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Christian Frederic Crusé (June 27, 1794 – October 5, 1865) was a minister of the Protestant Episcopal Church, born June 27, 1794, in Philadelphia, of Lutheran parentage. He entered the University of Pennsylvania in 1812, and graduated Jan. 10, 1815, with distinguished honors. He was appointed professor in the University in 1831, and resigned in 1833. He was a teacher for several years at Dr. Muhlenberg's celebrated boys' school on Long Island. He was ordained by bishop White about 1822; became rector of Trinity Parish, Fishkill, N.Y., in April, 1846, but resigned the cure in 1851, and afterwards had no parish. He soon after removed to the General Theological Seminary, where, as librarian, he had ample opportunities for those studies in which he was so successful. In the ancient languages — Syriac, Hebrew, and Greek — Dr. Cruse was very well informed. He translated and edited Eusebius's Church History, and his edition is the best in English. He died in New York October 5, 1865. — Church Review, January, 1866. References 1794 births 1865 deaths Clergy from Philadelphia American librarians
```c /* main.c - Application main entry point */ /* * */ #include <zephyr/kernel.h> #include <stddef.h> #include <zephyr/ztest.h> #include <zephyr/bluetooth/bluetooth.h> #include <zephyr/bluetooth/conn.h> #include <../subsys/bluetooth/host/smp.h> ZTEST_SUITE(test_smp, NULL, NULL, NULL, NULL, NULL); ZTEST(test_smp, test_bt_smp_err_to_str) { /* Test a couple of entries */ zassert_str_equal(bt_smp_err_to_str(0x00), "BT_SMP_ERR_SUCCESS"); zassert_str_equal(bt_smp_err_to_str(0x0a), "BT_SMP_ERR_INVALID_PARAMS"); zassert_str_equal(bt_smp_err_to_str(0x0F), "BT_SMP_ERR_KEY_REJECTED"); /* Test entries that are not used */ zassert_mem_equal(bt_smp_err_to_str(0x10), "(unknown)", strlen("(unknown)")); zassert_mem_equal(bt_smp_err_to_str(0xFF), "(unknown)", strlen("(unknown)")); for (uint16_t i = 0; i <= UINT8_MAX; i++) { zassert_not_null(bt_smp_err_to_str(i), ": %d", i); } } ZTEST(test_smp, test_bt_security_err_to_str) { /* Test a couple of entries */ zassert_str_equal(bt_security_err_to_str(BT_SECURITY_ERR_AUTH_FAIL), "BT_SECURITY_ERR_AUTH_FAIL"); zassert_str_equal(bt_security_err_to_str(BT_SECURITY_ERR_KEY_REJECTED), "BT_SECURITY_ERR_KEY_REJECTED"); zassert_str_equal(bt_security_err_to_str(BT_SECURITY_ERR_UNSPECIFIED), "BT_SECURITY_ERR_UNSPECIFIED"); /* Test outside range */ zassert_str_equal(bt_security_err_to_str(BT_SECURITY_ERR_UNSPECIFIED + 1), "(unknown)"); for (uint16_t i = 0; i <= UINT8_MAX; i++) { zassert_not_null(bt_security_err_to_str(i), ": %d", i); } } ```
```objective-c /* * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), * to deal in the Software without restriction, including without limitation * the rights to use, copy, modify, merge, publish, distribute, sublicense, * and/or sell copies of the Software, and to permit persons to whom the * Software is furnished to do so, subject to the following conditions: * * The above copyright notice and this permission notice shall be included * in all copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */ #ifndef _nbio_2_3_OFFSET_HEADER #define _nbio_2_3_OFFSET_HEADER // addressBlock: nbio_nbif0_bif_bx_pf_SYSPFVFDEC // base address: 0x0 #define mmBIF_BX_PF_MM_INDEX 0x0000 #define mmBIF_BX_PF_MM_INDEX_BASE_IDX 0 #define mmBIF_BX_PF_MM_DATA 0x0001 #define mmBIF_BX_PF_MM_DATA_BASE_IDX 0 #define mmBIF_BX_PF_MM_INDEX_HI 0x0006 #define mmBIF_BX_PF_MM_INDEX_HI_BASE_IDX 0 // addressBlock: nbio_nbif0_bif_bx_SYSDEC // base address: 0x0 #define mmSYSHUB_INDEX_OVLP 0x0008 #define mmSYSHUB_INDEX_OVLP_BASE_IDX 0 #define mmSYSHUB_DATA_OVLP 0x0009 #define mmSYSHUB_DATA_OVLP_BASE_IDX 0 #define mmPCIE_INDEX 0x000c #define mmPCIE_INDEX_BASE_IDX 0 #define mmPCIE_DATA 0x000d #define mmPCIE_DATA_BASE_IDX 0 #define mmPCIE_INDEX2 0x000e #define mmPCIE_INDEX2_BASE_IDX 0 #define mmPCIE_DATA2 0x000f #define mmPCIE_DATA2_BASE_IDX 0 #define mmSBIOS_SCRATCH_0 0x0034 #define mmSBIOS_SCRATCH_0_BASE_IDX 1 #define mmSBIOS_SCRATCH_1 0x0035 #define mmSBIOS_SCRATCH_1_BASE_IDX 1 #define mmSBIOS_SCRATCH_2 0x0036 #define mmSBIOS_SCRATCH_2_BASE_IDX 1 #define mmSBIOS_SCRATCH_3 0x0037 #define mmSBIOS_SCRATCH_3_BASE_IDX 1 #define mmBIOS_SCRATCH_0 0x0038 #define mmBIOS_SCRATCH_0_BASE_IDX 1 #define mmBIOS_SCRATCH_1 0x0039 #define mmBIOS_SCRATCH_1_BASE_IDX 1 #define mmBIOS_SCRATCH_2 0x003a #define mmBIOS_SCRATCH_2_BASE_IDX 1 #define mmBIOS_SCRATCH_3 0x003b #define mmBIOS_SCRATCH_3_BASE_IDX 1 #define mmBIOS_SCRATCH_4 0x003c #define mmBIOS_SCRATCH_4_BASE_IDX 1 #define mmBIOS_SCRATCH_5 0x003d #define mmBIOS_SCRATCH_5_BASE_IDX 1 #define mmBIOS_SCRATCH_6 0x003e #define mmBIOS_SCRATCH_6_BASE_IDX 1 #define mmBIOS_SCRATCH_7 0x003f #define mmBIOS_SCRATCH_7_BASE_IDX 1 #define mmBIOS_SCRATCH_8 0x0040 #define mmBIOS_SCRATCH_8_BASE_IDX 1 #define mmBIOS_SCRATCH_9 0x0041 #define mmBIOS_SCRATCH_9_BASE_IDX 1 #define mmBIOS_SCRATCH_10 0x0042 #define mmBIOS_SCRATCH_10_BASE_IDX 1 #define mmBIOS_SCRATCH_11 0x0043 #define mmBIOS_SCRATCH_11_BASE_IDX 1 #define mmBIOS_SCRATCH_12 0x0044 #define mmBIOS_SCRATCH_12_BASE_IDX 1 #define mmBIOS_SCRATCH_13 0x0045 #define mmBIOS_SCRATCH_13_BASE_IDX 1 #define mmBIOS_SCRATCH_14 0x0046 #define mmBIOS_SCRATCH_14_BASE_IDX 1 #define mmBIOS_SCRATCH_15 0x0047 #define mmBIOS_SCRATCH_15_BASE_IDX 1 #define mmBIF_RLC_INTR_CNTL 0x004c #define mmBIF_RLC_INTR_CNTL_BASE_IDX 1 #define mmBIF_VCE_INTR_CNTL 0x004d #define mmBIF_VCE_INTR_CNTL_BASE_IDX 1 #define mmBIF_UVD_INTR_CNTL 0x004e #define mmBIF_UVD_INTR_CNTL_BASE_IDX 1 #define mmGFX_MMIOREG_CAM_ADDR0 0x006c #define mmGFX_MMIOREG_CAM_ADDR0_BASE_IDX 1 #define mmGFX_MMIOREG_CAM_REMAP_ADDR0 0x006d #define mmGFX_MMIOREG_CAM_REMAP_ADDR0_BASE_IDX 1 #define mmGFX_MMIOREG_CAM_ADDR1 0x006e #define mmGFX_MMIOREG_CAM_ADDR1_BASE_IDX 1 #define mmGFX_MMIOREG_CAM_REMAP_ADDR1 0x006f #define mmGFX_MMIOREG_CAM_REMAP_ADDR1_BASE_IDX 1 #define mmGFX_MMIOREG_CAM_ADDR2 0x0070 #define mmGFX_MMIOREG_CAM_ADDR2_BASE_IDX 1 #define mmGFX_MMIOREG_CAM_REMAP_ADDR2 0x0071 #define mmGFX_MMIOREG_CAM_REMAP_ADDR2_BASE_IDX 1 #define mmGFX_MMIOREG_CAM_ADDR3 0x0072 #define mmGFX_MMIOREG_CAM_ADDR3_BASE_IDX 1 #define mmGFX_MMIOREG_CAM_REMAP_ADDR3 0x0073 #define mmGFX_MMIOREG_CAM_REMAP_ADDR3_BASE_IDX 1 #define mmGFX_MMIOREG_CAM_ADDR4 0x0074 #define mmGFX_MMIOREG_CAM_ADDR4_BASE_IDX 1 #define mmGFX_MMIOREG_CAM_REMAP_ADDR4 0x0075 #define mmGFX_MMIOREG_CAM_REMAP_ADDR4_BASE_IDX 1 #define mmGFX_MMIOREG_CAM_ADDR5 0x0076 #define mmGFX_MMIOREG_CAM_ADDR5_BASE_IDX 1 #define mmGFX_MMIOREG_CAM_REMAP_ADDR5 0x0077 #define mmGFX_MMIOREG_CAM_REMAP_ADDR5_BASE_IDX 1 #define mmGFX_MMIOREG_CAM_ADDR6 0x0078 #define mmGFX_MMIOREG_CAM_ADDR6_BASE_IDX 1 #define mmGFX_MMIOREG_CAM_REMAP_ADDR6 0x0079 #define mmGFX_MMIOREG_CAM_REMAP_ADDR6_BASE_IDX 1 #define mmGFX_MMIOREG_CAM_ADDR7 0x007a #define mmGFX_MMIOREG_CAM_ADDR7_BASE_IDX 1 #define mmGFX_MMIOREG_CAM_REMAP_ADDR7 0x007b #define mmGFX_MMIOREG_CAM_REMAP_ADDR7_BASE_IDX 1 #define mmGFX_MMIOREG_CAM_CNTL 0x007c #define mmGFX_MMIOREG_CAM_CNTL_BASE_IDX 1 #define mmGFX_MMIOREG_CAM_ZERO_CPL 0x007d #define mmGFX_MMIOREG_CAM_ZERO_CPL_BASE_IDX 1 #define mmGFX_MMIOREG_CAM_ONE_CPL 0x007e #define mmGFX_MMIOREG_CAM_ONE_CPL_BASE_IDX 1 #define mmGFX_MMIOREG_CAM_PROGRAMMABLE_CPL 0x007f #define mmGFX_MMIOREG_CAM_PROGRAMMABLE_CPL_BASE_IDX 1 // addressBlock: nbio_nbif0_syshub_mmreg_syshubdec // base address: 0x0 #define mmSYSHUB_INDEX 0x0008 #define mmSYSHUB_INDEX_BASE_IDX 0 #define mmSYSHUB_DATA 0x0009 #define mmSYSHUB_DATA_BASE_IDX 0 // addressBlock: nbio_nbif0_rcc_strap_BIFDEC1 // base address: 0x0 #define mmRCC_BIF_STRAP0 0x0000 #define mmRCC_BIF_STRAP0_BASE_IDX 2 #define mmRCC_BIF_STRAP1 0x0001 #define mmRCC_BIF_STRAP1_BASE_IDX 2 #define mmRCC_BIF_STRAP2 0x0002 #define mmRCC_BIF_STRAP2_BASE_IDX 2 #define mmRCC_BIF_STRAP3 0x0003 #define mmRCC_BIF_STRAP3_BASE_IDX 2 #define mmRCC_BIF_STRAP4 0x0004 #define mmRCC_BIF_STRAP4_BASE_IDX 2 #define mmRCC_BIF_STRAP5 0x0005 #define mmRCC_BIF_STRAP5_BASE_IDX 2 #define mmRCC_BIF_STRAP6 0x0006 #define mmRCC_BIF_STRAP6_BASE_IDX 2 #define mmRCC_DEV0_PORT_STRAP0 0x0007 #define mmRCC_DEV0_PORT_STRAP0_BASE_IDX 2 #define mmRCC_DEV0_PORT_STRAP1 0x0008 #define mmRCC_DEV0_PORT_STRAP1_BASE_IDX 2 #define mmRCC_DEV0_PORT_STRAP2 0x0009 #define mmRCC_DEV0_PORT_STRAP2_BASE_IDX 2 #define mmRCC_DEV0_PORT_STRAP3 0x000a #define mmRCC_DEV0_PORT_STRAP3_BASE_IDX 2 #define mmRCC_DEV0_PORT_STRAP4 0x000b #define mmRCC_DEV0_PORT_STRAP4_BASE_IDX 2 #define mmRCC_DEV0_PORT_STRAP5 0x000c #define mmRCC_DEV0_PORT_STRAP5_BASE_IDX 2 #define mmRCC_DEV0_PORT_STRAP6 0x000d #define mmRCC_DEV0_PORT_STRAP6_BASE_IDX 2 #define mmRCC_DEV0_PORT_STRAP7 0x000e #define mmRCC_DEV0_PORT_STRAP7_BASE_IDX 2 #define mmRCC_DEV0_PORT_STRAP8 0x000f #define mmRCC_DEV0_PORT_STRAP8_BASE_IDX 2 #define mmRCC_DEV0_PORT_STRAP9 0x0010 #define mmRCC_DEV0_PORT_STRAP9_BASE_IDX 2 #define mmRCC_DEV0_EPF0_STRAP0 0x0011 #define mmRCC_DEV0_EPF0_STRAP0_BASE_IDX 2 #define mmRCC_DEV0_EPF0_STRAP1 0x0012 #define mmRCC_DEV0_EPF0_STRAP1_BASE_IDX 2 #define mmRCC_DEV0_EPF0_STRAP13 0x0013 #define mmRCC_DEV0_EPF0_STRAP13_BASE_IDX 2 #define mmRCC_DEV0_EPF0_STRAP2 0x0014 #define mmRCC_DEV0_EPF0_STRAP2_BASE_IDX 2 #define mmRCC_DEV0_EPF0_STRAP3 0x0015 #define mmRCC_DEV0_EPF0_STRAP3_BASE_IDX 2 #define mmRCC_DEV0_EPF0_STRAP4 0x0016 #define mmRCC_DEV0_EPF0_STRAP4_BASE_IDX 2 #define mmRCC_DEV0_EPF0_STRAP5 0x0017 #define mmRCC_DEV0_EPF0_STRAP5_BASE_IDX 2 #define mmRCC_DEV0_EPF0_STRAP8 0x0018 #define mmRCC_DEV0_EPF0_STRAP8_BASE_IDX 2 #define mmRCC_DEV0_EPF0_STRAP9 0x0019 #define mmRCC_DEV0_EPF0_STRAP9_BASE_IDX 2 #define mmRCC_DEV0_EPF1_STRAP0 0x001a #define mmRCC_DEV0_EPF1_STRAP0_BASE_IDX 2 #define mmRCC_DEV0_EPF1_STRAP10 0x001b #define mmRCC_DEV0_EPF1_STRAP10_BASE_IDX 2 #define mmRCC_DEV0_EPF1_STRAP11 0x001c #define mmRCC_DEV0_EPF1_STRAP11_BASE_IDX 2 #define mmRCC_DEV0_EPF1_STRAP12 0x001d #define mmRCC_DEV0_EPF1_STRAP12_BASE_IDX 2 #define mmRCC_DEV0_EPF1_STRAP13 0x001e #define mmRCC_DEV0_EPF1_STRAP13_BASE_IDX 2 #define mmRCC_DEV0_EPF1_STRAP2 0x001f #define mmRCC_DEV0_EPF1_STRAP2_BASE_IDX 2 #define mmRCC_DEV0_EPF1_STRAP3 0x0020 #define mmRCC_DEV0_EPF1_STRAP3_BASE_IDX 2 #define mmRCC_DEV0_EPF1_STRAP4 0x0021 #define mmRCC_DEV0_EPF1_STRAP4_BASE_IDX 2 #define mmRCC_DEV0_EPF1_STRAP5 0x0022 #define mmRCC_DEV0_EPF1_STRAP5_BASE_IDX 2 #define mmRCC_DEV0_EPF1_STRAP6 0x0023 #define mmRCC_DEV0_EPF1_STRAP6_BASE_IDX 2 #define mmRCC_DEV0_EPF1_STRAP7 0x0024 #define mmRCC_DEV0_EPF1_STRAP7_BASE_IDX 2 // addressBlock: nbio_nbif0_rcc_ep_dev0_BIFDEC1 // base address: 0x0 #define mmEP_PCIE_SCRATCH 0x0025 #define mmEP_PCIE_SCRATCH_BASE_IDX 2 #define mmEP_PCIE_CNTL 0x0027 #define mmEP_PCIE_CNTL_BASE_IDX 2 #define mmEP_PCIE_INT_CNTL 0x0028 #define mmEP_PCIE_INT_CNTL_BASE_IDX 2 #define mmEP_PCIE_INT_STATUS 0x0029 #define mmEP_PCIE_INT_STATUS_BASE_IDX 2 #define mmEP_PCIE_RX_CNTL2 0x002a #define mmEP_PCIE_RX_CNTL2_BASE_IDX 2 #define mmEP_PCIE_BUS_CNTL 0x002b #define mmEP_PCIE_BUS_CNTL_BASE_IDX 2 #define mmEP_PCIE_CFG_CNTL 0x002c #define mmEP_PCIE_CFG_CNTL_BASE_IDX 2 #define mmEP_PCIE_TX_LTR_CNTL 0x002e #define mmEP_PCIE_TX_LTR_CNTL_BASE_IDX 2 #define mmPCIE_F1_DPA_SUBSTATE_PWR_ALLOC_0 0x002f #define mmPCIE_F1_DPA_SUBSTATE_PWR_ALLOC_0_BASE_IDX 2 #define mmPCIE_F1_DPA_SUBSTATE_PWR_ALLOC_1 0x002f #define mmPCIE_F1_DPA_SUBSTATE_PWR_ALLOC_1_BASE_IDX 2 #define mmPCIE_F1_DPA_SUBSTATE_PWR_ALLOC_2 0x002f #define mmPCIE_F1_DPA_SUBSTATE_PWR_ALLOC_2_BASE_IDX 2 #define mmPCIE_F1_DPA_SUBSTATE_PWR_ALLOC_3 0x002f #define mmPCIE_F1_DPA_SUBSTATE_PWR_ALLOC_3_BASE_IDX 2 #define mmPCIE_F1_DPA_SUBSTATE_PWR_ALLOC_4 0x0030 #define mmPCIE_F1_DPA_SUBSTATE_PWR_ALLOC_4_BASE_IDX 2 #define mmPCIE_F1_DPA_SUBSTATE_PWR_ALLOC_5 0x0030 #define mmPCIE_F1_DPA_SUBSTATE_PWR_ALLOC_5_BASE_IDX 2 #define mmPCIE_F1_DPA_SUBSTATE_PWR_ALLOC_6 0x0030 #define mmPCIE_F1_DPA_SUBSTATE_PWR_ALLOC_6_BASE_IDX 2 #define mmPCIE_F1_DPA_SUBSTATE_PWR_ALLOC_7 0x0030 #define mmPCIE_F1_DPA_SUBSTATE_PWR_ALLOC_7_BASE_IDX 2 #define mmEP_PCIE_STRAP_MISC 0x0031 #define mmEP_PCIE_STRAP_MISC_BASE_IDX 2 #define mmEP_PCIE_STRAP_MISC2 0x0032 #define mmEP_PCIE_STRAP_MISC2_BASE_IDX 2 #define mmEP_PCIE_F0_DPA_CAP 0x0034 #define mmEP_PCIE_F0_DPA_CAP_BASE_IDX 2 #define mmEP_PCIE_F0_DPA_LATENCY_INDICATOR 0x0035 #define mmEP_PCIE_F0_DPA_LATENCY_INDICATOR_BASE_IDX 2 #define mmEP_PCIE_F0_DPA_CNTL 0x0035 #define mmEP_PCIE_F0_DPA_CNTL_BASE_IDX 2 #define mmPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_0 0x0035 #define mmPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_0_BASE_IDX 2 #define mmPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_1 0x0036 #define mmPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_1_BASE_IDX 2 #define mmPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_2 0x0036 #define mmPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_2_BASE_IDX 2 #define mmPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_3 0x0036 #define mmPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_3_BASE_IDX 2 #define mmPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_4 0x0036 #define mmPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_4_BASE_IDX 2 #define mmPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_5 0x0037 #define mmPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_5_BASE_IDX 2 #define mmPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_6 0x0037 #define mmPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_6_BASE_IDX 2 #define mmPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_7 0x0037 #define mmPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_7_BASE_IDX 2 #define mmEP_PCIE_PME_CONTROL 0x0037 #define mmEP_PCIE_PME_CONTROL_BASE_IDX 2 #define mmEP_PCIEP_RESERVED 0x0038 #define mmEP_PCIEP_RESERVED_BASE_IDX 2 #define mmEP_PCIE_TX_CNTL 0x003a #define mmEP_PCIE_TX_CNTL_BASE_IDX 2 #define mmEP_PCIE_TX_REQUESTER_ID 0x003b #define mmEP_PCIE_TX_REQUESTER_ID_BASE_IDX 2 #define mmEP_PCIE_ERR_CNTL 0x003c #define mmEP_PCIE_ERR_CNTL_BASE_IDX 2 #define mmEP_PCIE_RX_CNTL 0x003d #define mmEP_PCIE_RX_CNTL_BASE_IDX 2 #define mmEP_PCIE_LC_SPEED_CNTL 0x003e #define mmEP_PCIE_LC_SPEED_CNTL_BASE_IDX 2 // addressBlock: nbio_nbif0_rcc_dwn_dev0_BIFDEC1 // base address: 0x0 #define mmDN_PCIE_RESERVED 0x0040 #define mmDN_PCIE_RESERVED_BASE_IDX 2 #define mmDN_PCIE_SCRATCH 0x0041 #define mmDN_PCIE_SCRATCH_BASE_IDX 2 #define mmDN_PCIE_CNTL 0x0043 #define mmDN_PCIE_CNTL_BASE_IDX 2 #define mmDN_PCIE_CONFIG_CNTL 0x0044 #define mmDN_PCIE_CONFIG_CNTL_BASE_IDX 2 #define mmDN_PCIE_RX_CNTL2 0x0045 #define mmDN_PCIE_RX_CNTL2_BASE_IDX 2 #define mmDN_PCIE_BUS_CNTL 0x0046 #define mmDN_PCIE_BUS_CNTL_BASE_IDX 2 #define mmDN_PCIE_CFG_CNTL 0x0047 #define mmDN_PCIE_CFG_CNTL_BASE_IDX 2 #define mmDN_PCIE_STRAP_F0 0x0048 #define mmDN_PCIE_STRAP_F0_BASE_IDX 2 #define mmDN_PCIE_STRAP_MISC 0x0049 #define mmDN_PCIE_STRAP_MISC_BASE_IDX 2 #define mmDN_PCIE_STRAP_MISC2 0x004a #define mmDN_PCIE_STRAP_MISC2_BASE_IDX 2 // addressBlock: nbio_nbif0_rcc_dwnp_dev0_BIFDEC1 // base address: 0x0 #define mmPCIE_ERR_CNTL 0x004f #define mmPCIE_ERR_CNTL_BASE_IDX 2 #define mmPCIE_RX_CNTL 0x0050 #define mmPCIE_RX_CNTL_BASE_IDX 2 #define mmPCIE_LC_SPEED_CNTL 0x0051 #define mmPCIE_LC_SPEED_CNTL_BASE_IDX 2 #define mmPCIE_LC_CNTL2 0x0052 #define mmPCIE_LC_CNTL2_BASE_IDX 2 #define mmPCIEP_STRAP_MISC 0x0053 #define mmPCIEP_STRAP_MISC_BASE_IDX 2 #define mmLTR_MSG_INFO_FROM_EP 0x0054 #define mmLTR_MSG_INFO_FROM_EP_BASE_IDX 2 // addressBlock: nbio_nbif0_rcc_dev0_epf0_BIFPFVFDEC1[13440..14975] // base address: 0x3480 #define mmRCC_DEV0_EPF0_RCC_ERR_LOG 0x0085 #define mmRCC_DEV0_EPF0_RCC_ERR_LOG_BASE_IDX 2 #define mmRCC_DEV0_EPF0_RCC_DOORBELL_APER_EN 0x00c0 #define mmRCC_DEV0_EPF0_RCC_DOORBELL_APER_EN_BASE_IDX 2 #define mmRCC_DEV0_EPF0_RCC_CONFIG_MEMSIZE 0x00c3 #define mmRCC_DEV0_EPF0_RCC_CONFIG_MEMSIZE_BASE_IDX 2 #define mmRCC_DEV0_EPF0_RCC_CONFIG_RESERVED 0x00c4 #define mmRCC_DEV0_EPF0_RCC_CONFIG_RESERVED_BASE_IDX 2 #define mmRCC_DEV0_EPF0_RCC_IOV_FUNC_IDENTIFIER 0x00c5 #define mmRCC_DEV0_EPF0_RCC_IOV_FUNC_IDENTIFIER_BASE_IDX 2 // addressBlock: nbio_nbif0_rcc_dev0_BIFDEC1 // base address: 0x0 #define mmRCC_ERR_INT_CNTL 0x0086 #define mmRCC_ERR_INT_CNTL_BASE_IDX 2 #define mmRCC_BACO_CNTL_MISC 0x0087 #define mmRCC_BACO_CNTL_MISC_BASE_IDX 2 #define mmRCC_RESET_EN 0x0088 #define mmRCC_RESET_EN_BASE_IDX 2 #define mmRCC_VDM_SUPPORT 0x0089 #define mmRCC_VDM_SUPPORT_BASE_IDX 2 #define mmRCC_MARGIN_PARAM_CNTL0 0x008a #define mmRCC_MARGIN_PARAM_CNTL0_BASE_IDX 2 #define mmRCC_MARGIN_PARAM_CNTL1 0x008b #define mmRCC_MARGIN_PARAM_CNTL1_BASE_IDX 2 #define mmRCC_GPUIOV_REGION 0x008c #define mmRCC_GPUIOV_REGION_BASE_IDX 2 #define mmRCC_PEER_REG_RANGE0 0x00be #define mmRCC_PEER_REG_RANGE0_BASE_IDX 2 #define mmRCC_PEER_REG_RANGE1 0x00bf #define mmRCC_PEER_REG_RANGE1_BASE_IDX 2 #define mmRCC_BUS_CNTL 0x00c1 #define mmRCC_BUS_CNTL_BASE_IDX 2 #define mmRCC_CONFIG_CNTL 0x00c2 #define mmRCC_CONFIG_CNTL_BASE_IDX 2 #define mmRCC_CONFIG_F0_BASE 0x00c6 #define mmRCC_CONFIG_F0_BASE_BASE_IDX 2 #define mmRCC_CONFIG_APER_SIZE 0x00c7 #define mmRCC_CONFIG_APER_SIZE_BASE_IDX 2 #define mmRCC_CONFIG_REG_APER_SIZE 0x00c8 #define mmRCC_CONFIG_REG_APER_SIZE_BASE_IDX 2 #define mmRCC_XDMA_LO 0x00c9 #define mmRCC_XDMA_LO_BASE_IDX 2 #define mmRCC_XDMA_HI 0x00ca #define mmRCC_XDMA_HI_BASE_IDX 2 #define mmRCC_FEATURES_CONTROL_MISC 0x00cb #define mmRCC_FEATURES_CONTROL_MISC_BASE_IDX 2 #define mmRCC_BUSNUM_CNTL1 0x00cc #define mmRCC_BUSNUM_CNTL1_BASE_IDX 2 #define mmRCC_BUSNUM_LIST0 0x00cd #define mmRCC_BUSNUM_LIST0_BASE_IDX 2 #define mmRCC_BUSNUM_LIST1 0x00ce #define mmRCC_BUSNUM_LIST1_BASE_IDX 2 #define mmRCC_BUSNUM_CNTL2 0x00cf #define mmRCC_BUSNUM_CNTL2_BASE_IDX 2 #define mmRCC_CAPTURE_HOST_BUSNUM 0x00d0 #define mmRCC_CAPTURE_HOST_BUSNUM_BASE_IDX 2 #define mmRCC_HOST_BUSNUM 0x00d1 #define mmRCC_HOST_BUSNUM_BASE_IDX 2 #define mmRCC_PEER0_FB_OFFSET_HI 0x00d2 #define mmRCC_PEER0_FB_OFFSET_HI_BASE_IDX 2 #define mmRCC_PEER0_FB_OFFSET_LO 0x00d3 #define mmRCC_PEER0_FB_OFFSET_LO_BASE_IDX 2 #define mmRCC_PEER1_FB_OFFSET_HI 0x00d4 #define mmRCC_PEER1_FB_OFFSET_HI_BASE_IDX 2 #define mmRCC_PEER1_FB_OFFSET_LO 0x00d5 #define mmRCC_PEER1_FB_OFFSET_LO_BASE_IDX 2 #define mmRCC_PEER2_FB_OFFSET_HI 0x00d6 #define mmRCC_PEER2_FB_OFFSET_HI_BASE_IDX 2 #define mmRCC_PEER2_FB_OFFSET_LO 0x00d7 #define mmRCC_PEER2_FB_OFFSET_LO_BASE_IDX 2 #define mmRCC_PEER3_FB_OFFSET_HI 0x00d8 #define mmRCC_PEER3_FB_OFFSET_HI_BASE_IDX 2 #define mmRCC_PEER3_FB_OFFSET_LO 0x00d9 #define mmRCC_PEER3_FB_OFFSET_LO_BASE_IDX 2 #define mmRCC_DEVFUNCNUM_LIST0 0x00da #define mmRCC_DEVFUNCNUM_LIST0_BASE_IDX 2 #define mmRCC_DEVFUNCNUM_LIST1 0x00db #define mmRCC_DEVFUNCNUM_LIST1_BASE_IDX 2 #define mmRCC_DEV0_LINK_CNTL 0x00dd #define mmRCC_DEV0_LINK_CNTL_BASE_IDX 2 #define mmRCC_CMN_LINK_CNTL 0x00de #define mmRCC_CMN_LINK_CNTL_BASE_IDX 2 #define mmRCC_EP_REQUESTERID_RESTORE 0x00df #define mmRCC_EP_REQUESTERID_RESTORE_BASE_IDX 2 #define mmRCC_LTR_LSWITCH_CNTL 0x00e0 #define mmRCC_LTR_LSWITCH_CNTL_BASE_IDX 2 #define mmRCC_MH_ARB_CNTL 0x00e1 #define mmRCC_MH_ARB_CNTL_BASE_IDX 2 // addressBlock: nbio_nbif0_bif_bx_BIFDEC1 // base address: 0x0 #define mmCC_BIF_BX_STRAP0 0x00e2 #define mmCC_BIF_BX_STRAP0_BASE_IDX 2 #define mmCC_BIF_BX_PINSTRAP0 0x00e4 #define mmCC_BIF_BX_PINSTRAP0_BASE_IDX 2 #define mmBIF_MM_INDACCESS_CNTL 0x00e6 #define mmBIF_MM_INDACCESS_CNTL_BASE_IDX 2 #define mmBUS_CNTL 0x00e7 #define mmBUS_CNTL_BASE_IDX 2 #define mmBIF_SCRATCH0 0x00e8 #define mmBIF_SCRATCH0_BASE_IDX 2 #define mmBIF_SCRATCH1 0x00e9 #define mmBIF_SCRATCH1_BASE_IDX 2 #define mmBX_RESET_EN 0x00ed #define mmBX_RESET_EN_BASE_IDX 2 #define mmMM_CFGREGS_CNTL 0x00ee #define mmMM_CFGREGS_CNTL_BASE_IDX 2 #define mmBX_RESET_CNTL 0x00f0 #define mmBX_RESET_CNTL_BASE_IDX 2 #define mmINTERRUPT_CNTL 0x00f1 #define mmINTERRUPT_CNTL_BASE_IDX 2 #define mmINTERRUPT_CNTL2 0x00f2 #define mmINTERRUPT_CNTL2_BASE_IDX 2 #define mmCLKREQB_PAD_CNTL 0x00f8 #define mmCLKREQB_PAD_CNTL_BASE_IDX 2 #define mmBIF_FEATURES_CONTROL_MISC 0x00fb #define mmBIF_FEATURES_CONTROL_MISC_BASE_IDX 2 #define mmBIF_DOORBELL_CNTL 0x00fc #define mmBIF_DOORBELL_CNTL_BASE_IDX 2 #define mmBIF_DOORBELL_INT_CNTL 0x00fd #define mmBIF_DOORBELL_INT_CNTL_BASE_IDX 2 #define mmBIF_FB_EN 0x00ff #define mmBIF_FB_EN_BASE_IDX 2 #define mmBIF_INTR_CNTL 0x0100 #define mmBIF_INTR_CNTL_BASE_IDX 2 #define mmBIF_MST_TRANS_PENDING_VF 0x0109 #define mmBIF_MST_TRANS_PENDING_VF_BASE_IDX 2 #define mmBIF_SLV_TRANS_PENDING_VF 0x010a #define mmBIF_SLV_TRANS_PENDING_VF_BASE_IDX 2 #define mmBACO_CNTL 0x010b #define mmBACO_CNTL_BASE_IDX 2 #define mmBIF_BACO_EXIT_TIME0 0x010c #define mmBIF_BACO_EXIT_TIME0_BASE_IDX 2 #define mmBIF_BACO_EXIT_TIMER1 0x010d #define mmBIF_BACO_EXIT_TIMER1_BASE_IDX 2 #define mmBIF_BACO_EXIT_TIMER2 0x010e #define mmBIF_BACO_EXIT_TIMER2_BASE_IDX 2 #define mmBIF_BACO_EXIT_TIMER3 0x010f #define mmBIF_BACO_EXIT_TIMER3_BASE_IDX 2 #define mmBIF_BACO_EXIT_TIMER4 0x0110 #define mmBIF_BACO_EXIT_TIMER4_BASE_IDX 2 #define mmMEM_TYPE_CNTL 0x0111 #define mmMEM_TYPE_CNTL_BASE_IDX 2 #define mmNBIF_GFX_ADDR_LUT_CNTL 0x0113 #define mmNBIF_GFX_ADDR_LUT_CNTL_BASE_IDX 2 #define mmNBIF_GFX_ADDR_LUT_0 0x0114 #define mmNBIF_GFX_ADDR_LUT_0_BASE_IDX 2 #define mmNBIF_GFX_ADDR_LUT_1 0x0115 #define mmNBIF_GFX_ADDR_LUT_1_BASE_IDX 2 #define mmNBIF_GFX_ADDR_LUT_2 0x0116 #define mmNBIF_GFX_ADDR_LUT_2_BASE_IDX 2 #define mmNBIF_GFX_ADDR_LUT_3 0x0117 #define mmNBIF_GFX_ADDR_LUT_3_BASE_IDX 2 #define mmNBIF_GFX_ADDR_LUT_4 0x0118 #define mmNBIF_GFX_ADDR_LUT_4_BASE_IDX 2 #define mmNBIF_GFX_ADDR_LUT_5 0x0119 #define mmNBIF_GFX_ADDR_LUT_5_BASE_IDX 2 #define mmNBIF_GFX_ADDR_LUT_6 0x011a #define mmNBIF_GFX_ADDR_LUT_6_BASE_IDX 2 #define mmNBIF_GFX_ADDR_LUT_7 0x011b #define mmNBIF_GFX_ADDR_LUT_7_BASE_IDX 2 #define mmNBIF_GFX_ADDR_LUT_8 0x011c #define mmNBIF_GFX_ADDR_LUT_8_BASE_IDX 2 #define mmNBIF_GFX_ADDR_LUT_9 0x011d #define mmNBIF_GFX_ADDR_LUT_9_BASE_IDX 2 #define mmNBIF_GFX_ADDR_LUT_10 0x011e #define mmNBIF_GFX_ADDR_LUT_10_BASE_IDX 2 #define mmNBIF_GFX_ADDR_LUT_11 0x011f #define mmNBIF_GFX_ADDR_LUT_11_BASE_IDX 2 #define mmNBIF_GFX_ADDR_LUT_12 0x0120 #define mmNBIF_GFX_ADDR_LUT_12_BASE_IDX 2 #define mmNBIF_GFX_ADDR_LUT_13 0x0121 #define mmNBIF_GFX_ADDR_LUT_13_BASE_IDX 2 #define mmNBIF_GFX_ADDR_LUT_14 0x0122 #define mmNBIF_GFX_ADDR_LUT_14_BASE_IDX 2 #define mmNBIF_GFX_ADDR_LUT_15 0x0123 #define mmNBIF_GFX_ADDR_LUT_15_BASE_IDX 2 #define mmREMAP_HDP_MEM_FLUSH_CNTL 0x012d #define mmREMAP_HDP_MEM_FLUSH_CNTL_BASE_IDX 2 #define mmREMAP_HDP_REG_FLUSH_CNTL 0x012e #define mmREMAP_HDP_REG_FLUSH_CNTL_BASE_IDX 2 #define mmBIF_RB_CNTL 0x012f #define mmBIF_RB_CNTL_BASE_IDX 2 #define mmBIF_RB_BASE 0x0130 #define mmBIF_RB_BASE_BASE_IDX 2 #define mmBIF_RB_RPTR 0x0131 #define mmBIF_RB_RPTR_BASE_IDX 2 #define mmBIF_RB_WPTR 0x0132 #define mmBIF_RB_WPTR_BASE_IDX 2 #define mmBIF_RB_WPTR_ADDR_HI 0x0133 #define mmBIF_RB_WPTR_ADDR_HI_BASE_IDX 2 #define mmBIF_RB_WPTR_ADDR_LO 0x0134 #define mmBIF_RB_WPTR_ADDR_LO_BASE_IDX 2 #define mmMAILBOX_INDEX 0x0135 #define mmMAILBOX_INDEX_BASE_IDX 2 #define mmBIF_MP1_INTR_CTRL 0x0142 #define mmBIF_MP1_INTR_CTRL_BASE_IDX 2 #define mmBIF_UVD_GPUIOV_CFG_SIZE 0x0143 #define mmBIF_UVD_GPUIOV_CFG_SIZE_BASE_IDX 2 #define mmBIF_VCE_GPUIOV_CFG_SIZE 0x0144 #define mmBIF_VCE_GPUIOV_CFG_SIZE_BASE_IDX 2 #define mmBIF_GFX_SDMA_GPUIOV_CFG_SIZE 0x0145 #define mmBIF_GFX_SDMA_GPUIOV_CFG_SIZE_BASE_IDX 2 #define mmBIF_PERSTB_PAD_CNTL 0x0148 #define mmBIF_PERSTB_PAD_CNTL_BASE_IDX 2 #define mmBIF_PX_EN_PAD_CNTL 0x0149 #define mmBIF_PX_EN_PAD_CNTL_BASE_IDX 2 #define mmBIF_REFPADKIN_PAD_CNTL 0x014a #define mmBIF_REFPADKIN_PAD_CNTL_BASE_IDX 2 #define mmBIF_CLKREQB_PAD_CNTL 0x014b #define mmBIF_CLKREQB_PAD_CNTL_BASE_IDX 2 #define mmBIF_PWRBRK_PAD_CNTL 0x014c #define mmBIF_PWRBRK_PAD_CNTL_BASE_IDX 2 #define mmBIF_WAKEB_PAD_CNTL 0x014d #define mmBIF_WAKEB_PAD_CNTL_BASE_IDX 2 #define mmBIF_VAUX_PRESENT_PAD_CNTL 0x014e #define mmBIF_VAUX_PRESENT_PAD_CNTL_BASE_IDX 2 // addressBlock: nbio_nbif0_bif_bx_pf_BIFPFVFDEC1 // base address: 0x0 #define mmBIF_BX_PF_BIF_BME_STATUS 0x00eb #define mmBIF_BX_PF_BIF_BME_STATUS_BASE_IDX 2 #define mmBIF_BX_PF_BIF_ATOMIC_ERR_LOG 0x00ec #define mmBIF_BX_PF_BIF_ATOMIC_ERR_LOG_BASE_IDX 2 #define mmBIF_BX_PF_DOORBELL_SELFRING_GPA_APER_BASE_HIGH 0x00f3 #define mmBIF_BX_PF_DOORBELL_SELFRING_GPA_APER_BASE_HIGH_BASE_IDX 2 #define mmBIF_BX_PF_DOORBELL_SELFRING_GPA_APER_BASE_LOW 0x00f4 #define mmBIF_BX_PF_DOORBELL_SELFRING_GPA_APER_BASE_LOW_BASE_IDX 2 #define mmBIF_BX_PF_DOORBELL_SELFRING_GPA_APER_CNTL 0x00f5 #define mmBIF_BX_PF_DOORBELL_SELFRING_GPA_APER_CNTL_BASE_IDX 2 #define mmBIF_BX_PF_HDP_REG_COHERENCY_FLUSH_CNTL 0x00f6 #define mmBIF_BX_PF_HDP_REG_COHERENCY_FLUSH_CNTL_BASE_IDX 2 #define mmBIF_BX_PF_HDP_MEM_COHERENCY_FLUSH_CNTL 0x00f7 #define mmBIF_BX_PF_HDP_MEM_COHERENCY_FLUSH_CNTL_BASE_IDX 2 #define mmBIF_BX_PF_GPU_HDP_FLUSH_REQ 0x0106 #define mmBIF_BX_PF_GPU_HDP_FLUSH_REQ_BASE_IDX 2 #define mmBIF_BX_PF_GPU_HDP_FLUSH_DONE 0x0107 #define mmBIF_BX_PF_GPU_HDP_FLUSH_DONE_BASE_IDX 2 #define mmBIF_BX_PF_BIF_TRANS_PENDING 0x0108 #define mmBIF_BX_PF_BIF_TRANS_PENDING_BASE_IDX 2 #define mmBIF_BX_PF_NBIF_GFX_ADDR_LUT_BYPASS 0x0112 #define mmBIF_BX_PF_NBIF_GFX_ADDR_LUT_BYPASS_BASE_IDX 2 #define mmBIF_BX_PF_MAILBOX_MSGBUF_TRN_DW0 0x0136 #define mmBIF_BX_PF_MAILBOX_MSGBUF_TRN_DW0_BASE_IDX 2 #define mmBIF_BX_PF_MAILBOX_MSGBUF_TRN_DW1 0x0137 #define mmBIF_BX_PF_MAILBOX_MSGBUF_TRN_DW1_BASE_IDX 2 #define mmBIF_BX_PF_MAILBOX_MSGBUF_TRN_DW2 0x0138 #define mmBIF_BX_PF_MAILBOX_MSGBUF_TRN_DW2_BASE_IDX 2 #define mmBIF_BX_PF_MAILBOX_MSGBUF_TRN_DW3 0x0139 #define mmBIF_BX_PF_MAILBOX_MSGBUF_TRN_DW3_BASE_IDX 2 #define mmBIF_BX_PF_MAILBOX_MSGBUF_RCV_DW0 0x013a #define mmBIF_BX_PF_MAILBOX_MSGBUF_RCV_DW0_BASE_IDX 2 #define mmBIF_BX_PF_MAILBOX_MSGBUF_RCV_DW1 0x013b #define mmBIF_BX_PF_MAILBOX_MSGBUF_RCV_DW1_BASE_IDX 2 #define mmBIF_BX_PF_MAILBOX_MSGBUF_RCV_DW2 0x013c #define mmBIF_BX_PF_MAILBOX_MSGBUF_RCV_DW2_BASE_IDX 2 #define mmBIF_BX_PF_MAILBOX_MSGBUF_RCV_DW3 0x013d #define mmBIF_BX_PF_MAILBOX_MSGBUF_RCV_DW3_BASE_IDX 2 #define mmBIF_BX_PF_MAILBOX_CONTROL 0x013e #define mmBIF_BX_PF_MAILBOX_CONTROL_BASE_IDX 2 #define mmBIF_BX_PF_MAILBOX_INT_CNTL 0x013f #define mmBIF_BX_PF_MAILBOX_INT_CNTL_BASE_IDX 2 #define mmBIF_BX_PF_BIF_VMHV_MAILBOX 0x0140 #define mmBIF_BX_PF_BIF_VMHV_MAILBOX_BASE_IDX 2 // addressBlock: nbio_nbif0_gdc_GDCDEC // base address: 0x0 #define mmA2S_CNTL_CL0 0x0190 #define mmA2S_CNTL_CL0_BASE_IDX 2 #define mmA2S_CNTL_CL1 0x0191 #define mmA2S_CNTL_CL1_BASE_IDX 2 #define mmA2S_CNTL3_CL0 0x01a0 #define mmA2S_CNTL3_CL0_BASE_IDX 2 #define mmA2S_CNTL3_CL1 0x01a1 #define mmA2S_CNTL3_CL1_BASE_IDX 2 #define mmA2S_CNTL_SW0 0x01b0 #define mmA2S_CNTL_SW0_BASE_IDX 2 #define mmA2S_CNTL_SW1 0x01b1 #define mmA2S_CNTL_SW1_BASE_IDX 2 #define mmA2S_CNTL_SW2 0x01b2 #define mmA2S_CNTL_SW2_BASE_IDX 2 #define mmA2S_CPLBUF_ALLOC_CNTL 0x01bc #define mmA2S_CPLBUF_ALLOC_CNTL_BASE_IDX 2 #define mmA2S_TAG_ALLOC_0 0x01bd #define mmA2S_TAG_ALLOC_0_BASE_IDX 2 #define mmA2S_TAG_ALLOC_1 0x01be #define mmA2S_TAG_ALLOC_1_BASE_IDX 2 #define mmA2S_MISC_CNTL 0x01c1 #define mmA2S_MISC_CNTL_BASE_IDX 2 #define mmNGDC_SDP_PORT_CTRL 0x01c2 #define mmNGDC_SDP_PORT_CTRL_BASE_IDX 2 #define mmSHUB_REGS_IF_CTL 0x01c3 #define mmSHUB_REGS_IF_CTL_BASE_IDX 2 #define mmNGDC_MGCG_CTRL 0x01ca #define mmNGDC_MGCG_CTRL_BASE_IDX 2 #define mmNGDC_RESERVED_0 0x01cb #define mmNGDC_RESERVED_0_BASE_IDX 2 #define mmNGDC_RESERVED_1 0x01cc #define mmNGDC_RESERVED_1_BASE_IDX 2 #define mmNGDC_SDP_PORT_CTRL_SOCCLK 0x01cd #define mmNGDC_SDP_PORT_CTRL_SOCCLK_BASE_IDX 2 #define mmBIF_SDMA0_DOORBELL_RANGE 0x01d0 #define mmBIF_SDMA0_DOORBELL_RANGE_BASE_IDX 2 #define mmBIF_SDMA1_DOORBELL_RANGE 0x01d1 #define mmBIF_SDMA1_DOORBELL_RANGE_BASE_IDX 2 #define mmBIF_IH_DOORBELL_RANGE 0x01d2 #define mmBIF_IH_DOORBELL_RANGE_BASE_IDX 2 #define mmBIF_MMSCH0_DOORBELL_RANGE 0x01d3 #define mmBIF_MMSCH0_DOORBELL_RANGE_BASE_IDX 2 #define mmBIF_ACV_DOORBELL_RANGE 0x01d4 #define mmBIF_ACV_DOORBELL_RANGE_BASE_IDX 2 #define mmBIF_DOORBELL_FENCE_CNTL 0x01de #define mmBIF_DOORBELL_FENCE_CNTL_BASE_IDX 2 #define mmS2A_MISC_CNTL 0x01df #define mmS2A_MISC_CNTL_BASE_IDX 2 #define mmNGDC_PG_MISC_CTRL 0x01f0 #define mmNGDC_PG_MISC_CTRL_BASE_IDX 2 #define mmNGDC_PGMST_CTRL 0x01f1 #define mmNGDC_PGMST_CTRL_BASE_IDX 2 #define mmNGDC_PGSLV_CTRL 0x01f2 #define mmNGDC_PGSLV_CTRL_BASE_IDX 2 // addressBlock: nbio_nbif0_rcc_dev0_epf0_BIFDEC2 // base address: 0x0 #define mmRCC_DEV0_EPF0_GFXMSIX_VECT0_ADDR_LO 0x0400 #define mmRCC_DEV0_EPF0_GFXMSIX_VECT0_ADDR_LO_BASE_IDX 3 #define mmRCC_DEV0_EPF0_GFXMSIX_VECT0_ADDR_HI 0x0401 #define mmRCC_DEV0_EPF0_GFXMSIX_VECT0_ADDR_HI_BASE_IDX 3 #define mmRCC_DEV0_EPF0_GFXMSIX_VECT0_MSG_DATA 0x0402 #define mmRCC_DEV0_EPF0_GFXMSIX_VECT0_MSG_DATA_BASE_IDX 3 #define mmRCC_DEV0_EPF0_GFXMSIX_VECT0_CONTROL 0x0403 #define mmRCC_DEV0_EPF0_GFXMSIX_VECT0_CONTROL_BASE_IDX 3 #define mmRCC_DEV0_EPF0_GFXMSIX_VECT1_ADDR_LO 0x0404 #define mmRCC_DEV0_EPF0_GFXMSIX_VECT1_ADDR_LO_BASE_IDX 3 #define mmRCC_DEV0_EPF0_GFXMSIX_VECT1_ADDR_HI 0x0405 #define mmRCC_DEV0_EPF0_GFXMSIX_VECT1_ADDR_HI_BASE_IDX 3 #define mmRCC_DEV0_EPF0_GFXMSIX_VECT1_MSG_DATA 0x0406 #define mmRCC_DEV0_EPF0_GFXMSIX_VECT1_MSG_DATA_BASE_IDX 3 #define mmRCC_DEV0_EPF0_GFXMSIX_VECT1_CONTROL 0x0407 #define mmRCC_DEV0_EPF0_GFXMSIX_VECT1_CONTROL_BASE_IDX 3 #define mmRCC_DEV0_EPF0_GFXMSIX_VECT2_ADDR_LO 0x0408 #define mmRCC_DEV0_EPF0_GFXMSIX_VECT2_ADDR_LO_BASE_IDX 3 #define mmRCC_DEV0_EPF0_GFXMSIX_VECT2_ADDR_HI 0x0409 #define mmRCC_DEV0_EPF0_GFXMSIX_VECT2_ADDR_HI_BASE_IDX 3 #define mmRCC_DEV0_EPF0_GFXMSIX_VECT2_MSG_DATA 0x040a #define mmRCC_DEV0_EPF0_GFXMSIX_VECT2_MSG_DATA_BASE_IDX 3 #define mmRCC_DEV0_EPF0_GFXMSIX_VECT2_CONTROL 0x040b #define mmRCC_DEV0_EPF0_GFXMSIX_VECT2_CONTROL_BASE_IDX 3 #define mmRCC_DEV0_EPF0_GFXMSIX_VECT3_ADDR_LO 0x040c #define mmRCC_DEV0_EPF0_GFXMSIX_VECT3_ADDR_LO_BASE_IDX 3 #define mmRCC_DEV0_EPF0_GFXMSIX_VECT3_ADDR_HI 0x040d #define mmRCC_DEV0_EPF0_GFXMSIX_VECT3_ADDR_HI_BASE_IDX 3 #define mmRCC_DEV0_EPF0_GFXMSIX_VECT3_MSG_DATA 0x040e #define mmRCC_DEV0_EPF0_GFXMSIX_VECT3_MSG_DATA_BASE_IDX 3 #define mmRCC_DEV0_EPF0_GFXMSIX_VECT3_CONTROL 0x040f #define mmRCC_DEV0_EPF0_GFXMSIX_VECT3_CONTROL_BASE_IDX 3 #define mmRCC_DEV0_EPF0_GFXMSIX_PBA 0x0800 #define mmRCC_DEV0_EPF0_GFXMSIX_PBA_BASE_IDX 3 // addressBlock: nbio_pcie0_pswuscfg0_cfgdecp // base address: 0x0 #define cfgPSWUSCFG0_0_VENDOR_ID 0x0000 #define cfgPSWUSCFG0_0_DEVICE_ID 0x0002 #define cfgPSWUSCFG0_0_COMMAND 0x0004 #define cfgPSWUSCFG0_0_STATUS 0x0006 #define cfgPSWUSCFG0_0_REVISION_ID 0x0008 #define cfgPSWUSCFG0_0_PROG_INTERFACE 0x0009 #define cfgPSWUSCFG0_0_SUB_CLASS 0x000a #define cfgPSWUSCFG0_0_BASE_CLASS 0x000b #define cfgPSWUSCFG0_0_CACHE_LINE 0x000c #define cfgPSWUSCFG0_0_LATENCY 0x000d #define cfgPSWUSCFG0_0_HEADER 0x000e #define cfgPSWUSCFG0_0_BIST 0x000f #define cfgPSWUSCFG0_0_SUB_BUS_NUMBER_LATENCY 0x0018 #define cfgPSWUSCFG0_0_IO_BASE_LIMIT 0x001c #define cfgPSWUSCFG0_0_SECONDARY_STATUS 0x001e #define cfgPSWUSCFG0_0_MEM_BASE_LIMIT 0x0020 #define cfgPSWUSCFG0_0_PREF_BASE_LIMIT 0x0024 #define cfgPSWUSCFG0_0_PREF_BASE_UPPER 0x0028 #define cfgPSWUSCFG0_0_PREF_LIMIT_UPPER 0x002c #define cfgPSWUSCFG0_0_IO_BASE_LIMIT_HI 0x0030 #define cfgPSWUSCFG0_0_CAP_PTR 0x0034 #define cfgPSWUSCFG0_0_ROM_BASE_ADDR 0x0038 #define cfgPSWUSCFG0_0_INTERRUPT_LINE 0x003c #define cfgPSWUSCFG0_0_INTERRUPT_PIN 0x003d #define cfgPSWUSCFG0_0_IRQ_BRIDGE_CNTL 0x003e #define cfgPSWUSCFG0_0_EXT_BRIDGE_CNTL 0x0040 #define cfgPSWUSCFG0_0_VENDOR_CAP_LIST 0x0048 #define cfgPSWUSCFG0_0_ADAPTER_ID_W 0x004c #define cfgPSWUSCFG0_0_PMI_CAP_LIST 0x0050 #define cfgPSWUSCFG0_0_PMI_CAP 0x0052 #define cfgPSWUSCFG0_0_PMI_STATUS_CNTL 0x0054 #define cfgPSWUSCFG0_0_PCIE_CAP_LIST 0x0058 #define cfgPSWUSCFG0_0_PCIE_CAP 0x005a #define cfgPSWUSCFG0_0_DEVICE_CAP 0x005c #define cfgPSWUSCFG0_0_DEVICE_CNTL 0x0060 #define cfgPSWUSCFG0_0_DEVICE_STATUS 0x0062 #define cfgPSWUSCFG0_0_LINK_CAP 0x0064 #define cfgPSWUSCFG0_0_LINK_CNTL 0x0068 #define cfgPSWUSCFG0_0_LINK_STATUS 0x006a #define cfgPSWUSCFG0_0_DEVICE_CAP2 0x007c #define cfgPSWUSCFG0_0_DEVICE_CNTL2 0x0080 #define cfgPSWUSCFG0_0_DEVICE_STATUS2 0x0082 #define cfgPSWUSCFG0_0_LINK_CAP2 0x0084 #define cfgPSWUSCFG0_0_LINK_CNTL2 0x0088 #define cfgPSWUSCFG0_0_LINK_STATUS2 0x008a #define cfgPSWUSCFG0_0_MSI_CAP_LIST 0x00a0 #define cfgPSWUSCFG0_0_MSI_MSG_CNTL 0x00a2 #define cfgPSWUSCFG0_0_MSI_MSG_ADDR_LO 0x00a4 #define cfgPSWUSCFG0_0_MSI_MSG_ADDR_HI 0x00a8 #define cfgPSWUSCFG0_0_MSI_MSG_DATA 0x00a8 #define cfgPSWUSCFG0_0_MSI_MSG_DATA_64 0x00ac #define cfgPSWUSCFG0_0_SSID_CAP_LIST 0x00c0 #define cfgPSWUSCFG0_0_SSID_CAP 0x00c4 #define cfgPSWUSCFG0_0_MSI_MAP_CAP_LIST 0x00c8 #define cfgPSWUSCFG0_0_MSI_MAP_CAP 0x00ca #define cfgPSWUSCFG0_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x0100 #define cfgPSWUSCFG0_0_PCIE_VENDOR_SPECIFIC_HDR 0x0104 #define cfgPSWUSCFG0_0_PCIE_VENDOR_SPECIFIC1 0x0108 #define cfgPSWUSCFG0_0_PCIE_VENDOR_SPECIFIC2 0x010c #define cfgPSWUSCFG0_0_PCIE_VC_ENH_CAP_LIST 0x0110 #define cfgPSWUSCFG0_0_PCIE_PORT_VC_CAP_REG1 0x0114 #define cfgPSWUSCFG0_0_PCIE_PORT_VC_CAP_REG2 0x0118 #define cfgPSWUSCFG0_0_PCIE_PORT_VC_CNTL 0x011c #define cfgPSWUSCFG0_0_PCIE_PORT_VC_STATUS 0x011e #define cfgPSWUSCFG0_0_PCIE_VC0_RESOURCE_CAP 0x0120 #define cfgPSWUSCFG0_0_PCIE_VC0_RESOURCE_CNTL 0x0124 #define cfgPSWUSCFG0_0_PCIE_VC0_RESOURCE_STATUS 0x012a #define cfgPSWUSCFG0_0_PCIE_VC1_RESOURCE_CAP 0x012c #define cfgPSWUSCFG0_0_PCIE_VC1_RESOURCE_CNTL 0x0130 #define cfgPSWUSCFG0_0_PCIE_VC1_RESOURCE_STATUS 0x0136 #define cfgPSWUSCFG0_0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST 0x0140 #define cfgPSWUSCFG0_0_PCIE_DEV_SERIAL_NUM_DW1 0x0144 #define cfgPSWUSCFG0_0_PCIE_DEV_SERIAL_NUM_DW2 0x0148 #define cfgPSWUSCFG0_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x0150 #define cfgPSWUSCFG0_0_PCIE_UNCORR_ERR_STATUS 0x0154 #define cfgPSWUSCFG0_0_PCIE_UNCORR_ERR_MASK 0x0158 #define cfgPSWUSCFG0_0_PCIE_UNCORR_ERR_SEVERITY 0x015c #define cfgPSWUSCFG0_0_PCIE_CORR_ERR_STATUS 0x0160 #define cfgPSWUSCFG0_0_PCIE_CORR_ERR_MASK 0x0164 #define cfgPSWUSCFG0_0_PCIE_ADV_ERR_CAP_CNTL 0x0168 #define cfgPSWUSCFG0_0_PCIE_HDR_LOG0 0x016c #define cfgPSWUSCFG0_0_PCIE_HDR_LOG1 0x0170 #define cfgPSWUSCFG0_0_PCIE_HDR_LOG2 0x0174 #define cfgPSWUSCFG0_0_PCIE_HDR_LOG3 0x0178 #define cfgPSWUSCFG0_0_PCIE_TLP_PREFIX_LOG0 0x0188 #define cfgPSWUSCFG0_0_PCIE_TLP_PREFIX_LOG1 0x018c #define cfgPSWUSCFG0_0_PCIE_TLP_PREFIX_LOG2 0x0190 #define cfgPSWUSCFG0_0_PCIE_TLP_PREFIX_LOG3 0x0194 #define cfgPSWUSCFG0_0_PCIE_SECONDARY_ENH_CAP_LIST 0x0270 #define cfgPSWUSCFG0_0_PCIE_LINK_CNTL3 0x0274 #define cfgPSWUSCFG0_0_PCIE_LANE_ERROR_STATUS 0x0278 #define cfgPSWUSCFG0_0_PCIE_LANE_0_EQUALIZATION_CNTL 0x027c #define cfgPSWUSCFG0_0_PCIE_LANE_1_EQUALIZATION_CNTL 0x027e #define cfgPSWUSCFG0_0_PCIE_LANE_2_EQUALIZATION_CNTL 0x0280 #define cfgPSWUSCFG0_0_PCIE_LANE_3_EQUALIZATION_CNTL 0x0282 #define cfgPSWUSCFG0_0_PCIE_LANE_4_EQUALIZATION_CNTL 0x0284 #define cfgPSWUSCFG0_0_PCIE_LANE_5_EQUALIZATION_CNTL 0x0286 #define cfgPSWUSCFG0_0_PCIE_LANE_6_EQUALIZATION_CNTL 0x0288 #define cfgPSWUSCFG0_0_PCIE_LANE_7_EQUALIZATION_CNTL 0x028a #define cfgPSWUSCFG0_0_PCIE_LANE_8_EQUALIZATION_CNTL 0x028c #define cfgPSWUSCFG0_0_PCIE_LANE_9_EQUALIZATION_CNTL 0x028e #define cfgPSWUSCFG0_0_PCIE_LANE_10_EQUALIZATION_CNTL 0x0290 #define cfgPSWUSCFG0_0_PCIE_LANE_11_EQUALIZATION_CNTL 0x0292 #define cfgPSWUSCFG0_0_PCIE_LANE_12_EQUALIZATION_CNTL 0x0294 #define cfgPSWUSCFG0_0_PCIE_LANE_13_EQUALIZATION_CNTL 0x0296 #define cfgPSWUSCFG0_0_PCIE_LANE_14_EQUALIZATION_CNTL 0x0298 #define cfgPSWUSCFG0_0_PCIE_LANE_15_EQUALIZATION_CNTL 0x029a #define cfgPSWUSCFG0_0_PCIE_ACS_ENH_CAP_LIST 0x02a0 #define cfgPSWUSCFG0_0_PCIE_ACS_CAP 0x02a4 #define cfgPSWUSCFG0_0_PCIE_ACS_CNTL 0x02a6 #define cfgPSWUSCFG0_0_PCIE_MC_ENH_CAP_LIST 0x02f0 #define cfgPSWUSCFG0_0_PCIE_MC_CAP 0x02f4 #define cfgPSWUSCFG0_0_PCIE_MC_CNTL 0x02f6 #define cfgPSWUSCFG0_0_PCIE_MC_ADDR0 0x02f8 #define cfgPSWUSCFG0_0_PCIE_MC_ADDR1 0x02fc #define cfgPSWUSCFG0_0_PCIE_MC_RCV0 0x0300 #define cfgPSWUSCFG0_0_PCIE_MC_RCV1 0x0304 #define cfgPSWUSCFG0_0_PCIE_MC_BLOCK_ALL0 0x0308 #define cfgPSWUSCFG0_0_PCIE_MC_BLOCK_ALL1 0x030c #define cfgPSWUSCFG0_0_PCIE_MC_BLOCK_UNTRANSLATED_0 0x0310 #define cfgPSWUSCFG0_0_PCIE_MC_BLOCK_UNTRANSLATED_1 0x0314 #define cfgPSWUSCFG0_0_PCIE_MC_OVERLAY_BAR0 0x0318 #define cfgPSWUSCFG0_0_PCIE_MC_OVERLAY_BAR1 0x031c #define cfgPSWUSCFG0_0_PCIE_LTR_ENH_CAP_LIST 0x0320 #define cfgPSWUSCFG0_0_PCIE_LTR_CAP 0x0324 #define cfgPSWUSCFG0_0_PCIE_ARI_ENH_CAP_LIST 0x0328 #define cfgPSWUSCFG0_0_PCIE_ARI_CAP 0x032c #define cfgPSWUSCFG0_0_PCIE_ARI_CNTL 0x032e #define cfgPSWUSCFG0_0_PCIE_L1_PM_SUB_CAP_LIST 0x0370 #define cfgPSWUSCFG0_0_PCIE_L1_PM_SUB_CAP 0x0374 #define cfgPSWUSCFG0_0_PCIE_L1_PM_SUB_CNTL 0x0378 #define cfgPSWUSCFG0_0_PCIE_L1_PM_SUB_CNTL2 0x037c #define cfgPSWUSCFG0_0_PCIE_ESM_CAP_LIST 0x03c4 #define cfgPSWUSCFG0_0_PCIE_ESM_HEADER_1 0x03c8 #define cfgPSWUSCFG0_0_PCIE_ESM_HEADER_2 0x03cc #define cfgPSWUSCFG0_0_PCIE_ESM_STATUS 0x03ce #define cfgPSWUSCFG0_0_PCIE_ESM_CTRL 0x03d0 #define cfgPSWUSCFG0_0_PCIE_ESM_CAP_1 0x03d4 #define cfgPSWUSCFG0_0_PCIE_ESM_CAP_2 0x03d8 #define cfgPSWUSCFG0_0_PCIE_ESM_CAP_3 0x03dc #define cfgPSWUSCFG0_0_PCIE_ESM_CAP_4 0x03e0 #define cfgPSWUSCFG0_0_PCIE_ESM_CAP_5 0x03e4 #define cfgPSWUSCFG0_0_PCIE_ESM_CAP_6 0x03e8 #define cfgPSWUSCFG0_0_PCIE_ESM_CAP_7 0x03ec #define cfgPSWUSCFG0_0_PCIE_DLF_ENH_CAP_LIST 0x0400 #define cfgPSWUSCFG0_0_DATA_LINK_FEATURE_CAP 0x0404 #define cfgPSWUSCFG0_0_DATA_LINK_FEATURE_STATUS 0x0408 #define cfgPSWUSCFG0_0_PCIE_PHY_16GT_ENH_CAP_LIST 0x0410 #define cfgPSWUSCFG0_0_LINK_CAP_16GT 0x0414 #define cfgPSWUSCFG0_0_LINK_CNTL_16GT 0x0418 #define cfgPSWUSCFG0_0_LINK_STATUS_16GT 0x041c #define cfgPSWUSCFG0_0_LOCAL_PARITY_MISMATCH_STATUS_16GT 0x0420 #define cfgPSWUSCFG0_0_RTM1_PARITY_MISMATCH_STATUS_16GT 0x0424 #define cfgPSWUSCFG0_0_RTM2_PARITY_MISMATCH_STATUS_16GT 0x0428 #define cfgPSWUSCFG0_0_LANE_0_EQUALIZATION_CNTL_16GT 0x0430 #define cfgPSWUSCFG0_0_LANE_1_EQUALIZATION_CNTL_16GT 0x0431 #define cfgPSWUSCFG0_0_LANE_2_EQUALIZATION_CNTL_16GT 0x0432 #define cfgPSWUSCFG0_0_LANE_3_EQUALIZATION_CNTL_16GT 0x0433 #define cfgPSWUSCFG0_0_LANE_4_EQUALIZATION_CNTL_16GT 0x0434 #define cfgPSWUSCFG0_0_LANE_5_EQUALIZATION_CNTL_16GT 0x0435 #define cfgPSWUSCFG0_0_LANE_6_EQUALIZATION_CNTL_16GT 0x0436 #define cfgPSWUSCFG0_0_LANE_7_EQUALIZATION_CNTL_16GT 0x0437 #define cfgPSWUSCFG0_0_LANE_8_EQUALIZATION_CNTL_16GT 0x0438 #define cfgPSWUSCFG0_0_LANE_9_EQUALIZATION_CNTL_16GT 0x0439 #define cfgPSWUSCFG0_0_LANE_10_EQUALIZATION_CNTL_16GT 0x043a #define cfgPSWUSCFG0_0_LANE_11_EQUALIZATION_CNTL_16GT 0x043b #define cfgPSWUSCFG0_0_LANE_12_EQUALIZATION_CNTL_16GT 0x043c #define cfgPSWUSCFG0_0_LANE_13_EQUALIZATION_CNTL_16GT 0x043d #define cfgPSWUSCFG0_0_LANE_14_EQUALIZATION_CNTL_16GT 0x043e #define cfgPSWUSCFG0_0_LANE_15_EQUALIZATION_CNTL_16GT 0x043f #define cfgPSWUSCFG0_0_PCIE_MARGINING_ENH_CAP_LIST 0x0440 #define cfgPSWUSCFG0_0_MARGINING_PORT_CAP 0x0444 #define cfgPSWUSCFG0_0_MARGINING_PORT_STATUS 0x0446 #define cfgPSWUSCFG0_0_LANE_0_MARGINING_LANE_CNTL 0x0448 #define cfgPSWUSCFG0_0_LANE_0_MARGINING_LANE_STATUS 0x044a #define cfgPSWUSCFG0_0_LANE_1_MARGINING_LANE_CNTL 0x044c #define cfgPSWUSCFG0_0_LANE_1_MARGINING_LANE_STATUS 0x044e #define cfgPSWUSCFG0_0_LANE_2_MARGINING_LANE_CNTL 0x0450 #define cfgPSWUSCFG0_0_LANE_2_MARGINING_LANE_STATUS 0x0452 #define cfgPSWUSCFG0_0_LANE_3_MARGINING_LANE_CNTL 0x0454 #define cfgPSWUSCFG0_0_LANE_3_MARGINING_LANE_STATUS 0x0456 #define cfgPSWUSCFG0_0_LANE_4_MARGINING_LANE_CNTL 0x0458 #define cfgPSWUSCFG0_0_LANE_4_MARGINING_LANE_STATUS 0x045a #define cfgPSWUSCFG0_0_LANE_5_MARGINING_LANE_CNTL 0x045c #define cfgPSWUSCFG0_0_LANE_5_MARGINING_LANE_STATUS 0x045e #define cfgPSWUSCFG0_0_LANE_6_MARGINING_LANE_CNTL 0x0460 #define cfgPSWUSCFG0_0_LANE_6_MARGINING_LANE_STATUS 0x0462 #define cfgPSWUSCFG0_0_LANE_7_MARGINING_LANE_CNTL 0x0464 #define cfgPSWUSCFG0_0_LANE_7_MARGINING_LANE_STATUS 0x0466 #define cfgPSWUSCFG0_0_LANE_8_MARGINING_LANE_CNTL 0x0468 #define cfgPSWUSCFG0_0_LANE_8_MARGINING_LANE_STATUS 0x046a #define cfgPSWUSCFG0_0_LANE_9_MARGINING_LANE_CNTL 0x046c #define cfgPSWUSCFG0_0_LANE_9_MARGINING_LANE_STATUS 0x046e #define cfgPSWUSCFG0_0_LANE_10_MARGINING_LANE_CNTL 0x0470 #define cfgPSWUSCFG0_0_LANE_10_MARGINING_LANE_STATUS 0x0472 #define cfgPSWUSCFG0_0_LANE_11_MARGINING_LANE_CNTL 0x0474 #define cfgPSWUSCFG0_0_LANE_11_MARGINING_LANE_STATUS 0x0476 #define cfgPSWUSCFG0_0_LANE_12_MARGINING_LANE_CNTL 0x0478 #define cfgPSWUSCFG0_0_LANE_12_MARGINING_LANE_STATUS 0x047a #define cfgPSWUSCFG0_0_LANE_13_MARGINING_LANE_CNTL 0x047c #define cfgPSWUSCFG0_0_LANE_13_MARGINING_LANE_STATUS 0x047e #define cfgPSWUSCFG0_0_LANE_14_MARGINING_LANE_CNTL 0x0480 #define cfgPSWUSCFG0_0_LANE_14_MARGINING_LANE_STATUS 0x0482 #define cfgPSWUSCFG0_0_LANE_15_MARGINING_LANE_CNTL 0x0484 #define cfgPSWUSCFG0_0_LANE_15_MARGINING_LANE_STATUS 0x0486 #define cfgPSWUSCFG0_0_PCIE_CCIX_CAP_LIST 0x0488 #define cfgPSWUSCFG0_0_PCIE_CCIX_HEADER_1 0x048c #define cfgPSWUSCFG0_0_PCIE_CCIX_HEADER_2 0x0490 #define cfgPSWUSCFG0_0_PCIE_CCIX_CAP 0x0492 #define cfgPSWUSCFG0_0_PCIE_CCIX_ESM_REQD_CAP 0x0494 #define cfgPSWUSCFG0_0_PCIE_CCIX_ESM_OPTL_CAP 0x0498 #define cfgPSWUSCFG0_0_PCIE_CCIX_ESM_STATUS 0x049c #define cfgPSWUSCFG0_0_PCIE_CCIX_ESM_CNTL 0x04a0 #define cfgPSWUSCFG0_0_ESM_LANE_0_EQUALIZATION_CNTL_20GT 0x04a4 #define cfgPSWUSCFG0_0_ESM_LANE_1_EQUALIZATION_CNTL_20GT 0x04a5 #define cfgPSWUSCFG0_0_ESM_LANE_2_EQUALIZATION_CNTL_20GT 0x04a6 #define cfgPSWUSCFG0_0_ESM_LANE_3_EQUALIZATION_CNTL_20GT 0x04a7 #define cfgPSWUSCFG0_0_ESM_LANE_4_EQUALIZATION_CNTL_20GT 0x04a8 #define cfgPSWUSCFG0_0_ESM_LANE_5_EQUALIZATION_CNTL_20GT 0x04a9 #define cfgPSWUSCFG0_0_ESM_LANE_6_EQUALIZATION_CNTL_20GT 0x04aa #define cfgPSWUSCFG0_0_ESM_LANE_7_EQUALIZATION_CNTL_20GT 0x04ab #define cfgPSWUSCFG0_0_ESM_LANE_8_EQUALIZATION_CNTL_20GT 0x04ac #define cfgPSWUSCFG0_0_ESM_LANE_9_EQUALIZATION_CNTL_20GT 0x04ad #define cfgPSWUSCFG0_0_ESM_LANE_10_EQUALIZATION_CNTL_20GT 0x04ae #define cfgPSWUSCFG0_0_ESM_LANE_11_EQUALIZATION_CNTL_20GT 0x04af #define cfgPSWUSCFG0_0_ESM_LANE_12_EQUALIZATION_CNTL_20GT 0x04b0 #define cfgPSWUSCFG0_0_ESM_LANE_13_EQUALIZATION_CNTL_20GT 0x04b1 #define cfgPSWUSCFG0_0_ESM_LANE_14_EQUALIZATION_CNTL_20GT 0x04b2 #define cfgPSWUSCFG0_0_ESM_LANE_15_EQUALIZATION_CNTL_20GT 0x04b3 #define cfgPSWUSCFG0_0_ESM_LANE_0_EQUALIZATION_CNTL_25GT 0x04b4 #define cfgPSWUSCFG0_0_ESM_LANE_1_EQUALIZATION_CNTL_25GT 0x04b5 #define cfgPSWUSCFG0_0_ESM_LANE_2_EQUALIZATION_CNTL_25GT 0x04b6 #define cfgPSWUSCFG0_0_ESM_LANE_3_EQUALIZATION_CNTL_25GT 0x04b7 #define cfgPSWUSCFG0_0_ESM_LANE_4_EQUALIZATION_CNTL_25GT 0x04b8 #define cfgPSWUSCFG0_0_ESM_LANE_5_EQUALIZATION_CNTL_25GT 0x04b9 #define cfgPSWUSCFG0_0_ESM_LANE_6_EQUALIZATION_CNTL_25GT 0x04ba #define cfgPSWUSCFG0_0_ESM_LANE_7_EQUALIZATION_CNTL_25GT 0x04bb #define cfgPSWUSCFG0_0_ESM_LANE_8_EQUALIZATION_CNTL_25GT 0x04bc #define cfgPSWUSCFG0_0_ESM_LANE_9_EQUALIZATION_CNTL_25GT 0x04bd #define cfgPSWUSCFG0_0_ESM_LANE_10_EQUALIZATION_CNTL_25GT 0x04be #define cfgPSWUSCFG0_0_ESM_LANE_11_EQUALIZATION_CNTL_25GT 0x04bf #define cfgPSWUSCFG0_0_ESM_LANE_12_EQUALIZATION_CNTL_25GT 0x04c0 #define cfgPSWUSCFG0_0_ESM_LANE_13_EQUALIZATION_CNTL_25GT 0x04c1 #define cfgPSWUSCFG0_0_ESM_LANE_14_EQUALIZATION_CNTL_25GT 0x04c2 #define cfgPSWUSCFG0_0_ESM_LANE_15_EQUALIZATION_CNTL_25GT 0x04c3 #define cfgPSWUSCFG0_0_PCIE_CCIX_TRANS_CAP 0x04c4 #define cfgPSWUSCFG0_0_PCIE_CCIX_TRANS_CNTL 0x04c8 // addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_bifcfgdecp // base address: 0x0 #define cfgBIF_CFG_DEV0_EPF0_0_VENDOR_ID 0x0000 #define cfgBIF_CFG_DEV0_EPF0_0_DEVICE_ID 0x0002 #define cfgBIF_CFG_DEV0_EPF0_0_COMMAND 0x0004 #define cfgBIF_CFG_DEV0_EPF0_0_STATUS 0x0006 #define cfgBIF_CFG_DEV0_EPF0_0_REVISION_ID 0x0008 #define cfgBIF_CFG_DEV0_EPF0_0_PROG_INTERFACE 0x0009 #define cfgBIF_CFG_DEV0_EPF0_0_SUB_CLASS 0x000a #define cfgBIF_CFG_DEV0_EPF0_0_BASE_CLASS 0x000b #define cfgBIF_CFG_DEV0_EPF0_0_CACHE_LINE 0x000c #define cfgBIF_CFG_DEV0_EPF0_0_LATENCY 0x000d #define cfgBIF_CFG_DEV0_EPF0_0_HEADER 0x000e #define cfgBIF_CFG_DEV0_EPF0_0_BIST 0x000f #define cfgBIF_CFG_DEV0_EPF0_0_BASE_ADDR_1 0x0010 #define cfgBIF_CFG_DEV0_EPF0_0_BASE_ADDR_2 0x0014 #define cfgBIF_CFG_DEV0_EPF0_0_BASE_ADDR_3 0x0018 #define cfgBIF_CFG_DEV0_EPF0_0_BASE_ADDR_4 0x001c #define cfgBIF_CFG_DEV0_EPF0_0_BASE_ADDR_5 0x0020 #define cfgBIF_CFG_DEV0_EPF0_0_BASE_ADDR_6 0x0024 #define cfgBIF_CFG_DEV0_EPF0_0_CARDBUS_CIS_PTR 0x0028 #define cfgBIF_CFG_DEV0_EPF0_0_ADAPTER_ID 0x002c #define cfgBIF_CFG_DEV0_EPF0_0_ROM_BASE_ADDR 0x0030 #define cfgBIF_CFG_DEV0_EPF0_0_CAP_PTR 0x0034 #define cfgBIF_CFG_DEV0_EPF0_0_INTERRUPT_LINE 0x003c #define cfgBIF_CFG_DEV0_EPF0_0_INTERRUPT_PIN 0x003d #define cfgBIF_CFG_DEV0_EPF0_0_MIN_GRANT 0x003e #define cfgBIF_CFG_DEV0_EPF0_0_MAX_LATENCY 0x003f #define cfgBIF_CFG_DEV0_EPF0_0_VENDOR_CAP_LIST 0x0048 #define cfgBIF_CFG_DEV0_EPF0_0_ADAPTER_ID_W 0x004c #define cfgBIF_CFG_DEV0_EPF0_0_PMI_CAP_LIST 0x0050 #define cfgBIF_CFG_DEV0_EPF0_0_PMI_CAP 0x0052 #define cfgBIF_CFG_DEV0_EPF0_0_PMI_STATUS_CNTL 0x0054 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_CAP_LIST 0x0064 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_CAP 0x0066 #define cfgBIF_CFG_DEV0_EPF0_0_DEVICE_CAP 0x0068 #define cfgBIF_CFG_DEV0_EPF0_0_DEVICE_CNTL 0x006c #define cfgBIF_CFG_DEV0_EPF0_0_DEVICE_STATUS 0x006e #define cfgBIF_CFG_DEV0_EPF0_0_LINK_CAP 0x0070 #define cfgBIF_CFG_DEV0_EPF0_0_LINK_CNTL 0x0074 #define cfgBIF_CFG_DEV0_EPF0_0_LINK_STATUS 0x0076 #define cfgBIF_CFG_DEV0_EPF0_0_DEVICE_CAP2 0x0088 #define cfgBIF_CFG_DEV0_EPF0_0_DEVICE_CNTL2 0x008c #define cfgBIF_CFG_DEV0_EPF0_0_DEVICE_STATUS2 0x008e #define cfgBIF_CFG_DEV0_EPF0_0_LINK_CAP2 0x0090 #define cfgBIF_CFG_DEV0_EPF0_0_LINK_CNTL2 0x0094 #define cfgBIF_CFG_DEV0_EPF0_0_LINK_STATUS2 0x0096 #define cfgBIF_CFG_DEV0_EPF0_0_MSI_CAP_LIST 0x00a0 #define cfgBIF_CFG_DEV0_EPF0_0_MSI_MSG_CNTL 0x00a2 #define cfgBIF_CFG_DEV0_EPF0_0_MSI_MSG_ADDR_LO 0x00a4 #define cfgBIF_CFG_DEV0_EPF0_0_MSI_MSG_ADDR_HI 0x00a8 #define cfgBIF_CFG_DEV0_EPF0_0_MSI_MSG_DATA 0x00a8 #define cfgBIF_CFG_DEV0_EPF0_0_MSI_MASK 0x00ac #define cfgBIF_CFG_DEV0_EPF0_0_MSI_MSG_DATA_64 0x00ac #define cfgBIF_CFG_DEV0_EPF0_0_MSI_MASK_64 0x00b0 #define cfgBIF_CFG_DEV0_EPF0_0_MSI_PENDING 0x00b0 #define cfgBIF_CFG_DEV0_EPF0_0_MSI_PENDING_64 0x00b4 #define cfgBIF_CFG_DEV0_EPF0_0_MSIX_CAP_LIST 0x00c0 #define cfgBIF_CFG_DEV0_EPF0_0_MSIX_MSG_CNTL 0x00c2 #define cfgBIF_CFG_DEV0_EPF0_0_MSIX_TABLE 0x00c4 #define cfgBIF_CFG_DEV0_EPF0_0_MSIX_PBA 0x00c8 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x0100 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR 0x0104 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC1 0x0108 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC2 0x010c #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VC_ENH_CAP_LIST 0x0110 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_PORT_VC_CAP_REG1 0x0114 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_PORT_VC_CAP_REG2 0x0118 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_PORT_VC_CNTL 0x011c #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_PORT_VC_STATUS 0x011e #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VC0_RESOURCE_CAP 0x0120 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VC0_RESOURCE_CNTL 0x0124 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VC0_RESOURCE_STATUS 0x012a #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VC1_RESOURCE_CAP 0x012c #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VC1_RESOURCE_CNTL 0x0130 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VC1_RESOURCE_STATUS 0x0136 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST 0x0140 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_DEV_SERIAL_NUM_DW1 0x0144 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_DEV_SERIAL_NUM_DW2 0x0148 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x0150 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS 0x0154 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK 0x0158 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY 0x015c #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_STATUS 0x0160 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_MASK 0x0164 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_ADV_ERR_CAP_CNTL 0x0168 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_HDR_LOG0 0x016c #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_HDR_LOG1 0x0170 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_HDR_LOG2 0x0174 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_HDR_LOG3 0x0178 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_TLP_PREFIX_LOG0 0x0188 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_TLP_PREFIX_LOG1 0x018c #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_TLP_PREFIX_LOG2 0x0190 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_TLP_PREFIX_LOG3 0x0194 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_BAR_ENH_CAP_LIST 0x0200 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_BAR1_CAP 0x0204 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_BAR1_CNTL 0x0208 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_BAR2_CAP 0x020c #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_BAR2_CNTL 0x0210 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_BAR3_CAP 0x0214 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_BAR3_CNTL 0x0218 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_BAR4_CAP 0x021c #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_BAR4_CNTL 0x0220 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_BAR5_CAP 0x0224 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_BAR5_CNTL 0x0228 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_BAR6_CAP 0x022c #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_BAR6_CNTL 0x0230 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_PWR_BUDGET_ENH_CAP_LIST 0x0240 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_PWR_BUDGET_DATA_SELECT 0x0244 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_PWR_BUDGET_DATA 0x0248 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_PWR_BUDGET_CAP 0x024c #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_DPA_ENH_CAP_LIST 0x0250 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_DPA_CAP 0x0254 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_DPA_LATENCY_INDICATOR 0x0258 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_DPA_STATUS 0x025c #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_DPA_CNTL 0x025e #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_0 0x0260 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_1 0x0261 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_2 0x0262 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_3 0x0263 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_4 0x0264 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_5 0x0265 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_6 0x0266 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_7 0x0267 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_SECONDARY_ENH_CAP_LIST 0x0270 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_LINK_CNTL3 0x0274 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_LANE_ERROR_STATUS 0x0278 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_LANE_0_EQUALIZATION_CNTL 0x027c #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_LANE_1_EQUALIZATION_CNTL 0x027e #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_LANE_2_EQUALIZATION_CNTL 0x0280 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_LANE_3_EQUALIZATION_CNTL 0x0282 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_LANE_4_EQUALIZATION_CNTL 0x0284 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_LANE_5_EQUALIZATION_CNTL 0x0286 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_LANE_6_EQUALIZATION_CNTL 0x0288 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_LANE_7_EQUALIZATION_CNTL 0x028a #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_LANE_8_EQUALIZATION_CNTL 0x028c #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_LANE_9_EQUALIZATION_CNTL 0x028e #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_LANE_10_EQUALIZATION_CNTL 0x0290 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_LANE_11_EQUALIZATION_CNTL 0x0292 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_LANE_12_EQUALIZATION_CNTL 0x0294 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_LANE_13_EQUALIZATION_CNTL 0x0296 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_LANE_14_EQUALIZATION_CNTL 0x0298 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_LANE_15_EQUALIZATION_CNTL 0x029a #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_ACS_ENH_CAP_LIST 0x02a0 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_ACS_CAP 0x02a4 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_ACS_CNTL 0x02a6 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_ATS_ENH_CAP_LIST 0x02b0 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_ATS_CAP 0x02b4 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_ATS_CNTL 0x02b6 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_PAGE_REQ_ENH_CAP_LIST 0x02c0 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_PAGE_REQ_CNTL 0x02c4 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_PAGE_REQ_STATUS 0x02c6 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_OUTSTAND_PAGE_REQ_CAPACITY 0x02c8 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_OUTSTAND_PAGE_REQ_ALLOC 0x02cc #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_PASID_ENH_CAP_LIST 0x02d0 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_PASID_CAP 0x02d4 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_PASID_CNTL 0x02d6 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_MC_ENH_CAP_LIST 0x02f0 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_MC_CAP 0x02f4 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_MC_CNTL 0x02f6 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_MC_ADDR0 0x02f8 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_MC_ADDR1 0x02fc #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_MC_RCV0 0x0300 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_MC_RCV1 0x0304 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_MC_BLOCK_ALL0 0x0308 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_MC_BLOCK_ALL1 0x030c #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_MC_BLOCK_UNTRANSLATED_0 0x0310 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_MC_BLOCK_UNTRANSLATED_1 0x0314 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_LTR_ENH_CAP_LIST 0x0320 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_LTR_CAP 0x0324 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_ARI_ENH_CAP_LIST 0x0328 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_ARI_CAP 0x032c #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_ARI_CNTL 0x032e #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_ENH_CAP_LIST 0x0330 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_CAP 0x0334 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_CONTROL 0x0338 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_STATUS 0x033a #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_INITIAL_VFS 0x033c #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_TOTAL_VFS 0x033e #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_NUM_VFS 0x0340 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_FUNC_DEP_LINK 0x0342 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_FIRST_VF_OFFSET 0x0344 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_STRIDE 0x0346 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_DEVICE_ID 0x034a #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_SUPPORTED_PAGE_SIZE 0x034c #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_SYSTEM_PAGE_SIZE 0x0350 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_BASE_ADDR_0 0x0354 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_BASE_ADDR_1 0x0358 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_BASE_ADDR_2 0x035c #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_BASE_ADDR_3 0x0360 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_BASE_ADDR_4 0x0364 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_BASE_ADDR_5 0x0368 #define your_sha256_hashT 0x036c #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_TPH_REQR_ENH_CAP_LIST 0x0370 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_TPH_REQR_CAP 0x0374 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_TPH_REQR_CNTL 0x0378 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_DLF_ENH_CAP_LIST 0x0400 #define cfgBIF_CFG_DEV0_EPF0_0_DATA_LINK_FEATURE_CAP 0x0404 #define cfgBIF_CFG_DEV0_EPF0_0_DATA_LINK_FEATURE_STATUS 0x0408 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_PHY_16GT_ENH_CAP_LIST 0x0410 #define cfgBIF_CFG_DEV0_EPF0_0_LINK_CAP_16GT 0x0414 #define cfgBIF_CFG_DEV0_EPF0_0_LINK_CNTL_16GT 0x0418 #define cfgBIF_CFG_DEV0_EPF0_0_LINK_STATUS_16GT 0x041c #define cfgBIF_CFG_DEV0_EPF0_0_LOCAL_PARITY_MISMATCH_STATUS_16GT 0x0420 #define cfgBIF_CFG_DEV0_EPF0_0_RTM1_PARITY_MISMATCH_STATUS_16GT 0x0424 #define cfgBIF_CFG_DEV0_EPF0_0_RTM2_PARITY_MISMATCH_STATUS_16GT 0x0428 #define cfgBIF_CFG_DEV0_EPF0_0_LANE_0_EQUALIZATION_CNTL_16GT 0x0430 #define cfgBIF_CFG_DEV0_EPF0_0_LANE_1_EQUALIZATION_CNTL_16GT 0x0431 #define cfgBIF_CFG_DEV0_EPF0_0_LANE_2_EQUALIZATION_CNTL_16GT 0x0432 #define cfgBIF_CFG_DEV0_EPF0_0_LANE_3_EQUALIZATION_CNTL_16GT 0x0433 #define cfgBIF_CFG_DEV0_EPF0_0_LANE_4_EQUALIZATION_CNTL_16GT 0x0434 #define cfgBIF_CFG_DEV0_EPF0_0_LANE_5_EQUALIZATION_CNTL_16GT 0x0435 #define cfgBIF_CFG_DEV0_EPF0_0_LANE_6_EQUALIZATION_CNTL_16GT 0x0436 #define cfgBIF_CFG_DEV0_EPF0_0_LANE_7_EQUALIZATION_CNTL_16GT 0x0437 #define cfgBIF_CFG_DEV0_EPF0_0_LANE_8_EQUALIZATION_CNTL_16GT 0x0438 #define cfgBIF_CFG_DEV0_EPF0_0_LANE_9_EQUALIZATION_CNTL_16GT 0x0439 #define cfgBIF_CFG_DEV0_EPF0_0_LANE_10_EQUALIZATION_CNTL_16GT 0x043a #define cfgBIF_CFG_DEV0_EPF0_0_LANE_11_EQUALIZATION_CNTL_16GT 0x043b #define cfgBIF_CFG_DEV0_EPF0_0_LANE_12_EQUALIZATION_CNTL_16GT 0x043c #define cfgBIF_CFG_DEV0_EPF0_0_LANE_13_EQUALIZATION_CNTL_16GT 0x043d #define cfgBIF_CFG_DEV0_EPF0_0_LANE_14_EQUALIZATION_CNTL_16GT 0x043e #define cfgBIF_CFG_DEV0_EPF0_0_LANE_15_EQUALIZATION_CNTL_16GT 0x043f #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_MARGINING_ENH_CAP_LIST 0x0440 #define cfgBIF_CFG_DEV0_EPF0_0_MARGINING_PORT_CAP 0x0444 #define cfgBIF_CFG_DEV0_EPF0_0_MARGINING_PORT_STATUS 0x0446 #define cfgBIF_CFG_DEV0_EPF0_0_LANE_0_MARGINING_LANE_CNTL 0x0448 #define cfgBIF_CFG_DEV0_EPF0_0_LANE_0_MARGINING_LANE_STATUS 0x044a #define cfgBIF_CFG_DEV0_EPF0_0_LANE_1_MARGINING_LANE_CNTL 0x044c #define cfgBIF_CFG_DEV0_EPF0_0_LANE_1_MARGINING_LANE_STATUS 0x044e #define cfgBIF_CFG_DEV0_EPF0_0_LANE_2_MARGINING_LANE_CNTL 0x0450 #define cfgBIF_CFG_DEV0_EPF0_0_LANE_2_MARGINING_LANE_STATUS 0x0452 #define cfgBIF_CFG_DEV0_EPF0_0_LANE_3_MARGINING_LANE_CNTL 0x0454 #define cfgBIF_CFG_DEV0_EPF0_0_LANE_3_MARGINING_LANE_STATUS 0x0456 #define cfgBIF_CFG_DEV0_EPF0_0_LANE_4_MARGINING_LANE_CNTL 0x0458 #define cfgBIF_CFG_DEV0_EPF0_0_LANE_4_MARGINING_LANE_STATUS 0x045a #define cfgBIF_CFG_DEV0_EPF0_0_LANE_5_MARGINING_LANE_CNTL 0x045c #define cfgBIF_CFG_DEV0_EPF0_0_LANE_5_MARGINING_LANE_STATUS 0x045e #define cfgBIF_CFG_DEV0_EPF0_0_LANE_6_MARGINING_LANE_CNTL 0x0460 #define cfgBIF_CFG_DEV0_EPF0_0_LANE_6_MARGINING_LANE_STATUS 0x0462 #define cfgBIF_CFG_DEV0_EPF0_0_LANE_7_MARGINING_LANE_CNTL 0x0464 #define cfgBIF_CFG_DEV0_EPF0_0_LANE_7_MARGINING_LANE_STATUS 0x0466 #define cfgBIF_CFG_DEV0_EPF0_0_LANE_8_MARGINING_LANE_CNTL 0x0468 #define cfgBIF_CFG_DEV0_EPF0_0_LANE_8_MARGINING_LANE_STATUS 0x046a #define cfgBIF_CFG_DEV0_EPF0_0_LANE_9_MARGINING_LANE_CNTL 0x046c #define cfgBIF_CFG_DEV0_EPF0_0_LANE_9_MARGINING_LANE_STATUS 0x046e #define cfgBIF_CFG_DEV0_EPF0_0_LANE_10_MARGINING_LANE_CNTL 0x0470 #define cfgBIF_CFG_DEV0_EPF0_0_LANE_10_MARGINING_LANE_STATUS 0x0472 #define cfgBIF_CFG_DEV0_EPF0_0_LANE_11_MARGINING_LANE_CNTL 0x0474 #define cfgBIF_CFG_DEV0_EPF0_0_LANE_11_MARGINING_LANE_STATUS 0x0476 #define cfgBIF_CFG_DEV0_EPF0_0_LANE_12_MARGINING_LANE_CNTL 0x0478 #define cfgBIF_CFG_DEV0_EPF0_0_LANE_12_MARGINING_LANE_STATUS 0x047a #define cfgBIF_CFG_DEV0_EPF0_0_LANE_13_MARGINING_LANE_CNTL 0x047c #define cfgBIF_CFG_DEV0_EPF0_0_LANE_13_MARGINING_LANE_STATUS 0x047e #define cfgBIF_CFG_DEV0_EPF0_0_LANE_14_MARGINING_LANE_CNTL 0x0480 #define cfgBIF_CFG_DEV0_EPF0_0_LANE_14_MARGINING_LANE_STATUS 0x0482 #define cfgBIF_CFG_DEV0_EPF0_0_LANE_15_MARGINING_LANE_CNTL 0x0484 #define cfgBIF_CFG_DEV0_EPF0_0_LANE_15_MARGINING_LANE_STATUS 0x0486 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR_ENH_CAP_LIST 0x04c0 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR1_CAP 0x04c4 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR1_CNTL 0x04c8 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR2_CAP 0x04cc #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR2_CNTL 0x04d0 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR3_CAP 0x04d4 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR3_CNTL 0x04d8 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR4_CAP 0x04dc #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR4_CNTL 0x04e0 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR5_CAP 0x04e4 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR5_CNTL 0x04e8 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR6_CAP 0x04ec #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR6_CNTL 0x04f0 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV 0x0500 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV 0x0504 #define your_sha256_hashDOW 0x0508 #define your_sha256_hashLE 0x050c #define your_sha256_hashUS 0x0510 #define your_sha256_hashTROL 0x0514 #define your_sha256_hash_DW0 0x0518 #define your_sha256_hash_DW1 0x051c #define your_sha256_hash_DW2 0x0520 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CONTEXT 0x0524 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_TOTAL_FB 0x0528 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS 0x052c #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_REGION 0x0530 #define your_sha256_hashXGMI_ENABLE 0x0534 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF0_FB 0x0538 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF1_FB 0x053c #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF2_FB 0x0540 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF3_FB 0x0544 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF4_FB 0x0548 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF5_FB 0x054c #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF6_FB 0x0550 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF7_FB 0x0554 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF8_FB 0x0558 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF9_FB 0x055c #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF10_FB 0x0560 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF11_FB 0x0564 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF12_FB 0x0568 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF13_FB 0x056c #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF14_FB 0x0570 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF15_FB 0x0574 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF16_FB 0x0578 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF17_FB 0x057c #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF18_FB 0x0580 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF19_FB 0x0584 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF20_FB 0x0588 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF21_FB 0x058c #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF22_FB 0x0590 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF23_FB 0x0594 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF24_FB 0x0598 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF25_FB 0x059c #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF26_FB 0x05a0 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF27_FB 0x05a4 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF28_FB 0x05a8 #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF29_FB 0x05ac #define cfgBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF30_FB 0x05b0 #define your_sha256_hash0 0x05c0 #define your_sha256_hash1 0x05c4 #define your_sha256_hash2 0x05c8 #define your_sha256_hash3 0x05cc #define your_sha256_hash4 0x05d0 #define your_sha256_hash5 0x05d4 #define your_sha256_hash6 0x05d8 #define your_sha256_hash7 0x05dc #define your_sha256_hash8 0x05e0 #define your_sha256_hash0 0x05f0 #define your_sha256_hash1 0x05f4 #define your_sha256_hash2 0x05f8 #define your_sha256_hash3 0x05fc #define your_sha256_hash4 0x0600 #define your_sha256_hash5 0x0604 #define your_sha256_hash6 0x0608 #define your_sha256_hash7 0x060c #define your_sha256_hash8 0x0610 #define your_sha256_hash0 0x0620 #define your_sha256_hash1 0x0624 #define your_sha256_hash2 0x0628 #define your_sha256_hash3 0x062c #define your_sha256_hash4 0x0630 #define your_sha256_hash5 0x0634 #define your_sha256_hash6 0x0638 #define your_sha256_hash7 0x063c #define your_sha256_hash8 0x0640 #define your_sha256_hashW0 0x0650 #define your_sha256_hashW1 0x0654 #define your_sha256_hashW2 0x0658 #define your_sha256_hashW3 0x065c #define your_sha256_hashW4 0x0660 #define your_sha256_hashW5 0x0664 #define your_sha256_hashW6 0x0668 #define your_sha256_hashW7 0x066c #define your_sha256_hashW8 0x0670 // addressBlock: nbio_nbif0_bif_cfg_dev0_epf1_bifcfgdecp // base address: 0x0 #define cfgBIF_CFG_DEV0_EPF1_0_VENDOR_ID 0x0000 #define cfgBIF_CFG_DEV0_EPF1_0_DEVICE_ID 0x0002 #define cfgBIF_CFG_DEV0_EPF1_0_COMMAND 0x0004 #define cfgBIF_CFG_DEV0_EPF1_0_STATUS 0x0006 #define cfgBIF_CFG_DEV0_EPF1_0_REVISION_ID 0x0008 #define cfgBIF_CFG_DEV0_EPF1_0_PROG_INTERFACE 0x0009 #define cfgBIF_CFG_DEV0_EPF1_0_SUB_CLASS 0x000a #define cfgBIF_CFG_DEV0_EPF1_0_BASE_CLASS 0x000b #define cfgBIF_CFG_DEV0_EPF1_0_CACHE_LINE 0x000c #define cfgBIF_CFG_DEV0_EPF1_0_LATENCY 0x000d #define cfgBIF_CFG_DEV0_EPF1_0_HEADER 0x000e #define cfgBIF_CFG_DEV0_EPF1_0_BIST 0x000f #define cfgBIF_CFG_DEV0_EPF1_0_BASE_ADDR_1 0x0010 #define cfgBIF_CFG_DEV0_EPF1_0_BASE_ADDR_2 0x0014 #define cfgBIF_CFG_DEV0_EPF1_0_BASE_ADDR_3 0x0018 #define cfgBIF_CFG_DEV0_EPF1_0_BASE_ADDR_4 0x001c #define cfgBIF_CFG_DEV0_EPF1_0_BASE_ADDR_5 0x0020 #define cfgBIF_CFG_DEV0_EPF1_0_BASE_ADDR_6 0x0024 #define cfgBIF_CFG_DEV0_EPF1_0_CARDBUS_CIS_PTR 0x0028 #define cfgBIF_CFG_DEV0_EPF1_0_ADAPTER_ID 0x002c #define cfgBIF_CFG_DEV0_EPF1_0_ROM_BASE_ADDR 0x0030 #define cfgBIF_CFG_DEV0_EPF1_0_CAP_PTR 0x0034 #define cfgBIF_CFG_DEV0_EPF1_0_INTERRUPT_LINE 0x003c #define cfgBIF_CFG_DEV0_EPF1_0_INTERRUPT_PIN 0x003d #define cfgBIF_CFG_DEV0_EPF1_0_MIN_GRANT 0x003e #define cfgBIF_CFG_DEV0_EPF1_0_MAX_LATENCY 0x003f #define cfgBIF_CFG_DEV0_EPF1_0_VENDOR_CAP_LIST 0x0048 #define cfgBIF_CFG_DEV0_EPF1_0_ADAPTER_ID_W 0x004c #define cfgBIF_CFG_DEV0_EPF1_0_PMI_CAP_LIST 0x0050 #define cfgBIF_CFG_DEV0_EPF1_0_PMI_CAP 0x0052 #define cfgBIF_CFG_DEV0_EPF1_0_PMI_STATUS_CNTL 0x0054 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_CAP_LIST 0x0064 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_CAP 0x0066 #define cfgBIF_CFG_DEV0_EPF1_0_DEVICE_CAP 0x0068 #define cfgBIF_CFG_DEV0_EPF1_0_DEVICE_CNTL 0x006c #define cfgBIF_CFG_DEV0_EPF1_0_DEVICE_STATUS 0x006e #define cfgBIF_CFG_DEV0_EPF1_0_LINK_CAP 0x0070 #define cfgBIF_CFG_DEV0_EPF1_0_LINK_CNTL 0x0074 #define cfgBIF_CFG_DEV0_EPF1_0_LINK_STATUS 0x0076 #define cfgBIF_CFG_DEV0_EPF1_0_DEVICE_CAP2 0x0088 #define cfgBIF_CFG_DEV0_EPF1_0_DEVICE_CNTL2 0x008c #define cfgBIF_CFG_DEV0_EPF1_0_DEVICE_STATUS2 0x008e #define cfgBIF_CFG_DEV0_EPF1_0_LINK_CAP2 0x0090 #define cfgBIF_CFG_DEV0_EPF1_0_LINK_CNTL2 0x0094 #define cfgBIF_CFG_DEV0_EPF1_0_LINK_STATUS2 0x0096 #define cfgBIF_CFG_DEV0_EPF1_0_MSI_CAP_LIST 0x00a0 #define cfgBIF_CFG_DEV0_EPF1_0_MSI_MSG_CNTL 0x00a2 #define cfgBIF_CFG_DEV0_EPF1_0_MSI_MSG_ADDR_LO 0x00a4 #define cfgBIF_CFG_DEV0_EPF1_0_MSI_MSG_ADDR_HI 0x00a8 #define cfgBIF_CFG_DEV0_EPF1_0_MSI_MSG_DATA 0x00a8 #define cfgBIF_CFG_DEV0_EPF1_0_MSI_MASK 0x00ac #define cfgBIF_CFG_DEV0_EPF1_0_MSI_MSG_DATA_64 0x00ac #define cfgBIF_CFG_DEV0_EPF1_0_MSI_MASK_64 0x00b0 #define cfgBIF_CFG_DEV0_EPF1_0_MSI_PENDING 0x00b0 #define cfgBIF_CFG_DEV0_EPF1_0_MSI_PENDING_64 0x00b4 #define cfgBIF_CFG_DEV0_EPF1_0_MSIX_CAP_LIST 0x00c0 #define cfgBIF_CFG_DEV0_EPF1_0_MSIX_MSG_CNTL 0x00c2 #define cfgBIF_CFG_DEV0_EPF1_0_MSIX_TABLE 0x00c4 #define cfgBIF_CFG_DEV0_EPF1_0_MSIX_PBA 0x00c8 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x0100 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR 0x0104 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC1 0x0108 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC2 0x010c #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VC_ENH_CAP_LIST 0x0110 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_PORT_VC_CAP_REG1 0x0114 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_PORT_VC_CAP_REG2 0x0118 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_PORT_VC_CNTL 0x011c #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_PORT_VC_STATUS 0x011e #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VC0_RESOURCE_CAP 0x0120 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VC0_RESOURCE_CNTL 0x0124 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VC0_RESOURCE_STATUS 0x012a #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VC1_RESOURCE_CAP 0x012c #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VC1_RESOURCE_CNTL 0x0130 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VC1_RESOURCE_STATUS 0x0136 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST 0x0140 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_DEV_SERIAL_NUM_DW1 0x0144 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_DEV_SERIAL_NUM_DW2 0x0148 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x0150 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_STATUS 0x0154 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_MASK 0x0158 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_SEVERITY 0x015c #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_CORR_ERR_STATUS 0x0160 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_CORR_ERR_MASK 0x0164 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_ADV_ERR_CAP_CNTL 0x0168 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_HDR_LOG0 0x016c #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_HDR_LOG1 0x0170 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_HDR_LOG2 0x0174 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_HDR_LOG3 0x0178 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_TLP_PREFIX_LOG0 0x0188 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_TLP_PREFIX_LOG1 0x018c #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_TLP_PREFIX_LOG2 0x0190 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_TLP_PREFIX_LOG3 0x0194 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_BAR_ENH_CAP_LIST 0x0200 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_BAR1_CAP 0x0204 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_BAR1_CNTL 0x0208 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_BAR2_CAP 0x020c #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_BAR2_CNTL 0x0210 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_BAR3_CAP 0x0214 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_BAR3_CNTL 0x0218 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_BAR4_CAP 0x021c #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_BAR4_CNTL 0x0220 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_BAR5_CAP 0x0224 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_BAR5_CNTL 0x0228 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_BAR6_CAP 0x022c #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_BAR6_CNTL 0x0230 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_PWR_BUDGET_ENH_CAP_LIST 0x0240 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_PWR_BUDGET_DATA_SELECT 0x0244 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_PWR_BUDGET_DATA 0x0248 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_PWR_BUDGET_CAP 0x024c #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_DPA_ENH_CAP_LIST 0x0250 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_DPA_CAP 0x0254 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_DPA_LATENCY_INDICATOR 0x0258 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_DPA_STATUS 0x025c #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_DPA_CNTL 0x025e #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_0 0x0260 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_1 0x0261 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_2 0x0262 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_3 0x0263 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_4 0x0264 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_5 0x0265 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_6 0x0266 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_7 0x0267 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_SECONDARY_ENH_CAP_LIST 0x0270 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_LINK_CNTL3 0x0274 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_LANE_ERROR_STATUS 0x0278 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_LANE_0_EQUALIZATION_CNTL 0x027c #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_LANE_1_EQUALIZATION_CNTL 0x027e #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_LANE_2_EQUALIZATION_CNTL 0x0280 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_LANE_3_EQUALIZATION_CNTL 0x0282 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_LANE_4_EQUALIZATION_CNTL 0x0284 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_LANE_5_EQUALIZATION_CNTL 0x0286 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_LANE_6_EQUALIZATION_CNTL 0x0288 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_LANE_7_EQUALIZATION_CNTL 0x028a #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_LANE_8_EQUALIZATION_CNTL 0x028c #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_LANE_9_EQUALIZATION_CNTL 0x028e #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_LANE_10_EQUALIZATION_CNTL 0x0290 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_LANE_11_EQUALIZATION_CNTL 0x0292 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_LANE_12_EQUALIZATION_CNTL 0x0294 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_LANE_13_EQUALIZATION_CNTL 0x0296 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_LANE_14_EQUALIZATION_CNTL 0x0298 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_LANE_15_EQUALIZATION_CNTL 0x029a #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_ACS_ENH_CAP_LIST 0x02a0 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_ACS_CAP 0x02a4 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_ACS_CNTL 0x02a6 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_ATS_ENH_CAP_LIST 0x02b0 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_ATS_CAP 0x02b4 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_ATS_CNTL 0x02b6 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_PAGE_REQ_ENH_CAP_LIST 0x02c0 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_PAGE_REQ_CNTL 0x02c4 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_PAGE_REQ_STATUS 0x02c6 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_OUTSTAND_PAGE_REQ_CAPACITY 0x02c8 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_OUTSTAND_PAGE_REQ_ALLOC 0x02cc #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_PASID_ENH_CAP_LIST 0x02d0 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_PASID_CAP 0x02d4 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_PASID_CNTL 0x02d6 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_MC_ENH_CAP_LIST 0x02f0 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_MC_CAP 0x02f4 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_MC_CNTL 0x02f6 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_MC_ADDR0 0x02f8 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_MC_ADDR1 0x02fc #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_MC_RCV0 0x0300 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_MC_RCV1 0x0304 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_MC_BLOCK_ALL0 0x0308 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_MC_BLOCK_ALL1 0x030c #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_MC_BLOCK_UNTRANSLATED_0 0x0310 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_MC_BLOCK_UNTRANSLATED_1 0x0314 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_LTR_ENH_CAP_LIST 0x0320 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_LTR_CAP 0x0324 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_ARI_ENH_CAP_LIST 0x0328 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_ARI_CAP 0x032c #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_ARI_CNTL 0x032e #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_ENH_CAP_LIST 0x0330 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_CAP 0x0334 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_CONTROL 0x0338 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_STATUS 0x033a #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_INITIAL_VFS 0x033c #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_TOTAL_VFS 0x033e #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_NUM_VFS 0x0340 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_FUNC_DEP_LINK 0x0342 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_FIRST_VF_OFFSET 0x0344 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_VF_STRIDE 0x0346 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_VF_DEVICE_ID 0x034a #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_SUPPORTED_PAGE_SIZE 0x034c #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_SYSTEM_PAGE_SIZE 0x0350 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_VF_BASE_ADDR_0 0x0354 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_VF_BASE_ADDR_1 0x0358 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_VF_BASE_ADDR_2 0x035c #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_VF_BASE_ADDR_3 0x0360 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_VF_BASE_ADDR_4 0x0364 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_VF_BASE_ADDR_5 0x0368 #define your_sha256_hashT 0x036c #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_TPH_REQR_ENH_CAP_LIST 0x0370 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_TPH_REQR_CAP 0x0374 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_TPH_REQR_CNTL 0x0378 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_DLF_ENH_CAP_LIST 0x0400 #define cfgBIF_CFG_DEV0_EPF1_0_DATA_LINK_FEATURE_CAP 0x0404 #define cfgBIF_CFG_DEV0_EPF1_0_DATA_LINK_FEATURE_STATUS 0x0408 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_PHY_16GT_ENH_CAP_LIST 0x0410 #define cfgBIF_CFG_DEV0_EPF1_0_LINK_CAP_16GT 0x0414 #define cfgBIF_CFG_DEV0_EPF1_0_LINK_CNTL_16GT 0x0418 #define cfgBIF_CFG_DEV0_EPF1_0_LINK_STATUS_16GT 0x041c #define cfgBIF_CFG_DEV0_EPF1_0_LOCAL_PARITY_MISMATCH_STATUS_16GT 0x0420 #define cfgBIF_CFG_DEV0_EPF1_0_RTM1_PARITY_MISMATCH_STATUS_16GT 0x0424 #define cfgBIF_CFG_DEV0_EPF1_0_RTM2_PARITY_MISMATCH_STATUS_16GT 0x0428 #define cfgBIF_CFG_DEV0_EPF1_0_LANE_0_EQUALIZATION_CNTL_16GT 0x0430 #define cfgBIF_CFG_DEV0_EPF1_0_LANE_1_EQUALIZATION_CNTL_16GT 0x0431 #define cfgBIF_CFG_DEV0_EPF1_0_LANE_2_EQUALIZATION_CNTL_16GT 0x0432 #define cfgBIF_CFG_DEV0_EPF1_0_LANE_3_EQUALIZATION_CNTL_16GT 0x0433 #define cfgBIF_CFG_DEV0_EPF1_0_LANE_4_EQUALIZATION_CNTL_16GT 0x0434 #define cfgBIF_CFG_DEV0_EPF1_0_LANE_5_EQUALIZATION_CNTL_16GT 0x0435 #define cfgBIF_CFG_DEV0_EPF1_0_LANE_6_EQUALIZATION_CNTL_16GT 0x0436 #define cfgBIF_CFG_DEV0_EPF1_0_LANE_7_EQUALIZATION_CNTL_16GT 0x0437 #define cfgBIF_CFG_DEV0_EPF1_0_LANE_8_EQUALIZATION_CNTL_16GT 0x0438 #define cfgBIF_CFG_DEV0_EPF1_0_LANE_9_EQUALIZATION_CNTL_16GT 0x0439 #define cfgBIF_CFG_DEV0_EPF1_0_LANE_10_EQUALIZATION_CNTL_16GT 0x043a #define cfgBIF_CFG_DEV0_EPF1_0_LANE_11_EQUALIZATION_CNTL_16GT 0x043b #define cfgBIF_CFG_DEV0_EPF1_0_LANE_12_EQUALIZATION_CNTL_16GT 0x043c #define cfgBIF_CFG_DEV0_EPF1_0_LANE_13_EQUALIZATION_CNTL_16GT 0x043d #define cfgBIF_CFG_DEV0_EPF1_0_LANE_14_EQUALIZATION_CNTL_16GT 0x043e #define cfgBIF_CFG_DEV0_EPF1_0_LANE_15_EQUALIZATION_CNTL_16GT 0x043f #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_MARGINING_ENH_CAP_LIST 0x0440 #define cfgBIF_CFG_DEV0_EPF1_0_MARGINING_PORT_CAP 0x0444 #define cfgBIF_CFG_DEV0_EPF1_0_MARGINING_PORT_STATUS 0x0446 #define cfgBIF_CFG_DEV0_EPF1_0_LANE_0_MARGINING_LANE_CNTL 0x0448 #define cfgBIF_CFG_DEV0_EPF1_0_LANE_0_MARGINING_LANE_STATUS 0x044a #define cfgBIF_CFG_DEV0_EPF1_0_LANE_1_MARGINING_LANE_CNTL 0x044c #define cfgBIF_CFG_DEV0_EPF1_0_LANE_1_MARGINING_LANE_STATUS 0x044e #define cfgBIF_CFG_DEV0_EPF1_0_LANE_2_MARGINING_LANE_CNTL 0x0450 #define cfgBIF_CFG_DEV0_EPF1_0_LANE_2_MARGINING_LANE_STATUS 0x0452 #define cfgBIF_CFG_DEV0_EPF1_0_LANE_3_MARGINING_LANE_CNTL 0x0454 #define cfgBIF_CFG_DEV0_EPF1_0_LANE_3_MARGINING_LANE_STATUS 0x0456 #define cfgBIF_CFG_DEV0_EPF1_0_LANE_4_MARGINING_LANE_CNTL 0x0458 #define cfgBIF_CFG_DEV0_EPF1_0_LANE_4_MARGINING_LANE_STATUS 0x045a #define cfgBIF_CFG_DEV0_EPF1_0_LANE_5_MARGINING_LANE_CNTL 0x045c #define cfgBIF_CFG_DEV0_EPF1_0_LANE_5_MARGINING_LANE_STATUS 0x045e #define cfgBIF_CFG_DEV0_EPF1_0_LANE_6_MARGINING_LANE_CNTL 0x0460 #define cfgBIF_CFG_DEV0_EPF1_0_LANE_6_MARGINING_LANE_STATUS 0x0462 #define cfgBIF_CFG_DEV0_EPF1_0_LANE_7_MARGINING_LANE_CNTL 0x0464 #define cfgBIF_CFG_DEV0_EPF1_0_LANE_7_MARGINING_LANE_STATUS 0x0466 #define cfgBIF_CFG_DEV0_EPF1_0_LANE_8_MARGINING_LANE_CNTL 0x0468 #define cfgBIF_CFG_DEV0_EPF1_0_LANE_8_MARGINING_LANE_STATUS 0x046a #define cfgBIF_CFG_DEV0_EPF1_0_LANE_9_MARGINING_LANE_CNTL 0x046c #define cfgBIF_CFG_DEV0_EPF1_0_LANE_9_MARGINING_LANE_STATUS 0x046e #define cfgBIF_CFG_DEV0_EPF1_0_LANE_10_MARGINING_LANE_CNTL 0x0470 #define cfgBIF_CFG_DEV0_EPF1_0_LANE_10_MARGINING_LANE_STATUS 0x0472 #define cfgBIF_CFG_DEV0_EPF1_0_LANE_11_MARGINING_LANE_CNTL 0x0474 #define cfgBIF_CFG_DEV0_EPF1_0_LANE_11_MARGINING_LANE_STATUS 0x0476 #define cfgBIF_CFG_DEV0_EPF1_0_LANE_12_MARGINING_LANE_CNTL 0x0478 #define cfgBIF_CFG_DEV0_EPF1_0_LANE_12_MARGINING_LANE_STATUS 0x047a #define cfgBIF_CFG_DEV0_EPF1_0_LANE_13_MARGINING_LANE_CNTL 0x047c #define cfgBIF_CFG_DEV0_EPF1_0_LANE_13_MARGINING_LANE_STATUS 0x047e #define cfgBIF_CFG_DEV0_EPF1_0_LANE_14_MARGINING_LANE_CNTL 0x0480 #define cfgBIF_CFG_DEV0_EPF1_0_LANE_14_MARGINING_LANE_STATUS 0x0482 #define cfgBIF_CFG_DEV0_EPF1_0_LANE_15_MARGINING_LANE_CNTL 0x0484 #define cfgBIF_CFG_DEV0_EPF1_0_LANE_15_MARGINING_LANE_STATUS 0x0486 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR_ENH_CAP_LIST 0x04c0 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR1_CAP 0x04c4 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR1_CNTL 0x04c8 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR2_CAP 0x04cc #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR2_CNTL 0x04d0 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR3_CAP 0x04d4 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR3_CNTL 0x04d8 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR4_CAP 0x04dc #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR4_CNTL 0x04e0 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR5_CAP 0x04e4 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR5_CNTL 0x04e8 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR6_CAP 0x04ec #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VF_RESIZE_BAR6_CNTL 0x04f0 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV 0x0500 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV 0x0504 #define your_sha256_hashDOW 0x0508 #define your_sha256_hashLE 0x050c #define your_sha256_hashUS 0x0510 #define your_sha256_hashTROL 0x0514 #define your_sha256_hash_DW0 0x0518 #define your_sha256_hash_DW1 0x051c #define your_sha256_hash_DW2 0x0520 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CONTEXT 0x0524 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_TOTAL_FB 0x0528 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS 0x052c #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_REGION 0x0530 #define your_sha256_hashXGMI_ENABLE 0x0534 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF0_FB 0x0538 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF1_FB 0x053c #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF2_FB 0x0540 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF3_FB 0x0544 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF4_FB 0x0548 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF5_FB 0x054c #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF6_FB 0x0550 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF7_FB 0x0554 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF8_FB 0x0558 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF9_FB 0x055c #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF10_FB 0x0560 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF11_FB 0x0564 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF12_FB 0x0568 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF13_FB 0x056c #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF14_FB 0x0570 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF15_FB 0x0574 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF16_FB 0x0578 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF17_FB 0x057c #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF18_FB 0x0580 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF19_FB 0x0584 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF20_FB 0x0588 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF21_FB 0x058c #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF22_FB 0x0590 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF23_FB 0x0594 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF24_FB 0x0598 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF25_FB 0x059c #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF26_FB 0x05a0 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF27_FB 0x05a4 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF28_FB 0x05a8 #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF29_FB 0x05ac #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF30_FB 0x05b0 #define your_sha256_hash0 0x05c0 #define your_sha256_hash1 0x05c4 #define your_sha256_hash2 0x05c8 #define your_sha256_hash3 0x05cc #define your_sha256_hash4 0x05d0 #define your_sha256_hash5 0x05d4 #define your_sha256_hash6 0x05d8 #define your_sha256_hash7 0x05dc #define your_sha256_hash8 0x05e0 #define your_sha256_hash0 0x05f0 #define your_sha256_hash1 0x05f4 #define your_sha256_hash2 0x05f8 #define your_sha256_hash3 0x05fc #define your_sha256_hash4 0x0600 #define your_sha256_hash5 0x0604 #define your_sha256_hash6 0x0608 #define your_sha256_hash7 0x060c #define your_sha256_hash8 0x0610 #define your_sha256_hash0 0x0620 #define your_sha256_hash1 0x0624 #define your_sha256_hash2 0x0628 #define your_sha256_hash3 0x062c #define your_sha256_hash4 0x0630 #define your_sha256_hash5 0x0634 #define your_sha256_hash6 0x0638 #define your_sha256_hash7 0x063c #define your_sha256_hash8 0x0640 #define your_sha256_hashW0 0x0650 #define your_sha256_hashW1 0x0654 #define your_sha256_hashW2 0x0658 #define your_sha256_hashW3 0x065c #define your_sha256_hashW4 0x0660 #define your_sha256_hashW5 0x0664 #define your_sha256_hashW6 0x0668 #define your_sha256_hashW7 0x066c #define your_sha256_hashW8 0x0670 // addressBlock: nbio_nbif0_bif_cfg_dev0_epf2_bifcfgdecp // base address: 0x0 #define cfgBIF_CFG_DEV0_EPF2_0_VENDOR_ID 0x0000 #define cfgBIF_CFG_DEV0_EPF2_0_DEVICE_ID 0x0002 #define cfgBIF_CFG_DEV0_EPF2_0_COMMAND 0x0004 #define cfgBIF_CFG_DEV0_EPF2_0_STATUS 0x0006 #define cfgBIF_CFG_DEV0_EPF2_0_REVISION_ID 0x0008 #define cfgBIF_CFG_DEV0_EPF2_0_PROG_INTERFACE 0x0009 #define cfgBIF_CFG_DEV0_EPF2_0_SUB_CLASS 0x000a #define cfgBIF_CFG_DEV0_EPF2_0_BASE_CLASS 0x000b #define cfgBIF_CFG_DEV0_EPF2_0_CACHE_LINE 0x000c #define cfgBIF_CFG_DEV0_EPF2_0_LATENCY 0x000d #define cfgBIF_CFG_DEV0_EPF2_0_HEADER 0x000e #define cfgBIF_CFG_DEV0_EPF2_0_BIST 0x000f #define cfgBIF_CFG_DEV0_EPF2_0_BASE_ADDR_1 0x0010 #define cfgBIF_CFG_DEV0_EPF2_0_BASE_ADDR_2 0x0014 #define cfgBIF_CFG_DEV0_EPF2_0_BASE_ADDR_3 0x0018 #define cfgBIF_CFG_DEV0_EPF2_0_BASE_ADDR_4 0x001c #define cfgBIF_CFG_DEV0_EPF2_0_BASE_ADDR_5 0x0020 #define cfgBIF_CFG_DEV0_EPF2_0_BASE_ADDR_6 0x0024 #define cfgBIF_CFG_DEV0_EPF2_0_CARDBUS_CIS_PTR 0x0028 #define cfgBIF_CFG_DEV0_EPF2_0_ADAPTER_ID 0x002c #define cfgBIF_CFG_DEV0_EPF2_0_ROM_BASE_ADDR 0x0030 #define cfgBIF_CFG_DEV0_EPF2_0_CAP_PTR 0x0034 #define cfgBIF_CFG_DEV0_EPF2_0_INTERRUPT_LINE 0x003c #define cfgBIF_CFG_DEV0_EPF2_0_INTERRUPT_PIN 0x003d #define cfgBIF_CFG_DEV0_EPF2_0_MIN_GRANT 0x003e #define cfgBIF_CFG_DEV0_EPF2_0_MAX_LATENCY 0x003f #define cfgBIF_CFG_DEV0_EPF2_0_VENDOR_CAP_LIST 0x0048 #define cfgBIF_CFG_DEV0_EPF2_0_ADAPTER_ID_W 0x004c #define cfgBIF_CFG_DEV0_EPF2_0_PMI_CAP_LIST 0x0050 #define cfgBIF_CFG_DEV0_EPF2_0_PMI_CAP 0x0052 #define cfgBIF_CFG_DEV0_EPF2_0_PMI_STATUS_CNTL 0x0054 #define cfgBIF_CFG_DEV0_EPF2_0_SBRN 0x0060 #define cfgBIF_CFG_DEV0_EPF2_0_FLADJ 0x0061 #define cfgBIF_CFG_DEV0_EPF2_0_DBESL_DBESLD 0x0062 #define cfgBIF_CFG_DEV0_EPF2_0_PCIE_CAP_LIST 0x0064 #define cfgBIF_CFG_DEV0_EPF2_0_PCIE_CAP 0x0066 #define cfgBIF_CFG_DEV0_EPF2_0_DEVICE_CAP 0x0068 #define cfgBIF_CFG_DEV0_EPF2_0_DEVICE_CNTL 0x006c #define cfgBIF_CFG_DEV0_EPF2_0_DEVICE_STATUS 0x006e #define cfgBIF_CFG_DEV0_EPF2_0_LINK_CAP 0x0070 #define cfgBIF_CFG_DEV0_EPF2_0_LINK_CNTL 0x0074 #define cfgBIF_CFG_DEV0_EPF2_0_LINK_STATUS 0x0076 #define cfgBIF_CFG_DEV0_EPF2_0_DEVICE_CAP2 0x0088 #define cfgBIF_CFG_DEV0_EPF2_0_DEVICE_CNTL2 0x008c #define cfgBIF_CFG_DEV0_EPF2_0_DEVICE_STATUS2 0x008e #define cfgBIF_CFG_DEV0_EPF2_0_LINK_CAP2 0x0090 #define cfgBIF_CFG_DEV0_EPF2_0_LINK_CNTL2 0x0094 #define cfgBIF_CFG_DEV0_EPF2_0_LINK_STATUS2 0x0096 #define cfgBIF_CFG_DEV0_EPF2_0_MSI_CAP_LIST 0x00a0 #define cfgBIF_CFG_DEV0_EPF2_0_MSI_MSG_CNTL 0x00a2 #define cfgBIF_CFG_DEV0_EPF2_0_MSI_MSG_ADDR_LO 0x00a4 #define cfgBIF_CFG_DEV0_EPF2_0_MSI_MSG_ADDR_HI 0x00a8 #define cfgBIF_CFG_DEV0_EPF2_0_MSI_MSG_DATA 0x00a8 #define cfgBIF_CFG_DEV0_EPF2_0_MSI_MASK 0x00ac #define cfgBIF_CFG_DEV0_EPF2_0_MSI_MSG_DATA_64 0x00ac #define cfgBIF_CFG_DEV0_EPF2_0_MSI_MASK_64 0x00b0 #define cfgBIF_CFG_DEV0_EPF2_0_MSI_PENDING 0x00b0 #define cfgBIF_CFG_DEV0_EPF2_0_MSI_PENDING_64 0x00b4 #define cfgBIF_CFG_DEV0_EPF2_0_MSIX_CAP_LIST 0x00c0 #define cfgBIF_CFG_DEV0_EPF2_0_MSIX_MSG_CNTL 0x00c2 #define cfgBIF_CFG_DEV0_EPF2_0_MSIX_TABLE 0x00c4 #define cfgBIF_CFG_DEV0_EPF2_0_MSIX_PBA 0x00c8 #define cfgBIF_CFG_DEV0_EPF2_0_SATA_CAP_0 0x00d0 #define cfgBIF_CFG_DEV0_EPF2_0_SATA_CAP_1 0x00d4 #define cfgBIF_CFG_DEV0_EPF2_0_SATA_IDP_INDEX 0x00d8 #define cfgBIF_CFG_DEV0_EPF2_0_SATA_IDP_DATA 0x00dc #define cfgBIF_CFG_DEV0_EPF2_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x0100 #define cfgBIF_CFG_DEV0_EPF2_0_PCIE_VENDOR_SPECIFIC_HDR 0x0104 #define cfgBIF_CFG_DEV0_EPF2_0_PCIE_VENDOR_SPECIFIC1 0x0108 #define cfgBIF_CFG_DEV0_EPF2_0_PCIE_VENDOR_SPECIFIC2 0x010c #define cfgBIF_CFG_DEV0_EPF2_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x0150 #define cfgBIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_STATUS 0x0154 #define cfgBIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_MASK 0x0158 #define cfgBIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_SEVERITY 0x015c #define cfgBIF_CFG_DEV0_EPF2_0_PCIE_CORR_ERR_STATUS 0x0160 #define cfgBIF_CFG_DEV0_EPF2_0_PCIE_CORR_ERR_MASK 0x0164 #define cfgBIF_CFG_DEV0_EPF2_0_PCIE_ADV_ERR_CAP_CNTL 0x0168 #define cfgBIF_CFG_DEV0_EPF2_0_PCIE_HDR_LOG0 0x016c #define cfgBIF_CFG_DEV0_EPF2_0_PCIE_HDR_LOG1 0x0170 #define cfgBIF_CFG_DEV0_EPF2_0_PCIE_HDR_LOG2 0x0174 #define cfgBIF_CFG_DEV0_EPF2_0_PCIE_HDR_LOG3 0x0178 #define cfgBIF_CFG_DEV0_EPF2_0_PCIE_TLP_PREFIX_LOG0 0x0188 #define cfgBIF_CFG_DEV0_EPF2_0_PCIE_TLP_PREFIX_LOG1 0x018c #define cfgBIF_CFG_DEV0_EPF2_0_PCIE_TLP_PREFIX_LOG2 0x0190 #define cfgBIF_CFG_DEV0_EPF2_0_PCIE_TLP_PREFIX_LOG3 0x0194 #define cfgBIF_CFG_DEV0_EPF2_0_PCIE_BAR_ENH_CAP_LIST 0x0200 #define cfgBIF_CFG_DEV0_EPF2_0_PCIE_BAR1_CAP 0x0204 #define cfgBIF_CFG_DEV0_EPF2_0_PCIE_BAR1_CNTL 0x0208 #define cfgBIF_CFG_DEV0_EPF2_0_PCIE_BAR2_CAP 0x020c #define cfgBIF_CFG_DEV0_EPF2_0_PCIE_BAR2_CNTL 0x0210 #define cfgBIF_CFG_DEV0_EPF2_0_PCIE_BAR3_CAP 0x0214 #define cfgBIF_CFG_DEV0_EPF2_0_PCIE_BAR3_CNTL 0x0218 #define cfgBIF_CFG_DEV0_EPF2_0_PCIE_BAR4_CAP 0x021c #define cfgBIF_CFG_DEV0_EPF2_0_PCIE_BAR4_CNTL 0x0220 #define cfgBIF_CFG_DEV0_EPF2_0_PCIE_BAR5_CAP 0x0224 #define cfgBIF_CFG_DEV0_EPF2_0_PCIE_BAR5_CNTL 0x0228 #define cfgBIF_CFG_DEV0_EPF2_0_PCIE_BAR6_CAP 0x022c #define cfgBIF_CFG_DEV0_EPF2_0_PCIE_BAR6_CNTL 0x0230 #define cfgBIF_CFG_DEV0_EPF2_0_PCIE_PWR_BUDGET_ENH_CAP_LIST 0x0240 #define cfgBIF_CFG_DEV0_EPF2_0_PCIE_PWR_BUDGET_DATA_SELECT 0x0244 #define cfgBIF_CFG_DEV0_EPF2_0_PCIE_PWR_BUDGET_DATA 0x0248 #define cfgBIF_CFG_DEV0_EPF2_0_PCIE_PWR_BUDGET_CAP 0x024c #define cfgBIF_CFG_DEV0_EPF2_0_PCIE_DPA_ENH_CAP_LIST 0x0250 #define cfgBIF_CFG_DEV0_EPF2_0_PCIE_DPA_CAP 0x0254 #define cfgBIF_CFG_DEV0_EPF2_0_PCIE_DPA_LATENCY_INDICATOR 0x0258 #define cfgBIF_CFG_DEV0_EPF2_0_PCIE_DPA_STATUS 0x025c #define cfgBIF_CFG_DEV0_EPF2_0_PCIE_DPA_CNTL 0x025e #define cfgBIF_CFG_DEV0_EPF2_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_0 0x0260 #define cfgBIF_CFG_DEV0_EPF2_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_1 0x0261 #define cfgBIF_CFG_DEV0_EPF2_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_2 0x0262 #define cfgBIF_CFG_DEV0_EPF2_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_3 0x0263 #define cfgBIF_CFG_DEV0_EPF2_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_4 0x0264 #define cfgBIF_CFG_DEV0_EPF2_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_5 0x0265 #define cfgBIF_CFG_DEV0_EPF2_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_6 0x0266 #define cfgBIF_CFG_DEV0_EPF2_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_7 0x0267 #define cfgBIF_CFG_DEV0_EPF2_0_PCIE_ACS_ENH_CAP_LIST 0x02a0 #define cfgBIF_CFG_DEV0_EPF2_0_PCIE_ACS_CAP 0x02a4 #define cfgBIF_CFG_DEV0_EPF2_0_PCIE_ACS_CNTL 0x02a6 #define cfgBIF_CFG_DEV0_EPF2_0_PCIE_PASID_ENH_CAP_LIST 0x02d0 #define cfgBIF_CFG_DEV0_EPF2_0_PCIE_PASID_CAP 0x02d4 #define cfgBIF_CFG_DEV0_EPF2_0_PCIE_PASID_CNTL 0x02d6 #define cfgBIF_CFG_DEV0_EPF2_0_PCIE_ARI_ENH_CAP_LIST 0x0328 #define cfgBIF_CFG_DEV0_EPF2_0_PCIE_ARI_CAP 0x032c #define cfgBIF_CFG_DEV0_EPF2_0_PCIE_ARI_CNTL 0x032e #define cfgBIF_CFG_DEV0_EPF2_0_PCIE_TPH_REQR_ENH_CAP_LIST 0x0370 #define cfgBIF_CFG_DEV0_EPF2_0_PCIE_TPH_REQR_CAP 0x0374 #define cfgBIF_CFG_DEV0_EPF2_0_PCIE_TPH_REQR_CNTL 0x0378 #define cfgBIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_0 0x037c #define cfgBIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_1 0x037e #define cfgBIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_2 0x0380 #define cfgBIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_3 0x0382 #define cfgBIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_4 0x0384 #define cfgBIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_5 0x0386 #define cfgBIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_6 0x0388 #define cfgBIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_7 0x038a #define cfgBIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_8 0x038c #define cfgBIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_9 0x038e #define cfgBIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_10 0x0390 #define cfgBIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_11 0x0392 #define cfgBIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_12 0x0394 #define cfgBIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_13 0x0396 #define cfgBIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_14 0x0398 #define cfgBIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_15 0x039a #define cfgBIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_16 0x039c #define cfgBIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_17 0x039e #define cfgBIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_18 0x03a0 #define cfgBIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_19 0x03a2 #define cfgBIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_20 0x03a4 #define cfgBIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_21 0x03a6 #define cfgBIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_22 0x03a8 #define cfgBIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_23 0x03aa #define cfgBIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_24 0x03ac #define cfgBIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_25 0x03ae #define cfgBIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_26 0x03b0 #define cfgBIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_27 0x03b2 #define cfgBIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_28 0x03b4 #define cfgBIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_29 0x03b6 #define cfgBIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_30 0x03b8 #define cfgBIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_31 0x03ba #define cfgBIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_32 0x03bc #define cfgBIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_33 0x03be #define cfgBIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_34 0x03c0 #define cfgBIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_35 0x03c2 #define cfgBIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_36 0x03c4 #define cfgBIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_37 0x03c6 #define cfgBIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_38 0x03c8 #define cfgBIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_39 0x03ca #define cfgBIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_40 0x03cc #define cfgBIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_41 0x03ce #define cfgBIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_42 0x03d0 #define cfgBIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_43 0x03d2 #define cfgBIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_44 0x03d4 #define cfgBIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_45 0x03d6 #define cfgBIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_46 0x03d8 #define cfgBIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_47 0x03da #define cfgBIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_48 0x03dc #define cfgBIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_49 0x03de #define cfgBIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_50 0x03e0 #define cfgBIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_51 0x03e2 #define cfgBIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_52 0x03e4 #define cfgBIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_53 0x03e6 #define cfgBIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_54 0x03e8 #define cfgBIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_55 0x03ea #define cfgBIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_56 0x03ec #define cfgBIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_57 0x03ee #define cfgBIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_58 0x03f0 #define cfgBIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_59 0x03f2 #define cfgBIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_60 0x03f4 #define cfgBIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_61 0x03f6 #define cfgBIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_62 0x03f8 #define cfgBIF_CFG_DEV0_EPF2_0_PCIE_TPH_ST_TABLE_63 0x03fa // addressBlock: nbio_nbif0_bif_cfg_dev0_epf3_bifcfgdecp // base address: 0x0 #define cfgBIF_CFG_DEV0_EPF3_0_VENDOR_ID 0x0000 #define cfgBIF_CFG_DEV0_EPF3_0_DEVICE_ID 0x0002 #define cfgBIF_CFG_DEV0_EPF3_0_COMMAND 0x0004 #define cfgBIF_CFG_DEV0_EPF3_0_STATUS 0x0006 #define cfgBIF_CFG_DEV0_EPF3_0_REVISION_ID 0x0008 #define cfgBIF_CFG_DEV0_EPF3_0_PROG_INTERFACE 0x0009 #define cfgBIF_CFG_DEV0_EPF3_0_SUB_CLASS 0x000a #define cfgBIF_CFG_DEV0_EPF3_0_BASE_CLASS 0x000b #define cfgBIF_CFG_DEV0_EPF3_0_CACHE_LINE 0x000c #define cfgBIF_CFG_DEV0_EPF3_0_LATENCY 0x000d #define cfgBIF_CFG_DEV0_EPF3_0_HEADER 0x000e #define cfgBIF_CFG_DEV0_EPF3_0_BIST 0x000f #define cfgBIF_CFG_DEV0_EPF3_0_BASE_ADDR_1 0x0010 #define cfgBIF_CFG_DEV0_EPF3_0_BASE_ADDR_2 0x0014 #define cfgBIF_CFG_DEV0_EPF3_0_BASE_ADDR_3 0x0018 #define cfgBIF_CFG_DEV0_EPF3_0_BASE_ADDR_4 0x001c #define cfgBIF_CFG_DEV0_EPF3_0_BASE_ADDR_5 0x0020 #define cfgBIF_CFG_DEV0_EPF3_0_BASE_ADDR_6 0x0024 #define cfgBIF_CFG_DEV0_EPF3_0_CARDBUS_CIS_PTR 0x0028 #define cfgBIF_CFG_DEV0_EPF3_0_ADAPTER_ID 0x002c #define cfgBIF_CFG_DEV0_EPF3_0_ROM_BASE_ADDR 0x0030 #define cfgBIF_CFG_DEV0_EPF3_0_CAP_PTR 0x0034 #define cfgBIF_CFG_DEV0_EPF3_0_INTERRUPT_LINE 0x003c #define cfgBIF_CFG_DEV0_EPF3_0_INTERRUPT_PIN 0x003d #define cfgBIF_CFG_DEV0_EPF3_0_MIN_GRANT 0x003e #define cfgBIF_CFG_DEV0_EPF3_0_MAX_LATENCY 0x003f #define cfgBIF_CFG_DEV0_EPF3_0_VENDOR_CAP_LIST 0x0048 #define cfgBIF_CFG_DEV0_EPF3_0_ADAPTER_ID_W 0x004c #define cfgBIF_CFG_DEV0_EPF3_0_PMI_CAP_LIST 0x0050 #define cfgBIF_CFG_DEV0_EPF3_0_PMI_CAP 0x0052 #define cfgBIF_CFG_DEV0_EPF3_0_PMI_STATUS_CNTL 0x0054 #define cfgBIF_CFG_DEV0_EPF3_0_SBRN 0x0060 #define cfgBIF_CFG_DEV0_EPF3_0_FLADJ 0x0061 #define cfgBIF_CFG_DEV0_EPF3_0_DBESL_DBESLD 0x0062 #define cfgBIF_CFG_DEV0_EPF3_0_PCIE_CAP_LIST 0x0064 #define cfgBIF_CFG_DEV0_EPF3_0_PCIE_CAP 0x0066 #define cfgBIF_CFG_DEV0_EPF3_0_DEVICE_CAP 0x0068 #define cfgBIF_CFG_DEV0_EPF3_0_DEVICE_CNTL 0x006c #define cfgBIF_CFG_DEV0_EPF3_0_DEVICE_STATUS 0x006e #define cfgBIF_CFG_DEV0_EPF3_0_LINK_CAP 0x0070 #define cfgBIF_CFG_DEV0_EPF3_0_LINK_CNTL 0x0074 #define cfgBIF_CFG_DEV0_EPF3_0_LINK_STATUS 0x0076 #define cfgBIF_CFG_DEV0_EPF3_0_DEVICE_CAP2 0x0088 #define cfgBIF_CFG_DEV0_EPF3_0_DEVICE_CNTL2 0x008c #define cfgBIF_CFG_DEV0_EPF3_0_DEVICE_STATUS2 0x008e #define cfgBIF_CFG_DEV0_EPF3_0_LINK_CAP2 0x0090 #define cfgBIF_CFG_DEV0_EPF3_0_LINK_CNTL2 0x0094 #define cfgBIF_CFG_DEV0_EPF3_0_LINK_STATUS2 0x0096 #define cfgBIF_CFG_DEV0_EPF3_0_MSI_CAP_LIST 0x00a0 #define cfgBIF_CFG_DEV0_EPF3_0_MSI_MSG_CNTL 0x00a2 #define cfgBIF_CFG_DEV0_EPF3_0_MSI_MSG_ADDR_LO 0x00a4 #define cfgBIF_CFG_DEV0_EPF3_0_MSI_MSG_ADDR_HI 0x00a8 #define cfgBIF_CFG_DEV0_EPF3_0_MSI_MSG_DATA 0x00a8 #define cfgBIF_CFG_DEV0_EPF3_0_MSI_MASK 0x00ac #define cfgBIF_CFG_DEV0_EPF3_0_MSI_MSG_DATA_64 0x00ac #define cfgBIF_CFG_DEV0_EPF3_0_MSI_MASK_64 0x00b0 #define cfgBIF_CFG_DEV0_EPF3_0_MSI_PENDING 0x00b0 #define cfgBIF_CFG_DEV0_EPF3_0_MSI_PENDING_64 0x00b4 #define cfgBIF_CFG_DEV0_EPF3_0_MSIX_CAP_LIST 0x00c0 #define cfgBIF_CFG_DEV0_EPF3_0_MSIX_MSG_CNTL 0x00c2 #define cfgBIF_CFG_DEV0_EPF3_0_MSIX_TABLE 0x00c4 #define cfgBIF_CFG_DEV0_EPF3_0_MSIX_PBA 0x00c8 #define cfgBIF_CFG_DEV0_EPF3_0_SATA_CAP_0 0x00d0 #define cfgBIF_CFG_DEV0_EPF3_0_SATA_CAP_1 0x00d4 #define cfgBIF_CFG_DEV0_EPF3_0_SATA_IDP_INDEX 0x00d8 #define cfgBIF_CFG_DEV0_EPF3_0_SATA_IDP_DATA 0x00dc #define cfgBIF_CFG_DEV0_EPF3_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x0100 #define cfgBIF_CFG_DEV0_EPF3_0_PCIE_VENDOR_SPECIFIC_HDR 0x0104 #define cfgBIF_CFG_DEV0_EPF3_0_PCIE_VENDOR_SPECIFIC1 0x0108 #define cfgBIF_CFG_DEV0_EPF3_0_PCIE_VENDOR_SPECIFIC2 0x010c #define cfgBIF_CFG_DEV0_EPF3_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x0150 #define cfgBIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_STATUS 0x0154 #define cfgBIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_MASK 0x0158 #define cfgBIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_SEVERITY 0x015c #define cfgBIF_CFG_DEV0_EPF3_0_PCIE_CORR_ERR_STATUS 0x0160 #define cfgBIF_CFG_DEV0_EPF3_0_PCIE_CORR_ERR_MASK 0x0164 #define cfgBIF_CFG_DEV0_EPF3_0_PCIE_ADV_ERR_CAP_CNTL 0x0168 #define cfgBIF_CFG_DEV0_EPF3_0_PCIE_HDR_LOG0 0x016c #define cfgBIF_CFG_DEV0_EPF3_0_PCIE_HDR_LOG1 0x0170 #define cfgBIF_CFG_DEV0_EPF3_0_PCIE_HDR_LOG2 0x0174 #define cfgBIF_CFG_DEV0_EPF3_0_PCIE_HDR_LOG3 0x0178 #define cfgBIF_CFG_DEV0_EPF3_0_PCIE_TLP_PREFIX_LOG0 0x0188 #define cfgBIF_CFG_DEV0_EPF3_0_PCIE_TLP_PREFIX_LOG1 0x018c #define cfgBIF_CFG_DEV0_EPF3_0_PCIE_TLP_PREFIX_LOG2 0x0190 #define cfgBIF_CFG_DEV0_EPF3_0_PCIE_TLP_PREFIX_LOG3 0x0194 #define cfgBIF_CFG_DEV0_EPF3_0_PCIE_BAR_ENH_CAP_LIST 0x0200 #define cfgBIF_CFG_DEV0_EPF3_0_PCIE_BAR1_CAP 0x0204 #define cfgBIF_CFG_DEV0_EPF3_0_PCIE_BAR1_CNTL 0x0208 #define cfgBIF_CFG_DEV0_EPF3_0_PCIE_BAR2_CAP 0x020c #define cfgBIF_CFG_DEV0_EPF3_0_PCIE_BAR2_CNTL 0x0210 #define cfgBIF_CFG_DEV0_EPF3_0_PCIE_BAR3_CAP 0x0214 #define cfgBIF_CFG_DEV0_EPF3_0_PCIE_BAR3_CNTL 0x0218 #define cfgBIF_CFG_DEV0_EPF3_0_PCIE_BAR4_CAP 0x021c #define cfgBIF_CFG_DEV0_EPF3_0_PCIE_BAR4_CNTL 0x0220 #define cfgBIF_CFG_DEV0_EPF3_0_PCIE_BAR5_CAP 0x0224 #define cfgBIF_CFG_DEV0_EPF3_0_PCIE_BAR5_CNTL 0x0228 #define cfgBIF_CFG_DEV0_EPF3_0_PCIE_BAR6_CAP 0x022c #define cfgBIF_CFG_DEV0_EPF3_0_PCIE_BAR6_CNTL 0x0230 #define cfgBIF_CFG_DEV0_EPF3_0_PCIE_PWR_BUDGET_ENH_CAP_LIST 0x0240 #define cfgBIF_CFG_DEV0_EPF3_0_PCIE_PWR_BUDGET_DATA_SELECT 0x0244 #define cfgBIF_CFG_DEV0_EPF3_0_PCIE_PWR_BUDGET_DATA 0x0248 #define cfgBIF_CFG_DEV0_EPF3_0_PCIE_PWR_BUDGET_CAP 0x024c #define cfgBIF_CFG_DEV0_EPF3_0_PCIE_DPA_ENH_CAP_LIST 0x0250 #define cfgBIF_CFG_DEV0_EPF3_0_PCIE_DPA_CAP 0x0254 #define cfgBIF_CFG_DEV0_EPF3_0_PCIE_DPA_LATENCY_INDICATOR 0x0258 #define cfgBIF_CFG_DEV0_EPF3_0_PCIE_DPA_STATUS 0x025c #define cfgBIF_CFG_DEV0_EPF3_0_PCIE_DPA_CNTL 0x025e #define cfgBIF_CFG_DEV0_EPF3_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_0 0x0260 #define cfgBIF_CFG_DEV0_EPF3_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_1 0x0261 #define cfgBIF_CFG_DEV0_EPF3_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_2 0x0262 #define cfgBIF_CFG_DEV0_EPF3_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_3 0x0263 #define cfgBIF_CFG_DEV0_EPF3_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_4 0x0264 #define cfgBIF_CFG_DEV0_EPF3_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_5 0x0265 #define cfgBIF_CFG_DEV0_EPF3_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_6 0x0266 #define cfgBIF_CFG_DEV0_EPF3_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_7 0x0267 #define cfgBIF_CFG_DEV0_EPF3_0_PCIE_ACS_ENH_CAP_LIST 0x02a0 #define cfgBIF_CFG_DEV0_EPF3_0_PCIE_ACS_CAP 0x02a4 #define cfgBIF_CFG_DEV0_EPF3_0_PCIE_ACS_CNTL 0x02a6 #define cfgBIF_CFG_DEV0_EPF3_0_PCIE_PASID_ENH_CAP_LIST 0x02d0 #define cfgBIF_CFG_DEV0_EPF3_0_PCIE_PASID_CAP 0x02d4 #define cfgBIF_CFG_DEV0_EPF3_0_PCIE_PASID_CNTL 0x02d6 #define cfgBIF_CFG_DEV0_EPF3_0_PCIE_ARI_ENH_CAP_LIST 0x0328 #define cfgBIF_CFG_DEV0_EPF3_0_PCIE_ARI_CAP 0x032c #define cfgBIF_CFG_DEV0_EPF3_0_PCIE_ARI_CNTL 0x032e #define cfgBIF_CFG_DEV0_EPF3_0_PCIE_TPH_REQR_ENH_CAP_LIST 0x0370 #define cfgBIF_CFG_DEV0_EPF3_0_PCIE_TPH_REQR_CAP 0x0374 #define cfgBIF_CFG_DEV0_EPF3_0_PCIE_TPH_REQR_CNTL 0x0378 #define cfgBIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_0 0x037c #define cfgBIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_1 0x037e #define cfgBIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_2 0x0380 #define cfgBIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_3 0x0382 #define cfgBIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_4 0x0384 #define cfgBIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_5 0x0386 #define cfgBIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_6 0x0388 #define cfgBIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_7 0x038a #define cfgBIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_8 0x038c #define cfgBIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_9 0x038e #define cfgBIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_10 0x0390 #define cfgBIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_11 0x0392 #define cfgBIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_12 0x0394 #define cfgBIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_13 0x0396 #define cfgBIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_14 0x0398 #define cfgBIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_15 0x039a #define cfgBIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_16 0x039c #define cfgBIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_17 0x039e #define cfgBIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_18 0x03a0 #define cfgBIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_19 0x03a2 #define cfgBIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_20 0x03a4 #define cfgBIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_21 0x03a6 #define cfgBIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_22 0x03a8 #define cfgBIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_23 0x03aa #define cfgBIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_24 0x03ac #define cfgBIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_25 0x03ae #define cfgBIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_26 0x03b0 #define cfgBIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_27 0x03b2 #define cfgBIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_28 0x03b4 #define cfgBIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_29 0x03b6 #define cfgBIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_30 0x03b8 #define cfgBIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_31 0x03ba #define cfgBIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_32 0x03bc #define cfgBIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_33 0x03be #define cfgBIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_34 0x03c0 #define cfgBIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_35 0x03c2 #define cfgBIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_36 0x03c4 #define cfgBIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_37 0x03c6 #define cfgBIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_38 0x03c8 #define cfgBIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_39 0x03ca #define cfgBIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_40 0x03cc #define cfgBIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_41 0x03ce #define cfgBIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_42 0x03d0 #define cfgBIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_43 0x03d2 #define cfgBIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_44 0x03d4 #define cfgBIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_45 0x03d6 #define cfgBIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_46 0x03d8 #define cfgBIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_47 0x03da #define cfgBIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_48 0x03dc #define cfgBIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_49 0x03de #define cfgBIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_50 0x03e0 #define cfgBIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_51 0x03e2 #define cfgBIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_52 0x03e4 #define cfgBIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_53 0x03e6 #define cfgBIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_54 0x03e8 #define cfgBIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_55 0x03ea #define cfgBIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_56 0x03ec #define cfgBIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_57 0x03ee #define cfgBIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_58 0x03f0 #define cfgBIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_59 0x03f2 #define cfgBIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_60 0x03f4 #define cfgBIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_61 0x03f6 #define cfgBIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_62 0x03f8 #define cfgBIF_CFG_DEV0_EPF3_0_PCIE_TPH_ST_TABLE_63 0x03fa // addressBlock: nbio_nbif0_bif_cfg_dev0_swds_bifcfgdecp // base address: 0x0 #define cfgBIF_CFG_DEV0_SWDS0_VENDOR_ID 0x0000 #define cfgBIF_CFG_DEV0_SWDS0_DEVICE_ID 0x0002 #define cfgBIF_CFG_DEV0_SWDS0_COMMAND 0x0004 #define cfgBIF_CFG_DEV0_SWDS0_STATUS 0x0006 #define cfgBIF_CFG_DEV0_SWDS0_REVISION_ID 0x0008 #define cfgBIF_CFG_DEV0_SWDS0_PROG_INTERFACE 0x0009 #define cfgBIF_CFG_DEV0_SWDS0_SUB_CLASS 0x000a #define cfgBIF_CFG_DEV0_SWDS0_BASE_CLASS 0x000b #define cfgBIF_CFG_DEV0_SWDS0_CACHE_LINE 0x000c #define cfgBIF_CFG_DEV0_SWDS0_LATENCY 0x000d #define cfgBIF_CFG_DEV0_SWDS0_HEADER 0x000e #define cfgBIF_CFG_DEV0_SWDS0_BIST 0x000f #define cfgBIF_CFG_DEV0_SWDS0_BASE_ADDR_1 0x0010 #define cfgBIF_CFG_DEV0_SWDS0_BASE_ADDR_2 0x0014 #define cfgBIF_CFG_DEV0_SWDS0_SUB_BUS_NUMBER_LATENCY 0x0018 #define cfgBIF_CFG_DEV0_SWDS0_IO_BASE_LIMIT 0x001c #define cfgBIF_CFG_DEV0_SWDS0_SECONDARY_STATUS 0x001e #define cfgBIF_CFG_DEV0_SWDS0_MEM_BASE_LIMIT 0x0020 #define cfgBIF_CFG_DEV0_SWDS0_PREF_BASE_LIMIT 0x0024 #define cfgBIF_CFG_DEV0_SWDS0_PREF_BASE_UPPER 0x0028 #define cfgBIF_CFG_DEV0_SWDS0_PREF_LIMIT_UPPER 0x002c #define cfgBIF_CFG_DEV0_SWDS0_IO_BASE_LIMIT_HI 0x0030 #define cfgBIF_CFG_DEV0_SWDS0_CAP_PTR 0x0034 #define cfgBIF_CFG_DEV0_SWDS0_ROM_BASE_ADDR 0x0038 #define cfgBIF_CFG_DEV0_SWDS0_INTERRUPT_LINE 0x003c #define cfgBIF_CFG_DEV0_SWDS0_INTERRUPT_PIN 0x003d #define cfgBIF_CFG_DEV0_SWDS0_IRQ_BRIDGE_CNTL 0x003e #define cfgBIF_CFG_DEV0_SWDS0_PMI_CAP_LIST 0x0050 #define cfgBIF_CFG_DEV0_SWDS0_PMI_CAP 0x0052 #define cfgBIF_CFG_DEV0_SWDS0_PMI_STATUS_CNTL 0x0054 #define cfgBIF_CFG_DEV0_SWDS0_PCIE_CAP_LIST 0x0058 #define cfgBIF_CFG_DEV0_SWDS0_PCIE_CAP 0x005a #define cfgBIF_CFG_DEV0_SWDS0_DEVICE_CAP 0x005c #define cfgBIF_CFG_DEV0_SWDS0_DEVICE_CNTL 0x0060 #define cfgBIF_CFG_DEV0_SWDS0_DEVICE_STATUS 0x0062 #define cfgBIF_CFG_DEV0_SWDS0_LINK_CAP 0x0064 #define cfgBIF_CFG_DEV0_SWDS0_LINK_CNTL 0x0068 #define cfgBIF_CFG_DEV0_SWDS0_LINK_STATUS 0x006a #define cfgBIF_CFG_DEV0_SWDS0_SLOT_CAP 0x006c #define cfgBIF_CFG_DEV0_SWDS0_SLOT_CNTL 0x0070 #define cfgBIF_CFG_DEV0_SWDS0_SLOT_STATUS 0x0072 #define cfgBIF_CFG_DEV0_SWDS0_DEVICE_CAP2 0x007c #define cfgBIF_CFG_DEV0_SWDS0_DEVICE_CNTL2 0x0080 #define cfgBIF_CFG_DEV0_SWDS0_DEVICE_STATUS2 0x0082 #define cfgBIF_CFG_DEV0_SWDS0_LINK_CAP2 0x0084 #define cfgBIF_CFG_DEV0_SWDS0_LINK_CNTL2 0x0088 #define cfgBIF_CFG_DEV0_SWDS0_LINK_STATUS2 0x008a #define cfgBIF_CFG_DEV0_SWDS0_SLOT_CAP2 0x008c #define cfgBIF_CFG_DEV0_SWDS0_SLOT_CNTL2 0x0090 #define cfgBIF_CFG_DEV0_SWDS0_SLOT_STATUS2 0x0092 #define cfgBIF_CFG_DEV0_SWDS0_MSI_CAP_LIST 0x00a0 #define cfgBIF_CFG_DEV0_SWDS0_MSI_MSG_CNTL 0x00a2 #define cfgBIF_CFG_DEV0_SWDS0_MSI_MSG_ADDR_LO 0x00a4 #define cfgBIF_CFG_DEV0_SWDS0_MSI_MSG_ADDR_HI 0x00a8 #define cfgBIF_CFG_DEV0_SWDS0_MSI_MSG_DATA 0x00a8 #define cfgBIF_CFG_DEV0_SWDS0_MSI_MSG_DATA_64 0x00ac #define cfgBIF_CFG_DEV0_SWDS0_SSID_CAP_LIST 0x00c0 #define cfgBIF_CFG_DEV0_SWDS0_SSID_CAP 0x00c4 #define cfgBIF_CFG_DEV0_SWDS0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x0100 #define cfgBIF_CFG_DEV0_SWDS0_PCIE_VENDOR_SPECIFIC_HDR 0x0104 #define cfgBIF_CFG_DEV0_SWDS0_PCIE_VENDOR_SPECIFIC1 0x0108 #define cfgBIF_CFG_DEV0_SWDS0_PCIE_VENDOR_SPECIFIC2 0x010c #define cfgBIF_CFG_DEV0_SWDS0_PCIE_VC_ENH_CAP_LIST 0x0110 #define cfgBIF_CFG_DEV0_SWDS0_PCIE_PORT_VC_CAP_REG1 0x0114 #define cfgBIF_CFG_DEV0_SWDS0_PCIE_PORT_VC_CAP_REG2 0x0118 #define cfgBIF_CFG_DEV0_SWDS0_PCIE_PORT_VC_CNTL 0x011c #define cfgBIF_CFG_DEV0_SWDS0_PCIE_PORT_VC_STATUS 0x011e #define cfgBIF_CFG_DEV0_SWDS0_PCIE_VC0_RESOURCE_CAP 0x0120 #define cfgBIF_CFG_DEV0_SWDS0_PCIE_VC0_RESOURCE_CNTL 0x0124 #define cfgBIF_CFG_DEV0_SWDS0_PCIE_VC0_RESOURCE_STATUS 0x012a #define cfgBIF_CFG_DEV0_SWDS0_PCIE_VC1_RESOURCE_CAP 0x012c #define cfgBIF_CFG_DEV0_SWDS0_PCIE_VC1_RESOURCE_CNTL 0x0130 #define cfgBIF_CFG_DEV0_SWDS0_PCIE_VC1_RESOURCE_STATUS 0x0136 #define cfgBIF_CFG_DEV0_SWDS0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST 0x0140 #define cfgBIF_CFG_DEV0_SWDS0_PCIE_DEV_SERIAL_NUM_DW1 0x0144 #define cfgBIF_CFG_DEV0_SWDS0_PCIE_DEV_SERIAL_NUM_DW2 0x0148 #define cfgBIF_CFG_DEV0_SWDS0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x0150 #define cfgBIF_CFG_DEV0_SWDS0_PCIE_UNCORR_ERR_STATUS 0x0154 #define cfgBIF_CFG_DEV0_SWDS0_PCIE_UNCORR_ERR_MASK 0x0158 #define cfgBIF_CFG_DEV0_SWDS0_PCIE_UNCORR_ERR_SEVERITY 0x015c #define cfgBIF_CFG_DEV0_SWDS0_PCIE_CORR_ERR_STATUS 0x0160 #define cfgBIF_CFG_DEV0_SWDS0_PCIE_CORR_ERR_MASK 0x0164 #define cfgBIF_CFG_DEV0_SWDS0_PCIE_ADV_ERR_CAP_CNTL 0x0168 #define cfgBIF_CFG_DEV0_SWDS0_PCIE_HDR_LOG0 0x016c #define cfgBIF_CFG_DEV0_SWDS0_PCIE_HDR_LOG1 0x0170 #define cfgBIF_CFG_DEV0_SWDS0_PCIE_HDR_LOG2 0x0174 #define cfgBIF_CFG_DEV0_SWDS0_PCIE_HDR_LOG3 0x0178 #define cfgBIF_CFG_DEV0_SWDS0_PCIE_TLP_PREFIX_LOG0 0x0188 #define cfgBIF_CFG_DEV0_SWDS0_PCIE_TLP_PREFIX_LOG1 0x018c #define cfgBIF_CFG_DEV0_SWDS0_PCIE_TLP_PREFIX_LOG2 0x0190 #define cfgBIF_CFG_DEV0_SWDS0_PCIE_TLP_PREFIX_LOG3 0x0194 #define cfgBIF_CFG_DEV0_SWDS0_PCIE_SECONDARY_ENH_CAP_LIST 0x0270 #define cfgBIF_CFG_DEV0_SWDS0_PCIE_LINK_CNTL3 0x0274 #define cfgBIF_CFG_DEV0_SWDS0_PCIE_LANE_ERROR_STATUS 0x0278 #define cfgBIF_CFG_DEV0_SWDS0_PCIE_LANE_0_EQUALIZATION_CNTL 0x027c #define cfgBIF_CFG_DEV0_SWDS0_PCIE_LANE_1_EQUALIZATION_CNTL 0x027e #define cfgBIF_CFG_DEV0_SWDS0_PCIE_LANE_2_EQUALIZATION_CNTL 0x0280 #define cfgBIF_CFG_DEV0_SWDS0_PCIE_LANE_3_EQUALIZATION_CNTL 0x0282 #define cfgBIF_CFG_DEV0_SWDS0_PCIE_LANE_4_EQUALIZATION_CNTL 0x0284 #define cfgBIF_CFG_DEV0_SWDS0_PCIE_LANE_5_EQUALIZATION_CNTL 0x0286 #define cfgBIF_CFG_DEV0_SWDS0_PCIE_LANE_6_EQUALIZATION_CNTL 0x0288 #define cfgBIF_CFG_DEV0_SWDS0_PCIE_LANE_7_EQUALIZATION_CNTL 0x028a #define cfgBIF_CFG_DEV0_SWDS0_PCIE_LANE_8_EQUALIZATION_CNTL 0x028c #define cfgBIF_CFG_DEV0_SWDS0_PCIE_LANE_9_EQUALIZATION_CNTL 0x028e #define cfgBIF_CFG_DEV0_SWDS0_PCIE_LANE_10_EQUALIZATION_CNTL 0x0290 #define cfgBIF_CFG_DEV0_SWDS0_PCIE_LANE_11_EQUALIZATION_CNTL 0x0292 #define cfgBIF_CFG_DEV0_SWDS0_PCIE_LANE_12_EQUALIZATION_CNTL 0x0294 #define cfgBIF_CFG_DEV0_SWDS0_PCIE_LANE_13_EQUALIZATION_CNTL 0x0296 #define cfgBIF_CFG_DEV0_SWDS0_PCIE_LANE_14_EQUALIZATION_CNTL 0x0298 #define cfgBIF_CFG_DEV0_SWDS0_PCIE_LANE_15_EQUALIZATION_CNTL 0x029a #define cfgBIF_CFG_DEV0_SWDS0_PCIE_ACS_ENH_CAP_LIST 0x02a0 #define cfgBIF_CFG_DEV0_SWDS0_PCIE_ACS_CAP 0x02a4 #define cfgBIF_CFG_DEV0_SWDS0_PCIE_ACS_CNTL 0x02a6 #define cfgBIF_CFG_DEV0_SWDS0_PCIE_DLF_ENH_CAP_LIST 0x0400 #define cfgBIF_CFG_DEV0_SWDS0_DATA_LINK_FEATURE_CAP 0x0404 #define cfgBIF_CFG_DEV0_SWDS0_DATA_LINK_FEATURE_STATUS 0x0408 #define cfgBIF_CFG_DEV0_SWDS0_PCIE_PHY_16GT_ENH_CAP_LIST 0x0410 #define cfgBIF_CFG_DEV0_SWDS0_LINK_CAP_16GT 0x0414 #define cfgBIF_CFG_DEV0_SWDS0_LINK_CNTL_16GT 0x0418 #define cfgBIF_CFG_DEV0_SWDS0_LINK_STATUS_16GT 0x041c #define cfgBIF_CFG_DEV0_SWDS0_LOCAL_PARITY_MISMATCH_STATUS_16GT 0x0420 #define cfgBIF_CFG_DEV0_SWDS0_RTM1_PARITY_MISMATCH_STATUS_16GT 0x0424 #define cfgBIF_CFG_DEV0_SWDS0_RTM2_PARITY_MISMATCH_STATUS_16GT 0x0428 #define cfgBIF_CFG_DEV0_SWDS0_LANE_0_EQUALIZATION_CNTL_16GT 0x0430 #define cfgBIF_CFG_DEV0_SWDS0_LANE_1_EQUALIZATION_CNTL_16GT 0x0431 #define cfgBIF_CFG_DEV0_SWDS0_LANE_2_EQUALIZATION_CNTL_16GT 0x0432 #define cfgBIF_CFG_DEV0_SWDS0_LANE_3_EQUALIZATION_CNTL_16GT 0x0433 #define cfgBIF_CFG_DEV0_SWDS0_LANE_4_EQUALIZATION_CNTL_16GT 0x0434 #define cfgBIF_CFG_DEV0_SWDS0_LANE_5_EQUALIZATION_CNTL_16GT 0x0435 #define cfgBIF_CFG_DEV0_SWDS0_LANE_6_EQUALIZATION_CNTL_16GT 0x0436 #define cfgBIF_CFG_DEV0_SWDS0_LANE_7_EQUALIZATION_CNTL_16GT 0x0437 #define cfgBIF_CFG_DEV0_SWDS0_LANE_8_EQUALIZATION_CNTL_16GT 0x0438 #define cfgBIF_CFG_DEV0_SWDS0_LANE_9_EQUALIZATION_CNTL_16GT 0x0439 #define cfgBIF_CFG_DEV0_SWDS0_LANE_10_EQUALIZATION_CNTL_16GT 0x043a #define cfgBIF_CFG_DEV0_SWDS0_LANE_11_EQUALIZATION_CNTL_16GT 0x043b #define cfgBIF_CFG_DEV0_SWDS0_LANE_12_EQUALIZATION_CNTL_16GT 0x043c #define cfgBIF_CFG_DEV0_SWDS0_LANE_13_EQUALIZATION_CNTL_16GT 0x043d #define cfgBIF_CFG_DEV0_SWDS0_LANE_14_EQUALIZATION_CNTL_16GT 0x043e #define cfgBIF_CFG_DEV0_SWDS0_LANE_15_EQUALIZATION_CNTL_16GT 0x043f #define cfgBIF_CFG_DEV0_SWDS0_PCIE_MARGINING_ENH_CAP_LIST 0x0440 #define cfgBIF_CFG_DEV0_SWDS0_MARGINING_PORT_CAP 0x0444 #define cfgBIF_CFG_DEV0_SWDS0_MARGINING_PORT_STATUS 0x0446 #define cfgBIF_CFG_DEV0_SWDS0_LANE_0_MARGINING_LANE_CNTL 0x0448 #define cfgBIF_CFG_DEV0_SWDS0_LANE_0_MARGINING_LANE_STATUS 0x044a #define cfgBIF_CFG_DEV0_SWDS0_LANE_1_MARGINING_LANE_CNTL 0x044c #define cfgBIF_CFG_DEV0_SWDS0_LANE_1_MARGINING_LANE_STATUS 0x044e #define cfgBIF_CFG_DEV0_SWDS0_LANE_2_MARGINING_LANE_CNTL 0x0450 #define cfgBIF_CFG_DEV0_SWDS0_LANE_2_MARGINING_LANE_STATUS 0x0452 #define cfgBIF_CFG_DEV0_SWDS0_LANE_3_MARGINING_LANE_CNTL 0x0454 #define cfgBIF_CFG_DEV0_SWDS0_LANE_3_MARGINING_LANE_STATUS 0x0456 #define cfgBIF_CFG_DEV0_SWDS0_LANE_4_MARGINING_LANE_CNTL 0x0458 #define cfgBIF_CFG_DEV0_SWDS0_LANE_4_MARGINING_LANE_STATUS 0x045a #define cfgBIF_CFG_DEV0_SWDS0_LANE_5_MARGINING_LANE_CNTL 0x045c #define cfgBIF_CFG_DEV0_SWDS0_LANE_5_MARGINING_LANE_STATUS 0x045e #define cfgBIF_CFG_DEV0_SWDS0_LANE_6_MARGINING_LANE_CNTL 0x0460 #define cfgBIF_CFG_DEV0_SWDS0_LANE_6_MARGINING_LANE_STATUS 0x0462 #define cfgBIF_CFG_DEV0_SWDS0_LANE_7_MARGINING_LANE_CNTL 0x0464 #define cfgBIF_CFG_DEV0_SWDS0_LANE_7_MARGINING_LANE_STATUS 0x0466 #define cfgBIF_CFG_DEV0_SWDS0_LANE_8_MARGINING_LANE_CNTL 0x0468 #define cfgBIF_CFG_DEV0_SWDS0_LANE_8_MARGINING_LANE_STATUS 0x046a #define cfgBIF_CFG_DEV0_SWDS0_LANE_9_MARGINING_LANE_CNTL 0x046c #define cfgBIF_CFG_DEV0_SWDS0_LANE_9_MARGINING_LANE_STATUS 0x046e #define cfgBIF_CFG_DEV0_SWDS0_LANE_10_MARGINING_LANE_CNTL 0x0470 #define cfgBIF_CFG_DEV0_SWDS0_LANE_10_MARGINING_LANE_STATUS 0x0472 #define cfgBIF_CFG_DEV0_SWDS0_LANE_11_MARGINING_LANE_CNTL 0x0474 #define cfgBIF_CFG_DEV0_SWDS0_LANE_11_MARGINING_LANE_STATUS 0x0476 #define cfgBIF_CFG_DEV0_SWDS0_LANE_12_MARGINING_LANE_CNTL 0x0478 #define cfgBIF_CFG_DEV0_SWDS0_LANE_12_MARGINING_LANE_STATUS 0x047a #define cfgBIF_CFG_DEV0_SWDS0_LANE_13_MARGINING_LANE_CNTL 0x047c #define cfgBIF_CFG_DEV0_SWDS0_LANE_13_MARGINING_LANE_STATUS 0x047e #define cfgBIF_CFG_DEV0_SWDS0_LANE_14_MARGINING_LANE_CNTL 0x0480 #define cfgBIF_CFG_DEV0_SWDS0_LANE_14_MARGINING_LANE_STATUS 0x0482 #define cfgBIF_CFG_DEV0_SWDS0_LANE_15_MARGINING_LANE_CNTL 0x0484 #define cfgBIF_CFG_DEV0_SWDS0_LANE_15_MARGINING_LANE_STATUS 0x0486 // addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf0_bifcfgdecp // base address: 0x0 #define cfgBIF_CFG_DEV0_EPF0_VF0_0_VENDOR_ID 0x0000 #define cfgBIF_CFG_DEV0_EPF0_VF0_0_DEVICE_ID 0x0002 #define cfgBIF_CFG_DEV0_EPF0_VF0_0_COMMAND 0x0004 #define cfgBIF_CFG_DEV0_EPF0_VF0_0_STATUS 0x0006 #define cfgBIF_CFG_DEV0_EPF0_VF0_0_REVISION_ID 0x0008 #define cfgBIF_CFG_DEV0_EPF0_VF0_0_PROG_INTERFACE 0x0009 #define cfgBIF_CFG_DEV0_EPF0_VF0_0_SUB_CLASS 0x000a #define cfgBIF_CFG_DEV0_EPF0_VF0_0_BASE_CLASS 0x000b #define cfgBIF_CFG_DEV0_EPF0_VF0_0_CACHE_LINE 0x000c #define cfgBIF_CFG_DEV0_EPF0_VF0_0_LATENCY 0x000d #define cfgBIF_CFG_DEV0_EPF0_VF0_0_HEADER 0x000e #define cfgBIF_CFG_DEV0_EPF0_VF0_0_BIST 0x000f #define cfgBIF_CFG_DEV0_EPF0_VF0_0_BASE_ADDR_1 0x0010 #define cfgBIF_CFG_DEV0_EPF0_VF0_0_BASE_ADDR_2 0x0014 #define cfgBIF_CFG_DEV0_EPF0_VF0_0_BASE_ADDR_3 0x0018 #define cfgBIF_CFG_DEV0_EPF0_VF0_0_BASE_ADDR_4 0x001c #define cfgBIF_CFG_DEV0_EPF0_VF0_0_BASE_ADDR_5 0x0020 #define cfgBIF_CFG_DEV0_EPF0_VF0_0_BASE_ADDR_6 0x0024 #define cfgBIF_CFG_DEV0_EPF0_VF0_0_CARDBUS_CIS_PTR 0x0028 #define cfgBIF_CFG_DEV0_EPF0_VF0_0_ADAPTER_ID 0x002c #define cfgBIF_CFG_DEV0_EPF0_VF0_0_ROM_BASE_ADDR 0x0030 #define cfgBIF_CFG_DEV0_EPF0_VF0_0_CAP_PTR 0x0034 #define cfgBIF_CFG_DEV0_EPF0_VF0_0_INTERRUPT_LINE 0x003c #define cfgBIF_CFG_DEV0_EPF0_VF0_0_INTERRUPT_PIN 0x003d #define cfgBIF_CFG_DEV0_EPF0_VF0_0_MIN_GRANT 0x003e #define cfgBIF_CFG_DEV0_EPF0_VF0_0_MAX_LATENCY 0x003f #define cfgBIF_CFG_DEV0_EPF0_VF0_0_PCIE_CAP_LIST 0x0064 #define cfgBIF_CFG_DEV0_EPF0_VF0_0_PCIE_CAP 0x0066 #define cfgBIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CAP 0x0068 #define cfgBIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CNTL 0x006c #define cfgBIF_CFG_DEV0_EPF0_VF0_0_DEVICE_STATUS 0x006e #define cfgBIF_CFG_DEV0_EPF0_VF0_0_LINK_CAP 0x0070 #define cfgBIF_CFG_DEV0_EPF0_VF0_0_LINK_CNTL 0x0074 #define cfgBIF_CFG_DEV0_EPF0_VF0_0_LINK_STATUS 0x0076 #define cfgBIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CAP2 0x0088 #define cfgBIF_CFG_DEV0_EPF0_VF0_0_DEVICE_CNTL2 0x008c #define cfgBIF_CFG_DEV0_EPF0_VF0_0_DEVICE_STATUS2 0x008e #define cfgBIF_CFG_DEV0_EPF0_VF0_0_LINK_CAP2 0x0090 #define cfgBIF_CFG_DEV0_EPF0_VF0_0_LINK_CNTL2 0x0094 #define cfgBIF_CFG_DEV0_EPF0_VF0_0_LINK_STATUS2 0x0096 #define cfgBIF_CFG_DEV0_EPF0_VF0_0_MSI_CAP_LIST 0x00a0 #define cfgBIF_CFG_DEV0_EPF0_VF0_0_MSI_MSG_CNTL 0x00a2 #define cfgBIF_CFG_DEV0_EPF0_VF0_0_MSI_MSG_ADDR_LO 0x00a4 #define cfgBIF_CFG_DEV0_EPF0_VF0_0_MSI_MSG_ADDR_HI 0x00a8 #define cfgBIF_CFG_DEV0_EPF0_VF0_0_MSI_MSG_DATA 0x00a8 #define cfgBIF_CFG_DEV0_EPF0_VF0_0_MSI_MASK 0x00ac #define cfgBIF_CFG_DEV0_EPF0_VF0_0_MSI_MSG_DATA_64 0x00ac #define cfgBIF_CFG_DEV0_EPF0_VF0_0_MSI_MASK_64 0x00b0 #define cfgBIF_CFG_DEV0_EPF0_VF0_0_MSI_PENDING 0x00b0 #define cfgBIF_CFG_DEV0_EPF0_VF0_0_MSI_PENDING_64 0x00b4 #define cfgBIF_CFG_DEV0_EPF0_VF0_0_MSIX_CAP_LIST 0x00c0 #define cfgBIF_CFG_DEV0_EPF0_VF0_0_MSIX_MSG_CNTL 0x00c2 #define cfgBIF_CFG_DEV0_EPF0_VF0_0_MSIX_TABLE 0x00c4 #define cfgBIF_CFG_DEV0_EPF0_VF0_0_MSIX_PBA 0x00c8 #define cfgBIF_CFG_DEV0_EPF0_VF0_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x0100 #define cfgBIF_CFG_DEV0_EPF0_VF0_0_PCIE_VENDOR_SPECIFIC_HDR 0x0104 #define cfgBIF_CFG_DEV0_EPF0_VF0_0_PCIE_VENDOR_SPECIFIC1 0x0108 #define cfgBIF_CFG_DEV0_EPF0_VF0_0_PCIE_VENDOR_SPECIFIC2 0x010c #define cfgBIF_CFG_DEV0_EPF0_VF0_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x0150 #define cfgBIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_STATUS 0x0154 #define cfgBIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_MASK 0x0158 #define cfgBIF_CFG_DEV0_EPF0_VF0_0_PCIE_UNCORR_ERR_SEVERITY 0x015c #define cfgBIF_CFG_DEV0_EPF0_VF0_0_PCIE_CORR_ERR_STATUS 0x0160 #define cfgBIF_CFG_DEV0_EPF0_VF0_0_PCIE_CORR_ERR_MASK 0x0164 #define cfgBIF_CFG_DEV0_EPF0_VF0_0_PCIE_ADV_ERR_CAP_CNTL 0x0168 #define cfgBIF_CFG_DEV0_EPF0_VF0_0_PCIE_HDR_LOG0 0x016c #define cfgBIF_CFG_DEV0_EPF0_VF0_0_PCIE_HDR_LOG1 0x0170 #define cfgBIF_CFG_DEV0_EPF0_VF0_0_PCIE_HDR_LOG2 0x0174 #define cfgBIF_CFG_DEV0_EPF0_VF0_0_PCIE_HDR_LOG3 0x0178 #define cfgBIF_CFG_DEV0_EPF0_VF0_0_PCIE_TLP_PREFIX_LOG0 0x0188 #define cfgBIF_CFG_DEV0_EPF0_VF0_0_PCIE_TLP_PREFIX_LOG1 0x018c #define cfgBIF_CFG_DEV0_EPF0_VF0_0_PCIE_TLP_PREFIX_LOG2 0x0190 #define cfgBIF_CFG_DEV0_EPF0_VF0_0_PCIE_TLP_PREFIX_LOG3 0x0194 #define cfgBIF_CFG_DEV0_EPF0_VF0_0_PCIE_ATS_ENH_CAP_LIST 0x02b0 #define cfgBIF_CFG_DEV0_EPF0_VF0_0_PCIE_ATS_CAP 0x02b4 #define cfgBIF_CFG_DEV0_EPF0_VF0_0_PCIE_ATS_CNTL 0x02b6 #define cfgBIF_CFG_DEV0_EPF0_VF0_0_PCIE_ARI_ENH_CAP_LIST 0x0328 #define cfgBIF_CFG_DEV0_EPF0_VF0_0_PCIE_ARI_CAP 0x032c #define cfgBIF_CFG_DEV0_EPF0_VF0_0_PCIE_ARI_CNTL 0x032e // addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf1_bifcfgdecp // base address: 0x0 #define cfgBIF_CFG_DEV0_EPF0_VF1_0_VENDOR_ID 0x0000 #define cfgBIF_CFG_DEV0_EPF0_VF1_0_DEVICE_ID 0x0002 #define cfgBIF_CFG_DEV0_EPF0_VF1_0_COMMAND 0x0004 #define cfgBIF_CFG_DEV0_EPF0_VF1_0_STATUS 0x0006 #define cfgBIF_CFG_DEV0_EPF0_VF1_0_REVISION_ID 0x0008 #define cfgBIF_CFG_DEV0_EPF0_VF1_0_PROG_INTERFACE 0x0009 #define cfgBIF_CFG_DEV0_EPF0_VF1_0_SUB_CLASS 0x000a #define cfgBIF_CFG_DEV0_EPF0_VF1_0_BASE_CLASS 0x000b #define cfgBIF_CFG_DEV0_EPF0_VF1_0_CACHE_LINE 0x000c #define cfgBIF_CFG_DEV0_EPF0_VF1_0_LATENCY 0x000d #define cfgBIF_CFG_DEV0_EPF0_VF1_0_HEADER 0x000e #define cfgBIF_CFG_DEV0_EPF0_VF1_0_BIST 0x000f #define cfgBIF_CFG_DEV0_EPF0_VF1_0_BASE_ADDR_1 0x0010 #define cfgBIF_CFG_DEV0_EPF0_VF1_0_BASE_ADDR_2 0x0014 #define cfgBIF_CFG_DEV0_EPF0_VF1_0_BASE_ADDR_3 0x0018 #define cfgBIF_CFG_DEV0_EPF0_VF1_0_BASE_ADDR_4 0x001c #define cfgBIF_CFG_DEV0_EPF0_VF1_0_BASE_ADDR_5 0x0020 #define cfgBIF_CFG_DEV0_EPF0_VF1_0_BASE_ADDR_6 0x0024 #define cfgBIF_CFG_DEV0_EPF0_VF1_0_CARDBUS_CIS_PTR 0x0028 #define cfgBIF_CFG_DEV0_EPF0_VF1_0_ADAPTER_ID 0x002c #define cfgBIF_CFG_DEV0_EPF0_VF1_0_ROM_BASE_ADDR 0x0030 #define cfgBIF_CFG_DEV0_EPF0_VF1_0_CAP_PTR 0x0034 #define cfgBIF_CFG_DEV0_EPF0_VF1_0_INTERRUPT_LINE 0x003c #define cfgBIF_CFG_DEV0_EPF0_VF1_0_INTERRUPT_PIN 0x003d #define cfgBIF_CFG_DEV0_EPF0_VF1_0_MIN_GRANT 0x003e #define cfgBIF_CFG_DEV0_EPF0_VF1_0_MAX_LATENCY 0x003f #define cfgBIF_CFG_DEV0_EPF0_VF1_0_PCIE_CAP_LIST 0x0064 #define cfgBIF_CFG_DEV0_EPF0_VF1_0_PCIE_CAP 0x0066 #define cfgBIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CAP 0x0068 #define cfgBIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CNTL 0x006c #define cfgBIF_CFG_DEV0_EPF0_VF1_0_DEVICE_STATUS 0x006e #define cfgBIF_CFG_DEV0_EPF0_VF1_0_LINK_CAP 0x0070 #define cfgBIF_CFG_DEV0_EPF0_VF1_0_LINK_CNTL 0x0074 #define cfgBIF_CFG_DEV0_EPF0_VF1_0_LINK_STATUS 0x0076 #define cfgBIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CAP2 0x0088 #define cfgBIF_CFG_DEV0_EPF0_VF1_0_DEVICE_CNTL2 0x008c #define cfgBIF_CFG_DEV0_EPF0_VF1_0_DEVICE_STATUS2 0x008e #define cfgBIF_CFG_DEV0_EPF0_VF1_0_LINK_CAP2 0x0090 #define cfgBIF_CFG_DEV0_EPF0_VF1_0_LINK_CNTL2 0x0094 #define cfgBIF_CFG_DEV0_EPF0_VF1_0_LINK_STATUS2 0x0096 #define cfgBIF_CFG_DEV0_EPF0_VF1_0_MSI_CAP_LIST 0x00a0 #define cfgBIF_CFG_DEV0_EPF0_VF1_0_MSI_MSG_CNTL 0x00a2 #define cfgBIF_CFG_DEV0_EPF0_VF1_0_MSI_MSG_ADDR_LO 0x00a4 #define cfgBIF_CFG_DEV0_EPF0_VF1_0_MSI_MSG_ADDR_HI 0x00a8 #define cfgBIF_CFG_DEV0_EPF0_VF1_0_MSI_MSG_DATA 0x00a8 #define cfgBIF_CFG_DEV0_EPF0_VF1_0_MSI_MASK 0x00ac #define cfgBIF_CFG_DEV0_EPF0_VF1_0_MSI_MSG_DATA_64 0x00ac #define cfgBIF_CFG_DEV0_EPF0_VF1_0_MSI_MASK_64 0x00b0 #define cfgBIF_CFG_DEV0_EPF0_VF1_0_MSI_PENDING 0x00b0 #define cfgBIF_CFG_DEV0_EPF0_VF1_0_MSI_PENDING_64 0x00b4 #define cfgBIF_CFG_DEV0_EPF0_VF1_0_MSIX_CAP_LIST 0x00c0 #define cfgBIF_CFG_DEV0_EPF0_VF1_0_MSIX_MSG_CNTL 0x00c2 #define cfgBIF_CFG_DEV0_EPF0_VF1_0_MSIX_TABLE 0x00c4 #define cfgBIF_CFG_DEV0_EPF0_VF1_0_MSIX_PBA 0x00c8 #define cfgBIF_CFG_DEV0_EPF0_VF1_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x0100 #define cfgBIF_CFG_DEV0_EPF0_VF1_0_PCIE_VENDOR_SPECIFIC_HDR 0x0104 #define cfgBIF_CFG_DEV0_EPF0_VF1_0_PCIE_VENDOR_SPECIFIC1 0x0108 #define cfgBIF_CFG_DEV0_EPF0_VF1_0_PCIE_VENDOR_SPECIFIC2 0x010c #define cfgBIF_CFG_DEV0_EPF0_VF1_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x0150 #define cfgBIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_STATUS 0x0154 #define cfgBIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_MASK 0x0158 #define cfgBIF_CFG_DEV0_EPF0_VF1_0_PCIE_UNCORR_ERR_SEVERITY 0x015c #define cfgBIF_CFG_DEV0_EPF0_VF1_0_PCIE_CORR_ERR_STATUS 0x0160 #define cfgBIF_CFG_DEV0_EPF0_VF1_0_PCIE_CORR_ERR_MASK 0x0164 #define cfgBIF_CFG_DEV0_EPF0_VF1_0_PCIE_ADV_ERR_CAP_CNTL 0x0168 #define cfgBIF_CFG_DEV0_EPF0_VF1_0_PCIE_HDR_LOG0 0x016c #define cfgBIF_CFG_DEV0_EPF0_VF1_0_PCIE_HDR_LOG1 0x0170 #define cfgBIF_CFG_DEV0_EPF0_VF1_0_PCIE_HDR_LOG2 0x0174 #define cfgBIF_CFG_DEV0_EPF0_VF1_0_PCIE_HDR_LOG3 0x0178 #define cfgBIF_CFG_DEV0_EPF0_VF1_0_PCIE_TLP_PREFIX_LOG0 0x0188 #define cfgBIF_CFG_DEV0_EPF0_VF1_0_PCIE_TLP_PREFIX_LOG1 0x018c #define cfgBIF_CFG_DEV0_EPF0_VF1_0_PCIE_TLP_PREFIX_LOG2 0x0190 #define cfgBIF_CFG_DEV0_EPF0_VF1_0_PCIE_TLP_PREFIX_LOG3 0x0194 #define cfgBIF_CFG_DEV0_EPF0_VF1_0_PCIE_ATS_ENH_CAP_LIST 0x02b0 #define cfgBIF_CFG_DEV0_EPF0_VF1_0_PCIE_ATS_CAP 0x02b4 #define cfgBIF_CFG_DEV0_EPF0_VF1_0_PCIE_ATS_CNTL 0x02b6 #define cfgBIF_CFG_DEV0_EPF0_VF1_0_PCIE_ARI_ENH_CAP_LIST 0x0328 #define cfgBIF_CFG_DEV0_EPF0_VF1_0_PCIE_ARI_CAP 0x032c #define cfgBIF_CFG_DEV0_EPF0_VF1_0_PCIE_ARI_CNTL 0x032e // addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf2_bifcfgdecp // base address: 0x0 #define cfgBIF_CFG_DEV0_EPF0_VF2_0_VENDOR_ID 0x0000 #define cfgBIF_CFG_DEV0_EPF0_VF2_0_DEVICE_ID 0x0002 #define cfgBIF_CFG_DEV0_EPF0_VF2_0_COMMAND 0x0004 #define cfgBIF_CFG_DEV0_EPF0_VF2_0_STATUS 0x0006 #define cfgBIF_CFG_DEV0_EPF0_VF2_0_REVISION_ID 0x0008 #define cfgBIF_CFG_DEV0_EPF0_VF2_0_PROG_INTERFACE 0x0009 #define cfgBIF_CFG_DEV0_EPF0_VF2_0_SUB_CLASS 0x000a #define cfgBIF_CFG_DEV0_EPF0_VF2_0_BASE_CLASS 0x000b #define cfgBIF_CFG_DEV0_EPF0_VF2_0_CACHE_LINE 0x000c #define cfgBIF_CFG_DEV0_EPF0_VF2_0_LATENCY 0x000d #define cfgBIF_CFG_DEV0_EPF0_VF2_0_HEADER 0x000e #define cfgBIF_CFG_DEV0_EPF0_VF2_0_BIST 0x000f #define cfgBIF_CFG_DEV0_EPF0_VF2_0_BASE_ADDR_1 0x0010 #define cfgBIF_CFG_DEV0_EPF0_VF2_0_BASE_ADDR_2 0x0014 #define cfgBIF_CFG_DEV0_EPF0_VF2_0_BASE_ADDR_3 0x0018 #define cfgBIF_CFG_DEV0_EPF0_VF2_0_BASE_ADDR_4 0x001c #define cfgBIF_CFG_DEV0_EPF0_VF2_0_BASE_ADDR_5 0x0020 #define cfgBIF_CFG_DEV0_EPF0_VF2_0_BASE_ADDR_6 0x0024 #define cfgBIF_CFG_DEV0_EPF0_VF2_0_CARDBUS_CIS_PTR 0x0028 #define cfgBIF_CFG_DEV0_EPF0_VF2_0_ADAPTER_ID 0x002c #define cfgBIF_CFG_DEV0_EPF0_VF2_0_ROM_BASE_ADDR 0x0030 #define cfgBIF_CFG_DEV0_EPF0_VF2_0_CAP_PTR 0x0034 #define cfgBIF_CFG_DEV0_EPF0_VF2_0_INTERRUPT_LINE 0x003c #define cfgBIF_CFG_DEV0_EPF0_VF2_0_INTERRUPT_PIN 0x003d #define cfgBIF_CFG_DEV0_EPF0_VF2_0_MIN_GRANT 0x003e #define cfgBIF_CFG_DEV0_EPF0_VF2_0_MAX_LATENCY 0x003f #define cfgBIF_CFG_DEV0_EPF0_VF2_0_PCIE_CAP_LIST 0x0064 #define cfgBIF_CFG_DEV0_EPF0_VF2_0_PCIE_CAP 0x0066 #define cfgBIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CAP 0x0068 #define cfgBIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CNTL 0x006c #define cfgBIF_CFG_DEV0_EPF0_VF2_0_DEVICE_STATUS 0x006e #define cfgBIF_CFG_DEV0_EPF0_VF2_0_LINK_CAP 0x0070 #define cfgBIF_CFG_DEV0_EPF0_VF2_0_LINK_CNTL 0x0074 #define cfgBIF_CFG_DEV0_EPF0_VF2_0_LINK_STATUS 0x0076 #define cfgBIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CAP2 0x0088 #define cfgBIF_CFG_DEV0_EPF0_VF2_0_DEVICE_CNTL2 0x008c #define cfgBIF_CFG_DEV0_EPF0_VF2_0_DEVICE_STATUS2 0x008e #define cfgBIF_CFG_DEV0_EPF0_VF2_0_LINK_CAP2 0x0090 #define cfgBIF_CFG_DEV0_EPF0_VF2_0_LINK_CNTL2 0x0094 #define cfgBIF_CFG_DEV0_EPF0_VF2_0_LINK_STATUS2 0x0096 #define cfgBIF_CFG_DEV0_EPF0_VF2_0_MSI_CAP_LIST 0x00a0 #define cfgBIF_CFG_DEV0_EPF0_VF2_0_MSI_MSG_CNTL 0x00a2 #define cfgBIF_CFG_DEV0_EPF0_VF2_0_MSI_MSG_ADDR_LO 0x00a4 #define cfgBIF_CFG_DEV0_EPF0_VF2_0_MSI_MSG_ADDR_HI 0x00a8 #define cfgBIF_CFG_DEV0_EPF0_VF2_0_MSI_MSG_DATA 0x00a8 #define cfgBIF_CFG_DEV0_EPF0_VF2_0_MSI_MASK 0x00ac #define cfgBIF_CFG_DEV0_EPF0_VF2_0_MSI_MSG_DATA_64 0x00ac #define cfgBIF_CFG_DEV0_EPF0_VF2_0_MSI_MASK_64 0x00b0 #define cfgBIF_CFG_DEV0_EPF0_VF2_0_MSI_PENDING 0x00b0 #define cfgBIF_CFG_DEV0_EPF0_VF2_0_MSI_PENDING_64 0x00b4 #define cfgBIF_CFG_DEV0_EPF0_VF2_0_MSIX_CAP_LIST 0x00c0 #define cfgBIF_CFG_DEV0_EPF0_VF2_0_MSIX_MSG_CNTL 0x00c2 #define cfgBIF_CFG_DEV0_EPF0_VF2_0_MSIX_TABLE 0x00c4 #define cfgBIF_CFG_DEV0_EPF0_VF2_0_MSIX_PBA 0x00c8 #define cfgBIF_CFG_DEV0_EPF0_VF2_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x0100 #define cfgBIF_CFG_DEV0_EPF0_VF2_0_PCIE_VENDOR_SPECIFIC_HDR 0x0104 #define cfgBIF_CFG_DEV0_EPF0_VF2_0_PCIE_VENDOR_SPECIFIC1 0x0108 #define cfgBIF_CFG_DEV0_EPF0_VF2_0_PCIE_VENDOR_SPECIFIC2 0x010c #define cfgBIF_CFG_DEV0_EPF0_VF2_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x0150 #define cfgBIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_STATUS 0x0154 #define cfgBIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_MASK 0x0158 #define cfgBIF_CFG_DEV0_EPF0_VF2_0_PCIE_UNCORR_ERR_SEVERITY 0x015c #define cfgBIF_CFG_DEV0_EPF0_VF2_0_PCIE_CORR_ERR_STATUS 0x0160 #define cfgBIF_CFG_DEV0_EPF0_VF2_0_PCIE_CORR_ERR_MASK 0x0164 #define cfgBIF_CFG_DEV0_EPF0_VF2_0_PCIE_ADV_ERR_CAP_CNTL 0x0168 #define cfgBIF_CFG_DEV0_EPF0_VF2_0_PCIE_HDR_LOG0 0x016c #define cfgBIF_CFG_DEV0_EPF0_VF2_0_PCIE_HDR_LOG1 0x0170 #define cfgBIF_CFG_DEV0_EPF0_VF2_0_PCIE_HDR_LOG2 0x0174 #define cfgBIF_CFG_DEV0_EPF0_VF2_0_PCIE_HDR_LOG3 0x0178 #define cfgBIF_CFG_DEV0_EPF0_VF2_0_PCIE_TLP_PREFIX_LOG0 0x0188 #define cfgBIF_CFG_DEV0_EPF0_VF2_0_PCIE_TLP_PREFIX_LOG1 0x018c #define cfgBIF_CFG_DEV0_EPF0_VF2_0_PCIE_TLP_PREFIX_LOG2 0x0190 #define cfgBIF_CFG_DEV0_EPF0_VF2_0_PCIE_TLP_PREFIX_LOG3 0x0194 #define cfgBIF_CFG_DEV0_EPF0_VF2_0_PCIE_ATS_ENH_CAP_LIST 0x02b0 #define cfgBIF_CFG_DEV0_EPF0_VF2_0_PCIE_ATS_CAP 0x02b4 #define cfgBIF_CFG_DEV0_EPF0_VF2_0_PCIE_ATS_CNTL 0x02b6 #define cfgBIF_CFG_DEV0_EPF0_VF2_0_PCIE_ARI_ENH_CAP_LIST 0x0328 #define cfgBIF_CFG_DEV0_EPF0_VF2_0_PCIE_ARI_CAP 0x032c #define cfgBIF_CFG_DEV0_EPF0_VF2_0_PCIE_ARI_CNTL 0x032e // addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf3_bifcfgdecp // base address: 0x0 #define cfgBIF_CFG_DEV0_EPF0_VF3_0_VENDOR_ID 0x0000 #define cfgBIF_CFG_DEV0_EPF0_VF3_0_DEVICE_ID 0x0002 #define cfgBIF_CFG_DEV0_EPF0_VF3_0_COMMAND 0x0004 #define cfgBIF_CFG_DEV0_EPF0_VF3_0_STATUS 0x0006 #define cfgBIF_CFG_DEV0_EPF0_VF3_0_REVISION_ID 0x0008 #define cfgBIF_CFG_DEV0_EPF0_VF3_0_PROG_INTERFACE 0x0009 #define cfgBIF_CFG_DEV0_EPF0_VF3_0_SUB_CLASS 0x000a #define cfgBIF_CFG_DEV0_EPF0_VF3_0_BASE_CLASS 0x000b #define cfgBIF_CFG_DEV0_EPF0_VF3_0_CACHE_LINE 0x000c #define cfgBIF_CFG_DEV0_EPF0_VF3_0_LATENCY 0x000d #define cfgBIF_CFG_DEV0_EPF0_VF3_0_HEADER 0x000e #define cfgBIF_CFG_DEV0_EPF0_VF3_0_BIST 0x000f #define cfgBIF_CFG_DEV0_EPF0_VF3_0_BASE_ADDR_1 0x0010 #define cfgBIF_CFG_DEV0_EPF0_VF3_0_BASE_ADDR_2 0x0014 #define cfgBIF_CFG_DEV0_EPF0_VF3_0_BASE_ADDR_3 0x0018 #define cfgBIF_CFG_DEV0_EPF0_VF3_0_BASE_ADDR_4 0x001c #define cfgBIF_CFG_DEV0_EPF0_VF3_0_BASE_ADDR_5 0x0020 #define cfgBIF_CFG_DEV0_EPF0_VF3_0_BASE_ADDR_6 0x0024 #define cfgBIF_CFG_DEV0_EPF0_VF3_0_CARDBUS_CIS_PTR 0x0028 #define cfgBIF_CFG_DEV0_EPF0_VF3_0_ADAPTER_ID 0x002c #define cfgBIF_CFG_DEV0_EPF0_VF3_0_ROM_BASE_ADDR 0x0030 #define cfgBIF_CFG_DEV0_EPF0_VF3_0_CAP_PTR 0x0034 #define cfgBIF_CFG_DEV0_EPF0_VF3_0_INTERRUPT_LINE 0x003c #define cfgBIF_CFG_DEV0_EPF0_VF3_0_INTERRUPT_PIN 0x003d #define cfgBIF_CFG_DEV0_EPF0_VF3_0_MIN_GRANT 0x003e #define cfgBIF_CFG_DEV0_EPF0_VF3_0_MAX_LATENCY 0x003f #define cfgBIF_CFG_DEV0_EPF0_VF3_0_PCIE_CAP_LIST 0x0064 #define cfgBIF_CFG_DEV0_EPF0_VF3_0_PCIE_CAP 0x0066 #define cfgBIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CAP 0x0068 #define cfgBIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CNTL 0x006c #define cfgBIF_CFG_DEV0_EPF0_VF3_0_DEVICE_STATUS 0x006e #define cfgBIF_CFG_DEV0_EPF0_VF3_0_LINK_CAP 0x0070 #define cfgBIF_CFG_DEV0_EPF0_VF3_0_LINK_CNTL 0x0074 #define cfgBIF_CFG_DEV0_EPF0_VF3_0_LINK_STATUS 0x0076 #define cfgBIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CAP2 0x0088 #define cfgBIF_CFG_DEV0_EPF0_VF3_0_DEVICE_CNTL2 0x008c #define cfgBIF_CFG_DEV0_EPF0_VF3_0_DEVICE_STATUS2 0x008e #define cfgBIF_CFG_DEV0_EPF0_VF3_0_LINK_CAP2 0x0090 #define cfgBIF_CFG_DEV0_EPF0_VF3_0_LINK_CNTL2 0x0094 #define cfgBIF_CFG_DEV0_EPF0_VF3_0_LINK_STATUS2 0x0096 #define cfgBIF_CFG_DEV0_EPF0_VF3_0_MSI_CAP_LIST 0x00a0 #define cfgBIF_CFG_DEV0_EPF0_VF3_0_MSI_MSG_CNTL 0x00a2 #define cfgBIF_CFG_DEV0_EPF0_VF3_0_MSI_MSG_ADDR_LO 0x00a4 #define cfgBIF_CFG_DEV0_EPF0_VF3_0_MSI_MSG_ADDR_HI 0x00a8 #define cfgBIF_CFG_DEV0_EPF0_VF3_0_MSI_MSG_DATA 0x00a8 #define cfgBIF_CFG_DEV0_EPF0_VF3_0_MSI_MASK 0x00ac #define cfgBIF_CFG_DEV0_EPF0_VF3_0_MSI_MSG_DATA_64 0x00ac #define cfgBIF_CFG_DEV0_EPF0_VF3_0_MSI_MASK_64 0x00b0 #define cfgBIF_CFG_DEV0_EPF0_VF3_0_MSI_PENDING 0x00b0 #define cfgBIF_CFG_DEV0_EPF0_VF3_0_MSI_PENDING_64 0x00b4 #define cfgBIF_CFG_DEV0_EPF0_VF3_0_MSIX_CAP_LIST 0x00c0 #define cfgBIF_CFG_DEV0_EPF0_VF3_0_MSIX_MSG_CNTL 0x00c2 #define cfgBIF_CFG_DEV0_EPF0_VF3_0_MSIX_TABLE 0x00c4 #define cfgBIF_CFG_DEV0_EPF0_VF3_0_MSIX_PBA 0x00c8 #define cfgBIF_CFG_DEV0_EPF0_VF3_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x0100 #define cfgBIF_CFG_DEV0_EPF0_VF3_0_PCIE_VENDOR_SPECIFIC_HDR 0x0104 #define cfgBIF_CFG_DEV0_EPF0_VF3_0_PCIE_VENDOR_SPECIFIC1 0x0108 #define cfgBIF_CFG_DEV0_EPF0_VF3_0_PCIE_VENDOR_SPECIFIC2 0x010c #define cfgBIF_CFG_DEV0_EPF0_VF3_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x0150 #define cfgBIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_STATUS 0x0154 #define cfgBIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_MASK 0x0158 #define cfgBIF_CFG_DEV0_EPF0_VF3_0_PCIE_UNCORR_ERR_SEVERITY 0x015c #define cfgBIF_CFG_DEV0_EPF0_VF3_0_PCIE_CORR_ERR_STATUS 0x0160 #define cfgBIF_CFG_DEV0_EPF0_VF3_0_PCIE_CORR_ERR_MASK 0x0164 #define cfgBIF_CFG_DEV0_EPF0_VF3_0_PCIE_ADV_ERR_CAP_CNTL 0x0168 #define cfgBIF_CFG_DEV0_EPF0_VF3_0_PCIE_HDR_LOG0 0x016c #define cfgBIF_CFG_DEV0_EPF0_VF3_0_PCIE_HDR_LOG1 0x0170 #define cfgBIF_CFG_DEV0_EPF0_VF3_0_PCIE_HDR_LOG2 0x0174 #define cfgBIF_CFG_DEV0_EPF0_VF3_0_PCIE_HDR_LOG3 0x0178 #define cfgBIF_CFG_DEV0_EPF0_VF3_0_PCIE_TLP_PREFIX_LOG0 0x0188 #define cfgBIF_CFG_DEV0_EPF0_VF3_0_PCIE_TLP_PREFIX_LOG1 0x018c #define cfgBIF_CFG_DEV0_EPF0_VF3_0_PCIE_TLP_PREFIX_LOG2 0x0190 #define cfgBIF_CFG_DEV0_EPF0_VF3_0_PCIE_TLP_PREFIX_LOG3 0x0194 #define cfgBIF_CFG_DEV0_EPF0_VF3_0_PCIE_ATS_ENH_CAP_LIST 0x02b0 #define cfgBIF_CFG_DEV0_EPF0_VF3_0_PCIE_ATS_CAP 0x02b4 #define cfgBIF_CFG_DEV0_EPF0_VF3_0_PCIE_ATS_CNTL 0x02b6 #define cfgBIF_CFG_DEV0_EPF0_VF3_0_PCIE_ARI_ENH_CAP_LIST 0x0328 #define cfgBIF_CFG_DEV0_EPF0_VF3_0_PCIE_ARI_CAP 0x032c #define cfgBIF_CFG_DEV0_EPF0_VF3_0_PCIE_ARI_CNTL 0x032e // addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf4_bifcfgdecp // base address: 0x0 #define cfgBIF_CFG_DEV0_EPF0_VF4_0_VENDOR_ID 0x0000 #define cfgBIF_CFG_DEV0_EPF0_VF4_0_DEVICE_ID 0x0002 #define cfgBIF_CFG_DEV0_EPF0_VF4_0_COMMAND 0x0004 #define cfgBIF_CFG_DEV0_EPF0_VF4_0_STATUS 0x0006 #define cfgBIF_CFG_DEV0_EPF0_VF4_0_REVISION_ID 0x0008 #define cfgBIF_CFG_DEV0_EPF0_VF4_0_PROG_INTERFACE 0x0009 #define cfgBIF_CFG_DEV0_EPF0_VF4_0_SUB_CLASS 0x000a #define cfgBIF_CFG_DEV0_EPF0_VF4_0_BASE_CLASS 0x000b #define cfgBIF_CFG_DEV0_EPF0_VF4_0_CACHE_LINE 0x000c #define cfgBIF_CFG_DEV0_EPF0_VF4_0_LATENCY 0x000d #define cfgBIF_CFG_DEV0_EPF0_VF4_0_HEADER 0x000e #define cfgBIF_CFG_DEV0_EPF0_VF4_0_BIST 0x000f #define cfgBIF_CFG_DEV0_EPF0_VF4_0_BASE_ADDR_1 0x0010 #define cfgBIF_CFG_DEV0_EPF0_VF4_0_BASE_ADDR_2 0x0014 #define cfgBIF_CFG_DEV0_EPF0_VF4_0_BASE_ADDR_3 0x0018 #define cfgBIF_CFG_DEV0_EPF0_VF4_0_BASE_ADDR_4 0x001c #define cfgBIF_CFG_DEV0_EPF0_VF4_0_BASE_ADDR_5 0x0020 #define cfgBIF_CFG_DEV0_EPF0_VF4_0_BASE_ADDR_6 0x0024 #define cfgBIF_CFG_DEV0_EPF0_VF4_0_CARDBUS_CIS_PTR 0x0028 #define cfgBIF_CFG_DEV0_EPF0_VF4_0_ADAPTER_ID 0x002c #define cfgBIF_CFG_DEV0_EPF0_VF4_0_ROM_BASE_ADDR 0x0030 #define cfgBIF_CFG_DEV0_EPF0_VF4_0_CAP_PTR 0x0034 #define cfgBIF_CFG_DEV0_EPF0_VF4_0_INTERRUPT_LINE 0x003c #define cfgBIF_CFG_DEV0_EPF0_VF4_0_INTERRUPT_PIN 0x003d #define cfgBIF_CFG_DEV0_EPF0_VF4_0_MIN_GRANT 0x003e #define cfgBIF_CFG_DEV0_EPF0_VF4_0_MAX_LATENCY 0x003f #define cfgBIF_CFG_DEV0_EPF0_VF4_0_PCIE_CAP_LIST 0x0064 #define cfgBIF_CFG_DEV0_EPF0_VF4_0_PCIE_CAP 0x0066 #define cfgBIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CAP 0x0068 #define cfgBIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CNTL 0x006c #define cfgBIF_CFG_DEV0_EPF0_VF4_0_DEVICE_STATUS 0x006e #define cfgBIF_CFG_DEV0_EPF0_VF4_0_LINK_CAP 0x0070 #define cfgBIF_CFG_DEV0_EPF0_VF4_0_LINK_CNTL 0x0074 #define cfgBIF_CFG_DEV0_EPF0_VF4_0_LINK_STATUS 0x0076 #define cfgBIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CAP2 0x0088 #define cfgBIF_CFG_DEV0_EPF0_VF4_0_DEVICE_CNTL2 0x008c #define cfgBIF_CFG_DEV0_EPF0_VF4_0_DEVICE_STATUS2 0x008e #define cfgBIF_CFG_DEV0_EPF0_VF4_0_LINK_CAP2 0x0090 #define cfgBIF_CFG_DEV0_EPF0_VF4_0_LINK_CNTL2 0x0094 #define cfgBIF_CFG_DEV0_EPF0_VF4_0_LINK_STATUS2 0x0096 #define cfgBIF_CFG_DEV0_EPF0_VF4_0_MSI_CAP_LIST 0x00a0 #define cfgBIF_CFG_DEV0_EPF0_VF4_0_MSI_MSG_CNTL 0x00a2 #define cfgBIF_CFG_DEV0_EPF0_VF4_0_MSI_MSG_ADDR_LO 0x00a4 #define cfgBIF_CFG_DEV0_EPF0_VF4_0_MSI_MSG_ADDR_HI 0x00a8 #define cfgBIF_CFG_DEV0_EPF0_VF4_0_MSI_MSG_DATA 0x00a8 #define cfgBIF_CFG_DEV0_EPF0_VF4_0_MSI_MASK 0x00ac #define cfgBIF_CFG_DEV0_EPF0_VF4_0_MSI_MSG_DATA_64 0x00ac #define cfgBIF_CFG_DEV0_EPF0_VF4_0_MSI_MASK_64 0x00b0 #define cfgBIF_CFG_DEV0_EPF0_VF4_0_MSI_PENDING 0x00b0 #define cfgBIF_CFG_DEV0_EPF0_VF4_0_MSI_PENDING_64 0x00b4 #define cfgBIF_CFG_DEV0_EPF0_VF4_0_MSIX_CAP_LIST 0x00c0 #define cfgBIF_CFG_DEV0_EPF0_VF4_0_MSIX_MSG_CNTL 0x00c2 #define cfgBIF_CFG_DEV0_EPF0_VF4_0_MSIX_TABLE 0x00c4 #define cfgBIF_CFG_DEV0_EPF0_VF4_0_MSIX_PBA 0x00c8 #define cfgBIF_CFG_DEV0_EPF0_VF4_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x0100 #define cfgBIF_CFG_DEV0_EPF0_VF4_0_PCIE_VENDOR_SPECIFIC_HDR 0x0104 #define cfgBIF_CFG_DEV0_EPF0_VF4_0_PCIE_VENDOR_SPECIFIC1 0x0108 #define cfgBIF_CFG_DEV0_EPF0_VF4_0_PCIE_VENDOR_SPECIFIC2 0x010c #define cfgBIF_CFG_DEV0_EPF0_VF4_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x0150 #define cfgBIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_STATUS 0x0154 #define cfgBIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_MASK 0x0158 #define cfgBIF_CFG_DEV0_EPF0_VF4_0_PCIE_UNCORR_ERR_SEVERITY 0x015c #define cfgBIF_CFG_DEV0_EPF0_VF4_0_PCIE_CORR_ERR_STATUS 0x0160 #define cfgBIF_CFG_DEV0_EPF0_VF4_0_PCIE_CORR_ERR_MASK 0x0164 #define cfgBIF_CFG_DEV0_EPF0_VF4_0_PCIE_ADV_ERR_CAP_CNTL 0x0168 #define cfgBIF_CFG_DEV0_EPF0_VF4_0_PCIE_HDR_LOG0 0x016c #define cfgBIF_CFG_DEV0_EPF0_VF4_0_PCIE_HDR_LOG1 0x0170 #define cfgBIF_CFG_DEV0_EPF0_VF4_0_PCIE_HDR_LOG2 0x0174 #define cfgBIF_CFG_DEV0_EPF0_VF4_0_PCIE_HDR_LOG3 0x0178 #define cfgBIF_CFG_DEV0_EPF0_VF4_0_PCIE_TLP_PREFIX_LOG0 0x0188 #define cfgBIF_CFG_DEV0_EPF0_VF4_0_PCIE_TLP_PREFIX_LOG1 0x018c #define cfgBIF_CFG_DEV0_EPF0_VF4_0_PCIE_TLP_PREFIX_LOG2 0x0190 #define cfgBIF_CFG_DEV0_EPF0_VF4_0_PCIE_TLP_PREFIX_LOG3 0x0194 #define cfgBIF_CFG_DEV0_EPF0_VF4_0_PCIE_ATS_ENH_CAP_LIST 0x02b0 #define cfgBIF_CFG_DEV0_EPF0_VF4_0_PCIE_ATS_CAP 0x02b4 #define cfgBIF_CFG_DEV0_EPF0_VF4_0_PCIE_ATS_CNTL 0x02b6 #define cfgBIF_CFG_DEV0_EPF0_VF4_0_PCIE_ARI_ENH_CAP_LIST 0x0328 #define cfgBIF_CFG_DEV0_EPF0_VF4_0_PCIE_ARI_CAP 0x032c #define cfgBIF_CFG_DEV0_EPF0_VF4_0_PCIE_ARI_CNTL 0x032e // addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf5_bifcfgdecp // base address: 0x0 #define cfgBIF_CFG_DEV0_EPF0_VF5_0_VENDOR_ID 0x0000 #define cfgBIF_CFG_DEV0_EPF0_VF5_0_DEVICE_ID 0x0002 #define cfgBIF_CFG_DEV0_EPF0_VF5_0_COMMAND 0x0004 #define cfgBIF_CFG_DEV0_EPF0_VF5_0_STATUS 0x0006 #define cfgBIF_CFG_DEV0_EPF0_VF5_0_REVISION_ID 0x0008 #define cfgBIF_CFG_DEV0_EPF0_VF5_0_PROG_INTERFACE 0x0009 #define cfgBIF_CFG_DEV0_EPF0_VF5_0_SUB_CLASS 0x000a #define cfgBIF_CFG_DEV0_EPF0_VF5_0_BASE_CLASS 0x000b #define cfgBIF_CFG_DEV0_EPF0_VF5_0_CACHE_LINE 0x000c #define cfgBIF_CFG_DEV0_EPF0_VF5_0_LATENCY 0x000d #define cfgBIF_CFG_DEV0_EPF0_VF5_0_HEADER 0x000e #define cfgBIF_CFG_DEV0_EPF0_VF5_0_BIST 0x000f #define cfgBIF_CFG_DEV0_EPF0_VF5_0_BASE_ADDR_1 0x0010 #define cfgBIF_CFG_DEV0_EPF0_VF5_0_BASE_ADDR_2 0x0014 #define cfgBIF_CFG_DEV0_EPF0_VF5_0_BASE_ADDR_3 0x0018 #define cfgBIF_CFG_DEV0_EPF0_VF5_0_BASE_ADDR_4 0x001c #define cfgBIF_CFG_DEV0_EPF0_VF5_0_BASE_ADDR_5 0x0020 #define cfgBIF_CFG_DEV0_EPF0_VF5_0_BASE_ADDR_6 0x0024 #define cfgBIF_CFG_DEV0_EPF0_VF5_0_CARDBUS_CIS_PTR 0x0028 #define cfgBIF_CFG_DEV0_EPF0_VF5_0_ADAPTER_ID 0x002c #define cfgBIF_CFG_DEV0_EPF0_VF5_0_ROM_BASE_ADDR 0x0030 #define cfgBIF_CFG_DEV0_EPF0_VF5_0_CAP_PTR 0x0034 #define cfgBIF_CFG_DEV0_EPF0_VF5_0_INTERRUPT_LINE 0x003c #define cfgBIF_CFG_DEV0_EPF0_VF5_0_INTERRUPT_PIN 0x003d #define cfgBIF_CFG_DEV0_EPF0_VF5_0_MIN_GRANT 0x003e #define cfgBIF_CFG_DEV0_EPF0_VF5_0_MAX_LATENCY 0x003f #define cfgBIF_CFG_DEV0_EPF0_VF5_0_PCIE_CAP_LIST 0x0064 #define cfgBIF_CFG_DEV0_EPF0_VF5_0_PCIE_CAP 0x0066 #define cfgBIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CAP 0x0068 #define cfgBIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CNTL 0x006c #define cfgBIF_CFG_DEV0_EPF0_VF5_0_DEVICE_STATUS 0x006e #define cfgBIF_CFG_DEV0_EPF0_VF5_0_LINK_CAP 0x0070 #define cfgBIF_CFG_DEV0_EPF0_VF5_0_LINK_CNTL 0x0074 #define cfgBIF_CFG_DEV0_EPF0_VF5_0_LINK_STATUS 0x0076 #define cfgBIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CAP2 0x0088 #define cfgBIF_CFG_DEV0_EPF0_VF5_0_DEVICE_CNTL2 0x008c #define cfgBIF_CFG_DEV0_EPF0_VF5_0_DEVICE_STATUS2 0x008e #define cfgBIF_CFG_DEV0_EPF0_VF5_0_LINK_CAP2 0x0090 #define cfgBIF_CFG_DEV0_EPF0_VF5_0_LINK_CNTL2 0x0094 #define cfgBIF_CFG_DEV0_EPF0_VF5_0_LINK_STATUS2 0x0096 #define cfgBIF_CFG_DEV0_EPF0_VF5_0_MSI_CAP_LIST 0x00a0 #define cfgBIF_CFG_DEV0_EPF0_VF5_0_MSI_MSG_CNTL 0x00a2 #define cfgBIF_CFG_DEV0_EPF0_VF5_0_MSI_MSG_ADDR_LO 0x00a4 #define cfgBIF_CFG_DEV0_EPF0_VF5_0_MSI_MSG_ADDR_HI 0x00a8 #define cfgBIF_CFG_DEV0_EPF0_VF5_0_MSI_MSG_DATA 0x00a8 #define cfgBIF_CFG_DEV0_EPF0_VF5_0_MSI_MASK 0x00ac #define cfgBIF_CFG_DEV0_EPF0_VF5_0_MSI_MSG_DATA_64 0x00ac #define cfgBIF_CFG_DEV0_EPF0_VF5_0_MSI_MASK_64 0x00b0 #define cfgBIF_CFG_DEV0_EPF0_VF5_0_MSI_PENDING 0x00b0 #define cfgBIF_CFG_DEV0_EPF0_VF5_0_MSI_PENDING_64 0x00b4 #define cfgBIF_CFG_DEV0_EPF0_VF5_0_MSIX_CAP_LIST 0x00c0 #define cfgBIF_CFG_DEV0_EPF0_VF5_0_MSIX_MSG_CNTL 0x00c2 #define cfgBIF_CFG_DEV0_EPF0_VF5_0_MSIX_TABLE 0x00c4 #define cfgBIF_CFG_DEV0_EPF0_VF5_0_MSIX_PBA 0x00c8 #define cfgBIF_CFG_DEV0_EPF0_VF5_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x0100 #define cfgBIF_CFG_DEV0_EPF0_VF5_0_PCIE_VENDOR_SPECIFIC_HDR 0x0104 #define cfgBIF_CFG_DEV0_EPF0_VF5_0_PCIE_VENDOR_SPECIFIC1 0x0108 #define cfgBIF_CFG_DEV0_EPF0_VF5_0_PCIE_VENDOR_SPECIFIC2 0x010c #define cfgBIF_CFG_DEV0_EPF0_VF5_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x0150 #define cfgBIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_STATUS 0x0154 #define cfgBIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_MASK 0x0158 #define cfgBIF_CFG_DEV0_EPF0_VF5_0_PCIE_UNCORR_ERR_SEVERITY 0x015c #define cfgBIF_CFG_DEV0_EPF0_VF5_0_PCIE_CORR_ERR_STATUS 0x0160 #define cfgBIF_CFG_DEV0_EPF0_VF5_0_PCIE_CORR_ERR_MASK 0x0164 #define cfgBIF_CFG_DEV0_EPF0_VF5_0_PCIE_ADV_ERR_CAP_CNTL 0x0168 #define cfgBIF_CFG_DEV0_EPF0_VF5_0_PCIE_HDR_LOG0 0x016c #define cfgBIF_CFG_DEV0_EPF0_VF5_0_PCIE_HDR_LOG1 0x0170 #define cfgBIF_CFG_DEV0_EPF0_VF5_0_PCIE_HDR_LOG2 0x0174 #define cfgBIF_CFG_DEV0_EPF0_VF5_0_PCIE_HDR_LOG3 0x0178 #define cfgBIF_CFG_DEV0_EPF0_VF5_0_PCIE_TLP_PREFIX_LOG0 0x0188 #define cfgBIF_CFG_DEV0_EPF0_VF5_0_PCIE_TLP_PREFIX_LOG1 0x018c #define cfgBIF_CFG_DEV0_EPF0_VF5_0_PCIE_TLP_PREFIX_LOG2 0x0190 #define cfgBIF_CFG_DEV0_EPF0_VF5_0_PCIE_TLP_PREFIX_LOG3 0x0194 #define cfgBIF_CFG_DEV0_EPF0_VF5_0_PCIE_ATS_ENH_CAP_LIST 0x02b0 #define cfgBIF_CFG_DEV0_EPF0_VF5_0_PCIE_ATS_CAP 0x02b4 #define cfgBIF_CFG_DEV0_EPF0_VF5_0_PCIE_ATS_CNTL 0x02b6 #define cfgBIF_CFG_DEV0_EPF0_VF5_0_PCIE_ARI_ENH_CAP_LIST 0x0328 #define cfgBIF_CFG_DEV0_EPF0_VF5_0_PCIE_ARI_CAP 0x032c #define cfgBIF_CFG_DEV0_EPF0_VF5_0_PCIE_ARI_CNTL 0x032e // addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf6_bifcfgdecp // base address: 0x0 #define cfgBIF_CFG_DEV0_EPF0_VF6_0_VENDOR_ID 0x0000 #define cfgBIF_CFG_DEV0_EPF0_VF6_0_DEVICE_ID 0x0002 #define cfgBIF_CFG_DEV0_EPF0_VF6_0_COMMAND 0x0004 #define cfgBIF_CFG_DEV0_EPF0_VF6_0_STATUS 0x0006 #define cfgBIF_CFG_DEV0_EPF0_VF6_0_REVISION_ID 0x0008 #define cfgBIF_CFG_DEV0_EPF0_VF6_0_PROG_INTERFACE 0x0009 #define cfgBIF_CFG_DEV0_EPF0_VF6_0_SUB_CLASS 0x000a #define cfgBIF_CFG_DEV0_EPF0_VF6_0_BASE_CLASS 0x000b #define cfgBIF_CFG_DEV0_EPF0_VF6_0_CACHE_LINE 0x000c #define cfgBIF_CFG_DEV0_EPF0_VF6_0_LATENCY 0x000d #define cfgBIF_CFG_DEV0_EPF0_VF6_0_HEADER 0x000e #define cfgBIF_CFG_DEV0_EPF0_VF6_0_BIST 0x000f #define cfgBIF_CFG_DEV0_EPF0_VF6_0_BASE_ADDR_1 0x0010 #define cfgBIF_CFG_DEV0_EPF0_VF6_0_BASE_ADDR_2 0x0014 #define cfgBIF_CFG_DEV0_EPF0_VF6_0_BASE_ADDR_3 0x0018 #define cfgBIF_CFG_DEV0_EPF0_VF6_0_BASE_ADDR_4 0x001c #define cfgBIF_CFG_DEV0_EPF0_VF6_0_BASE_ADDR_5 0x0020 #define cfgBIF_CFG_DEV0_EPF0_VF6_0_BASE_ADDR_6 0x0024 #define cfgBIF_CFG_DEV0_EPF0_VF6_0_CARDBUS_CIS_PTR 0x0028 #define cfgBIF_CFG_DEV0_EPF0_VF6_0_ADAPTER_ID 0x002c #define cfgBIF_CFG_DEV0_EPF0_VF6_0_ROM_BASE_ADDR 0x0030 #define cfgBIF_CFG_DEV0_EPF0_VF6_0_CAP_PTR 0x0034 #define cfgBIF_CFG_DEV0_EPF0_VF6_0_INTERRUPT_LINE 0x003c #define cfgBIF_CFG_DEV0_EPF0_VF6_0_INTERRUPT_PIN 0x003d #define cfgBIF_CFG_DEV0_EPF0_VF6_0_MIN_GRANT 0x003e #define cfgBIF_CFG_DEV0_EPF0_VF6_0_MAX_LATENCY 0x003f #define cfgBIF_CFG_DEV0_EPF0_VF6_0_PCIE_CAP_LIST 0x0064 #define cfgBIF_CFG_DEV0_EPF0_VF6_0_PCIE_CAP 0x0066 #define cfgBIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CAP 0x0068 #define cfgBIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CNTL 0x006c #define cfgBIF_CFG_DEV0_EPF0_VF6_0_DEVICE_STATUS 0x006e #define cfgBIF_CFG_DEV0_EPF0_VF6_0_LINK_CAP 0x0070 #define cfgBIF_CFG_DEV0_EPF0_VF6_0_LINK_CNTL 0x0074 #define cfgBIF_CFG_DEV0_EPF0_VF6_0_LINK_STATUS 0x0076 #define cfgBIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CAP2 0x0088 #define cfgBIF_CFG_DEV0_EPF0_VF6_0_DEVICE_CNTL2 0x008c #define cfgBIF_CFG_DEV0_EPF0_VF6_0_DEVICE_STATUS2 0x008e #define cfgBIF_CFG_DEV0_EPF0_VF6_0_LINK_CAP2 0x0090 #define cfgBIF_CFG_DEV0_EPF0_VF6_0_LINK_CNTL2 0x0094 #define cfgBIF_CFG_DEV0_EPF0_VF6_0_LINK_STATUS2 0x0096 #define cfgBIF_CFG_DEV0_EPF0_VF6_0_MSI_CAP_LIST 0x00a0 #define cfgBIF_CFG_DEV0_EPF0_VF6_0_MSI_MSG_CNTL 0x00a2 #define cfgBIF_CFG_DEV0_EPF0_VF6_0_MSI_MSG_ADDR_LO 0x00a4 #define cfgBIF_CFG_DEV0_EPF0_VF6_0_MSI_MSG_ADDR_HI 0x00a8 #define cfgBIF_CFG_DEV0_EPF0_VF6_0_MSI_MSG_DATA 0x00a8 #define cfgBIF_CFG_DEV0_EPF0_VF6_0_MSI_MASK 0x00ac #define cfgBIF_CFG_DEV0_EPF0_VF6_0_MSI_MSG_DATA_64 0x00ac #define cfgBIF_CFG_DEV0_EPF0_VF6_0_MSI_MASK_64 0x00b0 #define cfgBIF_CFG_DEV0_EPF0_VF6_0_MSI_PENDING 0x00b0 #define cfgBIF_CFG_DEV0_EPF0_VF6_0_MSI_PENDING_64 0x00b4 #define cfgBIF_CFG_DEV0_EPF0_VF6_0_MSIX_CAP_LIST 0x00c0 #define cfgBIF_CFG_DEV0_EPF0_VF6_0_MSIX_MSG_CNTL 0x00c2 #define cfgBIF_CFG_DEV0_EPF0_VF6_0_MSIX_TABLE 0x00c4 #define cfgBIF_CFG_DEV0_EPF0_VF6_0_MSIX_PBA 0x00c8 #define cfgBIF_CFG_DEV0_EPF0_VF6_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x0100 #define cfgBIF_CFG_DEV0_EPF0_VF6_0_PCIE_VENDOR_SPECIFIC_HDR 0x0104 #define cfgBIF_CFG_DEV0_EPF0_VF6_0_PCIE_VENDOR_SPECIFIC1 0x0108 #define cfgBIF_CFG_DEV0_EPF0_VF6_0_PCIE_VENDOR_SPECIFIC2 0x010c #define cfgBIF_CFG_DEV0_EPF0_VF6_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x0150 #define cfgBIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_STATUS 0x0154 #define cfgBIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_MASK 0x0158 #define cfgBIF_CFG_DEV0_EPF0_VF6_0_PCIE_UNCORR_ERR_SEVERITY 0x015c #define cfgBIF_CFG_DEV0_EPF0_VF6_0_PCIE_CORR_ERR_STATUS 0x0160 #define cfgBIF_CFG_DEV0_EPF0_VF6_0_PCIE_CORR_ERR_MASK 0x0164 #define cfgBIF_CFG_DEV0_EPF0_VF6_0_PCIE_ADV_ERR_CAP_CNTL 0x0168 #define cfgBIF_CFG_DEV0_EPF0_VF6_0_PCIE_HDR_LOG0 0x016c #define cfgBIF_CFG_DEV0_EPF0_VF6_0_PCIE_HDR_LOG1 0x0170 #define cfgBIF_CFG_DEV0_EPF0_VF6_0_PCIE_HDR_LOG2 0x0174 #define cfgBIF_CFG_DEV0_EPF0_VF6_0_PCIE_HDR_LOG3 0x0178 #define cfgBIF_CFG_DEV0_EPF0_VF6_0_PCIE_TLP_PREFIX_LOG0 0x0188 #define cfgBIF_CFG_DEV0_EPF0_VF6_0_PCIE_TLP_PREFIX_LOG1 0x018c #define cfgBIF_CFG_DEV0_EPF0_VF6_0_PCIE_TLP_PREFIX_LOG2 0x0190 #define cfgBIF_CFG_DEV0_EPF0_VF6_0_PCIE_TLP_PREFIX_LOG3 0x0194 #define cfgBIF_CFG_DEV0_EPF0_VF6_0_PCIE_ATS_ENH_CAP_LIST 0x02b0 #define cfgBIF_CFG_DEV0_EPF0_VF6_0_PCIE_ATS_CAP 0x02b4 #define cfgBIF_CFG_DEV0_EPF0_VF6_0_PCIE_ATS_CNTL 0x02b6 #define cfgBIF_CFG_DEV0_EPF0_VF6_0_PCIE_ARI_ENH_CAP_LIST 0x0328 #define cfgBIF_CFG_DEV0_EPF0_VF6_0_PCIE_ARI_CAP 0x032c #define cfgBIF_CFG_DEV0_EPF0_VF6_0_PCIE_ARI_CNTL 0x032e // addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf7_bifcfgdecp // base address: 0x0 #define cfgBIF_CFG_DEV0_EPF0_VF7_0_VENDOR_ID 0x0000 #define cfgBIF_CFG_DEV0_EPF0_VF7_0_DEVICE_ID 0x0002 #define cfgBIF_CFG_DEV0_EPF0_VF7_0_COMMAND 0x0004 #define cfgBIF_CFG_DEV0_EPF0_VF7_0_STATUS 0x0006 #define cfgBIF_CFG_DEV0_EPF0_VF7_0_REVISION_ID 0x0008 #define cfgBIF_CFG_DEV0_EPF0_VF7_0_PROG_INTERFACE 0x0009 #define cfgBIF_CFG_DEV0_EPF0_VF7_0_SUB_CLASS 0x000a #define cfgBIF_CFG_DEV0_EPF0_VF7_0_BASE_CLASS 0x000b #define cfgBIF_CFG_DEV0_EPF0_VF7_0_CACHE_LINE 0x000c #define cfgBIF_CFG_DEV0_EPF0_VF7_0_LATENCY 0x000d #define cfgBIF_CFG_DEV0_EPF0_VF7_0_HEADER 0x000e #define cfgBIF_CFG_DEV0_EPF0_VF7_0_BIST 0x000f #define cfgBIF_CFG_DEV0_EPF0_VF7_0_BASE_ADDR_1 0x0010 #define cfgBIF_CFG_DEV0_EPF0_VF7_0_BASE_ADDR_2 0x0014 #define cfgBIF_CFG_DEV0_EPF0_VF7_0_BASE_ADDR_3 0x0018 #define cfgBIF_CFG_DEV0_EPF0_VF7_0_BASE_ADDR_4 0x001c #define cfgBIF_CFG_DEV0_EPF0_VF7_0_BASE_ADDR_5 0x0020 #define cfgBIF_CFG_DEV0_EPF0_VF7_0_BASE_ADDR_6 0x0024 #define cfgBIF_CFG_DEV0_EPF0_VF7_0_CARDBUS_CIS_PTR 0x0028 #define cfgBIF_CFG_DEV0_EPF0_VF7_0_ADAPTER_ID 0x002c #define cfgBIF_CFG_DEV0_EPF0_VF7_0_ROM_BASE_ADDR 0x0030 #define cfgBIF_CFG_DEV0_EPF0_VF7_0_CAP_PTR 0x0034 #define cfgBIF_CFG_DEV0_EPF0_VF7_0_INTERRUPT_LINE 0x003c #define cfgBIF_CFG_DEV0_EPF0_VF7_0_INTERRUPT_PIN 0x003d #define cfgBIF_CFG_DEV0_EPF0_VF7_0_MIN_GRANT 0x003e #define cfgBIF_CFG_DEV0_EPF0_VF7_0_MAX_LATENCY 0x003f #define cfgBIF_CFG_DEV0_EPF0_VF7_0_PCIE_CAP_LIST 0x0064 #define cfgBIF_CFG_DEV0_EPF0_VF7_0_PCIE_CAP 0x0066 #define cfgBIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CAP 0x0068 #define cfgBIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CNTL 0x006c #define cfgBIF_CFG_DEV0_EPF0_VF7_0_DEVICE_STATUS 0x006e #define cfgBIF_CFG_DEV0_EPF0_VF7_0_LINK_CAP 0x0070 #define cfgBIF_CFG_DEV0_EPF0_VF7_0_LINK_CNTL 0x0074 #define cfgBIF_CFG_DEV0_EPF0_VF7_0_LINK_STATUS 0x0076 #define cfgBIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CAP2 0x0088 #define cfgBIF_CFG_DEV0_EPF0_VF7_0_DEVICE_CNTL2 0x008c #define cfgBIF_CFG_DEV0_EPF0_VF7_0_DEVICE_STATUS2 0x008e #define cfgBIF_CFG_DEV0_EPF0_VF7_0_LINK_CAP2 0x0090 #define cfgBIF_CFG_DEV0_EPF0_VF7_0_LINK_CNTL2 0x0094 #define cfgBIF_CFG_DEV0_EPF0_VF7_0_LINK_STATUS2 0x0096 #define cfgBIF_CFG_DEV0_EPF0_VF7_0_MSI_CAP_LIST 0x00a0 #define cfgBIF_CFG_DEV0_EPF0_VF7_0_MSI_MSG_CNTL 0x00a2 #define cfgBIF_CFG_DEV0_EPF0_VF7_0_MSI_MSG_ADDR_LO 0x00a4 #define cfgBIF_CFG_DEV0_EPF0_VF7_0_MSI_MSG_ADDR_HI 0x00a8 #define cfgBIF_CFG_DEV0_EPF0_VF7_0_MSI_MSG_DATA 0x00a8 #define cfgBIF_CFG_DEV0_EPF0_VF7_0_MSI_MASK 0x00ac #define cfgBIF_CFG_DEV0_EPF0_VF7_0_MSI_MSG_DATA_64 0x00ac #define cfgBIF_CFG_DEV0_EPF0_VF7_0_MSI_MASK_64 0x00b0 #define cfgBIF_CFG_DEV0_EPF0_VF7_0_MSI_PENDING 0x00b0 #define cfgBIF_CFG_DEV0_EPF0_VF7_0_MSI_PENDING_64 0x00b4 #define cfgBIF_CFG_DEV0_EPF0_VF7_0_MSIX_CAP_LIST 0x00c0 #define cfgBIF_CFG_DEV0_EPF0_VF7_0_MSIX_MSG_CNTL 0x00c2 #define cfgBIF_CFG_DEV0_EPF0_VF7_0_MSIX_TABLE 0x00c4 #define cfgBIF_CFG_DEV0_EPF0_VF7_0_MSIX_PBA 0x00c8 #define cfgBIF_CFG_DEV0_EPF0_VF7_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x0100 #define cfgBIF_CFG_DEV0_EPF0_VF7_0_PCIE_VENDOR_SPECIFIC_HDR 0x0104 #define cfgBIF_CFG_DEV0_EPF0_VF7_0_PCIE_VENDOR_SPECIFIC1 0x0108 #define cfgBIF_CFG_DEV0_EPF0_VF7_0_PCIE_VENDOR_SPECIFIC2 0x010c #define cfgBIF_CFG_DEV0_EPF0_VF7_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x0150 #define cfgBIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_STATUS 0x0154 #define cfgBIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_MASK 0x0158 #define cfgBIF_CFG_DEV0_EPF0_VF7_0_PCIE_UNCORR_ERR_SEVERITY 0x015c #define cfgBIF_CFG_DEV0_EPF0_VF7_0_PCIE_CORR_ERR_STATUS 0x0160 #define cfgBIF_CFG_DEV0_EPF0_VF7_0_PCIE_CORR_ERR_MASK 0x0164 #define cfgBIF_CFG_DEV0_EPF0_VF7_0_PCIE_ADV_ERR_CAP_CNTL 0x0168 #define cfgBIF_CFG_DEV0_EPF0_VF7_0_PCIE_HDR_LOG0 0x016c #define cfgBIF_CFG_DEV0_EPF0_VF7_0_PCIE_HDR_LOG1 0x0170 #define cfgBIF_CFG_DEV0_EPF0_VF7_0_PCIE_HDR_LOG2 0x0174 #define cfgBIF_CFG_DEV0_EPF0_VF7_0_PCIE_HDR_LOG3 0x0178 #define cfgBIF_CFG_DEV0_EPF0_VF7_0_PCIE_TLP_PREFIX_LOG0 0x0188 #define cfgBIF_CFG_DEV0_EPF0_VF7_0_PCIE_TLP_PREFIX_LOG1 0x018c #define cfgBIF_CFG_DEV0_EPF0_VF7_0_PCIE_TLP_PREFIX_LOG2 0x0190 #define cfgBIF_CFG_DEV0_EPF0_VF7_0_PCIE_TLP_PREFIX_LOG3 0x0194 #define cfgBIF_CFG_DEV0_EPF0_VF7_0_PCIE_ATS_ENH_CAP_LIST 0x02b0 #define cfgBIF_CFG_DEV0_EPF0_VF7_0_PCIE_ATS_CAP 0x02b4 #define cfgBIF_CFG_DEV0_EPF0_VF7_0_PCIE_ATS_CNTL 0x02b6 #define cfgBIF_CFG_DEV0_EPF0_VF7_0_PCIE_ARI_ENH_CAP_LIST 0x0328 #define cfgBIF_CFG_DEV0_EPF0_VF7_0_PCIE_ARI_CAP 0x032c #define cfgBIF_CFG_DEV0_EPF0_VF7_0_PCIE_ARI_CNTL 0x032e // addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf8_bifcfgdecp // base address: 0x0 #define cfgBIF_CFG_DEV0_EPF0_VF8_0_VENDOR_ID 0x0000 #define cfgBIF_CFG_DEV0_EPF0_VF8_0_DEVICE_ID 0x0002 #define cfgBIF_CFG_DEV0_EPF0_VF8_0_COMMAND 0x0004 #define cfgBIF_CFG_DEV0_EPF0_VF8_0_STATUS 0x0006 #define cfgBIF_CFG_DEV0_EPF0_VF8_0_REVISION_ID 0x0008 #define cfgBIF_CFG_DEV0_EPF0_VF8_0_PROG_INTERFACE 0x0009 #define cfgBIF_CFG_DEV0_EPF0_VF8_0_SUB_CLASS 0x000a #define cfgBIF_CFG_DEV0_EPF0_VF8_0_BASE_CLASS 0x000b #define cfgBIF_CFG_DEV0_EPF0_VF8_0_CACHE_LINE 0x000c #define cfgBIF_CFG_DEV0_EPF0_VF8_0_LATENCY 0x000d #define cfgBIF_CFG_DEV0_EPF0_VF8_0_HEADER 0x000e #define cfgBIF_CFG_DEV0_EPF0_VF8_0_BIST 0x000f #define cfgBIF_CFG_DEV0_EPF0_VF8_0_BASE_ADDR_1 0x0010 #define cfgBIF_CFG_DEV0_EPF0_VF8_0_BASE_ADDR_2 0x0014 #define cfgBIF_CFG_DEV0_EPF0_VF8_0_BASE_ADDR_3 0x0018 #define cfgBIF_CFG_DEV0_EPF0_VF8_0_BASE_ADDR_4 0x001c #define cfgBIF_CFG_DEV0_EPF0_VF8_0_BASE_ADDR_5 0x0020 #define cfgBIF_CFG_DEV0_EPF0_VF8_0_BASE_ADDR_6 0x0024 #define cfgBIF_CFG_DEV0_EPF0_VF8_0_CARDBUS_CIS_PTR 0x0028 #define cfgBIF_CFG_DEV0_EPF0_VF8_0_ADAPTER_ID 0x002c #define cfgBIF_CFG_DEV0_EPF0_VF8_0_ROM_BASE_ADDR 0x0030 #define cfgBIF_CFG_DEV0_EPF0_VF8_0_CAP_PTR 0x0034 #define cfgBIF_CFG_DEV0_EPF0_VF8_0_INTERRUPT_LINE 0x003c #define cfgBIF_CFG_DEV0_EPF0_VF8_0_INTERRUPT_PIN 0x003d #define cfgBIF_CFG_DEV0_EPF0_VF8_0_MIN_GRANT 0x003e #define cfgBIF_CFG_DEV0_EPF0_VF8_0_MAX_LATENCY 0x003f #define cfgBIF_CFG_DEV0_EPF0_VF8_0_PCIE_CAP_LIST 0x0064 #define cfgBIF_CFG_DEV0_EPF0_VF8_0_PCIE_CAP 0x0066 #define cfgBIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CAP 0x0068 #define cfgBIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CNTL 0x006c #define cfgBIF_CFG_DEV0_EPF0_VF8_0_DEVICE_STATUS 0x006e #define cfgBIF_CFG_DEV0_EPF0_VF8_0_LINK_CAP 0x0070 #define cfgBIF_CFG_DEV0_EPF0_VF8_0_LINK_CNTL 0x0074 #define cfgBIF_CFG_DEV0_EPF0_VF8_0_LINK_STATUS 0x0076 #define cfgBIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CAP2 0x0088 #define cfgBIF_CFG_DEV0_EPF0_VF8_0_DEVICE_CNTL2 0x008c #define cfgBIF_CFG_DEV0_EPF0_VF8_0_DEVICE_STATUS2 0x008e #define cfgBIF_CFG_DEV0_EPF0_VF8_0_LINK_CAP2 0x0090 #define cfgBIF_CFG_DEV0_EPF0_VF8_0_LINK_CNTL2 0x0094 #define cfgBIF_CFG_DEV0_EPF0_VF8_0_LINK_STATUS2 0x0096 #define cfgBIF_CFG_DEV0_EPF0_VF8_0_MSI_CAP_LIST 0x00a0 #define cfgBIF_CFG_DEV0_EPF0_VF8_0_MSI_MSG_CNTL 0x00a2 #define cfgBIF_CFG_DEV0_EPF0_VF8_0_MSI_MSG_ADDR_LO 0x00a4 #define cfgBIF_CFG_DEV0_EPF0_VF8_0_MSI_MSG_ADDR_HI 0x00a8 #define cfgBIF_CFG_DEV0_EPF0_VF8_0_MSI_MSG_DATA 0x00a8 #define cfgBIF_CFG_DEV0_EPF0_VF8_0_MSI_MASK 0x00ac #define cfgBIF_CFG_DEV0_EPF0_VF8_0_MSI_MSG_DATA_64 0x00ac #define cfgBIF_CFG_DEV0_EPF0_VF8_0_MSI_MASK_64 0x00b0 #define cfgBIF_CFG_DEV0_EPF0_VF8_0_MSI_PENDING 0x00b0 #define cfgBIF_CFG_DEV0_EPF0_VF8_0_MSI_PENDING_64 0x00b4 #define cfgBIF_CFG_DEV0_EPF0_VF8_0_MSIX_CAP_LIST 0x00c0 #define cfgBIF_CFG_DEV0_EPF0_VF8_0_MSIX_MSG_CNTL 0x00c2 #define cfgBIF_CFG_DEV0_EPF0_VF8_0_MSIX_TABLE 0x00c4 #define cfgBIF_CFG_DEV0_EPF0_VF8_0_MSIX_PBA 0x00c8 #define cfgBIF_CFG_DEV0_EPF0_VF8_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x0100 #define cfgBIF_CFG_DEV0_EPF0_VF8_0_PCIE_VENDOR_SPECIFIC_HDR 0x0104 #define cfgBIF_CFG_DEV0_EPF0_VF8_0_PCIE_VENDOR_SPECIFIC1 0x0108 #define cfgBIF_CFG_DEV0_EPF0_VF8_0_PCIE_VENDOR_SPECIFIC2 0x010c #define cfgBIF_CFG_DEV0_EPF0_VF8_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x0150 #define cfgBIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_STATUS 0x0154 #define cfgBIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_MASK 0x0158 #define cfgBIF_CFG_DEV0_EPF0_VF8_0_PCIE_UNCORR_ERR_SEVERITY 0x015c #define cfgBIF_CFG_DEV0_EPF0_VF8_0_PCIE_CORR_ERR_STATUS 0x0160 #define cfgBIF_CFG_DEV0_EPF0_VF8_0_PCIE_CORR_ERR_MASK 0x0164 #define cfgBIF_CFG_DEV0_EPF0_VF8_0_PCIE_ADV_ERR_CAP_CNTL 0x0168 #define cfgBIF_CFG_DEV0_EPF0_VF8_0_PCIE_HDR_LOG0 0x016c #define cfgBIF_CFG_DEV0_EPF0_VF8_0_PCIE_HDR_LOG1 0x0170 #define cfgBIF_CFG_DEV0_EPF0_VF8_0_PCIE_HDR_LOG2 0x0174 #define cfgBIF_CFG_DEV0_EPF0_VF8_0_PCIE_HDR_LOG3 0x0178 #define cfgBIF_CFG_DEV0_EPF0_VF8_0_PCIE_TLP_PREFIX_LOG0 0x0188 #define cfgBIF_CFG_DEV0_EPF0_VF8_0_PCIE_TLP_PREFIX_LOG1 0x018c #define cfgBIF_CFG_DEV0_EPF0_VF8_0_PCIE_TLP_PREFIX_LOG2 0x0190 #define cfgBIF_CFG_DEV0_EPF0_VF8_0_PCIE_TLP_PREFIX_LOG3 0x0194 #define cfgBIF_CFG_DEV0_EPF0_VF8_0_PCIE_ATS_ENH_CAP_LIST 0x02b0 #define cfgBIF_CFG_DEV0_EPF0_VF8_0_PCIE_ATS_CAP 0x02b4 #define cfgBIF_CFG_DEV0_EPF0_VF8_0_PCIE_ATS_CNTL 0x02b6 #define cfgBIF_CFG_DEV0_EPF0_VF8_0_PCIE_ARI_ENH_CAP_LIST 0x0328 #define cfgBIF_CFG_DEV0_EPF0_VF8_0_PCIE_ARI_CAP 0x032c #define cfgBIF_CFG_DEV0_EPF0_VF8_0_PCIE_ARI_CNTL 0x032e // addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf9_bifcfgdecp // base address: 0x0 #define cfgBIF_CFG_DEV0_EPF0_VF9_0_VENDOR_ID 0x0000 #define cfgBIF_CFG_DEV0_EPF0_VF9_0_DEVICE_ID 0x0002 #define cfgBIF_CFG_DEV0_EPF0_VF9_0_COMMAND 0x0004 #define cfgBIF_CFG_DEV0_EPF0_VF9_0_STATUS 0x0006 #define cfgBIF_CFG_DEV0_EPF0_VF9_0_REVISION_ID 0x0008 #define cfgBIF_CFG_DEV0_EPF0_VF9_0_PROG_INTERFACE 0x0009 #define cfgBIF_CFG_DEV0_EPF0_VF9_0_SUB_CLASS 0x000a #define cfgBIF_CFG_DEV0_EPF0_VF9_0_BASE_CLASS 0x000b #define cfgBIF_CFG_DEV0_EPF0_VF9_0_CACHE_LINE 0x000c #define cfgBIF_CFG_DEV0_EPF0_VF9_0_LATENCY 0x000d #define cfgBIF_CFG_DEV0_EPF0_VF9_0_HEADER 0x000e #define cfgBIF_CFG_DEV0_EPF0_VF9_0_BIST 0x000f #define cfgBIF_CFG_DEV0_EPF0_VF9_0_BASE_ADDR_1 0x0010 #define cfgBIF_CFG_DEV0_EPF0_VF9_0_BASE_ADDR_2 0x0014 #define cfgBIF_CFG_DEV0_EPF0_VF9_0_BASE_ADDR_3 0x0018 #define cfgBIF_CFG_DEV0_EPF0_VF9_0_BASE_ADDR_4 0x001c #define cfgBIF_CFG_DEV0_EPF0_VF9_0_BASE_ADDR_5 0x0020 #define cfgBIF_CFG_DEV0_EPF0_VF9_0_BASE_ADDR_6 0x0024 #define cfgBIF_CFG_DEV0_EPF0_VF9_0_CARDBUS_CIS_PTR 0x0028 #define cfgBIF_CFG_DEV0_EPF0_VF9_0_ADAPTER_ID 0x002c #define cfgBIF_CFG_DEV0_EPF0_VF9_0_ROM_BASE_ADDR 0x0030 #define cfgBIF_CFG_DEV0_EPF0_VF9_0_CAP_PTR 0x0034 #define cfgBIF_CFG_DEV0_EPF0_VF9_0_INTERRUPT_LINE 0x003c #define cfgBIF_CFG_DEV0_EPF0_VF9_0_INTERRUPT_PIN 0x003d #define cfgBIF_CFG_DEV0_EPF0_VF9_0_MIN_GRANT 0x003e #define cfgBIF_CFG_DEV0_EPF0_VF9_0_MAX_LATENCY 0x003f #define cfgBIF_CFG_DEV0_EPF0_VF9_0_PCIE_CAP_LIST 0x0064 #define cfgBIF_CFG_DEV0_EPF0_VF9_0_PCIE_CAP 0x0066 #define cfgBIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CAP 0x0068 #define cfgBIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CNTL 0x006c #define cfgBIF_CFG_DEV0_EPF0_VF9_0_DEVICE_STATUS 0x006e #define cfgBIF_CFG_DEV0_EPF0_VF9_0_LINK_CAP 0x0070 #define cfgBIF_CFG_DEV0_EPF0_VF9_0_LINK_CNTL 0x0074 #define cfgBIF_CFG_DEV0_EPF0_VF9_0_LINK_STATUS 0x0076 #define cfgBIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CAP2 0x0088 #define cfgBIF_CFG_DEV0_EPF0_VF9_0_DEVICE_CNTL2 0x008c #define cfgBIF_CFG_DEV0_EPF0_VF9_0_DEVICE_STATUS2 0x008e #define cfgBIF_CFG_DEV0_EPF0_VF9_0_LINK_CAP2 0x0090 #define cfgBIF_CFG_DEV0_EPF0_VF9_0_LINK_CNTL2 0x0094 #define cfgBIF_CFG_DEV0_EPF0_VF9_0_LINK_STATUS2 0x0096 #define cfgBIF_CFG_DEV0_EPF0_VF9_0_MSI_CAP_LIST 0x00a0 #define cfgBIF_CFG_DEV0_EPF0_VF9_0_MSI_MSG_CNTL 0x00a2 #define cfgBIF_CFG_DEV0_EPF0_VF9_0_MSI_MSG_ADDR_LO 0x00a4 #define cfgBIF_CFG_DEV0_EPF0_VF9_0_MSI_MSG_ADDR_HI 0x00a8 #define cfgBIF_CFG_DEV0_EPF0_VF9_0_MSI_MSG_DATA 0x00a8 #define cfgBIF_CFG_DEV0_EPF0_VF9_0_MSI_MASK 0x00ac #define cfgBIF_CFG_DEV0_EPF0_VF9_0_MSI_MSG_DATA_64 0x00ac #define cfgBIF_CFG_DEV0_EPF0_VF9_0_MSI_MASK_64 0x00b0 #define cfgBIF_CFG_DEV0_EPF0_VF9_0_MSI_PENDING 0x00b0 #define cfgBIF_CFG_DEV0_EPF0_VF9_0_MSI_PENDING_64 0x00b4 #define cfgBIF_CFG_DEV0_EPF0_VF9_0_MSIX_CAP_LIST 0x00c0 #define cfgBIF_CFG_DEV0_EPF0_VF9_0_MSIX_MSG_CNTL 0x00c2 #define cfgBIF_CFG_DEV0_EPF0_VF9_0_MSIX_TABLE 0x00c4 #define cfgBIF_CFG_DEV0_EPF0_VF9_0_MSIX_PBA 0x00c8 #define cfgBIF_CFG_DEV0_EPF0_VF9_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x0100 #define cfgBIF_CFG_DEV0_EPF0_VF9_0_PCIE_VENDOR_SPECIFIC_HDR 0x0104 #define cfgBIF_CFG_DEV0_EPF0_VF9_0_PCIE_VENDOR_SPECIFIC1 0x0108 #define cfgBIF_CFG_DEV0_EPF0_VF9_0_PCIE_VENDOR_SPECIFIC2 0x010c #define cfgBIF_CFG_DEV0_EPF0_VF9_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x0150 #define cfgBIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_STATUS 0x0154 #define cfgBIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_MASK 0x0158 #define cfgBIF_CFG_DEV0_EPF0_VF9_0_PCIE_UNCORR_ERR_SEVERITY 0x015c #define cfgBIF_CFG_DEV0_EPF0_VF9_0_PCIE_CORR_ERR_STATUS 0x0160 #define cfgBIF_CFG_DEV0_EPF0_VF9_0_PCIE_CORR_ERR_MASK 0x0164 #define cfgBIF_CFG_DEV0_EPF0_VF9_0_PCIE_ADV_ERR_CAP_CNTL 0x0168 #define cfgBIF_CFG_DEV0_EPF0_VF9_0_PCIE_HDR_LOG0 0x016c #define cfgBIF_CFG_DEV0_EPF0_VF9_0_PCIE_HDR_LOG1 0x0170 #define cfgBIF_CFG_DEV0_EPF0_VF9_0_PCIE_HDR_LOG2 0x0174 #define cfgBIF_CFG_DEV0_EPF0_VF9_0_PCIE_HDR_LOG3 0x0178 #define cfgBIF_CFG_DEV0_EPF0_VF9_0_PCIE_TLP_PREFIX_LOG0 0x0188 #define cfgBIF_CFG_DEV0_EPF0_VF9_0_PCIE_TLP_PREFIX_LOG1 0x018c #define cfgBIF_CFG_DEV0_EPF0_VF9_0_PCIE_TLP_PREFIX_LOG2 0x0190 #define cfgBIF_CFG_DEV0_EPF0_VF9_0_PCIE_TLP_PREFIX_LOG3 0x0194 #define cfgBIF_CFG_DEV0_EPF0_VF9_0_PCIE_ATS_ENH_CAP_LIST 0x02b0 #define cfgBIF_CFG_DEV0_EPF0_VF9_0_PCIE_ATS_CAP 0x02b4 #define cfgBIF_CFG_DEV0_EPF0_VF9_0_PCIE_ATS_CNTL 0x02b6 #define cfgBIF_CFG_DEV0_EPF0_VF9_0_PCIE_ARI_ENH_CAP_LIST 0x0328 #define cfgBIF_CFG_DEV0_EPF0_VF9_0_PCIE_ARI_CAP 0x032c #define cfgBIF_CFG_DEV0_EPF0_VF9_0_PCIE_ARI_CNTL 0x032e // addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf10_bifcfgdecp // base address: 0x0 #define cfgBIF_CFG_DEV0_EPF0_VF10_0_VENDOR_ID 0x0000 #define cfgBIF_CFG_DEV0_EPF0_VF10_0_DEVICE_ID 0x0002 #define cfgBIF_CFG_DEV0_EPF0_VF10_0_COMMAND 0x0004 #define cfgBIF_CFG_DEV0_EPF0_VF10_0_STATUS 0x0006 #define cfgBIF_CFG_DEV0_EPF0_VF10_0_REVISION_ID 0x0008 #define cfgBIF_CFG_DEV0_EPF0_VF10_0_PROG_INTERFACE 0x0009 #define cfgBIF_CFG_DEV0_EPF0_VF10_0_SUB_CLASS 0x000a #define cfgBIF_CFG_DEV0_EPF0_VF10_0_BASE_CLASS 0x000b #define cfgBIF_CFG_DEV0_EPF0_VF10_0_CACHE_LINE 0x000c #define cfgBIF_CFG_DEV0_EPF0_VF10_0_LATENCY 0x000d #define cfgBIF_CFG_DEV0_EPF0_VF10_0_HEADER 0x000e #define cfgBIF_CFG_DEV0_EPF0_VF10_0_BIST 0x000f #define cfgBIF_CFG_DEV0_EPF0_VF10_0_BASE_ADDR_1 0x0010 #define cfgBIF_CFG_DEV0_EPF0_VF10_0_BASE_ADDR_2 0x0014 #define cfgBIF_CFG_DEV0_EPF0_VF10_0_BASE_ADDR_3 0x0018 #define cfgBIF_CFG_DEV0_EPF0_VF10_0_BASE_ADDR_4 0x001c #define cfgBIF_CFG_DEV0_EPF0_VF10_0_BASE_ADDR_5 0x0020 #define cfgBIF_CFG_DEV0_EPF0_VF10_0_BASE_ADDR_6 0x0024 #define cfgBIF_CFG_DEV0_EPF0_VF10_0_CARDBUS_CIS_PTR 0x0028 #define cfgBIF_CFG_DEV0_EPF0_VF10_0_ADAPTER_ID 0x002c #define cfgBIF_CFG_DEV0_EPF0_VF10_0_ROM_BASE_ADDR 0x0030 #define cfgBIF_CFG_DEV0_EPF0_VF10_0_CAP_PTR 0x0034 #define cfgBIF_CFG_DEV0_EPF0_VF10_0_INTERRUPT_LINE 0x003c #define cfgBIF_CFG_DEV0_EPF0_VF10_0_INTERRUPT_PIN 0x003d #define cfgBIF_CFG_DEV0_EPF0_VF10_0_MIN_GRANT 0x003e #define cfgBIF_CFG_DEV0_EPF0_VF10_0_MAX_LATENCY 0x003f #define cfgBIF_CFG_DEV0_EPF0_VF10_0_PCIE_CAP_LIST 0x0064 #define cfgBIF_CFG_DEV0_EPF0_VF10_0_PCIE_CAP 0x0066 #define cfgBIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CAP 0x0068 #define cfgBIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CNTL 0x006c #define cfgBIF_CFG_DEV0_EPF0_VF10_0_DEVICE_STATUS 0x006e #define cfgBIF_CFG_DEV0_EPF0_VF10_0_LINK_CAP 0x0070 #define cfgBIF_CFG_DEV0_EPF0_VF10_0_LINK_CNTL 0x0074 #define cfgBIF_CFG_DEV0_EPF0_VF10_0_LINK_STATUS 0x0076 #define cfgBIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CAP2 0x0088 #define cfgBIF_CFG_DEV0_EPF0_VF10_0_DEVICE_CNTL2 0x008c #define cfgBIF_CFG_DEV0_EPF0_VF10_0_DEVICE_STATUS2 0x008e #define cfgBIF_CFG_DEV0_EPF0_VF10_0_LINK_CAP2 0x0090 #define cfgBIF_CFG_DEV0_EPF0_VF10_0_LINK_CNTL2 0x0094 #define cfgBIF_CFG_DEV0_EPF0_VF10_0_LINK_STATUS2 0x0096 #define cfgBIF_CFG_DEV0_EPF0_VF10_0_MSI_CAP_LIST 0x00a0 #define cfgBIF_CFG_DEV0_EPF0_VF10_0_MSI_MSG_CNTL 0x00a2 #define cfgBIF_CFG_DEV0_EPF0_VF10_0_MSI_MSG_ADDR_LO 0x00a4 #define cfgBIF_CFG_DEV0_EPF0_VF10_0_MSI_MSG_ADDR_HI 0x00a8 #define cfgBIF_CFG_DEV0_EPF0_VF10_0_MSI_MSG_DATA 0x00a8 #define cfgBIF_CFG_DEV0_EPF0_VF10_0_MSI_MASK 0x00ac #define cfgBIF_CFG_DEV0_EPF0_VF10_0_MSI_MSG_DATA_64 0x00ac #define cfgBIF_CFG_DEV0_EPF0_VF10_0_MSI_MASK_64 0x00b0 #define cfgBIF_CFG_DEV0_EPF0_VF10_0_MSI_PENDING 0x00b0 #define cfgBIF_CFG_DEV0_EPF0_VF10_0_MSI_PENDING_64 0x00b4 #define cfgBIF_CFG_DEV0_EPF0_VF10_0_MSIX_CAP_LIST 0x00c0 #define cfgBIF_CFG_DEV0_EPF0_VF10_0_MSIX_MSG_CNTL 0x00c2 #define cfgBIF_CFG_DEV0_EPF0_VF10_0_MSIX_TABLE 0x00c4 #define cfgBIF_CFG_DEV0_EPF0_VF10_0_MSIX_PBA 0x00c8 #define cfgBIF_CFG_DEV0_EPF0_VF10_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x0100 #define cfgBIF_CFG_DEV0_EPF0_VF10_0_PCIE_VENDOR_SPECIFIC_HDR 0x0104 #define cfgBIF_CFG_DEV0_EPF0_VF10_0_PCIE_VENDOR_SPECIFIC1 0x0108 #define cfgBIF_CFG_DEV0_EPF0_VF10_0_PCIE_VENDOR_SPECIFIC2 0x010c #define cfgBIF_CFG_DEV0_EPF0_VF10_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x0150 #define cfgBIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_STATUS 0x0154 #define cfgBIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_MASK 0x0158 #define cfgBIF_CFG_DEV0_EPF0_VF10_0_PCIE_UNCORR_ERR_SEVERITY 0x015c #define cfgBIF_CFG_DEV0_EPF0_VF10_0_PCIE_CORR_ERR_STATUS 0x0160 #define cfgBIF_CFG_DEV0_EPF0_VF10_0_PCIE_CORR_ERR_MASK 0x0164 #define cfgBIF_CFG_DEV0_EPF0_VF10_0_PCIE_ADV_ERR_CAP_CNTL 0x0168 #define cfgBIF_CFG_DEV0_EPF0_VF10_0_PCIE_HDR_LOG0 0x016c #define cfgBIF_CFG_DEV0_EPF0_VF10_0_PCIE_HDR_LOG1 0x0170 #define cfgBIF_CFG_DEV0_EPF0_VF10_0_PCIE_HDR_LOG2 0x0174 #define cfgBIF_CFG_DEV0_EPF0_VF10_0_PCIE_HDR_LOG3 0x0178 #define cfgBIF_CFG_DEV0_EPF0_VF10_0_PCIE_TLP_PREFIX_LOG0 0x0188 #define cfgBIF_CFG_DEV0_EPF0_VF10_0_PCIE_TLP_PREFIX_LOG1 0x018c #define cfgBIF_CFG_DEV0_EPF0_VF10_0_PCIE_TLP_PREFIX_LOG2 0x0190 #define cfgBIF_CFG_DEV0_EPF0_VF10_0_PCIE_TLP_PREFIX_LOG3 0x0194 #define cfgBIF_CFG_DEV0_EPF0_VF10_0_PCIE_ATS_ENH_CAP_LIST 0x02b0 #define cfgBIF_CFG_DEV0_EPF0_VF10_0_PCIE_ATS_CAP 0x02b4 #define cfgBIF_CFG_DEV0_EPF0_VF10_0_PCIE_ATS_CNTL 0x02b6 #define cfgBIF_CFG_DEV0_EPF0_VF10_0_PCIE_ARI_ENH_CAP_LIST 0x0328 #define cfgBIF_CFG_DEV0_EPF0_VF10_0_PCIE_ARI_CAP 0x032c #define cfgBIF_CFG_DEV0_EPF0_VF10_0_PCIE_ARI_CNTL 0x032e // addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf11_bifcfgdecp // base address: 0x0 #define cfgBIF_CFG_DEV0_EPF0_VF11_0_VENDOR_ID 0x0000 #define cfgBIF_CFG_DEV0_EPF0_VF11_0_DEVICE_ID 0x0002 #define cfgBIF_CFG_DEV0_EPF0_VF11_0_COMMAND 0x0004 #define cfgBIF_CFG_DEV0_EPF0_VF11_0_STATUS 0x0006 #define cfgBIF_CFG_DEV0_EPF0_VF11_0_REVISION_ID 0x0008 #define cfgBIF_CFG_DEV0_EPF0_VF11_0_PROG_INTERFACE 0x0009 #define cfgBIF_CFG_DEV0_EPF0_VF11_0_SUB_CLASS 0x000a #define cfgBIF_CFG_DEV0_EPF0_VF11_0_BASE_CLASS 0x000b #define cfgBIF_CFG_DEV0_EPF0_VF11_0_CACHE_LINE 0x000c #define cfgBIF_CFG_DEV0_EPF0_VF11_0_LATENCY 0x000d #define cfgBIF_CFG_DEV0_EPF0_VF11_0_HEADER 0x000e #define cfgBIF_CFG_DEV0_EPF0_VF11_0_BIST 0x000f #define cfgBIF_CFG_DEV0_EPF0_VF11_0_BASE_ADDR_1 0x0010 #define cfgBIF_CFG_DEV0_EPF0_VF11_0_BASE_ADDR_2 0x0014 #define cfgBIF_CFG_DEV0_EPF0_VF11_0_BASE_ADDR_3 0x0018 #define cfgBIF_CFG_DEV0_EPF0_VF11_0_BASE_ADDR_4 0x001c #define cfgBIF_CFG_DEV0_EPF0_VF11_0_BASE_ADDR_5 0x0020 #define cfgBIF_CFG_DEV0_EPF0_VF11_0_BASE_ADDR_6 0x0024 #define cfgBIF_CFG_DEV0_EPF0_VF11_0_CARDBUS_CIS_PTR 0x0028 #define cfgBIF_CFG_DEV0_EPF0_VF11_0_ADAPTER_ID 0x002c #define cfgBIF_CFG_DEV0_EPF0_VF11_0_ROM_BASE_ADDR 0x0030 #define cfgBIF_CFG_DEV0_EPF0_VF11_0_CAP_PTR 0x0034 #define cfgBIF_CFG_DEV0_EPF0_VF11_0_INTERRUPT_LINE 0x003c #define cfgBIF_CFG_DEV0_EPF0_VF11_0_INTERRUPT_PIN 0x003d #define cfgBIF_CFG_DEV0_EPF0_VF11_0_MIN_GRANT 0x003e #define cfgBIF_CFG_DEV0_EPF0_VF11_0_MAX_LATENCY 0x003f #define cfgBIF_CFG_DEV0_EPF0_VF11_0_PCIE_CAP_LIST 0x0064 #define cfgBIF_CFG_DEV0_EPF0_VF11_0_PCIE_CAP 0x0066 #define cfgBIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CAP 0x0068 #define cfgBIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CNTL 0x006c #define cfgBIF_CFG_DEV0_EPF0_VF11_0_DEVICE_STATUS 0x006e #define cfgBIF_CFG_DEV0_EPF0_VF11_0_LINK_CAP 0x0070 #define cfgBIF_CFG_DEV0_EPF0_VF11_0_LINK_CNTL 0x0074 #define cfgBIF_CFG_DEV0_EPF0_VF11_0_LINK_STATUS 0x0076 #define cfgBIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CAP2 0x0088 #define cfgBIF_CFG_DEV0_EPF0_VF11_0_DEVICE_CNTL2 0x008c #define cfgBIF_CFG_DEV0_EPF0_VF11_0_DEVICE_STATUS2 0x008e #define cfgBIF_CFG_DEV0_EPF0_VF11_0_LINK_CAP2 0x0090 #define cfgBIF_CFG_DEV0_EPF0_VF11_0_LINK_CNTL2 0x0094 #define cfgBIF_CFG_DEV0_EPF0_VF11_0_LINK_STATUS2 0x0096 #define cfgBIF_CFG_DEV0_EPF0_VF11_0_MSI_CAP_LIST 0x00a0 #define cfgBIF_CFG_DEV0_EPF0_VF11_0_MSI_MSG_CNTL 0x00a2 #define cfgBIF_CFG_DEV0_EPF0_VF11_0_MSI_MSG_ADDR_LO 0x00a4 #define cfgBIF_CFG_DEV0_EPF0_VF11_0_MSI_MSG_ADDR_HI 0x00a8 #define cfgBIF_CFG_DEV0_EPF0_VF11_0_MSI_MSG_DATA 0x00a8 #define cfgBIF_CFG_DEV0_EPF0_VF11_0_MSI_MASK 0x00ac #define cfgBIF_CFG_DEV0_EPF0_VF11_0_MSI_MSG_DATA_64 0x00ac #define cfgBIF_CFG_DEV0_EPF0_VF11_0_MSI_MASK_64 0x00b0 #define cfgBIF_CFG_DEV0_EPF0_VF11_0_MSI_PENDING 0x00b0 #define cfgBIF_CFG_DEV0_EPF0_VF11_0_MSI_PENDING_64 0x00b4 #define cfgBIF_CFG_DEV0_EPF0_VF11_0_MSIX_CAP_LIST 0x00c0 #define cfgBIF_CFG_DEV0_EPF0_VF11_0_MSIX_MSG_CNTL 0x00c2 #define cfgBIF_CFG_DEV0_EPF0_VF11_0_MSIX_TABLE 0x00c4 #define cfgBIF_CFG_DEV0_EPF0_VF11_0_MSIX_PBA 0x00c8 #define cfgBIF_CFG_DEV0_EPF0_VF11_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x0100 #define cfgBIF_CFG_DEV0_EPF0_VF11_0_PCIE_VENDOR_SPECIFIC_HDR 0x0104 #define cfgBIF_CFG_DEV0_EPF0_VF11_0_PCIE_VENDOR_SPECIFIC1 0x0108 #define cfgBIF_CFG_DEV0_EPF0_VF11_0_PCIE_VENDOR_SPECIFIC2 0x010c #define cfgBIF_CFG_DEV0_EPF0_VF11_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x0150 #define cfgBIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_STATUS 0x0154 #define cfgBIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_MASK 0x0158 #define cfgBIF_CFG_DEV0_EPF0_VF11_0_PCIE_UNCORR_ERR_SEVERITY 0x015c #define cfgBIF_CFG_DEV0_EPF0_VF11_0_PCIE_CORR_ERR_STATUS 0x0160 #define cfgBIF_CFG_DEV0_EPF0_VF11_0_PCIE_CORR_ERR_MASK 0x0164 #define cfgBIF_CFG_DEV0_EPF0_VF11_0_PCIE_ADV_ERR_CAP_CNTL 0x0168 #define cfgBIF_CFG_DEV0_EPF0_VF11_0_PCIE_HDR_LOG0 0x016c #define cfgBIF_CFG_DEV0_EPF0_VF11_0_PCIE_HDR_LOG1 0x0170 #define cfgBIF_CFG_DEV0_EPF0_VF11_0_PCIE_HDR_LOG2 0x0174 #define cfgBIF_CFG_DEV0_EPF0_VF11_0_PCIE_HDR_LOG3 0x0178 #define cfgBIF_CFG_DEV0_EPF0_VF11_0_PCIE_TLP_PREFIX_LOG0 0x0188 #define cfgBIF_CFG_DEV0_EPF0_VF11_0_PCIE_TLP_PREFIX_LOG1 0x018c #define cfgBIF_CFG_DEV0_EPF0_VF11_0_PCIE_TLP_PREFIX_LOG2 0x0190 #define cfgBIF_CFG_DEV0_EPF0_VF11_0_PCIE_TLP_PREFIX_LOG3 0x0194 #define cfgBIF_CFG_DEV0_EPF0_VF11_0_PCIE_ATS_ENH_CAP_LIST 0x02b0 #define cfgBIF_CFG_DEV0_EPF0_VF11_0_PCIE_ATS_CAP 0x02b4 #define cfgBIF_CFG_DEV0_EPF0_VF11_0_PCIE_ATS_CNTL 0x02b6 #define cfgBIF_CFG_DEV0_EPF0_VF11_0_PCIE_ARI_ENH_CAP_LIST 0x0328 #define cfgBIF_CFG_DEV0_EPF0_VF11_0_PCIE_ARI_CAP 0x032c #define cfgBIF_CFG_DEV0_EPF0_VF11_0_PCIE_ARI_CNTL 0x032e // addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf12_bifcfgdecp // base address: 0x0 #define cfgBIF_CFG_DEV0_EPF0_VF12_0_VENDOR_ID 0x0000 #define cfgBIF_CFG_DEV0_EPF0_VF12_0_DEVICE_ID 0x0002 #define cfgBIF_CFG_DEV0_EPF0_VF12_0_COMMAND 0x0004 #define cfgBIF_CFG_DEV0_EPF0_VF12_0_STATUS 0x0006 #define cfgBIF_CFG_DEV0_EPF0_VF12_0_REVISION_ID 0x0008 #define cfgBIF_CFG_DEV0_EPF0_VF12_0_PROG_INTERFACE 0x0009 #define cfgBIF_CFG_DEV0_EPF0_VF12_0_SUB_CLASS 0x000a #define cfgBIF_CFG_DEV0_EPF0_VF12_0_BASE_CLASS 0x000b #define cfgBIF_CFG_DEV0_EPF0_VF12_0_CACHE_LINE 0x000c #define cfgBIF_CFG_DEV0_EPF0_VF12_0_LATENCY 0x000d #define cfgBIF_CFG_DEV0_EPF0_VF12_0_HEADER 0x000e #define cfgBIF_CFG_DEV0_EPF0_VF12_0_BIST 0x000f #define cfgBIF_CFG_DEV0_EPF0_VF12_0_BASE_ADDR_1 0x0010 #define cfgBIF_CFG_DEV0_EPF0_VF12_0_BASE_ADDR_2 0x0014 #define cfgBIF_CFG_DEV0_EPF0_VF12_0_BASE_ADDR_3 0x0018 #define cfgBIF_CFG_DEV0_EPF0_VF12_0_BASE_ADDR_4 0x001c #define cfgBIF_CFG_DEV0_EPF0_VF12_0_BASE_ADDR_5 0x0020 #define cfgBIF_CFG_DEV0_EPF0_VF12_0_BASE_ADDR_6 0x0024 #define cfgBIF_CFG_DEV0_EPF0_VF12_0_CARDBUS_CIS_PTR 0x0028 #define cfgBIF_CFG_DEV0_EPF0_VF12_0_ADAPTER_ID 0x002c #define cfgBIF_CFG_DEV0_EPF0_VF12_0_ROM_BASE_ADDR 0x0030 #define cfgBIF_CFG_DEV0_EPF0_VF12_0_CAP_PTR 0x0034 #define cfgBIF_CFG_DEV0_EPF0_VF12_0_INTERRUPT_LINE 0x003c #define cfgBIF_CFG_DEV0_EPF0_VF12_0_INTERRUPT_PIN 0x003d #define cfgBIF_CFG_DEV0_EPF0_VF12_0_MIN_GRANT 0x003e #define cfgBIF_CFG_DEV0_EPF0_VF12_0_MAX_LATENCY 0x003f #define cfgBIF_CFG_DEV0_EPF0_VF12_0_PCIE_CAP_LIST 0x0064 #define cfgBIF_CFG_DEV0_EPF0_VF12_0_PCIE_CAP 0x0066 #define cfgBIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CAP 0x0068 #define cfgBIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CNTL 0x006c #define cfgBIF_CFG_DEV0_EPF0_VF12_0_DEVICE_STATUS 0x006e #define cfgBIF_CFG_DEV0_EPF0_VF12_0_LINK_CAP 0x0070 #define cfgBIF_CFG_DEV0_EPF0_VF12_0_LINK_CNTL 0x0074 #define cfgBIF_CFG_DEV0_EPF0_VF12_0_LINK_STATUS 0x0076 #define cfgBIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CAP2 0x0088 #define cfgBIF_CFG_DEV0_EPF0_VF12_0_DEVICE_CNTL2 0x008c #define cfgBIF_CFG_DEV0_EPF0_VF12_0_DEVICE_STATUS2 0x008e #define cfgBIF_CFG_DEV0_EPF0_VF12_0_LINK_CAP2 0x0090 #define cfgBIF_CFG_DEV0_EPF0_VF12_0_LINK_CNTL2 0x0094 #define cfgBIF_CFG_DEV0_EPF0_VF12_0_LINK_STATUS2 0x0096 #define cfgBIF_CFG_DEV0_EPF0_VF12_0_MSI_CAP_LIST 0x00a0 #define cfgBIF_CFG_DEV0_EPF0_VF12_0_MSI_MSG_CNTL 0x00a2 #define cfgBIF_CFG_DEV0_EPF0_VF12_0_MSI_MSG_ADDR_LO 0x00a4 #define cfgBIF_CFG_DEV0_EPF0_VF12_0_MSI_MSG_ADDR_HI 0x00a8 #define cfgBIF_CFG_DEV0_EPF0_VF12_0_MSI_MSG_DATA 0x00a8 #define cfgBIF_CFG_DEV0_EPF0_VF12_0_MSI_MASK 0x00ac #define cfgBIF_CFG_DEV0_EPF0_VF12_0_MSI_MSG_DATA_64 0x00ac #define cfgBIF_CFG_DEV0_EPF0_VF12_0_MSI_MASK_64 0x00b0 #define cfgBIF_CFG_DEV0_EPF0_VF12_0_MSI_PENDING 0x00b0 #define cfgBIF_CFG_DEV0_EPF0_VF12_0_MSI_PENDING_64 0x00b4 #define cfgBIF_CFG_DEV0_EPF0_VF12_0_MSIX_CAP_LIST 0x00c0 #define cfgBIF_CFG_DEV0_EPF0_VF12_0_MSIX_MSG_CNTL 0x00c2 #define cfgBIF_CFG_DEV0_EPF0_VF12_0_MSIX_TABLE 0x00c4 #define cfgBIF_CFG_DEV0_EPF0_VF12_0_MSIX_PBA 0x00c8 #define cfgBIF_CFG_DEV0_EPF0_VF12_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x0100 #define cfgBIF_CFG_DEV0_EPF0_VF12_0_PCIE_VENDOR_SPECIFIC_HDR 0x0104 #define cfgBIF_CFG_DEV0_EPF0_VF12_0_PCIE_VENDOR_SPECIFIC1 0x0108 #define cfgBIF_CFG_DEV0_EPF0_VF12_0_PCIE_VENDOR_SPECIFIC2 0x010c #define cfgBIF_CFG_DEV0_EPF0_VF12_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x0150 #define cfgBIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_STATUS 0x0154 #define cfgBIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_MASK 0x0158 #define cfgBIF_CFG_DEV0_EPF0_VF12_0_PCIE_UNCORR_ERR_SEVERITY 0x015c #define cfgBIF_CFG_DEV0_EPF0_VF12_0_PCIE_CORR_ERR_STATUS 0x0160 #define cfgBIF_CFG_DEV0_EPF0_VF12_0_PCIE_CORR_ERR_MASK 0x0164 #define cfgBIF_CFG_DEV0_EPF0_VF12_0_PCIE_ADV_ERR_CAP_CNTL 0x0168 #define cfgBIF_CFG_DEV0_EPF0_VF12_0_PCIE_HDR_LOG0 0x016c #define cfgBIF_CFG_DEV0_EPF0_VF12_0_PCIE_HDR_LOG1 0x0170 #define cfgBIF_CFG_DEV0_EPF0_VF12_0_PCIE_HDR_LOG2 0x0174 #define cfgBIF_CFG_DEV0_EPF0_VF12_0_PCIE_HDR_LOG3 0x0178 #define cfgBIF_CFG_DEV0_EPF0_VF12_0_PCIE_TLP_PREFIX_LOG0 0x0188 #define cfgBIF_CFG_DEV0_EPF0_VF12_0_PCIE_TLP_PREFIX_LOG1 0x018c #define cfgBIF_CFG_DEV0_EPF0_VF12_0_PCIE_TLP_PREFIX_LOG2 0x0190 #define cfgBIF_CFG_DEV0_EPF0_VF12_0_PCIE_TLP_PREFIX_LOG3 0x0194 #define cfgBIF_CFG_DEV0_EPF0_VF12_0_PCIE_ATS_ENH_CAP_LIST 0x02b0 #define cfgBIF_CFG_DEV0_EPF0_VF12_0_PCIE_ATS_CAP 0x02b4 #define cfgBIF_CFG_DEV0_EPF0_VF12_0_PCIE_ATS_CNTL 0x02b6 #define cfgBIF_CFG_DEV0_EPF0_VF12_0_PCIE_ARI_ENH_CAP_LIST 0x0328 #define cfgBIF_CFG_DEV0_EPF0_VF12_0_PCIE_ARI_CAP 0x032c #define cfgBIF_CFG_DEV0_EPF0_VF12_0_PCIE_ARI_CNTL 0x032e // addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf13_bifcfgdecp // base address: 0x0 #define cfgBIF_CFG_DEV0_EPF0_VF13_0_VENDOR_ID 0x0000 #define cfgBIF_CFG_DEV0_EPF0_VF13_0_DEVICE_ID 0x0002 #define cfgBIF_CFG_DEV0_EPF0_VF13_0_COMMAND 0x0004 #define cfgBIF_CFG_DEV0_EPF0_VF13_0_STATUS 0x0006 #define cfgBIF_CFG_DEV0_EPF0_VF13_0_REVISION_ID 0x0008 #define cfgBIF_CFG_DEV0_EPF0_VF13_0_PROG_INTERFACE 0x0009 #define cfgBIF_CFG_DEV0_EPF0_VF13_0_SUB_CLASS 0x000a #define cfgBIF_CFG_DEV0_EPF0_VF13_0_BASE_CLASS 0x000b #define cfgBIF_CFG_DEV0_EPF0_VF13_0_CACHE_LINE 0x000c #define cfgBIF_CFG_DEV0_EPF0_VF13_0_LATENCY 0x000d #define cfgBIF_CFG_DEV0_EPF0_VF13_0_HEADER 0x000e #define cfgBIF_CFG_DEV0_EPF0_VF13_0_BIST 0x000f #define cfgBIF_CFG_DEV0_EPF0_VF13_0_BASE_ADDR_1 0x0010 #define cfgBIF_CFG_DEV0_EPF0_VF13_0_BASE_ADDR_2 0x0014 #define cfgBIF_CFG_DEV0_EPF0_VF13_0_BASE_ADDR_3 0x0018 #define cfgBIF_CFG_DEV0_EPF0_VF13_0_BASE_ADDR_4 0x001c #define cfgBIF_CFG_DEV0_EPF0_VF13_0_BASE_ADDR_5 0x0020 #define cfgBIF_CFG_DEV0_EPF0_VF13_0_BASE_ADDR_6 0x0024 #define cfgBIF_CFG_DEV0_EPF0_VF13_0_CARDBUS_CIS_PTR 0x0028 #define cfgBIF_CFG_DEV0_EPF0_VF13_0_ADAPTER_ID 0x002c #define cfgBIF_CFG_DEV0_EPF0_VF13_0_ROM_BASE_ADDR 0x0030 #define cfgBIF_CFG_DEV0_EPF0_VF13_0_CAP_PTR 0x0034 #define cfgBIF_CFG_DEV0_EPF0_VF13_0_INTERRUPT_LINE 0x003c #define cfgBIF_CFG_DEV0_EPF0_VF13_0_INTERRUPT_PIN 0x003d #define cfgBIF_CFG_DEV0_EPF0_VF13_0_MIN_GRANT 0x003e #define cfgBIF_CFG_DEV0_EPF0_VF13_0_MAX_LATENCY 0x003f #define cfgBIF_CFG_DEV0_EPF0_VF13_0_PCIE_CAP_LIST 0x0064 #define cfgBIF_CFG_DEV0_EPF0_VF13_0_PCIE_CAP 0x0066 #define cfgBIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CAP 0x0068 #define cfgBIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CNTL 0x006c #define cfgBIF_CFG_DEV0_EPF0_VF13_0_DEVICE_STATUS 0x006e #define cfgBIF_CFG_DEV0_EPF0_VF13_0_LINK_CAP 0x0070 #define cfgBIF_CFG_DEV0_EPF0_VF13_0_LINK_CNTL 0x0074 #define cfgBIF_CFG_DEV0_EPF0_VF13_0_LINK_STATUS 0x0076 #define cfgBIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CAP2 0x0088 #define cfgBIF_CFG_DEV0_EPF0_VF13_0_DEVICE_CNTL2 0x008c #define cfgBIF_CFG_DEV0_EPF0_VF13_0_DEVICE_STATUS2 0x008e #define cfgBIF_CFG_DEV0_EPF0_VF13_0_LINK_CAP2 0x0090 #define cfgBIF_CFG_DEV0_EPF0_VF13_0_LINK_CNTL2 0x0094 #define cfgBIF_CFG_DEV0_EPF0_VF13_0_LINK_STATUS2 0x0096 #define cfgBIF_CFG_DEV0_EPF0_VF13_0_MSI_CAP_LIST 0x00a0 #define cfgBIF_CFG_DEV0_EPF0_VF13_0_MSI_MSG_CNTL 0x00a2 #define cfgBIF_CFG_DEV0_EPF0_VF13_0_MSI_MSG_ADDR_LO 0x00a4 #define cfgBIF_CFG_DEV0_EPF0_VF13_0_MSI_MSG_ADDR_HI 0x00a8 #define cfgBIF_CFG_DEV0_EPF0_VF13_0_MSI_MSG_DATA 0x00a8 #define cfgBIF_CFG_DEV0_EPF0_VF13_0_MSI_MASK 0x00ac #define cfgBIF_CFG_DEV0_EPF0_VF13_0_MSI_MSG_DATA_64 0x00ac #define cfgBIF_CFG_DEV0_EPF0_VF13_0_MSI_MASK_64 0x00b0 #define cfgBIF_CFG_DEV0_EPF0_VF13_0_MSI_PENDING 0x00b0 #define cfgBIF_CFG_DEV0_EPF0_VF13_0_MSI_PENDING_64 0x00b4 #define cfgBIF_CFG_DEV0_EPF0_VF13_0_MSIX_CAP_LIST 0x00c0 #define cfgBIF_CFG_DEV0_EPF0_VF13_0_MSIX_MSG_CNTL 0x00c2 #define cfgBIF_CFG_DEV0_EPF0_VF13_0_MSIX_TABLE 0x00c4 #define cfgBIF_CFG_DEV0_EPF0_VF13_0_MSIX_PBA 0x00c8 #define cfgBIF_CFG_DEV0_EPF0_VF13_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x0100 #define cfgBIF_CFG_DEV0_EPF0_VF13_0_PCIE_VENDOR_SPECIFIC_HDR 0x0104 #define cfgBIF_CFG_DEV0_EPF0_VF13_0_PCIE_VENDOR_SPECIFIC1 0x0108 #define cfgBIF_CFG_DEV0_EPF0_VF13_0_PCIE_VENDOR_SPECIFIC2 0x010c #define cfgBIF_CFG_DEV0_EPF0_VF13_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x0150 #define cfgBIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_STATUS 0x0154 #define cfgBIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_MASK 0x0158 #define cfgBIF_CFG_DEV0_EPF0_VF13_0_PCIE_UNCORR_ERR_SEVERITY 0x015c #define cfgBIF_CFG_DEV0_EPF0_VF13_0_PCIE_CORR_ERR_STATUS 0x0160 #define cfgBIF_CFG_DEV0_EPF0_VF13_0_PCIE_CORR_ERR_MASK 0x0164 #define cfgBIF_CFG_DEV0_EPF0_VF13_0_PCIE_ADV_ERR_CAP_CNTL 0x0168 #define cfgBIF_CFG_DEV0_EPF0_VF13_0_PCIE_HDR_LOG0 0x016c #define cfgBIF_CFG_DEV0_EPF0_VF13_0_PCIE_HDR_LOG1 0x0170 #define cfgBIF_CFG_DEV0_EPF0_VF13_0_PCIE_HDR_LOG2 0x0174 #define cfgBIF_CFG_DEV0_EPF0_VF13_0_PCIE_HDR_LOG3 0x0178 #define cfgBIF_CFG_DEV0_EPF0_VF13_0_PCIE_TLP_PREFIX_LOG0 0x0188 #define cfgBIF_CFG_DEV0_EPF0_VF13_0_PCIE_TLP_PREFIX_LOG1 0x018c #define cfgBIF_CFG_DEV0_EPF0_VF13_0_PCIE_TLP_PREFIX_LOG2 0x0190 #define cfgBIF_CFG_DEV0_EPF0_VF13_0_PCIE_TLP_PREFIX_LOG3 0x0194 #define cfgBIF_CFG_DEV0_EPF0_VF13_0_PCIE_ATS_ENH_CAP_LIST 0x02b0 #define cfgBIF_CFG_DEV0_EPF0_VF13_0_PCIE_ATS_CAP 0x02b4 #define cfgBIF_CFG_DEV0_EPF0_VF13_0_PCIE_ATS_CNTL 0x02b6 #define cfgBIF_CFG_DEV0_EPF0_VF13_0_PCIE_ARI_ENH_CAP_LIST 0x0328 #define cfgBIF_CFG_DEV0_EPF0_VF13_0_PCIE_ARI_CAP 0x032c #define cfgBIF_CFG_DEV0_EPF0_VF13_0_PCIE_ARI_CNTL 0x032e // addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf14_bifcfgdecp // base address: 0x0 #define cfgBIF_CFG_DEV0_EPF0_VF14_0_VENDOR_ID 0x0000 #define cfgBIF_CFG_DEV0_EPF0_VF14_0_DEVICE_ID 0x0002 #define cfgBIF_CFG_DEV0_EPF0_VF14_0_COMMAND 0x0004 #define cfgBIF_CFG_DEV0_EPF0_VF14_0_STATUS 0x0006 #define cfgBIF_CFG_DEV0_EPF0_VF14_0_REVISION_ID 0x0008 #define cfgBIF_CFG_DEV0_EPF0_VF14_0_PROG_INTERFACE 0x0009 #define cfgBIF_CFG_DEV0_EPF0_VF14_0_SUB_CLASS 0x000a #define cfgBIF_CFG_DEV0_EPF0_VF14_0_BASE_CLASS 0x000b #define cfgBIF_CFG_DEV0_EPF0_VF14_0_CACHE_LINE 0x000c #define cfgBIF_CFG_DEV0_EPF0_VF14_0_LATENCY 0x000d #define cfgBIF_CFG_DEV0_EPF0_VF14_0_HEADER 0x000e #define cfgBIF_CFG_DEV0_EPF0_VF14_0_BIST 0x000f #define cfgBIF_CFG_DEV0_EPF0_VF14_0_BASE_ADDR_1 0x0010 #define cfgBIF_CFG_DEV0_EPF0_VF14_0_BASE_ADDR_2 0x0014 #define cfgBIF_CFG_DEV0_EPF0_VF14_0_BASE_ADDR_3 0x0018 #define cfgBIF_CFG_DEV0_EPF0_VF14_0_BASE_ADDR_4 0x001c #define cfgBIF_CFG_DEV0_EPF0_VF14_0_BASE_ADDR_5 0x0020 #define cfgBIF_CFG_DEV0_EPF0_VF14_0_BASE_ADDR_6 0x0024 #define cfgBIF_CFG_DEV0_EPF0_VF14_0_CARDBUS_CIS_PTR 0x0028 #define cfgBIF_CFG_DEV0_EPF0_VF14_0_ADAPTER_ID 0x002c #define cfgBIF_CFG_DEV0_EPF0_VF14_0_ROM_BASE_ADDR 0x0030 #define cfgBIF_CFG_DEV0_EPF0_VF14_0_CAP_PTR 0x0034 #define cfgBIF_CFG_DEV0_EPF0_VF14_0_INTERRUPT_LINE 0x003c #define cfgBIF_CFG_DEV0_EPF0_VF14_0_INTERRUPT_PIN 0x003d #define cfgBIF_CFG_DEV0_EPF0_VF14_0_MIN_GRANT 0x003e #define cfgBIF_CFG_DEV0_EPF0_VF14_0_MAX_LATENCY 0x003f #define cfgBIF_CFG_DEV0_EPF0_VF14_0_PCIE_CAP_LIST 0x0064 #define cfgBIF_CFG_DEV0_EPF0_VF14_0_PCIE_CAP 0x0066 #define cfgBIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CAP 0x0068 #define cfgBIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CNTL 0x006c #define cfgBIF_CFG_DEV0_EPF0_VF14_0_DEVICE_STATUS 0x006e #define cfgBIF_CFG_DEV0_EPF0_VF14_0_LINK_CAP 0x0070 #define cfgBIF_CFG_DEV0_EPF0_VF14_0_LINK_CNTL 0x0074 #define cfgBIF_CFG_DEV0_EPF0_VF14_0_LINK_STATUS 0x0076 #define cfgBIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CAP2 0x0088 #define cfgBIF_CFG_DEV0_EPF0_VF14_0_DEVICE_CNTL2 0x008c #define cfgBIF_CFG_DEV0_EPF0_VF14_0_DEVICE_STATUS2 0x008e #define cfgBIF_CFG_DEV0_EPF0_VF14_0_LINK_CAP2 0x0090 #define cfgBIF_CFG_DEV0_EPF0_VF14_0_LINK_CNTL2 0x0094 #define cfgBIF_CFG_DEV0_EPF0_VF14_0_LINK_STATUS2 0x0096 #define cfgBIF_CFG_DEV0_EPF0_VF14_0_MSI_CAP_LIST 0x00a0 #define cfgBIF_CFG_DEV0_EPF0_VF14_0_MSI_MSG_CNTL 0x00a2 #define cfgBIF_CFG_DEV0_EPF0_VF14_0_MSI_MSG_ADDR_LO 0x00a4 #define cfgBIF_CFG_DEV0_EPF0_VF14_0_MSI_MSG_ADDR_HI 0x00a8 #define cfgBIF_CFG_DEV0_EPF0_VF14_0_MSI_MSG_DATA 0x00a8 #define cfgBIF_CFG_DEV0_EPF0_VF14_0_MSI_MASK 0x00ac #define cfgBIF_CFG_DEV0_EPF0_VF14_0_MSI_MSG_DATA_64 0x00ac #define cfgBIF_CFG_DEV0_EPF0_VF14_0_MSI_MASK_64 0x00b0 #define cfgBIF_CFG_DEV0_EPF0_VF14_0_MSI_PENDING 0x00b0 #define cfgBIF_CFG_DEV0_EPF0_VF14_0_MSI_PENDING_64 0x00b4 #define cfgBIF_CFG_DEV0_EPF0_VF14_0_MSIX_CAP_LIST 0x00c0 #define cfgBIF_CFG_DEV0_EPF0_VF14_0_MSIX_MSG_CNTL 0x00c2 #define cfgBIF_CFG_DEV0_EPF0_VF14_0_MSIX_TABLE 0x00c4 #define cfgBIF_CFG_DEV0_EPF0_VF14_0_MSIX_PBA 0x00c8 #define cfgBIF_CFG_DEV0_EPF0_VF14_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x0100 #define cfgBIF_CFG_DEV0_EPF0_VF14_0_PCIE_VENDOR_SPECIFIC_HDR 0x0104 #define cfgBIF_CFG_DEV0_EPF0_VF14_0_PCIE_VENDOR_SPECIFIC1 0x0108 #define cfgBIF_CFG_DEV0_EPF0_VF14_0_PCIE_VENDOR_SPECIFIC2 0x010c #define cfgBIF_CFG_DEV0_EPF0_VF14_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x0150 #define cfgBIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_STATUS 0x0154 #define cfgBIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_MASK 0x0158 #define cfgBIF_CFG_DEV0_EPF0_VF14_0_PCIE_UNCORR_ERR_SEVERITY 0x015c #define cfgBIF_CFG_DEV0_EPF0_VF14_0_PCIE_CORR_ERR_STATUS 0x0160 #define cfgBIF_CFG_DEV0_EPF0_VF14_0_PCIE_CORR_ERR_MASK 0x0164 #define cfgBIF_CFG_DEV0_EPF0_VF14_0_PCIE_ADV_ERR_CAP_CNTL 0x0168 #define cfgBIF_CFG_DEV0_EPF0_VF14_0_PCIE_HDR_LOG0 0x016c #define cfgBIF_CFG_DEV0_EPF0_VF14_0_PCIE_HDR_LOG1 0x0170 #define cfgBIF_CFG_DEV0_EPF0_VF14_0_PCIE_HDR_LOG2 0x0174 #define cfgBIF_CFG_DEV0_EPF0_VF14_0_PCIE_HDR_LOG3 0x0178 #define cfgBIF_CFG_DEV0_EPF0_VF14_0_PCIE_TLP_PREFIX_LOG0 0x0188 #define cfgBIF_CFG_DEV0_EPF0_VF14_0_PCIE_TLP_PREFIX_LOG1 0x018c #define cfgBIF_CFG_DEV0_EPF0_VF14_0_PCIE_TLP_PREFIX_LOG2 0x0190 #define cfgBIF_CFG_DEV0_EPF0_VF14_0_PCIE_TLP_PREFIX_LOG3 0x0194 #define cfgBIF_CFG_DEV0_EPF0_VF14_0_PCIE_ATS_ENH_CAP_LIST 0x02b0 #define cfgBIF_CFG_DEV0_EPF0_VF14_0_PCIE_ATS_CAP 0x02b4 #define cfgBIF_CFG_DEV0_EPF0_VF14_0_PCIE_ATS_CNTL 0x02b6 #define cfgBIF_CFG_DEV0_EPF0_VF14_0_PCIE_ARI_ENH_CAP_LIST 0x0328 #define cfgBIF_CFG_DEV0_EPF0_VF14_0_PCIE_ARI_CAP 0x032c #define cfgBIF_CFG_DEV0_EPF0_VF14_0_PCIE_ARI_CNTL 0x032e // addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf15_bifcfgdecp // base address: 0x0 #define cfgBIF_CFG_DEV0_EPF0_VF15_0_VENDOR_ID 0x0000 #define cfgBIF_CFG_DEV0_EPF0_VF15_0_DEVICE_ID 0x0002 #define cfgBIF_CFG_DEV0_EPF0_VF15_0_COMMAND 0x0004 #define cfgBIF_CFG_DEV0_EPF0_VF15_0_STATUS 0x0006 #define cfgBIF_CFG_DEV0_EPF0_VF15_0_REVISION_ID 0x0008 #define cfgBIF_CFG_DEV0_EPF0_VF15_0_PROG_INTERFACE 0x0009 #define cfgBIF_CFG_DEV0_EPF0_VF15_0_SUB_CLASS 0x000a #define cfgBIF_CFG_DEV0_EPF0_VF15_0_BASE_CLASS 0x000b #define cfgBIF_CFG_DEV0_EPF0_VF15_0_CACHE_LINE 0x000c #define cfgBIF_CFG_DEV0_EPF0_VF15_0_LATENCY 0x000d #define cfgBIF_CFG_DEV0_EPF0_VF15_0_HEADER 0x000e #define cfgBIF_CFG_DEV0_EPF0_VF15_0_BIST 0x000f #define cfgBIF_CFG_DEV0_EPF0_VF15_0_BASE_ADDR_1 0x0010 #define cfgBIF_CFG_DEV0_EPF0_VF15_0_BASE_ADDR_2 0x0014 #define cfgBIF_CFG_DEV0_EPF0_VF15_0_BASE_ADDR_3 0x0018 #define cfgBIF_CFG_DEV0_EPF0_VF15_0_BASE_ADDR_4 0x001c #define cfgBIF_CFG_DEV0_EPF0_VF15_0_BASE_ADDR_5 0x0020 #define cfgBIF_CFG_DEV0_EPF0_VF15_0_BASE_ADDR_6 0x0024 #define cfgBIF_CFG_DEV0_EPF0_VF15_0_CARDBUS_CIS_PTR 0x0028 #define cfgBIF_CFG_DEV0_EPF0_VF15_0_ADAPTER_ID 0x002c #define cfgBIF_CFG_DEV0_EPF0_VF15_0_ROM_BASE_ADDR 0x0030 #define cfgBIF_CFG_DEV0_EPF0_VF15_0_CAP_PTR 0x0034 #define cfgBIF_CFG_DEV0_EPF0_VF15_0_INTERRUPT_LINE 0x003c #define cfgBIF_CFG_DEV0_EPF0_VF15_0_INTERRUPT_PIN 0x003d #define cfgBIF_CFG_DEV0_EPF0_VF15_0_MIN_GRANT 0x003e #define cfgBIF_CFG_DEV0_EPF0_VF15_0_MAX_LATENCY 0x003f #define cfgBIF_CFG_DEV0_EPF0_VF15_0_PCIE_CAP_LIST 0x0064 #define cfgBIF_CFG_DEV0_EPF0_VF15_0_PCIE_CAP 0x0066 #define cfgBIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CAP 0x0068 #define cfgBIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CNTL 0x006c #define cfgBIF_CFG_DEV0_EPF0_VF15_0_DEVICE_STATUS 0x006e #define cfgBIF_CFG_DEV0_EPF0_VF15_0_LINK_CAP 0x0070 #define cfgBIF_CFG_DEV0_EPF0_VF15_0_LINK_CNTL 0x0074 #define cfgBIF_CFG_DEV0_EPF0_VF15_0_LINK_STATUS 0x0076 #define cfgBIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CAP2 0x0088 #define cfgBIF_CFG_DEV0_EPF0_VF15_0_DEVICE_CNTL2 0x008c #define cfgBIF_CFG_DEV0_EPF0_VF15_0_DEVICE_STATUS2 0x008e #define cfgBIF_CFG_DEV0_EPF0_VF15_0_LINK_CAP2 0x0090 #define cfgBIF_CFG_DEV0_EPF0_VF15_0_LINK_CNTL2 0x0094 #define cfgBIF_CFG_DEV0_EPF0_VF15_0_LINK_STATUS2 0x0096 #define cfgBIF_CFG_DEV0_EPF0_VF15_0_MSI_CAP_LIST 0x00a0 #define cfgBIF_CFG_DEV0_EPF0_VF15_0_MSI_MSG_CNTL 0x00a2 #define cfgBIF_CFG_DEV0_EPF0_VF15_0_MSI_MSG_ADDR_LO 0x00a4 #define cfgBIF_CFG_DEV0_EPF0_VF15_0_MSI_MSG_ADDR_HI 0x00a8 #define cfgBIF_CFG_DEV0_EPF0_VF15_0_MSI_MSG_DATA 0x00a8 #define cfgBIF_CFG_DEV0_EPF0_VF15_0_MSI_MASK 0x00ac #define cfgBIF_CFG_DEV0_EPF0_VF15_0_MSI_MSG_DATA_64 0x00ac #define cfgBIF_CFG_DEV0_EPF0_VF15_0_MSI_MASK_64 0x00b0 #define cfgBIF_CFG_DEV0_EPF0_VF15_0_MSI_PENDING 0x00b0 #define cfgBIF_CFG_DEV0_EPF0_VF15_0_MSI_PENDING_64 0x00b4 #define cfgBIF_CFG_DEV0_EPF0_VF15_0_MSIX_CAP_LIST 0x00c0 #define cfgBIF_CFG_DEV0_EPF0_VF15_0_MSIX_MSG_CNTL 0x00c2 #define cfgBIF_CFG_DEV0_EPF0_VF15_0_MSIX_TABLE 0x00c4 #define cfgBIF_CFG_DEV0_EPF0_VF15_0_MSIX_PBA 0x00c8 #define cfgBIF_CFG_DEV0_EPF0_VF15_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x0100 #define cfgBIF_CFG_DEV0_EPF0_VF15_0_PCIE_VENDOR_SPECIFIC_HDR 0x0104 #define cfgBIF_CFG_DEV0_EPF0_VF15_0_PCIE_VENDOR_SPECIFIC1 0x0108 #define cfgBIF_CFG_DEV0_EPF0_VF15_0_PCIE_VENDOR_SPECIFIC2 0x010c #define cfgBIF_CFG_DEV0_EPF0_VF15_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x0150 #define cfgBIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_STATUS 0x0154 #define cfgBIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_MASK 0x0158 #define cfgBIF_CFG_DEV0_EPF0_VF15_0_PCIE_UNCORR_ERR_SEVERITY 0x015c #define cfgBIF_CFG_DEV0_EPF0_VF15_0_PCIE_CORR_ERR_STATUS 0x0160 #define cfgBIF_CFG_DEV0_EPF0_VF15_0_PCIE_CORR_ERR_MASK 0x0164 #define cfgBIF_CFG_DEV0_EPF0_VF15_0_PCIE_ADV_ERR_CAP_CNTL 0x0168 #define cfgBIF_CFG_DEV0_EPF0_VF15_0_PCIE_HDR_LOG0 0x016c #define cfgBIF_CFG_DEV0_EPF0_VF15_0_PCIE_HDR_LOG1 0x0170 #define cfgBIF_CFG_DEV0_EPF0_VF15_0_PCIE_HDR_LOG2 0x0174 #define cfgBIF_CFG_DEV0_EPF0_VF15_0_PCIE_HDR_LOG3 0x0178 #define cfgBIF_CFG_DEV0_EPF0_VF15_0_PCIE_TLP_PREFIX_LOG0 0x0188 #define cfgBIF_CFG_DEV0_EPF0_VF15_0_PCIE_TLP_PREFIX_LOG1 0x018c #define cfgBIF_CFG_DEV0_EPF0_VF15_0_PCIE_TLP_PREFIX_LOG2 0x0190 #define cfgBIF_CFG_DEV0_EPF0_VF15_0_PCIE_TLP_PREFIX_LOG3 0x0194 #define cfgBIF_CFG_DEV0_EPF0_VF15_0_PCIE_ATS_ENH_CAP_LIST 0x02b0 #define cfgBIF_CFG_DEV0_EPF0_VF15_0_PCIE_ATS_CAP 0x02b4 #define cfgBIF_CFG_DEV0_EPF0_VF15_0_PCIE_ATS_CNTL 0x02b6 #define cfgBIF_CFG_DEV0_EPF0_VF15_0_PCIE_ARI_ENH_CAP_LIST 0x0328 #define cfgBIF_CFG_DEV0_EPF0_VF15_0_PCIE_ARI_CAP 0x032c #define cfgBIF_CFG_DEV0_EPF0_VF15_0_PCIE_ARI_CNTL 0x032e // addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf16_bifcfgdecp // base address: 0x0 #define cfgBIF_CFG_DEV0_EPF0_VF16_0_VENDOR_ID 0x0000 #define cfgBIF_CFG_DEV0_EPF0_VF16_0_DEVICE_ID 0x0002 #define cfgBIF_CFG_DEV0_EPF0_VF16_0_COMMAND 0x0004 #define cfgBIF_CFG_DEV0_EPF0_VF16_0_STATUS 0x0006 #define cfgBIF_CFG_DEV0_EPF0_VF16_0_REVISION_ID 0x0008 #define cfgBIF_CFG_DEV0_EPF0_VF16_0_PROG_INTERFACE 0x0009 #define cfgBIF_CFG_DEV0_EPF0_VF16_0_SUB_CLASS 0x000a #define cfgBIF_CFG_DEV0_EPF0_VF16_0_BASE_CLASS 0x000b #define cfgBIF_CFG_DEV0_EPF0_VF16_0_CACHE_LINE 0x000c #define cfgBIF_CFG_DEV0_EPF0_VF16_0_LATENCY 0x000d #define cfgBIF_CFG_DEV0_EPF0_VF16_0_HEADER 0x000e #define cfgBIF_CFG_DEV0_EPF0_VF16_0_BIST 0x000f #define cfgBIF_CFG_DEV0_EPF0_VF16_0_BASE_ADDR_1 0x0010 #define cfgBIF_CFG_DEV0_EPF0_VF16_0_BASE_ADDR_2 0x0014 #define cfgBIF_CFG_DEV0_EPF0_VF16_0_BASE_ADDR_3 0x0018 #define cfgBIF_CFG_DEV0_EPF0_VF16_0_BASE_ADDR_4 0x001c #define cfgBIF_CFG_DEV0_EPF0_VF16_0_BASE_ADDR_5 0x0020 #define cfgBIF_CFG_DEV0_EPF0_VF16_0_BASE_ADDR_6 0x0024 #define cfgBIF_CFG_DEV0_EPF0_VF16_0_CARDBUS_CIS_PTR 0x0028 #define cfgBIF_CFG_DEV0_EPF0_VF16_0_ADAPTER_ID 0x002c #define cfgBIF_CFG_DEV0_EPF0_VF16_0_ROM_BASE_ADDR 0x0030 #define cfgBIF_CFG_DEV0_EPF0_VF16_0_CAP_PTR 0x0034 #define cfgBIF_CFG_DEV0_EPF0_VF16_0_INTERRUPT_LINE 0x003c #define cfgBIF_CFG_DEV0_EPF0_VF16_0_INTERRUPT_PIN 0x003d #define cfgBIF_CFG_DEV0_EPF0_VF16_0_MIN_GRANT 0x003e #define cfgBIF_CFG_DEV0_EPF0_VF16_0_MAX_LATENCY 0x003f #define cfgBIF_CFG_DEV0_EPF0_VF16_0_PCIE_CAP_LIST 0x0064 #define cfgBIF_CFG_DEV0_EPF0_VF16_0_PCIE_CAP 0x0066 #define cfgBIF_CFG_DEV0_EPF0_VF16_0_DEVICE_CAP 0x0068 #define cfgBIF_CFG_DEV0_EPF0_VF16_0_DEVICE_CNTL 0x006c #define cfgBIF_CFG_DEV0_EPF0_VF16_0_DEVICE_STATUS 0x006e #define cfgBIF_CFG_DEV0_EPF0_VF16_0_LINK_CAP 0x0070 #define cfgBIF_CFG_DEV0_EPF0_VF16_0_LINK_CNTL 0x0074 #define cfgBIF_CFG_DEV0_EPF0_VF16_0_LINK_STATUS 0x0076 #define cfgBIF_CFG_DEV0_EPF0_VF16_0_DEVICE_CAP2 0x0088 #define cfgBIF_CFG_DEV0_EPF0_VF16_0_DEVICE_CNTL2 0x008c #define cfgBIF_CFG_DEV0_EPF0_VF16_0_DEVICE_STATUS2 0x008e #define cfgBIF_CFG_DEV0_EPF0_VF16_0_LINK_CAP2 0x0090 #define cfgBIF_CFG_DEV0_EPF0_VF16_0_LINK_CNTL2 0x0094 #define cfgBIF_CFG_DEV0_EPF0_VF16_0_LINK_STATUS2 0x0096 #define cfgBIF_CFG_DEV0_EPF0_VF16_0_MSI_CAP_LIST 0x00a0 #define cfgBIF_CFG_DEV0_EPF0_VF16_0_MSI_MSG_CNTL 0x00a2 #define cfgBIF_CFG_DEV0_EPF0_VF16_0_MSI_MSG_ADDR_LO 0x00a4 #define cfgBIF_CFG_DEV0_EPF0_VF16_0_MSI_MSG_ADDR_HI 0x00a8 #define cfgBIF_CFG_DEV0_EPF0_VF16_0_MSI_MSG_DATA 0x00a8 #define cfgBIF_CFG_DEV0_EPF0_VF16_0_MSI_MASK 0x00ac #define cfgBIF_CFG_DEV0_EPF0_VF16_0_MSI_MSG_DATA_64 0x00ac #define cfgBIF_CFG_DEV0_EPF0_VF16_0_MSI_MASK_64 0x00b0 #define cfgBIF_CFG_DEV0_EPF0_VF16_0_MSI_PENDING 0x00b0 #define cfgBIF_CFG_DEV0_EPF0_VF16_0_MSI_PENDING_64 0x00b4 #define cfgBIF_CFG_DEV0_EPF0_VF16_0_MSIX_CAP_LIST 0x00c0 #define cfgBIF_CFG_DEV0_EPF0_VF16_0_MSIX_MSG_CNTL 0x00c2 #define cfgBIF_CFG_DEV0_EPF0_VF16_0_MSIX_TABLE 0x00c4 #define cfgBIF_CFG_DEV0_EPF0_VF16_0_MSIX_PBA 0x00c8 #define cfgBIF_CFG_DEV0_EPF0_VF16_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x0100 #define cfgBIF_CFG_DEV0_EPF0_VF16_0_PCIE_VENDOR_SPECIFIC_HDR 0x0104 #define cfgBIF_CFG_DEV0_EPF0_VF16_0_PCIE_VENDOR_SPECIFIC1 0x0108 #define cfgBIF_CFG_DEV0_EPF0_VF16_0_PCIE_VENDOR_SPECIFIC2 0x010c #define cfgBIF_CFG_DEV0_EPF0_VF16_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x0150 #define cfgBIF_CFG_DEV0_EPF0_VF16_0_PCIE_UNCORR_ERR_STATUS 0x0154 #define cfgBIF_CFG_DEV0_EPF0_VF16_0_PCIE_UNCORR_ERR_MASK 0x0158 #define cfgBIF_CFG_DEV0_EPF0_VF16_0_PCIE_UNCORR_ERR_SEVERITY 0x015c #define cfgBIF_CFG_DEV0_EPF0_VF16_0_PCIE_CORR_ERR_STATUS 0x0160 #define cfgBIF_CFG_DEV0_EPF0_VF16_0_PCIE_CORR_ERR_MASK 0x0164 #define cfgBIF_CFG_DEV0_EPF0_VF16_0_PCIE_ADV_ERR_CAP_CNTL 0x0168 #define cfgBIF_CFG_DEV0_EPF0_VF16_0_PCIE_HDR_LOG0 0x016c #define cfgBIF_CFG_DEV0_EPF0_VF16_0_PCIE_HDR_LOG1 0x0170 #define cfgBIF_CFG_DEV0_EPF0_VF16_0_PCIE_HDR_LOG2 0x0174 #define cfgBIF_CFG_DEV0_EPF0_VF16_0_PCIE_HDR_LOG3 0x0178 #define cfgBIF_CFG_DEV0_EPF0_VF16_0_PCIE_TLP_PREFIX_LOG0 0x0188 #define cfgBIF_CFG_DEV0_EPF0_VF16_0_PCIE_TLP_PREFIX_LOG1 0x018c #define cfgBIF_CFG_DEV0_EPF0_VF16_0_PCIE_TLP_PREFIX_LOG2 0x0190 #define cfgBIF_CFG_DEV0_EPF0_VF16_0_PCIE_TLP_PREFIX_LOG3 0x0194 #define cfgBIF_CFG_DEV0_EPF0_VF16_0_PCIE_ATS_ENH_CAP_LIST 0x02b0 #define cfgBIF_CFG_DEV0_EPF0_VF16_0_PCIE_ATS_CAP 0x02b4 #define cfgBIF_CFG_DEV0_EPF0_VF16_0_PCIE_ATS_CNTL 0x02b6 #define cfgBIF_CFG_DEV0_EPF0_VF16_0_PCIE_ARI_ENH_CAP_LIST 0x0328 #define cfgBIF_CFG_DEV0_EPF0_VF16_0_PCIE_ARI_CAP 0x032c #define cfgBIF_CFG_DEV0_EPF0_VF16_0_PCIE_ARI_CNTL 0x032e // addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf17_bifcfgdecp // base address: 0x0 #define cfgBIF_CFG_DEV0_EPF0_VF17_0_VENDOR_ID 0x0000 #define cfgBIF_CFG_DEV0_EPF0_VF17_0_DEVICE_ID 0x0002 #define cfgBIF_CFG_DEV0_EPF0_VF17_0_COMMAND 0x0004 #define cfgBIF_CFG_DEV0_EPF0_VF17_0_STATUS 0x0006 #define cfgBIF_CFG_DEV0_EPF0_VF17_0_REVISION_ID 0x0008 #define cfgBIF_CFG_DEV0_EPF0_VF17_0_PROG_INTERFACE 0x0009 #define cfgBIF_CFG_DEV0_EPF0_VF17_0_SUB_CLASS 0x000a #define cfgBIF_CFG_DEV0_EPF0_VF17_0_BASE_CLASS 0x000b #define cfgBIF_CFG_DEV0_EPF0_VF17_0_CACHE_LINE 0x000c #define cfgBIF_CFG_DEV0_EPF0_VF17_0_LATENCY 0x000d #define cfgBIF_CFG_DEV0_EPF0_VF17_0_HEADER 0x000e #define cfgBIF_CFG_DEV0_EPF0_VF17_0_BIST 0x000f #define cfgBIF_CFG_DEV0_EPF0_VF17_0_BASE_ADDR_1 0x0010 #define cfgBIF_CFG_DEV0_EPF0_VF17_0_BASE_ADDR_2 0x0014 #define cfgBIF_CFG_DEV0_EPF0_VF17_0_BASE_ADDR_3 0x0018 #define cfgBIF_CFG_DEV0_EPF0_VF17_0_BASE_ADDR_4 0x001c #define cfgBIF_CFG_DEV0_EPF0_VF17_0_BASE_ADDR_5 0x0020 #define cfgBIF_CFG_DEV0_EPF0_VF17_0_BASE_ADDR_6 0x0024 #define cfgBIF_CFG_DEV0_EPF0_VF17_0_CARDBUS_CIS_PTR 0x0028 #define cfgBIF_CFG_DEV0_EPF0_VF17_0_ADAPTER_ID 0x002c #define cfgBIF_CFG_DEV0_EPF0_VF17_0_ROM_BASE_ADDR 0x0030 #define cfgBIF_CFG_DEV0_EPF0_VF17_0_CAP_PTR 0x0034 #define cfgBIF_CFG_DEV0_EPF0_VF17_0_INTERRUPT_LINE 0x003c #define cfgBIF_CFG_DEV0_EPF0_VF17_0_INTERRUPT_PIN 0x003d #define cfgBIF_CFG_DEV0_EPF0_VF17_0_MIN_GRANT 0x003e #define cfgBIF_CFG_DEV0_EPF0_VF17_0_MAX_LATENCY 0x003f #define cfgBIF_CFG_DEV0_EPF0_VF17_0_PCIE_CAP_LIST 0x0064 #define cfgBIF_CFG_DEV0_EPF0_VF17_0_PCIE_CAP 0x0066 #define cfgBIF_CFG_DEV0_EPF0_VF17_0_DEVICE_CAP 0x0068 #define cfgBIF_CFG_DEV0_EPF0_VF17_0_DEVICE_CNTL 0x006c #define cfgBIF_CFG_DEV0_EPF0_VF17_0_DEVICE_STATUS 0x006e #define cfgBIF_CFG_DEV0_EPF0_VF17_0_LINK_CAP 0x0070 #define cfgBIF_CFG_DEV0_EPF0_VF17_0_LINK_CNTL 0x0074 #define cfgBIF_CFG_DEV0_EPF0_VF17_0_LINK_STATUS 0x0076 #define cfgBIF_CFG_DEV0_EPF0_VF17_0_DEVICE_CAP2 0x0088 #define cfgBIF_CFG_DEV0_EPF0_VF17_0_DEVICE_CNTL2 0x008c #define cfgBIF_CFG_DEV0_EPF0_VF17_0_DEVICE_STATUS2 0x008e #define cfgBIF_CFG_DEV0_EPF0_VF17_0_LINK_CAP2 0x0090 #define cfgBIF_CFG_DEV0_EPF0_VF17_0_LINK_CNTL2 0x0094 #define cfgBIF_CFG_DEV0_EPF0_VF17_0_LINK_STATUS2 0x0096 #define cfgBIF_CFG_DEV0_EPF0_VF17_0_MSI_CAP_LIST 0x00a0 #define cfgBIF_CFG_DEV0_EPF0_VF17_0_MSI_MSG_CNTL 0x00a2 #define cfgBIF_CFG_DEV0_EPF0_VF17_0_MSI_MSG_ADDR_LO 0x00a4 #define cfgBIF_CFG_DEV0_EPF0_VF17_0_MSI_MSG_ADDR_HI 0x00a8 #define cfgBIF_CFG_DEV0_EPF0_VF17_0_MSI_MSG_DATA 0x00a8 #define cfgBIF_CFG_DEV0_EPF0_VF17_0_MSI_MASK 0x00ac #define cfgBIF_CFG_DEV0_EPF0_VF17_0_MSI_MSG_DATA_64 0x00ac #define cfgBIF_CFG_DEV0_EPF0_VF17_0_MSI_MASK_64 0x00b0 #define cfgBIF_CFG_DEV0_EPF0_VF17_0_MSI_PENDING 0x00b0 #define cfgBIF_CFG_DEV0_EPF0_VF17_0_MSI_PENDING_64 0x00b4 #define cfgBIF_CFG_DEV0_EPF0_VF17_0_MSIX_CAP_LIST 0x00c0 #define cfgBIF_CFG_DEV0_EPF0_VF17_0_MSIX_MSG_CNTL 0x00c2 #define cfgBIF_CFG_DEV0_EPF0_VF17_0_MSIX_TABLE 0x00c4 #define cfgBIF_CFG_DEV0_EPF0_VF17_0_MSIX_PBA 0x00c8 #define cfgBIF_CFG_DEV0_EPF0_VF17_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x0100 #define cfgBIF_CFG_DEV0_EPF0_VF17_0_PCIE_VENDOR_SPECIFIC_HDR 0x0104 #define cfgBIF_CFG_DEV0_EPF0_VF17_0_PCIE_VENDOR_SPECIFIC1 0x0108 #define cfgBIF_CFG_DEV0_EPF0_VF17_0_PCIE_VENDOR_SPECIFIC2 0x010c #define cfgBIF_CFG_DEV0_EPF0_VF17_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x0150 #define cfgBIF_CFG_DEV0_EPF0_VF17_0_PCIE_UNCORR_ERR_STATUS 0x0154 #define cfgBIF_CFG_DEV0_EPF0_VF17_0_PCIE_UNCORR_ERR_MASK 0x0158 #define cfgBIF_CFG_DEV0_EPF0_VF17_0_PCIE_UNCORR_ERR_SEVERITY 0x015c #define cfgBIF_CFG_DEV0_EPF0_VF17_0_PCIE_CORR_ERR_STATUS 0x0160 #define cfgBIF_CFG_DEV0_EPF0_VF17_0_PCIE_CORR_ERR_MASK 0x0164 #define cfgBIF_CFG_DEV0_EPF0_VF17_0_PCIE_ADV_ERR_CAP_CNTL 0x0168 #define cfgBIF_CFG_DEV0_EPF0_VF17_0_PCIE_HDR_LOG0 0x016c #define cfgBIF_CFG_DEV0_EPF0_VF17_0_PCIE_HDR_LOG1 0x0170 #define cfgBIF_CFG_DEV0_EPF0_VF17_0_PCIE_HDR_LOG2 0x0174 #define cfgBIF_CFG_DEV0_EPF0_VF17_0_PCIE_HDR_LOG3 0x0178 #define cfgBIF_CFG_DEV0_EPF0_VF17_0_PCIE_TLP_PREFIX_LOG0 0x0188 #define cfgBIF_CFG_DEV0_EPF0_VF17_0_PCIE_TLP_PREFIX_LOG1 0x018c #define cfgBIF_CFG_DEV0_EPF0_VF17_0_PCIE_TLP_PREFIX_LOG2 0x0190 #define cfgBIF_CFG_DEV0_EPF0_VF17_0_PCIE_TLP_PREFIX_LOG3 0x0194 #define cfgBIF_CFG_DEV0_EPF0_VF17_0_PCIE_ATS_ENH_CAP_LIST 0x02b0 #define cfgBIF_CFG_DEV0_EPF0_VF17_0_PCIE_ATS_CAP 0x02b4 #define cfgBIF_CFG_DEV0_EPF0_VF17_0_PCIE_ATS_CNTL 0x02b6 #define cfgBIF_CFG_DEV0_EPF0_VF17_0_PCIE_ARI_ENH_CAP_LIST 0x0328 #define cfgBIF_CFG_DEV0_EPF0_VF17_0_PCIE_ARI_CAP 0x032c #define cfgBIF_CFG_DEV0_EPF0_VF17_0_PCIE_ARI_CNTL 0x032e // addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf18_bifcfgdecp // base address: 0x0 #define cfgBIF_CFG_DEV0_EPF0_VF18_0_VENDOR_ID 0x0000 #define cfgBIF_CFG_DEV0_EPF0_VF18_0_DEVICE_ID 0x0002 #define cfgBIF_CFG_DEV0_EPF0_VF18_0_COMMAND 0x0004 #define cfgBIF_CFG_DEV0_EPF0_VF18_0_STATUS 0x0006 #define cfgBIF_CFG_DEV0_EPF0_VF18_0_REVISION_ID 0x0008 #define cfgBIF_CFG_DEV0_EPF0_VF18_0_PROG_INTERFACE 0x0009 #define cfgBIF_CFG_DEV0_EPF0_VF18_0_SUB_CLASS 0x000a #define cfgBIF_CFG_DEV0_EPF0_VF18_0_BASE_CLASS 0x000b #define cfgBIF_CFG_DEV0_EPF0_VF18_0_CACHE_LINE 0x000c #define cfgBIF_CFG_DEV0_EPF0_VF18_0_LATENCY 0x000d #define cfgBIF_CFG_DEV0_EPF0_VF18_0_HEADER 0x000e #define cfgBIF_CFG_DEV0_EPF0_VF18_0_BIST 0x000f #define cfgBIF_CFG_DEV0_EPF0_VF18_0_BASE_ADDR_1 0x0010 #define cfgBIF_CFG_DEV0_EPF0_VF18_0_BASE_ADDR_2 0x0014 #define cfgBIF_CFG_DEV0_EPF0_VF18_0_BASE_ADDR_3 0x0018 #define cfgBIF_CFG_DEV0_EPF0_VF18_0_BASE_ADDR_4 0x001c #define cfgBIF_CFG_DEV0_EPF0_VF18_0_BASE_ADDR_5 0x0020 #define cfgBIF_CFG_DEV0_EPF0_VF18_0_BASE_ADDR_6 0x0024 #define cfgBIF_CFG_DEV0_EPF0_VF18_0_CARDBUS_CIS_PTR 0x0028 #define cfgBIF_CFG_DEV0_EPF0_VF18_0_ADAPTER_ID 0x002c #define cfgBIF_CFG_DEV0_EPF0_VF18_0_ROM_BASE_ADDR 0x0030 #define cfgBIF_CFG_DEV0_EPF0_VF18_0_CAP_PTR 0x0034 #define cfgBIF_CFG_DEV0_EPF0_VF18_0_INTERRUPT_LINE 0x003c #define cfgBIF_CFG_DEV0_EPF0_VF18_0_INTERRUPT_PIN 0x003d #define cfgBIF_CFG_DEV0_EPF0_VF18_0_MIN_GRANT 0x003e #define cfgBIF_CFG_DEV0_EPF0_VF18_0_MAX_LATENCY 0x003f #define cfgBIF_CFG_DEV0_EPF0_VF18_0_PCIE_CAP_LIST 0x0064 #define cfgBIF_CFG_DEV0_EPF0_VF18_0_PCIE_CAP 0x0066 #define cfgBIF_CFG_DEV0_EPF0_VF18_0_DEVICE_CAP 0x0068 #define cfgBIF_CFG_DEV0_EPF0_VF18_0_DEVICE_CNTL 0x006c #define cfgBIF_CFG_DEV0_EPF0_VF18_0_DEVICE_STATUS 0x006e #define cfgBIF_CFG_DEV0_EPF0_VF18_0_LINK_CAP 0x0070 #define cfgBIF_CFG_DEV0_EPF0_VF18_0_LINK_CNTL 0x0074 #define cfgBIF_CFG_DEV0_EPF0_VF18_0_LINK_STATUS 0x0076 #define cfgBIF_CFG_DEV0_EPF0_VF18_0_DEVICE_CAP2 0x0088 #define cfgBIF_CFG_DEV0_EPF0_VF18_0_DEVICE_CNTL2 0x008c #define cfgBIF_CFG_DEV0_EPF0_VF18_0_DEVICE_STATUS2 0x008e #define cfgBIF_CFG_DEV0_EPF0_VF18_0_LINK_CAP2 0x0090 #define cfgBIF_CFG_DEV0_EPF0_VF18_0_LINK_CNTL2 0x0094 #define cfgBIF_CFG_DEV0_EPF0_VF18_0_LINK_STATUS2 0x0096 #define cfgBIF_CFG_DEV0_EPF0_VF18_0_MSI_CAP_LIST 0x00a0 #define cfgBIF_CFG_DEV0_EPF0_VF18_0_MSI_MSG_CNTL 0x00a2 #define cfgBIF_CFG_DEV0_EPF0_VF18_0_MSI_MSG_ADDR_LO 0x00a4 #define cfgBIF_CFG_DEV0_EPF0_VF18_0_MSI_MSG_ADDR_HI 0x00a8 #define cfgBIF_CFG_DEV0_EPF0_VF18_0_MSI_MSG_DATA 0x00a8 #define cfgBIF_CFG_DEV0_EPF0_VF18_0_MSI_MASK 0x00ac #define cfgBIF_CFG_DEV0_EPF0_VF18_0_MSI_MSG_DATA_64 0x00ac #define cfgBIF_CFG_DEV0_EPF0_VF18_0_MSI_MASK_64 0x00b0 #define cfgBIF_CFG_DEV0_EPF0_VF18_0_MSI_PENDING 0x00b0 #define cfgBIF_CFG_DEV0_EPF0_VF18_0_MSI_PENDING_64 0x00b4 #define cfgBIF_CFG_DEV0_EPF0_VF18_0_MSIX_CAP_LIST 0x00c0 #define cfgBIF_CFG_DEV0_EPF0_VF18_0_MSIX_MSG_CNTL 0x00c2 #define cfgBIF_CFG_DEV0_EPF0_VF18_0_MSIX_TABLE 0x00c4 #define cfgBIF_CFG_DEV0_EPF0_VF18_0_MSIX_PBA 0x00c8 #define cfgBIF_CFG_DEV0_EPF0_VF18_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x0100 #define cfgBIF_CFG_DEV0_EPF0_VF18_0_PCIE_VENDOR_SPECIFIC_HDR 0x0104 #define cfgBIF_CFG_DEV0_EPF0_VF18_0_PCIE_VENDOR_SPECIFIC1 0x0108 #define cfgBIF_CFG_DEV0_EPF0_VF18_0_PCIE_VENDOR_SPECIFIC2 0x010c #define cfgBIF_CFG_DEV0_EPF0_VF18_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x0150 #define cfgBIF_CFG_DEV0_EPF0_VF18_0_PCIE_UNCORR_ERR_STATUS 0x0154 #define cfgBIF_CFG_DEV0_EPF0_VF18_0_PCIE_UNCORR_ERR_MASK 0x0158 #define cfgBIF_CFG_DEV0_EPF0_VF18_0_PCIE_UNCORR_ERR_SEVERITY 0x015c #define cfgBIF_CFG_DEV0_EPF0_VF18_0_PCIE_CORR_ERR_STATUS 0x0160 #define cfgBIF_CFG_DEV0_EPF0_VF18_0_PCIE_CORR_ERR_MASK 0x0164 #define cfgBIF_CFG_DEV0_EPF0_VF18_0_PCIE_ADV_ERR_CAP_CNTL 0x0168 #define cfgBIF_CFG_DEV0_EPF0_VF18_0_PCIE_HDR_LOG0 0x016c #define cfgBIF_CFG_DEV0_EPF0_VF18_0_PCIE_HDR_LOG1 0x0170 #define cfgBIF_CFG_DEV0_EPF0_VF18_0_PCIE_HDR_LOG2 0x0174 #define cfgBIF_CFG_DEV0_EPF0_VF18_0_PCIE_HDR_LOG3 0x0178 #define cfgBIF_CFG_DEV0_EPF0_VF18_0_PCIE_TLP_PREFIX_LOG0 0x0188 #define cfgBIF_CFG_DEV0_EPF0_VF18_0_PCIE_TLP_PREFIX_LOG1 0x018c #define cfgBIF_CFG_DEV0_EPF0_VF18_0_PCIE_TLP_PREFIX_LOG2 0x0190 #define cfgBIF_CFG_DEV0_EPF0_VF18_0_PCIE_TLP_PREFIX_LOG3 0x0194 #define cfgBIF_CFG_DEV0_EPF0_VF18_0_PCIE_ATS_ENH_CAP_LIST 0x02b0 #define cfgBIF_CFG_DEV0_EPF0_VF18_0_PCIE_ATS_CAP 0x02b4 #define cfgBIF_CFG_DEV0_EPF0_VF18_0_PCIE_ATS_CNTL 0x02b6 #define cfgBIF_CFG_DEV0_EPF0_VF18_0_PCIE_ARI_ENH_CAP_LIST 0x0328 #define cfgBIF_CFG_DEV0_EPF0_VF18_0_PCIE_ARI_CAP 0x032c #define cfgBIF_CFG_DEV0_EPF0_VF18_0_PCIE_ARI_CNTL 0x032e // addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf19_bifcfgdecp // base address: 0x0 #define cfgBIF_CFG_DEV0_EPF0_VF19_0_VENDOR_ID 0x0000 #define cfgBIF_CFG_DEV0_EPF0_VF19_0_DEVICE_ID 0x0002 #define cfgBIF_CFG_DEV0_EPF0_VF19_0_COMMAND 0x0004 #define cfgBIF_CFG_DEV0_EPF0_VF19_0_STATUS 0x0006 #define cfgBIF_CFG_DEV0_EPF0_VF19_0_REVISION_ID 0x0008 #define cfgBIF_CFG_DEV0_EPF0_VF19_0_PROG_INTERFACE 0x0009 #define cfgBIF_CFG_DEV0_EPF0_VF19_0_SUB_CLASS 0x000a #define cfgBIF_CFG_DEV0_EPF0_VF19_0_BASE_CLASS 0x000b #define cfgBIF_CFG_DEV0_EPF0_VF19_0_CACHE_LINE 0x000c #define cfgBIF_CFG_DEV0_EPF0_VF19_0_LATENCY 0x000d #define cfgBIF_CFG_DEV0_EPF0_VF19_0_HEADER 0x000e #define cfgBIF_CFG_DEV0_EPF0_VF19_0_BIST 0x000f #define cfgBIF_CFG_DEV0_EPF0_VF19_0_BASE_ADDR_1 0x0010 #define cfgBIF_CFG_DEV0_EPF0_VF19_0_BASE_ADDR_2 0x0014 #define cfgBIF_CFG_DEV0_EPF0_VF19_0_BASE_ADDR_3 0x0018 #define cfgBIF_CFG_DEV0_EPF0_VF19_0_BASE_ADDR_4 0x001c #define cfgBIF_CFG_DEV0_EPF0_VF19_0_BASE_ADDR_5 0x0020 #define cfgBIF_CFG_DEV0_EPF0_VF19_0_BASE_ADDR_6 0x0024 #define cfgBIF_CFG_DEV0_EPF0_VF19_0_CARDBUS_CIS_PTR 0x0028 #define cfgBIF_CFG_DEV0_EPF0_VF19_0_ADAPTER_ID 0x002c #define cfgBIF_CFG_DEV0_EPF0_VF19_0_ROM_BASE_ADDR 0x0030 #define cfgBIF_CFG_DEV0_EPF0_VF19_0_CAP_PTR 0x0034 #define cfgBIF_CFG_DEV0_EPF0_VF19_0_INTERRUPT_LINE 0x003c #define cfgBIF_CFG_DEV0_EPF0_VF19_0_INTERRUPT_PIN 0x003d #define cfgBIF_CFG_DEV0_EPF0_VF19_0_MIN_GRANT 0x003e #define cfgBIF_CFG_DEV0_EPF0_VF19_0_MAX_LATENCY 0x003f #define cfgBIF_CFG_DEV0_EPF0_VF19_0_PCIE_CAP_LIST 0x0064 #define cfgBIF_CFG_DEV0_EPF0_VF19_0_PCIE_CAP 0x0066 #define cfgBIF_CFG_DEV0_EPF0_VF19_0_DEVICE_CAP 0x0068 #define cfgBIF_CFG_DEV0_EPF0_VF19_0_DEVICE_CNTL 0x006c #define cfgBIF_CFG_DEV0_EPF0_VF19_0_DEVICE_STATUS 0x006e #define cfgBIF_CFG_DEV0_EPF0_VF19_0_LINK_CAP 0x0070 #define cfgBIF_CFG_DEV0_EPF0_VF19_0_LINK_CNTL 0x0074 #define cfgBIF_CFG_DEV0_EPF0_VF19_0_LINK_STATUS 0x0076 #define cfgBIF_CFG_DEV0_EPF0_VF19_0_DEVICE_CAP2 0x0088 #define cfgBIF_CFG_DEV0_EPF0_VF19_0_DEVICE_CNTL2 0x008c #define cfgBIF_CFG_DEV0_EPF0_VF19_0_DEVICE_STATUS2 0x008e #define cfgBIF_CFG_DEV0_EPF0_VF19_0_LINK_CAP2 0x0090 #define cfgBIF_CFG_DEV0_EPF0_VF19_0_LINK_CNTL2 0x0094 #define cfgBIF_CFG_DEV0_EPF0_VF19_0_LINK_STATUS2 0x0096 #define cfgBIF_CFG_DEV0_EPF0_VF19_0_MSI_CAP_LIST 0x00a0 #define cfgBIF_CFG_DEV0_EPF0_VF19_0_MSI_MSG_CNTL 0x00a2 #define cfgBIF_CFG_DEV0_EPF0_VF19_0_MSI_MSG_ADDR_LO 0x00a4 #define cfgBIF_CFG_DEV0_EPF0_VF19_0_MSI_MSG_ADDR_HI 0x00a8 #define cfgBIF_CFG_DEV0_EPF0_VF19_0_MSI_MSG_DATA 0x00a8 #define cfgBIF_CFG_DEV0_EPF0_VF19_0_MSI_MASK 0x00ac #define cfgBIF_CFG_DEV0_EPF0_VF19_0_MSI_MSG_DATA_64 0x00ac #define cfgBIF_CFG_DEV0_EPF0_VF19_0_MSI_MASK_64 0x00b0 #define cfgBIF_CFG_DEV0_EPF0_VF19_0_MSI_PENDING 0x00b0 #define cfgBIF_CFG_DEV0_EPF0_VF19_0_MSI_PENDING_64 0x00b4 #define cfgBIF_CFG_DEV0_EPF0_VF19_0_MSIX_CAP_LIST 0x00c0 #define cfgBIF_CFG_DEV0_EPF0_VF19_0_MSIX_MSG_CNTL 0x00c2 #define cfgBIF_CFG_DEV0_EPF0_VF19_0_MSIX_TABLE 0x00c4 #define cfgBIF_CFG_DEV0_EPF0_VF19_0_MSIX_PBA 0x00c8 #define cfgBIF_CFG_DEV0_EPF0_VF19_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x0100 #define cfgBIF_CFG_DEV0_EPF0_VF19_0_PCIE_VENDOR_SPECIFIC_HDR 0x0104 #define cfgBIF_CFG_DEV0_EPF0_VF19_0_PCIE_VENDOR_SPECIFIC1 0x0108 #define cfgBIF_CFG_DEV0_EPF0_VF19_0_PCIE_VENDOR_SPECIFIC2 0x010c #define cfgBIF_CFG_DEV0_EPF0_VF19_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x0150 #define cfgBIF_CFG_DEV0_EPF0_VF19_0_PCIE_UNCORR_ERR_STATUS 0x0154 #define cfgBIF_CFG_DEV0_EPF0_VF19_0_PCIE_UNCORR_ERR_MASK 0x0158 #define cfgBIF_CFG_DEV0_EPF0_VF19_0_PCIE_UNCORR_ERR_SEVERITY 0x015c #define cfgBIF_CFG_DEV0_EPF0_VF19_0_PCIE_CORR_ERR_STATUS 0x0160 #define cfgBIF_CFG_DEV0_EPF0_VF19_0_PCIE_CORR_ERR_MASK 0x0164 #define cfgBIF_CFG_DEV0_EPF0_VF19_0_PCIE_ADV_ERR_CAP_CNTL 0x0168 #define cfgBIF_CFG_DEV0_EPF0_VF19_0_PCIE_HDR_LOG0 0x016c #define cfgBIF_CFG_DEV0_EPF0_VF19_0_PCIE_HDR_LOG1 0x0170 #define cfgBIF_CFG_DEV0_EPF0_VF19_0_PCIE_HDR_LOG2 0x0174 #define cfgBIF_CFG_DEV0_EPF0_VF19_0_PCIE_HDR_LOG3 0x0178 #define cfgBIF_CFG_DEV0_EPF0_VF19_0_PCIE_TLP_PREFIX_LOG0 0x0188 #define cfgBIF_CFG_DEV0_EPF0_VF19_0_PCIE_TLP_PREFIX_LOG1 0x018c #define cfgBIF_CFG_DEV0_EPF0_VF19_0_PCIE_TLP_PREFIX_LOG2 0x0190 #define cfgBIF_CFG_DEV0_EPF0_VF19_0_PCIE_TLP_PREFIX_LOG3 0x0194 #define cfgBIF_CFG_DEV0_EPF0_VF19_0_PCIE_ATS_ENH_CAP_LIST 0x02b0 #define cfgBIF_CFG_DEV0_EPF0_VF19_0_PCIE_ATS_CAP 0x02b4 #define cfgBIF_CFG_DEV0_EPF0_VF19_0_PCIE_ATS_CNTL 0x02b6 #define cfgBIF_CFG_DEV0_EPF0_VF19_0_PCIE_ARI_ENH_CAP_LIST 0x0328 #define cfgBIF_CFG_DEV0_EPF0_VF19_0_PCIE_ARI_CAP 0x032c #define cfgBIF_CFG_DEV0_EPF0_VF19_0_PCIE_ARI_CNTL 0x032e // addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf20_bifcfgdecp // base address: 0x0 #define cfgBIF_CFG_DEV0_EPF0_VF20_0_VENDOR_ID 0x0000 #define cfgBIF_CFG_DEV0_EPF0_VF20_0_DEVICE_ID 0x0002 #define cfgBIF_CFG_DEV0_EPF0_VF20_0_COMMAND 0x0004 #define cfgBIF_CFG_DEV0_EPF0_VF20_0_STATUS 0x0006 #define cfgBIF_CFG_DEV0_EPF0_VF20_0_REVISION_ID 0x0008 #define cfgBIF_CFG_DEV0_EPF0_VF20_0_PROG_INTERFACE 0x0009 #define cfgBIF_CFG_DEV0_EPF0_VF20_0_SUB_CLASS 0x000a #define cfgBIF_CFG_DEV0_EPF0_VF20_0_BASE_CLASS 0x000b #define cfgBIF_CFG_DEV0_EPF0_VF20_0_CACHE_LINE 0x000c #define cfgBIF_CFG_DEV0_EPF0_VF20_0_LATENCY 0x000d #define cfgBIF_CFG_DEV0_EPF0_VF20_0_HEADER 0x000e #define cfgBIF_CFG_DEV0_EPF0_VF20_0_BIST 0x000f #define cfgBIF_CFG_DEV0_EPF0_VF20_0_BASE_ADDR_1 0x0010 #define cfgBIF_CFG_DEV0_EPF0_VF20_0_BASE_ADDR_2 0x0014 #define cfgBIF_CFG_DEV0_EPF0_VF20_0_BASE_ADDR_3 0x0018 #define cfgBIF_CFG_DEV0_EPF0_VF20_0_BASE_ADDR_4 0x001c #define cfgBIF_CFG_DEV0_EPF0_VF20_0_BASE_ADDR_5 0x0020 #define cfgBIF_CFG_DEV0_EPF0_VF20_0_BASE_ADDR_6 0x0024 #define cfgBIF_CFG_DEV0_EPF0_VF20_0_CARDBUS_CIS_PTR 0x0028 #define cfgBIF_CFG_DEV0_EPF0_VF20_0_ADAPTER_ID 0x002c #define cfgBIF_CFG_DEV0_EPF0_VF20_0_ROM_BASE_ADDR 0x0030 #define cfgBIF_CFG_DEV0_EPF0_VF20_0_CAP_PTR 0x0034 #define cfgBIF_CFG_DEV0_EPF0_VF20_0_INTERRUPT_LINE 0x003c #define cfgBIF_CFG_DEV0_EPF0_VF20_0_INTERRUPT_PIN 0x003d #define cfgBIF_CFG_DEV0_EPF0_VF20_0_MIN_GRANT 0x003e #define cfgBIF_CFG_DEV0_EPF0_VF20_0_MAX_LATENCY 0x003f #define cfgBIF_CFG_DEV0_EPF0_VF20_0_PCIE_CAP_LIST 0x0064 #define cfgBIF_CFG_DEV0_EPF0_VF20_0_PCIE_CAP 0x0066 #define cfgBIF_CFG_DEV0_EPF0_VF20_0_DEVICE_CAP 0x0068 #define cfgBIF_CFG_DEV0_EPF0_VF20_0_DEVICE_CNTL 0x006c #define cfgBIF_CFG_DEV0_EPF0_VF20_0_DEVICE_STATUS 0x006e #define cfgBIF_CFG_DEV0_EPF0_VF20_0_LINK_CAP 0x0070 #define cfgBIF_CFG_DEV0_EPF0_VF20_0_LINK_CNTL 0x0074 #define cfgBIF_CFG_DEV0_EPF0_VF20_0_LINK_STATUS 0x0076 #define cfgBIF_CFG_DEV0_EPF0_VF20_0_DEVICE_CAP2 0x0088 #define cfgBIF_CFG_DEV0_EPF0_VF20_0_DEVICE_CNTL2 0x008c #define cfgBIF_CFG_DEV0_EPF0_VF20_0_DEVICE_STATUS2 0x008e #define cfgBIF_CFG_DEV0_EPF0_VF20_0_LINK_CAP2 0x0090 #define cfgBIF_CFG_DEV0_EPF0_VF20_0_LINK_CNTL2 0x0094 #define cfgBIF_CFG_DEV0_EPF0_VF20_0_LINK_STATUS2 0x0096 #define cfgBIF_CFG_DEV0_EPF0_VF20_0_MSI_CAP_LIST 0x00a0 #define cfgBIF_CFG_DEV0_EPF0_VF20_0_MSI_MSG_CNTL 0x00a2 #define cfgBIF_CFG_DEV0_EPF0_VF20_0_MSI_MSG_ADDR_LO 0x00a4 #define cfgBIF_CFG_DEV0_EPF0_VF20_0_MSI_MSG_ADDR_HI 0x00a8 #define cfgBIF_CFG_DEV0_EPF0_VF20_0_MSI_MSG_DATA 0x00a8 #define cfgBIF_CFG_DEV0_EPF0_VF20_0_MSI_MASK 0x00ac #define cfgBIF_CFG_DEV0_EPF0_VF20_0_MSI_MSG_DATA_64 0x00ac #define cfgBIF_CFG_DEV0_EPF0_VF20_0_MSI_MASK_64 0x00b0 #define cfgBIF_CFG_DEV0_EPF0_VF20_0_MSI_PENDING 0x00b0 #define cfgBIF_CFG_DEV0_EPF0_VF20_0_MSI_PENDING_64 0x00b4 #define cfgBIF_CFG_DEV0_EPF0_VF20_0_MSIX_CAP_LIST 0x00c0 #define cfgBIF_CFG_DEV0_EPF0_VF20_0_MSIX_MSG_CNTL 0x00c2 #define cfgBIF_CFG_DEV0_EPF0_VF20_0_MSIX_TABLE 0x00c4 #define cfgBIF_CFG_DEV0_EPF0_VF20_0_MSIX_PBA 0x00c8 #define cfgBIF_CFG_DEV0_EPF0_VF20_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x0100 #define cfgBIF_CFG_DEV0_EPF0_VF20_0_PCIE_VENDOR_SPECIFIC_HDR 0x0104 #define cfgBIF_CFG_DEV0_EPF0_VF20_0_PCIE_VENDOR_SPECIFIC1 0x0108 #define cfgBIF_CFG_DEV0_EPF0_VF20_0_PCIE_VENDOR_SPECIFIC2 0x010c #define cfgBIF_CFG_DEV0_EPF0_VF20_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x0150 #define cfgBIF_CFG_DEV0_EPF0_VF20_0_PCIE_UNCORR_ERR_STATUS 0x0154 #define cfgBIF_CFG_DEV0_EPF0_VF20_0_PCIE_UNCORR_ERR_MASK 0x0158 #define cfgBIF_CFG_DEV0_EPF0_VF20_0_PCIE_UNCORR_ERR_SEVERITY 0x015c #define cfgBIF_CFG_DEV0_EPF0_VF20_0_PCIE_CORR_ERR_STATUS 0x0160 #define cfgBIF_CFG_DEV0_EPF0_VF20_0_PCIE_CORR_ERR_MASK 0x0164 #define cfgBIF_CFG_DEV0_EPF0_VF20_0_PCIE_ADV_ERR_CAP_CNTL 0x0168 #define cfgBIF_CFG_DEV0_EPF0_VF20_0_PCIE_HDR_LOG0 0x016c #define cfgBIF_CFG_DEV0_EPF0_VF20_0_PCIE_HDR_LOG1 0x0170 #define cfgBIF_CFG_DEV0_EPF0_VF20_0_PCIE_HDR_LOG2 0x0174 #define cfgBIF_CFG_DEV0_EPF0_VF20_0_PCIE_HDR_LOG3 0x0178 #define cfgBIF_CFG_DEV0_EPF0_VF20_0_PCIE_TLP_PREFIX_LOG0 0x0188 #define cfgBIF_CFG_DEV0_EPF0_VF20_0_PCIE_TLP_PREFIX_LOG1 0x018c #define cfgBIF_CFG_DEV0_EPF0_VF20_0_PCIE_TLP_PREFIX_LOG2 0x0190 #define cfgBIF_CFG_DEV0_EPF0_VF20_0_PCIE_TLP_PREFIX_LOG3 0x0194 #define cfgBIF_CFG_DEV0_EPF0_VF20_0_PCIE_ATS_ENH_CAP_LIST 0x02b0 #define cfgBIF_CFG_DEV0_EPF0_VF20_0_PCIE_ATS_CAP 0x02b4 #define cfgBIF_CFG_DEV0_EPF0_VF20_0_PCIE_ATS_CNTL 0x02b6 #define cfgBIF_CFG_DEV0_EPF0_VF20_0_PCIE_ARI_ENH_CAP_LIST 0x0328 #define cfgBIF_CFG_DEV0_EPF0_VF20_0_PCIE_ARI_CAP 0x032c #define cfgBIF_CFG_DEV0_EPF0_VF20_0_PCIE_ARI_CNTL 0x032e // addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf21_bifcfgdecp // base address: 0x0 #define cfgBIF_CFG_DEV0_EPF0_VF21_0_VENDOR_ID 0x0000 #define cfgBIF_CFG_DEV0_EPF0_VF21_0_DEVICE_ID 0x0002 #define cfgBIF_CFG_DEV0_EPF0_VF21_0_COMMAND 0x0004 #define cfgBIF_CFG_DEV0_EPF0_VF21_0_STATUS 0x0006 #define cfgBIF_CFG_DEV0_EPF0_VF21_0_REVISION_ID 0x0008 #define cfgBIF_CFG_DEV0_EPF0_VF21_0_PROG_INTERFACE 0x0009 #define cfgBIF_CFG_DEV0_EPF0_VF21_0_SUB_CLASS 0x000a #define cfgBIF_CFG_DEV0_EPF0_VF21_0_BASE_CLASS 0x000b #define cfgBIF_CFG_DEV0_EPF0_VF21_0_CACHE_LINE 0x000c #define cfgBIF_CFG_DEV0_EPF0_VF21_0_LATENCY 0x000d #define cfgBIF_CFG_DEV0_EPF0_VF21_0_HEADER 0x000e #define cfgBIF_CFG_DEV0_EPF0_VF21_0_BIST 0x000f #define cfgBIF_CFG_DEV0_EPF0_VF21_0_BASE_ADDR_1 0x0010 #define cfgBIF_CFG_DEV0_EPF0_VF21_0_BASE_ADDR_2 0x0014 #define cfgBIF_CFG_DEV0_EPF0_VF21_0_BASE_ADDR_3 0x0018 #define cfgBIF_CFG_DEV0_EPF0_VF21_0_BASE_ADDR_4 0x001c #define cfgBIF_CFG_DEV0_EPF0_VF21_0_BASE_ADDR_5 0x0020 #define cfgBIF_CFG_DEV0_EPF0_VF21_0_BASE_ADDR_6 0x0024 #define cfgBIF_CFG_DEV0_EPF0_VF21_0_CARDBUS_CIS_PTR 0x0028 #define cfgBIF_CFG_DEV0_EPF0_VF21_0_ADAPTER_ID 0x002c #define cfgBIF_CFG_DEV0_EPF0_VF21_0_ROM_BASE_ADDR 0x0030 #define cfgBIF_CFG_DEV0_EPF0_VF21_0_CAP_PTR 0x0034 #define cfgBIF_CFG_DEV0_EPF0_VF21_0_INTERRUPT_LINE 0x003c #define cfgBIF_CFG_DEV0_EPF0_VF21_0_INTERRUPT_PIN 0x003d #define cfgBIF_CFG_DEV0_EPF0_VF21_0_MIN_GRANT 0x003e #define cfgBIF_CFG_DEV0_EPF0_VF21_0_MAX_LATENCY 0x003f #define cfgBIF_CFG_DEV0_EPF0_VF21_0_PCIE_CAP_LIST 0x0064 #define cfgBIF_CFG_DEV0_EPF0_VF21_0_PCIE_CAP 0x0066 #define cfgBIF_CFG_DEV0_EPF0_VF21_0_DEVICE_CAP 0x0068 #define cfgBIF_CFG_DEV0_EPF0_VF21_0_DEVICE_CNTL 0x006c #define cfgBIF_CFG_DEV0_EPF0_VF21_0_DEVICE_STATUS 0x006e #define cfgBIF_CFG_DEV0_EPF0_VF21_0_LINK_CAP 0x0070 #define cfgBIF_CFG_DEV0_EPF0_VF21_0_LINK_CNTL 0x0074 #define cfgBIF_CFG_DEV0_EPF0_VF21_0_LINK_STATUS 0x0076 #define cfgBIF_CFG_DEV0_EPF0_VF21_0_DEVICE_CAP2 0x0088 #define cfgBIF_CFG_DEV0_EPF0_VF21_0_DEVICE_CNTL2 0x008c #define cfgBIF_CFG_DEV0_EPF0_VF21_0_DEVICE_STATUS2 0x008e #define cfgBIF_CFG_DEV0_EPF0_VF21_0_LINK_CAP2 0x0090 #define cfgBIF_CFG_DEV0_EPF0_VF21_0_LINK_CNTL2 0x0094 #define cfgBIF_CFG_DEV0_EPF0_VF21_0_LINK_STATUS2 0x0096 #define cfgBIF_CFG_DEV0_EPF0_VF21_0_MSI_CAP_LIST 0x00a0 #define cfgBIF_CFG_DEV0_EPF0_VF21_0_MSI_MSG_CNTL 0x00a2 #define cfgBIF_CFG_DEV0_EPF0_VF21_0_MSI_MSG_ADDR_LO 0x00a4 #define cfgBIF_CFG_DEV0_EPF0_VF21_0_MSI_MSG_ADDR_HI 0x00a8 #define cfgBIF_CFG_DEV0_EPF0_VF21_0_MSI_MSG_DATA 0x00a8 #define cfgBIF_CFG_DEV0_EPF0_VF21_0_MSI_MASK 0x00ac #define cfgBIF_CFG_DEV0_EPF0_VF21_0_MSI_MSG_DATA_64 0x00ac #define cfgBIF_CFG_DEV0_EPF0_VF21_0_MSI_MASK_64 0x00b0 #define cfgBIF_CFG_DEV0_EPF0_VF21_0_MSI_PENDING 0x00b0 #define cfgBIF_CFG_DEV0_EPF0_VF21_0_MSI_PENDING_64 0x00b4 #define cfgBIF_CFG_DEV0_EPF0_VF21_0_MSIX_CAP_LIST 0x00c0 #define cfgBIF_CFG_DEV0_EPF0_VF21_0_MSIX_MSG_CNTL 0x00c2 #define cfgBIF_CFG_DEV0_EPF0_VF21_0_MSIX_TABLE 0x00c4 #define cfgBIF_CFG_DEV0_EPF0_VF21_0_MSIX_PBA 0x00c8 #define cfgBIF_CFG_DEV0_EPF0_VF21_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x0100 #define cfgBIF_CFG_DEV0_EPF0_VF21_0_PCIE_VENDOR_SPECIFIC_HDR 0x0104 #define cfgBIF_CFG_DEV0_EPF0_VF21_0_PCIE_VENDOR_SPECIFIC1 0x0108 #define cfgBIF_CFG_DEV0_EPF0_VF21_0_PCIE_VENDOR_SPECIFIC2 0x010c #define cfgBIF_CFG_DEV0_EPF0_VF21_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x0150 #define cfgBIF_CFG_DEV0_EPF0_VF21_0_PCIE_UNCORR_ERR_STATUS 0x0154 #define cfgBIF_CFG_DEV0_EPF0_VF21_0_PCIE_UNCORR_ERR_MASK 0x0158 #define cfgBIF_CFG_DEV0_EPF0_VF21_0_PCIE_UNCORR_ERR_SEVERITY 0x015c #define cfgBIF_CFG_DEV0_EPF0_VF21_0_PCIE_CORR_ERR_STATUS 0x0160 #define cfgBIF_CFG_DEV0_EPF0_VF21_0_PCIE_CORR_ERR_MASK 0x0164 #define cfgBIF_CFG_DEV0_EPF0_VF21_0_PCIE_ADV_ERR_CAP_CNTL 0x0168 #define cfgBIF_CFG_DEV0_EPF0_VF21_0_PCIE_HDR_LOG0 0x016c #define cfgBIF_CFG_DEV0_EPF0_VF21_0_PCIE_HDR_LOG1 0x0170 #define cfgBIF_CFG_DEV0_EPF0_VF21_0_PCIE_HDR_LOG2 0x0174 #define cfgBIF_CFG_DEV0_EPF0_VF21_0_PCIE_HDR_LOG3 0x0178 #define cfgBIF_CFG_DEV0_EPF0_VF21_0_PCIE_TLP_PREFIX_LOG0 0x0188 #define cfgBIF_CFG_DEV0_EPF0_VF21_0_PCIE_TLP_PREFIX_LOG1 0x018c #define cfgBIF_CFG_DEV0_EPF0_VF21_0_PCIE_TLP_PREFIX_LOG2 0x0190 #define cfgBIF_CFG_DEV0_EPF0_VF21_0_PCIE_TLP_PREFIX_LOG3 0x0194 #define cfgBIF_CFG_DEV0_EPF0_VF21_0_PCIE_ATS_ENH_CAP_LIST 0x02b0 #define cfgBIF_CFG_DEV0_EPF0_VF21_0_PCIE_ATS_CAP 0x02b4 #define cfgBIF_CFG_DEV0_EPF0_VF21_0_PCIE_ATS_CNTL 0x02b6 #define cfgBIF_CFG_DEV0_EPF0_VF21_0_PCIE_ARI_ENH_CAP_LIST 0x0328 #define cfgBIF_CFG_DEV0_EPF0_VF21_0_PCIE_ARI_CAP 0x032c #define cfgBIF_CFG_DEV0_EPF0_VF21_0_PCIE_ARI_CNTL 0x032e // addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf22_bifcfgdecp // base address: 0x0 #define cfgBIF_CFG_DEV0_EPF0_VF22_0_VENDOR_ID 0x0000 #define cfgBIF_CFG_DEV0_EPF0_VF22_0_DEVICE_ID 0x0002 #define cfgBIF_CFG_DEV0_EPF0_VF22_0_COMMAND 0x0004 #define cfgBIF_CFG_DEV0_EPF0_VF22_0_STATUS 0x0006 #define cfgBIF_CFG_DEV0_EPF0_VF22_0_REVISION_ID 0x0008 #define cfgBIF_CFG_DEV0_EPF0_VF22_0_PROG_INTERFACE 0x0009 #define cfgBIF_CFG_DEV0_EPF0_VF22_0_SUB_CLASS 0x000a #define cfgBIF_CFG_DEV0_EPF0_VF22_0_BASE_CLASS 0x000b #define cfgBIF_CFG_DEV0_EPF0_VF22_0_CACHE_LINE 0x000c #define cfgBIF_CFG_DEV0_EPF0_VF22_0_LATENCY 0x000d #define cfgBIF_CFG_DEV0_EPF0_VF22_0_HEADER 0x000e #define cfgBIF_CFG_DEV0_EPF0_VF22_0_BIST 0x000f #define cfgBIF_CFG_DEV0_EPF0_VF22_0_BASE_ADDR_1 0x0010 #define cfgBIF_CFG_DEV0_EPF0_VF22_0_BASE_ADDR_2 0x0014 #define cfgBIF_CFG_DEV0_EPF0_VF22_0_BASE_ADDR_3 0x0018 #define cfgBIF_CFG_DEV0_EPF0_VF22_0_BASE_ADDR_4 0x001c #define cfgBIF_CFG_DEV0_EPF0_VF22_0_BASE_ADDR_5 0x0020 #define cfgBIF_CFG_DEV0_EPF0_VF22_0_BASE_ADDR_6 0x0024 #define cfgBIF_CFG_DEV0_EPF0_VF22_0_CARDBUS_CIS_PTR 0x0028 #define cfgBIF_CFG_DEV0_EPF0_VF22_0_ADAPTER_ID 0x002c #define cfgBIF_CFG_DEV0_EPF0_VF22_0_ROM_BASE_ADDR 0x0030 #define cfgBIF_CFG_DEV0_EPF0_VF22_0_CAP_PTR 0x0034 #define cfgBIF_CFG_DEV0_EPF0_VF22_0_INTERRUPT_LINE 0x003c #define cfgBIF_CFG_DEV0_EPF0_VF22_0_INTERRUPT_PIN 0x003d #define cfgBIF_CFG_DEV0_EPF0_VF22_0_MIN_GRANT 0x003e #define cfgBIF_CFG_DEV0_EPF0_VF22_0_MAX_LATENCY 0x003f #define cfgBIF_CFG_DEV0_EPF0_VF22_0_PCIE_CAP_LIST 0x0064 #define cfgBIF_CFG_DEV0_EPF0_VF22_0_PCIE_CAP 0x0066 #define cfgBIF_CFG_DEV0_EPF0_VF22_0_DEVICE_CAP 0x0068 #define cfgBIF_CFG_DEV0_EPF0_VF22_0_DEVICE_CNTL 0x006c #define cfgBIF_CFG_DEV0_EPF0_VF22_0_DEVICE_STATUS 0x006e #define cfgBIF_CFG_DEV0_EPF0_VF22_0_LINK_CAP 0x0070 #define cfgBIF_CFG_DEV0_EPF0_VF22_0_LINK_CNTL 0x0074 #define cfgBIF_CFG_DEV0_EPF0_VF22_0_LINK_STATUS 0x0076 #define cfgBIF_CFG_DEV0_EPF0_VF22_0_DEVICE_CAP2 0x0088 #define cfgBIF_CFG_DEV0_EPF0_VF22_0_DEVICE_CNTL2 0x008c #define cfgBIF_CFG_DEV0_EPF0_VF22_0_DEVICE_STATUS2 0x008e #define cfgBIF_CFG_DEV0_EPF0_VF22_0_LINK_CAP2 0x0090 #define cfgBIF_CFG_DEV0_EPF0_VF22_0_LINK_CNTL2 0x0094 #define cfgBIF_CFG_DEV0_EPF0_VF22_0_LINK_STATUS2 0x0096 #define cfgBIF_CFG_DEV0_EPF0_VF22_0_MSI_CAP_LIST 0x00a0 #define cfgBIF_CFG_DEV0_EPF0_VF22_0_MSI_MSG_CNTL 0x00a2 #define cfgBIF_CFG_DEV0_EPF0_VF22_0_MSI_MSG_ADDR_LO 0x00a4 #define cfgBIF_CFG_DEV0_EPF0_VF22_0_MSI_MSG_ADDR_HI 0x00a8 #define cfgBIF_CFG_DEV0_EPF0_VF22_0_MSI_MSG_DATA 0x00a8 #define cfgBIF_CFG_DEV0_EPF0_VF22_0_MSI_MASK 0x00ac #define cfgBIF_CFG_DEV0_EPF0_VF22_0_MSI_MSG_DATA_64 0x00ac #define cfgBIF_CFG_DEV0_EPF0_VF22_0_MSI_MASK_64 0x00b0 #define cfgBIF_CFG_DEV0_EPF0_VF22_0_MSI_PENDING 0x00b0 #define cfgBIF_CFG_DEV0_EPF0_VF22_0_MSI_PENDING_64 0x00b4 #define cfgBIF_CFG_DEV0_EPF0_VF22_0_MSIX_CAP_LIST 0x00c0 #define cfgBIF_CFG_DEV0_EPF0_VF22_0_MSIX_MSG_CNTL 0x00c2 #define cfgBIF_CFG_DEV0_EPF0_VF22_0_MSIX_TABLE 0x00c4 #define cfgBIF_CFG_DEV0_EPF0_VF22_0_MSIX_PBA 0x00c8 #define cfgBIF_CFG_DEV0_EPF0_VF22_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x0100 #define cfgBIF_CFG_DEV0_EPF0_VF22_0_PCIE_VENDOR_SPECIFIC_HDR 0x0104 #define cfgBIF_CFG_DEV0_EPF0_VF22_0_PCIE_VENDOR_SPECIFIC1 0x0108 #define cfgBIF_CFG_DEV0_EPF0_VF22_0_PCIE_VENDOR_SPECIFIC2 0x010c #define cfgBIF_CFG_DEV0_EPF0_VF22_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x0150 #define cfgBIF_CFG_DEV0_EPF0_VF22_0_PCIE_UNCORR_ERR_STATUS 0x0154 #define cfgBIF_CFG_DEV0_EPF0_VF22_0_PCIE_UNCORR_ERR_MASK 0x0158 #define cfgBIF_CFG_DEV0_EPF0_VF22_0_PCIE_UNCORR_ERR_SEVERITY 0x015c #define cfgBIF_CFG_DEV0_EPF0_VF22_0_PCIE_CORR_ERR_STATUS 0x0160 #define cfgBIF_CFG_DEV0_EPF0_VF22_0_PCIE_CORR_ERR_MASK 0x0164 #define cfgBIF_CFG_DEV0_EPF0_VF22_0_PCIE_ADV_ERR_CAP_CNTL 0x0168 #define cfgBIF_CFG_DEV0_EPF0_VF22_0_PCIE_HDR_LOG0 0x016c #define cfgBIF_CFG_DEV0_EPF0_VF22_0_PCIE_HDR_LOG1 0x0170 #define cfgBIF_CFG_DEV0_EPF0_VF22_0_PCIE_HDR_LOG2 0x0174 #define cfgBIF_CFG_DEV0_EPF0_VF22_0_PCIE_HDR_LOG3 0x0178 #define cfgBIF_CFG_DEV0_EPF0_VF22_0_PCIE_TLP_PREFIX_LOG0 0x0188 #define cfgBIF_CFG_DEV0_EPF0_VF22_0_PCIE_TLP_PREFIX_LOG1 0x018c #define cfgBIF_CFG_DEV0_EPF0_VF22_0_PCIE_TLP_PREFIX_LOG2 0x0190 #define cfgBIF_CFG_DEV0_EPF0_VF22_0_PCIE_TLP_PREFIX_LOG3 0x0194 #define cfgBIF_CFG_DEV0_EPF0_VF22_0_PCIE_ATS_ENH_CAP_LIST 0x02b0 #define cfgBIF_CFG_DEV0_EPF0_VF22_0_PCIE_ATS_CAP 0x02b4 #define cfgBIF_CFG_DEV0_EPF0_VF22_0_PCIE_ATS_CNTL 0x02b6 #define cfgBIF_CFG_DEV0_EPF0_VF22_0_PCIE_ARI_ENH_CAP_LIST 0x0328 #define cfgBIF_CFG_DEV0_EPF0_VF22_0_PCIE_ARI_CAP 0x032c #define cfgBIF_CFG_DEV0_EPF0_VF22_0_PCIE_ARI_CNTL 0x032e // addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf23_bifcfgdecp // base address: 0x0 #define cfgBIF_CFG_DEV0_EPF0_VF23_0_VENDOR_ID 0x0000 #define cfgBIF_CFG_DEV0_EPF0_VF23_0_DEVICE_ID 0x0002 #define cfgBIF_CFG_DEV0_EPF0_VF23_0_COMMAND 0x0004 #define cfgBIF_CFG_DEV0_EPF0_VF23_0_STATUS 0x0006 #define cfgBIF_CFG_DEV0_EPF0_VF23_0_REVISION_ID 0x0008 #define cfgBIF_CFG_DEV0_EPF0_VF23_0_PROG_INTERFACE 0x0009 #define cfgBIF_CFG_DEV0_EPF0_VF23_0_SUB_CLASS 0x000a #define cfgBIF_CFG_DEV0_EPF0_VF23_0_BASE_CLASS 0x000b #define cfgBIF_CFG_DEV0_EPF0_VF23_0_CACHE_LINE 0x000c #define cfgBIF_CFG_DEV0_EPF0_VF23_0_LATENCY 0x000d #define cfgBIF_CFG_DEV0_EPF0_VF23_0_HEADER 0x000e #define cfgBIF_CFG_DEV0_EPF0_VF23_0_BIST 0x000f #define cfgBIF_CFG_DEV0_EPF0_VF23_0_BASE_ADDR_1 0x0010 #define cfgBIF_CFG_DEV0_EPF0_VF23_0_BASE_ADDR_2 0x0014 #define cfgBIF_CFG_DEV0_EPF0_VF23_0_BASE_ADDR_3 0x0018 #define cfgBIF_CFG_DEV0_EPF0_VF23_0_BASE_ADDR_4 0x001c #define cfgBIF_CFG_DEV0_EPF0_VF23_0_BASE_ADDR_5 0x0020 #define cfgBIF_CFG_DEV0_EPF0_VF23_0_BASE_ADDR_6 0x0024 #define cfgBIF_CFG_DEV0_EPF0_VF23_0_CARDBUS_CIS_PTR 0x0028 #define cfgBIF_CFG_DEV0_EPF0_VF23_0_ADAPTER_ID 0x002c #define cfgBIF_CFG_DEV0_EPF0_VF23_0_ROM_BASE_ADDR 0x0030 #define cfgBIF_CFG_DEV0_EPF0_VF23_0_CAP_PTR 0x0034 #define cfgBIF_CFG_DEV0_EPF0_VF23_0_INTERRUPT_LINE 0x003c #define cfgBIF_CFG_DEV0_EPF0_VF23_0_INTERRUPT_PIN 0x003d #define cfgBIF_CFG_DEV0_EPF0_VF23_0_MIN_GRANT 0x003e #define cfgBIF_CFG_DEV0_EPF0_VF23_0_MAX_LATENCY 0x003f #define cfgBIF_CFG_DEV0_EPF0_VF23_0_PCIE_CAP_LIST 0x0064 #define cfgBIF_CFG_DEV0_EPF0_VF23_0_PCIE_CAP 0x0066 #define cfgBIF_CFG_DEV0_EPF0_VF23_0_DEVICE_CAP 0x0068 #define cfgBIF_CFG_DEV0_EPF0_VF23_0_DEVICE_CNTL 0x006c #define cfgBIF_CFG_DEV0_EPF0_VF23_0_DEVICE_STATUS 0x006e #define cfgBIF_CFG_DEV0_EPF0_VF23_0_LINK_CAP 0x0070 #define cfgBIF_CFG_DEV0_EPF0_VF23_0_LINK_CNTL 0x0074 #define cfgBIF_CFG_DEV0_EPF0_VF23_0_LINK_STATUS 0x0076 #define cfgBIF_CFG_DEV0_EPF0_VF23_0_DEVICE_CAP2 0x0088 #define cfgBIF_CFG_DEV0_EPF0_VF23_0_DEVICE_CNTL2 0x008c #define cfgBIF_CFG_DEV0_EPF0_VF23_0_DEVICE_STATUS2 0x008e #define cfgBIF_CFG_DEV0_EPF0_VF23_0_LINK_CAP2 0x0090 #define cfgBIF_CFG_DEV0_EPF0_VF23_0_LINK_CNTL2 0x0094 #define cfgBIF_CFG_DEV0_EPF0_VF23_0_LINK_STATUS2 0x0096 #define cfgBIF_CFG_DEV0_EPF0_VF23_0_MSI_CAP_LIST 0x00a0 #define cfgBIF_CFG_DEV0_EPF0_VF23_0_MSI_MSG_CNTL 0x00a2 #define cfgBIF_CFG_DEV0_EPF0_VF23_0_MSI_MSG_ADDR_LO 0x00a4 #define cfgBIF_CFG_DEV0_EPF0_VF23_0_MSI_MSG_ADDR_HI 0x00a8 #define cfgBIF_CFG_DEV0_EPF0_VF23_0_MSI_MSG_DATA 0x00a8 #define cfgBIF_CFG_DEV0_EPF0_VF23_0_MSI_MASK 0x00ac #define cfgBIF_CFG_DEV0_EPF0_VF23_0_MSI_MSG_DATA_64 0x00ac #define cfgBIF_CFG_DEV0_EPF0_VF23_0_MSI_MASK_64 0x00b0 #define cfgBIF_CFG_DEV0_EPF0_VF23_0_MSI_PENDING 0x00b0 #define cfgBIF_CFG_DEV0_EPF0_VF23_0_MSI_PENDING_64 0x00b4 #define cfgBIF_CFG_DEV0_EPF0_VF23_0_MSIX_CAP_LIST 0x00c0 #define cfgBIF_CFG_DEV0_EPF0_VF23_0_MSIX_MSG_CNTL 0x00c2 #define cfgBIF_CFG_DEV0_EPF0_VF23_0_MSIX_TABLE 0x00c4 #define cfgBIF_CFG_DEV0_EPF0_VF23_0_MSIX_PBA 0x00c8 #define cfgBIF_CFG_DEV0_EPF0_VF23_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x0100 #define cfgBIF_CFG_DEV0_EPF0_VF23_0_PCIE_VENDOR_SPECIFIC_HDR 0x0104 #define cfgBIF_CFG_DEV0_EPF0_VF23_0_PCIE_VENDOR_SPECIFIC1 0x0108 #define cfgBIF_CFG_DEV0_EPF0_VF23_0_PCIE_VENDOR_SPECIFIC2 0x010c #define cfgBIF_CFG_DEV0_EPF0_VF23_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x0150 #define cfgBIF_CFG_DEV0_EPF0_VF23_0_PCIE_UNCORR_ERR_STATUS 0x0154 #define cfgBIF_CFG_DEV0_EPF0_VF23_0_PCIE_UNCORR_ERR_MASK 0x0158 #define cfgBIF_CFG_DEV0_EPF0_VF23_0_PCIE_UNCORR_ERR_SEVERITY 0x015c #define cfgBIF_CFG_DEV0_EPF0_VF23_0_PCIE_CORR_ERR_STATUS 0x0160 #define cfgBIF_CFG_DEV0_EPF0_VF23_0_PCIE_CORR_ERR_MASK 0x0164 #define cfgBIF_CFG_DEV0_EPF0_VF23_0_PCIE_ADV_ERR_CAP_CNTL 0x0168 #define cfgBIF_CFG_DEV0_EPF0_VF23_0_PCIE_HDR_LOG0 0x016c #define cfgBIF_CFG_DEV0_EPF0_VF23_0_PCIE_HDR_LOG1 0x0170 #define cfgBIF_CFG_DEV0_EPF0_VF23_0_PCIE_HDR_LOG2 0x0174 #define cfgBIF_CFG_DEV0_EPF0_VF23_0_PCIE_HDR_LOG3 0x0178 #define cfgBIF_CFG_DEV0_EPF0_VF23_0_PCIE_TLP_PREFIX_LOG0 0x0188 #define cfgBIF_CFG_DEV0_EPF0_VF23_0_PCIE_TLP_PREFIX_LOG1 0x018c #define cfgBIF_CFG_DEV0_EPF0_VF23_0_PCIE_TLP_PREFIX_LOG2 0x0190 #define cfgBIF_CFG_DEV0_EPF0_VF23_0_PCIE_TLP_PREFIX_LOG3 0x0194 #define cfgBIF_CFG_DEV0_EPF0_VF23_0_PCIE_ATS_ENH_CAP_LIST 0x02b0 #define cfgBIF_CFG_DEV0_EPF0_VF23_0_PCIE_ATS_CAP 0x02b4 #define cfgBIF_CFG_DEV0_EPF0_VF23_0_PCIE_ATS_CNTL 0x02b6 #define cfgBIF_CFG_DEV0_EPF0_VF23_0_PCIE_ARI_ENH_CAP_LIST 0x0328 #define cfgBIF_CFG_DEV0_EPF0_VF23_0_PCIE_ARI_CAP 0x032c #define cfgBIF_CFG_DEV0_EPF0_VF23_0_PCIE_ARI_CNTL 0x032e // addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf24_bifcfgdecp // base address: 0x0 #define cfgBIF_CFG_DEV0_EPF0_VF24_0_VENDOR_ID 0x0000 #define cfgBIF_CFG_DEV0_EPF0_VF24_0_DEVICE_ID 0x0002 #define cfgBIF_CFG_DEV0_EPF0_VF24_0_COMMAND 0x0004 #define cfgBIF_CFG_DEV0_EPF0_VF24_0_STATUS 0x0006 #define cfgBIF_CFG_DEV0_EPF0_VF24_0_REVISION_ID 0x0008 #define cfgBIF_CFG_DEV0_EPF0_VF24_0_PROG_INTERFACE 0x0009 #define cfgBIF_CFG_DEV0_EPF0_VF24_0_SUB_CLASS 0x000a #define cfgBIF_CFG_DEV0_EPF0_VF24_0_BASE_CLASS 0x000b #define cfgBIF_CFG_DEV0_EPF0_VF24_0_CACHE_LINE 0x000c #define cfgBIF_CFG_DEV0_EPF0_VF24_0_LATENCY 0x000d #define cfgBIF_CFG_DEV0_EPF0_VF24_0_HEADER 0x000e #define cfgBIF_CFG_DEV0_EPF0_VF24_0_BIST 0x000f #define cfgBIF_CFG_DEV0_EPF0_VF24_0_BASE_ADDR_1 0x0010 #define cfgBIF_CFG_DEV0_EPF0_VF24_0_BASE_ADDR_2 0x0014 #define cfgBIF_CFG_DEV0_EPF0_VF24_0_BASE_ADDR_3 0x0018 #define cfgBIF_CFG_DEV0_EPF0_VF24_0_BASE_ADDR_4 0x001c #define cfgBIF_CFG_DEV0_EPF0_VF24_0_BASE_ADDR_5 0x0020 #define cfgBIF_CFG_DEV0_EPF0_VF24_0_BASE_ADDR_6 0x0024 #define cfgBIF_CFG_DEV0_EPF0_VF24_0_CARDBUS_CIS_PTR 0x0028 #define cfgBIF_CFG_DEV0_EPF0_VF24_0_ADAPTER_ID 0x002c #define cfgBIF_CFG_DEV0_EPF0_VF24_0_ROM_BASE_ADDR 0x0030 #define cfgBIF_CFG_DEV0_EPF0_VF24_0_CAP_PTR 0x0034 #define cfgBIF_CFG_DEV0_EPF0_VF24_0_INTERRUPT_LINE 0x003c #define cfgBIF_CFG_DEV0_EPF0_VF24_0_INTERRUPT_PIN 0x003d #define cfgBIF_CFG_DEV0_EPF0_VF24_0_MIN_GRANT 0x003e #define cfgBIF_CFG_DEV0_EPF0_VF24_0_MAX_LATENCY 0x003f #define cfgBIF_CFG_DEV0_EPF0_VF24_0_PCIE_CAP_LIST 0x0064 #define cfgBIF_CFG_DEV0_EPF0_VF24_0_PCIE_CAP 0x0066 #define cfgBIF_CFG_DEV0_EPF0_VF24_0_DEVICE_CAP 0x0068 #define cfgBIF_CFG_DEV0_EPF0_VF24_0_DEVICE_CNTL 0x006c #define cfgBIF_CFG_DEV0_EPF0_VF24_0_DEVICE_STATUS 0x006e #define cfgBIF_CFG_DEV0_EPF0_VF24_0_LINK_CAP 0x0070 #define cfgBIF_CFG_DEV0_EPF0_VF24_0_LINK_CNTL 0x0074 #define cfgBIF_CFG_DEV0_EPF0_VF24_0_LINK_STATUS 0x0076 #define cfgBIF_CFG_DEV0_EPF0_VF24_0_DEVICE_CAP2 0x0088 #define cfgBIF_CFG_DEV0_EPF0_VF24_0_DEVICE_CNTL2 0x008c #define cfgBIF_CFG_DEV0_EPF0_VF24_0_DEVICE_STATUS2 0x008e #define cfgBIF_CFG_DEV0_EPF0_VF24_0_LINK_CAP2 0x0090 #define cfgBIF_CFG_DEV0_EPF0_VF24_0_LINK_CNTL2 0x0094 #define cfgBIF_CFG_DEV0_EPF0_VF24_0_LINK_STATUS2 0x0096 #define cfgBIF_CFG_DEV0_EPF0_VF24_0_MSI_CAP_LIST 0x00a0 #define cfgBIF_CFG_DEV0_EPF0_VF24_0_MSI_MSG_CNTL 0x00a2 #define cfgBIF_CFG_DEV0_EPF0_VF24_0_MSI_MSG_ADDR_LO 0x00a4 #define cfgBIF_CFG_DEV0_EPF0_VF24_0_MSI_MSG_ADDR_HI 0x00a8 #define cfgBIF_CFG_DEV0_EPF0_VF24_0_MSI_MSG_DATA 0x00a8 #define cfgBIF_CFG_DEV0_EPF0_VF24_0_MSI_MASK 0x00ac #define cfgBIF_CFG_DEV0_EPF0_VF24_0_MSI_MSG_DATA_64 0x00ac #define cfgBIF_CFG_DEV0_EPF0_VF24_0_MSI_MASK_64 0x00b0 #define cfgBIF_CFG_DEV0_EPF0_VF24_0_MSI_PENDING 0x00b0 #define cfgBIF_CFG_DEV0_EPF0_VF24_0_MSI_PENDING_64 0x00b4 #define cfgBIF_CFG_DEV0_EPF0_VF24_0_MSIX_CAP_LIST 0x00c0 #define cfgBIF_CFG_DEV0_EPF0_VF24_0_MSIX_MSG_CNTL 0x00c2 #define cfgBIF_CFG_DEV0_EPF0_VF24_0_MSIX_TABLE 0x00c4 #define cfgBIF_CFG_DEV0_EPF0_VF24_0_MSIX_PBA 0x00c8 #define cfgBIF_CFG_DEV0_EPF0_VF24_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x0100 #define cfgBIF_CFG_DEV0_EPF0_VF24_0_PCIE_VENDOR_SPECIFIC_HDR 0x0104 #define cfgBIF_CFG_DEV0_EPF0_VF24_0_PCIE_VENDOR_SPECIFIC1 0x0108 #define cfgBIF_CFG_DEV0_EPF0_VF24_0_PCIE_VENDOR_SPECIFIC2 0x010c #define cfgBIF_CFG_DEV0_EPF0_VF24_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x0150 #define cfgBIF_CFG_DEV0_EPF0_VF24_0_PCIE_UNCORR_ERR_STATUS 0x0154 #define cfgBIF_CFG_DEV0_EPF0_VF24_0_PCIE_UNCORR_ERR_MASK 0x0158 #define cfgBIF_CFG_DEV0_EPF0_VF24_0_PCIE_UNCORR_ERR_SEVERITY 0x015c #define cfgBIF_CFG_DEV0_EPF0_VF24_0_PCIE_CORR_ERR_STATUS 0x0160 #define cfgBIF_CFG_DEV0_EPF0_VF24_0_PCIE_CORR_ERR_MASK 0x0164 #define cfgBIF_CFG_DEV0_EPF0_VF24_0_PCIE_ADV_ERR_CAP_CNTL 0x0168 #define cfgBIF_CFG_DEV0_EPF0_VF24_0_PCIE_HDR_LOG0 0x016c #define cfgBIF_CFG_DEV0_EPF0_VF24_0_PCIE_HDR_LOG1 0x0170 #define cfgBIF_CFG_DEV0_EPF0_VF24_0_PCIE_HDR_LOG2 0x0174 #define cfgBIF_CFG_DEV0_EPF0_VF24_0_PCIE_HDR_LOG3 0x0178 #define cfgBIF_CFG_DEV0_EPF0_VF24_0_PCIE_TLP_PREFIX_LOG0 0x0188 #define cfgBIF_CFG_DEV0_EPF0_VF24_0_PCIE_TLP_PREFIX_LOG1 0x018c #define cfgBIF_CFG_DEV0_EPF0_VF24_0_PCIE_TLP_PREFIX_LOG2 0x0190 #define cfgBIF_CFG_DEV0_EPF0_VF24_0_PCIE_TLP_PREFIX_LOG3 0x0194 #define cfgBIF_CFG_DEV0_EPF0_VF24_0_PCIE_ATS_ENH_CAP_LIST 0x02b0 #define cfgBIF_CFG_DEV0_EPF0_VF24_0_PCIE_ATS_CAP 0x02b4 #define cfgBIF_CFG_DEV0_EPF0_VF24_0_PCIE_ATS_CNTL 0x02b6 #define cfgBIF_CFG_DEV0_EPF0_VF24_0_PCIE_ARI_ENH_CAP_LIST 0x0328 #define cfgBIF_CFG_DEV0_EPF0_VF24_0_PCIE_ARI_CAP 0x032c #define cfgBIF_CFG_DEV0_EPF0_VF24_0_PCIE_ARI_CNTL 0x032e // addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf25_bifcfgdecp // base address: 0x0 #define cfgBIF_CFG_DEV0_EPF0_VF25_0_VENDOR_ID 0x0000 #define cfgBIF_CFG_DEV0_EPF0_VF25_0_DEVICE_ID 0x0002 #define cfgBIF_CFG_DEV0_EPF0_VF25_0_COMMAND 0x0004 #define cfgBIF_CFG_DEV0_EPF0_VF25_0_STATUS 0x0006 #define cfgBIF_CFG_DEV0_EPF0_VF25_0_REVISION_ID 0x0008 #define cfgBIF_CFG_DEV0_EPF0_VF25_0_PROG_INTERFACE 0x0009 #define cfgBIF_CFG_DEV0_EPF0_VF25_0_SUB_CLASS 0x000a #define cfgBIF_CFG_DEV0_EPF0_VF25_0_BASE_CLASS 0x000b #define cfgBIF_CFG_DEV0_EPF0_VF25_0_CACHE_LINE 0x000c #define cfgBIF_CFG_DEV0_EPF0_VF25_0_LATENCY 0x000d #define cfgBIF_CFG_DEV0_EPF0_VF25_0_HEADER 0x000e #define cfgBIF_CFG_DEV0_EPF0_VF25_0_BIST 0x000f #define cfgBIF_CFG_DEV0_EPF0_VF25_0_BASE_ADDR_1 0x0010 #define cfgBIF_CFG_DEV0_EPF0_VF25_0_BASE_ADDR_2 0x0014 #define cfgBIF_CFG_DEV0_EPF0_VF25_0_BASE_ADDR_3 0x0018 #define cfgBIF_CFG_DEV0_EPF0_VF25_0_BASE_ADDR_4 0x001c #define cfgBIF_CFG_DEV0_EPF0_VF25_0_BASE_ADDR_5 0x0020 #define cfgBIF_CFG_DEV0_EPF0_VF25_0_BASE_ADDR_6 0x0024 #define cfgBIF_CFG_DEV0_EPF0_VF25_0_CARDBUS_CIS_PTR 0x0028 #define cfgBIF_CFG_DEV0_EPF0_VF25_0_ADAPTER_ID 0x002c #define cfgBIF_CFG_DEV0_EPF0_VF25_0_ROM_BASE_ADDR 0x0030 #define cfgBIF_CFG_DEV0_EPF0_VF25_0_CAP_PTR 0x0034 #define cfgBIF_CFG_DEV0_EPF0_VF25_0_INTERRUPT_LINE 0x003c #define cfgBIF_CFG_DEV0_EPF0_VF25_0_INTERRUPT_PIN 0x003d #define cfgBIF_CFG_DEV0_EPF0_VF25_0_MIN_GRANT 0x003e #define cfgBIF_CFG_DEV0_EPF0_VF25_0_MAX_LATENCY 0x003f #define cfgBIF_CFG_DEV0_EPF0_VF25_0_PCIE_CAP_LIST 0x0064 #define cfgBIF_CFG_DEV0_EPF0_VF25_0_PCIE_CAP 0x0066 #define cfgBIF_CFG_DEV0_EPF0_VF25_0_DEVICE_CAP 0x0068 #define cfgBIF_CFG_DEV0_EPF0_VF25_0_DEVICE_CNTL 0x006c #define cfgBIF_CFG_DEV0_EPF0_VF25_0_DEVICE_STATUS 0x006e #define cfgBIF_CFG_DEV0_EPF0_VF25_0_LINK_CAP 0x0070 #define cfgBIF_CFG_DEV0_EPF0_VF25_0_LINK_CNTL 0x0074 #define cfgBIF_CFG_DEV0_EPF0_VF25_0_LINK_STATUS 0x0076 #define cfgBIF_CFG_DEV0_EPF0_VF25_0_DEVICE_CAP2 0x0088 #define cfgBIF_CFG_DEV0_EPF0_VF25_0_DEVICE_CNTL2 0x008c #define cfgBIF_CFG_DEV0_EPF0_VF25_0_DEVICE_STATUS2 0x008e #define cfgBIF_CFG_DEV0_EPF0_VF25_0_LINK_CAP2 0x0090 #define cfgBIF_CFG_DEV0_EPF0_VF25_0_LINK_CNTL2 0x0094 #define cfgBIF_CFG_DEV0_EPF0_VF25_0_LINK_STATUS2 0x0096 #define cfgBIF_CFG_DEV0_EPF0_VF25_0_MSI_CAP_LIST 0x00a0 #define cfgBIF_CFG_DEV0_EPF0_VF25_0_MSI_MSG_CNTL 0x00a2 #define cfgBIF_CFG_DEV0_EPF0_VF25_0_MSI_MSG_ADDR_LO 0x00a4 #define cfgBIF_CFG_DEV0_EPF0_VF25_0_MSI_MSG_ADDR_HI 0x00a8 #define cfgBIF_CFG_DEV0_EPF0_VF25_0_MSI_MSG_DATA 0x00a8 #define cfgBIF_CFG_DEV0_EPF0_VF25_0_MSI_MASK 0x00ac #define cfgBIF_CFG_DEV0_EPF0_VF25_0_MSI_MSG_DATA_64 0x00ac #define cfgBIF_CFG_DEV0_EPF0_VF25_0_MSI_MASK_64 0x00b0 #define cfgBIF_CFG_DEV0_EPF0_VF25_0_MSI_PENDING 0x00b0 #define cfgBIF_CFG_DEV0_EPF0_VF25_0_MSI_PENDING_64 0x00b4 #define cfgBIF_CFG_DEV0_EPF0_VF25_0_MSIX_CAP_LIST 0x00c0 #define cfgBIF_CFG_DEV0_EPF0_VF25_0_MSIX_MSG_CNTL 0x00c2 #define cfgBIF_CFG_DEV0_EPF0_VF25_0_MSIX_TABLE 0x00c4 #define cfgBIF_CFG_DEV0_EPF0_VF25_0_MSIX_PBA 0x00c8 #define cfgBIF_CFG_DEV0_EPF0_VF25_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x0100 #define cfgBIF_CFG_DEV0_EPF0_VF25_0_PCIE_VENDOR_SPECIFIC_HDR 0x0104 #define cfgBIF_CFG_DEV0_EPF0_VF25_0_PCIE_VENDOR_SPECIFIC1 0x0108 #define cfgBIF_CFG_DEV0_EPF0_VF25_0_PCIE_VENDOR_SPECIFIC2 0x010c #define cfgBIF_CFG_DEV0_EPF0_VF25_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x0150 #define cfgBIF_CFG_DEV0_EPF0_VF25_0_PCIE_UNCORR_ERR_STATUS 0x0154 #define cfgBIF_CFG_DEV0_EPF0_VF25_0_PCIE_UNCORR_ERR_MASK 0x0158 #define cfgBIF_CFG_DEV0_EPF0_VF25_0_PCIE_UNCORR_ERR_SEVERITY 0x015c #define cfgBIF_CFG_DEV0_EPF0_VF25_0_PCIE_CORR_ERR_STATUS 0x0160 #define cfgBIF_CFG_DEV0_EPF0_VF25_0_PCIE_CORR_ERR_MASK 0x0164 #define cfgBIF_CFG_DEV0_EPF0_VF25_0_PCIE_ADV_ERR_CAP_CNTL 0x0168 #define cfgBIF_CFG_DEV0_EPF0_VF25_0_PCIE_HDR_LOG0 0x016c #define cfgBIF_CFG_DEV0_EPF0_VF25_0_PCIE_HDR_LOG1 0x0170 #define cfgBIF_CFG_DEV0_EPF0_VF25_0_PCIE_HDR_LOG2 0x0174 #define cfgBIF_CFG_DEV0_EPF0_VF25_0_PCIE_HDR_LOG3 0x0178 #define cfgBIF_CFG_DEV0_EPF0_VF25_0_PCIE_TLP_PREFIX_LOG0 0x0188 #define cfgBIF_CFG_DEV0_EPF0_VF25_0_PCIE_TLP_PREFIX_LOG1 0x018c #define cfgBIF_CFG_DEV0_EPF0_VF25_0_PCIE_TLP_PREFIX_LOG2 0x0190 #define cfgBIF_CFG_DEV0_EPF0_VF25_0_PCIE_TLP_PREFIX_LOG3 0x0194 #define cfgBIF_CFG_DEV0_EPF0_VF25_0_PCIE_ATS_ENH_CAP_LIST 0x02b0 #define cfgBIF_CFG_DEV0_EPF0_VF25_0_PCIE_ATS_CAP 0x02b4 #define cfgBIF_CFG_DEV0_EPF0_VF25_0_PCIE_ATS_CNTL 0x02b6 #define cfgBIF_CFG_DEV0_EPF0_VF25_0_PCIE_ARI_ENH_CAP_LIST 0x0328 #define cfgBIF_CFG_DEV0_EPF0_VF25_0_PCIE_ARI_CAP 0x032c #define cfgBIF_CFG_DEV0_EPF0_VF25_0_PCIE_ARI_CNTL 0x032e // addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf26_bifcfgdecp // base address: 0x0 #define cfgBIF_CFG_DEV0_EPF0_VF26_0_VENDOR_ID 0x0000 #define cfgBIF_CFG_DEV0_EPF0_VF26_0_DEVICE_ID 0x0002 #define cfgBIF_CFG_DEV0_EPF0_VF26_0_COMMAND 0x0004 #define cfgBIF_CFG_DEV0_EPF0_VF26_0_STATUS 0x0006 #define cfgBIF_CFG_DEV0_EPF0_VF26_0_REVISION_ID 0x0008 #define cfgBIF_CFG_DEV0_EPF0_VF26_0_PROG_INTERFACE 0x0009 #define cfgBIF_CFG_DEV0_EPF0_VF26_0_SUB_CLASS 0x000a #define cfgBIF_CFG_DEV0_EPF0_VF26_0_BASE_CLASS 0x000b #define cfgBIF_CFG_DEV0_EPF0_VF26_0_CACHE_LINE 0x000c #define cfgBIF_CFG_DEV0_EPF0_VF26_0_LATENCY 0x000d #define cfgBIF_CFG_DEV0_EPF0_VF26_0_HEADER 0x000e #define cfgBIF_CFG_DEV0_EPF0_VF26_0_BIST 0x000f #define cfgBIF_CFG_DEV0_EPF0_VF26_0_BASE_ADDR_1 0x0010 #define cfgBIF_CFG_DEV0_EPF0_VF26_0_BASE_ADDR_2 0x0014 #define cfgBIF_CFG_DEV0_EPF0_VF26_0_BASE_ADDR_3 0x0018 #define cfgBIF_CFG_DEV0_EPF0_VF26_0_BASE_ADDR_4 0x001c #define cfgBIF_CFG_DEV0_EPF0_VF26_0_BASE_ADDR_5 0x0020 #define cfgBIF_CFG_DEV0_EPF0_VF26_0_BASE_ADDR_6 0x0024 #define cfgBIF_CFG_DEV0_EPF0_VF26_0_CARDBUS_CIS_PTR 0x0028 #define cfgBIF_CFG_DEV0_EPF0_VF26_0_ADAPTER_ID 0x002c #define cfgBIF_CFG_DEV0_EPF0_VF26_0_ROM_BASE_ADDR 0x0030 #define cfgBIF_CFG_DEV0_EPF0_VF26_0_CAP_PTR 0x0034 #define cfgBIF_CFG_DEV0_EPF0_VF26_0_INTERRUPT_LINE 0x003c #define cfgBIF_CFG_DEV0_EPF0_VF26_0_INTERRUPT_PIN 0x003d #define cfgBIF_CFG_DEV0_EPF0_VF26_0_MIN_GRANT 0x003e #define cfgBIF_CFG_DEV0_EPF0_VF26_0_MAX_LATENCY 0x003f #define cfgBIF_CFG_DEV0_EPF0_VF26_0_PCIE_CAP_LIST 0x0064 #define cfgBIF_CFG_DEV0_EPF0_VF26_0_PCIE_CAP 0x0066 #define cfgBIF_CFG_DEV0_EPF0_VF26_0_DEVICE_CAP 0x0068 #define cfgBIF_CFG_DEV0_EPF0_VF26_0_DEVICE_CNTL 0x006c #define cfgBIF_CFG_DEV0_EPF0_VF26_0_DEVICE_STATUS 0x006e #define cfgBIF_CFG_DEV0_EPF0_VF26_0_LINK_CAP 0x0070 #define cfgBIF_CFG_DEV0_EPF0_VF26_0_LINK_CNTL 0x0074 #define cfgBIF_CFG_DEV0_EPF0_VF26_0_LINK_STATUS 0x0076 #define cfgBIF_CFG_DEV0_EPF0_VF26_0_DEVICE_CAP2 0x0088 #define cfgBIF_CFG_DEV0_EPF0_VF26_0_DEVICE_CNTL2 0x008c #define cfgBIF_CFG_DEV0_EPF0_VF26_0_DEVICE_STATUS2 0x008e #define cfgBIF_CFG_DEV0_EPF0_VF26_0_LINK_CAP2 0x0090 #define cfgBIF_CFG_DEV0_EPF0_VF26_0_LINK_CNTL2 0x0094 #define cfgBIF_CFG_DEV0_EPF0_VF26_0_LINK_STATUS2 0x0096 #define cfgBIF_CFG_DEV0_EPF0_VF26_0_MSI_CAP_LIST 0x00a0 #define cfgBIF_CFG_DEV0_EPF0_VF26_0_MSI_MSG_CNTL 0x00a2 #define cfgBIF_CFG_DEV0_EPF0_VF26_0_MSI_MSG_ADDR_LO 0x00a4 #define cfgBIF_CFG_DEV0_EPF0_VF26_0_MSI_MSG_ADDR_HI 0x00a8 #define cfgBIF_CFG_DEV0_EPF0_VF26_0_MSI_MSG_DATA 0x00a8 #define cfgBIF_CFG_DEV0_EPF0_VF26_0_MSI_MASK 0x00ac #define cfgBIF_CFG_DEV0_EPF0_VF26_0_MSI_MSG_DATA_64 0x00ac #define cfgBIF_CFG_DEV0_EPF0_VF26_0_MSI_MASK_64 0x00b0 #define cfgBIF_CFG_DEV0_EPF0_VF26_0_MSI_PENDING 0x00b0 #define cfgBIF_CFG_DEV0_EPF0_VF26_0_MSI_PENDING_64 0x00b4 #define cfgBIF_CFG_DEV0_EPF0_VF26_0_MSIX_CAP_LIST 0x00c0 #define cfgBIF_CFG_DEV0_EPF0_VF26_0_MSIX_MSG_CNTL 0x00c2 #define cfgBIF_CFG_DEV0_EPF0_VF26_0_MSIX_TABLE 0x00c4 #define cfgBIF_CFG_DEV0_EPF0_VF26_0_MSIX_PBA 0x00c8 #define cfgBIF_CFG_DEV0_EPF0_VF26_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x0100 #define cfgBIF_CFG_DEV0_EPF0_VF26_0_PCIE_VENDOR_SPECIFIC_HDR 0x0104 #define cfgBIF_CFG_DEV0_EPF0_VF26_0_PCIE_VENDOR_SPECIFIC1 0x0108 #define cfgBIF_CFG_DEV0_EPF0_VF26_0_PCIE_VENDOR_SPECIFIC2 0x010c #define cfgBIF_CFG_DEV0_EPF0_VF26_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x0150 #define cfgBIF_CFG_DEV0_EPF0_VF26_0_PCIE_UNCORR_ERR_STATUS 0x0154 #define cfgBIF_CFG_DEV0_EPF0_VF26_0_PCIE_UNCORR_ERR_MASK 0x0158 #define cfgBIF_CFG_DEV0_EPF0_VF26_0_PCIE_UNCORR_ERR_SEVERITY 0x015c #define cfgBIF_CFG_DEV0_EPF0_VF26_0_PCIE_CORR_ERR_STATUS 0x0160 #define cfgBIF_CFG_DEV0_EPF0_VF26_0_PCIE_CORR_ERR_MASK 0x0164 #define cfgBIF_CFG_DEV0_EPF0_VF26_0_PCIE_ADV_ERR_CAP_CNTL 0x0168 #define cfgBIF_CFG_DEV0_EPF0_VF26_0_PCIE_HDR_LOG0 0x016c #define cfgBIF_CFG_DEV0_EPF0_VF26_0_PCIE_HDR_LOG1 0x0170 #define cfgBIF_CFG_DEV0_EPF0_VF26_0_PCIE_HDR_LOG2 0x0174 #define cfgBIF_CFG_DEV0_EPF0_VF26_0_PCIE_HDR_LOG3 0x0178 #define cfgBIF_CFG_DEV0_EPF0_VF26_0_PCIE_TLP_PREFIX_LOG0 0x0188 #define cfgBIF_CFG_DEV0_EPF0_VF26_0_PCIE_TLP_PREFIX_LOG1 0x018c #define cfgBIF_CFG_DEV0_EPF0_VF26_0_PCIE_TLP_PREFIX_LOG2 0x0190 #define cfgBIF_CFG_DEV0_EPF0_VF26_0_PCIE_TLP_PREFIX_LOG3 0x0194 #define cfgBIF_CFG_DEV0_EPF0_VF26_0_PCIE_ATS_ENH_CAP_LIST 0x02b0 #define cfgBIF_CFG_DEV0_EPF0_VF26_0_PCIE_ATS_CAP 0x02b4 #define cfgBIF_CFG_DEV0_EPF0_VF26_0_PCIE_ATS_CNTL 0x02b6 #define cfgBIF_CFG_DEV0_EPF0_VF26_0_PCIE_ARI_ENH_CAP_LIST 0x0328 #define cfgBIF_CFG_DEV0_EPF0_VF26_0_PCIE_ARI_CAP 0x032c #define cfgBIF_CFG_DEV0_EPF0_VF26_0_PCIE_ARI_CNTL 0x032e // addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf27_bifcfgdecp // base address: 0x0 #define cfgBIF_CFG_DEV0_EPF0_VF27_0_VENDOR_ID 0x0000 #define cfgBIF_CFG_DEV0_EPF0_VF27_0_DEVICE_ID 0x0002 #define cfgBIF_CFG_DEV0_EPF0_VF27_0_COMMAND 0x0004 #define cfgBIF_CFG_DEV0_EPF0_VF27_0_STATUS 0x0006 #define cfgBIF_CFG_DEV0_EPF0_VF27_0_REVISION_ID 0x0008 #define cfgBIF_CFG_DEV0_EPF0_VF27_0_PROG_INTERFACE 0x0009 #define cfgBIF_CFG_DEV0_EPF0_VF27_0_SUB_CLASS 0x000a #define cfgBIF_CFG_DEV0_EPF0_VF27_0_BASE_CLASS 0x000b #define cfgBIF_CFG_DEV0_EPF0_VF27_0_CACHE_LINE 0x000c #define cfgBIF_CFG_DEV0_EPF0_VF27_0_LATENCY 0x000d #define cfgBIF_CFG_DEV0_EPF0_VF27_0_HEADER 0x000e #define cfgBIF_CFG_DEV0_EPF0_VF27_0_BIST 0x000f #define cfgBIF_CFG_DEV0_EPF0_VF27_0_BASE_ADDR_1 0x0010 #define cfgBIF_CFG_DEV0_EPF0_VF27_0_BASE_ADDR_2 0x0014 #define cfgBIF_CFG_DEV0_EPF0_VF27_0_BASE_ADDR_3 0x0018 #define cfgBIF_CFG_DEV0_EPF0_VF27_0_BASE_ADDR_4 0x001c #define cfgBIF_CFG_DEV0_EPF0_VF27_0_BASE_ADDR_5 0x0020 #define cfgBIF_CFG_DEV0_EPF0_VF27_0_BASE_ADDR_6 0x0024 #define cfgBIF_CFG_DEV0_EPF0_VF27_0_CARDBUS_CIS_PTR 0x0028 #define cfgBIF_CFG_DEV0_EPF0_VF27_0_ADAPTER_ID 0x002c #define cfgBIF_CFG_DEV0_EPF0_VF27_0_ROM_BASE_ADDR 0x0030 #define cfgBIF_CFG_DEV0_EPF0_VF27_0_CAP_PTR 0x0034 #define cfgBIF_CFG_DEV0_EPF0_VF27_0_INTERRUPT_LINE 0x003c #define cfgBIF_CFG_DEV0_EPF0_VF27_0_INTERRUPT_PIN 0x003d #define cfgBIF_CFG_DEV0_EPF0_VF27_0_MIN_GRANT 0x003e #define cfgBIF_CFG_DEV0_EPF0_VF27_0_MAX_LATENCY 0x003f #define cfgBIF_CFG_DEV0_EPF0_VF27_0_PCIE_CAP_LIST 0x0064 #define cfgBIF_CFG_DEV0_EPF0_VF27_0_PCIE_CAP 0x0066 #define cfgBIF_CFG_DEV0_EPF0_VF27_0_DEVICE_CAP 0x0068 #define cfgBIF_CFG_DEV0_EPF0_VF27_0_DEVICE_CNTL 0x006c #define cfgBIF_CFG_DEV0_EPF0_VF27_0_DEVICE_STATUS 0x006e #define cfgBIF_CFG_DEV0_EPF0_VF27_0_LINK_CAP 0x0070 #define cfgBIF_CFG_DEV0_EPF0_VF27_0_LINK_CNTL 0x0074 #define cfgBIF_CFG_DEV0_EPF0_VF27_0_LINK_STATUS 0x0076 #define cfgBIF_CFG_DEV0_EPF0_VF27_0_DEVICE_CAP2 0x0088 #define cfgBIF_CFG_DEV0_EPF0_VF27_0_DEVICE_CNTL2 0x008c #define cfgBIF_CFG_DEV0_EPF0_VF27_0_DEVICE_STATUS2 0x008e #define cfgBIF_CFG_DEV0_EPF0_VF27_0_LINK_CAP2 0x0090 #define cfgBIF_CFG_DEV0_EPF0_VF27_0_LINK_CNTL2 0x0094 #define cfgBIF_CFG_DEV0_EPF0_VF27_0_LINK_STATUS2 0x0096 #define cfgBIF_CFG_DEV0_EPF0_VF27_0_MSI_CAP_LIST 0x00a0 #define cfgBIF_CFG_DEV0_EPF0_VF27_0_MSI_MSG_CNTL 0x00a2 #define cfgBIF_CFG_DEV0_EPF0_VF27_0_MSI_MSG_ADDR_LO 0x00a4 #define cfgBIF_CFG_DEV0_EPF0_VF27_0_MSI_MSG_ADDR_HI 0x00a8 #define cfgBIF_CFG_DEV0_EPF0_VF27_0_MSI_MSG_DATA 0x00a8 #define cfgBIF_CFG_DEV0_EPF0_VF27_0_MSI_MASK 0x00ac #define cfgBIF_CFG_DEV0_EPF0_VF27_0_MSI_MSG_DATA_64 0x00ac #define cfgBIF_CFG_DEV0_EPF0_VF27_0_MSI_MASK_64 0x00b0 #define cfgBIF_CFG_DEV0_EPF0_VF27_0_MSI_PENDING 0x00b0 #define cfgBIF_CFG_DEV0_EPF0_VF27_0_MSI_PENDING_64 0x00b4 #define cfgBIF_CFG_DEV0_EPF0_VF27_0_MSIX_CAP_LIST 0x00c0 #define cfgBIF_CFG_DEV0_EPF0_VF27_0_MSIX_MSG_CNTL 0x00c2 #define cfgBIF_CFG_DEV0_EPF0_VF27_0_MSIX_TABLE 0x00c4 #define cfgBIF_CFG_DEV0_EPF0_VF27_0_MSIX_PBA 0x00c8 #define cfgBIF_CFG_DEV0_EPF0_VF27_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x0100 #define cfgBIF_CFG_DEV0_EPF0_VF27_0_PCIE_VENDOR_SPECIFIC_HDR 0x0104 #define cfgBIF_CFG_DEV0_EPF0_VF27_0_PCIE_VENDOR_SPECIFIC1 0x0108 #define cfgBIF_CFG_DEV0_EPF0_VF27_0_PCIE_VENDOR_SPECIFIC2 0x010c #define cfgBIF_CFG_DEV0_EPF0_VF27_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x0150 #define cfgBIF_CFG_DEV0_EPF0_VF27_0_PCIE_UNCORR_ERR_STATUS 0x0154 #define cfgBIF_CFG_DEV0_EPF0_VF27_0_PCIE_UNCORR_ERR_MASK 0x0158 #define cfgBIF_CFG_DEV0_EPF0_VF27_0_PCIE_UNCORR_ERR_SEVERITY 0x015c #define cfgBIF_CFG_DEV0_EPF0_VF27_0_PCIE_CORR_ERR_STATUS 0x0160 #define cfgBIF_CFG_DEV0_EPF0_VF27_0_PCIE_CORR_ERR_MASK 0x0164 #define cfgBIF_CFG_DEV0_EPF0_VF27_0_PCIE_ADV_ERR_CAP_CNTL 0x0168 #define cfgBIF_CFG_DEV0_EPF0_VF27_0_PCIE_HDR_LOG0 0x016c #define cfgBIF_CFG_DEV0_EPF0_VF27_0_PCIE_HDR_LOG1 0x0170 #define cfgBIF_CFG_DEV0_EPF0_VF27_0_PCIE_HDR_LOG2 0x0174 #define cfgBIF_CFG_DEV0_EPF0_VF27_0_PCIE_HDR_LOG3 0x0178 #define cfgBIF_CFG_DEV0_EPF0_VF27_0_PCIE_TLP_PREFIX_LOG0 0x0188 #define cfgBIF_CFG_DEV0_EPF0_VF27_0_PCIE_TLP_PREFIX_LOG1 0x018c #define cfgBIF_CFG_DEV0_EPF0_VF27_0_PCIE_TLP_PREFIX_LOG2 0x0190 #define cfgBIF_CFG_DEV0_EPF0_VF27_0_PCIE_TLP_PREFIX_LOG3 0x0194 #define cfgBIF_CFG_DEV0_EPF0_VF27_0_PCIE_ATS_ENH_CAP_LIST 0x02b0 #define cfgBIF_CFG_DEV0_EPF0_VF27_0_PCIE_ATS_CAP 0x02b4 #define cfgBIF_CFG_DEV0_EPF0_VF27_0_PCIE_ATS_CNTL 0x02b6 #define cfgBIF_CFG_DEV0_EPF0_VF27_0_PCIE_ARI_ENH_CAP_LIST 0x0328 #define cfgBIF_CFG_DEV0_EPF0_VF27_0_PCIE_ARI_CAP 0x032c #define cfgBIF_CFG_DEV0_EPF0_VF27_0_PCIE_ARI_CNTL 0x032e // addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf28_bifcfgdecp // base address: 0x0 #define cfgBIF_CFG_DEV0_EPF0_VF28_0_VENDOR_ID 0x0000 #define cfgBIF_CFG_DEV0_EPF0_VF28_0_DEVICE_ID 0x0002 #define cfgBIF_CFG_DEV0_EPF0_VF28_0_COMMAND 0x0004 #define cfgBIF_CFG_DEV0_EPF0_VF28_0_STATUS 0x0006 #define cfgBIF_CFG_DEV0_EPF0_VF28_0_REVISION_ID 0x0008 #define cfgBIF_CFG_DEV0_EPF0_VF28_0_PROG_INTERFACE 0x0009 #define cfgBIF_CFG_DEV0_EPF0_VF28_0_SUB_CLASS 0x000a #define cfgBIF_CFG_DEV0_EPF0_VF28_0_BASE_CLASS 0x000b #define cfgBIF_CFG_DEV0_EPF0_VF28_0_CACHE_LINE 0x000c #define cfgBIF_CFG_DEV0_EPF0_VF28_0_LATENCY 0x000d #define cfgBIF_CFG_DEV0_EPF0_VF28_0_HEADER 0x000e #define cfgBIF_CFG_DEV0_EPF0_VF28_0_BIST 0x000f #define cfgBIF_CFG_DEV0_EPF0_VF28_0_BASE_ADDR_1 0x0010 #define cfgBIF_CFG_DEV0_EPF0_VF28_0_BASE_ADDR_2 0x0014 #define cfgBIF_CFG_DEV0_EPF0_VF28_0_BASE_ADDR_3 0x0018 #define cfgBIF_CFG_DEV0_EPF0_VF28_0_BASE_ADDR_4 0x001c #define cfgBIF_CFG_DEV0_EPF0_VF28_0_BASE_ADDR_5 0x0020 #define cfgBIF_CFG_DEV0_EPF0_VF28_0_BASE_ADDR_6 0x0024 #define cfgBIF_CFG_DEV0_EPF0_VF28_0_CARDBUS_CIS_PTR 0x0028 #define cfgBIF_CFG_DEV0_EPF0_VF28_0_ADAPTER_ID 0x002c #define cfgBIF_CFG_DEV0_EPF0_VF28_0_ROM_BASE_ADDR 0x0030 #define cfgBIF_CFG_DEV0_EPF0_VF28_0_CAP_PTR 0x0034 #define cfgBIF_CFG_DEV0_EPF0_VF28_0_INTERRUPT_LINE 0x003c #define cfgBIF_CFG_DEV0_EPF0_VF28_0_INTERRUPT_PIN 0x003d #define cfgBIF_CFG_DEV0_EPF0_VF28_0_MIN_GRANT 0x003e #define cfgBIF_CFG_DEV0_EPF0_VF28_0_MAX_LATENCY 0x003f #define cfgBIF_CFG_DEV0_EPF0_VF28_0_PCIE_CAP_LIST 0x0064 #define cfgBIF_CFG_DEV0_EPF0_VF28_0_PCIE_CAP 0x0066 #define cfgBIF_CFG_DEV0_EPF0_VF28_0_DEVICE_CAP 0x0068 #define cfgBIF_CFG_DEV0_EPF0_VF28_0_DEVICE_CNTL 0x006c #define cfgBIF_CFG_DEV0_EPF0_VF28_0_DEVICE_STATUS 0x006e #define cfgBIF_CFG_DEV0_EPF0_VF28_0_LINK_CAP 0x0070 #define cfgBIF_CFG_DEV0_EPF0_VF28_0_LINK_CNTL 0x0074 #define cfgBIF_CFG_DEV0_EPF0_VF28_0_LINK_STATUS 0x0076 #define cfgBIF_CFG_DEV0_EPF0_VF28_0_DEVICE_CAP2 0x0088 #define cfgBIF_CFG_DEV0_EPF0_VF28_0_DEVICE_CNTL2 0x008c #define cfgBIF_CFG_DEV0_EPF0_VF28_0_DEVICE_STATUS2 0x008e #define cfgBIF_CFG_DEV0_EPF0_VF28_0_LINK_CAP2 0x0090 #define cfgBIF_CFG_DEV0_EPF0_VF28_0_LINK_CNTL2 0x0094 #define cfgBIF_CFG_DEV0_EPF0_VF28_0_LINK_STATUS2 0x0096 #define cfgBIF_CFG_DEV0_EPF0_VF28_0_MSI_CAP_LIST 0x00a0 #define cfgBIF_CFG_DEV0_EPF0_VF28_0_MSI_MSG_CNTL 0x00a2 #define cfgBIF_CFG_DEV0_EPF0_VF28_0_MSI_MSG_ADDR_LO 0x00a4 #define cfgBIF_CFG_DEV0_EPF0_VF28_0_MSI_MSG_ADDR_HI 0x00a8 #define cfgBIF_CFG_DEV0_EPF0_VF28_0_MSI_MSG_DATA 0x00a8 #define cfgBIF_CFG_DEV0_EPF0_VF28_0_MSI_MASK 0x00ac #define cfgBIF_CFG_DEV0_EPF0_VF28_0_MSI_MSG_DATA_64 0x00ac #define cfgBIF_CFG_DEV0_EPF0_VF28_0_MSI_MASK_64 0x00b0 #define cfgBIF_CFG_DEV0_EPF0_VF28_0_MSI_PENDING 0x00b0 #define cfgBIF_CFG_DEV0_EPF0_VF28_0_MSI_PENDING_64 0x00b4 #define cfgBIF_CFG_DEV0_EPF0_VF28_0_MSIX_CAP_LIST 0x00c0 #define cfgBIF_CFG_DEV0_EPF0_VF28_0_MSIX_MSG_CNTL 0x00c2 #define cfgBIF_CFG_DEV0_EPF0_VF28_0_MSIX_TABLE 0x00c4 #define cfgBIF_CFG_DEV0_EPF0_VF28_0_MSIX_PBA 0x00c8 #define cfgBIF_CFG_DEV0_EPF0_VF28_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x0100 #define cfgBIF_CFG_DEV0_EPF0_VF28_0_PCIE_VENDOR_SPECIFIC_HDR 0x0104 #define cfgBIF_CFG_DEV0_EPF0_VF28_0_PCIE_VENDOR_SPECIFIC1 0x0108 #define cfgBIF_CFG_DEV0_EPF0_VF28_0_PCIE_VENDOR_SPECIFIC2 0x010c #define cfgBIF_CFG_DEV0_EPF0_VF28_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x0150 #define cfgBIF_CFG_DEV0_EPF0_VF28_0_PCIE_UNCORR_ERR_STATUS 0x0154 #define cfgBIF_CFG_DEV0_EPF0_VF28_0_PCIE_UNCORR_ERR_MASK 0x0158 #define cfgBIF_CFG_DEV0_EPF0_VF28_0_PCIE_UNCORR_ERR_SEVERITY 0x015c #define cfgBIF_CFG_DEV0_EPF0_VF28_0_PCIE_CORR_ERR_STATUS 0x0160 #define cfgBIF_CFG_DEV0_EPF0_VF28_0_PCIE_CORR_ERR_MASK 0x0164 #define cfgBIF_CFG_DEV0_EPF0_VF28_0_PCIE_ADV_ERR_CAP_CNTL 0x0168 #define cfgBIF_CFG_DEV0_EPF0_VF28_0_PCIE_HDR_LOG0 0x016c #define cfgBIF_CFG_DEV0_EPF0_VF28_0_PCIE_HDR_LOG1 0x0170 #define cfgBIF_CFG_DEV0_EPF0_VF28_0_PCIE_HDR_LOG2 0x0174 #define cfgBIF_CFG_DEV0_EPF0_VF28_0_PCIE_HDR_LOG3 0x0178 #define cfgBIF_CFG_DEV0_EPF0_VF28_0_PCIE_TLP_PREFIX_LOG0 0x0188 #define cfgBIF_CFG_DEV0_EPF0_VF28_0_PCIE_TLP_PREFIX_LOG1 0x018c #define cfgBIF_CFG_DEV0_EPF0_VF28_0_PCIE_TLP_PREFIX_LOG2 0x0190 #define cfgBIF_CFG_DEV0_EPF0_VF28_0_PCIE_TLP_PREFIX_LOG3 0x0194 #define cfgBIF_CFG_DEV0_EPF0_VF28_0_PCIE_ATS_ENH_CAP_LIST 0x02b0 #define cfgBIF_CFG_DEV0_EPF0_VF28_0_PCIE_ATS_CAP 0x02b4 #define cfgBIF_CFG_DEV0_EPF0_VF28_0_PCIE_ATS_CNTL 0x02b6 #define cfgBIF_CFG_DEV0_EPF0_VF28_0_PCIE_ARI_ENH_CAP_LIST 0x0328 #define cfgBIF_CFG_DEV0_EPF0_VF28_0_PCIE_ARI_CAP 0x032c #define cfgBIF_CFG_DEV0_EPF0_VF28_0_PCIE_ARI_CNTL 0x032e // addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf29_bifcfgdecp // base address: 0x0 #define cfgBIF_CFG_DEV0_EPF0_VF29_0_VENDOR_ID 0x0000 #define cfgBIF_CFG_DEV0_EPF0_VF29_0_DEVICE_ID 0x0002 #define cfgBIF_CFG_DEV0_EPF0_VF29_0_COMMAND 0x0004 #define cfgBIF_CFG_DEV0_EPF0_VF29_0_STATUS 0x0006 #define cfgBIF_CFG_DEV0_EPF0_VF29_0_REVISION_ID 0x0008 #define cfgBIF_CFG_DEV0_EPF0_VF29_0_PROG_INTERFACE 0x0009 #define cfgBIF_CFG_DEV0_EPF0_VF29_0_SUB_CLASS 0x000a #define cfgBIF_CFG_DEV0_EPF0_VF29_0_BASE_CLASS 0x000b #define cfgBIF_CFG_DEV0_EPF0_VF29_0_CACHE_LINE 0x000c #define cfgBIF_CFG_DEV0_EPF0_VF29_0_LATENCY 0x000d #define cfgBIF_CFG_DEV0_EPF0_VF29_0_HEADER 0x000e #define cfgBIF_CFG_DEV0_EPF0_VF29_0_BIST 0x000f #define cfgBIF_CFG_DEV0_EPF0_VF29_0_BASE_ADDR_1 0x0010 #define cfgBIF_CFG_DEV0_EPF0_VF29_0_BASE_ADDR_2 0x0014 #define cfgBIF_CFG_DEV0_EPF0_VF29_0_BASE_ADDR_3 0x0018 #define cfgBIF_CFG_DEV0_EPF0_VF29_0_BASE_ADDR_4 0x001c #define cfgBIF_CFG_DEV0_EPF0_VF29_0_BASE_ADDR_5 0x0020 #define cfgBIF_CFG_DEV0_EPF0_VF29_0_BASE_ADDR_6 0x0024 #define cfgBIF_CFG_DEV0_EPF0_VF29_0_CARDBUS_CIS_PTR 0x0028 #define cfgBIF_CFG_DEV0_EPF0_VF29_0_ADAPTER_ID 0x002c #define cfgBIF_CFG_DEV0_EPF0_VF29_0_ROM_BASE_ADDR 0x0030 #define cfgBIF_CFG_DEV0_EPF0_VF29_0_CAP_PTR 0x0034 #define cfgBIF_CFG_DEV0_EPF0_VF29_0_INTERRUPT_LINE 0x003c #define cfgBIF_CFG_DEV0_EPF0_VF29_0_INTERRUPT_PIN 0x003d #define cfgBIF_CFG_DEV0_EPF0_VF29_0_MIN_GRANT 0x003e #define cfgBIF_CFG_DEV0_EPF0_VF29_0_MAX_LATENCY 0x003f #define cfgBIF_CFG_DEV0_EPF0_VF29_0_PCIE_CAP_LIST 0x0064 #define cfgBIF_CFG_DEV0_EPF0_VF29_0_PCIE_CAP 0x0066 #define cfgBIF_CFG_DEV0_EPF0_VF29_0_DEVICE_CAP 0x0068 #define cfgBIF_CFG_DEV0_EPF0_VF29_0_DEVICE_CNTL 0x006c #define cfgBIF_CFG_DEV0_EPF0_VF29_0_DEVICE_STATUS 0x006e #define cfgBIF_CFG_DEV0_EPF0_VF29_0_LINK_CAP 0x0070 #define cfgBIF_CFG_DEV0_EPF0_VF29_0_LINK_CNTL 0x0074 #define cfgBIF_CFG_DEV0_EPF0_VF29_0_LINK_STATUS 0x0076 #define cfgBIF_CFG_DEV0_EPF0_VF29_0_DEVICE_CAP2 0x0088 #define cfgBIF_CFG_DEV0_EPF0_VF29_0_DEVICE_CNTL2 0x008c #define cfgBIF_CFG_DEV0_EPF0_VF29_0_DEVICE_STATUS2 0x008e #define cfgBIF_CFG_DEV0_EPF0_VF29_0_LINK_CAP2 0x0090 #define cfgBIF_CFG_DEV0_EPF0_VF29_0_LINK_CNTL2 0x0094 #define cfgBIF_CFG_DEV0_EPF0_VF29_0_LINK_STATUS2 0x0096 #define cfgBIF_CFG_DEV0_EPF0_VF29_0_MSI_CAP_LIST 0x00a0 #define cfgBIF_CFG_DEV0_EPF0_VF29_0_MSI_MSG_CNTL 0x00a2 #define cfgBIF_CFG_DEV0_EPF0_VF29_0_MSI_MSG_ADDR_LO 0x00a4 #define cfgBIF_CFG_DEV0_EPF0_VF29_0_MSI_MSG_ADDR_HI 0x00a8 #define cfgBIF_CFG_DEV0_EPF0_VF29_0_MSI_MSG_DATA 0x00a8 #define cfgBIF_CFG_DEV0_EPF0_VF29_0_MSI_MASK 0x00ac #define cfgBIF_CFG_DEV0_EPF0_VF29_0_MSI_MSG_DATA_64 0x00ac #define cfgBIF_CFG_DEV0_EPF0_VF29_0_MSI_MASK_64 0x00b0 #define cfgBIF_CFG_DEV0_EPF0_VF29_0_MSI_PENDING 0x00b0 #define cfgBIF_CFG_DEV0_EPF0_VF29_0_MSI_PENDING_64 0x00b4 #define cfgBIF_CFG_DEV0_EPF0_VF29_0_MSIX_CAP_LIST 0x00c0 #define cfgBIF_CFG_DEV0_EPF0_VF29_0_MSIX_MSG_CNTL 0x00c2 #define cfgBIF_CFG_DEV0_EPF0_VF29_0_MSIX_TABLE 0x00c4 #define cfgBIF_CFG_DEV0_EPF0_VF29_0_MSIX_PBA 0x00c8 #define cfgBIF_CFG_DEV0_EPF0_VF29_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x0100 #define cfgBIF_CFG_DEV0_EPF0_VF29_0_PCIE_VENDOR_SPECIFIC_HDR 0x0104 #define cfgBIF_CFG_DEV0_EPF0_VF29_0_PCIE_VENDOR_SPECIFIC1 0x0108 #define cfgBIF_CFG_DEV0_EPF0_VF29_0_PCIE_VENDOR_SPECIFIC2 0x010c #define cfgBIF_CFG_DEV0_EPF0_VF29_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x0150 #define cfgBIF_CFG_DEV0_EPF0_VF29_0_PCIE_UNCORR_ERR_STATUS 0x0154 #define cfgBIF_CFG_DEV0_EPF0_VF29_0_PCIE_UNCORR_ERR_MASK 0x0158 #define cfgBIF_CFG_DEV0_EPF0_VF29_0_PCIE_UNCORR_ERR_SEVERITY 0x015c #define cfgBIF_CFG_DEV0_EPF0_VF29_0_PCIE_CORR_ERR_STATUS 0x0160 #define cfgBIF_CFG_DEV0_EPF0_VF29_0_PCIE_CORR_ERR_MASK 0x0164 #define cfgBIF_CFG_DEV0_EPF0_VF29_0_PCIE_ADV_ERR_CAP_CNTL 0x0168 #define cfgBIF_CFG_DEV0_EPF0_VF29_0_PCIE_HDR_LOG0 0x016c #define cfgBIF_CFG_DEV0_EPF0_VF29_0_PCIE_HDR_LOG1 0x0170 #define cfgBIF_CFG_DEV0_EPF0_VF29_0_PCIE_HDR_LOG2 0x0174 #define cfgBIF_CFG_DEV0_EPF0_VF29_0_PCIE_HDR_LOG3 0x0178 #define cfgBIF_CFG_DEV0_EPF0_VF29_0_PCIE_TLP_PREFIX_LOG0 0x0188 #define cfgBIF_CFG_DEV0_EPF0_VF29_0_PCIE_TLP_PREFIX_LOG1 0x018c #define cfgBIF_CFG_DEV0_EPF0_VF29_0_PCIE_TLP_PREFIX_LOG2 0x0190 #define cfgBIF_CFG_DEV0_EPF0_VF29_0_PCIE_TLP_PREFIX_LOG3 0x0194 #define cfgBIF_CFG_DEV0_EPF0_VF29_0_PCIE_ATS_ENH_CAP_LIST 0x02b0 #define cfgBIF_CFG_DEV0_EPF0_VF29_0_PCIE_ATS_CAP 0x02b4 #define cfgBIF_CFG_DEV0_EPF0_VF29_0_PCIE_ATS_CNTL 0x02b6 #define cfgBIF_CFG_DEV0_EPF0_VF29_0_PCIE_ARI_ENH_CAP_LIST 0x0328 #define cfgBIF_CFG_DEV0_EPF0_VF29_0_PCIE_ARI_CAP 0x032c #define cfgBIF_CFG_DEV0_EPF0_VF29_0_PCIE_ARI_CNTL 0x032e // addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf30_bifcfgdecp // base address: 0x0 #define cfgBIF_CFG_DEV0_EPF0_VF30_0_VENDOR_ID 0x0000 #define cfgBIF_CFG_DEV0_EPF0_VF30_0_DEVICE_ID 0x0002 #define cfgBIF_CFG_DEV0_EPF0_VF30_0_COMMAND 0x0004 #define cfgBIF_CFG_DEV0_EPF0_VF30_0_STATUS 0x0006 #define cfgBIF_CFG_DEV0_EPF0_VF30_0_REVISION_ID 0x0008 #define cfgBIF_CFG_DEV0_EPF0_VF30_0_PROG_INTERFACE 0x0009 #define cfgBIF_CFG_DEV0_EPF0_VF30_0_SUB_CLASS 0x000a #define cfgBIF_CFG_DEV0_EPF0_VF30_0_BASE_CLASS 0x000b #define cfgBIF_CFG_DEV0_EPF0_VF30_0_CACHE_LINE 0x000c #define cfgBIF_CFG_DEV0_EPF0_VF30_0_LATENCY 0x000d #define cfgBIF_CFG_DEV0_EPF0_VF30_0_HEADER 0x000e #define cfgBIF_CFG_DEV0_EPF0_VF30_0_BIST 0x000f #define cfgBIF_CFG_DEV0_EPF0_VF30_0_BASE_ADDR_1 0x0010 #define cfgBIF_CFG_DEV0_EPF0_VF30_0_BASE_ADDR_2 0x0014 #define cfgBIF_CFG_DEV0_EPF0_VF30_0_BASE_ADDR_3 0x0018 #define cfgBIF_CFG_DEV0_EPF0_VF30_0_BASE_ADDR_4 0x001c #define cfgBIF_CFG_DEV0_EPF0_VF30_0_BASE_ADDR_5 0x0020 #define cfgBIF_CFG_DEV0_EPF0_VF30_0_BASE_ADDR_6 0x0024 #define cfgBIF_CFG_DEV0_EPF0_VF30_0_CARDBUS_CIS_PTR 0x0028 #define cfgBIF_CFG_DEV0_EPF0_VF30_0_ADAPTER_ID 0x002c #define cfgBIF_CFG_DEV0_EPF0_VF30_0_ROM_BASE_ADDR 0x0030 #define cfgBIF_CFG_DEV0_EPF0_VF30_0_CAP_PTR 0x0034 #define cfgBIF_CFG_DEV0_EPF0_VF30_0_INTERRUPT_LINE 0x003c #define cfgBIF_CFG_DEV0_EPF0_VF30_0_INTERRUPT_PIN 0x003d #define cfgBIF_CFG_DEV0_EPF0_VF30_0_MIN_GRANT 0x003e #define cfgBIF_CFG_DEV0_EPF0_VF30_0_MAX_LATENCY 0x003f #define cfgBIF_CFG_DEV0_EPF0_VF30_0_PCIE_CAP_LIST 0x0064 #define cfgBIF_CFG_DEV0_EPF0_VF30_0_PCIE_CAP 0x0066 #define cfgBIF_CFG_DEV0_EPF0_VF30_0_DEVICE_CAP 0x0068 #define cfgBIF_CFG_DEV0_EPF0_VF30_0_DEVICE_CNTL 0x006c #define cfgBIF_CFG_DEV0_EPF0_VF30_0_DEVICE_STATUS 0x006e #define cfgBIF_CFG_DEV0_EPF0_VF30_0_LINK_CAP 0x0070 #define cfgBIF_CFG_DEV0_EPF0_VF30_0_LINK_CNTL 0x0074 #define cfgBIF_CFG_DEV0_EPF0_VF30_0_LINK_STATUS 0x0076 #define cfgBIF_CFG_DEV0_EPF0_VF30_0_DEVICE_CAP2 0x0088 #define cfgBIF_CFG_DEV0_EPF0_VF30_0_DEVICE_CNTL2 0x008c #define cfgBIF_CFG_DEV0_EPF0_VF30_0_DEVICE_STATUS2 0x008e #define cfgBIF_CFG_DEV0_EPF0_VF30_0_LINK_CAP2 0x0090 #define cfgBIF_CFG_DEV0_EPF0_VF30_0_LINK_CNTL2 0x0094 #define cfgBIF_CFG_DEV0_EPF0_VF30_0_LINK_STATUS2 0x0096 #define cfgBIF_CFG_DEV0_EPF0_VF30_0_MSI_CAP_LIST 0x00a0 #define cfgBIF_CFG_DEV0_EPF0_VF30_0_MSI_MSG_CNTL 0x00a2 #define cfgBIF_CFG_DEV0_EPF0_VF30_0_MSI_MSG_ADDR_LO 0x00a4 #define cfgBIF_CFG_DEV0_EPF0_VF30_0_MSI_MSG_ADDR_HI 0x00a8 #define cfgBIF_CFG_DEV0_EPF0_VF30_0_MSI_MSG_DATA 0x00a8 #define cfgBIF_CFG_DEV0_EPF0_VF30_0_MSI_MASK 0x00ac #define cfgBIF_CFG_DEV0_EPF0_VF30_0_MSI_MSG_DATA_64 0x00ac #define cfgBIF_CFG_DEV0_EPF0_VF30_0_MSI_MASK_64 0x00b0 #define cfgBIF_CFG_DEV0_EPF0_VF30_0_MSI_PENDING 0x00b0 #define cfgBIF_CFG_DEV0_EPF0_VF30_0_MSI_PENDING_64 0x00b4 #define cfgBIF_CFG_DEV0_EPF0_VF30_0_MSIX_CAP_LIST 0x00c0 #define cfgBIF_CFG_DEV0_EPF0_VF30_0_MSIX_MSG_CNTL 0x00c2 #define cfgBIF_CFG_DEV0_EPF0_VF30_0_MSIX_TABLE 0x00c4 #define cfgBIF_CFG_DEV0_EPF0_VF30_0_MSIX_PBA 0x00c8 #define cfgBIF_CFG_DEV0_EPF0_VF30_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x0100 #define cfgBIF_CFG_DEV0_EPF0_VF30_0_PCIE_VENDOR_SPECIFIC_HDR 0x0104 #define cfgBIF_CFG_DEV0_EPF0_VF30_0_PCIE_VENDOR_SPECIFIC1 0x0108 #define cfgBIF_CFG_DEV0_EPF0_VF30_0_PCIE_VENDOR_SPECIFIC2 0x010c #define cfgBIF_CFG_DEV0_EPF0_VF30_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x0150 #define cfgBIF_CFG_DEV0_EPF0_VF30_0_PCIE_UNCORR_ERR_STATUS 0x0154 #define cfgBIF_CFG_DEV0_EPF0_VF30_0_PCIE_UNCORR_ERR_MASK 0x0158 #define cfgBIF_CFG_DEV0_EPF0_VF30_0_PCIE_UNCORR_ERR_SEVERITY 0x015c #define cfgBIF_CFG_DEV0_EPF0_VF30_0_PCIE_CORR_ERR_STATUS 0x0160 #define cfgBIF_CFG_DEV0_EPF0_VF30_0_PCIE_CORR_ERR_MASK 0x0164 #define cfgBIF_CFG_DEV0_EPF0_VF30_0_PCIE_ADV_ERR_CAP_CNTL 0x0168 #define cfgBIF_CFG_DEV0_EPF0_VF30_0_PCIE_HDR_LOG0 0x016c #define cfgBIF_CFG_DEV0_EPF0_VF30_0_PCIE_HDR_LOG1 0x0170 #define cfgBIF_CFG_DEV0_EPF0_VF30_0_PCIE_HDR_LOG2 0x0174 #define cfgBIF_CFG_DEV0_EPF0_VF30_0_PCIE_HDR_LOG3 0x0178 #define cfgBIF_CFG_DEV0_EPF0_VF30_0_PCIE_TLP_PREFIX_LOG0 0x0188 #define cfgBIF_CFG_DEV0_EPF0_VF30_0_PCIE_TLP_PREFIX_LOG1 0x018c #define cfgBIF_CFG_DEV0_EPF0_VF30_0_PCIE_TLP_PREFIX_LOG2 0x0190 #define cfgBIF_CFG_DEV0_EPF0_VF30_0_PCIE_TLP_PREFIX_LOG3 0x0194 #define cfgBIF_CFG_DEV0_EPF0_VF30_0_PCIE_ATS_ENH_CAP_LIST 0x02b0 #define cfgBIF_CFG_DEV0_EPF0_VF30_0_PCIE_ATS_CAP 0x02b4 #define cfgBIF_CFG_DEV0_EPF0_VF30_0_PCIE_ATS_CNTL 0x02b6 #define cfgBIF_CFG_DEV0_EPF0_VF30_0_PCIE_ARI_ENH_CAP_LIST 0x0328 #define cfgBIF_CFG_DEV0_EPF0_VF30_0_PCIE_ARI_CAP 0x032c #define cfgBIF_CFG_DEV0_EPF0_VF30_0_PCIE_ARI_CNTL 0x032e // addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf0_SYSPFVFDEC // base address: 0x0 #define mmBIF_BX_DEV0_EPF0_VF0_MM_INDEX 0x0000 #define mmBIF_BX_DEV0_EPF0_VF0_MM_INDEX_BASE_IDX 0 #define mmBIF_BX_DEV0_EPF0_VF0_MM_DATA 0x0001 #define mmBIF_BX_DEV0_EPF0_VF0_MM_DATA_BASE_IDX 0 #define mmBIF_BX_DEV0_EPF0_VF0_MM_INDEX_HI 0x0006 #define mmBIF_BX_DEV0_EPF0_VF0_MM_INDEX_HI_BASE_IDX 0 // addressBlock: nbio_nbif0_rcc_dev0_epf0_vf0_BIFPFVFDEC1 // base address: 0x0 #define mmRCC_DEV0_EPF0_VF0_RCC_ERR_LOG 0x0085 #define mmRCC_DEV0_EPF0_VF0_RCC_ERR_LOG_BASE_IDX 2 #define mmRCC_DEV0_EPF0_VF0_RCC_DOORBELL_APER_EN 0x00c0 #define mmRCC_DEV0_EPF0_VF0_RCC_DOORBELL_APER_EN_BASE_IDX 2 #define mmRCC_DEV0_EPF0_VF0_RCC_CONFIG_MEMSIZE 0x00c3 #define mmRCC_DEV0_EPF0_VF0_RCC_CONFIG_MEMSIZE_BASE_IDX 2 #define mmRCC_DEV0_EPF0_VF0_RCC_CONFIG_RESERVED 0x00c4 #define mmRCC_DEV0_EPF0_VF0_RCC_CONFIG_RESERVED_BASE_IDX 2 #define mmRCC_DEV0_EPF0_VF0_RCC_IOV_FUNC_IDENTIFIER 0x00c5 #define mmRCC_DEV0_EPF0_VF0_RCC_IOV_FUNC_IDENTIFIER_BASE_IDX 2 // addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf0_BIFPFVFDEC1 // base address: 0x0 #define mmBIF_BX_DEV0_EPF0_VF0_BIF_BME_STATUS 0x00eb #define mmBIF_BX_DEV0_EPF0_VF0_BIF_BME_STATUS_BASE_IDX 2 #define mmBIF_BX_DEV0_EPF0_VF0_BIF_ATOMIC_ERR_LOG 0x00ec #define mmBIF_BX_DEV0_EPF0_VF0_BIF_ATOMIC_ERR_LOG_BASE_IDX 2 #define mmBIF_BX_DEV0_EPF0_VF0_DOORBELL_SELFRING_GPA_APER_BASE_HIGH 0x00f3 #define your_sha256_hash_IDX 2 #define mmBIF_BX_DEV0_EPF0_VF0_DOORBELL_SELFRING_GPA_APER_BASE_LOW 0x00f4 #define your_sha256_hashIDX 2 #define mmBIF_BX_DEV0_EPF0_VF0_DOORBELL_SELFRING_GPA_APER_CNTL 0x00f5 #define mmBIF_BX_DEV0_EPF0_VF0_DOORBELL_SELFRING_GPA_APER_CNTL_BASE_IDX 2 #define mmBIF_BX_DEV0_EPF0_VF0_HDP_REG_COHERENCY_FLUSH_CNTL 0x00f6 #define mmBIF_BX_DEV0_EPF0_VF0_HDP_REG_COHERENCY_FLUSH_CNTL_BASE_IDX 2 #define mmBIF_BX_DEV0_EPF0_VF0_HDP_MEM_COHERENCY_FLUSH_CNTL 0x00f7 #define mmBIF_BX_DEV0_EPF0_VF0_HDP_MEM_COHERENCY_FLUSH_CNTL_BASE_IDX 2 #define mmBIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_REQ 0x0106 #define mmBIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_REQ_BASE_IDX 2 #define mmBIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_DONE 0x0107 #define mmBIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_DONE_BASE_IDX 2 #define mmBIF_BX_DEV0_EPF0_VF0_BIF_TRANS_PENDING 0x0108 #define mmBIF_BX_DEV0_EPF0_VF0_BIF_TRANS_PENDING_BASE_IDX 2 #define mmBIF_BX_DEV0_EPF0_VF0_NBIF_GFX_ADDR_LUT_BYPASS 0x0112 #define mmBIF_BX_DEV0_EPF0_VF0_NBIF_GFX_ADDR_LUT_BYPASS_BASE_IDX 2 #define mmBIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_TRN_DW0 0x0136 #define mmBIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_TRN_DW0_BASE_IDX 2 #define mmBIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_TRN_DW1 0x0137 #define mmBIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_TRN_DW1_BASE_IDX 2 #define mmBIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_TRN_DW2 0x0138 #define mmBIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_TRN_DW2_BASE_IDX 2 #define mmBIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_TRN_DW3 0x0139 #define mmBIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_TRN_DW3_BASE_IDX 2 #define mmBIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_RCV_DW0 0x013a #define mmBIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_RCV_DW0_BASE_IDX 2 #define mmBIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_RCV_DW1 0x013b #define mmBIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_RCV_DW1_BASE_IDX 2 #define mmBIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_RCV_DW2 0x013c #define mmBIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_RCV_DW2_BASE_IDX 2 #define mmBIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_RCV_DW3 0x013d #define mmBIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_RCV_DW3_BASE_IDX 2 #define mmBIF_BX_DEV0_EPF0_VF0_MAILBOX_CONTROL 0x013e #define mmBIF_BX_DEV0_EPF0_VF0_MAILBOX_CONTROL_BASE_IDX 2 #define mmBIF_BX_DEV0_EPF0_VF0_MAILBOX_INT_CNTL 0x013f #define mmBIF_BX_DEV0_EPF0_VF0_MAILBOX_INT_CNTL_BASE_IDX 2 #define mmBIF_BX_DEV0_EPF0_VF0_BIF_VMHV_MAILBOX 0x0140 #define mmBIF_BX_DEV0_EPF0_VF0_BIF_VMHV_MAILBOX_BASE_IDX 2 // addressBlock: nbio_nbif0_rcc_dev0_epf0_vf0_BIFDEC2 // base address: 0x0 #define mmRCC_DEV0_EPF0_VF0_GFXMSIX_VECT0_ADDR_LO 0x0400 #define mmRCC_DEV0_EPF0_VF0_GFXMSIX_VECT0_ADDR_LO_BASE_IDX 3 #define mmRCC_DEV0_EPF0_VF0_GFXMSIX_VECT0_ADDR_HI 0x0401 #define mmRCC_DEV0_EPF0_VF0_GFXMSIX_VECT0_ADDR_HI_BASE_IDX 3 #define mmRCC_DEV0_EPF0_VF0_GFXMSIX_VECT0_MSG_DATA 0x0402 #define mmRCC_DEV0_EPF0_VF0_GFXMSIX_VECT0_MSG_DATA_BASE_IDX 3 #define mmRCC_DEV0_EPF0_VF0_GFXMSIX_VECT0_CONTROL 0x0403 #define mmRCC_DEV0_EPF0_VF0_GFXMSIX_VECT0_CONTROL_BASE_IDX 3 #define mmRCC_DEV0_EPF0_VF0_GFXMSIX_VECT1_ADDR_LO 0x0404 #define mmRCC_DEV0_EPF0_VF0_GFXMSIX_VECT1_ADDR_LO_BASE_IDX 3 #define mmRCC_DEV0_EPF0_VF0_GFXMSIX_VECT1_ADDR_HI 0x0405 #define mmRCC_DEV0_EPF0_VF0_GFXMSIX_VECT1_ADDR_HI_BASE_IDX 3 #define mmRCC_DEV0_EPF0_VF0_GFXMSIX_VECT1_MSG_DATA 0x0406 #define mmRCC_DEV0_EPF0_VF0_GFXMSIX_VECT1_MSG_DATA_BASE_IDX 3 #define mmRCC_DEV0_EPF0_VF0_GFXMSIX_VECT1_CONTROL 0x0407 #define mmRCC_DEV0_EPF0_VF0_GFXMSIX_VECT1_CONTROL_BASE_IDX 3 #define mmRCC_DEV0_EPF0_VF0_GFXMSIX_VECT2_ADDR_LO 0x0408 #define mmRCC_DEV0_EPF0_VF0_GFXMSIX_VECT2_ADDR_LO_BASE_IDX 3 #define mmRCC_DEV0_EPF0_VF0_GFXMSIX_VECT2_ADDR_HI 0x0409 #define mmRCC_DEV0_EPF0_VF0_GFXMSIX_VECT2_ADDR_HI_BASE_IDX 3 #define mmRCC_DEV0_EPF0_VF0_GFXMSIX_VECT2_MSG_DATA 0x040a #define mmRCC_DEV0_EPF0_VF0_GFXMSIX_VECT2_MSG_DATA_BASE_IDX 3 #define mmRCC_DEV0_EPF0_VF0_GFXMSIX_VECT2_CONTROL 0x040b #define mmRCC_DEV0_EPF0_VF0_GFXMSIX_VECT2_CONTROL_BASE_IDX 3 #define mmRCC_DEV0_EPF0_VF0_GFXMSIX_VECT3_ADDR_LO 0x040c #define mmRCC_DEV0_EPF0_VF0_GFXMSIX_VECT3_ADDR_LO_BASE_IDX 3 #define mmRCC_DEV0_EPF0_VF0_GFXMSIX_VECT3_ADDR_HI 0x040d #define mmRCC_DEV0_EPF0_VF0_GFXMSIX_VECT3_ADDR_HI_BASE_IDX 3 #define mmRCC_DEV0_EPF0_VF0_GFXMSIX_VECT3_MSG_DATA 0x040e #define mmRCC_DEV0_EPF0_VF0_GFXMSIX_VECT3_MSG_DATA_BASE_IDX 3 #define mmRCC_DEV0_EPF0_VF0_GFXMSIX_VECT3_CONTROL 0x040f #define mmRCC_DEV0_EPF0_VF0_GFXMSIX_VECT3_CONTROL_BASE_IDX 3 #define mmRCC_DEV0_EPF0_VF0_GFXMSIX_PBA 0x0800 #define mmRCC_DEV0_EPF0_VF0_GFXMSIX_PBA_BASE_IDX 3 // addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf1_SYSPFVFDEC // base address: 0x0 #define mmBIF_BX_DEV0_EPF0_VF1_MM_INDEX 0x0000 #define mmBIF_BX_DEV0_EPF0_VF1_MM_INDEX_BASE_IDX 0 #define mmBIF_BX_DEV0_EPF0_VF1_MM_DATA 0x0001 #define mmBIF_BX_DEV0_EPF0_VF1_MM_DATA_BASE_IDX 0 #define mmBIF_BX_DEV0_EPF0_VF1_MM_INDEX_HI 0x0006 #define mmBIF_BX_DEV0_EPF0_VF1_MM_INDEX_HI_BASE_IDX 0 // addressBlock: nbio_nbif0_rcc_dev0_epf0_vf1_BIFPFVFDEC1 // base address: 0x0 #define mmRCC_DEV0_EPF0_VF1_RCC_ERR_LOG 0x0085 #define mmRCC_DEV0_EPF0_VF1_RCC_ERR_LOG_BASE_IDX 2 #define mmRCC_DEV0_EPF0_VF1_RCC_DOORBELL_APER_EN 0x00c0 #define mmRCC_DEV0_EPF0_VF1_RCC_DOORBELL_APER_EN_BASE_IDX 2 #define mmRCC_DEV0_EPF0_VF1_RCC_CONFIG_MEMSIZE 0x00c3 #define mmRCC_DEV0_EPF0_VF1_RCC_CONFIG_MEMSIZE_BASE_IDX 2 #define mmRCC_DEV0_EPF0_VF1_RCC_CONFIG_RESERVED 0x00c4 #define mmRCC_DEV0_EPF0_VF1_RCC_CONFIG_RESERVED_BASE_IDX 2 #define mmRCC_DEV0_EPF0_VF1_RCC_IOV_FUNC_IDENTIFIER 0x00c5 #define mmRCC_DEV0_EPF0_VF1_RCC_IOV_FUNC_IDENTIFIER_BASE_IDX 2 // addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf1_BIFPFVFDEC1 // base address: 0x0 #define mmBIF_BX_DEV0_EPF0_VF1_BIF_BME_STATUS 0x00eb #define mmBIF_BX_DEV0_EPF0_VF1_BIF_BME_STATUS_BASE_IDX 2 #define mmBIF_BX_DEV0_EPF0_VF1_BIF_ATOMIC_ERR_LOG 0x00ec #define mmBIF_BX_DEV0_EPF0_VF1_BIF_ATOMIC_ERR_LOG_BASE_IDX 2 #define mmBIF_BX_DEV0_EPF0_VF1_DOORBELL_SELFRING_GPA_APER_BASE_HIGH 0x00f3 #define your_sha256_hash_IDX 2 #define mmBIF_BX_DEV0_EPF0_VF1_DOORBELL_SELFRING_GPA_APER_BASE_LOW 0x00f4 #define your_sha256_hashIDX 2 #define mmBIF_BX_DEV0_EPF0_VF1_DOORBELL_SELFRING_GPA_APER_CNTL 0x00f5 #define mmBIF_BX_DEV0_EPF0_VF1_DOORBELL_SELFRING_GPA_APER_CNTL_BASE_IDX 2 #define mmBIF_BX_DEV0_EPF0_VF1_HDP_REG_COHERENCY_FLUSH_CNTL 0x00f6 #define mmBIF_BX_DEV0_EPF0_VF1_HDP_REG_COHERENCY_FLUSH_CNTL_BASE_IDX 2 #define mmBIF_BX_DEV0_EPF0_VF1_HDP_MEM_COHERENCY_FLUSH_CNTL 0x00f7 #define mmBIF_BX_DEV0_EPF0_VF1_HDP_MEM_COHERENCY_FLUSH_CNTL_BASE_IDX 2 #define mmBIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_REQ 0x0106 #define mmBIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_REQ_BASE_IDX 2 #define mmBIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_DONE 0x0107 #define mmBIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_DONE_BASE_IDX 2 #define mmBIF_BX_DEV0_EPF0_VF1_BIF_TRANS_PENDING 0x0108 #define mmBIF_BX_DEV0_EPF0_VF1_BIF_TRANS_PENDING_BASE_IDX 2 #define mmBIF_BX_DEV0_EPF0_VF1_NBIF_GFX_ADDR_LUT_BYPASS 0x0112 #define mmBIF_BX_DEV0_EPF0_VF1_NBIF_GFX_ADDR_LUT_BYPASS_BASE_IDX 2 #define mmBIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_TRN_DW0 0x0136 #define mmBIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_TRN_DW0_BASE_IDX 2 #define mmBIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_TRN_DW1 0x0137 #define mmBIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_TRN_DW1_BASE_IDX 2 #define mmBIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_TRN_DW2 0x0138 #define mmBIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_TRN_DW2_BASE_IDX 2 #define mmBIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_TRN_DW3 0x0139 #define mmBIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_TRN_DW3_BASE_IDX 2 #define mmBIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_RCV_DW0 0x013a #define mmBIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_RCV_DW0_BASE_IDX 2 #define mmBIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_RCV_DW1 0x013b #define mmBIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_RCV_DW1_BASE_IDX 2 #define mmBIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_RCV_DW2 0x013c #define mmBIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_RCV_DW2_BASE_IDX 2 #define mmBIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_RCV_DW3 0x013d #define mmBIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_RCV_DW3_BASE_IDX 2 #define mmBIF_BX_DEV0_EPF0_VF1_MAILBOX_CONTROL 0x013e #define mmBIF_BX_DEV0_EPF0_VF1_MAILBOX_CONTROL_BASE_IDX 2 #define mmBIF_BX_DEV0_EPF0_VF1_MAILBOX_INT_CNTL 0x013f #define mmBIF_BX_DEV0_EPF0_VF1_MAILBOX_INT_CNTL_BASE_IDX 2 #define mmBIF_BX_DEV0_EPF0_VF1_BIF_VMHV_MAILBOX 0x0140 #define mmBIF_BX_DEV0_EPF0_VF1_BIF_VMHV_MAILBOX_BASE_IDX 2 // addressBlock: nbio_nbif0_rcc_dev0_epf0_vf1_BIFDEC2 // base address: 0x0 #define mmRCC_DEV0_EPF0_VF1_GFXMSIX_VECT0_ADDR_LO 0x0400 #define mmRCC_DEV0_EPF0_VF1_GFXMSIX_VECT0_ADDR_LO_BASE_IDX 3 #define mmRCC_DEV0_EPF0_VF1_GFXMSIX_VECT0_ADDR_HI 0x0401 #define mmRCC_DEV0_EPF0_VF1_GFXMSIX_VECT0_ADDR_HI_BASE_IDX 3 #define mmRCC_DEV0_EPF0_VF1_GFXMSIX_VECT0_MSG_DATA 0x0402 #define mmRCC_DEV0_EPF0_VF1_GFXMSIX_VECT0_MSG_DATA_BASE_IDX 3 #define mmRCC_DEV0_EPF0_VF1_GFXMSIX_VECT0_CONTROL 0x0403 #define mmRCC_DEV0_EPF0_VF1_GFXMSIX_VECT0_CONTROL_BASE_IDX 3 #define mmRCC_DEV0_EPF0_VF1_GFXMSIX_VECT1_ADDR_LO 0x0404 #define mmRCC_DEV0_EPF0_VF1_GFXMSIX_VECT1_ADDR_LO_BASE_IDX 3 #define mmRCC_DEV0_EPF0_VF1_GFXMSIX_VECT1_ADDR_HI 0x0405 #define mmRCC_DEV0_EPF0_VF1_GFXMSIX_VECT1_ADDR_HI_BASE_IDX 3 #define mmRCC_DEV0_EPF0_VF1_GFXMSIX_VECT1_MSG_DATA 0x0406 #define mmRCC_DEV0_EPF0_VF1_GFXMSIX_VECT1_MSG_DATA_BASE_IDX 3 #define mmRCC_DEV0_EPF0_VF1_GFXMSIX_VECT1_CONTROL 0x0407 #define mmRCC_DEV0_EPF0_VF1_GFXMSIX_VECT1_CONTROL_BASE_IDX 3 #define mmRCC_DEV0_EPF0_VF1_GFXMSIX_VECT2_ADDR_LO 0x0408 #define mmRCC_DEV0_EPF0_VF1_GFXMSIX_VECT2_ADDR_LO_BASE_IDX 3 #define mmRCC_DEV0_EPF0_VF1_GFXMSIX_VECT2_ADDR_HI 0x0409 #define mmRCC_DEV0_EPF0_VF1_GFXMSIX_VECT2_ADDR_HI_BASE_IDX 3 #define mmRCC_DEV0_EPF0_VF1_GFXMSIX_VECT2_MSG_DATA 0x040a #define mmRCC_DEV0_EPF0_VF1_GFXMSIX_VECT2_MSG_DATA_BASE_IDX 3 #define mmRCC_DEV0_EPF0_VF1_GFXMSIX_VECT2_CONTROL 0x040b #define mmRCC_DEV0_EPF0_VF1_GFXMSIX_VECT2_CONTROL_BASE_IDX 3 #define mmRCC_DEV0_EPF0_VF1_GFXMSIX_VECT3_ADDR_LO 0x040c #define mmRCC_DEV0_EPF0_VF1_GFXMSIX_VECT3_ADDR_LO_BASE_IDX 3 #define mmRCC_DEV0_EPF0_VF1_GFXMSIX_VECT3_ADDR_HI 0x040d #define mmRCC_DEV0_EPF0_VF1_GFXMSIX_VECT3_ADDR_HI_BASE_IDX 3 #define mmRCC_DEV0_EPF0_VF1_GFXMSIX_VECT3_MSG_DATA 0x040e #define mmRCC_DEV0_EPF0_VF1_GFXMSIX_VECT3_MSG_DATA_BASE_IDX 3 #define mmRCC_DEV0_EPF0_VF1_GFXMSIX_VECT3_CONTROL 0x040f #define mmRCC_DEV0_EPF0_VF1_GFXMSIX_VECT3_CONTROL_BASE_IDX 3 #define mmRCC_DEV0_EPF0_VF1_GFXMSIX_PBA 0x0800 #define mmRCC_DEV0_EPF0_VF1_GFXMSIX_PBA_BASE_IDX 3 // addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf2_SYSPFVFDEC // base address: 0x0 #define mmBIF_BX_DEV0_EPF0_VF2_MM_INDEX 0x0000 #define mmBIF_BX_DEV0_EPF0_VF2_MM_INDEX_BASE_IDX 0 #define mmBIF_BX_DEV0_EPF0_VF2_MM_DATA 0x0001 #define mmBIF_BX_DEV0_EPF0_VF2_MM_DATA_BASE_IDX 0 #define mmBIF_BX_DEV0_EPF0_VF2_MM_INDEX_HI 0x0006 #define mmBIF_BX_DEV0_EPF0_VF2_MM_INDEX_HI_BASE_IDX 0 // addressBlock: nbio_nbif0_rcc_dev0_epf0_vf2_BIFPFVFDEC1 // base address: 0x0 #define mmRCC_DEV0_EPF0_VF2_RCC_ERR_LOG 0x0085 #define mmRCC_DEV0_EPF0_VF2_RCC_ERR_LOG_BASE_IDX 2 #define mmRCC_DEV0_EPF0_VF2_RCC_DOORBELL_APER_EN 0x00c0 #define mmRCC_DEV0_EPF0_VF2_RCC_DOORBELL_APER_EN_BASE_IDX 2 #define mmRCC_DEV0_EPF0_VF2_RCC_CONFIG_MEMSIZE 0x00c3 #define mmRCC_DEV0_EPF0_VF2_RCC_CONFIG_MEMSIZE_BASE_IDX 2 #define mmRCC_DEV0_EPF0_VF2_RCC_CONFIG_RESERVED 0x00c4 #define mmRCC_DEV0_EPF0_VF2_RCC_CONFIG_RESERVED_BASE_IDX 2 #define mmRCC_DEV0_EPF0_VF2_RCC_IOV_FUNC_IDENTIFIER 0x00c5 #define mmRCC_DEV0_EPF0_VF2_RCC_IOV_FUNC_IDENTIFIER_BASE_IDX 2 // addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf2_BIFPFVFDEC1 // base address: 0x0 #define mmBIF_BX_DEV0_EPF0_VF2_BIF_BME_STATUS 0x00eb #define mmBIF_BX_DEV0_EPF0_VF2_BIF_BME_STATUS_BASE_IDX 2 #define mmBIF_BX_DEV0_EPF0_VF2_BIF_ATOMIC_ERR_LOG 0x00ec #define mmBIF_BX_DEV0_EPF0_VF2_BIF_ATOMIC_ERR_LOG_BASE_IDX 2 #define mmBIF_BX_DEV0_EPF0_VF2_DOORBELL_SELFRING_GPA_APER_BASE_HIGH 0x00f3 #define your_sha256_hash_IDX 2 #define mmBIF_BX_DEV0_EPF0_VF2_DOORBELL_SELFRING_GPA_APER_BASE_LOW 0x00f4 #define your_sha256_hashIDX 2 #define mmBIF_BX_DEV0_EPF0_VF2_DOORBELL_SELFRING_GPA_APER_CNTL 0x00f5 #define mmBIF_BX_DEV0_EPF0_VF2_DOORBELL_SELFRING_GPA_APER_CNTL_BASE_IDX 2 #define mmBIF_BX_DEV0_EPF0_VF2_HDP_REG_COHERENCY_FLUSH_CNTL 0x00f6 #define mmBIF_BX_DEV0_EPF0_VF2_HDP_REG_COHERENCY_FLUSH_CNTL_BASE_IDX 2 #define mmBIF_BX_DEV0_EPF0_VF2_HDP_MEM_COHERENCY_FLUSH_CNTL 0x00f7 #define mmBIF_BX_DEV0_EPF0_VF2_HDP_MEM_COHERENCY_FLUSH_CNTL_BASE_IDX 2 #define mmBIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_REQ 0x0106 #define mmBIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_REQ_BASE_IDX 2 #define mmBIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_DONE 0x0107 #define mmBIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_DONE_BASE_IDX 2 #define mmBIF_BX_DEV0_EPF0_VF2_BIF_TRANS_PENDING 0x0108 #define mmBIF_BX_DEV0_EPF0_VF2_BIF_TRANS_PENDING_BASE_IDX 2 #define mmBIF_BX_DEV0_EPF0_VF2_NBIF_GFX_ADDR_LUT_BYPASS 0x0112 #define mmBIF_BX_DEV0_EPF0_VF2_NBIF_GFX_ADDR_LUT_BYPASS_BASE_IDX 2 #define mmBIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_TRN_DW0 0x0136 #define mmBIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_TRN_DW0_BASE_IDX 2 #define mmBIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_TRN_DW1 0x0137 #define mmBIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_TRN_DW1_BASE_IDX 2 #define mmBIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_TRN_DW2 0x0138 #define mmBIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_TRN_DW2_BASE_IDX 2 #define mmBIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_TRN_DW3 0x0139 #define mmBIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_TRN_DW3_BASE_IDX 2 #define mmBIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_RCV_DW0 0x013a #define mmBIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_RCV_DW0_BASE_IDX 2 #define mmBIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_RCV_DW1 0x013b #define mmBIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_RCV_DW1_BASE_IDX 2 #define mmBIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_RCV_DW2 0x013c #define mmBIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_RCV_DW2_BASE_IDX 2 #define mmBIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_RCV_DW3 0x013d #define mmBIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_RCV_DW3_BASE_IDX 2 #define mmBIF_BX_DEV0_EPF0_VF2_MAILBOX_CONTROL 0x013e #define mmBIF_BX_DEV0_EPF0_VF2_MAILBOX_CONTROL_BASE_IDX 2 #define mmBIF_BX_DEV0_EPF0_VF2_MAILBOX_INT_CNTL 0x013f #define mmBIF_BX_DEV0_EPF0_VF2_MAILBOX_INT_CNTL_BASE_IDX 2 #define mmBIF_BX_DEV0_EPF0_VF2_BIF_VMHV_MAILBOX 0x0140 #define mmBIF_BX_DEV0_EPF0_VF2_BIF_VMHV_MAILBOX_BASE_IDX 2 // addressBlock: nbio_nbif0_rcc_dev0_epf0_vf2_BIFDEC2 // base address: 0x0 #define mmRCC_DEV0_EPF0_VF2_GFXMSIX_VECT0_ADDR_LO 0x0400 #define mmRCC_DEV0_EPF0_VF2_GFXMSIX_VECT0_ADDR_LO_BASE_IDX 3 #define mmRCC_DEV0_EPF0_VF2_GFXMSIX_VECT0_ADDR_HI 0x0401 #define mmRCC_DEV0_EPF0_VF2_GFXMSIX_VECT0_ADDR_HI_BASE_IDX 3 #define mmRCC_DEV0_EPF0_VF2_GFXMSIX_VECT0_MSG_DATA 0x0402 #define mmRCC_DEV0_EPF0_VF2_GFXMSIX_VECT0_MSG_DATA_BASE_IDX 3 #define mmRCC_DEV0_EPF0_VF2_GFXMSIX_VECT0_CONTROL 0x0403 #define mmRCC_DEV0_EPF0_VF2_GFXMSIX_VECT0_CONTROL_BASE_IDX 3 #define mmRCC_DEV0_EPF0_VF2_GFXMSIX_VECT1_ADDR_LO 0x0404 #define mmRCC_DEV0_EPF0_VF2_GFXMSIX_VECT1_ADDR_LO_BASE_IDX 3 #define mmRCC_DEV0_EPF0_VF2_GFXMSIX_VECT1_ADDR_HI 0x0405 #define mmRCC_DEV0_EPF0_VF2_GFXMSIX_VECT1_ADDR_HI_BASE_IDX 3 #define mmRCC_DEV0_EPF0_VF2_GFXMSIX_VECT1_MSG_DATA 0x0406 #define mmRCC_DEV0_EPF0_VF2_GFXMSIX_VECT1_MSG_DATA_BASE_IDX 3 #define mmRCC_DEV0_EPF0_VF2_GFXMSIX_VECT1_CONTROL 0x0407 #define mmRCC_DEV0_EPF0_VF2_GFXMSIX_VECT1_CONTROL_BASE_IDX 3 #define mmRCC_DEV0_EPF0_VF2_GFXMSIX_VECT2_ADDR_LO 0x0408 #define mmRCC_DEV0_EPF0_VF2_GFXMSIX_VECT2_ADDR_LO_BASE_IDX 3 #define mmRCC_DEV0_EPF0_VF2_GFXMSIX_VECT2_ADDR_HI 0x0409 #define mmRCC_DEV0_EPF0_VF2_GFXMSIX_VECT2_ADDR_HI_BASE_IDX 3 #define mmRCC_DEV0_EPF0_VF2_GFXMSIX_VECT2_MSG_DATA 0x040a #define mmRCC_DEV0_EPF0_VF2_GFXMSIX_VECT2_MSG_DATA_BASE_IDX 3 #define mmRCC_DEV0_EPF0_VF2_GFXMSIX_VECT2_CONTROL 0x040b #define mmRCC_DEV0_EPF0_VF2_GFXMSIX_VECT2_CONTROL_BASE_IDX 3 #define mmRCC_DEV0_EPF0_VF2_GFXMSIX_VECT3_ADDR_LO 0x040c #define mmRCC_DEV0_EPF0_VF2_GFXMSIX_VECT3_ADDR_LO_BASE_IDX 3 #define mmRCC_DEV0_EPF0_VF2_GFXMSIX_VECT3_ADDR_HI 0x040d #define mmRCC_DEV0_EPF0_VF2_GFXMSIX_VECT3_ADDR_HI_BASE_IDX 3 #define mmRCC_DEV0_EPF0_VF2_GFXMSIX_VECT3_MSG_DATA 0x040e #define mmRCC_DEV0_EPF0_VF2_GFXMSIX_VECT3_MSG_DATA_BASE_IDX 3 #define mmRCC_DEV0_EPF0_VF2_GFXMSIX_VECT3_CONTROL 0x040f #define mmRCC_DEV0_EPF0_VF2_GFXMSIX_VECT3_CONTROL_BASE_IDX 3 #define mmRCC_DEV0_EPF0_VF2_GFXMSIX_PBA 0x0800 #define mmRCC_DEV0_EPF0_VF2_GFXMSIX_PBA_BASE_IDX 3 // addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf3_SYSPFVFDEC // base address: 0x0 #define mmBIF_BX_DEV0_EPF0_VF3_MM_INDEX 0x0000 #define mmBIF_BX_DEV0_EPF0_VF3_MM_INDEX_BASE_IDX 0 #define mmBIF_BX_DEV0_EPF0_VF3_MM_DATA 0x0001 #define mmBIF_BX_DEV0_EPF0_VF3_MM_DATA_BASE_IDX 0 #define mmBIF_BX_DEV0_EPF0_VF3_MM_INDEX_HI 0x0006 #define mmBIF_BX_DEV0_EPF0_VF3_MM_INDEX_HI_BASE_IDX 0 // addressBlock: nbio_nbif0_rcc_dev0_epf0_vf3_BIFPFVFDEC1 // base address: 0x0 #define mmRCC_DEV0_EPF0_VF3_RCC_ERR_LOG 0x0085 #define mmRCC_DEV0_EPF0_VF3_RCC_ERR_LOG_BASE_IDX 2 #define mmRCC_DEV0_EPF0_VF3_RCC_DOORBELL_APER_EN 0x00c0 #define mmRCC_DEV0_EPF0_VF3_RCC_DOORBELL_APER_EN_BASE_IDX 2 #define mmRCC_DEV0_EPF0_VF3_RCC_CONFIG_MEMSIZE 0x00c3 #define mmRCC_DEV0_EPF0_VF3_RCC_CONFIG_MEMSIZE_BASE_IDX 2 #define mmRCC_DEV0_EPF0_VF3_RCC_CONFIG_RESERVED 0x00c4 #define mmRCC_DEV0_EPF0_VF3_RCC_CONFIG_RESERVED_BASE_IDX 2 #define mmRCC_DEV0_EPF0_VF3_RCC_IOV_FUNC_IDENTIFIER 0x00c5 #define mmRCC_DEV0_EPF0_VF3_RCC_IOV_FUNC_IDENTIFIER_BASE_IDX 2 // addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf3_BIFPFVFDEC1 // base address: 0x0 #define mmBIF_BX_DEV0_EPF0_VF3_BIF_BME_STATUS 0x00eb #define mmBIF_BX_DEV0_EPF0_VF3_BIF_BME_STATUS_BASE_IDX 2 #define mmBIF_BX_DEV0_EPF0_VF3_BIF_ATOMIC_ERR_LOG 0x00ec #define mmBIF_BX_DEV0_EPF0_VF3_BIF_ATOMIC_ERR_LOG_BASE_IDX 2 #define mmBIF_BX_DEV0_EPF0_VF3_DOORBELL_SELFRING_GPA_APER_BASE_HIGH 0x00f3 #define your_sha256_hash_IDX 2 #define mmBIF_BX_DEV0_EPF0_VF3_DOORBELL_SELFRING_GPA_APER_BASE_LOW 0x00f4 #define your_sha256_hashIDX 2 #define mmBIF_BX_DEV0_EPF0_VF3_DOORBELL_SELFRING_GPA_APER_CNTL 0x00f5 #define mmBIF_BX_DEV0_EPF0_VF3_DOORBELL_SELFRING_GPA_APER_CNTL_BASE_IDX 2 #define mmBIF_BX_DEV0_EPF0_VF3_HDP_REG_COHERENCY_FLUSH_CNTL 0x00f6 #define mmBIF_BX_DEV0_EPF0_VF3_HDP_REG_COHERENCY_FLUSH_CNTL_BASE_IDX 2 #define mmBIF_BX_DEV0_EPF0_VF3_HDP_MEM_COHERENCY_FLUSH_CNTL 0x00f7 #define mmBIF_BX_DEV0_EPF0_VF3_HDP_MEM_COHERENCY_FLUSH_CNTL_BASE_IDX 2 #define mmBIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_REQ 0x0106 #define mmBIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_REQ_BASE_IDX 2 #define mmBIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_DONE 0x0107 #define mmBIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_DONE_BASE_IDX 2 #define mmBIF_BX_DEV0_EPF0_VF3_BIF_TRANS_PENDING 0x0108 #define mmBIF_BX_DEV0_EPF0_VF3_BIF_TRANS_PENDING_BASE_IDX 2 #define mmBIF_BX_DEV0_EPF0_VF3_NBIF_GFX_ADDR_LUT_BYPASS 0x0112 #define mmBIF_BX_DEV0_EPF0_VF3_NBIF_GFX_ADDR_LUT_BYPASS_BASE_IDX 2 #define mmBIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_TRN_DW0 0x0136 #define mmBIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_TRN_DW0_BASE_IDX 2 #define mmBIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_TRN_DW1 0x0137 #define mmBIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_TRN_DW1_BASE_IDX 2 #define mmBIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_TRN_DW2 0x0138 #define mmBIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_TRN_DW2_BASE_IDX 2 #define mmBIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_TRN_DW3 0x0139 #define mmBIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_TRN_DW3_BASE_IDX 2 #define mmBIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_RCV_DW0 0x013a #define mmBIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_RCV_DW0_BASE_IDX 2 #define mmBIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_RCV_DW1 0x013b #define mmBIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_RCV_DW1_BASE_IDX 2 #define mmBIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_RCV_DW2 0x013c #define mmBIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_RCV_DW2_BASE_IDX 2 #define mmBIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_RCV_DW3 0x013d #define mmBIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_RCV_DW3_BASE_IDX 2 #define mmBIF_BX_DEV0_EPF0_VF3_MAILBOX_CONTROL 0x013e #define mmBIF_BX_DEV0_EPF0_VF3_MAILBOX_CONTROL_BASE_IDX 2 #define mmBIF_BX_DEV0_EPF0_VF3_MAILBOX_INT_CNTL 0x013f #define mmBIF_BX_DEV0_EPF0_VF3_MAILBOX_INT_CNTL_BASE_IDX 2 #define mmBIF_BX_DEV0_EPF0_VF3_BIF_VMHV_MAILBOX 0x0140 #define mmBIF_BX_DEV0_EPF0_VF3_BIF_VMHV_MAILBOX_BASE_IDX 2 // addressBlock: nbio_nbif0_rcc_dev0_epf0_vf3_BIFDEC2 // base address: 0x0 #define mmRCC_DEV0_EPF0_VF3_GFXMSIX_VECT0_ADDR_LO 0x0400 #define mmRCC_DEV0_EPF0_VF3_GFXMSIX_VECT0_ADDR_LO_BASE_IDX 3 #define mmRCC_DEV0_EPF0_VF3_GFXMSIX_VECT0_ADDR_HI 0x0401 #define mmRCC_DEV0_EPF0_VF3_GFXMSIX_VECT0_ADDR_HI_BASE_IDX 3 #define mmRCC_DEV0_EPF0_VF3_GFXMSIX_VECT0_MSG_DATA 0x0402 #define mmRCC_DEV0_EPF0_VF3_GFXMSIX_VECT0_MSG_DATA_BASE_IDX 3 #define mmRCC_DEV0_EPF0_VF3_GFXMSIX_VECT0_CONTROL 0x0403 #define mmRCC_DEV0_EPF0_VF3_GFXMSIX_VECT0_CONTROL_BASE_IDX 3 #define mmRCC_DEV0_EPF0_VF3_GFXMSIX_VECT1_ADDR_LO 0x0404 #define mmRCC_DEV0_EPF0_VF3_GFXMSIX_VECT1_ADDR_LO_BASE_IDX 3 #define mmRCC_DEV0_EPF0_VF3_GFXMSIX_VECT1_ADDR_HI 0x0405 #define mmRCC_DEV0_EPF0_VF3_GFXMSIX_VECT1_ADDR_HI_BASE_IDX 3 #define mmRCC_DEV0_EPF0_VF3_GFXMSIX_VECT1_MSG_DATA 0x0406 #define mmRCC_DEV0_EPF0_VF3_GFXMSIX_VECT1_MSG_DATA_BASE_IDX 3 #define mmRCC_DEV0_EPF0_VF3_GFXMSIX_VECT1_CONTROL 0x0407 #define mmRCC_DEV0_EPF0_VF3_GFXMSIX_VECT1_CONTROL_BASE_IDX 3 #define mmRCC_DEV0_EPF0_VF3_GFXMSIX_VECT2_ADDR_LO 0x0408 #define mmRCC_DEV0_EPF0_VF3_GFXMSIX_VECT2_ADDR_LO_BASE_IDX 3 #define mmRCC_DEV0_EPF0_VF3_GFXMSIX_VECT2_ADDR_HI 0x0409 #define mmRCC_DEV0_EPF0_VF3_GFXMSIX_VECT2_ADDR_HI_BASE_IDX 3 #define mmRCC_DEV0_EPF0_VF3_GFXMSIX_VECT2_MSG_DATA 0x040a #define mmRCC_DEV0_EPF0_VF3_GFXMSIX_VECT2_MSG_DATA_BASE_IDX 3 #define mmRCC_DEV0_EPF0_VF3_GFXMSIX_VECT2_CONTROL 0x040b #define mmRCC_DEV0_EPF0_VF3_GFXMSIX_VECT2_CONTROL_BASE_IDX 3 #define mmRCC_DEV0_EPF0_VF3_GFXMSIX_VECT3_ADDR_LO 0x040c #define mmRCC_DEV0_EPF0_VF3_GFXMSIX_VECT3_ADDR_LO_BASE_IDX 3 #define mmRCC_DEV0_EPF0_VF3_GFXMSIX_VECT3_ADDR_HI 0x040d #define mmRCC_DEV0_EPF0_VF3_GFXMSIX_VECT3_ADDR_HI_BASE_IDX 3 #define mmRCC_DEV0_EPF0_VF3_GFXMSIX_VECT3_MSG_DATA 0x040e #define mmRCC_DEV0_EPF0_VF3_GFXMSIX_VECT3_MSG_DATA_BASE_IDX 3 #define mmRCC_DEV0_EPF0_VF3_GFXMSIX_VECT3_CONTROL 0x040f #define mmRCC_DEV0_EPF0_VF3_GFXMSIX_VECT3_CONTROL_BASE_IDX 3 #define mmRCC_DEV0_EPF0_VF3_GFXMSIX_PBA 0x0800 #define mmRCC_DEV0_EPF0_VF3_GFXMSIX_PBA_BASE_IDX 3 // addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf4_SYSPFVFDEC // base address: 0x0 #define mmBIF_BX_DEV0_EPF0_VF4_MM_INDEX 0x0000 #define mmBIF_BX_DEV0_EPF0_VF4_MM_INDEX_BASE_IDX 0 #define mmBIF_BX_DEV0_EPF0_VF4_MM_DATA 0x0001 #define mmBIF_BX_DEV0_EPF0_VF4_MM_DATA_BASE_IDX 0 #define mmBIF_BX_DEV0_EPF0_VF4_MM_INDEX_HI 0x0006 #define mmBIF_BX_DEV0_EPF0_VF4_MM_INDEX_HI_BASE_IDX 0 // addressBlock: nbio_nbif0_rcc_dev0_epf0_vf4_BIFPFVFDEC1 // base address: 0x0 #define mmRCC_DEV0_EPF0_VF4_RCC_ERR_LOG 0x0085 #define mmRCC_DEV0_EPF0_VF4_RCC_ERR_LOG_BASE_IDX 2 #define mmRCC_DEV0_EPF0_VF4_RCC_DOORBELL_APER_EN 0x00c0 #define mmRCC_DEV0_EPF0_VF4_RCC_DOORBELL_APER_EN_BASE_IDX 2 #define mmRCC_DEV0_EPF0_VF4_RCC_CONFIG_MEMSIZE 0x00c3 #define mmRCC_DEV0_EPF0_VF4_RCC_CONFIG_MEMSIZE_BASE_IDX 2 #define mmRCC_DEV0_EPF0_VF4_RCC_CONFIG_RESERVED 0x00c4 #define mmRCC_DEV0_EPF0_VF4_RCC_CONFIG_RESERVED_BASE_IDX 2 #define mmRCC_DEV0_EPF0_VF4_RCC_IOV_FUNC_IDENTIFIER 0x00c5 #define mmRCC_DEV0_EPF0_VF4_RCC_IOV_FUNC_IDENTIFIER_BASE_IDX 2 // addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf4_BIFPFVFDEC1 // base address: 0x0 #define mmBIF_BX_DEV0_EPF0_VF4_BIF_BME_STATUS 0x00eb #define mmBIF_BX_DEV0_EPF0_VF4_BIF_BME_STATUS_BASE_IDX 2 #define mmBIF_BX_DEV0_EPF0_VF4_BIF_ATOMIC_ERR_LOG 0x00ec #define mmBIF_BX_DEV0_EPF0_VF4_BIF_ATOMIC_ERR_LOG_BASE_IDX 2 #define mmBIF_BX_DEV0_EPF0_VF4_DOORBELL_SELFRING_GPA_APER_BASE_HIGH 0x00f3 #define your_sha256_hash_IDX 2 #define mmBIF_BX_DEV0_EPF0_VF4_DOORBELL_SELFRING_GPA_APER_BASE_LOW 0x00f4 #define your_sha256_hashIDX 2 #define mmBIF_BX_DEV0_EPF0_VF4_DOORBELL_SELFRING_GPA_APER_CNTL 0x00f5 #define mmBIF_BX_DEV0_EPF0_VF4_DOORBELL_SELFRING_GPA_APER_CNTL_BASE_IDX 2 #define mmBIF_BX_DEV0_EPF0_VF4_HDP_REG_COHERENCY_FLUSH_CNTL 0x00f6 #define mmBIF_BX_DEV0_EPF0_VF4_HDP_REG_COHERENCY_FLUSH_CNTL_BASE_IDX 2 #define mmBIF_BX_DEV0_EPF0_VF4_HDP_MEM_COHERENCY_FLUSH_CNTL 0x00f7 #define mmBIF_BX_DEV0_EPF0_VF4_HDP_MEM_COHERENCY_FLUSH_CNTL_BASE_IDX 2 #define mmBIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_REQ 0x0106 #define mmBIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_REQ_BASE_IDX 2 #define mmBIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_DONE 0x0107 #define mmBIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_DONE_BASE_IDX 2 #define mmBIF_BX_DEV0_EPF0_VF4_BIF_TRANS_PENDING 0x0108 #define mmBIF_BX_DEV0_EPF0_VF4_BIF_TRANS_PENDING_BASE_IDX 2 #define mmBIF_BX_DEV0_EPF0_VF4_NBIF_GFX_ADDR_LUT_BYPASS 0x0112 #define mmBIF_BX_DEV0_EPF0_VF4_NBIF_GFX_ADDR_LUT_BYPASS_BASE_IDX 2 #define mmBIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_TRN_DW0 0x0136 #define mmBIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_TRN_DW0_BASE_IDX 2 #define mmBIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_TRN_DW1 0x0137 #define mmBIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_TRN_DW1_BASE_IDX 2 #define mmBIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_TRN_DW2 0x0138 #define mmBIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_TRN_DW2_BASE_IDX 2 #define mmBIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_TRN_DW3 0x0139 #define mmBIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_TRN_DW3_BASE_IDX 2 #define mmBIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_RCV_DW0 0x013a #define mmBIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_RCV_DW0_BASE_IDX 2 #define mmBIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_RCV_DW1 0x013b #define mmBIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_RCV_DW1_BASE_IDX 2 #define mmBIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_RCV_DW2 0x013c #define mmBIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_RCV_DW2_BASE_IDX 2 #define mmBIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_RCV_DW3 0x013d #define mmBIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_RCV_DW3_BASE_IDX 2 #define mmBIF_BX_DEV0_EPF0_VF4_MAILBOX_CONTROL 0x013e #define mmBIF_BX_DEV0_EPF0_VF4_MAILBOX_CONTROL_BASE_IDX 2 #define mmBIF_BX_DEV0_EPF0_VF4_MAILBOX_INT_CNTL 0x013f #define mmBIF_BX_DEV0_EPF0_VF4_MAILBOX_INT_CNTL_BASE_IDX 2 #define mmBIF_BX_DEV0_EPF0_VF4_BIF_VMHV_MAILBOX 0x0140 #define mmBIF_BX_DEV0_EPF0_VF4_BIF_VMHV_MAILBOX_BASE_IDX 2 // addressBlock: nbio_nbif0_rcc_dev0_epf0_vf4_BIFDEC2 // base address: 0x0 #define mmRCC_DEV0_EPF0_VF4_GFXMSIX_VECT0_ADDR_LO 0x0400 #define mmRCC_DEV0_EPF0_VF4_GFXMSIX_VECT0_ADDR_LO_BASE_IDX 3 #define mmRCC_DEV0_EPF0_VF4_GFXMSIX_VECT0_ADDR_HI 0x0401 #define mmRCC_DEV0_EPF0_VF4_GFXMSIX_VECT0_ADDR_HI_BASE_IDX 3 #define mmRCC_DEV0_EPF0_VF4_GFXMSIX_VECT0_MSG_DATA 0x0402 #define mmRCC_DEV0_EPF0_VF4_GFXMSIX_VECT0_MSG_DATA_BASE_IDX 3 #define mmRCC_DEV0_EPF0_VF4_GFXMSIX_VECT0_CONTROL 0x0403 #define mmRCC_DEV0_EPF0_VF4_GFXMSIX_VECT0_CONTROL_BASE_IDX 3 #define mmRCC_DEV0_EPF0_VF4_GFXMSIX_VECT1_ADDR_LO 0x0404 #define mmRCC_DEV0_EPF0_VF4_GFXMSIX_VECT1_ADDR_LO_BASE_IDX 3 #define mmRCC_DEV0_EPF0_VF4_GFXMSIX_VECT1_ADDR_HI 0x0405 #define mmRCC_DEV0_EPF0_VF4_GFXMSIX_VECT1_ADDR_HI_BASE_IDX 3 #define mmRCC_DEV0_EPF0_VF4_GFXMSIX_VECT1_MSG_DATA 0x0406 #define mmRCC_DEV0_EPF0_VF4_GFXMSIX_VECT1_MSG_DATA_BASE_IDX 3 #define mmRCC_DEV0_EPF0_VF4_GFXMSIX_VECT1_CONTROL 0x0407 #define mmRCC_DEV0_EPF0_VF4_GFXMSIX_VECT1_CONTROL_BASE_IDX 3 #define mmRCC_DEV0_EPF0_VF4_GFXMSIX_VECT2_ADDR_LO 0x0408 #define mmRCC_DEV0_EPF0_VF4_GFXMSIX_VECT2_ADDR_LO_BASE_IDX 3 #define mmRCC_DEV0_EPF0_VF4_GFXMSIX_VECT2_ADDR_HI 0x0409 #define mmRCC_DEV0_EPF0_VF4_GFXMSIX_VECT2_ADDR_HI_BASE_IDX 3 #define mmRCC_DEV0_EPF0_VF4_GFXMSIX_VECT2_MSG_DATA 0x040a #define mmRCC_DEV0_EPF0_VF4_GFXMSIX_VECT2_MSG_DATA_BASE_IDX 3 #define mmRCC_DEV0_EPF0_VF4_GFXMSIX_VECT2_CONTROL 0x040b #define mmRCC_DEV0_EPF0_VF4_GFXMSIX_VECT2_CONTROL_BASE_IDX 3 #define mmRCC_DEV0_EPF0_VF4_GFXMSIX_VECT3_ADDR_LO 0x040c #define mmRCC_DEV0_EPF0_VF4_GFXMSIX_VECT3_ADDR_LO_BASE_IDX 3 #define mmRCC_DEV0_EPF0_VF4_GFXMSIX_VECT3_ADDR_HI 0x040d #define mmRCC_DEV0_EPF0_VF4_GFXMSIX_VECT3_ADDR_HI_BASE_IDX 3 #define mmRCC_DEV0_EPF0_VF4_GFXMSIX_VECT3_MSG_DATA 0x040e #define mmRCC_DEV0_EPF0_VF4_GFXMSIX_VECT3_MSG_DATA_BASE_IDX 3 #define mmRCC_DEV0_EPF0_VF4_GFXMSIX_VECT3_CONTROL 0x040f #define mmRCC_DEV0_EPF0_VF4_GFXMSIX_VECT3_CONTROL_BASE_IDX 3 #define mmRCC_DEV0_EPF0_VF4_GFXMSIX_PBA 0x0800 #define mmRCC_DEV0_EPF0_VF4_GFXMSIX_PBA_BASE_IDX 3 // addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf5_SYSPFVFDEC // base address: 0x0 #define mmBIF_BX_DEV0_EPF0_VF5_MM_INDEX 0x0000 #define mmBIF_BX_DEV0_EPF0_VF5_MM_INDEX_BASE_IDX 0 #define mmBIF_BX_DEV0_EPF0_VF5_MM_DATA 0x0001 #define mmBIF_BX_DEV0_EPF0_VF5_MM_DATA_BASE_IDX 0 #define mmBIF_BX_DEV0_EPF0_VF5_MM_INDEX_HI 0x0006 #define mmBIF_BX_DEV0_EPF0_VF5_MM_INDEX_HI_BASE_IDX 0 // addressBlock: nbio_nbif0_rcc_dev0_epf0_vf5_BIFPFVFDEC1 // base address: 0x0 #define mmRCC_DEV0_EPF0_VF5_RCC_ERR_LOG 0x0085 #define mmRCC_DEV0_EPF0_VF5_RCC_ERR_LOG_BASE_IDX 2 #define mmRCC_DEV0_EPF0_VF5_RCC_DOORBELL_APER_EN 0x00c0 #define mmRCC_DEV0_EPF0_VF5_RCC_DOORBELL_APER_EN_BASE_IDX 2 #define mmRCC_DEV0_EPF0_VF5_RCC_CONFIG_MEMSIZE 0x00c3 #define mmRCC_DEV0_EPF0_VF5_RCC_CONFIG_MEMSIZE_BASE_IDX 2 #define mmRCC_DEV0_EPF0_VF5_RCC_CONFIG_RESERVED 0x00c4 #define mmRCC_DEV0_EPF0_VF5_RCC_CONFIG_RESERVED_BASE_IDX 2 #define mmRCC_DEV0_EPF0_VF5_RCC_IOV_FUNC_IDENTIFIER 0x00c5 #define mmRCC_DEV0_EPF0_VF5_RCC_IOV_FUNC_IDENTIFIER_BASE_IDX 2 // addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf5_BIFPFVFDEC1 // base address: 0x0 #define mmBIF_BX_DEV0_EPF0_VF5_BIF_BME_STATUS 0x00eb #define mmBIF_BX_DEV0_EPF0_VF5_BIF_BME_STATUS_BASE_IDX 2 #define mmBIF_BX_DEV0_EPF0_VF5_BIF_ATOMIC_ERR_LOG 0x00ec #define mmBIF_BX_DEV0_EPF0_VF5_BIF_ATOMIC_ERR_LOG_BASE_IDX 2 #define mmBIF_BX_DEV0_EPF0_VF5_DOORBELL_SELFRING_GPA_APER_BASE_HIGH 0x00f3 #define your_sha256_hash_IDX 2 #define mmBIF_BX_DEV0_EPF0_VF5_DOORBELL_SELFRING_GPA_APER_BASE_LOW 0x00f4 #define your_sha256_hashIDX 2 #define mmBIF_BX_DEV0_EPF0_VF5_DOORBELL_SELFRING_GPA_APER_CNTL 0x00f5 #define mmBIF_BX_DEV0_EPF0_VF5_DOORBELL_SELFRING_GPA_APER_CNTL_BASE_IDX 2 #define mmBIF_BX_DEV0_EPF0_VF5_HDP_REG_COHERENCY_FLUSH_CNTL 0x00f6 #define mmBIF_BX_DEV0_EPF0_VF5_HDP_REG_COHERENCY_FLUSH_CNTL_BASE_IDX 2 #define mmBIF_BX_DEV0_EPF0_VF5_HDP_MEM_COHERENCY_FLUSH_CNTL 0x00f7 #define mmBIF_BX_DEV0_EPF0_VF5_HDP_MEM_COHERENCY_FLUSH_CNTL_BASE_IDX 2 #define mmBIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_REQ 0x0106 #define mmBIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_REQ_BASE_IDX 2 #define mmBIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_DONE 0x0107 #define mmBIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_DONE_BASE_IDX 2 #define mmBIF_BX_DEV0_EPF0_VF5_BIF_TRANS_PENDING 0x0108 #define mmBIF_BX_DEV0_EPF0_VF5_BIF_TRANS_PENDING_BASE_IDX 2 #define mmBIF_BX_DEV0_EPF0_VF5_NBIF_GFX_ADDR_LUT_BYPASS 0x0112 #define mmBIF_BX_DEV0_EPF0_VF5_NBIF_GFX_ADDR_LUT_BYPASS_BASE_IDX 2 #define mmBIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_TRN_DW0 0x0136 #define mmBIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_TRN_DW0_BASE_IDX 2 #define mmBIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_TRN_DW1 0x0137 #define mmBIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_TRN_DW1_BASE_IDX 2 #define mmBIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_TRN_DW2 0x0138 #define mmBIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_TRN_DW2_BASE_IDX 2 #define mmBIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_TRN_DW3 0x0139 #define mmBIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_TRN_DW3_BASE_IDX 2 #define mmBIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_RCV_DW0 0x013a #define mmBIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_RCV_DW0_BASE_IDX 2 #define mmBIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_RCV_DW1 0x013b #define mmBIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_RCV_DW1_BASE_IDX 2 #define mmBIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_RCV_DW2 0x013c #define mmBIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_RCV_DW2_BASE_IDX 2 #define mmBIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_RCV_DW3 0x013d #define mmBIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_RCV_DW3_BASE_IDX 2 #define mmBIF_BX_DEV0_EPF0_VF5_MAILBOX_CONTROL 0x013e #define mmBIF_BX_DEV0_EPF0_VF5_MAILBOX_CONTROL_BASE_IDX 2 #define mmBIF_BX_DEV0_EPF0_VF5_MAILBOX_INT_CNTL 0x013f #define mmBIF_BX_DEV0_EPF0_VF5_MAILBOX_INT_CNTL_BASE_IDX 2 #define mmBIF_BX_DEV0_EPF0_VF5_BIF_VMHV_MAILBOX 0x0140 #define mmBIF_BX_DEV0_EPF0_VF5_BIF_VMHV_MAILBOX_BASE_IDX 2 // addressBlock: nbio_nbif0_rcc_dev0_epf0_vf5_BIFDEC2 // base address: 0x0 #define mmRCC_DEV0_EPF0_VF5_GFXMSIX_VECT0_ADDR_LO 0x0400 #define mmRCC_DEV0_EPF0_VF5_GFXMSIX_VECT0_ADDR_LO_BASE_IDX 3 #define mmRCC_DEV0_EPF0_VF5_GFXMSIX_VECT0_ADDR_HI 0x0401 #define mmRCC_DEV0_EPF0_VF5_GFXMSIX_VECT0_ADDR_HI_BASE_IDX 3 #define mmRCC_DEV0_EPF0_VF5_GFXMSIX_VECT0_MSG_DATA 0x0402 #define mmRCC_DEV0_EPF0_VF5_GFXMSIX_VECT0_MSG_DATA_BASE_IDX 3 #define mmRCC_DEV0_EPF0_VF5_GFXMSIX_VECT0_CONTROL 0x0403 #define mmRCC_DEV0_EPF0_VF5_GFXMSIX_VECT0_CONTROL_BASE_IDX 3 #define mmRCC_DEV0_EPF0_VF5_GFXMSIX_VECT1_ADDR_LO 0x0404 #define mmRCC_DEV0_EPF0_VF5_GFXMSIX_VECT1_ADDR_LO_BASE_IDX 3 #define mmRCC_DEV0_EPF0_VF5_GFXMSIX_VECT1_ADDR_HI 0x0405 #define mmRCC_DEV0_EPF0_VF5_GFXMSIX_VECT1_ADDR_HI_BASE_IDX 3 #define mmRCC_DEV0_EPF0_VF5_GFXMSIX_VECT1_MSG_DATA 0x0406 #define mmRCC_DEV0_EPF0_VF5_GFXMSIX_VECT1_MSG_DATA_BASE_IDX 3 #define mmRCC_DEV0_EPF0_VF5_GFXMSIX_VECT1_CONTROL 0x0407 #define mmRCC_DEV0_EPF0_VF5_GFXMSIX_VECT1_CONTROL_BASE_IDX 3 #define mmRCC_DEV0_EPF0_VF5_GFXMSIX_VECT2_ADDR_LO 0x0408 #define mmRCC_DEV0_EPF0_VF5_GFXMSIX_VECT2_ADDR_LO_BASE_IDX 3 #define mmRCC_DEV0_EPF0_VF5_GFXMSIX_VECT2_ADDR_HI 0x0409 #define mmRCC_DEV0_EPF0_VF5_GFXMSIX_VECT2_ADDR_HI_BASE_IDX 3 #define mmRCC_DEV0_EPF0_VF5_GFXMSIX_VECT2_MSG_DATA 0x040a #define mmRCC_DEV0_EPF0_VF5_GFXMSIX_VECT2_MSG_DATA_BASE_IDX 3 #define mmRCC_DEV0_EPF0_VF5_GFXMSIX_VECT2_CONTROL 0x040b #define mmRCC_DEV0_EPF0_VF5_GFXMSIX_VECT2_CONTROL_BASE_IDX 3 #define mmRCC_DEV0_EPF0_VF5_GFXMSIX_VECT3_ADDR_LO 0x040c #define mmRCC_DEV0_EPF0_VF5_GFXMSIX_VECT3_ADDR_LO_BASE_IDX 3 #define mmRCC_DEV0_EPF0_VF5_GFXMSIX_VECT3_ADDR_HI 0x040d #define mmRCC_DEV0_EPF0_VF5_GFXMSIX_VECT3_ADDR_HI_BASE_IDX 3 #define mmRCC_DEV0_EPF0_VF5_GFXMSIX_VECT3_MSG_DATA 0x040e #define mmRCC_DEV0_EPF0_VF5_GFXMSIX_VECT3_MSG_DATA_BASE_IDX 3 #define mmRCC_DEV0_EPF0_VF5_GFXMSIX_VECT3_CONTROL 0x040f #define mmRCC_DEV0_EPF0_VF5_GFXMSIX_VECT3_CONTROL_BASE_IDX 3 #define mmRCC_DEV0_EPF0_VF5_GFXMSIX_PBA 0x0800 #define mmRCC_DEV0_EPF0_VF5_GFXMSIX_PBA_BASE_IDX 3 // addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf6_SYSPFVFDEC // base address: 0x0 #define mmBIF_BX_DEV0_EPF0_VF6_MM_INDEX 0x0000 #define mmBIF_BX_DEV0_EPF0_VF6_MM_INDEX_BASE_IDX 0 #define mmBIF_BX_DEV0_EPF0_VF6_MM_DATA 0x0001 #define mmBIF_BX_DEV0_EPF0_VF6_MM_DATA_BASE_IDX 0 #define mmBIF_BX_DEV0_EPF0_VF6_MM_INDEX_HI 0x0006 #define mmBIF_BX_DEV0_EPF0_VF6_MM_INDEX_HI_BASE_IDX 0 // addressBlock: nbio_nbif0_rcc_dev0_epf0_vf6_BIFPFVFDEC1 // base address: 0x0 #define mmRCC_DEV0_EPF0_VF6_RCC_ERR_LOG 0x0085 #define mmRCC_DEV0_EPF0_VF6_RCC_ERR_LOG_BASE_IDX 2 #define mmRCC_DEV0_EPF0_VF6_RCC_DOORBELL_APER_EN 0x00c0 #define mmRCC_DEV0_EPF0_VF6_RCC_DOORBELL_APER_EN_BASE_IDX 2 #define mmRCC_DEV0_EPF0_VF6_RCC_CONFIG_MEMSIZE 0x00c3 #define mmRCC_DEV0_EPF0_VF6_RCC_CONFIG_MEMSIZE_BASE_IDX 2 #define mmRCC_DEV0_EPF0_VF6_RCC_CONFIG_RESERVED 0x00c4 #define mmRCC_DEV0_EPF0_VF6_RCC_CONFIG_RESERVED_BASE_IDX 2 #define mmRCC_DEV0_EPF0_VF6_RCC_IOV_FUNC_IDENTIFIER 0x00c5 #define mmRCC_DEV0_EPF0_VF6_RCC_IOV_FUNC_IDENTIFIER_BASE_IDX 2 // addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf6_BIFPFVFDEC1 // base address: 0x0 #define mmBIF_BX_DEV0_EPF0_VF6_BIF_BME_STATUS 0x00eb #define mmBIF_BX_DEV0_EPF0_VF6_BIF_BME_STATUS_BASE_IDX 2 #define mmBIF_BX_DEV0_EPF0_VF6_BIF_ATOMIC_ERR_LOG 0x00ec #define mmBIF_BX_DEV0_EPF0_VF6_BIF_ATOMIC_ERR_LOG_BASE_IDX 2 #define mmBIF_BX_DEV0_EPF0_VF6_DOORBELL_SELFRING_GPA_APER_BASE_HIGH 0x00f3 #define your_sha256_hash_IDX 2 #define mmBIF_BX_DEV0_EPF0_VF6_DOORBELL_SELFRING_GPA_APER_BASE_LOW 0x00f4 #define your_sha256_hashIDX 2 #define mmBIF_BX_DEV0_EPF0_VF6_DOORBELL_SELFRING_GPA_APER_CNTL 0x00f5 #define mmBIF_BX_DEV0_EPF0_VF6_DOORBELL_SELFRING_GPA_APER_CNTL_BASE_IDX 2 #define mmBIF_BX_DEV0_EPF0_VF6_HDP_REG_COHERENCY_FLUSH_CNTL 0x00f6 #define mmBIF_BX_DEV0_EPF0_VF6_HDP_REG_COHERENCY_FLUSH_CNTL_BASE_IDX 2 #define mmBIF_BX_DEV0_EPF0_VF6_HDP_MEM_COHERENCY_FLUSH_CNTL 0x00f7 #define mmBIF_BX_DEV0_EPF0_VF6_HDP_MEM_COHERENCY_FLUSH_CNTL_BASE_IDX 2 #define mmBIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_REQ 0x0106 #define mmBIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_REQ_BASE_IDX 2 #define mmBIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_DONE 0x0107 #define mmBIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_DONE_BASE_IDX 2 #define mmBIF_BX_DEV0_EPF0_VF6_BIF_TRANS_PENDING 0x0108 #define mmBIF_BX_DEV0_EPF0_VF6_BIF_TRANS_PENDING_BASE_IDX 2 #define mmBIF_BX_DEV0_EPF0_VF6_NBIF_GFX_ADDR_LUT_BYPASS 0x0112 #define mmBIF_BX_DEV0_EPF0_VF6_NBIF_GFX_ADDR_LUT_BYPASS_BASE_IDX 2 #define mmBIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_TRN_DW0 0x0136 #define mmBIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_TRN_DW0_BASE_IDX 2 #define mmBIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_TRN_DW1 0x0137 #define mmBIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_TRN_DW1_BASE_IDX 2 #define mmBIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_TRN_DW2 0x0138 #define mmBIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_TRN_DW2_BASE_IDX 2 #define mmBIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_TRN_DW3 0x0139 #define mmBIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_TRN_DW3_BASE_IDX 2 #define mmBIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_RCV_DW0 0x013a #define mmBIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_RCV_DW0_BASE_IDX 2 #define mmBIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_RCV_DW1 0x013b #define mmBIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_RCV_DW1_BASE_IDX 2 #define mmBIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_RCV_DW2 0x013c #define mmBIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_RCV_DW2_BASE_IDX 2 #define mmBIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_RCV_DW3 0x013d #define mmBIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_RCV_DW3_BASE_IDX 2 #define mmBIF_BX_DEV0_EPF0_VF6_MAILBOX_CONTROL 0x013e #define mmBIF_BX_DEV0_EPF0_VF6_MAILBOX_CONTROL_BASE_IDX 2 #define mmBIF_BX_DEV0_EPF0_VF6_MAILBOX_INT_CNTL 0x013f #define mmBIF_BX_DEV0_EPF0_VF6_MAILBOX_INT_CNTL_BASE_IDX 2 #define mmBIF_BX_DEV0_EPF0_VF6_BIF_VMHV_MAILBOX 0x0140 #define mmBIF_BX_DEV0_EPF0_VF6_BIF_VMHV_MAILBOX_BASE_IDX 2 // addressBlock: nbio_nbif0_rcc_dev0_epf0_vf6_BIFDEC2 // base address: 0x0 #define mmRCC_DEV0_EPF0_VF6_GFXMSIX_VECT0_ADDR_LO 0x0400 #define mmRCC_DEV0_EPF0_VF6_GFXMSIX_VECT0_ADDR_LO_BASE_IDX 3 #define mmRCC_DEV0_EPF0_VF6_GFXMSIX_VECT0_ADDR_HI 0x0401 #define mmRCC_DEV0_EPF0_VF6_GFXMSIX_VECT0_ADDR_HI_BASE_IDX 3 #define mmRCC_DEV0_EPF0_VF6_GFXMSIX_VECT0_MSG_DATA 0x0402 #define mmRCC_DEV0_EPF0_VF6_GFXMSIX_VECT0_MSG_DATA_BASE_IDX 3 #define mmRCC_DEV0_EPF0_VF6_GFXMSIX_VECT0_CONTROL 0x0403 #define mmRCC_DEV0_EPF0_VF6_GFXMSIX_VECT0_CONTROL_BASE_IDX 3 #define mmRCC_DEV0_EPF0_VF6_GFXMSIX_VECT1_ADDR_LO 0x0404 #define mmRCC_DEV0_EPF0_VF6_GFXMSIX_VECT1_ADDR_LO_BASE_IDX 3 #define mmRCC_DEV0_EPF0_VF6_GFXMSIX_VECT1_ADDR_HI 0x0405 #define mmRCC_DEV0_EPF0_VF6_GFXMSIX_VECT1_ADDR_HI_BASE_IDX 3 #define mmRCC_DEV0_EPF0_VF6_GFXMSIX_VECT1_MSG_DATA 0x0406 #define mmRCC_DEV0_EPF0_VF6_GFXMSIX_VECT1_MSG_DATA_BASE_IDX 3 #define mmRCC_DEV0_EPF0_VF6_GFXMSIX_VECT1_CONTROL 0x0407 #define mmRCC_DEV0_EPF0_VF6_GFXMSIX_VECT1_CONTROL_BASE_IDX 3 #define mmRCC_DEV0_EPF0_VF6_GFXMSIX_VECT2_ADDR_LO 0x0408 #define mmRCC_DEV0_EPF0_VF6_GFXMSIX_VECT2_ADDR_LO_BASE_IDX 3 #define mmRCC_DEV0_EPF0_VF6_GFXMSIX_VECT2_ADDR_HI 0x0409 #define mmRCC_DEV0_EPF0_VF6_GFXMSIX_VECT2_ADDR_HI_BASE_IDX 3 #define mmRCC_DEV0_EPF0_VF6_GFXMSIX_VECT2_MSG_DATA 0x040a #define mmRCC_DEV0_EPF0_VF6_GFXMSIX_VECT2_MSG_DATA_BASE_IDX 3 #define mmRCC_DEV0_EPF0_VF6_GFXMSIX_VECT2_CONTROL 0x040b #define mmRCC_DEV0_EPF0_VF6_GFXMSIX_VECT2_CONTROL_BASE_IDX 3 #define mmRCC_DEV0_EPF0_VF6_GFXMSIX_VECT3_ADDR_LO 0x040c #define mmRCC_DEV0_EPF0_VF6_GFXMSIX_VECT3_ADDR_LO_BASE_IDX 3 #define mmRCC_DEV0_EPF0_VF6_GFXMSIX_VECT3_ADDR_HI 0x040d #define mmRCC_DEV0_EPF0_VF6_GFXMSIX_VECT3_ADDR_HI_BASE_IDX 3 #define mmRCC_DEV0_EPF0_VF6_GFXMSIX_VECT3_MSG_DATA 0x040e #define mmRCC_DEV0_EPF0_VF6_GFXMSIX_VECT3_MSG_DATA_BASE_IDX 3 #define mmRCC_DEV0_EPF0_VF6_GFXMSIX_VECT3_CONTROL 0x040f #define mmRCC_DEV0_EPF0_VF6_GFXMSIX_VECT3_CONTROL_BASE_IDX 3 #define mmRCC_DEV0_EPF0_VF6_GFXMSIX_PBA 0x0800 #define mmRCC_DEV0_EPF0_VF6_GFXMSIX_PBA_BASE_IDX 3 // addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf7_SYSPFVFDEC // base address: 0x0 #define mmBIF_BX_DEV0_EPF0_VF7_MM_INDEX 0x0000 #define mmBIF_BX_DEV0_EPF0_VF7_MM_INDEX_BASE_IDX 0 #define mmBIF_BX_DEV0_EPF0_VF7_MM_DATA 0x0001 #define mmBIF_BX_DEV0_EPF0_VF7_MM_DATA_BASE_IDX 0 #define mmBIF_BX_DEV0_EPF0_VF7_MM_INDEX_HI 0x0006 #define mmBIF_BX_DEV0_EPF0_VF7_MM_INDEX_HI_BASE_IDX 0 // addressBlock: nbio_nbif0_rcc_dev0_epf0_vf7_BIFPFVFDEC1 // base address: 0x0 #define mmRCC_DEV0_EPF0_VF7_RCC_ERR_LOG 0x0085 #define mmRCC_DEV0_EPF0_VF7_RCC_ERR_LOG_BASE_IDX 2 #define mmRCC_DEV0_EPF0_VF7_RCC_DOORBELL_APER_EN 0x00c0 #define mmRCC_DEV0_EPF0_VF7_RCC_DOORBELL_APER_EN_BASE_IDX 2 #define mmRCC_DEV0_EPF0_VF7_RCC_CONFIG_MEMSIZE 0x00c3 #define mmRCC_DEV0_EPF0_VF7_RCC_CONFIG_MEMSIZE_BASE_IDX 2 #define mmRCC_DEV0_EPF0_VF7_RCC_CONFIG_RESERVED 0x00c4 #define mmRCC_DEV0_EPF0_VF7_RCC_CONFIG_RESERVED_BASE_IDX 2 #define mmRCC_DEV0_EPF0_VF7_RCC_IOV_FUNC_IDENTIFIER 0x00c5 #define mmRCC_DEV0_EPF0_VF7_RCC_IOV_FUNC_IDENTIFIER_BASE_IDX 2 // addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf7_BIFPFVFDEC1 // base address: 0x0 #define mmBIF_BX_DEV0_EPF0_VF7_BIF_BME_STATUS 0x00eb #define mmBIF_BX_DEV0_EPF0_VF7_BIF_BME_STATUS_BASE_IDX 2 #define mmBIF_BX_DEV0_EPF0_VF7_BIF_ATOMIC_ERR_LOG 0x00ec #define mmBIF_BX_DEV0_EPF0_VF7_BIF_ATOMIC_ERR_LOG_BASE_IDX 2 #define mmBIF_BX_DEV0_EPF0_VF7_DOORBELL_SELFRING_GPA_APER_BASE_HIGH 0x00f3 #define your_sha256_hash_IDX 2 #define mmBIF_BX_DEV0_EPF0_VF7_DOORBELL_SELFRING_GPA_APER_BASE_LOW 0x00f4 #define your_sha256_hashIDX 2 #define mmBIF_BX_DEV0_EPF0_VF7_DOORBELL_SELFRING_GPA_APER_CNTL 0x00f5 #define mmBIF_BX_DEV0_EPF0_VF7_DOORBELL_SELFRING_GPA_APER_CNTL_BASE_IDX 2 #define mmBIF_BX_DEV0_EPF0_VF7_HDP_REG_COHERENCY_FLUSH_CNTL 0x00f6 #define mmBIF_BX_DEV0_EPF0_VF7_HDP_REG_COHERENCY_FLUSH_CNTL_BASE_IDX 2 #define mmBIF_BX_DEV0_EPF0_VF7_HDP_MEM_COHERENCY_FLUSH_CNTL 0x00f7 #define mmBIF_BX_DEV0_EPF0_VF7_HDP_MEM_COHERENCY_FLUSH_CNTL_BASE_IDX 2 #define mmBIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_REQ 0x0106 #define mmBIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_REQ_BASE_IDX 2 #define mmBIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_DONE 0x0107 #define mmBIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_DONE_BASE_IDX 2 #define mmBIF_BX_DEV0_EPF0_VF7_BIF_TRANS_PENDING 0x0108 #define mmBIF_BX_DEV0_EPF0_VF7_BIF_TRANS_PENDING_BASE_IDX 2 #define mmBIF_BX_DEV0_EPF0_VF7_NBIF_GFX_ADDR_LUT_BYPASS 0x0112 #define mmBIF_BX_DEV0_EPF0_VF7_NBIF_GFX_ADDR_LUT_BYPASS_BASE_IDX 2 #define mmBIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_TRN_DW0 0x0136 #define mmBIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_TRN_DW0_BASE_IDX 2 #define mmBIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_TRN_DW1 0x0137 #define mmBIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_TRN_DW1_BASE_IDX 2 #define mmBIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_TRN_DW2 0x0138 #define mmBIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_TRN_DW2_BASE_IDX 2 #define mmBIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_TRN_DW3 0x0139 #define mmBIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_TRN_DW3_BASE_IDX 2 #define mmBIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_RCV_DW0 0x013a #define mmBIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_RCV_DW0_BASE_IDX 2 #define mmBIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_RCV_DW1 0x013b #define mmBIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_RCV_DW1_BASE_IDX 2 #define mmBIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_RCV_DW2 0x013c #define mmBIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_RCV_DW2_BASE_IDX 2 #define mmBIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_RCV_DW3 0x013d #define mmBIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_RCV_DW3_BASE_IDX 2 #define mmBIF_BX_DEV0_EPF0_VF7_MAILBOX_CONTROL 0x013e #define mmBIF_BX_DEV0_EPF0_VF7_MAILBOX_CONTROL_BASE_IDX 2 #define mmBIF_BX_DEV0_EPF0_VF7_MAILBOX_INT_CNTL 0x013f #define mmBIF_BX_DEV0_EPF0_VF7_MAILBOX_INT_CNTL_BASE_IDX 2 #define mmBIF_BX_DEV0_EPF0_VF7_BIF_VMHV_MAILBOX 0x0140 #define mmBIF_BX_DEV0_EPF0_VF7_BIF_VMHV_MAILBOX_BASE_IDX 2 // addressBlock: nbio_nbif0_rcc_dev0_epf0_vf7_BIFDEC2 // base address: 0x0 #define mmRCC_DEV0_EPF0_VF7_GFXMSIX_VECT0_ADDR_LO 0x0400 #define mmRCC_DEV0_EPF0_VF7_GFXMSIX_VECT0_ADDR_LO_BASE_IDX 3 #define mmRCC_DEV0_EPF0_VF7_GFXMSIX_VECT0_ADDR_HI 0x0401 #define mmRCC_DEV0_EPF0_VF7_GFXMSIX_VECT0_ADDR_HI_BASE_IDX 3 #define mmRCC_DEV0_EPF0_VF7_GFXMSIX_VECT0_MSG_DATA 0x0402 #define mmRCC_DEV0_EPF0_VF7_GFXMSIX_VECT0_MSG_DATA_BASE_IDX 3 #define mmRCC_DEV0_EPF0_VF7_GFXMSIX_VECT0_CONTROL 0x0403 #define mmRCC_DEV0_EPF0_VF7_GFXMSIX_VECT0_CONTROL_BASE_IDX 3 #define mmRCC_DEV0_EPF0_VF7_GFXMSIX_VECT1_ADDR_LO 0x0404 #define mmRCC_DEV0_EPF0_VF7_GFXMSIX_VECT1_ADDR_LO_BASE_IDX 3 #define mmRCC_DEV0_EPF0_VF7_GFXMSIX_VECT1_ADDR_HI 0x0405 #define mmRCC_DEV0_EPF0_VF7_GFXMSIX_VECT1_ADDR_HI_BASE_IDX 3 #define mmRCC_DEV0_EPF0_VF7_GFXMSIX_VECT1_MSG_DATA 0x0406 #define mmRCC_DEV0_EPF0_VF7_GFXMSIX_VECT1_MSG_DATA_BASE_IDX 3 #define mmRCC_DEV0_EPF0_VF7_GFXMSIX_VECT1_CONTROL 0x0407 #define mmRCC_DEV0_EPF0_VF7_GFXMSIX_VECT1_CONTROL_BASE_IDX 3 #define mmRCC_DEV0_EPF0_VF7_GFXMSIX_VECT2_ADDR_LO 0x0408 #define mmRCC_DEV0_EPF0_VF7_GFXMSIX_VECT2_ADDR_LO_BASE_IDX 3 #define mmRCC_DEV0_EPF0_VF7_GFXMSIX_VECT2_ADDR_HI 0x0409 #define mmRCC_DEV0_EPF0_VF7_GFXMSIX_VECT2_ADDR_HI_BASE_IDX 3 #define mmRCC_DEV0_EPF0_VF7_GFXMSIX_VECT2_MSG_DATA 0x040a #define mmRCC_DEV0_EPF0_VF7_GFXMSIX_VECT2_MSG_DATA_BASE_IDX 3 #define mmRCC_DEV0_EPF0_VF7_GFXMSIX_VECT2_CONTROL 0x040b #define mmRCC_DEV0_EPF0_VF7_GFXMSIX_VECT2_CONTROL_BASE_IDX 3 #define mmRCC_DEV0_EPF0_VF7_GFXMSIX_VECT3_ADDR_LO 0x040c #define mmRCC_DEV0_EPF0_VF7_GFXMSIX_VECT3_ADDR_LO_BASE_IDX 3 #define mmRCC_DEV0_EPF0_VF7_GFXMSIX_VECT3_ADDR_HI 0x040d #define mmRCC_DEV0_EPF0_VF7_GFXMSIX_VECT3_ADDR_HI_BASE_IDX 3 #define mmRCC_DEV0_EPF0_VF7_GFXMSIX_VECT3_MSG_DATA 0x040e #define mmRCC_DEV0_EPF0_VF7_GFXMSIX_VECT3_MSG_DATA_BASE_IDX 3 #define mmRCC_DEV0_EPF0_VF7_GFXMSIX_VECT3_CONTROL 0x040f #define mmRCC_DEV0_EPF0_VF7_GFXMSIX_VECT3_CONTROL_BASE_IDX 3 #define mmRCC_DEV0_EPF0_VF7_GFXMSIX_PBA 0x0800 #define mmRCC_DEV0_EPF0_VF7_GFXMSIX_PBA_BASE_IDX 3 // addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf8_SYSPFVFDEC // base address: 0x0 #define mmBIF_BX_DEV0_EPF0_VF8_MM_INDEX 0x0000 #define mmBIF_BX_DEV0_EPF0_VF8_MM_INDEX_BASE_IDX 0 #define mmBIF_BX_DEV0_EPF0_VF8_MM_DATA 0x0001 #define mmBIF_BX_DEV0_EPF0_VF8_MM_DATA_BASE_IDX 0 #define mmBIF_BX_DEV0_EPF0_VF8_MM_INDEX_HI 0x0006 #define mmBIF_BX_DEV0_EPF0_VF8_MM_INDEX_HI_BASE_IDX 0 // addressBlock: nbio_nbif0_rcc_dev0_epf0_vf8_BIFPFVFDEC1 // base address: 0x0 #define mmRCC_DEV0_EPF0_VF8_RCC_ERR_LOG 0x0085 #define mmRCC_DEV0_EPF0_VF8_RCC_ERR_LOG_BASE_IDX 2 #define mmRCC_DEV0_EPF0_VF8_RCC_DOORBELL_APER_EN 0x00c0 #define mmRCC_DEV0_EPF0_VF8_RCC_DOORBELL_APER_EN_BASE_IDX 2 #define mmRCC_DEV0_EPF0_VF8_RCC_CONFIG_MEMSIZE 0x00c3 #define mmRCC_DEV0_EPF0_VF8_RCC_CONFIG_MEMSIZE_BASE_IDX 2 #define mmRCC_DEV0_EPF0_VF8_RCC_CONFIG_RESERVED 0x00c4 #define mmRCC_DEV0_EPF0_VF8_RCC_CONFIG_RESERVED_BASE_IDX 2 #define mmRCC_DEV0_EPF0_VF8_RCC_IOV_FUNC_IDENTIFIER 0x00c5 #define mmRCC_DEV0_EPF0_VF8_RCC_IOV_FUNC_IDENTIFIER_BASE_IDX 2 // addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf8_BIFPFVFDEC1 // base address: 0x0 #define mmBIF_BX_DEV0_EPF0_VF8_BIF_BME_STATUS 0x00eb #define mmBIF_BX_DEV0_EPF0_VF8_BIF_BME_STATUS_BASE_IDX 2 #define mmBIF_BX_DEV0_EPF0_VF8_BIF_ATOMIC_ERR_LOG 0x00ec #define mmBIF_BX_DEV0_EPF0_VF8_BIF_ATOMIC_ERR_LOG_BASE_IDX 2 #define mmBIF_BX_DEV0_EPF0_VF8_DOORBELL_SELFRING_GPA_APER_BASE_HIGH 0x00f3 #define your_sha256_hash_IDX 2 #define mmBIF_BX_DEV0_EPF0_VF8_DOORBELL_SELFRING_GPA_APER_BASE_LOW 0x00f4 #define your_sha256_hashIDX 2 #define mmBIF_BX_DEV0_EPF0_VF8_DOORBELL_SELFRING_GPA_APER_CNTL 0x00f5 #define mmBIF_BX_DEV0_EPF0_VF8_DOORBELL_SELFRING_GPA_APER_CNTL_BASE_IDX 2 #define mmBIF_BX_DEV0_EPF0_VF8_HDP_REG_COHERENCY_FLUSH_CNTL 0x00f6 #define mmBIF_BX_DEV0_EPF0_VF8_HDP_REG_COHERENCY_FLUSH_CNTL_BASE_IDX 2 #define mmBIF_BX_DEV0_EPF0_VF8_HDP_MEM_COHERENCY_FLUSH_CNTL 0x00f7 #define mmBIF_BX_DEV0_EPF0_VF8_HDP_MEM_COHERENCY_FLUSH_CNTL_BASE_IDX 2 #define mmBIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_REQ 0x0106 #define mmBIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_REQ_BASE_IDX 2 #define mmBIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_DONE 0x0107 #define mmBIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_DONE_BASE_IDX 2 #define mmBIF_BX_DEV0_EPF0_VF8_BIF_TRANS_PENDING 0x0108 #define mmBIF_BX_DEV0_EPF0_VF8_BIF_TRANS_PENDING_BASE_IDX 2 #define mmBIF_BX_DEV0_EPF0_VF8_NBIF_GFX_ADDR_LUT_BYPASS 0x0112 #define mmBIF_BX_DEV0_EPF0_VF8_NBIF_GFX_ADDR_LUT_BYPASS_BASE_IDX 2 #define mmBIF_BX_DEV0_EPF0_VF8_MAILBOX_MSGBUF_TRN_DW0 0x0136 #define mmBIF_BX_DEV0_EPF0_VF8_MAILBOX_MSGBUF_TRN_DW0_BASE_IDX 2 #define mmBIF_BX_DEV0_EPF0_VF8_MAILBOX_MSGBUF_TRN_DW1 0x0137 #define mmBIF_BX_DEV0_EPF0_VF8_MAILBOX_MSGBUF_TRN_DW1_BASE_IDX 2 #define mmBIF_BX_DEV0_EPF0_VF8_MAILBOX_MSGBUF_TRN_DW2 0x0138 #define mmBIF_BX_DEV0_EPF0_VF8_MAILBOX_MSGBUF_TRN_DW2_BASE_IDX 2 #define mmBIF_BX_DEV0_EPF0_VF8_MAILBOX_MSGBUF_TRN_DW3 0x0139 #define mmBIF_BX_DEV0_EPF0_VF8_MAILBOX_MSGBUF_TRN_DW3_BASE_IDX 2 #define mmBIF_BX_DEV0_EPF0_VF8_MAILBOX_MSGBUF_RCV_DW0 0x013a #define mmBIF_BX_DEV0_EPF0_VF8_MAILBOX_MSGBUF_RCV_DW0_BASE_IDX 2 #define mmBIF_BX_DEV0_EPF0_VF8_MAILBOX_MSGBUF_RCV_DW1 0x013b #define mmBIF_BX_DEV0_EPF0_VF8_MAILBOX_MSGBUF_RCV_DW1_BASE_IDX 2 #define mmBIF_BX_DEV0_EPF0_VF8_MAILBOX_MSGBUF_RCV_DW2 0x013c #define mmBIF_BX_DEV0_EPF0_VF8_MAILBOX_MSGBUF_RCV_DW2_BASE_IDX 2 #define mmBIF_BX_DEV0_EPF0_VF8_MAILBOX_MSGBUF_RCV_DW3 0x013d #define mmBIF_BX_DEV0_EPF0_VF8_MAILBOX_MSGBUF_RCV_DW3_BASE_IDX 2 #define mmBIF_BX_DEV0_EPF0_VF8_MAILBOX_CONTROL 0x013e #define mmBIF_BX_DEV0_EPF0_VF8_MAILBOX_CONTROL_BASE_IDX 2 #define mmBIF_BX_DEV0_EPF0_VF8_MAILBOX_INT_CNTL 0x013f #define mmBIF_BX_DEV0_EPF0_VF8_MAILBOX_INT_CNTL_BASE_IDX 2 #define mmBIF_BX_DEV0_EPF0_VF8_BIF_VMHV_MAILBOX 0x0140 #define mmBIF_BX_DEV0_EPF0_VF8_BIF_VMHV_MAILBOX_BASE_IDX 2 // addressBlock: nbio_nbif0_rcc_dev0_epf0_vf8_BIFDEC2 // base address: 0x0 #define mmRCC_DEV0_EPF0_VF8_GFXMSIX_VECT0_ADDR_LO 0x0400 #define mmRCC_DEV0_EPF0_VF8_GFXMSIX_VECT0_ADDR_LO_BASE_IDX 3 #define mmRCC_DEV0_EPF0_VF8_GFXMSIX_VECT0_ADDR_HI 0x0401 #define mmRCC_DEV0_EPF0_VF8_GFXMSIX_VECT0_ADDR_HI_BASE_IDX 3 #define mmRCC_DEV0_EPF0_VF8_GFXMSIX_VECT0_MSG_DATA 0x0402 #define mmRCC_DEV0_EPF0_VF8_GFXMSIX_VECT0_MSG_DATA_BASE_IDX 3 #define mmRCC_DEV0_EPF0_VF8_GFXMSIX_VECT0_CONTROL 0x0403 #define mmRCC_DEV0_EPF0_VF8_GFXMSIX_VECT0_CONTROL_BASE_IDX 3 #define mmRCC_DEV0_EPF0_VF8_GFXMSIX_VECT1_ADDR_LO 0x0404 #define mmRCC_DEV0_EPF0_VF8_GFXMSIX_VECT1_ADDR_LO_BASE_IDX 3 #define mmRCC_DEV0_EPF0_VF8_GFXMSIX_VECT1_ADDR_HI 0x0405 #define mmRCC_DEV0_EPF0_VF8_GFXMSIX_VECT1_ADDR_HI_BASE_IDX 3 #define mmRCC_DEV0_EPF0_VF8_GFXMSIX_VECT1_MSG_DATA 0x0406 #define mmRCC_DEV0_EPF0_VF8_GFXMSIX_VECT1_MSG_DATA_BASE_IDX 3 #define mmRCC_DEV0_EPF0_VF8_GFXMSIX_VECT1_CONTROL 0x0407 #define mmRCC_DEV0_EPF0_VF8_GFXMSIX_VECT1_CONTROL_BASE_IDX 3 #define mmRCC_DEV0_EPF0_VF8_GFXMSIX_VECT2_ADDR_LO 0x0408 #define mmRCC_DEV0_EPF0_VF8_GFXMSIX_VECT2_ADDR_LO_BASE_IDX 3 #define mmRCC_DEV0_EPF0_VF8_GFXMSIX_VECT2_ADDR_HI 0x0409 #define mmRCC_DEV0_EPF0_VF8_GFXMSIX_VECT2_ADDR_HI_BASE_IDX 3 #define mmRCC_DEV0_EPF0_VF8_GFXMSIX_VECT2_MSG_DATA 0x040a #define mmRCC_DEV0_EPF0_VF8_GFXMSIX_VECT2_MSG_DATA_BASE_IDX 3 #define mmRCC_DEV0_EPF0_VF8_GFXMSIX_VECT2_CONTROL 0x040b #define mmRCC_DEV0_EPF0_VF8_GFXMSIX_VECT2_CONTROL_BASE_IDX 3 #define mmRCC_DEV0_EPF0_VF8_GFXMSIX_VECT3_ADDR_LO 0x040c #define mmRCC_DEV0_EPF0_VF8_GFXMSIX_VECT3_ADDR_LO_BASE_IDX 3 #define mmRCC_DEV0_EPF0_VF8_GFXMSIX_VECT3_ADDR_HI 0x040d #define mmRCC_DEV0_EPF0_VF8_GFXMSIX_VECT3_ADDR_HI_BASE_IDX 3 #define mmRCC_DEV0_EPF0_VF8_GFXMSIX_VECT3_MSG_DATA 0x040e #define mmRCC_DEV0_EPF0_VF8_GFXMSIX_VECT3_MSG_DATA_BASE_IDX 3 #define mmRCC_DEV0_EPF0_VF8_GFXMSIX_VECT3_CONTROL 0x040f #define mmRCC_DEV0_EPF0_VF8_GFXMSIX_VECT3_CONTROL_BASE_IDX 3 #define mmRCC_DEV0_EPF0_VF8_GFXMSIX_PBA 0x0800 #define mmRCC_DEV0_EPF0_VF8_GFXMSIX_PBA_BASE_IDX 3 // addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf9_SYSPFVFDEC // base address: 0x0 #define mmBIF_BX_DEV0_EPF0_VF9_MM_INDEX 0x0000 #define mmBIF_BX_DEV0_EPF0_VF9_MM_INDEX_BASE_IDX 0 #define mmBIF_BX_DEV0_EPF0_VF9_MM_DATA 0x0001 #define mmBIF_BX_DEV0_EPF0_VF9_MM_DATA_BASE_IDX 0 #define mmBIF_BX_DEV0_EPF0_VF9_MM_INDEX_HI 0x0006 #define mmBIF_BX_DEV0_EPF0_VF9_MM_INDEX_HI_BASE_IDX 0 // addressBlock: nbio_nbif0_rcc_dev0_epf0_vf9_BIFPFVFDEC1 // base address: 0x0 #define mmRCC_DEV0_EPF0_VF9_RCC_ERR_LOG 0x0085 #define mmRCC_DEV0_EPF0_VF9_RCC_ERR_LOG_BASE_IDX 2 #define mmRCC_DEV0_EPF0_VF9_RCC_DOORBELL_APER_EN 0x00c0 #define mmRCC_DEV0_EPF0_VF9_RCC_DOORBELL_APER_EN_BASE_IDX 2 #define mmRCC_DEV0_EPF0_VF9_RCC_CONFIG_MEMSIZE 0x00c3 #define mmRCC_DEV0_EPF0_VF9_RCC_CONFIG_MEMSIZE_BASE_IDX 2 #define mmRCC_DEV0_EPF0_VF9_RCC_CONFIG_RESERVED 0x00c4 #define mmRCC_DEV0_EPF0_VF9_RCC_CONFIG_RESERVED_BASE_IDX 2 #define mmRCC_DEV0_EPF0_VF9_RCC_IOV_FUNC_IDENTIFIER 0x00c5 #define mmRCC_DEV0_EPF0_VF9_RCC_IOV_FUNC_IDENTIFIER_BASE_IDX 2 // addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf9_BIFPFVFDEC1 // base address: 0x0 #define mmBIF_BX_DEV0_EPF0_VF9_BIF_BME_STATUS 0x00eb #define mmBIF_BX_DEV0_EPF0_VF9_BIF_BME_STATUS_BASE_IDX 2 #define mmBIF_BX_DEV0_EPF0_VF9_BIF_ATOMIC_ERR_LOG 0x00ec #define mmBIF_BX_DEV0_EPF0_VF9_BIF_ATOMIC_ERR_LOG_BASE_IDX 2 #define mmBIF_BX_DEV0_EPF0_VF9_DOORBELL_SELFRING_GPA_APER_BASE_HIGH 0x00f3 #define your_sha256_hash_IDX 2 #define mmBIF_BX_DEV0_EPF0_VF9_DOORBELL_SELFRING_GPA_APER_BASE_LOW 0x00f4 #define your_sha256_hashIDX 2 #define mmBIF_BX_DEV0_EPF0_VF9_DOORBELL_SELFRING_GPA_APER_CNTL 0x00f5 #define mmBIF_BX_DEV0_EPF0_VF9_DOORBELL_SELFRING_GPA_APER_CNTL_BASE_IDX 2 #define mmBIF_BX_DEV0_EPF0_VF9_HDP_REG_COHERENCY_FLUSH_CNTL 0x00f6 #define mmBIF_BX_DEV0_EPF0_VF9_HDP_REG_COHERENCY_FLUSH_CNTL_BASE_IDX 2 #define mmBIF_BX_DEV0_EPF0_VF9_HDP_MEM_COHERENCY_FLUSH_CNTL 0x00f7 #define mmBIF_BX_DEV0_EPF0_VF9_HDP_MEM_COHERENCY_FLUSH_CNTL_BASE_IDX 2 #define mmBIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_REQ 0x0106 #define mmBIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_REQ_BASE_IDX 2 #define mmBIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_DONE 0x0107 #define mmBIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_DONE_BASE_IDX 2 #define mmBIF_BX_DEV0_EPF0_VF9_BIF_TRANS_PENDING 0x0108 #define mmBIF_BX_DEV0_EPF0_VF9_BIF_TRANS_PENDING_BASE_IDX 2 #define mmBIF_BX_DEV0_EPF0_VF9_NBIF_GFX_ADDR_LUT_BYPASS 0x0112 #define mmBIF_BX_DEV0_EPF0_VF9_NBIF_GFX_ADDR_LUT_BYPASS_BASE_IDX 2 #define mmBIF_BX_DEV0_EPF0_VF9_MAILBOX_MSGBUF_TRN_DW0 0x0136 #define mmBIF_BX_DEV0_EPF0_VF9_MAILBOX_MSGBUF_TRN_DW0_BASE_IDX 2 #define mmBIF_BX_DEV0_EPF0_VF9_MAILBOX_MSGBUF_TRN_DW1 0x0137 #define mmBIF_BX_DEV0_EPF0_VF9_MAILBOX_MSGBUF_TRN_DW1_BASE_IDX 2 #define mmBIF_BX_DEV0_EPF0_VF9_MAILBOX_MSGBUF_TRN_DW2 0x0138 #define mmBIF_BX_DEV0_EPF0_VF9_MAILBOX_MSGBUF_TRN_DW2_BASE_IDX 2 #define mmBIF_BX_DEV0_EPF0_VF9_MAILBOX_MSGBUF_TRN_DW3 0x0139 #define mmBIF_BX_DEV0_EPF0_VF9_MAILBOX_MSGBUF_TRN_DW3_BASE_IDX 2 #define mmBIF_BX_DEV0_EPF0_VF9_MAILBOX_MSGBUF_RCV_DW0 0x013a #define mmBIF_BX_DEV0_EPF0_VF9_MAILBOX_MSGBUF_RCV_DW0_BASE_IDX 2 #define mmBIF_BX_DEV0_EPF0_VF9_MAILBOX_MSGBUF_RCV_DW1 0x013b #define mmBIF_BX_DEV0_EPF0_VF9_MAILBOX_MSGBUF_RCV_DW1_BASE_IDX 2 #define mmBIF_BX_DEV0_EPF0_VF9_MAILBOX_MSGBUF_RCV_DW2 0x013c #define mmBIF_BX_DEV0_EPF0_VF9_MAILBOX_MSGBUF_RCV_DW2_BASE_IDX 2 #define mmBIF_BX_DEV0_EPF0_VF9_MAILBOX_MSGBUF_RCV_DW3 0x013d #define mmBIF_BX_DEV0_EPF0_VF9_MAILBOX_MSGBUF_RCV_DW3_BASE_IDX 2 #define mmBIF_BX_DEV0_EPF0_VF9_MAILBOX_CONTROL 0x013e #define mmBIF_BX_DEV0_EPF0_VF9_MAILBOX_CONTROL_BASE_IDX 2 #define mmBIF_BX_DEV0_EPF0_VF9_MAILBOX_INT_CNTL 0x013f #define mmBIF_BX_DEV0_EPF0_VF9_MAILBOX_INT_CNTL_BASE_IDX 2 #define mmBIF_BX_DEV0_EPF0_VF9_BIF_VMHV_MAILBOX 0x0140 #define mmBIF_BX_DEV0_EPF0_VF9_BIF_VMHV_MAILBOX_BASE_IDX 2 // addressBlock: nbio_nbif0_rcc_dev0_epf0_vf9_BIFDEC2 // base address: 0x0 #define mmRCC_DEV0_EPF0_VF9_GFXMSIX_VECT0_ADDR_LO 0x0400 #define mmRCC_DEV0_EPF0_VF9_GFXMSIX_VECT0_ADDR_LO_BASE_IDX 3 #define mmRCC_DEV0_EPF0_VF9_GFXMSIX_VECT0_ADDR_HI 0x0401 #define mmRCC_DEV0_EPF0_VF9_GFXMSIX_VECT0_ADDR_HI_BASE_IDX 3 #define mmRCC_DEV0_EPF0_VF9_GFXMSIX_VECT0_MSG_DATA 0x0402 #define mmRCC_DEV0_EPF0_VF9_GFXMSIX_VECT0_MSG_DATA_BASE_IDX 3 #define mmRCC_DEV0_EPF0_VF9_GFXMSIX_VECT0_CONTROL 0x0403 #define mmRCC_DEV0_EPF0_VF9_GFXMSIX_VECT0_CONTROL_BASE_IDX 3 #define mmRCC_DEV0_EPF0_VF9_GFXMSIX_VECT1_ADDR_LO 0x0404 #define mmRCC_DEV0_EPF0_VF9_GFXMSIX_VECT1_ADDR_LO_BASE_IDX 3 #define mmRCC_DEV0_EPF0_VF9_GFXMSIX_VECT1_ADDR_HI 0x0405 #define mmRCC_DEV0_EPF0_VF9_GFXMSIX_VECT1_ADDR_HI_BASE_IDX 3 #define mmRCC_DEV0_EPF0_VF9_GFXMSIX_VECT1_MSG_DATA 0x0406 #define mmRCC_DEV0_EPF0_VF9_GFXMSIX_VECT1_MSG_DATA_BASE_IDX 3 #define mmRCC_DEV0_EPF0_VF9_GFXMSIX_VECT1_CONTROL 0x0407 #define mmRCC_DEV0_EPF0_VF9_GFXMSIX_VECT1_CONTROL_BASE_IDX 3 #define mmRCC_DEV0_EPF0_VF9_GFXMSIX_VECT2_ADDR_LO 0x0408 #define mmRCC_DEV0_EPF0_VF9_GFXMSIX_VECT2_ADDR_LO_BASE_IDX 3 #define mmRCC_DEV0_EPF0_VF9_GFXMSIX_VECT2_ADDR_HI 0x0409 #define mmRCC_DEV0_EPF0_VF9_GFXMSIX_VECT2_ADDR_HI_BASE_IDX 3 #define mmRCC_DEV0_EPF0_VF9_GFXMSIX_VECT2_MSG_DATA 0x040a #define mmRCC_DEV0_EPF0_VF9_GFXMSIX_VECT2_MSG_DATA_BASE_IDX 3 #define mmRCC_DEV0_EPF0_VF9_GFXMSIX_VECT2_CONTROL 0x040b #define mmRCC_DEV0_EPF0_VF9_GFXMSIX_VECT2_CONTROL_BASE_IDX 3 #define mmRCC_DEV0_EPF0_VF9_GFXMSIX_VECT3_ADDR_LO 0x040c #define mmRCC_DEV0_EPF0_VF9_GFXMSIX_VECT3_ADDR_LO_BASE_IDX 3 #define mmRCC_DEV0_EPF0_VF9_GFXMSIX_VECT3_ADDR_HI 0x040d #define mmRCC_DEV0_EPF0_VF9_GFXMSIX_VECT3_ADDR_HI_BASE_IDX 3 #define mmRCC_DEV0_EPF0_VF9_GFXMSIX_VECT3_MSG_DATA 0x040e #define mmRCC_DEV0_EPF0_VF9_GFXMSIX_VECT3_MSG_DATA_BASE_IDX 3 #define mmRCC_DEV0_EPF0_VF9_GFXMSIX_VECT3_CONTROL 0x040f #define mmRCC_DEV0_EPF0_VF9_GFXMSIX_VECT3_CONTROL_BASE_IDX 3 #define mmRCC_DEV0_EPF0_VF9_GFXMSIX_PBA 0x0800 #define mmRCC_DEV0_EPF0_VF9_GFXMSIX_PBA_BASE_IDX 3 // addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf10_SYSPFVFDEC // base address: 0x0 #define mmBIF_BX_DEV0_EPF0_VF10_MM_INDEX 0x0000 #define mmBIF_BX_DEV0_EPF0_VF10_MM_INDEX_BASE_IDX 0 #define mmBIF_BX_DEV0_EPF0_VF10_MM_DATA 0x0001 #define mmBIF_BX_DEV0_EPF0_VF10_MM_DATA_BASE_IDX 0 #define mmBIF_BX_DEV0_EPF0_VF10_MM_INDEX_HI 0x0006 #define mmBIF_BX_DEV0_EPF0_VF10_MM_INDEX_HI_BASE_IDX 0 // addressBlock: nbio_nbif0_rcc_dev0_epf0_vf10_BIFPFVFDEC1 // base address: 0x0 #define mmRCC_DEV0_EPF0_VF10_RCC_ERR_LOG 0x0085 #define mmRCC_DEV0_EPF0_VF10_RCC_ERR_LOG_BASE_IDX 2 #define mmRCC_DEV0_EPF0_VF10_RCC_DOORBELL_APER_EN 0x00c0 #define mmRCC_DEV0_EPF0_VF10_RCC_DOORBELL_APER_EN_BASE_IDX 2 #define mmRCC_DEV0_EPF0_VF10_RCC_CONFIG_MEMSIZE 0x00c3 #define mmRCC_DEV0_EPF0_VF10_RCC_CONFIG_MEMSIZE_BASE_IDX 2 #define mmRCC_DEV0_EPF0_VF10_RCC_CONFIG_RESERVED 0x00c4 #define mmRCC_DEV0_EPF0_VF10_RCC_CONFIG_RESERVED_BASE_IDX 2 #define mmRCC_DEV0_EPF0_VF10_RCC_IOV_FUNC_IDENTIFIER 0x00c5 #define mmRCC_DEV0_EPF0_VF10_RCC_IOV_FUNC_IDENTIFIER_BASE_IDX 2 // addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf10_BIFPFVFDEC1 // base address: 0x0 #define mmBIF_BX_DEV0_EPF0_VF10_BIF_BME_STATUS 0x00eb #define mmBIF_BX_DEV0_EPF0_VF10_BIF_BME_STATUS_BASE_IDX 2 #define mmBIF_BX_DEV0_EPF0_VF10_BIF_ATOMIC_ERR_LOG 0x00ec #define mmBIF_BX_DEV0_EPF0_VF10_BIF_ATOMIC_ERR_LOG_BASE_IDX 2 #define mmBIF_BX_DEV0_EPF0_VF10_DOORBELL_SELFRING_GPA_APER_BASE_HIGH 0x00f3 #define your_sha256_hashE_IDX 2 #define mmBIF_BX_DEV0_EPF0_VF10_DOORBELL_SELFRING_GPA_APER_BASE_LOW 0x00f4 #define your_sha256_hash_IDX 2 #define mmBIF_BX_DEV0_EPF0_VF10_DOORBELL_SELFRING_GPA_APER_CNTL 0x00f5 #define your_sha256_hash 2 #define mmBIF_BX_DEV0_EPF0_VF10_HDP_REG_COHERENCY_FLUSH_CNTL 0x00f6 #define mmBIF_BX_DEV0_EPF0_VF10_HDP_REG_COHERENCY_FLUSH_CNTL_BASE_IDX 2 #define mmBIF_BX_DEV0_EPF0_VF10_HDP_MEM_COHERENCY_FLUSH_CNTL 0x00f7 #define mmBIF_BX_DEV0_EPF0_VF10_HDP_MEM_COHERENCY_FLUSH_CNTL_BASE_IDX 2 #define mmBIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_REQ 0x0106 #define mmBIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_REQ_BASE_IDX 2 #define mmBIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_DONE 0x0107 #define mmBIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_DONE_BASE_IDX 2 #define mmBIF_BX_DEV0_EPF0_VF10_BIF_TRANS_PENDING 0x0108 #define mmBIF_BX_DEV0_EPF0_VF10_BIF_TRANS_PENDING_BASE_IDX 2 #define mmBIF_BX_DEV0_EPF0_VF10_NBIF_GFX_ADDR_LUT_BYPASS 0x0112 #define mmBIF_BX_DEV0_EPF0_VF10_NBIF_GFX_ADDR_LUT_BYPASS_BASE_IDX 2 #define mmBIF_BX_DEV0_EPF0_VF10_MAILBOX_MSGBUF_TRN_DW0 0x0136 #define mmBIF_BX_DEV0_EPF0_VF10_MAILBOX_MSGBUF_TRN_DW0_BASE_IDX 2 #define mmBIF_BX_DEV0_EPF0_VF10_MAILBOX_MSGBUF_TRN_DW1 0x0137 #define mmBIF_BX_DEV0_EPF0_VF10_MAILBOX_MSGBUF_TRN_DW1_BASE_IDX 2 #define mmBIF_BX_DEV0_EPF0_VF10_MAILBOX_MSGBUF_TRN_DW2 0x0138 #define mmBIF_BX_DEV0_EPF0_VF10_MAILBOX_MSGBUF_TRN_DW2_BASE_IDX 2 #define mmBIF_BX_DEV0_EPF0_VF10_MAILBOX_MSGBUF_TRN_DW3 0x0139 #define mmBIF_BX_DEV0_EPF0_VF10_MAILBOX_MSGBUF_TRN_DW3_BASE_IDX 2 #define mmBIF_BX_DEV0_EPF0_VF10_MAILBOX_MSGBUF_RCV_DW0 0x013a #define mmBIF_BX_DEV0_EPF0_VF10_MAILBOX_MSGBUF_RCV_DW0_BASE_IDX 2 #define mmBIF_BX_DEV0_EPF0_VF10_MAILBOX_MSGBUF_RCV_DW1 0x013b #define mmBIF_BX_DEV0_EPF0_VF10_MAILBOX_MSGBUF_RCV_DW1_BASE_IDX 2 #define mmBIF_BX_DEV0_EPF0_VF10_MAILBOX_MSGBUF_RCV_DW2 0x013c #define mmBIF_BX_DEV0_EPF0_VF10_MAILBOX_MSGBUF_RCV_DW2_BASE_IDX 2 #define mmBIF_BX_DEV0_EPF0_VF10_MAILBOX_MSGBUF_RCV_DW3 0x013d #define mmBIF_BX_DEV0_EPF0_VF10_MAILBOX_MSGBUF_RCV_DW3_BASE_IDX 2 #define mmBIF_BX_DEV0_EPF0_VF10_MAILBOX_CONTROL 0x013e #define mmBIF_BX_DEV0_EPF0_VF10_MAILBOX_CONTROL_BASE_IDX 2 #define mmBIF_BX_DEV0_EPF0_VF10_MAILBOX_INT_CNTL 0x013f #define mmBIF_BX_DEV0_EPF0_VF10_MAILBOX_INT_CNTL_BASE_IDX 2 #define mmBIF_BX_DEV0_EPF0_VF10_BIF_VMHV_MAILBOX 0x0140 #define mmBIF_BX_DEV0_EPF0_VF10_BIF_VMHV_MAILBOX_BASE_IDX 2 // addressBlock: nbio_nbif0_rcc_dev0_epf0_vf10_BIFDEC2 // base address: 0x0 #define mmRCC_DEV0_EPF0_VF10_GFXMSIX_VECT0_ADDR_LO 0x0400 #define mmRCC_DEV0_EPF0_VF10_GFXMSIX_VECT0_ADDR_LO_BASE_IDX 3 #define mmRCC_DEV0_EPF0_VF10_GFXMSIX_VECT0_ADDR_HI 0x0401 #define mmRCC_DEV0_EPF0_VF10_GFXMSIX_VECT0_ADDR_HI_BASE_IDX 3 #define mmRCC_DEV0_EPF0_VF10_GFXMSIX_VECT0_MSG_DATA 0x0402 #define mmRCC_DEV0_EPF0_VF10_GFXMSIX_VECT0_MSG_DATA_BASE_IDX 3 #define mmRCC_DEV0_EPF0_VF10_GFXMSIX_VECT0_CONTROL 0x0403 #define mmRCC_DEV0_EPF0_VF10_GFXMSIX_VECT0_CONTROL_BASE_IDX 3 #define mmRCC_DEV0_EPF0_VF10_GFXMSIX_VECT1_ADDR_LO 0x0404 #define mmRCC_DEV0_EPF0_VF10_GFXMSIX_VECT1_ADDR_LO_BASE_IDX 3 #define mmRCC_DEV0_EPF0_VF10_GFXMSIX_VECT1_ADDR_HI 0x0405 #define mmRCC_DEV0_EPF0_VF10_GFXMSIX_VECT1_ADDR_HI_BASE_IDX 3 #define mmRCC_DEV0_EPF0_VF10_GFXMSIX_VECT1_MSG_DATA 0x0406 #define mmRCC_DEV0_EPF0_VF10_GFXMSIX_VECT1_MSG_DATA_BASE_IDX 3 #define mmRCC_DEV0_EPF0_VF10_GFXMSIX_VECT1_CONTROL 0x0407 #define mmRCC_DEV0_EPF0_VF10_GFXMSIX_VECT1_CONTROL_BASE_IDX 3 #define mmRCC_DEV0_EPF0_VF10_GFXMSIX_VECT2_ADDR_LO 0x0408 #define mmRCC_DEV0_EPF0_VF10_GFXMSIX_VECT2_ADDR_LO_BASE_IDX 3 #define mmRCC_DEV0_EPF0_VF10_GFXMSIX_VECT2_ADDR_HI 0x0409 #define mmRCC_DEV0_EPF0_VF10_GFXMSIX_VECT2_ADDR_HI_BASE_IDX 3 #define mmRCC_DEV0_EPF0_VF10_GFXMSIX_VECT2_MSG_DATA 0x040a #define mmRCC_DEV0_EPF0_VF10_GFXMSIX_VECT2_MSG_DATA_BASE_IDX 3 #define mmRCC_DEV0_EPF0_VF10_GFXMSIX_VECT2_CONTROL 0x040b #define mmRCC_DEV0_EPF0_VF10_GFXMSIX_VECT2_CONTROL_BASE_IDX 3 #define mmRCC_DEV0_EPF0_VF10_GFXMSIX_VECT3_ADDR_LO 0x040c #define mmRCC_DEV0_EPF0_VF10_GFXMSIX_VECT3_ADDR_LO_BASE_IDX 3 #define mmRCC_DEV0_EPF0_VF10_GFXMSIX_VECT3_ADDR_HI 0x040d #define mmRCC_DEV0_EPF0_VF10_GFXMSIX_VECT3_ADDR_HI_BASE_IDX 3 #define mmRCC_DEV0_EPF0_VF10_GFXMSIX_VECT3_MSG_DATA 0x040e #define mmRCC_DEV0_EPF0_VF10_GFXMSIX_VECT3_MSG_DATA_BASE_IDX 3 #define mmRCC_DEV0_EPF0_VF10_GFXMSIX_VECT3_CONTROL 0x040f #define mmRCC_DEV0_EPF0_VF10_GFXMSIX_VECT3_CONTROL_BASE_IDX 3 #define mmRCC_DEV0_EPF0_VF10_GFXMSIX_PBA 0x0800 #define mmRCC_DEV0_EPF0_VF10_GFXMSIX_PBA_BASE_IDX 3 // addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf11_SYSPFVFDEC // base address: 0x0 #define mmBIF_BX_DEV0_EPF0_VF11_MM_INDEX 0x0000 #define mmBIF_BX_DEV0_EPF0_VF11_MM_INDEX_BASE_IDX 0 #define mmBIF_BX_DEV0_EPF0_VF11_MM_DATA 0x0001 #define mmBIF_BX_DEV0_EPF0_VF11_MM_DATA_BASE_IDX 0 #define mmBIF_BX_DEV0_EPF0_VF11_MM_INDEX_HI 0x0006 #define mmBIF_BX_DEV0_EPF0_VF11_MM_INDEX_HI_BASE_IDX 0 // addressBlock: nbio_nbif0_rcc_dev0_epf0_vf11_BIFPFVFDEC1 // base address: 0x0 #define mmRCC_DEV0_EPF0_VF11_RCC_ERR_LOG 0x0085 #define mmRCC_DEV0_EPF0_VF11_RCC_ERR_LOG_BASE_IDX 2 #define mmRCC_DEV0_EPF0_VF11_RCC_DOORBELL_APER_EN 0x00c0 #define mmRCC_DEV0_EPF0_VF11_RCC_DOORBELL_APER_EN_BASE_IDX 2 #define mmRCC_DEV0_EPF0_VF11_RCC_CONFIG_MEMSIZE 0x00c3 #define mmRCC_DEV0_EPF0_VF11_RCC_CONFIG_MEMSIZE_BASE_IDX 2 #define mmRCC_DEV0_EPF0_VF11_RCC_CONFIG_RESERVED 0x00c4 #define mmRCC_DEV0_EPF0_VF11_RCC_CONFIG_RESERVED_BASE_IDX 2 #define mmRCC_DEV0_EPF0_VF11_RCC_IOV_FUNC_IDENTIFIER 0x00c5 #define mmRCC_DEV0_EPF0_VF11_RCC_IOV_FUNC_IDENTIFIER_BASE_IDX 2 // addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf11_BIFPFVFDEC1 // base address: 0x0 #define mmBIF_BX_DEV0_EPF0_VF11_BIF_BME_STATUS 0x00eb #define mmBIF_BX_DEV0_EPF0_VF11_BIF_BME_STATUS_BASE_IDX 2 #define mmBIF_BX_DEV0_EPF0_VF11_BIF_ATOMIC_ERR_LOG 0x00ec #define mmBIF_BX_DEV0_EPF0_VF11_BIF_ATOMIC_ERR_LOG_BASE_IDX 2 #define mmBIF_BX_DEV0_EPF0_VF11_DOORBELL_SELFRING_GPA_APER_BASE_HIGH 0x00f3 #define your_sha256_hashE_IDX 2 #define mmBIF_BX_DEV0_EPF0_VF11_DOORBELL_SELFRING_GPA_APER_BASE_LOW 0x00f4 #define your_sha256_hash_IDX 2 #define mmBIF_BX_DEV0_EPF0_VF11_DOORBELL_SELFRING_GPA_APER_CNTL 0x00f5 #define your_sha256_hash 2 #define mmBIF_BX_DEV0_EPF0_VF11_HDP_REG_COHERENCY_FLUSH_CNTL 0x00f6 #define mmBIF_BX_DEV0_EPF0_VF11_HDP_REG_COHERENCY_FLUSH_CNTL_BASE_IDX 2 #define mmBIF_BX_DEV0_EPF0_VF11_HDP_MEM_COHERENCY_FLUSH_CNTL 0x00f7 #define mmBIF_BX_DEV0_EPF0_VF11_HDP_MEM_COHERENCY_FLUSH_CNTL_BASE_IDX 2 #define mmBIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_REQ 0x0106 #define mmBIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_REQ_BASE_IDX 2 #define mmBIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_DONE 0x0107 #define mmBIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_DONE_BASE_IDX 2 #define mmBIF_BX_DEV0_EPF0_VF11_BIF_TRANS_PENDING 0x0108 #define mmBIF_BX_DEV0_EPF0_VF11_BIF_TRANS_PENDING_BASE_IDX 2 #define mmBIF_BX_DEV0_EPF0_VF11_NBIF_GFX_ADDR_LUT_BYPASS 0x0112 #define mmBIF_BX_DEV0_EPF0_VF11_NBIF_GFX_ADDR_LUT_BYPASS_BASE_IDX 2 #define mmBIF_BX_DEV0_EPF0_VF11_MAILBOX_MSGBUF_TRN_DW0 0x0136 #define mmBIF_BX_DEV0_EPF0_VF11_MAILBOX_MSGBUF_TRN_DW0_BASE_IDX 2 #define mmBIF_BX_DEV0_EPF0_VF11_MAILBOX_MSGBUF_TRN_DW1 0x0137 #define mmBIF_BX_DEV0_EPF0_VF11_MAILBOX_MSGBUF_TRN_DW1_BASE_IDX 2 #define mmBIF_BX_DEV0_EPF0_VF11_MAILBOX_MSGBUF_TRN_DW2 0x0138 #define mmBIF_BX_DEV0_EPF0_VF11_MAILBOX_MSGBUF_TRN_DW2_BASE_IDX 2 #define mmBIF_BX_DEV0_EPF0_VF11_MAILBOX_MSGBUF_TRN_DW3 0x0139 #define mmBIF_BX_DEV0_EPF0_VF11_MAILBOX_MSGBUF_TRN_DW3_BASE_IDX 2 #define mmBIF_BX_DEV0_EPF0_VF11_MAILBOX_MSGBUF_RCV_DW0 0x013a #define mmBIF_BX_DEV0_EPF0_VF11_MAILBOX_MSGBUF_RCV_DW0_BASE_IDX 2 #define mmBIF_BX_DEV0_EPF0_VF11_MAILBOX_MSGBUF_RCV_DW1 0x013b #define mmBIF_BX_DEV0_EPF0_VF11_MAILBOX_MSGBUF_RCV_DW1_BASE_IDX 2 #define mmBIF_BX_DEV0_EPF0_VF11_MAILBOX_MSGBUF_RCV_DW2 0x013c #define mmBIF_BX_DEV0_EPF0_VF11_MAILBOX_MSGBUF_RCV_DW2_BASE_IDX 2 #define mmBIF_BX_DEV0_EPF0_VF11_MAILBOX_MSGBUF_RCV_DW3 0x013d #define mmBIF_BX_DEV0_EPF0_VF11_MAILBOX_MSGBUF_RCV_DW3_BASE_IDX 2 #define mmBIF_BX_DEV0_EPF0_VF11_MAILBOX_CONTROL 0x013e #define mmBIF_BX_DEV0_EPF0_VF11_MAILBOX_CONTROL_BASE_IDX 2 #define mmBIF_BX_DEV0_EPF0_VF11_MAILBOX_INT_CNTL 0x013f #define mmBIF_BX_DEV0_EPF0_VF11_MAILBOX_INT_CNTL_BASE_IDX 2 #define mmBIF_BX_DEV0_EPF0_VF11_BIF_VMHV_MAILBOX 0x0140 #define mmBIF_BX_DEV0_EPF0_VF11_BIF_VMHV_MAILBOX_BASE_IDX 2 // addressBlock: nbio_nbif0_rcc_dev0_epf0_vf11_BIFDEC2 // base address: 0x0 #define mmRCC_DEV0_EPF0_VF11_GFXMSIX_VECT0_ADDR_LO 0x0400 #define mmRCC_DEV0_EPF0_VF11_GFXMSIX_VECT0_ADDR_LO_BASE_IDX 3 #define mmRCC_DEV0_EPF0_VF11_GFXMSIX_VECT0_ADDR_HI 0x0401 #define mmRCC_DEV0_EPF0_VF11_GFXMSIX_VECT0_ADDR_HI_BASE_IDX 3 #define mmRCC_DEV0_EPF0_VF11_GFXMSIX_VECT0_MSG_DATA 0x0402 #define mmRCC_DEV0_EPF0_VF11_GFXMSIX_VECT0_MSG_DATA_BASE_IDX 3 #define mmRCC_DEV0_EPF0_VF11_GFXMSIX_VECT0_CONTROL 0x0403 #define mmRCC_DEV0_EPF0_VF11_GFXMSIX_VECT0_CONTROL_BASE_IDX 3 #define mmRCC_DEV0_EPF0_VF11_GFXMSIX_VECT1_ADDR_LO 0x0404 #define mmRCC_DEV0_EPF0_VF11_GFXMSIX_VECT1_ADDR_LO_BASE_IDX 3 #define mmRCC_DEV0_EPF0_VF11_GFXMSIX_VECT1_ADDR_HI 0x0405 #define mmRCC_DEV0_EPF0_VF11_GFXMSIX_VECT1_ADDR_HI_BASE_IDX 3 #define mmRCC_DEV0_EPF0_VF11_GFXMSIX_VECT1_MSG_DATA 0x0406 #define mmRCC_DEV0_EPF0_VF11_GFXMSIX_VECT1_MSG_DATA_BASE_IDX 3 #define mmRCC_DEV0_EPF0_VF11_GFXMSIX_VECT1_CONTROL 0x0407 #define mmRCC_DEV0_EPF0_VF11_GFXMSIX_VECT1_CONTROL_BASE_IDX 3 #define mmRCC_DEV0_EPF0_VF11_GFXMSIX_VECT2_ADDR_LO 0x0408 #define mmRCC_DEV0_EPF0_VF11_GFXMSIX_VECT2_ADDR_LO_BASE_IDX 3 #define mmRCC_DEV0_EPF0_VF11_GFXMSIX_VECT2_ADDR_HI 0x0409 #define mmRCC_DEV0_EPF0_VF11_GFXMSIX_VECT2_ADDR_HI_BASE_IDX 3 #define mmRCC_DEV0_EPF0_VF11_GFXMSIX_VECT2_MSG_DATA 0x040a #define mmRCC_DEV0_EPF0_VF11_GFXMSIX_VECT2_MSG_DATA_BASE_IDX 3 #define mmRCC_DEV0_EPF0_VF11_GFXMSIX_VECT2_CONTROL 0x040b #define mmRCC_DEV0_EPF0_VF11_GFXMSIX_VECT2_CONTROL_BASE_IDX 3 #define mmRCC_DEV0_EPF0_VF11_GFXMSIX_VECT3_ADDR_LO 0x040c #define mmRCC_DEV0_EPF0_VF11_GFXMSIX_VECT3_ADDR_LO_BASE_IDX 3 #define mmRCC_DEV0_EPF0_VF11_GFXMSIX_VECT3_ADDR_HI 0x040d #define mmRCC_DEV0_EPF0_VF11_GFXMSIX_VECT3_ADDR_HI_BASE_IDX 3 #define mmRCC_DEV0_EPF0_VF11_GFXMSIX_VECT3_MSG_DATA 0x040e #define mmRCC_DEV0_EPF0_VF11_GFXMSIX_VECT3_MSG_DATA_BASE_IDX 3 #define mmRCC_DEV0_EPF0_VF11_GFXMSIX_VECT3_CONTROL 0x040f #define mmRCC_DEV0_EPF0_VF11_GFXMSIX_VECT3_CONTROL_BASE_IDX 3 #define mmRCC_DEV0_EPF0_VF11_GFXMSIX_PBA 0x0800 #define mmRCC_DEV0_EPF0_VF11_GFXMSIX_PBA_BASE_IDX 3 // addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf12_SYSPFVFDEC // base address: 0x0 #define mmBIF_BX_DEV0_EPF0_VF12_MM_INDEX 0x0000 #define mmBIF_BX_DEV0_EPF0_VF12_MM_INDEX_BASE_IDX 0 #define mmBIF_BX_DEV0_EPF0_VF12_MM_DATA 0x0001 #define mmBIF_BX_DEV0_EPF0_VF12_MM_DATA_BASE_IDX 0 #define mmBIF_BX_DEV0_EPF0_VF12_MM_INDEX_HI 0x0006 #define mmBIF_BX_DEV0_EPF0_VF12_MM_INDEX_HI_BASE_IDX 0 // addressBlock: nbio_nbif0_rcc_dev0_epf0_vf12_BIFPFVFDEC1 // base address: 0x0 #define mmRCC_DEV0_EPF0_VF12_RCC_ERR_LOG 0x0085 #define mmRCC_DEV0_EPF0_VF12_RCC_ERR_LOG_BASE_IDX 2 #define mmRCC_DEV0_EPF0_VF12_RCC_DOORBELL_APER_EN 0x00c0 #define mmRCC_DEV0_EPF0_VF12_RCC_DOORBELL_APER_EN_BASE_IDX 2 #define mmRCC_DEV0_EPF0_VF12_RCC_CONFIG_MEMSIZE 0x00c3 #define mmRCC_DEV0_EPF0_VF12_RCC_CONFIG_MEMSIZE_BASE_IDX 2 #define mmRCC_DEV0_EPF0_VF12_RCC_CONFIG_RESERVED 0x00c4 #define mmRCC_DEV0_EPF0_VF12_RCC_CONFIG_RESERVED_BASE_IDX 2 #define mmRCC_DEV0_EPF0_VF12_RCC_IOV_FUNC_IDENTIFIER 0x00c5 #define mmRCC_DEV0_EPF0_VF12_RCC_IOV_FUNC_IDENTIFIER_BASE_IDX 2 // addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf12_BIFPFVFDEC1 // base address: 0x0 #define mmBIF_BX_DEV0_EPF0_VF12_BIF_BME_STATUS 0x00eb #define mmBIF_BX_DEV0_EPF0_VF12_BIF_BME_STATUS_BASE_IDX 2 #define mmBIF_BX_DEV0_EPF0_VF12_BIF_ATOMIC_ERR_LOG 0x00ec #define mmBIF_BX_DEV0_EPF0_VF12_BIF_ATOMIC_ERR_LOG_BASE_IDX 2 #define mmBIF_BX_DEV0_EPF0_VF12_DOORBELL_SELFRING_GPA_APER_BASE_HIGH 0x00f3 #define your_sha256_hashE_IDX 2 #define mmBIF_BX_DEV0_EPF0_VF12_DOORBELL_SELFRING_GPA_APER_BASE_LOW 0x00f4 #define your_sha256_hash_IDX 2 #define mmBIF_BX_DEV0_EPF0_VF12_DOORBELL_SELFRING_GPA_APER_CNTL 0x00f5 #define your_sha256_hash 2 #define mmBIF_BX_DEV0_EPF0_VF12_HDP_REG_COHERENCY_FLUSH_CNTL 0x00f6 #define mmBIF_BX_DEV0_EPF0_VF12_HDP_REG_COHERENCY_FLUSH_CNTL_BASE_IDX 2 #define mmBIF_BX_DEV0_EPF0_VF12_HDP_MEM_COHERENCY_FLUSH_CNTL 0x00f7 #define mmBIF_BX_DEV0_EPF0_VF12_HDP_MEM_COHERENCY_FLUSH_CNTL_BASE_IDX 2 #define mmBIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_REQ 0x0106 #define mmBIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_REQ_BASE_IDX 2 #define mmBIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_DONE 0x0107 #define mmBIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_DONE_BASE_IDX 2 #define mmBIF_BX_DEV0_EPF0_VF12_BIF_TRANS_PENDING 0x0108 #define mmBIF_BX_DEV0_EPF0_VF12_BIF_TRANS_PENDING_BASE_IDX 2 #define mmBIF_BX_DEV0_EPF0_VF12_NBIF_GFX_ADDR_LUT_BYPASS 0x0112 #define mmBIF_BX_DEV0_EPF0_VF12_NBIF_GFX_ADDR_LUT_BYPASS_BASE_IDX 2 #define mmBIF_BX_DEV0_EPF0_VF12_MAILBOX_MSGBUF_TRN_DW0 0x0136 #define mmBIF_BX_DEV0_EPF0_VF12_MAILBOX_MSGBUF_TRN_DW0_BASE_IDX 2 #define mmBIF_BX_DEV0_EPF0_VF12_MAILBOX_MSGBUF_TRN_DW1 0x0137 #define mmBIF_BX_DEV0_EPF0_VF12_MAILBOX_MSGBUF_TRN_DW1_BASE_IDX 2 #define mmBIF_BX_DEV0_EPF0_VF12_MAILBOX_MSGBUF_TRN_DW2 0x0138 #define mmBIF_BX_DEV0_EPF0_VF12_MAILBOX_MSGBUF_TRN_DW2_BASE_IDX 2 #define mmBIF_BX_DEV0_EPF0_VF12_MAILBOX_MSGBUF_TRN_DW3 0x0139 #define mmBIF_BX_DEV0_EPF0_VF12_MAILBOX_MSGBUF_TRN_DW3_BASE_IDX 2 #define mmBIF_BX_DEV0_EPF0_VF12_MAILBOX_MSGBUF_RCV_DW0 0x013a #define mmBIF_BX_DEV0_EPF0_VF12_MAILBOX_MSGBUF_RCV_DW0_BASE_IDX 2 #define mmBIF_BX_DEV0_EPF0_VF12_MAILBOX_MSGBUF_RCV_DW1 0x013b #define mmBIF_BX_DEV0_EPF0_VF12_MAILBOX_MSGBUF_RCV_DW1_BASE_IDX 2 #define mmBIF_BX_DEV0_EPF0_VF12_MAILBOX_MSGBUF_RCV_DW2 0x013c #define mmBIF_BX_DEV0_EPF0_VF12_MAILBOX_MSGBUF_RCV_DW2_BASE_IDX 2 #define mmBIF_BX_DEV0_EPF0_VF12_MAILBOX_MSGBUF_RCV_DW3 0x013d #define mmBIF_BX_DEV0_EPF0_VF12_MAILBOX_MSGBUF_RCV_DW3_BASE_IDX 2 #define mmBIF_BX_DEV0_EPF0_VF12_MAILBOX_CONTROL 0x013e #define mmBIF_BX_DEV0_EPF0_VF12_MAILBOX_CONTROL_BASE_IDX 2 #define mmBIF_BX_DEV0_EPF0_VF12_MAILBOX_INT_CNTL 0x013f #define mmBIF_BX_DEV0_EPF0_VF12_MAILBOX_INT_CNTL_BASE_IDX 2 #define mmBIF_BX_DEV0_EPF0_VF12_BIF_VMHV_MAILBOX 0x0140 #define mmBIF_BX_DEV0_EPF0_VF12_BIF_VMHV_MAILBOX_BASE_IDX 2 // addressBlock: nbio_nbif0_rcc_dev0_epf0_vf12_BIFDEC2 // base address: 0x0 #define mmRCC_DEV0_EPF0_VF12_GFXMSIX_VECT0_ADDR_LO 0x0400 #define mmRCC_DEV0_EPF0_VF12_GFXMSIX_VECT0_ADDR_LO_BASE_IDX 3 #define mmRCC_DEV0_EPF0_VF12_GFXMSIX_VECT0_ADDR_HI 0x0401 #define mmRCC_DEV0_EPF0_VF12_GFXMSIX_VECT0_ADDR_HI_BASE_IDX 3 #define mmRCC_DEV0_EPF0_VF12_GFXMSIX_VECT0_MSG_DATA 0x0402 #define mmRCC_DEV0_EPF0_VF12_GFXMSIX_VECT0_MSG_DATA_BASE_IDX 3 #define mmRCC_DEV0_EPF0_VF12_GFXMSIX_VECT0_CONTROL 0x0403 #define mmRCC_DEV0_EPF0_VF12_GFXMSIX_VECT0_CONTROL_BASE_IDX 3 #define mmRCC_DEV0_EPF0_VF12_GFXMSIX_VECT1_ADDR_LO 0x0404 #define mmRCC_DEV0_EPF0_VF12_GFXMSIX_VECT1_ADDR_LO_BASE_IDX 3 #define mmRCC_DEV0_EPF0_VF12_GFXMSIX_VECT1_ADDR_HI 0x0405 #define mmRCC_DEV0_EPF0_VF12_GFXMSIX_VECT1_ADDR_HI_BASE_IDX 3 #define mmRCC_DEV0_EPF0_VF12_GFXMSIX_VECT1_MSG_DATA 0x0406 #define mmRCC_DEV0_EPF0_VF12_GFXMSIX_VECT1_MSG_DATA_BASE_IDX 3 #define mmRCC_DEV0_EPF0_VF12_GFXMSIX_VECT1_CONTROL 0x0407 #define mmRCC_DEV0_EPF0_VF12_GFXMSIX_VECT1_CONTROL_BASE_IDX 3 #define mmRCC_DEV0_EPF0_VF12_GFXMSIX_VECT2_ADDR_LO 0x0408 #define mmRCC_DEV0_EPF0_VF12_GFXMSIX_VECT2_ADDR_LO_BASE_IDX 3 #define mmRCC_DEV0_EPF0_VF12_GFXMSIX_VECT2_ADDR_HI 0x0409 #define mmRCC_DEV0_EPF0_VF12_GFXMSIX_VECT2_ADDR_HI_BASE_IDX 3 #define mmRCC_DEV0_EPF0_VF12_GFXMSIX_VECT2_MSG_DATA 0x040a #define mmRCC_DEV0_EPF0_VF12_GFXMSIX_VECT2_MSG_DATA_BASE_IDX 3 #define mmRCC_DEV0_EPF0_VF12_GFXMSIX_VECT2_CONTROL 0x040b #define mmRCC_DEV0_EPF0_VF12_GFXMSIX_VECT2_CONTROL_BASE_IDX 3 #define mmRCC_DEV0_EPF0_VF12_GFXMSIX_VECT3_ADDR_LO 0x040c #define mmRCC_DEV0_EPF0_VF12_GFXMSIX_VECT3_ADDR_LO_BASE_IDX 3 #define mmRCC_DEV0_EPF0_VF12_GFXMSIX_VECT3_ADDR_HI 0x040d #define mmRCC_DEV0_EPF0_VF12_GFXMSIX_VECT3_ADDR_HI_BASE_IDX 3 #define mmRCC_DEV0_EPF0_VF12_GFXMSIX_VECT3_MSG_DATA 0x040e #define mmRCC_DEV0_EPF0_VF12_GFXMSIX_VECT3_MSG_DATA_BASE_IDX 3 #define mmRCC_DEV0_EPF0_VF12_GFXMSIX_VECT3_CONTROL 0x040f #define mmRCC_DEV0_EPF0_VF12_GFXMSIX_VECT3_CONTROL_BASE_IDX 3 #define mmRCC_DEV0_EPF0_VF12_GFXMSIX_PBA 0x0800 #define mmRCC_DEV0_EPF0_VF12_GFXMSIX_PBA_BASE_IDX 3 // addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf13_SYSPFVFDEC // base address: 0x0 #define mmBIF_BX_DEV0_EPF0_VF13_MM_INDEX 0x0000 #define mmBIF_BX_DEV0_EPF0_VF13_MM_INDEX_BASE_IDX 0 #define mmBIF_BX_DEV0_EPF0_VF13_MM_DATA 0x0001 #define mmBIF_BX_DEV0_EPF0_VF13_MM_DATA_BASE_IDX 0 #define mmBIF_BX_DEV0_EPF0_VF13_MM_INDEX_HI 0x0006 #define mmBIF_BX_DEV0_EPF0_VF13_MM_INDEX_HI_BASE_IDX 0 // addressBlock: nbio_nbif0_rcc_dev0_epf0_vf13_BIFPFVFDEC1 // base address: 0x0 #define mmRCC_DEV0_EPF0_VF13_RCC_ERR_LOG 0x0085 #define mmRCC_DEV0_EPF0_VF13_RCC_ERR_LOG_BASE_IDX 2 #define mmRCC_DEV0_EPF0_VF13_RCC_DOORBELL_APER_EN 0x00c0 #define mmRCC_DEV0_EPF0_VF13_RCC_DOORBELL_APER_EN_BASE_IDX 2 #define mmRCC_DEV0_EPF0_VF13_RCC_CONFIG_MEMSIZE 0x00c3 #define mmRCC_DEV0_EPF0_VF13_RCC_CONFIG_MEMSIZE_BASE_IDX 2 #define mmRCC_DEV0_EPF0_VF13_RCC_CONFIG_RESERVED 0x00c4 #define mmRCC_DEV0_EPF0_VF13_RCC_CONFIG_RESERVED_BASE_IDX 2 #define mmRCC_DEV0_EPF0_VF13_RCC_IOV_FUNC_IDENTIFIER 0x00c5 #define mmRCC_DEV0_EPF0_VF13_RCC_IOV_FUNC_IDENTIFIER_BASE_IDX 2 // addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf13_BIFPFVFDEC1 // base address: 0x0 #define mmBIF_BX_DEV0_EPF0_VF13_BIF_BME_STATUS 0x00eb #define mmBIF_BX_DEV0_EPF0_VF13_BIF_BME_STATUS_BASE_IDX 2 #define mmBIF_BX_DEV0_EPF0_VF13_BIF_ATOMIC_ERR_LOG 0x00ec #define mmBIF_BX_DEV0_EPF0_VF13_BIF_ATOMIC_ERR_LOG_BASE_IDX 2 #define mmBIF_BX_DEV0_EPF0_VF13_DOORBELL_SELFRING_GPA_APER_BASE_HIGH 0x00f3 #define your_sha256_hashE_IDX 2 #define mmBIF_BX_DEV0_EPF0_VF13_DOORBELL_SELFRING_GPA_APER_BASE_LOW 0x00f4 #define your_sha256_hash_IDX 2 #define mmBIF_BX_DEV0_EPF0_VF13_DOORBELL_SELFRING_GPA_APER_CNTL 0x00f5 #define your_sha256_hash 2 #define mmBIF_BX_DEV0_EPF0_VF13_HDP_REG_COHERENCY_FLUSH_CNTL 0x00f6 #define mmBIF_BX_DEV0_EPF0_VF13_HDP_REG_COHERENCY_FLUSH_CNTL_BASE_IDX 2 #define mmBIF_BX_DEV0_EPF0_VF13_HDP_MEM_COHERENCY_FLUSH_CNTL 0x00f7 #define mmBIF_BX_DEV0_EPF0_VF13_HDP_MEM_COHERENCY_FLUSH_CNTL_BASE_IDX 2 #define mmBIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_REQ 0x0106 #define mmBIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_REQ_BASE_IDX 2 #define mmBIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_DONE 0x0107 #define mmBIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_DONE_BASE_IDX 2 #define mmBIF_BX_DEV0_EPF0_VF13_BIF_TRANS_PENDING 0x0108 #define mmBIF_BX_DEV0_EPF0_VF13_BIF_TRANS_PENDING_BASE_IDX 2 #define mmBIF_BX_DEV0_EPF0_VF13_NBIF_GFX_ADDR_LUT_BYPASS 0x0112 #define mmBIF_BX_DEV0_EPF0_VF13_NBIF_GFX_ADDR_LUT_BYPASS_BASE_IDX 2 #define mmBIF_BX_DEV0_EPF0_VF13_MAILBOX_MSGBUF_TRN_DW0 0x0136 #define mmBIF_BX_DEV0_EPF0_VF13_MAILBOX_MSGBUF_TRN_DW0_BASE_IDX 2 #define mmBIF_BX_DEV0_EPF0_VF13_MAILBOX_MSGBUF_TRN_DW1 0x0137 #define mmBIF_BX_DEV0_EPF0_VF13_MAILBOX_MSGBUF_TRN_DW1_BASE_IDX 2 #define mmBIF_BX_DEV0_EPF0_VF13_MAILBOX_MSGBUF_TRN_DW2 0x0138 #define mmBIF_BX_DEV0_EPF0_VF13_MAILBOX_MSGBUF_TRN_DW2_BASE_IDX 2 #define mmBIF_BX_DEV0_EPF0_VF13_MAILBOX_MSGBUF_TRN_DW3 0x0139 #define mmBIF_BX_DEV0_EPF0_VF13_MAILBOX_MSGBUF_TRN_DW3_BASE_IDX 2 #define mmBIF_BX_DEV0_EPF0_VF13_MAILBOX_MSGBUF_RCV_DW0 0x013a #define mmBIF_BX_DEV0_EPF0_VF13_MAILBOX_MSGBUF_RCV_DW0_BASE_IDX 2 #define mmBIF_BX_DEV0_EPF0_VF13_MAILBOX_MSGBUF_RCV_DW1 0x013b #define mmBIF_BX_DEV0_EPF0_VF13_MAILBOX_MSGBUF_RCV_DW1_BASE_IDX 2 #define mmBIF_BX_DEV0_EPF0_VF13_MAILBOX_MSGBUF_RCV_DW2 0x013c #define mmBIF_BX_DEV0_EPF0_VF13_MAILBOX_MSGBUF_RCV_DW2_BASE_IDX 2 #define mmBIF_BX_DEV0_EPF0_VF13_MAILBOX_MSGBUF_RCV_DW3 0x013d #define mmBIF_BX_DEV0_EPF0_VF13_MAILBOX_MSGBUF_RCV_DW3_BASE_IDX 2 #define mmBIF_BX_DEV0_EPF0_VF13_MAILBOX_CONTROL 0x013e #define mmBIF_BX_DEV0_EPF0_VF13_MAILBOX_CONTROL_BASE_IDX 2 #define mmBIF_BX_DEV0_EPF0_VF13_MAILBOX_INT_CNTL 0x013f #define mmBIF_BX_DEV0_EPF0_VF13_MAILBOX_INT_CNTL_BASE_IDX 2 #define mmBIF_BX_DEV0_EPF0_VF13_BIF_VMHV_MAILBOX 0x0140 #define mmBIF_BX_DEV0_EPF0_VF13_BIF_VMHV_MAILBOX_BASE_IDX 2 // addressBlock: nbio_nbif0_rcc_dev0_epf0_vf13_BIFDEC2 // base address: 0x0 #define mmRCC_DEV0_EPF0_VF13_GFXMSIX_VECT0_ADDR_LO 0x0400 #define mmRCC_DEV0_EPF0_VF13_GFXMSIX_VECT0_ADDR_LO_BASE_IDX 3 #define mmRCC_DEV0_EPF0_VF13_GFXMSIX_VECT0_ADDR_HI 0x0401 #define mmRCC_DEV0_EPF0_VF13_GFXMSIX_VECT0_ADDR_HI_BASE_IDX 3 #define mmRCC_DEV0_EPF0_VF13_GFXMSIX_VECT0_MSG_DATA 0x0402 #define mmRCC_DEV0_EPF0_VF13_GFXMSIX_VECT0_MSG_DATA_BASE_IDX 3 #define mmRCC_DEV0_EPF0_VF13_GFXMSIX_VECT0_CONTROL 0x0403 #define mmRCC_DEV0_EPF0_VF13_GFXMSIX_VECT0_CONTROL_BASE_IDX 3 #define mmRCC_DEV0_EPF0_VF13_GFXMSIX_VECT1_ADDR_LO 0x0404 #define mmRCC_DEV0_EPF0_VF13_GFXMSIX_VECT1_ADDR_LO_BASE_IDX 3 #define mmRCC_DEV0_EPF0_VF13_GFXMSIX_VECT1_ADDR_HI 0x0405 #define mmRCC_DEV0_EPF0_VF13_GFXMSIX_VECT1_ADDR_HI_BASE_IDX 3 #define mmRCC_DEV0_EPF0_VF13_GFXMSIX_VECT1_MSG_DATA 0x0406 #define mmRCC_DEV0_EPF0_VF13_GFXMSIX_VECT1_MSG_DATA_BASE_IDX 3 #define mmRCC_DEV0_EPF0_VF13_GFXMSIX_VECT1_CONTROL 0x0407 #define mmRCC_DEV0_EPF0_VF13_GFXMSIX_VECT1_CONTROL_BASE_IDX 3 #define mmRCC_DEV0_EPF0_VF13_GFXMSIX_VECT2_ADDR_LO 0x0408 #define mmRCC_DEV0_EPF0_VF13_GFXMSIX_VECT2_ADDR_LO_BASE_IDX 3 #define mmRCC_DEV0_EPF0_VF13_GFXMSIX_VECT2_ADDR_HI 0x0409 #define mmRCC_DEV0_EPF0_VF13_GFXMSIX_VECT2_ADDR_HI_BASE_IDX 3 #define mmRCC_DEV0_EPF0_VF13_GFXMSIX_VECT2_MSG_DATA 0x040a #define mmRCC_DEV0_EPF0_VF13_GFXMSIX_VECT2_MSG_DATA_BASE_IDX 3 #define mmRCC_DEV0_EPF0_VF13_GFXMSIX_VECT2_CONTROL 0x040b #define mmRCC_DEV0_EPF0_VF13_GFXMSIX_VECT2_CONTROL_BASE_IDX 3 #define mmRCC_DEV0_EPF0_VF13_GFXMSIX_VECT3_ADDR_LO 0x040c #define mmRCC_DEV0_EPF0_VF13_GFXMSIX_VECT3_ADDR_LO_BASE_IDX 3 #define mmRCC_DEV0_EPF0_VF13_GFXMSIX_VECT3_ADDR_HI 0x040d #define mmRCC_DEV0_EPF0_VF13_GFXMSIX_VECT3_ADDR_HI_BASE_IDX 3 #define mmRCC_DEV0_EPF0_VF13_GFXMSIX_VECT3_MSG_DATA 0x040e #define mmRCC_DEV0_EPF0_VF13_GFXMSIX_VECT3_MSG_DATA_BASE_IDX 3 #define mmRCC_DEV0_EPF0_VF13_GFXMSIX_VECT3_CONTROL 0x040f #define mmRCC_DEV0_EPF0_VF13_GFXMSIX_VECT3_CONTROL_BASE_IDX 3 #define mmRCC_DEV0_EPF0_VF13_GFXMSIX_PBA 0x0800 #define mmRCC_DEV0_EPF0_VF13_GFXMSIX_PBA_BASE_IDX 3 // addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf14_SYSPFVFDEC // base address: 0x0 #define mmBIF_BX_DEV0_EPF0_VF14_MM_INDEX 0x0000 #define mmBIF_BX_DEV0_EPF0_VF14_MM_INDEX_BASE_IDX 0 #define mmBIF_BX_DEV0_EPF0_VF14_MM_DATA 0x0001 #define mmBIF_BX_DEV0_EPF0_VF14_MM_DATA_BASE_IDX 0 #define mmBIF_BX_DEV0_EPF0_VF14_MM_INDEX_HI 0x0006 #define mmBIF_BX_DEV0_EPF0_VF14_MM_INDEX_HI_BASE_IDX 0 // addressBlock: nbio_nbif0_rcc_dev0_epf0_vf14_BIFPFVFDEC1 // base address: 0x0 #define mmRCC_DEV0_EPF0_VF14_RCC_ERR_LOG 0x0085 #define mmRCC_DEV0_EPF0_VF14_RCC_ERR_LOG_BASE_IDX 2 #define mmRCC_DEV0_EPF0_VF14_RCC_DOORBELL_APER_EN 0x00c0 #define mmRCC_DEV0_EPF0_VF14_RCC_DOORBELL_APER_EN_BASE_IDX 2 #define mmRCC_DEV0_EPF0_VF14_RCC_CONFIG_MEMSIZE 0x00c3 #define mmRCC_DEV0_EPF0_VF14_RCC_CONFIG_MEMSIZE_BASE_IDX 2 #define mmRCC_DEV0_EPF0_VF14_RCC_CONFIG_RESERVED 0x00c4 #define mmRCC_DEV0_EPF0_VF14_RCC_CONFIG_RESERVED_BASE_IDX 2 #define mmRCC_DEV0_EPF0_VF14_RCC_IOV_FUNC_IDENTIFIER 0x00c5 #define mmRCC_DEV0_EPF0_VF14_RCC_IOV_FUNC_IDENTIFIER_BASE_IDX 2 // addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf14_BIFPFVFDEC1 // base address: 0x0 #define mmBIF_BX_DEV0_EPF0_VF14_BIF_BME_STATUS 0x00eb #define mmBIF_BX_DEV0_EPF0_VF14_BIF_BME_STATUS_BASE_IDX 2 #define mmBIF_BX_DEV0_EPF0_VF14_BIF_ATOMIC_ERR_LOG 0x00ec #define mmBIF_BX_DEV0_EPF0_VF14_BIF_ATOMIC_ERR_LOG_BASE_IDX 2 #define mmBIF_BX_DEV0_EPF0_VF14_DOORBELL_SELFRING_GPA_APER_BASE_HIGH 0x00f3 #define your_sha256_hashE_IDX 2 #define mmBIF_BX_DEV0_EPF0_VF14_DOORBELL_SELFRING_GPA_APER_BASE_LOW 0x00f4 #define your_sha256_hash_IDX 2 #define mmBIF_BX_DEV0_EPF0_VF14_DOORBELL_SELFRING_GPA_APER_CNTL 0x00f5 #define your_sha256_hash 2 #define mmBIF_BX_DEV0_EPF0_VF14_HDP_REG_COHERENCY_FLUSH_CNTL 0x00f6 #define mmBIF_BX_DEV0_EPF0_VF14_HDP_REG_COHERENCY_FLUSH_CNTL_BASE_IDX 2 #define mmBIF_BX_DEV0_EPF0_VF14_HDP_MEM_COHERENCY_FLUSH_CNTL 0x00f7 #define mmBIF_BX_DEV0_EPF0_VF14_HDP_MEM_COHERENCY_FLUSH_CNTL_BASE_IDX 2 #define mmBIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_REQ 0x0106 #define mmBIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_REQ_BASE_IDX 2 #define mmBIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_DONE 0x0107 #define mmBIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_DONE_BASE_IDX 2 #define mmBIF_BX_DEV0_EPF0_VF14_BIF_TRANS_PENDING 0x0108 #define mmBIF_BX_DEV0_EPF0_VF14_BIF_TRANS_PENDING_BASE_IDX 2 #define mmBIF_BX_DEV0_EPF0_VF14_NBIF_GFX_ADDR_LUT_BYPASS 0x0112 #define mmBIF_BX_DEV0_EPF0_VF14_NBIF_GFX_ADDR_LUT_BYPASS_BASE_IDX 2 #define mmBIF_BX_DEV0_EPF0_VF14_MAILBOX_MSGBUF_TRN_DW0 0x0136 #define mmBIF_BX_DEV0_EPF0_VF14_MAILBOX_MSGBUF_TRN_DW0_BASE_IDX 2 #define mmBIF_BX_DEV0_EPF0_VF14_MAILBOX_MSGBUF_TRN_DW1 0x0137 #define mmBIF_BX_DEV0_EPF0_VF14_MAILBOX_MSGBUF_TRN_DW1_BASE_IDX 2 #define mmBIF_BX_DEV0_EPF0_VF14_MAILBOX_MSGBUF_TRN_DW2 0x0138 #define mmBIF_BX_DEV0_EPF0_VF14_MAILBOX_MSGBUF_TRN_DW2_BASE_IDX 2 #define mmBIF_BX_DEV0_EPF0_VF14_MAILBOX_MSGBUF_TRN_DW3 0x0139 #define mmBIF_BX_DEV0_EPF0_VF14_MAILBOX_MSGBUF_TRN_DW3_BASE_IDX 2 #define mmBIF_BX_DEV0_EPF0_VF14_MAILBOX_MSGBUF_RCV_DW0 0x013a #define mmBIF_BX_DEV0_EPF0_VF14_MAILBOX_MSGBUF_RCV_DW0_BASE_IDX 2 #define mmBIF_BX_DEV0_EPF0_VF14_MAILBOX_MSGBUF_RCV_DW1 0x013b #define mmBIF_BX_DEV0_EPF0_VF14_MAILBOX_MSGBUF_RCV_DW1_BASE_IDX 2 #define mmBIF_BX_DEV0_EPF0_VF14_MAILBOX_MSGBUF_RCV_DW2 0x013c #define mmBIF_BX_DEV0_EPF0_VF14_MAILBOX_MSGBUF_RCV_DW2_BASE_IDX 2 #define mmBIF_BX_DEV0_EPF0_VF14_MAILBOX_MSGBUF_RCV_DW3 0x013d #define mmBIF_BX_DEV0_EPF0_VF14_MAILBOX_MSGBUF_RCV_DW3_BASE_IDX 2 #define mmBIF_BX_DEV0_EPF0_VF14_MAILBOX_CONTROL 0x013e #define mmBIF_BX_DEV0_EPF0_VF14_MAILBOX_CONTROL_BASE_IDX 2 #define mmBIF_BX_DEV0_EPF0_VF14_MAILBOX_INT_CNTL 0x013f #define mmBIF_BX_DEV0_EPF0_VF14_MAILBOX_INT_CNTL_BASE_IDX 2 #define mmBIF_BX_DEV0_EPF0_VF14_BIF_VMHV_MAILBOX 0x0140 #define mmBIF_BX_DEV0_EPF0_VF14_BIF_VMHV_MAILBOX_BASE_IDX 2 // addressBlock: nbio_nbif0_rcc_dev0_epf0_vf14_BIFDEC2 // base address: 0x0 #define mmRCC_DEV0_EPF0_VF14_GFXMSIX_VECT0_ADDR_LO 0x0400 #define mmRCC_DEV0_EPF0_VF14_GFXMSIX_VECT0_ADDR_LO_BASE_IDX 3 #define mmRCC_DEV0_EPF0_VF14_GFXMSIX_VECT0_ADDR_HI 0x0401 #define mmRCC_DEV0_EPF0_VF14_GFXMSIX_VECT0_ADDR_HI_BASE_IDX 3 #define mmRCC_DEV0_EPF0_VF14_GFXMSIX_VECT0_MSG_DATA 0x0402 #define mmRCC_DEV0_EPF0_VF14_GFXMSIX_VECT0_MSG_DATA_BASE_IDX 3 #define mmRCC_DEV0_EPF0_VF14_GFXMSIX_VECT0_CONTROL 0x0403 #define mmRCC_DEV0_EPF0_VF14_GFXMSIX_VECT0_CONTROL_BASE_IDX 3 #define mmRCC_DEV0_EPF0_VF14_GFXMSIX_VECT1_ADDR_LO 0x0404 #define mmRCC_DEV0_EPF0_VF14_GFXMSIX_VECT1_ADDR_LO_BASE_IDX 3 #define mmRCC_DEV0_EPF0_VF14_GFXMSIX_VECT1_ADDR_HI 0x0405 #define mmRCC_DEV0_EPF0_VF14_GFXMSIX_VECT1_ADDR_HI_BASE_IDX 3 #define mmRCC_DEV0_EPF0_VF14_GFXMSIX_VECT1_MSG_DATA 0x0406 #define mmRCC_DEV0_EPF0_VF14_GFXMSIX_VECT1_MSG_DATA_BASE_IDX 3 #define mmRCC_DEV0_EPF0_VF14_GFXMSIX_VECT1_CONTROL 0x0407 #define mmRCC_DEV0_EPF0_VF14_GFXMSIX_VECT1_CONTROL_BASE_IDX 3 #define mmRCC_DEV0_EPF0_VF14_GFXMSIX_VECT2_ADDR_LO 0x0408 #define mmRCC_DEV0_EPF0_VF14_GFXMSIX_VECT2_ADDR_LO_BASE_IDX 3 #define mmRCC_DEV0_EPF0_VF14_GFXMSIX_VECT2_ADDR_HI 0x0409 #define mmRCC_DEV0_EPF0_VF14_GFXMSIX_VECT2_ADDR_HI_BASE_IDX 3 #define mmRCC_DEV0_EPF0_VF14_GFXMSIX_VECT2_MSG_DATA 0x040a #define mmRCC_DEV0_EPF0_VF14_GFXMSIX_VECT2_MSG_DATA_BASE_IDX 3 #define mmRCC_DEV0_EPF0_VF14_GFXMSIX_VECT2_CONTROL 0x040b #define mmRCC_DEV0_EPF0_VF14_GFXMSIX_VECT2_CONTROL_BASE_IDX 3 #define mmRCC_DEV0_EPF0_VF14_GFXMSIX_VECT3_ADDR_LO 0x040c #define mmRCC_DEV0_EPF0_VF14_GFXMSIX_VECT3_ADDR_LO_BASE_IDX 3 #define mmRCC_DEV0_EPF0_VF14_GFXMSIX_VECT3_ADDR_HI 0x040d #define mmRCC_DEV0_EPF0_VF14_GFXMSIX_VECT3_ADDR_HI_BASE_IDX 3 #define mmRCC_DEV0_EPF0_VF14_GFXMSIX_VECT3_MSG_DATA 0x040e #define mmRCC_DEV0_EPF0_VF14_GFXMSIX_VECT3_MSG_DATA_BASE_IDX 3 #define mmRCC_DEV0_EPF0_VF14_GFXMSIX_VECT3_CONTROL 0x040f #define mmRCC_DEV0_EPF0_VF14_GFXMSIX_VECT3_CONTROL_BASE_IDX 3 #define mmRCC_DEV0_EPF0_VF14_GFXMSIX_PBA 0x0800 #define mmRCC_DEV0_EPF0_VF14_GFXMSIX_PBA_BASE_IDX 3 // addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf15_SYSPFVFDEC // base address: 0x0 #define mmBIF_BX_DEV0_EPF0_VF15_MM_INDEX 0x0000 #define mmBIF_BX_DEV0_EPF0_VF15_MM_INDEX_BASE_IDX 0 #define mmBIF_BX_DEV0_EPF0_VF15_MM_DATA 0x0001 #define mmBIF_BX_DEV0_EPF0_VF15_MM_DATA_BASE_IDX 0 #define mmBIF_BX_DEV0_EPF0_VF15_MM_INDEX_HI 0x0006 #define mmBIF_BX_DEV0_EPF0_VF15_MM_INDEX_HI_BASE_IDX 0 // addressBlock: nbio_nbif0_rcc_dev0_epf0_vf15_BIFPFVFDEC1 // base address: 0x0 #define mmRCC_DEV0_EPF0_VF15_RCC_ERR_LOG 0x0085 #define mmRCC_DEV0_EPF0_VF15_RCC_ERR_LOG_BASE_IDX 2 #define mmRCC_DEV0_EPF0_VF15_RCC_DOORBELL_APER_EN 0x00c0 #define mmRCC_DEV0_EPF0_VF15_RCC_DOORBELL_APER_EN_BASE_IDX 2 #define mmRCC_DEV0_EPF0_VF15_RCC_CONFIG_MEMSIZE 0x00c3 #define mmRCC_DEV0_EPF0_VF15_RCC_CONFIG_MEMSIZE_BASE_IDX 2 #define mmRCC_DEV0_EPF0_VF15_RCC_CONFIG_RESERVED 0x00c4 #define mmRCC_DEV0_EPF0_VF15_RCC_CONFIG_RESERVED_BASE_IDX 2 #define mmRCC_DEV0_EPF0_VF15_RCC_IOV_FUNC_IDENTIFIER 0x00c5 #define mmRCC_DEV0_EPF0_VF15_RCC_IOV_FUNC_IDENTIFIER_BASE_IDX 2 // addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf15_BIFPFVFDEC1 // base address: 0x0 #define mmBIF_BX_DEV0_EPF0_VF15_BIF_BME_STATUS 0x00eb #define mmBIF_BX_DEV0_EPF0_VF15_BIF_BME_STATUS_BASE_IDX 2 #define mmBIF_BX_DEV0_EPF0_VF15_BIF_ATOMIC_ERR_LOG 0x00ec #define mmBIF_BX_DEV0_EPF0_VF15_BIF_ATOMIC_ERR_LOG_BASE_IDX 2 #define mmBIF_BX_DEV0_EPF0_VF15_DOORBELL_SELFRING_GPA_APER_BASE_HIGH 0x00f3 #define your_sha256_hashE_IDX 2 #define mmBIF_BX_DEV0_EPF0_VF15_DOORBELL_SELFRING_GPA_APER_BASE_LOW 0x00f4 #define your_sha256_hash_IDX 2 #define mmBIF_BX_DEV0_EPF0_VF15_DOORBELL_SELFRING_GPA_APER_CNTL 0x00f5 #define your_sha256_hash 2 #define mmBIF_BX_DEV0_EPF0_VF15_HDP_REG_COHERENCY_FLUSH_CNTL 0x00f6 #define mmBIF_BX_DEV0_EPF0_VF15_HDP_REG_COHERENCY_FLUSH_CNTL_BASE_IDX 2 #define mmBIF_BX_DEV0_EPF0_VF15_HDP_MEM_COHERENCY_FLUSH_CNTL 0x00f7 #define mmBIF_BX_DEV0_EPF0_VF15_HDP_MEM_COHERENCY_FLUSH_CNTL_BASE_IDX 2 #define mmBIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_REQ 0x0106 #define mmBIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_REQ_BASE_IDX 2 #define mmBIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_DONE 0x0107 #define mmBIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_DONE_BASE_IDX 2 #define mmBIF_BX_DEV0_EPF0_VF15_BIF_TRANS_PENDING 0x0108 #define mmBIF_BX_DEV0_EPF0_VF15_BIF_TRANS_PENDING_BASE_IDX 2 #define mmBIF_BX_DEV0_EPF0_VF15_NBIF_GFX_ADDR_LUT_BYPASS 0x0112 #define mmBIF_BX_DEV0_EPF0_VF15_NBIF_GFX_ADDR_LUT_BYPASS_BASE_IDX 2 #define mmBIF_BX_DEV0_EPF0_VF15_MAILBOX_MSGBUF_TRN_DW0 0x0136 #define mmBIF_BX_DEV0_EPF0_VF15_MAILBOX_MSGBUF_TRN_DW0_BASE_IDX 2 #define mmBIF_BX_DEV0_EPF0_VF15_MAILBOX_MSGBUF_TRN_DW1 0x0137 #define mmBIF_BX_DEV0_EPF0_VF15_MAILBOX_MSGBUF_TRN_DW1_BASE_IDX 2 #define mmBIF_BX_DEV0_EPF0_VF15_MAILBOX_MSGBUF_TRN_DW2 0x0138 #define mmBIF_BX_DEV0_EPF0_VF15_MAILBOX_MSGBUF_TRN_DW2_BASE_IDX 2 #define mmBIF_BX_DEV0_EPF0_VF15_MAILBOX_MSGBUF_TRN_DW3 0x0139 #define mmBIF_BX_DEV0_EPF0_VF15_MAILBOX_MSGBUF_TRN_DW3_BASE_IDX 2 #define mmBIF_BX_DEV0_EPF0_VF15_MAILBOX_MSGBUF_RCV_DW0 0x013a #define mmBIF_BX_DEV0_EPF0_VF15_MAILBOX_MSGBUF_RCV_DW0_BASE_IDX 2 #define mmBIF_BX_DEV0_EPF0_VF15_MAILBOX_MSGBUF_RCV_DW1 0x013b #define mmBIF_BX_DEV0_EPF0_VF15_MAILBOX_MSGBUF_RCV_DW1_BASE_IDX 2 #define mmBIF_BX_DEV0_EPF0_VF15_MAILBOX_MSGBUF_RCV_DW2 0x013c #define mmBIF_BX_DEV0_EPF0_VF15_MAILBOX_MSGBUF_RCV_DW2_BASE_IDX 2 #define mmBIF_BX_DEV0_EPF0_VF15_MAILBOX_MSGBUF_RCV_DW3 0x013d #define mmBIF_BX_DEV0_EPF0_VF15_MAILBOX_MSGBUF_RCV_DW3_BASE_IDX 2 #define mmBIF_BX_DEV0_EPF0_VF15_MAILBOX_CONTROL 0x013e #define mmBIF_BX_DEV0_EPF0_VF15_MAILBOX_CONTROL_BASE_IDX 2 #define mmBIF_BX_DEV0_EPF0_VF15_MAILBOX_INT_CNTL 0x013f #define mmBIF_BX_DEV0_EPF0_VF15_MAILBOX_INT_CNTL_BASE_IDX 2 #define mmBIF_BX_DEV0_EPF0_VF15_BIF_VMHV_MAILBOX 0x0140 #define mmBIF_BX_DEV0_EPF0_VF15_BIF_VMHV_MAILBOX_BASE_IDX 2 // addressBlock: nbio_nbif0_rcc_dev0_epf0_vf15_BIFDEC2 // base address: 0x0 #define mmRCC_DEV0_EPF0_VF15_GFXMSIX_VECT0_ADDR_LO 0x0400 #define mmRCC_DEV0_EPF0_VF15_GFXMSIX_VECT0_ADDR_LO_BASE_IDX 3 #define mmRCC_DEV0_EPF0_VF15_GFXMSIX_VECT0_ADDR_HI 0x0401 #define mmRCC_DEV0_EPF0_VF15_GFXMSIX_VECT0_ADDR_HI_BASE_IDX 3 #define mmRCC_DEV0_EPF0_VF15_GFXMSIX_VECT0_MSG_DATA 0x0402 #define mmRCC_DEV0_EPF0_VF15_GFXMSIX_VECT0_MSG_DATA_BASE_IDX 3 #define mmRCC_DEV0_EPF0_VF15_GFXMSIX_VECT0_CONTROL 0x0403 #define mmRCC_DEV0_EPF0_VF15_GFXMSIX_VECT0_CONTROL_BASE_IDX 3 #define mmRCC_DEV0_EPF0_VF15_GFXMSIX_VECT1_ADDR_LO 0x0404 #define mmRCC_DEV0_EPF0_VF15_GFXMSIX_VECT1_ADDR_LO_BASE_IDX 3 #define mmRCC_DEV0_EPF0_VF15_GFXMSIX_VECT1_ADDR_HI 0x0405 #define mmRCC_DEV0_EPF0_VF15_GFXMSIX_VECT1_ADDR_HI_BASE_IDX 3 #define mmRCC_DEV0_EPF0_VF15_GFXMSIX_VECT1_MSG_DATA 0x0406 #define mmRCC_DEV0_EPF0_VF15_GFXMSIX_VECT1_MSG_DATA_BASE_IDX 3 #define mmRCC_DEV0_EPF0_VF15_GFXMSIX_VECT1_CONTROL 0x0407 #define mmRCC_DEV0_EPF0_VF15_GFXMSIX_VECT1_CONTROL_BASE_IDX 3 #define mmRCC_DEV0_EPF0_VF15_GFXMSIX_VECT2_ADDR_LO 0x0408 #define mmRCC_DEV0_EPF0_VF15_GFXMSIX_VECT2_ADDR_LO_BASE_IDX 3 #define mmRCC_DEV0_EPF0_VF15_GFXMSIX_VECT2_ADDR_HI 0x0409 #define mmRCC_DEV0_EPF0_VF15_GFXMSIX_VECT2_ADDR_HI_BASE_IDX 3 #define mmRCC_DEV0_EPF0_VF15_GFXMSIX_VECT2_MSG_DATA 0x040a #define mmRCC_DEV0_EPF0_VF15_GFXMSIX_VECT2_MSG_DATA_BASE_IDX 3 #define mmRCC_DEV0_EPF0_VF15_GFXMSIX_VECT2_CONTROL 0x040b #define mmRCC_DEV0_EPF0_VF15_GFXMSIX_VECT2_CONTROL_BASE_IDX 3 #define mmRCC_DEV0_EPF0_VF15_GFXMSIX_VECT3_ADDR_LO 0x040c #define mmRCC_DEV0_EPF0_VF15_GFXMSIX_VECT3_ADDR_LO_BASE_IDX 3 #define mmRCC_DEV0_EPF0_VF15_GFXMSIX_VECT3_ADDR_HI 0x040d #define mmRCC_DEV0_EPF0_VF15_GFXMSIX_VECT3_ADDR_HI_BASE_IDX 3 #define mmRCC_DEV0_EPF0_VF15_GFXMSIX_VECT3_MSG_DATA 0x040e #define mmRCC_DEV0_EPF0_VF15_GFXMSIX_VECT3_MSG_DATA_BASE_IDX 3 #define mmRCC_DEV0_EPF0_VF15_GFXMSIX_VECT3_CONTROL 0x040f #define mmRCC_DEV0_EPF0_VF15_GFXMSIX_VECT3_CONTROL_BASE_IDX 3 #define mmRCC_DEV0_EPF0_VF15_GFXMSIX_PBA 0x0800 #define mmRCC_DEV0_EPF0_VF15_GFXMSIX_PBA_BASE_IDX 3 // addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf16_SYSPFVFDEC // base address: 0x0 #define mmBIF_BX_DEV0_EPF0_VF16_MM_INDEX 0x0000 #define mmBIF_BX_DEV0_EPF0_VF16_MM_INDEX_BASE_IDX 0 #define mmBIF_BX_DEV0_EPF0_VF16_MM_DATA 0x0001 #define mmBIF_BX_DEV0_EPF0_VF16_MM_DATA_BASE_IDX 0 #define mmBIF_BX_DEV0_EPF0_VF16_MM_INDEX_HI 0x0006 #define mmBIF_BX_DEV0_EPF0_VF16_MM_INDEX_HI_BASE_IDX 0 // addressBlock: nbio_nbif0_rcc_dev0_epf0_vf16_BIFPFVFDEC1 // base address: 0x0 #define mmRCC_DEV0_EPF0_VF16_RCC_ERR_LOG 0x0085 #define mmRCC_DEV0_EPF0_VF16_RCC_ERR_LOG_BASE_IDX 2 #define mmRCC_DEV0_EPF0_VF16_RCC_DOORBELL_APER_EN 0x00c0 #define mmRCC_DEV0_EPF0_VF16_RCC_DOORBELL_APER_EN_BASE_IDX 2 #define mmRCC_DEV0_EPF0_VF16_RCC_CONFIG_MEMSIZE 0x00c3 #define mmRCC_DEV0_EPF0_VF16_RCC_CONFIG_MEMSIZE_BASE_IDX 2 #define mmRCC_DEV0_EPF0_VF16_RCC_CONFIG_RESERVED 0x00c4 #define mmRCC_DEV0_EPF0_VF16_RCC_CONFIG_RESERVED_BASE_IDX 2 #define mmRCC_DEV0_EPF0_VF16_RCC_IOV_FUNC_IDENTIFIER 0x00c5 #define mmRCC_DEV0_EPF0_VF16_RCC_IOV_FUNC_IDENTIFIER_BASE_IDX 2 // addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf16_BIFPFVFDEC1 // base address: 0x0 #define mmBIF_BX_DEV0_EPF0_VF16_BIF_BME_STATUS 0x00eb #define mmBIF_BX_DEV0_EPF0_VF16_BIF_BME_STATUS_BASE_IDX 2 #define mmBIF_BX_DEV0_EPF0_VF16_BIF_ATOMIC_ERR_LOG 0x00ec #define mmBIF_BX_DEV0_EPF0_VF16_BIF_ATOMIC_ERR_LOG_BASE_IDX 2 #define mmBIF_BX_DEV0_EPF0_VF16_DOORBELL_SELFRING_GPA_APER_BASE_HIGH 0x00f3 #define your_sha256_hashE_IDX 2 #define mmBIF_BX_DEV0_EPF0_VF16_DOORBELL_SELFRING_GPA_APER_BASE_LOW 0x00f4 #define your_sha256_hash_IDX 2 #define mmBIF_BX_DEV0_EPF0_VF16_DOORBELL_SELFRING_GPA_APER_CNTL 0x00f5 #define your_sha256_hash 2 #define mmBIF_BX_DEV0_EPF0_VF16_HDP_REG_COHERENCY_FLUSH_CNTL 0x00f6 #define mmBIF_BX_DEV0_EPF0_VF16_HDP_REG_COHERENCY_FLUSH_CNTL_BASE_IDX 2 #define mmBIF_BX_DEV0_EPF0_VF16_HDP_MEM_COHERENCY_FLUSH_CNTL 0x00f7 #define mmBIF_BX_DEV0_EPF0_VF16_HDP_MEM_COHERENCY_FLUSH_CNTL_BASE_IDX 2 #define mmBIF_BX_DEV0_EPF0_VF16_GPU_HDP_FLUSH_REQ 0x0106 #define mmBIF_BX_DEV0_EPF0_VF16_GPU_HDP_FLUSH_REQ_BASE_IDX 2 #define mmBIF_BX_DEV0_EPF0_VF16_GPU_HDP_FLUSH_DONE 0x0107 #define mmBIF_BX_DEV0_EPF0_VF16_GPU_HDP_FLUSH_DONE_BASE_IDX 2 #define mmBIF_BX_DEV0_EPF0_VF16_BIF_TRANS_PENDING 0x0108 #define mmBIF_BX_DEV0_EPF0_VF16_BIF_TRANS_PENDING_BASE_IDX 2 #define mmBIF_BX_DEV0_EPF0_VF16_NBIF_GFX_ADDR_LUT_BYPASS 0x0112 #define mmBIF_BX_DEV0_EPF0_VF16_NBIF_GFX_ADDR_LUT_BYPASS_BASE_IDX 2 #define mmBIF_BX_DEV0_EPF0_VF16_MAILBOX_MSGBUF_TRN_DW0 0x0136 #define mmBIF_BX_DEV0_EPF0_VF16_MAILBOX_MSGBUF_TRN_DW0_BASE_IDX 2 #define mmBIF_BX_DEV0_EPF0_VF16_MAILBOX_MSGBUF_TRN_DW1 0x0137 #define mmBIF_BX_DEV0_EPF0_VF16_MAILBOX_MSGBUF_TRN_DW1_BASE_IDX 2 #define mmBIF_BX_DEV0_EPF0_VF16_MAILBOX_MSGBUF_TRN_DW2 0x0138 #define mmBIF_BX_DEV0_EPF0_VF16_MAILBOX_MSGBUF_TRN_DW2_BASE_IDX 2 #define mmBIF_BX_DEV0_EPF0_VF16_MAILBOX_MSGBUF_TRN_DW3 0x0139 #define mmBIF_BX_DEV0_EPF0_VF16_MAILBOX_MSGBUF_TRN_DW3_BASE_IDX 2 #define mmBIF_BX_DEV0_EPF0_VF16_MAILBOX_MSGBUF_RCV_DW0 0x013a #define mmBIF_BX_DEV0_EPF0_VF16_MAILBOX_MSGBUF_RCV_DW0_BASE_IDX 2 #define mmBIF_BX_DEV0_EPF0_VF16_MAILBOX_MSGBUF_RCV_DW1 0x013b #define mmBIF_BX_DEV0_EPF0_VF16_MAILBOX_MSGBUF_RCV_DW1_BASE_IDX 2 #define mmBIF_BX_DEV0_EPF0_VF16_MAILBOX_MSGBUF_RCV_DW2 0x013c #define mmBIF_BX_DEV0_EPF0_VF16_MAILBOX_MSGBUF_RCV_DW2_BASE_IDX 2 #define mmBIF_BX_DEV0_EPF0_VF16_MAILBOX_MSGBUF_RCV_DW3 0x013d #define mmBIF_BX_DEV0_EPF0_VF16_MAILBOX_MSGBUF_RCV_DW3_BASE_IDX 2 #define mmBIF_BX_DEV0_EPF0_VF16_MAILBOX_CONTROL 0x013e #define mmBIF_BX_DEV0_EPF0_VF16_MAILBOX_CONTROL_BASE_IDX 2 #define mmBIF_BX_DEV0_EPF0_VF16_MAILBOX_INT_CNTL 0x013f #define mmBIF_BX_DEV0_EPF0_VF16_MAILBOX_INT_CNTL_BASE_IDX 2 #define mmBIF_BX_DEV0_EPF0_VF16_BIF_VMHV_MAILBOX 0x0140 #define mmBIF_BX_DEV0_EPF0_VF16_BIF_VMHV_MAILBOX_BASE_IDX 2 // addressBlock: nbio_nbif0_rcc_dev0_epf0_vf16_BIFDEC2 // base address: 0x0 #define mmRCC_DEV0_EPF0_VF16_GFXMSIX_VECT0_ADDR_LO 0x0400 #define mmRCC_DEV0_EPF0_VF16_GFXMSIX_VECT0_ADDR_LO_BASE_IDX 3 #define mmRCC_DEV0_EPF0_VF16_GFXMSIX_VECT0_ADDR_HI 0x0401 #define mmRCC_DEV0_EPF0_VF16_GFXMSIX_VECT0_ADDR_HI_BASE_IDX 3 #define mmRCC_DEV0_EPF0_VF16_GFXMSIX_VECT0_MSG_DATA 0x0402 #define mmRCC_DEV0_EPF0_VF16_GFXMSIX_VECT0_MSG_DATA_BASE_IDX 3 #define mmRCC_DEV0_EPF0_VF16_GFXMSIX_VECT0_CONTROL 0x0403 #define mmRCC_DEV0_EPF0_VF16_GFXMSIX_VECT0_CONTROL_BASE_IDX 3 #define mmRCC_DEV0_EPF0_VF16_GFXMSIX_VECT1_ADDR_LO 0x0404 #define mmRCC_DEV0_EPF0_VF16_GFXMSIX_VECT1_ADDR_LO_BASE_IDX 3 #define mmRCC_DEV0_EPF0_VF16_GFXMSIX_VECT1_ADDR_HI 0x0405 #define mmRCC_DEV0_EPF0_VF16_GFXMSIX_VECT1_ADDR_HI_BASE_IDX 3 #define mmRCC_DEV0_EPF0_VF16_GFXMSIX_VECT1_MSG_DATA 0x0406 #define mmRCC_DEV0_EPF0_VF16_GFXMSIX_VECT1_MSG_DATA_BASE_IDX 3 #define mmRCC_DEV0_EPF0_VF16_GFXMSIX_VECT1_CONTROL 0x0407 #define mmRCC_DEV0_EPF0_VF16_GFXMSIX_VECT1_CONTROL_BASE_IDX 3 #define mmRCC_DEV0_EPF0_VF16_GFXMSIX_VECT2_ADDR_LO 0x0408 #define mmRCC_DEV0_EPF0_VF16_GFXMSIX_VECT2_ADDR_LO_BASE_IDX 3 #define mmRCC_DEV0_EPF0_VF16_GFXMSIX_VECT2_ADDR_HI 0x0409 #define mmRCC_DEV0_EPF0_VF16_GFXMSIX_VECT2_ADDR_HI_BASE_IDX 3 #define mmRCC_DEV0_EPF0_VF16_GFXMSIX_VECT2_MSG_DATA 0x040a #define mmRCC_DEV0_EPF0_VF16_GFXMSIX_VECT2_MSG_DATA_BASE_IDX 3 #define mmRCC_DEV0_EPF0_VF16_GFXMSIX_VECT2_CONTROL 0x040b #define mmRCC_DEV0_EPF0_VF16_GFXMSIX_VECT2_CONTROL_BASE_IDX 3 #define mmRCC_DEV0_EPF0_VF16_GFXMSIX_VECT3_ADDR_LO 0x040c #define mmRCC_DEV0_EPF0_VF16_GFXMSIX_VECT3_ADDR_LO_BASE_IDX 3 #define mmRCC_DEV0_EPF0_VF16_GFXMSIX_VECT3_ADDR_HI 0x040d #define mmRCC_DEV0_EPF0_VF16_GFXMSIX_VECT3_ADDR_HI_BASE_IDX 3 #define mmRCC_DEV0_EPF0_VF16_GFXMSIX_VECT3_MSG_DATA 0x040e #define mmRCC_DEV0_EPF0_VF16_GFXMSIX_VECT3_MSG_DATA_BASE_IDX 3 #define mmRCC_DEV0_EPF0_VF16_GFXMSIX_VECT3_CONTROL 0x040f #define mmRCC_DEV0_EPF0_VF16_GFXMSIX_VECT3_CONTROL_BASE_IDX 3 #define mmRCC_DEV0_EPF0_VF16_GFXMSIX_PBA 0x0800 #define mmRCC_DEV0_EPF0_VF16_GFXMSIX_PBA_BASE_IDX 3 // addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf17_SYSPFVFDEC // base address: 0x0 #define mmBIF_BX_DEV0_EPF0_VF17_MM_INDEX 0x0000 #define mmBIF_BX_DEV0_EPF0_VF17_MM_INDEX_BASE_IDX 0 #define mmBIF_BX_DEV0_EPF0_VF17_MM_DATA 0x0001 #define mmBIF_BX_DEV0_EPF0_VF17_MM_DATA_BASE_IDX 0 #define mmBIF_BX_DEV0_EPF0_VF17_MM_INDEX_HI 0x0006 #define mmBIF_BX_DEV0_EPF0_VF17_MM_INDEX_HI_BASE_IDX 0 // addressBlock: nbio_nbif0_rcc_dev0_epf0_vf17_BIFPFVFDEC1 // base address: 0x0 #define mmRCC_DEV0_EPF0_VF17_RCC_ERR_LOG 0x0085 #define mmRCC_DEV0_EPF0_VF17_RCC_ERR_LOG_BASE_IDX 2 #define mmRCC_DEV0_EPF0_VF17_RCC_DOORBELL_APER_EN 0x00c0 #define mmRCC_DEV0_EPF0_VF17_RCC_DOORBELL_APER_EN_BASE_IDX 2 #define mmRCC_DEV0_EPF0_VF17_RCC_CONFIG_MEMSIZE 0x00c3 #define mmRCC_DEV0_EPF0_VF17_RCC_CONFIG_MEMSIZE_BASE_IDX 2 #define mmRCC_DEV0_EPF0_VF17_RCC_CONFIG_RESERVED 0x00c4 #define mmRCC_DEV0_EPF0_VF17_RCC_CONFIG_RESERVED_BASE_IDX 2 #define mmRCC_DEV0_EPF0_VF17_RCC_IOV_FUNC_IDENTIFIER 0x00c5 #define mmRCC_DEV0_EPF0_VF17_RCC_IOV_FUNC_IDENTIFIER_BASE_IDX 2 // addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf17_BIFPFVFDEC1 // base address: 0x0 #define mmBIF_BX_DEV0_EPF0_VF17_BIF_BME_STATUS 0x00eb #define mmBIF_BX_DEV0_EPF0_VF17_BIF_BME_STATUS_BASE_IDX 2 #define mmBIF_BX_DEV0_EPF0_VF17_BIF_ATOMIC_ERR_LOG 0x00ec #define mmBIF_BX_DEV0_EPF0_VF17_BIF_ATOMIC_ERR_LOG_BASE_IDX 2 #define mmBIF_BX_DEV0_EPF0_VF17_DOORBELL_SELFRING_GPA_APER_BASE_HIGH 0x00f3 #define your_sha256_hashE_IDX 2 #define mmBIF_BX_DEV0_EPF0_VF17_DOORBELL_SELFRING_GPA_APER_BASE_LOW 0x00f4 #define your_sha256_hash_IDX 2 #define mmBIF_BX_DEV0_EPF0_VF17_DOORBELL_SELFRING_GPA_APER_CNTL 0x00f5 #define your_sha256_hash 2 #define mmBIF_BX_DEV0_EPF0_VF17_HDP_REG_COHERENCY_FLUSH_CNTL 0x00f6 #define mmBIF_BX_DEV0_EPF0_VF17_HDP_REG_COHERENCY_FLUSH_CNTL_BASE_IDX 2 #define mmBIF_BX_DEV0_EPF0_VF17_HDP_MEM_COHERENCY_FLUSH_CNTL 0x00f7 #define mmBIF_BX_DEV0_EPF0_VF17_HDP_MEM_COHERENCY_FLUSH_CNTL_BASE_IDX 2 #define mmBIF_BX_DEV0_EPF0_VF17_GPU_HDP_FLUSH_REQ 0x0106 #define mmBIF_BX_DEV0_EPF0_VF17_GPU_HDP_FLUSH_REQ_BASE_IDX 2 #define mmBIF_BX_DEV0_EPF0_VF17_GPU_HDP_FLUSH_DONE 0x0107 #define mmBIF_BX_DEV0_EPF0_VF17_GPU_HDP_FLUSH_DONE_BASE_IDX 2 #define mmBIF_BX_DEV0_EPF0_VF17_BIF_TRANS_PENDING 0x0108 #define mmBIF_BX_DEV0_EPF0_VF17_BIF_TRANS_PENDING_BASE_IDX 2 #define mmBIF_BX_DEV0_EPF0_VF17_NBIF_GFX_ADDR_LUT_BYPASS 0x0112 #define mmBIF_BX_DEV0_EPF0_VF17_NBIF_GFX_ADDR_LUT_BYPASS_BASE_IDX 2 #define mmBIF_BX_DEV0_EPF0_VF17_MAILBOX_MSGBUF_TRN_DW0 0x0136 #define mmBIF_BX_DEV0_EPF0_VF17_MAILBOX_MSGBUF_TRN_DW0_BASE_IDX 2 #define mmBIF_BX_DEV0_EPF0_VF17_MAILBOX_MSGBUF_TRN_DW1 0x0137 #define mmBIF_BX_DEV0_EPF0_VF17_MAILBOX_MSGBUF_TRN_DW1_BASE_IDX 2 #define mmBIF_BX_DEV0_EPF0_VF17_MAILBOX_MSGBUF_TRN_DW2 0x0138 #define mmBIF_BX_DEV0_EPF0_VF17_MAILBOX_MSGBUF_TRN_DW2_BASE_IDX 2 #define mmBIF_BX_DEV0_EPF0_VF17_MAILBOX_MSGBUF_TRN_DW3 0x0139 #define mmBIF_BX_DEV0_EPF0_VF17_MAILBOX_MSGBUF_TRN_DW3_BASE_IDX 2 #define mmBIF_BX_DEV0_EPF0_VF17_MAILBOX_MSGBUF_RCV_DW0 0x013a #define mmBIF_BX_DEV0_EPF0_VF17_MAILBOX_MSGBUF_RCV_DW0_BASE_IDX 2 #define mmBIF_BX_DEV0_EPF0_VF17_MAILBOX_MSGBUF_RCV_DW1 0x013b #define mmBIF_BX_DEV0_EPF0_VF17_MAILBOX_MSGBUF_RCV_DW1_BASE_IDX 2 #define mmBIF_BX_DEV0_EPF0_VF17_MAILBOX_MSGBUF_RCV_DW2 0x013c #define mmBIF_BX_DEV0_EPF0_VF17_MAILBOX_MSGBUF_RCV_DW2_BASE_IDX 2 #define mmBIF_BX_DEV0_EPF0_VF17_MAILBOX_MSGBUF_RCV_DW3 0x013d #define mmBIF_BX_DEV0_EPF0_VF17_MAILBOX_MSGBUF_RCV_DW3_BASE_IDX 2 #define mmBIF_BX_DEV0_EPF0_VF17_MAILBOX_CONTROL 0x013e #define mmBIF_BX_DEV0_EPF0_VF17_MAILBOX_CONTROL_BASE_IDX 2 #define mmBIF_BX_DEV0_EPF0_VF17_MAILBOX_INT_CNTL 0x013f #define mmBIF_BX_DEV0_EPF0_VF17_MAILBOX_INT_CNTL_BASE_IDX 2 #define mmBIF_BX_DEV0_EPF0_VF17_BIF_VMHV_MAILBOX 0x0140 #define mmBIF_BX_DEV0_EPF0_VF17_BIF_VMHV_MAILBOX_BASE_IDX 2 // addressBlock: nbio_nbif0_rcc_dev0_epf0_vf17_BIFDEC2 // base address: 0x0 #define mmRCC_DEV0_EPF0_VF17_GFXMSIX_VECT0_ADDR_LO 0x0400 #define mmRCC_DEV0_EPF0_VF17_GFXMSIX_VECT0_ADDR_LO_BASE_IDX 3 #define mmRCC_DEV0_EPF0_VF17_GFXMSIX_VECT0_ADDR_HI 0x0401 #define mmRCC_DEV0_EPF0_VF17_GFXMSIX_VECT0_ADDR_HI_BASE_IDX 3 #define mmRCC_DEV0_EPF0_VF17_GFXMSIX_VECT0_MSG_DATA 0x0402 #define mmRCC_DEV0_EPF0_VF17_GFXMSIX_VECT0_MSG_DATA_BASE_IDX 3 #define mmRCC_DEV0_EPF0_VF17_GFXMSIX_VECT0_CONTROL 0x0403 #define mmRCC_DEV0_EPF0_VF17_GFXMSIX_VECT0_CONTROL_BASE_IDX 3 #define mmRCC_DEV0_EPF0_VF17_GFXMSIX_VECT1_ADDR_LO 0x0404 #define mmRCC_DEV0_EPF0_VF17_GFXMSIX_VECT1_ADDR_LO_BASE_IDX 3 #define mmRCC_DEV0_EPF0_VF17_GFXMSIX_VECT1_ADDR_HI 0x0405 #define mmRCC_DEV0_EPF0_VF17_GFXMSIX_VECT1_ADDR_HI_BASE_IDX 3 #define mmRCC_DEV0_EPF0_VF17_GFXMSIX_VECT1_MSG_DATA 0x0406 #define mmRCC_DEV0_EPF0_VF17_GFXMSIX_VECT1_MSG_DATA_BASE_IDX 3 #define mmRCC_DEV0_EPF0_VF17_GFXMSIX_VECT1_CONTROL 0x0407 #define mmRCC_DEV0_EPF0_VF17_GFXMSIX_VECT1_CONTROL_BASE_IDX 3 #define mmRCC_DEV0_EPF0_VF17_GFXMSIX_VECT2_ADDR_LO 0x0408 #define mmRCC_DEV0_EPF0_VF17_GFXMSIX_VECT2_ADDR_LO_BASE_IDX 3 #define mmRCC_DEV0_EPF0_VF17_GFXMSIX_VECT2_ADDR_HI 0x0409 #define mmRCC_DEV0_EPF0_VF17_GFXMSIX_VECT2_ADDR_HI_BASE_IDX 3 #define mmRCC_DEV0_EPF0_VF17_GFXMSIX_VECT2_MSG_DATA 0x040a #define mmRCC_DEV0_EPF0_VF17_GFXMSIX_VECT2_MSG_DATA_BASE_IDX 3 #define mmRCC_DEV0_EPF0_VF17_GFXMSIX_VECT2_CONTROL 0x040b #define mmRCC_DEV0_EPF0_VF17_GFXMSIX_VECT2_CONTROL_BASE_IDX 3 #define mmRCC_DEV0_EPF0_VF17_GFXMSIX_VECT3_ADDR_LO 0x040c #define mmRCC_DEV0_EPF0_VF17_GFXMSIX_VECT3_ADDR_LO_BASE_IDX 3 #define mmRCC_DEV0_EPF0_VF17_GFXMSIX_VECT3_ADDR_HI 0x040d #define mmRCC_DEV0_EPF0_VF17_GFXMSIX_VECT3_ADDR_HI_BASE_IDX 3 #define mmRCC_DEV0_EPF0_VF17_GFXMSIX_VECT3_MSG_DATA 0x040e #define mmRCC_DEV0_EPF0_VF17_GFXMSIX_VECT3_MSG_DATA_BASE_IDX 3 #define mmRCC_DEV0_EPF0_VF17_GFXMSIX_VECT3_CONTROL 0x040f #define mmRCC_DEV0_EPF0_VF17_GFXMSIX_VECT3_CONTROL_BASE_IDX 3 #define mmRCC_DEV0_EPF0_VF17_GFXMSIX_PBA 0x0800 #define mmRCC_DEV0_EPF0_VF17_GFXMSIX_PBA_BASE_IDX 3 // addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf18_SYSPFVFDEC // base address: 0x0 #define mmBIF_BX_DEV0_EPF0_VF18_MM_INDEX 0x0000 #define mmBIF_BX_DEV0_EPF0_VF18_MM_INDEX_BASE_IDX 0 #define mmBIF_BX_DEV0_EPF0_VF18_MM_DATA 0x0001 #define mmBIF_BX_DEV0_EPF0_VF18_MM_DATA_BASE_IDX 0 #define mmBIF_BX_DEV0_EPF0_VF18_MM_INDEX_HI 0x0006 #define mmBIF_BX_DEV0_EPF0_VF18_MM_INDEX_HI_BASE_IDX 0 // addressBlock: nbio_nbif0_rcc_dev0_epf0_vf18_BIFPFVFDEC1 // base address: 0x0 #define mmRCC_DEV0_EPF0_VF18_RCC_ERR_LOG 0x0085 #define mmRCC_DEV0_EPF0_VF18_RCC_ERR_LOG_BASE_IDX 2 #define mmRCC_DEV0_EPF0_VF18_RCC_DOORBELL_APER_EN 0x00c0 #define mmRCC_DEV0_EPF0_VF18_RCC_DOORBELL_APER_EN_BASE_IDX 2 #define mmRCC_DEV0_EPF0_VF18_RCC_CONFIG_MEMSIZE 0x00c3 #define mmRCC_DEV0_EPF0_VF18_RCC_CONFIG_MEMSIZE_BASE_IDX 2 #define mmRCC_DEV0_EPF0_VF18_RCC_CONFIG_RESERVED 0x00c4 #define mmRCC_DEV0_EPF0_VF18_RCC_CONFIG_RESERVED_BASE_IDX 2 #define mmRCC_DEV0_EPF0_VF18_RCC_IOV_FUNC_IDENTIFIER 0x00c5 #define mmRCC_DEV0_EPF0_VF18_RCC_IOV_FUNC_IDENTIFIER_BASE_IDX 2 // addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf18_BIFPFVFDEC1 // base address: 0x0 #define mmBIF_BX_DEV0_EPF0_VF18_BIF_BME_STATUS 0x00eb #define mmBIF_BX_DEV0_EPF0_VF18_BIF_BME_STATUS_BASE_IDX 2 #define mmBIF_BX_DEV0_EPF0_VF18_BIF_ATOMIC_ERR_LOG 0x00ec #define mmBIF_BX_DEV0_EPF0_VF18_BIF_ATOMIC_ERR_LOG_BASE_IDX 2 #define mmBIF_BX_DEV0_EPF0_VF18_DOORBELL_SELFRING_GPA_APER_BASE_HIGH 0x00f3 #define your_sha256_hashE_IDX 2 #define mmBIF_BX_DEV0_EPF0_VF18_DOORBELL_SELFRING_GPA_APER_BASE_LOW 0x00f4 #define your_sha256_hash_IDX 2 #define mmBIF_BX_DEV0_EPF0_VF18_DOORBELL_SELFRING_GPA_APER_CNTL 0x00f5 #define your_sha256_hash 2 #define mmBIF_BX_DEV0_EPF0_VF18_HDP_REG_COHERENCY_FLUSH_CNTL 0x00f6 #define mmBIF_BX_DEV0_EPF0_VF18_HDP_REG_COHERENCY_FLUSH_CNTL_BASE_IDX 2 #define mmBIF_BX_DEV0_EPF0_VF18_HDP_MEM_COHERENCY_FLUSH_CNTL 0x00f7 #define mmBIF_BX_DEV0_EPF0_VF18_HDP_MEM_COHERENCY_FLUSH_CNTL_BASE_IDX 2 #define mmBIF_BX_DEV0_EPF0_VF18_GPU_HDP_FLUSH_REQ 0x0106 #define mmBIF_BX_DEV0_EPF0_VF18_GPU_HDP_FLUSH_REQ_BASE_IDX 2 #define mmBIF_BX_DEV0_EPF0_VF18_GPU_HDP_FLUSH_DONE 0x0107 #define mmBIF_BX_DEV0_EPF0_VF18_GPU_HDP_FLUSH_DONE_BASE_IDX 2 #define mmBIF_BX_DEV0_EPF0_VF18_BIF_TRANS_PENDING 0x0108 #define mmBIF_BX_DEV0_EPF0_VF18_BIF_TRANS_PENDING_BASE_IDX 2 #define mmBIF_BX_DEV0_EPF0_VF18_NBIF_GFX_ADDR_LUT_BYPASS 0x0112 #define mmBIF_BX_DEV0_EPF0_VF18_NBIF_GFX_ADDR_LUT_BYPASS_BASE_IDX 2 #define mmBIF_BX_DEV0_EPF0_VF18_MAILBOX_MSGBUF_TRN_DW0 0x0136 #define mmBIF_BX_DEV0_EPF0_VF18_MAILBOX_MSGBUF_TRN_DW0_BASE_IDX 2 #define mmBIF_BX_DEV0_EPF0_VF18_MAILBOX_MSGBUF_TRN_DW1 0x0137 #define mmBIF_BX_DEV0_EPF0_VF18_MAILBOX_MSGBUF_TRN_DW1_BASE_IDX 2 #define mmBIF_BX_DEV0_EPF0_VF18_MAILBOX_MSGBUF_TRN_DW2 0x0138 #define mmBIF_BX_DEV0_EPF0_VF18_MAILBOX_MSGBUF_TRN_DW2_BASE_IDX 2 #define mmBIF_BX_DEV0_EPF0_VF18_MAILBOX_MSGBUF_TRN_DW3 0x0139 #define mmBIF_BX_DEV0_EPF0_VF18_MAILBOX_MSGBUF_TRN_DW3_BASE_IDX 2 #define mmBIF_BX_DEV0_EPF0_VF18_MAILBOX_MSGBUF_RCV_DW0 0x013a #define mmBIF_BX_DEV0_EPF0_VF18_MAILBOX_MSGBUF_RCV_DW0_BASE_IDX 2 #define mmBIF_BX_DEV0_EPF0_VF18_MAILBOX_MSGBUF_RCV_DW1 0x013b #define mmBIF_BX_DEV0_EPF0_VF18_MAILBOX_MSGBUF_RCV_DW1_BASE_IDX 2 #define mmBIF_BX_DEV0_EPF0_VF18_MAILBOX_MSGBUF_RCV_DW2 0x013c #define mmBIF_BX_DEV0_EPF0_VF18_MAILBOX_MSGBUF_RCV_DW2_BASE_IDX 2 #define mmBIF_BX_DEV0_EPF0_VF18_MAILBOX_MSGBUF_RCV_DW3 0x013d #define mmBIF_BX_DEV0_EPF0_VF18_MAILBOX_MSGBUF_RCV_DW3_BASE_IDX 2 #define mmBIF_BX_DEV0_EPF0_VF18_MAILBOX_CONTROL 0x013e #define mmBIF_BX_DEV0_EPF0_VF18_MAILBOX_CONTROL_BASE_IDX 2 #define mmBIF_BX_DEV0_EPF0_VF18_MAILBOX_INT_CNTL 0x013f #define mmBIF_BX_DEV0_EPF0_VF18_MAILBOX_INT_CNTL_BASE_IDX 2 #define mmBIF_BX_DEV0_EPF0_VF18_BIF_VMHV_MAILBOX 0x0140 #define mmBIF_BX_DEV0_EPF0_VF18_BIF_VMHV_MAILBOX_BASE_IDX 2 // addressBlock: nbio_nbif0_rcc_dev0_epf0_vf18_BIFDEC2 // base address: 0x0 #define mmRCC_DEV0_EPF0_VF18_GFXMSIX_VECT0_ADDR_LO 0x0400 #define mmRCC_DEV0_EPF0_VF18_GFXMSIX_VECT0_ADDR_LO_BASE_IDX 3 #define mmRCC_DEV0_EPF0_VF18_GFXMSIX_VECT0_ADDR_HI 0x0401 #define mmRCC_DEV0_EPF0_VF18_GFXMSIX_VECT0_ADDR_HI_BASE_IDX 3 #define mmRCC_DEV0_EPF0_VF18_GFXMSIX_VECT0_MSG_DATA 0x0402 #define mmRCC_DEV0_EPF0_VF18_GFXMSIX_VECT0_MSG_DATA_BASE_IDX 3 #define mmRCC_DEV0_EPF0_VF18_GFXMSIX_VECT0_CONTROL 0x0403 #define mmRCC_DEV0_EPF0_VF18_GFXMSIX_VECT0_CONTROL_BASE_IDX 3 #define mmRCC_DEV0_EPF0_VF18_GFXMSIX_VECT1_ADDR_LO 0x0404 #define mmRCC_DEV0_EPF0_VF18_GFXMSIX_VECT1_ADDR_LO_BASE_IDX 3 #define mmRCC_DEV0_EPF0_VF18_GFXMSIX_VECT1_ADDR_HI 0x0405 #define mmRCC_DEV0_EPF0_VF18_GFXMSIX_VECT1_ADDR_HI_BASE_IDX 3 #define mmRCC_DEV0_EPF0_VF18_GFXMSIX_VECT1_MSG_DATA 0x0406 #define mmRCC_DEV0_EPF0_VF18_GFXMSIX_VECT1_MSG_DATA_BASE_IDX 3 #define mmRCC_DEV0_EPF0_VF18_GFXMSIX_VECT1_CONTROL 0x0407 #define mmRCC_DEV0_EPF0_VF18_GFXMSIX_VECT1_CONTROL_BASE_IDX 3 #define mmRCC_DEV0_EPF0_VF18_GFXMSIX_VECT2_ADDR_LO 0x0408 #define mmRCC_DEV0_EPF0_VF18_GFXMSIX_VECT2_ADDR_LO_BASE_IDX 3 #define mmRCC_DEV0_EPF0_VF18_GFXMSIX_VECT2_ADDR_HI 0x0409 #define mmRCC_DEV0_EPF0_VF18_GFXMSIX_VECT2_ADDR_HI_BASE_IDX 3 #define mmRCC_DEV0_EPF0_VF18_GFXMSIX_VECT2_MSG_DATA 0x040a #define mmRCC_DEV0_EPF0_VF18_GFXMSIX_VECT2_MSG_DATA_BASE_IDX 3 #define mmRCC_DEV0_EPF0_VF18_GFXMSIX_VECT2_CONTROL 0x040b #define mmRCC_DEV0_EPF0_VF18_GFXMSIX_VECT2_CONTROL_BASE_IDX 3 #define mmRCC_DEV0_EPF0_VF18_GFXMSIX_VECT3_ADDR_LO 0x040c #define mmRCC_DEV0_EPF0_VF18_GFXMSIX_VECT3_ADDR_LO_BASE_IDX 3 #define mmRCC_DEV0_EPF0_VF18_GFXMSIX_VECT3_ADDR_HI 0x040d #define mmRCC_DEV0_EPF0_VF18_GFXMSIX_VECT3_ADDR_HI_BASE_IDX 3 #define mmRCC_DEV0_EPF0_VF18_GFXMSIX_VECT3_MSG_DATA 0x040e #define mmRCC_DEV0_EPF0_VF18_GFXMSIX_VECT3_MSG_DATA_BASE_IDX 3 #define mmRCC_DEV0_EPF0_VF18_GFXMSIX_VECT3_CONTROL 0x040f #define mmRCC_DEV0_EPF0_VF18_GFXMSIX_VECT3_CONTROL_BASE_IDX 3 #define mmRCC_DEV0_EPF0_VF18_GFXMSIX_PBA 0x0800 #define mmRCC_DEV0_EPF0_VF18_GFXMSIX_PBA_BASE_IDX 3 // addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf19_SYSPFVFDEC // base address: 0x0 #define mmBIF_BX_DEV0_EPF0_VF19_MM_INDEX 0x0000 #define mmBIF_BX_DEV0_EPF0_VF19_MM_INDEX_BASE_IDX 0 #define mmBIF_BX_DEV0_EPF0_VF19_MM_DATA 0x0001 #define mmBIF_BX_DEV0_EPF0_VF19_MM_DATA_BASE_IDX 0 #define mmBIF_BX_DEV0_EPF0_VF19_MM_INDEX_HI 0x0006 #define mmBIF_BX_DEV0_EPF0_VF19_MM_INDEX_HI_BASE_IDX 0 // addressBlock: nbio_nbif0_rcc_dev0_epf0_vf19_BIFPFVFDEC1 // base address: 0x0 #define mmRCC_DEV0_EPF0_VF19_RCC_ERR_LOG 0x0085 #define mmRCC_DEV0_EPF0_VF19_RCC_ERR_LOG_BASE_IDX 2 #define mmRCC_DEV0_EPF0_VF19_RCC_DOORBELL_APER_EN 0x00c0 #define mmRCC_DEV0_EPF0_VF19_RCC_DOORBELL_APER_EN_BASE_IDX 2 #define mmRCC_DEV0_EPF0_VF19_RCC_CONFIG_MEMSIZE 0x00c3 #define mmRCC_DEV0_EPF0_VF19_RCC_CONFIG_MEMSIZE_BASE_IDX 2 #define mmRCC_DEV0_EPF0_VF19_RCC_CONFIG_RESERVED 0x00c4 #define mmRCC_DEV0_EPF0_VF19_RCC_CONFIG_RESERVED_BASE_IDX 2 #define mmRCC_DEV0_EPF0_VF19_RCC_IOV_FUNC_IDENTIFIER 0x00c5 #define mmRCC_DEV0_EPF0_VF19_RCC_IOV_FUNC_IDENTIFIER_BASE_IDX 2 // addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf19_BIFPFVFDEC1 // base address: 0x0 #define mmBIF_BX_DEV0_EPF0_VF19_BIF_BME_STATUS 0x00eb #define mmBIF_BX_DEV0_EPF0_VF19_BIF_BME_STATUS_BASE_IDX 2 #define mmBIF_BX_DEV0_EPF0_VF19_BIF_ATOMIC_ERR_LOG 0x00ec #define mmBIF_BX_DEV0_EPF0_VF19_BIF_ATOMIC_ERR_LOG_BASE_IDX 2 #define mmBIF_BX_DEV0_EPF0_VF19_DOORBELL_SELFRING_GPA_APER_BASE_HIGH 0x00f3 #define your_sha256_hashE_IDX 2 #define mmBIF_BX_DEV0_EPF0_VF19_DOORBELL_SELFRING_GPA_APER_BASE_LOW 0x00f4 #define your_sha256_hash_IDX 2 #define mmBIF_BX_DEV0_EPF0_VF19_DOORBELL_SELFRING_GPA_APER_CNTL 0x00f5 #define your_sha256_hash 2 #define mmBIF_BX_DEV0_EPF0_VF19_HDP_REG_COHERENCY_FLUSH_CNTL 0x00f6 #define mmBIF_BX_DEV0_EPF0_VF19_HDP_REG_COHERENCY_FLUSH_CNTL_BASE_IDX 2 #define mmBIF_BX_DEV0_EPF0_VF19_HDP_MEM_COHERENCY_FLUSH_CNTL 0x00f7 #define mmBIF_BX_DEV0_EPF0_VF19_HDP_MEM_COHERENCY_FLUSH_CNTL_BASE_IDX 2 #define mmBIF_BX_DEV0_EPF0_VF19_GPU_HDP_FLUSH_REQ 0x0106 #define mmBIF_BX_DEV0_EPF0_VF19_GPU_HDP_FLUSH_REQ_BASE_IDX 2 #define mmBIF_BX_DEV0_EPF0_VF19_GPU_HDP_FLUSH_DONE 0x0107 #define mmBIF_BX_DEV0_EPF0_VF19_GPU_HDP_FLUSH_DONE_BASE_IDX 2 #define mmBIF_BX_DEV0_EPF0_VF19_BIF_TRANS_PENDING 0x0108 #define mmBIF_BX_DEV0_EPF0_VF19_BIF_TRANS_PENDING_BASE_IDX 2 #define mmBIF_BX_DEV0_EPF0_VF19_NBIF_GFX_ADDR_LUT_BYPASS 0x0112 #define mmBIF_BX_DEV0_EPF0_VF19_NBIF_GFX_ADDR_LUT_BYPASS_BASE_IDX 2 #define mmBIF_BX_DEV0_EPF0_VF19_MAILBOX_MSGBUF_TRN_DW0 0x0136 #define mmBIF_BX_DEV0_EPF0_VF19_MAILBOX_MSGBUF_TRN_DW0_BASE_IDX 2 #define mmBIF_BX_DEV0_EPF0_VF19_MAILBOX_MSGBUF_TRN_DW1 0x0137 #define mmBIF_BX_DEV0_EPF0_VF19_MAILBOX_MSGBUF_TRN_DW1_BASE_IDX 2 #define mmBIF_BX_DEV0_EPF0_VF19_MAILBOX_MSGBUF_TRN_DW2 0x0138 #define mmBIF_BX_DEV0_EPF0_VF19_MAILBOX_MSGBUF_TRN_DW2_BASE_IDX 2 #define mmBIF_BX_DEV0_EPF0_VF19_MAILBOX_MSGBUF_TRN_DW3 0x0139 #define mmBIF_BX_DEV0_EPF0_VF19_MAILBOX_MSGBUF_TRN_DW3_BASE_IDX 2 #define mmBIF_BX_DEV0_EPF0_VF19_MAILBOX_MSGBUF_RCV_DW0 0x013a #define mmBIF_BX_DEV0_EPF0_VF19_MAILBOX_MSGBUF_RCV_DW0_BASE_IDX 2 #define mmBIF_BX_DEV0_EPF0_VF19_MAILBOX_MSGBUF_RCV_DW1 0x013b #define mmBIF_BX_DEV0_EPF0_VF19_MAILBOX_MSGBUF_RCV_DW1_BASE_IDX 2 #define mmBIF_BX_DEV0_EPF0_VF19_MAILBOX_MSGBUF_RCV_DW2 0x013c #define mmBIF_BX_DEV0_EPF0_VF19_MAILBOX_MSGBUF_RCV_DW2_BASE_IDX 2 #define mmBIF_BX_DEV0_EPF0_VF19_MAILBOX_MSGBUF_RCV_DW3 0x013d #define mmBIF_BX_DEV0_EPF0_VF19_MAILBOX_MSGBUF_RCV_DW3_BASE_IDX 2 #define mmBIF_BX_DEV0_EPF0_VF19_MAILBOX_CONTROL 0x013e #define mmBIF_BX_DEV0_EPF0_VF19_MAILBOX_CONTROL_BASE_IDX 2 #define mmBIF_BX_DEV0_EPF0_VF19_MAILBOX_INT_CNTL 0x013f #define mmBIF_BX_DEV0_EPF0_VF19_MAILBOX_INT_CNTL_BASE_IDX 2 #define mmBIF_BX_DEV0_EPF0_VF19_BIF_VMHV_MAILBOX 0x0140 #define mmBIF_BX_DEV0_EPF0_VF19_BIF_VMHV_MAILBOX_BASE_IDX 2 // addressBlock: nbio_nbif0_rcc_dev0_epf0_vf19_BIFDEC2 // base address: 0x0 #define mmRCC_DEV0_EPF0_VF19_GFXMSIX_VECT0_ADDR_LO 0x0400 #define mmRCC_DEV0_EPF0_VF19_GFXMSIX_VECT0_ADDR_LO_BASE_IDX 3 #define mmRCC_DEV0_EPF0_VF19_GFXMSIX_VECT0_ADDR_HI 0x0401 #define mmRCC_DEV0_EPF0_VF19_GFXMSIX_VECT0_ADDR_HI_BASE_IDX 3 #define mmRCC_DEV0_EPF0_VF19_GFXMSIX_VECT0_MSG_DATA 0x0402 #define mmRCC_DEV0_EPF0_VF19_GFXMSIX_VECT0_MSG_DATA_BASE_IDX 3 #define mmRCC_DEV0_EPF0_VF19_GFXMSIX_VECT0_CONTROL 0x0403 #define mmRCC_DEV0_EPF0_VF19_GFXMSIX_VECT0_CONTROL_BASE_IDX 3 #define mmRCC_DEV0_EPF0_VF19_GFXMSIX_VECT1_ADDR_LO 0x0404 #define mmRCC_DEV0_EPF0_VF19_GFXMSIX_VECT1_ADDR_LO_BASE_IDX 3 #define mmRCC_DEV0_EPF0_VF19_GFXMSIX_VECT1_ADDR_HI 0x0405 #define mmRCC_DEV0_EPF0_VF19_GFXMSIX_VECT1_ADDR_HI_BASE_IDX 3 #define mmRCC_DEV0_EPF0_VF19_GFXMSIX_VECT1_MSG_DATA 0x0406 #define mmRCC_DEV0_EPF0_VF19_GFXMSIX_VECT1_MSG_DATA_BASE_IDX 3 #define mmRCC_DEV0_EPF0_VF19_GFXMSIX_VECT1_CONTROL 0x0407 #define mmRCC_DEV0_EPF0_VF19_GFXMSIX_VECT1_CONTROL_BASE_IDX 3 #define mmRCC_DEV0_EPF0_VF19_GFXMSIX_VECT2_ADDR_LO 0x0408 #define mmRCC_DEV0_EPF0_VF19_GFXMSIX_VECT2_ADDR_LO_BASE_IDX 3 #define mmRCC_DEV0_EPF0_VF19_GFXMSIX_VECT2_ADDR_HI 0x0409 #define mmRCC_DEV0_EPF0_VF19_GFXMSIX_VECT2_ADDR_HI_BASE_IDX 3 #define mmRCC_DEV0_EPF0_VF19_GFXMSIX_VECT2_MSG_DATA 0x040a #define mmRCC_DEV0_EPF0_VF19_GFXMSIX_VECT2_MSG_DATA_BASE_IDX 3 #define mmRCC_DEV0_EPF0_VF19_GFXMSIX_VECT2_CONTROL 0x040b #define mmRCC_DEV0_EPF0_VF19_GFXMSIX_VECT2_CONTROL_BASE_IDX 3 #define mmRCC_DEV0_EPF0_VF19_GFXMSIX_VECT3_ADDR_LO 0x040c #define mmRCC_DEV0_EPF0_VF19_GFXMSIX_VECT3_ADDR_LO_BASE_IDX 3 #define mmRCC_DEV0_EPF0_VF19_GFXMSIX_VECT3_ADDR_HI 0x040d #define mmRCC_DEV0_EPF0_VF19_GFXMSIX_VECT3_ADDR_HI_BASE_IDX 3 #define mmRCC_DEV0_EPF0_VF19_GFXMSIX_VECT3_MSG_DATA 0x040e #define mmRCC_DEV0_EPF0_VF19_GFXMSIX_VECT3_MSG_DATA_BASE_IDX 3 #define mmRCC_DEV0_EPF0_VF19_GFXMSIX_VECT3_CONTROL 0x040f #define mmRCC_DEV0_EPF0_VF19_GFXMSIX_VECT3_CONTROL_BASE_IDX 3 #define mmRCC_DEV0_EPF0_VF19_GFXMSIX_PBA 0x0800 #define mmRCC_DEV0_EPF0_VF19_GFXMSIX_PBA_BASE_IDX 3 // addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf20_SYSPFVFDEC // base address: 0x0 #define mmBIF_BX_DEV0_EPF0_VF20_MM_INDEX 0x0000 #define mmBIF_BX_DEV0_EPF0_VF20_MM_INDEX_BASE_IDX 0 #define mmBIF_BX_DEV0_EPF0_VF20_MM_DATA 0x0001 #define mmBIF_BX_DEV0_EPF0_VF20_MM_DATA_BASE_IDX 0 #define mmBIF_BX_DEV0_EPF0_VF20_MM_INDEX_HI 0x0006 #define mmBIF_BX_DEV0_EPF0_VF20_MM_INDEX_HI_BASE_IDX 0 // addressBlock: nbio_nbif0_rcc_dev0_epf0_vf20_BIFPFVFDEC1 // base address: 0x0 #define mmRCC_DEV0_EPF0_VF20_RCC_ERR_LOG 0x0085 #define mmRCC_DEV0_EPF0_VF20_RCC_ERR_LOG_BASE_IDX 2 #define mmRCC_DEV0_EPF0_VF20_RCC_DOORBELL_APER_EN 0x00c0 #define mmRCC_DEV0_EPF0_VF20_RCC_DOORBELL_APER_EN_BASE_IDX 2 #define mmRCC_DEV0_EPF0_VF20_RCC_CONFIG_MEMSIZE 0x00c3 #define mmRCC_DEV0_EPF0_VF20_RCC_CONFIG_MEMSIZE_BASE_IDX 2 #define mmRCC_DEV0_EPF0_VF20_RCC_CONFIG_RESERVED 0x00c4 #define mmRCC_DEV0_EPF0_VF20_RCC_CONFIG_RESERVED_BASE_IDX 2 #define mmRCC_DEV0_EPF0_VF20_RCC_IOV_FUNC_IDENTIFIER 0x00c5 #define mmRCC_DEV0_EPF0_VF20_RCC_IOV_FUNC_IDENTIFIER_BASE_IDX 2 // addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf20_BIFPFVFDEC1 // base address: 0x0 #define mmBIF_BX_DEV0_EPF0_VF20_BIF_BME_STATUS 0x00eb #define mmBIF_BX_DEV0_EPF0_VF20_BIF_BME_STATUS_BASE_IDX 2 #define mmBIF_BX_DEV0_EPF0_VF20_BIF_ATOMIC_ERR_LOG 0x00ec #define mmBIF_BX_DEV0_EPF0_VF20_BIF_ATOMIC_ERR_LOG_BASE_IDX 2 #define mmBIF_BX_DEV0_EPF0_VF20_DOORBELL_SELFRING_GPA_APER_BASE_HIGH 0x00f3 #define your_sha256_hashE_IDX 2 #define mmBIF_BX_DEV0_EPF0_VF20_DOORBELL_SELFRING_GPA_APER_BASE_LOW 0x00f4 #define your_sha256_hash_IDX 2 #define mmBIF_BX_DEV0_EPF0_VF20_DOORBELL_SELFRING_GPA_APER_CNTL 0x00f5 #define your_sha256_hash 2 #define mmBIF_BX_DEV0_EPF0_VF20_HDP_REG_COHERENCY_FLUSH_CNTL 0x00f6 #define mmBIF_BX_DEV0_EPF0_VF20_HDP_REG_COHERENCY_FLUSH_CNTL_BASE_IDX 2 #define mmBIF_BX_DEV0_EPF0_VF20_HDP_MEM_COHERENCY_FLUSH_CNTL 0x00f7 #define mmBIF_BX_DEV0_EPF0_VF20_HDP_MEM_COHERENCY_FLUSH_CNTL_BASE_IDX 2 #define mmBIF_BX_DEV0_EPF0_VF20_GPU_HDP_FLUSH_REQ 0x0106 #define mmBIF_BX_DEV0_EPF0_VF20_GPU_HDP_FLUSH_REQ_BASE_IDX 2 #define mmBIF_BX_DEV0_EPF0_VF20_GPU_HDP_FLUSH_DONE 0x0107 #define mmBIF_BX_DEV0_EPF0_VF20_GPU_HDP_FLUSH_DONE_BASE_IDX 2 #define mmBIF_BX_DEV0_EPF0_VF20_BIF_TRANS_PENDING 0x0108 #define mmBIF_BX_DEV0_EPF0_VF20_BIF_TRANS_PENDING_BASE_IDX 2 #define mmBIF_BX_DEV0_EPF0_VF20_NBIF_GFX_ADDR_LUT_BYPASS 0x0112 #define mmBIF_BX_DEV0_EPF0_VF20_NBIF_GFX_ADDR_LUT_BYPASS_BASE_IDX 2 #define mmBIF_BX_DEV0_EPF0_VF20_MAILBOX_MSGBUF_TRN_DW0 0x0136 #define mmBIF_BX_DEV0_EPF0_VF20_MAILBOX_MSGBUF_TRN_DW0_BASE_IDX 2 #define mmBIF_BX_DEV0_EPF0_VF20_MAILBOX_MSGBUF_TRN_DW1 0x0137 #define mmBIF_BX_DEV0_EPF0_VF20_MAILBOX_MSGBUF_TRN_DW1_BASE_IDX 2 #define mmBIF_BX_DEV0_EPF0_VF20_MAILBOX_MSGBUF_TRN_DW2 0x0138 #define mmBIF_BX_DEV0_EPF0_VF20_MAILBOX_MSGBUF_TRN_DW2_BASE_IDX 2 #define mmBIF_BX_DEV0_EPF0_VF20_MAILBOX_MSGBUF_TRN_DW3 0x0139 #define mmBIF_BX_DEV0_EPF0_VF20_MAILBOX_MSGBUF_TRN_DW3_BASE_IDX 2 #define mmBIF_BX_DEV0_EPF0_VF20_MAILBOX_MSGBUF_RCV_DW0 0x013a #define mmBIF_BX_DEV0_EPF0_VF20_MAILBOX_MSGBUF_RCV_DW0_BASE_IDX 2 #define mmBIF_BX_DEV0_EPF0_VF20_MAILBOX_MSGBUF_RCV_DW1 0x013b #define mmBIF_BX_DEV0_EPF0_VF20_MAILBOX_MSGBUF_RCV_DW1_BASE_IDX 2 #define mmBIF_BX_DEV0_EPF0_VF20_MAILBOX_MSGBUF_RCV_DW2 0x013c #define mmBIF_BX_DEV0_EPF0_VF20_MAILBOX_MSGBUF_RCV_DW2_BASE_IDX 2 #define mmBIF_BX_DEV0_EPF0_VF20_MAILBOX_MSGBUF_RCV_DW3 0x013d #define mmBIF_BX_DEV0_EPF0_VF20_MAILBOX_MSGBUF_RCV_DW3_BASE_IDX 2 #define mmBIF_BX_DEV0_EPF0_VF20_MAILBOX_CONTROL 0x013e #define mmBIF_BX_DEV0_EPF0_VF20_MAILBOX_CONTROL_BASE_IDX 2 #define mmBIF_BX_DEV0_EPF0_VF20_MAILBOX_INT_CNTL 0x013f #define mmBIF_BX_DEV0_EPF0_VF20_MAILBOX_INT_CNTL_BASE_IDX 2 #define mmBIF_BX_DEV0_EPF0_VF20_BIF_VMHV_MAILBOX 0x0140 #define mmBIF_BX_DEV0_EPF0_VF20_BIF_VMHV_MAILBOX_BASE_IDX 2 // addressBlock: nbio_nbif0_rcc_dev0_epf0_vf20_BIFDEC2 // base address: 0x0 #define mmRCC_DEV0_EPF0_VF20_GFXMSIX_VECT0_ADDR_LO 0x0400 #define mmRCC_DEV0_EPF0_VF20_GFXMSIX_VECT0_ADDR_LO_BASE_IDX 3 #define mmRCC_DEV0_EPF0_VF20_GFXMSIX_VECT0_ADDR_HI 0x0401 #define mmRCC_DEV0_EPF0_VF20_GFXMSIX_VECT0_ADDR_HI_BASE_IDX 3 #define mmRCC_DEV0_EPF0_VF20_GFXMSIX_VECT0_MSG_DATA 0x0402 #define mmRCC_DEV0_EPF0_VF20_GFXMSIX_VECT0_MSG_DATA_BASE_IDX 3 #define mmRCC_DEV0_EPF0_VF20_GFXMSIX_VECT0_CONTROL 0x0403 #define mmRCC_DEV0_EPF0_VF20_GFXMSIX_VECT0_CONTROL_BASE_IDX 3 #define mmRCC_DEV0_EPF0_VF20_GFXMSIX_VECT1_ADDR_LO 0x0404 #define mmRCC_DEV0_EPF0_VF20_GFXMSIX_VECT1_ADDR_LO_BASE_IDX 3 #define mmRCC_DEV0_EPF0_VF20_GFXMSIX_VECT1_ADDR_HI 0x0405 #define mmRCC_DEV0_EPF0_VF20_GFXMSIX_VECT1_ADDR_HI_BASE_IDX 3 #define mmRCC_DEV0_EPF0_VF20_GFXMSIX_VECT1_MSG_DATA 0x0406 #define mmRCC_DEV0_EPF0_VF20_GFXMSIX_VECT1_MSG_DATA_BASE_IDX 3 #define mmRCC_DEV0_EPF0_VF20_GFXMSIX_VECT1_CONTROL 0x0407 #define mmRCC_DEV0_EPF0_VF20_GFXMSIX_VECT1_CONTROL_BASE_IDX 3 #define mmRCC_DEV0_EPF0_VF20_GFXMSIX_VECT2_ADDR_LO 0x0408 #define mmRCC_DEV0_EPF0_VF20_GFXMSIX_VECT2_ADDR_LO_BASE_IDX 3 #define mmRCC_DEV0_EPF0_VF20_GFXMSIX_VECT2_ADDR_HI 0x0409 #define mmRCC_DEV0_EPF0_VF20_GFXMSIX_VECT2_ADDR_HI_BASE_IDX 3 #define mmRCC_DEV0_EPF0_VF20_GFXMSIX_VECT2_MSG_DATA 0x040a #define mmRCC_DEV0_EPF0_VF20_GFXMSIX_VECT2_MSG_DATA_BASE_IDX 3 #define mmRCC_DEV0_EPF0_VF20_GFXMSIX_VECT2_CONTROL 0x040b #define mmRCC_DEV0_EPF0_VF20_GFXMSIX_VECT2_CONTROL_BASE_IDX 3 #define mmRCC_DEV0_EPF0_VF20_GFXMSIX_VECT3_ADDR_LO 0x040c #define mmRCC_DEV0_EPF0_VF20_GFXMSIX_VECT3_ADDR_LO_BASE_IDX 3 #define mmRCC_DEV0_EPF0_VF20_GFXMSIX_VECT3_ADDR_HI 0x040d #define mmRCC_DEV0_EPF0_VF20_GFXMSIX_VECT3_ADDR_HI_BASE_IDX 3 #define mmRCC_DEV0_EPF0_VF20_GFXMSIX_VECT3_MSG_DATA 0x040e #define mmRCC_DEV0_EPF0_VF20_GFXMSIX_VECT3_MSG_DATA_BASE_IDX 3 #define mmRCC_DEV0_EPF0_VF20_GFXMSIX_VECT3_CONTROL 0x040f #define mmRCC_DEV0_EPF0_VF20_GFXMSIX_VECT3_CONTROL_BASE_IDX 3 #define mmRCC_DEV0_EPF0_VF20_GFXMSIX_PBA 0x0800 #define mmRCC_DEV0_EPF0_VF20_GFXMSIX_PBA_BASE_IDX 3 // addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf21_SYSPFVFDEC // base address: 0x0 #define mmBIF_BX_DEV0_EPF0_VF21_MM_INDEX 0x0000 #define mmBIF_BX_DEV0_EPF0_VF21_MM_INDEX_BASE_IDX 0 #define mmBIF_BX_DEV0_EPF0_VF21_MM_DATA 0x0001 #define mmBIF_BX_DEV0_EPF0_VF21_MM_DATA_BASE_IDX 0 #define mmBIF_BX_DEV0_EPF0_VF21_MM_INDEX_HI 0x0006 #define mmBIF_BX_DEV0_EPF0_VF21_MM_INDEX_HI_BASE_IDX 0 // addressBlock: nbio_nbif0_rcc_dev0_epf0_vf21_BIFPFVFDEC1 // base address: 0x0 #define mmRCC_DEV0_EPF0_VF21_RCC_ERR_LOG 0x0085 #define mmRCC_DEV0_EPF0_VF21_RCC_ERR_LOG_BASE_IDX 2 #define mmRCC_DEV0_EPF0_VF21_RCC_DOORBELL_APER_EN 0x00c0 #define mmRCC_DEV0_EPF0_VF21_RCC_DOORBELL_APER_EN_BASE_IDX 2 #define mmRCC_DEV0_EPF0_VF21_RCC_CONFIG_MEMSIZE 0x00c3 #define mmRCC_DEV0_EPF0_VF21_RCC_CONFIG_MEMSIZE_BASE_IDX 2 #define mmRCC_DEV0_EPF0_VF21_RCC_CONFIG_RESERVED 0x00c4 #define mmRCC_DEV0_EPF0_VF21_RCC_CONFIG_RESERVED_BASE_IDX 2 #define mmRCC_DEV0_EPF0_VF21_RCC_IOV_FUNC_IDENTIFIER 0x00c5 #define mmRCC_DEV0_EPF0_VF21_RCC_IOV_FUNC_IDENTIFIER_BASE_IDX 2 // addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf21_BIFPFVFDEC1 // base address: 0x0 #define mmBIF_BX_DEV0_EPF0_VF21_BIF_BME_STATUS 0x00eb #define mmBIF_BX_DEV0_EPF0_VF21_BIF_BME_STATUS_BASE_IDX 2 #define mmBIF_BX_DEV0_EPF0_VF21_BIF_ATOMIC_ERR_LOG 0x00ec #define mmBIF_BX_DEV0_EPF0_VF21_BIF_ATOMIC_ERR_LOG_BASE_IDX 2 #define mmBIF_BX_DEV0_EPF0_VF21_DOORBELL_SELFRING_GPA_APER_BASE_HIGH 0x00f3 #define your_sha256_hashE_IDX 2 #define mmBIF_BX_DEV0_EPF0_VF21_DOORBELL_SELFRING_GPA_APER_BASE_LOW 0x00f4 #define your_sha256_hash_IDX 2 #define mmBIF_BX_DEV0_EPF0_VF21_DOORBELL_SELFRING_GPA_APER_CNTL 0x00f5 #define your_sha256_hash 2 #define mmBIF_BX_DEV0_EPF0_VF21_HDP_REG_COHERENCY_FLUSH_CNTL 0x00f6 #define mmBIF_BX_DEV0_EPF0_VF21_HDP_REG_COHERENCY_FLUSH_CNTL_BASE_IDX 2 #define mmBIF_BX_DEV0_EPF0_VF21_HDP_MEM_COHERENCY_FLUSH_CNTL 0x00f7 #define mmBIF_BX_DEV0_EPF0_VF21_HDP_MEM_COHERENCY_FLUSH_CNTL_BASE_IDX 2 #define mmBIF_BX_DEV0_EPF0_VF21_GPU_HDP_FLUSH_REQ 0x0106 #define mmBIF_BX_DEV0_EPF0_VF21_GPU_HDP_FLUSH_REQ_BASE_IDX 2 #define mmBIF_BX_DEV0_EPF0_VF21_GPU_HDP_FLUSH_DONE 0x0107 #define mmBIF_BX_DEV0_EPF0_VF21_GPU_HDP_FLUSH_DONE_BASE_IDX 2 #define mmBIF_BX_DEV0_EPF0_VF21_BIF_TRANS_PENDING 0x0108 #define mmBIF_BX_DEV0_EPF0_VF21_BIF_TRANS_PENDING_BASE_IDX 2 #define mmBIF_BX_DEV0_EPF0_VF21_NBIF_GFX_ADDR_LUT_BYPASS 0x0112 #define mmBIF_BX_DEV0_EPF0_VF21_NBIF_GFX_ADDR_LUT_BYPASS_BASE_IDX 2 #define mmBIF_BX_DEV0_EPF0_VF21_MAILBOX_MSGBUF_TRN_DW0 0x0136 #define mmBIF_BX_DEV0_EPF0_VF21_MAILBOX_MSGBUF_TRN_DW0_BASE_IDX 2 #define mmBIF_BX_DEV0_EPF0_VF21_MAILBOX_MSGBUF_TRN_DW1 0x0137 #define mmBIF_BX_DEV0_EPF0_VF21_MAILBOX_MSGBUF_TRN_DW1_BASE_IDX 2 #define mmBIF_BX_DEV0_EPF0_VF21_MAILBOX_MSGBUF_TRN_DW2 0x0138 #define mmBIF_BX_DEV0_EPF0_VF21_MAILBOX_MSGBUF_TRN_DW2_BASE_IDX 2 #define mmBIF_BX_DEV0_EPF0_VF21_MAILBOX_MSGBUF_TRN_DW3 0x0139 #define mmBIF_BX_DEV0_EPF0_VF21_MAILBOX_MSGBUF_TRN_DW3_BASE_IDX 2 #define mmBIF_BX_DEV0_EPF0_VF21_MAILBOX_MSGBUF_RCV_DW0 0x013a #define mmBIF_BX_DEV0_EPF0_VF21_MAILBOX_MSGBUF_RCV_DW0_BASE_IDX 2 #define mmBIF_BX_DEV0_EPF0_VF21_MAILBOX_MSGBUF_RCV_DW1 0x013b #define mmBIF_BX_DEV0_EPF0_VF21_MAILBOX_MSGBUF_RCV_DW1_BASE_IDX 2 #define mmBIF_BX_DEV0_EPF0_VF21_MAILBOX_MSGBUF_RCV_DW2 0x013c #define mmBIF_BX_DEV0_EPF0_VF21_MAILBOX_MSGBUF_RCV_DW2_BASE_IDX 2 #define mmBIF_BX_DEV0_EPF0_VF21_MAILBOX_MSGBUF_RCV_DW3 0x013d #define mmBIF_BX_DEV0_EPF0_VF21_MAILBOX_MSGBUF_RCV_DW3_BASE_IDX 2 #define mmBIF_BX_DEV0_EPF0_VF21_MAILBOX_CONTROL 0x013e #define mmBIF_BX_DEV0_EPF0_VF21_MAILBOX_CONTROL_BASE_IDX 2 #define mmBIF_BX_DEV0_EPF0_VF21_MAILBOX_INT_CNTL 0x013f #define mmBIF_BX_DEV0_EPF0_VF21_MAILBOX_INT_CNTL_BASE_IDX 2 #define mmBIF_BX_DEV0_EPF0_VF21_BIF_VMHV_MAILBOX 0x0140 #define mmBIF_BX_DEV0_EPF0_VF21_BIF_VMHV_MAILBOX_BASE_IDX 2 // addressBlock: nbio_nbif0_rcc_dev0_epf0_vf21_BIFDEC2 // base address: 0x0 #define mmRCC_DEV0_EPF0_VF21_GFXMSIX_VECT0_ADDR_LO 0x0400 #define mmRCC_DEV0_EPF0_VF21_GFXMSIX_VECT0_ADDR_LO_BASE_IDX 3 #define mmRCC_DEV0_EPF0_VF21_GFXMSIX_VECT0_ADDR_HI 0x0401 #define mmRCC_DEV0_EPF0_VF21_GFXMSIX_VECT0_ADDR_HI_BASE_IDX 3 #define mmRCC_DEV0_EPF0_VF21_GFXMSIX_VECT0_MSG_DATA 0x0402 #define mmRCC_DEV0_EPF0_VF21_GFXMSIX_VECT0_MSG_DATA_BASE_IDX 3 #define mmRCC_DEV0_EPF0_VF21_GFXMSIX_VECT0_CONTROL 0x0403 #define mmRCC_DEV0_EPF0_VF21_GFXMSIX_VECT0_CONTROL_BASE_IDX 3 #define mmRCC_DEV0_EPF0_VF21_GFXMSIX_VECT1_ADDR_LO 0x0404 #define mmRCC_DEV0_EPF0_VF21_GFXMSIX_VECT1_ADDR_LO_BASE_IDX 3 #define mmRCC_DEV0_EPF0_VF21_GFXMSIX_VECT1_ADDR_HI 0x0405 #define mmRCC_DEV0_EPF0_VF21_GFXMSIX_VECT1_ADDR_HI_BASE_IDX 3 #define mmRCC_DEV0_EPF0_VF21_GFXMSIX_VECT1_MSG_DATA 0x0406 #define mmRCC_DEV0_EPF0_VF21_GFXMSIX_VECT1_MSG_DATA_BASE_IDX 3 #define mmRCC_DEV0_EPF0_VF21_GFXMSIX_VECT1_CONTROL 0x0407 #define mmRCC_DEV0_EPF0_VF21_GFXMSIX_VECT1_CONTROL_BASE_IDX 3 #define mmRCC_DEV0_EPF0_VF21_GFXMSIX_VECT2_ADDR_LO 0x0408 #define mmRCC_DEV0_EPF0_VF21_GFXMSIX_VECT2_ADDR_LO_BASE_IDX 3 #define mmRCC_DEV0_EPF0_VF21_GFXMSIX_VECT2_ADDR_HI 0x0409 #define mmRCC_DEV0_EPF0_VF21_GFXMSIX_VECT2_ADDR_HI_BASE_IDX 3 #define mmRCC_DEV0_EPF0_VF21_GFXMSIX_VECT2_MSG_DATA 0x040a #define mmRCC_DEV0_EPF0_VF21_GFXMSIX_VECT2_MSG_DATA_BASE_IDX 3 #define mmRCC_DEV0_EPF0_VF21_GFXMSIX_VECT2_CONTROL 0x040b #define mmRCC_DEV0_EPF0_VF21_GFXMSIX_VECT2_CONTROL_BASE_IDX 3 #define mmRCC_DEV0_EPF0_VF21_GFXMSIX_VECT3_ADDR_LO 0x040c #define mmRCC_DEV0_EPF0_VF21_GFXMSIX_VECT3_ADDR_LO_BASE_IDX 3 #define mmRCC_DEV0_EPF0_VF21_GFXMSIX_VECT3_ADDR_HI 0x040d #define mmRCC_DEV0_EPF0_VF21_GFXMSIX_VECT3_ADDR_HI_BASE_IDX 3 #define mmRCC_DEV0_EPF0_VF21_GFXMSIX_VECT3_MSG_DATA 0x040e #define mmRCC_DEV0_EPF0_VF21_GFXMSIX_VECT3_MSG_DATA_BASE_IDX 3 #define mmRCC_DEV0_EPF0_VF21_GFXMSIX_VECT3_CONTROL 0x040f #define mmRCC_DEV0_EPF0_VF21_GFXMSIX_VECT3_CONTROL_BASE_IDX 3 #define mmRCC_DEV0_EPF0_VF21_GFXMSIX_PBA 0x0800 #define mmRCC_DEV0_EPF0_VF21_GFXMSIX_PBA_BASE_IDX 3 // addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf22_SYSPFVFDEC // base address: 0x0 #define mmBIF_BX_DEV0_EPF0_VF22_MM_INDEX 0x0000 #define mmBIF_BX_DEV0_EPF0_VF22_MM_INDEX_BASE_IDX 0 #define mmBIF_BX_DEV0_EPF0_VF22_MM_DATA 0x0001 #define mmBIF_BX_DEV0_EPF0_VF22_MM_DATA_BASE_IDX 0 #define mmBIF_BX_DEV0_EPF0_VF22_MM_INDEX_HI 0x0006 #define mmBIF_BX_DEV0_EPF0_VF22_MM_INDEX_HI_BASE_IDX 0 // addressBlock: nbio_nbif0_rcc_dev0_epf0_vf22_BIFPFVFDEC1 // base address: 0x0 #define mmRCC_DEV0_EPF0_VF22_RCC_ERR_LOG 0x0085 #define mmRCC_DEV0_EPF0_VF22_RCC_ERR_LOG_BASE_IDX 2 #define mmRCC_DEV0_EPF0_VF22_RCC_DOORBELL_APER_EN 0x00c0 #define mmRCC_DEV0_EPF0_VF22_RCC_DOORBELL_APER_EN_BASE_IDX 2 #define mmRCC_DEV0_EPF0_VF22_RCC_CONFIG_MEMSIZE 0x00c3 #define mmRCC_DEV0_EPF0_VF22_RCC_CONFIG_MEMSIZE_BASE_IDX 2 #define mmRCC_DEV0_EPF0_VF22_RCC_CONFIG_RESERVED 0x00c4 #define mmRCC_DEV0_EPF0_VF22_RCC_CONFIG_RESERVED_BASE_IDX 2 #define mmRCC_DEV0_EPF0_VF22_RCC_IOV_FUNC_IDENTIFIER 0x00c5 #define mmRCC_DEV0_EPF0_VF22_RCC_IOV_FUNC_IDENTIFIER_BASE_IDX 2 // addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf22_BIFPFVFDEC1 // base address: 0x0 #define mmBIF_BX_DEV0_EPF0_VF22_BIF_BME_STATUS 0x00eb #define mmBIF_BX_DEV0_EPF0_VF22_BIF_BME_STATUS_BASE_IDX 2 #define mmBIF_BX_DEV0_EPF0_VF22_BIF_ATOMIC_ERR_LOG 0x00ec #define mmBIF_BX_DEV0_EPF0_VF22_BIF_ATOMIC_ERR_LOG_BASE_IDX 2 #define mmBIF_BX_DEV0_EPF0_VF22_DOORBELL_SELFRING_GPA_APER_BASE_HIGH 0x00f3 #define your_sha256_hashE_IDX 2 #define mmBIF_BX_DEV0_EPF0_VF22_DOORBELL_SELFRING_GPA_APER_BASE_LOW 0x00f4 #define your_sha256_hash_IDX 2 #define mmBIF_BX_DEV0_EPF0_VF22_DOORBELL_SELFRING_GPA_APER_CNTL 0x00f5 #define your_sha256_hash 2 #define mmBIF_BX_DEV0_EPF0_VF22_HDP_REG_COHERENCY_FLUSH_CNTL 0x00f6 #define mmBIF_BX_DEV0_EPF0_VF22_HDP_REG_COHERENCY_FLUSH_CNTL_BASE_IDX 2 #define mmBIF_BX_DEV0_EPF0_VF22_HDP_MEM_COHERENCY_FLUSH_CNTL 0x00f7 #define mmBIF_BX_DEV0_EPF0_VF22_HDP_MEM_COHERENCY_FLUSH_CNTL_BASE_IDX 2 #define mmBIF_BX_DEV0_EPF0_VF22_GPU_HDP_FLUSH_REQ 0x0106 #define mmBIF_BX_DEV0_EPF0_VF22_GPU_HDP_FLUSH_REQ_BASE_IDX 2 #define mmBIF_BX_DEV0_EPF0_VF22_GPU_HDP_FLUSH_DONE 0x0107 #define mmBIF_BX_DEV0_EPF0_VF22_GPU_HDP_FLUSH_DONE_BASE_IDX 2 #define mmBIF_BX_DEV0_EPF0_VF22_BIF_TRANS_PENDING 0x0108 #define mmBIF_BX_DEV0_EPF0_VF22_BIF_TRANS_PENDING_BASE_IDX 2 #define mmBIF_BX_DEV0_EPF0_VF22_NBIF_GFX_ADDR_LUT_BYPASS 0x0112 #define mmBIF_BX_DEV0_EPF0_VF22_NBIF_GFX_ADDR_LUT_BYPASS_BASE_IDX 2 #define mmBIF_BX_DEV0_EPF0_VF22_MAILBOX_MSGBUF_TRN_DW0 0x0136 #define mmBIF_BX_DEV0_EPF0_VF22_MAILBOX_MSGBUF_TRN_DW0_BASE_IDX 2 #define mmBIF_BX_DEV0_EPF0_VF22_MAILBOX_MSGBUF_TRN_DW1 0x0137 #define mmBIF_BX_DEV0_EPF0_VF22_MAILBOX_MSGBUF_TRN_DW1_BASE_IDX 2 #define mmBIF_BX_DEV0_EPF0_VF22_MAILBOX_MSGBUF_TRN_DW2 0x0138 #define mmBIF_BX_DEV0_EPF0_VF22_MAILBOX_MSGBUF_TRN_DW2_BASE_IDX 2 #define mmBIF_BX_DEV0_EPF0_VF22_MAILBOX_MSGBUF_TRN_DW3 0x0139 #define mmBIF_BX_DEV0_EPF0_VF22_MAILBOX_MSGBUF_TRN_DW3_BASE_IDX 2 #define mmBIF_BX_DEV0_EPF0_VF22_MAILBOX_MSGBUF_RCV_DW0 0x013a #define mmBIF_BX_DEV0_EPF0_VF22_MAILBOX_MSGBUF_RCV_DW0_BASE_IDX 2 #define mmBIF_BX_DEV0_EPF0_VF22_MAILBOX_MSGBUF_RCV_DW1 0x013b #define mmBIF_BX_DEV0_EPF0_VF22_MAILBOX_MSGBUF_RCV_DW1_BASE_IDX 2 #define mmBIF_BX_DEV0_EPF0_VF22_MAILBOX_MSGBUF_RCV_DW2 0x013c #define mmBIF_BX_DEV0_EPF0_VF22_MAILBOX_MSGBUF_RCV_DW2_BASE_IDX 2 #define mmBIF_BX_DEV0_EPF0_VF22_MAILBOX_MSGBUF_RCV_DW3 0x013d #define mmBIF_BX_DEV0_EPF0_VF22_MAILBOX_MSGBUF_RCV_DW3_BASE_IDX 2 #define mmBIF_BX_DEV0_EPF0_VF22_MAILBOX_CONTROL 0x013e #define mmBIF_BX_DEV0_EPF0_VF22_MAILBOX_CONTROL_BASE_IDX 2 #define mmBIF_BX_DEV0_EPF0_VF22_MAILBOX_INT_CNTL 0x013f #define mmBIF_BX_DEV0_EPF0_VF22_MAILBOX_INT_CNTL_BASE_IDX 2 #define mmBIF_BX_DEV0_EPF0_VF22_BIF_VMHV_MAILBOX 0x0140 #define mmBIF_BX_DEV0_EPF0_VF22_BIF_VMHV_MAILBOX_BASE_IDX 2 // addressBlock: nbio_nbif0_rcc_dev0_epf0_vf22_BIFDEC2 // base address: 0x0 #define mmRCC_DEV0_EPF0_VF22_GFXMSIX_VECT0_ADDR_LO 0x0400 #define mmRCC_DEV0_EPF0_VF22_GFXMSIX_VECT0_ADDR_LO_BASE_IDX 3 #define mmRCC_DEV0_EPF0_VF22_GFXMSIX_VECT0_ADDR_HI 0x0401 #define mmRCC_DEV0_EPF0_VF22_GFXMSIX_VECT0_ADDR_HI_BASE_IDX 3 #define mmRCC_DEV0_EPF0_VF22_GFXMSIX_VECT0_MSG_DATA 0x0402 #define mmRCC_DEV0_EPF0_VF22_GFXMSIX_VECT0_MSG_DATA_BASE_IDX 3 #define mmRCC_DEV0_EPF0_VF22_GFXMSIX_VECT0_CONTROL 0x0403 #define mmRCC_DEV0_EPF0_VF22_GFXMSIX_VECT0_CONTROL_BASE_IDX 3 #define mmRCC_DEV0_EPF0_VF22_GFXMSIX_VECT1_ADDR_LO 0x0404 #define mmRCC_DEV0_EPF0_VF22_GFXMSIX_VECT1_ADDR_LO_BASE_IDX 3 #define mmRCC_DEV0_EPF0_VF22_GFXMSIX_VECT1_ADDR_HI 0x0405 #define mmRCC_DEV0_EPF0_VF22_GFXMSIX_VECT1_ADDR_HI_BASE_IDX 3 #define mmRCC_DEV0_EPF0_VF22_GFXMSIX_VECT1_MSG_DATA 0x0406 #define mmRCC_DEV0_EPF0_VF22_GFXMSIX_VECT1_MSG_DATA_BASE_IDX 3 #define mmRCC_DEV0_EPF0_VF22_GFXMSIX_VECT1_CONTROL 0x0407 #define mmRCC_DEV0_EPF0_VF22_GFXMSIX_VECT1_CONTROL_BASE_IDX 3 #define mmRCC_DEV0_EPF0_VF22_GFXMSIX_VECT2_ADDR_LO 0x0408 #define mmRCC_DEV0_EPF0_VF22_GFXMSIX_VECT2_ADDR_LO_BASE_IDX 3 #define mmRCC_DEV0_EPF0_VF22_GFXMSIX_VECT2_ADDR_HI 0x0409 #define mmRCC_DEV0_EPF0_VF22_GFXMSIX_VECT2_ADDR_HI_BASE_IDX 3 #define mmRCC_DEV0_EPF0_VF22_GFXMSIX_VECT2_MSG_DATA 0x040a #define mmRCC_DEV0_EPF0_VF22_GFXMSIX_VECT2_MSG_DATA_BASE_IDX 3 #define mmRCC_DEV0_EPF0_VF22_GFXMSIX_VECT2_CONTROL 0x040b #define mmRCC_DEV0_EPF0_VF22_GFXMSIX_VECT2_CONTROL_BASE_IDX 3 #define mmRCC_DEV0_EPF0_VF22_GFXMSIX_VECT3_ADDR_LO 0x040c #define mmRCC_DEV0_EPF0_VF22_GFXMSIX_VECT3_ADDR_LO_BASE_IDX 3 #define mmRCC_DEV0_EPF0_VF22_GFXMSIX_VECT3_ADDR_HI 0x040d #define mmRCC_DEV0_EPF0_VF22_GFXMSIX_VECT3_ADDR_HI_BASE_IDX 3 #define mmRCC_DEV0_EPF0_VF22_GFXMSIX_VECT3_MSG_DATA 0x040e #define mmRCC_DEV0_EPF0_VF22_GFXMSIX_VECT3_MSG_DATA_BASE_IDX 3 #define mmRCC_DEV0_EPF0_VF22_GFXMSIX_VECT3_CONTROL 0x040f #define mmRCC_DEV0_EPF0_VF22_GFXMSIX_VECT3_CONTROL_BASE_IDX 3 #define mmRCC_DEV0_EPF0_VF22_GFXMSIX_PBA 0x0800 #define mmRCC_DEV0_EPF0_VF22_GFXMSIX_PBA_BASE_IDX 3 // addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf23_SYSPFVFDEC // base address: 0x0 #define mmBIF_BX_DEV0_EPF0_VF23_MM_INDEX 0x0000 #define mmBIF_BX_DEV0_EPF0_VF23_MM_INDEX_BASE_IDX 0 #define mmBIF_BX_DEV0_EPF0_VF23_MM_DATA 0x0001 #define mmBIF_BX_DEV0_EPF0_VF23_MM_DATA_BASE_IDX 0 #define mmBIF_BX_DEV0_EPF0_VF23_MM_INDEX_HI 0x0006 #define mmBIF_BX_DEV0_EPF0_VF23_MM_INDEX_HI_BASE_IDX 0 // addressBlock: nbio_nbif0_rcc_dev0_epf0_vf23_BIFPFVFDEC1 // base address: 0x0 #define mmRCC_DEV0_EPF0_VF23_RCC_ERR_LOG 0x0085 #define mmRCC_DEV0_EPF0_VF23_RCC_ERR_LOG_BASE_IDX 2 #define mmRCC_DEV0_EPF0_VF23_RCC_DOORBELL_APER_EN 0x00c0 #define mmRCC_DEV0_EPF0_VF23_RCC_DOORBELL_APER_EN_BASE_IDX 2 #define mmRCC_DEV0_EPF0_VF23_RCC_CONFIG_MEMSIZE 0x00c3 #define mmRCC_DEV0_EPF0_VF23_RCC_CONFIG_MEMSIZE_BASE_IDX 2 #define mmRCC_DEV0_EPF0_VF23_RCC_CONFIG_RESERVED 0x00c4 #define mmRCC_DEV0_EPF0_VF23_RCC_CONFIG_RESERVED_BASE_IDX 2 #define mmRCC_DEV0_EPF0_VF23_RCC_IOV_FUNC_IDENTIFIER 0x00c5 #define mmRCC_DEV0_EPF0_VF23_RCC_IOV_FUNC_IDENTIFIER_BASE_IDX 2 // addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf23_BIFPFVFDEC1 // base address: 0x0 #define mmBIF_BX_DEV0_EPF0_VF23_BIF_BME_STATUS 0x00eb #define mmBIF_BX_DEV0_EPF0_VF23_BIF_BME_STATUS_BASE_IDX 2 #define mmBIF_BX_DEV0_EPF0_VF23_BIF_ATOMIC_ERR_LOG 0x00ec #define mmBIF_BX_DEV0_EPF0_VF23_BIF_ATOMIC_ERR_LOG_BASE_IDX 2 #define mmBIF_BX_DEV0_EPF0_VF23_DOORBELL_SELFRING_GPA_APER_BASE_HIGH 0x00f3 #define your_sha256_hashE_IDX 2 #define mmBIF_BX_DEV0_EPF0_VF23_DOORBELL_SELFRING_GPA_APER_BASE_LOW 0x00f4 #define your_sha256_hash_IDX 2 #define mmBIF_BX_DEV0_EPF0_VF23_DOORBELL_SELFRING_GPA_APER_CNTL 0x00f5 #define your_sha256_hash 2 #define mmBIF_BX_DEV0_EPF0_VF23_HDP_REG_COHERENCY_FLUSH_CNTL 0x00f6 #define mmBIF_BX_DEV0_EPF0_VF23_HDP_REG_COHERENCY_FLUSH_CNTL_BASE_IDX 2 #define mmBIF_BX_DEV0_EPF0_VF23_HDP_MEM_COHERENCY_FLUSH_CNTL 0x00f7 #define mmBIF_BX_DEV0_EPF0_VF23_HDP_MEM_COHERENCY_FLUSH_CNTL_BASE_IDX 2 #define mmBIF_BX_DEV0_EPF0_VF23_GPU_HDP_FLUSH_REQ 0x0106 #define mmBIF_BX_DEV0_EPF0_VF23_GPU_HDP_FLUSH_REQ_BASE_IDX 2 #define mmBIF_BX_DEV0_EPF0_VF23_GPU_HDP_FLUSH_DONE 0x0107 #define mmBIF_BX_DEV0_EPF0_VF23_GPU_HDP_FLUSH_DONE_BASE_IDX 2 #define mmBIF_BX_DEV0_EPF0_VF23_BIF_TRANS_PENDING 0x0108 #define mmBIF_BX_DEV0_EPF0_VF23_BIF_TRANS_PENDING_BASE_IDX 2 #define mmBIF_BX_DEV0_EPF0_VF23_NBIF_GFX_ADDR_LUT_BYPASS 0x0112 #define mmBIF_BX_DEV0_EPF0_VF23_NBIF_GFX_ADDR_LUT_BYPASS_BASE_IDX 2 #define mmBIF_BX_DEV0_EPF0_VF23_MAILBOX_MSGBUF_TRN_DW0 0x0136 #define mmBIF_BX_DEV0_EPF0_VF23_MAILBOX_MSGBUF_TRN_DW0_BASE_IDX 2 #define mmBIF_BX_DEV0_EPF0_VF23_MAILBOX_MSGBUF_TRN_DW1 0x0137 #define mmBIF_BX_DEV0_EPF0_VF23_MAILBOX_MSGBUF_TRN_DW1_BASE_IDX 2 #define mmBIF_BX_DEV0_EPF0_VF23_MAILBOX_MSGBUF_TRN_DW2 0x0138 #define mmBIF_BX_DEV0_EPF0_VF23_MAILBOX_MSGBUF_TRN_DW2_BASE_IDX 2 #define mmBIF_BX_DEV0_EPF0_VF23_MAILBOX_MSGBUF_TRN_DW3 0x0139 #define mmBIF_BX_DEV0_EPF0_VF23_MAILBOX_MSGBUF_TRN_DW3_BASE_IDX 2 #define mmBIF_BX_DEV0_EPF0_VF23_MAILBOX_MSGBUF_RCV_DW0 0x013a #define mmBIF_BX_DEV0_EPF0_VF23_MAILBOX_MSGBUF_RCV_DW0_BASE_IDX 2 #define mmBIF_BX_DEV0_EPF0_VF23_MAILBOX_MSGBUF_RCV_DW1 0x013b #define mmBIF_BX_DEV0_EPF0_VF23_MAILBOX_MSGBUF_RCV_DW1_BASE_IDX 2 #define mmBIF_BX_DEV0_EPF0_VF23_MAILBOX_MSGBUF_RCV_DW2 0x013c #define mmBIF_BX_DEV0_EPF0_VF23_MAILBOX_MSGBUF_RCV_DW2_BASE_IDX 2 #define mmBIF_BX_DEV0_EPF0_VF23_MAILBOX_MSGBUF_RCV_DW3 0x013d #define mmBIF_BX_DEV0_EPF0_VF23_MAILBOX_MSGBUF_RCV_DW3_BASE_IDX 2 #define mmBIF_BX_DEV0_EPF0_VF23_MAILBOX_CONTROL 0x013e #define mmBIF_BX_DEV0_EPF0_VF23_MAILBOX_CONTROL_BASE_IDX 2 #define mmBIF_BX_DEV0_EPF0_VF23_MAILBOX_INT_CNTL 0x013f #define mmBIF_BX_DEV0_EPF0_VF23_MAILBOX_INT_CNTL_BASE_IDX 2 #define mmBIF_BX_DEV0_EPF0_VF23_BIF_VMHV_MAILBOX 0x0140 #define mmBIF_BX_DEV0_EPF0_VF23_BIF_VMHV_MAILBOX_BASE_IDX 2 // addressBlock: nbio_nbif0_rcc_dev0_epf0_vf23_BIFDEC2 // base address: 0x0 #define mmRCC_DEV0_EPF0_VF23_GFXMSIX_VECT0_ADDR_LO 0x0400 #define mmRCC_DEV0_EPF0_VF23_GFXMSIX_VECT0_ADDR_LO_BASE_IDX 3 #define mmRCC_DEV0_EPF0_VF23_GFXMSIX_VECT0_ADDR_HI 0x0401 #define mmRCC_DEV0_EPF0_VF23_GFXMSIX_VECT0_ADDR_HI_BASE_IDX 3 #define mmRCC_DEV0_EPF0_VF23_GFXMSIX_VECT0_MSG_DATA 0x0402 #define mmRCC_DEV0_EPF0_VF23_GFXMSIX_VECT0_MSG_DATA_BASE_IDX 3 #define mmRCC_DEV0_EPF0_VF23_GFXMSIX_VECT0_CONTROL 0x0403 #define mmRCC_DEV0_EPF0_VF23_GFXMSIX_VECT0_CONTROL_BASE_IDX 3 #define mmRCC_DEV0_EPF0_VF23_GFXMSIX_VECT1_ADDR_LO 0x0404 #define mmRCC_DEV0_EPF0_VF23_GFXMSIX_VECT1_ADDR_LO_BASE_IDX 3 #define mmRCC_DEV0_EPF0_VF23_GFXMSIX_VECT1_ADDR_HI 0x0405 #define mmRCC_DEV0_EPF0_VF23_GFXMSIX_VECT1_ADDR_HI_BASE_IDX 3 #define mmRCC_DEV0_EPF0_VF23_GFXMSIX_VECT1_MSG_DATA 0x0406 #define mmRCC_DEV0_EPF0_VF23_GFXMSIX_VECT1_MSG_DATA_BASE_IDX 3 #define mmRCC_DEV0_EPF0_VF23_GFXMSIX_VECT1_CONTROL 0x0407 #define mmRCC_DEV0_EPF0_VF23_GFXMSIX_VECT1_CONTROL_BASE_IDX 3 #define mmRCC_DEV0_EPF0_VF23_GFXMSIX_VECT2_ADDR_LO 0x0408 #define mmRCC_DEV0_EPF0_VF23_GFXMSIX_VECT2_ADDR_LO_BASE_IDX 3 #define mmRCC_DEV0_EPF0_VF23_GFXMSIX_VECT2_ADDR_HI 0x0409 #define mmRCC_DEV0_EPF0_VF23_GFXMSIX_VECT2_ADDR_HI_BASE_IDX 3 #define mmRCC_DEV0_EPF0_VF23_GFXMSIX_VECT2_MSG_DATA 0x040a #define mmRCC_DEV0_EPF0_VF23_GFXMSIX_VECT2_MSG_DATA_BASE_IDX 3 #define mmRCC_DEV0_EPF0_VF23_GFXMSIX_VECT2_CONTROL 0x040b #define mmRCC_DEV0_EPF0_VF23_GFXMSIX_VECT2_CONTROL_BASE_IDX 3 #define mmRCC_DEV0_EPF0_VF23_GFXMSIX_VECT3_ADDR_LO 0x040c #define mmRCC_DEV0_EPF0_VF23_GFXMSIX_VECT3_ADDR_LO_BASE_IDX 3 #define mmRCC_DEV0_EPF0_VF23_GFXMSIX_VECT3_ADDR_HI 0x040d #define mmRCC_DEV0_EPF0_VF23_GFXMSIX_VECT3_ADDR_HI_BASE_IDX 3 #define mmRCC_DEV0_EPF0_VF23_GFXMSIX_VECT3_MSG_DATA 0x040e #define mmRCC_DEV0_EPF0_VF23_GFXMSIX_VECT3_MSG_DATA_BASE_IDX 3 #define mmRCC_DEV0_EPF0_VF23_GFXMSIX_VECT3_CONTROL 0x040f #define mmRCC_DEV0_EPF0_VF23_GFXMSIX_VECT3_CONTROL_BASE_IDX 3 #define mmRCC_DEV0_EPF0_VF23_GFXMSIX_PBA 0x0800 #define mmRCC_DEV0_EPF0_VF23_GFXMSIX_PBA_BASE_IDX 3 // addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf24_SYSPFVFDEC // base address: 0x0 #define mmBIF_BX_DEV0_EPF0_VF24_MM_INDEX 0x0000 #define mmBIF_BX_DEV0_EPF0_VF24_MM_INDEX_BASE_IDX 0 #define mmBIF_BX_DEV0_EPF0_VF24_MM_DATA 0x0001 #define mmBIF_BX_DEV0_EPF0_VF24_MM_DATA_BASE_IDX 0 #define mmBIF_BX_DEV0_EPF0_VF24_MM_INDEX_HI 0x0006 #define mmBIF_BX_DEV0_EPF0_VF24_MM_INDEX_HI_BASE_IDX 0 // addressBlock: nbio_nbif0_rcc_dev0_epf0_vf24_BIFPFVFDEC1 // base address: 0x0 #define mmRCC_DEV0_EPF0_VF24_RCC_ERR_LOG 0x0085 #define mmRCC_DEV0_EPF0_VF24_RCC_ERR_LOG_BASE_IDX 2 #define mmRCC_DEV0_EPF0_VF24_RCC_DOORBELL_APER_EN 0x00c0 #define mmRCC_DEV0_EPF0_VF24_RCC_DOORBELL_APER_EN_BASE_IDX 2 #define mmRCC_DEV0_EPF0_VF24_RCC_CONFIG_MEMSIZE 0x00c3 #define mmRCC_DEV0_EPF0_VF24_RCC_CONFIG_MEMSIZE_BASE_IDX 2 #define mmRCC_DEV0_EPF0_VF24_RCC_CONFIG_RESERVED 0x00c4 #define mmRCC_DEV0_EPF0_VF24_RCC_CONFIG_RESERVED_BASE_IDX 2 #define mmRCC_DEV0_EPF0_VF24_RCC_IOV_FUNC_IDENTIFIER 0x00c5 #define mmRCC_DEV0_EPF0_VF24_RCC_IOV_FUNC_IDENTIFIER_BASE_IDX 2 // addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf24_BIFPFVFDEC1 // base address: 0x0 #define mmBIF_BX_DEV0_EPF0_VF24_BIF_BME_STATUS 0x00eb #define mmBIF_BX_DEV0_EPF0_VF24_BIF_BME_STATUS_BASE_IDX 2 #define mmBIF_BX_DEV0_EPF0_VF24_BIF_ATOMIC_ERR_LOG 0x00ec #define mmBIF_BX_DEV0_EPF0_VF24_BIF_ATOMIC_ERR_LOG_BASE_IDX 2 #define mmBIF_BX_DEV0_EPF0_VF24_DOORBELL_SELFRING_GPA_APER_BASE_HIGH 0x00f3 #define your_sha256_hashE_IDX 2 #define mmBIF_BX_DEV0_EPF0_VF24_DOORBELL_SELFRING_GPA_APER_BASE_LOW 0x00f4 #define your_sha256_hash_IDX 2 #define mmBIF_BX_DEV0_EPF0_VF24_DOORBELL_SELFRING_GPA_APER_CNTL 0x00f5 #define your_sha256_hash 2 #define mmBIF_BX_DEV0_EPF0_VF24_HDP_REG_COHERENCY_FLUSH_CNTL 0x00f6 #define mmBIF_BX_DEV0_EPF0_VF24_HDP_REG_COHERENCY_FLUSH_CNTL_BASE_IDX 2 #define mmBIF_BX_DEV0_EPF0_VF24_HDP_MEM_COHERENCY_FLUSH_CNTL 0x00f7 #define mmBIF_BX_DEV0_EPF0_VF24_HDP_MEM_COHERENCY_FLUSH_CNTL_BASE_IDX 2 #define mmBIF_BX_DEV0_EPF0_VF24_GPU_HDP_FLUSH_REQ 0x0106 #define mmBIF_BX_DEV0_EPF0_VF24_GPU_HDP_FLUSH_REQ_BASE_IDX 2 #define mmBIF_BX_DEV0_EPF0_VF24_GPU_HDP_FLUSH_DONE 0x0107 #define mmBIF_BX_DEV0_EPF0_VF24_GPU_HDP_FLUSH_DONE_BASE_IDX 2 #define mmBIF_BX_DEV0_EPF0_VF24_BIF_TRANS_PENDING 0x0108 #define mmBIF_BX_DEV0_EPF0_VF24_BIF_TRANS_PENDING_BASE_IDX 2 #define mmBIF_BX_DEV0_EPF0_VF24_NBIF_GFX_ADDR_LUT_BYPASS 0x0112 #define mmBIF_BX_DEV0_EPF0_VF24_NBIF_GFX_ADDR_LUT_BYPASS_BASE_IDX 2 #define mmBIF_BX_DEV0_EPF0_VF24_MAILBOX_MSGBUF_TRN_DW0 0x0136 #define mmBIF_BX_DEV0_EPF0_VF24_MAILBOX_MSGBUF_TRN_DW0_BASE_IDX 2 #define mmBIF_BX_DEV0_EPF0_VF24_MAILBOX_MSGBUF_TRN_DW1 0x0137 #define mmBIF_BX_DEV0_EPF0_VF24_MAILBOX_MSGBUF_TRN_DW1_BASE_IDX 2 #define mmBIF_BX_DEV0_EPF0_VF24_MAILBOX_MSGBUF_TRN_DW2 0x0138 #define mmBIF_BX_DEV0_EPF0_VF24_MAILBOX_MSGBUF_TRN_DW2_BASE_IDX 2 #define mmBIF_BX_DEV0_EPF0_VF24_MAILBOX_MSGBUF_TRN_DW3 0x0139 #define mmBIF_BX_DEV0_EPF0_VF24_MAILBOX_MSGBUF_TRN_DW3_BASE_IDX 2 #define mmBIF_BX_DEV0_EPF0_VF24_MAILBOX_MSGBUF_RCV_DW0 0x013a #define mmBIF_BX_DEV0_EPF0_VF24_MAILBOX_MSGBUF_RCV_DW0_BASE_IDX 2 #define mmBIF_BX_DEV0_EPF0_VF24_MAILBOX_MSGBUF_RCV_DW1 0x013b #define mmBIF_BX_DEV0_EPF0_VF24_MAILBOX_MSGBUF_RCV_DW1_BASE_IDX 2 #define mmBIF_BX_DEV0_EPF0_VF24_MAILBOX_MSGBUF_RCV_DW2 0x013c #define mmBIF_BX_DEV0_EPF0_VF24_MAILBOX_MSGBUF_RCV_DW2_BASE_IDX 2 #define mmBIF_BX_DEV0_EPF0_VF24_MAILBOX_MSGBUF_RCV_DW3 0x013d #define mmBIF_BX_DEV0_EPF0_VF24_MAILBOX_MSGBUF_RCV_DW3_BASE_IDX 2 #define mmBIF_BX_DEV0_EPF0_VF24_MAILBOX_CONTROL 0x013e #define mmBIF_BX_DEV0_EPF0_VF24_MAILBOX_CONTROL_BASE_IDX 2 #define mmBIF_BX_DEV0_EPF0_VF24_MAILBOX_INT_CNTL 0x013f #define mmBIF_BX_DEV0_EPF0_VF24_MAILBOX_INT_CNTL_BASE_IDX 2 #define mmBIF_BX_DEV0_EPF0_VF24_BIF_VMHV_MAILBOX 0x0140 #define mmBIF_BX_DEV0_EPF0_VF24_BIF_VMHV_MAILBOX_BASE_IDX 2 // addressBlock: nbio_nbif0_rcc_dev0_epf0_vf24_BIFDEC2 // base address: 0x0 #define mmRCC_DEV0_EPF0_VF24_GFXMSIX_VECT0_ADDR_LO 0x0400 #define mmRCC_DEV0_EPF0_VF24_GFXMSIX_VECT0_ADDR_LO_BASE_IDX 3 #define mmRCC_DEV0_EPF0_VF24_GFXMSIX_VECT0_ADDR_HI 0x0401 #define mmRCC_DEV0_EPF0_VF24_GFXMSIX_VECT0_ADDR_HI_BASE_IDX 3 #define mmRCC_DEV0_EPF0_VF24_GFXMSIX_VECT0_MSG_DATA 0x0402 #define mmRCC_DEV0_EPF0_VF24_GFXMSIX_VECT0_MSG_DATA_BASE_IDX 3 #define mmRCC_DEV0_EPF0_VF24_GFXMSIX_VECT0_CONTROL 0x0403 #define mmRCC_DEV0_EPF0_VF24_GFXMSIX_VECT0_CONTROL_BASE_IDX 3 #define mmRCC_DEV0_EPF0_VF24_GFXMSIX_VECT1_ADDR_LO 0x0404 #define mmRCC_DEV0_EPF0_VF24_GFXMSIX_VECT1_ADDR_LO_BASE_IDX 3 #define mmRCC_DEV0_EPF0_VF24_GFXMSIX_VECT1_ADDR_HI 0x0405 #define mmRCC_DEV0_EPF0_VF24_GFXMSIX_VECT1_ADDR_HI_BASE_IDX 3 #define mmRCC_DEV0_EPF0_VF24_GFXMSIX_VECT1_MSG_DATA 0x0406 #define mmRCC_DEV0_EPF0_VF24_GFXMSIX_VECT1_MSG_DATA_BASE_IDX 3 #define mmRCC_DEV0_EPF0_VF24_GFXMSIX_VECT1_CONTROL 0x0407 #define mmRCC_DEV0_EPF0_VF24_GFXMSIX_VECT1_CONTROL_BASE_IDX 3 #define mmRCC_DEV0_EPF0_VF24_GFXMSIX_VECT2_ADDR_LO 0x0408 #define mmRCC_DEV0_EPF0_VF24_GFXMSIX_VECT2_ADDR_LO_BASE_IDX 3 #define mmRCC_DEV0_EPF0_VF24_GFXMSIX_VECT2_ADDR_HI 0x0409 #define mmRCC_DEV0_EPF0_VF24_GFXMSIX_VECT2_ADDR_HI_BASE_IDX 3 #define mmRCC_DEV0_EPF0_VF24_GFXMSIX_VECT2_MSG_DATA 0x040a #define mmRCC_DEV0_EPF0_VF24_GFXMSIX_VECT2_MSG_DATA_BASE_IDX 3 #define mmRCC_DEV0_EPF0_VF24_GFXMSIX_VECT2_CONTROL 0x040b #define mmRCC_DEV0_EPF0_VF24_GFXMSIX_VECT2_CONTROL_BASE_IDX 3 #define mmRCC_DEV0_EPF0_VF24_GFXMSIX_VECT3_ADDR_LO 0x040c #define mmRCC_DEV0_EPF0_VF24_GFXMSIX_VECT3_ADDR_LO_BASE_IDX 3 #define mmRCC_DEV0_EPF0_VF24_GFXMSIX_VECT3_ADDR_HI 0x040d #define mmRCC_DEV0_EPF0_VF24_GFXMSIX_VECT3_ADDR_HI_BASE_IDX 3 #define mmRCC_DEV0_EPF0_VF24_GFXMSIX_VECT3_MSG_DATA 0x040e #define mmRCC_DEV0_EPF0_VF24_GFXMSIX_VECT3_MSG_DATA_BASE_IDX 3 #define mmRCC_DEV0_EPF0_VF24_GFXMSIX_VECT3_CONTROL 0x040f #define mmRCC_DEV0_EPF0_VF24_GFXMSIX_VECT3_CONTROL_BASE_IDX 3 #define mmRCC_DEV0_EPF0_VF24_GFXMSIX_PBA 0x0800 #define mmRCC_DEV0_EPF0_VF24_GFXMSIX_PBA_BASE_IDX 3 // addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf25_SYSPFVFDEC // base address: 0x0 #define mmBIF_BX_DEV0_EPF0_VF25_MM_INDEX 0x0000 #define mmBIF_BX_DEV0_EPF0_VF25_MM_INDEX_BASE_IDX 0 #define mmBIF_BX_DEV0_EPF0_VF25_MM_DATA 0x0001 #define mmBIF_BX_DEV0_EPF0_VF25_MM_DATA_BASE_IDX 0 #define mmBIF_BX_DEV0_EPF0_VF25_MM_INDEX_HI 0x0006 #define mmBIF_BX_DEV0_EPF0_VF25_MM_INDEX_HI_BASE_IDX 0 // addressBlock: nbio_nbif0_rcc_dev0_epf0_vf25_BIFPFVFDEC1 // base address: 0x0 #define mmRCC_DEV0_EPF0_VF25_RCC_ERR_LOG 0x0085 #define mmRCC_DEV0_EPF0_VF25_RCC_ERR_LOG_BASE_IDX 2 #define mmRCC_DEV0_EPF0_VF25_RCC_DOORBELL_APER_EN 0x00c0 #define mmRCC_DEV0_EPF0_VF25_RCC_DOORBELL_APER_EN_BASE_IDX 2 #define mmRCC_DEV0_EPF0_VF25_RCC_CONFIG_MEMSIZE 0x00c3 #define mmRCC_DEV0_EPF0_VF25_RCC_CONFIG_MEMSIZE_BASE_IDX 2 #define mmRCC_DEV0_EPF0_VF25_RCC_CONFIG_RESERVED 0x00c4 #define mmRCC_DEV0_EPF0_VF25_RCC_CONFIG_RESERVED_BASE_IDX 2 #define mmRCC_DEV0_EPF0_VF25_RCC_IOV_FUNC_IDENTIFIER 0x00c5 #define mmRCC_DEV0_EPF0_VF25_RCC_IOV_FUNC_IDENTIFIER_BASE_IDX 2 // addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf25_BIFPFVFDEC1 // base address: 0x0 #define mmBIF_BX_DEV0_EPF0_VF25_BIF_BME_STATUS 0x00eb #define mmBIF_BX_DEV0_EPF0_VF25_BIF_BME_STATUS_BASE_IDX 2 #define mmBIF_BX_DEV0_EPF0_VF25_BIF_ATOMIC_ERR_LOG 0x00ec #define mmBIF_BX_DEV0_EPF0_VF25_BIF_ATOMIC_ERR_LOG_BASE_IDX 2 #define mmBIF_BX_DEV0_EPF0_VF25_DOORBELL_SELFRING_GPA_APER_BASE_HIGH 0x00f3 #define your_sha256_hashE_IDX 2 #define mmBIF_BX_DEV0_EPF0_VF25_DOORBELL_SELFRING_GPA_APER_BASE_LOW 0x00f4 #define your_sha256_hash_IDX 2 #define mmBIF_BX_DEV0_EPF0_VF25_DOORBELL_SELFRING_GPA_APER_CNTL 0x00f5 #define your_sha256_hash 2 #define mmBIF_BX_DEV0_EPF0_VF25_HDP_REG_COHERENCY_FLUSH_CNTL 0x00f6 #define mmBIF_BX_DEV0_EPF0_VF25_HDP_REG_COHERENCY_FLUSH_CNTL_BASE_IDX 2 #define mmBIF_BX_DEV0_EPF0_VF25_HDP_MEM_COHERENCY_FLUSH_CNTL 0x00f7 #define mmBIF_BX_DEV0_EPF0_VF25_HDP_MEM_COHERENCY_FLUSH_CNTL_BASE_IDX 2 #define mmBIF_BX_DEV0_EPF0_VF25_GPU_HDP_FLUSH_REQ 0x0106 #define mmBIF_BX_DEV0_EPF0_VF25_GPU_HDP_FLUSH_REQ_BASE_IDX 2 #define mmBIF_BX_DEV0_EPF0_VF25_GPU_HDP_FLUSH_DONE 0x0107 #define mmBIF_BX_DEV0_EPF0_VF25_GPU_HDP_FLUSH_DONE_BASE_IDX 2 #define mmBIF_BX_DEV0_EPF0_VF25_BIF_TRANS_PENDING 0x0108 #define mmBIF_BX_DEV0_EPF0_VF25_BIF_TRANS_PENDING_BASE_IDX 2 #define mmBIF_BX_DEV0_EPF0_VF25_NBIF_GFX_ADDR_LUT_BYPASS 0x0112 #define mmBIF_BX_DEV0_EPF0_VF25_NBIF_GFX_ADDR_LUT_BYPASS_BASE_IDX 2 #define mmBIF_BX_DEV0_EPF0_VF25_MAILBOX_MSGBUF_TRN_DW0 0x0136 #define mmBIF_BX_DEV0_EPF0_VF25_MAILBOX_MSGBUF_TRN_DW0_BASE_IDX 2 #define mmBIF_BX_DEV0_EPF0_VF25_MAILBOX_MSGBUF_TRN_DW1 0x0137 #define mmBIF_BX_DEV0_EPF0_VF25_MAILBOX_MSGBUF_TRN_DW1_BASE_IDX 2 #define mmBIF_BX_DEV0_EPF0_VF25_MAILBOX_MSGBUF_TRN_DW2 0x0138 #define mmBIF_BX_DEV0_EPF0_VF25_MAILBOX_MSGBUF_TRN_DW2_BASE_IDX 2 #define mmBIF_BX_DEV0_EPF0_VF25_MAILBOX_MSGBUF_TRN_DW3 0x0139 #define mmBIF_BX_DEV0_EPF0_VF25_MAILBOX_MSGBUF_TRN_DW3_BASE_IDX 2 #define mmBIF_BX_DEV0_EPF0_VF25_MAILBOX_MSGBUF_RCV_DW0 0x013a #define mmBIF_BX_DEV0_EPF0_VF25_MAILBOX_MSGBUF_RCV_DW0_BASE_IDX 2 #define mmBIF_BX_DEV0_EPF0_VF25_MAILBOX_MSGBUF_RCV_DW1 0x013b #define mmBIF_BX_DEV0_EPF0_VF25_MAILBOX_MSGBUF_RCV_DW1_BASE_IDX 2 #define mmBIF_BX_DEV0_EPF0_VF25_MAILBOX_MSGBUF_RCV_DW2 0x013c #define mmBIF_BX_DEV0_EPF0_VF25_MAILBOX_MSGBUF_RCV_DW2_BASE_IDX 2 #define mmBIF_BX_DEV0_EPF0_VF25_MAILBOX_MSGBUF_RCV_DW3 0x013d #define mmBIF_BX_DEV0_EPF0_VF25_MAILBOX_MSGBUF_RCV_DW3_BASE_IDX 2 #define mmBIF_BX_DEV0_EPF0_VF25_MAILBOX_CONTROL 0x013e #define mmBIF_BX_DEV0_EPF0_VF25_MAILBOX_CONTROL_BASE_IDX 2 #define mmBIF_BX_DEV0_EPF0_VF25_MAILBOX_INT_CNTL 0x013f #define mmBIF_BX_DEV0_EPF0_VF25_MAILBOX_INT_CNTL_BASE_IDX 2 #define mmBIF_BX_DEV0_EPF0_VF25_BIF_VMHV_MAILBOX 0x0140 #define mmBIF_BX_DEV0_EPF0_VF25_BIF_VMHV_MAILBOX_BASE_IDX 2 // addressBlock: nbio_nbif0_rcc_dev0_epf0_vf25_BIFDEC2 // base address: 0x0 #define mmRCC_DEV0_EPF0_VF25_GFXMSIX_VECT0_ADDR_LO 0x0400 #define mmRCC_DEV0_EPF0_VF25_GFXMSIX_VECT0_ADDR_LO_BASE_IDX 3 #define mmRCC_DEV0_EPF0_VF25_GFXMSIX_VECT0_ADDR_HI 0x0401 #define mmRCC_DEV0_EPF0_VF25_GFXMSIX_VECT0_ADDR_HI_BASE_IDX 3 #define mmRCC_DEV0_EPF0_VF25_GFXMSIX_VECT0_MSG_DATA 0x0402 #define mmRCC_DEV0_EPF0_VF25_GFXMSIX_VECT0_MSG_DATA_BASE_IDX 3 #define mmRCC_DEV0_EPF0_VF25_GFXMSIX_VECT0_CONTROL 0x0403 #define mmRCC_DEV0_EPF0_VF25_GFXMSIX_VECT0_CONTROL_BASE_IDX 3 #define mmRCC_DEV0_EPF0_VF25_GFXMSIX_VECT1_ADDR_LO 0x0404 #define mmRCC_DEV0_EPF0_VF25_GFXMSIX_VECT1_ADDR_LO_BASE_IDX 3 #define mmRCC_DEV0_EPF0_VF25_GFXMSIX_VECT1_ADDR_HI 0x0405 #define mmRCC_DEV0_EPF0_VF25_GFXMSIX_VECT1_ADDR_HI_BASE_IDX 3 #define mmRCC_DEV0_EPF0_VF25_GFXMSIX_VECT1_MSG_DATA 0x0406 #define mmRCC_DEV0_EPF0_VF25_GFXMSIX_VECT1_MSG_DATA_BASE_IDX 3 #define mmRCC_DEV0_EPF0_VF25_GFXMSIX_VECT1_CONTROL 0x0407 #define mmRCC_DEV0_EPF0_VF25_GFXMSIX_VECT1_CONTROL_BASE_IDX 3 #define mmRCC_DEV0_EPF0_VF25_GFXMSIX_VECT2_ADDR_LO 0x0408 #define mmRCC_DEV0_EPF0_VF25_GFXMSIX_VECT2_ADDR_LO_BASE_IDX 3 #define mmRCC_DEV0_EPF0_VF25_GFXMSIX_VECT2_ADDR_HI 0x0409 #define mmRCC_DEV0_EPF0_VF25_GFXMSIX_VECT2_ADDR_HI_BASE_IDX 3 #define mmRCC_DEV0_EPF0_VF25_GFXMSIX_VECT2_MSG_DATA 0x040a #define mmRCC_DEV0_EPF0_VF25_GFXMSIX_VECT2_MSG_DATA_BASE_IDX 3 #define mmRCC_DEV0_EPF0_VF25_GFXMSIX_VECT2_CONTROL 0x040b #define mmRCC_DEV0_EPF0_VF25_GFXMSIX_VECT2_CONTROL_BASE_IDX 3 #define mmRCC_DEV0_EPF0_VF25_GFXMSIX_VECT3_ADDR_LO 0x040c #define mmRCC_DEV0_EPF0_VF25_GFXMSIX_VECT3_ADDR_LO_BASE_IDX 3 #define mmRCC_DEV0_EPF0_VF25_GFXMSIX_VECT3_ADDR_HI 0x040d #define mmRCC_DEV0_EPF0_VF25_GFXMSIX_VECT3_ADDR_HI_BASE_IDX 3 #define mmRCC_DEV0_EPF0_VF25_GFXMSIX_VECT3_MSG_DATA 0x040e #define mmRCC_DEV0_EPF0_VF25_GFXMSIX_VECT3_MSG_DATA_BASE_IDX 3 #define mmRCC_DEV0_EPF0_VF25_GFXMSIX_VECT3_CONTROL 0x040f #define mmRCC_DEV0_EPF0_VF25_GFXMSIX_VECT3_CONTROL_BASE_IDX 3 #define mmRCC_DEV0_EPF0_VF25_GFXMSIX_PBA 0x0800 #define mmRCC_DEV0_EPF0_VF25_GFXMSIX_PBA_BASE_IDX 3 // addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf26_SYSPFVFDEC // base address: 0x0 #define mmBIF_BX_DEV0_EPF0_VF26_MM_INDEX 0x0000 #define mmBIF_BX_DEV0_EPF0_VF26_MM_INDEX_BASE_IDX 0 #define mmBIF_BX_DEV0_EPF0_VF26_MM_DATA 0x0001 #define mmBIF_BX_DEV0_EPF0_VF26_MM_DATA_BASE_IDX 0 #define mmBIF_BX_DEV0_EPF0_VF26_MM_INDEX_HI 0x0006 #define mmBIF_BX_DEV0_EPF0_VF26_MM_INDEX_HI_BASE_IDX 0 // addressBlock: nbio_nbif0_rcc_dev0_epf0_vf26_BIFPFVFDEC1 // base address: 0x0 #define mmRCC_DEV0_EPF0_VF26_RCC_ERR_LOG 0x0085 #define mmRCC_DEV0_EPF0_VF26_RCC_ERR_LOG_BASE_IDX 2 #define mmRCC_DEV0_EPF0_VF26_RCC_DOORBELL_APER_EN 0x00c0 #define mmRCC_DEV0_EPF0_VF26_RCC_DOORBELL_APER_EN_BASE_IDX 2 #define mmRCC_DEV0_EPF0_VF26_RCC_CONFIG_MEMSIZE 0x00c3 #define mmRCC_DEV0_EPF0_VF26_RCC_CONFIG_MEMSIZE_BASE_IDX 2 #define mmRCC_DEV0_EPF0_VF26_RCC_CONFIG_RESERVED 0x00c4 #define mmRCC_DEV0_EPF0_VF26_RCC_CONFIG_RESERVED_BASE_IDX 2 #define mmRCC_DEV0_EPF0_VF26_RCC_IOV_FUNC_IDENTIFIER 0x00c5 #define mmRCC_DEV0_EPF0_VF26_RCC_IOV_FUNC_IDENTIFIER_BASE_IDX 2 // addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf26_BIFPFVFDEC1 // base address: 0x0 #define mmBIF_BX_DEV0_EPF0_VF26_BIF_BME_STATUS 0x00eb #define mmBIF_BX_DEV0_EPF0_VF26_BIF_BME_STATUS_BASE_IDX 2 #define mmBIF_BX_DEV0_EPF0_VF26_BIF_ATOMIC_ERR_LOG 0x00ec #define mmBIF_BX_DEV0_EPF0_VF26_BIF_ATOMIC_ERR_LOG_BASE_IDX 2 #define mmBIF_BX_DEV0_EPF0_VF26_DOORBELL_SELFRING_GPA_APER_BASE_HIGH 0x00f3 #define your_sha256_hashE_IDX 2 #define mmBIF_BX_DEV0_EPF0_VF26_DOORBELL_SELFRING_GPA_APER_BASE_LOW 0x00f4 #define your_sha256_hash_IDX 2 #define mmBIF_BX_DEV0_EPF0_VF26_DOORBELL_SELFRING_GPA_APER_CNTL 0x00f5 #define your_sha256_hash 2 #define mmBIF_BX_DEV0_EPF0_VF26_HDP_REG_COHERENCY_FLUSH_CNTL 0x00f6 #define mmBIF_BX_DEV0_EPF0_VF26_HDP_REG_COHERENCY_FLUSH_CNTL_BASE_IDX 2 #define mmBIF_BX_DEV0_EPF0_VF26_HDP_MEM_COHERENCY_FLUSH_CNTL 0x00f7 #define mmBIF_BX_DEV0_EPF0_VF26_HDP_MEM_COHERENCY_FLUSH_CNTL_BASE_IDX 2 #define mmBIF_BX_DEV0_EPF0_VF26_GPU_HDP_FLUSH_REQ 0x0106 #define mmBIF_BX_DEV0_EPF0_VF26_GPU_HDP_FLUSH_REQ_BASE_IDX 2 #define mmBIF_BX_DEV0_EPF0_VF26_GPU_HDP_FLUSH_DONE 0x0107 #define mmBIF_BX_DEV0_EPF0_VF26_GPU_HDP_FLUSH_DONE_BASE_IDX 2 #define mmBIF_BX_DEV0_EPF0_VF26_BIF_TRANS_PENDING 0x0108 #define mmBIF_BX_DEV0_EPF0_VF26_BIF_TRANS_PENDING_BASE_IDX 2 #define mmBIF_BX_DEV0_EPF0_VF26_NBIF_GFX_ADDR_LUT_BYPASS 0x0112 #define mmBIF_BX_DEV0_EPF0_VF26_NBIF_GFX_ADDR_LUT_BYPASS_BASE_IDX 2 #define mmBIF_BX_DEV0_EPF0_VF26_MAILBOX_MSGBUF_TRN_DW0 0x0136 #define mmBIF_BX_DEV0_EPF0_VF26_MAILBOX_MSGBUF_TRN_DW0_BASE_IDX 2 #define mmBIF_BX_DEV0_EPF0_VF26_MAILBOX_MSGBUF_TRN_DW1 0x0137 #define mmBIF_BX_DEV0_EPF0_VF26_MAILBOX_MSGBUF_TRN_DW1_BASE_IDX 2 #define mmBIF_BX_DEV0_EPF0_VF26_MAILBOX_MSGBUF_TRN_DW2 0x0138 #define mmBIF_BX_DEV0_EPF0_VF26_MAILBOX_MSGBUF_TRN_DW2_BASE_IDX 2 #define mmBIF_BX_DEV0_EPF0_VF26_MAILBOX_MSGBUF_TRN_DW3 0x0139 #define mmBIF_BX_DEV0_EPF0_VF26_MAILBOX_MSGBUF_TRN_DW3_BASE_IDX 2 #define mmBIF_BX_DEV0_EPF0_VF26_MAILBOX_MSGBUF_RCV_DW0 0x013a #define mmBIF_BX_DEV0_EPF0_VF26_MAILBOX_MSGBUF_RCV_DW0_BASE_IDX 2 #define mmBIF_BX_DEV0_EPF0_VF26_MAILBOX_MSGBUF_RCV_DW1 0x013b #define mmBIF_BX_DEV0_EPF0_VF26_MAILBOX_MSGBUF_RCV_DW1_BASE_IDX 2 #define mmBIF_BX_DEV0_EPF0_VF26_MAILBOX_MSGBUF_RCV_DW2 0x013c #define mmBIF_BX_DEV0_EPF0_VF26_MAILBOX_MSGBUF_RCV_DW2_BASE_IDX 2 #define mmBIF_BX_DEV0_EPF0_VF26_MAILBOX_MSGBUF_RCV_DW3 0x013d #define mmBIF_BX_DEV0_EPF0_VF26_MAILBOX_MSGBUF_RCV_DW3_BASE_IDX 2 #define mmBIF_BX_DEV0_EPF0_VF26_MAILBOX_CONTROL 0x013e #define mmBIF_BX_DEV0_EPF0_VF26_MAILBOX_CONTROL_BASE_IDX 2 #define mmBIF_BX_DEV0_EPF0_VF26_MAILBOX_INT_CNTL 0x013f #define mmBIF_BX_DEV0_EPF0_VF26_MAILBOX_INT_CNTL_BASE_IDX 2 #define mmBIF_BX_DEV0_EPF0_VF26_BIF_VMHV_MAILBOX 0x0140 #define mmBIF_BX_DEV0_EPF0_VF26_BIF_VMHV_MAILBOX_BASE_IDX 2 // addressBlock: nbio_nbif0_rcc_dev0_epf0_vf26_BIFDEC2 // base address: 0x0 #define mmRCC_DEV0_EPF0_VF26_GFXMSIX_VECT0_ADDR_LO 0x0400 #define mmRCC_DEV0_EPF0_VF26_GFXMSIX_VECT0_ADDR_LO_BASE_IDX 3 #define mmRCC_DEV0_EPF0_VF26_GFXMSIX_VECT0_ADDR_HI 0x0401 #define mmRCC_DEV0_EPF0_VF26_GFXMSIX_VECT0_ADDR_HI_BASE_IDX 3 #define mmRCC_DEV0_EPF0_VF26_GFXMSIX_VECT0_MSG_DATA 0x0402 #define mmRCC_DEV0_EPF0_VF26_GFXMSIX_VECT0_MSG_DATA_BASE_IDX 3 #define mmRCC_DEV0_EPF0_VF26_GFXMSIX_VECT0_CONTROL 0x0403 #define mmRCC_DEV0_EPF0_VF26_GFXMSIX_VECT0_CONTROL_BASE_IDX 3 #define mmRCC_DEV0_EPF0_VF26_GFXMSIX_VECT1_ADDR_LO 0x0404 #define mmRCC_DEV0_EPF0_VF26_GFXMSIX_VECT1_ADDR_LO_BASE_IDX 3 #define mmRCC_DEV0_EPF0_VF26_GFXMSIX_VECT1_ADDR_HI 0x0405 #define mmRCC_DEV0_EPF0_VF26_GFXMSIX_VECT1_ADDR_HI_BASE_IDX 3 #define mmRCC_DEV0_EPF0_VF26_GFXMSIX_VECT1_MSG_DATA 0x0406 #define mmRCC_DEV0_EPF0_VF26_GFXMSIX_VECT1_MSG_DATA_BASE_IDX 3 #define mmRCC_DEV0_EPF0_VF26_GFXMSIX_VECT1_CONTROL 0x0407 #define mmRCC_DEV0_EPF0_VF26_GFXMSIX_VECT1_CONTROL_BASE_IDX 3 #define mmRCC_DEV0_EPF0_VF26_GFXMSIX_VECT2_ADDR_LO 0x0408 #define mmRCC_DEV0_EPF0_VF26_GFXMSIX_VECT2_ADDR_LO_BASE_IDX 3 #define mmRCC_DEV0_EPF0_VF26_GFXMSIX_VECT2_ADDR_HI 0x0409 #define mmRCC_DEV0_EPF0_VF26_GFXMSIX_VECT2_ADDR_HI_BASE_IDX 3 #define mmRCC_DEV0_EPF0_VF26_GFXMSIX_VECT2_MSG_DATA 0x040a #define mmRCC_DEV0_EPF0_VF26_GFXMSIX_VECT2_MSG_DATA_BASE_IDX 3 #define mmRCC_DEV0_EPF0_VF26_GFXMSIX_VECT2_CONTROL 0x040b #define mmRCC_DEV0_EPF0_VF26_GFXMSIX_VECT2_CONTROL_BASE_IDX 3 #define mmRCC_DEV0_EPF0_VF26_GFXMSIX_VECT3_ADDR_LO 0x040c #define mmRCC_DEV0_EPF0_VF26_GFXMSIX_VECT3_ADDR_LO_BASE_IDX 3 #define mmRCC_DEV0_EPF0_VF26_GFXMSIX_VECT3_ADDR_HI 0x040d #define mmRCC_DEV0_EPF0_VF26_GFXMSIX_VECT3_ADDR_HI_BASE_IDX 3 #define mmRCC_DEV0_EPF0_VF26_GFXMSIX_VECT3_MSG_DATA 0x040e #define mmRCC_DEV0_EPF0_VF26_GFXMSIX_VECT3_MSG_DATA_BASE_IDX 3 #define mmRCC_DEV0_EPF0_VF26_GFXMSIX_VECT3_CONTROL 0x040f #define mmRCC_DEV0_EPF0_VF26_GFXMSIX_VECT3_CONTROL_BASE_IDX 3 #define mmRCC_DEV0_EPF0_VF26_GFXMSIX_PBA 0x0800 #define mmRCC_DEV0_EPF0_VF26_GFXMSIX_PBA_BASE_IDX 3 // addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf27_SYSPFVFDEC // base address: 0x0 #define mmBIF_BX_DEV0_EPF0_VF27_MM_INDEX 0x0000 #define mmBIF_BX_DEV0_EPF0_VF27_MM_INDEX_BASE_IDX 0 #define mmBIF_BX_DEV0_EPF0_VF27_MM_DATA 0x0001 #define mmBIF_BX_DEV0_EPF0_VF27_MM_DATA_BASE_IDX 0 #define mmBIF_BX_DEV0_EPF0_VF27_MM_INDEX_HI 0x0006 #define mmBIF_BX_DEV0_EPF0_VF27_MM_INDEX_HI_BASE_IDX 0 // addressBlock: nbio_nbif0_rcc_dev0_epf0_vf27_BIFPFVFDEC1 // base address: 0x0 #define mmRCC_DEV0_EPF0_VF27_RCC_ERR_LOG 0x0085 #define mmRCC_DEV0_EPF0_VF27_RCC_ERR_LOG_BASE_IDX 2 #define mmRCC_DEV0_EPF0_VF27_RCC_DOORBELL_APER_EN 0x00c0 #define mmRCC_DEV0_EPF0_VF27_RCC_DOORBELL_APER_EN_BASE_IDX 2 #define mmRCC_DEV0_EPF0_VF27_RCC_CONFIG_MEMSIZE 0x00c3 #define mmRCC_DEV0_EPF0_VF27_RCC_CONFIG_MEMSIZE_BASE_IDX 2 #define mmRCC_DEV0_EPF0_VF27_RCC_CONFIG_RESERVED 0x00c4 #define mmRCC_DEV0_EPF0_VF27_RCC_CONFIG_RESERVED_BASE_IDX 2 #define mmRCC_DEV0_EPF0_VF27_RCC_IOV_FUNC_IDENTIFIER 0x00c5 #define mmRCC_DEV0_EPF0_VF27_RCC_IOV_FUNC_IDENTIFIER_BASE_IDX 2 // addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf27_BIFPFVFDEC1 // base address: 0x0 #define mmBIF_BX_DEV0_EPF0_VF27_BIF_BME_STATUS 0x00eb #define mmBIF_BX_DEV0_EPF0_VF27_BIF_BME_STATUS_BASE_IDX 2 #define mmBIF_BX_DEV0_EPF0_VF27_BIF_ATOMIC_ERR_LOG 0x00ec #define mmBIF_BX_DEV0_EPF0_VF27_BIF_ATOMIC_ERR_LOG_BASE_IDX 2 #define mmBIF_BX_DEV0_EPF0_VF27_DOORBELL_SELFRING_GPA_APER_BASE_HIGH 0x00f3 #define your_sha256_hashE_IDX 2 #define mmBIF_BX_DEV0_EPF0_VF27_DOORBELL_SELFRING_GPA_APER_BASE_LOW 0x00f4 #define your_sha256_hash_IDX 2 #define mmBIF_BX_DEV0_EPF0_VF27_DOORBELL_SELFRING_GPA_APER_CNTL 0x00f5 #define your_sha256_hash 2 #define mmBIF_BX_DEV0_EPF0_VF27_HDP_REG_COHERENCY_FLUSH_CNTL 0x00f6 #define mmBIF_BX_DEV0_EPF0_VF27_HDP_REG_COHERENCY_FLUSH_CNTL_BASE_IDX 2 #define mmBIF_BX_DEV0_EPF0_VF27_HDP_MEM_COHERENCY_FLUSH_CNTL 0x00f7 #define mmBIF_BX_DEV0_EPF0_VF27_HDP_MEM_COHERENCY_FLUSH_CNTL_BASE_IDX 2 #define mmBIF_BX_DEV0_EPF0_VF27_GPU_HDP_FLUSH_REQ 0x0106 #define mmBIF_BX_DEV0_EPF0_VF27_GPU_HDP_FLUSH_REQ_BASE_IDX 2 #define mmBIF_BX_DEV0_EPF0_VF27_GPU_HDP_FLUSH_DONE 0x0107 #define mmBIF_BX_DEV0_EPF0_VF27_GPU_HDP_FLUSH_DONE_BASE_IDX 2 #define mmBIF_BX_DEV0_EPF0_VF27_BIF_TRANS_PENDING 0x0108 #define mmBIF_BX_DEV0_EPF0_VF27_BIF_TRANS_PENDING_BASE_IDX 2 #define mmBIF_BX_DEV0_EPF0_VF27_NBIF_GFX_ADDR_LUT_BYPASS 0x0112 #define mmBIF_BX_DEV0_EPF0_VF27_NBIF_GFX_ADDR_LUT_BYPASS_BASE_IDX 2 #define mmBIF_BX_DEV0_EPF0_VF27_MAILBOX_MSGBUF_TRN_DW0 0x0136 #define mmBIF_BX_DEV0_EPF0_VF27_MAILBOX_MSGBUF_TRN_DW0_BASE_IDX 2 #define mmBIF_BX_DEV0_EPF0_VF27_MAILBOX_MSGBUF_TRN_DW1 0x0137 #define mmBIF_BX_DEV0_EPF0_VF27_MAILBOX_MSGBUF_TRN_DW1_BASE_IDX 2 #define mmBIF_BX_DEV0_EPF0_VF27_MAILBOX_MSGBUF_TRN_DW2 0x0138 #define mmBIF_BX_DEV0_EPF0_VF27_MAILBOX_MSGBUF_TRN_DW2_BASE_IDX 2 #define mmBIF_BX_DEV0_EPF0_VF27_MAILBOX_MSGBUF_TRN_DW3 0x0139 #define mmBIF_BX_DEV0_EPF0_VF27_MAILBOX_MSGBUF_TRN_DW3_BASE_IDX 2 #define mmBIF_BX_DEV0_EPF0_VF27_MAILBOX_MSGBUF_RCV_DW0 0x013a #define mmBIF_BX_DEV0_EPF0_VF27_MAILBOX_MSGBUF_RCV_DW0_BASE_IDX 2 #define mmBIF_BX_DEV0_EPF0_VF27_MAILBOX_MSGBUF_RCV_DW1 0x013b #define mmBIF_BX_DEV0_EPF0_VF27_MAILBOX_MSGBUF_RCV_DW1_BASE_IDX 2 #define mmBIF_BX_DEV0_EPF0_VF27_MAILBOX_MSGBUF_RCV_DW2 0x013c #define mmBIF_BX_DEV0_EPF0_VF27_MAILBOX_MSGBUF_RCV_DW2_BASE_IDX 2 #define mmBIF_BX_DEV0_EPF0_VF27_MAILBOX_MSGBUF_RCV_DW3 0x013d #define mmBIF_BX_DEV0_EPF0_VF27_MAILBOX_MSGBUF_RCV_DW3_BASE_IDX 2 #define mmBIF_BX_DEV0_EPF0_VF27_MAILBOX_CONTROL 0x013e #define mmBIF_BX_DEV0_EPF0_VF27_MAILBOX_CONTROL_BASE_IDX 2 #define mmBIF_BX_DEV0_EPF0_VF27_MAILBOX_INT_CNTL 0x013f #define mmBIF_BX_DEV0_EPF0_VF27_MAILBOX_INT_CNTL_BASE_IDX 2 #define mmBIF_BX_DEV0_EPF0_VF27_BIF_VMHV_MAILBOX 0x0140 #define mmBIF_BX_DEV0_EPF0_VF27_BIF_VMHV_MAILBOX_BASE_IDX 2 // addressBlock: nbio_nbif0_rcc_dev0_epf0_vf27_BIFDEC2 // base address: 0x0 #define mmRCC_DEV0_EPF0_VF27_GFXMSIX_VECT0_ADDR_LO 0x0400 #define mmRCC_DEV0_EPF0_VF27_GFXMSIX_VECT0_ADDR_LO_BASE_IDX 3 #define mmRCC_DEV0_EPF0_VF27_GFXMSIX_VECT0_ADDR_HI 0x0401 #define mmRCC_DEV0_EPF0_VF27_GFXMSIX_VECT0_ADDR_HI_BASE_IDX 3 #define mmRCC_DEV0_EPF0_VF27_GFXMSIX_VECT0_MSG_DATA 0x0402 #define mmRCC_DEV0_EPF0_VF27_GFXMSIX_VECT0_MSG_DATA_BASE_IDX 3 #define mmRCC_DEV0_EPF0_VF27_GFXMSIX_VECT0_CONTROL 0x0403 #define mmRCC_DEV0_EPF0_VF27_GFXMSIX_VECT0_CONTROL_BASE_IDX 3 #define mmRCC_DEV0_EPF0_VF27_GFXMSIX_VECT1_ADDR_LO 0x0404 #define mmRCC_DEV0_EPF0_VF27_GFXMSIX_VECT1_ADDR_LO_BASE_IDX 3 #define mmRCC_DEV0_EPF0_VF27_GFXMSIX_VECT1_ADDR_HI 0x0405 #define mmRCC_DEV0_EPF0_VF27_GFXMSIX_VECT1_ADDR_HI_BASE_IDX 3 #define mmRCC_DEV0_EPF0_VF27_GFXMSIX_VECT1_MSG_DATA 0x0406 #define mmRCC_DEV0_EPF0_VF27_GFXMSIX_VECT1_MSG_DATA_BASE_IDX 3 #define mmRCC_DEV0_EPF0_VF27_GFXMSIX_VECT1_CONTROL 0x0407 #define mmRCC_DEV0_EPF0_VF27_GFXMSIX_VECT1_CONTROL_BASE_IDX 3 #define mmRCC_DEV0_EPF0_VF27_GFXMSIX_VECT2_ADDR_LO 0x0408 #define mmRCC_DEV0_EPF0_VF27_GFXMSIX_VECT2_ADDR_LO_BASE_IDX 3 #define mmRCC_DEV0_EPF0_VF27_GFXMSIX_VECT2_ADDR_HI 0x0409 #define mmRCC_DEV0_EPF0_VF27_GFXMSIX_VECT2_ADDR_HI_BASE_IDX 3 #define mmRCC_DEV0_EPF0_VF27_GFXMSIX_VECT2_MSG_DATA 0x040a #define mmRCC_DEV0_EPF0_VF27_GFXMSIX_VECT2_MSG_DATA_BASE_IDX 3 #define mmRCC_DEV0_EPF0_VF27_GFXMSIX_VECT2_CONTROL 0x040b #define mmRCC_DEV0_EPF0_VF27_GFXMSIX_VECT2_CONTROL_BASE_IDX 3 #define mmRCC_DEV0_EPF0_VF27_GFXMSIX_VECT3_ADDR_LO 0x040c #define mmRCC_DEV0_EPF0_VF27_GFXMSIX_VECT3_ADDR_LO_BASE_IDX 3 #define mmRCC_DEV0_EPF0_VF27_GFXMSIX_VECT3_ADDR_HI 0x040d #define mmRCC_DEV0_EPF0_VF27_GFXMSIX_VECT3_ADDR_HI_BASE_IDX 3 #define mmRCC_DEV0_EPF0_VF27_GFXMSIX_VECT3_MSG_DATA 0x040e #define mmRCC_DEV0_EPF0_VF27_GFXMSIX_VECT3_MSG_DATA_BASE_IDX 3 #define mmRCC_DEV0_EPF0_VF27_GFXMSIX_VECT3_CONTROL 0x040f #define mmRCC_DEV0_EPF0_VF27_GFXMSIX_VECT3_CONTROL_BASE_IDX 3 #define mmRCC_DEV0_EPF0_VF27_GFXMSIX_PBA 0x0800 #define mmRCC_DEV0_EPF0_VF27_GFXMSIX_PBA_BASE_IDX 3 // addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf28_SYSPFVFDEC // base address: 0x0 #define mmBIF_BX_DEV0_EPF0_VF28_MM_INDEX 0x0000 #define mmBIF_BX_DEV0_EPF0_VF28_MM_INDEX_BASE_IDX 0 #define mmBIF_BX_DEV0_EPF0_VF28_MM_DATA 0x0001 #define mmBIF_BX_DEV0_EPF0_VF28_MM_DATA_BASE_IDX 0 #define mmBIF_BX_DEV0_EPF0_VF28_MM_INDEX_HI 0x0006 #define mmBIF_BX_DEV0_EPF0_VF28_MM_INDEX_HI_BASE_IDX 0 // addressBlock: nbio_nbif0_rcc_dev0_epf0_vf28_BIFPFVFDEC1 // base address: 0x0 #define mmRCC_DEV0_EPF0_VF28_RCC_ERR_LOG 0x0085 #define mmRCC_DEV0_EPF0_VF28_RCC_ERR_LOG_BASE_IDX 2 #define mmRCC_DEV0_EPF0_VF28_RCC_DOORBELL_APER_EN 0x00c0 #define mmRCC_DEV0_EPF0_VF28_RCC_DOORBELL_APER_EN_BASE_IDX 2 #define mmRCC_DEV0_EPF0_VF28_RCC_CONFIG_MEMSIZE 0x00c3 #define mmRCC_DEV0_EPF0_VF28_RCC_CONFIG_MEMSIZE_BASE_IDX 2 #define mmRCC_DEV0_EPF0_VF28_RCC_CONFIG_RESERVED 0x00c4 #define mmRCC_DEV0_EPF0_VF28_RCC_CONFIG_RESERVED_BASE_IDX 2 #define mmRCC_DEV0_EPF0_VF28_RCC_IOV_FUNC_IDENTIFIER 0x00c5 #define mmRCC_DEV0_EPF0_VF28_RCC_IOV_FUNC_IDENTIFIER_BASE_IDX 2 // addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf28_BIFPFVFDEC1 // base address: 0x0 #define mmBIF_BX_DEV0_EPF0_VF28_BIF_BME_STATUS 0x00eb #define mmBIF_BX_DEV0_EPF0_VF28_BIF_BME_STATUS_BASE_IDX 2 #define mmBIF_BX_DEV0_EPF0_VF28_BIF_ATOMIC_ERR_LOG 0x00ec #define mmBIF_BX_DEV0_EPF0_VF28_BIF_ATOMIC_ERR_LOG_BASE_IDX 2 #define mmBIF_BX_DEV0_EPF0_VF28_DOORBELL_SELFRING_GPA_APER_BASE_HIGH 0x00f3 #define your_sha256_hashE_IDX 2 #define mmBIF_BX_DEV0_EPF0_VF28_DOORBELL_SELFRING_GPA_APER_BASE_LOW 0x00f4 #define your_sha256_hash_IDX 2 #define mmBIF_BX_DEV0_EPF0_VF28_DOORBELL_SELFRING_GPA_APER_CNTL 0x00f5 #define your_sha256_hash 2 #define mmBIF_BX_DEV0_EPF0_VF28_HDP_REG_COHERENCY_FLUSH_CNTL 0x00f6 #define mmBIF_BX_DEV0_EPF0_VF28_HDP_REG_COHERENCY_FLUSH_CNTL_BASE_IDX 2 #define mmBIF_BX_DEV0_EPF0_VF28_HDP_MEM_COHERENCY_FLUSH_CNTL 0x00f7 #define mmBIF_BX_DEV0_EPF0_VF28_HDP_MEM_COHERENCY_FLUSH_CNTL_BASE_IDX 2 #define mmBIF_BX_DEV0_EPF0_VF28_GPU_HDP_FLUSH_REQ 0x0106 #define mmBIF_BX_DEV0_EPF0_VF28_GPU_HDP_FLUSH_REQ_BASE_IDX 2 #define mmBIF_BX_DEV0_EPF0_VF28_GPU_HDP_FLUSH_DONE 0x0107 #define mmBIF_BX_DEV0_EPF0_VF28_GPU_HDP_FLUSH_DONE_BASE_IDX 2 #define mmBIF_BX_DEV0_EPF0_VF28_BIF_TRANS_PENDING 0x0108 #define mmBIF_BX_DEV0_EPF0_VF28_BIF_TRANS_PENDING_BASE_IDX 2 #define mmBIF_BX_DEV0_EPF0_VF28_NBIF_GFX_ADDR_LUT_BYPASS 0x0112 #define mmBIF_BX_DEV0_EPF0_VF28_NBIF_GFX_ADDR_LUT_BYPASS_BASE_IDX 2 #define mmBIF_BX_DEV0_EPF0_VF28_MAILBOX_MSGBUF_TRN_DW0 0x0136 #define mmBIF_BX_DEV0_EPF0_VF28_MAILBOX_MSGBUF_TRN_DW0_BASE_IDX 2 #define mmBIF_BX_DEV0_EPF0_VF28_MAILBOX_MSGBUF_TRN_DW1 0x0137 #define mmBIF_BX_DEV0_EPF0_VF28_MAILBOX_MSGBUF_TRN_DW1_BASE_IDX 2 #define mmBIF_BX_DEV0_EPF0_VF28_MAILBOX_MSGBUF_TRN_DW2 0x0138 #define mmBIF_BX_DEV0_EPF0_VF28_MAILBOX_MSGBUF_TRN_DW2_BASE_IDX 2 #define mmBIF_BX_DEV0_EPF0_VF28_MAILBOX_MSGBUF_TRN_DW3 0x0139 #define mmBIF_BX_DEV0_EPF0_VF28_MAILBOX_MSGBUF_TRN_DW3_BASE_IDX 2 #define mmBIF_BX_DEV0_EPF0_VF28_MAILBOX_MSGBUF_RCV_DW0 0x013a #define mmBIF_BX_DEV0_EPF0_VF28_MAILBOX_MSGBUF_RCV_DW0_BASE_IDX 2 #define mmBIF_BX_DEV0_EPF0_VF28_MAILBOX_MSGBUF_RCV_DW1 0x013b #define mmBIF_BX_DEV0_EPF0_VF28_MAILBOX_MSGBUF_RCV_DW1_BASE_IDX 2 #define mmBIF_BX_DEV0_EPF0_VF28_MAILBOX_MSGBUF_RCV_DW2 0x013c #define mmBIF_BX_DEV0_EPF0_VF28_MAILBOX_MSGBUF_RCV_DW2_BASE_IDX 2 #define mmBIF_BX_DEV0_EPF0_VF28_MAILBOX_MSGBUF_RCV_DW3 0x013d #define mmBIF_BX_DEV0_EPF0_VF28_MAILBOX_MSGBUF_RCV_DW3_BASE_IDX 2 #define mmBIF_BX_DEV0_EPF0_VF28_MAILBOX_CONTROL 0x013e #define mmBIF_BX_DEV0_EPF0_VF28_MAILBOX_CONTROL_BASE_IDX 2 #define mmBIF_BX_DEV0_EPF0_VF28_MAILBOX_INT_CNTL 0x013f #define mmBIF_BX_DEV0_EPF0_VF28_MAILBOX_INT_CNTL_BASE_IDX 2 #define mmBIF_BX_DEV0_EPF0_VF28_BIF_VMHV_MAILBOX 0x0140 #define mmBIF_BX_DEV0_EPF0_VF28_BIF_VMHV_MAILBOX_BASE_IDX 2 // addressBlock: nbio_nbif0_rcc_dev0_epf0_vf28_BIFDEC2 // base address: 0x0 #define mmRCC_DEV0_EPF0_VF28_GFXMSIX_VECT0_ADDR_LO 0x0400 #define mmRCC_DEV0_EPF0_VF28_GFXMSIX_VECT0_ADDR_LO_BASE_IDX 3 #define mmRCC_DEV0_EPF0_VF28_GFXMSIX_VECT0_ADDR_HI 0x0401 #define mmRCC_DEV0_EPF0_VF28_GFXMSIX_VECT0_ADDR_HI_BASE_IDX 3 #define mmRCC_DEV0_EPF0_VF28_GFXMSIX_VECT0_MSG_DATA 0x0402 #define mmRCC_DEV0_EPF0_VF28_GFXMSIX_VECT0_MSG_DATA_BASE_IDX 3 #define mmRCC_DEV0_EPF0_VF28_GFXMSIX_VECT0_CONTROL 0x0403 #define mmRCC_DEV0_EPF0_VF28_GFXMSIX_VECT0_CONTROL_BASE_IDX 3 #define mmRCC_DEV0_EPF0_VF28_GFXMSIX_VECT1_ADDR_LO 0x0404 #define mmRCC_DEV0_EPF0_VF28_GFXMSIX_VECT1_ADDR_LO_BASE_IDX 3 #define mmRCC_DEV0_EPF0_VF28_GFXMSIX_VECT1_ADDR_HI 0x0405 #define mmRCC_DEV0_EPF0_VF28_GFXMSIX_VECT1_ADDR_HI_BASE_IDX 3 #define mmRCC_DEV0_EPF0_VF28_GFXMSIX_VECT1_MSG_DATA 0x0406 #define mmRCC_DEV0_EPF0_VF28_GFXMSIX_VECT1_MSG_DATA_BASE_IDX 3 #define mmRCC_DEV0_EPF0_VF28_GFXMSIX_VECT1_CONTROL 0x0407 #define mmRCC_DEV0_EPF0_VF28_GFXMSIX_VECT1_CONTROL_BASE_IDX 3 #define mmRCC_DEV0_EPF0_VF28_GFXMSIX_VECT2_ADDR_LO 0x0408 #define mmRCC_DEV0_EPF0_VF28_GFXMSIX_VECT2_ADDR_LO_BASE_IDX 3 #define mmRCC_DEV0_EPF0_VF28_GFXMSIX_VECT2_ADDR_HI 0x0409 #define mmRCC_DEV0_EPF0_VF28_GFXMSIX_VECT2_ADDR_HI_BASE_IDX 3 #define mmRCC_DEV0_EPF0_VF28_GFXMSIX_VECT2_MSG_DATA 0x040a #define mmRCC_DEV0_EPF0_VF28_GFXMSIX_VECT2_MSG_DATA_BASE_IDX 3 #define mmRCC_DEV0_EPF0_VF28_GFXMSIX_VECT2_CONTROL 0x040b #define mmRCC_DEV0_EPF0_VF28_GFXMSIX_VECT2_CONTROL_BASE_IDX 3 #define mmRCC_DEV0_EPF0_VF28_GFXMSIX_VECT3_ADDR_LO 0x040c #define mmRCC_DEV0_EPF0_VF28_GFXMSIX_VECT3_ADDR_LO_BASE_IDX 3 #define mmRCC_DEV0_EPF0_VF28_GFXMSIX_VECT3_ADDR_HI 0x040d #define mmRCC_DEV0_EPF0_VF28_GFXMSIX_VECT3_ADDR_HI_BASE_IDX 3 #define mmRCC_DEV0_EPF0_VF28_GFXMSIX_VECT3_MSG_DATA 0x040e #define mmRCC_DEV0_EPF0_VF28_GFXMSIX_VECT3_MSG_DATA_BASE_IDX 3 #define mmRCC_DEV0_EPF0_VF28_GFXMSIX_VECT3_CONTROL 0x040f #define mmRCC_DEV0_EPF0_VF28_GFXMSIX_VECT3_CONTROL_BASE_IDX 3 #define mmRCC_DEV0_EPF0_VF28_GFXMSIX_PBA 0x0800 #define mmRCC_DEV0_EPF0_VF28_GFXMSIX_PBA_BASE_IDX 3 // addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf29_SYSPFVFDEC // base address: 0x0 #define mmBIF_BX_DEV0_EPF0_VF29_MM_INDEX 0x0000 #define mmBIF_BX_DEV0_EPF0_VF29_MM_INDEX_BASE_IDX 0 #define mmBIF_BX_DEV0_EPF0_VF29_MM_DATA 0x0001 #define mmBIF_BX_DEV0_EPF0_VF29_MM_DATA_BASE_IDX 0 #define mmBIF_BX_DEV0_EPF0_VF29_MM_INDEX_HI 0x0006 #define mmBIF_BX_DEV0_EPF0_VF29_MM_INDEX_HI_BASE_IDX 0 // addressBlock: nbio_nbif0_rcc_dev0_epf0_vf29_BIFPFVFDEC1 // base address: 0x0 #define mmRCC_DEV0_EPF0_VF29_RCC_ERR_LOG 0x0085 #define mmRCC_DEV0_EPF0_VF29_RCC_ERR_LOG_BASE_IDX 2 #define mmRCC_DEV0_EPF0_VF29_RCC_DOORBELL_APER_EN 0x00c0 #define mmRCC_DEV0_EPF0_VF29_RCC_DOORBELL_APER_EN_BASE_IDX 2 #define mmRCC_DEV0_EPF0_VF29_RCC_CONFIG_MEMSIZE 0x00c3 #define mmRCC_DEV0_EPF0_VF29_RCC_CONFIG_MEMSIZE_BASE_IDX 2 #define mmRCC_DEV0_EPF0_VF29_RCC_CONFIG_RESERVED 0x00c4 #define mmRCC_DEV0_EPF0_VF29_RCC_CONFIG_RESERVED_BASE_IDX 2 #define mmRCC_DEV0_EPF0_VF29_RCC_IOV_FUNC_IDENTIFIER 0x00c5 #define mmRCC_DEV0_EPF0_VF29_RCC_IOV_FUNC_IDENTIFIER_BASE_IDX 2 // addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf29_BIFPFVFDEC1 // base address: 0x0 #define mmBIF_BX_DEV0_EPF0_VF29_BIF_BME_STATUS 0x00eb #define mmBIF_BX_DEV0_EPF0_VF29_BIF_BME_STATUS_BASE_IDX 2 #define mmBIF_BX_DEV0_EPF0_VF29_BIF_ATOMIC_ERR_LOG 0x00ec #define mmBIF_BX_DEV0_EPF0_VF29_BIF_ATOMIC_ERR_LOG_BASE_IDX 2 #define mmBIF_BX_DEV0_EPF0_VF29_DOORBELL_SELFRING_GPA_APER_BASE_HIGH 0x00f3 #define your_sha256_hashE_IDX 2 #define mmBIF_BX_DEV0_EPF0_VF29_DOORBELL_SELFRING_GPA_APER_BASE_LOW 0x00f4 #define your_sha256_hash_IDX 2 #define mmBIF_BX_DEV0_EPF0_VF29_DOORBELL_SELFRING_GPA_APER_CNTL 0x00f5 #define your_sha256_hash 2 #define mmBIF_BX_DEV0_EPF0_VF29_HDP_REG_COHERENCY_FLUSH_CNTL 0x00f6 #define mmBIF_BX_DEV0_EPF0_VF29_HDP_REG_COHERENCY_FLUSH_CNTL_BASE_IDX 2 #define mmBIF_BX_DEV0_EPF0_VF29_HDP_MEM_COHERENCY_FLUSH_CNTL 0x00f7 #define mmBIF_BX_DEV0_EPF0_VF29_HDP_MEM_COHERENCY_FLUSH_CNTL_BASE_IDX 2 #define mmBIF_BX_DEV0_EPF0_VF29_GPU_HDP_FLUSH_REQ 0x0106 #define mmBIF_BX_DEV0_EPF0_VF29_GPU_HDP_FLUSH_REQ_BASE_IDX 2 #define mmBIF_BX_DEV0_EPF0_VF29_GPU_HDP_FLUSH_DONE 0x0107 #define mmBIF_BX_DEV0_EPF0_VF29_GPU_HDP_FLUSH_DONE_BASE_IDX 2 #define mmBIF_BX_DEV0_EPF0_VF29_BIF_TRANS_PENDING 0x0108 #define mmBIF_BX_DEV0_EPF0_VF29_BIF_TRANS_PENDING_BASE_IDX 2 #define mmBIF_BX_DEV0_EPF0_VF29_NBIF_GFX_ADDR_LUT_BYPASS 0x0112 #define mmBIF_BX_DEV0_EPF0_VF29_NBIF_GFX_ADDR_LUT_BYPASS_BASE_IDX 2 #define mmBIF_BX_DEV0_EPF0_VF29_MAILBOX_MSGBUF_TRN_DW0 0x0136 #define mmBIF_BX_DEV0_EPF0_VF29_MAILBOX_MSGBUF_TRN_DW0_BASE_IDX 2 #define mmBIF_BX_DEV0_EPF0_VF29_MAILBOX_MSGBUF_TRN_DW1 0x0137 #define mmBIF_BX_DEV0_EPF0_VF29_MAILBOX_MSGBUF_TRN_DW1_BASE_IDX 2 #define mmBIF_BX_DEV0_EPF0_VF29_MAILBOX_MSGBUF_TRN_DW2 0x0138 #define mmBIF_BX_DEV0_EPF0_VF29_MAILBOX_MSGBUF_TRN_DW2_BASE_IDX 2 #define mmBIF_BX_DEV0_EPF0_VF29_MAILBOX_MSGBUF_TRN_DW3 0x0139 #define mmBIF_BX_DEV0_EPF0_VF29_MAILBOX_MSGBUF_TRN_DW3_BASE_IDX 2 #define mmBIF_BX_DEV0_EPF0_VF29_MAILBOX_MSGBUF_RCV_DW0 0x013a #define mmBIF_BX_DEV0_EPF0_VF29_MAILBOX_MSGBUF_RCV_DW0_BASE_IDX 2 #define mmBIF_BX_DEV0_EPF0_VF29_MAILBOX_MSGBUF_RCV_DW1 0x013b #define mmBIF_BX_DEV0_EPF0_VF29_MAILBOX_MSGBUF_RCV_DW1_BASE_IDX 2 #define mmBIF_BX_DEV0_EPF0_VF29_MAILBOX_MSGBUF_RCV_DW2 0x013c #define mmBIF_BX_DEV0_EPF0_VF29_MAILBOX_MSGBUF_RCV_DW2_BASE_IDX 2 #define mmBIF_BX_DEV0_EPF0_VF29_MAILBOX_MSGBUF_RCV_DW3 0x013d #define mmBIF_BX_DEV0_EPF0_VF29_MAILBOX_MSGBUF_RCV_DW3_BASE_IDX 2 #define mmBIF_BX_DEV0_EPF0_VF29_MAILBOX_CONTROL 0x013e #define mmBIF_BX_DEV0_EPF0_VF29_MAILBOX_CONTROL_BASE_IDX 2 #define mmBIF_BX_DEV0_EPF0_VF29_MAILBOX_INT_CNTL 0x013f #define mmBIF_BX_DEV0_EPF0_VF29_MAILBOX_INT_CNTL_BASE_IDX 2 #define mmBIF_BX_DEV0_EPF0_VF29_BIF_VMHV_MAILBOX 0x0140 #define mmBIF_BX_DEV0_EPF0_VF29_BIF_VMHV_MAILBOX_BASE_IDX 2 // addressBlock: nbio_nbif0_rcc_dev0_epf0_vf29_BIFDEC2 // base address: 0x0 #define mmRCC_DEV0_EPF0_VF29_GFXMSIX_VECT0_ADDR_LO 0x0400 #define mmRCC_DEV0_EPF0_VF29_GFXMSIX_VECT0_ADDR_LO_BASE_IDX 3 #define mmRCC_DEV0_EPF0_VF29_GFXMSIX_VECT0_ADDR_HI 0x0401 #define mmRCC_DEV0_EPF0_VF29_GFXMSIX_VECT0_ADDR_HI_BASE_IDX 3 #define mmRCC_DEV0_EPF0_VF29_GFXMSIX_VECT0_MSG_DATA 0x0402 #define mmRCC_DEV0_EPF0_VF29_GFXMSIX_VECT0_MSG_DATA_BASE_IDX 3 #define mmRCC_DEV0_EPF0_VF29_GFXMSIX_VECT0_CONTROL 0x0403 #define mmRCC_DEV0_EPF0_VF29_GFXMSIX_VECT0_CONTROL_BASE_IDX 3 #define mmRCC_DEV0_EPF0_VF29_GFXMSIX_VECT1_ADDR_LO 0x0404 #define mmRCC_DEV0_EPF0_VF29_GFXMSIX_VECT1_ADDR_LO_BASE_IDX 3 #define mmRCC_DEV0_EPF0_VF29_GFXMSIX_VECT1_ADDR_HI 0x0405 #define mmRCC_DEV0_EPF0_VF29_GFXMSIX_VECT1_ADDR_HI_BASE_IDX 3 #define mmRCC_DEV0_EPF0_VF29_GFXMSIX_VECT1_MSG_DATA 0x0406 #define mmRCC_DEV0_EPF0_VF29_GFXMSIX_VECT1_MSG_DATA_BASE_IDX 3 #define mmRCC_DEV0_EPF0_VF29_GFXMSIX_VECT1_CONTROL 0x0407 #define mmRCC_DEV0_EPF0_VF29_GFXMSIX_VECT1_CONTROL_BASE_IDX 3 #define mmRCC_DEV0_EPF0_VF29_GFXMSIX_VECT2_ADDR_LO 0x0408 #define mmRCC_DEV0_EPF0_VF29_GFXMSIX_VECT2_ADDR_LO_BASE_IDX 3 #define mmRCC_DEV0_EPF0_VF29_GFXMSIX_VECT2_ADDR_HI 0x0409 #define mmRCC_DEV0_EPF0_VF29_GFXMSIX_VECT2_ADDR_HI_BASE_IDX 3 #define mmRCC_DEV0_EPF0_VF29_GFXMSIX_VECT2_MSG_DATA 0x040a #define mmRCC_DEV0_EPF0_VF29_GFXMSIX_VECT2_MSG_DATA_BASE_IDX 3 #define mmRCC_DEV0_EPF0_VF29_GFXMSIX_VECT2_CONTROL 0x040b #define mmRCC_DEV0_EPF0_VF29_GFXMSIX_VECT2_CONTROL_BASE_IDX 3 #define mmRCC_DEV0_EPF0_VF29_GFXMSIX_VECT3_ADDR_LO 0x040c #define mmRCC_DEV0_EPF0_VF29_GFXMSIX_VECT3_ADDR_LO_BASE_IDX 3 #define mmRCC_DEV0_EPF0_VF29_GFXMSIX_VECT3_ADDR_HI 0x040d #define mmRCC_DEV0_EPF0_VF29_GFXMSIX_VECT3_ADDR_HI_BASE_IDX 3 #define mmRCC_DEV0_EPF0_VF29_GFXMSIX_VECT3_MSG_DATA 0x040e #define mmRCC_DEV0_EPF0_VF29_GFXMSIX_VECT3_MSG_DATA_BASE_IDX 3 #define mmRCC_DEV0_EPF0_VF29_GFXMSIX_VECT3_CONTROL 0x040f #define mmRCC_DEV0_EPF0_VF29_GFXMSIX_VECT3_CONTROL_BASE_IDX 3 #define mmRCC_DEV0_EPF0_VF29_GFXMSIX_PBA 0x0800 #define mmRCC_DEV0_EPF0_VF29_GFXMSIX_PBA_BASE_IDX 3 // addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf30_SYSPFVFDEC // base address: 0x0 #define mmBIF_BX_DEV0_EPF0_VF30_MM_INDEX 0x0000 #define mmBIF_BX_DEV0_EPF0_VF30_MM_INDEX_BASE_IDX 0 #define mmBIF_BX_DEV0_EPF0_VF30_MM_DATA 0x0001 #define mmBIF_BX_DEV0_EPF0_VF30_MM_DATA_BASE_IDX 0 #define mmBIF_BX_DEV0_EPF0_VF30_MM_INDEX_HI 0x0006 #define mmBIF_BX_DEV0_EPF0_VF30_MM_INDEX_HI_BASE_IDX 0 // addressBlock: nbio_nbif0_rcc_dev0_epf0_vf30_BIFPFVFDEC1 // base address: 0x0 #define mmRCC_DEV0_EPF0_VF30_RCC_ERR_LOG 0x0085 #define mmRCC_DEV0_EPF0_VF30_RCC_ERR_LOG_BASE_IDX 2 #define mmRCC_DEV0_EPF0_VF30_RCC_DOORBELL_APER_EN 0x00c0 #define mmRCC_DEV0_EPF0_VF30_RCC_DOORBELL_APER_EN_BASE_IDX 2 #define mmRCC_DEV0_EPF0_VF30_RCC_CONFIG_MEMSIZE 0x00c3 #define mmRCC_DEV0_EPF0_VF30_RCC_CONFIG_MEMSIZE_BASE_IDX 2 #define mmRCC_DEV0_EPF0_VF30_RCC_CONFIG_RESERVED 0x00c4 #define mmRCC_DEV0_EPF0_VF30_RCC_CONFIG_RESERVED_BASE_IDX 2 #define mmRCC_DEV0_EPF0_VF30_RCC_IOV_FUNC_IDENTIFIER 0x00c5 #define mmRCC_DEV0_EPF0_VF30_RCC_IOV_FUNC_IDENTIFIER_BASE_IDX 2 // addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf30_BIFPFVFDEC1 // base address: 0x0 #define mmBIF_BX_DEV0_EPF0_VF30_BIF_BME_STATUS 0x00eb #define mmBIF_BX_DEV0_EPF0_VF30_BIF_BME_STATUS_BASE_IDX 2 #define mmBIF_BX_DEV0_EPF0_VF30_BIF_ATOMIC_ERR_LOG 0x00ec #define mmBIF_BX_DEV0_EPF0_VF30_BIF_ATOMIC_ERR_LOG_BASE_IDX 2 #define mmBIF_BX_DEV0_EPF0_VF30_DOORBELL_SELFRING_GPA_APER_BASE_HIGH 0x00f3 #define your_sha256_hashE_IDX 2 #define mmBIF_BX_DEV0_EPF0_VF30_DOORBELL_SELFRING_GPA_APER_BASE_LOW 0x00f4 #define your_sha256_hash_IDX 2 #define mmBIF_BX_DEV0_EPF0_VF30_DOORBELL_SELFRING_GPA_APER_CNTL 0x00f5 #define your_sha256_hash 2 #define mmBIF_BX_DEV0_EPF0_VF30_HDP_REG_COHERENCY_FLUSH_CNTL 0x00f6 #define mmBIF_BX_DEV0_EPF0_VF30_HDP_REG_COHERENCY_FLUSH_CNTL_BASE_IDX 2 #define mmBIF_BX_DEV0_EPF0_VF30_HDP_MEM_COHERENCY_FLUSH_CNTL 0x00f7 #define mmBIF_BX_DEV0_EPF0_VF30_HDP_MEM_COHERENCY_FLUSH_CNTL_BASE_IDX 2 #define mmBIF_BX_DEV0_EPF0_VF30_GPU_HDP_FLUSH_REQ 0x0106 #define mmBIF_BX_DEV0_EPF0_VF30_GPU_HDP_FLUSH_REQ_BASE_IDX 2 #define mmBIF_BX_DEV0_EPF0_VF30_GPU_HDP_FLUSH_DONE 0x0107 #define mmBIF_BX_DEV0_EPF0_VF30_GPU_HDP_FLUSH_DONE_BASE_IDX 2 #define mmBIF_BX_DEV0_EPF0_VF30_BIF_TRANS_PENDING 0x0108 #define mmBIF_BX_DEV0_EPF0_VF30_BIF_TRANS_PENDING_BASE_IDX 2 #define mmBIF_BX_DEV0_EPF0_VF30_NBIF_GFX_ADDR_LUT_BYPASS 0x0112 #define mmBIF_BX_DEV0_EPF0_VF30_NBIF_GFX_ADDR_LUT_BYPASS_BASE_IDX 2 #define mmBIF_BX_DEV0_EPF0_VF30_MAILBOX_MSGBUF_TRN_DW0 0x0136 #define mmBIF_BX_DEV0_EPF0_VF30_MAILBOX_MSGBUF_TRN_DW0_BASE_IDX 2 #define mmBIF_BX_DEV0_EPF0_VF30_MAILBOX_MSGBUF_TRN_DW1 0x0137 #define mmBIF_BX_DEV0_EPF0_VF30_MAILBOX_MSGBUF_TRN_DW1_BASE_IDX 2 #define mmBIF_BX_DEV0_EPF0_VF30_MAILBOX_MSGBUF_TRN_DW2 0x0138 #define mmBIF_BX_DEV0_EPF0_VF30_MAILBOX_MSGBUF_TRN_DW2_BASE_IDX 2 #define mmBIF_BX_DEV0_EPF0_VF30_MAILBOX_MSGBUF_TRN_DW3 0x0139 #define mmBIF_BX_DEV0_EPF0_VF30_MAILBOX_MSGBUF_TRN_DW3_BASE_IDX 2 #define mmBIF_BX_DEV0_EPF0_VF30_MAILBOX_MSGBUF_RCV_DW0 0x013a #define mmBIF_BX_DEV0_EPF0_VF30_MAILBOX_MSGBUF_RCV_DW0_BASE_IDX 2 #define mmBIF_BX_DEV0_EPF0_VF30_MAILBOX_MSGBUF_RCV_DW1 0x013b #define mmBIF_BX_DEV0_EPF0_VF30_MAILBOX_MSGBUF_RCV_DW1_BASE_IDX 2 #define mmBIF_BX_DEV0_EPF0_VF30_MAILBOX_MSGBUF_RCV_DW2 0x013c #define mmBIF_BX_DEV0_EPF0_VF30_MAILBOX_MSGBUF_RCV_DW2_BASE_IDX 2 #define mmBIF_BX_DEV0_EPF0_VF30_MAILBOX_MSGBUF_RCV_DW3 0x013d #define mmBIF_BX_DEV0_EPF0_VF30_MAILBOX_MSGBUF_RCV_DW3_BASE_IDX 2 #define mmBIF_BX_DEV0_EPF0_VF30_MAILBOX_CONTROL 0x013e #define mmBIF_BX_DEV0_EPF0_VF30_MAILBOX_CONTROL_BASE_IDX 2 #define mmBIF_BX_DEV0_EPF0_VF30_MAILBOX_INT_CNTL 0x013f #define mmBIF_BX_DEV0_EPF0_VF30_MAILBOX_INT_CNTL_BASE_IDX 2 #define mmBIF_BX_DEV0_EPF0_VF30_BIF_VMHV_MAILBOX 0x0140 #define mmBIF_BX_DEV0_EPF0_VF30_BIF_VMHV_MAILBOX_BASE_IDX 2 // addressBlock: nbio_nbif0_rcc_dev0_epf0_vf30_BIFDEC2 // base address: 0x0 #define mmRCC_DEV0_EPF0_VF30_GFXMSIX_VECT0_ADDR_LO 0x0400 #define mmRCC_DEV0_EPF0_VF30_GFXMSIX_VECT0_ADDR_LO_BASE_IDX 3 #define mmRCC_DEV0_EPF0_VF30_GFXMSIX_VECT0_ADDR_HI 0x0401 #define mmRCC_DEV0_EPF0_VF30_GFXMSIX_VECT0_ADDR_HI_BASE_IDX 3 #define mmRCC_DEV0_EPF0_VF30_GFXMSIX_VECT0_MSG_DATA 0x0402 #define mmRCC_DEV0_EPF0_VF30_GFXMSIX_VECT0_MSG_DATA_BASE_IDX 3 #define mmRCC_DEV0_EPF0_VF30_GFXMSIX_VECT0_CONTROL 0x0403 #define mmRCC_DEV0_EPF0_VF30_GFXMSIX_VECT0_CONTROL_BASE_IDX 3 #define mmRCC_DEV0_EPF0_VF30_GFXMSIX_VECT1_ADDR_LO 0x0404 #define mmRCC_DEV0_EPF0_VF30_GFXMSIX_VECT1_ADDR_LO_BASE_IDX 3 #define mmRCC_DEV0_EPF0_VF30_GFXMSIX_VECT1_ADDR_HI 0x0405 #define mmRCC_DEV0_EPF0_VF30_GFXMSIX_VECT1_ADDR_HI_BASE_IDX 3 #define mmRCC_DEV0_EPF0_VF30_GFXMSIX_VECT1_MSG_DATA 0x0406 #define mmRCC_DEV0_EPF0_VF30_GFXMSIX_VECT1_MSG_DATA_BASE_IDX 3 #define mmRCC_DEV0_EPF0_VF30_GFXMSIX_VECT1_CONTROL 0x0407 #define mmRCC_DEV0_EPF0_VF30_GFXMSIX_VECT1_CONTROL_BASE_IDX 3 #define mmRCC_DEV0_EPF0_VF30_GFXMSIX_VECT2_ADDR_LO 0x0408 #define mmRCC_DEV0_EPF0_VF30_GFXMSIX_VECT2_ADDR_LO_BASE_IDX 3 #define mmRCC_DEV0_EPF0_VF30_GFXMSIX_VECT2_ADDR_HI 0x0409 #define mmRCC_DEV0_EPF0_VF30_GFXMSIX_VECT2_ADDR_HI_BASE_IDX 3 #define mmRCC_DEV0_EPF0_VF30_GFXMSIX_VECT2_MSG_DATA 0x040a #define mmRCC_DEV0_EPF0_VF30_GFXMSIX_VECT2_MSG_DATA_BASE_IDX 3 #define mmRCC_DEV0_EPF0_VF30_GFXMSIX_VECT2_CONTROL 0x040b #define mmRCC_DEV0_EPF0_VF30_GFXMSIX_VECT2_CONTROL_BASE_IDX 3 #define mmRCC_DEV0_EPF0_VF30_GFXMSIX_VECT3_ADDR_LO 0x040c #define mmRCC_DEV0_EPF0_VF30_GFXMSIX_VECT3_ADDR_LO_BASE_IDX 3 #define mmRCC_DEV0_EPF0_VF30_GFXMSIX_VECT3_ADDR_HI 0x040d #define mmRCC_DEV0_EPF0_VF30_GFXMSIX_VECT3_ADDR_HI_BASE_IDX 3 #define mmRCC_DEV0_EPF0_VF30_GFXMSIX_VECT3_MSG_DATA 0x040e #define mmRCC_DEV0_EPF0_VF30_GFXMSIX_VECT3_MSG_DATA_BASE_IDX 3 #define mmRCC_DEV0_EPF0_VF30_GFXMSIX_VECT3_CONTROL 0x040f #define mmRCC_DEV0_EPF0_VF30_GFXMSIX_VECT3_CONTROL_BASE_IDX 3 #define mmRCC_DEV0_EPF0_VF30_GFXMSIX_PBA 0x0800 #define mmRCC_DEV0_EPF0_VF30_GFXMSIX_PBA_BASE_IDX 3 // addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf0_SYSPFVFDEC // base address: 0xd0000000 #define cfgBIF_BX_DEV0_EPF0_VF0_MM_INDEX 0xd0000000 #define cfgBIF_BX_DEV0_EPF0_VF0_MM_DATA 0xd0000004 #define cfgBIF_BX_DEV0_EPF0_VF0_MM_INDEX_HI 0xd0000018 // addressBlock: nbio_nbif0_rcc_dev0_epf0_vf0_BIFPFVFDEC1 // base address: 0xd0000000 #define cfgRCC_DEV0_EPF0_VF0_RCC_ERR_LOG 0xd0003694 #define cfgRCC_DEV0_EPF0_VF0_RCC_DOORBELL_APER_EN 0xd0003780 #define cfgRCC_DEV0_EPF0_VF0_RCC_CONFIG_MEMSIZE 0xd000378c #define cfgRCC_DEV0_EPF0_VF0_RCC_CONFIG_RESERVED 0xd0003790 #define cfgRCC_DEV0_EPF0_VF0_RCC_IOV_FUNC_IDENTIFIER 0xd0003794 // addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf0_BIFPFVFDEC1 // base address: 0xd0000000 #define cfgBIF_BX_DEV0_EPF0_VF0_BIF_BME_STATUS 0xd000382c #define cfgBIF_BX_DEV0_EPF0_VF0_BIF_ATOMIC_ERR_LOG 0xd0003830 #define cfgBIF_BX_DEV0_EPF0_VF0_DOORBELL_SELFRING_GPA_APER_BASE_HIGH 0xd000384c #define cfgBIF_BX_DEV0_EPF0_VF0_DOORBELL_SELFRING_GPA_APER_BASE_LOW 0xd0003850 #define cfgBIF_BX_DEV0_EPF0_VF0_DOORBELL_SELFRING_GPA_APER_CNTL 0xd0003854 #define cfgBIF_BX_DEV0_EPF0_VF0_HDP_REG_COHERENCY_FLUSH_CNTL 0xd0003858 #define cfgBIF_BX_DEV0_EPF0_VF0_HDP_MEM_COHERENCY_FLUSH_CNTL 0xd000385c #define cfgBIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_REQ 0xd0003898 #define cfgBIF_BX_DEV0_EPF0_VF0_GPU_HDP_FLUSH_DONE 0xd000389c #define cfgBIF_BX_DEV0_EPF0_VF0_BIF_TRANS_PENDING 0xd00038a0 #define cfgBIF_BX_DEV0_EPF0_VF0_NBIF_GFX_ADDR_LUT_BYPASS 0xd00038c8 #define cfgBIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_TRN_DW0 0xd0003958 #define cfgBIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_TRN_DW1 0xd000395c #define cfgBIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_TRN_DW2 0xd0003960 #define cfgBIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_TRN_DW3 0xd0003964 #define cfgBIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_RCV_DW0 0xd0003968 #define cfgBIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_RCV_DW1 0xd000396c #define cfgBIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_RCV_DW2 0xd0003970 #define cfgBIF_BX_DEV0_EPF0_VF0_MAILBOX_MSGBUF_RCV_DW3 0xd0003974 #define cfgBIF_BX_DEV0_EPF0_VF0_MAILBOX_CONTROL 0xd0003978 #define cfgBIF_BX_DEV0_EPF0_VF0_MAILBOX_INT_CNTL 0xd000397c #define cfgBIF_BX_DEV0_EPF0_VF0_BIF_VMHV_MAILBOX 0xd0003980 // addressBlock: nbio_nbif0_rcc_dev0_epf0_vf0_BIFDEC2 // base address: 0xd0000000 #define cfgRCC_DEV0_EPF0_VF0_GFXMSIX_VECT0_ADDR_LO 0xd0042000 #define cfgRCC_DEV0_EPF0_VF0_GFXMSIX_VECT0_ADDR_HI 0xd0042004 #define cfgRCC_DEV0_EPF0_VF0_GFXMSIX_VECT0_MSG_DATA 0xd0042008 #define cfgRCC_DEV0_EPF0_VF0_GFXMSIX_VECT0_CONTROL 0xd004200c #define cfgRCC_DEV0_EPF0_VF0_GFXMSIX_VECT1_ADDR_LO 0xd0042010 #define cfgRCC_DEV0_EPF0_VF0_GFXMSIX_VECT1_ADDR_HI 0xd0042014 #define cfgRCC_DEV0_EPF0_VF0_GFXMSIX_VECT1_MSG_DATA 0xd0042018 #define cfgRCC_DEV0_EPF0_VF0_GFXMSIX_VECT1_CONTROL 0xd004201c #define cfgRCC_DEV0_EPF0_VF0_GFXMSIX_VECT2_ADDR_LO 0xd0042020 #define cfgRCC_DEV0_EPF0_VF0_GFXMSIX_VECT2_ADDR_HI 0xd0042024 #define cfgRCC_DEV0_EPF0_VF0_GFXMSIX_VECT2_MSG_DATA 0xd0042028 #define cfgRCC_DEV0_EPF0_VF0_GFXMSIX_VECT2_CONTROL 0xd004202c #define cfgRCC_DEV0_EPF0_VF0_GFXMSIX_VECT3_ADDR_LO 0xd0042030 #define cfgRCC_DEV0_EPF0_VF0_GFXMSIX_VECT3_ADDR_HI 0xd0042034 #define cfgRCC_DEV0_EPF0_VF0_GFXMSIX_VECT3_MSG_DATA 0xd0042038 #define cfgRCC_DEV0_EPF0_VF0_GFXMSIX_VECT3_CONTROL 0xd004203c #define cfgRCC_DEV0_EPF0_VF0_GFXMSIX_PBA 0xd0043000 // addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf1_SYSPFVFDEC // base address: 0xd0080000 #define cfgBIF_BX_DEV0_EPF0_VF1_MM_INDEX 0xd0080000 #define cfgBIF_BX_DEV0_EPF0_VF1_MM_DATA 0xd0080004 #define cfgBIF_BX_DEV0_EPF0_VF1_MM_INDEX_HI 0xd0080018 // addressBlock: nbio_nbif0_rcc_dev0_epf0_vf1_BIFPFVFDEC1 // base address: 0xd0080000 #define cfgRCC_DEV0_EPF0_VF1_RCC_ERR_LOG 0xd0083694 #define cfgRCC_DEV0_EPF0_VF1_RCC_DOORBELL_APER_EN 0xd0083780 #define cfgRCC_DEV0_EPF0_VF1_RCC_CONFIG_MEMSIZE 0xd008378c #define cfgRCC_DEV0_EPF0_VF1_RCC_CONFIG_RESERVED 0xd0083790 #define cfgRCC_DEV0_EPF0_VF1_RCC_IOV_FUNC_IDENTIFIER 0xd0083794 // addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf1_BIFPFVFDEC1 // base address: 0xd0080000 #define cfgBIF_BX_DEV0_EPF0_VF1_BIF_BME_STATUS 0xd008382c #define cfgBIF_BX_DEV0_EPF0_VF1_BIF_ATOMIC_ERR_LOG 0xd0083830 #define cfgBIF_BX_DEV0_EPF0_VF1_DOORBELL_SELFRING_GPA_APER_BASE_HIGH 0xd008384c #define cfgBIF_BX_DEV0_EPF0_VF1_DOORBELL_SELFRING_GPA_APER_BASE_LOW 0xd0083850 #define cfgBIF_BX_DEV0_EPF0_VF1_DOORBELL_SELFRING_GPA_APER_CNTL 0xd0083854 #define cfgBIF_BX_DEV0_EPF0_VF1_HDP_REG_COHERENCY_FLUSH_CNTL 0xd0083858 #define cfgBIF_BX_DEV0_EPF0_VF1_HDP_MEM_COHERENCY_FLUSH_CNTL 0xd008385c #define cfgBIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_REQ 0xd0083898 #define cfgBIF_BX_DEV0_EPF0_VF1_GPU_HDP_FLUSH_DONE 0xd008389c #define cfgBIF_BX_DEV0_EPF0_VF1_BIF_TRANS_PENDING 0xd00838a0 #define cfgBIF_BX_DEV0_EPF0_VF1_NBIF_GFX_ADDR_LUT_BYPASS 0xd00838c8 #define cfgBIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_TRN_DW0 0xd0083958 #define cfgBIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_TRN_DW1 0xd008395c #define cfgBIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_TRN_DW2 0xd0083960 #define cfgBIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_TRN_DW3 0xd0083964 #define cfgBIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_RCV_DW0 0xd0083968 #define cfgBIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_RCV_DW1 0xd008396c #define cfgBIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_RCV_DW2 0xd0083970 #define cfgBIF_BX_DEV0_EPF0_VF1_MAILBOX_MSGBUF_RCV_DW3 0xd0083974 #define cfgBIF_BX_DEV0_EPF0_VF1_MAILBOX_CONTROL 0xd0083978 #define cfgBIF_BX_DEV0_EPF0_VF1_MAILBOX_INT_CNTL 0xd008397c #define cfgBIF_BX_DEV0_EPF0_VF1_BIF_VMHV_MAILBOX 0xd0083980 // addressBlock: nbio_nbif0_rcc_dev0_epf0_vf1_BIFDEC2 // base address: 0xd0080000 #define cfgRCC_DEV0_EPF0_VF1_GFXMSIX_VECT0_ADDR_LO 0xd00c2000 #define cfgRCC_DEV0_EPF0_VF1_GFXMSIX_VECT0_ADDR_HI 0xd00c2004 #define cfgRCC_DEV0_EPF0_VF1_GFXMSIX_VECT0_MSG_DATA 0xd00c2008 #define cfgRCC_DEV0_EPF0_VF1_GFXMSIX_VECT0_CONTROL 0xd00c200c #define cfgRCC_DEV0_EPF0_VF1_GFXMSIX_VECT1_ADDR_LO 0xd00c2010 #define cfgRCC_DEV0_EPF0_VF1_GFXMSIX_VECT1_ADDR_HI 0xd00c2014 #define cfgRCC_DEV0_EPF0_VF1_GFXMSIX_VECT1_MSG_DATA 0xd00c2018 #define cfgRCC_DEV0_EPF0_VF1_GFXMSIX_VECT1_CONTROL 0xd00c201c #define cfgRCC_DEV0_EPF0_VF1_GFXMSIX_VECT2_ADDR_LO 0xd00c2020 #define cfgRCC_DEV0_EPF0_VF1_GFXMSIX_VECT2_ADDR_HI 0xd00c2024 #define cfgRCC_DEV0_EPF0_VF1_GFXMSIX_VECT2_MSG_DATA 0xd00c2028 #define cfgRCC_DEV0_EPF0_VF1_GFXMSIX_VECT2_CONTROL 0xd00c202c #define cfgRCC_DEV0_EPF0_VF1_GFXMSIX_VECT3_ADDR_LO 0xd00c2030 #define cfgRCC_DEV0_EPF0_VF1_GFXMSIX_VECT3_ADDR_HI 0xd00c2034 #define cfgRCC_DEV0_EPF0_VF1_GFXMSIX_VECT3_MSG_DATA 0xd00c2038 #define cfgRCC_DEV0_EPF0_VF1_GFXMSIX_VECT3_CONTROL 0xd00c203c #define cfgRCC_DEV0_EPF0_VF1_GFXMSIX_PBA 0xd00c3000 // addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf2_SYSPFVFDEC // base address: 0xd0100000 #define cfgBIF_BX_DEV0_EPF0_VF2_MM_INDEX 0xd0100000 #define cfgBIF_BX_DEV0_EPF0_VF2_MM_DATA 0xd0100004 #define cfgBIF_BX_DEV0_EPF0_VF2_MM_INDEX_HI 0xd0100018 // addressBlock: nbio_nbif0_rcc_dev0_epf0_vf2_BIFPFVFDEC1 // base address: 0xd0100000 #define cfgRCC_DEV0_EPF0_VF2_RCC_ERR_LOG 0xd0103694 #define cfgRCC_DEV0_EPF0_VF2_RCC_DOORBELL_APER_EN 0xd0103780 #define cfgRCC_DEV0_EPF0_VF2_RCC_CONFIG_MEMSIZE 0xd010378c #define cfgRCC_DEV0_EPF0_VF2_RCC_CONFIG_RESERVED 0xd0103790 #define cfgRCC_DEV0_EPF0_VF2_RCC_IOV_FUNC_IDENTIFIER 0xd0103794 // addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf2_BIFPFVFDEC1 // base address: 0xd0100000 #define cfgBIF_BX_DEV0_EPF0_VF2_BIF_BME_STATUS 0xd010382c #define cfgBIF_BX_DEV0_EPF0_VF2_BIF_ATOMIC_ERR_LOG 0xd0103830 #define cfgBIF_BX_DEV0_EPF0_VF2_DOORBELL_SELFRING_GPA_APER_BASE_HIGH 0xd010384c #define cfgBIF_BX_DEV0_EPF0_VF2_DOORBELL_SELFRING_GPA_APER_BASE_LOW 0xd0103850 #define cfgBIF_BX_DEV0_EPF0_VF2_DOORBELL_SELFRING_GPA_APER_CNTL 0xd0103854 #define cfgBIF_BX_DEV0_EPF0_VF2_HDP_REG_COHERENCY_FLUSH_CNTL 0xd0103858 #define cfgBIF_BX_DEV0_EPF0_VF2_HDP_MEM_COHERENCY_FLUSH_CNTL 0xd010385c #define cfgBIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_REQ 0xd0103898 #define cfgBIF_BX_DEV0_EPF0_VF2_GPU_HDP_FLUSH_DONE 0xd010389c #define cfgBIF_BX_DEV0_EPF0_VF2_BIF_TRANS_PENDING 0xd01038a0 #define cfgBIF_BX_DEV0_EPF0_VF2_NBIF_GFX_ADDR_LUT_BYPASS 0xd01038c8 #define cfgBIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_TRN_DW0 0xd0103958 #define cfgBIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_TRN_DW1 0xd010395c #define cfgBIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_TRN_DW2 0xd0103960 #define cfgBIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_TRN_DW3 0xd0103964 #define cfgBIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_RCV_DW0 0xd0103968 #define cfgBIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_RCV_DW1 0xd010396c #define cfgBIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_RCV_DW2 0xd0103970 #define cfgBIF_BX_DEV0_EPF0_VF2_MAILBOX_MSGBUF_RCV_DW3 0xd0103974 #define cfgBIF_BX_DEV0_EPF0_VF2_MAILBOX_CONTROL 0xd0103978 #define cfgBIF_BX_DEV0_EPF0_VF2_MAILBOX_INT_CNTL 0xd010397c #define cfgBIF_BX_DEV0_EPF0_VF2_BIF_VMHV_MAILBOX 0xd0103980 // addressBlock: nbio_nbif0_rcc_dev0_epf0_vf2_BIFDEC2 // base address: 0xd0100000 #define cfgRCC_DEV0_EPF0_VF2_GFXMSIX_VECT0_ADDR_LO 0xd0142000 #define cfgRCC_DEV0_EPF0_VF2_GFXMSIX_VECT0_ADDR_HI 0xd0142004 #define cfgRCC_DEV0_EPF0_VF2_GFXMSIX_VECT0_MSG_DATA 0xd0142008 #define cfgRCC_DEV0_EPF0_VF2_GFXMSIX_VECT0_CONTROL 0xd014200c #define cfgRCC_DEV0_EPF0_VF2_GFXMSIX_VECT1_ADDR_LO 0xd0142010 #define cfgRCC_DEV0_EPF0_VF2_GFXMSIX_VECT1_ADDR_HI 0xd0142014 #define cfgRCC_DEV0_EPF0_VF2_GFXMSIX_VECT1_MSG_DATA 0xd0142018 #define cfgRCC_DEV0_EPF0_VF2_GFXMSIX_VECT1_CONTROL 0xd014201c #define cfgRCC_DEV0_EPF0_VF2_GFXMSIX_VECT2_ADDR_LO 0xd0142020 #define cfgRCC_DEV0_EPF0_VF2_GFXMSIX_VECT2_ADDR_HI 0xd0142024 #define cfgRCC_DEV0_EPF0_VF2_GFXMSIX_VECT2_MSG_DATA 0xd0142028 #define cfgRCC_DEV0_EPF0_VF2_GFXMSIX_VECT2_CONTROL 0xd014202c #define cfgRCC_DEV0_EPF0_VF2_GFXMSIX_VECT3_ADDR_LO 0xd0142030 #define cfgRCC_DEV0_EPF0_VF2_GFXMSIX_VECT3_ADDR_HI 0xd0142034 #define cfgRCC_DEV0_EPF0_VF2_GFXMSIX_VECT3_MSG_DATA 0xd0142038 #define cfgRCC_DEV0_EPF0_VF2_GFXMSIX_VECT3_CONTROL 0xd014203c #define cfgRCC_DEV0_EPF0_VF2_GFXMSIX_PBA 0xd0143000 // addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf3_SYSPFVFDEC // base address: 0xd0180000 #define cfgBIF_BX_DEV0_EPF0_VF3_MM_INDEX 0xd0180000 #define cfgBIF_BX_DEV0_EPF0_VF3_MM_DATA 0xd0180004 #define cfgBIF_BX_DEV0_EPF0_VF3_MM_INDEX_HI 0xd0180018 // addressBlock: nbio_nbif0_rcc_dev0_epf0_vf3_BIFPFVFDEC1 // base address: 0xd0180000 #define cfgRCC_DEV0_EPF0_VF3_RCC_ERR_LOG 0xd0183694 #define cfgRCC_DEV0_EPF0_VF3_RCC_DOORBELL_APER_EN 0xd0183780 #define cfgRCC_DEV0_EPF0_VF3_RCC_CONFIG_MEMSIZE 0xd018378c #define cfgRCC_DEV0_EPF0_VF3_RCC_CONFIG_RESERVED 0xd0183790 #define cfgRCC_DEV0_EPF0_VF3_RCC_IOV_FUNC_IDENTIFIER 0xd0183794 // addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf3_BIFPFVFDEC1 // base address: 0xd0180000 #define cfgBIF_BX_DEV0_EPF0_VF3_BIF_BME_STATUS 0xd018382c #define cfgBIF_BX_DEV0_EPF0_VF3_BIF_ATOMIC_ERR_LOG 0xd0183830 #define cfgBIF_BX_DEV0_EPF0_VF3_DOORBELL_SELFRING_GPA_APER_BASE_HIGH 0xd018384c #define cfgBIF_BX_DEV0_EPF0_VF3_DOORBELL_SELFRING_GPA_APER_BASE_LOW 0xd0183850 #define cfgBIF_BX_DEV0_EPF0_VF3_DOORBELL_SELFRING_GPA_APER_CNTL 0xd0183854 #define cfgBIF_BX_DEV0_EPF0_VF3_HDP_REG_COHERENCY_FLUSH_CNTL 0xd0183858 #define cfgBIF_BX_DEV0_EPF0_VF3_HDP_MEM_COHERENCY_FLUSH_CNTL 0xd018385c #define cfgBIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_REQ 0xd0183898 #define cfgBIF_BX_DEV0_EPF0_VF3_GPU_HDP_FLUSH_DONE 0xd018389c #define cfgBIF_BX_DEV0_EPF0_VF3_BIF_TRANS_PENDING 0xd01838a0 #define cfgBIF_BX_DEV0_EPF0_VF3_NBIF_GFX_ADDR_LUT_BYPASS 0xd01838c8 #define cfgBIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_TRN_DW0 0xd0183958 #define cfgBIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_TRN_DW1 0xd018395c #define cfgBIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_TRN_DW2 0xd0183960 #define cfgBIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_TRN_DW3 0xd0183964 #define cfgBIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_RCV_DW0 0xd0183968 #define cfgBIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_RCV_DW1 0xd018396c #define cfgBIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_RCV_DW2 0xd0183970 #define cfgBIF_BX_DEV0_EPF0_VF3_MAILBOX_MSGBUF_RCV_DW3 0xd0183974 #define cfgBIF_BX_DEV0_EPF0_VF3_MAILBOX_CONTROL 0xd0183978 #define cfgBIF_BX_DEV0_EPF0_VF3_MAILBOX_INT_CNTL 0xd018397c #define cfgBIF_BX_DEV0_EPF0_VF3_BIF_VMHV_MAILBOX 0xd0183980 // addressBlock: nbio_nbif0_rcc_dev0_epf0_vf3_BIFDEC2 // base address: 0xd0180000 #define cfgRCC_DEV0_EPF0_VF3_GFXMSIX_VECT0_ADDR_LO 0xd01c2000 #define cfgRCC_DEV0_EPF0_VF3_GFXMSIX_VECT0_ADDR_HI 0xd01c2004 #define cfgRCC_DEV0_EPF0_VF3_GFXMSIX_VECT0_MSG_DATA 0xd01c2008 #define cfgRCC_DEV0_EPF0_VF3_GFXMSIX_VECT0_CONTROL 0xd01c200c #define cfgRCC_DEV0_EPF0_VF3_GFXMSIX_VECT1_ADDR_LO 0xd01c2010 #define cfgRCC_DEV0_EPF0_VF3_GFXMSIX_VECT1_ADDR_HI 0xd01c2014 #define cfgRCC_DEV0_EPF0_VF3_GFXMSIX_VECT1_MSG_DATA 0xd01c2018 #define cfgRCC_DEV0_EPF0_VF3_GFXMSIX_VECT1_CONTROL 0xd01c201c #define cfgRCC_DEV0_EPF0_VF3_GFXMSIX_VECT2_ADDR_LO 0xd01c2020 #define cfgRCC_DEV0_EPF0_VF3_GFXMSIX_VECT2_ADDR_HI 0xd01c2024 #define cfgRCC_DEV0_EPF0_VF3_GFXMSIX_VECT2_MSG_DATA 0xd01c2028 #define cfgRCC_DEV0_EPF0_VF3_GFXMSIX_VECT2_CONTROL 0xd01c202c #define cfgRCC_DEV0_EPF0_VF3_GFXMSIX_VECT3_ADDR_LO 0xd01c2030 #define cfgRCC_DEV0_EPF0_VF3_GFXMSIX_VECT3_ADDR_HI 0xd01c2034 #define cfgRCC_DEV0_EPF0_VF3_GFXMSIX_VECT3_MSG_DATA 0xd01c2038 #define cfgRCC_DEV0_EPF0_VF3_GFXMSIX_VECT3_CONTROL 0xd01c203c #define cfgRCC_DEV0_EPF0_VF3_GFXMSIX_PBA 0xd01c3000 // addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf4_SYSPFVFDEC // base address: 0xd0200000 #define cfgBIF_BX_DEV0_EPF0_VF4_MM_INDEX 0xd0200000 #define cfgBIF_BX_DEV0_EPF0_VF4_MM_DATA 0xd0200004 #define cfgBIF_BX_DEV0_EPF0_VF4_MM_INDEX_HI 0xd0200018 // addressBlock: nbio_nbif0_rcc_dev0_epf0_vf4_BIFPFVFDEC1 // base address: 0xd0200000 #define cfgRCC_DEV0_EPF0_VF4_RCC_ERR_LOG 0xd0203694 #define cfgRCC_DEV0_EPF0_VF4_RCC_DOORBELL_APER_EN 0xd0203780 #define cfgRCC_DEV0_EPF0_VF4_RCC_CONFIG_MEMSIZE 0xd020378c #define cfgRCC_DEV0_EPF0_VF4_RCC_CONFIG_RESERVED 0xd0203790 #define cfgRCC_DEV0_EPF0_VF4_RCC_IOV_FUNC_IDENTIFIER 0xd0203794 // addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf4_BIFPFVFDEC1 // base address: 0xd0200000 #define cfgBIF_BX_DEV0_EPF0_VF4_BIF_BME_STATUS 0xd020382c #define cfgBIF_BX_DEV0_EPF0_VF4_BIF_ATOMIC_ERR_LOG 0xd0203830 #define cfgBIF_BX_DEV0_EPF0_VF4_DOORBELL_SELFRING_GPA_APER_BASE_HIGH 0xd020384c #define cfgBIF_BX_DEV0_EPF0_VF4_DOORBELL_SELFRING_GPA_APER_BASE_LOW 0xd0203850 #define cfgBIF_BX_DEV0_EPF0_VF4_DOORBELL_SELFRING_GPA_APER_CNTL 0xd0203854 #define cfgBIF_BX_DEV0_EPF0_VF4_HDP_REG_COHERENCY_FLUSH_CNTL 0xd0203858 #define cfgBIF_BX_DEV0_EPF0_VF4_HDP_MEM_COHERENCY_FLUSH_CNTL 0xd020385c #define cfgBIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_REQ 0xd0203898 #define cfgBIF_BX_DEV0_EPF0_VF4_GPU_HDP_FLUSH_DONE 0xd020389c #define cfgBIF_BX_DEV0_EPF0_VF4_BIF_TRANS_PENDING 0xd02038a0 #define cfgBIF_BX_DEV0_EPF0_VF4_NBIF_GFX_ADDR_LUT_BYPASS 0xd02038c8 #define cfgBIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_TRN_DW0 0xd0203958 #define cfgBIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_TRN_DW1 0xd020395c #define cfgBIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_TRN_DW2 0xd0203960 #define cfgBIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_TRN_DW3 0xd0203964 #define cfgBIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_RCV_DW0 0xd0203968 #define cfgBIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_RCV_DW1 0xd020396c #define cfgBIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_RCV_DW2 0xd0203970 #define cfgBIF_BX_DEV0_EPF0_VF4_MAILBOX_MSGBUF_RCV_DW3 0xd0203974 #define cfgBIF_BX_DEV0_EPF0_VF4_MAILBOX_CONTROL 0xd0203978 #define cfgBIF_BX_DEV0_EPF0_VF4_MAILBOX_INT_CNTL 0xd020397c #define cfgBIF_BX_DEV0_EPF0_VF4_BIF_VMHV_MAILBOX 0xd0203980 // addressBlock: nbio_nbif0_rcc_dev0_epf0_vf4_BIFDEC2 // base address: 0xd0200000 #define cfgRCC_DEV0_EPF0_VF4_GFXMSIX_VECT0_ADDR_LO 0xd0242000 #define cfgRCC_DEV0_EPF0_VF4_GFXMSIX_VECT0_ADDR_HI 0xd0242004 #define cfgRCC_DEV0_EPF0_VF4_GFXMSIX_VECT0_MSG_DATA 0xd0242008 #define cfgRCC_DEV0_EPF0_VF4_GFXMSIX_VECT0_CONTROL 0xd024200c #define cfgRCC_DEV0_EPF0_VF4_GFXMSIX_VECT1_ADDR_LO 0xd0242010 #define cfgRCC_DEV0_EPF0_VF4_GFXMSIX_VECT1_ADDR_HI 0xd0242014 #define cfgRCC_DEV0_EPF0_VF4_GFXMSIX_VECT1_MSG_DATA 0xd0242018 #define cfgRCC_DEV0_EPF0_VF4_GFXMSIX_VECT1_CONTROL 0xd024201c #define cfgRCC_DEV0_EPF0_VF4_GFXMSIX_VECT2_ADDR_LO 0xd0242020 #define cfgRCC_DEV0_EPF0_VF4_GFXMSIX_VECT2_ADDR_HI 0xd0242024 #define cfgRCC_DEV0_EPF0_VF4_GFXMSIX_VECT2_MSG_DATA 0xd0242028 #define cfgRCC_DEV0_EPF0_VF4_GFXMSIX_VECT2_CONTROL 0xd024202c #define cfgRCC_DEV0_EPF0_VF4_GFXMSIX_VECT3_ADDR_LO 0xd0242030 #define cfgRCC_DEV0_EPF0_VF4_GFXMSIX_VECT3_ADDR_HI 0xd0242034 #define cfgRCC_DEV0_EPF0_VF4_GFXMSIX_VECT3_MSG_DATA 0xd0242038 #define cfgRCC_DEV0_EPF0_VF4_GFXMSIX_VECT3_CONTROL 0xd024203c #define cfgRCC_DEV0_EPF0_VF4_GFXMSIX_PBA 0xd0243000 // addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf5_SYSPFVFDEC // base address: 0xd0280000 #define cfgBIF_BX_DEV0_EPF0_VF5_MM_INDEX 0xd0280000 #define cfgBIF_BX_DEV0_EPF0_VF5_MM_DATA 0xd0280004 #define cfgBIF_BX_DEV0_EPF0_VF5_MM_INDEX_HI 0xd0280018 // addressBlock: nbio_nbif0_rcc_dev0_epf0_vf5_BIFPFVFDEC1 // base address: 0xd0280000 #define cfgRCC_DEV0_EPF0_VF5_RCC_ERR_LOG 0xd0283694 #define cfgRCC_DEV0_EPF0_VF5_RCC_DOORBELL_APER_EN 0xd0283780 #define cfgRCC_DEV0_EPF0_VF5_RCC_CONFIG_MEMSIZE 0xd028378c #define cfgRCC_DEV0_EPF0_VF5_RCC_CONFIG_RESERVED 0xd0283790 #define cfgRCC_DEV0_EPF0_VF5_RCC_IOV_FUNC_IDENTIFIER 0xd0283794 // addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf5_BIFPFVFDEC1 // base address: 0xd0280000 #define cfgBIF_BX_DEV0_EPF0_VF5_BIF_BME_STATUS 0xd028382c #define cfgBIF_BX_DEV0_EPF0_VF5_BIF_ATOMIC_ERR_LOG 0xd0283830 #define cfgBIF_BX_DEV0_EPF0_VF5_DOORBELL_SELFRING_GPA_APER_BASE_HIGH 0xd028384c #define cfgBIF_BX_DEV0_EPF0_VF5_DOORBELL_SELFRING_GPA_APER_BASE_LOW 0xd0283850 #define cfgBIF_BX_DEV0_EPF0_VF5_DOORBELL_SELFRING_GPA_APER_CNTL 0xd0283854 #define cfgBIF_BX_DEV0_EPF0_VF5_HDP_REG_COHERENCY_FLUSH_CNTL 0xd0283858 #define cfgBIF_BX_DEV0_EPF0_VF5_HDP_MEM_COHERENCY_FLUSH_CNTL 0xd028385c #define cfgBIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_REQ 0xd0283898 #define cfgBIF_BX_DEV0_EPF0_VF5_GPU_HDP_FLUSH_DONE 0xd028389c #define cfgBIF_BX_DEV0_EPF0_VF5_BIF_TRANS_PENDING 0xd02838a0 #define cfgBIF_BX_DEV0_EPF0_VF5_NBIF_GFX_ADDR_LUT_BYPASS 0xd02838c8 #define cfgBIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_TRN_DW0 0xd0283958 #define cfgBIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_TRN_DW1 0xd028395c #define cfgBIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_TRN_DW2 0xd0283960 #define cfgBIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_TRN_DW3 0xd0283964 #define cfgBIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_RCV_DW0 0xd0283968 #define cfgBIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_RCV_DW1 0xd028396c #define cfgBIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_RCV_DW2 0xd0283970 #define cfgBIF_BX_DEV0_EPF0_VF5_MAILBOX_MSGBUF_RCV_DW3 0xd0283974 #define cfgBIF_BX_DEV0_EPF0_VF5_MAILBOX_CONTROL 0xd0283978 #define cfgBIF_BX_DEV0_EPF0_VF5_MAILBOX_INT_CNTL 0xd028397c #define cfgBIF_BX_DEV0_EPF0_VF5_BIF_VMHV_MAILBOX 0xd0283980 // addressBlock: nbio_nbif0_rcc_dev0_epf0_vf5_BIFDEC2 // base address: 0xd0280000 #define cfgRCC_DEV0_EPF0_VF5_GFXMSIX_VECT0_ADDR_LO 0xd02c2000 #define cfgRCC_DEV0_EPF0_VF5_GFXMSIX_VECT0_ADDR_HI 0xd02c2004 #define cfgRCC_DEV0_EPF0_VF5_GFXMSIX_VECT0_MSG_DATA 0xd02c2008 #define cfgRCC_DEV0_EPF0_VF5_GFXMSIX_VECT0_CONTROL 0xd02c200c #define cfgRCC_DEV0_EPF0_VF5_GFXMSIX_VECT1_ADDR_LO 0xd02c2010 #define cfgRCC_DEV0_EPF0_VF5_GFXMSIX_VECT1_ADDR_HI 0xd02c2014 #define cfgRCC_DEV0_EPF0_VF5_GFXMSIX_VECT1_MSG_DATA 0xd02c2018 #define cfgRCC_DEV0_EPF0_VF5_GFXMSIX_VECT1_CONTROL 0xd02c201c #define cfgRCC_DEV0_EPF0_VF5_GFXMSIX_VECT2_ADDR_LO 0xd02c2020 #define cfgRCC_DEV0_EPF0_VF5_GFXMSIX_VECT2_ADDR_HI 0xd02c2024 #define cfgRCC_DEV0_EPF0_VF5_GFXMSIX_VECT2_MSG_DATA 0xd02c2028 #define cfgRCC_DEV0_EPF0_VF5_GFXMSIX_VECT2_CONTROL 0xd02c202c #define cfgRCC_DEV0_EPF0_VF5_GFXMSIX_VECT3_ADDR_LO 0xd02c2030 #define cfgRCC_DEV0_EPF0_VF5_GFXMSIX_VECT3_ADDR_HI 0xd02c2034 #define cfgRCC_DEV0_EPF0_VF5_GFXMSIX_VECT3_MSG_DATA 0xd02c2038 #define cfgRCC_DEV0_EPF0_VF5_GFXMSIX_VECT3_CONTROL 0xd02c203c #define cfgRCC_DEV0_EPF0_VF5_GFXMSIX_PBA 0xd02c3000 // addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf6_SYSPFVFDEC // base address: 0xd0300000 #define cfgBIF_BX_DEV0_EPF0_VF6_MM_INDEX 0xd0300000 #define cfgBIF_BX_DEV0_EPF0_VF6_MM_DATA 0xd0300004 #define cfgBIF_BX_DEV0_EPF0_VF6_MM_INDEX_HI 0xd0300018 // addressBlock: nbio_nbif0_rcc_dev0_epf0_vf6_BIFPFVFDEC1 // base address: 0xd0300000 #define cfgRCC_DEV0_EPF0_VF6_RCC_ERR_LOG 0xd0303694 #define cfgRCC_DEV0_EPF0_VF6_RCC_DOORBELL_APER_EN 0xd0303780 #define cfgRCC_DEV0_EPF0_VF6_RCC_CONFIG_MEMSIZE 0xd030378c #define cfgRCC_DEV0_EPF0_VF6_RCC_CONFIG_RESERVED 0xd0303790 #define cfgRCC_DEV0_EPF0_VF6_RCC_IOV_FUNC_IDENTIFIER 0xd0303794 // addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf6_BIFPFVFDEC1 // base address: 0xd0300000 #define cfgBIF_BX_DEV0_EPF0_VF6_BIF_BME_STATUS 0xd030382c #define cfgBIF_BX_DEV0_EPF0_VF6_BIF_ATOMIC_ERR_LOG 0xd0303830 #define cfgBIF_BX_DEV0_EPF0_VF6_DOORBELL_SELFRING_GPA_APER_BASE_HIGH 0xd030384c #define cfgBIF_BX_DEV0_EPF0_VF6_DOORBELL_SELFRING_GPA_APER_BASE_LOW 0xd0303850 #define cfgBIF_BX_DEV0_EPF0_VF6_DOORBELL_SELFRING_GPA_APER_CNTL 0xd0303854 #define cfgBIF_BX_DEV0_EPF0_VF6_HDP_REG_COHERENCY_FLUSH_CNTL 0xd0303858 #define cfgBIF_BX_DEV0_EPF0_VF6_HDP_MEM_COHERENCY_FLUSH_CNTL 0xd030385c #define cfgBIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_REQ 0xd0303898 #define cfgBIF_BX_DEV0_EPF0_VF6_GPU_HDP_FLUSH_DONE 0xd030389c #define cfgBIF_BX_DEV0_EPF0_VF6_BIF_TRANS_PENDING 0xd03038a0 #define cfgBIF_BX_DEV0_EPF0_VF6_NBIF_GFX_ADDR_LUT_BYPASS 0xd03038c8 #define cfgBIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_TRN_DW0 0xd0303958 #define cfgBIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_TRN_DW1 0xd030395c #define cfgBIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_TRN_DW2 0xd0303960 #define cfgBIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_TRN_DW3 0xd0303964 #define cfgBIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_RCV_DW0 0xd0303968 #define cfgBIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_RCV_DW1 0xd030396c #define cfgBIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_RCV_DW2 0xd0303970 #define cfgBIF_BX_DEV0_EPF0_VF6_MAILBOX_MSGBUF_RCV_DW3 0xd0303974 #define cfgBIF_BX_DEV0_EPF0_VF6_MAILBOX_CONTROL 0xd0303978 #define cfgBIF_BX_DEV0_EPF0_VF6_MAILBOX_INT_CNTL 0xd030397c #define cfgBIF_BX_DEV0_EPF0_VF6_BIF_VMHV_MAILBOX 0xd0303980 // addressBlock: nbio_nbif0_rcc_dev0_epf0_vf6_BIFDEC2 // base address: 0xd0300000 #define cfgRCC_DEV0_EPF0_VF6_GFXMSIX_VECT0_ADDR_LO 0xd0342000 #define cfgRCC_DEV0_EPF0_VF6_GFXMSIX_VECT0_ADDR_HI 0xd0342004 #define cfgRCC_DEV0_EPF0_VF6_GFXMSIX_VECT0_MSG_DATA 0xd0342008 #define cfgRCC_DEV0_EPF0_VF6_GFXMSIX_VECT0_CONTROL 0xd034200c #define cfgRCC_DEV0_EPF0_VF6_GFXMSIX_VECT1_ADDR_LO 0xd0342010 #define cfgRCC_DEV0_EPF0_VF6_GFXMSIX_VECT1_ADDR_HI 0xd0342014 #define cfgRCC_DEV0_EPF0_VF6_GFXMSIX_VECT1_MSG_DATA 0xd0342018 #define cfgRCC_DEV0_EPF0_VF6_GFXMSIX_VECT1_CONTROL 0xd034201c #define cfgRCC_DEV0_EPF0_VF6_GFXMSIX_VECT2_ADDR_LO 0xd0342020 #define cfgRCC_DEV0_EPF0_VF6_GFXMSIX_VECT2_ADDR_HI 0xd0342024 #define cfgRCC_DEV0_EPF0_VF6_GFXMSIX_VECT2_MSG_DATA 0xd0342028 #define cfgRCC_DEV0_EPF0_VF6_GFXMSIX_VECT2_CONTROL 0xd034202c #define cfgRCC_DEV0_EPF0_VF6_GFXMSIX_VECT3_ADDR_LO 0xd0342030 #define cfgRCC_DEV0_EPF0_VF6_GFXMSIX_VECT3_ADDR_HI 0xd0342034 #define cfgRCC_DEV0_EPF0_VF6_GFXMSIX_VECT3_MSG_DATA 0xd0342038 #define cfgRCC_DEV0_EPF0_VF6_GFXMSIX_VECT3_CONTROL 0xd034203c #define cfgRCC_DEV0_EPF0_VF6_GFXMSIX_PBA 0xd0343000 // addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf7_SYSPFVFDEC // base address: 0xd0380000 #define cfgBIF_BX_DEV0_EPF0_VF7_MM_INDEX 0xd0380000 #define cfgBIF_BX_DEV0_EPF0_VF7_MM_DATA 0xd0380004 #define cfgBIF_BX_DEV0_EPF0_VF7_MM_INDEX_HI 0xd0380018 // addressBlock: nbio_nbif0_rcc_dev0_epf0_vf7_BIFPFVFDEC1 // base address: 0xd0380000 #define cfgRCC_DEV0_EPF0_VF7_RCC_ERR_LOG 0xd0383694 #define cfgRCC_DEV0_EPF0_VF7_RCC_DOORBELL_APER_EN 0xd0383780 #define cfgRCC_DEV0_EPF0_VF7_RCC_CONFIG_MEMSIZE 0xd038378c #define cfgRCC_DEV0_EPF0_VF7_RCC_CONFIG_RESERVED 0xd0383790 #define cfgRCC_DEV0_EPF0_VF7_RCC_IOV_FUNC_IDENTIFIER 0xd0383794 // addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf7_BIFPFVFDEC1 // base address: 0xd0380000 #define cfgBIF_BX_DEV0_EPF0_VF7_BIF_BME_STATUS 0xd038382c #define cfgBIF_BX_DEV0_EPF0_VF7_BIF_ATOMIC_ERR_LOG 0xd0383830 #define cfgBIF_BX_DEV0_EPF0_VF7_DOORBELL_SELFRING_GPA_APER_BASE_HIGH 0xd038384c #define cfgBIF_BX_DEV0_EPF0_VF7_DOORBELL_SELFRING_GPA_APER_BASE_LOW 0xd0383850 #define cfgBIF_BX_DEV0_EPF0_VF7_DOORBELL_SELFRING_GPA_APER_CNTL 0xd0383854 #define cfgBIF_BX_DEV0_EPF0_VF7_HDP_REG_COHERENCY_FLUSH_CNTL 0xd0383858 #define cfgBIF_BX_DEV0_EPF0_VF7_HDP_MEM_COHERENCY_FLUSH_CNTL 0xd038385c #define cfgBIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_REQ 0xd0383898 #define cfgBIF_BX_DEV0_EPF0_VF7_GPU_HDP_FLUSH_DONE 0xd038389c #define cfgBIF_BX_DEV0_EPF0_VF7_BIF_TRANS_PENDING 0xd03838a0 #define cfgBIF_BX_DEV0_EPF0_VF7_NBIF_GFX_ADDR_LUT_BYPASS 0xd03838c8 #define cfgBIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_TRN_DW0 0xd0383958 #define cfgBIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_TRN_DW1 0xd038395c #define cfgBIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_TRN_DW2 0xd0383960 #define cfgBIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_TRN_DW3 0xd0383964 #define cfgBIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_RCV_DW0 0xd0383968 #define cfgBIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_RCV_DW1 0xd038396c #define cfgBIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_RCV_DW2 0xd0383970 #define cfgBIF_BX_DEV0_EPF0_VF7_MAILBOX_MSGBUF_RCV_DW3 0xd0383974 #define cfgBIF_BX_DEV0_EPF0_VF7_MAILBOX_CONTROL 0xd0383978 #define cfgBIF_BX_DEV0_EPF0_VF7_MAILBOX_INT_CNTL 0xd038397c #define cfgBIF_BX_DEV0_EPF0_VF7_BIF_VMHV_MAILBOX 0xd0383980 // addressBlock: nbio_nbif0_rcc_dev0_epf0_vf7_BIFDEC2 // base address: 0xd0380000 #define cfgRCC_DEV0_EPF0_VF7_GFXMSIX_VECT0_ADDR_LO 0xd03c2000 #define cfgRCC_DEV0_EPF0_VF7_GFXMSIX_VECT0_ADDR_HI 0xd03c2004 #define cfgRCC_DEV0_EPF0_VF7_GFXMSIX_VECT0_MSG_DATA 0xd03c2008 #define cfgRCC_DEV0_EPF0_VF7_GFXMSIX_VECT0_CONTROL 0xd03c200c #define cfgRCC_DEV0_EPF0_VF7_GFXMSIX_VECT1_ADDR_LO 0xd03c2010 #define cfgRCC_DEV0_EPF0_VF7_GFXMSIX_VECT1_ADDR_HI 0xd03c2014 #define cfgRCC_DEV0_EPF0_VF7_GFXMSIX_VECT1_MSG_DATA 0xd03c2018 #define cfgRCC_DEV0_EPF0_VF7_GFXMSIX_VECT1_CONTROL 0xd03c201c #define cfgRCC_DEV0_EPF0_VF7_GFXMSIX_VECT2_ADDR_LO 0xd03c2020 #define cfgRCC_DEV0_EPF0_VF7_GFXMSIX_VECT2_ADDR_HI 0xd03c2024 #define cfgRCC_DEV0_EPF0_VF7_GFXMSIX_VECT2_MSG_DATA 0xd03c2028 #define cfgRCC_DEV0_EPF0_VF7_GFXMSIX_VECT2_CONTROL 0xd03c202c #define cfgRCC_DEV0_EPF0_VF7_GFXMSIX_VECT3_ADDR_LO 0xd03c2030 #define cfgRCC_DEV0_EPF0_VF7_GFXMSIX_VECT3_ADDR_HI 0xd03c2034 #define cfgRCC_DEV0_EPF0_VF7_GFXMSIX_VECT3_MSG_DATA 0xd03c2038 #define cfgRCC_DEV0_EPF0_VF7_GFXMSIX_VECT3_CONTROL 0xd03c203c #define cfgRCC_DEV0_EPF0_VF7_GFXMSIX_PBA 0xd03c3000 // addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf8_SYSPFVFDEC // base address: 0xd0400000 #define cfgBIF_BX_DEV0_EPF0_VF8_MM_INDEX 0xd0400000 #define cfgBIF_BX_DEV0_EPF0_VF8_MM_DATA 0xd0400004 #define cfgBIF_BX_DEV0_EPF0_VF8_MM_INDEX_HI 0xd0400018 // addressBlock: nbio_nbif0_rcc_dev0_epf0_vf8_BIFPFVFDEC1 // base address: 0xd0400000 #define cfgRCC_DEV0_EPF0_VF8_RCC_ERR_LOG 0xd0403694 #define cfgRCC_DEV0_EPF0_VF8_RCC_DOORBELL_APER_EN 0xd0403780 #define cfgRCC_DEV0_EPF0_VF8_RCC_CONFIG_MEMSIZE 0xd040378c #define cfgRCC_DEV0_EPF0_VF8_RCC_CONFIG_RESERVED 0xd0403790 #define cfgRCC_DEV0_EPF0_VF8_RCC_IOV_FUNC_IDENTIFIER 0xd0403794 // addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf8_BIFPFVFDEC1 // base address: 0xd0400000 #define cfgBIF_BX_DEV0_EPF0_VF8_BIF_BME_STATUS 0xd040382c #define cfgBIF_BX_DEV0_EPF0_VF8_BIF_ATOMIC_ERR_LOG 0xd0403830 #define cfgBIF_BX_DEV0_EPF0_VF8_DOORBELL_SELFRING_GPA_APER_BASE_HIGH 0xd040384c #define cfgBIF_BX_DEV0_EPF0_VF8_DOORBELL_SELFRING_GPA_APER_BASE_LOW 0xd0403850 #define cfgBIF_BX_DEV0_EPF0_VF8_DOORBELL_SELFRING_GPA_APER_CNTL 0xd0403854 #define cfgBIF_BX_DEV0_EPF0_VF8_HDP_REG_COHERENCY_FLUSH_CNTL 0xd0403858 #define cfgBIF_BX_DEV0_EPF0_VF8_HDP_MEM_COHERENCY_FLUSH_CNTL 0xd040385c #define cfgBIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_REQ 0xd0403898 #define cfgBIF_BX_DEV0_EPF0_VF8_GPU_HDP_FLUSH_DONE 0xd040389c #define cfgBIF_BX_DEV0_EPF0_VF8_BIF_TRANS_PENDING 0xd04038a0 #define cfgBIF_BX_DEV0_EPF0_VF8_NBIF_GFX_ADDR_LUT_BYPASS 0xd04038c8 #define cfgBIF_BX_DEV0_EPF0_VF8_MAILBOX_MSGBUF_TRN_DW0 0xd0403958 #define cfgBIF_BX_DEV0_EPF0_VF8_MAILBOX_MSGBUF_TRN_DW1 0xd040395c #define cfgBIF_BX_DEV0_EPF0_VF8_MAILBOX_MSGBUF_TRN_DW2 0xd0403960 #define cfgBIF_BX_DEV0_EPF0_VF8_MAILBOX_MSGBUF_TRN_DW3 0xd0403964 #define cfgBIF_BX_DEV0_EPF0_VF8_MAILBOX_MSGBUF_RCV_DW0 0xd0403968 #define cfgBIF_BX_DEV0_EPF0_VF8_MAILBOX_MSGBUF_RCV_DW1 0xd040396c #define cfgBIF_BX_DEV0_EPF0_VF8_MAILBOX_MSGBUF_RCV_DW2 0xd0403970 #define cfgBIF_BX_DEV0_EPF0_VF8_MAILBOX_MSGBUF_RCV_DW3 0xd0403974 #define cfgBIF_BX_DEV0_EPF0_VF8_MAILBOX_CONTROL 0xd0403978 #define cfgBIF_BX_DEV0_EPF0_VF8_MAILBOX_INT_CNTL 0xd040397c #define cfgBIF_BX_DEV0_EPF0_VF8_BIF_VMHV_MAILBOX 0xd0403980 // addressBlock: nbio_nbif0_rcc_dev0_epf0_vf8_BIFDEC2 // base address: 0xd0400000 #define cfgRCC_DEV0_EPF0_VF8_GFXMSIX_VECT0_ADDR_LO 0xd0442000 #define cfgRCC_DEV0_EPF0_VF8_GFXMSIX_VECT0_ADDR_HI 0xd0442004 #define cfgRCC_DEV0_EPF0_VF8_GFXMSIX_VECT0_MSG_DATA 0xd0442008 #define cfgRCC_DEV0_EPF0_VF8_GFXMSIX_VECT0_CONTROL 0xd044200c #define cfgRCC_DEV0_EPF0_VF8_GFXMSIX_VECT1_ADDR_LO 0xd0442010 #define cfgRCC_DEV0_EPF0_VF8_GFXMSIX_VECT1_ADDR_HI 0xd0442014 #define cfgRCC_DEV0_EPF0_VF8_GFXMSIX_VECT1_MSG_DATA 0xd0442018 #define cfgRCC_DEV0_EPF0_VF8_GFXMSIX_VECT1_CONTROL 0xd044201c #define cfgRCC_DEV0_EPF0_VF8_GFXMSIX_VECT2_ADDR_LO 0xd0442020 #define cfgRCC_DEV0_EPF0_VF8_GFXMSIX_VECT2_ADDR_HI 0xd0442024 #define cfgRCC_DEV0_EPF0_VF8_GFXMSIX_VECT2_MSG_DATA 0xd0442028 #define cfgRCC_DEV0_EPF0_VF8_GFXMSIX_VECT2_CONTROL 0xd044202c #define cfgRCC_DEV0_EPF0_VF8_GFXMSIX_VECT3_ADDR_LO 0xd0442030 #define cfgRCC_DEV0_EPF0_VF8_GFXMSIX_VECT3_ADDR_HI 0xd0442034 #define cfgRCC_DEV0_EPF0_VF8_GFXMSIX_VECT3_MSG_DATA 0xd0442038 #define cfgRCC_DEV0_EPF0_VF8_GFXMSIX_VECT3_CONTROL 0xd044203c #define cfgRCC_DEV0_EPF0_VF8_GFXMSIX_PBA 0xd0443000 // addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf9_SYSPFVFDEC // base address: 0xd0480000 #define cfgBIF_BX_DEV0_EPF0_VF9_MM_INDEX 0xd0480000 #define cfgBIF_BX_DEV0_EPF0_VF9_MM_DATA 0xd0480004 #define cfgBIF_BX_DEV0_EPF0_VF9_MM_INDEX_HI 0xd0480018 // addressBlock: nbio_nbif0_rcc_dev0_epf0_vf9_BIFPFVFDEC1 // base address: 0xd0480000 #define cfgRCC_DEV0_EPF0_VF9_RCC_ERR_LOG 0xd0483694 #define cfgRCC_DEV0_EPF0_VF9_RCC_DOORBELL_APER_EN 0xd0483780 #define cfgRCC_DEV0_EPF0_VF9_RCC_CONFIG_MEMSIZE 0xd048378c #define cfgRCC_DEV0_EPF0_VF9_RCC_CONFIG_RESERVED 0xd0483790 #define cfgRCC_DEV0_EPF0_VF9_RCC_IOV_FUNC_IDENTIFIER 0xd0483794 // addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf9_BIFPFVFDEC1 // base address: 0xd0480000 #define cfgBIF_BX_DEV0_EPF0_VF9_BIF_BME_STATUS 0xd048382c #define cfgBIF_BX_DEV0_EPF0_VF9_BIF_ATOMIC_ERR_LOG 0xd0483830 #define cfgBIF_BX_DEV0_EPF0_VF9_DOORBELL_SELFRING_GPA_APER_BASE_HIGH 0xd048384c #define cfgBIF_BX_DEV0_EPF0_VF9_DOORBELL_SELFRING_GPA_APER_BASE_LOW 0xd0483850 #define cfgBIF_BX_DEV0_EPF0_VF9_DOORBELL_SELFRING_GPA_APER_CNTL 0xd0483854 #define cfgBIF_BX_DEV0_EPF0_VF9_HDP_REG_COHERENCY_FLUSH_CNTL 0xd0483858 #define cfgBIF_BX_DEV0_EPF0_VF9_HDP_MEM_COHERENCY_FLUSH_CNTL 0xd048385c #define cfgBIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_REQ 0xd0483898 #define cfgBIF_BX_DEV0_EPF0_VF9_GPU_HDP_FLUSH_DONE 0xd048389c #define cfgBIF_BX_DEV0_EPF0_VF9_BIF_TRANS_PENDING 0xd04838a0 #define cfgBIF_BX_DEV0_EPF0_VF9_NBIF_GFX_ADDR_LUT_BYPASS 0xd04838c8 #define cfgBIF_BX_DEV0_EPF0_VF9_MAILBOX_MSGBUF_TRN_DW0 0xd0483958 #define cfgBIF_BX_DEV0_EPF0_VF9_MAILBOX_MSGBUF_TRN_DW1 0xd048395c #define cfgBIF_BX_DEV0_EPF0_VF9_MAILBOX_MSGBUF_TRN_DW2 0xd0483960 #define cfgBIF_BX_DEV0_EPF0_VF9_MAILBOX_MSGBUF_TRN_DW3 0xd0483964 #define cfgBIF_BX_DEV0_EPF0_VF9_MAILBOX_MSGBUF_RCV_DW0 0xd0483968 #define cfgBIF_BX_DEV0_EPF0_VF9_MAILBOX_MSGBUF_RCV_DW1 0xd048396c #define cfgBIF_BX_DEV0_EPF0_VF9_MAILBOX_MSGBUF_RCV_DW2 0xd0483970 #define cfgBIF_BX_DEV0_EPF0_VF9_MAILBOX_MSGBUF_RCV_DW3 0xd0483974 #define cfgBIF_BX_DEV0_EPF0_VF9_MAILBOX_CONTROL 0xd0483978 #define cfgBIF_BX_DEV0_EPF0_VF9_MAILBOX_INT_CNTL 0xd048397c #define cfgBIF_BX_DEV0_EPF0_VF9_BIF_VMHV_MAILBOX 0xd0483980 // addressBlock: nbio_nbif0_rcc_dev0_epf0_vf9_BIFDEC2 // base address: 0xd0480000 #define cfgRCC_DEV0_EPF0_VF9_GFXMSIX_VECT0_ADDR_LO 0xd04c2000 #define cfgRCC_DEV0_EPF0_VF9_GFXMSIX_VECT0_ADDR_HI 0xd04c2004 #define cfgRCC_DEV0_EPF0_VF9_GFXMSIX_VECT0_MSG_DATA 0xd04c2008 #define cfgRCC_DEV0_EPF0_VF9_GFXMSIX_VECT0_CONTROL 0xd04c200c #define cfgRCC_DEV0_EPF0_VF9_GFXMSIX_VECT1_ADDR_LO 0xd04c2010 #define cfgRCC_DEV0_EPF0_VF9_GFXMSIX_VECT1_ADDR_HI 0xd04c2014 #define cfgRCC_DEV0_EPF0_VF9_GFXMSIX_VECT1_MSG_DATA 0xd04c2018 #define cfgRCC_DEV0_EPF0_VF9_GFXMSIX_VECT1_CONTROL 0xd04c201c #define cfgRCC_DEV0_EPF0_VF9_GFXMSIX_VECT2_ADDR_LO 0xd04c2020 #define cfgRCC_DEV0_EPF0_VF9_GFXMSIX_VECT2_ADDR_HI 0xd04c2024 #define cfgRCC_DEV0_EPF0_VF9_GFXMSIX_VECT2_MSG_DATA 0xd04c2028 #define cfgRCC_DEV0_EPF0_VF9_GFXMSIX_VECT2_CONTROL 0xd04c202c #define cfgRCC_DEV0_EPF0_VF9_GFXMSIX_VECT3_ADDR_LO 0xd04c2030 #define cfgRCC_DEV0_EPF0_VF9_GFXMSIX_VECT3_ADDR_HI 0xd04c2034 #define cfgRCC_DEV0_EPF0_VF9_GFXMSIX_VECT3_MSG_DATA 0xd04c2038 #define cfgRCC_DEV0_EPF0_VF9_GFXMSIX_VECT3_CONTROL 0xd04c203c #define cfgRCC_DEV0_EPF0_VF9_GFXMSIX_PBA 0xd04c3000 // addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf10_SYSPFVFDEC // base address: 0xd0500000 #define cfgBIF_BX_DEV0_EPF0_VF10_MM_INDEX 0xd0500000 #define cfgBIF_BX_DEV0_EPF0_VF10_MM_DATA 0xd0500004 #define cfgBIF_BX_DEV0_EPF0_VF10_MM_INDEX_HI 0xd0500018 // addressBlock: nbio_nbif0_rcc_dev0_epf0_vf10_BIFPFVFDEC1 // base address: 0xd0500000 #define cfgRCC_DEV0_EPF0_VF10_RCC_ERR_LOG 0xd0503694 #define cfgRCC_DEV0_EPF0_VF10_RCC_DOORBELL_APER_EN 0xd0503780 #define cfgRCC_DEV0_EPF0_VF10_RCC_CONFIG_MEMSIZE 0xd050378c #define cfgRCC_DEV0_EPF0_VF10_RCC_CONFIG_RESERVED 0xd0503790 #define cfgRCC_DEV0_EPF0_VF10_RCC_IOV_FUNC_IDENTIFIER 0xd0503794 // addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf10_BIFPFVFDEC1 // base address: 0xd0500000 #define cfgBIF_BX_DEV0_EPF0_VF10_BIF_BME_STATUS 0xd050382c #define cfgBIF_BX_DEV0_EPF0_VF10_BIF_ATOMIC_ERR_LOG 0xd0503830 #define cfgBIF_BX_DEV0_EPF0_VF10_DOORBELL_SELFRING_GPA_APER_BASE_HIGH 0xd050384c #define cfgBIF_BX_DEV0_EPF0_VF10_DOORBELL_SELFRING_GPA_APER_BASE_LOW 0xd0503850 #define cfgBIF_BX_DEV0_EPF0_VF10_DOORBELL_SELFRING_GPA_APER_CNTL 0xd0503854 #define cfgBIF_BX_DEV0_EPF0_VF10_HDP_REG_COHERENCY_FLUSH_CNTL 0xd0503858 #define cfgBIF_BX_DEV0_EPF0_VF10_HDP_MEM_COHERENCY_FLUSH_CNTL 0xd050385c #define cfgBIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_REQ 0xd0503898 #define cfgBIF_BX_DEV0_EPF0_VF10_GPU_HDP_FLUSH_DONE 0xd050389c #define cfgBIF_BX_DEV0_EPF0_VF10_BIF_TRANS_PENDING 0xd05038a0 #define cfgBIF_BX_DEV0_EPF0_VF10_NBIF_GFX_ADDR_LUT_BYPASS 0xd05038c8 #define cfgBIF_BX_DEV0_EPF0_VF10_MAILBOX_MSGBUF_TRN_DW0 0xd0503958 #define cfgBIF_BX_DEV0_EPF0_VF10_MAILBOX_MSGBUF_TRN_DW1 0xd050395c #define cfgBIF_BX_DEV0_EPF0_VF10_MAILBOX_MSGBUF_TRN_DW2 0xd0503960 #define cfgBIF_BX_DEV0_EPF0_VF10_MAILBOX_MSGBUF_TRN_DW3 0xd0503964 #define cfgBIF_BX_DEV0_EPF0_VF10_MAILBOX_MSGBUF_RCV_DW0 0xd0503968 #define cfgBIF_BX_DEV0_EPF0_VF10_MAILBOX_MSGBUF_RCV_DW1 0xd050396c #define cfgBIF_BX_DEV0_EPF0_VF10_MAILBOX_MSGBUF_RCV_DW2 0xd0503970 #define cfgBIF_BX_DEV0_EPF0_VF10_MAILBOX_MSGBUF_RCV_DW3 0xd0503974 #define cfgBIF_BX_DEV0_EPF0_VF10_MAILBOX_CONTROL 0xd0503978 #define cfgBIF_BX_DEV0_EPF0_VF10_MAILBOX_INT_CNTL 0xd050397c #define cfgBIF_BX_DEV0_EPF0_VF10_BIF_VMHV_MAILBOX 0xd0503980 // addressBlock: nbio_nbif0_rcc_dev0_epf0_vf10_BIFDEC2 // base address: 0xd0500000 #define cfgRCC_DEV0_EPF0_VF10_GFXMSIX_VECT0_ADDR_LO 0xd0542000 #define cfgRCC_DEV0_EPF0_VF10_GFXMSIX_VECT0_ADDR_HI 0xd0542004 #define cfgRCC_DEV0_EPF0_VF10_GFXMSIX_VECT0_MSG_DATA 0xd0542008 #define cfgRCC_DEV0_EPF0_VF10_GFXMSIX_VECT0_CONTROL 0xd054200c #define cfgRCC_DEV0_EPF0_VF10_GFXMSIX_VECT1_ADDR_LO 0xd0542010 #define cfgRCC_DEV0_EPF0_VF10_GFXMSIX_VECT1_ADDR_HI 0xd0542014 #define cfgRCC_DEV0_EPF0_VF10_GFXMSIX_VECT1_MSG_DATA 0xd0542018 #define cfgRCC_DEV0_EPF0_VF10_GFXMSIX_VECT1_CONTROL 0xd054201c #define cfgRCC_DEV0_EPF0_VF10_GFXMSIX_VECT2_ADDR_LO 0xd0542020 #define cfgRCC_DEV0_EPF0_VF10_GFXMSIX_VECT2_ADDR_HI 0xd0542024 #define cfgRCC_DEV0_EPF0_VF10_GFXMSIX_VECT2_MSG_DATA 0xd0542028 #define cfgRCC_DEV0_EPF0_VF10_GFXMSIX_VECT2_CONTROL 0xd054202c #define cfgRCC_DEV0_EPF0_VF10_GFXMSIX_VECT3_ADDR_LO 0xd0542030 #define cfgRCC_DEV0_EPF0_VF10_GFXMSIX_VECT3_ADDR_HI 0xd0542034 #define cfgRCC_DEV0_EPF0_VF10_GFXMSIX_VECT3_MSG_DATA 0xd0542038 #define cfgRCC_DEV0_EPF0_VF10_GFXMSIX_VECT3_CONTROL 0xd054203c #define cfgRCC_DEV0_EPF0_VF10_GFXMSIX_PBA 0xd0543000 // addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf11_SYSPFVFDEC // base address: 0xd0580000 #define cfgBIF_BX_DEV0_EPF0_VF11_MM_INDEX 0xd0580000 #define cfgBIF_BX_DEV0_EPF0_VF11_MM_DATA 0xd0580004 #define cfgBIF_BX_DEV0_EPF0_VF11_MM_INDEX_HI 0xd0580018 // addressBlock: nbio_nbif0_rcc_dev0_epf0_vf11_BIFPFVFDEC1 // base address: 0xd0580000 #define cfgRCC_DEV0_EPF0_VF11_RCC_ERR_LOG 0xd0583694 #define cfgRCC_DEV0_EPF0_VF11_RCC_DOORBELL_APER_EN 0xd0583780 #define cfgRCC_DEV0_EPF0_VF11_RCC_CONFIG_MEMSIZE 0xd058378c #define cfgRCC_DEV0_EPF0_VF11_RCC_CONFIG_RESERVED 0xd0583790 #define cfgRCC_DEV0_EPF0_VF11_RCC_IOV_FUNC_IDENTIFIER 0xd0583794 // addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf11_BIFPFVFDEC1 // base address: 0xd0580000 #define cfgBIF_BX_DEV0_EPF0_VF11_BIF_BME_STATUS 0xd058382c #define cfgBIF_BX_DEV0_EPF0_VF11_BIF_ATOMIC_ERR_LOG 0xd0583830 #define cfgBIF_BX_DEV0_EPF0_VF11_DOORBELL_SELFRING_GPA_APER_BASE_HIGH 0xd058384c #define cfgBIF_BX_DEV0_EPF0_VF11_DOORBELL_SELFRING_GPA_APER_BASE_LOW 0xd0583850 #define cfgBIF_BX_DEV0_EPF0_VF11_DOORBELL_SELFRING_GPA_APER_CNTL 0xd0583854 #define cfgBIF_BX_DEV0_EPF0_VF11_HDP_REG_COHERENCY_FLUSH_CNTL 0xd0583858 #define cfgBIF_BX_DEV0_EPF0_VF11_HDP_MEM_COHERENCY_FLUSH_CNTL 0xd058385c #define cfgBIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_REQ 0xd0583898 #define cfgBIF_BX_DEV0_EPF0_VF11_GPU_HDP_FLUSH_DONE 0xd058389c #define cfgBIF_BX_DEV0_EPF0_VF11_BIF_TRANS_PENDING 0xd05838a0 #define cfgBIF_BX_DEV0_EPF0_VF11_NBIF_GFX_ADDR_LUT_BYPASS 0xd05838c8 #define cfgBIF_BX_DEV0_EPF0_VF11_MAILBOX_MSGBUF_TRN_DW0 0xd0583958 #define cfgBIF_BX_DEV0_EPF0_VF11_MAILBOX_MSGBUF_TRN_DW1 0xd058395c #define cfgBIF_BX_DEV0_EPF0_VF11_MAILBOX_MSGBUF_TRN_DW2 0xd0583960 #define cfgBIF_BX_DEV0_EPF0_VF11_MAILBOX_MSGBUF_TRN_DW3 0xd0583964 #define cfgBIF_BX_DEV0_EPF0_VF11_MAILBOX_MSGBUF_RCV_DW0 0xd0583968 #define cfgBIF_BX_DEV0_EPF0_VF11_MAILBOX_MSGBUF_RCV_DW1 0xd058396c #define cfgBIF_BX_DEV0_EPF0_VF11_MAILBOX_MSGBUF_RCV_DW2 0xd0583970 #define cfgBIF_BX_DEV0_EPF0_VF11_MAILBOX_MSGBUF_RCV_DW3 0xd0583974 #define cfgBIF_BX_DEV0_EPF0_VF11_MAILBOX_CONTROL 0xd0583978 #define cfgBIF_BX_DEV0_EPF0_VF11_MAILBOX_INT_CNTL 0xd058397c #define cfgBIF_BX_DEV0_EPF0_VF11_BIF_VMHV_MAILBOX 0xd0583980 // addressBlock: nbio_nbif0_rcc_dev0_epf0_vf11_BIFDEC2 // base address: 0xd0580000 #define cfgRCC_DEV0_EPF0_VF11_GFXMSIX_VECT0_ADDR_LO 0xd05c2000 #define cfgRCC_DEV0_EPF0_VF11_GFXMSIX_VECT0_ADDR_HI 0xd05c2004 #define cfgRCC_DEV0_EPF0_VF11_GFXMSIX_VECT0_MSG_DATA 0xd05c2008 #define cfgRCC_DEV0_EPF0_VF11_GFXMSIX_VECT0_CONTROL 0xd05c200c #define cfgRCC_DEV0_EPF0_VF11_GFXMSIX_VECT1_ADDR_LO 0xd05c2010 #define cfgRCC_DEV0_EPF0_VF11_GFXMSIX_VECT1_ADDR_HI 0xd05c2014 #define cfgRCC_DEV0_EPF0_VF11_GFXMSIX_VECT1_MSG_DATA 0xd05c2018 #define cfgRCC_DEV0_EPF0_VF11_GFXMSIX_VECT1_CONTROL 0xd05c201c #define cfgRCC_DEV0_EPF0_VF11_GFXMSIX_VECT2_ADDR_LO 0xd05c2020 #define cfgRCC_DEV0_EPF0_VF11_GFXMSIX_VECT2_ADDR_HI 0xd05c2024 #define cfgRCC_DEV0_EPF0_VF11_GFXMSIX_VECT2_MSG_DATA 0xd05c2028 #define cfgRCC_DEV0_EPF0_VF11_GFXMSIX_VECT2_CONTROL 0xd05c202c #define cfgRCC_DEV0_EPF0_VF11_GFXMSIX_VECT3_ADDR_LO 0xd05c2030 #define cfgRCC_DEV0_EPF0_VF11_GFXMSIX_VECT3_ADDR_HI 0xd05c2034 #define cfgRCC_DEV0_EPF0_VF11_GFXMSIX_VECT3_MSG_DATA 0xd05c2038 #define cfgRCC_DEV0_EPF0_VF11_GFXMSIX_VECT3_CONTROL 0xd05c203c #define cfgRCC_DEV0_EPF0_VF11_GFXMSIX_PBA 0xd05c3000 // addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf12_SYSPFVFDEC // base address: 0xd0600000 #define cfgBIF_BX_DEV0_EPF0_VF12_MM_INDEX 0xd0600000 #define cfgBIF_BX_DEV0_EPF0_VF12_MM_DATA 0xd0600004 #define cfgBIF_BX_DEV0_EPF0_VF12_MM_INDEX_HI 0xd0600018 // addressBlock: nbio_nbif0_rcc_dev0_epf0_vf12_BIFPFVFDEC1 // base address: 0xd0600000 #define cfgRCC_DEV0_EPF0_VF12_RCC_ERR_LOG 0xd0603694 #define cfgRCC_DEV0_EPF0_VF12_RCC_DOORBELL_APER_EN 0xd0603780 #define cfgRCC_DEV0_EPF0_VF12_RCC_CONFIG_MEMSIZE 0xd060378c #define cfgRCC_DEV0_EPF0_VF12_RCC_CONFIG_RESERVED 0xd0603790 #define cfgRCC_DEV0_EPF0_VF12_RCC_IOV_FUNC_IDENTIFIER 0xd0603794 // addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf12_BIFPFVFDEC1 // base address: 0xd0600000 #define cfgBIF_BX_DEV0_EPF0_VF12_BIF_BME_STATUS 0xd060382c #define cfgBIF_BX_DEV0_EPF0_VF12_BIF_ATOMIC_ERR_LOG 0xd0603830 #define cfgBIF_BX_DEV0_EPF0_VF12_DOORBELL_SELFRING_GPA_APER_BASE_HIGH 0xd060384c #define cfgBIF_BX_DEV0_EPF0_VF12_DOORBELL_SELFRING_GPA_APER_BASE_LOW 0xd0603850 #define cfgBIF_BX_DEV0_EPF0_VF12_DOORBELL_SELFRING_GPA_APER_CNTL 0xd0603854 #define cfgBIF_BX_DEV0_EPF0_VF12_HDP_REG_COHERENCY_FLUSH_CNTL 0xd0603858 #define cfgBIF_BX_DEV0_EPF0_VF12_HDP_MEM_COHERENCY_FLUSH_CNTL 0xd060385c #define cfgBIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_REQ 0xd0603898 #define cfgBIF_BX_DEV0_EPF0_VF12_GPU_HDP_FLUSH_DONE 0xd060389c #define cfgBIF_BX_DEV0_EPF0_VF12_BIF_TRANS_PENDING 0xd06038a0 #define cfgBIF_BX_DEV0_EPF0_VF12_NBIF_GFX_ADDR_LUT_BYPASS 0xd06038c8 #define cfgBIF_BX_DEV0_EPF0_VF12_MAILBOX_MSGBUF_TRN_DW0 0xd0603958 #define cfgBIF_BX_DEV0_EPF0_VF12_MAILBOX_MSGBUF_TRN_DW1 0xd060395c #define cfgBIF_BX_DEV0_EPF0_VF12_MAILBOX_MSGBUF_TRN_DW2 0xd0603960 #define cfgBIF_BX_DEV0_EPF0_VF12_MAILBOX_MSGBUF_TRN_DW3 0xd0603964 #define cfgBIF_BX_DEV0_EPF0_VF12_MAILBOX_MSGBUF_RCV_DW0 0xd0603968 #define cfgBIF_BX_DEV0_EPF0_VF12_MAILBOX_MSGBUF_RCV_DW1 0xd060396c #define cfgBIF_BX_DEV0_EPF0_VF12_MAILBOX_MSGBUF_RCV_DW2 0xd0603970 #define cfgBIF_BX_DEV0_EPF0_VF12_MAILBOX_MSGBUF_RCV_DW3 0xd0603974 #define cfgBIF_BX_DEV0_EPF0_VF12_MAILBOX_CONTROL 0xd0603978 #define cfgBIF_BX_DEV0_EPF0_VF12_MAILBOX_INT_CNTL 0xd060397c #define cfgBIF_BX_DEV0_EPF0_VF12_BIF_VMHV_MAILBOX 0xd0603980 // addressBlock: nbio_nbif0_rcc_dev0_epf0_vf12_BIFDEC2 // base address: 0xd0600000 #define cfgRCC_DEV0_EPF0_VF12_GFXMSIX_VECT0_ADDR_LO 0xd0642000 #define cfgRCC_DEV0_EPF0_VF12_GFXMSIX_VECT0_ADDR_HI 0xd0642004 #define cfgRCC_DEV0_EPF0_VF12_GFXMSIX_VECT0_MSG_DATA 0xd0642008 #define cfgRCC_DEV0_EPF0_VF12_GFXMSIX_VECT0_CONTROL 0xd064200c #define cfgRCC_DEV0_EPF0_VF12_GFXMSIX_VECT1_ADDR_LO 0xd0642010 #define cfgRCC_DEV0_EPF0_VF12_GFXMSIX_VECT1_ADDR_HI 0xd0642014 #define cfgRCC_DEV0_EPF0_VF12_GFXMSIX_VECT1_MSG_DATA 0xd0642018 #define cfgRCC_DEV0_EPF0_VF12_GFXMSIX_VECT1_CONTROL 0xd064201c #define cfgRCC_DEV0_EPF0_VF12_GFXMSIX_VECT2_ADDR_LO 0xd0642020 #define cfgRCC_DEV0_EPF0_VF12_GFXMSIX_VECT2_ADDR_HI 0xd0642024 #define cfgRCC_DEV0_EPF0_VF12_GFXMSIX_VECT2_MSG_DATA 0xd0642028 #define cfgRCC_DEV0_EPF0_VF12_GFXMSIX_VECT2_CONTROL 0xd064202c #define cfgRCC_DEV0_EPF0_VF12_GFXMSIX_VECT3_ADDR_LO 0xd0642030 #define cfgRCC_DEV0_EPF0_VF12_GFXMSIX_VECT3_ADDR_HI 0xd0642034 #define cfgRCC_DEV0_EPF0_VF12_GFXMSIX_VECT3_MSG_DATA 0xd0642038 #define cfgRCC_DEV0_EPF0_VF12_GFXMSIX_VECT3_CONTROL 0xd064203c #define cfgRCC_DEV0_EPF0_VF12_GFXMSIX_PBA 0xd0643000 // addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf13_SYSPFVFDEC // base address: 0xd0680000 #define cfgBIF_BX_DEV0_EPF0_VF13_MM_INDEX 0xd0680000 #define cfgBIF_BX_DEV0_EPF0_VF13_MM_DATA 0xd0680004 #define cfgBIF_BX_DEV0_EPF0_VF13_MM_INDEX_HI 0xd0680018 // addressBlock: nbio_nbif0_rcc_dev0_epf0_vf13_BIFPFVFDEC1 // base address: 0xd0680000 #define cfgRCC_DEV0_EPF0_VF13_RCC_ERR_LOG 0xd0683694 #define cfgRCC_DEV0_EPF0_VF13_RCC_DOORBELL_APER_EN 0xd0683780 #define cfgRCC_DEV0_EPF0_VF13_RCC_CONFIG_MEMSIZE 0xd068378c #define cfgRCC_DEV0_EPF0_VF13_RCC_CONFIG_RESERVED 0xd0683790 #define cfgRCC_DEV0_EPF0_VF13_RCC_IOV_FUNC_IDENTIFIER 0xd0683794 // addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf13_BIFPFVFDEC1 // base address: 0xd0680000 #define cfgBIF_BX_DEV0_EPF0_VF13_BIF_BME_STATUS 0xd068382c #define cfgBIF_BX_DEV0_EPF0_VF13_BIF_ATOMIC_ERR_LOG 0xd0683830 #define cfgBIF_BX_DEV0_EPF0_VF13_DOORBELL_SELFRING_GPA_APER_BASE_HIGH 0xd068384c #define cfgBIF_BX_DEV0_EPF0_VF13_DOORBELL_SELFRING_GPA_APER_BASE_LOW 0xd0683850 #define cfgBIF_BX_DEV0_EPF0_VF13_DOORBELL_SELFRING_GPA_APER_CNTL 0xd0683854 #define cfgBIF_BX_DEV0_EPF0_VF13_HDP_REG_COHERENCY_FLUSH_CNTL 0xd0683858 #define cfgBIF_BX_DEV0_EPF0_VF13_HDP_MEM_COHERENCY_FLUSH_CNTL 0xd068385c #define cfgBIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_REQ 0xd0683898 #define cfgBIF_BX_DEV0_EPF0_VF13_GPU_HDP_FLUSH_DONE 0xd068389c #define cfgBIF_BX_DEV0_EPF0_VF13_BIF_TRANS_PENDING 0xd06838a0 #define cfgBIF_BX_DEV0_EPF0_VF13_NBIF_GFX_ADDR_LUT_BYPASS 0xd06838c8 #define cfgBIF_BX_DEV0_EPF0_VF13_MAILBOX_MSGBUF_TRN_DW0 0xd0683958 #define cfgBIF_BX_DEV0_EPF0_VF13_MAILBOX_MSGBUF_TRN_DW1 0xd068395c #define cfgBIF_BX_DEV0_EPF0_VF13_MAILBOX_MSGBUF_TRN_DW2 0xd0683960 #define cfgBIF_BX_DEV0_EPF0_VF13_MAILBOX_MSGBUF_TRN_DW3 0xd0683964 #define cfgBIF_BX_DEV0_EPF0_VF13_MAILBOX_MSGBUF_RCV_DW0 0xd0683968 #define cfgBIF_BX_DEV0_EPF0_VF13_MAILBOX_MSGBUF_RCV_DW1 0xd068396c #define cfgBIF_BX_DEV0_EPF0_VF13_MAILBOX_MSGBUF_RCV_DW2 0xd0683970 #define cfgBIF_BX_DEV0_EPF0_VF13_MAILBOX_MSGBUF_RCV_DW3 0xd0683974 #define cfgBIF_BX_DEV0_EPF0_VF13_MAILBOX_CONTROL 0xd0683978 #define cfgBIF_BX_DEV0_EPF0_VF13_MAILBOX_INT_CNTL 0xd068397c #define cfgBIF_BX_DEV0_EPF0_VF13_BIF_VMHV_MAILBOX 0xd0683980 // addressBlock: nbio_nbif0_rcc_dev0_epf0_vf13_BIFDEC2 // base address: 0xd0680000 #define cfgRCC_DEV0_EPF0_VF13_GFXMSIX_VECT0_ADDR_LO 0xd06c2000 #define cfgRCC_DEV0_EPF0_VF13_GFXMSIX_VECT0_ADDR_HI 0xd06c2004 #define cfgRCC_DEV0_EPF0_VF13_GFXMSIX_VECT0_MSG_DATA 0xd06c2008 #define cfgRCC_DEV0_EPF0_VF13_GFXMSIX_VECT0_CONTROL 0xd06c200c #define cfgRCC_DEV0_EPF0_VF13_GFXMSIX_VECT1_ADDR_LO 0xd06c2010 #define cfgRCC_DEV0_EPF0_VF13_GFXMSIX_VECT1_ADDR_HI 0xd06c2014 #define cfgRCC_DEV0_EPF0_VF13_GFXMSIX_VECT1_MSG_DATA 0xd06c2018 #define cfgRCC_DEV0_EPF0_VF13_GFXMSIX_VECT1_CONTROL 0xd06c201c #define cfgRCC_DEV0_EPF0_VF13_GFXMSIX_VECT2_ADDR_LO 0xd06c2020 #define cfgRCC_DEV0_EPF0_VF13_GFXMSIX_VECT2_ADDR_HI 0xd06c2024 #define cfgRCC_DEV0_EPF0_VF13_GFXMSIX_VECT2_MSG_DATA 0xd06c2028 #define cfgRCC_DEV0_EPF0_VF13_GFXMSIX_VECT2_CONTROL 0xd06c202c #define cfgRCC_DEV0_EPF0_VF13_GFXMSIX_VECT3_ADDR_LO 0xd06c2030 #define cfgRCC_DEV0_EPF0_VF13_GFXMSIX_VECT3_ADDR_HI 0xd06c2034 #define cfgRCC_DEV0_EPF0_VF13_GFXMSIX_VECT3_MSG_DATA 0xd06c2038 #define cfgRCC_DEV0_EPF0_VF13_GFXMSIX_VECT3_CONTROL 0xd06c203c #define cfgRCC_DEV0_EPF0_VF13_GFXMSIX_PBA 0xd06c3000 // addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf14_SYSPFVFDEC // base address: 0xd0700000 #define cfgBIF_BX_DEV0_EPF0_VF14_MM_INDEX 0xd0700000 #define cfgBIF_BX_DEV0_EPF0_VF14_MM_DATA 0xd0700004 #define cfgBIF_BX_DEV0_EPF0_VF14_MM_INDEX_HI 0xd0700018 // addressBlock: nbio_nbif0_rcc_dev0_epf0_vf14_BIFPFVFDEC1 // base address: 0xd0700000 #define cfgRCC_DEV0_EPF0_VF14_RCC_ERR_LOG 0xd0703694 #define cfgRCC_DEV0_EPF0_VF14_RCC_DOORBELL_APER_EN 0xd0703780 #define cfgRCC_DEV0_EPF0_VF14_RCC_CONFIG_MEMSIZE 0xd070378c #define cfgRCC_DEV0_EPF0_VF14_RCC_CONFIG_RESERVED 0xd0703790 #define cfgRCC_DEV0_EPF0_VF14_RCC_IOV_FUNC_IDENTIFIER 0xd0703794 // addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf14_BIFPFVFDEC1 // base address: 0xd0700000 #define cfgBIF_BX_DEV0_EPF0_VF14_BIF_BME_STATUS 0xd070382c #define cfgBIF_BX_DEV0_EPF0_VF14_BIF_ATOMIC_ERR_LOG 0xd0703830 #define cfgBIF_BX_DEV0_EPF0_VF14_DOORBELL_SELFRING_GPA_APER_BASE_HIGH 0xd070384c #define cfgBIF_BX_DEV0_EPF0_VF14_DOORBELL_SELFRING_GPA_APER_BASE_LOW 0xd0703850 #define cfgBIF_BX_DEV0_EPF0_VF14_DOORBELL_SELFRING_GPA_APER_CNTL 0xd0703854 #define cfgBIF_BX_DEV0_EPF0_VF14_HDP_REG_COHERENCY_FLUSH_CNTL 0xd0703858 #define cfgBIF_BX_DEV0_EPF0_VF14_HDP_MEM_COHERENCY_FLUSH_CNTL 0xd070385c #define cfgBIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_REQ 0xd0703898 #define cfgBIF_BX_DEV0_EPF0_VF14_GPU_HDP_FLUSH_DONE 0xd070389c #define cfgBIF_BX_DEV0_EPF0_VF14_BIF_TRANS_PENDING 0xd07038a0 #define cfgBIF_BX_DEV0_EPF0_VF14_NBIF_GFX_ADDR_LUT_BYPASS 0xd07038c8 #define cfgBIF_BX_DEV0_EPF0_VF14_MAILBOX_MSGBUF_TRN_DW0 0xd0703958 #define cfgBIF_BX_DEV0_EPF0_VF14_MAILBOX_MSGBUF_TRN_DW1 0xd070395c #define cfgBIF_BX_DEV0_EPF0_VF14_MAILBOX_MSGBUF_TRN_DW2 0xd0703960 #define cfgBIF_BX_DEV0_EPF0_VF14_MAILBOX_MSGBUF_TRN_DW3 0xd0703964 #define cfgBIF_BX_DEV0_EPF0_VF14_MAILBOX_MSGBUF_RCV_DW0 0xd0703968 #define cfgBIF_BX_DEV0_EPF0_VF14_MAILBOX_MSGBUF_RCV_DW1 0xd070396c #define cfgBIF_BX_DEV0_EPF0_VF14_MAILBOX_MSGBUF_RCV_DW2 0xd0703970 #define cfgBIF_BX_DEV0_EPF0_VF14_MAILBOX_MSGBUF_RCV_DW3 0xd0703974 #define cfgBIF_BX_DEV0_EPF0_VF14_MAILBOX_CONTROL 0xd0703978 #define cfgBIF_BX_DEV0_EPF0_VF14_MAILBOX_INT_CNTL 0xd070397c #define cfgBIF_BX_DEV0_EPF0_VF14_BIF_VMHV_MAILBOX 0xd0703980 // addressBlock: nbio_nbif0_rcc_dev0_epf0_vf14_BIFDEC2 // base address: 0xd0700000 #define cfgRCC_DEV0_EPF0_VF14_GFXMSIX_VECT0_ADDR_LO 0xd0742000 #define cfgRCC_DEV0_EPF0_VF14_GFXMSIX_VECT0_ADDR_HI 0xd0742004 #define cfgRCC_DEV0_EPF0_VF14_GFXMSIX_VECT0_MSG_DATA 0xd0742008 #define cfgRCC_DEV0_EPF0_VF14_GFXMSIX_VECT0_CONTROL 0xd074200c #define cfgRCC_DEV0_EPF0_VF14_GFXMSIX_VECT1_ADDR_LO 0xd0742010 #define cfgRCC_DEV0_EPF0_VF14_GFXMSIX_VECT1_ADDR_HI 0xd0742014 #define cfgRCC_DEV0_EPF0_VF14_GFXMSIX_VECT1_MSG_DATA 0xd0742018 #define cfgRCC_DEV0_EPF0_VF14_GFXMSIX_VECT1_CONTROL 0xd074201c #define cfgRCC_DEV0_EPF0_VF14_GFXMSIX_VECT2_ADDR_LO 0xd0742020 #define cfgRCC_DEV0_EPF0_VF14_GFXMSIX_VECT2_ADDR_HI 0xd0742024 #define cfgRCC_DEV0_EPF0_VF14_GFXMSIX_VECT2_MSG_DATA 0xd0742028 #define cfgRCC_DEV0_EPF0_VF14_GFXMSIX_VECT2_CONTROL 0xd074202c #define cfgRCC_DEV0_EPF0_VF14_GFXMSIX_VECT3_ADDR_LO 0xd0742030 #define cfgRCC_DEV0_EPF0_VF14_GFXMSIX_VECT3_ADDR_HI 0xd0742034 #define cfgRCC_DEV0_EPF0_VF14_GFXMSIX_VECT3_MSG_DATA 0xd0742038 #define cfgRCC_DEV0_EPF0_VF14_GFXMSIX_VECT3_CONTROL 0xd074203c #define cfgRCC_DEV0_EPF0_VF14_GFXMSIX_PBA 0xd0743000 // addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf15_SYSPFVFDEC // base address: 0xd0780000 #define cfgBIF_BX_DEV0_EPF0_VF15_MM_INDEX 0xd0780000 #define cfgBIF_BX_DEV0_EPF0_VF15_MM_DATA 0xd0780004 #define cfgBIF_BX_DEV0_EPF0_VF15_MM_INDEX_HI 0xd0780018 // addressBlock: nbio_nbif0_rcc_dev0_epf0_vf15_BIFPFVFDEC1 // base address: 0xd0780000 #define cfgRCC_DEV0_EPF0_VF15_RCC_ERR_LOG 0xd0783694 #define cfgRCC_DEV0_EPF0_VF15_RCC_DOORBELL_APER_EN 0xd0783780 #define cfgRCC_DEV0_EPF0_VF15_RCC_CONFIG_MEMSIZE 0xd078378c #define cfgRCC_DEV0_EPF0_VF15_RCC_CONFIG_RESERVED 0xd0783790 #define cfgRCC_DEV0_EPF0_VF15_RCC_IOV_FUNC_IDENTIFIER 0xd0783794 // addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf15_BIFPFVFDEC1 // base address: 0xd0780000 #define cfgBIF_BX_DEV0_EPF0_VF15_BIF_BME_STATUS 0xd078382c #define cfgBIF_BX_DEV0_EPF0_VF15_BIF_ATOMIC_ERR_LOG 0xd0783830 #define cfgBIF_BX_DEV0_EPF0_VF15_DOORBELL_SELFRING_GPA_APER_BASE_HIGH 0xd078384c #define cfgBIF_BX_DEV0_EPF0_VF15_DOORBELL_SELFRING_GPA_APER_BASE_LOW 0xd0783850 #define cfgBIF_BX_DEV0_EPF0_VF15_DOORBELL_SELFRING_GPA_APER_CNTL 0xd0783854 #define cfgBIF_BX_DEV0_EPF0_VF15_HDP_REG_COHERENCY_FLUSH_CNTL 0xd0783858 #define cfgBIF_BX_DEV0_EPF0_VF15_HDP_MEM_COHERENCY_FLUSH_CNTL 0xd078385c #define cfgBIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_REQ 0xd0783898 #define cfgBIF_BX_DEV0_EPF0_VF15_GPU_HDP_FLUSH_DONE 0xd078389c #define cfgBIF_BX_DEV0_EPF0_VF15_BIF_TRANS_PENDING 0xd07838a0 #define cfgBIF_BX_DEV0_EPF0_VF15_NBIF_GFX_ADDR_LUT_BYPASS 0xd07838c8 #define cfgBIF_BX_DEV0_EPF0_VF15_MAILBOX_MSGBUF_TRN_DW0 0xd0783958 #define cfgBIF_BX_DEV0_EPF0_VF15_MAILBOX_MSGBUF_TRN_DW1 0xd078395c #define cfgBIF_BX_DEV0_EPF0_VF15_MAILBOX_MSGBUF_TRN_DW2 0xd0783960 #define cfgBIF_BX_DEV0_EPF0_VF15_MAILBOX_MSGBUF_TRN_DW3 0xd0783964 #define cfgBIF_BX_DEV0_EPF0_VF15_MAILBOX_MSGBUF_RCV_DW0 0xd0783968 #define cfgBIF_BX_DEV0_EPF0_VF15_MAILBOX_MSGBUF_RCV_DW1 0xd078396c #define cfgBIF_BX_DEV0_EPF0_VF15_MAILBOX_MSGBUF_RCV_DW2 0xd0783970 #define cfgBIF_BX_DEV0_EPF0_VF15_MAILBOX_MSGBUF_RCV_DW3 0xd0783974 #define cfgBIF_BX_DEV0_EPF0_VF15_MAILBOX_CONTROL 0xd0783978 #define cfgBIF_BX_DEV0_EPF0_VF15_MAILBOX_INT_CNTL 0xd078397c #define cfgBIF_BX_DEV0_EPF0_VF15_BIF_VMHV_MAILBOX 0xd0783980 // addressBlock: nbio_nbif0_rcc_dev0_epf0_vf15_BIFDEC2 // base address: 0xd0780000 #define cfgRCC_DEV0_EPF0_VF15_GFXMSIX_VECT0_ADDR_LO 0xd07c2000 #define cfgRCC_DEV0_EPF0_VF15_GFXMSIX_VECT0_ADDR_HI 0xd07c2004 #define cfgRCC_DEV0_EPF0_VF15_GFXMSIX_VECT0_MSG_DATA 0xd07c2008 #define cfgRCC_DEV0_EPF0_VF15_GFXMSIX_VECT0_CONTROL 0xd07c200c #define cfgRCC_DEV0_EPF0_VF15_GFXMSIX_VECT1_ADDR_LO 0xd07c2010 #define cfgRCC_DEV0_EPF0_VF15_GFXMSIX_VECT1_ADDR_HI 0xd07c2014 #define cfgRCC_DEV0_EPF0_VF15_GFXMSIX_VECT1_MSG_DATA 0xd07c2018 #define cfgRCC_DEV0_EPF0_VF15_GFXMSIX_VECT1_CONTROL 0xd07c201c #define cfgRCC_DEV0_EPF0_VF15_GFXMSIX_VECT2_ADDR_LO 0xd07c2020 #define cfgRCC_DEV0_EPF0_VF15_GFXMSIX_VECT2_ADDR_HI 0xd07c2024 #define cfgRCC_DEV0_EPF0_VF15_GFXMSIX_VECT2_MSG_DATA 0xd07c2028 #define cfgRCC_DEV0_EPF0_VF15_GFXMSIX_VECT2_CONTROL 0xd07c202c #define cfgRCC_DEV0_EPF0_VF15_GFXMSIX_VECT3_ADDR_LO 0xd07c2030 #define cfgRCC_DEV0_EPF0_VF15_GFXMSIX_VECT3_ADDR_HI 0xd07c2034 #define cfgRCC_DEV0_EPF0_VF15_GFXMSIX_VECT3_MSG_DATA 0xd07c2038 #define cfgRCC_DEV0_EPF0_VF15_GFXMSIX_VECT3_CONTROL 0xd07c203c #define cfgRCC_DEV0_EPF0_VF15_GFXMSIX_PBA 0xd07c3000 // addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf16_SYSPFVFDEC // base address: 0xd0800000 #define cfgBIF_BX_DEV0_EPF0_VF16_MM_INDEX 0xd0800000 #define cfgBIF_BX_DEV0_EPF0_VF16_MM_DATA 0xd0800004 #define cfgBIF_BX_DEV0_EPF0_VF16_MM_INDEX_HI 0xd0800018 // addressBlock: nbio_nbif0_rcc_dev0_epf0_vf16_BIFPFVFDEC1 // base address: 0xd0800000 #define cfgRCC_DEV0_EPF0_VF16_RCC_ERR_LOG 0xd0803694 #define cfgRCC_DEV0_EPF0_VF16_RCC_DOORBELL_APER_EN 0xd0803780 #define cfgRCC_DEV0_EPF0_VF16_RCC_CONFIG_MEMSIZE 0xd080378c #define cfgRCC_DEV0_EPF0_VF16_RCC_CONFIG_RESERVED 0xd0803790 #define cfgRCC_DEV0_EPF0_VF16_RCC_IOV_FUNC_IDENTIFIER 0xd0803794 // addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf16_BIFPFVFDEC1 // base address: 0xd0800000 #define cfgBIF_BX_DEV0_EPF0_VF16_BIF_BME_STATUS 0xd080382c #define cfgBIF_BX_DEV0_EPF0_VF16_BIF_ATOMIC_ERR_LOG 0xd0803830 #define cfgBIF_BX_DEV0_EPF0_VF16_DOORBELL_SELFRING_GPA_APER_BASE_HIGH 0xd080384c #define cfgBIF_BX_DEV0_EPF0_VF16_DOORBELL_SELFRING_GPA_APER_BASE_LOW 0xd0803850 #define cfgBIF_BX_DEV0_EPF0_VF16_DOORBELL_SELFRING_GPA_APER_CNTL 0xd0803854 #define cfgBIF_BX_DEV0_EPF0_VF16_HDP_REG_COHERENCY_FLUSH_CNTL 0xd0803858 #define cfgBIF_BX_DEV0_EPF0_VF16_HDP_MEM_COHERENCY_FLUSH_CNTL 0xd080385c #define cfgBIF_BX_DEV0_EPF0_VF16_GPU_HDP_FLUSH_REQ 0xd0803898 #define cfgBIF_BX_DEV0_EPF0_VF16_GPU_HDP_FLUSH_DONE 0xd080389c #define cfgBIF_BX_DEV0_EPF0_VF16_BIF_TRANS_PENDING 0xd08038a0 #define cfgBIF_BX_DEV0_EPF0_VF16_NBIF_GFX_ADDR_LUT_BYPASS 0xd08038c8 #define cfgBIF_BX_DEV0_EPF0_VF16_MAILBOX_MSGBUF_TRN_DW0 0xd0803958 #define cfgBIF_BX_DEV0_EPF0_VF16_MAILBOX_MSGBUF_TRN_DW1 0xd080395c #define cfgBIF_BX_DEV0_EPF0_VF16_MAILBOX_MSGBUF_TRN_DW2 0xd0803960 #define cfgBIF_BX_DEV0_EPF0_VF16_MAILBOX_MSGBUF_TRN_DW3 0xd0803964 #define cfgBIF_BX_DEV0_EPF0_VF16_MAILBOX_MSGBUF_RCV_DW0 0xd0803968 #define cfgBIF_BX_DEV0_EPF0_VF16_MAILBOX_MSGBUF_RCV_DW1 0xd080396c #define cfgBIF_BX_DEV0_EPF0_VF16_MAILBOX_MSGBUF_RCV_DW2 0xd0803970 #define cfgBIF_BX_DEV0_EPF0_VF16_MAILBOX_MSGBUF_RCV_DW3 0xd0803974 #define cfgBIF_BX_DEV0_EPF0_VF16_MAILBOX_CONTROL 0xd0803978 #define cfgBIF_BX_DEV0_EPF0_VF16_MAILBOX_INT_CNTL 0xd080397c #define cfgBIF_BX_DEV0_EPF0_VF16_BIF_VMHV_MAILBOX 0xd0803980 // addressBlock: nbio_nbif0_rcc_dev0_epf0_vf16_BIFDEC2 // base address: 0xd0800000 #define cfgRCC_DEV0_EPF0_VF16_GFXMSIX_VECT0_ADDR_LO 0xd0842000 #define cfgRCC_DEV0_EPF0_VF16_GFXMSIX_VECT0_ADDR_HI 0xd0842004 #define cfgRCC_DEV0_EPF0_VF16_GFXMSIX_VECT0_MSG_DATA 0xd0842008 #define cfgRCC_DEV0_EPF0_VF16_GFXMSIX_VECT0_CONTROL 0xd084200c #define cfgRCC_DEV0_EPF0_VF16_GFXMSIX_VECT1_ADDR_LO 0xd0842010 #define cfgRCC_DEV0_EPF0_VF16_GFXMSIX_VECT1_ADDR_HI 0xd0842014 #define cfgRCC_DEV0_EPF0_VF16_GFXMSIX_VECT1_MSG_DATA 0xd0842018 #define cfgRCC_DEV0_EPF0_VF16_GFXMSIX_VECT1_CONTROL 0xd084201c #define cfgRCC_DEV0_EPF0_VF16_GFXMSIX_VECT2_ADDR_LO 0xd0842020 #define cfgRCC_DEV0_EPF0_VF16_GFXMSIX_VECT2_ADDR_HI 0xd0842024 #define cfgRCC_DEV0_EPF0_VF16_GFXMSIX_VECT2_MSG_DATA 0xd0842028 #define cfgRCC_DEV0_EPF0_VF16_GFXMSIX_VECT2_CONTROL 0xd084202c #define cfgRCC_DEV0_EPF0_VF16_GFXMSIX_VECT3_ADDR_LO 0xd0842030 #define cfgRCC_DEV0_EPF0_VF16_GFXMSIX_VECT3_ADDR_HI 0xd0842034 #define cfgRCC_DEV0_EPF0_VF16_GFXMSIX_VECT3_MSG_DATA 0xd0842038 #define cfgRCC_DEV0_EPF0_VF16_GFXMSIX_VECT3_CONTROL 0xd084203c #define cfgRCC_DEV0_EPF0_VF16_GFXMSIX_PBA 0xd0843000 // addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf17_SYSPFVFDEC // base address: 0xd0880000 #define cfgBIF_BX_DEV0_EPF0_VF17_MM_INDEX 0xd0880000 #define cfgBIF_BX_DEV0_EPF0_VF17_MM_DATA 0xd0880004 #define cfgBIF_BX_DEV0_EPF0_VF17_MM_INDEX_HI 0xd0880018 // addressBlock: nbio_nbif0_rcc_dev0_epf0_vf17_BIFPFVFDEC1 // base address: 0xd0880000 #define cfgRCC_DEV0_EPF0_VF17_RCC_ERR_LOG 0xd0883694 #define cfgRCC_DEV0_EPF0_VF17_RCC_DOORBELL_APER_EN 0xd0883780 #define cfgRCC_DEV0_EPF0_VF17_RCC_CONFIG_MEMSIZE 0xd088378c #define cfgRCC_DEV0_EPF0_VF17_RCC_CONFIG_RESERVED 0xd0883790 #define cfgRCC_DEV0_EPF0_VF17_RCC_IOV_FUNC_IDENTIFIER 0xd0883794 // addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf17_BIFPFVFDEC1 // base address: 0xd0880000 #define cfgBIF_BX_DEV0_EPF0_VF17_BIF_BME_STATUS 0xd088382c #define cfgBIF_BX_DEV0_EPF0_VF17_BIF_ATOMIC_ERR_LOG 0xd0883830 #define cfgBIF_BX_DEV0_EPF0_VF17_DOORBELL_SELFRING_GPA_APER_BASE_HIGH 0xd088384c #define cfgBIF_BX_DEV0_EPF0_VF17_DOORBELL_SELFRING_GPA_APER_BASE_LOW 0xd0883850 #define cfgBIF_BX_DEV0_EPF0_VF17_DOORBELL_SELFRING_GPA_APER_CNTL 0xd0883854 #define cfgBIF_BX_DEV0_EPF0_VF17_HDP_REG_COHERENCY_FLUSH_CNTL 0xd0883858 #define cfgBIF_BX_DEV0_EPF0_VF17_HDP_MEM_COHERENCY_FLUSH_CNTL 0xd088385c #define cfgBIF_BX_DEV0_EPF0_VF17_GPU_HDP_FLUSH_REQ 0xd0883898 #define cfgBIF_BX_DEV0_EPF0_VF17_GPU_HDP_FLUSH_DONE 0xd088389c #define cfgBIF_BX_DEV0_EPF0_VF17_BIF_TRANS_PENDING 0xd08838a0 #define cfgBIF_BX_DEV0_EPF0_VF17_NBIF_GFX_ADDR_LUT_BYPASS 0xd08838c8 #define cfgBIF_BX_DEV0_EPF0_VF17_MAILBOX_MSGBUF_TRN_DW0 0xd0883958 #define cfgBIF_BX_DEV0_EPF0_VF17_MAILBOX_MSGBUF_TRN_DW1 0xd088395c #define cfgBIF_BX_DEV0_EPF0_VF17_MAILBOX_MSGBUF_TRN_DW2 0xd0883960 #define cfgBIF_BX_DEV0_EPF0_VF17_MAILBOX_MSGBUF_TRN_DW3 0xd0883964 #define cfgBIF_BX_DEV0_EPF0_VF17_MAILBOX_MSGBUF_RCV_DW0 0xd0883968 #define cfgBIF_BX_DEV0_EPF0_VF17_MAILBOX_MSGBUF_RCV_DW1 0xd088396c #define cfgBIF_BX_DEV0_EPF0_VF17_MAILBOX_MSGBUF_RCV_DW2 0xd0883970 #define cfgBIF_BX_DEV0_EPF0_VF17_MAILBOX_MSGBUF_RCV_DW3 0xd0883974 #define cfgBIF_BX_DEV0_EPF0_VF17_MAILBOX_CONTROL 0xd0883978 #define cfgBIF_BX_DEV0_EPF0_VF17_MAILBOX_INT_CNTL 0xd088397c #define cfgBIF_BX_DEV0_EPF0_VF17_BIF_VMHV_MAILBOX 0xd0883980 // addressBlock: nbio_nbif0_rcc_dev0_epf0_vf17_BIFDEC2 // base address: 0xd0880000 #define cfgRCC_DEV0_EPF0_VF17_GFXMSIX_VECT0_ADDR_LO 0xd08c2000 #define cfgRCC_DEV0_EPF0_VF17_GFXMSIX_VECT0_ADDR_HI 0xd08c2004 #define cfgRCC_DEV0_EPF0_VF17_GFXMSIX_VECT0_MSG_DATA 0xd08c2008 #define cfgRCC_DEV0_EPF0_VF17_GFXMSIX_VECT0_CONTROL 0xd08c200c #define cfgRCC_DEV0_EPF0_VF17_GFXMSIX_VECT1_ADDR_LO 0xd08c2010 #define cfgRCC_DEV0_EPF0_VF17_GFXMSIX_VECT1_ADDR_HI 0xd08c2014 #define cfgRCC_DEV0_EPF0_VF17_GFXMSIX_VECT1_MSG_DATA 0xd08c2018 #define cfgRCC_DEV0_EPF0_VF17_GFXMSIX_VECT1_CONTROL 0xd08c201c #define cfgRCC_DEV0_EPF0_VF17_GFXMSIX_VECT2_ADDR_LO 0xd08c2020 #define cfgRCC_DEV0_EPF0_VF17_GFXMSIX_VECT2_ADDR_HI 0xd08c2024 #define cfgRCC_DEV0_EPF0_VF17_GFXMSIX_VECT2_MSG_DATA 0xd08c2028 #define cfgRCC_DEV0_EPF0_VF17_GFXMSIX_VECT2_CONTROL 0xd08c202c #define cfgRCC_DEV0_EPF0_VF17_GFXMSIX_VECT3_ADDR_LO 0xd08c2030 #define cfgRCC_DEV0_EPF0_VF17_GFXMSIX_VECT3_ADDR_HI 0xd08c2034 #define cfgRCC_DEV0_EPF0_VF17_GFXMSIX_VECT3_MSG_DATA 0xd08c2038 #define cfgRCC_DEV0_EPF0_VF17_GFXMSIX_VECT3_CONTROL 0xd08c203c #define cfgRCC_DEV0_EPF0_VF17_GFXMSIX_PBA 0xd08c3000 // addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf18_SYSPFVFDEC // base address: 0xd0900000 #define cfgBIF_BX_DEV0_EPF0_VF18_MM_INDEX 0xd0900000 #define cfgBIF_BX_DEV0_EPF0_VF18_MM_DATA 0xd0900004 #define cfgBIF_BX_DEV0_EPF0_VF18_MM_INDEX_HI 0xd0900018 // addressBlock: nbio_nbif0_rcc_dev0_epf0_vf18_BIFPFVFDEC1 // base address: 0xd0900000 #define cfgRCC_DEV0_EPF0_VF18_RCC_ERR_LOG 0xd0903694 #define cfgRCC_DEV0_EPF0_VF18_RCC_DOORBELL_APER_EN 0xd0903780 #define cfgRCC_DEV0_EPF0_VF18_RCC_CONFIG_MEMSIZE 0xd090378c #define cfgRCC_DEV0_EPF0_VF18_RCC_CONFIG_RESERVED 0xd0903790 #define cfgRCC_DEV0_EPF0_VF18_RCC_IOV_FUNC_IDENTIFIER 0xd0903794 // addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf18_BIFPFVFDEC1 // base address: 0xd0900000 #define cfgBIF_BX_DEV0_EPF0_VF18_BIF_BME_STATUS 0xd090382c #define cfgBIF_BX_DEV0_EPF0_VF18_BIF_ATOMIC_ERR_LOG 0xd0903830 #define cfgBIF_BX_DEV0_EPF0_VF18_DOORBELL_SELFRING_GPA_APER_BASE_HIGH 0xd090384c #define cfgBIF_BX_DEV0_EPF0_VF18_DOORBELL_SELFRING_GPA_APER_BASE_LOW 0xd0903850 #define cfgBIF_BX_DEV0_EPF0_VF18_DOORBELL_SELFRING_GPA_APER_CNTL 0xd0903854 #define cfgBIF_BX_DEV0_EPF0_VF18_HDP_REG_COHERENCY_FLUSH_CNTL 0xd0903858 #define cfgBIF_BX_DEV0_EPF0_VF18_HDP_MEM_COHERENCY_FLUSH_CNTL 0xd090385c #define cfgBIF_BX_DEV0_EPF0_VF18_GPU_HDP_FLUSH_REQ 0xd0903898 #define cfgBIF_BX_DEV0_EPF0_VF18_GPU_HDP_FLUSH_DONE 0xd090389c #define cfgBIF_BX_DEV0_EPF0_VF18_BIF_TRANS_PENDING 0xd09038a0 #define cfgBIF_BX_DEV0_EPF0_VF18_NBIF_GFX_ADDR_LUT_BYPASS 0xd09038c8 #define cfgBIF_BX_DEV0_EPF0_VF18_MAILBOX_MSGBUF_TRN_DW0 0xd0903958 #define cfgBIF_BX_DEV0_EPF0_VF18_MAILBOX_MSGBUF_TRN_DW1 0xd090395c #define cfgBIF_BX_DEV0_EPF0_VF18_MAILBOX_MSGBUF_TRN_DW2 0xd0903960 #define cfgBIF_BX_DEV0_EPF0_VF18_MAILBOX_MSGBUF_TRN_DW3 0xd0903964 #define cfgBIF_BX_DEV0_EPF0_VF18_MAILBOX_MSGBUF_RCV_DW0 0xd0903968 #define cfgBIF_BX_DEV0_EPF0_VF18_MAILBOX_MSGBUF_RCV_DW1 0xd090396c #define cfgBIF_BX_DEV0_EPF0_VF18_MAILBOX_MSGBUF_RCV_DW2 0xd0903970 #define cfgBIF_BX_DEV0_EPF0_VF18_MAILBOX_MSGBUF_RCV_DW3 0xd0903974 #define cfgBIF_BX_DEV0_EPF0_VF18_MAILBOX_CONTROL 0xd0903978 #define cfgBIF_BX_DEV0_EPF0_VF18_MAILBOX_INT_CNTL 0xd090397c #define cfgBIF_BX_DEV0_EPF0_VF18_BIF_VMHV_MAILBOX 0xd0903980 // addressBlock: nbio_nbif0_rcc_dev0_epf0_vf18_BIFDEC2 // base address: 0xd0900000 #define cfgRCC_DEV0_EPF0_VF18_GFXMSIX_VECT0_ADDR_LO 0xd0942000 #define cfgRCC_DEV0_EPF0_VF18_GFXMSIX_VECT0_ADDR_HI 0xd0942004 #define cfgRCC_DEV0_EPF0_VF18_GFXMSIX_VECT0_MSG_DATA 0xd0942008 #define cfgRCC_DEV0_EPF0_VF18_GFXMSIX_VECT0_CONTROL 0xd094200c #define cfgRCC_DEV0_EPF0_VF18_GFXMSIX_VECT1_ADDR_LO 0xd0942010 #define cfgRCC_DEV0_EPF0_VF18_GFXMSIX_VECT1_ADDR_HI 0xd0942014 #define cfgRCC_DEV0_EPF0_VF18_GFXMSIX_VECT1_MSG_DATA 0xd0942018 #define cfgRCC_DEV0_EPF0_VF18_GFXMSIX_VECT1_CONTROL 0xd094201c #define cfgRCC_DEV0_EPF0_VF18_GFXMSIX_VECT2_ADDR_LO 0xd0942020 #define cfgRCC_DEV0_EPF0_VF18_GFXMSIX_VECT2_ADDR_HI 0xd0942024 #define cfgRCC_DEV0_EPF0_VF18_GFXMSIX_VECT2_MSG_DATA 0xd0942028 #define cfgRCC_DEV0_EPF0_VF18_GFXMSIX_VECT2_CONTROL 0xd094202c #define cfgRCC_DEV0_EPF0_VF18_GFXMSIX_VECT3_ADDR_LO 0xd0942030 #define cfgRCC_DEV0_EPF0_VF18_GFXMSIX_VECT3_ADDR_HI 0xd0942034 #define cfgRCC_DEV0_EPF0_VF18_GFXMSIX_VECT3_MSG_DATA 0xd0942038 #define cfgRCC_DEV0_EPF0_VF18_GFXMSIX_VECT3_CONTROL 0xd094203c #define cfgRCC_DEV0_EPF0_VF18_GFXMSIX_PBA 0xd0943000 // addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf19_SYSPFVFDEC // base address: 0xd0980000 #define cfgBIF_BX_DEV0_EPF0_VF19_MM_INDEX 0xd0980000 #define cfgBIF_BX_DEV0_EPF0_VF19_MM_DATA 0xd0980004 #define cfgBIF_BX_DEV0_EPF0_VF19_MM_INDEX_HI 0xd0980018 // addressBlock: nbio_nbif0_rcc_dev0_epf0_vf19_BIFPFVFDEC1 // base address: 0xd0980000 #define cfgRCC_DEV0_EPF0_VF19_RCC_ERR_LOG 0xd0983694 #define cfgRCC_DEV0_EPF0_VF19_RCC_DOORBELL_APER_EN 0xd0983780 #define cfgRCC_DEV0_EPF0_VF19_RCC_CONFIG_MEMSIZE 0xd098378c #define cfgRCC_DEV0_EPF0_VF19_RCC_CONFIG_RESERVED 0xd0983790 #define cfgRCC_DEV0_EPF0_VF19_RCC_IOV_FUNC_IDENTIFIER 0xd0983794 // addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf19_BIFPFVFDEC1 // base address: 0xd0980000 #define cfgBIF_BX_DEV0_EPF0_VF19_BIF_BME_STATUS 0xd098382c #define cfgBIF_BX_DEV0_EPF0_VF19_BIF_ATOMIC_ERR_LOG 0xd0983830 #define cfgBIF_BX_DEV0_EPF0_VF19_DOORBELL_SELFRING_GPA_APER_BASE_HIGH 0xd098384c #define cfgBIF_BX_DEV0_EPF0_VF19_DOORBELL_SELFRING_GPA_APER_BASE_LOW 0xd0983850 #define cfgBIF_BX_DEV0_EPF0_VF19_DOORBELL_SELFRING_GPA_APER_CNTL 0xd0983854 #define cfgBIF_BX_DEV0_EPF0_VF19_HDP_REG_COHERENCY_FLUSH_CNTL 0xd0983858 #define cfgBIF_BX_DEV0_EPF0_VF19_HDP_MEM_COHERENCY_FLUSH_CNTL 0xd098385c #define cfgBIF_BX_DEV0_EPF0_VF19_GPU_HDP_FLUSH_REQ 0xd0983898 #define cfgBIF_BX_DEV0_EPF0_VF19_GPU_HDP_FLUSH_DONE 0xd098389c #define cfgBIF_BX_DEV0_EPF0_VF19_BIF_TRANS_PENDING 0xd09838a0 #define cfgBIF_BX_DEV0_EPF0_VF19_NBIF_GFX_ADDR_LUT_BYPASS 0xd09838c8 #define cfgBIF_BX_DEV0_EPF0_VF19_MAILBOX_MSGBUF_TRN_DW0 0xd0983958 #define cfgBIF_BX_DEV0_EPF0_VF19_MAILBOX_MSGBUF_TRN_DW1 0xd098395c #define cfgBIF_BX_DEV0_EPF0_VF19_MAILBOX_MSGBUF_TRN_DW2 0xd0983960 #define cfgBIF_BX_DEV0_EPF0_VF19_MAILBOX_MSGBUF_TRN_DW3 0xd0983964 #define cfgBIF_BX_DEV0_EPF0_VF19_MAILBOX_MSGBUF_RCV_DW0 0xd0983968 #define cfgBIF_BX_DEV0_EPF0_VF19_MAILBOX_MSGBUF_RCV_DW1 0xd098396c #define cfgBIF_BX_DEV0_EPF0_VF19_MAILBOX_MSGBUF_RCV_DW2 0xd0983970 #define cfgBIF_BX_DEV0_EPF0_VF19_MAILBOX_MSGBUF_RCV_DW3 0xd0983974 #define cfgBIF_BX_DEV0_EPF0_VF19_MAILBOX_CONTROL 0xd0983978 #define cfgBIF_BX_DEV0_EPF0_VF19_MAILBOX_INT_CNTL 0xd098397c #define cfgBIF_BX_DEV0_EPF0_VF19_BIF_VMHV_MAILBOX 0xd0983980 // addressBlock: nbio_nbif0_rcc_dev0_epf0_vf19_BIFDEC2 // base address: 0xd0980000 #define cfgRCC_DEV0_EPF0_VF19_GFXMSIX_VECT0_ADDR_LO 0xd09c2000 #define cfgRCC_DEV0_EPF0_VF19_GFXMSIX_VECT0_ADDR_HI 0xd09c2004 #define cfgRCC_DEV0_EPF0_VF19_GFXMSIX_VECT0_MSG_DATA 0xd09c2008 #define cfgRCC_DEV0_EPF0_VF19_GFXMSIX_VECT0_CONTROL 0xd09c200c #define cfgRCC_DEV0_EPF0_VF19_GFXMSIX_VECT1_ADDR_LO 0xd09c2010 #define cfgRCC_DEV0_EPF0_VF19_GFXMSIX_VECT1_ADDR_HI 0xd09c2014 #define cfgRCC_DEV0_EPF0_VF19_GFXMSIX_VECT1_MSG_DATA 0xd09c2018 #define cfgRCC_DEV0_EPF0_VF19_GFXMSIX_VECT1_CONTROL 0xd09c201c #define cfgRCC_DEV0_EPF0_VF19_GFXMSIX_VECT2_ADDR_LO 0xd09c2020 #define cfgRCC_DEV0_EPF0_VF19_GFXMSIX_VECT2_ADDR_HI 0xd09c2024 #define cfgRCC_DEV0_EPF0_VF19_GFXMSIX_VECT2_MSG_DATA 0xd09c2028 #define cfgRCC_DEV0_EPF0_VF19_GFXMSIX_VECT2_CONTROL 0xd09c202c #define cfgRCC_DEV0_EPF0_VF19_GFXMSIX_VECT3_ADDR_LO 0xd09c2030 #define cfgRCC_DEV0_EPF0_VF19_GFXMSIX_VECT3_ADDR_HI 0xd09c2034 #define cfgRCC_DEV0_EPF0_VF19_GFXMSIX_VECT3_MSG_DATA 0xd09c2038 #define cfgRCC_DEV0_EPF0_VF19_GFXMSIX_VECT3_CONTROL 0xd09c203c #define cfgRCC_DEV0_EPF0_VF19_GFXMSIX_PBA 0xd09c3000 // addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf20_SYSPFVFDEC // base address: 0xd0a00000 #define cfgBIF_BX_DEV0_EPF0_VF20_MM_INDEX 0xd0a00000 #define cfgBIF_BX_DEV0_EPF0_VF20_MM_DATA 0xd0a00004 #define cfgBIF_BX_DEV0_EPF0_VF20_MM_INDEX_HI 0xd0a00018 // addressBlock: nbio_nbif0_rcc_dev0_epf0_vf20_BIFPFVFDEC1 // base address: 0xd0a00000 #define cfgRCC_DEV0_EPF0_VF20_RCC_ERR_LOG 0xd0a03694 #define cfgRCC_DEV0_EPF0_VF20_RCC_DOORBELL_APER_EN 0xd0a03780 #define cfgRCC_DEV0_EPF0_VF20_RCC_CONFIG_MEMSIZE 0xd0a0378c #define cfgRCC_DEV0_EPF0_VF20_RCC_CONFIG_RESERVED 0xd0a03790 #define cfgRCC_DEV0_EPF0_VF20_RCC_IOV_FUNC_IDENTIFIER 0xd0a03794 // addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf20_BIFPFVFDEC1 // base address: 0xd0a00000 #define cfgBIF_BX_DEV0_EPF0_VF20_BIF_BME_STATUS 0xd0a0382c #define cfgBIF_BX_DEV0_EPF0_VF20_BIF_ATOMIC_ERR_LOG 0xd0a03830 #define cfgBIF_BX_DEV0_EPF0_VF20_DOORBELL_SELFRING_GPA_APER_BASE_HIGH 0xd0a0384c #define cfgBIF_BX_DEV0_EPF0_VF20_DOORBELL_SELFRING_GPA_APER_BASE_LOW 0xd0a03850 #define cfgBIF_BX_DEV0_EPF0_VF20_DOORBELL_SELFRING_GPA_APER_CNTL 0xd0a03854 #define cfgBIF_BX_DEV0_EPF0_VF20_HDP_REG_COHERENCY_FLUSH_CNTL 0xd0a03858 #define cfgBIF_BX_DEV0_EPF0_VF20_HDP_MEM_COHERENCY_FLUSH_CNTL 0xd0a0385c #define cfgBIF_BX_DEV0_EPF0_VF20_GPU_HDP_FLUSH_REQ 0xd0a03898 #define cfgBIF_BX_DEV0_EPF0_VF20_GPU_HDP_FLUSH_DONE 0xd0a0389c #define cfgBIF_BX_DEV0_EPF0_VF20_BIF_TRANS_PENDING 0xd0a038a0 #define cfgBIF_BX_DEV0_EPF0_VF20_NBIF_GFX_ADDR_LUT_BYPASS 0xd0a038c8 #define cfgBIF_BX_DEV0_EPF0_VF20_MAILBOX_MSGBUF_TRN_DW0 0xd0a03958 #define cfgBIF_BX_DEV0_EPF0_VF20_MAILBOX_MSGBUF_TRN_DW1 0xd0a0395c #define cfgBIF_BX_DEV0_EPF0_VF20_MAILBOX_MSGBUF_TRN_DW2 0xd0a03960 #define cfgBIF_BX_DEV0_EPF0_VF20_MAILBOX_MSGBUF_TRN_DW3 0xd0a03964 #define cfgBIF_BX_DEV0_EPF0_VF20_MAILBOX_MSGBUF_RCV_DW0 0xd0a03968 #define cfgBIF_BX_DEV0_EPF0_VF20_MAILBOX_MSGBUF_RCV_DW1 0xd0a0396c #define cfgBIF_BX_DEV0_EPF0_VF20_MAILBOX_MSGBUF_RCV_DW2 0xd0a03970 #define cfgBIF_BX_DEV0_EPF0_VF20_MAILBOX_MSGBUF_RCV_DW3 0xd0a03974 #define cfgBIF_BX_DEV0_EPF0_VF20_MAILBOX_CONTROL 0xd0a03978 #define cfgBIF_BX_DEV0_EPF0_VF20_MAILBOX_INT_CNTL 0xd0a0397c #define cfgBIF_BX_DEV0_EPF0_VF20_BIF_VMHV_MAILBOX 0xd0a03980 // addressBlock: nbio_nbif0_rcc_dev0_epf0_vf20_BIFDEC2 // base address: 0xd0a00000 #define cfgRCC_DEV0_EPF0_VF20_GFXMSIX_VECT0_ADDR_LO 0xd0a42000 #define cfgRCC_DEV0_EPF0_VF20_GFXMSIX_VECT0_ADDR_HI 0xd0a42004 #define cfgRCC_DEV0_EPF0_VF20_GFXMSIX_VECT0_MSG_DATA 0xd0a42008 #define cfgRCC_DEV0_EPF0_VF20_GFXMSIX_VECT0_CONTROL 0xd0a4200c #define cfgRCC_DEV0_EPF0_VF20_GFXMSIX_VECT1_ADDR_LO 0xd0a42010 #define cfgRCC_DEV0_EPF0_VF20_GFXMSIX_VECT1_ADDR_HI 0xd0a42014 #define cfgRCC_DEV0_EPF0_VF20_GFXMSIX_VECT1_MSG_DATA 0xd0a42018 #define cfgRCC_DEV0_EPF0_VF20_GFXMSIX_VECT1_CONTROL 0xd0a4201c #define cfgRCC_DEV0_EPF0_VF20_GFXMSIX_VECT2_ADDR_LO 0xd0a42020 #define cfgRCC_DEV0_EPF0_VF20_GFXMSIX_VECT2_ADDR_HI 0xd0a42024 #define cfgRCC_DEV0_EPF0_VF20_GFXMSIX_VECT2_MSG_DATA 0xd0a42028 #define cfgRCC_DEV0_EPF0_VF20_GFXMSIX_VECT2_CONTROL 0xd0a4202c #define cfgRCC_DEV0_EPF0_VF20_GFXMSIX_VECT3_ADDR_LO 0xd0a42030 #define cfgRCC_DEV0_EPF0_VF20_GFXMSIX_VECT3_ADDR_HI 0xd0a42034 #define cfgRCC_DEV0_EPF0_VF20_GFXMSIX_VECT3_MSG_DATA 0xd0a42038 #define cfgRCC_DEV0_EPF0_VF20_GFXMSIX_VECT3_CONTROL 0xd0a4203c #define cfgRCC_DEV0_EPF0_VF20_GFXMSIX_PBA 0xd0a43000 // addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf21_SYSPFVFDEC // base address: 0xd0a80000 #define cfgBIF_BX_DEV0_EPF0_VF21_MM_INDEX 0xd0a80000 #define cfgBIF_BX_DEV0_EPF0_VF21_MM_DATA 0xd0a80004 #define cfgBIF_BX_DEV0_EPF0_VF21_MM_INDEX_HI 0xd0a80018 // addressBlock: nbio_nbif0_rcc_dev0_epf0_vf21_BIFPFVFDEC1 // base address: 0xd0a80000 #define cfgRCC_DEV0_EPF0_VF21_RCC_ERR_LOG 0xd0a83694 #define cfgRCC_DEV0_EPF0_VF21_RCC_DOORBELL_APER_EN 0xd0a83780 #define cfgRCC_DEV0_EPF0_VF21_RCC_CONFIG_MEMSIZE 0xd0a8378c #define cfgRCC_DEV0_EPF0_VF21_RCC_CONFIG_RESERVED 0xd0a83790 #define cfgRCC_DEV0_EPF0_VF21_RCC_IOV_FUNC_IDENTIFIER 0xd0a83794 // addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf21_BIFPFVFDEC1 // base address: 0xd0a80000 #define cfgBIF_BX_DEV0_EPF0_VF21_BIF_BME_STATUS 0xd0a8382c #define cfgBIF_BX_DEV0_EPF0_VF21_BIF_ATOMIC_ERR_LOG 0xd0a83830 #define cfgBIF_BX_DEV0_EPF0_VF21_DOORBELL_SELFRING_GPA_APER_BASE_HIGH 0xd0a8384c #define cfgBIF_BX_DEV0_EPF0_VF21_DOORBELL_SELFRING_GPA_APER_BASE_LOW 0xd0a83850 #define cfgBIF_BX_DEV0_EPF0_VF21_DOORBELL_SELFRING_GPA_APER_CNTL 0xd0a83854 #define cfgBIF_BX_DEV0_EPF0_VF21_HDP_REG_COHERENCY_FLUSH_CNTL 0xd0a83858 #define cfgBIF_BX_DEV0_EPF0_VF21_HDP_MEM_COHERENCY_FLUSH_CNTL 0xd0a8385c #define cfgBIF_BX_DEV0_EPF0_VF21_GPU_HDP_FLUSH_REQ 0xd0a83898 #define cfgBIF_BX_DEV0_EPF0_VF21_GPU_HDP_FLUSH_DONE 0xd0a8389c #define cfgBIF_BX_DEV0_EPF0_VF21_BIF_TRANS_PENDING 0xd0a838a0 #define cfgBIF_BX_DEV0_EPF0_VF21_NBIF_GFX_ADDR_LUT_BYPASS 0xd0a838c8 #define cfgBIF_BX_DEV0_EPF0_VF21_MAILBOX_MSGBUF_TRN_DW0 0xd0a83958 #define cfgBIF_BX_DEV0_EPF0_VF21_MAILBOX_MSGBUF_TRN_DW1 0xd0a8395c #define cfgBIF_BX_DEV0_EPF0_VF21_MAILBOX_MSGBUF_TRN_DW2 0xd0a83960 #define cfgBIF_BX_DEV0_EPF0_VF21_MAILBOX_MSGBUF_TRN_DW3 0xd0a83964 #define cfgBIF_BX_DEV0_EPF0_VF21_MAILBOX_MSGBUF_RCV_DW0 0xd0a83968 #define cfgBIF_BX_DEV0_EPF0_VF21_MAILBOX_MSGBUF_RCV_DW1 0xd0a8396c #define cfgBIF_BX_DEV0_EPF0_VF21_MAILBOX_MSGBUF_RCV_DW2 0xd0a83970 #define cfgBIF_BX_DEV0_EPF0_VF21_MAILBOX_MSGBUF_RCV_DW3 0xd0a83974 #define cfgBIF_BX_DEV0_EPF0_VF21_MAILBOX_CONTROL 0xd0a83978 #define cfgBIF_BX_DEV0_EPF0_VF21_MAILBOX_INT_CNTL 0xd0a8397c #define cfgBIF_BX_DEV0_EPF0_VF21_BIF_VMHV_MAILBOX 0xd0a83980 // addressBlock: nbio_nbif0_rcc_dev0_epf0_vf21_BIFDEC2 // base address: 0xd0a80000 #define cfgRCC_DEV0_EPF0_VF21_GFXMSIX_VECT0_ADDR_LO 0xd0ac2000 #define cfgRCC_DEV0_EPF0_VF21_GFXMSIX_VECT0_ADDR_HI 0xd0ac2004 #define cfgRCC_DEV0_EPF0_VF21_GFXMSIX_VECT0_MSG_DATA 0xd0ac2008 #define cfgRCC_DEV0_EPF0_VF21_GFXMSIX_VECT0_CONTROL 0xd0ac200c #define cfgRCC_DEV0_EPF0_VF21_GFXMSIX_VECT1_ADDR_LO 0xd0ac2010 #define cfgRCC_DEV0_EPF0_VF21_GFXMSIX_VECT1_ADDR_HI 0xd0ac2014 #define cfgRCC_DEV0_EPF0_VF21_GFXMSIX_VECT1_MSG_DATA 0xd0ac2018 #define cfgRCC_DEV0_EPF0_VF21_GFXMSIX_VECT1_CONTROL 0xd0ac201c #define cfgRCC_DEV0_EPF0_VF21_GFXMSIX_VECT2_ADDR_LO 0xd0ac2020 #define cfgRCC_DEV0_EPF0_VF21_GFXMSIX_VECT2_ADDR_HI 0xd0ac2024 #define cfgRCC_DEV0_EPF0_VF21_GFXMSIX_VECT2_MSG_DATA 0xd0ac2028 #define cfgRCC_DEV0_EPF0_VF21_GFXMSIX_VECT2_CONTROL 0xd0ac202c #define cfgRCC_DEV0_EPF0_VF21_GFXMSIX_VECT3_ADDR_LO 0xd0ac2030 #define cfgRCC_DEV0_EPF0_VF21_GFXMSIX_VECT3_ADDR_HI 0xd0ac2034 #define cfgRCC_DEV0_EPF0_VF21_GFXMSIX_VECT3_MSG_DATA 0xd0ac2038 #define cfgRCC_DEV0_EPF0_VF21_GFXMSIX_VECT3_CONTROL 0xd0ac203c #define cfgRCC_DEV0_EPF0_VF21_GFXMSIX_PBA 0xd0ac3000 // addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf22_SYSPFVFDEC // base address: 0xd0b00000 #define cfgBIF_BX_DEV0_EPF0_VF22_MM_INDEX 0xd0b00000 #define cfgBIF_BX_DEV0_EPF0_VF22_MM_DATA 0xd0b00004 #define cfgBIF_BX_DEV0_EPF0_VF22_MM_INDEX_HI 0xd0b00018 // addressBlock: nbio_nbif0_rcc_dev0_epf0_vf22_BIFPFVFDEC1 // base address: 0xd0b00000 #define cfgRCC_DEV0_EPF0_VF22_RCC_ERR_LOG 0xd0b03694 #define cfgRCC_DEV0_EPF0_VF22_RCC_DOORBELL_APER_EN 0xd0b03780 #define cfgRCC_DEV0_EPF0_VF22_RCC_CONFIG_MEMSIZE 0xd0b0378c #define cfgRCC_DEV0_EPF0_VF22_RCC_CONFIG_RESERVED 0xd0b03790 #define cfgRCC_DEV0_EPF0_VF22_RCC_IOV_FUNC_IDENTIFIER 0xd0b03794 // addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf22_BIFPFVFDEC1 // base address: 0xd0b00000 #define cfgBIF_BX_DEV0_EPF0_VF22_BIF_BME_STATUS 0xd0b0382c #define cfgBIF_BX_DEV0_EPF0_VF22_BIF_ATOMIC_ERR_LOG 0xd0b03830 #define cfgBIF_BX_DEV0_EPF0_VF22_DOORBELL_SELFRING_GPA_APER_BASE_HIGH 0xd0b0384c #define cfgBIF_BX_DEV0_EPF0_VF22_DOORBELL_SELFRING_GPA_APER_BASE_LOW 0xd0b03850 #define cfgBIF_BX_DEV0_EPF0_VF22_DOORBELL_SELFRING_GPA_APER_CNTL 0xd0b03854 #define cfgBIF_BX_DEV0_EPF0_VF22_HDP_REG_COHERENCY_FLUSH_CNTL 0xd0b03858 #define cfgBIF_BX_DEV0_EPF0_VF22_HDP_MEM_COHERENCY_FLUSH_CNTL 0xd0b0385c #define cfgBIF_BX_DEV0_EPF0_VF22_GPU_HDP_FLUSH_REQ 0xd0b03898 #define cfgBIF_BX_DEV0_EPF0_VF22_GPU_HDP_FLUSH_DONE 0xd0b0389c #define cfgBIF_BX_DEV0_EPF0_VF22_BIF_TRANS_PENDING 0xd0b038a0 #define cfgBIF_BX_DEV0_EPF0_VF22_NBIF_GFX_ADDR_LUT_BYPASS 0xd0b038c8 #define cfgBIF_BX_DEV0_EPF0_VF22_MAILBOX_MSGBUF_TRN_DW0 0xd0b03958 #define cfgBIF_BX_DEV0_EPF0_VF22_MAILBOX_MSGBUF_TRN_DW1 0xd0b0395c #define cfgBIF_BX_DEV0_EPF0_VF22_MAILBOX_MSGBUF_TRN_DW2 0xd0b03960 #define cfgBIF_BX_DEV0_EPF0_VF22_MAILBOX_MSGBUF_TRN_DW3 0xd0b03964 #define cfgBIF_BX_DEV0_EPF0_VF22_MAILBOX_MSGBUF_RCV_DW0 0xd0b03968 #define cfgBIF_BX_DEV0_EPF0_VF22_MAILBOX_MSGBUF_RCV_DW1 0xd0b0396c #define cfgBIF_BX_DEV0_EPF0_VF22_MAILBOX_MSGBUF_RCV_DW2 0xd0b03970 #define cfgBIF_BX_DEV0_EPF0_VF22_MAILBOX_MSGBUF_RCV_DW3 0xd0b03974 #define cfgBIF_BX_DEV0_EPF0_VF22_MAILBOX_CONTROL 0xd0b03978 #define cfgBIF_BX_DEV0_EPF0_VF22_MAILBOX_INT_CNTL 0xd0b0397c #define cfgBIF_BX_DEV0_EPF0_VF22_BIF_VMHV_MAILBOX 0xd0b03980 // addressBlock: nbio_nbif0_rcc_dev0_epf0_vf22_BIFDEC2 // base address: 0xd0b00000 #define cfgRCC_DEV0_EPF0_VF22_GFXMSIX_VECT0_ADDR_LO 0xd0b42000 #define cfgRCC_DEV0_EPF0_VF22_GFXMSIX_VECT0_ADDR_HI 0xd0b42004 #define cfgRCC_DEV0_EPF0_VF22_GFXMSIX_VECT0_MSG_DATA 0xd0b42008 #define cfgRCC_DEV0_EPF0_VF22_GFXMSIX_VECT0_CONTROL 0xd0b4200c #define cfgRCC_DEV0_EPF0_VF22_GFXMSIX_VECT1_ADDR_LO 0xd0b42010 #define cfgRCC_DEV0_EPF0_VF22_GFXMSIX_VECT1_ADDR_HI 0xd0b42014 #define cfgRCC_DEV0_EPF0_VF22_GFXMSIX_VECT1_MSG_DATA 0xd0b42018 #define cfgRCC_DEV0_EPF0_VF22_GFXMSIX_VECT1_CONTROL 0xd0b4201c #define cfgRCC_DEV0_EPF0_VF22_GFXMSIX_VECT2_ADDR_LO 0xd0b42020 #define cfgRCC_DEV0_EPF0_VF22_GFXMSIX_VECT2_ADDR_HI 0xd0b42024 #define cfgRCC_DEV0_EPF0_VF22_GFXMSIX_VECT2_MSG_DATA 0xd0b42028 #define cfgRCC_DEV0_EPF0_VF22_GFXMSIX_VECT2_CONTROL 0xd0b4202c #define cfgRCC_DEV0_EPF0_VF22_GFXMSIX_VECT3_ADDR_LO 0xd0b42030 #define cfgRCC_DEV0_EPF0_VF22_GFXMSIX_VECT3_ADDR_HI 0xd0b42034 #define cfgRCC_DEV0_EPF0_VF22_GFXMSIX_VECT3_MSG_DATA 0xd0b42038 #define cfgRCC_DEV0_EPF0_VF22_GFXMSIX_VECT3_CONTROL 0xd0b4203c #define cfgRCC_DEV0_EPF0_VF22_GFXMSIX_PBA 0xd0b43000 // addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf23_SYSPFVFDEC // base address: 0xd0b80000 #define cfgBIF_BX_DEV0_EPF0_VF23_MM_INDEX 0xd0b80000 #define cfgBIF_BX_DEV0_EPF0_VF23_MM_DATA 0xd0b80004 #define cfgBIF_BX_DEV0_EPF0_VF23_MM_INDEX_HI 0xd0b80018 // addressBlock: nbio_nbif0_rcc_dev0_epf0_vf23_BIFPFVFDEC1 // base address: 0xd0b80000 #define cfgRCC_DEV0_EPF0_VF23_RCC_ERR_LOG 0xd0b83694 #define cfgRCC_DEV0_EPF0_VF23_RCC_DOORBELL_APER_EN 0xd0b83780 #define cfgRCC_DEV0_EPF0_VF23_RCC_CONFIG_MEMSIZE 0xd0b8378c #define cfgRCC_DEV0_EPF0_VF23_RCC_CONFIG_RESERVED 0xd0b83790 #define cfgRCC_DEV0_EPF0_VF23_RCC_IOV_FUNC_IDENTIFIER 0xd0b83794 // addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf23_BIFPFVFDEC1 // base address: 0xd0b80000 #define cfgBIF_BX_DEV0_EPF0_VF23_BIF_BME_STATUS 0xd0b8382c #define cfgBIF_BX_DEV0_EPF0_VF23_BIF_ATOMIC_ERR_LOG 0xd0b83830 #define cfgBIF_BX_DEV0_EPF0_VF23_DOORBELL_SELFRING_GPA_APER_BASE_HIGH 0xd0b8384c #define cfgBIF_BX_DEV0_EPF0_VF23_DOORBELL_SELFRING_GPA_APER_BASE_LOW 0xd0b83850 #define cfgBIF_BX_DEV0_EPF0_VF23_DOORBELL_SELFRING_GPA_APER_CNTL 0xd0b83854 #define cfgBIF_BX_DEV0_EPF0_VF23_HDP_REG_COHERENCY_FLUSH_CNTL 0xd0b83858 #define cfgBIF_BX_DEV0_EPF0_VF23_HDP_MEM_COHERENCY_FLUSH_CNTL 0xd0b8385c #define cfgBIF_BX_DEV0_EPF0_VF23_GPU_HDP_FLUSH_REQ 0xd0b83898 #define cfgBIF_BX_DEV0_EPF0_VF23_GPU_HDP_FLUSH_DONE 0xd0b8389c #define cfgBIF_BX_DEV0_EPF0_VF23_BIF_TRANS_PENDING 0xd0b838a0 #define cfgBIF_BX_DEV0_EPF0_VF23_NBIF_GFX_ADDR_LUT_BYPASS 0xd0b838c8 #define cfgBIF_BX_DEV0_EPF0_VF23_MAILBOX_MSGBUF_TRN_DW0 0xd0b83958 #define cfgBIF_BX_DEV0_EPF0_VF23_MAILBOX_MSGBUF_TRN_DW1 0xd0b8395c #define cfgBIF_BX_DEV0_EPF0_VF23_MAILBOX_MSGBUF_TRN_DW2 0xd0b83960 #define cfgBIF_BX_DEV0_EPF0_VF23_MAILBOX_MSGBUF_TRN_DW3 0xd0b83964 #define cfgBIF_BX_DEV0_EPF0_VF23_MAILBOX_MSGBUF_RCV_DW0 0xd0b83968 #define cfgBIF_BX_DEV0_EPF0_VF23_MAILBOX_MSGBUF_RCV_DW1 0xd0b8396c #define cfgBIF_BX_DEV0_EPF0_VF23_MAILBOX_MSGBUF_RCV_DW2 0xd0b83970 #define cfgBIF_BX_DEV0_EPF0_VF23_MAILBOX_MSGBUF_RCV_DW3 0xd0b83974 #define cfgBIF_BX_DEV0_EPF0_VF23_MAILBOX_CONTROL 0xd0b83978 #define cfgBIF_BX_DEV0_EPF0_VF23_MAILBOX_INT_CNTL 0xd0b8397c #define cfgBIF_BX_DEV0_EPF0_VF23_BIF_VMHV_MAILBOX 0xd0b83980 // addressBlock: nbio_nbif0_rcc_dev0_epf0_vf23_BIFDEC2 // base address: 0xd0b80000 #define cfgRCC_DEV0_EPF0_VF23_GFXMSIX_VECT0_ADDR_LO 0xd0bc2000 #define cfgRCC_DEV0_EPF0_VF23_GFXMSIX_VECT0_ADDR_HI 0xd0bc2004 #define cfgRCC_DEV0_EPF0_VF23_GFXMSIX_VECT0_MSG_DATA 0xd0bc2008 #define cfgRCC_DEV0_EPF0_VF23_GFXMSIX_VECT0_CONTROL 0xd0bc200c #define cfgRCC_DEV0_EPF0_VF23_GFXMSIX_VECT1_ADDR_LO 0xd0bc2010 #define cfgRCC_DEV0_EPF0_VF23_GFXMSIX_VECT1_ADDR_HI 0xd0bc2014 #define cfgRCC_DEV0_EPF0_VF23_GFXMSIX_VECT1_MSG_DATA 0xd0bc2018 #define cfgRCC_DEV0_EPF0_VF23_GFXMSIX_VECT1_CONTROL 0xd0bc201c #define cfgRCC_DEV0_EPF0_VF23_GFXMSIX_VECT2_ADDR_LO 0xd0bc2020 #define cfgRCC_DEV0_EPF0_VF23_GFXMSIX_VECT2_ADDR_HI 0xd0bc2024 #define cfgRCC_DEV0_EPF0_VF23_GFXMSIX_VECT2_MSG_DATA 0xd0bc2028 #define cfgRCC_DEV0_EPF0_VF23_GFXMSIX_VECT2_CONTROL 0xd0bc202c #define cfgRCC_DEV0_EPF0_VF23_GFXMSIX_VECT3_ADDR_LO 0xd0bc2030 #define cfgRCC_DEV0_EPF0_VF23_GFXMSIX_VECT3_ADDR_HI 0xd0bc2034 #define cfgRCC_DEV0_EPF0_VF23_GFXMSIX_VECT3_MSG_DATA 0xd0bc2038 #define cfgRCC_DEV0_EPF0_VF23_GFXMSIX_VECT3_CONTROL 0xd0bc203c #define cfgRCC_DEV0_EPF0_VF23_GFXMSIX_PBA 0xd0bc3000 // addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf24_SYSPFVFDEC // base address: 0xd0c00000 #define cfgBIF_BX_DEV0_EPF0_VF24_MM_INDEX 0xd0c00000 #define cfgBIF_BX_DEV0_EPF0_VF24_MM_DATA 0xd0c00004 #define cfgBIF_BX_DEV0_EPF0_VF24_MM_INDEX_HI 0xd0c00018 // addressBlock: nbio_nbif0_rcc_dev0_epf0_vf24_BIFPFVFDEC1 // base address: 0xd0c00000 #define cfgRCC_DEV0_EPF0_VF24_RCC_ERR_LOG 0xd0c03694 #define cfgRCC_DEV0_EPF0_VF24_RCC_DOORBELL_APER_EN 0xd0c03780 #define cfgRCC_DEV0_EPF0_VF24_RCC_CONFIG_MEMSIZE 0xd0c0378c #define cfgRCC_DEV0_EPF0_VF24_RCC_CONFIG_RESERVED 0xd0c03790 #define cfgRCC_DEV0_EPF0_VF24_RCC_IOV_FUNC_IDENTIFIER 0xd0c03794 // addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf24_BIFPFVFDEC1 // base address: 0xd0c00000 #define cfgBIF_BX_DEV0_EPF0_VF24_BIF_BME_STATUS 0xd0c0382c #define cfgBIF_BX_DEV0_EPF0_VF24_BIF_ATOMIC_ERR_LOG 0xd0c03830 #define cfgBIF_BX_DEV0_EPF0_VF24_DOORBELL_SELFRING_GPA_APER_BASE_HIGH 0xd0c0384c #define cfgBIF_BX_DEV0_EPF0_VF24_DOORBELL_SELFRING_GPA_APER_BASE_LOW 0xd0c03850 #define cfgBIF_BX_DEV0_EPF0_VF24_DOORBELL_SELFRING_GPA_APER_CNTL 0xd0c03854 #define cfgBIF_BX_DEV0_EPF0_VF24_HDP_REG_COHERENCY_FLUSH_CNTL 0xd0c03858 #define cfgBIF_BX_DEV0_EPF0_VF24_HDP_MEM_COHERENCY_FLUSH_CNTL 0xd0c0385c #define cfgBIF_BX_DEV0_EPF0_VF24_GPU_HDP_FLUSH_REQ 0xd0c03898 #define cfgBIF_BX_DEV0_EPF0_VF24_GPU_HDP_FLUSH_DONE 0xd0c0389c #define cfgBIF_BX_DEV0_EPF0_VF24_BIF_TRANS_PENDING 0xd0c038a0 #define cfgBIF_BX_DEV0_EPF0_VF24_NBIF_GFX_ADDR_LUT_BYPASS 0xd0c038c8 #define cfgBIF_BX_DEV0_EPF0_VF24_MAILBOX_MSGBUF_TRN_DW0 0xd0c03958 #define cfgBIF_BX_DEV0_EPF0_VF24_MAILBOX_MSGBUF_TRN_DW1 0xd0c0395c #define cfgBIF_BX_DEV0_EPF0_VF24_MAILBOX_MSGBUF_TRN_DW2 0xd0c03960 #define cfgBIF_BX_DEV0_EPF0_VF24_MAILBOX_MSGBUF_TRN_DW3 0xd0c03964 #define cfgBIF_BX_DEV0_EPF0_VF24_MAILBOX_MSGBUF_RCV_DW0 0xd0c03968 #define cfgBIF_BX_DEV0_EPF0_VF24_MAILBOX_MSGBUF_RCV_DW1 0xd0c0396c #define cfgBIF_BX_DEV0_EPF0_VF24_MAILBOX_MSGBUF_RCV_DW2 0xd0c03970 #define cfgBIF_BX_DEV0_EPF0_VF24_MAILBOX_MSGBUF_RCV_DW3 0xd0c03974 #define cfgBIF_BX_DEV0_EPF0_VF24_MAILBOX_CONTROL 0xd0c03978 #define cfgBIF_BX_DEV0_EPF0_VF24_MAILBOX_INT_CNTL 0xd0c0397c #define cfgBIF_BX_DEV0_EPF0_VF24_BIF_VMHV_MAILBOX 0xd0c03980 // addressBlock: nbio_nbif0_rcc_dev0_epf0_vf24_BIFDEC2 // base address: 0xd0c00000 #define cfgRCC_DEV0_EPF0_VF24_GFXMSIX_VECT0_ADDR_LO 0xd0c42000 #define cfgRCC_DEV0_EPF0_VF24_GFXMSIX_VECT0_ADDR_HI 0xd0c42004 #define cfgRCC_DEV0_EPF0_VF24_GFXMSIX_VECT0_MSG_DATA 0xd0c42008 #define cfgRCC_DEV0_EPF0_VF24_GFXMSIX_VECT0_CONTROL 0xd0c4200c #define cfgRCC_DEV0_EPF0_VF24_GFXMSIX_VECT1_ADDR_LO 0xd0c42010 #define cfgRCC_DEV0_EPF0_VF24_GFXMSIX_VECT1_ADDR_HI 0xd0c42014 #define cfgRCC_DEV0_EPF0_VF24_GFXMSIX_VECT1_MSG_DATA 0xd0c42018 #define cfgRCC_DEV0_EPF0_VF24_GFXMSIX_VECT1_CONTROL 0xd0c4201c #define cfgRCC_DEV0_EPF0_VF24_GFXMSIX_VECT2_ADDR_LO 0xd0c42020 #define cfgRCC_DEV0_EPF0_VF24_GFXMSIX_VECT2_ADDR_HI 0xd0c42024 #define cfgRCC_DEV0_EPF0_VF24_GFXMSIX_VECT2_MSG_DATA 0xd0c42028 #define cfgRCC_DEV0_EPF0_VF24_GFXMSIX_VECT2_CONTROL 0xd0c4202c #define cfgRCC_DEV0_EPF0_VF24_GFXMSIX_VECT3_ADDR_LO 0xd0c42030 #define cfgRCC_DEV0_EPF0_VF24_GFXMSIX_VECT3_ADDR_HI 0xd0c42034 #define cfgRCC_DEV0_EPF0_VF24_GFXMSIX_VECT3_MSG_DATA 0xd0c42038 #define cfgRCC_DEV0_EPF0_VF24_GFXMSIX_VECT3_CONTROL 0xd0c4203c #define cfgRCC_DEV0_EPF0_VF24_GFXMSIX_PBA 0xd0c43000 // addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf25_SYSPFVFDEC // base address: 0xd0c80000 #define cfgBIF_BX_DEV0_EPF0_VF25_MM_INDEX 0xd0c80000 #define cfgBIF_BX_DEV0_EPF0_VF25_MM_DATA 0xd0c80004 #define cfgBIF_BX_DEV0_EPF0_VF25_MM_INDEX_HI 0xd0c80018 // addressBlock: nbio_nbif0_rcc_dev0_epf0_vf25_BIFPFVFDEC1 // base address: 0xd0c80000 #define cfgRCC_DEV0_EPF0_VF25_RCC_ERR_LOG 0xd0c83694 #define cfgRCC_DEV0_EPF0_VF25_RCC_DOORBELL_APER_EN 0xd0c83780 #define cfgRCC_DEV0_EPF0_VF25_RCC_CONFIG_MEMSIZE 0xd0c8378c #define cfgRCC_DEV0_EPF0_VF25_RCC_CONFIG_RESERVED 0xd0c83790 #define cfgRCC_DEV0_EPF0_VF25_RCC_IOV_FUNC_IDENTIFIER 0xd0c83794 // addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf25_BIFPFVFDEC1 // base address: 0xd0c80000 #define cfgBIF_BX_DEV0_EPF0_VF25_BIF_BME_STATUS 0xd0c8382c #define cfgBIF_BX_DEV0_EPF0_VF25_BIF_ATOMIC_ERR_LOG 0xd0c83830 #define cfgBIF_BX_DEV0_EPF0_VF25_DOORBELL_SELFRING_GPA_APER_BASE_HIGH 0xd0c8384c #define cfgBIF_BX_DEV0_EPF0_VF25_DOORBELL_SELFRING_GPA_APER_BASE_LOW 0xd0c83850 #define cfgBIF_BX_DEV0_EPF0_VF25_DOORBELL_SELFRING_GPA_APER_CNTL 0xd0c83854 #define cfgBIF_BX_DEV0_EPF0_VF25_HDP_REG_COHERENCY_FLUSH_CNTL 0xd0c83858 #define cfgBIF_BX_DEV0_EPF0_VF25_HDP_MEM_COHERENCY_FLUSH_CNTL 0xd0c8385c #define cfgBIF_BX_DEV0_EPF0_VF25_GPU_HDP_FLUSH_REQ 0xd0c83898 #define cfgBIF_BX_DEV0_EPF0_VF25_GPU_HDP_FLUSH_DONE 0xd0c8389c #define cfgBIF_BX_DEV0_EPF0_VF25_BIF_TRANS_PENDING 0xd0c838a0 #define cfgBIF_BX_DEV0_EPF0_VF25_NBIF_GFX_ADDR_LUT_BYPASS 0xd0c838c8 #define cfgBIF_BX_DEV0_EPF0_VF25_MAILBOX_MSGBUF_TRN_DW0 0xd0c83958 #define cfgBIF_BX_DEV0_EPF0_VF25_MAILBOX_MSGBUF_TRN_DW1 0xd0c8395c #define cfgBIF_BX_DEV0_EPF0_VF25_MAILBOX_MSGBUF_TRN_DW2 0xd0c83960 #define cfgBIF_BX_DEV0_EPF0_VF25_MAILBOX_MSGBUF_TRN_DW3 0xd0c83964 #define cfgBIF_BX_DEV0_EPF0_VF25_MAILBOX_MSGBUF_RCV_DW0 0xd0c83968 #define cfgBIF_BX_DEV0_EPF0_VF25_MAILBOX_MSGBUF_RCV_DW1 0xd0c8396c #define cfgBIF_BX_DEV0_EPF0_VF25_MAILBOX_MSGBUF_RCV_DW2 0xd0c83970 #define cfgBIF_BX_DEV0_EPF0_VF25_MAILBOX_MSGBUF_RCV_DW3 0xd0c83974 #define cfgBIF_BX_DEV0_EPF0_VF25_MAILBOX_CONTROL 0xd0c83978 #define cfgBIF_BX_DEV0_EPF0_VF25_MAILBOX_INT_CNTL 0xd0c8397c #define cfgBIF_BX_DEV0_EPF0_VF25_BIF_VMHV_MAILBOX 0xd0c83980 // addressBlock: nbio_nbif0_rcc_dev0_epf0_vf25_BIFDEC2 // base address: 0xd0c80000 #define cfgRCC_DEV0_EPF0_VF25_GFXMSIX_VECT0_ADDR_LO 0xd0cc2000 #define cfgRCC_DEV0_EPF0_VF25_GFXMSIX_VECT0_ADDR_HI 0xd0cc2004 #define cfgRCC_DEV0_EPF0_VF25_GFXMSIX_VECT0_MSG_DATA 0xd0cc2008 #define cfgRCC_DEV0_EPF0_VF25_GFXMSIX_VECT0_CONTROL 0xd0cc200c #define cfgRCC_DEV0_EPF0_VF25_GFXMSIX_VECT1_ADDR_LO 0xd0cc2010 #define cfgRCC_DEV0_EPF0_VF25_GFXMSIX_VECT1_ADDR_HI 0xd0cc2014 #define cfgRCC_DEV0_EPF0_VF25_GFXMSIX_VECT1_MSG_DATA 0xd0cc2018 #define cfgRCC_DEV0_EPF0_VF25_GFXMSIX_VECT1_CONTROL 0xd0cc201c #define cfgRCC_DEV0_EPF0_VF25_GFXMSIX_VECT2_ADDR_LO 0xd0cc2020 #define cfgRCC_DEV0_EPF0_VF25_GFXMSIX_VECT2_ADDR_HI 0xd0cc2024 #define cfgRCC_DEV0_EPF0_VF25_GFXMSIX_VECT2_MSG_DATA 0xd0cc2028 #define cfgRCC_DEV0_EPF0_VF25_GFXMSIX_VECT2_CONTROL 0xd0cc202c #define cfgRCC_DEV0_EPF0_VF25_GFXMSIX_VECT3_ADDR_LO 0xd0cc2030 #define cfgRCC_DEV0_EPF0_VF25_GFXMSIX_VECT3_ADDR_HI 0xd0cc2034 #define cfgRCC_DEV0_EPF0_VF25_GFXMSIX_VECT3_MSG_DATA 0xd0cc2038 #define cfgRCC_DEV0_EPF0_VF25_GFXMSIX_VECT3_CONTROL 0xd0cc203c #define cfgRCC_DEV0_EPF0_VF25_GFXMSIX_PBA 0xd0cc3000 // addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf26_SYSPFVFDEC // base address: 0xd0d00000 #define cfgBIF_BX_DEV0_EPF0_VF26_MM_INDEX 0xd0d00000 #define cfgBIF_BX_DEV0_EPF0_VF26_MM_DATA 0xd0d00004 #define cfgBIF_BX_DEV0_EPF0_VF26_MM_INDEX_HI 0xd0d00018 // addressBlock: nbio_nbif0_rcc_dev0_epf0_vf26_BIFPFVFDEC1 // base address: 0xd0d00000 #define cfgRCC_DEV0_EPF0_VF26_RCC_ERR_LOG 0xd0d03694 #define cfgRCC_DEV0_EPF0_VF26_RCC_DOORBELL_APER_EN 0xd0d03780 #define cfgRCC_DEV0_EPF0_VF26_RCC_CONFIG_MEMSIZE 0xd0d0378c #define cfgRCC_DEV0_EPF0_VF26_RCC_CONFIG_RESERVED 0xd0d03790 #define cfgRCC_DEV0_EPF0_VF26_RCC_IOV_FUNC_IDENTIFIER 0xd0d03794 // addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf26_BIFPFVFDEC1 // base address: 0xd0d00000 #define cfgBIF_BX_DEV0_EPF0_VF26_BIF_BME_STATUS 0xd0d0382c #define cfgBIF_BX_DEV0_EPF0_VF26_BIF_ATOMIC_ERR_LOG 0xd0d03830 #define cfgBIF_BX_DEV0_EPF0_VF26_DOORBELL_SELFRING_GPA_APER_BASE_HIGH 0xd0d0384c #define cfgBIF_BX_DEV0_EPF0_VF26_DOORBELL_SELFRING_GPA_APER_BASE_LOW 0xd0d03850 #define cfgBIF_BX_DEV0_EPF0_VF26_DOORBELL_SELFRING_GPA_APER_CNTL 0xd0d03854 #define cfgBIF_BX_DEV0_EPF0_VF26_HDP_REG_COHERENCY_FLUSH_CNTL 0xd0d03858 #define cfgBIF_BX_DEV0_EPF0_VF26_HDP_MEM_COHERENCY_FLUSH_CNTL 0xd0d0385c #define cfgBIF_BX_DEV0_EPF0_VF26_GPU_HDP_FLUSH_REQ 0xd0d03898 #define cfgBIF_BX_DEV0_EPF0_VF26_GPU_HDP_FLUSH_DONE 0xd0d0389c #define cfgBIF_BX_DEV0_EPF0_VF26_BIF_TRANS_PENDING 0xd0d038a0 #define cfgBIF_BX_DEV0_EPF0_VF26_NBIF_GFX_ADDR_LUT_BYPASS 0xd0d038c8 #define cfgBIF_BX_DEV0_EPF0_VF26_MAILBOX_MSGBUF_TRN_DW0 0xd0d03958 #define cfgBIF_BX_DEV0_EPF0_VF26_MAILBOX_MSGBUF_TRN_DW1 0xd0d0395c #define cfgBIF_BX_DEV0_EPF0_VF26_MAILBOX_MSGBUF_TRN_DW2 0xd0d03960 #define cfgBIF_BX_DEV0_EPF0_VF26_MAILBOX_MSGBUF_TRN_DW3 0xd0d03964 #define cfgBIF_BX_DEV0_EPF0_VF26_MAILBOX_MSGBUF_RCV_DW0 0xd0d03968 #define cfgBIF_BX_DEV0_EPF0_VF26_MAILBOX_MSGBUF_RCV_DW1 0xd0d0396c #define cfgBIF_BX_DEV0_EPF0_VF26_MAILBOX_MSGBUF_RCV_DW2 0xd0d03970 #define cfgBIF_BX_DEV0_EPF0_VF26_MAILBOX_MSGBUF_RCV_DW3 0xd0d03974 #define cfgBIF_BX_DEV0_EPF0_VF26_MAILBOX_CONTROL 0xd0d03978 #define cfgBIF_BX_DEV0_EPF0_VF26_MAILBOX_INT_CNTL 0xd0d0397c #define cfgBIF_BX_DEV0_EPF0_VF26_BIF_VMHV_MAILBOX 0xd0d03980 // addressBlock: nbio_nbif0_rcc_dev0_epf0_vf26_BIFDEC2 // base address: 0xd0d00000 #define cfgRCC_DEV0_EPF0_VF26_GFXMSIX_VECT0_ADDR_LO 0xd0d42000 #define cfgRCC_DEV0_EPF0_VF26_GFXMSIX_VECT0_ADDR_HI 0xd0d42004 #define cfgRCC_DEV0_EPF0_VF26_GFXMSIX_VECT0_MSG_DATA 0xd0d42008 #define cfgRCC_DEV0_EPF0_VF26_GFXMSIX_VECT0_CONTROL 0xd0d4200c #define cfgRCC_DEV0_EPF0_VF26_GFXMSIX_VECT1_ADDR_LO 0xd0d42010 #define cfgRCC_DEV0_EPF0_VF26_GFXMSIX_VECT1_ADDR_HI 0xd0d42014 #define cfgRCC_DEV0_EPF0_VF26_GFXMSIX_VECT1_MSG_DATA 0xd0d42018 #define cfgRCC_DEV0_EPF0_VF26_GFXMSIX_VECT1_CONTROL 0xd0d4201c #define cfgRCC_DEV0_EPF0_VF26_GFXMSIX_VECT2_ADDR_LO 0xd0d42020 #define cfgRCC_DEV0_EPF0_VF26_GFXMSIX_VECT2_ADDR_HI 0xd0d42024 #define cfgRCC_DEV0_EPF0_VF26_GFXMSIX_VECT2_MSG_DATA 0xd0d42028 #define cfgRCC_DEV0_EPF0_VF26_GFXMSIX_VECT2_CONTROL 0xd0d4202c #define cfgRCC_DEV0_EPF0_VF26_GFXMSIX_VECT3_ADDR_LO 0xd0d42030 #define cfgRCC_DEV0_EPF0_VF26_GFXMSIX_VECT3_ADDR_HI 0xd0d42034 #define cfgRCC_DEV0_EPF0_VF26_GFXMSIX_VECT3_MSG_DATA 0xd0d42038 #define cfgRCC_DEV0_EPF0_VF26_GFXMSIX_VECT3_CONTROL 0xd0d4203c #define cfgRCC_DEV0_EPF0_VF26_GFXMSIX_PBA 0xd0d43000 // addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf27_SYSPFVFDEC // base address: 0xd0d80000 #define cfgBIF_BX_DEV0_EPF0_VF27_MM_INDEX 0xd0d80000 #define cfgBIF_BX_DEV0_EPF0_VF27_MM_DATA 0xd0d80004 #define cfgBIF_BX_DEV0_EPF0_VF27_MM_INDEX_HI 0xd0d80018 // addressBlock: nbio_nbif0_rcc_dev0_epf0_vf27_BIFPFVFDEC1 // base address: 0xd0d80000 #define cfgRCC_DEV0_EPF0_VF27_RCC_ERR_LOG 0xd0d83694 #define cfgRCC_DEV0_EPF0_VF27_RCC_DOORBELL_APER_EN 0xd0d83780 #define cfgRCC_DEV0_EPF0_VF27_RCC_CONFIG_MEMSIZE 0xd0d8378c #define cfgRCC_DEV0_EPF0_VF27_RCC_CONFIG_RESERVED 0xd0d83790 #define cfgRCC_DEV0_EPF0_VF27_RCC_IOV_FUNC_IDENTIFIER 0xd0d83794 // addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf27_BIFPFVFDEC1 // base address: 0xd0d80000 #define cfgBIF_BX_DEV0_EPF0_VF27_BIF_BME_STATUS 0xd0d8382c #define cfgBIF_BX_DEV0_EPF0_VF27_BIF_ATOMIC_ERR_LOG 0xd0d83830 #define cfgBIF_BX_DEV0_EPF0_VF27_DOORBELL_SELFRING_GPA_APER_BASE_HIGH 0xd0d8384c #define cfgBIF_BX_DEV0_EPF0_VF27_DOORBELL_SELFRING_GPA_APER_BASE_LOW 0xd0d83850 #define cfgBIF_BX_DEV0_EPF0_VF27_DOORBELL_SELFRING_GPA_APER_CNTL 0xd0d83854 #define cfgBIF_BX_DEV0_EPF0_VF27_HDP_REG_COHERENCY_FLUSH_CNTL 0xd0d83858 #define cfgBIF_BX_DEV0_EPF0_VF27_HDP_MEM_COHERENCY_FLUSH_CNTL 0xd0d8385c #define cfgBIF_BX_DEV0_EPF0_VF27_GPU_HDP_FLUSH_REQ 0xd0d83898 #define cfgBIF_BX_DEV0_EPF0_VF27_GPU_HDP_FLUSH_DONE 0xd0d8389c #define cfgBIF_BX_DEV0_EPF0_VF27_BIF_TRANS_PENDING 0xd0d838a0 #define cfgBIF_BX_DEV0_EPF0_VF27_NBIF_GFX_ADDR_LUT_BYPASS 0xd0d838c8 #define cfgBIF_BX_DEV0_EPF0_VF27_MAILBOX_MSGBUF_TRN_DW0 0xd0d83958 #define cfgBIF_BX_DEV0_EPF0_VF27_MAILBOX_MSGBUF_TRN_DW1 0xd0d8395c #define cfgBIF_BX_DEV0_EPF0_VF27_MAILBOX_MSGBUF_TRN_DW2 0xd0d83960 #define cfgBIF_BX_DEV0_EPF0_VF27_MAILBOX_MSGBUF_TRN_DW3 0xd0d83964 #define cfgBIF_BX_DEV0_EPF0_VF27_MAILBOX_MSGBUF_RCV_DW0 0xd0d83968 #define cfgBIF_BX_DEV0_EPF0_VF27_MAILBOX_MSGBUF_RCV_DW1 0xd0d8396c #define cfgBIF_BX_DEV0_EPF0_VF27_MAILBOX_MSGBUF_RCV_DW2 0xd0d83970 #define cfgBIF_BX_DEV0_EPF0_VF27_MAILBOX_MSGBUF_RCV_DW3 0xd0d83974 #define cfgBIF_BX_DEV0_EPF0_VF27_MAILBOX_CONTROL 0xd0d83978 #define cfgBIF_BX_DEV0_EPF0_VF27_MAILBOX_INT_CNTL 0xd0d8397c #define cfgBIF_BX_DEV0_EPF0_VF27_BIF_VMHV_MAILBOX 0xd0d83980 // addressBlock: nbio_nbif0_rcc_dev0_epf0_vf27_BIFDEC2 // base address: 0xd0d80000 #define cfgRCC_DEV0_EPF0_VF27_GFXMSIX_VECT0_ADDR_LO 0xd0dc2000 #define cfgRCC_DEV0_EPF0_VF27_GFXMSIX_VECT0_ADDR_HI 0xd0dc2004 #define cfgRCC_DEV0_EPF0_VF27_GFXMSIX_VECT0_MSG_DATA 0xd0dc2008 #define cfgRCC_DEV0_EPF0_VF27_GFXMSIX_VECT0_CONTROL 0xd0dc200c #define cfgRCC_DEV0_EPF0_VF27_GFXMSIX_VECT1_ADDR_LO 0xd0dc2010 #define cfgRCC_DEV0_EPF0_VF27_GFXMSIX_VECT1_ADDR_HI 0xd0dc2014 #define cfgRCC_DEV0_EPF0_VF27_GFXMSIX_VECT1_MSG_DATA 0xd0dc2018 #define cfgRCC_DEV0_EPF0_VF27_GFXMSIX_VECT1_CONTROL 0xd0dc201c #define cfgRCC_DEV0_EPF0_VF27_GFXMSIX_VECT2_ADDR_LO 0xd0dc2020 #define cfgRCC_DEV0_EPF0_VF27_GFXMSIX_VECT2_ADDR_HI 0xd0dc2024 #define cfgRCC_DEV0_EPF0_VF27_GFXMSIX_VECT2_MSG_DATA 0xd0dc2028 #define cfgRCC_DEV0_EPF0_VF27_GFXMSIX_VECT2_CONTROL 0xd0dc202c #define cfgRCC_DEV0_EPF0_VF27_GFXMSIX_VECT3_ADDR_LO 0xd0dc2030 #define cfgRCC_DEV0_EPF0_VF27_GFXMSIX_VECT3_ADDR_HI 0xd0dc2034 #define cfgRCC_DEV0_EPF0_VF27_GFXMSIX_VECT3_MSG_DATA 0xd0dc2038 #define cfgRCC_DEV0_EPF0_VF27_GFXMSIX_VECT3_CONTROL 0xd0dc203c #define cfgRCC_DEV0_EPF0_VF27_GFXMSIX_PBA 0xd0dc3000 // addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf28_SYSPFVFDEC // base address: 0xd0e00000 #define cfgBIF_BX_DEV0_EPF0_VF28_MM_INDEX 0xd0e00000 #define cfgBIF_BX_DEV0_EPF0_VF28_MM_DATA 0xd0e00004 #define cfgBIF_BX_DEV0_EPF0_VF28_MM_INDEX_HI 0xd0e00018 // addressBlock: nbio_nbif0_rcc_dev0_epf0_vf28_BIFPFVFDEC1 // base address: 0xd0e00000 #define cfgRCC_DEV0_EPF0_VF28_RCC_ERR_LOG 0xd0e03694 #define cfgRCC_DEV0_EPF0_VF28_RCC_DOORBELL_APER_EN 0xd0e03780 #define cfgRCC_DEV0_EPF0_VF28_RCC_CONFIG_MEMSIZE 0xd0e0378c #define cfgRCC_DEV0_EPF0_VF28_RCC_CONFIG_RESERVED 0xd0e03790 #define cfgRCC_DEV0_EPF0_VF28_RCC_IOV_FUNC_IDENTIFIER 0xd0e03794 // addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf28_BIFPFVFDEC1 // base address: 0xd0e00000 #define cfgBIF_BX_DEV0_EPF0_VF28_BIF_BME_STATUS 0xd0e0382c #define cfgBIF_BX_DEV0_EPF0_VF28_BIF_ATOMIC_ERR_LOG 0xd0e03830 #define cfgBIF_BX_DEV0_EPF0_VF28_DOORBELL_SELFRING_GPA_APER_BASE_HIGH 0xd0e0384c #define cfgBIF_BX_DEV0_EPF0_VF28_DOORBELL_SELFRING_GPA_APER_BASE_LOW 0xd0e03850 #define cfgBIF_BX_DEV0_EPF0_VF28_DOORBELL_SELFRING_GPA_APER_CNTL 0xd0e03854 #define cfgBIF_BX_DEV0_EPF0_VF28_HDP_REG_COHERENCY_FLUSH_CNTL 0xd0e03858 #define cfgBIF_BX_DEV0_EPF0_VF28_HDP_MEM_COHERENCY_FLUSH_CNTL 0xd0e0385c #define cfgBIF_BX_DEV0_EPF0_VF28_GPU_HDP_FLUSH_REQ 0xd0e03898 #define cfgBIF_BX_DEV0_EPF0_VF28_GPU_HDP_FLUSH_DONE 0xd0e0389c #define cfgBIF_BX_DEV0_EPF0_VF28_BIF_TRANS_PENDING 0xd0e038a0 #define cfgBIF_BX_DEV0_EPF0_VF28_NBIF_GFX_ADDR_LUT_BYPASS 0xd0e038c8 #define cfgBIF_BX_DEV0_EPF0_VF28_MAILBOX_MSGBUF_TRN_DW0 0xd0e03958 #define cfgBIF_BX_DEV0_EPF0_VF28_MAILBOX_MSGBUF_TRN_DW1 0xd0e0395c #define cfgBIF_BX_DEV0_EPF0_VF28_MAILBOX_MSGBUF_TRN_DW2 0xd0e03960 #define cfgBIF_BX_DEV0_EPF0_VF28_MAILBOX_MSGBUF_TRN_DW3 0xd0e03964 #define cfgBIF_BX_DEV0_EPF0_VF28_MAILBOX_MSGBUF_RCV_DW0 0xd0e03968 #define cfgBIF_BX_DEV0_EPF0_VF28_MAILBOX_MSGBUF_RCV_DW1 0xd0e0396c #define cfgBIF_BX_DEV0_EPF0_VF28_MAILBOX_MSGBUF_RCV_DW2 0xd0e03970 #define cfgBIF_BX_DEV0_EPF0_VF28_MAILBOX_MSGBUF_RCV_DW3 0xd0e03974 #define cfgBIF_BX_DEV0_EPF0_VF28_MAILBOX_CONTROL 0xd0e03978 #define cfgBIF_BX_DEV0_EPF0_VF28_MAILBOX_INT_CNTL 0xd0e0397c #define cfgBIF_BX_DEV0_EPF0_VF28_BIF_VMHV_MAILBOX 0xd0e03980 // addressBlock: nbio_nbif0_rcc_dev0_epf0_vf28_BIFDEC2 // base address: 0xd0e00000 #define cfgRCC_DEV0_EPF0_VF28_GFXMSIX_VECT0_ADDR_LO 0xd0e42000 #define cfgRCC_DEV0_EPF0_VF28_GFXMSIX_VECT0_ADDR_HI 0xd0e42004 #define cfgRCC_DEV0_EPF0_VF28_GFXMSIX_VECT0_MSG_DATA 0xd0e42008 #define cfgRCC_DEV0_EPF0_VF28_GFXMSIX_VECT0_CONTROL 0xd0e4200c #define cfgRCC_DEV0_EPF0_VF28_GFXMSIX_VECT1_ADDR_LO 0xd0e42010 #define cfgRCC_DEV0_EPF0_VF28_GFXMSIX_VECT1_ADDR_HI 0xd0e42014 #define cfgRCC_DEV0_EPF0_VF28_GFXMSIX_VECT1_MSG_DATA 0xd0e42018 #define cfgRCC_DEV0_EPF0_VF28_GFXMSIX_VECT1_CONTROL 0xd0e4201c #define cfgRCC_DEV0_EPF0_VF28_GFXMSIX_VECT2_ADDR_LO 0xd0e42020 #define cfgRCC_DEV0_EPF0_VF28_GFXMSIX_VECT2_ADDR_HI 0xd0e42024 #define cfgRCC_DEV0_EPF0_VF28_GFXMSIX_VECT2_MSG_DATA 0xd0e42028 #define cfgRCC_DEV0_EPF0_VF28_GFXMSIX_VECT2_CONTROL 0xd0e4202c #define cfgRCC_DEV0_EPF0_VF28_GFXMSIX_VECT3_ADDR_LO 0xd0e42030 #define cfgRCC_DEV0_EPF0_VF28_GFXMSIX_VECT3_ADDR_HI 0xd0e42034 #define cfgRCC_DEV0_EPF0_VF28_GFXMSIX_VECT3_MSG_DATA 0xd0e42038 #define cfgRCC_DEV0_EPF0_VF28_GFXMSIX_VECT3_CONTROL 0xd0e4203c #define cfgRCC_DEV0_EPF0_VF28_GFXMSIX_PBA 0xd0e43000 // addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf29_SYSPFVFDEC // base address: 0xd0e80000 #define cfgBIF_BX_DEV0_EPF0_VF29_MM_INDEX 0xd0e80000 #define cfgBIF_BX_DEV0_EPF0_VF29_MM_DATA 0xd0e80004 #define cfgBIF_BX_DEV0_EPF0_VF29_MM_INDEX_HI 0xd0e80018 // addressBlock: nbio_nbif0_rcc_dev0_epf0_vf29_BIFPFVFDEC1 // base address: 0xd0e80000 #define cfgRCC_DEV0_EPF0_VF29_RCC_ERR_LOG 0xd0e83694 #define cfgRCC_DEV0_EPF0_VF29_RCC_DOORBELL_APER_EN 0xd0e83780 #define cfgRCC_DEV0_EPF0_VF29_RCC_CONFIG_MEMSIZE 0xd0e8378c #define cfgRCC_DEV0_EPF0_VF29_RCC_CONFIG_RESERVED 0xd0e83790 #define cfgRCC_DEV0_EPF0_VF29_RCC_IOV_FUNC_IDENTIFIER 0xd0e83794 // addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf29_BIFPFVFDEC1 // base address: 0xd0e80000 #define cfgBIF_BX_DEV0_EPF0_VF29_BIF_BME_STATUS 0xd0e8382c #define cfgBIF_BX_DEV0_EPF0_VF29_BIF_ATOMIC_ERR_LOG 0xd0e83830 #define cfgBIF_BX_DEV0_EPF0_VF29_DOORBELL_SELFRING_GPA_APER_BASE_HIGH 0xd0e8384c #define cfgBIF_BX_DEV0_EPF0_VF29_DOORBELL_SELFRING_GPA_APER_BASE_LOW 0xd0e83850 #define cfgBIF_BX_DEV0_EPF0_VF29_DOORBELL_SELFRING_GPA_APER_CNTL 0xd0e83854 #define cfgBIF_BX_DEV0_EPF0_VF29_HDP_REG_COHERENCY_FLUSH_CNTL 0xd0e83858 #define cfgBIF_BX_DEV0_EPF0_VF29_HDP_MEM_COHERENCY_FLUSH_CNTL 0xd0e8385c #define cfgBIF_BX_DEV0_EPF0_VF29_GPU_HDP_FLUSH_REQ 0xd0e83898 #define cfgBIF_BX_DEV0_EPF0_VF29_GPU_HDP_FLUSH_DONE 0xd0e8389c #define cfgBIF_BX_DEV0_EPF0_VF29_BIF_TRANS_PENDING 0xd0e838a0 #define cfgBIF_BX_DEV0_EPF0_VF29_NBIF_GFX_ADDR_LUT_BYPASS 0xd0e838c8 #define cfgBIF_BX_DEV0_EPF0_VF29_MAILBOX_MSGBUF_TRN_DW0 0xd0e83958 #define cfgBIF_BX_DEV0_EPF0_VF29_MAILBOX_MSGBUF_TRN_DW1 0xd0e8395c #define cfgBIF_BX_DEV0_EPF0_VF29_MAILBOX_MSGBUF_TRN_DW2 0xd0e83960 #define cfgBIF_BX_DEV0_EPF0_VF29_MAILBOX_MSGBUF_TRN_DW3 0xd0e83964 #define cfgBIF_BX_DEV0_EPF0_VF29_MAILBOX_MSGBUF_RCV_DW0 0xd0e83968 #define cfgBIF_BX_DEV0_EPF0_VF29_MAILBOX_MSGBUF_RCV_DW1 0xd0e8396c #define cfgBIF_BX_DEV0_EPF0_VF29_MAILBOX_MSGBUF_RCV_DW2 0xd0e83970 #define cfgBIF_BX_DEV0_EPF0_VF29_MAILBOX_MSGBUF_RCV_DW3 0xd0e83974 #define cfgBIF_BX_DEV0_EPF0_VF29_MAILBOX_CONTROL 0xd0e83978 #define cfgBIF_BX_DEV0_EPF0_VF29_MAILBOX_INT_CNTL 0xd0e8397c #define cfgBIF_BX_DEV0_EPF0_VF29_BIF_VMHV_MAILBOX 0xd0e83980 // addressBlock: nbio_nbif0_rcc_dev0_epf0_vf29_BIFDEC2 // base address: 0xd0e80000 #define cfgRCC_DEV0_EPF0_VF29_GFXMSIX_VECT0_ADDR_LO 0xd0ec2000 #define cfgRCC_DEV0_EPF0_VF29_GFXMSIX_VECT0_ADDR_HI 0xd0ec2004 #define cfgRCC_DEV0_EPF0_VF29_GFXMSIX_VECT0_MSG_DATA 0xd0ec2008 #define cfgRCC_DEV0_EPF0_VF29_GFXMSIX_VECT0_CONTROL 0xd0ec200c #define cfgRCC_DEV0_EPF0_VF29_GFXMSIX_VECT1_ADDR_LO 0xd0ec2010 #define cfgRCC_DEV0_EPF0_VF29_GFXMSIX_VECT1_ADDR_HI 0xd0ec2014 #define cfgRCC_DEV0_EPF0_VF29_GFXMSIX_VECT1_MSG_DATA 0xd0ec2018 #define cfgRCC_DEV0_EPF0_VF29_GFXMSIX_VECT1_CONTROL 0xd0ec201c #define cfgRCC_DEV0_EPF0_VF29_GFXMSIX_VECT2_ADDR_LO 0xd0ec2020 #define cfgRCC_DEV0_EPF0_VF29_GFXMSIX_VECT2_ADDR_HI 0xd0ec2024 #define cfgRCC_DEV0_EPF0_VF29_GFXMSIX_VECT2_MSG_DATA 0xd0ec2028 #define cfgRCC_DEV0_EPF0_VF29_GFXMSIX_VECT2_CONTROL 0xd0ec202c #define cfgRCC_DEV0_EPF0_VF29_GFXMSIX_VECT3_ADDR_LO 0xd0ec2030 #define cfgRCC_DEV0_EPF0_VF29_GFXMSIX_VECT3_ADDR_HI 0xd0ec2034 #define cfgRCC_DEV0_EPF0_VF29_GFXMSIX_VECT3_MSG_DATA 0xd0ec2038 #define cfgRCC_DEV0_EPF0_VF29_GFXMSIX_VECT3_CONTROL 0xd0ec203c #define cfgRCC_DEV0_EPF0_VF29_GFXMSIX_PBA 0xd0ec3000 // addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf30_SYSPFVFDEC // base address: 0xd0f00000 #define cfgBIF_BX_DEV0_EPF0_VF30_MM_INDEX 0xd0f00000 #define cfgBIF_BX_DEV0_EPF0_VF30_MM_DATA 0xd0f00004 #define cfgBIF_BX_DEV0_EPF0_VF30_MM_INDEX_HI 0xd0f00018 // addressBlock: nbio_nbif0_rcc_dev0_epf0_vf30_BIFPFVFDEC1 // base address: 0xd0f00000 #define cfgRCC_DEV0_EPF0_VF30_RCC_ERR_LOG 0xd0f03694 #define cfgRCC_DEV0_EPF0_VF30_RCC_DOORBELL_APER_EN 0xd0f03780 #define cfgRCC_DEV0_EPF0_VF30_RCC_CONFIG_MEMSIZE 0xd0f0378c #define cfgRCC_DEV0_EPF0_VF30_RCC_CONFIG_RESERVED 0xd0f03790 #define cfgRCC_DEV0_EPF0_VF30_RCC_IOV_FUNC_IDENTIFIER 0xd0f03794 // addressBlock: nbio_nbif0_bif_bx_dev0_epf0_vf30_BIFPFVFDEC1 // base address: 0xd0f00000 #define cfgBIF_BX_DEV0_EPF0_VF30_BIF_BME_STATUS 0xd0f0382c #define cfgBIF_BX_DEV0_EPF0_VF30_BIF_ATOMIC_ERR_LOG 0xd0f03830 #define cfgBIF_BX_DEV0_EPF0_VF30_DOORBELL_SELFRING_GPA_APER_BASE_HIGH 0xd0f0384c #define cfgBIF_BX_DEV0_EPF0_VF30_DOORBELL_SELFRING_GPA_APER_BASE_LOW 0xd0f03850 #define cfgBIF_BX_DEV0_EPF0_VF30_DOORBELL_SELFRING_GPA_APER_CNTL 0xd0f03854 #define cfgBIF_BX_DEV0_EPF0_VF30_HDP_REG_COHERENCY_FLUSH_CNTL 0xd0f03858 #define cfgBIF_BX_DEV0_EPF0_VF30_HDP_MEM_COHERENCY_FLUSH_CNTL 0xd0f0385c #define cfgBIF_BX_DEV0_EPF0_VF30_GPU_HDP_FLUSH_REQ 0xd0f03898 #define cfgBIF_BX_DEV0_EPF0_VF30_GPU_HDP_FLUSH_DONE 0xd0f0389c #define cfgBIF_BX_DEV0_EPF0_VF30_BIF_TRANS_PENDING 0xd0f038a0 #define cfgBIF_BX_DEV0_EPF0_VF30_NBIF_GFX_ADDR_LUT_BYPASS 0xd0f038c8 #define cfgBIF_BX_DEV0_EPF0_VF30_MAILBOX_MSGBUF_TRN_DW0 0xd0f03958 #define cfgBIF_BX_DEV0_EPF0_VF30_MAILBOX_MSGBUF_TRN_DW1 0xd0f0395c #define cfgBIF_BX_DEV0_EPF0_VF30_MAILBOX_MSGBUF_TRN_DW2 0xd0f03960 #define cfgBIF_BX_DEV0_EPF0_VF30_MAILBOX_MSGBUF_TRN_DW3 0xd0f03964 #define cfgBIF_BX_DEV0_EPF0_VF30_MAILBOX_MSGBUF_RCV_DW0 0xd0f03968 #define cfgBIF_BX_DEV0_EPF0_VF30_MAILBOX_MSGBUF_RCV_DW1 0xd0f0396c #define cfgBIF_BX_DEV0_EPF0_VF30_MAILBOX_MSGBUF_RCV_DW2 0xd0f03970 #define cfgBIF_BX_DEV0_EPF0_VF30_MAILBOX_MSGBUF_RCV_DW3 0xd0f03974 #define cfgBIF_BX_DEV0_EPF0_VF30_MAILBOX_CONTROL 0xd0f03978 #define cfgBIF_BX_DEV0_EPF0_VF30_MAILBOX_INT_CNTL 0xd0f0397c #define cfgBIF_BX_DEV0_EPF0_VF30_BIF_VMHV_MAILBOX 0xd0f03980 // addressBlock: nbio_nbif0_rcc_dev0_epf0_vf30_BIFDEC2 // base address: 0xd0f00000 #define cfgRCC_DEV0_EPF0_VF30_GFXMSIX_VECT0_ADDR_LO 0xd0f42000 #define cfgRCC_DEV0_EPF0_VF30_GFXMSIX_VECT0_ADDR_HI 0xd0f42004 #define cfgRCC_DEV0_EPF0_VF30_GFXMSIX_VECT0_MSG_DATA 0xd0f42008 #define cfgRCC_DEV0_EPF0_VF30_GFXMSIX_VECT0_CONTROL 0xd0f4200c #define cfgRCC_DEV0_EPF0_VF30_GFXMSIX_VECT1_ADDR_LO 0xd0f42010 #define cfgRCC_DEV0_EPF0_VF30_GFXMSIX_VECT1_ADDR_HI 0xd0f42014 #define cfgRCC_DEV0_EPF0_VF30_GFXMSIX_VECT1_MSG_DATA 0xd0f42018 #define cfgRCC_DEV0_EPF0_VF30_GFXMSIX_VECT1_CONTROL 0xd0f4201c #define cfgRCC_DEV0_EPF0_VF30_GFXMSIX_VECT2_ADDR_LO 0xd0f42020 #define cfgRCC_DEV0_EPF0_VF30_GFXMSIX_VECT2_ADDR_HI 0xd0f42024 #define cfgRCC_DEV0_EPF0_VF30_GFXMSIX_VECT2_MSG_DATA 0xd0f42028 #define cfgRCC_DEV0_EPF0_VF30_GFXMSIX_VECT2_CONTROL 0xd0f4202c #define cfgRCC_DEV0_EPF0_VF30_GFXMSIX_VECT3_ADDR_LO 0xd0f42030 #define cfgRCC_DEV0_EPF0_VF30_GFXMSIX_VECT3_ADDR_HI 0xd0f42034 #define cfgRCC_DEV0_EPF0_VF30_GFXMSIX_VECT3_MSG_DATA 0xd0f42038 #define cfgRCC_DEV0_EPF0_VF30_GFXMSIX_VECT3_CONTROL 0xd0f4203c #define cfgRCC_DEV0_EPF0_VF30_GFXMSIX_PBA 0xd0f43000 // addressBlock: nbio_pcie0_pswuscfg0_cfgdecp // base address: 0xfffe00000000 #define cfgPSWUSCFG0_1_VENDOR_ID 0xfffe00000000 #define cfgPSWUSCFG0_1_DEVICE_ID 0xfffe00000002 #define cfgPSWUSCFG0_1_COMMAND 0xfffe00000004 #define cfgPSWUSCFG0_1_STATUS 0xfffe00000006 #define cfgPSWUSCFG0_1_REVISION_ID 0xfffe00000008 #define cfgPSWUSCFG0_1_PROG_INTERFACE 0xfffe00000009 #define cfgPSWUSCFG0_1_SUB_CLASS 0xfffe0000000a #define cfgPSWUSCFG0_1_BASE_CLASS 0xfffe0000000b #define cfgPSWUSCFG0_1_CACHE_LINE 0xfffe0000000c #define cfgPSWUSCFG0_1_LATENCY 0xfffe0000000d #define cfgPSWUSCFG0_1_HEADER 0xfffe0000000e #define cfgPSWUSCFG0_1_BIST 0xfffe0000000f #define cfgPSWUSCFG0_1_SUB_BUS_NUMBER_LATENCY 0xfffe00000018 #define cfgPSWUSCFG0_1_IO_BASE_LIMIT 0xfffe0000001c #define cfgPSWUSCFG0_1_SECONDARY_STATUS 0xfffe0000001e #define cfgPSWUSCFG0_1_MEM_BASE_LIMIT 0xfffe00000020 #define cfgPSWUSCFG0_1_PREF_BASE_LIMIT 0xfffe00000024 #define cfgPSWUSCFG0_1_PREF_BASE_UPPER 0xfffe00000028 #define cfgPSWUSCFG0_1_PREF_LIMIT_UPPER 0xfffe0000002c #define cfgPSWUSCFG0_1_IO_BASE_LIMIT_HI 0xfffe00000030 #define cfgPSWUSCFG0_1_CAP_PTR 0xfffe00000034 #define cfgPSWUSCFG0_1_ROM_BASE_ADDR 0xfffe00000038 #define cfgPSWUSCFG0_1_INTERRUPT_LINE 0xfffe0000003c #define cfgPSWUSCFG0_1_INTERRUPT_PIN 0xfffe0000003d #define cfgPSWUSCFG0_1_IRQ_BRIDGE_CNTL 0xfffe0000003e #define cfgPSWUSCFG0_1_EXT_BRIDGE_CNTL 0xfffe00000040 #define cfgPSWUSCFG0_1_VENDOR_CAP_LIST 0xfffe00000048 #define cfgPSWUSCFG0_1_ADAPTER_ID_W 0xfffe0000004c #define cfgPSWUSCFG0_1_PMI_CAP_LIST 0xfffe00000050 #define cfgPSWUSCFG0_1_PMI_CAP 0xfffe00000052 #define cfgPSWUSCFG0_1_PMI_STATUS_CNTL 0xfffe00000054 #define cfgPSWUSCFG0_1_PCIE_CAP_LIST 0xfffe00000058 #define cfgPSWUSCFG0_1_PCIE_CAP 0xfffe0000005a #define cfgPSWUSCFG0_1_DEVICE_CAP 0xfffe0000005c #define cfgPSWUSCFG0_1_DEVICE_CNTL 0xfffe00000060 #define cfgPSWUSCFG0_1_DEVICE_STATUS 0xfffe00000062 #define cfgPSWUSCFG0_1_LINK_CAP 0xfffe00000064 #define cfgPSWUSCFG0_1_LINK_CNTL 0xfffe00000068 #define cfgPSWUSCFG0_1_LINK_STATUS 0xfffe0000006a #define cfgPSWUSCFG0_1_DEVICE_CAP2 0xfffe0000007c #define cfgPSWUSCFG0_1_DEVICE_CNTL2 0xfffe00000080 #define cfgPSWUSCFG0_1_DEVICE_STATUS2 0xfffe00000082 #define cfgPSWUSCFG0_1_LINK_CAP2 0xfffe00000084 #define cfgPSWUSCFG0_1_LINK_CNTL2 0xfffe00000088 #define cfgPSWUSCFG0_1_LINK_STATUS2 0xfffe0000008a #define cfgPSWUSCFG0_1_MSI_CAP_LIST 0xfffe000000a0 #define cfgPSWUSCFG0_1_MSI_MSG_CNTL 0xfffe000000a2 #define cfgPSWUSCFG0_1_MSI_MSG_ADDR_LO 0xfffe000000a4 #define cfgPSWUSCFG0_1_MSI_MSG_ADDR_HI 0xfffe000000a8 #define cfgPSWUSCFG0_1_MSI_MSG_DATA 0xfffe000000a8 #define cfgPSWUSCFG0_1_MSI_MSG_DATA_64 0xfffe000000ac #define cfgPSWUSCFG0_1_SSID_CAP_LIST 0xfffe000000c0 #define cfgPSWUSCFG0_1_SSID_CAP 0xfffe000000c4 #define cfgPSWUSCFG0_1_MSI_MAP_CAP_LIST 0xfffe000000c8 #define cfgPSWUSCFG0_1_MSI_MAP_CAP 0xfffe000000ca #define cfgPSWUSCFG0_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0xfffe00000100 #define cfgPSWUSCFG0_1_PCIE_VENDOR_SPECIFIC_HDR 0xfffe00000104 #define cfgPSWUSCFG0_1_PCIE_VENDOR_SPECIFIC1 0xfffe00000108 #define cfgPSWUSCFG0_1_PCIE_VENDOR_SPECIFIC2 0xfffe0000010c #define cfgPSWUSCFG0_1_PCIE_VC_ENH_CAP_LIST 0xfffe00000110 #define cfgPSWUSCFG0_1_PCIE_PORT_VC_CAP_REG1 0xfffe00000114 #define cfgPSWUSCFG0_1_PCIE_PORT_VC_CAP_REG2 0xfffe00000118 #define cfgPSWUSCFG0_1_PCIE_PORT_VC_CNTL 0xfffe0000011c #define cfgPSWUSCFG0_1_PCIE_PORT_VC_STATUS 0xfffe0000011e #define cfgPSWUSCFG0_1_PCIE_VC0_RESOURCE_CAP 0xfffe00000120 #define cfgPSWUSCFG0_1_PCIE_VC0_RESOURCE_CNTL 0xfffe00000124 #define cfgPSWUSCFG0_1_PCIE_VC0_RESOURCE_STATUS 0xfffe0000012a #define cfgPSWUSCFG0_1_PCIE_VC1_RESOURCE_CAP 0xfffe0000012c #define cfgPSWUSCFG0_1_PCIE_VC1_RESOURCE_CNTL 0xfffe00000130 #define cfgPSWUSCFG0_1_PCIE_VC1_RESOURCE_STATUS 0xfffe00000136 #define cfgPSWUSCFG0_1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST 0xfffe00000140 #define cfgPSWUSCFG0_1_PCIE_DEV_SERIAL_NUM_DW1 0xfffe00000144 #define cfgPSWUSCFG0_1_PCIE_DEV_SERIAL_NUM_DW2 0xfffe00000148 #define cfgPSWUSCFG0_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0xfffe00000150 #define cfgPSWUSCFG0_1_PCIE_UNCORR_ERR_STATUS 0xfffe00000154 #define cfgPSWUSCFG0_1_PCIE_UNCORR_ERR_MASK 0xfffe00000158 #define cfgPSWUSCFG0_1_PCIE_UNCORR_ERR_SEVERITY 0xfffe0000015c #define cfgPSWUSCFG0_1_PCIE_CORR_ERR_STATUS 0xfffe00000160 #define cfgPSWUSCFG0_1_PCIE_CORR_ERR_MASK 0xfffe00000164 #define cfgPSWUSCFG0_1_PCIE_ADV_ERR_CAP_CNTL 0xfffe00000168 #define cfgPSWUSCFG0_1_PCIE_HDR_LOG0 0xfffe0000016c #define cfgPSWUSCFG0_1_PCIE_HDR_LOG1 0xfffe00000170 #define cfgPSWUSCFG0_1_PCIE_HDR_LOG2 0xfffe00000174 #define cfgPSWUSCFG0_1_PCIE_HDR_LOG3 0xfffe00000178 #define cfgPSWUSCFG0_1_PCIE_TLP_PREFIX_LOG0 0xfffe00000188 #define cfgPSWUSCFG0_1_PCIE_TLP_PREFIX_LOG1 0xfffe0000018c #define cfgPSWUSCFG0_1_PCIE_TLP_PREFIX_LOG2 0xfffe00000190 #define cfgPSWUSCFG0_1_PCIE_TLP_PREFIX_LOG3 0xfffe00000194 #define cfgPSWUSCFG0_1_PCIE_SECONDARY_ENH_CAP_LIST 0xfffe00000270 #define cfgPSWUSCFG0_1_PCIE_LINK_CNTL3 0xfffe00000274 #define cfgPSWUSCFG0_1_PCIE_LANE_ERROR_STATUS 0xfffe00000278 #define cfgPSWUSCFG0_1_PCIE_LANE_0_EQUALIZATION_CNTL 0xfffe0000027c #define cfgPSWUSCFG0_1_PCIE_LANE_1_EQUALIZATION_CNTL 0xfffe0000027e #define cfgPSWUSCFG0_1_PCIE_LANE_2_EQUALIZATION_CNTL 0xfffe00000280 #define cfgPSWUSCFG0_1_PCIE_LANE_3_EQUALIZATION_CNTL 0xfffe00000282 #define cfgPSWUSCFG0_1_PCIE_LANE_4_EQUALIZATION_CNTL 0xfffe00000284 #define cfgPSWUSCFG0_1_PCIE_LANE_5_EQUALIZATION_CNTL 0xfffe00000286 #define cfgPSWUSCFG0_1_PCIE_LANE_6_EQUALIZATION_CNTL 0xfffe00000288 #define cfgPSWUSCFG0_1_PCIE_LANE_7_EQUALIZATION_CNTL 0xfffe0000028a #define cfgPSWUSCFG0_1_PCIE_LANE_8_EQUALIZATION_CNTL 0xfffe0000028c #define cfgPSWUSCFG0_1_PCIE_LANE_9_EQUALIZATION_CNTL 0xfffe0000028e #define cfgPSWUSCFG0_1_PCIE_LANE_10_EQUALIZATION_CNTL 0xfffe00000290 #define cfgPSWUSCFG0_1_PCIE_LANE_11_EQUALIZATION_CNTL 0xfffe00000292 #define cfgPSWUSCFG0_1_PCIE_LANE_12_EQUALIZATION_CNTL 0xfffe00000294 #define cfgPSWUSCFG0_1_PCIE_LANE_13_EQUALIZATION_CNTL 0xfffe00000296 #define cfgPSWUSCFG0_1_PCIE_LANE_14_EQUALIZATION_CNTL 0xfffe00000298 #define cfgPSWUSCFG0_1_PCIE_LANE_15_EQUALIZATION_CNTL 0xfffe0000029a #define cfgPSWUSCFG0_1_PCIE_ACS_ENH_CAP_LIST 0xfffe000002a0 #define cfgPSWUSCFG0_1_PCIE_ACS_CAP 0xfffe000002a4 #define cfgPSWUSCFG0_1_PCIE_ACS_CNTL 0xfffe000002a6 #define cfgPSWUSCFG0_1_PCIE_MC_ENH_CAP_LIST 0xfffe000002f0 #define cfgPSWUSCFG0_1_PCIE_MC_CAP 0xfffe000002f4 #define cfgPSWUSCFG0_1_PCIE_MC_CNTL 0xfffe000002f6 #define cfgPSWUSCFG0_1_PCIE_MC_ADDR0 0xfffe000002f8 #define cfgPSWUSCFG0_1_PCIE_MC_ADDR1 0xfffe000002fc #define cfgPSWUSCFG0_1_PCIE_MC_RCV0 0xfffe00000300 #define cfgPSWUSCFG0_1_PCIE_MC_RCV1 0xfffe00000304 #define cfgPSWUSCFG0_1_PCIE_MC_BLOCK_ALL0 0xfffe00000308 #define cfgPSWUSCFG0_1_PCIE_MC_BLOCK_ALL1 0xfffe0000030c #define cfgPSWUSCFG0_1_PCIE_MC_BLOCK_UNTRANSLATED_0 0xfffe00000310 #define cfgPSWUSCFG0_1_PCIE_MC_BLOCK_UNTRANSLATED_1 0xfffe00000314 #define cfgPSWUSCFG0_1_PCIE_MC_OVERLAY_BAR0 0xfffe00000318 #define cfgPSWUSCFG0_1_PCIE_MC_OVERLAY_BAR1 0xfffe0000031c #define cfgPSWUSCFG0_1_PCIE_LTR_ENH_CAP_LIST 0xfffe00000320 #define cfgPSWUSCFG0_1_PCIE_LTR_CAP 0xfffe00000324 #define cfgPSWUSCFG0_1_PCIE_ARI_ENH_CAP_LIST 0xfffe00000328 #define cfgPSWUSCFG0_1_PCIE_ARI_CAP 0xfffe0000032c #define cfgPSWUSCFG0_1_PCIE_ARI_CNTL 0xfffe0000032e #define cfgPSWUSCFG0_1_PCIE_L1_PM_SUB_CAP_LIST 0xfffe00000370 #define cfgPSWUSCFG0_1_PCIE_L1_PM_SUB_CAP 0xfffe00000374 #define cfgPSWUSCFG0_1_PCIE_L1_PM_SUB_CNTL 0xfffe00000378 #define cfgPSWUSCFG0_1_PCIE_L1_PM_SUB_CNTL2 0xfffe0000037c #define cfgPSWUSCFG0_1_PCIE_ESM_CAP_LIST 0xfffe000003c4 #define cfgPSWUSCFG0_1_PCIE_ESM_HEADER_1 0xfffe000003c8 #define cfgPSWUSCFG0_1_PCIE_ESM_HEADER_2 0xfffe000003cc #define cfgPSWUSCFG0_1_PCIE_ESM_STATUS 0xfffe000003ce #define cfgPSWUSCFG0_1_PCIE_ESM_CTRL 0xfffe000003d0 #define cfgPSWUSCFG0_1_PCIE_ESM_CAP_1 0xfffe000003d4 #define cfgPSWUSCFG0_1_PCIE_ESM_CAP_2 0xfffe000003d8 #define cfgPSWUSCFG0_1_PCIE_ESM_CAP_3 0xfffe000003dc #define cfgPSWUSCFG0_1_PCIE_ESM_CAP_4 0xfffe000003e0 #define cfgPSWUSCFG0_1_PCIE_ESM_CAP_5 0xfffe000003e4 #define cfgPSWUSCFG0_1_PCIE_ESM_CAP_6 0xfffe000003e8 #define cfgPSWUSCFG0_1_PCIE_ESM_CAP_7 0xfffe000003ec #define cfgPSWUSCFG0_1_PCIE_DLF_ENH_CAP_LIST 0xfffe00000400 #define cfgPSWUSCFG0_1_DATA_LINK_FEATURE_CAP 0xfffe00000404 #define cfgPSWUSCFG0_1_DATA_LINK_FEATURE_STATUS 0xfffe00000408 #define cfgPSWUSCFG0_1_PCIE_PHY_16GT_ENH_CAP_LIST 0xfffe00000410 #define cfgPSWUSCFG0_1_LINK_CAP_16GT 0xfffe00000414 #define cfgPSWUSCFG0_1_LINK_CNTL_16GT 0xfffe00000418 #define cfgPSWUSCFG0_1_LINK_STATUS_16GT 0xfffe0000041c #define cfgPSWUSCFG0_1_LOCAL_PARITY_MISMATCH_STATUS_16GT 0xfffe00000420 #define cfgPSWUSCFG0_1_RTM1_PARITY_MISMATCH_STATUS_16GT 0xfffe00000424 #define cfgPSWUSCFG0_1_RTM2_PARITY_MISMATCH_STATUS_16GT 0xfffe00000428 #define cfgPSWUSCFG0_1_LANE_0_EQUALIZATION_CNTL_16GT 0xfffe00000430 #define cfgPSWUSCFG0_1_LANE_1_EQUALIZATION_CNTL_16GT 0xfffe00000431 #define cfgPSWUSCFG0_1_LANE_2_EQUALIZATION_CNTL_16GT 0xfffe00000432 #define cfgPSWUSCFG0_1_LANE_3_EQUALIZATION_CNTL_16GT 0xfffe00000433 #define cfgPSWUSCFG0_1_LANE_4_EQUALIZATION_CNTL_16GT 0xfffe00000434 #define cfgPSWUSCFG0_1_LANE_5_EQUALIZATION_CNTL_16GT 0xfffe00000435 #define cfgPSWUSCFG0_1_LANE_6_EQUALIZATION_CNTL_16GT 0xfffe00000436 #define cfgPSWUSCFG0_1_LANE_7_EQUALIZATION_CNTL_16GT 0xfffe00000437 #define cfgPSWUSCFG0_1_LANE_8_EQUALIZATION_CNTL_16GT 0xfffe00000438 #define cfgPSWUSCFG0_1_LANE_9_EQUALIZATION_CNTL_16GT 0xfffe00000439 #define cfgPSWUSCFG0_1_LANE_10_EQUALIZATION_CNTL_16GT 0xfffe0000043a #define cfgPSWUSCFG0_1_LANE_11_EQUALIZATION_CNTL_16GT 0xfffe0000043b #define cfgPSWUSCFG0_1_LANE_12_EQUALIZATION_CNTL_16GT 0xfffe0000043c #define cfgPSWUSCFG0_1_LANE_13_EQUALIZATION_CNTL_16GT 0xfffe0000043d #define cfgPSWUSCFG0_1_LANE_14_EQUALIZATION_CNTL_16GT 0xfffe0000043e #define cfgPSWUSCFG0_1_LANE_15_EQUALIZATION_CNTL_16GT 0xfffe0000043f #define cfgPSWUSCFG0_1_PCIE_MARGINING_ENH_CAP_LIST 0xfffe00000440 #define cfgPSWUSCFG0_1_MARGINING_PORT_CAP 0xfffe00000444 #define cfgPSWUSCFG0_1_MARGINING_PORT_STATUS 0xfffe00000446 #define cfgPSWUSCFG0_1_LANE_0_MARGINING_LANE_CNTL 0xfffe00000448 #define cfgPSWUSCFG0_1_LANE_0_MARGINING_LANE_STATUS 0xfffe0000044a #define cfgPSWUSCFG0_1_LANE_1_MARGINING_LANE_CNTL 0xfffe0000044c #define cfgPSWUSCFG0_1_LANE_1_MARGINING_LANE_STATUS 0xfffe0000044e #define cfgPSWUSCFG0_1_LANE_2_MARGINING_LANE_CNTL 0xfffe00000450 #define cfgPSWUSCFG0_1_LANE_2_MARGINING_LANE_STATUS 0xfffe00000452 #define cfgPSWUSCFG0_1_LANE_3_MARGINING_LANE_CNTL 0xfffe00000454 #define cfgPSWUSCFG0_1_LANE_3_MARGINING_LANE_STATUS 0xfffe00000456 #define cfgPSWUSCFG0_1_LANE_4_MARGINING_LANE_CNTL 0xfffe00000458 #define cfgPSWUSCFG0_1_LANE_4_MARGINING_LANE_STATUS 0xfffe0000045a #define cfgPSWUSCFG0_1_LANE_5_MARGINING_LANE_CNTL 0xfffe0000045c #define cfgPSWUSCFG0_1_LANE_5_MARGINING_LANE_STATUS 0xfffe0000045e #define cfgPSWUSCFG0_1_LANE_6_MARGINING_LANE_CNTL 0xfffe00000460 #define cfgPSWUSCFG0_1_LANE_6_MARGINING_LANE_STATUS 0xfffe00000462 #define cfgPSWUSCFG0_1_LANE_7_MARGINING_LANE_CNTL 0xfffe00000464 #define cfgPSWUSCFG0_1_LANE_7_MARGINING_LANE_STATUS 0xfffe00000466 #define cfgPSWUSCFG0_1_LANE_8_MARGINING_LANE_CNTL 0xfffe00000468 #define cfgPSWUSCFG0_1_LANE_8_MARGINING_LANE_STATUS 0xfffe0000046a #define cfgPSWUSCFG0_1_LANE_9_MARGINING_LANE_CNTL 0xfffe0000046c #define cfgPSWUSCFG0_1_LANE_9_MARGINING_LANE_STATUS 0xfffe0000046e #define cfgPSWUSCFG0_1_LANE_10_MARGINING_LANE_CNTL 0xfffe00000470 #define cfgPSWUSCFG0_1_LANE_10_MARGINING_LANE_STATUS 0xfffe00000472 #define cfgPSWUSCFG0_1_LANE_11_MARGINING_LANE_CNTL 0xfffe00000474 #define cfgPSWUSCFG0_1_LANE_11_MARGINING_LANE_STATUS 0xfffe00000476 #define cfgPSWUSCFG0_1_LANE_12_MARGINING_LANE_CNTL 0xfffe00000478 #define cfgPSWUSCFG0_1_LANE_12_MARGINING_LANE_STATUS 0xfffe0000047a #define cfgPSWUSCFG0_1_LANE_13_MARGINING_LANE_CNTL 0xfffe0000047c #define cfgPSWUSCFG0_1_LANE_13_MARGINING_LANE_STATUS 0xfffe0000047e #define cfgPSWUSCFG0_1_LANE_14_MARGINING_LANE_CNTL 0xfffe00000480 #define cfgPSWUSCFG0_1_LANE_14_MARGINING_LANE_STATUS 0xfffe00000482 #define cfgPSWUSCFG0_1_LANE_15_MARGINING_LANE_CNTL 0xfffe00000484 #define cfgPSWUSCFG0_1_LANE_15_MARGINING_LANE_STATUS 0xfffe00000486 #define cfgPSWUSCFG0_1_PCIE_CCIX_CAP_LIST 0xfffe00000488 #define cfgPSWUSCFG0_1_PCIE_CCIX_HEADER_1 0xfffe0000048c #define cfgPSWUSCFG0_1_PCIE_CCIX_HEADER_2 0xfffe00000490 #define cfgPSWUSCFG0_1_PCIE_CCIX_CAP 0xfffe00000492 #define cfgPSWUSCFG0_1_PCIE_CCIX_ESM_REQD_CAP 0xfffe00000494 #define cfgPSWUSCFG0_1_PCIE_CCIX_ESM_OPTL_CAP 0xfffe00000498 #define cfgPSWUSCFG0_1_PCIE_CCIX_ESM_STATUS 0xfffe0000049c #define cfgPSWUSCFG0_1_PCIE_CCIX_ESM_CNTL 0xfffe000004a0 #define cfgPSWUSCFG0_1_ESM_LANE_0_EQUALIZATION_CNTL_20GT 0xfffe000004a4 #define cfgPSWUSCFG0_1_ESM_LANE_1_EQUALIZATION_CNTL_20GT 0xfffe000004a5 #define cfgPSWUSCFG0_1_ESM_LANE_2_EQUALIZATION_CNTL_20GT 0xfffe000004a6 #define cfgPSWUSCFG0_1_ESM_LANE_3_EQUALIZATION_CNTL_20GT 0xfffe000004a7 #define cfgPSWUSCFG0_1_ESM_LANE_4_EQUALIZATION_CNTL_20GT 0xfffe000004a8 #define cfgPSWUSCFG0_1_ESM_LANE_5_EQUALIZATION_CNTL_20GT 0xfffe000004a9 #define cfgPSWUSCFG0_1_ESM_LANE_6_EQUALIZATION_CNTL_20GT 0xfffe000004aa #define cfgPSWUSCFG0_1_ESM_LANE_7_EQUALIZATION_CNTL_20GT 0xfffe000004ab #define cfgPSWUSCFG0_1_ESM_LANE_8_EQUALIZATION_CNTL_20GT 0xfffe000004ac #define cfgPSWUSCFG0_1_ESM_LANE_9_EQUALIZATION_CNTL_20GT 0xfffe000004ad #define cfgPSWUSCFG0_1_ESM_LANE_10_EQUALIZATION_CNTL_20GT 0xfffe000004ae #define cfgPSWUSCFG0_1_ESM_LANE_11_EQUALIZATION_CNTL_20GT 0xfffe000004af #define cfgPSWUSCFG0_1_ESM_LANE_12_EQUALIZATION_CNTL_20GT 0xfffe000004b0 #define cfgPSWUSCFG0_1_ESM_LANE_13_EQUALIZATION_CNTL_20GT 0xfffe000004b1 #define cfgPSWUSCFG0_1_ESM_LANE_14_EQUALIZATION_CNTL_20GT 0xfffe000004b2 #define cfgPSWUSCFG0_1_ESM_LANE_15_EQUALIZATION_CNTL_20GT 0xfffe000004b3 #define cfgPSWUSCFG0_1_ESM_LANE_0_EQUALIZATION_CNTL_25GT 0xfffe000004b4 #define cfgPSWUSCFG0_1_ESM_LANE_1_EQUALIZATION_CNTL_25GT 0xfffe000004b5 #define cfgPSWUSCFG0_1_ESM_LANE_2_EQUALIZATION_CNTL_25GT 0xfffe000004b6 #define cfgPSWUSCFG0_1_ESM_LANE_3_EQUALIZATION_CNTL_25GT 0xfffe000004b7 #define cfgPSWUSCFG0_1_ESM_LANE_4_EQUALIZATION_CNTL_25GT 0xfffe000004b8 #define cfgPSWUSCFG0_1_ESM_LANE_5_EQUALIZATION_CNTL_25GT 0xfffe000004b9 #define cfgPSWUSCFG0_1_ESM_LANE_6_EQUALIZATION_CNTL_25GT 0xfffe000004ba #define cfgPSWUSCFG0_1_ESM_LANE_7_EQUALIZATION_CNTL_25GT 0xfffe000004bb #define cfgPSWUSCFG0_1_ESM_LANE_8_EQUALIZATION_CNTL_25GT 0xfffe000004bc #define cfgPSWUSCFG0_1_ESM_LANE_9_EQUALIZATION_CNTL_25GT 0xfffe000004bd #define cfgPSWUSCFG0_1_ESM_LANE_10_EQUALIZATION_CNTL_25GT 0xfffe000004be #define cfgPSWUSCFG0_1_ESM_LANE_11_EQUALIZATION_CNTL_25GT 0xfffe000004bf #define cfgPSWUSCFG0_1_ESM_LANE_12_EQUALIZATION_CNTL_25GT 0xfffe000004c0 #define cfgPSWUSCFG0_1_ESM_LANE_13_EQUALIZATION_CNTL_25GT 0xfffe000004c1 #define cfgPSWUSCFG0_1_ESM_LANE_14_EQUALIZATION_CNTL_25GT 0xfffe000004c2 #define cfgPSWUSCFG0_1_ESM_LANE_15_EQUALIZATION_CNTL_25GT 0xfffe000004c3 #define cfgPSWUSCFG0_1_PCIE_CCIX_TRANS_CAP 0xfffe000004c4 #define cfgPSWUSCFG0_1_PCIE_CCIX_TRANS_CNTL 0xfffe000004c8 // addressBlock: nbio_nbif0_bif_bx_pf_SYSPFVFDEC:1 // base address: 0x0 #define cfgBIF_BX_PF0_MM_INDEX 0x0000 #define cfgBIF_BX_PF0_MM_DATA 0x0004 #define cfgBIF_BX_PF0_MM_INDEX_HI 0x0018 // addressBlock: nbio_nbif0_bif_swus_SUMDEC // base address: 0x100000 #define cfgSUM_INDEX 0x1000e0 #define cfgSUM_DATA 0x1000e4 // addressBlock: nbio_nbif0_bif_cfg_dev0_swds_bifcfgdecp // base address: 0xfffe10100000 #define cfgBIF_CFG_DEV0_SWDS1_VENDOR_ID 0xfffe10100000 #define cfgBIF_CFG_DEV0_SWDS1_DEVICE_ID 0xfffe10100002 #define cfgBIF_CFG_DEV0_SWDS1_COMMAND 0xfffe10100004 #define cfgBIF_CFG_DEV0_SWDS1_STATUS 0xfffe10100006 #define cfgBIF_CFG_DEV0_SWDS1_REVISION_ID 0xfffe10100008 #define cfgBIF_CFG_DEV0_SWDS1_PROG_INTERFACE 0xfffe10100009 #define cfgBIF_CFG_DEV0_SWDS1_SUB_CLASS 0xfffe1010000a #define cfgBIF_CFG_DEV0_SWDS1_BASE_CLASS 0xfffe1010000b #define cfgBIF_CFG_DEV0_SWDS1_CACHE_LINE 0xfffe1010000c #define cfgBIF_CFG_DEV0_SWDS1_LATENCY 0xfffe1010000d #define cfgBIF_CFG_DEV0_SWDS1_HEADER 0xfffe1010000e #define cfgBIF_CFG_DEV0_SWDS1_BIST 0xfffe1010000f #define cfgBIF_CFG_DEV0_SWDS1_BASE_ADDR_1 0xfffe10100010 #define cfgBIF_CFG_DEV0_SWDS1_BASE_ADDR_2 0xfffe10100014 #define cfgBIF_CFG_DEV0_SWDS1_SUB_BUS_NUMBER_LATENCY 0xfffe10100018 #define cfgBIF_CFG_DEV0_SWDS1_IO_BASE_LIMIT 0xfffe1010001c #define cfgBIF_CFG_DEV0_SWDS1_SECONDARY_STATUS 0xfffe1010001e #define cfgBIF_CFG_DEV0_SWDS1_MEM_BASE_LIMIT 0xfffe10100020 #define cfgBIF_CFG_DEV0_SWDS1_PREF_BASE_LIMIT 0xfffe10100024 #define cfgBIF_CFG_DEV0_SWDS1_PREF_BASE_UPPER 0xfffe10100028 #define cfgBIF_CFG_DEV0_SWDS1_PREF_LIMIT_UPPER 0xfffe1010002c #define cfgBIF_CFG_DEV0_SWDS1_IO_BASE_LIMIT_HI 0xfffe10100030 #define cfgBIF_CFG_DEV0_SWDS1_CAP_PTR 0xfffe10100034 #define cfgBIF_CFG_DEV0_SWDS1_ROM_BASE_ADDR 0xfffe10100038 #define cfgBIF_CFG_DEV0_SWDS1_INTERRUPT_LINE 0xfffe1010003c #define cfgBIF_CFG_DEV0_SWDS1_INTERRUPT_PIN 0xfffe1010003d #define cfgBIF_CFG_DEV0_SWDS1_IRQ_BRIDGE_CNTL 0xfffe1010003e #define cfgBIF_CFG_DEV0_SWDS1_PMI_CAP_LIST 0xfffe10100050 #define cfgBIF_CFG_DEV0_SWDS1_PMI_CAP 0xfffe10100052 #define cfgBIF_CFG_DEV0_SWDS1_PMI_STATUS_CNTL 0xfffe10100054 #define cfgBIF_CFG_DEV0_SWDS1_PCIE_CAP_LIST 0xfffe10100058 #define cfgBIF_CFG_DEV0_SWDS1_PCIE_CAP 0xfffe1010005a #define cfgBIF_CFG_DEV0_SWDS1_DEVICE_CAP 0xfffe1010005c #define cfgBIF_CFG_DEV0_SWDS1_DEVICE_CNTL 0xfffe10100060 #define cfgBIF_CFG_DEV0_SWDS1_DEVICE_STATUS 0xfffe10100062 #define cfgBIF_CFG_DEV0_SWDS1_LINK_CAP 0xfffe10100064 #define cfgBIF_CFG_DEV0_SWDS1_LINK_CNTL 0xfffe10100068 #define cfgBIF_CFG_DEV0_SWDS1_LINK_STATUS 0xfffe1010006a #define cfgBIF_CFG_DEV0_SWDS1_SLOT_CAP 0xfffe1010006c #define cfgBIF_CFG_DEV0_SWDS1_SLOT_CNTL 0xfffe10100070 #define cfgBIF_CFG_DEV0_SWDS1_SLOT_STATUS 0xfffe10100072 #define cfgBIF_CFG_DEV0_SWDS1_DEVICE_CAP2 0xfffe1010007c #define cfgBIF_CFG_DEV0_SWDS1_DEVICE_CNTL2 0xfffe10100080 #define cfgBIF_CFG_DEV0_SWDS1_DEVICE_STATUS2 0xfffe10100082 #define cfgBIF_CFG_DEV0_SWDS1_LINK_CAP2 0xfffe10100084 #define cfgBIF_CFG_DEV0_SWDS1_LINK_CNTL2 0xfffe10100088 #define cfgBIF_CFG_DEV0_SWDS1_LINK_STATUS2 0xfffe1010008a #define cfgBIF_CFG_DEV0_SWDS1_SLOT_CAP2 0xfffe1010008c #define cfgBIF_CFG_DEV0_SWDS1_SLOT_CNTL2 0xfffe10100090 #define cfgBIF_CFG_DEV0_SWDS1_SLOT_STATUS2 0xfffe10100092 #define cfgBIF_CFG_DEV0_SWDS1_MSI_CAP_LIST 0xfffe101000a0 #define cfgBIF_CFG_DEV0_SWDS1_MSI_MSG_CNTL 0xfffe101000a2 #define cfgBIF_CFG_DEV0_SWDS1_MSI_MSG_ADDR_LO 0xfffe101000a4 #define cfgBIF_CFG_DEV0_SWDS1_MSI_MSG_ADDR_HI 0xfffe101000a8 #define cfgBIF_CFG_DEV0_SWDS1_MSI_MSG_DATA 0xfffe101000a8 #define cfgBIF_CFG_DEV0_SWDS1_MSI_MSG_DATA_64 0xfffe101000ac #define cfgBIF_CFG_DEV0_SWDS1_SSID_CAP_LIST 0xfffe101000c0 #define cfgBIF_CFG_DEV0_SWDS1_SSID_CAP 0xfffe101000c4 #define cfgBIF_CFG_DEV0_SWDS1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0xfffe10100100 #define cfgBIF_CFG_DEV0_SWDS1_PCIE_VENDOR_SPECIFIC_HDR 0xfffe10100104 #define cfgBIF_CFG_DEV0_SWDS1_PCIE_VENDOR_SPECIFIC1 0xfffe10100108 #define cfgBIF_CFG_DEV0_SWDS1_PCIE_VENDOR_SPECIFIC2 0xfffe1010010c #define cfgBIF_CFG_DEV0_SWDS1_PCIE_VC_ENH_CAP_LIST 0xfffe10100110 #define cfgBIF_CFG_DEV0_SWDS1_PCIE_PORT_VC_CAP_REG1 0xfffe10100114 #define cfgBIF_CFG_DEV0_SWDS1_PCIE_PORT_VC_CAP_REG2 0xfffe10100118 #define cfgBIF_CFG_DEV0_SWDS1_PCIE_PORT_VC_CNTL 0xfffe1010011c #define cfgBIF_CFG_DEV0_SWDS1_PCIE_PORT_VC_STATUS 0xfffe1010011e #define cfgBIF_CFG_DEV0_SWDS1_PCIE_VC0_RESOURCE_CAP 0xfffe10100120 #define cfgBIF_CFG_DEV0_SWDS1_PCIE_VC0_RESOURCE_CNTL 0xfffe10100124 #define cfgBIF_CFG_DEV0_SWDS1_PCIE_VC0_RESOURCE_STATUS 0xfffe1010012a #define cfgBIF_CFG_DEV0_SWDS1_PCIE_VC1_RESOURCE_CAP 0xfffe1010012c #define cfgBIF_CFG_DEV0_SWDS1_PCIE_VC1_RESOURCE_CNTL 0xfffe10100130 #define cfgBIF_CFG_DEV0_SWDS1_PCIE_VC1_RESOURCE_STATUS 0xfffe10100136 #define cfgBIF_CFG_DEV0_SWDS1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST 0xfffe10100140 #define cfgBIF_CFG_DEV0_SWDS1_PCIE_DEV_SERIAL_NUM_DW1 0xfffe10100144 #define cfgBIF_CFG_DEV0_SWDS1_PCIE_DEV_SERIAL_NUM_DW2 0xfffe10100148 #define cfgBIF_CFG_DEV0_SWDS1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0xfffe10100150 #define cfgBIF_CFG_DEV0_SWDS1_PCIE_UNCORR_ERR_STATUS 0xfffe10100154 #define cfgBIF_CFG_DEV0_SWDS1_PCIE_UNCORR_ERR_MASK 0xfffe10100158 #define cfgBIF_CFG_DEV0_SWDS1_PCIE_UNCORR_ERR_SEVERITY 0xfffe1010015c #define cfgBIF_CFG_DEV0_SWDS1_PCIE_CORR_ERR_STATUS 0xfffe10100160 #define cfgBIF_CFG_DEV0_SWDS1_PCIE_CORR_ERR_MASK 0xfffe10100164 #define cfgBIF_CFG_DEV0_SWDS1_PCIE_ADV_ERR_CAP_CNTL 0xfffe10100168 #define cfgBIF_CFG_DEV0_SWDS1_PCIE_HDR_LOG0 0xfffe1010016c #define cfgBIF_CFG_DEV0_SWDS1_PCIE_HDR_LOG1 0xfffe10100170 #define cfgBIF_CFG_DEV0_SWDS1_PCIE_HDR_LOG2 0xfffe10100174 #define cfgBIF_CFG_DEV0_SWDS1_PCIE_HDR_LOG3 0xfffe10100178 #define cfgBIF_CFG_DEV0_SWDS1_PCIE_TLP_PREFIX_LOG0 0xfffe10100188 #define cfgBIF_CFG_DEV0_SWDS1_PCIE_TLP_PREFIX_LOG1 0xfffe1010018c #define cfgBIF_CFG_DEV0_SWDS1_PCIE_TLP_PREFIX_LOG2 0xfffe10100190 #define cfgBIF_CFG_DEV0_SWDS1_PCIE_TLP_PREFIX_LOG3 0xfffe10100194 #define cfgBIF_CFG_DEV0_SWDS1_PCIE_SECONDARY_ENH_CAP_LIST 0xfffe10100270 #define cfgBIF_CFG_DEV0_SWDS1_PCIE_LINK_CNTL3 0xfffe10100274 #define cfgBIF_CFG_DEV0_SWDS1_PCIE_LANE_ERROR_STATUS 0xfffe10100278 #define cfgBIF_CFG_DEV0_SWDS1_PCIE_LANE_0_EQUALIZATION_CNTL 0xfffe1010027c #define cfgBIF_CFG_DEV0_SWDS1_PCIE_LANE_1_EQUALIZATION_CNTL 0xfffe1010027e #define cfgBIF_CFG_DEV0_SWDS1_PCIE_LANE_2_EQUALIZATION_CNTL 0xfffe10100280 #define cfgBIF_CFG_DEV0_SWDS1_PCIE_LANE_3_EQUALIZATION_CNTL 0xfffe10100282 #define cfgBIF_CFG_DEV0_SWDS1_PCIE_LANE_4_EQUALIZATION_CNTL 0xfffe10100284 #define cfgBIF_CFG_DEV0_SWDS1_PCIE_LANE_5_EQUALIZATION_CNTL 0xfffe10100286 #define cfgBIF_CFG_DEV0_SWDS1_PCIE_LANE_6_EQUALIZATION_CNTL 0xfffe10100288 #define cfgBIF_CFG_DEV0_SWDS1_PCIE_LANE_7_EQUALIZATION_CNTL 0xfffe1010028a #define cfgBIF_CFG_DEV0_SWDS1_PCIE_LANE_8_EQUALIZATION_CNTL 0xfffe1010028c #define cfgBIF_CFG_DEV0_SWDS1_PCIE_LANE_9_EQUALIZATION_CNTL 0xfffe1010028e #define cfgBIF_CFG_DEV0_SWDS1_PCIE_LANE_10_EQUALIZATION_CNTL 0xfffe10100290 #define cfgBIF_CFG_DEV0_SWDS1_PCIE_LANE_11_EQUALIZATION_CNTL 0xfffe10100292 #define cfgBIF_CFG_DEV0_SWDS1_PCIE_LANE_12_EQUALIZATION_CNTL 0xfffe10100294 #define cfgBIF_CFG_DEV0_SWDS1_PCIE_LANE_13_EQUALIZATION_CNTL 0xfffe10100296 #define cfgBIF_CFG_DEV0_SWDS1_PCIE_LANE_14_EQUALIZATION_CNTL 0xfffe10100298 #define cfgBIF_CFG_DEV0_SWDS1_PCIE_LANE_15_EQUALIZATION_CNTL 0xfffe1010029a #define cfgBIF_CFG_DEV0_SWDS1_PCIE_ACS_ENH_CAP_LIST 0xfffe101002a0 #define cfgBIF_CFG_DEV0_SWDS1_PCIE_ACS_CAP 0xfffe101002a4 #define cfgBIF_CFG_DEV0_SWDS1_PCIE_ACS_CNTL 0xfffe101002a6 #define cfgBIF_CFG_DEV0_SWDS1_PCIE_DLF_ENH_CAP_LIST 0xfffe10100400 #define cfgBIF_CFG_DEV0_SWDS1_DATA_LINK_FEATURE_CAP 0xfffe10100404 #define cfgBIF_CFG_DEV0_SWDS1_DATA_LINK_FEATURE_STATUS 0xfffe10100408 #define cfgBIF_CFG_DEV0_SWDS1_PCIE_PHY_16GT_ENH_CAP_LIST 0xfffe10100410 #define cfgBIF_CFG_DEV0_SWDS1_LINK_CAP_16GT 0xfffe10100414 #define cfgBIF_CFG_DEV0_SWDS1_LINK_CNTL_16GT 0xfffe10100418 #define cfgBIF_CFG_DEV0_SWDS1_LINK_STATUS_16GT 0xfffe1010041c #define cfgBIF_CFG_DEV0_SWDS1_LOCAL_PARITY_MISMATCH_STATUS_16GT 0xfffe10100420 #define cfgBIF_CFG_DEV0_SWDS1_RTM1_PARITY_MISMATCH_STATUS_16GT 0xfffe10100424 #define cfgBIF_CFG_DEV0_SWDS1_RTM2_PARITY_MISMATCH_STATUS_16GT 0xfffe10100428 #define cfgBIF_CFG_DEV0_SWDS1_LANE_0_EQUALIZATION_CNTL_16GT 0xfffe10100430 #define cfgBIF_CFG_DEV0_SWDS1_LANE_1_EQUALIZATION_CNTL_16GT 0xfffe10100431 #define cfgBIF_CFG_DEV0_SWDS1_LANE_2_EQUALIZATION_CNTL_16GT 0xfffe10100432 #define cfgBIF_CFG_DEV0_SWDS1_LANE_3_EQUALIZATION_CNTL_16GT 0xfffe10100433 #define cfgBIF_CFG_DEV0_SWDS1_LANE_4_EQUALIZATION_CNTL_16GT 0xfffe10100434 #define cfgBIF_CFG_DEV0_SWDS1_LANE_5_EQUALIZATION_CNTL_16GT 0xfffe10100435 #define cfgBIF_CFG_DEV0_SWDS1_LANE_6_EQUALIZATION_CNTL_16GT 0xfffe10100436 #define cfgBIF_CFG_DEV0_SWDS1_LANE_7_EQUALIZATION_CNTL_16GT 0xfffe10100437 #define cfgBIF_CFG_DEV0_SWDS1_LANE_8_EQUALIZATION_CNTL_16GT 0xfffe10100438 #define cfgBIF_CFG_DEV0_SWDS1_LANE_9_EQUALIZATION_CNTL_16GT 0xfffe10100439 #define cfgBIF_CFG_DEV0_SWDS1_LANE_10_EQUALIZATION_CNTL_16GT 0xfffe1010043a #define cfgBIF_CFG_DEV0_SWDS1_LANE_11_EQUALIZATION_CNTL_16GT 0xfffe1010043b #define cfgBIF_CFG_DEV0_SWDS1_LANE_12_EQUALIZATION_CNTL_16GT 0xfffe1010043c #define cfgBIF_CFG_DEV0_SWDS1_LANE_13_EQUALIZATION_CNTL_16GT 0xfffe1010043d #define cfgBIF_CFG_DEV0_SWDS1_LANE_14_EQUALIZATION_CNTL_16GT 0xfffe1010043e #define cfgBIF_CFG_DEV0_SWDS1_LANE_15_EQUALIZATION_CNTL_16GT 0xfffe1010043f #define cfgBIF_CFG_DEV0_SWDS1_PCIE_MARGINING_ENH_CAP_LIST 0xfffe10100440 #define cfgBIF_CFG_DEV0_SWDS1_MARGINING_PORT_CAP 0xfffe10100444 #define cfgBIF_CFG_DEV0_SWDS1_MARGINING_PORT_STATUS 0xfffe10100446 #define cfgBIF_CFG_DEV0_SWDS1_LANE_0_MARGINING_LANE_CNTL 0xfffe10100448 #define cfgBIF_CFG_DEV0_SWDS1_LANE_0_MARGINING_LANE_STATUS 0xfffe1010044a #define cfgBIF_CFG_DEV0_SWDS1_LANE_1_MARGINING_LANE_CNTL 0xfffe1010044c #define cfgBIF_CFG_DEV0_SWDS1_LANE_1_MARGINING_LANE_STATUS 0xfffe1010044e #define cfgBIF_CFG_DEV0_SWDS1_LANE_2_MARGINING_LANE_CNTL 0xfffe10100450 #define cfgBIF_CFG_DEV0_SWDS1_LANE_2_MARGINING_LANE_STATUS 0xfffe10100452 #define cfgBIF_CFG_DEV0_SWDS1_LANE_3_MARGINING_LANE_CNTL 0xfffe10100454 #define cfgBIF_CFG_DEV0_SWDS1_LANE_3_MARGINING_LANE_STATUS 0xfffe10100456 #define cfgBIF_CFG_DEV0_SWDS1_LANE_4_MARGINING_LANE_CNTL 0xfffe10100458 #define cfgBIF_CFG_DEV0_SWDS1_LANE_4_MARGINING_LANE_STATUS 0xfffe1010045a #define cfgBIF_CFG_DEV0_SWDS1_LANE_5_MARGINING_LANE_CNTL 0xfffe1010045c #define cfgBIF_CFG_DEV0_SWDS1_LANE_5_MARGINING_LANE_STATUS 0xfffe1010045e #define cfgBIF_CFG_DEV0_SWDS1_LANE_6_MARGINING_LANE_CNTL 0xfffe10100460 #define cfgBIF_CFG_DEV0_SWDS1_LANE_6_MARGINING_LANE_STATUS 0xfffe10100462 #define cfgBIF_CFG_DEV0_SWDS1_LANE_7_MARGINING_LANE_CNTL 0xfffe10100464 #define cfgBIF_CFG_DEV0_SWDS1_LANE_7_MARGINING_LANE_STATUS 0xfffe10100466 #define cfgBIF_CFG_DEV0_SWDS1_LANE_8_MARGINING_LANE_CNTL 0xfffe10100468 #define cfgBIF_CFG_DEV0_SWDS1_LANE_8_MARGINING_LANE_STATUS 0xfffe1010046a #define cfgBIF_CFG_DEV0_SWDS1_LANE_9_MARGINING_LANE_CNTL 0xfffe1010046c #define cfgBIF_CFG_DEV0_SWDS1_LANE_9_MARGINING_LANE_STATUS 0xfffe1010046e #define cfgBIF_CFG_DEV0_SWDS1_LANE_10_MARGINING_LANE_CNTL 0xfffe10100470 #define cfgBIF_CFG_DEV0_SWDS1_LANE_10_MARGINING_LANE_STATUS 0xfffe10100472 #define cfgBIF_CFG_DEV0_SWDS1_LANE_11_MARGINING_LANE_CNTL 0xfffe10100474 #define cfgBIF_CFG_DEV0_SWDS1_LANE_11_MARGINING_LANE_STATUS 0xfffe10100476 #define cfgBIF_CFG_DEV0_SWDS1_LANE_12_MARGINING_LANE_CNTL 0xfffe10100478 #define cfgBIF_CFG_DEV0_SWDS1_LANE_12_MARGINING_LANE_STATUS 0xfffe1010047a #define cfgBIF_CFG_DEV0_SWDS1_LANE_13_MARGINING_LANE_CNTL 0xfffe1010047c #define cfgBIF_CFG_DEV0_SWDS1_LANE_13_MARGINING_LANE_STATUS 0xfffe1010047e #define cfgBIF_CFG_DEV0_SWDS1_LANE_14_MARGINING_LANE_CNTL 0xfffe10100480 #define cfgBIF_CFG_DEV0_SWDS1_LANE_14_MARGINING_LANE_STATUS 0xfffe10100482 #define cfgBIF_CFG_DEV0_SWDS1_LANE_15_MARGINING_LANE_CNTL 0xfffe10100484 #define cfgBIF_CFG_DEV0_SWDS1_LANE_15_MARGINING_LANE_STATUS 0xfffe10100486 // addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_bifcfgdecp // base address: 0xfffe10200000 #define cfgBIF_CFG_DEV0_EPF0_1_VENDOR_ID 0xfffe10200000 #define cfgBIF_CFG_DEV0_EPF0_1_DEVICE_ID 0xfffe10200002 #define cfgBIF_CFG_DEV0_EPF0_1_COMMAND 0xfffe10200004 #define cfgBIF_CFG_DEV0_EPF0_1_STATUS 0xfffe10200006 #define cfgBIF_CFG_DEV0_EPF0_1_REVISION_ID 0xfffe10200008 #define cfgBIF_CFG_DEV0_EPF0_1_PROG_INTERFACE 0xfffe10200009 #define cfgBIF_CFG_DEV0_EPF0_1_SUB_CLASS 0xfffe1020000a #define cfgBIF_CFG_DEV0_EPF0_1_BASE_CLASS 0xfffe1020000b #define cfgBIF_CFG_DEV0_EPF0_1_CACHE_LINE 0xfffe1020000c #define cfgBIF_CFG_DEV0_EPF0_1_LATENCY 0xfffe1020000d #define cfgBIF_CFG_DEV0_EPF0_1_HEADER 0xfffe1020000e #define cfgBIF_CFG_DEV0_EPF0_1_BIST 0xfffe1020000f #define cfgBIF_CFG_DEV0_EPF0_1_BASE_ADDR_1 0xfffe10200010 #define cfgBIF_CFG_DEV0_EPF0_1_BASE_ADDR_2 0xfffe10200014 #define cfgBIF_CFG_DEV0_EPF0_1_BASE_ADDR_3 0xfffe10200018 #define cfgBIF_CFG_DEV0_EPF0_1_BASE_ADDR_4 0xfffe1020001c #define cfgBIF_CFG_DEV0_EPF0_1_BASE_ADDR_5 0xfffe10200020 #define cfgBIF_CFG_DEV0_EPF0_1_BASE_ADDR_6 0xfffe10200024 #define cfgBIF_CFG_DEV0_EPF0_1_CARDBUS_CIS_PTR 0xfffe10200028 #define cfgBIF_CFG_DEV0_EPF0_1_ADAPTER_ID 0xfffe1020002c #define cfgBIF_CFG_DEV0_EPF0_1_ROM_BASE_ADDR 0xfffe10200030 #define cfgBIF_CFG_DEV0_EPF0_1_CAP_PTR 0xfffe10200034 #define cfgBIF_CFG_DEV0_EPF0_1_INTERRUPT_LINE 0xfffe1020003c #define cfgBIF_CFG_DEV0_EPF0_1_INTERRUPT_PIN 0xfffe1020003d #define cfgBIF_CFG_DEV0_EPF0_1_MIN_GRANT 0xfffe1020003e #define cfgBIF_CFG_DEV0_EPF0_1_MAX_LATENCY 0xfffe1020003f #define cfgBIF_CFG_DEV0_EPF0_1_VENDOR_CAP_LIST 0xfffe10200048 #define cfgBIF_CFG_DEV0_EPF0_1_ADAPTER_ID_W 0xfffe1020004c #define cfgBIF_CFG_DEV0_EPF0_1_PMI_CAP_LIST 0xfffe10200050 #define cfgBIF_CFG_DEV0_EPF0_1_PMI_CAP 0xfffe10200052 #define cfgBIF_CFG_DEV0_EPF0_1_PMI_STATUS_CNTL 0xfffe10200054 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_CAP_LIST 0xfffe10200064 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_CAP 0xfffe10200066 #define cfgBIF_CFG_DEV0_EPF0_1_DEVICE_CAP 0xfffe10200068 #define cfgBIF_CFG_DEV0_EPF0_1_DEVICE_CNTL 0xfffe1020006c #define cfgBIF_CFG_DEV0_EPF0_1_DEVICE_STATUS 0xfffe1020006e #define cfgBIF_CFG_DEV0_EPF0_1_LINK_CAP 0xfffe10200070 #define cfgBIF_CFG_DEV0_EPF0_1_LINK_CNTL 0xfffe10200074 #define cfgBIF_CFG_DEV0_EPF0_1_LINK_STATUS 0xfffe10200076 #define cfgBIF_CFG_DEV0_EPF0_1_DEVICE_CAP2 0xfffe10200088 #define cfgBIF_CFG_DEV0_EPF0_1_DEVICE_CNTL2 0xfffe1020008c #define cfgBIF_CFG_DEV0_EPF0_1_DEVICE_STATUS2 0xfffe1020008e #define cfgBIF_CFG_DEV0_EPF0_1_LINK_CAP2 0xfffe10200090 #define cfgBIF_CFG_DEV0_EPF0_1_LINK_CNTL2 0xfffe10200094 #define cfgBIF_CFG_DEV0_EPF0_1_LINK_STATUS2 0xfffe10200096 #define cfgBIF_CFG_DEV0_EPF0_1_MSI_CAP_LIST 0xfffe102000a0 #define cfgBIF_CFG_DEV0_EPF0_1_MSI_MSG_CNTL 0xfffe102000a2 #define cfgBIF_CFG_DEV0_EPF0_1_MSI_MSG_ADDR_LO 0xfffe102000a4 #define cfgBIF_CFG_DEV0_EPF0_1_MSI_MSG_ADDR_HI 0xfffe102000a8 #define cfgBIF_CFG_DEV0_EPF0_1_MSI_MSG_DATA 0xfffe102000a8 #define cfgBIF_CFG_DEV0_EPF0_1_MSI_MASK 0xfffe102000ac #define cfgBIF_CFG_DEV0_EPF0_1_MSI_MSG_DATA_64 0xfffe102000ac #define cfgBIF_CFG_DEV0_EPF0_1_MSI_MASK_64 0xfffe102000b0 #define cfgBIF_CFG_DEV0_EPF0_1_MSI_PENDING 0xfffe102000b0 #define cfgBIF_CFG_DEV0_EPF0_1_MSI_PENDING_64 0xfffe102000b4 #define cfgBIF_CFG_DEV0_EPF0_1_MSIX_CAP_LIST 0xfffe102000c0 #define cfgBIF_CFG_DEV0_EPF0_1_MSIX_MSG_CNTL 0xfffe102000c2 #define cfgBIF_CFG_DEV0_EPF0_1_MSIX_TABLE 0xfffe102000c4 #define cfgBIF_CFG_DEV0_EPF0_1_MSIX_PBA 0xfffe102000c8 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0xfffe10200100 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR 0xfffe10200104 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC1 0xfffe10200108 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC2 0xfffe1020010c #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_VC_ENH_CAP_LIST 0xfffe10200110 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_PORT_VC_CAP_REG1 0xfffe10200114 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_PORT_VC_CAP_REG2 0xfffe10200118 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_PORT_VC_CNTL 0xfffe1020011c #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_PORT_VC_STATUS 0xfffe1020011e #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_VC0_RESOURCE_CAP 0xfffe10200120 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_VC0_RESOURCE_CNTL 0xfffe10200124 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_VC0_RESOURCE_STATUS 0xfffe1020012a #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_VC1_RESOURCE_CAP 0xfffe1020012c #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_VC1_RESOURCE_CNTL 0xfffe10200130 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_VC1_RESOURCE_STATUS 0xfffe10200136 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST 0xfffe10200140 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_DEV_SERIAL_NUM_DW1 0xfffe10200144 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_DEV_SERIAL_NUM_DW2 0xfffe10200148 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0xfffe10200150 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_STATUS 0xfffe10200154 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_MASK 0xfffe10200158 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_UNCORR_ERR_SEVERITY 0xfffe1020015c #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_CORR_ERR_STATUS 0xfffe10200160 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_CORR_ERR_MASK 0xfffe10200164 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_ADV_ERR_CAP_CNTL 0xfffe10200168 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_HDR_LOG0 0xfffe1020016c #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_HDR_LOG1 0xfffe10200170 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_HDR_LOG2 0xfffe10200174 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_HDR_LOG3 0xfffe10200178 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_TLP_PREFIX_LOG0 0xfffe10200188 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_TLP_PREFIX_LOG1 0xfffe1020018c #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_TLP_PREFIX_LOG2 0xfffe10200190 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_TLP_PREFIX_LOG3 0xfffe10200194 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_BAR_ENH_CAP_LIST 0xfffe10200200 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_BAR1_CAP 0xfffe10200204 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_BAR1_CNTL 0xfffe10200208 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_BAR2_CAP 0xfffe1020020c #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_BAR2_CNTL 0xfffe10200210 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_BAR3_CAP 0xfffe10200214 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_BAR3_CNTL 0xfffe10200218 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_BAR4_CAP 0xfffe1020021c #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_BAR4_CNTL 0xfffe10200220 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_BAR5_CAP 0xfffe10200224 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_BAR5_CNTL 0xfffe10200228 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_BAR6_CAP 0xfffe1020022c #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_BAR6_CNTL 0xfffe10200230 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_PWR_BUDGET_ENH_CAP_LIST 0xfffe10200240 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_PWR_BUDGET_DATA_SELECT 0xfffe10200244 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_PWR_BUDGET_DATA 0xfffe10200248 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_PWR_BUDGET_CAP 0xfffe1020024c #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_DPA_ENH_CAP_LIST 0xfffe10200250 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_DPA_CAP 0xfffe10200254 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_DPA_LATENCY_INDICATOR 0xfffe10200258 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_DPA_STATUS 0xfffe1020025c #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_DPA_CNTL 0xfffe1020025e #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_0 0xfffe10200260 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_1 0xfffe10200261 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_2 0xfffe10200262 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_3 0xfffe10200263 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_4 0xfffe10200264 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_5 0xfffe10200265 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_6 0xfffe10200266 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_7 0xfffe10200267 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_SECONDARY_ENH_CAP_LIST 0xfffe10200270 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_LINK_CNTL3 0xfffe10200274 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_LANE_ERROR_STATUS 0xfffe10200278 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_LANE_0_EQUALIZATION_CNTL 0xfffe1020027c #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_LANE_1_EQUALIZATION_CNTL 0xfffe1020027e #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_LANE_2_EQUALIZATION_CNTL 0xfffe10200280 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_LANE_3_EQUALIZATION_CNTL 0xfffe10200282 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_LANE_4_EQUALIZATION_CNTL 0xfffe10200284 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_LANE_5_EQUALIZATION_CNTL 0xfffe10200286 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_LANE_6_EQUALIZATION_CNTL 0xfffe10200288 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_LANE_7_EQUALIZATION_CNTL 0xfffe1020028a #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_LANE_8_EQUALIZATION_CNTL 0xfffe1020028c #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_LANE_9_EQUALIZATION_CNTL 0xfffe1020028e #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_LANE_10_EQUALIZATION_CNTL 0xfffe10200290 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_LANE_11_EQUALIZATION_CNTL 0xfffe10200292 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_LANE_12_EQUALIZATION_CNTL 0xfffe10200294 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_LANE_13_EQUALIZATION_CNTL 0xfffe10200296 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_LANE_14_EQUALIZATION_CNTL 0xfffe10200298 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_LANE_15_EQUALIZATION_CNTL 0xfffe1020029a #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_ACS_ENH_CAP_LIST 0xfffe102002a0 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_ACS_CAP 0xfffe102002a4 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_ACS_CNTL 0xfffe102002a6 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_ATS_ENH_CAP_LIST 0xfffe102002b0 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_ATS_CAP 0xfffe102002b4 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_ATS_CNTL 0xfffe102002b6 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_PAGE_REQ_ENH_CAP_LIST 0xfffe102002c0 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_PAGE_REQ_CNTL 0xfffe102002c4 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_PAGE_REQ_STATUS 0xfffe102002c6 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_OUTSTAND_PAGE_REQ_CAPACITY 0xfffe102002c8 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_OUTSTAND_PAGE_REQ_ALLOC 0xfffe102002cc #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_PASID_ENH_CAP_LIST 0xfffe102002d0 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_PASID_CAP 0xfffe102002d4 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_PASID_CNTL 0xfffe102002d6 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_MC_ENH_CAP_LIST 0xfffe102002f0 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_MC_CAP 0xfffe102002f4 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_MC_CNTL 0xfffe102002f6 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_MC_ADDR0 0xfffe102002f8 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_MC_ADDR1 0xfffe102002fc #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_MC_RCV0 0xfffe10200300 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_MC_RCV1 0xfffe10200304 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_MC_BLOCK_ALL0 0xfffe10200308 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_MC_BLOCK_ALL1 0xfffe1020030c #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_MC_BLOCK_UNTRANSLATED_0 0xfffe10200310 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_MC_BLOCK_UNTRANSLATED_1 0xfffe10200314 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_LTR_ENH_CAP_LIST 0xfffe10200320 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_LTR_CAP 0xfffe10200324 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_ARI_ENH_CAP_LIST 0xfffe10200328 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_ARI_CAP 0xfffe1020032c #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_ARI_CNTL 0xfffe1020032e #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_ENH_CAP_LIST 0xfffe10200330 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_CAP 0xfffe10200334 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_CONTROL 0xfffe10200338 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_STATUS 0xfffe1020033a #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_INITIAL_VFS 0xfffe1020033c #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_TOTAL_VFS 0xfffe1020033e #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_NUM_VFS 0xfffe10200340 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_FUNC_DEP_LINK 0xfffe10200342 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_FIRST_VF_OFFSET 0xfffe10200344 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_VF_STRIDE 0xfffe10200346 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_VF_DEVICE_ID 0xfffe1020034a #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_SUPPORTED_PAGE_SIZE 0xfffe1020034c #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_SYSTEM_PAGE_SIZE 0xfffe10200350 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_VF_BASE_ADDR_0 0xfffe10200354 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_VF_BASE_ADDR_1 0xfffe10200358 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_VF_BASE_ADDR_2 0xfffe1020035c #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_VF_BASE_ADDR_3 0xfffe10200360 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_VF_BASE_ADDR_4 0xfffe10200364 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_SRIOV_VF_BASE_ADDR_5 0xfffe10200368 #define your_sha256_hashT 0xfffe1020036c #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_TPH_REQR_ENH_CAP_LIST 0xfffe10200370 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_TPH_REQR_CAP 0xfffe10200374 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_TPH_REQR_CNTL 0xfffe10200378 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_DLF_ENH_CAP_LIST 0xfffe10200400 #define cfgBIF_CFG_DEV0_EPF0_1_DATA_LINK_FEATURE_CAP 0xfffe10200404 #define cfgBIF_CFG_DEV0_EPF0_1_DATA_LINK_FEATURE_STATUS 0xfffe10200408 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_PHY_16GT_ENH_CAP_LIST 0xfffe10200410 #define cfgBIF_CFG_DEV0_EPF0_1_LINK_CAP_16GT 0xfffe10200414 #define cfgBIF_CFG_DEV0_EPF0_1_LINK_CNTL_16GT 0xfffe10200418 #define cfgBIF_CFG_DEV0_EPF0_1_LINK_STATUS_16GT 0xfffe1020041c #define cfgBIF_CFG_DEV0_EPF0_1_LOCAL_PARITY_MISMATCH_STATUS_16GT 0xfffe10200420 #define cfgBIF_CFG_DEV0_EPF0_1_RTM1_PARITY_MISMATCH_STATUS_16GT 0xfffe10200424 #define cfgBIF_CFG_DEV0_EPF0_1_RTM2_PARITY_MISMATCH_STATUS_16GT 0xfffe10200428 #define cfgBIF_CFG_DEV0_EPF0_1_LANE_0_EQUALIZATION_CNTL_16GT 0xfffe10200430 #define cfgBIF_CFG_DEV0_EPF0_1_LANE_1_EQUALIZATION_CNTL_16GT 0xfffe10200431 #define cfgBIF_CFG_DEV0_EPF0_1_LANE_2_EQUALIZATION_CNTL_16GT 0xfffe10200432 #define cfgBIF_CFG_DEV0_EPF0_1_LANE_3_EQUALIZATION_CNTL_16GT 0xfffe10200433 #define cfgBIF_CFG_DEV0_EPF0_1_LANE_4_EQUALIZATION_CNTL_16GT 0xfffe10200434 #define cfgBIF_CFG_DEV0_EPF0_1_LANE_5_EQUALIZATION_CNTL_16GT 0xfffe10200435 #define cfgBIF_CFG_DEV0_EPF0_1_LANE_6_EQUALIZATION_CNTL_16GT 0xfffe10200436 #define cfgBIF_CFG_DEV0_EPF0_1_LANE_7_EQUALIZATION_CNTL_16GT 0xfffe10200437 #define cfgBIF_CFG_DEV0_EPF0_1_LANE_8_EQUALIZATION_CNTL_16GT 0xfffe10200438 #define cfgBIF_CFG_DEV0_EPF0_1_LANE_9_EQUALIZATION_CNTL_16GT 0xfffe10200439 #define cfgBIF_CFG_DEV0_EPF0_1_LANE_10_EQUALIZATION_CNTL_16GT 0xfffe1020043a #define cfgBIF_CFG_DEV0_EPF0_1_LANE_11_EQUALIZATION_CNTL_16GT 0xfffe1020043b #define cfgBIF_CFG_DEV0_EPF0_1_LANE_12_EQUALIZATION_CNTL_16GT 0xfffe1020043c #define cfgBIF_CFG_DEV0_EPF0_1_LANE_13_EQUALIZATION_CNTL_16GT 0xfffe1020043d #define cfgBIF_CFG_DEV0_EPF0_1_LANE_14_EQUALIZATION_CNTL_16GT 0xfffe1020043e #define cfgBIF_CFG_DEV0_EPF0_1_LANE_15_EQUALIZATION_CNTL_16GT 0xfffe1020043f #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_MARGINING_ENH_CAP_LIST 0xfffe10200440 #define cfgBIF_CFG_DEV0_EPF0_1_MARGINING_PORT_CAP 0xfffe10200444 #define cfgBIF_CFG_DEV0_EPF0_1_MARGINING_PORT_STATUS 0xfffe10200446 #define cfgBIF_CFG_DEV0_EPF0_1_LANE_0_MARGINING_LANE_CNTL 0xfffe10200448 #define cfgBIF_CFG_DEV0_EPF0_1_LANE_0_MARGINING_LANE_STATUS 0xfffe1020044a #define cfgBIF_CFG_DEV0_EPF0_1_LANE_1_MARGINING_LANE_CNTL 0xfffe1020044c #define cfgBIF_CFG_DEV0_EPF0_1_LANE_1_MARGINING_LANE_STATUS 0xfffe1020044e #define cfgBIF_CFG_DEV0_EPF0_1_LANE_2_MARGINING_LANE_CNTL 0xfffe10200450 #define cfgBIF_CFG_DEV0_EPF0_1_LANE_2_MARGINING_LANE_STATUS 0xfffe10200452 #define cfgBIF_CFG_DEV0_EPF0_1_LANE_3_MARGINING_LANE_CNTL 0xfffe10200454 #define cfgBIF_CFG_DEV0_EPF0_1_LANE_3_MARGINING_LANE_STATUS 0xfffe10200456 #define cfgBIF_CFG_DEV0_EPF0_1_LANE_4_MARGINING_LANE_CNTL 0xfffe10200458 #define cfgBIF_CFG_DEV0_EPF0_1_LANE_4_MARGINING_LANE_STATUS 0xfffe1020045a #define cfgBIF_CFG_DEV0_EPF0_1_LANE_5_MARGINING_LANE_CNTL 0xfffe1020045c #define cfgBIF_CFG_DEV0_EPF0_1_LANE_5_MARGINING_LANE_STATUS 0xfffe1020045e #define cfgBIF_CFG_DEV0_EPF0_1_LANE_6_MARGINING_LANE_CNTL 0xfffe10200460 #define cfgBIF_CFG_DEV0_EPF0_1_LANE_6_MARGINING_LANE_STATUS 0xfffe10200462 #define cfgBIF_CFG_DEV0_EPF0_1_LANE_7_MARGINING_LANE_CNTL 0xfffe10200464 #define cfgBIF_CFG_DEV0_EPF0_1_LANE_7_MARGINING_LANE_STATUS 0xfffe10200466 #define cfgBIF_CFG_DEV0_EPF0_1_LANE_8_MARGINING_LANE_CNTL 0xfffe10200468 #define cfgBIF_CFG_DEV0_EPF0_1_LANE_8_MARGINING_LANE_STATUS 0xfffe1020046a #define cfgBIF_CFG_DEV0_EPF0_1_LANE_9_MARGINING_LANE_CNTL 0xfffe1020046c #define cfgBIF_CFG_DEV0_EPF0_1_LANE_9_MARGINING_LANE_STATUS 0xfffe1020046e #define cfgBIF_CFG_DEV0_EPF0_1_LANE_10_MARGINING_LANE_CNTL 0xfffe10200470 #define cfgBIF_CFG_DEV0_EPF0_1_LANE_10_MARGINING_LANE_STATUS 0xfffe10200472 #define cfgBIF_CFG_DEV0_EPF0_1_LANE_11_MARGINING_LANE_CNTL 0xfffe10200474 #define cfgBIF_CFG_DEV0_EPF0_1_LANE_11_MARGINING_LANE_STATUS 0xfffe10200476 #define cfgBIF_CFG_DEV0_EPF0_1_LANE_12_MARGINING_LANE_CNTL 0xfffe10200478 #define cfgBIF_CFG_DEV0_EPF0_1_LANE_12_MARGINING_LANE_STATUS 0xfffe1020047a #define cfgBIF_CFG_DEV0_EPF0_1_LANE_13_MARGINING_LANE_CNTL 0xfffe1020047c #define cfgBIF_CFG_DEV0_EPF0_1_LANE_13_MARGINING_LANE_STATUS 0xfffe1020047e #define cfgBIF_CFG_DEV0_EPF0_1_LANE_14_MARGINING_LANE_CNTL 0xfffe10200480 #define cfgBIF_CFG_DEV0_EPF0_1_LANE_14_MARGINING_LANE_STATUS 0xfffe10200482 #define cfgBIF_CFG_DEV0_EPF0_1_LANE_15_MARGINING_LANE_CNTL 0xfffe10200484 #define cfgBIF_CFG_DEV0_EPF0_1_LANE_15_MARGINING_LANE_STATUS 0xfffe10200486 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR_ENH_CAP_LIST 0xfffe102004c0 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR1_CAP 0xfffe102004c4 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR1_CNTL 0xfffe102004c8 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR2_CAP 0xfffe102004cc #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR2_CNTL 0xfffe102004d0 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR3_CAP 0xfffe102004d4 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR3_CNTL 0xfffe102004d8 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR4_CAP 0xfffe102004dc #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR4_CNTL 0xfffe102004e0 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR5_CAP 0xfffe102004e4 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR5_CNTL 0xfffe102004e8 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR6_CAP 0xfffe102004ec #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_VF_RESIZE_BAR6_CNTL 0xfffe102004f0 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV 0xfffe10200500 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV 0xfffe10200504 #define your_sha256_hashDOW 0xfffe10200508 #define your_sha256_hashLE 0xfffe1020050c #define your_sha256_hashUS 0xfffe10200510 #define your_sha256_hashTROL 0xfffe10200514 #define your_sha256_hash_DW0 0xfffe10200518 #define your_sha256_hash_DW1 0xfffe1020051c #define your_sha256_hash_DW2 0xfffe10200520 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CONTEXT 0xfffe10200524 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_TOTAL_FB 0xfffe10200528 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS 0xfffe1020052c #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_REGION 0xfffe10200530 #define your_sha256_hashXGMI_ENABLE 0xfffe10200534 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF0_FB 0xfffe10200538 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF1_FB 0xfffe1020053c #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF2_FB 0xfffe10200540 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF3_FB 0xfffe10200544 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF4_FB 0xfffe10200548 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF5_FB 0xfffe1020054c #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF6_FB 0xfffe10200550 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF7_FB 0xfffe10200554 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF8_FB 0xfffe10200558 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF9_FB 0xfffe1020055c #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF10_FB 0xfffe10200560 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF11_FB 0xfffe10200564 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF12_FB 0xfffe10200568 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF13_FB 0xfffe1020056c #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF14_FB 0xfffe10200570 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF15_FB 0xfffe10200574 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF16_FB 0xfffe10200578 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF17_FB 0xfffe1020057c #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF18_FB 0xfffe10200580 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF19_FB 0xfffe10200584 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF20_FB 0xfffe10200588 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF21_FB 0xfffe1020058c #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF22_FB 0xfffe10200590 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF23_FB 0xfffe10200594 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF24_FB 0xfffe10200598 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF25_FB 0xfffe1020059c #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF26_FB 0xfffe102005a0 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF27_FB 0xfffe102005a4 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF28_FB 0xfffe102005a8 #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF29_FB 0xfffe102005ac #define cfgBIF_CFG_DEV0_EPF0_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF30_FB 0xfffe102005b0 #define your_sha256_hash0 0xfffe102005c0 #define your_sha256_hash1 0xfffe102005c4 #define your_sha256_hash2 0xfffe102005c8 #define your_sha256_hash3 0xfffe102005cc #define your_sha256_hash4 0xfffe102005d0 #define your_sha256_hash5 0xfffe102005d4 #define your_sha256_hash6 0xfffe102005d8 #define your_sha256_hash7 0xfffe102005dc #define your_sha256_hash8 0xfffe102005e0 #define your_sha256_hash0 0xfffe102005f0 #define your_sha256_hash1 0xfffe102005f4 #define your_sha256_hash2 0xfffe102005f8 #define your_sha256_hash3 0xfffe102005fc #define your_sha256_hash4 0xfffe10200600 #define your_sha256_hash5 0xfffe10200604 #define your_sha256_hash6 0xfffe10200608 #define your_sha256_hash7 0xfffe1020060c #define your_sha256_hash8 0xfffe10200610 #define your_sha256_hash0 0xfffe10200620 #define your_sha256_hash1 0xfffe10200624 #define your_sha256_hash2 0xfffe10200628 #define your_sha256_hash3 0xfffe1020062c #define your_sha256_hash4 0xfffe10200630 #define your_sha256_hash5 0xfffe10200634 #define your_sha256_hash6 0xfffe10200638 #define your_sha256_hash7 0xfffe1020063c #define your_sha256_hash8 0xfffe10200640 #define your_sha256_hashW0 0xfffe10200650 #define your_sha256_hashW1 0xfffe10200654 #define your_sha256_hashW2 0xfffe10200658 #define your_sha256_hashW3 0xfffe1020065c #define your_sha256_hashW4 0xfffe10200660 #define your_sha256_hashW5 0xfffe10200664 #define your_sha256_hashW6 0xfffe10200668 #define your_sha256_hashW7 0xfffe1020066c #define your_sha256_hashW8 0xfffe10200670 // addressBlock: nbio_nbif0_bif_cfg_dev0_epf1_bifcfgdecp // base address: 0xfffe10201000 #define cfgBIF_CFG_DEV0_EPF1_1_VENDOR_ID 0xfffe10201000 #define cfgBIF_CFG_DEV0_EPF1_1_DEVICE_ID 0xfffe10201002 #define cfgBIF_CFG_DEV0_EPF1_1_COMMAND 0xfffe10201004 #define cfgBIF_CFG_DEV0_EPF1_1_STATUS 0xfffe10201006 #define cfgBIF_CFG_DEV0_EPF1_1_REVISION_ID 0xfffe10201008 #define cfgBIF_CFG_DEV0_EPF1_1_PROG_INTERFACE 0xfffe10201009 #define cfgBIF_CFG_DEV0_EPF1_1_SUB_CLASS 0xfffe1020100a #define cfgBIF_CFG_DEV0_EPF1_1_BASE_CLASS 0xfffe1020100b #define cfgBIF_CFG_DEV0_EPF1_1_CACHE_LINE 0xfffe1020100c #define cfgBIF_CFG_DEV0_EPF1_1_LATENCY 0xfffe1020100d #define cfgBIF_CFG_DEV0_EPF1_1_HEADER 0xfffe1020100e #define cfgBIF_CFG_DEV0_EPF1_1_BIST 0xfffe1020100f #define cfgBIF_CFG_DEV0_EPF1_1_BASE_ADDR_1 0xfffe10201010 #define cfgBIF_CFG_DEV0_EPF1_1_BASE_ADDR_2 0xfffe10201014 #define cfgBIF_CFG_DEV0_EPF1_1_BASE_ADDR_3 0xfffe10201018 #define cfgBIF_CFG_DEV0_EPF1_1_BASE_ADDR_4 0xfffe1020101c #define cfgBIF_CFG_DEV0_EPF1_1_BASE_ADDR_5 0xfffe10201020 #define cfgBIF_CFG_DEV0_EPF1_1_BASE_ADDR_6 0xfffe10201024 #define cfgBIF_CFG_DEV0_EPF1_1_CARDBUS_CIS_PTR 0xfffe10201028 #define cfgBIF_CFG_DEV0_EPF1_1_ADAPTER_ID 0xfffe1020102c #define cfgBIF_CFG_DEV0_EPF1_1_ROM_BASE_ADDR 0xfffe10201030 #define cfgBIF_CFG_DEV0_EPF1_1_CAP_PTR 0xfffe10201034 #define cfgBIF_CFG_DEV0_EPF1_1_INTERRUPT_LINE 0xfffe1020103c #define cfgBIF_CFG_DEV0_EPF1_1_INTERRUPT_PIN 0xfffe1020103d #define cfgBIF_CFG_DEV0_EPF1_1_MIN_GRANT 0xfffe1020103e #define cfgBIF_CFG_DEV0_EPF1_1_MAX_LATENCY 0xfffe1020103f #define cfgBIF_CFG_DEV0_EPF1_1_VENDOR_CAP_LIST 0xfffe10201048 #define cfgBIF_CFG_DEV0_EPF1_1_ADAPTER_ID_W 0xfffe1020104c #define cfgBIF_CFG_DEV0_EPF1_1_PMI_CAP_LIST 0xfffe10201050 #define cfgBIF_CFG_DEV0_EPF1_1_PMI_CAP 0xfffe10201052 #define cfgBIF_CFG_DEV0_EPF1_1_PMI_STATUS_CNTL 0xfffe10201054 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_CAP_LIST 0xfffe10201064 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_CAP 0xfffe10201066 #define cfgBIF_CFG_DEV0_EPF1_1_DEVICE_CAP 0xfffe10201068 #define cfgBIF_CFG_DEV0_EPF1_1_DEVICE_CNTL 0xfffe1020106c #define cfgBIF_CFG_DEV0_EPF1_1_DEVICE_STATUS 0xfffe1020106e #define cfgBIF_CFG_DEV0_EPF1_1_LINK_CAP 0xfffe10201070 #define cfgBIF_CFG_DEV0_EPF1_1_LINK_CNTL 0xfffe10201074 #define cfgBIF_CFG_DEV0_EPF1_1_LINK_STATUS 0xfffe10201076 #define cfgBIF_CFG_DEV0_EPF1_1_DEVICE_CAP2 0xfffe10201088 #define cfgBIF_CFG_DEV0_EPF1_1_DEVICE_CNTL2 0xfffe1020108c #define cfgBIF_CFG_DEV0_EPF1_1_DEVICE_STATUS2 0xfffe1020108e #define cfgBIF_CFG_DEV0_EPF1_1_LINK_CAP2 0xfffe10201090 #define cfgBIF_CFG_DEV0_EPF1_1_LINK_CNTL2 0xfffe10201094 #define cfgBIF_CFG_DEV0_EPF1_1_LINK_STATUS2 0xfffe10201096 #define cfgBIF_CFG_DEV0_EPF1_1_MSI_CAP_LIST 0xfffe102010a0 #define cfgBIF_CFG_DEV0_EPF1_1_MSI_MSG_CNTL 0xfffe102010a2 #define cfgBIF_CFG_DEV0_EPF1_1_MSI_MSG_ADDR_LO 0xfffe102010a4 #define cfgBIF_CFG_DEV0_EPF1_1_MSI_MSG_ADDR_HI 0xfffe102010a8 #define cfgBIF_CFG_DEV0_EPF1_1_MSI_MSG_DATA 0xfffe102010a8 #define cfgBIF_CFG_DEV0_EPF1_1_MSI_MASK 0xfffe102010ac #define cfgBIF_CFG_DEV0_EPF1_1_MSI_MSG_DATA_64 0xfffe102010ac #define cfgBIF_CFG_DEV0_EPF1_1_MSI_MASK_64 0xfffe102010b0 #define cfgBIF_CFG_DEV0_EPF1_1_MSI_PENDING 0xfffe102010b0 #define cfgBIF_CFG_DEV0_EPF1_1_MSI_PENDING_64 0xfffe102010b4 #define cfgBIF_CFG_DEV0_EPF1_1_MSIX_CAP_LIST 0xfffe102010c0 #define cfgBIF_CFG_DEV0_EPF1_1_MSIX_MSG_CNTL 0xfffe102010c2 #define cfgBIF_CFG_DEV0_EPF1_1_MSIX_TABLE 0xfffe102010c4 #define cfgBIF_CFG_DEV0_EPF1_1_MSIX_PBA 0xfffe102010c8 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0xfffe10201100 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR 0xfffe10201104 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC1 0xfffe10201108 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC2 0xfffe1020110c #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_VC_ENH_CAP_LIST 0xfffe10201110 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_PORT_VC_CAP_REG1 0xfffe10201114 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_PORT_VC_CAP_REG2 0xfffe10201118 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_PORT_VC_CNTL 0xfffe1020111c #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_PORT_VC_STATUS 0xfffe1020111e #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_VC0_RESOURCE_CAP 0xfffe10201120 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_VC0_RESOURCE_CNTL 0xfffe10201124 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_VC0_RESOURCE_STATUS 0xfffe1020112a #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_VC1_RESOURCE_CAP 0xfffe1020112c #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_VC1_RESOURCE_CNTL 0xfffe10201130 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_VC1_RESOURCE_STATUS 0xfffe10201136 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST 0xfffe10201140 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_DEV_SERIAL_NUM_DW1 0xfffe10201144 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_DEV_SERIAL_NUM_DW2 0xfffe10201148 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0xfffe10201150 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_STATUS 0xfffe10201154 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_MASK 0xfffe10201158 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_UNCORR_ERR_SEVERITY 0xfffe1020115c #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_CORR_ERR_STATUS 0xfffe10201160 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_CORR_ERR_MASK 0xfffe10201164 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_ADV_ERR_CAP_CNTL 0xfffe10201168 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_HDR_LOG0 0xfffe1020116c #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_HDR_LOG1 0xfffe10201170 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_HDR_LOG2 0xfffe10201174 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_HDR_LOG3 0xfffe10201178 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_TLP_PREFIX_LOG0 0xfffe10201188 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_TLP_PREFIX_LOG1 0xfffe1020118c #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_TLP_PREFIX_LOG2 0xfffe10201190 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_TLP_PREFIX_LOG3 0xfffe10201194 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_BAR_ENH_CAP_LIST 0xfffe10201200 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_BAR1_CAP 0xfffe10201204 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_BAR1_CNTL 0xfffe10201208 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_BAR2_CAP 0xfffe1020120c #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_BAR2_CNTL 0xfffe10201210 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_BAR3_CAP 0xfffe10201214 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_BAR3_CNTL 0xfffe10201218 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_BAR4_CAP 0xfffe1020121c #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_BAR4_CNTL 0xfffe10201220 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_BAR5_CAP 0xfffe10201224 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_BAR5_CNTL 0xfffe10201228 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_BAR6_CAP 0xfffe1020122c #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_BAR6_CNTL 0xfffe10201230 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_PWR_BUDGET_ENH_CAP_LIST 0xfffe10201240 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_PWR_BUDGET_DATA_SELECT 0xfffe10201244 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_PWR_BUDGET_DATA 0xfffe10201248 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_PWR_BUDGET_CAP 0xfffe1020124c #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_DPA_ENH_CAP_LIST 0xfffe10201250 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_DPA_CAP 0xfffe10201254 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_DPA_LATENCY_INDICATOR 0xfffe10201258 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_DPA_STATUS 0xfffe1020125c #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_DPA_CNTL 0xfffe1020125e #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_0 0xfffe10201260 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_1 0xfffe10201261 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_2 0xfffe10201262 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_3 0xfffe10201263 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_4 0xfffe10201264 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_5 0xfffe10201265 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_6 0xfffe10201266 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_7 0xfffe10201267 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_SECONDARY_ENH_CAP_LIST 0xfffe10201270 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_LINK_CNTL3 0xfffe10201274 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_LANE_ERROR_STATUS 0xfffe10201278 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_LANE_0_EQUALIZATION_CNTL 0xfffe1020127c #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_LANE_1_EQUALIZATION_CNTL 0xfffe1020127e #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_LANE_2_EQUALIZATION_CNTL 0xfffe10201280 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_LANE_3_EQUALIZATION_CNTL 0xfffe10201282 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_LANE_4_EQUALIZATION_CNTL 0xfffe10201284 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_LANE_5_EQUALIZATION_CNTL 0xfffe10201286 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_LANE_6_EQUALIZATION_CNTL 0xfffe10201288 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_LANE_7_EQUALIZATION_CNTL 0xfffe1020128a #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_LANE_8_EQUALIZATION_CNTL 0xfffe1020128c #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_LANE_9_EQUALIZATION_CNTL 0xfffe1020128e #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_LANE_10_EQUALIZATION_CNTL 0xfffe10201290 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_LANE_11_EQUALIZATION_CNTL 0xfffe10201292 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_LANE_12_EQUALIZATION_CNTL 0xfffe10201294 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_LANE_13_EQUALIZATION_CNTL 0xfffe10201296 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_LANE_14_EQUALIZATION_CNTL 0xfffe10201298 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_LANE_15_EQUALIZATION_CNTL 0xfffe1020129a #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_ACS_ENH_CAP_LIST 0xfffe102012a0 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_ACS_CAP 0xfffe102012a4 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_ACS_CNTL 0xfffe102012a6 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_ATS_ENH_CAP_LIST 0xfffe102012b0 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_ATS_CAP 0xfffe102012b4 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_ATS_CNTL 0xfffe102012b6 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_PAGE_REQ_ENH_CAP_LIST 0xfffe102012c0 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_PAGE_REQ_CNTL 0xfffe102012c4 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_PAGE_REQ_STATUS 0xfffe102012c6 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_OUTSTAND_PAGE_REQ_CAPACITY 0xfffe102012c8 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_OUTSTAND_PAGE_REQ_ALLOC 0xfffe102012cc #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_PASID_ENH_CAP_LIST 0xfffe102012d0 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_PASID_CAP 0xfffe102012d4 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_PASID_CNTL 0xfffe102012d6 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_MC_ENH_CAP_LIST 0xfffe102012f0 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_MC_CAP 0xfffe102012f4 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_MC_CNTL 0xfffe102012f6 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_MC_ADDR0 0xfffe102012f8 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_MC_ADDR1 0xfffe102012fc #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_MC_RCV0 0xfffe10201300 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_MC_RCV1 0xfffe10201304 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_MC_BLOCK_ALL0 0xfffe10201308 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_MC_BLOCK_ALL1 0xfffe1020130c #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_MC_BLOCK_UNTRANSLATED_0 0xfffe10201310 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_MC_BLOCK_UNTRANSLATED_1 0xfffe10201314 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_LTR_ENH_CAP_LIST 0xfffe10201320 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_LTR_CAP 0xfffe10201324 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_ARI_ENH_CAP_LIST 0xfffe10201328 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_ARI_CAP 0xfffe1020132c #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_ARI_CNTL 0xfffe1020132e #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_ENH_CAP_LIST 0xfffe10201330 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_CAP 0xfffe10201334 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_CONTROL 0xfffe10201338 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_STATUS 0xfffe1020133a #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_INITIAL_VFS 0xfffe1020133c #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_TOTAL_VFS 0xfffe1020133e #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_NUM_VFS 0xfffe10201340 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_FUNC_DEP_LINK 0xfffe10201342 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_FIRST_VF_OFFSET 0xfffe10201344 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_VF_STRIDE 0xfffe10201346 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_VF_DEVICE_ID 0xfffe1020134a #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_SUPPORTED_PAGE_SIZE 0xfffe1020134c #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_SYSTEM_PAGE_SIZE 0xfffe10201350 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_VF_BASE_ADDR_0 0xfffe10201354 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_VF_BASE_ADDR_1 0xfffe10201358 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_VF_BASE_ADDR_2 0xfffe1020135c #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_VF_BASE_ADDR_3 0xfffe10201360 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_VF_BASE_ADDR_4 0xfffe10201364 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_SRIOV_VF_BASE_ADDR_5 0xfffe10201368 #define your_sha256_hashT 0xfffe1020136c #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_TPH_REQR_ENH_CAP_LIST 0xfffe10201370 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_TPH_REQR_CAP 0xfffe10201374 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_TPH_REQR_CNTL 0xfffe10201378 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_DLF_ENH_CAP_LIST 0xfffe10201400 #define cfgBIF_CFG_DEV0_EPF1_1_DATA_LINK_FEATURE_CAP 0xfffe10201404 #define cfgBIF_CFG_DEV0_EPF1_1_DATA_LINK_FEATURE_STATUS 0xfffe10201408 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_PHY_16GT_ENH_CAP_LIST 0xfffe10201410 #define cfgBIF_CFG_DEV0_EPF1_1_LINK_CAP_16GT 0xfffe10201414 #define cfgBIF_CFG_DEV0_EPF1_1_LINK_CNTL_16GT 0xfffe10201418 #define cfgBIF_CFG_DEV0_EPF1_1_LINK_STATUS_16GT 0xfffe1020141c #define cfgBIF_CFG_DEV0_EPF1_1_LOCAL_PARITY_MISMATCH_STATUS_16GT 0xfffe10201420 #define cfgBIF_CFG_DEV0_EPF1_1_RTM1_PARITY_MISMATCH_STATUS_16GT 0xfffe10201424 #define cfgBIF_CFG_DEV0_EPF1_1_RTM2_PARITY_MISMATCH_STATUS_16GT 0xfffe10201428 #define cfgBIF_CFG_DEV0_EPF1_1_LANE_0_EQUALIZATION_CNTL_16GT 0xfffe10201430 #define cfgBIF_CFG_DEV0_EPF1_1_LANE_1_EQUALIZATION_CNTL_16GT 0xfffe10201431 #define cfgBIF_CFG_DEV0_EPF1_1_LANE_2_EQUALIZATION_CNTL_16GT 0xfffe10201432 #define cfgBIF_CFG_DEV0_EPF1_1_LANE_3_EQUALIZATION_CNTL_16GT 0xfffe10201433 #define cfgBIF_CFG_DEV0_EPF1_1_LANE_4_EQUALIZATION_CNTL_16GT 0xfffe10201434 #define cfgBIF_CFG_DEV0_EPF1_1_LANE_5_EQUALIZATION_CNTL_16GT 0xfffe10201435 #define cfgBIF_CFG_DEV0_EPF1_1_LANE_6_EQUALIZATION_CNTL_16GT 0xfffe10201436 #define cfgBIF_CFG_DEV0_EPF1_1_LANE_7_EQUALIZATION_CNTL_16GT 0xfffe10201437 #define cfgBIF_CFG_DEV0_EPF1_1_LANE_8_EQUALIZATION_CNTL_16GT 0xfffe10201438 #define cfgBIF_CFG_DEV0_EPF1_1_LANE_9_EQUALIZATION_CNTL_16GT 0xfffe10201439 #define cfgBIF_CFG_DEV0_EPF1_1_LANE_10_EQUALIZATION_CNTL_16GT 0xfffe1020143a #define cfgBIF_CFG_DEV0_EPF1_1_LANE_11_EQUALIZATION_CNTL_16GT 0xfffe1020143b #define cfgBIF_CFG_DEV0_EPF1_1_LANE_12_EQUALIZATION_CNTL_16GT 0xfffe1020143c #define cfgBIF_CFG_DEV0_EPF1_1_LANE_13_EQUALIZATION_CNTL_16GT 0xfffe1020143d #define cfgBIF_CFG_DEV0_EPF1_1_LANE_14_EQUALIZATION_CNTL_16GT 0xfffe1020143e #define cfgBIF_CFG_DEV0_EPF1_1_LANE_15_EQUALIZATION_CNTL_16GT 0xfffe1020143f #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_MARGINING_ENH_CAP_LIST 0xfffe10201440 #define cfgBIF_CFG_DEV0_EPF1_1_MARGINING_PORT_CAP 0xfffe10201444 #define cfgBIF_CFG_DEV0_EPF1_1_MARGINING_PORT_STATUS 0xfffe10201446 #define cfgBIF_CFG_DEV0_EPF1_1_LANE_0_MARGINING_LANE_CNTL 0xfffe10201448 #define cfgBIF_CFG_DEV0_EPF1_1_LANE_0_MARGINING_LANE_STATUS 0xfffe1020144a #define cfgBIF_CFG_DEV0_EPF1_1_LANE_1_MARGINING_LANE_CNTL 0xfffe1020144c #define cfgBIF_CFG_DEV0_EPF1_1_LANE_1_MARGINING_LANE_STATUS 0xfffe1020144e #define cfgBIF_CFG_DEV0_EPF1_1_LANE_2_MARGINING_LANE_CNTL 0xfffe10201450 #define cfgBIF_CFG_DEV0_EPF1_1_LANE_2_MARGINING_LANE_STATUS 0xfffe10201452 #define cfgBIF_CFG_DEV0_EPF1_1_LANE_3_MARGINING_LANE_CNTL 0xfffe10201454 #define cfgBIF_CFG_DEV0_EPF1_1_LANE_3_MARGINING_LANE_STATUS 0xfffe10201456 #define cfgBIF_CFG_DEV0_EPF1_1_LANE_4_MARGINING_LANE_CNTL 0xfffe10201458 #define cfgBIF_CFG_DEV0_EPF1_1_LANE_4_MARGINING_LANE_STATUS 0xfffe1020145a #define cfgBIF_CFG_DEV0_EPF1_1_LANE_5_MARGINING_LANE_CNTL 0xfffe1020145c #define cfgBIF_CFG_DEV0_EPF1_1_LANE_5_MARGINING_LANE_STATUS 0xfffe1020145e #define cfgBIF_CFG_DEV0_EPF1_1_LANE_6_MARGINING_LANE_CNTL 0xfffe10201460 #define cfgBIF_CFG_DEV0_EPF1_1_LANE_6_MARGINING_LANE_STATUS 0xfffe10201462 #define cfgBIF_CFG_DEV0_EPF1_1_LANE_7_MARGINING_LANE_CNTL 0xfffe10201464 #define cfgBIF_CFG_DEV0_EPF1_1_LANE_7_MARGINING_LANE_STATUS 0xfffe10201466 #define cfgBIF_CFG_DEV0_EPF1_1_LANE_8_MARGINING_LANE_CNTL 0xfffe10201468 #define cfgBIF_CFG_DEV0_EPF1_1_LANE_8_MARGINING_LANE_STATUS 0xfffe1020146a #define cfgBIF_CFG_DEV0_EPF1_1_LANE_9_MARGINING_LANE_CNTL 0xfffe1020146c #define cfgBIF_CFG_DEV0_EPF1_1_LANE_9_MARGINING_LANE_STATUS 0xfffe1020146e #define cfgBIF_CFG_DEV0_EPF1_1_LANE_10_MARGINING_LANE_CNTL 0xfffe10201470 #define cfgBIF_CFG_DEV0_EPF1_1_LANE_10_MARGINING_LANE_STATUS 0xfffe10201472 #define cfgBIF_CFG_DEV0_EPF1_1_LANE_11_MARGINING_LANE_CNTL 0xfffe10201474 #define cfgBIF_CFG_DEV0_EPF1_1_LANE_11_MARGINING_LANE_STATUS 0xfffe10201476 #define cfgBIF_CFG_DEV0_EPF1_1_LANE_12_MARGINING_LANE_CNTL 0xfffe10201478 #define cfgBIF_CFG_DEV0_EPF1_1_LANE_12_MARGINING_LANE_STATUS 0xfffe1020147a #define cfgBIF_CFG_DEV0_EPF1_1_LANE_13_MARGINING_LANE_CNTL 0xfffe1020147c #define cfgBIF_CFG_DEV0_EPF1_1_LANE_13_MARGINING_LANE_STATUS 0xfffe1020147e #define cfgBIF_CFG_DEV0_EPF1_1_LANE_14_MARGINING_LANE_CNTL 0xfffe10201480 #define cfgBIF_CFG_DEV0_EPF1_1_LANE_14_MARGINING_LANE_STATUS 0xfffe10201482 #define cfgBIF_CFG_DEV0_EPF1_1_LANE_15_MARGINING_LANE_CNTL 0xfffe10201484 #define cfgBIF_CFG_DEV0_EPF1_1_LANE_15_MARGINING_LANE_STATUS 0xfffe10201486 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR_ENH_CAP_LIST 0xfffe102014c0 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR1_CAP 0xfffe102014c4 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR1_CNTL 0xfffe102014c8 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR2_CAP 0xfffe102014cc #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR2_CNTL 0xfffe102014d0 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR3_CAP 0xfffe102014d4 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR3_CNTL 0xfffe102014d8 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR4_CAP 0xfffe102014dc #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR4_CNTL 0xfffe102014e0 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR5_CAP 0xfffe102014e4 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR5_CNTL 0xfffe102014e8 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR6_CAP 0xfffe102014ec #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_VF_RESIZE_BAR6_CNTL 0xfffe102014f0 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV 0xfffe10201500 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV 0xfffe10201504 #define your_sha256_hashDOW 0xfffe10201508 #define your_sha256_hashLE 0xfffe1020150c #define your_sha256_hashUS 0xfffe10201510 #define your_sha256_hashTROL 0xfffe10201514 #define your_sha256_hash_DW0 0xfffe10201518 #define your_sha256_hash_DW1 0xfffe1020151c #define your_sha256_hash_DW2 0xfffe10201520 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CONTEXT 0xfffe10201524 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_TOTAL_FB 0xfffe10201528 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS 0xfffe1020152c #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_REGION 0xfffe10201530 #define your_sha256_hashXGMI_ENABLE 0xfffe10201534 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF0_FB 0xfffe10201538 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF1_FB 0xfffe1020153c #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF2_FB 0xfffe10201540 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF3_FB 0xfffe10201544 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF4_FB 0xfffe10201548 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF5_FB 0xfffe1020154c #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF6_FB 0xfffe10201550 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF7_FB 0xfffe10201554 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF8_FB 0xfffe10201558 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF9_FB 0xfffe1020155c #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF10_FB 0xfffe10201560 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF11_FB 0xfffe10201564 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF12_FB 0xfffe10201568 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF13_FB 0xfffe1020156c #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF14_FB 0xfffe10201570 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF15_FB 0xfffe10201574 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF16_FB 0xfffe10201578 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF17_FB 0xfffe1020157c #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF18_FB 0xfffe10201580 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF19_FB 0xfffe10201584 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF20_FB 0xfffe10201588 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF21_FB 0xfffe1020158c #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF22_FB 0xfffe10201590 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF23_FB 0xfffe10201594 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF24_FB 0xfffe10201598 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF25_FB 0xfffe1020159c #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF26_FB 0xfffe102015a0 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF27_FB 0xfffe102015a4 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF28_FB 0xfffe102015a8 #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF29_FB 0xfffe102015ac #define cfgBIF_CFG_DEV0_EPF1_1_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF30_FB 0xfffe102015b0 #define your_sha256_hash0 0xfffe102015c0 #define your_sha256_hash1 0xfffe102015c4 #define your_sha256_hash2 0xfffe102015c8 #define your_sha256_hash3 0xfffe102015cc #define your_sha256_hash4 0xfffe102015d0 #define your_sha256_hash5 0xfffe102015d4 #define your_sha256_hash6 0xfffe102015d8 #define your_sha256_hash7 0xfffe102015dc #define your_sha256_hash8 0xfffe102015e0 #define your_sha256_hash0 0xfffe102015f0 #define your_sha256_hash1 0xfffe102015f4 #define your_sha256_hash2 0xfffe102015f8 #define your_sha256_hash3 0xfffe102015fc #define your_sha256_hash4 0xfffe10201600 #define your_sha256_hash5 0xfffe10201604 #define your_sha256_hash6 0xfffe10201608 #define your_sha256_hash7 0xfffe1020160c #define your_sha256_hash8 0xfffe10201610 #define your_sha256_hash0 0xfffe10201620 #define your_sha256_hash1 0xfffe10201624 #define your_sha256_hash2 0xfffe10201628 #define your_sha256_hash3 0xfffe1020162c #define your_sha256_hash4 0xfffe10201630 #define your_sha256_hash5 0xfffe10201634 #define your_sha256_hash6 0xfffe10201638 #define your_sha256_hash7 0xfffe1020163c #define your_sha256_hash8 0xfffe10201640 #define your_sha256_hashW0 0xfffe10201650 #define your_sha256_hashW1 0xfffe10201654 #define your_sha256_hashW2 0xfffe10201658 #define your_sha256_hashW3 0xfffe1020165c #define your_sha256_hashW4 0xfffe10201660 #define your_sha256_hashW5 0xfffe10201664 #define your_sha256_hashW6 0xfffe10201668 #define your_sha256_hashW7 0xfffe1020166c #define your_sha256_hashW8 0xfffe10201670 // addressBlock: nbio_nbif0_bif_cfg_dev0_epf2_bifcfgdecp // base address: 0xfffe10202000 #define cfgBIF_CFG_DEV0_EPF2_1_VENDOR_ID 0xfffe10202000 #define cfgBIF_CFG_DEV0_EPF2_1_DEVICE_ID 0xfffe10202002 #define cfgBIF_CFG_DEV0_EPF2_1_COMMAND 0xfffe10202004 #define cfgBIF_CFG_DEV0_EPF2_1_STATUS 0xfffe10202006 #define cfgBIF_CFG_DEV0_EPF2_1_REVISION_ID 0xfffe10202008 #define cfgBIF_CFG_DEV0_EPF2_1_PROG_INTERFACE 0xfffe10202009 #define cfgBIF_CFG_DEV0_EPF2_1_SUB_CLASS 0xfffe1020200a #define cfgBIF_CFG_DEV0_EPF2_1_BASE_CLASS 0xfffe1020200b #define cfgBIF_CFG_DEV0_EPF2_1_CACHE_LINE 0xfffe1020200c #define cfgBIF_CFG_DEV0_EPF2_1_LATENCY 0xfffe1020200d #define cfgBIF_CFG_DEV0_EPF2_1_HEADER 0xfffe1020200e #define cfgBIF_CFG_DEV0_EPF2_1_BIST 0xfffe1020200f #define cfgBIF_CFG_DEV0_EPF2_1_BASE_ADDR_1 0xfffe10202010 #define cfgBIF_CFG_DEV0_EPF2_1_BASE_ADDR_2 0xfffe10202014 #define cfgBIF_CFG_DEV0_EPF2_1_BASE_ADDR_3 0xfffe10202018 #define cfgBIF_CFG_DEV0_EPF2_1_BASE_ADDR_4 0xfffe1020201c #define cfgBIF_CFG_DEV0_EPF2_1_BASE_ADDR_5 0xfffe10202020 #define cfgBIF_CFG_DEV0_EPF2_1_BASE_ADDR_6 0xfffe10202024 #define cfgBIF_CFG_DEV0_EPF2_1_CARDBUS_CIS_PTR 0xfffe10202028 #define cfgBIF_CFG_DEV0_EPF2_1_ADAPTER_ID 0xfffe1020202c #define cfgBIF_CFG_DEV0_EPF2_1_ROM_BASE_ADDR 0xfffe10202030 #define cfgBIF_CFG_DEV0_EPF2_1_CAP_PTR 0xfffe10202034 #define cfgBIF_CFG_DEV0_EPF2_1_INTERRUPT_LINE 0xfffe1020203c #define cfgBIF_CFG_DEV0_EPF2_1_INTERRUPT_PIN 0xfffe1020203d #define cfgBIF_CFG_DEV0_EPF2_1_MIN_GRANT 0xfffe1020203e #define cfgBIF_CFG_DEV0_EPF2_1_MAX_LATENCY 0xfffe1020203f #define cfgBIF_CFG_DEV0_EPF2_1_VENDOR_CAP_LIST 0xfffe10202048 #define cfgBIF_CFG_DEV0_EPF2_1_ADAPTER_ID_W 0xfffe1020204c #define cfgBIF_CFG_DEV0_EPF2_1_PMI_CAP_LIST 0xfffe10202050 #define cfgBIF_CFG_DEV0_EPF2_1_PMI_CAP 0xfffe10202052 #define cfgBIF_CFG_DEV0_EPF2_1_PMI_STATUS_CNTL 0xfffe10202054 #define cfgBIF_CFG_DEV0_EPF2_1_SBRN 0xfffe10202060 #define cfgBIF_CFG_DEV0_EPF2_1_FLADJ 0xfffe10202061 #define cfgBIF_CFG_DEV0_EPF2_1_DBESL_DBESLD 0xfffe10202062 #define cfgBIF_CFG_DEV0_EPF2_1_PCIE_CAP_LIST 0xfffe10202064 #define cfgBIF_CFG_DEV0_EPF2_1_PCIE_CAP 0xfffe10202066 #define cfgBIF_CFG_DEV0_EPF2_1_DEVICE_CAP 0xfffe10202068 #define cfgBIF_CFG_DEV0_EPF2_1_DEVICE_CNTL 0xfffe1020206c #define cfgBIF_CFG_DEV0_EPF2_1_DEVICE_STATUS 0xfffe1020206e #define cfgBIF_CFG_DEV0_EPF2_1_LINK_CAP 0xfffe10202070 #define cfgBIF_CFG_DEV0_EPF2_1_LINK_CNTL 0xfffe10202074 #define cfgBIF_CFG_DEV0_EPF2_1_LINK_STATUS 0xfffe10202076 #define cfgBIF_CFG_DEV0_EPF2_1_DEVICE_CAP2 0xfffe10202088 #define cfgBIF_CFG_DEV0_EPF2_1_DEVICE_CNTL2 0xfffe1020208c #define cfgBIF_CFG_DEV0_EPF2_1_DEVICE_STATUS2 0xfffe1020208e #define cfgBIF_CFG_DEV0_EPF2_1_LINK_CAP2 0xfffe10202090 #define cfgBIF_CFG_DEV0_EPF2_1_LINK_CNTL2 0xfffe10202094 #define cfgBIF_CFG_DEV0_EPF2_1_LINK_STATUS2 0xfffe10202096 #define cfgBIF_CFG_DEV0_EPF2_1_MSI_CAP_LIST 0xfffe102020a0 #define cfgBIF_CFG_DEV0_EPF2_1_MSI_MSG_CNTL 0xfffe102020a2 #define cfgBIF_CFG_DEV0_EPF2_1_MSI_MSG_ADDR_LO 0xfffe102020a4 #define cfgBIF_CFG_DEV0_EPF2_1_MSI_MSG_ADDR_HI 0xfffe102020a8 #define cfgBIF_CFG_DEV0_EPF2_1_MSI_MSG_DATA 0xfffe102020a8 #define cfgBIF_CFG_DEV0_EPF2_1_MSI_MASK 0xfffe102020ac #define cfgBIF_CFG_DEV0_EPF2_1_MSI_MSG_DATA_64 0xfffe102020ac #define cfgBIF_CFG_DEV0_EPF2_1_MSI_MASK_64 0xfffe102020b0 #define cfgBIF_CFG_DEV0_EPF2_1_MSI_PENDING 0xfffe102020b0 #define cfgBIF_CFG_DEV0_EPF2_1_MSI_PENDING_64 0xfffe102020b4 #define cfgBIF_CFG_DEV0_EPF2_1_MSIX_CAP_LIST 0xfffe102020c0 #define cfgBIF_CFG_DEV0_EPF2_1_MSIX_MSG_CNTL 0xfffe102020c2 #define cfgBIF_CFG_DEV0_EPF2_1_MSIX_TABLE 0xfffe102020c4 #define cfgBIF_CFG_DEV0_EPF2_1_MSIX_PBA 0xfffe102020c8 #define cfgBIF_CFG_DEV0_EPF2_1_SATA_CAP_0 0xfffe102020d0 #define cfgBIF_CFG_DEV0_EPF2_1_SATA_CAP_1 0xfffe102020d4 #define cfgBIF_CFG_DEV0_EPF2_1_SATA_IDP_INDEX 0xfffe102020d8 #define cfgBIF_CFG_DEV0_EPF2_1_SATA_IDP_DATA 0xfffe102020dc #define cfgBIF_CFG_DEV0_EPF2_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0xfffe10202100 #define cfgBIF_CFG_DEV0_EPF2_1_PCIE_VENDOR_SPECIFIC_HDR 0xfffe10202104 #define cfgBIF_CFG_DEV0_EPF2_1_PCIE_VENDOR_SPECIFIC1 0xfffe10202108 #define cfgBIF_CFG_DEV0_EPF2_1_PCIE_VENDOR_SPECIFIC2 0xfffe1020210c #define cfgBIF_CFG_DEV0_EPF2_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0xfffe10202150 #define cfgBIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_STATUS 0xfffe10202154 #define cfgBIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_MASK 0xfffe10202158 #define cfgBIF_CFG_DEV0_EPF2_1_PCIE_UNCORR_ERR_SEVERITY 0xfffe1020215c #define cfgBIF_CFG_DEV0_EPF2_1_PCIE_CORR_ERR_STATUS 0xfffe10202160 #define cfgBIF_CFG_DEV0_EPF2_1_PCIE_CORR_ERR_MASK 0xfffe10202164 #define cfgBIF_CFG_DEV0_EPF2_1_PCIE_ADV_ERR_CAP_CNTL 0xfffe10202168 #define cfgBIF_CFG_DEV0_EPF2_1_PCIE_HDR_LOG0 0xfffe1020216c #define cfgBIF_CFG_DEV0_EPF2_1_PCIE_HDR_LOG1 0xfffe10202170 #define cfgBIF_CFG_DEV0_EPF2_1_PCIE_HDR_LOG2 0xfffe10202174 #define cfgBIF_CFG_DEV0_EPF2_1_PCIE_HDR_LOG3 0xfffe10202178 #define cfgBIF_CFG_DEV0_EPF2_1_PCIE_TLP_PREFIX_LOG0 0xfffe10202188 #define cfgBIF_CFG_DEV0_EPF2_1_PCIE_TLP_PREFIX_LOG1 0xfffe1020218c #define cfgBIF_CFG_DEV0_EPF2_1_PCIE_TLP_PREFIX_LOG2 0xfffe10202190 #define cfgBIF_CFG_DEV0_EPF2_1_PCIE_TLP_PREFIX_LOG3 0xfffe10202194 #define cfgBIF_CFG_DEV0_EPF2_1_PCIE_BAR_ENH_CAP_LIST 0xfffe10202200 #define cfgBIF_CFG_DEV0_EPF2_1_PCIE_BAR1_CAP 0xfffe10202204 #define cfgBIF_CFG_DEV0_EPF2_1_PCIE_BAR1_CNTL 0xfffe10202208 #define cfgBIF_CFG_DEV0_EPF2_1_PCIE_BAR2_CAP 0xfffe1020220c #define cfgBIF_CFG_DEV0_EPF2_1_PCIE_BAR2_CNTL 0xfffe10202210 #define cfgBIF_CFG_DEV0_EPF2_1_PCIE_BAR3_CAP 0xfffe10202214 #define cfgBIF_CFG_DEV0_EPF2_1_PCIE_BAR3_CNTL 0xfffe10202218 #define cfgBIF_CFG_DEV0_EPF2_1_PCIE_BAR4_CAP 0xfffe1020221c #define cfgBIF_CFG_DEV0_EPF2_1_PCIE_BAR4_CNTL 0xfffe10202220 #define cfgBIF_CFG_DEV0_EPF2_1_PCIE_BAR5_CAP 0xfffe10202224 #define cfgBIF_CFG_DEV0_EPF2_1_PCIE_BAR5_CNTL 0xfffe10202228 #define cfgBIF_CFG_DEV0_EPF2_1_PCIE_BAR6_CAP 0xfffe1020222c #define cfgBIF_CFG_DEV0_EPF2_1_PCIE_BAR6_CNTL 0xfffe10202230 #define cfgBIF_CFG_DEV0_EPF2_1_PCIE_PWR_BUDGET_ENH_CAP_LIST 0xfffe10202240 #define cfgBIF_CFG_DEV0_EPF2_1_PCIE_PWR_BUDGET_DATA_SELECT 0xfffe10202244 #define cfgBIF_CFG_DEV0_EPF2_1_PCIE_PWR_BUDGET_DATA 0xfffe10202248 #define cfgBIF_CFG_DEV0_EPF2_1_PCIE_PWR_BUDGET_CAP 0xfffe1020224c #define cfgBIF_CFG_DEV0_EPF2_1_PCIE_DPA_ENH_CAP_LIST 0xfffe10202250 #define cfgBIF_CFG_DEV0_EPF2_1_PCIE_DPA_CAP 0xfffe10202254 #define cfgBIF_CFG_DEV0_EPF2_1_PCIE_DPA_LATENCY_INDICATOR 0xfffe10202258 #define cfgBIF_CFG_DEV0_EPF2_1_PCIE_DPA_STATUS 0xfffe1020225c #define cfgBIF_CFG_DEV0_EPF2_1_PCIE_DPA_CNTL 0xfffe1020225e #define cfgBIF_CFG_DEV0_EPF2_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_0 0xfffe10202260 #define cfgBIF_CFG_DEV0_EPF2_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_1 0xfffe10202261 #define cfgBIF_CFG_DEV0_EPF2_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_2 0xfffe10202262 #define cfgBIF_CFG_DEV0_EPF2_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_3 0xfffe10202263 #define cfgBIF_CFG_DEV0_EPF2_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_4 0xfffe10202264 #define cfgBIF_CFG_DEV0_EPF2_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_5 0xfffe10202265 #define cfgBIF_CFG_DEV0_EPF2_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_6 0xfffe10202266 #define cfgBIF_CFG_DEV0_EPF2_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_7 0xfffe10202267 #define cfgBIF_CFG_DEV0_EPF2_1_PCIE_ACS_ENH_CAP_LIST 0xfffe102022a0 #define cfgBIF_CFG_DEV0_EPF2_1_PCIE_ACS_CAP 0xfffe102022a4 #define cfgBIF_CFG_DEV0_EPF2_1_PCIE_ACS_CNTL 0xfffe102022a6 #define cfgBIF_CFG_DEV0_EPF2_1_PCIE_PASID_ENH_CAP_LIST 0xfffe102022d0 #define cfgBIF_CFG_DEV0_EPF2_1_PCIE_PASID_CAP 0xfffe102022d4 #define cfgBIF_CFG_DEV0_EPF2_1_PCIE_PASID_CNTL 0xfffe102022d6 #define cfgBIF_CFG_DEV0_EPF2_1_PCIE_ARI_ENH_CAP_LIST 0xfffe10202328 #define cfgBIF_CFG_DEV0_EPF2_1_PCIE_ARI_CAP 0xfffe1020232c #define cfgBIF_CFG_DEV0_EPF2_1_PCIE_ARI_CNTL 0xfffe1020232e #define cfgBIF_CFG_DEV0_EPF2_1_PCIE_TPH_REQR_ENH_CAP_LIST 0xfffe10202370 #define cfgBIF_CFG_DEV0_EPF2_1_PCIE_TPH_REQR_CAP 0xfffe10202374 #define cfgBIF_CFG_DEV0_EPF2_1_PCIE_TPH_REQR_CNTL 0xfffe10202378 #define cfgBIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_0 0xfffe1020237c #define cfgBIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_1 0xfffe1020237e #define cfgBIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_2 0xfffe10202380 #define cfgBIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_3 0xfffe10202382 #define cfgBIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_4 0xfffe10202384 #define cfgBIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_5 0xfffe10202386 #define cfgBIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_6 0xfffe10202388 #define cfgBIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_7 0xfffe1020238a #define cfgBIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_8 0xfffe1020238c #define cfgBIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_9 0xfffe1020238e #define cfgBIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_10 0xfffe10202390 #define cfgBIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_11 0xfffe10202392 #define cfgBIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_12 0xfffe10202394 #define cfgBIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_13 0xfffe10202396 #define cfgBIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_14 0xfffe10202398 #define cfgBIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_15 0xfffe1020239a #define cfgBIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_16 0xfffe1020239c #define cfgBIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_17 0xfffe1020239e #define cfgBIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_18 0xfffe102023a0 #define cfgBIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_19 0xfffe102023a2 #define cfgBIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_20 0xfffe102023a4 #define cfgBIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_21 0xfffe102023a6 #define cfgBIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_22 0xfffe102023a8 #define cfgBIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_23 0xfffe102023aa #define cfgBIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_24 0xfffe102023ac #define cfgBIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_25 0xfffe102023ae #define cfgBIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_26 0xfffe102023b0 #define cfgBIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_27 0xfffe102023b2 #define cfgBIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_28 0xfffe102023b4 #define cfgBIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_29 0xfffe102023b6 #define cfgBIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_30 0xfffe102023b8 #define cfgBIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_31 0xfffe102023ba #define cfgBIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_32 0xfffe102023bc #define cfgBIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_33 0xfffe102023be #define cfgBIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_34 0xfffe102023c0 #define cfgBIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_35 0xfffe102023c2 #define cfgBIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_36 0xfffe102023c4 #define cfgBIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_37 0xfffe102023c6 #define cfgBIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_38 0xfffe102023c8 #define cfgBIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_39 0xfffe102023ca #define cfgBIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_40 0xfffe102023cc #define cfgBIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_41 0xfffe102023ce #define cfgBIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_42 0xfffe102023d0 #define cfgBIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_43 0xfffe102023d2 #define cfgBIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_44 0xfffe102023d4 #define cfgBIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_45 0xfffe102023d6 #define cfgBIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_46 0xfffe102023d8 #define cfgBIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_47 0xfffe102023da #define cfgBIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_48 0xfffe102023dc #define cfgBIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_49 0xfffe102023de #define cfgBIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_50 0xfffe102023e0 #define cfgBIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_51 0xfffe102023e2 #define cfgBIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_52 0xfffe102023e4 #define cfgBIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_53 0xfffe102023e6 #define cfgBIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_54 0xfffe102023e8 #define cfgBIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_55 0xfffe102023ea #define cfgBIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_56 0xfffe102023ec #define cfgBIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_57 0xfffe102023ee #define cfgBIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_58 0xfffe102023f0 #define cfgBIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_59 0xfffe102023f2 #define cfgBIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_60 0xfffe102023f4 #define cfgBIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_61 0xfffe102023f6 #define cfgBIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_62 0xfffe102023f8 #define cfgBIF_CFG_DEV0_EPF2_1_PCIE_TPH_ST_TABLE_63 0xfffe102023fa // addressBlock: nbio_nbif0_bif_cfg_dev0_epf3_bifcfgdecp // base address: 0xfffe10203000 #define cfgBIF_CFG_DEV0_EPF3_1_VENDOR_ID 0xfffe10203000 #define cfgBIF_CFG_DEV0_EPF3_1_DEVICE_ID 0xfffe10203002 #define cfgBIF_CFG_DEV0_EPF3_1_COMMAND 0xfffe10203004 #define cfgBIF_CFG_DEV0_EPF3_1_STATUS 0xfffe10203006 #define cfgBIF_CFG_DEV0_EPF3_1_REVISION_ID 0xfffe10203008 #define cfgBIF_CFG_DEV0_EPF3_1_PROG_INTERFACE 0xfffe10203009 #define cfgBIF_CFG_DEV0_EPF3_1_SUB_CLASS 0xfffe1020300a #define cfgBIF_CFG_DEV0_EPF3_1_BASE_CLASS 0xfffe1020300b #define cfgBIF_CFG_DEV0_EPF3_1_CACHE_LINE 0xfffe1020300c #define cfgBIF_CFG_DEV0_EPF3_1_LATENCY 0xfffe1020300d #define cfgBIF_CFG_DEV0_EPF3_1_HEADER 0xfffe1020300e #define cfgBIF_CFG_DEV0_EPF3_1_BIST 0xfffe1020300f #define cfgBIF_CFG_DEV0_EPF3_1_BASE_ADDR_1 0xfffe10203010 #define cfgBIF_CFG_DEV0_EPF3_1_BASE_ADDR_2 0xfffe10203014 #define cfgBIF_CFG_DEV0_EPF3_1_BASE_ADDR_3 0xfffe10203018 #define cfgBIF_CFG_DEV0_EPF3_1_BASE_ADDR_4 0xfffe1020301c #define cfgBIF_CFG_DEV0_EPF3_1_BASE_ADDR_5 0xfffe10203020 #define cfgBIF_CFG_DEV0_EPF3_1_BASE_ADDR_6 0xfffe10203024 #define cfgBIF_CFG_DEV0_EPF3_1_CARDBUS_CIS_PTR 0xfffe10203028 #define cfgBIF_CFG_DEV0_EPF3_1_ADAPTER_ID 0xfffe1020302c #define cfgBIF_CFG_DEV0_EPF3_1_ROM_BASE_ADDR 0xfffe10203030 #define cfgBIF_CFG_DEV0_EPF3_1_CAP_PTR 0xfffe10203034 #define cfgBIF_CFG_DEV0_EPF3_1_INTERRUPT_LINE 0xfffe1020303c #define cfgBIF_CFG_DEV0_EPF3_1_INTERRUPT_PIN 0xfffe1020303d #define cfgBIF_CFG_DEV0_EPF3_1_MIN_GRANT 0xfffe1020303e #define cfgBIF_CFG_DEV0_EPF3_1_MAX_LATENCY 0xfffe1020303f #define cfgBIF_CFG_DEV0_EPF3_1_VENDOR_CAP_LIST 0xfffe10203048 #define cfgBIF_CFG_DEV0_EPF3_1_ADAPTER_ID_W 0xfffe1020304c #define cfgBIF_CFG_DEV0_EPF3_1_PMI_CAP_LIST 0xfffe10203050 #define cfgBIF_CFG_DEV0_EPF3_1_PMI_CAP 0xfffe10203052 #define cfgBIF_CFG_DEV0_EPF3_1_PMI_STATUS_CNTL 0xfffe10203054 #define cfgBIF_CFG_DEV0_EPF3_1_SBRN 0xfffe10203060 #define cfgBIF_CFG_DEV0_EPF3_1_FLADJ 0xfffe10203061 #define cfgBIF_CFG_DEV0_EPF3_1_DBESL_DBESLD 0xfffe10203062 #define cfgBIF_CFG_DEV0_EPF3_1_PCIE_CAP_LIST 0xfffe10203064 #define cfgBIF_CFG_DEV0_EPF3_1_PCIE_CAP 0xfffe10203066 #define cfgBIF_CFG_DEV0_EPF3_1_DEVICE_CAP 0xfffe10203068 #define cfgBIF_CFG_DEV0_EPF3_1_DEVICE_CNTL 0xfffe1020306c #define cfgBIF_CFG_DEV0_EPF3_1_DEVICE_STATUS 0xfffe1020306e #define cfgBIF_CFG_DEV0_EPF3_1_LINK_CAP 0xfffe10203070 #define cfgBIF_CFG_DEV0_EPF3_1_LINK_CNTL 0xfffe10203074 #define cfgBIF_CFG_DEV0_EPF3_1_LINK_STATUS 0xfffe10203076 #define cfgBIF_CFG_DEV0_EPF3_1_DEVICE_CAP2 0xfffe10203088 #define cfgBIF_CFG_DEV0_EPF3_1_DEVICE_CNTL2 0xfffe1020308c #define cfgBIF_CFG_DEV0_EPF3_1_DEVICE_STATUS2 0xfffe1020308e #define cfgBIF_CFG_DEV0_EPF3_1_LINK_CAP2 0xfffe10203090 #define cfgBIF_CFG_DEV0_EPF3_1_LINK_CNTL2 0xfffe10203094 #define cfgBIF_CFG_DEV0_EPF3_1_LINK_STATUS2 0xfffe10203096 #define cfgBIF_CFG_DEV0_EPF3_1_MSI_CAP_LIST 0xfffe102030a0 #define cfgBIF_CFG_DEV0_EPF3_1_MSI_MSG_CNTL 0xfffe102030a2 #define cfgBIF_CFG_DEV0_EPF3_1_MSI_MSG_ADDR_LO 0xfffe102030a4 #define cfgBIF_CFG_DEV0_EPF3_1_MSI_MSG_ADDR_HI 0xfffe102030a8 #define cfgBIF_CFG_DEV0_EPF3_1_MSI_MSG_DATA 0xfffe102030a8 #define cfgBIF_CFG_DEV0_EPF3_1_MSI_MASK 0xfffe102030ac #define cfgBIF_CFG_DEV0_EPF3_1_MSI_MSG_DATA_64 0xfffe102030ac #define cfgBIF_CFG_DEV0_EPF3_1_MSI_MASK_64 0xfffe102030b0 #define cfgBIF_CFG_DEV0_EPF3_1_MSI_PENDING 0xfffe102030b0 #define cfgBIF_CFG_DEV0_EPF3_1_MSI_PENDING_64 0xfffe102030b4 #define cfgBIF_CFG_DEV0_EPF3_1_MSIX_CAP_LIST 0xfffe102030c0 #define cfgBIF_CFG_DEV0_EPF3_1_MSIX_MSG_CNTL 0xfffe102030c2 #define cfgBIF_CFG_DEV0_EPF3_1_MSIX_TABLE 0xfffe102030c4 #define cfgBIF_CFG_DEV0_EPF3_1_MSIX_PBA 0xfffe102030c8 #define cfgBIF_CFG_DEV0_EPF3_1_SATA_CAP_0 0xfffe102030d0 #define cfgBIF_CFG_DEV0_EPF3_1_SATA_CAP_1 0xfffe102030d4 #define cfgBIF_CFG_DEV0_EPF3_1_SATA_IDP_INDEX 0xfffe102030d8 #define cfgBIF_CFG_DEV0_EPF3_1_SATA_IDP_DATA 0xfffe102030dc #define cfgBIF_CFG_DEV0_EPF3_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0xfffe10203100 #define cfgBIF_CFG_DEV0_EPF3_1_PCIE_VENDOR_SPECIFIC_HDR 0xfffe10203104 #define cfgBIF_CFG_DEV0_EPF3_1_PCIE_VENDOR_SPECIFIC1 0xfffe10203108 #define cfgBIF_CFG_DEV0_EPF3_1_PCIE_VENDOR_SPECIFIC2 0xfffe1020310c #define cfgBIF_CFG_DEV0_EPF3_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0xfffe10203150 #define cfgBIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_STATUS 0xfffe10203154 #define cfgBIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_MASK 0xfffe10203158 #define cfgBIF_CFG_DEV0_EPF3_1_PCIE_UNCORR_ERR_SEVERITY 0xfffe1020315c #define cfgBIF_CFG_DEV0_EPF3_1_PCIE_CORR_ERR_STATUS 0xfffe10203160 #define cfgBIF_CFG_DEV0_EPF3_1_PCIE_CORR_ERR_MASK 0xfffe10203164 #define cfgBIF_CFG_DEV0_EPF3_1_PCIE_ADV_ERR_CAP_CNTL 0xfffe10203168 #define cfgBIF_CFG_DEV0_EPF3_1_PCIE_HDR_LOG0 0xfffe1020316c #define cfgBIF_CFG_DEV0_EPF3_1_PCIE_HDR_LOG1 0xfffe10203170 #define cfgBIF_CFG_DEV0_EPF3_1_PCIE_HDR_LOG2 0xfffe10203174 #define cfgBIF_CFG_DEV0_EPF3_1_PCIE_HDR_LOG3 0xfffe10203178 #define cfgBIF_CFG_DEV0_EPF3_1_PCIE_TLP_PREFIX_LOG0 0xfffe10203188 #define cfgBIF_CFG_DEV0_EPF3_1_PCIE_TLP_PREFIX_LOG1 0xfffe1020318c #define cfgBIF_CFG_DEV0_EPF3_1_PCIE_TLP_PREFIX_LOG2 0xfffe10203190 #define cfgBIF_CFG_DEV0_EPF3_1_PCIE_TLP_PREFIX_LOG3 0xfffe10203194 #define cfgBIF_CFG_DEV0_EPF3_1_PCIE_BAR_ENH_CAP_LIST 0xfffe10203200 #define cfgBIF_CFG_DEV0_EPF3_1_PCIE_BAR1_CAP 0xfffe10203204 #define cfgBIF_CFG_DEV0_EPF3_1_PCIE_BAR1_CNTL 0xfffe10203208 #define cfgBIF_CFG_DEV0_EPF3_1_PCIE_BAR2_CAP 0xfffe1020320c #define cfgBIF_CFG_DEV0_EPF3_1_PCIE_BAR2_CNTL 0xfffe10203210 #define cfgBIF_CFG_DEV0_EPF3_1_PCIE_BAR3_CAP 0xfffe10203214 #define cfgBIF_CFG_DEV0_EPF3_1_PCIE_BAR3_CNTL 0xfffe10203218 #define cfgBIF_CFG_DEV0_EPF3_1_PCIE_BAR4_CAP 0xfffe1020321c #define cfgBIF_CFG_DEV0_EPF3_1_PCIE_BAR4_CNTL 0xfffe10203220 #define cfgBIF_CFG_DEV0_EPF3_1_PCIE_BAR5_CAP 0xfffe10203224 #define cfgBIF_CFG_DEV0_EPF3_1_PCIE_BAR5_CNTL 0xfffe10203228 #define cfgBIF_CFG_DEV0_EPF3_1_PCIE_BAR6_CAP 0xfffe1020322c #define cfgBIF_CFG_DEV0_EPF3_1_PCIE_BAR6_CNTL 0xfffe10203230 #define cfgBIF_CFG_DEV0_EPF3_1_PCIE_PWR_BUDGET_ENH_CAP_LIST 0xfffe10203240 #define cfgBIF_CFG_DEV0_EPF3_1_PCIE_PWR_BUDGET_DATA_SELECT 0xfffe10203244 #define cfgBIF_CFG_DEV0_EPF3_1_PCIE_PWR_BUDGET_DATA 0xfffe10203248 #define cfgBIF_CFG_DEV0_EPF3_1_PCIE_PWR_BUDGET_CAP 0xfffe1020324c #define cfgBIF_CFG_DEV0_EPF3_1_PCIE_DPA_ENH_CAP_LIST 0xfffe10203250 #define cfgBIF_CFG_DEV0_EPF3_1_PCIE_DPA_CAP 0xfffe10203254 #define cfgBIF_CFG_DEV0_EPF3_1_PCIE_DPA_LATENCY_INDICATOR 0xfffe10203258 #define cfgBIF_CFG_DEV0_EPF3_1_PCIE_DPA_STATUS 0xfffe1020325c #define cfgBIF_CFG_DEV0_EPF3_1_PCIE_DPA_CNTL 0xfffe1020325e #define cfgBIF_CFG_DEV0_EPF3_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_0 0xfffe10203260 #define cfgBIF_CFG_DEV0_EPF3_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_1 0xfffe10203261 #define cfgBIF_CFG_DEV0_EPF3_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_2 0xfffe10203262 #define cfgBIF_CFG_DEV0_EPF3_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_3 0xfffe10203263 #define cfgBIF_CFG_DEV0_EPF3_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_4 0xfffe10203264 #define cfgBIF_CFG_DEV0_EPF3_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_5 0xfffe10203265 #define cfgBIF_CFG_DEV0_EPF3_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_6 0xfffe10203266 #define cfgBIF_CFG_DEV0_EPF3_1_PCIE_DPA_SUBSTATE_PWR_ALLOC_7 0xfffe10203267 #define cfgBIF_CFG_DEV0_EPF3_1_PCIE_ACS_ENH_CAP_LIST 0xfffe102032a0 #define cfgBIF_CFG_DEV0_EPF3_1_PCIE_ACS_CAP 0xfffe102032a4 #define cfgBIF_CFG_DEV0_EPF3_1_PCIE_ACS_CNTL 0xfffe102032a6 #define cfgBIF_CFG_DEV0_EPF3_1_PCIE_PASID_ENH_CAP_LIST 0xfffe102032d0 #define cfgBIF_CFG_DEV0_EPF3_1_PCIE_PASID_CAP 0xfffe102032d4 #define cfgBIF_CFG_DEV0_EPF3_1_PCIE_PASID_CNTL 0xfffe102032d6 #define cfgBIF_CFG_DEV0_EPF3_1_PCIE_ARI_ENH_CAP_LIST 0xfffe10203328 #define cfgBIF_CFG_DEV0_EPF3_1_PCIE_ARI_CAP 0xfffe1020332c #define cfgBIF_CFG_DEV0_EPF3_1_PCIE_ARI_CNTL 0xfffe1020332e #define cfgBIF_CFG_DEV0_EPF3_1_PCIE_TPH_REQR_ENH_CAP_LIST 0xfffe10203370 #define cfgBIF_CFG_DEV0_EPF3_1_PCIE_TPH_REQR_CAP 0xfffe10203374 #define cfgBIF_CFG_DEV0_EPF3_1_PCIE_TPH_REQR_CNTL 0xfffe10203378 #define cfgBIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_0 0xfffe1020337c #define cfgBIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_1 0xfffe1020337e #define cfgBIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_2 0xfffe10203380 #define cfgBIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_3 0xfffe10203382 #define cfgBIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_4 0xfffe10203384 #define cfgBIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_5 0xfffe10203386 #define cfgBIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_6 0xfffe10203388 #define cfgBIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_7 0xfffe1020338a #define cfgBIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_8 0xfffe1020338c #define cfgBIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_9 0xfffe1020338e #define cfgBIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_10 0xfffe10203390 #define cfgBIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_11 0xfffe10203392 #define cfgBIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_12 0xfffe10203394 #define cfgBIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_13 0xfffe10203396 #define cfgBIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_14 0xfffe10203398 #define cfgBIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_15 0xfffe1020339a #define cfgBIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_16 0xfffe1020339c #define cfgBIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_17 0xfffe1020339e #define cfgBIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_18 0xfffe102033a0 #define cfgBIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_19 0xfffe102033a2 #define cfgBIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_20 0xfffe102033a4 #define cfgBIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_21 0xfffe102033a6 #define cfgBIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_22 0xfffe102033a8 #define cfgBIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_23 0xfffe102033aa #define cfgBIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_24 0xfffe102033ac #define cfgBIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_25 0xfffe102033ae #define cfgBIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_26 0xfffe102033b0 #define cfgBIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_27 0xfffe102033b2 #define cfgBIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_28 0xfffe102033b4 #define cfgBIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_29 0xfffe102033b6 #define cfgBIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_30 0xfffe102033b8 #define cfgBIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_31 0xfffe102033ba #define cfgBIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_32 0xfffe102033bc #define cfgBIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_33 0xfffe102033be #define cfgBIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_34 0xfffe102033c0 #define cfgBIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_35 0xfffe102033c2 #define cfgBIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_36 0xfffe102033c4 #define cfgBIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_37 0xfffe102033c6 #define cfgBIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_38 0xfffe102033c8 #define cfgBIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_39 0xfffe102033ca #define cfgBIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_40 0xfffe102033cc #define cfgBIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_41 0xfffe102033ce #define cfgBIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_42 0xfffe102033d0 #define cfgBIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_43 0xfffe102033d2 #define cfgBIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_44 0xfffe102033d4 #define cfgBIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_45 0xfffe102033d6 #define cfgBIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_46 0xfffe102033d8 #define cfgBIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_47 0xfffe102033da #define cfgBIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_48 0xfffe102033dc #define cfgBIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_49 0xfffe102033de #define cfgBIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_50 0xfffe102033e0 #define cfgBIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_51 0xfffe102033e2 #define cfgBIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_52 0xfffe102033e4 #define cfgBIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_53 0xfffe102033e6 #define cfgBIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_54 0xfffe102033e8 #define cfgBIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_55 0xfffe102033ea #define cfgBIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_56 0xfffe102033ec #define cfgBIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_57 0xfffe102033ee #define cfgBIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_58 0xfffe102033f0 #define cfgBIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_59 0xfffe102033f2 #define cfgBIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_60 0xfffe102033f4 #define cfgBIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_61 0xfffe102033f6 #define cfgBIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_62 0xfffe102033f8 #define cfgBIF_CFG_DEV0_EPF3_1_PCIE_TPH_ST_TABLE_63 0xfffe102033fa // addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf0_bifcfgdecp // base address: 0xfffe10300000 #define cfgBIF_CFG_DEV0_EPF0_VF0_1_VENDOR_ID 0xfffe10300000 #define cfgBIF_CFG_DEV0_EPF0_VF0_1_DEVICE_ID 0xfffe10300002 #define cfgBIF_CFG_DEV0_EPF0_VF0_1_COMMAND 0xfffe10300004 #define cfgBIF_CFG_DEV0_EPF0_VF0_1_STATUS 0xfffe10300006 #define cfgBIF_CFG_DEV0_EPF0_VF0_1_REVISION_ID 0xfffe10300008 #define cfgBIF_CFG_DEV0_EPF0_VF0_1_PROG_INTERFACE 0xfffe10300009 #define cfgBIF_CFG_DEV0_EPF0_VF0_1_SUB_CLASS 0xfffe1030000a #define cfgBIF_CFG_DEV0_EPF0_VF0_1_BASE_CLASS 0xfffe1030000b #define cfgBIF_CFG_DEV0_EPF0_VF0_1_CACHE_LINE 0xfffe1030000c #define cfgBIF_CFG_DEV0_EPF0_VF0_1_LATENCY 0xfffe1030000d #define cfgBIF_CFG_DEV0_EPF0_VF0_1_HEADER 0xfffe1030000e #define cfgBIF_CFG_DEV0_EPF0_VF0_1_BIST 0xfffe1030000f #define cfgBIF_CFG_DEV0_EPF0_VF0_1_BASE_ADDR_1 0xfffe10300010 #define cfgBIF_CFG_DEV0_EPF0_VF0_1_BASE_ADDR_2 0xfffe10300014 #define cfgBIF_CFG_DEV0_EPF0_VF0_1_BASE_ADDR_3 0xfffe10300018 #define cfgBIF_CFG_DEV0_EPF0_VF0_1_BASE_ADDR_4 0xfffe1030001c #define cfgBIF_CFG_DEV0_EPF0_VF0_1_BASE_ADDR_5 0xfffe10300020 #define cfgBIF_CFG_DEV0_EPF0_VF0_1_BASE_ADDR_6 0xfffe10300024 #define cfgBIF_CFG_DEV0_EPF0_VF0_1_CARDBUS_CIS_PTR 0xfffe10300028 #define cfgBIF_CFG_DEV0_EPF0_VF0_1_ADAPTER_ID 0xfffe1030002c #define cfgBIF_CFG_DEV0_EPF0_VF0_1_ROM_BASE_ADDR 0xfffe10300030 #define cfgBIF_CFG_DEV0_EPF0_VF0_1_CAP_PTR 0xfffe10300034 #define cfgBIF_CFG_DEV0_EPF0_VF0_1_INTERRUPT_LINE 0xfffe1030003c #define cfgBIF_CFG_DEV0_EPF0_VF0_1_INTERRUPT_PIN 0xfffe1030003d #define cfgBIF_CFG_DEV0_EPF0_VF0_1_MIN_GRANT 0xfffe1030003e #define cfgBIF_CFG_DEV0_EPF0_VF0_1_MAX_LATENCY 0xfffe1030003f #define cfgBIF_CFG_DEV0_EPF0_VF0_1_PCIE_CAP_LIST 0xfffe10300064 #define cfgBIF_CFG_DEV0_EPF0_VF0_1_PCIE_CAP 0xfffe10300066 #define cfgBIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CAP 0xfffe10300068 #define cfgBIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CNTL 0xfffe1030006c #define cfgBIF_CFG_DEV0_EPF0_VF0_1_DEVICE_STATUS 0xfffe1030006e #define cfgBIF_CFG_DEV0_EPF0_VF0_1_LINK_CAP 0xfffe10300070 #define cfgBIF_CFG_DEV0_EPF0_VF0_1_LINK_CNTL 0xfffe10300074 #define cfgBIF_CFG_DEV0_EPF0_VF0_1_LINK_STATUS 0xfffe10300076 #define cfgBIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CAP2 0xfffe10300088 #define cfgBIF_CFG_DEV0_EPF0_VF0_1_DEVICE_CNTL2 0xfffe1030008c #define cfgBIF_CFG_DEV0_EPF0_VF0_1_DEVICE_STATUS2 0xfffe1030008e #define cfgBIF_CFG_DEV0_EPF0_VF0_1_LINK_CAP2 0xfffe10300090 #define cfgBIF_CFG_DEV0_EPF0_VF0_1_LINK_CNTL2 0xfffe10300094 #define cfgBIF_CFG_DEV0_EPF0_VF0_1_LINK_STATUS2 0xfffe10300096 #define cfgBIF_CFG_DEV0_EPF0_VF0_1_MSI_CAP_LIST 0xfffe103000a0 #define cfgBIF_CFG_DEV0_EPF0_VF0_1_MSI_MSG_CNTL 0xfffe103000a2 #define cfgBIF_CFG_DEV0_EPF0_VF0_1_MSI_MSG_ADDR_LO 0xfffe103000a4 #define cfgBIF_CFG_DEV0_EPF0_VF0_1_MSI_MSG_ADDR_HI 0xfffe103000a8 #define cfgBIF_CFG_DEV0_EPF0_VF0_1_MSI_MSG_DATA 0xfffe103000a8 #define cfgBIF_CFG_DEV0_EPF0_VF0_1_MSI_MASK 0xfffe103000ac #define cfgBIF_CFG_DEV0_EPF0_VF0_1_MSI_MSG_DATA_64 0xfffe103000ac #define cfgBIF_CFG_DEV0_EPF0_VF0_1_MSI_MASK_64 0xfffe103000b0 #define cfgBIF_CFG_DEV0_EPF0_VF0_1_MSI_PENDING 0xfffe103000b0 #define cfgBIF_CFG_DEV0_EPF0_VF0_1_MSI_PENDING_64 0xfffe103000b4 #define cfgBIF_CFG_DEV0_EPF0_VF0_1_MSIX_CAP_LIST 0xfffe103000c0 #define cfgBIF_CFG_DEV0_EPF0_VF0_1_MSIX_MSG_CNTL 0xfffe103000c2 #define cfgBIF_CFG_DEV0_EPF0_VF0_1_MSIX_TABLE 0xfffe103000c4 #define cfgBIF_CFG_DEV0_EPF0_VF0_1_MSIX_PBA 0xfffe103000c8 #define cfgBIF_CFG_DEV0_EPF0_VF0_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0xfffe10300100 #define cfgBIF_CFG_DEV0_EPF0_VF0_1_PCIE_VENDOR_SPECIFIC_HDR 0xfffe10300104 #define cfgBIF_CFG_DEV0_EPF0_VF0_1_PCIE_VENDOR_SPECIFIC1 0xfffe10300108 #define cfgBIF_CFG_DEV0_EPF0_VF0_1_PCIE_VENDOR_SPECIFIC2 0xfffe1030010c #define cfgBIF_CFG_DEV0_EPF0_VF0_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0xfffe10300150 #define cfgBIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_STATUS 0xfffe10300154 #define cfgBIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_MASK 0xfffe10300158 #define cfgBIF_CFG_DEV0_EPF0_VF0_1_PCIE_UNCORR_ERR_SEVERITY 0xfffe1030015c #define cfgBIF_CFG_DEV0_EPF0_VF0_1_PCIE_CORR_ERR_STATUS 0xfffe10300160 #define cfgBIF_CFG_DEV0_EPF0_VF0_1_PCIE_CORR_ERR_MASK 0xfffe10300164 #define cfgBIF_CFG_DEV0_EPF0_VF0_1_PCIE_ADV_ERR_CAP_CNTL 0xfffe10300168 #define cfgBIF_CFG_DEV0_EPF0_VF0_1_PCIE_HDR_LOG0 0xfffe1030016c #define cfgBIF_CFG_DEV0_EPF0_VF0_1_PCIE_HDR_LOG1 0xfffe10300170 #define cfgBIF_CFG_DEV0_EPF0_VF0_1_PCIE_HDR_LOG2 0xfffe10300174 #define cfgBIF_CFG_DEV0_EPF0_VF0_1_PCIE_HDR_LOG3 0xfffe10300178 #define cfgBIF_CFG_DEV0_EPF0_VF0_1_PCIE_TLP_PREFIX_LOG0 0xfffe10300188 #define cfgBIF_CFG_DEV0_EPF0_VF0_1_PCIE_TLP_PREFIX_LOG1 0xfffe1030018c #define cfgBIF_CFG_DEV0_EPF0_VF0_1_PCIE_TLP_PREFIX_LOG2 0xfffe10300190 #define cfgBIF_CFG_DEV0_EPF0_VF0_1_PCIE_TLP_PREFIX_LOG3 0xfffe10300194 #define cfgBIF_CFG_DEV0_EPF0_VF0_1_PCIE_ATS_ENH_CAP_LIST 0xfffe103002b0 #define cfgBIF_CFG_DEV0_EPF0_VF0_1_PCIE_ATS_CAP 0xfffe103002b4 #define cfgBIF_CFG_DEV0_EPF0_VF0_1_PCIE_ATS_CNTL 0xfffe103002b6 #define cfgBIF_CFG_DEV0_EPF0_VF0_1_PCIE_ARI_ENH_CAP_LIST 0xfffe10300328 #define cfgBIF_CFG_DEV0_EPF0_VF0_1_PCIE_ARI_CAP 0xfffe1030032c #define cfgBIF_CFG_DEV0_EPF0_VF0_1_PCIE_ARI_CNTL 0xfffe1030032e // addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf1_bifcfgdecp // base address: 0xfffe10301000 #define cfgBIF_CFG_DEV0_EPF0_VF1_1_VENDOR_ID 0xfffe10301000 #define cfgBIF_CFG_DEV0_EPF0_VF1_1_DEVICE_ID 0xfffe10301002 #define cfgBIF_CFG_DEV0_EPF0_VF1_1_COMMAND 0xfffe10301004 #define cfgBIF_CFG_DEV0_EPF0_VF1_1_STATUS 0xfffe10301006 #define cfgBIF_CFG_DEV0_EPF0_VF1_1_REVISION_ID 0xfffe10301008 #define cfgBIF_CFG_DEV0_EPF0_VF1_1_PROG_INTERFACE 0xfffe10301009 #define cfgBIF_CFG_DEV0_EPF0_VF1_1_SUB_CLASS 0xfffe1030100a #define cfgBIF_CFG_DEV0_EPF0_VF1_1_BASE_CLASS 0xfffe1030100b #define cfgBIF_CFG_DEV0_EPF0_VF1_1_CACHE_LINE 0xfffe1030100c #define cfgBIF_CFG_DEV0_EPF0_VF1_1_LATENCY 0xfffe1030100d #define cfgBIF_CFG_DEV0_EPF0_VF1_1_HEADER 0xfffe1030100e #define cfgBIF_CFG_DEV0_EPF0_VF1_1_BIST 0xfffe1030100f #define cfgBIF_CFG_DEV0_EPF0_VF1_1_BASE_ADDR_1 0xfffe10301010 #define cfgBIF_CFG_DEV0_EPF0_VF1_1_BASE_ADDR_2 0xfffe10301014 #define cfgBIF_CFG_DEV0_EPF0_VF1_1_BASE_ADDR_3 0xfffe10301018 #define cfgBIF_CFG_DEV0_EPF0_VF1_1_BASE_ADDR_4 0xfffe1030101c #define cfgBIF_CFG_DEV0_EPF0_VF1_1_BASE_ADDR_5 0xfffe10301020 #define cfgBIF_CFG_DEV0_EPF0_VF1_1_BASE_ADDR_6 0xfffe10301024 #define cfgBIF_CFG_DEV0_EPF0_VF1_1_CARDBUS_CIS_PTR 0xfffe10301028 #define cfgBIF_CFG_DEV0_EPF0_VF1_1_ADAPTER_ID 0xfffe1030102c #define cfgBIF_CFG_DEV0_EPF0_VF1_1_ROM_BASE_ADDR 0xfffe10301030 #define cfgBIF_CFG_DEV0_EPF0_VF1_1_CAP_PTR 0xfffe10301034 #define cfgBIF_CFG_DEV0_EPF0_VF1_1_INTERRUPT_LINE 0xfffe1030103c #define cfgBIF_CFG_DEV0_EPF0_VF1_1_INTERRUPT_PIN 0xfffe1030103d #define cfgBIF_CFG_DEV0_EPF0_VF1_1_MIN_GRANT 0xfffe1030103e #define cfgBIF_CFG_DEV0_EPF0_VF1_1_MAX_LATENCY 0xfffe1030103f #define cfgBIF_CFG_DEV0_EPF0_VF1_1_PCIE_CAP_LIST 0xfffe10301064 #define cfgBIF_CFG_DEV0_EPF0_VF1_1_PCIE_CAP 0xfffe10301066 #define cfgBIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CAP 0xfffe10301068 #define cfgBIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CNTL 0xfffe1030106c #define cfgBIF_CFG_DEV0_EPF0_VF1_1_DEVICE_STATUS 0xfffe1030106e #define cfgBIF_CFG_DEV0_EPF0_VF1_1_LINK_CAP 0xfffe10301070 #define cfgBIF_CFG_DEV0_EPF0_VF1_1_LINK_CNTL 0xfffe10301074 #define cfgBIF_CFG_DEV0_EPF0_VF1_1_LINK_STATUS 0xfffe10301076 #define cfgBIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CAP2 0xfffe10301088 #define cfgBIF_CFG_DEV0_EPF0_VF1_1_DEVICE_CNTL2 0xfffe1030108c #define cfgBIF_CFG_DEV0_EPF0_VF1_1_DEVICE_STATUS2 0xfffe1030108e #define cfgBIF_CFG_DEV0_EPF0_VF1_1_LINK_CAP2 0xfffe10301090 #define cfgBIF_CFG_DEV0_EPF0_VF1_1_LINK_CNTL2 0xfffe10301094 #define cfgBIF_CFG_DEV0_EPF0_VF1_1_LINK_STATUS2 0xfffe10301096 #define cfgBIF_CFG_DEV0_EPF0_VF1_1_MSI_CAP_LIST 0xfffe103010a0 #define cfgBIF_CFG_DEV0_EPF0_VF1_1_MSI_MSG_CNTL 0xfffe103010a2 #define cfgBIF_CFG_DEV0_EPF0_VF1_1_MSI_MSG_ADDR_LO 0xfffe103010a4 #define cfgBIF_CFG_DEV0_EPF0_VF1_1_MSI_MSG_ADDR_HI 0xfffe103010a8 #define cfgBIF_CFG_DEV0_EPF0_VF1_1_MSI_MSG_DATA 0xfffe103010a8 #define cfgBIF_CFG_DEV0_EPF0_VF1_1_MSI_MASK 0xfffe103010ac #define cfgBIF_CFG_DEV0_EPF0_VF1_1_MSI_MSG_DATA_64 0xfffe103010ac #define cfgBIF_CFG_DEV0_EPF0_VF1_1_MSI_MASK_64 0xfffe103010b0 #define cfgBIF_CFG_DEV0_EPF0_VF1_1_MSI_PENDING 0xfffe103010b0 #define cfgBIF_CFG_DEV0_EPF0_VF1_1_MSI_PENDING_64 0xfffe103010b4 #define cfgBIF_CFG_DEV0_EPF0_VF1_1_MSIX_CAP_LIST 0xfffe103010c0 #define cfgBIF_CFG_DEV0_EPF0_VF1_1_MSIX_MSG_CNTL 0xfffe103010c2 #define cfgBIF_CFG_DEV0_EPF0_VF1_1_MSIX_TABLE 0xfffe103010c4 #define cfgBIF_CFG_DEV0_EPF0_VF1_1_MSIX_PBA 0xfffe103010c8 #define cfgBIF_CFG_DEV0_EPF0_VF1_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0xfffe10301100 #define cfgBIF_CFG_DEV0_EPF0_VF1_1_PCIE_VENDOR_SPECIFIC_HDR 0xfffe10301104 #define cfgBIF_CFG_DEV0_EPF0_VF1_1_PCIE_VENDOR_SPECIFIC1 0xfffe10301108 #define cfgBIF_CFG_DEV0_EPF0_VF1_1_PCIE_VENDOR_SPECIFIC2 0xfffe1030110c #define cfgBIF_CFG_DEV0_EPF0_VF1_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0xfffe10301150 #define cfgBIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_STATUS 0xfffe10301154 #define cfgBIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_MASK 0xfffe10301158 #define cfgBIF_CFG_DEV0_EPF0_VF1_1_PCIE_UNCORR_ERR_SEVERITY 0xfffe1030115c #define cfgBIF_CFG_DEV0_EPF0_VF1_1_PCIE_CORR_ERR_STATUS 0xfffe10301160 #define cfgBIF_CFG_DEV0_EPF0_VF1_1_PCIE_CORR_ERR_MASK 0xfffe10301164 #define cfgBIF_CFG_DEV0_EPF0_VF1_1_PCIE_ADV_ERR_CAP_CNTL 0xfffe10301168 #define cfgBIF_CFG_DEV0_EPF0_VF1_1_PCIE_HDR_LOG0 0xfffe1030116c #define cfgBIF_CFG_DEV0_EPF0_VF1_1_PCIE_HDR_LOG1 0xfffe10301170 #define cfgBIF_CFG_DEV0_EPF0_VF1_1_PCIE_HDR_LOG2 0xfffe10301174 #define cfgBIF_CFG_DEV0_EPF0_VF1_1_PCIE_HDR_LOG3 0xfffe10301178 #define cfgBIF_CFG_DEV0_EPF0_VF1_1_PCIE_TLP_PREFIX_LOG0 0xfffe10301188 #define cfgBIF_CFG_DEV0_EPF0_VF1_1_PCIE_TLP_PREFIX_LOG1 0xfffe1030118c #define cfgBIF_CFG_DEV0_EPF0_VF1_1_PCIE_TLP_PREFIX_LOG2 0xfffe10301190 #define cfgBIF_CFG_DEV0_EPF0_VF1_1_PCIE_TLP_PREFIX_LOG3 0xfffe10301194 #define cfgBIF_CFG_DEV0_EPF0_VF1_1_PCIE_ATS_ENH_CAP_LIST 0xfffe103012b0 #define cfgBIF_CFG_DEV0_EPF0_VF1_1_PCIE_ATS_CAP 0xfffe103012b4 #define cfgBIF_CFG_DEV0_EPF0_VF1_1_PCIE_ATS_CNTL 0xfffe103012b6 #define cfgBIF_CFG_DEV0_EPF0_VF1_1_PCIE_ARI_ENH_CAP_LIST 0xfffe10301328 #define cfgBIF_CFG_DEV0_EPF0_VF1_1_PCIE_ARI_CAP 0xfffe1030132c #define cfgBIF_CFG_DEV0_EPF0_VF1_1_PCIE_ARI_CNTL 0xfffe1030132e // addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf2_bifcfgdecp // base address: 0xfffe10302000 #define cfgBIF_CFG_DEV0_EPF0_VF2_1_VENDOR_ID 0xfffe10302000 #define cfgBIF_CFG_DEV0_EPF0_VF2_1_DEVICE_ID 0xfffe10302002 #define cfgBIF_CFG_DEV0_EPF0_VF2_1_COMMAND 0xfffe10302004 #define cfgBIF_CFG_DEV0_EPF0_VF2_1_STATUS 0xfffe10302006 #define cfgBIF_CFG_DEV0_EPF0_VF2_1_REVISION_ID 0xfffe10302008 #define cfgBIF_CFG_DEV0_EPF0_VF2_1_PROG_INTERFACE 0xfffe10302009 #define cfgBIF_CFG_DEV0_EPF0_VF2_1_SUB_CLASS 0xfffe1030200a #define cfgBIF_CFG_DEV0_EPF0_VF2_1_BASE_CLASS 0xfffe1030200b #define cfgBIF_CFG_DEV0_EPF0_VF2_1_CACHE_LINE 0xfffe1030200c #define cfgBIF_CFG_DEV0_EPF0_VF2_1_LATENCY 0xfffe1030200d #define cfgBIF_CFG_DEV0_EPF0_VF2_1_HEADER 0xfffe1030200e #define cfgBIF_CFG_DEV0_EPF0_VF2_1_BIST 0xfffe1030200f #define cfgBIF_CFG_DEV0_EPF0_VF2_1_BASE_ADDR_1 0xfffe10302010 #define cfgBIF_CFG_DEV0_EPF0_VF2_1_BASE_ADDR_2 0xfffe10302014 #define cfgBIF_CFG_DEV0_EPF0_VF2_1_BASE_ADDR_3 0xfffe10302018 #define cfgBIF_CFG_DEV0_EPF0_VF2_1_BASE_ADDR_4 0xfffe1030201c #define cfgBIF_CFG_DEV0_EPF0_VF2_1_BASE_ADDR_5 0xfffe10302020 #define cfgBIF_CFG_DEV0_EPF0_VF2_1_BASE_ADDR_6 0xfffe10302024 #define cfgBIF_CFG_DEV0_EPF0_VF2_1_CARDBUS_CIS_PTR 0xfffe10302028 #define cfgBIF_CFG_DEV0_EPF0_VF2_1_ADAPTER_ID 0xfffe1030202c #define cfgBIF_CFG_DEV0_EPF0_VF2_1_ROM_BASE_ADDR 0xfffe10302030 #define cfgBIF_CFG_DEV0_EPF0_VF2_1_CAP_PTR 0xfffe10302034 #define cfgBIF_CFG_DEV0_EPF0_VF2_1_INTERRUPT_LINE 0xfffe1030203c #define cfgBIF_CFG_DEV0_EPF0_VF2_1_INTERRUPT_PIN 0xfffe1030203d #define cfgBIF_CFG_DEV0_EPF0_VF2_1_MIN_GRANT 0xfffe1030203e #define cfgBIF_CFG_DEV0_EPF0_VF2_1_MAX_LATENCY 0xfffe1030203f #define cfgBIF_CFG_DEV0_EPF0_VF2_1_PCIE_CAP_LIST 0xfffe10302064 #define cfgBIF_CFG_DEV0_EPF0_VF2_1_PCIE_CAP 0xfffe10302066 #define cfgBIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CAP 0xfffe10302068 #define cfgBIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CNTL 0xfffe1030206c #define cfgBIF_CFG_DEV0_EPF0_VF2_1_DEVICE_STATUS 0xfffe1030206e #define cfgBIF_CFG_DEV0_EPF0_VF2_1_LINK_CAP 0xfffe10302070 #define cfgBIF_CFG_DEV0_EPF0_VF2_1_LINK_CNTL 0xfffe10302074 #define cfgBIF_CFG_DEV0_EPF0_VF2_1_LINK_STATUS 0xfffe10302076 #define cfgBIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CAP2 0xfffe10302088 #define cfgBIF_CFG_DEV0_EPF0_VF2_1_DEVICE_CNTL2 0xfffe1030208c #define cfgBIF_CFG_DEV0_EPF0_VF2_1_DEVICE_STATUS2 0xfffe1030208e #define cfgBIF_CFG_DEV0_EPF0_VF2_1_LINK_CAP2 0xfffe10302090 #define cfgBIF_CFG_DEV0_EPF0_VF2_1_LINK_CNTL2 0xfffe10302094 #define cfgBIF_CFG_DEV0_EPF0_VF2_1_LINK_STATUS2 0xfffe10302096 #define cfgBIF_CFG_DEV0_EPF0_VF2_1_MSI_CAP_LIST 0xfffe103020a0 #define cfgBIF_CFG_DEV0_EPF0_VF2_1_MSI_MSG_CNTL 0xfffe103020a2 #define cfgBIF_CFG_DEV0_EPF0_VF2_1_MSI_MSG_ADDR_LO 0xfffe103020a4 #define cfgBIF_CFG_DEV0_EPF0_VF2_1_MSI_MSG_ADDR_HI 0xfffe103020a8 #define cfgBIF_CFG_DEV0_EPF0_VF2_1_MSI_MSG_DATA 0xfffe103020a8 #define cfgBIF_CFG_DEV0_EPF0_VF2_1_MSI_MASK 0xfffe103020ac #define cfgBIF_CFG_DEV0_EPF0_VF2_1_MSI_MSG_DATA_64 0xfffe103020ac #define cfgBIF_CFG_DEV0_EPF0_VF2_1_MSI_MASK_64 0xfffe103020b0 #define cfgBIF_CFG_DEV0_EPF0_VF2_1_MSI_PENDING 0xfffe103020b0 #define cfgBIF_CFG_DEV0_EPF0_VF2_1_MSI_PENDING_64 0xfffe103020b4 #define cfgBIF_CFG_DEV0_EPF0_VF2_1_MSIX_CAP_LIST 0xfffe103020c0 #define cfgBIF_CFG_DEV0_EPF0_VF2_1_MSIX_MSG_CNTL 0xfffe103020c2 #define cfgBIF_CFG_DEV0_EPF0_VF2_1_MSIX_TABLE 0xfffe103020c4 #define cfgBIF_CFG_DEV0_EPF0_VF2_1_MSIX_PBA 0xfffe103020c8 #define cfgBIF_CFG_DEV0_EPF0_VF2_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0xfffe10302100 #define cfgBIF_CFG_DEV0_EPF0_VF2_1_PCIE_VENDOR_SPECIFIC_HDR 0xfffe10302104 #define cfgBIF_CFG_DEV0_EPF0_VF2_1_PCIE_VENDOR_SPECIFIC1 0xfffe10302108 #define cfgBIF_CFG_DEV0_EPF0_VF2_1_PCIE_VENDOR_SPECIFIC2 0xfffe1030210c #define cfgBIF_CFG_DEV0_EPF0_VF2_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0xfffe10302150 #define cfgBIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_STATUS 0xfffe10302154 #define cfgBIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_MASK 0xfffe10302158 #define cfgBIF_CFG_DEV0_EPF0_VF2_1_PCIE_UNCORR_ERR_SEVERITY 0xfffe1030215c #define cfgBIF_CFG_DEV0_EPF0_VF2_1_PCIE_CORR_ERR_STATUS 0xfffe10302160 #define cfgBIF_CFG_DEV0_EPF0_VF2_1_PCIE_CORR_ERR_MASK 0xfffe10302164 #define cfgBIF_CFG_DEV0_EPF0_VF2_1_PCIE_ADV_ERR_CAP_CNTL 0xfffe10302168 #define cfgBIF_CFG_DEV0_EPF0_VF2_1_PCIE_HDR_LOG0 0xfffe1030216c #define cfgBIF_CFG_DEV0_EPF0_VF2_1_PCIE_HDR_LOG1 0xfffe10302170 #define cfgBIF_CFG_DEV0_EPF0_VF2_1_PCIE_HDR_LOG2 0xfffe10302174 #define cfgBIF_CFG_DEV0_EPF0_VF2_1_PCIE_HDR_LOG3 0xfffe10302178 #define cfgBIF_CFG_DEV0_EPF0_VF2_1_PCIE_TLP_PREFIX_LOG0 0xfffe10302188 #define cfgBIF_CFG_DEV0_EPF0_VF2_1_PCIE_TLP_PREFIX_LOG1 0xfffe1030218c #define cfgBIF_CFG_DEV0_EPF0_VF2_1_PCIE_TLP_PREFIX_LOG2 0xfffe10302190 #define cfgBIF_CFG_DEV0_EPF0_VF2_1_PCIE_TLP_PREFIX_LOG3 0xfffe10302194 #define cfgBIF_CFG_DEV0_EPF0_VF2_1_PCIE_ATS_ENH_CAP_LIST 0xfffe103022b0 #define cfgBIF_CFG_DEV0_EPF0_VF2_1_PCIE_ATS_CAP 0xfffe103022b4 #define cfgBIF_CFG_DEV0_EPF0_VF2_1_PCIE_ATS_CNTL 0xfffe103022b6 #define cfgBIF_CFG_DEV0_EPF0_VF2_1_PCIE_ARI_ENH_CAP_LIST 0xfffe10302328 #define cfgBIF_CFG_DEV0_EPF0_VF2_1_PCIE_ARI_CAP 0xfffe1030232c #define cfgBIF_CFG_DEV0_EPF0_VF2_1_PCIE_ARI_CNTL 0xfffe1030232e // addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf3_bifcfgdecp // base address: 0xfffe10303000 #define cfgBIF_CFG_DEV0_EPF0_VF3_1_VENDOR_ID 0xfffe10303000 #define cfgBIF_CFG_DEV0_EPF0_VF3_1_DEVICE_ID 0xfffe10303002 #define cfgBIF_CFG_DEV0_EPF0_VF3_1_COMMAND 0xfffe10303004 #define cfgBIF_CFG_DEV0_EPF0_VF3_1_STATUS 0xfffe10303006 #define cfgBIF_CFG_DEV0_EPF0_VF3_1_REVISION_ID 0xfffe10303008 #define cfgBIF_CFG_DEV0_EPF0_VF3_1_PROG_INTERFACE 0xfffe10303009 #define cfgBIF_CFG_DEV0_EPF0_VF3_1_SUB_CLASS 0xfffe1030300a #define cfgBIF_CFG_DEV0_EPF0_VF3_1_BASE_CLASS 0xfffe1030300b #define cfgBIF_CFG_DEV0_EPF0_VF3_1_CACHE_LINE 0xfffe1030300c #define cfgBIF_CFG_DEV0_EPF0_VF3_1_LATENCY 0xfffe1030300d #define cfgBIF_CFG_DEV0_EPF0_VF3_1_HEADER 0xfffe1030300e #define cfgBIF_CFG_DEV0_EPF0_VF3_1_BIST 0xfffe1030300f #define cfgBIF_CFG_DEV0_EPF0_VF3_1_BASE_ADDR_1 0xfffe10303010 #define cfgBIF_CFG_DEV0_EPF0_VF3_1_BASE_ADDR_2 0xfffe10303014 #define cfgBIF_CFG_DEV0_EPF0_VF3_1_BASE_ADDR_3 0xfffe10303018 #define cfgBIF_CFG_DEV0_EPF0_VF3_1_BASE_ADDR_4 0xfffe1030301c #define cfgBIF_CFG_DEV0_EPF0_VF3_1_BASE_ADDR_5 0xfffe10303020 #define cfgBIF_CFG_DEV0_EPF0_VF3_1_BASE_ADDR_6 0xfffe10303024 #define cfgBIF_CFG_DEV0_EPF0_VF3_1_CARDBUS_CIS_PTR 0xfffe10303028 #define cfgBIF_CFG_DEV0_EPF0_VF3_1_ADAPTER_ID 0xfffe1030302c #define cfgBIF_CFG_DEV0_EPF0_VF3_1_ROM_BASE_ADDR 0xfffe10303030 #define cfgBIF_CFG_DEV0_EPF0_VF3_1_CAP_PTR 0xfffe10303034 #define cfgBIF_CFG_DEV0_EPF0_VF3_1_INTERRUPT_LINE 0xfffe1030303c #define cfgBIF_CFG_DEV0_EPF0_VF3_1_INTERRUPT_PIN 0xfffe1030303d #define cfgBIF_CFG_DEV0_EPF0_VF3_1_MIN_GRANT 0xfffe1030303e #define cfgBIF_CFG_DEV0_EPF0_VF3_1_MAX_LATENCY 0xfffe1030303f #define cfgBIF_CFG_DEV0_EPF0_VF3_1_PCIE_CAP_LIST 0xfffe10303064 #define cfgBIF_CFG_DEV0_EPF0_VF3_1_PCIE_CAP 0xfffe10303066 #define cfgBIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CAP 0xfffe10303068 #define cfgBIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CNTL 0xfffe1030306c #define cfgBIF_CFG_DEV0_EPF0_VF3_1_DEVICE_STATUS 0xfffe1030306e #define cfgBIF_CFG_DEV0_EPF0_VF3_1_LINK_CAP 0xfffe10303070 #define cfgBIF_CFG_DEV0_EPF0_VF3_1_LINK_CNTL 0xfffe10303074 #define cfgBIF_CFG_DEV0_EPF0_VF3_1_LINK_STATUS 0xfffe10303076 #define cfgBIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CAP2 0xfffe10303088 #define cfgBIF_CFG_DEV0_EPF0_VF3_1_DEVICE_CNTL2 0xfffe1030308c #define cfgBIF_CFG_DEV0_EPF0_VF3_1_DEVICE_STATUS2 0xfffe1030308e #define cfgBIF_CFG_DEV0_EPF0_VF3_1_LINK_CAP2 0xfffe10303090 #define cfgBIF_CFG_DEV0_EPF0_VF3_1_LINK_CNTL2 0xfffe10303094 #define cfgBIF_CFG_DEV0_EPF0_VF3_1_LINK_STATUS2 0xfffe10303096 #define cfgBIF_CFG_DEV0_EPF0_VF3_1_MSI_CAP_LIST 0xfffe103030a0 #define cfgBIF_CFG_DEV0_EPF0_VF3_1_MSI_MSG_CNTL 0xfffe103030a2 #define cfgBIF_CFG_DEV0_EPF0_VF3_1_MSI_MSG_ADDR_LO 0xfffe103030a4 #define cfgBIF_CFG_DEV0_EPF0_VF3_1_MSI_MSG_ADDR_HI 0xfffe103030a8 #define cfgBIF_CFG_DEV0_EPF0_VF3_1_MSI_MSG_DATA 0xfffe103030a8 #define cfgBIF_CFG_DEV0_EPF0_VF3_1_MSI_MASK 0xfffe103030ac #define cfgBIF_CFG_DEV0_EPF0_VF3_1_MSI_MSG_DATA_64 0xfffe103030ac #define cfgBIF_CFG_DEV0_EPF0_VF3_1_MSI_MASK_64 0xfffe103030b0 #define cfgBIF_CFG_DEV0_EPF0_VF3_1_MSI_PENDING 0xfffe103030b0 #define cfgBIF_CFG_DEV0_EPF0_VF3_1_MSI_PENDING_64 0xfffe103030b4 #define cfgBIF_CFG_DEV0_EPF0_VF3_1_MSIX_CAP_LIST 0xfffe103030c0 #define cfgBIF_CFG_DEV0_EPF0_VF3_1_MSIX_MSG_CNTL 0xfffe103030c2 #define cfgBIF_CFG_DEV0_EPF0_VF3_1_MSIX_TABLE 0xfffe103030c4 #define cfgBIF_CFG_DEV0_EPF0_VF3_1_MSIX_PBA 0xfffe103030c8 #define cfgBIF_CFG_DEV0_EPF0_VF3_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0xfffe10303100 #define cfgBIF_CFG_DEV0_EPF0_VF3_1_PCIE_VENDOR_SPECIFIC_HDR 0xfffe10303104 #define cfgBIF_CFG_DEV0_EPF0_VF3_1_PCIE_VENDOR_SPECIFIC1 0xfffe10303108 #define cfgBIF_CFG_DEV0_EPF0_VF3_1_PCIE_VENDOR_SPECIFIC2 0xfffe1030310c #define cfgBIF_CFG_DEV0_EPF0_VF3_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0xfffe10303150 #define cfgBIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_STATUS 0xfffe10303154 #define cfgBIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_MASK 0xfffe10303158 #define cfgBIF_CFG_DEV0_EPF0_VF3_1_PCIE_UNCORR_ERR_SEVERITY 0xfffe1030315c #define cfgBIF_CFG_DEV0_EPF0_VF3_1_PCIE_CORR_ERR_STATUS 0xfffe10303160 #define cfgBIF_CFG_DEV0_EPF0_VF3_1_PCIE_CORR_ERR_MASK 0xfffe10303164 #define cfgBIF_CFG_DEV0_EPF0_VF3_1_PCIE_ADV_ERR_CAP_CNTL 0xfffe10303168 #define cfgBIF_CFG_DEV0_EPF0_VF3_1_PCIE_HDR_LOG0 0xfffe1030316c #define cfgBIF_CFG_DEV0_EPF0_VF3_1_PCIE_HDR_LOG1 0xfffe10303170 #define cfgBIF_CFG_DEV0_EPF0_VF3_1_PCIE_HDR_LOG2 0xfffe10303174 #define cfgBIF_CFG_DEV0_EPF0_VF3_1_PCIE_HDR_LOG3 0xfffe10303178 #define cfgBIF_CFG_DEV0_EPF0_VF3_1_PCIE_TLP_PREFIX_LOG0 0xfffe10303188 #define cfgBIF_CFG_DEV0_EPF0_VF3_1_PCIE_TLP_PREFIX_LOG1 0xfffe1030318c #define cfgBIF_CFG_DEV0_EPF0_VF3_1_PCIE_TLP_PREFIX_LOG2 0xfffe10303190 #define cfgBIF_CFG_DEV0_EPF0_VF3_1_PCIE_TLP_PREFIX_LOG3 0xfffe10303194 #define cfgBIF_CFG_DEV0_EPF0_VF3_1_PCIE_ATS_ENH_CAP_LIST 0xfffe103032b0 #define cfgBIF_CFG_DEV0_EPF0_VF3_1_PCIE_ATS_CAP 0xfffe103032b4 #define cfgBIF_CFG_DEV0_EPF0_VF3_1_PCIE_ATS_CNTL 0xfffe103032b6 #define cfgBIF_CFG_DEV0_EPF0_VF3_1_PCIE_ARI_ENH_CAP_LIST 0xfffe10303328 #define cfgBIF_CFG_DEV0_EPF0_VF3_1_PCIE_ARI_CAP 0xfffe1030332c #define cfgBIF_CFG_DEV0_EPF0_VF3_1_PCIE_ARI_CNTL 0xfffe1030332e // addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf4_bifcfgdecp // base address: 0xfffe10304000 #define cfgBIF_CFG_DEV0_EPF0_VF4_1_VENDOR_ID 0xfffe10304000 #define cfgBIF_CFG_DEV0_EPF0_VF4_1_DEVICE_ID 0xfffe10304002 #define cfgBIF_CFG_DEV0_EPF0_VF4_1_COMMAND 0xfffe10304004 #define cfgBIF_CFG_DEV0_EPF0_VF4_1_STATUS 0xfffe10304006 #define cfgBIF_CFG_DEV0_EPF0_VF4_1_REVISION_ID 0xfffe10304008 #define cfgBIF_CFG_DEV0_EPF0_VF4_1_PROG_INTERFACE 0xfffe10304009 #define cfgBIF_CFG_DEV0_EPF0_VF4_1_SUB_CLASS 0xfffe1030400a #define cfgBIF_CFG_DEV0_EPF0_VF4_1_BASE_CLASS 0xfffe1030400b #define cfgBIF_CFG_DEV0_EPF0_VF4_1_CACHE_LINE 0xfffe1030400c #define cfgBIF_CFG_DEV0_EPF0_VF4_1_LATENCY 0xfffe1030400d #define cfgBIF_CFG_DEV0_EPF0_VF4_1_HEADER 0xfffe1030400e #define cfgBIF_CFG_DEV0_EPF0_VF4_1_BIST 0xfffe1030400f #define cfgBIF_CFG_DEV0_EPF0_VF4_1_BASE_ADDR_1 0xfffe10304010 #define cfgBIF_CFG_DEV0_EPF0_VF4_1_BASE_ADDR_2 0xfffe10304014 #define cfgBIF_CFG_DEV0_EPF0_VF4_1_BASE_ADDR_3 0xfffe10304018 #define cfgBIF_CFG_DEV0_EPF0_VF4_1_BASE_ADDR_4 0xfffe1030401c #define cfgBIF_CFG_DEV0_EPF0_VF4_1_BASE_ADDR_5 0xfffe10304020 #define cfgBIF_CFG_DEV0_EPF0_VF4_1_BASE_ADDR_6 0xfffe10304024 #define cfgBIF_CFG_DEV0_EPF0_VF4_1_CARDBUS_CIS_PTR 0xfffe10304028 #define cfgBIF_CFG_DEV0_EPF0_VF4_1_ADAPTER_ID 0xfffe1030402c #define cfgBIF_CFG_DEV0_EPF0_VF4_1_ROM_BASE_ADDR 0xfffe10304030 #define cfgBIF_CFG_DEV0_EPF0_VF4_1_CAP_PTR 0xfffe10304034 #define cfgBIF_CFG_DEV0_EPF0_VF4_1_INTERRUPT_LINE 0xfffe1030403c #define cfgBIF_CFG_DEV0_EPF0_VF4_1_INTERRUPT_PIN 0xfffe1030403d #define cfgBIF_CFG_DEV0_EPF0_VF4_1_MIN_GRANT 0xfffe1030403e #define cfgBIF_CFG_DEV0_EPF0_VF4_1_MAX_LATENCY 0xfffe1030403f #define cfgBIF_CFG_DEV0_EPF0_VF4_1_PCIE_CAP_LIST 0xfffe10304064 #define cfgBIF_CFG_DEV0_EPF0_VF4_1_PCIE_CAP 0xfffe10304066 #define cfgBIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CAP 0xfffe10304068 #define cfgBIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CNTL 0xfffe1030406c #define cfgBIF_CFG_DEV0_EPF0_VF4_1_DEVICE_STATUS 0xfffe1030406e #define cfgBIF_CFG_DEV0_EPF0_VF4_1_LINK_CAP 0xfffe10304070 #define cfgBIF_CFG_DEV0_EPF0_VF4_1_LINK_CNTL 0xfffe10304074 #define cfgBIF_CFG_DEV0_EPF0_VF4_1_LINK_STATUS 0xfffe10304076 #define cfgBIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CAP2 0xfffe10304088 #define cfgBIF_CFG_DEV0_EPF0_VF4_1_DEVICE_CNTL2 0xfffe1030408c #define cfgBIF_CFG_DEV0_EPF0_VF4_1_DEVICE_STATUS2 0xfffe1030408e #define cfgBIF_CFG_DEV0_EPF0_VF4_1_LINK_CAP2 0xfffe10304090 #define cfgBIF_CFG_DEV0_EPF0_VF4_1_LINK_CNTL2 0xfffe10304094 #define cfgBIF_CFG_DEV0_EPF0_VF4_1_LINK_STATUS2 0xfffe10304096 #define cfgBIF_CFG_DEV0_EPF0_VF4_1_MSI_CAP_LIST 0xfffe103040a0 #define cfgBIF_CFG_DEV0_EPF0_VF4_1_MSI_MSG_CNTL 0xfffe103040a2 #define cfgBIF_CFG_DEV0_EPF0_VF4_1_MSI_MSG_ADDR_LO 0xfffe103040a4 #define cfgBIF_CFG_DEV0_EPF0_VF4_1_MSI_MSG_ADDR_HI 0xfffe103040a8 #define cfgBIF_CFG_DEV0_EPF0_VF4_1_MSI_MSG_DATA 0xfffe103040a8 #define cfgBIF_CFG_DEV0_EPF0_VF4_1_MSI_MASK 0xfffe103040ac #define cfgBIF_CFG_DEV0_EPF0_VF4_1_MSI_MSG_DATA_64 0xfffe103040ac #define cfgBIF_CFG_DEV0_EPF0_VF4_1_MSI_MASK_64 0xfffe103040b0 #define cfgBIF_CFG_DEV0_EPF0_VF4_1_MSI_PENDING 0xfffe103040b0 #define cfgBIF_CFG_DEV0_EPF0_VF4_1_MSI_PENDING_64 0xfffe103040b4 #define cfgBIF_CFG_DEV0_EPF0_VF4_1_MSIX_CAP_LIST 0xfffe103040c0 #define cfgBIF_CFG_DEV0_EPF0_VF4_1_MSIX_MSG_CNTL 0xfffe103040c2 #define cfgBIF_CFG_DEV0_EPF0_VF4_1_MSIX_TABLE 0xfffe103040c4 #define cfgBIF_CFG_DEV0_EPF0_VF4_1_MSIX_PBA 0xfffe103040c8 #define cfgBIF_CFG_DEV0_EPF0_VF4_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0xfffe10304100 #define cfgBIF_CFG_DEV0_EPF0_VF4_1_PCIE_VENDOR_SPECIFIC_HDR 0xfffe10304104 #define cfgBIF_CFG_DEV0_EPF0_VF4_1_PCIE_VENDOR_SPECIFIC1 0xfffe10304108 #define cfgBIF_CFG_DEV0_EPF0_VF4_1_PCIE_VENDOR_SPECIFIC2 0xfffe1030410c #define cfgBIF_CFG_DEV0_EPF0_VF4_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0xfffe10304150 #define cfgBIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_STATUS 0xfffe10304154 #define cfgBIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_MASK 0xfffe10304158 #define cfgBIF_CFG_DEV0_EPF0_VF4_1_PCIE_UNCORR_ERR_SEVERITY 0xfffe1030415c #define cfgBIF_CFG_DEV0_EPF0_VF4_1_PCIE_CORR_ERR_STATUS 0xfffe10304160 #define cfgBIF_CFG_DEV0_EPF0_VF4_1_PCIE_CORR_ERR_MASK 0xfffe10304164 #define cfgBIF_CFG_DEV0_EPF0_VF4_1_PCIE_ADV_ERR_CAP_CNTL 0xfffe10304168 #define cfgBIF_CFG_DEV0_EPF0_VF4_1_PCIE_HDR_LOG0 0xfffe1030416c #define cfgBIF_CFG_DEV0_EPF0_VF4_1_PCIE_HDR_LOG1 0xfffe10304170 #define cfgBIF_CFG_DEV0_EPF0_VF4_1_PCIE_HDR_LOG2 0xfffe10304174 #define cfgBIF_CFG_DEV0_EPF0_VF4_1_PCIE_HDR_LOG3 0xfffe10304178 #define cfgBIF_CFG_DEV0_EPF0_VF4_1_PCIE_TLP_PREFIX_LOG0 0xfffe10304188 #define cfgBIF_CFG_DEV0_EPF0_VF4_1_PCIE_TLP_PREFIX_LOG1 0xfffe1030418c #define cfgBIF_CFG_DEV0_EPF0_VF4_1_PCIE_TLP_PREFIX_LOG2 0xfffe10304190 #define cfgBIF_CFG_DEV0_EPF0_VF4_1_PCIE_TLP_PREFIX_LOG3 0xfffe10304194 #define cfgBIF_CFG_DEV0_EPF0_VF4_1_PCIE_ATS_ENH_CAP_LIST 0xfffe103042b0 #define cfgBIF_CFG_DEV0_EPF0_VF4_1_PCIE_ATS_CAP 0xfffe103042b4 #define cfgBIF_CFG_DEV0_EPF0_VF4_1_PCIE_ATS_CNTL 0xfffe103042b6 #define cfgBIF_CFG_DEV0_EPF0_VF4_1_PCIE_ARI_ENH_CAP_LIST 0xfffe10304328 #define cfgBIF_CFG_DEV0_EPF0_VF4_1_PCIE_ARI_CAP 0xfffe1030432c #define cfgBIF_CFG_DEV0_EPF0_VF4_1_PCIE_ARI_CNTL 0xfffe1030432e // addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf5_bifcfgdecp // base address: 0xfffe10305000 #define cfgBIF_CFG_DEV0_EPF0_VF5_1_VENDOR_ID 0xfffe10305000 #define cfgBIF_CFG_DEV0_EPF0_VF5_1_DEVICE_ID 0xfffe10305002 #define cfgBIF_CFG_DEV0_EPF0_VF5_1_COMMAND 0xfffe10305004 #define cfgBIF_CFG_DEV0_EPF0_VF5_1_STATUS 0xfffe10305006 #define cfgBIF_CFG_DEV0_EPF0_VF5_1_REVISION_ID 0xfffe10305008 #define cfgBIF_CFG_DEV0_EPF0_VF5_1_PROG_INTERFACE 0xfffe10305009 #define cfgBIF_CFG_DEV0_EPF0_VF5_1_SUB_CLASS 0xfffe1030500a #define cfgBIF_CFG_DEV0_EPF0_VF5_1_BASE_CLASS 0xfffe1030500b #define cfgBIF_CFG_DEV0_EPF0_VF5_1_CACHE_LINE 0xfffe1030500c #define cfgBIF_CFG_DEV0_EPF0_VF5_1_LATENCY 0xfffe1030500d #define cfgBIF_CFG_DEV0_EPF0_VF5_1_HEADER 0xfffe1030500e #define cfgBIF_CFG_DEV0_EPF0_VF5_1_BIST 0xfffe1030500f #define cfgBIF_CFG_DEV0_EPF0_VF5_1_BASE_ADDR_1 0xfffe10305010 #define cfgBIF_CFG_DEV0_EPF0_VF5_1_BASE_ADDR_2 0xfffe10305014 #define cfgBIF_CFG_DEV0_EPF0_VF5_1_BASE_ADDR_3 0xfffe10305018 #define cfgBIF_CFG_DEV0_EPF0_VF5_1_BASE_ADDR_4 0xfffe1030501c #define cfgBIF_CFG_DEV0_EPF0_VF5_1_BASE_ADDR_5 0xfffe10305020 #define cfgBIF_CFG_DEV0_EPF0_VF5_1_BASE_ADDR_6 0xfffe10305024 #define cfgBIF_CFG_DEV0_EPF0_VF5_1_CARDBUS_CIS_PTR 0xfffe10305028 #define cfgBIF_CFG_DEV0_EPF0_VF5_1_ADAPTER_ID 0xfffe1030502c #define cfgBIF_CFG_DEV0_EPF0_VF5_1_ROM_BASE_ADDR 0xfffe10305030 #define cfgBIF_CFG_DEV0_EPF0_VF5_1_CAP_PTR 0xfffe10305034 #define cfgBIF_CFG_DEV0_EPF0_VF5_1_INTERRUPT_LINE 0xfffe1030503c #define cfgBIF_CFG_DEV0_EPF0_VF5_1_INTERRUPT_PIN 0xfffe1030503d #define cfgBIF_CFG_DEV0_EPF0_VF5_1_MIN_GRANT 0xfffe1030503e #define cfgBIF_CFG_DEV0_EPF0_VF5_1_MAX_LATENCY 0xfffe1030503f #define cfgBIF_CFG_DEV0_EPF0_VF5_1_PCIE_CAP_LIST 0xfffe10305064 #define cfgBIF_CFG_DEV0_EPF0_VF5_1_PCIE_CAP 0xfffe10305066 #define cfgBIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CAP 0xfffe10305068 #define cfgBIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CNTL 0xfffe1030506c #define cfgBIF_CFG_DEV0_EPF0_VF5_1_DEVICE_STATUS 0xfffe1030506e #define cfgBIF_CFG_DEV0_EPF0_VF5_1_LINK_CAP 0xfffe10305070 #define cfgBIF_CFG_DEV0_EPF0_VF5_1_LINK_CNTL 0xfffe10305074 #define cfgBIF_CFG_DEV0_EPF0_VF5_1_LINK_STATUS 0xfffe10305076 #define cfgBIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CAP2 0xfffe10305088 #define cfgBIF_CFG_DEV0_EPF0_VF5_1_DEVICE_CNTL2 0xfffe1030508c #define cfgBIF_CFG_DEV0_EPF0_VF5_1_DEVICE_STATUS2 0xfffe1030508e #define cfgBIF_CFG_DEV0_EPF0_VF5_1_LINK_CAP2 0xfffe10305090 #define cfgBIF_CFG_DEV0_EPF0_VF5_1_LINK_CNTL2 0xfffe10305094 #define cfgBIF_CFG_DEV0_EPF0_VF5_1_LINK_STATUS2 0xfffe10305096 #define cfgBIF_CFG_DEV0_EPF0_VF5_1_MSI_CAP_LIST 0xfffe103050a0 #define cfgBIF_CFG_DEV0_EPF0_VF5_1_MSI_MSG_CNTL 0xfffe103050a2 #define cfgBIF_CFG_DEV0_EPF0_VF5_1_MSI_MSG_ADDR_LO 0xfffe103050a4 #define cfgBIF_CFG_DEV0_EPF0_VF5_1_MSI_MSG_ADDR_HI 0xfffe103050a8 #define cfgBIF_CFG_DEV0_EPF0_VF5_1_MSI_MSG_DATA 0xfffe103050a8 #define cfgBIF_CFG_DEV0_EPF0_VF5_1_MSI_MASK 0xfffe103050ac #define cfgBIF_CFG_DEV0_EPF0_VF5_1_MSI_MSG_DATA_64 0xfffe103050ac #define cfgBIF_CFG_DEV0_EPF0_VF5_1_MSI_MASK_64 0xfffe103050b0 #define cfgBIF_CFG_DEV0_EPF0_VF5_1_MSI_PENDING 0xfffe103050b0 #define cfgBIF_CFG_DEV0_EPF0_VF5_1_MSI_PENDING_64 0xfffe103050b4 #define cfgBIF_CFG_DEV0_EPF0_VF5_1_MSIX_CAP_LIST 0xfffe103050c0 #define cfgBIF_CFG_DEV0_EPF0_VF5_1_MSIX_MSG_CNTL 0xfffe103050c2 #define cfgBIF_CFG_DEV0_EPF0_VF5_1_MSIX_TABLE 0xfffe103050c4 #define cfgBIF_CFG_DEV0_EPF0_VF5_1_MSIX_PBA 0xfffe103050c8 #define cfgBIF_CFG_DEV0_EPF0_VF5_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0xfffe10305100 #define cfgBIF_CFG_DEV0_EPF0_VF5_1_PCIE_VENDOR_SPECIFIC_HDR 0xfffe10305104 #define cfgBIF_CFG_DEV0_EPF0_VF5_1_PCIE_VENDOR_SPECIFIC1 0xfffe10305108 #define cfgBIF_CFG_DEV0_EPF0_VF5_1_PCIE_VENDOR_SPECIFIC2 0xfffe1030510c #define cfgBIF_CFG_DEV0_EPF0_VF5_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0xfffe10305150 #define cfgBIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_STATUS 0xfffe10305154 #define cfgBIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_MASK 0xfffe10305158 #define cfgBIF_CFG_DEV0_EPF0_VF5_1_PCIE_UNCORR_ERR_SEVERITY 0xfffe1030515c #define cfgBIF_CFG_DEV0_EPF0_VF5_1_PCIE_CORR_ERR_STATUS 0xfffe10305160 #define cfgBIF_CFG_DEV0_EPF0_VF5_1_PCIE_CORR_ERR_MASK 0xfffe10305164 #define cfgBIF_CFG_DEV0_EPF0_VF5_1_PCIE_ADV_ERR_CAP_CNTL 0xfffe10305168 #define cfgBIF_CFG_DEV0_EPF0_VF5_1_PCIE_HDR_LOG0 0xfffe1030516c #define cfgBIF_CFG_DEV0_EPF0_VF5_1_PCIE_HDR_LOG1 0xfffe10305170 #define cfgBIF_CFG_DEV0_EPF0_VF5_1_PCIE_HDR_LOG2 0xfffe10305174 #define cfgBIF_CFG_DEV0_EPF0_VF5_1_PCIE_HDR_LOG3 0xfffe10305178 #define cfgBIF_CFG_DEV0_EPF0_VF5_1_PCIE_TLP_PREFIX_LOG0 0xfffe10305188 #define cfgBIF_CFG_DEV0_EPF0_VF5_1_PCIE_TLP_PREFIX_LOG1 0xfffe1030518c #define cfgBIF_CFG_DEV0_EPF0_VF5_1_PCIE_TLP_PREFIX_LOG2 0xfffe10305190 #define cfgBIF_CFG_DEV0_EPF0_VF5_1_PCIE_TLP_PREFIX_LOG3 0xfffe10305194 #define cfgBIF_CFG_DEV0_EPF0_VF5_1_PCIE_ATS_ENH_CAP_LIST 0xfffe103052b0 #define cfgBIF_CFG_DEV0_EPF0_VF5_1_PCIE_ATS_CAP 0xfffe103052b4 #define cfgBIF_CFG_DEV0_EPF0_VF5_1_PCIE_ATS_CNTL 0xfffe103052b6 #define cfgBIF_CFG_DEV0_EPF0_VF5_1_PCIE_ARI_ENH_CAP_LIST 0xfffe10305328 #define cfgBIF_CFG_DEV0_EPF0_VF5_1_PCIE_ARI_CAP 0xfffe1030532c #define cfgBIF_CFG_DEV0_EPF0_VF5_1_PCIE_ARI_CNTL 0xfffe1030532e // addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf6_bifcfgdecp // base address: 0xfffe10306000 #define cfgBIF_CFG_DEV0_EPF0_VF6_1_VENDOR_ID 0xfffe10306000 #define cfgBIF_CFG_DEV0_EPF0_VF6_1_DEVICE_ID 0xfffe10306002 #define cfgBIF_CFG_DEV0_EPF0_VF6_1_COMMAND 0xfffe10306004 #define cfgBIF_CFG_DEV0_EPF0_VF6_1_STATUS 0xfffe10306006 #define cfgBIF_CFG_DEV0_EPF0_VF6_1_REVISION_ID 0xfffe10306008 #define cfgBIF_CFG_DEV0_EPF0_VF6_1_PROG_INTERFACE 0xfffe10306009 #define cfgBIF_CFG_DEV0_EPF0_VF6_1_SUB_CLASS 0xfffe1030600a #define cfgBIF_CFG_DEV0_EPF0_VF6_1_BASE_CLASS 0xfffe1030600b #define cfgBIF_CFG_DEV0_EPF0_VF6_1_CACHE_LINE 0xfffe1030600c #define cfgBIF_CFG_DEV0_EPF0_VF6_1_LATENCY 0xfffe1030600d #define cfgBIF_CFG_DEV0_EPF0_VF6_1_HEADER 0xfffe1030600e #define cfgBIF_CFG_DEV0_EPF0_VF6_1_BIST 0xfffe1030600f #define cfgBIF_CFG_DEV0_EPF0_VF6_1_BASE_ADDR_1 0xfffe10306010 #define cfgBIF_CFG_DEV0_EPF0_VF6_1_BASE_ADDR_2 0xfffe10306014 #define cfgBIF_CFG_DEV0_EPF0_VF6_1_BASE_ADDR_3 0xfffe10306018 #define cfgBIF_CFG_DEV0_EPF0_VF6_1_BASE_ADDR_4 0xfffe1030601c #define cfgBIF_CFG_DEV0_EPF0_VF6_1_BASE_ADDR_5 0xfffe10306020 #define cfgBIF_CFG_DEV0_EPF0_VF6_1_BASE_ADDR_6 0xfffe10306024 #define cfgBIF_CFG_DEV0_EPF0_VF6_1_CARDBUS_CIS_PTR 0xfffe10306028 #define cfgBIF_CFG_DEV0_EPF0_VF6_1_ADAPTER_ID 0xfffe1030602c #define cfgBIF_CFG_DEV0_EPF0_VF6_1_ROM_BASE_ADDR 0xfffe10306030 #define cfgBIF_CFG_DEV0_EPF0_VF6_1_CAP_PTR 0xfffe10306034 #define cfgBIF_CFG_DEV0_EPF0_VF6_1_INTERRUPT_LINE 0xfffe1030603c #define cfgBIF_CFG_DEV0_EPF0_VF6_1_INTERRUPT_PIN 0xfffe1030603d #define cfgBIF_CFG_DEV0_EPF0_VF6_1_MIN_GRANT 0xfffe1030603e #define cfgBIF_CFG_DEV0_EPF0_VF6_1_MAX_LATENCY 0xfffe1030603f #define cfgBIF_CFG_DEV0_EPF0_VF6_1_PCIE_CAP_LIST 0xfffe10306064 #define cfgBIF_CFG_DEV0_EPF0_VF6_1_PCIE_CAP 0xfffe10306066 #define cfgBIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CAP 0xfffe10306068 #define cfgBIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CNTL 0xfffe1030606c #define cfgBIF_CFG_DEV0_EPF0_VF6_1_DEVICE_STATUS 0xfffe1030606e #define cfgBIF_CFG_DEV0_EPF0_VF6_1_LINK_CAP 0xfffe10306070 #define cfgBIF_CFG_DEV0_EPF0_VF6_1_LINK_CNTL 0xfffe10306074 #define cfgBIF_CFG_DEV0_EPF0_VF6_1_LINK_STATUS 0xfffe10306076 #define cfgBIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CAP2 0xfffe10306088 #define cfgBIF_CFG_DEV0_EPF0_VF6_1_DEVICE_CNTL2 0xfffe1030608c #define cfgBIF_CFG_DEV0_EPF0_VF6_1_DEVICE_STATUS2 0xfffe1030608e #define cfgBIF_CFG_DEV0_EPF0_VF6_1_LINK_CAP2 0xfffe10306090 #define cfgBIF_CFG_DEV0_EPF0_VF6_1_LINK_CNTL2 0xfffe10306094 #define cfgBIF_CFG_DEV0_EPF0_VF6_1_LINK_STATUS2 0xfffe10306096 #define cfgBIF_CFG_DEV0_EPF0_VF6_1_MSI_CAP_LIST 0xfffe103060a0 #define cfgBIF_CFG_DEV0_EPF0_VF6_1_MSI_MSG_CNTL 0xfffe103060a2 #define cfgBIF_CFG_DEV0_EPF0_VF6_1_MSI_MSG_ADDR_LO 0xfffe103060a4 #define cfgBIF_CFG_DEV0_EPF0_VF6_1_MSI_MSG_ADDR_HI 0xfffe103060a8 #define cfgBIF_CFG_DEV0_EPF0_VF6_1_MSI_MSG_DATA 0xfffe103060a8 #define cfgBIF_CFG_DEV0_EPF0_VF6_1_MSI_MASK 0xfffe103060ac #define cfgBIF_CFG_DEV0_EPF0_VF6_1_MSI_MSG_DATA_64 0xfffe103060ac #define cfgBIF_CFG_DEV0_EPF0_VF6_1_MSI_MASK_64 0xfffe103060b0 #define cfgBIF_CFG_DEV0_EPF0_VF6_1_MSI_PENDING 0xfffe103060b0 #define cfgBIF_CFG_DEV0_EPF0_VF6_1_MSI_PENDING_64 0xfffe103060b4 #define cfgBIF_CFG_DEV0_EPF0_VF6_1_MSIX_CAP_LIST 0xfffe103060c0 #define cfgBIF_CFG_DEV0_EPF0_VF6_1_MSIX_MSG_CNTL 0xfffe103060c2 #define cfgBIF_CFG_DEV0_EPF0_VF6_1_MSIX_TABLE 0xfffe103060c4 #define cfgBIF_CFG_DEV0_EPF0_VF6_1_MSIX_PBA 0xfffe103060c8 #define cfgBIF_CFG_DEV0_EPF0_VF6_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0xfffe10306100 #define cfgBIF_CFG_DEV0_EPF0_VF6_1_PCIE_VENDOR_SPECIFIC_HDR 0xfffe10306104 #define cfgBIF_CFG_DEV0_EPF0_VF6_1_PCIE_VENDOR_SPECIFIC1 0xfffe10306108 #define cfgBIF_CFG_DEV0_EPF0_VF6_1_PCIE_VENDOR_SPECIFIC2 0xfffe1030610c #define cfgBIF_CFG_DEV0_EPF0_VF6_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0xfffe10306150 #define cfgBIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_STATUS 0xfffe10306154 #define cfgBIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_MASK 0xfffe10306158 #define cfgBIF_CFG_DEV0_EPF0_VF6_1_PCIE_UNCORR_ERR_SEVERITY 0xfffe1030615c #define cfgBIF_CFG_DEV0_EPF0_VF6_1_PCIE_CORR_ERR_STATUS 0xfffe10306160 #define cfgBIF_CFG_DEV0_EPF0_VF6_1_PCIE_CORR_ERR_MASK 0xfffe10306164 #define cfgBIF_CFG_DEV0_EPF0_VF6_1_PCIE_ADV_ERR_CAP_CNTL 0xfffe10306168 #define cfgBIF_CFG_DEV0_EPF0_VF6_1_PCIE_HDR_LOG0 0xfffe1030616c #define cfgBIF_CFG_DEV0_EPF0_VF6_1_PCIE_HDR_LOG1 0xfffe10306170 #define cfgBIF_CFG_DEV0_EPF0_VF6_1_PCIE_HDR_LOG2 0xfffe10306174 #define cfgBIF_CFG_DEV0_EPF0_VF6_1_PCIE_HDR_LOG3 0xfffe10306178 #define cfgBIF_CFG_DEV0_EPF0_VF6_1_PCIE_TLP_PREFIX_LOG0 0xfffe10306188 #define cfgBIF_CFG_DEV0_EPF0_VF6_1_PCIE_TLP_PREFIX_LOG1 0xfffe1030618c #define cfgBIF_CFG_DEV0_EPF0_VF6_1_PCIE_TLP_PREFIX_LOG2 0xfffe10306190 #define cfgBIF_CFG_DEV0_EPF0_VF6_1_PCIE_TLP_PREFIX_LOG3 0xfffe10306194 #define cfgBIF_CFG_DEV0_EPF0_VF6_1_PCIE_ATS_ENH_CAP_LIST 0xfffe103062b0 #define cfgBIF_CFG_DEV0_EPF0_VF6_1_PCIE_ATS_CAP 0xfffe103062b4 #define cfgBIF_CFG_DEV0_EPF0_VF6_1_PCIE_ATS_CNTL 0xfffe103062b6 #define cfgBIF_CFG_DEV0_EPF0_VF6_1_PCIE_ARI_ENH_CAP_LIST 0xfffe10306328 #define cfgBIF_CFG_DEV0_EPF0_VF6_1_PCIE_ARI_CAP 0xfffe1030632c #define cfgBIF_CFG_DEV0_EPF0_VF6_1_PCIE_ARI_CNTL 0xfffe1030632e // addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf7_bifcfgdecp // base address: 0xfffe10307000 #define cfgBIF_CFG_DEV0_EPF0_VF7_1_VENDOR_ID 0xfffe10307000 #define cfgBIF_CFG_DEV0_EPF0_VF7_1_DEVICE_ID 0xfffe10307002 #define cfgBIF_CFG_DEV0_EPF0_VF7_1_COMMAND 0xfffe10307004 #define cfgBIF_CFG_DEV0_EPF0_VF7_1_STATUS 0xfffe10307006 #define cfgBIF_CFG_DEV0_EPF0_VF7_1_REVISION_ID 0xfffe10307008 #define cfgBIF_CFG_DEV0_EPF0_VF7_1_PROG_INTERFACE 0xfffe10307009 #define cfgBIF_CFG_DEV0_EPF0_VF7_1_SUB_CLASS 0xfffe1030700a #define cfgBIF_CFG_DEV0_EPF0_VF7_1_BASE_CLASS 0xfffe1030700b #define cfgBIF_CFG_DEV0_EPF0_VF7_1_CACHE_LINE 0xfffe1030700c #define cfgBIF_CFG_DEV0_EPF0_VF7_1_LATENCY 0xfffe1030700d #define cfgBIF_CFG_DEV0_EPF0_VF7_1_HEADER 0xfffe1030700e #define cfgBIF_CFG_DEV0_EPF0_VF7_1_BIST 0xfffe1030700f #define cfgBIF_CFG_DEV0_EPF0_VF7_1_BASE_ADDR_1 0xfffe10307010 #define cfgBIF_CFG_DEV0_EPF0_VF7_1_BASE_ADDR_2 0xfffe10307014 #define cfgBIF_CFG_DEV0_EPF0_VF7_1_BASE_ADDR_3 0xfffe10307018 #define cfgBIF_CFG_DEV0_EPF0_VF7_1_BASE_ADDR_4 0xfffe1030701c #define cfgBIF_CFG_DEV0_EPF0_VF7_1_BASE_ADDR_5 0xfffe10307020 #define cfgBIF_CFG_DEV0_EPF0_VF7_1_BASE_ADDR_6 0xfffe10307024 #define cfgBIF_CFG_DEV0_EPF0_VF7_1_CARDBUS_CIS_PTR 0xfffe10307028 #define cfgBIF_CFG_DEV0_EPF0_VF7_1_ADAPTER_ID 0xfffe1030702c #define cfgBIF_CFG_DEV0_EPF0_VF7_1_ROM_BASE_ADDR 0xfffe10307030 #define cfgBIF_CFG_DEV0_EPF0_VF7_1_CAP_PTR 0xfffe10307034 #define cfgBIF_CFG_DEV0_EPF0_VF7_1_INTERRUPT_LINE 0xfffe1030703c #define cfgBIF_CFG_DEV0_EPF0_VF7_1_INTERRUPT_PIN 0xfffe1030703d #define cfgBIF_CFG_DEV0_EPF0_VF7_1_MIN_GRANT 0xfffe1030703e #define cfgBIF_CFG_DEV0_EPF0_VF7_1_MAX_LATENCY 0xfffe1030703f #define cfgBIF_CFG_DEV0_EPF0_VF7_1_PCIE_CAP_LIST 0xfffe10307064 #define cfgBIF_CFG_DEV0_EPF0_VF7_1_PCIE_CAP 0xfffe10307066 #define cfgBIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CAP 0xfffe10307068 #define cfgBIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CNTL 0xfffe1030706c #define cfgBIF_CFG_DEV0_EPF0_VF7_1_DEVICE_STATUS 0xfffe1030706e #define cfgBIF_CFG_DEV0_EPF0_VF7_1_LINK_CAP 0xfffe10307070 #define cfgBIF_CFG_DEV0_EPF0_VF7_1_LINK_CNTL 0xfffe10307074 #define cfgBIF_CFG_DEV0_EPF0_VF7_1_LINK_STATUS 0xfffe10307076 #define cfgBIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CAP2 0xfffe10307088 #define cfgBIF_CFG_DEV0_EPF0_VF7_1_DEVICE_CNTL2 0xfffe1030708c #define cfgBIF_CFG_DEV0_EPF0_VF7_1_DEVICE_STATUS2 0xfffe1030708e #define cfgBIF_CFG_DEV0_EPF0_VF7_1_LINK_CAP2 0xfffe10307090 #define cfgBIF_CFG_DEV0_EPF0_VF7_1_LINK_CNTL2 0xfffe10307094 #define cfgBIF_CFG_DEV0_EPF0_VF7_1_LINK_STATUS2 0xfffe10307096 #define cfgBIF_CFG_DEV0_EPF0_VF7_1_MSI_CAP_LIST 0xfffe103070a0 #define cfgBIF_CFG_DEV0_EPF0_VF7_1_MSI_MSG_CNTL 0xfffe103070a2 #define cfgBIF_CFG_DEV0_EPF0_VF7_1_MSI_MSG_ADDR_LO 0xfffe103070a4 #define cfgBIF_CFG_DEV0_EPF0_VF7_1_MSI_MSG_ADDR_HI 0xfffe103070a8 #define cfgBIF_CFG_DEV0_EPF0_VF7_1_MSI_MSG_DATA 0xfffe103070a8 #define cfgBIF_CFG_DEV0_EPF0_VF7_1_MSI_MASK 0xfffe103070ac #define cfgBIF_CFG_DEV0_EPF0_VF7_1_MSI_MSG_DATA_64 0xfffe103070ac #define cfgBIF_CFG_DEV0_EPF0_VF7_1_MSI_MASK_64 0xfffe103070b0 #define cfgBIF_CFG_DEV0_EPF0_VF7_1_MSI_PENDING 0xfffe103070b0 #define cfgBIF_CFG_DEV0_EPF0_VF7_1_MSI_PENDING_64 0xfffe103070b4 #define cfgBIF_CFG_DEV0_EPF0_VF7_1_MSIX_CAP_LIST 0xfffe103070c0 #define cfgBIF_CFG_DEV0_EPF0_VF7_1_MSIX_MSG_CNTL 0xfffe103070c2 #define cfgBIF_CFG_DEV0_EPF0_VF7_1_MSIX_TABLE 0xfffe103070c4 #define cfgBIF_CFG_DEV0_EPF0_VF7_1_MSIX_PBA 0xfffe103070c8 #define cfgBIF_CFG_DEV0_EPF0_VF7_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0xfffe10307100 #define cfgBIF_CFG_DEV0_EPF0_VF7_1_PCIE_VENDOR_SPECIFIC_HDR 0xfffe10307104 #define cfgBIF_CFG_DEV0_EPF0_VF7_1_PCIE_VENDOR_SPECIFIC1 0xfffe10307108 #define cfgBIF_CFG_DEV0_EPF0_VF7_1_PCIE_VENDOR_SPECIFIC2 0xfffe1030710c #define cfgBIF_CFG_DEV0_EPF0_VF7_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0xfffe10307150 #define cfgBIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_STATUS 0xfffe10307154 #define cfgBIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_MASK 0xfffe10307158 #define cfgBIF_CFG_DEV0_EPF0_VF7_1_PCIE_UNCORR_ERR_SEVERITY 0xfffe1030715c #define cfgBIF_CFG_DEV0_EPF0_VF7_1_PCIE_CORR_ERR_STATUS 0xfffe10307160 #define cfgBIF_CFG_DEV0_EPF0_VF7_1_PCIE_CORR_ERR_MASK 0xfffe10307164 #define cfgBIF_CFG_DEV0_EPF0_VF7_1_PCIE_ADV_ERR_CAP_CNTL 0xfffe10307168 #define cfgBIF_CFG_DEV0_EPF0_VF7_1_PCIE_HDR_LOG0 0xfffe1030716c #define cfgBIF_CFG_DEV0_EPF0_VF7_1_PCIE_HDR_LOG1 0xfffe10307170 #define cfgBIF_CFG_DEV0_EPF0_VF7_1_PCIE_HDR_LOG2 0xfffe10307174 #define cfgBIF_CFG_DEV0_EPF0_VF7_1_PCIE_HDR_LOG3 0xfffe10307178 #define cfgBIF_CFG_DEV0_EPF0_VF7_1_PCIE_TLP_PREFIX_LOG0 0xfffe10307188 #define cfgBIF_CFG_DEV0_EPF0_VF7_1_PCIE_TLP_PREFIX_LOG1 0xfffe1030718c #define cfgBIF_CFG_DEV0_EPF0_VF7_1_PCIE_TLP_PREFIX_LOG2 0xfffe10307190 #define cfgBIF_CFG_DEV0_EPF0_VF7_1_PCIE_TLP_PREFIX_LOG3 0xfffe10307194 #define cfgBIF_CFG_DEV0_EPF0_VF7_1_PCIE_ATS_ENH_CAP_LIST 0xfffe103072b0 #define cfgBIF_CFG_DEV0_EPF0_VF7_1_PCIE_ATS_CAP 0xfffe103072b4 #define cfgBIF_CFG_DEV0_EPF0_VF7_1_PCIE_ATS_CNTL 0xfffe103072b6 #define cfgBIF_CFG_DEV0_EPF0_VF7_1_PCIE_ARI_ENH_CAP_LIST 0xfffe10307328 #define cfgBIF_CFG_DEV0_EPF0_VF7_1_PCIE_ARI_CAP 0xfffe1030732c #define cfgBIF_CFG_DEV0_EPF0_VF7_1_PCIE_ARI_CNTL 0xfffe1030732e // addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf8_bifcfgdecp // base address: 0xfffe10308000 #define cfgBIF_CFG_DEV0_EPF0_VF8_1_VENDOR_ID 0xfffe10308000 #define cfgBIF_CFG_DEV0_EPF0_VF8_1_DEVICE_ID 0xfffe10308002 #define cfgBIF_CFG_DEV0_EPF0_VF8_1_COMMAND 0xfffe10308004 #define cfgBIF_CFG_DEV0_EPF0_VF8_1_STATUS 0xfffe10308006 #define cfgBIF_CFG_DEV0_EPF0_VF8_1_REVISION_ID 0xfffe10308008 #define cfgBIF_CFG_DEV0_EPF0_VF8_1_PROG_INTERFACE 0xfffe10308009 #define cfgBIF_CFG_DEV0_EPF0_VF8_1_SUB_CLASS 0xfffe1030800a #define cfgBIF_CFG_DEV0_EPF0_VF8_1_BASE_CLASS 0xfffe1030800b #define cfgBIF_CFG_DEV0_EPF0_VF8_1_CACHE_LINE 0xfffe1030800c #define cfgBIF_CFG_DEV0_EPF0_VF8_1_LATENCY 0xfffe1030800d #define cfgBIF_CFG_DEV0_EPF0_VF8_1_HEADER 0xfffe1030800e #define cfgBIF_CFG_DEV0_EPF0_VF8_1_BIST 0xfffe1030800f #define cfgBIF_CFG_DEV0_EPF0_VF8_1_BASE_ADDR_1 0xfffe10308010 #define cfgBIF_CFG_DEV0_EPF0_VF8_1_BASE_ADDR_2 0xfffe10308014 #define cfgBIF_CFG_DEV0_EPF0_VF8_1_BASE_ADDR_3 0xfffe10308018 #define cfgBIF_CFG_DEV0_EPF0_VF8_1_BASE_ADDR_4 0xfffe1030801c #define cfgBIF_CFG_DEV0_EPF0_VF8_1_BASE_ADDR_5 0xfffe10308020 #define cfgBIF_CFG_DEV0_EPF0_VF8_1_BASE_ADDR_6 0xfffe10308024 #define cfgBIF_CFG_DEV0_EPF0_VF8_1_CARDBUS_CIS_PTR 0xfffe10308028 #define cfgBIF_CFG_DEV0_EPF0_VF8_1_ADAPTER_ID 0xfffe1030802c #define cfgBIF_CFG_DEV0_EPF0_VF8_1_ROM_BASE_ADDR 0xfffe10308030 #define cfgBIF_CFG_DEV0_EPF0_VF8_1_CAP_PTR 0xfffe10308034 #define cfgBIF_CFG_DEV0_EPF0_VF8_1_INTERRUPT_LINE 0xfffe1030803c #define cfgBIF_CFG_DEV0_EPF0_VF8_1_INTERRUPT_PIN 0xfffe1030803d #define cfgBIF_CFG_DEV0_EPF0_VF8_1_MIN_GRANT 0xfffe1030803e #define cfgBIF_CFG_DEV0_EPF0_VF8_1_MAX_LATENCY 0xfffe1030803f #define cfgBIF_CFG_DEV0_EPF0_VF8_1_PCIE_CAP_LIST 0xfffe10308064 #define cfgBIF_CFG_DEV0_EPF0_VF8_1_PCIE_CAP 0xfffe10308066 #define cfgBIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CAP 0xfffe10308068 #define cfgBIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CNTL 0xfffe1030806c #define cfgBIF_CFG_DEV0_EPF0_VF8_1_DEVICE_STATUS 0xfffe1030806e #define cfgBIF_CFG_DEV0_EPF0_VF8_1_LINK_CAP 0xfffe10308070 #define cfgBIF_CFG_DEV0_EPF0_VF8_1_LINK_CNTL 0xfffe10308074 #define cfgBIF_CFG_DEV0_EPF0_VF8_1_LINK_STATUS 0xfffe10308076 #define cfgBIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CAP2 0xfffe10308088 #define cfgBIF_CFG_DEV0_EPF0_VF8_1_DEVICE_CNTL2 0xfffe1030808c #define cfgBIF_CFG_DEV0_EPF0_VF8_1_DEVICE_STATUS2 0xfffe1030808e #define cfgBIF_CFG_DEV0_EPF0_VF8_1_LINK_CAP2 0xfffe10308090 #define cfgBIF_CFG_DEV0_EPF0_VF8_1_LINK_CNTL2 0xfffe10308094 #define cfgBIF_CFG_DEV0_EPF0_VF8_1_LINK_STATUS2 0xfffe10308096 #define cfgBIF_CFG_DEV0_EPF0_VF8_1_MSI_CAP_LIST 0xfffe103080a0 #define cfgBIF_CFG_DEV0_EPF0_VF8_1_MSI_MSG_CNTL 0xfffe103080a2 #define cfgBIF_CFG_DEV0_EPF0_VF8_1_MSI_MSG_ADDR_LO 0xfffe103080a4 #define cfgBIF_CFG_DEV0_EPF0_VF8_1_MSI_MSG_ADDR_HI 0xfffe103080a8 #define cfgBIF_CFG_DEV0_EPF0_VF8_1_MSI_MSG_DATA 0xfffe103080a8 #define cfgBIF_CFG_DEV0_EPF0_VF8_1_MSI_MASK 0xfffe103080ac #define cfgBIF_CFG_DEV0_EPF0_VF8_1_MSI_MSG_DATA_64 0xfffe103080ac #define cfgBIF_CFG_DEV0_EPF0_VF8_1_MSI_MASK_64 0xfffe103080b0 #define cfgBIF_CFG_DEV0_EPF0_VF8_1_MSI_PENDING 0xfffe103080b0 #define cfgBIF_CFG_DEV0_EPF0_VF8_1_MSI_PENDING_64 0xfffe103080b4 #define cfgBIF_CFG_DEV0_EPF0_VF8_1_MSIX_CAP_LIST 0xfffe103080c0 #define cfgBIF_CFG_DEV0_EPF0_VF8_1_MSIX_MSG_CNTL 0xfffe103080c2 #define cfgBIF_CFG_DEV0_EPF0_VF8_1_MSIX_TABLE 0xfffe103080c4 #define cfgBIF_CFG_DEV0_EPF0_VF8_1_MSIX_PBA 0xfffe103080c8 #define cfgBIF_CFG_DEV0_EPF0_VF8_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0xfffe10308100 #define cfgBIF_CFG_DEV0_EPF0_VF8_1_PCIE_VENDOR_SPECIFIC_HDR 0xfffe10308104 #define cfgBIF_CFG_DEV0_EPF0_VF8_1_PCIE_VENDOR_SPECIFIC1 0xfffe10308108 #define cfgBIF_CFG_DEV0_EPF0_VF8_1_PCIE_VENDOR_SPECIFIC2 0xfffe1030810c #define cfgBIF_CFG_DEV0_EPF0_VF8_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0xfffe10308150 #define cfgBIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_STATUS 0xfffe10308154 #define cfgBIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_MASK 0xfffe10308158 #define cfgBIF_CFG_DEV0_EPF0_VF8_1_PCIE_UNCORR_ERR_SEVERITY 0xfffe1030815c #define cfgBIF_CFG_DEV0_EPF0_VF8_1_PCIE_CORR_ERR_STATUS 0xfffe10308160 #define cfgBIF_CFG_DEV0_EPF0_VF8_1_PCIE_CORR_ERR_MASK 0xfffe10308164 #define cfgBIF_CFG_DEV0_EPF0_VF8_1_PCIE_ADV_ERR_CAP_CNTL 0xfffe10308168 #define cfgBIF_CFG_DEV0_EPF0_VF8_1_PCIE_HDR_LOG0 0xfffe1030816c #define cfgBIF_CFG_DEV0_EPF0_VF8_1_PCIE_HDR_LOG1 0xfffe10308170 #define cfgBIF_CFG_DEV0_EPF0_VF8_1_PCIE_HDR_LOG2 0xfffe10308174 #define cfgBIF_CFG_DEV0_EPF0_VF8_1_PCIE_HDR_LOG3 0xfffe10308178 #define cfgBIF_CFG_DEV0_EPF0_VF8_1_PCIE_TLP_PREFIX_LOG0 0xfffe10308188 #define cfgBIF_CFG_DEV0_EPF0_VF8_1_PCIE_TLP_PREFIX_LOG1 0xfffe1030818c #define cfgBIF_CFG_DEV0_EPF0_VF8_1_PCIE_TLP_PREFIX_LOG2 0xfffe10308190 #define cfgBIF_CFG_DEV0_EPF0_VF8_1_PCIE_TLP_PREFIX_LOG3 0xfffe10308194 #define cfgBIF_CFG_DEV0_EPF0_VF8_1_PCIE_ATS_ENH_CAP_LIST 0xfffe103082b0 #define cfgBIF_CFG_DEV0_EPF0_VF8_1_PCIE_ATS_CAP 0xfffe103082b4 #define cfgBIF_CFG_DEV0_EPF0_VF8_1_PCIE_ATS_CNTL 0xfffe103082b6 #define cfgBIF_CFG_DEV0_EPF0_VF8_1_PCIE_ARI_ENH_CAP_LIST 0xfffe10308328 #define cfgBIF_CFG_DEV0_EPF0_VF8_1_PCIE_ARI_CAP 0xfffe1030832c #define cfgBIF_CFG_DEV0_EPF0_VF8_1_PCIE_ARI_CNTL 0xfffe1030832e // addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf9_bifcfgdecp // base address: 0xfffe10309000 #define cfgBIF_CFG_DEV0_EPF0_VF9_1_VENDOR_ID 0xfffe10309000 #define cfgBIF_CFG_DEV0_EPF0_VF9_1_DEVICE_ID 0xfffe10309002 #define cfgBIF_CFG_DEV0_EPF0_VF9_1_COMMAND 0xfffe10309004 #define cfgBIF_CFG_DEV0_EPF0_VF9_1_STATUS 0xfffe10309006 #define cfgBIF_CFG_DEV0_EPF0_VF9_1_REVISION_ID 0xfffe10309008 #define cfgBIF_CFG_DEV0_EPF0_VF9_1_PROG_INTERFACE 0xfffe10309009 #define cfgBIF_CFG_DEV0_EPF0_VF9_1_SUB_CLASS 0xfffe1030900a #define cfgBIF_CFG_DEV0_EPF0_VF9_1_BASE_CLASS 0xfffe1030900b #define cfgBIF_CFG_DEV0_EPF0_VF9_1_CACHE_LINE 0xfffe1030900c #define cfgBIF_CFG_DEV0_EPF0_VF9_1_LATENCY 0xfffe1030900d #define cfgBIF_CFG_DEV0_EPF0_VF9_1_HEADER 0xfffe1030900e #define cfgBIF_CFG_DEV0_EPF0_VF9_1_BIST 0xfffe1030900f #define cfgBIF_CFG_DEV0_EPF0_VF9_1_BASE_ADDR_1 0xfffe10309010 #define cfgBIF_CFG_DEV0_EPF0_VF9_1_BASE_ADDR_2 0xfffe10309014 #define cfgBIF_CFG_DEV0_EPF0_VF9_1_BASE_ADDR_3 0xfffe10309018 #define cfgBIF_CFG_DEV0_EPF0_VF9_1_BASE_ADDR_4 0xfffe1030901c #define cfgBIF_CFG_DEV0_EPF0_VF9_1_BASE_ADDR_5 0xfffe10309020 #define cfgBIF_CFG_DEV0_EPF0_VF9_1_BASE_ADDR_6 0xfffe10309024 #define cfgBIF_CFG_DEV0_EPF0_VF9_1_CARDBUS_CIS_PTR 0xfffe10309028 #define cfgBIF_CFG_DEV0_EPF0_VF9_1_ADAPTER_ID 0xfffe1030902c #define cfgBIF_CFG_DEV0_EPF0_VF9_1_ROM_BASE_ADDR 0xfffe10309030 #define cfgBIF_CFG_DEV0_EPF0_VF9_1_CAP_PTR 0xfffe10309034 #define cfgBIF_CFG_DEV0_EPF0_VF9_1_INTERRUPT_LINE 0xfffe1030903c #define cfgBIF_CFG_DEV0_EPF0_VF9_1_INTERRUPT_PIN 0xfffe1030903d #define cfgBIF_CFG_DEV0_EPF0_VF9_1_MIN_GRANT 0xfffe1030903e #define cfgBIF_CFG_DEV0_EPF0_VF9_1_MAX_LATENCY 0xfffe1030903f #define cfgBIF_CFG_DEV0_EPF0_VF9_1_PCIE_CAP_LIST 0xfffe10309064 #define cfgBIF_CFG_DEV0_EPF0_VF9_1_PCIE_CAP 0xfffe10309066 #define cfgBIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CAP 0xfffe10309068 #define cfgBIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CNTL 0xfffe1030906c #define cfgBIF_CFG_DEV0_EPF0_VF9_1_DEVICE_STATUS 0xfffe1030906e #define cfgBIF_CFG_DEV0_EPF0_VF9_1_LINK_CAP 0xfffe10309070 #define cfgBIF_CFG_DEV0_EPF0_VF9_1_LINK_CNTL 0xfffe10309074 #define cfgBIF_CFG_DEV0_EPF0_VF9_1_LINK_STATUS 0xfffe10309076 #define cfgBIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CAP2 0xfffe10309088 #define cfgBIF_CFG_DEV0_EPF0_VF9_1_DEVICE_CNTL2 0xfffe1030908c #define cfgBIF_CFG_DEV0_EPF0_VF9_1_DEVICE_STATUS2 0xfffe1030908e #define cfgBIF_CFG_DEV0_EPF0_VF9_1_LINK_CAP2 0xfffe10309090 #define cfgBIF_CFG_DEV0_EPF0_VF9_1_LINK_CNTL2 0xfffe10309094 #define cfgBIF_CFG_DEV0_EPF0_VF9_1_LINK_STATUS2 0xfffe10309096 #define cfgBIF_CFG_DEV0_EPF0_VF9_1_MSI_CAP_LIST 0xfffe103090a0 #define cfgBIF_CFG_DEV0_EPF0_VF9_1_MSI_MSG_CNTL 0xfffe103090a2 #define cfgBIF_CFG_DEV0_EPF0_VF9_1_MSI_MSG_ADDR_LO 0xfffe103090a4 #define cfgBIF_CFG_DEV0_EPF0_VF9_1_MSI_MSG_ADDR_HI 0xfffe103090a8 #define cfgBIF_CFG_DEV0_EPF0_VF9_1_MSI_MSG_DATA 0xfffe103090a8 #define cfgBIF_CFG_DEV0_EPF0_VF9_1_MSI_MASK 0xfffe103090ac #define cfgBIF_CFG_DEV0_EPF0_VF9_1_MSI_MSG_DATA_64 0xfffe103090ac #define cfgBIF_CFG_DEV0_EPF0_VF9_1_MSI_MASK_64 0xfffe103090b0 #define cfgBIF_CFG_DEV0_EPF0_VF9_1_MSI_PENDING 0xfffe103090b0 #define cfgBIF_CFG_DEV0_EPF0_VF9_1_MSI_PENDING_64 0xfffe103090b4 #define cfgBIF_CFG_DEV0_EPF0_VF9_1_MSIX_CAP_LIST 0xfffe103090c0 #define cfgBIF_CFG_DEV0_EPF0_VF9_1_MSIX_MSG_CNTL 0xfffe103090c2 #define cfgBIF_CFG_DEV0_EPF0_VF9_1_MSIX_TABLE 0xfffe103090c4 #define cfgBIF_CFG_DEV0_EPF0_VF9_1_MSIX_PBA 0xfffe103090c8 #define cfgBIF_CFG_DEV0_EPF0_VF9_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0xfffe10309100 #define cfgBIF_CFG_DEV0_EPF0_VF9_1_PCIE_VENDOR_SPECIFIC_HDR 0xfffe10309104 #define cfgBIF_CFG_DEV0_EPF0_VF9_1_PCIE_VENDOR_SPECIFIC1 0xfffe10309108 #define cfgBIF_CFG_DEV0_EPF0_VF9_1_PCIE_VENDOR_SPECIFIC2 0xfffe1030910c #define cfgBIF_CFG_DEV0_EPF0_VF9_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0xfffe10309150 #define cfgBIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_STATUS 0xfffe10309154 #define cfgBIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_MASK 0xfffe10309158 #define cfgBIF_CFG_DEV0_EPF0_VF9_1_PCIE_UNCORR_ERR_SEVERITY 0xfffe1030915c #define cfgBIF_CFG_DEV0_EPF0_VF9_1_PCIE_CORR_ERR_STATUS 0xfffe10309160 #define cfgBIF_CFG_DEV0_EPF0_VF9_1_PCIE_CORR_ERR_MASK 0xfffe10309164 #define cfgBIF_CFG_DEV0_EPF0_VF9_1_PCIE_ADV_ERR_CAP_CNTL 0xfffe10309168 #define cfgBIF_CFG_DEV0_EPF0_VF9_1_PCIE_HDR_LOG0 0xfffe1030916c #define cfgBIF_CFG_DEV0_EPF0_VF9_1_PCIE_HDR_LOG1 0xfffe10309170 #define cfgBIF_CFG_DEV0_EPF0_VF9_1_PCIE_HDR_LOG2 0xfffe10309174 #define cfgBIF_CFG_DEV0_EPF0_VF9_1_PCIE_HDR_LOG3 0xfffe10309178 #define cfgBIF_CFG_DEV0_EPF0_VF9_1_PCIE_TLP_PREFIX_LOG0 0xfffe10309188 #define cfgBIF_CFG_DEV0_EPF0_VF9_1_PCIE_TLP_PREFIX_LOG1 0xfffe1030918c #define cfgBIF_CFG_DEV0_EPF0_VF9_1_PCIE_TLP_PREFIX_LOG2 0xfffe10309190 #define cfgBIF_CFG_DEV0_EPF0_VF9_1_PCIE_TLP_PREFIX_LOG3 0xfffe10309194 #define cfgBIF_CFG_DEV0_EPF0_VF9_1_PCIE_ATS_ENH_CAP_LIST 0xfffe103092b0 #define cfgBIF_CFG_DEV0_EPF0_VF9_1_PCIE_ATS_CAP 0xfffe103092b4 #define cfgBIF_CFG_DEV0_EPF0_VF9_1_PCIE_ATS_CNTL 0xfffe103092b6 #define cfgBIF_CFG_DEV0_EPF0_VF9_1_PCIE_ARI_ENH_CAP_LIST 0xfffe10309328 #define cfgBIF_CFG_DEV0_EPF0_VF9_1_PCIE_ARI_CAP 0xfffe1030932c #define cfgBIF_CFG_DEV0_EPF0_VF9_1_PCIE_ARI_CNTL 0xfffe1030932e // addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf10_bifcfgdecp // base address: 0xfffe1030a000 #define cfgBIF_CFG_DEV0_EPF0_VF10_1_VENDOR_ID 0xfffe1030a000 #define cfgBIF_CFG_DEV0_EPF0_VF10_1_DEVICE_ID 0xfffe1030a002 #define cfgBIF_CFG_DEV0_EPF0_VF10_1_COMMAND 0xfffe1030a004 #define cfgBIF_CFG_DEV0_EPF0_VF10_1_STATUS 0xfffe1030a006 #define cfgBIF_CFG_DEV0_EPF0_VF10_1_REVISION_ID 0xfffe1030a008 #define cfgBIF_CFG_DEV0_EPF0_VF10_1_PROG_INTERFACE 0xfffe1030a009 #define cfgBIF_CFG_DEV0_EPF0_VF10_1_SUB_CLASS 0xfffe1030a00a #define cfgBIF_CFG_DEV0_EPF0_VF10_1_BASE_CLASS 0xfffe1030a00b #define cfgBIF_CFG_DEV0_EPF0_VF10_1_CACHE_LINE 0xfffe1030a00c #define cfgBIF_CFG_DEV0_EPF0_VF10_1_LATENCY 0xfffe1030a00d #define cfgBIF_CFG_DEV0_EPF0_VF10_1_HEADER 0xfffe1030a00e #define cfgBIF_CFG_DEV0_EPF0_VF10_1_BIST 0xfffe1030a00f #define cfgBIF_CFG_DEV0_EPF0_VF10_1_BASE_ADDR_1 0xfffe1030a010 #define cfgBIF_CFG_DEV0_EPF0_VF10_1_BASE_ADDR_2 0xfffe1030a014 #define cfgBIF_CFG_DEV0_EPF0_VF10_1_BASE_ADDR_3 0xfffe1030a018 #define cfgBIF_CFG_DEV0_EPF0_VF10_1_BASE_ADDR_4 0xfffe1030a01c #define cfgBIF_CFG_DEV0_EPF0_VF10_1_BASE_ADDR_5 0xfffe1030a020 #define cfgBIF_CFG_DEV0_EPF0_VF10_1_BASE_ADDR_6 0xfffe1030a024 #define cfgBIF_CFG_DEV0_EPF0_VF10_1_CARDBUS_CIS_PTR 0xfffe1030a028 #define cfgBIF_CFG_DEV0_EPF0_VF10_1_ADAPTER_ID 0xfffe1030a02c #define cfgBIF_CFG_DEV0_EPF0_VF10_1_ROM_BASE_ADDR 0xfffe1030a030 #define cfgBIF_CFG_DEV0_EPF0_VF10_1_CAP_PTR 0xfffe1030a034 #define cfgBIF_CFG_DEV0_EPF0_VF10_1_INTERRUPT_LINE 0xfffe1030a03c #define cfgBIF_CFG_DEV0_EPF0_VF10_1_INTERRUPT_PIN 0xfffe1030a03d #define cfgBIF_CFG_DEV0_EPF0_VF10_1_MIN_GRANT 0xfffe1030a03e #define cfgBIF_CFG_DEV0_EPF0_VF10_1_MAX_LATENCY 0xfffe1030a03f #define cfgBIF_CFG_DEV0_EPF0_VF10_1_PCIE_CAP_LIST 0xfffe1030a064 #define cfgBIF_CFG_DEV0_EPF0_VF10_1_PCIE_CAP 0xfffe1030a066 #define cfgBIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CAP 0xfffe1030a068 #define cfgBIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CNTL 0xfffe1030a06c #define cfgBIF_CFG_DEV0_EPF0_VF10_1_DEVICE_STATUS 0xfffe1030a06e #define cfgBIF_CFG_DEV0_EPF0_VF10_1_LINK_CAP 0xfffe1030a070 #define cfgBIF_CFG_DEV0_EPF0_VF10_1_LINK_CNTL 0xfffe1030a074 #define cfgBIF_CFG_DEV0_EPF0_VF10_1_LINK_STATUS 0xfffe1030a076 #define cfgBIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CAP2 0xfffe1030a088 #define cfgBIF_CFG_DEV0_EPF0_VF10_1_DEVICE_CNTL2 0xfffe1030a08c #define cfgBIF_CFG_DEV0_EPF0_VF10_1_DEVICE_STATUS2 0xfffe1030a08e #define cfgBIF_CFG_DEV0_EPF0_VF10_1_LINK_CAP2 0xfffe1030a090 #define cfgBIF_CFG_DEV0_EPF0_VF10_1_LINK_CNTL2 0xfffe1030a094 #define cfgBIF_CFG_DEV0_EPF0_VF10_1_LINK_STATUS2 0xfffe1030a096 #define cfgBIF_CFG_DEV0_EPF0_VF10_1_MSI_CAP_LIST 0xfffe1030a0a0 #define cfgBIF_CFG_DEV0_EPF0_VF10_1_MSI_MSG_CNTL 0xfffe1030a0a2 #define cfgBIF_CFG_DEV0_EPF0_VF10_1_MSI_MSG_ADDR_LO 0xfffe1030a0a4 #define cfgBIF_CFG_DEV0_EPF0_VF10_1_MSI_MSG_ADDR_HI 0xfffe1030a0a8 #define cfgBIF_CFG_DEV0_EPF0_VF10_1_MSI_MSG_DATA 0xfffe1030a0a8 #define cfgBIF_CFG_DEV0_EPF0_VF10_1_MSI_MASK 0xfffe1030a0ac #define cfgBIF_CFG_DEV0_EPF0_VF10_1_MSI_MSG_DATA_64 0xfffe1030a0ac #define cfgBIF_CFG_DEV0_EPF0_VF10_1_MSI_MASK_64 0xfffe1030a0b0 #define cfgBIF_CFG_DEV0_EPF0_VF10_1_MSI_PENDING 0xfffe1030a0b0 #define cfgBIF_CFG_DEV0_EPF0_VF10_1_MSI_PENDING_64 0xfffe1030a0b4 #define cfgBIF_CFG_DEV0_EPF0_VF10_1_MSIX_CAP_LIST 0xfffe1030a0c0 #define cfgBIF_CFG_DEV0_EPF0_VF10_1_MSIX_MSG_CNTL 0xfffe1030a0c2 #define cfgBIF_CFG_DEV0_EPF0_VF10_1_MSIX_TABLE 0xfffe1030a0c4 #define cfgBIF_CFG_DEV0_EPF0_VF10_1_MSIX_PBA 0xfffe1030a0c8 #define cfgBIF_CFG_DEV0_EPF0_VF10_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0xfffe1030a100 #define cfgBIF_CFG_DEV0_EPF0_VF10_1_PCIE_VENDOR_SPECIFIC_HDR 0xfffe1030a104 #define cfgBIF_CFG_DEV0_EPF0_VF10_1_PCIE_VENDOR_SPECIFIC1 0xfffe1030a108 #define cfgBIF_CFG_DEV0_EPF0_VF10_1_PCIE_VENDOR_SPECIFIC2 0xfffe1030a10c #define cfgBIF_CFG_DEV0_EPF0_VF10_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0xfffe1030a150 #define cfgBIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_STATUS 0xfffe1030a154 #define cfgBIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_MASK 0xfffe1030a158 #define cfgBIF_CFG_DEV0_EPF0_VF10_1_PCIE_UNCORR_ERR_SEVERITY 0xfffe1030a15c #define cfgBIF_CFG_DEV0_EPF0_VF10_1_PCIE_CORR_ERR_STATUS 0xfffe1030a160 #define cfgBIF_CFG_DEV0_EPF0_VF10_1_PCIE_CORR_ERR_MASK 0xfffe1030a164 #define cfgBIF_CFG_DEV0_EPF0_VF10_1_PCIE_ADV_ERR_CAP_CNTL 0xfffe1030a168 #define cfgBIF_CFG_DEV0_EPF0_VF10_1_PCIE_HDR_LOG0 0xfffe1030a16c #define cfgBIF_CFG_DEV0_EPF0_VF10_1_PCIE_HDR_LOG1 0xfffe1030a170 #define cfgBIF_CFG_DEV0_EPF0_VF10_1_PCIE_HDR_LOG2 0xfffe1030a174 #define cfgBIF_CFG_DEV0_EPF0_VF10_1_PCIE_HDR_LOG3 0xfffe1030a178 #define cfgBIF_CFG_DEV0_EPF0_VF10_1_PCIE_TLP_PREFIX_LOG0 0xfffe1030a188 #define cfgBIF_CFG_DEV0_EPF0_VF10_1_PCIE_TLP_PREFIX_LOG1 0xfffe1030a18c #define cfgBIF_CFG_DEV0_EPF0_VF10_1_PCIE_TLP_PREFIX_LOG2 0xfffe1030a190 #define cfgBIF_CFG_DEV0_EPF0_VF10_1_PCIE_TLP_PREFIX_LOG3 0xfffe1030a194 #define cfgBIF_CFG_DEV0_EPF0_VF10_1_PCIE_ATS_ENH_CAP_LIST 0xfffe1030a2b0 #define cfgBIF_CFG_DEV0_EPF0_VF10_1_PCIE_ATS_CAP 0xfffe1030a2b4 #define cfgBIF_CFG_DEV0_EPF0_VF10_1_PCIE_ATS_CNTL 0xfffe1030a2b6 #define cfgBIF_CFG_DEV0_EPF0_VF10_1_PCIE_ARI_ENH_CAP_LIST 0xfffe1030a328 #define cfgBIF_CFG_DEV0_EPF0_VF10_1_PCIE_ARI_CAP 0xfffe1030a32c #define cfgBIF_CFG_DEV0_EPF0_VF10_1_PCIE_ARI_CNTL 0xfffe1030a32e // addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf11_bifcfgdecp // base address: 0xfffe1030b000 #define cfgBIF_CFG_DEV0_EPF0_VF11_1_VENDOR_ID 0xfffe1030b000 #define cfgBIF_CFG_DEV0_EPF0_VF11_1_DEVICE_ID 0xfffe1030b002 #define cfgBIF_CFG_DEV0_EPF0_VF11_1_COMMAND 0xfffe1030b004 #define cfgBIF_CFG_DEV0_EPF0_VF11_1_STATUS 0xfffe1030b006 #define cfgBIF_CFG_DEV0_EPF0_VF11_1_REVISION_ID 0xfffe1030b008 #define cfgBIF_CFG_DEV0_EPF0_VF11_1_PROG_INTERFACE 0xfffe1030b009 #define cfgBIF_CFG_DEV0_EPF0_VF11_1_SUB_CLASS 0xfffe1030b00a #define cfgBIF_CFG_DEV0_EPF0_VF11_1_BASE_CLASS 0xfffe1030b00b #define cfgBIF_CFG_DEV0_EPF0_VF11_1_CACHE_LINE 0xfffe1030b00c #define cfgBIF_CFG_DEV0_EPF0_VF11_1_LATENCY 0xfffe1030b00d #define cfgBIF_CFG_DEV0_EPF0_VF11_1_HEADER 0xfffe1030b00e #define cfgBIF_CFG_DEV0_EPF0_VF11_1_BIST 0xfffe1030b00f #define cfgBIF_CFG_DEV0_EPF0_VF11_1_BASE_ADDR_1 0xfffe1030b010 #define cfgBIF_CFG_DEV0_EPF0_VF11_1_BASE_ADDR_2 0xfffe1030b014 #define cfgBIF_CFG_DEV0_EPF0_VF11_1_BASE_ADDR_3 0xfffe1030b018 #define cfgBIF_CFG_DEV0_EPF0_VF11_1_BASE_ADDR_4 0xfffe1030b01c #define cfgBIF_CFG_DEV0_EPF0_VF11_1_BASE_ADDR_5 0xfffe1030b020 #define cfgBIF_CFG_DEV0_EPF0_VF11_1_BASE_ADDR_6 0xfffe1030b024 #define cfgBIF_CFG_DEV0_EPF0_VF11_1_CARDBUS_CIS_PTR 0xfffe1030b028 #define cfgBIF_CFG_DEV0_EPF0_VF11_1_ADAPTER_ID 0xfffe1030b02c #define cfgBIF_CFG_DEV0_EPF0_VF11_1_ROM_BASE_ADDR 0xfffe1030b030 #define cfgBIF_CFG_DEV0_EPF0_VF11_1_CAP_PTR 0xfffe1030b034 #define cfgBIF_CFG_DEV0_EPF0_VF11_1_INTERRUPT_LINE 0xfffe1030b03c #define cfgBIF_CFG_DEV0_EPF0_VF11_1_INTERRUPT_PIN 0xfffe1030b03d #define cfgBIF_CFG_DEV0_EPF0_VF11_1_MIN_GRANT 0xfffe1030b03e #define cfgBIF_CFG_DEV0_EPF0_VF11_1_MAX_LATENCY 0xfffe1030b03f #define cfgBIF_CFG_DEV0_EPF0_VF11_1_PCIE_CAP_LIST 0xfffe1030b064 #define cfgBIF_CFG_DEV0_EPF0_VF11_1_PCIE_CAP 0xfffe1030b066 #define cfgBIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CAP 0xfffe1030b068 #define cfgBIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CNTL 0xfffe1030b06c #define cfgBIF_CFG_DEV0_EPF0_VF11_1_DEVICE_STATUS 0xfffe1030b06e #define cfgBIF_CFG_DEV0_EPF0_VF11_1_LINK_CAP 0xfffe1030b070 #define cfgBIF_CFG_DEV0_EPF0_VF11_1_LINK_CNTL 0xfffe1030b074 #define cfgBIF_CFG_DEV0_EPF0_VF11_1_LINK_STATUS 0xfffe1030b076 #define cfgBIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CAP2 0xfffe1030b088 #define cfgBIF_CFG_DEV0_EPF0_VF11_1_DEVICE_CNTL2 0xfffe1030b08c #define cfgBIF_CFG_DEV0_EPF0_VF11_1_DEVICE_STATUS2 0xfffe1030b08e #define cfgBIF_CFG_DEV0_EPF0_VF11_1_LINK_CAP2 0xfffe1030b090 #define cfgBIF_CFG_DEV0_EPF0_VF11_1_LINK_CNTL2 0xfffe1030b094 #define cfgBIF_CFG_DEV0_EPF0_VF11_1_LINK_STATUS2 0xfffe1030b096 #define cfgBIF_CFG_DEV0_EPF0_VF11_1_MSI_CAP_LIST 0xfffe1030b0a0 #define cfgBIF_CFG_DEV0_EPF0_VF11_1_MSI_MSG_CNTL 0xfffe1030b0a2 #define cfgBIF_CFG_DEV0_EPF0_VF11_1_MSI_MSG_ADDR_LO 0xfffe1030b0a4 #define cfgBIF_CFG_DEV0_EPF0_VF11_1_MSI_MSG_ADDR_HI 0xfffe1030b0a8 #define cfgBIF_CFG_DEV0_EPF0_VF11_1_MSI_MSG_DATA 0xfffe1030b0a8 #define cfgBIF_CFG_DEV0_EPF0_VF11_1_MSI_MASK 0xfffe1030b0ac #define cfgBIF_CFG_DEV0_EPF0_VF11_1_MSI_MSG_DATA_64 0xfffe1030b0ac #define cfgBIF_CFG_DEV0_EPF0_VF11_1_MSI_MASK_64 0xfffe1030b0b0 #define cfgBIF_CFG_DEV0_EPF0_VF11_1_MSI_PENDING 0xfffe1030b0b0 #define cfgBIF_CFG_DEV0_EPF0_VF11_1_MSI_PENDING_64 0xfffe1030b0b4 #define cfgBIF_CFG_DEV0_EPF0_VF11_1_MSIX_CAP_LIST 0xfffe1030b0c0 #define cfgBIF_CFG_DEV0_EPF0_VF11_1_MSIX_MSG_CNTL 0xfffe1030b0c2 #define cfgBIF_CFG_DEV0_EPF0_VF11_1_MSIX_TABLE 0xfffe1030b0c4 #define cfgBIF_CFG_DEV0_EPF0_VF11_1_MSIX_PBA 0xfffe1030b0c8 #define cfgBIF_CFG_DEV0_EPF0_VF11_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0xfffe1030b100 #define cfgBIF_CFG_DEV0_EPF0_VF11_1_PCIE_VENDOR_SPECIFIC_HDR 0xfffe1030b104 #define cfgBIF_CFG_DEV0_EPF0_VF11_1_PCIE_VENDOR_SPECIFIC1 0xfffe1030b108 #define cfgBIF_CFG_DEV0_EPF0_VF11_1_PCIE_VENDOR_SPECIFIC2 0xfffe1030b10c #define cfgBIF_CFG_DEV0_EPF0_VF11_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0xfffe1030b150 #define cfgBIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_STATUS 0xfffe1030b154 #define cfgBIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_MASK 0xfffe1030b158 #define cfgBIF_CFG_DEV0_EPF0_VF11_1_PCIE_UNCORR_ERR_SEVERITY 0xfffe1030b15c #define cfgBIF_CFG_DEV0_EPF0_VF11_1_PCIE_CORR_ERR_STATUS 0xfffe1030b160 #define cfgBIF_CFG_DEV0_EPF0_VF11_1_PCIE_CORR_ERR_MASK 0xfffe1030b164 #define cfgBIF_CFG_DEV0_EPF0_VF11_1_PCIE_ADV_ERR_CAP_CNTL 0xfffe1030b168 #define cfgBIF_CFG_DEV0_EPF0_VF11_1_PCIE_HDR_LOG0 0xfffe1030b16c #define cfgBIF_CFG_DEV0_EPF0_VF11_1_PCIE_HDR_LOG1 0xfffe1030b170 #define cfgBIF_CFG_DEV0_EPF0_VF11_1_PCIE_HDR_LOG2 0xfffe1030b174 #define cfgBIF_CFG_DEV0_EPF0_VF11_1_PCIE_HDR_LOG3 0xfffe1030b178 #define cfgBIF_CFG_DEV0_EPF0_VF11_1_PCIE_TLP_PREFIX_LOG0 0xfffe1030b188 #define cfgBIF_CFG_DEV0_EPF0_VF11_1_PCIE_TLP_PREFIX_LOG1 0xfffe1030b18c #define cfgBIF_CFG_DEV0_EPF0_VF11_1_PCIE_TLP_PREFIX_LOG2 0xfffe1030b190 #define cfgBIF_CFG_DEV0_EPF0_VF11_1_PCIE_TLP_PREFIX_LOG3 0xfffe1030b194 #define cfgBIF_CFG_DEV0_EPF0_VF11_1_PCIE_ATS_ENH_CAP_LIST 0xfffe1030b2b0 #define cfgBIF_CFG_DEV0_EPF0_VF11_1_PCIE_ATS_CAP 0xfffe1030b2b4 #define cfgBIF_CFG_DEV0_EPF0_VF11_1_PCIE_ATS_CNTL 0xfffe1030b2b6 #define cfgBIF_CFG_DEV0_EPF0_VF11_1_PCIE_ARI_ENH_CAP_LIST 0xfffe1030b328 #define cfgBIF_CFG_DEV0_EPF0_VF11_1_PCIE_ARI_CAP 0xfffe1030b32c #define cfgBIF_CFG_DEV0_EPF0_VF11_1_PCIE_ARI_CNTL 0xfffe1030b32e // addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf12_bifcfgdecp // base address: 0xfffe1030c000 #define cfgBIF_CFG_DEV0_EPF0_VF12_1_VENDOR_ID 0xfffe1030c000 #define cfgBIF_CFG_DEV0_EPF0_VF12_1_DEVICE_ID 0xfffe1030c002 #define cfgBIF_CFG_DEV0_EPF0_VF12_1_COMMAND 0xfffe1030c004 #define cfgBIF_CFG_DEV0_EPF0_VF12_1_STATUS 0xfffe1030c006 #define cfgBIF_CFG_DEV0_EPF0_VF12_1_REVISION_ID 0xfffe1030c008 #define cfgBIF_CFG_DEV0_EPF0_VF12_1_PROG_INTERFACE 0xfffe1030c009 #define cfgBIF_CFG_DEV0_EPF0_VF12_1_SUB_CLASS 0xfffe1030c00a #define cfgBIF_CFG_DEV0_EPF0_VF12_1_BASE_CLASS 0xfffe1030c00b #define cfgBIF_CFG_DEV0_EPF0_VF12_1_CACHE_LINE 0xfffe1030c00c #define cfgBIF_CFG_DEV0_EPF0_VF12_1_LATENCY 0xfffe1030c00d #define cfgBIF_CFG_DEV0_EPF0_VF12_1_HEADER 0xfffe1030c00e #define cfgBIF_CFG_DEV0_EPF0_VF12_1_BIST 0xfffe1030c00f #define cfgBIF_CFG_DEV0_EPF0_VF12_1_BASE_ADDR_1 0xfffe1030c010 #define cfgBIF_CFG_DEV0_EPF0_VF12_1_BASE_ADDR_2 0xfffe1030c014 #define cfgBIF_CFG_DEV0_EPF0_VF12_1_BASE_ADDR_3 0xfffe1030c018 #define cfgBIF_CFG_DEV0_EPF0_VF12_1_BASE_ADDR_4 0xfffe1030c01c #define cfgBIF_CFG_DEV0_EPF0_VF12_1_BASE_ADDR_5 0xfffe1030c020 #define cfgBIF_CFG_DEV0_EPF0_VF12_1_BASE_ADDR_6 0xfffe1030c024 #define cfgBIF_CFG_DEV0_EPF0_VF12_1_CARDBUS_CIS_PTR 0xfffe1030c028 #define cfgBIF_CFG_DEV0_EPF0_VF12_1_ADAPTER_ID 0xfffe1030c02c #define cfgBIF_CFG_DEV0_EPF0_VF12_1_ROM_BASE_ADDR 0xfffe1030c030 #define cfgBIF_CFG_DEV0_EPF0_VF12_1_CAP_PTR 0xfffe1030c034 #define cfgBIF_CFG_DEV0_EPF0_VF12_1_INTERRUPT_LINE 0xfffe1030c03c #define cfgBIF_CFG_DEV0_EPF0_VF12_1_INTERRUPT_PIN 0xfffe1030c03d #define cfgBIF_CFG_DEV0_EPF0_VF12_1_MIN_GRANT 0xfffe1030c03e #define cfgBIF_CFG_DEV0_EPF0_VF12_1_MAX_LATENCY 0xfffe1030c03f #define cfgBIF_CFG_DEV0_EPF0_VF12_1_PCIE_CAP_LIST 0xfffe1030c064 #define cfgBIF_CFG_DEV0_EPF0_VF12_1_PCIE_CAP 0xfffe1030c066 #define cfgBIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CAP 0xfffe1030c068 #define cfgBIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CNTL 0xfffe1030c06c #define cfgBIF_CFG_DEV0_EPF0_VF12_1_DEVICE_STATUS 0xfffe1030c06e #define cfgBIF_CFG_DEV0_EPF0_VF12_1_LINK_CAP 0xfffe1030c070 #define cfgBIF_CFG_DEV0_EPF0_VF12_1_LINK_CNTL 0xfffe1030c074 #define cfgBIF_CFG_DEV0_EPF0_VF12_1_LINK_STATUS 0xfffe1030c076 #define cfgBIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CAP2 0xfffe1030c088 #define cfgBIF_CFG_DEV0_EPF0_VF12_1_DEVICE_CNTL2 0xfffe1030c08c #define cfgBIF_CFG_DEV0_EPF0_VF12_1_DEVICE_STATUS2 0xfffe1030c08e #define cfgBIF_CFG_DEV0_EPF0_VF12_1_LINK_CAP2 0xfffe1030c090 #define cfgBIF_CFG_DEV0_EPF0_VF12_1_LINK_CNTL2 0xfffe1030c094 #define cfgBIF_CFG_DEV0_EPF0_VF12_1_LINK_STATUS2 0xfffe1030c096 #define cfgBIF_CFG_DEV0_EPF0_VF12_1_MSI_CAP_LIST 0xfffe1030c0a0 #define cfgBIF_CFG_DEV0_EPF0_VF12_1_MSI_MSG_CNTL 0xfffe1030c0a2 #define cfgBIF_CFG_DEV0_EPF0_VF12_1_MSI_MSG_ADDR_LO 0xfffe1030c0a4 #define cfgBIF_CFG_DEV0_EPF0_VF12_1_MSI_MSG_ADDR_HI 0xfffe1030c0a8 #define cfgBIF_CFG_DEV0_EPF0_VF12_1_MSI_MSG_DATA 0xfffe1030c0a8 #define cfgBIF_CFG_DEV0_EPF0_VF12_1_MSI_MASK 0xfffe1030c0ac #define cfgBIF_CFG_DEV0_EPF0_VF12_1_MSI_MSG_DATA_64 0xfffe1030c0ac #define cfgBIF_CFG_DEV0_EPF0_VF12_1_MSI_MASK_64 0xfffe1030c0b0 #define cfgBIF_CFG_DEV0_EPF0_VF12_1_MSI_PENDING 0xfffe1030c0b0 #define cfgBIF_CFG_DEV0_EPF0_VF12_1_MSI_PENDING_64 0xfffe1030c0b4 #define cfgBIF_CFG_DEV0_EPF0_VF12_1_MSIX_CAP_LIST 0xfffe1030c0c0 #define cfgBIF_CFG_DEV0_EPF0_VF12_1_MSIX_MSG_CNTL 0xfffe1030c0c2 #define cfgBIF_CFG_DEV0_EPF0_VF12_1_MSIX_TABLE 0xfffe1030c0c4 #define cfgBIF_CFG_DEV0_EPF0_VF12_1_MSIX_PBA 0xfffe1030c0c8 #define cfgBIF_CFG_DEV0_EPF0_VF12_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0xfffe1030c100 #define cfgBIF_CFG_DEV0_EPF0_VF12_1_PCIE_VENDOR_SPECIFIC_HDR 0xfffe1030c104 #define cfgBIF_CFG_DEV0_EPF0_VF12_1_PCIE_VENDOR_SPECIFIC1 0xfffe1030c108 #define cfgBIF_CFG_DEV0_EPF0_VF12_1_PCIE_VENDOR_SPECIFIC2 0xfffe1030c10c #define cfgBIF_CFG_DEV0_EPF0_VF12_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0xfffe1030c150 #define cfgBIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_STATUS 0xfffe1030c154 #define cfgBIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_MASK 0xfffe1030c158 #define cfgBIF_CFG_DEV0_EPF0_VF12_1_PCIE_UNCORR_ERR_SEVERITY 0xfffe1030c15c #define cfgBIF_CFG_DEV0_EPF0_VF12_1_PCIE_CORR_ERR_STATUS 0xfffe1030c160 #define cfgBIF_CFG_DEV0_EPF0_VF12_1_PCIE_CORR_ERR_MASK 0xfffe1030c164 #define cfgBIF_CFG_DEV0_EPF0_VF12_1_PCIE_ADV_ERR_CAP_CNTL 0xfffe1030c168 #define cfgBIF_CFG_DEV0_EPF0_VF12_1_PCIE_HDR_LOG0 0xfffe1030c16c #define cfgBIF_CFG_DEV0_EPF0_VF12_1_PCIE_HDR_LOG1 0xfffe1030c170 #define cfgBIF_CFG_DEV0_EPF0_VF12_1_PCIE_HDR_LOG2 0xfffe1030c174 #define cfgBIF_CFG_DEV0_EPF0_VF12_1_PCIE_HDR_LOG3 0xfffe1030c178 #define cfgBIF_CFG_DEV0_EPF0_VF12_1_PCIE_TLP_PREFIX_LOG0 0xfffe1030c188 #define cfgBIF_CFG_DEV0_EPF0_VF12_1_PCIE_TLP_PREFIX_LOG1 0xfffe1030c18c #define cfgBIF_CFG_DEV0_EPF0_VF12_1_PCIE_TLP_PREFIX_LOG2 0xfffe1030c190 #define cfgBIF_CFG_DEV0_EPF0_VF12_1_PCIE_TLP_PREFIX_LOG3 0xfffe1030c194 #define cfgBIF_CFG_DEV0_EPF0_VF12_1_PCIE_ATS_ENH_CAP_LIST 0xfffe1030c2b0 #define cfgBIF_CFG_DEV0_EPF0_VF12_1_PCIE_ATS_CAP 0xfffe1030c2b4 #define cfgBIF_CFG_DEV0_EPF0_VF12_1_PCIE_ATS_CNTL 0xfffe1030c2b6 #define cfgBIF_CFG_DEV0_EPF0_VF12_1_PCIE_ARI_ENH_CAP_LIST 0xfffe1030c328 #define cfgBIF_CFG_DEV0_EPF0_VF12_1_PCIE_ARI_CAP 0xfffe1030c32c #define cfgBIF_CFG_DEV0_EPF0_VF12_1_PCIE_ARI_CNTL 0xfffe1030c32e // addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf13_bifcfgdecp // base address: 0xfffe1030d000 #define cfgBIF_CFG_DEV0_EPF0_VF13_1_VENDOR_ID 0xfffe1030d000 #define cfgBIF_CFG_DEV0_EPF0_VF13_1_DEVICE_ID 0xfffe1030d002 #define cfgBIF_CFG_DEV0_EPF0_VF13_1_COMMAND 0xfffe1030d004 #define cfgBIF_CFG_DEV0_EPF0_VF13_1_STATUS 0xfffe1030d006 #define cfgBIF_CFG_DEV0_EPF0_VF13_1_REVISION_ID 0xfffe1030d008 #define cfgBIF_CFG_DEV0_EPF0_VF13_1_PROG_INTERFACE 0xfffe1030d009 #define cfgBIF_CFG_DEV0_EPF0_VF13_1_SUB_CLASS 0xfffe1030d00a #define cfgBIF_CFG_DEV0_EPF0_VF13_1_BASE_CLASS 0xfffe1030d00b #define cfgBIF_CFG_DEV0_EPF0_VF13_1_CACHE_LINE 0xfffe1030d00c #define cfgBIF_CFG_DEV0_EPF0_VF13_1_LATENCY 0xfffe1030d00d #define cfgBIF_CFG_DEV0_EPF0_VF13_1_HEADER 0xfffe1030d00e #define cfgBIF_CFG_DEV0_EPF0_VF13_1_BIST 0xfffe1030d00f #define cfgBIF_CFG_DEV0_EPF0_VF13_1_BASE_ADDR_1 0xfffe1030d010 #define cfgBIF_CFG_DEV0_EPF0_VF13_1_BASE_ADDR_2 0xfffe1030d014 #define cfgBIF_CFG_DEV0_EPF0_VF13_1_BASE_ADDR_3 0xfffe1030d018 #define cfgBIF_CFG_DEV0_EPF0_VF13_1_BASE_ADDR_4 0xfffe1030d01c #define cfgBIF_CFG_DEV0_EPF0_VF13_1_BASE_ADDR_5 0xfffe1030d020 #define cfgBIF_CFG_DEV0_EPF0_VF13_1_BASE_ADDR_6 0xfffe1030d024 #define cfgBIF_CFG_DEV0_EPF0_VF13_1_CARDBUS_CIS_PTR 0xfffe1030d028 #define cfgBIF_CFG_DEV0_EPF0_VF13_1_ADAPTER_ID 0xfffe1030d02c #define cfgBIF_CFG_DEV0_EPF0_VF13_1_ROM_BASE_ADDR 0xfffe1030d030 #define cfgBIF_CFG_DEV0_EPF0_VF13_1_CAP_PTR 0xfffe1030d034 #define cfgBIF_CFG_DEV0_EPF0_VF13_1_INTERRUPT_LINE 0xfffe1030d03c #define cfgBIF_CFG_DEV0_EPF0_VF13_1_INTERRUPT_PIN 0xfffe1030d03d #define cfgBIF_CFG_DEV0_EPF0_VF13_1_MIN_GRANT 0xfffe1030d03e #define cfgBIF_CFG_DEV0_EPF0_VF13_1_MAX_LATENCY 0xfffe1030d03f #define cfgBIF_CFG_DEV0_EPF0_VF13_1_PCIE_CAP_LIST 0xfffe1030d064 #define cfgBIF_CFG_DEV0_EPF0_VF13_1_PCIE_CAP 0xfffe1030d066 #define cfgBIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CAP 0xfffe1030d068 #define cfgBIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CNTL 0xfffe1030d06c #define cfgBIF_CFG_DEV0_EPF0_VF13_1_DEVICE_STATUS 0xfffe1030d06e #define cfgBIF_CFG_DEV0_EPF0_VF13_1_LINK_CAP 0xfffe1030d070 #define cfgBIF_CFG_DEV0_EPF0_VF13_1_LINK_CNTL 0xfffe1030d074 #define cfgBIF_CFG_DEV0_EPF0_VF13_1_LINK_STATUS 0xfffe1030d076 #define cfgBIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CAP2 0xfffe1030d088 #define cfgBIF_CFG_DEV0_EPF0_VF13_1_DEVICE_CNTL2 0xfffe1030d08c #define cfgBIF_CFG_DEV0_EPF0_VF13_1_DEVICE_STATUS2 0xfffe1030d08e #define cfgBIF_CFG_DEV0_EPF0_VF13_1_LINK_CAP2 0xfffe1030d090 #define cfgBIF_CFG_DEV0_EPF0_VF13_1_LINK_CNTL2 0xfffe1030d094 #define cfgBIF_CFG_DEV0_EPF0_VF13_1_LINK_STATUS2 0xfffe1030d096 #define cfgBIF_CFG_DEV0_EPF0_VF13_1_MSI_CAP_LIST 0xfffe1030d0a0 #define cfgBIF_CFG_DEV0_EPF0_VF13_1_MSI_MSG_CNTL 0xfffe1030d0a2 #define cfgBIF_CFG_DEV0_EPF0_VF13_1_MSI_MSG_ADDR_LO 0xfffe1030d0a4 #define cfgBIF_CFG_DEV0_EPF0_VF13_1_MSI_MSG_ADDR_HI 0xfffe1030d0a8 #define cfgBIF_CFG_DEV0_EPF0_VF13_1_MSI_MSG_DATA 0xfffe1030d0a8 #define cfgBIF_CFG_DEV0_EPF0_VF13_1_MSI_MASK 0xfffe1030d0ac #define cfgBIF_CFG_DEV0_EPF0_VF13_1_MSI_MSG_DATA_64 0xfffe1030d0ac #define cfgBIF_CFG_DEV0_EPF0_VF13_1_MSI_MASK_64 0xfffe1030d0b0 #define cfgBIF_CFG_DEV0_EPF0_VF13_1_MSI_PENDING 0xfffe1030d0b0 #define cfgBIF_CFG_DEV0_EPF0_VF13_1_MSI_PENDING_64 0xfffe1030d0b4 #define cfgBIF_CFG_DEV0_EPF0_VF13_1_MSIX_CAP_LIST 0xfffe1030d0c0 #define cfgBIF_CFG_DEV0_EPF0_VF13_1_MSIX_MSG_CNTL 0xfffe1030d0c2 #define cfgBIF_CFG_DEV0_EPF0_VF13_1_MSIX_TABLE 0xfffe1030d0c4 #define cfgBIF_CFG_DEV0_EPF0_VF13_1_MSIX_PBA 0xfffe1030d0c8 #define cfgBIF_CFG_DEV0_EPF0_VF13_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0xfffe1030d100 #define cfgBIF_CFG_DEV0_EPF0_VF13_1_PCIE_VENDOR_SPECIFIC_HDR 0xfffe1030d104 #define cfgBIF_CFG_DEV0_EPF0_VF13_1_PCIE_VENDOR_SPECIFIC1 0xfffe1030d108 #define cfgBIF_CFG_DEV0_EPF0_VF13_1_PCIE_VENDOR_SPECIFIC2 0xfffe1030d10c #define cfgBIF_CFG_DEV0_EPF0_VF13_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0xfffe1030d150 #define cfgBIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_STATUS 0xfffe1030d154 #define cfgBIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_MASK 0xfffe1030d158 #define cfgBIF_CFG_DEV0_EPF0_VF13_1_PCIE_UNCORR_ERR_SEVERITY 0xfffe1030d15c #define cfgBIF_CFG_DEV0_EPF0_VF13_1_PCIE_CORR_ERR_STATUS 0xfffe1030d160 #define cfgBIF_CFG_DEV0_EPF0_VF13_1_PCIE_CORR_ERR_MASK 0xfffe1030d164 #define cfgBIF_CFG_DEV0_EPF0_VF13_1_PCIE_ADV_ERR_CAP_CNTL 0xfffe1030d168 #define cfgBIF_CFG_DEV0_EPF0_VF13_1_PCIE_HDR_LOG0 0xfffe1030d16c #define cfgBIF_CFG_DEV0_EPF0_VF13_1_PCIE_HDR_LOG1 0xfffe1030d170 #define cfgBIF_CFG_DEV0_EPF0_VF13_1_PCIE_HDR_LOG2 0xfffe1030d174 #define cfgBIF_CFG_DEV0_EPF0_VF13_1_PCIE_HDR_LOG3 0xfffe1030d178 #define cfgBIF_CFG_DEV0_EPF0_VF13_1_PCIE_TLP_PREFIX_LOG0 0xfffe1030d188 #define cfgBIF_CFG_DEV0_EPF0_VF13_1_PCIE_TLP_PREFIX_LOG1 0xfffe1030d18c #define cfgBIF_CFG_DEV0_EPF0_VF13_1_PCIE_TLP_PREFIX_LOG2 0xfffe1030d190 #define cfgBIF_CFG_DEV0_EPF0_VF13_1_PCIE_TLP_PREFIX_LOG3 0xfffe1030d194 #define cfgBIF_CFG_DEV0_EPF0_VF13_1_PCIE_ATS_ENH_CAP_LIST 0xfffe1030d2b0 #define cfgBIF_CFG_DEV0_EPF0_VF13_1_PCIE_ATS_CAP 0xfffe1030d2b4 #define cfgBIF_CFG_DEV0_EPF0_VF13_1_PCIE_ATS_CNTL 0xfffe1030d2b6 #define cfgBIF_CFG_DEV0_EPF0_VF13_1_PCIE_ARI_ENH_CAP_LIST 0xfffe1030d328 #define cfgBIF_CFG_DEV0_EPF0_VF13_1_PCIE_ARI_CAP 0xfffe1030d32c #define cfgBIF_CFG_DEV0_EPF0_VF13_1_PCIE_ARI_CNTL 0xfffe1030d32e // addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf14_bifcfgdecp // base address: 0xfffe1030e000 #define cfgBIF_CFG_DEV0_EPF0_VF14_1_VENDOR_ID 0xfffe1030e000 #define cfgBIF_CFG_DEV0_EPF0_VF14_1_DEVICE_ID 0xfffe1030e002 #define cfgBIF_CFG_DEV0_EPF0_VF14_1_COMMAND 0xfffe1030e004 #define cfgBIF_CFG_DEV0_EPF0_VF14_1_STATUS 0xfffe1030e006 #define cfgBIF_CFG_DEV0_EPF0_VF14_1_REVISION_ID 0xfffe1030e008 #define cfgBIF_CFG_DEV0_EPF0_VF14_1_PROG_INTERFACE 0xfffe1030e009 #define cfgBIF_CFG_DEV0_EPF0_VF14_1_SUB_CLASS 0xfffe1030e00a #define cfgBIF_CFG_DEV0_EPF0_VF14_1_BASE_CLASS 0xfffe1030e00b #define cfgBIF_CFG_DEV0_EPF0_VF14_1_CACHE_LINE 0xfffe1030e00c #define cfgBIF_CFG_DEV0_EPF0_VF14_1_LATENCY 0xfffe1030e00d #define cfgBIF_CFG_DEV0_EPF0_VF14_1_HEADER 0xfffe1030e00e #define cfgBIF_CFG_DEV0_EPF0_VF14_1_BIST 0xfffe1030e00f #define cfgBIF_CFG_DEV0_EPF0_VF14_1_BASE_ADDR_1 0xfffe1030e010 #define cfgBIF_CFG_DEV0_EPF0_VF14_1_BASE_ADDR_2 0xfffe1030e014 #define cfgBIF_CFG_DEV0_EPF0_VF14_1_BASE_ADDR_3 0xfffe1030e018 #define cfgBIF_CFG_DEV0_EPF0_VF14_1_BASE_ADDR_4 0xfffe1030e01c #define cfgBIF_CFG_DEV0_EPF0_VF14_1_BASE_ADDR_5 0xfffe1030e020 #define cfgBIF_CFG_DEV0_EPF0_VF14_1_BASE_ADDR_6 0xfffe1030e024 #define cfgBIF_CFG_DEV0_EPF0_VF14_1_CARDBUS_CIS_PTR 0xfffe1030e028 #define cfgBIF_CFG_DEV0_EPF0_VF14_1_ADAPTER_ID 0xfffe1030e02c #define cfgBIF_CFG_DEV0_EPF0_VF14_1_ROM_BASE_ADDR 0xfffe1030e030 #define cfgBIF_CFG_DEV0_EPF0_VF14_1_CAP_PTR 0xfffe1030e034 #define cfgBIF_CFG_DEV0_EPF0_VF14_1_INTERRUPT_LINE 0xfffe1030e03c #define cfgBIF_CFG_DEV0_EPF0_VF14_1_INTERRUPT_PIN 0xfffe1030e03d #define cfgBIF_CFG_DEV0_EPF0_VF14_1_MIN_GRANT 0xfffe1030e03e #define cfgBIF_CFG_DEV0_EPF0_VF14_1_MAX_LATENCY 0xfffe1030e03f #define cfgBIF_CFG_DEV0_EPF0_VF14_1_PCIE_CAP_LIST 0xfffe1030e064 #define cfgBIF_CFG_DEV0_EPF0_VF14_1_PCIE_CAP 0xfffe1030e066 #define cfgBIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CAP 0xfffe1030e068 #define cfgBIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CNTL 0xfffe1030e06c #define cfgBIF_CFG_DEV0_EPF0_VF14_1_DEVICE_STATUS 0xfffe1030e06e #define cfgBIF_CFG_DEV0_EPF0_VF14_1_LINK_CAP 0xfffe1030e070 #define cfgBIF_CFG_DEV0_EPF0_VF14_1_LINK_CNTL 0xfffe1030e074 #define cfgBIF_CFG_DEV0_EPF0_VF14_1_LINK_STATUS 0xfffe1030e076 #define cfgBIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CAP2 0xfffe1030e088 #define cfgBIF_CFG_DEV0_EPF0_VF14_1_DEVICE_CNTL2 0xfffe1030e08c #define cfgBIF_CFG_DEV0_EPF0_VF14_1_DEVICE_STATUS2 0xfffe1030e08e #define cfgBIF_CFG_DEV0_EPF0_VF14_1_LINK_CAP2 0xfffe1030e090 #define cfgBIF_CFG_DEV0_EPF0_VF14_1_LINK_CNTL2 0xfffe1030e094 #define cfgBIF_CFG_DEV0_EPF0_VF14_1_LINK_STATUS2 0xfffe1030e096 #define cfgBIF_CFG_DEV0_EPF0_VF14_1_MSI_CAP_LIST 0xfffe1030e0a0 #define cfgBIF_CFG_DEV0_EPF0_VF14_1_MSI_MSG_CNTL 0xfffe1030e0a2 #define cfgBIF_CFG_DEV0_EPF0_VF14_1_MSI_MSG_ADDR_LO 0xfffe1030e0a4 #define cfgBIF_CFG_DEV0_EPF0_VF14_1_MSI_MSG_ADDR_HI 0xfffe1030e0a8 #define cfgBIF_CFG_DEV0_EPF0_VF14_1_MSI_MSG_DATA 0xfffe1030e0a8 #define cfgBIF_CFG_DEV0_EPF0_VF14_1_MSI_MASK 0xfffe1030e0ac #define cfgBIF_CFG_DEV0_EPF0_VF14_1_MSI_MSG_DATA_64 0xfffe1030e0ac #define cfgBIF_CFG_DEV0_EPF0_VF14_1_MSI_MASK_64 0xfffe1030e0b0 #define cfgBIF_CFG_DEV0_EPF0_VF14_1_MSI_PENDING 0xfffe1030e0b0 #define cfgBIF_CFG_DEV0_EPF0_VF14_1_MSI_PENDING_64 0xfffe1030e0b4 #define cfgBIF_CFG_DEV0_EPF0_VF14_1_MSIX_CAP_LIST 0xfffe1030e0c0 #define cfgBIF_CFG_DEV0_EPF0_VF14_1_MSIX_MSG_CNTL 0xfffe1030e0c2 #define cfgBIF_CFG_DEV0_EPF0_VF14_1_MSIX_TABLE 0xfffe1030e0c4 #define cfgBIF_CFG_DEV0_EPF0_VF14_1_MSIX_PBA 0xfffe1030e0c8 #define cfgBIF_CFG_DEV0_EPF0_VF14_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0xfffe1030e100 #define cfgBIF_CFG_DEV0_EPF0_VF14_1_PCIE_VENDOR_SPECIFIC_HDR 0xfffe1030e104 #define cfgBIF_CFG_DEV0_EPF0_VF14_1_PCIE_VENDOR_SPECIFIC1 0xfffe1030e108 #define cfgBIF_CFG_DEV0_EPF0_VF14_1_PCIE_VENDOR_SPECIFIC2 0xfffe1030e10c #define cfgBIF_CFG_DEV0_EPF0_VF14_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0xfffe1030e150 #define cfgBIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_STATUS 0xfffe1030e154 #define cfgBIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_MASK 0xfffe1030e158 #define cfgBIF_CFG_DEV0_EPF0_VF14_1_PCIE_UNCORR_ERR_SEVERITY 0xfffe1030e15c #define cfgBIF_CFG_DEV0_EPF0_VF14_1_PCIE_CORR_ERR_STATUS 0xfffe1030e160 #define cfgBIF_CFG_DEV0_EPF0_VF14_1_PCIE_CORR_ERR_MASK 0xfffe1030e164 #define cfgBIF_CFG_DEV0_EPF0_VF14_1_PCIE_ADV_ERR_CAP_CNTL 0xfffe1030e168 #define cfgBIF_CFG_DEV0_EPF0_VF14_1_PCIE_HDR_LOG0 0xfffe1030e16c #define cfgBIF_CFG_DEV0_EPF0_VF14_1_PCIE_HDR_LOG1 0xfffe1030e170 #define cfgBIF_CFG_DEV0_EPF0_VF14_1_PCIE_HDR_LOG2 0xfffe1030e174 #define cfgBIF_CFG_DEV0_EPF0_VF14_1_PCIE_HDR_LOG3 0xfffe1030e178 #define cfgBIF_CFG_DEV0_EPF0_VF14_1_PCIE_TLP_PREFIX_LOG0 0xfffe1030e188 #define cfgBIF_CFG_DEV0_EPF0_VF14_1_PCIE_TLP_PREFIX_LOG1 0xfffe1030e18c #define cfgBIF_CFG_DEV0_EPF0_VF14_1_PCIE_TLP_PREFIX_LOG2 0xfffe1030e190 #define cfgBIF_CFG_DEV0_EPF0_VF14_1_PCIE_TLP_PREFIX_LOG3 0xfffe1030e194 #define cfgBIF_CFG_DEV0_EPF0_VF14_1_PCIE_ATS_ENH_CAP_LIST 0xfffe1030e2b0 #define cfgBIF_CFG_DEV0_EPF0_VF14_1_PCIE_ATS_CAP 0xfffe1030e2b4 #define cfgBIF_CFG_DEV0_EPF0_VF14_1_PCIE_ATS_CNTL 0xfffe1030e2b6 #define cfgBIF_CFG_DEV0_EPF0_VF14_1_PCIE_ARI_ENH_CAP_LIST 0xfffe1030e328 #define cfgBIF_CFG_DEV0_EPF0_VF14_1_PCIE_ARI_CAP 0xfffe1030e32c #define cfgBIF_CFG_DEV0_EPF0_VF14_1_PCIE_ARI_CNTL 0xfffe1030e32e // addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf15_bifcfgdecp // base address: 0xfffe1030f000 #define cfgBIF_CFG_DEV0_EPF0_VF15_1_VENDOR_ID 0xfffe1030f000 #define cfgBIF_CFG_DEV0_EPF0_VF15_1_DEVICE_ID 0xfffe1030f002 #define cfgBIF_CFG_DEV0_EPF0_VF15_1_COMMAND 0xfffe1030f004 #define cfgBIF_CFG_DEV0_EPF0_VF15_1_STATUS 0xfffe1030f006 #define cfgBIF_CFG_DEV0_EPF0_VF15_1_REVISION_ID 0xfffe1030f008 #define cfgBIF_CFG_DEV0_EPF0_VF15_1_PROG_INTERFACE 0xfffe1030f009 #define cfgBIF_CFG_DEV0_EPF0_VF15_1_SUB_CLASS 0xfffe1030f00a #define cfgBIF_CFG_DEV0_EPF0_VF15_1_BASE_CLASS 0xfffe1030f00b #define cfgBIF_CFG_DEV0_EPF0_VF15_1_CACHE_LINE 0xfffe1030f00c #define cfgBIF_CFG_DEV0_EPF0_VF15_1_LATENCY 0xfffe1030f00d #define cfgBIF_CFG_DEV0_EPF0_VF15_1_HEADER 0xfffe1030f00e #define cfgBIF_CFG_DEV0_EPF0_VF15_1_BIST 0xfffe1030f00f #define cfgBIF_CFG_DEV0_EPF0_VF15_1_BASE_ADDR_1 0xfffe1030f010 #define cfgBIF_CFG_DEV0_EPF0_VF15_1_BASE_ADDR_2 0xfffe1030f014 #define cfgBIF_CFG_DEV0_EPF0_VF15_1_BASE_ADDR_3 0xfffe1030f018 #define cfgBIF_CFG_DEV0_EPF0_VF15_1_BASE_ADDR_4 0xfffe1030f01c #define cfgBIF_CFG_DEV0_EPF0_VF15_1_BASE_ADDR_5 0xfffe1030f020 #define cfgBIF_CFG_DEV0_EPF0_VF15_1_BASE_ADDR_6 0xfffe1030f024 #define cfgBIF_CFG_DEV0_EPF0_VF15_1_CARDBUS_CIS_PTR 0xfffe1030f028 #define cfgBIF_CFG_DEV0_EPF0_VF15_1_ADAPTER_ID 0xfffe1030f02c #define cfgBIF_CFG_DEV0_EPF0_VF15_1_ROM_BASE_ADDR 0xfffe1030f030 #define cfgBIF_CFG_DEV0_EPF0_VF15_1_CAP_PTR 0xfffe1030f034 #define cfgBIF_CFG_DEV0_EPF0_VF15_1_INTERRUPT_LINE 0xfffe1030f03c #define cfgBIF_CFG_DEV0_EPF0_VF15_1_INTERRUPT_PIN 0xfffe1030f03d #define cfgBIF_CFG_DEV0_EPF0_VF15_1_MIN_GRANT 0xfffe1030f03e #define cfgBIF_CFG_DEV0_EPF0_VF15_1_MAX_LATENCY 0xfffe1030f03f #define cfgBIF_CFG_DEV0_EPF0_VF15_1_PCIE_CAP_LIST 0xfffe1030f064 #define cfgBIF_CFG_DEV0_EPF0_VF15_1_PCIE_CAP 0xfffe1030f066 #define cfgBIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CAP 0xfffe1030f068 #define cfgBIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CNTL 0xfffe1030f06c #define cfgBIF_CFG_DEV0_EPF0_VF15_1_DEVICE_STATUS 0xfffe1030f06e #define cfgBIF_CFG_DEV0_EPF0_VF15_1_LINK_CAP 0xfffe1030f070 #define cfgBIF_CFG_DEV0_EPF0_VF15_1_LINK_CNTL 0xfffe1030f074 #define cfgBIF_CFG_DEV0_EPF0_VF15_1_LINK_STATUS 0xfffe1030f076 #define cfgBIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CAP2 0xfffe1030f088 #define cfgBIF_CFG_DEV0_EPF0_VF15_1_DEVICE_CNTL2 0xfffe1030f08c #define cfgBIF_CFG_DEV0_EPF0_VF15_1_DEVICE_STATUS2 0xfffe1030f08e #define cfgBIF_CFG_DEV0_EPF0_VF15_1_LINK_CAP2 0xfffe1030f090 #define cfgBIF_CFG_DEV0_EPF0_VF15_1_LINK_CNTL2 0xfffe1030f094 #define cfgBIF_CFG_DEV0_EPF0_VF15_1_LINK_STATUS2 0xfffe1030f096 #define cfgBIF_CFG_DEV0_EPF0_VF15_1_MSI_CAP_LIST 0xfffe1030f0a0 #define cfgBIF_CFG_DEV0_EPF0_VF15_1_MSI_MSG_CNTL 0xfffe1030f0a2 #define cfgBIF_CFG_DEV0_EPF0_VF15_1_MSI_MSG_ADDR_LO 0xfffe1030f0a4 #define cfgBIF_CFG_DEV0_EPF0_VF15_1_MSI_MSG_ADDR_HI 0xfffe1030f0a8 #define cfgBIF_CFG_DEV0_EPF0_VF15_1_MSI_MSG_DATA 0xfffe1030f0a8 #define cfgBIF_CFG_DEV0_EPF0_VF15_1_MSI_MASK 0xfffe1030f0ac #define cfgBIF_CFG_DEV0_EPF0_VF15_1_MSI_MSG_DATA_64 0xfffe1030f0ac #define cfgBIF_CFG_DEV0_EPF0_VF15_1_MSI_MASK_64 0xfffe1030f0b0 #define cfgBIF_CFG_DEV0_EPF0_VF15_1_MSI_PENDING 0xfffe1030f0b0 #define cfgBIF_CFG_DEV0_EPF0_VF15_1_MSI_PENDING_64 0xfffe1030f0b4 #define cfgBIF_CFG_DEV0_EPF0_VF15_1_MSIX_CAP_LIST 0xfffe1030f0c0 #define cfgBIF_CFG_DEV0_EPF0_VF15_1_MSIX_MSG_CNTL 0xfffe1030f0c2 #define cfgBIF_CFG_DEV0_EPF0_VF15_1_MSIX_TABLE 0xfffe1030f0c4 #define cfgBIF_CFG_DEV0_EPF0_VF15_1_MSIX_PBA 0xfffe1030f0c8 #define cfgBIF_CFG_DEV0_EPF0_VF15_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0xfffe1030f100 #define cfgBIF_CFG_DEV0_EPF0_VF15_1_PCIE_VENDOR_SPECIFIC_HDR 0xfffe1030f104 #define cfgBIF_CFG_DEV0_EPF0_VF15_1_PCIE_VENDOR_SPECIFIC1 0xfffe1030f108 #define cfgBIF_CFG_DEV0_EPF0_VF15_1_PCIE_VENDOR_SPECIFIC2 0xfffe1030f10c #define cfgBIF_CFG_DEV0_EPF0_VF15_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0xfffe1030f150 #define cfgBIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_STATUS 0xfffe1030f154 #define cfgBIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_MASK 0xfffe1030f158 #define cfgBIF_CFG_DEV0_EPF0_VF15_1_PCIE_UNCORR_ERR_SEVERITY 0xfffe1030f15c #define cfgBIF_CFG_DEV0_EPF0_VF15_1_PCIE_CORR_ERR_STATUS 0xfffe1030f160 #define cfgBIF_CFG_DEV0_EPF0_VF15_1_PCIE_CORR_ERR_MASK 0xfffe1030f164 #define cfgBIF_CFG_DEV0_EPF0_VF15_1_PCIE_ADV_ERR_CAP_CNTL 0xfffe1030f168 #define cfgBIF_CFG_DEV0_EPF0_VF15_1_PCIE_HDR_LOG0 0xfffe1030f16c #define cfgBIF_CFG_DEV0_EPF0_VF15_1_PCIE_HDR_LOG1 0xfffe1030f170 #define cfgBIF_CFG_DEV0_EPF0_VF15_1_PCIE_HDR_LOG2 0xfffe1030f174 #define cfgBIF_CFG_DEV0_EPF0_VF15_1_PCIE_HDR_LOG3 0xfffe1030f178 #define cfgBIF_CFG_DEV0_EPF0_VF15_1_PCIE_TLP_PREFIX_LOG0 0xfffe1030f188 #define cfgBIF_CFG_DEV0_EPF0_VF15_1_PCIE_TLP_PREFIX_LOG1 0xfffe1030f18c #define cfgBIF_CFG_DEV0_EPF0_VF15_1_PCIE_TLP_PREFIX_LOG2 0xfffe1030f190 #define cfgBIF_CFG_DEV0_EPF0_VF15_1_PCIE_TLP_PREFIX_LOG3 0xfffe1030f194 #define cfgBIF_CFG_DEV0_EPF0_VF15_1_PCIE_ATS_ENH_CAP_LIST 0xfffe1030f2b0 #define cfgBIF_CFG_DEV0_EPF0_VF15_1_PCIE_ATS_CAP 0xfffe1030f2b4 #define cfgBIF_CFG_DEV0_EPF0_VF15_1_PCIE_ATS_CNTL 0xfffe1030f2b6 #define cfgBIF_CFG_DEV0_EPF0_VF15_1_PCIE_ARI_ENH_CAP_LIST 0xfffe1030f328 #define cfgBIF_CFG_DEV0_EPF0_VF15_1_PCIE_ARI_CAP 0xfffe1030f32c #define cfgBIF_CFG_DEV0_EPF0_VF15_1_PCIE_ARI_CNTL 0xfffe1030f32e // addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf16_bifcfgdecp // base address: 0xfffe10310000 #define cfgBIF_CFG_DEV0_EPF0_VF16_1_VENDOR_ID 0xfffe10310000 #define cfgBIF_CFG_DEV0_EPF0_VF16_1_DEVICE_ID 0xfffe10310002 #define cfgBIF_CFG_DEV0_EPF0_VF16_1_COMMAND 0xfffe10310004 #define cfgBIF_CFG_DEV0_EPF0_VF16_1_STATUS 0xfffe10310006 #define cfgBIF_CFG_DEV0_EPF0_VF16_1_REVISION_ID 0xfffe10310008 #define cfgBIF_CFG_DEV0_EPF0_VF16_1_PROG_INTERFACE 0xfffe10310009 #define cfgBIF_CFG_DEV0_EPF0_VF16_1_SUB_CLASS 0xfffe1031000a #define cfgBIF_CFG_DEV0_EPF0_VF16_1_BASE_CLASS 0xfffe1031000b #define cfgBIF_CFG_DEV0_EPF0_VF16_1_CACHE_LINE 0xfffe1031000c #define cfgBIF_CFG_DEV0_EPF0_VF16_1_LATENCY 0xfffe1031000d #define cfgBIF_CFG_DEV0_EPF0_VF16_1_HEADER 0xfffe1031000e #define cfgBIF_CFG_DEV0_EPF0_VF16_1_BIST 0xfffe1031000f #define cfgBIF_CFG_DEV0_EPF0_VF16_1_BASE_ADDR_1 0xfffe10310010 #define cfgBIF_CFG_DEV0_EPF0_VF16_1_BASE_ADDR_2 0xfffe10310014 #define cfgBIF_CFG_DEV0_EPF0_VF16_1_BASE_ADDR_3 0xfffe10310018 #define cfgBIF_CFG_DEV0_EPF0_VF16_1_BASE_ADDR_4 0xfffe1031001c #define cfgBIF_CFG_DEV0_EPF0_VF16_1_BASE_ADDR_5 0xfffe10310020 #define cfgBIF_CFG_DEV0_EPF0_VF16_1_BASE_ADDR_6 0xfffe10310024 #define cfgBIF_CFG_DEV0_EPF0_VF16_1_CARDBUS_CIS_PTR 0xfffe10310028 #define cfgBIF_CFG_DEV0_EPF0_VF16_1_ADAPTER_ID 0xfffe1031002c #define cfgBIF_CFG_DEV0_EPF0_VF16_1_ROM_BASE_ADDR 0xfffe10310030 #define cfgBIF_CFG_DEV0_EPF0_VF16_1_CAP_PTR 0xfffe10310034 #define cfgBIF_CFG_DEV0_EPF0_VF16_1_INTERRUPT_LINE 0xfffe1031003c #define cfgBIF_CFG_DEV0_EPF0_VF16_1_INTERRUPT_PIN 0xfffe1031003d #define cfgBIF_CFG_DEV0_EPF0_VF16_1_MIN_GRANT 0xfffe1031003e #define cfgBIF_CFG_DEV0_EPF0_VF16_1_MAX_LATENCY 0xfffe1031003f #define cfgBIF_CFG_DEV0_EPF0_VF16_1_PCIE_CAP_LIST 0xfffe10310064 #define cfgBIF_CFG_DEV0_EPF0_VF16_1_PCIE_CAP 0xfffe10310066 #define cfgBIF_CFG_DEV0_EPF0_VF16_1_DEVICE_CAP 0xfffe10310068 #define cfgBIF_CFG_DEV0_EPF0_VF16_1_DEVICE_CNTL 0xfffe1031006c #define cfgBIF_CFG_DEV0_EPF0_VF16_1_DEVICE_STATUS 0xfffe1031006e #define cfgBIF_CFG_DEV0_EPF0_VF16_1_LINK_CAP 0xfffe10310070 #define cfgBIF_CFG_DEV0_EPF0_VF16_1_LINK_CNTL 0xfffe10310074 #define cfgBIF_CFG_DEV0_EPF0_VF16_1_LINK_STATUS 0xfffe10310076 #define cfgBIF_CFG_DEV0_EPF0_VF16_1_DEVICE_CAP2 0xfffe10310088 #define cfgBIF_CFG_DEV0_EPF0_VF16_1_DEVICE_CNTL2 0xfffe1031008c #define cfgBIF_CFG_DEV0_EPF0_VF16_1_DEVICE_STATUS2 0xfffe1031008e #define cfgBIF_CFG_DEV0_EPF0_VF16_1_LINK_CAP2 0xfffe10310090 #define cfgBIF_CFG_DEV0_EPF0_VF16_1_LINK_CNTL2 0xfffe10310094 #define cfgBIF_CFG_DEV0_EPF0_VF16_1_LINK_STATUS2 0xfffe10310096 #define cfgBIF_CFG_DEV0_EPF0_VF16_1_MSI_CAP_LIST 0xfffe103100a0 #define cfgBIF_CFG_DEV0_EPF0_VF16_1_MSI_MSG_CNTL 0xfffe103100a2 #define cfgBIF_CFG_DEV0_EPF0_VF16_1_MSI_MSG_ADDR_LO 0xfffe103100a4 #define cfgBIF_CFG_DEV0_EPF0_VF16_1_MSI_MSG_ADDR_HI 0xfffe103100a8 #define cfgBIF_CFG_DEV0_EPF0_VF16_1_MSI_MSG_DATA 0xfffe103100a8 #define cfgBIF_CFG_DEV0_EPF0_VF16_1_MSI_MASK 0xfffe103100ac #define cfgBIF_CFG_DEV0_EPF0_VF16_1_MSI_MSG_DATA_64 0xfffe103100ac #define cfgBIF_CFG_DEV0_EPF0_VF16_1_MSI_MASK_64 0xfffe103100b0 #define cfgBIF_CFG_DEV0_EPF0_VF16_1_MSI_PENDING 0xfffe103100b0 #define cfgBIF_CFG_DEV0_EPF0_VF16_1_MSI_PENDING_64 0xfffe103100b4 #define cfgBIF_CFG_DEV0_EPF0_VF16_1_MSIX_CAP_LIST 0xfffe103100c0 #define cfgBIF_CFG_DEV0_EPF0_VF16_1_MSIX_MSG_CNTL 0xfffe103100c2 #define cfgBIF_CFG_DEV0_EPF0_VF16_1_MSIX_TABLE 0xfffe103100c4 #define cfgBIF_CFG_DEV0_EPF0_VF16_1_MSIX_PBA 0xfffe103100c8 #define cfgBIF_CFG_DEV0_EPF0_VF16_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0xfffe10310100 #define cfgBIF_CFG_DEV0_EPF0_VF16_1_PCIE_VENDOR_SPECIFIC_HDR 0xfffe10310104 #define cfgBIF_CFG_DEV0_EPF0_VF16_1_PCIE_VENDOR_SPECIFIC1 0xfffe10310108 #define cfgBIF_CFG_DEV0_EPF0_VF16_1_PCIE_VENDOR_SPECIFIC2 0xfffe1031010c #define cfgBIF_CFG_DEV0_EPF0_VF16_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0xfffe10310150 #define cfgBIF_CFG_DEV0_EPF0_VF16_1_PCIE_UNCORR_ERR_STATUS 0xfffe10310154 #define cfgBIF_CFG_DEV0_EPF0_VF16_1_PCIE_UNCORR_ERR_MASK 0xfffe10310158 #define cfgBIF_CFG_DEV0_EPF0_VF16_1_PCIE_UNCORR_ERR_SEVERITY 0xfffe1031015c #define cfgBIF_CFG_DEV0_EPF0_VF16_1_PCIE_CORR_ERR_STATUS 0xfffe10310160 #define cfgBIF_CFG_DEV0_EPF0_VF16_1_PCIE_CORR_ERR_MASK 0xfffe10310164 #define cfgBIF_CFG_DEV0_EPF0_VF16_1_PCIE_ADV_ERR_CAP_CNTL 0xfffe10310168 #define cfgBIF_CFG_DEV0_EPF0_VF16_1_PCIE_HDR_LOG0 0xfffe1031016c #define cfgBIF_CFG_DEV0_EPF0_VF16_1_PCIE_HDR_LOG1 0xfffe10310170 #define cfgBIF_CFG_DEV0_EPF0_VF16_1_PCIE_HDR_LOG2 0xfffe10310174 #define cfgBIF_CFG_DEV0_EPF0_VF16_1_PCIE_HDR_LOG3 0xfffe10310178 #define cfgBIF_CFG_DEV0_EPF0_VF16_1_PCIE_TLP_PREFIX_LOG0 0xfffe10310188 #define cfgBIF_CFG_DEV0_EPF0_VF16_1_PCIE_TLP_PREFIX_LOG1 0xfffe1031018c #define cfgBIF_CFG_DEV0_EPF0_VF16_1_PCIE_TLP_PREFIX_LOG2 0xfffe10310190 #define cfgBIF_CFG_DEV0_EPF0_VF16_1_PCIE_TLP_PREFIX_LOG3 0xfffe10310194 #define cfgBIF_CFG_DEV0_EPF0_VF16_1_PCIE_ATS_ENH_CAP_LIST 0xfffe103102b0 #define cfgBIF_CFG_DEV0_EPF0_VF16_1_PCIE_ATS_CAP 0xfffe103102b4 #define cfgBIF_CFG_DEV0_EPF0_VF16_1_PCIE_ATS_CNTL 0xfffe103102b6 #define cfgBIF_CFG_DEV0_EPF0_VF16_1_PCIE_ARI_ENH_CAP_LIST 0xfffe10310328 #define cfgBIF_CFG_DEV0_EPF0_VF16_1_PCIE_ARI_CAP 0xfffe1031032c #define cfgBIF_CFG_DEV0_EPF0_VF16_1_PCIE_ARI_CNTL 0xfffe1031032e // addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf17_bifcfgdecp // base address: 0xfffe10311000 #define cfgBIF_CFG_DEV0_EPF0_VF17_1_VENDOR_ID 0xfffe10311000 #define cfgBIF_CFG_DEV0_EPF0_VF17_1_DEVICE_ID 0xfffe10311002 #define cfgBIF_CFG_DEV0_EPF0_VF17_1_COMMAND 0xfffe10311004 #define cfgBIF_CFG_DEV0_EPF0_VF17_1_STATUS 0xfffe10311006 #define cfgBIF_CFG_DEV0_EPF0_VF17_1_REVISION_ID 0xfffe10311008 #define cfgBIF_CFG_DEV0_EPF0_VF17_1_PROG_INTERFACE 0xfffe10311009 #define cfgBIF_CFG_DEV0_EPF0_VF17_1_SUB_CLASS 0xfffe1031100a #define cfgBIF_CFG_DEV0_EPF0_VF17_1_BASE_CLASS 0xfffe1031100b #define cfgBIF_CFG_DEV0_EPF0_VF17_1_CACHE_LINE 0xfffe1031100c #define cfgBIF_CFG_DEV0_EPF0_VF17_1_LATENCY 0xfffe1031100d #define cfgBIF_CFG_DEV0_EPF0_VF17_1_HEADER 0xfffe1031100e #define cfgBIF_CFG_DEV0_EPF0_VF17_1_BIST 0xfffe1031100f #define cfgBIF_CFG_DEV0_EPF0_VF17_1_BASE_ADDR_1 0xfffe10311010 #define cfgBIF_CFG_DEV0_EPF0_VF17_1_BASE_ADDR_2 0xfffe10311014 #define cfgBIF_CFG_DEV0_EPF0_VF17_1_BASE_ADDR_3 0xfffe10311018 #define cfgBIF_CFG_DEV0_EPF0_VF17_1_BASE_ADDR_4 0xfffe1031101c #define cfgBIF_CFG_DEV0_EPF0_VF17_1_BASE_ADDR_5 0xfffe10311020 #define cfgBIF_CFG_DEV0_EPF0_VF17_1_BASE_ADDR_6 0xfffe10311024 #define cfgBIF_CFG_DEV0_EPF0_VF17_1_CARDBUS_CIS_PTR 0xfffe10311028 #define cfgBIF_CFG_DEV0_EPF0_VF17_1_ADAPTER_ID 0xfffe1031102c #define cfgBIF_CFG_DEV0_EPF0_VF17_1_ROM_BASE_ADDR 0xfffe10311030 #define cfgBIF_CFG_DEV0_EPF0_VF17_1_CAP_PTR 0xfffe10311034 #define cfgBIF_CFG_DEV0_EPF0_VF17_1_INTERRUPT_LINE 0xfffe1031103c #define cfgBIF_CFG_DEV0_EPF0_VF17_1_INTERRUPT_PIN 0xfffe1031103d #define cfgBIF_CFG_DEV0_EPF0_VF17_1_MIN_GRANT 0xfffe1031103e #define cfgBIF_CFG_DEV0_EPF0_VF17_1_MAX_LATENCY 0xfffe1031103f #define cfgBIF_CFG_DEV0_EPF0_VF17_1_PCIE_CAP_LIST 0xfffe10311064 #define cfgBIF_CFG_DEV0_EPF0_VF17_1_PCIE_CAP 0xfffe10311066 #define cfgBIF_CFG_DEV0_EPF0_VF17_1_DEVICE_CAP 0xfffe10311068 #define cfgBIF_CFG_DEV0_EPF0_VF17_1_DEVICE_CNTL 0xfffe1031106c #define cfgBIF_CFG_DEV0_EPF0_VF17_1_DEVICE_STATUS 0xfffe1031106e #define cfgBIF_CFG_DEV0_EPF0_VF17_1_LINK_CAP 0xfffe10311070 #define cfgBIF_CFG_DEV0_EPF0_VF17_1_LINK_CNTL 0xfffe10311074 #define cfgBIF_CFG_DEV0_EPF0_VF17_1_LINK_STATUS 0xfffe10311076 #define cfgBIF_CFG_DEV0_EPF0_VF17_1_DEVICE_CAP2 0xfffe10311088 #define cfgBIF_CFG_DEV0_EPF0_VF17_1_DEVICE_CNTL2 0xfffe1031108c #define cfgBIF_CFG_DEV0_EPF0_VF17_1_DEVICE_STATUS2 0xfffe1031108e #define cfgBIF_CFG_DEV0_EPF0_VF17_1_LINK_CAP2 0xfffe10311090 #define cfgBIF_CFG_DEV0_EPF0_VF17_1_LINK_CNTL2 0xfffe10311094 #define cfgBIF_CFG_DEV0_EPF0_VF17_1_LINK_STATUS2 0xfffe10311096 #define cfgBIF_CFG_DEV0_EPF0_VF17_1_MSI_CAP_LIST 0xfffe103110a0 #define cfgBIF_CFG_DEV0_EPF0_VF17_1_MSI_MSG_CNTL 0xfffe103110a2 #define cfgBIF_CFG_DEV0_EPF0_VF17_1_MSI_MSG_ADDR_LO 0xfffe103110a4 #define cfgBIF_CFG_DEV0_EPF0_VF17_1_MSI_MSG_ADDR_HI 0xfffe103110a8 #define cfgBIF_CFG_DEV0_EPF0_VF17_1_MSI_MSG_DATA 0xfffe103110a8 #define cfgBIF_CFG_DEV0_EPF0_VF17_1_MSI_MASK 0xfffe103110ac #define cfgBIF_CFG_DEV0_EPF0_VF17_1_MSI_MSG_DATA_64 0xfffe103110ac #define cfgBIF_CFG_DEV0_EPF0_VF17_1_MSI_MASK_64 0xfffe103110b0 #define cfgBIF_CFG_DEV0_EPF0_VF17_1_MSI_PENDING 0xfffe103110b0 #define cfgBIF_CFG_DEV0_EPF0_VF17_1_MSI_PENDING_64 0xfffe103110b4 #define cfgBIF_CFG_DEV0_EPF0_VF17_1_MSIX_CAP_LIST 0xfffe103110c0 #define cfgBIF_CFG_DEV0_EPF0_VF17_1_MSIX_MSG_CNTL 0xfffe103110c2 #define cfgBIF_CFG_DEV0_EPF0_VF17_1_MSIX_TABLE 0xfffe103110c4 #define cfgBIF_CFG_DEV0_EPF0_VF17_1_MSIX_PBA 0xfffe103110c8 #define cfgBIF_CFG_DEV0_EPF0_VF17_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0xfffe10311100 #define cfgBIF_CFG_DEV0_EPF0_VF17_1_PCIE_VENDOR_SPECIFIC_HDR 0xfffe10311104 #define cfgBIF_CFG_DEV0_EPF0_VF17_1_PCIE_VENDOR_SPECIFIC1 0xfffe10311108 #define cfgBIF_CFG_DEV0_EPF0_VF17_1_PCIE_VENDOR_SPECIFIC2 0xfffe1031110c #define cfgBIF_CFG_DEV0_EPF0_VF17_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0xfffe10311150 #define cfgBIF_CFG_DEV0_EPF0_VF17_1_PCIE_UNCORR_ERR_STATUS 0xfffe10311154 #define cfgBIF_CFG_DEV0_EPF0_VF17_1_PCIE_UNCORR_ERR_MASK 0xfffe10311158 #define cfgBIF_CFG_DEV0_EPF0_VF17_1_PCIE_UNCORR_ERR_SEVERITY 0xfffe1031115c #define cfgBIF_CFG_DEV0_EPF0_VF17_1_PCIE_CORR_ERR_STATUS 0xfffe10311160 #define cfgBIF_CFG_DEV0_EPF0_VF17_1_PCIE_CORR_ERR_MASK 0xfffe10311164 #define cfgBIF_CFG_DEV0_EPF0_VF17_1_PCIE_ADV_ERR_CAP_CNTL 0xfffe10311168 #define cfgBIF_CFG_DEV0_EPF0_VF17_1_PCIE_HDR_LOG0 0xfffe1031116c #define cfgBIF_CFG_DEV0_EPF0_VF17_1_PCIE_HDR_LOG1 0xfffe10311170 #define cfgBIF_CFG_DEV0_EPF0_VF17_1_PCIE_HDR_LOG2 0xfffe10311174 #define cfgBIF_CFG_DEV0_EPF0_VF17_1_PCIE_HDR_LOG3 0xfffe10311178 #define cfgBIF_CFG_DEV0_EPF0_VF17_1_PCIE_TLP_PREFIX_LOG0 0xfffe10311188 #define cfgBIF_CFG_DEV0_EPF0_VF17_1_PCIE_TLP_PREFIX_LOG1 0xfffe1031118c #define cfgBIF_CFG_DEV0_EPF0_VF17_1_PCIE_TLP_PREFIX_LOG2 0xfffe10311190 #define cfgBIF_CFG_DEV0_EPF0_VF17_1_PCIE_TLP_PREFIX_LOG3 0xfffe10311194 #define cfgBIF_CFG_DEV0_EPF0_VF17_1_PCIE_ATS_ENH_CAP_LIST 0xfffe103112b0 #define cfgBIF_CFG_DEV0_EPF0_VF17_1_PCIE_ATS_CAP 0xfffe103112b4 #define cfgBIF_CFG_DEV0_EPF0_VF17_1_PCIE_ATS_CNTL 0xfffe103112b6 #define cfgBIF_CFG_DEV0_EPF0_VF17_1_PCIE_ARI_ENH_CAP_LIST 0xfffe10311328 #define cfgBIF_CFG_DEV0_EPF0_VF17_1_PCIE_ARI_CAP 0xfffe1031132c #define cfgBIF_CFG_DEV0_EPF0_VF17_1_PCIE_ARI_CNTL 0xfffe1031132e // addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf18_bifcfgdecp // base address: 0xfffe10312000 #define cfgBIF_CFG_DEV0_EPF0_VF18_1_VENDOR_ID 0xfffe10312000 #define cfgBIF_CFG_DEV0_EPF0_VF18_1_DEVICE_ID 0xfffe10312002 #define cfgBIF_CFG_DEV0_EPF0_VF18_1_COMMAND 0xfffe10312004 #define cfgBIF_CFG_DEV0_EPF0_VF18_1_STATUS 0xfffe10312006 #define cfgBIF_CFG_DEV0_EPF0_VF18_1_REVISION_ID 0xfffe10312008 #define cfgBIF_CFG_DEV0_EPF0_VF18_1_PROG_INTERFACE 0xfffe10312009 #define cfgBIF_CFG_DEV0_EPF0_VF18_1_SUB_CLASS 0xfffe1031200a #define cfgBIF_CFG_DEV0_EPF0_VF18_1_BASE_CLASS 0xfffe1031200b #define cfgBIF_CFG_DEV0_EPF0_VF18_1_CACHE_LINE 0xfffe1031200c #define cfgBIF_CFG_DEV0_EPF0_VF18_1_LATENCY 0xfffe1031200d #define cfgBIF_CFG_DEV0_EPF0_VF18_1_HEADER 0xfffe1031200e #define cfgBIF_CFG_DEV0_EPF0_VF18_1_BIST 0xfffe1031200f #define cfgBIF_CFG_DEV0_EPF0_VF18_1_BASE_ADDR_1 0xfffe10312010 #define cfgBIF_CFG_DEV0_EPF0_VF18_1_BASE_ADDR_2 0xfffe10312014 #define cfgBIF_CFG_DEV0_EPF0_VF18_1_BASE_ADDR_3 0xfffe10312018 #define cfgBIF_CFG_DEV0_EPF0_VF18_1_BASE_ADDR_4 0xfffe1031201c #define cfgBIF_CFG_DEV0_EPF0_VF18_1_BASE_ADDR_5 0xfffe10312020 #define cfgBIF_CFG_DEV0_EPF0_VF18_1_BASE_ADDR_6 0xfffe10312024 #define cfgBIF_CFG_DEV0_EPF0_VF18_1_CARDBUS_CIS_PTR 0xfffe10312028 #define cfgBIF_CFG_DEV0_EPF0_VF18_1_ADAPTER_ID 0xfffe1031202c #define cfgBIF_CFG_DEV0_EPF0_VF18_1_ROM_BASE_ADDR 0xfffe10312030 #define cfgBIF_CFG_DEV0_EPF0_VF18_1_CAP_PTR 0xfffe10312034 #define cfgBIF_CFG_DEV0_EPF0_VF18_1_INTERRUPT_LINE 0xfffe1031203c #define cfgBIF_CFG_DEV0_EPF0_VF18_1_INTERRUPT_PIN 0xfffe1031203d #define cfgBIF_CFG_DEV0_EPF0_VF18_1_MIN_GRANT 0xfffe1031203e #define cfgBIF_CFG_DEV0_EPF0_VF18_1_MAX_LATENCY 0xfffe1031203f #define cfgBIF_CFG_DEV0_EPF0_VF18_1_PCIE_CAP_LIST 0xfffe10312064 #define cfgBIF_CFG_DEV0_EPF0_VF18_1_PCIE_CAP 0xfffe10312066 #define cfgBIF_CFG_DEV0_EPF0_VF18_1_DEVICE_CAP 0xfffe10312068 #define cfgBIF_CFG_DEV0_EPF0_VF18_1_DEVICE_CNTL 0xfffe1031206c #define cfgBIF_CFG_DEV0_EPF0_VF18_1_DEVICE_STATUS 0xfffe1031206e #define cfgBIF_CFG_DEV0_EPF0_VF18_1_LINK_CAP 0xfffe10312070 #define cfgBIF_CFG_DEV0_EPF0_VF18_1_LINK_CNTL 0xfffe10312074 #define cfgBIF_CFG_DEV0_EPF0_VF18_1_LINK_STATUS 0xfffe10312076 #define cfgBIF_CFG_DEV0_EPF0_VF18_1_DEVICE_CAP2 0xfffe10312088 #define cfgBIF_CFG_DEV0_EPF0_VF18_1_DEVICE_CNTL2 0xfffe1031208c #define cfgBIF_CFG_DEV0_EPF0_VF18_1_DEVICE_STATUS2 0xfffe1031208e #define cfgBIF_CFG_DEV0_EPF0_VF18_1_LINK_CAP2 0xfffe10312090 #define cfgBIF_CFG_DEV0_EPF0_VF18_1_LINK_CNTL2 0xfffe10312094 #define cfgBIF_CFG_DEV0_EPF0_VF18_1_LINK_STATUS2 0xfffe10312096 #define cfgBIF_CFG_DEV0_EPF0_VF18_1_MSI_CAP_LIST 0xfffe103120a0 #define cfgBIF_CFG_DEV0_EPF0_VF18_1_MSI_MSG_CNTL 0xfffe103120a2 #define cfgBIF_CFG_DEV0_EPF0_VF18_1_MSI_MSG_ADDR_LO 0xfffe103120a4 #define cfgBIF_CFG_DEV0_EPF0_VF18_1_MSI_MSG_ADDR_HI 0xfffe103120a8 #define cfgBIF_CFG_DEV0_EPF0_VF18_1_MSI_MSG_DATA 0xfffe103120a8 #define cfgBIF_CFG_DEV0_EPF0_VF18_1_MSI_MASK 0xfffe103120ac #define cfgBIF_CFG_DEV0_EPF0_VF18_1_MSI_MSG_DATA_64 0xfffe103120ac #define cfgBIF_CFG_DEV0_EPF0_VF18_1_MSI_MASK_64 0xfffe103120b0 #define cfgBIF_CFG_DEV0_EPF0_VF18_1_MSI_PENDING 0xfffe103120b0 #define cfgBIF_CFG_DEV0_EPF0_VF18_1_MSI_PENDING_64 0xfffe103120b4 #define cfgBIF_CFG_DEV0_EPF0_VF18_1_MSIX_CAP_LIST 0xfffe103120c0 #define cfgBIF_CFG_DEV0_EPF0_VF18_1_MSIX_MSG_CNTL 0xfffe103120c2 #define cfgBIF_CFG_DEV0_EPF0_VF18_1_MSIX_TABLE 0xfffe103120c4 #define cfgBIF_CFG_DEV0_EPF0_VF18_1_MSIX_PBA 0xfffe103120c8 #define cfgBIF_CFG_DEV0_EPF0_VF18_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0xfffe10312100 #define cfgBIF_CFG_DEV0_EPF0_VF18_1_PCIE_VENDOR_SPECIFIC_HDR 0xfffe10312104 #define cfgBIF_CFG_DEV0_EPF0_VF18_1_PCIE_VENDOR_SPECIFIC1 0xfffe10312108 #define cfgBIF_CFG_DEV0_EPF0_VF18_1_PCIE_VENDOR_SPECIFIC2 0xfffe1031210c #define cfgBIF_CFG_DEV0_EPF0_VF18_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0xfffe10312150 #define cfgBIF_CFG_DEV0_EPF0_VF18_1_PCIE_UNCORR_ERR_STATUS 0xfffe10312154 #define cfgBIF_CFG_DEV0_EPF0_VF18_1_PCIE_UNCORR_ERR_MASK 0xfffe10312158 #define cfgBIF_CFG_DEV0_EPF0_VF18_1_PCIE_UNCORR_ERR_SEVERITY 0xfffe1031215c #define cfgBIF_CFG_DEV0_EPF0_VF18_1_PCIE_CORR_ERR_STATUS 0xfffe10312160 #define cfgBIF_CFG_DEV0_EPF0_VF18_1_PCIE_CORR_ERR_MASK 0xfffe10312164 #define cfgBIF_CFG_DEV0_EPF0_VF18_1_PCIE_ADV_ERR_CAP_CNTL 0xfffe10312168 #define cfgBIF_CFG_DEV0_EPF0_VF18_1_PCIE_HDR_LOG0 0xfffe1031216c #define cfgBIF_CFG_DEV0_EPF0_VF18_1_PCIE_HDR_LOG1 0xfffe10312170 #define cfgBIF_CFG_DEV0_EPF0_VF18_1_PCIE_HDR_LOG2 0xfffe10312174 #define cfgBIF_CFG_DEV0_EPF0_VF18_1_PCIE_HDR_LOG3 0xfffe10312178 #define cfgBIF_CFG_DEV0_EPF0_VF18_1_PCIE_TLP_PREFIX_LOG0 0xfffe10312188 #define cfgBIF_CFG_DEV0_EPF0_VF18_1_PCIE_TLP_PREFIX_LOG1 0xfffe1031218c #define cfgBIF_CFG_DEV0_EPF0_VF18_1_PCIE_TLP_PREFIX_LOG2 0xfffe10312190 #define cfgBIF_CFG_DEV0_EPF0_VF18_1_PCIE_TLP_PREFIX_LOG3 0xfffe10312194 #define cfgBIF_CFG_DEV0_EPF0_VF18_1_PCIE_ATS_ENH_CAP_LIST 0xfffe103122b0 #define cfgBIF_CFG_DEV0_EPF0_VF18_1_PCIE_ATS_CAP 0xfffe103122b4 #define cfgBIF_CFG_DEV0_EPF0_VF18_1_PCIE_ATS_CNTL 0xfffe103122b6 #define cfgBIF_CFG_DEV0_EPF0_VF18_1_PCIE_ARI_ENH_CAP_LIST 0xfffe10312328 #define cfgBIF_CFG_DEV0_EPF0_VF18_1_PCIE_ARI_CAP 0xfffe1031232c #define cfgBIF_CFG_DEV0_EPF0_VF18_1_PCIE_ARI_CNTL 0xfffe1031232e // addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf19_bifcfgdecp // base address: 0xfffe10313000 #define cfgBIF_CFG_DEV0_EPF0_VF19_1_VENDOR_ID 0xfffe10313000 #define cfgBIF_CFG_DEV0_EPF0_VF19_1_DEVICE_ID 0xfffe10313002 #define cfgBIF_CFG_DEV0_EPF0_VF19_1_COMMAND 0xfffe10313004 #define cfgBIF_CFG_DEV0_EPF0_VF19_1_STATUS 0xfffe10313006 #define cfgBIF_CFG_DEV0_EPF0_VF19_1_REVISION_ID 0xfffe10313008 #define cfgBIF_CFG_DEV0_EPF0_VF19_1_PROG_INTERFACE 0xfffe10313009 #define cfgBIF_CFG_DEV0_EPF0_VF19_1_SUB_CLASS 0xfffe1031300a #define cfgBIF_CFG_DEV0_EPF0_VF19_1_BASE_CLASS 0xfffe1031300b #define cfgBIF_CFG_DEV0_EPF0_VF19_1_CACHE_LINE 0xfffe1031300c #define cfgBIF_CFG_DEV0_EPF0_VF19_1_LATENCY 0xfffe1031300d #define cfgBIF_CFG_DEV0_EPF0_VF19_1_HEADER 0xfffe1031300e #define cfgBIF_CFG_DEV0_EPF0_VF19_1_BIST 0xfffe1031300f #define cfgBIF_CFG_DEV0_EPF0_VF19_1_BASE_ADDR_1 0xfffe10313010 #define cfgBIF_CFG_DEV0_EPF0_VF19_1_BASE_ADDR_2 0xfffe10313014 #define cfgBIF_CFG_DEV0_EPF0_VF19_1_BASE_ADDR_3 0xfffe10313018 #define cfgBIF_CFG_DEV0_EPF0_VF19_1_BASE_ADDR_4 0xfffe1031301c #define cfgBIF_CFG_DEV0_EPF0_VF19_1_BASE_ADDR_5 0xfffe10313020 #define cfgBIF_CFG_DEV0_EPF0_VF19_1_BASE_ADDR_6 0xfffe10313024 #define cfgBIF_CFG_DEV0_EPF0_VF19_1_CARDBUS_CIS_PTR 0xfffe10313028 #define cfgBIF_CFG_DEV0_EPF0_VF19_1_ADAPTER_ID 0xfffe1031302c #define cfgBIF_CFG_DEV0_EPF0_VF19_1_ROM_BASE_ADDR 0xfffe10313030 #define cfgBIF_CFG_DEV0_EPF0_VF19_1_CAP_PTR 0xfffe10313034 #define cfgBIF_CFG_DEV0_EPF0_VF19_1_INTERRUPT_LINE 0xfffe1031303c #define cfgBIF_CFG_DEV0_EPF0_VF19_1_INTERRUPT_PIN 0xfffe1031303d #define cfgBIF_CFG_DEV0_EPF0_VF19_1_MIN_GRANT 0xfffe1031303e #define cfgBIF_CFG_DEV0_EPF0_VF19_1_MAX_LATENCY 0xfffe1031303f #define cfgBIF_CFG_DEV0_EPF0_VF19_1_PCIE_CAP_LIST 0xfffe10313064 #define cfgBIF_CFG_DEV0_EPF0_VF19_1_PCIE_CAP 0xfffe10313066 #define cfgBIF_CFG_DEV0_EPF0_VF19_1_DEVICE_CAP 0xfffe10313068 #define cfgBIF_CFG_DEV0_EPF0_VF19_1_DEVICE_CNTL 0xfffe1031306c #define cfgBIF_CFG_DEV0_EPF0_VF19_1_DEVICE_STATUS 0xfffe1031306e #define cfgBIF_CFG_DEV0_EPF0_VF19_1_LINK_CAP 0xfffe10313070 #define cfgBIF_CFG_DEV0_EPF0_VF19_1_LINK_CNTL 0xfffe10313074 #define cfgBIF_CFG_DEV0_EPF0_VF19_1_LINK_STATUS 0xfffe10313076 #define cfgBIF_CFG_DEV0_EPF0_VF19_1_DEVICE_CAP2 0xfffe10313088 #define cfgBIF_CFG_DEV0_EPF0_VF19_1_DEVICE_CNTL2 0xfffe1031308c #define cfgBIF_CFG_DEV0_EPF0_VF19_1_DEVICE_STATUS2 0xfffe1031308e #define cfgBIF_CFG_DEV0_EPF0_VF19_1_LINK_CAP2 0xfffe10313090 #define cfgBIF_CFG_DEV0_EPF0_VF19_1_LINK_CNTL2 0xfffe10313094 #define cfgBIF_CFG_DEV0_EPF0_VF19_1_LINK_STATUS2 0xfffe10313096 #define cfgBIF_CFG_DEV0_EPF0_VF19_1_MSI_CAP_LIST 0xfffe103130a0 #define cfgBIF_CFG_DEV0_EPF0_VF19_1_MSI_MSG_CNTL 0xfffe103130a2 #define cfgBIF_CFG_DEV0_EPF0_VF19_1_MSI_MSG_ADDR_LO 0xfffe103130a4 #define cfgBIF_CFG_DEV0_EPF0_VF19_1_MSI_MSG_ADDR_HI 0xfffe103130a8 #define cfgBIF_CFG_DEV0_EPF0_VF19_1_MSI_MSG_DATA 0xfffe103130a8 #define cfgBIF_CFG_DEV0_EPF0_VF19_1_MSI_MASK 0xfffe103130ac #define cfgBIF_CFG_DEV0_EPF0_VF19_1_MSI_MSG_DATA_64 0xfffe103130ac #define cfgBIF_CFG_DEV0_EPF0_VF19_1_MSI_MASK_64 0xfffe103130b0 #define cfgBIF_CFG_DEV0_EPF0_VF19_1_MSI_PENDING 0xfffe103130b0 #define cfgBIF_CFG_DEV0_EPF0_VF19_1_MSI_PENDING_64 0xfffe103130b4 #define cfgBIF_CFG_DEV0_EPF0_VF19_1_MSIX_CAP_LIST 0xfffe103130c0 #define cfgBIF_CFG_DEV0_EPF0_VF19_1_MSIX_MSG_CNTL 0xfffe103130c2 #define cfgBIF_CFG_DEV0_EPF0_VF19_1_MSIX_TABLE 0xfffe103130c4 #define cfgBIF_CFG_DEV0_EPF0_VF19_1_MSIX_PBA 0xfffe103130c8 #define cfgBIF_CFG_DEV0_EPF0_VF19_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0xfffe10313100 #define cfgBIF_CFG_DEV0_EPF0_VF19_1_PCIE_VENDOR_SPECIFIC_HDR 0xfffe10313104 #define cfgBIF_CFG_DEV0_EPF0_VF19_1_PCIE_VENDOR_SPECIFIC1 0xfffe10313108 #define cfgBIF_CFG_DEV0_EPF0_VF19_1_PCIE_VENDOR_SPECIFIC2 0xfffe1031310c #define cfgBIF_CFG_DEV0_EPF0_VF19_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0xfffe10313150 #define cfgBIF_CFG_DEV0_EPF0_VF19_1_PCIE_UNCORR_ERR_STATUS 0xfffe10313154 #define cfgBIF_CFG_DEV0_EPF0_VF19_1_PCIE_UNCORR_ERR_MASK 0xfffe10313158 #define cfgBIF_CFG_DEV0_EPF0_VF19_1_PCIE_UNCORR_ERR_SEVERITY 0xfffe1031315c #define cfgBIF_CFG_DEV0_EPF0_VF19_1_PCIE_CORR_ERR_STATUS 0xfffe10313160 #define cfgBIF_CFG_DEV0_EPF0_VF19_1_PCIE_CORR_ERR_MASK 0xfffe10313164 #define cfgBIF_CFG_DEV0_EPF0_VF19_1_PCIE_ADV_ERR_CAP_CNTL 0xfffe10313168 #define cfgBIF_CFG_DEV0_EPF0_VF19_1_PCIE_HDR_LOG0 0xfffe1031316c #define cfgBIF_CFG_DEV0_EPF0_VF19_1_PCIE_HDR_LOG1 0xfffe10313170 #define cfgBIF_CFG_DEV0_EPF0_VF19_1_PCIE_HDR_LOG2 0xfffe10313174 #define cfgBIF_CFG_DEV0_EPF0_VF19_1_PCIE_HDR_LOG3 0xfffe10313178 #define cfgBIF_CFG_DEV0_EPF0_VF19_1_PCIE_TLP_PREFIX_LOG0 0xfffe10313188 #define cfgBIF_CFG_DEV0_EPF0_VF19_1_PCIE_TLP_PREFIX_LOG1 0xfffe1031318c #define cfgBIF_CFG_DEV0_EPF0_VF19_1_PCIE_TLP_PREFIX_LOG2 0xfffe10313190 #define cfgBIF_CFG_DEV0_EPF0_VF19_1_PCIE_TLP_PREFIX_LOG3 0xfffe10313194 #define cfgBIF_CFG_DEV0_EPF0_VF19_1_PCIE_ATS_ENH_CAP_LIST 0xfffe103132b0 #define cfgBIF_CFG_DEV0_EPF0_VF19_1_PCIE_ATS_CAP 0xfffe103132b4 #define cfgBIF_CFG_DEV0_EPF0_VF19_1_PCIE_ATS_CNTL 0xfffe103132b6 #define cfgBIF_CFG_DEV0_EPF0_VF19_1_PCIE_ARI_ENH_CAP_LIST 0xfffe10313328 #define cfgBIF_CFG_DEV0_EPF0_VF19_1_PCIE_ARI_CAP 0xfffe1031332c #define cfgBIF_CFG_DEV0_EPF0_VF19_1_PCIE_ARI_CNTL 0xfffe1031332e // addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf20_bifcfgdecp // base address: 0xfffe10314000 #define cfgBIF_CFG_DEV0_EPF0_VF20_1_VENDOR_ID 0xfffe10314000 #define cfgBIF_CFG_DEV0_EPF0_VF20_1_DEVICE_ID 0xfffe10314002 #define cfgBIF_CFG_DEV0_EPF0_VF20_1_COMMAND 0xfffe10314004 #define cfgBIF_CFG_DEV0_EPF0_VF20_1_STATUS 0xfffe10314006 #define cfgBIF_CFG_DEV0_EPF0_VF20_1_REVISION_ID 0xfffe10314008 #define cfgBIF_CFG_DEV0_EPF0_VF20_1_PROG_INTERFACE 0xfffe10314009 #define cfgBIF_CFG_DEV0_EPF0_VF20_1_SUB_CLASS 0xfffe1031400a #define cfgBIF_CFG_DEV0_EPF0_VF20_1_BASE_CLASS 0xfffe1031400b #define cfgBIF_CFG_DEV0_EPF0_VF20_1_CACHE_LINE 0xfffe1031400c #define cfgBIF_CFG_DEV0_EPF0_VF20_1_LATENCY 0xfffe1031400d #define cfgBIF_CFG_DEV0_EPF0_VF20_1_HEADER 0xfffe1031400e #define cfgBIF_CFG_DEV0_EPF0_VF20_1_BIST 0xfffe1031400f #define cfgBIF_CFG_DEV0_EPF0_VF20_1_BASE_ADDR_1 0xfffe10314010 #define cfgBIF_CFG_DEV0_EPF0_VF20_1_BASE_ADDR_2 0xfffe10314014 #define cfgBIF_CFG_DEV0_EPF0_VF20_1_BASE_ADDR_3 0xfffe10314018 #define cfgBIF_CFG_DEV0_EPF0_VF20_1_BASE_ADDR_4 0xfffe1031401c #define cfgBIF_CFG_DEV0_EPF0_VF20_1_BASE_ADDR_5 0xfffe10314020 #define cfgBIF_CFG_DEV0_EPF0_VF20_1_BASE_ADDR_6 0xfffe10314024 #define cfgBIF_CFG_DEV0_EPF0_VF20_1_CARDBUS_CIS_PTR 0xfffe10314028 #define cfgBIF_CFG_DEV0_EPF0_VF20_1_ADAPTER_ID 0xfffe1031402c #define cfgBIF_CFG_DEV0_EPF0_VF20_1_ROM_BASE_ADDR 0xfffe10314030 #define cfgBIF_CFG_DEV0_EPF0_VF20_1_CAP_PTR 0xfffe10314034 #define cfgBIF_CFG_DEV0_EPF0_VF20_1_INTERRUPT_LINE 0xfffe1031403c #define cfgBIF_CFG_DEV0_EPF0_VF20_1_INTERRUPT_PIN 0xfffe1031403d #define cfgBIF_CFG_DEV0_EPF0_VF20_1_MIN_GRANT 0xfffe1031403e #define cfgBIF_CFG_DEV0_EPF0_VF20_1_MAX_LATENCY 0xfffe1031403f #define cfgBIF_CFG_DEV0_EPF0_VF20_1_PCIE_CAP_LIST 0xfffe10314064 #define cfgBIF_CFG_DEV0_EPF0_VF20_1_PCIE_CAP 0xfffe10314066 #define cfgBIF_CFG_DEV0_EPF0_VF20_1_DEVICE_CAP 0xfffe10314068 #define cfgBIF_CFG_DEV0_EPF0_VF20_1_DEVICE_CNTL 0xfffe1031406c #define cfgBIF_CFG_DEV0_EPF0_VF20_1_DEVICE_STATUS 0xfffe1031406e #define cfgBIF_CFG_DEV0_EPF0_VF20_1_LINK_CAP 0xfffe10314070 #define cfgBIF_CFG_DEV0_EPF0_VF20_1_LINK_CNTL 0xfffe10314074 #define cfgBIF_CFG_DEV0_EPF0_VF20_1_LINK_STATUS 0xfffe10314076 #define cfgBIF_CFG_DEV0_EPF0_VF20_1_DEVICE_CAP2 0xfffe10314088 #define cfgBIF_CFG_DEV0_EPF0_VF20_1_DEVICE_CNTL2 0xfffe1031408c #define cfgBIF_CFG_DEV0_EPF0_VF20_1_DEVICE_STATUS2 0xfffe1031408e #define cfgBIF_CFG_DEV0_EPF0_VF20_1_LINK_CAP2 0xfffe10314090 #define cfgBIF_CFG_DEV0_EPF0_VF20_1_LINK_CNTL2 0xfffe10314094 #define cfgBIF_CFG_DEV0_EPF0_VF20_1_LINK_STATUS2 0xfffe10314096 #define cfgBIF_CFG_DEV0_EPF0_VF20_1_MSI_CAP_LIST 0xfffe103140a0 #define cfgBIF_CFG_DEV0_EPF0_VF20_1_MSI_MSG_CNTL 0xfffe103140a2 #define cfgBIF_CFG_DEV0_EPF0_VF20_1_MSI_MSG_ADDR_LO 0xfffe103140a4 #define cfgBIF_CFG_DEV0_EPF0_VF20_1_MSI_MSG_ADDR_HI 0xfffe103140a8 #define cfgBIF_CFG_DEV0_EPF0_VF20_1_MSI_MSG_DATA 0xfffe103140a8 #define cfgBIF_CFG_DEV0_EPF0_VF20_1_MSI_MASK 0xfffe103140ac #define cfgBIF_CFG_DEV0_EPF0_VF20_1_MSI_MSG_DATA_64 0xfffe103140ac #define cfgBIF_CFG_DEV0_EPF0_VF20_1_MSI_MASK_64 0xfffe103140b0 #define cfgBIF_CFG_DEV0_EPF0_VF20_1_MSI_PENDING 0xfffe103140b0 #define cfgBIF_CFG_DEV0_EPF0_VF20_1_MSI_PENDING_64 0xfffe103140b4 #define cfgBIF_CFG_DEV0_EPF0_VF20_1_MSIX_CAP_LIST 0xfffe103140c0 #define cfgBIF_CFG_DEV0_EPF0_VF20_1_MSIX_MSG_CNTL 0xfffe103140c2 #define cfgBIF_CFG_DEV0_EPF0_VF20_1_MSIX_TABLE 0xfffe103140c4 #define cfgBIF_CFG_DEV0_EPF0_VF20_1_MSIX_PBA 0xfffe103140c8 #define cfgBIF_CFG_DEV0_EPF0_VF20_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0xfffe10314100 #define cfgBIF_CFG_DEV0_EPF0_VF20_1_PCIE_VENDOR_SPECIFIC_HDR 0xfffe10314104 #define cfgBIF_CFG_DEV0_EPF0_VF20_1_PCIE_VENDOR_SPECIFIC1 0xfffe10314108 #define cfgBIF_CFG_DEV0_EPF0_VF20_1_PCIE_VENDOR_SPECIFIC2 0xfffe1031410c #define cfgBIF_CFG_DEV0_EPF0_VF20_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0xfffe10314150 #define cfgBIF_CFG_DEV0_EPF0_VF20_1_PCIE_UNCORR_ERR_STATUS 0xfffe10314154 #define cfgBIF_CFG_DEV0_EPF0_VF20_1_PCIE_UNCORR_ERR_MASK 0xfffe10314158 #define cfgBIF_CFG_DEV0_EPF0_VF20_1_PCIE_UNCORR_ERR_SEVERITY 0xfffe1031415c #define cfgBIF_CFG_DEV0_EPF0_VF20_1_PCIE_CORR_ERR_STATUS 0xfffe10314160 #define cfgBIF_CFG_DEV0_EPF0_VF20_1_PCIE_CORR_ERR_MASK 0xfffe10314164 #define cfgBIF_CFG_DEV0_EPF0_VF20_1_PCIE_ADV_ERR_CAP_CNTL 0xfffe10314168 #define cfgBIF_CFG_DEV0_EPF0_VF20_1_PCIE_HDR_LOG0 0xfffe1031416c #define cfgBIF_CFG_DEV0_EPF0_VF20_1_PCIE_HDR_LOG1 0xfffe10314170 #define cfgBIF_CFG_DEV0_EPF0_VF20_1_PCIE_HDR_LOG2 0xfffe10314174 #define cfgBIF_CFG_DEV0_EPF0_VF20_1_PCIE_HDR_LOG3 0xfffe10314178 #define cfgBIF_CFG_DEV0_EPF0_VF20_1_PCIE_TLP_PREFIX_LOG0 0xfffe10314188 #define cfgBIF_CFG_DEV0_EPF0_VF20_1_PCIE_TLP_PREFIX_LOG1 0xfffe1031418c #define cfgBIF_CFG_DEV0_EPF0_VF20_1_PCIE_TLP_PREFIX_LOG2 0xfffe10314190 #define cfgBIF_CFG_DEV0_EPF0_VF20_1_PCIE_TLP_PREFIX_LOG3 0xfffe10314194 #define cfgBIF_CFG_DEV0_EPF0_VF20_1_PCIE_ATS_ENH_CAP_LIST 0xfffe103142b0 #define cfgBIF_CFG_DEV0_EPF0_VF20_1_PCIE_ATS_CAP 0xfffe103142b4 #define cfgBIF_CFG_DEV0_EPF0_VF20_1_PCIE_ATS_CNTL 0xfffe103142b6 #define cfgBIF_CFG_DEV0_EPF0_VF20_1_PCIE_ARI_ENH_CAP_LIST 0xfffe10314328 #define cfgBIF_CFG_DEV0_EPF0_VF20_1_PCIE_ARI_CAP 0xfffe1031432c #define cfgBIF_CFG_DEV0_EPF0_VF20_1_PCIE_ARI_CNTL 0xfffe1031432e // addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf21_bifcfgdecp // base address: 0xfffe10315000 #define cfgBIF_CFG_DEV0_EPF0_VF21_1_VENDOR_ID 0xfffe10315000 #define cfgBIF_CFG_DEV0_EPF0_VF21_1_DEVICE_ID 0xfffe10315002 #define cfgBIF_CFG_DEV0_EPF0_VF21_1_COMMAND 0xfffe10315004 #define cfgBIF_CFG_DEV0_EPF0_VF21_1_STATUS 0xfffe10315006 #define cfgBIF_CFG_DEV0_EPF0_VF21_1_REVISION_ID 0xfffe10315008 #define cfgBIF_CFG_DEV0_EPF0_VF21_1_PROG_INTERFACE 0xfffe10315009 #define cfgBIF_CFG_DEV0_EPF0_VF21_1_SUB_CLASS 0xfffe1031500a #define cfgBIF_CFG_DEV0_EPF0_VF21_1_BASE_CLASS 0xfffe1031500b #define cfgBIF_CFG_DEV0_EPF0_VF21_1_CACHE_LINE 0xfffe1031500c #define cfgBIF_CFG_DEV0_EPF0_VF21_1_LATENCY 0xfffe1031500d #define cfgBIF_CFG_DEV0_EPF0_VF21_1_HEADER 0xfffe1031500e #define cfgBIF_CFG_DEV0_EPF0_VF21_1_BIST 0xfffe1031500f #define cfgBIF_CFG_DEV0_EPF0_VF21_1_BASE_ADDR_1 0xfffe10315010 #define cfgBIF_CFG_DEV0_EPF0_VF21_1_BASE_ADDR_2 0xfffe10315014 #define cfgBIF_CFG_DEV0_EPF0_VF21_1_BASE_ADDR_3 0xfffe10315018 #define cfgBIF_CFG_DEV0_EPF0_VF21_1_BASE_ADDR_4 0xfffe1031501c #define cfgBIF_CFG_DEV0_EPF0_VF21_1_BASE_ADDR_5 0xfffe10315020 #define cfgBIF_CFG_DEV0_EPF0_VF21_1_BASE_ADDR_6 0xfffe10315024 #define cfgBIF_CFG_DEV0_EPF0_VF21_1_CARDBUS_CIS_PTR 0xfffe10315028 #define cfgBIF_CFG_DEV0_EPF0_VF21_1_ADAPTER_ID 0xfffe1031502c #define cfgBIF_CFG_DEV0_EPF0_VF21_1_ROM_BASE_ADDR 0xfffe10315030 #define cfgBIF_CFG_DEV0_EPF0_VF21_1_CAP_PTR 0xfffe10315034 #define cfgBIF_CFG_DEV0_EPF0_VF21_1_INTERRUPT_LINE 0xfffe1031503c #define cfgBIF_CFG_DEV0_EPF0_VF21_1_INTERRUPT_PIN 0xfffe1031503d #define cfgBIF_CFG_DEV0_EPF0_VF21_1_MIN_GRANT 0xfffe1031503e #define cfgBIF_CFG_DEV0_EPF0_VF21_1_MAX_LATENCY 0xfffe1031503f #define cfgBIF_CFG_DEV0_EPF0_VF21_1_PCIE_CAP_LIST 0xfffe10315064 #define cfgBIF_CFG_DEV0_EPF0_VF21_1_PCIE_CAP 0xfffe10315066 #define cfgBIF_CFG_DEV0_EPF0_VF21_1_DEVICE_CAP 0xfffe10315068 #define cfgBIF_CFG_DEV0_EPF0_VF21_1_DEVICE_CNTL 0xfffe1031506c #define cfgBIF_CFG_DEV0_EPF0_VF21_1_DEVICE_STATUS 0xfffe1031506e #define cfgBIF_CFG_DEV0_EPF0_VF21_1_LINK_CAP 0xfffe10315070 #define cfgBIF_CFG_DEV0_EPF0_VF21_1_LINK_CNTL 0xfffe10315074 #define cfgBIF_CFG_DEV0_EPF0_VF21_1_LINK_STATUS 0xfffe10315076 #define cfgBIF_CFG_DEV0_EPF0_VF21_1_DEVICE_CAP2 0xfffe10315088 #define cfgBIF_CFG_DEV0_EPF0_VF21_1_DEVICE_CNTL2 0xfffe1031508c #define cfgBIF_CFG_DEV0_EPF0_VF21_1_DEVICE_STATUS2 0xfffe1031508e #define cfgBIF_CFG_DEV0_EPF0_VF21_1_LINK_CAP2 0xfffe10315090 #define cfgBIF_CFG_DEV0_EPF0_VF21_1_LINK_CNTL2 0xfffe10315094 #define cfgBIF_CFG_DEV0_EPF0_VF21_1_LINK_STATUS2 0xfffe10315096 #define cfgBIF_CFG_DEV0_EPF0_VF21_1_MSI_CAP_LIST 0xfffe103150a0 #define cfgBIF_CFG_DEV0_EPF0_VF21_1_MSI_MSG_CNTL 0xfffe103150a2 #define cfgBIF_CFG_DEV0_EPF0_VF21_1_MSI_MSG_ADDR_LO 0xfffe103150a4 #define cfgBIF_CFG_DEV0_EPF0_VF21_1_MSI_MSG_ADDR_HI 0xfffe103150a8 #define cfgBIF_CFG_DEV0_EPF0_VF21_1_MSI_MSG_DATA 0xfffe103150a8 #define cfgBIF_CFG_DEV0_EPF0_VF21_1_MSI_MASK 0xfffe103150ac #define cfgBIF_CFG_DEV0_EPF0_VF21_1_MSI_MSG_DATA_64 0xfffe103150ac #define cfgBIF_CFG_DEV0_EPF0_VF21_1_MSI_MASK_64 0xfffe103150b0 #define cfgBIF_CFG_DEV0_EPF0_VF21_1_MSI_PENDING 0xfffe103150b0 #define cfgBIF_CFG_DEV0_EPF0_VF21_1_MSI_PENDING_64 0xfffe103150b4 #define cfgBIF_CFG_DEV0_EPF0_VF21_1_MSIX_CAP_LIST 0xfffe103150c0 #define cfgBIF_CFG_DEV0_EPF0_VF21_1_MSIX_MSG_CNTL 0xfffe103150c2 #define cfgBIF_CFG_DEV0_EPF0_VF21_1_MSIX_TABLE 0xfffe103150c4 #define cfgBIF_CFG_DEV0_EPF0_VF21_1_MSIX_PBA 0xfffe103150c8 #define cfgBIF_CFG_DEV0_EPF0_VF21_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0xfffe10315100 #define cfgBIF_CFG_DEV0_EPF0_VF21_1_PCIE_VENDOR_SPECIFIC_HDR 0xfffe10315104 #define cfgBIF_CFG_DEV0_EPF0_VF21_1_PCIE_VENDOR_SPECIFIC1 0xfffe10315108 #define cfgBIF_CFG_DEV0_EPF0_VF21_1_PCIE_VENDOR_SPECIFIC2 0xfffe1031510c #define cfgBIF_CFG_DEV0_EPF0_VF21_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0xfffe10315150 #define cfgBIF_CFG_DEV0_EPF0_VF21_1_PCIE_UNCORR_ERR_STATUS 0xfffe10315154 #define cfgBIF_CFG_DEV0_EPF0_VF21_1_PCIE_UNCORR_ERR_MASK 0xfffe10315158 #define cfgBIF_CFG_DEV0_EPF0_VF21_1_PCIE_UNCORR_ERR_SEVERITY 0xfffe1031515c #define cfgBIF_CFG_DEV0_EPF0_VF21_1_PCIE_CORR_ERR_STATUS 0xfffe10315160 #define cfgBIF_CFG_DEV0_EPF0_VF21_1_PCIE_CORR_ERR_MASK 0xfffe10315164 #define cfgBIF_CFG_DEV0_EPF0_VF21_1_PCIE_ADV_ERR_CAP_CNTL 0xfffe10315168 #define cfgBIF_CFG_DEV0_EPF0_VF21_1_PCIE_HDR_LOG0 0xfffe1031516c #define cfgBIF_CFG_DEV0_EPF0_VF21_1_PCIE_HDR_LOG1 0xfffe10315170 #define cfgBIF_CFG_DEV0_EPF0_VF21_1_PCIE_HDR_LOG2 0xfffe10315174 #define cfgBIF_CFG_DEV0_EPF0_VF21_1_PCIE_HDR_LOG3 0xfffe10315178 #define cfgBIF_CFG_DEV0_EPF0_VF21_1_PCIE_TLP_PREFIX_LOG0 0xfffe10315188 #define cfgBIF_CFG_DEV0_EPF0_VF21_1_PCIE_TLP_PREFIX_LOG1 0xfffe1031518c #define cfgBIF_CFG_DEV0_EPF0_VF21_1_PCIE_TLP_PREFIX_LOG2 0xfffe10315190 #define cfgBIF_CFG_DEV0_EPF0_VF21_1_PCIE_TLP_PREFIX_LOG3 0xfffe10315194 #define cfgBIF_CFG_DEV0_EPF0_VF21_1_PCIE_ATS_ENH_CAP_LIST 0xfffe103152b0 #define cfgBIF_CFG_DEV0_EPF0_VF21_1_PCIE_ATS_CAP 0xfffe103152b4 #define cfgBIF_CFG_DEV0_EPF0_VF21_1_PCIE_ATS_CNTL 0xfffe103152b6 #define cfgBIF_CFG_DEV0_EPF0_VF21_1_PCIE_ARI_ENH_CAP_LIST 0xfffe10315328 #define cfgBIF_CFG_DEV0_EPF0_VF21_1_PCIE_ARI_CAP 0xfffe1031532c #define cfgBIF_CFG_DEV0_EPF0_VF21_1_PCIE_ARI_CNTL 0xfffe1031532e // addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf22_bifcfgdecp // base address: 0xfffe10316000 #define cfgBIF_CFG_DEV0_EPF0_VF22_1_VENDOR_ID 0xfffe10316000 #define cfgBIF_CFG_DEV0_EPF0_VF22_1_DEVICE_ID 0xfffe10316002 #define cfgBIF_CFG_DEV0_EPF0_VF22_1_COMMAND 0xfffe10316004 #define cfgBIF_CFG_DEV0_EPF0_VF22_1_STATUS 0xfffe10316006 #define cfgBIF_CFG_DEV0_EPF0_VF22_1_REVISION_ID 0xfffe10316008 #define cfgBIF_CFG_DEV0_EPF0_VF22_1_PROG_INTERFACE 0xfffe10316009 #define cfgBIF_CFG_DEV0_EPF0_VF22_1_SUB_CLASS 0xfffe1031600a #define cfgBIF_CFG_DEV0_EPF0_VF22_1_BASE_CLASS 0xfffe1031600b #define cfgBIF_CFG_DEV0_EPF0_VF22_1_CACHE_LINE 0xfffe1031600c #define cfgBIF_CFG_DEV0_EPF0_VF22_1_LATENCY 0xfffe1031600d #define cfgBIF_CFG_DEV0_EPF0_VF22_1_HEADER 0xfffe1031600e #define cfgBIF_CFG_DEV0_EPF0_VF22_1_BIST 0xfffe1031600f #define cfgBIF_CFG_DEV0_EPF0_VF22_1_BASE_ADDR_1 0xfffe10316010 #define cfgBIF_CFG_DEV0_EPF0_VF22_1_BASE_ADDR_2 0xfffe10316014 #define cfgBIF_CFG_DEV0_EPF0_VF22_1_BASE_ADDR_3 0xfffe10316018 #define cfgBIF_CFG_DEV0_EPF0_VF22_1_BASE_ADDR_4 0xfffe1031601c #define cfgBIF_CFG_DEV0_EPF0_VF22_1_BASE_ADDR_5 0xfffe10316020 #define cfgBIF_CFG_DEV0_EPF0_VF22_1_BASE_ADDR_6 0xfffe10316024 #define cfgBIF_CFG_DEV0_EPF0_VF22_1_CARDBUS_CIS_PTR 0xfffe10316028 #define cfgBIF_CFG_DEV0_EPF0_VF22_1_ADAPTER_ID 0xfffe1031602c #define cfgBIF_CFG_DEV0_EPF0_VF22_1_ROM_BASE_ADDR 0xfffe10316030 #define cfgBIF_CFG_DEV0_EPF0_VF22_1_CAP_PTR 0xfffe10316034 #define cfgBIF_CFG_DEV0_EPF0_VF22_1_INTERRUPT_LINE 0xfffe1031603c #define cfgBIF_CFG_DEV0_EPF0_VF22_1_INTERRUPT_PIN 0xfffe1031603d #define cfgBIF_CFG_DEV0_EPF0_VF22_1_MIN_GRANT 0xfffe1031603e #define cfgBIF_CFG_DEV0_EPF0_VF22_1_MAX_LATENCY 0xfffe1031603f #define cfgBIF_CFG_DEV0_EPF0_VF22_1_PCIE_CAP_LIST 0xfffe10316064 #define cfgBIF_CFG_DEV0_EPF0_VF22_1_PCIE_CAP 0xfffe10316066 #define cfgBIF_CFG_DEV0_EPF0_VF22_1_DEVICE_CAP 0xfffe10316068 #define cfgBIF_CFG_DEV0_EPF0_VF22_1_DEVICE_CNTL 0xfffe1031606c #define cfgBIF_CFG_DEV0_EPF0_VF22_1_DEVICE_STATUS 0xfffe1031606e #define cfgBIF_CFG_DEV0_EPF0_VF22_1_LINK_CAP 0xfffe10316070 #define cfgBIF_CFG_DEV0_EPF0_VF22_1_LINK_CNTL 0xfffe10316074 #define cfgBIF_CFG_DEV0_EPF0_VF22_1_LINK_STATUS 0xfffe10316076 #define cfgBIF_CFG_DEV0_EPF0_VF22_1_DEVICE_CAP2 0xfffe10316088 #define cfgBIF_CFG_DEV0_EPF0_VF22_1_DEVICE_CNTL2 0xfffe1031608c #define cfgBIF_CFG_DEV0_EPF0_VF22_1_DEVICE_STATUS2 0xfffe1031608e #define cfgBIF_CFG_DEV0_EPF0_VF22_1_LINK_CAP2 0xfffe10316090 #define cfgBIF_CFG_DEV0_EPF0_VF22_1_LINK_CNTL2 0xfffe10316094 #define cfgBIF_CFG_DEV0_EPF0_VF22_1_LINK_STATUS2 0xfffe10316096 #define cfgBIF_CFG_DEV0_EPF0_VF22_1_MSI_CAP_LIST 0xfffe103160a0 #define cfgBIF_CFG_DEV0_EPF0_VF22_1_MSI_MSG_CNTL 0xfffe103160a2 #define cfgBIF_CFG_DEV0_EPF0_VF22_1_MSI_MSG_ADDR_LO 0xfffe103160a4 #define cfgBIF_CFG_DEV0_EPF0_VF22_1_MSI_MSG_ADDR_HI 0xfffe103160a8 #define cfgBIF_CFG_DEV0_EPF0_VF22_1_MSI_MSG_DATA 0xfffe103160a8 #define cfgBIF_CFG_DEV0_EPF0_VF22_1_MSI_MASK 0xfffe103160ac #define cfgBIF_CFG_DEV0_EPF0_VF22_1_MSI_MSG_DATA_64 0xfffe103160ac #define cfgBIF_CFG_DEV0_EPF0_VF22_1_MSI_MASK_64 0xfffe103160b0 #define cfgBIF_CFG_DEV0_EPF0_VF22_1_MSI_PENDING 0xfffe103160b0 #define cfgBIF_CFG_DEV0_EPF0_VF22_1_MSI_PENDING_64 0xfffe103160b4 #define cfgBIF_CFG_DEV0_EPF0_VF22_1_MSIX_CAP_LIST 0xfffe103160c0 #define cfgBIF_CFG_DEV0_EPF0_VF22_1_MSIX_MSG_CNTL 0xfffe103160c2 #define cfgBIF_CFG_DEV0_EPF0_VF22_1_MSIX_TABLE 0xfffe103160c4 #define cfgBIF_CFG_DEV0_EPF0_VF22_1_MSIX_PBA 0xfffe103160c8 #define cfgBIF_CFG_DEV0_EPF0_VF22_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0xfffe10316100 #define cfgBIF_CFG_DEV0_EPF0_VF22_1_PCIE_VENDOR_SPECIFIC_HDR 0xfffe10316104 #define cfgBIF_CFG_DEV0_EPF0_VF22_1_PCIE_VENDOR_SPECIFIC1 0xfffe10316108 #define cfgBIF_CFG_DEV0_EPF0_VF22_1_PCIE_VENDOR_SPECIFIC2 0xfffe1031610c #define cfgBIF_CFG_DEV0_EPF0_VF22_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0xfffe10316150 #define cfgBIF_CFG_DEV0_EPF0_VF22_1_PCIE_UNCORR_ERR_STATUS 0xfffe10316154 #define cfgBIF_CFG_DEV0_EPF0_VF22_1_PCIE_UNCORR_ERR_MASK 0xfffe10316158 #define cfgBIF_CFG_DEV0_EPF0_VF22_1_PCIE_UNCORR_ERR_SEVERITY 0xfffe1031615c #define cfgBIF_CFG_DEV0_EPF0_VF22_1_PCIE_CORR_ERR_STATUS 0xfffe10316160 #define cfgBIF_CFG_DEV0_EPF0_VF22_1_PCIE_CORR_ERR_MASK 0xfffe10316164 #define cfgBIF_CFG_DEV0_EPF0_VF22_1_PCIE_ADV_ERR_CAP_CNTL 0xfffe10316168 #define cfgBIF_CFG_DEV0_EPF0_VF22_1_PCIE_HDR_LOG0 0xfffe1031616c #define cfgBIF_CFG_DEV0_EPF0_VF22_1_PCIE_HDR_LOG1 0xfffe10316170 #define cfgBIF_CFG_DEV0_EPF0_VF22_1_PCIE_HDR_LOG2 0xfffe10316174 #define cfgBIF_CFG_DEV0_EPF0_VF22_1_PCIE_HDR_LOG3 0xfffe10316178 #define cfgBIF_CFG_DEV0_EPF0_VF22_1_PCIE_TLP_PREFIX_LOG0 0xfffe10316188 #define cfgBIF_CFG_DEV0_EPF0_VF22_1_PCIE_TLP_PREFIX_LOG1 0xfffe1031618c #define cfgBIF_CFG_DEV0_EPF0_VF22_1_PCIE_TLP_PREFIX_LOG2 0xfffe10316190 #define cfgBIF_CFG_DEV0_EPF0_VF22_1_PCIE_TLP_PREFIX_LOG3 0xfffe10316194 #define cfgBIF_CFG_DEV0_EPF0_VF22_1_PCIE_ATS_ENH_CAP_LIST 0xfffe103162b0 #define cfgBIF_CFG_DEV0_EPF0_VF22_1_PCIE_ATS_CAP 0xfffe103162b4 #define cfgBIF_CFG_DEV0_EPF0_VF22_1_PCIE_ATS_CNTL 0xfffe103162b6 #define cfgBIF_CFG_DEV0_EPF0_VF22_1_PCIE_ARI_ENH_CAP_LIST 0xfffe10316328 #define cfgBIF_CFG_DEV0_EPF0_VF22_1_PCIE_ARI_CAP 0xfffe1031632c #define cfgBIF_CFG_DEV0_EPF0_VF22_1_PCIE_ARI_CNTL 0xfffe1031632e // addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf23_bifcfgdecp // base address: 0xfffe10317000 #define cfgBIF_CFG_DEV0_EPF0_VF23_1_VENDOR_ID 0xfffe10317000 #define cfgBIF_CFG_DEV0_EPF0_VF23_1_DEVICE_ID 0xfffe10317002 #define cfgBIF_CFG_DEV0_EPF0_VF23_1_COMMAND 0xfffe10317004 #define cfgBIF_CFG_DEV0_EPF0_VF23_1_STATUS 0xfffe10317006 #define cfgBIF_CFG_DEV0_EPF0_VF23_1_REVISION_ID 0xfffe10317008 #define cfgBIF_CFG_DEV0_EPF0_VF23_1_PROG_INTERFACE 0xfffe10317009 #define cfgBIF_CFG_DEV0_EPF0_VF23_1_SUB_CLASS 0xfffe1031700a #define cfgBIF_CFG_DEV0_EPF0_VF23_1_BASE_CLASS 0xfffe1031700b #define cfgBIF_CFG_DEV0_EPF0_VF23_1_CACHE_LINE 0xfffe1031700c #define cfgBIF_CFG_DEV0_EPF0_VF23_1_LATENCY 0xfffe1031700d #define cfgBIF_CFG_DEV0_EPF0_VF23_1_HEADER 0xfffe1031700e #define cfgBIF_CFG_DEV0_EPF0_VF23_1_BIST 0xfffe1031700f #define cfgBIF_CFG_DEV0_EPF0_VF23_1_BASE_ADDR_1 0xfffe10317010 #define cfgBIF_CFG_DEV0_EPF0_VF23_1_BASE_ADDR_2 0xfffe10317014 #define cfgBIF_CFG_DEV0_EPF0_VF23_1_BASE_ADDR_3 0xfffe10317018 #define cfgBIF_CFG_DEV0_EPF0_VF23_1_BASE_ADDR_4 0xfffe1031701c #define cfgBIF_CFG_DEV0_EPF0_VF23_1_BASE_ADDR_5 0xfffe10317020 #define cfgBIF_CFG_DEV0_EPF0_VF23_1_BASE_ADDR_6 0xfffe10317024 #define cfgBIF_CFG_DEV0_EPF0_VF23_1_CARDBUS_CIS_PTR 0xfffe10317028 #define cfgBIF_CFG_DEV0_EPF0_VF23_1_ADAPTER_ID 0xfffe1031702c #define cfgBIF_CFG_DEV0_EPF0_VF23_1_ROM_BASE_ADDR 0xfffe10317030 #define cfgBIF_CFG_DEV0_EPF0_VF23_1_CAP_PTR 0xfffe10317034 #define cfgBIF_CFG_DEV0_EPF0_VF23_1_INTERRUPT_LINE 0xfffe1031703c #define cfgBIF_CFG_DEV0_EPF0_VF23_1_INTERRUPT_PIN 0xfffe1031703d #define cfgBIF_CFG_DEV0_EPF0_VF23_1_MIN_GRANT 0xfffe1031703e #define cfgBIF_CFG_DEV0_EPF0_VF23_1_MAX_LATENCY 0xfffe1031703f #define cfgBIF_CFG_DEV0_EPF0_VF23_1_PCIE_CAP_LIST 0xfffe10317064 #define cfgBIF_CFG_DEV0_EPF0_VF23_1_PCIE_CAP 0xfffe10317066 #define cfgBIF_CFG_DEV0_EPF0_VF23_1_DEVICE_CAP 0xfffe10317068 #define cfgBIF_CFG_DEV0_EPF0_VF23_1_DEVICE_CNTL 0xfffe1031706c #define cfgBIF_CFG_DEV0_EPF0_VF23_1_DEVICE_STATUS 0xfffe1031706e #define cfgBIF_CFG_DEV0_EPF0_VF23_1_LINK_CAP 0xfffe10317070 #define cfgBIF_CFG_DEV0_EPF0_VF23_1_LINK_CNTL 0xfffe10317074 #define cfgBIF_CFG_DEV0_EPF0_VF23_1_LINK_STATUS 0xfffe10317076 #define cfgBIF_CFG_DEV0_EPF0_VF23_1_DEVICE_CAP2 0xfffe10317088 #define cfgBIF_CFG_DEV0_EPF0_VF23_1_DEVICE_CNTL2 0xfffe1031708c #define cfgBIF_CFG_DEV0_EPF0_VF23_1_DEVICE_STATUS2 0xfffe1031708e #define cfgBIF_CFG_DEV0_EPF0_VF23_1_LINK_CAP2 0xfffe10317090 #define cfgBIF_CFG_DEV0_EPF0_VF23_1_LINK_CNTL2 0xfffe10317094 #define cfgBIF_CFG_DEV0_EPF0_VF23_1_LINK_STATUS2 0xfffe10317096 #define cfgBIF_CFG_DEV0_EPF0_VF23_1_MSI_CAP_LIST 0xfffe103170a0 #define cfgBIF_CFG_DEV0_EPF0_VF23_1_MSI_MSG_CNTL 0xfffe103170a2 #define cfgBIF_CFG_DEV0_EPF0_VF23_1_MSI_MSG_ADDR_LO 0xfffe103170a4 #define cfgBIF_CFG_DEV0_EPF0_VF23_1_MSI_MSG_ADDR_HI 0xfffe103170a8 #define cfgBIF_CFG_DEV0_EPF0_VF23_1_MSI_MSG_DATA 0xfffe103170a8 #define cfgBIF_CFG_DEV0_EPF0_VF23_1_MSI_MASK 0xfffe103170ac #define cfgBIF_CFG_DEV0_EPF0_VF23_1_MSI_MSG_DATA_64 0xfffe103170ac #define cfgBIF_CFG_DEV0_EPF0_VF23_1_MSI_MASK_64 0xfffe103170b0 #define cfgBIF_CFG_DEV0_EPF0_VF23_1_MSI_PENDING 0xfffe103170b0 #define cfgBIF_CFG_DEV0_EPF0_VF23_1_MSI_PENDING_64 0xfffe103170b4 #define cfgBIF_CFG_DEV0_EPF0_VF23_1_MSIX_CAP_LIST 0xfffe103170c0 #define cfgBIF_CFG_DEV0_EPF0_VF23_1_MSIX_MSG_CNTL 0xfffe103170c2 #define cfgBIF_CFG_DEV0_EPF0_VF23_1_MSIX_TABLE 0xfffe103170c4 #define cfgBIF_CFG_DEV0_EPF0_VF23_1_MSIX_PBA 0xfffe103170c8 #define cfgBIF_CFG_DEV0_EPF0_VF23_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0xfffe10317100 #define cfgBIF_CFG_DEV0_EPF0_VF23_1_PCIE_VENDOR_SPECIFIC_HDR 0xfffe10317104 #define cfgBIF_CFG_DEV0_EPF0_VF23_1_PCIE_VENDOR_SPECIFIC1 0xfffe10317108 #define cfgBIF_CFG_DEV0_EPF0_VF23_1_PCIE_VENDOR_SPECIFIC2 0xfffe1031710c #define cfgBIF_CFG_DEV0_EPF0_VF23_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0xfffe10317150 #define cfgBIF_CFG_DEV0_EPF0_VF23_1_PCIE_UNCORR_ERR_STATUS 0xfffe10317154 #define cfgBIF_CFG_DEV0_EPF0_VF23_1_PCIE_UNCORR_ERR_MASK 0xfffe10317158 #define cfgBIF_CFG_DEV0_EPF0_VF23_1_PCIE_UNCORR_ERR_SEVERITY 0xfffe1031715c #define cfgBIF_CFG_DEV0_EPF0_VF23_1_PCIE_CORR_ERR_STATUS 0xfffe10317160 #define cfgBIF_CFG_DEV0_EPF0_VF23_1_PCIE_CORR_ERR_MASK 0xfffe10317164 #define cfgBIF_CFG_DEV0_EPF0_VF23_1_PCIE_ADV_ERR_CAP_CNTL 0xfffe10317168 #define cfgBIF_CFG_DEV0_EPF0_VF23_1_PCIE_HDR_LOG0 0xfffe1031716c #define cfgBIF_CFG_DEV0_EPF0_VF23_1_PCIE_HDR_LOG1 0xfffe10317170 #define cfgBIF_CFG_DEV0_EPF0_VF23_1_PCIE_HDR_LOG2 0xfffe10317174 #define cfgBIF_CFG_DEV0_EPF0_VF23_1_PCIE_HDR_LOG3 0xfffe10317178 #define cfgBIF_CFG_DEV0_EPF0_VF23_1_PCIE_TLP_PREFIX_LOG0 0xfffe10317188 #define cfgBIF_CFG_DEV0_EPF0_VF23_1_PCIE_TLP_PREFIX_LOG1 0xfffe1031718c #define cfgBIF_CFG_DEV0_EPF0_VF23_1_PCIE_TLP_PREFIX_LOG2 0xfffe10317190 #define cfgBIF_CFG_DEV0_EPF0_VF23_1_PCIE_TLP_PREFIX_LOG3 0xfffe10317194 #define cfgBIF_CFG_DEV0_EPF0_VF23_1_PCIE_ATS_ENH_CAP_LIST 0xfffe103172b0 #define cfgBIF_CFG_DEV0_EPF0_VF23_1_PCIE_ATS_CAP 0xfffe103172b4 #define cfgBIF_CFG_DEV0_EPF0_VF23_1_PCIE_ATS_CNTL 0xfffe103172b6 #define cfgBIF_CFG_DEV0_EPF0_VF23_1_PCIE_ARI_ENH_CAP_LIST 0xfffe10317328 #define cfgBIF_CFG_DEV0_EPF0_VF23_1_PCIE_ARI_CAP 0xfffe1031732c #define cfgBIF_CFG_DEV0_EPF0_VF23_1_PCIE_ARI_CNTL 0xfffe1031732e // addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf24_bifcfgdecp // base address: 0xfffe10318000 #define cfgBIF_CFG_DEV0_EPF0_VF24_1_VENDOR_ID 0xfffe10318000 #define cfgBIF_CFG_DEV0_EPF0_VF24_1_DEVICE_ID 0xfffe10318002 #define cfgBIF_CFG_DEV0_EPF0_VF24_1_COMMAND 0xfffe10318004 #define cfgBIF_CFG_DEV0_EPF0_VF24_1_STATUS 0xfffe10318006 #define cfgBIF_CFG_DEV0_EPF0_VF24_1_REVISION_ID 0xfffe10318008 #define cfgBIF_CFG_DEV0_EPF0_VF24_1_PROG_INTERFACE 0xfffe10318009 #define cfgBIF_CFG_DEV0_EPF0_VF24_1_SUB_CLASS 0xfffe1031800a #define cfgBIF_CFG_DEV0_EPF0_VF24_1_BASE_CLASS 0xfffe1031800b #define cfgBIF_CFG_DEV0_EPF0_VF24_1_CACHE_LINE 0xfffe1031800c #define cfgBIF_CFG_DEV0_EPF0_VF24_1_LATENCY 0xfffe1031800d #define cfgBIF_CFG_DEV0_EPF0_VF24_1_HEADER 0xfffe1031800e #define cfgBIF_CFG_DEV0_EPF0_VF24_1_BIST 0xfffe1031800f #define cfgBIF_CFG_DEV0_EPF0_VF24_1_BASE_ADDR_1 0xfffe10318010 #define cfgBIF_CFG_DEV0_EPF0_VF24_1_BASE_ADDR_2 0xfffe10318014 #define cfgBIF_CFG_DEV0_EPF0_VF24_1_BASE_ADDR_3 0xfffe10318018 #define cfgBIF_CFG_DEV0_EPF0_VF24_1_BASE_ADDR_4 0xfffe1031801c #define cfgBIF_CFG_DEV0_EPF0_VF24_1_BASE_ADDR_5 0xfffe10318020 #define cfgBIF_CFG_DEV0_EPF0_VF24_1_BASE_ADDR_6 0xfffe10318024 #define cfgBIF_CFG_DEV0_EPF0_VF24_1_CARDBUS_CIS_PTR 0xfffe10318028 #define cfgBIF_CFG_DEV0_EPF0_VF24_1_ADAPTER_ID 0xfffe1031802c #define cfgBIF_CFG_DEV0_EPF0_VF24_1_ROM_BASE_ADDR 0xfffe10318030 #define cfgBIF_CFG_DEV0_EPF0_VF24_1_CAP_PTR 0xfffe10318034 #define cfgBIF_CFG_DEV0_EPF0_VF24_1_INTERRUPT_LINE 0xfffe1031803c #define cfgBIF_CFG_DEV0_EPF0_VF24_1_INTERRUPT_PIN 0xfffe1031803d #define cfgBIF_CFG_DEV0_EPF0_VF24_1_MIN_GRANT 0xfffe1031803e #define cfgBIF_CFG_DEV0_EPF0_VF24_1_MAX_LATENCY 0xfffe1031803f #define cfgBIF_CFG_DEV0_EPF0_VF24_1_PCIE_CAP_LIST 0xfffe10318064 #define cfgBIF_CFG_DEV0_EPF0_VF24_1_PCIE_CAP 0xfffe10318066 #define cfgBIF_CFG_DEV0_EPF0_VF24_1_DEVICE_CAP 0xfffe10318068 #define cfgBIF_CFG_DEV0_EPF0_VF24_1_DEVICE_CNTL 0xfffe1031806c #define cfgBIF_CFG_DEV0_EPF0_VF24_1_DEVICE_STATUS 0xfffe1031806e #define cfgBIF_CFG_DEV0_EPF0_VF24_1_LINK_CAP 0xfffe10318070 #define cfgBIF_CFG_DEV0_EPF0_VF24_1_LINK_CNTL 0xfffe10318074 #define cfgBIF_CFG_DEV0_EPF0_VF24_1_LINK_STATUS 0xfffe10318076 #define cfgBIF_CFG_DEV0_EPF0_VF24_1_DEVICE_CAP2 0xfffe10318088 #define cfgBIF_CFG_DEV0_EPF0_VF24_1_DEVICE_CNTL2 0xfffe1031808c #define cfgBIF_CFG_DEV0_EPF0_VF24_1_DEVICE_STATUS2 0xfffe1031808e #define cfgBIF_CFG_DEV0_EPF0_VF24_1_LINK_CAP2 0xfffe10318090 #define cfgBIF_CFG_DEV0_EPF0_VF24_1_LINK_CNTL2 0xfffe10318094 #define cfgBIF_CFG_DEV0_EPF0_VF24_1_LINK_STATUS2 0xfffe10318096 #define cfgBIF_CFG_DEV0_EPF0_VF24_1_MSI_CAP_LIST 0xfffe103180a0 #define cfgBIF_CFG_DEV0_EPF0_VF24_1_MSI_MSG_CNTL 0xfffe103180a2 #define cfgBIF_CFG_DEV0_EPF0_VF24_1_MSI_MSG_ADDR_LO 0xfffe103180a4 #define cfgBIF_CFG_DEV0_EPF0_VF24_1_MSI_MSG_ADDR_HI 0xfffe103180a8 #define cfgBIF_CFG_DEV0_EPF0_VF24_1_MSI_MSG_DATA 0xfffe103180a8 #define cfgBIF_CFG_DEV0_EPF0_VF24_1_MSI_MASK 0xfffe103180ac #define cfgBIF_CFG_DEV0_EPF0_VF24_1_MSI_MSG_DATA_64 0xfffe103180ac #define cfgBIF_CFG_DEV0_EPF0_VF24_1_MSI_MASK_64 0xfffe103180b0 #define cfgBIF_CFG_DEV0_EPF0_VF24_1_MSI_PENDING 0xfffe103180b0 #define cfgBIF_CFG_DEV0_EPF0_VF24_1_MSI_PENDING_64 0xfffe103180b4 #define cfgBIF_CFG_DEV0_EPF0_VF24_1_MSIX_CAP_LIST 0xfffe103180c0 #define cfgBIF_CFG_DEV0_EPF0_VF24_1_MSIX_MSG_CNTL 0xfffe103180c2 #define cfgBIF_CFG_DEV0_EPF0_VF24_1_MSIX_TABLE 0xfffe103180c4 #define cfgBIF_CFG_DEV0_EPF0_VF24_1_MSIX_PBA 0xfffe103180c8 #define cfgBIF_CFG_DEV0_EPF0_VF24_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0xfffe10318100 #define cfgBIF_CFG_DEV0_EPF0_VF24_1_PCIE_VENDOR_SPECIFIC_HDR 0xfffe10318104 #define cfgBIF_CFG_DEV0_EPF0_VF24_1_PCIE_VENDOR_SPECIFIC1 0xfffe10318108 #define cfgBIF_CFG_DEV0_EPF0_VF24_1_PCIE_VENDOR_SPECIFIC2 0xfffe1031810c #define cfgBIF_CFG_DEV0_EPF0_VF24_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0xfffe10318150 #define cfgBIF_CFG_DEV0_EPF0_VF24_1_PCIE_UNCORR_ERR_STATUS 0xfffe10318154 #define cfgBIF_CFG_DEV0_EPF0_VF24_1_PCIE_UNCORR_ERR_MASK 0xfffe10318158 #define cfgBIF_CFG_DEV0_EPF0_VF24_1_PCIE_UNCORR_ERR_SEVERITY 0xfffe1031815c #define cfgBIF_CFG_DEV0_EPF0_VF24_1_PCIE_CORR_ERR_STATUS 0xfffe10318160 #define cfgBIF_CFG_DEV0_EPF0_VF24_1_PCIE_CORR_ERR_MASK 0xfffe10318164 #define cfgBIF_CFG_DEV0_EPF0_VF24_1_PCIE_ADV_ERR_CAP_CNTL 0xfffe10318168 #define cfgBIF_CFG_DEV0_EPF0_VF24_1_PCIE_HDR_LOG0 0xfffe1031816c #define cfgBIF_CFG_DEV0_EPF0_VF24_1_PCIE_HDR_LOG1 0xfffe10318170 #define cfgBIF_CFG_DEV0_EPF0_VF24_1_PCIE_HDR_LOG2 0xfffe10318174 #define cfgBIF_CFG_DEV0_EPF0_VF24_1_PCIE_HDR_LOG3 0xfffe10318178 #define cfgBIF_CFG_DEV0_EPF0_VF24_1_PCIE_TLP_PREFIX_LOG0 0xfffe10318188 #define cfgBIF_CFG_DEV0_EPF0_VF24_1_PCIE_TLP_PREFIX_LOG1 0xfffe1031818c #define cfgBIF_CFG_DEV0_EPF0_VF24_1_PCIE_TLP_PREFIX_LOG2 0xfffe10318190 #define cfgBIF_CFG_DEV0_EPF0_VF24_1_PCIE_TLP_PREFIX_LOG3 0xfffe10318194 #define cfgBIF_CFG_DEV0_EPF0_VF24_1_PCIE_ATS_ENH_CAP_LIST 0xfffe103182b0 #define cfgBIF_CFG_DEV0_EPF0_VF24_1_PCIE_ATS_CAP 0xfffe103182b4 #define cfgBIF_CFG_DEV0_EPF0_VF24_1_PCIE_ATS_CNTL 0xfffe103182b6 #define cfgBIF_CFG_DEV0_EPF0_VF24_1_PCIE_ARI_ENH_CAP_LIST 0xfffe10318328 #define cfgBIF_CFG_DEV0_EPF0_VF24_1_PCIE_ARI_CAP 0xfffe1031832c #define cfgBIF_CFG_DEV0_EPF0_VF24_1_PCIE_ARI_CNTL 0xfffe1031832e // addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf25_bifcfgdecp // base address: 0xfffe10319000 #define cfgBIF_CFG_DEV0_EPF0_VF25_1_VENDOR_ID 0xfffe10319000 #define cfgBIF_CFG_DEV0_EPF0_VF25_1_DEVICE_ID 0xfffe10319002 #define cfgBIF_CFG_DEV0_EPF0_VF25_1_COMMAND 0xfffe10319004 #define cfgBIF_CFG_DEV0_EPF0_VF25_1_STATUS 0xfffe10319006 #define cfgBIF_CFG_DEV0_EPF0_VF25_1_REVISION_ID 0xfffe10319008 #define cfgBIF_CFG_DEV0_EPF0_VF25_1_PROG_INTERFACE 0xfffe10319009 #define cfgBIF_CFG_DEV0_EPF0_VF25_1_SUB_CLASS 0xfffe1031900a #define cfgBIF_CFG_DEV0_EPF0_VF25_1_BASE_CLASS 0xfffe1031900b #define cfgBIF_CFG_DEV0_EPF0_VF25_1_CACHE_LINE 0xfffe1031900c #define cfgBIF_CFG_DEV0_EPF0_VF25_1_LATENCY 0xfffe1031900d #define cfgBIF_CFG_DEV0_EPF0_VF25_1_HEADER 0xfffe1031900e #define cfgBIF_CFG_DEV0_EPF0_VF25_1_BIST 0xfffe1031900f #define cfgBIF_CFG_DEV0_EPF0_VF25_1_BASE_ADDR_1 0xfffe10319010 #define cfgBIF_CFG_DEV0_EPF0_VF25_1_BASE_ADDR_2 0xfffe10319014 #define cfgBIF_CFG_DEV0_EPF0_VF25_1_BASE_ADDR_3 0xfffe10319018 #define cfgBIF_CFG_DEV0_EPF0_VF25_1_BASE_ADDR_4 0xfffe1031901c #define cfgBIF_CFG_DEV0_EPF0_VF25_1_BASE_ADDR_5 0xfffe10319020 #define cfgBIF_CFG_DEV0_EPF0_VF25_1_BASE_ADDR_6 0xfffe10319024 #define cfgBIF_CFG_DEV0_EPF0_VF25_1_CARDBUS_CIS_PTR 0xfffe10319028 #define cfgBIF_CFG_DEV0_EPF0_VF25_1_ADAPTER_ID 0xfffe1031902c #define cfgBIF_CFG_DEV0_EPF0_VF25_1_ROM_BASE_ADDR 0xfffe10319030 #define cfgBIF_CFG_DEV0_EPF0_VF25_1_CAP_PTR 0xfffe10319034 #define cfgBIF_CFG_DEV0_EPF0_VF25_1_INTERRUPT_LINE 0xfffe1031903c #define cfgBIF_CFG_DEV0_EPF0_VF25_1_INTERRUPT_PIN 0xfffe1031903d #define cfgBIF_CFG_DEV0_EPF0_VF25_1_MIN_GRANT 0xfffe1031903e #define cfgBIF_CFG_DEV0_EPF0_VF25_1_MAX_LATENCY 0xfffe1031903f #define cfgBIF_CFG_DEV0_EPF0_VF25_1_PCIE_CAP_LIST 0xfffe10319064 #define cfgBIF_CFG_DEV0_EPF0_VF25_1_PCIE_CAP 0xfffe10319066 #define cfgBIF_CFG_DEV0_EPF0_VF25_1_DEVICE_CAP 0xfffe10319068 #define cfgBIF_CFG_DEV0_EPF0_VF25_1_DEVICE_CNTL 0xfffe1031906c #define cfgBIF_CFG_DEV0_EPF0_VF25_1_DEVICE_STATUS 0xfffe1031906e #define cfgBIF_CFG_DEV0_EPF0_VF25_1_LINK_CAP 0xfffe10319070 #define cfgBIF_CFG_DEV0_EPF0_VF25_1_LINK_CNTL 0xfffe10319074 #define cfgBIF_CFG_DEV0_EPF0_VF25_1_LINK_STATUS 0xfffe10319076 #define cfgBIF_CFG_DEV0_EPF0_VF25_1_DEVICE_CAP2 0xfffe10319088 #define cfgBIF_CFG_DEV0_EPF0_VF25_1_DEVICE_CNTL2 0xfffe1031908c #define cfgBIF_CFG_DEV0_EPF0_VF25_1_DEVICE_STATUS2 0xfffe1031908e #define cfgBIF_CFG_DEV0_EPF0_VF25_1_LINK_CAP2 0xfffe10319090 #define cfgBIF_CFG_DEV0_EPF0_VF25_1_LINK_CNTL2 0xfffe10319094 #define cfgBIF_CFG_DEV0_EPF0_VF25_1_LINK_STATUS2 0xfffe10319096 #define cfgBIF_CFG_DEV0_EPF0_VF25_1_MSI_CAP_LIST 0xfffe103190a0 #define cfgBIF_CFG_DEV0_EPF0_VF25_1_MSI_MSG_CNTL 0xfffe103190a2 #define cfgBIF_CFG_DEV0_EPF0_VF25_1_MSI_MSG_ADDR_LO 0xfffe103190a4 #define cfgBIF_CFG_DEV0_EPF0_VF25_1_MSI_MSG_ADDR_HI 0xfffe103190a8 #define cfgBIF_CFG_DEV0_EPF0_VF25_1_MSI_MSG_DATA 0xfffe103190a8 #define cfgBIF_CFG_DEV0_EPF0_VF25_1_MSI_MASK 0xfffe103190ac #define cfgBIF_CFG_DEV0_EPF0_VF25_1_MSI_MSG_DATA_64 0xfffe103190ac #define cfgBIF_CFG_DEV0_EPF0_VF25_1_MSI_MASK_64 0xfffe103190b0 #define cfgBIF_CFG_DEV0_EPF0_VF25_1_MSI_PENDING 0xfffe103190b0 #define cfgBIF_CFG_DEV0_EPF0_VF25_1_MSI_PENDING_64 0xfffe103190b4 #define cfgBIF_CFG_DEV0_EPF0_VF25_1_MSIX_CAP_LIST 0xfffe103190c0 #define cfgBIF_CFG_DEV0_EPF0_VF25_1_MSIX_MSG_CNTL 0xfffe103190c2 #define cfgBIF_CFG_DEV0_EPF0_VF25_1_MSIX_TABLE 0xfffe103190c4 #define cfgBIF_CFG_DEV0_EPF0_VF25_1_MSIX_PBA 0xfffe103190c8 #define cfgBIF_CFG_DEV0_EPF0_VF25_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0xfffe10319100 #define cfgBIF_CFG_DEV0_EPF0_VF25_1_PCIE_VENDOR_SPECIFIC_HDR 0xfffe10319104 #define cfgBIF_CFG_DEV0_EPF0_VF25_1_PCIE_VENDOR_SPECIFIC1 0xfffe10319108 #define cfgBIF_CFG_DEV0_EPF0_VF25_1_PCIE_VENDOR_SPECIFIC2 0xfffe1031910c #define cfgBIF_CFG_DEV0_EPF0_VF25_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0xfffe10319150 #define cfgBIF_CFG_DEV0_EPF0_VF25_1_PCIE_UNCORR_ERR_STATUS 0xfffe10319154 #define cfgBIF_CFG_DEV0_EPF0_VF25_1_PCIE_UNCORR_ERR_MASK 0xfffe10319158 #define cfgBIF_CFG_DEV0_EPF0_VF25_1_PCIE_UNCORR_ERR_SEVERITY 0xfffe1031915c #define cfgBIF_CFG_DEV0_EPF0_VF25_1_PCIE_CORR_ERR_STATUS 0xfffe10319160 #define cfgBIF_CFG_DEV0_EPF0_VF25_1_PCIE_CORR_ERR_MASK 0xfffe10319164 #define cfgBIF_CFG_DEV0_EPF0_VF25_1_PCIE_ADV_ERR_CAP_CNTL 0xfffe10319168 #define cfgBIF_CFG_DEV0_EPF0_VF25_1_PCIE_HDR_LOG0 0xfffe1031916c #define cfgBIF_CFG_DEV0_EPF0_VF25_1_PCIE_HDR_LOG1 0xfffe10319170 #define cfgBIF_CFG_DEV0_EPF0_VF25_1_PCIE_HDR_LOG2 0xfffe10319174 #define cfgBIF_CFG_DEV0_EPF0_VF25_1_PCIE_HDR_LOG3 0xfffe10319178 #define cfgBIF_CFG_DEV0_EPF0_VF25_1_PCIE_TLP_PREFIX_LOG0 0xfffe10319188 #define cfgBIF_CFG_DEV0_EPF0_VF25_1_PCIE_TLP_PREFIX_LOG1 0xfffe1031918c #define cfgBIF_CFG_DEV0_EPF0_VF25_1_PCIE_TLP_PREFIX_LOG2 0xfffe10319190 #define cfgBIF_CFG_DEV0_EPF0_VF25_1_PCIE_TLP_PREFIX_LOG3 0xfffe10319194 #define cfgBIF_CFG_DEV0_EPF0_VF25_1_PCIE_ATS_ENH_CAP_LIST 0xfffe103192b0 #define cfgBIF_CFG_DEV0_EPF0_VF25_1_PCIE_ATS_CAP 0xfffe103192b4 #define cfgBIF_CFG_DEV0_EPF0_VF25_1_PCIE_ATS_CNTL 0xfffe103192b6 #define cfgBIF_CFG_DEV0_EPF0_VF25_1_PCIE_ARI_ENH_CAP_LIST 0xfffe10319328 #define cfgBIF_CFG_DEV0_EPF0_VF25_1_PCIE_ARI_CAP 0xfffe1031932c #define cfgBIF_CFG_DEV0_EPF0_VF25_1_PCIE_ARI_CNTL 0xfffe1031932e // addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf26_bifcfgdecp // base address: 0xfffe1031a000 #define cfgBIF_CFG_DEV0_EPF0_VF26_1_VENDOR_ID 0xfffe1031a000 #define cfgBIF_CFG_DEV0_EPF0_VF26_1_DEVICE_ID 0xfffe1031a002 #define cfgBIF_CFG_DEV0_EPF0_VF26_1_COMMAND 0xfffe1031a004 #define cfgBIF_CFG_DEV0_EPF0_VF26_1_STATUS 0xfffe1031a006 #define cfgBIF_CFG_DEV0_EPF0_VF26_1_REVISION_ID 0xfffe1031a008 #define cfgBIF_CFG_DEV0_EPF0_VF26_1_PROG_INTERFACE 0xfffe1031a009 #define cfgBIF_CFG_DEV0_EPF0_VF26_1_SUB_CLASS 0xfffe1031a00a #define cfgBIF_CFG_DEV0_EPF0_VF26_1_BASE_CLASS 0xfffe1031a00b #define cfgBIF_CFG_DEV0_EPF0_VF26_1_CACHE_LINE 0xfffe1031a00c #define cfgBIF_CFG_DEV0_EPF0_VF26_1_LATENCY 0xfffe1031a00d #define cfgBIF_CFG_DEV0_EPF0_VF26_1_HEADER 0xfffe1031a00e #define cfgBIF_CFG_DEV0_EPF0_VF26_1_BIST 0xfffe1031a00f #define cfgBIF_CFG_DEV0_EPF0_VF26_1_BASE_ADDR_1 0xfffe1031a010 #define cfgBIF_CFG_DEV0_EPF0_VF26_1_BASE_ADDR_2 0xfffe1031a014 #define cfgBIF_CFG_DEV0_EPF0_VF26_1_BASE_ADDR_3 0xfffe1031a018 #define cfgBIF_CFG_DEV0_EPF0_VF26_1_BASE_ADDR_4 0xfffe1031a01c #define cfgBIF_CFG_DEV0_EPF0_VF26_1_BASE_ADDR_5 0xfffe1031a020 #define cfgBIF_CFG_DEV0_EPF0_VF26_1_BASE_ADDR_6 0xfffe1031a024 #define cfgBIF_CFG_DEV0_EPF0_VF26_1_CARDBUS_CIS_PTR 0xfffe1031a028 #define cfgBIF_CFG_DEV0_EPF0_VF26_1_ADAPTER_ID 0xfffe1031a02c #define cfgBIF_CFG_DEV0_EPF0_VF26_1_ROM_BASE_ADDR 0xfffe1031a030 #define cfgBIF_CFG_DEV0_EPF0_VF26_1_CAP_PTR 0xfffe1031a034 #define cfgBIF_CFG_DEV0_EPF0_VF26_1_INTERRUPT_LINE 0xfffe1031a03c #define cfgBIF_CFG_DEV0_EPF0_VF26_1_INTERRUPT_PIN 0xfffe1031a03d #define cfgBIF_CFG_DEV0_EPF0_VF26_1_MIN_GRANT 0xfffe1031a03e #define cfgBIF_CFG_DEV0_EPF0_VF26_1_MAX_LATENCY 0xfffe1031a03f #define cfgBIF_CFG_DEV0_EPF0_VF26_1_PCIE_CAP_LIST 0xfffe1031a064 #define cfgBIF_CFG_DEV0_EPF0_VF26_1_PCIE_CAP 0xfffe1031a066 #define cfgBIF_CFG_DEV0_EPF0_VF26_1_DEVICE_CAP 0xfffe1031a068 #define cfgBIF_CFG_DEV0_EPF0_VF26_1_DEVICE_CNTL 0xfffe1031a06c #define cfgBIF_CFG_DEV0_EPF0_VF26_1_DEVICE_STATUS 0xfffe1031a06e #define cfgBIF_CFG_DEV0_EPF0_VF26_1_LINK_CAP 0xfffe1031a070 #define cfgBIF_CFG_DEV0_EPF0_VF26_1_LINK_CNTL 0xfffe1031a074 #define cfgBIF_CFG_DEV0_EPF0_VF26_1_LINK_STATUS 0xfffe1031a076 #define cfgBIF_CFG_DEV0_EPF0_VF26_1_DEVICE_CAP2 0xfffe1031a088 #define cfgBIF_CFG_DEV0_EPF0_VF26_1_DEVICE_CNTL2 0xfffe1031a08c #define cfgBIF_CFG_DEV0_EPF0_VF26_1_DEVICE_STATUS2 0xfffe1031a08e #define cfgBIF_CFG_DEV0_EPF0_VF26_1_LINK_CAP2 0xfffe1031a090 #define cfgBIF_CFG_DEV0_EPF0_VF26_1_LINK_CNTL2 0xfffe1031a094 #define cfgBIF_CFG_DEV0_EPF0_VF26_1_LINK_STATUS2 0xfffe1031a096 #define cfgBIF_CFG_DEV0_EPF0_VF26_1_MSI_CAP_LIST 0xfffe1031a0a0 #define cfgBIF_CFG_DEV0_EPF0_VF26_1_MSI_MSG_CNTL 0xfffe1031a0a2 #define cfgBIF_CFG_DEV0_EPF0_VF26_1_MSI_MSG_ADDR_LO 0xfffe1031a0a4 #define cfgBIF_CFG_DEV0_EPF0_VF26_1_MSI_MSG_ADDR_HI 0xfffe1031a0a8 #define cfgBIF_CFG_DEV0_EPF0_VF26_1_MSI_MSG_DATA 0xfffe1031a0a8 #define cfgBIF_CFG_DEV0_EPF0_VF26_1_MSI_MASK 0xfffe1031a0ac #define cfgBIF_CFG_DEV0_EPF0_VF26_1_MSI_MSG_DATA_64 0xfffe1031a0ac #define cfgBIF_CFG_DEV0_EPF0_VF26_1_MSI_MASK_64 0xfffe1031a0b0 #define cfgBIF_CFG_DEV0_EPF0_VF26_1_MSI_PENDING 0xfffe1031a0b0 #define cfgBIF_CFG_DEV0_EPF0_VF26_1_MSI_PENDING_64 0xfffe1031a0b4 #define cfgBIF_CFG_DEV0_EPF0_VF26_1_MSIX_CAP_LIST 0xfffe1031a0c0 #define cfgBIF_CFG_DEV0_EPF0_VF26_1_MSIX_MSG_CNTL 0xfffe1031a0c2 #define cfgBIF_CFG_DEV0_EPF0_VF26_1_MSIX_TABLE 0xfffe1031a0c4 #define cfgBIF_CFG_DEV0_EPF0_VF26_1_MSIX_PBA 0xfffe1031a0c8 #define cfgBIF_CFG_DEV0_EPF0_VF26_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0xfffe1031a100 #define cfgBIF_CFG_DEV0_EPF0_VF26_1_PCIE_VENDOR_SPECIFIC_HDR 0xfffe1031a104 #define cfgBIF_CFG_DEV0_EPF0_VF26_1_PCIE_VENDOR_SPECIFIC1 0xfffe1031a108 #define cfgBIF_CFG_DEV0_EPF0_VF26_1_PCIE_VENDOR_SPECIFIC2 0xfffe1031a10c #define cfgBIF_CFG_DEV0_EPF0_VF26_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0xfffe1031a150 #define cfgBIF_CFG_DEV0_EPF0_VF26_1_PCIE_UNCORR_ERR_STATUS 0xfffe1031a154 #define cfgBIF_CFG_DEV0_EPF0_VF26_1_PCIE_UNCORR_ERR_MASK 0xfffe1031a158 #define cfgBIF_CFG_DEV0_EPF0_VF26_1_PCIE_UNCORR_ERR_SEVERITY 0xfffe1031a15c #define cfgBIF_CFG_DEV0_EPF0_VF26_1_PCIE_CORR_ERR_STATUS 0xfffe1031a160 #define cfgBIF_CFG_DEV0_EPF0_VF26_1_PCIE_CORR_ERR_MASK 0xfffe1031a164 #define cfgBIF_CFG_DEV0_EPF0_VF26_1_PCIE_ADV_ERR_CAP_CNTL 0xfffe1031a168 #define cfgBIF_CFG_DEV0_EPF0_VF26_1_PCIE_HDR_LOG0 0xfffe1031a16c #define cfgBIF_CFG_DEV0_EPF0_VF26_1_PCIE_HDR_LOG1 0xfffe1031a170 #define cfgBIF_CFG_DEV0_EPF0_VF26_1_PCIE_HDR_LOG2 0xfffe1031a174 #define cfgBIF_CFG_DEV0_EPF0_VF26_1_PCIE_HDR_LOG3 0xfffe1031a178 #define cfgBIF_CFG_DEV0_EPF0_VF26_1_PCIE_TLP_PREFIX_LOG0 0xfffe1031a188 #define cfgBIF_CFG_DEV0_EPF0_VF26_1_PCIE_TLP_PREFIX_LOG1 0xfffe1031a18c #define cfgBIF_CFG_DEV0_EPF0_VF26_1_PCIE_TLP_PREFIX_LOG2 0xfffe1031a190 #define cfgBIF_CFG_DEV0_EPF0_VF26_1_PCIE_TLP_PREFIX_LOG3 0xfffe1031a194 #define cfgBIF_CFG_DEV0_EPF0_VF26_1_PCIE_ATS_ENH_CAP_LIST 0xfffe1031a2b0 #define cfgBIF_CFG_DEV0_EPF0_VF26_1_PCIE_ATS_CAP 0xfffe1031a2b4 #define cfgBIF_CFG_DEV0_EPF0_VF26_1_PCIE_ATS_CNTL 0xfffe1031a2b6 #define cfgBIF_CFG_DEV0_EPF0_VF26_1_PCIE_ARI_ENH_CAP_LIST 0xfffe1031a328 #define cfgBIF_CFG_DEV0_EPF0_VF26_1_PCIE_ARI_CAP 0xfffe1031a32c #define cfgBIF_CFG_DEV0_EPF0_VF26_1_PCIE_ARI_CNTL 0xfffe1031a32e // addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf27_bifcfgdecp // base address: 0xfffe1031b000 #define cfgBIF_CFG_DEV0_EPF0_VF27_1_VENDOR_ID 0xfffe1031b000 #define cfgBIF_CFG_DEV0_EPF0_VF27_1_DEVICE_ID 0xfffe1031b002 #define cfgBIF_CFG_DEV0_EPF0_VF27_1_COMMAND 0xfffe1031b004 #define cfgBIF_CFG_DEV0_EPF0_VF27_1_STATUS 0xfffe1031b006 #define cfgBIF_CFG_DEV0_EPF0_VF27_1_REVISION_ID 0xfffe1031b008 #define cfgBIF_CFG_DEV0_EPF0_VF27_1_PROG_INTERFACE 0xfffe1031b009 #define cfgBIF_CFG_DEV0_EPF0_VF27_1_SUB_CLASS 0xfffe1031b00a #define cfgBIF_CFG_DEV0_EPF0_VF27_1_BASE_CLASS 0xfffe1031b00b #define cfgBIF_CFG_DEV0_EPF0_VF27_1_CACHE_LINE 0xfffe1031b00c #define cfgBIF_CFG_DEV0_EPF0_VF27_1_LATENCY 0xfffe1031b00d #define cfgBIF_CFG_DEV0_EPF0_VF27_1_HEADER 0xfffe1031b00e #define cfgBIF_CFG_DEV0_EPF0_VF27_1_BIST 0xfffe1031b00f #define cfgBIF_CFG_DEV0_EPF0_VF27_1_BASE_ADDR_1 0xfffe1031b010 #define cfgBIF_CFG_DEV0_EPF0_VF27_1_BASE_ADDR_2 0xfffe1031b014 #define cfgBIF_CFG_DEV0_EPF0_VF27_1_BASE_ADDR_3 0xfffe1031b018 #define cfgBIF_CFG_DEV0_EPF0_VF27_1_BASE_ADDR_4 0xfffe1031b01c #define cfgBIF_CFG_DEV0_EPF0_VF27_1_BASE_ADDR_5 0xfffe1031b020 #define cfgBIF_CFG_DEV0_EPF0_VF27_1_BASE_ADDR_6 0xfffe1031b024 #define cfgBIF_CFG_DEV0_EPF0_VF27_1_CARDBUS_CIS_PTR 0xfffe1031b028 #define cfgBIF_CFG_DEV0_EPF0_VF27_1_ADAPTER_ID 0xfffe1031b02c #define cfgBIF_CFG_DEV0_EPF0_VF27_1_ROM_BASE_ADDR 0xfffe1031b030 #define cfgBIF_CFG_DEV0_EPF0_VF27_1_CAP_PTR 0xfffe1031b034 #define cfgBIF_CFG_DEV0_EPF0_VF27_1_INTERRUPT_LINE 0xfffe1031b03c #define cfgBIF_CFG_DEV0_EPF0_VF27_1_INTERRUPT_PIN 0xfffe1031b03d #define cfgBIF_CFG_DEV0_EPF0_VF27_1_MIN_GRANT 0xfffe1031b03e #define cfgBIF_CFG_DEV0_EPF0_VF27_1_MAX_LATENCY 0xfffe1031b03f #define cfgBIF_CFG_DEV0_EPF0_VF27_1_PCIE_CAP_LIST 0xfffe1031b064 #define cfgBIF_CFG_DEV0_EPF0_VF27_1_PCIE_CAP 0xfffe1031b066 #define cfgBIF_CFG_DEV0_EPF0_VF27_1_DEVICE_CAP 0xfffe1031b068 #define cfgBIF_CFG_DEV0_EPF0_VF27_1_DEVICE_CNTL 0xfffe1031b06c #define cfgBIF_CFG_DEV0_EPF0_VF27_1_DEVICE_STATUS 0xfffe1031b06e #define cfgBIF_CFG_DEV0_EPF0_VF27_1_LINK_CAP 0xfffe1031b070 #define cfgBIF_CFG_DEV0_EPF0_VF27_1_LINK_CNTL 0xfffe1031b074 #define cfgBIF_CFG_DEV0_EPF0_VF27_1_LINK_STATUS 0xfffe1031b076 #define cfgBIF_CFG_DEV0_EPF0_VF27_1_DEVICE_CAP2 0xfffe1031b088 #define cfgBIF_CFG_DEV0_EPF0_VF27_1_DEVICE_CNTL2 0xfffe1031b08c #define cfgBIF_CFG_DEV0_EPF0_VF27_1_DEVICE_STATUS2 0xfffe1031b08e #define cfgBIF_CFG_DEV0_EPF0_VF27_1_LINK_CAP2 0xfffe1031b090 #define cfgBIF_CFG_DEV0_EPF0_VF27_1_LINK_CNTL2 0xfffe1031b094 #define cfgBIF_CFG_DEV0_EPF0_VF27_1_LINK_STATUS2 0xfffe1031b096 #define cfgBIF_CFG_DEV0_EPF0_VF27_1_MSI_CAP_LIST 0xfffe1031b0a0 #define cfgBIF_CFG_DEV0_EPF0_VF27_1_MSI_MSG_CNTL 0xfffe1031b0a2 #define cfgBIF_CFG_DEV0_EPF0_VF27_1_MSI_MSG_ADDR_LO 0xfffe1031b0a4 #define cfgBIF_CFG_DEV0_EPF0_VF27_1_MSI_MSG_ADDR_HI 0xfffe1031b0a8 #define cfgBIF_CFG_DEV0_EPF0_VF27_1_MSI_MSG_DATA 0xfffe1031b0a8 #define cfgBIF_CFG_DEV0_EPF0_VF27_1_MSI_MASK 0xfffe1031b0ac #define cfgBIF_CFG_DEV0_EPF0_VF27_1_MSI_MSG_DATA_64 0xfffe1031b0ac #define cfgBIF_CFG_DEV0_EPF0_VF27_1_MSI_MASK_64 0xfffe1031b0b0 #define cfgBIF_CFG_DEV0_EPF0_VF27_1_MSI_PENDING 0xfffe1031b0b0 #define cfgBIF_CFG_DEV0_EPF0_VF27_1_MSI_PENDING_64 0xfffe1031b0b4 #define cfgBIF_CFG_DEV0_EPF0_VF27_1_MSIX_CAP_LIST 0xfffe1031b0c0 #define cfgBIF_CFG_DEV0_EPF0_VF27_1_MSIX_MSG_CNTL 0xfffe1031b0c2 #define cfgBIF_CFG_DEV0_EPF0_VF27_1_MSIX_TABLE 0xfffe1031b0c4 #define cfgBIF_CFG_DEV0_EPF0_VF27_1_MSIX_PBA 0xfffe1031b0c8 #define cfgBIF_CFG_DEV0_EPF0_VF27_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0xfffe1031b100 #define cfgBIF_CFG_DEV0_EPF0_VF27_1_PCIE_VENDOR_SPECIFIC_HDR 0xfffe1031b104 #define cfgBIF_CFG_DEV0_EPF0_VF27_1_PCIE_VENDOR_SPECIFIC1 0xfffe1031b108 #define cfgBIF_CFG_DEV0_EPF0_VF27_1_PCIE_VENDOR_SPECIFIC2 0xfffe1031b10c #define cfgBIF_CFG_DEV0_EPF0_VF27_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0xfffe1031b150 #define cfgBIF_CFG_DEV0_EPF0_VF27_1_PCIE_UNCORR_ERR_STATUS 0xfffe1031b154 #define cfgBIF_CFG_DEV0_EPF0_VF27_1_PCIE_UNCORR_ERR_MASK 0xfffe1031b158 #define cfgBIF_CFG_DEV0_EPF0_VF27_1_PCIE_UNCORR_ERR_SEVERITY 0xfffe1031b15c #define cfgBIF_CFG_DEV0_EPF0_VF27_1_PCIE_CORR_ERR_STATUS 0xfffe1031b160 #define cfgBIF_CFG_DEV0_EPF0_VF27_1_PCIE_CORR_ERR_MASK 0xfffe1031b164 #define cfgBIF_CFG_DEV0_EPF0_VF27_1_PCIE_ADV_ERR_CAP_CNTL 0xfffe1031b168 #define cfgBIF_CFG_DEV0_EPF0_VF27_1_PCIE_HDR_LOG0 0xfffe1031b16c #define cfgBIF_CFG_DEV0_EPF0_VF27_1_PCIE_HDR_LOG1 0xfffe1031b170 #define cfgBIF_CFG_DEV0_EPF0_VF27_1_PCIE_HDR_LOG2 0xfffe1031b174 #define cfgBIF_CFG_DEV0_EPF0_VF27_1_PCIE_HDR_LOG3 0xfffe1031b178 #define cfgBIF_CFG_DEV0_EPF0_VF27_1_PCIE_TLP_PREFIX_LOG0 0xfffe1031b188 #define cfgBIF_CFG_DEV0_EPF0_VF27_1_PCIE_TLP_PREFIX_LOG1 0xfffe1031b18c #define cfgBIF_CFG_DEV0_EPF0_VF27_1_PCIE_TLP_PREFIX_LOG2 0xfffe1031b190 #define cfgBIF_CFG_DEV0_EPF0_VF27_1_PCIE_TLP_PREFIX_LOG3 0xfffe1031b194 #define cfgBIF_CFG_DEV0_EPF0_VF27_1_PCIE_ATS_ENH_CAP_LIST 0xfffe1031b2b0 #define cfgBIF_CFG_DEV0_EPF0_VF27_1_PCIE_ATS_CAP 0xfffe1031b2b4 #define cfgBIF_CFG_DEV0_EPF0_VF27_1_PCIE_ATS_CNTL 0xfffe1031b2b6 #define cfgBIF_CFG_DEV0_EPF0_VF27_1_PCIE_ARI_ENH_CAP_LIST 0xfffe1031b328 #define cfgBIF_CFG_DEV0_EPF0_VF27_1_PCIE_ARI_CAP 0xfffe1031b32c #define cfgBIF_CFG_DEV0_EPF0_VF27_1_PCIE_ARI_CNTL 0xfffe1031b32e // addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf28_bifcfgdecp // base address: 0xfffe1031c000 #define cfgBIF_CFG_DEV0_EPF0_VF28_1_VENDOR_ID 0xfffe1031c000 #define cfgBIF_CFG_DEV0_EPF0_VF28_1_DEVICE_ID 0xfffe1031c002 #define cfgBIF_CFG_DEV0_EPF0_VF28_1_COMMAND 0xfffe1031c004 #define cfgBIF_CFG_DEV0_EPF0_VF28_1_STATUS 0xfffe1031c006 #define cfgBIF_CFG_DEV0_EPF0_VF28_1_REVISION_ID 0xfffe1031c008 #define cfgBIF_CFG_DEV0_EPF0_VF28_1_PROG_INTERFACE 0xfffe1031c009 #define cfgBIF_CFG_DEV0_EPF0_VF28_1_SUB_CLASS 0xfffe1031c00a #define cfgBIF_CFG_DEV0_EPF0_VF28_1_BASE_CLASS 0xfffe1031c00b #define cfgBIF_CFG_DEV0_EPF0_VF28_1_CACHE_LINE 0xfffe1031c00c #define cfgBIF_CFG_DEV0_EPF0_VF28_1_LATENCY 0xfffe1031c00d #define cfgBIF_CFG_DEV0_EPF0_VF28_1_HEADER 0xfffe1031c00e #define cfgBIF_CFG_DEV0_EPF0_VF28_1_BIST 0xfffe1031c00f #define cfgBIF_CFG_DEV0_EPF0_VF28_1_BASE_ADDR_1 0xfffe1031c010 #define cfgBIF_CFG_DEV0_EPF0_VF28_1_BASE_ADDR_2 0xfffe1031c014 #define cfgBIF_CFG_DEV0_EPF0_VF28_1_BASE_ADDR_3 0xfffe1031c018 #define cfgBIF_CFG_DEV0_EPF0_VF28_1_BASE_ADDR_4 0xfffe1031c01c #define cfgBIF_CFG_DEV0_EPF0_VF28_1_BASE_ADDR_5 0xfffe1031c020 #define cfgBIF_CFG_DEV0_EPF0_VF28_1_BASE_ADDR_6 0xfffe1031c024 #define cfgBIF_CFG_DEV0_EPF0_VF28_1_CARDBUS_CIS_PTR 0xfffe1031c028 #define cfgBIF_CFG_DEV0_EPF0_VF28_1_ADAPTER_ID 0xfffe1031c02c #define cfgBIF_CFG_DEV0_EPF0_VF28_1_ROM_BASE_ADDR 0xfffe1031c030 #define cfgBIF_CFG_DEV0_EPF0_VF28_1_CAP_PTR 0xfffe1031c034 #define cfgBIF_CFG_DEV0_EPF0_VF28_1_INTERRUPT_LINE 0xfffe1031c03c #define cfgBIF_CFG_DEV0_EPF0_VF28_1_INTERRUPT_PIN 0xfffe1031c03d #define cfgBIF_CFG_DEV0_EPF0_VF28_1_MIN_GRANT 0xfffe1031c03e #define cfgBIF_CFG_DEV0_EPF0_VF28_1_MAX_LATENCY 0xfffe1031c03f #define cfgBIF_CFG_DEV0_EPF0_VF28_1_PCIE_CAP_LIST 0xfffe1031c064 #define cfgBIF_CFG_DEV0_EPF0_VF28_1_PCIE_CAP 0xfffe1031c066 #define cfgBIF_CFG_DEV0_EPF0_VF28_1_DEVICE_CAP 0xfffe1031c068 #define cfgBIF_CFG_DEV0_EPF0_VF28_1_DEVICE_CNTL 0xfffe1031c06c #define cfgBIF_CFG_DEV0_EPF0_VF28_1_DEVICE_STATUS 0xfffe1031c06e #define cfgBIF_CFG_DEV0_EPF0_VF28_1_LINK_CAP 0xfffe1031c070 #define cfgBIF_CFG_DEV0_EPF0_VF28_1_LINK_CNTL 0xfffe1031c074 #define cfgBIF_CFG_DEV0_EPF0_VF28_1_LINK_STATUS 0xfffe1031c076 #define cfgBIF_CFG_DEV0_EPF0_VF28_1_DEVICE_CAP2 0xfffe1031c088 #define cfgBIF_CFG_DEV0_EPF0_VF28_1_DEVICE_CNTL2 0xfffe1031c08c #define cfgBIF_CFG_DEV0_EPF0_VF28_1_DEVICE_STATUS2 0xfffe1031c08e #define cfgBIF_CFG_DEV0_EPF0_VF28_1_LINK_CAP2 0xfffe1031c090 #define cfgBIF_CFG_DEV0_EPF0_VF28_1_LINK_CNTL2 0xfffe1031c094 #define cfgBIF_CFG_DEV0_EPF0_VF28_1_LINK_STATUS2 0xfffe1031c096 #define cfgBIF_CFG_DEV0_EPF0_VF28_1_MSI_CAP_LIST 0xfffe1031c0a0 #define cfgBIF_CFG_DEV0_EPF0_VF28_1_MSI_MSG_CNTL 0xfffe1031c0a2 #define cfgBIF_CFG_DEV0_EPF0_VF28_1_MSI_MSG_ADDR_LO 0xfffe1031c0a4 #define cfgBIF_CFG_DEV0_EPF0_VF28_1_MSI_MSG_ADDR_HI 0xfffe1031c0a8 #define cfgBIF_CFG_DEV0_EPF0_VF28_1_MSI_MSG_DATA 0xfffe1031c0a8 #define cfgBIF_CFG_DEV0_EPF0_VF28_1_MSI_MASK 0xfffe1031c0ac #define cfgBIF_CFG_DEV0_EPF0_VF28_1_MSI_MSG_DATA_64 0xfffe1031c0ac #define cfgBIF_CFG_DEV0_EPF0_VF28_1_MSI_MASK_64 0xfffe1031c0b0 #define cfgBIF_CFG_DEV0_EPF0_VF28_1_MSI_PENDING 0xfffe1031c0b0 #define cfgBIF_CFG_DEV0_EPF0_VF28_1_MSI_PENDING_64 0xfffe1031c0b4 #define cfgBIF_CFG_DEV0_EPF0_VF28_1_MSIX_CAP_LIST 0xfffe1031c0c0 #define cfgBIF_CFG_DEV0_EPF0_VF28_1_MSIX_MSG_CNTL 0xfffe1031c0c2 #define cfgBIF_CFG_DEV0_EPF0_VF28_1_MSIX_TABLE 0xfffe1031c0c4 #define cfgBIF_CFG_DEV0_EPF0_VF28_1_MSIX_PBA 0xfffe1031c0c8 #define cfgBIF_CFG_DEV0_EPF0_VF28_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0xfffe1031c100 #define cfgBIF_CFG_DEV0_EPF0_VF28_1_PCIE_VENDOR_SPECIFIC_HDR 0xfffe1031c104 #define cfgBIF_CFG_DEV0_EPF0_VF28_1_PCIE_VENDOR_SPECIFIC1 0xfffe1031c108 #define cfgBIF_CFG_DEV0_EPF0_VF28_1_PCIE_VENDOR_SPECIFIC2 0xfffe1031c10c #define cfgBIF_CFG_DEV0_EPF0_VF28_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0xfffe1031c150 #define cfgBIF_CFG_DEV0_EPF0_VF28_1_PCIE_UNCORR_ERR_STATUS 0xfffe1031c154 #define cfgBIF_CFG_DEV0_EPF0_VF28_1_PCIE_UNCORR_ERR_MASK 0xfffe1031c158 #define cfgBIF_CFG_DEV0_EPF0_VF28_1_PCIE_UNCORR_ERR_SEVERITY 0xfffe1031c15c #define cfgBIF_CFG_DEV0_EPF0_VF28_1_PCIE_CORR_ERR_STATUS 0xfffe1031c160 #define cfgBIF_CFG_DEV0_EPF0_VF28_1_PCIE_CORR_ERR_MASK 0xfffe1031c164 #define cfgBIF_CFG_DEV0_EPF0_VF28_1_PCIE_ADV_ERR_CAP_CNTL 0xfffe1031c168 #define cfgBIF_CFG_DEV0_EPF0_VF28_1_PCIE_HDR_LOG0 0xfffe1031c16c #define cfgBIF_CFG_DEV0_EPF0_VF28_1_PCIE_HDR_LOG1 0xfffe1031c170 #define cfgBIF_CFG_DEV0_EPF0_VF28_1_PCIE_HDR_LOG2 0xfffe1031c174 #define cfgBIF_CFG_DEV0_EPF0_VF28_1_PCIE_HDR_LOG3 0xfffe1031c178 #define cfgBIF_CFG_DEV0_EPF0_VF28_1_PCIE_TLP_PREFIX_LOG0 0xfffe1031c188 #define cfgBIF_CFG_DEV0_EPF0_VF28_1_PCIE_TLP_PREFIX_LOG1 0xfffe1031c18c #define cfgBIF_CFG_DEV0_EPF0_VF28_1_PCIE_TLP_PREFIX_LOG2 0xfffe1031c190 #define cfgBIF_CFG_DEV0_EPF0_VF28_1_PCIE_TLP_PREFIX_LOG3 0xfffe1031c194 #define cfgBIF_CFG_DEV0_EPF0_VF28_1_PCIE_ATS_ENH_CAP_LIST 0xfffe1031c2b0 #define cfgBIF_CFG_DEV0_EPF0_VF28_1_PCIE_ATS_CAP 0xfffe1031c2b4 #define cfgBIF_CFG_DEV0_EPF0_VF28_1_PCIE_ATS_CNTL 0xfffe1031c2b6 #define cfgBIF_CFG_DEV0_EPF0_VF28_1_PCIE_ARI_ENH_CAP_LIST 0xfffe1031c328 #define cfgBIF_CFG_DEV0_EPF0_VF28_1_PCIE_ARI_CAP 0xfffe1031c32c #define cfgBIF_CFG_DEV0_EPF0_VF28_1_PCIE_ARI_CNTL 0xfffe1031c32e // addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf29_bifcfgdecp // base address: 0xfffe1031d000 #define cfgBIF_CFG_DEV0_EPF0_VF29_1_VENDOR_ID 0xfffe1031d000 #define cfgBIF_CFG_DEV0_EPF0_VF29_1_DEVICE_ID 0xfffe1031d002 #define cfgBIF_CFG_DEV0_EPF0_VF29_1_COMMAND 0xfffe1031d004 #define cfgBIF_CFG_DEV0_EPF0_VF29_1_STATUS 0xfffe1031d006 #define cfgBIF_CFG_DEV0_EPF0_VF29_1_REVISION_ID 0xfffe1031d008 #define cfgBIF_CFG_DEV0_EPF0_VF29_1_PROG_INTERFACE 0xfffe1031d009 #define cfgBIF_CFG_DEV0_EPF0_VF29_1_SUB_CLASS 0xfffe1031d00a #define cfgBIF_CFG_DEV0_EPF0_VF29_1_BASE_CLASS 0xfffe1031d00b #define cfgBIF_CFG_DEV0_EPF0_VF29_1_CACHE_LINE 0xfffe1031d00c #define cfgBIF_CFG_DEV0_EPF0_VF29_1_LATENCY 0xfffe1031d00d #define cfgBIF_CFG_DEV0_EPF0_VF29_1_HEADER 0xfffe1031d00e #define cfgBIF_CFG_DEV0_EPF0_VF29_1_BIST 0xfffe1031d00f #define cfgBIF_CFG_DEV0_EPF0_VF29_1_BASE_ADDR_1 0xfffe1031d010 #define cfgBIF_CFG_DEV0_EPF0_VF29_1_BASE_ADDR_2 0xfffe1031d014 #define cfgBIF_CFG_DEV0_EPF0_VF29_1_BASE_ADDR_3 0xfffe1031d018 #define cfgBIF_CFG_DEV0_EPF0_VF29_1_BASE_ADDR_4 0xfffe1031d01c #define cfgBIF_CFG_DEV0_EPF0_VF29_1_BASE_ADDR_5 0xfffe1031d020 #define cfgBIF_CFG_DEV0_EPF0_VF29_1_BASE_ADDR_6 0xfffe1031d024 #define cfgBIF_CFG_DEV0_EPF0_VF29_1_CARDBUS_CIS_PTR 0xfffe1031d028 #define cfgBIF_CFG_DEV0_EPF0_VF29_1_ADAPTER_ID 0xfffe1031d02c #define cfgBIF_CFG_DEV0_EPF0_VF29_1_ROM_BASE_ADDR 0xfffe1031d030 #define cfgBIF_CFG_DEV0_EPF0_VF29_1_CAP_PTR 0xfffe1031d034 #define cfgBIF_CFG_DEV0_EPF0_VF29_1_INTERRUPT_LINE 0xfffe1031d03c #define cfgBIF_CFG_DEV0_EPF0_VF29_1_INTERRUPT_PIN 0xfffe1031d03d #define cfgBIF_CFG_DEV0_EPF0_VF29_1_MIN_GRANT 0xfffe1031d03e #define cfgBIF_CFG_DEV0_EPF0_VF29_1_MAX_LATENCY 0xfffe1031d03f #define cfgBIF_CFG_DEV0_EPF0_VF29_1_PCIE_CAP_LIST 0xfffe1031d064 #define cfgBIF_CFG_DEV0_EPF0_VF29_1_PCIE_CAP 0xfffe1031d066 #define cfgBIF_CFG_DEV0_EPF0_VF29_1_DEVICE_CAP 0xfffe1031d068 #define cfgBIF_CFG_DEV0_EPF0_VF29_1_DEVICE_CNTL 0xfffe1031d06c #define cfgBIF_CFG_DEV0_EPF0_VF29_1_DEVICE_STATUS 0xfffe1031d06e #define cfgBIF_CFG_DEV0_EPF0_VF29_1_LINK_CAP 0xfffe1031d070 #define cfgBIF_CFG_DEV0_EPF0_VF29_1_LINK_CNTL 0xfffe1031d074 #define cfgBIF_CFG_DEV0_EPF0_VF29_1_LINK_STATUS 0xfffe1031d076 #define cfgBIF_CFG_DEV0_EPF0_VF29_1_DEVICE_CAP2 0xfffe1031d088 #define cfgBIF_CFG_DEV0_EPF0_VF29_1_DEVICE_CNTL2 0xfffe1031d08c #define cfgBIF_CFG_DEV0_EPF0_VF29_1_DEVICE_STATUS2 0xfffe1031d08e #define cfgBIF_CFG_DEV0_EPF0_VF29_1_LINK_CAP2 0xfffe1031d090 #define cfgBIF_CFG_DEV0_EPF0_VF29_1_LINK_CNTL2 0xfffe1031d094 #define cfgBIF_CFG_DEV0_EPF0_VF29_1_LINK_STATUS2 0xfffe1031d096 #define cfgBIF_CFG_DEV0_EPF0_VF29_1_MSI_CAP_LIST 0xfffe1031d0a0 #define cfgBIF_CFG_DEV0_EPF0_VF29_1_MSI_MSG_CNTL 0xfffe1031d0a2 #define cfgBIF_CFG_DEV0_EPF0_VF29_1_MSI_MSG_ADDR_LO 0xfffe1031d0a4 #define cfgBIF_CFG_DEV0_EPF0_VF29_1_MSI_MSG_ADDR_HI 0xfffe1031d0a8 #define cfgBIF_CFG_DEV0_EPF0_VF29_1_MSI_MSG_DATA 0xfffe1031d0a8 #define cfgBIF_CFG_DEV0_EPF0_VF29_1_MSI_MASK 0xfffe1031d0ac #define cfgBIF_CFG_DEV0_EPF0_VF29_1_MSI_MSG_DATA_64 0xfffe1031d0ac #define cfgBIF_CFG_DEV0_EPF0_VF29_1_MSI_MASK_64 0xfffe1031d0b0 #define cfgBIF_CFG_DEV0_EPF0_VF29_1_MSI_PENDING 0xfffe1031d0b0 #define cfgBIF_CFG_DEV0_EPF0_VF29_1_MSI_PENDING_64 0xfffe1031d0b4 #define cfgBIF_CFG_DEV0_EPF0_VF29_1_MSIX_CAP_LIST 0xfffe1031d0c0 #define cfgBIF_CFG_DEV0_EPF0_VF29_1_MSIX_MSG_CNTL 0xfffe1031d0c2 #define cfgBIF_CFG_DEV0_EPF0_VF29_1_MSIX_TABLE 0xfffe1031d0c4 #define cfgBIF_CFG_DEV0_EPF0_VF29_1_MSIX_PBA 0xfffe1031d0c8 #define cfgBIF_CFG_DEV0_EPF0_VF29_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0xfffe1031d100 #define cfgBIF_CFG_DEV0_EPF0_VF29_1_PCIE_VENDOR_SPECIFIC_HDR 0xfffe1031d104 #define cfgBIF_CFG_DEV0_EPF0_VF29_1_PCIE_VENDOR_SPECIFIC1 0xfffe1031d108 #define cfgBIF_CFG_DEV0_EPF0_VF29_1_PCIE_VENDOR_SPECIFIC2 0xfffe1031d10c #define cfgBIF_CFG_DEV0_EPF0_VF29_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0xfffe1031d150 #define cfgBIF_CFG_DEV0_EPF0_VF29_1_PCIE_UNCORR_ERR_STATUS 0xfffe1031d154 #define cfgBIF_CFG_DEV0_EPF0_VF29_1_PCIE_UNCORR_ERR_MASK 0xfffe1031d158 #define cfgBIF_CFG_DEV0_EPF0_VF29_1_PCIE_UNCORR_ERR_SEVERITY 0xfffe1031d15c #define cfgBIF_CFG_DEV0_EPF0_VF29_1_PCIE_CORR_ERR_STATUS 0xfffe1031d160 #define cfgBIF_CFG_DEV0_EPF0_VF29_1_PCIE_CORR_ERR_MASK 0xfffe1031d164 #define cfgBIF_CFG_DEV0_EPF0_VF29_1_PCIE_ADV_ERR_CAP_CNTL 0xfffe1031d168 #define cfgBIF_CFG_DEV0_EPF0_VF29_1_PCIE_HDR_LOG0 0xfffe1031d16c #define cfgBIF_CFG_DEV0_EPF0_VF29_1_PCIE_HDR_LOG1 0xfffe1031d170 #define cfgBIF_CFG_DEV0_EPF0_VF29_1_PCIE_HDR_LOG2 0xfffe1031d174 #define cfgBIF_CFG_DEV0_EPF0_VF29_1_PCIE_HDR_LOG3 0xfffe1031d178 #define cfgBIF_CFG_DEV0_EPF0_VF29_1_PCIE_TLP_PREFIX_LOG0 0xfffe1031d188 #define cfgBIF_CFG_DEV0_EPF0_VF29_1_PCIE_TLP_PREFIX_LOG1 0xfffe1031d18c #define cfgBIF_CFG_DEV0_EPF0_VF29_1_PCIE_TLP_PREFIX_LOG2 0xfffe1031d190 #define cfgBIF_CFG_DEV0_EPF0_VF29_1_PCIE_TLP_PREFIX_LOG3 0xfffe1031d194 #define cfgBIF_CFG_DEV0_EPF0_VF29_1_PCIE_ATS_ENH_CAP_LIST 0xfffe1031d2b0 #define cfgBIF_CFG_DEV0_EPF0_VF29_1_PCIE_ATS_CAP 0xfffe1031d2b4 #define cfgBIF_CFG_DEV0_EPF0_VF29_1_PCIE_ATS_CNTL 0xfffe1031d2b6 #define cfgBIF_CFG_DEV0_EPF0_VF29_1_PCIE_ARI_ENH_CAP_LIST 0xfffe1031d328 #define cfgBIF_CFG_DEV0_EPF0_VF29_1_PCIE_ARI_CAP 0xfffe1031d32c #define cfgBIF_CFG_DEV0_EPF0_VF29_1_PCIE_ARI_CNTL 0xfffe1031d32e // addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_vf30_bifcfgdecp // base address: 0xfffe1031e000 #define cfgBIF_CFG_DEV0_EPF0_VF30_1_VENDOR_ID 0xfffe1031e000 #define cfgBIF_CFG_DEV0_EPF0_VF30_1_DEVICE_ID 0xfffe1031e002 #define cfgBIF_CFG_DEV0_EPF0_VF30_1_COMMAND 0xfffe1031e004 #define cfgBIF_CFG_DEV0_EPF0_VF30_1_STATUS 0xfffe1031e006 #define cfgBIF_CFG_DEV0_EPF0_VF30_1_REVISION_ID 0xfffe1031e008 #define cfgBIF_CFG_DEV0_EPF0_VF30_1_PROG_INTERFACE 0xfffe1031e009 #define cfgBIF_CFG_DEV0_EPF0_VF30_1_SUB_CLASS 0xfffe1031e00a #define cfgBIF_CFG_DEV0_EPF0_VF30_1_BASE_CLASS 0xfffe1031e00b #define cfgBIF_CFG_DEV0_EPF0_VF30_1_CACHE_LINE 0xfffe1031e00c #define cfgBIF_CFG_DEV0_EPF0_VF30_1_LATENCY 0xfffe1031e00d #define cfgBIF_CFG_DEV0_EPF0_VF30_1_HEADER 0xfffe1031e00e #define cfgBIF_CFG_DEV0_EPF0_VF30_1_BIST 0xfffe1031e00f #define cfgBIF_CFG_DEV0_EPF0_VF30_1_BASE_ADDR_1 0xfffe1031e010 #define cfgBIF_CFG_DEV0_EPF0_VF30_1_BASE_ADDR_2 0xfffe1031e014 #define cfgBIF_CFG_DEV0_EPF0_VF30_1_BASE_ADDR_3 0xfffe1031e018 #define cfgBIF_CFG_DEV0_EPF0_VF30_1_BASE_ADDR_4 0xfffe1031e01c #define cfgBIF_CFG_DEV0_EPF0_VF30_1_BASE_ADDR_5 0xfffe1031e020 #define cfgBIF_CFG_DEV0_EPF0_VF30_1_BASE_ADDR_6 0xfffe1031e024 #define cfgBIF_CFG_DEV0_EPF0_VF30_1_CARDBUS_CIS_PTR 0xfffe1031e028 #define cfgBIF_CFG_DEV0_EPF0_VF30_1_ADAPTER_ID 0xfffe1031e02c #define cfgBIF_CFG_DEV0_EPF0_VF30_1_ROM_BASE_ADDR 0xfffe1031e030 #define cfgBIF_CFG_DEV0_EPF0_VF30_1_CAP_PTR 0xfffe1031e034 #define cfgBIF_CFG_DEV0_EPF0_VF30_1_INTERRUPT_LINE 0xfffe1031e03c #define cfgBIF_CFG_DEV0_EPF0_VF30_1_INTERRUPT_PIN 0xfffe1031e03d #define cfgBIF_CFG_DEV0_EPF0_VF30_1_MIN_GRANT 0xfffe1031e03e #define cfgBIF_CFG_DEV0_EPF0_VF30_1_MAX_LATENCY 0xfffe1031e03f #define cfgBIF_CFG_DEV0_EPF0_VF30_1_PCIE_CAP_LIST 0xfffe1031e064 #define cfgBIF_CFG_DEV0_EPF0_VF30_1_PCIE_CAP 0xfffe1031e066 #define cfgBIF_CFG_DEV0_EPF0_VF30_1_DEVICE_CAP 0xfffe1031e068 #define cfgBIF_CFG_DEV0_EPF0_VF30_1_DEVICE_CNTL 0xfffe1031e06c #define cfgBIF_CFG_DEV0_EPF0_VF30_1_DEVICE_STATUS 0xfffe1031e06e #define cfgBIF_CFG_DEV0_EPF0_VF30_1_LINK_CAP 0xfffe1031e070 #define cfgBIF_CFG_DEV0_EPF0_VF30_1_LINK_CNTL 0xfffe1031e074 #define cfgBIF_CFG_DEV0_EPF0_VF30_1_LINK_STATUS 0xfffe1031e076 #define cfgBIF_CFG_DEV0_EPF0_VF30_1_DEVICE_CAP2 0xfffe1031e088 #define cfgBIF_CFG_DEV0_EPF0_VF30_1_DEVICE_CNTL2 0xfffe1031e08c #define cfgBIF_CFG_DEV0_EPF0_VF30_1_DEVICE_STATUS2 0xfffe1031e08e #define cfgBIF_CFG_DEV0_EPF0_VF30_1_LINK_CAP2 0xfffe1031e090 #define cfgBIF_CFG_DEV0_EPF0_VF30_1_LINK_CNTL2 0xfffe1031e094 #define cfgBIF_CFG_DEV0_EPF0_VF30_1_LINK_STATUS2 0xfffe1031e096 #define cfgBIF_CFG_DEV0_EPF0_VF30_1_MSI_CAP_LIST 0xfffe1031e0a0 #define cfgBIF_CFG_DEV0_EPF0_VF30_1_MSI_MSG_CNTL 0xfffe1031e0a2 #define cfgBIF_CFG_DEV0_EPF0_VF30_1_MSI_MSG_ADDR_LO 0xfffe1031e0a4 #define cfgBIF_CFG_DEV0_EPF0_VF30_1_MSI_MSG_ADDR_HI 0xfffe1031e0a8 #define cfgBIF_CFG_DEV0_EPF0_VF30_1_MSI_MSG_DATA 0xfffe1031e0a8 #define cfgBIF_CFG_DEV0_EPF0_VF30_1_MSI_MASK 0xfffe1031e0ac #define cfgBIF_CFG_DEV0_EPF0_VF30_1_MSI_MSG_DATA_64 0xfffe1031e0ac #define cfgBIF_CFG_DEV0_EPF0_VF30_1_MSI_MASK_64 0xfffe1031e0b0 #define cfgBIF_CFG_DEV0_EPF0_VF30_1_MSI_PENDING 0xfffe1031e0b0 #define cfgBIF_CFG_DEV0_EPF0_VF30_1_MSI_PENDING_64 0xfffe1031e0b4 #define cfgBIF_CFG_DEV0_EPF0_VF30_1_MSIX_CAP_LIST 0xfffe1031e0c0 #define cfgBIF_CFG_DEV0_EPF0_VF30_1_MSIX_MSG_CNTL 0xfffe1031e0c2 #define cfgBIF_CFG_DEV0_EPF0_VF30_1_MSIX_TABLE 0xfffe1031e0c4 #define cfgBIF_CFG_DEV0_EPF0_VF30_1_MSIX_PBA 0xfffe1031e0c8 #define cfgBIF_CFG_DEV0_EPF0_VF30_1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0xfffe1031e100 #define cfgBIF_CFG_DEV0_EPF0_VF30_1_PCIE_VENDOR_SPECIFIC_HDR 0xfffe1031e104 #define cfgBIF_CFG_DEV0_EPF0_VF30_1_PCIE_VENDOR_SPECIFIC1 0xfffe1031e108 #define cfgBIF_CFG_DEV0_EPF0_VF30_1_PCIE_VENDOR_SPECIFIC2 0xfffe1031e10c #define cfgBIF_CFG_DEV0_EPF0_VF30_1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0xfffe1031e150 #define cfgBIF_CFG_DEV0_EPF0_VF30_1_PCIE_UNCORR_ERR_STATUS 0xfffe1031e154 #define cfgBIF_CFG_DEV0_EPF0_VF30_1_PCIE_UNCORR_ERR_MASK 0xfffe1031e158 #define cfgBIF_CFG_DEV0_EPF0_VF30_1_PCIE_UNCORR_ERR_SEVERITY 0xfffe1031e15c #define cfgBIF_CFG_DEV0_EPF0_VF30_1_PCIE_CORR_ERR_STATUS 0xfffe1031e160 #define cfgBIF_CFG_DEV0_EPF0_VF30_1_PCIE_CORR_ERR_MASK 0xfffe1031e164 #define cfgBIF_CFG_DEV0_EPF0_VF30_1_PCIE_ADV_ERR_CAP_CNTL 0xfffe1031e168 #define cfgBIF_CFG_DEV0_EPF0_VF30_1_PCIE_HDR_LOG0 0xfffe1031e16c #define cfgBIF_CFG_DEV0_EPF0_VF30_1_PCIE_HDR_LOG1 0xfffe1031e170 #define cfgBIF_CFG_DEV0_EPF0_VF30_1_PCIE_HDR_LOG2 0xfffe1031e174 #define cfgBIF_CFG_DEV0_EPF0_VF30_1_PCIE_HDR_LOG3 0xfffe1031e178 #define cfgBIF_CFG_DEV0_EPF0_VF30_1_PCIE_TLP_PREFIX_LOG0 0xfffe1031e188 #define cfgBIF_CFG_DEV0_EPF0_VF30_1_PCIE_TLP_PREFIX_LOG1 0xfffe1031e18c #define cfgBIF_CFG_DEV0_EPF0_VF30_1_PCIE_TLP_PREFIX_LOG2 0xfffe1031e190 #define cfgBIF_CFG_DEV0_EPF0_VF30_1_PCIE_TLP_PREFIX_LOG3 0xfffe1031e194 #define cfgBIF_CFG_DEV0_EPF0_VF30_1_PCIE_ATS_ENH_CAP_LIST 0xfffe1031e2b0 #define cfgBIF_CFG_DEV0_EPF0_VF30_1_PCIE_ATS_CAP 0xfffe1031e2b4 #define cfgBIF_CFG_DEV0_EPF0_VF30_1_PCIE_ATS_CNTL 0xfffe1031e2b6 #define cfgBIF_CFG_DEV0_EPF0_VF30_1_PCIE_ARI_ENH_CAP_LIST 0xfffe1031e328 #define cfgBIF_CFG_DEV0_EPF0_VF30_1_PCIE_ARI_CAP 0xfffe1031e32c #define cfgBIF_CFG_DEV0_EPF0_VF30_1_PCIE_ARI_CNTL 0xfffe1031e32e // addressBlock: nbio_nbif0_rcc_shadow_reg_shadowdec // base address: 0xfffe30000000 #define cfgSHADOW_COMMAND 0xfffe30000004 #define cfgSHADOW_BASE_ADDR_1 0xfffe30000010 #define cfgSHADOW_BASE_ADDR_2 0xfffe30000014 #define cfgSHADOW_SUB_BUS_NUMBER_LATENCY 0xfffe30000018 #define cfgSHADOW_IO_BASE_LIMIT 0xfffe3000001c #define cfgSHADOW_MEM_BASE_LIMIT 0xfffe30000020 #define cfgSHADOW_PREF_BASE_LIMIT 0xfffe30000024 #define cfgSHADOW_PREF_BASE_UPPER 0xfffe30000028 #define cfgSHADOW_PREF_LIMIT_UPPER 0xfffe3000002c #define cfgSHADOW_IO_BASE_LIMIT_HI 0xfffe30000030 #define cfgSHADOW_IRQ_BRIDGE_CNTL 0xfffe3000003e #define cfgSUC_INDEX 0xfffe300000e0 #define cfgSUC_DATA 0xfffe300000e4 // addressBlock: nbio_nbif0_bif_bx_pf_SYSPFVFDEC // base address: 0x30300000 #define cfgBIF_BX_PF1_MM_INDEX 0x30300000 #define cfgBIF_BX_PF1_MM_DATA 0x30300004 #define cfgBIF_BX_PF1_MM_INDEX_HI 0x30300018 // addressBlock: nbio_nbif0_bif_bx_SYSDEC // base address: 0x30300000 #define cfgSYSHUB_INDEX_OVLP 0x30300020 #define cfgSYSHUB_DATA_OVLP 0x30300024 #define cfgPCIE_INDEX 0x30300030 #define cfgPCIE_DATA 0x30300034 #define cfgPCIE_INDEX2 0x30300038 #define cfgPCIE_DATA2 0x3030003c #define cfgSBIOS_SCRATCH_0 0x30300120 #define cfgSBIOS_SCRATCH_1 0x30300124 #define cfgSBIOS_SCRATCH_2 0x30300128 #define cfgSBIOS_SCRATCH_3 0x3030012c #define cfgBIOS_SCRATCH_0 0x30300130 #define cfgBIOS_SCRATCH_1 0x30300134 #define cfgBIOS_SCRATCH_2 0x30300138 #define cfgBIOS_SCRATCH_3 0x3030013c #define cfgBIOS_SCRATCH_4 0x30300140 #define cfgBIOS_SCRATCH_5 0x30300144 #define cfgBIOS_SCRATCH_6 0x30300148 #define cfgBIOS_SCRATCH_7 0x3030014c #define cfgBIOS_SCRATCH_8 0x30300150 #define cfgBIOS_SCRATCH_9 0x30300154 #define cfgBIOS_SCRATCH_10 0x30300158 #define cfgBIOS_SCRATCH_11 0x3030015c #define cfgBIOS_SCRATCH_12 0x30300160 #define cfgBIOS_SCRATCH_13 0x30300164 #define cfgBIOS_SCRATCH_14 0x30300168 #define cfgBIOS_SCRATCH_15 0x3030016c #define cfgBIF_RLC_INTR_CNTL 0x30300180 #define cfgBIF_VCE_INTR_CNTL 0x30300184 #define cfgBIF_UVD_INTR_CNTL 0x30300188 #define cfgGFX_MMIOREG_CAM_ADDR0 0x30300200 #define cfgGFX_MMIOREG_CAM_REMAP_ADDR0 0x30300204 #define cfgGFX_MMIOREG_CAM_ADDR1 0x30300208 #define cfgGFX_MMIOREG_CAM_REMAP_ADDR1 0x3030020c #define cfgGFX_MMIOREG_CAM_ADDR2 0x30300210 #define cfgGFX_MMIOREG_CAM_REMAP_ADDR2 0x30300214 #define cfgGFX_MMIOREG_CAM_ADDR3 0x30300218 #define cfgGFX_MMIOREG_CAM_REMAP_ADDR3 0x3030021c #define cfgGFX_MMIOREG_CAM_ADDR4 0x30300220 #define cfgGFX_MMIOREG_CAM_REMAP_ADDR4 0x30300224 #define cfgGFX_MMIOREG_CAM_ADDR5 0x30300228 #define cfgGFX_MMIOREG_CAM_REMAP_ADDR5 0x3030022c #define cfgGFX_MMIOREG_CAM_ADDR6 0x30300230 #define cfgGFX_MMIOREG_CAM_REMAP_ADDR6 0x30300234 #define cfgGFX_MMIOREG_CAM_ADDR7 0x30300238 #define cfgGFX_MMIOREG_CAM_REMAP_ADDR7 0x3030023c #define cfgGFX_MMIOREG_CAM_CNTL 0x30300240 #define cfgGFX_MMIOREG_CAM_ZERO_CPL 0x30300244 #define cfgGFX_MMIOREG_CAM_ONE_CPL 0x30300248 #define cfgGFX_MMIOREG_CAM_PROGRAMMABLE_CPL 0x3030024c // addressBlock: nbio_nbif0_syshub_mmreg_syshubdec // base address: 0x30300000 #define cfgSYSHUB_INDEX 0x30300020 #define cfgSYSHUB_DATA 0x30300024 // addressBlock: nbio_nbif0_rcc_strap_BIFDEC1 // base address: 0x30300000 #define cfgRCC_BIF_STRAP0 0x30303480 #define cfgRCC_BIF_STRAP1 0x30303484 #define cfgRCC_BIF_STRAP2 0x30303488 #define cfgRCC_BIF_STRAP3 0x3030348c #define cfgRCC_BIF_STRAP4 0x30303490 #define cfgRCC_BIF_STRAP5 0x30303494 #define cfgRCC_BIF_STRAP6 0x30303498 #define cfgRCC_DEV0_PORT_STRAP0 0x3030349c #define cfgRCC_DEV0_PORT_STRAP1 0x303034a0 #define cfgRCC_DEV0_PORT_STRAP2 0x303034a4 #define cfgRCC_DEV0_PORT_STRAP3 0x303034a8 #define cfgRCC_DEV0_PORT_STRAP4 0x303034ac #define cfgRCC_DEV0_PORT_STRAP5 0x303034b0 #define cfgRCC_DEV0_PORT_STRAP6 0x303034b4 #define cfgRCC_DEV0_PORT_STRAP7 0x303034b8 #define cfgRCC_DEV0_PORT_STRAP8 0x303034bc #define cfgRCC_DEV0_PORT_STRAP9 0x303034c0 #define cfgRCC_DEV0_EPF0_STRAP0 0x303034c4 #define cfgRCC_DEV0_EPF0_STRAP1 0x303034c8 #define cfgRCC_DEV0_EPF0_STRAP13 0x303034cc #define cfgRCC_DEV0_EPF0_STRAP2 0x303034d0 #define cfgRCC_DEV0_EPF0_STRAP3 0x303034d4 #define cfgRCC_DEV0_EPF0_STRAP4 0x303034d8 #define cfgRCC_DEV0_EPF0_STRAP5 0x303034dc #define cfgRCC_DEV0_EPF0_STRAP8 0x303034e0 #define cfgRCC_DEV0_EPF0_STRAP9 0x303034e4 #define cfgRCC_DEV0_EPF1_STRAP0 0x303034e8 #define cfgRCC_DEV0_EPF1_STRAP10 0x303034ec #define cfgRCC_DEV0_EPF1_STRAP11 0x303034f0 #define cfgRCC_DEV0_EPF1_STRAP12 0x303034f4 #define cfgRCC_DEV0_EPF1_STRAP13 0x303034f8 #define cfgRCC_DEV0_EPF1_STRAP2 0x303034fc #define cfgRCC_DEV0_EPF1_STRAP3 0x30303500 #define cfgRCC_DEV0_EPF1_STRAP4 0x30303504 #define cfgRCC_DEV0_EPF1_STRAP5 0x30303508 #define cfgRCC_DEV0_EPF1_STRAP6 0x3030350c #define cfgRCC_DEV0_EPF1_STRAP7 0x30303510 // addressBlock: nbio_nbif0_rcc_ep_dev0_BIFDEC1 // base address: 0x30300000 #define cfgEP_PCIE_SCRATCH 0x30303514 #define cfgEP_PCIE_CNTL 0x3030351c #define cfgEP_PCIE_INT_CNTL 0x30303520 #define cfgEP_PCIE_INT_STATUS 0x30303524 #define cfgEP_PCIE_RX_CNTL2 0x30303528 #define cfgEP_PCIE_BUS_CNTL 0x3030352c #define cfgEP_PCIE_CFG_CNTL 0x30303530 #define cfgEP_PCIE_TX_LTR_CNTL 0x30303538 #define cfgPCIE_F1_DPA_SUBSTATE_PWR_ALLOC_0 0x3030353c #define cfgPCIE_F1_DPA_SUBSTATE_PWR_ALLOC_1 0x3030353d #define cfgPCIE_F1_DPA_SUBSTATE_PWR_ALLOC_2 0x3030353e #define cfgPCIE_F1_DPA_SUBSTATE_PWR_ALLOC_3 0x3030353f #define cfgPCIE_F1_DPA_SUBSTATE_PWR_ALLOC_4 0x30303540 #define cfgPCIE_F1_DPA_SUBSTATE_PWR_ALLOC_5 0x30303541 #define cfgPCIE_F1_DPA_SUBSTATE_PWR_ALLOC_6 0x30303542 #define cfgPCIE_F1_DPA_SUBSTATE_PWR_ALLOC_7 0x30303543 #define cfgEP_PCIE_STRAP_MISC 0x30303544 #define cfgEP_PCIE_STRAP_MISC2 0x30303548 #define cfgEP_PCIE_F0_DPA_CAP 0x30303550 #define cfgEP_PCIE_F0_DPA_LATENCY_INDICATOR 0x30303554 #define cfgEP_PCIE_F0_DPA_CNTL 0x30303555 #define cfgPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_0 0x30303557 #define cfgPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_1 0x30303558 #define cfgPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_2 0x30303559 #define cfgPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_3 0x3030355a #define cfgPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_4 0x3030355b #define cfgPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_5 0x3030355c #define cfgPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_6 0x3030355d #define cfgPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_7 0x3030355e #define cfgEP_PCIE_PME_CONTROL 0x3030355f #define cfgEP_PCIEP_RESERVED 0x30303560 #define cfgEP_PCIE_TX_CNTL 0x30303568 #define cfgEP_PCIE_TX_REQUESTER_ID 0x3030356c #define cfgEP_PCIE_ERR_CNTL 0x30303570 #define cfgEP_PCIE_RX_CNTL 0x30303574 #define cfgEP_PCIE_LC_SPEED_CNTL 0x30303578 // addressBlock: nbio_nbif0_rcc_dwn_dev0_BIFDEC1 // base address: 0x30300000 #define cfgDN_PCIE_RESERVED 0x30303580 #define cfgDN_PCIE_SCRATCH 0x30303584 #define cfgDN_PCIE_CNTL 0x3030358c #define cfgDN_PCIE_CONFIG_CNTL 0x30303590 #define cfgDN_PCIE_RX_CNTL2 0x30303594 #define cfgDN_PCIE_BUS_CNTL 0x30303598 #define cfgDN_PCIE_CFG_CNTL 0x3030359c #define cfgDN_PCIE_STRAP_F0 0x303035a0 #define cfgDN_PCIE_STRAP_MISC 0x303035a4 #define cfgDN_PCIE_STRAP_MISC2 0x303035a8 // addressBlock: nbio_nbif0_rcc_dwnp_dev0_BIFDEC1 // base address: 0x30300000 #define cfgPCIE_ERR_CNTL 0x303035bc #define cfgPCIE_RX_CNTL 0x303035c0 #define cfgPCIE_LC_SPEED_CNTL 0x303035c4 #define cfgPCIE_LC_CNTL2 0x303035c8 #define cfgPCIEP_STRAP_MISC 0x303035cc #define cfgLTR_MSG_INFO_FROM_EP 0x303035d0 // addressBlock: nbio_nbif0_rcc_dev0_epf0_BIFPFVFDEC1[13440..14975] // base address: 0x30303480 #define cfgRCC_DEV0_EPF0_RCC_ERR_LOG 0x30303694 #define cfgRCC_DEV0_EPF0_RCC_DOORBELL_APER_EN 0x30303780 #define cfgRCC_DEV0_EPF0_RCC_CONFIG_MEMSIZE 0x3030378c #define cfgRCC_DEV0_EPF0_RCC_CONFIG_RESERVED 0x30303790 #define cfgRCC_DEV0_EPF0_RCC_IOV_FUNC_IDENTIFIER 0x30303794 // addressBlock: nbio_nbif0_rcc_dev0_BIFDEC1 // base address: 0x30300000 #define cfgRCC_ERR_INT_CNTL 0x30303698 #define cfgRCC_BACO_CNTL_MISC 0x3030369c #define cfgRCC_RESET_EN 0x303036a0 #define cfgRCC_VDM_SUPPORT 0x303036a4 #define cfgRCC_MARGIN_PARAM_CNTL0 0x303036a8 #define cfgRCC_MARGIN_PARAM_CNTL1 0x303036ac #define cfgRCC_GPUIOV_REGION 0x303036b0 #define cfgRCC_PEER_REG_RANGE0 0x30303778 #define cfgRCC_PEER_REG_RANGE1 0x3030377c #define cfgRCC_BUS_CNTL 0x30303784 #define cfgRCC_CONFIG_CNTL 0x30303788 #define cfgRCC_CONFIG_F0_BASE 0x30303798 #define cfgRCC_CONFIG_APER_SIZE 0x3030379c #define cfgRCC_CONFIG_REG_APER_SIZE 0x303037a0 #define cfgRCC_XDMA_LO 0x303037a4 #define cfgRCC_XDMA_HI 0x303037a8 #define cfgRCC_FEATURES_CONTROL_MISC 0x303037ac #define cfgRCC_BUSNUM_CNTL1 0x303037b0 #define cfgRCC_BUSNUM_LIST0 0x303037b4 #define cfgRCC_BUSNUM_LIST1 0x303037b8 #define cfgRCC_BUSNUM_CNTL2 0x303037bc #define cfgRCC_CAPTURE_HOST_BUSNUM 0x303037c0 #define cfgRCC_HOST_BUSNUM 0x303037c4 #define cfgRCC_PEER0_FB_OFFSET_HI 0x303037c8 #define cfgRCC_PEER0_FB_OFFSET_LO 0x303037cc #define cfgRCC_PEER1_FB_OFFSET_HI 0x303037d0 #define cfgRCC_PEER1_FB_OFFSET_LO 0x303037d4 #define cfgRCC_PEER2_FB_OFFSET_HI 0x303037d8 #define cfgRCC_PEER2_FB_OFFSET_LO 0x303037dc #define cfgRCC_PEER3_FB_OFFSET_HI 0x303037e0 #define cfgRCC_PEER3_FB_OFFSET_LO 0x303037e4 #define cfgRCC_DEVFUNCNUM_LIST0 0x303037e8 #define cfgRCC_DEVFUNCNUM_LIST1 0x303037ec #define cfgRCC_DEV0_LINK_CNTL 0x303037f4 #define cfgRCC_CMN_LINK_CNTL 0x303037f8 #define cfgRCC_EP_REQUESTERID_RESTORE 0x303037fc #define cfgRCC_LTR_LSWITCH_CNTL 0x30303800 #define cfgRCC_MH_ARB_CNTL 0x30303804 // addressBlock: nbio_nbif0_bif_bx_BIFDEC1 // base address: 0x30300000 #define cfgCC_BIF_BX_STRAP0 0x30303808 #define cfgCC_BIF_BX_PINSTRAP0 0x30303810 #define cfgBIF_MM_INDACCESS_CNTL 0x30303818 #define cfgBUS_CNTL 0x3030381c #define cfgBIF_SCRATCH0 0x30303820 #define cfgBIF_SCRATCH1 0x30303824 #define cfgBX_RESET_EN 0x30303834 #define cfgMM_CFGREGS_CNTL 0x30303838 #define cfgBX_RESET_CNTL 0x30303840 #define cfgINTERRUPT_CNTL 0x30303844 #define cfgINTERRUPT_CNTL2 0x30303848 #define cfgCLKREQB_PAD_CNTL 0x30303860 #define cfgBIF_FEATURES_CONTROL_MISC 0x3030386c #define cfgBIF_DOORBELL_CNTL 0x30303870 #define cfgBIF_DOORBELL_INT_CNTL 0x30303874 #define cfgBIF_FB_EN 0x3030387c #define cfgBIF_INTR_CNTL 0x30303880 #define cfgBIF_MST_TRANS_PENDING_VF 0x303038a4 #define cfgBIF_SLV_TRANS_PENDING_VF 0x303038a8 #define cfgBACO_CNTL 0x303038ac #define cfgBIF_BACO_EXIT_TIME0 0x303038b0 #define cfgBIF_BACO_EXIT_TIMER1 0x303038b4 #define cfgBIF_BACO_EXIT_TIMER2 0x303038b8 #define cfgBIF_BACO_EXIT_TIMER3 0x303038bc #define cfgBIF_BACO_EXIT_TIMER4 0x303038c0 #define cfgMEM_TYPE_CNTL 0x303038c4 #define cfgNBIF_GFX_ADDR_LUT_CNTL 0x303038cc #define cfgNBIF_GFX_ADDR_LUT_0 0x303038d0 #define cfgNBIF_GFX_ADDR_LUT_1 0x303038d4 #define cfgNBIF_GFX_ADDR_LUT_2 0x303038d8 #define cfgNBIF_GFX_ADDR_LUT_3 0x303038dc #define cfgNBIF_GFX_ADDR_LUT_4 0x303038e0 #define cfgNBIF_GFX_ADDR_LUT_5 0x303038e4 #define cfgNBIF_GFX_ADDR_LUT_6 0x303038e8 #define cfgNBIF_GFX_ADDR_LUT_7 0x303038ec #define cfgNBIF_GFX_ADDR_LUT_8 0x303038f0 #define cfgNBIF_GFX_ADDR_LUT_9 0x303038f4 #define cfgNBIF_GFX_ADDR_LUT_10 0x303038f8 #define cfgNBIF_GFX_ADDR_LUT_11 0x303038fc #define cfgNBIF_GFX_ADDR_LUT_12 0x30303900 #define cfgNBIF_GFX_ADDR_LUT_13 0x30303904 #define cfgNBIF_GFX_ADDR_LUT_14 0x30303908 #define cfgNBIF_GFX_ADDR_LUT_15 0x3030390c #define cfgREMAP_HDP_MEM_FLUSH_CNTL 0x30303934 #define cfgREMAP_HDP_REG_FLUSH_CNTL 0x30303938 #define cfgBIF_RB_CNTL 0x3030393c #define cfgBIF_RB_BASE 0x30303940 #define cfgBIF_RB_RPTR 0x30303944 #define cfgBIF_RB_WPTR 0x30303948 #define cfgBIF_RB_WPTR_ADDR_HI 0x3030394c #define cfgBIF_RB_WPTR_ADDR_LO 0x30303950 #define cfgMAILBOX_INDEX 0x30303954 #define cfgBIF_MP1_INTR_CTRL 0x30303988 #define cfgBIF_UVD_GPUIOV_CFG_SIZE 0x3030398c #define cfgBIF_VCE_GPUIOV_CFG_SIZE 0x30303990 #define cfgBIF_GFX_SDMA_GPUIOV_CFG_SIZE 0x30303994 #define cfgBIF_PERSTB_PAD_CNTL 0x303039a0 #define cfgBIF_PX_EN_PAD_CNTL 0x303039a4 #define cfgBIF_REFPADKIN_PAD_CNTL 0x303039a8 #define cfgBIF_CLKREQB_PAD_CNTL 0x303039ac #define cfgBIF_PWRBRK_PAD_CNTL 0x303039b0 #define cfgBIF_WAKEB_PAD_CNTL 0x303039b4 #define cfgBIF_VAUX_PRESENT_PAD_CNTL 0x303039b8 // addressBlock: nbio_nbif0_bif_bx_pf_BIFPFVFDEC1 // base address: 0x30300000 #define cfgBIF_BX_PF_BIF_BME_STATUS 0x3030382c #define cfgBIF_BX_PF_BIF_ATOMIC_ERR_LOG 0x30303830 #define cfgBIF_BX_PF_DOORBELL_SELFRING_GPA_APER_BASE_HIGH 0x3030384c #define cfgBIF_BX_PF_DOORBELL_SELFRING_GPA_APER_BASE_LOW 0x30303850 #define cfgBIF_BX_PF_DOORBELL_SELFRING_GPA_APER_CNTL 0x30303854 #define cfgBIF_BX_PF_HDP_REG_COHERENCY_FLUSH_CNTL 0x30303858 #define cfgBIF_BX_PF_HDP_MEM_COHERENCY_FLUSH_CNTL 0x3030385c #define cfgBIF_BX_PF_GPU_HDP_FLUSH_REQ 0x30303898 #define cfgBIF_BX_PF_GPU_HDP_FLUSH_DONE 0x3030389c #define cfgBIF_BX_PF_BIF_TRANS_PENDING 0x303038a0 #define cfgBIF_BX_PF_NBIF_GFX_ADDR_LUT_BYPASS 0x303038c8 #define cfgBIF_BX_PF_MAILBOX_MSGBUF_TRN_DW0 0x30303958 #define cfgBIF_BX_PF_MAILBOX_MSGBUF_TRN_DW1 0x3030395c #define cfgBIF_BX_PF_MAILBOX_MSGBUF_TRN_DW2 0x30303960 #define cfgBIF_BX_PF_MAILBOX_MSGBUF_TRN_DW3 0x30303964 #define cfgBIF_BX_PF_MAILBOX_MSGBUF_RCV_DW0 0x30303968 #define cfgBIF_BX_PF_MAILBOX_MSGBUF_RCV_DW1 0x3030396c #define cfgBIF_BX_PF_MAILBOX_MSGBUF_RCV_DW2 0x30303970 #define cfgBIF_BX_PF_MAILBOX_MSGBUF_RCV_DW3 0x30303974 #define cfgBIF_BX_PF_MAILBOX_CONTROL 0x30303978 #define cfgBIF_BX_PF_MAILBOX_INT_CNTL 0x3030397c #define cfgBIF_BX_PF_BIF_VMHV_MAILBOX 0x30303980 // addressBlock: nbio_nbif0_gdc_GDCDEC // base address: 0x30300000 #define cfgA2S_CNTL_CL0 0x30303ac0 #define cfgA2S_CNTL_CL1 0x30303ac4 #define cfgA2S_CNTL3_CL0 0x30303b00 #define cfgA2S_CNTL3_CL1 0x30303b04 #define cfgA2S_CNTL_SW0 0x30303b40 #define cfgA2S_CNTL_SW1 0x30303b44 #define cfgA2S_CNTL_SW2 0x30303b48 #define cfgA2S_CPLBUF_ALLOC_CNTL 0x30303b70 #define cfgA2S_TAG_ALLOC_0 0x30303b74 #define cfgA2S_TAG_ALLOC_1 0x30303b78 #define cfgA2S_MISC_CNTL 0x30303b84 #define cfgNGDC_SDP_PORT_CTRL 0x30303b88 #define cfgSHUB_REGS_IF_CTL 0x30303b8c #define cfgNGDC_MGCG_CTRL 0x30303ba8 #define cfgNGDC_RESERVED_0 0x30303bac #define cfgNGDC_RESERVED_1 0x30303bb0 #define cfgNGDC_SDP_PORT_CTRL_SOCCLK 0x30303bb4 #define cfgBIF_SDMA0_DOORBELL_RANGE 0x30303bc0 #define cfgBIF_SDMA1_DOORBELL_RANGE 0x30303bc4 #define cfgBIF_IH_DOORBELL_RANGE 0x30303bc8 #define cfgBIF_MMSCH0_DOORBELL_RANGE 0x30303bcc #define cfgBIF_ACV_DOORBELL_RANGE 0x30303bd0 #define cfgBIF_DOORBELL_FENCE_CNTL 0x30303bf8 #define cfgS2A_MISC_CNTL 0x30303bfc #define cfgNGDC_PG_MISC_CTRL 0x30303c40 #define cfgNGDC_PGMST_CTRL 0x30303c44 #define cfgNGDC_PGSLV_CTRL 0x30303c48 // addressBlock: nbio_nbif0_rcc_dev0_epf0_BIFDEC2 // base address: 0x30300000 #define cfgRCC_DEV0_EPF0_GFXMSIX_VECT0_ADDR_LO 0x30342000 #define cfgRCC_DEV0_EPF0_GFXMSIX_VECT0_ADDR_HI 0x30342004 #define cfgRCC_DEV0_EPF0_GFXMSIX_VECT0_MSG_DATA 0x30342008 #define cfgRCC_DEV0_EPF0_GFXMSIX_VECT0_CONTROL 0x3034200c #define cfgRCC_DEV0_EPF0_GFXMSIX_VECT1_ADDR_LO 0x30342010 #define cfgRCC_DEV0_EPF0_GFXMSIX_VECT1_ADDR_HI 0x30342014 #define cfgRCC_DEV0_EPF0_GFXMSIX_VECT1_MSG_DATA 0x30342018 #define cfgRCC_DEV0_EPF0_GFXMSIX_VECT1_CONTROL 0x3034201c #define cfgRCC_DEV0_EPF0_GFXMSIX_VECT2_ADDR_LO 0x30342020 #define cfgRCC_DEV0_EPF0_GFXMSIX_VECT2_ADDR_HI 0x30342024 #define cfgRCC_DEV0_EPF0_GFXMSIX_VECT2_MSG_DATA 0x30342028 #define cfgRCC_DEV0_EPF0_GFXMSIX_VECT2_CONTROL 0x3034202c #define cfgRCC_DEV0_EPF0_GFXMSIX_VECT3_ADDR_LO 0x30342030 #define cfgRCC_DEV0_EPF0_GFXMSIX_VECT3_ADDR_HI 0x30342034 #define cfgRCC_DEV0_EPF0_GFXMSIX_VECT3_MSG_DATA 0x30342038 #define cfgRCC_DEV0_EPF0_GFXMSIX_VECT3_CONTROL 0x3034203c #define cfgRCC_DEV0_EPF0_GFXMSIX_PBA 0x30343000 #endif ```
```go // contributor license agreements. See the NOTICE file distributed with // this work for additional information regarding copyright ownership. // // path_to_url // // Unless required by applicable law or agreed to in writing, software // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. // beam-playground: // name: Mean // description: Mean example. // multifile: false // context_line: 38 // categories: // - Quickstart // complexity: BASIC // tags: // - hellobeam package main import ( "context" "github.com/apache/beam/sdks/v2/go/pkg/beam" "github.com/apache/beam/sdks/v2/go/pkg/beam/log" "github.com/apache/beam/sdks/v2/go/pkg/beam/transforms/stats" "github.com/apache/beam/sdks/v2/go/pkg/beam/x/beamx" "github.com/apache/beam/sdks/v2/go/pkg/beam/x/debug" ) func main() { ctx := context.Background() beam.Init() p, s := beam.NewPipelineWithRoot() // List of elements input := beam.Create(s, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10) // The applyTransform() converts [input] to [output] output := applyTransform(s, input) debug.Printf(s, "PCollection mean value: %v", output) err := beamx.Run(ctx, p) if err != nil { log.Exitf(ctx, "Failed to execute job: %v", err) } } // Return the mean of numbers from `PCollection`. func applyTransform(s beam.Scope, input beam.PCollection) beam.PCollection { return stats.Mean(s, input) } ```
```xml /************************************************************* * * * * path_to_url * * Unless required by applicable law or agreed to in writing, software * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. */ /** * @fileoverview Implements the interface and abstract class for the InputJax * * @author dpvc@mathjax.org (Davide Cervone) */ import {MathDocument} from './MathDocument.js'; import {MathItem, ProtoItem} from './MathItem.js'; import {MmlNode} from './MmlTree/MmlNode.js'; import {MmlFactory} from './MmlTree/MmlFactory.js'; import {userOptions, defaultOptions, OptionList} from '../util/Options.js'; import {FunctionList} from '../util/FunctionList.js'; import {DOMAdaptor} from '../core/DOMAdaptor.js'; /*****************************************************************/ /** * The InputJax interface * * @template N The HTMLElement node class * @template T The Text node class * @template D The Document class */ export interface InputJax<N, T, D> { /** * The name of the input jax subclass (e.g,. 'TeX') */ name: string; /** * Whether this input jax processes string arrays or DOM nodes * (TeX and AsciiMath process strings, MathML processes DOM nodes) */ processStrings: boolean; /** * The options for this input jax instance */ options: OptionList; /** * Lists of pre- and post-filters to call before and after processing the input */ preFilters: FunctionList; postFilters: FunctionList; /** * The DOM adaptor for managing HTML elements */ adaptor: DOMAdaptor<N, T, D>; /** * The MmlFactory for this input jax */ mmlFactory: MmlFactory; /** * @param {DOMAdaptor} adaptor The adaptor to use in this jax */ setAdaptor(adaptor: DOMAdaptor<N, T, D>): void; /** * @param {MmlFactory} mmlFactory The MmlFactory to use in this jax */ setMmlFactory(mmlFactory: MmlFactory): void; /** * Do any initialization that depends on the document being set up */ initialize(): void; /** * Reset any needed features of the input jax * * @param {any[]} args The arguments needed by the reset operation */ reset(...args: any[]): void; /** * Finds the math within the DOM or the list of strings * * @param {N | string[]} which The element or array of strings to be searched for math * @param {OptionList} options The options for the search, if any * @return {ProtoItem[]} Array of proto math items found (further processed by the * handler to produce actual MathItem objects) */ findMath(which: N | string[], options?: OptionList): ProtoItem<N, T>[]; /** * Convert the math in a math item into the internal format * * @param {MathItem} math The MathItem whose math content is to processed * @param {MathDocument} document The MathDocument for this input jax. * @return {MmlNode} The resulting internal node tree for the math */ compile(math: MathItem<N, T, D>, document: MathDocument<N, T, D>): MmlNode; } /*****************************************************************/ /** * The abstract InputJax class * * @template N The HTMLElement node class * @template T The Text node class * @template D The Document class */ export abstract class AbstractInputJax<N, T, D> implements InputJax<N, T, D> { /** * The name of the input jax */ public static NAME: string = 'generic'; /** * The default options for the input jax */ public static OPTIONS: OptionList = {}; /** * The actual options supplied to the input jax */ public options: OptionList; /** * Filters to run on the TeX string before it is processed */ public preFilters: FunctionList; /** * Filters to run on the generated MathML after the TeX string is processed */ public postFilters: FunctionList; /** * The DOMAdaptor for the MathDocument for this input jax */ public adaptor: DOMAdaptor<N, T, D> = null; // set by the handler /** * The MathML node factory */ public mmlFactory: MmlFactory = null; // set by the handler /** * @param {OptionList} options The options to apply to this input jax * * @constructor */ constructor(options: OptionList = {}) { let CLASS = this.constructor as typeof AbstractInputJax; this.options = userOptions(defaultOptions({}, CLASS.OPTIONS), options); this.preFilters = new FunctionList(); this.postFilters = new FunctionList(); } /** * @return {string} The name of this input jax class */ public get name(): string { return (this.constructor as typeof AbstractInputJax).NAME; } /** * @override */ public setAdaptor(adaptor: DOMAdaptor<N, T, D>) { this.adaptor = adaptor; } /** * @override */ public setMmlFactory(mmlFactory: MmlFactory) { this.mmlFactory = mmlFactory; } /** * @override */ public initialize() { } /** * @override */ public reset(..._args: any[]) { } /** * @return {boolean} True means find math in string array, false means in DOM element */ public get processStrings(): boolean { return true; } /** * @override */ public findMath(_node: N | string[], _options?: OptionList) { return [] as ProtoItem<N, T>[]; } /** * @override */ public abstract compile(math: MathItem<N, T, D>, document: MathDocument<N, T, D>): MmlNode; /** * Execute a set of filters, passing them the MathItem and any needed data, * and return the (possibly modified) data * * @param {FunctionList} filters The list of functions to be performed * @param {MathItem} math The math item that is being processed * @param {MathDocument} document The math document containg the math item * @param {any} data Whatever other data is needed * @return {any} The (possibly modified) data */ protected executeFilters( filters: FunctionList, math: MathItem<N, T, D>, document: MathDocument<N, T, D>, data: any ): any { let args = {math: math, document: document, data: data}; filters.execute(args); return args.data; } } ```
Joy Jittaun Moore is Professor of Biblical Preaching and serves as vice-president for Academic Affairs and Academic Dean at Luther Seminary in St. Paul, Minnesota. Biography A native of Chicago, Moore grew up from South Side, Chicago. Her passion to teaching led her to earn a B.A. in Education and Mathematics at the National College of Education (National-Louis University) in 1982. She attended Commonwealth Community Church in Chicago and experienced a call to ministry there. She received an M.Div. at Garrett–Evangelical Theological Seminary in 1989. Having received a John Wesley Fellowship (2001-2005), she completed a Ph.D. in Practical Theology at Brunel University/London School of Theology in 2007. Moore was the director of Student Life (1999-2001) at Asbury Theological Seminary. She was chaplain and director of Church Relations at Adrian College and has taught at Duke Divinity School. She was Assistant Professor of Preaching between 2012 and 2017 at Fuller Theological Seminary in Pasadena, CA and established its William E. Pannell Center for African American Church Studies in 2015. She was Associate Professor of Practical Theology at Wesley Seminary at Indiana Wesleyan University between 2017 and 2018. Prior to joining Luther Seminary, she has also pastored a historic African American United Methodist congregation in Flint, Michigan. She joined Luther Seminary as Professor of Biblical Preaching in 2019 and picked up the role of vice-president for Academic Affairs and Academic Dean in September 2019. She is an ordained elder of the United Methodist Church and is President of the Wesleyan Theological Society. References Living people National Louis University alumni Garrett–Evangelical Theological Seminary alumni Alumni of the London School of Theology Fuller Theological Seminary faculty Duke University faculty Indiana Wesleyan University faculty Asbury Theological Seminary faculty Adrian College faculty African-American Methodists 20th-century African-American women 20th-century African-American people 21st-century African-American women Year of birth missing (living people)
```css CSS Specificity Change the style of borders using `border-style` Disable resizable property of `textarea` Add `line-height` to `body` `:required` and `:optional` pseudo classes ```
During the history of the Latter Day Saint movement, the relationship between Black people and Mormonism has included enslavement, exclusion and inclusion, official and unofficial discrimination, and friendly ties. Black people have been involved with the Latter Day Saint movement since its inception in the 1830s. Their experiences have varied widely depending on the specific denomination within Mormonism, and the time in history of their involvement. From the mid-1800s to 1978, Mormonism's largest denomination, the Church of Jesus Christ of Latter-day Saints (LDS Church) barred Black women and men from participating in ordinances of its temples necessary for the highest level of salvation, prevented most men of Black African descent from being ordained to the church's lay, all-male priesthood, supported racial segregation in its communities and schools, taught that righteous Black people would be made White after death, and opposed interracial marriage. The temple and priesthood racial restrictions were lifted by top leaders in 1978. In 2013 the church disavowed its previous teachings on race for the first time. The priesthoods of most of the other Mormon denominations, such as the Bickertonite, and Strangite churches, have always been open to members of all races. The same is true in Mormonism's second largest denomination, the Community of Christ (formerly known as the Reorganized Church of Jesus Christ of Latter Day Saints or the RLDS), except for a few years in which Black people were barred from the priesthood. Other, more conservative denominations such as the Fundamentalist Church of Jesus Christ of Latter-Day Saints (FLDS), the Apostolic United Brethren (AUB), and the True and Living Church of Jesus Christ of Saints of the Last Days (TLC) all continue to exclude Black people into modern times. The LDS Church's views on Black people have alternated throughout its history. For example, on teachings about Black slavery, early church leaders went from views of neutrality, to one of anti-slavery, to one of pro-slavery. Since as early as 1844, church leaders taught that Black people's spirits were less righteous in premortality before birth. Mormonism's founder Joseph Smith and his most influential successor as church president, Brigham Young, both stated that Black people's skin color was the result of the Curse of Cain and the Curse of Ham. In the 20th century, many top leaders of the LDS Church vocally opposed the civil rights movement. In recent decades, the LDS Church has officially condemned racism, and it has also increased its proselytizing and outreach efforts in Black communities. It is still accused of perpetuating implicit racism by not apologizing for, acknowledging, or adequately counteracting the effects of its past discriminatory practices and beliefs. Church leaders have worked with the Black civil rights organization the National Association for the Advancement of Colored People (NAACP) since the 2010s, and they have also donated millions of dollars to Black organizations. Estimates state that there are between 400,000 and 1 million Black LDS Church members worldwide, and there are at least five operating LDS Church temples in Africa. Fourteen more temples are in some stage of development or construction in the African continent, in addition to several temples among communities of the African diaspora such as the Dominican Republic and Haiti. In the Community of Christ there are congregations in twelve Africa nations, with African membership steadily increasing. Most of this article focuses on the Brighamite LDS Church, but information on other Mormon denominations are found near the end. Joseph Smith's views on Black people Joseph Smith's views on Black People varied during his lifetime. As founder of the Latter Day Saint movement he included Black people in many ordinances and priesthood ordinations, but held multi-faceted views on racial segregation, the curses of Cain and Ham, and shifted his views on slavery several times, eventually coming to take an anti-slavery stance later in his life. Smith on slavery Initially, Smith expressed opposition to slavery, but, after the church was formally organized in 1830, Smith avoided any discussion of the controversial topic. During the Missouri years, Smith attempted to maintain peace with the members' pro-slavery neighbors, and in 1835, the church decleared it was not "right to interfere with bond-servants, nor baptize them contrary to the will and wish of their masters" nor cause "them to be dissatisfied with their situations in this life." In 1836, Smith published an essay sympathetic to the pro-slavery cause, arguing against a possible "race war", providing justification for slavery based on the biblical Curse of Ham, and stating that Northerners had no "more right to say that the South shall not hold slaves, than the South have to say that the North shall." During the Nauvoo settlement, Smith began preaching abolitionism and the equality of the races. In his presidential campaign, Smith called for "the break down [of] slavery", and wished to free all enslaved persons by 1850. Smith on temple and priesthood access Smith was apparently present at the priesthood ordination of Elijah Abel, a multi-ethnic, man of partial Black heritage, to the offices of both elder and seventy, and allowed for the ordination of a couple of other Black men into the priesthood of the early church. Though Black priesthood holder Elijah Able received his washing and anointing temple ordinance under Smith, he did not receive the temple endowments, and his petition for them was denied over thirty years later, and there is no record of any Black individuals receiving the Nauvoo endowment. After his death, Smith's successor Brigham Young barred Black people from temple endowments and marriage sealings, and from receiving the priesthood. There is no contemporary evidence that would suggest the anti-Black priesthood restriction originated with Joseph Smith. After Smith's death most other Latter-day Saint churches remained open to the ordination of Black people into the priesthood. Smith on equality and segregation Smith argued that Black and White people would be better off if they were "separate but legally equal", at times advocating for segregation. He once stated, "Had I anything to do with the negro, I would confine them by strict law to their own species, and put them on a national equalization." He also said, "They have souls, and are subjects of salvation. Go into Cincinnati or any city, and find an educated negro, who rides in his carriage, and you will see a man who has risen by the powers of his own mind to his exalted state of respectability." Overview of LDS policies and teachings on Black people Pre-existence After Smith's death in 1844 and a six-month succession crisis, his most popular successor became Brigham Young. The Brighamite branch of Mormonism became the LDS Church. By 1844 one of the justifications top LDS church leaders used for discriminatory policies was the belief that the spirits of Black individuals before earth life were "fence sitters" when choosing between God or the devil, or were simply less virtuous than White ones. Brigham Young rejected this pre-existence explanation, but the apostles Orson Pratt, Orson Hyde, and John Taylor all supported the concept, and it gained widespread acceptance among LDS members. A century later in a 1949 official statement the church's highest governing body, the First Presidency, wrote that Black people were not entitled to the full blessings of the gospel, and referenced previous revelations on the preexistence as justification. After the temple and priesthood ban was reversed in 1978, church leaders refuted the belief that Black people were less valiant in the pre-existence. For the first time the church disavowed its previous teachings on race in 2013, and explicitly denounced any justification for the temple and priesthood restriction based on any events which occurred during premortality. Curses of Cain and Ham Teachings on the curse of Cain, the curse of Ham, and their relation to Black people have changed throughout the church's history. Its first two leaders Joseph Smith and Brigham Young both referred to the curse of Ham as a justification for Black enslavement at some point in their lives. Smith believed that dark skin marked people of Black African ancestry as cursed by God. In his revisions of the King James Bible, and production of the Book of Abraham he traced their cursed state back to the curses placed on Cain and Ham, and linked the two curses within the Book of Abraham by positioning Ham's Canaanite cursed posterity as matrilinear descendants of the previously cursed Cain. During Smith's leadership Brigham Young seemed open to Black people holding the priesthood. Later as Smith's successor he used the biblical curses as justification of barring Black men from the priesthood, banning interracial marriages, and opposing Black civic voting rights. He stated that God's curse on Black people would one day be lifted and that they would be able to receive the priesthood sometime after death. According to the Bible, God cursed Adam's son Cain and put a mark on him after Cain killed Abel, though the text does not explicitly state what the nature of the mark was. Smith's canonized scripture the Pearl of Great Price described the mark of Cain as dark skin, and church president Brigham Young stated, "What is the mark [of Cain]? You will see it on the countenance of every African you ever did see". In another biblical account, Adam's eighth great-grandson Ham discovered his father Noah drunk and naked in his tent. Because of this, Noah cursed his grandson Canaan (Ham's son) to be "servants of servants". Although LDS scriptures do not mention the skin color of Ham or that of his son Canaan, some church teachings associated the Hamitic curse with Black people and used it to justify the enslavement of Black people. In 1978, when the church ended the temple and priesthood ban, apostle Bruce R. McConkie taught that the ancient curses of Cain and Ham were no longer in effect. In 2013 church leaders disavowed the idea that Black skin was the sign of a curse for the first time. Patriarchal blessings In the LDS Church, a patriarch gives patriarchal blessings to members describing their biblical lineage in the tribe of Israel, stating their strengths and weaknesses, and advising what the future holds for them. In the 19th and early 20th centuries, members were more likely to believe they were literally descended from a certain tribe of Israel. For Black members of the early LDS church they were sometimes given no lineage or given one from a non-Israelite lineage of Ham. After the 1978 revelation patriarchs sometimes did, and sometimes did not declare lineages for Black members. Some Black members since then asked for and received a new patriarchal blessings which included a lineage. Righteous Black people would become White Early church leaders taught that after death and resurrection everyone in the celestial kingdom (the highest tier of heaven) would be "white in eternity." They often equated Whiteness with righteousness, and taught that originally God made his children White in his own image. Smith reported that in his vision Jesus had a "white complexion" and "blue eyes", a description confirmed in another reported vision by follower Anson Call. A 1959 report by the U.S. Commission on Civil Rights found that most Utah Mormons believed "by righteous living, the dark-skinned races may again become white and delightsome." Conversely, the church also taught that White apostates would have their skins darkened when they abandoned the faith, and until at least the 1960s in the temple endowment ceremony Satan was said to have Black skin. Several Black Mormons were told that they would become White. Hyrum Smith told Jane Manning James that God could give her a new lineage, and in her patriarchal blessing promised her that she would become "white and delightsome". In 1836 Elijah Abel was similarly promised he would "be made ... white in eternity". Darius Gray, a prominent Black Mormon, was told that his skin color would become lighter. In 1978, apostle LeGrand Richards stated that the curse of dark skin for wickedness and promise of White skin through righteousness only applied to Native Americans, and not to Black people. In 2013, the LDS Church published an essay refuting these ideas, describing prior church teachings justifying the restriction as racial "folk beliefs". It stated that Blackness in Latter-day Saint theology is a symbol of disobedience to God and not necessarily a skin color. One youth Sunday School teacher was removed from their position for teaching from this essay in 2015. Slavery Initial Mormon converts were from the North and opposed slavery which caused contention in the slave-allowing state of Missouri. Subsequently, church leadership began distancing itself from abolitionism and sometimes justified the enslavement of Black people through Biblical teachings. During this time, several White people who enslaved Black individuals joined the church and brought their enslaved people with them when they moved to Nauvoo, Illinois. The church taught against influencing enslaved persons to be "dissatisfied with their condition". Eventually, contention between the mostly-abolitionist Latter-day Saints and slave-owning Southerners led to the Mormon expulsion from Jackson County, Missouri in the Missouri Mormon War. Joseph Smith began his presidential campaign on a platform for the government to buy enslaved people into freedom over several years. He called for "the break down of slavery" and the removal of "the shackles from the poor black man", but was killed during his presidential campaign. After Smith's death in 1844, most Latter-day Saints followed Young to Utah in 1847, which was part of the Mexican province of Alta California until 1848. Some Black enslaved people were brought to Utah, though some escaped. Brigham Young began teaching that enslaving people was ordained of God, but remained opposed to creating a slavery-based economy in Utah like that seen in the South. In 1852, the Utah Territory, under the governance of Brigham Young, legalized the purchasing of Black people and Native Americans for enslavement. Under his direction, Utah passed laws supporting this enslavement and making it illegal for Black people to vote, hold public office, join the local military, or marry White people. The slavery laws of Utah contrasted with the existing statutes of the Southern states, in that it only allowed for an enslavement more similar to indentured servitude than to the mass plantation slavery of the South. Twenty-six Black people were enslaved in the Utah Territory according to the 1850 census, and twenty-nine were reported in the one from 1860. Similar to the policies of other territories, one objective of the slavery laws was to prevent Black people from settling in Utah and to control those that remained. Many prominent members of the church enslaved people, including William H. Hooper, Abraham O. Smoot, Charles C. Rich, Brigham Young and Heber C. Kimball. Members bought and sold people as property, gave the church enslaved people as tithing, and recaptured individuals who had escaped their enslavers. In California, Black enslavement was illegally tolerated in the Mormon community of San Bernardino, despite California laws banning the practice. After the Civil War the US government freed enslaved people and allowed many Black adults to vote. By the early 1920s there were hundreds of members of the Ku Klux Klan (KKK) in Utah. Although Church leaders were against the KKK, there were several LDS members involved in the organization. Civil rights and the NAACP After the Civil War, little changed on church stances towards Black people and their rights until the civil rights movement in the 1960s. The NAACP, criticized the church's position on civil rights, led anti-discrimination marches and filed a lawsuit against the church in response to its practice of not allowing Black children to be Boy Scout troop leaders. Students from other schools protested against BYU's discriminatory practices church's racial restrictions. In response, the Church issued a statement supporting civil rights and changed its Boy Scout leader policy. The apostle Ezra Taft Benson criticized the civil rights movement and challenged accusations of police brutality. Black athletes at some schools protested against BYU's discriminatory practices by refusing to play against BYU teams. After the reversal of the temple and priesthood ban in 1978, LDS leaders stayed relatively silent on matters of civil rights for a time. Eventually, they began meeting with and formed a partnership with the NAACP. Beginning in 2017, local church leaders in Mississippi and the NAACP closely worked on projects to restore the NAACP office where Medgar Evers had worked. In 2018, it was announced that the Church and the NAACP would be starting a joint program that provided for the financial education of east-coast residents in larger cities like Baltimore, Atlanta and Camden, New Jersey. In 2019, church president Russell M. Nelson spoke at the national convention of the NAACP in Detroit. In June 2020, a spokesperson for the NAACP stated there was "no willingness on the part of the church to do anything material. ... It's time now for more than sweet talk." In the church's October 2020 general conference, multiple leaders spoke out against racism and called on church members to take action against it. Church president Nelson asked church members to "lead out in abandoning attitudes and actions of prejudice." The same month in a speech at BYU the apostle Dallin H. Oaks broadly denounced racism, endorsed the message of "Black lives matter" (while discouraging its use to advance controversial proposals), and called on church members to root out racist attitudes, behaviors and policies. Segregation During the first century of its existence, the church discouraged social interaction or marriage with Black people, and encouraged racial segregation in its congregations, facilities, and university, in medical blood supplies, and in public schools. Joseph Smith supported segregation, stating, "I would confine them [Black people] by strict law to their own species". Until 1963, many church leaders supported legalized racial segregation with David O. McKay, J. Reuben Clark, Henry D. Moyle, Ezra Taft Benson, Joseph Fielding Smith, Harold B. Lee, and Mark E. Petersen being leading proponents of it. During the years, different Black families were either told by church leadership not to attend church or chose not to attend church after White members complained. The church also advocated for segregation laws and enforced segregation in its facilities such as its Hotel Utah and Tabernacle performances. Church leaders counseled members to buy homes so Black people would not move next to LDS chapels. In 1954, apostle Mark E. Petersen taught that segregation was inspired by God. Leaders also advocated for the segregation of donated blood, concerned that giving White members blood from Black people might disqualify them from the priesthood. Church leaders opposed desegregation in public schools, and in its church-run BYU. Interracial marriage Nearly every decade for over a century—beginning with the church's formation in the 1830s until the 1970s—saw some denunciations of interracial marriage (miscegenation), with most of them focusing on Black–White marriages. The church's stance against interracial marriage held consistent for over a century while attitudes towards Black people and the priesthood and equal rights saw considerable changes. Church leaders' views stemmed from the temple and priesthood policies and racist "biological and social" principles of the time. Under Smith's leadership in Nauvoo it was against the law for Black men to marry White women, and he fined two Black men for violating his prohibition of interracial marriage. On at least three occasions (1847, 1852, and 1865) Smith's successor Young publicly taught that the punishment for Black–White interracial marriages was death, and the killing of a Black–White interracial couple and their children as part of a blood atonement would be a blessing to them. He also stated if the Church were to approve of White intermarriage with Black people it would go on to destruction and the priesthood would be taken away. Until at least the 1960s, the church penalized White members who married Black individuals by prohibiting both spouses from entering temples. In 1978 the temple and priesthood ban was lifted, but the church still officially discouraged any marriage across ethnic lines, though it no longer banned or punished it. Until 2013 at least one official church manual in use had continued encouraging members only to marry other members of the same race. LDS Temple and priesthood restriction Though a few Black men had been ordained to the priesthood under Smith before his death in 1844, by 1849 and continuing until 1978, the Brighamite LDS Church prohibited anyone with real or suspected Black ancestry from taking part in ordinances in its temples, serving in any significant church callings, serving missions, attending priesthood meetings, being ordained to any priesthood office, speaking at firesides, or receiving a lineage in their patriarchal blessing. Non-Black spouses of Black people were also prohibited from entering temples. Because temple ordinances are considered essential to enter the highest degree of heaven, the exclusion meant that Black people were banned from exaltation. Before 1849 a few Black men had been ordained to the priesthood under Smith. Over time, the ban was relaxed so that Black people could attend priesthood meetings and some people with a "questionable lineage" were given the priesthood, such as Fijians, Indigenous Australians, Egyptians, as well as some Brazilians and South Africans with unknown heritage who did not appear to have any Black heritage. In 1978, the church's First Presidency released "Official Declaration 2" which lifted the racial restrictions; this was later adopted as scripture. During the over 120-year span of the restrictions, the church stated they were instituted by God and offered several official race-based explanations for them, including the belief that Cain and his descendants are cursed, that Ham's marriage to Egyptus put a curse on Canaan's descendants, and that Black people were less valiant in their pre-mortal life. Leaders used LDS scriptures to justify their explanations, including the Book of Abraham which teaches that the descendants of Canaan were Black, and the Pharaoh could not have the priesthood because he was one of Canaan's descendants. Since 2013 these previous explanations are no longer accepted as official church teachings and the church teaches anti-racism. History During the early years of the Latter Day Saint movement, at least two Black men held the priesthood and became priests: Elijah Abel and Walker Lewis. Elijah Abel received both the priesthood office of elder and the office of seventy, evidently in the presence of Joseph Smith himself. Historians Armand Mauss and Lester E. Bush, Jr. found that statements on Smith's support of the ban were the result of reconciliation attempts by later church leaders after his death, made to square the differing policies of Smith and those of his successor Young. Sources suggest there were several other Black priesthood holders in the early church, including Peter Kerr and Jamaican immigrant Joseph T. Ball. Other prominent Black members of the early church included Jane Manning James, Green Flake, and Samuel D. Chambers. After Smith's death in 1844, and a six-month succession crisis, Young became leader of the majority of Smith's adherents and led the Mormon pioneers to what would become the Utah Territory. Like many American leaders at the time, Young, promoted discriminatory views about Black people as territorial governor. In 1852, Young made a pronouncement to the Utah Territorial Legislature that "any man having one drop of the seed of [Cain] ... in him [could not] hold the priesthood." Direct commandment of God (Doctrine) vs. Policy Church leaders taught for over a century that the priesthood ordination and temple ordinance ban was commanded by God. Young stated it was a "true eternal principle the Lord Almighty has ordained." In 1949, the First Presidency under George Albert Smith released an official statement saying the restriction "remains as it has always stood" and was "not a matter of the declaration of a policy but of direct commandment from the Lord". A second First Presidency statement twenty years later under David O. McKay re-emphasized that the "seeming discrimination by the Church towards the Negro is not something which originated with man; but goes back into the beginning with God". As president of the church, Spencer W. Kimball stated in 1973 that the ban was "not my policy or the Church's policy. It is the policy of the Lord who has established it." On the topic of doctrine versus policy on the removal of racial restrictions, the apostle Dallin H. Oaks stated in 1988, "I don't know that its possible to distinguish between policy and doctrine in a church that believes in continuing revelation and sustains its leader as a prophet. ... I'm not sure I could justify the difference in doctrine and policy in the fact that before 1978 a person could not hold the priesthood and after 1978 they could hold the priesthood." The research of historians Armand Mauss, Newell G. Bringhurst, and Lester E. Bush has weakened the idea that the ban was doctrinal. Bush commented that there was, in fact, no record of any revelation received by Young concerning the ban. According to Bush, justifications for Young's policies were developed much later by leaders and scholars of the church. The church has since refuted earlier justifications for the temple and priesthood ban and no longer teaches them as doctrine. End of the temple and priesthood bans Throughout its history the LDS church has had a history of major adaptations due to environmental pressures including going from polygamy to monogamy, from political separatism to assimilation with the United States, and from communitarian socialism to corporate capitalism. On June 8, 1978, the LDS Church's First Presidency released an official declaration allowing "all worthy male members of the church [to] be ordained to the priesthood without regard to race or color", and which further allowed Black women and men access to temple endowments and sealings. This was the most significant church policy change in decades. According to the accounts of several of those present, while praying in the Salt Lake Temple the First Presidency and the Quorum of the Twelve Apostles received the revelation to remove the racial restrictions. The apostle McConkie wrote that all present "received the same message" and were then able to understand "the will of the Lord". There were many factors that led up to the change. These included pressure from the NAACP, a growing membership and a temple in Brazil, pressures from member activists, negative publicity, and the need for resolving doctrinal contradictions. Due to the publicity from the publication of Lester Bush's seminal article "Mormonism's Negro Doctrine" in 1973, BYU vice-president Robert Thomas feared that the church would lose its tax-exempt status. The article described the church's racially discriminatory practices in detail, and inspired internal discussion among church leaders as it weakened the idea that the temple and priesthood ban was doctrinal. Some critics say the revelation was a business move to avoid losing church tax-exempt status. Post-1978 teachings regarding the restrictions The 1978 announcement of the removal of racial restrictions did not give reasons for them, nor did it renounce, apologize for, or present new teachings on them. Because these ideas were not officially repudiated, the justifications, ideas, and beliefs that had sustained the restrictions for generations continue to persist as of 2020. Even after the lifting of restrictions the apostle McConkie continued to teach until his death that Black people were descended from Cain and Ham, and that their curse came from God. His influential book Mormon Doctrine, published by the church-owned Deseret Book, continued to perpetuate these racial teachings until it was discontinued in 2010 despite going through many updated editions. In 2005 a church spokesperson told reporters that despite doctrines continuing to circulate among members about why people are Black, church leaders hadn't seen a need for any statements on the topic since 1978. In 2012, Randy L. Bott, a BYU professor, suggested that God denied the priesthood to Black men in order to protect them from the lowest rung of hell, since one of few damnable sins is to abuse the exercise of the priesthood. Bott compared the priesthood ban to a parent denying young children the keys to the family car, and stated, "You couldn't fall off the top of the ladder, because you weren't on the top of the ladder. So, in reality the Black men and boys not having the priesthood was the greatest blessing God could give them." The church responded saying those views do not represent the church's doctrine or teachings, and that BYU professors do not speak on its behalf. The next year the church officially disavowed teachings that Black skin was a sign of a curse for the first time. In a 2016 landmark survey, almost two-thirds of 1,156 self-identified Latter-day Saints reported believing the pre-1978 temple and priesthood ban was "God's will". Non-White members of the church were almost 10% more likely to believe that the ban was "God's will" than White members. In 2022 BYU professor and Young Men general presidency member Brad Wilcox was criticized about parts of a speech in which he downplayed and disrespected concerns about the priesthood and temple ban. Though Wilcox issued two apologies, reporter Jana Riess wrote that his scornful tone and words revealed that he "felt disdainful toward women" and that he believed "God is a racist". Riess called his apologies "not-quite-apologies" and stated they did not go far enough. Videos have surfaced of at least two other instances of Wilcox making similar speeches. W. Paul Reeve stated on the controversy that as of 2022 church leaders have still not clarified whether or not the original ban was divinely inspired, and have not disavowed the actual racial restrictions themselves, thus, resulting in members like Wilcox making controversial remarks. LDS members' views and actions Between the 19th and mid-20th centuries, some Mormons held racist views, and exclusion from temple and priesthood rites was not the only discriminatory practice towards Black people. For example, while mayor of Nauvoo, Smith barred them from holding office or joining the Nauvoo Legion military. Young taught that equality efforts were misguided, stating that those who fought for equality among Black people were trying to elevate them "to an equality with those whom Nature and Nature's God has indicated to be their masters, their superiors". A 1959 nationwide report by the US Commission found that Black people experienced widespread inequality in Utah, and Mormon teachings were used to justify racist treatment of Black people. During the 1960s and 1970s, Mormons in the western United States were close to averages in the United States in racial attitudes. American racial attitudes caused difficulties when the church tried to apply the one-drop rule to other ethnically diverse areas like Brazil where many members didn't understand American classifications of race and how it applied to the temple and priesthood ban, causing a rift between missionaries and members. Anti-Black jokes commonly circulated among Mormons before the 1978 revelation. By the early 1970s, apostle Spencer W. Kimball began preaching against racism calling intolerance by church members "despicable". In a study covering 1972 to 1996, church members in the United States were shown to have lower rates of approval of segregation than other groups in the United States, as well as a faster decline in approval of segregation over the periods covered. Today, the church actively opposes racism among its membership, and is working to reach out to Black communities, and hosts several predominantly Black wards inside the United States. In 2017, the LDS Church released a statement condeming racism in response to the white nationalist Unite the Right rally in Virginia. One Alt-right church member and blogger argued that the statement was non-binding since it only came from the Public Relations Department rather than the First Presidency. White LDS opposition to race-based policies In the second half of the 20th century some White church members protested against teachings and policies excluding Black members from temple ordinances and the priesthood. For instance, three members were all excommunicated by the LDS Church in the 1970s for publicly criticizing these teachings. Other White members who publicly opposed some church teachings and policies around Black people were denied access to the temple over their objections. Additionally, Prominent LDS politician Stewart Udall wrote a strongly worded public letter in 1967 criticizing church racial restrictions. His publication received hundreds of critical response letters, including ones from apostles Delbert Stapley and Spencer Kimball. Racial discrimination after the 1978 ban repeal LDS historian Wayne J. Embry interviewed several Black LDS Church members in 1987 and reported that all the participants reported "incidents of aloofness on the part of white members, a reluctance or a refusal to shake hands with them or sit by them, and racist comments made to them." Embry further reported that one Black woman attended church for three years, despite being completely ignored by fellow congregants. He stated that "she had to write directly to the president of the LDS Church to find out how to be baptized" because none of the other congregants would tell her. After the end of the temple and priesthood ban in 1978, and proclamations from church leadership extolling diversity, racist beliefs in the church continued. White church member Eugene England, a professor at Brigham Young University, wrote in 1998 that most Mormons still held deeply racist beliefs, including the belief that Black people were descended from Cain and Ham and subject to their curses. England's students at BYU who reported holding these beliefs stated they had learned them from their parents or from instructors at church, and did not know they contradicted current church teachings. In 2003, Black LDS Church member Darron Smith noticed a similar problem, and wrote in Sunstone about the persistence of racist beliefs in the LDS church. Smith wrote that racism persisted in the church because church leadership had not addressed the ban's origins. This racism persisted in the beliefs that Black people were descendants of Cain, that they were neutral in the war in heaven, and that skin color was tied to righteousness. In 2007, journalist and church member, Peggy Fletcher Stack, wrote that Black Mormons still felt separate from other church members because of how other members treat them, ranging from being called them the "n-word" in the church and temple, to small differences in treatment. The lack of Black people in LDS Church leadership also contributed to Black members' feelings of not belonging. In 2016 a leader of the LDS-sponsored Black organization Genesis Group, Alice Faulkner Burch, said Black members "still need support to remain in the church—not for doctrinal reasons but for cultural reasons." Burch added that "women are derided about our hair ... referred to in demeaning terms, our children mistreated, and callings withheld." When asked what Black women in the church wanted Burch recounted that one woman had told her she wished "to be able to attend church once without someone touching my hair." In 2020, a printed church Sunday school manual contained teachings about "dark skin" in the Book of Mormon being "the sign of [a] curse", which "curse was the withdrawal of the Spirit of the Lord". Public pressure led the church to change the manual's digital version which subsequently stated the nature and appearance of the mark of dark skin are not fully understood. A few days later, Elder Gary E. Stevenson told a Martin Luther King Day gathering of the NAACP that he was "saddened" by the "error", adding that the Church was "asking members to disregard the paragraph in the printed manual." BYU law professor Michalyn Steele, a Native American, later expressed concern about the church's editorial practice and dismay that church educators continue to perpetuate racism. In the summer of 2020, Nelson issued a joint statement with three top leaders of the NAACP condemning racism and calling for all institutions to work to remove any lingering racism. In the October 2020 general conference, Nelson, his first counselor Dallin H. Oaks, and the apostle Quentin L. Cook all denounced racism in their speeches. In response to a 2016 survey of self-identified Mormons, over 60% expressed that they either know (37%) or believe (25.5%) that the priesthood and temple ban was God's will, with another 17% expressing that it might be true, and 22% saying they know or believe it was not God's will. LDS Black membership The first statement regarding proselyting towards Black people was about enslaved Black individuals. In 1835, the Church's policy was to not proselyte to Black people held in slavery unless they had permission from their enslavers. This policy was changed in 1836, when Smith wrote that enslaved people should not be taught the gospel at all until after their owners were converted. Though the church had an open membership policy for all races, they avoided opening missions in areas with large Black populations, discouraged people with Black ancestry from investigating the church, counseled members to avoid social interactions with Black people, and instructed Black members to segregate themselves when White members complained of having to worship with them. Relatively few Black people who joined the church retained active membership prior to 1978. Proselytization Bruce R. McConkie stated in his 1966 Mormon Doctrine that the "gospel message of salvation is not carried affirmatively to [Black people], although sometimes negroes search out the truth." Despite interest from a few hundred Nigerians, proselyting efforts were delayed in Nigeria in the 1960s. After the Nigerian government stalled the church's visa, apostles decided against proselyting there. In Africa, there were only active missionaries among White people in South Africa. Black people there who requested baptism were told that the church was not working among the them. In the South Pacific, the church avoiding missionary work among native Fijians until 1955 when the church stated they were related to other Polynesian groups and not Black. In Brazil, LDS officials discouraged individuals with Black ancestry from investigating the church. Prior to WWII, proselytization in that country was limited to White German-speaking immigrants. For a time church headquarters had a group of full-time genealogists tasked with determining priesthood and temple eligibility for difficult-to-determine cases. The church instituted a genealogy program to discover Black ancestry, and people's church records were marked if any Black ancestry was discovered. In the 1970s, "lineage lessons" were added to determine if interested persons were eligible for being taught by missionaries. After 1978, there were no restrictions against proselytizing to Black people, and missionaries began entering predominately Black areas of Sub-Saharan Africa. After 1978 Even though the church does not currently keep official records on the racial makeup of its membership, many estimates of the total worldwide number of Black adherents have been made in the 21st century. These estimates include: 400,000 500,000 over 700,000 1 million. Black people have been members of Mormon congregations since the church's founding in the 1830s, but even by 1964 its Black membership was small, with only an estimated 300 to 400 Black members worldwide. In 1970, the church-sanctioned, Black, LDS support group Genesis Group was formed in Salt Lake City, Utah. Since then, Black membership has grown, especially in West Africa, where two temples have been built. In 1990, Helvécio Martins became the first Black general authority of the LDS Church. A 2007 Pew Poll found 3% of LDS respondents in the US identified as Black. In April 2017, the LDS Church announced plans to build a temple in Nairobi, Kenya, bringing the number of temples planned or built in Africa (outside South Africa) to six. In 2017, two Black South African men were called to serve as mission presidents. Under President Russell M. Nelson, the pace of announcement of new temples across Africa picked up. During his first two years as president of the Church, five additional temples were announced for Africa, including two in Nigeria (bringing that country to a total of three temples in some stage of operation or planning), one in the Democratic Republic of the Congo (which was the quickest announcement of a second temple after the dedication of the first for any country other than the United States), and the first temples in Sierra Leone and Cape Verde. Nelson also announced temples in San Juan, Puerto Rico and Salvador, Brazil, both places where large percentages of both church members and the overall population were of Black. In 2009, professor Philip Jenkins stated that in Africa, the growth of the LDS Church has been slower than the growth of other churches due to the White face of the church (a result of the temple and priesthood ban), and the church's refusal to accommodate local customs like polygamy. As of 2020, there had been six men of Black African descent who have been called general authorities and there has been one Black man of African descent appointed as a general officer of the LDS Church. Of these seven men, one was called while Ezra Taft Benson was president of the Church, two during Thomas S. Monson's ten-year tenure as president of the church and four during the first two years Russell M. Nelson was president of the Church. Other Latter Day Saint groups' positions Community of Christ Joseph Smith III, the son of Joseph Smith, founded the Reorganized Church of Jesus Christ of Latter Day Saints in 1860, now known as the Community of Christ. Smith was a vocal advocate of abolishing the slave trade, and a supporter of Owen Lovejoy, an anti-slavery congressman from Illinois, and Abraham Lincoln. He joined the Republican Party and advocated its anti-slavery politics. He rejected the fugitive slave law, and openly stated that he would assist people who tried to escape enslavement. He was a strong opponent of slavery, yet he viewed White people as superior to Black people, and held the view that they must not "sacrifice the dignity, honor and prestige that may be rightfully attached to the ruling races." The priesthood was not available to Black people between 1860 and 1865, and the first Black man was not ordained to the priesthood until 1893. The Community of Christ rejects the Pearl of Great Price. As of 2020 the church has congregations in twelve Africa nations, with Black African membership steadily increasing, despite the Western decline in membership. Fundamentalist Church of Jesus Christ of Latter-Day Saints The president of the Fundamentalist Church of Jesus Christ of Latter-Day Saints (FLDS) Warren Jeffs has made several anti-Black public statements since 2002. These included saying that the devil brings evil to the earth through Black people, that Cain is the father of the Black race, that people with "Negro blood" aren't worthy of the priesthood, that Black-White marriage is evil, and that even marrying someone who has "connections with a Negro" would bring a curse. Apostolic United Brethren The Apostolic United Brethren (AUB) is a Utah-based, Latter Day Saint, polygamous, fundamentalist group that separated itself in 1929. As of 2018 they continue to deny temple and priesthood rites to people with Black heritage, and teach that Black people are "Canaanites" and under the curse of Cain. In 1978 when the LDS church removed the racial restrictions, a reported dozens to hundreds of families left the LDS church for the AUB. Bickertonite The Church of Jesus Christ (Bickertonite) was founded by William Bickerton (and received many Rigdonite followers from Sidney Rigdons branch of Mormonism). It has advocated full racial integration throughout all aspects of the church since its organization in 1862. In 1905, the church suspended an elder for opposing the full integration of all races. Historian Dale Morgan wrote in 1949: "An interesting feature of the Church's doctrine is that it discriminates in no way against ... members of other racial groups, who are fully admitted to all the privileges of the priesthood. It has taken a strong stand for human rights, and was, for example, uncompromisingly against the Ku Klux Klan during that organization's period of ascendancy after the First World War." At a time when racial segregation or discrimination was commonplace in most institutions throughout America, two of the most prominent leaders of The Church of Jesus Christ were Black. Apostle John Penn, a member of the Quorum of the Twelve from 1910 to 1955, conducted missionary work among Italian Americans, and he was often referred to as "The Italian's Doctor". Matthew Miller, who was ordained an evangelist in 1937, traveled throughout Canada and established missions to Native Americans. The church had a mission in Nigeria. Strangite The Church of Jesus Christ of Latter Day Saints (Strangite) was founded by James Strang in 1844 and welcomed Black people into their church during a time when some other factions denied them the priesthood, and certain other benefits that come with membership in it. Strang ordained at least two Black men to his church's priesthood during his lifetime. Though his ethnicity remains unclear from the historical record, James T. Ball was identified as Black at least once, and joined the Strangites in 1849. True and Living Church of Jesus Christ of Saints of the Last Days The Manti, Utah-based True and Living Church of Jesus Christ of Saints of the Last Days (TLC) branched off from the LDS church in 1990 and as of 2008, it adhered to teachings and practices which were similar to the teachings and practices which were historically adhered to by the LDS church, including the Black temple and priesthood ban, the belief that the skin color of apostates would darken, and the practice of polygamy. The TLC's founder James D. Harmston taught his followers that the LDS Church's leader Gordon Hinckley was Cain in a previous life. See also Black people and temple and priesthood policies in the LDS Church Christian views on slavery Criticism of the Book of Mormon Criticism of the Church of Jesus Christ of Latter-day Saints History of African Americans in Utah Mormonism and Pacific Islanders Mormonism and slavery Mormonism and violence Native American people and Mormonism Phrenology and the Latter Day Saint Movement Racial segregation of churches in the United States References Further reading External links BlackLDS.org – Independent (not church-owned or operated) site maintained by some church members. Genesis Group – Church-affiliated organization for serving needs of Black Latter-day Saints. Race and the Priesthood – 2013 statement by the LDS Church renouncing previous teachings and stating the Church's current stances. The Church of Jesus Christ of Latter-day Saints in Africa History of the Church of Jesus Christ of Latter-day Saints Religion and race Christianity and race Mormonism and race Brigham Young Criticism of Mormonism Anti-black racism in the United States Harold B. Lee Library-related 19th century articles Harold B. Lee Library-related 20th century articles
The 1897 Quebec general election was held on May 11, 1897, to elect members of the Legislative Assembly of the Province of Quebec, Canada. The Quebec Liberal Party, led by Félix-Gabriel Marchand, defeated the incumbent Quebec Conservative Party, led by Edmund James Flynn. This marked the start of over 39 consecutive years in power for the Liberals. The Conservative Party never held power again in Quebec, and ceased to exist in 1936 when it merged with the Action libérale nationale to form the Union Nationale, which formed a government later that year. Marchand died in office in 1900, and was succeeded by Simon-Napoléon Parent as Liberal leader and premier. Additional Assembly seat An Act passed in 1895 provided for the Îles-de-la-Madeleine to be separated from Gaspé for the subsequent election, and thus elect their own MLA. Results See also List of Quebec premiers Politics of Quebec Timeline of Quebec history List of Quebec political parties 9th Legislative Assembly of Quebec References Quebec general election Elections in Quebec General election Quebec general election
Maulana Mohammad Merajuddin Mehsud was a Pakistani politician and Islamic scholar who served as members of the 12th National Assembly of Pakistan from 16 November 2002 -02-10-2007. Death He was assassinated on 20 May 2010 in Tank. See also List of Deobandis References Deobandis 2010 deaths Pakistani Islamic religious leaders Pakistani Sunni Muslims Pakistani MNAs 2002–2007 Jamiat Ulema-e-Islam (F) politicians People from South Waziristan
```python """ Code generator script to make the Cython BLAS and LAPACK wrappers from the files "cython_blas_signatures.txt" and "cython_lapack_signatures.txt" which contain the signatures for all the BLAS/LAPACK routines that should be included in the wrappers. """ from operator import itemgetter fortran_types = {'int': 'integer', 'c': 'complex', 'd': 'double precision', 's': 'real', 'z': 'complex*16', 'char': 'character', 'bint': 'logical'} c_types = {'int': 'int', 'c': 'npy_complex64', 'd': 'double', 's': 'float', 'z': 'npy_complex128', 'char': 'char', 'bint': 'int', 'cselect1': '_cselect1', 'cselect2': '_cselect2', 'dselect2': '_dselect2', 'dselect3': '_dselect3', 'sselect2': '_sselect2', 'sselect3': '_sselect3', 'zselect1': '_zselect1', 'zselect2': '_zselect2'} def arg_names_and_types(args): return zip(*[arg.split(' *') for arg in args.split(', ')]) pyx_func_template = """ cdef extern from "{header_name}": void _fortran_{name} "F_FUNC({name}wrp, {upname}WRP)"({ret_type} *out, {fort_args}) nogil cdef {ret_type} {name}({args}) nogil: cdef {ret_type} out _fortran_{name}(&out, {argnames}) return out """ npy_types = {'c': 'npy_complex64', 'z': 'npy_complex128', 'cselect1': '_cselect1', 'cselect2': '_cselect2', 'dselect2': '_dselect2', 'dselect3': '_dselect3', 'sselect2': '_sselect2', 'sselect3': '_sselect3', 'zselect1': '_zselect1', 'zselect2': '_zselect2'} def arg_casts(arg): if arg in ['npy_complex64', 'npy_complex128', '_cselect1', '_cselect2', '_dselect2', '_dselect3', '_sselect2', '_sselect3', '_zselect1', '_zselect2']: return '<{0}*>'.format(arg) return '' def pyx_decl_func(name, ret_type, args, header_name): argtypes, argnames = arg_names_and_types(args) # Fix the case where one of the arguments has the same name as the # abbreviation for the argument type. # Otherwise the variable passed as an argument is considered overwrites # the previous typedef and Cython compilation fails. if ret_type in argnames: argnames = [n if n != ret_type else ret_type + '_' for n in argnames] argnames = [n if n not in ['lambda', 'in'] else n + '_' for n in argnames] args = ', '.join([' *'.join([n, t]) for n, t in zip(argtypes, argnames)]) argtypes = [npy_types.get(t, t) for t in argtypes] fort_args = ', '.join([' *'.join([n, t]) for n, t in zip(argtypes, argnames)]) argnames = [arg_casts(t) + n for n, t in zip(argnames, argtypes)] argnames = ', '.join(argnames) c_ret_type = c_types[ret_type] args = args.replace('lambda', 'lambda_') return pyx_func_template.format(name=name, upname=name.upper(), args=args, fort_args=fort_args, ret_type=ret_type, c_ret_type=c_ret_type, argnames=argnames, header_name=header_name) pyx_sub_template = """cdef extern from "{header_name}": void _fortran_{name} "F_FUNC({name},{upname})"({fort_args}) nogil cdef void {name}({args}) nogil: _fortran_{name}({argnames}) """ def pyx_decl_sub(name, args, header_name): argtypes, argnames = arg_names_and_types(args) argtypes = [npy_types.get(t, t) for t in argtypes] argnames = [n if n not in ['lambda', 'in'] else n + '_' for n in argnames] fort_args = ', '.join([' *'.join([n, t]) for n, t in zip(argtypes, argnames)]) argnames = [arg_casts(t) + n for n, t in zip(argnames, argtypes)] argnames = ', '.join(argnames) args = args.replace('*lambda,', '*lambda_,').replace('*in,', '*in_,') return pyx_sub_template.format(name=name, upname=name.upper(), args=args, fort_args=fort_args, argnames=argnames, header_name=header_name) blas_pyx_preamble = '''# cython: boundscheck = False # cython: wraparound = False # cython: cdivision = True """ BLAS Functions for Cython ========================= Usable from Cython via:: cimport scipy.linalg.cython_blas These wrappers do not check for alignment of arrays. Alignment should be checked before these wrappers are used. Raw function pointers (Fortran-style pointer arguments): - {} """ # Within scipy, these wrappers can be used via relative or absolute cimport. # Examples: # from ..linalg cimport cython_blas # from scipy.linalg cimport cython_blas # cimport scipy.linalg.cython_blas as cython_blas # cimport ..linalg.cython_blas as cython_blas # Within scipy, if BLAS functions are needed in C/C++/Fortran, # these wrappers should not be used. # The original libraries should be linked directly. cdef extern from "fortran_defs.h": pass from numpy cimport npy_complex64, npy_complex128 ''' def make_blas_pyx_preamble(all_sigs): names = [sig[0] for sig in all_sigs] return blas_pyx_preamble.format("\n- ".join(names)) lapack_pyx_preamble = '''""" LAPACK functions for Cython =========================== Usable from Cython via:: cimport scipy.linalg.cython_lapack This module provides Cython-level wrappers for all primary routines included in LAPACK 3.1.0 except for ``zcgesv`` since its interface is not consistent from LAPACK 3.1.0 to 3.6.0. It also provides some of the fixed-api auxiliary routines. These wrappers do not check for alignment of arrays. Alignment should be checked before these wrappers are used. Raw function pointers (Fortran-style pointer arguments): - {} """ # Within scipy, these wrappers can be used via relative or absolute cimport. # Examples: # from ..linalg cimport cython_lapack # from scipy.linalg cimport cython_lapack # cimport scipy.linalg.cython_lapack as cython_lapack # cimport ..linalg.cython_lapack as cython_lapack # Within scipy, if LAPACK functions are needed in C/C++/Fortran, # these wrappers should not be used. # The original libraries should be linked directly. cdef extern from "fortran_defs.h": pass from numpy cimport npy_complex64, npy_complex128 cdef extern from "_lapack_subroutines.h": # Function pointer type declarations for # gees and gges families of functions. ctypedef bint _cselect1(npy_complex64*) ctypedef bint _cselect2(npy_complex64*, npy_complex64*) ctypedef bint _dselect2(d*, d*) ctypedef bint _dselect3(d*, d*, d*) ctypedef bint _sselect2(s*, s*) ctypedef bint _sselect3(s*, s*, s*) ctypedef bint _zselect1(npy_complex128*) ctypedef bint _zselect2(npy_complex128*, npy_complex128*) ''' def make_lapack_pyx_preamble(all_sigs): names = [sig[0] for sig in all_sigs] return lapack_pyx_preamble.format("\n- ".join(names)) blas_py_wrappers = """ # Python-accessible wrappers for testing: cdef inline bint _is_contiguous(double[:,:] a, int axis) nogil: return (a.strides[axis] == sizeof(a[0,0]) or a.shape[axis] == 1) cpdef float complex _test_cdotc(float complex[:] cx, float complex[:] cy) nogil: cdef: int n = cx.shape[0] int incx = cx.strides[0] // sizeof(cx[0]) int incy = cy.strides[0] // sizeof(cy[0]) return cdotc(&n, &cx[0], &incx, &cy[0], &incy) cpdef float complex _test_cdotu(float complex[:] cx, float complex[:] cy) nogil: cdef: int n = cx.shape[0] int incx = cx.strides[0] // sizeof(cx[0]) int incy = cy.strides[0] // sizeof(cy[0]) return cdotu(&n, &cx[0], &incx, &cy[0], &incy) cpdef double _test_dasum(double[:] dx) nogil: cdef: int n = dx.shape[0] int incx = dx.strides[0] // sizeof(dx[0]) return dasum(&n, &dx[0], &incx) cpdef double _test_ddot(double[:] dx, double[:] dy) nogil: cdef: int n = dx.shape[0] int incx = dx.strides[0] // sizeof(dx[0]) int incy = dy.strides[0] // sizeof(dy[0]) return ddot(&n, &dx[0], &incx, &dy[0], &incy) cpdef int _test_dgemm(double alpha, double[:,:] a, double[:,:] b, double beta, double[:,:] c) nogil except -1: cdef: char *transa char *transb int m, n, k, lda, ldb, ldc double *a0=&a[0,0] double *b0=&b[0,0] double *c0=&c[0,0] # In the case that c is C contiguous, swap a and b and # swap whether or not each of them is transposed. # This can be done because a.dot(b) = b.T.dot(a.T).T. if _is_contiguous(c, 1): if _is_contiguous(a, 1): transb = 'n' ldb = (&a[1,0]) - a0 if a.shape[0] > 1 else 1 elif _is_contiguous(a, 0): transb = 't' ldb = (&a[0,1]) - a0 if a.shape[1] > 1 else 1 else: with gil: raise ValueError("Input 'a' is neither C nor Fortran contiguous.") if _is_contiguous(b, 1): transa = 'n' lda = (&b[1,0]) - b0 if b.shape[0] > 1 else 1 elif _is_contiguous(b, 0): transa = 't' lda = (&b[0,1]) - b0 if b.shape[1] > 1 else 1 else: with gil: raise ValueError("Input 'b' is neither C nor Fortran contiguous.") k = b.shape[0] if k != a.shape[1]: with gil: raise ValueError("Shape mismatch in input arrays.") m = b.shape[1] n = a.shape[0] if n != c.shape[0] or m != c.shape[1]: with gil: raise ValueError("Output array does not have the correct shape.") ldc = (&c[1,0]) - c0 if c.shape[0] > 1 else 1 dgemm(transa, transb, &m, &n, &k, &alpha, b0, &lda, a0, &ldb, &beta, c0, &ldc) elif _is_contiguous(c, 0): if _is_contiguous(a, 1): transa = 't' lda = (&a[1,0]) - a0 if a.shape[0] > 1 else 1 elif _is_contiguous(a, 0): transa = 'n' lda = (&a[0,1]) - a0 if a.shape[1] > 1 else 1 else: with gil: raise ValueError("Input 'a' is neither C nor Fortran contiguous.") if _is_contiguous(b, 1): transb = 't' ldb = (&b[1,0]) - b0 if b.shape[0] > 1 else 1 elif _is_contiguous(b, 0): transb = 'n' ldb = (&b[0,1]) - b0 if b.shape[1] > 1 else 1 else: with gil: raise ValueError("Input 'b' is neither C nor Fortran contiguous.") m = a.shape[0] k = a.shape[1] if k != b.shape[0]: with gil: raise ValueError("Shape mismatch in input arrays.") n = b.shape[1] if m != c.shape[0] or n != c.shape[1]: with gil: raise ValueError("Output array does not have the correct shape.") ldc = (&c[0,1]) - c0 if c.shape[1] > 1 else 1 dgemm(transa, transb, &m, &n, &k, &alpha, a0, &lda, b0, &ldb, &beta, c0, &ldc) else: with gil: raise ValueError("Input 'c' is neither C nor Fortran contiguous.") return 0 cpdef double _test_dnrm2(double[:] x) nogil: cdef: int n = x.shape[0] int incx = x.strides[0] // sizeof(x[0]) return dnrm2(&n, &x[0], &incx) cpdef double _test_dzasum(double complex[:] zx) nogil: cdef: int n = zx.shape[0] int incx = zx.strides[0] // sizeof(zx[0]) return dzasum(&n, &zx[0], &incx) cpdef double _test_dznrm2(double complex[:] x) nogil: cdef: int n = x.shape[0] int incx = x.strides[0] // sizeof(x[0]) return dznrm2(&n, &x[0], &incx) cpdef int _test_icamax(float complex[:] cx) nogil: cdef: int n = cx.shape[0] int incx = cx.strides[0] // sizeof(cx[0]) return icamax(&n, &cx[0], &incx) cpdef int _test_idamax(double[:] dx) nogil: cdef: int n = dx.shape[0] int incx = dx.strides[0] // sizeof(dx[0]) return idamax(&n, &dx[0], &incx) cpdef int _test_isamax(float[:] sx) nogil: cdef: int n = sx.shape[0] int incx = sx.strides[0] // sizeof(sx[0]) return isamax(&n, &sx[0], &incx) cpdef int _test_izamax(double complex[:] zx) nogil: cdef: int n = zx.shape[0] int incx = zx.strides[0] // sizeof(zx[0]) return izamax(&n, &zx[0], &incx) cpdef float _test_sasum(float[:] sx) nogil: cdef: int n = sx.shape[0] int incx = sx.shape[0] // sizeof(sx[0]) return sasum(&n, &sx[0], &incx) cpdef float _test_scasum(float complex[:] cx) nogil: cdef: int n = cx.shape[0] int incx = cx.strides[0] // sizeof(cx[0]) return scasum(&n, &cx[0], &incx) cpdef float _test_scnrm2(float complex[:] x) nogil: cdef: int n = x.shape[0] int incx = x.strides[0] // sizeof(x[0]) return scnrm2(&n, &x[0], &incx) cpdef float _test_sdot(float[:] sx, float[:] sy) nogil: cdef: int n = sx.shape[0] int incx = sx.strides[0] // sizeof(sx[0]) int incy = sy.strides[0] // sizeof(sy[0]) return sdot(&n, &sx[0], &incx, &sy[0], &incy) cpdef float _test_snrm2(float[:] x) nogil: cdef: int n = x.shape[0] int incx = x.shape[0] // sizeof(x[0]) return snrm2(&n, &x[0], &incx) cpdef double complex _test_zdotc(double complex[:] zx, double complex[:] zy) nogil: cdef: int n = zx.shape[0] int incx = zx.strides[0] // sizeof(zx[0]) int incy = zy.strides[0] // sizeof(zy[0]) return zdotc(&n, &zx[0], &incx, &zy[0], &incy) cpdef double complex _test_zdotu(double complex[:] zx, double complex[:] zy) nogil: cdef: int n = zx.shape[0] int incx = zx.strides[0] // sizeof(zx[0]) int incy = zy.strides[0] // sizeof(zy[0]) return zdotu(&n, &zx[0], &incx, &zy[0], &incy) """ def generate_blas_pyx(func_sigs, sub_sigs, all_sigs, header_name): funcs = "\n".join(pyx_decl_func(*(s+(header_name,))) for s in func_sigs) subs = "\n" + "\n".join(pyx_decl_sub(*(s[::2]+(header_name,))) for s in sub_sigs) return make_blas_pyx_preamble(all_sigs) + funcs + subs + blas_py_wrappers lapack_py_wrappers = """ # Python accessible wrappers for testing: def _test_dlamch(cmach): # This conversion is necessary to handle Python 3 strings. cmach_bytes = bytes(cmach) # Now that it is a bytes representation, a non-temporary variable # must be passed as a part of the function call. cdef char* cmach_char = cmach_bytes return dlamch(cmach_char) def _test_slamch(cmach): # This conversion is necessary to handle Python 3 strings. cmach_bytes = bytes(cmach) # Now that it is a bytes representation, a non-temporary variable # must be passed as a part of the function call. cdef char* cmach_char = cmach_bytes return slamch(cmach_char) """ def generate_lapack_pyx(func_sigs, sub_sigs, all_sigs, header_name): funcs = "\n".join(pyx_decl_func(*(s+(header_name,))) for s in func_sigs) subs = "\n" + "\n".join(pyx_decl_sub(*(s[::2]+(header_name,))) for s in sub_sigs) preamble = make_lapack_pyx_preamble(all_sigs) return preamble + funcs + subs + lapack_py_wrappers pxd_template = """ctypedef {ret_type} {name}_t({args}) nogil cdef {name}_t *{name}_f """ pxd_template = """cdef {ret_type} {name}({args}) nogil """ def pxd_decl(name, ret_type, args): args = args.replace('lambda', 'lambda_').replace('*in,', '*in_,') return pxd_template.format(name=name, ret_type=ret_type, args=args) blas_pxd_preamble = """# Within scipy, these wrappers can be used via relative or absolute cimport. # Examples: # from ..linalg cimport cython_blas # from scipy.linalg cimport cython_blas # cimport scipy.linalg.cython_blas as cython_blas # cimport ..linalg.cython_blas as cython_blas # Within scipy, if BLAS functions are needed in C/C++/Fortran, # these wrappers should not be used. # The original libraries should be linked directly. ctypedef float s ctypedef double d ctypedef float complex c ctypedef double complex z """ def generate_blas_pxd(all_sigs): body = '\n'.join(pxd_decl(*sig) for sig in all_sigs) return blas_pxd_preamble + body lapack_pxd_preamble = """# Within scipy, these wrappers can be used via relative or absolute cimport. # Examples: # from ..linalg cimport cython_lapack # from scipy.linalg cimport cython_lapack # cimport scipy.linalg.cython_lapack as cython_lapack # cimport ..linalg.cython_lapack as cython_lapack # Within scipy, if LAPACK functions are needed in C/C++/Fortran, # these wrappers should not be used. # The original libraries should be linked directly. ctypedef float s ctypedef double d ctypedef float complex c ctypedef double complex z # Function pointer type declarations for # gees and gges families of functions. ctypedef bint cselect1(c*) ctypedef bint cselect2(c*, c*) ctypedef bint dselect2(d*, d*) ctypedef bint dselect3(d*, d*, d*) ctypedef bint sselect2(s*, s*) ctypedef bint sselect3(s*, s*, s*) ctypedef bint zselect1(z*) ctypedef bint zselect2(z*, z*) """ def generate_lapack_pxd(all_sigs): return lapack_pxd_preamble + '\n'.join(pxd_decl(*sig) for sig in all_sigs) fortran_template = """ subroutine {name}wrp(ret, {argnames}) external {wrapper} {ret_type} {wrapper} {ret_type} ret {argdecls} ret = {wrapper}({argnames}) end """ dims = {'work': '(*)', 'ab': '(ldab,*)', 'a': '(lda,*)', 'dl': '(*)', 'd': '(*)', 'du': '(*)', 'ap': '(*)', 'e': '(*)', 'lld': '(*)'} def process_fortran_name(name, funcname): if 'inc' in name: return name xy_exclusions = ['ladiv', 'lapy2', 'lapy3'] if ('x' in name or 'y' in name) and funcname[1:] not in xy_exclusions: return name + '(n)' if name in dims: return name + dims[name] return name def fort_subroutine_wrapper(name, ret_type, args): if name[0] in ['c', 's'] or name in ['zladiv', 'zdotu', 'zdotc']: wrapper = 'w' + name else: wrapper = name types, names = arg_names_and_types(args) argnames = ', '.join(names) names = [process_fortran_name(n, name) for n in names] argdecls = '\n '.join('{0} {1}'.format(fortran_types[t], n) for n, t in zip(names, types)) return fortran_template.format(name=name, wrapper=wrapper, argnames=argnames, argdecls=argdecls, ret_type=fortran_types[ret_type]) def generate_fortran(func_sigs): return "\n".join(fort_subroutine_wrapper(*sig) for sig in func_sigs) def make_c_args(args): types, names = arg_names_and_types(args) types = [c_types[arg] for arg in types] return ', '.join('{0} *{1}'.format(t, n) for t, n in zip(types, names)) c_func_template = "void F_FUNC({name}wrp, {upname}WRP)({return_type} *ret, {args});\n" def c_func_decl(name, return_type, args): args = make_c_args(args) return_type = c_types[return_type] return c_func_template.format(name=name, upname=name.upper(), return_type=return_type, args=args) c_sub_template = "void F_FUNC({name},{upname})({args});\n" def c_sub_decl(name, return_type, args): args = make_c_args(args) return c_sub_template.format(name=name, upname=name.upper(), args=args) c_preamble = """#ifndef SCIPY_LINALG_{lib}_FORTRAN_WRAPPERS_H #define SCIPY_LINALG_{lib}_FORTRAN_WRAPPERS_H #include "fortran_defs.h" #include "numpy/arrayobject.h" """ lapack_decls = """ typedef int (*_cselect1)(npy_complex64*); typedef int (*_cselect2)(npy_complex64*, npy_complex64*); typedef int (*_dselect2)(double*, double*); typedef int (*_dselect3)(double*, double*, double*); typedef int (*_sselect2)(float*, float*); typedef int (*_sselect3)(float*, float*, float*); typedef int (*_zselect1)(npy_complex128*); typedef int (*_zselect2)(npy_complex128*, npy_complex128*); """ cpp_guard = """ #ifdef __cplusplus extern "C" { #endif """ c_end = """ #ifdef __cplusplus } #endif #endif """ def generate_c_header(func_sigs, sub_sigs, all_sigs, lib_name): funcs = "".join(c_func_decl(*sig) for sig in func_sigs) subs = "\n" + "".join(c_sub_decl(*sig) for sig in sub_sigs) if lib_name == 'LAPACK': preamble = (c_preamble.format(lib=lib_name) + lapack_decls) else: preamble = c_preamble.format(lib=lib_name) return "".join([preamble, cpp_guard, funcs, subs, c_end]) def split_signature(sig): name_and_type, args = sig[:-1].split('(') ret_type, name = name_and_type.split(' ') return name, ret_type, args def filter_lines(ls): ls = [l.strip() for l in ls if l != '\n' and l[0] != '#'] func_sigs = [split_signature(l) for l in ls if l.split(' ')[0] != 'void'] sub_sigs = [split_signature(l) for l in ls if l.split(' ')[0] == 'void'] all_sigs = list(sorted(func_sigs + sub_sigs, key=itemgetter(0))) return func_sigs, sub_sigs, all_sigs def make_all(blas_signature_file="cython_blas_signatures.txt", lapack_signature_file="cython_lapack_signatures.txt", blas_name="cython_blas", lapack_name="cython_lapack", blas_fortran_name="_blas_subroutine_wrappers.f", lapack_fortran_name="_lapack_subroutine_wrappers.f", blas_header_name="_blas_subroutines.h", lapack_header_name="_lapack_subroutines.h"): comments = ["This file was generated by _cython_wrapper_generators.py.\n", "Do not edit this file directly.\n"] ccomment = ''.join(['// ' + line for line in comments]) + '\n' pyxcomment = ''.join(['# ' + line for line in comments]) + '\n' fcomment = ''.join(['c ' + line for line in comments]) + '\n' with open(blas_signature_file, 'r') as f: blas_sigs = f.readlines() blas_sigs = filter_lines(blas_sigs) blas_pyx = generate_blas_pyx(*(blas_sigs + (blas_header_name,))) with open(blas_name + '.pyx', 'w') as f: f.write(pyxcomment) f.write(blas_pyx) blas_pxd = generate_blas_pxd(blas_sigs[2]) with open(blas_name + '.pxd', 'w') as f: f.write(pyxcomment) f.write(blas_pxd) blas_fortran = generate_fortran(blas_sigs[0]) with open(blas_fortran_name, 'w') as f: f.write(fcomment) f.write(blas_fortran) blas_c_header = generate_c_header(*(blas_sigs + ('BLAS',))) with open(blas_header_name, 'w') as f: f.write(ccomment) f.write(blas_c_header) with open(lapack_signature_file, 'r') as f: lapack_sigs = f.readlines() lapack_sigs = filter_lines(lapack_sigs) lapack_pyx = generate_lapack_pyx(*(lapack_sigs + (lapack_header_name,))) with open(lapack_name + '.pyx', 'w') as f: f.write(pyxcomment) f.write(lapack_pyx) lapack_pxd = generate_lapack_pxd(lapack_sigs[2]) with open(lapack_name + '.pxd', 'w') as f: f.write(pyxcomment) f.write(lapack_pxd) lapack_fortran = generate_fortran(lapack_sigs[0]) with open(lapack_fortran_name, 'w') as f: f.write(fcomment) f.write(lapack_fortran) lapack_c_header = generate_c_header(*(lapack_sigs + ('LAPACK',))) with open(lapack_header_name, 'w') as f: f.write(ccomment) f.write(lapack_c_header) if __name__ == '__main__': make_all() ```
are fictional monsters and the antagonists in the Tokusatsu series Garo. Fictional history The Horrors are demons that originate from a . The usual variety of Horrors, called are grotesque black-winged skeletal demons that enter the human world, drawn by their primary "food" of human malice and darkness. They use Inga Gates, objects tainted by darkness from either playing a role in a naturally accumulated atrocity like mass murder or an unresolved traumatic experience. There are also Inga Gates that are created by someone infusing the object with dark energies. Regardless, all Inga Gates are usually activated when person with inner darkness approaches them, with the emerging Horror turning that person or any other living thing nearby into a host body. From there, either taking over the host or forming a symbiosis to act out the host's dark desires, the Horror "evolves" into a unique form based on the Gate they emerged from with personal tastes and feeding habits. Normally a human is dead the moment that an Inga Horror possesses them and what remains of the host follows the Horror in death as well. The Makai Knight Jinga seemingly possessed the unique ability to purge a Horror out of its human host with the human restored to their original self, but it is later revealed that he only suppressed the Horrors, and it only worked due to the original Jinga's machinations. Though rare, there are also some unusual Horrors that prefer to possess objects rather than living things, not having a preference of prey as they consume whoever comes into close contact one way or another instead. But the rarest Horrors are the ones that assume the form of large beasts without needing a host body, acting only on a primal and indiscriminate urge to feed. As revealed in Guren no Tsuki, Horrors have influenced humanity's myths such as the people of Heian-kyō believing them to be Preta. Three commonalities all Inga Horrors share is a preference of hunting at night, their blood marking someone for death as Horrors will have an increased desirability for the afflicted, and speaking in the Makai language which can be understood by someone well-versed in the language or a potential host, usually adopting a human language upon possession. While slain on a regular basis, Horrors can never truly die so long as darkness exists in the hearts of men. Upon a physical death, the Horror's essence is sealed within a Makaiken until its essence is formed into a dagger that is entrusted to a Watchdog to be sent back to the Demon World. Though there is a one night relief in the that occurs once every 20 years to bar any passage of Horrors into the human world, a slain Inga Horror can still return later. Trace essences of slain Horrors latch onto a Makai Knight and accumulate, requiring him to undergo a ritualistic purification periodically. In the case of those who bear the title of Garo, the essence of Horrors that the Garo user slain eventually forms into a Zaji, vowing slay whoever is holding the title of Garo at the moment. While Inga Horrors taken on human forms have no weakness against sunlight and can operate normally during daytime, they have an aversion nonetheless of showing their true forms under broad daylight. As such, Makai Knights almost never need to draw their blades for combat before sundown. While stronger Horrors, especially those evolved to have unique forms and powers, tend to live and hunt alone when they make it into the human world, the weaker ones with no desire to hunt on their own and dependent on others to feed tend to band together and form small community pockets, as revealed in "Garo: Makai Retsuden". Each of these communities have their own hideouts called "forts", despite having no fortifications of any kind. The forts have cages in which humans are kept as livestock to be consumed later. These Horrors are weak enough that a lone Makai Knight prove more than enough to wipe a dozen or two of them out within minutes. Despite their nature as enemies of humanity, some recurrent ones gaining so much notoriety that they are named and documented. Horrors are not always targeted for elimination. At times, they are re-purposed by Makai Priests to serve various functions, such as for sealing of other more powerful Horrors, experimentation, or those like Sedinbale sealed to provide their vast knowledge on various Makai-related matters. Even like Zaruba are created with Horrors that hold no enmity against humanity and have pledged their loyalty to the Makai order, the created items entrusted to certain Makai Knights of prestige. In the events of Yami o Terasu Mono and Zero: Black Blood, given humans as payment for their loyalty as familiars, the Inga Horrors are shown to be significantly weaker as they can be killed by Makai Knights at a quicker pace. These Inga Horrors lack unique Horror forms, mostly seen only in their human form even during battle while some can assume their true usual Horror form. In the events of Versus Road, a new form of Inga Horror is seen as an enemy that hunts down players. These Horrors appear to be modified with cybernetic enhancements, which seem to serve as restraints or control devices. The game world Horrors are shown to be incredibly fast, able to clear large distances in an instant. Despite the slight increase in physical ability granted to them by the game world, the players, being otherwise normal humans, are quickly overwhelmed by even one of these Horrors and generally opt to either flee or hide when encountering one. Messiah the Ultimate Horror is the originator of all Horrors from the and has existed well before the beginning of the conflict between the Makai community and Horrors. Messiah is the most unusual Horror because she is the only Horror that appears almost perfectly human in form, resembling a giant white-skinned half-naked woman with long-clawed fingers and unique jewelry and tattoos around her head and shoulders. Her back contains a Taoist round disc. While the full range of her powers are never revealed, Messiah's abilities include magical shielding, animating her body tattoos into cannons, summoning Horrors by merely touching the ground she walks upon, and flight. Messiah had long desired to enter the human realm but she could not cross through without a large source of energy. After sensing Barago's desperation for power, Messiah reveals herself in a Madō Book that contains forbidden techniques. Though only a shade of her true self, Messiah offers to give Barago the knowledge and power of the forbidden Makai methods in return to bring about the legendary Kiba. Barago wholeheartedly agrees to give up his soul for power and Messiah proceeds to start him on his path of destroying lives to set up the conditions to summon her in her full glory through Kaoru, who is a suitable vessel due to the conditions of her age and birth. But once he fulfills his part in her summoning by removing any trace of humanity in him, upon being awakened Messiah absorbs Barago using Kaoru's body as a medium to use his power to complete the process. Her plans to reach the human world are foiled by Kouga, who enters her realm and defeats her with spiritual help from Kaoru. She is ultimately defeated when, overconfident with her powers, she arrogantly fails to stop Kouga from running his sword into her head after he discards his armor. Shocked at how a normal human has defeated her, Messiah is forced back into her dormant state while releasing Kiba. During the events of Makai no Hana, it is revealed that Messiah can also be summoned to the human world through the blooming of the Demon Beast Eyrith. It becomes the goal of Kouga's son Raiga to prevent the return of one of his father's enemies by hunting down Eyrith with the help of Mayuri. During the events of Kami no Kiba, Rinza reveals she facilitated Jinga's resurrection so she could use him and the God's Fang to create a gate on the Moon to summon Messiah. After the God's Fang was destroyed, Messiah awakens from her dormant state in the Makai and is confronted by Jinga in his Horror form. Kami no Kiba: Jinga would reveal that Messiah destroyed Jinga, causing his reincarnation into a human. Messiah is portrayed by . In Kiba Gaiden, she is voiced by in a flashback and while possessing her body. Garo These are the Horrors that appear during Garo. : The 12th Horror to appear, Anglay is a trapper able to bring artwork to life. The Horror poses as a female nude portrait within a painting until the gallery owner, , finds it and is possessed by it. The monster has a taste for young women, liquifying them into paint for consumption, and targets Kaoru. But Kouga's appearance forces the monster to lock down the art exhibit. In the fight with Kouga, Anglay bursts out from its host and manifests itself into a painting, gaining an acidic paint-muck exterior with a frame collar until it regresses to its original form. Garo kills it and Kaoru stained by the Horror's blood as a result. Taniyama is portrayed by . : The 13th Horror. Emerging from the "Chain Gate", it possesses the body of , a con-woman who takes advantage of money-minded people using an IT company as a front. Using its host's plan, Ishutarb uses money to lure it victims to meet it at nighttime. From there, it would rip them to shreds with chains shooting from Kujō's body and ingest the pieces caught by its chains' links. it is about to kill Kaoru when dumb luck and Kouga stops her. During the fight, Ishutarb alters it host's form into an iron maiden-like armored form. Garo kills it in a parking lot. Kujō is portrayed by . : A unique Horror that has no need for a human host, once said to have wiped out an entire village in one night. Possessing a time-piece, altering it into a variety of forms, Morax lures those driven by time to pick him up. Once he has a hold on his victim, by after dusk, it dehydrates the victim until only dust remains. Forced to use humans as host, Morax takes advantage of Kouga's sympathy for humans to escape. Once he captures Kaoru, Morax assumes the form of a clock tower. Though he is armed with arsenal of bladed arms, Morax is killed finally by Garo, ripped out of his vessel as it crumbles to the ground. : A Horror that first appeared around the time Taiga was alive. It takes over the body of , making him a miracle worker of a surgeon so Pazuzu can feed on the euphoria-enriched blood of Tategami's patients. it slices them apart with the scalpel-bladed tendrils from the back of its head, while leaving the remains for its Horror minions. To ensure it could eat without interference, it erects a barrier to put any Makai Knight at a disadvantage. Kouga has trouble until he uses Kaoru to remove the seals that power the barrier. Upon Pazuzu's last moments, it pleas to devour Kaoru as its last meal. Utterly repulsed by this idea, Garo delivers the final blow, thus ending its reign of terror. Tategami is portrayed by . : A moth demon, possessing a woman who tries to commit suicide as the result of a man's insensitivity. it remains dormant in it zombified host until the full moon, when its bloodlust is at its zenith. During the fight, Garo realizes that the host is nothing more than a puppet composed/filled with moths. The actual Lunarken is the orb like weapon the puppet uses in its attacks. Lunarken is portrayed by . : A corpse-like Horror that appears in a graveyard and possesses the body of a middle-aged prostitute named , making her young again and giving her a beautiful body. In return, Kotomi uses her beauty to lure men for the Horror to devour, using the eyes as a medium to suck the life out of the victim's body before he explodes. In battle, she could launch graveyard tombs to attack Kouga & Rei before Utoque takes over. Once Utoque is killed by Garo, Kotomi is fatally wounded, and begs for help. But Garo states that she is already dead because she has allowed the Horror to possess her in the first place, and her body soon disintegrates. Kotomi is portrayed by , while her original form is portrayed by . : A Horror that is attracted to the sadness of , a woman who killed six young men and collected their fingers after her pianist boyfriend committed suicide for being robbed of his dream. The Horror rapes/possesses her, using her intent to kill a remaining four men for their fingers while eating the rest. In its true-form, Moloch's body is two-toned (flaming on the left, icy on the right) with control over the elements of ice and fire, launching its hands to attack its enemies or kill its victims. Garo kills Moloch, with only the ring Miri had from her boyfriend remaining. Later the father of Miri, obtains the ring, along with the Horror's essence dagger and special bullets forged from other purified blades. Intent on revenge for his daughter, Yūki uses the bullets to create a pack of Horrors to help him kill Kouga. But after they are all killed, and he is denied death, Yūki stabs himself and became Moloch's new host. However, Yūki feels the pain that his daughter suffered and has Garo end his misery before the demon fully consumes him. Miri is portrayed by , while Yūki is portrayed by . : A Horror that manifests from construction rubble to become a giant with strong armored body that seems invulnerable to the Garouken. Garo manages to kill it with the aid of Gōten and the Garou Zanbaken. : A clown-like Horror that possesses the body of an unnamed clown. Using the red nose and its puppets, Asmodai forces its victims to show "their nature", turning them against each other in a fight to the death, while laughing all the way. Once they are dead, it turns them into beach balls to ingest. It is giant-sized in his true form, using its arms for locomotion. Though its attempts to con Garo out of similar ideologies, it is killed when Zero lops off its red nose. The clown is portrayed by . : A neon-green stag beetle Horror that possesses a con artist gambler named , tricking people to play a fixed coin game and after they lost, sealed their souls inside a coin. After its takes Kaoru, it brings Kouga into its alternate realm with three games of chance to save Kaoru's soul. After the third, Dantarian assumes its true form out of rage to lower itself to physical combat and is defeated by Garo. However, the Horror sets up a final challenge for Kouga upon its death that Kouga manages to succeed. Kunugi is portrayed by . : A Horror that appeared during Taiga's time as Garo. Possessing the body of an , he befriended Kouga whom he used as a shield to protect himself from Taiga, but Taiga mortally wounded the host so that the Horror ripped itself out, resembling a reddish version of its original form, in an attempt to kill Taiga. It was from that ordeal that Kouga understood the treacherous nature of a Horror. The old toymaker is portrayed by . : A Horror that possessed a vehicle. : A Horror that takes the body of , a sculptor who sold his soul to the "devil" to possess the "Hands of God" so he could create the ideal sculpture. Using his "gift", Kuramachi creates voodoo sculptures to torture his victims (young women) to death before sucking them down face first. He attempts to kill Kaoru when she hopes to learn more of her father through him, as she thinks Kuramachi had met her father. However, she finds out Kuramachi actually never met Yūji Mitsuki and was only inspired by his work. Gargoyle is killed by Zero, with a dying Kuramachi in awe of finally finding his "ideal piece" just before Zero kills him. Kuramachi is portrayed by . : A Horror that possesses a fish, its uses a shut-in programmer whom its befriends to get its prey, killing women dumped into its tank and taking their attributes to become more human and move about on land without trouble. Tonuma is about to feed Kaoru to Haru as the final victim when Kouga arrives and exposes Haru, and kills the weakened monster, much to Tonuma's dismay. Though tempted to kill Tonuma, Kouga manages to control his anger and only knocks him unconscious. Haru's final words, how Kouga uses Kaoru to get to her, causes a rift between Kaoru and Kouga. Haru's human form is portrayed by miko. : A Horror born from the twelve purified blades containing the invading Horrors Kouga and Rei defeated. Much larger than others, Garo and Zero are unable to defeat it. In the end, the monster is killed/absorbed by Barago. : A skeleton gunman, created from , a security guard for a museum owned by Yuki Kamisugawa, using one of the special bullets made from Horror essences provided by the Watchdogs, in his attempt to avenge his daughter's death on Kouga. Tochino is portrayed by . Byakuya no Maju Garo Special: Byakuya no Maju features new types of Horrors and dark forces. Eruzu is an arachnid Horror that possesses a young girl, using its host to target aggressive men. Its abilities, other than spider-related powers, include each surviving piece of its body being able to regenerate into a new Horror. This power means that Garo cannot simply cut it down and has to burn it, using his Blazing Armament technique. Legules is a Horror that has existed for over 1,000 years. The Makai community has no recorded history and his movements have no records. One thousand years ago during a solar eclipse, Legules successfully crossed through the barrier between worlds and revived his followers known as the Legules Family. Many Makai Knights and Makai Priests died that day in order to suppress the Horrors that Legules unleashed on humanity. To make sure that the catastrophe would never happen again, the Makai Priests created the Phosphorus Arrow to destroy the barrier and seal away Legules. One thousand years later, Legules manages to find another gateway to return to the human realm by assimilating a dead body to make it his own. Legules is not the usual variety of Horror, as he is seemingly demi-human and possessing elementals similar to Oni or Yokai. He quickly begins building forces of his own by converting Horrors and a human into "his family". He then attacks Kantai during the night to find the Phosphorus Arrow so that he can complete his task of reviving his family. He tries to convert everyone, including the Madōgu of each Makai Knight, to join his forces. Tsubasa's Madōgu Goruba somehow gets possessed and Legules controls his bracelet body. When the night raid fails, he transfers himself into Goruba during the day and comes when people least suspect anything wrong. Legules takes the arrow and Rin Yamagatana with him, as he needs her blood to activate the arrow. Legules's capabilities include, and are not limited to, bodily assimilation, dark magic, immunity to regular physical attacks, human energy absorption, body transference, martial arts, ultra human strength, ultra healing, body parts that can move without attachment, and biological transfiguration. Once the eclipse begins, Legules transformed himself into his true form, a giant metallic skeleton-like Horror. In this form, he is able to transform into a bladed metal wasp. Legules is defeated when Garo throws the Phosphorus Arrow into him and destroys the barrier at the same time. With Legules destroyed, the demon family vanishes. Legules is portrayed by and is voiced by . Aomushi is a murderer who is trying to dispose of a body that Legules takes over. Aomushi is given the chance to live by becoming a servant to him. Legules fires demonic energies from his eyes to the man's eyes, transforming Aomushi into a member of the Legules Family. Though not possessed, Aomushi counts as a Horror because he serves as an extension of Legules like those he converts. His capabilities are cloaking and being acrobatic. He eventually suffers a severe injury in combat from Tsubasa and Legules finishes him off as he has no use for him, reverting Aomushi to his original form. Aomushi is portrayed by and is voiced by . Karakuri are Horrors that are changed by Legules. Legules carries with him demonic masks and transforms live Horrors into his Legules family foot soldiers. Just like regular Horrors, they are able to enter humans and take control of them. However, they seem to be unable to blend in naturally as the regular Horrors can behave like a normal person. Their movements are very mechanical and move almost like karakuri puppets. They have high regenerative capabilities, bladed weapons as arms, and seem to have a ninja-like combat method. Their combat potential and strength is not above a regular Horror, but Horrors act independently as these Horrors serve a master. They do not speak, but merely make sounds and shift their eye sockets up and down as they react to their environment. Their body parts are known to function on their own even though if dismembered. They are all destroyed as the result of Legules's death. Red Requiem Garo: Red Requiem features two of , the generic name for seven powerful Horrors who are near equal to Messiah, and their followers. Karma is a and one of the Apostle Horrors who lives in a mirror rather than human hosts, though she can turn a human into a Horror familiar if their darkness is great enough. She consumes human souls by showing illusions of their greatest desires, drawing them into her mirror realm and turning their bodies into piles of broken mirror shards to ingest with their souls trapped in the mirror world. Among her victims are untold numbers of Makai Knights who came to slay her, only to be defeated and devoured. Karma is able to jump from mirror to mirror if the one she is currently housed in is destroyed. The sorrows and hatreds of people consumed by her are used for her as childlike and the shadowy . Eventually, forced to fight Garo, Karma assumes a giant mirror-shard themed harpy form while trying to convince Garo to swear loyalty to her in return for immortality. However, empowered by the fallen Makai Knights' souls within the realm, Garo destroys Karma. Karma is portrayed by and is voiced by . Babel is a and one of the Apostle Horrors, a gigantic bull-like beast with a large headpiece resembling a guillotine with a blindfolded, naked human female form mounted on its front. The blade of the headpiece, tethered by the chains running through the Horror's body, can be launched. Unlike other Horrors, Babel is a cannibal and feeds on its own kind, posing as an infant in a carriage before being found out and destroyed by Garo. Kurusu is a Horror under Karma. Originally an elderly painter named , Kurusu was driven mad by the death of his lover, Shion. He eventually snaps and kills a girl he was using as a model for a painting, trying to emulate Shion onto her. Karma, hearing his anguish, transforms him into a Horror, restoring his youth, and revives the said girl's corpse in Shion's image. In his human form, Kurusu fights with a large sword, holding it in a reverse grip. His Horror form is a large, skeletal creature composed half of bone and half of a fleshy substance. Finding Shion dead, Kurusu goes after the Kouga and Rekka while refusing to accept his love for the girl is a lie before being destroyed by Garo. Kurusu is portrayed by , his original form portrayed by . Shion is a Horror under Karma. In reality, she is a Horror created from the corpse of a girl Kurusu murdered prior to his transformation and altered to resemble the real Shion who died long ago. Her Horror form is not monstrous like most, only possessing a single white wing and an angelic outfit. She is killed by Rekka, her body lasting long enough for Kurusu to find before it dissolves into feathers. Shion is portrayed by . Baul is a Horror that possesses the body of a woman and carries around the Apostle Horror Babel. Baul is killed by Rekka. The possessed woman is portrayed by . Kiba These are the Horrors that appeared in Kiba Gaiden. Garius and Blade and are two Horrors that were among the many that were absorbed by Kiba. While Garius is a serpentine flyer, Blade is a giant mantis-like monster. Kokuryū is a dragon-like Horror that exists within the mind of Barago in Kiba Gaiden and exists in a space produced by Sigma Fudō in Makai Senki. Gyanon is one of strongest Horrors in existence, labeled as and the . Having seemingly died, the Makai Senate sent a group of three Makai Knights and one Makai Guide to retrieve the monster's corpse from Amber Rock Valley. However, Barago also sought the Horror and Gyanon was nowhere to be found by either party. It is revealed in Makai Senki, that Sigma Fudō had stolen Gyanon as he intends to utilize the Horror in powering up his Magōryū Idea while reviving the fiend with large numbers of human sacrifices. To achieve this goal, Sigma obtains the pelt of a Spirit Beast to ensure the revived Gyanon is under his complete control while infusing Kouga's body and soul into the Horror to complete his resurrection. Though Kouga is freed, Gyanon awakens after Idea's creation in response to Sigma's darkness, devouring him and assimilating the ultimate Gōryū while assuming his androgynous human-like form. While telling Garo that his resurrection was unplanned, Gyanon intends to take advantage to bring all Horrors into the human world. However, Idea is destroyed with the Makai Knights and Madou Priests joining forces with Gyanon reduced to a head as Garo destroys the bodiless Horror. Gyanon is portrayed by . Makai Senki These are the Horrors that appear in Garo: Makai Senki. : A tricky that inhabits an antique cigarette lighter owned by a murderous military officer, his method of feeding being to invoke internal combustion in his victims and swallow the airborne ashes. Cigarien's lighter eventually ends up in the possession of , a petty crook who makes an enemy out of a mob boss named Katagiri by stealing his money. Making Anan an offer to save him in return for his soul, Cigarein possesses the man before slaughtering Katagiri and his entourage. Cigarein then proceeds to devour those who are considered to be scum of society before being found by Kouga. Though he repeatedly tries to weasel out of his fight with Kouga, Cigarein is forced to assume his true war-themed armored form before Garo cuts him down. Anan's soul endures a bit before Garo stabs the soul into oblivion. Anan is portrayed by . : A that inhabits a streetlight in an area once used for unsavory executions, able to use heat and light in her attacks. Luzagin possesses the body of , a vain yet dirty homeless woman who desires handsome men to the point of murdering them so she can have them. Acting on Ichikai's desires, Luzagin goes to captures ideal men, mutilating their bodies before freeze-drying them to add to her collection. However, she has strict physical requirements on who makes it to her collection, and devours through their shadows those who do not "pass". She eventually fights Kouga, forced to assume her true form before being cut down and left to die from the fatal wound. Ichikai is portrayed by . : A Horror that is terrorizing the road by murdering those who travel through a tunnel. He is destroyed by Reo with the Gōryū Colt. : Reo's Gōryū Colt which he uses to destroy the Horror Melgis. However, wounded during the fight, some of Reo's blood ends up on Colt and awakens its Horror-based instinct as it possesses a motorcycle and enhances it with multiple weapons. Eventually, Garo manages to destroy the Horror core and forces Colt out of the motorcycle. : A bird-based Horror that possesses the body of a gambler named , using his host to invite various gamblers to an underground casino on an island maintained by his Horror familiars. There, he has the gamblers play a life-and-death poker game where he uses his Joker card to send his victims into a limbo, where he can eat at his leisure along with those dear to the victim if they borrow chips from the house. However, posing as one of the guests, Kouga destroys the Joker card to release those among the victims still living and then the Horror himself. Kid is portrayed by . : A venus flytrap-headed that emerges from a gate that manifests from a manhole cover which was manufactured by , an artistic metal caster who left his wife to die under a manhole prior to the cover's creation. Possessing the body of a woman, and converting her host into the shaded woman in black, Death Hole uses Kijima to mass-produce more of the manhole covers to bring more of her kin into the world. However, while Death Hole meets her end against Garo, Kijima faces his own horrific end at the hands of his wife's specter. Kijima is portrayed by , while the woman in black is portrayed by Hiromi Eguchi. : A Horror that inhabits a tree which and his wife grew from a seed that they found among the belongings of their son , a wartime photographer who was killed in action. The two proceed to invite people who pass by into their house for a meal. They then poison their guests and bury them under the tree which casts an illusion of "Masato" under the moonlight which acts on the couple's stronger memory of him. Rei is invited for dinner and later poisoned as well. However, immune to poison, Rei confronts Erinnerung as it personally attacks him and kills the Horror with the couple heartbroken. Erinnerung is voiced by . : A Horror that possesses the body of a security guard before being slain by Zero. : A Horror that inhabits a katana, originally owned by a man named who was turned into a Horror familiar. But one day, a skilled swordsman named finds Ukyō and cuts him down. Having seen a Makai Knight in his youth, yet unaware of his identity, Jūzō had made it his life's goal to search for an opponent like that figure. But suffering from an illness and have little time left to live, Jūzō accepts Kagemitsu's offer of a second chance in life in return to give him the blood of living people. It takes the Horror several centuries to heal Jūzō, placing the samurai in suspended animation before reviving him in the modern era. However, as he follows bushidō, Jūzō is disappointed that he cannot find someone strong to fight with until he finds Rei by chance and challenges him. But as Kagemistu refuses to allow him to use the sword until he draws blood, Jūzō is forced to fight Rei with makeshift bokkens made from broomsticks. The duel cannot be truly concluded as Jūzō's symptoms resurface and Rei admits defeat, with Jūzō learning fully of the Makai Knights from Kagemitsu as the Horror demands blood if the human wants his help to maintain his health as well as using his sword. Still refusing to cut any innocent down to honor his pact, Jūzō commits seppuku instead to quench the blade's thirst, along with absorbing the horrified Kagemitsu, becoming his host. Surprisingly, as noted by Silva, Jūzō remains in control of his body as he forces Rei to resume their duel as Horror and Makai Knight, though Rei sees that the samurai had potential to become a Makai Knight, due to the surprising fact of being able to pick up one of Rei's swords without trouble despite having never touched Soul Metal before. Jūzō is eventually slain, dying with satisfaction that he was defeated by the blade of one stronger than him. But learning of Kouga as an even stronger fighter, Jūzō hands Rei his wakizashi before turning into ash. Igari is portrayed by and Kagemitsu is voiced by . : A Horror that inhabits a makeup box, altering appearances to whatever suits him. Agturus possesses the body of , an aged frail janitor at a theater who was once a star stage actor in the play The Sword of Arcite. His frustration over a flamboyant actor ruining the play as the lead attracts the Horror. After being possessed with his youth restored, Ryūnosuke devours the other actor and takes the stage for his own. Kouga eventually buys all the tickets to one of his plays one night to have a showdown with him, eventually cutting him down. Takamine is portrayed by . : A serpentine that flies at fast speeds. Sent to kill it, Kouga is forced to wait the Horror out before slaying it. : A Horror that appears at the site of a traffic accident where she possesses the nearby dead body of , a pâtissière who was forcing her daughter to follow in her footsteps. When Misao attempts to commit suicide to escape the pressure, Toshiko sacrifices herself to stop her daughter prior to being possessed. Using Toshiko's body, Yashual assumes her host's identity and uses Misao's guilt to manipulate her. The Horror is eventually found and slain by Rei, though the deed pained him a bit as he is forced to leave Misao heartbroken. Toshiko is portrayed by , while Misao is portrayed by . : A Horror from Kouga's childhood, who devoured the friends he made during his training under Wataru Shijima. In the present day, Kouga crosses paths with Raizon and avenges his friends' deaths by slaying Raizon personally. In Gold Storm Sho, a Raizon appeared in the flashback of Jinga's story. : An ancient Horror who can use word characters in her abilities and attacks, using printed words as gates. Due to her vast Makai-related knowledge, Sedinbale is sealed with a Madō Book instead of being destroyed so Makai Priests can gain access to her knowledge. However, breaking Sedinbale's seal, the red-masked man has the Horror help him translate the old Makai script in his possession before allowing the Horror to act on her whim. Being pursued by Rekka and Kouga, Sedinbale takes the body of a young woman who surrounds herself in depraved words before targeting Kaoru. Revealing Kouga's condition with Kaoru present, Sedinbale battles Garo and Rekka before they manage to rip the main character from the Horror's body and seal it into a Madō Book. The possessed woman is portrayed by Asami. Yami o Terasu Mono : Portrayed by . : A large Horror that can uses its brute strength and scorpion tail tongues to attack an opponent. During the events of Yami o Terasu Mono, a Palkeira in Vol City over gorged on humans and was trapped underground, using one of its two disembodied hands into a naked woman as an effective lure before it was destroyed by the Makai Knights. The naked woman is portrayed by . : A man who becomes the vessel of a Horror that emerges from a radio. Danda is portrayed by Namihei Koshige. : An overweight Horror who is normally weak until exposure to Shin's music gives him a power boost. Portrayed by Man (8): Portrayed by . : A teacher who became the vessel of a Horror that devours students periodically, sparing only those she considers promising. However, Ms. Toyama is forced to consume Haruka Kitajima and her family when the girl witnesses her true form. With the aid of Haruka's classmate Hiroki Tsuboi, Ryuga slays Ms. Toyama with her death covered up. Portrayed by . : A Horror in the service of the Kaneshiro Group who is based at the nightclub Paradaice. Able to read the minds of others and assume the form of what they desire, Boara lulls her victims into a moment of weakness and turns them into a vapor she consumes. Her victims are mostly men who the Kaneshiro Group are disposing of before Ryuga and Rian destroy Boara and her business. Portrayed by Nao Oikawa, while her naked young woman, mature woman, and plump woman forms are portrayed by , , and . : A violinist who became the vessel of a Horror that devoured an opera singer before being found and killed by Takeru and Aguri. Portrayed by . : Tousei Kaneshiro's mother, a fallen Makai Priestess who was left to care for her child after her lover Kensui Kaneshiro abandoned them. Becoming a Vol City resident, Karen raised Tousei to believe that he is destined for greater things. However, while entertaining her guests, Karen ends up being possessed by a Horror that her teenage son deliberately summoned into their home. Portrayed by . Madō Horrors are a unique form of Horror first created by Zedom by infusing human bodies with Horror Seeds, which germinate into Madō Horror Plants that spread across the body. As a result, unlike regular Horrors, Madō Horrors are born directly within the bodies of humans regardless if they have an innate darkness or not, willing or otherwise. Though bound ultimately to serve Zedom, Madō Horrors also answer to anyone who sires them as loyal servants in Zedom's absence. The personality of the sired human is retained to an extent, but warped in a way to suit to its master's needs, allowing Madō Horrors to adapt more easily than Inga Horrors with the need to feed a secondary priority. The need varies from one person to another, some might feed constantly while others only do so when they need to fight better or heal damage. Due to their fundamentally different nature from Inga Horrors, they are capable of hiding from the usual means of Horror detection, with Makai Knights and Makai Priests forced to use investigative deduction to hunt Madō Horrors before developing a specific device that exposes a Madō Horror's red eyes and lined face markings to confirm their identity. Unlike most Inga Horrors that devour human bodies, Madō Horrors rip the soul off a human and devour it with the body turning to dust. In a fight, Madō Horrors can create weapons from parts of their bodies and are stronger than Inga Horrors. The process of Madō Horrors being sired varies on their inner strength, which can be quickened to a certain extent with Zedom's Requiem. Due to the possibility of being sired without consciously knowing it, the turned humans can be blissfully unaware of the transformation until their powers and nature awaken by their first feeding. Ultimately, because of their origins as innocents, a Madō Horror is as much a victim as those they consume. During the events of Yami o Terasu Mono, Tousei creates his Madō Horror minions, using them to create a shadow empire within Vol City, from the Madō Horror Plants resulting from forcing Hakana to germinate Madō Horror Plants from the Zedom Seeds, seeded within her by accident from Zedom's Arm. However, Hakana altered the batch of Madō Horror Plants inside her for the purpose of restoring the Garo armor. As a result of singing enhancing them and the armor's restoration, these stronger Madō Horrors can only be slain by one bearing the title of Garo. However, other than Ryuga seeing Hakana's memories, there is adverse effect from killing these Madō Horrors one by one as the armor temporary regains its glow while rendering it unwearable for the moment. It was when all Madō Horrors in the city were slain that the Garo armor was restored to its original state. : The manager of Kaneshiro Real Estate, tending to only use his Horror powers whenever dealing with someone proves to be a hassle. Though slain by Ryuga, a scale from Washizu's body ends up in the possession of a youth named Shin who used it as a guitar pick before Ryuga destroys it. Portrayed by . : The manager of Vol City's Immigration Bureau who desires to make others happy, bringing people accepted by the city to a manor in Vol City's Dream Garden Hills community where they are devoured by the Horrors residing there. Shiranami almost fed the Suzuki family to his familiars before the Makai Knights intervening with Ryuga and Takeru slaying the Horror. Portrayed by . : The manager of Kaneshiro Foods' factory with a warped work mentality, Tsumazaki is tasked to develop a method by his kin where human souls can be stored within capsules to be ingested later. Wounded by Aguri, Tsumazaki is slain by Garo. Portrayed by . Councilor: A Vol City councilor and the first of the Madō Horrors to be hunted down after the development of the Madō Horror Detector. Though Aguri's arrows had no effect on him, the Councilor is decapitated by Garo before being finally destroyed. Portrayed by . Doctor: A doctor of Vol City's central hospital, he is slain by Garo when he fell into a trap that he, Rian, and Takeru set up. Portrayed by . : Originally known as Kaga Kaneshiro, he worked as a psychologist in the eastern district before being turned into a Madō Horror by his brother Tousei and rendered mute for being a blabbermouth. Forced to flee to the graveyard after being stripped of his ability to speak, Kaga came to be known as the deranged grave keeper Hyena due to being forced to feed on remnant human souls to survive. Hyena also becomes one of Vol City's urban legends as those who see him were said to fall ill in three days and die three days later. When Ryuga and Rian found him, with the latter restoring his voice, Hyena acts as a pervert to get Ryuga alone while lying of wanting to be human again. From there, revealing Zedom while hiding his true identity and that of his brother as the Madō Horrors' leader, Hyena sends Aguri and Takeru on suicide missions while managing to trick and restrain Ryuga. However, tricking Hyena at the last second, Ryuga dons the Garo armor and slays the Madō Horror. Hyena is portrayed by . Zedom is an Ancient Horror, labeled as the , whose body is composed of various blocks and alter themselves into weapons. Zedom created the first Madō Horrors in order to create the most powerful Horror army to conquer the world. However, Zedom is defeated by the Makai Priests of old with his body broken into pieces and each part sealed at various locations, with his head buried under the site of Vol City with the Goddess Statue erected, through the sacrifice of large numbers of Makai Priests, to keep the Horror imprisoned. The seeds from his body parts that were used to create Madō Horrors were entrusted to the Makai Priests who sealed the Horror, with two Makai Priestesses enacting a ritual where they open the Hill of Zedom's Arm's seals long enough to painfully absorb a Zedom seed, and grow a Madō Horror Plant from which Soul Metal is developed from. Though sealed, Zedom retained consciousness and witnessed the Makai Knights' birth, resulted in his resentment of the Makai Order for using his body parts to develop weapons used against his kind. Due to Tousei's actions fifteen years prior, Zedom's arm briefly emerged from the corrupted seal it was trapped in, infusing Hakana with more seeds than initially intended and knocked her out. When he attempts to harvest a new supply of seeds from the Horror's head for Rian to absorb, Tousei ends up awakening Zedom when one of the seeds accidentally falls back into the seal. As a result, Zedom begins to destroy the Goddess Statue in order to break free from his prison while having Sonshi acquire a Makai Knight to serve as his new body. Taking the lifeless Sonshi after he was killed as a vessel and altering it into a militant dressed form, Zedom attempts to recruit the Makai Knights in serving him before resolving to remake the world in his image. Although he is incredibly powerful, Zedom inadvertently created a weak spot within himself when he destroyed Burai, who offered to serve as a host to stop the Horror. Further weakened by a special arrow fired by Aguri into the said spot, Zedom is slain by the combined effort of the Makai Knights under the Garo armor's influence. Zedom is portrayed by . Zero: Black Blood Ring is a powerful skeletal and anthropomorphic bird-like Horror who is the main antagonist of Zero: Black Blood, appearing in the form of a handsome European gentleman dressed immaculately and predominantly in a white suit. Unlike most of his kind, though he considers humanity very selfish, Ring actually plans to have co-existence between his kind with humans as an improvement to how his kind normally feed, believing that doing so will bring lasting peace to both humans and Horrors. Ring begins this agenda by establishing a community where he offers sanctuary to humans escaping from reality. His only condition for someone to be accepted into the community is to undergo a monthly lottery, where there is a 2% chance that one of them would ingest a pill containing crystallized Horror blood to become a for his fellow Horrors to feed on. Ring's plan also relied on Iyu's calming singing ability, having also fallen in love with her to the point of obsession as it allowed him to maintain his sense of self, and keeping the humans serene and indifferent to the arrangement. Though Ring usually opts to settle things peacefully instead of resorting to violence, he is a powerful Horror who can transform his feathers into various weapons. In a state of rage however, Ring reverts to his colossal true form where he loses control over his Horror instincts unless Iyu sings to him. After devouring Iyu when she refuses to sing for him any longer, Ring is eventually slain by Zero with help from Yuna. Ring is portrayed by . Makai no Hana : A Horror resembling a Venus flytrap that emerged from a pair of pruning shears which belong to , an ikebana artist who currently creates works with the theme of death. Dissatisfied with her current works, Erina commits acts of murder to get to higher stages of her art, which causes her to be possessed. Allowed to maintain her sense of self in the possession, Erina acts on her desire to create art from victims by petrifying them for her art, her new mannequins sprouting flowers whose petals she consumes. Erina takes an interest in Mayuri and intended to make the girl into her masterpiece before Raiga intervened. Despite losing interest later due to realizing that Mayuri is but an object, she fights Raiga nonetheless due to him destroying her work. During the battle that followed, Succubus is slain by Raiga with Erina lasting long enough for the euphoria of her impending death to turn into utter dread. Erina is portrayed by . : A Horror that emerged from an old horror film that is able to send people into illusionary worlds, possessing characteristics of various Horror movie characters that include Freddy Krueger, Leatherface, and Pinhead. Ilgishin possesses the body of , a Horror film buff projectionist who allows the Horror to enter him so he can enact revenge on his manager for intending to close the movie theater down. Acting on Harima's passion, instead of feeding, Ilgishin places his victims in films to watch them get killed off by the film's monstrous antagonists. When Raiga refuses to play by his rules, Ilgishin personally battles the Makai Knight before being destroyed when Raiga uses his Makai Flame to burn him and his film away. Harima is portrayed by . : A glass-based Horror that possesses the body of , the owner of a wind chime shop who Raiga met as a child and taught him on how to make a wind chime - a memento which he has kept to the present day. However, after his son and apprentice Tetsuya died in a car crash, Shimada ended up becoming the host of Egosiren as he places pieces of his being into wind chimes that transform into ghostly women in kimono to devour buyers. When Raiga learns of this, he sees no other way to save Shimada other than slaying him. Shimada is portrayed by , while the woman in kimono is portrayed by . : A Horror that is Raiga's 100th slain Horror. The Horror makes a surprise attack on Raiga near the Tower of Heroic Spirits but ends up being slain by him. : A giant Oni-faced Horror that takes the form of a traditional Japanese straw-thatched house with its core assuming the form of a patriarch and his family: his wife and their children , , , , , and . Tricking people into entering their abode, the family makes the guest feel welcomed and joyful before tossing them into the empty communal pot in the center of the house to stew. From there, the house vanishes and appears at another unlikely location. Raiga arrives when they are about to cook their latest victim and is framed as a villain but shortly after, he reveals their deception. After being overwhelmed, Delitus assumes its true form with Raiga slaying the Horror with the help of Gōten. Ichiro is portrayed by , while his family is portrayed by , , , , , , and . : An insect-based Horror that emerged from the corpse of a woman that was raped and murdered by his host, a disturbed university student named who is obsessed with insects and locked himself away in the Natural Science Club. As Lizary is a Horror that does not fully manifest after possessing a human body, Mikimoto is unaware of the possession with his perception altered to believe his unconscious feedings were the work of the woman's corpse, believing her to be a random person he found who is an insect in human form, and his subsequent victims to be molted forms of the said corpse. Eventually, after Mayuri unlocks Mikimoto's memories, a fully manifested Lizary takes over his host's body before being slain by the combined efforts of Raiga and Crow. Mikimoto is portrayed by . : An ink-based Horror that emerged from a dip pen which belongs to , a manga artist who has become shadowed by newer manga artists with his talent and renown slowly fading. Kawabata ends up becoming Caricatuan's host when he attempts to kill an assistant who is leaving and insulted him prior, using his new power to regain his former glory by turning his victims into manga caricatures that he eats to gain their talents. Though a barrier is created around his workshop which effectively hides his presence as a Horror, his actions in accidentally using ancient Makai script in the popular manga Makai King he created under Caricatuan's influence tips off Raiga and Mayuri. He uses manga images to fight the Makai Knight, and assumes that he will be victorious by scripting every single aspect of the battle up to Raiga's death. However, Caricatuan is slain when the last panel is blotched by Raiga. Kawabata lasts in human form just long enough to be praised by Mayuri for Ninja Rin, his first manga drawn during elementary school. Kawabata is portrayed by . : A Horror whose eyes are located on the skull-shaped side of her head, Profundes is particularly detested by the Makai warriors, as her feeding methods require subjecting many victims at the same time to sheer terror and then drag them into the Demon World. Profundes possesses the body of , an amusement park ride developer who wears a witch's outfit, and she uses her host's skills to develop a motion simulator that doubles as a portal to the Makai realm. Kiera succeeds in setting up an arrangement with the Okura company, but her feeding is thwarted by Raiga. Profundes battles him in the entrance to the Demon World before he slays her. Kiera is portrayed by . : A mechanical that captures a pure-hearted human inside its body to serve as its power source, before going out to feed. After capturing a high school girl named Duoct hunts humans together with a Horror familiar that assumes Saki's appearance. However, some of Saki's thoughts still leak to hold Duoct back, which is presumed as mechanical glitches from the outside. After the fake Saki is slain by Crow, Raiga pulls off a gambit to allow himself be captured by Duoct to destroy it from the inside while saving the real Saki, who is unconscious and has no memory of her time inside the Horror. Saki is portrayed by . Ady Slate Horrors In Garo: Makai no Hana, besides the run of the mill Inga Horrors, there are nine special Horrors used by Makai Priests in the foundation of Eyrith's sealing. Unlike common Horrors, having been exposed to Eyrith's power, their personalities are dominant over their human hosts to the point where they won't recognize people the humans had known. They cannot be sealed within Makai Blades when vanquished and their essence congeals into stones. Mayuri is sent by the Senate to seal these stones due her power to seal Horrors within her body, using them to reform the Ady Slate after Eyrith is defeated. : A fish-like Horror who is the first of the Ady Slate Horrors Raiga encounters. Upon his freedom, Azdab possesses the body of the museum security guard after sensing the human's inner darkness from having murdered a girl. From there, Azdab proceeds to scare his victims with his water-based body before manifesting a swarm of piranha to eat them alive. Ultimately, Azdab is not a particularly powerful fighter and is soon slain by Raiga with Mayuri sealing him once he congregates into a stone. Sekiya is portrayed by . : A one-eyed spider-like Horror that once freed, assumed the form of a cat before possessing a shabby and old homeless woman after sensing her inner darkness. Altering her host to look youthful, Exta uses her power to assume the form of an object to ambush her prey. While she is a decent fighter, Exta mostly ran from Raiga and Crow before fighting the former in her true form before being sealed by Mayuri once congregated into a stone. The possessed woman is portrayed by . : Stellas possesses the body of , an English-speaking foreigner and serial killer who murders people because he claims that they are "his stars". Stellas is a flamboyant goofball who toys with his victims bilingually, and then turns his prey into stardust that he inhales. In his true form, Stellas is capable of flight and creating meteor-like Inga Stars. After being grounded by Crow's flight abilities, Stellas is slain by Raiga and then sealed by Mayuri once congregated into a stone. Luke is portrayed by Thane Camus. : A mechanical spherical Horror able to turn invisible and create clones of itself. As Granda is a type of Horror whose upcoming location is confirmed despite the time of arrival a mystery, Raiga and Mayuri wait it out before the former slays it and sealed by the latter once congregated into a stone. : A holder of Eyrith's seed, possessing the body of a young woman to move about. Though Idora is slain by Raiga as Eyrith transfers into one of her fellow Ady Slate Horrors still active, her essence attempts to take advantage of Mayuri's weakening condition from opening her inner cage during the encounter with Barg to regain physical form. Luckily, Raiga uses a Makai spell to enter Mayuri's consciousness to metaphysically destroy Idora and save Mayuri. The possessed woman is portrayed by . : Latel is a powerful Horror who seeks equally powerful opponents to devour. Latel first defeats the fallen Makai Knight , Bikuu's younger brother, before possessing his body to go after another worthy opponent. This leads to Latel going after Raiga, only to be slain by Raiga after Bikuu targeted a weak point on her brother's body. Once Latel is reduced to a stone, Bikuu proceeds to purify what remained of Izumo's body. Izumo is portrayed by . : Abysscore is a Horror who uses music to hypnotize his victims into a state of euphoria before converting them into cotton-candy like Life Scores. Possessing the body of a crazed conductor named , he goes on a feeding frenzy with the aid of his Makai March band before becoming bored with normal humans. This leads to Abysscore to target Raiga and Mayuri, only to be slain with Johann lasting long enough to praise the song of Raiga's soul. Johann is portrayed by Rolly. : A bat-like sword-wielding Horror that is an eccentric sadist who possessed the body of a young man named and prefers to toy with his victims, before devouring them. While he normally eats humans, Gogeet can devour other Horrors as well, despite not liking it much. After becoming the host of Eyrith's seed, Gogeet gains the ability to create an illusion of his first victim: a little girl that he devoured in front of her father. Gogeet calls the illusion "Ai" and refers to her as his daughter to put Raiga at a disadvantage. But after losing his ability, Gogeet gloats the truth about Ai and is slain by an enraged Raiga after being attacked with extreme prejudice. Matō is portrayed by . : The last of the Ady Slate Horrors, Jienda is a Horror with an eye for a right hand. Having just possessed the body of a young woman, Jienda become the final host of Eyrith's seed. However, she is soon found by Eiji Busujima and easily knocked out so he can extract the seed from the Ady Slate Horror when she congregates back into a stone. The possessed woman is portrayed by Hiromi Eguchi. Eyrith is an ancient plant-like Horror labeled as , and the originator of the Makai Trees. Eyrith is also tied to a legend that her flower, the , has the power to resurrect the dead. Ages ago, Eyrith was sealed in the by Makai Priests using nine other Horrors as foundation stones. Having left the slate where it was after the sealing is completed rather than secure it, the slate was forgotten throughout the ages even by the Makai Order until it was eventually dug up in present-day by archaeologists. The slate ended up in a museum as an archaeological relic until a mysterious person, who is later revealed to be Eiji Busujima, unraveled the seal after opening hours. Despite the slate's unsealing, Eyrith remains as a seed and is hidden within Idora, one of the Ady Slate Horrors who were also freed and each possessing the first human with inner darkness they come across. However, as Mayuri explained in the worst-case scenario, Eyrith would bloom within 100 days and enable Messiah's return by removing the boundaries that separate the human world from the Demon World. Though Raiga nearly succeeds in capturing it by slaying Idora once he finds her, Eyrith escapes by transferring its essence into the Ady Slate Horror Gogeet. As such, it is deemed impossible to capture and seal Eyrith until the remaining Ady Slate Horrors have been slain and sealed first. Despite Raiga finding and slaying Gogeet, Eyrith transfers into the last Ady Slate Horror left, Jienda, which is soon captured and Eyrith's seed is extracted by Eiji Busujima. Accepting Busujima's wish to bring back his lover, Eyrith produces a cloned body of Akari that will come to life the moment Horror is fully grown and blooms. When the time of her blooming draws near, Eyrith intends to turn Mayuri into her host to reach the place where she can bloom. However, Crow offers himself to her in order to spare Mayuri. Seeing that the now-repentant Busijima no longer has his original wish, Eyrith cancels her pact with him and brutally beats him up when he tries to stop her. Once reaching her destination, Eyrith leaves Crow's body and assumes her true human-like form before proceeding to grow into a giant tree. From there, recruiting Zaji to wipe out the line of Garo by targeting Rekka and Rian, Eyrith proceeds to spirit numerous Horrors from across time and space so that the bulb on top of her body can bloom and she can unleash a Horror army on the world. When Raiga attempts to destroy the bulb, Eyrith manifests a nude demonic version of her human form to fight him. Ultimately, the fight ends with Eyrith revealed to be the one who took Raiga's parents from him before she uses her temporal powers to suck out the Makai Knight's remaining time in the Garo armor so he can drive off his friends in his Lost Soul Beast form while she can bloom without interference. However, Raiga is later awakened as the Light Awakening Beast Garo and promptly resume to foil her plans. In a desperate bid to further demoralize Raiga, she tells him that all she has summoned are Horrors in both the past and the future and how his attempts have ended in vain, to which Raiga asserts that they will be taken care of by the Makai Knights of the past and future, as he proceeds to destroy the rest of her tree body. Left defenseless, Mayuri releases all nine stones at once and seals what remains of Eyrith in the Ady Slate once more. Eyrith is portrayed by . Gold Storm Sho These are the Horrors that appear in the film and television series Garo: Gold Storm Sho. The majority of Horrors in the television series are recruited servants of Jinga. : A bone-based Horror who possessed the body of a slum boss at the Wild Cat Bar, employing Horror familiars. When he learned that Rian is hunting him, Murado uses hoodlums Okabe and Fukaya to steal her Makai Gun so he and his familiars can kill her without trouble. But Ryuga's arrival ruins that and Murado finds himself slain by Ryuga after revealing himself in the restored Garo armor. Portrayed by . : A hoodlum employed by Murado alongside Fukaya to steal Rian's Makai Gun, awarded with money. But one bill is revealed to be a Yin Gate as Okabe later ends up being possessed by a Horror before being slain by Agō. Portrayed by . : A Horror that possesses the body of a girl, splitting into two to pose as twin sisters that can merge back into their true form. Hell Zwei is the third Horror that Ryuga has been encountering since a mysterious increase of Horror manifestations, Rian capturing one of the twins before the other appears with Ryuga arriving to pursue them. After attempting to hinder their pursuer by throwing humans at him, the twins assume their true form and attempt to kill a girl caught in the crossfire until Rian arrives to cancel their fusion. The twins attempt to convince Ryuga to let them have a final meal, but he refuses as he equips the Garo armor and cuts the reformed Hell Zwei down the middle. The possessed girl and her clone are portrayed by MIO and YAE, while both are voiced by . : A moth-winged Horror in the service of Jinga that manifests from the body of a man that Amily flung off a building. Allowed to act on his own devices, Bicro was about to eat a lady when Ryuga intercepts the Horror and forces him to flee. Bicro later gets instructions from Amily to find the red dagger that was part of the Hōken, facing Ryuga again before being slain by the Makai Knight with Rian's assistance. The possessed man is portrayed by . : A blade-based Horror that feeds on live prey by stabbing into them, releasing a pressure through the victim's body that causes it explode before the blade sucks up the blood. By chance, Bukeri possesses the body of a robber named , eating his host's partner. Then, with indirect assistance from Amily, Bukeri fatally injures Mina with Rian watching the young woman die while Ryuga eventually slays Bukeri. Hayashi is portrayed by . : A Horror that emerged from a type writer in the room where Risa and her accomplice were placed after being captured by Jinga and Amily to be made into Horror hosts. Though Risa was saved by Ryuga and Rian, Sakuma ended up being possessed by Scriptlla before being slain by Ryuga. Sakuma is portrayed by . : A Ganesha-like Horror that possesses the body of , the owner of an antique shop who has been distributing Inga Gates across the city and has become a Horror after killing the one who murdered his beloved. But Danke is not bothered by transition, seeing no distinction between remorseless murderers and Horrors. When found by Rian, Danke captures her and attempts to make her a Horror's host. But she escapes before being joined by Ryuga as he destroys the Inga Gates with Danke assuming his Horror form in response. But in the end, Vestage is killed and devoured by Jinga. Danke is portrayed by . : A mandible-mouth Horror that possesses the body of , spending his day looking for a perfect dinner by targeting food vendors and preceding to feed on them after sunset. Ressade is eventually found by Ryuga and is slain after the Makai Knight equips the Garo armor with Gald supporting him. Sumida is portrayed by . : A Horror that possesses the body of a heavily built man with knowledge of martial arts. Woska can be considered the most hated Horror before he targets children trained by Makai Knights as his food, his presence detected by Ryume after he devoured the students of Seiji Hiba, who cut off the Horror's ear to track him down to Daigo's school. Though Seiji manages to get his revenge with the help of Ryuga and Daigo, the fighting having worn the two Makai Knights out, Woska's displaced essence is absorbed by Jinga and Amily. The possessed man is portrayed by . : A festive Horror with power over electricity, using it to travel currents or enter electronic devices. Having possessed the body of a woman in a flamenco dress, Zeraza helps Jinga deal with Ryuga in return for entry into Radan, or the fallen Makai Knight's love if impossible. However, Zeraza is slain when Ryuga uses his tactics to ground the Horror's lightning attacks and delivered a slash that bifurcates her from the waist down. The possessed woman is portrayed by . : An Ent-like Horror that possesses the body of a business man, able to use vines in his attacks. Hedera is sent by Jinga and Amily to find the Houken in Yousei Forest with a hundred humans as payment. When Ryuga intervenes, Hedera assumes his true form before the Makai Knight destroys him after equipping the Garo armor. The possessed man is portrayed by . : A rotting-fish-like Horror that possesses the body of a drown man, able to turn into water. Geril is placed in the same cell as Garudo by Jinga in the fallen Makai Knight's attempt to get the whereabouts of the Houken from him. Though given permission to eat Garudo when the Makai Priest saw through him, Geril is ordered by Jinga to stop with the promise to eat Rian. Though Geril assumes his true form at Jinga's command, he is frozen in place by Rian as Ryuga slays him in the Garo armor. The possessed man is portrayed by . : A giant humanoid crustacean Horror that dwells under the waters of a swamp, the tip of its tongue assuming the form of a naked woman that functions as an esca that preys on fishermen. Begul continued to feed until the large amount of dark energy it gave off attracted the attention of Ryuga, Rian, and Gald on the notion that it is Radan. After Gald confirms the Horror is not Radan, Rian lures the monster out of the swamp so she and Ryuga can hold it off while Gald seals the swamp to keep the Horror from retreating back to the water. Though the Horror nearly overwhelmed them, Ryuga noticed a crack he made in the Horror's carapace and has Rian delay his Garo armor so he can be in a position for the armor to do the most damage. Ryuga then proceeds to destroy the Horror from the inside out. The naked woman is portrayed by . : A Horror resembling the Horror Palkeira, used by Jinga as a guard dog before it was destroyed by Ryume. Degol Known as the mad Horror, is an ancient red-skinned Horror that rampaged the area Line City was built on ages ago alongside his horde of Inga Horrors. He killed the Makai Priest Sōtatsu before being slain by the latter's creation Agō, with only his arm remaining as it was eventually sealed in a small shrine located in Line City since it could not be destroyed while the remainder of his horde were wiped out by a previous Garo. However, unaware that a fragment of Degol was in his body, Agō obtained the Horror's hand in an attempt to use Ryume to transmit the Horror's energy across Line City to kill everyone. But Degol eventually awakens and consumes Agō, creating a new centaur-like body before being slain for good by Ryuga with help from Agō. Degol is voiced by Rintarō Nishi. Radan is an ancient Horror, labeled as the , and is said to be a fortress too powerful to be destroyed. Once fully activated by two Horrors, with one becoming its ruler while the other becoming a moon that serves as its power source, Radan can absorb the life from the surrounding environment with its staff, open portals to the Demon World, fire an unlimited supply of projectiles, and command Horrors to form a scythe-like blade on its staff. The interior of Radan also serves as a defense system. Upon the death of Radan's previous king, two Makai Priests from Homura Village used the elements of Yin and Yang to create two daggers that form the Hōken blade that they used to seal Radan in the space between the human world and the Demon World. In modern times, Jinga and Amily trick the Makai Priest Gen into helping them break the seal on Radan, with Jinga obtaining one of the Hōken's dagger components, while the other is retrieved by Ryuga and Rian. Jinga releases Radan with the intent to sit at its throne, going so far as to becoming cannibal to fulfill its requirement of needing its king to have consumed Horrors. Despite attempts by Ryuga and his allies to seal Radan while they still can, it is awakened during the next full moon after its release and it flies off to await its chosen denizen. Once Jinga is fully restored, he takes the throne of Radan while Amily becomes the castle's power source, while Jinga directs it to wipe out the city. Though Jinga makes Rian the new power source after Amily is too wounded to continue, she sacrifices herself to enable Ryuga to use the stolen life force to force Radan back its inactive state and then Gald reseals the castle. The Hōken is then sent to the space between the human world and the Demon World where it shatters to ensure that the seal can never be broken again. Jinga is the main antagonist of the television series Garo: Gold Storm Sho, a cynical and arrogant manipulator who was once a Makai Knight. As revealed in Garo: Makai Retsuden, well known among the Makai Order with the nickname derived from his own name, Jinga first met Amily during a mission to retrieve a Spirit Beast pelt delivered by her group of Makai Priestesses. Despite unsavory first impressions, Jinga developed feelings for Amily as the two married and traveled the country to hunt Horrors while training their son to become a Makai Knight. But after slaying a Horror that plagued a village that considered it a rural demon they were appeasing with human sacrifices, Jinga and Amily return to find their son was ritualistically murdered by the villagers who assumed they would not return. This causes Jinga and his wife to lose their sanity and go on a rage-filled killing spree that extended to neighboring villages before Makai Priest Moyuru sacrificed himself to allow Gald and Haruna, survivors of one of the slaughtered villages, to escape to his home village Homura. Though they intended to die for their actions, Jinga and Amily survived Moyuru's suicidal attack and end up at an Inga Gate in the form of a gravestone ring in the forest at night, resulting with their Inga transforming them into their current Horror incarnations. Jinga, having be similar to Ryuga when human, saw his transition into a Horror as a liberating aphrodisiac. While once considering revenge a motive in his actions, Jinga resolves to release Radan and use its power to conquer the world. Jinga begins his scheme of freeing Radan by tricking a Makai Priest into breaking the seal on the Horror Radan for his own agenda, acquiring one of the twin daggers that form the Hōken and seeks the other while waiting for Radan to reawaken. He also employs Horrors by creating Inga Gates and offering the emerging Horrors human hosts. When the daggers resonate with each other, he and Amily casually go to meet Raiga and Rian and promptly reveal themselves to be Horrors while attempting to take their dagger. The fight ultimately ends in a stalemate as Gald grabs both blades and merges them back into the Hōken. Regardless, Jinga later abducts Gald in an attempt to find where he has hidden the Hōken, but he still has a fixation on Ryuga and orchestrates a side scheme to have the young Makai Knight give in to his darkness. After transferring his spiritual essence into Rian when his physical form is destroyed by Ryuga, Jinga attempts to consume her being to create a new body for himself while taunting Ryuga with Rian's memories. But Rian manages to make Jinga prisoner in her own mind while the others attempt to purge him from her with the waters of a holy spring. Amily stops the summoning ritual and kisses Rian to absorb Jinga's spiritual essence, offering herself for him to restore his physical form. Jinga later reconstitutes Amily's body and the two enter Radan before assuming his place as its king, while directing the giant to make its way to the city to take everyone's life energy. The plan fails and Jinga is slain by Ryuga. In Garo: Kami no Kiba, the Horror Rinza tricks Banbi into resurrecting Jinga, as a fallen Makai Knight is needed to activate the Fang of God. The process rendering him amnesiac, Jinga fights Ryuga and his friends before fleeing with a dying Banbi whom he turns into a replica of Amily. Seeing through Rinza despite his memory loss, Jinga joins Rinza's army to use the Fang of God in order to conquer the world while using Boel to create the Fang of God and sending Banbi to fight Rian. Jinga then joins the fray while returning their knights' Makai armor to defeat them as the Fang of God activates, his memories fully restored as he kills Rinza while revealing his only motivation is settling the score with Ryuga. The two battle before Jinga is once more slain by Ryuga, reunited with Amily in the Demon World as he decides to battle an awakened Messiah. As revealed in Kami no Kiba: Jinga, after being destroyed by Messiah, Jinga eventually reincarnated as a human and a Makai Knight named Jinga Mikage, an impossible case as Horrors do not truly die. Furthermore, due to Jinga's abilities as a cannibal Horror, Mikage possesses the ability to suppress Horrors within human hosts with the illusion of the humans being purified. Jinga eventually begins manifesting after Mikage followed a butterfly familiar conjured by Amily during one of his missions and once possessed the human to kill Shijo. Jinga finally 'introduces' himself to his reincarnated self one night, chastising Mikage for keeping to his mission as a Makai Knight and his decision of avoiding the darks aspects of their power. The resulting battle from the 'introduction' ends inconclusively, Jinga deciding to observe his reincarnated self and unconsciously manipulated the youth in breaking ties in everyone he knew and loved. Jinga then kills Mikage to complete his resurrection, devouring Toma after the two battle before departing. Unlike most Makai Knight-turned Horrors, Jinga's original Horror form had since sculpted into a being clad in grotesque-looking Demon Beast Exoskeleton seemingly themed after Roze Armor, Makai Armor donned by his reincarnated self Mikage, which he summons forth by swiping his left fist sideways. In his armored state, Jinga can sprout webbed wings for flight and has a tail with a sharp spine on the end to grab others. As he took to eating other Horrors to prepare himself to take Radan's throne, one of the abilities Jinga acquired from it is the ability to suppress a Horror within its human host and summon it to manifest at will. Jinga is portrayed by . Amily is Jinga's assistant, a cannibal Horror who was originally a Makai Priestess and Jinga's wife. As revealed in Garo: Makai Retsuden, being timid and inexperienced, Amily was from the Seiran Valley where many Makai tools are developed. She met Jinga while delivering a Spirit Beast pelt alongside her fellow Makai Priestesses, having a bad first impression of before getting to know him better and developed feelings for him. Amily later married Jinga after completing her training and traveled with him alongside their son. But when their son was sacrificed by villagers who were terrorized by a Horror that she and Jinga killed for their sake, a grieving Amily aided her husband in slaughtering the villagers. The two were stopped by the Makai Priest Moyuru who sacrificed himself to save Gald and Haruna, some of the few survivors. After surviving Moyuru's suicidal attempt to kill her and Jinga, the two later happened to wonder into an Inga Gate in the form of a gravestone ring in the forest at night, and the Inga within them transformed them into their current Horror incarnations. Being a former Makai Priestess and armed with a Madō brush, arrogant and seductive in her current state, Amily has extensive knowledge of magical spells and uses blue butterfly constructs as her spies, eating them to acquire their knowledge, while also recruiting Horrors to serve Jinga's purposes. Amily also possesses the Demon Mirror, a relic that allows its user to increase another's power. Amily helps Jinga in his plan to revive Radan, even revealing to Ryuga and Rian that she and her husband are Horrors when the pair are sent to reseal Radan. While captured by Ryuga's group, Amily feigns regaining her remorseful humanity to trick Ryuga into entering the Demon Mirror and then escaping Gald and Daigo's custody to meet back up with Jinga. When Jinga transfers his spiritual essence into Rian, Amily sends her blue butterfly constructs to find him. She eventually discovers his location and Amily interferes in Ryuga, Daigo, and Ryume's ceremony of banishing Jinga from Rian's body. Amily takes Rian and kisses her, absorbing Jinga's spiritual essence into her own body so he can restore himself before reconstituting her body later. Once Radan is activated, Amily, in a blue dress composed of her butterfly familiars, offers herself to become the castle's moon-like power source. But after Rian mortally wounds her, Amily ends up being killed by Jinga who has turned Rian into the new power source. In Garo: Kami no Kiba, an amnesiac Jinga transforms the deceased Banbi into a puppet replica of Amily which Rian managed to kill. After Jinga is slain and returned to the Demon World, Amily meets him and is witness to him attempting to defeat the awakened Messiah that ended with his demise. Following Jinga's reincarnation into Jinga Mikage, Amily infiltrated the Mikage family as and help influence events for her beloved to resurrect himself during the events of Kami no Kiba: Jinga. Amily eventually reveals herself and holds Rozan off long enough for Jinga to be fully restored. Amily is portrayed by , also voicing Alva. Makai Retsuden : A Horror residing the Bon Jackpot before he is killed by Wataru, portrayed by . : A Horror residing the Bon Jackpot before he is killed by Wataru, portrayed by . : A Horror residing the Bon Jackpot before he is killed by Wataru, portrayed by . Bartender: A Horror residing the Bon Jackpot before he is killed by Wataru after serving him a drink on request, portrayed by . : A Horror from the neighboring First Fort that was attacked by Wataru, telling a story of how the strongest Horrors of his group were easily killed off. Jan is portrayed by , with portrayed by Mizuho Yoshida, portrayed by , portrayed by , and portrayed by . Hoodlum: A thug during Ryuga's time as Garo who harassed Rian before she drove him and his gang off when they beating up a young man attempting to protect her. The hoodlum ended up becoming a Horror's host and killed by Rian soon after. Portrayed by . : A wasp-like Horror from Ryuga's time as Garo who fought him on a sky. : A Horror from Ryuga's time as Garo who possessed the body of a woman, able to assume the form whoever she had devoured. After taking the form of an electric worker to infiltrate Haruna's high school, Camphanto devours Ibuki, the president of astronomy club, and attempts to devour the club members. However, Camphanto's attempt is prevented by Daigo before the Makai Knight equips the Giga armor and slays the Horror. The possessed woman is portrayed by LUY, while the electrical worker and Ibuki are portrayed by and respectively. : A bat-like Horror from Raiga's time as Garo who possesses the body of a young nymphomanic , targeting men she has a crush. Antaeus targets a dancer named Hikaru before Daichi managed to enable the human's escape at cost to his wellbeing before Raiga arrived and slays the Horror. Yukino is portrayed by . : A rhinoceros-like large Horror who possessed the body of , a retired Makai Knight-to-be who was Tsubasa's friend, moving into the city where is ends up becoming a Horror. Forced to fight Tsubasa and Jabi, Kazuma assumes his true form before Tsubasa slays him. Kazuma is portrayed by . Zarugin is a powerful minotaur-like Horror from Gouki's time, the antagonist of Garo: Ashura. Based from his fortress in the Northern Valley, Zarugin and his familiars ravage the countryside before Gouki confronts them yet is overpowered by Zarugin. It was only with the aid of his new friends that Gouki gained the power to slay Zarugin. Zarugin is portrayed by . Zero: Dragon Blood : A rabbit-based Horror, drawing guests to be devoured by the Horrors dwelling in one of the hotel suites after possessing the body of , a hotel front desk clerk. He later draws Alice to be eaten by the Horrors as well, but she is rescued by Rei, who disposes of all the Horrors in the hotel to rescue her before slaying him. Kugano is portrayed by . : A plant-based Horror that emerged from a table lamp to possess the body of , a dancer. Lily is portrayed by . : A gun-based Horror that emerged from a bullet to possess the body of , a gang member. Jun is portrayed by , while a young Jun is portrayed by . : A gigantic dog/bear-faced centipede-based Horror that possessed the body of an unnamed young woman. Living at a wishing bell, she grants people visions of their greatest desires before devouring them. In human form, she can stretch her body out like a snake, wrapping up her victims. The possessed woman is portrayed by . : A termite-based Horror that possessed the body of . She gets her victims (young men) by firstly seducing them, then manifesting termites from her body to eat them alive. Towako is portrayed by . Kami no Kiba Rinza is a centauress-like Horror who gathers information on the Fang of God from a freelance professor researching the Makai community and its lore to summon Messiah into the world. She can controls a horde of Horror zombies as minions, disguise herself as other humans, and fire explosive spark bolts produced s by scraping the heels of her high-heels on rough surfaces. She deceives Banbi into aiding her by promising to revive her love Judo Tenma, claiming to help her steal Makai Knight armors in order to feed on the powerless Makai Knights later. When Banbi initiates her resurrection ritual, Rinza swaps out a strain of Judo's hair for that of Jinga's, after deeming Judo too weak to be used as a sacrificial offering to activate the Fang of God. While claiming to have summoned him to usher a new age of Horrors and swearing her loyalty, Jinga sees through Rinza's ruse and unceremoniously slays her later when she turns on him. Rinza is portrayed by , a singer who did several songs for the Garo animation franchise. Boel is a dimwitted Horror accompanying Rinza, serving as her second in command. His true Horror form is that of a large bullish creature, and is resistant to physical attacks both in his human form and his Horror form. He is slain by Jinga in order to build the Fang of God and initiate the ritual. Boel is portrayed by . Hederick is a Horror under Rinza that possesses the body of a hoodlum. Hederick is slain by Aguri. The hoodlum is portrayed by . Jagi is a bat-like Horror under Rinza that possesses the body of a gang leader. Jagi is slain by Takeru. The gang leader is portrayed by . Kami no Kiba: Jinga : A Horror targeting humans who are powerless yet with a strong will to protect their children, willing to go extreme lengths, such as murder, to keep their children safe. It emerged from a family photo to possess the body of , a truck driver, who was about to be killed by her husband and his mistress, to commit insurance fraud. Nonrosso acts only on Rena's maternal instincts, feeding on men she prostitutes herself to in order keep Rena's children from starving, and is otherwise seemingly benign. This created a conflict with Jinga due to comparing Nonrosso to his past trauma before recomposing himself and slaying her. Rena is portrayed by . : A Horror that is seemingly indestructible against Soul Metal blades and is symbiotic by nature, possessing the body of , a bullied high school girl, after emerging from the chains used to tie her up in her school's gym. Cadena gives Kanae the power to take revenge on her bullies before Jinga suppressed the Horror with Kanae's body. Before Jinga realized he was the cause of an unexpected feat and assuming that he exorcized the Horror, it was assumed that the peculiar phenomenon was attributed to Cadena. Kanae is portrayed by . : A Horror taking the form of a large mirror in an abandoned building. Instead of possessing a host like most others, it instead acts as an Inga Gate for other Horrors to emerge, by petrifying whoever stands in front of it and amplify the victim's Inga by bringing up their personal traumas and insecurities. Fons' body is destroyed by Jinga shortly after asserting his righteousness in his actions of cutting down his father, but not before turning Toma into a Horror's Host. : Initially a mild-mannered, kind-hearted pro wrestler before he unknowingly caused the death of his wife and son by helping a petty criminal, he ended up becoming a Horror after losing his faith in humanity and made a living in the underground fighting ring where he gain fame as a masked wrestler wearing a mask his son made for him. Ishida would use his Horror powers to hunt and feed on the scum of society, his sense of honor keeping him from attacking innocents. When Ishida tried to kill a young fighter named Fox, a fame seeker who tried to ruin his career before their upcoming match, Jinga manages to suppress his Horror. This restores Ishida to his original self as he spares Fox and takes him under his wing as an apprentice. Ishida is portrayed by . : A Horror that possesses the body of after emerging from her mother's wristwatch. Rika is portrayed by . : A Horror that possesses the body of , a thief. Hitoshi is portrayed by . : A Horror that possesses the body of . Okajima is portrayed by . Gekkou no Tabibito : A scorpion-like Horror that possesses the body of a woman and targets women. Ruto is slain by Raiga. The possessed woman is portrayed by . Notes See also Garo (TV series)
Israel participated in the Eurovision Song Contest 2007 with the song "Push the Button" written by Kobi Oz. The song was performed by the band Teapacks, which was internally selected by the Israeli broadcaster Israel Broadcasting Authority (IBA) in January 2007 to compete at the 2007 contest in Helsinki, Finland. The song Teapacks would perform at Eurovision was selected through the national final Kdam Eurovision 2007 which took place on 27 February 2007 that featured four songs. "Push the Button" emerged as the winning song after achieving the highest score following the combination of votes from an eleven-member jury panel, an online vote and a public vote. Israel competed in the semi-final of the Eurovision Song Contest which took place on 10 May 2007. Performing during the show in position 2, "Push the Button" was not announced among the top 10 entries of the semi-final and therefore did not qualify to compete in the final. It was later revealed that Israel placed twenty-fourth out of the 28 participating countries in the semi-final with 17 points. Background Prior to the 2007 Contest, Israel had participated in the Eurovision Song Contest twenty-nine times since its first entry in 1973. Israel has won the contest on three occasions: in 1978 with the song "A-Ba-Ni-Bi" performed by Izhar Cohen and the Alphabeta, in 1979 with the song "Hallelujah" performed by Milk and Honey and in 1998 with the song "Diva" performed by Dana International. Since the introduction of semi-finals to the format of the Eurovision Song Contest in 2004, Israel has, to this point, managed to qualify to the final two times, including a top ten result in 2005 with Shiri Maimon and "HaSheket SheNish'ar" placing fourth. Israel had qualified to the final for two consecutive years in 2005 and 2006, which included their 2006 entry "Together We Are One" performed by Eddie Butler. The Israeli national broadcaster, Israel Broadcasting Authority (IBA) had been in charge of the nation's participation in the contest since its debut in 1973. IBA confirmed Israel's participation in the contest on 10 October 2006. To select the Israeli entry for 2007, IBA conducted an internal selection to select the artist that would represent Israel and a national final to select the song for the artist. Before Eurovision Artist selection On 7 January 2007, IBA announced that the band Teapacks was selected as the Israeli representatives for the Eurovision Song Contest 2007. A special committee consisting of music industry professionals and members from IBA considered several artists, of which 2006 Swiss Eurovision entrant Liel and Michel Guriashvili were highly considered before Teapacks was ultimately selected. The members of the committee were Yoav Ginai (entertainment director of IBA), Yaakov Naveh (IBA artists representative), Dalia Cohen (musician and composer), Amnon Shiloni (director of Reshet Gimmel), Noam Gil-Or (editor and presenter at Reshet Gimmel), Bracha Rosenfeld (producer), Kobi Oshrat (composer), Yardena Arazi (1976 and 1988 Israeli Eurovision entrant), Haïm Ulliel (singer), Anastassia Michaeli (television presenter), Dafna Dekel (1992 Israeli Eurovision entrant) and Itzik Yehoshua (music editor at 88FM). It was also announced that a national final titled Kdam Eurovision 2007 featuring four songs would take place to select their song. Kdam Eurovision 2007 Four songs, all written by band member Kobi Oz, were provided by Teapacks for the competition. Prior to the final, the songs were presented on 22 February 2007 during a special presentation programme broadcast via radio on Reshet Gimmel, Reshet Bet and 88FM. Final The final took place on 27 February 2007 at the Auditorium in Dorot, hosted by Natali Atiya and Noa Barak and broadcast on Channel 1 as well as online via IBA's official Eurovision Song Contest website Eurovil. All four competing songs were performed by Teapacks and the winning song, "Push the Button", was selected by a combination of the votes from four voting groups: an expert jury of IBA representatives (40%), online voting conducted through Eurovil (20%), public voting conducted through telephone (20%) and public voting conducted through SMS (20%). In addition to the performances of the competing songs, Haïm Ulliel, the band Knesiyat Hasekhel and The Aluminum Show performed as the interval acts. At Eurovision According to Eurovision rules, all nations with the exceptions of the host country, the "Big Four" (France, Germany, Spain and the United Kingdom) and the ten highest placed finishers in the 2006 contest are required to qualify from the semi-final in order to compete for the final; the top ten countries from each semi-final progress to the final. On 12 March 2007, a special allocation draw was held which determined the running order for the semi-final. During the allocation draw, it was determined that Israel would perform in position 2, following the entry from Bulgaria and before the entry from Cyprus. At the end of the semi-final, Israel was not announced among the top 10 entries in the semi-final and therefore failed to qualify to compete in the final. It was later revealed that Israel placed twenty-fourth in the semi-final, receiving a total of 17 points. Voting Below is a breakdown of points awarded to Israel and awarded by Israel in the semi-final and grand final of the contest. The nation awarded its 12 points to Belarus in the semi-final and the final of the contest. Points awarded to Israel Points awarded by Israel References 2007 Countries in the Eurovision Song Contest 2007 Eurovision
```c++ // This is a part of the Microsoft Foundation Classes C++ library. // All rights reserved. // // This source code is only intended as a supplement to the // Microsoft Foundation Classes Reference and related // electronic documentation provided with the library. // See these sources for detailed information regarding the // Microsoft Foundation Classes product. #include "stdafx.h" #include <errno.h> #include <io.h> #include <sys\types.h> #include <sys\stat.h> #ifdef AFX_CORE1_SEG #pragma code_seg(AFX_CORE1_SEG) #endif #ifdef _DEBUG #undef THIS_FILE static char THIS_FILE[] = __FILE__; #endif #define new DEBUG_NEW //////////////////////////////////////////////////////////////////////////// // Status information for all file classes // In this file so everyone doesn't get the CTime package ///////////////////////////////////////////////////////////////////////////// // CFileStatus diagnostics #ifdef _DEBUG void CFileStatus::Dump(CDumpContext& dc) const { dc << "a CFileStatus at " << (void*)this; dc << "\nm_ctime = " << m_ctime; dc << "\nm_mtime = " << m_mtime; dc << "\nm_atime = " << m_atime; dc << "\nm_size = " << m_size; dc << "\nm_attribute = " << m_attribute; dc << "\nm_szFullName = " << m_szFullName; dc << "\n"; } #endif ///////////////////////////////////////////////////////////////////////////// // CFile name handlers #ifndef WINSCP CString CFile::GetFileName() const { ASSERT_VALID(this); CFileStatus status; GetStatus(status); CString strResult; AfxGetFileName(status.m_szFullName, strResult.GetBuffer(_MAX_FNAME), _MAX_FNAME); strResult.ReleaseBuffer(); return strResult; } CString CFile::GetFileTitle() const { ASSERT_VALID(this); CFileStatus status; GetStatus(status); CString strResult; AfxGetFileTitle(status.m_szFullName, strResult.GetBuffer(_MAX_FNAME), _MAX_FNAME); strResult.ReleaseBuffer(); return strResult; } #endif CString CFile::GetFilePath() const { ASSERT_VALID(this); CFileStatus status; GetStatus(status); return status.m_szFullName; } ///////////////////////////////////////////////////////////////////////////// // CFile Status implementation BOOL CFile::GetStatus(CFileStatus& rStatus) const { ASSERT_VALID(this); memset(&rStatus, 0, sizeof(CFileStatus)); // copy file name from cached m_strFileName lstrcpyn(rStatus.m_szFullName, m_strFileName, _countof(rStatus.m_szFullName)); if (m_hFile != hFileNull) { // get time current file size FILETIME ftCreate, ftAccess, ftModify; if (!::GetFileTime((HANDLE)m_hFile, &ftCreate, &ftAccess, &ftModify)) return FALSE; if ((rStatus.m_size = ::GetFileSize((HANDLE)m_hFile, NULL)) == (DWORD)-1L) return FALSE; if (m_strFileName.IsEmpty()) rStatus.m_attribute = 0; else { DWORD dwAttribute = ::GetFileAttributes(m_strFileName); // don't return an error for this because previous versions of MFC didn't if (dwAttribute == 0xFFFFFFFF) rStatus.m_attribute = 0; else { rStatus.m_attribute = (BYTE) dwAttribute; #ifdef _DEBUG // MFC BUG: m_attribute is only a BYTE wide if (dwAttribute & ~0xFF) TRACE0("Warning: CFile::GetStatus() returns m_attribute without high-order flags.\n"); #endif } } // convert times as appropriate rStatus.m_ctime = CTime(ftCreate); rStatus.m_atime = CTime(ftAccess); rStatus.m_mtime = CTime(ftModify); if (rStatus.m_ctime.GetTime() == 0) rStatus.m_ctime = rStatus.m_mtime; if (rStatus.m_atime.GetTime() == 0) rStatus.m_atime = rStatus.m_mtime; } return TRUE; } BOOL PASCAL CFile::GetStatus(LPCTSTR lpszFileName, CFileStatus& rStatus) { // attempt to fully qualify path first if (!AfxFullPath(rStatus.m_szFullName, lpszFileName)) { rStatus.m_szFullName[0] = '\0'; return FALSE; } WIN32_FIND_DATA findFileData; HANDLE hFind = FindFirstFile((LPTSTR)lpszFileName, &findFileData); if (hFind == INVALID_HANDLE_VALUE) return FALSE; VERIFY(FindClose(hFind)); // strip attribute of NORMAL bit, our API doesn't have a "normal" bit. rStatus.m_attribute = (BYTE) (findFileData.dwFileAttributes & ~FILE_ATTRIBUTE_NORMAL); // get just the low DWORD of the file size ASSERT(findFileData.nFileSizeHigh == 0); rStatus.m_size = (LONG)findFileData.nFileSizeLow; // convert times as appropriate rStatus.m_ctime = CTime(findFileData.ftCreationTime); rStatus.m_atime = CTime(findFileData.ftLastAccessTime); rStatus.m_mtime = CTime(findFileData.ftLastWriteTime); if (rStatus.m_ctime.GetTime() == 0) rStatus.m_ctime = rStatus.m_mtime; if (rStatus.m_atime.GetTime() == 0) rStatus.m_atime = rStatus.m_mtime; return TRUE; } void AFX_CDECL AfxTimeToFileTime(const CTime& time, LPFILETIME pFileTime) { SYSTEMTIME sysTime; sysTime.wYear = (WORD)time.GetYear(); sysTime.wMonth = (WORD)time.GetMonth(); sysTime.wDay = (WORD)time.GetDay(); sysTime.wHour = (WORD)time.GetHour(); sysTime.wMinute = (WORD)time.GetMinute(); sysTime.wSecond = (WORD)time.GetSecond(); sysTime.wMilliseconds = 0; // convert system time to local file time FILETIME localTime; if (!SystemTimeToFileTime((LPSYSTEMTIME)&sysTime, &localTime)) CFileException::ThrowOsError((LONG)::GetLastError()); // convert local file time to UTC file time if (!LocalFileTimeToFileTime(&localTime, pFileTime)) CFileException::ThrowOsError((LONG)::GetLastError()); } void PASCAL CFile::SetStatus(LPCTSTR lpszFileName, const CFileStatus& status) { DWORD wAttr; FILETIME creationTime; FILETIME lastAccessTime; FILETIME lastWriteTime; LPFILETIME lpCreationTime = NULL; LPFILETIME lpLastAccessTime = NULL; LPFILETIME lpLastWriteTime = NULL; if ((wAttr = GetFileAttributes((LPTSTR)lpszFileName)) == (DWORD)-1L) CFileException::ThrowOsError((LONG)GetLastError()); if ((DWORD)status.m_attribute != wAttr && (wAttr & readOnly)) { // Set file attribute, only if currently readonly. // This way we will be able to modify the time assuming the // caller changed the file from readonly. if (!SetFileAttributes((LPTSTR)lpszFileName, (DWORD)status.m_attribute)) CFileException::ThrowOsError((LONG)GetLastError()); } // last modification time if (status.m_mtime.GetTime() != 0) { AfxTimeToFileTime(status.m_mtime, &lastWriteTime); lpLastWriteTime = &lastWriteTime; // last access time if (status.m_atime.GetTime() != 0) { AfxTimeToFileTime(status.m_atime, &lastAccessTime); lpLastAccessTime = &lastAccessTime; } // create time if (status.m_ctime.GetTime() != 0) { AfxTimeToFileTime(status.m_ctime, &creationTime); lpCreationTime = &creationTime; } HANDLE hFile = ::CreateFile(lpszFileName, GENERIC_READ|GENERIC_WRITE, FILE_SHARE_READ, NULL, OPEN_EXISTING, FILE_ATTRIBUTE_NORMAL, NULL); if (hFile == INVALID_HANDLE_VALUE) CFileException::ThrowOsError((LONG)::GetLastError()); if (!SetFileTime((HANDLE)hFile, lpCreationTime, lpLastAccessTime, lpLastWriteTime)) CFileException::ThrowOsError((LONG)::GetLastError()); if (!::CloseHandle(hFile)) CFileException::ThrowOsError((LONG)::GetLastError()); } if ((DWORD)status.m_attribute != wAttr && !(wAttr & readOnly)) { if (!SetFileAttributes((LPTSTR)lpszFileName, (DWORD)status.m_attribute)) CFileException::ThrowOsError((LONG)GetLastError()); } } /////////////////////////////////////////////////////////////////////////////// // CMemFile::GetStatus implementation BOOL CMemFile::GetStatus(CFileStatus& rStatus) const { ASSERT_VALID(this); rStatus.m_ctime = 0; rStatus.m_mtime = 0; rStatus.m_atime = 0; rStatus.m_size = m_nFileSize; rStatus.m_attribute = normal; rStatus.m_szFullName[0] = '\0'; return TRUE; } ///////////////////////////////////////////////////////////////////////////// ```
Tsoukum Sümai is a Post-sowing or Pre-harvest festival of the Khiamniungans of Noklak district, Nagaland, India, celebrated in the month of September each year in the olden days.This is mainly observed to give thanks to the Almighty Deity for blessing abundant crops and safeguarding lives in the family. It is popualry known Tsokum orTsukhum. Tsoukum Sümai was the festival of dedication to commence the harvest in the jhum field. People harvest their crops after thanking God(Kou-o) for rich crops during Tsoukum Festival. Today, it is celebrated in the first week of October annually. During this festival, rituals are performed to invoke bountiful harvest from Kou-o (God). Community enjoy with sharing of food, meat, rice beer to relatives, friends and guest or even to the stranger who happens to come during the festive occasion and the host of the community feast i.e. the Memeipou (rich men), invite rich and poor alike, signifying love, concern and unity. Ampau(Today refers to pastor) the village priest declares or announce the date of commencement of Tsoukum festival. The first day of the fest is SÜMAI-TSIMTHAU(SUMAI JEMTHAO), Preparation of local brew by womenfolk. The second day is called SÜMAI-JANGKUM(SUMAI JANGKOM), which refers to Mithun Searching, dragging and cutting for fest continues that completes on third day. The fourth day i.e.PAIPUI(PAIUPIU), collection and bringing of a ceremonial and rituals tree called ‘Memei Pai’ is done on this day. The fifth day is the most significant of the villagers. The sixth day is called, JANGLAU (JANGLAO), The seventh day is the JANGLAU ANOU. Tsoukum Sümai is concluded on the eighth day which is called EMLIAMLIAM(EMYAMYAM) References India Entertainment events in India
```c /* * * This file is part of FFmpeg. * * FFmpeg is free software; you can redistribute it and/or * modify it under the terms of the GNU Lesser General Public * * FFmpeg is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU * * You should have received a copy of the GNU Lesser General Public * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA */ #include "opencl_allkernels.h" #if CONFIG_OPENCL #include "libavutil/opencl.h" #include "deshake_opencl_kernel.h" #include "unsharp_opencl_kernel.h" #endif #define OPENCL_REGISTER_KERNEL_CODE(X, x) \ { \ if (CONFIG_##X##_FILTER) { \ av_opencl_register_kernel_code(ff_kernel_##x##_opencl); \ } \ } void ff_opencl_register_filter_kernel_code_all(void) { #if CONFIG_OPENCL OPENCL_REGISTER_KERNEL_CODE(DESHAKE, deshake); OPENCL_REGISTER_KERNEL_CODE(UNSHARP, unsharp); #endif } ```
Johann Georg von Werdenstein (1542–1608), canon of Augsburg and Eichstätt, was the owner of a very substantial library consisting of tens of thousands of books. Werdenstein came from an aristocratic family and entered the Catholic Church, becoming a canon of Augsburg Cathedral in 1563, and adding a further canonry at Eichstatt in 1567. Around 9,000 volumes from his library including many musical items were purchased in 1592 for 6,000 florins by William V, Duke of Bavaria, for the Ducal Library in Munich, now the Bavarian State Library. References 1542 births 1608 deaths 16th-century German Roman Catholic priests German librarians People from Augsburg
United Methodist Free Churches, sometimes called Free Methodists, was an English nonconformist community in the last half of the 19th century. It was formed in 1857 by the amalgamation of the Wesleyan Association (which had in 1836 largely absorbed the Protestant Methodists of 1828) and the Wesleyan Reformers (dating from 1849, when a number of Methodist ministers were expelled from the Wesleyan Methodist Church on a charge of insubordination). It merged with the Bible Christian Church and the Methodist New Connexion to form the United Methodist Church in 1907. The United Methodist Free Churches had sent missionaries and established congregations in various colonies of Australia. These joined with four other Methodist denominations to unite as the Methodist Church of Australasia in 1902. See also List of Protestant missionary societies in China (1807–1953) Wesleyan Reform Union References Further reading 1857 establishments in England Former Methodist denominations Methodist denominations established in the 19th century Religious organizations established in 1857
```javascript 'use strict' var path = require('path') var test = require('tap').test var Tacks = require('tacks') var File = Tacks.File var Symlink = Tacks.Symlink var Dir = Tacks.Dir var common = require('../common-tap.js') var mr = require('npm-registry-mock') var testdir = path.join(__dirname, path.basename(__filename, '.js')) var bugdir = path.join(testdir, 'modules', 'bug') // This is an absolutely minimal version of the optimist included with // npm-registry-mock. var optimist = Dir({ 'package.json': File({ dependencies: { minimist: '~0.0.1', wordwrap: '~0.0.2' }, name: 'optimist', version: '0.6.0' }), node_modules: Dir({ minimist: Dir({ 'package.json': File({ _shasum: 'd7aa327bcecf518f9106ac6b8f003fa3bcea8566', _resolve: 'foo', name: 'minimist', version: '0.0.5' }) }), wordwrap: Dir({ 'package.json': File({ _shasum: 'b79669bb42ecb409f83d583cad52ca17eaa1643f', _resolve: 'foo', name: 'wordwrap', version: '0.0.2' }) }) }) }) var fixture = new Tacks( Dir({ cache: Dir({}), global: Dir({ lib: Dir({ node_modules: Dir({ linked1: Symlink('../../../modules/linked1/'), linked2: Symlink('../../../modules/linked2/') }) }) }), modules: Dir({ bug: Dir({ node_modules: Dir({ linked1: Symlink('../../../global/lib/node_modules/linked1'), linked2: Symlink('../../../global/lib/node_modules/linked2') }), 'package.json': File({ name: 'bug', version: '10800.0.0', devDependencies: { optimist: '0.6.0', linked1: '^1.0.0', linked2: '^1.0.0' } }) }), linked1: Dir({ 'package.json': File({ name: 'linked1', version: '1.0.0', devDependencies: { optimist: '0.6.0' } }), node_modules: Dir({ optimist: optimist }) }), linked2: Dir({ 'package.json': File({ name: 'linked2', version: '1.0.0', devDependencies: { optimist: '0.6.0', linked1: '^1.0.0' } }), node_modules: Dir({ linked1: Symlink('../../../global/lib/node_modules/linked1'), optimist: optimist }) }) }) }) ) function setup () { cleanup() fixture.create(testdir) } function cleanup () { fixture.remove(testdir) } var server test('setup', function (t) { setup() mr({port: common.port}, function (er, s) { t.ifError(er) server = s t.end() }) }) test('shared-linked', function (t) { var options = { cwd: bugdir, env: Object.assign({}, process.env, { npm_config_prefix: path.join(testdir, 'global') }) } var config = [ '--cache', path.join(testdir, 'cache'), '--registry', common.registry, '--unicode', 'false' ] common.npm(config.concat(['install', '--dry-run', '--parseable']), options, function (err, code, stdout, stderr) { if (err) throw err t.is(code, 0) var got = stdout.trim().replace(/\s+\n/g, '\n') var expected = 'add\tminimist\t0.0.5\tnode_modules/minimist\n' + 'add\twordwrap\t0.0.2\tnode_modules/wordwrap\n' + 'add\toptimist\t0.6.0\tnode_modules/optimist' t.is(got, expected, 'just an optimist install please') server.done() t.end() }) }) test('cleanup', function (t) { if (server) server.close() cleanup() t.end() }) ```
The terms conventional weapons or conventional arms generally refer to weapons whose ability to damage comes from kinetic, incendiary, or explosive energy and exclude weapons of mass destruction (e.g. nuclear, biological, radiological and chemical weapons). Conventional weapons include small arms, defensive shields and light weapons, sea and land mines, as well as bombs, shells, rockets, missiles and cluster munitions. These weapons use explosive material based on chemical energy, as opposed to nuclear energy in nuclear weapons. Conventional weapons are opposed to both "Weapons of Mass Destruction" and "Improvised Weapons". The acceptable use of all types of conventional weapons in war time is governed by the Geneva Conventions. Certain types of conventional weapons are also regulated or prohibited under the United Nations Convention on Certain Conventional Weapons. Others are prohibited under the Convention on Cluster Munitions, the Ottawa Treaty (also known as the Mine Ban Treaty) and Arms Trade Treaty. References Weapons
```java /* * * * path_to_url * * Unless required by applicable law or agreed to in writing, software * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * */ package com.haulmont.cuba.core.global; /** * Exception that is used to interrupt an execution flow without any messages to the user. * */ @Logging(Logging.Type.NONE) public class SilentException extends RuntimeException { private static final long serialVersionUID = 6598108074890603763L; } ```
```shell #!/bin/sh # path_to_url#ioctl set -e f=/sys/kernel/debug/lkmc_ioctl insmod ioctl.ko [ "$(./kernel_modules/ioctl.out "$f" 0 1)" = 2 ] [ "$(./kernel_modules/ioctl.out "$f" 1 1 1)" = '2 0' ] rmmod ioctl ```
```c++ // or more contributor license agreements. See the NOTICE file // distributed with this work for additional information // regarding copyright ownership. The ASF licenses this file // // path_to_url // // Unless required by applicable law or agreed to in writing, // "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY // specific language governing permissions and limitations // Implementation of casting to (or between) temporal types #include <limits> #include "arrow/array/builder_time.h" #include "arrow/compute/kernels/common_internal.h" #include "arrow/compute/kernels/scalar_cast_internal.h" #include "arrow/compute/kernels/temporal_internal.h" #include "arrow/util/bitmap_reader.h" #include "arrow/util/time.h" #include "arrow/util/value_parsing.h" namespace arrow { using internal::ParseTimestampISO8601; using internal::ParseYYYY_MM_DD; namespace compute { namespace internal { constexpr int64_t kMillisecondsInDay = 86400000; // your_sha256_hash------ // From one timestamp to another template <typename in_type, typename out_type> Status ShiftTime(KernelContext* ctx, const util::DivideOrMultiply factor_op, const int64_t factor, const ArraySpan& input, ArraySpan* output) { const CastOptions& options = checked_cast<const CastState&>(*ctx->state()).options; const in_type* in_data = input.GetValues<in_type>(1); out_type* out_data = output->GetValues<out_type>(1); if (factor == 1) { for (int64_t i = 0; i < input.length; i++) { out_data[i] = static_cast<out_type>(in_data[i]); } } else if (factor_op == util::MULTIPLY) { if (options.allow_time_overflow) { for (int64_t i = 0; i < input.length; i++) { out_data[i] = static_cast<out_type>(in_data[i] * factor); } } else { #define RAISE_OVERFLOW_CAST(VAL) \ return Status::Invalid("Casting from ", input.type->ToString(), " to ", \ output->type->ToString(), " would result in ", \ "out of bounds timestamp: ", VAL); int64_t max_val = std::numeric_limits<int64_t>::max() / factor; int64_t min_val = std::numeric_limits<int64_t>::min() / factor; if (input.null_count != 0 && input.buffers[0].data != nullptr) { BitmapReader bit_reader(input.buffers[0].data, input.offset, input.length); for (int64_t i = 0; i < input.length; i++) { if (bit_reader.IsSet() && (in_data[i] < min_val || in_data[i] > max_val)) { RAISE_OVERFLOW_CAST(in_data[i]); } out_data[i] = static_cast<out_type>(in_data[i] * factor); bit_reader.Next(); } } else { for (int64_t i = 0; i < input.length; i++) { if (in_data[i] < min_val || in_data[i] > max_val) { RAISE_OVERFLOW_CAST(in_data[i]); } out_data[i] = static_cast<out_type>(in_data[i] * factor); } } #undef RAISE_OVERFLOW_CAST } } else { if (options.allow_time_truncate) { for (int64_t i = 0; i < input.length; i++) { out_data[i] = static_cast<out_type>(in_data[i] / factor); } } else { #define RAISE_INVALID_CAST(VAL) \ return Status::Invalid("Casting from ", input.type->ToString(), " to ", \ output->type->ToString(), " would lose data: ", VAL); if (input.null_count != 0 && input.buffers[0].data != nullptr) { BitmapReader bit_reader(input.buffers[0].data, input.offset, input.length); for (int64_t i = 0; i < input.length; i++) { out_data[i] = static_cast<out_type>(in_data[i] / factor); if (bit_reader.IsSet() && (out_data[i] * factor != in_data[i])) { RAISE_INVALID_CAST(in_data[i]); } bit_reader.Next(); } } else { for (int64_t i = 0; i < input.length; i++) { out_data[i] = static_cast<out_type>(in_data[i] / factor); if (out_data[i] * factor != in_data[i]) { RAISE_INVALID_CAST(in_data[i]); } } } #undef RAISE_INVALID_CAST } } return Status::OK(); } template <template <typename...> class Op, typename OutType, typename... Args> Status ExtractTemporal(KernelContext* ctx, const ExecSpan& batch, ExecResult* out, Args... args) { const auto& ty = checked_cast<const TimestampType&>(*batch[0].type()); switch (ty.unit()) { case TimeUnit::SECOND: return TemporalComponentExtract<Op, std::chrono::seconds, TimestampType, OutType, Args...>::Exec(ctx, batch, out, args...); case TimeUnit::MILLI: return TemporalComponentExtract<Op, std::chrono::milliseconds, TimestampType, OutType, Args...>::Exec(ctx, batch, out, args...); case TimeUnit::MICRO: return TemporalComponentExtract<Op, std::chrono::microseconds, TimestampType, OutType, Args...>::Exec(ctx, batch, out, args...); case TimeUnit::NANO: return TemporalComponentExtract<Op, std::chrono::nanoseconds, TimestampType, OutType, Args...>::Exec(ctx, batch, out, args...); } return Status::Invalid("Unknown timestamp unit: ", ty); } // <TimestampType, TimestampType> and <DurationType, DurationType> template <typename O, typename I> struct CastFunctor< O, I, enable_if_t<(is_timestamp_type<O>::value && is_timestamp_type<I>::value) || (is_duration_type<O>::value && is_duration_type<I>::value)>> { static Status Exec(KernelContext* ctx, const ExecSpan& batch, ExecResult* out) { const auto& in_type = checked_cast<const I&>(*batch[0].type()); const auto& out_type = checked_cast<const O&>(*out->type()); if (in_type.unit() == out_type.unit()) { return ZeroCopyCastExec(ctx, batch, out); } ArrayData* out_arr = out->array_data().get(); DCHECK_EQ(0, out_arr->offset); int value_size = batch[0].type()->byte_width(); DCHECK_OK(ctx->Allocate(out_arr->length * value_size).Value(&out_arr->buffers[1])); ArraySpan output_span; output_span.SetMembers(*out_arr); const ArraySpan& input = batch[0].array; auto conversion = util::GetTimestampConversion(in_type.unit(), out_type.unit()); return ShiftTime<int64_t, int64_t>(ctx, conversion.first, conversion.second, input, &output_span); } }; // your_sha256_hash------ // From timestamp to date32 or date64 template <> struct CastFunctor<Date32Type, TimestampType> { template <typename Duration, typename Localizer> struct Date32 { Date32(const FunctionOptions* options, Localizer&& localizer) : localizer_(std::move(localizer)) {} template <typename T, typename Arg0> T Call(KernelContext*, Arg0 arg, Status*) const { return static_cast<T>(static_cast<const int32_t>( floor<days>(localizer_.template ConvertTimePoint<Duration>(arg)) .time_since_epoch() .count())); } Localizer localizer_; }; static Status Exec(KernelContext* ctx, const ExecSpan& batch, ExecResult* out) { return ExtractTemporal<Date32, Date32Type>(ctx, batch, out); } }; template <> struct CastFunctor<Date64Type, TimestampType> { template <typename Duration, typename Localizer> struct Date64 { constexpr static int64_t kMillisPerDay = 86400000; Date64(const FunctionOptions* options, Localizer&& localizer) : localizer_(std::move(localizer)) {} template <typename T, typename Arg0> T Call(KernelContext*, Arg0 arg, Status*) const { return static_cast<T>( kMillisPerDay * static_cast<const int32_t>( floor<days>(localizer_.template ConvertTimePoint<Duration>(arg)) .time_since_epoch() .count())); } Localizer localizer_; }; static Status Exec(KernelContext* ctx, const ExecSpan& batch, ExecResult* out) { return ExtractTemporal<Date64, Date64Type>(ctx, batch, out); } }; // your_sha256_hash------ // From timestamp to time32 or time64 template <typename Duration, typename Localizer> struct ExtractTimeDownscaled { ExtractTimeDownscaled(const FunctionOptions* options, Localizer&& localizer, const int64_t factor) : localizer_(std::move(localizer)), factor_(factor) {} template <typename T, typename Arg0> T Call(KernelContext*, Arg0 arg, Status* st) const { const auto t = localizer_.template ConvertTimePoint<Duration>(arg); const int64_t orig_value = (t - floor<days>(t)).count(); const T scaled = static_cast<T>(orig_value / factor_); const int64_t unscaled = static_cast<int64_t>(scaled) * factor_; if (unscaled != orig_value) { *st = Status::Invalid("Cast would lose data: ", orig_value); return 0; } return scaled; } Localizer localizer_; const int64_t factor_; }; template <typename Duration, typename Localizer> struct ExtractTimeUpscaledUnchecked { ExtractTimeUpscaledUnchecked(const FunctionOptions* options, Localizer&& localizer, const int64_t factor) : localizer_(std::move(localizer)), factor_(factor) {} template <typename T, typename Arg0> T Call(KernelContext*, Arg0 arg, Status*) const { const auto t = localizer_.template ConvertTimePoint<Duration>(arg); const int64_t orig_value = (t - floor<days>(t)).count(); return static_cast<T>(orig_value * factor_); } Localizer localizer_; const int64_t factor_; }; template <typename Duration, typename Localizer> struct ExtractTimeDownscaledUnchecked { ExtractTimeDownscaledUnchecked(const FunctionOptions* options, Localizer&& localizer, const int64_t factor) : localizer_(std::move(localizer)), factor_(factor) {} template <typename T, typename Arg0> T Call(KernelContext*, Arg0 arg, Status*) const { const auto t = localizer_.template ConvertTimePoint<Duration>(arg); const int64_t orig_value = (t - floor<days>(t)).count(); return static_cast<T>(orig_value / factor_); } Localizer localizer_; const int64_t factor_; }; template <> struct CastFunctor<Time32Type, TimestampType> { static Status Exec(KernelContext* ctx, const ExecSpan& batch, ExecResult* out) { const auto& in_type = checked_cast<const TimestampType&>(*batch[0].type()); const auto& out_type = checked_cast<const Time32Type&>(*out->type()); const CastOptions& options = checked_cast<const CastState&>(*ctx->state()).options; // Shifting before extraction won't work since the timestamp may not fit // even if the time itself fits if (in_type.unit() != out_type.unit()) { auto conversion = util::GetTimestampConversion(in_type.unit(), out_type.unit()); if (conversion.first == util::MULTIPLY) { return ExtractTemporal<ExtractTimeUpscaledUnchecked, Time32Type>( ctx, batch, out, conversion.second); } else { if (options.allow_time_truncate) { return ExtractTemporal<ExtractTimeDownscaledUnchecked, Time32Type>( ctx, batch, out, conversion.second); } else { return ExtractTemporal<ExtractTimeDownscaled, Time32Type>(ctx, batch, out, conversion.second); } } } return ExtractTemporal<ExtractTimeUpscaledUnchecked, Time32Type>(ctx, batch, out, 1); } }; template <> struct CastFunctor<Time64Type, TimestampType> { static Status Exec(KernelContext* ctx, const ExecSpan& batch, ExecResult* out) { const auto& in_type = checked_cast<const TimestampType&>(*batch[0].type()); const auto& out_type = checked_cast<const Time64Type&>(*out->type()); const CastOptions& options = checked_cast<const CastState&>(*ctx->state()).options; // Shifting before extraction won't work since the timestamp may not fit // even if the time itself fits if (in_type.unit() != out_type.unit()) { auto conversion = util::GetTimestampConversion(in_type.unit(), out_type.unit()); if (conversion.first == util::MULTIPLY) { return ExtractTemporal<ExtractTimeUpscaledUnchecked, Time64Type>( ctx, batch, out, conversion.second); } else { if (options.allow_time_truncate) { return ExtractTemporal<ExtractTimeDownscaledUnchecked, Time64Type>( ctx, batch, out, conversion.second); } else { return ExtractTemporal<ExtractTimeDownscaled, Time64Type>(ctx, batch, out, conversion.second); } } } return ExtractTemporal<ExtractTimeUpscaledUnchecked, Time64Type>(ctx, batch, out, 1); } }; // your_sha256_hash------ // From one time32 or time64 to another template <typename O, typename I> struct CastFunctor<O, I, enable_if_t<is_time_type<I>::value && is_time_type<O>::value>> { using in_t = typename I::c_type; using out_t = typename O::c_type; static Status Exec(KernelContext* ctx, const ExecSpan& batch, ExecResult* out) { const ArraySpan& input = batch[0].array; ArraySpan* output = out->array_span_mutable(); // If units are the same, zero copy, otherwise convert const auto& in_type = checked_cast<const I&>(*input.type); const auto& out_type = checked_cast<const O&>(*output->type); DCHECK_NE(in_type.unit(), out_type.unit()) << "Do not cast equal types"; auto conversion = util::GetTimestampConversion(in_type.unit(), out_type.unit()); return ShiftTime<in_t, out_t>(ctx, conversion.first, conversion.second, input, output); } }; // your_sha256_hash------ // Between date32 and date64 template <> struct CastFunctor<Date64Type, Date32Type> { static Status Exec(KernelContext* ctx, const ExecSpan& batch, ExecResult* out) { return ShiftTime<int32_t, int64_t>(ctx, util::MULTIPLY, kMillisecondsInDay, batch[0].array, out->array_span_mutable()); } }; template <> struct CastFunctor<Date32Type, Date64Type> { static Status Exec(KernelContext* ctx, const ExecSpan& batch, ExecResult* out) { return ShiftTime<int64_t, int32_t>(ctx, util::DIVIDE, kMillisecondsInDay, batch[0].array, out->array_span_mutable()); } }; // your_sha256_hash------ // date32, date64 to timestamp template <> struct CastFunctor<TimestampType, Date32Type> { static Status Exec(KernelContext* ctx, const ExecSpan& batch, ExecResult* out) { const auto& out_type = checked_cast<const TimestampType&>(*out->type()); // get conversion SECOND -> unit auto conversion = util::GetTimestampConversion(TimeUnit::SECOND, out_type.unit()); DCHECK_EQ(conversion.first, util::MULTIPLY); // multiply to achieve days -> unit conversion.second *= kMillisecondsInDay / 1000; return ShiftTime<int32_t, int64_t>(ctx, util::MULTIPLY, conversion.second, batch[0].array, out->array_span_mutable()); } }; template <> struct CastFunctor<TimestampType, Date64Type> { static Status Exec(KernelContext* ctx, const ExecSpan& batch, ExecResult* out) { const auto& out_type = checked_cast<const TimestampType&>(*out->type()); // date64 is ms since epoch auto conversion = util::GetTimestampConversion(TimeUnit::MILLI, out_type.unit()); return ShiftTime<int64_t, int64_t>(ctx, conversion.first, conversion.second, batch[0].array, out->array_span_mutable()); } }; // your_sha256_hash------ // String to Timestamp struct ParseTimestamp { explicit ParseTimestamp(const TimestampType& type) : type(type), expect_timezone(!type.timezone().empty()) {} template <typename OutValue, typename Arg0Value> OutValue Call(KernelContext*, Arg0Value val, Status* st) const { OutValue result = 0; bool zone_offset_present = false; if (ARROW_PREDICT_FALSE(!ParseTimestampISO8601(val.data(), val.size(), type.unit(), &result, &zone_offset_present))) { *st = Status::Invalid("Failed to parse string: '", val, "' as a scalar of type ", type.ToString()); } if (zone_offset_present != expect_timezone) { if (expect_timezone) { *st = Status::Invalid( "Failed to parse string: '", val, "' as a scalar of type ", type.ToString(), ": expected a zone offset. If these timestamps " "are in local time, cast to timestamp without timezone, then " "call assume_timezone."); } else { *st = Status::Invalid("Failed to parse string: '", val, "' as a scalar of type ", type.ToString(), ": expected no zone offset."); } } return result; } const TimestampType& type; bool expect_timezone; }; template <typename I> struct CastFunctor<TimestampType, I, enable_if_t<is_base_binary_type<I>::value>> { static Status Exec(KernelContext* ctx, const ExecSpan& batch, ExecResult* out) { const auto& out_type = checked_cast<const TimestampType&>(*out->type()); applicator::ScalarUnaryNotNullStateful<TimestampType, I, ParseTimestamp> kernel( ParseTimestamp{out_type}); return kernel.Exec(ctx, batch, out); } }; template <typename DateType> struct ParseDate { using value_type = typename DateType::c_type; using duration_type = typename std::conditional<std::is_same<DateType, Date32Type>::value, arrow_vendored::date::days, std::chrono::milliseconds>::type; template <typename OutValue, typename Arg0Value> OutValue Call(KernelContext* ctx, Arg0Value val, Status* st) const { OutValue result = OutValue(0); if (ARROW_PREDICT_FALSE(val.size() != 10)) { *st = Status::Invalid("Failed to parse string: '", val, "' as a scalar of type ", TypeTraits<DateType>::type_singleton()->ToString()); return result; } duration_type since_epoch; if (ARROW_PREDICT_FALSE(!ParseYYYY_MM_DD(val.data(), &since_epoch))) { *st = Status::Invalid("Failed to parse string: '", val, "' as a scalar of type ", TypeTraits<DateType>::type_singleton()->ToString()); } else { result = static_cast<value_type>(since_epoch.count()); } return result; } }; template <typename O, typename I> struct CastFunctor<O, I, enable_if_t<(is_date_type<O>::value && is_string_type<I>::value)>> { static Status Exec(KernelContext* ctx, const ExecSpan& batch, ExecResult* out) { return applicator::ScalarUnaryNotNull<O, I, ParseDate<O>>::Exec(ctx, batch, out); } }; template <typename Type> void AddCrossUnitCast(CastFunction* func) { ScalarKernel kernel; kernel.exec = CastFunctor<Type, Type>::Exec; kernel.signature = KernelSignature::Make({InputType(Type::type_id)}, kOutputTargetType); DCHECK_OK(func->AddKernel(Type::type_id, std::move(kernel))); } template <typename Type> void AddCrossUnitCastNoPreallocate(CastFunction* func) { ScalarKernel kernel; kernel.exec = CastFunctor<Type, Type>::Exec; kernel.null_handling = NullHandling::INTERSECTION; kernel.mem_allocation = MemAllocation::NO_PREALLOCATE; kernel.signature = KernelSignature::Make({InputType(Type::type_id)}, kOutputTargetType); DCHECK_OK(func->AddKernel(Type::type_id, std::move(kernel))); } std::shared_ptr<CastFunction> GetDate32Cast() { auto func = std::make_shared<CastFunction>("cast_date32", Type::DATE32); const auto& out_ty = date32(); AddCommonCasts(Type::DATE32, out_ty, func.get()); // date32 -> date32 AddZeroCopyCast(Type::DATE32, date32(), date32(), func.get()); // int32 -> date32 AddZeroCopyCast(Type::INT32, int32(), date32(), func.get()); // date64 -> date32 AddSimpleCast<Date64Type, Date32Type>(date64(), date32(), func.get()); // timestamp -> date32 AddSimpleCast<TimestampType, Date32Type>(InputType(Type::TIMESTAMP), date32(), func.get()); // string -> date32 AddSimpleCast<StringType, Date32Type>(utf8(), date32(), func.get()); AddSimpleCast<LargeStringType, Date32Type>(large_utf8(), date32(), func.get()); return func; } std::shared_ptr<CastFunction> GetDate64Cast() { auto func = std::make_shared<CastFunction>("cast_date64", Type::DATE64); const auto& out_ty = date64(); AddCommonCasts(Type::DATE64, out_ty, func.get()); // date64 -> date64 AddZeroCopyCast(Type::DATE64, date64(), date64(), func.get()); // int64 -> date64 AddZeroCopyCast(Type::INT64, int64(), date64(), func.get()); // date32 -> date64 AddSimpleCast<Date32Type, Date64Type>(date32(), date64(), func.get()); // timestamp -> date64 AddSimpleCast<TimestampType, Date64Type>(InputType(Type::TIMESTAMP), date64(), func.get()); // string -> date64 AddSimpleCast<StringType, Date64Type>(utf8(), date64(), func.get()); AddSimpleCast<LargeStringType, Date64Type>(large_utf8(), date64(), func.get()); return func; } std::shared_ptr<CastFunction> GetDurationCast() { auto func = std::make_shared<CastFunction>("cast_duration", Type::DURATION); AddCommonCasts(Type::DURATION, kOutputTargetType, func.get()); auto seconds = duration(TimeUnit::SECOND); auto millis = duration(TimeUnit::MILLI); auto micros = duration(TimeUnit::MICRO); auto nanos = duration(TimeUnit::NANO); // Same integer representation AddZeroCopyCast(Type::INT64, /*in_type=*/int64(), kOutputTargetType, func.get()); // Between durations AddCrossUnitCastNoPreallocate<DurationType>(func.get()); return func; } std::shared_ptr<CastFunction> GetIntervalCast() { auto func = std::make_shared<CastFunction>("cast_month_day_nano_interval", Type::INTERVAL_MONTH_DAY_NANO); AddCommonCasts(Type::INTERVAL_MONTH_DAY_NANO, kOutputTargetType, func.get()); return func; } std::shared_ptr<CastFunction> GetTime32Cast() { auto func = std::make_shared<CastFunction>("cast_time32", Type::TIME32); AddCommonCasts(Type::TIME32, kOutputTargetType, func.get()); // Zero copy when the unit is the same or same integer representation AddZeroCopyCast(Type::INT32, /*in_type=*/int32(), kOutputTargetType, func.get()); // time64 -> time32 AddSimpleCast<Time64Type, Time32Type>(InputType(Type::TIME64), kOutputTargetType, func.get()); // time32 -> time32 AddCrossUnitCast<Time32Type>(func.get()); // timestamp -> time32 AddSimpleCast<TimestampType, Time32Type>(InputType(Type::TIMESTAMP), kOutputTargetType, func.get()); return func; } std::shared_ptr<CastFunction> GetTime64Cast() { auto func = std::make_shared<CastFunction>("cast_time64", Type::TIME64); AddCommonCasts(Type::TIME64, kOutputTargetType, func.get()); // Zero copy when the unit is the same or same integer representation AddZeroCopyCast(Type::INT64, /*in_type=*/int64(), kOutputTargetType, func.get()); // time32 -> time64 AddSimpleCast<Time32Type, Time64Type>(InputType(Type::TIME32), kOutputTargetType, func.get()); // Between durations AddCrossUnitCast<Time64Type>(func.get()); // timestamp -> time64 AddSimpleCast<TimestampType, Time64Type>(InputType(Type::TIMESTAMP), kOutputTargetType, func.get()); return func; } std::shared_ptr<CastFunction> GetTimestampCast() { auto func = std::make_shared<CastFunction>("cast_timestamp", Type::TIMESTAMP); AddCommonCasts(Type::TIMESTAMP, kOutputTargetType, func.get()); // Same integer representation AddZeroCopyCast(Type::INT64, /*in_type=*/int64(), kOutputTargetType, func.get()); // From date types // TODO: ARROW-8876, these casts are not directly tested AddSimpleCast<Date32Type, TimestampType>(InputType(Type::DATE32), kOutputTargetType, func.get()); AddSimpleCast<Date64Type, TimestampType>(InputType(Type::DATE64), kOutputTargetType, func.get()); // string -> timestamp AddSimpleCast<StringType, TimestampType>(utf8(), kOutputTargetType, func.get()); // large_string -> timestamp AddSimpleCast<LargeStringType, TimestampType>(large_utf8(), kOutputTargetType, func.get()); // From one timestamp to another AddCrossUnitCastNoPreallocate<TimestampType>(func.get()); return func; } std::vector<std::shared_ptr<CastFunction>> GetTemporalCasts() { std::vector<std::shared_ptr<CastFunction>> functions; functions.push_back(GetDate32Cast()); functions.push_back(GetDate64Cast()); functions.push_back(GetDurationCast()); functions.push_back(GetIntervalCast()); functions.push_back(GetTime32Cast()); functions.push_back(GetTime64Cast()); functions.push_back(GetTimestampCast()); return functions; } } // namespace internal } // namespace compute } // namespace arrow ```
```java package com.journaldev.dynamictests; import static org.junit.jupiter.api.Assertions.*; import static org.junit.jupiter.api.DynamicTest.dynamicTest; import java.util.ArrayList; import java.util.Arrays; import java.util.Collection; import java.util.List; import java.util.stream.Stream; import org.junit.jupiter.api.DynamicTest; import org.junit.jupiter.api.TestFactory; import org.junit.jupiter.api.function.Executable; import com.journaldev.utils.MyUtils; public class JUnit5DynamicTests { @TestFactory Collection<DynamicTest> dynamicTests() { return Arrays.asList( dynamicTest("simple dynamic test", () -> assertTrue(true)), dynamicTest("My Executable Class", new MyExecutable()), // dynamicTest("Exception Executable", () -> {throw new Exception("Exception Example");}), dynamicTest("simple dynamic test-2", () -> assertTrue(true)) ); } @TestFactory Stream<DynamicTest> dynamicTestsExample() { List<Integer> input1List = Arrays.asList(1,2,3); List<Integer> input2List = Arrays.asList(10,20,30); List<DynamicTest> dynamicTests = new ArrayList<>(); for(int i=0; i < input1List.size(); i++) { int x = input1List.get(i); int y = input2List.get(i); DynamicTest dynamicTest = dynamicTest("Dynamic Test for MyUtils.add("+x+","+y+")", () ->{assertEquals(x+y,MyUtils.add(x,y));}); dynamicTests.add(dynamicTest); } return dynamicTests.stream(); } } class MyExecutable implements Executable { @Override public void execute() throws Throwable { System.out.println("Hello World!"); } } ```
```java /* * one or more contributor license agreements. See the NOTICE file distributed * with this work for additional information regarding copyright ownership. */ package io.camunda.optimize.service.db.es.reader; import static io.camunda.optimize.service.db.DatabaseConstants.MAX_RESPONSE_SIZE_LIMIT; import static io.camunda.optimize.service.db.DatabaseConstants.PROCESS_DEFINITION_INDEX_NAME; import static io.camunda.optimize.service.db.schema.index.AbstractDefinitionIndex.DEFINITION_DELETED; import static io.camunda.optimize.service.db.schema.index.ProcessDefinitionIndex.PROCESS_DEFINITION_ID; import static io.camunda.optimize.service.db.schema.index.ProcessDefinitionIndex.PROCESS_DEFINITION_XML; import static java.util.stream.Collectors.toSet; import static org.elasticsearch.index.query.QueryBuilders.boolQuery; import static org.elasticsearch.index.query.QueryBuilders.existsQuery; import static org.elasticsearch.index.query.QueryBuilders.matchAllQuery; import static org.elasticsearch.index.query.QueryBuilders.termQuery; import static org.elasticsearch.index.query.QueryBuilders.termsQuery; import static org.elasticsearch.search.aggregations.AggregationBuilders.terms; import io.camunda.optimize.dto.optimize.DefinitionType; import io.camunda.optimize.dto.optimize.ProcessDefinitionOptimizeDto; import io.camunda.optimize.service.db.es.OptimizeElasticsearchClient; import io.camunda.optimize.service.db.reader.DefinitionReader; import io.camunda.optimize.service.db.reader.ProcessDefinitionReader; import io.camunda.optimize.service.db.schema.index.ProcessDefinitionIndex; import io.camunda.optimize.service.exceptions.OptimizeRuntimeException; import io.camunda.optimize.service.util.configuration.condition.ElasticSearchCondition; import java.io.IOException; import java.util.Optional; import java.util.Set; import lombok.AllArgsConstructor; import lombok.extern.slf4j.Slf4j; import org.elasticsearch.action.search.SearchRequest; import org.elasticsearch.action.search.SearchResponse; import org.elasticsearch.index.query.BoolQueryBuilder; import org.elasticsearch.search.aggregations.bucket.MultiBucketsAggregation; import org.elasticsearch.search.aggregations.bucket.terms.Terms; import org.elasticsearch.search.builder.SearchSourceBuilder; import org.springframework.context.annotation.Conditional; import org.springframework.stereotype.Component; @AllArgsConstructor @Component @Slf4j @Conditional(ElasticSearchCondition.class) public class ProcessDefinitionReaderES implements ProcessDefinitionReader { private final DefinitionReaderES definitionReader; private final OptimizeElasticsearchClient esClient; @Override public Optional<ProcessDefinitionOptimizeDto> getProcessDefinition(final String definitionId) { final BoolQueryBuilder query = boolQuery().must(matchAllQuery()); query.must(termsQuery(PROCESS_DEFINITION_ID, definitionId)); return definitionReader.getDefinitions(DefinitionType.PROCESS, query, true).stream() .findFirst() .map(ProcessDefinitionOptimizeDto.class::cast); } @Override public Set<String> getAllNonOnboardedProcessDefinitionKeys() { final String defKeyAgg = "keyAgg"; SearchSourceBuilder searchSourceBuilder = new SearchSourceBuilder() .query( boolQuery() .must(termsQuery(ProcessDefinitionIndex.ONBOARDED, false)) .must(termQuery(DEFINITION_DELETED, false)) .should(existsQuery(PROCESS_DEFINITION_XML))) .aggregation(terms(defKeyAgg).field(ProcessDefinitionIndex.PROCESS_DEFINITION_KEY)) .fetchSource(false) .size(MAX_RESPONSE_SIZE_LIMIT); SearchRequest searchRequest = new SearchRequest(PROCESS_DEFINITION_INDEX_NAME).source(searchSourceBuilder); SearchResponse searchResponse; try { searchResponse = esClient.search(searchRequest); } catch (IOException e) { String reason = "Was not able to fetch non-onboarded process definition keys."; log.error(reason, e); throw new OptimizeRuntimeException(reason, e); } final Terms definitionKeyTerms = searchResponse.getAggregations().get(defKeyAgg); return definitionKeyTerms.getBuckets().stream() .map(MultiBucketsAggregation.Bucket::getKeyAsString) .collect(toSet()); } @Override public DefinitionReader getDefinitionReader() { return definitionReader; } } ```
Pahada is a village development committee in Dolpa District in the Karnali Zone of north-western Nepal. At the time of the 1991 Nepal census it had a population of 1413 persons living in 237 individual households. References External links UN map of the municipalities of Dolpa District Populated places in Dolpa District
```python # coding=utf-8 # # contributor license agreements. See the NOTICE file distributed with # this work for additional information regarding copyright ownership. # # path_to_url # # Unless required by applicable law or agreed to in writing, software # WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. # # pytype: skip-file # Wrapping hurts the readability of the docs. # pylint: disable=line-too-long import typing import unittest import mock import apache_beam as beam from apache_beam.testing.util import assert_that from apache_beam.testing.util import equal_to from .groupby_attr import groupby_attr from .groupby_attr_expr import groupby_attr_expr from .groupby_expr import groupby_expr from .groupby_expr_aggregate import expr_aggregate from .groupby_global_aggregate import global_aggregate from .groupby_simple_aggregate import simple_aggregate from .groupby_two_exprs import groupby_two_exprs class UnorderedList(object): def __init__(self, contents): self._contents = list(contents) def __eq__(self, other): try: return sorted(self._contents) == sorted(other) except TypeError: return sorted(self._contents, key=str) == sorted(other, key=str) def __hash__(self): return hash(tuple(sorted(self._contents))) def __repr__(self): return 'UnorderedList(%r)' % self._contents def normalize(x): if isinstance(x, tuple) and hasattr(x, '_fields'): # A named tuple. return beam.Row(**dict(zip(x._fields, x))) elif isinstance(x, typing.Iterable) and not isinstance(x, (str, beam.Row)): return UnorderedList(normalize(e) for e in x) else: return x def normalize_kv(k, v): return normalize(k), normalize(v) # For documentation. NamedTuple = beam.Row def check_groupby_expr_result(grouped): assert_that( grouped | beam.MapTuple(normalize_kv), equal_to([ #[START groupby_expr_result] ('s', ['strawberry']), ('r', ['raspberry']), ('b', ['banana', 'blackberry', 'blueberry']), #[END groupby_expr_result] ])) def check_groupby_two_exprs_result(grouped): assert_that( grouped | beam.MapTuple(normalize_kv), equal_to([ #[START groupby_two_exprs_result] (NamedTuple(letter='s', is_berry=True), ['strawberry']), (NamedTuple(letter='r', is_berry=True), ['raspberry']), (NamedTuple(letter='b', is_berry=True), ['blackberry', 'blueberry']), (NamedTuple(letter='b', is_berry=False), ['banana']), #[END groupby_two_exprs_result] ])) def check_groupby_attr_result(grouped): assert_that( grouped | beam.MapTuple(normalize_kv), equal_to([ #[START groupby_attr_result] ( 'pie', [ beam.Row( recipe='pie', fruit='strawberry', quantity=3, unit_price=1.50), beam.Row( recipe='pie', fruit='raspberry', quantity=1, unit_price=3.50), beam.Row( recipe='pie', fruit='blackberry', quantity=1, unit_price=4.00), beam.Row( recipe='pie', fruit='blueberry', quantity=1, unit_price=2.00), ]), ( 'muffin', [ beam.Row( recipe='muffin', fruit='blueberry', quantity=2, unit_price=2.00), beam.Row( recipe='muffin', fruit='banana', quantity=3, unit_price=1.00), ]), #[END groupby_attr_result] ])) def check_groupby_attr_expr_result(grouped): assert_that( grouped | beam.MapTuple(normalize_kv), equal_to([ #[START groupby_attr_expr_result] ( NamedTuple(recipe='pie', is_berry=True), [ beam.Row( recipe='pie', fruit='strawberry', quantity=3, unit_price=1.50), beam.Row( recipe='pie', fruit='raspberry', quantity=1, unit_price=3.50), beam.Row( recipe='pie', fruit='blackberry', quantity=1, unit_price=4.00), beam.Row( recipe='pie', fruit='blueberry', quantity=1, unit_price=2.00), ]), ( NamedTuple(recipe='muffin', is_berry=True), [ beam.Row( recipe='muffin', fruit='blueberry', quantity=2, unit_price=2.00), ]), ( NamedTuple(recipe='muffin', is_berry=False), [ beam.Row( recipe='muffin', fruit='banana', quantity=3, unit_price=1.00), ]), #[END groupby_attr_expr_result] ])) def check_simple_aggregate_result(grouped): assert_that( grouped | beam.MapTuple(normalize_kv), equal_to([ #[START simple_aggregate_result] NamedTuple(fruit='strawberry', total_quantity=3), NamedTuple(fruit='raspberry', total_quantity=1), NamedTuple(fruit='blackberry', total_quantity=1), NamedTuple(fruit='blueberry', total_quantity=3), NamedTuple(fruit='banana', total_quantity=3), #[END simple_aggregate_result] ])) def check_expr_aggregate_result(grouped): assert_that( grouped | beam.Map(normalize), equal_to([ #[START expr_aggregate_result] NamedTuple(recipe='pie', total_quantity=6, price=14.00), NamedTuple(recipe='muffin', total_quantity=5, price=7.00), #[END expr_aggregate_result] ])) def check_global_aggregate_result(grouped): assert_that( grouped | beam.Map(normalize), equal_to([ #[START global_aggregate_result] NamedTuple(min_price=1.00, mean_price=7 / 3, max_price=4.00), #[END global_aggregate_result] ])) @mock.patch( 'apache_beam.examples.snippets.transforms.aggregation.groupby_expr.print', str) @mock.patch( 'apache_beam.examples.snippets.transforms.aggregation.groupby_two_exprs.print', str) @mock.patch( 'apache_beam.examples.snippets.transforms.aggregation.groupby_attr.print', str) @mock.patch( 'apache_beam.examples.snippets.transforms.aggregation.groupby_attr_expr.print', str) @mock.patch( 'apache_beam.examples.snippets.transforms.aggregation.groupby_simple_aggregate.print', str) @mock.patch( 'apache_beam.examples.snippets.transforms.aggregation.groupby_expr_aggregate.print', str) @mock.patch( 'apache_beam.examples.snippets.transforms.aggregation.groupby_global_aggregate.print', str) class GroupByTest(unittest.TestCase): def test_groupby_expr(self): groupby_expr(check_groupby_expr_result) def test_groupby_two_exprs(self): groupby_two_exprs(check_groupby_two_exprs_result) def test_group_by_attr(self): groupby_attr(check_groupby_attr_result) def test_group_by_attr_expr(self): groupby_attr_expr(check_groupby_attr_expr_result) def test_simple_aggregate(self): simple_aggregate(check_simple_aggregate_result) def test_expr_aggregate(self): expr_aggregate(check_expr_aggregate_result) def test_global_aggregate(self): global_aggregate(check_global_aggregate_result) if __name__ == '__main__': unittest.main() ```
The Fraud is a historical novel based on the the Tichborne case written by Zadie Smith and published by Penguin in 2023. Synopsis According to The New York Times, Smith's "new novel, 'The Fraud,' is based on a celebrated 19th-century criminal trial, but it keeps one eye focused clearly on today’s political populism." According to the Los Angeles Times, "Not only is [the novel] set in 19th century England with a sprawling cast of characters high and low, but Charles Dickens himself makes an appearance, charming everyone except those who envy his success. But there’s more to this brilliant new entry in Smith’s catalog than a simple literary romp." References External links 2023 British novels Penguin Books Random House books Novels set in London Novels by Zadie Smith Postcolonial novels English historical novels
```yaml name: svgbob version: git summary: Svgbob description: | Svgbob converts your ascii diagrams to svg confinement: devmode grade: devel apps: svgbob: command: svgbob parts: svgbob: source: ../svgbob_cli/ plugin: rust build-attributes: [no-system-libraries] build-packages: - make - pkg-config stage-packages: - libc6 ```
```php <?php declare(strict_types = 1); namespace Rebing\GraphQL\Tests\Unit; use GraphQL\Type\Definition\ResolveInfo; use Illuminate\Validation\Validator; use PHPUnit\Framework\MockObject\MockObject; use Rebing\GraphQL\Error\ValidationError; use Rebing\GraphQL\Tests\Support\Objects\ExampleNestedValidationInputObject; use Rebing\GraphQL\Tests\Support\Objects\ExampleRuleTestingInputObject; use Rebing\GraphQL\Tests\Support\Objects\ExampleType; use Rebing\GraphQL\Tests\Support\Objects\ExampleValidationInputObject; use Rebing\GraphQL\Tests\Support\Objects\UpdateExampleMutationForRuleTesting; use Rebing\GraphQL\Tests\Support\Objects\UpdateExampleMutationWithInputType; class MutationTest extends FieldTest { /** * @return class-string<UpdateExampleMutationWithInputType> */ protected function getFieldClass() { return UpdateExampleMutationWithInputType::class; } protected function getEnvironmentSetUp($app): void { parent::getEnvironmentSetUp($app); $app['config']->set('graphql.types', [ 'Example' => ExampleType::class, 'ExampleValidationInputObject' => ExampleValidationInputObject::class, 'ExampleRuleTestingInputObject' => ExampleRuleTestingInputObject::class, 'ExampleNestedValidationInputObject' => ExampleNestedValidationInputObject::class, ]); } protected function resolveInfoMock(): MockObject { return $this->getMockBuilder(ResolveInfo::class) ->disableOriginalConstructor() ->getMock(); } public function testResolve(): void { $class = $this->getFieldClass(); $field = $this->getMockBuilder($class) ->onlyMethods(['resolve']) ->getMock(); $field->expects(self::once()) ->method('resolve'); $attributes = $field->getAttributes(); $attributes['resolve'](null, [ 'test' => 'test', 'test_with_rules' => 'test', 'test_with_rules_closure' => 'test', 'test_with_rules_nullable_input_object' => [ 'val' => 'test', 'otherValue' => '134', 'nest' => ['email' => 'test@test.com'], 'list' => [ ['email' => 'test@test.com'], ], ], 'test_with_rules_non_nullable_input_object' => [ 'val' => 'test', 'otherValue' => '134', 'nest' => ['email' => 'test@test.com'], 'list' => [ ['email' => 'test@test.com'], ], ], 'test_validation_custom_attributes' => 'test', ], [], $this->resolveInfoMock()); } public function testResolveThrowValidationError(): void { $class = $this->getFieldClass(); $field = new $class(); $attributes = $field->getAttributes(); $this->expectException(ValidationError::class); $attributes['resolve'](null, [], [], $this->resolveInfoMock()); } public function testValidationError(): void { $class = $this->getFieldClass(); $field = new $class(); $attributes = $field->getAttributes(); $exception = null; try { $attributes['resolve'](null, [ 'test_with_rules_non_nullable_input_object' => [ 'val' => 4, ], ], [], $this->resolveInfoMock()); } catch (ValidationError $exception) { } self::assertInstanceOf(ValidationError::class, $exception); $validator = $exception->getValidator(); self::assertInstanceOf(Validator::class, $validator); $messages = $exception->getValidatorMessages(); self::assertTrue($messages->has('test')); self::assertTrue($messages->has('test_with_rules')); self::assertTrue($messages->has('test_with_rules_closure')); self::assertTrue($messages->has('test_with_rules_non_nullable_input_object.otherValue')); self::assertTrue($messages->has('test_with_rules_non_nullable_input_object.nest')); self::assertTrue($messages->has('test_with_rules_non_nullable_input_object.list')); self::assertTrue($messages->has('test_validation_custom_attributes')); self::assertCount(7, $messages->all()); } public function testWithInput(): void { $class = $this->getFieldClass(); $field = new $class(); $attributes = $field->getAttributes(); $exception = null; try { $attributes['resolve'](null, [ 'test_with_rules_non_nullable_input_object' => [ 'val' => 4, ], ], [], $this->resolveInfoMock()); } catch (ValidationError $exception) { // Deliberately empty } self::assertInstanceOf(ValidationError::class, $exception); $validator = $exception->getValidator(); self::assertInstanceOf(Validator::class, $validator); $messages = $exception->getValidatorMessages(); self::assertTrue($messages->has('test')); self::assertTrue($messages->has('test_with_rules')); self::assertTrue($messages->has('test_with_rules_closure')); self::assertTrue($messages->has('test_with_rules_non_nullable_input_object.otherValue')); self::assertTrue($messages->has('test_with_rules_non_nullable_input_object.nest')); self::assertTrue($messages->has('test_with_rules_non_nullable_input_object.list')); self::assertTrue($messages->has('test_validation_custom_attributes')); self::assertCount(7, $messages->all()); } public function testWithEmptyInput(): void { $class = $this->getFieldClass(); $field = new $class(); $attributes = $field->getAttributes(); $exception = null; try { $attributes['resolve'](null, [], [], $this->resolveInfoMock()); } catch (ValidationError $exception) { } self::assertInstanceOf(ValidationError::class, $exception); $validator = $exception->getValidator(); self::assertInstanceOf(Validator::class, $validator); $messages = $exception->getValidatorMessages(); self::assertTrue($messages->has('test')); self::assertTrue($messages->has('test_with_rules')); self::assertTrue($messages->has('test_with_rules_non_nullable_input_object')); self::assertTrue($messages->has('test_with_rules_closure')); self::assertTrue($messages->has('test_validation_custom_attributes')); self::assertCount(5, $messages->all()); } public function testWithInputDepthOne(): void { $class = $this->getFieldClass(); $field = new $class(); $attributes = $field->getAttributes(); $exception = null; try { $attributes['resolve'](null, [ 'test_with_rules' => 'test', ], [], $this->resolveInfoMock()); } catch (ValidationError $exception) { } self::assertInstanceOf(ValidationError::class, $exception); $validator = $exception->getValidator(); self::assertInstanceOf(Validator::class, $validator); $messages = $exception->getValidatorMessages(); self::assertTrue($messages->has('test')); self::assertTrue($messages->has('test_with_rules_non_nullable_input_object')); self::assertTrue($messages->has('test_with_rules_closure')); self::assertTrue($messages->has('test_validation_custom_attributes')); self::assertCount(4, $messages->all()); } public function testWithInputWithEmptyInputObjects(): void { $class = $this->getFieldClass(); $field = new $class(); $attributes = $field->getAttributes(); $exception = null; try { $attributes['resolve'](null, [ 'test_with_rules_non_nullable_input_object' => [], 'test_with_rules_nullable_input_object' => [], ], [], $this->resolveInfoMock()); } catch (ValidationError $exception) { } self::assertInstanceOf(ValidationError::class, $exception); $validator = $exception->getValidator(); self::assertInstanceOf(Validator::class, $validator); $messages = $exception->getValidatorMessages(); self::assertTrue($messages->has('test')); self::assertTrue($messages->has('test_with_rules_closure')); self::assertTrue($messages->has('test_with_rules')); self::assertTrue($messages->has('test_validation_custom_attributes')); self::assertTrue($messages->has('test_with_rules_nullable_input_object.otherValue')); self::assertTrue($messages->has('test_with_rules_nullable_input_object.val')); self::assertTrue($messages->has('test_with_rules_nullable_input_object.nest')); self::assertTrue($messages->has('test_with_rules_nullable_input_object.list')); self::assertTrue($messages->has('test_with_rules_non_nullable_input_object.otherValue')); self::assertTrue($messages->has('test_with_rules_non_nullable_input_object.val')); self::assertTrue($messages->has('test_with_rules_non_nullable_input_object.nest')); self::assertTrue($messages->has('test_with_rules_non_nullable_input_object.list')); self::assertCount(13, $messages->all()); } public function testWithEmptyArrayOfInputsObjects(): void { $class = $this->getFieldClass(); $field = new $class(); $attributes = $field->getAttributes(); $exception = null; try { $attributes['resolve'](null, [ 'test_with_rules_non_nullable_list_of_non_nullable_input_object' => [], ], [], $this->resolveInfoMock()); } catch (ValidationError $exception) { } self::assertInstanceOf(ValidationError::class, $exception); $validator = $exception->getValidator(); self::assertInstanceOf(Validator::class, $validator); $messages = $exception->getValidatorMessages(); self::assertTrue($messages->has('test')); self::assertTrue($messages->has('test_with_rules')); self::assertTrue($messages->has('test_with_rules_non_nullable_input_object')); self::assertTrue($messages->has('test_with_rules_closure')); self::assertTrue($messages->has('test_validation_custom_attributes')); self::assertCount(5, $messages->all()); } public function testWithArrayOfInputsObjects(): void { $class = $this->getFieldClass(); $field = new $class(); $attributes = $field->getAttributes(); $exception = null; try { $attributes['resolve'](null, [ 'test_with_rules_non_nullable_list_of_non_nullable_input_object' => [ [ 'val' => 1245, ], ], ], [], $this->resolveInfoMock()); } catch (ValidationError $exception) { } self::assertInstanceOf(ValidationError::class, $exception); $validator = $exception->getValidator(); self::assertInstanceOf(Validator::class, $validator); $messages = $exception->getValidatorMessages(); self::assertTrue($messages->has('test')); self::assertTrue($messages->has('test_with_rules')); self::assertTrue($messages->has('test_with_rules_closure')); self::assertTrue($messages->has('test_with_rules_non_nullable_input_object')); self::assertTrue($messages->has('test_with_rules_non_nullable_list_of_non_nullable_input_object.0.otherValue')); self::assertTrue($messages->has('test_with_rules_non_nullable_list_of_non_nullable_input_object.0.nest')); self::assertTrue($messages->has('test_with_rules_non_nullable_list_of_non_nullable_input_object.0.list')); self::assertTrue($messages->has('test_validation_custom_attributes')); self::assertCount(8, $messages->all()); } public function testCustomValidationErrorMessages(): void { $class = $this->getFieldClass(); $field = new $class(); $attributes = $field->getAttributes(); $exception = null; try { $attributes['resolve'](null, [ 'test_with_rules_nullable_input_object' => [ 'nest' => ['email' => 'invalidTestEmail.com'], ], 'test_with_rules_non_nullable_input_object' => [ 'nest' => ['email' => 'invalidTestEmail.com'], ], ], [], $this->resolveInfoMock()); } catch (ValidationError $exception) { } self::assertInstanceOf(ValidationError::class, $exception); /** @var ValidationError $exception */ $messages = $exception->getValidatorMessages(); self::assertEquals('The test field is required.', $messages->first('test')); self::assertEquals( // The test with rules nullable input object.nest.email must be a valid email address. trans('validation.email', ['attribute' => 'test with rules nullable input object.nest.email']), $messages->first('test_with_rules_nullable_input_object.nest.email') ); self::assertEquals( // The test with rules non nullable input object.nest.email must be a valid email address. trans('validation.email', ['attribute' => 'test with rules non nullable input object.nest.email']), $messages->first('test_with_rules_non_nullable_input_object.nest.email') ); } public function testCustomValidationAttributes(): void { $class = $this->getFieldClass(); $field = new $class(); $attributes = $field->getAttributes(); $exception = null; try { $attributes['resolve'](null, [], [], $this->resolveInfoMock()); } catch (ValidationError $exception) { } self::assertInstanceOf(ValidationError::class, $exception); $messages = $exception->getValidatorMessages(); self::assertEquals('The custom attribute field is required.', $messages->first('test_validation_custom_attributes')); } public function testRuleCallbackArgumentsMatchesTheInput(): void { $this->expectException(ValidationError::class); $field = new UpdateExampleMutationForRuleTesting(); $attributes = $field->getAttributes(); $attributes['resolve'](null, [ 'test_with_rules_callback_params' => [ 'otherValue' => 1337, ], ], [], $this->resolveInfoMock()); } } ```
Charles Robert Robertson (28 September 1873 – 16 December 1946) was an eminent Anglican priest in the first half of the 20th century. Robertson was born on 28 September 1873, educated at Durham School and Durham University, and ordained in 1896. He held curacies in Glasgow, Bamburgh and Dumbarton; and incumbencies in Dumbarton, Fort William, Greenock and Dumfries. He was Dean of Moray, Ross and Caithness from 1935 until 1946. His last post was as Vicar of Glasson.He died on 2 February 1967. References Scottish Episcopalian clergy Deans of Moray, Ross and Caithness People educated at Durham School Alumni of University College, Durham 1873 births 1946 deaths
```powershell #################################### # Run from DC or mangement machine # #################################### #region check prerequisites #test if VMM console is installed if (!(get-module -ListAvailable | Where-Object Name -eq virtualmachinemanager)){ #ask for VMM setup.exe [reflection.assembly]::loadwithpartialname("System.Windows.Forms") $openFile = New-Object System.Windows.Forms.OpenFileDialog -Property @{ Title="Please select setup.exe from Virtual Machine Manager to install VMM console" } $openFile.Filter = "exe files (*.exe)|*.exe" If($openFile.ShowDialog() -eq "OK"){ Write-Host "File $($openfile.FileName) selected" -ForegroundColor Cyan } if (!$openFile.FileName){ Write-Host "No exe was selected... Press enter to exit" -ForegroundColor Red $exit=Read-Host exit } $SetupExePath = $openFile.FileName $SetupExeName = $openfile.SafeFileName $SetupRoot=$SetupExePath.Substring(0,$SetupExePath.Length-$setupexename.Length) #Create Answer file New-Item "$SetupRoot\VMConsole.ini" -type File -Force "[OPTIONS]" >> "$SetupRoot\VMConsole.ini" "VmmServerName=DC" >> "$SetupRoot\VMConsole.ini" "IndigoTcpPort=8100" >> "$SetupRoot\VMConsole.ini" "MUOptIn = 1" >> "$SetupRoot\VMConsole.ini" Write-Host "VMM console is being installed..." -ForegroundColor Cyan & $SetupExePath /client /i /f "$SetupRoot\VMConsole.ini" /IACCEPTSCEULA do{ Start-Sleep 2 }until ((Get-Process | Where-Object {$_.Description -eq "Virtual Machine Manager Setup"} -ErrorAction SilentlyContinue) -eq $null) Write-Host "VMM Console is Installed" -ForegroundColor Green Remove-Item "$SetupRoot\VMConsole.ini" -ErrorAction Ignore Write-Host "Please hit enter to exit. Please run the script again in new window to load PowerShell module" $exit=Read-Host exit }else{ Write-Host "SCVMM Console is installed" } #install features for management (Client needs RSAT, Server/Server Core have different features) $WindowsInstallationType=Get-ItemPropertyValue -Path 'HKLM:\SOFTWARE\Microsoft\Windows NT\CurrentVersion\' -Name InstallationType if ($WindowsInstallationType -eq "Server"){ Install-WindowsFeature -Name RSAT-Clustering,RSAT-Clustering-Mgmt,RSAT-Clustering-PowerShell,RSAT-Hyper-V-Tools,RSAT-Feature-Tools-BitLocker-BdeAducExt,RSAT-Storage-Replica }elseif ($WindowsInstallationType -eq "Server Core"){ Install-WindowsFeature -Name RSAT-Clustering,RSAT-Clustering-PowerShell,RSAT-Hyper-V-Tools,RSAT-Storage-Replica }elseif ($WindowsInstallationType -eq "Client"){ #Validate RSAT Installed if (!((Get-HotFix).hotfixid -contains "KB2693643") ){ Write-Host "Please install RSAT, Exitting in 5s" Start-Sleep 5 Exit } #Install Hyper-V Management features if ((Get-WindowsOptionalFeature -online -FeatureName Microsoft-Hyper-V-Management-PowerShell).state -ne "Enabled"){ #Install all features and then remove all except Management (fails when installing just management) Enable-WindowsOptionalFeature -online -FeatureName Microsoft-Hyper-V-All -NoRestart Disable-WindowsOptionalFeature -Online -FeatureName Microsoft-Hyper-V -NoRestart $Q=Read-Host -Prompt "Restart is needed. Do you want to restart now? Y/N" If ($Q -eq "Y"){ Write-Host "Restarting Computer" Start-Sleep 3 Restart-Computer }else{ Write-Host "You did not type Y, please restart Computer. Exitting" Start-Sleep 3 Exit } }elseif((get-command -Module Hyper-V) -eq $null){ $Q=Read-Host -Prompt "Restart is needed to load Hyper-V Management. Do you want to restart now? Y/N" If ($Q -eq "Y"){ Write-Host "Restarting Computer" Start-Sleep 3 Restart-Computer }else{ Write-Host "You did not type Y, please restart Computer. Exitting" Start-Sleep 3 Exit } } } #endregion #region Variables $VMMServerName="DC" $WDSServerName="DC" #can be also DC if you paste all scripts into DC $HostGroupName="SeattleDC" $PhysicalComputerProfileName="HVHost" $domain="corp.contoso.com" $vSwitchName="vSwitch" #DHCP and reservations configuration $DHCPServer="DC" $ScopeID="10.0.0.0" $IpaddressScope="10.0.0." $IPAddressStart=101 #starting this number IPs will be asigned #Servers Name Prefix $ServersNamePrefix="AzSHCI" #Names will be AzSHCI1, AzSHCI2,... #Cluster $ClusterName="AzS-Cluster" $ClusterIP="10.0.0.111" $ManagementNetwork="10.0.0.0" $StorageNetwork="172.16.1.0" #Credentials #Note: All account share the same credentials in this case. In real world deployments you want to use different accounts. Function ValidateCred ($cred) { $username = $cred.username $password = $cred.GetNetworkCredential().password # Get current domain using logged-on user's credentials $CurrentDomain = "LDAP://" + ([ADSI]"").distinguishedName $domain = New-Object System.DirectoryServices.DirectoryEntry($CurrentDomain,$UserName,$Password) if ($domain.name -eq $null){ return $false }else{ return $true } } #grab and validate Run As Account $RunAsAccountName="VMM RAA" do{ $RunAsAccountCred=Get-Credential -Message "Please provide Run as Admin Cred" }until (ValidateCred $RunAsAccountCred) #grab and validate Run Djoin Account $DomainJoinAccountName="VMM Djoin" <# do{ $DomainJoinAccountCred=Get-Credential -Message "Please provide Domain Join Cred" }until (ValidateCred $DomainJoinAccountCred) #> $DomainJoinAccountCred=$RunAsAccountCred #$LocalAdminCredentials=Get-Credential -Message "Please provide Local Admin Cred for physical computer profile" $LocalAdminCredentials=$RunAsAccountCred #Networking $SRIOV=$true $DCB=$true $iWARP=$False #vSwitch vNICs and vmNICs classifications $Classifications=@() $Classifications+=@{PortClassificationName="vNIC mgmt" ; NativePortProfileName="vNIC mgmt" ; Description="Classification for mgmt vNIC" ; EnableIov=$false ; EnableVrss=$true ; EnableIPsecOffload=$true ; EnableVmq=$true ; EnableRdma=$false} $Classifications+=@{PortClassificationName="vNIC RDMA" ; NativePortProfileName="vNIC RDMA" ; Description="Classification for RDMA enabled vNICs (Mode 2)" ; EnableIov=$false ; EnableVrss=$true ; EnableIPsecOffload=$true ; EnableVmq=$true ; EnableRdma=$true } $Classifications+=@{PortClassificationName="vmNIC VMQ" ; NativePortProfileName="vmNIC VMQ" ; Description="Classification for VMQ enabled vmNICs" ; EnableIov=$false ; EnableVrss=$false ; EnableIPsecOffload=$true ; EnableVmq=$true ; EnableRdma=$false} if ($SRIOV) { $Classifications+=@{PortClassificationName="vmNIC SR-IOV" ; NativePortProfileName="vmNIC SR-IOV" ; Description="Classification for SR-IOV enabled vmNICs" ; EnableIov=$true ; EnableVrss=$false ; EnableIPsecOffload=$true ; EnableVmq=$true ; EnableRdma=$false} } #logical networks definition $Networks=@() $Networks+=@{LogicalNetworkName="DatacenterNetwork" ; HostGroupNames=$HostGroupName ; Name="Management" ; Description="Management VLAN" ; VMNetworkName= "Management" ; VMNetworkDescription= "" ; Subnet="10.0.0.0/24" ; VLAN=0 ; IPAddressRangeStart="10.0.0.1" ;IPAddressRangeEnd="10.0.0.254" ; DNSSuffix="Corp.contoso.com" ;DNSServers="10.0.0.1" ;Gateways="10.0.0.1"} $Networks+=@{LogicalNetworkName="DatacenterNetwork" ; HostGroupNames=$HostGroupName ; Name="Storage" ; Description="SMB" ; VMNetworkName= "Storage" ; VMNetworkDescription= "" ; Subnet="172.16.1.0/24" ; VLAN=3 ; IPAddressRangeStart="172.16.1.1" ;IPAddressRangeEnd="172.16.1.254" ; DNSSuffix="Corp.contoso.com" ;DNSServers="" ;Gateways=""} #some fake networks just for demonstration $Networks+=@{LogicalNetworkName="VMs Network" ; HostGroupNames=$HostGroupName ; Name="Production" ; Description="Production VLAN" ; VMNetworkName= "Production" ; VMNetworkDescription= "" ; Subnet="192.168.1.0/24" ; VLAN=1 ; IPAddressRangeStart="192.168.1.1" ;IPAddressRangeEnd="192.168.1.254" ; DNSSuffix="Corp.contoso.com" ;DNSServers=("10.0.0.11","10.0.0.10") ;Gateways="192.168.1.1"} $Networks+=@{LogicalNetworkName="VMs Network" ; HostGroupNames=$HostGroupName ; Name="DMZ" ; Description="DMZ VLAN" ; VMNetworkName= "DMZ" ; VMNetworkDescription= "" ; Subnet="192.168.2.0/24" ; VLAN=2 ; IPAddressRangeStart="192.168.2.1" ;IPAddressRangeEnd="192.168.2.254" ; DNSSuffix="Corp.contoso.com" ;DNSServers=("10.0.0.11","10.0.0.10") ;Gateways="192.168.2.1"} $vNICDefinitions=@() $vNICDefinitions+=@{NetAdapterName="SMB01" ; Management=$false ; InheritSettings=$false ; IPv4AddressType="Static" ; VMNetworkName="Storage" ; VMSubnetName="Storage" ;PortClassificationName="vNIC RDMA" ;IPAddressPoolName="Storage_IPPool"} $vNICDefinitions+=@{NetAdapterName="SMB02" ; Management=$false ; InheritSettings=$false ; IPv4AddressType="Static" ; VMNetworkName="Storage" ; VMSubnetName="Storage" ;PortClassificationName="vNIC RDMA" ;IPAddressPoolName="Storage_IPPool"} $vNICDefinitions+=@{NetAdapterName="Mgmt" ; Management=$true ; InheritSettings=$true ; IPv4AddressType="Dynamic"; VMNetworkName="Management" ; VMSubnetName="Management" ;PortClassificationName="vNIC mgmt" ;IPAddressPoolName="Management_IPPool"} #Uplink Port Profile $UplinkPPName="Seattle_PP" $UplinkPPSiteNames='Storage','Management','Production','DMZ' #ask for parent vhdx for Hyper-V Hosts and VMs [reflection.assembly]::loadwithpartialname("System.Windows.Forms") $openFile = New-Object System.Windows.Forms.OpenFileDialog -Property @{ Title="Please select parent VHDx for Hyper-V Hosts and VMs." # You can copy it from parentdisks on the Hyper-V hosts somewhere into the lab and then browse for it" } $openFile.Filter = "VHDx files (*.vhdx)|*.vhdx" If($openFile.ShowDialog() -eq "OK"){ Write-Host "File $($openfile.FileName) selected" -ForegroundColor Cyan } if (!$openFile.FileName){ Write-Host "No VHD was selected... Skipping VM Creation" -ForegroundColor Red } $VHDPath = $openFile.FileName $VHDName = $openfile.SafeFileName #endregion #region basic SCVMM Configuration #Start services if not started if ((Get-Service -ComputerName $VMMServerName -Name MSSQLSERVER).status -ne "Running"){ Invoke-Command -ComputerName $VMMServerName -ScriptBlock {Start-service -Name MSSQLSERVER} } if ((Get-Service -ComputerName $VMMServerName -Name SCVMMService).status -ne "Running"){ Invoke-Command -ComputerName $VMMServerName -ScriptBlock {Start-service -Name SCVMMService} } #Connect to VMM Server Set-ExecutionPolicy -ExecutionPolicy RemoteSigned -Force Import-Module VirtualMachineManager Get-VMMServer $VMMServerName #Create Host Group New-SCVMHostGroup -Name $HostGroupName #Disable automatic logical network creation Set-SCVMMServer -AutomaticLogicalNetworkCreationEnabled $false -LogicalNetworkMatch "FirstDNSSuffixLabel" -BackupLogicalNetworkMatch "VirtualNetworkSwitchName" #Create Run As Account if (-not (Get-SCRunAsAccount -Name $RunAsAccountName)){ $runAsAccount = New-SCRunAsAccount -Credential $RunAsAccountCred -Name $RunAsAccountName -Description "" Write-Output $runAsAccount } #Create Djoin Account if (-not (Get-SCRunAsAccount -Name $DomainJoinAccountName)){ $runAsAccount = New-SCRunAsAccount -Credential $DomainJoinAccountCred -Name $DomainJoinAccountName -Description "" Write-Output $runAsAccount } #endregion #region Configure networks #create logical networks foreach ($NetworkName in ($Networks.LogicalNetworkName | Select-Object -Unique)){ if (-not (Get-SCLogicalNetwork -Name $NetworkName)){ New-SCLogicalNetwork -Name $NetworkName -LogicalNetworkDefinitionIsolation $true -EnableNetworkVirtualization $false -UseGRE $false -IsPVLAN $false } } #Create network sites foreach ($Network in $Networks){ if (-not (Get-SCLogicalNetworkDefinition -Name $Network.Name)){ $logicalNetwork=Get-SCLogicalNetwork -Name $Network.LogicalNetworkName $allHostGroups = @() foreach ($HostGroupName in $network.HostGroupNames){ $allHostGroups+=Get-SCVMHostGroup -Name $HostGroupName } $allSubnetVlan = @() $allSubnetVlan += New-SCSubnetVLan -Subnet $network.Subnet -VLanID $network.VLAN New-SCLogicalNetworkDefinition -Name $network.Name -LogicalNetwork $logicalNetwork -VMHostGroup $allHostGroups -SubnetVLan $allSubnetVlan -RunAsynchronously } } #create IP Pools foreach ($Network in $Networks){ if ($network.IPAddressRangeStart){ if (-not (Get-SCStaticIPAddressPool -Name "$($network.name)_IPPool")){ $logicalNetwork = Get-SCLogicalNetwork -Name $network.LogicalNetworkName $logicalNetworkDefinition = Get-SCLogicalNetworkDefinition -Name $network.Name # Gateways $allGateways = @() if ($Network.Gateways){ foreach ($gateway in $Network.Gateways){ $allGateways += New-SCDefaultGateway -IPAddress $gateway -Automatic } } # DNS servers if ($Network.DNSServers){ $allDnsServer = $Network.DNSServers }else{ $allDnsServer=@() } # DNS suffixes $allDnsSuffixes = @() # WINS servers $allWinsServers = @() New-SCStaticIPAddressPool -Name "$($network.Name)_IPPool" -LogicalNetworkDefinition $logicalNetworkDefinition -Subnet $Network.Subnet -IPAddressRangeStart $network.IPAddressRangeStart -IPAddressRangeEnd $network.IPAddressRangeEnd -DNSServer $allDnsServer -DNSSuffix $network.DNSSuffix -DNSSearchSuffix $allDnsSuffixes -NetworkRoute $allNetworkRoutes -DefaultGateway $allGateways -RunAsynchronously } } } #Create VM Networks foreach ($Network in $Networks){ if (-not (Get-SCVMNetwork -Name $network.VMNetworkName)){ $logicalNetwork = Get-SCLogicalNetwork -Name $network.LogicalNetworkName $vmNetwork = New-SCVMNetwork -Name $network.VMNetworkName -LogicalNetwork $logicalNetwork -IsolationType "VLANNetwork" $logicalNetworkDefinition = Get-SCLogicalNetworkDefinition -Name $Network.Name $subnetVLANs = @() $subnetVLANv4 = New-SCSubnetVLan -Subnet $Network.Subnet -VLanID $network.VLAN $subnetVLANs += $subnetVLANv4 $vmSubnet = New-SCVMSubnet -Name $network.VMNetworkName -Description $network.VMNetworkDescription -LogicalNetworkDefinition $logicalNetworkDefinition -SubnetVLan $subnetVLANs -VMNetwork $vmNetwork } } <#Cleanup networking if needed Get-SCVMNetwork | Remove-SCVMNetwork Get-SCIPAddress | Revoke-SCIPAddress Get-SCStaticIPAddressPool | Remove-SCStaticIPAddressPool get-sclogicalnetworkdefinition |Remove-SCLogicalNetworkDefinition Get-SCLogicalNetwork | remove-sclogicalnetwork #> #endregion #region Cofigure virtual Switch #create uplink pp. Use all Logical networks $definition = @() foreach ($UplinkPPSiteName in $UplinkPPSiteNames){ $definition += Get-SCLogicalNetworkDefinition -Name $uplinkppsitename } if (-not (Get-SCNativeUplinkPortProfile -Name $UplinkPPName)){ New-SCNativeUplinkPortProfile -Name $UplinkPPName -Description "" -LogicalNetworkDefinition $definition -EnableNetworkVirtualization $false -LBFOLoadBalancingAlgorithm "HyperVPort" -LBFOTeamMode "SwitchIndependent" -RunAsynchronously } #create port classifications and port profiles foreach ($Classification in $Classifications){ If (-not (Get-SCVirtualNetworkAdapterNativePortProfile -Name $Classification.NativePortProfileName)){ New-SCVirtualNetworkAdapterNativePortProfile -Name $Classification.NativePortProfileName -Description $Classification.Description -AllowIeeePriorityTagging $false -AllowMacAddressSpoofing $false -AllowTeaming $false -EnableDhcpGuard $false -EnableGuestIPNetworkVirtualizationUpdates $false -EnableIov $Classification.EnableIOV -EnableVrss $Classification.EnableVrss -EnableIPsecOffload $Classification.EnableIPsecOffload -EnableRouterGuard $false -EnableVmq $Classification.EnableVmq -EnableRdma $Classification.EnableRdma -MinimumBandwidthWeight "0" -RunAsynchronously } If (-not (Get-SCPortClassification -Name $Classification.PortClassificationName)){ New-SCPortClassification -Name $Classification.PortClassificationName -Description $Classification.Description } } #Create Logical Switch $virtualSwitchExtensions = @() if ($SRIOV){ $logicalSwitch = New-SCLogicalSwitch -Name $vSwitchName -Description "" -EnableSriov $true -SwitchUplinkMode "EmbeddedTeam" -MinimumBandwidthMode "None" -VirtualSwitchExtensions $virtualSwitchExtensions }else{ $logicalSwitch = New-SCLogicalSwitch -Name $vSwitchName -Description "" -EnableSriov $false -SwitchUplinkMode "EmbeddedTeam" -MinimumBandwidthMode "Absolute" -VirtualSwitchExtensions $virtualSwitchExtensions } #Add virtual port classifications foreach ($Classification in $Classifications){ # Get Network Port Classification $portClassification = Get-SCPortClassification -Name $Classification.PortClassificationName # Get Hyper-V Switch Port Profile $nativeProfile = Get-SCVirtualNetworkAdapterNativePortProfile -Name $Classification.NativePortProfileName New-SCVirtualNetworkAdapterPortProfileSet -Name $Classification.PortClassificationName -PortClassification $portClassification -LogicalSwitch $logicalSwitch -RunAsynchronously -VirtualNetworkAdapterNativePortProfile $nativeProfile } #Set Uplink Port Profile $nativeUppVar = Get-SCNativeUplinkPortProfile -Name $UplinkPPName $uppSetVar = New-SCUplinkPortProfileSet -Name $UplinkPPName -LogicalSwitch $logicalSwitch -NativeUplinkPortProfile $nativeUppVar -RunAsynchronously #Add virtual network adapters to switch. foreach ($vNICDefinition in $vNICDefinitions){ # Get VM Network $vmNetwork = Get-SCVMNetwork -Name $vNICDefinition.VMNetworkName # Get VMSubnet' $vmSubnet = Get-SCVMSubnet -Name $vNICDefinition.VMSubnetName #Get Classification $vNICPortClassification = Get-SCPortClassification -Name $vNICDefinition.PortClassificationName New-SCLogicalSwitchVirtualNetworkAdapter -Name $vNICDefinition.NetAdapterName -PortClassification $vNICPortClassification -UplinkPortProfileSet $uppSetVar -RunAsynchronously -VMNetwork $vmNetwork -VMSubnet $vmSubnet -IsUsedForHostManagement $vNICDefinition.Management -InheritsAddressFromPhysicalNetworkAdapter $vNICDefinition.InheritSettings -IPv4AddressType $vNICDefinition.IPv4AddressType -IPv6AddressType "Dynamic" } #endregion #region Configure Physical Computer Profile #Add drivers (real environment only) <# Can be done by copying inf into some folder. Like Proliant DL380G9 and then mathcing it like this get-scdriverpackage | where sharepath -like *DL380G9* | set-scdriverpackage -tag "HP Proliant DL380G9" #> #Copy Host VHD to library Copy-Item -Path $VHDPath -Destination "$((Get-SCLibraryShare).Path)\VHDs" #Refresh Library Get-SCLibraryShare | Read-SCLibraryShare #Set that VHD as Server 2016 Datacenter $libraryobject=Get-SCVirtualHardDisk -Name $VHDName $os=Get-SCOperatingSystem | Where-Object Name -eq "Azure Stack HCI 20H2" Set-SCVirtualHardDisk -VirtualHardDisk $libraryObject -OperatingSystem $os -VirtualizationPlatform "HyperV" -Name $VHDName -Description "" -Release "" -FamilyName "" #Configure Profile (In real environment you would also configure PNP matching for drivers) $VHD = Get-SCVirtualHardDisk -Name $VHDName # Get RunAs Account for Domain Join (Best practice is use some account that has only rights to write to one OU) $DomainJoinRunAsAccount = Get-SCRunAsAccount | Where-Object Name -eq $DomainJoinAccountName # Get RunAs Account for Computer Access (Best practice is use some account that has privileges to Hyper-V hosts, but not Domain Admin as we are showing here) $ComputerAccessRunAsAccount = Get-SCRunAsAccount | Where-Object Name -eq $RunAsAccountName $NicProfilesArray = @() $NicProfile1 = New-SCPhysicalComputerNetworkAdapterProfile -SetAsManagementNIC -SetAsPhysicalNetworkAdapter -UseDhcpForIPConfiguration $NicProfilesArray += $NicProfile1 #$Tags = @("HP Proliant") New-SCPhysicalComputerProfile -Name $PhysicalComputerProfileName -Description "" -DiskConfiguration "GPT=1:PRIMARY:QUICK:4:FALSE:OS::0:BOOTPARTITION;" -Domain $domain -TimeZone 4 -RunAsynchronously -FullName "" -OrganizationName "" -ProductKey "" -IsGuarded $false -VMPaths "" -UseAsVMHost -VirtualHardDisk $VHD -BypassVHDConversion $true -DomainJoinRunAsAccount $DomainJoinRunAsAccount -ComputerAccessRunAsAccount $ComputerAccessRunAsAccount -LocalAdministratorCredential $LocalAdminCredentials -PhysicalComputerNetworkAdapterProfile $NicProfilesArray #-DriverMatchingTag $Tags #endregion #region Configure WDS # Configure WDS Install-WindowsFeature WDS -IncludeManagementTools -IncludeAllSubFeature -ComputerName $WDSServerName if ($env:COMPUTERNAME -eq $WDSServerName){ wdsutil /initialize-server /reminst:"C:\RemoteInstall" wdsutil /start-server }else{ #need to do credssp delegation to be able to send creds to server. Make sure the remote server is not DC. winrm quickconfig -force #on client is winrm not configured Enable-WSManCredSSP -DelegateComputer "$WDSServerName" -Role Client -Force Invoke-Command -ComputerName $WDSServerName -ScriptBlock {Enable-WSManCredSSP Server -Force} Invoke-Command -ComputerName $WDSServerName -Credential $RunAsAccountCred -Authentication Credssp -ScriptBlock { wdsutil /initialize-server /reminst:"C:\RemoteInstall" wdsutil /start-server } Disable-WSManCredSSP -Role Client Invoke-Command -ComputerName $WDSServerName -ScriptBlock {Disable-WSManCredSSP Server} } #Add WDS to SCVMM $credential = Get-SCRunAsAccount -Name $RunAsAccountName Add-SCPXEServer -ComputerName $WDSServerName -Credential $credential #not needed #Publish-SCWindowsPE -UseDefaultImage #endregion ######################### # Run from Hyper-V Host # ######################### #region Run from Hyper-V Host to create new VMs #some variables $LabPrefix="MSLab17763.1852VMM-" $vSwitchName="$($LabPrefix)LabSwitch" $VMsPath="E:\MSLab17763.1852VMM\LAB\VMs" $VMNames="AzSHCI1","AzSHCI2","AzSHCI3","AzSHCI4" $NumberOfHDDs=4 $SizeOfHDD=8TB $MemoryStartupBytes=4GB #create some blank VMs foreach ($VMName in $VMNames){ $VMName="$LabPrefix$VMName" New-VM -Name $VMName -NewVHDPath "$VMsPath\$VMName\Virtual Hard Disks\$VMName.vhdx" -NewVHDSizeBytes 128GB -SwitchName $vSwitchName -Generation 2 -Path "$VMsPath" -MemoryStartupBytes $MemoryStartupBytes 1..$NumberOfHDDs | ForEach-Object { $VHD=New-VHD -Path "$VMsPath\$VMName\Virtual Hard Disks\HDD$_.vhdx" -SizeBytes $SizeOfHDD Add-VMHardDiskDrive -VMName $VMName -Path "$VMsPath\$VMName\Virtual Hard Disks\HDD$_.vhdx" } #Add Adapter Add-VMNetworkAdapter -VMName $VMName -SwitchName $vSwitchName #configure Nested Virt and 2 cores Set-VMProcessor -ExposeVirtualizationExtensions $true -VMName $VMName -Count 2 #configure Memory Set-VMMemory -VMName $VMName -DynamicMemoryEnabled $false #configure network adapters Set-VMNetworkAdapter -VMName $VMName -AllowTeaming On -MacAddressSpoofing On Set-VMNetworkAdapterVlan -VMName $VMName -Trunk -NativeVlanId 0 -AllowedVlanIdList "1-10" #disable automatic checkpoints if ((get-vm -VMName $VMName).AutomaticCheckpointsEnabled -eq $True){ Set-VM -Name $VMName -AutomaticCheckpointsEnabled $False } #Start VM Start-VM -Name $VMName } #endregion ################################### # Continue on DC or Management VM # ################################### #region deploy hosts <#Example of manual host definition if you do real deployments $HVHosts=@() $HVHosts+=@{ComputerName="xxx01HV1" ;IPAddress="10.0.0.31" ; MACAddress="AA:BB:CC:8F:BD:E8" ; BMCAddress="10.0.1.31" ; SMBiosGuid="20170518-0000-0000-0001-1ABB4983C428"} $HVHosts+=@{ComputerName="xxx02HV1" ;IPAddress="10.0.0.32" ; MACAddress="AA:BB:CC:8F:BC:E8" ; BMCAddress="10.0.1.32" ; SMBiosGuid="20170518-0000-0000-0001-1ABB4983C433"} $HVHosts+=@{ComputerName="xxx03HV1" ;IPAddress="10.0.0.33" ; MACAddress="AA:BB:CC:8F:BE:20" ; BMCAddress="10.0.1.33" ; SMBiosGuid="20170518-0000-0000-0001-1ABB4983C43E"} $HVHosts+=@{ComputerName="xxx04HV1" ;IPAddress="10.0.0.34" ; MACAddress="AA:BB:CC:8F:BB:48" ; BMCAddress="10.0.1.34" ; SMBiosGuid="20170518-0000-0000-0001-1ABB4983C442"} $HVHosts+=@{ComputerName="xxx05HV1" ;IPAddress="10.0.0.35" ; MACAddress="AA:BB:CC:8F:BC:F8" ; BMCAddress="10.0.1.35" ; SMBiosGuid="20170518-0000-0000-0001-1ABB4983C443"} $HVHosts+=@{ComputerName="xxx09HV1" ;IPAddress="10.0.0.39" ; MACAddress="AA:BB:CC:8F:BD:F8" ; BMCAddress="10.0.1.39" ; SMBiosGuid="20170518-0000-0000-0001-1ABB4983C447"} $HVHosts+=@{ComputerName="xxx10HV1" ;IPAddress="10.0.0.40" ; MACAddress="AA:BB:CC:7E:8E:78" ; BMCAddress="10.0.1.40" ; SMBiosGuid="20170518-0000-0000-0001-1ABB4983C429"} $HVHosts+=@{ComputerName="xxx11HV1" ;IPAddress="10.0.0.41" ; MACAddress="AA:BB:CC:8F:BD:90" ; BMCAddress="10.0.1.41" ; SMBiosGuid="20170518-0000-0000-0001-1ABB4983C42A"} $HVHosts+=@{ComputerName="xxx12HV1" ;IPAddress="10.0.0.42" ; MACAddress="AA:BB:CC:8F:BD:E0" ; BMCAddress="10.0.1.42" ; SMBiosGuid="20170518-0000-0000-0001-1ABB4983C42B"} #> #Grab Machine GUIDs from Event log, sort oldest->newest, select unique and add it to hash table with server names. Grab only unique GUIDs #If you do this in real environment, think twice. You grab all servers that attemted PXE boot (!!!you can wipe production with this!!!) <#sample HVHosts output PS C:\Users\Administrator> $HVHosts Name Value ---- ----- SMBiosGuid 27ED1EF6-8ACD-49E7-9AFB-26CF7E639AA1 ComputerName S2D1 IPAddress 10.0.0.100 MACAddress 00:15:5D:89:E9:6F SMBiosGuid DE3F75DF-0DCC-4BA1-89FF-AE692734A277 ComputerName S2D2 IPAddress 10.0.0.101 MACAddress 00:15:5D:89:E9:71 SMBiosGuid 6E8B1544-844B-4D8A-BDF2-217033230069 ComputerName S2D3 IPAddress 10.0.0.102 MACAddress 00:15:5D:89:E9:73 SMBiosGuid 8618D3F3-09E6-4E9A-878F-7A4D3A032BA5 ComputerName S2D4 IPAddress 10.0.0.103 MACAddress 00:15:5D:89:E9:75 #> $messages=Invoke-Command -ComputerName $VMMServerName -ScriptBlock {(Get-WinEvent -FilterHashTable @{LogName="Microsoft-VirtualMachineManager-Server/Admin";StartTime=(get-date).AddHours(-1)} | Where-Object message -Like "*will not deploy*" | Sort-Object timecreated).message | Select-Object -Unique} $HVHosts = @() $GUIDS=@() $i=1 foreach ($message in $Messages){ if (!($guids).Contains($message.Substring(76,37))){ $HVHosts+= @{ ComputerName="$ServersNamePrefix$i";SMBiosGuid = $message.Substring(76,37) ; MACAddress = $message.Substring(118,17);IPAddress="$IpaddressScope$($IPAddressStart.tostring())"} $i++ $IPAddressStart++ $GUIDS+=$message.Substring(76,37) } } #Create DHCP reservations for Hyper-V hosts #install RSAT for DHCP if ((Get-ItemPropertyValue -Path 'HKLM:\SOFTWARE\Microsoft\Windows NT\CurrentVersion\' -Name InstallationType) -ne "Client"){ Install-WindowsFeature -Name RSAT-DHCP } #Add DHCP Reservations foreach ($HVHost in $HVHosts){ if (!(Get-DhcpServerv4Reservation -ErrorAction SilentlyContinue -ComputerName $DHCPServer -ScopeId $ScopeID -ClientId ($HVHost.MACAddress).Replace(":","") | Where-Object IPAddress -eq $HVHost.IPAddress)){ Add-DhcpServerv4Reservation -ComputerName $DHCPServer -ScopeId $ScopeID -IPAddress $HVHost.IPAddress -ClientId ($HVHost.MACAddress).Replace(":","") } } #configure NTP server in DHCP (might be useful if Servers have issues with time) if (!(get-DhcpServerv4OptionValue -ComputerName $DHCPServer -ScopeId $ScopeID -OptionId 042 -ErrorAction SilentlyContinue)){ Set-DhcpServerv4OptionValue -ComputerName $DHCPServer -ScopeId $ScopeID -OptionId 042 -Value "10.0.0.1" } #deploy hosts $PhysicalComputerProfile=Get-SCPhysicalComputerProfile -Name $PhysicalComputerProfileName $HostGroup=Get-SCVMHostGroup -Name $HostGroupName foreach ($HVHost in $HVHosts){ $NetworkAdapters = @() $NetworkAdapters += New-SCPhysicalComputerNetworkAdapterConfig -UseDhcpForIPConfiguration -SetAsManagementNIC -SetAsPhysicalNetworkAdapter -MACAddress $HVHost.MACAddress <#Example of real deployment $PhysicalComputerConfig = New-SCPhysicalComputerConfig -BypassADMachineAccountCheck -BMCAddress $HVHost.BMCAddress -BMCPort 623 -BMCProtocol "IPMI" -BMCRunAsAccount $RunAsAccount -ComputerName $HVHost.ComputerName -Description "" -SMBiosGuid $HVHost.SMBiosGuid -PhysicalComputerProfile $PhysicalComputerProfile -VMHostGroup $HostGroup -BootDiskVolume "\\.\PHYSICALDRIVE0" -PhysicalComputerNetworkAdapterConfig $NetworkAdapters #> #Deployment in virtual environment $PhysicalComputerConfig = New-SCPhysicalComputerConfig -SkipBmcPowerControl -BypassADMachineAccountCheck -ComputerName $HVHost.ComputerName -Description "" -SMBiosGuid $HVHost.SMBiosGuid -PhysicalComputerProfile $PhysicalComputerProfile -VMHostGroup $HostGroup -BootDiskVolume "\\.\PHYSICALDRIVE0" -PhysicalComputerNetworkAdapterConfig $NetworkAdapters New-SCVMHost -VMHostConfig $PhysicalComputerConfig -RunAsynchronously } #verify status of deployment jobs. $jobs=Get-SCJob | Where-Object Name -like "Create a new host from physical machine*" | Sort-Object Name foreach ($Job in $jobs){ If ($job.status -eq "Running"){ Write-Output "Waiting for $($job.Name.Substring(41,($job.Name.Length-41))) to Finish" do { [System.Console]::Write("Progress {0}`r", $job.Progress) Start-Sleep 1 } until (($job.status -eq "Completed") -or ($job.status -eq "Failed") -or ($job.status -eq "SucceedWithInfo")) } if (($job.status -eq "Completed") -or ($job.status -eq "SucceedWithInfo")){ Write-Output "Deployment of Host $($job.Name.Substring(41,($job.Name.Length-41))) Finished" } if ($job.status -eq "failed"){ Write-Output "Deployment of Host $($job.Name.Substring(41,($job.Name.Length-41))) Failed" } } #endregion ######################### # Action on Hyper-V Host# ######################### #Restart (turn off and start) the S2D machines on Host manualy to initiate deployment (othervise deployment progress will stick at 29% and fails) #This step mimics BMC, that will send reboot to hosts. ################################### # Continue on DC or Management VM # ################################### #region Apply vSwitch #refresh hosts Get-SCVMHost | Read-SCVMHost #apply vSwitch Note: this takes forever, so be patient foreach ($HVHost in $HVHosts){ $vmHost = Get-SCVMHost | Where-Object computername -eq $HVHost.ComputerName #Make management adapter only the one defined in $HVHosts $ManagementAdapter=(Get-SCVMHostNetworkAdapter -VMHost $VMHost.Name) | Where-Object {$_.IPAddresses.IPAddressToString -eq $HVHost.IPAddress} $VMHost | Get-SCVMHostNetworkAdapter | Where-Object Name -ne $ManagementAdapter.Name | Set-SCVMHostNetworkAdapter -UsedForManagement $false $networkAdapter = @() # Set uplink port profile to all adapters $vmhost | Get-SCVMHostNetworkAdapter | ForEach-Object { Set-SCVMHostNetworkAdapter -VMHostNetworkAdapter $_ -UplinkPortProfileSet (Get-SCUplinkPortProfileSet -Name $UplinkPPName) $networkAdapter += $_ } $logicalSwitch = Get-SCLogicalSwitch -Name $vSwitchName New-SCVirtualNetwork -VMHost $vmHost -VMHostNetworkAdapters $networkAdapter -LogicalSwitch $logicalSwitch -DeployVirtualNetworkAdapters Set-SCVMHost -VMHost $vmHost -RunAsynchronously } $servers=$HVHosts.ComputerName #Verify that the VlanID is set Get-VMNetworkAdapterVlan -ManagementOS -CimSession $servers |Sort-Object -Property Computername | Format-Table ComputerName,AccessVlanID,ParentAdapter -AutoSize -GroupBy ComputerName #verify RDMA Get-NetAdapterRdma -CimSession $servers | Sort-Object -Property Systemname | Format-Table systemname,interfacedescription,name,enabled -AutoSize -GroupBy Systemname #verify ip config Get-NetIPAddress -CimSession $servers -InterfaceAlias vEthernet* -AddressFamily IPv4 | Sort-Object -Property PSComputername | Format-Table pscomputername,interfacealias,ipaddress -AutoSize -GroupBy pscomputername #endregion #region set static IP Does not work ?? BUG ?? <# foreach ($HVHost in $HVHosts){ $vmHost = Get-SCVMHost | where computername -eq $HVHost.ComputerName $vNic = $VMHost | Get-SCVirtualNetworkAdapter | where IsUsedForHostManagement -eq $True $vmNetwork = Get-SCVMNetwork -Name $vNIC.VMNetwork $vmSubnet = Get-SCVMSubnet -Name $vNIC.VMSubnet $vNICPortClassification = Get-SCPortClassification -Name $vNIC.PortClassification $vNicLogicalSwitch = Get-SCLogicalSwitch -Name $vNic.LogicalSwitch $ipV4Pool = Get-SCStaticIPAddressPool | where Subnet -eq $Vnic.IPv4Subnets $ipv4List=$vnic.IPv4Addresses Set-SCVirtualNetworkAdapter -VirtualNetworkAdapter $vNic -VMNetwork $vmNetwork -VMSubnet $vmSubnet -PortClassification $vNICPortClassification -IPv4AddressType "Static" -IPv4AddressPools $ipV4Pool -IPv4Addresses $ipv4List -IPv6AddressType "Dynamic" Set-SCVMHost -VMHost $vmHost -RunAsynchronously } #> #endregion #region Configure Networking (classic approach) #set static IP address (need to test more, not sure if this is OK) Foreach ($Server in $servers){ Invoke-Command -ComputerName $server -ArgumentList $vSwitchName -ScriptBlock { param ($vSwitchname); $IPConf=Get-NetIPConfiguration | Where-Object InterfaceAlias -like "*$vSwitchName*" $IPAddress=Get-NetIPAddress -AddressFamily IPv4 | Where-Object InterfaceAlias -like "*$vSwitchName*" $IP=$IPAddress.IPAddress $Index=$IPAddress.InterfaceIndex $GW=$IPConf.IPv4DefaultGateway.NextHop $Prefix=$IPAddress.PrefixLength $DNSServers=@() $ipconf.dnsserver | ForEach-Object {if ($_.addressfamily -eq 2){$DNSServers+=$_.ServerAddresses}} Set-NetIPInterface -InterfaceIndex $Index -Dhcp Disabled New-NetIPAddress -InterfaceIndex $Index -AddressFamily IPv4 -IPAddress $IP -PrefixLength $Prefix -DefaultGateway $GW -ErrorAction SilentlyContinue Set-DnsClientServerAddress -InterfaceIndex $index -ServerAddresses $DNSServers } } #Refresh VM Hosts Get-SCVMHost | Read-SCVMHost #Associate each of the vNICs configured for RDMA to a physical adapter that is up and is not virtual (to be sure that each RDMA enabled ManagementOS vNIC is mapped to separate RDMA pNIC) #install features foreach ($server in $servers) {Install-WindowsFeature -Name "Hyper-V-PowerShell" -ComputerName $server} #Associate vNICs Invoke-Command -ComputerName $servers -ArgumentList $vSwitchName -ScriptBlock { param($vSwitchName); $physicaladapters=(get-vmswitch $vSwitchName).NetAdapterInterfaceDescriptions | Sort-Object 1..$physicaladapters.Count | ForEach-Object { Set-VMNetworkAdapterTeamMapping -VMNetworkAdapterName "SMB_$_" -ManagementOS -PhysicalNetAdapterName (get-netadapter -InterfaceDescription $physicaladapters | Select-Object -Index ($_-1)).name } } #verify mapping Get-VMNetworkAdapterTeamMapping -CimSession $servers -ManagementOS | Format-Table ComputerName,NetAdapterName,ParentAdapter #configure DCB if requested if ($DCB -eq $True){ #Install DCB if (!$NanoServer){ foreach ($server in $servers) {Install-WindowsFeature -Name "Data-Center-Bridging" -ComputerName $server} } ##Configure QoS New-NetQosPolicy "SMB" -NetDirectPortMatchCondition 445 -PriorityValue8021Action 3 -CimSession $servers New-NetQosPolicy "ClusterHB" -Cluster -PriorityValue8021Action 7 -CimSession $servers New-NetQosPolicy "Default" -Default -PriorityValue8021Action 0 -CimSession $servers #Turn on Flow Control for SMB Invoke-Command -ComputerName $servers -ScriptBlock {Enable-NetQosFlowControl -Priority 3} #Disable flow control for other traffic than 3 (pause frames should go only from prio 3) Invoke-Command -ComputerName $servers -ScriptBlock {Disable-NetQosFlowControl -Priority 0,1,2,4,5,6,7} #Disable Data Center bridging exchange (disable accept data center bridging (DCB) configurations from a remote device via the DCBX protocol, which is specified in the IEEE data center bridging (DCB) standard.) Invoke-Command -ComputerName $servers -ScriptBlock {Set-NetQosDcbxSetting -willing $false -confirm:$false} #Configure IeeePriorityTag #IeePriorityTag needs to be On if you want tag your nonRDMA traffic for QoS. Can be off if you use adapters that pass vSwitch (both SR-IOV and RDMA bypasses vSwitch) Invoke-Command -ComputerName $servers -ScriptBlock {Set-VMNetworkAdapter -ManagementOS -Name "SMB*" -IeeePriorityTag on} #validate flow control setting Invoke-Command -ComputerName $servers -ScriptBlock { Get-NetQosFlowControl} | Sort-Object -Property PSComputername | ft PSComputerName,Priority,Enabled -GroupBy PSComputerName #Validate DCBX setting Invoke-Command -ComputerName $servers -ScriptBlock {Get-NetQosDcbxSetting} | Sort-Object PSComputerName | Format-Table Willing,PSComputerName #Apply policy to the target adapters. The target adapters are adapters connected to vSwitch Invoke-Command -ComputerName $servers -ScriptBlock {Enable-NetAdapterQos -InterfaceDescription (Get-VMSwitch).NetAdapterInterfaceDescriptions} #validate policy Invoke-Command -ComputerName $servers -ScriptBlock {Get-NetAdapterQos | where enabled -eq true} | Sort-Object PSComputerName #Create a Traffic class and give SMB Direct 60% of the bandwidth minimum. The name of the class will be "SMB". #This value needs to match physical switch configuration. Value might vary based on your needs. #If connected directly (in 2 node configuration) skip this step. Invoke-Command -ComputerName $servers -ScriptBlock {New-NetQosTrafficClass "SMB" -Priority 3 -BandwidthPercentage 60 -Algorithm ETS} Invoke-Command -ComputerName $servers -ScriptBlock {New-NetQosTrafficClass "ClusterHB" -Priority 7 -BandwidthPercentage 1 -Algorithm ETS} } #enable iWARP firewall rule if requested if ($iWARP -eq $True){ Enable-NetFirewallRule -Name "FPSSMBD-iWARP-In-TCP" -CimSession $servers } #endregion #region Configure Cluster and S2D (classic approach) <#Create Cluster with SCVMM - Validate cluster takes forever... skipping #get hosts $VMHosts = @() foreach ($server in $servers){ $VMHosts += Get-SCVMHost | where computername -eq $server } #Grab run as account $credential = Get-SCRunAsAccount -Name $RunAsAccountName #create cluster Install-SCVMHostCluster -ClusterName $ClusterName -EnableS2D -Credential $credential -VMHost $VMHosts -ClusterIPAddress $ClusterIP -SkipValidation #> #Classic approach to enable cluster and S2D #install features foreach ($server in $servers) {Install-WindowsFeature -Name "Failover-Clustering","RSAT-Clustering","RSAT-Clustering-PowerShell" -ComputerName $server} #create cluster Test-Cluster -Node $servers -Include "Storage Spaces Direct",Inventory,Network,"System Configuration" New-Cluster -Name $ClusterName -node $servers -StaticAddress $ClusterIP Start-Sleep 5 Clear-DnsClientCache #Enable-ClusterS2D with invoke command, as RSAT1709 is not compatible with 1607, so it might fail without invoke-command Invoke-Command -ComputerName $clustername -ScriptBlock {Enable-ClusterS2D -confirm:0 -Verbose} #rename networks (Get-ClusterNetwork -Cluster $clustername | Where-Object Address -eq $StorageNetwork).Name="SMB" (Get-ClusterNetwork -Cluster $clustername | Where-Object Address -eq $ManagementNetwork).Name="Management" #Configure LM to use RDMA Get-ClusterResourceType -Cluster $clustername -Name "Virtual Machine" | Set-ClusterParameter -Name MigrationExcludeNetworks -Value ([String]::Join(";",(Get-ClusterNetwork -Cluster $clustername | Where-Object {$_.Name -ne "SMB"}).ID)) #Set-VMHost -VirtualMachineMigrationPerformanceOption SMB -cimsession $servers foreach ($Server in $servers){ Get-VMHost -ComputerName $Server | Set-VMHost -MigrationPerformanceOption UseSmbTransport } #Configure SMB Bandwidth Limits for Live Migration path_to_url #install feature Invoke-Command -ComputerName $servers -ScriptBlock {Install-WindowsFeature -Name "FS-SMBBW"} #Calculate 40% of capacity of NICs in vSwitch (considering 2 NICs, if 1 fails, it will not consume all bandwith, therefore 40%) $Adapters=(Get-VMSwitch -CimSession $Servers[0]).NetAdapterInterfaceDescriptions $BytesPerSecond=((Get-NetAdapter -CimSession $Servers[0] -InterfaceDescription $adapters).TransmitLinkSpeed | Measure-Object -Sum).Sum/8 Set-SmbBandwidthLimit -Category LiveMigration -BytesPerSecond ($BytesPerSecond*0.4) -CimSession $Servers #set CSV Cache #(Get-Cluster $ClusterName).BlockCacheSize = 10240 #configure witness #Create new directory $WitnessName=$Clustername+"Witness" Invoke-Command -ComputerName DC -ScriptBlock {param($WitnessName);new-item -Path c:\Shares -Name $WitnessName -ItemType Directory} -ArgumentList $WitnessName $accounts=@() $accounts+="corp\$ClusterName$" $accounts+="corp\Domain Admins" New-SmbShare -Name $WitnessName -Path "c:\Shares\$WitnessName" -FullAccess $accounts -CimSession DC # Set NTFS permissions Invoke-Command -ComputerName DC -ScriptBlock {param($WitnessName);(Get-SmbShare "$WitnessName").PresetPathAcl | Set-Acl} -ArgumentList $WitnessName #Set Quorum Set-ClusterQuorum -Cluster $ClusterName -FileShareWitness "\\DC\$WitnessName" #endregion #region Create some Volumes (classic approach) #Create volumes 1..(get-clusternode -Cluster $clustername).count | ForEach-Object { New-Volume -StoragePoolFriendlyName "S2D on $ClusterName" -FriendlyName MirrorDisk$_ -FileSystem CSVFS_ReFS -StorageTierFriendlyNames Capacity -StorageTierSizes 2TB -CimSession $ClusterName New-Volume -StoragePoolFriendlyName "S2D on $ClusterName" -FriendlyName MirrorAcceleratedParity$_ -FileSystem CSVFS_ReFS -StorageTierFriendlyNames performance,capacity -StorageTierSizes 2TB,8TB -CimSession $ClusterName } #Fix volume names Get-ClusterSharedVolume -Cluster $ClusterName | ForEach-Object { $volumepath=$_.sharedvolumeinfo.friendlyvolumename $newname=$_.name.Substring(22,$_.name.Length-23) Invoke-Command -ComputerName (Get-ClusterSharedVolume -Cluster $ClusterName -Name $_.Name).ownernode -ScriptBlock {param($volumepath,$newname); Rename-Item -Path $volumepath -NewName $newname} -ArgumentList $volumepath,$newname -ErrorAction SilentlyContinue } #endregion #region Create some dummy VMs (3 per each CSV disk) Start-Sleep -Seconds 60 #just to a bit wait as I saw sometimes that first VMs fails to create $CSVs=(Get-ClusterSharedVolume -Cluster $ClusterName).Name foreach ($CSV in $CSVs){ $CSV=($csv -split '\((.*?)\)')[1] 1..3 | ForEach-Object { $VMName="TestVM$($CSV)_$_" Invoke-Command -ComputerName ((Get-ClusterNode -Cluster $ClusterName).Name | Get-Random) -ArgumentList $CSV,$VMName -ScriptBlock { param($CSV,$VMName); New-VM -Name $VMName -NewVHDPath "c:\ClusterStorage\$CSV\$VMName\Virtual Hard Disks\$VMName.vhdx" -NewVHDSizeBytes 32GB -SwitchName SETSwitch -Generation 2 -Path "c:\ClusterStorage\$CSV\" } Add-ClusterVirtualMachineRole -VMName $VMName -Cluster $ClusterName } } #endregion #region add storage provider to VMM $ClassS2D=New-SCStorageClassification -Name "S2D" -Description "" -RunAsynchronously $ClassMirror=New-SCStorageClassification -Name "Mirror" -Description "" -RunAsynchronously $ClassMAP=New-SCStorageClassification -Name "MirrorAcceleratedParity" -Description "" -RunAsynchronously $runAsAccount = Get-SCRunAsAccount -Name $RunAsAccountName Add-SCStorageProvider -ComputerName $ClusterName -AddWindowsNativeWmiProvider -Name $Clustername -RunAsAccount $runAsAccount -RunAsynchronously $provider = Get-SCStorageProvider -Name "s2d-cluster" Set-SCStorageProvider -StorageProvider $provider -RunAsynchronously $pool = Get-SCStoragePool -Name "S2D on $Clustername" $ClassS2D = Get-SCStorageClassification -Name "S2D" $Pool | Set-SCStoragePool -StorageClassification $ClassS2D #refresh provider Read-SCStorageProvider $provider Get-SCStorageDisk | Where-Object StorageLogicalUnit -like MirrorDisk* | Set-SCStorageDisk -StorageClassification $ClassMirror Get-SCStorageDisk | Where-Object StorageLogicalUnit -like MirrorAcceleratedParity* | Set-SCStorageDisk -StorageClassification $ClassMAP #endregion ```
```java Short-circuit evaluation Difference between ```HashMap``` and ```Hashtable``` Common mistake on switch statements Locks in `static synchronized` methods Measuring time ```
```javascript Check if an argument is a number Types of numbers Treating a boolean as number Apply `map` function to array items JavaScript compilation ```
```python import queue import copy class DirectedGraph(object): """ Directed Graph, with graph represented as an adjacency list """ def __init__(self): self.adjacency_list = {} def add_edge(self, source, destination): """ Adds an edge defined by vertices source and destination :param source: :param destination: :return: """ if source not in self.adjacency_list: self.adjacency_list[source] = set() self.adjacency_list[source].add(destination) def get_vertex(self): """ Generator for returning the next vertex from the adjacency list :return: """ for v in self.adjacency_list: yield v def get_neighbor(self, vertex): """ Generator for returning the next vertex adjacent to the given vertex :param vertex: :return: """ if vertex in self.adjacency_list: for u in self.adjacency_list[vertex]: yield u def get_reverse_neighbor(self, vertex): """ Generator for returning the reversed edge neighbor to the given vertex (parent) :param vertex: :return: """ reversed_list = {} for v, u in self.adjacency_list.items(): for w in u: if w not in reversed_list: reversed_list[w] = set() reversed_list[w].add(v) if vertex in reversed_list: for u in reversed_list[vertex]: yield u def dfs(self): """ Computes the initial source vertices for each connected component and the parents for each vertex as determined through depth-first-search :return: initial source vertices for each connected component, parents for each vertex :rtype: set, dict """ parents = {} components = set() to_visit = [] for vertex in self.get_vertex(): if vertex not in parents: components.add(vertex) else: continue to_visit.append(vertex) while to_visit: v = to_visit.pop() for neighbor in self.get_neighbor(v): if neighbor not in parents: parents[neighbor] = v to_visit.append(neighbor) return components, parents def bfs(self): """ Computes the the parents for each vertex as determined through breadth-first search :return: parents for each vertex :rtype: dict """ parents = {} to_visit = queue.Queue() for vertex in self.get_vertex(): to_visit.put(vertex) while not to_visit.empty(): v = to_visit.get() for neighbor in self.get_neighbor(v): if neighbor not in parents: parents[neighbor] = v to_visit.put(neighbor) return parents def contains_cycle(self): """ Determines if one of the connected components contains a cycle :return: true if one of the connected components contains a cycle :rtype: bool """ contains_cycle = False STATUS_STARTED = 1 STATUS_FINISHED = 2 for vertex in self.get_vertex(): statuses = {} to_visit = [vertex] while to_visit and not contains_cycle: v = to_visit.pop() if v in statuses: if statuses[v] == STATUS_STARTED: statuses[v] = STATUS_FINISHED else: statuses[v] = STATUS_STARTED to_visit.append(v) # add to stack again to signal vertex has finished DFS for u in self.get_neighbor(v): if u in statuses: if statuses[u] == STATUS_STARTED: contains_cycle = True break else: to_visit.append(u) if contains_cycle: break return contains_cycle def topological_sort(self): """ Determines the priority of vertices to be visited. :return: """ STATUS_STARTED = 1 STATUS_FINISHED = 2 order = [] statuses = {} assert (not self.contains_cycle()) for vertex in self.get_vertex(): to_visit = [vertex] while to_visit: v = to_visit.pop() if v in statuses: if statuses[v] == STATUS_STARTED: statuses[v] = STATUS_FINISHED order.append(v) else: statuses[v] = STATUS_STARTED to_visit.append(v) # add to stack again to signal vertex has finished DFS for u in self.get_neighbor(v): if u not in statuses: to_visit.append(u) order.reverse() return order def strongly_connected_components(self): """ Compute the vertices in the strongly connected components :return list of lists, one for each component's vertices: """ stack = self.scc_dfs_forward_pass() components = self.scc_dfs_reverse_pass(stack) return components def scc_dfs_forward_pass(self): stack = [] visited = set() for v in self.get_vertex(): self.dfs_forward(v, stack, visited) return stack def dfs_forward(self, vertex, stack, visited): if vertex not in visited: visited.add(vertex) for u in self.get_neighbor(vertex): self.dfs_forward(u, stack, visited) stack.append(vertex) def scc_dfs_reverse_pass(self, stack): components = [] visited = set() while stack: v = stack.pop() if v not in visited: component = [] self.dfs_reverse(v, component, visited) component.reverse() components.append(component) return components def dfs_reverse(self, vertex, component, visited): if vertex not in visited: visited.add(vertex) component.append(vertex) for u in self.get_reverse_neighbor(vertex): self.dfs_reverse(u, component, visited) def get_test_graph_1(): dg = DirectedGraph() dg.add_edge(0, 1) dg.add_edge(0, 5) dg.add_edge(1, 2) dg.add_edge(2, 4) dg.add_edge(2, 6) dg.add_edge(3, 2) dg.add_edge(5, 8) dg.add_edge(6, 5) dg.add_edge(7, 5) dg.add_edge(7, 5) return dg def get_test_graph_2(): dg_small = DirectedGraph() dg_small.add_edge(2, 1) dg_small.add_edge(4, 5) dg_small.add_edge(0, 1) dg_small.add_edge(1, 4) dg_small.add_edge(1, 3) return dg_small def get_test_graph_3(): dg_other = DirectedGraph() dg_other.add_edge(3, 11) dg_other.add_edge(5, 2) dg_other.add_edge(2, 4) dg_other.add_edge(2, 7) dg_other.add_edge(8, 11) dg_other.add_edge(4, 7) dg_other.add_edge(7, 8) return dg_other def get_test_graph_4(): """ Returns graph containing a cycle :return: """ dg = copy.copy(get_test_graph_1()) dg.add_edge(8, 0) # creates cycle return dg def get_test_graph_5(): """ Returns a graph with 3 cycles and 5 strongly connected components :return: """ dg = DirectedGraph() dg.add_edge(0, 2) dg.add_edge(1, 3) dg.add_edge(3, 2) dg.add_edge(2, 1) dg.add_edge(4, 5) dg.add_edge(5, 6) dg.add_edge(6, 4) dg.add_edge(3, 5) dg.add_edge(7, 5) dg.add_edge(8, 10) dg.add_edge(10, 11) dg.add_edge(11, 9) dg.add_edge(9, 8) return dg def test_dfs(): dg1 = get_test_graph_1() c1, p1 = dg1.dfs() assert (c1 == {0, 3, 7}) assert (p1 == {1: 0, 2: 1, 4: 2, 5: 0, 6: 2, 8: 5}) def test_bfs(): dg1 = get_test_graph_1() p1 = dg1.bfs() assert (p1 == {1: 0, 2: 1, 4: 2, 5: 0, 6: 2, 8: 5}) def test_contains_cycle(): assert (get_test_graph_1().contains_cycle() == False) assert (get_test_graph_2().contains_cycle() == False) assert (get_test_graph_3().contains_cycle() == False) assert (get_test_graph_4().contains_cycle() == True) def test_topological_sort(): assert (get_test_graph_1().topological_sort() == [7, 3, 0, 1, 2, 4, 6, 5, 8]) assert (get_test_graph_2().topological_sort() == [2, 0, 1, 3, 4, 5]) assert (get_test_graph_3().topological_sort() == [5, 3, 2, 4, 7, 8, 11]) def test_strongly_connected_components(): dg = get_test_graph_5() assert (dg.contains_cycle()) components = dg.strongly_connected_components() assert (components == [[10, 11, 9, 8], [7], [0], [1, 3, 2], [6, 4, 5]]) def main(): test_dfs() test_bfs() test_contains_cycle() test_topological_sort() test_strongly_connected_components() print("Tests complete.") if __name__ == "__main__": main() ```
Eretmocera impactella is a moth of the family Scythrididae. This species is known from Oman, United Arab Emirates, India, Sri Lanka, Taiwan and Thailand and Pakistan. Description The forewings are blackish brown with more or less distinct whitish or white yellowish markings. Biology The larvae feed on various Amaranthaceae species and other food plants. Gallery References External links boldsystems.org: Pictures of this species impactella Invertebrates of the Arabian Peninsula Moths described in 1864
```yaml {{- /* */}} {{- if and .Values.replica.autoscaling.hpa.enabled .Values.sentinel.enabled }} apiVersion: {{ include "common.capabilities.hpa.apiVersion" ( dict "context" $ ) }} kind: HorizontalPodAutoscaler metadata: name: {{ printf "%s-node" (include "common.names.fullname" .) }} namespace: {{ include "common.names.namespace" . | quote }} labels: {{- include "common.labels.standard" ( dict "customLabels" .Values.commonLabels "context" $ ) | nindent 4 }} app.kubernetes.io/component: replica app.kubernetes.io/part-of: valkey {{- if .Values.commonAnnotations }} annotations: {{- include "common.tplvalues.render" ( dict "value" .Values.commonAnnotations "context" $ ) | nindent 4 }} {{- end }} spec: scaleTargetRef: apiVersion: {{ include "common.capabilities.deployment.apiVersion" . }} kind: StatefulSet name: {{ printf "%s-node" (include "common.names.fullname" .) }} minReplicas: {{ .Values.replica.autoscaling.hpa.minReplicas }} maxReplicas: {{ .Values.replica.autoscaling.hpa.maxReplicas }} metrics: {{- if .Values.replica.autoscaling.hpa.targetMemory }} - type: Resource resource: name: memory {{- if semverCompare "<1.23-0" (include "common.capabilities.kubeVersion" .) }} targetAverageUtilization: {{ .Values.replica.autoscaling.hpa.targetMemory }} {{- else }} target: type: Utilization averageUtilization: {{ .Values.replica.autoscaling.hpa.targetMemory }} {{- end }} {{- end }} {{- if .Values.replica.autoscaling.hpa.targetCPU }} - type: Resource resource: name: cpu {{- if semverCompare "<1.23-0" (include "common.capabilities.kubeVersion" .) }} targetAverageUtilization: {{ .Values.replica.autoscaling.hpa.targetCPU }} {{- else }} target: type: Utilization averageUtilization: {{ .Values.replica.autoscaling.hpa.targetCPU }} {{- end }} {{- end }} {{- end }} ```
Nikoghayos Tigranian (, 31 August 1856, Alexandropol – 17 February 1951, Yerevan) was an Armenian composer, pianist, musicologist, and sociocultural activist. He introduced the Braille System to Armenia. Biography Nikoghayos Tigranian was born in Alexandropol in the Russian Empire (present-day Gyumri, Armenia) to a prominent family. His younger brother Sirakan Tigranian was the foreign minister of the First Republic of Armenia. Hovsep and Ghazar Tigranian, also his brothers, were trustees of Nersisian School. Nikoghayos lost his sight at the age of 9 as a result of smallpox. His family sent him to Vienna in 1873 to study at the Imperial Royal Institute for the Education of the Blind (1873–1880). He also took piano lessons from Professor Schenner of the Vienna Conservatory (now named University of Music and Performing Arts). He returned to his homeland in 1880. He gave piano recitals and delivered lectures in Western Europe, Russia and Transcaucasia, and published several articles on Oriental music. In 1893, Tigranian studied composition at the St. Petersburg Conservatory with Rimsky-Korsakov and N.F. Solovyov. Music He collected folk music, particularly mughams, which he used in original works and in various arrangements. He was awarded a bronze medal at the 1900 Paris International Festival as a “pioneer in collecting and featuring Oriental melodies”. It was through his efforts that melodies sung at the turn of the previous century in Transcaucasia by Armenian, Persian and Kurdish peoples were preserved. A number of composers, including Alexander Spendiaryan, Aram Khachaturian, Mikhail Ippolitov-Ivanov, Reinhold Moritzevich Glière, Armen Tigranian, and Sargis Barkhudaryan, have utilized these melodies in their own compositions. Tigranian was the first composer to translate such music into orchestral terms. In his compositions, Tigranian's motto was to always stay faithful to the spirit of the folk music, to communicate the timbre of folk instruments, and to retain the plasticity of folk dances. His approach became an example to other composers who expanded further Tigranian's ideas and tools. In 1921, Nikoghayos Tigranian implemented the Braille System for the first time in Armenia at the Gyumri school he founded. He moved to Yerevan in 1934 where he died in 1951. A collection of his articles, memoires and letters was published in 1981. A street in Yerevan and the Art School of Gyumri are named after him. Awards People's Artist of the Armenian SSR (1933) Hero of Socialist Labour (1936) Order of the Red Banner of Labour (1939) References Bibliography Ruzanna Mazmanyan. Nikoghayos Tigranyan: Ocherk Zhizni i Tvorchestva [Essay on Life and Creativity]. Yerevan: Sovetakan Grokh, 1978. Nikoghayos Tigranyan. Hodvatsner, husher, namakner, 1981 NIKOLAY FADDEEVICH TIGRANOV Oriental Music, Leningrad 1927. Lonigradskiy Gublit e 36130, 31/2 nel. A. - Circulation 1000 The State Academic Printing House. VO, line 9. Book in Russian. External links Biography Biography A letter from Komitas Armenian composers Armenian musicologists Armenian classical pianists Musicians from the Russian Empire Armenian ethnomusicologists Blind classical musicians Saint Petersburg Conservatory alumni People from Gyumri 1856 births 1951 deaths People's Artists of Armenia
Sir Hilary Nicholas Hugh Synnott KCMG (20 March 1945 – 8 September 2011) was a British diplomat who was Regional Coordinator of the Coalition Provisional Authority (CPA) in Southern Iraq from 2003 to 2004, before retiring in 2005. He published a book about his time there called 'Bad Days In Basra'. Education Hilary Synnott attended Peterhouse, Cambridge where he was awarded an MA. From 1962 to 1973, he was a Royal Navy officer serving as a submariner. Diplomatic career In 1973, Synnott joined the Foreign and Commonwealth Office as Second Secretary. He was posted as First Secretary to UKDEL OECD Paris in 1975 and was transferred to Bonn in 1978. He returned to the FCO in 1981. In November 1985, Synnott was appointed Counsellor, Consul-General and Head of Chancery in Amman. He was Deputy High Commissioner to India from 1993 to 1996. At the FCO, he served as Director for South and South East Asian Affairs from 1996 until 1998. He was appointed British High Commissioner to Pakistan from 2000 until 2003. In his final posting to Iraq, Sir Hilary replaced the Danish Ambassador Ole Wøhlers Olsen who had complained at the lack of support given to his reconstruction efforts. Post retirement On 9 December 2009, Synnott gave evidence to The Iraq Inquiry in which he was critical of the Coalition Provisional Authority. References External links BBC News 'Tribal justice takes hold in Iraq' The Times, Tales of chaos, by our man in Basra BBC Today, discussing whether the Obama administration is seeking new allies in Pakistan 1945 births Alumni of Peterhouse, Cambridge Royal Navy officers High Commissioners of the United Kingdom to Pakistan Members of HM Diplomatic Service Coalition Provisional Authority Knights Commander of the Order of St Michael and St George 2011 deaths 20th-century British diplomats
Lewis Francis Brest (May 15, 1842 - December 2, 1915) was an American soldier who received the Medal of Honor for valor during the American Civil War. Biography Brest served in the American Civil War in the 57th Pennsylvania Infantry for the Union Army. He received the Medal of Honor on May 10, 1865 for his actions at the Battle of Sailor's Creek. Medal of Honor citation Rank and organization: Private, Company D, 57th Pennsylvania Infantry. Place and date: At Sailors Creek, Va., 6 April 1865. Entered service at:------. Birth: Mercer, Pa. Date of Issue: 10 May 1865. Citation: Capture of flag. See also List of American Civil War Medal of Honor recipients: A-F References External links Military Times 1842 births 1915 deaths Union Army soldiers United States Army Medal of Honor recipients People of Pennsylvania in the American Civil War American Civil War recipients of the Medal of Honor People from Mercer, Pennsylvania
```html <!-- @license This code may only be used under the BSD style license found at path_to_url The complete set of authors may be found at path_to_url The complete set of contributors may be found at path_to_url Code distributed by Google as part of the polymer project is also subject to an additional IP rights grant found at path_to_url --> <!-- `iron-icons` is a utility import that includes the definition for the `iron-icon` element, `iron-iconset-svg` element, as well as an import for the default icon set. The `iron-icons` directory also includes imports for additional icon sets that can be loaded into your project. Example loading icon set: <link rel="import" href="../iron-icons/maps-icons.html"> To use an icon from one of these sets, first prefix your `iron-icon` with the icon set name, followed by a colon, ":", and then the icon id. Example using the directions-bus icon from the maps icon set: <iron-icon icon="maps:directions-bus"></iron-icon> To load a subset of icons from one of the default `iron-icons` sets, you can use the [poly-icon](path_to_url tool. It allows you to select individual icons, and creates an iconset from them that you can use directly in your elements. See [iron-icon](#iron-icon) for more information about working with icons. See [iron-iconset](#iron-iconset) and [iron-iconset-svg](#iron-iconset-svg) for more information about how to create a custom iconset. @group Iron Elements @pseudoElement iron-icons @demo demo/index.html --> <link rel="import" href="../iron-icon/iron-icon.html"> <link rel="import" href="../iron-iconset-svg/iron-iconset-svg.html"> <iron-iconset-svg name="icons" size="24"> <svg><defs> <g id="3d-rotation"><path d="M7.52 21.48C4.25 19.94 1.91 16.76 1.55 13H.05C.56 19.16 5.71 24 12 24l.66-.03-3.81-3.81-1.33 1.32zm.89-6.52c-.19 0-.37-.03-.52-.08-.16-.06-.29-.13-.4-.24-.11-.1-.2-.22-.26-.37-.06-.14-.09-.3-.09-.47h-1.3c0 .36.07.68.21.95.14.27.33.5.56.69.24.18.51.32.82.41.3.1.62.15.96.15.37 0 .72-.05 1.03-.15.32-.1.6-.25.83-.44s.42-.43.55-.72c.13-.29.2-.61.2-.97 0-.19-.02-.38-.07-.56-.05-.18-.12-.35-.23-.51-.1-.16-.24-.3-.4-.43-.17-.13-.37-.23-.61-.31.2-.09.37-.2.52-.33.15-.13.27-.27.37-.42.1-.15.17-.3.22-.46.05-.16.07-.32.07-.48 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```go package errors import ( "strconv" "strings" ) type uncaughtPanic struct{ message string } func (p uncaughtPanic) Error() string { return p.message } // ParsePanic allows you to get an error object from the output of a go program // that panicked. This is particularly useful with path_to_url func ParsePanic(text string) (*Error, error) { lines := strings.Split(text, "\n") state := "start" var message string var stack []StackFrame for i := 0; i < len(lines); i++ { line := lines[i] if state == "start" { if strings.HasPrefix(line, "panic: ") { message = strings.TrimPrefix(line, "panic: ") state = "seek" } else { return nil, Errorf("bugsnag.panicParser: Invalid line (no prefix): %s", line) } } else if state == "seek" { if strings.HasPrefix(line, "goroutine ") && strings.HasSuffix(line, "[running]:") { state = "parsing" } } else if state == "parsing" { if line == "" { state = "done" break } createdBy := false if strings.HasPrefix(line, "created by ") { line = strings.TrimPrefix(line, "created by ") createdBy = true } i++ if i >= len(lines) { return nil, Errorf("bugsnag.panicParser: Invalid line (unpaired): %s", line) } frame, err := parsePanicFrame(line, lines[i], createdBy) if err != nil { return nil, err } stack = append(stack, *frame) if createdBy { state = "done" break } } } if state == "done" || state == "parsing" { return &Error{Err: uncaughtPanic{message}, frames: stack}, nil } return nil, Errorf("could not parse panic: %v", text) } // The lines we're passing look like this: // // main.(*foo).destruct(0xc208067e98) // /0/go/src/github.com/bugsnag/bugsnag-go/pan/main.go:22 +0x151 func parsePanicFrame(name string, line string, createdBy bool) (*StackFrame, error) { idx := strings.LastIndex(name, "(") if idx == -1 && !createdBy { return nil, Errorf("bugsnag.panicParser: Invalid line (no call): %s", name) } if idx != -1 { name = name[:idx] } pkg := "" if lastslash := strings.LastIndex(name, "/"); lastslash >= 0 { pkg += name[:lastslash] + "/" name = name[lastslash+1:] } if period := strings.Index(name, "."); period >= 0 { pkg += name[:period] name = name[period+1:] } name = strings.Replace(name, "", ".", -1) if !strings.HasPrefix(line, "\t") { return nil, Errorf("bugsnag.panicParser: Invalid line (no tab): %s", line) } idx = strings.LastIndex(line, ":") if idx == -1 { return nil, Errorf("bugsnag.panicParser: Invalid line (no line number): %s", line) } file := line[1:idx] number := line[idx+1:] if idx = strings.Index(number, " +"); idx > -1 { number = number[:idx] } lno, err := strconv.ParseInt(number, 10, 32) if err != nil { return nil, Errorf("bugsnag.panicParser: Invalid line (bad line number): %s", line) } return &StackFrame{ File: file, LineNumber: int(lno), Package: pkg, Name: name, }, nil } ```
```xml import type { AssetPathResolver } from "@Core/AssetPathResolver"; import { describe, expect, it, vi } from "vitest"; import { MacOsTrayIconFilePathResolver } from "./MacOsTrayIconFilePathResolver"; describe(MacOsTrayIconFilePathResolver, () => { describe(MacOsTrayIconFilePathResolver.prototype.resolve, () => { it("should return file path to 'ueliTemplate.png'", () => { const getModuleAssetPathMock = vi.fn().mockReturnValue("assetPath"); const assetPathResolver = <AssetPathResolver>{ getModuleAssetPath: (m, f) => getModuleAssetPathMock(m, f) }; expect(new MacOsTrayIconFilePathResolver(assetPathResolver).resolve()).toBe("assetPath"); expect(getModuleAssetPathMock).toHaveBeenCalledOnce(); expect(getModuleAssetPathMock).toHaveBeenCalledWith("TrayIcon", "ueliTemplate.png"); }); }); }); ```
Sue Worthington Bradley (born Sue Worthington Cox; December 25, 1883 – August 30, 1970) was the American First Lady of Guam from 1929 to 1931. She was the wife of naval Governor of Guam Willis W. Bradley. Early life On December 25, 1883, Bradley was born as Sue Worthington Cox in Baltimore, Maryland. Bradley's father was Henry Cox (1847-1915). Bradley's mother was Elizabeth Janney (nee Merrefield) Cox (1850-1926). Bradley's siblings include Rebecca, Lillian, Josephine and Douglas. Bradley attended Edgeworth School, a day and boarding school in Baltimore, Maryland. Career In 1929, when Willis W. Bradley was appointed the military Governor of Guam, Bradley became the First Lady of Guam on June 11, 1929, until March 15, 1931. Bradley became the President of Officers' Wives Club. On March 26, 1964, Bradley sponsored the launching of USS Bradley at Bethlehem Steel Co in San Francisco, California. The USS Bradley was named for Bradley's husband, Captain Willis Winter Bradley, Jr. Personal life On October 16, 1907, in Baltimore, Maryland, Bradley married Willis W. Bradley, Jr., who later became a US Navy officer and Military Governor of Guam. They had four daughters, Elizabeth, Sue, Anne, and Josephine. Bradley and her family lived in places including Long Beach, California and Guam. In Guam, Bradley and her family lived in the ancient Spanish Governor's Palace. On August 30, 1970, Bradley died in El Paso, Texas. Bradley is interred at Fort Rosecrans National Cemetery in San Diego, California. References External links The Role of a Sponsor at societyofsponsorsofusn.org Sue Worthington Cox Bradley at findagrave.com Sue Worthington Cox at ancestry.com 1883 births 1970 deaths Burials at Fort Rosecrans National Cemetery First ladies and gentlemen of Guam People from Maryland People from El Paso, Texas
```java /* This file is part of the iText (R) project. Authors: Apryse Software. This program is offered under a commercial and under the AGPL license. For commercial licensing, contact us at path_to_url For AGPL licensing, see below. AGPL licensing: This program is free software: you can redistribute it and/or modify (at your option) any later version. This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the along with this program. If not, see <path_to_url */ package com.itextpdf.barcodes.qrcode; final class MaskUtil { private MaskUtil() { } /** * Apply mask penalty rule 1 and return the penalty. Find repetitive cells with the same color and * give penalty to them. Example: 00000 or 11111. * @param matrix ByteMatrix to apply the penalty rule to * @return the rule 1 penalty */ public static int applyMaskPenaltyRule1(ByteMatrix matrix) { return applyMaskPenaltyRule1Internal(matrix, true) + applyMaskPenaltyRule1Internal(matrix, false); } /** * Apply mask penalty rule 2 and return the penalty. Find 2x2 blocks with the same color and give * penalty to them. * @param matrix ByteMatrix to apply the penalty rule to * @return the rule 2 penalty */ public static int applyMaskPenaltyRule2(ByteMatrix matrix) { int penalty = 0; byte[][] array = matrix.getArray(); int width = matrix.getWidth(); int height = matrix.getHeight(); for (int y = 0; y < height - 1; ++y) { for (int x = 0; x < width - 1; ++x) { int value = array[y][x]; if (value == array[y][x + 1] && value == array[y + 1][x] && value == array[y + 1][x + 1]) { penalty += 3; } } } return penalty; } /** * Apply mask penalty rule 3 and return the penalty. Find consecutive cells of 00001011101 or * 10111010000, and give penalty to them. If we find patterns like 000010111010000, we give * penalties twice (i.e. 40 * 2). * @param matrix ByteMatrix to apply the penalty rule to * @return the rule 3 penalty */ public static int applyMaskPenaltyRule3(ByteMatrix matrix) { int penalty = 0; byte[][] array = matrix.getArray(); int width = matrix.getWidth(); int height = matrix.getHeight(); for (int y = 0; y < height; ++y) { for (int x = 0; x < width; ++x) { // Tried to simplify following conditions but failed. if (x + 6 < width && array[y][x] == 1 && array[y][x + 1] == 0 && array[y][x + 2] == 1 && array[y][x + 3] == 1 && array[y][x + 4] == 1 && array[y][x + 5] == 0 && array[y][x + 6] == 1 && ((x + 10 < width && array[y][x + 7] == 0 && array[y][x + 8] == 0 && array[y][x + 9] == 0 && array[y][x + 10] == 0) || (x - 4 >= 0 && array[y][x - 1] == 0 && array[y][x - 2] == 0 && array[y][x - 3] == 0 && array[y][x - 4] == 0))) { penalty += 40; } if (y + 6 < height && array[y][x] == 1 && array[y + 1][x] == 0 && array[y + 2][x] == 1 && array[y + 3][x] == 1 && array[y + 4][x] == 1 && array[y + 5][x] == 0 && array[y + 6][x] == 1 && ((y + 10 < height && array[y + 7][x] == 0 && array[y + 8][x] == 0 && array[y + 9][x] == 0 && array[y + 10][x] == 0) || (y - 4 >= 0 && array[y - 1][x] == 0 && array[y - 2][x] == 0 && array[y - 3][x] == 0 && array[y - 4][x] == 0))) { penalty += 40; } } } return penalty; } /** * Apply mask penalty rule 4 and return the penalty. Calculate the ratio of dark cells and give * penalty if the ratio is far from 50%. It gives 10 penalty for 5% distance. Examples: * - 0% => 100 * - 40% => 20 * - 45% => 10 * - 50% => 0 * - 55% => 10 * - 55% => 20 * - 100% => 100 * @param matrix Bytematrix to apply the rule to * @return the rule 4 penalty */ public static int applyMaskPenaltyRule4(ByteMatrix matrix) { int numDarkCells = 0; byte[][] array = matrix.getArray(); int width = matrix.getWidth(); int height = matrix.getHeight(); for (int y = 0; y < height; ++y) { for (int x = 0; x < width; ++x) { if (array[y][x] == 1) { numDarkCells += 1; } } } int numTotalCells = matrix.getHeight() * matrix.getWidth(); double darkRatio = (double) numDarkCells / numTotalCells; return Math.abs((int) (darkRatio * 100 - 50)) / 5 * 10; } /** * Return the mask bit for "getMaskPattern" at "x" and "y". See 8.8 of JISX0510:2004 for mask * pattern conditions. * @param maskPattern masking pattern to use * @param x width coordiante * @param y height-coordinate * @return the mask bit at that position */ public static boolean getDataMaskBit(int maskPattern, int x, int y) { if (!QRCode.isValidMaskPattern(maskPattern)) { throw new IllegalArgumentException("Invalid mask pattern"); } int intermediate, temp; switch (maskPattern) { case 0: intermediate = (y + x) & 0x1; break; case 1: intermediate = y & 0x1; break; case 2: intermediate = x % 3; break; case 3: intermediate = (y + x) % 3; break; case 4: intermediate = ((y >>> 1) + (x / 3)) & 0x1; break; case 5: temp = y * x; intermediate = (temp & 0x1) + (temp % 3); break; case 6: temp = y * x; intermediate = (((temp & 0x1) + (temp % 3)) & 0x1); break; case 7: temp = y * x; intermediate = (((temp % 3) + ((y + x) & 0x1)) & 0x1); break; default: throw new IllegalArgumentException("Invalid mask pattern: " + maskPattern); } return intermediate == 0; } // Helper function for applyMaskPenaltyRule1. We need this for doing this calculation in both // vertical and horizontal orders respectively. private static int applyMaskPenaltyRule1Internal(ByteMatrix matrix, boolean isHorizontal) { int penalty = 0; int numSameBitCells = 0; int prevBit = -1; // Horizontal mode: // for (int i = 0; i < matrix.height(); ++i) { // for (int j = 0; j < matrix.width(); ++j) { // int bit = matrix.get(i, j); // Vertical mode: // for (int i = 0; i < matrix.width(); ++i) { // for (int j = 0; j < matrix.height(); ++j) { // int bit = matrix.get(j, i); int iLimit = isHorizontal ? matrix.getHeight() : matrix.getWidth(); int jLimit = isHorizontal ? matrix.getWidth() : matrix.getHeight(); byte[][] array = matrix.getArray(); for (int i = 0; i < iLimit; ++i) { for (int j = 0; j < jLimit; ++j) { int bit = isHorizontal ? array[i][j] : array[j][i]; if (bit == prevBit) { numSameBitCells += 1; // Found five repetitive cells with the same color (bit). // We'll give penalty of 3. if (numSameBitCells == 5) { penalty += 3; } else if (numSameBitCells > 5) { // After five repetitive cells, we'll add the penalty one // by one. penalty += 1; } } else { // Include the cell itself. numSameBitCells = 1; prevBit = bit; } } // Clear at each row/column. numSameBitCells = 0; } return penalty; } } ```
```smalltalk #nullable enable using System; using System.Collections.Generic; using System.IO; using System.Linq; using System.Text; using Java.Interop.Tools.Diagnostics; using Microsoft.Android.Build.Tasks; using Microsoft.Build.Framework; using Xamarin.Android.Tools; namespace Xamarin.Android.Tasks { /// <summary> /// The <Aot/> task subclasses this in "legacy" Xamarin.Android. /// The <GetAotAssemblies/> task subclasses this in .NET 6+. /// </summary> public abstract class GetAotArguments : AsyncTask { [Required] public string AndroidApiLevel { get; set; } = ""; [Required] public string AndroidAotMode { get; set; } = ""; [Required] public string AotOutputDirectory { get; set; } = ""; [Required] public string AndroidBinUtilsDirectory { get; set; } = ""; [Required] public string TargetName { get; set; } = ""; /// <summary> /// Will be blank in .NET 6+ /// </summary> public string ManifestFile { get; set; } = ""; /// <summary> /// $(AndroidMinimumSupportedApiLevel) in .NET 6+ /// </summary> public string MinimumSupportedApiLevel { get; set; } = ""; public string RuntimeIdentifier { get; set; } = ""; public string AndroidNdkDirectory { get; set; } = ""; public bool EnableLLVM { get; set; } public bool StripLibraries { get; set; } public string AndroidSequencePointsMode { get; set; } = ""; public ITaskItem [] Profiles { get; set; } = Array.Empty<ITaskItem> (); public int ZipAlignmentPages { get; set; } = AndroidZipAlign.DefaultZipAlignment64Bit; [Required, Output] public ITaskItem [] ResolvedAssemblies { get; set; } = Array.Empty<ITaskItem> (); [Output] public string? Triple { get; set; } [Output] public string? ToolPrefix { get; set; } [Output] public string? MsymPath { get; set; } [Output] public string? LdName { get; set; } [Output] public string? LdFlags { get; set; } protected AotMode AotMode; protected SequencePointsMode SequencePointsMode; protected string SdkBinDirectory = ""; protected bool UseAndroidNdk => !string.IsNullOrWhiteSpace (AndroidNdkDirectory); public static bool GetAndroidAotMode(string androidAotMode, out AotMode aotMode) { aotMode = AotMode.Normal; switch ((androidAotMode ?? string.Empty).ToLowerInvariant().Trim()) { case "": case "none": aotMode = AotMode.None; return true; case "normal": aotMode = AotMode.Normal; return true; case "hybrid": aotMode = AotMode.Hybrid; return true; case "full": aotMode = AotMode.Full; return true; case "interpreter": // We don't do anything here for this mode, this is just to set the flag for the XA // runtime to initialize Mono in the interpreter "AOT" mode. aotMode = AotMode.Interp; return true; } return false; } public static bool TryGetSequencePointsMode (string value, out SequencePointsMode mode) { mode = SequencePointsMode.None; switch ((value ?? string.Empty).ToLowerInvariant ().Trim ()) { case "none": mode = SequencePointsMode.None; return true; case "normal": mode = SequencePointsMode.Normal; return true; case "offline": mode = SequencePointsMode.Offline; return true; } return false; } protected string GetToolPrefix (NdkTools ndk, AndroidTargetArch arch, out int level) { level = 0; return UseAndroidNdk ? ndk.GetNdkToolPrefixForAOT (arch, level = GetNdkApiLevel (ndk, arch)) : Path.Combine (AndroidBinUtilsDirectory, $"{ndk.GetArchDirName (arch)}-"); } int GetNdkApiLevel (NdkTools ndk, AndroidTargetArch arch) { AndroidAppManifest? manifest = null; if (!string.IsNullOrEmpty (ManifestFile)) { manifest = AndroidAppManifest.Load (ManifestFile, MonoAndroidHelper.SupportedVersions); } int level; if (manifest?.MinSdkVersion != null) { level = manifest.MinSdkVersion.Value; } else if (int.TryParse (MinimumSupportedApiLevel, out level)) { // level already set } else if (int.TryParse (AndroidApiLevel, out level)) { // level already set } else { // Probably not ideal! level = MonoAndroidHelper.SupportedVersions.MaxStableVersion.ApiLevel; } // Some Android API levels do not exist on the NDK level. Workaround this my mapping them to the // most appropriate API level that does exist. if (level == 6 || level == 7) level = 5; else if (level == 10) level = 9; else if (level == 11) level = 12; else if (level == 20) level = 19; else if (level == 22) level = 21; else if (level == 23) level = 21; // API levels below level 21 do not provide support for 64-bit architectures. if (ndk.IsNdk64BitArch (arch) && level < 21) { level = 21; } // We perform a downwards API level lookup search since we might not have hardcoded the correct API // mapping above and we do not want to crash needlessly. for (; level >= 5; level--) { try { ndk.GetDirectoryPath (NdkToolchainDir.PlatformLib, arch, level); break; } catch (InvalidOperationException ex) { // Path not found, continue searching... continue; } } return level; } protected (string aotCompiler, string outdir, string mtriple, AndroidTargetArch arch) GetAbiSettings (string abi) { switch (abi) { case "armeabi-v7a": return ( Path.Combine (SdkBinDirectory, "cross-arm"), Path.Combine (AotOutputDirectory, "armeabi-v7a"), "armv7-linux-gnueabi", AndroidTargetArch.Arm ); case "arm64": case "arm64-v8a": case "aarch64": return ( Path.Combine (SdkBinDirectory, "cross-arm64"), Path.Combine (AotOutputDirectory, "arm64-v8a"), "aarch64-linux-android", AndroidTargetArch.Arm64 ); case "x86": return ( Path.Combine (SdkBinDirectory, "cross-x86"), Path.Combine (AotOutputDirectory, "x86"), "i686-linux-android", AndroidTargetArch.X86 ); case "x86_64": return ( Path.Combine (SdkBinDirectory, "cross-x86_64"), Path.Combine (AotOutputDirectory, "x86_64"), "x86_64-linux-android", AndroidTargetArch.X86_64 ); // case "mips": default: throw new Exception ("Unsupported Android target architecture ABI: " + abi); } } /// <summary> /// Fills [Output] parameters to pass to the --aot switch /// </summary> protected void GetAotOptions (NdkTools ndk, AndroidTargetArch arch, int level, string outdir, string toolPrefix) { if (SequencePointsMode == SequencePointsMode.Offline) MsymPath = outdir; string ldName; if (UseAndroidNdk) { ldName = ndk.GetToolPath (NdkToolKind.Linker, arch, level); if (!string.IsNullOrEmpty (ldName)) { ldName = Path.GetFileName (ldName); if (ldName.IndexOf ('-') >= 0) { ldName = ldName.Substring (ldName.LastIndexOf ("-", StringComparison.Ordinal) + 1); } } } else { ldName = "ld"; } string ldFlags = GetLdFlags (ndk, arch, level, toolPrefix); if (!string.IsNullOrEmpty (ldName)) { LdName = ldName; } if (!string.IsNullOrEmpty (ldFlags)) { LdFlags = ldFlags; } } string GetLdFlags (NdkTools ndk, AndroidTargetArch arch, int level, string toolPrefix) { var toolchainPath = toolPrefix.Substring (0, toolPrefix.LastIndexOf (Path.DirectorySeparatorChar)); var ldFlags = new StringBuilder (); var libs = new List<string> (); if (UseAndroidNdk && EnableLLVM) { string androidLibPath = string.Empty; try { androidLibPath = ndk.GetDirectoryPath (NdkToolchainDir.PlatformLib, arch, level); } catch (InvalidOperationException ex) { Diagnostic.Error (5101, ex.Message); } string toolchainLibDir; if (ndk.UsesClang) { if (ndk.NoBinutils) { toolchainLibDir = String.Empty; } else { toolchainLibDir = GetNdkToolchainLibraryDir (ndk, toolchainPath, arch); } } else toolchainLibDir = GetNdkToolchainLibraryDir (ndk, toolchainPath); if (ndk.UsesClang) { if (!String.IsNullOrEmpty (toolchainLibDir)) { libs.Add ($"-L{toolchainLibDir.TrimEnd ('\\')}"); } libs.Add ($"-L{androidLibPath.TrimEnd ('\\')}"); if (arch == AndroidTargetArch.Arm) { // Needed for -lunwind to work string compilerLibDir = Path.Combine (toolchainPath, "..", "sysroot", "usr", "lib", ndk.GetArchDirName (arch)); libs.Add ($"-L{compilerLibDir.TrimEnd ('\\')}"); } } if (!String.IsNullOrEmpty (toolchainLibDir)) { libs.Add (Path.Combine (toolchainLibDir, "libgcc.a")); } libs.Add (Path.Combine (androidLibPath, "libc.so")); libs.Add (Path.Combine (androidLibPath, "libm.so")); } else if (!UseAndroidNdk && EnableLLVM) { string libstubsPath = MonoAndroidHelper.GetLibstubsArchDirectoryPath (AndroidBinUtilsDirectory, arch); libs.Add (Path.Combine (libstubsPath, "libc.so")); libs.Add (Path.Combine (libstubsPath, "libm.so")); } if (libs.Count > 0) { ldFlags.Append ($"\\\"{string.Join ("\\\";\\\"", libs)}\\\""); } // // This flag is needed for Mono AOT to work correctly with the LLVM 14 `lld` linker due to the following change: // // The AArch64 port now supports adrp+ldr and adrp+add optimizations. --no-relax can suppress the optimization. // // Without the flag, `lld` will modify AOT-generated code in a way that the Mono runtime doesn't support. Until // the runtime issue is fixed, we need to pass this flag then. // if (!UseAndroidNdk) { if (ldFlags.Length > 0) { ldFlags.Append (' '); } ldFlags.Append ("--no-relax"); } if (StripLibraries) { if (ldFlags.Length > 0) { ldFlags.Append (' '); } ldFlags.Append ("-s"); } uint maxPageSize; switch (arch) { case AndroidTargetArch.Arm64: case AndroidTargetArch.X86_64: maxPageSize = MonoAndroidHelper.ZipAlignmentToPageSize (ZipAlignmentPages); break; case AndroidTargetArch.Arm: case AndroidTargetArch.X86: maxPageSize = MonoAndroidHelper.ZipAlignmentToPageSize (AndroidZipAlign.ZipAlignment32Bit); break; default: throw new InvalidOperationException ($"Internal error: unsupported target architecture {arch}"); } if (ldFlags.Length > 0) { ldFlags.Append (' '); } ldFlags.Append ("-z "); ldFlags.Append ($"max-page-size={maxPageSize}"); return ldFlags.ToString (); } static string GetNdkToolchainLibraryDir (NdkTools ndk, string binDir, string archDir = null) { var baseDir = Path.GetFullPath (Path.Combine (binDir, "..")); string libDir = Path.Combine (baseDir, "lib", "gcc"); if (!String.IsNullOrEmpty (archDir)) libDir = Path.Combine (libDir, archDir); var gccLibDir = Directory.EnumerateDirectories (libDir).ToList (); gccLibDir.Sort (); var libPath = gccLibDir.LastOrDefault (); if (libPath == null) { goto no_toolchain_error; } if (ndk.UsesClang) return libPath; gccLibDir = Directory.EnumerateDirectories (libPath).ToList (); gccLibDir.Sort (); libPath = gccLibDir.LastOrDefault (); if (libPath == null) { goto no_toolchain_error; } return libPath; no_toolchain_error: throw new Exception ("Could not find a valid NDK compiler toolchain library path"); } static string GetNdkToolchainLibraryDir (NdkTools ndk, string binDir, AndroidTargetArch arch) { return GetNdkToolchainLibraryDir (ndk, binDir, ndk.GetArchDirName (arch)); } } } ```
Darodine is a town in the Bondigui Department of Bougouriba Province in south-western Burkina Faso. The town has a population of 1,318. References Populated places in the Sud-Ouest Region (Burkina Faso)
Kyle Alexander Lewis (born July 13, 1995) is an American professional baseball outfielder for the Arizona Diamondbacks of Major League Baseball (MLB). He has previously played in MLB for the Seattle Mariners. Prior to his MLB debut, he played college baseball for the Mercer Bears. For his 2016 performance at Mercer, Lewis was named an All-American, Baseball America's 2016 College Player of the Year, and won the 2016 Golden Spikes Award. He was selected in the first round of the 2016 Major League Baseball draft by the Seattle Mariners. Lewis made his major league debut in September 2019, and was unanimously selected as the 2020 American League Rookie of the Year. Amateur career Lewis attended Shiloh High School in Snellville, Georgia. He played both baseball and basketball in high school. He chose baseball over basketball and attended Mercer University, where he played college baseball for the Bears. As a freshman in 2014, he appeared in 42 games with 17 starts and hit .281/.340/.382 with two home runs and 17 runs batted in (RBI) over 89 at-bats. After his freshman season he played collegiate summer baseball in the Cape Cod Baseball League (CCBL) for the Cotuit Kettleers. As a sophomore in 2015, he played in 54 games, hitting .367/.423/.677 with 17 home runs and 56 RBI. He was the Southern Conference Baseball Player of the Year and was the co-winner of the Gregg Olson Award, bestowed upon college baseball's breakout player of the year. After the season, Lewis returned to the CCBL to play for the Orleans Firebirds and was named a league all-star. As a junior at Mercer, he hit .395/.535/.731 with 20 home runs and 72 RBI, and was named an All-American by Louisville Slugger, Baseball America, the American Baseball Coaches Association, and Collegiate Baseball. Following that season, Lewis received the 2016 Golden Spikes Award, which is awarded annually to the best amateur baseball player in the United States. In addition, he was the Southern Conference Baseball Player of the Year for the second straight year and was named both Baseball Americas College Player of the Year and the American Baseball Coaches Association's Division I National Player of the Year. Professional career Minor Leagues The Seattle Mariners selected Lewis with the 11th overall pick in the 2016 Major League Baseball draft. He made his professional debut with the Everett AquaSox. Lewis only played 30 games for the Everett AquaSox due to a right ACL injury, batting .299 with three home runs and 26 RBIs. He spent 2017 with both the AZL Mariners and the Modesto Nuts, posting a combined .257 average with seven home runs and 31 RBIs in 49 games between both clubs, and 2018 with Modesto and the Arkansas Travelers, batting .244 with nine home runs and 52 RBIs in 86 games with the two teams. Lewis returned to Arkansas for the 2019 season, hitting .263/.343/.398/.741 with 11 home runs and 62 RBI over 122 games. Seattle Mariners The Mariners selected Lewis' contract and promoted him to the major leagues on September 10, 2019. Lewis hit a home run off Trevor Bauer in his major league debut that night versus the Cincinnati Reds. He hit home runs in each of his next two games as well, becoming the second player in history, after Trevor Story, to homer in each of his first three major league games. He finished the 2019 season with a .268/.293/.592 slash line along with 6 home runs and 13 RBIs in 71 at bats. In 2020, Lewis became the first Mariners player to be selected for the American League Rookie of the Year award since 2001, finishing the abbreviated season with a .262/.364/.437 slash line, 11 home runs, and 28 RBIs across 206 at bats. He was awarded the title of American League Rookie of the Year by numerous other publications, including Sporting News. On June 1, 2021, Lewis was placed on the injured list after suffering a right meniscus tear. He was placed on the 60-day injured list on June 18 and subsequently missed the rest of the season. Lewis went into MLB's concussion protocol after having been hit by a pitch on May 29, 2022. He returned to the active roster on July 22. After continuing to struggle at the plate, and still dealing with issues related to his knee, Lewis was demoted to the Triple-A Tacoma Rainiers, where he ended the 2022 season. Arizona Diamondbacks On November 17, 2022, the Mariners traded Lewis to the Arizona Diamondbacks for Cooper Hummel. On January 13, 2023, Lewis agreed to a one-year, $1.61 million contract with the Diamondbacks, avoiding salary arbitration. References External links Mercer Bears bio 1995 births Living people African-American baseball players All-American college baseball players Arizona Diamondbacks players Arizona League Mariners players Arkansas Travelers players Baseball players from Gwinnett County, Georgia Cotuit Kettleers players Everett AquaSox players Major League Baseball Rookie of the Year Award winners Major League Baseball outfielders Mercer Bears baseball players Modesto Nuts players Orleans Firebirds players Peoria Javelinas players Reno Aces players Seattle Mariners players Sportspeople from Snellville, Georgia Tacoma Rainiers players 21st-century African-American sportspeople
Carl Stefan Ridderwall (born 5 March 1988) is a Swedish former professional ice hockey goaltender. He last played with EC Kitzbühel of the Alps Hockey League (AlpsHL). Playing career He began his career in the 2003–04 season with Huddinge IK in the J18 Allsvenskan. The following season he joined league rival Djurgårdens IF. During the winter 2005 he was promoted to Djurgården's J20 team in J20 SuperElit. Ridderwall made his Elitserien debut the following season, but only played one game during the 2005–06 season. Ridderwall was drafted in the sixth round of the 2006 NHL Entry Draft, 173rd overall, by the New York Islanders. Ridderwall did not play in Elitserien during the 2006–07 season, and spent the season playing in Djurgården's J20 team. The following season, Ridderwall was Djurgården's second goaltender behind Daniel Larsson, and played 11 games in Elitserien. He also spent some time on loan to Allsvenskan teams IK Nyköpings NH 90 and Almtuna IS. During the 2008–09 season, Ridderwall became the first choice goaltender in the senior team, and played 27 games out of 55 during the regular season. For the 2009–10 season, Ridderwall shares the first choice position with Gustaf Wesslau. In the 2013–14 season, Ridderwall signed for his first venture abroad, agreeing to a one-year deal with Düsseldorfer EG in the Deutsche Eishockey Liga. He is the son of former goaltender Rolf Ridderwall. Ridderwall has been awarded "goaltender of the tournament" twice on the national junior tournament TV-pucken. References External links 1988 births Living people Almtuna IS players Djurgårdens IF Hockey players Düsseldorfer EG players Heilbronner Falken players Huddinge IK players New York Islanders draft picks Nyköpings Hockey players Örebro HK players IK Oskarshamn players Ice hockey people from Stockholm Rødovre Mighty Bulls players Rögle BK players Swedish ice hockey goaltenders Timrå IK players
```prolog #! /usr/bin/env perl -w use 5.10.0; use strict; use FindBin; use lib "$FindBin::Bin/../openssl/"; use lib "$FindBin::Bin/../openssl/util/perl"; use File::Basename; use File::Spec::Functions qw/:DEFAULT abs2rel rel2abs/; use File::Copy; use File::Path qw/make_path/; use with_fallback qw(Text::Template); # Read configdata from ../openssl/configdata.pm that is generated # with ../openssl/Configure options arch use configdata; my $asm = $ARGV[0]; unless ($asm eq "asm" or $asm eq "no-asm") { die "Error: $asm is invalid argument"; } my $arch = $ARGV[1]; # nasm version check my $nasm_banner = `nasm -v`; die "Error: nasm is not installed." if (!$nasm_banner); my $nasm_version_min = 2.11; my ($nasm_version) = ($nasm_banner =~/^NASM version ([0-9]\.[0-9][0-9])+/); if ($nasm_version < $nasm_version_min) { die "Error: nasm version $nasm_version is too old." . "$nasm_version_min or higher is required."; } # gas version check my $gas_version_min = 2.26; my $gas_banner = `gcc -Wa,-v -c -o /dev/null -x assembler /dev/null 2>&1`; my ($gas_version) = ($gas_banner =~/GNU assembler version ([2-9]\.[0-9]+)/); if ($gas_version < $gas_version_min) { die "Error: gas version $gas_version is too old." . "$gas_version_min or higher is required."; } my $src_dir = "../openssl"; my $arch_dir = "../config/archs/$arch"; my $base_dir = "$arch_dir/$asm"; my $is_win = ($arch =~/^VC-WIN/); # VC-WIN32 and VC-WIN64A generate makefile but it can be available # with only nmake. Use pre-created Makefile_VC_WIN32 # Makefile_VC-WIN64A instead. my $makefile = $is_win ? "../config/Makefile_$arch": "Makefile"; # Generate arch dependent header files with Makefile my $buildinf = "crypto/buildinf.h"; my $progs = "apps/progs.h"; my $cmd1 = "cd ../openssl; make -f $makefile build_generated $buildinf $progs;"; system($cmd1) == 0 or die "Error in system($cmd1)"; # Copy and move all arch dependent header files into config/archs make_path("$base_dir/crypto/include/internal", "$base_dir/include/openssl", { error => \my $make_path_err}); if (@$make_path_err) { for my $diag (@$make_path_err) { my ($file, $message) = %$diag; die "make_path error: $file $message\n"; } } copy("$src_dir/configdata.pm", "$base_dir/") or die "Copy failed: $!"; copy("$src_dir/include/openssl/opensslconf.h", "$base_dir/include/openssl/") or die "Copy failed: $!"; move("$src_dir/crypto/include/internal/bn_conf.h", "$base_dir/crypto/include/internal/") or die "Move failed: $!"; move("$src_dir/crypto/include/internal/dso_conf.h", "$base_dir/crypto/include/internal/") or die "Move failed: $!"; copy("$src_dir/$buildinf", "$base_dir/crypto/") or die "Copy failed: $!"; move("$src_dir/$progs", "$base_dir/include") or die "Copy failed: $!"; # read openssl source lists from configdata.pm my @libapps_srcs = (); foreach my $obj (@{$unified_info{sources}->{'apps/libapps.a'}}) { push(@libapps_srcs, ${$unified_info{sources}->{$obj}}[0]); } my @libssl_srcs = (); foreach my $obj (@{$unified_info{sources}->{libssl}}) { push(@libssl_srcs, ${$unified_info{sources}->{$obj}}[0]); } my @libcrypto_srcs = (); my @generated_srcs = (); foreach my $obj (@{$unified_info{sources}->{libcrypto}}) { my $src = ${$unified_info{sources}->{$obj}}[0]; # .S files should be preprocessed into .s if ($unified_info{generate}->{$src}) { # .S or .s files should be preprocessed into .asm for WIN $src =~ s\.[sS]$\.asm\ if ($is_win); push(@generated_srcs, $src); } else { push(@libcrypto_srcs, $src); } } my @apps_openssl_srcs = (); foreach my $obj (@{$unified_info{sources}->{'apps/openssl'}}) { push(@apps_openssl_srcs, ${$unified_info{sources}->{$obj}}[0]); } # Generate all asm files and copy into config/archs foreach my $src (@generated_srcs) { my $cmd = "cd ../openssl; CC=gcc ASM=nasm make -f $makefile $src;" . "cp --parents $src ../config/archs/$arch/$asm; cd ../config"; system("$cmd") == 0 or die "Error in system($cmd)"; } # Create openssl.gypi my $template = Text::Template->new(TYPE => 'FILE', SOURCE => 'openssl.gypi.tmpl', DELIMITERS => [ "%%-", "-%%" ] ); my $gypi = $template->fill_in( HASH => { libssl_srcs => \@libssl_srcs, libcrypto_srcs => \@libcrypto_srcs, generated_srcs => \@generated_srcs, config => \%config, target => \%target, asm => \$asm, arch => \$arch, is_win => \$is_win, }); open(GYPI, "> ./archs/$arch/$asm/openssl.gypi"); print GYPI "$gypi"; close(GYPI); # Create openssl-cl.gypi my $cltemplate = Text::Template->new(TYPE => 'FILE', SOURCE => 'openssl-cl.gypi.tmpl', DELIMITERS => [ "%%-", "-%%" ] ); my $clgypi = $cltemplate->fill_in( HASH => { apps_openssl_srcs => \@apps_openssl_srcs, libapps_srcs => \@libapps_srcs, config => \%config, target => \%target, arch => \$arch, is_win => \$is_win, }); open(CLGYPI, "> ./archs/$arch/$asm/openssl-cl.gypi"); print CLGYPI "$clgypi"; close(CLGYPI); # Clean Up my $cmd2 ="cd $src_dir; make -f $makefile clean; make -f $makefile distclean;" . "git clean -f $src_dir/crypto"; system($cmd2) == 0 or die "Error in system($cmd2)"; ```
```go /* path_to_url Unless required by applicable law or agreed to in writing, software WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. */ // Code generated by applyconfiguration-gen. DO NOT EDIT. package v1 // ResourceClaimApplyConfiguration represents an declarative configuration of the ResourceClaim type for use // with apply. type ResourceClaimApplyConfiguration struct { Name *string `json:"name,omitempty"` } // ResourceClaimApplyConfiguration constructs an declarative configuration of the ResourceClaim type for use with // apply. func ResourceClaim() *ResourceClaimApplyConfiguration { return &ResourceClaimApplyConfiguration{} } // WithName sets the Name field in the declarative configuration to the given value // and returns the receiver, so that objects can be built by chaining "With" function invocations. // If called multiple times, the Name field is set to the value of the last call. func (b *ResourceClaimApplyConfiguration) WithName(value string) *ResourceClaimApplyConfiguration { b.Name = &value return b } ```
```c /* * */ #include "w1_ds2482_84_common.h" #include <zephyr/devicetree.h> #include <zephyr/drivers/gpio.h> #include <zephyr/drivers/i2c.h> #include <zephyr/drivers/w1.h> #include <zephyr/kernel.h> #include <zephyr/logging/log.h> #include <zephyr/pm/device.h> #define DT_DRV_COMPAT maxim_ds2484 LOG_MODULE_REGISTER(ds2484, CONFIG_W1_LOG_LEVEL); struct ds2484_config { struct w1_master_config w1_config; const struct i2c_dt_spec i2c_spec; const struct gpio_dt_spec slpz_spec; bool apu; }; struct ds2484_data { struct w1_master_data w1_data; uint8_t reg_device_config; }; static int ds2484_reset_bus(const struct device *dev) { const struct ds2484_config *config = dev->config; return ds2482_84_reset_bus(&config->i2c_spec); } static int ds2484_read_bit(const struct device *dev) { const struct ds2484_config *config = dev->config; return ds2482_84_read_bit(&config->i2c_spec); } static int ds2484_write_bit(const struct device *dev, bool bit) { const struct ds2484_config *config = dev->config; return ds2482_84_write_bit(&config->i2c_spec, bit); } static int ds2484_read_byte(const struct device *dev) { const struct ds2484_config *config = dev->config; return ds2482_84_read_byte(&config->i2c_spec); } static int ds2484_write_byte(const struct device *dev, uint8_t byte) { const struct ds2484_config *config = dev->config; return ds2482_84_write_byte(&config->i2c_spec, byte); } static int ds2484_configure(const struct device *dev, enum w1_settings_type type, uint32_t value) { const struct ds2484_config *config = dev->config; struct ds2484_data *data = dev->data; switch (type) { case W1_SETTING_SPEED: WRITE_BIT(data->reg_device_config, DEVICE_1WS_pos, value); break; case W1_SETTING_STRONG_PULLUP: WRITE_BIT(data->reg_device_config, DEVICE_SPU_pos, value); break; default: return -EINVAL; } return ds2482_84_write_config(&config->i2c_spec, data->reg_device_config); } #ifdef CONFIG_PM_DEVICE static int ds2484_pm_control(const struct device *dev, enum pm_device_action action) { const struct ds2484_config *config = dev->config; switch (action) { case PM_DEVICE_ACTION_SUSPEND: if (!config->slpz_spec.port) { return -ENOTSUP; } return gpio_pin_set_dt(&config->slpz_spec, 1); case PM_DEVICE_ACTION_RESUME: if (!config->slpz_spec.port) { return -ENOTSUP; } return gpio_pin_set_dt(&config->slpz_spec, 0); default: return -ENOTSUP; }; return 0; } #endif /* CONFIG_PM_DEVICE */ static int ds2484_init(const struct device *dev) { int ret; const struct ds2484_config *config = dev->config; struct ds2484_data *data = dev->data; if (config->slpz_spec.port) { if (!gpio_is_ready_dt(&config->slpz_spec)) { LOG_ERR("Port (SLPZ) not ready"); return -ENODEV; } ret = gpio_pin_configure_dt(&config->slpz_spec, GPIO_OUTPUT_INACTIVE); if (ret < 0) { LOG_ERR("Pin configuration (SLPZ) failed: %d", ret); return ret; } } if (!device_is_ready(config->i2c_spec.bus)) { return -ENODEV; } ret = ds2482_84_reset_device(&config->i2c_spec); if (ret < 0) { LOG_ERR("Device reset failed: %d", ret); return ret; } WRITE_BIT(data->reg_device_config, DEVICE_APU_pos, config->apu); ret = ds2482_84_write_config(&config->i2c_spec, data->reg_device_config); if (ret < 0) { LOG_ERR("Device config update failed: %d", ret); return ret; } return 0; } static const struct w1_driver_api ds2484_driver_api = { .reset_bus = ds2484_reset_bus, .read_bit = ds2484_read_bit, .write_bit = ds2484_write_bit, .read_byte = ds2484_read_byte, .write_byte = ds2484_write_byte, .configure = ds2484_configure, }; #define DS2484_INIT(inst) \ static const struct ds2484_config inst_##inst##_config = { \ .w1_config.slave_count = W1_INST_SLAVE_COUNT(inst), \ .i2c_spec = I2C_DT_SPEC_INST_GET(inst), \ .slpz_spec = GPIO_DT_SPEC_INST_GET_OR(inst, slpz_gpios, {0}), \ .apu = DT_INST_PROP(inst, active_pullup), \ }; \ static struct ds2484_data inst_##inst##_data; \ PM_DEVICE_DT_INST_DEFINE(inst, ds2484_pm_control); \ DEVICE_DT_INST_DEFINE(inst, ds2484_init, PM_DEVICE_DT_INST_GET(inst), &inst_##inst##_data, \ &inst_##inst##_config, POST_KERNEL, CONFIG_W1_INIT_PRIORITY, \ &ds2484_driver_api); DT_INST_FOREACH_STATUS_OKAY(DS2484_INIT) /* * Make sure that this driver is not initialized before the i2c bus is available */ BUILD_ASSERT(CONFIG_W1_INIT_PRIORITY > CONFIG_I2C_INIT_PRIORITY); ```
```smalltalk using NUnit.Framework; using Microsoft.AspNetCore.Mvc.Testing; using System.Net; public class Tests { private WebApplicationFactory<Startup> _factory; private HttpClient _client; [OneTimeSetUp] public void OneTimeSetUp() { _factory = new WebApplicationFactory<Startup>(); } [SetUp] public void Setup() { _client = _factory.CreateClient(); } [Test] public async Task ReturnsTextStartingWithHelloWorld() { var result = await _client.GetStringAsync("/"); Assert.That(result, Does.StartWith("Hello world")); } [Test] public async Task Returns200() { using var request = new HttpRequestMessage(HttpMethod.Get, "/"); using var response = await _client.SendAsync(request); Assert.That(response.StatusCode, Is.EqualTo(HttpStatusCode.OK)); } } ```
```objective-c /* * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * * THIS SOFTWARE IS PROVIDED BY APPLE INC. AND ITS CONTRIBUTORS ``AS IS'' * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL APPLE INC. OR ITS CONTRIBUTORS * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF * THE POSSIBILITY OF SUCH DAMAGE. */ #ifndef IntRect_h #define IntRect_h #include "platform/geometry/IntPoint.h" #include "wtf/FastAllocBase.h" #include "wtf/Vector.h" #include "wtf/VectorTraits.h" #if OS(MACOSX) typedef struct CGRect CGRect; #ifdef __OBJC__ #import <Foundation/Foundation.h> #endif #endif struct SkRect; struct SkIRect; namespace blink { class FloatRect; class LayoutRect; class PLATFORM_EXPORT IntRect { WTF_MAKE_FAST_ALLOCATED(IntRect); public: IntRect() { } IntRect(const IntPoint& location, const IntSize& size) : m_location(location), m_size(size) { } IntRect(int x, int y, int width, int height) : m_location(IntPoint(x, y)), m_size(IntSize(width, height)) { } explicit IntRect(const FloatRect&); // don't do this implicitly since it's lossy explicit IntRect(const LayoutRect&); // don't do this implicitly since it's lossy IntPoint location() const { return m_location; } IntSize size() const { return m_size; } void setLocation(const IntPoint& location) { m_location = location; } void setSize(const IntSize& size) { m_size = size; } int x() const { return m_location.x(); } int y() const { return m_location.y(); } int maxX() const { return x() + width(); } int maxY() const { return y() + height(); } int width() const { return m_size.width(); } int height() const { return m_size.height(); } void setX(int x) { m_location.setX(x); } void setY(int y) { m_location.setY(y); } void setWidth(int width) { m_size.setWidth(width); } void setHeight(int height) { m_size.setHeight(height); } bool isEmpty() const { return m_size.isEmpty(); } // NOTE: The result is rounded to integer values, and thus may be not the exact // center point. IntPoint center() const { return IntPoint(x() + width() / 2, y() + height() / 2); } void move(const IntSize& size) { m_location += size; } void moveBy(const IntPoint& offset) { m_location.move(offset.x(), offset.y()); } void move(int dx, int dy) { m_location.move(dx, dy); } void expand(const IntSize& size) { m_size += size; } void expand(int dw, int dh) { m_size.expand(dw, dh); } void contract(const IntSize& size) { m_size -= size; } void contract(int dw, int dh) { m_size.expand(-dw, -dh); } void shiftXEdgeTo(int edge) { int delta = edge - x(); setX(edge); setWidth(std::max(0, width() - delta)); } void shiftMaxXEdgeTo(int edge) { int delta = edge - maxX(); setWidth(std::max(0, width() + delta)); } void shiftYEdgeTo(int edge) { int delta = edge - y(); setY(edge); setHeight(std::max(0, height() - delta)); } void shiftMaxYEdgeTo(int edge) { int delta = edge - maxY(); setHeight(std::max(0, height() + delta)); } IntPoint minXMinYCorner() const { return m_location; } // typically topLeft IntPoint maxXMinYCorner() const { return IntPoint(m_location.x() + m_size.width(), m_location.y()); } // typically topRight IntPoint minXMaxYCorner() const { return IntPoint(m_location.x(), m_location.y() + m_size.height()); } // typically bottomLeft IntPoint maxXMaxYCorner() const { return IntPoint(m_location.x() + m_size.width(), m_location.y() + m_size.height()); } // typically bottomRight bool intersects(const IntRect&) const; bool contains(const IntRect&) const; // This checks to see if the rect contains x,y in the traditional sense. // Equivalent to checking if the rect contains a 1x1 rect below and to the right of (px,py). bool contains(int px, int py) const { return px >= x() && px < maxX() && py >= y() && py < maxY(); } bool contains(const IntPoint& point) const { return contains(point.x(), point.y()); } void intersect(const IntRect&); void unite(const IntRect&); void uniteIfNonZero(const IntRect&); void inflateX(int dx) { m_location.setX(m_location.x() - dx); m_size.setWidth(m_size.width() + dx + dx); } void inflateY(int dy) { m_location.setY(m_location.y() - dy); m_size.setHeight(m_size.height() + dy + dy); } void inflate(int d) { inflateX(d); inflateY(d); } void scale(float s); IntSize differenceToPoint(const IntPoint&) const; int distanceSquaredToPoint(const IntPoint& p) const { return differenceToPoint(p).diagonalLengthSquared(); } IntRect transposedRect() const { return IntRect(m_location.transposedPoint(), m_size.transposedSize()); } #if OS(MACOSX) operator CGRect() const; #if defined(__OBJC__) && !defined(NSGEOMETRY_TYPES_SAME_AS_CGGEOMETRY_TYPES) operator NSRect() const; #endif #endif operator SkRect() const; operator SkIRect() const; #ifndef NDEBUG // Prints the rect to the screen. void show() const; #endif private: IntPoint m_location; IntSize m_size; }; inline IntRect intersection(const IntRect& a, const IntRect& b) { IntRect c = a; c.intersect(b); return c; } inline IntRect unionRect(const IntRect& a, const IntRect& b) { IntRect c = a; c.unite(b); return c; } PLATFORM_EXPORT IntRect unionRect(const Vector<IntRect>&); inline bool operator==(const IntRect& a, const IntRect& b) { return a.location() == b.location() && a.size() == b.size(); } inline bool operator!=(const IntRect& a, const IntRect& b) { return a.location() != b.location() || a.size() != b.size(); } #if OS(MACOSX) PLATFORM_EXPORT IntRect enclosingIntRect(const CGRect&); #if defined(__OBJC__) && !defined(NSGEOMETRY_TYPES_SAME_AS_CGGEOMETRY_TYPES) PLATFORM_EXPORT IntRect enclosingIntRect(const NSRect&); #endif #endif } // namespace blink WTF_ALLOW_MOVE_INIT_AND_COMPARE_WITH_MEM_FUNCTIONS(blink::IntRect); #endif // IntRect_h ```
```php <?php /* * * ____ _ _ __ __ _ __ __ ____ * | _ \ ___ ___| | _____| |_| \/ (_)_ __ ___ | \/ | _ \ * | |_) / _ \ / __| |/ / _ \ __| |\/| | | '_ \ / _ \_____| |\/| | |_) | * | __/ (_) | (__| < __/ |_| | | | | | | | __/_____| | | | __/ * |_| \___/ \___|_|\_\___|\__|_| |_|_|_| |_|\___| |_| |_|_| * * This program is free software: you can redistribute it and/or modify * (at your option) any later version. * * @author PocketMine Team * @link path_to_url * * */ declare(strict_types=1); namespace pocketmine\event\entity; use pocketmine\entity\Entity; use pocketmine\event\Cancellable; use pocketmine\event\CancellableTrait; use function array_sum; use function max; /** * Called when an entity takes damage. * @phpstan-extends EntityEvent<Entity> */ class EntityDamageEvent extends EntityEvent implements Cancellable{ use CancellableTrait; public const MODIFIER_ARMOR = 1; public const MODIFIER_STRENGTH = 2; public const MODIFIER_WEAKNESS = 3; public const MODIFIER_RESISTANCE = 4; public const MODIFIER_ABSORPTION = 5; public const MODIFIER_ARMOR_ENCHANTMENTS = 6; public const MODIFIER_CRITICAL = 7; public const MODIFIER_TOTEM = 8; public const MODIFIER_WEAPON_ENCHANTMENTS = 9; public const MODIFIER_PREVIOUS_DAMAGE_COOLDOWN = 10; public const MODIFIER_ARMOR_HELMET = 11; public const CAUSE_CONTACT = 0; public const CAUSE_ENTITY_ATTACK = 1; public const CAUSE_PROJECTILE = 2; public const CAUSE_SUFFOCATION = 3; public const CAUSE_FALL = 4; public const CAUSE_FIRE = 5; public const CAUSE_FIRE_TICK = 6; public const CAUSE_LAVA = 7; public const CAUSE_DROWNING = 8; public const CAUSE_BLOCK_EXPLOSION = 9; public const CAUSE_ENTITY_EXPLOSION = 10; public const CAUSE_VOID = 11; public const CAUSE_SUICIDE = 12; public const CAUSE_MAGIC = 13; public const CAUSE_CUSTOM = 14; public const CAUSE_STARVATION = 15; public const CAUSE_FALLING_BLOCK = 16; private float $baseDamage; private float $originalBase; /** @var float[] */ private array $originals; private int $attackCooldown = 10; /** * @param float[] $modifiers */ public function __construct( Entity $entity, private int $cause, float $damage, private array $modifiers = [] ){ $this->entity = $entity; $this->baseDamage = $this->originalBase = $damage; $this->originals = $modifiers; } public function getCause() : int{ return $this->cause; } /** * Returns the base amount of damage applied, before modifiers. */ public function getBaseDamage() : float{ return $this->baseDamage; } /** * Sets the base amount of damage applied, optionally recalculating modifiers. * * TODO: add ability to recalculate modifiers when this is set */ public function setBaseDamage(float $damage) : void{ $this->baseDamage = $damage; } /** * Returns the original base amount of damage applied, before alterations by plugins. */ public function getOriginalBaseDamage() : float{ return $this->originalBase; } /** * @return float[] */ public function getOriginalModifiers() : array{ return $this->originals; } public function getOriginalModifier(int $type) : float{ return $this->originals[$type] ?? 0.0; } /** * @return float[] */ public function getModifiers() : array{ return $this->modifiers; } public function getModifier(int $type) : float{ return $this->modifiers[$type] ?? 0.0; } public function setModifier(float $damage, int $type) : void{ $this->modifiers[$type] = $damage; } public function isApplicable(int $type) : bool{ return isset($this->modifiers[$type]); } public function getFinalDamage() : float{ return max(0, $this->baseDamage + array_sum($this->modifiers)); } /** * Returns whether an entity can use armour points to reduce this type of damage. */ public function canBeReducedByArmor() : bool{ switch($this->cause){ case self::CAUSE_FIRE_TICK: case self::CAUSE_SUFFOCATION: case self::CAUSE_DROWNING: case self::CAUSE_STARVATION: case self::CAUSE_FALL: case self::CAUSE_VOID: case self::CAUSE_MAGIC: case self::CAUSE_SUICIDE: return false; } return true; } /** * Returns the cooldown in ticks before the target entity can be attacked again. */ public function getAttackCooldown() : int{ return $this->attackCooldown; } /** * Sets the cooldown in ticks before the target entity can be attacked again. * * NOTE: This value is not used in non-Living entities */ public function setAttackCooldown(int $attackCooldown) : void{ $this->attackCooldown = $attackCooldown; } } ```
```smalltalk using System; using System.Threading.Tasks; namespace CSharpFunctionalExtensions { public static partial class AsyncResultExtensionsBothOperands { public static Task<Result<T>> CheckIf<T>(this Task<Result<T>> resultTask, bool condition, Func<T, Task<Result>> func) { if (condition) return resultTask.Check(func); else return resultTask; } public static Task<Result<T>> CheckIf<T, K>(this Task<Result<T>> resultTask, bool condition, Func<T, Task<Result<K>>> func) { if (condition) return resultTask.Check(func); else return resultTask; } public static Task<Result<T, E>> CheckIf<T, K, E>(this Task<Result<T, E>> resultTask, bool condition, Func<T, Task<Result<K, E>>> func) { if (condition) return resultTask.Check(func); else return resultTask; } public static Task<Result<T, E>> CheckIf<T, E>(this Task<Result<T, E>> resultTask, bool condition, Func<T, Task<UnitResult<E>>> func) { if (condition) return resultTask.Check(func); else return resultTask; } public static Task<UnitResult<E>> CheckIf<E>(this Task<UnitResult<E>> resultTask, bool condition, Func<Task<UnitResult<E>>> func) { if (condition) return resultTask.Check(func); else return resultTask; } public static async Task<Result<T>> CheckIf<T>(this Task<Result<T>> resultTask, Func<T, bool> predicate, Func<T, Task<Result>> func) { Result<T> result = await resultTask.DefaultAwait(); if (result.IsSuccess && predicate(result.Value)) return await result.Check(func).DefaultAwait(); else return result; } public static async Task<Result<T>> CheckIf<T, K>(this Task<Result<T>> resultTask, Func<T, bool> predicate, Func<T, Task<Result<K>>> func) { Result<T> result = await resultTask.DefaultAwait(); if (result.IsSuccess && predicate(result.Value)) return await result.Check(func).DefaultAwait(); else return result; } public static async Task<Result<T, E>> CheckIf<T, K, E>(this Task<Result<T, E>> resultTask, Func<T, bool> predicate, Func<T, Task<Result<K, E>>> func) { Result<T, E> result = await resultTask.DefaultAwait(); if (result.IsSuccess && predicate(result.Value)) return await result.Check(func).DefaultAwait(); else return result; } public static async Task<Result<T, E>> CheckIf<T, E>(this Task<Result<T, E>> resultTask, Func<T, bool> predicate, Func<T, Task<UnitResult<E>>> func) { Result<T, E> result = await resultTask.DefaultAwait(); if (result.IsSuccess && predicate(result.Value)) return await result.Check(func).DefaultAwait(); else return result; } public static async Task<UnitResult<E>> CheckIf<E>(this Task<UnitResult<E>> resultTask, Func<bool> predicate, Func<Task<UnitResult<E>>> func) { UnitResult<E> result = await resultTask.DefaultAwait(); if (result.IsSuccess && predicate()) return await result.Check(func).DefaultAwait(); else return result; } } } ```
Bromochlorofluoromethane or fluorochlorobromomethane, is a chemical compound and trihalomethane derivative with the chemical formula CHBrClF. As one of the simplest possible stable chiral compounds, it is useful for fundamental research into this area of chemistry. However, its relative instability to hydrolysis, and lack of suitable functional groups, made separation of the enantiomers of bromochlorofluoromethane especially challenging, and this was not accomplished until almost a century after it was first synthesised, in March 2005, though it has now been done by a variety of methods. More recent research using bromochlorofluoromethane has focused on its potential use for experimental measurement of parity violation, a major unsolved problem in quantum physics. See also Bromochlorodifluoromethane, used in fire extinguishers Bromochlorofluoroiodomethane, a theoretical derivative with iodine replacing the hydrogen References Halomethanes Chirality
```swift import ExpoModulesCore internal class BackgroundFetchDisabled: Exception { override var reason: String { "Background Fetch has not been configured. To enable it, add `fetch` to `UIBackgroundModes` in the application's Info.plist file" } } internal class TaskManagerNotFound: Exception { override var reason: String { "TaskManager not found. Are you sure that Expo modules are properly linked?" } } ```
Thomas Neely Carruthers (June 10, 1900 – June 12, 1960) was bishop of the Episcopal Diocese of South Carolina, serving from 1944 to 1960. Early life and education Carruthers was born on June 10, 1900, in Collierville, Tennessee, the son of Thomas Neely Carruthers and Linnie Louise Hunter. He was educated at the Collierville High School, before studying at Sewanee: The University of the South, from where he graduated with a Bachelor of Arts in 1921. He then earned a Master of Arts from Princeton University in 1924. He married Ellen Douglas Everett on December 27, 1927. Carruthers also graduated with a Bachelor of Divinity from the University of the South in 1929, which also honoured him with a Doctor of Divinity in 1940. Ordained ministry Carruthers was ordained deacon in June 1925 by Bishop James M. Maxon Coadjutor of Tennessee and priest in May 1926 by Bishop Thomas F. Gailor of Tennessee. He then became rector of St Peter's Church in Columbia, Tennessee in 1926. He became rector of Trinity Church in Houston, Texas in 1931, and then rector of Christ Church in Nashville, Tennessee in 1939. Episcopacy On January 18, 1944, Carruthers was elected on the third ballot as Bishop of South Carolina during a special convention which was held in St John's Church in Florence, South Carolina. He was consecrated on May 4, 1944, in St Philip's Church in Charleston, South Carolina, by Presiding Bishop Henry St. George Tucker. From 1953 till 1956, he served as President of Province IV. At the time of his death, he was also Chancellor of the University of the South. Death He died in office on June 12, 1960, in Seabrook Island, South Carolina. He was found dead on the floor of his room, the death being the result of an Intracerebral hemorrhage. His funeral was held at St Philip's Church on June 14 and he was buried in the cemetery of the University of the South. References External links Obituary and funeral notices Finding Aid for papers 1900 births 1960 deaths Episcopal bishops of South Carolina People from Collierville, Tennessee Sewanee: The University of the South alumni 20th-century American Episcopalians 20th-century American clergy
The Pourvoyeuse was a 40-gun frigate of the French Navy, lead ship of her class. She is notable as one of the earliest attempts at building a frigate armed with 24-pounders on the artillery deck, rather than the 18-pounders typical of the day. Career Launched at Lorient in November 1772, Pourvoyeuse was completed during the following year. During the American Revolutionary War, she took part in the Indian campaign of the naval operations, notable in the Siege of Pondicherry. At the outbreak of the war, Pourvoyeuse, under Captain Saint-Orens, constituted the brunt of the French naval forces at Pondicherry, along with the 64-gun , under Captain François-Jean-Baptiste l'Ollivier de Tronjoli, whose departure for France had been delayed in response to the British preparations for war. On 21 February 1779, under Captain de Tromelin, she captured the East Indiaman . On 1 November 1781, Lieutenant Morard de Galles was given command of Pourvoyeuse. After Thomas d'Estienne d'Orves died on 9 February 1782 and he assumed command of the French forces in the Indian Ocean, Suffren gave Morard de Galles command of the 50-gun Petit Hannibal, putting Lieutenant de Ruyter in charge Pourvoyeuse. In March 1781, Pourvoyeuse escorted transports bound for the neutral Danish harbour of Trinquebar. The convoy sustained an attack from the British, and the transport Bons-Amis, under Captain Granières, managed to repel . Pourvoyeuse failed to intervene, and Suffren replaced Lieutenant De Ruyter with Lannuguy-Tromelin. In early July 1782, during the run-up of the Battle of Negapatam, Suffren sent Pourvoyeuse to Malacca to purchase spare spars, food and ammunition to resupply his fleet. After the battle, Pourvoyeuse had to provide her entire main mast to Brillant and exchange it for that of the fluyt . In late 1782, Pourvoyeuse cruised in the Strait of Malacca under Captain de Lannuguy-Tromelin. On 9 September, she encountered the East Indiamen Asia, Essex, , and , and the country ship Shah Byram Gore. The next day the action of 10 September 1782 ensued, an inconclusive two-and-a-half hour battle after which Pourvoyeuse withdrew. She had suffered four men killed and several wounded. After Pourvoyeuse withdrew, she sailed for Malacca where she could take shelter under the guns of the Dutch fort there. On 26 December she arrived at Trincomalee, which the French under Bailli de Suffren had captured from the British at the battle of Trincomalee on 3 September 1782, having left him and his squadron at Aceh, where they were wintering. At Trincomalee the memorist William Hickey met Trommelin. Later, Hickey described Pourvoyeuse as "Almost tumbling to pieces, and in want of every kind of stores." Fate Pourvoyeuse was later armed en flûte, with her armament reduced to 26 guns. She was eventually struck from the lists in 1794. Notes Citations References Spencer, Alfred, Ed. (1913–1925) The Memoirs of William Hickey (London: Hurst & Blackett). Unienville, Raymond d' (2004) Hier Suffren. Frigates of the French Navy Pourvoyeuse-class frigates 1772 ships Ships built in France
Andrick Cora Jackson (born November 6, 1978), aka Corey Jackson, is a former American football player who was a defensive lineman in the National Football League (NFL) from 2003 to 2007. Jackson played for the Cleveland Browns and the Denver Broncos. Jackson officially retired from the NFL in 2008. After retiring from the NFL, Jackson became a professional speaker and was featured on several television networks, newspapers, and magazines. Jackson is currently the CEO of Qwerkz, a social networking platform and database that allows athletes to form professional networks and find business opportunities. Early life On November 6, 1978, Andrick Cora Jackson was born in Camden, South Carolina to Andrew and Juanita Jackson. He attended North Central High School in Kershaw, South Carolina where he played basketball and ran track. In 1997, Jackson received an All Area MVP Award in basketball for the 1996–1997 basketball season. He was also named to the all-conference and all-defensive team. College career (1998–2003) In 1998, at the age of 19, Jackson quit his job at Walmart and bought a one-way Greyhound bus ticket to Ranger, Texas. He attended Ranger College from 1998 to 2000 and received an associate degree. While at Ranger College, Jackson played basketball under head coach Todd Neighbors, where he averaged 16.5 points, 11.0 rebounds, 2.0 assists and 2.0 blocked shots per game. During the 1999–2000 basketball season, his team posted a 17–13 record. After graduating from Ranger College in 2000, Jackson earned a basketball scholarship to the University of Nevada where he received a degree in speech communications. While at the University of Nevada, Jackson was voted team captain, finished sixth in the nation in rebounding, and averaged 9.9 points and 11.1 rebounds per game. Additionally, he was on the WAC all-defensive team and earned the Alpha Male of the Year Award. NFL career (2003–2008) In 2003, after deciding against playing professional basketball overseas, Jackson returned to the University of Nevada to continue his studies and was offered an opportunity to play football by the school's head football coach. Jackson played only 12 plays of college football and posted stats of 1 blocked field goal, 1 pass break up, and 1 tackle. In 2003, Jackson signed with the Cleveland Browns as a rookie free agent and participated on the practice squad. In 2004, Jackson signed a two-year contract with the Cleveland Browns and was added to the active roster, appearing in one game that season. During the 2004 season, Jackson played in NFL Europe, where he won Defensive MVP of the League. The Cleveland Browns released Jackson in 2005. But, shortly thereafter, he signed a contract with the Denver Broncos where he participated on the Broncos' practice squad. In 2006, he signed a two-year contract with the Denver Broncos. In September 2006, Jackson became injured and eventually was released by the Broncos. Jackson officially retired from the NFL in 2008. Later career (2008–2016) Prior to his official retirement from the NFL in 2008, Jackson formed his own company, Corey Jackson Speaks, which focused on motivational speaking. Jackson provides free daily inspirational messages on social media sites such as Facebook, LinkedIn, YouTube and Twitter. Corey also co-founded Stone Lion, a real estate investment trust. Qwerkz (2017–present) In 2017, Jackson launched Qwerkz, social networking platform and database which aims to help professional athletes and former athletes to develop professional relationships and launch business enterprises. Jackson compared the platform to LinkedIn in a 2017 interview with HuffPost. Jackson found that it was often difficult for young athletes to adapt to new careers after their athletic careers were over, and that many lacked the resumes and professional connections to be successful entrepreneurs. Qwerkz was intended to help athletes build 'social capital' and connect with companies. Qwerkz translates athletes' experiences in sports into practical skills sets that help them to become more qualified candidates and connect with companies. The Qwerkz app allows athletes to register with the site and begin networking with businesses and enterprises. Athletes can show off their entrepreneurial plans and accomplishments, and can collaborate with each other on personal projects. The app also allows fans to interact with their favorite athletes, and give feedback on their ideas and enterprises. In 2019 Qwerkz evolved into an executive recruiting firm specifically for pro athletes. Qwerkz takes athletes' experiences and skills and translates the into a traditional format. Jackson stated that he believes this process will give companies a better understanding of the athletes' value and how they can give their company an advantage in the market. References External links Qwerkz official website Living people 1978 births People from Camden, South Carolina Cleveland Browns players Denver Broncos players Nevada Wolf Pack football players Nevada Wolf Pack men's basketball players American men's basketball players
```php <?php /** * elFinder - file manager for web. * Session Wrapper Interface. * * @package elfinder * @author Naoki Sawada **/ interface elFinderSessionInterface { /** * Session start * * @return self **/ public function start(); /** * Session write & close * * @return self **/ public function close(); /** * Get session data * * This method must be equipped with an automatic start / close. * * @param string $key Target key * @param mixed $empty Return value of if session target key does not exist * * @return mixed **/ public function get($key, $empty = ''); /** * Set session data * * This method must be equipped with an automatic start / close. * * @param string $key Target key * @param mixed $data Value * * @return self **/ public function set($key, $data); /** * Get session data * * @param string $key Target key * * @return self **/ public function remove($key); } ```
```python # # # # path_to_url # # Unless required by applicable law or agreed to in writing, software # WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. # import sys import pathlib from ipex_llm.utils.common import invalidInputError, invalidOperationError def get_shared_lib_info(lib_base_name: str): # Determine the file extension based on the platform if sys.platform.startswith("linux") or sys.platform == "darwin": lib_ext = ".so" elif sys.platform == "win32": lib_ext = ".dll" else: invalidInputError(False, "Unsupported platform.") # Construct the paths to the possible shared library names (python/llm/src/bigdl/llm/libs) _base_path = pathlib.Path(__file__).parent.parent.resolve() _base_path = _base_path / 'libs' # Searching for the library in the current directory under the name "lib{lib_base_name}" # (default name for llmcpp) and "{lib_base_name}" (default name for this repo) _lib_paths = [ _base_path / f"lib{lib_base_name}-api{lib_ext}", _base_path / f"{lib_base_name}-api{lib_ext}", ] return _base_path, _lib_paths ```
```groff .\" $OpenBSD: UI_new.3,v 1.11 2022/12/17 22:23:31 tb Exp $ .\" full merge up to: OpenSSL 78b19e90 Jan 11 00:12:01 2017 +0100 .\" selective merge up to: OpenSSL 61f805c1 Jan 16 01:01:46 2018 +0800 .\" .\" This file was written by Richard Levitte <levitte@openssl.org>. .\" .\" Redistribution and use in source and binary forms, with or without .\" modification, are permitted provided that the following conditions .\" are met: .\" .\" 1. Redistributions of source code must retain the above copyright .\" notice, this list of conditions and the following disclaimer. .\" .\" 2. Redistributions in binary form must reproduce the above copyright .\" notice, this list of conditions and the following disclaimer in .\" the documentation and/or other materials provided with the .\" distribution. .\" .\" 3. All advertising materials mentioning features or use of this .\" software must display the following acknowledgment: .\" "This product includes software developed by the OpenSSL Project .\" for use in the OpenSSL Toolkit. (path_to_url" .\" .\" 4. The names "OpenSSL Toolkit" and "OpenSSL Project" must not be used to .\" endorse or promote products derived from this software without .\" prior written permission. For written permission, please contact .\" openssl-core@openssl.org. .\" .\" 5. Products derived from this software may not be called "OpenSSL" .\" nor may "OpenSSL" appear in their names without prior written .\" permission of the OpenSSL Project. .\" .\" 6. Redistributions of any form whatsoever must retain the following .\" acknowledgment: .\" "This product includes software developed by the OpenSSL Project .\" for use in the OpenSSL Toolkit (path_to_url" .\" .\" THIS SOFTWARE IS PROVIDED BY THE OpenSSL PROJECT ``AS IS'' AND ANY .\" EXPRESSED OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE .\" IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR .\" PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE OpenSSL PROJECT OR .\" ITS CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, .\" SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT .\" NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; .\" LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) .\" HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, .\" STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) .\" ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED .\" OF THE POSSIBILITY OF SUCH DAMAGE. .\" .Dd $Mdocdate: December 17 2022 $ .Dt UI_NEW 3 .Os .Sh NAME .Nm UI_new , .Nm UI_new_method , .Nm UI_free , .Nm UI_add_input_string , .Nm UI_dup_input_string , .Nm UI_add_verify_string , .Nm UI_dup_verify_string , .Nm UI_add_input_boolean , .Nm UI_dup_input_boolean , .Nm UI_add_info_string , .Nm UI_dup_info_string , .Nm UI_add_error_string , .Nm UI_dup_error_string , .Nm UI_construct_prompt , .Nm UI_add_user_data , .Nm UI_get0_user_data , .Nm UI_get0_result , .Nm UI_process , .Nm UI_ctrl , .Nm UI_set_default_method , .Nm UI_get_default_method , .Nm UI_get_method , .Nm UI_set_method , .Nm UI_OpenSSL , .Nm UI_null .Nd New User Interface .Sh SYNOPSIS .In openssl/ui.h .Ft UI * .Fn UI_new void .Ft UI * .Fo UI_new_method .Fa "const UI_METHOD *method" .Fc .Ft void .Fo UI_free .Fa "UI *ui" .Fc .Ft int .Fo UI_add_input_string .Fa "UI *ui" .Fa "const char *prompt" .Fa "int flags" .Fa "char *result_buf" .Fa "int minsize" .Fa "int maxsize" .Fc .Ft int .Fo UI_dup_input_string .Fa "UI *ui" .Fa "const char *prompt" .Fa "int flags" .Fa "char *result_buf" .Fa "int minsize" .Fa "int maxsize" .Fc .Ft int .Fo UI_add_verify_string .Fa "UI *ui" .Fa "const char *prompt" .Fa "int flags" .Fa "char *result_buf" .Fa "int minsize" .Fa "int maxsize" .Fa "const char *test_buf" .Fc .Ft int .Fo UI_dup_verify_string .Fa "UI *ui" .Fa "const char *prompt" .Fa "int flags" .Fa "char *result_buf" .Fa "int minsize" .Fa "int maxsize" .Fa "const char *test_buf" .Fc .Ft int .Fo UI_add_input_boolean .Fa "UI *ui" .Fa "const char *prompt" .Fa "const char *action_desc" .Fa "const char *ok_chars" .Fa "const char *cancel_chars" .Fa "int flags" .Fa "char *result_buf" .Fc .Ft int .Fo UI_dup_input_boolean .Fa "UI *ui" .Fa "const char *prompt" .Fa "const char *action_desc" .Fa "const char *ok_chars" .Fa "const char *cancel_chars" .Fa "int flags" .Fa "char *result_buf" .Fc .Ft int .Fo UI_add_info_string .Fa "UI *ui" .Fa "const char *text" .Fc .Ft int .Fo UI_dup_info_string .Fa "UI *ui" .Fa "const char *text" .Fc .Ft int .Fo UI_add_error_string .Fa "UI *ui" .Fa "const char *text" .Fc .Ft int .Fo UI_dup_error_string .Fa "UI *ui" .Fa "const char *text" .Fc .Fd /* These are the possible flags. They can be OR'ed together. */ .Fd #define UI_INPUT_FLAG_ECHO 0x01 .Fd #define UI_INPUT_FLAG_DEFAULT_PWD 0x02 .Ft char * .Fo UI_construct_prompt .Fa "UI *ui_method" .Fa "const char *object_desc" .Fa "const char *object_name" .Fc .Ft void * .Fo UI_add_user_data .Fa "UI *ui" .Fa "void *user_data" .Fc .Ft void * .Fo UI_get0_user_data .Fa "UI *ui" .Fc .Ft const char * .Fo UI_get0_result .Fa "UI *ui" .Fa "int i" .Fc .Ft int .Fo UI_process .Fa "UI *ui" .Fc .Ft int .Fo UI_ctrl .Fa "UI *ui" .Fa "int cmd" .Fa "long i" .Fa "void *p" .Fa "void (*f)()" .Fc .Fd #define UI_CTRL_PRINT_ERRORS 1 .Fd #define UI_CTRL_IS_REDOABLE 2 .Ft void .Fo UI_set_default_method .Fa "const UI_METHOD *meth" .Fc .Ft const UI_METHOD * .Fo UI_get_default_method .Fa void .Fc .Ft const UI_METHOD * .Fo UI_get_method .Fa "UI *ui" .Fc .Ft const UI_METHOD * .Fo UI_set_method .Fa "UI *ui" .Fa "const UI_METHOD *meth" .Fc .Ft UI_METHOD * .Fo UI_OpenSSL .Fa void .Fc .Ft const UI_METHOD * .Fo UI_null .Fa void .Fc .Sh DESCRIPTION UI stands for User Interface, and is a general purpose set of routines to prompt the user for text-based information. Through user-written methods (see .Xr UI_create_method 3 ) , prompting can be done in any way imaginable, be it plain text prompting, through dialog boxes or from a cell phone. .Pp All the functions work through a context of the type .Vt UI . This context contains all the information needed to prompt correctly as well as a reference to a .Vt UI_METHOD , which is an ordered vector of functions that carry out the actual prompting. .Pp The first thing to do is to create a .Vt UI with .Fn UI_new or .Fn UI_new_method , then add information to it with the .Fn UI_add_* or .Fn UI_dup_* functions. Also, user-defined random data can be passed down to the underlying method through calls to .Fn UI_add_user_data . The default UI method doesn't care about these data, but other methods might. Finally, use .Fn UI_process to actually perform the prompting and .Fn UI_get0_result to find the result to the prompt. .Pp A .Vt UI can contain more than one prompt, which are performed in the given sequence. Each prompt gets an index number which is returned by the .Fn UI_add_* and .Fn UI_dup_* functions, and has to be used to get the corresponding result with .Fn UI_get0_result . .Pp The functions are as follows: .Pp .Fn UI_new creates a new .Vt UI using the default UI method. When done with this UI, it should be freed using .Fn UI_free . .Pp .Fn UI_new_method creates a new .Vt UI using the given UI method. When done with this UI, it should be freed using .Fn UI_free . .Pp .Fn UI_OpenSSL returns the built-in UI method (note: not necessarily the default one, since the default can be changed. See further on). This method is the most machine/OS dependent part of OpenSSL and normally generates the most problems when porting. .Pp .Fn UI_null returns a UI method that does nothing. Its use is to avoid getting internal defaults for passed .Vt UI_METHOD pointers. .Pp .Fn UI_free removes .Fa ui from memory, along with all other pieces of memory that are connected to it, like duplicated input strings, results and others. If .Fa ui is a .Dv NULL pointer, no action occurs. .Pp .Fn UI_add_input_string and .Fn UI_add_verify_string add a prompt to .Fa ui , as well as flags and a result buffer and the desired minimum and maximum sizes of the result, not counting the final NUL character. The given information is used to prompt for information, for example a password, and to verify a password (i.e. having the user enter it twice and check that the same string was entered twice). .Fn UI_add_verify_string takes an extra argument that should be a pointer to the result buffer of the input string that it's supposed to verify, or verification will fail. .Pp .Fn UI_add_input_boolean adds a prompt to .Fa ui that's supposed to be answered in a boolean way, with a single character for yes and a different character for no. A set of characters that can be used to cancel the prompt is given as well. The prompt itself is really divided in two, one part being the descriptive text (given through the .Fa prompt argument) and one describing the possible answers (given through the .Fa action_desc argument). .Pp .Fn UI_add_info_string and .Fn UI_add_error_string add strings that are shown at the same time as the prompt for extra information or to show an error string. The difference between the two is only conceptual. With the builtin method, there's no technical difference between them. Other methods may make a difference between them, however. .Pp The flags currently supported are .Dv UI_INPUT_FLAG_ECHO , which is relevant for .Fn UI_add_input_string and will have the users response be echoed (when prompting for a password, this flag should obviously not be used), and .Dv UI_INPUT_FLAG_DEFAULT_PWD , which means that a default password of some sort will be used (completely depending on the application and the UI method). .Pp .Fn UI_dup_input_string , .Fn UI_dup_verify_string , .Fn UI_dup_input_boolean , .Fn UI_dup_info_string , and .Fn UI_dup_error_string are basically the same as their .Fn UI_add_* counterparts, except that they make their own copies of all strings. .Pp .Fn UI_construct_prompt is a helper function that can be used to create a prompt from two pieces of information: a description and a name. The default constructor (if there is none provided by the method used) creates a string "Enter .Em description for .Em name Ns :". With the description "pass phrase" and the file name "foo.key", that becomes "Enter pass phrase for foo.key:". Other methods may create whatever string and may include encodings that will be processed by the other method functions. .Pp .Fn UI_add_user_data adds a user data pointer for the method to use at any time. The builtin UI method doesn't care about this info. Note that several calls to this function doesn't add data - the previous blob is replaced with the one given as argument. .Pp .Fn UI_get0_user_data retrieves the data that has last been given to the .Fa ui with .Fn UI_add_user_data . .Pp .Fn UI_get0_result returns a pointer to the result buffer associated with the information indexed by .Fa i . .Pp .Fn UI_process goes through the information given so far, does all the printing and prompting and returns the final status, which is -2 on out-of-band events (Interrupt, Cancel, ...), -1 on error, or 0 on success. .Pp .Fn UI_ctrl adds extra control for the application author. For now, it understands two commands: .Dv UI_CTRL_PRINT_ERRORS , which makes .Fn UI_process print the OpenSSL error stack as part of processing the .Fa ui , and .Dv UI_CTRL_IS_REDOABLE , which returns a flag saying if the used .Fa ui can be used again or not. .Pp .Fn UI_set_default_method changes the default UI method to the one given. This function is not thread-safe and should not be called at the same time as other OpenSSL functions. .Pp .Fn UI_get_default_method returns a pointer to the current default UI method. .Pp .Fn UI_get_method returns the UI method associated with a given .Fa ui . .Pp .Fn UI_set_method changes the UI method associated with a given .Fa ui . .Sh RETURN VALUES .Fn UI_new and .Fn UI_new_method return a valid .Vt UI structure or .Dv NULL if an error occurred. .Pp .Fn UI_add_input_string , .Fn UI_dup_input_string , .Fn UI_add_verify_string , .Fn UI_dup_verify_string , .Fn UI_add_input_boolean , .Fn UI_dup_input_boolean , .Fn UI_add_info_string , .Fn UI_dup_info_string , .Fn UI_add_error_string , and .Fn UI_dup_error_string return a positive number on success or a number less than or equal to zero otherwise. .Pp .Fn UI_construct_prompt and .Fn UI_get0_result return a string or .Dv NULL if an error occurred. .Pp .Fn UI_add_user_data and .Fn UI_get0_user_data return a pointer to the user data that was contained in .Fa ui before the call. In particular, .Dv NULL is a valid return value. .Pp .Fn UI_process returns 0 on success or a negative value on error. .Pp .Fn UI_ctrl returns a mask on success or \-1 on error. .Pp .Fn UI_get_default_method , .Fn UI_OpenSSL and .Fn UI_null always return a pointer to a valid .Vt UI_METHOD structure. .Pp .Fn UI_get_method and .Fn UI_set_method return a pointer to the .Vt UI_METHOD structure that is installed in .Fa ui after the call. The OpenSSL documentation says that they can fail and return .Dv NULL , but currently, this can only happen when and after .Fn UI_set_method is called with an explicit .Dv NULL argument. .Sh SEE ALSO .Xr crypto 3 , .Xr UI_create_method 3 , .Xr UI_get_string_type 3 , .Xr UI_UTIL_read_pw 3 .Sh HISTORY These functions first appeared in OpenSSL 0.9.7 and have been available since .Ox 3.2 . .Pp .Fn UI_null first appeared in OpenSSL 1.1.1 and has been available since .Ox 7.3 . .Sh AUTHORS .An Richard Levitte Aq Mt richard@levitte.org for the OpenSSL project. ```
```text Memory Unknown Code 1 0 jgduff1 0 35151E80 40140000 # ASM Unknown Code 1 0 jgduff1 0 00197958 60000000 0 00197960 60000000 # Memory Unknown Code 2 0 jgduff1 0 34A3B3BC 35392E39 0 34A3B3C0 37363031 0 34A3B3C4 33313833 0 34A3B3C8 35392C7D 0 34FE26D0 34CE1980 0 35151E80 40140000 0 35BFC900 3F17E4D1 0 35BFC904 3F2AC629 0 35BFC908 3F2EEC6F 0 35BFC910 3DD07B50 0 35BFC914 3EFA2D95 0 35BFC918 3F04E837 # ```
```c /* Select target systems and architectures at runtime for GDB. 1999, 2000, 2001, 2002, 2003, 2004 Free Software Foundation, Inc. Contributed by Cygnus Support. This file is part of GDB. This program is free software; you can redistribute it and/or modify (at your option) any later version. This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the along with this program; if not, write to the Free Software Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ #include "defs.h" #include <errno.h> #include "gdb_string.h" #include "target.h" #include "gdbcmd.h" #include "symtab.h" #include "inferior.h" #include "bfd.h" #include "symfile.h" #include "objfiles.h" #include "gdb_wait.h" #include "dcache.h" #include <signal.h> #include "regcache.h" #include "gdb_assert.h" #include "gdbcore.h" static void target_info (char *, int); static void maybe_kill_then_attach (char *, int); static void kill_or_be_killed (int); static void default_terminal_info (char *, int); static int default_region_size_ok_for_hw_watchpoint (int); static int nosymbol (char *, CORE_ADDR *); static void tcomplain (void); static int nomemory (CORE_ADDR, char *, int, int, struct target_ops *); static int return_zero (void); static int return_one (void); static int return_minus_one (void); void target_ignore (void); static void target_command (char *, int); static struct target_ops *find_default_run_target (char *); static void nosupport_runtime (void); static LONGEST default_xfer_partial (struct target_ops *ops, enum target_object object, const char *annex, void *readbuf, const void *writebuf, ULONGEST offset, LONGEST len); /* Transfer LEN bytes between target address MEMADDR and GDB address MYADDR. Returns 0 for success, errno code for failure (which includes partial transfers -- if you want a more useful response to partial transfers, try either target_read_memory_partial or target_write_memory_partial). */ static int target_xfer_memory (CORE_ADDR memaddr, char *myaddr, int len, int write); static void init_dummy_target (void); static struct target_ops debug_target; static void debug_to_open (char *, int); static void debug_to_close (int); static void debug_to_attach (char *, int); static void debug_to_detach (char *, int); static void debug_to_disconnect (char *, int); static void debug_to_resume (ptid_t, int, enum target_signal); static ptid_t debug_to_wait (ptid_t, struct target_waitstatus *); static void debug_to_fetch_registers (int); static void debug_to_store_registers (int); static void debug_to_prepare_to_store (void); static int deprecated_debug_xfer_memory (CORE_ADDR, char *, int, int, struct mem_attrib *, struct target_ops *); static void debug_to_files_info (struct target_ops *); static int debug_to_insert_breakpoint (CORE_ADDR, char *); static int debug_to_remove_breakpoint (CORE_ADDR, char *); static int debug_to_can_use_hw_breakpoint (int, int, int); static int debug_to_insert_hw_breakpoint (CORE_ADDR, char *); static int debug_to_remove_hw_breakpoint (CORE_ADDR, char *); static int debug_to_insert_watchpoint (CORE_ADDR, int, int); static int debug_to_remove_watchpoint (CORE_ADDR, int, int); static int debug_to_stopped_by_watchpoint (void); static int debug_to_stopped_data_address (struct target_ops *, CORE_ADDR *); static int debug_to_region_size_ok_for_hw_watchpoint (int); static void debug_to_terminal_init (void); static void debug_to_terminal_inferior (void); static void debug_to_terminal_ours_for_output (void); static void debug_to_terminal_save_ours (void); static void debug_to_terminal_ours (void); static void debug_to_terminal_info (char *, int); static void debug_to_kill (void); static void debug_to_load (char *, int); static int debug_to_lookup_symbol (char *, CORE_ADDR *); static void debug_to_mourn_inferior (void); static int debug_to_can_run (void); static void debug_to_notice_signals (ptid_t); static int debug_to_thread_alive (ptid_t); static void debug_to_stop (void); /* NOTE: cagney/2004-09-29: Many targets reference this variable in wierd and mysterious ways. Putting the variable here lets those wierd and mysterious ways keep building while they are being converted to the inferior inheritance structure. */ struct target_ops deprecated_child_ops; /* Pointer to array of target architecture structures; the size of the array; the current index into the array; the allocated size of the array. */ struct target_ops **target_structs; unsigned target_struct_size; unsigned target_struct_index; unsigned target_struct_allocsize; #define DEFAULT_ALLOCSIZE 10 /* The initial current target, so that there is always a semi-valid current target. */ static struct target_ops dummy_target; /* Top of target stack. */ static struct target_ops *target_stack; /* The target structure we are currently using to talk to a process or file or whatever "inferior" we have. */ struct target_ops current_target; /* Command list for target. */ static struct cmd_list_element *targetlist = NULL; /* Nonzero if we are debugging an attached outside process rather than an inferior. */ int attach_flag; /* Non-zero if we want to see trace of target level stuff. */ static int targetdebug = 0; static void setup_target_debug (void); DCACHE *target_dcache; /* The user just typed 'target' without the name of a target. */ static void target_command (char *arg, int from_tty) { fputs_filtered ("Argument required (target name). Try `help target'\n", gdb_stdout); } /* Add a possible target architecture to the list. */ void add_target (struct target_ops *t) { /* Provide default values for all "must have" methods. */ if (t->to_xfer_partial == NULL) t->to_xfer_partial = default_xfer_partial; if (!target_structs) { target_struct_allocsize = DEFAULT_ALLOCSIZE; target_structs = (struct target_ops **) xmalloc (target_struct_allocsize * sizeof (*target_structs)); } if (target_struct_size >= target_struct_allocsize) { target_struct_allocsize *= 2; target_structs = (struct target_ops **) xrealloc ((char *) target_structs, target_struct_allocsize * sizeof (*target_structs)); } target_structs[target_struct_size++] = t; if (targetlist == NULL) add_prefix_cmd ("target", class_run, target_command, "Connect to a target machine or process.\n\ The first argument is the type or protocol of the target machine.\n\ Remaining arguments are interpreted by the target protocol. For more\n\ information on the arguments for a particular protocol, type\n\ `help target ' followed by the protocol name.", &targetlist, "target ", 0, &cmdlist); add_cmd (t->to_shortname, no_class, t->to_open, t->to_doc, &targetlist); } /* Stub functions */ void target_ignore (void) { } void target_load (char *arg, int from_tty) { dcache_invalidate (target_dcache); (*current_target.to_load) (arg, from_tty); } static int nomemory (CORE_ADDR memaddr, char *myaddr, int len, int write, struct target_ops *t) { errno = EIO; /* Can't read/write this location */ return 0; /* No bytes handled */ } static void tcomplain (void) { error ("You can't do that when your target is `%s'", current_target.to_shortname); } void noprocess (void) { error ("You can't do that without a process to debug."); } static int nosymbol (char *name, CORE_ADDR *addrp) { return 1; /* Symbol does not exist in target env */ } static void nosupport_runtime (void) { if (ptid_equal (inferior_ptid, null_ptid)) noprocess (); else error ("No run-time support for this"); } static void default_terminal_info (char *args, int from_tty) { printf_unfiltered ("No saved terminal information.\n"); } /* This is the default target_create_inferior and target_attach function. If the current target is executing, it asks whether to kill it off. If this function returns without calling error(), it has killed off the target, and the operation should be attempted. */ static void kill_or_be_killed (int from_tty) { if (target_has_execution) { printf_unfiltered ("You are already running a program:\n"); target_files_info (); if (query ("Kill it? ")) { target_kill (); if (target_has_execution) error ("Killing the program did not help."); return; } else { error ("Program not killed."); } } tcomplain (); } static void maybe_kill_then_attach (char *args, int from_tty) { kill_or_be_killed (from_tty); target_attach (args, from_tty); } static void maybe_kill_then_create_inferior (char *exec, char *args, char **env, int from_tty) { kill_or_be_killed (0); target_create_inferior (exec, args, env, from_tty); } /* Go through the target stack from top to bottom, copying over zero entries in current_target, then filling in still empty entries. In effect, we are doing class inheritance through the pushed target vectors. NOTE: cagney/2003-10-17: The problem with this inheritance, as it is currently implemented, is that it discards any knowledge of which target an inherited method originally belonged to. Consequently, new new target methods should instead explicitly and locally search the target stack for the target that can handle the request. */ static void update_current_target (void) { struct target_ops *t; /* First, reset curren'ts contents. */ memset (&current_target, 0, sizeof (current_target)); #define INHERIT(FIELD, TARGET) \ if (!current_target.FIELD) \ current_target.FIELD = (TARGET)->FIELD for (t = target_stack; t; t = t->beneath) { INHERIT (to_shortname, t); INHERIT (to_longname, t); INHERIT (to_doc, t); INHERIT (to_open, t); INHERIT (to_close, t); INHERIT (to_attach, t); INHERIT (to_post_attach, t); INHERIT (to_detach, t); INHERIT (to_disconnect, t); INHERIT (to_resume, t); INHERIT (to_wait, t); INHERIT (to_fetch_registers, t); INHERIT (to_store_registers, t); INHERIT (to_prepare_to_store, t); INHERIT (deprecated_xfer_memory, t); INHERIT (to_files_info, t); INHERIT (to_insert_breakpoint, t); INHERIT (to_remove_breakpoint, t); INHERIT (to_can_use_hw_breakpoint, t); INHERIT (to_insert_hw_breakpoint, t); INHERIT (to_remove_hw_breakpoint, t); INHERIT (to_insert_watchpoint, t); INHERIT (to_remove_watchpoint, t); INHERIT (to_stopped_data_address, t); INHERIT (to_stopped_by_watchpoint, t); INHERIT (to_have_continuable_watchpoint, t); INHERIT (to_region_size_ok_for_hw_watchpoint, t); INHERIT (to_terminal_init, t); INHERIT (to_terminal_inferior, t); INHERIT (to_terminal_ours_for_output, t); INHERIT (to_terminal_ours, t); INHERIT (to_terminal_save_ours, t); INHERIT (to_terminal_info, t); INHERIT (to_kill, t); INHERIT (to_load, t); INHERIT (to_lookup_symbol, t); INHERIT (to_create_inferior, t); INHERIT (to_post_startup_inferior, t); INHERIT (to_acknowledge_created_inferior, t); INHERIT (to_insert_fork_catchpoint, t); INHERIT (to_remove_fork_catchpoint, t); INHERIT (to_insert_vfork_catchpoint, t); INHERIT (to_remove_vfork_catchpoint, t); INHERIT (to_follow_fork, t); INHERIT (to_insert_exec_catchpoint, t); INHERIT (to_remove_exec_catchpoint, t); INHERIT (to_reported_exec_events_per_exec_call, t); INHERIT (to_has_exited, t); INHERIT (to_mourn_inferior, t); INHERIT (to_can_run, t); INHERIT (to_notice_signals, t); INHERIT (to_thread_alive, t); INHERIT (to_find_new_threads, t); INHERIT (to_pid_to_str, t); INHERIT (to_extra_thread_info, t); INHERIT (to_stop, t); /* Do not inherit to_xfer_partial. */ INHERIT (to_rcmd, t); INHERIT (to_enable_exception_callback, t); INHERIT (to_get_current_exception_event, t); INHERIT (to_pid_to_exec_file, t); INHERIT (to_stratum, t); INHERIT (to_has_all_memory, t); INHERIT (to_has_memory, t); INHERIT (to_has_stack, t); INHERIT (to_has_registers, t); INHERIT (to_has_execution, t); INHERIT (to_has_thread_control, t); INHERIT (to_sections, t); INHERIT (to_sections_end, t); INHERIT (to_can_async_p, t); INHERIT (to_is_async_p, t); INHERIT (to_async, t); INHERIT (to_async_mask_value, t); INHERIT (to_find_memory_regions, t); INHERIT (to_make_corefile_notes, t); INHERIT (to_get_thread_local_address, t); INHERIT (to_magic, t); } #undef INHERIT /* Clean up a target struct so it no longer has any zero pointers in it. Some entries are defaulted to a method that print an error, others are hard-wired to a standard recursive default. */ #define de_fault(field, value) \ if (!current_target.field) \ current_target.field = value de_fault (to_open, (void (*) (char *, int)) tcomplain); de_fault (to_close, (void (*) (int)) target_ignore); de_fault (to_attach, maybe_kill_then_attach); de_fault (to_post_attach, (void (*) (int)) target_ignore); de_fault (to_detach, (void (*) (char *, int)) target_ignore); de_fault (to_disconnect, (void (*) (char *, int)) tcomplain); de_fault (to_resume, (void (*) (ptid_t, int, enum target_signal)) noprocess); de_fault (to_wait, (ptid_t (*) (ptid_t, struct target_waitstatus *)) noprocess); de_fault (to_fetch_registers, (void (*) (int)) target_ignore); de_fault (to_store_registers, (void (*) (int)) noprocess); de_fault (to_prepare_to_store, (void (*) (void)) noprocess); de_fault (deprecated_xfer_memory, (int (*) (CORE_ADDR, char *, int, int, struct mem_attrib *, struct target_ops *)) nomemory); de_fault (to_files_info, (void (*) (struct target_ops *)) target_ignore); de_fault (to_insert_breakpoint, memory_insert_breakpoint); de_fault (to_remove_breakpoint, memory_remove_breakpoint); de_fault (to_can_use_hw_breakpoint, (int (*) (int, int, int)) return_zero); de_fault (to_insert_hw_breakpoint, (int (*) (CORE_ADDR, char *)) return_minus_one); de_fault (to_remove_hw_breakpoint, (int (*) (CORE_ADDR, char *)) return_minus_one); de_fault (to_insert_watchpoint, (int (*) (CORE_ADDR, int, int)) return_minus_one); de_fault (to_remove_watchpoint, (int (*) (CORE_ADDR, int, int)) return_minus_one); de_fault (to_stopped_by_watchpoint, (int (*) (void)) return_zero); de_fault (to_stopped_data_address, (int (*) (struct target_ops *, CORE_ADDR *)) return_zero); de_fault (to_region_size_ok_for_hw_watchpoint, default_region_size_ok_for_hw_watchpoint); de_fault (to_terminal_init, (void (*) (void)) target_ignore); de_fault (to_terminal_inferior, (void (*) (void)) target_ignore); de_fault (to_terminal_ours_for_output, (void (*) (void)) target_ignore); de_fault (to_terminal_ours, (void (*) (void)) target_ignore); de_fault (to_terminal_save_ours, (void (*) (void)) target_ignore); de_fault (to_terminal_info, default_terminal_info); de_fault (to_kill, (void (*) (void)) noprocess); de_fault (to_load, (void (*) (char *, int)) tcomplain); de_fault (to_lookup_symbol, (int (*) (char *, CORE_ADDR *)) nosymbol); de_fault (to_create_inferior, maybe_kill_then_create_inferior); de_fault (to_post_startup_inferior, (void (*) (ptid_t)) target_ignore); de_fault (to_acknowledge_created_inferior, (void (*) (int)) target_ignore); de_fault (to_insert_fork_catchpoint, (int (*) (int)) tcomplain); de_fault (to_remove_fork_catchpoint, (int (*) (int)) tcomplain); de_fault (to_insert_vfork_catchpoint, (int (*) (int)) tcomplain); de_fault (to_remove_vfork_catchpoint, (int (*) (int)) tcomplain); de_fault (to_follow_fork, (int (*) (int)) target_ignore); de_fault (to_insert_exec_catchpoint, (int (*) (int)) tcomplain); de_fault (to_remove_exec_catchpoint, (int (*) (int)) tcomplain); de_fault (to_reported_exec_events_per_exec_call, (int (*) (void)) return_one); de_fault (to_has_exited, (int (*) (int, int, int *)) return_zero); de_fault (to_mourn_inferior, (void (*) (void)) noprocess); de_fault (to_can_run, return_zero); de_fault (to_notice_signals, (void (*) (ptid_t)) target_ignore); de_fault (to_thread_alive, (int (*) (ptid_t)) return_zero); de_fault (to_find_new_threads, (void (*) (void)) target_ignore); de_fault (to_extra_thread_info, (char *(*) (struct thread_info *)) return_zero); de_fault (to_stop, (void (*) (void)) target_ignore); current_target.to_xfer_partial = default_xfer_partial; de_fault (to_rcmd, (void (*) (char *, struct ui_file *)) tcomplain); de_fault (to_enable_exception_callback, (struct symtab_and_line * (*) (enum exception_event_kind, int)) nosupport_runtime); de_fault (to_get_current_exception_event, (struct exception_event_record * (*) (void)) nosupport_runtime); de_fault (to_pid_to_exec_file, (char *(*) (int)) return_zero); de_fault (to_can_async_p, (int (*) (void)) return_zero); de_fault (to_is_async_p, (int (*) (void)) return_zero); de_fault (to_async, (void (*) (void (*) (enum inferior_event_type, void*), void*)) tcomplain); #undef de_fault /* Finally, position the target-stack beneath the squashed "current_target". That way code looking for a non-inherited target method can quickly and simply find it. */ current_target.beneath = target_stack; } /* Push a new target type into the stack of the existing target accessors, possibly superseding some of the existing accessors. Result is zero if the pushed target ended up on top of the stack, nonzero if at least one target is on top of it. Rather than allow an empty stack, we always have the dummy target at the bottom stratum, so we can call the function vectors without checking them. */ int push_target (struct target_ops *t) { struct target_ops **cur; /* Check magic number. If wrong, it probably means someone changed the struct definition, but not all the places that initialize one. */ if (t->to_magic != OPS_MAGIC) { fprintf_unfiltered (gdb_stderr, "Magic number of %s target struct wrong\n", t->to_shortname); internal_error (__FILE__, __LINE__, "failed internal consistency check"); } /* Find the proper stratum to install this target in. */ for (cur = &target_stack; (*cur) != NULL; cur = &(*cur)->beneath) { if ((int) (t->to_stratum) >= (int) (*cur)->to_stratum) break; } /* If there's already targets at this stratum, remove them. */ /* FIXME: cagney/2003-10-15: I think this should be poping all targets to CUR, and not just those at this stratum level. */ while ((*cur) != NULL && t->to_stratum == (*cur)->to_stratum) { /* There's already something at this stratum level. Close it, and un-hook it from the stack. */ struct target_ops *tmp = (*cur); (*cur) = (*cur)->beneath; tmp->beneath = NULL; target_close (tmp, 0); } /* We have removed all targets in our stratum, now add the new one. */ t->beneath = (*cur); (*cur) = t; update_current_target (); if (targetdebug) setup_target_debug (); /* Not on top? */ return (t != target_stack); } /* Remove a target_ops vector from the stack, wherever it may be. Return how many times it was removed (0 or 1). */ int unpush_target (struct target_ops *t) { struct target_ops **cur; struct target_ops *tmp; /* Look for the specified target. Note that we assume that a target can only occur once in the target stack. */ for (cur = &target_stack; (*cur) != NULL; cur = &(*cur)->beneath) { if ((*cur) == t) break; } if ((*cur) == NULL) return 0; /* Didn't find target_ops, quit now */ /* NOTE: cagney/2003-12-06: In '94 the close call was made unconditional by moving it to before the above check that the target was in the target stack (something about "Change the way pushing and popping of targets work to support target overlays and inheritance"). This doesn't make much sense - only open targets should be closed. */ target_close (t, 0); /* Unchain the target */ tmp = (*cur); (*cur) = (*cur)->beneath; tmp->beneath = NULL; update_current_target (); return 1; } void pop_target (void) { target_close (&current_target, 0); /* Let it clean up */ if (unpush_target (target_stack) == 1) return; fprintf_unfiltered (gdb_stderr, "pop_target couldn't find target %s\n", current_target.to_shortname); internal_error (__FILE__, __LINE__, "failed internal consistency check"); } #undef MIN #define MIN(A, B) (((A) <= (B)) ? (A) : (B)) /* target_read_string -- read a null terminated string, up to LEN bytes, from MEMADDR in target. Set *ERRNOP to the errno code, or 0 if successful. Set *STRING to a pointer to malloc'd memory containing the data; the caller is responsible for freeing it. Return the number of bytes successfully read. */ int target_read_string (CORE_ADDR memaddr, char **string, int len, int *errnop) { int tlen, origlen, offset, i; char buf[4]; int errcode = 0; char *buffer; int buffer_allocated; char *bufptr; unsigned int nbytes_read = 0; /* Small for testing. */ buffer_allocated = 4; buffer = xmalloc (buffer_allocated); bufptr = buffer; origlen = len; while (len > 0) { tlen = MIN (len, 4 - (memaddr & 3)); offset = memaddr & 3; errcode = target_read_memory (memaddr & ~3, buf, 4); if (errcode != 0) { /* The transfer request might have crossed the boundary to an unallocated region of memory. Retry the transfer, requesting a single byte. */ tlen = 1; offset = 0; errcode = target_read_memory (memaddr, buf, 1); if (errcode != 0) goto done; } if (bufptr - buffer + tlen > buffer_allocated) { unsigned int bytes; bytes = bufptr - buffer; buffer_allocated *= 2; buffer = xrealloc (buffer, buffer_allocated); bufptr = buffer + bytes; } for (i = 0; i < tlen; i++) { *bufptr++ = buf[i + offset]; if (buf[i + offset] == '\000') { nbytes_read += i + 1; goto done; } } memaddr += tlen; len -= tlen; nbytes_read += tlen; } done: if (errnop != NULL) *errnop = errcode; if (string != NULL) *string = buffer; return nbytes_read; } /* Find a section containing ADDR. */ struct section_table * target_section_by_addr (struct target_ops *target, CORE_ADDR addr) { struct section_table *secp; for (secp = target->to_sections; secp < target->to_sections_end; secp++) { if (addr >= secp->addr && addr < secp->endaddr) return secp; } return NULL; } /* Return non-zero when the target vector has supplied an xfer_partial method and it, rather than xfer_memory, should be used. */ static int target_xfer_partial_p (void) { return (target_stack != NULL && target_stack->to_xfer_partial != default_xfer_partial); } static LONGEST target_xfer_partial (struct target_ops *ops, enum target_object object, const char *annex, void *readbuf, const void *writebuf, ULONGEST offset, LONGEST len) { LONGEST retval; gdb_assert (ops->to_xfer_partial != NULL); retval = ops->to_xfer_partial (ops, object, annex, readbuf, writebuf, offset, len); if (targetdebug) { const unsigned char *myaddr = NULL; fprintf_unfiltered (gdb_stdlog, "%s:target_xfer_partial (%d, %s, 0x%lx, 0x%lx, 0x%s, %s) = %s", ops->to_shortname, (int) object, (annex ? annex : "(null)"), (long) readbuf, (long) writebuf, paddr_nz (offset), paddr_d (len), paddr_d (retval)); if (readbuf) myaddr = readbuf; if (writebuf) myaddr = writebuf; if (retval > 0 && myaddr != NULL) { int i; fputs_unfiltered (", bytes =", gdb_stdlog); for (i = 0; i < retval; i++) { if ((((long) &(myaddr[i])) & 0xf) == 0) { if (targetdebug < 2 && i > 0) { fprintf_unfiltered (gdb_stdlog, " ..."); break; } fprintf_unfiltered (gdb_stdlog, "\n"); } fprintf_unfiltered (gdb_stdlog, " %02x", myaddr[i] & 0xff); } } fputc_unfiltered ('\n', gdb_stdlog); } return retval; } /* Attempt a transfer all LEN bytes starting at OFFSET between the inferior's KIND:ANNEX space and GDB's READBUF/WRITEBUF buffer. If the transfer succeeds, return zero, otherwize the host ERRNO is returned. The inferior is formed from several layers. In the case of corefiles, inf-corefile is layered above inf-exec and a request for text (corefiles do not include text pages) will be first sent to the core-stratum, fail, and then sent to the object-file where it will succeed. NOTE: cagney/2004-09-30: The old code tried to use four separate mechanisms for mapping an object:offset:len tuple onto an inferior and its address space: the target stack; the inferior's TO_SECTIONS; solib's SO_LIST; overlays. This is stupid. The code below is instead using a single mechanism (currently strata). If that mechanism proves insufficient then re-factor it implementing another singluar mechanism (for instance, a generic object:annex onto inferior:object:annex say). */ static LONGEST xfer_using_stratum (enum target_object object, const char *annex, ULONGEST offset, LONGEST len, void *readbuf, const void *writebuf) { LONGEST xfered; struct target_ops *target; /* Always successful. */ if (len == 0) return 0; /* Never successful. */ if (target_stack == NULL) return EIO; target = target_stack; while (1) { xfered = target_xfer_partial (target, object, annex, readbuf, writebuf, offset, len); if (xfered > 0) { /* The partial xfer succeeded, update the counts, check that the xfer hasn't finished and if it hasn't set things up for the next round. */ len -= xfered; if (len <= 0) return 0; offset += xfered; if (readbuf != NULL) readbuf = (bfd_byte *) readbuf + xfered; if (writebuf != NULL) writebuf = (bfd_byte *) writebuf + xfered; target = target_stack; } else if (xfered < 0) { /* Something totally screwed up, abandon the attempt to xfer. */ if (errno) return errno; else return EIO; } else { /* This "stratum" didn't work, try the next one down. */ target = target->beneath; if (target == NULL) return EIO; } } } /* Read LEN bytes of target memory at address MEMADDR, placing the results in GDB's memory at MYADDR. Returns either 0 for success or an errno value if any error occurs. If an error occurs, no guarantee is made about the contents of the data at MYADDR. In particular, the caller should not depend upon partial reads filling the buffer with good data. There is no way for the caller to know how much good data might have been transfered anyway. Callers that can deal with partial reads should call target_read_memory_partial. */ int target_read_memory (CORE_ADDR memaddr, char *myaddr, int len) { if (target_xfer_partial_p ()) return xfer_using_stratum (TARGET_OBJECT_MEMORY, NULL, memaddr, len, myaddr, NULL); else return target_xfer_memory (memaddr, myaddr, len, 0); } int target_write_memory (CORE_ADDR memaddr, char *myaddr, int len) { if (target_xfer_partial_p ()) return xfer_using_stratum (TARGET_OBJECT_MEMORY, NULL, memaddr, len, NULL, myaddr); else return target_xfer_memory (memaddr, myaddr, len, 1); } #ifndef target_stopped_data_address_p int target_stopped_data_address_p (struct target_ops *target) { if (target->to_stopped_data_address == (int (*) (struct target_ops *, CORE_ADDR *)) return_zero) return 0; if (target->to_stopped_data_address == debug_to_stopped_data_address && (debug_target.to_stopped_data_address == (int (*) (struct target_ops *, CORE_ADDR *)) return_zero)) return 0; return 1; } #endif static int trust_readonly = 0; /* Move memory to or from the targets. The top target gets priority; if it cannot handle it, it is offered to the next one down, etc. Result is -1 on error, or the number of bytes transfered. */ int do_xfer_memory (CORE_ADDR memaddr, char *myaddr, int len, int write, struct mem_attrib *attrib) { int res; int done = 0; struct target_ops *t; /* Zero length requests are ok and require no work. */ if (len == 0) return 0; /* deprecated_xfer_memory is not guaranteed to set errno, even when it returns 0. */ errno = 0; if (!write && trust_readonly) { struct section_table *secp; /* User-settable option, "trust-readonly-sections". If true, then memory from any SEC_READONLY bfd section may be read directly from the bfd file. */ secp = target_section_by_addr (&current_target, memaddr); if (secp != NULL && (bfd_get_section_flags (secp->bfd, secp->the_bfd_section) & SEC_READONLY)) return xfer_memory (memaddr, myaddr, len, 0, attrib, &current_target); } /* The quick case is that the top target can handle the transfer. */ res = current_target.deprecated_xfer_memory (memaddr, myaddr, len, write, attrib, &current_target); /* If res <= 0 then we call it again in the loop. Ah well. */ if (res <= 0) { for (t = target_stack; t != NULL; t = t->beneath) { if (!t->to_has_memory) continue; res = t->deprecated_xfer_memory (memaddr, myaddr, len, write, attrib, t); if (res > 0) break; /* Handled all or part of xfer */ if (t->to_has_all_memory) break; } if (res <= 0) return -1; } return res; } /* Perform a memory transfer. Iterate until the entire region has been transfered. Result is 0 or errno value. */ static int target_xfer_memory (CORE_ADDR memaddr, char *myaddr, int len, int write) { int res; int reg_len; struct mem_region *region; /* Zero length requests are ok and require no work. */ if (len == 0) { return 0; } while (len > 0) { region = lookup_mem_region(memaddr); if (memaddr + len < region->hi) reg_len = len; else reg_len = region->hi - memaddr; switch (region->attrib.mode) { case MEM_RO: if (write) return EIO; break; case MEM_WO: if (!write) return EIO; break; } while (reg_len > 0) { if (region->attrib.cache) res = dcache_xfer_memory (target_dcache, memaddr, myaddr, reg_len, write); else res = do_xfer_memory (memaddr, myaddr, reg_len, write, &region->attrib); if (res <= 0) { /* If this address is for nonexistent memory, read zeros if reading, or do nothing if writing. Return error. */ if (!write) memset (myaddr, 0, len); if (errno == 0) return EIO; else return errno; } memaddr += res; myaddr += res; len -= res; reg_len -= res; } } return 0; /* We managed to cover it all somehow. */ } /* Perform a partial memory transfer. Result is -1 on error, or the number of bytes transfered. */ static int target_xfer_memory_partial (CORE_ADDR memaddr, char *myaddr, int len, int write_p, int *err) { int res; int reg_len; struct mem_region *region; /* Zero length requests are ok and require no work. */ if (len == 0) { *err = 0; return 0; } region = lookup_mem_region(memaddr); if (memaddr + len < region->hi) reg_len = len; else reg_len = region->hi - memaddr; switch (region->attrib.mode) { case MEM_RO: if (write_p) { *err = EIO; return -1; } break; case MEM_WO: if (write_p) { *err = EIO; return -1; } break; } if (region->attrib.cache) res = dcache_xfer_memory (target_dcache, memaddr, myaddr, reg_len, write_p); else res = do_xfer_memory (memaddr, myaddr, reg_len, write_p, &region->attrib); if (res <= 0) { if (errno != 0) *err = errno; else *err = EIO; return -1; } *err = 0; return res; } int target_read_memory_partial (CORE_ADDR memaddr, char *buf, int len, int *err) { if (target_xfer_partial_p ()) return target_xfer_partial (target_stack, TARGET_OBJECT_MEMORY, NULL, buf, NULL, memaddr, len); else return target_xfer_memory_partial (memaddr, buf, len, 0, err); } int target_write_memory_partial (CORE_ADDR memaddr, char *buf, int len, int *err) { if (target_xfer_partial_p ()) return target_xfer_partial (target_stack, TARGET_OBJECT_MEMORY, NULL, NULL, buf, memaddr, len); else return target_xfer_memory_partial (memaddr, buf, len, 1, err); } /* More generic transfers. */ static LONGEST default_xfer_partial (struct target_ops *ops, enum target_object object, const char *annex, void *readbuf, const void *writebuf, ULONGEST offset, LONGEST len) { if (object == TARGET_OBJECT_MEMORY && ops->deprecated_xfer_memory != NULL) /* If available, fall back to the target's "deprecated_xfer_memory" method. */ { int xfered = -1; errno = 0; if (writebuf != NULL) { void *buffer = xmalloc (len); struct cleanup *cleanup = make_cleanup (xfree, buffer); memcpy (buffer, writebuf, len); xfered = ops->deprecated_xfer_memory (offset, buffer, len, 1/*write*/, NULL, ops); do_cleanups (cleanup); } if (readbuf != NULL) xfered = ops->deprecated_xfer_memory (offset, readbuf, len, 0/*read*/, NULL, ops); if (xfered > 0) return xfered; else if (xfered == 0 && errno == 0) /* "deprecated_xfer_memory" uses 0, cross checked against ERRNO as one indication of an error. */ return 0; else return -1; } else if (ops->beneath != NULL) return target_xfer_partial (ops->beneath, object, annex, readbuf, writebuf, offset, len); else return -1; } /* Target vector read/write partial wrapper functions. NOTE: cagney/2003-10-21: I wonder if having "to_xfer_partial (inbuf, outbuf)", instead of separate read/write methods, make life easier. */ LONGEST target_read_partial (struct target_ops *ops, enum target_object object, const char *annex, void *buf, ULONGEST offset, LONGEST len) { return target_xfer_partial (ops, object, annex, buf, NULL, offset, len); } LONGEST target_write_partial (struct target_ops *ops, enum target_object object, const char *annex, const void *buf, ULONGEST offset, LONGEST len) { return target_xfer_partial (ops, object, annex, NULL, buf, offset, len); } /* Wrappers to perform the full transfer. */ LONGEST target_read (struct target_ops *ops, enum target_object object, const char *annex, void *buf, ULONGEST offset, LONGEST len) { LONGEST xfered = 0; while (xfered < len) { LONGEST xfer = target_read_partial (ops, object, annex, (bfd_byte *) buf + xfered, offset + xfered, len - xfered); /* Call an observer, notifying them of the xfer progress? */ if (xfer <= 0) /* Call memory_error? */ return -1; xfered += xfer; QUIT; } return len; } LONGEST target_write (struct target_ops *ops, enum target_object object, const char *annex, const void *buf, ULONGEST offset, LONGEST len) { LONGEST xfered = 0; while (xfered < len) { LONGEST xfer = target_write_partial (ops, object, annex, (bfd_byte *) buf + xfered, offset + xfered, len - xfered); /* Call an observer, notifying them of the xfer progress? */ if (xfer <= 0) /* Call memory_error? */ return -1; xfered += xfer; QUIT; } return len; } /* Memory transfer methods. */ void get_target_memory (struct target_ops *ops, CORE_ADDR addr, void *buf, LONGEST len) { if (target_read (ops, TARGET_OBJECT_MEMORY, NULL, buf, addr, len) != len) memory_error (EIO, addr); } ULONGEST get_target_memory_unsigned (struct target_ops *ops, CORE_ADDR addr, int len) { char buf[sizeof (ULONGEST)]; gdb_assert (len <= sizeof (buf)); get_target_memory (ops, addr, buf, len); return extract_unsigned_integer (buf, len); } static void target_info (char *args, int from_tty) { struct target_ops *t; int has_all_mem = 0; if (symfile_objfile != NULL) printf_unfiltered ("Symbols from \"%s\".\n", symfile_objfile->name); for (t = target_stack; t != NULL; t = t->beneath) { if (!t->to_has_memory) continue; if ((int) (t->to_stratum) <= (int) dummy_stratum) continue; if (has_all_mem) printf_unfiltered ("\tWhile running this, GDB does not access memory from...\n"); printf_unfiltered ("%s:\n", t->to_longname); (t->to_files_info) (t); has_all_mem = t->to_has_all_memory; } } /* This is to be called by the open routine before it does anything. */ void target_preopen (int from_tty) { dont_repeat (); if (target_has_execution) { if (!from_tty || query ("A program is being debugged already. Kill it? ")) target_kill (); else error ("Program not killed."); } /* Calling target_kill may remove the target from the stack. But if it doesn't (which seems like a win for UDI), remove it now. */ if (target_has_execution) pop_target (); } /* Detach a target after doing deferred register stores. */ void target_detach (char *args, int from_tty) { (current_target.to_detach) (args, from_tty); } void target_disconnect (char *args, int from_tty) { (current_target.to_disconnect) (args, from_tty); } void target_link (char *modname, CORE_ADDR *t_reloc) { if (DEPRECATED_STREQ (current_target.to_shortname, "rombug")) { (current_target.to_lookup_symbol) (modname, t_reloc); if (*t_reloc == 0) error ("Unable to link to %s and get relocation in rombug", modname); } else *t_reloc = (CORE_ADDR) -1; } int target_async_mask (int mask) { int saved_async_masked_status = target_async_mask_value; target_async_mask_value = mask; return saved_async_masked_status; } /* Look through the list of possible targets for a target that can execute a run or attach command without any other data. This is used to locate the default process stratum. Result is always valid (error() is called for errors). */ static struct target_ops * find_default_run_target (char *do_mesg) { struct target_ops **t; struct target_ops *runable = NULL; int count; count = 0; for (t = target_structs; t < target_structs + target_struct_size; ++t) { if ((*t)->to_can_run && target_can_run (*t)) { runable = *t; ++count; } } if (count != 1) error ("Don't know how to %s. Try \"help target\".", do_mesg); return runable; } void find_default_attach (char *args, int from_tty) { struct target_ops *t; t = find_default_run_target ("attach"); (t->to_attach) (args, from_tty); return; } void find_default_create_inferior (char *exec_file, char *allargs, char **env, int from_tty) { struct target_ops *t; t = find_default_run_target ("run"); (t->to_create_inferior) (exec_file, allargs, env, from_tty); return; } static int default_region_size_ok_for_hw_watchpoint (int byte_count) { return (byte_count <= TYPE_LENGTH (builtin_type_void_data_ptr)); } static int return_zero (void) { return 0; } static int return_one (void) { return 1; } static int return_minus_one (void) { return -1; } /* * Resize the to_sections pointer. Also make sure that anyone that * was holding on to an old value of it gets updated. * Returns the old size. */ int target_resize_to_sections (struct target_ops *target, int num_added) { struct target_ops **t; struct section_table *old_value; int old_count; old_value = target->to_sections; if (target->to_sections) { old_count = target->to_sections_end - target->to_sections; target->to_sections = (struct section_table *) xrealloc ((char *) target->to_sections, (sizeof (struct section_table)) * (num_added + old_count)); } else { old_count = 0; target->to_sections = (struct section_table *) xmalloc ((sizeof (struct section_table)) * num_added); } target->to_sections_end = target->to_sections + (num_added + old_count); /* Check to see if anyone else was pointing to this structure. If old_value was null, then no one was. */ if (old_value) { for (t = target_structs; t < target_structs + target_struct_size; ++t) { if ((*t)->to_sections == old_value) { (*t)->to_sections = target->to_sections; (*t)->to_sections_end = target->to_sections_end; } } /* There is a flattened view of the target stack in current_target, so its to_sections pointer might also need updating. */ if (current_target.to_sections == old_value) { current_target.to_sections = target->to_sections; current_target.to_sections_end = target->to_sections_end; } } return old_count; } /* Remove all target sections taken from ABFD. Scan the current target stack for targets whose section tables refer to sections from BFD, and remove those sections. We use this when we notice that the inferior has unloaded a shared object, for example. */ void remove_target_sections (bfd *abfd) { struct target_ops **t; for (t = target_structs; t < target_structs + target_struct_size; t++) { struct section_table *src, *dest; dest = (*t)->to_sections; for (src = (*t)->to_sections; src < (*t)->to_sections_end; src++) if (src->bfd != abfd) { /* Keep this section. */ if (dest < src) *dest = *src; dest++; } /* If we've dropped any sections, resize the section table. */ if (dest < src) target_resize_to_sections (*t, dest - src); } } /* Find a single runnable target in the stack and return it. If for some reason there is more than one, return NULL. */ struct target_ops * find_run_target (void) { struct target_ops **t; struct target_ops *runable = NULL; int count; count = 0; for (t = target_structs; t < target_structs + target_struct_size; ++t) { if ((*t)->to_can_run && target_can_run (*t)) { runable = *t; ++count; } } return (count == 1 ? runable : NULL); } /* Find a single core_stratum target in the list of targets and return it. If for some reason there is more than one, return NULL. */ struct target_ops * find_core_target (void) { struct target_ops **t; struct target_ops *runable = NULL; int count; count = 0; for (t = target_structs; t < target_structs + target_struct_size; ++t) { if ((*t)->to_stratum == core_stratum) { runable = *t; ++count; } } return (count == 1 ? runable : NULL); } /* * Find the next target down the stack from the specified target. */ struct target_ops * find_target_beneath (struct target_ops *t) { return t->beneath; } /* The inferior process has died. Long live the inferior! */ void generic_mourn_inferior (void) { extern int show_breakpoint_hit_counts; inferior_ptid = null_ptid; attach_flag = 0; breakpoint_init_inferior (inf_exited); registers_changed (); reopen_exec_file (); reinit_frame_cache (); /* It is confusing to the user for ignore counts to stick around from previous runs of the inferior. So clear them. */ /* However, it is more confusing for the ignore counts to disappear when using hit counts. So don't clear them if we're counting hits. */ if (!show_breakpoint_hit_counts) breakpoint_clear_ignore_counts (); if (deprecated_detach_hook) deprecated_detach_hook (); } /* Helper function for child_wait and the Lynx derivatives of child_wait. HOSTSTATUS is the waitstatus from wait() or the equivalent; store our translation of that in OURSTATUS. */ void store_waitstatus (struct target_waitstatus *ourstatus, int hoststatus) { #ifdef CHILD_SPECIAL_WAITSTATUS /* CHILD_SPECIAL_WAITSTATUS should return nonzero and set *OURSTATUS if it wants to deal with hoststatus. */ if (CHILD_SPECIAL_WAITSTATUS (ourstatus, hoststatus)) return; #endif if (WIFEXITED (hoststatus)) { ourstatus->kind = TARGET_WAITKIND_EXITED; ourstatus->value.integer = WEXITSTATUS (hoststatus); } else if (!WIFSTOPPED (hoststatus)) { ourstatus->kind = TARGET_WAITKIND_SIGNALLED; ourstatus->value.sig = target_signal_from_host (WTERMSIG (hoststatus)); } else { ourstatus->kind = TARGET_WAITKIND_STOPPED; ourstatus->value.sig = target_signal_from_host (WSTOPSIG (hoststatus)); } } /* Returns zero to leave the inferior alone, one to interrupt it. */ int (*target_activity_function) (void); int target_activity_fd; /* Convert a normal process ID to a string. Returns the string in a static buffer. */ char * normal_pid_to_str (ptid_t ptid) { static char buf[30]; sprintf (buf, "process %d", PIDGET (ptid)); return buf; } /* Error-catcher for target_find_memory_regions */ static int dummy_find_memory_regions (int (*ignore1) (), void *ignore2) { error ("No target."); return 0; } /* Error-catcher for target_make_corefile_notes */ static char * dummy_make_corefile_notes (bfd *ignore1, int *ignore2) { error ("No target."); return NULL; } /* Set up the handful of non-empty slots needed by the dummy target vector. */ static void init_dummy_target (void) { dummy_target.to_shortname = "None"; dummy_target.to_longname = "None"; dummy_target.to_doc = ""; dummy_target.to_attach = find_default_attach; dummy_target.to_create_inferior = find_default_create_inferior; dummy_target.to_pid_to_str = normal_pid_to_str; dummy_target.to_stratum = dummy_stratum; dummy_target.to_find_memory_regions = dummy_find_memory_regions; dummy_target.to_make_corefile_notes = dummy_make_corefile_notes; dummy_target.to_xfer_partial = default_xfer_partial; dummy_target.to_magic = OPS_MAGIC; } static void debug_to_open (char *args, int from_tty) { debug_target.to_open (args, from_tty); fprintf_unfiltered (gdb_stdlog, "target_open (%s, %d)\n", args, from_tty); } static void debug_to_close (int quitting) { target_close (&debug_target, quitting); fprintf_unfiltered (gdb_stdlog, "target_close (%d)\n", quitting); } void target_close (struct target_ops *targ, int quitting) { if (targ->to_xclose != NULL) targ->to_xclose (targ, quitting); else if (targ->to_close != NULL) targ->to_close (quitting); } static void debug_to_attach (char *args, int from_tty) { debug_target.to_attach (args, from_tty); fprintf_unfiltered (gdb_stdlog, "target_attach (%s, %d)\n", args, from_tty); } static void debug_to_post_attach (int pid) { debug_target.to_post_attach (pid); fprintf_unfiltered (gdb_stdlog, "target_post_attach (%d)\n", pid); } static void debug_to_detach (char *args, int from_tty) { debug_target.to_detach (args, from_tty); fprintf_unfiltered (gdb_stdlog, "target_detach (%s, %d)\n", args, from_tty); } static void debug_to_disconnect (char *args, int from_tty) { debug_target.to_disconnect (args, from_tty); fprintf_unfiltered (gdb_stdlog, "target_disconnect (%s, %d)\n", args, from_tty); } static void debug_to_resume (ptid_t ptid, int step, enum target_signal siggnal) { debug_target.to_resume (ptid, step, siggnal); fprintf_unfiltered (gdb_stdlog, "target_resume (%d, %s, %s)\n", PIDGET (ptid), step ? "step" : "continue", target_signal_to_name (siggnal)); } static ptid_t debug_to_wait (ptid_t ptid, struct target_waitstatus *status) { ptid_t retval; retval = debug_target.to_wait (ptid, status); fprintf_unfiltered (gdb_stdlog, "target_wait (%d, status) = %d, ", PIDGET (ptid), PIDGET (retval)); fprintf_unfiltered (gdb_stdlog, "status->kind = "); switch (status->kind) { case TARGET_WAITKIND_EXITED: fprintf_unfiltered (gdb_stdlog, "exited, status = %d\n", status->value.integer); break; case TARGET_WAITKIND_STOPPED: fprintf_unfiltered (gdb_stdlog, "stopped, signal = %s\n", target_signal_to_name (status->value.sig)); break; case TARGET_WAITKIND_SIGNALLED: fprintf_unfiltered (gdb_stdlog, "signalled, signal = %s\n", target_signal_to_name (status->value.sig)); break; case TARGET_WAITKIND_LOADED: fprintf_unfiltered (gdb_stdlog, "loaded\n"); break; case TARGET_WAITKIND_FORKED: fprintf_unfiltered (gdb_stdlog, "forked\n"); break; case TARGET_WAITKIND_VFORKED: fprintf_unfiltered (gdb_stdlog, "vforked\n"); break; case TARGET_WAITKIND_EXECD: fprintf_unfiltered (gdb_stdlog, "execd\n"); break; case TARGET_WAITKIND_SPURIOUS: fprintf_unfiltered (gdb_stdlog, "spurious\n"); break; default: fprintf_unfiltered (gdb_stdlog, "unknown???\n"); break; } return retval; } static void debug_print_register (const char * func, int regno) { fprintf_unfiltered (gdb_stdlog, "%s ", func); if (regno >= 0 && regno < NUM_REGS + NUM_PSEUDO_REGS && REGISTER_NAME (regno) != NULL && REGISTER_NAME (regno)[0] != '\0') fprintf_unfiltered (gdb_stdlog, "(%s)", REGISTER_NAME (regno)); else fprintf_unfiltered (gdb_stdlog, "(%d)", regno); if (regno >= 0) { int i; unsigned char buf[MAX_REGISTER_SIZE]; deprecated_read_register_gen (regno, buf); fprintf_unfiltered (gdb_stdlog, " = "); for (i = 0; i < register_size (current_gdbarch, regno); i++) { fprintf_unfiltered (gdb_stdlog, "%02x", buf[i]); } if (register_size (current_gdbarch, regno) <= sizeof (LONGEST)) { fprintf_unfiltered (gdb_stdlog, " 0x%s %s", paddr_nz (read_register (regno)), paddr_d (read_register (regno))); } } fprintf_unfiltered (gdb_stdlog, "\n"); } static void debug_to_fetch_registers (int regno) { debug_target.to_fetch_registers (regno); debug_print_register ("target_fetch_registers", regno); } static void debug_to_store_registers (int regno) { debug_target.to_store_registers (regno); debug_print_register ("target_store_registers", regno); fprintf_unfiltered (gdb_stdlog, "\n"); } static void debug_to_prepare_to_store (void) { debug_target.to_prepare_to_store (); fprintf_unfiltered (gdb_stdlog, "target_prepare_to_store ()\n"); } static int deprecated_debug_xfer_memory (CORE_ADDR memaddr, char *myaddr, int len, int write, struct mem_attrib *attrib, struct target_ops *target) { int retval; retval = debug_target.deprecated_xfer_memory (memaddr, myaddr, len, write, attrib, target); fprintf_unfiltered (gdb_stdlog, "target_xfer_memory (0x%x, xxx, %d, %s, xxx) = %d", (unsigned int) memaddr, /* possable truncate long long */ len, write ? "write" : "read", retval); if (retval > 0) { int i; fputs_unfiltered (", bytes =", gdb_stdlog); for (i = 0; i < retval; i++) { if ((((long) &(myaddr[i])) & 0xf) == 0) { if (targetdebug < 2 && i > 0) { fprintf_unfiltered (gdb_stdlog, " ..."); break; } fprintf_unfiltered (gdb_stdlog, "\n"); } fprintf_unfiltered (gdb_stdlog, " %02x", myaddr[i] & 0xff); } } fputc_unfiltered ('\n', gdb_stdlog); return retval; } static void debug_to_files_info (struct target_ops *target) { debug_target.to_files_info (target); fprintf_unfiltered (gdb_stdlog, "target_files_info (xxx)\n"); } static int debug_to_insert_breakpoint (CORE_ADDR addr, char *save) { int retval; retval = debug_target.to_insert_breakpoint (addr, save); fprintf_unfiltered (gdb_stdlog, "target_insert_breakpoint (0x%lx, xxx) = %ld\n", (unsigned long) addr, (unsigned long) retval); return retval; } static int debug_to_remove_breakpoint (CORE_ADDR addr, char *save) { int retval; retval = debug_target.to_remove_breakpoint (addr, save); fprintf_unfiltered (gdb_stdlog, "target_remove_breakpoint (0x%lx, xxx) = %ld\n", (unsigned long) addr, (unsigned long) retval); return retval; } static int debug_to_can_use_hw_breakpoint (int type, int cnt, int from_tty) { int retval; retval = debug_target.to_can_use_hw_breakpoint (type, cnt, from_tty); fprintf_unfiltered (gdb_stdlog, "target_can_use_hw_breakpoint (%ld, %ld, %ld) = %ld\n", (unsigned long) type, (unsigned long) cnt, (unsigned long) from_tty, (unsigned long) retval); return retval; } static int debug_to_region_size_ok_for_hw_watchpoint (int byte_count) { CORE_ADDR retval; retval = debug_target.to_region_size_ok_for_hw_watchpoint (byte_count); fprintf_unfiltered (gdb_stdlog, "TARGET_REGION_SIZE_OK_FOR_HW_WATCHPOINT (%ld) = 0x%lx\n", (unsigned long) byte_count, (unsigned long) retval); return retval; } static int debug_to_stopped_by_watchpoint (void) { int retval; retval = debug_target.to_stopped_by_watchpoint (); fprintf_unfiltered (gdb_stdlog, "STOPPED_BY_WATCHPOINT () = %ld\n", (unsigned long) retval); return retval; } static int debug_to_stopped_data_address (struct target_ops *target, CORE_ADDR *addr) { int retval; retval = debug_target.to_stopped_data_address (target, addr); fprintf_unfiltered (gdb_stdlog, "target_stopped_data_address ([0x%lx]) = %ld\n", (unsigned long)*addr, (unsigned long)retval); return retval; } static int debug_to_insert_hw_breakpoint (CORE_ADDR addr, char *save) { int retval; retval = debug_target.to_insert_hw_breakpoint (addr, save); fprintf_unfiltered (gdb_stdlog, "target_insert_hw_breakpoint (0x%lx, xxx) = %ld\n", (unsigned long) addr, (unsigned long) retval); return retval; } static int debug_to_remove_hw_breakpoint (CORE_ADDR addr, char *save) { int retval; retval = debug_target.to_remove_hw_breakpoint (addr, save); fprintf_unfiltered (gdb_stdlog, "target_remove_hw_breakpoint (0x%lx, xxx) = %ld\n", (unsigned long) addr, (unsigned long) retval); return retval; } static int debug_to_insert_watchpoint (CORE_ADDR addr, int len, int type) { int retval; retval = debug_target.to_insert_watchpoint (addr, len, type); fprintf_unfiltered (gdb_stdlog, "target_insert_watchpoint (0x%lx, %d, %d) = %ld\n", (unsigned long) addr, len, type, (unsigned long) retval); return retval; } static int debug_to_remove_watchpoint (CORE_ADDR addr, int len, int type) { int retval; retval = debug_target.to_insert_watchpoint (addr, len, type); fprintf_unfiltered (gdb_stdlog, "target_insert_watchpoint (0x%lx, %d, %d) = %ld\n", (unsigned long) addr, len, type, (unsigned long) retval); return retval; } static void debug_to_terminal_init (void) { debug_target.to_terminal_init (); fprintf_unfiltered (gdb_stdlog, "target_terminal_init ()\n"); } static void debug_to_terminal_inferior (void) { debug_target.to_terminal_inferior (); fprintf_unfiltered (gdb_stdlog, "target_terminal_inferior ()\n"); } static void debug_to_terminal_ours_for_output (void) { debug_target.to_terminal_ours_for_output (); fprintf_unfiltered (gdb_stdlog, "target_terminal_ours_for_output ()\n"); } static void debug_to_terminal_ours (void) { debug_target.to_terminal_ours (); fprintf_unfiltered (gdb_stdlog, "target_terminal_ours ()\n"); } static void debug_to_terminal_save_ours (void) { debug_target.to_terminal_save_ours (); fprintf_unfiltered (gdb_stdlog, "target_terminal_save_ours ()\n"); } static void debug_to_terminal_info (char *arg, int from_tty) { debug_target.to_terminal_info (arg, from_tty); fprintf_unfiltered (gdb_stdlog, "target_terminal_info (%s, %d)\n", arg, from_tty); } static void debug_to_kill (void) { debug_target.to_kill (); fprintf_unfiltered (gdb_stdlog, "target_kill ()\n"); } static void debug_to_load (char *args, int from_tty) { debug_target.to_load (args, from_tty); fprintf_unfiltered (gdb_stdlog, "target_load (%s, %d)\n", args, from_tty); } static int debug_to_lookup_symbol (char *name, CORE_ADDR *addrp) { int retval; retval = debug_target.to_lookup_symbol (name, addrp); fprintf_unfiltered (gdb_stdlog, "target_lookup_symbol (%s, xxx)\n", name); return retval; } static void debug_to_create_inferior (char *exec_file, char *args, char **env, int from_tty) { debug_target.to_create_inferior (exec_file, args, env, from_tty); fprintf_unfiltered (gdb_stdlog, "target_create_inferior (%s, %s, xxx, %d)\n", exec_file, args, from_tty); } static void debug_to_post_startup_inferior (ptid_t ptid) { debug_target.to_post_startup_inferior (ptid); fprintf_unfiltered (gdb_stdlog, "target_post_startup_inferior (%d)\n", PIDGET (ptid)); } static void debug_to_acknowledge_created_inferior (int pid) { debug_target.to_acknowledge_created_inferior (pid); fprintf_unfiltered (gdb_stdlog, "target_acknowledge_created_inferior (%d)\n", pid); } static int debug_to_insert_fork_catchpoint (int pid) { int retval; retval = debug_target.to_insert_fork_catchpoint (pid); fprintf_unfiltered (gdb_stdlog, "target_insert_fork_catchpoint (%d) = %d\n", pid, retval); return retval; } static int debug_to_remove_fork_catchpoint (int pid) { int retval; retval = debug_target.to_remove_fork_catchpoint (pid); fprintf_unfiltered (gdb_stdlog, "target_remove_fork_catchpoint (%d) = %d\n", pid, retval); return retval; } static int debug_to_insert_vfork_catchpoint (int pid) { int retval; retval = debug_target.to_insert_vfork_catchpoint (pid); fprintf_unfiltered (gdb_stdlog, "target_insert_vfork_catchpoint (%d)= %d\n", pid, retval); return retval; } static int debug_to_remove_vfork_catchpoint (int pid) { int retval; retval = debug_target.to_remove_vfork_catchpoint (pid); fprintf_unfiltered (gdb_stdlog, "target_remove_vfork_catchpoint (%d) = %d\n", pid, retval); return retval; } static int debug_to_follow_fork (int follow_child) { int retval = debug_target.to_follow_fork (follow_child); fprintf_unfiltered (gdb_stdlog, "target_follow_fork (%d) = %d\n", follow_child, retval); return retval; } static int debug_to_insert_exec_catchpoint (int pid) { int retval; retval = debug_target.to_insert_exec_catchpoint (pid); fprintf_unfiltered (gdb_stdlog, "target_insert_exec_catchpoint (%d) = %d\n", pid, retval); return retval; } static int debug_to_remove_exec_catchpoint (int pid) { int retval; retval = debug_target.to_remove_exec_catchpoint (pid); fprintf_unfiltered (gdb_stdlog, "target_remove_exec_catchpoint (%d) = %d\n", pid, retval); return retval; } static int debug_to_reported_exec_events_per_exec_call (void) { int reported_exec_events; reported_exec_events = debug_target.to_reported_exec_events_per_exec_call (); fprintf_unfiltered (gdb_stdlog, "target_reported_exec_events_per_exec_call () = %d\n", reported_exec_events); return reported_exec_events; } static int debug_to_has_exited (int pid, int wait_status, int *exit_status) { int has_exited; has_exited = debug_target.to_has_exited (pid, wait_status, exit_status); fprintf_unfiltered (gdb_stdlog, "target_has_exited (%d, %d, %d) = %d\n", pid, wait_status, *exit_status, has_exited); return has_exited; } static void debug_to_mourn_inferior (void) { debug_target.to_mourn_inferior (); fprintf_unfiltered (gdb_stdlog, "target_mourn_inferior ()\n"); } static int debug_to_can_run (void) { int retval; retval = debug_target.to_can_run (); fprintf_unfiltered (gdb_stdlog, "target_can_run () = %d\n", retval); return retval; } static void debug_to_notice_signals (ptid_t ptid) { debug_target.to_notice_signals (ptid); fprintf_unfiltered (gdb_stdlog, "target_notice_signals (%d)\n", PIDGET (ptid)); } static int debug_to_thread_alive (ptid_t ptid) { int retval; retval = debug_target.to_thread_alive (ptid); fprintf_unfiltered (gdb_stdlog, "target_thread_alive (%d) = %d\n", PIDGET (ptid), retval); return retval; } static void debug_to_find_new_threads (void) { debug_target.to_find_new_threads (); fputs_unfiltered ("target_find_new_threads ()\n", gdb_stdlog); } static void debug_to_stop (void) { debug_target.to_stop (); fprintf_unfiltered (gdb_stdlog, "target_stop ()\n"); } static void debug_to_rcmd (char *command, struct ui_file *outbuf) { debug_target.to_rcmd (command, outbuf); fprintf_unfiltered (gdb_stdlog, "target_rcmd (%s, ...)\n", command); } static struct symtab_and_line * debug_to_enable_exception_callback (enum exception_event_kind kind, int enable) { struct symtab_and_line *result; result = debug_target.to_enable_exception_callback (kind, enable); fprintf_unfiltered (gdb_stdlog, "target get_exception_callback_sal (%d, %d)\n", kind, enable); return result; } static struct exception_event_record * debug_to_get_current_exception_event (void) { struct exception_event_record *result; result = debug_target.to_get_current_exception_event (); fprintf_unfiltered (gdb_stdlog, "target get_current_exception_event ()\n"); return result; } static char * debug_to_pid_to_exec_file (int pid) { char *exec_file; exec_file = debug_target.to_pid_to_exec_file (pid); fprintf_unfiltered (gdb_stdlog, "target_pid_to_exec_file (%d) = %s\n", pid, exec_file); return exec_file; } static void setup_target_debug (void) { memcpy (&debug_target, &current_target, sizeof debug_target); current_target.to_open = debug_to_open; current_target.to_close = debug_to_close; current_target.to_attach = debug_to_attach; current_target.to_post_attach = debug_to_post_attach; current_target.to_detach = debug_to_detach; current_target.to_disconnect = debug_to_disconnect; current_target.to_resume = debug_to_resume; current_target.to_wait = debug_to_wait; current_target.to_fetch_registers = debug_to_fetch_registers; current_target.to_store_registers = debug_to_store_registers; current_target.to_prepare_to_store = debug_to_prepare_to_store; current_target.deprecated_xfer_memory = deprecated_debug_xfer_memory; current_target.to_files_info = debug_to_files_info; current_target.to_insert_breakpoint = debug_to_insert_breakpoint; current_target.to_remove_breakpoint = debug_to_remove_breakpoint; current_target.to_can_use_hw_breakpoint = debug_to_can_use_hw_breakpoint; current_target.to_insert_hw_breakpoint = debug_to_insert_hw_breakpoint; current_target.to_remove_hw_breakpoint = debug_to_remove_hw_breakpoint; current_target.to_insert_watchpoint = debug_to_insert_watchpoint; current_target.to_remove_watchpoint = debug_to_remove_watchpoint; current_target.to_stopped_by_watchpoint = debug_to_stopped_by_watchpoint; current_target.to_stopped_data_address = debug_to_stopped_data_address; current_target.to_region_size_ok_for_hw_watchpoint = debug_to_region_size_ok_for_hw_watchpoint; current_target.to_terminal_init = debug_to_terminal_init; current_target.to_terminal_inferior = debug_to_terminal_inferior; current_target.to_terminal_ours_for_output = debug_to_terminal_ours_for_output; current_target.to_terminal_ours = debug_to_terminal_ours; current_target.to_terminal_save_ours = debug_to_terminal_save_ours; current_target.to_terminal_info = debug_to_terminal_info; current_target.to_kill = debug_to_kill; current_target.to_load = debug_to_load; current_target.to_lookup_symbol = debug_to_lookup_symbol; current_target.to_create_inferior = debug_to_create_inferior; current_target.to_post_startup_inferior = debug_to_post_startup_inferior; current_target.to_acknowledge_created_inferior = debug_to_acknowledge_created_inferior; current_target.to_insert_fork_catchpoint = debug_to_insert_fork_catchpoint; current_target.to_remove_fork_catchpoint = debug_to_remove_fork_catchpoint; current_target.to_insert_vfork_catchpoint = debug_to_insert_vfork_catchpoint; current_target.to_remove_vfork_catchpoint = debug_to_remove_vfork_catchpoint; current_target.to_follow_fork = debug_to_follow_fork; current_target.to_insert_exec_catchpoint = debug_to_insert_exec_catchpoint; current_target.to_remove_exec_catchpoint = debug_to_remove_exec_catchpoint; current_target.to_reported_exec_events_per_exec_call = debug_to_reported_exec_events_per_exec_call; current_target.to_has_exited = debug_to_has_exited; current_target.to_mourn_inferior = debug_to_mourn_inferior; current_target.to_can_run = debug_to_can_run; current_target.to_notice_signals = debug_to_notice_signals; current_target.to_thread_alive = debug_to_thread_alive; current_target.to_find_new_threads = debug_to_find_new_threads; current_target.to_stop = debug_to_stop; current_target.to_rcmd = debug_to_rcmd; current_target.to_enable_exception_callback = debug_to_enable_exception_callback; current_target.to_get_current_exception_event = debug_to_get_current_exception_event; current_target.to_pid_to_exec_file = debug_to_pid_to_exec_file; } static char targ_desc[] = "Names of targets and files being debugged.\n\ Shows the entire stack of targets currently in use (including the exec-file,\n\ core-file, and process, if any), as well as the symbol file name."; static void do_monitor_command (char *cmd, int from_tty) { if ((current_target.to_rcmd == (void (*) (char *, struct ui_file *)) tcomplain) || (current_target.to_rcmd == debug_to_rcmd && (debug_target.to_rcmd == (void (*) (char *, struct ui_file *)) tcomplain))) { error ("\"monitor\" command not supported by this target.\n"); } target_rcmd (cmd, gdb_stdtarg); } void initialize_targets (void) { init_dummy_target (); push_target (&dummy_target); add_info ("target", target_info, targ_desc); add_info ("files", target_info, targ_desc); deprecated_add_show_from_set (add_set_cmd ("target", class_maintenance, var_zinteger, (char *) &targetdebug, "Set target debugging.\n\ When non-zero, target debugging is enabled. Higher numbers are more\n\ verbose. Changes do not take effect until the next \"run\" or \"target\"\n\ command.", &setdebuglist), &showdebuglist); add_setshow_boolean_cmd ("trust-readonly-sections", class_support, &trust_readonly, "\ Set mode for reading from readonly sections.", "\ Show mode for reading from readonly sections.", "\ When this mode is on, memory reads from readonly sections (such as .text)\n\ will be read from the object file instead of from the target. This will\n\ result in significant performance improvement for remote targets.", "\ Mode for reading from readonly sections is %s.", NULL, NULL, &setlist, &showlist); add_com ("monitor", class_obscure, do_monitor_command, "Send a command to the remote monitor (remote targets only)."); target_dcache = dcache_init (); } ```
```toml [build-system] build-backend = "hatchling.build" requires = [ "hatch-vcs", "hatchling", ] [project] name = "prettytable" description = "A simple Python library for easily displaying tabular data in a visually appealing ASCII table format" readme = "README.md" license = { text = "BSD (3 clause)" } maintainers = [ { name = "Jazzband" }, ] authors = [ { name = "Luke Maurits", email = "luke@maurits.id.au" }, ] requires-python = ">=3.8" classifiers = [ "Programming Language :: Python", "Programming Language :: Python :: 3 :: Only", "Programming Language :: Python :: 3.8", "Programming Language :: Python :: 3.9", "Programming Language :: Python :: 3.10", "Programming Language :: Python :: 3.11", "Programming Language :: Python :: 3.12", "Programming Language :: Python :: 3.13", "Programming Language :: Python :: Implementation :: CPython", "Programming Language :: Python :: Implementation :: PyPy", "Topic :: Text Processing", "Typing :: Typed", ] dynamic = [ "version", ] dependencies = [ "wcwidth", ] optional-dependencies.tests = [ "pytest", "pytest-cov", "pytest-lazy-fixtures", ] urls.Changelog = "path_to_url" urls.Homepage = "path_to_url" urls.Source = "path_to_url" [tool.hatch] version.source = "vcs" [tool.hatch.version.raw-options] local_scheme = "no-local-version" [tool.ruff] fix = true lint.select = [ "C4", # flake8-comprehensions "E", # pycodestyle errors "EM", # flake8-errmsg "F", # pyflakes errors "I", # isort "ISC", # flake8-implicit-str-concat "LOG", # flake8-logging "PGH", # pygrep-hooks "RUF100", # unused noqa (yesqa) "UP", # pyupgrade "W", # pycodestyle warnings "YTT", # flake8-2020 ] lint.extend-ignore = [ "E203", # Whitespace before ':' "E221", # Multiple spaces before operator "E226", # Missing whitespace around arithmetic operator "E241", # Multiple spaces after ',' ] lint.isort.known-first-party = [ "prettytable", ] lint.isort.required-imports = [ "from __future__ import annotations", ] [tool.pyproject-fmt] max_supported_python = "3.13" ```
```html <!DOCTYPE html> <!-- Forty by HTML5 UP html5up.net | @ajlkn Free for personal and commercial use under the CCA 3.0 license (html5up.net/license) --> <html> {{> head}} <body> {{> header}} <section id="banner" class="style2"> <div class="inner"> <span class="image"> <img src="{{ site.baseurl }}/{{ page.image }}" alt=""> </span> <header class="major"> <h1>{{ page.title }}</h1> </header> <div class="content"> {{ page.description }} </div> </div> </section> {{ content }} {{> footer}} </body> </html> ```
```html <html lang="en"> <head> <title>fgetpos - Untitled</title> <meta http-equiv="Content-Type" content="text/html"> <meta name="description" content="Untitled"> <meta name="generator" content="makeinfo 4.8"> <link title="Top" rel="start" href="index.html#Top"> <link rel="up" href="Stdio.html#Stdio" title="Stdio"> <link rel="prev" href="fgetc.html#fgetc" title="fgetc"> <link rel="next" href="fgets.html#fgets" title="fgets"> <link href="path_to_url" rel="generator-home" title="Texinfo Homepage"> <meta http-equiv="Content-Style-Type" content="text/css"> <style type="text/css"><!-- pre.display { font-family:inherit } pre.format { font-family:inherit } pre.smalldisplay { font-family:inherit; font-size:smaller } pre.smallformat { font-family:inherit; font-size:smaller } pre.smallexample { font-size:smaller } pre.smalllisp { font-size:smaller } span.sc { font-variant:small-caps } span.roman { font-family:serif; font-weight:normal; } span.sansserif { font-family:sans-serif; font-weight:normal; } --></style> </head> <body> <div class="node"> <p> <a name="fgetpos"></a> Next:&nbsp;<a rel="next" accesskey="n" href="fgets.html#fgets">fgets</a>, Previous:&nbsp;<a rel="previous" accesskey="p" href="fgetc.html#fgetc">fgetc</a>, Up:&nbsp;<a rel="up" accesskey="u" href="Stdio.html#Stdio">Stdio</a> <hr> </div> <h3 class="section">4.11 <code>fgetpos</code>&mdash;record position in a stream or file</h3> <p><a name="index-fgetpos-179"></a><a name="index-g_t_005ffgetpos_005fr-180"></a><strong>Synopsis</strong> <pre class="example"> #include &lt;stdio.h&gt; int fgetpos(FILE *restrict <var>fp</var>, fpos_t *restrict <var>pos</var>); int _fgetpos_r(struct _reent *<var>ptr</var>, FILE *restrict <var>fp</var>, fpos_t *restrict <var>pos</var>); </pre> <p><strong>Description</strong><br> Objects of type <code>FILE</code> can have a &ldquo;position&rdquo; that records how much of the file your program has already read. Many of the <code>stdio</code> functions depend on this position, and many change it as a side effect. <p>You can use <code>fgetpos</code> to report on the current position for a file identified by <var>fp</var>; <code>fgetpos</code> will write a value representing that position at <code>*</code><var>pos</var>. Later, you can use this value with <code>fsetpos</code> to return the file to this position. <p>In the current implementation, <code>fgetpos</code> simply uses a character count to represent the file position; this is the same number that would be returned by <code>ftell</code>. <pre class="sp"> </pre> <strong>Returns</strong><br> <code>fgetpos</code> returns <code>0</code> when successful. If <code>fgetpos</code> fails, the result is <code>1</code>. Failure occurs on streams that do not support positioning; the global <code>errno</code> indicates this condition with the value <code>ESPIPE</code>. <pre class="sp"> </pre> <strong>Portability</strong><br> <code>fgetpos</code> is required by the ANSI C standard, but the meaning of the value it records is not specified beyond requiring that it be acceptable as an argument to <code>fsetpos</code>. In particular, other conforming C implementations may return a different result from <code>ftell</code> than what <code>fgetpos</code> writes at <code>*</code><var>pos</var>. <p>No supporting OS subroutines are required. <pre class="sp"> </pre> </body></html> ```
Rudolf Münger (1862–1929) was a Swiss painter. References 19th-century Swiss painters Swiss male painters 20th-century Swiss painters 1862 births 1929 deaths 19th-century Swiss male artists 20th-century Swiss male artists
María Mercedes Corral Aguilar (born 24 September 1947) is a Mexican politician from the National Action Party. From 2006 to 2009 she served as Deputy of the LX Legislature of the Mexican Congress representing Sonora, and previously served in the LVII Legislatur of the Congress of Sonora. References 1947 births Living people Politicians from Sonora Women members of the Chamber of Deputies (Mexico) National Action Party (Mexico) politicians 21st-century Mexican politicians 21st-century Mexican women politicians Academic staff of Universidad de Sonora Universidad de Sonora alumni Members of the Congress of Sonora Deputies of the LX Legislature of Mexico Members of the Chamber of Deputies (Mexico) for Sonora
Set You Free or Set U Free may refer to: Albums Set You Free (album), by Gary Allan, 2013 Set You Free, by Chisel, 1997 Set You Free, by Nomos, 1997 Set You Free, by Tammy Trent, 2000 Set You Free: Gene Clark in the Byrds 1964–1973, by Gene Clark, 2004 Songs "Set You Free" (N-Trance song), 1995 "Set You Free" (The Black Keys song), 2003 "Set U Free" (Keshia Chanté song), 2011 "Set U Free" (Planet Soul song), 1995 "Set You Free", by Ol' Skool, 1997 "Set You Free", by Poison from Crack a Smile... and More!, 2000 "Set You Free", by Wale from Wow... That's Crazy, 2019 See also "I'll Set You Free", a 1988 song by The Bangles Love Will Set You Free (disambiguation) "Set You Free This Time", a 1966 song by The Byrds Set Me Free (disambiguation)
Linda Tsungirirai Masarira is a Zimbabwean politician who served as a spokesperson for one of the smaller faction of the opposition parties in Zimbabwe, MDC-T led by Thokozani Khupe. Linda Masarira is also a human rights defender who is known for her role in advocating for democracy, equality, gender balance, women and girl child rights, inclusion and economic and political freedom for marginalized groups of society. She has formed her own political party known as LEAD. Masarira made headlines when she blasted sick Marry Mubaiwa who used to be a wife of a professional footballer Shingi Kawondera after their break up, Mary Mubaiwa wedded the then Army General Constantino Guvheya Nyikadzino Chiwenga who is the current serving vice president of Zimbabwe. Mary and Chiwenga broke up. Background Linda Masarira grew up in Harare where she was based before moving to Bulawayo, Hwange and Mutare where she was employed as a train woman. She returned to Harare in 2015 and then formed the Zimbabwe Women In Politics Alliance. Human rights activism After a series of demonstrations, petitions and protests for human rights violations by the Government of Zimbabwe during the Mugabe regime which she organised, she was incarcerated for more than 80 days in Chikurubhi Maximum Prison for challenging the government to respect humanity. During her days of incarceration, Masarira mobilised fellow women prisoners and led an inmate protest against poor conditions that women were facing including lack of sanitary pads and proper access to medical services. Because of her activism, Masarira was brutalised and moved to a male prison where she was placed on solitary confinement until she was finally granted bail by a High court order in September 2016. Linda Masarira organised a series of several successful campaigns including the “Bring back our women from Kuwait” campaign where she took a leading role in petitioning the government of Zimbabwe and the Kuwaiti Embassy to expedite the repatriation process to the stranded Zimbabwean women who had fallen victim to human trafficking. Following this campaign, the government of Zimbabwe later came up with an expatriation plan for all trafficked persons outside Zimbabwe which saw more than 200 women victims coming back home. Linda Masarira and her 5 other allies including Lynette Tendai Mudehwe of Zimbabwe Activists Alliance launched the Occupy Africa Unity Square Campaign in June 2016, which was organised to run for 16 days. The campaign was crushed by Zimbabwe Republic Police who then arrested fellow activist Patson Dzamara and several other campaign members for made up robbery charges. Linda then got arrested on a charge of obstructing the course of justice. During her time at National Railways of Zimbabwe and Systems Technology, Linda was also involved in trade unionism where she mobilised other employees to fight for their labour rights, which got her fired from the organisations. She said challenges she faced as a young Zimbabwean is what shaped her opinions and these challenges include gender and justice, labor and justice as well as social injustice. Political career Masarira is a former member of the executive management committee of the People's Democratic Party (PDP) responsible for recruitment and mobilization. She is the current spokesperson of the Movement for Democratic Change (MDC-T) led by President Dr Thokozani Khupe. In June 2018, Linda successfully registered to contest for the Harare Central parliamentary seat in the 2018 elections driven by her gender equality and conviction that she can make a difference for all workers facing labour injustice in Zimbabwe. Controversy In May 2015, Linda appeared before the Mutare magistrate Annia Ndiraya for allegedly insulting the then President of Zimbabwe Robert Mugabe by referring to him as shit of which she denied charges citing that she was framed. She was remanded out of custody on free bail. 2016 in December, Masarira reportedly said "Ndebele people are cowards and cry-babies" at a Crisis in Zimbabwe Coalition conference which was held in Harare. The statement went viral on social media and she was accused for tribalism. Masarira then clarified saying that she meant most Ndebele people were reluctant to participate in efforts to confront the Mugabe regime in fighting for their rights. In 2017, Linda Masarira sued top government officials including the current president of Zimbabwe Emmerson Mnangagwa who was the Vice President as well as the then Home Affairs minister Ignatius Chombo, ZRP commissioner Augustine Chihuri and prison chief Paradzai Zimondi. She filed a $150 000 lawsuit for unlawful detention over an outstanding warrant of arrest. In March 2018 she filed papers at the constitutional court challenging the legitimacy of President Emmerson Mnangagwa who ascended into power after 2017 Zimbabwean coup d'état in November 2017. During the 2018 Workers Day celebrations, Linda Masarira was barred from entering Zimbabwe Congress of Trade Unions VIP tent, Peter Mutasa the ZCTU president said they barred MDC-T spokesperson from sitting in the VIP tent because she wanted to disrupt the Workers’ Day celebrations. In August 2019, she questioned Julius Malema's involvement in Zimbabwe's politics and declared that "Zimbabwe is a sovereign nation and not an extension of South Africa". She urged him to facilitate the Covid treatment for foreign nationals in South Africa as well as the issuing of Visa documents instead of meddling in Zimbabwean politics. Fadzai Mahere questioned this move by her which led to a spat on Twitter. Positions held Founder and national coordinator for Zimbabwe Women in Politics Alliance. National Coordinator for the Young African Leadership Forum (Zimbabwean Chapter). Founder and Chairperson of the Association of Railways Terminated Employees. Chairperson of the Revolutionary Freedom Fighters. Chairperson of STAR fellowship cohort 3. FES Alumni. Former President of the Trainmen workers Union (2008–2013). Awards and recognition Zimrights Female Human Rights Defender of the year 2016 Giraffe Award for Human Rights Fortune Magazine 2016 5th Most Powerful Woman in the World Phenomenal African Woman October 2017 References 1982 births Living people Zimbabwean politicians Zimbabwean women activists Zimbabwean human rights activists Women human rights activists
```go // Unless explicitly stated otherwise all files in this repository are licensed // This product includes software developed at Datadog (path_to_url package ec2 import ( "context" "fmt" "time" "github.com/DataDog/datadog-agent/pkg/config" httputils "github.com/DataDog/datadog-agent/pkg/util/http" "github.com/DataDog/datadog-agent/pkg/util/log" ) var ( imdsInstanceID = "/instance-id" imdsHostname = "/hostname" // This is used in ec2_tags.go which is behind the 'ec2' build flag imdsTags = "/tags/instance" //nolint:unused imdsIPv4 = "/public-ipv4" imdsNetworkMacs = "/network/interfaces/macs" ) func getToken(ctx context.Context) (string, time.Time, error) { tokenLifetime := time.Duration(config.Datadog().GetInt("ec2_metadata_token_lifetime")) * time.Second // Set the local expiration date before requesting the metadata endpoint so the local expiration date will always // expire before the expiration date computed on the AWS side. The expiration date is set minus the renewal window // to ensure the token will be refreshed before it expires. expirationDate := time.Now().Add(tokenLifetime - tokenRenewalWindow) res, err := httputils.Put(ctx, tokenURL, map[string]string{ "X-aws-ec2-metadata-token-ttl-seconds": fmt.Sprintf("%d", int(tokenLifetime.Seconds())), }, nil, config.Datadog().GetDuration("ec2_metadata_timeout")*time.Millisecond, config.Datadog()) if err != nil { return "", time.Now(), err } return res, expirationDate, nil } func getMetadataItemWithMaxLength(ctx context.Context, endpoint string, forceIMDSv2 bool) (string, error) { result, err := getMetadataItem(ctx, endpoint, forceIMDSv2) if err != nil { return result, err } maxLength := config.Datadog().GetInt("metadata_endpoints_max_hostname_size") if len(result) > maxLength { return "", fmt.Errorf("%v gave a response with length > to %v", endpoint, maxLength) } return result, err } func getMetadataItem(ctx context.Context, endpoint string, forceIMDSv2 bool) (string, error) { if !config.IsCloudProviderEnabled(CloudProviderName) { return "", fmt.Errorf("cloud provider is disabled by configuration") } return doHTTPRequest(ctx, metadataURL+endpoint, forceIMDSv2) } // UseIMDSv2 returns true if the agent should use IMDSv2 func UseIMDSv2(forceIMDSv2 bool) bool { return config.Datadog().GetBool("ec2_prefer_imdsv2") || forceIMDSv2 } func doHTTPRequest(ctx context.Context, url string, forceIMDSv2 bool) (string, error) { source := metadataSourceIMDSv1 headers := map[string]string{} if UseIMDSv2(forceIMDSv2) { tokenValue, err := token.Get(ctx) if err != nil { if forceIMDSv2 { return "", fmt.Errorf("Could not fetch token from IMDSv2") } log.Warnf("ec2_prefer_imdsv2 is set to true in the configuration but the agent was unable to proceed: %s", err) } else { headers["X-aws-ec2-metadata-token"] = tokenValue if !forceIMDSv2 { source = metadataSourceIMDSv2 } } } res, err := httputils.Get(ctx, url, headers, time.Duration(config.Datadog().GetInt("ec2_metadata_timeout"))*time.Millisecond, config.Datadog()) // We don't want to register the source when we force imdsv2 if err == nil && !forceIMDSv2 { setCloudProviderSource(source) } return res, err } ```
```go package ca import ( "crypto/ecdsa" "crypto/elliptic" "crypto/rand" "crypto/x509" "crypto/x509/pkix" "encoding/pem" "math/big" "os" "time" "github.com/cortexproject/cortex/pkg/util/runutil" ) type CA struct { key *ecdsa.PrivateKey cert *x509.Certificate serial *big.Int } func New(name string) *CA { key, err := ecdsa.GenerateKey(elliptic.P521(), rand.Reader) if err != nil { panic(err) } return &CA{ key: key, cert: &x509.Certificate{ SerialNumber: big.NewInt(1), Subject: pkix.Name{ Organization: []string{name}, }, NotBefore: time.Now(), NotAfter: time.Now().Add(time.Hour * 24 * 180), KeyUsage: x509.KeyUsageKeyEncipherment | x509.KeyUsageDigitalSignature | x509.KeyUsageCertSign, ExtKeyUsage: []x509.ExtKeyUsage{x509.ExtKeyUsageServerAuth, x509.ExtKeyUsageClientAuth}, BasicConstraintsValid: true, IsCA: true, }, serial: big.NewInt(2), } } func writeExclusivePEMFile(path, marker string, mode os.FileMode, data []byte) (err error) { f, err := os.OpenFile(path, os.O_WRONLY|os.O_CREATE|os.O_EXCL, mode) if err != nil { return err } defer runutil.CloseWithErrCapture(&err, f, "write pem file") if err := pem.Encode(f, &pem.Block{Type: marker, Bytes: data}); err != nil { return err } return nil } func (ca *CA) WriteCACertificate(path string) error { derBytes, err := x509.CreateCertificate(rand.Reader, ca.cert, ca.cert, ca.key.Public(), ca.key) if err != nil { return err } return writeExclusivePEMFile(path, "CERTIFICATE", 0644, derBytes) } func (ca *CA) WriteCertificate(template *x509.Certificate, certPath string, keyPath string) error { key, err := ecdsa.GenerateKey(elliptic.P521(), rand.Reader) if err != nil { return err } keyBytes, err := x509.MarshalECPrivateKey(key) if err != nil { return err } if err := writeExclusivePEMFile(keyPath, "PRIVATE KEY", 0600, keyBytes); err != nil { return err } template.IsCA = false template.NotBefore = time.Now() if template.NotAfter.IsZero() { template.NotAfter = time.Now().Add(time.Hour * 24 * 180) } template.SerialNumber = ca.serial.Add(ca.serial, big.NewInt(1)) derBytes, err := x509.CreateCertificate(rand.Reader, template, ca.cert, key.Public(), ca.key) if err != nil { return err } return writeExclusivePEMFile(certPath, "CERTIFICATE", 0644, derBytes) } ```
"Requiem" is British Europop duo London Boys' first hit single, released on 28 November 1988 from their debut album, The Twelve Commandments of Dance (1989). The single was written and produced by Ralf René Maué. The single peaked at 4 in the United Kingdom, No. 8 in Ireland, and No. 11 in Austria. Critical reception According to James Masterton, "Requiem " is "the quintessential bubblegum Euro-hit, complete with bouncing bassline, a semi-rapped verse and the inevitable multi-tracked chorus". Retrospectively, in a 2015 review of the parent album, the Pop Rescue website considered "Requiem" "a wonderful dancey, uplifting song", with "catchy" verses composed of a "throbbing synth bass", the repeated sentence "Never gonna get enough" and spoken words, a feature recalling Pet Shop Boys. Track listings 7-inch single A. "Requiem" (Hamburg Edit) B. "The Midi Dance" UK 12-inch single A1. "Requiem" (Hamburg Mix) B1. "Requiem" (Hamburg Edit) B2. "The Midi Dance" German mini-CD single 1 "Requiem" (Special UK-Mix) – 8:05 "My Love" – 3:05 "Dance Dance Dance" – 3:54 German mini-CD single 2 "Requiem" (Hamburg Edit) – 4:12 "Requiem" (London Remix) – 8:04 "Requiem" (Hamburg Mix) – 7:34 Charts Weekly charts Year-end charts Certifications References 1988 songs London Boys songs Songs written by Ralf René Maué 1988 singles Warner Music Group singles Atlantic Records singles Teldec singles
Julio Salgado (born September 1, 1983) is a gay Mexican-born artist who grew up in Long Beach, California. Through the use of art, Salgado has become a well-known activist within the DREAM Act movement. Salgado uses his art to empower undocumented and queer people by telling their story and putting a human face to the issue. He has worked on various art projects that address anti-immigrant discourse, the issues of what it means to be undocumented, and what it means to be undocu-queer. One of his more well-known projects is a series of satire images addressing American Apparel’s use of a farm worker in one of their ads in the summer of 2011. Early life and education Salgado was born on September 1, 1983, in Ensenada, Mexico. When Salgado’s younger sister was diagnosed with a life-threatening kidney disease in 1995, Salgado and his family emigrated to the United States. After being advised by the doctor that a return to Mexico would result in his sister's death, Salgado’s family decided to remain in the United States. The Salgado family overstayed their visas and Salgado was left to live under an undocumented immigrant status in the United States. Salgado attended David Starr Jordan High School in Long Beach, California and graduated from the class of 2001. Because Salgado was an undocumented student, he did not qualify for federal financial aid. After high school Salgado took on various low-paying jobs in order to pay his way through college. In 2010 he obtained a Bachelor of Arts in Journalism from California State University, Long Beach. He began his artistic career as the editorial cartoonist for the Daily 49er newspaper of CSU, Long Beach. Salgado faced the challenges of being both undocumented and gay, forcing him to "come out" twice. Growing up in a traditional heterosexual family Salgado found being queer a much more difficult challenge than being undocumented. During his high school and college years, afraid of insults and rejection, he maintained his queer identity hidden and only felt safe revealing his undocumented status since many of those around him faced the same struggle. Salgado’s mother was the first person to know about his queer identity. In the 8th grade, he began documenting intimate sketches and writings in a personal journal, expressing his feelings for other boys. After his mother stumbled upon this journal and read his entries, he had no choice but to confess his queer identity. To Salgado’s surprise, his mother was very understanding and accepted him regardless. Salgado has made his queer identity and undocumented status public by speaking on the need to humanize both issues. Career In 2010, a group of undocumented students protested in front of the Hart Senate Building in Washington, D.C., demanding the passage of the Federal DREAM Act. Julio’s activist role emerged after coming across the photograph in the Washington Post of Diana Yael Martinez, an undocumented student who was being arrested after refusing to leave the sit-in at the senate building. His anger with such treatment ignited the illustrations that were later used in the DREAM Act movement. He states, “I channeled all that anger into my sketchpad and I began to draw.”. Although Julio's use of art began as a refuge that saved him from his hardships, DREAM Act activists soon found themselves using them as weapons for rallies and campaigns. Salgado links his undocumented and queer identity in most of his artwork in order to put a face to the issue. Salgado explains, “In the past, one could see articles or interviews with a hidden face or an anonymous name. That would dehumanize the issue and by us coming out and saying we’re undocumented and unafraid, we’re putting a face to it." As a result, he has worked on multiple projects that give young undocumented and undocumented queers a chance to come out of the shadows and share their experiences. Salgado uses his art as a form of activism. He considers himself an "artivist". Projects I am Undocu-Queer! Salgado began working on the “I am Undocu-Queer!” art project in 2012. With this project Salgado, in conjunction with the Queer Undocumented Immigrant Project (QUIP), “aims to give … undocumented queers more of a presence in the discussion of migrant rights”. The illustrations consist of images of actual young undocumented queer people who have chosen to come out of the shadows to define what it means to be both undocumented and queer. Undocumented Apparel In May 2012 American Apparel faced criticism due to a magazine ad that was published in the Summer of 2011. The ad features a young white female model linking arms with a dark-skinned Latino farm worker. The ad identifies the models as “Robin a USC student, studying Public Relations, with Raul, a California farmer in Denim and Chambray.” In an interview with ColorLines Salgado expressed his reaction: “My first thought was, this is so unrealistic…. what exactly is it that American Apparel is trying to say here? Is it, ‘See? There’s unity? We like you!’ That's not how it happens, and American Apparel has always used people, especially women, as objects. Were they just doing this to get on the undocumented wagon?” Salgado created the “Undocumented Apparel” series as a reaction to the original ad by drawing real undocumented people that are part of his life. The images of the people are also “accompanied by an acidic quote contrasting their lives to American Apparel’s upwardly mobile clientele.” Like much of Salgado's previous work, the images turned into a form of homage for the people he knows. Dreamers Adrift In 2010 Salgado along with four friends – Jesus Iñiguez, Fernando Romero, and Deisy Hernandez – launched the nationwide media project DREAMers Adrift. The project features a series of videos titled “Undocumented and Awkward” that demonstrate through the use of comedy the predicaments in which numerous of undocumented students find themselves in throughout and after college. Salgado states that many of the situations that are acted out throughout the skits are situations that he has personally found himself in. “For My Dreamers” Salgado dedicates much of his art to the undocumented activists who are in the forefront of the DREAM Act movement. The images include messages in support of the DREAM Act, opposition to anti-immigrant bills, as well as messages of encouragement for undocumented people. Salgado also uses his art in order to raise awareness of deportation cases and the ways that people can take action in order to stop them. Much of his artwork is used in rallies all throughout the United States in support of the DREAM Act. "I Exist" The “I Exist” collection specifically addresses the DREAM Act movement. The images in this collection demand the anti-immigrant discourse in mainstream media to humanize the language and treatment aimed towards undocumented youth. Salgado declares: “The language that anti-immigrant folks have used [aims to]…erase our identities or erase the fact that we exist here. So I wanted with my artwork kind of to say, ‘hey listen, I exist,’ [and] it's almost like a scream." References 1983 births Living people Mexican artists Artists from Baja California Immigrant rights activists Artists from Long Beach, California People from Ensenada, Baja California American gay artists Queer artists Queer men
```yaml apiVersion: release-notes/v2 kind: bug-fix area: security issue: - path_to_url releaseNotes: - | **Fixed** an issue preventing istio-proxy to access root ca when automountServiceAccountToken is false and PILOT_CERT_PROVIDER is kubernetes. **Deprecated** using PILOT_CERT_PROVIDER kubernetes for kubernetes versions less than 1.20. ```
```php <?php declare(strict_types=1); use PhpOffice\PhpSpreadsheet\Calculation\Information\ExcelError; return [ [ '93502.0563713182121-65794.6618967782119j', '12.34+5.67j', ], [ ExcelError::NAN(), 'Invalid Complex Number', ], [ '-13.2772126767962807+9.90030162194353525i', '3.5+2.5i', ], [ '8.95433538452066202+13.9201408750362033i', '3.5+i', ], [ '16.5728246710573161', '3.5', ], [ '8.95433538452066202-13.9201408750362033i', '3.5-i', ], [ '-13.2772126767962807-9.90030162194353525i', '3.5-2.5i', ], [ '-1.23622919885634208+0.703325178113534826i', '1+2.5i', ], [ '0.833730025131149049+0.988897705762865096i', '1+i', ], [ '1.54308063481524378', '1', ], [ '0.833730025131149049-0.988897705762865096i', '1-i', ], [ '-1.23622919885634208-0.703325178113534826i', '1-2.5i', ], [ '-0.801143615546933715', '2.5i', ], [ '0.540302305868139717', 'i', ], [ '1', '0', ], [ '0.540302305868139717', '-i', ], [ '-0.801143615546933715', '-2.5i', ], [ '-1.23622919885634208-0.703325178113534826i', '-1+2.5i', ], [ '0.833730025131149049-0.988897705762865096i', '-1+i', ], [ '1.54308063481524378', '-1', ], [ '0.833730025131149049+0.988897705762865096i', '-1-i', ], [ '-1.23622919885634208+0.703325178113534826i', '-1-2.5i', ], [ '-13.2772126767962807-9.90030162194353525i', '-3.5+2.5i', ], [ '8.95433538452066202-13.9201408750362033i', '-3.5+i', ], [ '16.5728246710573161', '-3.5', ], [ '8.95433538452066202+13.9201408750362033i', '-3.5-i', ], [ '-13.2772126767962807+9.90030162194353525i', '-3.5-2.5i', ], [ '10.0676619957777658', '3', ], ]; ```
Matondo is a surname. Notable people with the surname include: Rabbi Matondo (born 2000), Welsh footballer Rosalie Matondo (born 1963), Republic of the Congo agronomist Sita-Taty Matondo (born 1984), Canadian soccer player See also Jeanvion Yulu-Matondo (born 1986), Belgian footballer Surnames of Republic of the Congo origin
```ruby # frozen_string_literal: true class RenameBudgetToBudgetAmmount < ActiveRecord::Migration[5.2] def change rename_column :decidim_budgets_projects, :budget, :budget_amount end end ```
```kotlin package wangdaye.com.geometricweather.theme.compose.day import androidx.compose.ui.graphics.Color val day_md_theme_light_primary = Color(0xFF205daf) val day_md_theme_light_onPrimary = Color(0xFFffffff) val day_md_theme_light_primaryContainer = Color(0xFFd6e3ff) val day_md_theme_light_onPrimaryContainer = Color(0xFF001b3f) val day_md_theme_light_secondary = Color(0xFF00677e) val day_md_theme_light_onSecondary = Color(0xFFffffff) val day_md_theme_light_secondaryContainer = Color(0xFFb1ebff) val day_md_theme_light_onSecondaryContainer = Color(0xFF001f28) val day_md_theme_light_tertiary = Color(0xFF775a00) val day_md_theme_light_onTertiary = Color(0xFFffffff) val day_md_theme_light_tertiaryContainer = Color(0xFFffdf8e) val day_md_theme_light_onTertiaryContainer = Color(0xFF251a00) val day_md_theme_light_error = Color(0xFFB3261E) val day_md_theme_light_errorContainer = Color(0xFFF9DEDC) val day_md_theme_light_onError = Color(0xFFFFFFFF) val day_md_theme_light_onErrorContainer = Color(0xFF410E0B) val day_md_theme_light_background = Color(0xFFfdfbff) val day_md_theme_light_onBackground = Color(0xFF1b1b1d) val day_md_theme_light_surface = Color(0xFFfdfbff) val day_md_theme_light_onSurface = Color(0xFF1b1b1d) val day_md_theme_light_surfaceVariant = Color(0xFFEFF4F8) val day_md_theme_light_onSurfaceVariant = Color(0xFF49454F) val day_md_theme_light_outline = Color(0x10000000) val day_md_theme_light_inverseOnSurface = Color(0xFFf2f0f4) val day_md_theme_light_inverseSurface = Color(0xFF2f3033) val day_md_theme_light_inversePrimary = Color(0xFFa8c7ff) val day_md_theme_light_shadow = Color(0xFF000000) ```
ECMAScript is a JavaScript standard developed by Ecma International. Since 2015, major versions have been published every June. ECMAScript 2023, the 14th and current version, was released in June 2023. Versions In June 2004, Ecma International published ECMA-357 standard, defining an extension to ECMAScript, known as ECMAScript for XML (E4X). Ecma also defined a "Compact Profile" for ECMAScript – known as ES-CP, or ECMA 327 – that was designed for resource-constrained devices, which was withdrawn in 2015. 4th Edition (abandoned) The proposed fourth edition of ECMA-262 (ECMAScript 4 or ES4) would have been the first major update to ECMAScript since the third edition was published in 1999. The specification (along with a reference implementation) was originally targeted for completion by October 2008. The first draft was dated February 1999. An overview of the language was released by the working group on 23 October 2007. By August 2008, the ECMAScript 4th edition proposal had been scaled back into a project code named ECMAScript Harmony. Features under discussion for Harmony at the time included: classes, a module system, optional type annotations and static typing, probably using a structural type system, generators and iterators, destructuring assignment, and algebraic data types. The intent of these features was partly to better support programming in the large, and to allow sacrificing some of the script's ability to be dynamic to improve performance. For example, Tamarin – the virtual machine for ActionScript, developed and open-sourced by Adobe – has just-in-time compilation (JIT) support for certain classes of scripts. In addition to introducing new features, some ES3 bugs were proposed to be fixed in edition 4. These fixes and others, and support for JSON encoding/decoding, have been folded into the ECMAScript, 5th Edition specification. Work started on Edition 4 after the ES-CP (Compact Profile) specification was completed, and continued for approximately 18 months where slow progress was made balancing the theory of Netscape's JavaScript 2 specification with the implementation experience of Microsoft's JScript .NET. After some time, the focus shifted to the ECMAScript for XML (E4X) standard. The update has not been without controversy. In late 2007, a debate between Eich, later the Mozilla Foundation's CTO, and Chris Wilson, Microsoft's platform architect for Internet Explorer, became public on a number of blogs. Wilson cautioned that because the proposed changes to ECMAScript made it backwards incompatible in some respects to earlier versions of the language, the update amounted to "breaking the Web", and that stakeholders who opposed the changes were being "hidden from view". Eich responded by stating that Wilson seemed to be "repeating falsehoods in blogs" and denied that there was attempt to suppress dissent and challenged critics to give specific examples of incompatibility. He pointed out that Microsoft Silverlight and Adobe AIR rely on C# and ActionScript 3 respectively, both of which are larger and more complex than ECMAScript Edition 3. 5th Edition – ECMAScript 2009 Yahoo, Microsoft, Google, and other 4th edition dissenters formed their own subcommittee to design a less ambitious update of ECMAScript 3, tentatively named ECMAScript 3.1. This edition would focus on security and library updates, with a large emphasis on compatibility. After the aforementioned public sparring, the ECMAScript 3.1 and ECMAScript 4 teams agreed on a compromise: the two editions would be worked on, in parallel, with coordination between the teams to ensure that ECMAScript 3.1 remains a strict subset of ECMAScript 4 in both semantics and syntax. However, the differing philosophies in each team resulted in repeated breakages of the subset rule, and it remained doubtful that the ECMAScript 4 dissenters would ever support or implement ECMAScript 4 in the future. After over a year since the disagreement over the future of ECMAScript within the Ecma Technical Committee 39, the two teams reached a new compromise in July 2008: Brendan Eich announced that Ecma TC39 would focus work on the ECMAScript 3.1 (later renamed to ECMAScript, 5th Edition) project with full collaboration of all parties, and vendors would target at least two interoperable implementations by early 2009. In April 2009, Ecma TC39 published the "final" draft of the 5th edition and announced that testing of interoperable implementations was expected to be completed by mid-July. On December 3, 2009, ECMA-262 5th edition was published. Additions include JSON, String.trim() to easily remove whitespaces surrounding a string (" example " to "example"), String.charAt() to return a single character from a given position in a string, and Array.isArray(). A comma after the final pair of values in an object (var example = { "property1":"value1", "property2":"value2", }) also no longer causes a syntax error. 6th Edition – ECMAScript 2015 The 6th edition, ECMAScript 6 (ES6) and later renamed to ECMAScript 2015, was finalized in June 2015. This update adds significant new syntax for writing complex applications, including class declarations (class Foo { ... } ), ES6 modules like import * as moduleName from "..."; export const Foo, but defines them semantically in the same terms as ECMAScript 5 strict mode. Other new features include iterators and for...of loops, Python-style generators, arrow function expression (() => {...} ), let keyword for local declarations, const keyword for constant local declarations, binary data, typed arrays, new collections (maps, sets and WeakMap), promises, number and math enhancements, reflection, proxies (metaprogramming for virtual objects and wrappers) and template literals using backticks (`) for multi-line strings without escape characters. The complete list is extensive. As the first "ECMAScript Harmony" specification, it is also known as "ES6 Harmony". 7th Edition – ECMAScript 2016 The 7th edition, or ECMAScript 2016, was finalized in June 2016. Its features include block-scoping of variables and functions, destructuring patterns (of variables), proper tail calls, exponentiation operator ** for numbers, await, async keywords for asynchronous programming (as a preparation for ES2017), and the function. The exponentiation operator is equivalent to , but provides a simpler syntax similar to languages like Python, F#, Perl, and Ruby. async / await was hailed as an easier way to use promises and develop asynchronous code. 8th Edition – ECMAScript 2017 The 8th edition, or ECMAScript 2017, was finalized in June 2017. Its features include the , and functions for easy manipulation of Objects, async / await constructions which use generators and promises, and additional features for concurrency and atomics. 9th Edition – ECMAScript 2018 The 9th edition, or ECMAScript 2018, was finalized in June 2018. New features include the spread operator and rest parameters (...) for object literals, asynchronous iteration, Promise.prototype.finally and additions to RegExp. The spread operator allows for the easy copying of object properties, as shown below.let object = {a: 1, b: 2} let objectClone = Object.assign({}, object) // before ES2018 let objectClone = {...object} // ES2018 syntax let otherObject = {c: 3, ...object} console.log(otherObject) // -> {c: 3, a: 1, b: 2} 10th Edition – ECMAScript 2019 The 10th edition, or ECMAScript 2019, was published in June 2019. Added features include, but are not limited to, Array.prototype.flat, Array.prototype.flatMap, changes to Array.sort and Object.fromEntries. is now guaranteed to be stable, meaning that elements with equal sorting keys will not change relative order before and after the sort operation. Array.prototype.flat(depth=1) flattens an array to a specified depth, meaning that all subarray elements (up to the specified depth) are concatenated recursively. Another notable change is that so-called catch binding became optional. 11th Edition – ECMAScript 2020 The 11th edition, or ECMAScript 2020, was published in June 2020. In addition to new functions, this version introduces a BigInt primitive type for arbitrary-sized integers, the nullish coalescing operator, and the globalThis object. BigInts are created either with the constructor or with the syntax , where "n" is placed after the number literal. BigInts allow the representation and manipulation of integers beyond , while Numbers are represented by a double-precision 64-bit IEEE 754 value. The built-in functions in are not compatible with BigInts; for example, exponentiation of BigInts must be done with the operator instead of . The nullish coalescing operator, , returns its right-hand side operand when its left-hand side is or . This contrasts with the operator, which would return for all "falsy" values, such as the ones below.undefined ?? "string" // -> "string" null ?? "string" // -> "string" false ?? "string" // -> false NaN ?? "string" // -> NaN Optional chaining makes it possible to access the nested properties of an object without having an AND check at each level. An example is . If any of the properties are not present, will be . 12th Edition – ECMAScript 2021 The 12th edition, ECMAScript 2021, was published in June 2021. This version introduces the method for strings; , a promise combinator that short-circuits when an input value is fulfilled; , a new error type to represent multiple errors at once; logical assignment operators (, , ||=); , for referring to a target object without preserving it from garbage collection, and , to manage registration and unregistration of cleanup operations performed when target objects are garbage collected; separators for numeric literals (); and was made more precise, reducing the number of cases that result in an implementation-defined sort order. 13th Edition – ECMAScript 2022 The 13th edition, ECMAScript 2022, was published in June 2022. This version introduces top-level , allowing the keyword to be used at the top level of modules; new class elements: public and private instance fields, public and private static fields, private instance methods and accessors, and private static methods and accessors; static blocks inside classes, to perform per-class evaluation initialization; the syntax, to test for presence of private fields on objects; regular expression match indices via the flag, which provides start and end indices for matched substrings; the property on objects, which can be used to record a causation chain in errors; the at method for Strings, Arrays, and TypedArrays, which allows relative indexing; and , a convenient alternative to . 14th Edition – ECMAScript 2023 The 14th edition, ECMAScript 2023, was published in June 2023. This version introduces the toSorted, toReversed, with, findLast, and findLastIndex methods on Array.prototype and TypedArray.prototype, as well as the toSpliced method on Array.prototype; added support for #! shebang comments at the beginning of files to better facilitate executable ECMAScript files; and allowed the use of most Symbols as keys in weak collections. ES.Next ES.Next is a dynamic name that refers to whatever the next version is at the time of writing. ES.Next features include finished proposals (aka "stage 4 proposals") as listed at finished proposals that are not part of a ratified specification. The language committee follows a "living spec" model, so these changes are part of the standard, and ratification is a formality. References External links JavaScript 1.0 As implemented in Netscape Navigator 2.0 before submitting the first version for standardization as Ecmascript: ISO standards ISO/IEC 22275:2018 ECMA standards ECMAScript Language Specification 1st Edition, June 1997: PDF 2nd Edition, August 1998: PDF 3rd Edition, December 1999: PDF Edition 3 Final, March 2000: PDF 4th Edition (overview): PDF 4th Edition (final draft): HTML, PDF 5th Edition, December 2009: PDF 5.1 Edition, June 2011: HTML, PDF 6th Edition, June 2015 (ECMAScript 2015 Language Specification): HTML, PDF 7th Edition, June 2016 (ECMAScript 2016 Language Specification): HTML, PDF 8th edition, June 2017 (ECMAScript 2017 Language Specification): HTML, PDF 9th edition, June 2018 (ECMAScript 2018 Language Specification): HTML,PDF 10th edition, June 2019 (ECMAScript 2019 Language Specification): HTML,PDF 11th edition, June 2020 (ECMAScript 2020 Language Specification): HTML,PDF 12th edition, June 2021 (ECMAScript 2021 Language Specification): HTML,PDF 13th edition, June 2022 (ECMAScript 2022 Language specification):HTML, PDF 14th edition, June 2023 (ECMAScript 2023 Language specification):HTML, PDF ECMA-290 ECMAScript Components Specification (June 1999) ECMA-327 ECMAScript 3rd Edition Compact Profile (June 2001) ECMA-357 ECMAScript for XML (E4X) Specification (June 2004) Ecma standards JavaScript
Shirley Wind is a wind farm in the Shirley section of Glenmore, Brown County, Wisconsin. The site, which opened in 2011, includes eight Nordex 2.5 (MW) wind turbines, each about tall. Originally developed by Emerging Energies LLC, it is owned by Duke Energy. When the wind farm was built, the turbines were the tallest in the state of Wisconsin, and among the tallest in North America. Following a study conducted in 2013, the Brown County Board of Health declared the Shirley Wind Farm a “human health hazard” in 2014. In 2015 the Brown County Health Director Chua Xiong said that there was insufficient scientific evidence to link wind turbines to illnesses experienced by residents. History Shirley Wind was originally developed by Emerging Energies LLC, a Wisconsin wind energy company. Emerging Energies had been looking to construct a wind farm in northeast Wisconsin since 2004. The permits were secured from the town of Glenmore in 2007. In 2009, Emerging Energies sold a 90 percent stake in the project to Central Hudson Energy Group. Construction on the wind farm began in April 2009. The farm began commercial operation in December 2010, selling the power to Wisconsin Public Service Corporation. In 2011, Duke Energy purchased Shirley Wind. Electricity Production * Data not available Health hazard Soon after the wind farm went into operation, local residents began complaining of health problems they said were caused by low frequency noise stemming from the wind turbines. Ultimately, over 75 local residents filed complaints with the Brown County Board of Health. In January 2012, the Brown County Board of Health requested emergency aid from the state to assist families suffering from the effects of the wind farm. In January 2013, a study of the low frequency noise was completed, which showed that three of the houses studied had evidence of low frequency noise, but in only one house was that noise coming from the outside. However, the study could not conclude that the health effects experienced by local residents were caused by the wind farm. In October 2014, the Brown County Board of Health declared the Shirley Wind farm a "human health hazard", based on the complaints of local residents, becoming the first board of health in the country to make such a declaration. In December 2015, after reviewing studies and evidence, Brown County Health Director Chua Xiong declared that there was insufficient evidence linking the wind turbines to the illnesses suffered by local residents. This decision was called into question after an Open Records request revealed that Xiong experienced migraines when near the wind turbines. She said: "The times I have been out there by the Wind Turbines, l get such migraine headaches, I think I should take some preventative Tylenol before I head out there." Migraines are a frequently observed symptom reported to the Brown County Health Department by people living near Shirley Wind's turbines when they are operating. Xiong resigned her position the day before the emails were revealed to a local citizen's group through an Open Records request. See also Wind power in Wisconsin Solar power in Wisconsin Wind power in the United States List of wind farms References Buildings and structures in Brown County, Wisconsin Wind farms in Wisconsin Duke Energy
John McCain, the nominee of the Republican party in the 2008 United States presidential election, has gained the endorsements of many high-profile figures. Both McCain and his Democratic opponent, Barack Obama, have stated that a person or entity's endorsement of their candidacy does not necessarily imply an endorsement by the candidate of all of the views of the endorser. U.S. presidents, vice presidents, and spouses President George W. Bush Vice President Dick Cheney Former President George H. W. Bush Former Vice President Dan Quayle Former First Lady Nancy Reagan U.S. senators U.S. representatives Governors Retired military Senator McCain was endorsed by over 100 retired generals and admirals from the U.S. Army, Navy, Air Force, and Marine Corps, among them: Mayors Tommy Joe Alexander of Irondale, Alabama Carlos Alvarez of Miami-Dade County Alan Autry of Fresno Rich Crotty of Orange County, Florida Richard J. Gerbounka of Linden, New Jersey (I-NJ) Rudy Giuliani, former mayor of New York City, former 2008 presidential candidate State, local, and territorial officials Other political figures National figures Francis J. Beckwith, Professor of Philosophy and Church-State Studies, Baylor University Robert Gleason, Chairman of the Republican Party of Pennsylvania John C. Hagee, founder and senior pastor of the evangelical mega-church Cornerstone Church in San Antonio, Texas Fmr. Treasurer of the United States Rosario Marin (CA) Newspapers These newspapers have endorsed John McCain's general election run: Academics Anne O. Krueger, Economist and former World Bank Chief Economist. Robert P. George, McCormick Professor of Jurisprudence at Princeton University. Bernie Machen, president of the University of Florida. Business people Sheldon Adelson, Las Vegas Casino billionaire Bradbury Anderson, Best Buy CEO Hoyt R. Barnett, Publix Vice Chairman August A. Busch III, former Anheuser-Busch Chairman Pete Coors, Coors Brewing Company Chairman Carly Fiorina, former CEO of Hewlett-Packard Steve Forbes, magazine publisher, former GOP presidential candidate (1996, 2000) Deal W. Hudson, Conservative publisher. Tom Monaghan, founder of Domino's Pizza. Frederick W. Smith, founder, chairman, president, and CEO of FedEx. Donald Trump, chairman and CEO of the Trump Organization and future U.S. president Robert Ulrich, Target Chairman and CEO Michael D. White, Pepsi Vice Chairman Meg Whitman, former CEO of eBay Bob Wright, former NBC Universal Chairman and CEO Entertainers Foreign entertainers Eduardo Verástegui, Mexican actor Adult entertainment Gauge, porn star Teri Weigel, porn star Athletes and sportspeople Troy Aikman, former Dallas Cowboys quarterback George Bodenheimer, ESPN President Bryan Clay Olympic gold medalist in decathlon. Bill Davidson, owner of the Detroit Pistons Mike Ditka, ESPN NFL Analyst and Former Chicago Bears and New Orleans Saints Head Coach. John Elway, Hall of Fame Denver Broncos quarterback Al Leiter, Former MLB Pitcher. Chuck Liddell, MMA fighter Colette Nelson, IFBB professional bodybuilder Brady Quinn, Cleveland Browns quarterback Nolan Ryan, Hall of Fame MLB pitcher Curt Schilling, Boston Red Sox pitcher Jason Sehorn, retired New York Giants cornerback Roger Staubach, Hall of Fame Dallas Cowboys quarterback Joe Thomas, Cleveland Browns offensive tackle Organizations Al-Hesbah National Rifle Association of America Republicans for Environmental Protection Log Cabin Republicans Conservative Voice Other individuals Morris J. Amitay, AIPAC. David Frum, Journalist. Charles Krauthammer, Conservative political pundit Michael Savage, radio host Samuel Joseph Wurzelbacher "Joe the Plumber" Foreign political figures David Cameron, member of the British Conservative Party. Wilfried Martens, president of the European People's Party See also Congressional endorsements for the 2008 United States presidential election Newspaper endorsements in the United States presidential primaries, 2008 List of Barack Obama presidential campaign endorsements, 2008 List of Hillary Clinton 2008 presidential campaign endorsements List of Ron Paul 2008 presidential endorsements McCain Democrat References External links Supporters list from the John McCain campaign website List of endorsers, from Project Vote Smart. John McCain 2008 presidential campaign McCain, John McCain presidential campaign endorsements, 2008 2008 United States presidential election endorsements
```python def test(self): self.sendline('tbreak main') self.sendline('continue') self.continue_to('r0') self.sendline('set $r0 = 3') self.continue_to('r1') assert self.get_int('$r0') == 3 assert self.get_int('$r1') == 2 ```
```go package upgrade import ( "github.com/spf13/cast" "github.com/spf13/viper" modulev1 "cosmossdk.io/api/cosmos/upgrade/module/v1" "cosmossdk.io/core/address" "cosmossdk.io/core/app" "cosmossdk.io/core/appmodule" "cosmossdk.io/depinject" "cosmossdk.io/depinject/appconfig" authtypes "cosmossdk.io/x/auth/types" "cosmossdk.io/x/upgrade/keeper" "cosmossdk.io/x/upgrade/types" "github.com/cosmos/cosmos-sdk/client/flags" "github.com/cosmos/cosmos-sdk/codec" "github.com/cosmos/cosmos-sdk/server" servertypes "github.com/cosmos/cosmos-sdk/server/types" "github.com/cosmos/cosmos-sdk/types/module" ) var _ depinject.OnePerModuleType = AppModule{} // IsOnePerModuleType implements the depinject.OnePerModuleType interface. func (am AppModule) IsOnePerModuleType() {} func init() { appconfig.RegisterModule(&modulev1.Module{}, appconfig.Provide(ProvideModule), appconfig.Invoke(PopulateVersionMap), ) } type ModuleInputs struct { depinject.In Config *modulev1.Module Environment appmodule.Environment Cdc codec.Codec AddressCodec address.Codec AppVersionModifier app.VersionModifier AppOpts servertypes.AppOptions `optional:"true"` // server v0 Viper *viper.Viper `optional:"true"` // server v2 } type ModuleOutputs struct { depinject.Out UpgradeKeeper *keeper.Keeper Module appmodule.AppModule } func ProvideModule(in ModuleInputs) ModuleOutputs { var ( homePath string skipUpgradeHeights = make(map[int64]bool) ) if in.Viper != nil { // viper takes precedence over app options for _, h := range in.Viper.GetIntSlice(server.FlagUnsafeSkipUpgrades) { skipUpgradeHeights[int64(h)] = true } homePath = in.Viper.GetString(flags.FlagHome) } else if in.AppOpts != nil { for _, h := range cast.ToIntSlice(in.AppOpts.Get(server.FlagUnsafeSkipUpgrades)) { skipUpgradeHeights[int64(h)] = true } homePath = cast.ToString(in.AppOpts.Get(flags.FlagHome)) } // default to governance authority if not provided authority := authtypes.NewModuleAddress(types.GovModuleName) if in.Config.Authority != "" { authority = authtypes.NewModuleAddressOrBech32Address(in.Config.Authority) } authorityStr, err := in.AddressCodec.BytesToString(authority) if err != nil { panic(err) } // set the governance module account as the authority for conducting upgrades k := keeper.NewKeeper(in.Environment, skipUpgradeHeights, in.Cdc, homePath, in.AppVersionModifier, authorityStr) m := NewAppModule(k) return ModuleOutputs{UpgradeKeeper: k, Module: m} } func PopulateVersionMap(upgradeKeeper *keeper.Keeper, modules map[string]appmodule.AppModule) { if upgradeKeeper == nil { return } upgradeKeeper.SetInitVersionMap(module.NewManagerFromMap(modules).GetVersionMap()) } ```
Abraham Han (born September 29, 1984) is an American professional boxer. He also fought in the World Combat League. Personal life Han's siblings are all professional or amateur boxers. Professional career On January 22, 2011, Han beat veteran Orphius Waite by TKO in the second round. This bout was held at the Texas Station in North Las Vegas, Nevada. On April 5, 2014, Han defeated former world title contender Juan Carlos Candelo via second-round TKO. By defeating Candelo, he was awarded the Universal Boxing Federation Inter-Continental middleweight title. On September 8, 2017, Han fought J'Leon Love to a technical majority draw. The fight was stopped in the eight round after a clash of heads left Han unable to continue. References External links Boxers from Texas Light-middleweight boxers 1984 births Living people Sportspeople from El Paso, Texas American male boxers
Foreign relations between the Argentine Republic and People's Republic of China has existed for decades. Both countries established diplomatic relations in 1945 as the Republic of China and again on March 19, 1972, with the PRC. Both nations are members of the G20 and the United Nations. Background China's Zhou Enlai, during Mao Zedong's leadership, steered the initial China–Latin America relations by encouraging friendly connections that eventually led to diplomatic relations. The development of diplomatic relations of China and Latin America was in the interest of developing cultural and economic ties. Organizations without ties to the governments of Latin American countries were created to help strengthen these ties between China and Latin America. Starting from 1970, until 1974, China successfully developed diplomatic relations with 12 of Latin America's countries. Five of them in the early part of the four-year span being Argentina, Brazil, Chile, Mexico, and Venezuela. Diplomatic relations were normalized in 1972, under the presidency of Alejandro Lanusse. In 1973, Isabel Perón led a mission in China as the official envoy of Justicialist Party. In 1980, General Jorge Rafael Videla, as de facto president of the country, was the first Argentine leader to visit China. For China and Latin America to expand on their diplomatic relations, China generated four interrelated concepts – “peace, mutual support, mutual benefit, and collaborative development." One of Argentina's main export is soybeans and soybean related products. The Argentine government in 2002 led by Eduardo Duhalde enforced high taxes of soybean exports, and Néstor Kirchner's following administration doubled that amount. In November 2004, Kirchner went to Beijing to address China and Argentina's cooperation in future investments and exchanges. In April 2020, China has become Argentina's biggest trading partner. In Feb 2022, Argentine president's Alberto Fernandez attended the Beijing Winter 2022 Olympics and met with China's Xi Jinping. Within the same month, Argentina officially joined China's Belt and Road Initiative via a memorandum of understanding (MoU) and China also issued an official statement that it backs Argentina's territorial claims over the British-run Falkland Islands. On 7 February 2022, Liz Truss called on China to respect the sovereignty of the Falklands Islands. Trade Two factors on economic influence within Argentina is China's emigration, and exports and imports. Approximately 64% of the farmable land in Argentina is reserved for soybean production. Since 2010, Argentina has become a main exporter of soybean meal and soybean oil. The soybean meal and soybean oil percentages of Argentina range from over 40% (soybean meal) and 60% (soybean oil) of global production. In order to grow Argentina's collective income, soybeans (and soybean related items) are charged 35% of their worth; the greater part of these profits are 5% of Argentina's collective income in soybean exportation. Argentina's financial sector has experienced changes within their soybean exports since the early 2000s. With China's influence in Latin America during this early period, countries a part of the Mercosur organization also experienced changes within their trade evaluations. The rate of soybean production of five South American countries a part of Mercosur witnessed a 221.4% growth from 1995 to 2010. Argentina is one of China's main trading partners in South America; the trade between both countries amounting to nearly $13 billion in US currency. Before 2008, the amount of exports Argentina sent to China accounted to be US$5.796 billion, and the imports from China to Argentina totaled to be US$7.649 billion. The trade exchange between Argentina and China showed an 80% export of soybean products to China from Argentina, and Chinese industrial exports totaling to be 98.9% of Argentina's imports. During the economic crisis of 2008, with the minor loss in profits in imports and exports worldwide, and China managing to maintain consistency economically, China was recognized as a world power which directly effected the relationship with Argentina. In 2008, when Argentine trades to China reached US$6,379 million, the exports of soybean products to China from Argentina stopped. Already processed soybean products were prohibited in the Chinese market due to China's own competitive soybean crushing industry. Argentina's total investment in soybean exports was US$143 million in the past two decades and increased to US$5.55 billion. This event led to Argentina's bilateral trade deficit from 2007 to 2014 amounting to US$24,164 million. During these two decades, Argentina's economic strategies have been ideal to soybean production which expanded from 1995's, 12 million tons, to 2010's, 52.6 million tons. During Argentina's trade deficit, not all of Argentina's soybean products were exported to China, leading to a growth in Argentina's trading partners. In 2012, India was an important importer of Argentine soy oil, followed by China, some European countries, Iran, and Peru. In 2013, Argentina was ranked third in global soybean production, after Brazil and the United States. The amount of soybean production within Argentina totaled to be 18% worldwide. When trade between China and Argentina increased after the initial deficit, China started to direct their attention towards Argentina's local markets, and infrastructures. China invested in large projects in Argentina such as roads, railroads, and shipping ports to increase export profitability to China. Chinese interest in Argentina has been focused on areas of manufacturing connected to exports to China such as oil, railroads to transport products across different areas of the country, and the soybean industry. In 2010, Chinese investments influenced the Economic Commission for Latin America which largely influenced the economy in Argentina. One of China's influences has been through supplying industrial items to Argentina's growing economy such as: cellular, radio, and television equipment, and computer mainframes. In April 2023, Argentina announced to pay for Chinese imports in yuan rather than dollars. This decision aims to relieve the country's dwindling dollar reserves. Violation of Argentina's EEZ There have been a number of reported violations of Argentina's Exclusive Economic Zone by Chinese trawlers which extract approximately 950,000 tonnes per year of fish worth around US$2.47 billion from the Argentine Sea. These have resulted in clashes with the Argentine Coast Guard. On 17 June 2013, Argentine Coast Guard apprehended a Chinese fishing vessel off its coast. On 15 March 2016, Chinese fishing trawler Lu Yan Yuan Yu 010 violated the EEZ, and was sunk by Argentine Coast Guard. There were no fatalities. On 9 March 2018, Argentina issued an International capture order for five Chinese boats illegally fishing in its EEZ. On 4 March 2019, a Chinese fishing trawler Hua Xiang 801 which was fishing illegally within the country's exclusive economic zone was fired upon by an Argentine Coast guard vessel. Chinese involvement in migration and land investments Residency In 2010 Argentina's National Census listed 11,804 Chinese immigrants living within its borders - 75.6% of this number were immigrants from the People's Republic of China. Foreign immigrants are allowed to stay in the country as either "permanent residents", refugees, or "temporary" residents due to the 2004 Argentine Migration Act. The National Directorate of Migration (NDM) confirmed that 17,505 Chinese citizens had their permanent residency requests approved between 2004 and 2013. After this period, the NDM published their completed analysis/study in 2014 concerning the 2003–2013 census of Chinese residents to show that 48.8% of Chinese immigrants had violated Argentine laws at one point during this time period. This statistic represents a relatively small number of Chinese immigrants actually within the prison system - specifically the 19 Chinese immigrants out of 2,259 foreigners inside the Argentine prison system.Crimes committed against the Chinese citizens of Argentina remained unresolved. The Argentine government submitted requests during this time to China's Ministry of Public Security for help with solving and reducing the number of repeat cases. After the first initial visit from the Chinese police delegation of December 2011, homicides continued, and Argentina and China together decided to resume the cooperation agreement of 1997 in order to solve homicide cases and crimes related to human and drug trafficking. Both the Chinese government and the Argentine government regulate the migration communication and flow through administrative decisions. Illegal immigration in 2004 was addressed by the Argentine government's Decree No. 1169 that insisted on regulating the migration of people from countries not a part of Mercosur. An impact of the Chinese community within Argentina's society and government has spread through the creation of organizations assembled by citizens, and establishment of offices representing Chinese companies within the last ten years. Chinese community organizations and groups within Argentina aim to improve education and advancement of media, as well as provide space for incoming offices of Chinese corporations. Land investment Chinese ventures have focused on governing parcels of open land in Argentina for resources and food production wholly aimed towards Chinese purchase. Neoliberal reforms endorsed by Latin American countries recognize foreign investments as being equal to domestic investment. After the Chinese globalization program of 1999, "Going Global", aimed at expanding capital for the Chinese government on a global scale, Chinese corporations such as China International Water and Electric Corporation started to focus on garnering land in Latin America in 2000. During discussion of global expanse within Argentina, it was determined that Argentine land being invested in by Chinese companies would not officially be considered Chinese land, however China would have control over the production of resources within the area. As of 2015, Chinese land investment discussions have stopped due to differences in views. Military relations In February 2015, Chinese president and general secretary of the Chinese Communist Party Xi Jinping and his Argentine counterpart, Cristina Fernandez de Kirchner, announced prospective ambitious arms sales and defense cooperation agreements extending beyond the scope of any made. These plans include Argentina's purchase or coproduction of 110 8×8 VN-1 APCs, 14 JF-17/FC-1 multirole fighters, and five P18 Malvinas class patrol ships. While the government of President Mauricio Macri, elected in December 2015, soon dropped the arms purchases from China. that also authorizes construction of satellite tracking facility near Las Lajas, Neuquén; base is managed by People's Liberation Army Strategic Support Force. Per Argentine ambassador to China, Diego Guelar, China has agreed to use the base only for civilian purposes. Resident diplomatic missions Argentina has an embassy in Beijing and consulates-general in Guangzhou, Hong Kong and Shanghai. China has an embassy in Buenos Aires. See also Chinese Argentines Embassy of Argentina, Beijing Foreign relations of Argentina Foreign relations of China References Citations Bibliography External links List of Treaties ruling relations Argentina and China (Argentine Foreign Ministry, in Spanish) Chinese Ministry of Foreign Affairs about relations with Argentina Chinese embassy in Buenos Aires (in Spanish only) Bilateral relations of China China, People's Republic of
Ivana Rentsch (born in 1974) is a Swiss musicologist and teacher at the University of Hamburg. Life Born in Olten, Rentsch studied musicology, media and linguistics at the University of Zürich. From 2000, she spent five years as a research assistant at the Musicological Institute of the University of Bern. In 2004 she received her doctorate with her thesis on Bohuslav Martinů's operas of the interwar period. In 2005 she was granted a research scholarship at the Austrian universities of Graz and Salzburg for the project Dance in Score (Swiss National Science Foundation). From 2006 to 2013 Rentsch was assistant at the Musicological Institute of the University of Zurich. She habilitated there in 2010 with her study on the significance of dance for instrumental music and music theory of the early modern period. At the same time, she held teaching positions at the universities of Basel, Bern, Fribourg and Graz. Since 2013 Rentsch has been professor for historical musicology at the University of Hamburg. Rentsch is married to the musicologist Arne Stollberg. Focus of research and publications Rentsch is co-editor of the journal Die Musikforschung and member of the scientific advisory board of both Bohuslav Martinů Complete Edition (Bohuslav Martinů Stiftung Prag, Bärenreiter-Verlag), as well as that of the Recherche sur la musique française XVIIe-XVIIIe siècles. Nouvelle série and the journal Musicologica slovaca (Slovak Academy of Sciences). Publications Anklänge an die Avantgarde : Bohuslav Martinůs Opern der Zwischenkriegszeit(Beihefte zum Archiv für Musikwissenschaft, vol. 61), Stuttgart : Steiner, 2007. Die Poesie der Oper. Bohuslav Martinus Theaterästhetik als Gegenentwurf zum Musikdrama, Sonderband Bohuslav Martinu. Musik-Konzepte. Neue Folge. Edited by Ulrich Tadday, 2009, References External links Ivana Rentsch – University of Hamburg Ivana Rentsch on WorldCat Swiss musicologists 21st-century musicologists Women musicologists Academic staff of the University of Hamburg 1974 births Living people People from Olten
```objective-c #pragma once #include <torch/types.h> #include "../image_read_mode.h" #include "decode_jpegs_cuda.h" #include "encode_jpegs_cuda.h" namespace vision { namespace image { /* Fast jpeg decoding with CUDA. A100+ GPUs have dedicated hardware support for jpeg decoding. Args: - encoded_images (const std::vector<torch::Tensor>&): a vector of tensors containing the jpeg bitstreams to be decoded. Each tensor must have dtype torch.uint8 and device cpu - mode (ImageReadMode): IMAGE_READ_MODE_UNCHANGED, IMAGE_READ_MODE_GRAY and IMAGE_READ_MODE_RGB are supported - device (torch::Device): The desired CUDA device to run the decoding on and which will contain the output tensors Returns: - decoded_images (std::vector<torch::Tensor>): a vector of torch::Tensors of dtype torch.uint8 on the specified <device> containing the decoded images Notes: - If a single image fails, the whole batch fails. - This function is thread-safe */ C10_EXPORT std::vector<torch::Tensor> decode_jpegs_cuda( const std::vector<torch::Tensor>& encoded_images, vision::image::ImageReadMode mode, torch::Device device); /* Fast jpeg encoding with CUDA. Args: - decoded_images (const std::vector<torch::Tensor>&): a vector of contiguous CUDA tensors of dtype torch.uint8 to be encoded. - quality (int64_t): 0-100, 75 is the default Returns: - encoded_images (std::vector<torch::Tensor>): a vector of CUDA torch::Tensors of dtype torch.uint8 containing the encoded images Notes: - If a single image fails, the whole batch fails. - This function is thread-safe */ C10_EXPORT std::vector<torch::Tensor> encode_jpegs_cuda( const std::vector<torch::Tensor>& decoded_images, const int64_t quality); } // namespace image } // namespace vision ```
Cotysomerida lampyroides is a species of beetle in the family Cerambycidae, and the only species in the genus Cotysomerida. It was described by Martins and Galileo in 2009. References Hemilophini Beetles described in 2009
Luther Gilyard Jr. (February 20, 1910 – September 20, 1976), sometimes listed as "Gillard", was an American Negro league first baseman in the 1930s and 1940s. A native of Fort Smith, Arkansas, Gilyard made his Negro leagues debut in 1937 with the St. Louis Stars and Chicago American Giants. He played for Chicago again the following two seasons, and finished his career in 1942 with the Birmingham Black Barons. Gilyard died in Detroit, Michigan in 1976 at age 66. References External links and Seamheads Luther Gilyard at Arkansas Baseball Encyclopedia 1910 births 1976 deaths Birmingham Black Barons players Chicago American Giants players St. Louis Stars (1937) players 20th-century African-American sportspeople Baseball infielders
The 2016 Jacob Companies 200 was the 5th stock car race of the 2016 NASCAR Camping World Truck Series, and the 17th iteration of the event. The race was held on Friday, May 13, 2016, in Dover, Delaware at Dover International Speedway, a 1-mile (1.6 km) permanent oval-shaped racetrack. The race took the scheduled 200 laps to complete. Matt Crafton, driving for ThorSport Racing, held off Daniel Suárez in the final 28 laps for his 12th career NASCAR Camping World Truck Series win, and his first of the season. To fill out the podium, Christopher Bell, driving for Kyle Busch Motorsports, would finish in 3rd, respectively. Background Dover International Speedway is a race track in Dover, Delaware. The track has hosted at least one NASCAR Cup Series race each year since 1969, including two per year from 1971 to 2020. In addition to NASCAR, the track also hosted USAC and the Indy Racing League. The track features one layout, a concrete oval, with 24° banking in the turns and 9° banking on the straights. The speedway is owned and operated by Speedway Motorsports. The track, nicknamed "The Monster Mile", was built in 1969 by Melvin Joseph of Melvin L. Joseph Construction Company, Inc., with an asphalt surface, but was replaced with concrete in 1995. Six years later in 2001, the track's capacity increased to 135,000 seats, giving the track the largest seating capacity of any sports venue in the mid-Atlantic region. In 2002, the name changed to Dover International Speedway from Dover Downs International Speedway after Dover Downs Gaming and Entertainment split, making Dover Motorsports. From 2007 to 2009, the speedway worked on an improvement project called "The Monster Makeover", which expanded facilities at the track and beautified the track. Depending on configuration, the track's capacity is at 95,500 seats. Its grand total maximum capacity was at 135,000 spectators. Entry list (R) denotes rookie driver. (i) denotes driver who is ineligible for series driver points. Practice First practice The first practice session was held on Thursday, May 12, at 2:00 pm EST, and would last for 55 minutes. William Byron, driving for Kyle Busch Motorsports, would set the fastest time in the session, with a lap of 22.581, and an average speed of . Final practice The final practice session was held on Thursday, May 12, at 4:00 pm EST, and would last for 55 minutes. Cole Custer, driving for JR Motorsports, would set the fastest time in the session, with a lap of 22.846, and an average speed of . Qualifying Qualifying was originally going to be held on Friday, May 13, at 2:15 pm EST. Since Dover International Speedway is under 1.5 miles (2.4 km) in length, the qualifying system was a multi-car system that included three rounds. The first round was 15 minutes, where every driver would be able to set a lap within the 15 minutes. Then, the second round would consist of the fastest 24 cars in Round 1, and drivers would have 10 minutes to set a lap. Round 3 consisted of the fastest 12 drivers from Round 2, and the drivers would have 5 minutes to set a time. Whoever was fastest in Round 3 would win the pole. Qualifying would be cancelled due to inclement weather. The starting lineup would be determined by speeds in first practice. As a result, William Byron, driving for Kyle Busch Motorsports would earn the pole. Austin Cindric and Norm Benning would fail to qualify. Starting lineup Race results Standings after the race Drivers' Championship standings Note: Only the first 8 positions are included for the driver standings. References NASCAR races at Dover Motor Speedway May 2016 sports events in the United States 2016 in sports in Delaware
Crime Against Joe is a 1956 American film noir crime film directed by Lee Sholem and written by Robert C. Dennis. The film stars John Bromfield, Julie London, Henry Calvin, Patricia Blair, Joel Ashley and Robert Keys. Plot A Korean War veteran is accused of the murder of a night club singer in Tucson, Arizona. A high school pin was found on the scene of the crime and the veteran's pin is missing. However, when the crime was committed, the veteran was leading a female somnambulist to her home but her over-protective father gives a false testimony to the district attorney. "Slacks", a female friend, gives him a false alibi but the police soon sort that out. The veteran thinks that one of his fellow high school students from 1945 was the murderer. He has got possible suspects on a list. Is the murderer among them? Cast John Bromfield as Joe Manning Julie London as Frances 'Slacks' Bennett Henry Calvin as Red Waller Patricia Blair as Christine 'Christy' Rowen Joel Ashley as Philip Rowen Robert Keys as Detective Sgt. Hollander Alika Louis as Irene Crescent John Pickard as Harry Dorn Frances Morris as Nora Manning Rhodes Reason as George Niles Mauritz Hugo as Dr. Louis Tatreau Joyce Jameson as Gloria Wayne Morgan Jones as Luther Woods James Parnell as Ralph Corey Addison Richards as District Attorney Roy Kasden References External links 1956 films United Artists films American crime films 1956 crime films Film noir Films directed by Lee Sholem Films scored by Paul Dunlap American black-and-white films 1950s English-language films 1950s American films
The Royal Air Force (RAF) and Fleet Air Arm had included personnel from outside the United Kingdom from before the beginning of the Second World War, and many served in the Battle of Britain in summer 1940. Many of these volunteers were British subjects—thus, citizens—coming from territories that made up part of the British Empire. Additionally, a significant part was made up of refugees and exiles from German-occupied Europe and American emigrants. The RAF Roll of Honour recognises that 574 pilots, from countries other than the United Kingdom, as flying at least one authorized, operational sortie with an eligible unit during the period between 10 July to 31 October 1940, alongside 2,353 British pilots. The numbers differ slightly from the participants whose names are engraved on the Battle of Britain Monument in London, unveiled on 18 September 2005. All pilots, regardless of nationality, who flew with British units during the Battle are known collectively, after a phrase coined by Winston Churchill, as "The Few". Background Prior to the outbreak of war, in view of the worsening European situation, the RAF had embarked on a series of expansion plans. These included Short-Service Commissions for pilots from the air forces of other British Commonwealth countries, namely Australia, Canada, New Zealand, South Africa and Southern Rhodesia. The governments of Australia, Canada, New Zealand and the UK, under an agreement signed in December 1939, created the British Commonwealth Air Training Plan (BCATP), also known as the Empire Air Training Scheme. The plan had three main effects: first, joint military aircrew training facilities were set up in each member country, as well as Southern Rhodesia; second, these air forces also formed a common pool of aircrew and ground staff, who were posted to units according to operational needs and regardless of nationality and; third, under Article XV of the agreement, the Royal Australian Air Force (RAAF), Royal Canadian Air Force (RCAF) and Royal New Zealand Air Force (RNZAF) formed squadrons for service under RAF operational control. These so-called "Article XV squadrons" were given numbers in the 400-series, to avoid confusion with RAF units. Other squadrons from Dominion air forces served under RAF control during the Battle and other units, composed mostly of RAAF, RCAF and RNZAF personnel were formed within the RAF itself. Most of these squadrons and personnel were still in training and/or were not involved in fighter operations during the Battle of Britain, although No. 1 Squadron RCAF took part in operations from August 1940. Contribution by country Australia When the war began, about 450 Australian pilots were serving in the RAF. Australia was among the first countries to declare war on Germany and the Royal Australian Air Force (RAAF) was among the world's oldest air forces, having been formed in 1921; a predecessor, the Australian Flying Corps served during the First World War, in the Middle East and Europe, but was disbanded in 1919. Under the Empire Air Training Scheme (EATS), a total of 37,000 aircrew were trained in Australia during 1939–45. However, the flow of RAAF personnel to the European theatre was slowed by three factors: first, establishment of the massively expanded training process meant that first aircrews trained by the RAAF during the war did not graduate until November 1940; second, RAAF doctrine emphasised the army co-operation and maritime patrol roles; third, the Australian authorities placed great emphasis on a provision of EATS, that Dominion personnel should serve with units from their own air forces, wherever possible. RAAF Article XV fighter squadrons were not operational in Europe until mid-1941. Nevertheless, more than 30 Australians served in RAF Fighter Command during the Battle. The highest scoring Australian ace of the Battle was Flight Lieutenant Pat Hughes, of No. 234 Squadron RAF, who claimed 14 kills before his death on 7 September 1940. No. 10 Squadron RAAF, a flying boat squadron was also based in Britain at the time, as part of Coastal Command. Barbados At the start of the war, the small Caribbean island of Barbados was a British crown colony. Aubrey "Sinbad" de Lisle Inniss (1916–2003) was the sole Barbadian to serve as a pilot during the Battle of Britain. Inniss was born in Barbados to a British family and joined the RAF in 1939. During the Battle, he flew a Bristol Blenheim IF night fighter with No. 236 Squadron RAF and was responsible for shooting down a Heinkel He 111 in September 1940. Inniss, who became an ace during his subsequent war service, survived the conflict and retired from the RAF in 1957. The RAF Monument lists Inniss as Bajan, while the RAF Roll of Honour lists him as British. Belgium At the time Belgium was invaded in May 1940, it had only a small airforce known as the Aéronautique militaire (AéMI). Although it played little role during the campaign in Belgium, a number of Belgian pilots succeeded in reaching Britain in the aftermath of the surrender. A significant number of Belgians were also undergoing flight training in France and, despite the reluctance of the Belgian government in Bordeaux, 124 reached Britain by August 1940 but few were able to participate in the Battle of Britain. As of December 2014, the RAF officially recognizes 30 Belgians as having participated in the Battle of Britain (of whom 18 did not survive the war) although the Battle of Britain monument (constructed in 2005) includes 28. At the time of the battle, Belgian pilots were mixed into British units and did not have their own squadrons. By the summer of 1940, Belgians made up around half of No. 609 Squadron RAF, a unit flying Spitfire fighters. Nos. 235 and 236 Squadrons of RAF Coastal Command also had disproportionate numbers of Belgian pilots at 8 and 6 respectively. Altogether, Belgium provided the largest contingent of pilots during the Battle of Britain that were not from Eastern Europe or the Commonwealth. During the course of the battle, Belgian pilots were responsible for shooting down 21 German aircraft. Between seven and 10 Belgians were killed. In 1942, two all-Belgian squadrons were formed and, in total, 1,200 Belgians had served in the RAF during the course of the war. Canada Many Canadians served in the fighter squadrons which repulsed the Luftwaffe in the summer of 1940. In fact, although the RAF only recognises 83 Canadian pilots as flying on fighter operations during the Battle of Britain, the RCAF claims the actual figure was over 100, and that of those 23 who died and 30 more were killed later in the war. Much of this confusion can be attributed to the fact that apart from RCAF members flying in RCAF units, there were those RCAF members who were in RAF units as well as Canadians who were members of the RAF, not the RCAF. Another 200 Canadian pilots fought with RAF Bomber Command and RAF Coastal Command during the period and approx 2,000 Canadians served as ground crew. Of these, 26 were in No. 1 Squadron RCAF, flying Hurricanes. The squadron arrived in Britain soon after Dunkirk with 27 officers and 314 ground staff. This squadron would later be re-numbered as No. 401 "City of Westmount" Squadron RCAF, in line with Article XV of the British Commonwealth Air Training Plan (see above). It was the only fighter unit from the Commonwealth air forces to see combat in the Battle of Britain. No. 1 Squadron made an inauspicious start to its service with Fighter Command, when on 24 August 1940 two of its Hurricanes mistook a flight of Bristol Blenheims for Junkers Ju 88s, shooting one down with the loss of its crew; an example of what is now known as friendly fire. No. 1 became the first RCAF unit to engage enemy aircraft in battle when it met a formation of German bombers over southern England on 26 August 1940, claiming three kills and four damaged, with the loss of one pilot and one aircraft. By mid-October the squadron had claimed 31 enemy aircraft destroyed and 43 probables or damaged for the loss of 16 aircraft and three pilots. Other Canadians were spread across RAF squadrons, and on the second day of the Battle, 11 July, Canada suffered its first fighter casualty. In a Luftwaffe attack on the Royal Navy Dockyard naval base at Portland Harbour, Plt Offr D. A. Hewitt of Saint John, New Brunswick, flying a Hurricane with No. 501 Squadron RAF, attacked a Dornier Do 17 bomber and was hit himself. His aircraft plunged into the sea. Another Canadian pilot, Richard Howley, died eight days later. The dispersed Canadian airmen included one who flew with No. 303 (Polish) Squadron. A total of 12 Canadian pilots in the Royal Air Force including Willie McKnight flew with No. 242 Squadron RAF at various times through the Battle. On 30 August, under the command of Squadron Leader Douglas Bader, nine 242 Squadron aircraft met 100 enemy aircraft over Essex. Attacking from above, the squadron claimed 12 victories for no loss. Canadians also shared in repulsing the Luftwaffe'''s last major daylight attack. On 27 September 303 Squadron and 1 Squadron RCAF, attacked the first wave of enemy bombers. Seven aircraft were claimed destroyed, one probably destroyed and seven were damaged. The top Canadian scorer during the Battle was Flt Lt Hamilton Upton of No. 43 Squadron RAF, who claimed 10.25 aircraft shot down. Czechoslovakia Many of the Czechoslovak pilots had fled to France after Hitler's occupation of their country in March 1939 and had fought in the short Armée de L'Air in the Battle of France, gaining important combat experience. The rapid fall of France caused Czechoslovak soldiers and airmen to leave for Britain, where they established their own squadrons. Nearly 90 Czechoslovak pilots would fly in the Battle of Britain, with No. 310 and No. 312 (Czechoslovak) Squadrons, RAF, formed in the summer 1940 and operational during the battle. Some Czechs also served in other Fighter Command squadrons. Both Czechoslovak squadrons were equipped with Hurricanes. Czechoslovak fighters earned a reputation for aggressive aerial combat and for skills and bravery. Together with Czechoslovak pilots serving in other RAF units, a total of 86 - 84 Czechs and 2 Slovaks - served, claiming almost 60 air kills. Nine pilots were killed. The top Czechoslovak ace was Sgt. Josef František, flying with No. 303 (Polish) Squadron, who claimed 17 confirmed kills, making him the highest scoring non-British pilot in the Battle of Britain. Czechoslovak forces were financed by Czechoslovak government-in-exile through loan by Great Britain (Czechoslovak–British financial agreement). France French volunteers and Free French forces served in 245 and 615 Squadron. 13 are recognised in the Battle of Britain Roll of Honour. Pilots of the Free French Forces also flew with the RAF 100 (Bomber Support) Group, between 1943 and 1945. Ireland The Irish Free State (officially called Ireland or, in Gaelic, Eire from 1937) seceded from the British rule in 1922 after a two-year war of independence. Relations between the two countries were still strained in 1940. Although technically a British dominion, Ireland remained neutral for the duration of the Second World War. Many individual Irish citizens did enlist in the British military, however, and ten pilots from the country fought in the RAF during the Battle of Britain. One of them, Brendan "Paddy" Finucane, became an ace who would claim a total of 32 enemy aircraft before he was killed in 1942. The eldest of five children, Finucane grew up in County Dublin, where his father had taken part in the Easter Rising of 1916. He and his family moved to England in 1936, and he enlisted in the Royal Air Force aged 17. Finucane became operational in July 1940 and downed his first Bf 109 on 12 August, claiming a second the following day. During a 51-day period in 1941, Finucane claimed 16 Messerschmitt Bf 109 fighters shot down, while he was flying with an Australian squadron. Finucane became the youngest Wing Commander in the RAF, a rank he received at 21. He was shot down on 15 July 1942.Byrne, Maurice. "Spitfire Paddy: A rose named after a Battle of Britain pilot." bbm.org. Retrieved: 28 May 2011. The world's last verified surviving Battle of Britain pilot as of March 2023 is Group Captain John Hemingway, who was born in Dublin and returned to settle in Ireland in 2011. A Flying Officer during the Battle, he damaged a Bf 109 and was himself twice shot down in that period. Jamaica In 1940, the island of Jamaica was a crown colony under British rule. The sole Jamaican recognized as a participant in the Battle of Britain was Herbert Capstick, a Pilot Officer of British origin, who had been born in Jamaica in 1920. Capstick served in No. 236 Squadron RAF of Coastal Command. The Squadron was equipped with Bristol Blenheims and participated in anti-submarine operations in the English Channel. He survived the war and returned to live in Jamaica. Newfoundland Newfoundland was a separate dominion within the British Empire at the time of the battle. Pilot Officer Richard Alexander Howley is recognized as the sole Newfoundlander to serve in the RAF during the period by the Battle of Britain monument. Howley served in No. 141 Squadron RAF, flying Boulton Paul Defiant turret fighters. He was shot down over Dover on 19 July 1940, and posted missing in action. New Zealand New Zealand was among the first countries to declare war on Germany. The Royal New Zealand Air Force (RNZAF) was set up as a separate service in 1937, but numbered less than 1,200 personnel by September 1939. The Empire Air Training Scheme had resulted in about 100 RNZAF pilots being sent to Europe by the time the battle started. Unlike the other dominions, New Zealand did not insist on its aircrews serving with RNZAF squadrons, thereby speeding up the rate at which they entered service. An annual rate of 1,500 fully trained pilots was reached by January 1941. The most prominent New Zealander in the battle was Air Vice Marshal Keith Park, a high scoring air ace in the First World War and a member of the RAF since its creation. At the time he was air officer commanding No. 11 Group, defending London and south-east England. The RAF recognises 135 Fighter Command aircrew from New Zealand as having served in the battle. Several New Zealanders became high scorers, including Pilot Officer Colin Falkland Gray (No. 54 Squadron) with 14 claims, Flying Officer Brian Carbury (No. 603 Squadron) with 14 claims, and Pilot Officer Alan Christopher Deere (No. 54 Squadron), with 12 claims. Carbury shot down the first German aircraft over British territory since 1918, and was also one of two ace-in-a-day pilots of the battle. Northern Rhodesia In 1940, Northern Rhodesia (today Zambia) was a British protectorate in Southern Africa. One Northern Rhodesian, of British origin, is recognised as a participant in the Battle of Britain. Pilot Officer John Ellacombe was born in Livingstone in 1920 and was educated in South Africa. He joined the RAF in 1939 and served in No. 151 Squadron during the Battle of Britain, flying Hurricanes. During the Battle, Ellacombe shot down several German bomber aircraft and was himself shot down on two occasions. He enjoyed a successful career in the RAF after 1940, retiring as an Air Commodore in 1973. He died in 2014. Poland Following the German invasion of Poland, many Polish pilots were evacuated and made their way to France and Britain. During the German invasion of France in May 1940, of the 1,600 Polish pilots available to the Armée de l'Air it is estimated that only about 150 took an active part in combat. By June 1940, the Poles had over 85,000 men in France, including pilots and ground troops. Many of these personnel escaped to the UK around the time of the fall of France. By mid 1940, some 35,000 Polish airmen, soldiers and sailors had made their way to Britain, making up the largest foreign military force in the country after the French, as well as making it the largest Polish army ever formed abroad; of these some 8,500 were airmen. Many were members of the Polish Air Force which had fought the Luftwaffe. However, the Air Ministry and the RAF underestimated their potential value in fighting against the Luftwaffe, as they felt that the Polish defeat on home soil was due to incompetence and lack of training. Most of the Poles were initially posted either to bomber squadrons or the RAF Volunteer Reserve. Another one of the biggest barriers the Poles had to face was that of language. The fact that the majority of the Poles could not speak English made them unreliable in battle in the eyes of British commanders. One of the commanders stated that he would not have "people crashing around the sky until they understand what they're told to do." The Poles had to go through English language training before the majority of them could see action. On 11 June 1940, the Polish government-in-exile signed an agreement with the British Government to form a Polish Air Force in Great Britain. Finally, in July 1940, the RAF announced that it would form two Polish fighter squadrons: No. 302 Squadron and No. 303 Squadron were composed of Polish pilots and ground crews, although their flight commanders and commanding officers were British. The two fighter squadrons went into action in August, with 89 Polish pilots. Another 50 Poles took part in the battle, in RAF squadrons. Polish pilots were among the most experienced in the battle; most had hundreds of hours of pre-war flying experience and had fought in the Invasion of Poland or the battle of France. The Polish pilots had been well trained in formation flying and had learned from combat experience to fire from close range. By comparison, one Polish pilot referred to the close formation flying and set-piece attacks practiced in the RAF as "simply suicidal". The 147 Polish pilots claimed 201 aircraft shot down. No. 303 Squadron claimed the highest number of kills, 126, of any Hurricane squadron engaged in the battle of Britain. Witold Urbanowicz of No. 303 Squadron was the top Polish scorer with 15 claims. Antoni Głowacki was one of two Allied pilots in the battle to shoot down five German aircraft in one day, on 24 August –the other being New Zealander Brian Carbury. Stanisław Skalski, became the top-scoring Polish fighter ace of the Second World War. With their combat experience, Polish pilots would have known that the quickest and most efficient way to destroy an enemy aircraft was to fire from close range, which often surprised their British counterparts: "After firing a brief opening burst at 150 to 200 yards, just to get on the enemy's nerves, the Poles would close almost to point-blank range. That was where they did their real work. "When they go tearing into enemy bombers and fighters they get so close you would think they were going to collide." In all, 30 Polish airmen were killed during the battle. The close range tactics used by the Poles led to suggestions of recklessness, but there is little evidence for this view. For example, the death rate in No. 303 Squadron was lower than the average rate for other RAF squadrons, despite the squadron having been the highest-scoring Hurricane squadron during the battle. The Polish War Memorial on the outskirts of RAF Northolt was dedicated in 1948, as a commemoration of the Polish contribution to Allied arms. South Africa One of the RAF's leading aces, and one of the highest scoring pilots during the Battle of Britain was Adolph "Sailor" Malan DFC, an RAF pilot since 1936, who led No. 74 Squadron at the height of the Battle of Britain. Under his leadership No. 74 became one of the RAF's best units. Malan claimed his first two victories over Dunkirk on 21 May 1940, and had claimed five more by the time the Battle started in earnest. Between 19 July and 22 October he shot down six German aircraft. His "Ten Rules for Air Fighting" were printed and pinned up in crew rooms all over Fighter Command. He was part of a group of about 25 pilots from South Africa that took part in the Battle, eight or nine of whom (depending on sources) died during the Battle. Other notable pilots included P/O Albert "Zulu" Lewis, who opened his account over France in May with No. 85 Squadron, shooting down three Messerschmitt Bf 109s in one action. With No. 85 in August, and then in September with No. 249 Squadron under Squadron Leader (later Air Chief Marshal) Sir John Grandy, at North Weald. Lewis flew three, four and five times a day and 15 September 1940 got a He 111, and shared in the probable destruction of another. On 18 September he got his 12th confirmed enemy aircraft. By 27 September, flying GN-R, Lewis had 18 victories. He was shot down and badly burned on 28 September. Lewis missed the rest of the Battle and his recovery to flying fitness took over three months. Basil Gerald "Stapme" Stapleton, with several probables to his credit, survived a crash on 7 September, trying to stop bombers getting through to London. Both men would later command RAF squadrons. The most senior officer of South African origin during the Battle was Air Vice-Marshal Sir Christopher J. Quintin-Brand KBE, DSO, MC, DFC, Air Officer Commanding No. 10 Group RAF covering the South-West; a long service RAF officer, he had joined the RFC in 1916. Southern Rhodesia Southern Rhodesia (today Zimbabwe) was a British self-governing colony in Southern Africa at the time of the Battle of Britain. Three pilots born in Southern Rhodesia took part in the Battle of Britain: Squadron Leader Caesar Hull, Pilot Officer John Chomley, and Flight Lieutenant John Holderness. Of these, Hull and Chomley lost their lives. Hull, the highest-scoring RAF ace of the Norwegian Campaign earlier in the year, was killed in a dogfight over south London on 7 September 1940, a week after taking command of No. 43 Squadron RAF. Chomley went missing in action over the Channel on 12 August 1940 and was never found. United States The RAF recognises seven aircrew personnel who were from the United States as having taken part in the Battle of Britain. American citizens were prohibited from serving under the various U.S. Neutrality Acts; if an American citizen had defied strict neutrality laws, there was a risk of losing their citizenship and imprisonment. It is believed that another four Americans misled the British authorities about their origins, claiming to be Canadian or other nationalities. Billy Fiske was probably the most famous American pilot in the Battle of Britain, although he pretended to be a Canadian at the time. Fiske saw service with No. 601 Squadron RAF and claimed one—unconfirmed—kill. He crashed on 16 August 1940, and died the following day. Alexander Zatonski, No. 79 Squadron RAF - missing in action North Africa 6 December 1941 Andrew Mamedoff, No. 609 Squadron RAF - killed in crash 8 October 1941 Art Donahue, No. 64 Squadron RAF - KIA 11 September 1942 Carl Raymond Davis, No. 601 Squadron RAF - KIA 6 September 1940 De Peyster Brown, No. 401 Squadron RCAF Eugene Tobin, No. 609 Squadron RAF - KIA over France 7 September 1941 John Kenneth Haviland, No. 152 Squadron RAF Phillip Leckrone, No. 616 Squadron RAF - killed in flying accident 5 January 1941 Vernon Keough, No. 609 Squadron RAF - crashed during combat 15 February 1941 Billy Fiske, No. 601 Squadron RAF - died of wounds 17 August 1940 In popular culture Arkady Fiedler wrote a book about Polish pilots flying in the RAF during the Second World War, which was published in August 1942. The 2018 Polish-British film Hurricane depicts the experiences of a group of Poles flying as part of the No. 303 Squadron RAF ( 303) in the Battle of Britain during the war. At the end of the 1969 film the Battle of Britain a list is shown containing the nationality of pilots that flew for the RAF. It incorrectly includes within this list a single person from Israel. This relates to George Goodman who was born in Haifa in 1920 and which was at the time British military-administered Mandatory Palestine. Goodman was a British citizen and Israel did not become an independent country until May 1948. In some lists he is even recorded as Palestinian - also incorrectly. During campaigning for the 2009 elections for the European Parliament, the far-right British National Party (BNP) used an image of a Spitfire, with the caption "Battle for Britain", in a publicity attempt to win support for the party's anti-immigration stance. The picture chosen, however, depicted a Spitfire flown by a Polish pilot from No. 303 (Polish) Squadron and the party was mocked in the British media as "absurd". The song "Aces in Exile" from the 2010 album Coat of Arms by Swedish power metal band Sabaton is about foreign pilots serving in the battle of Britain. The song specifically references the No. 303(Polish), No. 310(Czechoslovakian), and No. 401 (Canadian) Squadrons See also List of RAF aircrew in the Battle of Britain No. 10 (Inter-Allied) Commando Emergency Powers (Defence) Act 1939 Allied Forces Act 1940 References Notes Citations Bibliography Coulthard-Clark, Chris. The Encyclopedia of Australia's Battles. Sydney: Allen & Unwin, 2001. . Fiedler, Arkady. 303 Squadron: The Legendary Battle of Britain Fighter Squadron. Los Angeles: Aquila Polonica, 2010. . Orange, Vincent. Park: The Biography of Air Chief Marshal Sir Keith Park. London: Grub Street, 2001. . Polak, Thomas with Jiri Radlich and Pavel Vancata. No. 310 (Czechoslovak) Squadron 1940–1945; Hurricane, Spitfire. Boé Cedex, France: Graphic Sud, 2006. . Shores, Christopher and Clive Williams. Aces High.'' London: Grub Street, 1994. . Further reading External links Battle of Britain Memorial, London website - participants Northern Irish pilots in Battle of Britain Irish pilots from the Republic of Ireland who fought in the Battle of Britain The Polish pilots who flew in the Battle Of Britain Britain Expatriate military units and formations
```java /* * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. * * This code is free software; you can redistribute it and/or modify it * published by the Free Software Foundation. Oracle designates this * particular file as subject to the "Classpath" exception as provided * by Oracle in the LICENSE file that accompanied this code. * * This code is distributed in the hope that it will be useful, but WITHOUT * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or * version 2 for more details (a copy is included in the LICENSE file that * accompanied this code). * * 2 along with this work; if not, write to the Free Software Foundation, * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. * * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA * or visit www.oracle.com if you need additional information or have any * questions. */ /* @ApiInfo( group="Tools" ) */ /** * Package containing classes implementing the Truffle Code Coverage Tracker. * * @since 19.3.0 */ package com.oracle.truffle.tools.coverage; ```
Ernie Parkinson is a former Irish international lawn bowler. Bowls career He won a bronze medal in the fours at the 1986 Commonwealth Games in Edinburgh with Billie Montgomery, Willie Watson and Roy McCune. Four years later he represented Northern Ireland in the pairs at the 1990 Commonwealth Games in Auckland, New Zealand. He plays for the Belmont Bowling Club which he joined from the Ormeau Bowls Club. References Living people Male lawn bowls players from Northern Ireland Bowls players at the 1986 Commonwealth Games Bowls players at the 1990 Commonwealth Games Commonwealth Games bronze medallists for Northern Ireland Commonwealth Games medallists in lawn bowls Year of birth missing (living people) Medallists at the 1986 Commonwealth Games
Saman Fallah (; born 12 May 2001) is an Iranian football defender who currently plays for Paykan in the Persian Gulf Pro League. References Living people 2001 births People from Sari, Iran Men's association football defenders Iranian men's footballers Paykan F.C. players Persian Gulf Pro League players Footballers at the 2022 Asian Games
```php <?php /* * * * path_to_url * * Unless required by applicable law or agreed to in writing, software * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the */ namespace Google\Service\Contactcenterinsights; class GoogleCloudContactcenterinsightsV1ExportIssueModelResponse extends \Google\Model { } // Adding a class alias for backwards compatibility with the previous class name. class_alias(GoogleCloudContactcenterinsightsV1ExportIssueModelResponse::class, your_sha256_hashightsV1ExportIssueModelResponse'); ```