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|---|
```html
<html>
<head>
<meta http-equiv="Content-Type" content="text/html; charset=US-ASCII">
<title>random_shuffle</title>
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<div class="section">
<div class="titlepage"><div><div><h5 class="title">
<a name="range.reference.algorithms.mutating.random_shuffle"></a><a class="link" href="random_shuffle.html" title="random_shuffle">random_shuffle</a>
</h5></div></div></div>
<h6>
<a name="range.reference.algorithms.mutating.random_shuffle.h0"></a>
<span class="phrase"><a name="range.reference.algorithms.mutating.random_shuffle.prototype"></a></span><a class="link" href="random_shuffle.html#range.reference.algorithms.mutating.random_shuffle.prototype">Prototype</a>
</h6>
<p>
</p>
<pre class="programlisting"><span class="keyword">template</span><span class="special"><</span><span class="keyword">class</span> <span class="identifier">RandomAccessRange</span><span class="special">></span>
<span class="identifier">RandomAccessRange</span><span class="special">&</span> <span class="identifier">random_shuffle</span><span class="special">(</span><span class="identifier">RandomAccessRange</span><span class="special">&</span> <span class="identifier">rng</span><span class="special">);</span>
<span class="keyword">template</span><span class="special"><</span><span class="keyword">class</span> <span class="identifier">RandomAccessRange</span><span class="special">></span>
<span class="keyword">const</span> <span class="identifier">RandomAccessRange</span><span class="special">&</span> <span class="identifier">random_shuffle</span><span class="special">(</span><span class="keyword">const</span> <span class="identifier">RandomAccessRange</span><span class="special">&</span> <span class="identifier">rng</span><span class="special">);</span>
<span class="keyword">template</span><span class="special"><</span><span class="keyword">class</span> <span class="identifier">RandomAccessRange</span><span class="special">,</span> <span class="keyword">class</span> <span class="identifier">Generator</span><span class="special">></span>
<span class="identifier">RandomAccessRange</span><span class="special">&</span> <span class="identifier">random_shuffle</span><span class="special">(</span><span class="identifier">RandomAccessRange</span><span class="special">&</span> <span class="identifier">rng</span><span class="special">,</span> <span class="identifier">Generator</span><span class="special">&</span> <span class="identifier">gen</span><span class="special">);</span>
<span class="keyword">template</span><span class="special"><</span><span class="keyword">class</span> <span class="identifier">RandomAccessRange</span><span class="special">,</span> <span class="keyword">class</span> <span class="identifier">Generator</span><span class="special">></span>
<span class="keyword">const</span> <span class="identifier">RandomAccessRange</span><span class="special">&</span> <span class="identifier">random_shuffle</span><span class="special">(</span><span class="keyword">const</span> <span class="identifier">RandomAccessRange</span><span class="special">&</span> <span class="identifier">rng</span><span class="special">,</span> <span class="identifier">Generator</span><span class="special">&</span> <span class="identifier">gen</span><span class="special">);</span>
</pre>
<p>
</p>
<h6>
<a name="range.reference.algorithms.mutating.random_shuffle.h1"></a>
<span class="phrase"><a name="range.reference.algorithms.mutating.random_shuffle.description"></a></span><a class="link" href="random_shuffle.html#range.reference.algorithms.mutating.random_shuffle.description">Description</a>
</h6>
<p>
<code class="computeroutput"><span class="identifier">random_shuffle</span></code> randomly
rearranges the elements in <code class="computeroutput"><span class="identifier">rng</span></code>.
The versions of <code class="computeroutput"><span class="identifier">random_shuffle</span></code>
that do not specify a <code class="computeroutput"><span class="identifier">Generator</span></code>
use an internal random number generator. The versions of <code class="computeroutput"><span class="identifier">random_shuffle</span></code> that do specify a <code class="computeroutput"><span class="identifier">Generator</span></code> use this instead. Returns
the shuffles range.
</p>
<h6>
<a name="range.reference.algorithms.mutating.random_shuffle.h2"></a>
<span class="phrase"><a name="range.reference.algorithms.mutating.random_shuffle.definition"></a></span><a class="link" href="random_shuffle.html#range.reference.algorithms.mutating.random_shuffle.definition">Definition</a>
</h6>
<p>
Defined in the header file <code class="computeroutput"><span class="identifier">boost</span><span class="special">/</span><span class="identifier">range</span><span class="special">/</span><span class="identifier">algorithm</span><span class="special">/</span><span class="identifier">random_shuffle</span><span class="special">.</span><span class="identifier">hpp</span></code>
</p>
<h6>
<a name="range.reference.algorithms.mutating.random_shuffle.h3"></a>
<span class="phrase"><a name="range.reference.algorithms.mutating.random_shuffle.requirements"></a></span><a class="link" href="random_shuffle.html#range.reference.algorithms.mutating.random_shuffle.requirements">Requirements</a>
</h6>
<p>
<span class="bold"><strong>For the version without a Generator:</strong></span>
</p>
<div class="itemizedlist"><ul class="itemizedlist" style="list-style-type: disc; "><li class="listitem">
<code class="computeroutput"><span class="identifier">RandomAccessRange</span></code>
is a model of the <a class="link" href="../../../concepts/random_access_range.html" title="Random Access Range">Random
Access Range</a> Concept.
</li></ul></div>
<p>
<span class="bold"><strong>For the version with a Generator:</strong></span>
</p>
<div class="itemizedlist"><ul class="itemizedlist" style="list-style-type: disc; ">
<li class="listitem">
<code class="computeroutput"><span class="identifier">RandomAccessRange</span></code>
is a model of the <a class="link" href="../../../concepts/random_access_range.html" title="Random Access Range">Random
Access Range</a> Concept.
</li>
<li class="listitem">
<code class="computeroutput"><span class="identifier">Generator</span></code> is a model
of the <code class="computeroutput"><span class="identifier">RandomNumberGeneratorConcept</span></code>.
</li>
<li class="listitem">
<code class="computeroutput"><span class="identifier">RandomAccessRange</span></code>'s
distance type is convertible to <code class="computeroutput"><span class="identifier">Generator</span></code>'s
argument type.
</li>
</ul></div>
<h6>
<a name="range.reference.algorithms.mutating.random_shuffle.h4"></a>
<span class="phrase"><a name="range.reference.algorithms.mutating.random_shuffle.precondition_"></a></span><a class="link" href="random_shuffle.html#range.reference.algorithms.mutating.random_shuffle.precondition_">Precondition:</a>
</h6>
<div class="itemizedlist"><ul class="itemizedlist" style="list-style-type: disc; "><li class="listitem">
<code class="computeroutput"><span class="identifier">distance</span><span class="special">(</span><span class="identifier">rng</span><span class="special">)</span></code>
is less than <code class="computeroutput"><span class="identifier">gen</span></code>'s
maximum value.
</li></ul></div>
<h6>
<a name="range.reference.algorithms.mutating.random_shuffle.h5"></a>
<span class="phrase"><a name="range.reference.algorithms.mutating.random_shuffle.complexity"></a></span><a class="link" href="random_shuffle.html#range.reference.algorithms.mutating.random_shuffle.complexity">Complexity</a>
</h6>
<p>
Linear. If <code class="computeroutput"><span class="special">!</span><span class="identifier">empty</span><span class="special">(</span><span class="identifier">rng</span><span class="special">)</span></code>, exactly <code class="computeroutput"><span class="identifier">distance</span><span class="special">(</span><span class="identifier">rng</span><span class="special">)</span> <span class="special">-</span> <span class="number">1</span></code>
swaps are performed.
</p>
</div>
<table xmlns:rev="path_to_url~gregod/boost/tools/doc/revision" width="100%"><tr>
<td align="left"></td>
Neil Groves<p>
file LICENSE_1_0.txt or copy at <a href="path_to_url" target="_top">path_to_url
</p>
</div></td>
</tr></table>
<hr>
<div class="spirit-nav">
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</html>
```
|
```objective-c
// or more contributor license agreements. See the NOTICE file
// distributed with this work for additional information
// regarding copyright ownership. The ASF licenses this file
//
// path_to_url
//
// Unless required by applicable law or agreed to in writing,
// "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
// specific language governing permissions and limitations
#pragma once
#include "parquet/api/io.h"
#include "parquet/api/schema.h"
#include "parquet/column_writer.h"
#include "parquet/exception.h"
#include "parquet/file_writer.h"
#include "parquet/statistics.h"
```
|
```xml
import { inject, observer } from 'mobx-react';
import { Spinner, SpinnerSize } from 'office-ui-fabric-react/lib/Spinner';
import * as React from 'react';
import { ApplicationStatus, AppStore } from '../../../stores/AppStore';
import { ConfigStore } from '../../../stores/ConfigStore';
import { Stores } from '../../../stores/RootStore';
import { DetailedFakeItemViewer } from './DetailedFakeItemViewer';
import { FakeItemContainer } from './FakeItemContainer';
import { ListCreator } from './ListCreator';
import styles from './MobxTutorial.module.scss';
import { ProgressIndicator } from './ProgressIndicator';
export type MobxTutorialStoreProps = {
appStore: AppStore;
configStore: ConfigStore;
};
export type MobxTutorialProps = Partial<MobxTutorialStoreProps>;
@inject(Stores.AppStore, Stores.ConfigurationStore)
@observer
export class MobxTutorial extends React.Component<MobxTutorialProps, {}> {
public render(): React.ReactElement<MobxTutorialProps> {
const { appStore, configStore } = this.props;
if (appStore.isInitializing)
return (<Spinner size={SpinnerSize.large} label="Initializing... please hodl" ariaLive="assertive" labelPosition="left" />);
return (
<div className={styles.mobxTutorial}>
<div className={styles.row}>
<div className={styles.title}>{configStore.applicationTitle}</div>
<ProgressIndicator></ProgressIndicator>
</div>
{appStore.status === ApplicationStatus.CreateList ?
<div className={styles.row}>
<div className={styles.subTitle}>1) Create List</div>
<ListCreator></ListCreator>
</div>
: null
}
{appStore.status === ApplicationStatus.CreateItems ?
<div className={styles.row}>
<div className={styles.subTitle}>2) Create Items</div>
<FakeItemContainer></FakeItemContainer>
</div>
: null
}
{appStore.status === ApplicationStatus.Completed ?
<div className={styles.row}>
<DetailedFakeItemViewer items={appStore.items}></DetailedFakeItemViewer>
</div>
:
null
}
</div>
);
}
}
```
|
The Molino de Pérez is a watermill which was built by the Uruguayan merchant Juan María Pérez in 1840. It's located in what nowadays is known as the Veltroni Passage, near Rambla O´Higgins (the promenade of Montevideo) and Alejandro Gallinal. It became a national historical heritage in 1975.
Location
It is located in the Parque Baroffio (in English: Baroffio Park) between the barrios (neighborhoods) of Malvín and Punta Gorda, in the department of Montevideo.
History
The building was constructed by Juan María Pérez in 1840. It was originally a milling industry, due to the fact that Pérez grew wheat along his own surrounding lands. It had a running watermill which worked due to the Malvin stream that flowed nearby, but it suffered damage over the years and in 1950 a reconstruction of the wheel was planned in “Abra del Perdomo”, Maldonado Department. Horacio Arredondo was in charge of this construction.
The stone walls remain from the original building, but the most touristic feature of the watermill is its mechanism inside.
The structure has 2 levels. It was constructed with stone and in some original parts with brick. The floor is wood. In the 1950 restoration large windows were added to the sides of the building so that the machinery could be seen from outside.
References
Buildings and structures in Montevideo
History museums in Uruguay
Watermills
|
```javascript
define("ace/snippets/scala",["require","exports","module"],function(e,t,n){"use strict";t.snippetText=undefined,t.scope="scala"}); (function() {
window.require(["ace/snippets/scala"], function(m) {
if (typeof module == "object" && typeof exports == "object" && module) {
module.exports = m;
}
});
})();
```
|
```objective-c
/*
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included
* in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
* AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*/
#ifndef _dcn_3_0_2_OFFSET_HEADER
#define _dcn_3_0_2_OFFSET_HEADER
// addressBlock: dce_dc_mmhubbub_vga_dispdec
// base address: 0x0
#define mmVGA_MEM_WRITE_PAGE_ADDR 0x0000
#define mmVGA_MEM_WRITE_PAGE_ADDR_BASE_IDX 0
#define mmVGA_MEM_READ_PAGE_ADDR 0x0001
#define mmVGA_MEM_READ_PAGE_ADDR_BASE_IDX 0
#define mmVGA_RENDER_CONTROL 0x0000
#define mmVGA_RENDER_CONTROL_BASE_IDX 1
#define mmVGA_SEQUENCER_RESET_CONTROL 0x0001
#define mmVGA_SEQUENCER_RESET_CONTROL_BASE_IDX 1
#define mmVGA_MODE_CONTROL 0x0002
#define mmVGA_MODE_CONTROL_BASE_IDX 1
#define mmVGA_SURFACE_PITCH_SELECT 0x0003
#define mmVGA_SURFACE_PITCH_SELECT_BASE_IDX 1
#define mmVGA_MEMORY_BASE_ADDRESS 0x0004
#define mmVGA_MEMORY_BASE_ADDRESS_BASE_IDX 1
#define mmVGA_DISPBUF1_SURFACE_ADDR 0x0006
#define mmVGA_DISPBUF1_SURFACE_ADDR_BASE_IDX 1
#define mmVGA_DISPBUF2_SURFACE_ADDR 0x0008
#define mmVGA_DISPBUF2_SURFACE_ADDR_BASE_IDX 1
#define mmVGA_MEMORY_BASE_ADDRESS_HIGH 0x0009
#define mmVGA_MEMORY_BASE_ADDRESS_HIGH_BASE_IDX 1
#define mmVGA_HDP_CONTROL 0x000a
#define mmVGA_HDP_CONTROL_BASE_IDX 1
#define mmVGA_CACHE_CONTROL 0x000b
#define mmVGA_CACHE_CONTROL_BASE_IDX 1
#define mmD1VGA_CONTROL 0x000c
#define mmD1VGA_CONTROL_BASE_IDX 1
#define mmD2VGA_CONTROL 0x000e
#define mmD2VGA_CONTROL_BASE_IDX 1
#define mmVGA_STATUS 0x0010
#define mmVGA_STATUS_BASE_IDX 1
#define mmVGA_INTERRUPT_CONTROL 0x0011
#define mmVGA_INTERRUPT_CONTROL_BASE_IDX 1
#define mmVGA_STATUS_CLEAR 0x0012
#define mmVGA_STATUS_CLEAR_BASE_IDX 1
#define mmVGA_INTERRUPT_STATUS 0x0013
#define mmVGA_INTERRUPT_STATUS_BASE_IDX 1
#define mmVGA_MAIN_CONTROL 0x0014
#define mmVGA_MAIN_CONTROL_BASE_IDX 1
#define mmVGA_TEST_CONTROL 0x0015
#define mmVGA_TEST_CONTROL_BASE_IDX 1
#define mmVGA_QOS_CTRL 0x0018
#define mmVGA_QOS_CTRL_BASE_IDX 1
#define mmCRTC8_IDX 0x002d
#define mmCRTC8_IDX_BASE_IDX 1
#define mmCRTC8_DATA 0x002d
#define mmCRTC8_DATA_BASE_IDX 1
#define mmGENFC_WT 0x002e
#define mmGENFC_WT_BASE_IDX 1
#define mmGENS1 0x002e
#define mmGENS1_BASE_IDX 1
#define mmATTRDW 0x0030
#define mmATTRDW_BASE_IDX 1
#define mmATTRX 0x0030
#define mmATTRX_BASE_IDX 1
#define mmATTRDR 0x0030
#define mmATTRDR_BASE_IDX 1
#define mmGENMO_WT 0x0030
#define mmGENMO_WT_BASE_IDX 1
#define mmGENS0 0x0030
#define mmGENS0_BASE_IDX 1
#define mmGENENB 0x0030
#define mmGENENB_BASE_IDX 1
#define mmSEQ8_IDX 0x0031
#define mmSEQ8_IDX_BASE_IDX 1
#define mmSEQ8_DATA 0x0031
#define mmSEQ8_DATA_BASE_IDX 1
#define mmDAC_MASK 0x0031
#define mmDAC_MASK_BASE_IDX 1
#define mmDAC_R_INDEX 0x0031
#define mmDAC_R_INDEX_BASE_IDX 1
#define mmDAC_W_INDEX 0x0032
#define mmDAC_W_INDEX_BASE_IDX 1
#define mmDAC_DATA 0x0032
#define mmDAC_DATA_BASE_IDX 1
#define mmGENFC_RD 0x0032
#define mmGENFC_RD_BASE_IDX 1
#define mmGENMO_RD 0x0033
#define mmGENMO_RD_BASE_IDX 1
#define mmGRPH8_IDX 0x0033
#define mmGRPH8_IDX_BASE_IDX 1
#define mmGRPH8_DATA 0x0033
#define mmGRPH8_DATA_BASE_IDX 1
#define mmCRTC8_IDX_1 0x0035
#define mmCRTC8_IDX_1_BASE_IDX 1
#define mmCRTC8_DATA_1 0x0035
#define mmCRTC8_DATA_1_BASE_IDX 1
#define mmGENFC_WT_1 0x0036
#define mmGENFC_WT_1_BASE_IDX 1
#define mmGENS1_1 0x0036
#define mmGENS1_1_BASE_IDX 1
#define mmD3VGA_CONTROL 0x0038
#define mmD3VGA_CONTROL_BASE_IDX 1
#define mmD4VGA_CONTROL 0x0039
#define mmD4VGA_CONTROL_BASE_IDX 1
#define mmD5VGA_CONTROL 0x003a
#define mmD5VGA_CONTROL_BASE_IDX 1
#define mmD6VGA_CONTROL 0x003b
#define mmD6VGA_CONTROL_BASE_IDX 1
#define mmVGA_SOURCE_SELECT 0x003c
#define mmVGA_SOURCE_SELECT_BASE_IDX 1
// addressBlock: dce_dc_dccg_dccg_dispdec
// base address: 0x0
#define mmPHYPLLA_PIXCLK_RESYNC_CNTL 0x0040
#define mmPHYPLLA_PIXCLK_RESYNC_CNTL_BASE_IDX 1
#define mmPHYPLLB_PIXCLK_RESYNC_CNTL 0x0041
#define mmPHYPLLB_PIXCLK_RESYNC_CNTL_BASE_IDX 1
#define mmPHYPLLC_PIXCLK_RESYNC_CNTL 0x0042
#define mmPHYPLLC_PIXCLK_RESYNC_CNTL_BASE_IDX 1
#define mmPHYPLLD_PIXCLK_RESYNC_CNTL 0x0043
#define mmPHYPLLD_PIXCLK_RESYNC_CNTL_BASE_IDX 1
#define mmDP_DTO_DBUF_EN 0x0044
#define mmDP_DTO_DBUF_EN_BASE_IDX 1
#define mmDSCCLK3_DTO_PARAM 0x0045
#define mmDSCCLK3_DTO_PARAM_BASE_IDX 1
#define mmDSCCLK4_DTO_PARAM 0x0046
#define mmDSCCLK4_DTO_PARAM_BASE_IDX 1
#define mmDPREFCLK_CGTT_BLK_CTRL_REG 0x0048
#define mmDPREFCLK_CGTT_BLK_CTRL_REG_BASE_IDX 1
#define mmREFCLK_CNTL 0x0049
#define mmREFCLK_CNTL_BASE_IDX 1
#define mmREFCLK_CGTT_BLK_CTRL_REG 0x004b
#define mmREFCLK_CGTT_BLK_CTRL_REG_BASE_IDX 1
#define mmPHYPLLE_PIXCLK_RESYNC_CNTL 0x004c
#define mmPHYPLLE_PIXCLK_RESYNC_CNTL_BASE_IDX 1
#define mmDCCG_PERFMON_CNTL2 0x004e
#define mmDCCG_PERFMON_CNTL2_BASE_IDX 1
#define mmDCCG_DS_DTO_INCR 0x0053
#define mmDCCG_DS_DTO_INCR_BASE_IDX 1
#define mmDCCG_DS_DTO_MODULO 0x0054
#define mmDCCG_DS_DTO_MODULO_BASE_IDX 1
#define mmDCCG_DS_CNTL 0x0055
#define mmDCCG_DS_CNTL_BASE_IDX 1
#define mmDCCG_DS_HW_CAL_INTERVAL 0x0056
#define mmDCCG_DS_HW_CAL_INTERVAL_BASE_IDX 1
#define mmDPREFCLK_CNTL 0x0058
#define mmDPREFCLK_CNTL_BASE_IDX 1
#define mmDCE_VERSION 0x005e
#define mmDCE_VERSION_BASE_IDX 1
#define mmDCCG_GTC_CNTL 0x0060
#define mmDCCG_GTC_CNTL_BASE_IDX 1
#define mmDCCG_GTC_DTO_INCR 0x0061
#define mmDCCG_GTC_DTO_INCR_BASE_IDX 1
#define mmDCCG_GTC_DTO_MODULO 0x0062
#define mmDCCG_GTC_DTO_MODULO_BASE_IDX 1
#define mmDCCG_GTC_CURRENT 0x0063
#define mmDCCG_GTC_CURRENT_BASE_IDX 1
#define mmDSCCLK0_DTO_PARAM 0x006c
#define mmDSCCLK0_DTO_PARAM_BASE_IDX 1
#define mmDSCCLK1_DTO_PARAM 0x006d
#define mmDSCCLK1_DTO_PARAM_BASE_IDX 1
#define mmDSCCLK2_DTO_PARAM 0x006e
#define mmDSCCLK2_DTO_PARAM_BASE_IDX 1
#define mmMILLISECOND_TIME_BASE_DIV 0x0070
#define mmMILLISECOND_TIME_BASE_DIV_BASE_IDX 1
#define mmDISPCLK_FREQ_CHANGE_CNTL 0x0071
#define mmDISPCLK_FREQ_CHANGE_CNTL_BASE_IDX 1
#define mmDC_MEM_GLOBAL_PWR_REQ_CNTL 0x0072
#define mmDC_MEM_GLOBAL_PWR_REQ_CNTL_BASE_IDX 1
#define mmDCCG_PERFMON_CNTL 0x0073
#define mmDCCG_PERFMON_CNTL_BASE_IDX 1
#define mmDCCG_GATE_DISABLE_CNTL 0x0074
#define mmDCCG_GATE_DISABLE_CNTL_BASE_IDX 1
#define mmDISPCLK_CGTT_BLK_CTRL_REG 0x0075
#define mmDISPCLK_CGTT_BLK_CTRL_REG_BASE_IDX 1
#define mmSOCCLK_CGTT_BLK_CTRL_REG 0x0076
#define mmSOCCLK_CGTT_BLK_CTRL_REG_BASE_IDX 1
#define mmDCCG_CAC_STATUS 0x0077
#define mmDCCG_CAC_STATUS_BASE_IDX 1
#define mmMICROSECOND_TIME_BASE_DIV 0x007b
#define mmMICROSECOND_TIME_BASE_DIV_BASE_IDX 1
#define mmDCCG_GATE_DISABLE_CNTL2 0x007c
#define mmDCCG_GATE_DISABLE_CNTL2_BASE_IDX 1
#define mmSYMCLK_CGTT_BLK_CTRL_REG 0x007d
#define mmSYMCLK_CGTT_BLK_CTRL_REG_BASE_IDX 1
#define mmDCCG_DISP_CNTL_REG 0x007f
#define mmDCCG_DISP_CNTL_REG_BASE_IDX 1
#define mmOTG0_PIXEL_RATE_CNTL 0x0080
#define mmOTG0_PIXEL_RATE_CNTL_BASE_IDX 1
#define mmDP_DTO0_PHASE 0x0081
#define mmDP_DTO0_PHASE_BASE_IDX 1
#define mmDP_DTO0_MODULO 0x0082
#define mmDP_DTO0_MODULO_BASE_IDX 1
#define mmOTG0_PHYPLL_PIXEL_RATE_CNTL 0x0083
#define mmOTG0_PHYPLL_PIXEL_RATE_CNTL_BASE_IDX 1
#define mmOTG1_PIXEL_RATE_CNTL 0x0084
#define mmOTG1_PIXEL_RATE_CNTL_BASE_IDX 1
#define mmDP_DTO1_PHASE 0x0085
#define mmDP_DTO1_PHASE_BASE_IDX 1
#define mmDP_DTO1_MODULO 0x0086
#define mmDP_DTO1_MODULO_BASE_IDX 1
#define mmOTG1_PHYPLL_PIXEL_RATE_CNTL 0x0087
#define mmOTG1_PHYPLL_PIXEL_RATE_CNTL_BASE_IDX 1
#define mmOTG2_PIXEL_RATE_CNTL 0x0088
#define mmOTG2_PIXEL_RATE_CNTL_BASE_IDX 1
#define mmDP_DTO2_PHASE 0x0089
#define mmDP_DTO2_PHASE_BASE_IDX 1
#define mmDP_DTO2_MODULO 0x008a
#define mmDP_DTO2_MODULO_BASE_IDX 1
#define mmOTG2_PHYPLL_PIXEL_RATE_CNTL 0x008b
#define mmOTG2_PHYPLL_PIXEL_RATE_CNTL_BASE_IDX 1
#define mmOTG3_PIXEL_RATE_CNTL 0x008c
#define mmOTG3_PIXEL_RATE_CNTL_BASE_IDX 1
#define mmDP_DTO3_PHASE 0x008d
#define mmDP_DTO3_PHASE_BASE_IDX 1
#define mmDP_DTO3_MODULO 0x008e
#define mmDP_DTO3_MODULO_BASE_IDX 1
#define mmOTG3_PHYPLL_PIXEL_RATE_CNTL 0x008f
#define mmOTG3_PHYPLL_PIXEL_RATE_CNTL_BASE_IDX 1
#define mmOTG4_PIXEL_RATE_CNTL 0x0090
#define mmOTG4_PIXEL_RATE_CNTL_BASE_IDX 1
#define mmDP_DTO4_PHASE 0x0091
#define mmDP_DTO4_PHASE_BASE_IDX 1
#define mmDP_DTO4_MODULO 0x0092
#define mmDP_DTO4_MODULO_BASE_IDX 1
#define mmOTG4_PHYPLL_PIXEL_RATE_CNTL 0x0093
#define mmOTG4_PHYPLL_PIXEL_RATE_CNTL_BASE_IDX 1
#define mmDPPCLK_CGTT_BLK_CTRL_REG 0x0098
#define mmDPPCLK_CGTT_BLK_CTRL_REG_BASE_IDX 1
#define mmDPPCLK0_DTO_PARAM 0x0099
#define mmDPPCLK0_DTO_PARAM_BASE_IDX 1
#define mmDPPCLK1_DTO_PARAM 0x009a
#define mmDPPCLK1_DTO_PARAM_BASE_IDX 1
#define mmDPPCLK2_DTO_PARAM 0x009b
#define mmDPPCLK2_DTO_PARAM_BASE_IDX 1
#define mmDPPCLK3_DTO_PARAM 0x009c
#define mmDPPCLK3_DTO_PARAM_BASE_IDX 1
#define mmDPPCLK4_DTO_PARAM 0x009d
#define mmDPPCLK4_DTO_PARAM_BASE_IDX 1
#define mmDCCG_CAC_STATUS2 0x009f
#define mmDCCG_CAC_STATUS2_BASE_IDX 1
#define mmSYMCLKA_CLOCK_ENABLE 0x00a0
#define mmSYMCLKA_CLOCK_ENABLE_BASE_IDX 1
#define mmSYMCLKB_CLOCK_ENABLE 0x00a1
#define mmSYMCLKB_CLOCK_ENABLE_BASE_IDX 1
#define mmSYMCLKC_CLOCK_ENABLE 0x00a2
#define mmSYMCLKC_CLOCK_ENABLE_BASE_IDX 1
#define mmSYMCLKD_CLOCK_ENABLE 0x00a3
#define mmSYMCLKD_CLOCK_ENABLE_BASE_IDX 1
#define mmSYMCLKE_CLOCK_ENABLE 0x00a4
#define mmSYMCLKE_CLOCK_ENABLE_BASE_IDX 1
#define mmDCCG_SOFT_RESET 0x00a6
#define mmDCCG_SOFT_RESET_BASE_IDX 1
#define mmDSCCLK_DTO_CTRL 0x00a7
#define mmDSCCLK_DTO_CTRL_BASE_IDX 1
#define mmDCCG_AUDIO_DTO_SOURCE 0x00ab
#define mmDCCG_AUDIO_DTO_SOURCE_BASE_IDX 1
#define mmDCCG_AUDIO_DTO0_PHASE 0x00ac
#define mmDCCG_AUDIO_DTO0_PHASE_BASE_IDX 1
#define mmDCCG_AUDIO_DTO0_MODULE 0x00ad
#define mmDCCG_AUDIO_DTO0_MODULE_BASE_IDX 1
#define mmDCCG_AUDIO_DTO1_PHASE 0x00ae
#define mmDCCG_AUDIO_DTO1_PHASE_BASE_IDX 1
#define mmDCCG_AUDIO_DTO1_MODULE 0x00af
#define mmDCCG_AUDIO_DTO1_MODULE_BASE_IDX 1
#define mmDCCG_VSYNC_OTG0_LATCH_VALUE 0x00b0
#define mmDCCG_VSYNC_OTG0_LATCH_VALUE_BASE_IDX 1
#define mmDCCG_VSYNC_OTG1_LATCH_VALUE 0x00b1
#define mmDCCG_VSYNC_OTG1_LATCH_VALUE_BASE_IDX 1
#define mmDCCG_VSYNC_OTG2_LATCH_VALUE 0x00b2
#define mmDCCG_VSYNC_OTG2_LATCH_VALUE_BASE_IDX 1
#define mmDCCG_VSYNC_OTG3_LATCH_VALUE 0x00b3
#define mmDCCG_VSYNC_OTG3_LATCH_VALUE_BASE_IDX 1
#define mmDCCG_VSYNC_OTG4_LATCH_VALUE 0x00b4
#define mmDCCG_VSYNC_OTG4_LATCH_VALUE_BASE_IDX 1
#define mmDCCG_VSYNC_OTG5_LATCH_VALUE 0x00b5
#define mmDCCG_VSYNC_OTG5_LATCH_VALUE_BASE_IDX 1
#define mmDPPCLK_DTO_CTRL 0x00b6
#define mmDPPCLK_DTO_CTRL_BASE_IDX 1
#define mmDCCG_VSYNC_CNT_CTRL 0x00b8
#define mmDCCG_VSYNC_CNT_CTRL_BASE_IDX 1
#define mmDCCG_VSYNC_CNT_INT_CTRL 0x00b9
#define mmDCCG_VSYNC_CNT_INT_CTRL_BASE_IDX 1
#define mmFORCE_SYMCLK_DISABLE 0x00ba
#define mmFORCE_SYMCLK_DISABLE_BASE_IDX 1
#define mmPHYASYMCLK_CLOCK_CNTL 0x0052
#define mmPHYASYMCLK_CLOCK_CNTL_BASE_IDX 2
#define mmPHYBSYMCLK_CLOCK_CNTL 0x0053
#define mmPHYBSYMCLK_CLOCK_CNTL_BASE_IDX 2
#define mmPHYCSYMCLK_CLOCK_CNTL 0x0054
#define mmPHYCSYMCLK_CLOCK_CNTL_BASE_IDX 2
#define mmPHYDSYMCLK_CLOCK_CNTL 0x0055
#define mmPHYDSYMCLK_CLOCK_CNTL_BASE_IDX 2
#define mmPHYESYMCLK_CLOCK_CNTL 0x0056
#define mmPHYESYMCLK_CLOCK_CNTL_BASE_IDX 2
// addressBlock: dce_dc_dccg_dccg_dfs_dispdec
// base address: 0x0
#define mmDENTIST_DISPCLK_CNTL 0x0064
#define mmDENTIST_DISPCLK_CNTL_BASE_IDX 1
// addressBlock: dce_dc_dccg_dccg_dcperfmon0_dc_perfmon_dispdec
// base address: 0x0
#define mmDC_PERFMON0_PERFCOUNTER_CNTL 0x0000
#define mmDC_PERFMON0_PERFCOUNTER_CNTL_BASE_IDX 2
#define mmDC_PERFMON0_PERFCOUNTER_CNTL2 0x0001
#define mmDC_PERFMON0_PERFCOUNTER_CNTL2_BASE_IDX 2
#define mmDC_PERFMON0_PERFCOUNTER_STATE 0x0002
#define mmDC_PERFMON0_PERFCOUNTER_STATE_BASE_IDX 2
#define mmDC_PERFMON0_PERFMON_CNTL 0x0003
#define mmDC_PERFMON0_PERFMON_CNTL_BASE_IDX 2
#define mmDC_PERFMON0_PERFMON_CNTL2 0x0004
#define mmDC_PERFMON0_PERFMON_CNTL2_BASE_IDX 2
#define mmDC_PERFMON0_PERFMON_CVALUE_INT_MISC 0x0005
#define mmDC_PERFMON0_PERFMON_CVALUE_INT_MISC_BASE_IDX 2
#define mmDC_PERFMON0_PERFMON_CVALUE_LOW 0x0006
#define mmDC_PERFMON0_PERFMON_CVALUE_LOW_BASE_IDX 2
#define mmDC_PERFMON0_PERFMON_HI 0x0007
#define mmDC_PERFMON0_PERFMON_HI_BASE_IDX 2
#define mmDC_PERFMON0_PERFMON_LOW 0x0008
#define mmDC_PERFMON0_PERFMON_LOW_BASE_IDX 2
// addressBlock: dce_dc_dccg_dccg_dcperfmon1_dc_perfmon_dispdec
// base address: 0x30
#define mmDC_PERFMON1_PERFCOUNTER_CNTL 0x000c
#define mmDC_PERFMON1_PERFCOUNTER_CNTL_BASE_IDX 2
#define mmDC_PERFMON1_PERFCOUNTER_CNTL2 0x000d
#define mmDC_PERFMON1_PERFCOUNTER_CNTL2_BASE_IDX 2
#define mmDC_PERFMON1_PERFCOUNTER_STATE 0x000e
#define mmDC_PERFMON1_PERFCOUNTER_STATE_BASE_IDX 2
#define mmDC_PERFMON1_PERFMON_CNTL 0x000f
#define mmDC_PERFMON1_PERFMON_CNTL_BASE_IDX 2
#define mmDC_PERFMON1_PERFMON_CNTL2 0x0010
#define mmDC_PERFMON1_PERFMON_CNTL2_BASE_IDX 2
#define mmDC_PERFMON1_PERFMON_CVALUE_INT_MISC 0x0011
#define mmDC_PERFMON1_PERFMON_CVALUE_INT_MISC_BASE_IDX 2
#define mmDC_PERFMON1_PERFMON_CVALUE_LOW 0x0012
#define mmDC_PERFMON1_PERFMON_CVALUE_LOW_BASE_IDX 2
#define mmDC_PERFMON1_PERFMON_HI 0x0013
#define mmDC_PERFMON1_PERFMON_HI_BASE_IDX 2
#define mmDC_PERFMON1_PERFMON_LOW 0x0014
#define mmDC_PERFMON1_PERFMON_LOW_BASE_IDX 2
// addressBlock: dce_dc_dmu_dc_pg_dispdec
// base address: 0x0
#define mmDOMAIN0_PG_CONFIG 0x0080
#define mmDOMAIN0_PG_CONFIG_BASE_IDX 2
#define mmDOMAIN0_PG_STATUS 0x0081
#define mmDOMAIN0_PG_STATUS_BASE_IDX 2
#define mmDOMAIN1_PG_CONFIG 0x0082
#define mmDOMAIN1_PG_CONFIG_BASE_IDX 2
#define mmDOMAIN1_PG_STATUS 0x0083
#define mmDOMAIN1_PG_STATUS_BASE_IDX 2
#define mmDOMAIN2_PG_CONFIG 0x0084
#define mmDOMAIN2_PG_CONFIG_BASE_IDX 2
#define mmDOMAIN2_PG_STATUS 0x0085
#define mmDOMAIN2_PG_STATUS_BASE_IDX 2
#define mmDOMAIN3_PG_CONFIG 0x0086
#define mmDOMAIN3_PG_CONFIG_BASE_IDX 2
#define mmDOMAIN3_PG_STATUS 0x0087
#define mmDOMAIN3_PG_STATUS_BASE_IDX 2
#define mmDOMAIN4_PG_CONFIG 0x0088
#define mmDOMAIN4_PG_CONFIG_BASE_IDX 2
#define mmDOMAIN4_PG_STATUS 0x0089
#define mmDOMAIN4_PG_STATUS_BASE_IDX 2
#define mmDOMAIN5_PG_CONFIG 0x008a
#define mmDOMAIN5_PG_CONFIG_BASE_IDX 2
#define mmDOMAIN5_PG_STATUS 0x008b
#define mmDOMAIN5_PG_STATUS_BASE_IDX 2
#define mmDOMAIN6_PG_CONFIG 0x008c
#define mmDOMAIN6_PG_CONFIG_BASE_IDX 2
#define mmDOMAIN6_PG_STATUS 0x008d
#define mmDOMAIN6_PG_STATUS_BASE_IDX 2
#define mmDOMAIN7_PG_CONFIG 0x008e
#define mmDOMAIN7_PG_CONFIG_BASE_IDX 2
#define mmDOMAIN7_PG_STATUS 0x008f
#define mmDOMAIN7_PG_STATUS_BASE_IDX 2
#define mmDOMAIN8_PG_CONFIG 0x0090
#define mmDOMAIN8_PG_CONFIG_BASE_IDX 2
#define mmDOMAIN8_PG_STATUS 0x0091
#define mmDOMAIN8_PG_STATUS_BASE_IDX 2
#define mmDOMAIN9_PG_CONFIG 0x0092
#define mmDOMAIN9_PG_CONFIG_BASE_IDX 2
#define mmDOMAIN9_PG_STATUS 0x0093
#define mmDOMAIN9_PG_STATUS_BASE_IDX 2
#define mmDOMAIN16_PG_CONFIG 0x00a1
#define mmDOMAIN16_PG_CONFIG_BASE_IDX 2
#define mmDOMAIN16_PG_STATUS 0x00a2
#define mmDOMAIN16_PG_STATUS_BASE_IDX 2
#define mmDOMAIN17_PG_CONFIG 0x00a3
#define mmDOMAIN17_PG_CONFIG_BASE_IDX 2
#define mmDOMAIN17_PG_STATUS 0x00a4
#define mmDOMAIN17_PG_STATUS_BASE_IDX 2
#define mmDOMAIN18_PG_CONFIG 0x00a5
#define mmDOMAIN18_PG_CONFIG_BASE_IDX 2
#define mmDOMAIN18_PG_STATUS 0x00a6
#define mmDOMAIN18_PG_STATUS_BASE_IDX 2
#define mmDOMAIN19_PG_CONFIG 0x00a7
#define mmDOMAIN19_PG_CONFIG_BASE_IDX 2
#define mmDOMAIN19_PG_STATUS 0x00a8
#define mmDOMAIN19_PG_STATUS_BASE_IDX 2
#define mmDOMAIN20_PG_CONFIG 0x00a9
#define mmDOMAIN20_PG_CONFIG_BASE_IDX 2
#define mmDOMAIN20_PG_STATUS 0x00aa
#define mmDOMAIN20_PG_STATUS_BASE_IDX 2
#define mmDCPG_INTERRUPT_STATUS 0x00ad
#define mmDCPG_INTERRUPT_STATUS_BASE_IDX 2
#define mmDCPG_INTERRUPT_STATUS_2 0x00ae
#define mmDCPG_INTERRUPT_STATUS_2_BASE_IDX 2
#define mmDCPG_INTERRUPT_CONTROL_1 0x00af
#define mmDCPG_INTERRUPT_CONTROL_1_BASE_IDX 2
#define mmDCPG_INTERRUPT_CONTROL_2 0x00b0
#define mmDCPG_INTERRUPT_CONTROL_2_BASE_IDX 2
#define mmDCPG_INTERRUPT_CONTROL_3 0x00b1
#define mmDCPG_INTERRUPT_CONTROL_3_BASE_IDX 2
#define mmDC_IP_REQUEST_CNTL 0x00b2
#define mmDC_IP_REQUEST_CNTL_BASE_IDX 2
// addressBlock: dce_dc_dmu_dmu_dcperfmon_dc_perfmon_dispdec
// base address: 0x2f8
#define mmDC_PERFMON2_PERFCOUNTER_CNTL 0x00be
#define mmDC_PERFMON2_PERFCOUNTER_CNTL_BASE_IDX 2
#define mmDC_PERFMON2_PERFCOUNTER_CNTL2 0x00bf
#define mmDC_PERFMON2_PERFCOUNTER_CNTL2_BASE_IDX 2
#define mmDC_PERFMON2_PERFCOUNTER_STATE 0x00c0
#define mmDC_PERFMON2_PERFCOUNTER_STATE_BASE_IDX 2
#define mmDC_PERFMON2_PERFMON_CNTL 0x00c1
#define mmDC_PERFMON2_PERFMON_CNTL_BASE_IDX 2
#define mmDC_PERFMON2_PERFMON_CNTL2 0x00c2
#define mmDC_PERFMON2_PERFMON_CNTL2_BASE_IDX 2
#define mmDC_PERFMON2_PERFMON_CVALUE_INT_MISC 0x00c3
#define mmDC_PERFMON2_PERFMON_CVALUE_INT_MISC_BASE_IDX 2
#define mmDC_PERFMON2_PERFMON_CVALUE_LOW 0x00c4
#define mmDC_PERFMON2_PERFMON_CVALUE_LOW_BASE_IDX 2
#define mmDC_PERFMON2_PERFMON_HI 0x00c5
#define mmDC_PERFMON2_PERFMON_HI_BASE_IDX 2
#define mmDC_PERFMON2_PERFMON_LOW 0x00c6
#define mmDC_PERFMON2_PERFMON_LOW_BASE_IDX 2
// addressBlock: dce_dc_dmu_dmu_misc_dispdec
// base address: 0x0
#define mmCC_DC_PIPE_DIS 0x00ca
#define mmCC_DC_PIPE_DIS_BASE_IDX 2
#define mmDMU_CLK_CNTL 0x00cb
#define mmDMU_CLK_CNTL_BASE_IDX 2
#define mmDMU_MEM_PWR_CNTL 0x00cc
#define mmDMU_MEM_PWR_CNTL_BASE_IDX 2
#define mmDMCU_SMU_INTERRUPT_CNTL 0x00cd
#define mmDMCU_SMU_INTERRUPT_CNTL_BASE_IDX 2
#define mmSMU_INTERRUPT_CONTROL 0x00ce
#define mmSMU_INTERRUPT_CONTROL_BASE_IDX 2
#define mmDMU_MISC_ALLOW_DS_FORCE 0x00d6
#define mmDMU_MISC_ALLOW_DS_FORCE_BASE_IDX 2
// addressBlock: dce_dc_dmu_dmcu_dispdec
// base address: 0x0
#define mmDMCU_CTRL 0x00da
#define mmDMCU_CTRL_BASE_IDX 2
#define mmDMCU_STATUS 0x00db
#define mmDMCU_STATUS_BASE_IDX 2
#define mmDMCU_PC_START_ADDR 0x00dc
#define mmDMCU_PC_START_ADDR_BASE_IDX 2
#define mmDMCU_FW_START_ADDR 0x00dd
#define mmDMCU_FW_START_ADDR_BASE_IDX 2
#define mmDMCU_FW_END_ADDR 0x00de
#define mmDMCU_FW_END_ADDR_BASE_IDX 2
#define mmDMCU_FW_ISR_START_ADDR 0x00df
#define mmDMCU_FW_ISR_START_ADDR_BASE_IDX 2
#define mmDMCU_FW_CS_HI 0x00e0
#define mmDMCU_FW_CS_HI_BASE_IDX 2
#define mmDMCU_FW_CS_LO 0x00e1
#define mmDMCU_FW_CS_LO_BASE_IDX 2
#define mmDMCU_RAM_ACCESS_CTRL 0x00e2
#define mmDMCU_RAM_ACCESS_CTRL_BASE_IDX 2
#define mmDMCU_ERAM_WR_CTRL 0x00e3
#define mmDMCU_ERAM_WR_CTRL_BASE_IDX 2
#define mmDMCU_ERAM_WR_DATA 0x00e4
#define mmDMCU_ERAM_WR_DATA_BASE_IDX 2
#define mmDMCU_ERAM_RD_CTRL 0x00e5
#define mmDMCU_ERAM_RD_CTRL_BASE_IDX 2
#define mmDMCU_ERAM_RD_DATA 0x00e6
#define mmDMCU_ERAM_RD_DATA_BASE_IDX 2
#define mmDMCU_IRAM_WR_CTRL 0x00e7
#define mmDMCU_IRAM_WR_CTRL_BASE_IDX 2
#define mmDMCU_IRAM_WR_DATA 0x00e8
#define mmDMCU_IRAM_WR_DATA_BASE_IDX 2
#define mmDMCU_IRAM_RD_CTRL 0x00e9
#define mmDMCU_IRAM_RD_CTRL_BASE_IDX 2
#define mmDMCU_IRAM_RD_DATA 0x00ea
#define mmDMCU_IRAM_RD_DATA_BASE_IDX 2
#define mmDMCU_EVENT_TRIGGER 0x00eb
#define mmDMCU_EVENT_TRIGGER_BASE_IDX 2
#define mmDMCU_UC_INTERNAL_INT_STATUS 0x00ec
#define mmDMCU_UC_INTERNAL_INT_STATUS_BASE_IDX 2
#define mmDMCU_SS_INTERRUPT_CNTL_STATUS 0x00ed
#define mmDMCU_SS_INTERRUPT_CNTL_STATUS_BASE_IDX 2
#define mmDMCU_INTERRUPT_STATUS 0x00ee
#define mmDMCU_INTERRUPT_STATUS_BASE_IDX 2
#define mmDMCU_INTERRUPT_STATUS_1 0x00ef
#define mmDMCU_INTERRUPT_STATUS_1_BASE_IDX 2
#define mmDMCU_INTERRUPT_TO_HOST_EN_MASK 0x00f0
#define mmDMCU_INTERRUPT_TO_HOST_EN_MASK_BASE_IDX 2
#define mmDMCU_INTERRUPT_TO_UC_EN_MASK 0x00f1
#define mmDMCU_INTERRUPT_TO_UC_EN_MASK_BASE_IDX 2
#define mmDMCU_INTERRUPT_TO_UC_EN_MASK_1 0x00f2
#define mmDMCU_INTERRUPT_TO_UC_EN_MASK_1_BASE_IDX 2
#define mmDMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL 0x00f3
#define mmDMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_BASE_IDX 2
#define mmDMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_1 0x00f4
#define mmDMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_1_BASE_IDX 2
#define mmDC_DMCU_SCRATCH 0x00f5
#define mmDC_DMCU_SCRATCH_BASE_IDX 2
#define mmDMCU_INT_CNT 0x00f6
#define mmDMCU_INT_CNT_BASE_IDX 2
#define mmDMCU_FW_CHECKSUM_SMPL_BYTE_POS 0x00f7
#define mmDMCU_FW_CHECKSUM_SMPL_BYTE_POS_BASE_IDX 2
#define mmDMCU_UC_CLK_GATING_CNTL 0x00f8
#define mmDMCU_UC_CLK_GATING_CNTL_BASE_IDX 2
#define mmMASTER_COMM_DATA_REG1 0x00f9
#define mmMASTER_COMM_DATA_REG1_BASE_IDX 2
#define mmMASTER_COMM_DATA_REG2 0x00fa
#define mmMASTER_COMM_DATA_REG2_BASE_IDX 2
#define mmMASTER_COMM_DATA_REG3 0x00fb
#define mmMASTER_COMM_DATA_REG3_BASE_IDX 2
#define mmMASTER_COMM_CMD_REG 0x00fc
#define mmMASTER_COMM_CMD_REG_BASE_IDX 2
#define mmMASTER_COMM_CNTL_REG 0x00fd
#define mmMASTER_COMM_CNTL_REG_BASE_IDX 2
#define mmSLAVE_COMM_DATA_REG1 0x00fe
#define mmSLAVE_COMM_DATA_REG1_BASE_IDX 2
#define mmSLAVE_COMM_DATA_REG2 0x00ff
#define mmSLAVE_COMM_DATA_REG2_BASE_IDX 2
#define mmSLAVE_COMM_DATA_REG3 0x0100
#define mmSLAVE_COMM_DATA_REG3_BASE_IDX 2
#define mmSLAVE_COMM_CMD_REG 0x0101
#define mmSLAVE_COMM_CMD_REG_BASE_IDX 2
#define mmSLAVE_COMM_CNTL_REG 0x0102
#define mmSLAVE_COMM_CNTL_REG_BASE_IDX 2
#define mmDMCU_PERFMON_INTERRUPT_STATUS1 0x0105
#define mmDMCU_PERFMON_INTERRUPT_STATUS1_BASE_IDX 2
#define mmDMCU_PERFMON_INTERRUPT_STATUS2 0x0106
#define mmDMCU_PERFMON_INTERRUPT_STATUS2_BASE_IDX 2
#define mmDMCU_PERFMON_INTERRUPT_STATUS3 0x0107
#define mmDMCU_PERFMON_INTERRUPT_STATUS3_BASE_IDX 2
#define mmDMCU_PERFMON_INTERRUPT_STATUS4 0x0108
#define mmDMCU_PERFMON_INTERRUPT_STATUS4_BASE_IDX 2
#define mmDMCU_PERFMON_INTERRUPT_STATUS5 0x0109
#define mmDMCU_PERFMON_INTERRUPT_STATUS5_BASE_IDX 2
#define mmDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1 0x010a
#define mmDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1_BASE_IDX 2
#define mmDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2 0x010b
#define mmDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2_BASE_IDX 2
#define mmDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3 0x010c
#define mmDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3_BASE_IDX 2
#define mmDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4 0x010d
#define mmDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4_BASE_IDX 2
#define mmDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5 0x010e
#define mmDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5_BASE_IDX 2
#define mmDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1 0x010f
#define mmDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1_BASE_IDX 2
#define mmDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2 0x0110
#define mmDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2_BASE_IDX 2
#define mmDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3 0x0111
#define mmDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3_BASE_IDX 2
#define mmDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4 0x0112
#define mmDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4_BASE_IDX 2
#define mmDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5 0x0113
#define mmDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5_BASE_IDX 2
#define mmDMCU_DPRX_INTERRUPT_STATUS1 0x0114
#define mmDMCU_DPRX_INTERRUPT_STATUS1_BASE_IDX 2
#define mmDMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1 0x0115
#define mmDMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1_BASE_IDX 2
#define mmDMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1 0x0116
#define mmDMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1_BASE_IDX 2
#define mmDMCU_INTERRUPT_STATUS_CONTINUE 0x0119
#define mmDMCU_INTERRUPT_STATUS_CONTINUE_BASE_IDX 2
#define mmDMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE 0x011a
#define mmDMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE_BASE_IDX 2
#define mmDMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE 0x011b
#define mmDMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE_BASE_IDX 2
#define mmDMCU_INT_CNT_CONTINUE 0x011c
#define mmDMCU_INT_CNT_CONTINUE_BASE_IDX 2
#define mmDMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONT2 0x011d
#define mmDMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONT2_BASE_IDX 2
#define mmDMCU_INTERRUPT_STATUS_2 0x011e
#define mmDMCU_INTERRUPT_STATUS_2_BASE_IDX 2
#define mmDMCU_INTERRUPT_TO_UC_EN_MASK_2 0x011f
#define mmDMCU_INTERRUPT_TO_UC_EN_MASK_2_BASE_IDX 2
#define mmDMCU_INT_CNT_CONT2 0x0120
#define mmDMCU_INT_CNT_CONT2_BASE_IDX 2
#define mmDMCU_INT_CNT_CONT3 0x0121
#define mmDMCU_INT_CNT_CONT3_BASE_IDX 2
#define mmDMCU_INT_CNT_CONT4 0x0122
#define mmDMCU_INT_CNT_CONT4_BASE_IDX 2
// addressBlock: dce_dc_dmu_ihc_dispdec
// base address: 0x0
#define mmDC_GPU_TIMER_START_POSITION_V_UPDATE 0x0126
#define mmDC_GPU_TIMER_START_POSITION_V_UPDATE_BASE_IDX 2
#define mmDC_GPU_TIMER_START_POSITION_VSTARTUP 0x0127
#define mmDC_GPU_TIMER_START_POSITION_VSTARTUP_BASE_IDX 2
#define mmDC_GPU_TIMER_READ 0x0128
#define mmDC_GPU_TIMER_READ_BASE_IDX 2
#define mmDC_GPU_TIMER_READ_CNTL 0x0129
#define mmDC_GPU_TIMER_READ_CNTL_BASE_IDX 2
#define mmDISP_INTERRUPT_STATUS 0x012a
#define mmDISP_INTERRUPT_STATUS_BASE_IDX 2
#define mmDISP_INTERRUPT_STATUS_CONTINUE 0x012b
#define mmDISP_INTERRUPT_STATUS_CONTINUE_BASE_IDX 2
#define mmDISP_INTERRUPT_STATUS_CONTINUE2 0x012c
#define mmDISP_INTERRUPT_STATUS_CONTINUE2_BASE_IDX 2
#define mmDISP_INTERRUPT_STATUS_CONTINUE3 0x012d
#define mmDISP_INTERRUPT_STATUS_CONTINUE3_BASE_IDX 2
#define mmDISP_INTERRUPT_STATUS_CONTINUE4 0x012e
#define mmDISP_INTERRUPT_STATUS_CONTINUE4_BASE_IDX 2
#define mmDISP_INTERRUPT_STATUS_CONTINUE5 0x012f
#define mmDISP_INTERRUPT_STATUS_CONTINUE5_BASE_IDX 2
#define mmDISP_INTERRUPT_STATUS_CONTINUE6 0x0130
#define mmDISP_INTERRUPT_STATUS_CONTINUE6_BASE_IDX 2
#define mmDISP_INTERRUPT_STATUS_CONTINUE7 0x0131
#define mmDISP_INTERRUPT_STATUS_CONTINUE7_BASE_IDX 2
#define mmDISP_INTERRUPT_STATUS_CONTINUE8 0x0132
#define mmDISP_INTERRUPT_STATUS_CONTINUE8_BASE_IDX 2
#define mmDISP_INTERRUPT_STATUS_CONTINUE9 0x0133
#define mmDISP_INTERRUPT_STATUS_CONTINUE9_BASE_IDX 2
#define mmDISP_INTERRUPT_STATUS_CONTINUE10 0x0134
#define mmDISP_INTERRUPT_STATUS_CONTINUE10_BASE_IDX 2
#define mmDISP_INTERRUPT_STATUS_CONTINUE11 0x0135
#define mmDISP_INTERRUPT_STATUS_CONTINUE11_BASE_IDX 2
#define mmDISP_INTERRUPT_STATUS_CONTINUE12 0x0136
#define mmDISP_INTERRUPT_STATUS_CONTINUE12_BASE_IDX 2
#define mmDISP_INTERRUPT_STATUS_CONTINUE13 0x0137
#define mmDISP_INTERRUPT_STATUS_CONTINUE13_BASE_IDX 2
#define mmDISP_INTERRUPT_STATUS_CONTINUE14 0x0138
#define mmDISP_INTERRUPT_STATUS_CONTINUE14_BASE_IDX 2
#define mmDISP_INTERRUPT_STATUS_CONTINUE15 0x0139
#define mmDISP_INTERRUPT_STATUS_CONTINUE15_BASE_IDX 2
#define mmDISP_INTERRUPT_STATUS_CONTINUE16 0x013a
#define mmDISP_INTERRUPT_STATUS_CONTINUE16_BASE_IDX 2
#define mmDISP_INTERRUPT_STATUS_CONTINUE17 0x013b
#define mmDISP_INTERRUPT_STATUS_CONTINUE17_BASE_IDX 2
#define mmDISP_INTERRUPT_STATUS_CONTINUE18 0x013c
#define mmDISP_INTERRUPT_STATUS_CONTINUE18_BASE_IDX 2
#define mmDISP_INTERRUPT_STATUS_CONTINUE19 0x013d
#define mmDISP_INTERRUPT_STATUS_CONTINUE19_BASE_IDX 2
#define mmDISP_INTERRUPT_STATUS_CONTINUE20 0x013e
#define mmDISP_INTERRUPT_STATUS_CONTINUE20_BASE_IDX 2
#define mmDISP_INTERRUPT_STATUS_CONTINUE21 0x013f
#define mmDISP_INTERRUPT_STATUS_CONTINUE21_BASE_IDX 2
#define mmDISP_INTERRUPT_STATUS_CONTINUE22 0x0140
#define mmDISP_INTERRUPT_STATUS_CONTINUE22_BASE_IDX 2
#define mmDC_GPU_TIMER_START_POSITION_VREADY 0x0141
#define mmDC_GPU_TIMER_START_POSITION_VREADY_BASE_IDX 2
#define mmDC_GPU_TIMER_START_POSITION_FLIP 0x0142
#define mmDC_GPU_TIMER_START_POSITION_FLIP_BASE_IDX 2
#define mmDC_GPU_TIMER_START_POSITION_V_UPDATE_NO_LOCK 0x0143
#define mmDC_GPU_TIMER_START_POSITION_V_UPDATE_NO_LOCK_BASE_IDX 2
#define mmDC_GPU_TIMER_START_POSITION_FLIP_AWAY 0x0144
#define mmDC_GPU_TIMER_START_POSITION_FLIP_AWAY_BASE_IDX 2
#define mmDISP_INTERRUPT_STATUS_CONTINUE23 0x0145
#define mmDISP_INTERRUPT_STATUS_CONTINUE23_BASE_IDX 2
#define mmDISP_INTERRUPT_STATUS_CONTINUE24 0x0146
#define mmDISP_INTERRUPT_STATUS_CONTINUE24_BASE_IDX 2
#define mmDISP_INTERRUPT_STATUS_CONTINUE25 0x0147
#define mmDISP_INTERRUPT_STATUS_CONTINUE25_BASE_IDX 2
#define mmDCCG_INTERRUPT_DEST 0x0148
#define mmDCCG_INTERRUPT_DEST_BASE_IDX 2
#define mmDMU_INTERRUPT_DEST 0x0149
#define mmDMU_INTERRUPT_DEST_BASE_IDX 2
#define mmDMU_INTERRUPT_DEST2 0x014a
#define mmDMU_INTERRUPT_DEST2_BASE_IDX 2
#define mmDCPG_INTERRUPT_DEST 0x014b
#define mmDCPG_INTERRUPT_DEST_BASE_IDX 2
#define mmDCPG_INTERRUPT_DEST2 0x014c
#define mmDCPG_INTERRUPT_DEST2_BASE_IDX 2
#define mmMMHUBBUB_INTERRUPT_DEST 0x014d
#define mmMMHUBBUB_INTERRUPT_DEST_BASE_IDX 2
#define mmWB_INTERRUPT_DEST 0x014e
#define mmWB_INTERRUPT_DEST_BASE_IDX 2
#define mmDCHUB_INTERRUPT_DEST 0x014f
#define mmDCHUB_INTERRUPT_DEST_BASE_IDX 2
#define mmDCHUB_PERFCOUNTER_INTERRUPT_DEST 0x0150
#define mmDCHUB_PERFCOUNTER_INTERRUPT_DEST_BASE_IDX 2
#define mmDCHUB_INTERRUPT_DEST2 0x0151
#define mmDCHUB_INTERRUPT_DEST2_BASE_IDX 2
#define mmDPP_PERFCOUNTER_INTERRUPT_DEST 0x0152
#define mmDPP_PERFCOUNTER_INTERRUPT_DEST_BASE_IDX 2
#define mmMPC_INTERRUPT_DEST 0x0153
#define mmMPC_INTERRUPT_DEST_BASE_IDX 2
#define mmOPP_INTERRUPT_DEST 0x0154
#define mmOPP_INTERRUPT_DEST_BASE_IDX 2
#define mmOPTC_INTERRUPT_DEST 0x0155
#define mmOPTC_INTERRUPT_DEST_BASE_IDX 2
#define mmOTG0_INTERRUPT_DEST 0x0156
#define mmOTG0_INTERRUPT_DEST_BASE_IDX 2
#define mmOTG1_INTERRUPT_DEST 0x0157
#define mmOTG1_INTERRUPT_DEST_BASE_IDX 2
#define mmOTG2_INTERRUPT_DEST 0x0158
#define mmOTG2_INTERRUPT_DEST_BASE_IDX 2
#define mmOTG3_INTERRUPT_DEST 0x0159
#define mmOTG3_INTERRUPT_DEST_BASE_IDX 2
#define mmOTG4_INTERRUPT_DEST 0x015a
#define mmOTG4_INTERRUPT_DEST_BASE_IDX 2
#define mmOTG5_INTERRUPT_DEST 0x015b
#define mmOTG5_INTERRUPT_DEST_BASE_IDX 2
#define mmDIG_INTERRUPT_DEST 0x015c
#define mmDIG_INTERRUPT_DEST_BASE_IDX 2
#define mmI2C_DDC_HPD_INTERRUPT_DEST 0x015d
#define mmI2C_DDC_HPD_INTERRUPT_DEST_BASE_IDX 2
#define mmDIO_INTERRUPT_DEST 0x015f
#define mmDIO_INTERRUPT_DEST_BASE_IDX 2
#define mmDCIO_INTERRUPT_DEST 0x0160
#define mmDCIO_INTERRUPT_DEST_BASE_IDX 2
#define mmHPD_INTERRUPT_DEST 0x0161
#define mmHPD_INTERRUPT_DEST_BASE_IDX 2
#define mmAZ_INTERRUPT_DEST 0x0162
#define mmAZ_INTERRUPT_DEST_BASE_IDX 2
#define mmAUX_INTERRUPT_DEST 0x0163
#define mmAUX_INTERRUPT_DEST_BASE_IDX 2
#define mmDSC_INTERRUPT_DEST 0x0164
#define mmDSC_INTERRUPT_DEST_BASE_IDX 2
// addressBlock: dce_dc_dmu_fgsec_dispdec
// base address: 0x0
#define mmDMCUB_RBBMIF_SEC_CNTL 0x017a
#define mmDMCUB_RBBMIF_SEC_CNTL_BASE_IDX 2
// addressBlock: dce_dc_dmu_rbbmif_dispdec
// base address: 0x0
#define mmRBBMIF_TIMEOUT 0x017f
#define mmRBBMIF_TIMEOUT_BASE_IDX 2
#define mmRBBMIF_STATUS 0x0180
#define mmRBBMIF_STATUS_BASE_IDX 2
#define mmRBBMIF_STATUS_2 0x0181
#define mmRBBMIF_STATUS_2_BASE_IDX 2
#define mmRBBMIF_INT_STATUS 0x0182
#define mmRBBMIF_INT_STATUS_BASE_IDX 2
#define mmRBBMIF_TIMEOUT_DIS 0x0183
#define mmRBBMIF_TIMEOUT_DIS_BASE_IDX 2
#define mmRBBMIF_TIMEOUT_DIS_2 0x0184
#define mmRBBMIF_TIMEOUT_DIS_2_BASE_IDX 2
#define mmRBBMIF_STATUS_FLAG 0x0185
#define mmRBBMIF_STATUS_FLAG_BASE_IDX 2
// addressBlock: dce_dc_dmu_dmcub_dispdec
// base address: 0x0
#define mmDMCUB_REGION0_OFFSET 0x018e
#define mmDMCUB_REGION0_OFFSET_BASE_IDX 2
#define mmDMCUB_REGION0_OFFSET_HIGH 0x018f
#define mmDMCUB_REGION0_OFFSET_HIGH_BASE_IDX 2
#define mmDMCUB_REGION1_OFFSET 0x0190
#define mmDMCUB_REGION1_OFFSET_BASE_IDX 2
#define mmDMCUB_REGION1_OFFSET_HIGH 0x0191
#define mmDMCUB_REGION1_OFFSET_HIGH_BASE_IDX 2
#define mmDMCUB_REGION2_OFFSET 0x0192
#define mmDMCUB_REGION2_OFFSET_BASE_IDX 2
#define mmDMCUB_REGION2_OFFSET_HIGH 0x0193
#define mmDMCUB_REGION2_OFFSET_HIGH_BASE_IDX 2
#define mmDMCUB_REGION4_OFFSET 0x0196
#define mmDMCUB_REGION4_OFFSET_BASE_IDX 2
#define mmDMCUB_REGION4_OFFSET_HIGH 0x0197
#define mmDMCUB_REGION4_OFFSET_HIGH_BASE_IDX 2
#define mmDMCUB_REGION5_OFFSET 0x0198
#define mmDMCUB_REGION5_OFFSET_BASE_IDX 2
#define mmDMCUB_REGION5_OFFSET_HIGH 0x0199
#define mmDMCUB_REGION5_OFFSET_HIGH_BASE_IDX 2
#define mmDMCUB_REGION6_OFFSET 0x019a
#define mmDMCUB_REGION6_OFFSET_BASE_IDX 2
#define mmDMCUB_REGION6_OFFSET_HIGH 0x019b
#define mmDMCUB_REGION6_OFFSET_HIGH_BASE_IDX 2
#define mmDMCUB_REGION7_OFFSET 0x019c
#define mmDMCUB_REGION7_OFFSET_BASE_IDX 2
#define mmDMCUB_REGION7_OFFSET_HIGH 0x019d
#define mmDMCUB_REGION7_OFFSET_HIGH_BASE_IDX 2
#define mmDMCUB_REGION0_TOP_ADDRESS 0x019e
#define mmDMCUB_REGION0_TOP_ADDRESS_BASE_IDX 2
#define mmDMCUB_REGION1_TOP_ADDRESS 0x019f
#define mmDMCUB_REGION1_TOP_ADDRESS_BASE_IDX 2
#define mmDMCUB_REGION2_TOP_ADDRESS 0x01a0
#define mmDMCUB_REGION2_TOP_ADDRESS_BASE_IDX 2
#define mmDMCUB_REGION4_TOP_ADDRESS 0x01a1
#define mmDMCUB_REGION4_TOP_ADDRESS_BASE_IDX 2
#define mmDMCUB_REGION5_TOP_ADDRESS 0x01a2
#define mmDMCUB_REGION5_TOP_ADDRESS_BASE_IDX 2
#define mmDMCUB_REGION6_TOP_ADDRESS 0x01a3
#define mmDMCUB_REGION6_TOP_ADDRESS_BASE_IDX 2
#define mmDMCUB_REGION7_TOP_ADDRESS 0x01a4
#define mmDMCUB_REGION7_TOP_ADDRESS_BASE_IDX 2
#define mmDMCUB_REGION3_CW0_BASE_ADDRESS 0x01a5
#define mmDMCUB_REGION3_CW0_BASE_ADDRESS_BASE_IDX 2
#define mmDMCUB_REGION3_CW1_BASE_ADDRESS 0x01a6
#define mmDMCUB_REGION3_CW1_BASE_ADDRESS_BASE_IDX 2
#define mmDMCUB_REGION3_CW2_BASE_ADDRESS 0x01a7
#define mmDMCUB_REGION3_CW2_BASE_ADDRESS_BASE_IDX 2
#define mmDMCUB_REGION3_CW3_BASE_ADDRESS 0x01a8
#define mmDMCUB_REGION3_CW3_BASE_ADDRESS_BASE_IDX 2
#define mmDMCUB_REGION3_CW4_BASE_ADDRESS 0x01a9
#define mmDMCUB_REGION3_CW4_BASE_ADDRESS_BASE_IDX 2
#define mmDMCUB_REGION3_CW5_BASE_ADDRESS 0x01aa
#define mmDMCUB_REGION3_CW5_BASE_ADDRESS_BASE_IDX 2
#define mmDMCUB_REGION3_CW6_BASE_ADDRESS 0x01ab
#define mmDMCUB_REGION3_CW6_BASE_ADDRESS_BASE_IDX 2
#define mmDMCUB_REGION3_CW7_BASE_ADDRESS 0x01ac
#define mmDMCUB_REGION3_CW7_BASE_ADDRESS_BASE_IDX 2
#define mmDMCUB_REGION3_CW0_TOP_ADDRESS 0x01ad
#define mmDMCUB_REGION3_CW0_TOP_ADDRESS_BASE_IDX 2
#define mmDMCUB_REGION3_CW1_TOP_ADDRESS 0x01ae
#define mmDMCUB_REGION3_CW1_TOP_ADDRESS_BASE_IDX 2
#define mmDMCUB_REGION3_CW2_TOP_ADDRESS 0x01af
#define mmDMCUB_REGION3_CW2_TOP_ADDRESS_BASE_IDX 2
#define mmDMCUB_REGION3_CW3_TOP_ADDRESS 0x01b0
#define mmDMCUB_REGION3_CW3_TOP_ADDRESS_BASE_IDX 2
#define mmDMCUB_REGION3_CW4_TOP_ADDRESS 0x01b1
#define mmDMCUB_REGION3_CW4_TOP_ADDRESS_BASE_IDX 2
#define mmDMCUB_REGION3_CW5_TOP_ADDRESS 0x01b2
#define mmDMCUB_REGION3_CW5_TOP_ADDRESS_BASE_IDX 2
#define mmDMCUB_REGION3_CW6_TOP_ADDRESS 0x01b3
#define mmDMCUB_REGION3_CW6_TOP_ADDRESS_BASE_IDX 2
#define mmDMCUB_REGION3_CW7_TOP_ADDRESS 0x01b4
#define mmDMCUB_REGION3_CW7_TOP_ADDRESS_BASE_IDX 2
#define mmDMCUB_REGION3_CW0_OFFSET 0x01b5
#define mmDMCUB_REGION3_CW0_OFFSET_BASE_IDX 2
#define mmDMCUB_REGION3_CW0_OFFSET_HIGH 0x01b6
#define mmDMCUB_REGION3_CW0_OFFSET_HIGH_BASE_IDX 2
#define mmDMCUB_REGION3_CW1_OFFSET 0x01b7
#define mmDMCUB_REGION3_CW1_OFFSET_BASE_IDX 2
#define mmDMCUB_REGION3_CW1_OFFSET_HIGH 0x01b8
#define mmDMCUB_REGION3_CW1_OFFSET_HIGH_BASE_IDX 2
#define mmDMCUB_REGION3_CW2_OFFSET 0x01b9
#define mmDMCUB_REGION3_CW2_OFFSET_BASE_IDX 2
#define mmDMCUB_REGION3_CW2_OFFSET_HIGH 0x01ba
#define mmDMCUB_REGION3_CW2_OFFSET_HIGH_BASE_IDX 2
#define mmDMCUB_REGION3_CW3_OFFSET 0x01bb
#define mmDMCUB_REGION3_CW3_OFFSET_BASE_IDX 2
#define mmDMCUB_REGION3_CW3_OFFSET_HIGH 0x01bc
#define mmDMCUB_REGION3_CW3_OFFSET_HIGH_BASE_IDX 2
#define mmDMCUB_REGION3_CW4_OFFSET 0x01bd
#define mmDMCUB_REGION3_CW4_OFFSET_BASE_IDX 2
#define mmDMCUB_REGION3_CW4_OFFSET_HIGH 0x01be
#define mmDMCUB_REGION3_CW4_OFFSET_HIGH_BASE_IDX 2
#define mmDMCUB_REGION3_CW5_OFFSET 0x01bf
#define mmDMCUB_REGION3_CW5_OFFSET_BASE_IDX 2
#define mmDMCUB_REGION3_CW5_OFFSET_HIGH 0x01c0
#define mmDMCUB_REGION3_CW5_OFFSET_HIGH_BASE_IDX 2
#define mmDMCUB_REGION3_CW6_OFFSET 0x01c1
#define mmDMCUB_REGION3_CW6_OFFSET_BASE_IDX 2
#define mmDMCUB_REGION3_CW6_OFFSET_HIGH 0x01c2
#define mmDMCUB_REGION3_CW6_OFFSET_HIGH_BASE_IDX 2
#define mmDMCUB_REGION3_CW7_OFFSET 0x01c3
#define mmDMCUB_REGION3_CW7_OFFSET_BASE_IDX 2
#define mmDMCUB_REGION3_CW7_OFFSET_HIGH 0x01c4
#define mmDMCUB_REGION3_CW7_OFFSET_HIGH_BASE_IDX 2
#define mmDMCUB_INTERRUPT_ENABLE 0x01c5
#define mmDMCUB_INTERRUPT_ENABLE_BASE_IDX 2
#define mmDMCUB_INTERRUPT_ACK 0x01c6
#define mmDMCUB_INTERRUPT_ACK_BASE_IDX 2
#define mmDMCUB_INTERRUPT_STATUS 0x01c7
#define mmDMCUB_INTERRUPT_STATUS_BASE_IDX 2
#define mmDMCUB_INTERRUPT_TYPE 0x01c8
#define mmDMCUB_INTERRUPT_TYPE_BASE_IDX 2
#define mmDMCUB_EXT_INTERRUPT_STATUS 0x01c9
#define mmDMCUB_EXT_INTERRUPT_STATUS_BASE_IDX 2
#define mmDMCUB_EXT_INTERRUPT_CTXID 0x01ca
#define mmDMCUB_EXT_INTERRUPT_CTXID_BASE_IDX 2
#define mmDMCUB_EXT_INTERRUPT_ACK 0x01cb
#define mmDMCUB_EXT_INTERRUPT_ACK_BASE_IDX 2
#define mmDMCUB_INST_FETCH_FAULT_ADDR 0x01cc
#define mmDMCUB_INST_FETCH_FAULT_ADDR_BASE_IDX 2
#define mmDMCUB_DATA_WRITE_FAULT_ADDR 0x01cd
#define mmDMCUB_DATA_WRITE_FAULT_ADDR_BASE_IDX 2
#define mmDMCUB_SEC_CNTL 0x01ce
#define mmDMCUB_SEC_CNTL_BASE_IDX 2
#define mmDMCUB_MEM_CNTL 0x01cf
#define mmDMCUB_MEM_CNTL_BASE_IDX 2
#define mmDMCUB_INBOX0_BASE_ADDRESS 0x01d0
#define mmDMCUB_INBOX0_BASE_ADDRESS_BASE_IDX 2
#define mmDMCUB_INBOX0_SIZE 0x01d1
#define mmDMCUB_INBOX0_SIZE_BASE_IDX 2
#define mmDMCUB_INBOX0_WPTR 0x01d2
#define mmDMCUB_INBOX0_WPTR_BASE_IDX 2
#define mmDMCUB_INBOX0_RPTR 0x01d3
#define mmDMCUB_INBOX0_RPTR_BASE_IDX 2
#define mmDMCUB_INBOX1_BASE_ADDRESS 0x01d4
#define mmDMCUB_INBOX1_BASE_ADDRESS_BASE_IDX 2
#define mmDMCUB_INBOX1_SIZE 0x01d5
#define mmDMCUB_INBOX1_SIZE_BASE_IDX 2
#define mmDMCUB_INBOX1_WPTR 0x01d6
#define mmDMCUB_INBOX1_WPTR_BASE_IDX 2
#define mmDMCUB_INBOX1_RPTR 0x01d7
#define mmDMCUB_INBOX1_RPTR_BASE_IDX 2
#define mmDMCUB_OUTBOX0_BASE_ADDRESS 0x01d8
#define mmDMCUB_OUTBOX0_BASE_ADDRESS_BASE_IDX 2
#define mmDMCUB_OUTBOX0_SIZE 0x01d9
#define mmDMCUB_OUTBOX0_SIZE_BASE_IDX 2
#define mmDMCUB_OUTBOX0_WPTR 0x01da
#define mmDMCUB_OUTBOX0_WPTR_BASE_IDX 2
#define mmDMCUB_OUTBOX0_RPTR 0x01db
#define mmDMCUB_OUTBOX0_RPTR_BASE_IDX 2
#define mmDMCUB_OUTBOX1_BASE_ADDRESS 0x01dc
#define mmDMCUB_OUTBOX1_BASE_ADDRESS_BASE_IDX 2
#define mmDMCUB_OUTBOX1_SIZE 0x01dd
#define mmDMCUB_OUTBOX1_SIZE_BASE_IDX 2
#define mmDMCUB_OUTBOX1_WPTR 0x01de
#define mmDMCUB_OUTBOX1_WPTR_BASE_IDX 2
#define mmDMCUB_OUTBOX1_RPTR 0x01df
#define mmDMCUB_OUTBOX1_RPTR_BASE_IDX 2
#define mmDMCUB_TIMER_TRIGGER0 0x01e0
#define mmDMCUB_TIMER_TRIGGER0_BASE_IDX 2
#define mmDMCUB_TIMER_TRIGGER1 0x01e1
#define mmDMCUB_TIMER_TRIGGER1_BASE_IDX 2
#define mmDMCUB_TIMER_WINDOW 0x01e2
#define mmDMCUB_TIMER_WINDOW_BASE_IDX 2
#define mmDMCUB_SCRATCH0 0x01e3
#define mmDMCUB_SCRATCH0_BASE_IDX 2
#define mmDMCUB_SCRATCH1 0x01e4
#define mmDMCUB_SCRATCH1_BASE_IDX 2
#define mmDMCUB_SCRATCH2 0x01e5
#define mmDMCUB_SCRATCH2_BASE_IDX 2
#define mmDMCUB_SCRATCH3 0x01e6
#define mmDMCUB_SCRATCH3_BASE_IDX 2
#define mmDMCUB_SCRATCH4 0x01e7
#define mmDMCUB_SCRATCH4_BASE_IDX 2
#define mmDMCUB_SCRATCH5 0x01e8
#define mmDMCUB_SCRATCH5_BASE_IDX 2
#define mmDMCUB_SCRATCH6 0x01e9
#define mmDMCUB_SCRATCH6_BASE_IDX 2
#define mmDMCUB_SCRATCH7 0x01ea
#define mmDMCUB_SCRATCH7_BASE_IDX 2
#define mmDMCUB_SCRATCH8 0x01eb
#define mmDMCUB_SCRATCH8_BASE_IDX 2
#define mmDMCUB_SCRATCH9 0x01ec
#define mmDMCUB_SCRATCH9_BASE_IDX 2
#define mmDMCUB_SCRATCH10 0x01ed
#define mmDMCUB_SCRATCH10_BASE_IDX 2
#define mmDMCUB_SCRATCH11 0x01ee
#define mmDMCUB_SCRATCH11_BASE_IDX 2
#define mmDMCUB_SCRATCH12 0x01ef
#define mmDMCUB_SCRATCH12_BASE_IDX 2
#define mmDMCUB_SCRATCH13 0x01f0
#define mmDMCUB_SCRATCH13_BASE_IDX 2
#define mmDMCUB_SCRATCH14 0x01f1
#define mmDMCUB_SCRATCH14_BASE_IDX 2
#define mmDMCUB_SCRATCH15 0x01f2
#define mmDMCUB_SCRATCH15_BASE_IDX 2
#define mmDMCUB_CNTL 0x01f6
#define mmDMCUB_CNTL_BASE_IDX 2
#define mmDMCUB_GPINT_DATAIN0 0x01f7
#define mmDMCUB_GPINT_DATAIN0_BASE_IDX 2
#define mmDMCUB_GPINT_DATAIN1 0x01f8
#define mmDMCUB_GPINT_DATAIN1_BASE_IDX 2
#define mmDMCUB_GPINT_DATAOUT 0x01f9
#define mmDMCUB_GPINT_DATAOUT_BASE_IDX 2
#define mmDMCUB_UNDEFINED_ADDRESS_FAULT_ADDR 0x01fa
#define mmDMCUB_UNDEFINED_ADDRESS_FAULT_ADDR_BASE_IDX 2
#define mmDMCUB_LS_WAKE_INT_ENABLE 0x01fb
#define mmDMCUB_LS_WAKE_INT_ENABLE_BASE_IDX 2
#define mmDMCUB_MEM_PWR_CNTL 0x01fc
#define mmDMCUB_MEM_PWR_CNTL_BASE_IDX 2
#define mmDMCUB_TIMER_CURRENT 0x01fd
#define mmDMCUB_TIMER_CURRENT_BASE_IDX 2
#define mmDMCUB_PROC_ID 0x01ff
#define mmDMCUB_PROC_ID_BASE_IDX 2
// addressBlock: dce_dc_mmhubbub_mcif_wb0_dispdec
// base address: 0x0
#define mmMCIF_WB_BUFMGR_SW_CONTROL 0x0272
#define mmMCIF_WB_BUFMGR_SW_CONTROL_BASE_IDX 2
#define mmMCIF_WB_BUFMGR_STATUS 0x0274
#define mmMCIF_WB_BUFMGR_STATUS_BASE_IDX 2
#define mmMCIF_WB_BUF_PITCH 0x0275
#define mmMCIF_WB_BUF_PITCH_BASE_IDX 2
#define mmMCIF_WB_BUF_1_STATUS 0x0276
#define mmMCIF_WB_BUF_1_STATUS_BASE_IDX 2
#define mmMCIF_WB_BUF_1_STATUS2 0x0277
#define mmMCIF_WB_BUF_1_STATUS2_BASE_IDX 2
#define mmMCIF_WB_BUF_2_STATUS 0x0278
#define mmMCIF_WB_BUF_2_STATUS_BASE_IDX 2
#define mmMCIF_WB_BUF_2_STATUS2 0x0279
#define mmMCIF_WB_BUF_2_STATUS2_BASE_IDX 2
#define mmMCIF_WB_BUF_3_STATUS 0x027a
#define mmMCIF_WB_BUF_3_STATUS_BASE_IDX 2
#define mmMCIF_WB_BUF_3_STATUS2 0x027b
#define mmMCIF_WB_BUF_3_STATUS2_BASE_IDX 2
#define mmMCIF_WB_BUF_4_STATUS 0x027c
#define mmMCIF_WB_BUF_4_STATUS_BASE_IDX 2
#define mmMCIF_WB_BUF_4_STATUS2 0x027d
#define mmMCIF_WB_BUF_4_STATUS2_BASE_IDX 2
#define mmMCIF_WB_ARBITRATION_CONTROL 0x027e
#define mmMCIF_WB_ARBITRATION_CONTROL_BASE_IDX 2
#define mmMCIF_WB_SCLK_CHANGE 0x027f
#define mmMCIF_WB_SCLK_CHANGE_BASE_IDX 2
#define mmMCIF_WB_BUF_1_ADDR_Y 0x0282
#define mmMCIF_WB_BUF_1_ADDR_Y_BASE_IDX 2
#define mmMCIF_WB_BUF_1_ADDR_C 0x0284
#define mmMCIF_WB_BUF_1_ADDR_C_BASE_IDX 2
#define mmMCIF_WB_BUF_2_ADDR_Y 0x0286
#define mmMCIF_WB_BUF_2_ADDR_Y_BASE_IDX 2
#define mmMCIF_WB_BUF_2_ADDR_C 0x0288
#define mmMCIF_WB_BUF_2_ADDR_C_BASE_IDX 2
#define mmMCIF_WB_BUF_3_ADDR_Y 0x028a
#define mmMCIF_WB_BUF_3_ADDR_Y_BASE_IDX 2
#define mmMCIF_WB_BUF_3_ADDR_C 0x028c
#define mmMCIF_WB_BUF_3_ADDR_C_BASE_IDX 2
#define mmMCIF_WB_BUF_4_ADDR_Y 0x028e
#define mmMCIF_WB_BUF_4_ADDR_Y_BASE_IDX 2
#define mmMCIF_WB_BUF_4_ADDR_C 0x0290
#define mmMCIF_WB_BUF_4_ADDR_C_BASE_IDX 2
#define mmMCIF_WB_BUFMGR_VCE_CONTROL 0x0292
#define mmMCIF_WB_BUFMGR_VCE_CONTROL_BASE_IDX 2
#define mmMCIF_WB_NB_PSTATE_CONTROL 0x0293
#define mmMCIF_WB_NB_PSTATE_CONTROL_BASE_IDX 2
#define mmMCIF_WB_CLOCK_GATER_CONTROL 0x0294
#define mmMCIF_WB_CLOCK_GATER_CONTROL_BASE_IDX 2
#define mmMCIF_WB_SELF_REFRESH_CONTROL 0x0296
#define mmMCIF_WB_SELF_REFRESH_CONTROL_BASE_IDX 2
#define mmMULTI_LEVEL_QOS_CTRL 0x0297
#define mmMULTI_LEVEL_QOS_CTRL_BASE_IDX 2
#define mmMCIF_WB_BUF_LUMA_SIZE 0x0299
#define mmMCIF_WB_BUF_LUMA_SIZE_BASE_IDX 2
#define mmMCIF_WB_BUF_CHROMA_SIZE 0x029a
#define mmMCIF_WB_BUF_CHROMA_SIZE_BASE_IDX 2
#define mmMCIF_WB_BUF_1_ADDR_Y_HIGH 0x029b
#define mmMCIF_WB_BUF_1_ADDR_Y_HIGH_BASE_IDX 2
#define mmMCIF_WB_BUF_1_ADDR_C_HIGH 0x029c
#define mmMCIF_WB_BUF_1_ADDR_C_HIGH_BASE_IDX 2
#define mmMCIF_WB_BUF_2_ADDR_Y_HIGH 0x029d
#define mmMCIF_WB_BUF_2_ADDR_Y_HIGH_BASE_IDX 2
#define mmMCIF_WB_BUF_2_ADDR_C_HIGH 0x029e
#define mmMCIF_WB_BUF_2_ADDR_C_HIGH_BASE_IDX 2
#define mmMCIF_WB_BUF_3_ADDR_Y_HIGH 0x029f
#define mmMCIF_WB_BUF_3_ADDR_Y_HIGH_BASE_IDX 2
#define mmMCIF_WB_BUF_3_ADDR_C_HIGH 0x02a0
#define mmMCIF_WB_BUF_3_ADDR_C_HIGH_BASE_IDX 2
#define mmMCIF_WB_BUF_4_ADDR_Y_HIGH 0x02a1
#define mmMCIF_WB_BUF_4_ADDR_Y_HIGH_BASE_IDX 2
#define mmMCIF_WB_BUF_4_ADDR_C_HIGH 0x02a2
#define mmMCIF_WB_BUF_4_ADDR_C_HIGH_BASE_IDX 2
#define mmMCIF_WB_BUF_1_RESOLUTION 0x02a3
#define mmMCIF_WB_BUF_1_RESOLUTION_BASE_IDX 2
#define mmMCIF_WB_BUF_2_RESOLUTION 0x02a4
#define mmMCIF_WB_BUF_2_RESOLUTION_BASE_IDX 2
#define mmMCIF_WB_BUF_3_RESOLUTION 0x02a5
#define mmMCIF_WB_BUF_3_RESOLUTION_BASE_IDX 2
#define mmMCIF_WB_BUF_4_RESOLUTION 0x02a6
#define mmMCIF_WB_BUF_4_RESOLUTION_BASE_IDX 2
#define mmMCIF_WB_DRAM_SPEED_CHANGE_DURATION_VBI 0x02a7
#define mmMCIF_WB_DRAM_SPEED_CHANGE_DURATION_VBI_BASE_IDX 2
#define mmMCIF_WB_VMID_CONTROL 0x02a8
#define mmMCIF_WB_VMID_CONTROL_BASE_IDX 2
#define mmMCIF_WB_MIN_TTO 0x02a9
#define mmMCIF_WB_MIN_TTO_BASE_IDX 2
// addressBlock: dce_dc_mmhubbub_mmhubbub_dispdec
// base address: 0x0
#define mmMCIF_WB_NB_PSTATE_LATENCY_WATERMARK 0x02aa
#define mmMCIF_WB_NB_PSTATE_LATENCY_WATERMARK_BASE_IDX 2
#define mmMCIF_WB_WATERMARK 0x02ab
#define mmMCIF_WB_WATERMARK_BASE_IDX 2
#define mmMMHUBBUB_WARMUP_CONFIG 0x02ac
#define mmMMHUBBUB_WARMUP_CONFIG_BASE_IDX 2
#define mmMMHUBBUB_WARMUP_CONTROL_STATUS 0x02ad
#define mmMMHUBBUB_WARMUP_CONTROL_STATUS_BASE_IDX 2
#define mmMMHUBBUB_WARMUP_BASE_ADDR_LOW 0x02ae
#define mmMMHUBBUB_WARMUP_BASE_ADDR_LOW_BASE_IDX 2
#define mmMMHUBBUB_WARMUP_BASE_ADDR_HIGH 0x02af
#define mmMMHUBBUB_WARMUP_BASE_ADDR_HIGH_BASE_IDX 2
#define mmMMHUBBUB_WARMUP_ADDR_REGION 0x02b0
#define mmMMHUBBUB_WARMUP_ADDR_REGION_BASE_IDX 2
#define mmMMHUBBUB_MIN_TTO 0x02b1
#define mmMMHUBBUB_MIN_TTO_BASE_IDX 2
#define mmWBIF_SMU_WM_CONTROL 0x0333
#define mmWBIF_SMU_WM_CONTROL_BASE_IDX 2
#define mmWBIF0_MISC_CTRL 0x0334
#define mmWBIF0_MISC_CTRL_BASE_IDX 2
#define mmWBIF0_PHASE0_OUTSTANDING_COUNTER 0x0335
#define mmWBIF0_PHASE0_OUTSTANDING_COUNTER_BASE_IDX 2
#define mmWBIF0_PHASE1_OUTSTANDING_COUNTER 0x0336
#define mmWBIF0_PHASE1_OUTSTANDING_COUNTER_BASE_IDX 2
#define mmVGA_SRC_SPLIT_CNTL 0x033d
#define mmVGA_SRC_SPLIT_CNTL_BASE_IDX 2
#define mmMMHUBBUB_MEM_PWR_STATUS 0x033e
#define mmMMHUBBUB_MEM_PWR_STATUS_BASE_IDX 2
#define mmMMHUBBUB_MEM_PWR_CNTL 0x033f
#define mmMMHUBBUB_MEM_PWR_CNTL_BASE_IDX 2
#define mmMMHUBBUB_CLOCK_CNTL 0x0340
#define mmMMHUBBUB_CLOCK_CNTL_BASE_IDX 2
#define mmMMHUBBUB_SOFT_RESET 0x0341
#define mmMMHUBBUB_SOFT_RESET_BASE_IDX 2
#define mmDMU_IF_ERR_STATUS 0x0345
#define mmDMU_IF_ERR_STATUS_BASE_IDX 2
#define mmMMHUBBUB_CLIENT_UNIT_ID 0x0346
#define mmMMHUBBUB_CLIENT_UNIT_ID_BASE_IDX 2
#define mmMMHUBBUB_WARMUP_VMID_CONTROL 0x0348
#define mmMMHUBBUB_WARMUP_VMID_CONTROL_BASE_IDX 2
// addressBlock: dce_dc_mmhubbub_vgaif_dispdec
// base address: 0x0
#define mmMCIF_CONTROL 0x034a
#define mmMCIF_CONTROL_BASE_IDX 2
#define mmMCIF_WRITE_COMBINE_CONTROL 0x034b
#define mmMCIF_WRITE_COMBINE_CONTROL_BASE_IDX 2
#define mmMCIF_PHASE0_OUTSTANDING_COUNTER 0x034e
#define mmMCIF_PHASE0_OUTSTANDING_COUNTER_BASE_IDX 2
#define mmMCIF_PHASE1_OUTSTANDING_COUNTER 0x034f
#define mmMCIF_PHASE1_OUTSTANDING_COUNTER_BASE_IDX 2
#define mmMCIF_PHASE2_OUTSTANDING_COUNTER 0x0350
#define mmMCIF_PHASE2_OUTSTANDING_COUNTER_BASE_IDX 2
// addressBlock: dce_dc_mmhubbub_mmhubbub_dcperfmon_dc_perfmon_dispdec
// base address: 0xd48
#define mmDC_PERFMON3_PERFCOUNTER_CNTL 0x0352
#define mmDC_PERFMON3_PERFCOUNTER_CNTL_BASE_IDX 2
#define mmDC_PERFMON3_PERFCOUNTER_CNTL2 0x0353
#define mmDC_PERFMON3_PERFCOUNTER_CNTL2_BASE_IDX 2
#define mmDC_PERFMON3_PERFCOUNTER_STATE 0x0354
#define mmDC_PERFMON3_PERFCOUNTER_STATE_BASE_IDX 2
#define mmDC_PERFMON3_PERFMON_CNTL 0x0355
#define mmDC_PERFMON3_PERFMON_CNTL_BASE_IDX 2
#define mmDC_PERFMON3_PERFMON_CNTL2 0x0356
#define mmDC_PERFMON3_PERFMON_CNTL2_BASE_IDX 2
#define mmDC_PERFMON3_PERFMON_CVALUE_INT_MISC 0x0357
#define mmDC_PERFMON3_PERFMON_CVALUE_INT_MISC_BASE_IDX 2
#define mmDC_PERFMON3_PERFMON_CVALUE_LOW 0x0358
#define mmDC_PERFMON3_PERFMON_CVALUE_LOW_BASE_IDX 2
#define mmDC_PERFMON3_PERFMON_HI 0x0359
#define mmDC_PERFMON3_PERFMON_HI_BASE_IDX 2
#define mmDC_PERFMON3_PERFMON_LOW 0x035a
#define mmDC_PERFMON3_PERFMON_LOW_BASE_IDX 2
// addressBlock: dce_dc_hda_azf0stream0_dispdec
// base address: 0x0
#define mmAZF0STREAM0_AZALIA_STREAM_INDEX 0x035e
#define mmAZF0STREAM0_AZALIA_STREAM_INDEX_BASE_IDX 2
#define mmAZF0STREAM0_AZALIA_STREAM_DATA 0x035f
#define mmAZF0STREAM0_AZALIA_STREAM_DATA_BASE_IDX 2
// addressBlock: dce_dc_hda_azf0stream1_dispdec
// base address: 0x8
#define mmAZF0STREAM1_AZALIA_STREAM_INDEX 0x0360
#define mmAZF0STREAM1_AZALIA_STREAM_INDEX_BASE_IDX 2
#define mmAZF0STREAM1_AZALIA_STREAM_DATA 0x0361
#define mmAZF0STREAM1_AZALIA_STREAM_DATA_BASE_IDX 2
// addressBlock: dce_dc_hda_azf0stream2_dispdec
// base address: 0x10
#define mmAZF0STREAM2_AZALIA_STREAM_INDEX 0x0362
#define mmAZF0STREAM2_AZALIA_STREAM_INDEX_BASE_IDX 2
#define mmAZF0STREAM2_AZALIA_STREAM_DATA 0x0363
#define mmAZF0STREAM2_AZALIA_STREAM_DATA_BASE_IDX 2
// addressBlock: dce_dc_hda_azf0stream3_dispdec
// base address: 0x18
#define mmAZF0STREAM3_AZALIA_STREAM_INDEX 0x0364
#define mmAZF0STREAM3_AZALIA_STREAM_INDEX_BASE_IDX 2
#define mmAZF0STREAM3_AZALIA_STREAM_DATA 0x0365
#define mmAZF0STREAM3_AZALIA_STREAM_DATA_BASE_IDX 2
// addressBlock: dce_dc_hda_azf0stream4_dispdec
// base address: 0x20
#define mmAZF0STREAM4_AZALIA_STREAM_INDEX 0x0366
#define mmAZF0STREAM4_AZALIA_STREAM_INDEX_BASE_IDX 2
#define mmAZF0STREAM4_AZALIA_STREAM_DATA 0x0367
#define mmAZF0STREAM4_AZALIA_STREAM_DATA_BASE_IDX 2
// addressBlock: dce_dc_hda_azf0stream5_dispdec
// base address: 0x28
#define mmAZF0STREAM5_AZALIA_STREAM_INDEX 0x0368
#define mmAZF0STREAM5_AZALIA_STREAM_INDEX_BASE_IDX 2
#define mmAZF0STREAM5_AZALIA_STREAM_DATA 0x0369
#define mmAZF0STREAM5_AZALIA_STREAM_DATA_BASE_IDX 2
// addressBlock: dce_dc_hda_azf0stream6_dispdec
// base address: 0x30
#define mmAZF0STREAM6_AZALIA_STREAM_INDEX 0x036a
#define mmAZF0STREAM6_AZALIA_STREAM_INDEX_BASE_IDX 2
#define mmAZF0STREAM6_AZALIA_STREAM_DATA 0x036b
#define mmAZF0STREAM6_AZALIA_STREAM_DATA_BASE_IDX 2
// addressBlock: dce_dc_hda_azf0stream7_dispdec
// base address: 0x38
#define mmAZF0STREAM7_AZALIA_STREAM_INDEX 0x036c
#define mmAZF0STREAM7_AZALIA_STREAM_INDEX_BASE_IDX 2
#define mmAZF0STREAM7_AZALIA_STREAM_DATA 0x036d
#define mmAZF0STREAM7_AZALIA_STREAM_DATA_BASE_IDX 2
// addressBlock: dce_dc_hda_az_misc_dispdec
// base address: 0x0
#define mmAZ_CLOCK_CNTL 0x0372
#define mmAZ_CLOCK_CNTL_BASE_IDX 2
// addressBlock: dce_dc_hda_az_dcperfmon_dc_perfmon_dispdec
// base address: 0xde8
#define mmDC_PERFMON4_PERFCOUNTER_CNTL 0x037a
#define mmDC_PERFMON4_PERFCOUNTER_CNTL_BASE_IDX 2
#define mmDC_PERFMON4_PERFCOUNTER_CNTL2 0x037b
#define mmDC_PERFMON4_PERFCOUNTER_CNTL2_BASE_IDX 2
#define mmDC_PERFMON4_PERFCOUNTER_STATE 0x037c
#define mmDC_PERFMON4_PERFCOUNTER_STATE_BASE_IDX 2
#define mmDC_PERFMON4_PERFMON_CNTL 0x037d
#define mmDC_PERFMON4_PERFMON_CNTL_BASE_IDX 2
#define mmDC_PERFMON4_PERFMON_CNTL2 0x037e
#define mmDC_PERFMON4_PERFMON_CNTL2_BASE_IDX 2
#define mmDC_PERFMON4_PERFMON_CVALUE_INT_MISC 0x037f
#define mmDC_PERFMON4_PERFMON_CVALUE_INT_MISC_BASE_IDX 2
#define mmDC_PERFMON4_PERFMON_CVALUE_LOW 0x0380
#define mmDC_PERFMON4_PERFMON_CVALUE_LOW_BASE_IDX 2
#define mmDC_PERFMON4_PERFMON_HI 0x0381
#define mmDC_PERFMON4_PERFMON_HI_BASE_IDX 2
#define mmDC_PERFMON4_PERFMON_LOW 0x0382
#define mmDC_PERFMON4_PERFMON_LOW_BASE_IDX 2
// addressBlock: dce_dc_hda_azf0endpoint0_dispdec
// base address: 0x0
#define mmAZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_INDEX 0x0386
#define mmAZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_INDEX_BASE_IDX 2
#define mmAZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_DATA 0x0387
#define mmAZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_DATA_BASE_IDX 2
// addressBlock: dce_dc_hda_azf0endpoint1_dispdec
// base address: 0x18
#define mmAZF0ENDPOINT1_AZALIA_F0_CODEC_ENDPOINT_INDEX 0x038c
#define mmAZF0ENDPOINT1_AZALIA_F0_CODEC_ENDPOINT_INDEX_BASE_IDX 2
#define mmAZF0ENDPOINT1_AZALIA_F0_CODEC_ENDPOINT_DATA 0x038d
#define mmAZF0ENDPOINT1_AZALIA_F0_CODEC_ENDPOINT_DATA_BASE_IDX 2
// addressBlock: dce_dc_hda_azf0endpoint2_dispdec
// base address: 0x30
#define mmAZF0ENDPOINT2_AZALIA_F0_CODEC_ENDPOINT_INDEX 0x0392
#define mmAZF0ENDPOINT2_AZALIA_F0_CODEC_ENDPOINT_INDEX_BASE_IDX 2
#define mmAZF0ENDPOINT2_AZALIA_F0_CODEC_ENDPOINT_DATA 0x0393
#define mmAZF0ENDPOINT2_AZALIA_F0_CODEC_ENDPOINT_DATA_BASE_IDX 2
// addressBlock: dce_dc_hda_azf0endpoint3_dispdec
// base address: 0x48
#define mmAZF0ENDPOINT3_AZALIA_F0_CODEC_ENDPOINT_INDEX 0x0398
#define mmAZF0ENDPOINT3_AZALIA_F0_CODEC_ENDPOINT_INDEX_BASE_IDX 2
#define mmAZF0ENDPOINT3_AZALIA_F0_CODEC_ENDPOINT_DATA 0x0399
#define mmAZF0ENDPOINT3_AZALIA_F0_CODEC_ENDPOINT_DATA_BASE_IDX 2
// addressBlock: dce_dc_hda_azf0endpoint4_dispdec
// base address: 0x60
#define mmAZF0ENDPOINT4_AZALIA_F0_CODEC_ENDPOINT_INDEX 0x039e
#define mmAZF0ENDPOINT4_AZALIA_F0_CODEC_ENDPOINT_INDEX_BASE_IDX 2
#define mmAZF0ENDPOINT4_AZALIA_F0_CODEC_ENDPOINT_DATA 0x039f
#define mmAZF0ENDPOINT4_AZALIA_F0_CODEC_ENDPOINT_DATA_BASE_IDX 2
// addressBlock: dce_dc_hda_azf0endpoint5_dispdec
// base address: 0x78
#define mmAZF0ENDPOINT5_AZALIA_F0_CODEC_ENDPOINT_INDEX 0x03a4
#define mmAZF0ENDPOINT5_AZALIA_F0_CODEC_ENDPOINT_INDEX_BASE_IDX 2
#define mmAZF0ENDPOINT5_AZALIA_F0_CODEC_ENDPOINT_DATA 0x03a5
#define mmAZF0ENDPOINT5_AZALIA_F0_CODEC_ENDPOINT_DATA_BASE_IDX 2
// addressBlock: dce_dc_hda_azf0endpoint6_dispdec
// base address: 0x90
#define mmAZF0ENDPOINT6_AZALIA_F0_CODEC_ENDPOINT_INDEX 0x03aa
#define mmAZF0ENDPOINT6_AZALIA_F0_CODEC_ENDPOINT_INDEX_BASE_IDX 2
#define mmAZF0ENDPOINT6_AZALIA_F0_CODEC_ENDPOINT_DATA 0x03ab
#define mmAZF0ENDPOINT6_AZALIA_F0_CODEC_ENDPOINT_DATA_BASE_IDX 2
// addressBlock: dce_dc_hda_azf0endpoint7_dispdec
// base address: 0xa8
#define mmAZF0ENDPOINT7_AZALIA_F0_CODEC_ENDPOINT_INDEX 0x03b0
#define mmAZF0ENDPOINT7_AZALIA_F0_CODEC_ENDPOINT_INDEX_BASE_IDX 2
#define mmAZF0ENDPOINT7_AZALIA_F0_CODEC_ENDPOINT_DATA 0x03b1
#define mmAZF0ENDPOINT7_AZALIA_F0_CODEC_ENDPOINT_DATA_BASE_IDX 2
// addressBlock: dce_dc_hda_azf0controller_dispdec
// base address: 0x0
#define mmAZALIA_CONTROLLER_CLOCK_GATING 0x03c2
#define mmAZALIA_CONTROLLER_CLOCK_GATING_BASE_IDX 2
#define mmAZALIA_AUDIO_DTO 0x03c3
#define mmAZALIA_AUDIO_DTO_BASE_IDX 2
#define mmAZALIA_AUDIO_DTO_CONTROL 0x03c4
#define mmAZALIA_AUDIO_DTO_CONTROL_BASE_IDX 2
#define mmAZALIA_SOCCLK_CONTROL 0x03c5
#define mmAZALIA_SOCCLK_CONTROL_BASE_IDX 2
#define mmAZALIA_UNDERFLOW_FILLER_SAMPLE 0x03c6
#define mmAZALIA_UNDERFLOW_FILLER_SAMPLE_BASE_IDX 2
#define mmAZALIA_DATA_DMA_CONTROL 0x03c7
#define mmAZALIA_DATA_DMA_CONTROL_BASE_IDX 2
#define mmAZALIA_BDL_DMA_CONTROL 0x03c8
#define mmAZALIA_BDL_DMA_CONTROL_BASE_IDX 2
#define mmAZALIA_RIRB_AND_DP_CONTROL 0x03c9
#define mmAZALIA_RIRB_AND_DP_CONTROL_BASE_IDX 2
#define mmAZALIA_CORB_DMA_CONTROL 0x03ca
#define mmAZALIA_CORB_DMA_CONTROL_BASE_IDX 2
#define mmAZALIA_APPLICATION_POSITION_IN_CYCLIC_BUFFER 0x03d1
#define mmAZALIA_APPLICATION_POSITION_IN_CYCLIC_BUFFER_BASE_IDX 2
#define mmAZALIA_CYCLIC_BUFFER_SYNC 0x03d2
#define mmAZALIA_CYCLIC_BUFFER_SYNC_BASE_IDX 2
#define mmAZALIA_GLOBAL_CAPABILITIES 0x03d3
#define mmAZALIA_GLOBAL_CAPABILITIES_BASE_IDX 2
#define mmAZALIA_OUTPUT_PAYLOAD_CAPABILITY 0x03d4
#define mmAZALIA_OUTPUT_PAYLOAD_CAPABILITY_BASE_IDX 2
#define mmAZALIA_OUTPUT_STREAM_ARBITER_CONTROL 0x03d5
#define mmAZALIA_OUTPUT_STREAM_ARBITER_CONTROL_BASE_IDX 2
#define mmAZALIA_INPUT_PAYLOAD_CAPABILITY 0x03d6
#define mmAZALIA_INPUT_PAYLOAD_CAPABILITY_BASE_IDX 2
#define mmAZALIA_INPUT_CRC0_CONTROL0 0x03d9
#define mmAZALIA_INPUT_CRC0_CONTROL0_BASE_IDX 2
#define mmAZALIA_INPUT_CRC0_CONTROL1 0x03da
#define mmAZALIA_INPUT_CRC0_CONTROL1_BASE_IDX 2
#define mmAZALIA_INPUT_CRC0_CONTROL2 0x03db
#define mmAZALIA_INPUT_CRC0_CONTROL2_BASE_IDX 2
#define mmAZALIA_INPUT_CRC0_CONTROL3 0x03dc
#define mmAZALIA_INPUT_CRC0_CONTROL3_BASE_IDX 2
#define mmAZALIA_INPUT_CRC0_RESULT 0x03dd
#define mmAZALIA_INPUT_CRC0_RESULT_BASE_IDX 2
#define mmAZALIA_INPUT_CRC1_CONTROL0 0x03de
#define mmAZALIA_INPUT_CRC1_CONTROL0_BASE_IDX 2
#define mmAZALIA_INPUT_CRC1_CONTROL1 0x03df
#define mmAZALIA_INPUT_CRC1_CONTROL1_BASE_IDX 2
#define mmAZALIA_INPUT_CRC1_CONTROL2 0x03e0
#define mmAZALIA_INPUT_CRC1_CONTROL2_BASE_IDX 2
#define mmAZALIA_INPUT_CRC1_CONTROL3 0x03e1
#define mmAZALIA_INPUT_CRC1_CONTROL3_BASE_IDX 2
#define mmAZALIA_INPUT_CRC1_RESULT 0x03e2
#define mmAZALIA_INPUT_CRC1_RESULT_BASE_IDX 2
#define mmAZALIA_CRC0_CONTROL0 0x03e3
#define mmAZALIA_CRC0_CONTROL0_BASE_IDX 2
#define mmAZALIA_CRC0_CONTROL1 0x03e4
#define mmAZALIA_CRC0_CONTROL1_BASE_IDX 2
#define mmAZALIA_CRC0_CONTROL2 0x03e5
#define mmAZALIA_CRC0_CONTROL2_BASE_IDX 2
#define mmAZALIA_CRC0_CONTROL3 0x03e6
#define mmAZALIA_CRC0_CONTROL3_BASE_IDX 2
#define mmAZALIA_CRC0_RESULT 0x03e7
#define mmAZALIA_CRC0_RESULT_BASE_IDX 2
#define mmAZALIA_CRC1_CONTROL0 0x03e8
#define mmAZALIA_CRC1_CONTROL0_BASE_IDX 2
#define mmAZALIA_CRC1_CONTROL1 0x03e9
#define mmAZALIA_CRC1_CONTROL1_BASE_IDX 2
#define mmAZALIA_CRC1_CONTROL2 0x03ea
#define mmAZALIA_CRC1_CONTROL2_BASE_IDX 2
#define mmAZALIA_CRC1_CONTROL3 0x03eb
#define mmAZALIA_CRC1_CONTROL3_BASE_IDX 2
#define mmAZALIA_CRC1_RESULT 0x03ec
#define mmAZALIA_CRC1_RESULT_BASE_IDX 2
#define mmAZALIA_MEM_PWR_CTRL 0x03ee
#define mmAZALIA_MEM_PWR_CTRL_BASE_IDX 2
#define mmAZALIA_MEM_PWR_STATUS 0x03ef
#define mmAZALIA_MEM_PWR_STATUS_BASE_IDX 2
// addressBlock: dce_dc_hda_azf0root_dispdec
// base address: 0x0
#define mmAZALIA_F0_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID 0x0406
#define mmAZALIA_F0_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID_BASE_IDX 2
#define mmAZALIA_F0_CODEC_ROOT_PARAMETER_REVISION_ID 0x0407
#define mmAZALIA_F0_CODEC_ROOT_PARAMETER_REVISION_ID_BASE_IDX 2
#define mmAZALIA_F0_CODEC_CHANNEL_COUNT_CONTROL 0x0408
#define mmAZALIA_F0_CODEC_CHANNEL_COUNT_CONTROL_BASE_IDX 2
#define mmAZALIA_F0_CODEC_RESYNC_FIFO_CONTROL 0x0409
#define mmAZALIA_F0_CODEC_RESYNC_FIFO_CONTROL_BASE_IDX 2
#define mmAZALIA_F0_CODEC_FUNCTION_PARAMETER_GROUP_TYPE 0x040a
#define mmAZALIA_F0_CODEC_FUNCTION_PARAMETER_GROUP_TYPE_BASE_IDX 2
#define mmAZALIA_F0_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES 0x040b
#define your_sha256_hashDX 2
#define mmAZALIA_F0_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS 0x040c
#define mmAZALIA_F0_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS_BASE_IDX 2
#define mmAZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES 0x040d
#define mmAZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES_BASE_IDX 2
#define mmAZALIA_F0_CODEC_FUNCTION_CONTROL_POWER_STATE 0x040e
#define mmAZALIA_F0_CODEC_FUNCTION_CONTROL_POWER_STATE_BASE_IDX 2
#define mmAZALIA_F0_CODEC_FUNCTION_CONTROL_RESET 0x040f
#define mmAZALIA_F0_CODEC_FUNCTION_CONTROL_RESET_BASE_IDX 2
#define mmAZALIA_F0_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID 0x0410
#define your_sha256_hashX 2
#define mmAZALIA_F0_CODEC_FUNCTION_CONTROL_CONVERTER_SYNCHRONIZATION 0x0411
#define your_sha256_hashE_IDX 2
#define mmCC_RCU_DC_AUDIO_PORT_CONNECTIVITY 0x0412
#define mmCC_RCU_DC_AUDIO_PORT_CONNECTIVITY_BASE_IDX 2
#define mmCC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY 0x0413
#define mmCC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_BASE_IDX 2
#define mmAZALIA_F0_GTC_GROUP_OFFSET0 0x0415
#define mmAZALIA_F0_GTC_GROUP_OFFSET0_BASE_IDX 2
#define mmAZALIA_F0_GTC_GROUP_OFFSET1 0x0416
#define mmAZALIA_F0_GTC_GROUP_OFFSET1_BASE_IDX 2
#define mmAZALIA_F0_GTC_GROUP_OFFSET2 0x0417
#define mmAZALIA_F0_GTC_GROUP_OFFSET2_BASE_IDX 2
#define mmAZALIA_F0_GTC_GROUP_OFFSET3 0x0418
#define mmAZALIA_F0_GTC_GROUP_OFFSET3_BASE_IDX 2
#define mmAZALIA_F0_GTC_GROUP_OFFSET4 0x0419
#define mmAZALIA_F0_GTC_GROUP_OFFSET4_BASE_IDX 2
#define mmAZALIA_F0_GTC_GROUP_OFFSET5 0x041a
#define mmAZALIA_F0_GTC_GROUP_OFFSET5_BASE_IDX 2
#define mmAZALIA_F0_GTC_GROUP_OFFSET6 0x041b
#define mmAZALIA_F0_GTC_GROUP_OFFSET6_BASE_IDX 2
#define mmREG_DC_AUDIO_PORT_CONNECTIVITY 0x041c
#define mmREG_DC_AUDIO_PORT_CONNECTIVITY_BASE_IDX 2
#define mmREG_DC_AUDIO_INPUT_PORT_CONNECTIVITY 0x041d
#define mmREG_DC_AUDIO_INPUT_PORT_CONNECTIVITY_BASE_IDX 2
// addressBlock: dce_dc_hda_azf0stream8_dispdec
// base address: 0x320
#define mmAZF0STREAM8_AZALIA_STREAM_INDEX 0x0426
#define mmAZF0STREAM8_AZALIA_STREAM_INDEX_BASE_IDX 2
#define mmAZF0STREAM8_AZALIA_STREAM_DATA 0x0427
#define mmAZF0STREAM8_AZALIA_STREAM_DATA_BASE_IDX 2
// addressBlock: dce_dc_hda_azf0stream9_dispdec
// base address: 0x328
#define mmAZF0STREAM9_AZALIA_STREAM_INDEX 0x0428
#define mmAZF0STREAM9_AZALIA_STREAM_INDEX_BASE_IDX 2
#define mmAZF0STREAM9_AZALIA_STREAM_DATA 0x0429
#define mmAZF0STREAM9_AZALIA_STREAM_DATA_BASE_IDX 2
// addressBlock: dce_dc_hda_azf0stream10_dispdec
// base address: 0x330
#define mmAZF0STREAM10_AZALIA_STREAM_INDEX 0x042a
#define mmAZF0STREAM10_AZALIA_STREAM_INDEX_BASE_IDX 2
#define mmAZF0STREAM10_AZALIA_STREAM_DATA 0x042b
#define mmAZF0STREAM10_AZALIA_STREAM_DATA_BASE_IDX 2
// addressBlock: dce_dc_hda_azf0stream11_dispdec
// base address: 0x338
#define mmAZF0STREAM11_AZALIA_STREAM_INDEX 0x042c
#define mmAZF0STREAM11_AZALIA_STREAM_INDEX_BASE_IDX 2
#define mmAZF0STREAM11_AZALIA_STREAM_DATA 0x042d
#define mmAZF0STREAM11_AZALIA_STREAM_DATA_BASE_IDX 2
// addressBlock: dce_dc_hda_azf0stream12_dispdec
// base address: 0x340
#define mmAZF0STREAM12_AZALIA_STREAM_INDEX 0x042e
#define mmAZF0STREAM12_AZALIA_STREAM_INDEX_BASE_IDX 2
#define mmAZF0STREAM12_AZALIA_STREAM_DATA 0x042f
#define mmAZF0STREAM12_AZALIA_STREAM_DATA_BASE_IDX 2
// addressBlock: dce_dc_hda_azf0stream13_dispdec
// base address: 0x348
#define mmAZF0STREAM13_AZALIA_STREAM_INDEX 0x0430
#define mmAZF0STREAM13_AZALIA_STREAM_INDEX_BASE_IDX 2
#define mmAZF0STREAM13_AZALIA_STREAM_DATA 0x0431
#define mmAZF0STREAM13_AZALIA_STREAM_DATA_BASE_IDX 2
// addressBlock: dce_dc_hda_azf0stream14_dispdec
// base address: 0x350
#define mmAZF0STREAM14_AZALIA_STREAM_INDEX 0x0432
#define mmAZF0STREAM14_AZALIA_STREAM_INDEX_BASE_IDX 2
#define mmAZF0STREAM14_AZALIA_STREAM_DATA 0x0433
#define mmAZF0STREAM14_AZALIA_STREAM_DATA_BASE_IDX 2
// addressBlock: dce_dc_hda_azf0stream15_dispdec
// base address: 0x358
#define mmAZF0STREAM15_AZALIA_STREAM_INDEX 0x0434
#define mmAZF0STREAM15_AZALIA_STREAM_INDEX_BASE_IDX 2
#define mmAZF0STREAM15_AZALIA_STREAM_DATA 0x0435
#define mmAZF0STREAM15_AZALIA_STREAM_DATA_BASE_IDX 2
// addressBlock: dce_dc_hda_azf0inputendpoint0_dispdec
// base address: 0x0
#define mmAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX 0x043a
#define your_sha256_hashDX 2
#define mmAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA 0x043b
#define your_sha256_hashX 2
// addressBlock: dce_dc_hda_azf0inputendpoint1_dispdec
// base address: 0x10
#define mmAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX 0x043e
#define your_sha256_hashDX 2
#define mmAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA 0x043f
#define your_sha256_hashX 2
// addressBlock: dce_dc_hda_azf0inputendpoint2_dispdec
// base address: 0x20
#define mmAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX 0x0442
#define your_sha256_hashDX 2
#define mmAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA 0x0443
#define your_sha256_hashX 2
// addressBlock: dce_dc_hda_azf0inputendpoint3_dispdec
// base address: 0x30
#define mmAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX 0x0446
#define your_sha256_hashDX 2
#define mmAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA 0x0447
#define your_sha256_hashX 2
// addressBlock: dce_dc_hda_azf0inputendpoint4_dispdec
// base address: 0x40
#define mmAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX 0x044a
#define your_sha256_hashDX 2
#define mmAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA 0x044b
#define your_sha256_hashX 2
// addressBlock: dce_dc_hda_azf0inputendpoint5_dispdec
// base address: 0x50
#define mmAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX 0x044e
#define your_sha256_hashDX 2
#define mmAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA 0x044f
#define your_sha256_hashX 2
// addressBlock: dce_dc_hda_azf0inputendpoint6_dispdec
// base address: 0x60
#define mmAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX 0x0452
#define your_sha256_hashDX 2
#define mmAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA 0x0453
#define your_sha256_hashX 2
// addressBlock: dce_dc_hda_azf0inputendpoint7_dispdec
// base address: 0x70
#define mmAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX 0x0456
#define your_sha256_hashDX 2
#define mmAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA 0x0457
#define your_sha256_hashX 2
// addressBlock: dce_dc_dchubbub_hubbub_sdpif_dispdec
// base address: 0x0
#define mmDCHUBBUB_SDPIF_CFG0 0x048f
#define mmDCHUBBUB_SDPIF_CFG0_BASE_IDX 2
#define mmVM_REQUEST_PHYSICAL 0x0490
#define mmVM_REQUEST_PHYSICAL_BASE_IDX 2
#define mmDCHUBBUB_FORCE_IO_STATUS_0 0x0491
#define mmDCHUBBUB_FORCE_IO_STATUS_0_BASE_IDX 2
#define mmDCHUBBUB_FORCE_IO_STATUS_1 0x0492
#define mmDCHUBBUB_FORCE_IO_STATUS_1_BASE_IDX 2
#define mmDCN_VM_FB_LOCATION_BASE 0x0493
#define mmDCN_VM_FB_LOCATION_BASE_BASE_IDX 2
#define mmDCN_VM_FB_LOCATION_TOP 0x0494
#define mmDCN_VM_FB_LOCATION_TOP_BASE_IDX 2
#define mmDCN_VM_FB_OFFSET 0x0495
#define mmDCN_VM_FB_OFFSET_BASE_IDX 2
#define mmDCN_VM_AGP_BOT 0x0496
#define mmDCN_VM_AGP_BOT_BASE_IDX 2
#define mmDCN_VM_AGP_TOP 0x0497
#define mmDCN_VM_AGP_TOP_BASE_IDX 2
#define mmDCN_VM_AGP_BASE 0x0498
#define mmDCN_VM_AGP_BASE_BASE_IDX 2
#define mmDCN_VM_LOCAL_HBM_ADDRESS_START 0x0499
#define mmDCN_VM_LOCAL_HBM_ADDRESS_START_BASE_IDX 2
#define mmDCN_VM_LOCAL_HBM_ADDRESS_END 0x049a
#define mmDCN_VM_LOCAL_HBM_ADDRESS_END_BASE_IDX 2
#define mmDCN_VM_LOCAL_HBM_ADDRESS_LOCK_CNTL 0x049b
#define mmDCN_VM_LOCAL_HBM_ADDRESS_LOCK_CNTL_BASE_IDX 2
#define mmDCHUBBUB_SDPIF_MEM_PWR_CTRL 0x04ba
#define mmDCHUBBUB_SDPIF_MEM_PWR_CTRL_BASE_IDX 2
#define mmDCHUBBUB_SDPIF_MEM_PWR_STATUS 0x04bb
#define mmDCHUBBUB_SDPIF_MEM_PWR_STATUS_BASE_IDX 2
#define mmDCHUBBUB_SDPIF_CFG1 0x04bf
#define mmDCHUBBUB_SDPIF_CFG1_BASE_IDX 2
#define mmDCHUBBUB_SDPIF_CFG2 0x04c0
#define mmDCHUBBUB_SDPIF_CFG2_BASE_IDX 2
// addressBlock: dce_dc_dchubbub_hubbub_ret_path_dispdec
// base address: 0x0
#define mmDCHUBBUB_RET_PATH_DCC_CFG 0x04cf
#define mmDCHUBBUB_RET_PATH_DCC_CFG_BASE_IDX 2
#define mmDCHUBBUB_RET_PATH_DCC_CFG0_0 0x04d0
#define mmDCHUBBUB_RET_PATH_DCC_CFG0_0_BASE_IDX 2
#define mmDCHUBBUB_RET_PATH_DCC_CFG0_1 0x04d1
#define mmDCHUBBUB_RET_PATH_DCC_CFG0_1_BASE_IDX 2
#define mmDCHUBBUB_RET_PATH_DCC_CFG1_0 0x04d2
#define mmDCHUBBUB_RET_PATH_DCC_CFG1_0_BASE_IDX 2
#define mmDCHUBBUB_RET_PATH_DCC_CFG1_1 0x04d3
#define mmDCHUBBUB_RET_PATH_DCC_CFG1_1_BASE_IDX 2
#define mmDCHUBBUB_RET_PATH_DCC_CFG2_0 0x04d4
#define mmDCHUBBUB_RET_PATH_DCC_CFG2_0_BASE_IDX 2
#define mmDCHUBBUB_RET_PATH_DCC_CFG2_1 0x04d5
#define mmDCHUBBUB_RET_PATH_DCC_CFG2_1_BASE_IDX 2
#define mmDCHUBBUB_RET_PATH_DCC_CFG3_0 0x04d6
#define mmDCHUBBUB_RET_PATH_DCC_CFG3_0_BASE_IDX 2
#define mmDCHUBBUB_RET_PATH_DCC_CFG3_1 0x04d7
#define mmDCHUBBUB_RET_PATH_DCC_CFG3_1_BASE_IDX 2
#define mmDCHUBBUB_RET_PATH_DCC_CFG4_0 0x04d8
#define mmDCHUBBUB_RET_PATH_DCC_CFG4_0_BASE_IDX 2
#define mmDCHUBBUB_RET_PATH_DCC_CFG4_1 0x04d9
#define mmDCHUBBUB_RET_PATH_DCC_CFG4_1_BASE_IDX 2
#define mmDCHUBBUB_RET_PATH_DCC_CFG5_0 0x04da
#define mmDCHUBBUB_RET_PATH_DCC_CFG5_0_BASE_IDX 2
#define mmDCHUBBUB_RET_PATH_DCC_CFG5_1 0x04db
#define mmDCHUBBUB_RET_PATH_DCC_CFG5_1_BASE_IDX 2
#define mmDCHUBBUB_RET_PATH_DCC_CFG6_0 0x04dc
#define mmDCHUBBUB_RET_PATH_DCC_CFG6_0_BASE_IDX 2
#define mmDCHUBBUB_RET_PATH_DCC_CFG6_1 0x04dd
#define mmDCHUBBUB_RET_PATH_DCC_CFG6_1_BASE_IDX 2
#define mmDCHUBBUB_RET_PATH_DCC_CFG7_0 0x04de
#define mmDCHUBBUB_RET_PATH_DCC_CFG7_0_BASE_IDX 2
#define mmDCHUBBUB_RET_PATH_DCC_CFG7_1 0x04df
#define mmDCHUBBUB_RET_PATH_DCC_CFG7_1_BASE_IDX 2
#define mmDCHUBBUB_RET_PATH_DCC_CFG8_0 0x04e0
#define mmDCHUBBUB_RET_PATH_DCC_CFG8_0_BASE_IDX 2
#define mmDCHUBBUB_RET_PATH_DCC_CFG8_1 0x04e1
#define mmDCHUBBUB_RET_PATH_DCC_CFG8_1_BASE_IDX 2
#define mmDCHUBBUB_RET_PATH_DCC_CFG9_0 0x04e2
#define mmDCHUBBUB_RET_PATH_DCC_CFG9_0_BASE_IDX 2
#define mmDCHUBBUB_RET_PATH_DCC_CFG9_1 0x04e3
#define mmDCHUBBUB_RET_PATH_DCC_CFG9_1_BASE_IDX 2
#define mmDCHUBBUB_RET_PATH_MEM_PWR_CTRL 0x04ef
#define mmDCHUBBUB_RET_PATH_MEM_PWR_CTRL_BASE_IDX 2
#define mmDCHUBBUB_RET_PATH_MEM_PWR_STATUS 0x04f0
#define mmDCHUBBUB_RET_PATH_MEM_PWR_STATUS_BASE_IDX 2
#define mmDCHUBBUB_CRC_CTRL 0x04f1
#define mmDCHUBBUB_CRC_CTRL_BASE_IDX 2
#define mmDCHUBBUB_CRC0_VAL_R_G 0x04f2
#define mmDCHUBBUB_CRC0_VAL_R_G_BASE_IDX 2
#define mmDCHUBBUB_CRC0_VAL_B_A 0x04f3
#define mmDCHUBBUB_CRC0_VAL_B_A_BASE_IDX 2
#define mmDCHUBBUB_CRC1_VAL_R_G 0x04f4
#define mmDCHUBBUB_CRC1_VAL_R_G_BASE_IDX 2
#define mmDCHUBBUB_CRC1_VAL_B_A 0x04f5
#define mmDCHUBBUB_CRC1_VAL_B_A_BASE_IDX 2
// addressBlock: dce_dc_dchubbub_hubbub_dispdec
// base address: 0x0
#define mmDCHUBBUB_ARB_DF_REQ_OUTSTAND 0x0505
#define mmDCHUBBUB_ARB_DF_REQ_OUTSTAND_BASE_IDX 2
#define mmDCHUBBUB_ARB_SAT_LEVEL 0x0506
#define mmDCHUBBUB_ARB_SAT_LEVEL_BASE_IDX 2
#define mmDCHUBBUB_ARB_QOS_FORCE 0x0507
#define mmDCHUBBUB_ARB_QOS_FORCE_BASE_IDX 2
#define mmDCHUBBUB_ARB_DRAM_STATE_CNTL 0x0508
#define mmDCHUBBUB_ARB_DRAM_STATE_CNTL_BASE_IDX 2
#define mmDCHUBBUB_ARB_DATA_URGENCY_WATERMARK_A 0x0509
#define mmDCHUBBUB_ARB_DATA_URGENCY_WATERMARK_A_BASE_IDX 2
#define mmDCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_A 0x050a
#define mmDCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_A_BASE_IDX 2
#define mmDCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_A 0x050b
#define mmDCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_A_BASE_IDX 2
#define mmDCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_A 0x050c
#define mmDCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_A_BASE_IDX 2
#define mmDCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_A 0x050d
#define mmDCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_A_BASE_IDX 2
#define mmDCHUBBUB_ARB_DATA_URGENCY_WATERMARK_B 0x050e
#define mmDCHUBBUB_ARB_DATA_URGENCY_WATERMARK_B_BASE_IDX 2
#define mmDCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_B 0x050f
#define mmDCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_B_BASE_IDX 2
#define mmDCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_B 0x0510
#define mmDCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_B_BASE_IDX 2
#define mmDCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_B 0x0511
#define mmDCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_B_BASE_IDX 2
#define mmDCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_B 0x0512
#define mmDCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_B_BASE_IDX 2
#define mmDCHUBBUB_ARB_DATA_URGENCY_WATERMARK_C 0x0513
#define mmDCHUBBUB_ARB_DATA_URGENCY_WATERMARK_C_BASE_IDX 2
#define mmDCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_C 0x0514
#define mmDCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_C_BASE_IDX 2
#define mmDCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_C 0x0515
#define mmDCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_C_BASE_IDX 2
#define mmDCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_C 0x0516
#define mmDCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_C_BASE_IDX 2
#define mmDCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_C 0x0517
#define mmDCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_C_BASE_IDX 2
#define mmDCHUBBUB_ARB_DATA_URGENCY_WATERMARK_D 0x0518
#define mmDCHUBBUB_ARB_DATA_URGENCY_WATERMARK_D_BASE_IDX 2
#define mmDCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_D 0x0519
#define mmDCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_D_BASE_IDX 2
#define mmDCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_D 0x051a
#define mmDCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_D_BASE_IDX 2
#define mmDCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_D 0x051b
#define mmDCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_D_BASE_IDX 2
#define mmDCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_D 0x051c
#define mmDCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_D_BASE_IDX 2
#define mmDCHUBBUB_ARB_WATERMARK_CHANGE_CNTL 0x051d
#define mmDCHUBBUB_ARB_WATERMARK_CHANGE_CNTL_BASE_IDX 2
#define mmDCHUBBUB_ARB_TIMEOUT_ENABLE 0x051e
#define mmDCHUBBUB_ARB_TIMEOUT_ENABLE_BASE_IDX 2
#define mmDCHUBBUB_GLOBAL_TIMER_CNTL 0x051f
#define mmDCHUBBUB_GLOBAL_TIMER_CNTL_BASE_IDX 2
#define mmSURFACE_CHECK0_ADDRESS_LSB 0x0520
#define mmSURFACE_CHECK0_ADDRESS_LSB_BASE_IDX 2
#define mmSURFACE_CHECK0_ADDRESS_MSB 0x0521
#define mmSURFACE_CHECK0_ADDRESS_MSB_BASE_IDX 2
#define mmSURFACE_CHECK1_ADDRESS_LSB 0x0522
#define mmSURFACE_CHECK1_ADDRESS_LSB_BASE_IDX 2
#define mmSURFACE_CHECK1_ADDRESS_MSB 0x0523
#define mmSURFACE_CHECK1_ADDRESS_MSB_BASE_IDX 2
#define mmSURFACE_CHECK2_ADDRESS_LSB 0x0524
#define mmSURFACE_CHECK2_ADDRESS_LSB_BASE_IDX 2
#define mmSURFACE_CHECK2_ADDRESS_MSB 0x0525
#define mmSURFACE_CHECK2_ADDRESS_MSB_BASE_IDX 2
#define mmSURFACE_CHECK3_ADDRESS_LSB 0x0526
#define mmSURFACE_CHECK3_ADDRESS_LSB_BASE_IDX 2
#define mmSURFACE_CHECK3_ADDRESS_MSB 0x0527
#define mmSURFACE_CHECK3_ADDRESS_MSB_BASE_IDX 2
#define mmVTG0_CONTROL 0x0528
#define mmVTG0_CONTROL_BASE_IDX 2
#define mmVTG1_CONTROL 0x0529
#define mmVTG1_CONTROL_BASE_IDX 2
#define mmVTG2_CONTROL 0x052a
#define mmVTG2_CONTROL_BASE_IDX 2
#define mmVTG3_CONTROL 0x052b
#define mmVTG3_CONTROL_BASE_IDX 2
#define mmVTG4_CONTROL 0x052c
#define mmVTG4_CONTROL_BASE_IDX 2
#define mmDCHUBBUB_SOFT_RESET 0x052e
#define mmDCHUBBUB_SOFT_RESET_BASE_IDX 2
#define mmDCHUBBUB_CLOCK_CNTL 0x052f
#define mmDCHUBBUB_CLOCK_CNTL_BASE_IDX 2
#define mmDCFCLK_CNTL 0x0530
#define mmDCFCLK_CNTL_BASE_IDX 2
#define mmDCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL 0x0531
#define mmDCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL_BASE_IDX 2
#define mmDCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL2 0x0532
#define mmDCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL2_BASE_IDX 2
#define mmDCHUBBUB_VLINE_SNAPSHOT 0x0533
#define mmDCHUBBUB_VLINE_SNAPSHOT_BASE_IDX 2
#define mmDCHUBBUB_CTRL_STATUS 0x0534
#define mmDCHUBBUB_CTRL_STATUS_BASE_IDX 2
#define mmDCHUBBUB_TIMEOUT_DETECTION_CTRL1 0x053a
#define mmDCHUBBUB_TIMEOUT_DETECTION_CTRL1_BASE_IDX 2
#define mmDCHUBBUB_TIMEOUT_DETECTION_CTRL2 0x053b
#define mmDCHUBBUB_TIMEOUT_DETECTION_CTRL2_BASE_IDX 2
#define mmDCHUBBUB_TIMEOUT_INTERRUPT_STATUS 0x053c
#define mmDCHUBBUB_TIMEOUT_INTERRUPT_STATUS_BASE_IDX 2
#define mmDCHUBBUB_TEST_DEBUG_INDEX 0x053d
#define mmDCHUBBUB_TEST_DEBUG_INDEX_BASE_IDX 2
#define mmDCHUBBUB_TEST_DEBUG_DATA 0x053e
#define mmDCHUBBUB_TEST_DEBUG_DATA_BASE_IDX 2
#define mmDCHUBBUB_ARB_FRAC_URG_BW_NOM_A 0x053f
#define mmDCHUBBUB_ARB_FRAC_URG_BW_NOM_A_BASE_IDX 2
#define mmDCHUBBUB_ARB_FRAC_URG_BW_FLIP_A 0x0540
#define mmDCHUBBUB_ARB_FRAC_URG_BW_FLIP_A_BASE_IDX 2
#define mmDCHUBBUB_ARB_FRAC_URG_BW_NOM_B 0x0541
#define mmDCHUBBUB_ARB_FRAC_URG_BW_NOM_B_BASE_IDX 2
#define mmDCHUBBUB_ARB_FRAC_URG_BW_FLIP_B 0x0542
#define mmDCHUBBUB_ARB_FRAC_URG_BW_FLIP_B_BASE_IDX 2
#define mmDCHUBBUB_ARB_FRAC_URG_BW_NOM_C 0x0543
#define mmDCHUBBUB_ARB_FRAC_URG_BW_NOM_C_BASE_IDX 2
#define mmDCHUBBUB_ARB_FRAC_URG_BW_FLIP_C 0x0544
#define mmDCHUBBUB_ARB_FRAC_URG_BW_FLIP_C_BASE_IDX 2
#define mmDCHUBBUB_ARB_FRAC_URG_BW_NOM_D 0x0545
#define mmDCHUBBUB_ARB_FRAC_URG_BW_NOM_D_BASE_IDX 2
#define mmDCHUBBUB_ARB_FRAC_URG_BW_FLIP_D 0x0546
#define mmDCHUBBUB_ARB_FRAC_URG_BW_FLIP_D_BASE_IDX 2
#define mmFMON_CTRL 0x0548
#define mmFMON_CTRL_BASE_IDX 2
#define mmFMON_CTRL_1 0x0548
#define mmFMON_CTRL_1_BASE_IDX 2
// addressBlock: dce_dc_dchubbub_dchubbub_dcperfmon_dc_perfmon_dispdec
// base address: 0x1534
#define mmDC_PERFMON5_PERFCOUNTER_CNTL 0x054d
#define mmDC_PERFMON5_PERFCOUNTER_CNTL_BASE_IDX 2
#define mmDC_PERFMON5_PERFCOUNTER_CNTL2 0x054e
#define mmDC_PERFMON5_PERFCOUNTER_CNTL2_BASE_IDX 2
#define mmDC_PERFMON5_PERFCOUNTER_STATE 0x054f
#define mmDC_PERFMON5_PERFCOUNTER_STATE_BASE_IDX 2
#define mmDC_PERFMON5_PERFMON_CNTL 0x0550
#define mmDC_PERFMON5_PERFMON_CNTL_BASE_IDX 2
#define mmDC_PERFMON5_PERFMON_CNTL2 0x0551
#define mmDC_PERFMON5_PERFMON_CNTL2_BASE_IDX 2
#define mmDC_PERFMON5_PERFMON_CVALUE_INT_MISC 0x0552
#define mmDC_PERFMON5_PERFMON_CVALUE_INT_MISC_BASE_IDX 2
#define mmDC_PERFMON5_PERFMON_CVALUE_LOW 0x0553
#define mmDC_PERFMON5_PERFMON_CVALUE_LOW_BASE_IDX 2
#define mmDC_PERFMON5_PERFMON_HI 0x0554
#define mmDC_PERFMON5_PERFMON_HI_BASE_IDX 2
#define mmDC_PERFMON5_PERFMON_LOW 0x0555
#define mmDC_PERFMON5_PERFMON_LOW_BASE_IDX 2
// addressBlock: dce_dc_dchubbub_hubbub_vmrq_if_dispdec
// base address: 0x0
#define mmDCN_VM_CONTEXT0_CNTL 0x0559
#define mmDCN_VM_CONTEXT0_CNTL_BASE_IDX 2
#define mmDCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32 0x055a
#define mmDCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 2
#define mmDCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32 0x055b
#define mmDCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 2
#define mmDCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32 0x055c
#define mmDCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 2
#define mmDCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32 0x055d
#define mmDCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 2
#define mmDCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32 0x055e
#define mmDCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 2
#define mmDCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32 0x055f
#define mmDCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 2
#define mmDCN_VM_CONTEXT1_CNTL 0x0560
#define mmDCN_VM_CONTEXT1_CNTL_BASE_IDX 2
#define mmDCN_VM_CONTEXT1_PAGE_TABLE_BASE_ADDR_HI32 0x0561
#define mmDCN_VM_CONTEXT1_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 2
#define mmDCN_VM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32 0x0562
#define mmDCN_VM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 2
#define mmDCN_VM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32 0x0563
#define mmDCN_VM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 2
#define mmDCN_VM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32 0x0564
#define mmDCN_VM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 2
#define mmDCN_VM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32 0x0565
#define mmDCN_VM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 2
#define mmDCN_VM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32 0x0566
#define mmDCN_VM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 2
#define mmDCN_VM_CONTEXT2_CNTL 0x0567
#define mmDCN_VM_CONTEXT2_CNTL_BASE_IDX 2
#define mmDCN_VM_CONTEXT2_PAGE_TABLE_BASE_ADDR_HI32 0x0568
#define mmDCN_VM_CONTEXT2_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 2
#define mmDCN_VM_CONTEXT2_PAGE_TABLE_BASE_ADDR_LO32 0x0569
#define mmDCN_VM_CONTEXT2_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 2
#define mmDCN_VM_CONTEXT2_PAGE_TABLE_START_ADDR_HI32 0x056a
#define mmDCN_VM_CONTEXT2_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 2
#define mmDCN_VM_CONTEXT2_PAGE_TABLE_START_ADDR_LO32 0x056b
#define mmDCN_VM_CONTEXT2_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 2
#define mmDCN_VM_CONTEXT2_PAGE_TABLE_END_ADDR_HI32 0x056c
#define mmDCN_VM_CONTEXT2_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 2
#define mmDCN_VM_CONTEXT2_PAGE_TABLE_END_ADDR_LO32 0x056d
#define mmDCN_VM_CONTEXT2_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 2
#define mmDCN_VM_CONTEXT3_CNTL 0x056e
#define mmDCN_VM_CONTEXT3_CNTL_BASE_IDX 2
#define mmDCN_VM_CONTEXT3_PAGE_TABLE_BASE_ADDR_HI32 0x056f
#define mmDCN_VM_CONTEXT3_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 2
#define mmDCN_VM_CONTEXT3_PAGE_TABLE_BASE_ADDR_LO32 0x0570
#define mmDCN_VM_CONTEXT3_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 2
#define mmDCN_VM_CONTEXT3_PAGE_TABLE_START_ADDR_HI32 0x0571
#define mmDCN_VM_CONTEXT3_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 2
#define mmDCN_VM_CONTEXT3_PAGE_TABLE_START_ADDR_LO32 0x0572
#define mmDCN_VM_CONTEXT3_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 2
#define mmDCN_VM_CONTEXT3_PAGE_TABLE_END_ADDR_HI32 0x0573
#define mmDCN_VM_CONTEXT3_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 2
#define mmDCN_VM_CONTEXT3_PAGE_TABLE_END_ADDR_LO32 0x0574
#define mmDCN_VM_CONTEXT3_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 2
#define mmDCN_VM_CONTEXT4_CNTL 0x0575
#define mmDCN_VM_CONTEXT4_CNTL_BASE_IDX 2
#define mmDCN_VM_CONTEXT4_PAGE_TABLE_BASE_ADDR_HI32 0x0576
#define mmDCN_VM_CONTEXT4_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 2
#define mmDCN_VM_CONTEXT4_PAGE_TABLE_BASE_ADDR_LO32 0x0577
#define mmDCN_VM_CONTEXT4_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 2
#define mmDCN_VM_CONTEXT4_PAGE_TABLE_START_ADDR_HI32 0x0578
#define mmDCN_VM_CONTEXT4_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 2
#define mmDCN_VM_CONTEXT4_PAGE_TABLE_START_ADDR_LO32 0x0579
#define mmDCN_VM_CONTEXT4_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 2
#define mmDCN_VM_CONTEXT4_PAGE_TABLE_END_ADDR_HI32 0x057a
#define mmDCN_VM_CONTEXT4_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 2
#define mmDCN_VM_CONTEXT4_PAGE_TABLE_END_ADDR_LO32 0x057b
#define mmDCN_VM_CONTEXT4_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 2
#define mmDCN_VM_CONTEXT5_CNTL 0x057c
#define mmDCN_VM_CONTEXT5_CNTL_BASE_IDX 2
#define mmDCN_VM_CONTEXT5_PAGE_TABLE_BASE_ADDR_HI32 0x057d
#define mmDCN_VM_CONTEXT5_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 2
#define mmDCN_VM_CONTEXT5_PAGE_TABLE_BASE_ADDR_LO32 0x057e
#define mmDCN_VM_CONTEXT5_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 2
#define mmDCN_VM_CONTEXT5_PAGE_TABLE_START_ADDR_HI32 0x057f
#define mmDCN_VM_CONTEXT5_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 2
#define mmDCN_VM_CONTEXT5_PAGE_TABLE_START_ADDR_LO32 0x0580
#define mmDCN_VM_CONTEXT5_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 2
#define mmDCN_VM_CONTEXT5_PAGE_TABLE_END_ADDR_HI32 0x0581
#define mmDCN_VM_CONTEXT5_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 2
#define mmDCN_VM_CONTEXT5_PAGE_TABLE_END_ADDR_LO32 0x0582
#define mmDCN_VM_CONTEXT5_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 2
#define mmDCN_VM_CONTEXT6_CNTL 0x0583
#define mmDCN_VM_CONTEXT6_CNTL_BASE_IDX 2
#define mmDCN_VM_CONTEXT6_PAGE_TABLE_BASE_ADDR_HI32 0x0584
#define mmDCN_VM_CONTEXT6_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 2
#define mmDCN_VM_CONTEXT6_PAGE_TABLE_BASE_ADDR_LO32 0x0585
#define mmDCN_VM_CONTEXT6_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 2
#define mmDCN_VM_CONTEXT6_PAGE_TABLE_START_ADDR_HI32 0x0586
#define mmDCN_VM_CONTEXT6_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 2
#define mmDCN_VM_CONTEXT6_PAGE_TABLE_START_ADDR_LO32 0x0587
#define mmDCN_VM_CONTEXT6_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 2
#define mmDCN_VM_CONTEXT6_PAGE_TABLE_END_ADDR_HI32 0x0588
#define mmDCN_VM_CONTEXT6_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 2
#define mmDCN_VM_CONTEXT6_PAGE_TABLE_END_ADDR_LO32 0x0589
#define mmDCN_VM_CONTEXT6_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 2
#define mmDCN_VM_CONTEXT7_CNTL 0x058a
#define mmDCN_VM_CONTEXT7_CNTL_BASE_IDX 2
#define mmDCN_VM_CONTEXT7_PAGE_TABLE_BASE_ADDR_HI32 0x058b
#define mmDCN_VM_CONTEXT7_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 2
#define mmDCN_VM_CONTEXT7_PAGE_TABLE_BASE_ADDR_LO32 0x058c
#define mmDCN_VM_CONTEXT7_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 2
#define mmDCN_VM_CONTEXT7_PAGE_TABLE_START_ADDR_HI32 0x058d
#define mmDCN_VM_CONTEXT7_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 2
#define mmDCN_VM_CONTEXT7_PAGE_TABLE_START_ADDR_LO32 0x058e
#define mmDCN_VM_CONTEXT7_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 2
#define mmDCN_VM_CONTEXT7_PAGE_TABLE_END_ADDR_HI32 0x058f
#define mmDCN_VM_CONTEXT7_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 2
#define mmDCN_VM_CONTEXT7_PAGE_TABLE_END_ADDR_LO32 0x0590
#define mmDCN_VM_CONTEXT7_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 2
#define mmDCN_VM_CONTEXT8_CNTL 0x0591
#define mmDCN_VM_CONTEXT8_CNTL_BASE_IDX 2
#define mmDCN_VM_CONTEXT8_PAGE_TABLE_BASE_ADDR_HI32 0x0592
#define mmDCN_VM_CONTEXT8_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 2
#define mmDCN_VM_CONTEXT8_PAGE_TABLE_BASE_ADDR_LO32 0x0593
#define mmDCN_VM_CONTEXT8_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 2
#define mmDCN_VM_CONTEXT8_PAGE_TABLE_START_ADDR_HI32 0x0594
#define mmDCN_VM_CONTEXT8_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 2
#define mmDCN_VM_CONTEXT8_PAGE_TABLE_START_ADDR_LO32 0x0595
#define mmDCN_VM_CONTEXT8_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 2
#define mmDCN_VM_CONTEXT8_PAGE_TABLE_END_ADDR_HI32 0x0596
#define mmDCN_VM_CONTEXT8_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 2
#define mmDCN_VM_CONTEXT8_PAGE_TABLE_END_ADDR_LO32 0x0597
#define mmDCN_VM_CONTEXT8_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 2
#define mmDCN_VM_CONTEXT9_CNTL 0x0598
#define mmDCN_VM_CONTEXT9_CNTL_BASE_IDX 2
#define mmDCN_VM_CONTEXT9_PAGE_TABLE_BASE_ADDR_HI32 0x0599
#define mmDCN_VM_CONTEXT9_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 2
#define mmDCN_VM_CONTEXT9_PAGE_TABLE_BASE_ADDR_LO32 0x059a
#define mmDCN_VM_CONTEXT9_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 2
#define mmDCN_VM_CONTEXT9_PAGE_TABLE_START_ADDR_HI32 0x059b
#define mmDCN_VM_CONTEXT9_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 2
#define mmDCN_VM_CONTEXT9_PAGE_TABLE_START_ADDR_LO32 0x059c
#define mmDCN_VM_CONTEXT9_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 2
#define mmDCN_VM_CONTEXT9_PAGE_TABLE_END_ADDR_HI32 0x059d
#define mmDCN_VM_CONTEXT9_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 2
#define mmDCN_VM_CONTEXT9_PAGE_TABLE_END_ADDR_LO32 0x059e
#define mmDCN_VM_CONTEXT9_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 2
#define mmDCN_VM_CONTEXT10_CNTL 0x059f
#define mmDCN_VM_CONTEXT10_CNTL_BASE_IDX 2
#define mmDCN_VM_CONTEXT10_PAGE_TABLE_BASE_ADDR_HI32 0x05a0
#define mmDCN_VM_CONTEXT10_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 2
#define mmDCN_VM_CONTEXT10_PAGE_TABLE_BASE_ADDR_LO32 0x05a1
#define mmDCN_VM_CONTEXT10_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 2
#define mmDCN_VM_CONTEXT10_PAGE_TABLE_START_ADDR_HI32 0x05a2
#define mmDCN_VM_CONTEXT10_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 2
#define mmDCN_VM_CONTEXT10_PAGE_TABLE_START_ADDR_LO32 0x05a3
#define mmDCN_VM_CONTEXT10_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 2
#define mmDCN_VM_CONTEXT10_PAGE_TABLE_END_ADDR_HI32 0x05a4
#define mmDCN_VM_CONTEXT10_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 2
#define mmDCN_VM_CONTEXT10_PAGE_TABLE_END_ADDR_LO32 0x05a5
#define mmDCN_VM_CONTEXT10_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 2
#define mmDCN_VM_CONTEXT11_CNTL 0x05a6
#define mmDCN_VM_CONTEXT11_CNTL_BASE_IDX 2
#define mmDCN_VM_CONTEXT11_PAGE_TABLE_BASE_ADDR_HI32 0x05a7
#define mmDCN_VM_CONTEXT11_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 2
#define mmDCN_VM_CONTEXT11_PAGE_TABLE_BASE_ADDR_LO32 0x05a8
#define mmDCN_VM_CONTEXT11_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 2
#define mmDCN_VM_CONTEXT11_PAGE_TABLE_START_ADDR_HI32 0x05a9
#define mmDCN_VM_CONTEXT11_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 2
#define mmDCN_VM_CONTEXT11_PAGE_TABLE_START_ADDR_LO32 0x05aa
#define mmDCN_VM_CONTEXT11_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 2
#define mmDCN_VM_CONTEXT11_PAGE_TABLE_END_ADDR_HI32 0x05ab
#define mmDCN_VM_CONTEXT11_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 2
#define mmDCN_VM_CONTEXT11_PAGE_TABLE_END_ADDR_LO32 0x05ac
#define mmDCN_VM_CONTEXT11_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 2
#define mmDCN_VM_CONTEXT12_CNTL 0x05ad
#define mmDCN_VM_CONTEXT12_CNTL_BASE_IDX 2
#define mmDCN_VM_CONTEXT12_PAGE_TABLE_BASE_ADDR_HI32 0x05ae
#define mmDCN_VM_CONTEXT12_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 2
#define mmDCN_VM_CONTEXT12_PAGE_TABLE_BASE_ADDR_LO32 0x05af
#define mmDCN_VM_CONTEXT12_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 2
#define mmDCN_VM_CONTEXT12_PAGE_TABLE_START_ADDR_HI32 0x05b0
#define mmDCN_VM_CONTEXT12_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 2
#define mmDCN_VM_CONTEXT12_PAGE_TABLE_START_ADDR_LO32 0x05b1
#define mmDCN_VM_CONTEXT12_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 2
#define mmDCN_VM_CONTEXT12_PAGE_TABLE_END_ADDR_HI32 0x05b2
#define mmDCN_VM_CONTEXT12_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 2
#define mmDCN_VM_CONTEXT12_PAGE_TABLE_END_ADDR_LO32 0x05b3
#define mmDCN_VM_CONTEXT12_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 2
#define mmDCN_VM_CONTEXT13_CNTL 0x05b4
#define mmDCN_VM_CONTEXT13_CNTL_BASE_IDX 2
#define mmDCN_VM_CONTEXT13_PAGE_TABLE_BASE_ADDR_HI32 0x05b5
#define mmDCN_VM_CONTEXT13_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 2
#define mmDCN_VM_CONTEXT13_PAGE_TABLE_BASE_ADDR_LO32 0x05b6
#define mmDCN_VM_CONTEXT13_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 2
#define mmDCN_VM_CONTEXT13_PAGE_TABLE_START_ADDR_HI32 0x05b7
#define mmDCN_VM_CONTEXT13_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 2
#define mmDCN_VM_CONTEXT13_PAGE_TABLE_START_ADDR_LO32 0x05b8
#define mmDCN_VM_CONTEXT13_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 2
#define mmDCN_VM_CONTEXT13_PAGE_TABLE_END_ADDR_HI32 0x05b9
#define mmDCN_VM_CONTEXT13_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 2
#define mmDCN_VM_CONTEXT13_PAGE_TABLE_END_ADDR_LO32 0x05ba
#define mmDCN_VM_CONTEXT13_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 2
#define mmDCN_VM_CONTEXT14_CNTL 0x05bb
#define mmDCN_VM_CONTEXT14_CNTL_BASE_IDX 2
#define mmDCN_VM_CONTEXT14_PAGE_TABLE_BASE_ADDR_HI32 0x05bc
#define mmDCN_VM_CONTEXT14_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 2
#define mmDCN_VM_CONTEXT14_PAGE_TABLE_BASE_ADDR_LO32 0x05bd
#define mmDCN_VM_CONTEXT14_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 2
#define mmDCN_VM_CONTEXT14_PAGE_TABLE_START_ADDR_HI32 0x05be
#define mmDCN_VM_CONTEXT14_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 2
#define mmDCN_VM_CONTEXT14_PAGE_TABLE_START_ADDR_LO32 0x05bf
#define mmDCN_VM_CONTEXT14_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 2
#define mmDCN_VM_CONTEXT14_PAGE_TABLE_END_ADDR_HI32 0x05c0
#define mmDCN_VM_CONTEXT14_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 2
#define mmDCN_VM_CONTEXT14_PAGE_TABLE_END_ADDR_LO32 0x05c1
#define mmDCN_VM_CONTEXT14_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 2
#define mmDCN_VM_CONTEXT15_CNTL 0x05c2
#define mmDCN_VM_CONTEXT15_CNTL_BASE_IDX 2
#define mmDCN_VM_CONTEXT15_PAGE_TABLE_BASE_ADDR_HI32 0x05c3
#define mmDCN_VM_CONTEXT15_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 2
#define mmDCN_VM_CONTEXT15_PAGE_TABLE_BASE_ADDR_LO32 0x05c4
#define mmDCN_VM_CONTEXT15_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 2
#define mmDCN_VM_CONTEXT15_PAGE_TABLE_START_ADDR_HI32 0x05c5
#define mmDCN_VM_CONTEXT15_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 2
#define mmDCN_VM_CONTEXT15_PAGE_TABLE_START_ADDR_LO32 0x05c6
#define mmDCN_VM_CONTEXT15_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 2
#define mmDCN_VM_CONTEXT15_PAGE_TABLE_END_ADDR_HI32 0x05c7
#define mmDCN_VM_CONTEXT15_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 2
#define mmDCN_VM_CONTEXT15_PAGE_TABLE_END_ADDR_LO32 0x05c8
#define mmDCN_VM_CONTEXT15_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 2
#define mmDCN_VM_DEFAULT_ADDR_MSB 0x05c9
#define mmDCN_VM_DEFAULT_ADDR_MSB_BASE_IDX 2
#define mmDCN_VM_DEFAULT_ADDR_LSB 0x05ca
#define mmDCN_VM_DEFAULT_ADDR_LSB_BASE_IDX 2
#define mmDCN_VM_FAULT_CNTL 0x05cb
#define mmDCN_VM_FAULT_CNTL_BASE_IDX 2
#define mmDCN_VM_FAULT_STATUS 0x05cc
#define mmDCN_VM_FAULT_STATUS_BASE_IDX 2
#define mmDCN_VM_FAULT_ADDR_MSB 0x05cd
#define mmDCN_VM_FAULT_ADDR_MSB_BASE_IDX 2
#define mmDCN_VM_FAULT_ADDR_LSB 0x05ce
#define mmDCN_VM_FAULT_ADDR_LSB_BASE_IDX 2
// addressBlock: dce_dc_dcbubp0_dispdec_hubp_dispdec
// base address: 0x0
#define mmHUBP0_DCSURF_SURFACE_CONFIG 0x05e5
#define mmHUBP0_DCSURF_SURFACE_CONFIG_BASE_IDX 2
#define mmHUBP0_DCSURF_ADDR_CONFIG 0x05e6
#define mmHUBP0_DCSURF_ADDR_CONFIG_BASE_IDX 2
#define mmHUBP0_DCSURF_TILING_CONFIG 0x05e7
#define mmHUBP0_DCSURF_TILING_CONFIG_BASE_IDX 2
#define mmHUBP0_DCSURF_PRI_VIEWPORT_START 0x05e9
#define mmHUBP0_DCSURF_PRI_VIEWPORT_START_BASE_IDX 2
#define mmHUBP0_DCSURF_PRI_VIEWPORT_DIMENSION 0x05ea
#define mmHUBP0_DCSURF_PRI_VIEWPORT_DIMENSION_BASE_IDX 2
#define mmHUBP0_DCSURF_PRI_VIEWPORT_START_C 0x05eb
#define mmHUBP0_DCSURF_PRI_VIEWPORT_START_C_BASE_IDX 2
#define mmHUBP0_DCSURF_PRI_VIEWPORT_DIMENSION_C 0x05ec
#define mmHUBP0_DCSURF_PRI_VIEWPORT_DIMENSION_C_BASE_IDX 2
#define mmHUBP0_DCSURF_SEC_VIEWPORT_START 0x05ed
#define mmHUBP0_DCSURF_SEC_VIEWPORT_START_BASE_IDX 2
#define mmHUBP0_DCSURF_SEC_VIEWPORT_DIMENSION 0x05ee
#define mmHUBP0_DCSURF_SEC_VIEWPORT_DIMENSION_BASE_IDX 2
#define mmHUBP0_DCSURF_SEC_VIEWPORT_START_C 0x05ef
#define mmHUBP0_DCSURF_SEC_VIEWPORT_START_C_BASE_IDX 2
#define mmHUBP0_DCSURF_SEC_VIEWPORT_DIMENSION_C 0x05f0
#define mmHUBP0_DCSURF_SEC_VIEWPORT_DIMENSION_C_BASE_IDX 2
#define mmHUBP0_DCHUBP_REQ_SIZE_CONFIG 0x05f1
#define mmHUBP0_DCHUBP_REQ_SIZE_CONFIG_BASE_IDX 2
#define mmHUBP0_DCHUBP_REQ_SIZE_CONFIG_C 0x05f2
#define mmHUBP0_DCHUBP_REQ_SIZE_CONFIG_C_BASE_IDX 2
#define mmHUBP0_DCHUBP_CNTL 0x05f3
#define mmHUBP0_DCHUBP_CNTL_BASE_IDX 2
#define mmHUBP0_HUBP_CLK_CNTL 0x05f4
#define mmHUBP0_HUBP_CLK_CNTL_BASE_IDX 2
#define mmHUBP0_DCHUBP_VMPG_CONFIG 0x05f5
#define mmHUBP0_DCHUBP_VMPG_CONFIG_BASE_IDX 2
#define mmHUBP0_HUBP_MEASURE_WIN_CTRL_DCFCLK 0x05fb
#define mmHUBP0_HUBP_MEASURE_WIN_CTRL_DCFCLK_BASE_IDX 2
#define mmHUBP0_HUBP_MEASURE_WIN_CTRL_DPPCLK 0x05fc
#define mmHUBP0_HUBP_MEASURE_WIN_CTRL_DPPCLK_BASE_IDX 2
#define mmHUBP0_HUBPREQ_DEBUG_DB 0x05f6
#define mmHUBP0_HUBPREQ_DEBUG_DB_BASE_IDX 2
#define mmHUBP0_HUBPREQ_DEBUG 0x05f7
#define mmHUBP0_HUBPREQ_DEBUG_BASE_IDX 2
// addressBlock: dce_dc_dcbubp0_dispdec_hubpreq_dispdec
// base address: 0x0
#define mmHUBPREQ0_DCSURF_SURFACE_PITCH 0x0607
#define mmHUBPREQ0_DCSURF_SURFACE_PITCH_BASE_IDX 2
#define mmHUBPREQ0_DCSURF_SURFACE_PITCH_C 0x0608
#define mmHUBPREQ0_DCSURF_SURFACE_PITCH_C_BASE_IDX 2
#define mmHUBPREQ0_VMID_SETTINGS_0 0x0609
#define mmHUBPREQ0_VMID_SETTINGS_0_BASE_IDX 2
#define mmHUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS 0x060a
#define mmHUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_BASE_IDX 2
#define mmHUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH 0x060b
#define mmHUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_BASE_IDX 2
#define mmHUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_C 0x060c
#define mmHUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_C_BASE_IDX 2
#define mmHUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C 0x060d
#define mmHUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C_BASE_IDX 2
#define mmHUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS 0x060e
#define mmHUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_BASE_IDX 2
#define mmHUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH 0x060f
#define mmHUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_BASE_IDX 2
#define mmHUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_C 0x0610
#define mmHUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_C_BASE_IDX 2
#define mmHUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C 0x0611
#define mmHUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C_BASE_IDX 2
#define mmHUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS 0x0612
#define mmHUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_BASE_IDX 2
#define mmHUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH 0x0613
#define mmHUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_BASE_IDX 2
#define mmHUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C 0x0614
#define mmHUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C_BASE_IDX 2
#define mmHUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C 0x0615
#define mmHUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C_BASE_IDX 2
#define mmHUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS 0x0616
#define mmHUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS_BASE_IDX 2
#define mmHUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH 0x0617
#define mmHUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_BASE_IDX 2
#define mmHUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C 0x0618
#define mmHUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C_BASE_IDX 2
#define mmHUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C 0x0619
#define your_sha256_hash 2
#define mmHUBPREQ0_DCSURF_SURFACE_CONTROL 0x061a
#define mmHUBPREQ0_DCSURF_SURFACE_CONTROL_BASE_IDX 2
#define mmHUBPREQ0_DCSURF_FLIP_CONTROL 0x061b
#define mmHUBPREQ0_DCSURF_FLIP_CONTROL_BASE_IDX 2
#define mmHUBPREQ0_DCSURF_FLIP_CONTROL2 0x061c
#define mmHUBPREQ0_DCSURF_FLIP_CONTROL2_BASE_IDX 2
#define mmHUBPREQ0_DCSURF_SURFACE_FLIP_INTERRUPT 0x0620
#define mmHUBPREQ0_DCSURF_SURFACE_FLIP_INTERRUPT_BASE_IDX 2
#define mmHUBPREQ0_DCSURF_SURFACE_INUSE 0x0621
#define mmHUBPREQ0_DCSURF_SURFACE_INUSE_BASE_IDX 2
#define mmHUBPREQ0_DCSURF_SURFACE_INUSE_HIGH 0x0622
#define mmHUBPREQ0_DCSURF_SURFACE_INUSE_HIGH_BASE_IDX 2
#define mmHUBPREQ0_DCSURF_SURFACE_INUSE_C 0x0623
#define mmHUBPREQ0_DCSURF_SURFACE_INUSE_C_BASE_IDX 2
#define mmHUBPREQ0_DCSURF_SURFACE_INUSE_HIGH_C 0x0624
#define mmHUBPREQ0_DCSURF_SURFACE_INUSE_HIGH_C_BASE_IDX 2
#define mmHUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE 0x0625
#define mmHUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_BASE_IDX 2
#define mmHUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_HIGH 0x0626
#define mmHUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_BASE_IDX 2
#define mmHUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_C 0x0627
#define mmHUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_C_BASE_IDX 2
#define mmHUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C 0x0628
#define mmHUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C_BASE_IDX 2
#define mmHUBPREQ0_DCN_EXPANSION_MODE 0x0629
#define mmHUBPREQ0_DCN_EXPANSION_MODE_BASE_IDX 2
#define mmHUBPREQ0_DCN_TTU_QOS_WM 0x062a
#define mmHUBPREQ0_DCN_TTU_QOS_WM_BASE_IDX 2
#define mmHUBPREQ0_DCN_GLOBAL_TTU_CNTL 0x062b
#define mmHUBPREQ0_DCN_GLOBAL_TTU_CNTL_BASE_IDX 2
#define mmHUBPREQ0_DCN_SURF0_TTU_CNTL0 0x062c
#define mmHUBPREQ0_DCN_SURF0_TTU_CNTL0_BASE_IDX 2
#define mmHUBPREQ0_DCN_SURF0_TTU_CNTL1 0x062d
#define mmHUBPREQ0_DCN_SURF0_TTU_CNTL1_BASE_IDX 2
#define mmHUBPREQ0_DCN_SURF1_TTU_CNTL0 0x062e
#define mmHUBPREQ0_DCN_SURF1_TTU_CNTL0_BASE_IDX 2
#define mmHUBPREQ0_DCN_SURF1_TTU_CNTL1 0x062f
#define mmHUBPREQ0_DCN_SURF1_TTU_CNTL1_BASE_IDX 2
#define mmHUBPREQ0_DCN_CUR0_TTU_CNTL0 0x0630
#define mmHUBPREQ0_DCN_CUR0_TTU_CNTL0_BASE_IDX 2
#define mmHUBPREQ0_DCN_CUR0_TTU_CNTL1 0x0631
#define mmHUBPREQ0_DCN_CUR0_TTU_CNTL1_BASE_IDX 2
#define mmHUBPREQ0_DCN_CUR1_TTU_CNTL0 0x0632
#define mmHUBPREQ0_DCN_CUR1_TTU_CNTL0_BASE_IDX 2
#define mmHUBPREQ0_DCN_CUR1_TTU_CNTL1 0x0633
#define mmHUBPREQ0_DCN_CUR1_TTU_CNTL1_BASE_IDX 2
#define mmHUBPREQ0_DCN_DMDATA_VM_CNTL 0x0634
#define mmHUBPREQ0_DCN_DMDATA_VM_CNTL_BASE_IDX 2
#define mmHUBPREQ0_DCN_VM_SYSTEM_APERTURE_LOW_ADDR 0x0635
#define mmHUBPREQ0_DCN_VM_SYSTEM_APERTURE_LOW_ADDR_BASE_IDX 2
#define mmHUBPREQ0_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR 0x0636
#define mmHUBPREQ0_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR_BASE_IDX 2
#define mmHUBPREQ0_DCN_VM_MX_L1_TLB_CNTL 0x0643
#define mmHUBPREQ0_DCN_VM_MX_L1_TLB_CNTL_BASE_IDX 2
#define mmHUBPREQ0_BLANK_OFFSET_0 0x0644
#define mmHUBPREQ0_BLANK_OFFSET_0_BASE_IDX 2
#define mmHUBPREQ0_BLANK_OFFSET_1 0x0645
#define mmHUBPREQ0_BLANK_OFFSET_1_BASE_IDX 2
#define mmHUBPREQ0_DST_DIMENSIONS 0x0646
#define mmHUBPREQ0_DST_DIMENSIONS_BASE_IDX 2
#define mmHUBPREQ0_DST_AFTER_SCALER 0x0647
#define mmHUBPREQ0_DST_AFTER_SCALER_BASE_IDX 2
#define mmHUBPREQ0_PREFETCH_SETTINGS 0x0648
#define mmHUBPREQ0_PREFETCH_SETTINGS_BASE_IDX 2
#define mmHUBPREQ0_PREFETCH_SETTINGS_C 0x0649
#define mmHUBPREQ0_PREFETCH_SETTINGS_C_BASE_IDX 2
#define mmHUBPREQ0_VBLANK_PARAMETERS_0 0x064a
#define mmHUBPREQ0_VBLANK_PARAMETERS_0_BASE_IDX 2
#define mmHUBPREQ0_VBLANK_PARAMETERS_1 0x064b
#define mmHUBPREQ0_VBLANK_PARAMETERS_1_BASE_IDX 2
#define mmHUBPREQ0_VBLANK_PARAMETERS_2 0x064c
#define mmHUBPREQ0_VBLANK_PARAMETERS_2_BASE_IDX 2
#define mmHUBPREQ0_VBLANK_PARAMETERS_3 0x064d
#define mmHUBPREQ0_VBLANK_PARAMETERS_3_BASE_IDX 2
#define mmHUBPREQ0_VBLANK_PARAMETERS_4 0x064e
#define mmHUBPREQ0_VBLANK_PARAMETERS_4_BASE_IDX 2
#define mmHUBPREQ0_FLIP_PARAMETERS_0 0x064f
#define mmHUBPREQ0_FLIP_PARAMETERS_0_BASE_IDX 2
#define mmHUBPREQ0_FLIP_PARAMETERS_1 0x0650
#define mmHUBPREQ0_FLIP_PARAMETERS_1_BASE_IDX 2
#define mmHUBPREQ0_FLIP_PARAMETERS_2 0x0651
#define mmHUBPREQ0_FLIP_PARAMETERS_2_BASE_IDX 2
#define mmHUBPREQ0_NOM_PARAMETERS_0 0x0652
#define mmHUBPREQ0_NOM_PARAMETERS_0_BASE_IDX 2
#define mmHUBPREQ0_NOM_PARAMETERS_1 0x0653
#define mmHUBPREQ0_NOM_PARAMETERS_1_BASE_IDX 2
#define mmHUBPREQ0_NOM_PARAMETERS_2 0x0654
#define mmHUBPREQ0_NOM_PARAMETERS_2_BASE_IDX 2
#define mmHUBPREQ0_NOM_PARAMETERS_3 0x0655
#define mmHUBPREQ0_NOM_PARAMETERS_3_BASE_IDX 2
#define mmHUBPREQ0_NOM_PARAMETERS_4 0x0656
#define mmHUBPREQ0_NOM_PARAMETERS_4_BASE_IDX 2
#define mmHUBPREQ0_NOM_PARAMETERS_5 0x0657
#define mmHUBPREQ0_NOM_PARAMETERS_5_BASE_IDX 2
#define mmHUBPREQ0_NOM_PARAMETERS_6 0x0658
#define mmHUBPREQ0_NOM_PARAMETERS_6_BASE_IDX 2
#define mmHUBPREQ0_NOM_PARAMETERS_7 0x0659
#define mmHUBPREQ0_NOM_PARAMETERS_7_BASE_IDX 2
#define mmHUBPREQ0_PER_LINE_DELIVERY_PRE 0x065a
#define mmHUBPREQ0_PER_LINE_DELIVERY_PRE_BASE_IDX 2
#define mmHUBPREQ0_PER_LINE_DELIVERY 0x065b
#define mmHUBPREQ0_PER_LINE_DELIVERY_BASE_IDX 2
#define mmHUBPREQ0_CURSOR_SETTINGS 0x065c
#define mmHUBPREQ0_CURSOR_SETTINGS_BASE_IDX 2
#define mmHUBPREQ0_REF_FREQ_TO_PIX_FREQ 0x065d
#define mmHUBPREQ0_REF_FREQ_TO_PIX_FREQ_BASE_IDX 2
#define mmHUBPREQ0_DST_Y_DELTA_DRQ_LIMIT 0x065e
#define mmHUBPREQ0_DST_Y_DELTA_DRQ_LIMIT_BASE_IDX 2
#define mmHUBPREQ0_HUBPREQ_MEM_PWR_CTRL 0x065f
#define mmHUBPREQ0_HUBPREQ_MEM_PWR_CTRL_BASE_IDX 2
#define mmHUBPREQ0_HUBPREQ_MEM_PWR_STATUS 0x0660
#define mmHUBPREQ0_HUBPREQ_MEM_PWR_STATUS_BASE_IDX 2
#define mmHUBPREQ0_VBLANK_PARAMETERS_5 0x0663
#define mmHUBPREQ0_VBLANK_PARAMETERS_5_BASE_IDX 2
#define mmHUBPREQ0_VBLANK_PARAMETERS_6 0x0664
#define mmHUBPREQ0_VBLANK_PARAMETERS_6_BASE_IDX 2
#define mmHUBPREQ0_FLIP_PARAMETERS_3 0x0665
#define mmHUBPREQ0_FLIP_PARAMETERS_3_BASE_IDX 2
#define mmHUBPREQ0_FLIP_PARAMETERS_4 0x0666
#define mmHUBPREQ0_FLIP_PARAMETERS_4_BASE_IDX 2
#define mmHUBPREQ0_FLIP_PARAMETERS_5 0x0667
#define mmHUBPREQ0_FLIP_PARAMETERS_5_BASE_IDX 2
#define mmHUBPREQ0_FLIP_PARAMETERS_6 0x0668
#define mmHUBPREQ0_FLIP_PARAMETERS_6_BASE_IDX 2
// addressBlock: dce_dc_dcbubp0_dispdec_hubpret_dispdec
// base address: 0x0
#define mmHUBPRET0_HUBPRET_CONTROL 0x066c
#define mmHUBPRET0_HUBPRET_CONTROL_BASE_IDX 2
#define mmHUBPRET0_HUBPRET_MEM_PWR_CTRL 0x066d
#define mmHUBPRET0_HUBPRET_MEM_PWR_CTRL_BASE_IDX 2
#define mmHUBPRET0_HUBPRET_MEM_PWR_STATUS 0x066e
#define mmHUBPRET0_HUBPRET_MEM_PWR_STATUS_BASE_IDX 2
#define mmHUBPRET0_HUBPRET_READ_LINE_CTRL0 0x066f
#define mmHUBPRET0_HUBPRET_READ_LINE_CTRL0_BASE_IDX 2
#define mmHUBPRET0_HUBPRET_READ_LINE_CTRL1 0x0670
#define mmHUBPRET0_HUBPRET_READ_LINE_CTRL1_BASE_IDX 2
#define mmHUBPRET0_HUBPRET_READ_LINE0 0x0671
#define mmHUBPRET0_HUBPRET_READ_LINE0_BASE_IDX 2
#define mmHUBPRET0_HUBPRET_READ_LINE1 0x0672
#define mmHUBPRET0_HUBPRET_READ_LINE1_BASE_IDX 2
#define mmHUBPRET0_HUBPRET_INTERRUPT 0x0673
#define mmHUBPRET0_HUBPRET_INTERRUPT_BASE_IDX 2
#define mmHUBPRET0_HUBPRET_READ_LINE_VALUE 0x0674
#define mmHUBPRET0_HUBPRET_READ_LINE_VALUE_BASE_IDX 2
#define mmHUBPRET0_HUBPRET_READ_LINE_STATUS 0x0675
#define mmHUBPRET0_HUBPRET_READ_LINE_STATUS_BASE_IDX 2
// addressBlock: dce_dc_dcbubp0_dispdec_cursor0_dispdec
// base address: 0x0
#define mmCURSOR0_0_CURSOR_CONTROL 0x0678
#define mmCURSOR0_0_CURSOR_CONTROL_BASE_IDX 2
#define mmCURSOR0_0_CURSOR_SURFACE_ADDRESS 0x0679
#define mmCURSOR0_0_CURSOR_SURFACE_ADDRESS_BASE_IDX 2
#define mmCURSOR0_0_CURSOR_SURFACE_ADDRESS_HIGH 0x067a
#define mmCURSOR0_0_CURSOR_SURFACE_ADDRESS_HIGH_BASE_IDX 2
#define mmCURSOR0_0_CURSOR_SIZE 0x067b
#define mmCURSOR0_0_CURSOR_SIZE_BASE_IDX 2
#define mmCURSOR0_0_CURSOR_POSITION 0x067c
#define mmCURSOR0_0_CURSOR_POSITION_BASE_IDX 2
#define mmCURSOR0_0_CURSOR_HOT_SPOT 0x067d
#define mmCURSOR0_0_CURSOR_HOT_SPOT_BASE_IDX 2
#define mmCURSOR0_0_CURSOR_STEREO_CONTROL 0x067e
#define mmCURSOR0_0_CURSOR_STEREO_CONTROL_BASE_IDX 2
#define mmCURSOR0_0_CURSOR_DST_OFFSET 0x067f
#define mmCURSOR0_0_CURSOR_DST_OFFSET_BASE_IDX 2
#define mmCURSOR0_0_CURSOR_MEM_PWR_CTRL 0x0680
#define mmCURSOR0_0_CURSOR_MEM_PWR_CTRL_BASE_IDX 2
#define mmCURSOR0_0_CURSOR_MEM_PWR_STATUS 0x0681
#define mmCURSOR0_0_CURSOR_MEM_PWR_STATUS_BASE_IDX 2
#define mmCURSOR0_0_DMDATA_ADDRESS_HIGH 0x0682
#define mmCURSOR0_0_DMDATA_ADDRESS_HIGH_BASE_IDX 2
#define mmCURSOR0_0_DMDATA_ADDRESS_LOW 0x0683
#define mmCURSOR0_0_DMDATA_ADDRESS_LOW_BASE_IDX 2
#define mmCURSOR0_0_DMDATA_CNTL 0x0684
#define mmCURSOR0_0_DMDATA_CNTL_BASE_IDX 2
#define mmCURSOR0_0_DMDATA_QOS_CNTL 0x0685
#define mmCURSOR0_0_DMDATA_QOS_CNTL_BASE_IDX 2
#define mmCURSOR0_0_DMDATA_STATUS 0x0686
#define mmCURSOR0_0_DMDATA_STATUS_BASE_IDX 2
#define mmCURSOR0_0_DMDATA_SW_CNTL 0x0687
#define mmCURSOR0_0_DMDATA_SW_CNTL_BASE_IDX 2
#define mmCURSOR0_0_DMDATA_SW_DATA 0x0688
#define mmCURSOR0_0_DMDATA_SW_DATA_BASE_IDX 2
// addressBlock: dce_dc_dcbubp0_dispdec_hubp_dcperfmon_dc_perfmon_dispdec
// base address: 0x1a74
#define mmDC_PERFMON6_PERFCOUNTER_CNTL 0x069d
#define mmDC_PERFMON6_PERFCOUNTER_CNTL_BASE_IDX 2
#define mmDC_PERFMON6_PERFCOUNTER_CNTL2 0x069e
#define mmDC_PERFMON6_PERFCOUNTER_CNTL2_BASE_IDX 2
#define mmDC_PERFMON6_PERFCOUNTER_STATE 0x069f
#define mmDC_PERFMON6_PERFCOUNTER_STATE_BASE_IDX 2
#define mmDC_PERFMON6_PERFMON_CNTL 0x06a0
#define mmDC_PERFMON6_PERFMON_CNTL_BASE_IDX 2
#define mmDC_PERFMON6_PERFMON_CNTL2 0x06a1
#define mmDC_PERFMON6_PERFMON_CNTL2_BASE_IDX 2
#define mmDC_PERFMON6_PERFMON_CVALUE_INT_MISC 0x06a2
#define mmDC_PERFMON6_PERFMON_CVALUE_INT_MISC_BASE_IDX 2
#define mmDC_PERFMON6_PERFMON_CVALUE_LOW 0x06a3
#define mmDC_PERFMON6_PERFMON_CVALUE_LOW_BASE_IDX 2
#define mmDC_PERFMON6_PERFMON_HI 0x06a4
#define mmDC_PERFMON6_PERFMON_HI_BASE_IDX 2
#define mmDC_PERFMON6_PERFMON_LOW 0x06a5
#define mmDC_PERFMON6_PERFMON_LOW_BASE_IDX 2
// addressBlock: dce_dc_dcbubp1_dispdec_hubp_dispdec
// base address: 0x370
#define mmHUBP1_DCSURF_SURFACE_CONFIG 0x06c1
#define mmHUBP1_DCSURF_SURFACE_CONFIG_BASE_IDX 2
#define mmHUBP1_DCSURF_ADDR_CONFIG 0x06c2
#define mmHUBP1_DCSURF_ADDR_CONFIG_BASE_IDX 2
#define mmHUBP1_DCSURF_TILING_CONFIG 0x06c3
#define mmHUBP1_DCSURF_TILING_CONFIG_BASE_IDX 2
#define mmHUBP1_DCSURF_PRI_VIEWPORT_START 0x06c5
#define mmHUBP1_DCSURF_PRI_VIEWPORT_START_BASE_IDX 2
#define mmHUBP1_DCSURF_PRI_VIEWPORT_DIMENSION 0x06c6
#define mmHUBP1_DCSURF_PRI_VIEWPORT_DIMENSION_BASE_IDX 2
#define mmHUBP1_DCSURF_PRI_VIEWPORT_START_C 0x06c7
#define mmHUBP1_DCSURF_PRI_VIEWPORT_START_C_BASE_IDX 2
#define mmHUBP1_DCSURF_PRI_VIEWPORT_DIMENSION_C 0x06c8
#define mmHUBP1_DCSURF_PRI_VIEWPORT_DIMENSION_C_BASE_IDX 2
#define mmHUBP1_DCSURF_SEC_VIEWPORT_START 0x06c9
#define mmHUBP1_DCSURF_SEC_VIEWPORT_START_BASE_IDX 2
#define mmHUBP1_DCSURF_SEC_VIEWPORT_DIMENSION 0x06ca
#define mmHUBP1_DCSURF_SEC_VIEWPORT_DIMENSION_BASE_IDX 2
#define mmHUBP1_DCSURF_SEC_VIEWPORT_START_C 0x06cb
#define mmHUBP1_DCSURF_SEC_VIEWPORT_START_C_BASE_IDX 2
#define mmHUBP1_DCSURF_SEC_VIEWPORT_DIMENSION_C 0x06cc
#define mmHUBP1_DCSURF_SEC_VIEWPORT_DIMENSION_C_BASE_IDX 2
#define mmHUBP1_DCHUBP_REQ_SIZE_CONFIG 0x06cd
#define mmHUBP1_DCHUBP_REQ_SIZE_CONFIG_BASE_IDX 2
#define mmHUBP1_DCHUBP_REQ_SIZE_CONFIG_C 0x06ce
#define mmHUBP1_DCHUBP_REQ_SIZE_CONFIG_C_BASE_IDX 2
#define mmHUBP1_DCHUBP_CNTL 0x06cf
#define mmHUBP1_DCHUBP_CNTL_BASE_IDX 2
#define mmHUBP1_HUBP_CLK_CNTL 0x06d0
#define mmHUBP1_HUBP_CLK_CNTL_BASE_IDX 2
#define mmHUBP1_DCHUBP_VMPG_CONFIG 0x06d1
#define mmHUBP1_DCHUBP_VMPG_CONFIG_BASE_IDX 2
#define mmHUBP1_HUBPREQ_DEBUG_DB 0x06d2
#define mmHUBP1_HUBPREQ_DEBUG_DB_BASE_IDX 2
#define mmHUBP1_HUBPREQ_DEBUG 0x06d3
#define mmHUBP1_HUBPREQ_DEBUG_BASE_IDX 2
#define mmHUBP1_HUBP_MEASURE_WIN_CTRL_DCFCLK 0x06d7
#define mmHUBP1_HUBP_MEASURE_WIN_CTRL_DCFCLK_BASE_IDX 2
#define mmHUBP1_HUBP_MEASURE_WIN_CTRL_DPPCLK 0x06d8
#define mmHUBP1_HUBP_MEASURE_WIN_CTRL_DPPCLK_BASE_IDX 2
// addressBlock: dce_dc_dcbubp1_dispdec_hubpreq_dispdec
// base address: 0x370
#define mmHUBPREQ1_DCSURF_SURFACE_PITCH 0x06e3
#define mmHUBPREQ1_DCSURF_SURFACE_PITCH_BASE_IDX 2
#define mmHUBPREQ1_DCSURF_SURFACE_PITCH_C 0x06e4
#define mmHUBPREQ1_DCSURF_SURFACE_PITCH_C_BASE_IDX 2
#define mmHUBPREQ1_VMID_SETTINGS_0 0x06e5
#define mmHUBPREQ1_VMID_SETTINGS_0_BASE_IDX 2
#define mmHUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS 0x06e6
#define mmHUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS_BASE_IDX 2
#define mmHUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH 0x06e7
#define mmHUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_BASE_IDX 2
#define mmHUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS_C 0x06e8
#define mmHUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS_C_BASE_IDX 2
#define mmHUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C 0x06e9
#define mmHUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C_BASE_IDX 2
#define mmHUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS 0x06ea
#define mmHUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS_BASE_IDX 2
#define mmHUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH 0x06eb
#define mmHUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_BASE_IDX 2
#define mmHUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS_C 0x06ec
#define mmHUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS_C_BASE_IDX 2
#define mmHUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C 0x06ed
#define mmHUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C_BASE_IDX 2
#define mmHUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS 0x06ee
#define mmHUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS_BASE_IDX 2
#define mmHUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH 0x06ef
#define mmHUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_BASE_IDX 2
#define mmHUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C 0x06f0
#define mmHUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C_BASE_IDX 2
#define mmHUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C 0x06f1
#define mmHUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C_BASE_IDX 2
#define mmHUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS 0x06f2
#define mmHUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS_BASE_IDX 2
#define mmHUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH 0x06f3
#define mmHUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_BASE_IDX 2
#define mmHUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C 0x06f4
#define mmHUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C_BASE_IDX 2
#define mmHUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C 0x06f5
#define your_sha256_hash 2
#define mmHUBPREQ1_DCSURF_SURFACE_CONTROL 0x06f6
#define mmHUBPREQ1_DCSURF_SURFACE_CONTROL_BASE_IDX 2
#define mmHUBPREQ1_DCSURF_FLIP_CONTROL 0x06f7
#define mmHUBPREQ1_DCSURF_FLIP_CONTROL_BASE_IDX 2
#define mmHUBPREQ1_DCSURF_FLIP_CONTROL2 0x06f8
#define mmHUBPREQ1_DCSURF_FLIP_CONTROL2_BASE_IDX 2
#define mmHUBPREQ1_DCSURF_SURFACE_FLIP_INTERRUPT 0x06fc
#define mmHUBPREQ1_DCSURF_SURFACE_FLIP_INTERRUPT_BASE_IDX 2
#define mmHUBPREQ1_DCSURF_SURFACE_INUSE 0x06fd
#define mmHUBPREQ1_DCSURF_SURFACE_INUSE_BASE_IDX 2
#define mmHUBPREQ1_DCSURF_SURFACE_INUSE_HIGH 0x06fe
#define mmHUBPREQ1_DCSURF_SURFACE_INUSE_HIGH_BASE_IDX 2
#define mmHUBPREQ1_DCSURF_SURFACE_INUSE_C 0x06ff
#define mmHUBPREQ1_DCSURF_SURFACE_INUSE_C_BASE_IDX 2
#define mmHUBPREQ1_DCSURF_SURFACE_INUSE_HIGH_C 0x0700
#define mmHUBPREQ1_DCSURF_SURFACE_INUSE_HIGH_C_BASE_IDX 2
#define mmHUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE 0x0701
#define mmHUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE_BASE_IDX 2
#define mmHUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE_HIGH 0x0702
#define mmHUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_BASE_IDX 2
#define mmHUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE_C 0x0703
#define mmHUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE_C_BASE_IDX 2
#define mmHUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C 0x0704
#define mmHUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C_BASE_IDX 2
#define mmHUBPREQ1_DCN_EXPANSION_MODE 0x0705
#define mmHUBPREQ1_DCN_EXPANSION_MODE_BASE_IDX 2
#define mmHUBPREQ1_DCN_TTU_QOS_WM 0x0706
#define mmHUBPREQ1_DCN_TTU_QOS_WM_BASE_IDX 2
#define mmHUBPREQ1_DCN_GLOBAL_TTU_CNTL 0x0707
#define mmHUBPREQ1_DCN_GLOBAL_TTU_CNTL_BASE_IDX 2
#define mmHUBPREQ1_DCN_SURF0_TTU_CNTL0 0x0708
#define mmHUBPREQ1_DCN_SURF0_TTU_CNTL0_BASE_IDX 2
#define mmHUBPREQ1_DCN_SURF0_TTU_CNTL1 0x0709
#define mmHUBPREQ1_DCN_SURF0_TTU_CNTL1_BASE_IDX 2
#define mmHUBPREQ1_DCN_SURF1_TTU_CNTL0 0x070a
#define mmHUBPREQ1_DCN_SURF1_TTU_CNTL0_BASE_IDX 2
#define mmHUBPREQ1_DCN_SURF1_TTU_CNTL1 0x070b
#define mmHUBPREQ1_DCN_SURF1_TTU_CNTL1_BASE_IDX 2
#define mmHUBPREQ1_DCN_CUR0_TTU_CNTL0 0x070c
#define mmHUBPREQ1_DCN_CUR0_TTU_CNTL0_BASE_IDX 2
#define mmHUBPREQ1_DCN_CUR0_TTU_CNTL1 0x070d
#define mmHUBPREQ1_DCN_CUR0_TTU_CNTL1_BASE_IDX 2
#define mmHUBPREQ1_DCN_CUR1_TTU_CNTL0 0x070e
#define mmHUBPREQ1_DCN_CUR1_TTU_CNTL0_BASE_IDX 2
#define mmHUBPREQ1_DCN_CUR1_TTU_CNTL1 0x070f
#define mmHUBPREQ1_DCN_CUR1_TTU_CNTL1_BASE_IDX 2
#define mmHUBPREQ1_DCN_DMDATA_VM_CNTL 0x0710
#define mmHUBPREQ1_DCN_DMDATA_VM_CNTL_BASE_IDX 2
#define mmHUBPREQ1_DCN_VM_SYSTEM_APERTURE_LOW_ADDR 0x0711
#define mmHUBPREQ1_DCN_VM_SYSTEM_APERTURE_LOW_ADDR_BASE_IDX 2
#define mmHUBPREQ1_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR 0x0712
#define mmHUBPREQ1_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR_BASE_IDX 2
#define mmHUBPREQ1_DCN_VM_MX_L1_TLB_CNTL 0x071f
#define mmHUBPREQ1_DCN_VM_MX_L1_TLB_CNTL_BASE_IDX 2
#define mmHUBPREQ1_BLANK_OFFSET_0 0x0720
#define mmHUBPREQ1_BLANK_OFFSET_0_BASE_IDX 2
#define mmHUBPREQ1_BLANK_OFFSET_1 0x0721
#define mmHUBPREQ1_BLANK_OFFSET_1_BASE_IDX 2
#define mmHUBPREQ1_DST_DIMENSIONS 0x0722
#define mmHUBPREQ1_DST_DIMENSIONS_BASE_IDX 2
#define mmHUBPREQ1_DST_AFTER_SCALER 0x0723
#define mmHUBPREQ1_DST_AFTER_SCALER_BASE_IDX 2
#define mmHUBPREQ1_PREFETCH_SETTINGS 0x0724
#define mmHUBPREQ1_PREFETCH_SETTINGS_BASE_IDX 2
#define mmHUBPREQ1_PREFETCH_SETTINGS_C 0x0725
#define mmHUBPREQ1_PREFETCH_SETTINGS_C_BASE_IDX 2
#define mmHUBPREQ1_VBLANK_PARAMETERS_0 0x0726
#define mmHUBPREQ1_VBLANK_PARAMETERS_0_BASE_IDX 2
#define mmHUBPREQ1_VBLANK_PARAMETERS_1 0x0727
#define mmHUBPREQ1_VBLANK_PARAMETERS_1_BASE_IDX 2
#define mmHUBPREQ1_VBLANK_PARAMETERS_2 0x0728
#define mmHUBPREQ1_VBLANK_PARAMETERS_2_BASE_IDX 2
#define mmHUBPREQ1_VBLANK_PARAMETERS_3 0x0729
#define mmHUBPREQ1_VBLANK_PARAMETERS_3_BASE_IDX 2
#define mmHUBPREQ1_VBLANK_PARAMETERS_4 0x072a
#define mmHUBPREQ1_VBLANK_PARAMETERS_4_BASE_IDX 2
#define mmHUBPREQ1_FLIP_PARAMETERS_0 0x072b
#define mmHUBPREQ1_FLIP_PARAMETERS_0_BASE_IDX 2
#define mmHUBPREQ1_FLIP_PARAMETERS_1 0x072c
#define mmHUBPREQ1_FLIP_PARAMETERS_1_BASE_IDX 2
#define mmHUBPREQ1_FLIP_PARAMETERS_2 0x072d
#define mmHUBPREQ1_FLIP_PARAMETERS_2_BASE_IDX 2
#define mmHUBPREQ1_NOM_PARAMETERS_0 0x072e
#define mmHUBPREQ1_NOM_PARAMETERS_0_BASE_IDX 2
#define mmHUBPREQ1_NOM_PARAMETERS_1 0x072f
#define mmHUBPREQ1_NOM_PARAMETERS_1_BASE_IDX 2
#define mmHUBPREQ1_NOM_PARAMETERS_2 0x0730
#define mmHUBPREQ1_NOM_PARAMETERS_2_BASE_IDX 2
#define mmHUBPREQ1_NOM_PARAMETERS_3 0x0731
#define mmHUBPREQ1_NOM_PARAMETERS_3_BASE_IDX 2
#define mmHUBPREQ1_NOM_PARAMETERS_4 0x0732
#define mmHUBPREQ1_NOM_PARAMETERS_4_BASE_IDX 2
#define mmHUBPREQ1_NOM_PARAMETERS_5 0x0733
#define mmHUBPREQ1_NOM_PARAMETERS_5_BASE_IDX 2
#define mmHUBPREQ1_NOM_PARAMETERS_6 0x0734
#define mmHUBPREQ1_NOM_PARAMETERS_6_BASE_IDX 2
#define mmHUBPREQ1_NOM_PARAMETERS_7 0x0735
#define mmHUBPREQ1_NOM_PARAMETERS_7_BASE_IDX 2
#define mmHUBPREQ1_PER_LINE_DELIVERY_PRE 0x0736
#define mmHUBPREQ1_PER_LINE_DELIVERY_PRE_BASE_IDX 2
#define mmHUBPREQ1_PER_LINE_DELIVERY 0x0737
#define mmHUBPREQ1_PER_LINE_DELIVERY_BASE_IDX 2
#define mmHUBPREQ1_CURSOR_SETTINGS 0x0738
#define mmHUBPREQ1_CURSOR_SETTINGS_BASE_IDX 2
#define mmHUBPREQ1_REF_FREQ_TO_PIX_FREQ 0x0739
#define mmHUBPREQ1_REF_FREQ_TO_PIX_FREQ_BASE_IDX 2
#define mmHUBPREQ1_DST_Y_DELTA_DRQ_LIMIT 0x073a
#define mmHUBPREQ1_DST_Y_DELTA_DRQ_LIMIT_BASE_IDX 2
#define mmHUBPREQ1_HUBPREQ_MEM_PWR_CTRL 0x073b
#define mmHUBPREQ1_HUBPREQ_MEM_PWR_CTRL_BASE_IDX 2
#define mmHUBPREQ1_HUBPREQ_MEM_PWR_STATUS 0x073c
#define mmHUBPREQ1_HUBPREQ_MEM_PWR_STATUS_BASE_IDX 2
#define mmHUBPREQ1_VBLANK_PARAMETERS_5 0x073f
#define mmHUBPREQ1_VBLANK_PARAMETERS_5_BASE_IDX 2
#define mmHUBPREQ1_VBLANK_PARAMETERS_6 0x0740
#define mmHUBPREQ1_VBLANK_PARAMETERS_6_BASE_IDX 2
#define mmHUBPREQ1_FLIP_PARAMETERS_3 0x0741
#define mmHUBPREQ1_FLIP_PARAMETERS_3_BASE_IDX 2
#define mmHUBPREQ1_FLIP_PARAMETERS_4 0x0742
#define mmHUBPREQ1_FLIP_PARAMETERS_4_BASE_IDX 2
#define mmHUBPREQ1_FLIP_PARAMETERS_5 0x0743
#define mmHUBPREQ1_FLIP_PARAMETERS_5_BASE_IDX 2
#define mmHUBPREQ1_FLIP_PARAMETERS_6 0x0744
#define mmHUBPREQ1_FLIP_PARAMETERS_6_BASE_IDX 2
// addressBlock: dce_dc_dcbubp1_dispdec_hubpret_dispdec
// base address: 0x370
#define mmHUBPRET1_HUBPRET_CONTROL 0x0748
#define mmHUBPRET1_HUBPRET_CONTROL_BASE_IDX 2
#define mmHUBPRET1_HUBPRET_MEM_PWR_CTRL 0x0749
#define mmHUBPRET1_HUBPRET_MEM_PWR_CTRL_BASE_IDX 2
#define mmHUBPRET1_HUBPRET_MEM_PWR_STATUS 0x074a
#define mmHUBPRET1_HUBPRET_MEM_PWR_STATUS_BASE_IDX 2
#define mmHUBPRET1_HUBPRET_READ_LINE_CTRL0 0x074b
#define mmHUBPRET1_HUBPRET_READ_LINE_CTRL0_BASE_IDX 2
#define mmHUBPRET1_HUBPRET_READ_LINE_CTRL1 0x074c
#define mmHUBPRET1_HUBPRET_READ_LINE_CTRL1_BASE_IDX 2
#define mmHUBPRET1_HUBPRET_READ_LINE0 0x074d
#define mmHUBPRET1_HUBPRET_READ_LINE0_BASE_IDX 2
#define mmHUBPRET1_HUBPRET_READ_LINE1 0x074e
#define mmHUBPRET1_HUBPRET_READ_LINE1_BASE_IDX 2
#define mmHUBPRET1_HUBPRET_INTERRUPT 0x074f
#define mmHUBPRET1_HUBPRET_INTERRUPT_BASE_IDX 2
#define mmHUBPRET1_HUBPRET_READ_LINE_VALUE 0x0750
#define mmHUBPRET1_HUBPRET_READ_LINE_VALUE_BASE_IDX 2
#define mmHUBPRET1_HUBPRET_READ_LINE_STATUS 0x0751
#define mmHUBPRET1_HUBPRET_READ_LINE_STATUS_BASE_IDX 2
// addressBlock: dce_dc_dcbubp1_dispdec_cursor0_dispdec
// base address: 0x370
#define mmCURSOR0_1_CURSOR_CONTROL 0x0754
#define mmCURSOR0_1_CURSOR_CONTROL_BASE_IDX 2
#define mmCURSOR0_1_CURSOR_SURFACE_ADDRESS 0x0755
#define mmCURSOR0_1_CURSOR_SURFACE_ADDRESS_BASE_IDX 2
#define mmCURSOR0_1_CURSOR_SURFACE_ADDRESS_HIGH 0x0756
#define mmCURSOR0_1_CURSOR_SURFACE_ADDRESS_HIGH_BASE_IDX 2
#define mmCURSOR0_1_CURSOR_SIZE 0x0757
#define mmCURSOR0_1_CURSOR_SIZE_BASE_IDX 2
#define mmCURSOR0_1_CURSOR_POSITION 0x0758
#define mmCURSOR0_1_CURSOR_POSITION_BASE_IDX 2
#define mmCURSOR0_1_CURSOR_HOT_SPOT 0x0759
#define mmCURSOR0_1_CURSOR_HOT_SPOT_BASE_IDX 2
#define mmCURSOR0_1_CURSOR_STEREO_CONTROL 0x075a
#define mmCURSOR0_1_CURSOR_STEREO_CONTROL_BASE_IDX 2
#define mmCURSOR0_1_CURSOR_DST_OFFSET 0x075b
#define mmCURSOR0_1_CURSOR_DST_OFFSET_BASE_IDX 2
#define mmCURSOR0_1_CURSOR_MEM_PWR_CTRL 0x075c
#define mmCURSOR0_1_CURSOR_MEM_PWR_CTRL_BASE_IDX 2
#define mmCURSOR0_1_CURSOR_MEM_PWR_STATUS 0x075d
#define mmCURSOR0_1_CURSOR_MEM_PWR_STATUS_BASE_IDX 2
#define mmCURSOR0_1_DMDATA_ADDRESS_HIGH 0x075e
#define mmCURSOR0_1_DMDATA_ADDRESS_HIGH_BASE_IDX 2
#define mmCURSOR0_1_DMDATA_ADDRESS_LOW 0x075f
#define mmCURSOR0_1_DMDATA_ADDRESS_LOW_BASE_IDX 2
#define mmCURSOR0_1_DMDATA_CNTL 0x0760
#define mmCURSOR0_1_DMDATA_CNTL_BASE_IDX 2
#define mmCURSOR0_1_DMDATA_QOS_CNTL 0x0761
#define mmCURSOR0_1_DMDATA_QOS_CNTL_BASE_IDX 2
#define mmCURSOR0_1_DMDATA_STATUS 0x0762
#define mmCURSOR0_1_DMDATA_STATUS_BASE_IDX 2
#define mmCURSOR0_1_DMDATA_SW_CNTL 0x0763
#define mmCURSOR0_1_DMDATA_SW_CNTL_BASE_IDX 2
#define mmCURSOR0_1_DMDATA_SW_DATA 0x0764
#define mmCURSOR0_1_DMDATA_SW_DATA_BASE_IDX 2
// addressBlock: dce_dc_dcbubp1_dispdec_hubp_dcperfmon_dc_perfmon_dispdec
// base address: 0x1de4
#define mmDC_PERFMON7_PERFCOUNTER_CNTL 0x0779
#define mmDC_PERFMON7_PERFCOUNTER_CNTL_BASE_IDX 2
#define mmDC_PERFMON7_PERFCOUNTER_CNTL2 0x077a
#define mmDC_PERFMON7_PERFCOUNTER_CNTL2_BASE_IDX 2
#define mmDC_PERFMON7_PERFCOUNTER_STATE 0x077b
#define mmDC_PERFMON7_PERFCOUNTER_STATE_BASE_IDX 2
#define mmDC_PERFMON7_PERFMON_CNTL 0x077c
#define mmDC_PERFMON7_PERFMON_CNTL_BASE_IDX 2
#define mmDC_PERFMON7_PERFMON_CNTL2 0x077d
#define mmDC_PERFMON7_PERFMON_CNTL2_BASE_IDX 2
#define mmDC_PERFMON7_PERFMON_CVALUE_INT_MISC 0x077e
#define mmDC_PERFMON7_PERFMON_CVALUE_INT_MISC_BASE_IDX 2
#define mmDC_PERFMON7_PERFMON_CVALUE_LOW 0x077f
#define mmDC_PERFMON7_PERFMON_CVALUE_LOW_BASE_IDX 2
#define mmDC_PERFMON7_PERFMON_HI 0x0780
#define mmDC_PERFMON7_PERFMON_HI_BASE_IDX 2
#define mmDC_PERFMON7_PERFMON_LOW 0x0781
#define mmDC_PERFMON7_PERFMON_LOW_BASE_IDX 2
// addressBlock: dce_dc_dcbubp2_dispdec_hubp_dispdec
// base address: 0x6e0
#define mmHUBP2_DCSURF_SURFACE_CONFIG 0x079d
#define mmHUBP2_DCSURF_SURFACE_CONFIG_BASE_IDX 2
#define mmHUBP2_DCSURF_ADDR_CONFIG 0x079e
#define mmHUBP2_DCSURF_ADDR_CONFIG_BASE_IDX 2
#define mmHUBP2_DCSURF_TILING_CONFIG 0x079f
#define mmHUBP2_DCSURF_TILING_CONFIG_BASE_IDX 2
#define mmHUBP2_DCSURF_PRI_VIEWPORT_START 0x07a1
#define mmHUBP2_DCSURF_PRI_VIEWPORT_START_BASE_IDX 2
#define mmHUBP2_DCSURF_PRI_VIEWPORT_DIMENSION 0x07a2
#define mmHUBP2_DCSURF_PRI_VIEWPORT_DIMENSION_BASE_IDX 2
#define mmHUBP2_DCSURF_PRI_VIEWPORT_START_C 0x07a3
#define mmHUBP2_DCSURF_PRI_VIEWPORT_START_C_BASE_IDX 2
#define mmHUBP2_DCSURF_PRI_VIEWPORT_DIMENSION_C 0x07a4
#define mmHUBP2_DCSURF_PRI_VIEWPORT_DIMENSION_C_BASE_IDX 2
#define mmHUBP2_DCSURF_SEC_VIEWPORT_START 0x07a5
#define mmHUBP2_DCSURF_SEC_VIEWPORT_START_BASE_IDX 2
#define mmHUBP2_DCSURF_SEC_VIEWPORT_DIMENSION 0x07a6
#define mmHUBP2_DCSURF_SEC_VIEWPORT_DIMENSION_BASE_IDX 2
#define mmHUBP2_DCSURF_SEC_VIEWPORT_START_C 0x07a7
#define mmHUBP2_DCSURF_SEC_VIEWPORT_START_C_BASE_IDX 2
#define mmHUBP2_DCSURF_SEC_VIEWPORT_DIMENSION_C 0x07a8
#define mmHUBP2_DCSURF_SEC_VIEWPORT_DIMENSION_C_BASE_IDX 2
#define mmHUBP2_DCHUBP_REQ_SIZE_CONFIG 0x07a9
#define mmHUBP2_DCHUBP_REQ_SIZE_CONFIG_BASE_IDX 2
#define mmHUBP2_DCHUBP_REQ_SIZE_CONFIG_C 0x07aa
#define mmHUBP2_DCHUBP_REQ_SIZE_CONFIG_C_BASE_IDX 2
#define mmHUBP2_DCHUBP_CNTL 0x07ab
#define mmHUBP2_DCHUBP_CNTL_BASE_IDX 2
#define mmHUBP2_HUBP_CLK_CNTL 0x07ac
#define mmHUBP2_HUBP_CLK_CNTL_BASE_IDX 2
#define mmHUBP2_DCHUBP_VMPG_CONFIG 0x07ad
#define mmHUBP2_DCHUBP_VMPG_CONFIG_BASE_IDX 2
#define mmHUBP2_HUBPREQ_DEBUG_DB 0x07ae
#define mmHUBP2_HUBPREQ_DEBUG_DB_BASE_IDX 2
#define mmHUBP2_HUBPREQ_DEBUG 0x07af
#define mmHUBP2_HUBPREQ_DEBUG_BASE_IDX 2
#define mmHUBP2_HUBP_MEASURE_WIN_CTRL_DCFCLK 0x07b3
#define mmHUBP2_HUBP_MEASURE_WIN_CTRL_DCFCLK_BASE_IDX 2
#define mmHUBP2_HUBP_MEASURE_WIN_CTRL_DPPCLK 0x07b4
#define mmHUBP2_HUBP_MEASURE_WIN_CTRL_DPPCLK_BASE_IDX 2
// addressBlock: dce_dc_dcbubp2_dispdec_hubpreq_dispdec
// base address: 0x6e0
#define mmHUBPREQ2_DCSURF_SURFACE_PITCH 0x07bf
#define mmHUBPREQ2_DCSURF_SURFACE_PITCH_BASE_IDX 2
#define mmHUBPREQ2_DCSURF_SURFACE_PITCH_C 0x07c0
#define mmHUBPREQ2_DCSURF_SURFACE_PITCH_C_BASE_IDX 2
#define mmHUBPREQ2_VMID_SETTINGS_0 0x07c1
#define mmHUBPREQ2_VMID_SETTINGS_0_BASE_IDX 2
#define mmHUBPREQ2_DCSURF_PRIMARY_SURFACE_ADDRESS 0x07c2
#define mmHUBPREQ2_DCSURF_PRIMARY_SURFACE_ADDRESS_BASE_IDX 2
#define mmHUBPREQ2_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH 0x07c3
#define mmHUBPREQ2_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_BASE_IDX 2
#define mmHUBPREQ2_DCSURF_PRIMARY_SURFACE_ADDRESS_C 0x07c4
#define mmHUBPREQ2_DCSURF_PRIMARY_SURFACE_ADDRESS_C_BASE_IDX 2
#define mmHUBPREQ2_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C 0x07c5
#define mmHUBPREQ2_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C_BASE_IDX 2
#define mmHUBPREQ2_DCSURF_SECONDARY_SURFACE_ADDRESS 0x07c6
#define mmHUBPREQ2_DCSURF_SECONDARY_SURFACE_ADDRESS_BASE_IDX 2
#define mmHUBPREQ2_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH 0x07c7
#define mmHUBPREQ2_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_BASE_IDX 2
#define mmHUBPREQ2_DCSURF_SECONDARY_SURFACE_ADDRESS_C 0x07c8
#define mmHUBPREQ2_DCSURF_SECONDARY_SURFACE_ADDRESS_C_BASE_IDX 2
#define mmHUBPREQ2_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C 0x07c9
#define mmHUBPREQ2_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C_BASE_IDX 2
#define mmHUBPREQ2_DCSURF_PRIMARY_META_SURFACE_ADDRESS 0x07ca
#define mmHUBPREQ2_DCSURF_PRIMARY_META_SURFACE_ADDRESS_BASE_IDX 2
#define mmHUBPREQ2_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH 0x07cb
#define mmHUBPREQ2_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_BASE_IDX 2
#define mmHUBPREQ2_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C 0x07cc
#define mmHUBPREQ2_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C_BASE_IDX 2
#define mmHUBPREQ2_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C 0x07cd
#define mmHUBPREQ2_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C_BASE_IDX 2
#define mmHUBPREQ2_DCSURF_SECONDARY_META_SURFACE_ADDRESS 0x07ce
#define mmHUBPREQ2_DCSURF_SECONDARY_META_SURFACE_ADDRESS_BASE_IDX 2
#define mmHUBPREQ2_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH 0x07cf
#define mmHUBPREQ2_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_BASE_IDX 2
#define mmHUBPREQ2_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C 0x07d0
#define mmHUBPREQ2_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C_BASE_IDX 2
#define mmHUBPREQ2_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C 0x07d1
#define your_sha256_hash 2
#define mmHUBPREQ2_DCSURF_SURFACE_CONTROL 0x07d2
#define mmHUBPREQ2_DCSURF_SURFACE_CONTROL_BASE_IDX 2
#define mmHUBPREQ2_DCSURF_FLIP_CONTROL 0x07d3
#define mmHUBPREQ2_DCSURF_FLIP_CONTROL_BASE_IDX 2
#define mmHUBPREQ2_DCSURF_FLIP_CONTROL2 0x07d4
#define mmHUBPREQ2_DCSURF_FLIP_CONTROL2_BASE_IDX 2
#define mmHUBPREQ2_DCSURF_SURFACE_FLIP_INTERRUPT 0x07d8
#define mmHUBPREQ2_DCSURF_SURFACE_FLIP_INTERRUPT_BASE_IDX 2
#define mmHUBPREQ2_DCSURF_SURFACE_INUSE 0x07d9
#define mmHUBPREQ2_DCSURF_SURFACE_INUSE_BASE_IDX 2
#define mmHUBPREQ2_DCSURF_SURFACE_INUSE_HIGH 0x07da
#define mmHUBPREQ2_DCSURF_SURFACE_INUSE_HIGH_BASE_IDX 2
#define mmHUBPREQ2_DCSURF_SURFACE_INUSE_C 0x07db
#define mmHUBPREQ2_DCSURF_SURFACE_INUSE_C_BASE_IDX 2
#define mmHUBPREQ2_DCSURF_SURFACE_INUSE_HIGH_C 0x07dc
#define mmHUBPREQ2_DCSURF_SURFACE_INUSE_HIGH_C_BASE_IDX 2
#define mmHUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE 0x07dd
#define mmHUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE_BASE_IDX 2
#define mmHUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE_HIGH 0x07de
#define mmHUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_BASE_IDX 2
#define mmHUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE_C 0x07df
#define mmHUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE_C_BASE_IDX 2
#define mmHUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C 0x07e0
#define mmHUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C_BASE_IDX 2
#define mmHUBPREQ2_DCN_EXPANSION_MODE 0x07e1
#define mmHUBPREQ2_DCN_EXPANSION_MODE_BASE_IDX 2
#define mmHUBPREQ2_DCN_TTU_QOS_WM 0x07e2
#define mmHUBPREQ2_DCN_TTU_QOS_WM_BASE_IDX 2
#define mmHUBPREQ2_DCN_GLOBAL_TTU_CNTL 0x07e3
#define mmHUBPREQ2_DCN_GLOBAL_TTU_CNTL_BASE_IDX 2
#define mmHUBPREQ2_DCN_SURF0_TTU_CNTL0 0x07e4
#define mmHUBPREQ2_DCN_SURF0_TTU_CNTL0_BASE_IDX 2
#define mmHUBPREQ2_DCN_SURF0_TTU_CNTL1 0x07e5
#define mmHUBPREQ2_DCN_SURF0_TTU_CNTL1_BASE_IDX 2
#define mmHUBPREQ2_DCN_SURF1_TTU_CNTL0 0x07e6
#define mmHUBPREQ2_DCN_SURF1_TTU_CNTL0_BASE_IDX 2
#define mmHUBPREQ2_DCN_SURF1_TTU_CNTL1 0x07e7
#define mmHUBPREQ2_DCN_SURF1_TTU_CNTL1_BASE_IDX 2
#define mmHUBPREQ2_DCN_CUR0_TTU_CNTL0 0x07e8
#define mmHUBPREQ2_DCN_CUR0_TTU_CNTL0_BASE_IDX 2
#define mmHUBPREQ2_DCN_CUR0_TTU_CNTL1 0x07e9
#define mmHUBPREQ2_DCN_CUR0_TTU_CNTL1_BASE_IDX 2
#define mmHUBPREQ2_DCN_CUR1_TTU_CNTL0 0x07ea
#define mmHUBPREQ2_DCN_CUR1_TTU_CNTL0_BASE_IDX 2
#define mmHUBPREQ2_DCN_CUR1_TTU_CNTL1 0x07eb
#define mmHUBPREQ2_DCN_CUR1_TTU_CNTL1_BASE_IDX 2
#define mmHUBPREQ2_DCN_DMDATA_VM_CNTL 0x07ec
#define mmHUBPREQ2_DCN_DMDATA_VM_CNTL_BASE_IDX 2
#define mmHUBPREQ2_DCN_VM_SYSTEM_APERTURE_LOW_ADDR 0x07ed
#define mmHUBPREQ2_DCN_VM_SYSTEM_APERTURE_LOW_ADDR_BASE_IDX 2
#define mmHUBPREQ2_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR 0x07ee
#define mmHUBPREQ2_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR_BASE_IDX 2
#define mmHUBPREQ2_DCN_VM_MX_L1_TLB_CNTL 0x07fb
#define mmHUBPREQ2_DCN_VM_MX_L1_TLB_CNTL_BASE_IDX 2
#define mmHUBPREQ2_BLANK_OFFSET_0 0x07fc
#define mmHUBPREQ2_BLANK_OFFSET_0_BASE_IDX 2
#define mmHUBPREQ2_BLANK_OFFSET_1 0x07fd
#define mmHUBPREQ2_BLANK_OFFSET_1_BASE_IDX 2
#define mmHUBPREQ2_DST_DIMENSIONS 0x07fe
#define mmHUBPREQ2_DST_DIMENSIONS_BASE_IDX 2
#define mmHUBPREQ2_DST_AFTER_SCALER 0x07ff
#define mmHUBPREQ2_DST_AFTER_SCALER_BASE_IDX 2
#define mmHUBPREQ2_PREFETCH_SETTINGS 0x0800
#define mmHUBPREQ2_PREFETCH_SETTINGS_BASE_IDX 2
#define mmHUBPREQ2_PREFETCH_SETTINGS_C 0x0801
#define mmHUBPREQ2_PREFETCH_SETTINGS_C_BASE_IDX 2
#define mmHUBPREQ2_VBLANK_PARAMETERS_0 0x0802
#define mmHUBPREQ2_VBLANK_PARAMETERS_0_BASE_IDX 2
#define mmHUBPREQ2_VBLANK_PARAMETERS_1 0x0803
#define mmHUBPREQ2_VBLANK_PARAMETERS_1_BASE_IDX 2
#define mmHUBPREQ2_VBLANK_PARAMETERS_2 0x0804
#define mmHUBPREQ2_VBLANK_PARAMETERS_2_BASE_IDX 2
#define mmHUBPREQ2_VBLANK_PARAMETERS_3 0x0805
#define mmHUBPREQ2_VBLANK_PARAMETERS_3_BASE_IDX 2
#define mmHUBPREQ2_VBLANK_PARAMETERS_4 0x0806
#define mmHUBPREQ2_VBLANK_PARAMETERS_4_BASE_IDX 2
#define mmHUBPREQ2_FLIP_PARAMETERS_0 0x0807
#define mmHUBPREQ2_FLIP_PARAMETERS_0_BASE_IDX 2
#define mmHUBPREQ2_FLIP_PARAMETERS_1 0x0808
#define mmHUBPREQ2_FLIP_PARAMETERS_1_BASE_IDX 2
#define mmHUBPREQ2_FLIP_PARAMETERS_2 0x0809
#define mmHUBPREQ2_FLIP_PARAMETERS_2_BASE_IDX 2
#define mmHUBPREQ2_NOM_PARAMETERS_0 0x080a
#define mmHUBPREQ2_NOM_PARAMETERS_0_BASE_IDX 2
#define mmHUBPREQ2_NOM_PARAMETERS_1 0x080b
#define mmHUBPREQ2_NOM_PARAMETERS_1_BASE_IDX 2
#define mmHUBPREQ2_NOM_PARAMETERS_2 0x080c
#define mmHUBPREQ2_NOM_PARAMETERS_2_BASE_IDX 2
#define mmHUBPREQ2_NOM_PARAMETERS_3 0x080d
#define mmHUBPREQ2_NOM_PARAMETERS_3_BASE_IDX 2
#define mmHUBPREQ2_NOM_PARAMETERS_4 0x080e
#define mmHUBPREQ2_NOM_PARAMETERS_4_BASE_IDX 2
#define mmHUBPREQ2_NOM_PARAMETERS_5 0x080f
#define mmHUBPREQ2_NOM_PARAMETERS_5_BASE_IDX 2
#define mmHUBPREQ2_NOM_PARAMETERS_6 0x0810
#define mmHUBPREQ2_NOM_PARAMETERS_6_BASE_IDX 2
#define mmHUBPREQ2_NOM_PARAMETERS_7 0x0811
#define mmHUBPREQ2_NOM_PARAMETERS_7_BASE_IDX 2
#define mmHUBPREQ2_PER_LINE_DELIVERY_PRE 0x0812
#define mmHUBPREQ2_PER_LINE_DELIVERY_PRE_BASE_IDX 2
#define mmHUBPREQ2_PER_LINE_DELIVERY 0x0813
#define mmHUBPREQ2_PER_LINE_DELIVERY_BASE_IDX 2
#define mmHUBPREQ2_CURSOR_SETTINGS 0x0814
#define mmHUBPREQ2_CURSOR_SETTINGS_BASE_IDX 2
#define mmHUBPREQ2_REF_FREQ_TO_PIX_FREQ 0x0815
#define mmHUBPREQ2_REF_FREQ_TO_PIX_FREQ_BASE_IDX 2
#define mmHUBPREQ2_DST_Y_DELTA_DRQ_LIMIT 0x0816
#define mmHUBPREQ2_DST_Y_DELTA_DRQ_LIMIT_BASE_IDX 2
#define mmHUBPREQ2_HUBPREQ_MEM_PWR_CTRL 0x0817
#define mmHUBPREQ2_HUBPREQ_MEM_PWR_CTRL_BASE_IDX 2
#define mmHUBPREQ2_HUBPREQ_MEM_PWR_STATUS 0x0818
#define mmHUBPREQ2_HUBPREQ_MEM_PWR_STATUS_BASE_IDX 2
#define mmHUBPREQ2_VBLANK_PARAMETERS_5 0x081b
#define mmHUBPREQ2_VBLANK_PARAMETERS_5_BASE_IDX 2
#define mmHUBPREQ2_VBLANK_PARAMETERS_6 0x081c
#define mmHUBPREQ2_VBLANK_PARAMETERS_6_BASE_IDX 2
#define mmHUBPREQ2_FLIP_PARAMETERS_3 0x081d
#define mmHUBPREQ2_FLIP_PARAMETERS_3_BASE_IDX 2
#define mmHUBPREQ2_FLIP_PARAMETERS_4 0x081e
#define mmHUBPREQ2_FLIP_PARAMETERS_4_BASE_IDX 2
#define mmHUBPREQ2_FLIP_PARAMETERS_5 0x081f
#define mmHUBPREQ2_FLIP_PARAMETERS_5_BASE_IDX 2
#define mmHUBPREQ2_FLIP_PARAMETERS_6 0x0820
#define mmHUBPREQ2_FLIP_PARAMETERS_6_BASE_IDX 2
// addressBlock: dce_dc_dcbubp2_dispdec_hubpret_dispdec
// base address: 0x6e0
#define mmHUBPRET2_HUBPRET_CONTROL 0x0824
#define mmHUBPRET2_HUBPRET_CONTROL_BASE_IDX 2
#define mmHUBPRET2_HUBPRET_MEM_PWR_CTRL 0x0825
#define mmHUBPRET2_HUBPRET_MEM_PWR_CTRL_BASE_IDX 2
#define mmHUBPRET2_HUBPRET_MEM_PWR_STATUS 0x0826
#define mmHUBPRET2_HUBPRET_MEM_PWR_STATUS_BASE_IDX 2
#define mmHUBPRET2_HUBPRET_READ_LINE_CTRL0 0x0827
#define mmHUBPRET2_HUBPRET_READ_LINE_CTRL0_BASE_IDX 2
#define mmHUBPRET2_HUBPRET_READ_LINE_CTRL1 0x0828
#define mmHUBPRET2_HUBPRET_READ_LINE_CTRL1_BASE_IDX 2
#define mmHUBPRET2_HUBPRET_READ_LINE0 0x0829
#define mmHUBPRET2_HUBPRET_READ_LINE0_BASE_IDX 2
#define mmHUBPRET2_HUBPRET_READ_LINE1 0x082a
#define mmHUBPRET2_HUBPRET_READ_LINE1_BASE_IDX 2
#define mmHUBPRET2_HUBPRET_INTERRUPT 0x082b
#define mmHUBPRET2_HUBPRET_INTERRUPT_BASE_IDX 2
#define mmHUBPRET2_HUBPRET_READ_LINE_VALUE 0x082c
#define mmHUBPRET2_HUBPRET_READ_LINE_VALUE_BASE_IDX 2
#define mmHUBPRET2_HUBPRET_READ_LINE_STATUS 0x082d
#define mmHUBPRET2_HUBPRET_READ_LINE_STATUS_BASE_IDX 2
// addressBlock: dce_dc_dcbubp2_dispdec_cursor0_dispdec
// base address: 0x6e0
#define mmCURSOR0_2_CURSOR_CONTROL 0x0830
#define mmCURSOR0_2_CURSOR_CONTROL_BASE_IDX 2
#define mmCURSOR0_2_CURSOR_SURFACE_ADDRESS 0x0831
#define mmCURSOR0_2_CURSOR_SURFACE_ADDRESS_BASE_IDX 2
#define mmCURSOR0_2_CURSOR_SURFACE_ADDRESS_HIGH 0x0832
#define mmCURSOR0_2_CURSOR_SURFACE_ADDRESS_HIGH_BASE_IDX 2
#define mmCURSOR0_2_CURSOR_SIZE 0x0833
#define mmCURSOR0_2_CURSOR_SIZE_BASE_IDX 2
#define mmCURSOR0_2_CURSOR_POSITION 0x0834
#define mmCURSOR0_2_CURSOR_POSITION_BASE_IDX 2
#define mmCURSOR0_2_CURSOR_HOT_SPOT 0x0835
#define mmCURSOR0_2_CURSOR_HOT_SPOT_BASE_IDX 2
#define mmCURSOR0_2_CURSOR_STEREO_CONTROL 0x0836
#define mmCURSOR0_2_CURSOR_STEREO_CONTROL_BASE_IDX 2
#define mmCURSOR0_2_CURSOR_DST_OFFSET 0x0837
#define mmCURSOR0_2_CURSOR_DST_OFFSET_BASE_IDX 2
#define mmCURSOR0_2_CURSOR_MEM_PWR_CTRL 0x0838
#define mmCURSOR0_2_CURSOR_MEM_PWR_CTRL_BASE_IDX 2
#define mmCURSOR0_2_CURSOR_MEM_PWR_STATUS 0x0839
#define mmCURSOR0_2_CURSOR_MEM_PWR_STATUS_BASE_IDX 2
#define mmCURSOR0_2_DMDATA_ADDRESS_HIGH 0x083a
#define mmCURSOR0_2_DMDATA_ADDRESS_HIGH_BASE_IDX 2
#define mmCURSOR0_2_DMDATA_ADDRESS_LOW 0x083b
#define mmCURSOR0_2_DMDATA_ADDRESS_LOW_BASE_IDX 2
#define mmCURSOR0_2_DMDATA_CNTL 0x083c
#define mmCURSOR0_2_DMDATA_CNTL_BASE_IDX 2
#define mmCURSOR0_2_DMDATA_QOS_CNTL 0x083d
#define mmCURSOR0_2_DMDATA_QOS_CNTL_BASE_IDX 2
#define mmCURSOR0_2_DMDATA_STATUS 0x083e
#define mmCURSOR0_2_DMDATA_STATUS_BASE_IDX 2
#define mmCURSOR0_2_DMDATA_SW_CNTL 0x083f
#define mmCURSOR0_2_DMDATA_SW_CNTL_BASE_IDX 2
#define mmCURSOR0_2_DMDATA_SW_DATA 0x0840
#define mmCURSOR0_2_DMDATA_SW_DATA_BASE_IDX 2
// addressBlock: dce_dc_dcbubp2_dispdec_hubp_dcperfmon_dc_perfmon_dispdec
// base address: 0x2154
#define mmDC_PERFMON8_PERFCOUNTER_CNTL 0x0855
#define mmDC_PERFMON8_PERFCOUNTER_CNTL_BASE_IDX 2
#define mmDC_PERFMON8_PERFCOUNTER_CNTL2 0x0856
#define mmDC_PERFMON8_PERFCOUNTER_CNTL2_BASE_IDX 2
#define mmDC_PERFMON8_PERFCOUNTER_STATE 0x0857
#define mmDC_PERFMON8_PERFCOUNTER_STATE_BASE_IDX 2
#define mmDC_PERFMON8_PERFMON_CNTL 0x0858
#define mmDC_PERFMON8_PERFMON_CNTL_BASE_IDX 2
#define mmDC_PERFMON8_PERFMON_CNTL2 0x0859
#define mmDC_PERFMON8_PERFMON_CNTL2_BASE_IDX 2
#define mmDC_PERFMON8_PERFMON_CVALUE_INT_MISC 0x085a
#define mmDC_PERFMON8_PERFMON_CVALUE_INT_MISC_BASE_IDX 2
#define mmDC_PERFMON8_PERFMON_CVALUE_LOW 0x085b
#define mmDC_PERFMON8_PERFMON_CVALUE_LOW_BASE_IDX 2
#define mmDC_PERFMON8_PERFMON_HI 0x085c
#define mmDC_PERFMON8_PERFMON_HI_BASE_IDX 2
#define mmDC_PERFMON8_PERFMON_LOW 0x085d
#define mmDC_PERFMON8_PERFMON_LOW_BASE_IDX 2
// addressBlock: dce_dc_dcbubp3_dispdec_hubp_dispdec
// base address: 0xa50
#define mmHUBP3_DCSURF_SURFACE_CONFIG 0x0879
#define mmHUBP3_DCSURF_SURFACE_CONFIG_BASE_IDX 2
#define mmHUBP3_DCSURF_ADDR_CONFIG 0x087a
#define mmHUBP3_DCSURF_ADDR_CONFIG_BASE_IDX 2
#define mmHUBP3_DCSURF_TILING_CONFIG 0x087b
#define mmHUBP3_DCSURF_TILING_CONFIG_BASE_IDX 2
#define mmHUBP3_DCSURF_PRI_VIEWPORT_START 0x087d
#define mmHUBP3_DCSURF_PRI_VIEWPORT_START_BASE_IDX 2
#define mmHUBP3_DCSURF_PRI_VIEWPORT_DIMENSION 0x087e
#define mmHUBP3_DCSURF_PRI_VIEWPORT_DIMENSION_BASE_IDX 2
#define mmHUBP3_DCSURF_PRI_VIEWPORT_START_C 0x087f
#define mmHUBP3_DCSURF_PRI_VIEWPORT_START_C_BASE_IDX 2
#define mmHUBP3_DCSURF_PRI_VIEWPORT_DIMENSION_C 0x0880
#define mmHUBP3_DCSURF_PRI_VIEWPORT_DIMENSION_C_BASE_IDX 2
#define mmHUBP3_DCSURF_SEC_VIEWPORT_START 0x0881
#define mmHUBP3_DCSURF_SEC_VIEWPORT_START_BASE_IDX 2
#define mmHUBP3_DCSURF_SEC_VIEWPORT_DIMENSION 0x0882
#define mmHUBP3_DCSURF_SEC_VIEWPORT_DIMENSION_BASE_IDX 2
#define mmHUBP3_DCSURF_SEC_VIEWPORT_START_C 0x0883
#define mmHUBP3_DCSURF_SEC_VIEWPORT_START_C_BASE_IDX 2
#define mmHUBP3_DCSURF_SEC_VIEWPORT_DIMENSION_C 0x0884
#define mmHUBP3_DCSURF_SEC_VIEWPORT_DIMENSION_C_BASE_IDX 2
#define mmHUBP3_DCHUBP_REQ_SIZE_CONFIG 0x0885
#define mmHUBP3_DCHUBP_REQ_SIZE_CONFIG_BASE_IDX 2
#define mmHUBP3_DCHUBP_REQ_SIZE_CONFIG_C 0x0886
#define mmHUBP3_DCHUBP_REQ_SIZE_CONFIG_C_BASE_IDX 2
#define mmHUBP3_DCHUBP_CNTL 0x0887
#define mmHUBP3_DCHUBP_CNTL_BASE_IDX 2
#define mmHUBP3_HUBP_CLK_CNTL 0x0888
#define mmHUBP3_HUBP_CLK_CNTL_BASE_IDX 2
#define mmHUBP3_DCHUBP_VMPG_CONFIG 0x0889
#define mmHUBP3_DCHUBP_VMPG_CONFIG_BASE_IDX 2
#define mmHUBP3_HUBPREQ_DEBUG_DB 0x088a
#define mmHUBP3_HUBPREQ_DEBUG_DB_BASE_IDX 2
#define mmHUBP3_HUBPREQ_DEBUG 0x088b
#define mmHUBP3_HUBPREQ_DEBUG_BASE_IDX 2
#define mmHUBP3_HUBP_MEASURE_WIN_CTRL_DCFCLK 0x088f
#define mmHUBP3_HUBP_MEASURE_WIN_CTRL_DCFCLK_BASE_IDX 2
#define mmHUBP3_HUBP_MEASURE_WIN_CTRL_DPPCLK 0x0890
#define mmHUBP3_HUBP_MEASURE_WIN_CTRL_DPPCLK_BASE_IDX 2
// addressBlock: dce_dc_dcbubp3_dispdec_hubpreq_dispdec
// base address: 0xa50
#define mmHUBPREQ3_DCSURF_SURFACE_PITCH 0x089b
#define mmHUBPREQ3_DCSURF_SURFACE_PITCH_BASE_IDX 2
#define mmHUBPREQ3_DCSURF_SURFACE_PITCH_C 0x089c
#define mmHUBPREQ3_DCSURF_SURFACE_PITCH_C_BASE_IDX 2
#define mmHUBPREQ3_VMID_SETTINGS_0 0x089d
#define mmHUBPREQ3_VMID_SETTINGS_0_BASE_IDX 2
#define mmHUBPREQ3_DCSURF_PRIMARY_SURFACE_ADDRESS 0x089e
#define mmHUBPREQ3_DCSURF_PRIMARY_SURFACE_ADDRESS_BASE_IDX 2
#define mmHUBPREQ3_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH 0x089f
#define mmHUBPREQ3_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_BASE_IDX 2
#define mmHUBPREQ3_DCSURF_PRIMARY_SURFACE_ADDRESS_C 0x08a0
#define mmHUBPREQ3_DCSURF_PRIMARY_SURFACE_ADDRESS_C_BASE_IDX 2
#define mmHUBPREQ3_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C 0x08a1
#define mmHUBPREQ3_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C_BASE_IDX 2
#define mmHUBPREQ3_DCSURF_SECONDARY_SURFACE_ADDRESS 0x08a2
#define mmHUBPREQ3_DCSURF_SECONDARY_SURFACE_ADDRESS_BASE_IDX 2
#define mmHUBPREQ3_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH 0x08a3
#define mmHUBPREQ3_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_BASE_IDX 2
#define mmHUBPREQ3_DCSURF_SECONDARY_SURFACE_ADDRESS_C 0x08a4
#define mmHUBPREQ3_DCSURF_SECONDARY_SURFACE_ADDRESS_C_BASE_IDX 2
#define mmHUBPREQ3_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C 0x08a5
#define mmHUBPREQ3_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C_BASE_IDX 2
#define mmHUBPREQ3_DCSURF_PRIMARY_META_SURFACE_ADDRESS 0x08a6
#define mmHUBPREQ3_DCSURF_PRIMARY_META_SURFACE_ADDRESS_BASE_IDX 2
#define mmHUBPREQ3_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH 0x08a7
#define mmHUBPREQ3_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_BASE_IDX 2
#define mmHUBPREQ3_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C 0x08a8
#define mmHUBPREQ3_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C_BASE_IDX 2
#define mmHUBPREQ3_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C 0x08a9
#define mmHUBPREQ3_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C_BASE_IDX 2
#define mmHUBPREQ3_DCSURF_SECONDARY_META_SURFACE_ADDRESS 0x08aa
#define mmHUBPREQ3_DCSURF_SECONDARY_META_SURFACE_ADDRESS_BASE_IDX 2
#define mmHUBPREQ3_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH 0x08ab
#define mmHUBPREQ3_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_BASE_IDX 2
#define mmHUBPREQ3_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C 0x08ac
#define mmHUBPREQ3_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C_BASE_IDX 2
#define mmHUBPREQ3_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C 0x08ad
#define your_sha256_hash 2
#define mmHUBPREQ3_DCSURF_SURFACE_CONTROL 0x08ae
#define mmHUBPREQ3_DCSURF_SURFACE_CONTROL_BASE_IDX 2
#define mmHUBPREQ3_DCSURF_FLIP_CONTROL 0x08af
#define mmHUBPREQ3_DCSURF_FLIP_CONTROL_BASE_IDX 2
#define mmHUBPREQ3_DCSURF_FLIP_CONTROL2 0x08b0
#define mmHUBPREQ3_DCSURF_FLIP_CONTROL2_BASE_IDX 2
#define mmHUBPREQ3_DCSURF_SURFACE_FLIP_INTERRUPT 0x08b4
#define mmHUBPREQ3_DCSURF_SURFACE_FLIP_INTERRUPT_BASE_IDX 2
#define mmHUBPREQ3_DCSURF_SURFACE_INUSE 0x08b5
#define mmHUBPREQ3_DCSURF_SURFACE_INUSE_BASE_IDX 2
#define mmHUBPREQ3_DCSURF_SURFACE_INUSE_HIGH 0x08b6
#define mmHUBPREQ3_DCSURF_SURFACE_INUSE_HIGH_BASE_IDX 2
#define mmHUBPREQ3_DCSURF_SURFACE_INUSE_C 0x08b7
#define mmHUBPREQ3_DCSURF_SURFACE_INUSE_C_BASE_IDX 2
#define mmHUBPREQ3_DCSURF_SURFACE_INUSE_HIGH_C 0x08b8
#define mmHUBPREQ3_DCSURF_SURFACE_INUSE_HIGH_C_BASE_IDX 2
#define mmHUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE 0x08b9
#define mmHUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE_BASE_IDX 2
#define mmHUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE_HIGH 0x08ba
#define mmHUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_BASE_IDX 2
#define mmHUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE_C 0x08bb
#define mmHUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE_C_BASE_IDX 2
#define mmHUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C 0x08bc
#define mmHUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C_BASE_IDX 2
#define mmHUBPREQ3_DCN_EXPANSION_MODE 0x08bd
#define mmHUBPREQ3_DCN_EXPANSION_MODE_BASE_IDX 2
#define mmHUBPREQ3_DCN_TTU_QOS_WM 0x08be
#define mmHUBPREQ3_DCN_TTU_QOS_WM_BASE_IDX 2
#define mmHUBPREQ3_DCN_GLOBAL_TTU_CNTL 0x08bf
#define mmHUBPREQ3_DCN_GLOBAL_TTU_CNTL_BASE_IDX 2
#define mmHUBPREQ3_DCN_SURF0_TTU_CNTL0 0x08c0
#define mmHUBPREQ3_DCN_SURF0_TTU_CNTL0_BASE_IDX 2
#define mmHUBPREQ3_DCN_SURF0_TTU_CNTL1 0x08c1
#define mmHUBPREQ3_DCN_SURF0_TTU_CNTL1_BASE_IDX 2
#define mmHUBPREQ3_DCN_SURF1_TTU_CNTL0 0x08c2
#define mmHUBPREQ3_DCN_SURF1_TTU_CNTL0_BASE_IDX 2
#define mmHUBPREQ3_DCN_SURF1_TTU_CNTL1 0x08c3
#define mmHUBPREQ3_DCN_SURF1_TTU_CNTL1_BASE_IDX 2
#define mmHUBPREQ3_DCN_CUR0_TTU_CNTL0 0x08c4
#define mmHUBPREQ3_DCN_CUR0_TTU_CNTL0_BASE_IDX 2
#define mmHUBPREQ3_DCN_CUR0_TTU_CNTL1 0x08c5
#define mmHUBPREQ3_DCN_CUR0_TTU_CNTL1_BASE_IDX 2
#define mmHUBPREQ3_DCN_CUR1_TTU_CNTL0 0x08c6
#define mmHUBPREQ3_DCN_CUR1_TTU_CNTL0_BASE_IDX 2
#define mmHUBPREQ3_DCN_CUR1_TTU_CNTL1 0x08c7
#define mmHUBPREQ3_DCN_CUR1_TTU_CNTL1_BASE_IDX 2
#define mmHUBPREQ3_DCN_DMDATA_VM_CNTL 0x08c8
#define mmHUBPREQ3_DCN_DMDATA_VM_CNTL_BASE_IDX 2
#define mmHUBPREQ3_DCN_VM_SYSTEM_APERTURE_LOW_ADDR 0x08c9
#define mmHUBPREQ3_DCN_VM_SYSTEM_APERTURE_LOW_ADDR_BASE_IDX 2
#define mmHUBPREQ3_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR 0x08ca
#define mmHUBPREQ3_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR_BASE_IDX 2
#define mmHUBPREQ3_DCN_VM_MX_L1_TLB_CNTL 0x08d7
#define mmHUBPREQ3_DCN_VM_MX_L1_TLB_CNTL_BASE_IDX 2
#define mmHUBPREQ3_BLANK_OFFSET_0 0x08d8
#define mmHUBPREQ3_BLANK_OFFSET_0_BASE_IDX 2
#define mmHUBPREQ3_BLANK_OFFSET_1 0x08d9
#define mmHUBPREQ3_BLANK_OFFSET_1_BASE_IDX 2
#define mmHUBPREQ3_DST_DIMENSIONS 0x08da
#define mmHUBPREQ3_DST_DIMENSIONS_BASE_IDX 2
#define mmHUBPREQ3_DST_AFTER_SCALER 0x08db
#define mmHUBPREQ3_DST_AFTER_SCALER_BASE_IDX 2
#define mmHUBPREQ3_PREFETCH_SETTINGS 0x08dc
#define mmHUBPREQ3_PREFETCH_SETTINGS_BASE_IDX 2
#define mmHUBPREQ3_PREFETCH_SETTINGS_C 0x08dd
#define mmHUBPREQ3_PREFETCH_SETTINGS_C_BASE_IDX 2
#define mmHUBPREQ3_VBLANK_PARAMETERS_0 0x08de
#define mmHUBPREQ3_VBLANK_PARAMETERS_0_BASE_IDX 2
#define mmHUBPREQ3_VBLANK_PARAMETERS_1 0x08df
#define mmHUBPREQ3_VBLANK_PARAMETERS_1_BASE_IDX 2
#define mmHUBPREQ3_VBLANK_PARAMETERS_2 0x08e0
#define mmHUBPREQ3_VBLANK_PARAMETERS_2_BASE_IDX 2
#define mmHUBPREQ3_VBLANK_PARAMETERS_3 0x08e1
#define mmHUBPREQ3_VBLANK_PARAMETERS_3_BASE_IDX 2
#define mmHUBPREQ3_VBLANK_PARAMETERS_4 0x08e2
#define mmHUBPREQ3_VBLANK_PARAMETERS_4_BASE_IDX 2
#define mmHUBPREQ3_FLIP_PARAMETERS_0 0x08e3
#define mmHUBPREQ3_FLIP_PARAMETERS_0_BASE_IDX 2
#define mmHUBPREQ3_FLIP_PARAMETERS_1 0x08e4
#define mmHUBPREQ3_FLIP_PARAMETERS_1_BASE_IDX 2
#define mmHUBPREQ3_FLIP_PARAMETERS_2 0x08e5
#define mmHUBPREQ3_FLIP_PARAMETERS_2_BASE_IDX 2
#define mmHUBPREQ3_NOM_PARAMETERS_0 0x08e6
#define mmHUBPREQ3_NOM_PARAMETERS_0_BASE_IDX 2
#define mmHUBPREQ3_NOM_PARAMETERS_1 0x08e7
#define mmHUBPREQ3_NOM_PARAMETERS_1_BASE_IDX 2
#define mmHUBPREQ3_NOM_PARAMETERS_2 0x08e8
#define mmHUBPREQ3_NOM_PARAMETERS_2_BASE_IDX 2
#define mmHUBPREQ3_NOM_PARAMETERS_3 0x08e9
#define mmHUBPREQ3_NOM_PARAMETERS_3_BASE_IDX 2
#define mmHUBPREQ3_NOM_PARAMETERS_4 0x08ea
#define mmHUBPREQ3_NOM_PARAMETERS_4_BASE_IDX 2
#define mmHUBPREQ3_NOM_PARAMETERS_5 0x08eb
#define mmHUBPREQ3_NOM_PARAMETERS_5_BASE_IDX 2
#define mmHUBPREQ3_NOM_PARAMETERS_6 0x08ec
#define mmHUBPREQ3_NOM_PARAMETERS_6_BASE_IDX 2
#define mmHUBPREQ3_NOM_PARAMETERS_7 0x08ed
#define mmHUBPREQ3_NOM_PARAMETERS_7_BASE_IDX 2
#define mmHUBPREQ3_PER_LINE_DELIVERY_PRE 0x08ee
#define mmHUBPREQ3_PER_LINE_DELIVERY_PRE_BASE_IDX 2
#define mmHUBPREQ3_PER_LINE_DELIVERY 0x08ef
#define mmHUBPREQ3_PER_LINE_DELIVERY_BASE_IDX 2
#define mmHUBPREQ3_CURSOR_SETTINGS 0x08f0
#define mmHUBPREQ3_CURSOR_SETTINGS_BASE_IDX 2
#define mmHUBPREQ3_REF_FREQ_TO_PIX_FREQ 0x08f1
#define mmHUBPREQ3_REF_FREQ_TO_PIX_FREQ_BASE_IDX 2
#define mmHUBPREQ3_DST_Y_DELTA_DRQ_LIMIT 0x08f2
#define mmHUBPREQ3_DST_Y_DELTA_DRQ_LIMIT_BASE_IDX 2
#define mmHUBPREQ3_HUBPREQ_MEM_PWR_CTRL 0x08f3
#define mmHUBPREQ3_HUBPREQ_MEM_PWR_CTRL_BASE_IDX 2
#define mmHUBPREQ3_HUBPREQ_MEM_PWR_STATUS 0x08f4
#define mmHUBPREQ3_HUBPREQ_MEM_PWR_STATUS_BASE_IDX 2
#define mmHUBPREQ3_VBLANK_PARAMETERS_5 0x08f7
#define mmHUBPREQ3_VBLANK_PARAMETERS_5_BASE_IDX 2
#define mmHUBPREQ3_VBLANK_PARAMETERS_6 0x08f8
#define mmHUBPREQ3_VBLANK_PARAMETERS_6_BASE_IDX 2
#define mmHUBPREQ3_FLIP_PARAMETERS_3 0x08f9
#define mmHUBPREQ3_FLIP_PARAMETERS_3_BASE_IDX 2
#define mmHUBPREQ3_FLIP_PARAMETERS_4 0x08fa
#define mmHUBPREQ3_FLIP_PARAMETERS_4_BASE_IDX 2
#define mmHUBPREQ3_FLIP_PARAMETERS_5 0x08fb
#define mmHUBPREQ3_FLIP_PARAMETERS_5_BASE_IDX 2
#define mmHUBPREQ3_FLIP_PARAMETERS_6 0x08fc
#define mmHUBPREQ3_FLIP_PARAMETERS_6_BASE_IDX 2
// addressBlock: dce_dc_dcbubp3_dispdec_hubpret_dispdec
// base address: 0xa50
#define mmHUBPRET3_HUBPRET_CONTROL 0x0900
#define mmHUBPRET3_HUBPRET_CONTROL_BASE_IDX 2
#define mmHUBPRET3_HUBPRET_MEM_PWR_CTRL 0x0901
#define mmHUBPRET3_HUBPRET_MEM_PWR_CTRL_BASE_IDX 2
#define mmHUBPRET3_HUBPRET_MEM_PWR_STATUS 0x0902
#define mmHUBPRET3_HUBPRET_MEM_PWR_STATUS_BASE_IDX 2
#define mmHUBPRET3_HUBPRET_READ_LINE_CTRL0 0x0903
#define mmHUBPRET3_HUBPRET_READ_LINE_CTRL0_BASE_IDX 2
#define mmHUBPRET3_HUBPRET_READ_LINE_CTRL1 0x0904
#define mmHUBPRET3_HUBPRET_READ_LINE_CTRL1_BASE_IDX 2
#define mmHUBPRET3_HUBPRET_READ_LINE0 0x0905
#define mmHUBPRET3_HUBPRET_READ_LINE0_BASE_IDX 2
#define mmHUBPRET3_HUBPRET_READ_LINE1 0x0906
#define mmHUBPRET3_HUBPRET_READ_LINE1_BASE_IDX 2
#define mmHUBPRET3_HUBPRET_INTERRUPT 0x0907
#define mmHUBPRET3_HUBPRET_INTERRUPT_BASE_IDX 2
#define mmHUBPRET3_HUBPRET_READ_LINE_VALUE 0x0908
#define mmHUBPRET3_HUBPRET_READ_LINE_VALUE_BASE_IDX 2
#define mmHUBPRET3_HUBPRET_READ_LINE_STATUS 0x0909
#define mmHUBPRET3_HUBPRET_READ_LINE_STATUS_BASE_IDX 2
// addressBlock: dce_dc_dcbubp3_dispdec_cursor0_dispdec
// base address: 0xa50
#define mmCURSOR0_3_CURSOR_CONTROL 0x090c
#define mmCURSOR0_3_CURSOR_CONTROL_BASE_IDX 2
#define mmCURSOR0_3_CURSOR_SURFACE_ADDRESS 0x090d
#define mmCURSOR0_3_CURSOR_SURFACE_ADDRESS_BASE_IDX 2
#define mmCURSOR0_3_CURSOR_SURFACE_ADDRESS_HIGH 0x090e
#define mmCURSOR0_3_CURSOR_SURFACE_ADDRESS_HIGH_BASE_IDX 2
#define mmCURSOR0_3_CURSOR_SIZE 0x090f
#define mmCURSOR0_3_CURSOR_SIZE_BASE_IDX 2
#define mmCURSOR0_3_CURSOR_POSITION 0x0910
#define mmCURSOR0_3_CURSOR_POSITION_BASE_IDX 2
#define mmCURSOR0_3_CURSOR_HOT_SPOT 0x0911
#define mmCURSOR0_3_CURSOR_HOT_SPOT_BASE_IDX 2
#define mmCURSOR0_3_CURSOR_STEREO_CONTROL 0x0912
#define mmCURSOR0_3_CURSOR_STEREO_CONTROL_BASE_IDX 2
#define mmCURSOR0_3_CURSOR_DST_OFFSET 0x0913
#define mmCURSOR0_3_CURSOR_DST_OFFSET_BASE_IDX 2
#define mmCURSOR0_3_CURSOR_MEM_PWR_CTRL 0x0914
#define mmCURSOR0_3_CURSOR_MEM_PWR_CTRL_BASE_IDX 2
#define mmCURSOR0_3_CURSOR_MEM_PWR_STATUS 0x0915
#define mmCURSOR0_3_CURSOR_MEM_PWR_STATUS_BASE_IDX 2
#define mmCURSOR0_3_DMDATA_ADDRESS_HIGH 0x0916
#define mmCURSOR0_3_DMDATA_ADDRESS_HIGH_BASE_IDX 2
#define mmCURSOR0_3_DMDATA_ADDRESS_LOW 0x0917
#define mmCURSOR0_3_DMDATA_ADDRESS_LOW_BASE_IDX 2
#define mmCURSOR0_3_DMDATA_CNTL 0x0918
#define mmCURSOR0_3_DMDATA_CNTL_BASE_IDX 2
#define mmCURSOR0_3_DMDATA_QOS_CNTL 0x0919
#define mmCURSOR0_3_DMDATA_QOS_CNTL_BASE_IDX 2
#define mmCURSOR0_3_DMDATA_STATUS 0x091a
#define mmCURSOR0_3_DMDATA_STATUS_BASE_IDX 2
#define mmCURSOR0_3_DMDATA_SW_CNTL 0x091b
#define mmCURSOR0_3_DMDATA_SW_CNTL_BASE_IDX 2
#define mmCURSOR0_3_DMDATA_SW_DATA 0x091c
#define mmCURSOR0_3_DMDATA_SW_DATA_BASE_IDX 2
// addressBlock: dce_dc_dcbubp3_dispdec_hubp_dcperfmon_dc_perfmon_dispdec
// base address: 0x24c4
#define mmDC_PERFMON9_PERFCOUNTER_CNTL 0x0931
#define mmDC_PERFMON9_PERFCOUNTER_CNTL_BASE_IDX 2
#define mmDC_PERFMON9_PERFCOUNTER_CNTL2 0x0932
#define mmDC_PERFMON9_PERFCOUNTER_CNTL2_BASE_IDX 2
#define mmDC_PERFMON9_PERFCOUNTER_STATE 0x0933
#define mmDC_PERFMON9_PERFCOUNTER_STATE_BASE_IDX 2
#define mmDC_PERFMON9_PERFMON_CNTL 0x0934
#define mmDC_PERFMON9_PERFMON_CNTL_BASE_IDX 2
#define mmDC_PERFMON9_PERFMON_CNTL2 0x0935
#define mmDC_PERFMON9_PERFMON_CNTL2_BASE_IDX 2
#define mmDC_PERFMON9_PERFMON_CVALUE_INT_MISC 0x0936
#define mmDC_PERFMON9_PERFMON_CVALUE_INT_MISC_BASE_IDX 2
#define mmDC_PERFMON9_PERFMON_CVALUE_LOW 0x0937
#define mmDC_PERFMON9_PERFMON_CVALUE_LOW_BASE_IDX 2
#define mmDC_PERFMON9_PERFMON_HI 0x0938
#define mmDC_PERFMON9_PERFMON_HI_BASE_IDX 2
#define mmDC_PERFMON9_PERFMON_LOW 0x0939
#define mmDC_PERFMON9_PERFMON_LOW_BASE_IDX 2
// addressBlock: dce_dc_dcbubp4_dispdec_hubp_dispdec
// base address: 0xdc0
#define mmHUBP4_DCSURF_SURFACE_CONFIG 0x0955
#define mmHUBP4_DCSURF_SURFACE_CONFIG_BASE_IDX 2
#define mmHUBP4_DCSURF_ADDR_CONFIG 0x0956
#define mmHUBP4_DCSURF_ADDR_CONFIG_BASE_IDX 2
#define mmHUBP4_DCSURF_TILING_CONFIG 0x0957
#define mmHUBP4_DCSURF_TILING_CONFIG_BASE_IDX 2
#define mmHUBP4_DCSURF_PRI_VIEWPORT_START 0x0959
#define mmHUBP4_DCSURF_PRI_VIEWPORT_START_BASE_IDX 2
#define mmHUBP4_DCSURF_PRI_VIEWPORT_DIMENSION 0x095a
#define mmHUBP4_DCSURF_PRI_VIEWPORT_DIMENSION_BASE_IDX 2
#define mmHUBP4_DCSURF_PRI_VIEWPORT_START_C 0x095b
#define mmHUBP4_DCSURF_PRI_VIEWPORT_START_C_BASE_IDX 2
#define mmHUBP4_DCSURF_PRI_VIEWPORT_DIMENSION_C 0x095c
#define mmHUBP4_DCSURF_PRI_VIEWPORT_DIMENSION_C_BASE_IDX 2
#define mmHUBP4_DCSURF_SEC_VIEWPORT_START 0x095d
#define mmHUBP4_DCSURF_SEC_VIEWPORT_START_BASE_IDX 2
#define mmHUBP4_DCSURF_SEC_VIEWPORT_DIMENSION 0x095e
#define mmHUBP4_DCSURF_SEC_VIEWPORT_DIMENSION_BASE_IDX 2
#define mmHUBP4_DCSURF_SEC_VIEWPORT_START_C 0x095f
#define mmHUBP4_DCSURF_SEC_VIEWPORT_START_C_BASE_IDX 2
#define mmHUBP4_DCSURF_SEC_VIEWPORT_DIMENSION_C 0x0960
#define mmHUBP4_DCSURF_SEC_VIEWPORT_DIMENSION_C_BASE_IDX 2
#define mmHUBP4_DCHUBP_REQ_SIZE_CONFIG 0x0961
#define mmHUBP4_DCHUBP_REQ_SIZE_CONFIG_BASE_IDX 2
#define mmHUBP4_DCHUBP_REQ_SIZE_CONFIG_C 0x0962
#define mmHUBP4_DCHUBP_REQ_SIZE_CONFIG_C_BASE_IDX 2
#define mmHUBP4_DCHUBP_CNTL 0x0963
#define mmHUBP4_DCHUBP_CNTL_BASE_IDX 2
#define mmHUBP4_HUBP_CLK_CNTL 0x0964
#define mmHUBP4_HUBP_CLK_CNTL_BASE_IDX 2
#define mmHUBP4_DCHUBP_VMPG_CONFIG 0x0965
#define mmHUBP4_DCHUBP_VMPG_CONFIG_BASE_IDX 2
#define mmHUBP4_HUBPREQ_DEBUG_DB 0x0966
#define mmHUBP4_HUBPREQ_DEBUG_DB_BASE_IDX 2
#define mmHUBP4_HUBPREQ_DEBUG 0x0967
#define mmHUBP4_HUBPREQ_DEBUG_BASE_IDX 2
#define mmHUBP4_HUBP_MEASURE_WIN_CTRL_DCFCLK 0x096b
#define mmHUBP4_HUBP_MEASURE_WIN_CTRL_DCFCLK_BASE_IDX 2
#define mmHUBP4_HUBP_MEASURE_WIN_CTRL_DPPCLK 0x096c
#define mmHUBP4_HUBP_MEASURE_WIN_CTRL_DPPCLK_BASE_IDX 2
// addressBlock: dce_dc_dcbubp4_dispdec_hubpreq_dispdec
// base address: 0xdc0
#define mmHUBPREQ4_DCSURF_SURFACE_PITCH 0x0977
#define mmHUBPREQ4_DCSURF_SURFACE_PITCH_BASE_IDX 2
#define mmHUBPREQ4_DCSURF_SURFACE_PITCH_C 0x0978
#define mmHUBPREQ4_DCSURF_SURFACE_PITCH_C_BASE_IDX 2
#define mmHUBPREQ4_VMID_SETTINGS_0 0x0979
#define mmHUBPREQ4_VMID_SETTINGS_0_BASE_IDX 2
#define mmHUBPREQ4_DCSURF_PRIMARY_SURFACE_ADDRESS 0x097a
#define mmHUBPREQ4_DCSURF_PRIMARY_SURFACE_ADDRESS_BASE_IDX 2
#define mmHUBPREQ4_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH 0x097b
#define mmHUBPREQ4_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_BASE_IDX 2
#define mmHUBPREQ4_DCSURF_PRIMARY_SURFACE_ADDRESS_C 0x097c
#define mmHUBPREQ4_DCSURF_PRIMARY_SURFACE_ADDRESS_C_BASE_IDX 2
#define mmHUBPREQ4_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C 0x097d
#define mmHUBPREQ4_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C_BASE_IDX 2
#define mmHUBPREQ4_DCSURF_SECONDARY_SURFACE_ADDRESS 0x097e
#define mmHUBPREQ4_DCSURF_SECONDARY_SURFACE_ADDRESS_BASE_IDX 2
#define mmHUBPREQ4_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH 0x097f
#define mmHUBPREQ4_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_BASE_IDX 2
#define mmHUBPREQ4_DCSURF_SECONDARY_SURFACE_ADDRESS_C 0x0980
#define mmHUBPREQ4_DCSURF_SECONDARY_SURFACE_ADDRESS_C_BASE_IDX 2
#define mmHUBPREQ4_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C 0x0981
#define mmHUBPREQ4_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C_BASE_IDX 2
#define mmHUBPREQ4_DCSURF_PRIMARY_META_SURFACE_ADDRESS 0x0982
#define mmHUBPREQ4_DCSURF_PRIMARY_META_SURFACE_ADDRESS_BASE_IDX 2
#define mmHUBPREQ4_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH 0x0983
#define mmHUBPREQ4_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_BASE_IDX 2
#define mmHUBPREQ4_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C 0x0984
#define mmHUBPREQ4_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C_BASE_IDX 2
#define mmHUBPREQ4_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C 0x0985
#define mmHUBPREQ4_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C_BASE_IDX 2
#define mmHUBPREQ4_DCSURF_SECONDARY_META_SURFACE_ADDRESS 0x0986
#define mmHUBPREQ4_DCSURF_SECONDARY_META_SURFACE_ADDRESS_BASE_IDX 2
#define mmHUBPREQ4_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH 0x0987
#define mmHUBPREQ4_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_BASE_IDX 2
#define mmHUBPREQ4_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C 0x0988
#define mmHUBPREQ4_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C_BASE_IDX 2
#define mmHUBPREQ4_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C 0x0989
#define your_sha256_hash 2
#define mmHUBPREQ4_DCSURF_SURFACE_CONTROL 0x098a
#define mmHUBPREQ4_DCSURF_SURFACE_CONTROL_BASE_IDX 2
#define mmHUBPREQ4_DCSURF_FLIP_CONTROL 0x098b
#define mmHUBPREQ4_DCSURF_FLIP_CONTROL_BASE_IDX 2
#define mmHUBPREQ4_DCSURF_FLIP_CONTROL2 0x098c
#define mmHUBPREQ4_DCSURF_FLIP_CONTROL2_BASE_IDX 2
#define mmHUBPREQ4_DCSURF_SURFACE_FLIP_INTERRUPT 0x0990
#define mmHUBPREQ4_DCSURF_SURFACE_FLIP_INTERRUPT_BASE_IDX 2
#define mmHUBPREQ4_DCSURF_SURFACE_INUSE 0x0991
#define mmHUBPREQ4_DCSURF_SURFACE_INUSE_BASE_IDX 2
#define mmHUBPREQ4_DCSURF_SURFACE_INUSE_HIGH 0x0992
#define mmHUBPREQ4_DCSURF_SURFACE_INUSE_HIGH_BASE_IDX 2
#define mmHUBPREQ4_DCSURF_SURFACE_INUSE_C 0x0993
#define mmHUBPREQ4_DCSURF_SURFACE_INUSE_C_BASE_IDX 2
#define mmHUBPREQ4_DCSURF_SURFACE_INUSE_HIGH_C 0x0994
#define mmHUBPREQ4_DCSURF_SURFACE_INUSE_HIGH_C_BASE_IDX 2
#define mmHUBPREQ4_DCSURF_SURFACE_EARLIEST_INUSE 0x0995
#define mmHUBPREQ4_DCSURF_SURFACE_EARLIEST_INUSE_BASE_IDX 2
#define mmHUBPREQ4_DCSURF_SURFACE_EARLIEST_INUSE_HIGH 0x0996
#define mmHUBPREQ4_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_BASE_IDX 2
#define mmHUBPREQ4_DCSURF_SURFACE_EARLIEST_INUSE_C 0x0997
#define mmHUBPREQ4_DCSURF_SURFACE_EARLIEST_INUSE_C_BASE_IDX 2
#define mmHUBPREQ4_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C 0x0998
#define mmHUBPREQ4_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C_BASE_IDX 2
#define mmHUBPREQ4_DCN_EXPANSION_MODE 0x0999
#define mmHUBPREQ4_DCN_EXPANSION_MODE_BASE_IDX 2
#define mmHUBPREQ4_DCN_TTU_QOS_WM 0x099a
#define mmHUBPREQ4_DCN_TTU_QOS_WM_BASE_IDX 2
#define mmHUBPREQ4_DCN_GLOBAL_TTU_CNTL 0x099b
#define mmHUBPREQ4_DCN_GLOBAL_TTU_CNTL_BASE_IDX 2
#define mmHUBPREQ4_DCN_SURF0_TTU_CNTL0 0x099c
#define mmHUBPREQ4_DCN_SURF0_TTU_CNTL0_BASE_IDX 2
#define mmHUBPREQ4_DCN_SURF0_TTU_CNTL1 0x099d
#define mmHUBPREQ4_DCN_SURF0_TTU_CNTL1_BASE_IDX 2
#define mmHUBPREQ4_DCN_SURF1_TTU_CNTL0 0x099e
#define mmHUBPREQ4_DCN_SURF1_TTU_CNTL0_BASE_IDX 2
#define mmHUBPREQ4_DCN_SURF1_TTU_CNTL1 0x099f
#define mmHUBPREQ4_DCN_SURF1_TTU_CNTL1_BASE_IDX 2
#define mmHUBPREQ4_DCN_CUR0_TTU_CNTL0 0x09a0
#define mmHUBPREQ4_DCN_CUR0_TTU_CNTL0_BASE_IDX 2
#define mmHUBPREQ4_DCN_CUR0_TTU_CNTL1 0x09a1
#define mmHUBPREQ4_DCN_CUR0_TTU_CNTL1_BASE_IDX 2
#define mmHUBPREQ4_DCN_CUR1_TTU_CNTL0 0x09a2
#define mmHUBPREQ4_DCN_CUR1_TTU_CNTL0_BASE_IDX 2
#define mmHUBPREQ4_DCN_CUR1_TTU_CNTL1 0x09a3
#define mmHUBPREQ4_DCN_CUR1_TTU_CNTL1_BASE_IDX 2
#define mmHUBPREQ4_DCN_DMDATA_VM_CNTL 0x09a4
#define mmHUBPREQ4_DCN_DMDATA_VM_CNTL_BASE_IDX 2
#define mmHUBPREQ4_DCN_VM_SYSTEM_APERTURE_LOW_ADDR 0x09a5
#define mmHUBPREQ4_DCN_VM_SYSTEM_APERTURE_LOW_ADDR_BASE_IDX 2
#define mmHUBPREQ4_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR 0x09a6
#define mmHUBPREQ4_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR_BASE_IDX 2
#define mmHUBPREQ4_DCN_VM_MX_L1_TLB_CNTL 0x09b3
#define mmHUBPREQ4_DCN_VM_MX_L1_TLB_CNTL_BASE_IDX 2
#define mmHUBPREQ4_BLANK_OFFSET_0 0x09b4
#define mmHUBPREQ4_BLANK_OFFSET_0_BASE_IDX 2
#define mmHUBPREQ4_BLANK_OFFSET_1 0x09b5
#define mmHUBPREQ4_BLANK_OFFSET_1_BASE_IDX 2
#define mmHUBPREQ4_DST_DIMENSIONS 0x09b6
#define mmHUBPREQ4_DST_DIMENSIONS_BASE_IDX 2
#define mmHUBPREQ4_DST_AFTER_SCALER 0x09b7
#define mmHUBPREQ4_DST_AFTER_SCALER_BASE_IDX 2
#define mmHUBPREQ4_PREFETCH_SETTINGS 0x09b8
#define mmHUBPREQ4_PREFETCH_SETTINGS_BASE_IDX 2
#define mmHUBPREQ4_PREFETCH_SETTINGS_C 0x09b9
#define mmHUBPREQ4_PREFETCH_SETTINGS_C_BASE_IDX 2
#define mmHUBPREQ4_VBLANK_PARAMETERS_0 0x09ba
#define mmHUBPREQ4_VBLANK_PARAMETERS_0_BASE_IDX 2
#define mmHUBPREQ4_VBLANK_PARAMETERS_1 0x09bb
#define mmHUBPREQ4_VBLANK_PARAMETERS_1_BASE_IDX 2
#define mmHUBPREQ4_VBLANK_PARAMETERS_2 0x09bc
#define mmHUBPREQ4_VBLANK_PARAMETERS_2_BASE_IDX 2
#define mmHUBPREQ4_VBLANK_PARAMETERS_3 0x09bd
#define mmHUBPREQ4_VBLANK_PARAMETERS_3_BASE_IDX 2
#define mmHUBPREQ4_VBLANK_PARAMETERS_4 0x09be
#define mmHUBPREQ4_VBLANK_PARAMETERS_4_BASE_IDX 2
#define mmHUBPREQ4_FLIP_PARAMETERS_0 0x09bf
#define mmHUBPREQ4_FLIP_PARAMETERS_0_BASE_IDX 2
#define mmHUBPREQ4_FLIP_PARAMETERS_1 0x09c0
#define mmHUBPREQ4_FLIP_PARAMETERS_1_BASE_IDX 2
#define mmHUBPREQ4_FLIP_PARAMETERS_2 0x09c1
#define mmHUBPREQ4_FLIP_PARAMETERS_2_BASE_IDX 2
#define mmHUBPREQ4_NOM_PARAMETERS_0 0x09c2
#define mmHUBPREQ4_NOM_PARAMETERS_0_BASE_IDX 2
#define mmHUBPREQ4_NOM_PARAMETERS_1 0x09c3
#define mmHUBPREQ4_NOM_PARAMETERS_1_BASE_IDX 2
#define mmHUBPREQ4_NOM_PARAMETERS_2 0x09c4
#define mmHUBPREQ4_NOM_PARAMETERS_2_BASE_IDX 2
#define mmHUBPREQ4_NOM_PARAMETERS_3 0x09c5
#define mmHUBPREQ4_NOM_PARAMETERS_3_BASE_IDX 2
#define mmHUBPREQ4_NOM_PARAMETERS_4 0x09c6
#define mmHUBPREQ4_NOM_PARAMETERS_4_BASE_IDX 2
#define mmHUBPREQ4_NOM_PARAMETERS_5 0x09c7
#define mmHUBPREQ4_NOM_PARAMETERS_5_BASE_IDX 2
#define mmHUBPREQ4_NOM_PARAMETERS_6 0x09c8
#define mmHUBPREQ4_NOM_PARAMETERS_6_BASE_IDX 2
#define mmHUBPREQ4_NOM_PARAMETERS_7 0x09c9
#define mmHUBPREQ4_NOM_PARAMETERS_7_BASE_IDX 2
#define mmHUBPREQ4_PER_LINE_DELIVERY_PRE 0x09ca
#define mmHUBPREQ4_PER_LINE_DELIVERY_PRE_BASE_IDX 2
#define mmHUBPREQ4_PER_LINE_DELIVERY 0x09cb
#define mmHUBPREQ4_PER_LINE_DELIVERY_BASE_IDX 2
#define mmHUBPREQ4_CURSOR_SETTINGS 0x09cc
#define mmHUBPREQ4_CURSOR_SETTINGS_BASE_IDX 2
#define mmHUBPREQ4_REF_FREQ_TO_PIX_FREQ 0x09cd
#define mmHUBPREQ4_REF_FREQ_TO_PIX_FREQ_BASE_IDX 2
#define mmHUBPREQ4_DST_Y_DELTA_DRQ_LIMIT 0x09ce
#define mmHUBPREQ4_DST_Y_DELTA_DRQ_LIMIT_BASE_IDX 2
#define mmHUBPREQ4_HUBPREQ_MEM_PWR_CTRL 0x09cf
#define mmHUBPREQ4_HUBPREQ_MEM_PWR_CTRL_BASE_IDX 2
#define mmHUBPREQ4_HUBPREQ_MEM_PWR_STATUS 0x09d0
#define mmHUBPREQ4_HUBPREQ_MEM_PWR_STATUS_BASE_IDX 2
#define mmHUBPREQ4_VBLANK_PARAMETERS_5 0x09d3
#define mmHUBPREQ4_VBLANK_PARAMETERS_5_BASE_IDX 2
#define mmHUBPREQ4_VBLANK_PARAMETERS_6 0x09d4
#define mmHUBPREQ4_VBLANK_PARAMETERS_6_BASE_IDX 2
#define mmHUBPREQ4_FLIP_PARAMETERS_3 0x09d5
#define mmHUBPREQ4_FLIP_PARAMETERS_3_BASE_IDX 2
#define mmHUBPREQ4_FLIP_PARAMETERS_4 0x09d6
#define mmHUBPREQ4_FLIP_PARAMETERS_4_BASE_IDX 2
#define mmHUBPREQ4_FLIP_PARAMETERS_5 0x09d7
#define mmHUBPREQ4_FLIP_PARAMETERS_5_BASE_IDX 2
#define mmHUBPREQ4_FLIP_PARAMETERS_6 0x09d8
#define mmHUBPREQ4_FLIP_PARAMETERS_6_BASE_IDX 2
// addressBlock: dce_dc_dcbubp4_dispdec_hubpret_dispdec
// base address: 0xdc0
#define mmHUBPRET4_HUBPRET_CONTROL 0x09dc
#define mmHUBPRET4_HUBPRET_CONTROL_BASE_IDX 2
#define mmHUBPRET4_HUBPRET_MEM_PWR_CTRL 0x09dd
#define mmHUBPRET4_HUBPRET_MEM_PWR_CTRL_BASE_IDX 2
#define mmHUBPRET4_HUBPRET_MEM_PWR_STATUS 0x09de
#define mmHUBPRET4_HUBPRET_MEM_PWR_STATUS_BASE_IDX 2
#define mmHUBPRET4_HUBPRET_READ_LINE_CTRL0 0x09df
#define mmHUBPRET4_HUBPRET_READ_LINE_CTRL0_BASE_IDX 2
#define mmHUBPRET4_HUBPRET_READ_LINE_CTRL1 0x09e0
#define mmHUBPRET4_HUBPRET_READ_LINE_CTRL1_BASE_IDX 2
#define mmHUBPRET4_HUBPRET_READ_LINE0 0x09e1
#define mmHUBPRET4_HUBPRET_READ_LINE0_BASE_IDX 2
#define mmHUBPRET4_HUBPRET_READ_LINE1 0x09e2
#define mmHUBPRET4_HUBPRET_READ_LINE1_BASE_IDX 2
#define mmHUBPRET4_HUBPRET_INTERRUPT 0x09e3
#define mmHUBPRET4_HUBPRET_INTERRUPT_BASE_IDX 2
#define mmHUBPRET4_HUBPRET_READ_LINE_VALUE 0x09e4
#define mmHUBPRET4_HUBPRET_READ_LINE_VALUE_BASE_IDX 2
#define mmHUBPRET4_HUBPRET_READ_LINE_STATUS 0x09e5
#define mmHUBPRET4_HUBPRET_READ_LINE_STATUS_BASE_IDX 2
// addressBlock: dce_dc_dcbubp4_dispdec_cursor0_dispdec
// base address: 0xdc0
#define mmCURSOR0_4_CURSOR_CONTROL 0x09e8
#define mmCURSOR0_4_CURSOR_CONTROL_BASE_IDX 2
#define mmCURSOR0_4_CURSOR_SURFACE_ADDRESS 0x09e9
#define mmCURSOR0_4_CURSOR_SURFACE_ADDRESS_BASE_IDX 2
#define mmCURSOR0_4_CURSOR_SURFACE_ADDRESS_HIGH 0x09ea
#define mmCURSOR0_4_CURSOR_SURFACE_ADDRESS_HIGH_BASE_IDX 2
#define mmCURSOR0_4_CURSOR_SIZE 0x09eb
#define mmCURSOR0_4_CURSOR_SIZE_BASE_IDX 2
#define mmCURSOR0_4_CURSOR_POSITION 0x09ec
#define mmCURSOR0_4_CURSOR_POSITION_BASE_IDX 2
#define mmCURSOR0_4_CURSOR_HOT_SPOT 0x09ed
#define mmCURSOR0_4_CURSOR_HOT_SPOT_BASE_IDX 2
#define mmCURSOR0_4_CURSOR_STEREO_CONTROL 0x09ee
#define mmCURSOR0_4_CURSOR_STEREO_CONTROL_BASE_IDX 2
#define mmCURSOR0_4_CURSOR_DST_OFFSET 0x09ef
#define mmCURSOR0_4_CURSOR_DST_OFFSET_BASE_IDX 2
#define mmCURSOR0_4_CURSOR_MEM_PWR_CTRL 0x09f0
#define mmCURSOR0_4_CURSOR_MEM_PWR_CTRL_BASE_IDX 2
#define mmCURSOR0_4_CURSOR_MEM_PWR_STATUS 0x09f1
#define mmCURSOR0_4_CURSOR_MEM_PWR_STATUS_BASE_IDX 2
#define mmCURSOR0_4_DMDATA_ADDRESS_HIGH 0x09f2
#define mmCURSOR0_4_DMDATA_ADDRESS_HIGH_BASE_IDX 2
#define mmCURSOR0_4_DMDATA_ADDRESS_LOW 0x09f3
#define mmCURSOR0_4_DMDATA_ADDRESS_LOW_BASE_IDX 2
#define mmCURSOR0_4_DMDATA_CNTL 0x09f4
#define mmCURSOR0_4_DMDATA_CNTL_BASE_IDX 2
#define mmCURSOR0_4_DMDATA_QOS_CNTL 0x09f5
#define mmCURSOR0_4_DMDATA_QOS_CNTL_BASE_IDX 2
#define mmCURSOR0_4_DMDATA_STATUS 0x09f6
#define mmCURSOR0_4_DMDATA_STATUS_BASE_IDX 2
#define mmCURSOR0_4_DMDATA_SW_CNTL 0x09f7
#define mmCURSOR0_4_DMDATA_SW_CNTL_BASE_IDX 2
#define mmCURSOR0_4_DMDATA_SW_DATA 0x09f8
#define mmCURSOR0_4_DMDATA_SW_DATA_BASE_IDX 2
// addressBlock: dce_dc_dcbubp4_dispdec_hubp_dcperfmon_dc_perfmon_dispdec
// base address: 0x2834
#define mmDC_PERFMON10_PERFCOUNTER_CNTL 0x0a0d
#define mmDC_PERFMON10_PERFCOUNTER_CNTL_BASE_IDX 2
#define mmDC_PERFMON10_PERFCOUNTER_CNTL2 0x0a0e
#define mmDC_PERFMON10_PERFCOUNTER_CNTL2_BASE_IDX 2
#define mmDC_PERFMON10_PERFCOUNTER_STATE 0x0a0f
#define mmDC_PERFMON10_PERFCOUNTER_STATE_BASE_IDX 2
#define mmDC_PERFMON10_PERFMON_CNTL 0x0a10
#define mmDC_PERFMON10_PERFMON_CNTL_BASE_IDX 2
#define mmDC_PERFMON10_PERFMON_CNTL2 0x0a11
#define mmDC_PERFMON10_PERFMON_CNTL2_BASE_IDX 2
#define mmDC_PERFMON10_PERFMON_CVALUE_INT_MISC 0x0a12
#define mmDC_PERFMON10_PERFMON_CVALUE_INT_MISC_BASE_IDX 2
#define mmDC_PERFMON10_PERFMON_CVALUE_LOW 0x0a13
#define mmDC_PERFMON10_PERFMON_CVALUE_LOW_BASE_IDX 2
#define mmDC_PERFMON10_PERFMON_HI 0x0a14
#define mmDC_PERFMON10_PERFMON_HI_BASE_IDX 2
#define mmDC_PERFMON10_PERFMON_LOW 0x0a15
#define mmDC_PERFMON10_PERFMON_LOW_BASE_IDX 2
// addressBlock: dce_dc_dcbubp5_dispdec_hubp_dispdec
// base address: 0x1130
#define mmHUBP5_DCSURF_SURFACE_CONFIG 0x0a31
#define mmHUBP5_DCSURF_SURFACE_CONFIG_BASE_IDX 2
#define mmHUBP5_DCSURF_ADDR_CONFIG 0x0a32
#define mmHUBP5_DCSURF_ADDR_CONFIG_BASE_IDX 2
#define mmHUBP5_DCSURF_TILING_CONFIG 0x0a33
#define mmHUBP5_DCSURF_TILING_CONFIG_BASE_IDX 2
#define mmHUBP5_DCSURF_PRI_VIEWPORT_START 0x0a35
#define mmHUBP5_DCSURF_PRI_VIEWPORT_START_BASE_IDX 2
#define mmHUBP5_DCSURF_PRI_VIEWPORT_DIMENSION 0x0a36
#define mmHUBP5_DCSURF_PRI_VIEWPORT_DIMENSION_BASE_IDX 2
#define mmHUBP5_DCSURF_PRI_VIEWPORT_START_C 0x0a37
#define mmHUBP5_DCSURF_PRI_VIEWPORT_START_C_BASE_IDX 2
#define mmHUBP5_DCSURF_PRI_VIEWPORT_DIMENSION_C 0x0a38
#define mmHUBP5_DCSURF_PRI_VIEWPORT_DIMENSION_C_BASE_IDX 2
#define mmHUBP5_DCSURF_SEC_VIEWPORT_START 0x0a39
#define mmHUBP5_DCSURF_SEC_VIEWPORT_START_BASE_IDX 2
#define mmHUBP5_DCSURF_SEC_VIEWPORT_DIMENSION 0x0a3a
#define mmHUBP5_DCSURF_SEC_VIEWPORT_DIMENSION_BASE_IDX 2
#define mmHUBP5_DCSURF_SEC_VIEWPORT_START_C 0x0a3b
#define mmHUBP5_DCSURF_SEC_VIEWPORT_START_C_BASE_IDX 2
#define mmHUBP5_DCSURF_SEC_VIEWPORT_DIMENSION_C 0x0a3c
#define mmHUBP5_DCSURF_SEC_VIEWPORT_DIMENSION_C_BASE_IDX 2
#define mmHUBP5_DCHUBP_REQ_SIZE_CONFIG 0x0a3d
#define mmHUBP5_DCHUBP_REQ_SIZE_CONFIG_BASE_IDX 2
#define mmHUBP5_DCHUBP_REQ_SIZE_CONFIG_C 0x0a3e
#define mmHUBP5_DCHUBP_REQ_SIZE_CONFIG_C_BASE_IDX 2
#define mmHUBP5_DCHUBP_CNTL 0x0a3f
#define mmHUBP5_DCHUBP_CNTL_BASE_IDX 2
#define mmHUBP5_HUBP_CLK_CNTL 0x0a40
#define mmHUBP5_HUBP_CLK_CNTL_BASE_IDX 2
#define mmHUBP5_DCHUBP_VMPG_CONFIG 0x0a41
#define mmHUBP5_DCHUBP_VMPG_CONFIG_BASE_IDX 2
#define mmHUBP5_HUBPREQ_DEBUG_DB 0x0a42
#define mmHUBP5_HUBPREQ_DEBUG_DB_BASE_IDX 2
#define mmHUBP5_HUBPREQ_DEBUG 0x0a43
#define mmHUBP5_HUBPREQ_DEBUG_BASE_IDX 2
#define mmHUBP5_HUBP_MEASURE_WIN_CTRL_DCFCLK 0x0a47
#define mmHUBP5_HUBP_MEASURE_WIN_CTRL_DCFCLK_BASE_IDX 2
#define mmHUBP5_HUBP_MEASURE_WIN_CTRL_DPPCLK 0x0a48
#define mmHUBP5_HUBP_MEASURE_WIN_CTRL_DPPCLK_BASE_IDX 2
// addressBlock: dce_dc_dcbubp5_dispdec_hubpreq_dispdec
// base address: 0x1130
#define mmHUBPREQ5_DCSURF_SURFACE_PITCH 0x0a53
#define mmHUBPREQ5_DCSURF_SURFACE_PITCH_BASE_IDX 2
#define mmHUBPREQ5_DCSURF_SURFACE_PITCH_C 0x0a54
#define mmHUBPREQ5_DCSURF_SURFACE_PITCH_C_BASE_IDX 2
#define mmHUBPREQ5_VMID_SETTINGS_0 0x0a55
#define mmHUBPREQ5_VMID_SETTINGS_0_BASE_IDX 2
#define mmHUBPREQ5_DCSURF_PRIMARY_SURFACE_ADDRESS 0x0a56
#define mmHUBPREQ5_DCSURF_PRIMARY_SURFACE_ADDRESS_BASE_IDX 2
#define mmHUBPREQ5_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH 0x0a57
#define mmHUBPREQ5_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_BASE_IDX 2
#define mmHUBPREQ5_DCSURF_PRIMARY_SURFACE_ADDRESS_C 0x0a58
#define mmHUBPREQ5_DCSURF_PRIMARY_SURFACE_ADDRESS_C_BASE_IDX 2
#define mmHUBPREQ5_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C 0x0a59
#define mmHUBPREQ5_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C_BASE_IDX 2
#define mmHUBPREQ5_DCSURF_SECONDARY_SURFACE_ADDRESS 0x0a5a
#define mmHUBPREQ5_DCSURF_SECONDARY_SURFACE_ADDRESS_BASE_IDX 2
#define mmHUBPREQ5_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH 0x0a5b
#define mmHUBPREQ5_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_BASE_IDX 2
#define mmHUBPREQ5_DCSURF_SECONDARY_SURFACE_ADDRESS_C 0x0a5c
#define mmHUBPREQ5_DCSURF_SECONDARY_SURFACE_ADDRESS_C_BASE_IDX 2
#define mmHUBPREQ5_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C 0x0a5d
#define mmHUBPREQ5_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C_BASE_IDX 2
#define mmHUBPREQ5_DCSURF_PRIMARY_META_SURFACE_ADDRESS 0x0a5e
#define mmHUBPREQ5_DCSURF_PRIMARY_META_SURFACE_ADDRESS_BASE_IDX 2
#define mmHUBPREQ5_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH 0x0a5f
#define mmHUBPREQ5_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_BASE_IDX 2
#define mmHUBPREQ5_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C 0x0a60
#define mmHUBPREQ5_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C_BASE_IDX 2
#define mmHUBPREQ5_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C 0x0a61
#define mmHUBPREQ5_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C_BASE_IDX 2
#define mmHUBPREQ5_DCSURF_SECONDARY_META_SURFACE_ADDRESS 0x0a62
#define mmHUBPREQ5_DCSURF_SECONDARY_META_SURFACE_ADDRESS_BASE_IDX 2
#define mmHUBPREQ5_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH 0x0a63
#define mmHUBPREQ5_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_BASE_IDX 2
#define mmHUBPREQ5_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C 0x0a64
#define mmHUBPREQ5_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C_BASE_IDX 2
#define mmHUBPREQ5_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C 0x0a65
#define your_sha256_hash 2
#define mmHUBPREQ5_DCSURF_SURFACE_CONTROL 0x0a66
#define mmHUBPREQ5_DCSURF_SURFACE_CONTROL_BASE_IDX 2
#define mmHUBPREQ5_DCSURF_FLIP_CONTROL 0x0a67
#define mmHUBPREQ5_DCSURF_FLIP_CONTROL_BASE_IDX 2
#define mmHUBPREQ5_DCSURF_FLIP_CONTROL2 0x0a68
#define mmHUBPREQ5_DCSURF_FLIP_CONTROL2_BASE_IDX 2
#define mmHUBPREQ5_DCSURF_SURFACE_FLIP_INTERRUPT 0x0a6c
#define mmHUBPREQ5_DCSURF_SURFACE_FLIP_INTERRUPT_BASE_IDX 2
#define mmHUBPREQ5_DCSURF_SURFACE_INUSE 0x0a6d
#define mmHUBPREQ5_DCSURF_SURFACE_INUSE_BASE_IDX 2
#define mmHUBPREQ5_DCSURF_SURFACE_INUSE_HIGH 0x0a6e
#define mmHUBPREQ5_DCSURF_SURFACE_INUSE_HIGH_BASE_IDX 2
#define mmHUBPREQ5_DCSURF_SURFACE_INUSE_C 0x0a6f
#define mmHUBPREQ5_DCSURF_SURFACE_INUSE_C_BASE_IDX 2
#define mmHUBPREQ5_DCSURF_SURFACE_INUSE_HIGH_C 0x0a70
#define mmHUBPREQ5_DCSURF_SURFACE_INUSE_HIGH_C_BASE_IDX 2
#define mmHUBPREQ5_DCSURF_SURFACE_EARLIEST_INUSE 0x0a71
#define mmHUBPREQ5_DCSURF_SURFACE_EARLIEST_INUSE_BASE_IDX 2
#define mmHUBPREQ5_DCSURF_SURFACE_EARLIEST_INUSE_HIGH 0x0a72
#define mmHUBPREQ5_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_BASE_IDX 2
#define mmHUBPREQ5_DCSURF_SURFACE_EARLIEST_INUSE_C 0x0a73
#define mmHUBPREQ5_DCSURF_SURFACE_EARLIEST_INUSE_C_BASE_IDX 2
#define mmHUBPREQ5_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C 0x0a74
#define mmHUBPREQ5_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C_BASE_IDX 2
#define mmHUBPREQ5_DCN_EXPANSION_MODE 0x0a75
#define mmHUBPREQ5_DCN_EXPANSION_MODE_BASE_IDX 2
#define mmHUBPREQ5_DCN_TTU_QOS_WM 0x0a76
#define mmHUBPREQ5_DCN_TTU_QOS_WM_BASE_IDX 2
#define mmHUBPREQ5_DCN_GLOBAL_TTU_CNTL 0x0a77
#define mmHUBPREQ5_DCN_GLOBAL_TTU_CNTL_BASE_IDX 2
#define mmHUBPREQ5_DCN_SURF0_TTU_CNTL0 0x0a78
#define mmHUBPREQ5_DCN_SURF0_TTU_CNTL0_BASE_IDX 2
#define mmHUBPREQ5_DCN_SURF0_TTU_CNTL1 0x0a79
#define mmHUBPREQ5_DCN_SURF0_TTU_CNTL1_BASE_IDX 2
#define mmHUBPREQ5_DCN_SURF1_TTU_CNTL0 0x0a7a
#define mmHUBPREQ5_DCN_SURF1_TTU_CNTL0_BASE_IDX 2
#define mmHUBPREQ5_DCN_SURF1_TTU_CNTL1 0x0a7b
#define mmHUBPREQ5_DCN_SURF1_TTU_CNTL1_BASE_IDX 2
#define mmHUBPREQ5_DCN_CUR0_TTU_CNTL0 0x0a7c
#define mmHUBPREQ5_DCN_CUR0_TTU_CNTL0_BASE_IDX 2
#define mmHUBPREQ5_DCN_CUR0_TTU_CNTL1 0x0a7d
#define mmHUBPREQ5_DCN_CUR0_TTU_CNTL1_BASE_IDX 2
#define mmHUBPREQ5_DCN_CUR1_TTU_CNTL0 0x0a7e
#define mmHUBPREQ5_DCN_CUR1_TTU_CNTL0_BASE_IDX 2
#define mmHUBPREQ5_DCN_CUR1_TTU_CNTL1 0x0a7f
#define mmHUBPREQ5_DCN_CUR1_TTU_CNTL1_BASE_IDX 2
#define mmHUBPREQ5_DCN_DMDATA_VM_CNTL 0x0a80
#define mmHUBPREQ5_DCN_DMDATA_VM_CNTL_BASE_IDX 2
#define mmHUBPREQ5_DCN_VM_SYSTEM_APERTURE_LOW_ADDR 0x0a81
#define mmHUBPREQ5_DCN_VM_SYSTEM_APERTURE_LOW_ADDR_BASE_IDX 2
#define mmHUBPREQ5_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR 0x0a82
#define mmHUBPREQ5_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR_BASE_IDX 2
#define mmHUBPREQ5_DCN_VM_MX_L1_TLB_CNTL 0x0a8f
#define mmHUBPREQ5_DCN_VM_MX_L1_TLB_CNTL_BASE_IDX 2
#define mmHUBPREQ5_BLANK_OFFSET_0 0x0a90
#define mmHUBPREQ5_BLANK_OFFSET_0_BASE_IDX 2
#define mmHUBPREQ5_BLANK_OFFSET_1 0x0a91
#define mmHUBPREQ5_BLANK_OFFSET_1_BASE_IDX 2
#define mmHUBPREQ5_DST_DIMENSIONS 0x0a92
#define mmHUBPREQ5_DST_DIMENSIONS_BASE_IDX 2
#define mmHUBPREQ5_DST_AFTER_SCALER 0x0a93
#define mmHUBPREQ5_DST_AFTER_SCALER_BASE_IDX 2
#define mmHUBPREQ5_PREFETCH_SETTINGS 0x0a94
#define mmHUBPREQ5_PREFETCH_SETTINGS_BASE_IDX 2
#define mmHUBPREQ5_PREFETCH_SETTINGS_C 0x0a95
#define mmHUBPREQ5_PREFETCH_SETTINGS_C_BASE_IDX 2
#define mmHUBPREQ5_VBLANK_PARAMETERS_0 0x0a96
#define mmHUBPREQ5_VBLANK_PARAMETERS_0_BASE_IDX 2
#define mmHUBPREQ5_VBLANK_PARAMETERS_1 0x0a97
#define mmHUBPREQ5_VBLANK_PARAMETERS_1_BASE_IDX 2
#define mmHUBPREQ5_VBLANK_PARAMETERS_2 0x0a98
#define mmHUBPREQ5_VBLANK_PARAMETERS_2_BASE_IDX 2
#define mmHUBPREQ5_VBLANK_PARAMETERS_3 0x0a99
#define mmHUBPREQ5_VBLANK_PARAMETERS_3_BASE_IDX 2
#define mmHUBPREQ5_VBLANK_PARAMETERS_4 0x0a9a
#define mmHUBPREQ5_VBLANK_PARAMETERS_4_BASE_IDX 2
#define mmHUBPREQ5_FLIP_PARAMETERS_0 0x0a9b
#define mmHUBPREQ5_FLIP_PARAMETERS_0_BASE_IDX 2
#define mmHUBPREQ5_FLIP_PARAMETERS_1 0x0a9c
#define mmHUBPREQ5_FLIP_PARAMETERS_1_BASE_IDX 2
#define mmHUBPREQ5_FLIP_PARAMETERS_2 0x0a9d
#define mmHUBPREQ5_FLIP_PARAMETERS_2_BASE_IDX 2
#define mmHUBPREQ5_NOM_PARAMETERS_0 0x0a9e
#define mmHUBPREQ5_NOM_PARAMETERS_0_BASE_IDX 2
#define mmHUBPREQ5_NOM_PARAMETERS_1 0x0a9f
#define mmHUBPREQ5_NOM_PARAMETERS_1_BASE_IDX 2
#define mmHUBPREQ5_NOM_PARAMETERS_2 0x0aa0
#define mmHUBPREQ5_NOM_PARAMETERS_2_BASE_IDX 2
#define mmHUBPREQ5_NOM_PARAMETERS_3 0x0aa1
#define mmHUBPREQ5_NOM_PARAMETERS_3_BASE_IDX 2
#define mmHUBPREQ5_NOM_PARAMETERS_4 0x0aa2
#define mmHUBPREQ5_NOM_PARAMETERS_4_BASE_IDX 2
#define mmHUBPREQ5_NOM_PARAMETERS_5 0x0aa3
#define mmHUBPREQ5_NOM_PARAMETERS_5_BASE_IDX 2
#define mmHUBPREQ5_NOM_PARAMETERS_6 0x0aa4
#define mmHUBPREQ5_NOM_PARAMETERS_6_BASE_IDX 2
#define mmHUBPREQ5_NOM_PARAMETERS_7 0x0aa5
#define mmHUBPREQ5_NOM_PARAMETERS_7_BASE_IDX 2
#define mmHUBPREQ5_PER_LINE_DELIVERY_PRE 0x0aa6
#define mmHUBPREQ5_PER_LINE_DELIVERY_PRE_BASE_IDX 2
#define mmHUBPREQ5_PER_LINE_DELIVERY 0x0aa7
#define mmHUBPREQ5_PER_LINE_DELIVERY_BASE_IDX 2
#define mmHUBPREQ5_CURSOR_SETTINGS 0x0aa8
#define mmHUBPREQ5_CURSOR_SETTINGS_BASE_IDX 2
#define mmHUBPREQ5_REF_FREQ_TO_PIX_FREQ 0x0aa9
#define mmHUBPREQ5_REF_FREQ_TO_PIX_FREQ_BASE_IDX 2
#define mmHUBPREQ5_DST_Y_DELTA_DRQ_LIMIT 0x0aaa
#define mmHUBPREQ5_DST_Y_DELTA_DRQ_LIMIT_BASE_IDX 2
#define mmHUBPREQ5_HUBPREQ_MEM_PWR_CTRL 0x0aab
#define mmHUBPREQ5_HUBPREQ_MEM_PWR_CTRL_BASE_IDX 2
#define mmHUBPREQ5_HUBPREQ_MEM_PWR_STATUS 0x0aac
#define mmHUBPREQ5_HUBPREQ_MEM_PWR_STATUS_BASE_IDX 2
#define mmHUBPREQ5_VBLANK_PARAMETERS_5 0x0aaf
#define mmHUBPREQ5_VBLANK_PARAMETERS_5_BASE_IDX 2
#define mmHUBPREQ5_VBLANK_PARAMETERS_6 0x0ab0
#define mmHUBPREQ5_VBLANK_PARAMETERS_6_BASE_IDX 2
#define mmHUBPREQ5_FLIP_PARAMETERS_3 0x0ab1
#define mmHUBPREQ5_FLIP_PARAMETERS_3_BASE_IDX 2
#define mmHUBPREQ5_FLIP_PARAMETERS_4 0x0ab2
#define mmHUBPREQ5_FLIP_PARAMETERS_4_BASE_IDX 2
#define mmHUBPREQ5_FLIP_PARAMETERS_5 0x0ab3
#define mmHUBPREQ5_FLIP_PARAMETERS_5_BASE_IDX 2
#define mmHUBPREQ5_FLIP_PARAMETERS_6 0x0ab4
#define mmHUBPREQ5_FLIP_PARAMETERS_6_BASE_IDX 2
// addressBlock: dce_dc_dcbubp5_dispdec_hubpret_dispdec
// base address: 0x1130
#define mmHUBPRET5_HUBPRET_CONTROL 0x0ab8
#define mmHUBPRET5_HUBPRET_CONTROL_BASE_IDX 2
#define mmHUBPRET5_HUBPRET_MEM_PWR_CTRL 0x0ab9
#define mmHUBPRET5_HUBPRET_MEM_PWR_CTRL_BASE_IDX 2
#define mmHUBPRET5_HUBPRET_MEM_PWR_STATUS 0x0aba
#define mmHUBPRET5_HUBPRET_MEM_PWR_STATUS_BASE_IDX 2
#define mmHUBPRET5_HUBPRET_READ_LINE_CTRL0 0x0abb
#define mmHUBPRET5_HUBPRET_READ_LINE_CTRL0_BASE_IDX 2
#define mmHUBPRET5_HUBPRET_READ_LINE_CTRL1 0x0abc
#define mmHUBPRET5_HUBPRET_READ_LINE_CTRL1_BASE_IDX 2
#define mmHUBPRET5_HUBPRET_READ_LINE0 0x0abd
#define mmHUBPRET5_HUBPRET_READ_LINE0_BASE_IDX 2
#define mmHUBPRET5_HUBPRET_READ_LINE1 0x0abe
#define mmHUBPRET5_HUBPRET_READ_LINE1_BASE_IDX 2
#define mmHUBPRET5_HUBPRET_INTERRUPT 0x0abf
#define mmHUBPRET5_HUBPRET_INTERRUPT_BASE_IDX 2
#define mmHUBPRET5_HUBPRET_READ_LINE_VALUE 0x0ac0
#define mmHUBPRET5_HUBPRET_READ_LINE_VALUE_BASE_IDX 2
#define mmHUBPRET5_HUBPRET_READ_LINE_STATUS 0x0ac1
#define mmHUBPRET5_HUBPRET_READ_LINE_STATUS_BASE_IDX 2
// addressBlock: dce_dc_dcbubp5_dispdec_cursor0_dispdec
// base address: 0x1130
#define mmCURSOR0_5_CURSOR_CONTROL 0x0ac4
#define mmCURSOR0_5_CURSOR_CONTROL_BASE_IDX 2
#define mmCURSOR0_5_CURSOR_SURFACE_ADDRESS 0x0ac5
#define mmCURSOR0_5_CURSOR_SURFACE_ADDRESS_BASE_IDX 2
#define mmCURSOR0_5_CURSOR_SURFACE_ADDRESS_HIGH 0x0ac6
#define mmCURSOR0_5_CURSOR_SURFACE_ADDRESS_HIGH_BASE_IDX 2
#define mmCURSOR0_5_CURSOR_SIZE 0x0ac7
#define mmCURSOR0_5_CURSOR_SIZE_BASE_IDX 2
#define mmCURSOR0_5_CURSOR_POSITION 0x0ac8
#define mmCURSOR0_5_CURSOR_POSITION_BASE_IDX 2
#define mmCURSOR0_5_CURSOR_HOT_SPOT 0x0ac9
#define mmCURSOR0_5_CURSOR_HOT_SPOT_BASE_IDX 2
#define mmCURSOR0_5_CURSOR_STEREO_CONTROL 0x0aca
#define mmCURSOR0_5_CURSOR_STEREO_CONTROL_BASE_IDX 2
#define mmCURSOR0_5_CURSOR_DST_OFFSET 0x0acb
#define mmCURSOR0_5_CURSOR_DST_OFFSET_BASE_IDX 2
#define mmCURSOR0_5_CURSOR_MEM_PWR_CTRL 0x0acc
#define mmCURSOR0_5_CURSOR_MEM_PWR_CTRL_BASE_IDX 2
#define mmCURSOR0_5_CURSOR_MEM_PWR_STATUS 0x0acd
#define mmCURSOR0_5_CURSOR_MEM_PWR_STATUS_BASE_IDX 2
#define mmCURSOR0_5_DMDATA_ADDRESS_HIGH 0x0ace
#define mmCURSOR0_5_DMDATA_ADDRESS_HIGH_BASE_IDX 2
#define mmCURSOR0_5_DMDATA_ADDRESS_LOW 0x0acf
#define mmCURSOR0_5_DMDATA_ADDRESS_LOW_BASE_IDX 2
#define mmCURSOR0_5_DMDATA_CNTL 0x0ad0
#define mmCURSOR0_5_DMDATA_CNTL_BASE_IDX 2
#define mmCURSOR0_5_DMDATA_QOS_CNTL 0x0ad1
#define mmCURSOR0_5_DMDATA_QOS_CNTL_BASE_IDX 2
#define mmCURSOR0_5_DMDATA_STATUS 0x0ad2
#define mmCURSOR0_5_DMDATA_STATUS_BASE_IDX 2
#define mmCURSOR0_5_DMDATA_SW_CNTL 0x0ad3
#define mmCURSOR0_5_DMDATA_SW_CNTL_BASE_IDX 2
#define mmCURSOR0_5_DMDATA_SW_DATA 0x0ad4
#define mmCURSOR0_5_DMDATA_SW_DATA_BASE_IDX 2
// addressBlock: dce_dc_dpp0_dispdec_dpp_top_dispdec
// base address: 0x0
#define mmDPP_TOP0_DPP_CONTROL 0x0cc5
#define mmDPP_TOP0_DPP_CONTROL_BASE_IDX 2
#define mmDPP_TOP0_DPP_SOFT_RESET 0x0cc6
#define mmDPP_TOP0_DPP_SOFT_RESET_BASE_IDX 2
#define mmDPP_TOP0_DPP_CRC_VAL_R_G 0x0cc7
#define mmDPP_TOP0_DPP_CRC_VAL_R_G_BASE_IDX 2
#define mmDPP_TOP0_DPP_CRC_VAL_B_A 0x0cc8
#define mmDPP_TOP0_DPP_CRC_VAL_B_A_BASE_IDX 2
#define mmDPP_TOP0_DPP_CRC_CTRL 0x0cc9
#define mmDPP_TOP0_DPP_CRC_CTRL_BASE_IDX 2
#define mmDPP_TOP0_HOST_READ_CONTROL 0x0cca
#define mmDPP_TOP0_HOST_READ_CONTROL_BASE_IDX 2
// addressBlock: dce_dc_dpp0_dispdec_cnvc_cfg_dispdec
// base address: 0x0
#define mmCNVC_CFG0_CNVC_SURFACE_PIXEL_FORMAT 0x0ccf
#define mmCNVC_CFG0_CNVC_SURFACE_PIXEL_FORMAT_BASE_IDX 2
#define mmCNVC_CFG0_FORMAT_CONTROL 0x0cd0
#define mmCNVC_CFG0_FORMAT_CONTROL_BASE_IDX 2
#define mmCNVC_CFG0_FCNV_FP_BIAS_R 0x0cd1
#define mmCNVC_CFG0_FCNV_FP_BIAS_R_BASE_IDX 2
#define mmCNVC_CFG0_FCNV_FP_BIAS_G 0x0cd2
#define mmCNVC_CFG0_FCNV_FP_BIAS_G_BASE_IDX 2
#define mmCNVC_CFG0_FCNV_FP_BIAS_B 0x0cd3
#define mmCNVC_CFG0_FCNV_FP_BIAS_B_BASE_IDX 2
#define mmCNVC_CFG0_FCNV_FP_SCALE_R 0x0cd4
#define mmCNVC_CFG0_FCNV_FP_SCALE_R_BASE_IDX 2
#define mmCNVC_CFG0_FCNV_FP_SCALE_G 0x0cd5
#define mmCNVC_CFG0_FCNV_FP_SCALE_G_BASE_IDX 2
#define mmCNVC_CFG0_FCNV_FP_SCALE_B 0x0cd6
#define mmCNVC_CFG0_FCNV_FP_SCALE_B_BASE_IDX 2
#define mmCNVC_CFG0_COLOR_KEYER_CONTROL 0x0cd7
#define mmCNVC_CFG0_COLOR_KEYER_CONTROL_BASE_IDX 2
#define mmCNVC_CFG0_COLOR_KEYER_ALPHA 0x0cd8
#define mmCNVC_CFG0_COLOR_KEYER_ALPHA_BASE_IDX 2
#define mmCNVC_CFG0_COLOR_KEYER_RED 0x0cd9
#define mmCNVC_CFG0_COLOR_KEYER_RED_BASE_IDX 2
#define mmCNVC_CFG0_COLOR_KEYER_GREEN 0x0cda
#define mmCNVC_CFG0_COLOR_KEYER_GREEN_BASE_IDX 2
#define mmCNVC_CFG0_COLOR_KEYER_BLUE 0x0cdb
#define mmCNVC_CFG0_COLOR_KEYER_BLUE_BASE_IDX 2
#define mmCNVC_CFG0_ALPHA_2BIT_LUT 0x0cdd
#define mmCNVC_CFG0_ALPHA_2BIT_LUT_BASE_IDX 2
#define mmCNVC_CFG0_PRE_DEALPHA 0x0cde
#define mmCNVC_CFG0_PRE_DEALPHA_BASE_IDX 2
#define mmCNVC_CFG0_PRE_CSC_MODE 0x0cdf
#define mmCNVC_CFG0_PRE_CSC_MODE_BASE_IDX 2
#define mmCNVC_CFG0_PRE_CSC_C11_C12 0x0ce0
#define mmCNVC_CFG0_PRE_CSC_C11_C12_BASE_IDX 2
#define mmCNVC_CFG0_PRE_CSC_C13_C14 0x0ce1
#define mmCNVC_CFG0_PRE_CSC_C13_C14_BASE_IDX 2
#define mmCNVC_CFG0_PRE_CSC_C21_C22 0x0ce2
#define mmCNVC_CFG0_PRE_CSC_C21_C22_BASE_IDX 2
#define mmCNVC_CFG0_PRE_CSC_C23_C24 0x0ce3
#define mmCNVC_CFG0_PRE_CSC_C23_C24_BASE_IDX 2
#define mmCNVC_CFG0_PRE_CSC_C31_C32 0x0ce4
#define mmCNVC_CFG0_PRE_CSC_C31_C32_BASE_IDX 2
#define mmCNVC_CFG0_PRE_CSC_C33_C34 0x0ce5
#define mmCNVC_CFG0_PRE_CSC_C33_C34_BASE_IDX 2
#define mmCNVC_CFG0_PRE_CSC_B_C11_C12 0x0ce6
#define mmCNVC_CFG0_PRE_CSC_B_C11_C12_BASE_IDX 2
#define mmCNVC_CFG0_PRE_CSC_B_C13_C14 0x0ce7
#define mmCNVC_CFG0_PRE_CSC_B_C13_C14_BASE_IDX 2
#define mmCNVC_CFG0_PRE_CSC_B_C21_C22 0x0ce8
#define mmCNVC_CFG0_PRE_CSC_B_C21_C22_BASE_IDX 2
#define mmCNVC_CFG0_PRE_CSC_B_C23_C24 0x0ce9
#define mmCNVC_CFG0_PRE_CSC_B_C23_C24_BASE_IDX 2
#define mmCNVC_CFG0_PRE_CSC_B_C31_C32 0x0cea
#define mmCNVC_CFG0_PRE_CSC_B_C31_C32_BASE_IDX 2
#define mmCNVC_CFG0_PRE_CSC_B_C33_C34 0x0ceb
#define mmCNVC_CFG0_PRE_CSC_B_C33_C34_BASE_IDX 2
#define mmCNVC_CFG0_CNVC_COEF_FORMAT 0x0cec
#define mmCNVC_CFG0_CNVC_COEF_FORMAT_BASE_IDX 2
#define mmCNVC_CFG0_PRE_DEGAM 0x0ced
#define mmCNVC_CFG0_PRE_DEGAM_BASE_IDX 2
#define mmCNVC_CFG0_PRE_REALPHA 0x0cee
#define mmCNVC_CFG0_PRE_REALPHA_BASE_IDX 2
// addressBlock: dce_dc_dpp0_dispdec_cnvc_cur_dispdec
// base address: 0x0
#define mmCNVC_CUR0_CURSOR0_CONTROL 0x0cf1
#define mmCNVC_CUR0_CURSOR0_CONTROL_BASE_IDX 2
#define mmCNVC_CUR0_CURSOR0_COLOR0 0x0cf2
#define mmCNVC_CUR0_CURSOR0_COLOR0_BASE_IDX 2
#define mmCNVC_CUR0_CURSOR0_COLOR1 0x0cf3
#define mmCNVC_CUR0_CURSOR0_COLOR1_BASE_IDX 2
#define mmCNVC_CUR0_CURSOR0_FP_SCALE_BIAS 0x0cf4
#define mmCNVC_CUR0_CURSOR0_FP_SCALE_BIAS_BASE_IDX 2
// addressBlock: dce_dc_dpp0_dispdec_dscl_dispdec
// base address: 0x0
#define mmDSCL0_SCL_COEF_RAM_TAP_SELECT 0x0cf9
#define mmDSCL0_SCL_COEF_RAM_TAP_SELECT_BASE_IDX 2
#define mmDSCL0_SCL_COEF_RAM_TAP_DATA 0x0cfa
#define mmDSCL0_SCL_COEF_RAM_TAP_DATA_BASE_IDX 2
#define mmDSCL0_SCL_MODE 0x0cfb
#define mmDSCL0_SCL_MODE_BASE_IDX 2
#define mmDSCL0_SCL_TAP_CONTROL 0x0cfc
#define mmDSCL0_SCL_TAP_CONTROL_BASE_IDX 2
#define mmDSCL0_DSCL_CONTROL 0x0cfd
#define mmDSCL0_DSCL_CONTROL_BASE_IDX 2
#define mmDSCL0_DSCL_2TAP_CONTROL 0x0cfe
#define mmDSCL0_DSCL_2TAP_CONTROL_BASE_IDX 2
#define mmDSCL0_SCL_MANUAL_REPLICATE_CONTROL 0x0cff
#define mmDSCL0_SCL_MANUAL_REPLICATE_CONTROL_BASE_IDX 2
#define mmDSCL0_SCL_HORZ_FILTER_SCALE_RATIO 0x0d00
#define mmDSCL0_SCL_HORZ_FILTER_SCALE_RATIO_BASE_IDX 2
#define mmDSCL0_SCL_HORZ_FILTER_INIT 0x0d01
#define mmDSCL0_SCL_HORZ_FILTER_INIT_BASE_IDX 2
#define mmDSCL0_SCL_HORZ_FILTER_SCALE_RATIO_C 0x0d02
#define mmDSCL0_SCL_HORZ_FILTER_SCALE_RATIO_C_BASE_IDX 2
#define mmDSCL0_SCL_HORZ_FILTER_INIT_C 0x0d03
#define mmDSCL0_SCL_HORZ_FILTER_INIT_C_BASE_IDX 2
#define mmDSCL0_SCL_VERT_FILTER_SCALE_RATIO 0x0d04
#define mmDSCL0_SCL_VERT_FILTER_SCALE_RATIO_BASE_IDX 2
#define mmDSCL0_SCL_VERT_FILTER_INIT 0x0d05
#define mmDSCL0_SCL_VERT_FILTER_INIT_BASE_IDX 2
#define mmDSCL0_SCL_VERT_FILTER_INIT_BOT 0x0d06
#define mmDSCL0_SCL_VERT_FILTER_INIT_BOT_BASE_IDX 2
#define mmDSCL0_SCL_VERT_FILTER_SCALE_RATIO_C 0x0d07
#define mmDSCL0_SCL_VERT_FILTER_SCALE_RATIO_C_BASE_IDX 2
#define mmDSCL0_SCL_VERT_FILTER_INIT_C 0x0d08
#define mmDSCL0_SCL_VERT_FILTER_INIT_C_BASE_IDX 2
#define mmDSCL0_SCL_VERT_FILTER_INIT_BOT_C 0x0d09
#define mmDSCL0_SCL_VERT_FILTER_INIT_BOT_C_BASE_IDX 2
#define mmDSCL0_SCL_BLACK_COLOR 0x0d0a
#define mmDSCL0_SCL_BLACK_COLOR_BASE_IDX 2
#define mmDSCL0_DSCL_UPDATE 0x0d0b
#define mmDSCL0_DSCL_UPDATE_BASE_IDX 2
#define mmDSCL0_DSCL_AUTOCAL 0x0d0c
#define mmDSCL0_DSCL_AUTOCAL_BASE_IDX 2
#define mmDSCL0_DSCL_EXT_OVERSCAN_LEFT_RIGHT 0x0d0d
#define mmDSCL0_DSCL_EXT_OVERSCAN_LEFT_RIGHT_BASE_IDX 2
#define mmDSCL0_DSCL_EXT_OVERSCAN_TOP_BOTTOM 0x0d0e
#define mmDSCL0_DSCL_EXT_OVERSCAN_TOP_BOTTOM_BASE_IDX 2
#define mmDSCL0_OTG_H_BLANK 0x0d0f
#define mmDSCL0_OTG_H_BLANK_BASE_IDX 2
#define mmDSCL0_OTG_V_BLANK 0x0d10
#define mmDSCL0_OTG_V_BLANK_BASE_IDX 2
#define mmDSCL0_RECOUT_START 0x0d11
#define mmDSCL0_RECOUT_START_BASE_IDX 2
#define mmDSCL0_RECOUT_SIZE 0x0d12
#define mmDSCL0_RECOUT_SIZE_BASE_IDX 2
#define mmDSCL0_MPC_SIZE 0x0d13
#define mmDSCL0_MPC_SIZE_BASE_IDX 2
#define mmDSCL0_LB_DATA_FORMAT 0x0d14
#define mmDSCL0_LB_DATA_FORMAT_BASE_IDX 2
#define mmDSCL0_LB_MEMORY_CTRL 0x0d15
#define mmDSCL0_LB_MEMORY_CTRL_BASE_IDX 2
#define mmDSCL0_LB_V_COUNTER 0x0d16
#define mmDSCL0_LB_V_COUNTER_BASE_IDX 2
#define mmDSCL0_DSCL_MEM_PWR_CTRL 0x0d17
#define mmDSCL0_DSCL_MEM_PWR_CTRL_BASE_IDX 2
#define mmDSCL0_DSCL_MEM_PWR_STATUS 0x0d18
#define mmDSCL0_DSCL_MEM_PWR_STATUS_BASE_IDX 2
#define mmDSCL0_OBUF_CONTROL 0x0d19
#define mmDSCL0_OBUF_CONTROL_BASE_IDX 2
#define mmDSCL0_OBUF_MEM_PWR_CTRL 0x0d1a
#define mmDSCL0_OBUF_MEM_PWR_CTRL_BASE_IDX 2
// addressBlock: dce_dc_dpp0_dispdec_cm_dispdec
// base address: 0x0
#define mmCM0_CM_CONTROL 0x0d20
#define mmCM0_CM_CONTROL_BASE_IDX 2
#define mmCM0_CM_POST_CSC_CONTROL 0x0d21
#define mmCM0_CM_POST_CSC_CONTROL_BASE_IDX 2
#define mmCM0_CM_POST_CSC_C11_C12 0x0d22
#define mmCM0_CM_POST_CSC_C11_C12_BASE_IDX 2
#define mmCM0_CM_POST_CSC_C13_C14 0x0d23
#define mmCM0_CM_POST_CSC_C13_C14_BASE_IDX 2
#define mmCM0_CM_POST_CSC_C21_C22 0x0d24
#define mmCM0_CM_POST_CSC_C21_C22_BASE_IDX 2
#define mmCM0_CM_POST_CSC_C23_C24 0x0d25
#define mmCM0_CM_POST_CSC_C23_C24_BASE_IDX 2
#define mmCM0_CM_POST_CSC_C31_C32 0x0d26
#define mmCM0_CM_POST_CSC_C31_C32_BASE_IDX 2
#define mmCM0_CM_POST_CSC_C33_C34 0x0d27
#define mmCM0_CM_POST_CSC_C33_C34_BASE_IDX 2
#define mmCM0_CM_POST_CSC_B_C11_C12 0x0d28
#define mmCM0_CM_POST_CSC_B_C11_C12_BASE_IDX 2
#define mmCM0_CM_POST_CSC_B_C13_C14 0x0d29
#define mmCM0_CM_POST_CSC_B_C13_C14_BASE_IDX 2
#define mmCM0_CM_POST_CSC_B_C21_C22 0x0d2a
#define mmCM0_CM_POST_CSC_B_C21_C22_BASE_IDX 2
#define mmCM0_CM_POST_CSC_B_C23_C24 0x0d2b
#define mmCM0_CM_POST_CSC_B_C23_C24_BASE_IDX 2
#define mmCM0_CM_POST_CSC_B_C31_C32 0x0d2c
#define mmCM0_CM_POST_CSC_B_C31_C32_BASE_IDX 2
#define mmCM0_CM_POST_CSC_B_C33_C34 0x0d2d
#define mmCM0_CM_POST_CSC_B_C33_C34_BASE_IDX 2
#define mmCM0_CM_GAMUT_REMAP_CONTROL 0x0d2e
#define mmCM0_CM_GAMUT_REMAP_CONTROL_BASE_IDX 2
#define mmCM0_CM_GAMUT_REMAP_C11_C12 0x0d2f
#define mmCM0_CM_GAMUT_REMAP_C11_C12_BASE_IDX 2
#define mmCM0_CM_GAMUT_REMAP_C13_C14 0x0d30
#define mmCM0_CM_GAMUT_REMAP_C13_C14_BASE_IDX 2
#define mmCM0_CM_GAMUT_REMAP_C21_C22 0x0d31
#define mmCM0_CM_GAMUT_REMAP_C21_C22_BASE_IDX 2
#define mmCM0_CM_GAMUT_REMAP_C23_C24 0x0d32
#define mmCM0_CM_GAMUT_REMAP_C23_C24_BASE_IDX 2
#define mmCM0_CM_GAMUT_REMAP_C31_C32 0x0d33
#define mmCM0_CM_GAMUT_REMAP_C31_C32_BASE_IDX 2
#define mmCM0_CM_GAMUT_REMAP_C33_C34 0x0d34
#define mmCM0_CM_GAMUT_REMAP_C33_C34_BASE_IDX 2
#define mmCM0_CM_GAMUT_REMAP_B_C11_C12 0x0d35
#define mmCM0_CM_GAMUT_REMAP_B_C11_C12_BASE_IDX 2
#define mmCM0_CM_GAMUT_REMAP_B_C13_C14 0x0d36
#define mmCM0_CM_GAMUT_REMAP_B_C13_C14_BASE_IDX 2
#define mmCM0_CM_GAMUT_REMAP_B_C21_C22 0x0d37
#define mmCM0_CM_GAMUT_REMAP_B_C21_C22_BASE_IDX 2
#define mmCM0_CM_GAMUT_REMAP_B_C23_C24 0x0d38
#define mmCM0_CM_GAMUT_REMAP_B_C23_C24_BASE_IDX 2
#define mmCM0_CM_GAMUT_REMAP_B_C31_C32 0x0d39
#define mmCM0_CM_GAMUT_REMAP_B_C31_C32_BASE_IDX 2
#define mmCM0_CM_GAMUT_REMAP_B_C33_C34 0x0d3a
#define mmCM0_CM_GAMUT_REMAP_B_C33_C34_BASE_IDX 2
#define mmCM0_CM_BIAS_CR_R 0x0d3b
#define mmCM0_CM_BIAS_CR_R_BASE_IDX 2
#define mmCM0_CM_BIAS_Y_G_CB_B 0x0d3c
#define mmCM0_CM_BIAS_Y_G_CB_B_BASE_IDX 2
#define mmCM0_CM_GAMCOR_CONTROL 0x0d3d
#define mmCM0_CM_GAMCOR_CONTROL_BASE_IDX 2
#define mmCM0_CM_GAMCOR_LUT_INDEX 0x0d3e
#define mmCM0_CM_GAMCOR_LUT_INDEX_BASE_IDX 2
#define mmCM0_CM_GAMCOR_LUT_DATA 0x0d3f
#define mmCM0_CM_GAMCOR_LUT_DATA_BASE_IDX 2
#define mmCM0_CM_GAMCOR_LUT_CONTROL 0x0d40
#define mmCM0_CM_GAMCOR_LUT_CONTROL_BASE_IDX 2
#define mmCM0_CM_GAMCOR_RAMA_START_CNTL_B 0x0d41
#define mmCM0_CM_GAMCOR_RAMA_START_CNTL_B_BASE_IDX 2
#define mmCM0_CM_GAMCOR_RAMA_START_CNTL_G 0x0d42
#define mmCM0_CM_GAMCOR_RAMA_START_CNTL_G_BASE_IDX 2
#define mmCM0_CM_GAMCOR_RAMA_START_CNTL_R 0x0d43
#define mmCM0_CM_GAMCOR_RAMA_START_CNTL_R_BASE_IDX 2
#define mmCM0_CM_GAMCOR_RAMA_START_SLOPE_CNTL_B 0x0d44
#define mmCM0_CM_GAMCOR_RAMA_START_SLOPE_CNTL_B_BASE_IDX 2
#define mmCM0_CM_GAMCOR_RAMA_START_SLOPE_CNTL_G 0x0d45
#define mmCM0_CM_GAMCOR_RAMA_START_SLOPE_CNTL_G_BASE_IDX 2
#define mmCM0_CM_GAMCOR_RAMA_START_SLOPE_CNTL_R 0x0d46
#define mmCM0_CM_GAMCOR_RAMA_START_SLOPE_CNTL_R_BASE_IDX 2
#define mmCM0_CM_GAMCOR_RAMA_START_BASE_CNTL_B 0x0d47
#define mmCM0_CM_GAMCOR_RAMA_START_BASE_CNTL_B_BASE_IDX 2
#define mmCM0_CM_GAMCOR_RAMA_START_BASE_CNTL_G 0x0d48
#define mmCM0_CM_GAMCOR_RAMA_START_BASE_CNTL_G_BASE_IDX 2
#define mmCM0_CM_GAMCOR_RAMA_START_BASE_CNTL_R 0x0d49
#define mmCM0_CM_GAMCOR_RAMA_START_BASE_CNTL_R_BASE_IDX 2
#define mmCM0_CM_GAMCOR_RAMA_END_CNTL1_B 0x0d4a
#define mmCM0_CM_GAMCOR_RAMA_END_CNTL1_B_BASE_IDX 2
#define mmCM0_CM_GAMCOR_RAMA_END_CNTL2_B 0x0d4b
#define mmCM0_CM_GAMCOR_RAMA_END_CNTL2_B_BASE_IDX 2
#define mmCM0_CM_GAMCOR_RAMA_END_CNTL1_G 0x0d4c
#define mmCM0_CM_GAMCOR_RAMA_END_CNTL1_G_BASE_IDX 2
#define mmCM0_CM_GAMCOR_RAMA_END_CNTL2_G 0x0d4d
#define mmCM0_CM_GAMCOR_RAMA_END_CNTL2_G_BASE_IDX 2
#define mmCM0_CM_GAMCOR_RAMA_END_CNTL1_R 0x0d4e
#define mmCM0_CM_GAMCOR_RAMA_END_CNTL1_R_BASE_IDX 2
#define mmCM0_CM_GAMCOR_RAMA_END_CNTL2_R 0x0d4f
#define mmCM0_CM_GAMCOR_RAMA_END_CNTL2_R_BASE_IDX 2
#define mmCM0_CM_GAMCOR_RAMA_OFFSET_B 0x0d50
#define mmCM0_CM_GAMCOR_RAMA_OFFSET_B_BASE_IDX 2
#define mmCM0_CM_GAMCOR_RAMA_OFFSET_G 0x0d51
#define mmCM0_CM_GAMCOR_RAMA_OFFSET_G_BASE_IDX 2
#define mmCM0_CM_GAMCOR_RAMA_OFFSET_R 0x0d52
#define mmCM0_CM_GAMCOR_RAMA_OFFSET_R_BASE_IDX 2
#define mmCM0_CM_GAMCOR_RAMA_REGION_0_1 0x0d53
#define mmCM0_CM_GAMCOR_RAMA_REGION_0_1_BASE_IDX 2
#define mmCM0_CM_GAMCOR_RAMA_REGION_2_3 0x0d54
#define mmCM0_CM_GAMCOR_RAMA_REGION_2_3_BASE_IDX 2
#define mmCM0_CM_GAMCOR_RAMA_REGION_4_5 0x0d55
#define mmCM0_CM_GAMCOR_RAMA_REGION_4_5_BASE_IDX 2
#define mmCM0_CM_GAMCOR_RAMA_REGION_6_7 0x0d56
#define mmCM0_CM_GAMCOR_RAMA_REGION_6_7_BASE_IDX 2
#define mmCM0_CM_GAMCOR_RAMA_REGION_8_9 0x0d57
#define mmCM0_CM_GAMCOR_RAMA_REGION_8_9_BASE_IDX 2
#define mmCM0_CM_GAMCOR_RAMA_REGION_10_11 0x0d58
#define mmCM0_CM_GAMCOR_RAMA_REGION_10_11_BASE_IDX 2
#define mmCM0_CM_GAMCOR_RAMA_REGION_12_13 0x0d59
#define mmCM0_CM_GAMCOR_RAMA_REGION_12_13_BASE_IDX 2
#define mmCM0_CM_GAMCOR_RAMA_REGION_14_15 0x0d5a
#define mmCM0_CM_GAMCOR_RAMA_REGION_14_15_BASE_IDX 2
#define mmCM0_CM_GAMCOR_RAMA_REGION_16_17 0x0d5b
#define mmCM0_CM_GAMCOR_RAMA_REGION_16_17_BASE_IDX 2
#define mmCM0_CM_GAMCOR_RAMA_REGION_18_19 0x0d5c
#define mmCM0_CM_GAMCOR_RAMA_REGION_18_19_BASE_IDX 2
#define mmCM0_CM_GAMCOR_RAMA_REGION_20_21 0x0d5d
#define mmCM0_CM_GAMCOR_RAMA_REGION_20_21_BASE_IDX 2
#define mmCM0_CM_GAMCOR_RAMA_REGION_22_23 0x0d5e
#define mmCM0_CM_GAMCOR_RAMA_REGION_22_23_BASE_IDX 2
#define mmCM0_CM_GAMCOR_RAMA_REGION_24_25 0x0d5f
#define mmCM0_CM_GAMCOR_RAMA_REGION_24_25_BASE_IDX 2
#define mmCM0_CM_GAMCOR_RAMA_REGION_26_27 0x0d60
#define mmCM0_CM_GAMCOR_RAMA_REGION_26_27_BASE_IDX 2
#define mmCM0_CM_GAMCOR_RAMA_REGION_28_29 0x0d61
#define mmCM0_CM_GAMCOR_RAMA_REGION_28_29_BASE_IDX 2
#define mmCM0_CM_GAMCOR_RAMA_REGION_30_31 0x0d62
#define mmCM0_CM_GAMCOR_RAMA_REGION_30_31_BASE_IDX 2
#define mmCM0_CM_GAMCOR_RAMA_REGION_32_33 0x0d63
#define mmCM0_CM_GAMCOR_RAMA_REGION_32_33_BASE_IDX 2
#define mmCM0_CM_GAMCOR_RAMB_START_CNTL_B 0x0d64
#define mmCM0_CM_GAMCOR_RAMB_START_CNTL_B_BASE_IDX 2
#define mmCM0_CM_GAMCOR_RAMB_START_CNTL_G 0x0d65
#define mmCM0_CM_GAMCOR_RAMB_START_CNTL_G_BASE_IDX 2
#define mmCM0_CM_GAMCOR_RAMB_START_CNTL_R 0x0d66
#define mmCM0_CM_GAMCOR_RAMB_START_CNTL_R_BASE_IDX 2
#define mmCM0_CM_GAMCOR_RAMB_START_SLOPE_CNTL_B 0x0d67
#define mmCM0_CM_GAMCOR_RAMB_START_SLOPE_CNTL_B_BASE_IDX 2
#define mmCM0_CM_GAMCOR_RAMB_START_SLOPE_CNTL_G 0x0d68
#define mmCM0_CM_GAMCOR_RAMB_START_SLOPE_CNTL_G_BASE_IDX 2
#define mmCM0_CM_GAMCOR_RAMB_START_SLOPE_CNTL_R 0x0d69
#define mmCM0_CM_GAMCOR_RAMB_START_SLOPE_CNTL_R_BASE_IDX 2
#define mmCM0_CM_GAMCOR_RAMB_START_BASE_CNTL_B 0x0d6a
#define mmCM0_CM_GAMCOR_RAMB_START_BASE_CNTL_B_BASE_IDX 2
#define mmCM0_CM_GAMCOR_RAMB_START_BASE_CNTL_G 0x0d6b
#define mmCM0_CM_GAMCOR_RAMB_START_BASE_CNTL_G_BASE_IDX 2
#define mmCM0_CM_GAMCOR_RAMB_START_BASE_CNTL_R 0x0d6c
#define mmCM0_CM_GAMCOR_RAMB_START_BASE_CNTL_R_BASE_IDX 2
#define mmCM0_CM_GAMCOR_RAMB_END_CNTL1_B 0x0d6d
#define mmCM0_CM_GAMCOR_RAMB_END_CNTL1_B_BASE_IDX 2
#define mmCM0_CM_GAMCOR_RAMB_END_CNTL2_B 0x0d6e
#define mmCM0_CM_GAMCOR_RAMB_END_CNTL2_B_BASE_IDX 2
#define mmCM0_CM_GAMCOR_RAMB_END_CNTL1_G 0x0d6f
#define mmCM0_CM_GAMCOR_RAMB_END_CNTL1_G_BASE_IDX 2
#define mmCM0_CM_GAMCOR_RAMB_END_CNTL2_G 0x0d70
#define mmCM0_CM_GAMCOR_RAMB_END_CNTL2_G_BASE_IDX 2
#define mmCM0_CM_GAMCOR_RAMB_END_CNTL1_R 0x0d71
#define mmCM0_CM_GAMCOR_RAMB_END_CNTL1_R_BASE_IDX 2
#define mmCM0_CM_GAMCOR_RAMB_END_CNTL2_R 0x0d72
#define mmCM0_CM_GAMCOR_RAMB_END_CNTL2_R_BASE_IDX 2
#define mmCM0_CM_GAMCOR_RAMB_OFFSET_B 0x0d73
#define mmCM0_CM_GAMCOR_RAMB_OFFSET_B_BASE_IDX 2
#define mmCM0_CM_GAMCOR_RAMB_OFFSET_G 0x0d74
#define mmCM0_CM_GAMCOR_RAMB_OFFSET_G_BASE_IDX 2
#define mmCM0_CM_GAMCOR_RAMB_OFFSET_R 0x0d75
#define mmCM0_CM_GAMCOR_RAMB_OFFSET_R_BASE_IDX 2
#define mmCM0_CM_GAMCOR_RAMB_REGION_0_1 0x0d76
#define mmCM0_CM_GAMCOR_RAMB_REGION_0_1_BASE_IDX 2
#define mmCM0_CM_GAMCOR_RAMB_REGION_2_3 0x0d77
#define mmCM0_CM_GAMCOR_RAMB_REGION_2_3_BASE_IDX 2
#define mmCM0_CM_GAMCOR_RAMB_REGION_4_5 0x0d78
#define mmCM0_CM_GAMCOR_RAMB_REGION_4_5_BASE_IDX 2
#define mmCM0_CM_GAMCOR_RAMB_REGION_6_7 0x0d79
#define mmCM0_CM_GAMCOR_RAMB_REGION_6_7_BASE_IDX 2
#define mmCM0_CM_GAMCOR_RAMB_REGION_8_9 0x0d7a
#define mmCM0_CM_GAMCOR_RAMB_REGION_8_9_BASE_IDX 2
#define mmCM0_CM_GAMCOR_RAMB_REGION_10_11 0x0d7b
#define mmCM0_CM_GAMCOR_RAMB_REGION_10_11_BASE_IDX 2
#define mmCM0_CM_GAMCOR_RAMB_REGION_12_13 0x0d7c
#define mmCM0_CM_GAMCOR_RAMB_REGION_12_13_BASE_IDX 2
#define mmCM0_CM_GAMCOR_RAMB_REGION_14_15 0x0d7d
#define mmCM0_CM_GAMCOR_RAMB_REGION_14_15_BASE_IDX 2
#define mmCM0_CM_GAMCOR_RAMB_REGION_16_17 0x0d7e
#define mmCM0_CM_GAMCOR_RAMB_REGION_16_17_BASE_IDX 2
#define mmCM0_CM_GAMCOR_RAMB_REGION_18_19 0x0d7f
#define mmCM0_CM_GAMCOR_RAMB_REGION_18_19_BASE_IDX 2
#define mmCM0_CM_GAMCOR_RAMB_REGION_20_21 0x0d80
#define mmCM0_CM_GAMCOR_RAMB_REGION_20_21_BASE_IDX 2
#define mmCM0_CM_GAMCOR_RAMB_REGION_22_23 0x0d81
#define mmCM0_CM_GAMCOR_RAMB_REGION_22_23_BASE_IDX 2
#define mmCM0_CM_GAMCOR_RAMB_REGION_24_25 0x0d82
#define mmCM0_CM_GAMCOR_RAMB_REGION_24_25_BASE_IDX 2
#define mmCM0_CM_GAMCOR_RAMB_REGION_26_27 0x0d83
#define mmCM0_CM_GAMCOR_RAMB_REGION_26_27_BASE_IDX 2
#define mmCM0_CM_GAMCOR_RAMB_REGION_28_29 0x0d84
#define mmCM0_CM_GAMCOR_RAMB_REGION_28_29_BASE_IDX 2
#define mmCM0_CM_GAMCOR_RAMB_REGION_30_31 0x0d85
#define mmCM0_CM_GAMCOR_RAMB_REGION_30_31_BASE_IDX 2
#define mmCM0_CM_GAMCOR_RAMB_REGION_32_33 0x0d86
#define mmCM0_CM_GAMCOR_RAMB_REGION_32_33_BASE_IDX 2
#define mmCM0_CM_BLNDGAM_CONTROL 0x0d87
#define mmCM0_CM_BLNDGAM_CONTROL_BASE_IDX 2
#define mmCM0_CM_BLNDGAM_LUT_INDEX 0x0d88
#define mmCM0_CM_BLNDGAM_LUT_INDEX_BASE_IDX 2
#define mmCM0_CM_BLNDGAM_LUT_DATA 0x0d89
#define mmCM0_CM_BLNDGAM_LUT_DATA_BASE_IDX 2
#define mmCM0_CM_BLNDGAM_LUT_CONTROL 0x0d8a
#define mmCM0_CM_BLNDGAM_LUT_CONTROL_BASE_IDX 2
#define mmCM0_CM_BLNDGAM_RAMA_START_CNTL_B 0x0d8b
#define mmCM0_CM_BLNDGAM_RAMA_START_CNTL_B_BASE_IDX 2
#define mmCM0_CM_BLNDGAM_RAMA_START_CNTL_G 0x0d8c
#define mmCM0_CM_BLNDGAM_RAMA_START_CNTL_G_BASE_IDX 2
#define mmCM0_CM_BLNDGAM_RAMA_START_CNTL_R 0x0d8d
#define mmCM0_CM_BLNDGAM_RAMA_START_CNTL_R_BASE_IDX 2
#define mmCM0_CM_BLNDGAM_RAMA_START_SLOPE_CNTL_B 0x0d8e
#define mmCM0_CM_BLNDGAM_RAMA_START_SLOPE_CNTL_B_BASE_IDX 2
#define mmCM0_CM_BLNDGAM_RAMA_START_SLOPE_CNTL_G 0x0d8f
#define mmCM0_CM_BLNDGAM_RAMA_START_SLOPE_CNTL_G_BASE_IDX 2
#define mmCM0_CM_BLNDGAM_RAMA_START_SLOPE_CNTL_R 0x0d90
#define mmCM0_CM_BLNDGAM_RAMA_START_SLOPE_CNTL_R_BASE_IDX 2
#define mmCM0_CM_BLNDGAM_RAMA_START_BASE_CNTL_B 0x0d91
#define mmCM0_CM_BLNDGAM_RAMA_START_BASE_CNTL_B_BASE_IDX 2
#define mmCM0_CM_BLNDGAM_RAMA_START_BASE_CNTL_G 0x0d92
#define mmCM0_CM_BLNDGAM_RAMA_START_BASE_CNTL_G_BASE_IDX 2
#define mmCM0_CM_BLNDGAM_RAMA_START_BASE_CNTL_R 0x0d93
#define mmCM0_CM_BLNDGAM_RAMA_START_BASE_CNTL_R_BASE_IDX 2
#define mmCM0_CM_BLNDGAM_RAMA_END_CNTL1_B 0x0d94
#define mmCM0_CM_BLNDGAM_RAMA_END_CNTL1_B_BASE_IDX 2
#define mmCM0_CM_BLNDGAM_RAMA_END_CNTL2_B 0x0d95
#define mmCM0_CM_BLNDGAM_RAMA_END_CNTL2_B_BASE_IDX 2
#define mmCM0_CM_BLNDGAM_RAMA_END_CNTL1_G 0x0d96
#define mmCM0_CM_BLNDGAM_RAMA_END_CNTL1_G_BASE_IDX 2
#define mmCM0_CM_BLNDGAM_RAMA_END_CNTL2_G 0x0d97
#define mmCM0_CM_BLNDGAM_RAMA_END_CNTL2_G_BASE_IDX 2
#define mmCM0_CM_BLNDGAM_RAMA_END_CNTL1_R 0x0d98
#define mmCM0_CM_BLNDGAM_RAMA_END_CNTL1_R_BASE_IDX 2
#define mmCM0_CM_BLNDGAM_RAMA_END_CNTL2_R 0x0d99
#define mmCM0_CM_BLNDGAM_RAMA_END_CNTL2_R_BASE_IDX 2
#define mmCM0_CM_BLNDGAM_RAMA_OFFSET_B 0x0d9a
#define mmCM0_CM_BLNDGAM_RAMA_OFFSET_B_BASE_IDX 2
#define mmCM0_CM_BLNDGAM_RAMA_OFFSET_G 0x0d9b
#define mmCM0_CM_BLNDGAM_RAMA_OFFSET_G_BASE_IDX 2
#define mmCM0_CM_BLNDGAM_RAMA_OFFSET_R 0x0d9c
#define mmCM0_CM_BLNDGAM_RAMA_OFFSET_R_BASE_IDX 2
#define mmCM0_CM_BLNDGAM_RAMA_REGION_0_1 0x0d9d
#define mmCM0_CM_BLNDGAM_RAMA_REGION_0_1_BASE_IDX 2
#define mmCM0_CM_BLNDGAM_RAMA_REGION_2_3 0x0d9e
#define mmCM0_CM_BLNDGAM_RAMA_REGION_2_3_BASE_IDX 2
#define mmCM0_CM_BLNDGAM_RAMA_REGION_4_5 0x0d9f
#define mmCM0_CM_BLNDGAM_RAMA_REGION_4_5_BASE_IDX 2
#define mmCM0_CM_BLNDGAM_RAMA_REGION_6_7 0x0da0
#define mmCM0_CM_BLNDGAM_RAMA_REGION_6_7_BASE_IDX 2
#define mmCM0_CM_BLNDGAM_RAMA_REGION_8_9 0x0da1
#define mmCM0_CM_BLNDGAM_RAMA_REGION_8_9_BASE_IDX 2
#define mmCM0_CM_BLNDGAM_RAMA_REGION_10_11 0x0da2
#define mmCM0_CM_BLNDGAM_RAMA_REGION_10_11_BASE_IDX 2
#define mmCM0_CM_BLNDGAM_RAMA_REGION_12_13 0x0da3
#define mmCM0_CM_BLNDGAM_RAMA_REGION_12_13_BASE_IDX 2
#define mmCM0_CM_BLNDGAM_RAMA_REGION_14_15 0x0da4
#define mmCM0_CM_BLNDGAM_RAMA_REGION_14_15_BASE_IDX 2
#define mmCM0_CM_BLNDGAM_RAMA_REGION_16_17 0x0da5
#define mmCM0_CM_BLNDGAM_RAMA_REGION_16_17_BASE_IDX 2
#define mmCM0_CM_BLNDGAM_RAMA_REGION_18_19 0x0da6
#define mmCM0_CM_BLNDGAM_RAMA_REGION_18_19_BASE_IDX 2
#define mmCM0_CM_BLNDGAM_RAMA_REGION_20_21 0x0da7
#define mmCM0_CM_BLNDGAM_RAMA_REGION_20_21_BASE_IDX 2
#define mmCM0_CM_BLNDGAM_RAMA_REGION_22_23 0x0da8
#define mmCM0_CM_BLNDGAM_RAMA_REGION_22_23_BASE_IDX 2
#define mmCM0_CM_BLNDGAM_RAMA_REGION_24_25 0x0da9
#define mmCM0_CM_BLNDGAM_RAMA_REGION_24_25_BASE_IDX 2
#define mmCM0_CM_BLNDGAM_RAMA_REGION_26_27 0x0daa
#define mmCM0_CM_BLNDGAM_RAMA_REGION_26_27_BASE_IDX 2
#define mmCM0_CM_BLNDGAM_RAMA_REGION_28_29 0x0dab
#define mmCM0_CM_BLNDGAM_RAMA_REGION_28_29_BASE_IDX 2
#define mmCM0_CM_BLNDGAM_RAMA_REGION_30_31 0x0dac
#define mmCM0_CM_BLNDGAM_RAMA_REGION_30_31_BASE_IDX 2
#define mmCM0_CM_BLNDGAM_RAMA_REGION_32_33 0x0dad
#define mmCM0_CM_BLNDGAM_RAMA_REGION_32_33_BASE_IDX 2
#define mmCM0_CM_BLNDGAM_RAMB_START_CNTL_B 0x0dae
#define mmCM0_CM_BLNDGAM_RAMB_START_CNTL_B_BASE_IDX 2
#define mmCM0_CM_BLNDGAM_RAMB_START_CNTL_G 0x0daf
#define mmCM0_CM_BLNDGAM_RAMB_START_CNTL_G_BASE_IDX 2
#define mmCM0_CM_BLNDGAM_RAMB_START_CNTL_R 0x0db0
#define mmCM0_CM_BLNDGAM_RAMB_START_CNTL_R_BASE_IDX 2
#define mmCM0_CM_BLNDGAM_RAMB_START_SLOPE_CNTL_B 0x0db1
#define mmCM0_CM_BLNDGAM_RAMB_START_SLOPE_CNTL_B_BASE_IDX 2
#define mmCM0_CM_BLNDGAM_RAMB_START_SLOPE_CNTL_G 0x0db2
#define mmCM0_CM_BLNDGAM_RAMB_START_SLOPE_CNTL_G_BASE_IDX 2
#define mmCM0_CM_BLNDGAM_RAMB_START_SLOPE_CNTL_R 0x0db3
#define mmCM0_CM_BLNDGAM_RAMB_START_SLOPE_CNTL_R_BASE_IDX 2
#define mmCM0_CM_BLNDGAM_RAMB_START_BASE_CNTL_B 0x0db4
#define mmCM0_CM_BLNDGAM_RAMB_START_BASE_CNTL_B_BASE_IDX 2
#define mmCM0_CM_BLNDGAM_RAMB_START_BASE_CNTL_G 0x0db5
#define mmCM0_CM_BLNDGAM_RAMB_START_BASE_CNTL_G_BASE_IDX 2
#define mmCM0_CM_BLNDGAM_RAMB_START_BASE_CNTL_R 0x0db6
#define mmCM0_CM_BLNDGAM_RAMB_START_BASE_CNTL_R_BASE_IDX 2
#define mmCM0_CM_BLNDGAM_RAMB_END_CNTL1_B 0x0db7
#define mmCM0_CM_BLNDGAM_RAMB_END_CNTL1_B_BASE_IDX 2
#define mmCM0_CM_BLNDGAM_RAMB_END_CNTL2_B 0x0db8
#define mmCM0_CM_BLNDGAM_RAMB_END_CNTL2_B_BASE_IDX 2
#define mmCM0_CM_BLNDGAM_RAMB_END_CNTL1_G 0x0db9
#define mmCM0_CM_BLNDGAM_RAMB_END_CNTL1_G_BASE_IDX 2
#define mmCM0_CM_BLNDGAM_RAMB_END_CNTL2_G 0x0dba
#define mmCM0_CM_BLNDGAM_RAMB_END_CNTL2_G_BASE_IDX 2
#define mmCM0_CM_BLNDGAM_RAMB_END_CNTL1_R 0x0dbb
#define mmCM0_CM_BLNDGAM_RAMB_END_CNTL1_R_BASE_IDX 2
#define mmCM0_CM_BLNDGAM_RAMB_END_CNTL2_R 0x0dbc
#define mmCM0_CM_BLNDGAM_RAMB_END_CNTL2_R_BASE_IDX 2
#define mmCM0_CM_BLNDGAM_RAMB_OFFSET_B 0x0dbd
#define mmCM0_CM_BLNDGAM_RAMB_OFFSET_B_BASE_IDX 2
#define mmCM0_CM_BLNDGAM_RAMB_OFFSET_G 0x0dbe
#define mmCM0_CM_BLNDGAM_RAMB_OFFSET_G_BASE_IDX 2
#define mmCM0_CM_BLNDGAM_RAMB_OFFSET_R 0x0dbf
#define mmCM0_CM_BLNDGAM_RAMB_OFFSET_R_BASE_IDX 2
#define mmCM0_CM_BLNDGAM_RAMB_REGION_0_1 0x0dc0
#define mmCM0_CM_BLNDGAM_RAMB_REGION_0_1_BASE_IDX 2
#define mmCM0_CM_BLNDGAM_RAMB_REGION_2_3 0x0dc1
#define mmCM0_CM_BLNDGAM_RAMB_REGION_2_3_BASE_IDX 2
#define mmCM0_CM_BLNDGAM_RAMB_REGION_4_5 0x0dc2
#define mmCM0_CM_BLNDGAM_RAMB_REGION_4_5_BASE_IDX 2
#define mmCM0_CM_BLNDGAM_RAMB_REGION_6_7 0x0dc3
#define mmCM0_CM_BLNDGAM_RAMB_REGION_6_7_BASE_IDX 2
#define mmCM0_CM_BLNDGAM_RAMB_REGION_8_9 0x0dc4
#define mmCM0_CM_BLNDGAM_RAMB_REGION_8_9_BASE_IDX 2
#define mmCM0_CM_BLNDGAM_RAMB_REGION_10_11 0x0dc5
#define mmCM0_CM_BLNDGAM_RAMB_REGION_10_11_BASE_IDX 2
#define mmCM0_CM_BLNDGAM_RAMB_REGION_12_13 0x0dc6
#define mmCM0_CM_BLNDGAM_RAMB_REGION_12_13_BASE_IDX 2
#define mmCM0_CM_BLNDGAM_RAMB_REGION_14_15 0x0dc7
#define mmCM0_CM_BLNDGAM_RAMB_REGION_14_15_BASE_IDX 2
#define mmCM0_CM_BLNDGAM_RAMB_REGION_16_17 0x0dc8
#define mmCM0_CM_BLNDGAM_RAMB_REGION_16_17_BASE_IDX 2
#define mmCM0_CM_BLNDGAM_RAMB_REGION_18_19 0x0dc9
#define mmCM0_CM_BLNDGAM_RAMB_REGION_18_19_BASE_IDX 2
#define mmCM0_CM_BLNDGAM_RAMB_REGION_20_21 0x0dca
#define mmCM0_CM_BLNDGAM_RAMB_REGION_20_21_BASE_IDX 2
#define mmCM0_CM_BLNDGAM_RAMB_REGION_22_23 0x0dcb
#define mmCM0_CM_BLNDGAM_RAMB_REGION_22_23_BASE_IDX 2
#define mmCM0_CM_BLNDGAM_RAMB_REGION_24_25 0x0dcc
#define mmCM0_CM_BLNDGAM_RAMB_REGION_24_25_BASE_IDX 2
#define mmCM0_CM_BLNDGAM_RAMB_REGION_26_27 0x0dcd
#define mmCM0_CM_BLNDGAM_RAMB_REGION_26_27_BASE_IDX 2
#define mmCM0_CM_BLNDGAM_RAMB_REGION_28_29 0x0dce
#define mmCM0_CM_BLNDGAM_RAMB_REGION_28_29_BASE_IDX 2
#define mmCM0_CM_BLNDGAM_RAMB_REGION_30_31 0x0dcf
#define mmCM0_CM_BLNDGAM_RAMB_REGION_30_31_BASE_IDX 2
#define mmCM0_CM_BLNDGAM_RAMB_REGION_32_33 0x0dd0
#define mmCM0_CM_BLNDGAM_RAMB_REGION_32_33_BASE_IDX 2
#define mmCM0_CM_HDR_MULT_COEF 0x0dd1
#define mmCM0_CM_HDR_MULT_COEF_BASE_IDX 2
#define mmCM0_CM_MEM_PWR_CTRL 0x0dd2
#define mmCM0_CM_MEM_PWR_CTRL_BASE_IDX 2
#define mmCM0_CM_MEM_PWR_STATUS 0x0dd3
#define mmCM0_CM_MEM_PWR_STATUS_BASE_IDX 2
#define mmCM0_CM_DEALPHA 0x0dd5
#define mmCM0_CM_DEALPHA_BASE_IDX 2
#define mmCM0_CM_COEF_FORMAT 0x0dd6
#define mmCM0_CM_COEF_FORMAT_BASE_IDX 2
#define mmCM0_CM_SHAPER_CONTROL 0x0dd7
#define mmCM0_CM_SHAPER_CONTROL_BASE_IDX 2
#define mmCM0_CM_SHAPER_OFFSET_R 0x0dd8
#define mmCM0_CM_SHAPER_OFFSET_R_BASE_IDX 2
#define mmCM0_CM_SHAPER_OFFSET_G 0x0dd9
#define mmCM0_CM_SHAPER_OFFSET_G_BASE_IDX 2
#define mmCM0_CM_SHAPER_OFFSET_B 0x0dda
#define mmCM0_CM_SHAPER_OFFSET_B_BASE_IDX 2
#define mmCM0_CM_SHAPER_SCALE_R 0x0ddb
#define mmCM0_CM_SHAPER_SCALE_R_BASE_IDX 2
#define mmCM0_CM_SHAPER_SCALE_G_B 0x0ddc
#define mmCM0_CM_SHAPER_SCALE_G_B_BASE_IDX 2
#define mmCM0_CM_SHAPER_LUT_INDEX 0x0ddd
#define mmCM0_CM_SHAPER_LUT_INDEX_BASE_IDX 2
#define mmCM0_CM_SHAPER_LUT_DATA 0x0dde
#define mmCM0_CM_SHAPER_LUT_DATA_BASE_IDX 2
#define mmCM0_CM_SHAPER_LUT_WRITE_EN_MASK 0x0ddf
#define mmCM0_CM_SHAPER_LUT_WRITE_EN_MASK_BASE_IDX 2
#define mmCM0_CM_SHAPER_RAMA_START_CNTL_B 0x0de0
#define mmCM0_CM_SHAPER_RAMA_START_CNTL_B_BASE_IDX 2
#define mmCM0_CM_SHAPER_RAMA_START_CNTL_G 0x0de1
#define mmCM0_CM_SHAPER_RAMA_START_CNTL_G_BASE_IDX 2
#define mmCM0_CM_SHAPER_RAMA_START_CNTL_R 0x0de2
#define mmCM0_CM_SHAPER_RAMA_START_CNTL_R_BASE_IDX 2
#define mmCM0_CM_SHAPER_RAMA_END_CNTL_B 0x0de3
#define mmCM0_CM_SHAPER_RAMA_END_CNTL_B_BASE_IDX 2
#define mmCM0_CM_SHAPER_RAMA_END_CNTL_G 0x0de4
#define mmCM0_CM_SHAPER_RAMA_END_CNTL_G_BASE_IDX 2
#define mmCM0_CM_SHAPER_RAMA_END_CNTL_R 0x0de5
#define mmCM0_CM_SHAPER_RAMA_END_CNTL_R_BASE_IDX 2
#define mmCM0_CM_SHAPER_RAMA_REGION_0_1 0x0de6
#define mmCM0_CM_SHAPER_RAMA_REGION_0_1_BASE_IDX 2
#define mmCM0_CM_SHAPER_RAMA_REGION_2_3 0x0de7
#define mmCM0_CM_SHAPER_RAMA_REGION_2_3_BASE_IDX 2
#define mmCM0_CM_SHAPER_RAMA_REGION_4_5 0x0de8
#define mmCM0_CM_SHAPER_RAMA_REGION_4_5_BASE_IDX 2
#define mmCM0_CM_SHAPER_RAMA_REGION_6_7 0x0de9
#define mmCM0_CM_SHAPER_RAMA_REGION_6_7_BASE_IDX 2
#define mmCM0_CM_SHAPER_RAMA_REGION_8_9 0x0dea
#define mmCM0_CM_SHAPER_RAMA_REGION_8_9_BASE_IDX 2
#define mmCM0_CM_SHAPER_RAMA_REGION_10_11 0x0deb
#define mmCM0_CM_SHAPER_RAMA_REGION_10_11_BASE_IDX 2
#define mmCM0_CM_SHAPER_RAMA_REGION_12_13 0x0dec
#define mmCM0_CM_SHAPER_RAMA_REGION_12_13_BASE_IDX 2
#define mmCM0_CM_SHAPER_RAMA_REGION_14_15 0x0ded
#define mmCM0_CM_SHAPER_RAMA_REGION_14_15_BASE_IDX 2
#define mmCM0_CM_SHAPER_RAMA_REGION_16_17 0x0dee
#define mmCM0_CM_SHAPER_RAMA_REGION_16_17_BASE_IDX 2
#define mmCM0_CM_SHAPER_RAMA_REGION_18_19 0x0def
#define mmCM0_CM_SHAPER_RAMA_REGION_18_19_BASE_IDX 2
#define mmCM0_CM_SHAPER_RAMA_REGION_20_21 0x0df0
#define mmCM0_CM_SHAPER_RAMA_REGION_20_21_BASE_IDX 2
#define mmCM0_CM_SHAPER_RAMA_REGION_22_23 0x0df1
#define mmCM0_CM_SHAPER_RAMA_REGION_22_23_BASE_IDX 2
#define mmCM0_CM_SHAPER_RAMA_REGION_24_25 0x0df2
#define mmCM0_CM_SHAPER_RAMA_REGION_24_25_BASE_IDX 2
#define mmCM0_CM_SHAPER_RAMA_REGION_26_27 0x0df3
#define mmCM0_CM_SHAPER_RAMA_REGION_26_27_BASE_IDX 2
#define mmCM0_CM_SHAPER_RAMA_REGION_28_29 0x0df4
#define mmCM0_CM_SHAPER_RAMA_REGION_28_29_BASE_IDX 2
#define mmCM0_CM_SHAPER_RAMA_REGION_30_31 0x0df5
#define mmCM0_CM_SHAPER_RAMA_REGION_30_31_BASE_IDX 2
#define mmCM0_CM_SHAPER_RAMA_REGION_32_33 0x0df6
#define mmCM0_CM_SHAPER_RAMA_REGION_32_33_BASE_IDX 2
#define mmCM0_CM_SHAPER_RAMB_START_CNTL_B 0x0df7
#define mmCM0_CM_SHAPER_RAMB_START_CNTL_B_BASE_IDX 2
#define mmCM0_CM_SHAPER_RAMB_START_CNTL_G 0x0df8
#define mmCM0_CM_SHAPER_RAMB_START_CNTL_G_BASE_IDX 2
#define mmCM0_CM_SHAPER_RAMB_START_CNTL_R 0x0df9
#define mmCM0_CM_SHAPER_RAMB_START_CNTL_R_BASE_IDX 2
#define mmCM0_CM_SHAPER_RAMB_END_CNTL_B 0x0dfa
#define mmCM0_CM_SHAPER_RAMB_END_CNTL_B_BASE_IDX 2
#define mmCM0_CM_SHAPER_RAMB_END_CNTL_G 0x0dfb
#define mmCM0_CM_SHAPER_RAMB_END_CNTL_G_BASE_IDX 2
#define mmCM0_CM_SHAPER_RAMB_END_CNTL_R 0x0dfc
#define mmCM0_CM_SHAPER_RAMB_END_CNTL_R_BASE_IDX 2
#define mmCM0_CM_SHAPER_RAMB_REGION_0_1 0x0dfd
#define mmCM0_CM_SHAPER_RAMB_REGION_0_1_BASE_IDX 2
#define mmCM0_CM_SHAPER_RAMB_REGION_2_3 0x0dfe
#define mmCM0_CM_SHAPER_RAMB_REGION_2_3_BASE_IDX 2
#define mmCM0_CM_SHAPER_RAMB_REGION_4_5 0x0dff
#define mmCM0_CM_SHAPER_RAMB_REGION_4_5_BASE_IDX 2
#define mmCM0_CM_SHAPER_RAMB_REGION_6_7 0x0e00
#define mmCM0_CM_SHAPER_RAMB_REGION_6_7_BASE_IDX 2
#define mmCM0_CM_SHAPER_RAMB_REGION_8_9 0x0e01
#define mmCM0_CM_SHAPER_RAMB_REGION_8_9_BASE_IDX 2
#define mmCM0_CM_SHAPER_RAMB_REGION_10_11 0x0e02
#define mmCM0_CM_SHAPER_RAMB_REGION_10_11_BASE_IDX 2
#define mmCM0_CM_SHAPER_RAMB_REGION_12_13 0x0e03
#define mmCM0_CM_SHAPER_RAMB_REGION_12_13_BASE_IDX 2
#define mmCM0_CM_SHAPER_RAMB_REGION_14_15 0x0e04
#define mmCM0_CM_SHAPER_RAMB_REGION_14_15_BASE_IDX 2
#define mmCM0_CM_SHAPER_RAMB_REGION_16_17 0x0e05
#define mmCM0_CM_SHAPER_RAMB_REGION_16_17_BASE_IDX 2
#define mmCM0_CM_SHAPER_RAMB_REGION_18_19 0x0e06
#define mmCM0_CM_SHAPER_RAMB_REGION_18_19_BASE_IDX 2
#define mmCM0_CM_SHAPER_RAMB_REGION_20_21 0x0e07
#define mmCM0_CM_SHAPER_RAMB_REGION_20_21_BASE_IDX 2
#define mmCM0_CM_SHAPER_RAMB_REGION_22_23 0x0e08
#define mmCM0_CM_SHAPER_RAMB_REGION_22_23_BASE_IDX 2
#define mmCM0_CM_SHAPER_RAMB_REGION_24_25 0x0e09
#define mmCM0_CM_SHAPER_RAMB_REGION_24_25_BASE_IDX 2
#define mmCM0_CM_SHAPER_RAMB_REGION_26_27 0x0e0a
#define mmCM0_CM_SHAPER_RAMB_REGION_26_27_BASE_IDX 2
#define mmCM0_CM_SHAPER_RAMB_REGION_28_29 0x0e0b
#define mmCM0_CM_SHAPER_RAMB_REGION_28_29_BASE_IDX 2
#define mmCM0_CM_SHAPER_RAMB_REGION_30_31 0x0e0c
#define mmCM0_CM_SHAPER_RAMB_REGION_30_31_BASE_IDX 2
#define mmCM0_CM_SHAPER_RAMB_REGION_32_33 0x0e0d
#define mmCM0_CM_SHAPER_RAMB_REGION_32_33_BASE_IDX 2
#define mmCM0_CM_MEM_PWR_CTRL2 0x0e0e
#define mmCM0_CM_MEM_PWR_CTRL2_BASE_IDX 2
#define mmCM0_CM_MEM_PWR_STATUS2 0x0e0f
#define mmCM0_CM_MEM_PWR_STATUS2_BASE_IDX 2
#define mmCM0_CM_3DLUT_MODE 0x0e10
#define mmCM0_CM_3DLUT_MODE_BASE_IDX 2
#define mmCM0_CM_3DLUT_INDEX 0x0e11
#define mmCM0_CM_3DLUT_INDEX_BASE_IDX 2
#define mmCM0_CM_3DLUT_DATA 0x0e12
#define mmCM0_CM_3DLUT_DATA_BASE_IDX 2
#define mmCM0_CM_3DLUT_DATA_30BIT 0x0e13
#define mmCM0_CM_3DLUT_DATA_30BIT_BASE_IDX 2
#define mmCM0_CM_3DLUT_READ_WRITE_CONTROL 0x0e14
#define mmCM0_CM_3DLUT_READ_WRITE_CONTROL_BASE_IDX 2
#define mmCM0_CM_3DLUT_OUT_NORM_FACTOR 0x0e15
#define mmCM0_CM_3DLUT_OUT_NORM_FACTOR_BASE_IDX 2
#define mmCM0_CM_3DLUT_OUT_OFFSET_R 0x0e16
#define mmCM0_CM_3DLUT_OUT_OFFSET_R_BASE_IDX 2
#define mmCM0_CM_3DLUT_OUT_OFFSET_G 0x0e17
#define mmCM0_CM_3DLUT_OUT_OFFSET_G_BASE_IDX 2
#define mmCM0_CM_3DLUT_OUT_OFFSET_B 0x0e18
#define mmCM0_CM_3DLUT_OUT_OFFSET_B_BASE_IDX 2
// addressBlock: dce_dc_dpp0_dispdec_dpp_dcperfmon_dc_perfmon_dispdec
// base address: 0x3890
#define mmDC_PERFMON11_PERFCOUNTER_CNTL 0x0e24
#define mmDC_PERFMON11_PERFCOUNTER_CNTL_BASE_IDX 2
#define mmDC_PERFMON11_PERFCOUNTER_CNTL2 0x0e25
#define mmDC_PERFMON11_PERFCOUNTER_CNTL2_BASE_IDX 2
#define mmDC_PERFMON11_PERFCOUNTER_STATE 0x0e26
#define mmDC_PERFMON11_PERFCOUNTER_STATE_BASE_IDX 2
#define mmDC_PERFMON11_PERFMON_CNTL 0x0e27
#define mmDC_PERFMON11_PERFMON_CNTL_BASE_IDX 2
#define mmDC_PERFMON11_PERFMON_CNTL2 0x0e28
#define mmDC_PERFMON11_PERFMON_CNTL2_BASE_IDX 2
#define mmDC_PERFMON11_PERFMON_CVALUE_INT_MISC 0x0e29
#define mmDC_PERFMON11_PERFMON_CVALUE_INT_MISC_BASE_IDX 2
#define mmDC_PERFMON11_PERFMON_CVALUE_LOW 0x0e2a
#define mmDC_PERFMON11_PERFMON_CVALUE_LOW_BASE_IDX 2
#define mmDC_PERFMON11_PERFMON_HI 0x0e2b
#define mmDC_PERFMON11_PERFMON_HI_BASE_IDX 2
#define mmDC_PERFMON11_PERFMON_LOW 0x0e2c
#define mmDC_PERFMON11_PERFMON_LOW_BASE_IDX 2
// addressBlock: dce_dc_dpp1_dispdec_dpp_top_dispdec
// base address: 0x5ac
#define mmDPP_TOP1_DPP_CONTROL 0x0e30
#define mmDPP_TOP1_DPP_CONTROL_BASE_IDX 2
#define mmDPP_TOP1_DPP_SOFT_RESET 0x0e31
#define mmDPP_TOP1_DPP_SOFT_RESET_BASE_IDX 2
#define mmDPP_TOP1_DPP_CRC_VAL_R_G 0x0e32
#define mmDPP_TOP1_DPP_CRC_VAL_R_G_BASE_IDX 2
#define mmDPP_TOP1_DPP_CRC_VAL_B_A 0x0e33
#define mmDPP_TOP1_DPP_CRC_VAL_B_A_BASE_IDX 2
#define mmDPP_TOP1_DPP_CRC_CTRL 0x0e34
#define mmDPP_TOP1_DPP_CRC_CTRL_BASE_IDX 2
#define mmDPP_TOP1_HOST_READ_CONTROL 0x0e35
#define mmDPP_TOP1_HOST_READ_CONTROL_BASE_IDX 2
// addressBlock: dce_dc_dpp1_dispdec_cnvc_cfg_dispdec
// base address: 0x5ac
#define mmCNVC_CFG1_CNVC_SURFACE_PIXEL_FORMAT 0x0e3a
#define mmCNVC_CFG1_CNVC_SURFACE_PIXEL_FORMAT_BASE_IDX 2
#define mmCNVC_CFG1_FORMAT_CONTROL 0x0e3b
#define mmCNVC_CFG1_FORMAT_CONTROL_BASE_IDX 2
#define mmCNVC_CFG1_FCNV_FP_BIAS_R 0x0e3c
#define mmCNVC_CFG1_FCNV_FP_BIAS_R_BASE_IDX 2
#define mmCNVC_CFG1_FCNV_FP_BIAS_G 0x0e3d
#define mmCNVC_CFG1_FCNV_FP_BIAS_G_BASE_IDX 2
#define mmCNVC_CFG1_FCNV_FP_BIAS_B 0x0e3e
#define mmCNVC_CFG1_FCNV_FP_BIAS_B_BASE_IDX 2
#define mmCNVC_CFG1_FCNV_FP_SCALE_R 0x0e3f
#define mmCNVC_CFG1_FCNV_FP_SCALE_R_BASE_IDX 2
#define mmCNVC_CFG1_FCNV_FP_SCALE_G 0x0e40
#define mmCNVC_CFG1_FCNV_FP_SCALE_G_BASE_IDX 2
#define mmCNVC_CFG1_FCNV_FP_SCALE_B 0x0e41
#define mmCNVC_CFG1_FCNV_FP_SCALE_B_BASE_IDX 2
#define mmCNVC_CFG1_COLOR_KEYER_CONTROL 0x0e42
#define mmCNVC_CFG1_COLOR_KEYER_CONTROL_BASE_IDX 2
#define mmCNVC_CFG1_COLOR_KEYER_ALPHA 0x0e43
#define mmCNVC_CFG1_COLOR_KEYER_ALPHA_BASE_IDX 2
#define mmCNVC_CFG1_COLOR_KEYER_RED 0x0e44
#define mmCNVC_CFG1_COLOR_KEYER_RED_BASE_IDX 2
#define mmCNVC_CFG1_COLOR_KEYER_GREEN 0x0e45
#define mmCNVC_CFG1_COLOR_KEYER_GREEN_BASE_IDX 2
#define mmCNVC_CFG1_COLOR_KEYER_BLUE 0x0e46
#define mmCNVC_CFG1_COLOR_KEYER_BLUE_BASE_IDX 2
#define mmCNVC_CFG1_ALPHA_2BIT_LUT 0x0e48
#define mmCNVC_CFG1_ALPHA_2BIT_LUT_BASE_IDX 2
#define mmCNVC_CFG1_PRE_DEALPHA 0x0e49
#define mmCNVC_CFG1_PRE_DEALPHA_BASE_IDX 2
#define mmCNVC_CFG1_PRE_CSC_MODE 0x0e4a
#define mmCNVC_CFG1_PRE_CSC_MODE_BASE_IDX 2
#define mmCNVC_CFG1_PRE_CSC_C11_C12 0x0e4b
#define mmCNVC_CFG1_PRE_CSC_C11_C12_BASE_IDX 2
#define mmCNVC_CFG1_PRE_CSC_C13_C14 0x0e4c
#define mmCNVC_CFG1_PRE_CSC_C13_C14_BASE_IDX 2
#define mmCNVC_CFG1_PRE_CSC_C21_C22 0x0e4d
#define mmCNVC_CFG1_PRE_CSC_C21_C22_BASE_IDX 2
#define mmCNVC_CFG1_PRE_CSC_C23_C24 0x0e4e
#define mmCNVC_CFG1_PRE_CSC_C23_C24_BASE_IDX 2
#define mmCNVC_CFG1_PRE_CSC_C31_C32 0x0e4f
#define mmCNVC_CFG1_PRE_CSC_C31_C32_BASE_IDX 2
#define mmCNVC_CFG1_PRE_CSC_C33_C34 0x0e50
#define mmCNVC_CFG1_PRE_CSC_C33_C34_BASE_IDX 2
#define mmCNVC_CFG1_PRE_CSC_B_C11_C12 0x0e51
#define mmCNVC_CFG1_PRE_CSC_B_C11_C12_BASE_IDX 2
#define mmCNVC_CFG1_PRE_CSC_B_C13_C14 0x0e52
#define mmCNVC_CFG1_PRE_CSC_B_C13_C14_BASE_IDX 2
#define mmCNVC_CFG1_PRE_CSC_B_C21_C22 0x0e53
#define mmCNVC_CFG1_PRE_CSC_B_C21_C22_BASE_IDX 2
#define mmCNVC_CFG1_PRE_CSC_B_C23_C24 0x0e54
#define mmCNVC_CFG1_PRE_CSC_B_C23_C24_BASE_IDX 2
#define mmCNVC_CFG1_PRE_CSC_B_C31_C32 0x0e55
#define mmCNVC_CFG1_PRE_CSC_B_C31_C32_BASE_IDX 2
#define mmCNVC_CFG1_PRE_CSC_B_C33_C34 0x0e56
#define mmCNVC_CFG1_PRE_CSC_B_C33_C34_BASE_IDX 2
#define mmCNVC_CFG1_CNVC_COEF_FORMAT 0x0e57
#define mmCNVC_CFG1_CNVC_COEF_FORMAT_BASE_IDX 2
#define mmCNVC_CFG1_PRE_DEGAM 0x0e58
#define mmCNVC_CFG1_PRE_DEGAM_BASE_IDX 2
#define mmCNVC_CFG1_PRE_REALPHA 0x0e59
#define mmCNVC_CFG1_PRE_REALPHA_BASE_IDX 2
// addressBlock: dce_dc_dpp1_dispdec_cnvc_cur_dispdec
// base address: 0x5ac
#define mmCNVC_CUR1_CURSOR0_CONTROL 0x0e5c
#define mmCNVC_CUR1_CURSOR0_CONTROL_BASE_IDX 2
#define mmCNVC_CUR1_CURSOR0_COLOR0 0x0e5d
#define mmCNVC_CUR1_CURSOR0_COLOR0_BASE_IDX 2
#define mmCNVC_CUR1_CURSOR0_COLOR1 0x0e5e
#define mmCNVC_CUR1_CURSOR0_COLOR1_BASE_IDX 2
#define mmCNVC_CUR1_CURSOR0_FP_SCALE_BIAS 0x0e5f
#define mmCNVC_CUR1_CURSOR0_FP_SCALE_BIAS_BASE_IDX 2
// addressBlock: dce_dc_dpp1_dispdec_dscl_dispdec
// base address: 0x5ac
#define mmDSCL1_SCL_COEF_RAM_TAP_SELECT 0x0e64
#define mmDSCL1_SCL_COEF_RAM_TAP_SELECT_BASE_IDX 2
#define mmDSCL1_SCL_COEF_RAM_TAP_DATA 0x0e65
#define mmDSCL1_SCL_COEF_RAM_TAP_DATA_BASE_IDX 2
#define mmDSCL1_SCL_MODE 0x0e66
#define mmDSCL1_SCL_MODE_BASE_IDX 2
#define mmDSCL1_SCL_TAP_CONTROL 0x0e67
#define mmDSCL1_SCL_TAP_CONTROL_BASE_IDX 2
#define mmDSCL1_DSCL_CONTROL 0x0e68
#define mmDSCL1_DSCL_CONTROL_BASE_IDX 2
#define mmDSCL1_DSCL_2TAP_CONTROL 0x0e69
#define mmDSCL1_DSCL_2TAP_CONTROL_BASE_IDX 2
#define mmDSCL1_SCL_MANUAL_REPLICATE_CONTROL 0x0e6a
#define mmDSCL1_SCL_MANUAL_REPLICATE_CONTROL_BASE_IDX 2
#define mmDSCL1_SCL_HORZ_FILTER_SCALE_RATIO 0x0e6b
#define mmDSCL1_SCL_HORZ_FILTER_SCALE_RATIO_BASE_IDX 2
#define mmDSCL1_SCL_HORZ_FILTER_INIT 0x0e6c
#define mmDSCL1_SCL_HORZ_FILTER_INIT_BASE_IDX 2
#define mmDSCL1_SCL_HORZ_FILTER_SCALE_RATIO_C 0x0e6d
#define mmDSCL1_SCL_HORZ_FILTER_SCALE_RATIO_C_BASE_IDX 2
#define mmDSCL1_SCL_HORZ_FILTER_INIT_C 0x0e6e
#define mmDSCL1_SCL_HORZ_FILTER_INIT_C_BASE_IDX 2
#define mmDSCL1_SCL_VERT_FILTER_SCALE_RATIO 0x0e6f
#define mmDSCL1_SCL_VERT_FILTER_SCALE_RATIO_BASE_IDX 2
#define mmDSCL1_SCL_VERT_FILTER_INIT 0x0e70
#define mmDSCL1_SCL_VERT_FILTER_INIT_BASE_IDX 2
#define mmDSCL1_SCL_VERT_FILTER_INIT_BOT 0x0e71
#define mmDSCL1_SCL_VERT_FILTER_INIT_BOT_BASE_IDX 2
#define mmDSCL1_SCL_VERT_FILTER_SCALE_RATIO_C 0x0e72
#define mmDSCL1_SCL_VERT_FILTER_SCALE_RATIO_C_BASE_IDX 2
#define mmDSCL1_SCL_VERT_FILTER_INIT_C 0x0e73
#define mmDSCL1_SCL_VERT_FILTER_INIT_C_BASE_IDX 2
#define mmDSCL1_SCL_VERT_FILTER_INIT_BOT_C 0x0e74
#define mmDSCL1_SCL_VERT_FILTER_INIT_BOT_C_BASE_IDX 2
#define mmDSCL1_SCL_BLACK_COLOR 0x0e75
#define mmDSCL1_SCL_BLACK_COLOR_BASE_IDX 2
#define mmDSCL1_DSCL_UPDATE 0x0e76
#define mmDSCL1_DSCL_UPDATE_BASE_IDX 2
#define mmDSCL1_DSCL_AUTOCAL 0x0e77
#define mmDSCL1_DSCL_AUTOCAL_BASE_IDX 2
#define mmDSCL1_DSCL_EXT_OVERSCAN_LEFT_RIGHT 0x0e78
#define mmDSCL1_DSCL_EXT_OVERSCAN_LEFT_RIGHT_BASE_IDX 2
#define mmDSCL1_DSCL_EXT_OVERSCAN_TOP_BOTTOM 0x0e79
#define mmDSCL1_DSCL_EXT_OVERSCAN_TOP_BOTTOM_BASE_IDX 2
#define mmDSCL1_OTG_H_BLANK 0x0e7a
#define mmDSCL1_OTG_H_BLANK_BASE_IDX 2
#define mmDSCL1_OTG_V_BLANK 0x0e7b
#define mmDSCL1_OTG_V_BLANK_BASE_IDX 2
#define mmDSCL1_RECOUT_START 0x0e7c
#define mmDSCL1_RECOUT_START_BASE_IDX 2
#define mmDSCL1_RECOUT_SIZE 0x0e7d
#define mmDSCL1_RECOUT_SIZE_BASE_IDX 2
#define mmDSCL1_MPC_SIZE 0x0e7e
#define mmDSCL1_MPC_SIZE_BASE_IDX 2
#define mmDSCL1_LB_DATA_FORMAT 0x0e7f
#define mmDSCL1_LB_DATA_FORMAT_BASE_IDX 2
#define mmDSCL1_LB_MEMORY_CTRL 0x0e80
#define mmDSCL1_LB_MEMORY_CTRL_BASE_IDX 2
#define mmDSCL1_LB_V_COUNTER 0x0e81
#define mmDSCL1_LB_V_COUNTER_BASE_IDX 2
#define mmDSCL1_DSCL_MEM_PWR_CTRL 0x0e82
#define mmDSCL1_DSCL_MEM_PWR_CTRL_BASE_IDX 2
#define mmDSCL1_DSCL_MEM_PWR_STATUS 0x0e83
#define mmDSCL1_DSCL_MEM_PWR_STATUS_BASE_IDX 2
#define mmDSCL1_OBUF_CONTROL 0x0e84
#define mmDSCL1_OBUF_CONTROL_BASE_IDX 2
#define mmDSCL1_OBUF_MEM_PWR_CTRL 0x0e85
#define mmDSCL1_OBUF_MEM_PWR_CTRL_BASE_IDX 2
// addressBlock: dce_dc_dpp1_dispdec_cm_dispdec
// base address: 0x5ac
#define mmCM1_CM_CONTROL 0x0e8b
#define mmCM1_CM_CONTROL_BASE_IDX 2
#define mmCM1_CM_POST_CSC_CONTROL 0x0e8c
#define mmCM1_CM_POST_CSC_CONTROL_BASE_IDX 2
#define mmCM1_CM_POST_CSC_C11_C12 0x0e8d
#define mmCM1_CM_POST_CSC_C11_C12_BASE_IDX 2
#define mmCM1_CM_POST_CSC_C13_C14 0x0e8e
#define mmCM1_CM_POST_CSC_C13_C14_BASE_IDX 2
#define mmCM1_CM_POST_CSC_C21_C22 0x0e8f
#define mmCM1_CM_POST_CSC_C21_C22_BASE_IDX 2
#define mmCM1_CM_POST_CSC_C23_C24 0x0e90
#define mmCM1_CM_POST_CSC_C23_C24_BASE_IDX 2
#define mmCM1_CM_POST_CSC_C31_C32 0x0e91
#define mmCM1_CM_POST_CSC_C31_C32_BASE_IDX 2
#define mmCM1_CM_POST_CSC_C33_C34 0x0e92
#define mmCM1_CM_POST_CSC_C33_C34_BASE_IDX 2
#define mmCM1_CM_POST_CSC_B_C11_C12 0x0e93
#define mmCM1_CM_POST_CSC_B_C11_C12_BASE_IDX 2
#define mmCM1_CM_POST_CSC_B_C13_C14 0x0e94
#define mmCM1_CM_POST_CSC_B_C13_C14_BASE_IDX 2
#define mmCM1_CM_POST_CSC_B_C21_C22 0x0e95
#define mmCM1_CM_POST_CSC_B_C21_C22_BASE_IDX 2
#define mmCM1_CM_POST_CSC_B_C23_C24 0x0e96
#define mmCM1_CM_POST_CSC_B_C23_C24_BASE_IDX 2
#define mmCM1_CM_POST_CSC_B_C31_C32 0x0e97
#define mmCM1_CM_POST_CSC_B_C31_C32_BASE_IDX 2
#define mmCM1_CM_POST_CSC_B_C33_C34 0x0e98
#define mmCM1_CM_POST_CSC_B_C33_C34_BASE_IDX 2
#define mmCM1_CM_GAMUT_REMAP_CONTROL 0x0e99
#define mmCM1_CM_GAMUT_REMAP_CONTROL_BASE_IDX 2
#define mmCM1_CM_GAMUT_REMAP_C11_C12 0x0e9a
#define mmCM1_CM_GAMUT_REMAP_C11_C12_BASE_IDX 2
#define mmCM1_CM_GAMUT_REMAP_C13_C14 0x0e9b
#define mmCM1_CM_GAMUT_REMAP_C13_C14_BASE_IDX 2
#define mmCM1_CM_GAMUT_REMAP_C21_C22 0x0e9c
#define mmCM1_CM_GAMUT_REMAP_C21_C22_BASE_IDX 2
#define mmCM1_CM_GAMUT_REMAP_C23_C24 0x0e9d
#define mmCM1_CM_GAMUT_REMAP_C23_C24_BASE_IDX 2
#define mmCM1_CM_GAMUT_REMAP_C31_C32 0x0e9e
#define mmCM1_CM_GAMUT_REMAP_C31_C32_BASE_IDX 2
#define mmCM1_CM_GAMUT_REMAP_C33_C34 0x0e9f
#define mmCM1_CM_GAMUT_REMAP_C33_C34_BASE_IDX 2
#define mmCM1_CM_GAMUT_REMAP_B_C11_C12 0x0ea0
#define mmCM1_CM_GAMUT_REMAP_B_C11_C12_BASE_IDX 2
#define mmCM1_CM_GAMUT_REMAP_B_C13_C14 0x0ea1
#define mmCM1_CM_GAMUT_REMAP_B_C13_C14_BASE_IDX 2
#define mmCM1_CM_GAMUT_REMAP_B_C21_C22 0x0ea2
#define mmCM1_CM_GAMUT_REMAP_B_C21_C22_BASE_IDX 2
#define mmCM1_CM_GAMUT_REMAP_B_C23_C24 0x0ea3
#define mmCM1_CM_GAMUT_REMAP_B_C23_C24_BASE_IDX 2
#define mmCM1_CM_GAMUT_REMAP_B_C31_C32 0x0ea4
#define mmCM1_CM_GAMUT_REMAP_B_C31_C32_BASE_IDX 2
#define mmCM1_CM_GAMUT_REMAP_B_C33_C34 0x0ea5
#define mmCM1_CM_GAMUT_REMAP_B_C33_C34_BASE_IDX 2
#define mmCM1_CM_BIAS_CR_R 0x0ea6
#define mmCM1_CM_BIAS_CR_R_BASE_IDX 2
#define mmCM1_CM_BIAS_Y_G_CB_B 0x0ea7
#define mmCM1_CM_BIAS_Y_G_CB_B_BASE_IDX 2
#define mmCM1_CM_GAMCOR_CONTROL 0x0ea8
#define mmCM1_CM_GAMCOR_CONTROL_BASE_IDX 2
#define mmCM1_CM_GAMCOR_LUT_INDEX 0x0ea9
#define mmCM1_CM_GAMCOR_LUT_INDEX_BASE_IDX 2
#define mmCM1_CM_GAMCOR_LUT_DATA 0x0eaa
#define mmCM1_CM_GAMCOR_LUT_DATA_BASE_IDX 2
#define mmCM1_CM_GAMCOR_LUT_CONTROL 0x0eab
#define mmCM1_CM_GAMCOR_LUT_CONTROL_BASE_IDX 2
#define mmCM1_CM_GAMCOR_RAMA_START_CNTL_B 0x0eac
#define mmCM1_CM_GAMCOR_RAMA_START_CNTL_B_BASE_IDX 2
#define mmCM1_CM_GAMCOR_RAMA_START_CNTL_G 0x0ead
#define mmCM1_CM_GAMCOR_RAMA_START_CNTL_G_BASE_IDX 2
#define mmCM1_CM_GAMCOR_RAMA_START_CNTL_R 0x0eae
#define mmCM1_CM_GAMCOR_RAMA_START_CNTL_R_BASE_IDX 2
#define mmCM1_CM_GAMCOR_RAMA_START_SLOPE_CNTL_B 0x0eaf
#define mmCM1_CM_GAMCOR_RAMA_START_SLOPE_CNTL_B_BASE_IDX 2
#define mmCM1_CM_GAMCOR_RAMA_START_SLOPE_CNTL_G 0x0eb0
#define mmCM1_CM_GAMCOR_RAMA_START_SLOPE_CNTL_G_BASE_IDX 2
#define mmCM1_CM_GAMCOR_RAMA_START_SLOPE_CNTL_R 0x0eb1
#define mmCM1_CM_GAMCOR_RAMA_START_SLOPE_CNTL_R_BASE_IDX 2
#define mmCM1_CM_GAMCOR_RAMA_START_BASE_CNTL_B 0x0eb2
#define mmCM1_CM_GAMCOR_RAMA_START_BASE_CNTL_B_BASE_IDX 2
#define mmCM1_CM_GAMCOR_RAMA_START_BASE_CNTL_G 0x0eb3
#define mmCM1_CM_GAMCOR_RAMA_START_BASE_CNTL_G_BASE_IDX 2
#define mmCM1_CM_GAMCOR_RAMA_START_BASE_CNTL_R 0x0eb4
#define mmCM1_CM_GAMCOR_RAMA_START_BASE_CNTL_R_BASE_IDX 2
#define mmCM1_CM_GAMCOR_RAMA_END_CNTL1_B 0x0eb5
#define mmCM1_CM_GAMCOR_RAMA_END_CNTL1_B_BASE_IDX 2
#define mmCM1_CM_GAMCOR_RAMA_END_CNTL2_B 0x0eb6
#define mmCM1_CM_GAMCOR_RAMA_END_CNTL2_B_BASE_IDX 2
#define mmCM1_CM_GAMCOR_RAMA_END_CNTL1_G 0x0eb7
#define mmCM1_CM_GAMCOR_RAMA_END_CNTL1_G_BASE_IDX 2
#define mmCM1_CM_GAMCOR_RAMA_END_CNTL2_G 0x0eb8
#define mmCM1_CM_GAMCOR_RAMA_END_CNTL2_G_BASE_IDX 2
#define mmCM1_CM_GAMCOR_RAMA_END_CNTL1_R 0x0eb9
#define mmCM1_CM_GAMCOR_RAMA_END_CNTL1_R_BASE_IDX 2
#define mmCM1_CM_GAMCOR_RAMA_END_CNTL2_R 0x0eba
#define mmCM1_CM_GAMCOR_RAMA_END_CNTL2_R_BASE_IDX 2
#define mmCM1_CM_GAMCOR_RAMA_OFFSET_B 0x0ebb
#define mmCM1_CM_GAMCOR_RAMA_OFFSET_B_BASE_IDX 2
#define mmCM1_CM_GAMCOR_RAMA_OFFSET_G 0x0ebc
#define mmCM1_CM_GAMCOR_RAMA_OFFSET_G_BASE_IDX 2
#define mmCM1_CM_GAMCOR_RAMA_OFFSET_R 0x0ebd
#define mmCM1_CM_GAMCOR_RAMA_OFFSET_R_BASE_IDX 2
#define mmCM1_CM_GAMCOR_RAMA_REGION_0_1 0x0ebe
#define mmCM1_CM_GAMCOR_RAMA_REGION_0_1_BASE_IDX 2
#define mmCM1_CM_GAMCOR_RAMA_REGION_2_3 0x0ebf
#define mmCM1_CM_GAMCOR_RAMA_REGION_2_3_BASE_IDX 2
#define mmCM1_CM_GAMCOR_RAMA_REGION_4_5 0x0ec0
#define mmCM1_CM_GAMCOR_RAMA_REGION_4_5_BASE_IDX 2
#define mmCM1_CM_GAMCOR_RAMA_REGION_6_7 0x0ec1
#define mmCM1_CM_GAMCOR_RAMA_REGION_6_7_BASE_IDX 2
#define mmCM1_CM_GAMCOR_RAMA_REGION_8_9 0x0ec2
#define mmCM1_CM_GAMCOR_RAMA_REGION_8_9_BASE_IDX 2
#define mmCM1_CM_GAMCOR_RAMA_REGION_10_11 0x0ec3
#define mmCM1_CM_GAMCOR_RAMA_REGION_10_11_BASE_IDX 2
#define mmCM1_CM_GAMCOR_RAMA_REGION_12_13 0x0ec4
#define mmCM1_CM_GAMCOR_RAMA_REGION_12_13_BASE_IDX 2
#define mmCM1_CM_GAMCOR_RAMA_REGION_14_15 0x0ec5
#define mmCM1_CM_GAMCOR_RAMA_REGION_14_15_BASE_IDX 2
#define mmCM1_CM_GAMCOR_RAMA_REGION_16_17 0x0ec6
#define mmCM1_CM_GAMCOR_RAMA_REGION_16_17_BASE_IDX 2
#define mmCM1_CM_GAMCOR_RAMA_REGION_18_19 0x0ec7
#define mmCM1_CM_GAMCOR_RAMA_REGION_18_19_BASE_IDX 2
#define mmCM1_CM_GAMCOR_RAMA_REGION_20_21 0x0ec8
#define mmCM1_CM_GAMCOR_RAMA_REGION_20_21_BASE_IDX 2
#define mmCM1_CM_GAMCOR_RAMA_REGION_22_23 0x0ec9
#define mmCM1_CM_GAMCOR_RAMA_REGION_22_23_BASE_IDX 2
#define mmCM1_CM_GAMCOR_RAMA_REGION_24_25 0x0eca
#define mmCM1_CM_GAMCOR_RAMA_REGION_24_25_BASE_IDX 2
#define mmCM1_CM_GAMCOR_RAMA_REGION_26_27 0x0ecb
#define mmCM1_CM_GAMCOR_RAMA_REGION_26_27_BASE_IDX 2
#define mmCM1_CM_GAMCOR_RAMA_REGION_28_29 0x0ecc
#define mmCM1_CM_GAMCOR_RAMA_REGION_28_29_BASE_IDX 2
#define mmCM1_CM_GAMCOR_RAMA_REGION_30_31 0x0ecd
#define mmCM1_CM_GAMCOR_RAMA_REGION_30_31_BASE_IDX 2
#define mmCM1_CM_GAMCOR_RAMA_REGION_32_33 0x0ece
#define mmCM1_CM_GAMCOR_RAMA_REGION_32_33_BASE_IDX 2
#define mmCM1_CM_GAMCOR_RAMB_START_CNTL_B 0x0ecf
#define mmCM1_CM_GAMCOR_RAMB_START_CNTL_B_BASE_IDX 2
#define mmCM1_CM_GAMCOR_RAMB_START_CNTL_G 0x0ed0
#define mmCM1_CM_GAMCOR_RAMB_START_CNTL_G_BASE_IDX 2
#define mmCM1_CM_GAMCOR_RAMB_START_CNTL_R 0x0ed1
#define mmCM1_CM_GAMCOR_RAMB_START_CNTL_R_BASE_IDX 2
#define mmCM1_CM_GAMCOR_RAMB_START_SLOPE_CNTL_B 0x0ed2
#define mmCM1_CM_GAMCOR_RAMB_START_SLOPE_CNTL_B_BASE_IDX 2
#define mmCM1_CM_GAMCOR_RAMB_START_SLOPE_CNTL_G 0x0ed3
#define mmCM1_CM_GAMCOR_RAMB_START_SLOPE_CNTL_G_BASE_IDX 2
#define mmCM1_CM_GAMCOR_RAMB_START_SLOPE_CNTL_R 0x0ed4
#define mmCM1_CM_GAMCOR_RAMB_START_SLOPE_CNTL_R_BASE_IDX 2
#define mmCM1_CM_GAMCOR_RAMB_START_BASE_CNTL_B 0x0ed5
#define mmCM1_CM_GAMCOR_RAMB_START_BASE_CNTL_B_BASE_IDX 2
#define mmCM1_CM_GAMCOR_RAMB_START_BASE_CNTL_G 0x0ed6
#define mmCM1_CM_GAMCOR_RAMB_START_BASE_CNTL_G_BASE_IDX 2
#define mmCM1_CM_GAMCOR_RAMB_START_BASE_CNTL_R 0x0ed7
#define mmCM1_CM_GAMCOR_RAMB_START_BASE_CNTL_R_BASE_IDX 2
#define mmCM1_CM_GAMCOR_RAMB_END_CNTL1_B 0x0ed8
#define mmCM1_CM_GAMCOR_RAMB_END_CNTL1_B_BASE_IDX 2
#define mmCM1_CM_GAMCOR_RAMB_END_CNTL2_B 0x0ed9
#define mmCM1_CM_GAMCOR_RAMB_END_CNTL2_B_BASE_IDX 2
#define mmCM1_CM_GAMCOR_RAMB_END_CNTL1_G 0x0eda
#define mmCM1_CM_GAMCOR_RAMB_END_CNTL1_G_BASE_IDX 2
#define mmCM1_CM_GAMCOR_RAMB_END_CNTL2_G 0x0edb
#define mmCM1_CM_GAMCOR_RAMB_END_CNTL2_G_BASE_IDX 2
#define mmCM1_CM_GAMCOR_RAMB_END_CNTL1_R 0x0edc
#define mmCM1_CM_GAMCOR_RAMB_END_CNTL1_R_BASE_IDX 2
#define mmCM1_CM_GAMCOR_RAMB_END_CNTL2_R 0x0edd
#define mmCM1_CM_GAMCOR_RAMB_END_CNTL2_R_BASE_IDX 2
#define mmCM1_CM_GAMCOR_RAMB_OFFSET_B 0x0ede
#define mmCM1_CM_GAMCOR_RAMB_OFFSET_B_BASE_IDX 2
#define mmCM1_CM_GAMCOR_RAMB_OFFSET_G 0x0edf
#define mmCM1_CM_GAMCOR_RAMB_OFFSET_G_BASE_IDX 2
#define mmCM1_CM_GAMCOR_RAMB_OFFSET_R 0x0ee0
#define mmCM1_CM_GAMCOR_RAMB_OFFSET_R_BASE_IDX 2
#define mmCM1_CM_GAMCOR_RAMB_REGION_0_1 0x0ee1
#define mmCM1_CM_GAMCOR_RAMB_REGION_0_1_BASE_IDX 2
#define mmCM1_CM_GAMCOR_RAMB_REGION_2_3 0x0ee2
#define mmCM1_CM_GAMCOR_RAMB_REGION_2_3_BASE_IDX 2
#define mmCM1_CM_GAMCOR_RAMB_REGION_4_5 0x0ee3
#define mmCM1_CM_GAMCOR_RAMB_REGION_4_5_BASE_IDX 2
#define mmCM1_CM_GAMCOR_RAMB_REGION_6_7 0x0ee4
#define mmCM1_CM_GAMCOR_RAMB_REGION_6_7_BASE_IDX 2
#define mmCM1_CM_GAMCOR_RAMB_REGION_8_9 0x0ee5
#define mmCM1_CM_GAMCOR_RAMB_REGION_8_9_BASE_IDX 2
#define mmCM1_CM_GAMCOR_RAMB_REGION_10_11 0x0ee6
#define mmCM1_CM_GAMCOR_RAMB_REGION_10_11_BASE_IDX 2
#define mmCM1_CM_GAMCOR_RAMB_REGION_12_13 0x0ee7
#define mmCM1_CM_GAMCOR_RAMB_REGION_12_13_BASE_IDX 2
#define mmCM1_CM_GAMCOR_RAMB_REGION_14_15 0x0ee8
#define mmCM1_CM_GAMCOR_RAMB_REGION_14_15_BASE_IDX 2
#define mmCM1_CM_GAMCOR_RAMB_REGION_16_17 0x0ee9
#define mmCM1_CM_GAMCOR_RAMB_REGION_16_17_BASE_IDX 2
#define mmCM1_CM_GAMCOR_RAMB_REGION_18_19 0x0eea
#define mmCM1_CM_GAMCOR_RAMB_REGION_18_19_BASE_IDX 2
#define mmCM1_CM_GAMCOR_RAMB_REGION_20_21 0x0eeb
#define mmCM1_CM_GAMCOR_RAMB_REGION_20_21_BASE_IDX 2
#define mmCM1_CM_GAMCOR_RAMB_REGION_22_23 0x0eec
#define mmCM1_CM_GAMCOR_RAMB_REGION_22_23_BASE_IDX 2
#define mmCM1_CM_GAMCOR_RAMB_REGION_24_25 0x0eed
#define mmCM1_CM_GAMCOR_RAMB_REGION_24_25_BASE_IDX 2
#define mmCM1_CM_GAMCOR_RAMB_REGION_26_27 0x0eee
#define mmCM1_CM_GAMCOR_RAMB_REGION_26_27_BASE_IDX 2
#define mmCM1_CM_GAMCOR_RAMB_REGION_28_29 0x0eef
#define mmCM1_CM_GAMCOR_RAMB_REGION_28_29_BASE_IDX 2
#define mmCM1_CM_GAMCOR_RAMB_REGION_30_31 0x0ef0
#define mmCM1_CM_GAMCOR_RAMB_REGION_30_31_BASE_IDX 2
#define mmCM1_CM_GAMCOR_RAMB_REGION_32_33 0x0ef1
#define mmCM1_CM_GAMCOR_RAMB_REGION_32_33_BASE_IDX 2
#define mmCM1_CM_BLNDGAM_CONTROL 0x0ef2
#define mmCM1_CM_BLNDGAM_CONTROL_BASE_IDX 2
#define mmCM1_CM_BLNDGAM_LUT_INDEX 0x0ef3
#define mmCM1_CM_BLNDGAM_LUT_INDEX_BASE_IDX 2
#define mmCM1_CM_BLNDGAM_LUT_DATA 0x0ef4
#define mmCM1_CM_BLNDGAM_LUT_DATA_BASE_IDX 2
#define mmCM1_CM_BLNDGAM_LUT_CONTROL 0x0ef5
#define mmCM1_CM_BLNDGAM_LUT_CONTROL_BASE_IDX 2
#define mmCM1_CM_BLNDGAM_RAMA_START_CNTL_B 0x0ef6
#define mmCM1_CM_BLNDGAM_RAMA_START_CNTL_B_BASE_IDX 2
#define mmCM1_CM_BLNDGAM_RAMA_START_CNTL_G 0x0ef7
#define mmCM1_CM_BLNDGAM_RAMA_START_CNTL_G_BASE_IDX 2
#define mmCM1_CM_BLNDGAM_RAMA_START_CNTL_R 0x0ef8
#define mmCM1_CM_BLNDGAM_RAMA_START_CNTL_R_BASE_IDX 2
#define mmCM1_CM_BLNDGAM_RAMA_START_SLOPE_CNTL_B 0x0ef9
#define mmCM1_CM_BLNDGAM_RAMA_START_SLOPE_CNTL_B_BASE_IDX 2
#define mmCM1_CM_BLNDGAM_RAMA_START_SLOPE_CNTL_G 0x0efa
#define mmCM1_CM_BLNDGAM_RAMA_START_SLOPE_CNTL_G_BASE_IDX 2
#define mmCM1_CM_BLNDGAM_RAMA_START_SLOPE_CNTL_R 0x0efb
#define mmCM1_CM_BLNDGAM_RAMA_START_SLOPE_CNTL_R_BASE_IDX 2
#define mmCM1_CM_BLNDGAM_RAMA_START_BASE_CNTL_B 0x0efc
#define mmCM1_CM_BLNDGAM_RAMA_START_BASE_CNTL_B_BASE_IDX 2
#define mmCM1_CM_BLNDGAM_RAMA_START_BASE_CNTL_G 0x0efd
#define mmCM1_CM_BLNDGAM_RAMA_START_BASE_CNTL_G_BASE_IDX 2
#define mmCM1_CM_BLNDGAM_RAMA_START_BASE_CNTL_R 0x0efe
#define mmCM1_CM_BLNDGAM_RAMA_START_BASE_CNTL_R_BASE_IDX 2
#define mmCM1_CM_BLNDGAM_RAMA_END_CNTL1_B 0x0eff
#define mmCM1_CM_BLNDGAM_RAMA_END_CNTL1_B_BASE_IDX 2
#define mmCM1_CM_BLNDGAM_RAMA_END_CNTL2_B 0x0f00
#define mmCM1_CM_BLNDGAM_RAMA_END_CNTL2_B_BASE_IDX 2
#define mmCM1_CM_BLNDGAM_RAMA_END_CNTL1_G 0x0f01
#define mmCM1_CM_BLNDGAM_RAMA_END_CNTL1_G_BASE_IDX 2
#define mmCM1_CM_BLNDGAM_RAMA_END_CNTL2_G 0x0f02
#define mmCM1_CM_BLNDGAM_RAMA_END_CNTL2_G_BASE_IDX 2
#define mmCM1_CM_BLNDGAM_RAMA_END_CNTL1_R 0x0f03
#define mmCM1_CM_BLNDGAM_RAMA_END_CNTL1_R_BASE_IDX 2
#define mmCM1_CM_BLNDGAM_RAMA_END_CNTL2_R 0x0f04
#define mmCM1_CM_BLNDGAM_RAMA_END_CNTL2_R_BASE_IDX 2
#define mmCM1_CM_BLNDGAM_RAMA_OFFSET_B 0x0f05
#define mmCM1_CM_BLNDGAM_RAMA_OFFSET_B_BASE_IDX 2
#define mmCM1_CM_BLNDGAM_RAMA_OFFSET_G 0x0f06
#define mmCM1_CM_BLNDGAM_RAMA_OFFSET_G_BASE_IDX 2
#define mmCM1_CM_BLNDGAM_RAMA_OFFSET_R 0x0f07
#define mmCM1_CM_BLNDGAM_RAMA_OFFSET_R_BASE_IDX 2
#define mmCM1_CM_BLNDGAM_RAMA_REGION_0_1 0x0f08
#define mmCM1_CM_BLNDGAM_RAMA_REGION_0_1_BASE_IDX 2
#define mmCM1_CM_BLNDGAM_RAMA_REGION_2_3 0x0f09
#define mmCM1_CM_BLNDGAM_RAMA_REGION_2_3_BASE_IDX 2
#define mmCM1_CM_BLNDGAM_RAMA_REGION_4_5 0x0f0a
#define mmCM1_CM_BLNDGAM_RAMA_REGION_4_5_BASE_IDX 2
#define mmCM1_CM_BLNDGAM_RAMA_REGION_6_7 0x0f0b
#define mmCM1_CM_BLNDGAM_RAMA_REGION_6_7_BASE_IDX 2
#define mmCM1_CM_BLNDGAM_RAMA_REGION_8_9 0x0f0c
#define mmCM1_CM_BLNDGAM_RAMA_REGION_8_9_BASE_IDX 2
#define mmCM1_CM_BLNDGAM_RAMA_REGION_10_11 0x0f0d
#define mmCM1_CM_BLNDGAM_RAMA_REGION_10_11_BASE_IDX 2
#define mmCM1_CM_BLNDGAM_RAMA_REGION_12_13 0x0f0e
#define mmCM1_CM_BLNDGAM_RAMA_REGION_12_13_BASE_IDX 2
#define mmCM1_CM_BLNDGAM_RAMA_REGION_14_15 0x0f0f
#define mmCM1_CM_BLNDGAM_RAMA_REGION_14_15_BASE_IDX 2
#define mmCM1_CM_BLNDGAM_RAMA_REGION_16_17 0x0f10
#define mmCM1_CM_BLNDGAM_RAMA_REGION_16_17_BASE_IDX 2
#define mmCM1_CM_BLNDGAM_RAMA_REGION_18_19 0x0f11
#define mmCM1_CM_BLNDGAM_RAMA_REGION_18_19_BASE_IDX 2
#define mmCM1_CM_BLNDGAM_RAMA_REGION_20_21 0x0f12
#define mmCM1_CM_BLNDGAM_RAMA_REGION_20_21_BASE_IDX 2
#define mmCM1_CM_BLNDGAM_RAMA_REGION_22_23 0x0f13
#define mmCM1_CM_BLNDGAM_RAMA_REGION_22_23_BASE_IDX 2
#define mmCM1_CM_BLNDGAM_RAMA_REGION_24_25 0x0f14
#define mmCM1_CM_BLNDGAM_RAMA_REGION_24_25_BASE_IDX 2
#define mmCM1_CM_BLNDGAM_RAMA_REGION_26_27 0x0f15
#define mmCM1_CM_BLNDGAM_RAMA_REGION_26_27_BASE_IDX 2
#define mmCM1_CM_BLNDGAM_RAMA_REGION_28_29 0x0f16
#define mmCM1_CM_BLNDGAM_RAMA_REGION_28_29_BASE_IDX 2
#define mmCM1_CM_BLNDGAM_RAMA_REGION_30_31 0x0f17
#define mmCM1_CM_BLNDGAM_RAMA_REGION_30_31_BASE_IDX 2
#define mmCM1_CM_BLNDGAM_RAMA_REGION_32_33 0x0f18
#define mmCM1_CM_BLNDGAM_RAMA_REGION_32_33_BASE_IDX 2
#define mmCM1_CM_BLNDGAM_RAMB_START_CNTL_B 0x0f19
#define mmCM1_CM_BLNDGAM_RAMB_START_CNTL_B_BASE_IDX 2
#define mmCM1_CM_BLNDGAM_RAMB_START_CNTL_G 0x0f1a
#define mmCM1_CM_BLNDGAM_RAMB_START_CNTL_G_BASE_IDX 2
#define mmCM1_CM_BLNDGAM_RAMB_START_CNTL_R 0x0f1b
#define mmCM1_CM_BLNDGAM_RAMB_START_CNTL_R_BASE_IDX 2
#define mmCM1_CM_BLNDGAM_RAMB_START_SLOPE_CNTL_B 0x0f1c
#define mmCM1_CM_BLNDGAM_RAMB_START_SLOPE_CNTL_B_BASE_IDX 2
#define mmCM1_CM_BLNDGAM_RAMB_START_SLOPE_CNTL_G 0x0f1d
#define mmCM1_CM_BLNDGAM_RAMB_START_SLOPE_CNTL_G_BASE_IDX 2
#define mmCM1_CM_BLNDGAM_RAMB_START_SLOPE_CNTL_R 0x0f1e
#define mmCM1_CM_BLNDGAM_RAMB_START_SLOPE_CNTL_R_BASE_IDX 2
#define mmCM1_CM_BLNDGAM_RAMB_START_BASE_CNTL_B 0x0f1f
#define mmCM1_CM_BLNDGAM_RAMB_START_BASE_CNTL_B_BASE_IDX 2
#define mmCM1_CM_BLNDGAM_RAMB_START_BASE_CNTL_G 0x0f20
#define mmCM1_CM_BLNDGAM_RAMB_START_BASE_CNTL_G_BASE_IDX 2
#define mmCM1_CM_BLNDGAM_RAMB_START_BASE_CNTL_R 0x0f21
#define mmCM1_CM_BLNDGAM_RAMB_START_BASE_CNTL_R_BASE_IDX 2
#define mmCM1_CM_BLNDGAM_RAMB_END_CNTL1_B 0x0f22
#define mmCM1_CM_BLNDGAM_RAMB_END_CNTL1_B_BASE_IDX 2
#define mmCM1_CM_BLNDGAM_RAMB_END_CNTL2_B 0x0f23
#define mmCM1_CM_BLNDGAM_RAMB_END_CNTL2_B_BASE_IDX 2
#define mmCM1_CM_BLNDGAM_RAMB_END_CNTL1_G 0x0f24
#define mmCM1_CM_BLNDGAM_RAMB_END_CNTL1_G_BASE_IDX 2
#define mmCM1_CM_BLNDGAM_RAMB_END_CNTL2_G 0x0f25
#define mmCM1_CM_BLNDGAM_RAMB_END_CNTL2_G_BASE_IDX 2
#define mmCM1_CM_BLNDGAM_RAMB_END_CNTL1_R 0x0f26
#define mmCM1_CM_BLNDGAM_RAMB_END_CNTL1_R_BASE_IDX 2
#define mmCM1_CM_BLNDGAM_RAMB_END_CNTL2_R 0x0f27
#define mmCM1_CM_BLNDGAM_RAMB_END_CNTL2_R_BASE_IDX 2
#define mmCM1_CM_BLNDGAM_RAMB_OFFSET_B 0x0f28
#define mmCM1_CM_BLNDGAM_RAMB_OFFSET_B_BASE_IDX 2
#define mmCM1_CM_BLNDGAM_RAMB_OFFSET_G 0x0f29
#define mmCM1_CM_BLNDGAM_RAMB_OFFSET_G_BASE_IDX 2
#define mmCM1_CM_BLNDGAM_RAMB_OFFSET_R 0x0f2a
#define mmCM1_CM_BLNDGAM_RAMB_OFFSET_R_BASE_IDX 2
#define mmCM1_CM_BLNDGAM_RAMB_REGION_0_1 0x0f2b
#define mmCM1_CM_BLNDGAM_RAMB_REGION_0_1_BASE_IDX 2
#define mmCM1_CM_BLNDGAM_RAMB_REGION_2_3 0x0f2c
#define mmCM1_CM_BLNDGAM_RAMB_REGION_2_3_BASE_IDX 2
#define mmCM1_CM_BLNDGAM_RAMB_REGION_4_5 0x0f2d
#define mmCM1_CM_BLNDGAM_RAMB_REGION_4_5_BASE_IDX 2
#define mmCM1_CM_BLNDGAM_RAMB_REGION_6_7 0x0f2e
#define mmCM1_CM_BLNDGAM_RAMB_REGION_6_7_BASE_IDX 2
#define mmCM1_CM_BLNDGAM_RAMB_REGION_8_9 0x0f2f
#define mmCM1_CM_BLNDGAM_RAMB_REGION_8_9_BASE_IDX 2
#define mmCM1_CM_BLNDGAM_RAMB_REGION_10_11 0x0f30
#define mmCM1_CM_BLNDGAM_RAMB_REGION_10_11_BASE_IDX 2
#define mmCM1_CM_BLNDGAM_RAMB_REGION_12_13 0x0f31
#define mmCM1_CM_BLNDGAM_RAMB_REGION_12_13_BASE_IDX 2
#define mmCM1_CM_BLNDGAM_RAMB_REGION_14_15 0x0f32
#define mmCM1_CM_BLNDGAM_RAMB_REGION_14_15_BASE_IDX 2
#define mmCM1_CM_BLNDGAM_RAMB_REGION_16_17 0x0f33
#define mmCM1_CM_BLNDGAM_RAMB_REGION_16_17_BASE_IDX 2
#define mmCM1_CM_BLNDGAM_RAMB_REGION_18_19 0x0f34
#define mmCM1_CM_BLNDGAM_RAMB_REGION_18_19_BASE_IDX 2
#define mmCM1_CM_BLNDGAM_RAMB_REGION_20_21 0x0f35
#define mmCM1_CM_BLNDGAM_RAMB_REGION_20_21_BASE_IDX 2
#define mmCM1_CM_BLNDGAM_RAMB_REGION_22_23 0x0f36
#define mmCM1_CM_BLNDGAM_RAMB_REGION_22_23_BASE_IDX 2
#define mmCM1_CM_BLNDGAM_RAMB_REGION_24_25 0x0f37
#define mmCM1_CM_BLNDGAM_RAMB_REGION_24_25_BASE_IDX 2
#define mmCM1_CM_BLNDGAM_RAMB_REGION_26_27 0x0f38
#define mmCM1_CM_BLNDGAM_RAMB_REGION_26_27_BASE_IDX 2
#define mmCM1_CM_BLNDGAM_RAMB_REGION_28_29 0x0f39
#define mmCM1_CM_BLNDGAM_RAMB_REGION_28_29_BASE_IDX 2
#define mmCM1_CM_BLNDGAM_RAMB_REGION_30_31 0x0f3a
#define mmCM1_CM_BLNDGAM_RAMB_REGION_30_31_BASE_IDX 2
#define mmCM1_CM_BLNDGAM_RAMB_REGION_32_33 0x0f3b
#define mmCM1_CM_BLNDGAM_RAMB_REGION_32_33_BASE_IDX 2
#define mmCM1_CM_HDR_MULT_COEF 0x0f3c
#define mmCM1_CM_HDR_MULT_COEF_BASE_IDX 2
#define mmCM1_CM_MEM_PWR_CTRL 0x0f3d
#define mmCM1_CM_MEM_PWR_CTRL_BASE_IDX 2
#define mmCM1_CM_MEM_PWR_STATUS 0x0f3e
#define mmCM1_CM_MEM_PWR_STATUS_BASE_IDX 2
#define mmCM1_CM_DEALPHA 0x0f40
#define mmCM1_CM_DEALPHA_BASE_IDX 2
#define mmCM1_CM_COEF_FORMAT 0x0f41
#define mmCM1_CM_COEF_FORMAT_BASE_IDX 2
#define mmCM1_CM_SHAPER_CONTROL 0x0f42
#define mmCM1_CM_SHAPER_CONTROL_BASE_IDX 2
#define mmCM1_CM_SHAPER_OFFSET_R 0x0f43
#define mmCM1_CM_SHAPER_OFFSET_R_BASE_IDX 2
#define mmCM1_CM_SHAPER_OFFSET_G 0x0f44
#define mmCM1_CM_SHAPER_OFFSET_G_BASE_IDX 2
#define mmCM1_CM_SHAPER_OFFSET_B 0x0f45
#define mmCM1_CM_SHAPER_OFFSET_B_BASE_IDX 2
#define mmCM1_CM_SHAPER_SCALE_R 0x0f46
#define mmCM1_CM_SHAPER_SCALE_R_BASE_IDX 2
#define mmCM1_CM_SHAPER_SCALE_G_B 0x0f47
#define mmCM1_CM_SHAPER_SCALE_G_B_BASE_IDX 2
#define mmCM1_CM_SHAPER_LUT_INDEX 0x0f48
#define mmCM1_CM_SHAPER_LUT_INDEX_BASE_IDX 2
#define mmCM1_CM_SHAPER_LUT_DATA 0x0f49
#define mmCM1_CM_SHAPER_LUT_DATA_BASE_IDX 2
#define mmCM1_CM_SHAPER_LUT_WRITE_EN_MASK 0x0f4a
#define mmCM1_CM_SHAPER_LUT_WRITE_EN_MASK_BASE_IDX 2
#define mmCM1_CM_SHAPER_RAMA_START_CNTL_B 0x0f4b
#define mmCM1_CM_SHAPER_RAMA_START_CNTL_B_BASE_IDX 2
#define mmCM1_CM_SHAPER_RAMA_START_CNTL_G 0x0f4c
#define mmCM1_CM_SHAPER_RAMA_START_CNTL_G_BASE_IDX 2
#define mmCM1_CM_SHAPER_RAMA_START_CNTL_R 0x0f4d
#define mmCM1_CM_SHAPER_RAMA_START_CNTL_R_BASE_IDX 2
#define mmCM1_CM_SHAPER_RAMA_END_CNTL_B 0x0f4e
#define mmCM1_CM_SHAPER_RAMA_END_CNTL_B_BASE_IDX 2
#define mmCM1_CM_SHAPER_RAMA_END_CNTL_G 0x0f4f
#define mmCM1_CM_SHAPER_RAMA_END_CNTL_G_BASE_IDX 2
#define mmCM1_CM_SHAPER_RAMA_END_CNTL_R 0x0f50
#define mmCM1_CM_SHAPER_RAMA_END_CNTL_R_BASE_IDX 2
#define mmCM1_CM_SHAPER_RAMA_REGION_0_1 0x0f51
#define mmCM1_CM_SHAPER_RAMA_REGION_0_1_BASE_IDX 2
#define mmCM1_CM_SHAPER_RAMA_REGION_2_3 0x0f52
#define mmCM1_CM_SHAPER_RAMA_REGION_2_3_BASE_IDX 2
#define mmCM1_CM_SHAPER_RAMA_REGION_4_5 0x0f53
#define mmCM1_CM_SHAPER_RAMA_REGION_4_5_BASE_IDX 2
#define mmCM1_CM_SHAPER_RAMA_REGION_6_7 0x0f54
#define mmCM1_CM_SHAPER_RAMA_REGION_6_7_BASE_IDX 2
#define mmCM1_CM_SHAPER_RAMA_REGION_8_9 0x0f55
#define mmCM1_CM_SHAPER_RAMA_REGION_8_9_BASE_IDX 2
#define mmCM1_CM_SHAPER_RAMA_REGION_10_11 0x0f56
#define mmCM1_CM_SHAPER_RAMA_REGION_10_11_BASE_IDX 2
#define mmCM1_CM_SHAPER_RAMA_REGION_12_13 0x0f57
#define mmCM1_CM_SHAPER_RAMA_REGION_12_13_BASE_IDX 2
#define mmCM1_CM_SHAPER_RAMA_REGION_14_15 0x0f58
#define mmCM1_CM_SHAPER_RAMA_REGION_14_15_BASE_IDX 2
#define mmCM1_CM_SHAPER_RAMA_REGION_16_17 0x0f59
#define mmCM1_CM_SHAPER_RAMA_REGION_16_17_BASE_IDX 2
#define mmCM1_CM_SHAPER_RAMA_REGION_18_19 0x0f5a
#define mmCM1_CM_SHAPER_RAMA_REGION_18_19_BASE_IDX 2
#define mmCM1_CM_SHAPER_RAMA_REGION_20_21 0x0f5b
#define mmCM1_CM_SHAPER_RAMA_REGION_20_21_BASE_IDX 2
#define mmCM1_CM_SHAPER_RAMA_REGION_22_23 0x0f5c
#define mmCM1_CM_SHAPER_RAMA_REGION_22_23_BASE_IDX 2
#define mmCM1_CM_SHAPER_RAMA_REGION_24_25 0x0f5d
#define mmCM1_CM_SHAPER_RAMA_REGION_24_25_BASE_IDX 2
#define mmCM1_CM_SHAPER_RAMA_REGION_26_27 0x0f5e
#define mmCM1_CM_SHAPER_RAMA_REGION_26_27_BASE_IDX 2
#define mmCM1_CM_SHAPER_RAMA_REGION_28_29 0x0f5f
#define mmCM1_CM_SHAPER_RAMA_REGION_28_29_BASE_IDX 2
#define mmCM1_CM_SHAPER_RAMA_REGION_30_31 0x0f60
#define mmCM1_CM_SHAPER_RAMA_REGION_30_31_BASE_IDX 2
#define mmCM1_CM_SHAPER_RAMA_REGION_32_33 0x0f61
#define mmCM1_CM_SHAPER_RAMA_REGION_32_33_BASE_IDX 2
#define mmCM1_CM_SHAPER_RAMB_START_CNTL_B 0x0f62
#define mmCM1_CM_SHAPER_RAMB_START_CNTL_B_BASE_IDX 2
#define mmCM1_CM_SHAPER_RAMB_START_CNTL_G 0x0f63
#define mmCM1_CM_SHAPER_RAMB_START_CNTL_G_BASE_IDX 2
#define mmCM1_CM_SHAPER_RAMB_START_CNTL_R 0x0f64
#define mmCM1_CM_SHAPER_RAMB_START_CNTL_R_BASE_IDX 2
#define mmCM1_CM_SHAPER_RAMB_END_CNTL_B 0x0f65
#define mmCM1_CM_SHAPER_RAMB_END_CNTL_B_BASE_IDX 2
#define mmCM1_CM_SHAPER_RAMB_END_CNTL_G 0x0f66
#define mmCM1_CM_SHAPER_RAMB_END_CNTL_G_BASE_IDX 2
#define mmCM1_CM_SHAPER_RAMB_END_CNTL_R 0x0f67
#define mmCM1_CM_SHAPER_RAMB_END_CNTL_R_BASE_IDX 2
#define mmCM1_CM_SHAPER_RAMB_REGION_0_1 0x0f68
#define mmCM1_CM_SHAPER_RAMB_REGION_0_1_BASE_IDX 2
#define mmCM1_CM_SHAPER_RAMB_REGION_2_3 0x0f69
#define mmCM1_CM_SHAPER_RAMB_REGION_2_3_BASE_IDX 2
#define mmCM1_CM_SHAPER_RAMB_REGION_4_5 0x0f6a
#define mmCM1_CM_SHAPER_RAMB_REGION_4_5_BASE_IDX 2
#define mmCM1_CM_SHAPER_RAMB_REGION_6_7 0x0f6b
#define mmCM1_CM_SHAPER_RAMB_REGION_6_7_BASE_IDX 2
#define mmCM1_CM_SHAPER_RAMB_REGION_8_9 0x0f6c
#define mmCM1_CM_SHAPER_RAMB_REGION_8_9_BASE_IDX 2
#define mmCM1_CM_SHAPER_RAMB_REGION_10_11 0x0f6d
#define mmCM1_CM_SHAPER_RAMB_REGION_10_11_BASE_IDX 2
#define mmCM1_CM_SHAPER_RAMB_REGION_12_13 0x0f6e
#define mmCM1_CM_SHAPER_RAMB_REGION_12_13_BASE_IDX 2
#define mmCM1_CM_SHAPER_RAMB_REGION_14_15 0x0f6f
#define mmCM1_CM_SHAPER_RAMB_REGION_14_15_BASE_IDX 2
#define mmCM1_CM_SHAPER_RAMB_REGION_16_17 0x0f70
#define mmCM1_CM_SHAPER_RAMB_REGION_16_17_BASE_IDX 2
#define mmCM1_CM_SHAPER_RAMB_REGION_18_19 0x0f71
#define mmCM1_CM_SHAPER_RAMB_REGION_18_19_BASE_IDX 2
#define mmCM1_CM_SHAPER_RAMB_REGION_20_21 0x0f72
#define mmCM1_CM_SHAPER_RAMB_REGION_20_21_BASE_IDX 2
#define mmCM1_CM_SHAPER_RAMB_REGION_22_23 0x0f73
#define mmCM1_CM_SHAPER_RAMB_REGION_22_23_BASE_IDX 2
#define mmCM1_CM_SHAPER_RAMB_REGION_24_25 0x0f74
#define mmCM1_CM_SHAPER_RAMB_REGION_24_25_BASE_IDX 2
#define mmCM1_CM_SHAPER_RAMB_REGION_26_27 0x0f75
#define mmCM1_CM_SHAPER_RAMB_REGION_26_27_BASE_IDX 2
#define mmCM1_CM_SHAPER_RAMB_REGION_28_29 0x0f76
#define mmCM1_CM_SHAPER_RAMB_REGION_28_29_BASE_IDX 2
#define mmCM1_CM_SHAPER_RAMB_REGION_30_31 0x0f77
#define mmCM1_CM_SHAPER_RAMB_REGION_30_31_BASE_IDX 2
#define mmCM1_CM_SHAPER_RAMB_REGION_32_33 0x0f78
#define mmCM1_CM_SHAPER_RAMB_REGION_32_33_BASE_IDX 2
#define mmCM1_CM_MEM_PWR_CTRL2 0x0f79
#define mmCM1_CM_MEM_PWR_CTRL2_BASE_IDX 2
#define mmCM1_CM_MEM_PWR_STATUS2 0x0f7a
#define mmCM1_CM_MEM_PWR_STATUS2_BASE_IDX 2
#define mmCM1_CM_3DLUT_MODE 0x0f7b
#define mmCM1_CM_3DLUT_MODE_BASE_IDX 2
#define mmCM1_CM_3DLUT_INDEX 0x0f7c
#define mmCM1_CM_3DLUT_INDEX_BASE_IDX 2
#define mmCM1_CM_3DLUT_DATA 0x0f7d
#define mmCM1_CM_3DLUT_DATA_BASE_IDX 2
#define mmCM1_CM_3DLUT_DATA_30BIT 0x0f7e
#define mmCM1_CM_3DLUT_DATA_30BIT_BASE_IDX 2
#define mmCM1_CM_3DLUT_READ_WRITE_CONTROL 0x0f7f
#define mmCM1_CM_3DLUT_READ_WRITE_CONTROL_BASE_IDX 2
#define mmCM1_CM_3DLUT_OUT_NORM_FACTOR 0x0f80
#define mmCM1_CM_3DLUT_OUT_NORM_FACTOR_BASE_IDX 2
#define mmCM1_CM_3DLUT_OUT_OFFSET_R 0x0f81
#define mmCM1_CM_3DLUT_OUT_OFFSET_R_BASE_IDX 2
#define mmCM1_CM_3DLUT_OUT_OFFSET_G 0x0f82
#define mmCM1_CM_3DLUT_OUT_OFFSET_G_BASE_IDX 2
#define mmCM1_CM_3DLUT_OUT_OFFSET_B 0x0f83
#define mmCM1_CM_3DLUT_OUT_OFFSET_B_BASE_IDX 2
// addressBlock: dce_dc_dpp1_dispdec_dpp_dcperfmon_dc_perfmon_dispdec
// base address: 0x3e3c
#define mmDC_PERFMON12_PERFCOUNTER_CNTL 0x0f8f
#define mmDC_PERFMON12_PERFCOUNTER_CNTL_BASE_IDX 2
#define mmDC_PERFMON12_PERFCOUNTER_CNTL2 0x0f90
#define mmDC_PERFMON12_PERFCOUNTER_CNTL2_BASE_IDX 2
#define mmDC_PERFMON12_PERFCOUNTER_STATE 0x0f91
#define mmDC_PERFMON12_PERFCOUNTER_STATE_BASE_IDX 2
#define mmDC_PERFMON12_PERFMON_CNTL 0x0f92
#define mmDC_PERFMON12_PERFMON_CNTL_BASE_IDX 2
#define mmDC_PERFMON12_PERFMON_CNTL2 0x0f93
#define mmDC_PERFMON12_PERFMON_CNTL2_BASE_IDX 2
#define mmDC_PERFMON12_PERFMON_CVALUE_INT_MISC 0x0f94
#define mmDC_PERFMON12_PERFMON_CVALUE_INT_MISC_BASE_IDX 2
#define mmDC_PERFMON12_PERFMON_CVALUE_LOW 0x0f95
#define mmDC_PERFMON12_PERFMON_CVALUE_LOW_BASE_IDX 2
#define mmDC_PERFMON12_PERFMON_HI 0x0f96
#define mmDC_PERFMON12_PERFMON_HI_BASE_IDX 2
#define mmDC_PERFMON12_PERFMON_LOW 0x0f97
#define mmDC_PERFMON12_PERFMON_LOW_BASE_IDX 2
// addressBlock: dce_dc_dpp2_dispdec_dpp_top_dispdec
// base address: 0xb58
#define mmDPP_TOP2_DPP_CONTROL 0x0f9b
#define mmDPP_TOP2_DPP_CONTROL_BASE_IDX 2
#define mmDPP_TOP2_DPP_SOFT_RESET 0x0f9c
#define mmDPP_TOP2_DPP_SOFT_RESET_BASE_IDX 2
#define mmDPP_TOP2_DPP_CRC_VAL_R_G 0x0f9d
#define mmDPP_TOP2_DPP_CRC_VAL_R_G_BASE_IDX 2
#define mmDPP_TOP2_DPP_CRC_VAL_B_A 0x0f9e
#define mmDPP_TOP2_DPP_CRC_VAL_B_A_BASE_IDX 2
#define mmDPP_TOP2_DPP_CRC_CTRL 0x0f9f
#define mmDPP_TOP2_DPP_CRC_CTRL_BASE_IDX 2
#define mmDPP_TOP2_HOST_READ_CONTROL 0x0fa0
#define mmDPP_TOP2_HOST_READ_CONTROL_BASE_IDX 2
// addressBlock: dce_dc_dpp2_dispdec_cnvc_cfg_dispdec
// base address: 0xb58
#define mmCNVC_CFG2_CNVC_SURFACE_PIXEL_FORMAT 0x0fa5
#define mmCNVC_CFG2_CNVC_SURFACE_PIXEL_FORMAT_BASE_IDX 2
#define mmCNVC_CFG2_FORMAT_CONTROL 0x0fa6
#define mmCNVC_CFG2_FORMAT_CONTROL_BASE_IDX 2
#define mmCNVC_CFG2_FCNV_FP_BIAS_R 0x0fa7
#define mmCNVC_CFG2_FCNV_FP_BIAS_R_BASE_IDX 2
#define mmCNVC_CFG2_FCNV_FP_BIAS_G 0x0fa8
#define mmCNVC_CFG2_FCNV_FP_BIAS_G_BASE_IDX 2
#define mmCNVC_CFG2_FCNV_FP_BIAS_B 0x0fa9
#define mmCNVC_CFG2_FCNV_FP_BIAS_B_BASE_IDX 2
#define mmCNVC_CFG2_FCNV_FP_SCALE_R 0x0faa
#define mmCNVC_CFG2_FCNV_FP_SCALE_R_BASE_IDX 2
#define mmCNVC_CFG2_FCNV_FP_SCALE_G 0x0fab
#define mmCNVC_CFG2_FCNV_FP_SCALE_G_BASE_IDX 2
#define mmCNVC_CFG2_FCNV_FP_SCALE_B 0x0fac
#define mmCNVC_CFG2_FCNV_FP_SCALE_B_BASE_IDX 2
#define mmCNVC_CFG2_COLOR_KEYER_CONTROL 0x0fad
#define mmCNVC_CFG2_COLOR_KEYER_CONTROL_BASE_IDX 2
#define mmCNVC_CFG2_COLOR_KEYER_ALPHA 0x0fae
#define mmCNVC_CFG2_COLOR_KEYER_ALPHA_BASE_IDX 2
#define mmCNVC_CFG2_COLOR_KEYER_RED 0x0faf
#define mmCNVC_CFG2_COLOR_KEYER_RED_BASE_IDX 2
#define mmCNVC_CFG2_COLOR_KEYER_GREEN 0x0fb0
#define mmCNVC_CFG2_COLOR_KEYER_GREEN_BASE_IDX 2
#define mmCNVC_CFG2_COLOR_KEYER_BLUE 0x0fb1
#define mmCNVC_CFG2_COLOR_KEYER_BLUE_BASE_IDX 2
#define mmCNVC_CFG2_ALPHA_2BIT_LUT 0x0fb3
#define mmCNVC_CFG2_ALPHA_2BIT_LUT_BASE_IDX 2
#define mmCNVC_CFG2_PRE_DEALPHA 0x0fb4
#define mmCNVC_CFG2_PRE_DEALPHA_BASE_IDX 2
#define mmCNVC_CFG2_PRE_CSC_MODE 0x0fb5
#define mmCNVC_CFG2_PRE_CSC_MODE_BASE_IDX 2
#define mmCNVC_CFG2_PRE_CSC_C11_C12 0x0fb6
#define mmCNVC_CFG2_PRE_CSC_C11_C12_BASE_IDX 2
#define mmCNVC_CFG2_PRE_CSC_C13_C14 0x0fb7
#define mmCNVC_CFG2_PRE_CSC_C13_C14_BASE_IDX 2
#define mmCNVC_CFG2_PRE_CSC_C21_C22 0x0fb8
#define mmCNVC_CFG2_PRE_CSC_C21_C22_BASE_IDX 2
#define mmCNVC_CFG2_PRE_CSC_C23_C24 0x0fb9
#define mmCNVC_CFG2_PRE_CSC_C23_C24_BASE_IDX 2
#define mmCNVC_CFG2_PRE_CSC_C31_C32 0x0fba
#define mmCNVC_CFG2_PRE_CSC_C31_C32_BASE_IDX 2
#define mmCNVC_CFG2_PRE_CSC_C33_C34 0x0fbb
#define mmCNVC_CFG2_PRE_CSC_C33_C34_BASE_IDX 2
#define mmCNVC_CFG2_PRE_CSC_B_C11_C12 0x0fbc
#define mmCNVC_CFG2_PRE_CSC_B_C11_C12_BASE_IDX 2
#define mmCNVC_CFG2_PRE_CSC_B_C13_C14 0x0fbd
#define mmCNVC_CFG2_PRE_CSC_B_C13_C14_BASE_IDX 2
#define mmCNVC_CFG2_PRE_CSC_B_C21_C22 0x0fbe
#define mmCNVC_CFG2_PRE_CSC_B_C21_C22_BASE_IDX 2
#define mmCNVC_CFG2_PRE_CSC_B_C23_C24 0x0fbf
#define mmCNVC_CFG2_PRE_CSC_B_C23_C24_BASE_IDX 2
#define mmCNVC_CFG2_PRE_CSC_B_C31_C32 0x0fc0
#define mmCNVC_CFG2_PRE_CSC_B_C31_C32_BASE_IDX 2
#define mmCNVC_CFG2_PRE_CSC_B_C33_C34 0x0fc1
#define mmCNVC_CFG2_PRE_CSC_B_C33_C34_BASE_IDX 2
#define mmCNVC_CFG2_CNVC_COEF_FORMAT 0x0fc2
#define mmCNVC_CFG2_CNVC_COEF_FORMAT_BASE_IDX 2
#define mmCNVC_CFG2_PRE_DEGAM 0x0fc3
#define mmCNVC_CFG2_PRE_DEGAM_BASE_IDX 2
#define mmCNVC_CFG2_PRE_REALPHA 0x0fc4
#define mmCNVC_CFG2_PRE_REALPHA_BASE_IDX 2
// addressBlock: dce_dc_dpp2_dispdec_cnvc_cur_dispdec
// base address: 0xb58
#define mmCNVC_CUR2_CURSOR0_CONTROL 0x0fc7
#define mmCNVC_CUR2_CURSOR0_CONTROL_BASE_IDX 2
#define mmCNVC_CUR2_CURSOR0_COLOR0 0x0fc8
#define mmCNVC_CUR2_CURSOR0_COLOR0_BASE_IDX 2
#define mmCNVC_CUR2_CURSOR0_COLOR1 0x0fc9
#define mmCNVC_CUR2_CURSOR0_COLOR1_BASE_IDX 2
#define mmCNVC_CUR2_CURSOR0_FP_SCALE_BIAS 0x0fca
#define mmCNVC_CUR2_CURSOR0_FP_SCALE_BIAS_BASE_IDX 2
// addressBlock: dce_dc_dpp2_dispdec_dscl_dispdec
// base address: 0xb58
#define mmDSCL2_SCL_COEF_RAM_TAP_SELECT 0x0fcf
#define mmDSCL2_SCL_COEF_RAM_TAP_SELECT_BASE_IDX 2
#define mmDSCL2_SCL_COEF_RAM_TAP_DATA 0x0fd0
#define mmDSCL2_SCL_COEF_RAM_TAP_DATA_BASE_IDX 2
#define mmDSCL2_SCL_MODE 0x0fd1
#define mmDSCL2_SCL_MODE_BASE_IDX 2
#define mmDSCL2_SCL_TAP_CONTROL 0x0fd2
#define mmDSCL2_SCL_TAP_CONTROL_BASE_IDX 2
#define mmDSCL2_DSCL_CONTROL 0x0fd3
#define mmDSCL2_DSCL_CONTROL_BASE_IDX 2
#define mmDSCL2_DSCL_2TAP_CONTROL 0x0fd4
#define mmDSCL2_DSCL_2TAP_CONTROL_BASE_IDX 2
#define mmDSCL2_SCL_MANUAL_REPLICATE_CONTROL 0x0fd5
#define mmDSCL2_SCL_MANUAL_REPLICATE_CONTROL_BASE_IDX 2
#define mmDSCL2_SCL_HORZ_FILTER_SCALE_RATIO 0x0fd6
#define mmDSCL2_SCL_HORZ_FILTER_SCALE_RATIO_BASE_IDX 2
#define mmDSCL2_SCL_HORZ_FILTER_INIT 0x0fd7
#define mmDSCL2_SCL_HORZ_FILTER_INIT_BASE_IDX 2
#define mmDSCL2_SCL_HORZ_FILTER_SCALE_RATIO_C 0x0fd8
#define mmDSCL2_SCL_HORZ_FILTER_SCALE_RATIO_C_BASE_IDX 2
#define mmDSCL2_SCL_HORZ_FILTER_INIT_C 0x0fd9
#define mmDSCL2_SCL_HORZ_FILTER_INIT_C_BASE_IDX 2
#define mmDSCL2_SCL_VERT_FILTER_SCALE_RATIO 0x0fda
#define mmDSCL2_SCL_VERT_FILTER_SCALE_RATIO_BASE_IDX 2
#define mmDSCL2_SCL_VERT_FILTER_INIT 0x0fdb
#define mmDSCL2_SCL_VERT_FILTER_INIT_BASE_IDX 2
#define mmDSCL2_SCL_VERT_FILTER_INIT_BOT 0x0fdc
#define mmDSCL2_SCL_VERT_FILTER_INIT_BOT_BASE_IDX 2
#define mmDSCL2_SCL_VERT_FILTER_SCALE_RATIO_C 0x0fdd
#define mmDSCL2_SCL_VERT_FILTER_SCALE_RATIO_C_BASE_IDX 2
#define mmDSCL2_SCL_VERT_FILTER_INIT_C 0x0fde
#define mmDSCL2_SCL_VERT_FILTER_INIT_C_BASE_IDX 2
#define mmDSCL2_SCL_VERT_FILTER_INIT_BOT_C 0x0fdf
#define mmDSCL2_SCL_VERT_FILTER_INIT_BOT_C_BASE_IDX 2
#define mmDSCL2_SCL_BLACK_COLOR 0x0fe0
#define mmDSCL2_SCL_BLACK_COLOR_BASE_IDX 2
#define mmDSCL2_DSCL_UPDATE 0x0fe1
#define mmDSCL2_DSCL_UPDATE_BASE_IDX 2
#define mmDSCL2_DSCL_AUTOCAL 0x0fe2
#define mmDSCL2_DSCL_AUTOCAL_BASE_IDX 2
#define mmDSCL2_DSCL_EXT_OVERSCAN_LEFT_RIGHT 0x0fe3
#define mmDSCL2_DSCL_EXT_OVERSCAN_LEFT_RIGHT_BASE_IDX 2
#define mmDSCL2_DSCL_EXT_OVERSCAN_TOP_BOTTOM 0x0fe4
#define mmDSCL2_DSCL_EXT_OVERSCAN_TOP_BOTTOM_BASE_IDX 2
#define mmDSCL2_OTG_H_BLANK 0x0fe5
#define mmDSCL2_OTG_H_BLANK_BASE_IDX 2
#define mmDSCL2_OTG_V_BLANK 0x0fe6
#define mmDSCL2_OTG_V_BLANK_BASE_IDX 2
#define mmDSCL2_RECOUT_START 0x0fe7
#define mmDSCL2_RECOUT_START_BASE_IDX 2
#define mmDSCL2_RECOUT_SIZE 0x0fe8
#define mmDSCL2_RECOUT_SIZE_BASE_IDX 2
#define mmDSCL2_MPC_SIZE 0x0fe9
#define mmDSCL2_MPC_SIZE_BASE_IDX 2
#define mmDSCL2_LB_DATA_FORMAT 0x0fea
#define mmDSCL2_LB_DATA_FORMAT_BASE_IDX 2
#define mmDSCL2_LB_MEMORY_CTRL 0x0feb
#define mmDSCL2_LB_MEMORY_CTRL_BASE_IDX 2
#define mmDSCL2_LB_V_COUNTER 0x0fec
#define mmDSCL2_LB_V_COUNTER_BASE_IDX 2
#define mmDSCL2_DSCL_MEM_PWR_CTRL 0x0fed
#define mmDSCL2_DSCL_MEM_PWR_CTRL_BASE_IDX 2
#define mmDSCL2_DSCL_MEM_PWR_STATUS 0x0fee
#define mmDSCL2_DSCL_MEM_PWR_STATUS_BASE_IDX 2
#define mmDSCL2_OBUF_CONTROL 0x0fef
#define mmDSCL2_OBUF_CONTROL_BASE_IDX 2
#define mmDSCL2_OBUF_MEM_PWR_CTRL 0x0ff0
#define mmDSCL2_OBUF_MEM_PWR_CTRL_BASE_IDX 2
// addressBlock: dce_dc_dpp2_dispdec_cm_dispdec
// base address: 0xb58
#define mmCM2_CM_CONTROL 0x0ff6
#define mmCM2_CM_CONTROL_BASE_IDX 2
#define mmCM2_CM_POST_CSC_CONTROL 0x0ff7
#define mmCM2_CM_POST_CSC_CONTROL_BASE_IDX 2
#define mmCM2_CM_POST_CSC_C11_C12 0x0ff8
#define mmCM2_CM_POST_CSC_C11_C12_BASE_IDX 2
#define mmCM2_CM_POST_CSC_C13_C14 0x0ff9
#define mmCM2_CM_POST_CSC_C13_C14_BASE_IDX 2
#define mmCM2_CM_POST_CSC_C21_C22 0x0ffa
#define mmCM2_CM_POST_CSC_C21_C22_BASE_IDX 2
#define mmCM2_CM_POST_CSC_C23_C24 0x0ffb
#define mmCM2_CM_POST_CSC_C23_C24_BASE_IDX 2
#define mmCM2_CM_POST_CSC_C31_C32 0x0ffc
#define mmCM2_CM_POST_CSC_C31_C32_BASE_IDX 2
#define mmCM2_CM_POST_CSC_C33_C34 0x0ffd
#define mmCM2_CM_POST_CSC_C33_C34_BASE_IDX 2
#define mmCM2_CM_POST_CSC_B_C11_C12 0x0ffe
#define mmCM2_CM_POST_CSC_B_C11_C12_BASE_IDX 2
#define mmCM2_CM_POST_CSC_B_C13_C14 0x0fff
#define mmCM2_CM_POST_CSC_B_C13_C14_BASE_IDX 2
#define mmCM2_CM_POST_CSC_B_C21_C22 0x1000
#define mmCM2_CM_POST_CSC_B_C21_C22_BASE_IDX 2
#define mmCM2_CM_POST_CSC_B_C23_C24 0x1001
#define mmCM2_CM_POST_CSC_B_C23_C24_BASE_IDX 2
#define mmCM2_CM_POST_CSC_B_C31_C32 0x1002
#define mmCM2_CM_POST_CSC_B_C31_C32_BASE_IDX 2
#define mmCM2_CM_POST_CSC_B_C33_C34 0x1003
#define mmCM2_CM_POST_CSC_B_C33_C34_BASE_IDX 2
#define mmCM2_CM_GAMUT_REMAP_CONTROL 0x1004
#define mmCM2_CM_GAMUT_REMAP_CONTROL_BASE_IDX 2
#define mmCM2_CM_GAMUT_REMAP_C11_C12 0x1005
#define mmCM2_CM_GAMUT_REMAP_C11_C12_BASE_IDX 2
#define mmCM2_CM_GAMUT_REMAP_C13_C14 0x1006
#define mmCM2_CM_GAMUT_REMAP_C13_C14_BASE_IDX 2
#define mmCM2_CM_GAMUT_REMAP_C21_C22 0x1007
#define mmCM2_CM_GAMUT_REMAP_C21_C22_BASE_IDX 2
#define mmCM2_CM_GAMUT_REMAP_C23_C24 0x1008
#define mmCM2_CM_GAMUT_REMAP_C23_C24_BASE_IDX 2
#define mmCM2_CM_GAMUT_REMAP_C31_C32 0x1009
#define mmCM2_CM_GAMUT_REMAP_C31_C32_BASE_IDX 2
#define mmCM2_CM_GAMUT_REMAP_C33_C34 0x100a
#define mmCM2_CM_GAMUT_REMAP_C33_C34_BASE_IDX 2
#define mmCM2_CM_GAMUT_REMAP_B_C11_C12 0x100b
#define mmCM2_CM_GAMUT_REMAP_B_C11_C12_BASE_IDX 2
#define mmCM2_CM_GAMUT_REMAP_B_C13_C14 0x100c
#define mmCM2_CM_GAMUT_REMAP_B_C13_C14_BASE_IDX 2
#define mmCM2_CM_GAMUT_REMAP_B_C21_C22 0x100d
#define mmCM2_CM_GAMUT_REMAP_B_C21_C22_BASE_IDX 2
#define mmCM2_CM_GAMUT_REMAP_B_C23_C24 0x100e
#define mmCM2_CM_GAMUT_REMAP_B_C23_C24_BASE_IDX 2
#define mmCM2_CM_GAMUT_REMAP_B_C31_C32 0x100f
#define mmCM2_CM_GAMUT_REMAP_B_C31_C32_BASE_IDX 2
#define mmCM2_CM_GAMUT_REMAP_B_C33_C34 0x1010
#define mmCM2_CM_GAMUT_REMAP_B_C33_C34_BASE_IDX 2
#define mmCM2_CM_BIAS_CR_R 0x1011
#define mmCM2_CM_BIAS_CR_R_BASE_IDX 2
#define mmCM2_CM_BIAS_Y_G_CB_B 0x1012
#define mmCM2_CM_BIAS_Y_G_CB_B_BASE_IDX 2
#define mmCM2_CM_GAMCOR_CONTROL 0x1013
#define mmCM2_CM_GAMCOR_CONTROL_BASE_IDX 2
#define mmCM2_CM_GAMCOR_LUT_INDEX 0x1014
#define mmCM2_CM_GAMCOR_LUT_INDEX_BASE_IDX 2
#define mmCM2_CM_GAMCOR_LUT_DATA 0x1015
#define mmCM2_CM_GAMCOR_LUT_DATA_BASE_IDX 2
#define mmCM2_CM_GAMCOR_LUT_CONTROL 0x1016
#define mmCM2_CM_GAMCOR_LUT_CONTROL_BASE_IDX 2
#define mmCM2_CM_GAMCOR_RAMA_START_CNTL_B 0x1017
#define mmCM2_CM_GAMCOR_RAMA_START_CNTL_B_BASE_IDX 2
#define mmCM2_CM_GAMCOR_RAMA_START_CNTL_G 0x1018
#define mmCM2_CM_GAMCOR_RAMA_START_CNTL_G_BASE_IDX 2
#define mmCM2_CM_GAMCOR_RAMA_START_CNTL_R 0x1019
#define mmCM2_CM_GAMCOR_RAMA_START_CNTL_R_BASE_IDX 2
#define mmCM2_CM_GAMCOR_RAMA_START_SLOPE_CNTL_B 0x101a
#define mmCM2_CM_GAMCOR_RAMA_START_SLOPE_CNTL_B_BASE_IDX 2
#define mmCM2_CM_GAMCOR_RAMA_START_SLOPE_CNTL_G 0x101b
#define mmCM2_CM_GAMCOR_RAMA_START_SLOPE_CNTL_G_BASE_IDX 2
#define mmCM2_CM_GAMCOR_RAMA_START_SLOPE_CNTL_R 0x101c
#define mmCM2_CM_GAMCOR_RAMA_START_SLOPE_CNTL_R_BASE_IDX 2
#define mmCM2_CM_GAMCOR_RAMA_START_BASE_CNTL_B 0x101d
#define mmCM2_CM_GAMCOR_RAMA_START_BASE_CNTL_B_BASE_IDX 2
#define mmCM2_CM_GAMCOR_RAMA_START_BASE_CNTL_G 0x101e
#define mmCM2_CM_GAMCOR_RAMA_START_BASE_CNTL_G_BASE_IDX 2
#define mmCM2_CM_GAMCOR_RAMA_START_BASE_CNTL_R 0x101f
#define mmCM2_CM_GAMCOR_RAMA_START_BASE_CNTL_R_BASE_IDX 2
#define mmCM2_CM_GAMCOR_RAMA_END_CNTL1_B 0x1020
#define mmCM2_CM_GAMCOR_RAMA_END_CNTL1_B_BASE_IDX 2
#define mmCM2_CM_GAMCOR_RAMA_END_CNTL2_B 0x1021
#define mmCM2_CM_GAMCOR_RAMA_END_CNTL2_B_BASE_IDX 2
#define mmCM2_CM_GAMCOR_RAMA_END_CNTL1_G 0x1022
#define mmCM2_CM_GAMCOR_RAMA_END_CNTL1_G_BASE_IDX 2
#define mmCM2_CM_GAMCOR_RAMA_END_CNTL2_G 0x1023
#define mmCM2_CM_GAMCOR_RAMA_END_CNTL2_G_BASE_IDX 2
#define mmCM2_CM_GAMCOR_RAMA_END_CNTL1_R 0x1024
#define mmCM2_CM_GAMCOR_RAMA_END_CNTL1_R_BASE_IDX 2
#define mmCM2_CM_GAMCOR_RAMA_END_CNTL2_R 0x1025
#define mmCM2_CM_GAMCOR_RAMA_END_CNTL2_R_BASE_IDX 2
#define mmCM2_CM_GAMCOR_RAMA_OFFSET_B 0x1026
#define mmCM2_CM_GAMCOR_RAMA_OFFSET_B_BASE_IDX 2
#define mmCM2_CM_GAMCOR_RAMA_OFFSET_G 0x1027
#define mmCM2_CM_GAMCOR_RAMA_OFFSET_G_BASE_IDX 2
#define mmCM2_CM_GAMCOR_RAMA_OFFSET_R 0x1028
#define mmCM2_CM_GAMCOR_RAMA_OFFSET_R_BASE_IDX 2
#define mmCM2_CM_GAMCOR_RAMA_REGION_0_1 0x1029
#define mmCM2_CM_GAMCOR_RAMA_REGION_0_1_BASE_IDX 2
#define mmCM2_CM_GAMCOR_RAMA_REGION_2_3 0x102a
#define mmCM2_CM_GAMCOR_RAMA_REGION_2_3_BASE_IDX 2
#define mmCM2_CM_GAMCOR_RAMA_REGION_4_5 0x102b
#define mmCM2_CM_GAMCOR_RAMA_REGION_4_5_BASE_IDX 2
#define mmCM2_CM_GAMCOR_RAMA_REGION_6_7 0x102c
#define mmCM2_CM_GAMCOR_RAMA_REGION_6_7_BASE_IDX 2
#define mmCM2_CM_GAMCOR_RAMA_REGION_8_9 0x102d
#define mmCM2_CM_GAMCOR_RAMA_REGION_8_9_BASE_IDX 2
#define mmCM2_CM_GAMCOR_RAMA_REGION_10_11 0x102e
#define mmCM2_CM_GAMCOR_RAMA_REGION_10_11_BASE_IDX 2
#define mmCM2_CM_GAMCOR_RAMA_REGION_12_13 0x102f
#define mmCM2_CM_GAMCOR_RAMA_REGION_12_13_BASE_IDX 2
#define mmCM2_CM_GAMCOR_RAMA_REGION_14_15 0x1030
#define mmCM2_CM_GAMCOR_RAMA_REGION_14_15_BASE_IDX 2
#define mmCM2_CM_GAMCOR_RAMA_REGION_16_17 0x1031
#define mmCM2_CM_GAMCOR_RAMA_REGION_16_17_BASE_IDX 2
#define mmCM2_CM_GAMCOR_RAMA_REGION_18_19 0x1032
#define mmCM2_CM_GAMCOR_RAMA_REGION_18_19_BASE_IDX 2
#define mmCM2_CM_GAMCOR_RAMA_REGION_20_21 0x1033
#define mmCM2_CM_GAMCOR_RAMA_REGION_20_21_BASE_IDX 2
#define mmCM2_CM_GAMCOR_RAMA_REGION_22_23 0x1034
#define mmCM2_CM_GAMCOR_RAMA_REGION_22_23_BASE_IDX 2
#define mmCM2_CM_GAMCOR_RAMA_REGION_24_25 0x1035
#define mmCM2_CM_GAMCOR_RAMA_REGION_24_25_BASE_IDX 2
#define mmCM2_CM_GAMCOR_RAMA_REGION_26_27 0x1036
#define mmCM2_CM_GAMCOR_RAMA_REGION_26_27_BASE_IDX 2
#define mmCM2_CM_GAMCOR_RAMA_REGION_28_29 0x1037
#define mmCM2_CM_GAMCOR_RAMA_REGION_28_29_BASE_IDX 2
#define mmCM2_CM_GAMCOR_RAMA_REGION_30_31 0x1038
#define mmCM2_CM_GAMCOR_RAMA_REGION_30_31_BASE_IDX 2
#define mmCM2_CM_GAMCOR_RAMA_REGION_32_33 0x1039
#define mmCM2_CM_GAMCOR_RAMA_REGION_32_33_BASE_IDX 2
#define mmCM2_CM_GAMCOR_RAMB_START_CNTL_B 0x103a
#define mmCM2_CM_GAMCOR_RAMB_START_CNTL_B_BASE_IDX 2
#define mmCM2_CM_GAMCOR_RAMB_START_CNTL_G 0x103b
#define mmCM2_CM_GAMCOR_RAMB_START_CNTL_G_BASE_IDX 2
#define mmCM2_CM_GAMCOR_RAMB_START_CNTL_R 0x103c
#define mmCM2_CM_GAMCOR_RAMB_START_CNTL_R_BASE_IDX 2
#define mmCM2_CM_GAMCOR_RAMB_START_SLOPE_CNTL_B 0x103d
#define mmCM2_CM_GAMCOR_RAMB_START_SLOPE_CNTL_B_BASE_IDX 2
#define mmCM2_CM_GAMCOR_RAMB_START_SLOPE_CNTL_G 0x103e
#define mmCM2_CM_GAMCOR_RAMB_START_SLOPE_CNTL_G_BASE_IDX 2
#define mmCM2_CM_GAMCOR_RAMB_START_SLOPE_CNTL_R 0x103f
#define mmCM2_CM_GAMCOR_RAMB_START_SLOPE_CNTL_R_BASE_IDX 2
#define mmCM2_CM_GAMCOR_RAMB_START_BASE_CNTL_B 0x1040
#define mmCM2_CM_GAMCOR_RAMB_START_BASE_CNTL_B_BASE_IDX 2
#define mmCM2_CM_GAMCOR_RAMB_START_BASE_CNTL_G 0x1041
#define mmCM2_CM_GAMCOR_RAMB_START_BASE_CNTL_G_BASE_IDX 2
#define mmCM2_CM_GAMCOR_RAMB_START_BASE_CNTL_R 0x1042
#define mmCM2_CM_GAMCOR_RAMB_START_BASE_CNTL_R_BASE_IDX 2
#define mmCM2_CM_GAMCOR_RAMB_END_CNTL1_B 0x1043
#define mmCM2_CM_GAMCOR_RAMB_END_CNTL1_B_BASE_IDX 2
#define mmCM2_CM_GAMCOR_RAMB_END_CNTL2_B 0x1044
#define mmCM2_CM_GAMCOR_RAMB_END_CNTL2_B_BASE_IDX 2
#define mmCM2_CM_GAMCOR_RAMB_END_CNTL1_G 0x1045
#define mmCM2_CM_GAMCOR_RAMB_END_CNTL1_G_BASE_IDX 2
#define mmCM2_CM_GAMCOR_RAMB_END_CNTL2_G 0x1046
#define mmCM2_CM_GAMCOR_RAMB_END_CNTL2_G_BASE_IDX 2
#define mmCM2_CM_GAMCOR_RAMB_END_CNTL1_R 0x1047
#define mmCM2_CM_GAMCOR_RAMB_END_CNTL1_R_BASE_IDX 2
#define mmCM2_CM_GAMCOR_RAMB_END_CNTL2_R 0x1048
#define mmCM2_CM_GAMCOR_RAMB_END_CNTL2_R_BASE_IDX 2
#define mmCM2_CM_GAMCOR_RAMB_OFFSET_B 0x1049
#define mmCM2_CM_GAMCOR_RAMB_OFFSET_B_BASE_IDX 2
#define mmCM2_CM_GAMCOR_RAMB_OFFSET_G 0x104a
#define mmCM2_CM_GAMCOR_RAMB_OFFSET_G_BASE_IDX 2
#define mmCM2_CM_GAMCOR_RAMB_OFFSET_R 0x104b
#define mmCM2_CM_GAMCOR_RAMB_OFFSET_R_BASE_IDX 2
#define mmCM2_CM_GAMCOR_RAMB_REGION_0_1 0x104c
#define mmCM2_CM_GAMCOR_RAMB_REGION_0_1_BASE_IDX 2
#define mmCM2_CM_GAMCOR_RAMB_REGION_2_3 0x104d
#define mmCM2_CM_GAMCOR_RAMB_REGION_2_3_BASE_IDX 2
#define mmCM2_CM_GAMCOR_RAMB_REGION_4_5 0x104e
#define mmCM2_CM_GAMCOR_RAMB_REGION_4_5_BASE_IDX 2
#define mmCM2_CM_GAMCOR_RAMB_REGION_6_7 0x104f
#define mmCM2_CM_GAMCOR_RAMB_REGION_6_7_BASE_IDX 2
#define mmCM2_CM_GAMCOR_RAMB_REGION_8_9 0x1050
#define mmCM2_CM_GAMCOR_RAMB_REGION_8_9_BASE_IDX 2
#define mmCM2_CM_GAMCOR_RAMB_REGION_10_11 0x1051
#define mmCM2_CM_GAMCOR_RAMB_REGION_10_11_BASE_IDX 2
#define mmCM2_CM_GAMCOR_RAMB_REGION_12_13 0x1052
#define mmCM2_CM_GAMCOR_RAMB_REGION_12_13_BASE_IDX 2
#define mmCM2_CM_GAMCOR_RAMB_REGION_14_15 0x1053
#define mmCM2_CM_GAMCOR_RAMB_REGION_14_15_BASE_IDX 2
#define mmCM2_CM_GAMCOR_RAMB_REGION_16_17 0x1054
#define mmCM2_CM_GAMCOR_RAMB_REGION_16_17_BASE_IDX 2
#define mmCM2_CM_GAMCOR_RAMB_REGION_18_19 0x1055
#define mmCM2_CM_GAMCOR_RAMB_REGION_18_19_BASE_IDX 2
#define mmCM2_CM_GAMCOR_RAMB_REGION_20_21 0x1056
#define mmCM2_CM_GAMCOR_RAMB_REGION_20_21_BASE_IDX 2
#define mmCM2_CM_GAMCOR_RAMB_REGION_22_23 0x1057
#define mmCM2_CM_GAMCOR_RAMB_REGION_22_23_BASE_IDX 2
#define mmCM2_CM_GAMCOR_RAMB_REGION_24_25 0x1058
#define mmCM2_CM_GAMCOR_RAMB_REGION_24_25_BASE_IDX 2
#define mmCM2_CM_GAMCOR_RAMB_REGION_26_27 0x1059
#define mmCM2_CM_GAMCOR_RAMB_REGION_26_27_BASE_IDX 2
#define mmCM2_CM_GAMCOR_RAMB_REGION_28_29 0x105a
#define mmCM2_CM_GAMCOR_RAMB_REGION_28_29_BASE_IDX 2
#define mmCM2_CM_GAMCOR_RAMB_REGION_30_31 0x105b
#define mmCM2_CM_GAMCOR_RAMB_REGION_30_31_BASE_IDX 2
#define mmCM2_CM_GAMCOR_RAMB_REGION_32_33 0x105c
#define mmCM2_CM_GAMCOR_RAMB_REGION_32_33_BASE_IDX 2
#define mmCM2_CM_BLNDGAM_CONTROL 0x105d
#define mmCM2_CM_BLNDGAM_CONTROL_BASE_IDX 2
#define mmCM2_CM_BLNDGAM_LUT_INDEX 0x105e
#define mmCM2_CM_BLNDGAM_LUT_INDEX_BASE_IDX 2
#define mmCM2_CM_BLNDGAM_LUT_DATA 0x105f
#define mmCM2_CM_BLNDGAM_LUT_DATA_BASE_IDX 2
#define mmCM2_CM_BLNDGAM_LUT_CONTROL 0x1060
#define mmCM2_CM_BLNDGAM_LUT_CONTROL_BASE_IDX 2
#define mmCM2_CM_BLNDGAM_RAMA_START_CNTL_B 0x1061
#define mmCM2_CM_BLNDGAM_RAMA_START_CNTL_B_BASE_IDX 2
#define mmCM2_CM_BLNDGAM_RAMA_START_CNTL_G 0x1062
#define mmCM2_CM_BLNDGAM_RAMA_START_CNTL_G_BASE_IDX 2
#define mmCM2_CM_BLNDGAM_RAMA_START_CNTL_R 0x1063
#define mmCM2_CM_BLNDGAM_RAMA_START_CNTL_R_BASE_IDX 2
#define mmCM2_CM_BLNDGAM_RAMA_START_SLOPE_CNTL_B 0x1064
#define mmCM2_CM_BLNDGAM_RAMA_START_SLOPE_CNTL_B_BASE_IDX 2
#define mmCM2_CM_BLNDGAM_RAMA_START_SLOPE_CNTL_G 0x1065
#define mmCM2_CM_BLNDGAM_RAMA_START_SLOPE_CNTL_G_BASE_IDX 2
#define mmCM2_CM_BLNDGAM_RAMA_START_SLOPE_CNTL_R 0x1066
#define mmCM2_CM_BLNDGAM_RAMA_START_SLOPE_CNTL_R_BASE_IDX 2
#define mmCM2_CM_BLNDGAM_RAMA_START_BASE_CNTL_B 0x1067
#define mmCM2_CM_BLNDGAM_RAMA_START_BASE_CNTL_B_BASE_IDX 2
#define mmCM2_CM_BLNDGAM_RAMA_START_BASE_CNTL_G 0x1068
#define mmCM2_CM_BLNDGAM_RAMA_START_BASE_CNTL_G_BASE_IDX 2
#define mmCM2_CM_BLNDGAM_RAMA_START_BASE_CNTL_R 0x1069
#define mmCM2_CM_BLNDGAM_RAMA_START_BASE_CNTL_R_BASE_IDX 2
#define mmCM2_CM_BLNDGAM_RAMA_END_CNTL1_B 0x106a
#define mmCM2_CM_BLNDGAM_RAMA_END_CNTL1_B_BASE_IDX 2
#define mmCM2_CM_BLNDGAM_RAMA_END_CNTL2_B 0x106b
#define mmCM2_CM_BLNDGAM_RAMA_END_CNTL2_B_BASE_IDX 2
#define mmCM2_CM_BLNDGAM_RAMA_END_CNTL1_G 0x106c
#define mmCM2_CM_BLNDGAM_RAMA_END_CNTL1_G_BASE_IDX 2
#define mmCM2_CM_BLNDGAM_RAMA_END_CNTL2_G 0x106d
#define mmCM2_CM_BLNDGAM_RAMA_END_CNTL2_G_BASE_IDX 2
#define mmCM2_CM_BLNDGAM_RAMA_END_CNTL1_R 0x106e
#define mmCM2_CM_BLNDGAM_RAMA_END_CNTL1_R_BASE_IDX 2
#define mmCM2_CM_BLNDGAM_RAMA_END_CNTL2_R 0x106f
#define mmCM2_CM_BLNDGAM_RAMA_END_CNTL2_R_BASE_IDX 2
#define mmCM2_CM_BLNDGAM_RAMA_OFFSET_B 0x1070
#define mmCM2_CM_BLNDGAM_RAMA_OFFSET_B_BASE_IDX 2
#define mmCM2_CM_BLNDGAM_RAMA_OFFSET_G 0x1071
#define mmCM2_CM_BLNDGAM_RAMA_OFFSET_G_BASE_IDX 2
#define mmCM2_CM_BLNDGAM_RAMA_OFFSET_R 0x1072
#define mmCM2_CM_BLNDGAM_RAMA_OFFSET_R_BASE_IDX 2
#define mmCM2_CM_BLNDGAM_RAMA_REGION_0_1 0x1073
#define mmCM2_CM_BLNDGAM_RAMA_REGION_0_1_BASE_IDX 2
#define mmCM2_CM_BLNDGAM_RAMA_REGION_2_3 0x1074
#define mmCM2_CM_BLNDGAM_RAMA_REGION_2_3_BASE_IDX 2
#define mmCM2_CM_BLNDGAM_RAMA_REGION_4_5 0x1075
#define mmCM2_CM_BLNDGAM_RAMA_REGION_4_5_BASE_IDX 2
#define mmCM2_CM_BLNDGAM_RAMA_REGION_6_7 0x1076
#define mmCM2_CM_BLNDGAM_RAMA_REGION_6_7_BASE_IDX 2
#define mmCM2_CM_BLNDGAM_RAMA_REGION_8_9 0x1077
#define mmCM2_CM_BLNDGAM_RAMA_REGION_8_9_BASE_IDX 2
#define mmCM2_CM_BLNDGAM_RAMA_REGION_10_11 0x1078
#define mmCM2_CM_BLNDGAM_RAMA_REGION_10_11_BASE_IDX 2
#define mmCM2_CM_BLNDGAM_RAMA_REGION_12_13 0x1079
#define mmCM2_CM_BLNDGAM_RAMA_REGION_12_13_BASE_IDX 2
#define mmCM2_CM_BLNDGAM_RAMA_REGION_14_15 0x107a
#define mmCM2_CM_BLNDGAM_RAMA_REGION_14_15_BASE_IDX 2
#define mmCM2_CM_BLNDGAM_RAMA_REGION_16_17 0x107b
#define mmCM2_CM_BLNDGAM_RAMA_REGION_16_17_BASE_IDX 2
#define mmCM2_CM_BLNDGAM_RAMA_REGION_18_19 0x107c
#define mmCM2_CM_BLNDGAM_RAMA_REGION_18_19_BASE_IDX 2
#define mmCM2_CM_BLNDGAM_RAMA_REGION_20_21 0x107d
#define mmCM2_CM_BLNDGAM_RAMA_REGION_20_21_BASE_IDX 2
#define mmCM2_CM_BLNDGAM_RAMA_REGION_22_23 0x107e
#define mmCM2_CM_BLNDGAM_RAMA_REGION_22_23_BASE_IDX 2
#define mmCM2_CM_BLNDGAM_RAMA_REGION_24_25 0x107f
#define mmCM2_CM_BLNDGAM_RAMA_REGION_24_25_BASE_IDX 2
#define mmCM2_CM_BLNDGAM_RAMA_REGION_26_27 0x1080
#define mmCM2_CM_BLNDGAM_RAMA_REGION_26_27_BASE_IDX 2
#define mmCM2_CM_BLNDGAM_RAMA_REGION_28_29 0x1081
#define mmCM2_CM_BLNDGAM_RAMA_REGION_28_29_BASE_IDX 2
#define mmCM2_CM_BLNDGAM_RAMA_REGION_30_31 0x1082
#define mmCM2_CM_BLNDGAM_RAMA_REGION_30_31_BASE_IDX 2
#define mmCM2_CM_BLNDGAM_RAMA_REGION_32_33 0x1083
#define mmCM2_CM_BLNDGAM_RAMA_REGION_32_33_BASE_IDX 2
#define mmCM2_CM_BLNDGAM_RAMB_START_CNTL_B 0x1084
#define mmCM2_CM_BLNDGAM_RAMB_START_CNTL_B_BASE_IDX 2
#define mmCM2_CM_BLNDGAM_RAMB_START_CNTL_G 0x1085
#define mmCM2_CM_BLNDGAM_RAMB_START_CNTL_G_BASE_IDX 2
#define mmCM2_CM_BLNDGAM_RAMB_START_CNTL_R 0x1086
#define mmCM2_CM_BLNDGAM_RAMB_START_CNTL_R_BASE_IDX 2
#define mmCM2_CM_BLNDGAM_RAMB_START_SLOPE_CNTL_B 0x1087
#define mmCM2_CM_BLNDGAM_RAMB_START_SLOPE_CNTL_B_BASE_IDX 2
#define mmCM2_CM_BLNDGAM_RAMB_START_SLOPE_CNTL_G 0x1088
#define mmCM2_CM_BLNDGAM_RAMB_START_SLOPE_CNTL_G_BASE_IDX 2
#define mmCM2_CM_BLNDGAM_RAMB_START_SLOPE_CNTL_R 0x1089
#define mmCM2_CM_BLNDGAM_RAMB_START_SLOPE_CNTL_R_BASE_IDX 2
#define mmCM2_CM_BLNDGAM_RAMB_START_BASE_CNTL_B 0x108a
#define mmCM2_CM_BLNDGAM_RAMB_START_BASE_CNTL_B_BASE_IDX 2
#define mmCM2_CM_BLNDGAM_RAMB_START_BASE_CNTL_G 0x108b
#define mmCM2_CM_BLNDGAM_RAMB_START_BASE_CNTL_G_BASE_IDX 2
#define mmCM2_CM_BLNDGAM_RAMB_START_BASE_CNTL_R 0x108c
#define mmCM2_CM_BLNDGAM_RAMB_START_BASE_CNTL_R_BASE_IDX 2
#define mmCM2_CM_BLNDGAM_RAMB_END_CNTL1_B 0x108d
#define mmCM2_CM_BLNDGAM_RAMB_END_CNTL1_B_BASE_IDX 2
#define mmCM2_CM_BLNDGAM_RAMB_END_CNTL2_B 0x108e
#define mmCM2_CM_BLNDGAM_RAMB_END_CNTL2_B_BASE_IDX 2
#define mmCM2_CM_BLNDGAM_RAMB_END_CNTL1_G 0x108f
#define mmCM2_CM_BLNDGAM_RAMB_END_CNTL1_G_BASE_IDX 2
#define mmCM2_CM_BLNDGAM_RAMB_END_CNTL2_G 0x1090
#define mmCM2_CM_BLNDGAM_RAMB_END_CNTL2_G_BASE_IDX 2
#define mmCM2_CM_BLNDGAM_RAMB_END_CNTL1_R 0x1091
#define mmCM2_CM_BLNDGAM_RAMB_END_CNTL1_R_BASE_IDX 2
#define mmCM2_CM_BLNDGAM_RAMB_END_CNTL2_R 0x1092
#define mmCM2_CM_BLNDGAM_RAMB_END_CNTL2_R_BASE_IDX 2
#define mmCM2_CM_BLNDGAM_RAMB_OFFSET_B 0x1093
#define mmCM2_CM_BLNDGAM_RAMB_OFFSET_B_BASE_IDX 2
#define mmCM2_CM_BLNDGAM_RAMB_OFFSET_G 0x1094
#define mmCM2_CM_BLNDGAM_RAMB_OFFSET_G_BASE_IDX 2
#define mmCM2_CM_BLNDGAM_RAMB_OFFSET_R 0x1095
#define mmCM2_CM_BLNDGAM_RAMB_OFFSET_R_BASE_IDX 2
#define mmCM2_CM_BLNDGAM_RAMB_REGION_0_1 0x1096
#define mmCM2_CM_BLNDGAM_RAMB_REGION_0_1_BASE_IDX 2
#define mmCM2_CM_BLNDGAM_RAMB_REGION_2_3 0x1097
#define mmCM2_CM_BLNDGAM_RAMB_REGION_2_3_BASE_IDX 2
#define mmCM2_CM_BLNDGAM_RAMB_REGION_4_5 0x1098
#define mmCM2_CM_BLNDGAM_RAMB_REGION_4_5_BASE_IDX 2
#define mmCM2_CM_BLNDGAM_RAMB_REGION_6_7 0x1099
#define mmCM2_CM_BLNDGAM_RAMB_REGION_6_7_BASE_IDX 2
#define mmCM2_CM_BLNDGAM_RAMB_REGION_8_9 0x109a
#define mmCM2_CM_BLNDGAM_RAMB_REGION_8_9_BASE_IDX 2
#define mmCM2_CM_BLNDGAM_RAMB_REGION_10_11 0x109b
#define mmCM2_CM_BLNDGAM_RAMB_REGION_10_11_BASE_IDX 2
#define mmCM2_CM_BLNDGAM_RAMB_REGION_12_13 0x109c
#define mmCM2_CM_BLNDGAM_RAMB_REGION_12_13_BASE_IDX 2
#define mmCM2_CM_BLNDGAM_RAMB_REGION_14_15 0x109d
#define mmCM2_CM_BLNDGAM_RAMB_REGION_14_15_BASE_IDX 2
#define mmCM2_CM_BLNDGAM_RAMB_REGION_16_17 0x109e
#define mmCM2_CM_BLNDGAM_RAMB_REGION_16_17_BASE_IDX 2
#define mmCM2_CM_BLNDGAM_RAMB_REGION_18_19 0x109f
#define mmCM2_CM_BLNDGAM_RAMB_REGION_18_19_BASE_IDX 2
#define mmCM2_CM_BLNDGAM_RAMB_REGION_20_21 0x10a0
#define mmCM2_CM_BLNDGAM_RAMB_REGION_20_21_BASE_IDX 2
#define mmCM2_CM_BLNDGAM_RAMB_REGION_22_23 0x10a1
#define mmCM2_CM_BLNDGAM_RAMB_REGION_22_23_BASE_IDX 2
#define mmCM2_CM_BLNDGAM_RAMB_REGION_24_25 0x10a2
#define mmCM2_CM_BLNDGAM_RAMB_REGION_24_25_BASE_IDX 2
#define mmCM2_CM_BLNDGAM_RAMB_REGION_26_27 0x10a3
#define mmCM2_CM_BLNDGAM_RAMB_REGION_26_27_BASE_IDX 2
#define mmCM2_CM_BLNDGAM_RAMB_REGION_28_29 0x10a4
#define mmCM2_CM_BLNDGAM_RAMB_REGION_28_29_BASE_IDX 2
#define mmCM2_CM_BLNDGAM_RAMB_REGION_30_31 0x10a5
#define mmCM2_CM_BLNDGAM_RAMB_REGION_30_31_BASE_IDX 2
#define mmCM2_CM_BLNDGAM_RAMB_REGION_32_33 0x10a6
#define mmCM2_CM_BLNDGAM_RAMB_REGION_32_33_BASE_IDX 2
#define mmCM2_CM_HDR_MULT_COEF 0x10a7
#define mmCM2_CM_HDR_MULT_COEF_BASE_IDX 2
#define mmCM2_CM_MEM_PWR_CTRL 0x10a8
#define mmCM2_CM_MEM_PWR_CTRL_BASE_IDX 2
#define mmCM2_CM_MEM_PWR_STATUS 0x10a9
#define mmCM2_CM_MEM_PWR_STATUS_BASE_IDX 2
#define mmCM2_CM_DEALPHA 0x10ab
#define mmCM2_CM_DEALPHA_BASE_IDX 2
#define mmCM2_CM_COEF_FORMAT 0x10ac
#define mmCM2_CM_COEF_FORMAT_BASE_IDX 2
#define mmCM2_CM_SHAPER_CONTROL 0x10ad
#define mmCM2_CM_SHAPER_CONTROL_BASE_IDX 2
#define mmCM2_CM_SHAPER_OFFSET_R 0x10ae
#define mmCM2_CM_SHAPER_OFFSET_R_BASE_IDX 2
#define mmCM2_CM_SHAPER_OFFSET_G 0x10af
#define mmCM2_CM_SHAPER_OFFSET_G_BASE_IDX 2
#define mmCM2_CM_SHAPER_OFFSET_B 0x10b0
#define mmCM2_CM_SHAPER_OFFSET_B_BASE_IDX 2
#define mmCM2_CM_SHAPER_SCALE_R 0x10b1
#define mmCM2_CM_SHAPER_SCALE_R_BASE_IDX 2
#define mmCM2_CM_SHAPER_SCALE_G_B 0x10b2
#define mmCM2_CM_SHAPER_SCALE_G_B_BASE_IDX 2
#define mmCM2_CM_SHAPER_LUT_INDEX 0x10b3
#define mmCM2_CM_SHAPER_LUT_INDEX_BASE_IDX 2
#define mmCM2_CM_SHAPER_LUT_DATA 0x10b4
#define mmCM2_CM_SHAPER_LUT_DATA_BASE_IDX 2
#define mmCM2_CM_SHAPER_LUT_WRITE_EN_MASK 0x10b5
#define mmCM2_CM_SHAPER_LUT_WRITE_EN_MASK_BASE_IDX 2
#define mmCM2_CM_SHAPER_RAMA_START_CNTL_B 0x10b6
#define mmCM2_CM_SHAPER_RAMA_START_CNTL_B_BASE_IDX 2
#define mmCM2_CM_SHAPER_RAMA_START_CNTL_G 0x10b7
#define mmCM2_CM_SHAPER_RAMA_START_CNTL_G_BASE_IDX 2
#define mmCM2_CM_SHAPER_RAMA_START_CNTL_R 0x10b8
#define mmCM2_CM_SHAPER_RAMA_START_CNTL_R_BASE_IDX 2
#define mmCM2_CM_SHAPER_RAMA_END_CNTL_B 0x10b9
#define mmCM2_CM_SHAPER_RAMA_END_CNTL_B_BASE_IDX 2
#define mmCM2_CM_SHAPER_RAMA_END_CNTL_G 0x10ba
#define mmCM2_CM_SHAPER_RAMA_END_CNTL_G_BASE_IDX 2
#define mmCM2_CM_SHAPER_RAMA_END_CNTL_R 0x10bb
#define mmCM2_CM_SHAPER_RAMA_END_CNTL_R_BASE_IDX 2
#define mmCM2_CM_SHAPER_RAMA_REGION_0_1 0x10bc
#define mmCM2_CM_SHAPER_RAMA_REGION_0_1_BASE_IDX 2
#define mmCM2_CM_SHAPER_RAMA_REGION_2_3 0x10bd
#define mmCM2_CM_SHAPER_RAMA_REGION_2_3_BASE_IDX 2
#define mmCM2_CM_SHAPER_RAMA_REGION_4_5 0x10be
#define mmCM2_CM_SHAPER_RAMA_REGION_4_5_BASE_IDX 2
#define mmCM2_CM_SHAPER_RAMA_REGION_6_7 0x10bf
#define mmCM2_CM_SHAPER_RAMA_REGION_6_7_BASE_IDX 2
#define mmCM2_CM_SHAPER_RAMA_REGION_8_9 0x10c0
#define mmCM2_CM_SHAPER_RAMA_REGION_8_9_BASE_IDX 2
#define mmCM2_CM_SHAPER_RAMA_REGION_10_11 0x10c1
#define mmCM2_CM_SHAPER_RAMA_REGION_10_11_BASE_IDX 2
#define mmCM2_CM_SHAPER_RAMA_REGION_12_13 0x10c2
#define mmCM2_CM_SHAPER_RAMA_REGION_12_13_BASE_IDX 2
#define mmCM2_CM_SHAPER_RAMA_REGION_14_15 0x10c3
#define mmCM2_CM_SHAPER_RAMA_REGION_14_15_BASE_IDX 2
#define mmCM2_CM_SHAPER_RAMA_REGION_16_17 0x10c4
#define mmCM2_CM_SHAPER_RAMA_REGION_16_17_BASE_IDX 2
#define mmCM2_CM_SHAPER_RAMA_REGION_18_19 0x10c5
#define mmCM2_CM_SHAPER_RAMA_REGION_18_19_BASE_IDX 2
#define mmCM2_CM_SHAPER_RAMA_REGION_20_21 0x10c6
#define mmCM2_CM_SHAPER_RAMA_REGION_20_21_BASE_IDX 2
#define mmCM2_CM_SHAPER_RAMA_REGION_22_23 0x10c7
#define mmCM2_CM_SHAPER_RAMA_REGION_22_23_BASE_IDX 2
#define mmCM2_CM_SHAPER_RAMA_REGION_24_25 0x10c8
#define mmCM2_CM_SHAPER_RAMA_REGION_24_25_BASE_IDX 2
#define mmCM2_CM_SHAPER_RAMA_REGION_26_27 0x10c9
#define mmCM2_CM_SHAPER_RAMA_REGION_26_27_BASE_IDX 2
#define mmCM2_CM_SHAPER_RAMA_REGION_28_29 0x10ca
#define mmCM2_CM_SHAPER_RAMA_REGION_28_29_BASE_IDX 2
#define mmCM2_CM_SHAPER_RAMA_REGION_30_31 0x10cb
#define mmCM2_CM_SHAPER_RAMA_REGION_30_31_BASE_IDX 2
#define mmCM2_CM_SHAPER_RAMA_REGION_32_33 0x10cc
#define mmCM2_CM_SHAPER_RAMA_REGION_32_33_BASE_IDX 2
#define mmCM2_CM_SHAPER_RAMB_START_CNTL_B 0x10cd
#define mmCM2_CM_SHAPER_RAMB_START_CNTL_B_BASE_IDX 2
#define mmCM2_CM_SHAPER_RAMB_START_CNTL_G 0x10ce
#define mmCM2_CM_SHAPER_RAMB_START_CNTL_G_BASE_IDX 2
#define mmCM2_CM_SHAPER_RAMB_START_CNTL_R 0x10cf
#define mmCM2_CM_SHAPER_RAMB_START_CNTL_R_BASE_IDX 2
#define mmCM2_CM_SHAPER_RAMB_END_CNTL_B 0x10d0
#define mmCM2_CM_SHAPER_RAMB_END_CNTL_B_BASE_IDX 2
#define mmCM2_CM_SHAPER_RAMB_END_CNTL_G 0x10d1
#define mmCM2_CM_SHAPER_RAMB_END_CNTL_G_BASE_IDX 2
#define mmCM2_CM_SHAPER_RAMB_END_CNTL_R 0x10d2
#define mmCM2_CM_SHAPER_RAMB_END_CNTL_R_BASE_IDX 2
#define mmCM2_CM_SHAPER_RAMB_REGION_0_1 0x10d3
#define mmCM2_CM_SHAPER_RAMB_REGION_0_1_BASE_IDX 2
#define mmCM2_CM_SHAPER_RAMB_REGION_2_3 0x10d4
#define mmCM2_CM_SHAPER_RAMB_REGION_2_3_BASE_IDX 2
#define mmCM2_CM_SHAPER_RAMB_REGION_4_5 0x10d5
#define mmCM2_CM_SHAPER_RAMB_REGION_4_5_BASE_IDX 2
#define mmCM2_CM_SHAPER_RAMB_REGION_6_7 0x10d6
#define mmCM2_CM_SHAPER_RAMB_REGION_6_7_BASE_IDX 2
#define mmCM2_CM_SHAPER_RAMB_REGION_8_9 0x10d7
#define mmCM2_CM_SHAPER_RAMB_REGION_8_9_BASE_IDX 2
#define mmCM2_CM_SHAPER_RAMB_REGION_10_11 0x10d8
#define mmCM2_CM_SHAPER_RAMB_REGION_10_11_BASE_IDX 2
#define mmCM2_CM_SHAPER_RAMB_REGION_12_13 0x10d9
#define mmCM2_CM_SHAPER_RAMB_REGION_12_13_BASE_IDX 2
#define mmCM2_CM_SHAPER_RAMB_REGION_14_15 0x10da
#define mmCM2_CM_SHAPER_RAMB_REGION_14_15_BASE_IDX 2
#define mmCM2_CM_SHAPER_RAMB_REGION_16_17 0x10db
#define mmCM2_CM_SHAPER_RAMB_REGION_16_17_BASE_IDX 2
#define mmCM2_CM_SHAPER_RAMB_REGION_18_19 0x10dc
#define mmCM2_CM_SHAPER_RAMB_REGION_18_19_BASE_IDX 2
#define mmCM2_CM_SHAPER_RAMB_REGION_20_21 0x10dd
#define mmCM2_CM_SHAPER_RAMB_REGION_20_21_BASE_IDX 2
#define mmCM2_CM_SHAPER_RAMB_REGION_22_23 0x10de
#define mmCM2_CM_SHAPER_RAMB_REGION_22_23_BASE_IDX 2
#define mmCM2_CM_SHAPER_RAMB_REGION_24_25 0x10df
#define mmCM2_CM_SHAPER_RAMB_REGION_24_25_BASE_IDX 2
#define mmCM2_CM_SHAPER_RAMB_REGION_26_27 0x10e0
#define mmCM2_CM_SHAPER_RAMB_REGION_26_27_BASE_IDX 2
#define mmCM2_CM_SHAPER_RAMB_REGION_28_29 0x10e1
#define mmCM2_CM_SHAPER_RAMB_REGION_28_29_BASE_IDX 2
#define mmCM2_CM_SHAPER_RAMB_REGION_30_31 0x10e2
#define mmCM2_CM_SHAPER_RAMB_REGION_30_31_BASE_IDX 2
#define mmCM2_CM_SHAPER_RAMB_REGION_32_33 0x10e3
#define mmCM2_CM_SHAPER_RAMB_REGION_32_33_BASE_IDX 2
#define mmCM2_CM_MEM_PWR_CTRL2 0x10e4
#define mmCM2_CM_MEM_PWR_CTRL2_BASE_IDX 2
#define mmCM2_CM_MEM_PWR_STATUS2 0x10e5
#define mmCM2_CM_MEM_PWR_STATUS2_BASE_IDX 2
#define mmCM2_CM_3DLUT_MODE 0x10e6
#define mmCM2_CM_3DLUT_MODE_BASE_IDX 2
#define mmCM2_CM_3DLUT_INDEX 0x10e7
#define mmCM2_CM_3DLUT_INDEX_BASE_IDX 2
#define mmCM2_CM_3DLUT_DATA 0x10e8
#define mmCM2_CM_3DLUT_DATA_BASE_IDX 2
#define mmCM2_CM_3DLUT_DATA_30BIT 0x10e9
#define mmCM2_CM_3DLUT_DATA_30BIT_BASE_IDX 2
#define mmCM2_CM_3DLUT_READ_WRITE_CONTROL 0x10ea
#define mmCM2_CM_3DLUT_READ_WRITE_CONTROL_BASE_IDX 2
#define mmCM2_CM_3DLUT_OUT_NORM_FACTOR 0x10eb
#define mmCM2_CM_3DLUT_OUT_NORM_FACTOR_BASE_IDX 2
#define mmCM2_CM_3DLUT_OUT_OFFSET_R 0x10ec
#define mmCM2_CM_3DLUT_OUT_OFFSET_R_BASE_IDX 2
#define mmCM2_CM_3DLUT_OUT_OFFSET_G 0x10ed
#define mmCM2_CM_3DLUT_OUT_OFFSET_G_BASE_IDX 2
#define mmCM2_CM_3DLUT_OUT_OFFSET_B 0x10ee
#define mmCM2_CM_3DLUT_OUT_OFFSET_B_BASE_IDX 2
// addressBlock: dce_dc_dpp2_dispdec_dpp_dcperfmon_dc_perfmon_dispdec
// base address: 0x43e8
#define mmDC_PERFMON13_PERFCOUNTER_CNTL 0x10fa
#define mmDC_PERFMON13_PERFCOUNTER_CNTL_BASE_IDX 2
#define mmDC_PERFMON13_PERFCOUNTER_CNTL2 0x10fb
#define mmDC_PERFMON13_PERFCOUNTER_CNTL2_BASE_IDX 2
#define mmDC_PERFMON13_PERFCOUNTER_STATE 0x10fc
#define mmDC_PERFMON13_PERFCOUNTER_STATE_BASE_IDX 2
#define mmDC_PERFMON13_PERFMON_CNTL 0x10fd
#define mmDC_PERFMON13_PERFMON_CNTL_BASE_IDX 2
#define mmDC_PERFMON13_PERFMON_CNTL2 0x10fe
#define mmDC_PERFMON13_PERFMON_CNTL2_BASE_IDX 2
#define mmDC_PERFMON13_PERFMON_CVALUE_INT_MISC 0x10ff
#define mmDC_PERFMON13_PERFMON_CVALUE_INT_MISC_BASE_IDX 2
#define mmDC_PERFMON13_PERFMON_CVALUE_LOW 0x1100
#define mmDC_PERFMON13_PERFMON_CVALUE_LOW_BASE_IDX 2
#define mmDC_PERFMON13_PERFMON_HI 0x1101
#define mmDC_PERFMON13_PERFMON_HI_BASE_IDX 2
#define mmDC_PERFMON13_PERFMON_LOW 0x1102
#define mmDC_PERFMON13_PERFMON_LOW_BASE_IDX 2
// addressBlock: dce_dc_dpp3_dispdec_dpp_top_dispdec
// base address: 0x1104
#define mmDPP_TOP3_DPP_CONTROL 0x1106
#define mmDPP_TOP3_DPP_CONTROL_BASE_IDX 2
#define mmDPP_TOP3_DPP_SOFT_RESET 0x1107
#define mmDPP_TOP3_DPP_SOFT_RESET_BASE_IDX 2
#define mmDPP_TOP3_DPP_CRC_VAL_R_G 0x1108
#define mmDPP_TOP3_DPP_CRC_VAL_R_G_BASE_IDX 2
#define mmDPP_TOP3_DPP_CRC_VAL_B_A 0x1109
#define mmDPP_TOP3_DPP_CRC_VAL_B_A_BASE_IDX 2
#define mmDPP_TOP3_DPP_CRC_CTRL 0x110a
#define mmDPP_TOP3_DPP_CRC_CTRL_BASE_IDX 2
#define mmDPP_TOP3_HOST_READ_CONTROL 0x110b
#define mmDPP_TOP3_HOST_READ_CONTROL_BASE_IDX 2
// addressBlock: dce_dc_dpp3_dispdec_cnvc_cfg_dispdec
// base address: 0x1104
#define mmCNVC_CFG3_CNVC_SURFACE_PIXEL_FORMAT 0x1110
#define mmCNVC_CFG3_CNVC_SURFACE_PIXEL_FORMAT_BASE_IDX 2
#define mmCNVC_CFG3_FORMAT_CONTROL 0x1111
#define mmCNVC_CFG3_FORMAT_CONTROL_BASE_IDX 2
#define mmCNVC_CFG3_FCNV_FP_BIAS_R 0x1112
#define mmCNVC_CFG3_FCNV_FP_BIAS_R_BASE_IDX 2
#define mmCNVC_CFG3_FCNV_FP_BIAS_G 0x1113
#define mmCNVC_CFG3_FCNV_FP_BIAS_G_BASE_IDX 2
#define mmCNVC_CFG3_FCNV_FP_BIAS_B 0x1114
#define mmCNVC_CFG3_FCNV_FP_BIAS_B_BASE_IDX 2
#define mmCNVC_CFG3_FCNV_FP_SCALE_R 0x1115
#define mmCNVC_CFG3_FCNV_FP_SCALE_R_BASE_IDX 2
#define mmCNVC_CFG3_FCNV_FP_SCALE_G 0x1116
#define mmCNVC_CFG3_FCNV_FP_SCALE_G_BASE_IDX 2
#define mmCNVC_CFG3_FCNV_FP_SCALE_B 0x1117
#define mmCNVC_CFG3_FCNV_FP_SCALE_B_BASE_IDX 2
#define mmCNVC_CFG3_COLOR_KEYER_CONTROL 0x1118
#define mmCNVC_CFG3_COLOR_KEYER_CONTROL_BASE_IDX 2
#define mmCNVC_CFG3_COLOR_KEYER_ALPHA 0x1119
#define mmCNVC_CFG3_COLOR_KEYER_ALPHA_BASE_IDX 2
#define mmCNVC_CFG3_COLOR_KEYER_RED 0x111a
#define mmCNVC_CFG3_COLOR_KEYER_RED_BASE_IDX 2
#define mmCNVC_CFG3_COLOR_KEYER_GREEN 0x111b
#define mmCNVC_CFG3_COLOR_KEYER_GREEN_BASE_IDX 2
#define mmCNVC_CFG3_COLOR_KEYER_BLUE 0x111c
#define mmCNVC_CFG3_COLOR_KEYER_BLUE_BASE_IDX 2
#define mmCNVC_CFG3_ALPHA_2BIT_LUT 0x111e
#define mmCNVC_CFG3_ALPHA_2BIT_LUT_BASE_IDX 2
#define mmCNVC_CFG3_PRE_DEALPHA 0x111f
#define mmCNVC_CFG3_PRE_DEALPHA_BASE_IDX 2
#define mmCNVC_CFG3_PRE_CSC_MODE 0x1120
#define mmCNVC_CFG3_PRE_CSC_MODE_BASE_IDX 2
#define mmCNVC_CFG3_PRE_CSC_C11_C12 0x1121
#define mmCNVC_CFG3_PRE_CSC_C11_C12_BASE_IDX 2
#define mmCNVC_CFG3_PRE_CSC_C13_C14 0x1122
#define mmCNVC_CFG3_PRE_CSC_C13_C14_BASE_IDX 2
#define mmCNVC_CFG3_PRE_CSC_C21_C22 0x1123
#define mmCNVC_CFG3_PRE_CSC_C21_C22_BASE_IDX 2
#define mmCNVC_CFG3_PRE_CSC_C23_C24 0x1124
#define mmCNVC_CFG3_PRE_CSC_C23_C24_BASE_IDX 2
#define mmCNVC_CFG3_PRE_CSC_C31_C32 0x1125
#define mmCNVC_CFG3_PRE_CSC_C31_C32_BASE_IDX 2
#define mmCNVC_CFG3_PRE_CSC_C33_C34 0x1126
#define mmCNVC_CFG3_PRE_CSC_C33_C34_BASE_IDX 2
#define mmCNVC_CFG3_PRE_CSC_B_C11_C12 0x1127
#define mmCNVC_CFG3_PRE_CSC_B_C11_C12_BASE_IDX 2
#define mmCNVC_CFG3_PRE_CSC_B_C13_C14 0x1128
#define mmCNVC_CFG3_PRE_CSC_B_C13_C14_BASE_IDX 2
#define mmCNVC_CFG3_PRE_CSC_B_C21_C22 0x1129
#define mmCNVC_CFG3_PRE_CSC_B_C21_C22_BASE_IDX 2
#define mmCNVC_CFG3_PRE_CSC_B_C23_C24 0x112a
#define mmCNVC_CFG3_PRE_CSC_B_C23_C24_BASE_IDX 2
#define mmCNVC_CFG3_PRE_CSC_B_C31_C32 0x112b
#define mmCNVC_CFG3_PRE_CSC_B_C31_C32_BASE_IDX 2
#define mmCNVC_CFG3_PRE_CSC_B_C33_C34 0x112c
#define mmCNVC_CFG3_PRE_CSC_B_C33_C34_BASE_IDX 2
#define mmCNVC_CFG3_CNVC_COEF_FORMAT 0x112d
#define mmCNVC_CFG3_CNVC_COEF_FORMAT_BASE_IDX 2
#define mmCNVC_CFG3_PRE_DEGAM 0x112e
#define mmCNVC_CFG3_PRE_DEGAM_BASE_IDX 2
#define mmCNVC_CFG3_PRE_REALPHA 0x112f
#define mmCNVC_CFG3_PRE_REALPHA_BASE_IDX 2
// addressBlock: dce_dc_dpp3_dispdec_cnvc_cur_dispdec
// base address: 0x1104
#define mmCNVC_CUR3_CURSOR0_CONTROL 0x1132
#define mmCNVC_CUR3_CURSOR0_CONTROL_BASE_IDX 2
#define mmCNVC_CUR3_CURSOR0_COLOR0 0x1133
#define mmCNVC_CUR3_CURSOR0_COLOR0_BASE_IDX 2
#define mmCNVC_CUR3_CURSOR0_COLOR1 0x1134
#define mmCNVC_CUR3_CURSOR0_COLOR1_BASE_IDX 2
#define mmCNVC_CUR3_CURSOR0_FP_SCALE_BIAS 0x1135
#define mmCNVC_CUR3_CURSOR0_FP_SCALE_BIAS_BASE_IDX 2
// addressBlock: dce_dc_dpp3_dispdec_dscl_dispdec
// base address: 0x1104
#define mmDSCL3_SCL_COEF_RAM_TAP_SELECT 0x113a
#define mmDSCL3_SCL_COEF_RAM_TAP_SELECT_BASE_IDX 2
#define mmDSCL3_SCL_COEF_RAM_TAP_DATA 0x113b
#define mmDSCL3_SCL_COEF_RAM_TAP_DATA_BASE_IDX 2
#define mmDSCL3_SCL_MODE 0x113c
#define mmDSCL3_SCL_MODE_BASE_IDX 2
#define mmDSCL3_SCL_TAP_CONTROL 0x113d
#define mmDSCL3_SCL_TAP_CONTROL_BASE_IDX 2
#define mmDSCL3_DSCL_CONTROL 0x113e
#define mmDSCL3_DSCL_CONTROL_BASE_IDX 2
#define mmDSCL3_DSCL_2TAP_CONTROL 0x113f
#define mmDSCL3_DSCL_2TAP_CONTROL_BASE_IDX 2
#define mmDSCL3_SCL_MANUAL_REPLICATE_CONTROL 0x1140
#define mmDSCL3_SCL_MANUAL_REPLICATE_CONTROL_BASE_IDX 2
#define mmDSCL3_SCL_HORZ_FILTER_SCALE_RATIO 0x1141
#define mmDSCL3_SCL_HORZ_FILTER_SCALE_RATIO_BASE_IDX 2
#define mmDSCL3_SCL_HORZ_FILTER_INIT 0x1142
#define mmDSCL3_SCL_HORZ_FILTER_INIT_BASE_IDX 2
#define mmDSCL3_SCL_HORZ_FILTER_SCALE_RATIO_C 0x1143
#define mmDSCL3_SCL_HORZ_FILTER_SCALE_RATIO_C_BASE_IDX 2
#define mmDSCL3_SCL_HORZ_FILTER_INIT_C 0x1144
#define mmDSCL3_SCL_HORZ_FILTER_INIT_C_BASE_IDX 2
#define mmDSCL3_SCL_VERT_FILTER_SCALE_RATIO 0x1145
#define mmDSCL3_SCL_VERT_FILTER_SCALE_RATIO_BASE_IDX 2
#define mmDSCL3_SCL_VERT_FILTER_INIT 0x1146
#define mmDSCL3_SCL_VERT_FILTER_INIT_BASE_IDX 2
#define mmDSCL3_SCL_VERT_FILTER_INIT_BOT 0x1147
#define mmDSCL3_SCL_VERT_FILTER_INIT_BOT_BASE_IDX 2
#define mmDSCL3_SCL_VERT_FILTER_SCALE_RATIO_C 0x1148
#define mmDSCL3_SCL_VERT_FILTER_SCALE_RATIO_C_BASE_IDX 2
#define mmDSCL3_SCL_VERT_FILTER_INIT_C 0x1149
#define mmDSCL3_SCL_VERT_FILTER_INIT_C_BASE_IDX 2
#define mmDSCL3_SCL_VERT_FILTER_INIT_BOT_C 0x114a
#define mmDSCL3_SCL_VERT_FILTER_INIT_BOT_C_BASE_IDX 2
#define mmDSCL3_SCL_BLACK_COLOR 0x114b
#define mmDSCL3_SCL_BLACK_COLOR_BASE_IDX 2
#define mmDSCL3_DSCL_UPDATE 0x114c
#define mmDSCL3_DSCL_UPDATE_BASE_IDX 2
#define mmDSCL3_DSCL_AUTOCAL 0x114d
#define mmDSCL3_DSCL_AUTOCAL_BASE_IDX 2
#define mmDSCL3_DSCL_EXT_OVERSCAN_LEFT_RIGHT 0x114e
#define mmDSCL3_DSCL_EXT_OVERSCAN_LEFT_RIGHT_BASE_IDX 2
#define mmDSCL3_DSCL_EXT_OVERSCAN_TOP_BOTTOM 0x114f
#define mmDSCL3_DSCL_EXT_OVERSCAN_TOP_BOTTOM_BASE_IDX 2
#define mmDSCL3_OTG_H_BLANK 0x1150
#define mmDSCL3_OTG_H_BLANK_BASE_IDX 2
#define mmDSCL3_OTG_V_BLANK 0x1151
#define mmDSCL3_OTG_V_BLANK_BASE_IDX 2
#define mmDSCL3_RECOUT_START 0x1152
#define mmDSCL3_RECOUT_START_BASE_IDX 2
#define mmDSCL3_RECOUT_SIZE 0x1153
#define mmDSCL3_RECOUT_SIZE_BASE_IDX 2
#define mmDSCL3_MPC_SIZE 0x1154
#define mmDSCL3_MPC_SIZE_BASE_IDX 2
#define mmDSCL3_LB_DATA_FORMAT 0x1155
#define mmDSCL3_LB_DATA_FORMAT_BASE_IDX 2
#define mmDSCL3_LB_MEMORY_CTRL 0x1156
#define mmDSCL3_LB_MEMORY_CTRL_BASE_IDX 2
#define mmDSCL3_LB_V_COUNTER 0x1157
#define mmDSCL3_LB_V_COUNTER_BASE_IDX 2
#define mmDSCL3_DSCL_MEM_PWR_CTRL 0x1158
#define mmDSCL3_DSCL_MEM_PWR_CTRL_BASE_IDX 2
#define mmDSCL3_DSCL_MEM_PWR_STATUS 0x1159
#define mmDSCL3_DSCL_MEM_PWR_STATUS_BASE_IDX 2
#define mmDSCL3_OBUF_CONTROL 0x115a
#define mmDSCL3_OBUF_CONTROL_BASE_IDX 2
#define mmDSCL3_OBUF_MEM_PWR_CTRL 0x115b
#define mmDSCL3_OBUF_MEM_PWR_CTRL_BASE_IDX 2
// addressBlock: dce_dc_dpp3_dispdec_cm_dispdec
// base address: 0x1104
#define mmCM3_CM_CONTROL 0x1161
#define mmCM3_CM_CONTROL_BASE_IDX 2
#define mmCM3_CM_POST_CSC_CONTROL 0x1162
#define mmCM3_CM_POST_CSC_CONTROL_BASE_IDX 2
#define mmCM3_CM_POST_CSC_C11_C12 0x1163
#define mmCM3_CM_POST_CSC_C11_C12_BASE_IDX 2
#define mmCM3_CM_POST_CSC_C13_C14 0x1164
#define mmCM3_CM_POST_CSC_C13_C14_BASE_IDX 2
#define mmCM3_CM_POST_CSC_C21_C22 0x1165
#define mmCM3_CM_POST_CSC_C21_C22_BASE_IDX 2
#define mmCM3_CM_POST_CSC_C23_C24 0x1166
#define mmCM3_CM_POST_CSC_C23_C24_BASE_IDX 2
#define mmCM3_CM_POST_CSC_C31_C32 0x1167
#define mmCM3_CM_POST_CSC_C31_C32_BASE_IDX 2
#define mmCM3_CM_POST_CSC_C33_C34 0x1168
#define mmCM3_CM_POST_CSC_C33_C34_BASE_IDX 2
#define mmCM3_CM_POST_CSC_B_C11_C12 0x1169
#define mmCM3_CM_POST_CSC_B_C11_C12_BASE_IDX 2
#define mmCM3_CM_POST_CSC_B_C13_C14 0x116a
#define mmCM3_CM_POST_CSC_B_C13_C14_BASE_IDX 2
#define mmCM3_CM_POST_CSC_B_C21_C22 0x116b
#define mmCM3_CM_POST_CSC_B_C21_C22_BASE_IDX 2
#define mmCM3_CM_POST_CSC_B_C23_C24 0x116c
#define mmCM3_CM_POST_CSC_B_C23_C24_BASE_IDX 2
#define mmCM3_CM_POST_CSC_B_C31_C32 0x116d
#define mmCM3_CM_POST_CSC_B_C31_C32_BASE_IDX 2
#define mmCM3_CM_POST_CSC_B_C33_C34 0x116e
#define mmCM3_CM_POST_CSC_B_C33_C34_BASE_IDX 2
#define mmCM3_CM_GAMUT_REMAP_CONTROL 0x116f
#define mmCM3_CM_GAMUT_REMAP_CONTROL_BASE_IDX 2
#define mmCM3_CM_GAMUT_REMAP_C11_C12 0x1170
#define mmCM3_CM_GAMUT_REMAP_C11_C12_BASE_IDX 2
#define mmCM3_CM_GAMUT_REMAP_C13_C14 0x1171
#define mmCM3_CM_GAMUT_REMAP_C13_C14_BASE_IDX 2
#define mmCM3_CM_GAMUT_REMAP_C21_C22 0x1172
#define mmCM3_CM_GAMUT_REMAP_C21_C22_BASE_IDX 2
#define mmCM3_CM_GAMUT_REMAP_C23_C24 0x1173
#define mmCM3_CM_GAMUT_REMAP_C23_C24_BASE_IDX 2
#define mmCM3_CM_GAMUT_REMAP_C31_C32 0x1174
#define mmCM3_CM_GAMUT_REMAP_C31_C32_BASE_IDX 2
#define mmCM3_CM_GAMUT_REMAP_C33_C34 0x1175
#define mmCM3_CM_GAMUT_REMAP_C33_C34_BASE_IDX 2
#define mmCM3_CM_GAMUT_REMAP_B_C11_C12 0x1176
#define mmCM3_CM_GAMUT_REMAP_B_C11_C12_BASE_IDX 2
#define mmCM3_CM_GAMUT_REMAP_B_C13_C14 0x1177
#define mmCM3_CM_GAMUT_REMAP_B_C13_C14_BASE_IDX 2
#define mmCM3_CM_GAMUT_REMAP_B_C21_C22 0x1178
#define mmCM3_CM_GAMUT_REMAP_B_C21_C22_BASE_IDX 2
#define mmCM3_CM_GAMUT_REMAP_B_C23_C24 0x1179
#define mmCM3_CM_GAMUT_REMAP_B_C23_C24_BASE_IDX 2
#define mmCM3_CM_GAMUT_REMAP_B_C31_C32 0x117a
#define mmCM3_CM_GAMUT_REMAP_B_C31_C32_BASE_IDX 2
#define mmCM3_CM_GAMUT_REMAP_B_C33_C34 0x117b
#define mmCM3_CM_GAMUT_REMAP_B_C33_C34_BASE_IDX 2
#define mmCM3_CM_BIAS_CR_R 0x117c
#define mmCM3_CM_BIAS_CR_R_BASE_IDX 2
#define mmCM3_CM_BIAS_Y_G_CB_B 0x117d
#define mmCM3_CM_BIAS_Y_G_CB_B_BASE_IDX 2
#define mmCM3_CM_GAMCOR_CONTROL 0x117e
#define mmCM3_CM_GAMCOR_CONTROL_BASE_IDX 2
#define mmCM3_CM_GAMCOR_LUT_INDEX 0x117f
#define mmCM3_CM_GAMCOR_LUT_INDEX_BASE_IDX 2
#define mmCM3_CM_GAMCOR_LUT_DATA 0x1180
#define mmCM3_CM_GAMCOR_LUT_DATA_BASE_IDX 2
#define mmCM3_CM_GAMCOR_LUT_CONTROL 0x1181
#define mmCM3_CM_GAMCOR_LUT_CONTROL_BASE_IDX 2
#define mmCM3_CM_GAMCOR_RAMA_START_CNTL_B 0x1182
#define mmCM3_CM_GAMCOR_RAMA_START_CNTL_B_BASE_IDX 2
#define mmCM3_CM_GAMCOR_RAMA_START_CNTL_G 0x1183
#define mmCM3_CM_GAMCOR_RAMA_START_CNTL_G_BASE_IDX 2
#define mmCM3_CM_GAMCOR_RAMA_START_CNTL_R 0x1184
#define mmCM3_CM_GAMCOR_RAMA_START_CNTL_R_BASE_IDX 2
#define mmCM3_CM_GAMCOR_RAMA_START_SLOPE_CNTL_B 0x1185
#define mmCM3_CM_GAMCOR_RAMA_START_SLOPE_CNTL_B_BASE_IDX 2
#define mmCM3_CM_GAMCOR_RAMA_START_SLOPE_CNTL_G 0x1186
#define mmCM3_CM_GAMCOR_RAMA_START_SLOPE_CNTL_G_BASE_IDX 2
#define mmCM3_CM_GAMCOR_RAMA_START_SLOPE_CNTL_R 0x1187
#define mmCM3_CM_GAMCOR_RAMA_START_SLOPE_CNTL_R_BASE_IDX 2
#define mmCM3_CM_GAMCOR_RAMA_START_BASE_CNTL_B 0x1188
#define mmCM3_CM_GAMCOR_RAMA_START_BASE_CNTL_B_BASE_IDX 2
#define mmCM3_CM_GAMCOR_RAMA_START_BASE_CNTL_G 0x1189
#define mmCM3_CM_GAMCOR_RAMA_START_BASE_CNTL_G_BASE_IDX 2
#define mmCM3_CM_GAMCOR_RAMA_START_BASE_CNTL_R 0x118a
#define mmCM3_CM_GAMCOR_RAMA_START_BASE_CNTL_R_BASE_IDX 2
#define mmCM3_CM_GAMCOR_RAMA_END_CNTL1_B 0x118b
#define mmCM3_CM_GAMCOR_RAMA_END_CNTL1_B_BASE_IDX 2
#define mmCM3_CM_GAMCOR_RAMA_END_CNTL2_B 0x118c
#define mmCM3_CM_GAMCOR_RAMA_END_CNTL2_B_BASE_IDX 2
#define mmCM3_CM_GAMCOR_RAMA_END_CNTL1_G 0x118d
#define mmCM3_CM_GAMCOR_RAMA_END_CNTL1_G_BASE_IDX 2
#define mmCM3_CM_GAMCOR_RAMA_END_CNTL2_G 0x118e
#define mmCM3_CM_GAMCOR_RAMA_END_CNTL2_G_BASE_IDX 2
#define mmCM3_CM_GAMCOR_RAMA_END_CNTL1_R 0x118f
#define mmCM3_CM_GAMCOR_RAMA_END_CNTL1_R_BASE_IDX 2
#define mmCM3_CM_GAMCOR_RAMA_END_CNTL2_R 0x1190
#define mmCM3_CM_GAMCOR_RAMA_END_CNTL2_R_BASE_IDX 2
#define mmCM3_CM_GAMCOR_RAMA_OFFSET_B 0x1191
#define mmCM3_CM_GAMCOR_RAMA_OFFSET_B_BASE_IDX 2
#define mmCM3_CM_GAMCOR_RAMA_OFFSET_G 0x1192
#define mmCM3_CM_GAMCOR_RAMA_OFFSET_G_BASE_IDX 2
#define mmCM3_CM_GAMCOR_RAMA_OFFSET_R 0x1193
#define mmCM3_CM_GAMCOR_RAMA_OFFSET_R_BASE_IDX 2
#define mmCM3_CM_GAMCOR_RAMA_REGION_0_1 0x1194
#define mmCM3_CM_GAMCOR_RAMA_REGION_0_1_BASE_IDX 2
#define mmCM3_CM_GAMCOR_RAMA_REGION_2_3 0x1195
#define mmCM3_CM_GAMCOR_RAMA_REGION_2_3_BASE_IDX 2
#define mmCM3_CM_GAMCOR_RAMA_REGION_4_5 0x1196
#define mmCM3_CM_GAMCOR_RAMA_REGION_4_5_BASE_IDX 2
#define mmCM3_CM_GAMCOR_RAMA_REGION_6_7 0x1197
#define mmCM3_CM_GAMCOR_RAMA_REGION_6_7_BASE_IDX 2
#define mmCM3_CM_GAMCOR_RAMA_REGION_8_9 0x1198
#define mmCM3_CM_GAMCOR_RAMA_REGION_8_9_BASE_IDX 2
#define mmCM3_CM_GAMCOR_RAMA_REGION_10_11 0x1199
#define mmCM3_CM_GAMCOR_RAMA_REGION_10_11_BASE_IDX 2
#define mmCM3_CM_GAMCOR_RAMA_REGION_12_13 0x119a
#define mmCM3_CM_GAMCOR_RAMA_REGION_12_13_BASE_IDX 2
#define mmCM3_CM_GAMCOR_RAMA_REGION_14_15 0x119b
#define mmCM3_CM_GAMCOR_RAMA_REGION_14_15_BASE_IDX 2
#define mmCM3_CM_GAMCOR_RAMA_REGION_16_17 0x119c
#define mmCM3_CM_GAMCOR_RAMA_REGION_16_17_BASE_IDX 2
#define mmCM3_CM_GAMCOR_RAMA_REGION_18_19 0x119d
#define mmCM3_CM_GAMCOR_RAMA_REGION_18_19_BASE_IDX 2
#define mmCM3_CM_GAMCOR_RAMA_REGION_20_21 0x119e
#define mmCM3_CM_GAMCOR_RAMA_REGION_20_21_BASE_IDX 2
#define mmCM3_CM_GAMCOR_RAMA_REGION_22_23 0x119f
#define mmCM3_CM_GAMCOR_RAMA_REGION_22_23_BASE_IDX 2
#define mmCM3_CM_GAMCOR_RAMA_REGION_24_25 0x11a0
#define mmCM3_CM_GAMCOR_RAMA_REGION_24_25_BASE_IDX 2
#define mmCM3_CM_GAMCOR_RAMA_REGION_26_27 0x11a1
#define mmCM3_CM_GAMCOR_RAMA_REGION_26_27_BASE_IDX 2
#define mmCM3_CM_GAMCOR_RAMA_REGION_28_29 0x11a2
#define mmCM3_CM_GAMCOR_RAMA_REGION_28_29_BASE_IDX 2
#define mmCM3_CM_GAMCOR_RAMA_REGION_30_31 0x11a3
#define mmCM3_CM_GAMCOR_RAMA_REGION_30_31_BASE_IDX 2
#define mmCM3_CM_GAMCOR_RAMA_REGION_32_33 0x11a4
#define mmCM3_CM_GAMCOR_RAMA_REGION_32_33_BASE_IDX 2
#define mmCM3_CM_GAMCOR_RAMB_START_CNTL_B 0x11a5
#define mmCM3_CM_GAMCOR_RAMB_START_CNTL_B_BASE_IDX 2
#define mmCM3_CM_GAMCOR_RAMB_START_CNTL_G 0x11a6
#define mmCM3_CM_GAMCOR_RAMB_START_CNTL_G_BASE_IDX 2
#define mmCM3_CM_GAMCOR_RAMB_START_CNTL_R 0x11a7
#define mmCM3_CM_GAMCOR_RAMB_START_CNTL_R_BASE_IDX 2
#define mmCM3_CM_GAMCOR_RAMB_START_SLOPE_CNTL_B 0x11a8
#define mmCM3_CM_GAMCOR_RAMB_START_SLOPE_CNTL_B_BASE_IDX 2
#define mmCM3_CM_GAMCOR_RAMB_START_SLOPE_CNTL_G 0x11a9
#define mmCM3_CM_GAMCOR_RAMB_START_SLOPE_CNTL_G_BASE_IDX 2
#define mmCM3_CM_GAMCOR_RAMB_START_SLOPE_CNTL_R 0x11aa
#define mmCM3_CM_GAMCOR_RAMB_START_SLOPE_CNTL_R_BASE_IDX 2
#define mmCM3_CM_GAMCOR_RAMB_START_BASE_CNTL_B 0x11ab
#define mmCM3_CM_GAMCOR_RAMB_START_BASE_CNTL_B_BASE_IDX 2
#define mmCM3_CM_GAMCOR_RAMB_START_BASE_CNTL_G 0x11ac
#define mmCM3_CM_GAMCOR_RAMB_START_BASE_CNTL_G_BASE_IDX 2
#define mmCM3_CM_GAMCOR_RAMB_START_BASE_CNTL_R 0x11ad
#define mmCM3_CM_GAMCOR_RAMB_START_BASE_CNTL_R_BASE_IDX 2
#define mmCM3_CM_GAMCOR_RAMB_END_CNTL1_B 0x11ae
#define mmCM3_CM_GAMCOR_RAMB_END_CNTL1_B_BASE_IDX 2
#define mmCM3_CM_GAMCOR_RAMB_END_CNTL2_B 0x11af
#define mmCM3_CM_GAMCOR_RAMB_END_CNTL2_B_BASE_IDX 2
#define mmCM3_CM_GAMCOR_RAMB_END_CNTL1_G 0x11b0
#define mmCM3_CM_GAMCOR_RAMB_END_CNTL1_G_BASE_IDX 2
#define mmCM3_CM_GAMCOR_RAMB_END_CNTL2_G 0x11b1
#define mmCM3_CM_GAMCOR_RAMB_END_CNTL2_G_BASE_IDX 2
#define mmCM3_CM_GAMCOR_RAMB_END_CNTL1_R 0x11b2
#define mmCM3_CM_GAMCOR_RAMB_END_CNTL1_R_BASE_IDX 2
#define mmCM3_CM_GAMCOR_RAMB_END_CNTL2_R 0x11b3
#define mmCM3_CM_GAMCOR_RAMB_END_CNTL2_R_BASE_IDX 2
#define mmCM3_CM_GAMCOR_RAMB_OFFSET_B 0x11b4
#define mmCM3_CM_GAMCOR_RAMB_OFFSET_B_BASE_IDX 2
#define mmCM3_CM_GAMCOR_RAMB_OFFSET_G 0x11b5
#define mmCM3_CM_GAMCOR_RAMB_OFFSET_G_BASE_IDX 2
#define mmCM3_CM_GAMCOR_RAMB_OFFSET_R 0x11b6
#define mmCM3_CM_GAMCOR_RAMB_OFFSET_R_BASE_IDX 2
#define mmCM3_CM_GAMCOR_RAMB_REGION_0_1 0x11b7
#define mmCM3_CM_GAMCOR_RAMB_REGION_0_1_BASE_IDX 2
#define mmCM3_CM_GAMCOR_RAMB_REGION_2_3 0x11b8
#define mmCM3_CM_GAMCOR_RAMB_REGION_2_3_BASE_IDX 2
#define mmCM3_CM_GAMCOR_RAMB_REGION_4_5 0x11b9
#define mmCM3_CM_GAMCOR_RAMB_REGION_4_5_BASE_IDX 2
#define mmCM3_CM_GAMCOR_RAMB_REGION_6_7 0x11ba
#define mmCM3_CM_GAMCOR_RAMB_REGION_6_7_BASE_IDX 2
#define mmCM3_CM_GAMCOR_RAMB_REGION_8_9 0x11bb
#define mmCM3_CM_GAMCOR_RAMB_REGION_8_9_BASE_IDX 2
#define mmCM3_CM_GAMCOR_RAMB_REGION_10_11 0x11bc
#define mmCM3_CM_GAMCOR_RAMB_REGION_10_11_BASE_IDX 2
#define mmCM3_CM_GAMCOR_RAMB_REGION_12_13 0x11bd
#define mmCM3_CM_GAMCOR_RAMB_REGION_12_13_BASE_IDX 2
#define mmCM3_CM_GAMCOR_RAMB_REGION_14_15 0x11be
#define mmCM3_CM_GAMCOR_RAMB_REGION_14_15_BASE_IDX 2
#define mmCM3_CM_GAMCOR_RAMB_REGION_16_17 0x11bf
#define mmCM3_CM_GAMCOR_RAMB_REGION_16_17_BASE_IDX 2
#define mmCM3_CM_GAMCOR_RAMB_REGION_18_19 0x11c0
#define mmCM3_CM_GAMCOR_RAMB_REGION_18_19_BASE_IDX 2
#define mmCM3_CM_GAMCOR_RAMB_REGION_20_21 0x11c1
#define mmCM3_CM_GAMCOR_RAMB_REGION_20_21_BASE_IDX 2
#define mmCM3_CM_GAMCOR_RAMB_REGION_22_23 0x11c2
#define mmCM3_CM_GAMCOR_RAMB_REGION_22_23_BASE_IDX 2
#define mmCM3_CM_GAMCOR_RAMB_REGION_24_25 0x11c3
#define mmCM3_CM_GAMCOR_RAMB_REGION_24_25_BASE_IDX 2
#define mmCM3_CM_GAMCOR_RAMB_REGION_26_27 0x11c4
#define mmCM3_CM_GAMCOR_RAMB_REGION_26_27_BASE_IDX 2
#define mmCM3_CM_GAMCOR_RAMB_REGION_28_29 0x11c5
#define mmCM3_CM_GAMCOR_RAMB_REGION_28_29_BASE_IDX 2
#define mmCM3_CM_GAMCOR_RAMB_REGION_30_31 0x11c6
#define mmCM3_CM_GAMCOR_RAMB_REGION_30_31_BASE_IDX 2
#define mmCM3_CM_GAMCOR_RAMB_REGION_32_33 0x11c7
#define mmCM3_CM_GAMCOR_RAMB_REGION_32_33_BASE_IDX 2
#define mmCM3_CM_BLNDGAM_CONTROL 0x11c8
#define mmCM3_CM_BLNDGAM_CONTROL_BASE_IDX 2
#define mmCM3_CM_BLNDGAM_LUT_INDEX 0x11c9
#define mmCM3_CM_BLNDGAM_LUT_INDEX_BASE_IDX 2
#define mmCM3_CM_BLNDGAM_LUT_DATA 0x11ca
#define mmCM3_CM_BLNDGAM_LUT_DATA_BASE_IDX 2
#define mmCM3_CM_BLNDGAM_LUT_CONTROL 0x11cb
#define mmCM3_CM_BLNDGAM_LUT_CONTROL_BASE_IDX 2
#define mmCM3_CM_BLNDGAM_RAMA_START_CNTL_B 0x11cc
#define mmCM3_CM_BLNDGAM_RAMA_START_CNTL_B_BASE_IDX 2
#define mmCM3_CM_BLNDGAM_RAMA_START_CNTL_G 0x11cd
#define mmCM3_CM_BLNDGAM_RAMA_START_CNTL_G_BASE_IDX 2
#define mmCM3_CM_BLNDGAM_RAMA_START_CNTL_R 0x11ce
#define mmCM3_CM_BLNDGAM_RAMA_START_CNTL_R_BASE_IDX 2
#define mmCM3_CM_BLNDGAM_RAMA_START_SLOPE_CNTL_B 0x11cf
#define mmCM3_CM_BLNDGAM_RAMA_START_SLOPE_CNTL_B_BASE_IDX 2
#define mmCM3_CM_BLNDGAM_RAMA_START_SLOPE_CNTL_G 0x11d0
#define mmCM3_CM_BLNDGAM_RAMA_START_SLOPE_CNTL_G_BASE_IDX 2
#define mmCM3_CM_BLNDGAM_RAMA_START_SLOPE_CNTL_R 0x11d1
#define mmCM3_CM_BLNDGAM_RAMA_START_SLOPE_CNTL_R_BASE_IDX 2
#define mmCM3_CM_BLNDGAM_RAMA_START_BASE_CNTL_B 0x11d2
#define mmCM3_CM_BLNDGAM_RAMA_START_BASE_CNTL_B_BASE_IDX 2
#define mmCM3_CM_BLNDGAM_RAMA_START_BASE_CNTL_G 0x11d3
#define mmCM3_CM_BLNDGAM_RAMA_START_BASE_CNTL_G_BASE_IDX 2
#define mmCM3_CM_BLNDGAM_RAMA_START_BASE_CNTL_R 0x11d4
#define mmCM3_CM_BLNDGAM_RAMA_START_BASE_CNTL_R_BASE_IDX 2
#define mmCM3_CM_BLNDGAM_RAMA_END_CNTL1_B 0x11d5
#define mmCM3_CM_BLNDGAM_RAMA_END_CNTL1_B_BASE_IDX 2
#define mmCM3_CM_BLNDGAM_RAMA_END_CNTL2_B 0x11d6
#define mmCM3_CM_BLNDGAM_RAMA_END_CNTL2_B_BASE_IDX 2
#define mmCM3_CM_BLNDGAM_RAMA_END_CNTL1_G 0x11d7
#define mmCM3_CM_BLNDGAM_RAMA_END_CNTL1_G_BASE_IDX 2
#define mmCM3_CM_BLNDGAM_RAMA_END_CNTL2_G 0x11d8
#define mmCM3_CM_BLNDGAM_RAMA_END_CNTL2_G_BASE_IDX 2
#define mmCM3_CM_BLNDGAM_RAMA_END_CNTL1_R 0x11d9
#define mmCM3_CM_BLNDGAM_RAMA_END_CNTL1_R_BASE_IDX 2
#define mmCM3_CM_BLNDGAM_RAMA_END_CNTL2_R 0x11da
#define mmCM3_CM_BLNDGAM_RAMA_END_CNTL2_R_BASE_IDX 2
#define mmCM3_CM_BLNDGAM_RAMA_OFFSET_B 0x11db
#define mmCM3_CM_BLNDGAM_RAMA_OFFSET_B_BASE_IDX 2
#define mmCM3_CM_BLNDGAM_RAMA_OFFSET_G 0x11dc
#define mmCM3_CM_BLNDGAM_RAMA_OFFSET_G_BASE_IDX 2
#define mmCM3_CM_BLNDGAM_RAMA_OFFSET_R 0x11dd
#define mmCM3_CM_BLNDGAM_RAMA_OFFSET_R_BASE_IDX 2
#define mmCM3_CM_BLNDGAM_RAMA_REGION_0_1 0x11de
#define mmCM3_CM_BLNDGAM_RAMA_REGION_0_1_BASE_IDX 2
#define mmCM3_CM_BLNDGAM_RAMA_REGION_2_3 0x11df
#define mmCM3_CM_BLNDGAM_RAMA_REGION_2_3_BASE_IDX 2
#define mmCM3_CM_BLNDGAM_RAMA_REGION_4_5 0x11e0
#define mmCM3_CM_BLNDGAM_RAMA_REGION_4_5_BASE_IDX 2
#define mmCM3_CM_BLNDGAM_RAMA_REGION_6_7 0x11e1
#define mmCM3_CM_BLNDGAM_RAMA_REGION_6_7_BASE_IDX 2
#define mmCM3_CM_BLNDGAM_RAMA_REGION_8_9 0x11e2
#define mmCM3_CM_BLNDGAM_RAMA_REGION_8_9_BASE_IDX 2
#define mmCM3_CM_BLNDGAM_RAMA_REGION_10_11 0x11e3
#define mmCM3_CM_BLNDGAM_RAMA_REGION_10_11_BASE_IDX 2
#define mmCM3_CM_BLNDGAM_RAMA_REGION_12_13 0x11e4
#define mmCM3_CM_BLNDGAM_RAMA_REGION_12_13_BASE_IDX 2
#define mmCM3_CM_BLNDGAM_RAMA_REGION_14_15 0x11e5
#define mmCM3_CM_BLNDGAM_RAMA_REGION_14_15_BASE_IDX 2
#define mmCM3_CM_BLNDGAM_RAMA_REGION_16_17 0x11e6
#define mmCM3_CM_BLNDGAM_RAMA_REGION_16_17_BASE_IDX 2
#define mmCM3_CM_BLNDGAM_RAMA_REGION_18_19 0x11e7
#define mmCM3_CM_BLNDGAM_RAMA_REGION_18_19_BASE_IDX 2
#define mmCM3_CM_BLNDGAM_RAMA_REGION_20_21 0x11e8
#define mmCM3_CM_BLNDGAM_RAMA_REGION_20_21_BASE_IDX 2
#define mmCM3_CM_BLNDGAM_RAMA_REGION_22_23 0x11e9
#define mmCM3_CM_BLNDGAM_RAMA_REGION_22_23_BASE_IDX 2
#define mmCM3_CM_BLNDGAM_RAMA_REGION_24_25 0x11ea
#define mmCM3_CM_BLNDGAM_RAMA_REGION_24_25_BASE_IDX 2
#define mmCM3_CM_BLNDGAM_RAMA_REGION_26_27 0x11eb
#define mmCM3_CM_BLNDGAM_RAMA_REGION_26_27_BASE_IDX 2
#define mmCM3_CM_BLNDGAM_RAMA_REGION_28_29 0x11ec
#define mmCM3_CM_BLNDGAM_RAMA_REGION_28_29_BASE_IDX 2
#define mmCM3_CM_BLNDGAM_RAMA_REGION_30_31 0x11ed
#define mmCM3_CM_BLNDGAM_RAMA_REGION_30_31_BASE_IDX 2
#define mmCM3_CM_BLNDGAM_RAMA_REGION_32_33 0x11ee
#define mmCM3_CM_BLNDGAM_RAMA_REGION_32_33_BASE_IDX 2
#define mmCM3_CM_BLNDGAM_RAMB_START_CNTL_B 0x11ef
#define mmCM3_CM_BLNDGAM_RAMB_START_CNTL_B_BASE_IDX 2
#define mmCM3_CM_BLNDGAM_RAMB_START_CNTL_G 0x11f0
#define mmCM3_CM_BLNDGAM_RAMB_START_CNTL_G_BASE_IDX 2
#define mmCM3_CM_BLNDGAM_RAMB_START_CNTL_R 0x11f1
#define mmCM3_CM_BLNDGAM_RAMB_START_CNTL_R_BASE_IDX 2
#define mmCM3_CM_BLNDGAM_RAMB_START_SLOPE_CNTL_B 0x11f2
#define mmCM3_CM_BLNDGAM_RAMB_START_SLOPE_CNTL_B_BASE_IDX 2
#define mmCM3_CM_BLNDGAM_RAMB_START_SLOPE_CNTL_G 0x11f3
#define mmCM3_CM_BLNDGAM_RAMB_START_SLOPE_CNTL_G_BASE_IDX 2
#define mmCM3_CM_BLNDGAM_RAMB_START_SLOPE_CNTL_R 0x11f4
#define mmCM3_CM_BLNDGAM_RAMB_START_SLOPE_CNTL_R_BASE_IDX 2
#define mmCM3_CM_BLNDGAM_RAMB_START_BASE_CNTL_B 0x11f5
#define mmCM3_CM_BLNDGAM_RAMB_START_BASE_CNTL_B_BASE_IDX 2
#define mmCM3_CM_BLNDGAM_RAMB_START_BASE_CNTL_G 0x11f6
#define mmCM3_CM_BLNDGAM_RAMB_START_BASE_CNTL_G_BASE_IDX 2
#define mmCM3_CM_BLNDGAM_RAMB_START_BASE_CNTL_R 0x11f7
#define mmCM3_CM_BLNDGAM_RAMB_START_BASE_CNTL_R_BASE_IDX 2
#define mmCM3_CM_BLNDGAM_RAMB_END_CNTL1_B 0x11f8
#define mmCM3_CM_BLNDGAM_RAMB_END_CNTL1_B_BASE_IDX 2
#define mmCM3_CM_BLNDGAM_RAMB_END_CNTL2_B 0x11f9
#define mmCM3_CM_BLNDGAM_RAMB_END_CNTL2_B_BASE_IDX 2
#define mmCM3_CM_BLNDGAM_RAMB_END_CNTL1_G 0x11fa
#define mmCM3_CM_BLNDGAM_RAMB_END_CNTL1_G_BASE_IDX 2
#define mmCM3_CM_BLNDGAM_RAMB_END_CNTL2_G 0x11fb
#define mmCM3_CM_BLNDGAM_RAMB_END_CNTL2_G_BASE_IDX 2
#define mmCM3_CM_BLNDGAM_RAMB_END_CNTL1_R 0x11fc
#define mmCM3_CM_BLNDGAM_RAMB_END_CNTL1_R_BASE_IDX 2
#define mmCM3_CM_BLNDGAM_RAMB_END_CNTL2_R 0x11fd
#define mmCM3_CM_BLNDGAM_RAMB_END_CNTL2_R_BASE_IDX 2
#define mmCM3_CM_BLNDGAM_RAMB_OFFSET_B 0x11fe
#define mmCM3_CM_BLNDGAM_RAMB_OFFSET_B_BASE_IDX 2
#define mmCM3_CM_BLNDGAM_RAMB_OFFSET_G 0x11ff
#define mmCM3_CM_BLNDGAM_RAMB_OFFSET_G_BASE_IDX 2
#define mmCM3_CM_BLNDGAM_RAMB_OFFSET_R 0x1200
#define mmCM3_CM_BLNDGAM_RAMB_OFFSET_R_BASE_IDX 2
#define mmCM3_CM_BLNDGAM_RAMB_REGION_0_1 0x1201
#define mmCM3_CM_BLNDGAM_RAMB_REGION_0_1_BASE_IDX 2
#define mmCM3_CM_BLNDGAM_RAMB_REGION_2_3 0x1202
#define mmCM3_CM_BLNDGAM_RAMB_REGION_2_3_BASE_IDX 2
#define mmCM3_CM_BLNDGAM_RAMB_REGION_4_5 0x1203
#define mmCM3_CM_BLNDGAM_RAMB_REGION_4_5_BASE_IDX 2
#define mmCM3_CM_BLNDGAM_RAMB_REGION_6_7 0x1204
#define mmCM3_CM_BLNDGAM_RAMB_REGION_6_7_BASE_IDX 2
#define mmCM3_CM_BLNDGAM_RAMB_REGION_8_9 0x1205
#define mmCM3_CM_BLNDGAM_RAMB_REGION_8_9_BASE_IDX 2
#define mmCM3_CM_BLNDGAM_RAMB_REGION_10_11 0x1206
#define mmCM3_CM_BLNDGAM_RAMB_REGION_10_11_BASE_IDX 2
#define mmCM3_CM_BLNDGAM_RAMB_REGION_12_13 0x1207
#define mmCM3_CM_BLNDGAM_RAMB_REGION_12_13_BASE_IDX 2
#define mmCM3_CM_BLNDGAM_RAMB_REGION_14_15 0x1208
#define mmCM3_CM_BLNDGAM_RAMB_REGION_14_15_BASE_IDX 2
#define mmCM3_CM_BLNDGAM_RAMB_REGION_16_17 0x1209
#define mmCM3_CM_BLNDGAM_RAMB_REGION_16_17_BASE_IDX 2
#define mmCM3_CM_BLNDGAM_RAMB_REGION_18_19 0x120a
#define mmCM3_CM_BLNDGAM_RAMB_REGION_18_19_BASE_IDX 2
#define mmCM3_CM_BLNDGAM_RAMB_REGION_20_21 0x120b
#define mmCM3_CM_BLNDGAM_RAMB_REGION_20_21_BASE_IDX 2
#define mmCM3_CM_BLNDGAM_RAMB_REGION_22_23 0x120c
#define mmCM3_CM_BLNDGAM_RAMB_REGION_22_23_BASE_IDX 2
#define mmCM3_CM_BLNDGAM_RAMB_REGION_24_25 0x120d
#define mmCM3_CM_BLNDGAM_RAMB_REGION_24_25_BASE_IDX 2
#define mmCM3_CM_BLNDGAM_RAMB_REGION_26_27 0x120e
#define mmCM3_CM_BLNDGAM_RAMB_REGION_26_27_BASE_IDX 2
#define mmCM3_CM_BLNDGAM_RAMB_REGION_28_29 0x120f
#define mmCM3_CM_BLNDGAM_RAMB_REGION_28_29_BASE_IDX 2
#define mmCM3_CM_BLNDGAM_RAMB_REGION_30_31 0x1210
#define mmCM3_CM_BLNDGAM_RAMB_REGION_30_31_BASE_IDX 2
#define mmCM3_CM_BLNDGAM_RAMB_REGION_32_33 0x1211
#define mmCM3_CM_BLNDGAM_RAMB_REGION_32_33_BASE_IDX 2
#define mmCM3_CM_HDR_MULT_COEF 0x1212
#define mmCM3_CM_HDR_MULT_COEF_BASE_IDX 2
#define mmCM3_CM_MEM_PWR_CTRL 0x1213
#define mmCM3_CM_MEM_PWR_CTRL_BASE_IDX 2
#define mmCM3_CM_MEM_PWR_STATUS 0x1214
#define mmCM3_CM_MEM_PWR_STATUS_BASE_IDX 2
#define mmCM3_CM_DEALPHA 0x1216
#define mmCM3_CM_DEALPHA_BASE_IDX 2
#define mmCM3_CM_COEF_FORMAT 0x1217
#define mmCM3_CM_COEF_FORMAT_BASE_IDX 2
#define mmCM3_CM_SHAPER_CONTROL 0x1218
#define mmCM3_CM_SHAPER_CONTROL_BASE_IDX 2
#define mmCM3_CM_SHAPER_OFFSET_R 0x1219
#define mmCM3_CM_SHAPER_OFFSET_R_BASE_IDX 2
#define mmCM3_CM_SHAPER_OFFSET_G 0x121a
#define mmCM3_CM_SHAPER_OFFSET_G_BASE_IDX 2
#define mmCM3_CM_SHAPER_OFFSET_B 0x121b
#define mmCM3_CM_SHAPER_OFFSET_B_BASE_IDX 2
#define mmCM3_CM_SHAPER_SCALE_R 0x121c
#define mmCM3_CM_SHAPER_SCALE_R_BASE_IDX 2
#define mmCM3_CM_SHAPER_SCALE_G_B 0x121d
#define mmCM3_CM_SHAPER_SCALE_G_B_BASE_IDX 2
#define mmCM3_CM_SHAPER_LUT_INDEX 0x121e
#define mmCM3_CM_SHAPER_LUT_INDEX_BASE_IDX 2
#define mmCM3_CM_SHAPER_LUT_DATA 0x121f
#define mmCM3_CM_SHAPER_LUT_DATA_BASE_IDX 2
#define mmCM3_CM_SHAPER_LUT_WRITE_EN_MASK 0x1220
#define mmCM3_CM_SHAPER_LUT_WRITE_EN_MASK_BASE_IDX 2
#define mmCM3_CM_SHAPER_RAMA_START_CNTL_B 0x1221
#define mmCM3_CM_SHAPER_RAMA_START_CNTL_B_BASE_IDX 2
#define mmCM3_CM_SHAPER_RAMA_START_CNTL_G 0x1222
#define mmCM3_CM_SHAPER_RAMA_START_CNTL_G_BASE_IDX 2
#define mmCM3_CM_SHAPER_RAMA_START_CNTL_R 0x1223
#define mmCM3_CM_SHAPER_RAMA_START_CNTL_R_BASE_IDX 2
#define mmCM3_CM_SHAPER_RAMA_END_CNTL_B 0x1224
#define mmCM3_CM_SHAPER_RAMA_END_CNTL_B_BASE_IDX 2
#define mmCM3_CM_SHAPER_RAMA_END_CNTL_G 0x1225
#define mmCM3_CM_SHAPER_RAMA_END_CNTL_G_BASE_IDX 2
#define mmCM3_CM_SHAPER_RAMA_END_CNTL_R 0x1226
#define mmCM3_CM_SHAPER_RAMA_END_CNTL_R_BASE_IDX 2
#define mmCM3_CM_SHAPER_RAMA_REGION_0_1 0x1227
#define mmCM3_CM_SHAPER_RAMA_REGION_0_1_BASE_IDX 2
#define mmCM3_CM_SHAPER_RAMA_REGION_2_3 0x1228
#define mmCM3_CM_SHAPER_RAMA_REGION_2_3_BASE_IDX 2
#define mmCM3_CM_SHAPER_RAMA_REGION_4_5 0x1229
#define mmCM3_CM_SHAPER_RAMA_REGION_4_5_BASE_IDX 2
#define mmCM3_CM_SHAPER_RAMA_REGION_6_7 0x122a
#define mmCM3_CM_SHAPER_RAMA_REGION_6_7_BASE_IDX 2
#define mmCM3_CM_SHAPER_RAMA_REGION_8_9 0x122b
#define mmCM3_CM_SHAPER_RAMA_REGION_8_9_BASE_IDX 2
#define mmCM3_CM_SHAPER_RAMA_REGION_10_11 0x122c
#define mmCM3_CM_SHAPER_RAMA_REGION_10_11_BASE_IDX 2
#define mmCM3_CM_SHAPER_RAMA_REGION_12_13 0x122d
#define mmCM3_CM_SHAPER_RAMA_REGION_12_13_BASE_IDX 2
#define mmCM3_CM_SHAPER_RAMA_REGION_14_15 0x122e
#define mmCM3_CM_SHAPER_RAMA_REGION_14_15_BASE_IDX 2
#define mmCM3_CM_SHAPER_RAMA_REGION_16_17 0x122f
#define mmCM3_CM_SHAPER_RAMA_REGION_16_17_BASE_IDX 2
#define mmCM3_CM_SHAPER_RAMA_REGION_18_19 0x1230
#define mmCM3_CM_SHAPER_RAMA_REGION_18_19_BASE_IDX 2
#define mmCM3_CM_SHAPER_RAMA_REGION_20_21 0x1231
#define mmCM3_CM_SHAPER_RAMA_REGION_20_21_BASE_IDX 2
#define mmCM3_CM_SHAPER_RAMA_REGION_22_23 0x1232
#define mmCM3_CM_SHAPER_RAMA_REGION_22_23_BASE_IDX 2
#define mmCM3_CM_SHAPER_RAMA_REGION_24_25 0x1233
#define mmCM3_CM_SHAPER_RAMA_REGION_24_25_BASE_IDX 2
#define mmCM3_CM_SHAPER_RAMA_REGION_26_27 0x1234
#define mmCM3_CM_SHAPER_RAMA_REGION_26_27_BASE_IDX 2
#define mmCM3_CM_SHAPER_RAMA_REGION_28_29 0x1235
#define mmCM3_CM_SHAPER_RAMA_REGION_28_29_BASE_IDX 2
#define mmCM3_CM_SHAPER_RAMA_REGION_30_31 0x1236
#define mmCM3_CM_SHAPER_RAMA_REGION_30_31_BASE_IDX 2
#define mmCM3_CM_SHAPER_RAMA_REGION_32_33 0x1237
#define mmCM3_CM_SHAPER_RAMA_REGION_32_33_BASE_IDX 2
#define mmCM3_CM_SHAPER_RAMB_START_CNTL_B 0x1238
#define mmCM3_CM_SHAPER_RAMB_START_CNTL_B_BASE_IDX 2
#define mmCM3_CM_SHAPER_RAMB_START_CNTL_G 0x1239
#define mmCM3_CM_SHAPER_RAMB_START_CNTL_G_BASE_IDX 2
#define mmCM3_CM_SHAPER_RAMB_START_CNTL_R 0x123a
#define mmCM3_CM_SHAPER_RAMB_START_CNTL_R_BASE_IDX 2
#define mmCM3_CM_SHAPER_RAMB_END_CNTL_B 0x123b
#define mmCM3_CM_SHAPER_RAMB_END_CNTL_B_BASE_IDX 2
#define mmCM3_CM_SHAPER_RAMB_END_CNTL_G 0x123c
#define mmCM3_CM_SHAPER_RAMB_END_CNTL_G_BASE_IDX 2
#define mmCM3_CM_SHAPER_RAMB_END_CNTL_R 0x123d
#define mmCM3_CM_SHAPER_RAMB_END_CNTL_R_BASE_IDX 2
#define mmCM3_CM_SHAPER_RAMB_REGION_0_1 0x123e
#define mmCM3_CM_SHAPER_RAMB_REGION_0_1_BASE_IDX 2
#define mmCM3_CM_SHAPER_RAMB_REGION_2_3 0x123f
#define mmCM3_CM_SHAPER_RAMB_REGION_2_3_BASE_IDX 2
#define mmCM3_CM_SHAPER_RAMB_REGION_4_5 0x1240
#define mmCM3_CM_SHAPER_RAMB_REGION_4_5_BASE_IDX 2
#define mmCM3_CM_SHAPER_RAMB_REGION_6_7 0x1241
#define mmCM3_CM_SHAPER_RAMB_REGION_6_7_BASE_IDX 2
#define mmCM3_CM_SHAPER_RAMB_REGION_8_9 0x1242
#define mmCM3_CM_SHAPER_RAMB_REGION_8_9_BASE_IDX 2
#define mmCM3_CM_SHAPER_RAMB_REGION_10_11 0x1243
#define mmCM3_CM_SHAPER_RAMB_REGION_10_11_BASE_IDX 2
#define mmCM3_CM_SHAPER_RAMB_REGION_12_13 0x1244
#define mmCM3_CM_SHAPER_RAMB_REGION_12_13_BASE_IDX 2
#define mmCM3_CM_SHAPER_RAMB_REGION_14_15 0x1245
#define mmCM3_CM_SHAPER_RAMB_REGION_14_15_BASE_IDX 2
#define mmCM3_CM_SHAPER_RAMB_REGION_16_17 0x1246
#define mmCM3_CM_SHAPER_RAMB_REGION_16_17_BASE_IDX 2
#define mmCM3_CM_SHAPER_RAMB_REGION_18_19 0x1247
#define mmCM3_CM_SHAPER_RAMB_REGION_18_19_BASE_IDX 2
#define mmCM3_CM_SHAPER_RAMB_REGION_20_21 0x1248
#define mmCM3_CM_SHAPER_RAMB_REGION_20_21_BASE_IDX 2
#define mmCM3_CM_SHAPER_RAMB_REGION_22_23 0x1249
#define mmCM3_CM_SHAPER_RAMB_REGION_22_23_BASE_IDX 2
#define mmCM3_CM_SHAPER_RAMB_REGION_24_25 0x124a
#define mmCM3_CM_SHAPER_RAMB_REGION_24_25_BASE_IDX 2
#define mmCM3_CM_SHAPER_RAMB_REGION_26_27 0x124b
#define mmCM3_CM_SHAPER_RAMB_REGION_26_27_BASE_IDX 2
#define mmCM3_CM_SHAPER_RAMB_REGION_28_29 0x124c
#define mmCM3_CM_SHAPER_RAMB_REGION_28_29_BASE_IDX 2
#define mmCM3_CM_SHAPER_RAMB_REGION_30_31 0x124d
#define mmCM3_CM_SHAPER_RAMB_REGION_30_31_BASE_IDX 2
#define mmCM3_CM_SHAPER_RAMB_REGION_32_33 0x124e
#define mmCM3_CM_SHAPER_RAMB_REGION_32_33_BASE_IDX 2
#define mmCM3_CM_MEM_PWR_CTRL2 0x124f
#define mmCM3_CM_MEM_PWR_CTRL2_BASE_IDX 2
#define mmCM3_CM_MEM_PWR_STATUS2 0x1250
#define mmCM3_CM_MEM_PWR_STATUS2_BASE_IDX 2
#define mmCM3_CM_3DLUT_MODE 0x1251
#define mmCM3_CM_3DLUT_MODE_BASE_IDX 2
#define mmCM3_CM_3DLUT_INDEX 0x1252
#define mmCM3_CM_3DLUT_INDEX_BASE_IDX 2
#define mmCM3_CM_3DLUT_DATA 0x1253
#define mmCM3_CM_3DLUT_DATA_BASE_IDX 2
#define mmCM3_CM_3DLUT_DATA_30BIT 0x1254
#define mmCM3_CM_3DLUT_DATA_30BIT_BASE_IDX 2
#define mmCM3_CM_3DLUT_READ_WRITE_CONTROL 0x1255
#define mmCM3_CM_3DLUT_READ_WRITE_CONTROL_BASE_IDX 2
#define mmCM3_CM_3DLUT_OUT_NORM_FACTOR 0x1256
#define mmCM3_CM_3DLUT_OUT_NORM_FACTOR_BASE_IDX 2
#define mmCM3_CM_3DLUT_OUT_OFFSET_R 0x1257
#define mmCM3_CM_3DLUT_OUT_OFFSET_R_BASE_IDX 2
#define mmCM3_CM_3DLUT_OUT_OFFSET_G 0x1258
#define mmCM3_CM_3DLUT_OUT_OFFSET_G_BASE_IDX 2
#define mmCM3_CM_3DLUT_OUT_OFFSET_B 0x1259
#define mmCM3_CM_3DLUT_OUT_OFFSET_B_BASE_IDX 2
// addressBlock: dce_dc_dpp3_dispdec_dpp_dcperfmon_dc_perfmon_dispdec
// base address: 0x4994
#define mmDC_PERFMON14_PERFCOUNTER_CNTL 0x1265
#define mmDC_PERFMON14_PERFCOUNTER_CNTL_BASE_IDX 2
#define mmDC_PERFMON14_PERFCOUNTER_CNTL2 0x1266
#define mmDC_PERFMON14_PERFCOUNTER_CNTL2_BASE_IDX 2
#define mmDC_PERFMON14_PERFCOUNTER_STATE 0x1267
#define mmDC_PERFMON14_PERFCOUNTER_STATE_BASE_IDX 2
#define mmDC_PERFMON14_PERFMON_CNTL 0x1268
#define mmDC_PERFMON14_PERFMON_CNTL_BASE_IDX 2
#define mmDC_PERFMON14_PERFMON_CNTL2 0x1269
#define mmDC_PERFMON14_PERFMON_CNTL2_BASE_IDX 2
#define mmDC_PERFMON14_PERFMON_CVALUE_INT_MISC 0x126a
#define mmDC_PERFMON14_PERFMON_CVALUE_INT_MISC_BASE_IDX 2
#define mmDC_PERFMON14_PERFMON_CVALUE_LOW 0x126b
#define mmDC_PERFMON14_PERFMON_CVALUE_LOW_BASE_IDX 2
#define mmDC_PERFMON14_PERFMON_HI 0x126c
#define mmDC_PERFMON14_PERFMON_HI_BASE_IDX 2
#define mmDC_PERFMON14_PERFMON_LOW 0x126d
#define mmDC_PERFMON14_PERFMON_LOW_BASE_IDX 2
// addressBlock: dce_dc_dpp4_dispdec_dpp_top_dispdec
// base address: 0x16b0
#define mmDPP_TOP4_DPP_CONTROL 0x1271
#define mmDPP_TOP4_DPP_CONTROL_BASE_IDX 2
#define mmDPP_TOP4_DPP_SOFT_RESET 0x1272
#define mmDPP_TOP4_DPP_SOFT_RESET_BASE_IDX 2
#define mmDPP_TOP4_DPP_CRC_VAL_R_G 0x1273
#define mmDPP_TOP4_DPP_CRC_VAL_R_G_BASE_IDX 2
#define mmDPP_TOP4_DPP_CRC_VAL_B_A 0x1274
#define mmDPP_TOP4_DPP_CRC_VAL_B_A_BASE_IDX 2
#define mmDPP_TOP4_DPP_CRC_CTRL 0x1275
#define mmDPP_TOP4_DPP_CRC_CTRL_BASE_IDX 2
#define mmDPP_TOP4_HOST_READ_CONTROL 0x1276
#define mmDPP_TOP4_HOST_READ_CONTROL_BASE_IDX 2
// addressBlock: dce_dc_dpp4_dispdec_cnvc_cfg_dispdec
// base address: 0x16b0
#define mmCNVC_CFG4_CNVC_SURFACE_PIXEL_FORMAT 0x127b
#define mmCNVC_CFG4_CNVC_SURFACE_PIXEL_FORMAT_BASE_IDX 2
#define mmCNVC_CFG4_FORMAT_CONTROL 0x127c
#define mmCNVC_CFG4_FORMAT_CONTROL_BASE_IDX 2
#define mmCNVC_CFG4_FCNV_FP_BIAS_R 0x127d
#define mmCNVC_CFG4_FCNV_FP_BIAS_R_BASE_IDX 2
#define mmCNVC_CFG4_FCNV_FP_BIAS_G 0x127e
#define mmCNVC_CFG4_FCNV_FP_BIAS_G_BASE_IDX 2
#define mmCNVC_CFG4_FCNV_FP_BIAS_B 0x127f
#define mmCNVC_CFG4_FCNV_FP_BIAS_B_BASE_IDX 2
#define mmCNVC_CFG4_FCNV_FP_SCALE_R 0x1280
#define mmCNVC_CFG4_FCNV_FP_SCALE_R_BASE_IDX 2
#define mmCNVC_CFG4_FCNV_FP_SCALE_G 0x1281
#define mmCNVC_CFG4_FCNV_FP_SCALE_G_BASE_IDX 2
#define mmCNVC_CFG4_FCNV_FP_SCALE_B 0x1282
#define mmCNVC_CFG4_FCNV_FP_SCALE_B_BASE_IDX 2
#define mmCNVC_CFG4_COLOR_KEYER_CONTROL 0x1283
#define mmCNVC_CFG4_COLOR_KEYER_CONTROL_BASE_IDX 2
#define mmCNVC_CFG4_COLOR_KEYER_ALPHA 0x1284
#define mmCNVC_CFG4_COLOR_KEYER_ALPHA_BASE_IDX 2
#define mmCNVC_CFG4_COLOR_KEYER_RED 0x1285
#define mmCNVC_CFG4_COLOR_KEYER_RED_BASE_IDX 2
#define mmCNVC_CFG4_COLOR_KEYER_GREEN 0x1286
#define mmCNVC_CFG4_COLOR_KEYER_GREEN_BASE_IDX 2
#define mmCNVC_CFG4_COLOR_KEYER_BLUE 0x1287
#define mmCNVC_CFG4_COLOR_KEYER_BLUE_BASE_IDX 2
#define mmCNVC_CFG4_ALPHA_2BIT_LUT 0x1289
#define mmCNVC_CFG4_ALPHA_2BIT_LUT_BASE_IDX 2
#define mmCNVC_CFG4_PRE_DEALPHA 0x128a
#define mmCNVC_CFG4_PRE_DEALPHA_BASE_IDX 2
#define mmCNVC_CFG4_PRE_CSC_MODE 0x128b
#define mmCNVC_CFG4_PRE_CSC_MODE_BASE_IDX 2
#define mmCNVC_CFG4_PRE_CSC_C11_C12 0x128c
#define mmCNVC_CFG4_PRE_CSC_C11_C12_BASE_IDX 2
#define mmCNVC_CFG4_PRE_CSC_C13_C14 0x128d
#define mmCNVC_CFG4_PRE_CSC_C13_C14_BASE_IDX 2
#define mmCNVC_CFG4_PRE_CSC_C21_C22 0x128e
#define mmCNVC_CFG4_PRE_CSC_C21_C22_BASE_IDX 2
#define mmCNVC_CFG4_PRE_CSC_C23_C24 0x128f
#define mmCNVC_CFG4_PRE_CSC_C23_C24_BASE_IDX 2
#define mmCNVC_CFG4_PRE_CSC_C31_C32 0x1290
#define mmCNVC_CFG4_PRE_CSC_C31_C32_BASE_IDX 2
#define mmCNVC_CFG4_PRE_CSC_C33_C34 0x1291
#define mmCNVC_CFG4_PRE_CSC_C33_C34_BASE_IDX 2
#define mmCNVC_CFG4_PRE_CSC_B_C11_C12 0x1292
#define mmCNVC_CFG4_PRE_CSC_B_C11_C12_BASE_IDX 2
#define mmCNVC_CFG4_PRE_CSC_B_C13_C14 0x1293
#define mmCNVC_CFG4_PRE_CSC_B_C13_C14_BASE_IDX 2
#define mmCNVC_CFG4_PRE_CSC_B_C21_C22 0x1294
#define mmCNVC_CFG4_PRE_CSC_B_C21_C22_BASE_IDX 2
#define mmCNVC_CFG4_PRE_CSC_B_C23_C24 0x1295
#define mmCNVC_CFG4_PRE_CSC_B_C23_C24_BASE_IDX 2
#define mmCNVC_CFG4_PRE_CSC_B_C31_C32 0x1296
#define mmCNVC_CFG4_PRE_CSC_B_C31_C32_BASE_IDX 2
#define mmCNVC_CFG4_PRE_CSC_B_C33_C34 0x1297
#define mmCNVC_CFG4_PRE_CSC_B_C33_C34_BASE_IDX 2
#define mmCNVC_CFG4_CNVC_COEF_FORMAT 0x1298
#define mmCNVC_CFG4_CNVC_COEF_FORMAT_BASE_IDX 2
#define mmCNVC_CFG4_PRE_DEGAM 0x1299
#define mmCNVC_CFG4_PRE_DEGAM_BASE_IDX 2
#define mmCNVC_CFG4_PRE_REALPHA 0x129a
#define mmCNVC_CFG4_PRE_REALPHA_BASE_IDX 2
// addressBlock: dce_dc_dpp4_dispdec_cnvc_cur_dispdec
// base address: 0x16b0
#define mmCNVC_CUR4_CURSOR0_CONTROL 0x129d
#define mmCNVC_CUR4_CURSOR0_CONTROL_BASE_IDX 2
#define mmCNVC_CUR4_CURSOR0_COLOR0 0x129e
#define mmCNVC_CUR4_CURSOR0_COLOR0_BASE_IDX 2
#define mmCNVC_CUR4_CURSOR0_COLOR1 0x129f
#define mmCNVC_CUR4_CURSOR0_COLOR1_BASE_IDX 2
#define mmCNVC_CUR4_CURSOR0_FP_SCALE_BIAS 0x12a0
#define mmCNVC_CUR4_CURSOR0_FP_SCALE_BIAS_BASE_IDX 2
// addressBlock: dce_dc_dpp4_dispdec_dscl_dispdec
// base address: 0x16b0
#define mmDSCL4_SCL_COEF_RAM_TAP_SELECT 0x12a5
#define mmDSCL4_SCL_COEF_RAM_TAP_SELECT_BASE_IDX 2
#define mmDSCL4_SCL_COEF_RAM_TAP_DATA 0x12a6
#define mmDSCL4_SCL_COEF_RAM_TAP_DATA_BASE_IDX 2
#define mmDSCL4_SCL_MODE 0x12a7
#define mmDSCL4_SCL_MODE_BASE_IDX 2
#define mmDSCL4_SCL_TAP_CONTROL 0x12a8
#define mmDSCL4_SCL_TAP_CONTROL_BASE_IDX 2
#define mmDSCL4_DSCL_CONTROL 0x12a9
#define mmDSCL4_DSCL_CONTROL_BASE_IDX 2
#define mmDSCL4_DSCL_2TAP_CONTROL 0x12aa
#define mmDSCL4_DSCL_2TAP_CONTROL_BASE_IDX 2
#define mmDSCL4_SCL_MANUAL_REPLICATE_CONTROL 0x12ab
#define mmDSCL4_SCL_MANUAL_REPLICATE_CONTROL_BASE_IDX 2
#define mmDSCL4_SCL_HORZ_FILTER_SCALE_RATIO 0x12ac
#define mmDSCL4_SCL_HORZ_FILTER_SCALE_RATIO_BASE_IDX 2
#define mmDSCL4_SCL_HORZ_FILTER_INIT 0x12ad
#define mmDSCL4_SCL_HORZ_FILTER_INIT_BASE_IDX 2
#define mmDSCL4_SCL_HORZ_FILTER_SCALE_RATIO_C 0x12ae
#define mmDSCL4_SCL_HORZ_FILTER_SCALE_RATIO_C_BASE_IDX 2
#define mmDSCL4_SCL_HORZ_FILTER_INIT_C 0x12af
#define mmDSCL4_SCL_HORZ_FILTER_INIT_C_BASE_IDX 2
#define mmDSCL4_SCL_VERT_FILTER_SCALE_RATIO 0x12b0
#define mmDSCL4_SCL_VERT_FILTER_SCALE_RATIO_BASE_IDX 2
#define mmDSCL4_SCL_VERT_FILTER_INIT 0x12b1
#define mmDSCL4_SCL_VERT_FILTER_INIT_BASE_IDX 2
#define mmDSCL4_SCL_VERT_FILTER_INIT_BOT 0x12b2
#define mmDSCL4_SCL_VERT_FILTER_INIT_BOT_BASE_IDX 2
#define mmDSCL4_SCL_VERT_FILTER_SCALE_RATIO_C 0x12b3
#define mmDSCL4_SCL_VERT_FILTER_SCALE_RATIO_C_BASE_IDX 2
#define mmDSCL4_SCL_VERT_FILTER_INIT_C 0x12b4
#define mmDSCL4_SCL_VERT_FILTER_INIT_C_BASE_IDX 2
#define mmDSCL4_SCL_VERT_FILTER_INIT_BOT_C 0x12b5
#define mmDSCL4_SCL_VERT_FILTER_INIT_BOT_C_BASE_IDX 2
#define mmDSCL4_SCL_BLACK_COLOR 0x12b6
#define mmDSCL4_SCL_BLACK_COLOR_BASE_IDX 2
#define mmDSCL4_DSCL_UPDATE 0x12b7
#define mmDSCL4_DSCL_UPDATE_BASE_IDX 2
#define mmDSCL4_DSCL_AUTOCAL 0x12b8
#define mmDSCL4_DSCL_AUTOCAL_BASE_IDX 2
#define mmDSCL4_DSCL_EXT_OVERSCAN_LEFT_RIGHT 0x12b9
#define mmDSCL4_DSCL_EXT_OVERSCAN_LEFT_RIGHT_BASE_IDX 2
#define mmDSCL4_DSCL_EXT_OVERSCAN_TOP_BOTTOM 0x12ba
#define mmDSCL4_DSCL_EXT_OVERSCAN_TOP_BOTTOM_BASE_IDX 2
#define mmDSCL4_OTG_H_BLANK 0x12bb
#define mmDSCL4_OTG_H_BLANK_BASE_IDX 2
#define mmDSCL4_OTG_V_BLANK 0x12bc
#define mmDSCL4_OTG_V_BLANK_BASE_IDX 2
#define mmDSCL4_RECOUT_START 0x12bd
#define mmDSCL4_RECOUT_START_BASE_IDX 2
#define mmDSCL4_RECOUT_SIZE 0x12be
#define mmDSCL4_RECOUT_SIZE_BASE_IDX 2
#define mmDSCL4_MPC_SIZE 0x12bf
#define mmDSCL4_MPC_SIZE_BASE_IDX 2
#define mmDSCL4_LB_DATA_FORMAT 0x12c0
#define mmDSCL4_LB_DATA_FORMAT_BASE_IDX 2
#define mmDSCL4_LB_MEMORY_CTRL 0x12c1
#define mmDSCL4_LB_MEMORY_CTRL_BASE_IDX 2
#define mmDSCL4_LB_V_COUNTER 0x12c2
#define mmDSCL4_LB_V_COUNTER_BASE_IDX 2
#define mmDSCL4_DSCL_MEM_PWR_CTRL 0x12c3
#define mmDSCL4_DSCL_MEM_PWR_CTRL_BASE_IDX 2
#define mmDSCL4_DSCL_MEM_PWR_STATUS 0x12c4
#define mmDSCL4_DSCL_MEM_PWR_STATUS_BASE_IDX 2
#define mmDSCL4_OBUF_CONTROL 0x12c5
#define mmDSCL4_OBUF_CONTROL_BASE_IDX 2
#define mmDSCL4_OBUF_MEM_PWR_CTRL 0x12c6
#define mmDSCL4_OBUF_MEM_PWR_CTRL_BASE_IDX 2
// addressBlock: dce_dc_dpp4_dispdec_cm_dispdec
// base address: 0x16b0
#define mmCM4_CM_CONTROL 0x12cc
#define mmCM4_CM_CONTROL_BASE_IDX 2
#define mmCM4_CM_POST_CSC_CONTROL 0x12cd
#define mmCM4_CM_POST_CSC_CONTROL_BASE_IDX 2
#define mmCM4_CM_POST_CSC_C11_C12 0x12ce
#define mmCM4_CM_POST_CSC_C11_C12_BASE_IDX 2
#define mmCM4_CM_POST_CSC_C13_C14 0x12cf
#define mmCM4_CM_POST_CSC_C13_C14_BASE_IDX 2
#define mmCM4_CM_POST_CSC_C21_C22 0x12d0
#define mmCM4_CM_POST_CSC_C21_C22_BASE_IDX 2
#define mmCM4_CM_POST_CSC_C23_C24 0x12d1
#define mmCM4_CM_POST_CSC_C23_C24_BASE_IDX 2
#define mmCM4_CM_POST_CSC_C31_C32 0x12d2
#define mmCM4_CM_POST_CSC_C31_C32_BASE_IDX 2
#define mmCM4_CM_POST_CSC_C33_C34 0x12d3
#define mmCM4_CM_POST_CSC_C33_C34_BASE_IDX 2
#define mmCM4_CM_POST_CSC_B_C11_C12 0x12d4
#define mmCM4_CM_POST_CSC_B_C11_C12_BASE_IDX 2
#define mmCM4_CM_POST_CSC_B_C13_C14 0x12d5
#define mmCM4_CM_POST_CSC_B_C13_C14_BASE_IDX 2
#define mmCM4_CM_POST_CSC_B_C21_C22 0x12d6
#define mmCM4_CM_POST_CSC_B_C21_C22_BASE_IDX 2
#define mmCM4_CM_POST_CSC_B_C23_C24 0x12d7
#define mmCM4_CM_POST_CSC_B_C23_C24_BASE_IDX 2
#define mmCM4_CM_POST_CSC_B_C31_C32 0x12d8
#define mmCM4_CM_POST_CSC_B_C31_C32_BASE_IDX 2
#define mmCM4_CM_POST_CSC_B_C33_C34 0x12d9
#define mmCM4_CM_POST_CSC_B_C33_C34_BASE_IDX 2
#define mmCM4_CM_GAMUT_REMAP_CONTROL 0x12da
#define mmCM4_CM_GAMUT_REMAP_CONTROL_BASE_IDX 2
#define mmCM4_CM_GAMUT_REMAP_C11_C12 0x12db
#define mmCM4_CM_GAMUT_REMAP_C11_C12_BASE_IDX 2
#define mmCM4_CM_GAMUT_REMAP_C13_C14 0x12dc
#define mmCM4_CM_GAMUT_REMAP_C13_C14_BASE_IDX 2
#define mmCM4_CM_GAMUT_REMAP_C21_C22 0x12dd
#define mmCM4_CM_GAMUT_REMAP_C21_C22_BASE_IDX 2
#define mmCM4_CM_GAMUT_REMAP_C23_C24 0x12de
#define mmCM4_CM_GAMUT_REMAP_C23_C24_BASE_IDX 2
#define mmCM4_CM_GAMUT_REMAP_C31_C32 0x12df
#define mmCM4_CM_GAMUT_REMAP_C31_C32_BASE_IDX 2
#define mmCM4_CM_GAMUT_REMAP_C33_C34 0x12e0
#define mmCM4_CM_GAMUT_REMAP_C33_C34_BASE_IDX 2
#define mmCM4_CM_GAMUT_REMAP_B_C11_C12 0x12e1
#define mmCM4_CM_GAMUT_REMAP_B_C11_C12_BASE_IDX 2
#define mmCM4_CM_GAMUT_REMAP_B_C13_C14 0x12e2
#define mmCM4_CM_GAMUT_REMAP_B_C13_C14_BASE_IDX 2
#define mmCM4_CM_GAMUT_REMAP_B_C21_C22 0x12e3
#define mmCM4_CM_GAMUT_REMAP_B_C21_C22_BASE_IDX 2
#define mmCM4_CM_GAMUT_REMAP_B_C23_C24 0x12e4
#define mmCM4_CM_GAMUT_REMAP_B_C23_C24_BASE_IDX 2
#define mmCM4_CM_GAMUT_REMAP_B_C31_C32 0x12e5
#define mmCM4_CM_GAMUT_REMAP_B_C31_C32_BASE_IDX 2
#define mmCM4_CM_GAMUT_REMAP_B_C33_C34 0x12e6
#define mmCM4_CM_GAMUT_REMAP_B_C33_C34_BASE_IDX 2
#define mmCM4_CM_BIAS_CR_R 0x12e7
#define mmCM4_CM_BIAS_CR_R_BASE_IDX 2
#define mmCM4_CM_BIAS_Y_G_CB_B 0x12e8
#define mmCM4_CM_BIAS_Y_G_CB_B_BASE_IDX 2
#define mmCM4_CM_GAMCOR_CONTROL 0x12e9
#define mmCM4_CM_GAMCOR_CONTROL_BASE_IDX 2
#define mmCM4_CM_GAMCOR_LUT_INDEX 0x12ea
#define mmCM4_CM_GAMCOR_LUT_INDEX_BASE_IDX 2
#define mmCM4_CM_GAMCOR_LUT_DATA 0x12eb
#define mmCM4_CM_GAMCOR_LUT_DATA_BASE_IDX 2
#define mmCM4_CM_GAMCOR_LUT_CONTROL 0x12ec
#define mmCM4_CM_GAMCOR_LUT_CONTROL_BASE_IDX 2
#define mmCM4_CM_GAMCOR_RAMA_START_CNTL_B 0x12ed
#define mmCM4_CM_GAMCOR_RAMA_START_CNTL_B_BASE_IDX 2
#define mmCM4_CM_GAMCOR_RAMA_START_CNTL_G 0x12ee
#define mmCM4_CM_GAMCOR_RAMA_START_CNTL_G_BASE_IDX 2
#define mmCM4_CM_GAMCOR_RAMA_START_CNTL_R 0x12ef
#define mmCM4_CM_GAMCOR_RAMA_START_CNTL_R_BASE_IDX 2
#define mmCM4_CM_GAMCOR_RAMA_START_SLOPE_CNTL_B 0x12f0
#define mmCM4_CM_GAMCOR_RAMA_START_SLOPE_CNTL_B_BASE_IDX 2
#define mmCM4_CM_GAMCOR_RAMA_START_SLOPE_CNTL_G 0x12f1
#define mmCM4_CM_GAMCOR_RAMA_START_SLOPE_CNTL_G_BASE_IDX 2
#define mmCM4_CM_GAMCOR_RAMA_START_SLOPE_CNTL_R 0x12f2
#define mmCM4_CM_GAMCOR_RAMA_START_SLOPE_CNTL_R_BASE_IDX 2
#define mmCM4_CM_GAMCOR_RAMA_START_BASE_CNTL_B 0x12f3
#define mmCM4_CM_GAMCOR_RAMA_START_BASE_CNTL_B_BASE_IDX 2
#define mmCM4_CM_GAMCOR_RAMA_START_BASE_CNTL_G 0x12f4
#define mmCM4_CM_GAMCOR_RAMA_START_BASE_CNTL_G_BASE_IDX 2
#define mmCM4_CM_GAMCOR_RAMA_START_BASE_CNTL_R 0x12f5
#define mmCM4_CM_GAMCOR_RAMA_START_BASE_CNTL_R_BASE_IDX 2
#define mmCM4_CM_GAMCOR_RAMA_END_CNTL1_B 0x12f6
#define mmCM4_CM_GAMCOR_RAMA_END_CNTL1_B_BASE_IDX 2
#define mmCM4_CM_GAMCOR_RAMA_END_CNTL2_B 0x12f7
#define mmCM4_CM_GAMCOR_RAMA_END_CNTL2_B_BASE_IDX 2
#define mmCM4_CM_GAMCOR_RAMA_END_CNTL1_G 0x12f8
#define mmCM4_CM_GAMCOR_RAMA_END_CNTL1_G_BASE_IDX 2
#define mmCM4_CM_GAMCOR_RAMA_END_CNTL2_G 0x12f9
#define mmCM4_CM_GAMCOR_RAMA_END_CNTL2_G_BASE_IDX 2
#define mmCM4_CM_GAMCOR_RAMA_END_CNTL1_R 0x12fa
#define mmCM4_CM_GAMCOR_RAMA_END_CNTL1_R_BASE_IDX 2
#define mmCM4_CM_GAMCOR_RAMA_END_CNTL2_R 0x12fb
#define mmCM4_CM_GAMCOR_RAMA_END_CNTL2_R_BASE_IDX 2
#define mmCM4_CM_GAMCOR_RAMA_OFFSET_B 0x12fc
#define mmCM4_CM_GAMCOR_RAMA_OFFSET_B_BASE_IDX 2
#define mmCM4_CM_GAMCOR_RAMA_OFFSET_G 0x12fd
#define mmCM4_CM_GAMCOR_RAMA_OFFSET_G_BASE_IDX 2
#define mmCM4_CM_GAMCOR_RAMA_OFFSET_R 0x12fe
#define mmCM4_CM_GAMCOR_RAMA_OFFSET_R_BASE_IDX 2
#define mmCM4_CM_GAMCOR_RAMA_REGION_0_1 0x12ff
#define mmCM4_CM_GAMCOR_RAMA_REGION_0_1_BASE_IDX 2
#define mmCM4_CM_GAMCOR_RAMA_REGION_2_3 0x1300
#define mmCM4_CM_GAMCOR_RAMA_REGION_2_3_BASE_IDX 2
#define mmCM4_CM_GAMCOR_RAMA_REGION_4_5 0x1301
#define mmCM4_CM_GAMCOR_RAMA_REGION_4_5_BASE_IDX 2
#define mmCM4_CM_GAMCOR_RAMA_REGION_6_7 0x1302
#define mmCM4_CM_GAMCOR_RAMA_REGION_6_7_BASE_IDX 2
#define mmCM4_CM_GAMCOR_RAMA_REGION_8_9 0x1303
#define mmCM4_CM_GAMCOR_RAMA_REGION_8_9_BASE_IDX 2
#define mmCM4_CM_GAMCOR_RAMA_REGION_10_11 0x1304
#define mmCM4_CM_GAMCOR_RAMA_REGION_10_11_BASE_IDX 2
#define mmCM4_CM_GAMCOR_RAMA_REGION_12_13 0x1305
#define mmCM4_CM_GAMCOR_RAMA_REGION_12_13_BASE_IDX 2
#define mmCM4_CM_GAMCOR_RAMA_REGION_14_15 0x1306
#define mmCM4_CM_GAMCOR_RAMA_REGION_14_15_BASE_IDX 2
#define mmCM4_CM_GAMCOR_RAMA_REGION_16_17 0x1307
#define mmCM4_CM_GAMCOR_RAMA_REGION_16_17_BASE_IDX 2
#define mmCM4_CM_GAMCOR_RAMA_REGION_18_19 0x1308
#define mmCM4_CM_GAMCOR_RAMA_REGION_18_19_BASE_IDX 2
#define mmCM4_CM_GAMCOR_RAMA_REGION_20_21 0x1309
#define mmCM4_CM_GAMCOR_RAMA_REGION_20_21_BASE_IDX 2
#define mmCM4_CM_GAMCOR_RAMA_REGION_22_23 0x130a
#define mmCM4_CM_GAMCOR_RAMA_REGION_22_23_BASE_IDX 2
#define mmCM4_CM_GAMCOR_RAMA_REGION_24_25 0x130b
#define mmCM4_CM_GAMCOR_RAMA_REGION_24_25_BASE_IDX 2
#define mmCM4_CM_GAMCOR_RAMA_REGION_26_27 0x130c
#define mmCM4_CM_GAMCOR_RAMA_REGION_26_27_BASE_IDX 2
#define mmCM4_CM_GAMCOR_RAMA_REGION_28_29 0x130d
#define mmCM4_CM_GAMCOR_RAMA_REGION_28_29_BASE_IDX 2
#define mmCM4_CM_GAMCOR_RAMA_REGION_30_31 0x130e
#define mmCM4_CM_GAMCOR_RAMA_REGION_30_31_BASE_IDX 2
#define mmCM4_CM_GAMCOR_RAMA_REGION_32_33 0x130f
#define mmCM4_CM_GAMCOR_RAMA_REGION_32_33_BASE_IDX 2
#define mmCM4_CM_GAMCOR_RAMB_START_CNTL_B 0x1310
#define mmCM4_CM_GAMCOR_RAMB_START_CNTL_B_BASE_IDX 2
#define mmCM4_CM_GAMCOR_RAMB_START_CNTL_G 0x1311
#define mmCM4_CM_GAMCOR_RAMB_START_CNTL_G_BASE_IDX 2
#define mmCM4_CM_GAMCOR_RAMB_START_CNTL_R 0x1312
#define mmCM4_CM_GAMCOR_RAMB_START_CNTL_R_BASE_IDX 2
#define mmCM4_CM_GAMCOR_RAMB_START_SLOPE_CNTL_B 0x1313
#define mmCM4_CM_GAMCOR_RAMB_START_SLOPE_CNTL_B_BASE_IDX 2
#define mmCM4_CM_GAMCOR_RAMB_START_SLOPE_CNTL_G 0x1314
#define mmCM4_CM_GAMCOR_RAMB_START_SLOPE_CNTL_G_BASE_IDX 2
#define mmCM4_CM_GAMCOR_RAMB_START_SLOPE_CNTL_R 0x1315
#define mmCM4_CM_GAMCOR_RAMB_START_SLOPE_CNTL_R_BASE_IDX 2
#define mmCM4_CM_GAMCOR_RAMB_START_BASE_CNTL_B 0x1316
#define mmCM4_CM_GAMCOR_RAMB_START_BASE_CNTL_B_BASE_IDX 2
#define mmCM4_CM_GAMCOR_RAMB_START_BASE_CNTL_G 0x1317
#define mmCM4_CM_GAMCOR_RAMB_START_BASE_CNTL_G_BASE_IDX 2
#define mmCM4_CM_GAMCOR_RAMB_START_BASE_CNTL_R 0x1318
#define mmCM4_CM_GAMCOR_RAMB_START_BASE_CNTL_R_BASE_IDX 2
#define mmCM4_CM_GAMCOR_RAMB_END_CNTL1_B 0x1319
#define mmCM4_CM_GAMCOR_RAMB_END_CNTL1_B_BASE_IDX 2
#define mmCM4_CM_GAMCOR_RAMB_END_CNTL2_B 0x131a
#define mmCM4_CM_GAMCOR_RAMB_END_CNTL2_B_BASE_IDX 2
#define mmCM4_CM_GAMCOR_RAMB_END_CNTL1_G 0x131b
#define mmCM4_CM_GAMCOR_RAMB_END_CNTL1_G_BASE_IDX 2
#define mmCM4_CM_GAMCOR_RAMB_END_CNTL2_G 0x131c
#define mmCM4_CM_GAMCOR_RAMB_END_CNTL2_G_BASE_IDX 2
#define mmCM4_CM_GAMCOR_RAMB_END_CNTL1_R 0x131d
#define mmCM4_CM_GAMCOR_RAMB_END_CNTL1_R_BASE_IDX 2
#define mmCM4_CM_GAMCOR_RAMB_END_CNTL2_R 0x131e
#define mmCM4_CM_GAMCOR_RAMB_END_CNTL2_R_BASE_IDX 2
#define mmCM4_CM_GAMCOR_RAMB_OFFSET_B 0x131f
#define mmCM4_CM_GAMCOR_RAMB_OFFSET_B_BASE_IDX 2
#define mmCM4_CM_GAMCOR_RAMB_OFFSET_G 0x1320
#define mmCM4_CM_GAMCOR_RAMB_OFFSET_G_BASE_IDX 2
#define mmCM4_CM_GAMCOR_RAMB_OFFSET_R 0x1321
#define mmCM4_CM_GAMCOR_RAMB_OFFSET_R_BASE_IDX 2
#define mmCM4_CM_GAMCOR_RAMB_REGION_0_1 0x1322
#define mmCM4_CM_GAMCOR_RAMB_REGION_0_1_BASE_IDX 2
#define mmCM4_CM_GAMCOR_RAMB_REGION_2_3 0x1323
#define mmCM4_CM_GAMCOR_RAMB_REGION_2_3_BASE_IDX 2
#define mmCM4_CM_GAMCOR_RAMB_REGION_4_5 0x1324
#define mmCM4_CM_GAMCOR_RAMB_REGION_4_5_BASE_IDX 2
#define mmCM4_CM_GAMCOR_RAMB_REGION_6_7 0x1325
#define mmCM4_CM_GAMCOR_RAMB_REGION_6_7_BASE_IDX 2
#define mmCM4_CM_GAMCOR_RAMB_REGION_8_9 0x1326
#define mmCM4_CM_GAMCOR_RAMB_REGION_8_9_BASE_IDX 2
#define mmCM4_CM_GAMCOR_RAMB_REGION_10_11 0x1327
#define mmCM4_CM_GAMCOR_RAMB_REGION_10_11_BASE_IDX 2
#define mmCM4_CM_GAMCOR_RAMB_REGION_12_13 0x1328
#define mmCM4_CM_GAMCOR_RAMB_REGION_12_13_BASE_IDX 2
#define mmCM4_CM_GAMCOR_RAMB_REGION_14_15 0x1329
#define mmCM4_CM_GAMCOR_RAMB_REGION_14_15_BASE_IDX 2
#define mmCM4_CM_GAMCOR_RAMB_REGION_16_17 0x132a
#define mmCM4_CM_GAMCOR_RAMB_REGION_16_17_BASE_IDX 2
#define mmCM4_CM_GAMCOR_RAMB_REGION_18_19 0x132b
#define mmCM4_CM_GAMCOR_RAMB_REGION_18_19_BASE_IDX 2
#define mmCM4_CM_GAMCOR_RAMB_REGION_20_21 0x132c
#define mmCM4_CM_GAMCOR_RAMB_REGION_20_21_BASE_IDX 2
#define mmCM4_CM_GAMCOR_RAMB_REGION_22_23 0x132d
#define mmCM4_CM_GAMCOR_RAMB_REGION_22_23_BASE_IDX 2
#define mmCM4_CM_GAMCOR_RAMB_REGION_24_25 0x132e
#define mmCM4_CM_GAMCOR_RAMB_REGION_24_25_BASE_IDX 2
#define mmCM4_CM_GAMCOR_RAMB_REGION_26_27 0x132f
#define mmCM4_CM_GAMCOR_RAMB_REGION_26_27_BASE_IDX 2
#define mmCM4_CM_GAMCOR_RAMB_REGION_28_29 0x1330
#define mmCM4_CM_GAMCOR_RAMB_REGION_28_29_BASE_IDX 2
#define mmCM4_CM_GAMCOR_RAMB_REGION_30_31 0x1331
#define mmCM4_CM_GAMCOR_RAMB_REGION_30_31_BASE_IDX 2
#define mmCM4_CM_GAMCOR_RAMB_REGION_32_33 0x1332
#define mmCM4_CM_GAMCOR_RAMB_REGION_32_33_BASE_IDX 2
#define mmCM4_CM_BLNDGAM_CONTROL 0x1333
#define mmCM4_CM_BLNDGAM_CONTROL_BASE_IDX 2
#define mmCM4_CM_BLNDGAM_LUT_INDEX 0x1334
#define mmCM4_CM_BLNDGAM_LUT_INDEX_BASE_IDX 2
#define mmCM4_CM_BLNDGAM_LUT_DATA 0x1335
#define mmCM4_CM_BLNDGAM_LUT_DATA_BASE_IDX 2
#define mmCM4_CM_BLNDGAM_LUT_CONTROL 0x1336
#define mmCM4_CM_BLNDGAM_LUT_CONTROL_BASE_IDX 2
#define mmCM4_CM_BLNDGAM_RAMA_START_CNTL_B 0x1337
#define mmCM4_CM_BLNDGAM_RAMA_START_CNTL_B_BASE_IDX 2
#define mmCM4_CM_BLNDGAM_RAMA_START_CNTL_G 0x1338
#define mmCM4_CM_BLNDGAM_RAMA_START_CNTL_G_BASE_IDX 2
#define mmCM4_CM_BLNDGAM_RAMA_START_CNTL_R 0x1339
#define mmCM4_CM_BLNDGAM_RAMA_START_CNTL_R_BASE_IDX 2
#define mmCM4_CM_BLNDGAM_RAMA_START_SLOPE_CNTL_B 0x133a
#define mmCM4_CM_BLNDGAM_RAMA_START_SLOPE_CNTL_B_BASE_IDX 2
#define mmCM4_CM_BLNDGAM_RAMA_START_SLOPE_CNTL_G 0x133b
#define mmCM4_CM_BLNDGAM_RAMA_START_SLOPE_CNTL_G_BASE_IDX 2
#define mmCM4_CM_BLNDGAM_RAMA_START_SLOPE_CNTL_R 0x133c
#define mmCM4_CM_BLNDGAM_RAMA_START_SLOPE_CNTL_R_BASE_IDX 2
#define mmCM4_CM_BLNDGAM_RAMA_START_BASE_CNTL_B 0x133d
#define mmCM4_CM_BLNDGAM_RAMA_START_BASE_CNTL_B_BASE_IDX 2
#define mmCM4_CM_BLNDGAM_RAMA_START_BASE_CNTL_G 0x133e
#define mmCM4_CM_BLNDGAM_RAMA_START_BASE_CNTL_G_BASE_IDX 2
#define mmCM4_CM_BLNDGAM_RAMA_START_BASE_CNTL_R 0x133f
#define mmCM4_CM_BLNDGAM_RAMA_START_BASE_CNTL_R_BASE_IDX 2
#define mmCM4_CM_BLNDGAM_RAMA_END_CNTL1_B 0x1340
#define mmCM4_CM_BLNDGAM_RAMA_END_CNTL1_B_BASE_IDX 2
#define mmCM4_CM_BLNDGAM_RAMA_END_CNTL2_B 0x1341
#define mmCM4_CM_BLNDGAM_RAMA_END_CNTL2_B_BASE_IDX 2
#define mmCM4_CM_BLNDGAM_RAMA_END_CNTL1_G 0x1342
#define mmCM4_CM_BLNDGAM_RAMA_END_CNTL1_G_BASE_IDX 2
#define mmCM4_CM_BLNDGAM_RAMA_END_CNTL2_G 0x1343
#define mmCM4_CM_BLNDGAM_RAMA_END_CNTL2_G_BASE_IDX 2
#define mmCM4_CM_BLNDGAM_RAMA_END_CNTL1_R 0x1344
#define mmCM4_CM_BLNDGAM_RAMA_END_CNTL1_R_BASE_IDX 2
#define mmCM4_CM_BLNDGAM_RAMA_END_CNTL2_R 0x1345
#define mmCM4_CM_BLNDGAM_RAMA_END_CNTL2_R_BASE_IDX 2
#define mmCM4_CM_BLNDGAM_RAMA_OFFSET_B 0x1346
#define mmCM4_CM_BLNDGAM_RAMA_OFFSET_B_BASE_IDX 2
#define mmCM4_CM_BLNDGAM_RAMA_OFFSET_G 0x1347
#define mmCM4_CM_BLNDGAM_RAMA_OFFSET_G_BASE_IDX 2
#define mmCM4_CM_BLNDGAM_RAMA_OFFSET_R 0x1348
#define mmCM4_CM_BLNDGAM_RAMA_OFFSET_R_BASE_IDX 2
#define mmCM4_CM_BLNDGAM_RAMA_REGION_0_1 0x1349
#define mmCM4_CM_BLNDGAM_RAMA_REGION_0_1_BASE_IDX 2
#define mmCM4_CM_BLNDGAM_RAMA_REGION_2_3 0x134a
#define mmCM4_CM_BLNDGAM_RAMA_REGION_2_3_BASE_IDX 2
#define mmCM4_CM_BLNDGAM_RAMA_REGION_4_5 0x134b
#define mmCM4_CM_BLNDGAM_RAMA_REGION_4_5_BASE_IDX 2
#define mmCM4_CM_BLNDGAM_RAMA_REGION_6_7 0x134c
#define mmCM4_CM_BLNDGAM_RAMA_REGION_6_7_BASE_IDX 2
#define mmCM4_CM_BLNDGAM_RAMA_REGION_8_9 0x134d
#define mmCM4_CM_BLNDGAM_RAMA_REGION_8_9_BASE_IDX 2
#define mmCM4_CM_BLNDGAM_RAMA_REGION_10_11 0x134e
#define mmCM4_CM_BLNDGAM_RAMA_REGION_10_11_BASE_IDX 2
#define mmCM4_CM_BLNDGAM_RAMA_REGION_12_13 0x134f
#define mmCM4_CM_BLNDGAM_RAMA_REGION_12_13_BASE_IDX 2
#define mmCM4_CM_BLNDGAM_RAMA_REGION_14_15 0x1350
#define mmCM4_CM_BLNDGAM_RAMA_REGION_14_15_BASE_IDX 2
#define mmCM4_CM_BLNDGAM_RAMA_REGION_16_17 0x1351
#define mmCM4_CM_BLNDGAM_RAMA_REGION_16_17_BASE_IDX 2
#define mmCM4_CM_BLNDGAM_RAMA_REGION_18_19 0x1352
#define mmCM4_CM_BLNDGAM_RAMA_REGION_18_19_BASE_IDX 2
#define mmCM4_CM_BLNDGAM_RAMA_REGION_20_21 0x1353
#define mmCM4_CM_BLNDGAM_RAMA_REGION_20_21_BASE_IDX 2
#define mmCM4_CM_BLNDGAM_RAMA_REGION_22_23 0x1354
#define mmCM4_CM_BLNDGAM_RAMA_REGION_22_23_BASE_IDX 2
#define mmCM4_CM_BLNDGAM_RAMA_REGION_24_25 0x1355
#define mmCM4_CM_BLNDGAM_RAMA_REGION_24_25_BASE_IDX 2
#define mmCM4_CM_BLNDGAM_RAMA_REGION_26_27 0x1356
#define mmCM4_CM_BLNDGAM_RAMA_REGION_26_27_BASE_IDX 2
#define mmCM4_CM_BLNDGAM_RAMA_REGION_28_29 0x1357
#define mmCM4_CM_BLNDGAM_RAMA_REGION_28_29_BASE_IDX 2
#define mmCM4_CM_BLNDGAM_RAMA_REGION_30_31 0x1358
#define mmCM4_CM_BLNDGAM_RAMA_REGION_30_31_BASE_IDX 2
#define mmCM4_CM_BLNDGAM_RAMA_REGION_32_33 0x1359
#define mmCM4_CM_BLNDGAM_RAMA_REGION_32_33_BASE_IDX 2
#define mmCM4_CM_BLNDGAM_RAMB_START_CNTL_B 0x135a
#define mmCM4_CM_BLNDGAM_RAMB_START_CNTL_B_BASE_IDX 2
#define mmCM4_CM_BLNDGAM_RAMB_START_CNTL_G 0x135b
#define mmCM4_CM_BLNDGAM_RAMB_START_CNTL_G_BASE_IDX 2
#define mmCM4_CM_BLNDGAM_RAMB_START_CNTL_R 0x135c
#define mmCM4_CM_BLNDGAM_RAMB_START_CNTL_R_BASE_IDX 2
#define mmCM4_CM_BLNDGAM_RAMB_START_SLOPE_CNTL_B 0x135d
#define mmCM4_CM_BLNDGAM_RAMB_START_SLOPE_CNTL_B_BASE_IDX 2
#define mmCM4_CM_BLNDGAM_RAMB_START_SLOPE_CNTL_G 0x135e
#define mmCM4_CM_BLNDGAM_RAMB_START_SLOPE_CNTL_G_BASE_IDX 2
#define mmCM4_CM_BLNDGAM_RAMB_START_SLOPE_CNTL_R 0x135f
#define mmCM4_CM_BLNDGAM_RAMB_START_SLOPE_CNTL_R_BASE_IDX 2
#define mmCM4_CM_BLNDGAM_RAMB_START_BASE_CNTL_B 0x1360
#define mmCM4_CM_BLNDGAM_RAMB_START_BASE_CNTL_B_BASE_IDX 2
#define mmCM4_CM_BLNDGAM_RAMB_START_BASE_CNTL_G 0x1361
#define mmCM4_CM_BLNDGAM_RAMB_START_BASE_CNTL_G_BASE_IDX 2
#define mmCM4_CM_BLNDGAM_RAMB_START_BASE_CNTL_R 0x1362
#define mmCM4_CM_BLNDGAM_RAMB_START_BASE_CNTL_R_BASE_IDX 2
#define mmCM4_CM_BLNDGAM_RAMB_END_CNTL1_B 0x1363
#define mmCM4_CM_BLNDGAM_RAMB_END_CNTL1_B_BASE_IDX 2
#define mmCM4_CM_BLNDGAM_RAMB_END_CNTL2_B 0x1364
#define mmCM4_CM_BLNDGAM_RAMB_END_CNTL2_B_BASE_IDX 2
#define mmCM4_CM_BLNDGAM_RAMB_END_CNTL1_G 0x1365
#define mmCM4_CM_BLNDGAM_RAMB_END_CNTL1_G_BASE_IDX 2
#define mmCM4_CM_BLNDGAM_RAMB_END_CNTL2_G 0x1366
#define mmCM4_CM_BLNDGAM_RAMB_END_CNTL2_G_BASE_IDX 2
#define mmCM4_CM_BLNDGAM_RAMB_END_CNTL1_R 0x1367
#define mmCM4_CM_BLNDGAM_RAMB_END_CNTL1_R_BASE_IDX 2
#define mmCM4_CM_BLNDGAM_RAMB_END_CNTL2_R 0x1368
#define mmCM4_CM_BLNDGAM_RAMB_END_CNTL2_R_BASE_IDX 2
#define mmCM4_CM_BLNDGAM_RAMB_OFFSET_B 0x1369
#define mmCM4_CM_BLNDGAM_RAMB_OFFSET_B_BASE_IDX 2
#define mmCM4_CM_BLNDGAM_RAMB_OFFSET_G 0x136a
#define mmCM4_CM_BLNDGAM_RAMB_OFFSET_G_BASE_IDX 2
#define mmCM4_CM_BLNDGAM_RAMB_OFFSET_R 0x136b
#define mmCM4_CM_BLNDGAM_RAMB_OFFSET_R_BASE_IDX 2
#define mmCM4_CM_BLNDGAM_RAMB_REGION_0_1 0x136c
#define mmCM4_CM_BLNDGAM_RAMB_REGION_0_1_BASE_IDX 2
#define mmCM4_CM_BLNDGAM_RAMB_REGION_2_3 0x136d
#define mmCM4_CM_BLNDGAM_RAMB_REGION_2_3_BASE_IDX 2
#define mmCM4_CM_BLNDGAM_RAMB_REGION_4_5 0x136e
#define mmCM4_CM_BLNDGAM_RAMB_REGION_4_5_BASE_IDX 2
#define mmCM4_CM_BLNDGAM_RAMB_REGION_6_7 0x136f
#define mmCM4_CM_BLNDGAM_RAMB_REGION_6_7_BASE_IDX 2
#define mmCM4_CM_BLNDGAM_RAMB_REGION_8_9 0x1370
#define mmCM4_CM_BLNDGAM_RAMB_REGION_8_9_BASE_IDX 2
#define mmCM4_CM_BLNDGAM_RAMB_REGION_10_11 0x1371
#define mmCM4_CM_BLNDGAM_RAMB_REGION_10_11_BASE_IDX 2
#define mmCM4_CM_BLNDGAM_RAMB_REGION_12_13 0x1372
#define mmCM4_CM_BLNDGAM_RAMB_REGION_12_13_BASE_IDX 2
#define mmCM4_CM_BLNDGAM_RAMB_REGION_14_15 0x1373
#define mmCM4_CM_BLNDGAM_RAMB_REGION_14_15_BASE_IDX 2
#define mmCM4_CM_BLNDGAM_RAMB_REGION_16_17 0x1374
#define mmCM4_CM_BLNDGAM_RAMB_REGION_16_17_BASE_IDX 2
#define mmCM4_CM_BLNDGAM_RAMB_REGION_18_19 0x1375
#define mmCM4_CM_BLNDGAM_RAMB_REGION_18_19_BASE_IDX 2
#define mmCM4_CM_BLNDGAM_RAMB_REGION_20_21 0x1376
#define mmCM4_CM_BLNDGAM_RAMB_REGION_20_21_BASE_IDX 2
#define mmCM4_CM_BLNDGAM_RAMB_REGION_22_23 0x1377
#define mmCM4_CM_BLNDGAM_RAMB_REGION_22_23_BASE_IDX 2
#define mmCM4_CM_BLNDGAM_RAMB_REGION_24_25 0x1378
#define mmCM4_CM_BLNDGAM_RAMB_REGION_24_25_BASE_IDX 2
#define mmCM4_CM_BLNDGAM_RAMB_REGION_26_27 0x1379
#define mmCM4_CM_BLNDGAM_RAMB_REGION_26_27_BASE_IDX 2
#define mmCM4_CM_BLNDGAM_RAMB_REGION_28_29 0x137a
#define mmCM4_CM_BLNDGAM_RAMB_REGION_28_29_BASE_IDX 2
#define mmCM4_CM_BLNDGAM_RAMB_REGION_30_31 0x137b
#define mmCM4_CM_BLNDGAM_RAMB_REGION_30_31_BASE_IDX 2
#define mmCM4_CM_BLNDGAM_RAMB_REGION_32_33 0x137c
#define mmCM4_CM_BLNDGAM_RAMB_REGION_32_33_BASE_IDX 2
#define mmCM4_CM_HDR_MULT_COEF 0x137d
#define mmCM4_CM_HDR_MULT_COEF_BASE_IDX 2
#define mmCM4_CM_MEM_PWR_CTRL 0x137e
#define mmCM4_CM_MEM_PWR_CTRL_BASE_IDX 2
#define mmCM4_CM_MEM_PWR_STATUS 0x137f
#define mmCM4_CM_MEM_PWR_STATUS_BASE_IDX 2
#define mmCM4_CM_DEALPHA 0x1381
#define mmCM4_CM_DEALPHA_BASE_IDX 2
#define mmCM4_CM_COEF_FORMAT 0x1382
#define mmCM4_CM_COEF_FORMAT_BASE_IDX 2
#define mmCM4_CM_SHAPER_CONTROL 0x1383
#define mmCM4_CM_SHAPER_CONTROL_BASE_IDX 2
#define mmCM4_CM_SHAPER_OFFSET_R 0x1384
#define mmCM4_CM_SHAPER_OFFSET_R_BASE_IDX 2
#define mmCM4_CM_SHAPER_OFFSET_G 0x1385
#define mmCM4_CM_SHAPER_OFFSET_G_BASE_IDX 2
#define mmCM4_CM_SHAPER_OFFSET_B 0x1386
#define mmCM4_CM_SHAPER_OFFSET_B_BASE_IDX 2
#define mmCM4_CM_SHAPER_SCALE_R 0x1387
#define mmCM4_CM_SHAPER_SCALE_R_BASE_IDX 2
#define mmCM4_CM_SHAPER_SCALE_G_B 0x1388
#define mmCM4_CM_SHAPER_SCALE_G_B_BASE_IDX 2
#define mmCM4_CM_SHAPER_LUT_INDEX 0x1389
#define mmCM4_CM_SHAPER_LUT_INDEX_BASE_IDX 2
#define mmCM4_CM_SHAPER_LUT_DATA 0x138a
#define mmCM4_CM_SHAPER_LUT_DATA_BASE_IDX 2
#define mmCM4_CM_SHAPER_LUT_WRITE_EN_MASK 0x138b
#define mmCM4_CM_SHAPER_LUT_WRITE_EN_MASK_BASE_IDX 2
#define mmCM4_CM_SHAPER_RAMA_START_CNTL_B 0x138c
#define mmCM4_CM_SHAPER_RAMA_START_CNTL_B_BASE_IDX 2
#define mmCM4_CM_SHAPER_RAMA_START_CNTL_G 0x138d
#define mmCM4_CM_SHAPER_RAMA_START_CNTL_G_BASE_IDX 2
#define mmCM4_CM_SHAPER_RAMA_START_CNTL_R 0x138e
#define mmCM4_CM_SHAPER_RAMA_START_CNTL_R_BASE_IDX 2
#define mmCM4_CM_SHAPER_RAMA_END_CNTL_B 0x138f
#define mmCM4_CM_SHAPER_RAMA_END_CNTL_B_BASE_IDX 2
#define mmCM4_CM_SHAPER_RAMA_END_CNTL_G 0x1390
#define mmCM4_CM_SHAPER_RAMA_END_CNTL_G_BASE_IDX 2
#define mmCM4_CM_SHAPER_RAMA_END_CNTL_R 0x1391
#define mmCM4_CM_SHAPER_RAMA_END_CNTL_R_BASE_IDX 2
#define mmCM4_CM_SHAPER_RAMA_REGION_0_1 0x1392
#define mmCM4_CM_SHAPER_RAMA_REGION_0_1_BASE_IDX 2
#define mmCM4_CM_SHAPER_RAMA_REGION_2_3 0x1393
#define mmCM4_CM_SHAPER_RAMA_REGION_2_3_BASE_IDX 2
#define mmCM4_CM_SHAPER_RAMA_REGION_4_5 0x1394
#define mmCM4_CM_SHAPER_RAMA_REGION_4_5_BASE_IDX 2
#define mmCM4_CM_SHAPER_RAMA_REGION_6_7 0x1395
#define mmCM4_CM_SHAPER_RAMA_REGION_6_7_BASE_IDX 2
#define mmCM4_CM_SHAPER_RAMA_REGION_8_9 0x1396
#define mmCM4_CM_SHAPER_RAMA_REGION_8_9_BASE_IDX 2
#define mmCM4_CM_SHAPER_RAMA_REGION_10_11 0x1397
#define mmCM4_CM_SHAPER_RAMA_REGION_10_11_BASE_IDX 2
#define mmCM4_CM_SHAPER_RAMA_REGION_12_13 0x1398
#define mmCM4_CM_SHAPER_RAMA_REGION_12_13_BASE_IDX 2
#define mmCM4_CM_SHAPER_RAMA_REGION_14_15 0x1399
#define mmCM4_CM_SHAPER_RAMA_REGION_14_15_BASE_IDX 2
#define mmCM4_CM_SHAPER_RAMA_REGION_16_17 0x139a
#define mmCM4_CM_SHAPER_RAMA_REGION_16_17_BASE_IDX 2
#define mmCM4_CM_SHAPER_RAMA_REGION_18_19 0x139b
#define mmCM4_CM_SHAPER_RAMA_REGION_18_19_BASE_IDX 2
#define mmCM4_CM_SHAPER_RAMA_REGION_20_21 0x139c
#define mmCM4_CM_SHAPER_RAMA_REGION_20_21_BASE_IDX 2
#define mmCM4_CM_SHAPER_RAMA_REGION_22_23 0x139d
#define mmCM4_CM_SHAPER_RAMA_REGION_22_23_BASE_IDX 2
#define mmCM4_CM_SHAPER_RAMA_REGION_24_25 0x139e
#define mmCM4_CM_SHAPER_RAMA_REGION_24_25_BASE_IDX 2
#define mmCM4_CM_SHAPER_RAMA_REGION_26_27 0x139f
#define mmCM4_CM_SHAPER_RAMA_REGION_26_27_BASE_IDX 2
#define mmCM4_CM_SHAPER_RAMA_REGION_28_29 0x13a0
#define mmCM4_CM_SHAPER_RAMA_REGION_28_29_BASE_IDX 2
#define mmCM4_CM_SHAPER_RAMA_REGION_30_31 0x13a1
#define mmCM4_CM_SHAPER_RAMA_REGION_30_31_BASE_IDX 2
#define mmCM4_CM_SHAPER_RAMA_REGION_32_33 0x13a2
#define mmCM4_CM_SHAPER_RAMA_REGION_32_33_BASE_IDX 2
#define mmCM4_CM_SHAPER_RAMB_START_CNTL_B 0x13a3
#define mmCM4_CM_SHAPER_RAMB_START_CNTL_B_BASE_IDX 2
#define mmCM4_CM_SHAPER_RAMB_START_CNTL_G 0x13a4
#define mmCM4_CM_SHAPER_RAMB_START_CNTL_G_BASE_IDX 2
#define mmCM4_CM_SHAPER_RAMB_START_CNTL_R 0x13a5
#define mmCM4_CM_SHAPER_RAMB_START_CNTL_R_BASE_IDX 2
#define mmCM4_CM_SHAPER_RAMB_END_CNTL_B 0x13a6
#define mmCM4_CM_SHAPER_RAMB_END_CNTL_B_BASE_IDX 2
#define mmCM4_CM_SHAPER_RAMB_END_CNTL_G 0x13a7
#define mmCM4_CM_SHAPER_RAMB_END_CNTL_G_BASE_IDX 2
#define mmCM4_CM_SHAPER_RAMB_END_CNTL_R 0x13a8
#define mmCM4_CM_SHAPER_RAMB_END_CNTL_R_BASE_IDX 2
#define mmCM4_CM_SHAPER_RAMB_REGION_0_1 0x13a9
#define mmCM4_CM_SHAPER_RAMB_REGION_0_1_BASE_IDX 2
#define mmCM4_CM_SHAPER_RAMB_REGION_2_3 0x13aa
#define mmCM4_CM_SHAPER_RAMB_REGION_2_3_BASE_IDX 2
#define mmCM4_CM_SHAPER_RAMB_REGION_4_5 0x13ab
#define mmCM4_CM_SHAPER_RAMB_REGION_4_5_BASE_IDX 2
#define mmCM4_CM_SHAPER_RAMB_REGION_6_7 0x13ac
#define mmCM4_CM_SHAPER_RAMB_REGION_6_7_BASE_IDX 2
#define mmCM4_CM_SHAPER_RAMB_REGION_8_9 0x13ad
#define mmCM4_CM_SHAPER_RAMB_REGION_8_9_BASE_IDX 2
#define mmCM4_CM_SHAPER_RAMB_REGION_10_11 0x13ae
#define mmCM4_CM_SHAPER_RAMB_REGION_10_11_BASE_IDX 2
#define mmCM4_CM_SHAPER_RAMB_REGION_12_13 0x13af
#define mmCM4_CM_SHAPER_RAMB_REGION_12_13_BASE_IDX 2
#define mmCM4_CM_SHAPER_RAMB_REGION_14_15 0x13b0
#define mmCM4_CM_SHAPER_RAMB_REGION_14_15_BASE_IDX 2
#define mmCM4_CM_SHAPER_RAMB_REGION_16_17 0x13b1
#define mmCM4_CM_SHAPER_RAMB_REGION_16_17_BASE_IDX 2
#define mmCM4_CM_SHAPER_RAMB_REGION_18_19 0x13b2
#define mmCM4_CM_SHAPER_RAMB_REGION_18_19_BASE_IDX 2
#define mmCM4_CM_SHAPER_RAMB_REGION_20_21 0x13b3
#define mmCM4_CM_SHAPER_RAMB_REGION_20_21_BASE_IDX 2
#define mmCM4_CM_SHAPER_RAMB_REGION_22_23 0x13b4
#define mmCM4_CM_SHAPER_RAMB_REGION_22_23_BASE_IDX 2
#define mmCM4_CM_SHAPER_RAMB_REGION_24_25 0x13b5
#define mmCM4_CM_SHAPER_RAMB_REGION_24_25_BASE_IDX 2
#define mmCM4_CM_SHAPER_RAMB_REGION_26_27 0x13b6
#define mmCM4_CM_SHAPER_RAMB_REGION_26_27_BASE_IDX 2
#define mmCM4_CM_SHAPER_RAMB_REGION_28_29 0x13b7
#define mmCM4_CM_SHAPER_RAMB_REGION_28_29_BASE_IDX 2
#define mmCM4_CM_SHAPER_RAMB_REGION_30_31 0x13b8
#define mmCM4_CM_SHAPER_RAMB_REGION_30_31_BASE_IDX 2
#define mmCM4_CM_SHAPER_RAMB_REGION_32_33 0x13b9
#define mmCM4_CM_SHAPER_RAMB_REGION_32_33_BASE_IDX 2
#define mmCM4_CM_MEM_PWR_CTRL2 0x13ba
#define mmCM4_CM_MEM_PWR_CTRL2_BASE_IDX 2
#define mmCM4_CM_MEM_PWR_STATUS2 0x13bb
#define mmCM4_CM_MEM_PWR_STATUS2_BASE_IDX 2
#define mmCM4_CM_3DLUT_MODE 0x13bc
#define mmCM4_CM_3DLUT_MODE_BASE_IDX 2
#define mmCM4_CM_3DLUT_INDEX 0x13bd
#define mmCM4_CM_3DLUT_INDEX_BASE_IDX 2
#define mmCM4_CM_3DLUT_DATA 0x13be
#define mmCM4_CM_3DLUT_DATA_BASE_IDX 2
#define mmCM4_CM_3DLUT_DATA_30BIT 0x13bf
#define mmCM4_CM_3DLUT_DATA_30BIT_BASE_IDX 2
#define mmCM4_CM_3DLUT_READ_WRITE_CONTROL 0x13c0
#define mmCM4_CM_3DLUT_READ_WRITE_CONTROL_BASE_IDX 2
#define mmCM4_CM_3DLUT_OUT_NORM_FACTOR 0x13c1
#define mmCM4_CM_3DLUT_OUT_NORM_FACTOR_BASE_IDX 2
#define mmCM4_CM_3DLUT_OUT_OFFSET_R 0x13c2
#define mmCM4_CM_3DLUT_OUT_OFFSET_R_BASE_IDX 2
#define mmCM4_CM_3DLUT_OUT_OFFSET_G 0x13c3
#define mmCM4_CM_3DLUT_OUT_OFFSET_G_BASE_IDX 2
#define mmCM4_CM_3DLUT_OUT_OFFSET_B 0x13c4
#define mmCM4_CM_3DLUT_OUT_OFFSET_B_BASE_IDX 2
// addressBlock: dce_dc_dpp4_dispdec_dpp_dcperfmon_dc_perfmon_dispdec
// base address: 0x4f40
#define mmDC_PERFMON15_PERFCOUNTER_CNTL 0x13d0
#define mmDC_PERFMON15_PERFCOUNTER_CNTL_BASE_IDX 2
#define mmDC_PERFMON15_PERFCOUNTER_CNTL2 0x13d1
#define mmDC_PERFMON15_PERFCOUNTER_CNTL2_BASE_IDX 2
#define mmDC_PERFMON15_PERFCOUNTER_STATE 0x13d2
#define mmDC_PERFMON15_PERFCOUNTER_STATE_BASE_IDX 2
#define mmDC_PERFMON15_PERFMON_CNTL 0x13d3
#define mmDC_PERFMON15_PERFMON_CNTL_BASE_IDX 2
#define mmDC_PERFMON15_PERFMON_CNTL2 0x13d4
#define mmDC_PERFMON15_PERFMON_CNTL2_BASE_IDX 2
#define mmDC_PERFMON15_PERFMON_CVALUE_INT_MISC 0x13d5
#define mmDC_PERFMON15_PERFMON_CVALUE_INT_MISC_BASE_IDX 2
#define mmDC_PERFMON15_PERFMON_CVALUE_LOW 0x13d6
#define mmDC_PERFMON15_PERFMON_CVALUE_LOW_BASE_IDX 2
#define mmDC_PERFMON15_PERFMON_HI 0x13d7
#define mmDC_PERFMON15_PERFMON_HI_BASE_IDX 2
#define mmDC_PERFMON15_PERFMON_LOW 0x13d8
#define mmDC_PERFMON15_PERFMON_LOW_BASE_IDX 2
// addressBlock: dce_dc_opp_fmt0_dispdec
// base address: 0x0
#define mmFMT0_FMT_CLAMP_COMPONENT_R 0x183c
#define mmFMT0_FMT_CLAMP_COMPONENT_R_BASE_IDX 2
#define mmFMT0_FMT_CLAMP_COMPONENT_G 0x183d
#define mmFMT0_FMT_CLAMP_COMPONENT_G_BASE_IDX 2
#define mmFMT0_FMT_CLAMP_COMPONENT_B 0x183e
#define mmFMT0_FMT_CLAMP_COMPONENT_B_BASE_IDX 2
#define mmFMT0_FMT_DYNAMIC_EXP_CNTL 0x183f
#define mmFMT0_FMT_DYNAMIC_EXP_CNTL_BASE_IDX 2
#define mmFMT0_FMT_CONTROL 0x1840
#define mmFMT0_FMT_CONTROL_BASE_IDX 2
#define mmFMT0_FMT_BIT_DEPTH_CONTROL 0x1841
#define mmFMT0_FMT_BIT_DEPTH_CONTROL_BASE_IDX 2
#define mmFMT0_FMT_DITHER_RAND_R_SEED 0x1842
#define mmFMT0_FMT_DITHER_RAND_R_SEED_BASE_IDX 2
#define mmFMT0_FMT_DITHER_RAND_G_SEED 0x1843
#define mmFMT0_FMT_DITHER_RAND_G_SEED_BASE_IDX 2
#define mmFMT0_FMT_DITHER_RAND_B_SEED 0x1844
#define mmFMT0_FMT_DITHER_RAND_B_SEED_BASE_IDX 2
#define mmFMT0_FMT_CLAMP_CNTL 0x1845
#define mmFMT0_FMT_CLAMP_CNTL_BASE_IDX 2
#define mmFMT0_FMT_SIDE_BY_SIDE_STEREO_CONTROL 0x1846
#define mmFMT0_FMT_SIDE_BY_SIDE_STEREO_CONTROL_BASE_IDX 2
#define mmFMT0_FMT_MAP420_MEMORY_CONTROL 0x1847
#define mmFMT0_FMT_MAP420_MEMORY_CONTROL_BASE_IDX 2
#define mmFMT0_FMT_422_CONTROL 0x1849
#define mmFMT0_FMT_422_CONTROL_BASE_IDX 2
// addressBlock: dce_dc_opp_dpg0_dispdec
// base address: 0x0
#define mmDPG0_DPG_CONTROL 0x1854
#define mmDPG0_DPG_CONTROL_BASE_IDX 2
#define mmDPG0_DPG_RAMP_CONTROL 0x1855
#define mmDPG0_DPG_RAMP_CONTROL_BASE_IDX 2
#define mmDPG0_DPG_DIMENSIONS 0x1856
#define mmDPG0_DPG_DIMENSIONS_BASE_IDX 2
#define mmDPG0_DPG_COLOUR_R_CR 0x1857
#define mmDPG0_DPG_COLOUR_R_CR_BASE_IDX 2
#define mmDPG0_DPG_COLOUR_G_Y 0x1858
#define mmDPG0_DPG_COLOUR_G_Y_BASE_IDX 2
#define mmDPG0_DPG_COLOUR_B_CB 0x1859
#define mmDPG0_DPG_COLOUR_B_CB_BASE_IDX 2
#define mmDPG0_DPG_OFFSET_SEGMENT 0x185a
#define mmDPG0_DPG_OFFSET_SEGMENT_BASE_IDX 2
#define mmDPG0_DPG_STATUS 0x185b
#define mmDPG0_DPG_STATUS_BASE_IDX 2
// addressBlock: dce_dc_opp_oppbuf0_dispdec
// base address: 0x0
#define mmOPPBUF0_OPPBUF_CONTROL 0x1884
#define mmOPPBUF0_OPPBUF_CONTROL_BASE_IDX 2
#define mmOPPBUF0_OPPBUF_3D_PARAMETERS_0 0x1885
#define mmOPPBUF0_OPPBUF_3D_PARAMETERS_0_BASE_IDX 2
#define mmOPPBUF0_OPPBUF_3D_PARAMETERS_1 0x1886
#define mmOPPBUF0_OPPBUF_3D_PARAMETERS_1_BASE_IDX 2
#define mmOPPBUF0_OPPBUF_CONTROL1 0x1889
#define mmOPPBUF0_OPPBUF_CONTROL1_BASE_IDX 2
// addressBlock: dce_dc_opp_opp_pipe0_dispdec
// base address: 0x0
#define mmOPP_PIPE0_OPP_PIPE_CONTROL 0x188c
#define mmOPP_PIPE0_OPP_PIPE_CONTROL_BASE_IDX 2
// addressBlock: dce_dc_opp_opp_pipe_crc0_dispdec
// base address: 0x0
#define mmOPP_PIPE_CRC0_OPP_PIPE_CRC_CONTROL 0x1891
#define mmOPP_PIPE_CRC0_OPP_PIPE_CRC_CONTROL_BASE_IDX 2
#define mmOPP_PIPE_CRC0_OPP_PIPE_CRC_MASK 0x1892
#define mmOPP_PIPE_CRC0_OPP_PIPE_CRC_MASK_BASE_IDX 2
#define mmOPP_PIPE_CRC0_OPP_PIPE_CRC_RESULT0 0x1893
#define mmOPP_PIPE_CRC0_OPP_PIPE_CRC_RESULT0_BASE_IDX 2
#define mmOPP_PIPE_CRC0_OPP_PIPE_CRC_RESULT1 0x1894
#define mmOPP_PIPE_CRC0_OPP_PIPE_CRC_RESULT1_BASE_IDX 2
#define mmOPP_PIPE_CRC0_OPP_PIPE_CRC_RESULT2 0x1895
#define mmOPP_PIPE_CRC0_OPP_PIPE_CRC_RESULT2_BASE_IDX 2
// addressBlock: dce_dc_opp_fmt1_dispdec
// base address: 0x168
#define mmFMT1_FMT_CLAMP_COMPONENT_R 0x1896
#define mmFMT1_FMT_CLAMP_COMPONENT_R_BASE_IDX 2
#define mmFMT1_FMT_CLAMP_COMPONENT_G 0x1897
#define mmFMT1_FMT_CLAMP_COMPONENT_G_BASE_IDX 2
#define mmFMT1_FMT_CLAMP_COMPONENT_B 0x1898
#define mmFMT1_FMT_CLAMP_COMPONENT_B_BASE_IDX 2
#define mmFMT1_FMT_DYNAMIC_EXP_CNTL 0x1899
#define mmFMT1_FMT_DYNAMIC_EXP_CNTL_BASE_IDX 2
#define mmFMT1_FMT_CONTROL 0x189a
#define mmFMT1_FMT_CONTROL_BASE_IDX 2
#define mmFMT1_FMT_BIT_DEPTH_CONTROL 0x189b
#define mmFMT1_FMT_BIT_DEPTH_CONTROL_BASE_IDX 2
#define mmFMT1_FMT_DITHER_RAND_R_SEED 0x189c
#define mmFMT1_FMT_DITHER_RAND_R_SEED_BASE_IDX 2
#define mmFMT1_FMT_DITHER_RAND_G_SEED 0x189d
#define mmFMT1_FMT_DITHER_RAND_G_SEED_BASE_IDX 2
#define mmFMT1_FMT_DITHER_RAND_B_SEED 0x189e
#define mmFMT1_FMT_DITHER_RAND_B_SEED_BASE_IDX 2
#define mmFMT1_FMT_CLAMP_CNTL 0x189f
#define mmFMT1_FMT_CLAMP_CNTL_BASE_IDX 2
#define mmFMT1_FMT_SIDE_BY_SIDE_STEREO_CONTROL 0x18a0
#define mmFMT1_FMT_SIDE_BY_SIDE_STEREO_CONTROL_BASE_IDX 2
#define mmFMT1_FMT_MAP420_MEMORY_CONTROL 0x18a1
#define mmFMT1_FMT_MAP420_MEMORY_CONTROL_BASE_IDX 2
#define mmFMT1_FMT_422_CONTROL 0x18a3
#define mmFMT1_FMT_422_CONTROL_BASE_IDX 2
// addressBlock: dce_dc_opp_dpg1_dispdec
// base address: 0x168
#define mmDPG1_DPG_CONTROL 0x18ae
#define mmDPG1_DPG_CONTROL_BASE_IDX 2
#define mmDPG1_DPG_RAMP_CONTROL 0x18af
#define mmDPG1_DPG_RAMP_CONTROL_BASE_IDX 2
#define mmDPG1_DPG_DIMENSIONS 0x18b0
#define mmDPG1_DPG_DIMENSIONS_BASE_IDX 2
#define mmDPG1_DPG_COLOUR_R_CR 0x18b1
#define mmDPG1_DPG_COLOUR_R_CR_BASE_IDX 2
#define mmDPG1_DPG_COLOUR_G_Y 0x18b2
#define mmDPG1_DPG_COLOUR_G_Y_BASE_IDX 2
#define mmDPG1_DPG_COLOUR_B_CB 0x18b3
#define mmDPG1_DPG_COLOUR_B_CB_BASE_IDX 2
#define mmDPG1_DPG_OFFSET_SEGMENT 0x18b4
#define mmDPG1_DPG_OFFSET_SEGMENT_BASE_IDX 2
#define mmDPG1_DPG_STATUS 0x18b5
#define mmDPG1_DPG_STATUS_BASE_IDX 2
// addressBlock: dce_dc_opp_oppbuf1_dispdec
// base address: 0x168
#define mmOPPBUF1_OPPBUF_CONTROL 0x18de
#define mmOPPBUF1_OPPBUF_CONTROL_BASE_IDX 2
#define mmOPPBUF1_OPPBUF_3D_PARAMETERS_0 0x18df
#define mmOPPBUF1_OPPBUF_3D_PARAMETERS_0_BASE_IDX 2
#define mmOPPBUF1_OPPBUF_3D_PARAMETERS_1 0x18e0
#define mmOPPBUF1_OPPBUF_3D_PARAMETERS_1_BASE_IDX 2
#define mmOPPBUF1_OPPBUF_CONTROL1 0x18e3
#define mmOPPBUF1_OPPBUF_CONTROL1_BASE_IDX 2
// addressBlock: dce_dc_opp_opp_pipe1_dispdec
// base address: 0x168
#define mmOPP_PIPE1_OPP_PIPE_CONTROL 0x18e6
#define mmOPP_PIPE1_OPP_PIPE_CONTROL_BASE_IDX 2
// addressBlock: dce_dc_opp_opp_pipe_crc1_dispdec
// base address: 0x168
#define mmOPP_PIPE_CRC1_OPP_PIPE_CRC_CONTROL 0x18eb
#define mmOPP_PIPE_CRC1_OPP_PIPE_CRC_CONTROL_BASE_IDX 2
#define mmOPP_PIPE_CRC1_OPP_PIPE_CRC_MASK 0x18ec
#define mmOPP_PIPE_CRC1_OPP_PIPE_CRC_MASK_BASE_IDX 2
#define mmOPP_PIPE_CRC1_OPP_PIPE_CRC_RESULT0 0x18ed
#define mmOPP_PIPE_CRC1_OPP_PIPE_CRC_RESULT0_BASE_IDX 2
#define mmOPP_PIPE_CRC1_OPP_PIPE_CRC_RESULT1 0x18ee
#define mmOPP_PIPE_CRC1_OPP_PIPE_CRC_RESULT1_BASE_IDX 2
#define mmOPP_PIPE_CRC1_OPP_PIPE_CRC_RESULT2 0x18ef
#define mmOPP_PIPE_CRC1_OPP_PIPE_CRC_RESULT2_BASE_IDX 2
// addressBlock: dce_dc_opp_fmt2_dispdec
// base address: 0x2d0
#define mmFMT2_FMT_CLAMP_COMPONENT_R 0x18f0
#define mmFMT2_FMT_CLAMP_COMPONENT_R_BASE_IDX 2
#define mmFMT2_FMT_CLAMP_COMPONENT_G 0x18f1
#define mmFMT2_FMT_CLAMP_COMPONENT_G_BASE_IDX 2
#define mmFMT2_FMT_CLAMP_COMPONENT_B 0x18f2
#define mmFMT2_FMT_CLAMP_COMPONENT_B_BASE_IDX 2
#define mmFMT2_FMT_DYNAMIC_EXP_CNTL 0x18f3
#define mmFMT2_FMT_DYNAMIC_EXP_CNTL_BASE_IDX 2
#define mmFMT2_FMT_CONTROL 0x18f4
#define mmFMT2_FMT_CONTROL_BASE_IDX 2
#define mmFMT2_FMT_BIT_DEPTH_CONTROL 0x18f5
#define mmFMT2_FMT_BIT_DEPTH_CONTROL_BASE_IDX 2
#define mmFMT2_FMT_DITHER_RAND_R_SEED 0x18f6
#define mmFMT2_FMT_DITHER_RAND_R_SEED_BASE_IDX 2
#define mmFMT2_FMT_DITHER_RAND_G_SEED 0x18f7
#define mmFMT2_FMT_DITHER_RAND_G_SEED_BASE_IDX 2
#define mmFMT2_FMT_DITHER_RAND_B_SEED 0x18f8
#define mmFMT2_FMT_DITHER_RAND_B_SEED_BASE_IDX 2
#define mmFMT2_FMT_CLAMP_CNTL 0x18f9
#define mmFMT2_FMT_CLAMP_CNTL_BASE_IDX 2
#define mmFMT2_FMT_SIDE_BY_SIDE_STEREO_CONTROL 0x18fa
#define mmFMT2_FMT_SIDE_BY_SIDE_STEREO_CONTROL_BASE_IDX 2
#define mmFMT2_FMT_MAP420_MEMORY_CONTROL 0x18fb
#define mmFMT2_FMT_MAP420_MEMORY_CONTROL_BASE_IDX 2
#define mmFMT2_FMT_422_CONTROL 0x18fd
#define mmFMT2_FMT_422_CONTROL_BASE_IDX 2
// addressBlock: dce_dc_opp_dpg2_dispdec
// base address: 0x2d0
#define mmDPG2_DPG_CONTROL 0x1908
#define mmDPG2_DPG_CONTROL_BASE_IDX 2
#define mmDPG2_DPG_RAMP_CONTROL 0x1909
#define mmDPG2_DPG_RAMP_CONTROL_BASE_IDX 2
#define mmDPG2_DPG_DIMENSIONS 0x190a
#define mmDPG2_DPG_DIMENSIONS_BASE_IDX 2
#define mmDPG2_DPG_COLOUR_R_CR 0x190b
#define mmDPG2_DPG_COLOUR_R_CR_BASE_IDX 2
#define mmDPG2_DPG_COLOUR_G_Y 0x190c
#define mmDPG2_DPG_COLOUR_G_Y_BASE_IDX 2
#define mmDPG2_DPG_COLOUR_B_CB 0x190d
#define mmDPG2_DPG_COLOUR_B_CB_BASE_IDX 2
#define mmDPG2_DPG_OFFSET_SEGMENT 0x190e
#define mmDPG2_DPG_OFFSET_SEGMENT_BASE_IDX 2
#define mmDPG2_DPG_STATUS 0x190f
#define mmDPG2_DPG_STATUS_BASE_IDX 2
// addressBlock: dce_dc_opp_oppbuf2_dispdec
// base address: 0x2d0
#define mmOPPBUF2_OPPBUF_CONTROL 0x1938
#define mmOPPBUF2_OPPBUF_CONTROL_BASE_IDX 2
#define mmOPPBUF2_OPPBUF_3D_PARAMETERS_0 0x1939
#define mmOPPBUF2_OPPBUF_3D_PARAMETERS_0_BASE_IDX 2
#define mmOPPBUF2_OPPBUF_3D_PARAMETERS_1 0x193a
#define mmOPPBUF2_OPPBUF_3D_PARAMETERS_1_BASE_IDX 2
#define mmOPPBUF2_OPPBUF_CONTROL1 0x193d
#define mmOPPBUF2_OPPBUF_CONTROL1_BASE_IDX 2
// addressBlock: dce_dc_opp_opp_pipe2_dispdec
// base address: 0x2d0
#define mmOPP_PIPE2_OPP_PIPE_CONTROL 0x1940
#define mmOPP_PIPE2_OPP_PIPE_CONTROL_BASE_IDX 2
// addressBlock: dce_dc_opp_opp_pipe_crc2_dispdec
// base address: 0x2d0
#define mmOPP_PIPE_CRC2_OPP_PIPE_CRC_CONTROL 0x1945
#define mmOPP_PIPE_CRC2_OPP_PIPE_CRC_CONTROL_BASE_IDX 2
#define mmOPP_PIPE_CRC2_OPP_PIPE_CRC_MASK 0x1946
#define mmOPP_PIPE_CRC2_OPP_PIPE_CRC_MASK_BASE_IDX 2
#define mmOPP_PIPE_CRC2_OPP_PIPE_CRC_RESULT0 0x1947
#define mmOPP_PIPE_CRC2_OPP_PIPE_CRC_RESULT0_BASE_IDX 2
#define mmOPP_PIPE_CRC2_OPP_PIPE_CRC_RESULT1 0x1948
#define mmOPP_PIPE_CRC2_OPP_PIPE_CRC_RESULT1_BASE_IDX 2
#define mmOPP_PIPE_CRC2_OPP_PIPE_CRC_RESULT2 0x1949
#define mmOPP_PIPE_CRC2_OPP_PIPE_CRC_RESULT2_BASE_IDX 2
// addressBlock: dce_dc_opp_fmt3_dispdec
// base address: 0x438
#define mmFMT3_FMT_CLAMP_COMPONENT_R 0x194a
#define mmFMT3_FMT_CLAMP_COMPONENT_R_BASE_IDX 2
#define mmFMT3_FMT_CLAMP_COMPONENT_G 0x194b
#define mmFMT3_FMT_CLAMP_COMPONENT_G_BASE_IDX 2
#define mmFMT3_FMT_CLAMP_COMPONENT_B 0x194c
#define mmFMT3_FMT_CLAMP_COMPONENT_B_BASE_IDX 2
#define mmFMT3_FMT_DYNAMIC_EXP_CNTL 0x194d
#define mmFMT3_FMT_DYNAMIC_EXP_CNTL_BASE_IDX 2
#define mmFMT3_FMT_CONTROL 0x194e
#define mmFMT3_FMT_CONTROL_BASE_IDX 2
#define mmFMT3_FMT_BIT_DEPTH_CONTROL 0x194f
#define mmFMT3_FMT_BIT_DEPTH_CONTROL_BASE_IDX 2
#define mmFMT3_FMT_DITHER_RAND_R_SEED 0x1950
#define mmFMT3_FMT_DITHER_RAND_R_SEED_BASE_IDX 2
#define mmFMT3_FMT_DITHER_RAND_G_SEED 0x1951
#define mmFMT3_FMT_DITHER_RAND_G_SEED_BASE_IDX 2
#define mmFMT3_FMT_DITHER_RAND_B_SEED 0x1952
#define mmFMT3_FMT_DITHER_RAND_B_SEED_BASE_IDX 2
#define mmFMT3_FMT_CLAMP_CNTL 0x1953
#define mmFMT3_FMT_CLAMP_CNTL_BASE_IDX 2
#define mmFMT3_FMT_SIDE_BY_SIDE_STEREO_CONTROL 0x1954
#define mmFMT3_FMT_SIDE_BY_SIDE_STEREO_CONTROL_BASE_IDX 2
#define mmFMT3_FMT_MAP420_MEMORY_CONTROL 0x1955
#define mmFMT3_FMT_MAP420_MEMORY_CONTROL_BASE_IDX 2
#define mmFMT3_FMT_422_CONTROL 0x1957
#define mmFMT3_FMT_422_CONTROL_BASE_IDX 2
// addressBlock: dce_dc_opp_dpg3_dispdec
// base address: 0x438
#define mmDPG3_DPG_CONTROL 0x1962
#define mmDPG3_DPG_CONTROL_BASE_IDX 2
#define mmDPG3_DPG_RAMP_CONTROL 0x1963
#define mmDPG3_DPG_RAMP_CONTROL_BASE_IDX 2
#define mmDPG3_DPG_DIMENSIONS 0x1964
#define mmDPG3_DPG_DIMENSIONS_BASE_IDX 2
#define mmDPG3_DPG_COLOUR_R_CR 0x1965
#define mmDPG3_DPG_COLOUR_R_CR_BASE_IDX 2
#define mmDPG3_DPG_COLOUR_G_Y 0x1966
#define mmDPG3_DPG_COLOUR_G_Y_BASE_IDX 2
#define mmDPG3_DPG_COLOUR_B_CB 0x1967
#define mmDPG3_DPG_COLOUR_B_CB_BASE_IDX 2
#define mmDPG3_DPG_OFFSET_SEGMENT 0x1968
#define mmDPG3_DPG_OFFSET_SEGMENT_BASE_IDX 2
#define mmDPG3_DPG_STATUS 0x1969
#define mmDPG3_DPG_STATUS_BASE_IDX 2
// addressBlock: dce_dc_opp_oppbuf3_dispdec
// base address: 0x438
#define mmOPPBUF3_OPPBUF_CONTROL 0x1992
#define mmOPPBUF3_OPPBUF_CONTROL_BASE_IDX 2
#define mmOPPBUF3_OPPBUF_3D_PARAMETERS_0 0x1993
#define mmOPPBUF3_OPPBUF_3D_PARAMETERS_0_BASE_IDX 2
#define mmOPPBUF3_OPPBUF_3D_PARAMETERS_1 0x1994
#define mmOPPBUF3_OPPBUF_3D_PARAMETERS_1_BASE_IDX 2
#define mmOPPBUF3_OPPBUF_CONTROL1 0x1997
#define mmOPPBUF3_OPPBUF_CONTROL1_BASE_IDX 2
// addressBlock: dce_dc_opp_opp_pipe3_dispdec
// base address: 0x438
#define mmOPP_PIPE3_OPP_PIPE_CONTROL 0x199a
#define mmOPP_PIPE3_OPP_PIPE_CONTROL_BASE_IDX 2
// addressBlock: dce_dc_opp_opp_pipe_crc3_dispdec
// base address: 0x438
#define mmOPP_PIPE_CRC3_OPP_PIPE_CRC_CONTROL 0x199f
#define mmOPP_PIPE_CRC3_OPP_PIPE_CRC_CONTROL_BASE_IDX 2
#define mmOPP_PIPE_CRC3_OPP_PIPE_CRC_MASK 0x19a0
#define mmOPP_PIPE_CRC3_OPP_PIPE_CRC_MASK_BASE_IDX 2
#define mmOPP_PIPE_CRC3_OPP_PIPE_CRC_RESULT0 0x19a1
#define mmOPP_PIPE_CRC3_OPP_PIPE_CRC_RESULT0_BASE_IDX 2
#define mmOPP_PIPE_CRC3_OPP_PIPE_CRC_RESULT1 0x19a2
#define mmOPP_PIPE_CRC3_OPP_PIPE_CRC_RESULT1_BASE_IDX 2
#define mmOPP_PIPE_CRC3_OPP_PIPE_CRC_RESULT2 0x19a3
#define mmOPP_PIPE_CRC3_OPP_PIPE_CRC_RESULT2_BASE_IDX 2
// addressBlock: dce_dc_opp_fmt4_dispdec
// base address: 0x5a0
#define mmFMT4_FMT_CLAMP_COMPONENT_R 0x19a4
#define mmFMT4_FMT_CLAMP_COMPONENT_R_BASE_IDX 2
#define mmFMT4_FMT_CLAMP_COMPONENT_G 0x19a5
#define mmFMT4_FMT_CLAMP_COMPONENT_G_BASE_IDX 2
#define mmFMT4_FMT_CLAMP_COMPONENT_B 0x19a6
#define mmFMT4_FMT_CLAMP_COMPONENT_B_BASE_IDX 2
#define mmFMT4_FMT_DYNAMIC_EXP_CNTL 0x19a7
#define mmFMT4_FMT_DYNAMIC_EXP_CNTL_BASE_IDX 2
#define mmFMT4_FMT_CONTROL 0x19a8
#define mmFMT4_FMT_CONTROL_BASE_IDX 2
#define mmFMT4_FMT_BIT_DEPTH_CONTROL 0x19a9
#define mmFMT4_FMT_BIT_DEPTH_CONTROL_BASE_IDX 2
#define mmFMT4_FMT_DITHER_RAND_R_SEED 0x19aa
#define mmFMT4_FMT_DITHER_RAND_R_SEED_BASE_IDX 2
#define mmFMT4_FMT_DITHER_RAND_G_SEED 0x19ab
#define mmFMT4_FMT_DITHER_RAND_G_SEED_BASE_IDX 2
#define mmFMT4_FMT_DITHER_RAND_B_SEED 0x19ac
#define mmFMT4_FMT_DITHER_RAND_B_SEED_BASE_IDX 2
#define mmFMT4_FMT_CLAMP_CNTL 0x19ad
#define mmFMT4_FMT_CLAMP_CNTL_BASE_IDX 2
#define mmFMT4_FMT_SIDE_BY_SIDE_STEREO_CONTROL 0x19ae
#define mmFMT4_FMT_SIDE_BY_SIDE_STEREO_CONTROL_BASE_IDX 2
#define mmFMT4_FMT_MAP420_MEMORY_CONTROL 0x19af
#define mmFMT4_FMT_MAP420_MEMORY_CONTROL_BASE_IDX 2
#define mmFMT4_FMT_422_CONTROL 0x19b1
#define mmFMT4_FMT_422_CONTROL_BASE_IDX 2
// addressBlock: dce_dc_opp_dpg4_dispdec
// base address: 0x5a0
#define mmDPG4_DPG_CONTROL 0x19bc
#define mmDPG4_DPG_CONTROL_BASE_IDX 2
#define mmDPG4_DPG_RAMP_CONTROL 0x19bd
#define mmDPG4_DPG_RAMP_CONTROL_BASE_IDX 2
#define mmDPG4_DPG_DIMENSIONS 0x19be
#define mmDPG4_DPG_DIMENSIONS_BASE_IDX 2
#define mmDPG4_DPG_COLOUR_R_CR 0x19bf
#define mmDPG4_DPG_COLOUR_R_CR_BASE_IDX 2
#define mmDPG4_DPG_COLOUR_G_Y 0x19c0
#define mmDPG4_DPG_COLOUR_G_Y_BASE_IDX 2
#define mmDPG4_DPG_COLOUR_B_CB 0x19c1
#define mmDPG4_DPG_COLOUR_B_CB_BASE_IDX 2
#define mmDPG4_DPG_OFFSET_SEGMENT 0x19c2
#define mmDPG4_DPG_OFFSET_SEGMENT_BASE_IDX 2
#define mmDPG4_DPG_STATUS 0x19c3
#define mmDPG4_DPG_STATUS_BASE_IDX 2
// addressBlock: dce_dc_opp_oppbuf4_dispdec
// base address: 0x5a0
#define mmOPPBUF4_OPPBUF_CONTROL 0x19ec
#define mmOPPBUF4_OPPBUF_CONTROL_BASE_IDX 2
#define mmOPPBUF4_OPPBUF_3D_PARAMETERS_0 0x19ed
#define mmOPPBUF4_OPPBUF_3D_PARAMETERS_0_BASE_IDX 2
#define mmOPPBUF4_OPPBUF_3D_PARAMETERS_1 0x19ee
#define mmOPPBUF4_OPPBUF_3D_PARAMETERS_1_BASE_IDX 2
#define mmOPPBUF4_OPPBUF_CONTROL1 0x19f1
#define mmOPPBUF4_OPPBUF_CONTROL1_BASE_IDX 2
// addressBlock: dce_dc_opp_opp_pipe4_dispdec
// base address: 0x5a0
#define mmOPP_PIPE4_OPP_PIPE_CONTROL 0x19f4
#define mmOPP_PIPE4_OPP_PIPE_CONTROL_BASE_IDX 2
// addressBlock: dce_dc_opp_opp_pipe_crc4_dispdec
// base address: 0x5a0
#define mmOPP_PIPE_CRC4_OPP_PIPE_CRC_CONTROL 0x19f9
#define mmOPP_PIPE_CRC4_OPP_PIPE_CRC_CONTROL_BASE_IDX 2
#define mmOPP_PIPE_CRC4_OPP_PIPE_CRC_MASK 0x19fa
#define mmOPP_PIPE_CRC4_OPP_PIPE_CRC_MASK_BASE_IDX 2
#define mmOPP_PIPE_CRC4_OPP_PIPE_CRC_RESULT0 0x19fb
#define mmOPP_PIPE_CRC4_OPP_PIPE_CRC_RESULT0_BASE_IDX 2
#define mmOPP_PIPE_CRC4_OPP_PIPE_CRC_RESULT1 0x19fc
#define mmOPP_PIPE_CRC4_OPP_PIPE_CRC_RESULT1_BASE_IDX 2
#define mmOPP_PIPE_CRC4_OPP_PIPE_CRC_RESULT2 0x19fd
#define mmOPP_PIPE_CRC4_OPP_PIPE_CRC_RESULT2_BASE_IDX 2
// addressBlock: dce_dc_opp_opp_top_dispdec
// base address: 0x0
#define mmOPP_TOP_CLK_CONTROL 0x1a5e
#define mmOPP_TOP_CLK_CONTROL_BASE_IDX 2
#define mmOPP_ABM_CONTROL 0x1a60
#define mmOPP_ABM_CONTROL_BASE_IDX 2
// addressBlock: dce_dc_opp_dscrm0_dispdec
// base address: 0x0
#define mmDSCRM0_DSCRM_DSC_FORWARD_CONFIG 0x1a64
#define mmDSCRM0_DSCRM_DSC_FORWARD_CONFIG_BASE_IDX 2
// addressBlock: dce_dc_opp_dscrm1_dispdec
// base address: 0x4
#define mmDSCRM1_DSCRM_DSC_FORWARD_CONFIG 0x1a65
#define mmDSCRM1_DSCRM_DSC_FORWARD_CONFIG_BASE_IDX 2
// addressBlock: dce_dc_opp_dscrm2_dispdec
// base address: 0x8
#define mmDSCRM2_DSCRM_DSC_FORWARD_CONFIG 0x1a66
#define mmDSCRM2_DSCRM_DSC_FORWARD_CONFIG_BASE_IDX 2
// addressBlock: dce_dc_opp_dscrm3_dispdec
// base address: 0xc
#define mmDSCRM3_DSCRM_DSC_FORWARD_CONFIG 0x1a67
#define mmDSCRM3_DSCRM_DSC_FORWARD_CONFIG_BASE_IDX 2
// addressBlock: dce_dc_opp_dscrm4_dispdec
// base address: 0x10
#define mmDSCRM4_DSCRM_DSC_FORWARD_CONFIG 0x1a68
#define mmDSCRM4_DSCRM_DSC_FORWARD_CONFIG_BASE_IDX 2
// addressBlock: dce_dc_opp_opp_dcperfmon_dc_perfmon_dispdec
// base address: 0x6af8
#define mmDC_PERFMON16_PERFCOUNTER_CNTL 0x1abe
#define mmDC_PERFMON16_PERFCOUNTER_CNTL_BASE_IDX 2
#define mmDC_PERFMON16_PERFCOUNTER_CNTL2 0x1abf
#define mmDC_PERFMON16_PERFCOUNTER_CNTL2_BASE_IDX 2
#define mmDC_PERFMON16_PERFCOUNTER_STATE 0x1ac0
#define mmDC_PERFMON16_PERFCOUNTER_STATE_BASE_IDX 2
#define mmDC_PERFMON16_PERFMON_CNTL 0x1ac1
#define mmDC_PERFMON16_PERFMON_CNTL_BASE_IDX 2
#define mmDC_PERFMON16_PERFMON_CNTL2 0x1ac2
#define mmDC_PERFMON16_PERFMON_CNTL2_BASE_IDX 2
#define mmDC_PERFMON16_PERFMON_CVALUE_INT_MISC 0x1ac3
#define mmDC_PERFMON16_PERFMON_CVALUE_INT_MISC_BASE_IDX 2
#define mmDC_PERFMON16_PERFMON_CVALUE_LOW 0x1ac4
#define mmDC_PERFMON16_PERFMON_CVALUE_LOW_BASE_IDX 2
#define mmDC_PERFMON16_PERFMON_HI 0x1ac5
#define mmDC_PERFMON16_PERFMON_HI_BASE_IDX 2
#define mmDC_PERFMON16_PERFMON_LOW 0x1ac6
#define mmDC_PERFMON16_PERFMON_LOW_BASE_IDX 2
// addressBlock: dce_dc_optc_odm0_dispdec
// base address: 0x0
#define mmODM0_OPTC_INPUT_GLOBAL_CONTROL 0x1aca
#define mmODM0_OPTC_INPUT_GLOBAL_CONTROL_BASE_IDX 2
#define mmODM0_OPTC_DATA_SOURCE_SELECT 0x1acb
#define mmODM0_OPTC_DATA_SOURCE_SELECT_BASE_IDX 2
#define mmODM0_OPTC_DATA_FORMAT_CONTROL 0x1acc
#define mmODM0_OPTC_DATA_FORMAT_CONTROL_BASE_IDX 2
#define mmODM0_OPTC_BYTES_PER_PIXEL 0x1acd
#define mmODM0_OPTC_BYTES_PER_PIXEL_BASE_IDX 2
#define mmODM0_OPTC_WIDTH_CONTROL 0x1ace
#define mmODM0_OPTC_WIDTH_CONTROL_BASE_IDX 2
#define mmODM0_OPTC_INPUT_CLOCK_CONTROL 0x1acf
#define mmODM0_OPTC_INPUT_CLOCK_CONTROL_BASE_IDX 2
#define mmODM0_OPTC_MEMORY_CONFIG 0x1ad0
#define mmODM0_OPTC_MEMORY_CONFIG_BASE_IDX 2
#define mmODM0_OPTC_INPUT_SPARE_REGISTER 0x1ad1
#define mmODM0_OPTC_INPUT_SPARE_REGISTER_BASE_IDX 2
// addressBlock: dce_dc_optc_odm1_dispdec
// base address: 0x40
#define mmODM1_OPTC_INPUT_GLOBAL_CONTROL 0x1ada
#define mmODM1_OPTC_INPUT_GLOBAL_CONTROL_BASE_IDX 2
#define mmODM1_OPTC_DATA_SOURCE_SELECT 0x1adb
#define mmODM1_OPTC_DATA_SOURCE_SELECT_BASE_IDX 2
#define mmODM1_OPTC_DATA_FORMAT_CONTROL 0x1adc
#define mmODM1_OPTC_DATA_FORMAT_CONTROL_BASE_IDX 2
#define mmODM1_OPTC_BYTES_PER_PIXEL 0x1add
#define mmODM1_OPTC_BYTES_PER_PIXEL_BASE_IDX 2
#define mmODM1_OPTC_WIDTH_CONTROL 0x1ade
#define mmODM1_OPTC_WIDTH_CONTROL_BASE_IDX 2
#define mmODM1_OPTC_INPUT_CLOCK_CONTROL 0x1adf
#define mmODM1_OPTC_INPUT_CLOCK_CONTROL_BASE_IDX 2
#define mmODM1_OPTC_MEMORY_CONFIG 0x1ae0
#define mmODM1_OPTC_MEMORY_CONFIG_BASE_IDX 2
#define mmODM1_OPTC_INPUT_SPARE_REGISTER 0x1ae1
#define mmODM1_OPTC_INPUT_SPARE_REGISTER_BASE_IDX 2
// addressBlock: dce_dc_optc_odm2_dispdec
// base address: 0x80
#define mmODM2_OPTC_INPUT_GLOBAL_CONTROL 0x1aea
#define mmODM2_OPTC_INPUT_GLOBAL_CONTROL_BASE_IDX 2
#define mmODM2_OPTC_DATA_SOURCE_SELECT 0x1aeb
#define mmODM2_OPTC_DATA_SOURCE_SELECT_BASE_IDX 2
#define mmODM2_OPTC_DATA_FORMAT_CONTROL 0x1aec
#define mmODM2_OPTC_DATA_FORMAT_CONTROL_BASE_IDX 2
#define mmODM2_OPTC_BYTES_PER_PIXEL 0x1aed
#define mmODM2_OPTC_BYTES_PER_PIXEL_BASE_IDX 2
#define mmODM2_OPTC_WIDTH_CONTROL 0x1aee
#define mmODM2_OPTC_WIDTH_CONTROL_BASE_IDX 2
#define mmODM2_OPTC_INPUT_CLOCK_CONTROL 0x1aef
#define mmODM2_OPTC_INPUT_CLOCK_CONTROL_BASE_IDX 2
#define mmODM2_OPTC_MEMORY_CONFIG 0x1af0
#define mmODM2_OPTC_MEMORY_CONFIG_BASE_IDX 2
#define mmODM2_OPTC_INPUT_SPARE_REGISTER 0x1af1
#define mmODM2_OPTC_INPUT_SPARE_REGISTER_BASE_IDX 2
// addressBlock: dce_dc_optc_odm3_dispdec
// base address: 0xc0
#define mmODM3_OPTC_INPUT_GLOBAL_CONTROL 0x1afa
#define mmODM3_OPTC_INPUT_GLOBAL_CONTROL_BASE_IDX 2
#define mmODM3_OPTC_DATA_SOURCE_SELECT 0x1afb
#define mmODM3_OPTC_DATA_SOURCE_SELECT_BASE_IDX 2
#define mmODM3_OPTC_DATA_FORMAT_CONTROL 0x1afc
#define mmODM3_OPTC_DATA_FORMAT_CONTROL_BASE_IDX 2
#define mmODM3_OPTC_BYTES_PER_PIXEL 0x1afd
#define mmODM3_OPTC_BYTES_PER_PIXEL_BASE_IDX 2
#define mmODM3_OPTC_WIDTH_CONTROL 0x1afe
#define mmODM3_OPTC_WIDTH_CONTROL_BASE_IDX 2
#define mmODM3_OPTC_INPUT_CLOCK_CONTROL 0x1aff
#define mmODM3_OPTC_INPUT_CLOCK_CONTROL_BASE_IDX 2
#define mmODM3_OPTC_MEMORY_CONFIG 0x1b00
#define mmODM3_OPTC_MEMORY_CONFIG_BASE_IDX 2
#define mmODM3_OPTC_INPUT_SPARE_REGISTER 0x1b01
#define mmODM3_OPTC_INPUT_SPARE_REGISTER_BASE_IDX 2
// addressBlock: dce_dc_optc_odm4_dispdec
// base address: 0x100
#define mmODM4_OPTC_INPUT_GLOBAL_CONTROL 0x1b0a
#define mmODM4_OPTC_INPUT_GLOBAL_CONTROL_BASE_IDX 2
#define mmODM4_OPTC_DATA_SOURCE_SELECT 0x1b0b
#define mmODM4_OPTC_DATA_SOURCE_SELECT_BASE_IDX 2
#define mmODM4_OPTC_DATA_FORMAT_CONTROL 0x1b0c
#define mmODM4_OPTC_DATA_FORMAT_CONTROL_BASE_IDX 2
#define mmODM4_OPTC_BYTES_PER_PIXEL 0x1b0d
#define mmODM4_OPTC_BYTES_PER_PIXEL_BASE_IDX 2
#define mmODM4_OPTC_WIDTH_CONTROL 0x1b0e
#define mmODM4_OPTC_WIDTH_CONTROL_BASE_IDX 2
#define mmODM4_OPTC_INPUT_CLOCK_CONTROL 0x1b0f
#define mmODM4_OPTC_INPUT_CLOCK_CONTROL_BASE_IDX 2
#define mmODM4_OPTC_MEMORY_CONFIG 0x1b10
#define mmODM4_OPTC_MEMORY_CONFIG_BASE_IDX 2
#define mmODM4_OPTC_INPUT_SPARE_REGISTER 0x1b11
#define mmODM4_OPTC_INPUT_SPARE_REGISTER_BASE_IDX 2
// addressBlock: dce_dc_optc_otg0_dispdec
// base address: 0x0
#define mmOTG0_OTG_H_TOTAL 0x1b2a
#define mmOTG0_OTG_H_TOTAL_BASE_IDX 2
#define mmOTG0_OTG_H_BLANK_START_END 0x1b2b
#define mmOTG0_OTG_H_BLANK_START_END_BASE_IDX 2
#define mmOTG0_OTG_H_SYNC_A 0x1b2c
#define mmOTG0_OTG_H_SYNC_A_BASE_IDX 2
#define mmOTG0_OTG_H_SYNC_A_CNTL 0x1b2d
#define mmOTG0_OTG_H_SYNC_A_CNTL_BASE_IDX 2
#define mmOTG0_OTG_H_TIMING_CNTL 0x1b2e
#define mmOTG0_OTG_H_TIMING_CNTL_BASE_IDX 2
#define mmOTG0_OTG_V_TOTAL 0x1b2f
#define mmOTG0_OTG_V_TOTAL_BASE_IDX 2
#define mmOTG0_OTG_V_TOTAL_MIN 0x1b30
#define mmOTG0_OTG_V_TOTAL_MIN_BASE_IDX 2
#define mmOTG0_OTG_V_TOTAL_MAX 0x1b31
#define mmOTG0_OTG_V_TOTAL_MAX_BASE_IDX 2
#define mmOTG0_OTG_V_TOTAL_MID 0x1b32
#define mmOTG0_OTG_V_TOTAL_MID_BASE_IDX 2
#define mmOTG0_OTG_V_TOTAL_CONTROL 0x1b33
#define mmOTG0_OTG_V_TOTAL_CONTROL_BASE_IDX 2
#define mmOTG0_OTG_V_TOTAL_INT_STATUS 0x1b34
#define mmOTG0_OTG_V_TOTAL_INT_STATUS_BASE_IDX 2
#define mmOTG0_OTG_VSYNC_NOM_INT_STATUS 0x1b35
#define mmOTG0_OTG_VSYNC_NOM_INT_STATUS_BASE_IDX 2
#define mmOTG0_OTG_V_BLANK_START_END 0x1b36
#define mmOTG0_OTG_V_BLANK_START_END_BASE_IDX 2
#define mmOTG0_OTG_V_SYNC_A 0x1b37
#define mmOTG0_OTG_V_SYNC_A_BASE_IDX 2
#define mmOTG0_OTG_V_SYNC_A_CNTL 0x1b38
#define mmOTG0_OTG_V_SYNC_A_CNTL_BASE_IDX 2
#define mmOTG0_OTG_TRIGA_CNTL 0x1b39
#define mmOTG0_OTG_TRIGA_CNTL_BASE_IDX 2
#define mmOTG0_OTG_TRIGA_MANUAL_TRIG 0x1b3a
#define mmOTG0_OTG_TRIGA_MANUAL_TRIG_BASE_IDX 2
#define mmOTG0_OTG_TRIGB_CNTL 0x1b3b
#define mmOTG0_OTG_TRIGB_CNTL_BASE_IDX 2
#define mmOTG0_OTG_TRIGB_MANUAL_TRIG 0x1b3c
#define mmOTG0_OTG_TRIGB_MANUAL_TRIG_BASE_IDX 2
#define mmOTG0_OTG_FORCE_COUNT_NOW_CNTL 0x1b3d
#define mmOTG0_OTG_FORCE_COUNT_NOW_CNTL_BASE_IDX 2
#define mmOTG0_OTG_FLOW_CONTROL 0x1b3e
#define mmOTG0_OTG_FLOW_CONTROL_BASE_IDX 2
#define mmOTG0_OTG_STEREO_FORCE_NEXT_EYE 0x1b3f
#define mmOTG0_OTG_STEREO_FORCE_NEXT_EYE_BASE_IDX 2
#define mmOTG0_OTG_CONTROL 0x1b41
#define mmOTG0_OTG_CONTROL_BASE_IDX 2
#define mmOTG0_OTG_INTERLACE_CONTROL 0x1b44
#define mmOTG0_OTG_INTERLACE_CONTROL_BASE_IDX 2
#define mmOTG0_OTG_INTERLACE_STATUS 0x1b45
#define mmOTG0_OTG_INTERLACE_STATUS_BASE_IDX 2
#define mmOTG0_OTG_PIXEL_DATA_READBACK0 0x1b47
#define mmOTG0_OTG_PIXEL_DATA_READBACK0_BASE_IDX 2
#define mmOTG0_OTG_PIXEL_DATA_READBACK1 0x1b48
#define mmOTG0_OTG_PIXEL_DATA_READBACK1_BASE_IDX 2
#define mmOTG0_OTG_STATUS 0x1b49
#define mmOTG0_OTG_STATUS_BASE_IDX 2
#define mmOTG0_OTG_STATUS_POSITION 0x1b4a
#define mmOTG0_OTG_STATUS_POSITION_BASE_IDX 2
#define mmOTG0_OTG_NOM_VERT_POSITION 0x1b4b
#define mmOTG0_OTG_NOM_VERT_POSITION_BASE_IDX 2
#define mmOTG0_OTG_STATUS_FRAME_COUNT 0x1b4c
#define mmOTG0_OTG_STATUS_FRAME_COUNT_BASE_IDX 2
#define mmOTG0_OTG_STATUS_VF_COUNT 0x1b4d
#define mmOTG0_OTG_STATUS_VF_COUNT_BASE_IDX 2
#define mmOTG0_OTG_STATUS_HV_COUNT 0x1b4e
#define mmOTG0_OTG_STATUS_HV_COUNT_BASE_IDX 2
#define mmOTG0_OTG_COUNT_CONTROL 0x1b4f
#define mmOTG0_OTG_COUNT_CONTROL_BASE_IDX 2
#define mmOTG0_OTG_COUNT_RESET 0x1b50
#define mmOTG0_OTG_COUNT_RESET_BASE_IDX 2
#define mmOTG0_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE 0x1b51
#define mmOTG0_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE_BASE_IDX 2
#define mmOTG0_OTG_VERT_SYNC_CONTROL 0x1b52
#define mmOTG0_OTG_VERT_SYNC_CONTROL_BASE_IDX 2
#define mmOTG0_OTG_STEREO_STATUS 0x1b53
#define mmOTG0_OTG_STEREO_STATUS_BASE_IDX 2
#define mmOTG0_OTG_STEREO_CONTROL 0x1b54
#define mmOTG0_OTG_STEREO_CONTROL_BASE_IDX 2
#define mmOTG0_OTG_SNAPSHOT_STATUS 0x1b55
#define mmOTG0_OTG_SNAPSHOT_STATUS_BASE_IDX 2
#define mmOTG0_OTG_SNAPSHOT_CONTROL 0x1b56
#define mmOTG0_OTG_SNAPSHOT_CONTROL_BASE_IDX 2
#define mmOTG0_OTG_SNAPSHOT_POSITION 0x1b57
#define mmOTG0_OTG_SNAPSHOT_POSITION_BASE_IDX 2
#define mmOTG0_OTG_SNAPSHOT_FRAME 0x1b58
#define mmOTG0_OTG_SNAPSHOT_FRAME_BASE_IDX 2
#define mmOTG0_OTG_INTERRUPT_CONTROL 0x1b59
#define mmOTG0_OTG_INTERRUPT_CONTROL_BASE_IDX 2
#define mmOTG0_OTG_UPDATE_LOCK 0x1b5a
#define mmOTG0_OTG_UPDATE_LOCK_BASE_IDX 2
#define mmOTG0_OTG_DOUBLE_BUFFER_CONTROL 0x1b5b
#define mmOTG0_OTG_DOUBLE_BUFFER_CONTROL_BASE_IDX 2
#define mmOTG0_OTG_MASTER_EN 0x1b5c
#define mmOTG0_OTG_MASTER_EN_BASE_IDX 2
#define mmOTG0_OTG_BLANK_DATA_COLOR 0x1b5e
#define mmOTG0_OTG_BLANK_DATA_COLOR_BASE_IDX 2
#define mmOTG0_OTG_BLANK_DATA_COLOR_EXT 0x1b5f
#define mmOTG0_OTG_BLANK_DATA_COLOR_EXT_BASE_IDX 2
#define mmOTG0_OTG_VERTICAL_INTERRUPT0_POSITION 0x1b62
#define mmOTG0_OTG_VERTICAL_INTERRUPT0_POSITION_BASE_IDX 2
#define mmOTG0_OTG_VERTICAL_INTERRUPT0_CONTROL 0x1b63
#define mmOTG0_OTG_VERTICAL_INTERRUPT0_CONTROL_BASE_IDX 2
#define mmOTG0_OTG_VERTICAL_INTERRUPT1_POSITION 0x1b64
#define mmOTG0_OTG_VERTICAL_INTERRUPT1_POSITION_BASE_IDX 2
#define mmOTG0_OTG_VERTICAL_INTERRUPT1_CONTROL 0x1b65
#define mmOTG0_OTG_VERTICAL_INTERRUPT1_CONTROL_BASE_IDX 2
#define mmOTG0_OTG_VERTICAL_INTERRUPT2_POSITION 0x1b66
#define mmOTG0_OTG_VERTICAL_INTERRUPT2_POSITION_BASE_IDX 2
#define mmOTG0_OTG_VERTICAL_INTERRUPT2_CONTROL 0x1b67
#define mmOTG0_OTG_VERTICAL_INTERRUPT2_CONTROL_BASE_IDX 2
#define mmOTG0_OTG_CRC_CNTL 0x1b68
#define mmOTG0_OTG_CRC_CNTL_BASE_IDX 2
#define mmOTG0_OTG_CRC_CNTL2 0x1b69
#define mmOTG0_OTG_CRC_CNTL2_BASE_IDX 2
#define mmOTG0_OTG_CRC0_WINDOWA_X_CONTROL 0x1b6a
#define mmOTG0_OTG_CRC0_WINDOWA_X_CONTROL_BASE_IDX 2
#define mmOTG0_OTG_CRC0_WINDOWA_Y_CONTROL 0x1b6b
#define mmOTG0_OTG_CRC0_WINDOWA_Y_CONTROL_BASE_IDX 2
#define mmOTG0_OTG_CRC0_WINDOWB_X_CONTROL 0x1b6c
#define mmOTG0_OTG_CRC0_WINDOWB_X_CONTROL_BASE_IDX 2
#define mmOTG0_OTG_CRC0_WINDOWB_Y_CONTROL 0x1b6d
#define mmOTG0_OTG_CRC0_WINDOWB_Y_CONTROL_BASE_IDX 2
#define mmOTG0_OTG_CRC0_DATA_RG 0x1b6e
#define mmOTG0_OTG_CRC0_DATA_RG_BASE_IDX 2
#define mmOTG0_OTG_CRC0_DATA_B 0x1b6f
#define mmOTG0_OTG_CRC0_DATA_B_BASE_IDX 2
#define mmOTG0_OTG_CRC1_WINDOWA_X_CONTROL 0x1b70
#define mmOTG0_OTG_CRC1_WINDOWA_X_CONTROL_BASE_IDX 2
#define mmOTG0_OTG_CRC1_WINDOWA_Y_CONTROL 0x1b71
#define mmOTG0_OTG_CRC1_WINDOWA_Y_CONTROL_BASE_IDX 2
#define mmOTG0_OTG_CRC1_WINDOWB_X_CONTROL 0x1b72
#define mmOTG0_OTG_CRC1_WINDOWB_X_CONTROL_BASE_IDX 2
#define mmOTG0_OTG_CRC1_WINDOWB_Y_CONTROL 0x1b73
#define mmOTG0_OTG_CRC1_WINDOWB_Y_CONTROL_BASE_IDX 2
#define mmOTG0_OTG_CRC1_DATA_RG 0x1b74
#define mmOTG0_OTG_CRC1_DATA_RG_BASE_IDX 2
#define mmOTG0_OTG_CRC1_DATA_B 0x1b75
#define mmOTG0_OTG_CRC1_DATA_B_BASE_IDX 2
#define mmOTG0_OTG_CRC2_DATA_RG 0x1b76
#define mmOTG0_OTG_CRC2_DATA_RG_BASE_IDX 2
#define mmOTG0_OTG_CRC2_DATA_B 0x1b77
#define mmOTG0_OTG_CRC2_DATA_B_BASE_IDX 2
#define mmOTG0_OTG_CRC3_DATA_RG 0x1b78
#define mmOTG0_OTG_CRC3_DATA_RG_BASE_IDX 2
#define mmOTG0_OTG_CRC3_DATA_B 0x1b79
#define mmOTG0_OTG_CRC3_DATA_B_BASE_IDX 2
#define mmOTG0_OTG_CRC_SIG_RED_GREEN_MASK 0x1b7a
#define mmOTG0_OTG_CRC_SIG_RED_GREEN_MASK_BASE_IDX 2
#define mmOTG0_OTG_CRC_SIG_BLUE_CONTROL_MASK 0x1b7b
#define mmOTG0_OTG_CRC_SIG_BLUE_CONTROL_MASK_BASE_IDX 2
#define mmOTG0_OTG_STATIC_SCREEN_CONTROL 0x1b82
#define mmOTG0_OTG_STATIC_SCREEN_CONTROL_BASE_IDX 2
#define mmOTG0_OTG_3D_STRUCTURE_CONTROL 0x1b83
#define mmOTG0_OTG_3D_STRUCTURE_CONTROL_BASE_IDX 2
#define mmOTG0_OTG_GSL_VSYNC_GAP 0x1b84
#define mmOTG0_OTG_GSL_VSYNC_GAP_BASE_IDX 2
#define mmOTG0_OTG_MASTER_UPDATE_MODE 0x1b85
#define mmOTG0_OTG_MASTER_UPDATE_MODE_BASE_IDX 2
#define mmOTG0_OTG_CLOCK_CONTROL 0x1b86
#define mmOTG0_OTG_CLOCK_CONTROL_BASE_IDX 2
#define mmOTG0_OTG_VSTARTUP_PARAM 0x1b87
#define mmOTG0_OTG_VSTARTUP_PARAM_BASE_IDX 2
#define mmOTG0_OTG_VUPDATE_PARAM 0x1b88
#define mmOTG0_OTG_VUPDATE_PARAM_BASE_IDX 2
#define mmOTG0_OTG_VREADY_PARAM 0x1b89
#define mmOTG0_OTG_VREADY_PARAM_BASE_IDX 2
#define mmOTG0_OTG_GLOBAL_SYNC_STATUS 0x1b8a
#define mmOTG0_OTG_GLOBAL_SYNC_STATUS_BASE_IDX 2
#define mmOTG0_OTG_MASTER_UPDATE_LOCK 0x1b8b
#define mmOTG0_OTG_MASTER_UPDATE_LOCK_BASE_IDX 2
#define mmOTG0_OTG_GSL_CONTROL 0x1b8c
#define mmOTG0_OTG_GSL_CONTROL_BASE_IDX 2
#define mmOTG0_OTG_GSL_WINDOW_X 0x1b8d
#define mmOTG0_OTG_GSL_WINDOW_X_BASE_IDX 2
#define mmOTG0_OTG_GSL_WINDOW_Y 0x1b8e
#define mmOTG0_OTG_GSL_WINDOW_Y_BASE_IDX 2
#define mmOTG0_OTG_VUPDATE_KEEPOUT 0x1b8f
#define mmOTG0_OTG_VUPDATE_KEEPOUT_BASE_IDX 2
#define mmOTG0_OTG_GLOBAL_CONTROL0 0x1b90
#define mmOTG0_OTG_GLOBAL_CONTROL0_BASE_IDX 2
#define mmOTG0_OTG_GLOBAL_CONTROL1 0x1b91
#define mmOTG0_OTG_GLOBAL_CONTROL1_BASE_IDX 2
#define mmOTG0_OTG_GLOBAL_CONTROL2 0x1b92
#define mmOTG0_OTG_GLOBAL_CONTROL2_BASE_IDX 2
#define mmOTG0_OTG_GLOBAL_CONTROL3 0x1b93
#define mmOTG0_OTG_GLOBAL_CONTROL3_BASE_IDX 2
#define mmOTG0_OTG_GLOBAL_CONTROL4 0x1b94
#define mmOTG0_OTG_GLOBAL_CONTROL4_BASE_IDX 2
#define mmOTG0_OTG_TRIG_MANUAL_CONTROL 0x1b95
#define mmOTG0_OTG_TRIG_MANUAL_CONTROL_BASE_IDX 2
#define mmOTG0_OTG_MANUAL_FLOW_CONTROL 0x1b96
#define mmOTG0_OTG_MANUAL_FLOW_CONTROL_BASE_IDX 2
#define mmOTG0_OTG_DRR_TIMING_INT_STATUS 0x1b97
#define mmOTG0_OTG_DRR_TIMING_INT_STATUS_BASE_IDX 2
#define mmOTG0_OTG_DRR_V_TOTAL_REACH_RANGE 0x1b98
#define mmOTG0_OTG_DRR_V_TOTAL_REACH_RANGE_BASE_IDX 2
#define mmOTG0_OTG_DRR_V_TOTAL_CHANGE 0x1b99
#define mmOTG0_OTG_DRR_V_TOTAL_CHANGE_BASE_IDX 2
#define mmOTG0_OTG_DRR_TRIGGER_WINDOW 0x1b9a
#define mmOTG0_OTG_DRR_TRIGGER_WINDOW_BASE_IDX 2
#define mmOTG0_OTG_DRR_CONTROL 0x1b9b
#define mmOTG0_OTG_DRR_CONTROL_BASE_IDX 2
#define mmOTG0_OTG_M_CONST_DTO0 0x1b9c
#define mmOTG0_OTG_M_CONST_DTO0_BASE_IDX 2
#define mmOTG0_OTG_M_CONST_DTO1 0x1b9d
#define mmOTG0_OTG_M_CONST_DTO1_BASE_IDX 2
#define mmOTG0_OTG_REQUEST_CONTROL 0x1b9e
#define mmOTG0_OTG_REQUEST_CONTROL_BASE_IDX 2
#define mmOTG0_OTG_DSC_START_POSITION 0x1b9f
#define mmOTG0_OTG_DSC_START_POSITION_BASE_IDX 2
#define mmOTG0_OTG_PIPE_UPDATE_STATUS 0x1ba0
#define mmOTG0_OTG_PIPE_UPDATE_STATUS_BASE_IDX 2
#define mmOTG0_OTG_SPARE_REGISTER 0x1ba2
#define mmOTG0_OTG_SPARE_REGISTER_BASE_IDX 2
// addressBlock: dce_dc_optc_otg1_dispdec
// base address: 0x200
#define mmOTG1_OTG_H_TOTAL 0x1baa
#define mmOTG1_OTG_H_TOTAL_BASE_IDX 2
#define mmOTG1_OTG_H_BLANK_START_END 0x1bab
#define mmOTG1_OTG_H_BLANK_START_END_BASE_IDX 2
#define mmOTG1_OTG_H_SYNC_A 0x1bac
#define mmOTG1_OTG_H_SYNC_A_BASE_IDX 2
#define mmOTG1_OTG_H_SYNC_A_CNTL 0x1bad
#define mmOTG1_OTG_H_SYNC_A_CNTL_BASE_IDX 2
#define mmOTG1_OTG_H_TIMING_CNTL 0x1bae
#define mmOTG1_OTG_H_TIMING_CNTL_BASE_IDX 2
#define mmOTG1_OTG_V_TOTAL 0x1baf
#define mmOTG1_OTG_V_TOTAL_BASE_IDX 2
#define mmOTG1_OTG_V_TOTAL_MIN 0x1bb0
#define mmOTG1_OTG_V_TOTAL_MIN_BASE_IDX 2
#define mmOTG1_OTG_V_TOTAL_MAX 0x1bb1
#define mmOTG1_OTG_V_TOTAL_MAX_BASE_IDX 2
#define mmOTG1_OTG_V_TOTAL_MID 0x1bb2
#define mmOTG1_OTG_V_TOTAL_MID_BASE_IDX 2
#define mmOTG1_OTG_V_TOTAL_CONTROL 0x1bb3
#define mmOTG1_OTG_V_TOTAL_CONTROL_BASE_IDX 2
#define mmOTG1_OTG_V_TOTAL_INT_STATUS 0x1bb4
#define mmOTG1_OTG_V_TOTAL_INT_STATUS_BASE_IDX 2
#define mmOTG1_OTG_VSYNC_NOM_INT_STATUS 0x1bb5
#define mmOTG1_OTG_VSYNC_NOM_INT_STATUS_BASE_IDX 2
#define mmOTG1_OTG_V_BLANK_START_END 0x1bb6
#define mmOTG1_OTG_V_BLANK_START_END_BASE_IDX 2
#define mmOTG1_OTG_V_SYNC_A 0x1bb7
#define mmOTG1_OTG_V_SYNC_A_BASE_IDX 2
#define mmOTG1_OTG_V_SYNC_A_CNTL 0x1bb8
#define mmOTG1_OTG_V_SYNC_A_CNTL_BASE_IDX 2
#define mmOTG1_OTG_TRIGA_CNTL 0x1bb9
#define mmOTG1_OTG_TRIGA_CNTL_BASE_IDX 2
#define mmOTG1_OTG_TRIGA_MANUAL_TRIG 0x1bba
#define mmOTG1_OTG_TRIGA_MANUAL_TRIG_BASE_IDX 2
#define mmOTG1_OTG_TRIGB_CNTL 0x1bbb
#define mmOTG1_OTG_TRIGB_CNTL_BASE_IDX 2
#define mmOTG1_OTG_TRIGB_MANUAL_TRIG 0x1bbc
#define mmOTG1_OTG_TRIGB_MANUAL_TRIG_BASE_IDX 2
#define mmOTG1_OTG_FORCE_COUNT_NOW_CNTL 0x1bbd
#define mmOTG1_OTG_FORCE_COUNT_NOW_CNTL_BASE_IDX 2
#define mmOTG1_OTG_FLOW_CONTROL 0x1bbe
#define mmOTG1_OTG_FLOW_CONTROL_BASE_IDX 2
#define mmOTG1_OTG_STEREO_FORCE_NEXT_EYE 0x1bbf
#define mmOTG1_OTG_STEREO_FORCE_NEXT_EYE_BASE_IDX 2
#define mmOTG1_OTG_CONTROL 0x1bc1
#define mmOTG1_OTG_CONTROL_BASE_IDX 2
#define mmOTG1_OTG_INTERLACE_CONTROL 0x1bc4
#define mmOTG1_OTG_INTERLACE_CONTROL_BASE_IDX 2
#define mmOTG1_OTG_INTERLACE_STATUS 0x1bc5
#define mmOTG1_OTG_INTERLACE_STATUS_BASE_IDX 2
#define mmOTG1_OTG_PIXEL_DATA_READBACK0 0x1bc7
#define mmOTG1_OTG_PIXEL_DATA_READBACK0_BASE_IDX 2
#define mmOTG1_OTG_PIXEL_DATA_READBACK1 0x1bc8
#define mmOTG1_OTG_PIXEL_DATA_READBACK1_BASE_IDX 2
#define mmOTG1_OTG_STATUS 0x1bc9
#define mmOTG1_OTG_STATUS_BASE_IDX 2
#define mmOTG1_OTG_STATUS_POSITION 0x1bca
#define mmOTG1_OTG_STATUS_POSITION_BASE_IDX 2
#define mmOTG1_OTG_NOM_VERT_POSITION 0x1bcb
#define mmOTG1_OTG_NOM_VERT_POSITION_BASE_IDX 2
#define mmOTG1_OTG_STATUS_FRAME_COUNT 0x1bcc
#define mmOTG1_OTG_STATUS_FRAME_COUNT_BASE_IDX 2
#define mmOTG1_OTG_STATUS_VF_COUNT 0x1bcd
#define mmOTG1_OTG_STATUS_VF_COUNT_BASE_IDX 2
#define mmOTG1_OTG_STATUS_HV_COUNT 0x1bce
#define mmOTG1_OTG_STATUS_HV_COUNT_BASE_IDX 2
#define mmOTG1_OTG_COUNT_CONTROL 0x1bcf
#define mmOTG1_OTG_COUNT_CONTROL_BASE_IDX 2
#define mmOTG1_OTG_COUNT_RESET 0x1bd0
#define mmOTG1_OTG_COUNT_RESET_BASE_IDX 2
#define mmOTG1_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE 0x1bd1
#define mmOTG1_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE_BASE_IDX 2
#define mmOTG1_OTG_VERT_SYNC_CONTROL 0x1bd2
#define mmOTG1_OTG_VERT_SYNC_CONTROL_BASE_IDX 2
#define mmOTG1_OTG_STEREO_STATUS 0x1bd3
#define mmOTG1_OTG_STEREO_STATUS_BASE_IDX 2
#define mmOTG1_OTG_STEREO_CONTROL 0x1bd4
#define mmOTG1_OTG_STEREO_CONTROL_BASE_IDX 2
#define mmOTG1_OTG_SNAPSHOT_STATUS 0x1bd5
#define mmOTG1_OTG_SNAPSHOT_STATUS_BASE_IDX 2
#define mmOTG1_OTG_SNAPSHOT_CONTROL 0x1bd6
#define mmOTG1_OTG_SNAPSHOT_CONTROL_BASE_IDX 2
#define mmOTG1_OTG_SNAPSHOT_POSITION 0x1bd7
#define mmOTG1_OTG_SNAPSHOT_POSITION_BASE_IDX 2
#define mmOTG1_OTG_SNAPSHOT_FRAME 0x1bd8
#define mmOTG1_OTG_SNAPSHOT_FRAME_BASE_IDX 2
#define mmOTG1_OTG_INTERRUPT_CONTROL 0x1bd9
#define mmOTG1_OTG_INTERRUPT_CONTROL_BASE_IDX 2
#define mmOTG1_OTG_UPDATE_LOCK 0x1bda
#define mmOTG1_OTG_UPDATE_LOCK_BASE_IDX 2
#define mmOTG1_OTG_DOUBLE_BUFFER_CONTROL 0x1bdb
#define mmOTG1_OTG_DOUBLE_BUFFER_CONTROL_BASE_IDX 2
#define mmOTG1_OTG_MASTER_EN 0x1bdc
#define mmOTG1_OTG_MASTER_EN_BASE_IDX 2
#define mmOTG1_OTG_BLANK_DATA_COLOR 0x1bde
#define mmOTG1_OTG_BLANK_DATA_COLOR_BASE_IDX 2
#define mmOTG1_OTG_BLANK_DATA_COLOR_EXT 0x1bdf
#define mmOTG1_OTG_BLANK_DATA_COLOR_EXT_BASE_IDX 2
#define mmOTG1_OTG_VERTICAL_INTERRUPT0_POSITION 0x1be2
#define mmOTG1_OTG_VERTICAL_INTERRUPT0_POSITION_BASE_IDX 2
#define mmOTG1_OTG_VERTICAL_INTERRUPT0_CONTROL 0x1be3
#define mmOTG1_OTG_VERTICAL_INTERRUPT0_CONTROL_BASE_IDX 2
#define mmOTG1_OTG_VERTICAL_INTERRUPT1_POSITION 0x1be4
#define mmOTG1_OTG_VERTICAL_INTERRUPT1_POSITION_BASE_IDX 2
#define mmOTG1_OTG_VERTICAL_INTERRUPT1_CONTROL 0x1be5
#define mmOTG1_OTG_VERTICAL_INTERRUPT1_CONTROL_BASE_IDX 2
#define mmOTG1_OTG_VERTICAL_INTERRUPT2_POSITION 0x1be6
#define mmOTG1_OTG_VERTICAL_INTERRUPT2_POSITION_BASE_IDX 2
#define mmOTG1_OTG_VERTICAL_INTERRUPT2_CONTROL 0x1be7
#define mmOTG1_OTG_VERTICAL_INTERRUPT2_CONTROL_BASE_IDX 2
#define mmOTG1_OTG_CRC_CNTL 0x1be8
#define mmOTG1_OTG_CRC_CNTL_BASE_IDX 2
#define mmOTG1_OTG_CRC_CNTL2 0x1be9
#define mmOTG1_OTG_CRC_CNTL2_BASE_IDX 2
#define mmOTG1_OTG_CRC0_WINDOWA_X_CONTROL 0x1bea
#define mmOTG1_OTG_CRC0_WINDOWA_X_CONTROL_BASE_IDX 2
#define mmOTG1_OTG_CRC0_WINDOWA_Y_CONTROL 0x1beb
#define mmOTG1_OTG_CRC0_WINDOWA_Y_CONTROL_BASE_IDX 2
#define mmOTG1_OTG_CRC0_WINDOWB_X_CONTROL 0x1bec
#define mmOTG1_OTG_CRC0_WINDOWB_X_CONTROL_BASE_IDX 2
#define mmOTG1_OTG_CRC0_WINDOWB_Y_CONTROL 0x1bed
#define mmOTG1_OTG_CRC0_WINDOWB_Y_CONTROL_BASE_IDX 2
#define mmOTG1_OTG_CRC0_DATA_RG 0x1bee
#define mmOTG1_OTG_CRC0_DATA_RG_BASE_IDX 2
#define mmOTG1_OTG_CRC0_DATA_B 0x1bef
#define mmOTG1_OTG_CRC0_DATA_B_BASE_IDX 2
#define mmOTG1_OTG_CRC1_WINDOWA_X_CONTROL 0x1bf0
#define mmOTG1_OTG_CRC1_WINDOWA_X_CONTROL_BASE_IDX 2
#define mmOTG1_OTG_CRC1_WINDOWA_Y_CONTROL 0x1bf1
#define mmOTG1_OTG_CRC1_WINDOWA_Y_CONTROL_BASE_IDX 2
#define mmOTG1_OTG_CRC1_WINDOWB_X_CONTROL 0x1bf2
#define mmOTG1_OTG_CRC1_WINDOWB_X_CONTROL_BASE_IDX 2
#define mmOTG1_OTG_CRC1_WINDOWB_Y_CONTROL 0x1bf3
#define mmOTG1_OTG_CRC1_WINDOWB_Y_CONTROL_BASE_IDX 2
#define mmOTG1_OTG_CRC1_DATA_RG 0x1bf4
#define mmOTG1_OTG_CRC1_DATA_RG_BASE_IDX 2
#define mmOTG1_OTG_CRC1_DATA_B 0x1bf5
#define mmOTG1_OTG_CRC1_DATA_B_BASE_IDX 2
#define mmOTG1_OTG_CRC2_DATA_RG 0x1bf6
#define mmOTG1_OTG_CRC2_DATA_RG_BASE_IDX 2
#define mmOTG1_OTG_CRC2_DATA_B 0x1bf7
#define mmOTG1_OTG_CRC2_DATA_B_BASE_IDX 2
#define mmOTG1_OTG_CRC3_DATA_RG 0x1bf8
#define mmOTG1_OTG_CRC3_DATA_RG_BASE_IDX 2
#define mmOTG1_OTG_CRC3_DATA_B 0x1bf9
#define mmOTG1_OTG_CRC3_DATA_B_BASE_IDX 2
#define mmOTG1_OTG_CRC_SIG_RED_GREEN_MASK 0x1bfa
#define mmOTG1_OTG_CRC_SIG_RED_GREEN_MASK_BASE_IDX 2
#define mmOTG1_OTG_CRC_SIG_BLUE_CONTROL_MASK 0x1bfb
#define mmOTG1_OTG_CRC_SIG_BLUE_CONTROL_MASK_BASE_IDX 2
#define mmOTG1_OTG_STATIC_SCREEN_CONTROL 0x1c02
#define mmOTG1_OTG_STATIC_SCREEN_CONTROL_BASE_IDX 2
#define mmOTG1_OTG_3D_STRUCTURE_CONTROL 0x1c03
#define mmOTG1_OTG_3D_STRUCTURE_CONTROL_BASE_IDX 2
#define mmOTG1_OTG_GSL_VSYNC_GAP 0x1c04
#define mmOTG1_OTG_GSL_VSYNC_GAP_BASE_IDX 2
#define mmOTG1_OTG_MASTER_UPDATE_MODE 0x1c05
#define mmOTG1_OTG_MASTER_UPDATE_MODE_BASE_IDX 2
#define mmOTG1_OTG_CLOCK_CONTROL 0x1c06
#define mmOTG1_OTG_CLOCK_CONTROL_BASE_IDX 2
#define mmOTG1_OTG_VSTARTUP_PARAM 0x1c07
#define mmOTG1_OTG_VSTARTUP_PARAM_BASE_IDX 2
#define mmOTG1_OTG_VUPDATE_PARAM 0x1c08
#define mmOTG1_OTG_VUPDATE_PARAM_BASE_IDX 2
#define mmOTG1_OTG_VREADY_PARAM 0x1c09
#define mmOTG1_OTG_VREADY_PARAM_BASE_IDX 2
#define mmOTG1_OTG_GLOBAL_SYNC_STATUS 0x1c0a
#define mmOTG1_OTG_GLOBAL_SYNC_STATUS_BASE_IDX 2
#define mmOTG1_OTG_MASTER_UPDATE_LOCK 0x1c0b
#define mmOTG1_OTG_MASTER_UPDATE_LOCK_BASE_IDX 2
#define mmOTG1_OTG_GSL_CONTROL 0x1c0c
#define mmOTG1_OTG_GSL_CONTROL_BASE_IDX 2
#define mmOTG1_OTG_GSL_WINDOW_X 0x1c0d
#define mmOTG1_OTG_GSL_WINDOW_X_BASE_IDX 2
#define mmOTG1_OTG_GSL_WINDOW_Y 0x1c0e
#define mmOTG1_OTG_GSL_WINDOW_Y_BASE_IDX 2
#define mmOTG1_OTG_VUPDATE_KEEPOUT 0x1c0f
#define mmOTG1_OTG_VUPDATE_KEEPOUT_BASE_IDX 2
#define mmOTG1_OTG_GLOBAL_CONTROL0 0x1c10
#define mmOTG1_OTG_GLOBAL_CONTROL0_BASE_IDX 2
#define mmOTG1_OTG_GLOBAL_CONTROL1 0x1c11
#define mmOTG1_OTG_GLOBAL_CONTROL1_BASE_IDX 2
#define mmOTG1_OTG_GLOBAL_CONTROL2 0x1c12
#define mmOTG1_OTG_GLOBAL_CONTROL2_BASE_IDX 2
#define mmOTG1_OTG_GLOBAL_CONTROL3 0x1c13
#define mmOTG1_OTG_GLOBAL_CONTROL3_BASE_IDX 2
#define mmOTG1_OTG_GLOBAL_CONTROL4 0x1c14
#define mmOTG1_OTG_GLOBAL_CONTROL4_BASE_IDX 2
#define mmOTG1_OTG_TRIG_MANUAL_CONTROL 0x1c15
#define mmOTG1_OTG_TRIG_MANUAL_CONTROL_BASE_IDX 2
#define mmOTG1_OTG_MANUAL_FLOW_CONTROL 0x1c16
#define mmOTG1_OTG_MANUAL_FLOW_CONTROL_BASE_IDX 2
#define mmOTG1_OTG_DRR_TIMING_INT_STATUS 0x1c17
#define mmOTG1_OTG_DRR_TIMING_INT_STATUS_BASE_IDX 2
#define mmOTG1_OTG_DRR_V_TOTAL_REACH_RANGE 0x1c18
#define mmOTG1_OTG_DRR_V_TOTAL_REACH_RANGE_BASE_IDX 2
#define mmOTG1_OTG_DRR_V_TOTAL_CHANGE 0x1c19
#define mmOTG1_OTG_DRR_V_TOTAL_CHANGE_BASE_IDX 2
#define mmOTG1_OTG_DRR_TRIGGER_WINDOW 0x1c1a
#define mmOTG1_OTG_DRR_TRIGGER_WINDOW_BASE_IDX 2
#define mmOTG1_OTG_DRR_CONTROL 0x1c1b
#define mmOTG1_OTG_DRR_CONTROL_BASE_IDX 2
#define mmOTG1_OTG_M_CONST_DTO0 0x1c1c
#define mmOTG1_OTG_M_CONST_DTO0_BASE_IDX 2
#define mmOTG1_OTG_M_CONST_DTO1 0x1c1d
#define mmOTG1_OTG_M_CONST_DTO1_BASE_IDX 2
#define mmOTG1_OTG_REQUEST_CONTROL 0x1c1e
#define mmOTG1_OTG_REQUEST_CONTROL_BASE_IDX 2
#define mmOTG1_OTG_DSC_START_POSITION 0x1c1f
#define mmOTG1_OTG_DSC_START_POSITION_BASE_IDX 2
#define mmOTG1_OTG_PIPE_UPDATE_STATUS 0x1c20
#define mmOTG1_OTG_PIPE_UPDATE_STATUS_BASE_IDX 2
#define mmOTG1_OTG_SPARE_REGISTER 0x1c22
#define mmOTG1_OTG_SPARE_REGISTER_BASE_IDX 2
// addressBlock: dce_dc_optc_otg2_dispdec
// base address: 0x400
#define mmOTG2_OTG_H_TOTAL 0x1c2a
#define mmOTG2_OTG_H_TOTAL_BASE_IDX 2
#define mmOTG2_OTG_H_BLANK_START_END 0x1c2b
#define mmOTG2_OTG_H_BLANK_START_END_BASE_IDX 2
#define mmOTG2_OTG_H_SYNC_A 0x1c2c
#define mmOTG2_OTG_H_SYNC_A_BASE_IDX 2
#define mmOTG2_OTG_H_SYNC_A_CNTL 0x1c2d
#define mmOTG2_OTG_H_SYNC_A_CNTL_BASE_IDX 2
#define mmOTG2_OTG_H_TIMING_CNTL 0x1c2e
#define mmOTG2_OTG_H_TIMING_CNTL_BASE_IDX 2
#define mmOTG2_OTG_V_TOTAL 0x1c2f
#define mmOTG2_OTG_V_TOTAL_BASE_IDX 2
#define mmOTG2_OTG_V_TOTAL_MIN 0x1c30
#define mmOTG2_OTG_V_TOTAL_MIN_BASE_IDX 2
#define mmOTG2_OTG_V_TOTAL_MAX 0x1c31
#define mmOTG2_OTG_V_TOTAL_MAX_BASE_IDX 2
#define mmOTG2_OTG_V_TOTAL_MID 0x1c32
#define mmOTG2_OTG_V_TOTAL_MID_BASE_IDX 2
#define mmOTG2_OTG_V_TOTAL_CONTROL 0x1c33
#define mmOTG2_OTG_V_TOTAL_CONTROL_BASE_IDX 2
#define mmOTG2_OTG_V_TOTAL_INT_STATUS 0x1c34
#define mmOTG2_OTG_V_TOTAL_INT_STATUS_BASE_IDX 2
#define mmOTG2_OTG_VSYNC_NOM_INT_STATUS 0x1c35
#define mmOTG2_OTG_VSYNC_NOM_INT_STATUS_BASE_IDX 2
#define mmOTG2_OTG_V_BLANK_START_END 0x1c36
#define mmOTG2_OTG_V_BLANK_START_END_BASE_IDX 2
#define mmOTG2_OTG_V_SYNC_A 0x1c37
#define mmOTG2_OTG_V_SYNC_A_BASE_IDX 2
#define mmOTG2_OTG_V_SYNC_A_CNTL 0x1c38
#define mmOTG2_OTG_V_SYNC_A_CNTL_BASE_IDX 2
#define mmOTG2_OTG_TRIGA_CNTL 0x1c39
#define mmOTG2_OTG_TRIGA_CNTL_BASE_IDX 2
#define mmOTG2_OTG_TRIGA_MANUAL_TRIG 0x1c3a
#define mmOTG2_OTG_TRIGA_MANUAL_TRIG_BASE_IDX 2
#define mmOTG2_OTG_TRIGB_CNTL 0x1c3b
#define mmOTG2_OTG_TRIGB_CNTL_BASE_IDX 2
#define mmOTG2_OTG_TRIGB_MANUAL_TRIG 0x1c3c
#define mmOTG2_OTG_TRIGB_MANUAL_TRIG_BASE_IDX 2
#define mmOTG2_OTG_FORCE_COUNT_NOW_CNTL 0x1c3d
#define mmOTG2_OTG_FORCE_COUNT_NOW_CNTL_BASE_IDX 2
#define mmOTG2_OTG_FLOW_CONTROL 0x1c3e
#define mmOTG2_OTG_FLOW_CONTROL_BASE_IDX 2
#define mmOTG2_OTG_STEREO_FORCE_NEXT_EYE 0x1c3f
#define mmOTG2_OTG_STEREO_FORCE_NEXT_EYE_BASE_IDX 2
#define mmOTG2_OTG_CONTROL 0x1c41
#define mmOTG2_OTG_CONTROL_BASE_IDX 2
#define mmOTG2_OTG_INTERLACE_CONTROL 0x1c44
#define mmOTG2_OTG_INTERLACE_CONTROL_BASE_IDX 2
#define mmOTG2_OTG_INTERLACE_STATUS 0x1c45
#define mmOTG2_OTG_INTERLACE_STATUS_BASE_IDX 2
#define mmOTG2_OTG_PIXEL_DATA_READBACK0 0x1c47
#define mmOTG2_OTG_PIXEL_DATA_READBACK0_BASE_IDX 2
#define mmOTG2_OTG_PIXEL_DATA_READBACK1 0x1c48
#define mmOTG2_OTG_PIXEL_DATA_READBACK1_BASE_IDX 2
#define mmOTG2_OTG_STATUS 0x1c49
#define mmOTG2_OTG_STATUS_BASE_IDX 2
#define mmOTG2_OTG_STATUS_POSITION 0x1c4a
#define mmOTG2_OTG_STATUS_POSITION_BASE_IDX 2
#define mmOTG2_OTG_NOM_VERT_POSITION 0x1c4b
#define mmOTG2_OTG_NOM_VERT_POSITION_BASE_IDX 2
#define mmOTG2_OTG_STATUS_FRAME_COUNT 0x1c4c
#define mmOTG2_OTG_STATUS_FRAME_COUNT_BASE_IDX 2
#define mmOTG2_OTG_STATUS_VF_COUNT 0x1c4d
#define mmOTG2_OTG_STATUS_VF_COUNT_BASE_IDX 2
#define mmOTG2_OTG_STATUS_HV_COUNT 0x1c4e
#define mmOTG2_OTG_STATUS_HV_COUNT_BASE_IDX 2
#define mmOTG2_OTG_COUNT_CONTROL 0x1c4f
#define mmOTG2_OTG_COUNT_CONTROL_BASE_IDX 2
#define mmOTG2_OTG_COUNT_RESET 0x1c50
#define mmOTG2_OTG_COUNT_RESET_BASE_IDX 2
#define mmOTG2_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE 0x1c51
#define mmOTG2_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE_BASE_IDX 2
#define mmOTG2_OTG_VERT_SYNC_CONTROL 0x1c52
#define mmOTG2_OTG_VERT_SYNC_CONTROL_BASE_IDX 2
#define mmOTG2_OTG_STEREO_STATUS 0x1c53
#define mmOTG2_OTG_STEREO_STATUS_BASE_IDX 2
#define mmOTG2_OTG_STEREO_CONTROL 0x1c54
#define mmOTG2_OTG_STEREO_CONTROL_BASE_IDX 2
#define mmOTG2_OTG_SNAPSHOT_STATUS 0x1c55
#define mmOTG2_OTG_SNAPSHOT_STATUS_BASE_IDX 2
#define mmOTG2_OTG_SNAPSHOT_CONTROL 0x1c56
#define mmOTG2_OTG_SNAPSHOT_CONTROL_BASE_IDX 2
#define mmOTG2_OTG_SNAPSHOT_POSITION 0x1c57
#define mmOTG2_OTG_SNAPSHOT_POSITION_BASE_IDX 2
#define mmOTG2_OTG_SNAPSHOT_FRAME 0x1c58
#define mmOTG2_OTG_SNAPSHOT_FRAME_BASE_IDX 2
#define mmOTG2_OTG_INTERRUPT_CONTROL 0x1c59
#define mmOTG2_OTG_INTERRUPT_CONTROL_BASE_IDX 2
#define mmOTG2_OTG_UPDATE_LOCK 0x1c5a
#define mmOTG2_OTG_UPDATE_LOCK_BASE_IDX 2
#define mmOTG2_OTG_DOUBLE_BUFFER_CONTROL 0x1c5b
#define mmOTG2_OTG_DOUBLE_BUFFER_CONTROL_BASE_IDX 2
#define mmOTG2_OTG_MASTER_EN 0x1c5c
#define mmOTG2_OTG_MASTER_EN_BASE_IDX 2
#define mmOTG2_OTG_BLANK_DATA_COLOR 0x1c5e
#define mmOTG2_OTG_BLANK_DATA_COLOR_BASE_IDX 2
#define mmOTG2_OTG_BLANK_DATA_COLOR_EXT 0x1c5f
#define mmOTG2_OTG_BLANK_DATA_COLOR_EXT_BASE_IDX 2
#define mmOTG2_OTG_VERTICAL_INTERRUPT0_POSITION 0x1c62
#define mmOTG2_OTG_VERTICAL_INTERRUPT0_POSITION_BASE_IDX 2
#define mmOTG2_OTG_VERTICAL_INTERRUPT0_CONTROL 0x1c63
#define mmOTG2_OTG_VERTICAL_INTERRUPT0_CONTROL_BASE_IDX 2
#define mmOTG2_OTG_VERTICAL_INTERRUPT1_POSITION 0x1c64
#define mmOTG2_OTG_VERTICAL_INTERRUPT1_POSITION_BASE_IDX 2
#define mmOTG2_OTG_VERTICAL_INTERRUPT1_CONTROL 0x1c65
#define mmOTG2_OTG_VERTICAL_INTERRUPT1_CONTROL_BASE_IDX 2
#define mmOTG2_OTG_VERTICAL_INTERRUPT2_POSITION 0x1c66
#define mmOTG2_OTG_VERTICAL_INTERRUPT2_POSITION_BASE_IDX 2
#define mmOTG2_OTG_VERTICAL_INTERRUPT2_CONTROL 0x1c67
#define mmOTG2_OTG_VERTICAL_INTERRUPT2_CONTROL_BASE_IDX 2
#define mmOTG2_OTG_CRC_CNTL 0x1c68
#define mmOTG2_OTG_CRC_CNTL_BASE_IDX 2
#define mmOTG2_OTG_CRC_CNTL2 0x1c69
#define mmOTG2_OTG_CRC_CNTL2_BASE_IDX 2
#define mmOTG2_OTG_CRC0_WINDOWA_X_CONTROL 0x1c6a
#define mmOTG2_OTG_CRC0_WINDOWA_X_CONTROL_BASE_IDX 2
#define mmOTG2_OTG_CRC0_WINDOWA_Y_CONTROL 0x1c6b
#define mmOTG2_OTG_CRC0_WINDOWA_Y_CONTROL_BASE_IDX 2
#define mmOTG2_OTG_CRC0_WINDOWB_X_CONTROL 0x1c6c
#define mmOTG2_OTG_CRC0_WINDOWB_X_CONTROL_BASE_IDX 2
#define mmOTG2_OTG_CRC0_WINDOWB_Y_CONTROL 0x1c6d
#define mmOTG2_OTG_CRC0_WINDOWB_Y_CONTROL_BASE_IDX 2
#define mmOTG2_OTG_CRC0_DATA_RG 0x1c6e
#define mmOTG2_OTG_CRC0_DATA_RG_BASE_IDX 2
#define mmOTG2_OTG_CRC0_DATA_B 0x1c6f
#define mmOTG2_OTG_CRC0_DATA_B_BASE_IDX 2
#define mmOTG2_OTG_CRC1_WINDOWA_X_CONTROL 0x1c70
#define mmOTG2_OTG_CRC1_WINDOWA_X_CONTROL_BASE_IDX 2
#define mmOTG2_OTG_CRC1_WINDOWA_Y_CONTROL 0x1c71
#define mmOTG2_OTG_CRC1_WINDOWA_Y_CONTROL_BASE_IDX 2
#define mmOTG2_OTG_CRC1_WINDOWB_X_CONTROL 0x1c72
#define mmOTG2_OTG_CRC1_WINDOWB_X_CONTROL_BASE_IDX 2
#define mmOTG2_OTG_CRC1_WINDOWB_Y_CONTROL 0x1c73
#define mmOTG2_OTG_CRC1_WINDOWB_Y_CONTROL_BASE_IDX 2
#define mmOTG2_OTG_CRC1_DATA_RG 0x1c74
#define mmOTG2_OTG_CRC1_DATA_RG_BASE_IDX 2
#define mmOTG2_OTG_CRC1_DATA_B 0x1c75
#define mmOTG2_OTG_CRC1_DATA_B_BASE_IDX 2
#define mmOTG2_OTG_CRC2_DATA_RG 0x1c76
#define mmOTG2_OTG_CRC2_DATA_RG_BASE_IDX 2
#define mmOTG2_OTG_CRC2_DATA_B 0x1c77
#define mmOTG2_OTG_CRC2_DATA_B_BASE_IDX 2
#define mmOTG2_OTG_CRC3_DATA_RG 0x1c78
#define mmOTG2_OTG_CRC3_DATA_RG_BASE_IDX 2
#define mmOTG2_OTG_CRC3_DATA_B 0x1c79
#define mmOTG2_OTG_CRC3_DATA_B_BASE_IDX 2
#define mmOTG2_OTG_CRC_SIG_RED_GREEN_MASK 0x1c7a
#define mmOTG2_OTG_CRC_SIG_RED_GREEN_MASK_BASE_IDX 2
#define mmOTG2_OTG_CRC_SIG_BLUE_CONTROL_MASK 0x1c7b
#define mmOTG2_OTG_CRC_SIG_BLUE_CONTROL_MASK_BASE_IDX 2
#define mmOTG2_OTG_STATIC_SCREEN_CONTROL 0x1c82
#define mmOTG2_OTG_STATIC_SCREEN_CONTROL_BASE_IDX 2
#define mmOTG2_OTG_3D_STRUCTURE_CONTROL 0x1c83
#define mmOTG2_OTG_3D_STRUCTURE_CONTROL_BASE_IDX 2
#define mmOTG2_OTG_GSL_VSYNC_GAP 0x1c84
#define mmOTG2_OTG_GSL_VSYNC_GAP_BASE_IDX 2
#define mmOTG2_OTG_MASTER_UPDATE_MODE 0x1c85
#define mmOTG2_OTG_MASTER_UPDATE_MODE_BASE_IDX 2
#define mmOTG2_OTG_CLOCK_CONTROL 0x1c86
#define mmOTG2_OTG_CLOCK_CONTROL_BASE_IDX 2
#define mmOTG2_OTG_VSTARTUP_PARAM 0x1c87
#define mmOTG2_OTG_VSTARTUP_PARAM_BASE_IDX 2
#define mmOTG2_OTG_VUPDATE_PARAM 0x1c88
#define mmOTG2_OTG_VUPDATE_PARAM_BASE_IDX 2
#define mmOTG2_OTG_VREADY_PARAM 0x1c89
#define mmOTG2_OTG_VREADY_PARAM_BASE_IDX 2
#define mmOTG2_OTG_GLOBAL_SYNC_STATUS 0x1c8a
#define mmOTG2_OTG_GLOBAL_SYNC_STATUS_BASE_IDX 2
#define mmOTG2_OTG_MASTER_UPDATE_LOCK 0x1c8b
#define mmOTG2_OTG_MASTER_UPDATE_LOCK_BASE_IDX 2
#define mmOTG2_OTG_GSL_CONTROL 0x1c8c
#define mmOTG2_OTG_GSL_CONTROL_BASE_IDX 2
#define mmOTG2_OTG_GSL_WINDOW_X 0x1c8d
#define mmOTG2_OTG_GSL_WINDOW_X_BASE_IDX 2
#define mmOTG2_OTG_GSL_WINDOW_Y 0x1c8e
#define mmOTG2_OTG_GSL_WINDOW_Y_BASE_IDX 2
#define mmOTG2_OTG_VUPDATE_KEEPOUT 0x1c8f
#define mmOTG2_OTG_VUPDATE_KEEPOUT_BASE_IDX 2
#define mmOTG2_OTG_GLOBAL_CONTROL0 0x1c90
#define mmOTG2_OTG_GLOBAL_CONTROL0_BASE_IDX 2
#define mmOTG2_OTG_GLOBAL_CONTROL1 0x1c91
#define mmOTG2_OTG_GLOBAL_CONTROL1_BASE_IDX 2
#define mmOTG2_OTG_GLOBAL_CONTROL2 0x1c92
#define mmOTG2_OTG_GLOBAL_CONTROL2_BASE_IDX 2
#define mmOTG2_OTG_GLOBAL_CONTROL3 0x1c93
#define mmOTG2_OTG_GLOBAL_CONTROL3_BASE_IDX 2
#define mmOTG2_OTG_GLOBAL_CONTROL4 0x1c94
#define mmOTG2_OTG_GLOBAL_CONTROL4_BASE_IDX 2
#define mmOTG2_OTG_TRIG_MANUAL_CONTROL 0x1c95
#define mmOTG2_OTG_TRIG_MANUAL_CONTROL_BASE_IDX 2
#define mmOTG2_OTG_MANUAL_FLOW_CONTROL 0x1c96
#define mmOTG2_OTG_MANUAL_FLOW_CONTROL_BASE_IDX 2
#define mmOTG2_OTG_DRR_TIMING_INT_STATUS 0x1c97
#define mmOTG2_OTG_DRR_TIMING_INT_STATUS_BASE_IDX 2
#define mmOTG2_OTG_DRR_V_TOTAL_REACH_RANGE 0x1c98
#define mmOTG2_OTG_DRR_V_TOTAL_REACH_RANGE_BASE_IDX 2
#define mmOTG2_OTG_DRR_V_TOTAL_CHANGE 0x1c99
#define mmOTG2_OTG_DRR_V_TOTAL_CHANGE_BASE_IDX 2
#define mmOTG2_OTG_DRR_TRIGGER_WINDOW 0x1c9a
#define mmOTG2_OTG_DRR_TRIGGER_WINDOW_BASE_IDX 2
#define mmOTG2_OTG_DRR_CONTROL 0x1c9b
#define mmOTG2_OTG_DRR_CONTROL_BASE_IDX 2
#define mmOTG2_OTG_M_CONST_DTO0 0x1c9c
#define mmOTG2_OTG_M_CONST_DTO0_BASE_IDX 2
#define mmOTG2_OTG_M_CONST_DTO1 0x1c9d
#define mmOTG2_OTG_M_CONST_DTO1_BASE_IDX 2
#define mmOTG2_OTG_REQUEST_CONTROL 0x1c9e
#define mmOTG2_OTG_REQUEST_CONTROL_BASE_IDX 2
#define mmOTG2_OTG_DSC_START_POSITION 0x1c9f
#define mmOTG2_OTG_DSC_START_POSITION_BASE_IDX 2
#define mmOTG2_OTG_PIPE_UPDATE_STATUS 0x1ca0
#define mmOTG2_OTG_PIPE_UPDATE_STATUS_BASE_IDX 2
#define mmOTG2_OTG_SPARE_REGISTER 0x1ca2
#define mmOTG2_OTG_SPARE_REGISTER_BASE_IDX 2
// addressBlock: dce_dc_optc_otg3_dispdec
// base address: 0x600
#define mmOTG3_OTG_H_TOTAL 0x1caa
#define mmOTG3_OTG_H_TOTAL_BASE_IDX 2
#define mmOTG3_OTG_H_BLANK_START_END 0x1cab
#define mmOTG3_OTG_H_BLANK_START_END_BASE_IDX 2
#define mmOTG3_OTG_H_SYNC_A 0x1cac
#define mmOTG3_OTG_H_SYNC_A_BASE_IDX 2
#define mmOTG3_OTG_H_SYNC_A_CNTL 0x1cad
#define mmOTG3_OTG_H_SYNC_A_CNTL_BASE_IDX 2
#define mmOTG3_OTG_H_TIMING_CNTL 0x1cae
#define mmOTG3_OTG_H_TIMING_CNTL_BASE_IDX 2
#define mmOTG3_OTG_V_TOTAL 0x1caf
#define mmOTG3_OTG_V_TOTAL_BASE_IDX 2
#define mmOTG3_OTG_V_TOTAL_MIN 0x1cb0
#define mmOTG3_OTG_V_TOTAL_MIN_BASE_IDX 2
#define mmOTG3_OTG_V_TOTAL_MAX 0x1cb1
#define mmOTG3_OTG_V_TOTAL_MAX_BASE_IDX 2
#define mmOTG3_OTG_V_TOTAL_MID 0x1cb2
#define mmOTG3_OTG_V_TOTAL_MID_BASE_IDX 2
#define mmOTG3_OTG_V_TOTAL_CONTROL 0x1cb3
#define mmOTG3_OTG_V_TOTAL_CONTROL_BASE_IDX 2
#define mmOTG3_OTG_V_TOTAL_INT_STATUS 0x1cb4
#define mmOTG3_OTG_V_TOTAL_INT_STATUS_BASE_IDX 2
#define mmOTG3_OTG_VSYNC_NOM_INT_STATUS 0x1cb5
#define mmOTG3_OTG_VSYNC_NOM_INT_STATUS_BASE_IDX 2
#define mmOTG3_OTG_V_BLANK_START_END 0x1cb6
#define mmOTG3_OTG_V_BLANK_START_END_BASE_IDX 2
#define mmOTG3_OTG_V_SYNC_A 0x1cb7
#define mmOTG3_OTG_V_SYNC_A_BASE_IDX 2
#define mmOTG3_OTG_V_SYNC_A_CNTL 0x1cb8
#define mmOTG3_OTG_V_SYNC_A_CNTL_BASE_IDX 2
#define mmOTG3_OTG_TRIGA_CNTL 0x1cb9
#define mmOTG3_OTG_TRIGA_CNTL_BASE_IDX 2
#define mmOTG3_OTG_TRIGA_MANUAL_TRIG 0x1cba
#define mmOTG3_OTG_TRIGA_MANUAL_TRIG_BASE_IDX 2
#define mmOTG3_OTG_TRIGB_CNTL 0x1cbb
#define mmOTG3_OTG_TRIGB_CNTL_BASE_IDX 2
#define mmOTG3_OTG_TRIGB_MANUAL_TRIG 0x1cbc
#define mmOTG3_OTG_TRIGB_MANUAL_TRIG_BASE_IDX 2
#define mmOTG3_OTG_FORCE_COUNT_NOW_CNTL 0x1cbd
#define mmOTG3_OTG_FORCE_COUNT_NOW_CNTL_BASE_IDX 2
#define mmOTG3_OTG_FLOW_CONTROL 0x1cbe
#define mmOTG3_OTG_FLOW_CONTROL_BASE_IDX 2
#define mmOTG3_OTG_STEREO_FORCE_NEXT_EYE 0x1cbf
#define mmOTG3_OTG_STEREO_FORCE_NEXT_EYE_BASE_IDX 2
#define mmOTG3_OTG_CONTROL 0x1cc1
#define mmOTG3_OTG_CONTROL_BASE_IDX 2
#define mmOTG3_OTG_INTERLACE_CONTROL 0x1cc4
#define mmOTG3_OTG_INTERLACE_CONTROL_BASE_IDX 2
#define mmOTG3_OTG_INTERLACE_STATUS 0x1cc5
#define mmOTG3_OTG_INTERLACE_STATUS_BASE_IDX 2
#define mmOTG3_OTG_PIXEL_DATA_READBACK0 0x1cc7
#define mmOTG3_OTG_PIXEL_DATA_READBACK0_BASE_IDX 2
#define mmOTG3_OTG_PIXEL_DATA_READBACK1 0x1cc8
#define mmOTG3_OTG_PIXEL_DATA_READBACK1_BASE_IDX 2
#define mmOTG3_OTG_STATUS 0x1cc9
#define mmOTG3_OTG_STATUS_BASE_IDX 2
#define mmOTG3_OTG_STATUS_POSITION 0x1cca
#define mmOTG3_OTG_STATUS_POSITION_BASE_IDX 2
#define mmOTG3_OTG_NOM_VERT_POSITION 0x1ccb
#define mmOTG3_OTG_NOM_VERT_POSITION_BASE_IDX 2
#define mmOTG3_OTG_STATUS_FRAME_COUNT 0x1ccc
#define mmOTG3_OTG_STATUS_FRAME_COUNT_BASE_IDX 2
#define mmOTG3_OTG_STATUS_VF_COUNT 0x1ccd
#define mmOTG3_OTG_STATUS_VF_COUNT_BASE_IDX 2
#define mmOTG3_OTG_STATUS_HV_COUNT 0x1cce
#define mmOTG3_OTG_STATUS_HV_COUNT_BASE_IDX 2
#define mmOTG3_OTG_COUNT_CONTROL 0x1ccf
#define mmOTG3_OTG_COUNT_CONTROL_BASE_IDX 2
#define mmOTG3_OTG_COUNT_RESET 0x1cd0
#define mmOTG3_OTG_COUNT_RESET_BASE_IDX 2
#define mmOTG3_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE 0x1cd1
#define mmOTG3_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE_BASE_IDX 2
#define mmOTG3_OTG_VERT_SYNC_CONTROL 0x1cd2
#define mmOTG3_OTG_VERT_SYNC_CONTROL_BASE_IDX 2
#define mmOTG3_OTG_STEREO_STATUS 0x1cd3
#define mmOTG3_OTG_STEREO_STATUS_BASE_IDX 2
#define mmOTG3_OTG_STEREO_CONTROL 0x1cd4
#define mmOTG3_OTG_STEREO_CONTROL_BASE_IDX 2
#define mmOTG3_OTG_SNAPSHOT_STATUS 0x1cd5
#define mmOTG3_OTG_SNAPSHOT_STATUS_BASE_IDX 2
#define mmOTG3_OTG_SNAPSHOT_CONTROL 0x1cd6
#define mmOTG3_OTG_SNAPSHOT_CONTROL_BASE_IDX 2
#define mmOTG3_OTG_SNAPSHOT_POSITION 0x1cd7
#define mmOTG3_OTG_SNAPSHOT_POSITION_BASE_IDX 2
#define mmOTG3_OTG_SNAPSHOT_FRAME 0x1cd8
#define mmOTG3_OTG_SNAPSHOT_FRAME_BASE_IDX 2
#define mmOTG3_OTG_INTERRUPT_CONTROL 0x1cd9
#define mmOTG3_OTG_INTERRUPT_CONTROL_BASE_IDX 2
#define mmOTG3_OTG_UPDATE_LOCK 0x1cda
#define mmOTG3_OTG_UPDATE_LOCK_BASE_IDX 2
#define mmOTG3_OTG_DOUBLE_BUFFER_CONTROL 0x1cdb
#define mmOTG3_OTG_DOUBLE_BUFFER_CONTROL_BASE_IDX 2
#define mmOTG3_OTG_MASTER_EN 0x1cdc
#define mmOTG3_OTG_MASTER_EN_BASE_IDX 2
#define mmOTG3_OTG_BLANK_DATA_COLOR 0x1cde
#define mmOTG3_OTG_BLANK_DATA_COLOR_BASE_IDX 2
#define mmOTG3_OTG_BLANK_DATA_COLOR_EXT 0x1cdf
#define mmOTG3_OTG_BLANK_DATA_COLOR_EXT_BASE_IDX 2
#define mmOTG3_OTG_VERTICAL_INTERRUPT0_POSITION 0x1ce2
#define mmOTG3_OTG_VERTICAL_INTERRUPT0_POSITION_BASE_IDX 2
#define mmOTG3_OTG_VERTICAL_INTERRUPT0_CONTROL 0x1ce3
#define mmOTG3_OTG_VERTICAL_INTERRUPT0_CONTROL_BASE_IDX 2
#define mmOTG3_OTG_VERTICAL_INTERRUPT1_POSITION 0x1ce4
#define mmOTG3_OTG_VERTICAL_INTERRUPT1_POSITION_BASE_IDX 2
#define mmOTG3_OTG_VERTICAL_INTERRUPT1_CONTROL 0x1ce5
#define mmOTG3_OTG_VERTICAL_INTERRUPT1_CONTROL_BASE_IDX 2
#define mmOTG3_OTG_VERTICAL_INTERRUPT2_POSITION 0x1ce6
#define mmOTG3_OTG_VERTICAL_INTERRUPT2_POSITION_BASE_IDX 2
#define mmOTG3_OTG_VERTICAL_INTERRUPT2_CONTROL 0x1ce7
#define mmOTG3_OTG_VERTICAL_INTERRUPT2_CONTROL_BASE_IDX 2
#define mmOTG3_OTG_CRC_CNTL 0x1ce8
#define mmOTG3_OTG_CRC_CNTL_BASE_IDX 2
#define mmOTG3_OTG_CRC_CNTL2 0x1ce9
#define mmOTG3_OTG_CRC_CNTL2_BASE_IDX 2
#define mmOTG3_OTG_CRC0_WINDOWA_X_CONTROL 0x1cea
#define mmOTG3_OTG_CRC0_WINDOWA_X_CONTROL_BASE_IDX 2
#define mmOTG3_OTG_CRC0_WINDOWA_Y_CONTROL 0x1ceb
#define mmOTG3_OTG_CRC0_WINDOWA_Y_CONTROL_BASE_IDX 2
#define mmOTG3_OTG_CRC0_WINDOWB_X_CONTROL 0x1cec
#define mmOTG3_OTG_CRC0_WINDOWB_X_CONTROL_BASE_IDX 2
#define mmOTG3_OTG_CRC0_WINDOWB_Y_CONTROL 0x1ced
#define mmOTG3_OTG_CRC0_WINDOWB_Y_CONTROL_BASE_IDX 2
#define mmOTG3_OTG_CRC0_DATA_RG 0x1cee
#define mmOTG3_OTG_CRC0_DATA_RG_BASE_IDX 2
#define mmOTG3_OTG_CRC0_DATA_B 0x1cef
#define mmOTG3_OTG_CRC0_DATA_B_BASE_IDX 2
#define mmOTG3_OTG_CRC1_WINDOWA_X_CONTROL 0x1cf0
#define mmOTG3_OTG_CRC1_WINDOWA_X_CONTROL_BASE_IDX 2
#define mmOTG3_OTG_CRC1_WINDOWA_Y_CONTROL 0x1cf1
#define mmOTG3_OTG_CRC1_WINDOWA_Y_CONTROL_BASE_IDX 2
#define mmOTG3_OTG_CRC1_WINDOWB_X_CONTROL 0x1cf2
#define mmOTG3_OTG_CRC1_WINDOWB_X_CONTROL_BASE_IDX 2
#define mmOTG3_OTG_CRC1_WINDOWB_Y_CONTROL 0x1cf3
#define mmOTG3_OTG_CRC1_WINDOWB_Y_CONTROL_BASE_IDX 2
#define mmOTG3_OTG_CRC1_DATA_RG 0x1cf4
#define mmOTG3_OTG_CRC1_DATA_RG_BASE_IDX 2
#define mmOTG3_OTG_CRC1_DATA_B 0x1cf5
#define mmOTG3_OTG_CRC1_DATA_B_BASE_IDX 2
#define mmOTG3_OTG_CRC2_DATA_RG 0x1cf6
#define mmOTG3_OTG_CRC2_DATA_RG_BASE_IDX 2
#define mmOTG3_OTG_CRC2_DATA_B 0x1cf7
#define mmOTG3_OTG_CRC2_DATA_B_BASE_IDX 2
#define mmOTG3_OTG_CRC3_DATA_RG 0x1cf8
#define mmOTG3_OTG_CRC3_DATA_RG_BASE_IDX 2
#define mmOTG3_OTG_CRC3_DATA_B 0x1cf9
#define mmOTG3_OTG_CRC3_DATA_B_BASE_IDX 2
#define mmOTG3_OTG_CRC_SIG_RED_GREEN_MASK 0x1cfa
#define mmOTG3_OTG_CRC_SIG_RED_GREEN_MASK_BASE_IDX 2
#define mmOTG3_OTG_CRC_SIG_BLUE_CONTROL_MASK 0x1cfb
#define mmOTG3_OTG_CRC_SIG_BLUE_CONTROL_MASK_BASE_IDX 2
#define mmOTG3_OTG_STATIC_SCREEN_CONTROL 0x1d02
#define mmOTG3_OTG_STATIC_SCREEN_CONTROL_BASE_IDX 2
#define mmOTG3_OTG_3D_STRUCTURE_CONTROL 0x1d03
#define mmOTG3_OTG_3D_STRUCTURE_CONTROL_BASE_IDX 2
#define mmOTG3_OTG_GSL_VSYNC_GAP 0x1d04
#define mmOTG3_OTG_GSL_VSYNC_GAP_BASE_IDX 2
#define mmOTG3_OTG_MASTER_UPDATE_MODE 0x1d05
#define mmOTG3_OTG_MASTER_UPDATE_MODE_BASE_IDX 2
#define mmOTG3_OTG_CLOCK_CONTROL 0x1d06
#define mmOTG3_OTG_CLOCK_CONTROL_BASE_IDX 2
#define mmOTG3_OTG_VSTARTUP_PARAM 0x1d07
#define mmOTG3_OTG_VSTARTUP_PARAM_BASE_IDX 2
#define mmOTG3_OTG_VUPDATE_PARAM 0x1d08
#define mmOTG3_OTG_VUPDATE_PARAM_BASE_IDX 2
#define mmOTG3_OTG_VREADY_PARAM 0x1d09
#define mmOTG3_OTG_VREADY_PARAM_BASE_IDX 2
#define mmOTG3_OTG_GLOBAL_SYNC_STATUS 0x1d0a
#define mmOTG3_OTG_GLOBAL_SYNC_STATUS_BASE_IDX 2
#define mmOTG3_OTG_MASTER_UPDATE_LOCK 0x1d0b
#define mmOTG3_OTG_MASTER_UPDATE_LOCK_BASE_IDX 2
#define mmOTG3_OTG_GSL_CONTROL 0x1d0c
#define mmOTG3_OTG_GSL_CONTROL_BASE_IDX 2
#define mmOTG3_OTG_GSL_WINDOW_X 0x1d0d
#define mmOTG3_OTG_GSL_WINDOW_X_BASE_IDX 2
#define mmOTG3_OTG_GSL_WINDOW_Y 0x1d0e
#define mmOTG3_OTG_GSL_WINDOW_Y_BASE_IDX 2
#define mmOTG3_OTG_VUPDATE_KEEPOUT 0x1d0f
#define mmOTG3_OTG_VUPDATE_KEEPOUT_BASE_IDX 2
#define mmOTG3_OTG_GLOBAL_CONTROL0 0x1d10
#define mmOTG3_OTG_GLOBAL_CONTROL0_BASE_IDX 2
#define mmOTG3_OTG_GLOBAL_CONTROL1 0x1d11
#define mmOTG3_OTG_GLOBAL_CONTROL1_BASE_IDX 2
#define mmOTG3_OTG_GLOBAL_CONTROL2 0x1d12
#define mmOTG3_OTG_GLOBAL_CONTROL2_BASE_IDX 2
#define mmOTG3_OTG_GLOBAL_CONTROL3 0x1d13
#define mmOTG3_OTG_GLOBAL_CONTROL3_BASE_IDX 2
#define mmOTG3_OTG_GLOBAL_CONTROL4 0x1d14
#define mmOTG3_OTG_GLOBAL_CONTROL4_BASE_IDX 2
#define mmOTG3_OTG_TRIG_MANUAL_CONTROL 0x1d15
#define mmOTG3_OTG_TRIG_MANUAL_CONTROL_BASE_IDX 2
#define mmOTG3_OTG_MANUAL_FLOW_CONTROL 0x1d16
#define mmOTG3_OTG_MANUAL_FLOW_CONTROL_BASE_IDX 2
#define mmOTG3_OTG_DRR_TIMING_INT_STATUS 0x1d17
#define mmOTG3_OTG_DRR_TIMING_INT_STATUS_BASE_IDX 2
#define mmOTG3_OTG_DRR_V_TOTAL_REACH_RANGE 0x1d18
#define mmOTG3_OTG_DRR_V_TOTAL_REACH_RANGE_BASE_IDX 2
#define mmOTG3_OTG_DRR_V_TOTAL_CHANGE 0x1d19
#define mmOTG3_OTG_DRR_V_TOTAL_CHANGE_BASE_IDX 2
#define mmOTG3_OTG_DRR_TRIGGER_WINDOW 0x1d1a
#define mmOTG3_OTG_DRR_TRIGGER_WINDOW_BASE_IDX 2
#define mmOTG3_OTG_DRR_CONTROL 0x1d1b
#define mmOTG3_OTG_DRR_CONTROL_BASE_IDX 2
#define mmOTG3_OTG_M_CONST_DTO0 0x1d1c
#define mmOTG3_OTG_M_CONST_DTO0_BASE_IDX 2
#define mmOTG3_OTG_M_CONST_DTO1 0x1d1d
#define mmOTG3_OTG_M_CONST_DTO1_BASE_IDX 2
#define mmOTG3_OTG_REQUEST_CONTROL 0x1d1e
#define mmOTG3_OTG_REQUEST_CONTROL_BASE_IDX 2
#define mmOTG3_OTG_DSC_START_POSITION 0x1d1f
#define mmOTG3_OTG_DSC_START_POSITION_BASE_IDX 2
#define mmOTG3_OTG_PIPE_UPDATE_STATUS 0x1d20
#define mmOTG3_OTG_PIPE_UPDATE_STATUS_BASE_IDX 2
#define mmOTG3_OTG_SPARE_REGISTER 0x1d22
#define mmOTG3_OTG_SPARE_REGISTER_BASE_IDX 2
// addressBlock: dce_dc_optc_otg4_dispdec
// base address: 0x800
#define mmOTG4_OTG_H_TOTAL 0x1d2a
#define mmOTG4_OTG_H_TOTAL_BASE_IDX 2
#define mmOTG4_OTG_H_BLANK_START_END 0x1d2b
#define mmOTG4_OTG_H_BLANK_START_END_BASE_IDX 2
#define mmOTG4_OTG_H_SYNC_A 0x1d2c
#define mmOTG4_OTG_H_SYNC_A_BASE_IDX 2
#define mmOTG4_OTG_H_SYNC_A_CNTL 0x1d2d
#define mmOTG4_OTG_H_SYNC_A_CNTL_BASE_IDX 2
#define mmOTG4_OTG_H_TIMING_CNTL 0x1d2e
#define mmOTG4_OTG_H_TIMING_CNTL_BASE_IDX 2
#define mmOTG4_OTG_V_TOTAL 0x1d2f
#define mmOTG4_OTG_V_TOTAL_BASE_IDX 2
#define mmOTG4_OTG_V_TOTAL_MIN 0x1d30
#define mmOTG4_OTG_V_TOTAL_MIN_BASE_IDX 2
#define mmOTG4_OTG_V_TOTAL_MAX 0x1d31
#define mmOTG4_OTG_V_TOTAL_MAX_BASE_IDX 2
#define mmOTG4_OTG_V_TOTAL_MID 0x1d32
#define mmOTG4_OTG_V_TOTAL_MID_BASE_IDX 2
#define mmOTG4_OTG_V_TOTAL_CONTROL 0x1d33
#define mmOTG4_OTG_V_TOTAL_CONTROL_BASE_IDX 2
#define mmOTG4_OTG_V_TOTAL_INT_STATUS 0x1d34
#define mmOTG4_OTG_V_TOTAL_INT_STATUS_BASE_IDX 2
#define mmOTG4_OTG_VSYNC_NOM_INT_STATUS 0x1d35
#define mmOTG4_OTG_VSYNC_NOM_INT_STATUS_BASE_IDX 2
#define mmOTG4_OTG_V_BLANK_START_END 0x1d36
#define mmOTG4_OTG_V_BLANK_START_END_BASE_IDX 2
#define mmOTG4_OTG_V_SYNC_A 0x1d37
#define mmOTG4_OTG_V_SYNC_A_BASE_IDX 2
#define mmOTG4_OTG_V_SYNC_A_CNTL 0x1d38
#define mmOTG4_OTG_V_SYNC_A_CNTL_BASE_IDX 2
#define mmOTG4_OTG_TRIGA_CNTL 0x1d39
#define mmOTG4_OTG_TRIGA_CNTL_BASE_IDX 2
#define mmOTG4_OTG_TRIGA_MANUAL_TRIG 0x1d3a
#define mmOTG4_OTG_TRIGA_MANUAL_TRIG_BASE_IDX 2
#define mmOTG4_OTG_TRIGB_CNTL 0x1d3b
#define mmOTG4_OTG_TRIGB_CNTL_BASE_IDX 2
#define mmOTG4_OTG_TRIGB_MANUAL_TRIG 0x1d3c
#define mmOTG4_OTG_TRIGB_MANUAL_TRIG_BASE_IDX 2
#define mmOTG4_OTG_FORCE_COUNT_NOW_CNTL 0x1d3d
#define mmOTG4_OTG_FORCE_COUNT_NOW_CNTL_BASE_IDX 2
#define mmOTG4_OTG_FLOW_CONTROL 0x1d3e
#define mmOTG4_OTG_FLOW_CONTROL_BASE_IDX 2
#define mmOTG4_OTG_STEREO_FORCE_NEXT_EYE 0x1d3f
#define mmOTG4_OTG_STEREO_FORCE_NEXT_EYE_BASE_IDX 2
#define mmOTG4_OTG_CONTROL 0x1d41
#define mmOTG4_OTG_CONTROL_BASE_IDX 2
#define mmOTG4_OTG_INTERLACE_CONTROL 0x1d44
#define mmOTG4_OTG_INTERLACE_CONTROL_BASE_IDX 2
#define mmOTG4_OTG_INTERLACE_STATUS 0x1d45
#define mmOTG4_OTG_INTERLACE_STATUS_BASE_IDX 2
#define mmOTG4_OTG_PIXEL_DATA_READBACK0 0x1d47
#define mmOTG4_OTG_PIXEL_DATA_READBACK0_BASE_IDX 2
#define mmOTG4_OTG_PIXEL_DATA_READBACK1 0x1d48
#define mmOTG4_OTG_PIXEL_DATA_READBACK1_BASE_IDX 2
#define mmOTG4_OTG_STATUS 0x1d49
#define mmOTG4_OTG_STATUS_BASE_IDX 2
#define mmOTG4_OTG_STATUS_POSITION 0x1d4a
#define mmOTG4_OTG_STATUS_POSITION_BASE_IDX 2
#define mmOTG4_OTG_NOM_VERT_POSITION 0x1d4b
#define mmOTG4_OTG_NOM_VERT_POSITION_BASE_IDX 2
#define mmOTG4_OTG_STATUS_FRAME_COUNT 0x1d4c
#define mmOTG4_OTG_STATUS_FRAME_COUNT_BASE_IDX 2
#define mmOTG4_OTG_STATUS_VF_COUNT 0x1d4d
#define mmOTG4_OTG_STATUS_VF_COUNT_BASE_IDX 2
#define mmOTG4_OTG_STATUS_HV_COUNT 0x1d4e
#define mmOTG4_OTG_STATUS_HV_COUNT_BASE_IDX 2
#define mmOTG4_OTG_COUNT_CONTROL 0x1d4f
#define mmOTG4_OTG_COUNT_CONTROL_BASE_IDX 2
#define mmOTG4_OTG_COUNT_RESET 0x1d50
#define mmOTG4_OTG_COUNT_RESET_BASE_IDX 2
#define mmOTG4_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE 0x1d51
#define mmOTG4_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE_BASE_IDX 2
#define mmOTG4_OTG_VERT_SYNC_CONTROL 0x1d52
#define mmOTG4_OTG_VERT_SYNC_CONTROL_BASE_IDX 2
#define mmOTG4_OTG_STEREO_STATUS 0x1d53
#define mmOTG4_OTG_STEREO_STATUS_BASE_IDX 2
#define mmOTG4_OTG_STEREO_CONTROL 0x1d54
#define mmOTG4_OTG_STEREO_CONTROL_BASE_IDX 2
#define mmOTG4_OTG_SNAPSHOT_STATUS 0x1d55
#define mmOTG4_OTG_SNAPSHOT_STATUS_BASE_IDX 2
#define mmOTG4_OTG_SNAPSHOT_CONTROL 0x1d56
#define mmOTG4_OTG_SNAPSHOT_CONTROL_BASE_IDX 2
#define mmOTG4_OTG_SNAPSHOT_POSITION 0x1d57
#define mmOTG4_OTG_SNAPSHOT_POSITION_BASE_IDX 2
#define mmOTG4_OTG_SNAPSHOT_FRAME 0x1d58
#define mmOTG4_OTG_SNAPSHOT_FRAME_BASE_IDX 2
#define mmOTG4_OTG_INTERRUPT_CONTROL 0x1d59
#define mmOTG4_OTG_INTERRUPT_CONTROL_BASE_IDX 2
#define mmOTG4_OTG_UPDATE_LOCK 0x1d5a
#define mmOTG4_OTG_UPDATE_LOCK_BASE_IDX 2
#define mmOTG4_OTG_DOUBLE_BUFFER_CONTROL 0x1d5b
#define mmOTG4_OTG_DOUBLE_BUFFER_CONTROL_BASE_IDX 2
#define mmOTG4_OTG_MASTER_EN 0x1d5c
#define mmOTG4_OTG_MASTER_EN_BASE_IDX 2
#define mmOTG4_OTG_BLANK_DATA_COLOR 0x1d5e
#define mmOTG4_OTG_BLANK_DATA_COLOR_BASE_IDX 2
#define mmOTG4_OTG_BLANK_DATA_COLOR_EXT 0x1d5f
#define mmOTG4_OTG_BLANK_DATA_COLOR_EXT_BASE_IDX 2
#define mmOTG4_OTG_VERTICAL_INTERRUPT0_POSITION 0x1d62
#define mmOTG4_OTG_VERTICAL_INTERRUPT0_POSITION_BASE_IDX 2
#define mmOTG4_OTG_VERTICAL_INTERRUPT0_CONTROL 0x1d63
#define mmOTG4_OTG_VERTICAL_INTERRUPT0_CONTROL_BASE_IDX 2
#define mmOTG4_OTG_VERTICAL_INTERRUPT1_POSITION 0x1d64
#define mmOTG4_OTG_VERTICAL_INTERRUPT1_POSITION_BASE_IDX 2
#define mmOTG4_OTG_VERTICAL_INTERRUPT1_CONTROL 0x1d65
#define mmOTG4_OTG_VERTICAL_INTERRUPT1_CONTROL_BASE_IDX 2
#define mmOTG4_OTG_VERTICAL_INTERRUPT2_POSITION 0x1d66
#define mmOTG4_OTG_VERTICAL_INTERRUPT2_POSITION_BASE_IDX 2
#define mmOTG4_OTG_VERTICAL_INTERRUPT2_CONTROL 0x1d67
#define mmOTG4_OTG_VERTICAL_INTERRUPT2_CONTROL_BASE_IDX 2
#define mmOTG4_OTG_CRC_CNTL 0x1d68
#define mmOTG4_OTG_CRC_CNTL_BASE_IDX 2
#define mmOTG4_OTG_CRC_CNTL2 0x1d69
#define mmOTG4_OTG_CRC_CNTL2_BASE_IDX 2
#define mmOTG4_OTG_CRC0_WINDOWA_X_CONTROL 0x1d6a
#define mmOTG4_OTG_CRC0_WINDOWA_X_CONTROL_BASE_IDX 2
#define mmOTG4_OTG_CRC0_WINDOWA_Y_CONTROL 0x1d6b
#define mmOTG4_OTG_CRC0_WINDOWA_Y_CONTROL_BASE_IDX 2
#define mmOTG4_OTG_CRC0_WINDOWB_X_CONTROL 0x1d6c
#define mmOTG4_OTG_CRC0_WINDOWB_X_CONTROL_BASE_IDX 2
#define mmOTG4_OTG_CRC0_WINDOWB_Y_CONTROL 0x1d6d
#define mmOTG4_OTG_CRC0_WINDOWB_Y_CONTROL_BASE_IDX 2
#define mmOTG4_OTG_CRC0_DATA_RG 0x1d6e
#define mmOTG4_OTG_CRC0_DATA_RG_BASE_IDX 2
#define mmOTG4_OTG_CRC0_DATA_B 0x1d6f
#define mmOTG4_OTG_CRC0_DATA_B_BASE_IDX 2
#define mmOTG4_OTG_CRC1_WINDOWA_X_CONTROL 0x1d70
#define mmOTG4_OTG_CRC1_WINDOWA_X_CONTROL_BASE_IDX 2
#define mmOTG4_OTG_CRC1_WINDOWA_Y_CONTROL 0x1d71
#define mmOTG4_OTG_CRC1_WINDOWA_Y_CONTROL_BASE_IDX 2
#define mmOTG4_OTG_CRC1_WINDOWB_X_CONTROL 0x1d72
#define mmOTG4_OTG_CRC1_WINDOWB_X_CONTROL_BASE_IDX 2
#define mmOTG4_OTG_CRC1_WINDOWB_Y_CONTROL 0x1d73
#define mmOTG4_OTG_CRC1_WINDOWB_Y_CONTROL_BASE_IDX 2
#define mmOTG4_OTG_CRC1_DATA_RG 0x1d74
#define mmOTG4_OTG_CRC1_DATA_RG_BASE_IDX 2
#define mmOTG4_OTG_CRC1_DATA_B 0x1d75
#define mmOTG4_OTG_CRC1_DATA_B_BASE_IDX 2
#define mmOTG4_OTG_CRC2_DATA_RG 0x1d76
#define mmOTG4_OTG_CRC2_DATA_RG_BASE_IDX 2
#define mmOTG4_OTG_CRC2_DATA_B 0x1d77
#define mmOTG4_OTG_CRC2_DATA_B_BASE_IDX 2
#define mmOTG4_OTG_CRC3_DATA_RG 0x1d78
#define mmOTG4_OTG_CRC3_DATA_RG_BASE_IDX 2
#define mmOTG4_OTG_CRC3_DATA_B 0x1d79
#define mmOTG4_OTG_CRC3_DATA_B_BASE_IDX 2
#define mmOTG4_OTG_CRC_SIG_RED_GREEN_MASK 0x1d7a
#define mmOTG4_OTG_CRC_SIG_RED_GREEN_MASK_BASE_IDX 2
#define mmOTG4_OTG_CRC_SIG_BLUE_CONTROL_MASK 0x1d7b
#define mmOTG4_OTG_CRC_SIG_BLUE_CONTROL_MASK_BASE_IDX 2
#define mmOTG4_OTG_STATIC_SCREEN_CONTROL 0x1d82
#define mmOTG4_OTG_STATIC_SCREEN_CONTROL_BASE_IDX 2
#define mmOTG4_OTG_3D_STRUCTURE_CONTROL 0x1d83
#define mmOTG4_OTG_3D_STRUCTURE_CONTROL_BASE_IDX 2
#define mmOTG4_OTG_GSL_VSYNC_GAP 0x1d84
#define mmOTG4_OTG_GSL_VSYNC_GAP_BASE_IDX 2
#define mmOTG4_OTG_MASTER_UPDATE_MODE 0x1d85
#define mmOTG4_OTG_MASTER_UPDATE_MODE_BASE_IDX 2
#define mmOTG4_OTG_CLOCK_CONTROL 0x1d86
#define mmOTG4_OTG_CLOCK_CONTROL_BASE_IDX 2
#define mmOTG4_OTG_VSTARTUP_PARAM 0x1d87
#define mmOTG4_OTG_VSTARTUP_PARAM_BASE_IDX 2
#define mmOTG4_OTG_VUPDATE_PARAM 0x1d88
#define mmOTG4_OTG_VUPDATE_PARAM_BASE_IDX 2
#define mmOTG4_OTG_VREADY_PARAM 0x1d89
#define mmOTG4_OTG_VREADY_PARAM_BASE_IDX 2
#define mmOTG4_OTG_GLOBAL_SYNC_STATUS 0x1d8a
#define mmOTG4_OTG_GLOBAL_SYNC_STATUS_BASE_IDX 2
#define mmOTG4_OTG_MASTER_UPDATE_LOCK 0x1d8b
#define mmOTG4_OTG_MASTER_UPDATE_LOCK_BASE_IDX 2
#define mmOTG4_OTG_GSL_CONTROL 0x1d8c
#define mmOTG4_OTG_GSL_CONTROL_BASE_IDX 2
#define mmOTG4_OTG_GSL_WINDOW_X 0x1d8d
#define mmOTG4_OTG_GSL_WINDOW_X_BASE_IDX 2
#define mmOTG4_OTG_GSL_WINDOW_Y 0x1d8e
#define mmOTG4_OTG_GSL_WINDOW_Y_BASE_IDX 2
#define mmOTG4_OTG_VUPDATE_KEEPOUT 0x1d8f
#define mmOTG4_OTG_VUPDATE_KEEPOUT_BASE_IDX 2
#define mmOTG4_OTG_GLOBAL_CONTROL0 0x1d90
#define mmOTG4_OTG_GLOBAL_CONTROL0_BASE_IDX 2
#define mmOTG4_OTG_GLOBAL_CONTROL1 0x1d91
#define mmOTG4_OTG_GLOBAL_CONTROL1_BASE_IDX 2
#define mmOTG4_OTG_GLOBAL_CONTROL2 0x1d92
#define mmOTG4_OTG_GLOBAL_CONTROL2_BASE_IDX 2
#define mmOTG4_OTG_GLOBAL_CONTROL3 0x1d93
#define mmOTG4_OTG_GLOBAL_CONTROL3_BASE_IDX 2
#define mmOTG4_OTG_GLOBAL_CONTROL4 0x1d94
#define mmOTG4_OTG_GLOBAL_CONTROL4_BASE_IDX 2
#define mmOTG4_OTG_TRIG_MANUAL_CONTROL 0x1d95
#define mmOTG4_OTG_TRIG_MANUAL_CONTROL_BASE_IDX 2
#define mmOTG4_OTG_MANUAL_FLOW_CONTROL 0x1d96
#define mmOTG4_OTG_MANUAL_FLOW_CONTROL_BASE_IDX 2
#define mmOTG4_OTG_DRR_TIMING_INT_STATUS 0x1d97
#define mmOTG4_OTG_DRR_TIMING_INT_STATUS_BASE_IDX 2
#define mmOTG4_OTG_DRR_V_TOTAL_REACH_RANGE 0x1d98
#define mmOTG4_OTG_DRR_V_TOTAL_REACH_RANGE_BASE_IDX 2
#define mmOTG4_OTG_DRR_V_TOTAL_CHANGE 0x1d99
#define mmOTG4_OTG_DRR_V_TOTAL_CHANGE_BASE_IDX 2
#define mmOTG4_OTG_DRR_TRIGGER_WINDOW 0x1d9a
#define mmOTG4_OTG_DRR_TRIGGER_WINDOW_BASE_IDX 2
#define mmOTG4_OTG_DRR_CONTROL 0x1d9b
#define mmOTG4_OTG_DRR_CONTROL_BASE_IDX 2
#define mmOTG4_OTG_M_CONST_DTO0 0x1d9c
#define mmOTG4_OTG_M_CONST_DTO0_BASE_IDX 2
#define mmOTG4_OTG_M_CONST_DTO1 0x1d9d
#define mmOTG4_OTG_M_CONST_DTO1_BASE_IDX 2
#define mmOTG4_OTG_REQUEST_CONTROL 0x1d9e
#define mmOTG4_OTG_REQUEST_CONTROL_BASE_IDX 2
#define mmOTG4_OTG_DSC_START_POSITION 0x1d9f
#define mmOTG4_OTG_DSC_START_POSITION_BASE_IDX 2
#define mmOTG4_OTG_PIPE_UPDATE_STATUS 0x1da0
#define mmOTG4_OTG_PIPE_UPDATE_STATUS_BASE_IDX 2
#define mmOTG4_OTG_SPARE_REGISTER 0x1da2
#define mmOTG4_OTG_SPARE_REGISTER_BASE_IDX 2
// addressBlock: dce_dc_optc_optc_misc_dispdec
// base address: 0x0
#define mmDWB_SOURCE_SELECT 0x1e2a
#define mmDWB_SOURCE_SELECT_BASE_IDX 2
#define mmGSL_SOURCE_SELECT 0x1e2b
#define mmGSL_SOURCE_SELECT_BASE_IDX 2
#define mmOPTC_CLOCK_CONTROL 0x1e2c
#define mmOPTC_CLOCK_CONTROL_BASE_IDX 2
#define mmODM_MEM_PWR_CTRL 0x1e2d
#define mmODM_MEM_PWR_CTRL_BASE_IDX 2
#define mmODM_MEM_PWR_CTRL2 0x1e2e
#define mmODM_MEM_PWR_CTRL2_BASE_IDX 2
#define mmODM_MEM_PWR_CTRL3 0x1e2f
#define mmODM_MEM_PWR_CTRL3_BASE_IDX 2
#define mmODM_MEM_PWR_STATUS 0x1e30
#define mmODM_MEM_PWR_STATUS_BASE_IDX 2
#define mmOPTC_MISC_SPARE_REGISTER 0x1e31
#define mmOPTC_MISC_SPARE_REGISTER_BASE_IDX 2
// addressBlock: dce_dc_optc_optc_dcperfmon_dc_perfmon_dispdec
// base address: 0x79a8
#define mmDC_PERFMON17_PERFCOUNTER_CNTL 0x1e6a
#define mmDC_PERFMON17_PERFCOUNTER_CNTL_BASE_IDX 2
#define mmDC_PERFMON17_PERFCOUNTER_CNTL2 0x1e6b
#define mmDC_PERFMON17_PERFCOUNTER_CNTL2_BASE_IDX 2
#define mmDC_PERFMON17_PERFCOUNTER_STATE 0x1e6c
#define mmDC_PERFMON17_PERFCOUNTER_STATE_BASE_IDX 2
#define mmDC_PERFMON17_PERFMON_CNTL 0x1e6d
#define mmDC_PERFMON17_PERFMON_CNTL_BASE_IDX 2
#define mmDC_PERFMON17_PERFMON_CNTL2 0x1e6e
#define mmDC_PERFMON17_PERFMON_CNTL2_BASE_IDX 2
#define mmDC_PERFMON17_PERFMON_CVALUE_INT_MISC 0x1e6f
#define mmDC_PERFMON17_PERFMON_CVALUE_INT_MISC_BASE_IDX 2
#define mmDC_PERFMON17_PERFMON_CVALUE_LOW 0x1e70
#define mmDC_PERFMON17_PERFMON_CVALUE_LOW_BASE_IDX 2
#define mmDC_PERFMON17_PERFMON_HI 0x1e71
#define mmDC_PERFMON17_PERFMON_HI_BASE_IDX 2
#define mmDC_PERFMON17_PERFMON_LOW 0x1e72
#define mmDC_PERFMON17_PERFMON_LOW_BASE_IDX 2
// addressBlock: dce_dc_dio_dout_i2c_dispdec
// base address: 0x0
#define mmDC_I2C_CONTROL 0x1e98
#define mmDC_I2C_CONTROL_BASE_IDX 2
#define mmDC_I2C_ARBITRATION 0x1e99
#define mmDC_I2C_ARBITRATION_BASE_IDX 2
#define mmDC_I2C_INTERRUPT_CONTROL 0x1e9a
#define mmDC_I2C_INTERRUPT_CONTROL_BASE_IDX 2
#define mmDC_I2C_SW_STATUS 0x1e9b
#define mmDC_I2C_SW_STATUS_BASE_IDX 2
#define mmDC_I2C_DDC1_HW_STATUS 0x1e9c
#define mmDC_I2C_DDC1_HW_STATUS_BASE_IDX 2
#define mmDC_I2C_DDC2_HW_STATUS 0x1e9d
#define mmDC_I2C_DDC2_HW_STATUS_BASE_IDX 2
#define mmDC_I2C_DDC3_HW_STATUS 0x1e9e
#define mmDC_I2C_DDC3_HW_STATUS_BASE_IDX 2
#define mmDC_I2C_DDC4_HW_STATUS 0x1e9f
#define mmDC_I2C_DDC4_HW_STATUS_BASE_IDX 2
#define mmDC_I2C_DDC5_HW_STATUS 0x1ea0
#define mmDC_I2C_DDC5_HW_STATUS_BASE_IDX 2
#define mmDC_I2C_DDC1_SPEED 0x1ea2
#define mmDC_I2C_DDC1_SPEED_BASE_IDX 2
#define mmDC_I2C_DDC1_SETUP 0x1ea3
#define mmDC_I2C_DDC1_SETUP_BASE_IDX 2
#define mmDC_I2C_DDC2_SPEED 0x1ea4
#define mmDC_I2C_DDC2_SPEED_BASE_IDX 2
#define mmDC_I2C_DDC2_SETUP 0x1ea5
#define mmDC_I2C_DDC2_SETUP_BASE_IDX 2
#define mmDC_I2C_DDC3_SPEED 0x1ea6
#define mmDC_I2C_DDC3_SPEED_BASE_IDX 2
#define mmDC_I2C_DDC3_SETUP 0x1ea7
#define mmDC_I2C_DDC3_SETUP_BASE_IDX 2
#define mmDC_I2C_DDC4_SPEED 0x1ea8
#define mmDC_I2C_DDC4_SPEED_BASE_IDX 2
#define mmDC_I2C_DDC4_SETUP 0x1ea9
#define mmDC_I2C_DDC4_SETUP_BASE_IDX 2
#define mmDC_I2C_DDC5_SPEED 0x1eaa
#define mmDC_I2C_DDC5_SPEED_BASE_IDX 2
#define mmDC_I2C_DDC5_SETUP 0x1eab
#define mmDC_I2C_DDC5_SETUP_BASE_IDX 2
#define mmDC_I2C_TRANSACTION0 0x1eae
#define mmDC_I2C_TRANSACTION0_BASE_IDX 2
#define mmDC_I2C_TRANSACTION1 0x1eaf
#define mmDC_I2C_TRANSACTION1_BASE_IDX 2
#define mmDC_I2C_TRANSACTION2 0x1eb0
#define mmDC_I2C_TRANSACTION2_BASE_IDX 2
#define mmDC_I2C_TRANSACTION3 0x1eb1
#define mmDC_I2C_TRANSACTION3_BASE_IDX 2
#define mmDC_I2C_DATA 0x1eb2
#define mmDC_I2C_DATA_BASE_IDX 2
#define mmDC_I2C_EDID_DETECT_CTRL 0x1eb6
#define mmDC_I2C_EDID_DETECT_CTRL_BASE_IDX 2
#define mmDC_I2C_READ_REQUEST_INTERRUPT 0x1eb7
#define mmDC_I2C_READ_REQUEST_INTERRUPT_BASE_IDX 2
// addressBlock: dce_dc_dio_dio_misc_dispdec
// base address: 0x0
#define mmDIO_SCRATCH0 0x1eca
#define mmDIO_SCRATCH0_BASE_IDX 2
#define mmDIO_SCRATCH1 0x1ecb
#define mmDIO_SCRATCH1_BASE_IDX 2
#define mmDIO_SCRATCH2 0x1ecc
#define mmDIO_SCRATCH2_BASE_IDX 2
#define mmDIO_SCRATCH3 0x1ecd
#define mmDIO_SCRATCH3_BASE_IDX 2
#define mmDIO_SCRATCH4 0x1ece
#define mmDIO_SCRATCH4_BASE_IDX 2
#define mmDIO_SCRATCH5 0x1ecf
#define mmDIO_SCRATCH5_BASE_IDX 2
#define mmDIO_SCRATCH6 0x1ed0
#define mmDIO_SCRATCH6_BASE_IDX 2
#define mmDIO_SCRATCH7 0x1ed1
#define mmDIO_SCRATCH7_BASE_IDX 2
#define mmDIO_MEM_PWR_STATUS 0x1edd
#define mmDIO_MEM_PWR_STATUS_BASE_IDX 2
#define mmDIO_MEM_PWR_CTRL 0x1ede
#define mmDIO_MEM_PWR_CTRL_BASE_IDX 2
#define mmDIO_MEM_PWR_CTRL2 0x1edf
#define mmDIO_MEM_PWR_CTRL2_BASE_IDX 2
#define mmDIO_CLK_CNTL 0x1ee0
#define mmDIO_CLK_CNTL_BASE_IDX 2
#define mmDIO_POWER_MANAGEMENT_CNTL 0x1ee4
#define mmDIO_POWER_MANAGEMENT_CNTL_BASE_IDX 2
#define mmDIG_SOFT_RESET 0x1eee
#define mmDIG_SOFT_RESET_BASE_IDX 2
#define mmDIO_CLK_CNTL2 0x1ef2
#define mmDIO_CLK_CNTL2_BASE_IDX 2
#define mmDIO_CLK_CNTL3 0x1ef3
#define mmDIO_CLK_CNTL3_BASE_IDX 2
#define mmDIO_HDMI_RXSTATUS_TIMER_CONTROL 0x1eff
#define mmDIO_HDMI_RXSTATUS_TIMER_CONTROL_BASE_IDX 2
#define mmDIO_GENERIC_INTERRUPT_MESSAGE 0x1f02
#define mmDIO_GENERIC_INTERRUPT_MESSAGE_BASE_IDX 2
#define mmDIO_GENERIC_INTERRUPT_CLEAR 0x1f03
#define mmDIO_GENERIC_INTERRUPT_CLEAR_BASE_IDX 2
// addressBlock: dce_dc_dio_hpd0_dispdec
// base address: 0x0
#define mmHPD0_DC_HPD_INT_STATUS 0x1f14
#define mmHPD0_DC_HPD_INT_STATUS_BASE_IDX 2
#define mmHPD0_DC_HPD_INT_CONTROL 0x1f15
#define mmHPD0_DC_HPD_INT_CONTROL_BASE_IDX 2
#define mmHPD0_DC_HPD_CONTROL 0x1f16
#define mmHPD0_DC_HPD_CONTROL_BASE_IDX 2
#define mmHPD0_DC_HPD_FAST_TRAIN_CNTL 0x1f17
#define mmHPD0_DC_HPD_FAST_TRAIN_CNTL_BASE_IDX 2
#define mmHPD0_DC_HPD_TOGGLE_FILT_CNTL 0x1f18
#define mmHPD0_DC_HPD_TOGGLE_FILT_CNTL_BASE_IDX 2
// addressBlock: dce_dc_dio_hpd1_dispdec
// base address: 0x20
#define mmHPD1_DC_HPD_INT_STATUS 0x1f1c
#define mmHPD1_DC_HPD_INT_STATUS_BASE_IDX 2
#define mmHPD1_DC_HPD_INT_CONTROL 0x1f1d
#define mmHPD1_DC_HPD_INT_CONTROL_BASE_IDX 2
#define mmHPD1_DC_HPD_CONTROL 0x1f1e
#define mmHPD1_DC_HPD_CONTROL_BASE_IDX 2
#define mmHPD1_DC_HPD_FAST_TRAIN_CNTL 0x1f1f
#define mmHPD1_DC_HPD_FAST_TRAIN_CNTL_BASE_IDX 2
#define mmHPD1_DC_HPD_TOGGLE_FILT_CNTL 0x1f20
#define mmHPD1_DC_HPD_TOGGLE_FILT_CNTL_BASE_IDX 2
// addressBlock: dce_dc_dio_hpd2_dispdec
// base address: 0x40
#define mmHPD2_DC_HPD_INT_STATUS 0x1f24
#define mmHPD2_DC_HPD_INT_STATUS_BASE_IDX 2
#define mmHPD2_DC_HPD_INT_CONTROL 0x1f25
#define mmHPD2_DC_HPD_INT_CONTROL_BASE_IDX 2
#define mmHPD2_DC_HPD_CONTROL 0x1f26
#define mmHPD2_DC_HPD_CONTROL_BASE_IDX 2
#define mmHPD2_DC_HPD_FAST_TRAIN_CNTL 0x1f27
#define mmHPD2_DC_HPD_FAST_TRAIN_CNTL_BASE_IDX 2
#define mmHPD2_DC_HPD_TOGGLE_FILT_CNTL 0x1f28
#define mmHPD2_DC_HPD_TOGGLE_FILT_CNTL_BASE_IDX 2
// addressBlock: dce_dc_dio_hpd3_dispdec
// base address: 0x60
#define mmHPD3_DC_HPD_INT_STATUS 0x1f2c
#define mmHPD3_DC_HPD_INT_STATUS_BASE_IDX 2
#define mmHPD3_DC_HPD_INT_CONTROL 0x1f2d
#define mmHPD3_DC_HPD_INT_CONTROL_BASE_IDX 2
#define mmHPD3_DC_HPD_CONTROL 0x1f2e
#define mmHPD3_DC_HPD_CONTROL_BASE_IDX 2
#define mmHPD3_DC_HPD_FAST_TRAIN_CNTL 0x1f2f
#define mmHPD3_DC_HPD_FAST_TRAIN_CNTL_BASE_IDX 2
#define mmHPD3_DC_HPD_TOGGLE_FILT_CNTL 0x1f30
#define mmHPD3_DC_HPD_TOGGLE_FILT_CNTL_BASE_IDX 2
// addressBlock: dce_dc_dio_hpd4_dispdec
// base address: 0x80
#define mmHPD4_DC_HPD_INT_STATUS 0x1f34
#define mmHPD4_DC_HPD_INT_STATUS_BASE_IDX 2
#define mmHPD4_DC_HPD_INT_CONTROL 0x1f35
#define mmHPD4_DC_HPD_INT_CONTROL_BASE_IDX 2
#define mmHPD4_DC_HPD_CONTROL 0x1f36
#define mmHPD4_DC_HPD_CONTROL_BASE_IDX 2
#define mmHPD4_DC_HPD_FAST_TRAIN_CNTL 0x1f37
#define mmHPD4_DC_HPD_FAST_TRAIN_CNTL_BASE_IDX 2
#define mmHPD4_DC_HPD_TOGGLE_FILT_CNTL 0x1f38
#define mmHPD4_DC_HPD_TOGGLE_FILT_CNTL_BASE_IDX 2
// addressBlock: dce_dc_dio_dio_dcperfmon_dc_perfmon_dispdec
// base address: 0x7d10
#define mmDC_PERFMON18_PERFCOUNTER_CNTL 0x1f44
#define mmDC_PERFMON18_PERFCOUNTER_CNTL_BASE_IDX 2
#define mmDC_PERFMON18_PERFCOUNTER_CNTL2 0x1f45
#define mmDC_PERFMON18_PERFCOUNTER_CNTL2_BASE_IDX 2
#define mmDC_PERFMON18_PERFCOUNTER_STATE 0x1f46
#define mmDC_PERFMON18_PERFCOUNTER_STATE_BASE_IDX 2
#define mmDC_PERFMON18_PERFMON_CNTL 0x1f47
#define mmDC_PERFMON18_PERFMON_CNTL_BASE_IDX 2
#define mmDC_PERFMON18_PERFMON_CNTL2 0x1f48
#define mmDC_PERFMON18_PERFMON_CNTL2_BASE_IDX 2
#define mmDC_PERFMON18_PERFMON_CVALUE_INT_MISC 0x1f49
#define mmDC_PERFMON18_PERFMON_CVALUE_INT_MISC_BASE_IDX 2
#define mmDC_PERFMON18_PERFMON_CVALUE_LOW 0x1f4a
#define mmDC_PERFMON18_PERFMON_CVALUE_LOW_BASE_IDX 2
#define mmDC_PERFMON18_PERFMON_HI 0x1f4b
#define mmDC_PERFMON18_PERFMON_HI_BASE_IDX 2
#define mmDC_PERFMON18_PERFMON_LOW 0x1f4c
#define mmDC_PERFMON18_PERFMON_LOW_BASE_IDX 2
// addressBlock: dce_dc_dio_dp_aux0_dispdec
// base address: 0x0
#define mmDP_AUX0_AUX_CONTROL 0x1f50
#define mmDP_AUX0_AUX_CONTROL_BASE_IDX 2
#define mmDP_AUX0_AUX_SW_CONTROL 0x1f51
#define mmDP_AUX0_AUX_SW_CONTROL_BASE_IDX 2
#define mmDP_AUX0_AUX_ARB_CONTROL 0x1f52
#define mmDP_AUX0_AUX_ARB_CONTROL_BASE_IDX 2
#define mmDP_AUX0_AUX_INTERRUPT_CONTROL 0x1f53
#define mmDP_AUX0_AUX_INTERRUPT_CONTROL_BASE_IDX 2
#define mmDP_AUX0_AUX_SW_STATUS 0x1f54
#define mmDP_AUX0_AUX_SW_STATUS_BASE_IDX 2
#define mmDP_AUX0_AUX_LS_STATUS 0x1f55
#define mmDP_AUX0_AUX_LS_STATUS_BASE_IDX 2
#define mmDP_AUX0_AUX_SW_DATA 0x1f56
#define mmDP_AUX0_AUX_SW_DATA_BASE_IDX 2
#define mmDP_AUX0_AUX_LS_DATA 0x1f57
#define mmDP_AUX0_AUX_LS_DATA_BASE_IDX 2
#define mmDP_AUX0_AUX_DPHY_TX_REF_CONTROL 0x1f58
#define mmDP_AUX0_AUX_DPHY_TX_REF_CONTROL_BASE_IDX 2
#define mmDP_AUX0_AUX_DPHY_TX_CONTROL 0x1f59
#define mmDP_AUX0_AUX_DPHY_TX_CONTROL_BASE_IDX 2
#define mmDP_AUX0_AUX_DPHY_RX_CONTROL0 0x1f5a
#define mmDP_AUX0_AUX_DPHY_RX_CONTROL0_BASE_IDX 2
#define mmDP_AUX0_AUX_DPHY_RX_CONTROL1 0x1f5b
#define mmDP_AUX0_AUX_DPHY_RX_CONTROL1_BASE_IDX 2
#define mmDP_AUX0_AUX_DPHY_TX_STATUS 0x1f5c
#define mmDP_AUX0_AUX_DPHY_TX_STATUS_BASE_IDX 2
#define mmDP_AUX0_AUX_DPHY_RX_STATUS 0x1f5d
#define mmDP_AUX0_AUX_DPHY_RX_STATUS_BASE_IDX 2
#define mmDP_AUX0_AUX_GTC_SYNC_CONTROL 0x1f5e
#define mmDP_AUX0_AUX_GTC_SYNC_CONTROL_BASE_IDX 2
#define mmDP_AUX0_AUX_GTC_SYNC_ERROR_CONTROL 0x1f5f
#define mmDP_AUX0_AUX_GTC_SYNC_ERROR_CONTROL_BASE_IDX 2
#define mmDP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS 0x1f60
#define mmDP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS_BASE_IDX 2
#define mmDP_AUX0_AUX_GTC_SYNC_STATUS 0x1f61
#define mmDP_AUX0_AUX_GTC_SYNC_STATUS_BASE_IDX 2
#define mmDP_AUX0_AUX_PHY_WAKE_CNTL 0x1f66
#define mmDP_AUX0_AUX_PHY_WAKE_CNTL_BASE_IDX 2
// addressBlock: dce_dc_dio_dp_aux1_dispdec
// base address: 0x70
#define mmDP_AUX1_AUX_CONTROL 0x1f6c
#define mmDP_AUX1_AUX_CONTROL_BASE_IDX 2
#define mmDP_AUX1_AUX_SW_CONTROL 0x1f6d
#define mmDP_AUX1_AUX_SW_CONTROL_BASE_IDX 2
#define mmDP_AUX1_AUX_ARB_CONTROL 0x1f6e
#define mmDP_AUX1_AUX_ARB_CONTROL_BASE_IDX 2
#define mmDP_AUX1_AUX_INTERRUPT_CONTROL 0x1f6f
#define mmDP_AUX1_AUX_INTERRUPT_CONTROL_BASE_IDX 2
#define mmDP_AUX1_AUX_SW_STATUS 0x1f70
#define mmDP_AUX1_AUX_SW_STATUS_BASE_IDX 2
#define mmDP_AUX1_AUX_LS_STATUS 0x1f71
#define mmDP_AUX1_AUX_LS_STATUS_BASE_IDX 2
#define mmDP_AUX1_AUX_SW_DATA 0x1f72
#define mmDP_AUX1_AUX_SW_DATA_BASE_IDX 2
#define mmDP_AUX1_AUX_LS_DATA 0x1f73
#define mmDP_AUX1_AUX_LS_DATA_BASE_IDX 2
#define mmDP_AUX1_AUX_DPHY_TX_REF_CONTROL 0x1f74
#define mmDP_AUX1_AUX_DPHY_TX_REF_CONTROL_BASE_IDX 2
#define mmDP_AUX1_AUX_DPHY_TX_CONTROL 0x1f75
#define mmDP_AUX1_AUX_DPHY_TX_CONTROL_BASE_IDX 2
#define mmDP_AUX1_AUX_DPHY_RX_CONTROL0 0x1f76
#define mmDP_AUX1_AUX_DPHY_RX_CONTROL0_BASE_IDX 2
#define mmDP_AUX1_AUX_DPHY_RX_CONTROL1 0x1f77
#define mmDP_AUX1_AUX_DPHY_RX_CONTROL1_BASE_IDX 2
#define mmDP_AUX1_AUX_DPHY_TX_STATUS 0x1f78
#define mmDP_AUX1_AUX_DPHY_TX_STATUS_BASE_IDX 2
#define mmDP_AUX1_AUX_DPHY_RX_STATUS 0x1f79
#define mmDP_AUX1_AUX_DPHY_RX_STATUS_BASE_IDX 2
#define mmDP_AUX1_AUX_GTC_SYNC_CONTROL 0x1f7a
#define mmDP_AUX1_AUX_GTC_SYNC_CONTROL_BASE_IDX 2
#define mmDP_AUX1_AUX_GTC_SYNC_ERROR_CONTROL 0x1f7b
#define mmDP_AUX1_AUX_GTC_SYNC_ERROR_CONTROL_BASE_IDX 2
#define mmDP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS 0x1f7c
#define mmDP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS_BASE_IDX 2
#define mmDP_AUX1_AUX_GTC_SYNC_STATUS 0x1f7d
#define mmDP_AUX1_AUX_GTC_SYNC_STATUS_BASE_IDX 2
#define mmDP_AUX1_AUX_PHY_WAKE_CNTL 0x1f82
#define mmDP_AUX1_AUX_PHY_WAKE_CNTL_BASE_IDX 2
// addressBlock: dce_dc_dio_dp_aux2_dispdec
// base address: 0xe0
#define mmDP_AUX2_AUX_CONTROL 0x1f88
#define mmDP_AUX2_AUX_CONTROL_BASE_IDX 2
#define mmDP_AUX2_AUX_SW_CONTROL 0x1f89
#define mmDP_AUX2_AUX_SW_CONTROL_BASE_IDX 2
#define mmDP_AUX2_AUX_ARB_CONTROL 0x1f8a
#define mmDP_AUX2_AUX_ARB_CONTROL_BASE_IDX 2
#define mmDP_AUX2_AUX_INTERRUPT_CONTROL 0x1f8b
#define mmDP_AUX2_AUX_INTERRUPT_CONTROL_BASE_IDX 2
#define mmDP_AUX2_AUX_SW_STATUS 0x1f8c
#define mmDP_AUX2_AUX_SW_STATUS_BASE_IDX 2
#define mmDP_AUX2_AUX_LS_STATUS 0x1f8d
#define mmDP_AUX2_AUX_LS_STATUS_BASE_IDX 2
#define mmDP_AUX2_AUX_SW_DATA 0x1f8e
#define mmDP_AUX2_AUX_SW_DATA_BASE_IDX 2
#define mmDP_AUX2_AUX_LS_DATA 0x1f8f
#define mmDP_AUX2_AUX_LS_DATA_BASE_IDX 2
#define mmDP_AUX2_AUX_DPHY_TX_REF_CONTROL 0x1f90
#define mmDP_AUX2_AUX_DPHY_TX_REF_CONTROL_BASE_IDX 2
#define mmDP_AUX2_AUX_DPHY_TX_CONTROL 0x1f91
#define mmDP_AUX2_AUX_DPHY_TX_CONTROL_BASE_IDX 2
#define mmDP_AUX2_AUX_DPHY_RX_CONTROL0 0x1f92
#define mmDP_AUX2_AUX_DPHY_RX_CONTROL0_BASE_IDX 2
#define mmDP_AUX2_AUX_DPHY_RX_CONTROL1 0x1f93
#define mmDP_AUX2_AUX_DPHY_RX_CONTROL1_BASE_IDX 2
#define mmDP_AUX2_AUX_DPHY_TX_STATUS 0x1f94
#define mmDP_AUX2_AUX_DPHY_TX_STATUS_BASE_IDX 2
#define mmDP_AUX2_AUX_DPHY_RX_STATUS 0x1f95
#define mmDP_AUX2_AUX_DPHY_RX_STATUS_BASE_IDX 2
#define mmDP_AUX2_AUX_GTC_SYNC_CONTROL 0x1f96
#define mmDP_AUX2_AUX_GTC_SYNC_CONTROL_BASE_IDX 2
#define mmDP_AUX2_AUX_GTC_SYNC_ERROR_CONTROL 0x1f97
#define mmDP_AUX2_AUX_GTC_SYNC_ERROR_CONTROL_BASE_IDX 2
#define mmDP_AUX2_AUX_GTC_SYNC_CONTROLLER_STATUS 0x1f98
#define mmDP_AUX2_AUX_GTC_SYNC_CONTROLLER_STATUS_BASE_IDX 2
#define mmDP_AUX2_AUX_GTC_SYNC_STATUS 0x1f99
#define mmDP_AUX2_AUX_GTC_SYNC_STATUS_BASE_IDX 2
#define mmDP_AUX2_AUX_PHY_WAKE_CNTL 0x1f9e
#define mmDP_AUX2_AUX_PHY_WAKE_CNTL_BASE_IDX 2
// addressBlock: dce_dc_dio_dp_aux3_dispdec
// base address: 0x150
#define mmDP_AUX3_AUX_CONTROL 0x1fa4
#define mmDP_AUX3_AUX_CONTROL_BASE_IDX 2
#define mmDP_AUX3_AUX_SW_CONTROL 0x1fa5
#define mmDP_AUX3_AUX_SW_CONTROL_BASE_IDX 2
#define mmDP_AUX3_AUX_ARB_CONTROL 0x1fa6
#define mmDP_AUX3_AUX_ARB_CONTROL_BASE_IDX 2
#define mmDP_AUX3_AUX_INTERRUPT_CONTROL 0x1fa7
#define mmDP_AUX3_AUX_INTERRUPT_CONTROL_BASE_IDX 2
#define mmDP_AUX3_AUX_SW_STATUS 0x1fa8
#define mmDP_AUX3_AUX_SW_STATUS_BASE_IDX 2
#define mmDP_AUX3_AUX_LS_STATUS 0x1fa9
#define mmDP_AUX3_AUX_LS_STATUS_BASE_IDX 2
#define mmDP_AUX3_AUX_SW_DATA 0x1faa
#define mmDP_AUX3_AUX_SW_DATA_BASE_IDX 2
#define mmDP_AUX3_AUX_LS_DATA 0x1fab
#define mmDP_AUX3_AUX_LS_DATA_BASE_IDX 2
#define mmDP_AUX3_AUX_DPHY_TX_REF_CONTROL 0x1fac
#define mmDP_AUX3_AUX_DPHY_TX_REF_CONTROL_BASE_IDX 2
#define mmDP_AUX3_AUX_DPHY_TX_CONTROL 0x1fad
#define mmDP_AUX3_AUX_DPHY_TX_CONTROL_BASE_IDX 2
#define mmDP_AUX3_AUX_DPHY_RX_CONTROL0 0x1fae
#define mmDP_AUX3_AUX_DPHY_RX_CONTROL0_BASE_IDX 2
#define mmDP_AUX3_AUX_DPHY_RX_CONTROL1 0x1faf
#define mmDP_AUX3_AUX_DPHY_RX_CONTROL1_BASE_IDX 2
#define mmDP_AUX3_AUX_DPHY_TX_STATUS 0x1fb0
#define mmDP_AUX3_AUX_DPHY_TX_STATUS_BASE_IDX 2
#define mmDP_AUX3_AUX_DPHY_RX_STATUS 0x1fb1
#define mmDP_AUX3_AUX_DPHY_RX_STATUS_BASE_IDX 2
#define mmDP_AUX3_AUX_GTC_SYNC_CONTROL 0x1fb2
#define mmDP_AUX3_AUX_GTC_SYNC_CONTROL_BASE_IDX 2
#define mmDP_AUX3_AUX_GTC_SYNC_ERROR_CONTROL 0x1fb3
#define mmDP_AUX3_AUX_GTC_SYNC_ERROR_CONTROL_BASE_IDX 2
#define mmDP_AUX3_AUX_GTC_SYNC_CONTROLLER_STATUS 0x1fb4
#define mmDP_AUX3_AUX_GTC_SYNC_CONTROLLER_STATUS_BASE_IDX 2
#define mmDP_AUX3_AUX_GTC_SYNC_STATUS 0x1fb5
#define mmDP_AUX3_AUX_GTC_SYNC_STATUS_BASE_IDX 2
#define mmDP_AUX3_AUX_PHY_WAKE_CNTL 0x1fba
#define mmDP_AUX3_AUX_PHY_WAKE_CNTL_BASE_IDX 2
// addressBlock: dce_dc_dio_dp_aux4_dispdec
// base address: 0x1c0
#define mmDP_AUX4_AUX_CONTROL 0x1fc0
#define mmDP_AUX4_AUX_CONTROL_BASE_IDX 2
#define mmDP_AUX4_AUX_SW_CONTROL 0x1fc1
#define mmDP_AUX4_AUX_SW_CONTROL_BASE_IDX 2
#define mmDP_AUX4_AUX_ARB_CONTROL 0x1fc2
#define mmDP_AUX4_AUX_ARB_CONTROL_BASE_IDX 2
#define mmDP_AUX4_AUX_INTERRUPT_CONTROL 0x1fc3
#define mmDP_AUX4_AUX_INTERRUPT_CONTROL_BASE_IDX 2
#define mmDP_AUX4_AUX_SW_STATUS 0x1fc4
#define mmDP_AUX4_AUX_SW_STATUS_BASE_IDX 2
#define mmDP_AUX4_AUX_LS_STATUS 0x1fc5
#define mmDP_AUX4_AUX_LS_STATUS_BASE_IDX 2
#define mmDP_AUX4_AUX_SW_DATA 0x1fc6
#define mmDP_AUX4_AUX_SW_DATA_BASE_IDX 2
#define mmDP_AUX4_AUX_LS_DATA 0x1fc7
#define mmDP_AUX4_AUX_LS_DATA_BASE_IDX 2
#define mmDP_AUX4_AUX_DPHY_TX_REF_CONTROL 0x1fc8
#define mmDP_AUX4_AUX_DPHY_TX_REF_CONTROL_BASE_IDX 2
#define mmDP_AUX4_AUX_DPHY_TX_CONTROL 0x1fc9
#define mmDP_AUX4_AUX_DPHY_TX_CONTROL_BASE_IDX 2
#define mmDP_AUX4_AUX_DPHY_RX_CONTROL0 0x1fca
#define mmDP_AUX4_AUX_DPHY_RX_CONTROL0_BASE_IDX 2
#define mmDP_AUX4_AUX_DPHY_RX_CONTROL1 0x1fcb
#define mmDP_AUX4_AUX_DPHY_RX_CONTROL1_BASE_IDX 2
#define mmDP_AUX4_AUX_DPHY_TX_STATUS 0x1fcc
#define mmDP_AUX4_AUX_DPHY_TX_STATUS_BASE_IDX 2
#define mmDP_AUX4_AUX_DPHY_RX_STATUS 0x1fcd
#define mmDP_AUX4_AUX_DPHY_RX_STATUS_BASE_IDX 2
#define mmDP_AUX4_AUX_GTC_SYNC_CONTROL 0x1fce
#define mmDP_AUX4_AUX_GTC_SYNC_CONTROL_BASE_IDX 2
#define mmDP_AUX4_AUX_GTC_SYNC_ERROR_CONTROL 0x1fcf
#define mmDP_AUX4_AUX_GTC_SYNC_ERROR_CONTROL_BASE_IDX 2
#define mmDP_AUX4_AUX_GTC_SYNC_CONTROLLER_STATUS 0x1fd0
#define mmDP_AUX4_AUX_GTC_SYNC_CONTROLLER_STATUS_BASE_IDX 2
#define mmDP_AUX4_AUX_GTC_SYNC_STATUS 0x1fd1
#define mmDP_AUX4_AUX_GTC_SYNC_STATUS_BASE_IDX 2
#define mmDP_AUX4_AUX_PHY_WAKE_CNTL 0x1fd6
#define mmDP_AUX4_AUX_PHY_WAKE_CNTL_BASE_IDX 2
// addressBlock: dce_dc_dio_dig0_vpg_vpg_dispdec
// base address: 0x154a0
#define mmVPG0_VPG_GENERIC_PACKET_ACCESS_CTRL 0x2068
#define mmVPG0_VPG_GENERIC_PACKET_ACCESS_CTRL_BASE_IDX 2
#define mmVPG0_VPG_GENERIC_PACKET_DATA 0x2069
#define mmVPG0_VPG_GENERIC_PACKET_DATA_BASE_IDX 2
#define mmVPG0_VPG_GSP_FRAME_UPDATE_CTRL 0x206a
#define mmVPG0_VPG_GSP_FRAME_UPDATE_CTRL_BASE_IDX 2
#define mmVPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL 0x206b
#define mmVPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL_BASE_IDX 2
#define mmVPG0_VPG_GENERIC_STATUS 0x206c
#define mmVPG0_VPG_GENERIC_STATUS_BASE_IDX 2
#define mmVPG0_VPG_MEM_PWR 0x206d
#define mmVPG0_VPG_MEM_PWR_BASE_IDX 2
#define mmVPG0_VPG_ISRC1_2_ACCESS_CTRL 0x206e
#define mmVPG0_VPG_ISRC1_2_ACCESS_CTRL_BASE_IDX 2
#define mmVPG0_VPG_ISRC1_2_DATA 0x206f
#define mmVPG0_VPG_ISRC1_2_DATA_BASE_IDX 2
#define mmVPG0_VPG_MPEG_INFO0 0x2070
#define mmVPG0_VPG_MPEG_INFO0_BASE_IDX 2
#define mmVPG0_VPG_MPEG_INFO1 0x2071
#define mmVPG0_VPG_MPEG_INFO1_BASE_IDX 2
// addressBlock: dce_dc_dio_dig0_afmt_afmt_dispdec
// base address: 0x154cc
#define mmAFMT0_AFMT_VBI_PACKET_CONTROL 0x2074
#define mmAFMT0_AFMT_VBI_PACKET_CONTROL_BASE_IDX 2
#define mmAFMT0_AFMT_AUDIO_PACKET_CONTROL2 0x2075
#define mmAFMT0_AFMT_AUDIO_PACKET_CONTROL2_BASE_IDX 2
#define mmAFMT0_AFMT_AUDIO_INFO0 0x2076
#define mmAFMT0_AFMT_AUDIO_INFO0_BASE_IDX 2
#define mmAFMT0_AFMT_AUDIO_INFO1 0x2077
#define mmAFMT0_AFMT_AUDIO_INFO1_BASE_IDX 2
#define mmAFMT0_AFMT_60958_0 0x2078
#define mmAFMT0_AFMT_60958_0_BASE_IDX 2
#define mmAFMT0_AFMT_60958_1 0x2079
#define mmAFMT0_AFMT_60958_1_BASE_IDX 2
#define mmAFMT0_AFMT_AUDIO_CRC_CONTROL 0x207a
#define mmAFMT0_AFMT_AUDIO_CRC_CONTROL_BASE_IDX 2
#define mmAFMT0_AFMT_RAMP_CONTROL0 0x207b
#define mmAFMT0_AFMT_RAMP_CONTROL0_BASE_IDX 2
#define mmAFMT0_AFMT_RAMP_CONTROL1 0x207c
#define mmAFMT0_AFMT_RAMP_CONTROL1_BASE_IDX 2
#define mmAFMT0_AFMT_RAMP_CONTROL2 0x207d
#define mmAFMT0_AFMT_RAMP_CONTROL2_BASE_IDX 2
#define mmAFMT0_AFMT_RAMP_CONTROL3 0x207e
#define mmAFMT0_AFMT_RAMP_CONTROL3_BASE_IDX 2
#define mmAFMT0_AFMT_60958_2 0x207f
#define mmAFMT0_AFMT_60958_2_BASE_IDX 2
#define mmAFMT0_AFMT_AUDIO_CRC_RESULT 0x2080
#define mmAFMT0_AFMT_AUDIO_CRC_RESULT_BASE_IDX 2
#define mmAFMT0_AFMT_STATUS 0x2081
#define mmAFMT0_AFMT_STATUS_BASE_IDX 2
#define mmAFMT0_AFMT_AUDIO_PACKET_CONTROL 0x2082
#define mmAFMT0_AFMT_AUDIO_PACKET_CONTROL_BASE_IDX 2
#define mmAFMT0_AFMT_INFOFRAME_CONTROL0 0x2083
#define mmAFMT0_AFMT_INFOFRAME_CONTROL0_BASE_IDX 2
#define mmAFMT0_AFMT_INTERRUPT_STATUS 0x2084
#define mmAFMT0_AFMT_INTERRUPT_STATUS_BASE_IDX 2
#define mmAFMT0_AFMT_AUDIO_SRC_CONTROL 0x2085
#define mmAFMT0_AFMT_AUDIO_SRC_CONTROL_BASE_IDX 2
#define mmAFMT0_AFMT_MEM_PWR 0x2087
#define mmAFMT0_AFMT_MEM_PWR_BASE_IDX 2
// addressBlock: dce_dc_dio_dig0_dme_dme_dispdec
// base address: 0x15524
#define mmDME0_DME_CONTROL 0x2089
#define mmDME0_DME_CONTROL_BASE_IDX 2
#define mmDME0_DME_MEMORY_CONTROL 0x208a
#define mmDME0_DME_MEMORY_CONTROL_BASE_IDX 2
// addressBlock: dce_dc_dio_dig0_dispdec
// base address: 0x0
#define mmDIG0_DIG_FE_CNTL 0x208b
#define mmDIG0_DIG_FE_CNTL_BASE_IDX 2
#define mmDIG0_DIG_OUTPUT_CRC_CNTL 0x208c
#define mmDIG0_DIG_OUTPUT_CRC_CNTL_BASE_IDX 2
#define mmDIG0_DIG_OUTPUT_CRC_RESULT 0x208d
#define mmDIG0_DIG_OUTPUT_CRC_RESULT_BASE_IDX 2
#define mmDIG0_DIG_CLOCK_PATTERN 0x208e
#define mmDIG0_DIG_CLOCK_PATTERN_BASE_IDX 2
#define mmDIG0_DIG_TEST_PATTERN 0x208f
#define mmDIG0_DIG_TEST_PATTERN_BASE_IDX 2
#define mmDIG0_DIG_RANDOM_PATTERN_SEED 0x2090
#define mmDIG0_DIG_RANDOM_PATTERN_SEED_BASE_IDX 2
#define mmDIG0_DIG_FIFO_STATUS 0x2091
#define mmDIG0_DIG_FIFO_STATUS_BASE_IDX 2
#define mmDIG0_HDMI_METADATA_PACKET_CONTROL 0x2092
#define mmDIG0_HDMI_METADATA_PACKET_CONTROL_BASE_IDX 2
#define mmDIG0_HDMI_CONTROL 0x2093
#define mmDIG0_HDMI_CONTROL_BASE_IDX 2
#define mmDIG0_HDMI_STATUS 0x2094
#define mmDIG0_HDMI_STATUS_BASE_IDX 2
#define mmDIG0_HDMI_AUDIO_PACKET_CONTROL 0x2095
#define mmDIG0_HDMI_AUDIO_PACKET_CONTROL_BASE_IDX 2
#define mmDIG0_HDMI_ACR_PACKET_CONTROL 0x2096
#define mmDIG0_HDMI_ACR_PACKET_CONTROL_BASE_IDX 2
#define mmDIG0_HDMI_VBI_PACKET_CONTROL 0x2097
#define mmDIG0_HDMI_VBI_PACKET_CONTROL_BASE_IDX 2
#define mmDIG0_HDMI_INFOFRAME_CONTROL0 0x2098
#define mmDIG0_HDMI_INFOFRAME_CONTROL0_BASE_IDX 2
#define mmDIG0_HDMI_INFOFRAME_CONTROL1 0x2099
#define mmDIG0_HDMI_INFOFRAME_CONTROL1_BASE_IDX 2
#define mmDIG0_HDMI_GENERIC_PACKET_CONTROL0 0x209a
#define mmDIG0_HDMI_GENERIC_PACKET_CONTROL0_BASE_IDX 2
#define mmDIG0_HDMI_GENERIC_PACKET_CONTROL6 0x209b
#define mmDIG0_HDMI_GENERIC_PACKET_CONTROL6_BASE_IDX 2
#define mmDIG0_HDMI_GENERIC_PACKET_CONTROL5 0x209c
#define mmDIG0_HDMI_GENERIC_PACKET_CONTROL5_BASE_IDX 2
#define mmDIG0_HDMI_GC 0x209d
#define mmDIG0_HDMI_GC_BASE_IDX 2
#define mmDIG0_HDMI_GENERIC_PACKET_CONTROL1 0x209e
#define mmDIG0_HDMI_GENERIC_PACKET_CONTROL1_BASE_IDX 2
#define mmDIG0_HDMI_GENERIC_PACKET_CONTROL2 0x209f
#define mmDIG0_HDMI_GENERIC_PACKET_CONTROL2_BASE_IDX 2
#define mmDIG0_HDMI_GENERIC_PACKET_CONTROL3 0x20a0
#define mmDIG0_HDMI_GENERIC_PACKET_CONTROL3_BASE_IDX 2
#define mmDIG0_HDMI_GENERIC_PACKET_CONTROL4 0x20a1
#define mmDIG0_HDMI_GENERIC_PACKET_CONTROL4_BASE_IDX 2
#define mmDIG0_HDMI_GENERIC_PACKET_CONTROL7 0x20a2
#define mmDIG0_HDMI_GENERIC_PACKET_CONTROL7_BASE_IDX 2
#define mmDIG0_HDMI_GENERIC_PACKET_CONTROL8 0x20a3
#define mmDIG0_HDMI_GENERIC_PACKET_CONTROL8_BASE_IDX 2
#define mmDIG0_HDMI_GENERIC_PACKET_CONTROL9 0x20a4
#define mmDIG0_HDMI_GENERIC_PACKET_CONTROL9_BASE_IDX 2
#define mmDIG0_HDMI_GENERIC_PACKET_CONTROL10 0x20a5
#define mmDIG0_HDMI_GENERIC_PACKET_CONTROL10_BASE_IDX 2
#define mmDIG0_HDMI_DB_CONTROL 0x20a6
#define mmDIG0_HDMI_DB_CONTROL_BASE_IDX 2
#define mmDIG0_HDMI_ACR_32_0 0x20a7
#define mmDIG0_HDMI_ACR_32_0_BASE_IDX 2
#define mmDIG0_HDMI_ACR_32_1 0x20a8
#define mmDIG0_HDMI_ACR_32_1_BASE_IDX 2
#define mmDIG0_HDMI_ACR_44_0 0x20a9
#define mmDIG0_HDMI_ACR_44_0_BASE_IDX 2
#define mmDIG0_HDMI_ACR_44_1 0x20aa
#define mmDIG0_HDMI_ACR_44_1_BASE_IDX 2
#define mmDIG0_HDMI_ACR_48_0 0x20ab
#define mmDIG0_HDMI_ACR_48_0_BASE_IDX 2
#define mmDIG0_HDMI_ACR_48_1 0x20ac
#define mmDIG0_HDMI_ACR_48_1_BASE_IDX 2
#define mmDIG0_HDMI_ACR_STATUS_0 0x20ad
#define mmDIG0_HDMI_ACR_STATUS_0_BASE_IDX 2
#define mmDIG0_HDMI_ACR_STATUS_1 0x20ae
#define mmDIG0_HDMI_ACR_STATUS_1_BASE_IDX 2
#define mmDIG0_AFMT_CNTL 0x20af
#define mmDIG0_AFMT_CNTL_BASE_IDX 2
#define mmDIG0_DIG_BE_CNTL 0x20b0
#define mmDIG0_DIG_BE_CNTL_BASE_IDX 2
#define mmDIG0_DIG_BE_EN_CNTL 0x20b1
#define mmDIG0_DIG_BE_EN_CNTL_BASE_IDX 2
#define mmDIG0_TMDS_CNTL 0x20d7
#define mmDIG0_TMDS_CNTL_BASE_IDX 2
#define mmDIG0_TMDS_CONTROL_CHAR 0x20d8
#define mmDIG0_TMDS_CONTROL_CHAR_BASE_IDX 2
#define mmDIG0_TMDS_CONTROL0_FEEDBACK 0x20d9
#define mmDIG0_TMDS_CONTROL0_FEEDBACK_BASE_IDX 2
#define mmDIG0_TMDS_STEREOSYNC_CTL_SEL 0x20da
#define mmDIG0_TMDS_STEREOSYNC_CTL_SEL_BASE_IDX 2
#define mmDIG0_TMDS_SYNC_CHAR_PATTERN_0_1 0x20db
#define mmDIG0_TMDS_SYNC_CHAR_PATTERN_0_1_BASE_IDX 2
#define mmDIG0_TMDS_SYNC_CHAR_PATTERN_2_3 0x20dc
#define mmDIG0_TMDS_SYNC_CHAR_PATTERN_2_3_BASE_IDX 2
#define mmDIG0_TMDS_CTL_BITS 0x20de
#define mmDIG0_TMDS_CTL_BITS_BASE_IDX 2
#define mmDIG0_TMDS_DCBALANCER_CONTROL 0x20df
#define mmDIG0_TMDS_DCBALANCER_CONTROL_BASE_IDX 2
#define mmDIG0_TMDS_SYNC_DCBALANCE_CHAR 0x20e0
#define mmDIG0_TMDS_SYNC_DCBALANCE_CHAR_BASE_IDX 2
#define mmDIG0_TMDS_CTL0_1_GEN_CNTL 0x20e1
#define mmDIG0_TMDS_CTL0_1_GEN_CNTL_BASE_IDX 2
#define mmDIG0_TMDS_CTL2_3_GEN_CNTL 0x20e2
#define mmDIG0_TMDS_CTL2_3_GEN_CNTL_BASE_IDX 2
#define mmDIG0_DIG_VERSION 0x20e4
#define mmDIG0_DIG_VERSION_BASE_IDX 2
#define mmDIG0_DIG_LANE_ENABLE 0x20e5
#define mmDIG0_DIG_LANE_ENABLE_BASE_IDX 2
#define mmDIG0_FORCE_DIG_DISABLE 0x20e6
#define mmDIG0_FORCE_DIG_DISABLE_BASE_IDX 2
// addressBlock: dce_dc_dio_dp0_dispdec
// base address: 0x0
#define mmDP0_DP_LINK_CNTL 0x2108
#define mmDP0_DP_LINK_CNTL_BASE_IDX 2
#define mmDP0_DP_PIXEL_FORMAT 0x2109
#define mmDP0_DP_PIXEL_FORMAT_BASE_IDX 2
#define mmDP0_DP_MSA_COLORIMETRY 0x210a
#define mmDP0_DP_MSA_COLORIMETRY_BASE_IDX 2
#define mmDP0_DP_CONFIG 0x210b
#define mmDP0_DP_CONFIG_BASE_IDX 2
#define mmDP0_DP_VID_STREAM_CNTL 0x210c
#define mmDP0_DP_VID_STREAM_CNTL_BASE_IDX 2
#define mmDP0_DP_STEER_FIFO 0x210d
#define mmDP0_DP_STEER_FIFO_BASE_IDX 2
#define mmDP0_DP_MSA_MISC 0x210e
#define mmDP0_DP_MSA_MISC_BASE_IDX 2
#define mmDP0_DP_DPHY_INTERNAL_CTRL 0x210f
#define mmDP0_DP_DPHY_INTERNAL_CTRL_BASE_IDX 2
#define mmDP0_DP_VID_TIMING 0x2110
#define mmDP0_DP_VID_TIMING_BASE_IDX 2
#define mmDP0_DP_VID_N 0x2111
#define mmDP0_DP_VID_N_BASE_IDX 2
#define mmDP0_DP_VID_M 0x2112
#define mmDP0_DP_VID_M_BASE_IDX 2
#define mmDP0_DP_LINK_FRAMING_CNTL 0x2113
#define mmDP0_DP_LINK_FRAMING_CNTL_BASE_IDX 2
#define mmDP0_DP_HBR2_EYE_PATTERN 0x2114
#define mmDP0_DP_HBR2_EYE_PATTERN_BASE_IDX 2
#define mmDP0_DP_VID_MSA_VBID 0x2115
#define mmDP0_DP_VID_MSA_VBID_BASE_IDX 2
#define mmDP0_DP_VID_INTERRUPT_CNTL 0x2116
#define mmDP0_DP_VID_INTERRUPT_CNTL_BASE_IDX 2
#define mmDP0_DP_DPHY_CNTL 0x2117
#define mmDP0_DP_DPHY_CNTL_BASE_IDX 2
#define mmDP0_DP_DPHY_TRAINING_PATTERN_SEL 0x2118
#define mmDP0_DP_DPHY_TRAINING_PATTERN_SEL_BASE_IDX 2
#define mmDP0_DP_DPHY_SYM0 0x2119
#define mmDP0_DP_DPHY_SYM0_BASE_IDX 2
#define mmDP0_DP_DPHY_SYM1 0x211a
#define mmDP0_DP_DPHY_SYM1_BASE_IDX 2
#define mmDP0_DP_DPHY_SYM2 0x211b
#define mmDP0_DP_DPHY_SYM2_BASE_IDX 2
#define mmDP0_DP_DPHY_8B10B_CNTL 0x211c
#define mmDP0_DP_DPHY_8B10B_CNTL_BASE_IDX 2
#define mmDP0_DP_DPHY_PRBS_CNTL 0x211d
#define mmDP0_DP_DPHY_PRBS_CNTL_BASE_IDX 2
#define mmDP0_DP_DPHY_SCRAM_CNTL 0x211e
#define mmDP0_DP_DPHY_SCRAM_CNTL_BASE_IDX 2
#define mmDP0_DP_DPHY_CRC_EN 0x211f
#define mmDP0_DP_DPHY_CRC_EN_BASE_IDX 2
#define mmDP0_DP_DPHY_CRC_CNTL 0x2120
#define mmDP0_DP_DPHY_CRC_CNTL_BASE_IDX 2
#define mmDP0_DP_DPHY_CRC_RESULT 0x2121
#define mmDP0_DP_DPHY_CRC_RESULT_BASE_IDX 2
#define mmDP0_DP_DPHY_CRC_MST_CNTL 0x2122
#define mmDP0_DP_DPHY_CRC_MST_CNTL_BASE_IDX 2
#define mmDP0_DP_DPHY_CRC_MST_STATUS 0x2123
#define mmDP0_DP_DPHY_CRC_MST_STATUS_BASE_IDX 2
#define mmDP0_DP_DPHY_FAST_TRAINING 0x2124
#define mmDP0_DP_DPHY_FAST_TRAINING_BASE_IDX 2
#define mmDP0_DP_DPHY_FAST_TRAINING_STATUS 0x2125
#define mmDP0_DP_DPHY_FAST_TRAINING_STATUS_BASE_IDX 2
#define mmDP0_DP_SEC_CNTL 0x212b
#define mmDP0_DP_SEC_CNTL_BASE_IDX 2
#define mmDP0_DP_SEC_CNTL1 0x212c
#define mmDP0_DP_SEC_CNTL1_BASE_IDX 2
#define mmDP0_DP_SEC_FRAMING1 0x212d
#define mmDP0_DP_SEC_FRAMING1_BASE_IDX 2
#define mmDP0_DP_SEC_FRAMING2 0x212e
#define mmDP0_DP_SEC_FRAMING2_BASE_IDX 2
#define mmDP0_DP_SEC_FRAMING3 0x212f
#define mmDP0_DP_SEC_FRAMING3_BASE_IDX 2
#define mmDP0_DP_SEC_FRAMING4 0x2130
#define mmDP0_DP_SEC_FRAMING4_BASE_IDX 2
#define mmDP0_DP_SEC_AUD_N 0x2131
#define mmDP0_DP_SEC_AUD_N_BASE_IDX 2
#define mmDP0_DP_SEC_AUD_N_READBACK 0x2132
#define mmDP0_DP_SEC_AUD_N_READBACK_BASE_IDX 2
#define mmDP0_DP_SEC_AUD_M 0x2133
#define mmDP0_DP_SEC_AUD_M_BASE_IDX 2
#define mmDP0_DP_SEC_AUD_M_READBACK 0x2134
#define mmDP0_DP_SEC_AUD_M_READBACK_BASE_IDX 2
#define mmDP0_DP_SEC_TIMESTAMP 0x2135
#define mmDP0_DP_SEC_TIMESTAMP_BASE_IDX 2
#define mmDP0_DP_SEC_PACKET_CNTL 0x2136
#define mmDP0_DP_SEC_PACKET_CNTL_BASE_IDX 2
#define mmDP0_DP_MSE_RATE_CNTL 0x2137
#define mmDP0_DP_MSE_RATE_CNTL_BASE_IDX 2
#define mmDP0_DP_MSE_RATE_UPDATE 0x2139
#define mmDP0_DP_MSE_RATE_UPDATE_BASE_IDX 2
#define mmDP0_DP_MSE_SAT0 0x213a
#define mmDP0_DP_MSE_SAT0_BASE_IDX 2
#define mmDP0_DP_MSE_SAT1 0x213b
#define mmDP0_DP_MSE_SAT1_BASE_IDX 2
#define mmDP0_DP_MSE_SAT2 0x213c
#define mmDP0_DP_MSE_SAT2_BASE_IDX 2
#define mmDP0_DP_MSE_SAT_UPDATE 0x213d
#define mmDP0_DP_MSE_SAT_UPDATE_BASE_IDX 2
#define mmDP0_DP_MSE_LINK_TIMING 0x213e
#define mmDP0_DP_MSE_LINK_TIMING_BASE_IDX 2
#define mmDP0_DP_MSE_MISC_CNTL 0x213f
#define mmDP0_DP_MSE_MISC_CNTL_BASE_IDX 2
#define mmDP0_DP_DPHY_BS_SR_SWAP_CNTL 0x2144
#define mmDP0_DP_DPHY_BS_SR_SWAP_CNTL_BASE_IDX 2
#define mmDP0_DP_DPHY_HBR2_PATTERN_CONTROL 0x2145
#define mmDP0_DP_DPHY_HBR2_PATTERN_CONTROL_BASE_IDX 2
#define mmDP0_DP_MSE_SAT0_STATUS 0x2147
#define mmDP0_DP_MSE_SAT0_STATUS_BASE_IDX 2
#define mmDP0_DP_MSE_SAT1_STATUS 0x2148
#define mmDP0_DP_MSE_SAT1_STATUS_BASE_IDX 2
#define mmDP0_DP_MSE_SAT2_STATUS 0x2149
#define mmDP0_DP_MSE_SAT2_STATUS_BASE_IDX 2
#define mmDP0_DP_MSA_TIMING_PARAM1 0x214c
#define mmDP0_DP_MSA_TIMING_PARAM1_BASE_IDX 2
#define mmDP0_DP_MSA_TIMING_PARAM2 0x214d
#define mmDP0_DP_MSA_TIMING_PARAM2_BASE_IDX 2
#define mmDP0_DP_MSA_TIMING_PARAM3 0x214e
#define mmDP0_DP_MSA_TIMING_PARAM3_BASE_IDX 2
#define mmDP0_DP_MSA_TIMING_PARAM4 0x214f
#define mmDP0_DP_MSA_TIMING_PARAM4_BASE_IDX 2
#define mmDP0_DP_MSO_CNTL 0x2150
#define mmDP0_DP_MSO_CNTL_BASE_IDX 2
#define mmDP0_DP_MSO_CNTL1 0x2151
#define mmDP0_DP_MSO_CNTL1_BASE_IDX 2
#define mmDP0_DP_DSC_CNTL 0x2152
#define mmDP0_DP_DSC_CNTL_BASE_IDX 2
#define mmDP0_DP_SEC_CNTL2 0x2153
#define mmDP0_DP_SEC_CNTL2_BASE_IDX 2
#define mmDP0_DP_SEC_CNTL3 0x2154
#define mmDP0_DP_SEC_CNTL3_BASE_IDX 2
#define mmDP0_DP_SEC_CNTL4 0x2155
#define mmDP0_DP_SEC_CNTL4_BASE_IDX 2
#define mmDP0_DP_SEC_CNTL5 0x2156
#define mmDP0_DP_SEC_CNTL5_BASE_IDX 2
#define mmDP0_DP_SEC_CNTL6 0x2157
#define mmDP0_DP_SEC_CNTL6_BASE_IDX 2
#define mmDP0_DP_SEC_CNTL7 0x2158
#define mmDP0_DP_SEC_CNTL7_BASE_IDX 2
#define mmDP0_DP_DB_CNTL 0x2159
#define mmDP0_DP_DB_CNTL_BASE_IDX 2
#define mmDP0_DP_MSA_VBID_MISC 0x215a
#define mmDP0_DP_MSA_VBID_MISC_BASE_IDX 2
#define mmDP0_DP_SEC_METADATA_TRANSMISSION 0x215b
#define mmDP0_DP_SEC_METADATA_TRANSMISSION_BASE_IDX 2
#define mmDP0_DP_DSC_BYTES_PER_PIXEL 0x215c
#define mmDP0_DP_DSC_BYTES_PER_PIXEL_BASE_IDX 2
#define mmDP0_DP_ALPM_CNTL 0x215d
#define mmDP0_DP_ALPM_CNTL_BASE_IDX 2
#define mmDP0_DP_GSP8_CNTL 0x215e
#define mmDP0_DP_GSP8_CNTL_BASE_IDX 2
#define mmDP0_DP_GSP9_CNTL 0x215f
#define mmDP0_DP_GSP9_CNTL_BASE_IDX 2
#define mmDP0_DP_GSP10_CNTL 0x2160
#define mmDP0_DP_GSP10_CNTL_BASE_IDX 2
#define mmDP0_DP_GSP11_CNTL 0x2161
#define mmDP0_DP_GSP11_CNTL_BASE_IDX 2
#define mmDP0_DP_GSP_EN_DB_STATUS 0x2162
#define mmDP0_DP_GSP_EN_DB_STATUS_BASE_IDX 2
// addressBlock: dce_dc_dio_dig1_vpg_vpg_dispdec
// base address: 0x158a0
#define mmVPG1_VPG_GENERIC_PACKET_ACCESS_CTRL 0x2168
#define mmVPG1_VPG_GENERIC_PACKET_ACCESS_CTRL_BASE_IDX 2
#define mmVPG1_VPG_GENERIC_PACKET_DATA 0x2169
#define mmVPG1_VPG_GENERIC_PACKET_DATA_BASE_IDX 2
#define mmVPG1_VPG_GSP_FRAME_UPDATE_CTRL 0x216a
#define mmVPG1_VPG_GSP_FRAME_UPDATE_CTRL_BASE_IDX 2
#define mmVPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL 0x216b
#define mmVPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL_BASE_IDX 2
#define mmVPG1_VPG_GENERIC_STATUS 0x216c
#define mmVPG1_VPG_GENERIC_STATUS_BASE_IDX 2
#define mmVPG1_VPG_MEM_PWR 0x216d
#define mmVPG1_VPG_MEM_PWR_BASE_IDX 2
#define mmVPG1_VPG_ISRC1_2_ACCESS_CTRL 0x216e
#define mmVPG1_VPG_ISRC1_2_ACCESS_CTRL_BASE_IDX 2
#define mmVPG1_VPG_ISRC1_2_DATA 0x216f
#define mmVPG1_VPG_ISRC1_2_DATA_BASE_IDX 2
#define mmVPG1_VPG_MPEG_INFO0 0x2170
#define mmVPG1_VPG_MPEG_INFO0_BASE_IDX 2
#define mmVPG1_VPG_MPEG_INFO1 0x2171
#define mmVPG1_VPG_MPEG_INFO1_BASE_IDX 2
// addressBlock: dce_dc_dio_dig1_afmt_afmt_dispdec
// base address: 0x158cc
#define mmAFMT1_AFMT_VBI_PACKET_CONTROL 0x2174
#define mmAFMT1_AFMT_VBI_PACKET_CONTROL_BASE_IDX 2
#define mmAFMT1_AFMT_AUDIO_PACKET_CONTROL2 0x2175
#define mmAFMT1_AFMT_AUDIO_PACKET_CONTROL2_BASE_IDX 2
#define mmAFMT1_AFMT_AUDIO_INFO0 0x2176
#define mmAFMT1_AFMT_AUDIO_INFO0_BASE_IDX 2
#define mmAFMT1_AFMT_AUDIO_INFO1 0x2177
#define mmAFMT1_AFMT_AUDIO_INFO1_BASE_IDX 2
#define mmAFMT1_AFMT_60958_0 0x2178
#define mmAFMT1_AFMT_60958_0_BASE_IDX 2
#define mmAFMT1_AFMT_60958_1 0x2179
#define mmAFMT1_AFMT_60958_1_BASE_IDX 2
#define mmAFMT1_AFMT_AUDIO_CRC_CONTROL 0x217a
#define mmAFMT1_AFMT_AUDIO_CRC_CONTROL_BASE_IDX 2
#define mmAFMT1_AFMT_RAMP_CONTROL0 0x217b
#define mmAFMT1_AFMT_RAMP_CONTROL0_BASE_IDX 2
#define mmAFMT1_AFMT_RAMP_CONTROL1 0x217c
#define mmAFMT1_AFMT_RAMP_CONTROL1_BASE_IDX 2
#define mmAFMT1_AFMT_RAMP_CONTROL2 0x217d
#define mmAFMT1_AFMT_RAMP_CONTROL2_BASE_IDX 2
#define mmAFMT1_AFMT_RAMP_CONTROL3 0x217e
#define mmAFMT1_AFMT_RAMP_CONTROL3_BASE_IDX 2
#define mmAFMT1_AFMT_60958_2 0x217f
#define mmAFMT1_AFMT_60958_2_BASE_IDX 2
#define mmAFMT1_AFMT_AUDIO_CRC_RESULT 0x2180
#define mmAFMT1_AFMT_AUDIO_CRC_RESULT_BASE_IDX 2
#define mmAFMT1_AFMT_STATUS 0x2181
#define mmAFMT1_AFMT_STATUS_BASE_IDX 2
#define mmAFMT1_AFMT_AUDIO_PACKET_CONTROL 0x2182
#define mmAFMT1_AFMT_AUDIO_PACKET_CONTROL_BASE_IDX 2
#define mmAFMT1_AFMT_INFOFRAME_CONTROL0 0x2183
#define mmAFMT1_AFMT_INFOFRAME_CONTROL0_BASE_IDX 2
#define mmAFMT1_AFMT_INTERRUPT_STATUS 0x2184
#define mmAFMT1_AFMT_INTERRUPT_STATUS_BASE_IDX 2
#define mmAFMT1_AFMT_AUDIO_SRC_CONTROL 0x2185
#define mmAFMT1_AFMT_AUDIO_SRC_CONTROL_BASE_IDX 2
#define mmAFMT1_AFMT_MEM_PWR 0x2187
#define mmAFMT1_AFMT_MEM_PWR_BASE_IDX 2
// addressBlock: dce_dc_dio_dig1_dme_dme_dispdec
// base address: 0x15924
#define mmDME1_DME_CONTROL 0x2189
#define mmDME1_DME_CONTROL_BASE_IDX 2
#define mmDME1_DME_MEMORY_CONTROL 0x218a
#define mmDME1_DME_MEMORY_CONTROL_BASE_IDX 2
// addressBlock: dce_dc_dio_dig1_dispdec
// base address: 0x400
#define mmDIG1_DIG_FE_CNTL 0x218b
#define mmDIG1_DIG_FE_CNTL_BASE_IDX 2
#define mmDIG1_DIG_OUTPUT_CRC_CNTL 0x218c
#define mmDIG1_DIG_OUTPUT_CRC_CNTL_BASE_IDX 2
#define mmDIG1_DIG_OUTPUT_CRC_RESULT 0x218d
#define mmDIG1_DIG_OUTPUT_CRC_RESULT_BASE_IDX 2
#define mmDIG1_DIG_CLOCK_PATTERN 0x218e
#define mmDIG1_DIG_CLOCK_PATTERN_BASE_IDX 2
#define mmDIG1_DIG_TEST_PATTERN 0x218f
#define mmDIG1_DIG_TEST_PATTERN_BASE_IDX 2
#define mmDIG1_DIG_RANDOM_PATTERN_SEED 0x2190
#define mmDIG1_DIG_RANDOM_PATTERN_SEED_BASE_IDX 2
#define mmDIG1_DIG_FIFO_STATUS 0x2191
#define mmDIG1_DIG_FIFO_STATUS_BASE_IDX 2
#define mmDIG1_HDMI_METADATA_PACKET_CONTROL 0x2192
#define mmDIG1_HDMI_METADATA_PACKET_CONTROL_BASE_IDX 2
#define mmDIG1_HDMI_CONTROL 0x2193
#define mmDIG1_HDMI_CONTROL_BASE_IDX 2
#define mmDIG1_HDMI_STATUS 0x2194
#define mmDIG1_HDMI_STATUS_BASE_IDX 2
#define mmDIG1_HDMI_AUDIO_PACKET_CONTROL 0x2195
#define mmDIG1_HDMI_AUDIO_PACKET_CONTROL_BASE_IDX 2
#define mmDIG1_HDMI_ACR_PACKET_CONTROL 0x2196
#define mmDIG1_HDMI_ACR_PACKET_CONTROL_BASE_IDX 2
#define mmDIG1_HDMI_VBI_PACKET_CONTROL 0x2197
#define mmDIG1_HDMI_VBI_PACKET_CONTROL_BASE_IDX 2
#define mmDIG1_HDMI_INFOFRAME_CONTROL0 0x2198
#define mmDIG1_HDMI_INFOFRAME_CONTROL0_BASE_IDX 2
#define mmDIG1_HDMI_INFOFRAME_CONTROL1 0x2199
#define mmDIG1_HDMI_INFOFRAME_CONTROL1_BASE_IDX 2
#define mmDIG1_HDMI_GENERIC_PACKET_CONTROL0 0x219a
#define mmDIG1_HDMI_GENERIC_PACKET_CONTROL0_BASE_IDX 2
#define mmDIG1_HDMI_GENERIC_PACKET_CONTROL6 0x219b
#define mmDIG1_HDMI_GENERIC_PACKET_CONTROL6_BASE_IDX 2
#define mmDIG1_HDMI_GENERIC_PACKET_CONTROL5 0x219c
#define mmDIG1_HDMI_GENERIC_PACKET_CONTROL5_BASE_IDX 2
#define mmDIG1_HDMI_GC 0x219d
#define mmDIG1_HDMI_GC_BASE_IDX 2
#define mmDIG1_HDMI_GENERIC_PACKET_CONTROL1 0x219e
#define mmDIG1_HDMI_GENERIC_PACKET_CONTROL1_BASE_IDX 2
#define mmDIG1_HDMI_GENERIC_PACKET_CONTROL2 0x219f
#define mmDIG1_HDMI_GENERIC_PACKET_CONTROL2_BASE_IDX 2
#define mmDIG1_HDMI_GENERIC_PACKET_CONTROL3 0x21a0
#define mmDIG1_HDMI_GENERIC_PACKET_CONTROL3_BASE_IDX 2
#define mmDIG1_HDMI_GENERIC_PACKET_CONTROL4 0x21a1
#define mmDIG1_HDMI_GENERIC_PACKET_CONTROL4_BASE_IDX 2
#define mmDIG1_HDMI_GENERIC_PACKET_CONTROL7 0x21a2
#define mmDIG1_HDMI_GENERIC_PACKET_CONTROL7_BASE_IDX 2
#define mmDIG1_HDMI_GENERIC_PACKET_CONTROL8 0x21a3
#define mmDIG1_HDMI_GENERIC_PACKET_CONTROL8_BASE_IDX 2
#define mmDIG1_HDMI_GENERIC_PACKET_CONTROL9 0x21a4
#define mmDIG1_HDMI_GENERIC_PACKET_CONTROL9_BASE_IDX 2
#define mmDIG1_HDMI_GENERIC_PACKET_CONTROL10 0x21a5
#define mmDIG1_HDMI_GENERIC_PACKET_CONTROL10_BASE_IDX 2
#define mmDIG1_HDMI_DB_CONTROL 0x21a6
#define mmDIG1_HDMI_DB_CONTROL_BASE_IDX 2
#define mmDIG1_HDMI_ACR_32_0 0x21a7
#define mmDIG1_HDMI_ACR_32_0_BASE_IDX 2
#define mmDIG1_HDMI_ACR_32_1 0x21a8
#define mmDIG1_HDMI_ACR_32_1_BASE_IDX 2
#define mmDIG1_HDMI_ACR_44_0 0x21a9
#define mmDIG1_HDMI_ACR_44_0_BASE_IDX 2
#define mmDIG1_HDMI_ACR_44_1 0x21aa
#define mmDIG1_HDMI_ACR_44_1_BASE_IDX 2
#define mmDIG1_HDMI_ACR_48_0 0x21ab
#define mmDIG1_HDMI_ACR_48_0_BASE_IDX 2
#define mmDIG1_HDMI_ACR_48_1 0x21ac
#define mmDIG1_HDMI_ACR_48_1_BASE_IDX 2
#define mmDIG1_HDMI_ACR_STATUS_0 0x21ad
#define mmDIG1_HDMI_ACR_STATUS_0_BASE_IDX 2
#define mmDIG1_HDMI_ACR_STATUS_1 0x21ae
#define mmDIG1_HDMI_ACR_STATUS_1_BASE_IDX 2
#define mmDIG1_AFMT_CNTL 0x21af
#define mmDIG1_AFMT_CNTL_BASE_IDX 2
#define mmDIG1_DIG_BE_CNTL 0x21b0
#define mmDIG1_DIG_BE_CNTL_BASE_IDX 2
#define mmDIG1_DIG_BE_EN_CNTL 0x21b1
#define mmDIG1_DIG_BE_EN_CNTL_BASE_IDX 2
#define mmDIG1_TMDS_CNTL 0x21d7
#define mmDIG1_TMDS_CNTL_BASE_IDX 2
#define mmDIG1_TMDS_CONTROL_CHAR 0x21d8
#define mmDIG1_TMDS_CONTROL_CHAR_BASE_IDX 2
#define mmDIG1_TMDS_CONTROL0_FEEDBACK 0x21d9
#define mmDIG1_TMDS_CONTROL0_FEEDBACK_BASE_IDX 2
#define mmDIG1_TMDS_STEREOSYNC_CTL_SEL 0x21da
#define mmDIG1_TMDS_STEREOSYNC_CTL_SEL_BASE_IDX 2
#define mmDIG1_TMDS_SYNC_CHAR_PATTERN_0_1 0x21db
#define mmDIG1_TMDS_SYNC_CHAR_PATTERN_0_1_BASE_IDX 2
#define mmDIG1_TMDS_SYNC_CHAR_PATTERN_2_3 0x21dc
#define mmDIG1_TMDS_SYNC_CHAR_PATTERN_2_3_BASE_IDX 2
#define mmDIG1_TMDS_CTL_BITS 0x21de
#define mmDIG1_TMDS_CTL_BITS_BASE_IDX 2
#define mmDIG1_TMDS_DCBALANCER_CONTROL 0x21df
#define mmDIG1_TMDS_DCBALANCER_CONTROL_BASE_IDX 2
#define mmDIG1_TMDS_SYNC_DCBALANCE_CHAR 0x21e0
#define mmDIG1_TMDS_SYNC_DCBALANCE_CHAR_BASE_IDX 2
#define mmDIG1_TMDS_CTL0_1_GEN_CNTL 0x21e1
#define mmDIG1_TMDS_CTL0_1_GEN_CNTL_BASE_IDX 2
#define mmDIG1_TMDS_CTL2_3_GEN_CNTL 0x21e2
#define mmDIG1_TMDS_CTL2_3_GEN_CNTL_BASE_IDX 2
#define mmDIG1_DIG_VERSION 0x21e4
#define mmDIG1_DIG_VERSION_BASE_IDX 2
#define mmDIG1_DIG_LANE_ENABLE 0x21e5
#define mmDIG1_DIG_LANE_ENABLE_BASE_IDX 2
#define mmDIG1_FORCE_DIG_DISABLE 0x21e6
#define mmDIG1_FORCE_DIG_DISABLE_BASE_IDX 2
// addressBlock: dce_dc_dio_dp1_dispdec
// base address: 0x400
#define mmDP1_DP_LINK_CNTL 0x2208
#define mmDP1_DP_LINK_CNTL_BASE_IDX 2
#define mmDP1_DP_PIXEL_FORMAT 0x2209
#define mmDP1_DP_PIXEL_FORMAT_BASE_IDX 2
#define mmDP1_DP_MSA_COLORIMETRY 0x220a
#define mmDP1_DP_MSA_COLORIMETRY_BASE_IDX 2
#define mmDP1_DP_CONFIG 0x220b
#define mmDP1_DP_CONFIG_BASE_IDX 2
#define mmDP1_DP_VID_STREAM_CNTL 0x220c
#define mmDP1_DP_VID_STREAM_CNTL_BASE_IDX 2
#define mmDP1_DP_STEER_FIFO 0x220d
#define mmDP1_DP_STEER_FIFO_BASE_IDX 2
#define mmDP1_DP_MSA_MISC 0x220e
#define mmDP1_DP_MSA_MISC_BASE_IDX 2
#define mmDP1_DP_DPHY_INTERNAL_CTRL 0x220f
#define mmDP1_DP_DPHY_INTERNAL_CTRL_BASE_IDX 2
#define mmDP1_DP_VID_TIMING 0x2210
#define mmDP1_DP_VID_TIMING_BASE_IDX 2
#define mmDP1_DP_VID_N 0x2211
#define mmDP1_DP_VID_N_BASE_IDX 2
#define mmDP1_DP_VID_M 0x2212
#define mmDP1_DP_VID_M_BASE_IDX 2
#define mmDP1_DP_LINK_FRAMING_CNTL 0x2213
#define mmDP1_DP_LINK_FRAMING_CNTL_BASE_IDX 2
#define mmDP1_DP_HBR2_EYE_PATTERN 0x2214
#define mmDP1_DP_HBR2_EYE_PATTERN_BASE_IDX 2
#define mmDP1_DP_VID_MSA_VBID 0x2215
#define mmDP1_DP_VID_MSA_VBID_BASE_IDX 2
#define mmDP1_DP_VID_INTERRUPT_CNTL 0x2216
#define mmDP1_DP_VID_INTERRUPT_CNTL_BASE_IDX 2
#define mmDP1_DP_DPHY_CNTL 0x2217
#define mmDP1_DP_DPHY_CNTL_BASE_IDX 2
#define mmDP1_DP_DPHY_TRAINING_PATTERN_SEL 0x2218
#define mmDP1_DP_DPHY_TRAINING_PATTERN_SEL_BASE_IDX 2
#define mmDP1_DP_DPHY_SYM0 0x2219
#define mmDP1_DP_DPHY_SYM0_BASE_IDX 2
#define mmDP1_DP_DPHY_SYM1 0x221a
#define mmDP1_DP_DPHY_SYM1_BASE_IDX 2
#define mmDP1_DP_DPHY_SYM2 0x221b
#define mmDP1_DP_DPHY_SYM2_BASE_IDX 2
#define mmDP1_DP_DPHY_8B10B_CNTL 0x221c
#define mmDP1_DP_DPHY_8B10B_CNTL_BASE_IDX 2
#define mmDP1_DP_DPHY_PRBS_CNTL 0x221d
#define mmDP1_DP_DPHY_PRBS_CNTL_BASE_IDX 2
#define mmDP1_DP_DPHY_SCRAM_CNTL 0x221e
#define mmDP1_DP_DPHY_SCRAM_CNTL_BASE_IDX 2
#define mmDP1_DP_DPHY_CRC_EN 0x221f
#define mmDP1_DP_DPHY_CRC_EN_BASE_IDX 2
#define mmDP1_DP_DPHY_CRC_CNTL 0x2220
#define mmDP1_DP_DPHY_CRC_CNTL_BASE_IDX 2
#define mmDP1_DP_DPHY_CRC_RESULT 0x2221
#define mmDP1_DP_DPHY_CRC_RESULT_BASE_IDX 2
#define mmDP1_DP_DPHY_CRC_MST_CNTL 0x2222
#define mmDP1_DP_DPHY_CRC_MST_CNTL_BASE_IDX 2
#define mmDP1_DP_DPHY_CRC_MST_STATUS 0x2223
#define mmDP1_DP_DPHY_CRC_MST_STATUS_BASE_IDX 2
#define mmDP1_DP_DPHY_FAST_TRAINING 0x2224
#define mmDP1_DP_DPHY_FAST_TRAINING_BASE_IDX 2
#define mmDP1_DP_DPHY_FAST_TRAINING_STATUS 0x2225
#define mmDP1_DP_DPHY_FAST_TRAINING_STATUS_BASE_IDX 2
#define mmDP1_DP_SEC_CNTL 0x222b
#define mmDP1_DP_SEC_CNTL_BASE_IDX 2
#define mmDP1_DP_SEC_CNTL1 0x222c
#define mmDP1_DP_SEC_CNTL1_BASE_IDX 2
#define mmDP1_DP_SEC_FRAMING1 0x222d
#define mmDP1_DP_SEC_FRAMING1_BASE_IDX 2
#define mmDP1_DP_SEC_FRAMING2 0x222e
#define mmDP1_DP_SEC_FRAMING2_BASE_IDX 2
#define mmDP1_DP_SEC_FRAMING3 0x222f
#define mmDP1_DP_SEC_FRAMING3_BASE_IDX 2
#define mmDP1_DP_SEC_FRAMING4 0x2230
#define mmDP1_DP_SEC_FRAMING4_BASE_IDX 2
#define mmDP1_DP_SEC_AUD_N 0x2231
#define mmDP1_DP_SEC_AUD_N_BASE_IDX 2
#define mmDP1_DP_SEC_AUD_N_READBACK 0x2232
#define mmDP1_DP_SEC_AUD_N_READBACK_BASE_IDX 2
#define mmDP1_DP_SEC_AUD_M 0x2233
#define mmDP1_DP_SEC_AUD_M_BASE_IDX 2
#define mmDP1_DP_SEC_AUD_M_READBACK 0x2234
#define mmDP1_DP_SEC_AUD_M_READBACK_BASE_IDX 2
#define mmDP1_DP_SEC_TIMESTAMP 0x2235
#define mmDP1_DP_SEC_TIMESTAMP_BASE_IDX 2
#define mmDP1_DP_SEC_PACKET_CNTL 0x2236
#define mmDP1_DP_SEC_PACKET_CNTL_BASE_IDX 2
#define mmDP1_DP_MSE_RATE_CNTL 0x2237
#define mmDP1_DP_MSE_RATE_CNTL_BASE_IDX 2
#define mmDP1_DP_MSE_RATE_UPDATE 0x2239
#define mmDP1_DP_MSE_RATE_UPDATE_BASE_IDX 2
#define mmDP1_DP_MSE_SAT0 0x223a
#define mmDP1_DP_MSE_SAT0_BASE_IDX 2
#define mmDP1_DP_MSE_SAT1 0x223b
#define mmDP1_DP_MSE_SAT1_BASE_IDX 2
#define mmDP1_DP_MSE_SAT2 0x223c
#define mmDP1_DP_MSE_SAT2_BASE_IDX 2
#define mmDP1_DP_MSE_SAT_UPDATE 0x223d
#define mmDP1_DP_MSE_SAT_UPDATE_BASE_IDX 2
#define mmDP1_DP_MSE_LINK_TIMING 0x223e
#define mmDP1_DP_MSE_LINK_TIMING_BASE_IDX 2
#define mmDP1_DP_MSE_MISC_CNTL 0x223f
#define mmDP1_DP_MSE_MISC_CNTL_BASE_IDX 2
#define mmDP1_DP_DPHY_BS_SR_SWAP_CNTL 0x2244
#define mmDP1_DP_DPHY_BS_SR_SWAP_CNTL_BASE_IDX 2
#define mmDP1_DP_DPHY_HBR2_PATTERN_CONTROL 0x2245
#define mmDP1_DP_DPHY_HBR2_PATTERN_CONTROL_BASE_IDX 2
#define mmDP1_DP_MSE_SAT0_STATUS 0x2247
#define mmDP1_DP_MSE_SAT0_STATUS_BASE_IDX 2
#define mmDP1_DP_MSE_SAT1_STATUS 0x2248
#define mmDP1_DP_MSE_SAT1_STATUS_BASE_IDX 2
#define mmDP1_DP_MSE_SAT2_STATUS 0x2249
#define mmDP1_DP_MSE_SAT2_STATUS_BASE_IDX 2
#define mmDP1_DP_MSA_TIMING_PARAM1 0x224c
#define mmDP1_DP_MSA_TIMING_PARAM1_BASE_IDX 2
#define mmDP1_DP_MSA_TIMING_PARAM2 0x224d
#define mmDP1_DP_MSA_TIMING_PARAM2_BASE_IDX 2
#define mmDP1_DP_MSA_TIMING_PARAM3 0x224e
#define mmDP1_DP_MSA_TIMING_PARAM3_BASE_IDX 2
#define mmDP1_DP_MSA_TIMING_PARAM4 0x224f
#define mmDP1_DP_MSA_TIMING_PARAM4_BASE_IDX 2
#define mmDP1_DP_MSO_CNTL 0x2250
#define mmDP1_DP_MSO_CNTL_BASE_IDX 2
#define mmDP1_DP_MSO_CNTL1 0x2251
#define mmDP1_DP_MSO_CNTL1_BASE_IDX 2
#define mmDP1_DP_DSC_CNTL 0x2252
#define mmDP1_DP_DSC_CNTL_BASE_IDX 2
#define mmDP1_DP_SEC_CNTL2 0x2253
#define mmDP1_DP_SEC_CNTL2_BASE_IDX 2
#define mmDP1_DP_SEC_CNTL3 0x2254
#define mmDP1_DP_SEC_CNTL3_BASE_IDX 2
#define mmDP1_DP_SEC_CNTL4 0x2255
#define mmDP1_DP_SEC_CNTL4_BASE_IDX 2
#define mmDP1_DP_SEC_CNTL5 0x2256
#define mmDP1_DP_SEC_CNTL5_BASE_IDX 2
#define mmDP1_DP_SEC_CNTL6 0x2257
#define mmDP1_DP_SEC_CNTL6_BASE_IDX 2
#define mmDP1_DP_SEC_CNTL7 0x2258
#define mmDP1_DP_SEC_CNTL7_BASE_IDX 2
#define mmDP1_DP_DB_CNTL 0x2259
#define mmDP1_DP_DB_CNTL_BASE_IDX 2
#define mmDP1_DP_MSA_VBID_MISC 0x225a
#define mmDP1_DP_MSA_VBID_MISC_BASE_IDX 2
#define mmDP1_DP_SEC_METADATA_TRANSMISSION 0x225b
#define mmDP1_DP_SEC_METADATA_TRANSMISSION_BASE_IDX 2
#define mmDP1_DP_DSC_BYTES_PER_PIXEL 0x225c
#define mmDP1_DP_DSC_BYTES_PER_PIXEL_BASE_IDX 2
#define mmDP1_DP_ALPM_CNTL 0x225d
#define mmDP1_DP_ALPM_CNTL_BASE_IDX 2
#define mmDP1_DP_GSP8_CNTL 0x225e
#define mmDP1_DP_GSP8_CNTL_BASE_IDX 2
#define mmDP1_DP_GSP9_CNTL 0x225f
#define mmDP1_DP_GSP9_CNTL_BASE_IDX 2
#define mmDP1_DP_GSP10_CNTL 0x2260
#define mmDP1_DP_GSP10_CNTL_BASE_IDX 2
#define mmDP1_DP_GSP11_CNTL 0x2261
#define mmDP1_DP_GSP11_CNTL_BASE_IDX 2
#define mmDP1_DP_GSP_EN_DB_STATUS 0x2262
#define mmDP1_DP_GSP_EN_DB_STATUS_BASE_IDX 2
// addressBlock: dce_dc_dio_dig2_vpg_vpg_dispdec
// base address: 0x15ca0
#define mmVPG2_VPG_GENERIC_PACKET_ACCESS_CTRL 0x2268
#define mmVPG2_VPG_GENERIC_PACKET_ACCESS_CTRL_BASE_IDX 2
#define mmVPG2_VPG_GENERIC_PACKET_DATA 0x2269
#define mmVPG2_VPG_GENERIC_PACKET_DATA_BASE_IDX 2
#define mmVPG2_VPG_GSP_FRAME_UPDATE_CTRL 0x226a
#define mmVPG2_VPG_GSP_FRAME_UPDATE_CTRL_BASE_IDX 2
#define mmVPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL 0x226b
#define mmVPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL_BASE_IDX 2
#define mmVPG2_VPG_GENERIC_STATUS 0x226c
#define mmVPG2_VPG_GENERIC_STATUS_BASE_IDX 2
#define mmVPG2_VPG_MEM_PWR 0x226d
#define mmVPG2_VPG_MEM_PWR_BASE_IDX 2
#define mmVPG2_VPG_ISRC1_2_ACCESS_CTRL 0x226e
#define mmVPG2_VPG_ISRC1_2_ACCESS_CTRL_BASE_IDX 2
#define mmVPG2_VPG_ISRC1_2_DATA 0x226f
#define mmVPG2_VPG_ISRC1_2_DATA_BASE_IDX 2
#define mmVPG2_VPG_MPEG_INFO0 0x2270
#define mmVPG2_VPG_MPEG_INFO0_BASE_IDX 2
#define mmVPG2_VPG_MPEG_INFO1 0x2271
#define mmVPG2_VPG_MPEG_INFO1_BASE_IDX 2
// addressBlock: dce_dc_dio_dig2_afmt_afmt_dispdec
// base address: 0x15ccc
#define mmAFMT2_AFMT_VBI_PACKET_CONTROL 0x2274
#define mmAFMT2_AFMT_VBI_PACKET_CONTROL_BASE_IDX 2
#define mmAFMT2_AFMT_AUDIO_PACKET_CONTROL2 0x2275
#define mmAFMT2_AFMT_AUDIO_PACKET_CONTROL2_BASE_IDX 2
#define mmAFMT2_AFMT_AUDIO_INFO0 0x2276
#define mmAFMT2_AFMT_AUDIO_INFO0_BASE_IDX 2
#define mmAFMT2_AFMT_AUDIO_INFO1 0x2277
#define mmAFMT2_AFMT_AUDIO_INFO1_BASE_IDX 2
#define mmAFMT2_AFMT_60958_0 0x2278
#define mmAFMT2_AFMT_60958_0_BASE_IDX 2
#define mmAFMT2_AFMT_60958_1 0x2279
#define mmAFMT2_AFMT_60958_1_BASE_IDX 2
#define mmAFMT2_AFMT_AUDIO_CRC_CONTROL 0x227a
#define mmAFMT2_AFMT_AUDIO_CRC_CONTROL_BASE_IDX 2
#define mmAFMT2_AFMT_RAMP_CONTROL0 0x227b
#define mmAFMT2_AFMT_RAMP_CONTROL0_BASE_IDX 2
#define mmAFMT2_AFMT_RAMP_CONTROL1 0x227c
#define mmAFMT2_AFMT_RAMP_CONTROL1_BASE_IDX 2
#define mmAFMT2_AFMT_RAMP_CONTROL2 0x227d
#define mmAFMT2_AFMT_RAMP_CONTROL2_BASE_IDX 2
#define mmAFMT2_AFMT_RAMP_CONTROL3 0x227e
#define mmAFMT2_AFMT_RAMP_CONTROL3_BASE_IDX 2
#define mmAFMT2_AFMT_60958_2 0x227f
#define mmAFMT2_AFMT_60958_2_BASE_IDX 2
#define mmAFMT2_AFMT_AUDIO_CRC_RESULT 0x2280
#define mmAFMT2_AFMT_AUDIO_CRC_RESULT_BASE_IDX 2
#define mmAFMT2_AFMT_STATUS 0x2281
#define mmAFMT2_AFMT_STATUS_BASE_IDX 2
#define mmAFMT2_AFMT_AUDIO_PACKET_CONTROL 0x2282
#define mmAFMT2_AFMT_AUDIO_PACKET_CONTROL_BASE_IDX 2
#define mmAFMT2_AFMT_INFOFRAME_CONTROL0 0x2283
#define mmAFMT2_AFMT_INFOFRAME_CONTROL0_BASE_IDX 2
#define mmAFMT2_AFMT_INTERRUPT_STATUS 0x2284
#define mmAFMT2_AFMT_INTERRUPT_STATUS_BASE_IDX 2
#define mmAFMT2_AFMT_AUDIO_SRC_CONTROL 0x2285
#define mmAFMT2_AFMT_AUDIO_SRC_CONTROL_BASE_IDX 2
#define mmAFMT2_AFMT_MEM_PWR 0x2287
#define mmAFMT2_AFMT_MEM_PWR_BASE_IDX 2
// addressBlock: dce_dc_dio_dig2_dme_dme_dispdec
// base address: 0x15d24
#define mmDME2_DME_CONTROL 0x2289
#define mmDME2_DME_CONTROL_BASE_IDX 2
#define mmDME2_DME_MEMORY_CONTROL 0x228a
#define mmDME2_DME_MEMORY_CONTROL_BASE_IDX 2
// addressBlock: dce_dc_dio_dig2_dispdec
// base address: 0x800
#define mmDIG2_DIG_FE_CNTL 0x228b
#define mmDIG2_DIG_FE_CNTL_BASE_IDX 2
#define mmDIG2_DIG_OUTPUT_CRC_CNTL 0x228c
#define mmDIG2_DIG_OUTPUT_CRC_CNTL_BASE_IDX 2
#define mmDIG2_DIG_OUTPUT_CRC_RESULT 0x228d
#define mmDIG2_DIG_OUTPUT_CRC_RESULT_BASE_IDX 2
#define mmDIG2_DIG_CLOCK_PATTERN 0x228e
#define mmDIG2_DIG_CLOCK_PATTERN_BASE_IDX 2
#define mmDIG2_DIG_TEST_PATTERN 0x228f
#define mmDIG2_DIG_TEST_PATTERN_BASE_IDX 2
#define mmDIG2_DIG_RANDOM_PATTERN_SEED 0x2290
#define mmDIG2_DIG_RANDOM_PATTERN_SEED_BASE_IDX 2
#define mmDIG2_DIG_FIFO_STATUS 0x2291
#define mmDIG2_DIG_FIFO_STATUS_BASE_IDX 2
#define mmDIG2_HDMI_METADATA_PACKET_CONTROL 0x2292
#define mmDIG2_HDMI_METADATA_PACKET_CONTROL_BASE_IDX 2
#define mmDIG2_HDMI_CONTROL 0x2293
#define mmDIG2_HDMI_CONTROL_BASE_IDX 2
#define mmDIG2_HDMI_STATUS 0x2294
#define mmDIG2_HDMI_STATUS_BASE_IDX 2
#define mmDIG2_HDMI_AUDIO_PACKET_CONTROL 0x2295
#define mmDIG2_HDMI_AUDIO_PACKET_CONTROL_BASE_IDX 2
#define mmDIG2_HDMI_ACR_PACKET_CONTROL 0x2296
#define mmDIG2_HDMI_ACR_PACKET_CONTROL_BASE_IDX 2
#define mmDIG2_HDMI_VBI_PACKET_CONTROL 0x2297
#define mmDIG2_HDMI_VBI_PACKET_CONTROL_BASE_IDX 2
#define mmDIG2_HDMI_INFOFRAME_CONTROL0 0x2298
#define mmDIG2_HDMI_INFOFRAME_CONTROL0_BASE_IDX 2
#define mmDIG2_HDMI_INFOFRAME_CONTROL1 0x2299
#define mmDIG2_HDMI_INFOFRAME_CONTROL1_BASE_IDX 2
#define mmDIG2_HDMI_GENERIC_PACKET_CONTROL0 0x229a
#define mmDIG2_HDMI_GENERIC_PACKET_CONTROL0_BASE_IDX 2
#define mmDIG2_HDMI_GENERIC_PACKET_CONTROL6 0x229b
#define mmDIG2_HDMI_GENERIC_PACKET_CONTROL6_BASE_IDX 2
#define mmDIG2_HDMI_GENERIC_PACKET_CONTROL5 0x229c
#define mmDIG2_HDMI_GENERIC_PACKET_CONTROL5_BASE_IDX 2
#define mmDIG2_HDMI_GC 0x229d
#define mmDIG2_HDMI_GC_BASE_IDX 2
#define mmDIG2_HDMI_GENERIC_PACKET_CONTROL1 0x229e
#define mmDIG2_HDMI_GENERIC_PACKET_CONTROL1_BASE_IDX 2
#define mmDIG2_HDMI_GENERIC_PACKET_CONTROL2 0x229f
#define mmDIG2_HDMI_GENERIC_PACKET_CONTROL2_BASE_IDX 2
#define mmDIG2_HDMI_GENERIC_PACKET_CONTROL3 0x22a0
#define mmDIG2_HDMI_GENERIC_PACKET_CONTROL3_BASE_IDX 2
#define mmDIG2_HDMI_GENERIC_PACKET_CONTROL4 0x22a1
#define mmDIG2_HDMI_GENERIC_PACKET_CONTROL4_BASE_IDX 2
#define mmDIG2_HDMI_GENERIC_PACKET_CONTROL7 0x22a2
#define mmDIG2_HDMI_GENERIC_PACKET_CONTROL7_BASE_IDX 2
#define mmDIG2_HDMI_GENERIC_PACKET_CONTROL8 0x22a3
#define mmDIG2_HDMI_GENERIC_PACKET_CONTROL8_BASE_IDX 2
#define mmDIG2_HDMI_GENERIC_PACKET_CONTROL9 0x22a4
#define mmDIG2_HDMI_GENERIC_PACKET_CONTROL9_BASE_IDX 2
#define mmDIG2_HDMI_GENERIC_PACKET_CONTROL10 0x22a5
#define mmDIG2_HDMI_GENERIC_PACKET_CONTROL10_BASE_IDX 2
#define mmDIG2_HDMI_DB_CONTROL 0x22a6
#define mmDIG2_HDMI_DB_CONTROL_BASE_IDX 2
#define mmDIG2_HDMI_ACR_32_0 0x22a7
#define mmDIG2_HDMI_ACR_32_0_BASE_IDX 2
#define mmDIG2_HDMI_ACR_32_1 0x22a8
#define mmDIG2_HDMI_ACR_32_1_BASE_IDX 2
#define mmDIG2_HDMI_ACR_44_0 0x22a9
#define mmDIG2_HDMI_ACR_44_0_BASE_IDX 2
#define mmDIG2_HDMI_ACR_44_1 0x22aa
#define mmDIG2_HDMI_ACR_44_1_BASE_IDX 2
#define mmDIG2_HDMI_ACR_48_0 0x22ab
#define mmDIG2_HDMI_ACR_48_0_BASE_IDX 2
#define mmDIG2_HDMI_ACR_48_1 0x22ac
#define mmDIG2_HDMI_ACR_48_1_BASE_IDX 2
#define mmDIG2_HDMI_ACR_STATUS_0 0x22ad
#define mmDIG2_HDMI_ACR_STATUS_0_BASE_IDX 2
#define mmDIG2_HDMI_ACR_STATUS_1 0x22ae
#define mmDIG2_HDMI_ACR_STATUS_1_BASE_IDX 2
#define mmDIG2_AFMT_CNTL 0x22af
#define mmDIG2_AFMT_CNTL_BASE_IDX 2
#define mmDIG2_DIG_BE_CNTL 0x22b0
#define mmDIG2_DIG_BE_CNTL_BASE_IDX 2
#define mmDIG2_DIG_BE_EN_CNTL 0x22b1
#define mmDIG2_DIG_BE_EN_CNTL_BASE_IDX 2
#define mmDIG2_TMDS_CNTL 0x22d7
#define mmDIG2_TMDS_CNTL_BASE_IDX 2
#define mmDIG2_TMDS_CONTROL_CHAR 0x22d8
#define mmDIG2_TMDS_CONTROL_CHAR_BASE_IDX 2
#define mmDIG2_TMDS_CONTROL0_FEEDBACK 0x22d9
#define mmDIG2_TMDS_CONTROL0_FEEDBACK_BASE_IDX 2
#define mmDIG2_TMDS_STEREOSYNC_CTL_SEL 0x22da
#define mmDIG2_TMDS_STEREOSYNC_CTL_SEL_BASE_IDX 2
#define mmDIG2_TMDS_SYNC_CHAR_PATTERN_0_1 0x22db
#define mmDIG2_TMDS_SYNC_CHAR_PATTERN_0_1_BASE_IDX 2
#define mmDIG2_TMDS_SYNC_CHAR_PATTERN_2_3 0x22dc
#define mmDIG2_TMDS_SYNC_CHAR_PATTERN_2_3_BASE_IDX 2
#define mmDIG2_TMDS_CTL_BITS 0x22de
#define mmDIG2_TMDS_CTL_BITS_BASE_IDX 2
#define mmDIG2_TMDS_DCBALANCER_CONTROL 0x22df
#define mmDIG2_TMDS_DCBALANCER_CONTROL_BASE_IDX 2
#define mmDIG2_TMDS_SYNC_DCBALANCE_CHAR 0x22e0
#define mmDIG2_TMDS_SYNC_DCBALANCE_CHAR_BASE_IDX 2
#define mmDIG2_TMDS_CTL0_1_GEN_CNTL 0x22e1
#define mmDIG2_TMDS_CTL0_1_GEN_CNTL_BASE_IDX 2
#define mmDIG2_TMDS_CTL2_3_GEN_CNTL 0x22e2
#define mmDIG2_TMDS_CTL2_3_GEN_CNTL_BASE_IDX 2
#define mmDIG2_DIG_VERSION 0x22e4
#define mmDIG2_DIG_VERSION_BASE_IDX 2
#define mmDIG2_DIG_LANE_ENABLE 0x22e5
#define mmDIG2_DIG_LANE_ENABLE_BASE_IDX 2
#define mmDIG2_FORCE_DIG_DISABLE 0x22e6
#define mmDIG2_FORCE_DIG_DISABLE_BASE_IDX 2
// addressBlock: dce_dc_dio_dp2_dispdec
// base address: 0x800
#define mmDP2_DP_LINK_CNTL 0x2308
#define mmDP2_DP_LINK_CNTL_BASE_IDX 2
#define mmDP2_DP_PIXEL_FORMAT 0x2309
#define mmDP2_DP_PIXEL_FORMAT_BASE_IDX 2
#define mmDP2_DP_MSA_COLORIMETRY 0x230a
#define mmDP2_DP_MSA_COLORIMETRY_BASE_IDX 2
#define mmDP2_DP_CONFIG 0x230b
#define mmDP2_DP_CONFIG_BASE_IDX 2
#define mmDP2_DP_VID_STREAM_CNTL 0x230c
#define mmDP2_DP_VID_STREAM_CNTL_BASE_IDX 2
#define mmDP2_DP_STEER_FIFO 0x230d
#define mmDP2_DP_STEER_FIFO_BASE_IDX 2
#define mmDP2_DP_MSA_MISC 0x230e
#define mmDP2_DP_MSA_MISC_BASE_IDX 2
#define mmDP2_DP_DPHY_INTERNAL_CTRL 0x230f
#define mmDP2_DP_DPHY_INTERNAL_CTRL_BASE_IDX 2
#define mmDP2_DP_VID_TIMING 0x2310
#define mmDP2_DP_VID_TIMING_BASE_IDX 2
#define mmDP2_DP_VID_N 0x2311
#define mmDP2_DP_VID_N_BASE_IDX 2
#define mmDP2_DP_VID_M 0x2312
#define mmDP2_DP_VID_M_BASE_IDX 2
#define mmDP2_DP_LINK_FRAMING_CNTL 0x2313
#define mmDP2_DP_LINK_FRAMING_CNTL_BASE_IDX 2
#define mmDP2_DP_HBR2_EYE_PATTERN 0x2314
#define mmDP2_DP_HBR2_EYE_PATTERN_BASE_IDX 2
#define mmDP2_DP_VID_MSA_VBID 0x2315
#define mmDP2_DP_VID_MSA_VBID_BASE_IDX 2
#define mmDP2_DP_VID_INTERRUPT_CNTL 0x2316
#define mmDP2_DP_VID_INTERRUPT_CNTL_BASE_IDX 2
#define mmDP2_DP_DPHY_CNTL 0x2317
#define mmDP2_DP_DPHY_CNTL_BASE_IDX 2
#define mmDP2_DP_DPHY_TRAINING_PATTERN_SEL 0x2318
#define mmDP2_DP_DPHY_TRAINING_PATTERN_SEL_BASE_IDX 2
#define mmDP2_DP_DPHY_SYM0 0x2319
#define mmDP2_DP_DPHY_SYM0_BASE_IDX 2
#define mmDP2_DP_DPHY_SYM1 0x231a
#define mmDP2_DP_DPHY_SYM1_BASE_IDX 2
#define mmDP2_DP_DPHY_SYM2 0x231b
#define mmDP2_DP_DPHY_SYM2_BASE_IDX 2
#define mmDP2_DP_DPHY_8B10B_CNTL 0x231c
#define mmDP2_DP_DPHY_8B10B_CNTL_BASE_IDX 2
#define mmDP2_DP_DPHY_PRBS_CNTL 0x231d
#define mmDP2_DP_DPHY_PRBS_CNTL_BASE_IDX 2
#define mmDP2_DP_DPHY_SCRAM_CNTL 0x231e
#define mmDP2_DP_DPHY_SCRAM_CNTL_BASE_IDX 2
#define mmDP2_DP_DPHY_CRC_EN 0x231f
#define mmDP2_DP_DPHY_CRC_EN_BASE_IDX 2
#define mmDP2_DP_DPHY_CRC_CNTL 0x2320
#define mmDP2_DP_DPHY_CRC_CNTL_BASE_IDX 2
#define mmDP2_DP_DPHY_CRC_RESULT 0x2321
#define mmDP2_DP_DPHY_CRC_RESULT_BASE_IDX 2
#define mmDP2_DP_DPHY_CRC_MST_CNTL 0x2322
#define mmDP2_DP_DPHY_CRC_MST_CNTL_BASE_IDX 2
#define mmDP2_DP_DPHY_CRC_MST_STATUS 0x2323
#define mmDP2_DP_DPHY_CRC_MST_STATUS_BASE_IDX 2
#define mmDP2_DP_DPHY_FAST_TRAINING 0x2324
#define mmDP2_DP_DPHY_FAST_TRAINING_BASE_IDX 2
#define mmDP2_DP_DPHY_FAST_TRAINING_STATUS 0x2325
#define mmDP2_DP_DPHY_FAST_TRAINING_STATUS_BASE_IDX 2
#define mmDP2_DP_SEC_CNTL 0x232b
#define mmDP2_DP_SEC_CNTL_BASE_IDX 2
#define mmDP2_DP_SEC_CNTL1 0x232c
#define mmDP2_DP_SEC_CNTL1_BASE_IDX 2
#define mmDP2_DP_SEC_FRAMING1 0x232d
#define mmDP2_DP_SEC_FRAMING1_BASE_IDX 2
#define mmDP2_DP_SEC_FRAMING2 0x232e
#define mmDP2_DP_SEC_FRAMING2_BASE_IDX 2
#define mmDP2_DP_SEC_FRAMING3 0x232f
#define mmDP2_DP_SEC_FRAMING3_BASE_IDX 2
#define mmDP2_DP_SEC_FRAMING4 0x2330
#define mmDP2_DP_SEC_FRAMING4_BASE_IDX 2
#define mmDP2_DP_SEC_AUD_N 0x2331
#define mmDP2_DP_SEC_AUD_N_BASE_IDX 2
#define mmDP2_DP_SEC_AUD_N_READBACK 0x2332
#define mmDP2_DP_SEC_AUD_N_READBACK_BASE_IDX 2
#define mmDP2_DP_SEC_AUD_M 0x2333
#define mmDP2_DP_SEC_AUD_M_BASE_IDX 2
#define mmDP2_DP_SEC_AUD_M_READBACK 0x2334
#define mmDP2_DP_SEC_AUD_M_READBACK_BASE_IDX 2
#define mmDP2_DP_SEC_TIMESTAMP 0x2335
#define mmDP2_DP_SEC_TIMESTAMP_BASE_IDX 2
#define mmDP2_DP_SEC_PACKET_CNTL 0x2336
#define mmDP2_DP_SEC_PACKET_CNTL_BASE_IDX 2
#define mmDP2_DP_MSE_RATE_CNTL 0x2337
#define mmDP2_DP_MSE_RATE_CNTL_BASE_IDX 2
#define mmDP2_DP_MSE_RATE_UPDATE 0x2339
#define mmDP2_DP_MSE_RATE_UPDATE_BASE_IDX 2
#define mmDP2_DP_MSE_SAT0 0x233a
#define mmDP2_DP_MSE_SAT0_BASE_IDX 2
#define mmDP2_DP_MSE_SAT1 0x233b
#define mmDP2_DP_MSE_SAT1_BASE_IDX 2
#define mmDP2_DP_MSE_SAT2 0x233c
#define mmDP2_DP_MSE_SAT2_BASE_IDX 2
#define mmDP2_DP_MSE_SAT_UPDATE 0x233d
#define mmDP2_DP_MSE_SAT_UPDATE_BASE_IDX 2
#define mmDP2_DP_MSE_LINK_TIMING 0x233e
#define mmDP2_DP_MSE_LINK_TIMING_BASE_IDX 2
#define mmDP2_DP_MSE_MISC_CNTL 0x233f
#define mmDP2_DP_MSE_MISC_CNTL_BASE_IDX 2
#define mmDP2_DP_DPHY_BS_SR_SWAP_CNTL 0x2344
#define mmDP2_DP_DPHY_BS_SR_SWAP_CNTL_BASE_IDX 2
#define mmDP2_DP_DPHY_HBR2_PATTERN_CONTROL 0x2345
#define mmDP2_DP_DPHY_HBR2_PATTERN_CONTROL_BASE_IDX 2
#define mmDP2_DP_MSE_SAT0_STATUS 0x2347
#define mmDP2_DP_MSE_SAT0_STATUS_BASE_IDX 2
#define mmDP2_DP_MSE_SAT1_STATUS 0x2348
#define mmDP2_DP_MSE_SAT1_STATUS_BASE_IDX 2
#define mmDP2_DP_MSE_SAT2_STATUS 0x2349
#define mmDP2_DP_MSE_SAT2_STATUS_BASE_IDX 2
#define mmDP2_DP_MSA_TIMING_PARAM1 0x234c
#define mmDP2_DP_MSA_TIMING_PARAM1_BASE_IDX 2
#define mmDP2_DP_MSA_TIMING_PARAM2 0x234d
#define mmDP2_DP_MSA_TIMING_PARAM2_BASE_IDX 2
#define mmDP2_DP_MSA_TIMING_PARAM3 0x234e
#define mmDP2_DP_MSA_TIMING_PARAM3_BASE_IDX 2
#define mmDP2_DP_MSA_TIMING_PARAM4 0x234f
#define mmDP2_DP_MSA_TIMING_PARAM4_BASE_IDX 2
#define mmDP2_DP_MSO_CNTL 0x2350
#define mmDP2_DP_MSO_CNTL_BASE_IDX 2
#define mmDP2_DP_MSO_CNTL1 0x2351
#define mmDP2_DP_MSO_CNTL1_BASE_IDX 2
#define mmDP2_DP_DSC_CNTL 0x2352
#define mmDP2_DP_DSC_CNTL_BASE_IDX 2
#define mmDP2_DP_SEC_CNTL2 0x2353
#define mmDP2_DP_SEC_CNTL2_BASE_IDX 2
#define mmDP2_DP_SEC_CNTL3 0x2354
#define mmDP2_DP_SEC_CNTL3_BASE_IDX 2
#define mmDP2_DP_SEC_CNTL4 0x2355
#define mmDP2_DP_SEC_CNTL4_BASE_IDX 2
#define mmDP2_DP_SEC_CNTL5 0x2356
#define mmDP2_DP_SEC_CNTL5_BASE_IDX 2
#define mmDP2_DP_SEC_CNTL6 0x2357
#define mmDP2_DP_SEC_CNTL6_BASE_IDX 2
#define mmDP2_DP_SEC_CNTL7 0x2358
#define mmDP2_DP_SEC_CNTL7_BASE_IDX 2
#define mmDP2_DP_DB_CNTL 0x2359
#define mmDP2_DP_DB_CNTL_BASE_IDX 2
#define mmDP2_DP_MSA_VBID_MISC 0x235a
#define mmDP2_DP_MSA_VBID_MISC_BASE_IDX 2
#define mmDP2_DP_SEC_METADATA_TRANSMISSION 0x235b
#define mmDP2_DP_SEC_METADATA_TRANSMISSION_BASE_IDX 2
#define mmDP2_DP_DSC_BYTES_PER_PIXEL 0x235c
#define mmDP2_DP_DSC_BYTES_PER_PIXEL_BASE_IDX 2
#define mmDP2_DP_ALPM_CNTL 0x235d
#define mmDP2_DP_ALPM_CNTL_BASE_IDX 2
#define mmDP2_DP_GSP8_CNTL 0x235e
#define mmDP2_DP_GSP8_CNTL_BASE_IDX 2
#define mmDP2_DP_GSP9_CNTL 0x235f
#define mmDP2_DP_GSP9_CNTL_BASE_IDX 2
#define mmDP2_DP_GSP10_CNTL 0x2360
#define mmDP2_DP_GSP10_CNTL_BASE_IDX 2
#define mmDP2_DP_GSP11_CNTL 0x2361
#define mmDP2_DP_GSP11_CNTL_BASE_IDX 2
#define mmDP2_DP_GSP_EN_DB_STATUS 0x2362
#define mmDP2_DP_GSP_EN_DB_STATUS_BASE_IDX 2
// addressBlock: dce_dc_dio_dig3_vpg_vpg_dispdec
// base address: 0x160a0
#define mmVPG3_VPG_GENERIC_PACKET_ACCESS_CTRL 0x2368
#define mmVPG3_VPG_GENERIC_PACKET_ACCESS_CTRL_BASE_IDX 2
#define mmVPG3_VPG_GENERIC_PACKET_DATA 0x2369
#define mmVPG3_VPG_GENERIC_PACKET_DATA_BASE_IDX 2
#define mmVPG3_VPG_GSP_FRAME_UPDATE_CTRL 0x236a
#define mmVPG3_VPG_GSP_FRAME_UPDATE_CTRL_BASE_IDX 2
#define mmVPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL 0x236b
#define mmVPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL_BASE_IDX 2
#define mmVPG3_VPG_GENERIC_STATUS 0x236c
#define mmVPG3_VPG_GENERIC_STATUS_BASE_IDX 2
#define mmVPG3_VPG_MEM_PWR 0x236d
#define mmVPG3_VPG_MEM_PWR_BASE_IDX 2
#define mmVPG3_VPG_ISRC1_2_ACCESS_CTRL 0x236e
#define mmVPG3_VPG_ISRC1_2_ACCESS_CTRL_BASE_IDX 2
#define mmVPG3_VPG_ISRC1_2_DATA 0x236f
#define mmVPG3_VPG_ISRC1_2_DATA_BASE_IDX 2
#define mmVPG3_VPG_MPEG_INFO0 0x2370
#define mmVPG3_VPG_MPEG_INFO0_BASE_IDX 2
#define mmVPG3_VPG_MPEG_INFO1 0x2371
#define mmVPG3_VPG_MPEG_INFO1_BASE_IDX 2
// addressBlock: dce_dc_dio_dig3_afmt_afmt_dispdec
// base address: 0x160cc
#define mmAFMT3_AFMT_VBI_PACKET_CONTROL 0x2374
#define mmAFMT3_AFMT_VBI_PACKET_CONTROL_BASE_IDX 2
#define mmAFMT3_AFMT_AUDIO_PACKET_CONTROL2 0x2375
#define mmAFMT3_AFMT_AUDIO_PACKET_CONTROL2_BASE_IDX 2
#define mmAFMT3_AFMT_AUDIO_INFO0 0x2376
#define mmAFMT3_AFMT_AUDIO_INFO0_BASE_IDX 2
#define mmAFMT3_AFMT_AUDIO_INFO1 0x2377
#define mmAFMT3_AFMT_AUDIO_INFO1_BASE_IDX 2
#define mmAFMT3_AFMT_60958_0 0x2378
#define mmAFMT3_AFMT_60958_0_BASE_IDX 2
#define mmAFMT3_AFMT_60958_1 0x2379
#define mmAFMT3_AFMT_60958_1_BASE_IDX 2
#define mmAFMT3_AFMT_AUDIO_CRC_CONTROL 0x237a
#define mmAFMT3_AFMT_AUDIO_CRC_CONTROL_BASE_IDX 2
#define mmAFMT3_AFMT_RAMP_CONTROL0 0x237b
#define mmAFMT3_AFMT_RAMP_CONTROL0_BASE_IDX 2
#define mmAFMT3_AFMT_RAMP_CONTROL1 0x237c
#define mmAFMT3_AFMT_RAMP_CONTROL1_BASE_IDX 2
#define mmAFMT3_AFMT_RAMP_CONTROL2 0x237d
#define mmAFMT3_AFMT_RAMP_CONTROL2_BASE_IDX 2
#define mmAFMT3_AFMT_RAMP_CONTROL3 0x237e
#define mmAFMT3_AFMT_RAMP_CONTROL3_BASE_IDX 2
#define mmAFMT3_AFMT_60958_2 0x237f
#define mmAFMT3_AFMT_60958_2_BASE_IDX 2
#define mmAFMT3_AFMT_AUDIO_CRC_RESULT 0x2380
#define mmAFMT3_AFMT_AUDIO_CRC_RESULT_BASE_IDX 2
#define mmAFMT3_AFMT_STATUS 0x2381
#define mmAFMT3_AFMT_STATUS_BASE_IDX 2
#define mmAFMT3_AFMT_AUDIO_PACKET_CONTROL 0x2382
#define mmAFMT3_AFMT_AUDIO_PACKET_CONTROL_BASE_IDX 2
#define mmAFMT3_AFMT_INFOFRAME_CONTROL0 0x2383
#define mmAFMT3_AFMT_INFOFRAME_CONTROL0_BASE_IDX 2
#define mmAFMT3_AFMT_INTERRUPT_STATUS 0x2384
#define mmAFMT3_AFMT_INTERRUPT_STATUS_BASE_IDX 2
#define mmAFMT3_AFMT_AUDIO_SRC_CONTROL 0x2385
#define mmAFMT3_AFMT_AUDIO_SRC_CONTROL_BASE_IDX 2
#define mmAFMT3_AFMT_MEM_PWR 0x2387
#define mmAFMT3_AFMT_MEM_PWR_BASE_IDX 2
// addressBlock: dce_dc_dio_dig3_dme_dme_dispdec
// base address: 0x16124
#define mmDME3_DME_CONTROL 0x2389
#define mmDME3_DME_CONTROL_BASE_IDX 2
#define mmDME3_DME_MEMORY_CONTROL 0x238a
#define mmDME3_DME_MEMORY_CONTROL_BASE_IDX 2
// addressBlock: dce_dc_dio_dig3_dispdec
// base address: 0xc00
#define mmDIG3_DIG_FE_CNTL 0x238b
#define mmDIG3_DIG_FE_CNTL_BASE_IDX 2
#define mmDIG3_DIG_OUTPUT_CRC_CNTL 0x238c
#define mmDIG3_DIG_OUTPUT_CRC_CNTL_BASE_IDX 2
#define mmDIG3_DIG_OUTPUT_CRC_RESULT 0x238d
#define mmDIG3_DIG_OUTPUT_CRC_RESULT_BASE_IDX 2
#define mmDIG3_DIG_CLOCK_PATTERN 0x238e
#define mmDIG3_DIG_CLOCK_PATTERN_BASE_IDX 2
#define mmDIG3_DIG_TEST_PATTERN 0x238f
#define mmDIG3_DIG_TEST_PATTERN_BASE_IDX 2
#define mmDIG3_DIG_RANDOM_PATTERN_SEED 0x2390
#define mmDIG3_DIG_RANDOM_PATTERN_SEED_BASE_IDX 2
#define mmDIG3_DIG_FIFO_STATUS 0x2391
#define mmDIG3_DIG_FIFO_STATUS_BASE_IDX 2
#define mmDIG3_HDMI_METADATA_PACKET_CONTROL 0x2392
#define mmDIG3_HDMI_METADATA_PACKET_CONTROL_BASE_IDX 2
#define mmDIG3_HDMI_CONTROL 0x2393
#define mmDIG3_HDMI_CONTROL_BASE_IDX 2
#define mmDIG3_HDMI_STATUS 0x2394
#define mmDIG3_HDMI_STATUS_BASE_IDX 2
#define mmDIG3_HDMI_AUDIO_PACKET_CONTROL 0x2395
#define mmDIG3_HDMI_AUDIO_PACKET_CONTROL_BASE_IDX 2
#define mmDIG3_HDMI_ACR_PACKET_CONTROL 0x2396
#define mmDIG3_HDMI_ACR_PACKET_CONTROL_BASE_IDX 2
#define mmDIG3_HDMI_VBI_PACKET_CONTROL 0x2397
#define mmDIG3_HDMI_VBI_PACKET_CONTROL_BASE_IDX 2
#define mmDIG3_HDMI_INFOFRAME_CONTROL0 0x2398
#define mmDIG3_HDMI_INFOFRAME_CONTROL0_BASE_IDX 2
#define mmDIG3_HDMI_INFOFRAME_CONTROL1 0x2399
#define mmDIG3_HDMI_INFOFRAME_CONTROL1_BASE_IDX 2
#define mmDIG3_HDMI_GENERIC_PACKET_CONTROL0 0x239a
#define mmDIG3_HDMI_GENERIC_PACKET_CONTROL0_BASE_IDX 2
#define mmDIG3_HDMI_GENERIC_PACKET_CONTROL6 0x239b
#define mmDIG3_HDMI_GENERIC_PACKET_CONTROL6_BASE_IDX 2
#define mmDIG3_HDMI_GENERIC_PACKET_CONTROL5 0x239c
#define mmDIG3_HDMI_GENERIC_PACKET_CONTROL5_BASE_IDX 2
#define mmDIG3_HDMI_GC 0x239d
#define mmDIG3_HDMI_GC_BASE_IDX 2
#define mmDIG3_HDMI_GENERIC_PACKET_CONTROL1 0x239e
#define mmDIG3_HDMI_GENERIC_PACKET_CONTROL1_BASE_IDX 2
#define mmDIG3_HDMI_GENERIC_PACKET_CONTROL2 0x239f
#define mmDIG3_HDMI_GENERIC_PACKET_CONTROL2_BASE_IDX 2
#define mmDIG3_HDMI_GENERIC_PACKET_CONTROL3 0x23a0
#define mmDIG3_HDMI_GENERIC_PACKET_CONTROL3_BASE_IDX 2
#define mmDIG3_HDMI_GENERIC_PACKET_CONTROL4 0x23a1
#define mmDIG3_HDMI_GENERIC_PACKET_CONTROL4_BASE_IDX 2
#define mmDIG3_HDMI_GENERIC_PACKET_CONTROL7 0x23a2
#define mmDIG3_HDMI_GENERIC_PACKET_CONTROL7_BASE_IDX 2
#define mmDIG3_HDMI_GENERIC_PACKET_CONTROL8 0x23a3
#define mmDIG3_HDMI_GENERIC_PACKET_CONTROL8_BASE_IDX 2
#define mmDIG3_HDMI_GENERIC_PACKET_CONTROL9 0x23a4
#define mmDIG3_HDMI_GENERIC_PACKET_CONTROL9_BASE_IDX 2
#define mmDIG3_HDMI_GENERIC_PACKET_CONTROL10 0x23a5
#define mmDIG3_HDMI_GENERIC_PACKET_CONTROL10_BASE_IDX 2
#define mmDIG3_HDMI_DB_CONTROL 0x23a6
#define mmDIG3_HDMI_DB_CONTROL_BASE_IDX 2
#define mmDIG3_HDMI_ACR_32_0 0x23a7
#define mmDIG3_HDMI_ACR_32_0_BASE_IDX 2
#define mmDIG3_HDMI_ACR_32_1 0x23a8
#define mmDIG3_HDMI_ACR_32_1_BASE_IDX 2
#define mmDIG3_HDMI_ACR_44_0 0x23a9
#define mmDIG3_HDMI_ACR_44_0_BASE_IDX 2
#define mmDIG3_HDMI_ACR_44_1 0x23aa
#define mmDIG3_HDMI_ACR_44_1_BASE_IDX 2
#define mmDIG3_HDMI_ACR_48_0 0x23ab
#define mmDIG3_HDMI_ACR_48_0_BASE_IDX 2
#define mmDIG3_HDMI_ACR_48_1 0x23ac
#define mmDIG3_HDMI_ACR_48_1_BASE_IDX 2
#define mmDIG3_HDMI_ACR_STATUS_0 0x23ad
#define mmDIG3_HDMI_ACR_STATUS_0_BASE_IDX 2
#define mmDIG3_HDMI_ACR_STATUS_1 0x23ae
#define mmDIG3_HDMI_ACR_STATUS_1_BASE_IDX 2
#define mmDIG3_AFMT_CNTL 0x23af
#define mmDIG3_AFMT_CNTL_BASE_IDX 2
#define mmDIG3_DIG_BE_CNTL 0x23b0
#define mmDIG3_DIG_BE_CNTL_BASE_IDX 2
#define mmDIG3_DIG_BE_EN_CNTL 0x23b1
#define mmDIG3_DIG_BE_EN_CNTL_BASE_IDX 2
#define mmDIG3_TMDS_CNTL 0x23d7
#define mmDIG3_TMDS_CNTL_BASE_IDX 2
#define mmDIG3_TMDS_CONTROL_CHAR 0x23d8
#define mmDIG3_TMDS_CONTROL_CHAR_BASE_IDX 2
#define mmDIG3_TMDS_CONTROL0_FEEDBACK 0x23d9
#define mmDIG3_TMDS_CONTROL0_FEEDBACK_BASE_IDX 2
#define mmDIG3_TMDS_STEREOSYNC_CTL_SEL 0x23da
#define mmDIG3_TMDS_STEREOSYNC_CTL_SEL_BASE_IDX 2
#define mmDIG3_TMDS_SYNC_CHAR_PATTERN_0_1 0x23db
#define mmDIG3_TMDS_SYNC_CHAR_PATTERN_0_1_BASE_IDX 2
#define mmDIG3_TMDS_SYNC_CHAR_PATTERN_2_3 0x23dc
#define mmDIG3_TMDS_SYNC_CHAR_PATTERN_2_3_BASE_IDX 2
#define mmDIG3_TMDS_CTL_BITS 0x23de
#define mmDIG3_TMDS_CTL_BITS_BASE_IDX 2
#define mmDIG3_TMDS_DCBALANCER_CONTROL 0x23df
#define mmDIG3_TMDS_DCBALANCER_CONTROL_BASE_IDX 2
#define mmDIG3_TMDS_SYNC_DCBALANCE_CHAR 0x23e0
#define mmDIG3_TMDS_SYNC_DCBALANCE_CHAR_BASE_IDX 2
#define mmDIG3_TMDS_CTL0_1_GEN_CNTL 0x23e1
#define mmDIG3_TMDS_CTL0_1_GEN_CNTL_BASE_IDX 2
#define mmDIG3_TMDS_CTL2_3_GEN_CNTL 0x23e2
#define mmDIG3_TMDS_CTL2_3_GEN_CNTL_BASE_IDX 2
#define mmDIG3_DIG_VERSION 0x23e4
#define mmDIG3_DIG_VERSION_BASE_IDX 2
#define mmDIG3_DIG_LANE_ENABLE 0x23e5
#define mmDIG3_DIG_LANE_ENABLE_BASE_IDX 2
#define mmDIG3_FORCE_DIG_DISABLE 0x23e6
#define mmDIG3_FORCE_DIG_DISABLE_BASE_IDX 2
// addressBlock: dce_dc_dio_dp3_dispdec
// base address: 0xc00
#define mmDP3_DP_LINK_CNTL 0x2408
#define mmDP3_DP_LINK_CNTL_BASE_IDX 2
#define mmDP3_DP_PIXEL_FORMAT 0x2409
#define mmDP3_DP_PIXEL_FORMAT_BASE_IDX 2
#define mmDP3_DP_MSA_COLORIMETRY 0x240a
#define mmDP3_DP_MSA_COLORIMETRY_BASE_IDX 2
#define mmDP3_DP_CONFIG 0x240b
#define mmDP3_DP_CONFIG_BASE_IDX 2
#define mmDP3_DP_VID_STREAM_CNTL 0x240c
#define mmDP3_DP_VID_STREAM_CNTL_BASE_IDX 2
#define mmDP3_DP_STEER_FIFO 0x240d
#define mmDP3_DP_STEER_FIFO_BASE_IDX 2
#define mmDP3_DP_MSA_MISC 0x240e
#define mmDP3_DP_MSA_MISC_BASE_IDX 2
#define mmDP3_DP_DPHY_INTERNAL_CTRL 0x240f
#define mmDP3_DP_DPHY_INTERNAL_CTRL_BASE_IDX 2
#define mmDP3_DP_VID_TIMING 0x2410
#define mmDP3_DP_VID_TIMING_BASE_IDX 2
#define mmDP3_DP_VID_N 0x2411
#define mmDP3_DP_VID_N_BASE_IDX 2
#define mmDP3_DP_VID_M 0x2412
#define mmDP3_DP_VID_M_BASE_IDX 2
#define mmDP3_DP_LINK_FRAMING_CNTL 0x2413
#define mmDP3_DP_LINK_FRAMING_CNTL_BASE_IDX 2
#define mmDP3_DP_HBR2_EYE_PATTERN 0x2414
#define mmDP3_DP_HBR2_EYE_PATTERN_BASE_IDX 2
#define mmDP3_DP_VID_MSA_VBID 0x2415
#define mmDP3_DP_VID_MSA_VBID_BASE_IDX 2
#define mmDP3_DP_VID_INTERRUPT_CNTL 0x2416
#define mmDP3_DP_VID_INTERRUPT_CNTL_BASE_IDX 2
#define mmDP3_DP_DPHY_CNTL 0x2417
#define mmDP3_DP_DPHY_CNTL_BASE_IDX 2
#define mmDP3_DP_DPHY_TRAINING_PATTERN_SEL 0x2418
#define mmDP3_DP_DPHY_TRAINING_PATTERN_SEL_BASE_IDX 2
#define mmDP3_DP_DPHY_SYM0 0x2419
#define mmDP3_DP_DPHY_SYM0_BASE_IDX 2
#define mmDP3_DP_DPHY_SYM1 0x241a
#define mmDP3_DP_DPHY_SYM1_BASE_IDX 2
#define mmDP3_DP_DPHY_SYM2 0x241b
#define mmDP3_DP_DPHY_SYM2_BASE_IDX 2
#define mmDP3_DP_DPHY_8B10B_CNTL 0x241c
#define mmDP3_DP_DPHY_8B10B_CNTL_BASE_IDX 2
#define mmDP3_DP_DPHY_PRBS_CNTL 0x241d
#define mmDP3_DP_DPHY_PRBS_CNTL_BASE_IDX 2
#define mmDP3_DP_DPHY_SCRAM_CNTL 0x241e
#define mmDP3_DP_DPHY_SCRAM_CNTL_BASE_IDX 2
#define mmDP3_DP_DPHY_CRC_EN 0x241f
#define mmDP3_DP_DPHY_CRC_EN_BASE_IDX 2
#define mmDP3_DP_DPHY_CRC_CNTL 0x2420
#define mmDP3_DP_DPHY_CRC_CNTL_BASE_IDX 2
#define mmDP3_DP_DPHY_CRC_RESULT 0x2421
#define mmDP3_DP_DPHY_CRC_RESULT_BASE_IDX 2
#define mmDP3_DP_DPHY_CRC_MST_CNTL 0x2422
#define mmDP3_DP_DPHY_CRC_MST_CNTL_BASE_IDX 2
#define mmDP3_DP_DPHY_CRC_MST_STATUS 0x2423
#define mmDP3_DP_DPHY_CRC_MST_STATUS_BASE_IDX 2
#define mmDP3_DP_DPHY_FAST_TRAINING 0x2424
#define mmDP3_DP_DPHY_FAST_TRAINING_BASE_IDX 2
#define mmDP3_DP_DPHY_FAST_TRAINING_STATUS 0x2425
#define mmDP3_DP_DPHY_FAST_TRAINING_STATUS_BASE_IDX 2
#define mmDP3_DP_SEC_CNTL 0x242b
#define mmDP3_DP_SEC_CNTL_BASE_IDX 2
#define mmDP3_DP_SEC_CNTL1 0x242c
#define mmDP3_DP_SEC_CNTL1_BASE_IDX 2
#define mmDP3_DP_SEC_FRAMING1 0x242d
#define mmDP3_DP_SEC_FRAMING1_BASE_IDX 2
#define mmDP3_DP_SEC_FRAMING2 0x242e
#define mmDP3_DP_SEC_FRAMING2_BASE_IDX 2
#define mmDP3_DP_SEC_FRAMING3 0x242f
#define mmDP3_DP_SEC_FRAMING3_BASE_IDX 2
#define mmDP3_DP_SEC_FRAMING4 0x2430
#define mmDP3_DP_SEC_FRAMING4_BASE_IDX 2
#define mmDP3_DP_SEC_AUD_N 0x2431
#define mmDP3_DP_SEC_AUD_N_BASE_IDX 2
#define mmDP3_DP_SEC_AUD_N_READBACK 0x2432
#define mmDP3_DP_SEC_AUD_N_READBACK_BASE_IDX 2
#define mmDP3_DP_SEC_AUD_M 0x2433
#define mmDP3_DP_SEC_AUD_M_BASE_IDX 2
#define mmDP3_DP_SEC_AUD_M_READBACK 0x2434
#define mmDP3_DP_SEC_AUD_M_READBACK_BASE_IDX 2
#define mmDP3_DP_SEC_TIMESTAMP 0x2435
#define mmDP3_DP_SEC_TIMESTAMP_BASE_IDX 2
#define mmDP3_DP_SEC_PACKET_CNTL 0x2436
#define mmDP3_DP_SEC_PACKET_CNTL_BASE_IDX 2
#define mmDP3_DP_MSE_RATE_CNTL 0x2437
#define mmDP3_DP_MSE_RATE_CNTL_BASE_IDX 2
#define mmDP3_DP_MSE_RATE_UPDATE 0x2439
#define mmDP3_DP_MSE_RATE_UPDATE_BASE_IDX 2
#define mmDP3_DP_MSE_SAT0 0x243a
#define mmDP3_DP_MSE_SAT0_BASE_IDX 2
#define mmDP3_DP_MSE_SAT1 0x243b
#define mmDP3_DP_MSE_SAT1_BASE_IDX 2
#define mmDP3_DP_MSE_SAT2 0x243c
#define mmDP3_DP_MSE_SAT2_BASE_IDX 2
#define mmDP3_DP_MSE_SAT_UPDATE 0x243d
#define mmDP3_DP_MSE_SAT_UPDATE_BASE_IDX 2
#define mmDP3_DP_MSE_LINK_TIMING 0x243e
#define mmDP3_DP_MSE_LINK_TIMING_BASE_IDX 2
#define mmDP3_DP_MSE_MISC_CNTL 0x243f
#define mmDP3_DP_MSE_MISC_CNTL_BASE_IDX 2
#define mmDP3_DP_DPHY_BS_SR_SWAP_CNTL 0x2444
#define mmDP3_DP_DPHY_BS_SR_SWAP_CNTL_BASE_IDX 2
#define mmDP3_DP_DPHY_HBR2_PATTERN_CONTROL 0x2445
#define mmDP3_DP_DPHY_HBR2_PATTERN_CONTROL_BASE_IDX 2
#define mmDP3_DP_MSE_SAT0_STATUS 0x2447
#define mmDP3_DP_MSE_SAT0_STATUS_BASE_IDX 2
#define mmDP3_DP_MSE_SAT1_STATUS 0x2448
#define mmDP3_DP_MSE_SAT1_STATUS_BASE_IDX 2
#define mmDP3_DP_MSE_SAT2_STATUS 0x2449
#define mmDP3_DP_MSE_SAT2_STATUS_BASE_IDX 2
#define mmDP3_DP_MSA_TIMING_PARAM1 0x244c
#define mmDP3_DP_MSA_TIMING_PARAM1_BASE_IDX 2
#define mmDP3_DP_MSA_TIMING_PARAM2 0x244d
#define mmDP3_DP_MSA_TIMING_PARAM2_BASE_IDX 2
#define mmDP3_DP_MSA_TIMING_PARAM3 0x244e
#define mmDP3_DP_MSA_TIMING_PARAM3_BASE_IDX 2
#define mmDP3_DP_MSA_TIMING_PARAM4 0x244f
#define mmDP3_DP_MSA_TIMING_PARAM4_BASE_IDX 2
#define mmDP3_DP_MSO_CNTL 0x2450
#define mmDP3_DP_MSO_CNTL_BASE_IDX 2
#define mmDP3_DP_MSO_CNTL1 0x2451
#define mmDP3_DP_MSO_CNTL1_BASE_IDX 2
#define mmDP3_DP_DSC_CNTL 0x2452
#define mmDP3_DP_DSC_CNTL_BASE_IDX 2
#define mmDP3_DP_SEC_CNTL2 0x2453
#define mmDP3_DP_SEC_CNTL2_BASE_IDX 2
#define mmDP3_DP_SEC_CNTL3 0x2454
#define mmDP3_DP_SEC_CNTL3_BASE_IDX 2
#define mmDP3_DP_SEC_CNTL4 0x2455
#define mmDP3_DP_SEC_CNTL4_BASE_IDX 2
#define mmDP3_DP_SEC_CNTL5 0x2456
#define mmDP3_DP_SEC_CNTL5_BASE_IDX 2
#define mmDP3_DP_SEC_CNTL6 0x2457
#define mmDP3_DP_SEC_CNTL6_BASE_IDX 2
#define mmDP3_DP_SEC_CNTL7 0x2458
#define mmDP3_DP_SEC_CNTL7_BASE_IDX 2
#define mmDP3_DP_DB_CNTL 0x2459
#define mmDP3_DP_DB_CNTL_BASE_IDX 2
#define mmDP3_DP_MSA_VBID_MISC 0x245a
#define mmDP3_DP_MSA_VBID_MISC_BASE_IDX 2
#define mmDP3_DP_SEC_METADATA_TRANSMISSION 0x245b
#define mmDP3_DP_SEC_METADATA_TRANSMISSION_BASE_IDX 2
#define mmDP3_DP_DSC_BYTES_PER_PIXEL 0x245c
#define mmDP3_DP_DSC_BYTES_PER_PIXEL_BASE_IDX 2
#define mmDP3_DP_ALPM_CNTL 0x245d
#define mmDP3_DP_ALPM_CNTL_BASE_IDX 2
#define mmDP3_DP_GSP8_CNTL 0x245e
#define mmDP3_DP_GSP8_CNTL_BASE_IDX 2
#define mmDP3_DP_GSP9_CNTL 0x245f
#define mmDP3_DP_GSP9_CNTL_BASE_IDX 2
#define mmDP3_DP_GSP10_CNTL 0x2460
#define mmDP3_DP_GSP10_CNTL_BASE_IDX 2
#define mmDP3_DP_GSP11_CNTL 0x2461
#define mmDP3_DP_GSP11_CNTL_BASE_IDX 2
#define mmDP3_DP_GSP_EN_DB_STATUS 0x2462
#define mmDP3_DP_GSP_EN_DB_STATUS_BASE_IDX 2
// addressBlock: dce_dc_dio_dig4_vpg_vpg_dispdec
// base address: 0x164a0
#define mmVPG4_VPG_GENERIC_PACKET_ACCESS_CTRL 0x2468
#define mmVPG4_VPG_GENERIC_PACKET_ACCESS_CTRL_BASE_IDX 2
#define mmVPG4_VPG_GENERIC_PACKET_DATA 0x2469
#define mmVPG4_VPG_GENERIC_PACKET_DATA_BASE_IDX 2
#define mmVPG4_VPG_GSP_FRAME_UPDATE_CTRL 0x246a
#define mmVPG4_VPG_GSP_FRAME_UPDATE_CTRL_BASE_IDX 2
#define mmVPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL 0x246b
#define mmVPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL_BASE_IDX 2
#define mmVPG4_VPG_GENERIC_STATUS 0x246c
#define mmVPG4_VPG_GENERIC_STATUS_BASE_IDX 2
#define mmVPG4_VPG_MEM_PWR 0x246d
#define mmVPG4_VPG_MEM_PWR_BASE_IDX 2
#define mmVPG4_VPG_ISRC1_2_ACCESS_CTRL 0x246e
#define mmVPG4_VPG_ISRC1_2_ACCESS_CTRL_BASE_IDX 2
#define mmVPG4_VPG_ISRC1_2_DATA 0x246f
#define mmVPG4_VPG_ISRC1_2_DATA_BASE_IDX 2
#define mmVPG4_VPG_MPEG_INFO0 0x2470
#define mmVPG4_VPG_MPEG_INFO0_BASE_IDX 2
#define mmVPG4_VPG_MPEG_INFO1 0x2471
#define mmVPG4_VPG_MPEG_INFO1_BASE_IDX 2
// addressBlock: dce_dc_dio_dig4_afmt_afmt_dispdec
#define mmAFMT4_AFMT_VBI_PACKET_CONTROL 0x2474
#define mmAFMT4_AFMT_VBI_PACKET_CONTROL_BASE_IDX 2
#define mmAFMT4_AFMT_AUDIO_PACKET_CONTROL2 0x2475
#define mmAFMT4_AFMT_AUDIO_PACKET_CONTROL2_BASE_IDX 2
#define mmAFMT4_AFMT_AUDIO_INFO0 0x2476
#define mmAFMT4_AFMT_AUDIO_INFO0_BASE_IDX 2
#define mmAFMT4_AFMT_AUDIO_INFO1 0x2477
#define mmAFMT4_AFMT_AUDIO_INFO1_BASE_IDX 2
#define mmAFMT4_AFMT_60958_0 0x2478
#define mmAFMT4_AFMT_60958_0_BASE_IDX 2
#define mmAFMT4_AFMT_60958_1 0x2479
#define mmAFMT4_AFMT_60958_1_BASE_IDX 2
#define mmAFMT4_AFMT_AUDIO_CRC_CONTROL 0x247a
#define mmAFMT4_AFMT_AUDIO_CRC_CONTROL_BASE_IDX 2
#define mmAFMT4_AFMT_RAMP_CONTROL0 0x247b
#define mmAFMT4_AFMT_RAMP_CONTROL0_BASE_IDX 2
#define mmAFMT4_AFMT_RAMP_CONTROL1 0x247c
#define mmAFMT4_AFMT_RAMP_CONTROL1_BASE_IDX 2
#define mmAFMT4_AFMT_RAMP_CONTROL2 0x247d
#define mmAFMT4_AFMT_RAMP_CONTROL2_BASE_IDX 2
#define mmAFMT4_AFMT_RAMP_CONTROL3 0x247e
#define mmAFMT4_AFMT_RAMP_CONTROL3_BASE_IDX 2
#define mmAFMT4_AFMT_60958_2 0x247f
#define mmAFMT4_AFMT_60958_2_BASE_IDX 2
#define mmAFMT4_AFMT_AUDIO_CRC_RESULT 0x2480
#define mmAFMT4_AFMT_AUDIO_CRC_RESULT_BASE_IDX 2
#define mmAFMT4_AFMT_STATUS 0x2481
#define mmAFMT4_AFMT_STATUS_BASE_IDX 2
#define mmAFMT4_AFMT_AUDIO_PACKET_CONTROL 0x2482
#define mmAFMT4_AFMT_AUDIO_PACKET_CONTROL_BASE_IDX 2
#define mmAFMT4_AFMT_INFOFRAME_CONTROL0 0x2483
#define mmAFMT4_AFMT_INFOFRAME_CONTROL0_BASE_IDX 2
#define mmAFMT4_AFMT_INTERRUPT_STATUS 0x2484
#define mmAFMT4_AFMT_INTERRUPT_STATUS_BASE_IDX 2
#define mmAFMT4_AFMT_AUDIO_SRC_CONTROL 0x2485
#define mmAFMT4_AFMT_AUDIO_SRC_CONTROL_BASE_IDX 2
#define mmAFMT4_AFMT_MEM_PWR 0x2487
#define mmAFMT4_AFMT_MEM_PWR_BASE_IDX 2
// addressBlock: dce_dc_dio_dig4_dme_dme_dispdec
// base address: 0x16524
#define mmDME4_DME_CONTROL 0x2489
#define mmDME4_DME_CONTROL_BASE_IDX 2
#define mmDME4_DME_MEMORY_CONTROL 0x248a
#define mmDME4_DME_MEMORY_CONTROL_BASE_IDX 2
// addressBlock: dce_dc_dio_dig4_dispdec
// base address: 0x1000
#define mmDIG4_DIG_FE_CNTL 0x248b
#define mmDIG4_DIG_FE_CNTL_BASE_IDX 2
#define mmDIG4_DIG_OUTPUT_CRC_CNTL 0x248c
#define mmDIG4_DIG_OUTPUT_CRC_CNTL_BASE_IDX 2
#define mmDIG4_DIG_OUTPUT_CRC_RESULT 0x248d
#define mmDIG4_DIG_OUTPUT_CRC_RESULT_BASE_IDX 2
#define mmDIG4_DIG_CLOCK_PATTERN 0x248e
#define mmDIG4_DIG_CLOCK_PATTERN_BASE_IDX 2
#define mmDIG4_DIG_TEST_PATTERN 0x248f
#define mmDIG4_DIG_TEST_PATTERN_BASE_IDX 2
#define mmDIG4_DIG_RANDOM_PATTERN_SEED 0x2490
#define mmDIG4_DIG_RANDOM_PATTERN_SEED_BASE_IDX 2
#define mmDIG4_DIG_FIFO_STATUS 0x2491
#define mmDIG4_DIG_FIFO_STATUS_BASE_IDX 2
#define mmDIG4_HDMI_METADATA_PACKET_CONTROL 0x2492
#define mmDIG4_HDMI_METADATA_PACKET_CONTROL_BASE_IDX 2
#define mmDIG4_HDMI_CONTROL 0x2493
#define mmDIG4_HDMI_CONTROL_BASE_IDX 2
#define mmDIG4_HDMI_STATUS 0x2494
#define mmDIG4_HDMI_STATUS_BASE_IDX 2
#define mmDIG4_HDMI_AUDIO_PACKET_CONTROL 0x2495
#define mmDIG4_HDMI_AUDIO_PACKET_CONTROL_BASE_IDX 2
#define mmDIG4_HDMI_ACR_PACKET_CONTROL 0x2496
#define mmDIG4_HDMI_ACR_PACKET_CONTROL_BASE_IDX 2
#define mmDIG4_HDMI_VBI_PACKET_CONTROL 0x2497
#define mmDIG4_HDMI_VBI_PACKET_CONTROL_BASE_IDX 2
#define mmDIG4_HDMI_INFOFRAME_CONTROL0 0x2498
#define mmDIG4_HDMI_INFOFRAME_CONTROL0_BASE_IDX 2
#define mmDIG4_HDMI_INFOFRAME_CONTROL1 0x2499
#define mmDIG4_HDMI_INFOFRAME_CONTROL1_BASE_IDX 2
#define mmDIG4_HDMI_GENERIC_PACKET_CONTROL0 0x249a
#define mmDIG4_HDMI_GENERIC_PACKET_CONTROL0_BASE_IDX 2
#define mmDIG4_HDMI_GENERIC_PACKET_CONTROL6 0x249b
#define mmDIG4_HDMI_GENERIC_PACKET_CONTROL6_BASE_IDX 2
#define mmDIG4_HDMI_GENERIC_PACKET_CONTROL5 0x249c
#define mmDIG4_HDMI_GENERIC_PACKET_CONTROL5_BASE_IDX 2
#define mmDIG4_HDMI_GC 0x249d
#define mmDIG4_HDMI_GC_BASE_IDX 2
#define mmDIG4_HDMI_GENERIC_PACKET_CONTROL1 0x249e
#define mmDIG4_HDMI_GENERIC_PACKET_CONTROL1_BASE_IDX 2
#define mmDIG4_HDMI_GENERIC_PACKET_CONTROL2 0x249f
#define mmDIG4_HDMI_GENERIC_PACKET_CONTROL2_BASE_IDX 2
#define mmDIG4_HDMI_GENERIC_PACKET_CONTROL3 0x24a0
#define mmDIG4_HDMI_GENERIC_PACKET_CONTROL3_BASE_IDX 2
#define mmDIG4_HDMI_GENERIC_PACKET_CONTROL4 0x24a1
#define mmDIG4_HDMI_GENERIC_PACKET_CONTROL4_BASE_IDX 2
#define mmDIG4_HDMI_GENERIC_PACKET_CONTROL7 0x24a2
#define mmDIG4_HDMI_GENERIC_PACKET_CONTROL7_BASE_IDX 2
#define mmDIG4_HDMI_GENERIC_PACKET_CONTROL8 0x24a3
#define mmDIG4_HDMI_GENERIC_PACKET_CONTROL8_BASE_IDX 2
#define mmDIG4_HDMI_GENERIC_PACKET_CONTROL9 0x24a4
#define mmDIG4_HDMI_GENERIC_PACKET_CONTROL9_BASE_IDX 2
#define mmDIG4_HDMI_GENERIC_PACKET_CONTROL10 0x24a5
#define mmDIG4_HDMI_GENERIC_PACKET_CONTROL10_BASE_IDX 2
#define mmDIG4_HDMI_DB_CONTROL 0x24a6
#define mmDIG4_HDMI_DB_CONTROL_BASE_IDX 2
#define mmDIG4_HDMI_ACR_32_0 0x24a7
#define mmDIG4_HDMI_ACR_32_0_BASE_IDX 2
#define mmDIG4_HDMI_ACR_32_1 0x24a8
#define mmDIG4_HDMI_ACR_32_1_BASE_IDX 2
#define mmDIG4_HDMI_ACR_44_0 0x24a9
#define mmDIG4_HDMI_ACR_44_0_BASE_IDX 2
#define mmDIG4_HDMI_ACR_44_1 0x24aa
#define mmDIG4_HDMI_ACR_44_1_BASE_IDX 2
#define mmDIG4_HDMI_ACR_48_0 0x24ab
#define mmDIG4_HDMI_ACR_48_0_BASE_IDX 2
#define mmDIG4_HDMI_ACR_48_1 0x24ac
#define mmDIG4_HDMI_ACR_48_1_BASE_IDX 2
#define mmDIG4_HDMI_ACR_STATUS_0 0x24ad
#define mmDIG4_HDMI_ACR_STATUS_0_BASE_IDX 2
#define mmDIG4_HDMI_ACR_STATUS_1 0x24ae
#define mmDIG4_HDMI_ACR_STATUS_1_BASE_IDX 2
#define mmDIG4_AFMT_CNTL 0x24af
#define mmDIG4_AFMT_CNTL_BASE_IDX 2
#define mmDIG4_DIG_BE_CNTL 0x24b0
#define mmDIG4_DIG_BE_CNTL_BASE_IDX 2
#define mmDIG4_DIG_BE_EN_CNTL 0x24b1
#define mmDIG4_DIG_BE_EN_CNTL_BASE_IDX 2
#define mmDIG4_TMDS_CNTL 0x24d7
#define mmDIG4_TMDS_CNTL_BASE_IDX 2
#define mmDIG4_TMDS_CONTROL_CHAR 0x24d8
#define mmDIG4_TMDS_CONTROL_CHAR_BASE_IDX 2
#define mmDIG4_TMDS_CONTROL0_FEEDBACK 0x24d9
#define mmDIG4_TMDS_CONTROL0_FEEDBACK_BASE_IDX 2
#define mmDIG4_TMDS_STEREOSYNC_CTL_SEL 0x24da
#define mmDIG4_TMDS_STEREOSYNC_CTL_SEL_BASE_IDX 2
#define mmDIG4_TMDS_SYNC_CHAR_PATTERN_0_1 0x24db
#define mmDIG4_TMDS_SYNC_CHAR_PATTERN_0_1_BASE_IDX 2
#define mmDIG4_TMDS_SYNC_CHAR_PATTERN_2_3 0x24dc
#define mmDIG4_TMDS_SYNC_CHAR_PATTERN_2_3_BASE_IDX 2
#define mmDIG4_TMDS_CTL_BITS 0x24de
#define mmDIG4_TMDS_CTL_BITS_BASE_IDX 2
#define mmDIG4_TMDS_DCBALANCER_CONTROL 0x24df
#define mmDIG4_TMDS_DCBALANCER_CONTROL_BASE_IDX 2
#define mmDIG4_TMDS_SYNC_DCBALANCE_CHAR 0x24e0
#define mmDIG4_TMDS_SYNC_DCBALANCE_CHAR_BASE_IDX 2
#define mmDIG4_TMDS_CTL0_1_GEN_CNTL 0x24e1
#define mmDIG4_TMDS_CTL0_1_GEN_CNTL_BASE_IDX 2
#define mmDIG4_TMDS_CTL2_3_GEN_CNTL 0x24e2
#define mmDIG4_TMDS_CTL2_3_GEN_CNTL_BASE_IDX 2
#define mmDIG4_DIG_VERSION 0x24e4
#define mmDIG4_DIG_VERSION_BASE_IDX 2
#define mmDIG4_DIG_LANE_ENABLE 0x24e5
#define mmDIG4_DIG_LANE_ENABLE_BASE_IDX 2
#define mmDIG4_FORCE_DIG_DISABLE 0x24e6
#define mmDIG4_FORCE_DIG_DISABLE_BASE_IDX 2
// addressBlock: dce_dc_dio_dp4_dispdec
// base address: 0x1000
#define mmDP4_DP_LINK_CNTL 0x2508
#define mmDP4_DP_LINK_CNTL_BASE_IDX 2
#define mmDP4_DP_PIXEL_FORMAT 0x2509
#define mmDP4_DP_PIXEL_FORMAT_BASE_IDX 2
#define mmDP4_DP_MSA_COLORIMETRY 0x250a
#define mmDP4_DP_MSA_COLORIMETRY_BASE_IDX 2
#define mmDP4_DP_CONFIG 0x250b
#define mmDP4_DP_CONFIG_BASE_IDX 2
#define mmDP4_DP_VID_STREAM_CNTL 0x250c
#define mmDP4_DP_VID_STREAM_CNTL_BASE_IDX 2
#define mmDP4_DP_STEER_FIFO 0x250d
#define mmDP4_DP_STEER_FIFO_BASE_IDX 2
#define mmDP4_DP_MSA_MISC 0x250e
#define mmDP4_DP_MSA_MISC_BASE_IDX 2
#define mmDP4_DP_DPHY_INTERNAL_CTRL 0x250f
#define mmDP4_DP_DPHY_INTERNAL_CTRL_BASE_IDX 2
#define mmDP4_DP_VID_TIMING 0x2510
#define mmDP4_DP_VID_TIMING_BASE_IDX 2
#define mmDP4_DP_VID_N 0x2511
#define mmDP4_DP_VID_N_BASE_IDX 2
#define mmDP4_DP_VID_M 0x2512
#define mmDP4_DP_VID_M_BASE_IDX 2
#define mmDP4_DP_LINK_FRAMING_CNTL 0x2513
#define mmDP4_DP_LINK_FRAMING_CNTL_BASE_IDX 2
#define mmDP4_DP_HBR2_EYE_PATTERN 0x2514
#define mmDP4_DP_HBR2_EYE_PATTERN_BASE_IDX 2
#define mmDP4_DP_VID_MSA_VBID 0x2515
#define mmDP4_DP_VID_MSA_VBID_BASE_IDX 2
#define mmDP4_DP_VID_INTERRUPT_CNTL 0x2516
#define mmDP4_DP_VID_INTERRUPT_CNTL_BASE_IDX 2
#define mmDP4_DP_DPHY_CNTL 0x2517
#define mmDP4_DP_DPHY_CNTL_BASE_IDX 2
#define mmDP4_DP_DPHY_TRAINING_PATTERN_SEL 0x2518
#define mmDP4_DP_DPHY_TRAINING_PATTERN_SEL_BASE_IDX 2
#define mmDP4_DP_DPHY_SYM0 0x2519
#define mmDP4_DP_DPHY_SYM0_BASE_IDX 2
#define mmDP4_DP_DPHY_SYM1 0x251a
#define mmDP4_DP_DPHY_SYM1_BASE_IDX 2
#define mmDP4_DP_DPHY_SYM2 0x251b
#define mmDP4_DP_DPHY_SYM2_BASE_IDX 2
#define mmDP4_DP_DPHY_8B10B_CNTL 0x251c
#define mmDP4_DP_DPHY_8B10B_CNTL_BASE_IDX 2
#define mmDP4_DP_DPHY_PRBS_CNTL 0x251d
#define mmDP4_DP_DPHY_PRBS_CNTL_BASE_IDX 2
#define mmDP4_DP_DPHY_SCRAM_CNTL 0x251e
#define mmDP4_DP_DPHY_SCRAM_CNTL_BASE_IDX 2
#define mmDP4_DP_DPHY_CRC_EN 0x251f
#define mmDP4_DP_DPHY_CRC_EN_BASE_IDX 2
#define mmDP4_DP_DPHY_CRC_CNTL 0x2520
#define mmDP4_DP_DPHY_CRC_CNTL_BASE_IDX 2
#define mmDP4_DP_DPHY_CRC_RESULT 0x2521
#define mmDP4_DP_DPHY_CRC_RESULT_BASE_IDX 2
#define mmDP4_DP_DPHY_CRC_MST_CNTL 0x2522
#define mmDP4_DP_DPHY_CRC_MST_CNTL_BASE_IDX 2
#define mmDP4_DP_DPHY_CRC_MST_STATUS 0x2523
#define mmDP4_DP_DPHY_CRC_MST_STATUS_BASE_IDX 2
#define mmDP4_DP_DPHY_FAST_TRAINING 0x2524
#define mmDP4_DP_DPHY_FAST_TRAINING_BASE_IDX 2
#define mmDP4_DP_DPHY_FAST_TRAINING_STATUS 0x2525
#define mmDP4_DP_DPHY_FAST_TRAINING_STATUS_BASE_IDX 2
#define mmDP4_DP_SEC_CNTL 0x252b
#define mmDP4_DP_SEC_CNTL_BASE_IDX 2
#define mmDP4_DP_SEC_CNTL1 0x252c
#define mmDP4_DP_SEC_CNTL1_BASE_IDX 2
#define mmDP4_DP_SEC_FRAMING1 0x252d
#define mmDP4_DP_SEC_FRAMING1_BASE_IDX 2
#define mmDP4_DP_SEC_FRAMING2 0x252e
#define mmDP4_DP_SEC_FRAMING2_BASE_IDX 2
#define mmDP4_DP_SEC_FRAMING3 0x252f
#define mmDP4_DP_SEC_FRAMING3_BASE_IDX 2
#define mmDP4_DP_SEC_FRAMING4 0x2530
#define mmDP4_DP_SEC_FRAMING4_BASE_IDX 2
#define mmDP4_DP_SEC_AUD_N 0x2531
#define mmDP4_DP_SEC_AUD_N_BASE_IDX 2
#define mmDP4_DP_SEC_AUD_N_READBACK 0x2532
#define mmDP4_DP_SEC_AUD_N_READBACK_BASE_IDX 2
#define mmDP4_DP_SEC_AUD_M 0x2533
#define mmDP4_DP_SEC_AUD_M_BASE_IDX 2
#define mmDP4_DP_SEC_AUD_M_READBACK 0x2534
#define mmDP4_DP_SEC_AUD_M_READBACK_BASE_IDX 2
#define mmDP4_DP_SEC_TIMESTAMP 0x2535
#define mmDP4_DP_SEC_TIMESTAMP_BASE_IDX 2
#define mmDP4_DP_SEC_PACKET_CNTL 0x2536
#define mmDP4_DP_SEC_PACKET_CNTL_BASE_IDX 2
#define mmDP4_DP_MSE_RATE_CNTL 0x2537
#define mmDP4_DP_MSE_RATE_CNTL_BASE_IDX 2
#define mmDP4_DP_MSE_RATE_UPDATE 0x2539
#define mmDP4_DP_MSE_RATE_UPDATE_BASE_IDX 2
#define mmDP4_DP_MSE_SAT0 0x253a
#define mmDP4_DP_MSE_SAT0_BASE_IDX 2
#define mmDP4_DP_MSE_SAT1 0x253b
#define mmDP4_DP_MSE_SAT1_BASE_IDX 2
#define mmDP4_DP_MSE_SAT2 0x253c
#define mmDP4_DP_MSE_SAT2_BASE_IDX 2
#define mmDP4_DP_MSE_SAT_UPDATE 0x253d
#define mmDP4_DP_MSE_SAT_UPDATE_BASE_IDX 2
#define mmDP4_DP_MSE_LINK_TIMING 0x253e
#define mmDP4_DP_MSE_LINK_TIMING_BASE_IDX 2
#define mmDP4_DP_MSE_MISC_CNTL 0x253f
#define mmDP4_DP_MSE_MISC_CNTL_BASE_IDX 2
#define mmDP4_DP_DPHY_BS_SR_SWAP_CNTL 0x2544
#define mmDP4_DP_DPHY_BS_SR_SWAP_CNTL_BASE_IDX 2
#define mmDP4_DP_DPHY_HBR2_PATTERN_CONTROL 0x2545
#define mmDP4_DP_DPHY_HBR2_PATTERN_CONTROL_BASE_IDX 2
#define mmDP4_DP_MSE_SAT0_STATUS 0x2547
#define mmDP4_DP_MSE_SAT0_STATUS_BASE_IDX 2
#define mmDP4_DP_MSE_SAT1_STATUS 0x2548
#define mmDP4_DP_MSE_SAT1_STATUS_BASE_IDX 2
#define mmDP4_DP_MSE_SAT2_STATUS 0x2549
#define mmDP4_DP_MSE_SAT2_STATUS_BASE_IDX 2
#define mmDP4_DP_MSA_TIMING_PARAM1 0x254c
#define mmDP4_DP_MSA_TIMING_PARAM1_BASE_IDX 2
#define mmDP4_DP_MSA_TIMING_PARAM2 0x254d
#define mmDP4_DP_MSA_TIMING_PARAM2_BASE_IDX 2
#define mmDP4_DP_MSA_TIMING_PARAM3 0x254e
#define mmDP4_DP_MSA_TIMING_PARAM3_BASE_IDX 2
#define mmDP4_DP_MSA_TIMING_PARAM4 0x254f
#define mmDP4_DP_MSA_TIMING_PARAM4_BASE_IDX 2
#define mmDP4_DP_MSO_CNTL 0x2550
#define mmDP4_DP_MSO_CNTL_BASE_IDX 2
#define mmDP4_DP_MSO_CNTL1 0x2551
#define mmDP4_DP_MSO_CNTL1_BASE_IDX 2
#define mmDP4_DP_DSC_CNTL 0x2552
#define mmDP4_DP_DSC_CNTL_BASE_IDX 2
#define mmDP4_DP_SEC_CNTL2 0x2553
#define mmDP4_DP_SEC_CNTL2_BASE_IDX 2
#define mmDP4_DP_SEC_CNTL3 0x2554
#define mmDP4_DP_SEC_CNTL3_BASE_IDX 2
#define mmDP4_DP_SEC_CNTL4 0x2555
#define mmDP4_DP_SEC_CNTL4_BASE_IDX 2
#define mmDP4_DP_SEC_CNTL5 0x2556
#define mmDP4_DP_SEC_CNTL5_BASE_IDX 2
#define mmDP4_DP_SEC_CNTL6 0x2557
#define mmDP4_DP_SEC_CNTL6_BASE_IDX 2
#define mmDP4_DP_SEC_CNTL7 0x2558
#define mmDP4_DP_SEC_CNTL7_BASE_IDX 2
#define mmDP4_DP_DB_CNTL 0x2559
#define mmDP4_DP_DB_CNTL_BASE_IDX 2
#define mmDP4_DP_MSA_VBID_MISC 0x255a
#define mmDP4_DP_MSA_VBID_MISC_BASE_IDX 2
#define mmDP4_DP_SEC_METADATA_TRANSMISSION 0x255b
#define mmDP4_DP_SEC_METADATA_TRANSMISSION_BASE_IDX 2
#define mmDP4_DP_DSC_BYTES_PER_PIXEL 0x255c
#define mmDP4_DP_DSC_BYTES_PER_PIXEL_BASE_IDX 2
#define mmDP4_DP_ALPM_CNTL 0x255d
#define mmDP4_DP_ALPM_CNTL_BASE_IDX 2
#define mmDP4_DP_GSP8_CNTL 0x255e
#define mmDP4_DP_GSP8_CNTL_BASE_IDX 2
#define mmDP4_DP_GSP9_CNTL 0x255f
#define mmDP4_DP_GSP9_CNTL_BASE_IDX 2
#define mmDP4_DP_GSP10_CNTL 0x2560
#define mmDP4_DP_GSP10_CNTL_BASE_IDX 2
#define mmDP4_DP_GSP11_CNTL 0x2561
#define mmDP4_DP_GSP11_CNTL_BASE_IDX 2
#define mmDP4_DP_GSP_EN_DB_STATUS 0x2562
#define mmDP4_DP_GSP_EN_DB_STATUS_BASE_IDX 2
// addressBlock: dce_dc_dio_dig5_vpg_vpg_dispdec
// base address: 0x168a0
#define mmVPG5_VPG_GENERIC_PACKET_ACCESS_CTRL 0x2568
#define mmVPG5_VPG_GENERIC_PACKET_ACCESS_CTRL_BASE_IDX 2
#define mmVPG5_VPG_GENERIC_PACKET_DATA 0x2569
#define mmVPG5_VPG_GENERIC_PACKET_DATA_BASE_IDX 2
#define mmVPG5_VPG_GSP_FRAME_UPDATE_CTRL 0x256a
#define mmVPG5_VPG_GSP_FRAME_UPDATE_CTRL_BASE_IDX 2
#define mmVPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL 0x256b
#define mmVPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL_BASE_IDX 2
#define mmVPG5_VPG_GENERIC_STATUS 0x256c
#define mmVPG5_VPG_GENERIC_STATUS_BASE_IDX 2
#define mmVPG5_VPG_MEM_PWR 0x256d
#define mmVPG5_VPG_MEM_PWR_BASE_IDX 2
#define mmVPG5_VPG_ISRC1_2_ACCESS_CTRL 0x256e
#define mmVPG5_VPG_ISRC1_2_ACCESS_CTRL_BASE_IDX 2
#define mmVPG5_VPG_ISRC1_2_DATA 0x256f
#define mmVPG5_VPG_ISRC1_2_DATA_BASE_IDX 2
#define mmVPG5_VPG_MPEG_INFO0 0x2570
#define mmVPG5_VPG_MPEG_INFO0_BASE_IDX 2
#define mmVPG5_VPG_MPEG_INFO1 0x2571
#define mmVPG5_VPG_MPEG_INFO1_BASE_IDX 2
// addressBlock: dce_dc_dio_dig5_afmt_afmt_dispdec
// base address: 0x168cc
#define mmAFMT5_AFMT_VBI_PACKET_CONTROL 0x2574
#define mmAFMT5_AFMT_VBI_PACKET_CONTROL_BASE_IDX 2
#define mmAFMT5_AFMT_AUDIO_PACKET_CONTROL2 0x2575
#define mmAFMT5_AFMT_AUDIO_PACKET_CONTROL2_BASE_IDX 2
#define mmAFMT5_AFMT_AUDIO_INFO0 0x2576
#define mmAFMT5_AFMT_AUDIO_INFO0_BASE_IDX 2
#define mmAFMT5_AFMT_AUDIO_INFO1 0x2577
#define mmAFMT5_AFMT_AUDIO_INFO1_BASE_IDX 2
#define mmAFMT5_AFMT_60958_0 0x2578
#define mmAFMT5_AFMT_60958_0_BASE_IDX 2
#define mmAFMT5_AFMT_60958_1 0x2579
#define mmAFMT5_AFMT_60958_1_BASE_IDX 2
#define mmAFMT5_AFMT_AUDIO_CRC_CONTROL 0x257a
#define mmAFMT5_AFMT_AUDIO_CRC_CONTROL_BASE_IDX 2
#define mmAFMT5_AFMT_RAMP_CONTROL0 0x257b
#define mmAFMT5_AFMT_RAMP_CONTROL0_BASE_IDX 2
#define mmAFMT5_AFMT_RAMP_CONTROL1 0x257c
#define mmAFMT5_AFMT_RAMP_CONTROL1_BASE_IDX 2
#define mmAFMT5_AFMT_RAMP_CONTROL2 0x257d
#define mmAFMT5_AFMT_RAMP_CONTROL2_BASE_IDX 2
#define mmAFMT5_AFMT_RAMP_CONTROL3 0x257e
#define mmAFMT5_AFMT_RAMP_CONTROL3_BASE_IDX 2
#define mmAFMT5_AFMT_60958_2 0x257f
#define mmAFMT5_AFMT_60958_2_BASE_IDX 2
#define mmAFMT5_AFMT_AUDIO_CRC_RESULT 0x2580
#define mmAFMT5_AFMT_AUDIO_CRC_RESULT_BASE_IDX 2
#define mmAFMT5_AFMT_STATUS 0x2581
#define mmAFMT5_AFMT_STATUS_BASE_IDX 2
#define mmAFMT5_AFMT_AUDIO_PACKET_CONTROL 0x2582
#define mmAFMT5_AFMT_AUDIO_PACKET_CONTROL_BASE_IDX 2
#define mmAFMT5_AFMT_INFOFRAME_CONTROL0 0x2583
#define mmAFMT5_AFMT_INFOFRAME_CONTROL0_BASE_IDX 2
#define mmAFMT5_AFMT_INTERRUPT_STATUS 0x2584
#define mmAFMT5_AFMT_INTERRUPT_STATUS_BASE_IDX 2
#define mmAFMT5_AFMT_AUDIO_SRC_CONTROL 0x2585
#define mmAFMT5_AFMT_AUDIO_SRC_CONTROL_BASE_IDX 2
#define mmAFMT5_AFMT_MEM_PWR 0x2587
#define mmAFMT5_AFMT_MEM_PWR_BASE_IDX 2
// addressBlock: dce_dc_dio_dig5_dispdec
// base address: 0x1400
#define mmDIG5_DIG_FE_CNTL 0x258b
#define mmDIG5_DIG_FE_CNTL_BASE_IDX 2
#define mmDIG5_DIG_OUTPUT_CRC_CNTL 0x258c
#define mmDIG5_DIG_OUTPUT_CRC_CNTL_BASE_IDX 2
#define mmDIG5_DIG_OUTPUT_CRC_RESULT 0x258d
#define mmDIG5_DIG_OUTPUT_CRC_RESULT_BASE_IDX 2
#define mmDIG5_DIG_CLOCK_PATTERN 0x258e
#define mmDIG5_DIG_CLOCK_PATTERN_BASE_IDX 2
#define mmDIG5_DIG_TEST_PATTERN 0x258f
#define mmDIG5_DIG_TEST_PATTERN_BASE_IDX 2
#define mmDIG5_DIG_RANDOM_PATTERN_SEED 0x2590
#define mmDIG5_DIG_RANDOM_PATTERN_SEED_BASE_IDX 2
#define mmDIG5_DIG_FIFO_STATUS 0x2591
#define mmDIG5_DIG_FIFO_STATUS_BASE_IDX 2
#define mmDIG5_HDMI_METADATA_PACKET_CONTROL 0x2592
#define mmDIG5_HDMI_METADATA_PACKET_CONTROL_BASE_IDX 2
#define mmDIG5_HDMI_CONTROL 0x2593
#define mmDIG5_HDMI_CONTROL_BASE_IDX 2
#define mmDIG5_HDMI_STATUS 0x2594
#define mmDIG5_HDMI_STATUS_BASE_IDX 2
#define mmDIG5_HDMI_AUDIO_PACKET_CONTROL 0x2595
#define mmDIG5_HDMI_AUDIO_PACKET_CONTROL_BASE_IDX 2
#define mmDIG5_HDMI_ACR_PACKET_CONTROL 0x2596
#define mmDIG5_HDMI_ACR_PACKET_CONTROL_BASE_IDX 2
#define mmDIG5_HDMI_VBI_PACKET_CONTROL 0x2597
#define mmDIG5_HDMI_VBI_PACKET_CONTROL_BASE_IDX 2
#define mmDIG5_HDMI_INFOFRAME_CONTROL0 0x2598
#define mmDIG5_HDMI_INFOFRAME_CONTROL0_BASE_IDX 2
#define mmDIG5_HDMI_INFOFRAME_CONTROL1 0x2599
#define mmDIG5_HDMI_INFOFRAME_CONTROL1_BASE_IDX 2
#define mmDIG5_HDMI_GENERIC_PACKET_CONTROL0 0x259a
#define mmDIG5_HDMI_GENERIC_PACKET_CONTROL0_BASE_IDX 2
#define mmDIG5_HDMI_GENERIC_PACKET_CONTROL6 0x259b
#define mmDIG5_HDMI_GENERIC_PACKET_CONTROL6_BASE_IDX 2
#define mmDIG5_HDMI_GENERIC_PACKET_CONTROL5 0x259c
#define mmDIG5_HDMI_GENERIC_PACKET_CONTROL5_BASE_IDX 2
#define mmDIG5_HDMI_GC 0x259d
#define mmDIG5_HDMI_GC_BASE_IDX 2
#define mmDIG5_HDMI_GENERIC_PACKET_CONTROL1 0x259e
#define mmDIG5_HDMI_GENERIC_PACKET_CONTROL1_BASE_IDX 2
#define mmDIG5_HDMI_GENERIC_PACKET_CONTROL2 0x259f
#define mmDIG5_HDMI_GENERIC_PACKET_CONTROL2_BASE_IDX 2
#define mmDIG5_HDMI_GENERIC_PACKET_CONTROL3 0x25a0
#define mmDIG5_HDMI_GENERIC_PACKET_CONTROL3_BASE_IDX 2
#define mmDIG5_HDMI_GENERIC_PACKET_CONTROL4 0x25a1
#define mmDIG5_HDMI_GENERIC_PACKET_CONTROL4_BASE_IDX 2
#define mmDIG5_HDMI_GENERIC_PACKET_CONTROL7 0x25a2
#define mmDIG5_HDMI_GENERIC_PACKET_CONTROL7_BASE_IDX 2
#define mmDIG5_HDMI_GENERIC_PACKET_CONTROL8 0x25a3
#define mmDIG5_HDMI_GENERIC_PACKET_CONTROL8_BASE_IDX 2
#define mmDIG5_HDMI_GENERIC_PACKET_CONTROL9 0x25a4
#define mmDIG5_HDMI_GENERIC_PACKET_CONTROL9_BASE_IDX 2
#define mmDIG5_HDMI_GENERIC_PACKET_CONTROL10 0x25a5
#define mmDIG5_HDMI_GENERIC_PACKET_CONTROL10_BASE_IDX 2
#define mmDIG5_HDMI_DB_CONTROL 0x25a6
#define mmDIG5_HDMI_DB_CONTROL_BASE_IDX 2
#define mmDIG5_HDMI_ACR_32_0 0x25a7
#define mmDIG5_HDMI_ACR_32_0_BASE_IDX 2
#define mmDIG5_HDMI_ACR_32_1 0x25a8
#define mmDIG5_HDMI_ACR_32_1_BASE_IDX 2
#define mmDIG5_HDMI_ACR_44_0 0x25a9
#define mmDIG5_HDMI_ACR_44_0_BASE_IDX 2
#define mmDIG5_HDMI_ACR_44_1 0x25aa
#define mmDIG5_HDMI_ACR_44_1_BASE_IDX 2
#define mmDIG5_HDMI_ACR_48_0 0x25ab
#define mmDIG5_HDMI_ACR_48_0_BASE_IDX 2
#define mmDIG5_HDMI_ACR_48_1 0x25ac
#define mmDIG5_HDMI_ACR_48_1_BASE_IDX 2
#define mmDIG5_HDMI_ACR_STATUS_0 0x25ad
#define mmDIG5_HDMI_ACR_STATUS_0_BASE_IDX 2
#define mmDIG5_HDMI_ACR_STATUS_1 0x25ae
#define mmDIG5_HDMI_ACR_STATUS_1_BASE_IDX 2
#define mmDIG5_AFMT_CNTL 0x25af
#define mmDIG5_AFMT_CNTL_BASE_IDX 2
#define mmDIG5_DIG_BE_CNTL 0x25b0
#define mmDIG5_DIG_BE_CNTL_BASE_IDX 2
#define mmDIG5_DIG_BE_EN_CNTL 0x25b1
#define mmDIG5_DIG_BE_EN_CNTL_BASE_IDX 2
#define mmDIG5_TMDS_CNTL 0x25d7
#define mmDIG5_TMDS_CNTL_BASE_IDX 2
#define mmDIG5_TMDS_CONTROL_CHAR 0x25d8
#define mmDIG5_TMDS_CONTROL_CHAR_BASE_IDX 2
#define mmDIG5_TMDS_CONTROL0_FEEDBACK 0x25d9
#define mmDIG5_TMDS_CONTROL0_FEEDBACK_BASE_IDX 2
#define mmDIG5_TMDS_STEREOSYNC_CTL_SEL 0x25da
#define mmDIG5_TMDS_STEREOSYNC_CTL_SEL_BASE_IDX 2
#define mmDIG5_TMDS_SYNC_CHAR_PATTERN_0_1 0x25db
#define mmDIG5_TMDS_SYNC_CHAR_PATTERN_0_1_BASE_IDX 2
#define mmDIG5_TMDS_SYNC_CHAR_PATTERN_2_3 0x25dc
#define mmDIG5_TMDS_SYNC_CHAR_PATTERN_2_3_BASE_IDX 2
#define mmDIG5_TMDS_CTL_BITS 0x25de
#define mmDIG5_TMDS_CTL_BITS_BASE_IDX 2
#define mmDIG5_TMDS_DCBALANCER_CONTROL 0x25df
#define mmDIG5_TMDS_DCBALANCER_CONTROL_BASE_IDX 2
#define mmDIG5_TMDS_SYNC_DCBALANCE_CHAR 0x25e0
#define mmDIG5_TMDS_SYNC_DCBALANCE_CHAR_BASE_IDX 2
#define mmDIG5_TMDS_CTL0_1_GEN_CNTL 0x25e1
#define mmDIG5_TMDS_CTL0_1_GEN_CNTL_BASE_IDX 2
#define mmDIG5_TMDS_CTL2_3_GEN_CNTL 0x25e2
#define mmDIG5_TMDS_CTL2_3_GEN_CNTL_BASE_IDX 2
#define mmDIG5_DIG_VERSION 0x25e4
#define mmDIG5_DIG_VERSION_BASE_IDX 2
#define mmDIG5_DIG_LANE_ENABLE 0x25e5
#define mmDIG5_DIG_LANE_ENABLE_BASE_IDX 2
#define mmDIG5_FORCE_DIG_DISABLE 0x25e6
#define mmDIG5_FORCE_DIG_DISABLE_BASE_IDX 2
// addressBlock: dce_dc_dio_dp5_dispdec
// base address: 0x1400
#define mmDP5_DP_LINK_CNTL 0x2608
#define mmDP5_DP_LINK_CNTL_BASE_IDX 2
#define mmDP5_DP_PIXEL_FORMAT 0x2609
#define mmDP5_DP_PIXEL_FORMAT_BASE_IDX 2
#define mmDP5_DP_MSA_COLORIMETRY 0x260a
#define mmDP5_DP_MSA_COLORIMETRY_BASE_IDX 2
#define mmDP5_DP_CONFIG 0x260b
#define mmDP5_DP_CONFIG_BASE_IDX 2
#define mmDP5_DP_VID_STREAM_CNTL 0x260c
#define mmDP5_DP_VID_STREAM_CNTL_BASE_IDX 2
#define mmDP5_DP_STEER_FIFO 0x260d
#define mmDP5_DP_STEER_FIFO_BASE_IDX 2
#define mmDP5_DP_MSA_MISC 0x260e
#define mmDP5_DP_MSA_MISC_BASE_IDX 2
#define mmDP5_DP_DPHY_INTERNAL_CTRL 0x260f
#define mmDP5_DP_DPHY_INTERNAL_CTRL_BASE_IDX 2
#define mmDP5_DP_VID_TIMING 0x2610
#define mmDP5_DP_VID_TIMING_BASE_IDX 2
#define mmDP5_DP_VID_N 0x2611
#define mmDP5_DP_VID_N_BASE_IDX 2
#define mmDP5_DP_VID_M 0x2612
#define mmDP5_DP_VID_M_BASE_IDX 2
#define mmDP5_DP_LINK_FRAMING_CNTL 0x2613
#define mmDP5_DP_LINK_FRAMING_CNTL_BASE_IDX 2
#define mmDP5_DP_HBR2_EYE_PATTERN 0x2614
#define mmDP5_DP_HBR2_EYE_PATTERN_BASE_IDX 2
#define mmDP5_DP_VID_MSA_VBID 0x2615
#define mmDP5_DP_VID_MSA_VBID_BASE_IDX 2
#define mmDP5_DP_VID_INTERRUPT_CNTL 0x2616
#define mmDP5_DP_VID_INTERRUPT_CNTL_BASE_IDX 2
#define mmDP5_DP_DPHY_CNTL 0x2617
#define mmDP5_DP_DPHY_CNTL_BASE_IDX 2
#define mmDP5_DP_DPHY_TRAINING_PATTERN_SEL 0x2618
#define mmDP5_DP_DPHY_TRAINING_PATTERN_SEL_BASE_IDX 2
#define mmDP5_DP_DPHY_SYM0 0x2619
#define mmDP5_DP_DPHY_SYM0_BASE_IDX 2
#define mmDP5_DP_DPHY_SYM1 0x261a
#define mmDP5_DP_DPHY_SYM1_BASE_IDX 2
#define mmDP5_DP_DPHY_SYM2 0x261b
#define mmDP5_DP_DPHY_SYM2_BASE_IDX 2
#define mmDP5_DP_DPHY_8B10B_CNTL 0x261c
#define mmDP5_DP_DPHY_8B10B_CNTL_BASE_IDX 2
#define mmDP5_DP_DPHY_PRBS_CNTL 0x261d
#define mmDP5_DP_DPHY_PRBS_CNTL_BASE_IDX 2
#define mmDP5_DP_DPHY_SCRAM_CNTL 0x261e
#define mmDP5_DP_DPHY_SCRAM_CNTL_BASE_IDX 2
#define mmDP5_DP_DPHY_CRC_EN 0x261f
#define mmDP5_DP_DPHY_CRC_EN_BASE_IDX 2
#define mmDP5_DP_DPHY_CRC_CNTL 0x2620
#define mmDP5_DP_DPHY_CRC_CNTL_BASE_IDX 2
#define mmDP5_DP_DPHY_CRC_RESULT 0x2621
#define mmDP5_DP_DPHY_CRC_RESULT_BASE_IDX 2
#define mmDP5_DP_DPHY_CRC_MST_CNTL 0x2622
#define mmDP5_DP_DPHY_CRC_MST_CNTL_BASE_IDX 2
#define mmDP5_DP_DPHY_CRC_MST_STATUS 0x2623
#define mmDP5_DP_DPHY_CRC_MST_STATUS_BASE_IDX 2
#define mmDP5_DP_DPHY_FAST_TRAINING 0x2624
#define mmDP5_DP_DPHY_FAST_TRAINING_BASE_IDX 2
#define mmDP5_DP_DPHY_FAST_TRAINING_STATUS 0x2625
#define mmDP5_DP_DPHY_FAST_TRAINING_STATUS_BASE_IDX 2
#define mmDP5_DP_SEC_CNTL 0x262b
#define mmDP5_DP_SEC_CNTL_BASE_IDX 2
#define mmDP5_DP_SEC_CNTL1 0x262c
#define mmDP5_DP_SEC_CNTL1_BASE_IDX 2
#define mmDP5_DP_SEC_FRAMING1 0x262d
#define mmDP5_DP_SEC_FRAMING1_BASE_IDX 2
#define mmDP5_DP_SEC_FRAMING2 0x262e
#define mmDP5_DP_SEC_FRAMING2_BASE_IDX 2
#define mmDP5_DP_SEC_FRAMING3 0x262f
#define mmDP5_DP_SEC_FRAMING3_BASE_IDX 2
#define mmDP5_DP_SEC_FRAMING4 0x2630
#define mmDP5_DP_SEC_FRAMING4_BASE_IDX 2
#define mmDP5_DP_SEC_AUD_N 0x2631
#define mmDP5_DP_SEC_AUD_N_BASE_IDX 2
#define mmDP5_DP_SEC_AUD_N_READBACK 0x2632
#define mmDP5_DP_SEC_AUD_N_READBACK_BASE_IDX 2
#define mmDP5_DP_SEC_AUD_M 0x2633
#define mmDP5_DP_SEC_AUD_M_BASE_IDX 2
#define mmDP5_DP_SEC_AUD_M_READBACK 0x2634
#define mmDP5_DP_SEC_AUD_M_READBACK_BASE_IDX 2
#define mmDP5_DP_SEC_TIMESTAMP 0x2635
#define mmDP5_DP_SEC_TIMESTAMP_BASE_IDX 2
#define mmDP5_DP_SEC_PACKET_CNTL 0x2636
#define mmDP5_DP_SEC_PACKET_CNTL_BASE_IDX 2
#define mmDP5_DP_MSE_RATE_CNTL 0x2637
#define mmDP5_DP_MSE_RATE_CNTL_BASE_IDX 2
#define mmDP5_DP_MSE_RATE_UPDATE 0x2639
#define mmDP5_DP_MSE_RATE_UPDATE_BASE_IDX 2
#define mmDP5_DP_MSE_SAT0 0x263a
#define mmDP5_DP_MSE_SAT0_BASE_IDX 2
#define mmDP5_DP_MSE_SAT1 0x263b
#define mmDP5_DP_MSE_SAT1_BASE_IDX 2
#define mmDP5_DP_MSE_SAT2 0x263c
#define mmDP5_DP_MSE_SAT2_BASE_IDX 2
#define mmDP5_DP_MSE_SAT_UPDATE 0x263d
#define mmDP5_DP_MSE_SAT_UPDATE_BASE_IDX 2
#define mmDP5_DP_MSE_LINK_TIMING 0x263e
#define mmDP5_DP_MSE_LINK_TIMING_BASE_IDX 2
#define mmDP5_DP_MSE_MISC_CNTL 0x263f
#define mmDP5_DP_MSE_MISC_CNTL_BASE_IDX 2
#define mmDP5_DP_DPHY_BS_SR_SWAP_CNTL 0x2644
#define mmDP5_DP_DPHY_BS_SR_SWAP_CNTL_BASE_IDX 2
#define mmDP5_DP_DPHY_HBR2_PATTERN_CONTROL 0x2645
#define mmDP5_DP_DPHY_HBR2_PATTERN_CONTROL_BASE_IDX 2
#define mmDP5_DP_MSE_SAT0_STATUS 0x2647
#define mmDP5_DP_MSE_SAT0_STATUS_BASE_IDX 2
#define mmDP5_DP_MSE_SAT1_STATUS 0x2648
#define mmDP5_DP_MSE_SAT1_STATUS_BASE_IDX 2
#define mmDP5_DP_MSE_SAT2_STATUS 0x2649
#define mmDP5_DP_MSE_SAT2_STATUS_BASE_IDX 2
#define mmDP5_DP_MSA_TIMING_PARAM1 0x264c
#define mmDP5_DP_MSA_TIMING_PARAM1_BASE_IDX 2
#define mmDP5_DP_MSA_TIMING_PARAM2 0x264d
#define mmDP5_DP_MSA_TIMING_PARAM2_BASE_IDX 2
#define mmDP5_DP_MSA_TIMING_PARAM3 0x264e
#define mmDP5_DP_MSA_TIMING_PARAM3_BASE_IDX 2
#define mmDP5_DP_MSA_TIMING_PARAM4 0x264f
#define mmDP5_DP_MSA_TIMING_PARAM4_BASE_IDX 2
#define mmDP5_DP_MSO_CNTL 0x2650
#define mmDP5_DP_MSO_CNTL_BASE_IDX 2
#define mmDP5_DP_MSO_CNTL1 0x2651
#define mmDP5_DP_MSO_CNTL1_BASE_IDX 2
#define mmDP5_DP_DSC_CNTL 0x2652
#define mmDP5_DP_DSC_CNTL_BASE_IDX 2
#define mmDP5_DP_SEC_CNTL2 0x2653
#define mmDP5_DP_SEC_CNTL2_BASE_IDX 2
#define mmDP5_DP_SEC_CNTL3 0x2654
#define mmDP5_DP_SEC_CNTL3_BASE_IDX 2
#define mmDP5_DP_SEC_CNTL4 0x2655
#define mmDP5_DP_SEC_CNTL4_BASE_IDX 2
#define mmDP5_DP_SEC_CNTL5 0x2656
#define mmDP5_DP_SEC_CNTL5_BASE_IDX 2
#define mmDP5_DP_SEC_CNTL6 0x2657
#define mmDP5_DP_SEC_CNTL6_BASE_IDX 2
#define mmDP5_DP_SEC_CNTL7 0x2658
#define mmDP5_DP_SEC_CNTL7_BASE_IDX 2
#define mmDP5_DP_DB_CNTL 0x2659
#define mmDP5_DP_DB_CNTL_BASE_IDX 2
#define mmDP5_DP_MSA_VBID_MISC 0x265a
#define mmDP5_DP_MSA_VBID_MISC_BASE_IDX 2
#define mmDP5_DP_SEC_METADATA_TRANSMISSION 0x265b
#define mmDP5_DP_SEC_METADATA_TRANSMISSION_BASE_IDX 2
#define mmDP5_DP_DSC_BYTES_PER_PIXEL 0x265c
#define mmDP5_DP_DSC_BYTES_PER_PIXEL_BASE_IDX 2
#define mmDP5_DP_ALPM_CNTL 0x265d
#define mmDP5_DP_ALPM_CNTL_BASE_IDX 2
#define mmDP5_DP_GSP8_CNTL 0x265e
#define mmDP5_DP_GSP8_CNTL_BASE_IDX 2
#define mmDP5_DP_GSP9_CNTL 0x265f
#define mmDP5_DP_GSP9_CNTL_BASE_IDX 2
#define mmDP5_DP_GSP10_CNTL 0x2660
#define mmDP5_DP_GSP10_CNTL_BASE_IDX 2
#define mmDP5_DP_GSP11_CNTL 0x2661
#define mmDP5_DP_GSP11_CNTL_BASE_IDX 2
#define mmDP5_DP_GSP_EN_DB_STATUS 0x2662
#define mmDP5_DP_GSP_EN_DB_STATUS_BASE_IDX 2
// addressBlock: dce_dc_dcio_dcio_dispdec
// base address: 0x0
#define mmDC_GENERICA 0x2868
#define mmDC_GENERICA_BASE_IDX 2
#define mmDC_GENERICB 0x2869
#define mmDC_GENERICB_BASE_IDX 2
#define mmDCIO_CLOCK_CNTL 0x286a
#define mmDCIO_CLOCK_CNTL_BASE_IDX 2
#define mmDC_REF_CLK_CNTL 0x286b
#define mmDC_REF_CLK_CNTL_BASE_IDX 2
#define mmUNIPHYA_LINK_CNTL 0x286d
#define mmUNIPHYA_LINK_CNTL_BASE_IDX 2
#define mmUNIPHYA_CHANNEL_XBAR_CNTL 0x286e
#define mmUNIPHYA_CHANNEL_XBAR_CNTL_BASE_IDX 2
#define mmUNIPHYB_LINK_CNTL 0x286f
#define mmUNIPHYB_LINK_CNTL_BASE_IDX 2
#define mmUNIPHYB_CHANNEL_XBAR_CNTL 0x2870
#define mmUNIPHYB_CHANNEL_XBAR_CNTL_BASE_IDX 2
#define mmUNIPHYC_LINK_CNTL 0x2871
#define mmUNIPHYC_LINK_CNTL_BASE_IDX 2
#define mmUNIPHYC_CHANNEL_XBAR_CNTL 0x2872
#define mmUNIPHYC_CHANNEL_XBAR_CNTL_BASE_IDX 2
#define mmUNIPHYD_LINK_CNTL 0x2873
#define mmUNIPHYD_LINK_CNTL_BASE_IDX 2
#define mmUNIPHYD_CHANNEL_XBAR_CNTL 0x2874
#define mmUNIPHYD_CHANNEL_XBAR_CNTL_BASE_IDX 2
#define mmUNIPHYE_LINK_CNTL 0x2875
#define mmUNIPHYE_LINK_CNTL_BASE_IDX 2
#define mmUNIPHYE_CHANNEL_XBAR_CNTL 0x2876
#define mmUNIPHYE_CHANNEL_XBAR_CNTL_BASE_IDX 2
#define mmDCIO_WRCMD_DELAY 0x287e
#define mmDCIO_WRCMD_DELAY_BASE_IDX 2
#define mmDC_PINSTRAPS 0x2880
#define mmDC_PINSTRAPS_BASE_IDX 2
#define mmLVTMA_PWRSEQ_CNTL 0x2883
#define mmLVTMA_PWRSEQ_CNTL_BASE_IDX 2
#define mmLVTMA_PWRSEQ_STATE 0x2884
#define mmLVTMA_PWRSEQ_STATE_BASE_IDX 2
#define mmLVTMA_PWRSEQ_REF_DIV 0x2885
#define mmLVTMA_PWRSEQ_REF_DIV_BASE_IDX 2
#define mmLVTMA_PWRSEQ_DELAY1 0x2886
#define mmLVTMA_PWRSEQ_DELAY1_BASE_IDX 2
#define mmLVTMA_PWRSEQ_DELAY2 0x2887
#define mmLVTMA_PWRSEQ_DELAY2_BASE_IDX 2
#define mmBL_PWM_CNTL 0x2888
#define mmBL_PWM_CNTL_BASE_IDX 2
#define mmBL_PWM_CNTL2 0x2889
#define mmBL_PWM_CNTL2_BASE_IDX 2
#define mmBL_PWM_PERIOD_CNTL 0x288a
#define mmBL_PWM_PERIOD_CNTL_BASE_IDX 2
#define mmBL_PWM_GRP1_REG_LOCK 0x288b
#define mmBL_PWM_GRP1_REG_LOCK_BASE_IDX 2
#define mmDCIO_GSL_GENLK_PAD_CNTL 0x288c
#define mmDCIO_GSL_GENLK_PAD_CNTL_BASE_IDX 2
#define mmDCIO_GSL_SWAPLOCK_PAD_CNTL 0x288d
#define mmDCIO_GSL_SWAPLOCK_PAD_CNTL_BASE_IDX 2
#define mmDCIO_SOFT_RESET 0x289e
#define mmDCIO_SOFT_RESET_BASE_IDX 2
// addressBlock: dce_dc_dcio_dcio_chip_dispdec
// base address: 0x0
#define mmDC_GPIO_GENERIC_MASK 0x28c8
#define mmDC_GPIO_GENERIC_MASK_BASE_IDX 2
#define mmDC_GPIO_GENERIC_A 0x28c9
#define mmDC_GPIO_GENERIC_A_BASE_IDX 2
#define mmDC_GPIO_GENERIC_EN 0x28ca
#define mmDC_GPIO_GENERIC_EN_BASE_IDX 2
#define mmDC_GPIO_GENERIC_Y 0x28cb
#define mmDC_GPIO_GENERIC_Y_BASE_IDX 2
#define mmDC_GPIO_DDC1_MASK 0x28d0
#define mmDC_GPIO_DDC1_MASK_BASE_IDX 2
#define mmDC_GPIO_DDC1_A 0x28d1
#define mmDC_GPIO_DDC1_A_BASE_IDX 2
#define mmDC_GPIO_DDC1_EN 0x28d2
#define mmDC_GPIO_DDC1_EN_BASE_IDX 2
#define mmDC_GPIO_DDC1_Y 0x28d3
#define mmDC_GPIO_DDC1_Y_BASE_IDX 2
#define mmDC_GPIO_DDC2_MASK 0x28d4
#define mmDC_GPIO_DDC2_MASK_BASE_IDX 2
#define mmDC_GPIO_DDC2_A 0x28d5
#define mmDC_GPIO_DDC2_A_BASE_IDX 2
#define mmDC_GPIO_DDC2_EN 0x28d6
#define mmDC_GPIO_DDC2_EN_BASE_IDX 2
#define mmDC_GPIO_DDC2_Y 0x28d7
#define mmDC_GPIO_DDC2_Y_BASE_IDX 2
#define mmDC_GPIO_DDC3_MASK 0x28d8
#define mmDC_GPIO_DDC3_MASK_BASE_IDX 2
#define mmDC_GPIO_DDC3_A 0x28d9
#define mmDC_GPIO_DDC3_A_BASE_IDX 2
#define mmDC_GPIO_DDC3_EN 0x28da
#define mmDC_GPIO_DDC3_EN_BASE_IDX 2
#define mmDC_GPIO_DDC3_Y 0x28db
#define mmDC_GPIO_DDC3_Y_BASE_IDX 2
#define mmDC_GPIO_DDC4_MASK 0x28dc
#define mmDC_GPIO_DDC4_MASK_BASE_IDX 2
#define mmDC_GPIO_DDC4_A 0x28dd
#define mmDC_GPIO_DDC4_A_BASE_IDX 2
#define mmDC_GPIO_DDC4_EN 0x28de
#define mmDC_GPIO_DDC4_EN_BASE_IDX 2
#define mmDC_GPIO_DDC4_Y 0x28df
#define mmDC_GPIO_DDC4_Y_BASE_IDX 2
#define mmDC_GPIO_DDC5_MASK 0x28e0
#define mmDC_GPIO_DDC5_MASK_BASE_IDX 2
#define mmDC_GPIO_DDC5_A 0x28e1
#define mmDC_GPIO_DDC5_A_BASE_IDX 2
#define mmDC_GPIO_DDC5_EN 0x28e2
#define mmDC_GPIO_DDC5_EN_BASE_IDX 2
#define mmDC_GPIO_DDC5_Y 0x28e3
#define mmDC_GPIO_DDC5_Y_BASE_IDX 2
#define mmDC_GPIO_DDCVGA_MASK 0x28e8
#define mmDC_GPIO_DDCVGA_MASK_BASE_IDX 2
#define mmDC_GPIO_DDCVGA_A 0x28e9
#define mmDC_GPIO_DDCVGA_A_BASE_IDX 2
#define mmDC_GPIO_DDCVGA_EN 0x28ea
#define mmDC_GPIO_DDCVGA_EN_BASE_IDX 2
#define mmDC_GPIO_DDCVGA_Y 0x28eb
#define mmDC_GPIO_DDCVGA_Y_BASE_IDX 2
#define mmDC_GPIO_GENLK_MASK 0x28f0
#define mmDC_GPIO_GENLK_MASK_BASE_IDX 2
#define mmDC_GPIO_GENLK_A 0x28f1
#define mmDC_GPIO_GENLK_A_BASE_IDX 2
#define mmDC_GPIO_GENLK_EN 0x28f2
#define mmDC_GPIO_GENLK_EN_BASE_IDX 2
#define mmDC_GPIO_GENLK_Y 0x28f3
#define mmDC_GPIO_GENLK_Y_BASE_IDX 2
#define mmDC_GPIO_HPD_MASK 0x28f4
#define mmDC_GPIO_HPD_MASK_BASE_IDX 2
#define mmDC_GPIO_HPD_A 0x28f5
#define mmDC_GPIO_HPD_A_BASE_IDX 2
#define mmDC_GPIO_HPD_EN 0x28f6
#define mmDC_GPIO_HPD_EN_BASE_IDX 2
#define mmDC_GPIO_HPD_Y 0x28f7
#define mmDC_GPIO_HPD_Y_BASE_IDX 2
#define mmDC_GPIO_PWRSEQ_MASK 0x28f8
#define mmDC_GPIO_PWRSEQ_MASK_BASE_IDX 2
#define mmDC_GPIO_PWRSEQ_A 0x28f9
#define mmDC_GPIO_PWRSEQ_A_BASE_IDX 2
#define mmDC_GPIO_PWRSEQ_EN 0x28fa
#define mmDC_GPIO_PWRSEQ_EN_BASE_IDX 2
#define mmDC_GPIO_PWRSEQ_Y 0x28fb
#define mmDC_GPIO_PWRSEQ_Y_BASE_IDX 2
#define mmDC_GPIO_PAD_STRENGTH_1 0x28fc
#define mmDC_GPIO_PAD_STRENGTH_1_BASE_IDX 2
#define mmDC_GPIO_PAD_STRENGTH_2 0x28fd
#define mmDC_GPIO_PAD_STRENGTH_2_BASE_IDX 2
#define mmPHY_AUX_CNTL 0x28ff
#define mmPHY_AUX_CNTL_BASE_IDX 2
#define mmDC_GPIO_TX12_EN 0x2915
#define mmDC_GPIO_TX12_EN_BASE_IDX 2
#define mmDC_GPIO_AUX_CTRL_0 0x2916
#define mmDC_GPIO_AUX_CTRL_0_BASE_IDX 2
#define mmDC_GPIO_AUX_CTRL_1 0x2917
#define mmDC_GPIO_AUX_CTRL_1_BASE_IDX 2
#define mmDC_GPIO_AUX_CTRL_2 0x2918
#define mmDC_GPIO_AUX_CTRL_2_BASE_IDX 2
#define mmDC_GPIO_RXEN 0x2919
#define mmDC_GPIO_RXEN_BASE_IDX 2
#define mmDC_GPIO_PULLUPEN 0x291a
#define mmDC_GPIO_PULLUPEN_BASE_IDX 2
#define mmDC_GPIO_AUX_CTRL_3 0x291b
#define mmDC_GPIO_AUX_CTRL_3_BASE_IDX 2
#define mmDC_GPIO_AUX_CTRL_4 0x291c
#define mmDC_GPIO_AUX_CTRL_4_BASE_IDX 2
#define mmDC_GPIO_AUX_CTRL_5 0x291d
#define mmDC_GPIO_AUX_CTRL_5_BASE_IDX 2
#define mmAUXI2C_PAD_ALL_PWR_OK 0x291e
#define mmAUXI2C_PAD_ALL_PWR_OK_BASE_IDX 2
// addressBlock: dce_dc_dsc0_dispdec_dsc_top_dispdec
// base address: 0x0
#define mmDSC_TOP0_DSC_TOP_CONTROL 0x3000
#define mmDSC_TOP0_DSC_TOP_CONTROL_BASE_IDX 2
#define mmDSC_TOP0_DSC_DEBUG_CONTROL 0x3001
#define mmDSC_TOP0_DSC_DEBUG_CONTROL_BASE_IDX 2
// addressBlock: dce_dc_dsc0_dispdec_dsccif_dispdec
// base address: 0x0
#define mmDSCCIF0_DSCCIF_CONFIG0 0x3005
#define mmDSCCIF0_DSCCIF_CONFIG0_BASE_IDX 2
#define mmDSCCIF0_DSCCIF_CONFIG1 0x3006
#define mmDSCCIF0_DSCCIF_CONFIG1_BASE_IDX 2
// addressBlock: dce_dc_dsc0_dispdec_dscc_dispdec
// base address: 0x0
#define mmDSCC0_DSCC_CONFIG0 0x300a
#define mmDSCC0_DSCC_CONFIG0_BASE_IDX 2
#define mmDSCC0_DSCC_CONFIG1 0x300b
#define mmDSCC0_DSCC_CONFIG1_BASE_IDX 2
#define mmDSCC0_DSCC_STATUS 0x300c
#define mmDSCC0_DSCC_STATUS_BASE_IDX 2
#define mmDSCC0_DSCC_INTERRUPT_CONTROL_STATUS 0x300d
#define mmDSCC0_DSCC_INTERRUPT_CONTROL_STATUS_BASE_IDX 2
#define mmDSCC0_DSCC_PPS_CONFIG0 0x300e
#define mmDSCC0_DSCC_PPS_CONFIG0_BASE_IDX 2
#define mmDSCC0_DSCC_PPS_CONFIG1 0x300f
#define mmDSCC0_DSCC_PPS_CONFIG1_BASE_IDX 2
#define mmDSCC0_DSCC_PPS_CONFIG2 0x3010
#define mmDSCC0_DSCC_PPS_CONFIG2_BASE_IDX 2
#define mmDSCC0_DSCC_PPS_CONFIG3 0x3011
#define mmDSCC0_DSCC_PPS_CONFIG3_BASE_IDX 2
#define mmDSCC0_DSCC_PPS_CONFIG4 0x3012
#define mmDSCC0_DSCC_PPS_CONFIG4_BASE_IDX 2
#define mmDSCC0_DSCC_PPS_CONFIG5 0x3013
#define mmDSCC0_DSCC_PPS_CONFIG5_BASE_IDX 2
#define mmDSCC0_DSCC_PPS_CONFIG6 0x3014
#define mmDSCC0_DSCC_PPS_CONFIG6_BASE_IDX 2
#define mmDSCC0_DSCC_PPS_CONFIG7 0x3015
#define mmDSCC0_DSCC_PPS_CONFIG7_BASE_IDX 2
#define mmDSCC0_DSCC_PPS_CONFIG8 0x3016
#define mmDSCC0_DSCC_PPS_CONFIG8_BASE_IDX 2
#define mmDSCC0_DSCC_PPS_CONFIG9 0x3017
#define mmDSCC0_DSCC_PPS_CONFIG9_BASE_IDX 2
#define mmDSCC0_DSCC_PPS_CONFIG10 0x3018
#define mmDSCC0_DSCC_PPS_CONFIG10_BASE_IDX 2
#define mmDSCC0_DSCC_PPS_CONFIG11 0x3019
#define mmDSCC0_DSCC_PPS_CONFIG11_BASE_IDX 2
#define mmDSCC0_DSCC_PPS_CONFIG12 0x301a
#define mmDSCC0_DSCC_PPS_CONFIG12_BASE_IDX 2
#define mmDSCC0_DSCC_PPS_CONFIG13 0x301b
#define mmDSCC0_DSCC_PPS_CONFIG13_BASE_IDX 2
#define mmDSCC0_DSCC_PPS_CONFIG14 0x301c
#define mmDSCC0_DSCC_PPS_CONFIG14_BASE_IDX 2
#define mmDSCC0_DSCC_PPS_CONFIG15 0x301d
#define mmDSCC0_DSCC_PPS_CONFIG15_BASE_IDX 2
#define mmDSCC0_DSCC_PPS_CONFIG16 0x301e
#define mmDSCC0_DSCC_PPS_CONFIG16_BASE_IDX 2
#define mmDSCC0_DSCC_PPS_CONFIG17 0x301f
#define mmDSCC0_DSCC_PPS_CONFIG17_BASE_IDX 2
#define mmDSCC0_DSCC_PPS_CONFIG18 0x3020
#define mmDSCC0_DSCC_PPS_CONFIG18_BASE_IDX 2
#define mmDSCC0_DSCC_PPS_CONFIG19 0x3021
#define mmDSCC0_DSCC_PPS_CONFIG19_BASE_IDX 2
#define mmDSCC0_DSCC_PPS_CONFIG20 0x3022
#define mmDSCC0_DSCC_PPS_CONFIG20_BASE_IDX 2
#define mmDSCC0_DSCC_PPS_CONFIG21 0x3023
#define mmDSCC0_DSCC_PPS_CONFIG21_BASE_IDX 2
#define mmDSCC0_DSCC_PPS_CONFIG22 0x3024
#define mmDSCC0_DSCC_PPS_CONFIG22_BASE_IDX 2
#define mmDSCC0_DSCC_MEM_POWER_CONTROL 0x3025
#define mmDSCC0_DSCC_MEM_POWER_CONTROL_BASE_IDX 2
#define mmDSCC0_DSCC_R_Y_SQUARED_ERROR_LOWER 0x3026
#define mmDSCC0_DSCC_R_Y_SQUARED_ERROR_LOWER_BASE_IDX 2
#define mmDSCC0_DSCC_R_Y_SQUARED_ERROR_UPPER 0x3027
#define mmDSCC0_DSCC_R_Y_SQUARED_ERROR_UPPER_BASE_IDX 2
#define mmDSCC0_DSCC_G_CB_SQUARED_ERROR_LOWER 0x3028
#define mmDSCC0_DSCC_G_CB_SQUARED_ERROR_LOWER_BASE_IDX 2
#define mmDSCC0_DSCC_G_CB_SQUARED_ERROR_UPPER 0x3029
#define mmDSCC0_DSCC_G_CB_SQUARED_ERROR_UPPER_BASE_IDX 2
#define mmDSCC0_DSCC_B_CR_SQUARED_ERROR_LOWER 0x302a
#define mmDSCC0_DSCC_B_CR_SQUARED_ERROR_LOWER_BASE_IDX 2
#define mmDSCC0_DSCC_B_CR_SQUARED_ERROR_UPPER 0x302b
#define mmDSCC0_DSCC_B_CR_SQUARED_ERROR_UPPER_BASE_IDX 2
#define mmDSCC0_DSCC_MAX_ABS_ERROR0 0x302c
#define mmDSCC0_DSCC_MAX_ABS_ERROR0_BASE_IDX 2
#define mmDSCC0_DSCC_MAX_ABS_ERROR1 0x302d
#define mmDSCC0_DSCC_MAX_ABS_ERROR1_BASE_IDX 2
#define mmDSCC0_DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL 0x302e
#define mmDSCC0_DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL_BASE_IDX 2
#define mmDSCC0_DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL 0x302f
#define mmDSCC0_DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL_BASE_IDX 2
#define mmDSCC0_DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL 0x3030
#define mmDSCC0_DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL_BASE_IDX 2
#define mmDSCC0_DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL 0x3031
#define mmDSCC0_DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL_BASE_IDX 2
#define mmDSCC0_DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL 0x3032
#define mmDSCC0_DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL_BASE_IDX 2
#define mmDSCC0_DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL 0x3033
#define mmDSCC0_DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL_BASE_IDX 2
#define mmDSCC0_DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL 0x3034
#define mmDSCC0_DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL_BASE_IDX 2
#define mmDSCC0_DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL 0x3035
#define mmDSCC0_DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL_BASE_IDX 2
// addressBlock: dce_dc_dsc0_dispdec_dsc_dcperfmon_dc_perfmon_dispdec
// base address: 0xc140
#define mmDC_PERFMON19_PERFCOUNTER_CNTL 0x3050
#define mmDC_PERFMON19_PERFCOUNTER_CNTL_BASE_IDX 2
#define mmDC_PERFMON19_PERFCOUNTER_CNTL2 0x3051
#define mmDC_PERFMON19_PERFCOUNTER_CNTL2_BASE_IDX 2
#define mmDC_PERFMON19_PERFCOUNTER_STATE 0x3052
#define mmDC_PERFMON19_PERFCOUNTER_STATE_BASE_IDX 2
#define mmDC_PERFMON19_PERFMON_CNTL 0x3053
#define mmDC_PERFMON19_PERFMON_CNTL_BASE_IDX 2
#define mmDC_PERFMON19_PERFMON_CNTL2 0x3054
#define mmDC_PERFMON19_PERFMON_CNTL2_BASE_IDX 2
#define mmDC_PERFMON19_PERFMON_CVALUE_INT_MISC 0x3055
#define mmDC_PERFMON19_PERFMON_CVALUE_INT_MISC_BASE_IDX 2
#define mmDC_PERFMON19_PERFMON_CVALUE_LOW 0x3056
#define mmDC_PERFMON19_PERFMON_CVALUE_LOW_BASE_IDX 2
#define mmDC_PERFMON19_PERFMON_HI 0x3057
#define mmDC_PERFMON19_PERFMON_HI_BASE_IDX 2
#define mmDC_PERFMON19_PERFMON_LOW 0x3058
#define mmDC_PERFMON19_PERFMON_LOW_BASE_IDX 2
// addressBlock: dce_dc_dsc1_dispdec_dsc_top_dispdec
// base address: 0x170
#define mmDSC_TOP1_DSC_TOP_CONTROL 0x305c
#define mmDSC_TOP1_DSC_TOP_CONTROL_BASE_IDX 2
#define mmDSC_TOP1_DSC_DEBUG_CONTROL 0x305d
#define mmDSC_TOP1_DSC_DEBUG_CONTROL_BASE_IDX 2
// addressBlock: dce_dc_dsc1_dispdec_dsccif_dispdec
// base address: 0x170
#define mmDSCCIF1_DSCCIF_CONFIG0 0x3061
#define mmDSCCIF1_DSCCIF_CONFIG0_BASE_IDX 2
#define mmDSCCIF1_DSCCIF_CONFIG1 0x3062
#define mmDSCCIF1_DSCCIF_CONFIG1_BASE_IDX 2
// addressBlock: dce_dc_dsc1_dispdec_dscc_dispdec
// base address: 0x170
#define mmDSCC1_DSCC_CONFIG0 0x3066
#define mmDSCC1_DSCC_CONFIG0_BASE_IDX 2
#define mmDSCC1_DSCC_CONFIG1 0x3067
#define mmDSCC1_DSCC_CONFIG1_BASE_IDX 2
#define mmDSCC1_DSCC_STATUS 0x3068
#define mmDSCC1_DSCC_STATUS_BASE_IDX 2
#define mmDSCC1_DSCC_INTERRUPT_CONTROL_STATUS 0x3069
#define mmDSCC1_DSCC_INTERRUPT_CONTROL_STATUS_BASE_IDX 2
#define mmDSCC1_DSCC_PPS_CONFIG0 0x306a
#define mmDSCC1_DSCC_PPS_CONFIG0_BASE_IDX 2
#define mmDSCC1_DSCC_PPS_CONFIG1 0x306b
#define mmDSCC1_DSCC_PPS_CONFIG1_BASE_IDX 2
#define mmDSCC1_DSCC_PPS_CONFIG2 0x306c
#define mmDSCC1_DSCC_PPS_CONFIG2_BASE_IDX 2
#define mmDSCC1_DSCC_PPS_CONFIG3 0x306d
#define mmDSCC1_DSCC_PPS_CONFIG3_BASE_IDX 2
#define mmDSCC1_DSCC_PPS_CONFIG4 0x306e
#define mmDSCC1_DSCC_PPS_CONFIG4_BASE_IDX 2
#define mmDSCC1_DSCC_PPS_CONFIG5 0x306f
#define mmDSCC1_DSCC_PPS_CONFIG5_BASE_IDX 2
#define mmDSCC1_DSCC_PPS_CONFIG6 0x3070
#define mmDSCC1_DSCC_PPS_CONFIG6_BASE_IDX 2
#define mmDSCC1_DSCC_PPS_CONFIG7 0x3071
#define mmDSCC1_DSCC_PPS_CONFIG7_BASE_IDX 2
#define mmDSCC1_DSCC_PPS_CONFIG8 0x3072
#define mmDSCC1_DSCC_PPS_CONFIG8_BASE_IDX 2
#define mmDSCC1_DSCC_PPS_CONFIG9 0x3073
#define mmDSCC1_DSCC_PPS_CONFIG9_BASE_IDX 2
#define mmDSCC1_DSCC_PPS_CONFIG10 0x3074
#define mmDSCC1_DSCC_PPS_CONFIG10_BASE_IDX 2
#define mmDSCC1_DSCC_PPS_CONFIG11 0x3075
#define mmDSCC1_DSCC_PPS_CONFIG11_BASE_IDX 2
#define mmDSCC1_DSCC_PPS_CONFIG12 0x3076
#define mmDSCC1_DSCC_PPS_CONFIG12_BASE_IDX 2
#define mmDSCC1_DSCC_PPS_CONFIG13 0x3077
#define mmDSCC1_DSCC_PPS_CONFIG13_BASE_IDX 2
#define mmDSCC1_DSCC_PPS_CONFIG14 0x3078
#define mmDSCC1_DSCC_PPS_CONFIG14_BASE_IDX 2
#define mmDSCC1_DSCC_PPS_CONFIG15 0x3079
#define mmDSCC1_DSCC_PPS_CONFIG15_BASE_IDX 2
#define mmDSCC1_DSCC_PPS_CONFIG16 0x307a
#define mmDSCC1_DSCC_PPS_CONFIG16_BASE_IDX 2
#define mmDSCC1_DSCC_PPS_CONFIG17 0x307b
#define mmDSCC1_DSCC_PPS_CONFIG17_BASE_IDX 2
#define mmDSCC1_DSCC_PPS_CONFIG18 0x307c
#define mmDSCC1_DSCC_PPS_CONFIG18_BASE_IDX 2
#define mmDSCC1_DSCC_PPS_CONFIG19 0x307d
#define mmDSCC1_DSCC_PPS_CONFIG19_BASE_IDX 2
#define mmDSCC1_DSCC_PPS_CONFIG20 0x307e
#define mmDSCC1_DSCC_PPS_CONFIG20_BASE_IDX 2
#define mmDSCC1_DSCC_PPS_CONFIG21 0x307f
#define mmDSCC1_DSCC_PPS_CONFIG21_BASE_IDX 2
#define mmDSCC1_DSCC_PPS_CONFIG22 0x3080
#define mmDSCC1_DSCC_PPS_CONFIG22_BASE_IDX 2
#define mmDSCC1_DSCC_MEM_POWER_CONTROL 0x3081
#define mmDSCC1_DSCC_MEM_POWER_CONTROL_BASE_IDX 2
#define mmDSCC1_DSCC_R_Y_SQUARED_ERROR_LOWER 0x3082
#define mmDSCC1_DSCC_R_Y_SQUARED_ERROR_LOWER_BASE_IDX 2
#define mmDSCC1_DSCC_R_Y_SQUARED_ERROR_UPPER 0x3083
#define mmDSCC1_DSCC_R_Y_SQUARED_ERROR_UPPER_BASE_IDX 2
#define mmDSCC1_DSCC_G_CB_SQUARED_ERROR_LOWER 0x3084
#define mmDSCC1_DSCC_G_CB_SQUARED_ERROR_LOWER_BASE_IDX 2
#define mmDSCC1_DSCC_G_CB_SQUARED_ERROR_UPPER 0x3085
#define mmDSCC1_DSCC_G_CB_SQUARED_ERROR_UPPER_BASE_IDX 2
#define mmDSCC1_DSCC_B_CR_SQUARED_ERROR_LOWER 0x3086
#define mmDSCC1_DSCC_B_CR_SQUARED_ERROR_LOWER_BASE_IDX 2
#define mmDSCC1_DSCC_B_CR_SQUARED_ERROR_UPPER 0x3087
#define mmDSCC1_DSCC_B_CR_SQUARED_ERROR_UPPER_BASE_IDX 2
#define mmDSCC1_DSCC_MAX_ABS_ERROR0 0x3088
#define mmDSCC1_DSCC_MAX_ABS_ERROR0_BASE_IDX 2
#define mmDSCC1_DSCC_MAX_ABS_ERROR1 0x3089
#define mmDSCC1_DSCC_MAX_ABS_ERROR1_BASE_IDX 2
#define mmDSCC1_DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL 0x308a
#define mmDSCC1_DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL_BASE_IDX 2
#define mmDSCC1_DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL 0x308b
#define mmDSCC1_DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL_BASE_IDX 2
#define mmDSCC1_DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL 0x308c
#define mmDSCC1_DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL_BASE_IDX 2
#define mmDSCC1_DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL 0x308d
#define mmDSCC1_DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL_BASE_IDX 2
#define mmDSCC1_DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL 0x308e
#define mmDSCC1_DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL_BASE_IDX 2
#define mmDSCC1_DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL 0x308f
#define mmDSCC1_DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL_BASE_IDX 2
#define mmDSCC1_DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL 0x3090
#define mmDSCC1_DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL_BASE_IDX 2
#define mmDSCC1_DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL 0x3091
#define mmDSCC1_DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL_BASE_IDX 2
// addressBlock: dce_dc_dsc1_dispdec_dsc_dcperfmon_dc_perfmon_dispdec
// base address: 0xc2b0
#define mmDC_PERFMON20_PERFCOUNTER_CNTL 0x30ac
#define mmDC_PERFMON20_PERFCOUNTER_CNTL_BASE_IDX 2
#define mmDC_PERFMON20_PERFCOUNTER_CNTL2 0x30ad
#define mmDC_PERFMON20_PERFCOUNTER_CNTL2_BASE_IDX 2
#define mmDC_PERFMON20_PERFCOUNTER_STATE 0x30ae
#define mmDC_PERFMON20_PERFCOUNTER_STATE_BASE_IDX 2
#define mmDC_PERFMON20_PERFMON_CNTL 0x30af
#define mmDC_PERFMON20_PERFMON_CNTL_BASE_IDX 2
#define mmDC_PERFMON20_PERFMON_CNTL2 0x30b0
#define mmDC_PERFMON20_PERFMON_CNTL2_BASE_IDX 2
#define mmDC_PERFMON20_PERFMON_CVALUE_INT_MISC 0x30b1
#define mmDC_PERFMON20_PERFMON_CVALUE_INT_MISC_BASE_IDX 2
#define mmDC_PERFMON20_PERFMON_CVALUE_LOW 0x30b2
#define mmDC_PERFMON20_PERFMON_CVALUE_LOW_BASE_IDX 2
#define mmDC_PERFMON20_PERFMON_HI 0x30b3
#define mmDC_PERFMON20_PERFMON_HI_BASE_IDX 2
#define mmDC_PERFMON20_PERFMON_LOW 0x30b4
#define mmDC_PERFMON20_PERFMON_LOW_BASE_IDX 2
// addressBlock: dce_dc_dsc2_dispdec_dsc_top_dispdec
// base address: 0x2e0
#define mmDSC_TOP2_DSC_TOP_CONTROL 0x30b8
#define mmDSC_TOP2_DSC_TOP_CONTROL_BASE_IDX 2
#define mmDSC_TOP2_DSC_DEBUG_CONTROL 0x30b9
#define mmDSC_TOP2_DSC_DEBUG_CONTROL_BASE_IDX 2
// addressBlock: dce_dc_dsc2_dispdec_dsccif_dispdec
// base address: 0x2e0
#define mmDSCCIF2_DSCCIF_CONFIG0 0x30bd
#define mmDSCCIF2_DSCCIF_CONFIG0_BASE_IDX 2
#define mmDSCCIF2_DSCCIF_CONFIG1 0x30be
#define mmDSCCIF2_DSCCIF_CONFIG1_BASE_IDX 2
// addressBlock: dce_dc_dsc2_dispdec_dscc_dispdec
// base address: 0x2e0
#define mmDSCC2_DSCC_CONFIG0 0x30c2
#define mmDSCC2_DSCC_CONFIG0_BASE_IDX 2
#define mmDSCC2_DSCC_CONFIG1 0x30c3
#define mmDSCC2_DSCC_CONFIG1_BASE_IDX 2
#define mmDSCC2_DSCC_STATUS 0x30c4
#define mmDSCC2_DSCC_STATUS_BASE_IDX 2
#define mmDSCC2_DSCC_INTERRUPT_CONTROL_STATUS 0x30c5
#define mmDSCC2_DSCC_INTERRUPT_CONTROL_STATUS_BASE_IDX 2
#define mmDSCC2_DSCC_PPS_CONFIG0 0x30c6
#define mmDSCC2_DSCC_PPS_CONFIG0_BASE_IDX 2
#define mmDSCC2_DSCC_PPS_CONFIG1 0x30c7
#define mmDSCC2_DSCC_PPS_CONFIG1_BASE_IDX 2
#define mmDSCC2_DSCC_PPS_CONFIG2 0x30c8
#define mmDSCC2_DSCC_PPS_CONFIG2_BASE_IDX 2
#define mmDSCC2_DSCC_PPS_CONFIG3 0x30c9
#define mmDSCC2_DSCC_PPS_CONFIG3_BASE_IDX 2
#define mmDSCC2_DSCC_PPS_CONFIG4 0x30ca
#define mmDSCC2_DSCC_PPS_CONFIG4_BASE_IDX 2
#define mmDSCC2_DSCC_PPS_CONFIG5 0x30cb
#define mmDSCC2_DSCC_PPS_CONFIG5_BASE_IDX 2
#define mmDSCC2_DSCC_PPS_CONFIG6 0x30cc
#define mmDSCC2_DSCC_PPS_CONFIG6_BASE_IDX 2
#define mmDSCC2_DSCC_PPS_CONFIG7 0x30cd
#define mmDSCC2_DSCC_PPS_CONFIG7_BASE_IDX 2
#define mmDSCC2_DSCC_PPS_CONFIG8 0x30ce
#define mmDSCC2_DSCC_PPS_CONFIG8_BASE_IDX 2
#define mmDSCC2_DSCC_PPS_CONFIG9 0x30cf
#define mmDSCC2_DSCC_PPS_CONFIG9_BASE_IDX 2
#define mmDSCC2_DSCC_PPS_CONFIG10 0x30d0
#define mmDSCC2_DSCC_PPS_CONFIG10_BASE_IDX 2
#define mmDSCC2_DSCC_PPS_CONFIG11 0x30d1
#define mmDSCC2_DSCC_PPS_CONFIG11_BASE_IDX 2
#define mmDSCC2_DSCC_PPS_CONFIG12 0x30d2
#define mmDSCC2_DSCC_PPS_CONFIG12_BASE_IDX 2
#define mmDSCC2_DSCC_PPS_CONFIG13 0x30d3
#define mmDSCC2_DSCC_PPS_CONFIG13_BASE_IDX 2
#define mmDSCC2_DSCC_PPS_CONFIG14 0x30d4
#define mmDSCC2_DSCC_PPS_CONFIG14_BASE_IDX 2
#define mmDSCC2_DSCC_PPS_CONFIG15 0x30d5
#define mmDSCC2_DSCC_PPS_CONFIG15_BASE_IDX 2
#define mmDSCC2_DSCC_PPS_CONFIG16 0x30d6
#define mmDSCC2_DSCC_PPS_CONFIG16_BASE_IDX 2
#define mmDSCC2_DSCC_PPS_CONFIG17 0x30d7
#define mmDSCC2_DSCC_PPS_CONFIG17_BASE_IDX 2
#define mmDSCC2_DSCC_PPS_CONFIG18 0x30d8
#define mmDSCC2_DSCC_PPS_CONFIG18_BASE_IDX 2
#define mmDSCC2_DSCC_PPS_CONFIG19 0x30d9
#define mmDSCC2_DSCC_PPS_CONFIG19_BASE_IDX 2
#define mmDSCC2_DSCC_PPS_CONFIG20 0x30da
#define mmDSCC2_DSCC_PPS_CONFIG20_BASE_IDX 2
#define mmDSCC2_DSCC_PPS_CONFIG21 0x30db
#define mmDSCC2_DSCC_PPS_CONFIG21_BASE_IDX 2
#define mmDSCC2_DSCC_PPS_CONFIG22 0x30dc
#define mmDSCC2_DSCC_PPS_CONFIG22_BASE_IDX 2
#define mmDSCC2_DSCC_MEM_POWER_CONTROL 0x30dd
#define mmDSCC2_DSCC_MEM_POWER_CONTROL_BASE_IDX 2
#define mmDSCC2_DSCC_R_Y_SQUARED_ERROR_LOWER 0x30de
#define mmDSCC2_DSCC_R_Y_SQUARED_ERROR_LOWER_BASE_IDX 2
#define mmDSCC2_DSCC_R_Y_SQUARED_ERROR_UPPER 0x30df
#define mmDSCC2_DSCC_R_Y_SQUARED_ERROR_UPPER_BASE_IDX 2
#define mmDSCC2_DSCC_G_CB_SQUARED_ERROR_LOWER 0x30e0
#define mmDSCC2_DSCC_G_CB_SQUARED_ERROR_LOWER_BASE_IDX 2
#define mmDSCC2_DSCC_G_CB_SQUARED_ERROR_UPPER 0x30e1
#define mmDSCC2_DSCC_G_CB_SQUARED_ERROR_UPPER_BASE_IDX 2
#define mmDSCC2_DSCC_B_CR_SQUARED_ERROR_LOWER 0x30e2
#define mmDSCC2_DSCC_B_CR_SQUARED_ERROR_LOWER_BASE_IDX 2
#define mmDSCC2_DSCC_B_CR_SQUARED_ERROR_UPPER 0x30e3
#define mmDSCC2_DSCC_B_CR_SQUARED_ERROR_UPPER_BASE_IDX 2
#define mmDSCC2_DSCC_MAX_ABS_ERROR0 0x30e4
#define mmDSCC2_DSCC_MAX_ABS_ERROR0_BASE_IDX 2
#define mmDSCC2_DSCC_MAX_ABS_ERROR1 0x30e5
#define mmDSCC2_DSCC_MAX_ABS_ERROR1_BASE_IDX 2
#define mmDSCC2_DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL 0x30e6
#define mmDSCC2_DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL_BASE_IDX 2
#define mmDSCC2_DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL 0x30e7
#define mmDSCC2_DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL_BASE_IDX 2
#define mmDSCC2_DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL 0x30e8
#define mmDSCC2_DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL_BASE_IDX 2
#define mmDSCC2_DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL 0x30e9
#define mmDSCC2_DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL_BASE_IDX 2
#define mmDSCC2_DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL 0x30ea
#define mmDSCC2_DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL_BASE_IDX 2
#define mmDSCC2_DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL 0x30eb
#define mmDSCC2_DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL_BASE_IDX 2
#define mmDSCC2_DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL 0x30ec
#define mmDSCC2_DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL_BASE_IDX 2
#define mmDSCC2_DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL 0x30ed
#define mmDSCC2_DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL_BASE_IDX 2
// addressBlock: dce_dc_dsc2_dispdec_dsc_dcperfmon_dc_perfmon_dispdec
// base address: 0xc420
#define mmDC_PERFMON21_PERFCOUNTER_CNTL 0x3108
#define mmDC_PERFMON21_PERFCOUNTER_CNTL_BASE_IDX 2
#define mmDC_PERFMON21_PERFCOUNTER_CNTL2 0x3109
#define mmDC_PERFMON21_PERFCOUNTER_CNTL2_BASE_IDX 2
#define mmDC_PERFMON21_PERFCOUNTER_STATE 0x310a
#define mmDC_PERFMON21_PERFCOUNTER_STATE_BASE_IDX 2
#define mmDC_PERFMON21_PERFMON_CNTL 0x310b
#define mmDC_PERFMON21_PERFMON_CNTL_BASE_IDX 2
#define mmDC_PERFMON21_PERFMON_CNTL2 0x310c
#define mmDC_PERFMON21_PERFMON_CNTL2_BASE_IDX 2
#define mmDC_PERFMON21_PERFMON_CVALUE_INT_MISC 0x310d
#define mmDC_PERFMON21_PERFMON_CVALUE_INT_MISC_BASE_IDX 2
#define mmDC_PERFMON21_PERFMON_CVALUE_LOW 0x310e
#define mmDC_PERFMON21_PERFMON_CVALUE_LOW_BASE_IDX 2
#define mmDC_PERFMON21_PERFMON_HI 0x310f
#define mmDC_PERFMON21_PERFMON_HI_BASE_IDX 2
#define mmDC_PERFMON21_PERFMON_LOW 0x3110
#define mmDC_PERFMON21_PERFMON_LOW_BASE_IDX 2
// addressBlock: dce_dc_dsc3_dispdec_dsc_top_dispdec
// base address: 0x450
#define mmDSC_TOP3_DSC_TOP_CONTROL 0x3114
#define mmDSC_TOP3_DSC_TOP_CONTROL_BASE_IDX 2
#define mmDSC_TOP3_DSC_DEBUG_CONTROL 0x3115
#define mmDSC_TOP3_DSC_DEBUG_CONTROL_BASE_IDX 2
// addressBlock: dce_dc_dsc3_dispdec_dsccif_dispdec
// base address: 0x450
#define mmDSCCIF3_DSCCIF_CONFIG0 0x3119
#define mmDSCCIF3_DSCCIF_CONFIG0_BASE_IDX 2
#define mmDSCCIF3_DSCCIF_CONFIG1 0x311a
#define mmDSCCIF3_DSCCIF_CONFIG1_BASE_IDX 2
// addressBlock: dce_dc_dsc3_dispdec_dscc_dispdec
// base address: 0x450
#define mmDSCC3_DSCC_CONFIG0 0x311e
#define mmDSCC3_DSCC_CONFIG0_BASE_IDX 2
#define mmDSCC3_DSCC_CONFIG1 0x311f
#define mmDSCC3_DSCC_CONFIG1_BASE_IDX 2
#define mmDSCC3_DSCC_STATUS 0x3120
#define mmDSCC3_DSCC_STATUS_BASE_IDX 2
#define mmDSCC3_DSCC_INTERRUPT_CONTROL_STATUS 0x3121
#define mmDSCC3_DSCC_INTERRUPT_CONTROL_STATUS_BASE_IDX 2
#define mmDSCC3_DSCC_PPS_CONFIG0 0x3122
#define mmDSCC3_DSCC_PPS_CONFIG0_BASE_IDX 2
#define mmDSCC3_DSCC_PPS_CONFIG1 0x3123
#define mmDSCC3_DSCC_PPS_CONFIG1_BASE_IDX 2
#define mmDSCC3_DSCC_PPS_CONFIG2 0x3124
#define mmDSCC3_DSCC_PPS_CONFIG2_BASE_IDX 2
#define mmDSCC3_DSCC_PPS_CONFIG3 0x3125
#define mmDSCC3_DSCC_PPS_CONFIG3_BASE_IDX 2
#define mmDSCC3_DSCC_PPS_CONFIG4 0x3126
#define mmDSCC3_DSCC_PPS_CONFIG4_BASE_IDX 2
#define mmDSCC3_DSCC_PPS_CONFIG5 0x3127
#define mmDSCC3_DSCC_PPS_CONFIG5_BASE_IDX 2
#define mmDSCC3_DSCC_PPS_CONFIG6 0x3128
#define mmDSCC3_DSCC_PPS_CONFIG6_BASE_IDX 2
#define mmDSCC3_DSCC_PPS_CONFIG7 0x3129
#define mmDSCC3_DSCC_PPS_CONFIG7_BASE_IDX 2
#define mmDSCC3_DSCC_PPS_CONFIG8 0x312a
#define mmDSCC3_DSCC_PPS_CONFIG8_BASE_IDX 2
#define mmDSCC3_DSCC_PPS_CONFIG9 0x312b
#define mmDSCC3_DSCC_PPS_CONFIG9_BASE_IDX 2
#define mmDSCC3_DSCC_PPS_CONFIG10 0x312c
#define mmDSCC3_DSCC_PPS_CONFIG10_BASE_IDX 2
#define mmDSCC3_DSCC_PPS_CONFIG11 0x312d
#define mmDSCC3_DSCC_PPS_CONFIG11_BASE_IDX 2
#define mmDSCC3_DSCC_PPS_CONFIG12 0x312e
#define mmDSCC3_DSCC_PPS_CONFIG12_BASE_IDX 2
#define mmDSCC3_DSCC_PPS_CONFIG13 0x312f
#define mmDSCC3_DSCC_PPS_CONFIG13_BASE_IDX 2
#define mmDSCC3_DSCC_PPS_CONFIG14 0x3130
#define mmDSCC3_DSCC_PPS_CONFIG14_BASE_IDX 2
#define mmDSCC3_DSCC_PPS_CONFIG15 0x3131
#define mmDSCC3_DSCC_PPS_CONFIG15_BASE_IDX 2
#define mmDSCC3_DSCC_PPS_CONFIG16 0x3132
#define mmDSCC3_DSCC_PPS_CONFIG16_BASE_IDX 2
#define mmDSCC3_DSCC_PPS_CONFIG17 0x3133
#define mmDSCC3_DSCC_PPS_CONFIG17_BASE_IDX 2
#define mmDSCC3_DSCC_PPS_CONFIG18 0x3134
#define mmDSCC3_DSCC_PPS_CONFIG18_BASE_IDX 2
#define mmDSCC3_DSCC_PPS_CONFIG19 0x3135
#define mmDSCC3_DSCC_PPS_CONFIG19_BASE_IDX 2
#define mmDSCC3_DSCC_PPS_CONFIG20 0x3136
#define mmDSCC3_DSCC_PPS_CONFIG20_BASE_IDX 2
#define mmDSCC3_DSCC_PPS_CONFIG21 0x3137
#define mmDSCC3_DSCC_PPS_CONFIG21_BASE_IDX 2
#define mmDSCC3_DSCC_PPS_CONFIG22 0x3138
#define mmDSCC3_DSCC_PPS_CONFIG22_BASE_IDX 2
#define mmDSCC3_DSCC_MEM_POWER_CONTROL 0x3139
#define mmDSCC3_DSCC_MEM_POWER_CONTROL_BASE_IDX 2
#define mmDSCC3_DSCC_R_Y_SQUARED_ERROR_LOWER 0x313a
#define mmDSCC3_DSCC_R_Y_SQUARED_ERROR_LOWER_BASE_IDX 2
#define mmDSCC3_DSCC_R_Y_SQUARED_ERROR_UPPER 0x313b
#define mmDSCC3_DSCC_R_Y_SQUARED_ERROR_UPPER_BASE_IDX 2
#define mmDSCC3_DSCC_G_CB_SQUARED_ERROR_LOWER 0x313c
#define mmDSCC3_DSCC_G_CB_SQUARED_ERROR_LOWER_BASE_IDX 2
#define mmDSCC3_DSCC_G_CB_SQUARED_ERROR_UPPER 0x313d
#define mmDSCC3_DSCC_G_CB_SQUARED_ERROR_UPPER_BASE_IDX 2
#define mmDSCC3_DSCC_B_CR_SQUARED_ERROR_LOWER 0x313e
#define mmDSCC3_DSCC_B_CR_SQUARED_ERROR_LOWER_BASE_IDX 2
#define mmDSCC3_DSCC_B_CR_SQUARED_ERROR_UPPER 0x313f
#define mmDSCC3_DSCC_B_CR_SQUARED_ERROR_UPPER_BASE_IDX 2
#define mmDSCC3_DSCC_MAX_ABS_ERROR0 0x3140
#define mmDSCC3_DSCC_MAX_ABS_ERROR0_BASE_IDX 2
#define mmDSCC3_DSCC_MAX_ABS_ERROR1 0x3141
#define mmDSCC3_DSCC_MAX_ABS_ERROR1_BASE_IDX 2
#define mmDSCC3_DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL 0x3142
#define mmDSCC3_DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL_BASE_IDX 2
#define mmDSCC3_DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL 0x3143
#define mmDSCC3_DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL_BASE_IDX 2
#define mmDSCC3_DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL 0x3144
#define mmDSCC3_DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL_BASE_IDX 2
#define mmDSCC3_DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL 0x3145
#define mmDSCC3_DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL_BASE_IDX 2
#define mmDSCC3_DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL 0x3146
#define mmDSCC3_DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL_BASE_IDX 2
#define mmDSCC3_DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL 0x3147
#define mmDSCC3_DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL_BASE_IDX 2
#define mmDSCC3_DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL 0x3148
#define mmDSCC3_DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL_BASE_IDX 2
#define mmDSCC3_DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL 0x3149
#define mmDSCC3_DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL_BASE_IDX 2
// addressBlock: dce_dc_dsc3_dispdec_dsc_dcperfmon_dc_perfmon_dispdec
// base address: 0xc590
#define mmDC_PERFMON22_PERFCOUNTER_CNTL 0x3164
#define mmDC_PERFMON22_PERFCOUNTER_CNTL_BASE_IDX 2
#define mmDC_PERFMON22_PERFCOUNTER_CNTL2 0x3165
#define mmDC_PERFMON22_PERFCOUNTER_CNTL2_BASE_IDX 2
#define mmDC_PERFMON22_PERFCOUNTER_STATE 0x3166
#define mmDC_PERFMON22_PERFCOUNTER_STATE_BASE_IDX 2
#define mmDC_PERFMON22_PERFMON_CNTL 0x3167
#define mmDC_PERFMON22_PERFMON_CNTL_BASE_IDX 2
#define mmDC_PERFMON22_PERFMON_CNTL2 0x3168
#define mmDC_PERFMON22_PERFMON_CNTL2_BASE_IDX 2
#define mmDC_PERFMON22_PERFMON_CVALUE_INT_MISC 0x3169
#define mmDC_PERFMON22_PERFMON_CVALUE_INT_MISC_BASE_IDX 2
#define mmDC_PERFMON22_PERFMON_CVALUE_LOW 0x316a
#define mmDC_PERFMON22_PERFMON_CVALUE_LOW_BASE_IDX 2
#define mmDC_PERFMON22_PERFMON_HI 0x316b
#define mmDC_PERFMON22_PERFMON_HI_BASE_IDX 2
#define mmDC_PERFMON22_PERFMON_LOW 0x316c
#define mmDC_PERFMON22_PERFMON_LOW_BASE_IDX 2
// addressBlock: dce_dc_dsc4_dispdec_dsc_top_dispdec
// base address: 0x5c0
#define mmDSC_TOP4_DSC_TOP_CONTROL 0x3170
#define mmDSC_TOP4_DSC_TOP_CONTROL_BASE_IDX 2
#define mmDSC_TOP4_DSC_DEBUG_CONTROL 0x3171
#define mmDSC_TOP4_DSC_DEBUG_CONTROL_BASE_IDX 2
// addressBlock: dce_dc_dsc4_dispdec_dsccif_dispdec
// base address: 0x5c0
#define mmDSCCIF4_DSCCIF_CONFIG0 0x3175
#define mmDSCCIF4_DSCCIF_CONFIG0_BASE_IDX 2
#define mmDSCCIF4_DSCCIF_CONFIG1 0x3176
#define mmDSCCIF4_DSCCIF_CONFIG1_BASE_IDX 2
// addressBlock: dce_dc_dsc4_dispdec_dscc_dispdec
// base address: 0x5c0
#define mmDSCC4_DSCC_CONFIG0 0x317a
#define mmDSCC4_DSCC_CONFIG0_BASE_IDX 2
#define mmDSCC4_DSCC_CONFIG1 0x317b
#define mmDSCC4_DSCC_CONFIG1_BASE_IDX 2
#define mmDSCC4_DSCC_STATUS 0x317c
#define mmDSCC4_DSCC_STATUS_BASE_IDX 2
#define mmDSCC4_DSCC_INTERRUPT_CONTROL_STATUS 0x317d
#define mmDSCC4_DSCC_INTERRUPT_CONTROL_STATUS_BASE_IDX 2
#define mmDSCC4_DSCC_PPS_CONFIG0 0x317e
#define mmDSCC4_DSCC_PPS_CONFIG0_BASE_IDX 2
#define mmDSCC4_DSCC_PPS_CONFIG1 0x317f
#define mmDSCC4_DSCC_PPS_CONFIG1_BASE_IDX 2
#define mmDSCC4_DSCC_PPS_CONFIG2 0x3180
#define mmDSCC4_DSCC_PPS_CONFIG2_BASE_IDX 2
#define mmDSCC4_DSCC_PPS_CONFIG3 0x3181
#define mmDSCC4_DSCC_PPS_CONFIG3_BASE_IDX 2
#define mmDSCC4_DSCC_PPS_CONFIG4 0x3182
#define mmDSCC4_DSCC_PPS_CONFIG4_BASE_IDX 2
#define mmDSCC4_DSCC_PPS_CONFIG5 0x3183
#define mmDSCC4_DSCC_PPS_CONFIG5_BASE_IDX 2
#define mmDSCC4_DSCC_PPS_CONFIG6 0x3184
#define mmDSCC4_DSCC_PPS_CONFIG6_BASE_IDX 2
#define mmDSCC4_DSCC_PPS_CONFIG7 0x3185
#define mmDSCC4_DSCC_PPS_CONFIG7_BASE_IDX 2
#define mmDSCC4_DSCC_PPS_CONFIG8 0x3186
#define mmDSCC4_DSCC_PPS_CONFIG8_BASE_IDX 2
#define mmDSCC4_DSCC_PPS_CONFIG9 0x3187
#define mmDSCC4_DSCC_PPS_CONFIG9_BASE_IDX 2
#define mmDSCC4_DSCC_PPS_CONFIG10 0x3188
#define mmDSCC4_DSCC_PPS_CONFIG10_BASE_IDX 2
#define mmDSCC4_DSCC_PPS_CONFIG11 0x3189
#define mmDSCC4_DSCC_PPS_CONFIG11_BASE_IDX 2
#define mmDSCC4_DSCC_PPS_CONFIG12 0x318a
#define mmDSCC4_DSCC_PPS_CONFIG12_BASE_IDX 2
#define mmDSCC4_DSCC_PPS_CONFIG13 0x318b
#define mmDSCC4_DSCC_PPS_CONFIG13_BASE_IDX 2
#define mmDSCC4_DSCC_PPS_CONFIG14 0x318c
#define mmDSCC4_DSCC_PPS_CONFIG14_BASE_IDX 2
#define mmDSCC4_DSCC_PPS_CONFIG15 0x318d
#define mmDSCC4_DSCC_PPS_CONFIG15_BASE_IDX 2
#define mmDSCC4_DSCC_PPS_CONFIG16 0x318e
#define mmDSCC4_DSCC_PPS_CONFIG16_BASE_IDX 2
#define mmDSCC4_DSCC_PPS_CONFIG17 0x318f
#define mmDSCC4_DSCC_PPS_CONFIG17_BASE_IDX 2
#define mmDSCC4_DSCC_PPS_CONFIG18 0x3190
#define mmDSCC4_DSCC_PPS_CONFIG18_BASE_IDX 2
#define mmDSCC4_DSCC_PPS_CONFIG19 0x3191
#define mmDSCC4_DSCC_PPS_CONFIG19_BASE_IDX 2
#define mmDSCC4_DSCC_PPS_CONFIG20 0x3192
#define mmDSCC4_DSCC_PPS_CONFIG20_BASE_IDX 2
#define mmDSCC4_DSCC_PPS_CONFIG21 0x3193
#define mmDSCC4_DSCC_PPS_CONFIG21_BASE_IDX 2
#define mmDSCC4_DSCC_PPS_CONFIG22 0x3194
#define mmDSCC4_DSCC_PPS_CONFIG22_BASE_IDX 2
#define mmDSCC4_DSCC_MEM_POWER_CONTROL 0x3195
#define mmDSCC4_DSCC_MEM_POWER_CONTROL_BASE_IDX 2
#define mmDSCC4_DSCC_R_Y_SQUARED_ERROR_LOWER 0x3196
#define mmDSCC4_DSCC_R_Y_SQUARED_ERROR_LOWER_BASE_IDX 2
#define mmDSCC4_DSCC_R_Y_SQUARED_ERROR_UPPER 0x3197
#define mmDSCC4_DSCC_R_Y_SQUARED_ERROR_UPPER_BASE_IDX 2
#define mmDSCC4_DSCC_G_CB_SQUARED_ERROR_LOWER 0x3198
#define mmDSCC4_DSCC_G_CB_SQUARED_ERROR_LOWER_BASE_IDX 2
#define mmDSCC4_DSCC_G_CB_SQUARED_ERROR_UPPER 0x3199
#define mmDSCC4_DSCC_G_CB_SQUARED_ERROR_UPPER_BASE_IDX 2
#define mmDSCC4_DSCC_B_CR_SQUARED_ERROR_LOWER 0x319a
#define mmDSCC4_DSCC_B_CR_SQUARED_ERROR_LOWER_BASE_IDX 2
#define mmDSCC4_DSCC_B_CR_SQUARED_ERROR_UPPER 0x319b
#define mmDSCC4_DSCC_B_CR_SQUARED_ERROR_UPPER_BASE_IDX 2
#define mmDSCC4_DSCC_MAX_ABS_ERROR0 0x319c
#define mmDSCC4_DSCC_MAX_ABS_ERROR0_BASE_IDX 2
#define mmDSCC4_DSCC_MAX_ABS_ERROR1 0x319d
#define mmDSCC4_DSCC_MAX_ABS_ERROR1_BASE_IDX 2
#define mmDSCC4_DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL 0x319e
#define mmDSCC4_DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL_BASE_IDX 2
#define mmDSCC4_DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL 0x319f
#define mmDSCC4_DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL_BASE_IDX 2
#define mmDSCC4_DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL 0x31a0
#define mmDSCC4_DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL_BASE_IDX 2
#define mmDSCC4_DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL 0x31a1
#define mmDSCC4_DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL_BASE_IDX 2
#define mmDSCC4_DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL 0x31a2
#define mmDSCC4_DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL_BASE_IDX 2
#define mmDSCC4_DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL 0x31a3
#define mmDSCC4_DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL_BASE_IDX 2
#define mmDSCC4_DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL 0x31a4
#define mmDSCC4_DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL_BASE_IDX 2
#define mmDSCC4_DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL 0x31a5
#define mmDSCC4_DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL_BASE_IDX 2
// addressBlock: dce_dc_dsc4_dispdec_dsc_dcperfmon_dc_perfmon_dispdec
// base address: 0xc700
#define mmDC_PERFMON23_PERFCOUNTER_CNTL 0x31c0
#define mmDC_PERFMON23_PERFCOUNTER_CNTL_BASE_IDX 2
#define mmDC_PERFMON23_PERFCOUNTER_CNTL2 0x31c1
#define mmDC_PERFMON23_PERFCOUNTER_CNTL2_BASE_IDX 2
#define mmDC_PERFMON23_PERFCOUNTER_STATE 0x31c2
#define mmDC_PERFMON23_PERFCOUNTER_STATE_BASE_IDX 2
#define mmDC_PERFMON23_PERFMON_CNTL 0x31c3
#define mmDC_PERFMON23_PERFMON_CNTL_BASE_IDX 2
#define mmDC_PERFMON23_PERFMON_CNTL2 0x31c4
#define mmDC_PERFMON23_PERFMON_CNTL2_BASE_IDX 2
#define mmDC_PERFMON23_PERFMON_CVALUE_INT_MISC 0x31c5
#define mmDC_PERFMON23_PERFMON_CVALUE_INT_MISC_BASE_IDX 2
#define mmDC_PERFMON23_PERFMON_CVALUE_LOW 0x31c6
#define mmDC_PERFMON23_PERFMON_CVALUE_LOW_BASE_IDX 2
#define mmDC_PERFMON23_PERFMON_HI 0x31c7
#define mmDC_PERFMON23_PERFMON_HI_BASE_IDX 2
#define mmDC_PERFMON23_PERFMON_LOW 0x31c8
#define mmDC_PERFMON23_PERFMON_LOW_BASE_IDX 2
// addressBlock: dce_dc_wb0_dispdec_dwb_top_dispdec
// base address: 0x0
#define mmDWB_ENABLE_CLK_CTRL 0x3228
#define mmDWB_ENABLE_CLK_CTRL_BASE_IDX 2
#define mmDWB_MEM_PWR_CTRL 0x3229
#define mmDWB_MEM_PWR_CTRL_BASE_IDX 2
#define mmFC_MODE_CTRL 0x322a
#define mmFC_MODE_CTRL_BASE_IDX 2
#define mmFC_FLOW_CTRL 0x322b
#define mmFC_FLOW_CTRL_BASE_IDX 2
#define mmFC_WINDOW_START 0x322c
#define mmFC_WINDOW_START_BASE_IDX 2
#define mmFC_WINDOW_SIZE 0x322d
#define mmFC_WINDOW_SIZE_BASE_IDX 2
#define mmFC_SOURCE_SIZE 0x322e
#define mmFC_SOURCE_SIZE_BASE_IDX 2
#define mmDWB_UPDATE_CTRL 0x322f
#define mmDWB_UPDATE_CTRL_BASE_IDX 2
#define mmDWB_CRC_CTRL 0x3230
#define mmDWB_CRC_CTRL_BASE_IDX 2
#define mmDWB_CRC_MASK_R_G 0x3231
#define mmDWB_CRC_MASK_R_G_BASE_IDX 2
#define mmDWB_CRC_MASK_B_A 0x3232
#define mmDWB_CRC_MASK_B_A_BASE_IDX 2
#define mmDWB_CRC_VAL_R_G 0x3233
#define mmDWB_CRC_VAL_R_G_BASE_IDX 2
#define mmDWB_CRC_VAL_B_A 0x3234
#define mmDWB_CRC_VAL_B_A_BASE_IDX 2
#define mmDWB_OUT_CTRL 0x3235
#define mmDWB_OUT_CTRL_BASE_IDX 2
#define mmDWB_MMHUBBUB_BACKPRESSURE_CNT_EN 0x3236
#define mmDWB_MMHUBBUB_BACKPRESSURE_CNT_EN_BASE_IDX 2
#define mmDWB_MMHUBBUB_BACKPRESSURE_CNT 0x3237
#define mmDWB_MMHUBBUB_BACKPRESSURE_CNT_BASE_IDX 2
#define mmDWB_HOST_READ_CONTROL 0x3238
#define mmDWB_HOST_READ_CONTROL_BASE_IDX 2
#define mmDWB_OVERFLOW_STATUS 0x3239
#define mmDWB_OVERFLOW_STATUS_BASE_IDX 2
#define mmDWB_OVERFLOW_COUNTER 0x323a
#define mmDWB_OVERFLOW_COUNTER_BASE_IDX 2
#define mmDWB_SOFT_RESET 0x323b
#define mmDWB_SOFT_RESET_BASE_IDX 2
// addressBlock: dce_dc_wb0_dispdec_wb_dcperfmon_dc_perfmon_dispdec
// base address: 0xca20
#define mmDC_PERFMON24_PERFCOUNTER_CNTL 0x3288
#define mmDC_PERFMON24_PERFCOUNTER_CNTL_BASE_IDX 2
#define mmDC_PERFMON24_PERFCOUNTER_CNTL2 0x3289
#define mmDC_PERFMON24_PERFCOUNTER_CNTL2_BASE_IDX 2
#define mmDC_PERFMON24_PERFCOUNTER_STATE 0x328a
#define mmDC_PERFMON24_PERFCOUNTER_STATE_BASE_IDX 2
#define mmDC_PERFMON24_PERFMON_CNTL 0x328b
#define mmDC_PERFMON24_PERFMON_CNTL_BASE_IDX 2
#define mmDC_PERFMON24_PERFMON_CNTL2 0x328c
#define mmDC_PERFMON24_PERFMON_CNTL2_BASE_IDX 2
#define mmDC_PERFMON24_PERFMON_CVALUE_INT_MISC 0x328d
#define mmDC_PERFMON24_PERFMON_CVALUE_INT_MISC_BASE_IDX 2
#define mmDC_PERFMON24_PERFMON_CVALUE_LOW 0x328e
#define mmDC_PERFMON24_PERFMON_CVALUE_LOW_BASE_IDX 2
#define mmDC_PERFMON24_PERFMON_HI 0x328f
#define mmDC_PERFMON24_PERFMON_HI_BASE_IDX 2
#define mmDC_PERFMON24_PERFMON_LOW 0x3290
#define mmDC_PERFMON24_PERFMON_LOW_BASE_IDX 2
// addressBlock: dce_dc_wb0_dispdec_dwbcp_dispdec
// base address: 0x0
#define mmDWB_HDR_MULT_COEF 0x3294
#define mmDWB_HDR_MULT_COEF_BASE_IDX 2
#define mmDWB_GAMUT_REMAP_MODE 0x3295
#define mmDWB_GAMUT_REMAP_MODE_BASE_IDX 2
#define mmDWB_GAMUT_REMAP_COEF_FORMAT 0x3296
#define mmDWB_GAMUT_REMAP_COEF_FORMAT_BASE_IDX 2
#define mmDWB_GAMUT_REMAPA_C11_C12 0x3297
#define mmDWB_GAMUT_REMAPA_C11_C12_BASE_IDX 2
#define mmDWB_GAMUT_REMAPA_C13_C14 0x3298
#define mmDWB_GAMUT_REMAPA_C13_C14_BASE_IDX 2
#define mmDWB_GAMUT_REMAPA_C21_C22 0x3299
#define mmDWB_GAMUT_REMAPA_C21_C22_BASE_IDX 2
#define mmDWB_GAMUT_REMAPA_C23_C24 0x329a
#define mmDWB_GAMUT_REMAPA_C23_C24_BASE_IDX 2
#define mmDWB_GAMUT_REMAPA_C31_C32 0x329b
#define mmDWB_GAMUT_REMAPA_C31_C32_BASE_IDX 2
#define mmDWB_GAMUT_REMAPA_C33_C34 0x329c
#define mmDWB_GAMUT_REMAPA_C33_C34_BASE_IDX 2
#define mmDWB_GAMUT_REMAPB_C11_C12 0x329d
#define mmDWB_GAMUT_REMAPB_C11_C12_BASE_IDX 2
#define mmDWB_GAMUT_REMAPB_C13_C14 0x329e
#define mmDWB_GAMUT_REMAPB_C13_C14_BASE_IDX 2
#define mmDWB_GAMUT_REMAPB_C21_C22 0x329f
#define mmDWB_GAMUT_REMAPB_C21_C22_BASE_IDX 2
#define mmDWB_GAMUT_REMAPB_C23_C24 0x32a0
#define mmDWB_GAMUT_REMAPB_C23_C24_BASE_IDX 2
#define mmDWB_GAMUT_REMAPB_C31_C32 0x32a1
#define mmDWB_GAMUT_REMAPB_C31_C32_BASE_IDX 2
#define mmDWB_GAMUT_REMAPB_C33_C34 0x32a2
#define mmDWB_GAMUT_REMAPB_C33_C34_BASE_IDX 2
#define mmDWB_OGAM_CONTROL 0x32a3
#define mmDWB_OGAM_CONTROL_BASE_IDX 2
#define mmDWB_OGAM_LUT_INDEX 0x32a4
#define mmDWB_OGAM_LUT_INDEX_BASE_IDX 2
#define mmDWB_OGAM_LUT_DATA 0x32a5
#define mmDWB_OGAM_LUT_DATA_BASE_IDX 2
#define mmDWB_OGAM_LUT_CONTROL 0x32a6
#define mmDWB_OGAM_LUT_CONTROL_BASE_IDX 2
#define mmDWB_OGAM_RAMA_START_CNTL_B 0x32a7
#define mmDWB_OGAM_RAMA_START_CNTL_B_BASE_IDX 2
#define mmDWB_OGAM_RAMA_START_CNTL_G 0x32a8
#define mmDWB_OGAM_RAMA_START_CNTL_G_BASE_IDX 2
#define mmDWB_OGAM_RAMA_START_CNTL_R 0x32a9
#define mmDWB_OGAM_RAMA_START_CNTL_R_BASE_IDX 2
#define mmDWB_OGAM_RAMA_START_BASE_CNTL_B 0x32aa
#define mmDWB_OGAM_RAMA_START_BASE_CNTL_B_BASE_IDX 2
#define mmDWB_OGAM_RAMA_START_SLOPE_CNTL_B 0x32ab
#define mmDWB_OGAM_RAMA_START_SLOPE_CNTL_B_BASE_IDX 2
#define mmDWB_OGAM_RAMA_START_BASE_CNTL_G 0x32ac
#define mmDWB_OGAM_RAMA_START_BASE_CNTL_G_BASE_IDX 2
#define mmDWB_OGAM_RAMA_START_SLOPE_CNTL_G 0x32ad
#define mmDWB_OGAM_RAMA_START_SLOPE_CNTL_G_BASE_IDX 2
#define mmDWB_OGAM_RAMA_START_BASE_CNTL_R 0x32ae
#define mmDWB_OGAM_RAMA_START_BASE_CNTL_R_BASE_IDX 2
#define mmDWB_OGAM_RAMA_START_SLOPE_CNTL_R 0x32af
#define mmDWB_OGAM_RAMA_START_SLOPE_CNTL_R_BASE_IDX 2
#define mmDWB_OGAM_RAMA_END_CNTL1_B 0x32b0
#define mmDWB_OGAM_RAMA_END_CNTL1_B_BASE_IDX 2
#define mmDWB_OGAM_RAMA_END_CNTL2_B 0x32b1
#define mmDWB_OGAM_RAMA_END_CNTL2_B_BASE_IDX 2
#define mmDWB_OGAM_RAMA_END_CNTL1_G 0x32b2
#define mmDWB_OGAM_RAMA_END_CNTL1_G_BASE_IDX 2
#define mmDWB_OGAM_RAMA_END_CNTL2_G 0x32b3
#define mmDWB_OGAM_RAMA_END_CNTL2_G_BASE_IDX 2
#define mmDWB_OGAM_RAMA_END_CNTL1_R 0x32b4
#define mmDWB_OGAM_RAMA_END_CNTL1_R_BASE_IDX 2
#define mmDWB_OGAM_RAMA_END_CNTL2_R 0x32b5
#define mmDWB_OGAM_RAMA_END_CNTL2_R_BASE_IDX 2
#define mmDWB_OGAM_RAMA_OFFSET_B 0x32b6
#define mmDWB_OGAM_RAMA_OFFSET_B_BASE_IDX 2
#define mmDWB_OGAM_RAMA_OFFSET_G 0x32b7
#define mmDWB_OGAM_RAMA_OFFSET_G_BASE_IDX 2
#define mmDWB_OGAM_RAMA_OFFSET_R 0x32b8
#define mmDWB_OGAM_RAMA_OFFSET_R_BASE_IDX 2
#define mmDWB_OGAM_RAMA_REGION_0_1 0x32b9
#define mmDWB_OGAM_RAMA_REGION_0_1_BASE_IDX 2
#define mmDWB_OGAM_RAMA_REGION_2_3 0x32ba
#define mmDWB_OGAM_RAMA_REGION_2_3_BASE_IDX 2
#define mmDWB_OGAM_RAMA_REGION_4_5 0x32bb
#define mmDWB_OGAM_RAMA_REGION_4_5_BASE_IDX 2
#define mmDWB_OGAM_RAMA_REGION_6_7 0x32bc
#define mmDWB_OGAM_RAMA_REGION_6_7_BASE_IDX 2
#define mmDWB_OGAM_RAMA_REGION_8_9 0x32bd
#define mmDWB_OGAM_RAMA_REGION_8_9_BASE_IDX 2
#define mmDWB_OGAM_RAMA_REGION_10_11 0x32be
#define mmDWB_OGAM_RAMA_REGION_10_11_BASE_IDX 2
#define mmDWB_OGAM_RAMA_REGION_12_13 0x32bf
#define mmDWB_OGAM_RAMA_REGION_12_13_BASE_IDX 2
#define mmDWB_OGAM_RAMA_REGION_14_15 0x32c0
#define mmDWB_OGAM_RAMA_REGION_14_15_BASE_IDX 2
#define mmDWB_OGAM_RAMA_REGION_16_17 0x32c1
#define mmDWB_OGAM_RAMA_REGION_16_17_BASE_IDX 2
#define mmDWB_OGAM_RAMA_REGION_18_19 0x32c2
#define mmDWB_OGAM_RAMA_REGION_18_19_BASE_IDX 2
#define mmDWB_OGAM_RAMA_REGION_20_21 0x32c3
#define mmDWB_OGAM_RAMA_REGION_20_21_BASE_IDX 2
#define mmDWB_OGAM_RAMA_REGION_22_23 0x32c4
#define mmDWB_OGAM_RAMA_REGION_22_23_BASE_IDX 2
#define mmDWB_OGAM_RAMA_REGION_24_25 0x32c5
#define mmDWB_OGAM_RAMA_REGION_24_25_BASE_IDX 2
#define mmDWB_OGAM_RAMA_REGION_26_27 0x32c6
#define mmDWB_OGAM_RAMA_REGION_26_27_BASE_IDX 2
#define mmDWB_OGAM_RAMA_REGION_28_29 0x32c7
#define mmDWB_OGAM_RAMA_REGION_28_29_BASE_IDX 2
#define mmDWB_OGAM_RAMA_REGION_30_31 0x32c8
#define mmDWB_OGAM_RAMA_REGION_30_31_BASE_IDX 2
#define mmDWB_OGAM_RAMA_REGION_32_33 0x32c9
#define mmDWB_OGAM_RAMA_REGION_32_33_BASE_IDX 2
#define mmDWB_OGAM_RAMB_START_CNTL_B 0x32ca
#define mmDWB_OGAM_RAMB_START_CNTL_B_BASE_IDX 2
#define mmDWB_OGAM_RAMB_START_CNTL_G 0x32cb
#define mmDWB_OGAM_RAMB_START_CNTL_G_BASE_IDX 2
#define mmDWB_OGAM_RAMB_START_CNTL_R 0x32cc
#define mmDWB_OGAM_RAMB_START_CNTL_R_BASE_IDX 2
#define mmDWB_OGAM_RAMB_START_BASE_CNTL_B 0x32cd
#define mmDWB_OGAM_RAMB_START_BASE_CNTL_B_BASE_IDX 2
#define mmDWB_OGAM_RAMB_START_SLOPE_CNTL_B 0x32ce
#define mmDWB_OGAM_RAMB_START_SLOPE_CNTL_B_BASE_IDX 2
#define mmDWB_OGAM_RAMB_START_BASE_CNTL_G 0x32cf
#define mmDWB_OGAM_RAMB_START_BASE_CNTL_G_BASE_IDX 2
#define mmDWB_OGAM_RAMB_START_SLOPE_CNTL_G 0x32d0
#define mmDWB_OGAM_RAMB_START_SLOPE_CNTL_G_BASE_IDX 2
#define mmDWB_OGAM_RAMB_START_BASE_CNTL_R 0x32d1
#define mmDWB_OGAM_RAMB_START_BASE_CNTL_R_BASE_IDX 2
#define mmDWB_OGAM_RAMB_START_SLOPE_CNTL_R 0x32d2
#define mmDWB_OGAM_RAMB_START_SLOPE_CNTL_R_BASE_IDX 2
#define mmDWB_OGAM_RAMB_END_CNTL1_B 0x32d3
#define mmDWB_OGAM_RAMB_END_CNTL1_B_BASE_IDX 2
#define mmDWB_OGAM_RAMB_END_CNTL2_B 0x32d4
#define mmDWB_OGAM_RAMB_END_CNTL2_B_BASE_IDX 2
#define mmDWB_OGAM_RAMB_END_CNTL1_G 0x32d5
#define mmDWB_OGAM_RAMB_END_CNTL1_G_BASE_IDX 2
#define mmDWB_OGAM_RAMB_END_CNTL2_G 0x32d6
#define mmDWB_OGAM_RAMB_END_CNTL2_G_BASE_IDX 2
#define mmDWB_OGAM_RAMB_END_CNTL1_R 0x32d7
#define mmDWB_OGAM_RAMB_END_CNTL1_R_BASE_IDX 2
#define mmDWB_OGAM_RAMB_END_CNTL2_R 0x32d8
#define mmDWB_OGAM_RAMB_END_CNTL2_R_BASE_IDX 2
#define mmDWB_OGAM_RAMB_OFFSET_B 0x32d9
#define mmDWB_OGAM_RAMB_OFFSET_B_BASE_IDX 2
#define mmDWB_OGAM_RAMB_OFFSET_G 0x32da
#define mmDWB_OGAM_RAMB_OFFSET_G_BASE_IDX 2
#define mmDWB_OGAM_RAMB_OFFSET_R 0x32db
#define mmDWB_OGAM_RAMB_OFFSET_R_BASE_IDX 2
#define mmDWB_OGAM_RAMB_REGION_0_1 0x32dc
#define mmDWB_OGAM_RAMB_REGION_0_1_BASE_IDX 2
#define mmDWB_OGAM_RAMB_REGION_2_3 0x32dd
#define mmDWB_OGAM_RAMB_REGION_2_3_BASE_IDX 2
#define mmDWB_OGAM_RAMB_REGION_4_5 0x32de
#define mmDWB_OGAM_RAMB_REGION_4_5_BASE_IDX 2
#define mmDWB_OGAM_RAMB_REGION_6_7 0x32df
#define mmDWB_OGAM_RAMB_REGION_6_7_BASE_IDX 2
#define mmDWB_OGAM_RAMB_REGION_8_9 0x32e0
#define mmDWB_OGAM_RAMB_REGION_8_9_BASE_IDX 2
#define mmDWB_OGAM_RAMB_REGION_10_11 0x32e1
#define mmDWB_OGAM_RAMB_REGION_10_11_BASE_IDX 2
#define mmDWB_OGAM_RAMB_REGION_12_13 0x32e2
#define mmDWB_OGAM_RAMB_REGION_12_13_BASE_IDX 2
#define mmDWB_OGAM_RAMB_REGION_14_15 0x32e3
#define mmDWB_OGAM_RAMB_REGION_14_15_BASE_IDX 2
#define mmDWB_OGAM_RAMB_REGION_16_17 0x32e4
#define mmDWB_OGAM_RAMB_REGION_16_17_BASE_IDX 2
#define mmDWB_OGAM_RAMB_REGION_18_19 0x32e5
#define mmDWB_OGAM_RAMB_REGION_18_19_BASE_IDX 2
#define mmDWB_OGAM_RAMB_REGION_20_21 0x32e6
#define mmDWB_OGAM_RAMB_REGION_20_21_BASE_IDX 2
#define mmDWB_OGAM_RAMB_REGION_22_23 0x32e7
#define mmDWB_OGAM_RAMB_REGION_22_23_BASE_IDX 2
#define mmDWB_OGAM_RAMB_REGION_24_25 0x32e8
#define mmDWB_OGAM_RAMB_REGION_24_25_BASE_IDX 2
#define mmDWB_OGAM_RAMB_REGION_26_27 0x32e9
#define mmDWB_OGAM_RAMB_REGION_26_27_BASE_IDX 2
#define mmDWB_OGAM_RAMB_REGION_28_29 0x32ea
#define mmDWB_OGAM_RAMB_REGION_28_29_BASE_IDX 2
#define mmDWB_OGAM_RAMB_REGION_30_31 0x32eb
#define mmDWB_OGAM_RAMB_REGION_30_31_BASE_IDX 2
#define mmDWB_OGAM_RAMB_REGION_32_33 0x32ec
#define mmDWB_OGAM_RAMB_REGION_32_33_BASE_IDX 2
// addressBlock: dce_dc_mpc_mpcc0_dispdec
// base address: 0x0
#define mmMPCC0_MPCC_TOP_SEL 0x0000
#define mmMPCC0_MPCC_TOP_SEL_BASE_IDX 3
#define mmMPCC0_MPCC_BOT_SEL 0x0001
#define mmMPCC0_MPCC_BOT_SEL_BASE_IDX 3
#define mmMPCC0_MPCC_OPP_ID 0x0002
#define mmMPCC0_MPCC_OPP_ID_BASE_IDX 3
#define mmMPCC0_MPCC_CONTROL 0x0003
#define mmMPCC0_MPCC_CONTROL_BASE_IDX 3
#define mmMPCC0_MPCC_SM_CONTROL 0x0004
#define mmMPCC0_MPCC_SM_CONTROL_BASE_IDX 3
#define mmMPCC0_MPCC_UPDATE_LOCK_SEL 0x0005
#define mmMPCC0_MPCC_UPDATE_LOCK_SEL_BASE_IDX 3
#define mmMPCC0_MPCC_TOP_GAIN 0x0006
#define mmMPCC0_MPCC_TOP_GAIN_BASE_IDX 3
#define mmMPCC0_MPCC_BOT_GAIN_INSIDE 0x0007
#define mmMPCC0_MPCC_BOT_GAIN_INSIDE_BASE_IDX 3
#define mmMPCC0_MPCC_BOT_GAIN_OUTSIDE 0x0008
#define mmMPCC0_MPCC_BOT_GAIN_OUTSIDE_BASE_IDX 3
#define mmMPCC0_MPCC_BG_R_CR 0x0009
#define mmMPCC0_MPCC_BG_R_CR_BASE_IDX 3
#define mmMPCC0_MPCC_BG_G_Y 0x000a
#define mmMPCC0_MPCC_BG_G_Y_BASE_IDX 3
#define mmMPCC0_MPCC_BG_B_CB 0x000b
#define mmMPCC0_MPCC_BG_B_CB_BASE_IDX 3
#define mmMPCC0_MPCC_MEM_PWR_CTRL 0x000c
#define mmMPCC0_MPCC_MEM_PWR_CTRL_BASE_IDX 3
#define mmMPCC0_MPCC_STATUS 0x000d
#define mmMPCC0_MPCC_STATUS_BASE_IDX 3
// addressBlock: dce_dc_mpc_mpcc1_dispdec
// base address: 0x80
#define mmMPCC1_MPCC_TOP_SEL 0x0020
#define mmMPCC1_MPCC_TOP_SEL_BASE_IDX 3
#define mmMPCC1_MPCC_BOT_SEL 0x0021
#define mmMPCC1_MPCC_BOT_SEL_BASE_IDX 3
#define mmMPCC1_MPCC_OPP_ID 0x0022
#define mmMPCC1_MPCC_OPP_ID_BASE_IDX 3
#define mmMPCC1_MPCC_CONTROL 0x0023
#define mmMPCC1_MPCC_CONTROL_BASE_IDX 3
#define mmMPCC1_MPCC_SM_CONTROL 0x0024
#define mmMPCC1_MPCC_SM_CONTROL_BASE_IDX 3
#define mmMPCC1_MPCC_UPDATE_LOCK_SEL 0x0025
#define mmMPCC1_MPCC_UPDATE_LOCK_SEL_BASE_IDX 3
#define mmMPCC1_MPCC_TOP_GAIN 0x0026
#define mmMPCC1_MPCC_TOP_GAIN_BASE_IDX 3
#define mmMPCC1_MPCC_BOT_GAIN_INSIDE 0x0027
#define mmMPCC1_MPCC_BOT_GAIN_INSIDE_BASE_IDX 3
#define mmMPCC1_MPCC_BOT_GAIN_OUTSIDE 0x0028
#define mmMPCC1_MPCC_BOT_GAIN_OUTSIDE_BASE_IDX 3
#define mmMPCC1_MPCC_BG_R_CR 0x0029
#define mmMPCC1_MPCC_BG_R_CR_BASE_IDX 3
#define mmMPCC1_MPCC_BG_G_Y 0x002a
#define mmMPCC1_MPCC_BG_G_Y_BASE_IDX 3
#define mmMPCC1_MPCC_BG_B_CB 0x002b
#define mmMPCC1_MPCC_BG_B_CB_BASE_IDX 3
#define mmMPCC1_MPCC_MEM_PWR_CTRL 0x002c
#define mmMPCC1_MPCC_MEM_PWR_CTRL_BASE_IDX 3
#define mmMPCC1_MPCC_STATUS 0x002d
#define mmMPCC1_MPCC_STATUS_BASE_IDX 3
// addressBlock: dce_dc_mpc_mpcc2_dispdec
// base address: 0x100
#define mmMPCC2_MPCC_TOP_SEL 0x0040
#define mmMPCC2_MPCC_TOP_SEL_BASE_IDX 3
#define mmMPCC2_MPCC_BOT_SEL 0x0041
#define mmMPCC2_MPCC_BOT_SEL_BASE_IDX 3
#define mmMPCC2_MPCC_OPP_ID 0x0042
#define mmMPCC2_MPCC_OPP_ID_BASE_IDX 3
#define mmMPCC2_MPCC_CONTROL 0x0043
#define mmMPCC2_MPCC_CONTROL_BASE_IDX 3
#define mmMPCC2_MPCC_SM_CONTROL 0x0044
#define mmMPCC2_MPCC_SM_CONTROL_BASE_IDX 3
#define mmMPCC2_MPCC_UPDATE_LOCK_SEL 0x0045
#define mmMPCC2_MPCC_UPDATE_LOCK_SEL_BASE_IDX 3
#define mmMPCC2_MPCC_TOP_GAIN 0x0046
#define mmMPCC2_MPCC_TOP_GAIN_BASE_IDX 3
#define mmMPCC2_MPCC_BOT_GAIN_INSIDE 0x0047
#define mmMPCC2_MPCC_BOT_GAIN_INSIDE_BASE_IDX 3
#define mmMPCC2_MPCC_BOT_GAIN_OUTSIDE 0x0048
#define mmMPCC2_MPCC_BOT_GAIN_OUTSIDE_BASE_IDX 3
#define mmMPCC2_MPCC_BG_R_CR 0x0049
#define mmMPCC2_MPCC_BG_R_CR_BASE_IDX 3
#define mmMPCC2_MPCC_BG_G_Y 0x004a
#define mmMPCC2_MPCC_BG_G_Y_BASE_IDX 3
#define mmMPCC2_MPCC_BG_B_CB 0x004b
#define mmMPCC2_MPCC_BG_B_CB_BASE_IDX 3
#define mmMPCC2_MPCC_MEM_PWR_CTRL 0x004c
#define mmMPCC2_MPCC_MEM_PWR_CTRL_BASE_IDX 3
#define mmMPCC2_MPCC_STATUS 0x004d
#define mmMPCC2_MPCC_STATUS_BASE_IDX 3
// addressBlock: dce_dc_mpc_mpcc3_dispdec
// base address: 0x180
#define mmMPCC3_MPCC_TOP_SEL 0x0060
#define mmMPCC3_MPCC_TOP_SEL_BASE_IDX 3
#define mmMPCC3_MPCC_BOT_SEL 0x0061
#define mmMPCC3_MPCC_BOT_SEL_BASE_IDX 3
#define mmMPCC3_MPCC_OPP_ID 0x0062
#define mmMPCC3_MPCC_OPP_ID_BASE_IDX 3
#define mmMPCC3_MPCC_CONTROL 0x0063
#define mmMPCC3_MPCC_CONTROL_BASE_IDX 3
#define mmMPCC3_MPCC_SM_CONTROL 0x0064
#define mmMPCC3_MPCC_SM_CONTROL_BASE_IDX 3
#define mmMPCC3_MPCC_UPDATE_LOCK_SEL 0x0065
#define mmMPCC3_MPCC_UPDATE_LOCK_SEL_BASE_IDX 3
#define mmMPCC3_MPCC_TOP_GAIN 0x0066
#define mmMPCC3_MPCC_TOP_GAIN_BASE_IDX 3
#define mmMPCC3_MPCC_BOT_GAIN_INSIDE 0x0067
#define mmMPCC3_MPCC_BOT_GAIN_INSIDE_BASE_IDX 3
#define mmMPCC3_MPCC_BOT_GAIN_OUTSIDE 0x0068
#define mmMPCC3_MPCC_BOT_GAIN_OUTSIDE_BASE_IDX 3
#define mmMPCC3_MPCC_BG_R_CR 0x0069
#define mmMPCC3_MPCC_BG_R_CR_BASE_IDX 3
#define mmMPCC3_MPCC_BG_G_Y 0x006a
#define mmMPCC3_MPCC_BG_G_Y_BASE_IDX 3
#define mmMPCC3_MPCC_BG_B_CB 0x006b
#define mmMPCC3_MPCC_BG_B_CB_BASE_IDX 3
#define mmMPCC3_MPCC_MEM_PWR_CTRL 0x006c
#define mmMPCC3_MPCC_MEM_PWR_CTRL_BASE_IDX 3
#define mmMPCC3_MPCC_STATUS 0x006d
#define mmMPCC3_MPCC_STATUS_BASE_IDX 3
// addressBlock: dce_dc_mpc_mpcc4_dispdec
// base address: 0x200
#define mmMPCC4_MPCC_TOP_SEL 0x0080
#define mmMPCC4_MPCC_TOP_SEL_BASE_IDX 3
#define mmMPCC4_MPCC_BOT_SEL 0x0081
#define mmMPCC4_MPCC_BOT_SEL_BASE_IDX 3
#define mmMPCC4_MPCC_OPP_ID 0x0082
#define mmMPCC4_MPCC_OPP_ID_BASE_IDX 3
#define mmMPCC4_MPCC_CONTROL 0x0083
#define mmMPCC4_MPCC_CONTROL_BASE_IDX 3
#define mmMPCC4_MPCC_SM_CONTROL 0x0084
#define mmMPCC4_MPCC_SM_CONTROL_BASE_IDX 3
#define mmMPCC4_MPCC_UPDATE_LOCK_SEL 0x0085
#define mmMPCC4_MPCC_UPDATE_LOCK_SEL_BASE_IDX 3
#define mmMPCC4_MPCC_TOP_GAIN 0x0086
#define mmMPCC4_MPCC_TOP_GAIN_BASE_IDX 3
#define mmMPCC4_MPCC_BOT_GAIN_INSIDE 0x0087
#define mmMPCC4_MPCC_BOT_GAIN_INSIDE_BASE_IDX 3
#define mmMPCC4_MPCC_BOT_GAIN_OUTSIDE 0x0088
#define mmMPCC4_MPCC_BOT_GAIN_OUTSIDE_BASE_IDX 3
#define mmMPCC4_MPCC_BG_R_CR 0x0089
#define mmMPCC4_MPCC_BG_R_CR_BASE_IDX 3
#define mmMPCC4_MPCC_BG_G_Y 0x008a
#define mmMPCC4_MPCC_BG_G_Y_BASE_IDX 3
#define mmMPCC4_MPCC_BG_B_CB 0x008b
#define mmMPCC4_MPCC_BG_B_CB_BASE_IDX 3
#define mmMPCC4_MPCC_MEM_PWR_CTRL 0x008c
#define mmMPCC4_MPCC_MEM_PWR_CTRL_BASE_IDX 3
#define mmMPCC4_MPCC_STATUS 0x008d
#define mmMPCC4_MPCC_STATUS_BASE_IDX 3
// addressBlock: dce_dc_mpc_mpcc_ogam0_dispdec
// base address: 0x0
#define mmMPCC_OGAM0_MPCC_OGAM_CONTROL 0x0100
#define mmMPCC_OGAM0_MPCC_OGAM_CONTROL_BASE_IDX 3
#define mmMPCC_OGAM0_MPCC_OGAM_LUT_INDEX 0x0101
#define mmMPCC_OGAM0_MPCC_OGAM_LUT_INDEX_BASE_IDX 3
#define mmMPCC_OGAM0_MPCC_OGAM_LUT_DATA 0x0102
#define mmMPCC_OGAM0_MPCC_OGAM_LUT_DATA_BASE_IDX 3
#define mmMPCC_OGAM0_MPCC_OGAM_LUT_CONTROL 0x0103
#define mmMPCC_OGAM0_MPCC_OGAM_LUT_CONTROL_BASE_IDX 3
#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_START_CNTL_B 0x0104
#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_START_CNTL_B_BASE_IDX 3
#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_START_CNTL_G 0x0105
#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_START_CNTL_G_BASE_IDX 3
#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_START_CNTL_R 0x0106
#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_START_CNTL_R_BASE_IDX 3
#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_START_SLOPE_CNTL_B 0x0107
#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_START_SLOPE_CNTL_B_BASE_IDX 3
#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_START_SLOPE_CNTL_G 0x0108
#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_START_SLOPE_CNTL_G_BASE_IDX 3
#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_START_SLOPE_CNTL_R 0x0109
#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_START_SLOPE_CNTL_R_BASE_IDX 3
#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_START_BASE_CNTL_B 0x010a
#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_START_BASE_CNTL_B_BASE_IDX 3
#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_START_BASE_CNTL_G 0x010b
#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_START_BASE_CNTL_G_BASE_IDX 3
#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_START_BASE_CNTL_R 0x010c
#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_START_BASE_CNTL_R_BASE_IDX 3
#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL1_B 0x010d
#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL1_B_BASE_IDX 3
#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL2_B 0x010e
#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL2_B_BASE_IDX 3
#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL1_G 0x010f
#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL1_G_BASE_IDX 3
#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL2_G 0x0110
#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL2_G_BASE_IDX 3
#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL1_R 0x0111
#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL1_R_BASE_IDX 3
#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL2_R 0x0112
#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL2_R_BASE_IDX 3
#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_OFFSET_B 0x0113
#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_OFFSET_B_BASE_IDX 3
#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_OFFSET_G 0x0114
#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_OFFSET_G_BASE_IDX 3
#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_OFFSET_R 0x0115
#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_OFFSET_R_BASE_IDX 3
#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_0_1 0x0116
#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_0_1_BASE_IDX 3
#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_2_3 0x0117
#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_2_3_BASE_IDX 3
#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_4_5 0x0118
#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_4_5_BASE_IDX 3
#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_6_7 0x0119
#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_6_7_BASE_IDX 3
#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_8_9 0x011a
#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_8_9_BASE_IDX 3
#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_10_11 0x011b
#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_10_11_BASE_IDX 3
#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_12_13 0x011c
#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_12_13_BASE_IDX 3
#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_14_15 0x011d
#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_14_15_BASE_IDX 3
#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_16_17 0x011e
#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_16_17_BASE_IDX 3
#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_18_19 0x011f
#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_18_19_BASE_IDX 3
#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_20_21 0x0120
#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_20_21_BASE_IDX 3
#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_22_23 0x0121
#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_22_23_BASE_IDX 3
#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_24_25 0x0122
#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_24_25_BASE_IDX 3
#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_26_27 0x0123
#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_26_27_BASE_IDX 3
#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_28_29 0x0124
#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_28_29_BASE_IDX 3
#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_30_31 0x0125
#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_30_31_BASE_IDX 3
#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_32_33 0x0126
#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_32_33_BASE_IDX 3
#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_START_CNTL_B 0x0127
#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_START_CNTL_B_BASE_IDX 3
#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_START_CNTL_G 0x0128
#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_START_CNTL_G_BASE_IDX 3
#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_START_CNTL_R 0x0129
#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_START_CNTL_R_BASE_IDX 3
#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_START_SLOPE_CNTL_B 0x012a
#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_START_SLOPE_CNTL_B_BASE_IDX 3
#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_START_SLOPE_CNTL_G 0x012b
#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_START_SLOPE_CNTL_G_BASE_IDX 3
#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_START_SLOPE_CNTL_R 0x012c
#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_START_SLOPE_CNTL_R_BASE_IDX 3
#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_START_BASE_CNTL_B 0x012d
#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_START_BASE_CNTL_B_BASE_IDX 3
#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_START_BASE_CNTL_G 0x012e
#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_START_BASE_CNTL_G_BASE_IDX 3
#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_START_BASE_CNTL_R 0x012f
#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_START_BASE_CNTL_R_BASE_IDX 3
#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL1_B 0x0130
#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL1_B_BASE_IDX 3
#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL2_B 0x0131
#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL2_B_BASE_IDX 3
#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL1_G 0x0132
#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL1_G_BASE_IDX 3
#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL2_G 0x0133
#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL2_G_BASE_IDX 3
#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL1_R 0x0134
#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL1_R_BASE_IDX 3
#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL2_R 0x0135
#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL2_R_BASE_IDX 3
#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_OFFSET_B 0x0136
#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_OFFSET_B_BASE_IDX 3
#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_OFFSET_G 0x0137
#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_OFFSET_G_BASE_IDX 3
#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_OFFSET_R 0x0138
#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_OFFSET_R_BASE_IDX 3
#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_0_1 0x0139
#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_0_1_BASE_IDX 3
#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_2_3 0x013a
#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_2_3_BASE_IDX 3
#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_4_5 0x013b
#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_4_5_BASE_IDX 3
#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_6_7 0x013c
#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_6_7_BASE_IDX 3
#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_8_9 0x013d
#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_8_9_BASE_IDX 3
#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_10_11 0x013e
#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_10_11_BASE_IDX 3
#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_12_13 0x013f
#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_12_13_BASE_IDX 3
#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_14_15 0x0140
#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_14_15_BASE_IDX 3
#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_16_17 0x0141
#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_16_17_BASE_IDX 3
#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_18_19 0x0142
#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_18_19_BASE_IDX 3
#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_20_21 0x0143
#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_20_21_BASE_IDX 3
#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_22_23 0x0144
#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_22_23_BASE_IDX 3
#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_24_25 0x0145
#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_24_25_BASE_IDX 3
#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_26_27 0x0146
#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_26_27_BASE_IDX 3
#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_28_29 0x0147
#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_28_29_BASE_IDX 3
#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_30_31 0x0148
#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_30_31_BASE_IDX 3
#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_32_33 0x0149
#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_32_33_BASE_IDX 3
#define mmMPCC_OGAM0_MPCC_GAMUT_REMAP_COEF_FORMAT 0x014a
#define mmMPCC_OGAM0_MPCC_GAMUT_REMAP_COEF_FORMAT_BASE_IDX 3
#define mmMPCC_OGAM0_MPCC_GAMUT_REMAP_MODE 0x014b
#define mmMPCC_OGAM0_MPCC_GAMUT_REMAP_MODE_BASE_IDX 3
#define mmMPCC_OGAM0_MPC_GAMUT_REMAP_C11_C12_A 0x014c
#define mmMPCC_OGAM0_MPC_GAMUT_REMAP_C11_C12_A_BASE_IDX 3
#define mmMPCC_OGAM0_MPC_GAMUT_REMAP_C13_C14_A 0x014d
#define mmMPCC_OGAM0_MPC_GAMUT_REMAP_C13_C14_A_BASE_IDX 3
#define mmMPCC_OGAM0_MPC_GAMUT_REMAP_C21_C22_A 0x014e
#define mmMPCC_OGAM0_MPC_GAMUT_REMAP_C21_C22_A_BASE_IDX 3
#define mmMPCC_OGAM0_MPC_GAMUT_REMAP_C23_C24_A 0x014f
#define mmMPCC_OGAM0_MPC_GAMUT_REMAP_C23_C24_A_BASE_IDX 3
#define mmMPCC_OGAM0_MPC_GAMUT_REMAP_C31_C32_A 0x0150
#define mmMPCC_OGAM0_MPC_GAMUT_REMAP_C31_C32_A_BASE_IDX 3
#define mmMPCC_OGAM0_MPC_GAMUT_REMAP_C33_C34_A 0x0151
#define mmMPCC_OGAM0_MPC_GAMUT_REMAP_C33_C34_A_BASE_IDX 3
#define mmMPCC_OGAM0_MPC_GAMUT_REMAP_C11_C12_B 0x0152
#define mmMPCC_OGAM0_MPC_GAMUT_REMAP_C11_C12_B_BASE_IDX 3
#define mmMPCC_OGAM0_MPC_GAMUT_REMAP_C13_C14_B 0x0153
#define mmMPCC_OGAM0_MPC_GAMUT_REMAP_C13_C14_B_BASE_IDX 3
#define mmMPCC_OGAM0_MPC_GAMUT_REMAP_C21_C22_B 0x0154
#define mmMPCC_OGAM0_MPC_GAMUT_REMAP_C21_C22_B_BASE_IDX 3
#define mmMPCC_OGAM0_MPC_GAMUT_REMAP_C23_C24_B 0x0155
#define mmMPCC_OGAM0_MPC_GAMUT_REMAP_C23_C24_B_BASE_IDX 3
#define mmMPCC_OGAM0_MPC_GAMUT_REMAP_C31_C32_B 0x0156
#define mmMPCC_OGAM0_MPC_GAMUT_REMAP_C31_C32_B_BASE_IDX 3
#define mmMPCC_OGAM0_MPC_GAMUT_REMAP_C33_C34_B 0x0157
#define mmMPCC_OGAM0_MPC_GAMUT_REMAP_C33_C34_B_BASE_IDX 3
// addressBlock: dce_dc_mpc_mpcc_ogam1_dispdec
// base address: 0x200
#define mmMPCC_OGAM1_MPCC_OGAM_CONTROL 0x0180
#define mmMPCC_OGAM1_MPCC_OGAM_CONTROL_BASE_IDX 3
#define mmMPCC_OGAM1_MPCC_OGAM_LUT_INDEX 0x0181
#define mmMPCC_OGAM1_MPCC_OGAM_LUT_INDEX_BASE_IDX 3
#define mmMPCC_OGAM1_MPCC_OGAM_LUT_DATA 0x0182
#define mmMPCC_OGAM1_MPCC_OGAM_LUT_DATA_BASE_IDX 3
#define mmMPCC_OGAM1_MPCC_OGAM_LUT_CONTROL 0x0183
#define mmMPCC_OGAM1_MPCC_OGAM_LUT_CONTROL_BASE_IDX 3
#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_START_CNTL_B 0x0184
#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_START_CNTL_B_BASE_IDX 3
#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_START_CNTL_G 0x0185
#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_START_CNTL_G_BASE_IDX 3
#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_START_CNTL_R 0x0186
#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_START_CNTL_R_BASE_IDX 3
#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_START_SLOPE_CNTL_B 0x0187
#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_START_SLOPE_CNTL_B_BASE_IDX 3
#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_START_SLOPE_CNTL_G 0x0188
#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_START_SLOPE_CNTL_G_BASE_IDX 3
#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_START_SLOPE_CNTL_R 0x0189
#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_START_SLOPE_CNTL_R_BASE_IDX 3
#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_START_BASE_CNTL_B 0x018a
#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_START_BASE_CNTL_B_BASE_IDX 3
#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_START_BASE_CNTL_G 0x018b
#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_START_BASE_CNTL_G_BASE_IDX 3
#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_START_BASE_CNTL_R 0x018c
#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_START_BASE_CNTL_R_BASE_IDX 3
#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL1_B 0x018d
#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL1_B_BASE_IDX 3
#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL2_B 0x018e
#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL2_B_BASE_IDX 3
#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL1_G 0x018f
#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL1_G_BASE_IDX 3
#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL2_G 0x0190
#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL2_G_BASE_IDX 3
#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL1_R 0x0191
#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL1_R_BASE_IDX 3
#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL2_R 0x0192
#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL2_R_BASE_IDX 3
#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_OFFSET_B 0x0193
#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_OFFSET_B_BASE_IDX 3
#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_OFFSET_G 0x0194
#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_OFFSET_G_BASE_IDX 3
#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_OFFSET_R 0x0195
#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_OFFSET_R_BASE_IDX 3
#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_0_1 0x0196
#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_0_1_BASE_IDX 3
#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_2_3 0x0197
#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_2_3_BASE_IDX 3
#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_4_5 0x0198
#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_4_5_BASE_IDX 3
#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_6_7 0x0199
#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_6_7_BASE_IDX 3
#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_8_9 0x019a
#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_8_9_BASE_IDX 3
#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_10_11 0x019b
#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_10_11_BASE_IDX 3
#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_12_13 0x019c
#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_12_13_BASE_IDX 3
#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_14_15 0x019d
#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_14_15_BASE_IDX 3
#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_16_17 0x019e
#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_16_17_BASE_IDX 3
#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_18_19 0x019f
#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_18_19_BASE_IDX 3
#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_20_21 0x01a0
#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_20_21_BASE_IDX 3
#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_22_23 0x01a1
#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_22_23_BASE_IDX 3
#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_24_25 0x01a2
#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_24_25_BASE_IDX 3
#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_26_27 0x01a3
#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_26_27_BASE_IDX 3
#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_28_29 0x01a4
#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_28_29_BASE_IDX 3
#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_30_31 0x01a5
#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_30_31_BASE_IDX 3
#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_32_33 0x01a6
#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_32_33_BASE_IDX 3
#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_START_CNTL_B 0x01a7
#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_START_CNTL_B_BASE_IDX 3
#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_START_CNTL_G 0x01a8
#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_START_CNTL_G_BASE_IDX 3
#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_START_CNTL_R 0x01a9
#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_START_CNTL_R_BASE_IDX 3
#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_START_SLOPE_CNTL_B 0x01aa
#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_START_SLOPE_CNTL_B_BASE_IDX 3
#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_START_SLOPE_CNTL_G 0x01ab
#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_START_SLOPE_CNTL_G_BASE_IDX 3
#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_START_SLOPE_CNTL_R 0x01ac
#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_START_SLOPE_CNTL_R_BASE_IDX 3
#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_START_BASE_CNTL_B 0x01ad
#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_START_BASE_CNTL_B_BASE_IDX 3
#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_START_BASE_CNTL_G 0x01ae
#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_START_BASE_CNTL_G_BASE_IDX 3
#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_START_BASE_CNTL_R 0x01af
#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_START_BASE_CNTL_R_BASE_IDX 3
#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL1_B 0x01b0
#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL1_B_BASE_IDX 3
#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL2_B 0x01b1
#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL2_B_BASE_IDX 3
#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL1_G 0x01b2
#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL1_G_BASE_IDX 3
#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL2_G 0x01b3
#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL2_G_BASE_IDX 3
#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL1_R 0x01b4
#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL1_R_BASE_IDX 3
#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL2_R 0x01b5
#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL2_R_BASE_IDX 3
#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_OFFSET_B 0x01b6
#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_OFFSET_B_BASE_IDX 3
#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_OFFSET_G 0x01b7
#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_OFFSET_G_BASE_IDX 3
#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_OFFSET_R 0x01b8
#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_OFFSET_R_BASE_IDX 3
#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_0_1 0x01b9
#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_0_1_BASE_IDX 3
#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_2_3 0x01ba
#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_2_3_BASE_IDX 3
#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_4_5 0x01bb
#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_4_5_BASE_IDX 3
#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_6_7 0x01bc
#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_6_7_BASE_IDX 3
#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_8_9 0x01bd
#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_8_9_BASE_IDX 3
#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_10_11 0x01be
#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_10_11_BASE_IDX 3
#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_12_13 0x01bf
#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_12_13_BASE_IDX 3
#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_14_15 0x01c0
#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_14_15_BASE_IDX 3
#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_16_17 0x01c1
#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_16_17_BASE_IDX 3
#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_18_19 0x01c2
#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_18_19_BASE_IDX 3
#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_20_21 0x01c3
#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_20_21_BASE_IDX 3
#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_22_23 0x01c4
#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_22_23_BASE_IDX 3
#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_24_25 0x01c5
#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_24_25_BASE_IDX 3
#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_26_27 0x01c6
#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_26_27_BASE_IDX 3
#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_28_29 0x01c7
#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_28_29_BASE_IDX 3
#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_30_31 0x01c8
#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_30_31_BASE_IDX 3
#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_32_33 0x01c9
#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_32_33_BASE_IDX 3
#define mmMPCC_OGAM1_MPCC_GAMUT_REMAP_COEF_FORMAT 0x01ca
#define mmMPCC_OGAM1_MPCC_GAMUT_REMAP_COEF_FORMAT_BASE_IDX 3
#define mmMPCC_OGAM1_MPCC_GAMUT_REMAP_MODE 0x01cb
#define mmMPCC_OGAM1_MPCC_GAMUT_REMAP_MODE_BASE_IDX 3
#define mmMPCC_OGAM1_MPC_GAMUT_REMAP_C11_C12_A 0x01cc
#define mmMPCC_OGAM1_MPC_GAMUT_REMAP_C11_C12_A_BASE_IDX 3
#define mmMPCC_OGAM1_MPC_GAMUT_REMAP_C13_C14_A 0x01cd
#define mmMPCC_OGAM1_MPC_GAMUT_REMAP_C13_C14_A_BASE_IDX 3
#define mmMPCC_OGAM1_MPC_GAMUT_REMAP_C21_C22_A 0x01ce
#define mmMPCC_OGAM1_MPC_GAMUT_REMAP_C21_C22_A_BASE_IDX 3
#define mmMPCC_OGAM1_MPC_GAMUT_REMAP_C23_C24_A 0x01cf
#define mmMPCC_OGAM1_MPC_GAMUT_REMAP_C23_C24_A_BASE_IDX 3
#define mmMPCC_OGAM1_MPC_GAMUT_REMAP_C31_C32_A 0x01d0
#define mmMPCC_OGAM1_MPC_GAMUT_REMAP_C31_C32_A_BASE_IDX 3
#define mmMPCC_OGAM1_MPC_GAMUT_REMAP_C33_C34_A 0x01d1
#define mmMPCC_OGAM1_MPC_GAMUT_REMAP_C33_C34_A_BASE_IDX 3
#define mmMPCC_OGAM1_MPC_GAMUT_REMAP_C11_C12_B 0x01d2
#define mmMPCC_OGAM1_MPC_GAMUT_REMAP_C11_C12_B_BASE_IDX 3
#define mmMPCC_OGAM1_MPC_GAMUT_REMAP_C13_C14_B 0x01d3
#define mmMPCC_OGAM1_MPC_GAMUT_REMAP_C13_C14_B_BASE_IDX 3
#define mmMPCC_OGAM1_MPC_GAMUT_REMAP_C21_C22_B 0x01d4
#define mmMPCC_OGAM1_MPC_GAMUT_REMAP_C21_C22_B_BASE_IDX 3
#define mmMPCC_OGAM1_MPC_GAMUT_REMAP_C23_C24_B 0x01d5
#define mmMPCC_OGAM1_MPC_GAMUT_REMAP_C23_C24_B_BASE_IDX 3
#define mmMPCC_OGAM1_MPC_GAMUT_REMAP_C31_C32_B 0x01d6
#define mmMPCC_OGAM1_MPC_GAMUT_REMAP_C31_C32_B_BASE_IDX 3
#define mmMPCC_OGAM1_MPC_GAMUT_REMAP_C33_C34_B 0x01d7
#define mmMPCC_OGAM1_MPC_GAMUT_REMAP_C33_C34_B_BASE_IDX 3
// addressBlock: dce_dc_mpc_mpcc_ogam2_dispdec
// base address: 0x400
#define mmMPCC_OGAM2_MPCC_OGAM_CONTROL 0x0200
#define mmMPCC_OGAM2_MPCC_OGAM_CONTROL_BASE_IDX 3
#define mmMPCC_OGAM2_MPCC_OGAM_LUT_INDEX 0x0201
#define mmMPCC_OGAM2_MPCC_OGAM_LUT_INDEX_BASE_IDX 3
#define mmMPCC_OGAM2_MPCC_OGAM_LUT_DATA 0x0202
#define mmMPCC_OGAM2_MPCC_OGAM_LUT_DATA_BASE_IDX 3
#define mmMPCC_OGAM2_MPCC_OGAM_LUT_CONTROL 0x0203
#define mmMPCC_OGAM2_MPCC_OGAM_LUT_CONTROL_BASE_IDX 3
#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_START_CNTL_B 0x0204
#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_START_CNTL_B_BASE_IDX 3
#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_START_CNTL_G 0x0205
#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_START_CNTL_G_BASE_IDX 3
#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_START_CNTL_R 0x0206
#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_START_CNTL_R_BASE_IDX 3
#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_START_SLOPE_CNTL_B 0x0207
#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_START_SLOPE_CNTL_B_BASE_IDX 3
#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_START_SLOPE_CNTL_G 0x0208
#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_START_SLOPE_CNTL_G_BASE_IDX 3
#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_START_SLOPE_CNTL_R 0x0209
#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_START_SLOPE_CNTL_R_BASE_IDX 3
#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_START_BASE_CNTL_B 0x020a
#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_START_BASE_CNTL_B_BASE_IDX 3
#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_START_BASE_CNTL_G 0x020b
#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_START_BASE_CNTL_G_BASE_IDX 3
#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_START_BASE_CNTL_R 0x020c
#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_START_BASE_CNTL_R_BASE_IDX 3
#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL1_B 0x020d
#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL1_B_BASE_IDX 3
#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL2_B 0x020e
#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL2_B_BASE_IDX 3
#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL1_G 0x020f
#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL1_G_BASE_IDX 3
#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL2_G 0x0210
#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL2_G_BASE_IDX 3
#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL1_R 0x0211
#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL1_R_BASE_IDX 3
#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL2_R 0x0212
#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL2_R_BASE_IDX 3
#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_OFFSET_B 0x0213
#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_OFFSET_B_BASE_IDX 3
#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_OFFSET_G 0x0214
#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_OFFSET_G_BASE_IDX 3
#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_OFFSET_R 0x0215
#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_OFFSET_R_BASE_IDX 3
#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_0_1 0x0216
#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_0_1_BASE_IDX 3
#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_2_3 0x0217
#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_2_3_BASE_IDX 3
#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_4_5 0x0218
#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_4_5_BASE_IDX 3
#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_6_7 0x0219
#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_6_7_BASE_IDX 3
#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_8_9 0x021a
#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_8_9_BASE_IDX 3
#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_10_11 0x021b
#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_10_11_BASE_IDX 3
#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_12_13 0x021c
#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_12_13_BASE_IDX 3
#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_14_15 0x021d
#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_14_15_BASE_IDX 3
#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_16_17 0x021e
#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_16_17_BASE_IDX 3
#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_18_19 0x021f
#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_18_19_BASE_IDX 3
#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_20_21 0x0220
#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_20_21_BASE_IDX 3
#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_22_23 0x0221
#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_22_23_BASE_IDX 3
#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_24_25 0x0222
#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_24_25_BASE_IDX 3
#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_26_27 0x0223
#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_26_27_BASE_IDX 3
#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_28_29 0x0224
#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_28_29_BASE_IDX 3
#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_30_31 0x0225
#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_30_31_BASE_IDX 3
#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_32_33 0x0226
#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_32_33_BASE_IDX 3
#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_START_CNTL_B 0x0227
#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_START_CNTL_B_BASE_IDX 3
#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_START_CNTL_G 0x0228
#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_START_CNTL_G_BASE_IDX 3
#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_START_CNTL_R 0x0229
#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_START_CNTL_R_BASE_IDX 3
#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_START_SLOPE_CNTL_B 0x022a
#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_START_SLOPE_CNTL_B_BASE_IDX 3
#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_START_SLOPE_CNTL_G 0x022b
#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_START_SLOPE_CNTL_G_BASE_IDX 3
#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_START_SLOPE_CNTL_R 0x022c
#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_START_SLOPE_CNTL_R_BASE_IDX 3
#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_START_BASE_CNTL_B 0x022d
#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_START_BASE_CNTL_B_BASE_IDX 3
#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_START_BASE_CNTL_G 0x022e
#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_START_BASE_CNTL_G_BASE_IDX 3
#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_START_BASE_CNTL_R 0x022f
#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_START_BASE_CNTL_R_BASE_IDX 3
#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL1_B 0x0230
#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL1_B_BASE_IDX 3
#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL2_B 0x0231
#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL2_B_BASE_IDX 3
#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL1_G 0x0232
#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL1_G_BASE_IDX 3
#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL2_G 0x0233
#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL2_G_BASE_IDX 3
#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL1_R 0x0234
#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL1_R_BASE_IDX 3
#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL2_R 0x0235
#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL2_R_BASE_IDX 3
#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_OFFSET_B 0x0236
#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_OFFSET_B_BASE_IDX 3
#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_OFFSET_G 0x0237
#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_OFFSET_G_BASE_IDX 3
#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_OFFSET_R 0x0238
#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_OFFSET_R_BASE_IDX 3
#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_0_1 0x0239
#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_0_1_BASE_IDX 3
#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_2_3 0x023a
#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_2_3_BASE_IDX 3
#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_4_5 0x023b
#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_4_5_BASE_IDX 3
#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_6_7 0x023c
#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_6_7_BASE_IDX 3
#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_8_9 0x023d
#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_8_9_BASE_IDX 3
#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_10_11 0x023e
#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_10_11_BASE_IDX 3
#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_12_13 0x023f
#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_12_13_BASE_IDX 3
#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_14_15 0x0240
#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_14_15_BASE_IDX 3
#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_16_17 0x0241
#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_16_17_BASE_IDX 3
#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_18_19 0x0242
#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_18_19_BASE_IDX 3
#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_20_21 0x0243
#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_20_21_BASE_IDX 3
#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_22_23 0x0244
#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_22_23_BASE_IDX 3
#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_24_25 0x0245
#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_24_25_BASE_IDX 3
#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_26_27 0x0246
#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_26_27_BASE_IDX 3
#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_28_29 0x0247
#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_28_29_BASE_IDX 3
#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_30_31 0x0248
#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_30_31_BASE_IDX 3
#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_32_33 0x0249
#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_32_33_BASE_IDX 3
#define mmMPCC_OGAM2_MPCC_GAMUT_REMAP_COEF_FORMAT 0x024a
#define mmMPCC_OGAM2_MPCC_GAMUT_REMAP_COEF_FORMAT_BASE_IDX 3
#define mmMPCC_OGAM2_MPCC_GAMUT_REMAP_MODE 0x024b
#define mmMPCC_OGAM2_MPCC_GAMUT_REMAP_MODE_BASE_IDX 3
#define mmMPCC_OGAM2_MPC_GAMUT_REMAP_C11_C12_A 0x024c
#define mmMPCC_OGAM2_MPC_GAMUT_REMAP_C11_C12_A_BASE_IDX 3
#define mmMPCC_OGAM2_MPC_GAMUT_REMAP_C13_C14_A 0x024d
#define mmMPCC_OGAM2_MPC_GAMUT_REMAP_C13_C14_A_BASE_IDX 3
#define mmMPCC_OGAM2_MPC_GAMUT_REMAP_C21_C22_A 0x024e
#define mmMPCC_OGAM2_MPC_GAMUT_REMAP_C21_C22_A_BASE_IDX 3
#define mmMPCC_OGAM2_MPC_GAMUT_REMAP_C23_C24_A 0x024f
#define mmMPCC_OGAM2_MPC_GAMUT_REMAP_C23_C24_A_BASE_IDX 3
#define mmMPCC_OGAM2_MPC_GAMUT_REMAP_C31_C32_A 0x0250
#define mmMPCC_OGAM2_MPC_GAMUT_REMAP_C31_C32_A_BASE_IDX 3
#define mmMPCC_OGAM2_MPC_GAMUT_REMAP_C33_C34_A 0x0251
#define mmMPCC_OGAM2_MPC_GAMUT_REMAP_C33_C34_A_BASE_IDX 3
#define mmMPCC_OGAM2_MPC_GAMUT_REMAP_C11_C12_B 0x0252
#define mmMPCC_OGAM2_MPC_GAMUT_REMAP_C11_C12_B_BASE_IDX 3
#define mmMPCC_OGAM2_MPC_GAMUT_REMAP_C13_C14_B 0x0253
#define mmMPCC_OGAM2_MPC_GAMUT_REMAP_C13_C14_B_BASE_IDX 3
#define mmMPCC_OGAM2_MPC_GAMUT_REMAP_C21_C22_B 0x0254
#define mmMPCC_OGAM2_MPC_GAMUT_REMAP_C21_C22_B_BASE_IDX 3
#define mmMPCC_OGAM2_MPC_GAMUT_REMAP_C23_C24_B 0x0255
#define mmMPCC_OGAM2_MPC_GAMUT_REMAP_C23_C24_B_BASE_IDX 3
#define mmMPCC_OGAM2_MPC_GAMUT_REMAP_C31_C32_B 0x0256
#define mmMPCC_OGAM2_MPC_GAMUT_REMAP_C31_C32_B_BASE_IDX 3
#define mmMPCC_OGAM2_MPC_GAMUT_REMAP_C33_C34_B 0x0257
#define mmMPCC_OGAM2_MPC_GAMUT_REMAP_C33_C34_B_BASE_IDX 3
// addressBlock: dce_dc_mpc_mpcc_ogam3_dispdec
// base address: 0x600
#define mmMPCC_OGAM3_MPCC_OGAM_CONTROL 0x0280
#define mmMPCC_OGAM3_MPCC_OGAM_CONTROL_BASE_IDX 3
#define mmMPCC_OGAM3_MPCC_OGAM_LUT_INDEX 0x0281
#define mmMPCC_OGAM3_MPCC_OGAM_LUT_INDEX_BASE_IDX 3
#define mmMPCC_OGAM3_MPCC_OGAM_LUT_DATA 0x0282
#define mmMPCC_OGAM3_MPCC_OGAM_LUT_DATA_BASE_IDX 3
#define mmMPCC_OGAM3_MPCC_OGAM_LUT_CONTROL 0x0283
#define mmMPCC_OGAM3_MPCC_OGAM_LUT_CONTROL_BASE_IDX 3
#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_START_CNTL_B 0x0284
#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_START_CNTL_B_BASE_IDX 3
#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_START_CNTL_G 0x0285
#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_START_CNTL_G_BASE_IDX 3
#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_START_CNTL_R 0x0286
#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_START_CNTL_R_BASE_IDX 3
#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_START_SLOPE_CNTL_B 0x0287
#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_START_SLOPE_CNTL_B_BASE_IDX 3
#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_START_SLOPE_CNTL_G 0x0288
#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_START_SLOPE_CNTL_G_BASE_IDX 3
#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_START_SLOPE_CNTL_R 0x0289
#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_START_SLOPE_CNTL_R_BASE_IDX 3
#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_START_BASE_CNTL_B 0x028a
#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_START_BASE_CNTL_B_BASE_IDX 3
#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_START_BASE_CNTL_G 0x028b
#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_START_BASE_CNTL_G_BASE_IDX 3
#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_START_BASE_CNTL_R 0x028c
#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_START_BASE_CNTL_R_BASE_IDX 3
#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL1_B 0x028d
#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL1_B_BASE_IDX 3
#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL2_B 0x028e
#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL2_B_BASE_IDX 3
#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL1_G 0x028f
#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL1_G_BASE_IDX 3
#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL2_G 0x0290
#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL2_G_BASE_IDX 3
#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL1_R 0x0291
#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL1_R_BASE_IDX 3
#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL2_R 0x0292
#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL2_R_BASE_IDX 3
#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_OFFSET_B 0x0293
#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_OFFSET_B_BASE_IDX 3
#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_OFFSET_G 0x0294
#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_OFFSET_G_BASE_IDX 3
#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_OFFSET_R 0x0295
#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_OFFSET_R_BASE_IDX 3
#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_0_1 0x0296
#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_0_1_BASE_IDX 3
#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_2_3 0x0297
#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_2_3_BASE_IDX 3
#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_4_5 0x0298
#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_4_5_BASE_IDX 3
#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_6_7 0x0299
#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_6_7_BASE_IDX 3
#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_8_9 0x029a
#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_8_9_BASE_IDX 3
#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_10_11 0x029b
#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_10_11_BASE_IDX 3
#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_12_13 0x029c
#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_12_13_BASE_IDX 3
#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_14_15 0x029d
#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_14_15_BASE_IDX 3
#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_16_17 0x029e
#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_16_17_BASE_IDX 3
#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_18_19 0x029f
#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_18_19_BASE_IDX 3
#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_20_21 0x02a0
#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_20_21_BASE_IDX 3
#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_22_23 0x02a1
#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_22_23_BASE_IDX 3
#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_24_25 0x02a2
#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_24_25_BASE_IDX 3
#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_26_27 0x02a3
#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_26_27_BASE_IDX 3
#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_28_29 0x02a4
#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_28_29_BASE_IDX 3
#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_30_31 0x02a5
#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_30_31_BASE_IDX 3
#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_32_33 0x02a6
#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_32_33_BASE_IDX 3
#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_START_CNTL_B 0x02a7
#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_START_CNTL_B_BASE_IDX 3
#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_START_CNTL_G 0x02a8
#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_START_CNTL_G_BASE_IDX 3
#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_START_CNTL_R 0x02a9
#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_START_CNTL_R_BASE_IDX 3
#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_START_SLOPE_CNTL_B 0x02aa
#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_START_SLOPE_CNTL_B_BASE_IDX 3
#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_START_SLOPE_CNTL_G 0x02ab
#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_START_SLOPE_CNTL_G_BASE_IDX 3
#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_START_SLOPE_CNTL_R 0x02ac
#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_START_SLOPE_CNTL_R_BASE_IDX 3
#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_START_BASE_CNTL_B 0x02ad
#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_START_BASE_CNTL_B_BASE_IDX 3
#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_START_BASE_CNTL_G 0x02ae
#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_START_BASE_CNTL_G_BASE_IDX 3
#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_START_BASE_CNTL_R 0x02af
#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_START_BASE_CNTL_R_BASE_IDX 3
#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL1_B 0x02b0
#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL1_B_BASE_IDX 3
#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL2_B 0x02b1
#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL2_B_BASE_IDX 3
#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL1_G 0x02b2
#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL1_G_BASE_IDX 3
#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL2_G 0x02b3
#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL2_G_BASE_IDX 3
#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL1_R 0x02b4
#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL1_R_BASE_IDX 3
#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL2_R 0x02b5
#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL2_R_BASE_IDX 3
#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_OFFSET_B 0x02b6
#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_OFFSET_B_BASE_IDX 3
#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_OFFSET_G 0x02b7
#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_OFFSET_G_BASE_IDX 3
#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_OFFSET_R 0x02b8
#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_OFFSET_R_BASE_IDX 3
#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_0_1 0x02b9
#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_0_1_BASE_IDX 3
#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_2_3 0x02ba
#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_2_3_BASE_IDX 3
#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_4_5 0x02bb
#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_4_5_BASE_IDX 3
#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_6_7 0x02bc
#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_6_7_BASE_IDX 3
#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_8_9 0x02bd
#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_8_9_BASE_IDX 3
#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_10_11 0x02be
#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_10_11_BASE_IDX 3
#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_12_13 0x02bf
#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_12_13_BASE_IDX 3
#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_14_15 0x02c0
#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_14_15_BASE_IDX 3
#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_16_17 0x02c1
#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_16_17_BASE_IDX 3
#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_18_19 0x02c2
#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_18_19_BASE_IDX 3
#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_20_21 0x02c3
#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_20_21_BASE_IDX 3
#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_22_23 0x02c4
#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_22_23_BASE_IDX 3
#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_24_25 0x02c5
#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_24_25_BASE_IDX 3
#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_26_27 0x02c6
#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_26_27_BASE_IDX 3
#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_28_29 0x02c7
#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_28_29_BASE_IDX 3
#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_30_31 0x02c8
#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_30_31_BASE_IDX 3
#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_32_33 0x02c9
#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_32_33_BASE_IDX 3
#define mmMPCC_OGAM3_MPCC_GAMUT_REMAP_COEF_FORMAT 0x02ca
#define mmMPCC_OGAM3_MPCC_GAMUT_REMAP_COEF_FORMAT_BASE_IDX 3
#define mmMPCC_OGAM3_MPCC_GAMUT_REMAP_MODE 0x02cb
#define mmMPCC_OGAM3_MPCC_GAMUT_REMAP_MODE_BASE_IDX 3
#define mmMPCC_OGAM3_MPC_GAMUT_REMAP_C11_C12_A 0x02cc
#define mmMPCC_OGAM3_MPC_GAMUT_REMAP_C11_C12_A_BASE_IDX 3
#define mmMPCC_OGAM3_MPC_GAMUT_REMAP_C13_C14_A 0x02cd
#define mmMPCC_OGAM3_MPC_GAMUT_REMAP_C13_C14_A_BASE_IDX 3
#define mmMPCC_OGAM3_MPC_GAMUT_REMAP_C21_C22_A 0x02ce
#define mmMPCC_OGAM3_MPC_GAMUT_REMAP_C21_C22_A_BASE_IDX 3
#define mmMPCC_OGAM3_MPC_GAMUT_REMAP_C23_C24_A 0x02cf
#define mmMPCC_OGAM3_MPC_GAMUT_REMAP_C23_C24_A_BASE_IDX 3
#define mmMPCC_OGAM3_MPC_GAMUT_REMAP_C31_C32_A 0x02d0
#define mmMPCC_OGAM3_MPC_GAMUT_REMAP_C31_C32_A_BASE_IDX 3
#define mmMPCC_OGAM3_MPC_GAMUT_REMAP_C33_C34_A 0x02d1
#define mmMPCC_OGAM3_MPC_GAMUT_REMAP_C33_C34_A_BASE_IDX 3
#define mmMPCC_OGAM3_MPC_GAMUT_REMAP_C11_C12_B 0x02d2
#define mmMPCC_OGAM3_MPC_GAMUT_REMAP_C11_C12_B_BASE_IDX 3
#define mmMPCC_OGAM3_MPC_GAMUT_REMAP_C13_C14_B 0x02d3
#define mmMPCC_OGAM3_MPC_GAMUT_REMAP_C13_C14_B_BASE_IDX 3
#define mmMPCC_OGAM3_MPC_GAMUT_REMAP_C21_C22_B 0x02d4
#define mmMPCC_OGAM3_MPC_GAMUT_REMAP_C21_C22_B_BASE_IDX 3
#define mmMPCC_OGAM3_MPC_GAMUT_REMAP_C23_C24_B 0x02d5
#define mmMPCC_OGAM3_MPC_GAMUT_REMAP_C23_C24_B_BASE_IDX 3
#define mmMPCC_OGAM3_MPC_GAMUT_REMAP_C31_C32_B 0x02d6
#define mmMPCC_OGAM3_MPC_GAMUT_REMAP_C31_C32_B_BASE_IDX 3
#define mmMPCC_OGAM3_MPC_GAMUT_REMAP_C33_C34_B 0x02d7
#define mmMPCC_OGAM3_MPC_GAMUT_REMAP_C33_C34_B_BASE_IDX 3
// addressBlock: dce_dc_mpc_mpcc_ogam4_dispdec
// base address: 0x800
#define mmMPCC_OGAM4_MPCC_OGAM_CONTROL 0x0300
#define mmMPCC_OGAM4_MPCC_OGAM_CONTROL_BASE_IDX 3
#define mmMPCC_OGAM4_MPCC_OGAM_LUT_INDEX 0x0301
#define mmMPCC_OGAM4_MPCC_OGAM_LUT_INDEX_BASE_IDX 3
#define mmMPCC_OGAM4_MPCC_OGAM_LUT_DATA 0x0302
#define mmMPCC_OGAM4_MPCC_OGAM_LUT_DATA_BASE_IDX 3
#define mmMPCC_OGAM4_MPCC_OGAM_LUT_CONTROL 0x0303
#define mmMPCC_OGAM4_MPCC_OGAM_LUT_CONTROL_BASE_IDX 3
#define mmMPCC_OGAM4_MPCC_OGAM_RAMA_START_CNTL_B 0x0304
#define mmMPCC_OGAM4_MPCC_OGAM_RAMA_START_CNTL_B_BASE_IDX 3
#define mmMPCC_OGAM4_MPCC_OGAM_RAMA_START_CNTL_G 0x0305
#define mmMPCC_OGAM4_MPCC_OGAM_RAMA_START_CNTL_G_BASE_IDX 3
#define mmMPCC_OGAM4_MPCC_OGAM_RAMA_START_CNTL_R 0x0306
#define mmMPCC_OGAM4_MPCC_OGAM_RAMA_START_CNTL_R_BASE_IDX 3
#define mmMPCC_OGAM4_MPCC_OGAM_RAMA_START_SLOPE_CNTL_B 0x0307
#define mmMPCC_OGAM4_MPCC_OGAM_RAMA_START_SLOPE_CNTL_B_BASE_IDX 3
#define mmMPCC_OGAM4_MPCC_OGAM_RAMA_START_SLOPE_CNTL_G 0x0308
#define mmMPCC_OGAM4_MPCC_OGAM_RAMA_START_SLOPE_CNTL_G_BASE_IDX 3
#define mmMPCC_OGAM4_MPCC_OGAM_RAMA_START_SLOPE_CNTL_R 0x0309
#define mmMPCC_OGAM4_MPCC_OGAM_RAMA_START_SLOPE_CNTL_R_BASE_IDX 3
#define mmMPCC_OGAM4_MPCC_OGAM_RAMA_START_BASE_CNTL_B 0x030a
#define mmMPCC_OGAM4_MPCC_OGAM_RAMA_START_BASE_CNTL_B_BASE_IDX 3
#define mmMPCC_OGAM4_MPCC_OGAM_RAMA_START_BASE_CNTL_G 0x030b
#define mmMPCC_OGAM4_MPCC_OGAM_RAMA_START_BASE_CNTL_G_BASE_IDX 3
#define mmMPCC_OGAM4_MPCC_OGAM_RAMA_START_BASE_CNTL_R 0x030c
#define mmMPCC_OGAM4_MPCC_OGAM_RAMA_START_BASE_CNTL_R_BASE_IDX 3
#define mmMPCC_OGAM4_MPCC_OGAM_RAMA_END_CNTL1_B 0x030d
#define mmMPCC_OGAM4_MPCC_OGAM_RAMA_END_CNTL1_B_BASE_IDX 3
#define mmMPCC_OGAM4_MPCC_OGAM_RAMA_END_CNTL2_B 0x030e
#define mmMPCC_OGAM4_MPCC_OGAM_RAMA_END_CNTL2_B_BASE_IDX 3
#define mmMPCC_OGAM4_MPCC_OGAM_RAMA_END_CNTL1_G 0x030f
#define mmMPCC_OGAM4_MPCC_OGAM_RAMA_END_CNTL1_G_BASE_IDX 3
#define mmMPCC_OGAM4_MPCC_OGAM_RAMA_END_CNTL2_G 0x0310
#define mmMPCC_OGAM4_MPCC_OGAM_RAMA_END_CNTL2_G_BASE_IDX 3
#define mmMPCC_OGAM4_MPCC_OGAM_RAMA_END_CNTL1_R 0x0311
#define mmMPCC_OGAM4_MPCC_OGAM_RAMA_END_CNTL1_R_BASE_IDX 3
#define mmMPCC_OGAM4_MPCC_OGAM_RAMA_END_CNTL2_R 0x0312
#define mmMPCC_OGAM4_MPCC_OGAM_RAMA_END_CNTL2_R_BASE_IDX 3
#define mmMPCC_OGAM4_MPCC_OGAM_RAMA_OFFSET_B 0x0313
#define mmMPCC_OGAM4_MPCC_OGAM_RAMA_OFFSET_B_BASE_IDX 3
#define mmMPCC_OGAM4_MPCC_OGAM_RAMA_OFFSET_G 0x0314
#define mmMPCC_OGAM4_MPCC_OGAM_RAMA_OFFSET_G_BASE_IDX 3
#define mmMPCC_OGAM4_MPCC_OGAM_RAMA_OFFSET_R 0x0315
#define mmMPCC_OGAM4_MPCC_OGAM_RAMA_OFFSET_R_BASE_IDX 3
#define mmMPCC_OGAM4_MPCC_OGAM_RAMA_REGION_0_1 0x0316
#define mmMPCC_OGAM4_MPCC_OGAM_RAMA_REGION_0_1_BASE_IDX 3
#define mmMPCC_OGAM4_MPCC_OGAM_RAMA_REGION_2_3 0x0317
#define mmMPCC_OGAM4_MPCC_OGAM_RAMA_REGION_2_3_BASE_IDX 3
#define mmMPCC_OGAM4_MPCC_OGAM_RAMA_REGION_4_5 0x0318
#define mmMPCC_OGAM4_MPCC_OGAM_RAMA_REGION_4_5_BASE_IDX 3
#define mmMPCC_OGAM4_MPCC_OGAM_RAMA_REGION_6_7 0x0319
#define mmMPCC_OGAM4_MPCC_OGAM_RAMA_REGION_6_7_BASE_IDX 3
#define mmMPCC_OGAM4_MPCC_OGAM_RAMA_REGION_8_9 0x031a
#define mmMPCC_OGAM4_MPCC_OGAM_RAMA_REGION_8_9_BASE_IDX 3
#define mmMPCC_OGAM4_MPCC_OGAM_RAMA_REGION_10_11 0x031b
#define mmMPCC_OGAM4_MPCC_OGAM_RAMA_REGION_10_11_BASE_IDX 3
#define mmMPCC_OGAM4_MPCC_OGAM_RAMA_REGION_12_13 0x031c
#define mmMPCC_OGAM4_MPCC_OGAM_RAMA_REGION_12_13_BASE_IDX 3
#define mmMPCC_OGAM4_MPCC_OGAM_RAMA_REGION_14_15 0x031d
#define mmMPCC_OGAM4_MPCC_OGAM_RAMA_REGION_14_15_BASE_IDX 3
#define mmMPCC_OGAM4_MPCC_OGAM_RAMA_REGION_16_17 0x031e
#define mmMPCC_OGAM4_MPCC_OGAM_RAMA_REGION_16_17_BASE_IDX 3
#define mmMPCC_OGAM4_MPCC_OGAM_RAMA_REGION_18_19 0x031f
#define mmMPCC_OGAM4_MPCC_OGAM_RAMA_REGION_18_19_BASE_IDX 3
#define mmMPCC_OGAM4_MPCC_OGAM_RAMA_REGION_20_21 0x0320
#define mmMPCC_OGAM4_MPCC_OGAM_RAMA_REGION_20_21_BASE_IDX 3
#define mmMPCC_OGAM4_MPCC_OGAM_RAMA_REGION_22_23 0x0321
#define mmMPCC_OGAM4_MPCC_OGAM_RAMA_REGION_22_23_BASE_IDX 3
#define mmMPCC_OGAM4_MPCC_OGAM_RAMA_REGION_24_25 0x0322
#define mmMPCC_OGAM4_MPCC_OGAM_RAMA_REGION_24_25_BASE_IDX 3
#define mmMPCC_OGAM4_MPCC_OGAM_RAMA_REGION_26_27 0x0323
#define mmMPCC_OGAM4_MPCC_OGAM_RAMA_REGION_26_27_BASE_IDX 3
#define mmMPCC_OGAM4_MPCC_OGAM_RAMA_REGION_28_29 0x0324
#define mmMPCC_OGAM4_MPCC_OGAM_RAMA_REGION_28_29_BASE_IDX 3
#define mmMPCC_OGAM4_MPCC_OGAM_RAMA_REGION_30_31 0x0325
#define mmMPCC_OGAM4_MPCC_OGAM_RAMA_REGION_30_31_BASE_IDX 3
#define mmMPCC_OGAM4_MPCC_OGAM_RAMA_REGION_32_33 0x0326
#define mmMPCC_OGAM4_MPCC_OGAM_RAMA_REGION_32_33_BASE_IDX 3
#define mmMPCC_OGAM4_MPCC_OGAM_RAMB_START_CNTL_B 0x0327
#define mmMPCC_OGAM4_MPCC_OGAM_RAMB_START_CNTL_B_BASE_IDX 3
#define mmMPCC_OGAM4_MPCC_OGAM_RAMB_START_CNTL_G 0x0328
#define mmMPCC_OGAM4_MPCC_OGAM_RAMB_START_CNTL_G_BASE_IDX 3
#define mmMPCC_OGAM4_MPCC_OGAM_RAMB_START_CNTL_R 0x0329
#define mmMPCC_OGAM4_MPCC_OGAM_RAMB_START_CNTL_R_BASE_IDX 3
#define mmMPCC_OGAM4_MPCC_OGAM_RAMB_START_SLOPE_CNTL_B 0x032a
#define mmMPCC_OGAM4_MPCC_OGAM_RAMB_START_SLOPE_CNTL_B_BASE_IDX 3
#define mmMPCC_OGAM4_MPCC_OGAM_RAMB_START_SLOPE_CNTL_G 0x032b
#define mmMPCC_OGAM4_MPCC_OGAM_RAMB_START_SLOPE_CNTL_G_BASE_IDX 3
#define mmMPCC_OGAM4_MPCC_OGAM_RAMB_START_SLOPE_CNTL_R 0x032c
#define mmMPCC_OGAM4_MPCC_OGAM_RAMB_START_SLOPE_CNTL_R_BASE_IDX 3
#define mmMPCC_OGAM4_MPCC_OGAM_RAMB_START_BASE_CNTL_B 0x032d
#define mmMPCC_OGAM4_MPCC_OGAM_RAMB_START_BASE_CNTL_B_BASE_IDX 3
#define mmMPCC_OGAM4_MPCC_OGAM_RAMB_START_BASE_CNTL_G 0x032e
#define mmMPCC_OGAM4_MPCC_OGAM_RAMB_START_BASE_CNTL_G_BASE_IDX 3
#define mmMPCC_OGAM4_MPCC_OGAM_RAMB_START_BASE_CNTL_R 0x032f
#define mmMPCC_OGAM4_MPCC_OGAM_RAMB_START_BASE_CNTL_R_BASE_IDX 3
#define mmMPCC_OGAM4_MPCC_OGAM_RAMB_END_CNTL1_B 0x0330
#define mmMPCC_OGAM4_MPCC_OGAM_RAMB_END_CNTL1_B_BASE_IDX 3
#define mmMPCC_OGAM4_MPCC_OGAM_RAMB_END_CNTL2_B 0x0331
#define mmMPCC_OGAM4_MPCC_OGAM_RAMB_END_CNTL2_B_BASE_IDX 3
#define mmMPCC_OGAM4_MPCC_OGAM_RAMB_END_CNTL1_G 0x0332
#define mmMPCC_OGAM4_MPCC_OGAM_RAMB_END_CNTL1_G_BASE_IDX 3
#define mmMPCC_OGAM4_MPCC_OGAM_RAMB_END_CNTL2_G 0x0333
#define mmMPCC_OGAM4_MPCC_OGAM_RAMB_END_CNTL2_G_BASE_IDX 3
#define mmMPCC_OGAM4_MPCC_OGAM_RAMB_END_CNTL1_R 0x0334
#define mmMPCC_OGAM4_MPCC_OGAM_RAMB_END_CNTL1_R_BASE_IDX 3
#define mmMPCC_OGAM4_MPCC_OGAM_RAMB_END_CNTL2_R 0x0335
#define mmMPCC_OGAM4_MPCC_OGAM_RAMB_END_CNTL2_R_BASE_IDX 3
#define mmMPCC_OGAM4_MPCC_OGAM_RAMB_OFFSET_B 0x0336
#define mmMPCC_OGAM4_MPCC_OGAM_RAMB_OFFSET_B_BASE_IDX 3
#define mmMPCC_OGAM4_MPCC_OGAM_RAMB_OFFSET_G 0x0337
#define mmMPCC_OGAM4_MPCC_OGAM_RAMB_OFFSET_G_BASE_IDX 3
#define mmMPCC_OGAM4_MPCC_OGAM_RAMB_OFFSET_R 0x0338
#define mmMPCC_OGAM4_MPCC_OGAM_RAMB_OFFSET_R_BASE_IDX 3
#define mmMPCC_OGAM4_MPCC_OGAM_RAMB_REGION_0_1 0x0339
#define mmMPCC_OGAM4_MPCC_OGAM_RAMB_REGION_0_1_BASE_IDX 3
#define mmMPCC_OGAM4_MPCC_OGAM_RAMB_REGION_2_3 0x033a
#define mmMPCC_OGAM4_MPCC_OGAM_RAMB_REGION_2_3_BASE_IDX 3
#define mmMPCC_OGAM4_MPCC_OGAM_RAMB_REGION_4_5 0x033b
#define mmMPCC_OGAM4_MPCC_OGAM_RAMB_REGION_4_5_BASE_IDX 3
#define mmMPCC_OGAM4_MPCC_OGAM_RAMB_REGION_6_7 0x033c
#define mmMPCC_OGAM4_MPCC_OGAM_RAMB_REGION_6_7_BASE_IDX 3
#define mmMPCC_OGAM4_MPCC_OGAM_RAMB_REGION_8_9 0x033d
#define mmMPCC_OGAM4_MPCC_OGAM_RAMB_REGION_8_9_BASE_IDX 3
#define mmMPCC_OGAM4_MPCC_OGAM_RAMB_REGION_10_11 0x033e
#define mmMPCC_OGAM4_MPCC_OGAM_RAMB_REGION_10_11_BASE_IDX 3
#define mmMPCC_OGAM4_MPCC_OGAM_RAMB_REGION_12_13 0x033f
#define mmMPCC_OGAM4_MPCC_OGAM_RAMB_REGION_12_13_BASE_IDX 3
#define mmMPCC_OGAM4_MPCC_OGAM_RAMB_REGION_14_15 0x0340
#define mmMPCC_OGAM4_MPCC_OGAM_RAMB_REGION_14_15_BASE_IDX 3
#define mmMPCC_OGAM4_MPCC_OGAM_RAMB_REGION_16_17 0x0341
#define mmMPCC_OGAM4_MPCC_OGAM_RAMB_REGION_16_17_BASE_IDX 3
#define mmMPCC_OGAM4_MPCC_OGAM_RAMB_REGION_18_19 0x0342
#define mmMPCC_OGAM4_MPCC_OGAM_RAMB_REGION_18_19_BASE_IDX 3
#define mmMPCC_OGAM4_MPCC_OGAM_RAMB_REGION_20_21 0x0343
#define mmMPCC_OGAM4_MPCC_OGAM_RAMB_REGION_20_21_BASE_IDX 3
#define mmMPCC_OGAM4_MPCC_OGAM_RAMB_REGION_22_23 0x0344
#define mmMPCC_OGAM4_MPCC_OGAM_RAMB_REGION_22_23_BASE_IDX 3
#define mmMPCC_OGAM4_MPCC_OGAM_RAMB_REGION_24_25 0x0345
#define mmMPCC_OGAM4_MPCC_OGAM_RAMB_REGION_24_25_BASE_IDX 3
#define mmMPCC_OGAM4_MPCC_OGAM_RAMB_REGION_26_27 0x0346
#define mmMPCC_OGAM4_MPCC_OGAM_RAMB_REGION_26_27_BASE_IDX 3
#define mmMPCC_OGAM4_MPCC_OGAM_RAMB_REGION_28_29 0x0347
#define mmMPCC_OGAM4_MPCC_OGAM_RAMB_REGION_28_29_BASE_IDX 3
#define mmMPCC_OGAM4_MPCC_OGAM_RAMB_REGION_30_31 0x0348
#define mmMPCC_OGAM4_MPCC_OGAM_RAMB_REGION_30_31_BASE_IDX 3
#define mmMPCC_OGAM4_MPCC_OGAM_RAMB_REGION_32_33 0x0349
#define mmMPCC_OGAM4_MPCC_OGAM_RAMB_REGION_32_33_BASE_IDX 3
#define mmMPCC_OGAM4_MPCC_GAMUT_REMAP_COEF_FORMAT 0x034a
#define mmMPCC_OGAM4_MPCC_GAMUT_REMAP_COEF_FORMAT_BASE_IDX 3
#define mmMPCC_OGAM4_MPCC_GAMUT_REMAP_MODE 0x034b
#define mmMPCC_OGAM4_MPCC_GAMUT_REMAP_MODE_BASE_IDX 3
#define mmMPCC_OGAM4_MPC_GAMUT_REMAP_C11_C12_A 0x034c
#define mmMPCC_OGAM4_MPC_GAMUT_REMAP_C11_C12_A_BASE_IDX 3
#define mmMPCC_OGAM4_MPC_GAMUT_REMAP_C13_C14_A 0x034d
#define mmMPCC_OGAM4_MPC_GAMUT_REMAP_C13_C14_A_BASE_IDX 3
#define mmMPCC_OGAM4_MPC_GAMUT_REMAP_C21_C22_A 0x034e
#define mmMPCC_OGAM4_MPC_GAMUT_REMAP_C21_C22_A_BASE_IDX 3
#define mmMPCC_OGAM4_MPC_GAMUT_REMAP_C23_C24_A 0x034f
#define mmMPCC_OGAM4_MPC_GAMUT_REMAP_C23_C24_A_BASE_IDX 3
#define mmMPCC_OGAM4_MPC_GAMUT_REMAP_C31_C32_A 0x0350
#define mmMPCC_OGAM4_MPC_GAMUT_REMAP_C31_C32_A_BASE_IDX 3
#define mmMPCC_OGAM4_MPC_GAMUT_REMAP_C33_C34_A 0x0351
#define mmMPCC_OGAM4_MPC_GAMUT_REMAP_C33_C34_A_BASE_IDX 3
#define mmMPCC_OGAM4_MPC_GAMUT_REMAP_C11_C12_B 0x0352
#define mmMPCC_OGAM4_MPC_GAMUT_REMAP_C11_C12_B_BASE_IDX 3
#define mmMPCC_OGAM4_MPC_GAMUT_REMAP_C13_C14_B 0x0353
#define mmMPCC_OGAM4_MPC_GAMUT_REMAP_C13_C14_B_BASE_IDX 3
#define mmMPCC_OGAM4_MPC_GAMUT_REMAP_C21_C22_B 0x0354
#define mmMPCC_OGAM4_MPC_GAMUT_REMAP_C21_C22_B_BASE_IDX 3
#define mmMPCC_OGAM4_MPC_GAMUT_REMAP_C23_C24_B 0x0355
#define mmMPCC_OGAM4_MPC_GAMUT_REMAP_C23_C24_B_BASE_IDX 3
#define mmMPCC_OGAM4_MPC_GAMUT_REMAP_C31_C32_B 0x0356
#define mmMPCC_OGAM4_MPC_GAMUT_REMAP_C31_C32_B_BASE_IDX 3
#define mmMPCC_OGAM4_MPC_GAMUT_REMAP_C33_C34_B 0x0357
#define mmMPCC_OGAM4_MPC_GAMUT_REMAP_C33_C34_B_BASE_IDX 3
// addressBlock: dce_dc_mpc_mpc_cfg_dispdec
// base address: 0x0
#define mmMPC_CLOCK_CONTROL 0x0500
#define mmMPC_CLOCK_CONTROL_BASE_IDX 3
#define mmMPC_SOFT_RESET 0x0501
#define mmMPC_SOFT_RESET_BASE_IDX 3
#define mmMPC_CRC_CTRL 0x0502
#define mmMPC_CRC_CTRL_BASE_IDX 3
#define mmMPC_CRC_SEL_CONTROL 0x0503
#define mmMPC_CRC_SEL_CONTROL_BASE_IDX 3
#define mmMPC_CRC_RESULT_AR 0x0504
#define mmMPC_CRC_RESULT_AR_BASE_IDX 3
#define mmMPC_CRC_RESULT_GB 0x0505
#define mmMPC_CRC_RESULT_GB_BASE_IDX 3
#define mmMPC_CRC_RESULT_C 0x0506
#define mmMPC_CRC_RESULT_C_BASE_IDX 3
#define mmMPC_PERFMON_EVENT_CTRL 0x0509
#define mmMPC_PERFMON_EVENT_CTRL_BASE_IDX 3
#define mmMPC_BYPASS_BG_AR 0x050a
#define mmMPC_BYPASS_BG_AR_BASE_IDX 3
#define mmMPC_BYPASS_BG_GB 0x050b
#define mmMPC_BYPASS_BG_GB_BASE_IDX 3
#define mmMPC_HOST_READ_CONTROL 0x050c
#define mmMPC_HOST_READ_CONTROL_BASE_IDX 3
#define mmMPC_DPP_PENDING_STATUS 0x050d
#define mmMPC_DPP_PENDING_STATUS_BASE_IDX 3
#define mmMPC_PENDING_STATUS_MISC 0x050e
#define mmMPC_PENDING_STATUS_MISC_BASE_IDX 3
#define mmADR_CFG_CUR_VUPDATE_LOCK_SET0 0x050f
#define mmADR_CFG_CUR_VUPDATE_LOCK_SET0_BASE_IDX 3
#define mmADR_CFG_VUPDATE_LOCK_SET0 0x0510
#define mmADR_CFG_VUPDATE_LOCK_SET0_BASE_IDX 3
#define mmADR_VUPDATE_LOCK_SET0 0x0511
#define mmADR_VUPDATE_LOCK_SET0_BASE_IDX 3
#define mmCFG_VUPDATE_LOCK_SET0 0x0512
#define mmCFG_VUPDATE_LOCK_SET0_BASE_IDX 3
#define mmCUR_VUPDATE_LOCK_SET0 0x0513
#define mmCUR_VUPDATE_LOCK_SET0_BASE_IDX 3
#define mmADR_CFG_CUR_VUPDATE_LOCK_SET1 0x0514
#define mmADR_CFG_CUR_VUPDATE_LOCK_SET1_BASE_IDX 3
#define mmADR_CFG_VUPDATE_LOCK_SET1 0x0515
#define mmADR_CFG_VUPDATE_LOCK_SET1_BASE_IDX 3
#define mmADR_VUPDATE_LOCK_SET1 0x0516
#define mmADR_VUPDATE_LOCK_SET1_BASE_IDX 3
#define mmCFG_VUPDATE_LOCK_SET1 0x0517
#define mmCFG_VUPDATE_LOCK_SET1_BASE_IDX 3
#define mmCUR_VUPDATE_LOCK_SET1 0x0518
#define mmCUR_VUPDATE_LOCK_SET1_BASE_IDX 3
#define mmADR_CFG_CUR_VUPDATE_LOCK_SET2 0x0519
#define mmADR_CFG_CUR_VUPDATE_LOCK_SET2_BASE_IDX 3
#define mmADR_CFG_VUPDATE_LOCK_SET2 0x051a
#define mmADR_CFG_VUPDATE_LOCK_SET2_BASE_IDX 3
#define mmADR_VUPDATE_LOCK_SET2 0x051b
#define mmADR_VUPDATE_LOCK_SET2_BASE_IDX 3
#define mmCFG_VUPDATE_LOCK_SET2 0x051c
#define mmCFG_VUPDATE_LOCK_SET2_BASE_IDX 3
#define mmCUR_VUPDATE_LOCK_SET2 0x051d
#define mmCUR_VUPDATE_LOCK_SET2_BASE_IDX 3
#define mmADR_CFG_CUR_VUPDATE_LOCK_SET3 0x051e
#define mmADR_CFG_CUR_VUPDATE_LOCK_SET3_BASE_IDX 3
#define mmADR_CFG_VUPDATE_LOCK_SET3 0x051f
#define mmADR_CFG_VUPDATE_LOCK_SET3_BASE_IDX 3
#define mmADR_VUPDATE_LOCK_SET3 0x0520
#define mmADR_VUPDATE_LOCK_SET3_BASE_IDX 3
#define mmCFG_VUPDATE_LOCK_SET3 0x0521
#define mmCFG_VUPDATE_LOCK_SET3_BASE_IDX 3
#define mmCUR_VUPDATE_LOCK_SET3 0x0522
#define mmCUR_VUPDATE_LOCK_SET3_BASE_IDX 3
#define mmADR_CFG_CUR_VUPDATE_LOCK_SET4 0x0523
#define mmADR_CFG_CUR_VUPDATE_LOCK_SET4_BASE_IDX 3
#define mmADR_CFG_VUPDATE_LOCK_SET4 0x0524
#define mmADR_CFG_VUPDATE_LOCK_SET4_BASE_IDX 3
#define mmADR_VUPDATE_LOCK_SET4 0x0525
#define mmADR_VUPDATE_LOCK_SET4_BASE_IDX 3
#define mmCFG_VUPDATE_LOCK_SET4 0x0526
#define mmCFG_VUPDATE_LOCK_SET4_BASE_IDX 3
#define mmCUR_VUPDATE_LOCK_SET4 0x0527
#define mmCUR_VUPDATE_LOCK_SET4_BASE_IDX 3
#define mmMPC_DWB0_MUX 0x055c
#define mmMPC_DWB0_MUX_BASE_IDX 3
// addressBlock: dce_dc_mpc_mpc_ocsc_dispdec
// base address: 0x0
#define mmMPC_OUT0_MUX 0x0580
#define mmMPC_OUT0_MUX_BASE_IDX 3
#define mmMPC_OUT0_DENORM_CONTROL 0x0581
#define mmMPC_OUT0_DENORM_CONTROL_BASE_IDX 3
#define mmMPC_OUT0_DENORM_CLAMP_G_Y 0x0582
#define mmMPC_OUT0_DENORM_CLAMP_G_Y_BASE_IDX 3
#define mmMPC_OUT0_DENORM_CLAMP_B_CB 0x0583
#define mmMPC_OUT0_DENORM_CLAMP_B_CB_BASE_IDX 3
#define mmMPC_OUT1_MUX 0x0584
#define mmMPC_OUT1_MUX_BASE_IDX 3
#define mmMPC_OUT1_DENORM_CONTROL 0x0585
#define mmMPC_OUT1_DENORM_CONTROL_BASE_IDX 3
#define mmMPC_OUT1_DENORM_CLAMP_G_Y 0x0586
#define mmMPC_OUT1_DENORM_CLAMP_G_Y_BASE_IDX 3
#define mmMPC_OUT1_DENORM_CLAMP_B_CB 0x0587
#define mmMPC_OUT1_DENORM_CLAMP_B_CB_BASE_IDX 3
#define mmMPC_OUT2_MUX 0x0588
#define mmMPC_OUT2_MUX_BASE_IDX 3
#define mmMPC_OUT2_DENORM_CONTROL 0x0589
#define mmMPC_OUT2_DENORM_CONTROL_BASE_IDX 3
#define mmMPC_OUT2_DENORM_CLAMP_G_Y 0x058a
#define mmMPC_OUT2_DENORM_CLAMP_G_Y_BASE_IDX 3
#define mmMPC_OUT2_DENORM_CLAMP_B_CB 0x058b
#define mmMPC_OUT2_DENORM_CLAMP_B_CB_BASE_IDX 3
#define mmMPC_OUT3_MUX 0x058c
#define mmMPC_OUT3_MUX_BASE_IDX 3
#define mmMPC_OUT3_DENORM_CONTROL 0x058d
#define mmMPC_OUT3_DENORM_CONTROL_BASE_IDX 3
#define mmMPC_OUT3_DENORM_CLAMP_G_Y 0x058e
#define mmMPC_OUT3_DENORM_CLAMP_G_Y_BASE_IDX 3
#define mmMPC_OUT3_DENORM_CLAMP_B_CB 0x058f
#define mmMPC_OUT3_DENORM_CLAMP_B_CB_BASE_IDX 3
#define mmMPC_OUT4_MUX 0x0590
#define mmMPC_OUT4_MUX_BASE_IDX 3
#define mmMPC_OUT4_DENORM_CONTROL 0x0591
#define mmMPC_OUT4_DENORM_CONTROL_BASE_IDX 3
#define mmMPC_OUT4_DENORM_CLAMP_G_Y 0x0592
#define mmMPC_OUT4_DENORM_CLAMP_G_Y_BASE_IDX 3
#define mmMPC_OUT4_DENORM_CLAMP_B_CB 0x0593
#define mmMPC_OUT4_DENORM_CLAMP_B_CB_BASE_IDX 3
#define mmMPC_OUT_CSC_COEF_FORMAT 0x0594
#define mmMPC_OUT_CSC_COEF_FORMAT_BASE_IDX 3
#define mmMPC_OUT0_CSC_MODE 0x0595
#define mmMPC_OUT0_CSC_MODE_BASE_IDX 3
#define mmMPC_OUT0_CSC_C11_C12_A 0x0596
#define mmMPC_OUT0_CSC_C11_C12_A_BASE_IDX 3
#define mmMPC_OUT0_CSC_C13_C14_A 0x0597
#define mmMPC_OUT0_CSC_C13_C14_A_BASE_IDX 3
#define mmMPC_OUT0_CSC_C21_C22_A 0x0598
#define mmMPC_OUT0_CSC_C21_C22_A_BASE_IDX 3
#define mmMPC_OUT0_CSC_C23_C24_A 0x0599
#define mmMPC_OUT0_CSC_C23_C24_A_BASE_IDX 3
#define mmMPC_OUT0_CSC_C31_C32_A 0x059a
#define mmMPC_OUT0_CSC_C31_C32_A_BASE_IDX 3
#define mmMPC_OUT0_CSC_C33_C34_A 0x059b
#define mmMPC_OUT0_CSC_C33_C34_A_BASE_IDX 3
#define mmMPC_OUT0_CSC_C11_C12_B 0x059c
#define mmMPC_OUT0_CSC_C11_C12_B_BASE_IDX 3
#define mmMPC_OUT0_CSC_C13_C14_B 0x059d
#define mmMPC_OUT0_CSC_C13_C14_B_BASE_IDX 3
#define mmMPC_OUT0_CSC_C21_C22_B 0x059e
#define mmMPC_OUT0_CSC_C21_C22_B_BASE_IDX 3
#define mmMPC_OUT0_CSC_C23_C24_B 0x059f
#define mmMPC_OUT0_CSC_C23_C24_B_BASE_IDX 3
#define mmMPC_OUT0_CSC_C31_C32_B 0x05a0
#define mmMPC_OUT0_CSC_C31_C32_B_BASE_IDX 3
#define mmMPC_OUT0_CSC_C33_C34_B 0x05a1
#define mmMPC_OUT0_CSC_C33_C34_B_BASE_IDX 3
#define mmMPC_OUT1_CSC_MODE 0x05a2
#define mmMPC_OUT1_CSC_MODE_BASE_IDX 3
#define mmMPC_OUT1_CSC_C11_C12_A 0x05a3
#define mmMPC_OUT1_CSC_C11_C12_A_BASE_IDX 3
#define mmMPC_OUT1_CSC_C13_C14_A 0x05a4
#define mmMPC_OUT1_CSC_C13_C14_A_BASE_IDX 3
#define mmMPC_OUT1_CSC_C21_C22_A 0x05a5
#define mmMPC_OUT1_CSC_C21_C22_A_BASE_IDX 3
#define mmMPC_OUT1_CSC_C23_C24_A 0x05a6
#define mmMPC_OUT1_CSC_C23_C24_A_BASE_IDX 3
#define mmMPC_OUT1_CSC_C31_C32_A 0x05a7
#define mmMPC_OUT1_CSC_C31_C32_A_BASE_IDX 3
#define mmMPC_OUT1_CSC_C33_C34_A 0x05a8
#define mmMPC_OUT1_CSC_C33_C34_A_BASE_IDX 3
#define mmMPC_OUT1_CSC_C11_C12_B 0x05a9
#define mmMPC_OUT1_CSC_C11_C12_B_BASE_IDX 3
#define mmMPC_OUT1_CSC_C13_C14_B 0x05aa
#define mmMPC_OUT1_CSC_C13_C14_B_BASE_IDX 3
#define mmMPC_OUT1_CSC_C21_C22_B 0x05ab
#define mmMPC_OUT1_CSC_C21_C22_B_BASE_IDX 3
#define mmMPC_OUT1_CSC_C23_C24_B 0x05ac
#define mmMPC_OUT1_CSC_C23_C24_B_BASE_IDX 3
#define mmMPC_OUT1_CSC_C31_C32_B 0x05ad
#define mmMPC_OUT1_CSC_C31_C32_B_BASE_IDX 3
#define mmMPC_OUT1_CSC_C33_C34_B 0x05ae
#define mmMPC_OUT1_CSC_C33_C34_B_BASE_IDX 3
#define mmMPC_OUT2_CSC_MODE 0x05af
#define mmMPC_OUT2_CSC_MODE_BASE_IDX 3
#define mmMPC_OUT2_CSC_C11_C12_A 0x05b0
#define mmMPC_OUT2_CSC_C11_C12_A_BASE_IDX 3
#define mmMPC_OUT2_CSC_C13_C14_A 0x05b1
#define mmMPC_OUT2_CSC_C13_C14_A_BASE_IDX 3
#define mmMPC_OUT2_CSC_C21_C22_A 0x05b2
#define mmMPC_OUT2_CSC_C21_C22_A_BASE_IDX 3
#define mmMPC_OUT2_CSC_C23_C24_A 0x05b3
#define mmMPC_OUT2_CSC_C23_C24_A_BASE_IDX 3
#define mmMPC_OUT2_CSC_C31_C32_A 0x05b4
#define mmMPC_OUT2_CSC_C31_C32_A_BASE_IDX 3
#define mmMPC_OUT2_CSC_C33_C34_A 0x05b5
#define mmMPC_OUT2_CSC_C33_C34_A_BASE_IDX 3
#define mmMPC_OUT2_CSC_C11_C12_B 0x05b6
#define mmMPC_OUT2_CSC_C11_C12_B_BASE_IDX 3
#define mmMPC_OUT2_CSC_C13_C14_B 0x05b7
#define mmMPC_OUT2_CSC_C13_C14_B_BASE_IDX 3
#define mmMPC_OUT2_CSC_C21_C22_B 0x05b8
#define mmMPC_OUT2_CSC_C21_C22_B_BASE_IDX 3
#define mmMPC_OUT2_CSC_C23_C24_B 0x05b9
#define mmMPC_OUT2_CSC_C23_C24_B_BASE_IDX 3
#define mmMPC_OUT2_CSC_C31_C32_B 0x05ba
#define mmMPC_OUT2_CSC_C31_C32_B_BASE_IDX 3
#define mmMPC_OUT2_CSC_C33_C34_B 0x05bb
#define mmMPC_OUT2_CSC_C33_C34_B_BASE_IDX 3
#define mmMPC_OUT3_CSC_MODE 0x05bc
#define mmMPC_OUT3_CSC_MODE_BASE_IDX 3
#define mmMPC_OUT3_CSC_C11_C12_A 0x05bd
#define mmMPC_OUT3_CSC_C11_C12_A_BASE_IDX 3
#define mmMPC_OUT3_CSC_C13_C14_A 0x05be
#define mmMPC_OUT3_CSC_C13_C14_A_BASE_IDX 3
#define mmMPC_OUT3_CSC_C21_C22_A 0x05bf
#define mmMPC_OUT3_CSC_C21_C22_A_BASE_IDX 3
#define mmMPC_OUT3_CSC_C23_C24_A 0x05c0
#define mmMPC_OUT3_CSC_C23_C24_A_BASE_IDX 3
#define mmMPC_OUT3_CSC_C31_C32_A 0x05c1
#define mmMPC_OUT3_CSC_C31_C32_A_BASE_IDX 3
#define mmMPC_OUT3_CSC_C33_C34_A 0x05c2
#define mmMPC_OUT3_CSC_C33_C34_A_BASE_IDX 3
#define mmMPC_OUT3_CSC_C11_C12_B 0x05c3
#define mmMPC_OUT3_CSC_C11_C12_B_BASE_IDX 3
#define mmMPC_OUT3_CSC_C13_C14_B 0x05c4
#define mmMPC_OUT3_CSC_C13_C14_B_BASE_IDX 3
#define mmMPC_OUT3_CSC_C21_C22_B 0x05c5
#define mmMPC_OUT3_CSC_C21_C22_B_BASE_IDX 3
#define mmMPC_OUT3_CSC_C23_C24_B 0x05c6
#define mmMPC_OUT3_CSC_C23_C24_B_BASE_IDX 3
#define mmMPC_OUT3_CSC_C31_C32_B 0x05c7
#define mmMPC_OUT3_CSC_C31_C32_B_BASE_IDX 3
#define mmMPC_OUT3_CSC_C33_C34_B 0x05c8
#define mmMPC_OUT3_CSC_C33_C34_B_BASE_IDX 3
#define mmMPC_OUT4_CSC_MODE 0x05c9
#define mmMPC_OUT4_CSC_MODE_BASE_IDX 3
#define mmMPC_OUT4_CSC_C11_C12_A 0x05ca
#define mmMPC_OUT4_CSC_C11_C12_A_BASE_IDX 3
#define mmMPC_OUT4_CSC_C13_C14_A 0x05cb
#define mmMPC_OUT4_CSC_C13_C14_A_BASE_IDX 3
#define mmMPC_OUT4_CSC_C21_C22_A 0x05cc
#define mmMPC_OUT4_CSC_C21_C22_A_BASE_IDX 3
#define mmMPC_OUT4_CSC_C23_C24_A 0x05cd
#define mmMPC_OUT4_CSC_C23_C24_A_BASE_IDX 3
#define mmMPC_OUT4_CSC_C31_C32_A 0x05ce
#define mmMPC_OUT4_CSC_C31_C32_A_BASE_IDX 3
#define mmMPC_OUT4_CSC_C33_C34_A 0x05cf
#define mmMPC_OUT4_CSC_C33_C34_A_BASE_IDX 3
#define mmMPC_OUT4_CSC_C11_C12_B 0x05d0
#define mmMPC_OUT4_CSC_C11_C12_B_BASE_IDX 3
#define mmMPC_OUT4_CSC_C13_C14_B 0x05d1
#define mmMPC_OUT4_CSC_C13_C14_B_BASE_IDX 3
#define mmMPC_OUT4_CSC_C21_C22_B 0x05d2
#define mmMPC_OUT4_CSC_C21_C22_B_BASE_IDX 3
#define mmMPC_OUT4_CSC_C23_C24_B 0x05d3
#define mmMPC_OUT4_CSC_C23_C24_B_BASE_IDX 3
#define mmMPC_OUT4_CSC_C31_C32_B 0x05d4
#define mmMPC_OUT4_CSC_C31_C32_B_BASE_IDX 3
#define mmMPC_OUT4_CSC_C33_C34_B 0x05d5
#define mmMPC_OUT4_CSC_C33_C34_B_BASE_IDX 3
// addressBlock: dce_dc_mpc_mpc_rmu_dispdec
// base address: 0x0
#define mmMPC_RMU_CONTROL 0x0680
#define mmMPC_RMU_CONTROL_BASE_IDX 3
#define mmMPC_RMU_MEM_PWR_CTRL 0x0681
#define mmMPC_RMU_MEM_PWR_CTRL_BASE_IDX 3
#define mmMPC_RMU0_SHAPER_CONTROL 0x0682
#define mmMPC_RMU0_SHAPER_CONTROL_BASE_IDX 3
#define mmMPC_RMU0_SHAPER_OFFSET_R 0x0683
#define mmMPC_RMU0_SHAPER_OFFSET_R_BASE_IDX 3
#define mmMPC_RMU0_SHAPER_OFFSET_G 0x0684
#define mmMPC_RMU0_SHAPER_OFFSET_G_BASE_IDX 3
#define mmMPC_RMU0_SHAPER_OFFSET_B 0x0685
#define mmMPC_RMU0_SHAPER_OFFSET_B_BASE_IDX 3
#define mmMPC_RMU0_SHAPER_SCALE_R 0x0686
#define mmMPC_RMU0_SHAPER_SCALE_R_BASE_IDX 3
#define mmMPC_RMU0_SHAPER_SCALE_G_B 0x0687
#define mmMPC_RMU0_SHAPER_SCALE_G_B_BASE_IDX 3
#define mmMPC_RMU0_SHAPER_LUT_INDEX 0x0688
#define mmMPC_RMU0_SHAPER_LUT_INDEX_BASE_IDX 3
#define mmMPC_RMU0_SHAPER_LUT_DATA 0x0689
#define mmMPC_RMU0_SHAPER_LUT_DATA_BASE_IDX 3
#define mmMPC_RMU0_SHAPER_LUT_WRITE_EN_MASK 0x068a
#define mmMPC_RMU0_SHAPER_LUT_WRITE_EN_MASK_BASE_IDX 3
#define mmMPC_RMU0_SHAPER_RAMA_START_CNTL_B 0x068b
#define mmMPC_RMU0_SHAPER_RAMA_START_CNTL_B_BASE_IDX 3
#define mmMPC_RMU0_SHAPER_RAMA_START_CNTL_G 0x068c
#define mmMPC_RMU0_SHAPER_RAMA_START_CNTL_G_BASE_IDX 3
#define mmMPC_RMU0_SHAPER_RAMA_START_CNTL_R 0x068d
#define mmMPC_RMU0_SHAPER_RAMA_START_CNTL_R_BASE_IDX 3
#define mmMPC_RMU0_SHAPER_RAMA_END_CNTL_B 0x068e
#define mmMPC_RMU0_SHAPER_RAMA_END_CNTL_B_BASE_IDX 3
#define mmMPC_RMU0_SHAPER_RAMA_END_CNTL_G 0x068f
#define mmMPC_RMU0_SHAPER_RAMA_END_CNTL_G_BASE_IDX 3
#define mmMPC_RMU0_SHAPER_RAMA_END_CNTL_R 0x0690
#define mmMPC_RMU0_SHAPER_RAMA_END_CNTL_R_BASE_IDX 3
#define mmMPC_RMU0_SHAPER_RAMA_REGION_0_1 0x0691
#define mmMPC_RMU0_SHAPER_RAMA_REGION_0_1_BASE_IDX 3
#define mmMPC_RMU0_SHAPER_RAMA_REGION_2_3 0x0692
#define mmMPC_RMU0_SHAPER_RAMA_REGION_2_3_BASE_IDX 3
#define mmMPC_RMU0_SHAPER_RAMA_REGION_4_5 0x0693
#define mmMPC_RMU0_SHAPER_RAMA_REGION_4_5_BASE_IDX 3
#define mmMPC_RMU0_SHAPER_RAMA_REGION_6_7 0x0694
#define mmMPC_RMU0_SHAPER_RAMA_REGION_6_7_BASE_IDX 3
#define mmMPC_RMU0_SHAPER_RAMA_REGION_8_9 0x0695
#define mmMPC_RMU0_SHAPER_RAMA_REGION_8_9_BASE_IDX 3
#define mmMPC_RMU0_SHAPER_RAMA_REGION_10_11 0x0696
#define mmMPC_RMU0_SHAPER_RAMA_REGION_10_11_BASE_IDX 3
#define mmMPC_RMU0_SHAPER_RAMA_REGION_12_13 0x0697
#define mmMPC_RMU0_SHAPER_RAMA_REGION_12_13_BASE_IDX 3
#define mmMPC_RMU0_SHAPER_RAMA_REGION_14_15 0x0698
#define mmMPC_RMU0_SHAPER_RAMA_REGION_14_15_BASE_IDX 3
#define mmMPC_RMU0_SHAPER_RAMA_REGION_16_17 0x0699
#define mmMPC_RMU0_SHAPER_RAMA_REGION_16_17_BASE_IDX 3
#define mmMPC_RMU0_SHAPER_RAMA_REGION_18_19 0x069a
#define mmMPC_RMU0_SHAPER_RAMA_REGION_18_19_BASE_IDX 3
#define mmMPC_RMU0_SHAPER_RAMA_REGION_20_21 0x069b
#define mmMPC_RMU0_SHAPER_RAMA_REGION_20_21_BASE_IDX 3
#define mmMPC_RMU0_SHAPER_RAMA_REGION_22_23 0x069c
#define mmMPC_RMU0_SHAPER_RAMA_REGION_22_23_BASE_IDX 3
#define mmMPC_RMU0_SHAPER_RAMA_REGION_24_25 0x069d
#define mmMPC_RMU0_SHAPER_RAMA_REGION_24_25_BASE_IDX 3
#define mmMPC_RMU0_SHAPER_RAMA_REGION_26_27 0x069e
#define mmMPC_RMU0_SHAPER_RAMA_REGION_26_27_BASE_IDX 3
#define mmMPC_RMU0_SHAPER_RAMA_REGION_28_29 0x069f
#define mmMPC_RMU0_SHAPER_RAMA_REGION_28_29_BASE_IDX 3
#define mmMPC_RMU0_SHAPER_RAMA_REGION_30_31 0x06a0
#define mmMPC_RMU0_SHAPER_RAMA_REGION_30_31_BASE_IDX 3
#define mmMPC_RMU0_SHAPER_RAMA_REGION_32_33 0x06a1
#define mmMPC_RMU0_SHAPER_RAMA_REGION_32_33_BASE_IDX 3
#define mmMPC_RMU0_SHAPER_RAMB_START_CNTL_B 0x06a2
#define mmMPC_RMU0_SHAPER_RAMB_START_CNTL_B_BASE_IDX 3
#define mmMPC_RMU0_SHAPER_RAMB_START_CNTL_G 0x06a3
#define mmMPC_RMU0_SHAPER_RAMB_START_CNTL_G_BASE_IDX 3
#define mmMPC_RMU0_SHAPER_RAMB_START_CNTL_R 0x06a4
#define mmMPC_RMU0_SHAPER_RAMB_START_CNTL_R_BASE_IDX 3
#define mmMPC_RMU0_SHAPER_RAMB_END_CNTL_B 0x06a5
#define mmMPC_RMU0_SHAPER_RAMB_END_CNTL_B_BASE_IDX 3
#define mmMPC_RMU0_SHAPER_RAMB_END_CNTL_G 0x06a6
#define mmMPC_RMU0_SHAPER_RAMB_END_CNTL_G_BASE_IDX 3
#define mmMPC_RMU0_SHAPER_RAMB_END_CNTL_R 0x06a7
#define mmMPC_RMU0_SHAPER_RAMB_END_CNTL_R_BASE_IDX 3
#define mmMPC_RMU0_SHAPER_RAMB_REGION_0_1 0x06a8
#define mmMPC_RMU0_SHAPER_RAMB_REGION_0_1_BASE_IDX 3
#define mmMPC_RMU0_SHAPER_RAMB_REGION_2_3 0x06a9
#define mmMPC_RMU0_SHAPER_RAMB_REGION_2_3_BASE_IDX 3
#define mmMPC_RMU0_SHAPER_RAMB_REGION_4_5 0x06aa
#define mmMPC_RMU0_SHAPER_RAMB_REGION_4_5_BASE_IDX 3
#define mmMPC_RMU0_SHAPER_RAMB_REGION_6_7 0x06ab
#define mmMPC_RMU0_SHAPER_RAMB_REGION_6_7_BASE_IDX 3
#define mmMPC_RMU0_SHAPER_RAMB_REGION_8_9 0x06ac
#define mmMPC_RMU0_SHAPER_RAMB_REGION_8_9_BASE_IDX 3
#define mmMPC_RMU0_SHAPER_RAMB_REGION_10_11 0x06ad
#define mmMPC_RMU0_SHAPER_RAMB_REGION_10_11_BASE_IDX 3
#define mmMPC_RMU0_SHAPER_RAMB_REGION_12_13 0x06ae
#define mmMPC_RMU0_SHAPER_RAMB_REGION_12_13_BASE_IDX 3
#define mmMPC_RMU0_SHAPER_RAMB_REGION_14_15 0x06af
#define mmMPC_RMU0_SHAPER_RAMB_REGION_14_15_BASE_IDX 3
#define mmMPC_RMU0_SHAPER_RAMB_REGION_16_17 0x06b0
#define mmMPC_RMU0_SHAPER_RAMB_REGION_16_17_BASE_IDX 3
#define mmMPC_RMU0_SHAPER_RAMB_REGION_18_19 0x06b1
#define mmMPC_RMU0_SHAPER_RAMB_REGION_18_19_BASE_IDX 3
#define mmMPC_RMU0_SHAPER_RAMB_REGION_20_21 0x06b2
#define mmMPC_RMU0_SHAPER_RAMB_REGION_20_21_BASE_IDX 3
#define mmMPC_RMU0_SHAPER_RAMB_REGION_22_23 0x06b3
#define mmMPC_RMU0_SHAPER_RAMB_REGION_22_23_BASE_IDX 3
#define mmMPC_RMU0_SHAPER_RAMB_REGION_24_25 0x06b4
#define mmMPC_RMU0_SHAPER_RAMB_REGION_24_25_BASE_IDX 3
#define mmMPC_RMU0_SHAPER_RAMB_REGION_26_27 0x06b5
#define mmMPC_RMU0_SHAPER_RAMB_REGION_26_27_BASE_IDX 3
#define mmMPC_RMU0_SHAPER_RAMB_REGION_28_29 0x06b6
#define mmMPC_RMU0_SHAPER_RAMB_REGION_28_29_BASE_IDX 3
#define mmMPC_RMU0_SHAPER_RAMB_REGION_30_31 0x06b7
#define mmMPC_RMU0_SHAPER_RAMB_REGION_30_31_BASE_IDX 3
#define mmMPC_RMU0_SHAPER_RAMB_REGION_32_33 0x06b8
#define mmMPC_RMU0_SHAPER_RAMB_REGION_32_33_BASE_IDX 3
#define mmMPC_RMU0_3DLUT_MODE 0x06b9
#define mmMPC_RMU0_3DLUT_MODE_BASE_IDX 3
#define mmMPC_RMU0_3DLUT_INDEX 0x06ba
#define mmMPC_RMU0_3DLUT_INDEX_BASE_IDX 3
#define mmMPC_RMU0_3DLUT_DATA 0x06bb
#define mmMPC_RMU0_3DLUT_DATA_BASE_IDX 3
#define mmMPC_RMU0_3DLUT_DATA_30BIT 0x06bc
#define mmMPC_RMU0_3DLUT_DATA_30BIT_BASE_IDX 3
#define mmMPC_RMU0_3DLUT_READ_WRITE_CONTROL 0x06bd
#define mmMPC_RMU0_3DLUT_READ_WRITE_CONTROL_BASE_IDX 3
#define mmMPC_RMU0_3DLUT_OUT_NORM_FACTOR 0x06be
#define mmMPC_RMU0_3DLUT_OUT_NORM_FACTOR_BASE_IDX 3
#define mmMPC_RMU0_3DLUT_OUT_OFFSET_R 0x06bf
#define mmMPC_RMU0_3DLUT_OUT_OFFSET_R_BASE_IDX 3
#define mmMPC_RMU0_3DLUT_OUT_OFFSET_G 0x06c0
#define mmMPC_RMU0_3DLUT_OUT_OFFSET_G_BASE_IDX 3
#define mmMPC_RMU0_3DLUT_OUT_OFFSET_B 0x06c1
#define mmMPC_RMU0_3DLUT_OUT_OFFSET_B_BASE_IDX 3
#define mmMPC_RMU1_SHAPER_CONTROL 0x06c2
#define mmMPC_RMU1_SHAPER_CONTROL_BASE_IDX 3
#define mmMPC_RMU1_SHAPER_OFFSET_R 0x06c3
#define mmMPC_RMU1_SHAPER_OFFSET_R_BASE_IDX 3
#define mmMPC_RMU1_SHAPER_OFFSET_G 0x06c4
#define mmMPC_RMU1_SHAPER_OFFSET_G_BASE_IDX 3
#define mmMPC_RMU1_SHAPER_OFFSET_B 0x06c5
#define mmMPC_RMU1_SHAPER_OFFSET_B_BASE_IDX 3
#define mmMPC_RMU1_SHAPER_SCALE_R 0x06c6
#define mmMPC_RMU1_SHAPER_SCALE_R_BASE_IDX 3
#define mmMPC_RMU1_SHAPER_SCALE_G_B 0x06c7
#define mmMPC_RMU1_SHAPER_SCALE_G_B_BASE_IDX 3
#define mmMPC_RMU1_SHAPER_LUT_INDEX 0x06c8
#define mmMPC_RMU1_SHAPER_LUT_INDEX_BASE_IDX 3
#define mmMPC_RMU1_SHAPER_LUT_DATA 0x06c9
#define mmMPC_RMU1_SHAPER_LUT_DATA_BASE_IDX 3
#define mmMPC_RMU1_SHAPER_LUT_WRITE_EN_MASK 0x06ca
#define mmMPC_RMU1_SHAPER_LUT_WRITE_EN_MASK_BASE_IDX 3
#define mmMPC_RMU1_SHAPER_RAMA_START_CNTL_B 0x06cb
#define mmMPC_RMU1_SHAPER_RAMA_START_CNTL_B_BASE_IDX 3
#define mmMPC_RMU1_SHAPER_RAMA_START_CNTL_G 0x06cc
#define mmMPC_RMU1_SHAPER_RAMA_START_CNTL_G_BASE_IDX 3
#define mmMPC_RMU1_SHAPER_RAMA_START_CNTL_R 0x06cd
#define mmMPC_RMU1_SHAPER_RAMA_START_CNTL_R_BASE_IDX 3
#define mmMPC_RMU1_SHAPER_RAMA_END_CNTL_B 0x06ce
#define mmMPC_RMU1_SHAPER_RAMA_END_CNTL_B_BASE_IDX 3
#define mmMPC_RMU1_SHAPER_RAMA_END_CNTL_G 0x06cf
#define mmMPC_RMU1_SHAPER_RAMA_END_CNTL_G_BASE_IDX 3
#define mmMPC_RMU1_SHAPER_RAMA_END_CNTL_R 0x06d0
#define mmMPC_RMU1_SHAPER_RAMA_END_CNTL_R_BASE_IDX 3
#define mmMPC_RMU1_SHAPER_RAMA_REGION_0_1 0x06d1
#define mmMPC_RMU1_SHAPER_RAMA_REGION_0_1_BASE_IDX 3
#define mmMPC_RMU1_SHAPER_RAMA_REGION_2_3 0x06d2
#define mmMPC_RMU1_SHAPER_RAMA_REGION_2_3_BASE_IDX 3
#define mmMPC_RMU1_SHAPER_RAMA_REGION_4_5 0x06d3
#define mmMPC_RMU1_SHAPER_RAMA_REGION_4_5_BASE_IDX 3
#define mmMPC_RMU1_SHAPER_RAMA_REGION_6_7 0x06d4
#define mmMPC_RMU1_SHAPER_RAMA_REGION_6_7_BASE_IDX 3
#define mmMPC_RMU1_SHAPER_RAMA_REGION_8_9 0x06d5
#define mmMPC_RMU1_SHAPER_RAMA_REGION_8_9_BASE_IDX 3
#define mmMPC_RMU1_SHAPER_RAMA_REGION_10_11 0x06d6
#define mmMPC_RMU1_SHAPER_RAMA_REGION_10_11_BASE_IDX 3
#define mmMPC_RMU1_SHAPER_RAMA_REGION_12_13 0x06d7
#define mmMPC_RMU1_SHAPER_RAMA_REGION_12_13_BASE_IDX 3
#define mmMPC_RMU1_SHAPER_RAMA_REGION_14_15 0x06d8
#define mmMPC_RMU1_SHAPER_RAMA_REGION_14_15_BASE_IDX 3
#define mmMPC_RMU1_SHAPER_RAMA_REGION_16_17 0x06d9
#define mmMPC_RMU1_SHAPER_RAMA_REGION_16_17_BASE_IDX 3
#define mmMPC_RMU1_SHAPER_RAMA_REGION_18_19 0x06da
#define mmMPC_RMU1_SHAPER_RAMA_REGION_18_19_BASE_IDX 3
#define mmMPC_RMU1_SHAPER_RAMA_REGION_20_21 0x06db
#define mmMPC_RMU1_SHAPER_RAMA_REGION_20_21_BASE_IDX 3
#define mmMPC_RMU1_SHAPER_RAMA_REGION_22_23 0x06dc
#define mmMPC_RMU1_SHAPER_RAMA_REGION_22_23_BASE_IDX 3
#define mmMPC_RMU1_SHAPER_RAMA_REGION_24_25 0x06dd
#define mmMPC_RMU1_SHAPER_RAMA_REGION_24_25_BASE_IDX 3
#define mmMPC_RMU1_SHAPER_RAMA_REGION_26_27 0x06de
#define mmMPC_RMU1_SHAPER_RAMA_REGION_26_27_BASE_IDX 3
#define mmMPC_RMU1_SHAPER_RAMA_REGION_28_29 0x06df
#define mmMPC_RMU1_SHAPER_RAMA_REGION_28_29_BASE_IDX 3
#define mmMPC_RMU1_SHAPER_RAMA_REGION_30_31 0x06e0
#define mmMPC_RMU1_SHAPER_RAMA_REGION_30_31_BASE_IDX 3
#define mmMPC_RMU1_SHAPER_RAMA_REGION_32_33 0x06e1
#define mmMPC_RMU1_SHAPER_RAMA_REGION_32_33_BASE_IDX 3
#define mmMPC_RMU1_SHAPER_RAMB_START_CNTL_B 0x06e2
#define mmMPC_RMU1_SHAPER_RAMB_START_CNTL_B_BASE_IDX 3
#define mmMPC_RMU1_SHAPER_RAMB_START_CNTL_G 0x06e3
#define mmMPC_RMU1_SHAPER_RAMB_START_CNTL_G_BASE_IDX 3
#define mmMPC_RMU1_SHAPER_RAMB_START_CNTL_R 0x06e4
#define mmMPC_RMU1_SHAPER_RAMB_START_CNTL_R_BASE_IDX 3
#define mmMPC_RMU1_SHAPER_RAMB_END_CNTL_B 0x06e5
#define mmMPC_RMU1_SHAPER_RAMB_END_CNTL_B_BASE_IDX 3
#define mmMPC_RMU1_SHAPER_RAMB_END_CNTL_G 0x06e6
#define mmMPC_RMU1_SHAPER_RAMB_END_CNTL_G_BASE_IDX 3
#define mmMPC_RMU1_SHAPER_RAMB_END_CNTL_R 0x06e7
#define mmMPC_RMU1_SHAPER_RAMB_END_CNTL_R_BASE_IDX 3
#define mmMPC_RMU1_SHAPER_RAMB_REGION_0_1 0x06e8
#define mmMPC_RMU1_SHAPER_RAMB_REGION_0_1_BASE_IDX 3
#define mmMPC_RMU1_SHAPER_RAMB_REGION_2_3 0x06e9
#define mmMPC_RMU1_SHAPER_RAMB_REGION_2_3_BASE_IDX 3
#define mmMPC_RMU1_SHAPER_RAMB_REGION_4_5 0x06ea
#define mmMPC_RMU1_SHAPER_RAMB_REGION_4_5_BASE_IDX 3
#define mmMPC_RMU1_SHAPER_RAMB_REGION_6_7 0x06eb
#define mmMPC_RMU1_SHAPER_RAMB_REGION_6_7_BASE_IDX 3
#define mmMPC_RMU1_SHAPER_RAMB_REGION_8_9 0x06ec
#define mmMPC_RMU1_SHAPER_RAMB_REGION_8_9_BASE_IDX 3
#define mmMPC_RMU1_SHAPER_RAMB_REGION_10_11 0x06ed
#define mmMPC_RMU1_SHAPER_RAMB_REGION_10_11_BASE_IDX 3
#define mmMPC_RMU1_SHAPER_RAMB_REGION_12_13 0x06ee
#define mmMPC_RMU1_SHAPER_RAMB_REGION_12_13_BASE_IDX 3
#define mmMPC_RMU1_SHAPER_RAMB_REGION_14_15 0x06ef
#define mmMPC_RMU1_SHAPER_RAMB_REGION_14_15_BASE_IDX 3
#define mmMPC_RMU1_SHAPER_RAMB_REGION_16_17 0x06f0
#define mmMPC_RMU1_SHAPER_RAMB_REGION_16_17_BASE_IDX 3
#define mmMPC_RMU1_SHAPER_RAMB_REGION_18_19 0x06f1
#define mmMPC_RMU1_SHAPER_RAMB_REGION_18_19_BASE_IDX 3
#define mmMPC_RMU1_SHAPER_RAMB_REGION_20_21 0x06f2
#define mmMPC_RMU1_SHAPER_RAMB_REGION_20_21_BASE_IDX 3
#define mmMPC_RMU1_SHAPER_RAMB_REGION_22_23 0x06f3
#define mmMPC_RMU1_SHAPER_RAMB_REGION_22_23_BASE_IDX 3
#define mmMPC_RMU1_SHAPER_RAMB_REGION_24_25 0x06f4
#define mmMPC_RMU1_SHAPER_RAMB_REGION_24_25_BASE_IDX 3
#define mmMPC_RMU1_SHAPER_RAMB_REGION_26_27 0x06f5
#define mmMPC_RMU1_SHAPER_RAMB_REGION_26_27_BASE_IDX 3
#define mmMPC_RMU1_SHAPER_RAMB_REGION_28_29 0x06f6
#define mmMPC_RMU1_SHAPER_RAMB_REGION_28_29_BASE_IDX 3
#define mmMPC_RMU1_SHAPER_RAMB_REGION_30_31 0x06f7
#define mmMPC_RMU1_SHAPER_RAMB_REGION_30_31_BASE_IDX 3
#define mmMPC_RMU1_SHAPER_RAMB_REGION_32_33 0x06f8
#define mmMPC_RMU1_SHAPER_RAMB_REGION_32_33_BASE_IDX 3
#define mmMPC_RMU1_3DLUT_MODE 0x06f9
#define mmMPC_RMU1_3DLUT_MODE_BASE_IDX 3
#define mmMPC_RMU1_3DLUT_INDEX 0x06fa
#define mmMPC_RMU1_3DLUT_INDEX_BASE_IDX 3
#define mmMPC_RMU1_3DLUT_DATA 0x06fb
#define mmMPC_RMU1_3DLUT_DATA_BASE_IDX 3
#define mmMPC_RMU1_3DLUT_DATA_30BIT 0x06fc
#define mmMPC_RMU1_3DLUT_DATA_30BIT_BASE_IDX 3
#define mmMPC_RMU1_3DLUT_READ_WRITE_CONTROL 0x06fd
#define mmMPC_RMU1_3DLUT_READ_WRITE_CONTROL_BASE_IDX 3
#define mmMPC_RMU1_3DLUT_OUT_NORM_FACTOR 0x06fe
#define mmMPC_RMU1_3DLUT_OUT_NORM_FACTOR_BASE_IDX 3
#define mmMPC_RMU1_3DLUT_OUT_OFFSET_R 0x06ff
#define mmMPC_RMU1_3DLUT_OUT_OFFSET_R_BASE_IDX 3
#define mmMPC_RMU1_3DLUT_OUT_OFFSET_G 0x0700
#define mmMPC_RMU1_3DLUT_OUT_OFFSET_G_BASE_IDX 3
#define mmMPC_RMU1_3DLUT_OUT_OFFSET_B 0x0701
#define mmMPC_RMU1_3DLUT_OUT_OFFSET_B_BASE_IDX 3
#define mmMPC_RMU2_SHAPER_CONTROL 0x0702
#define mmMPC_RMU2_SHAPER_CONTROL_BASE_IDX 3
#define mmMPC_RMU2_SHAPER_OFFSET_R 0x0703
#define mmMPC_RMU2_SHAPER_OFFSET_R_BASE_IDX 3
#define mmMPC_RMU2_SHAPER_OFFSET_G 0x0704
#define mmMPC_RMU2_SHAPER_OFFSET_G_BASE_IDX 3
#define mmMPC_RMU2_SHAPER_OFFSET_B 0x0705
#define mmMPC_RMU2_SHAPER_OFFSET_B_BASE_IDX 3
#define mmMPC_RMU2_SHAPER_SCALE_R 0x0706
#define mmMPC_RMU2_SHAPER_SCALE_R_BASE_IDX 3
#define mmMPC_RMU2_SHAPER_SCALE_G_B 0x0707
#define mmMPC_RMU2_SHAPER_SCALE_G_B_BASE_IDX 3
#define mmMPC_RMU2_SHAPER_LUT_INDEX 0x0708
#define mmMPC_RMU2_SHAPER_LUT_INDEX_BASE_IDX 3
#define mmMPC_RMU2_SHAPER_LUT_DATA 0x0709
#define mmMPC_RMU2_SHAPER_LUT_DATA_BASE_IDX 3
#define mmMPC_RMU2_SHAPER_LUT_WRITE_EN_MASK 0x070a
#define mmMPC_RMU2_SHAPER_LUT_WRITE_EN_MASK_BASE_IDX 3
#define mmMPC_RMU2_SHAPER_RAMA_START_CNTL_B 0x070b
#define mmMPC_RMU2_SHAPER_RAMA_START_CNTL_B_BASE_IDX 3
#define mmMPC_RMU2_SHAPER_RAMA_START_CNTL_G 0x070c
#define mmMPC_RMU2_SHAPER_RAMA_START_CNTL_G_BASE_IDX 3
#define mmMPC_RMU2_SHAPER_RAMA_START_CNTL_R 0x070d
#define mmMPC_RMU2_SHAPER_RAMA_START_CNTL_R_BASE_IDX 3
#define mmMPC_RMU2_SHAPER_RAMA_END_CNTL_B 0x070e
#define mmMPC_RMU2_SHAPER_RAMA_END_CNTL_B_BASE_IDX 3
#define mmMPC_RMU2_SHAPER_RAMA_END_CNTL_G 0x070f
#define mmMPC_RMU2_SHAPER_RAMA_END_CNTL_G_BASE_IDX 3
#define mmMPC_RMU2_SHAPER_RAMA_END_CNTL_R 0x0710
#define mmMPC_RMU2_SHAPER_RAMA_END_CNTL_R_BASE_IDX 3
#define mmMPC_RMU2_SHAPER_RAMA_REGION_0_1 0x0711
#define mmMPC_RMU2_SHAPER_RAMA_REGION_0_1_BASE_IDX 3
#define mmMPC_RMU2_SHAPER_RAMA_REGION_2_3 0x0712
#define mmMPC_RMU2_SHAPER_RAMA_REGION_2_3_BASE_IDX 3
#define mmMPC_RMU2_SHAPER_RAMA_REGION_4_5 0x0713
#define mmMPC_RMU2_SHAPER_RAMA_REGION_4_5_BASE_IDX 3
#define mmMPC_RMU2_SHAPER_RAMA_REGION_6_7 0x0714
#define mmMPC_RMU2_SHAPER_RAMA_REGION_6_7_BASE_IDX 3
#define mmMPC_RMU2_SHAPER_RAMA_REGION_8_9 0x0715
#define mmMPC_RMU2_SHAPER_RAMA_REGION_8_9_BASE_IDX 3
#define mmMPC_RMU2_SHAPER_RAMA_REGION_10_11 0x0716
#define mmMPC_RMU2_SHAPER_RAMA_REGION_10_11_BASE_IDX 3
#define mmMPC_RMU2_SHAPER_RAMA_REGION_12_13 0x0717
#define mmMPC_RMU2_SHAPER_RAMA_REGION_12_13_BASE_IDX 3
#define mmMPC_RMU2_SHAPER_RAMA_REGION_14_15 0x0718
#define mmMPC_RMU2_SHAPER_RAMA_REGION_14_15_BASE_IDX 3
#define mmMPC_RMU2_SHAPER_RAMA_REGION_16_17 0x0719
#define mmMPC_RMU2_SHAPER_RAMA_REGION_16_17_BASE_IDX 3
#define mmMPC_RMU2_SHAPER_RAMA_REGION_18_19 0x071a
#define mmMPC_RMU2_SHAPER_RAMA_REGION_18_19_BASE_IDX 3
#define mmMPC_RMU2_SHAPER_RAMA_REGION_20_21 0x071b
#define mmMPC_RMU2_SHAPER_RAMA_REGION_20_21_BASE_IDX 3
#define mmMPC_RMU2_SHAPER_RAMA_REGION_22_23 0x071c
#define mmMPC_RMU2_SHAPER_RAMA_REGION_22_23_BASE_IDX 3
#define mmMPC_RMU2_SHAPER_RAMA_REGION_24_25 0x071d
#define mmMPC_RMU2_SHAPER_RAMA_REGION_24_25_BASE_IDX 3
#define mmMPC_RMU2_SHAPER_RAMA_REGION_26_27 0x071e
#define mmMPC_RMU2_SHAPER_RAMA_REGION_26_27_BASE_IDX 3
#define mmMPC_RMU2_SHAPER_RAMA_REGION_28_29 0x071f
#define mmMPC_RMU2_SHAPER_RAMA_REGION_28_29_BASE_IDX 3
#define mmMPC_RMU2_SHAPER_RAMA_REGION_30_31 0x0720
#define mmMPC_RMU2_SHAPER_RAMA_REGION_30_31_BASE_IDX 3
#define mmMPC_RMU2_SHAPER_RAMA_REGION_32_33 0x0721
#define mmMPC_RMU2_SHAPER_RAMA_REGION_32_33_BASE_IDX 3
#define mmMPC_RMU2_SHAPER_RAMB_START_CNTL_B 0x0722
#define mmMPC_RMU2_SHAPER_RAMB_START_CNTL_B_BASE_IDX 3
#define mmMPC_RMU2_SHAPER_RAMB_START_CNTL_G 0x0723
#define mmMPC_RMU2_SHAPER_RAMB_START_CNTL_G_BASE_IDX 3
#define mmMPC_RMU2_SHAPER_RAMB_START_CNTL_R 0x0724
#define mmMPC_RMU2_SHAPER_RAMB_START_CNTL_R_BASE_IDX 3
#define mmMPC_RMU2_SHAPER_RAMB_END_CNTL_B 0x0725
#define mmMPC_RMU2_SHAPER_RAMB_END_CNTL_B_BASE_IDX 3
#define mmMPC_RMU2_SHAPER_RAMB_END_CNTL_G 0x0726
#define mmMPC_RMU2_SHAPER_RAMB_END_CNTL_G_BASE_IDX 3
#define mmMPC_RMU2_SHAPER_RAMB_END_CNTL_R 0x0727
#define mmMPC_RMU2_SHAPER_RAMB_END_CNTL_R_BASE_IDX 3
#define mmMPC_RMU2_SHAPER_RAMB_REGION_0_1 0x0728
#define mmMPC_RMU2_SHAPER_RAMB_REGION_0_1_BASE_IDX 3
#define mmMPC_RMU2_SHAPER_RAMB_REGION_2_3 0x0729
#define mmMPC_RMU2_SHAPER_RAMB_REGION_2_3_BASE_IDX 3
#define mmMPC_RMU2_SHAPER_RAMB_REGION_4_5 0x072a
#define mmMPC_RMU2_SHAPER_RAMB_REGION_4_5_BASE_IDX 3
#define mmMPC_RMU2_SHAPER_RAMB_REGION_6_7 0x072b
#define mmMPC_RMU2_SHAPER_RAMB_REGION_6_7_BASE_IDX 3
#define mmMPC_RMU2_SHAPER_RAMB_REGION_8_9 0x072c
#define mmMPC_RMU2_SHAPER_RAMB_REGION_8_9_BASE_IDX 3
#define mmMPC_RMU2_SHAPER_RAMB_REGION_10_11 0x072d
#define mmMPC_RMU2_SHAPER_RAMB_REGION_10_11_BASE_IDX 3
#define mmMPC_RMU2_SHAPER_RAMB_REGION_12_13 0x072e
#define mmMPC_RMU2_SHAPER_RAMB_REGION_12_13_BASE_IDX 3
#define mmMPC_RMU2_SHAPER_RAMB_REGION_14_15 0x072f
#define mmMPC_RMU2_SHAPER_RAMB_REGION_14_15_BASE_IDX 3
#define mmMPC_RMU2_SHAPER_RAMB_REGION_16_17 0x0730
#define mmMPC_RMU2_SHAPER_RAMB_REGION_16_17_BASE_IDX 3
#define mmMPC_RMU2_SHAPER_RAMB_REGION_18_19 0x0731
#define mmMPC_RMU2_SHAPER_RAMB_REGION_18_19_BASE_IDX 3
#define mmMPC_RMU2_SHAPER_RAMB_REGION_20_21 0x0732
#define mmMPC_RMU2_SHAPER_RAMB_REGION_20_21_BASE_IDX 3
#define mmMPC_RMU2_SHAPER_RAMB_REGION_22_23 0x0733
#define mmMPC_RMU2_SHAPER_RAMB_REGION_22_23_BASE_IDX 3
#define mmMPC_RMU2_SHAPER_RAMB_REGION_24_25 0x0734
#define mmMPC_RMU2_SHAPER_RAMB_REGION_24_25_BASE_IDX 3
#define mmMPC_RMU2_SHAPER_RAMB_REGION_26_27 0x0735
#define mmMPC_RMU2_SHAPER_RAMB_REGION_26_27_BASE_IDX 3
#define mmMPC_RMU2_SHAPER_RAMB_REGION_28_29 0x0736
#define mmMPC_RMU2_SHAPER_RAMB_REGION_28_29_BASE_IDX 3
#define mmMPC_RMU2_SHAPER_RAMB_REGION_30_31 0x0737
#define mmMPC_RMU2_SHAPER_RAMB_REGION_30_31_BASE_IDX 3
#define mmMPC_RMU2_SHAPER_RAMB_REGION_32_33 0x0738
#define mmMPC_RMU2_SHAPER_RAMB_REGION_32_33_BASE_IDX 3
#define mmMPC_RMU2_3DLUT_MODE 0x0739
#define mmMPC_RMU2_3DLUT_MODE_BASE_IDX 3
#define mmMPC_RMU2_3DLUT_INDEX 0x073a
#define mmMPC_RMU2_3DLUT_INDEX_BASE_IDX 3
#define mmMPC_RMU2_3DLUT_DATA 0x073b
#define mmMPC_RMU2_3DLUT_DATA_BASE_IDX 3
#define mmMPC_RMU2_3DLUT_DATA_30BIT 0x073c
#define mmMPC_RMU2_3DLUT_DATA_30BIT_BASE_IDX 3
#define mmMPC_RMU2_3DLUT_READ_WRITE_CONTROL 0x073d
#define mmMPC_RMU2_3DLUT_READ_WRITE_CONTROL_BASE_IDX 3
#define mmMPC_RMU2_3DLUT_OUT_NORM_FACTOR 0x073e
#define mmMPC_RMU2_3DLUT_OUT_NORM_FACTOR_BASE_IDX 3
#define mmMPC_RMU2_3DLUT_OUT_OFFSET_R 0x073f
#define mmMPC_RMU2_3DLUT_OUT_OFFSET_R_BASE_IDX 3
#define mmMPC_RMU2_3DLUT_OUT_OFFSET_G 0x0740
#define mmMPC_RMU2_3DLUT_OUT_OFFSET_G_BASE_IDX 3
#define mmMPC_RMU2_3DLUT_OUT_OFFSET_B 0x0741
#define mmMPC_RMU2_3DLUT_OUT_OFFSET_B_BASE_IDX 3
// addressBlock: dce_dc_mpc_mpc_dcperfmon_dc_perfmon_dispdec
// base address: 0x1901c
#define mmDC_PERFMON25_PERFCOUNTER_CNTL 0x08c7
#define mmDC_PERFMON25_PERFCOUNTER_CNTL_BASE_IDX 3
#define mmDC_PERFMON25_PERFCOUNTER_CNTL2 0x08c8
#define mmDC_PERFMON25_PERFCOUNTER_CNTL2_BASE_IDX 3
#define mmDC_PERFMON25_PERFCOUNTER_STATE 0x08c9
#define mmDC_PERFMON25_PERFCOUNTER_STATE_BASE_IDX 3
#define mmDC_PERFMON25_PERFMON_CNTL 0x08ca
#define mmDC_PERFMON25_PERFMON_CNTL_BASE_IDX 3
#define mmDC_PERFMON25_PERFMON_CNTL2 0x08cb
#define mmDC_PERFMON25_PERFMON_CNTL2_BASE_IDX 3
#define mmDC_PERFMON25_PERFMON_CVALUE_INT_MISC 0x08cc
#define mmDC_PERFMON25_PERFMON_CVALUE_INT_MISC_BASE_IDX 3
#define mmDC_PERFMON25_PERFMON_CVALUE_LOW 0x08cd
#define mmDC_PERFMON25_PERFMON_CVALUE_LOW_BASE_IDX 3
#define mmDC_PERFMON25_PERFMON_HI 0x08ce
#define mmDC_PERFMON25_PERFMON_HI_BASE_IDX 3
#define mmDC_PERFMON25_PERFMON_LOW 0x08cf
#define mmDC_PERFMON25_PERFMON_LOW_BASE_IDX 3
// base address: 0x264f0
#define mmDME5_DME_CONTROL 0x093c
#define mmDME5_DME_CONTROL_BASE_IDX 3
#define mmDME5_DME_MEMORY_CONTROL 0x093d
#define mmDME5_DME_MEMORY_CONTROL_BASE_IDX 3
// addressBlock: dce_dc_hpo_hdmi_stream_enc0_hdcp2_hdcp2_dispdec
// base address: 0x264f8
// addressBlock: dce_dc_hpo_hpo_top_dispdec
// base address: 0x0
#define mmHPO_TOP_CLOCK_CONTROL 0x0e43
#define mmHPO_TOP_CLOCK_CONTROL_BASE_IDX 3
// base address: 0x1a698
#define mmDC_PERFMON26_PERFCOUNTER_CNTL 0x0e66
#define mmDC_PERFMON26_PERFCOUNTER_CNTL_BASE_IDX 3
#define mmDC_PERFMON26_PERFCOUNTER_CNTL2 0x0e67
#define mmDC_PERFMON26_PERFCOUNTER_CNTL2_BASE_IDX 3
#define mmDC_PERFMON26_PERFCOUNTER_STATE 0x0e68
#define mmDC_PERFMON26_PERFCOUNTER_STATE_BASE_IDX 3
#define mmDC_PERFMON26_PERFMON_CNTL 0x0e69
#define mmDC_PERFMON26_PERFMON_CNTL_BASE_IDX 3
#define mmDC_PERFMON26_PERFMON_CNTL2 0x0e6a
#define mmDC_PERFMON26_PERFMON_CNTL2_BASE_IDX 3
#define mmDC_PERFMON26_PERFMON_CVALUE_INT_MISC 0x0e6b
#define mmDC_PERFMON26_PERFMON_CVALUE_INT_MISC_BASE_IDX 3
#define mmDC_PERFMON26_PERFMON_CVALUE_LOW 0x0e6c
#define mmDC_PERFMON26_PERFMON_CVALUE_LOW_BASE_IDX 3
#define mmDC_PERFMON26_PERFMON_HI 0x0e6d
#define mmDC_PERFMON26_PERFMON_HI_BASE_IDX 3
#define mmDC_PERFMON26_PERFMON_LOW 0x0e6e
#define mmDC_PERFMON26_PERFMON_LOW_BASE_IDX 3
// addressBlock: dce_dc_opp_abm0_dispdec
// base address: 0x0
#define mmABM0_BL1_PWM_AMBIENT_LIGHT_LEVEL 0x0e7a
#define mmABM0_BL1_PWM_AMBIENT_LIGHT_LEVEL_BASE_IDX 3
#define mmABM0_BL1_PWM_USER_LEVEL 0x0e7b
#define mmABM0_BL1_PWM_USER_LEVEL_BASE_IDX 3
#define mmABM0_BL1_PWM_TARGET_ABM_LEVEL 0x0e7c
#define mmABM0_BL1_PWM_TARGET_ABM_LEVEL_BASE_IDX 3
#define mmABM0_BL1_PWM_CURRENT_ABM_LEVEL 0x0e7d
#define mmABM0_BL1_PWM_CURRENT_ABM_LEVEL_BASE_IDX 3
#define mmABM0_BL1_PWM_FINAL_DUTY_CYCLE 0x0e7e
#define mmABM0_BL1_PWM_FINAL_DUTY_CYCLE_BASE_IDX 3
#define mmABM0_BL1_PWM_MINIMUM_DUTY_CYCLE 0x0e7f
#define mmABM0_BL1_PWM_MINIMUM_DUTY_CYCLE_BASE_IDX 3
#define mmABM0_BL1_PWM_ABM_CNTL 0x0e80
#define mmABM0_BL1_PWM_ABM_CNTL_BASE_IDX 3
#define mmABM0_BL1_PWM_BL_UPDATE_SAMPLE_RATE 0x0e81
#define mmABM0_BL1_PWM_BL_UPDATE_SAMPLE_RATE_BASE_IDX 3
#define mmABM0_BL1_PWM_GRP2_REG_LOCK 0x0e82
#define mmABM0_BL1_PWM_GRP2_REG_LOCK_BASE_IDX 3
#define mmABM0_DC_ABM1_CNTL 0x0e83
#define mmABM0_DC_ABM1_CNTL_BASE_IDX 3
#define mmABM0_DC_ABM1_IPCSC_COEFF_SEL 0x0e84
#define mmABM0_DC_ABM1_IPCSC_COEFF_SEL_BASE_IDX 3
#define mmABM0_DC_ABM1_ACE_OFFSET_SLOPE_0 0x0e85
#define mmABM0_DC_ABM1_ACE_OFFSET_SLOPE_0_BASE_IDX 3
#define mmABM0_DC_ABM1_ACE_OFFSET_SLOPE_1 0x0e86
#define mmABM0_DC_ABM1_ACE_OFFSET_SLOPE_1_BASE_IDX 3
#define mmABM0_DC_ABM1_ACE_OFFSET_SLOPE_2 0x0e87
#define mmABM0_DC_ABM1_ACE_OFFSET_SLOPE_2_BASE_IDX 3
#define mmABM0_DC_ABM1_ACE_OFFSET_SLOPE_3 0x0e88
#define mmABM0_DC_ABM1_ACE_OFFSET_SLOPE_3_BASE_IDX 3
#define mmABM0_DC_ABM1_ACE_OFFSET_SLOPE_4 0x0e89
#define mmABM0_DC_ABM1_ACE_OFFSET_SLOPE_4_BASE_IDX 3
#define mmABM0_DC_ABM1_ACE_THRES_12 0x0e8a
#define mmABM0_DC_ABM1_ACE_THRES_12_BASE_IDX 3
#define mmABM0_DC_ABM1_ACE_THRES_34 0x0e8b
#define mmABM0_DC_ABM1_ACE_THRES_34_BASE_IDX 3
#define mmABM0_DC_ABM1_ACE_CNTL_MISC 0x0e8c
#define mmABM0_DC_ABM1_ACE_CNTL_MISC_BASE_IDX 3
#define mmABM0_DC_ABM1_HGLS_REG_READ_PROGRESS 0x0e8e
#define mmABM0_DC_ABM1_HGLS_REG_READ_PROGRESS_BASE_IDX 3
#define mmABM0_DC_ABM1_HG_MISC_CTRL 0x0e8f
#define mmABM0_DC_ABM1_HG_MISC_CTRL_BASE_IDX 3
#define mmABM0_DC_ABM1_LS_SUM_OF_LUMA 0x0e90
#define mmABM0_DC_ABM1_LS_SUM_OF_LUMA_BASE_IDX 3
#define mmABM0_DC_ABM1_LS_MIN_MAX_LUMA 0x0e91
#define mmABM0_DC_ABM1_LS_MIN_MAX_LUMA_BASE_IDX 3
#define mmABM0_DC_ABM1_LS_FILTERED_MIN_MAX_LUMA 0x0e92
#define mmABM0_DC_ABM1_LS_FILTERED_MIN_MAX_LUMA_BASE_IDX 3
#define mmABM0_DC_ABM1_LS_PIXEL_COUNT 0x0e93
#define mmABM0_DC_ABM1_LS_PIXEL_COUNT_BASE_IDX 3
#define mmABM0_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES 0x0e94
#define mmABM0_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES_BASE_IDX 3
#define mmABM0_DC_ABM1_LS_MIN_PIXEL_VALUE_COUNT 0x0e95
#define mmABM0_DC_ABM1_LS_MIN_PIXEL_VALUE_COUNT_BASE_IDX 3
#define mmABM0_DC_ABM1_LS_MAX_PIXEL_VALUE_COUNT 0x0e96
#define mmABM0_DC_ABM1_LS_MAX_PIXEL_VALUE_COUNT_BASE_IDX 3
#define mmABM0_DC_ABM1_HG_SAMPLE_RATE 0x0e97
#define mmABM0_DC_ABM1_HG_SAMPLE_RATE_BASE_IDX 3
#define mmABM0_DC_ABM1_LS_SAMPLE_RATE 0x0e98
#define mmABM0_DC_ABM1_LS_SAMPLE_RATE_BASE_IDX 3
#define mmABM0_DC_ABM1_HG_BIN_1_32_SHIFT_FLAG 0x0e99
#define mmABM0_DC_ABM1_HG_BIN_1_32_SHIFT_FLAG_BASE_IDX 3
#define mmABM0_DC_ABM1_HG_BIN_1_8_SHIFT_INDEX 0x0e9a
#define mmABM0_DC_ABM1_HG_BIN_1_8_SHIFT_INDEX_BASE_IDX 3
#define mmABM0_DC_ABM1_HG_BIN_9_16_SHIFT_INDEX 0x0e9b
#define mmABM0_DC_ABM1_HG_BIN_9_16_SHIFT_INDEX_BASE_IDX 3
#define mmABM0_DC_ABM1_HG_BIN_17_24_SHIFT_INDEX 0x0e9c
#define mmABM0_DC_ABM1_HG_BIN_17_24_SHIFT_INDEX_BASE_IDX 3
#define mmABM0_DC_ABM1_HG_BIN_25_32_SHIFT_INDEX 0x0e9d
#define mmABM0_DC_ABM1_HG_BIN_25_32_SHIFT_INDEX_BASE_IDX 3
#define mmABM0_DC_ABM1_HG_RESULT_1 0x0e9e
#define mmABM0_DC_ABM1_HG_RESULT_1_BASE_IDX 3
#define mmABM0_DC_ABM1_HG_RESULT_2 0x0e9f
#define mmABM0_DC_ABM1_HG_RESULT_2_BASE_IDX 3
#define mmABM0_DC_ABM1_HG_RESULT_3 0x0ea0
#define mmABM0_DC_ABM1_HG_RESULT_3_BASE_IDX 3
#define mmABM0_DC_ABM1_HG_RESULT_4 0x0ea1
#define mmABM0_DC_ABM1_HG_RESULT_4_BASE_IDX 3
#define mmABM0_DC_ABM1_HG_RESULT_5 0x0ea2
#define mmABM0_DC_ABM1_HG_RESULT_5_BASE_IDX 3
#define mmABM0_DC_ABM1_HG_RESULT_6 0x0ea3
#define mmABM0_DC_ABM1_HG_RESULT_6_BASE_IDX 3
#define mmABM0_DC_ABM1_HG_RESULT_7 0x0ea4
#define mmABM0_DC_ABM1_HG_RESULT_7_BASE_IDX 3
#define mmABM0_DC_ABM1_HG_RESULT_8 0x0ea5
#define mmABM0_DC_ABM1_HG_RESULT_8_BASE_IDX 3
#define mmABM0_DC_ABM1_HG_RESULT_9 0x0ea6
#define mmABM0_DC_ABM1_HG_RESULT_9_BASE_IDX 3
#define mmABM0_DC_ABM1_HG_RESULT_10 0x0ea7
#define mmABM0_DC_ABM1_HG_RESULT_10_BASE_IDX 3
#define mmABM0_DC_ABM1_HG_RESULT_11 0x0ea8
#define mmABM0_DC_ABM1_HG_RESULT_11_BASE_IDX 3
#define mmABM0_DC_ABM1_HG_RESULT_12 0x0ea9
#define mmABM0_DC_ABM1_HG_RESULT_12_BASE_IDX 3
#define mmABM0_DC_ABM1_HG_RESULT_13 0x0eaa
#define mmABM0_DC_ABM1_HG_RESULT_13_BASE_IDX 3
#define mmABM0_DC_ABM1_HG_RESULT_14 0x0eab
#define mmABM0_DC_ABM1_HG_RESULT_14_BASE_IDX 3
#define mmABM0_DC_ABM1_HG_RESULT_15 0x0eac
#define mmABM0_DC_ABM1_HG_RESULT_15_BASE_IDX 3
#define mmABM0_DC_ABM1_HG_RESULT_16 0x0ead
#define mmABM0_DC_ABM1_HG_RESULT_16_BASE_IDX 3
#define mmABM0_DC_ABM1_HG_RESULT_17 0x0eae
#define mmABM0_DC_ABM1_HG_RESULT_17_BASE_IDX 3
#define mmABM0_DC_ABM1_HG_RESULT_18 0x0eaf
#define mmABM0_DC_ABM1_HG_RESULT_18_BASE_IDX 3
#define mmABM0_DC_ABM1_HG_RESULT_19 0x0eb0
#define mmABM0_DC_ABM1_HG_RESULT_19_BASE_IDX 3
#define mmABM0_DC_ABM1_HG_RESULT_20 0x0eb1
#define mmABM0_DC_ABM1_HG_RESULT_20_BASE_IDX 3
#define mmABM0_DC_ABM1_HG_RESULT_21 0x0eb2
#define mmABM0_DC_ABM1_HG_RESULT_21_BASE_IDX 3
#define mmABM0_DC_ABM1_HG_RESULT_22 0x0eb3
#define mmABM0_DC_ABM1_HG_RESULT_22_BASE_IDX 3
#define mmABM0_DC_ABM1_HG_RESULT_23 0x0eb4
#define mmABM0_DC_ABM1_HG_RESULT_23_BASE_IDX 3
#define mmABM0_DC_ABM1_HG_RESULT_24 0x0eb5
#define mmABM0_DC_ABM1_HG_RESULT_24_BASE_IDX 3
#define mmABM0_DC_ABM1_BL_MASTER_LOCK 0x0eb6
#define mmABM0_DC_ABM1_BL_MASTER_LOCK_BASE_IDX 3
// addressBlock: dce_dc_opp_abm1_dispdec
// base address: 0x104
#define mmABM1_BL1_PWM_AMBIENT_LIGHT_LEVEL 0x0ebb
#define mmABM1_BL1_PWM_AMBIENT_LIGHT_LEVEL_BASE_IDX 3
#define mmABM1_BL1_PWM_USER_LEVEL 0x0ebc
#define mmABM1_BL1_PWM_USER_LEVEL_BASE_IDX 3
#define mmABM1_BL1_PWM_TARGET_ABM_LEVEL 0x0ebd
#define mmABM1_BL1_PWM_TARGET_ABM_LEVEL_BASE_IDX 3
#define mmABM1_BL1_PWM_CURRENT_ABM_LEVEL 0x0ebe
#define mmABM1_BL1_PWM_CURRENT_ABM_LEVEL_BASE_IDX 3
#define mmABM1_BL1_PWM_FINAL_DUTY_CYCLE 0x0ebf
#define mmABM1_BL1_PWM_FINAL_DUTY_CYCLE_BASE_IDX 3
#define mmABM1_BL1_PWM_MINIMUM_DUTY_CYCLE 0x0ec0
#define mmABM1_BL1_PWM_MINIMUM_DUTY_CYCLE_BASE_IDX 3
#define mmABM1_BL1_PWM_ABM_CNTL 0x0ec1
#define mmABM1_BL1_PWM_ABM_CNTL_BASE_IDX 3
#define mmABM1_BL1_PWM_BL_UPDATE_SAMPLE_RATE 0x0ec2
#define mmABM1_BL1_PWM_BL_UPDATE_SAMPLE_RATE_BASE_IDX 3
#define mmABM1_BL1_PWM_GRP2_REG_LOCK 0x0ec3
#define mmABM1_BL1_PWM_GRP2_REG_LOCK_BASE_IDX 3
#define mmABM1_DC_ABM1_CNTL 0x0ec4
#define mmABM1_DC_ABM1_CNTL_BASE_IDX 3
#define mmABM1_DC_ABM1_IPCSC_COEFF_SEL 0x0ec5
#define mmABM1_DC_ABM1_IPCSC_COEFF_SEL_BASE_IDX 3
#define mmABM1_DC_ABM1_ACE_OFFSET_SLOPE_0 0x0ec6
#define mmABM1_DC_ABM1_ACE_OFFSET_SLOPE_0_BASE_IDX 3
#define mmABM1_DC_ABM1_ACE_OFFSET_SLOPE_1 0x0ec7
#define mmABM1_DC_ABM1_ACE_OFFSET_SLOPE_1_BASE_IDX 3
#define mmABM1_DC_ABM1_ACE_OFFSET_SLOPE_2 0x0ec8
#define mmABM1_DC_ABM1_ACE_OFFSET_SLOPE_2_BASE_IDX 3
#define mmABM1_DC_ABM1_ACE_OFFSET_SLOPE_3 0x0ec9
#define mmABM1_DC_ABM1_ACE_OFFSET_SLOPE_3_BASE_IDX 3
#define mmABM1_DC_ABM1_ACE_OFFSET_SLOPE_4 0x0eca
#define mmABM1_DC_ABM1_ACE_OFFSET_SLOPE_4_BASE_IDX 3
#define mmABM1_DC_ABM1_ACE_THRES_12 0x0ecb
#define mmABM1_DC_ABM1_ACE_THRES_12_BASE_IDX 3
#define mmABM1_DC_ABM1_ACE_THRES_34 0x0ecc
#define mmABM1_DC_ABM1_ACE_THRES_34_BASE_IDX 3
#define mmABM1_DC_ABM1_ACE_CNTL_MISC 0x0ecd
#define mmABM1_DC_ABM1_ACE_CNTL_MISC_BASE_IDX 3
#define mmABM1_DC_ABM1_HGLS_REG_READ_PROGRESS 0x0ecf
#define mmABM1_DC_ABM1_HGLS_REG_READ_PROGRESS_BASE_IDX 3
#define mmABM1_DC_ABM1_HG_MISC_CTRL 0x0ed0
#define mmABM1_DC_ABM1_HG_MISC_CTRL_BASE_IDX 3
#define mmABM1_DC_ABM1_LS_SUM_OF_LUMA 0x0ed1
#define mmABM1_DC_ABM1_LS_SUM_OF_LUMA_BASE_IDX 3
#define mmABM1_DC_ABM1_LS_MIN_MAX_LUMA 0x0ed2
#define mmABM1_DC_ABM1_LS_MIN_MAX_LUMA_BASE_IDX 3
#define mmABM1_DC_ABM1_LS_FILTERED_MIN_MAX_LUMA 0x0ed3
#define mmABM1_DC_ABM1_LS_FILTERED_MIN_MAX_LUMA_BASE_IDX 3
#define mmABM1_DC_ABM1_LS_PIXEL_COUNT 0x0ed4
#define mmABM1_DC_ABM1_LS_PIXEL_COUNT_BASE_IDX 3
#define mmABM1_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES 0x0ed5
#define mmABM1_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES_BASE_IDX 3
#define mmABM1_DC_ABM1_LS_MIN_PIXEL_VALUE_COUNT 0x0ed6
#define mmABM1_DC_ABM1_LS_MIN_PIXEL_VALUE_COUNT_BASE_IDX 3
#define mmABM1_DC_ABM1_LS_MAX_PIXEL_VALUE_COUNT 0x0ed7
#define mmABM1_DC_ABM1_LS_MAX_PIXEL_VALUE_COUNT_BASE_IDX 3
#define mmABM1_DC_ABM1_HG_SAMPLE_RATE 0x0ed8
#define mmABM1_DC_ABM1_HG_SAMPLE_RATE_BASE_IDX 3
#define mmABM1_DC_ABM1_LS_SAMPLE_RATE 0x0ed9
#define mmABM1_DC_ABM1_LS_SAMPLE_RATE_BASE_IDX 3
#define mmABM1_DC_ABM1_HG_BIN_1_32_SHIFT_FLAG 0x0eda
#define mmABM1_DC_ABM1_HG_BIN_1_32_SHIFT_FLAG_BASE_IDX 3
#define mmABM1_DC_ABM1_HG_BIN_1_8_SHIFT_INDEX 0x0edb
#define mmABM1_DC_ABM1_HG_BIN_1_8_SHIFT_INDEX_BASE_IDX 3
#define mmABM1_DC_ABM1_HG_BIN_9_16_SHIFT_INDEX 0x0edc
#define mmABM1_DC_ABM1_HG_BIN_9_16_SHIFT_INDEX_BASE_IDX 3
#define mmABM1_DC_ABM1_HG_BIN_17_24_SHIFT_INDEX 0x0edd
#define mmABM1_DC_ABM1_HG_BIN_17_24_SHIFT_INDEX_BASE_IDX 3
#define mmABM1_DC_ABM1_HG_BIN_25_32_SHIFT_INDEX 0x0ede
#define mmABM1_DC_ABM1_HG_BIN_25_32_SHIFT_INDEX_BASE_IDX 3
#define mmABM1_DC_ABM1_HG_RESULT_1 0x0edf
#define mmABM1_DC_ABM1_HG_RESULT_1_BASE_IDX 3
#define mmABM1_DC_ABM1_HG_RESULT_2 0x0ee0
#define mmABM1_DC_ABM1_HG_RESULT_2_BASE_IDX 3
#define mmABM1_DC_ABM1_HG_RESULT_3 0x0ee1
#define mmABM1_DC_ABM1_HG_RESULT_3_BASE_IDX 3
#define mmABM1_DC_ABM1_HG_RESULT_4 0x0ee2
#define mmABM1_DC_ABM1_HG_RESULT_4_BASE_IDX 3
#define mmABM1_DC_ABM1_HG_RESULT_5 0x0ee3
#define mmABM1_DC_ABM1_HG_RESULT_5_BASE_IDX 3
#define mmABM1_DC_ABM1_HG_RESULT_6 0x0ee4
#define mmABM1_DC_ABM1_HG_RESULT_6_BASE_IDX 3
#define mmABM1_DC_ABM1_HG_RESULT_7 0x0ee5
#define mmABM1_DC_ABM1_HG_RESULT_7_BASE_IDX 3
#define mmABM1_DC_ABM1_HG_RESULT_8 0x0ee6
#define mmABM1_DC_ABM1_HG_RESULT_8_BASE_IDX 3
#define mmABM1_DC_ABM1_HG_RESULT_9 0x0ee7
#define mmABM1_DC_ABM1_HG_RESULT_9_BASE_IDX 3
#define mmABM1_DC_ABM1_HG_RESULT_10 0x0ee8
#define mmABM1_DC_ABM1_HG_RESULT_10_BASE_IDX 3
#define mmABM1_DC_ABM1_HG_RESULT_11 0x0ee9
#define mmABM1_DC_ABM1_HG_RESULT_11_BASE_IDX 3
#define mmABM1_DC_ABM1_HG_RESULT_12 0x0eea
#define mmABM1_DC_ABM1_HG_RESULT_12_BASE_IDX 3
#define mmABM1_DC_ABM1_HG_RESULT_13 0x0eeb
#define mmABM1_DC_ABM1_HG_RESULT_13_BASE_IDX 3
#define mmABM1_DC_ABM1_HG_RESULT_14 0x0eec
#define mmABM1_DC_ABM1_HG_RESULT_14_BASE_IDX 3
#define mmABM1_DC_ABM1_HG_RESULT_15 0x0eed
#define mmABM1_DC_ABM1_HG_RESULT_15_BASE_IDX 3
#define mmABM1_DC_ABM1_HG_RESULT_16 0x0eee
#define mmABM1_DC_ABM1_HG_RESULT_16_BASE_IDX 3
#define mmABM1_DC_ABM1_HG_RESULT_17 0x0eef
#define mmABM1_DC_ABM1_HG_RESULT_17_BASE_IDX 3
#define mmABM1_DC_ABM1_HG_RESULT_18 0x0ef0
#define mmABM1_DC_ABM1_HG_RESULT_18_BASE_IDX 3
#define mmABM1_DC_ABM1_HG_RESULT_19 0x0ef1
#define mmABM1_DC_ABM1_HG_RESULT_19_BASE_IDX 3
#define mmABM1_DC_ABM1_HG_RESULT_20 0x0ef2
#define mmABM1_DC_ABM1_HG_RESULT_20_BASE_IDX 3
#define mmABM1_DC_ABM1_HG_RESULT_21 0x0ef3
#define mmABM1_DC_ABM1_HG_RESULT_21_BASE_IDX 3
#define mmABM1_DC_ABM1_HG_RESULT_22 0x0ef4
#define mmABM1_DC_ABM1_HG_RESULT_22_BASE_IDX 3
#define mmABM1_DC_ABM1_HG_RESULT_23 0x0ef5
#define mmABM1_DC_ABM1_HG_RESULT_23_BASE_IDX 3
#define mmABM1_DC_ABM1_HG_RESULT_24 0x0ef6
#define mmABM1_DC_ABM1_HG_RESULT_24_BASE_IDX 3
#define mmABM1_DC_ABM1_BL_MASTER_LOCK 0x0ef7
#define mmABM1_DC_ABM1_BL_MASTER_LOCK_BASE_IDX 3
// addressBlock: dce_dc_opp_abm2_dispdec
// base address: 0x208
#define mmABM2_BL1_PWM_AMBIENT_LIGHT_LEVEL 0x0efc
#define mmABM2_BL1_PWM_AMBIENT_LIGHT_LEVEL_BASE_IDX 3
#define mmABM2_BL1_PWM_USER_LEVEL 0x0efd
#define mmABM2_BL1_PWM_USER_LEVEL_BASE_IDX 3
#define mmABM2_BL1_PWM_TARGET_ABM_LEVEL 0x0efe
#define mmABM2_BL1_PWM_TARGET_ABM_LEVEL_BASE_IDX 3
#define mmABM2_BL1_PWM_CURRENT_ABM_LEVEL 0x0eff
#define mmABM2_BL1_PWM_CURRENT_ABM_LEVEL_BASE_IDX 3
#define mmABM2_BL1_PWM_FINAL_DUTY_CYCLE 0x0f00
#define mmABM2_BL1_PWM_FINAL_DUTY_CYCLE_BASE_IDX 3
#define mmABM2_BL1_PWM_MINIMUM_DUTY_CYCLE 0x0f01
#define mmABM2_BL1_PWM_MINIMUM_DUTY_CYCLE_BASE_IDX 3
#define mmABM2_BL1_PWM_ABM_CNTL 0x0f02
#define mmABM2_BL1_PWM_ABM_CNTL_BASE_IDX 3
#define mmABM2_BL1_PWM_BL_UPDATE_SAMPLE_RATE 0x0f03
#define mmABM2_BL1_PWM_BL_UPDATE_SAMPLE_RATE_BASE_IDX 3
#define mmABM2_BL1_PWM_GRP2_REG_LOCK 0x0f04
#define mmABM2_BL1_PWM_GRP2_REG_LOCK_BASE_IDX 3
#define mmABM2_DC_ABM1_CNTL 0x0f05
#define mmABM2_DC_ABM1_CNTL_BASE_IDX 3
#define mmABM2_DC_ABM1_IPCSC_COEFF_SEL 0x0f06
#define mmABM2_DC_ABM1_IPCSC_COEFF_SEL_BASE_IDX 3
#define mmABM2_DC_ABM1_ACE_OFFSET_SLOPE_0 0x0f07
#define mmABM2_DC_ABM1_ACE_OFFSET_SLOPE_0_BASE_IDX 3
#define mmABM2_DC_ABM1_ACE_OFFSET_SLOPE_1 0x0f08
#define mmABM2_DC_ABM1_ACE_OFFSET_SLOPE_1_BASE_IDX 3
#define mmABM2_DC_ABM1_ACE_OFFSET_SLOPE_2 0x0f09
#define mmABM2_DC_ABM1_ACE_OFFSET_SLOPE_2_BASE_IDX 3
#define mmABM2_DC_ABM1_ACE_OFFSET_SLOPE_3 0x0f0a
#define mmABM2_DC_ABM1_ACE_OFFSET_SLOPE_3_BASE_IDX 3
#define mmABM2_DC_ABM1_ACE_OFFSET_SLOPE_4 0x0f0b
#define mmABM2_DC_ABM1_ACE_OFFSET_SLOPE_4_BASE_IDX 3
#define mmABM2_DC_ABM1_ACE_THRES_12 0x0f0c
#define mmABM2_DC_ABM1_ACE_THRES_12_BASE_IDX 3
#define mmABM2_DC_ABM1_ACE_THRES_34 0x0f0d
#define mmABM2_DC_ABM1_ACE_THRES_34_BASE_IDX 3
#define mmABM2_DC_ABM1_ACE_CNTL_MISC 0x0f0e
#define mmABM2_DC_ABM1_ACE_CNTL_MISC_BASE_IDX 3
#define mmABM2_DC_ABM1_HGLS_REG_READ_PROGRESS 0x0f10
#define mmABM2_DC_ABM1_HGLS_REG_READ_PROGRESS_BASE_IDX 3
#define mmABM2_DC_ABM1_HG_MISC_CTRL 0x0f11
#define mmABM2_DC_ABM1_HG_MISC_CTRL_BASE_IDX 3
#define mmABM2_DC_ABM1_LS_SUM_OF_LUMA 0x0f12
#define mmABM2_DC_ABM1_LS_SUM_OF_LUMA_BASE_IDX 3
#define mmABM2_DC_ABM1_LS_MIN_MAX_LUMA 0x0f13
#define mmABM2_DC_ABM1_LS_MIN_MAX_LUMA_BASE_IDX 3
#define mmABM2_DC_ABM1_LS_FILTERED_MIN_MAX_LUMA 0x0f14
#define mmABM2_DC_ABM1_LS_FILTERED_MIN_MAX_LUMA_BASE_IDX 3
#define mmABM2_DC_ABM1_LS_PIXEL_COUNT 0x0f15
#define mmABM2_DC_ABM1_LS_PIXEL_COUNT_BASE_IDX 3
#define mmABM2_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES 0x0f16
#define mmABM2_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES_BASE_IDX 3
#define mmABM2_DC_ABM1_LS_MIN_PIXEL_VALUE_COUNT 0x0f17
#define mmABM2_DC_ABM1_LS_MIN_PIXEL_VALUE_COUNT_BASE_IDX 3
#define mmABM2_DC_ABM1_LS_MAX_PIXEL_VALUE_COUNT 0x0f18
#define mmABM2_DC_ABM1_LS_MAX_PIXEL_VALUE_COUNT_BASE_IDX 3
#define mmABM2_DC_ABM1_HG_SAMPLE_RATE 0x0f19
#define mmABM2_DC_ABM1_HG_SAMPLE_RATE_BASE_IDX 3
#define mmABM2_DC_ABM1_LS_SAMPLE_RATE 0x0f1a
#define mmABM2_DC_ABM1_LS_SAMPLE_RATE_BASE_IDX 3
#define mmABM2_DC_ABM1_HG_BIN_1_32_SHIFT_FLAG 0x0f1b
#define mmABM2_DC_ABM1_HG_BIN_1_32_SHIFT_FLAG_BASE_IDX 3
#define mmABM2_DC_ABM1_HG_BIN_1_8_SHIFT_INDEX 0x0f1c
#define mmABM2_DC_ABM1_HG_BIN_1_8_SHIFT_INDEX_BASE_IDX 3
#define mmABM2_DC_ABM1_HG_BIN_9_16_SHIFT_INDEX 0x0f1d
#define mmABM2_DC_ABM1_HG_BIN_9_16_SHIFT_INDEX_BASE_IDX 3
#define mmABM2_DC_ABM1_HG_BIN_17_24_SHIFT_INDEX 0x0f1e
#define mmABM2_DC_ABM1_HG_BIN_17_24_SHIFT_INDEX_BASE_IDX 3
#define mmABM2_DC_ABM1_HG_BIN_25_32_SHIFT_INDEX 0x0f1f
#define mmABM2_DC_ABM1_HG_BIN_25_32_SHIFT_INDEX_BASE_IDX 3
#define mmABM2_DC_ABM1_HG_RESULT_1 0x0f20
#define mmABM2_DC_ABM1_HG_RESULT_1_BASE_IDX 3
#define mmABM2_DC_ABM1_HG_RESULT_2 0x0f21
#define mmABM2_DC_ABM1_HG_RESULT_2_BASE_IDX 3
#define mmABM2_DC_ABM1_HG_RESULT_3 0x0f22
#define mmABM2_DC_ABM1_HG_RESULT_3_BASE_IDX 3
#define mmABM2_DC_ABM1_HG_RESULT_4 0x0f23
#define mmABM2_DC_ABM1_HG_RESULT_4_BASE_IDX 3
#define mmABM2_DC_ABM1_HG_RESULT_5 0x0f24
#define mmABM2_DC_ABM1_HG_RESULT_5_BASE_IDX 3
#define mmABM2_DC_ABM1_HG_RESULT_6 0x0f25
#define mmABM2_DC_ABM1_HG_RESULT_6_BASE_IDX 3
#define mmABM2_DC_ABM1_HG_RESULT_7 0x0f26
#define mmABM2_DC_ABM1_HG_RESULT_7_BASE_IDX 3
#define mmABM2_DC_ABM1_HG_RESULT_8 0x0f27
#define mmABM2_DC_ABM1_HG_RESULT_8_BASE_IDX 3
#define mmABM2_DC_ABM1_HG_RESULT_9 0x0f28
#define mmABM2_DC_ABM1_HG_RESULT_9_BASE_IDX 3
#define mmABM2_DC_ABM1_HG_RESULT_10 0x0f29
#define mmABM2_DC_ABM1_HG_RESULT_10_BASE_IDX 3
#define mmABM2_DC_ABM1_HG_RESULT_11 0x0f2a
#define mmABM2_DC_ABM1_HG_RESULT_11_BASE_IDX 3
#define mmABM2_DC_ABM1_HG_RESULT_12 0x0f2b
#define mmABM2_DC_ABM1_HG_RESULT_12_BASE_IDX 3
#define mmABM2_DC_ABM1_HG_RESULT_13 0x0f2c
#define mmABM2_DC_ABM1_HG_RESULT_13_BASE_IDX 3
#define mmABM2_DC_ABM1_HG_RESULT_14 0x0f2d
#define mmABM2_DC_ABM1_HG_RESULT_14_BASE_IDX 3
#define mmABM2_DC_ABM1_HG_RESULT_15 0x0f2e
#define mmABM2_DC_ABM1_HG_RESULT_15_BASE_IDX 3
#define mmABM2_DC_ABM1_HG_RESULT_16 0x0f2f
#define mmABM2_DC_ABM1_HG_RESULT_16_BASE_IDX 3
#define mmABM2_DC_ABM1_HG_RESULT_17 0x0f30
#define mmABM2_DC_ABM1_HG_RESULT_17_BASE_IDX 3
#define mmABM2_DC_ABM1_HG_RESULT_18 0x0f31
#define mmABM2_DC_ABM1_HG_RESULT_18_BASE_IDX 3
#define mmABM2_DC_ABM1_HG_RESULT_19 0x0f32
#define mmABM2_DC_ABM1_HG_RESULT_19_BASE_IDX 3
#define mmABM2_DC_ABM1_HG_RESULT_20 0x0f33
#define mmABM2_DC_ABM1_HG_RESULT_20_BASE_IDX 3
#define mmABM2_DC_ABM1_HG_RESULT_21 0x0f34
#define mmABM2_DC_ABM1_HG_RESULT_21_BASE_IDX 3
#define mmABM2_DC_ABM1_HG_RESULT_22 0x0f35
#define mmABM2_DC_ABM1_HG_RESULT_22_BASE_IDX 3
#define mmABM2_DC_ABM1_HG_RESULT_23 0x0f36
#define mmABM2_DC_ABM1_HG_RESULT_23_BASE_IDX 3
#define mmABM2_DC_ABM1_HG_RESULT_24 0x0f37
#define mmABM2_DC_ABM1_HG_RESULT_24_BASE_IDX 3
#define mmABM2_DC_ABM1_BL_MASTER_LOCK 0x0f38
#define mmABM2_DC_ABM1_BL_MASTER_LOCK_BASE_IDX 3
// addressBlock: dce_dc_opp_abm3_dispdec
// base address: 0x30c
#define mmABM3_BL1_PWM_AMBIENT_LIGHT_LEVEL 0x0f3d
#define mmABM3_BL1_PWM_AMBIENT_LIGHT_LEVEL_BASE_IDX 3
#define mmABM3_BL1_PWM_USER_LEVEL 0x0f3e
#define mmABM3_BL1_PWM_USER_LEVEL_BASE_IDX 3
#define mmABM3_BL1_PWM_TARGET_ABM_LEVEL 0x0f3f
#define mmABM3_BL1_PWM_TARGET_ABM_LEVEL_BASE_IDX 3
#define mmABM3_BL1_PWM_CURRENT_ABM_LEVEL 0x0f40
#define mmABM3_BL1_PWM_CURRENT_ABM_LEVEL_BASE_IDX 3
#define mmABM3_BL1_PWM_FINAL_DUTY_CYCLE 0x0f41
#define mmABM3_BL1_PWM_FINAL_DUTY_CYCLE_BASE_IDX 3
#define mmABM3_BL1_PWM_MINIMUM_DUTY_CYCLE 0x0f42
#define mmABM3_BL1_PWM_MINIMUM_DUTY_CYCLE_BASE_IDX 3
#define mmABM3_BL1_PWM_ABM_CNTL 0x0f43
#define mmABM3_BL1_PWM_ABM_CNTL_BASE_IDX 3
#define mmABM3_BL1_PWM_BL_UPDATE_SAMPLE_RATE 0x0f44
#define mmABM3_BL1_PWM_BL_UPDATE_SAMPLE_RATE_BASE_IDX 3
#define mmABM3_BL1_PWM_GRP2_REG_LOCK 0x0f45
#define mmABM3_BL1_PWM_GRP2_REG_LOCK_BASE_IDX 3
#define mmABM3_DC_ABM1_CNTL 0x0f46
#define mmABM3_DC_ABM1_CNTL_BASE_IDX 3
#define mmABM3_DC_ABM1_IPCSC_COEFF_SEL 0x0f47
#define mmABM3_DC_ABM1_IPCSC_COEFF_SEL_BASE_IDX 3
#define mmABM3_DC_ABM1_ACE_OFFSET_SLOPE_0 0x0f48
#define mmABM3_DC_ABM1_ACE_OFFSET_SLOPE_0_BASE_IDX 3
#define mmABM3_DC_ABM1_ACE_OFFSET_SLOPE_1 0x0f49
#define mmABM3_DC_ABM1_ACE_OFFSET_SLOPE_1_BASE_IDX 3
#define mmABM3_DC_ABM1_ACE_OFFSET_SLOPE_2 0x0f4a
#define mmABM3_DC_ABM1_ACE_OFFSET_SLOPE_2_BASE_IDX 3
#define mmABM3_DC_ABM1_ACE_OFFSET_SLOPE_3 0x0f4b
#define mmABM3_DC_ABM1_ACE_OFFSET_SLOPE_3_BASE_IDX 3
#define mmABM3_DC_ABM1_ACE_OFFSET_SLOPE_4 0x0f4c
#define mmABM3_DC_ABM1_ACE_OFFSET_SLOPE_4_BASE_IDX 3
#define mmABM3_DC_ABM1_ACE_THRES_12 0x0f4d
#define mmABM3_DC_ABM1_ACE_THRES_12_BASE_IDX 3
#define mmABM3_DC_ABM1_ACE_THRES_34 0x0f4e
#define mmABM3_DC_ABM1_ACE_THRES_34_BASE_IDX 3
#define mmABM3_DC_ABM1_ACE_CNTL_MISC 0x0f4f
#define mmABM3_DC_ABM1_ACE_CNTL_MISC_BASE_IDX 3
#define mmABM3_DC_ABM1_HGLS_REG_READ_PROGRESS 0x0f51
#define mmABM3_DC_ABM1_HGLS_REG_READ_PROGRESS_BASE_IDX 3
#define mmABM3_DC_ABM1_HG_MISC_CTRL 0x0f52
#define mmABM3_DC_ABM1_HG_MISC_CTRL_BASE_IDX 3
#define mmABM3_DC_ABM1_LS_SUM_OF_LUMA 0x0f53
#define mmABM3_DC_ABM1_LS_SUM_OF_LUMA_BASE_IDX 3
#define mmABM3_DC_ABM1_LS_MIN_MAX_LUMA 0x0f54
#define mmABM3_DC_ABM1_LS_MIN_MAX_LUMA_BASE_IDX 3
#define mmABM3_DC_ABM1_LS_FILTERED_MIN_MAX_LUMA 0x0f55
#define mmABM3_DC_ABM1_LS_FILTERED_MIN_MAX_LUMA_BASE_IDX 3
#define mmABM3_DC_ABM1_LS_PIXEL_COUNT 0x0f56
#define mmABM3_DC_ABM1_LS_PIXEL_COUNT_BASE_IDX 3
#define mmABM3_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES 0x0f57
#define mmABM3_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES_BASE_IDX 3
#define mmABM3_DC_ABM1_LS_MIN_PIXEL_VALUE_COUNT 0x0f58
#define mmABM3_DC_ABM1_LS_MIN_PIXEL_VALUE_COUNT_BASE_IDX 3
#define mmABM3_DC_ABM1_LS_MAX_PIXEL_VALUE_COUNT 0x0f59
#define mmABM3_DC_ABM1_LS_MAX_PIXEL_VALUE_COUNT_BASE_IDX 3
#define mmABM3_DC_ABM1_HG_SAMPLE_RATE 0x0f5a
#define mmABM3_DC_ABM1_HG_SAMPLE_RATE_BASE_IDX 3
#define mmABM3_DC_ABM1_LS_SAMPLE_RATE 0x0f5b
#define mmABM3_DC_ABM1_LS_SAMPLE_RATE_BASE_IDX 3
#define mmABM3_DC_ABM1_HG_BIN_1_32_SHIFT_FLAG 0x0f5c
#define mmABM3_DC_ABM1_HG_BIN_1_32_SHIFT_FLAG_BASE_IDX 3
#define mmABM3_DC_ABM1_HG_BIN_1_8_SHIFT_INDEX 0x0f5d
#define mmABM3_DC_ABM1_HG_BIN_1_8_SHIFT_INDEX_BASE_IDX 3
#define mmABM3_DC_ABM1_HG_BIN_9_16_SHIFT_INDEX 0x0f5e
#define mmABM3_DC_ABM1_HG_BIN_9_16_SHIFT_INDEX_BASE_IDX 3
#define mmABM3_DC_ABM1_HG_BIN_17_24_SHIFT_INDEX 0x0f5f
#define mmABM3_DC_ABM1_HG_BIN_17_24_SHIFT_INDEX_BASE_IDX 3
#define mmABM3_DC_ABM1_HG_BIN_25_32_SHIFT_INDEX 0x0f60
#define mmABM3_DC_ABM1_HG_BIN_25_32_SHIFT_INDEX_BASE_IDX 3
#define mmABM3_DC_ABM1_HG_RESULT_1 0x0f61
#define mmABM3_DC_ABM1_HG_RESULT_1_BASE_IDX 3
#define mmABM3_DC_ABM1_HG_RESULT_2 0x0f62
#define mmABM3_DC_ABM1_HG_RESULT_2_BASE_IDX 3
#define mmABM3_DC_ABM1_HG_RESULT_3 0x0f63
#define mmABM3_DC_ABM1_HG_RESULT_3_BASE_IDX 3
#define mmABM3_DC_ABM1_HG_RESULT_4 0x0f64
#define mmABM3_DC_ABM1_HG_RESULT_4_BASE_IDX 3
#define mmABM3_DC_ABM1_HG_RESULT_5 0x0f65
#define mmABM3_DC_ABM1_HG_RESULT_5_BASE_IDX 3
#define mmABM3_DC_ABM1_HG_RESULT_6 0x0f66
#define mmABM3_DC_ABM1_HG_RESULT_6_BASE_IDX 3
#define mmABM3_DC_ABM1_HG_RESULT_7 0x0f67
#define mmABM3_DC_ABM1_HG_RESULT_7_BASE_IDX 3
#define mmABM3_DC_ABM1_HG_RESULT_8 0x0f68
#define mmABM3_DC_ABM1_HG_RESULT_8_BASE_IDX 3
#define mmABM3_DC_ABM1_HG_RESULT_9 0x0f69
#define mmABM3_DC_ABM1_HG_RESULT_9_BASE_IDX 3
#define mmABM3_DC_ABM1_HG_RESULT_10 0x0f6a
#define mmABM3_DC_ABM1_HG_RESULT_10_BASE_IDX 3
#define mmABM3_DC_ABM1_HG_RESULT_11 0x0f6b
#define mmABM3_DC_ABM1_HG_RESULT_11_BASE_IDX 3
#define mmABM3_DC_ABM1_HG_RESULT_12 0x0f6c
#define mmABM3_DC_ABM1_HG_RESULT_12_BASE_IDX 3
#define mmABM3_DC_ABM1_HG_RESULT_13 0x0f6d
#define mmABM3_DC_ABM1_HG_RESULT_13_BASE_IDX 3
#define mmABM3_DC_ABM1_HG_RESULT_14 0x0f6e
#define mmABM3_DC_ABM1_HG_RESULT_14_BASE_IDX 3
#define mmABM3_DC_ABM1_HG_RESULT_15 0x0f6f
#define mmABM3_DC_ABM1_HG_RESULT_15_BASE_IDX 3
#define mmABM3_DC_ABM1_HG_RESULT_16 0x0f70
#define mmABM3_DC_ABM1_HG_RESULT_16_BASE_IDX 3
#define mmABM3_DC_ABM1_HG_RESULT_17 0x0f71
#define mmABM3_DC_ABM1_HG_RESULT_17_BASE_IDX 3
#define mmABM3_DC_ABM1_HG_RESULT_18 0x0f72
#define mmABM3_DC_ABM1_HG_RESULT_18_BASE_IDX 3
#define mmABM3_DC_ABM1_HG_RESULT_19 0x0f73
#define mmABM3_DC_ABM1_HG_RESULT_19_BASE_IDX 3
#define mmABM3_DC_ABM1_HG_RESULT_20 0x0f74
#define mmABM3_DC_ABM1_HG_RESULT_20_BASE_IDX 3
#define mmABM3_DC_ABM1_HG_RESULT_21 0x0f75
#define mmABM3_DC_ABM1_HG_RESULT_21_BASE_IDX 3
#define mmABM3_DC_ABM1_HG_RESULT_22 0x0f76
#define mmABM3_DC_ABM1_HG_RESULT_22_BASE_IDX 3
#define mmABM3_DC_ABM1_HG_RESULT_23 0x0f77
#define mmABM3_DC_ABM1_HG_RESULT_23_BASE_IDX 3
#define mmABM3_DC_ABM1_HG_RESULT_24 0x0f78
#define mmABM3_DC_ABM1_HG_RESULT_24_BASE_IDX 3
#define mmABM3_DC_ABM1_BL_MASTER_LOCK 0x0f79
#define mmABM3_DC_ABM1_BL_MASTER_LOCK_BASE_IDX 3
// addressBlock: dce_dc_opp_abm4_dispdec
// base address: 0x410
#define mmABM4_BL1_PWM_AMBIENT_LIGHT_LEVEL 0x0f7e
#define mmABM4_BL1_PWM_AMBIENT_LIGHT_LEVEL_BASE_IDX 3
#define mmABM4_BL1_PWM_USER_LEVEL 0x0f7f
#define mmABM4_BL1_PWM_USER_LEVEL_BASE_IDX 3
#define mmABM4_BL1_PWM_TARGET_ABM_LEVEL 0x0f80
#define mmABM4_BL1_PWM_TARGET_ABM_LEVEL_BASE_IDX 3
#define mmABM4_BL1_PWM_CURRENT_ABM_LEVEL 0x0f81
#define mmABM4_BL1_PWM_CURRENT_ABM_LEVEL_BASE_IDX 3
#define mmABM4_BL1_PWM_FINAL_DUTY_CYCLE 0x0f82
#define mmABM4_BL1_PWM_FINAL_DUTY_CYCLE_BASE_IDX 3
#define mmABM4_BL1_PWM_MINIMUM_DUTY_CYCLE 0x0f83
#define mmABM4_BL1_PWM_MINIMUM_DUTY_CYCLE_BASE_IDX 3
#define mmABM4_BL1_PWM_ABM_CNTL 0x0f84
#define mmABM4_BL1_PWM_ABM_CNTL_BASE_IDX 3
#define mmABM4_BL1_PWM_BL_UPDATE_SAMPLE_RATE 0x0f85
#define mmABM4_BL1_PWM_BL_UPDATE_SAMPLE_RATE_BASE_IDX 3
#define mmABM4_BL1_PWM_GRP2_REG_LOCK 0x0f86
#define mmABM4_BL1_PWM_GRP2_REG_LOCK_BASE_IDX 3
#define mmABM4_DC_ABM1_CNTL 0x0f87
#define mmABM4_DC_ABM1_CNTL_BASE_IDX 3
#define mmABM4_DC_ABM1_IPCSC_COEFF_SEL 0x0f88
#define mmABM4_DC_ABM1_IPCSC_COEFF_SEL_BASE_IDX 3
#define mmABM4_DC_ABM1_ACE_OFFSET_SLOPE_0 0x0f89
#define mmABM4_DC_ABM1_ACE_OFFSET_SLOPE_0_BASE_IDX 3
#define mmABM4_DC_ABM1_ACE_OFFSET_SLOPE_1 0x0f8a
#define mmABM4_DC_ABM1_ACE_OFFSET_SLOPE_1_BASE_IDX 3
#define mmABM4_DC_ABM1_ACE_OFFSET_SLOPE_2 0x0f8b
#define mmABM4_DC_ABM1_ACE_OFFSET_SLOPE_2_BASE_IDX 3
#define mmABM4_DC_ABM1_ACE_OFFSET_SLOPE_3 0x0f8c
#define mmABM4_DC_ABM1_ACE_OFFSET_SLOPE_3_BASE_IDX 3
#define mmABM4_DC_ABM1_ACE_OFFSET_SLOPE_4 0x0f8d
#define mmABM4_DC_ABM1_ACE_OFFSET_SLOPE_4_BASE_IDX 3
#define mmABM4_DC_ABM1_ACE_THRES_12 0x0f8e
#define mmABM4_DC_ABM1_ACE_THRES_12_BASE_IDX 3
#define mmABM4_DC_ABM1_ACE_THRES_34 0x0f8f
#define mmABM4_DC_ABM1_ACE_THRES_34_BASE_IDX 3
#define mmABM4_DC_ABM1_ACE_CNTL_MISC 0x0f90
#define mmABM4_DC_ABM1_ACE_CNTL_MISC_BASE_IDX 3
#define mmABM4_DC_ABM1_HGLS_REG_READ_PROGRESS 0x0f92
#define mmABM4_DC_ABM1_HGLS_REG_READ_PROGRESS_BASE_IDX 3
#define mmABM4_DC_ABM1_HG_MISC_CTRL 0x0f93
#define mmABM4_DC_ABM1_HG_MISC_CTRL_BASE_IDX 3
#define mmABM4_DC_ABM1_LS_SUM_OF_LUMA 0x0f94
#define mmABM4_DC_ABM1_LS_SUM_OF_LUMA_BASE_IDX 3
#define mmABM4_DC_ABM1_LS_MIN_MAX_LUMA 0x0f95
#define mmABM4_DC_ABM1_LS_MIN_MAX_LUMA_BASE_IDX 3
#define mmABM4_DC_ABM1_LS_FILTERED_MIN_MAX_LUMA 0x0f96
#define mmABM4_DC_ABM1_LS_FILTERED_MIN_MAX_LUMA_BASE_IDX 3
#define mmABM4_DC_ABM1_LS_PIXEL_COUNT 0x0f97
#define mmABM4_DC_ABM1_LS_PIXEL_COUNT_BASE_IDX 3
#define mmABM4_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES 0x0f98
#define mmABM4_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES_BASE_IDX 3
#define mmABM4_DC_ABM1_LS_MIN_PIXEL_VALUE_COUNT 0x0f99
#define mmABM4_DC_ABM1_LS_MIN_PIXEL_VALUE_COUNT_BASE_IDX 3
#define mmABM4_DC_ABM1_LS_MAX_PIXEL_VALUE_COUNT 0x0f9a
#define mmABM4_DC_ABM1_LS_MAX_PIXEL_VALUE_COUNT_BASE_IDX 3
#define mmABM4_DC_ABM1_HG_SAMPLE_RATE 0x0f9b
#define mmABM4_DC_ABM1_HG_SAMPLE_RATE_BASE_IDX 3
#define mmABM4_DC_ABM1_LS_SAMPLE_RATE 0x0f9c
#define mmABM4_DC_ABM1_LS_SAMPLE_RATE_BASE_IDX 3
#define mmABM4_DC_ABM1_HG_BIN_1_32_SHIFT_FLAG 0x0f9d
#define mmABM4_DC_ABM1_HG_BIN_1_32_SHIFT_FLAG_BASE_IDX 3
#define mmABM4_DC_ABM1_HG_BIN_1_8_SHIFT_INDEX 0x0f9e
#define mmABM4_DC_ABM1_HG_BIN_1_8_SHIFT_INDEX_BASE_IDX 3
#define mmABM4_DC_ABM1_HG_BIN_9_16_SHIFT_INDEX 0x0f9f
#define mmABM4_DC_ABM1_HG_BIN_9_16_SHIFT_INDEX_BASE_IDX 3
#define mmABM4_DC_ABM1_HG_BIN_17_24_SHIFT_INDEX 0x0fa0
#define mmABM4_DC_ABM1_HG_BIN_17_24_SHIFT_INDEX_BASE_IDX 3
#define mmABM4_DC_ABM1_HG_BIN_25_32_SHIFT_INDEX 0x0fa1
#define mmABM4_DC_ABM1_HG_BIN_25_32_SHIFT_INDEX_BASE_IDX 3
#define mmABM4_DC_ABM1_HG_RESULT_1 0x0fa2
#define mmABM4_DC_ABM1_HG_RESULT_1_BASE_IDX 3
#define mmABM4_DC_ABM1_HG_RESULT_2 0x0fa3
#define mmABM4_DC_ABM1_HG_RESULT_2_BASE_IDX 3
#define mmABM4_DC_ABM1_HG_RESULT_3 0x0fa4
#define mmABM4_DC_ABM1_HG_RESULT_3_BASE_IDX 3
#define mmABM4_DC_ABM1_HG_RESULT_4 0x0fa5
#define mmABM4_DC_ABM1_HG_RESULT_4_BASE_IDX 3
#define mmABM4_DC_ABM1_HG_RESULT_5 0x0fa6
#define mmABM4_DC_ABM1_HG_RESULT_5_BASE_IDX 3
#define mmABM4_DC_ABM1_HG_RESULT_6 0x0fa7
#define mmABM4_DC_ABM1_HG_RESULT_6_BASE_IDX 3
#define mmABM4_DC_ABM1_HG_RESULT_7 0x0fa8
#define mmABM4_DC_ABM1_HG_RESULT_7_BASE_IDX 3
#define mmABM4_DC_ABM1_HG_RESULT_8 0x0fa9
#define mmABM4_DC_ABM1_HG_RESULT_8_BASE_IDX 3
#define mmABM4_DC_ABM1_HG_RESULT_9 0x0faa
#define mmABM4_DC_ABM1_HG_RESULT_9_BASE_IDX 3
#define mmABM4_DC_ABM1_HG_RESULT_10 0x0fab
#define mmABM4_DC_ABM1_HG_RESULT_10_BASE_IDX 3
#define mmABM4_DC_ABM1_HG_RESULT_11 0x0fac
#define mmABM4_DC_ABM1_HG_RESULT_11_BASE_IDX 3
#define mmABM4_DC_ABM1_HG_RESULT_12 0x0fad
#define mmABM4_DC_ABM1_HG_RESULT_12_BASE_IDX 3
#define mmABM4_DC_ABM1_HG_RESULT_13 0x0fae
#define mmABM4_DC_ABM1_HG_RESULT_13_BASE_IDX 3
#define mmABM4_DC_ABM1_HG_RESULT_14 0x0faf
#define mmABM4_DC_ABM1_HG_RESULT_14_BASE_IDX 3
#define mmABM4_DC_ABM1_HG_RESULT_15 0x0fb0
#define mmABM4_DC_ABM1_HG_RESULT_15_BASE_IDX 3
#define mmABM4_DC_ABM1_HG_RESULT_16 0x0fb1
#define mmABM4_DC_ABM1_HG_RESULT_16_BASE_IDX 3
#define mmABM4_DC_ABM1_HG_RESULT_17 0x0fb2
#define mmABM4_DC_ABM1_HG_RESULT_17_BASE_IDX 3
#define mmABM4_DC_ABM1_HG_RESULT_18 0x0fb3
#define mmABM4_DC_ABM1_HG_RESULT_18_BASE_IDX 3
#define mmABM4_DC_ABM1_HG_RESULT_19 0x0fb4
#define mmABM4_DC_ABM1_HG_RESULT_19_BASE_IDX 3
#define mmABM4_DC_ABM1_HG_RESULT_20 0x0fb5
#define mmABM4_DC_ABM1_HG_RESULT_20_BASE_IDX 3
#define mmABM4_DC_ABM1_HG_RESULT_21 0x0fb6
#define mmABM4_DC_ABM1_HG_RESULT_21_BASE_IDX 3
#define mmABM4_DC_ABM1_HG_RESULT_22 0x0fb7
#define mmABM4_DC_ABM1_HG_RESULT_22_BASE_IDX 3
#define mmABM4_DC_ABM1_HG_RESULT_23 0x0fb8
#define mmABM4_DC_ABM1_HG_RESULT_23_BASE_IDX 3
#define mmABM4_DC_ABM1_HG_RESULT_24 0x0fb9
#define mmABM4_DC_ABM1_HG_RESULT_24_BASE_IDX 3
#define mmABM4_DC_ABM1_BL_MASTER_LOCK 0x0fba
#define mmABM4_DC_ABM1_BL_MASTER_LOCK_BASE_IDX 3
// addressBlock: dce_dc_hda_azcontroller_azdec
// base address: 0x0
#define mmCORB_WRITE_POINTER 0x0000
#define mmCORB_WRITE_POINTER_BASE_IDX 0
#define mmCORB_READ_POINTER 0x0000
#define mmCORB_READ_POINTER_BASE_IDX 0
#define mmCORB_CONTROL 0x0001
#define mmCORB_CONTROL_BASE_IDX 0
#define mmCORB_STATUS 0x0001
#define mmCORB_STATUS_BASE_IDX 0
#define mmCORB_SIZE 0x0001
#define mmCORB_SIZE_BASE_IDX 0
#define mmRIRB_LOWER_BASE_ADDRESS 0x0002
#define mmRIRB_LOWER_BASE_ADDRESS_BASE_IDX 0
#define mmRIRB_UPPER_BASE_ADDRESS 0x0003
#define mmRIRB_UPPER_BASE_ADDRESS_BASE_IDX 0
#define mmRIRB_WRITE_POINTER 0x0004
#define mmRIRB_WRITE_POINTER_BASE_IDX 0
#define mmRESPONSE_INTERRUPT_COUNT 0x0004
#define mmRESPONSE_INTERRUPT_COUNT_BASE_IDX 0
#define mmRIRB_CONTROL 0x0005
#define mmRIRB_CONTROL_BASE_IDX 0
#define mmRIRB_STATUS 0x0005
#define mmRIRB_STATUS_BASE_IDX 0
#define mmRIRB_SIZE 0x0005
#define mmRIRB_SIZE_BASE_IDX 0
#define mmIMMEDIATE_COMMAND_OUTPUT_INTERFACE 0x0006
#define mmIMMEDIATE_COMMAND_OUTPUT_INTERFACE_BASE_IDX 0
#define mmIMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA 0x0006
#define mmIMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA_BASE_IDX 0
#define mmIMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX 0x0006
#define mmIMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX_BASE_IDX 0
#define mmIMMEDIATE_RESPONSE_INPUT_INTERFACE 0x0007
#define mmIMMEDIATE_RESPONSE_INPUT_INTERFACE_BASE_IDX 0
#define mmIMMEDIATE_COMMAND_STATUS 0x0008
#define mmIMMEDIATE_COMMAND_STATUS_BASE_IDX 0
#define mmDMA_POSITION_LOWER_BASE_ADDRESS 0x000a
#define mmDMA_POSITION_LOWER_BASE_ADDRESS_BASE_IDX 0
#define mmDMA_POSITION_UPPER_BASE_ADDRESS 0x000b
#define mmDMA_POSITION_UPPER_BASE_ADDRESS_BASE_IDX 0
#define mmWALL_CLOCK_COUNTER_ALIAS 0x074c
#define mmWALL_CLOCK_COUNTER_ALIAS_BASE_IDX 1
// addressBlock: dce_dc_hda_azendpoint_azdec
// base address: 0x0
#define mmAZENDPOINT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA 0x0006
#define mmAZENDPOINT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA_BASE_IDX 0
#define mmAZENDPOINT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX 0x0006
#define mmAZENDPOINT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX_BASE_IDX 0
// addressBlock: dce_dc_hda_azinputendpoint_azdec
// base address: 0x0
#define mmAZENDPOINT_IMMEDIATE_COMMAND_INPUT_INTERFACE_DATA 0x0006
#define mmAZENDPOINT_IMMEDIATE_COMMAND_INPUT_INTERFACE_DATA_BASE_IDX 0
#define mmAZENDPOINT_IMMEDIATE_COMMAND_INPUT_INTERFACE_INDEX 0x0006
#define mmAZENDPOINT_IMMEDIATE_COMMAND_INPUT_INTERFACE_INDEX_BASE_IDX 0
// addressBlock: vga_vgaseqind
// base address: 0x0
#define ixSEQ00 0x0000
#define ixSEQ01 0x0001
#define ixSEQ02 0x0002
#define ixSEQ03 0x0003
#define ixSEQ04 0x0004
// addressBlock: vga_vgacrtind
// base address: 0x0
#define ixCRT00 0x0000
#define ixCRT01 0x0001
#define ixCRT02 0x0002
#define ixCRT03 0x0003
#define ixCRT04 0x0004
#define ixCRT05 0x0005
#define ixCRT06 0x0006
#define ixCRT07 0x0007
#define ixCRT08 0x0008
#define ixCRT09 0x0009
#define ixCRT0A 0x000a
#define ixCRT0B 0x000b
#define ixCRT0C 0x000c
#define ixCRT0D 0x000d
#define ixCRT0E 0x000e
#define ixCRT0F 0x000f
#define ixCRT10 0x0010
#define ixCRT11 0x0011
#define ixCRT12 0x0012
#define ixCRT13 0x0013
#define ixCRT14 0x0014
#define ixCRT15 0x0015
#define ixCRT16 0x0016
#define ixCRT17 0x0017
#define ixCRT18 0x0018
#define ixCRT1E 0x001e
#define ixCRT1F 0x001f
#define ixCRT22 0x0022
// addressBlock: vga_vgagrphind
// base address: 0x0
#define ixGRA00 0x0000
#define ixGRA01 0x0001
#define ixGRA02 0x0002
#define ixGRA03 0x0003
#define ixGRA04 0x0004
#define ixGRA05 0x0005
#define ixGRA06 0x0006
#define ixGRA07 0x0007
#define ixGRA08 0x0008
// addressBlock: vga_vgaattrind
// base address: 0x0
#define ixATTR00 0x0000
#define ixATTR01 0x0001
#define ixATTR02 0x0002
#define ixATTR03 0x0003
#define ixATTR04 0x0004
#define ixATTR05 0x0005
#define ixATTR06 0x0006
#define ixATTR07 0x0007
#define ixATTR08 0x0008
#define ixATTR09 0x0009
#define ixATTR0A 0x000a
#define ixATTR0B 0x000b
#define ixATTR0C 0x000c
#define ixATTR0D 0x000d
#define ixATTR0E 0x000e
#define ixATTR0F 0x000f
#define ixATTR10 0x0010
#define ixATTR11 0x0011
#define ixATTR12 0x0012
#define ixATTR13 0x0013
#define ixATTR14 0x0014
// addressBlock: azendpoint_f2codecind
// base address: 0x0
#define ixAZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT 0x2200
#define ixAZALIA_F2_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x2706
#define ixAZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x270d
#define ixAZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_2 0x270e
#define ixAZALIA_F2_CODEC_CONVERTER_STRIPE_CONTROL 0x2724
#define ixAZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_3 0x273e
#define ixAZALIA_F2_CODEC_CONVERTER_CONTROL_RAMP_RATE 0x2770
#define ixAZALIA_F2_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING 0x2771
#define ixAZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x2f09
#define ixAZALIA_F2_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x2f0a
#define ixAZALIA_F2_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS 0x2f0b
#define ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONNECTION_LIST_ENTRY 0x3702
#define ixAZALIA_F2_CODEC_PIN_CONTROL_WIDGET_CONTROL 0x3707
#define ixAZALIA_F2_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE 0x3708
#define ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE 0x3709
#define ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x371c
#define ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_2 0x371d
#define ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_3 0x371e
#define ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_4 0x371f
#define ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_SPEAKER_ALLOCATION 0x3770
#define ixAZALIA_F2_CODEC_PIN_CONTROL_CHANNEL_ALLOCATION 0x3771
#define ixAZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_INFO 0x3772
#define ixAZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR 0x3776
#define ixAZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_DATA 0x3776
#define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE 0x3777
#define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE 0x3778
#define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE 0x3779
#define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE 0x377a
#define ixAZALIA_F2_CODEC_PIN_CONTROL_LIPSYNC 0x377b
#define ixAZALIA_F2_CODEC_PIN_CONTROL_HBR 0x377c
#define ixAZALIA_F2_CODEC_PIN_CONTROL_AUDIO_SINK_INFO_INDEX 0x3780
#define ixAZALIA_F2_CODEC_PIN_CONTROL_AUDIO_SINK_INFO_DATA 0x3781
#define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE 0x3785
#define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE 0x3786
#define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE 0x3787
#define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE 0x3788
#define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL_MODE 0x3789
#define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_0 0x378a
#define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_1 0x378b
#define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_2 0x378c
#define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_3 0x378d
#define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_4 0x378e
#define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_5 0x378f
#define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_6 0x3790
#define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_7 0x3791
#define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_8 0x3792
#define ixAZALIA_F2_CODEC_PIN_ASSOCIATION_INFO 0x3793
#define ixAZALIA_F2_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS 0x3797
#define ixAZALIA_F2_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x3798
#define ixAZALIA_F2_CODEC_PIN_CONTROL_LPIB 0x3799
#define ixAZALIA_F2_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x379a
#define ixAZALIA_F2_CODEC_PIN_CONTROL_CODING_TYPE 0x379b
#define ixAZALIA_F2_CODEC_PIN_CONTROL_FORMAT_CHANGED 0x379c
#define ixAZALIA_F2_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION 0x379d
#define ixAZALIA_F2_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE 0x379e
#define ixAZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x3f09
#define ixAZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES 0x3f0c
#define ixAZALIA_F2_CODEC_PIN_PARAMETER_CONNECTION_LIST_LENGTH 0x3f0e
// addressBlock: azendpoint_descriptorind
// base address: 0x0
#define ixAUDIO_DESCRIPTOR0 0x0001
#define ixAUDIO_DESCRIPTOR1 0x0002
#define ixAUDIO_DESCRIPTOR2 0x0003
#define ixAUDIO_DESCRIPTOR3 0x0004
#define ixAUDIO_DESCRIPTOR4 0x0005
#define ixAUDIO_DESCRIPTOR5 0x0006
#define ixAUDIO_DESCRIPTOR6 0x0007
#define ixAUDIO_DESCRIPTOR7 0x0008
#define ixAUDIO_DESCRIPTOR8 0x0009
#define ixAUDIO_DESCRIPTOR9 0x000a
#define ixAUDIO_DESCRIPTOR10 0x000b
#define ixAUDIO_DESCRIPTOR11 0x000c
#define ixAUDIO_DESCRIPTOR12 0x000d
#define ixAUDIO_DESCRIPTOR13 0x000e
// addressBlock: azendpoint_sinkinfoind
// base address: 0x0
#define ixAZALIA_F2_CODEC_PIN_CONTROL_MANUFACTURER_ID 0x0000
#define ixAZALIA_F2_CODEC_PIN_CONTROL_PRODUCT_ID 0x0001
#define ixAZALIA_F2_CODEC_PIN_CONTROL_SINK_DESCRIPTION_LEN 0x0002
#define ixAZALIA_F2_CODEC_PIN_CONTROL_PORTID0 0x0003
#define ixAZALIA_F2_CODEC_PIN_CONTROL_PORTID1 0x0004
#define ixSINK_DESCRIPTION0 0x0005
#define ixSINK_DESCRIPTION1 0x0006
#define ixSINK_DESCRIPTION2 0x0007
#define ixSINK_DESCRIPTION3 0x0008
#define ixSINK_DESCRIPTION4 0x0009
#define ixSINK_DESCRIPTION5 0x000a
#define ixSINK_DESCRIPTION6 0x000b
#define ixSINK_DESCRIPTION7 0x000c
#define ixSINK_DESCRIPTION8 0x000d
#define ixSINK_DESCRIPTION9 0x000e
#define ixSINK_DESCRIPTION10 0x000f
#define ixSINK_DESCRIPTION11 0x0010
#define ixSINK_DESCRIPTION12 0x0011
#define ixSINK_DESCRIPTION13 0x0012
#define ixSINK_DESCRIPTION14 0x0013
#define ixSINK_DESCRIPTION15 0x0014
#define ixSINK_DESCRIPTION16 0x0015
#define ixSINK_DESCRIPTION17 0x0016
// addressBlock: azf0controller_azinputcrc0resultind
// base address: 0x0
#define ixAZALIA_INPUT_CRC0_CHANNEL0 0x0000
#define ixAZALIA_INPUT_CRC0_CHANNEL1 0x0001
#define ixAZALIA_INPUT_CRC0_CHANNEL2 0x0002
#define ixAZALIA_INPUT_CRC0_CHANNEL3 0x0003
#define ixAZALIA_INPUT_CRC0_CHANNEL4 0x0004
#define ixAZALIA_INPUT_CRC0_CHANNEL5 0x0005
#define ixAZALIA_INPUT_CRC0_CHANNEL6 0x0006
#define ixAZALIA_INPUT_CRC0_CHANNEL7 0x0007
// addressBlock: azf0controller_azinputcrc1resultind
// base address: 0x0
#define ixAZALIA_INPUT_CRC1_CHANNEL0 0x0000
#define ixAZALIA_INPUT_CRC1_CHANNEL1 0x0001
#define ixAZALIA_INPUT_CRC1_CHANNEL2 0x0002
#define ixAZALIA_INPUT_CRC1_CHANNEL3 0x0003
#define ixAZALIA_INPUT_CRC1_CHANNEL4 0x0004
#define ixAZALIA_INPUT_CRC1_CHANNEL5 0x0005
#define ixAZALIA_INPUT_CRC1_CHANNEL6 0x0006
#define ixAZALIA_INPUT_CRC1_CHANNEL7 0x0007
// addressBlock: azf0controller_azcrc0resultind
// base address: 0x0
#define ixAZALIA_CRC0_CHANNEL0 0x0000
#define ixAZALIA_CRC0_CHANNEL1 0x0001
#define ixAZALIA_CRC0_CHANNEL2 0x0002
#define ixAZALIA_CRC0_CHANNEL3 0x0003
#define ixAZALIA_CRC0_CHANNEL4 0x0004
#define ixAZALIA_CRC0_CHANNEL5 0x0005
#define ixAZALIA_CRC0_CHANNEL6 0x0006
#define ixAZALIA_CRC0_CHANNEL7 0x0007
// addressBlock: azf0controller_azcrc1resultind
// base address: 0x0
#define ixAZALIA_CRC1_CHANNEL0 0x0000
#define ixAZALIA_CRC1_CHANNEL1 0x0001
#define ixAZALIA_CRC1_CHANNEL2 0x0002
#define ixAZALIA_CRC1_CHANNEL3 0x0003
#define ixAZALIA_CRC1_CHANNEL4 0x0004
#define ixAZALIA_CRC1_CHANNEL5 0x0005
#define ixAZALIA_CRC1_CHANNEL6 0x0006
#define ixAZALIA_CRC1_CHANNEL7 0x0007
// addressBlock: azinputendpoint_f2codecind
// base address: 0x0
#define ixAZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT 0x6200
#define ixAZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x6706
#define ixAZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x670d
#define your_sha256_hashITIES 0x6f09
#define your_sha256_hash 0x6f0a
#define ixAZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS 0x6f0b
#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL 0x7707
#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE 0x7708
#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_PIN_SENSE 0x7709
#define your_sha256_hashLT 0x771c
#define your_sha256_hashLT_2 0x771d
#define your_sha256_hashLT_3 0x771e
#define your_sha256_hashLT_4 0x771f
#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION 0x7771
#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL0_ENABLE 0x7777
#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL2_ENABLE 0x7778
#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL4_ENABLE 0x7779
#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL6_ENABLE 0x777a
#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_HBR 0x777c
#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL1_ENABLE 0x7785
#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL3_ENABLE 0x7786
#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL5_ENABLE 0x7787
#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL7_ENABLE 0x7788
#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x7798
#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB 0x7799
#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x779a
#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL 0x779b
#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_INFOFRAME 0x779c
#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_CHANNEL_STATUS_L 0x779d
#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_CHANNEL_STATUS_H 0x779e
#define ixAZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x7f09
#define ixAZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES 0x7f0c
// addressBlock: azroot_f2codecind
// base address: 0x0
#define ixAZALIA_F2_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID 0x0f00
#define ixAZALIA_F2_CODEC_ROOT_PARAMETER_REVISION_ID 0x0f02
#define ixAZALIA_F2_CODEC_ROOT_PARAMETER_SUBORDINATE_NODE_COUNT 0x0f04
#define ixAZALIA_F2_CODEC_FUNCTION_CONTROL_POWER_STATE 0x1705
#define ixAZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID 0x1720
#define ixAZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_2 0x1721
#define ixAZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_3 0x1722
#define ixAZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_4 0x1723
#define ixAZALIA_F2_CODEC_FUNCTION_CONTROL_CONVERTER_SYNCHRONIZATION 0x1770
#define ixAZALIA_F2_CODEC_FUNCTION_CONTROL_RESET 0x17ff
#define ixAZALIA_F2_CODEC_FUNCTION_PARAMETER_SUBORDINATE_NODE_COUNT 0x1f04
#define ixAZALIA_F2_CODEC_FUNCTION_PARAMETER_GROUP_TYPE 0x1f05
#define ixAZALIA_F2_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES 0x1f0a
#define ixAZALIA_F2_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS 0x1f0b
#define ixAZALIA_F2_CODEC_FUNCTION_PARAMETER_POWER_STATES 0x1f0f
// addressBlock: azf0stream0_streamind
// base address: 0x0
#define ixAZF0STREAM0_AZALIA_FIFO_SIZE_CONTROL 0x0000
#define ixAZF0STREAM0_AZALIA_LATENCY_COUNTER_CONTROL 0x0001
#define ixAZF0STREAM0_AZALIA_WORSTCASE_LATENCY_COUNT 0x0002
#define ixAZF0STREAM0_AZALIA_CUMULATIVE_LATENCY_COUNT 0x0003
#define ixAZF0STREAM0_AZALIA_CUMULATIVE_REQUEST_COUNT 0x0004
// addressBlock: azf0stream1_streamind
// base address: 0x0
#define ixAZF0STREAM1_AZALIA_FIFO_SIZE_CONTROL 0x0000
#define ixAZF0STREAM1_AZALIA_LATENCY_COUNTER_CONTROL 0x0001
#define ixAZF0STREAM1_AZALIA_WORSTCASE_LATENCY_COUNT 0x0002
#define ixAZF0STREAM1_AZALIA_CUMULATIVE_LATENCY_COUNT 0x0003
#define ixAZF0STREAM1_AZALIA_CUMULATIVE_REQUEST_COUNT 0x0004
// addressBlock: azf0stream2_streamind
// base address: 0x0
#define ixAZF0STREAM2_AZALIA_FIFO_SIZE_CONTROL 0x0000
#define ixAZF0STREAM2_AZALIA_LATENCY_COUNTER_CONTROL 0x0001
#define ixAZF0STREAM2_AZALIA_WORSTCASE_LATENCY_COUNT 0x0002
#define ixAZF0STREAM2_AZALIA_CUMULATIVE_LATENCY_COUNT 0x0003
#define ixAZF0STREAM2_AZALIA_CUMULATIVE_REQUEST_COUNT 0x0004
// addressBlock: azf0stream3_streamind
// base address: 0x0
#define ixAZF0STREAM3_AZALIA_FIFO_SIZE_CONTROL 0x0000
#define ixAZF0STREAM3_AZALIA_LATENCY_COUNTER_CONTROL 0x0001
#define ixAZF0STREAM3_AZALIA_WORSTCASE_LATENCY_COUNT 0x0002
#define ixAZF0STREAM3_AZALIA_CUMULATIVE_LATENCY_COUNT 0x0003
#define ixAZF0STREAM3_AZALIA_CUMULATIVE_REQUEST_COUNT 0x0004
// addressBlock: azf0stream4_streamind
// base address: 0x0
#define ixAZF0STREAM4_AZALIA_FIFO_SIZE_CONTROL 0x0000
#define ixAZF0STREAM4_AZALIA_LATENCY_COUNTER_CONTROL 0x0001
#define ixAZF0STREAM4_AZALIA_WORSTCASE_LATENCY_COUNT 0x0002
#define ixAZF0STREAM4_AZALIA_CUMULATIVE_LATENCY_COUNT 0x0003
#define ixAZF0STREAM4_AZALIA_CUMULATIVE_REQUEST_COUNT 0x0004
// addressBlock: azf0stream5_streamind
// base address: 0x0
#define ixAZF0STREAM5_AZALIA_FIFO_SIZE_CONTROL 0x0000
#define ixAZF0STREAM5_AZALIA_LATENCY_COUNTER_CONTROL 0x0001
#define ixAZF0STREAM5_AZALIA_WORSTCASE_LATENCY_COUNT 0x0002
#define ixAZF0STREAM5_AZALIA_CUMULATIVE_LATENCY_COUNT 0x0003
#define ixAZF0STREAM5_AZALIA_CUMULATIVE_REQUEST_COUNT 0x0004
// addressBlock: azf0stream6_streamind
// base address: 0x0
#define ixAZF0STREAM6_AZALIA_FIFO_SIZE_CONTROL 0x0000
#define ixAZF0STREAM6_AZALIA_LATENCY_COUNTER_CONTROL 0x0001
#define ixAZF0STREAM6_AZALIA_WORSTCASE_LATENCY_COUNT 0x0002
#define ixAZF0STREAM6_AZALIA_CUMULATIVE_LATENCY_COUNT 0x0003
#define ixAZF0STREAM6_AZALIA_CUMULATIVE_REQUEST_COUNT 0x0004
// addressBlock: azf0stream7_streamind
// base address: 0x0
#define ixAZF0STREAM7_AZALIA_FIFO_SIZE_CONTROL 0x0000
#define ixAZF0STREAM7_AZALIA_LATENCY_COUNTER_CONTROL 0x0001
#define ixAZF0STREAM7_AZALIA_WORSTCASE_LATENCY_COUNT 0x0002
#define ixAZF0STREAM7_AZALIA_CUMULATIVE_LATENCY_COUNT 0x0003
#define ixAZF0STREAM7_AZALIA_CUMULATIVE_REQUEST_COUNT 0x0004
// addressBlock: azf0stream8_streamind
// base address: 0x0
#define ixAZF0STREAM8_AZALIA_FIFO_SIZE_CONTROL 0x0000
#define ixAZF0STREAM8_AZALIA_LATENCY_COUNTER_CONTROL 0x0001
#define ixAZF0STREAM8_AZALIA_WORSTCASE_LATENCY_COUNT 0x0002
#define ixAZF0STREAM8_AZALIA_CUMULATIVE_LATENCY_COUNT 0x0003
#define ixAZF0STREAM8_AZALIA_CUMULATIVE_REQUEST_COUNT 0x0004
// addressBlock: azf0stream9_streamind
// base address: 0x0
#define ixAZF0STREAM9_AZALIA_FIFO_SIZE_CONTROL 0x0000
#define ixAZF0STREAM9_AZALIA_LATENCY_COUNTER_CONTROL 0x0001
#define ixAZF0STREAM9_AZALIA_WORSTCASE_LATENCY_COUNT 0x0002
#define ixAZF0STREAM9_AZALIA_CUMULATIVE_LATENCY_COUNT 0x0003
#define ixAZF0STREAM9_AZALIA_CUMULATIVE_REQUEST_COUNT 0x0004
// addressBlock: azf0stream10_streamind
// base address: 0x0
#define ixAZF0STREAM10_AZALIA_FIFO_SIZE_CONTROL 0x0000
#define ixAZF0STREAM10_AZALIA_LATENCY_COUNTER_CONTROL 0x0001
#define ixAZF0STREAM10_AZALIA_WORSTCASE_LATENCY_COUNT 0x0002
#define ixAZF0STREAM10_AZALIA_CUMULATIVE_LATENCY_COUNT 0x0003
#define ixAZF0STREAM10_AZALIA_CUMULATIVE_REQUEST_COUNT 0x0004
// addressBlock: azf0stream11_streamind
// base address: 0x0
#define ixAZF0STREAM11_AZALIA_FIFO_SIZE_CONTROL 0x0000
#define ixAZF0STREAM11_AZALIA_LATENCY_COUNTER_CONTROL 0x0001
#define ixAZF0STREAM11_AZALIA_WORSTCASE_LATENCY_COUNT 0x0002
#define ixAZF0STREAM11_AZALIA_CUMULATIVE_LATENCY_COUNT 0x0003
#define ixAZF0STREAM11_AZALIA_CUMULATIVE_REQUEST_COUNT 0x0004
// addressBlock: azf0stream12_streamind
// base address: 0x0
#define ixAZF0STREAM12_AZALIA_FIFO_SIZE_CONTROL 0x0000
#define ixAZF0STREAM12_AZALIA_LATENCY_COUNTER_CONTROL 0x0001
#define ixAZF0STREAM12_AZALIA_WORSTCASE_LATENCY_COUNT 0x0002
#define ixAZF0STREAM12_AZALIA_CUMULATIVE_LATENCY_COUNT 0x0003
#define ixAZF0STREAM12_AZALIA_CUMULATIVE_REQUEST_COUNT 0x0004
// addressBlock: azf0stream13_streamind
// base address: 0x0
#define ixAZF0STREAM13_AZALIA_FIFO_SIZE_CONTROL 0x0000
#define ixAZF0STREAM13_AZALIA_LATENCY_COUNTER_CONTROL 0x0001
#define ixAZF0STREAM13_AZALIA_WORSTCASE_LATENCY_COUNT 0x0002
#define ixAZF0STREAM13_AZALIA_CUMULATIVE_LATENCY_COUNT 0x0003
#define ixAZF0STREAM13_AZALIA_CUMULATIVE_REQUEST_COUNT 0x0004
// addressBlock: azf0stream14_streamind
// base address: 0x0
#define ixAZF0STREAM14_AZALIA_FIFO_SIZE_CONTROL 0x0000
#define ixAZF0STREAM14_AZALIA_LATENCY_COUNTER_CONTROL 0x0001
#define ixAZF0STREAM14_AZALIA_WORSTCASE_LATENCY_COUNT 0x0002
#define ixAZF0STREAM14_AZALIA_CUMULATIVE_LATENCY_COUNT 0x0003
#define ixAZF0STREAM14_AZALIA_CUMULATIVE_REQUEST_COUNT 0x0004
// addressBlock: azf0stream15_streamind
// base address: 0x0
#define ixAZF0STREAM15_AZALIA_FIFO_SIZE_CONTROL 0x0000
#define ixAZF0STREAM15_AZALIA_LATENCY_COUNTER_CONTROL 0x0001
#define ixAZF0STREAM15_AZALIA_WORSTCASE_LATENCY_COUNT 0x0002
#define ixAZF0STREAM15_AZALIA_CUMULATIVE_LATENCY_COUNT 0x0003
#define ixAZF0STREAM15_AZALIA_CUMULATIVE_REQUEST_COUNT 0x0004
// addressBlock: azf0endpoint0_endpointind
// base address: 0x0
#define your_sha256_hash_CAPABILITIES 0x0001
#define your_sha256_hashAT 0x0002
#define your_sha256_hash_ID 0x0003
#define your_sha256_hashTER 0x0004
#define your_sha256_hashTS 0x0005
#define your_sha256_hashZE_RATES 0x0006
#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL 0x0007
#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE 0x0008
#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING 0x0009
#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA 0x000c
#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN 0x000d
#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX 0x000e
#define your_sha256_hashILITIES 0x0020
#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES 0x0021
#define your_sha256_hash 0x0022
#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE 0x0023
#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL 0x0024
#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER 0x0025
#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0 0x0028
#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1 0x0029
#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2 0x002a
#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3 0x002b
#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4 0x002c
#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5 0x002d
#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6 0x002e
#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7 0x002f
#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8 0x0030
#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9 0x0031
#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10 0x0032
#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11 0x0033
#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12 0x0034
#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13 0x0035
#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE 0x0036
#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC 0x0037
#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR 0x0038
#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0 0x003a
#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1 0x003b
#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2 0x003c
#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3 0x003d
#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4 0x003e
#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5 0x003f
#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6 0x0040
#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7 0x0041
#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8 0x0042
#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL 0x0054
#define your_sha256_hash_FORCE 0x0055
#define your_sha256_hashON_DEFAULT 0x0056
#define your_sha256_hash 0x0057
#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE 0x0058
#define ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0 0x0059
#define ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1 0x005a
#define ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2 0x005b
#define ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3 0x005c
#define ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4 0x005d
#define ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5 0x005e
#define ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6 0x005f
#define ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7 0x0060
#define ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8 0x0061
#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO 0x0062
#define your_sha256_hashS 0x0063
#define your_sha256_hashL 0x0064
#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_LPIB 0x0065
#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x0066
#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE 0x0067
#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED 0x0068
#define your_sha256_hashNTIFICATION 0x0069
#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE 0x006a
#define ixAZF0ENDPOINT0_AZALIA_F0_AUDIO_ENABLE_STATUS 0x006b
#define ixAZF0ENDPOINT0_AZALIA_F0_AUDIO_ENABLED_INT_STATUS 0x006c
#define ixAZF0ENDPOINT0_AZALIA_F0_AUDIO_DISABLED_INT_STATUS 0x006d
#define ixAZF0ENDPOINT0_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS 0x006e
// addressBlock: azf0endpoint1_endpointind
// base address: 0x0
#define your_sha256_hash_CAPABILITIES 0x0001
#define your_sha256_hashAT 0x0002
#define your_sha256_hash_ID 0x0003
#define your_sha256_hashTER 0x0004
#define your_sha256_hashTS 0x0005
#define your_sha256_hashZE_RATES 0x0006
#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL 0x0007
#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE 0x0008
#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING 0x0009
#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA 0x000c
#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN 0x000d
#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX 0x000e
#define your_sha256_hashILITIES 0x0020
#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES 0x0021
#define your_sha256_hash 0x0022
#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE 0x0023
#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL 0x0024
#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER 0x0025
#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0 0x0028
#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1 0x0029
#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2 0x002a
#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3 0x002b
#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4 0x002c
#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5 0x002d
#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6 0x002e
#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7 0x002f
#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8 0x0030
#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9 0x0031
#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10 0x0032
#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11 0x0033
#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12 0x0034
#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13 0x0035
#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE 0x0036
#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC 0x0037
#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR 0x0038
#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0 0x003a
#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1 0x003b
#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2 0x003c
#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3 0x003d
#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4 0x003e
#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5 0x003f
#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6 0x0040
#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7 0x0041
#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8 0x0042
#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL 0x0054
#define your_sha256_hash_FORCE 0x0055
#define your_sha256_hashON_DEFAULT 0x0056
#define your_sha256_hash 0x0057
#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE 0x0058
#define ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0 0x0059
#define ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1 0x005a
#define ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2 0x005b
#define ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3 0x005c
#define ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4 0x005d
#define ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5 0x005e
#define ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6 0x005f
#define ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7 0x0060
#define ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8 0x0061
#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO 0x0062
#define your_sha256_hashS 0x0063
#define your_sha256_hashL 0x0064
#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_LPIB 0x0065
#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x0066
#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE 0x0067
#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED 0x0068
#define your_sha256_hashNTIFICATION 0x0069
#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE 0x006a
#define ixAZF0ENDPOINT1_AZALIA_F0_AUDIO_ENABLE_STATUS 0x006b
#define ixAZF0ENDPOINT1_AZALIA_F0_AUDIO_ENABLED_INT_STATUS 0x006c
#define ixAZF0ENDPOINT1_AZALIA_F0_AUDIO_DISABLED_INT_STATUS 0x006d
#define ixAZF0ENDPOINT1_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS 0x006e
// addressBlock: azf0endpoint2_endpointind
// base address: 0x0
#define your_sha256_hash_CAPABILITIES 0x0001
#define your_sha256_hashAT 0x0002
#define your_sha256_hash_ID 0x0003
#define your_sha256_hashTER 0x0004
#define your_sha256_hashTS 0x0005
#define your_sha256_hashZE_RATES 0x0006
#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL 0x0007
#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE 0x0008
#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING 0x0009
#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA 0x000c
#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN 0x000d
#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX 0x000e
#define your_sha256_hashILITIES 0x0020
#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES 0x0021
#define your_sha256_hash 0x0022
#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE 0x0023
#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL 0x0024
#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER 0x0025
#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0 0x0028
#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1 0x0029
#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2 0x002a
#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3 0x002b
#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4 0x002c
#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5 0x002d
#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6 0x002e
#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7 0x002f
#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8 0x0030
#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9 0x0031
#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10 0x0032
#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11 0x0033
#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12 0x0034
#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13 0x0035
#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE 0x0036
#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC 0x0037
#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR 0x0038
#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0 0x003a
#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1 0x003b
#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2 0x003c
#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3 0x003d
#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4 0x003e
#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5 0x003f
#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6 0x0040
#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7 0x0041
#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8 0x0042
#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL 0x0054
#define your_sha256_hash_FORCE 0x0055
#define your_sha256_hashON_DEFAULT 0x0056
#define your_sha256_hash 0x0057
#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE 0x0058
#define ixAZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0 0x0059
#define ixAZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1 0x005a
#define ixAZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2 0x005b
#define ixAZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3 0x005c
#define ixAZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4 0x005d
#define ixAZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5 0x005e
#define ixAZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6 0x005f
#define ixAZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7 0x0060
#define ixAZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8 0x0061
#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO 0x0062
#define your_sha256_hashS 0x0063
#define your_sha256_hashL 0x0064
#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_LPIB 0x0065
#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x0066
#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE 0x0067
#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED 0x0068
#define your_sha256_hashNTIFICATION 0x0069
#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE 0x006a
#define ixAZF0ENDPOINT2_AZALIA_F0_AUDIO_ENABLE_STATUS 0x006b
#define ixAZF0ENDPOINT2_AZALIA_F0_AUDIO_ENABLED_INT_STATUS 0x006c
#define ixAZF0ENDPOINT2_AZALIA_F0_AUDIO_DISABLED_INT_STATUS 0x006d
#define ixAZF0ENDPOINT2_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS 0x006e
// addressBlock: azf0endpoint3_endpointind
// base address: 0x0
#define your_sha256_hash_CAPABILITIES 0x0001
#define your_sha256_hashAT 0x0002
#define your_sha256_hash_ID 0x0003
#define your_sha256_hashTER 0x0004
#define your_sha256_hashTS 0x0005
#define your_sha256_hashZE_RATES 0x0006
#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL 0x0007
#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE 0x0008
#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING 0x0009
#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA 0x000c
#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN 0x000d
#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX 0x000e
#define your_sha256_hashILITIES 0x0020
#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES 0x0021
#define your_sha256_hash 0x0022
#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE 0x0023
#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL 0x0024
#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER 0x0025
#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0 0x0028
#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1 0x0029
#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2 0x002a
#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3 0x002b
#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4 0x002c
#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5 0x002d
#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6 0x002e
#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7 0x002f
#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8 0x0030
#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9 0x0031
#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10 0x0032
#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11 0x0033
#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12 0x0034
#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13 0x0035
#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE 0x0036
#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC 0x0037
#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR 0x0038
#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0 0x003a
#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1 0x003b
#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2 0x003c
#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3 0x003d
#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4 0x003e
#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5 0x003f
#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6 0x0040
#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7 0x0041
#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8 0x0042
#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL 0x0054
#define your_sha256_hash_FORCE 0x0055
#define your_sha256_hashON_DEFAULT 0x0056
#define your_sha256_hash 0x0057
#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE 0x0058
#define ixAZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0 0x0059
#define ixAZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1 0x005a
#define ixAZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2 0x005b
#define ixAZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3 0x005c
#define ixAZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4 0x005d
#define ixAZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5 0x005e
#define ixAZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6 0x005f
#define ixAZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7 0x0060
#define ixAZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8 0x0061
#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO 0x0062
#define your_sha256_hashS 0x0063
#define your_sha256_hashL 0x0064
#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_LPIB 0x0065
#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x0066
#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE 0x0067
#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED 0x0068
#define your_sha256_hashNTIFICATION 0x0069
#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE 0x006a
#define ixAZF0ENDPOINT3_AZALIA_F0_AUDIO_ENABLE_STATUS 0x006b
#define ixAZF0ENDPOINT3_AZALIA_F0_AUDIO_ENABLED_INT_STATUS 0x006c
#define ixAZF0ENDPOINT3_AZALIA_F0_AUDIO_DISABLED_INT_STATUS 0x006d
#define ixAZF0ENDPOINT3_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS 0x006e
// addressBlock: azf0endpoint4_endpointind
// base address: 0x0
#define your_sha256_hash_CAPABILITIES 0x0001
#define your_sha256_hashAT 0x0002
#define your_sha256_hash_ID 0x0003
#define your_sha256_hashTER 0x0004
#define your_sha256_hashTS 0x0005
#define your_sha256_hashZE_RATES 0x0006
#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL 0x0007
#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE 0x0008
#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING 0x0009
#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA 0x000c
#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN 0x000d
#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX 0x000e
#define your_sha256_hashILITIES 0x0020
#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES 0x0021
#define your_sha256_hash 0x0022
#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE 0x0023
#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL 0x0024
#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER 0x0025
#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0 0x0028
#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1 0x0029
#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2 0x002a
#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3 0x002b
#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4 0x002c
#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5 0x002d
#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6 0x002e
#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7 0x002f
#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8 0x0030
#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9 0x0031
#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10 0x0032
#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11 0x0033
#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12 0x0034
#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13 0x0035
#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE 0x0036
#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC 0x0037
#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR 0x0038
#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0 0x003a
#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1 0x003b
#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2 0x003c
#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3 0x003d
#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4 0x003e
#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5 0x003f
#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6 0x0040
#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7 0x0041
#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8 0x0042
#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL 0x0054
#define your_sha256_hash_FORCE 0x0055
#define your_sha256_hashON_DEFAULT 0x0056
#define your_sha256_hash 0x0057
#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE 0x0058
#define ixAZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0 0x0059
#define ixAZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1 0x005a
#define ixAZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2 0x005b
#define ixAZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3 0x005c
#define ixAZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4 0x005d
#define ixAZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5 0x005e
#define ixAZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6 0x005f
#define ixAZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7 0x0060
#define ixAZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8 0x0061
#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO 0x0062
#define your_sha256_hashS 0x0063
#define your_sha256_hashL 0x0064
#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_LPIB 0x0065
#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x0066
#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE 0x0067
#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED 0x0068
#define your_sha256_hashNTIFICATION 0x0069
#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE 0x006a
#define ixAZF0ENDPOINT4_AZALIA_F0_AUDIO_ENABLE_STATUS 0x006b
#define ixAZF0ENDPOINT4_AZALIA_F0_AUDIO_ENABLED_INT_STATUS 0x006c
#define ixAZF0ENDPOINT4_AZALIA_F0_AUDIO_DISABLED_INT_STATUS 0x006d
#define ixAZF0ENDPOINT4_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS 0x006e
// addressBlock: azf0endpoint5_endpointind
// base address: 0x0
#define your_sha256_hash_CAPABILITIES 0x0001
#define your_sha256_hashAT 0x0002
#define your_sha256_hash_ID 0x0003
#define your_sha256_hashTER 0x0004
#define your_sha256_hashTS 0x0005
#define your_sha256_hashZE_RATES 0x0006
#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL 0x0007
#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE 0x0008
#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING 0x0009
#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA 0x000c
#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN 0x000d
#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX 0x000e
#define your_sha256_hashILITIES 0x0020
#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES 0x0021
#define your_sha256_hash 0x0022
#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE 0x0023
#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL 0x0024
#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER 0x0025
#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0 0x0028
#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1 0x0029
#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2 0x002a
#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3 0x002b
#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4 0x002c
#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5 0x002d
#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6 0x002e
#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7 0x002f
#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8 0x0030
#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9 0x0031
#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10 0x0032
#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11 0x0033
#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12 0x0034
#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13 0x0035
#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE 0x0036
#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC 0x0037
#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR 0x0038
#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0 0x003a
#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1 0x003b
#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2 0x003c
#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3 0x003d
#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4 0x003e
#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5 0x003f
#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6 0x0040
#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7 0x0041
#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8 0x0042
#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL 0x0054
#define your_sha256_hash_FORCE 0x0055
#define your_sha256_hashON_DEFAULT 0x0056
#define your_sha256_hash 0x0057
#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE 0x0058
#define ixAZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0 0x0059
#define ixAZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1 0x005a
#define ixAZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2 0x005b
#define ixAZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3 0x005c
#define ixAZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4 0x005d
#define ixAZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5 0x005e
#define ixAZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6 0x005f
#define ixAZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7 0x0060
#define ixAZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8 0x0061
#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO 0x0062
#define your_sha256_hashS 0x0063
#define your_sha256_hashL 0x0064
#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_LPIB 0x0065
#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x0066
#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE 0x0067
#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED 0x0068
#define your_sha256_hashNTIFICATION 0x0069
#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE 0x006a
#define ixAZF0ENDPOINT5_AZALIA_F0_AUDIO_ENABLE_STATUS 0x006b
#define ixAZF0ENDPOINT5_AZALIA_F0_AUDIO_ENABLED_INT_STATUS 0x006c
#define ixAZF0ENDPOINT5_AZALIA_F0_AUDIO_DISABLED_INT_STATUS 0x006d
#define ixAZF0ENDPOINT5_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS 0x006e
// addressBlock: azf0endpoint6_endpointind
// base address: 0x0
#define your_sha256_hash_CAPABILITIES 0x0001
#define your_sha256_hashAT 0x0002
#define your_sha256_hash_ID 0x0003
#define your_sha256_hashTER 0x0004
#define your_sha256_hashTS 0x0005
#define your_sha256_hashZE_RATES 0x0006
#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL 0x0007
#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE 0x0008
#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING 0x0009
#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA 0x000c
#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN 0x000d
#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX 0x000e
#define your_sha256_hashILITIES 0x0020
#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES 0x0021
#define your_sha256_hash 0x0022
#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE 0x0023
#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL 0x0024
#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER 0x0025
#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0 0x0028
#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1 0x0029
#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2 0x002a
#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3 0x002b
#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4 0x002c
#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5 0x002d
#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6 0x002e
#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7 0x002f
#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8 0x0030
#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9 0x0031
#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10 0x0032
#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11 0x0033
#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12 0x0034
#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13 0x0035
#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE 0x0036
#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC 0x0037
#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR 0x0038
#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0 0x003a
#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1 0x003b
#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2 0x003c
#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3 0x003d
#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4 0x003e
#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5 0x003f
#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6 0x0040
#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7 0x0041
#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8 0x0042
#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL 0x0054
#define your_sha256_hash_FORCE 0x0055
#define your_sha256_hashON_DEFAULT 0x0056
#define your_sha256_hash 0x0057
#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE 0x0058
#define ixAZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0 0x0059
#define ixAZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1 0x005a
#define ixAZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2 0x005b
#define ixAZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3 0x005c
#define ixAZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4 0x005d
#define ixAZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5 0x005e
#define ixAZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6 0x005f
#define ixAZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7 0x0060
#define ixAZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8 0x0061
#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO 0x0062
#define your_sha256_hashS 0x0063
#define your_sha256_hashL 0x0064
#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_LPIB 0x0065
#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x0066
#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE 0x0067
#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED 0x0068
#define your_sha256_hashNTIFICATION 0x0069
#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE 0x006a
#define ixAZF0ENDPOINT6_AZALIA_F0_AUDIO_ENABLE_STATUS 0x006b
#define ixAZF0ENDPOINT6_AZALIA_F0_AUDIO_ENABLED_INT_STATUS 0x006c
#define ixAZF0ENDPOINT6_AZALIA_F0_AUDIO_DISABLED_INT_STATUS 0x006d
#define ixAZF0ENDPOINT6_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS 0x006e
// addressBlock: azf0endpoint7_endpointind
// base address: 0x0
#define your_sha256_hash_CAPABILITIES 0x0001
#define your_sha256_hashAT 0x0002
#define your_sha256_hash_ID 0x0003
#define your_sha256_hashTER 0x0004
#define your_sha256_hashTS 0x0005
#define your_sha256_hashZE_RATES 0x0006
#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL 0x0007
#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE 0x0008
#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING 0x0009
#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA 0x000c
#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN 0x000d
#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX 0x000e
#define your_sha256_hashILITIES 0x0020
#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES 0x0021
#define your_sha256_hash 0x0022
#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE 0x0023
#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL 0x0024
#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER 0x0025
#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0 0x0028
#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1 0x0029
#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2 0x002a
#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3 0x002b
#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4 0x002c
#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5 0x002d
#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6 0x002e
#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7 0x002f
#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8 0x0030
#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9 0x0031
#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10 0x0032
#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11 0x0033
#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12 0x0034
#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13 0x0035
#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE 0x0036
#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC 0x0037
#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR 0x0038
#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0 0x003a
#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1 0x003b
#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2 0x003c
#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3 0x003d
#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4 0x003e
#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5 0x003f
#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6 0x0040
#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7 0x0041
#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8 0x0042
#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL 0x0054
#define your_sha256_hash_FORCE 0x0055
#define your_sha256_hashON_DEFAULT 0x0056
#define your_sha256_hash 0x0057
#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE 0x0058
#define ixAZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0 0x0059
#define ixAZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1 0x005a
#define ixAZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2 0x005b
#define ixAZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3 0x005c
#define ixAZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4 0x005d
#define ixAZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5 0x005e
#define ixAZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6 0x005f
#define ixAZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7 0x0060
#define ixAZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8 0x0061
#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO 0x0062
#define your_sha256_hashS 0x0063
#define your_sha256_hashL 0x0064
#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_LPIB 0x0065
#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x0066
#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE 0x0067
#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED 0x0068
#define your_sha256_hashNTIFICATION 0x0069
#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE 0x006a
#define ixAZF0ENDPOINT7_AZALIA_F0_AUDIO_ENABLE_STATUS 0x006b
#define ixAZF0ENDPOINT7_AZALIA_F0_AUDIO_ENABLED_INT_STATUS 0x006c
#define ixAZF0ENDPOINT7_AZALIA_F0_AUDIO_DISABLED_INT_STATUS 0x006d
#define ixAZF0ENDPOINT7_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS 0x006e
// addressBlock: azf0inputendpoint0_inputendpointind
// base address: 0x0
#define your_sha256_hashUDIO_WIDGET_CAPABILITIES 0x0001
#define your_sha256_hashVERTER_FORMAT 0x0002
#define your_sha256_hashNNEL_STREAM_ID 0x0003
#define your_sha256_hashITAL_CONVERTER 0x0004
#define your_sha256_hashTREAM_FORMATS 0x0005
#define your_sha256_hashUPPORTED_SIZE_RATES 0x0006
#define your_sha256_hashIDGET_CAPABILITIES 0x0020
#define your_sha256_hashITIES 0x0021
#define your_sha256_hashED_RESPONSE 0x0022
#define your_sha256_hashINPUT_PIN_SENSE 0x0023
#define your_sha256_hashNTROL 0x0024
#define your_sha256_hashNEL_ENABLE 0x0036
#define your_sha256_hashNEL_ENABLE2 0x0037
#define your_sha256_hashHBR 0x0038
#define your_sha256_hashLLOCATION 0x0053
#define your_sha256_hashCONTROL 0x0054
#define your_sha256_hashED_RESPONSE_FORCE 0x0055
#define your_sha256_hashCONFIGURATION_DEFAULT 0x0056
#define your_sha256_hashSHOT_CONTROL 0x0064
#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB 0x0065
#define your_sha256_hashR_SNAPSHOT 0x0066
#define your_sha256_hashTUS_CONTROL 0x0067
#define your_sha256_hash 0x0068
// addressBlock: azf0inputendpoint1_inputendpointind
// base address: 0x0
#define your_sha256_hashUDIO_WIDGET_CAPABILITIES 0x0001
#define your_sha256_hashVERTER_FORMAT 0x0002
#define your_sha256_hashNNEL_STREAM_ID 0x0003
#define your_sha256_hashITAL_CONVERTER 0x0004
#define your_sha256_hashTREAM_FORMATS 0x0005
#define your_sha256_hashUPPORTED_SIZE_RATES 0x0006
#define your_sha256_hashIDGET_CAPABILITIES 0x0020
#define your_sha256_hashITIES 0x0021
#define your_sha256_hashED_RESPONSE 0x0022
#define your_sha256_hashINPUT_PIN_SENSE 0x0023
#define your_sha256_hashNTROL 0x0024
#define your_sha256_hashNEL_ENABLE 0x0036
#define your_sha256_hashNEL_ENABLE2 0x0037
#define your_sha256_hashHBR 0x0038
#define your_sha256_hashLLOCATION 0x0053
#define your_sha256_hashCONTROL 0x0054
#define your_sha256_hashED_RESPONSE_FORCE 0x0055
#define your_sha256_hashCONFIGURATION_DEFAULT 0x0056
#define your_sha256_hashSHOT_CONTROL 0x0064
#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB 0x0065
#define your_sha256_hashR_SNAPSHOT 0x0066
#define your_sha256_hashTUS_CONTROL 0x0067
#define your_sha256_hash 0x0068
// addressBlock: azf0inputendpoint2_inputendpointind
// base address: 0x0
#define your_sha256_hashUDIO_WIDGET_CAPABILITIES 0x0001
#define your_sha256_hashVERTER_FORMAT 0x0002
#define your_sha256_hashNNEL_STREAM_ID 0x0003
#define your_sha256_hashITAL_CONVERTER 0x0004
#define your_sha256_hashTREAM_FORMATS 0x0005
#define your_sha256_hashUPPORTED_SIZE_RATES 0x0006
#define your_sha256_hashIDGET_CAPABILITIES 0x0020
#define your_sha256_hashITIES 0x0021
#define your_sha256_hashED_RESPONSE 0x0022
#define your_sha256_hashINPUT_PIN_SENSE 0x0023
#define your_sha256_hashNTROL 0x0024
#define your_sha256_hashNEL_ENABLE 0x0036
#define your_sha256_hashNEL_ENABLE2 0x0037
#define your_sha256_hashHBR 0x0038
#define your_sha256_hashLLOCATION 0x0053
#define your_sha256_hashCONTROL 0x0054
#define your_sha256_hashED_RESPONSE_FORCE 0x0055
#define your_sha256_hashCONFIGURATION_DEFAULT 0x0056
#define your_sha256_hashSHOT_CONTROL 0x0064
#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB 0x0065
#define your_sha256_hashR_SNAPSHOT 0x0066
#define your_sha256_hashTUS_CONTROL 0x0067
#define your_sha256_hash 0x0068
// addressBlock: azf0inputendpoint3_inputendpointind
// base address: 0x0
#define your_sha256_hashUDIO_WIDGET_CAPABILITIES 0x0001
#define your_sha256_hashVERTER_FORMAT 0x0002
#define your_sha256_hashNNEL_STREAM_ID 0x0003
#define your_sha256_hashITAL_CONVERTER 0x0004
#define your_sha256_hashTREAM_FORMATS 0x0005
#define your_sha256_hashUPPORTED_SIZE_RATES 0x0006
#define your_sha256_hashIDGET_CAPABILITIES 0x0020
#define your_sha256_hashITIES 0x0021
#define your_sha256_hashED_RESPONSE 0x0022
#define your_sha256_hashINPUT_PIN_SENSE 0x0023
#define your_sha256_hashNTROL 0x0024
#define your_sha256_hashNEL_ENABLE 0x0036
#define your_sha256_hashNEL_ENABLE2 0x0037
#define your_sha256_hashHBR 0x0038
#define your_sha256_hashLLOCATION 0x0053
#define your_sha256_hashCONTROL 0x0054
#define your_sha256_hashED_RESPONSE_FORCE 0x0055
#define your_sha256_hashCONFIGURATION_DEFAULT 0x0056
#define your_sha256_hashSHOT_CONTROL 0x0064
#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB 0x0065
#define your_sha256_hashR_SNAPSHOT 0x0066
#define your_sha256_hashTUS_CONTROL 0x0067
#define your_sha256_hash 0x0068
// addressBlock: azf0inputendpoint4_inputendpointind
// base address: 0x0
#define your_sha256_hashUDIO_WIDGET_CAPABILITIES 0x0001
#define your_sha256_hashVERTER_FORMAT 0x0002
#define your_sha256_hashNNEL_STREAM_ID 0x0003
#define your_sha256_hashITAL_CONVERTER 0x0004
#define your_sha256_hashTREAM_FORMATS 0x0005
#define your_sha256_hashUPPORTED_SIZE_RATES 0x0006
#define your_sha256_hashIDGET_CAPABILITIES 0x0020
#define your_sha256_hashITIES 0x0021
#define your_sha256_hashED_RESPONSE 0x0022
#define your_sha256_hashINPUT_PIN_SENSE 0x0023
#define your_sha256_hashNTROL 0x0024
#define your_sha256_hashNEL_ENABLE 0x0036
#define your_sha256_hashNEL_ENABLE2 0x0037
#define your_sha256_hashHBR 0x0038
#define your_sha256_hashLLOCATION 0x0053
#define your_sha256_hashCONTROL 0x0054
#define your_sha256_hashED_RESPONSE_FORCE 0x0055
#define your_sha256_hashCONFIGURATION_DEFAULT 0x0056
#define your_sha256_hashSHOT_CONTROL 0x0064
#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB 0x0065
#define your_sha256_hashR_SNAPSHOT 0x0066
#define your_sha256_hashTUS_CONTROL 0x0067
#define your_sha256_hash 0x0068
// addressBlock: azf0inputendpoint5_inputendpointind
// base address: 0x0
#define your_sha256_hashUDIO_WIDGET_CAPABILITIES 0x0001
#define your_sha256_hashVERTER_FORMAT 0x0002
#define your_sha256_hashNNEL_STREAM_ID 0x0003
#define your_sha256_hashITAL_CONVERTER 0x0004
#define your_sha256_hashTREAM_FORMATS 0x0005
#define your_sha256_hashUPPORTED_SIZE_RATES 0x0006
#define your_sha256_hashIDGET_CAPABILITIES 0x0020
#define your_sha256_hashITIES 0x0021
#define your_sha256_hashED_RESPONSE 0x0022
#define your_sha256_hashINPUT_PIN_SENSE 0x0023
#define your_sha256_hashNTROL 0x0024
#define your_sha256_hashNEL_ENABLE 0x0036
#define your_sha256_hashNEL_ENABLE2 0x0037
#define your_sha256_hashHBR 0x0038
#define your_sha256_hashLLOCATION 0x0053
#define your_sha256_hashCONTROL 0x0054
#define your_sha256_hashED_RESPONSE_FORCE 0x0055
#define your_sha256_hashCONFIGURATION_DEFAULT 0x0056
#define your_sha256_hashSHOT_CONTROL 0x0064
#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB 0x0065
#define your_sha256_hashR_SNAPSHOT 0x0066
#define your_sha256_hashTUS_CONTROL 0x0067
#define your_sha256_hash 0x0068
// addressBlock: azf0inputendpoint6_inputendpointind
// base address: 0x0
#define your_sha256_hashUDIO_WIDGET_CAPABILITIES 0x0001
#define your_sha256_hashVERTER_FORMAT 0x0002
#define your_sha256_hashNNEL_STREAM_ID 0x0003
#define your_sha256_hashITAL_CONVERTER 0x0004
#define your_sha256_hashTREAM_FORMATS 0x0005
#define your_sha256_hashUPPORTED_SIZE_RATES 0x0006
#define your_sha256_hashIDGET_CAPABILITIES 0x0020
#define your_sha256_hashITIES 0x0021
#define your_sha256_hashED_RESPONSE 0x0022
#define your_sha256_hashINPUT_PIN_SENSE 0x0023
#define your_sha256_hashNTROL 0x0024
#define your_sha256_hashNEL_ENABLE 0x0036
#define your_sha256_hashNEL_ENABLE2 0x0037
#define your_sha256_hashHBR 0x0038
#define your_sha256_hashLLOCATION 0x0053
#define your_sha256_hashCONTROL 0x0054
#define your_sha256_hashED_RESPONSE_FORCE 0x0055
#define your_sha256_hashCONFIGURATION_DEFAULT 0x0056
#define your_sha256_hashSHOT_CONTROL 0x0064
#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB 0x0065
#define your_sha256_hashR_SNAPSHOT 0x0066
#define your_sha256_hashTUS_CONTROL 0x0067
#define your_sha256_hash 0x0068
// addressBlock: azf0inputendpoint7_inputendpointind
// base address: 0x0
#define your_sha256_hashUDIO_WIDGET_CAPABILITIES 0x0001
#define your_sha256_hashVERTER_FORMAT 0x0002
#define your_sha256_hashNNEL_STREAM_ID 0x0003
#define your_sha256_hashITAL_CONVERTER 0x0004
#define your_sha256_hashTREAM_FORMATS 0x0005
#define your_sha256_hashUPPORTED_SIZE_RATES 0x0006
#define your_sha256_hashIDGET_CAPABILITIES 0x0020
#define your_sha256_hashITIES 0x0021
#define your_sha256_hashED_RESPONSE 0x0022
#define your_sha256_hashINPUT_PIN_SENSE 0x0023
#define your_sha256_hashNTROL 0x0024
#define your_sha256_hashNEL_ENABLE 0x0036
#define your_sha256_hashNEL_ENABLE2 0x0037
#define your_sha256_hashHBR 0x0038
#define your_sha256_hashLLOCATION 0x0053
#define your_sha256_hashCONTROL 0x0054
#define your_sha256_hashED_RESPONSE_FORCE 0x0055
#define your_sha256_hashCONFIGURATION_DEFAULT 0x0056
#define your_sha256_hashSHOT_CONTROL 0x0064
#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB 0x0065
#define your_sha256_hashR_SNAPSHOT 0x0066
#define your_sha256_hashTUS_CONTROL 0x0067
#define your_sha256_hash 0x0068
#endif
```
|
```c++
//===-- DNBLog.cpp ----------------------------------------------*- C++ -*-===//
//
// See path_to_url for license information.
//
//===your_sha256_hash------===//
//
// Created by Greg Clayton on 6/18/07.
//
//===your_sha256_hash------===//
#include "DNBLog.h"
static int g_debug = 0;
static int g_verbose = 0;
#if defined(DNBLOG_ENABLED)
#include "PThreadMutex.h"
#include <cstdarg>
#include <cstdio>
#include <cstdlib>
#include <mach/mach.h>
#include <pthread.h>
#include <sys/time.h>
#include <unistd.h>
uint32_t g_log_bits = 0;
static DNBCallbackLog g_log_callback = NULL;
static void *g_log_baton = NULL;
int DNBLogGetDebug() { return g_debug; }
void DNBLogSetDebug(int g) { g_debug = g; }
int DNBLogGetVerbose() { return g_verbose; }
void DNBLogSetVerbose(int v) { g_verbose = v; }
bool DNBLogCheckLogBit(uint32_t bit) { return (g_log_bits & bit) != 0; }
uint32_t DNBLogSetLogMask(uint32_t mask) {
uint32_t old = g_log_bits;
g_log_bits = mask;
return old;
}
uint32_t DNBLogGetLogMask() { return g_log_bits; }
void DNBLogSetLogCallback(DNBCallbackLog callback, void *baton) {
g_log_callback = callback;
g_log_baton = baton;
}
DNBCallbackLog DNBLogGetLogCallback() { return g_log_callback; }
bool DNBLogEnabled() { return g_log_callback != NULL; }
bool DNBLogEnabledForAny(uint32_t mask) {
if (g_log_callback)
return (g_log_bits & mask) != 0;
return false;
}
static inline void _DNBLogVAPrintf(uint32_t flags, const char *format,
va_list args) {
static PThreadMutex g_LogThreadedMutex(PTHREAD_MUTEX_RECURSIVE);
PTHREAD_MUTEX_LOCKER(locker, g_LogThreadedMutex);
if (g_log_callback)
g_log_callback(g_log_baton, flags, format, args);
}
void _DNBLog(uint32_t flags, const char *format, ...) {
va_list args;
va_start(args, format);
_DNBLogVAPrintf(flags, format, args);
va_end(args);
}
// Print debug strings if and only if the global g_debug is set to
// a non-zero value.
void _DNBLogDebug(const char *format, ...) {
if (DNBLogEnabled() && g_debug) {
va_list args;
va_start(args, format);
_DNBLogVAPrintf(DNBLOG_FLAG_DEBUG, format, args);
va_end(args);
}
}
// Print debug strings if and only if the global g_debug is set to
// a non-zero value.
void _DNBLogDebugVerbose(const char *format, ...) {
if (DNBLogEnabled() && g_debug && g_verbose) {
va_list args;
va_start(args, format);
_DNBLogVAPrintf(DNBLOG_FLAG_DEBUG | DNBLOG_FLAG_VERBOSE, format, args);
va_end(args);
}
}
static uint32_t g_message_id = 0;
// Prefix the formatted log string with process and thread IDs and
// suffix it with a newline.
void _DNBLogThreaded(const char *format, ...) {
if (DNBLogEnabled()) {
// PTHREAD_MUTEX_LOCKER(locker, GetLogThreadedMutex());
char *arg_msg = NULL;
va_list args;
va_start(args, format);
::vasprintf(&arg_msg, format, args);
va_end(args);
if (arg_msg != NULL) {
static struct timeval g_timeval = {0, 0};
static struct timeval tv;
static struct timeval delta;
gettimeofday(&tv, NULL);
if (g_timeval.tv_sec == 0) {
delta.tv_sec = 0;
delta.tv_usec = 0;
} else {
timersub(&tv, &g_timeval, &delta);
}
g_timeval = tv;
// Calling "mach_port_deallocate()" bumps the reference count on the
// thread
// port, so we need to deallocate it. mach_task_self() doesn't bump the
// ref
// count.
thread_port_t thread_self = mach_thread_self();
_DNBLog(DNBLOG_FLAG_THREADED, "%u +%lu.%06u sec [%4.4x/%4.4x]: %s",
++g_message_id, delta.tv_sec, delta.tv_usec, getpid(),
thread_self, arg_msg);
mach_port_deallocate(mach_task_self(), thread_self);
free(arg_msg);
}
}
}
// Prefix the formatted log string with process and thread IDs and
// suffix it with a newline.
void _DNBLogThreadedIf(uint32_t log_bit, const char *format, ...) {
if (DNBLogEnabled() && (log_bit & g_log_bits) == log_bit) {
// PTHREAD_MUTEX_LOCKER(locker, GetLogThreadedMutex());
char *arg_msg = NULL;
va_list args;
va_start(args, format);
::vasprintf(&arg_msg, format, args);
va_end(args);
if (arg_msg != NULL) {
static struct timeval g_timeval = {0, 0};
static struct timeval tv;
static struct timeval delta;
gettimeofday(&tv, NULL);
if (g_timeval.tv_sec == 0) {
delta.tv_sec = 0;
delta.tv_usec = 0;
} else {
timersub(&tv, &g_timeval, &delta);
}
g_timeval = tv;
// Calling "mach_port_deallocate()" bumps the reference count on the
// thread
// port, so we need to deallocate it. mach_task_self() doesn't bump the
// ref
// count.
thread_port_t thread_self = mach_thread_self();
_DNBLog(DNBLOG_FLAG_THREADED, "%u +%lu.%06u sec [%4.4x/%4.4x]: %s",
++g_message_id, delta.tv_sec, delta.tv_usec, getpid(),
thread_self, arg_msg);
mach_port_deallocate(mach_task_self(), thread_self);
free(arg_msg);
}
}
}
// Printing of errors that are not fatal.
void _DNBLogError(const char *format, ...) {
if (DNBLogEnabled()) {
char *arg_msg = NULL;
va_list args;
va_start(args, format);
::vasprintf(&arg_msg, format, args);
va_end(args);
if (arg_msg != NULL) {
_DNBLog(DNBLOG_FLAG_ERROR, "error: %s", arg_msg);
free(arg_msg);
}
}
}
// Printing of errors that ARE fatal. Exit with ERR exit code
// immediately.
void _DNBLogFatalError(int err, const char *format, ...) {
if (DNBLogEnabled()) {
char *arg_msg = NULL;
va_list args;
va_start(args, format);
::vasprintf(&arg_msg, format, args);
va_end(args);
if (arg_msg != NULL) {
_DNBLog(DNBLOG_FLAG_ERROR | DNBLOG_FLAG_FATAL, "error: %s", arg_msg);
free(arg_msg);
}
::exit(err);
}
}
// Printing of warnings that are not fatal only if verbose mode is
// enabled.
void _DNBLogVerbose(const char *format, ...) {
if (DNBLogEnabled() && g_verbose) {
va_list args;
va_start(args, format);
_DNBLogVAPrintf(DNBLOG_FLAG_VERBOSE, format, args);
va_end(args);
}
}
// Printing of warnings that are not fatal only if verbose mode is
// enabled.
void _DNBLogWarningVerbose(const char *format, ...) {
if (DNBLogEnabled() && g_verbose) {
char *arg_msg = NULL;
va_list args;
va_start(args, format);
::vasprintf(&arg_msg, format, args);
va_end(args);
if (arg_msg != NULL) {
_DNBLog(DNBLOG_FLAG_WARNING | DNBLOG_FLAG_VERBOSE, "warning: %s",
arg_msg);
free(arg_msg);
}
}
}
// Printing of warnings that are not fatal.
void _DNBLogWarning(const char *format, ...) {
if (DNBLogEnabled()) {
char *arg_msg = NULL;
va_list args;
va_start(args, format);
::vasprintf(&arg_msg, format, args);
va_end(args);
if (arg_msg != NULL) {
_DNBLog(DNBLOG_FLAG_WARNING, "warning: %s", arg_msg);
free(arg_msg);
}
}
}
#endif
```
|
The Collingswood Story is a 2002 American computer screen supernatural horror film written and directed by Michael Costanza, and starring Stephanie Dees, Johnny Burton, Grant Edmonds, and Diane Behrens. Its plot follows a college-aged couple who attempt to maintain their long-distance relationship via video chatting; however, a chance encounter with an online psychic plunges their lives into a world of nightmarish supernatural phenomena.
The Collingswood Story began production in the year 2000, when video chatting was in its infancy and far from mainstream. It is known today as the first screenlife film for its innovative video chat concept. In an August 2022 editorial "The Evolution of Found Footage: A History of Screenlife Horror" The Collingswood Story is referred to as "the first true Screenlife horror flick." The film has been cited as a precursor to a number of horror films presented in the computer screen format, such as Host, and Unfriended.
Plot
Rebecca Miles relocates to Collingswood, New Jersey to attend Rutgers University, renting a room in a historic house. On Rebecca's twenty-first birthday, her boyfriend, Johnny, gifts her a webcam so the two can maintain a long-distance relationship. Johnny, communicating with his friend Billy—also via webcam—is introduced to Vera Madeline, an online psychic whom Billy claims contacted his deceased father. Rebecca is skeptical of Vera, and offers to have a virtual session with her first. During the video conference, Vera appears in a darkened room, backlit by two candelabras, and donning sunglasses. Rebecca gives Vera a false name, but shortly into her psychic reading, Vera calls Rebecca by her actual name. This piques Rebecca's interest, but she chalks it up to Vera having some method of caller identification.
When Johnny has a session with Vera, she asks who referred him, and he mentions Rebecca. Vera comments that Collingswood is well-known to psychics and mediums due to grim historical events that occurred there involving a secret society founded by a French immigrant named Alan Tashi, who in the 1800s, murdered and mutilated nine girls, cutting out their eyes, before disposing of their bodies in a well. When the townspeople attempted to seek vengeance, they stormed Tashi's home, but found it empty; in the attic, they discovered a wooden shaker toy, but no sign of Tashi, Vera urges Johnny to have Rebecca contact her again for another session, imparting that Rebecca is a "sensitive," and that she has important information for her.
Upon further investigation, Johnny discovers that the house Rebecca is living in was the site of a murder–suicide four years prior, in which a judge drowned his children in the bathtub before killing his wife, and then, himself. In crime scene photos published online, Johnny glimpses a wooden shaker toy. Armed with this knowledge, Johnny worries about Rebecca, who has been left alone in the house by the homeowners over the Halloween weekend. Rebecca begins to look for evidence of the supposed secret society in Collingswood, recording footage as she drives around town, but is unable to locate the address of the original Tashi home.
On Saturday, Halloween, Rebecca again connects with Vera for a video conference, inquiring about the secret society Vera had told Johnny about—Vera, however, denies having any knowledge of the matter, and acts as though she has never spoken to Rebecca. Furthermore, she claims her psychic readings are for entertainment purposes only. Rebecca video calls Johnny to tell him about her call with Vera. While perusing the bookshelf in the den of the home, Rebecca finds postcards depicting a wooden shaker toy resembling the one left behind in Alan Tashi's absence, as well as in the crime scene photos. Rebecca recalls that Vera spoke in French during one of their sessions, and begins to suspect that Vera might be a member of the secret society.
Johnny manages to contact Vera again, who tells him to get Rebecca out of the house, and alludes to the fact that the secret society practiced rituals in the attic of the house. Meanwhile, Rebecca goes for a drive to get food. On the way home, she again attempts to locate the Tashi residence, and manages to find it. When she returns home, Johnny tells her what Vera told him. A defiant Rebecca decides to explore the attic, recording her endeavor with the webcam as Johnny watches. She finds a secret room, where she locates a number of old photographs and occult paraphernalia. Her webcam stream is interrupted by a video call from Vera, who warns her to leave. Vera removes her sunglasses, revealing one glass eye—she explains that she narrowly escaped the cult, who cut out one of her eyes.
Vera's call suddenly ends, and Rebecca reconnects with Johnny, who watches as she attempts to flee the attic in a panic, but is confronted by Alan Tashi. Simultaneously, an unknown figure emerges from the closed door behind Johnny and attacks him.
Cast
Production
Writer-director Michael Costanza developed the idea for the film based on an old news article about a mass murder that occurred in a New Jersey home in the 19th century.
Stephanie Dees, who portrays Rebecca in the film, had previously appeared in a minor part in Halloween 4: The Return of Michael Myers (1988) as a child.
Filming of The Collingswood Story took place primarily in Los Angeles, California, though some exteriors were filmed by Costanza in Collingswood, New Jersey.
Release
In 2005, The Collingswood Story screened at film festivals including Frightfest in London, The Festival of Fantastic Films in Manchester, and the Fearless Tales Film Festival in San Francisco. The film received the Best Cast and Best Indie Film Award. During the film's Anchor Bay release The Collingswood Story received raves reviews. Quotes included "A Low Budget Triumph", "Inventive and Frightening", "The Tense Atmosphere is Simply Superb and Unnerving", "Original and Clever", "Unquestionably the Best "Pure" Horror Film of this Year's Frightfest". Empire, Dreamwatch, SFX, and journalist Kim Newman also praised the film.
The Collingswood Story was then pitched as a remake to various studios including the producers of Paranormal Activity.
In April 2011, Dread Central screened the film during their celebration of Indie Horror Month.
In March 2022 The Collingswood Story was featured in the Unnamed Footage Festival and screened at the Balboa Theater in San Francisco.
Home media
The Collingswood Story was initially distributed on DVD on June 21, 2006 by film veteran Mo Claridge Anchor Bay UK (which is no longer in business.)
On October 5, 2021, The Collingswood Story was released on Amazon Prime Video as well as on Blu-ray via Cauldron Films.
On October 3, 2022, The Collingswood Story began streaming uncut exclusively on AMC's Shudder.
Awards
Best Cast, Fearless Tales Film Festival San Francisco, California 2005
References
Further reading
"The Best Low Budget Movie Since The Blair Witch Project"—Shivers Magazine, October 2006, Iss. 108, pg. 66, by: Calum Waddell
"Kim Newman's Dungeon Breakout Name to Watch: Michael Costanza"—Empire October 2006, pg. 66, by: Kim Newman
"Pleasantly Spooky Post Blair Witch Ghost Story"—SFX Magazine" August 2006, Iss. 146, pg. 130, by: Andrew Osmond
"The Making of The Collingswood Story"—The Dark Side Magazine (UK) September 2006, Iss. 122, pg. 60, by: Cameron Scott
DVD Monthly August 2006, Iss. 95, pg. 132, by: Jordon Brown
External links
Official website
2002 films
2002 horror films
American independent films
American mockumentary films
American supernatural horror films
Films about psychic powers
Films about secret societies
Films set in New Jersey
Films shot in Los Angeles
Films shot in New Jersey
Found footage films
Halloween horror films
Techno-horror films
Screenlife films
2000s English-language films
2000s American films
|
Torrens title is a land registration and land transfer system, in which a state creates and maintains a register of land holdings, which serves as the conclusive evidence (termed "indefeasibility") of title of the person recorded on the register as the proprietor (owner), and of all other interests recorded on the register.
Ownership of land is transferred by registration of a transfer of title, instead of by the use of deeds. The Registrar provides a Certificate of Title to the new proprietor, which is merely a copy of the related folio of the register. The main benefit of the system is to enhance certainty of title to land and to simplify dealings involving land.
Its name derives from Sir Robert Richard Torrens (1814–1884), who designed, lobbied for and introduced the private member's bill which was enacted as the Real Property Act 1858 in the Colony of South Australia, the first version of Torrens title enacted in the world. Torrens based his proposal on many of the ideas of Ulrich Hübbe, a German lawyer living in South Australia. The system has been adopted by many countries and has been adapted to cover other interests, including credit interests (such as mortgages), leaseholds and strata titles.
Overview
The Torrens title system operates on the principle of "title by registration" (granting the high indefeasibility of a registered ownership) rather than "registration of title". The system does away with the need for proving a chain of title (i.e., tracing title back in time through a series of documents). The State guarantees title, and the system is usually supported by a compensation scheme for those who lose their title due to private fraud or error in the State's operation.
In most jurisdictions, there will be parcels of land which are still unregistered.
The Torrens system works on three principles:
Mirror principle – the register reflects (mirrors) accurately and completely the current facts about title to each registered lot. This means that each dealing affecting a lot (such as a transfer of title, a mortgage or discharge of same, a lease, an easement or a covenant) must be entered on the register and so be viewable by anyone.
Curtain principle – one does not need to go behind the Certificate of Title as it contains all the information about the title. This means that ownership need not be proved by long complicated documents that are kept by the owner, as in the Private Conveyancing system. All of the necessary information regarding ownership is on the Certificate of Title.
Indemnity principle – provides for compensation of loss caused by private fraud or by errors made by the Registrar of Titles.
Background
Common law
At common law, the vendor of land needs to show his or her ownership of the land by tracing the chain of ownership back to the earliest grant of land by the Crown to its first owner. The documents relating to transactions with the land are collectively known as the "title deeds" or the "chain of title". This event may have occurred hundreds of years prior and could have had dozens of intervened changes in the land's ownership. A person's ownership over land could also be challenged, potentially causing great legal expense to land owners and hindering development.
Even an exhaustive title search of the chain of title would not give the purchaser complete security, largely because of the principle, nemo dat quod non habet ("no one gives what he does not have") and the ever-present possibility of undetected outstanding interests. For example, in the UK Court of Chancery case Pilcher v Rawlins (1872), the vendor conveyed the fee-simple estate to P1, but retained the title deeds and fraudulently purported to convey the fee-simple estate to P2. The latter could receive only the title retained by the vendor—in short, nothing. However, the case was ultimately decided in favor of P2, over P1. The courts of equity could not bring themselves to decide against a totally innocent (without notice) purchaser.
The common-law position has been changed in minor respects by legislation designed to minimize the searches that should be undertaken by a prospective purchaser. In some jurisdictions, a limitation has been placed on the period of commencement of title a purchaser may require.
Deeds registration
The effect of registration under the deeds registration system (also known as "record title") was to give the instrument registered "priority" over all instruments that are either unregistered or not registered until later. The recording of the deed served to give notice to the world of the conveyance of title to the grantee named in the deed. The basic difference between the deeds registration and Torrens systems is that the former involves registration of instruments while the latter involves registration of title.
Moreover, though a register of who owned what land was maintained, it was unreliable and could be challenged in the courts at any time. The limits of the deeds-registration system meant that transfers of land were slow, expensive, and often unable to create certain title.
Creation
Sir Robert Richard Torrens, Registrar-General and Treasurer of the colony of South Australia and later a member of the House of Assembly, lobbied for many years for a new title system to improve the currently cumbersome, slow and expensive system of land transfer. He was largely responsible for shepherding the new Bill through Parliament, enacted in 1858 as the Real Property Act 1858. The system laid out in this bill became known as the Torrens title system, and was based on a central registry of all the land in the jurisdiction of South Australia.
Torrens drew ideas from the system of registration of merchant ships in the United Kingdom, experience gained from his years of working as a customs official. He also used many of the ideas incorporated in the Act from Ulrich Hübbe, a German lawyer living in South Australia at that time, who had expert knowledge of the Hanseatic registration system in Hamburg.
Land register
The central aspect of the Torrens system is the land register, in which all dealings with land are recorded. The register may be a bound paper record, but today most registers are typically kept in a database. Ownership of the land is established by virtue of the owner's name being recorded in the government's register. The Torrens title also records easements and the creation and discharge of mortgages.
On the first registration of land under the system, the land is given a unique number (called a volume-folio number) which identifies the land by reference to a registered plan. The folio records the dimensions of the land and its boundaries, the name of the registered owner, and any legal interests that affect title to the land. To change the boundaries of a parcel of land, a revised plan must be prepared and registered. Once registered, the land cannot be withdrawn from the system.
A transfer of ownership of a parcel of land is effected by a change of the record on the register. The registrar has a duty to ensure that only legally valid changes are made to the register. To this end, the registrar will indicate what documentation he or she will require to be satisfied that there has in fact been a change of ownership. A change of ownership may come about because of a sale of the land, or the death of the registered owner, or as a result of a court order, to name only the most common ways that ownership may change. Similarly, any interest which affects or limits the ownership rights of the registered owner, such as a mortgage, can also be noted on the register. There are legal rules which regulate the rights and powers of each of these interests in relation to each other and in relation to third parties.
The State guarantees the accuracy of the register and undertakes to compensate those whose rights are adversely affected by an administrative error. Claims for compensation are very rare.
Effect of registration
The main difference between a common law title and a Torrens title is that a member of the general community, acting in good faith, can rely on the information on the land register as to the rights and interests of parties recorded there, and act on the basis of that information. A prospective purchaser, for example, is not required to look beyond that record. He or she does not need even to examine the Certificate of Title, the register information being paramount. This contrasts with a common law title, which is based on the principle that a vendor cannot transfer to a purchaser a greater interest than he or she owns. As with a chain, the seller's title is as good as the weakest link of the chain of title. Accordingly, if a vendor's common law title were defective in any way, so would be the purchaser's title. Hence, it is incumbent on the purchaser to ensure that the vendor's title is beyond question. This may involve both inquiries and an examination of the chain of title, which can be a protracted and costly exercise each time there is a dealing in the property.
The registered proprietor of Torrens land is said to have an indefeasible title, which means that his or her title can be challenged only in very limited circumstances (see following).
Indefeasibility of title
The register of titles is said to confer “indefeasibility of title” to the person or persons registered on the register as proprietor or joint proprietors of land. Although the concept of indefeasibility is similar to that of conclusive evidence, in practice there are some limitations to indefeasibility, and different jurisdictions have different laws and provisions.
For example, in the Australian state of Victoria, the Torrens system is manifested in the Transfer of Land Act 1958 (Vic). Upon registration of an interest and subsequent recording on title of the interest, the registered owner's claim to that interest is superior to all other claims other than those listed in s.42 of that Act, which provides that the title of the registered interest holder is subject to, inter alia:
those listed on the title,
those claiming the land on a prior folio (s.42(1)(a)),
where the land is included by wrong description on the part of the Registrar and the proprietor is not or has not derived title from a purchaser ‘for value’ (s.42(1)(b),
“paramount interests” (s.42(2)(a)-(f)) – these interests, although even possibly unregistered, are 'superior' to interests that are registered.
Additionally, there are other exceptions or circumstances that can defeat indefeasibility, such as:
fraud committed by the registered interest holder [principle of immediate indefeasibility]. See, for example, the New Zealand case of Efstratiou, Glantschnig, and Petrovic v Glantschnig,
judicial action, where it can be shown that there was some contractual promise or undertaking by the registered party vis-à-vis the unregistered party,
inconsistent legislation (in which case the most recent legislation prevails),
volunteer, where the registering party acquires the interest for no consideration (e.g. bequeathed in a will). By contrast, in New South Wales volunteers are entitled to indefeasibility.
Adoption
The adoption of the Torrens title registry throughout the British Commonwealth, and its legal context, was covered in depth by James Edward Hogg in 1920.
Australia
The first sale of land registered under the system was to pastoralist William Ransom Mortlock (later elected to the South Australian House of Assembly) on 25 August 1858.
Starting with South Australia, all Australian colonies introduced the Torrens system between 1858 and 1875. Since then, each colony, and since 1901, states and territories, state or territory has maintained its own land titles register of land.
The Torrens system did not replace the common law system but applied only to new land grants and to land that was voluntarily registered under the relevant Act. In Australia most land is held under the Torrens Title system, although remnants of the old system of land title still remain. All land in the Australian Capital Territory is leasehold (effectively Torrens freehold), while much of the Northern Territory is held under Crown lease. Native Title is recognised as a separate form of ownership. Some land remains as Crown Land (i.e. in Australia, public land).
Canada
The second Torrens jurisdiction in the world was established in 1861 in the then-British colony of Vancouver Island, now part of the Canadian province of British Columbia. Canada, through the federal Parliament in 1886, implemented the Torrens system in the Northwest Territories. It has continued to be used by the three Prairie provinces (Alberta, Saskatchewan and Manitoba) into which the southern part of the Northwest Territories was divided. British Columbia uses a modified Torrens system. Since 1885, Ontario has used an English system, which is not a Torrens system, but it has similar purposes. In Ontario, electronic registration led to this version covering almost all land, but the past deeds registration still governs some issues. For properties still under deeds registration, a 40-year rule governed title, but the government converted them under a streamlined process. New Brunswick and Nova Scotia converted from a Deeds registration system to a Torrens title system in the 2000s, with the expense of the changeover charged to the purchaser. The only provinces in Canada which do not have Torrens titles include Newfoundland and Labrador, Prince Edward Island, and Quebec, which is a civil rather than common law jurisdiction and instead uses the cadastre system.
Fiji
Fiji's Torrens statute is the Land Transfer Act 1971.
Dominican Republic
The Dominican Republic has been using the Torrens Title System since 1920. All of commercial property and most real estate within the main cities are registered and thus guaranteed under the system. An acceleration of registration for land in the rural areas is underway in the 21st century, to promote a more efficient and effective real estate market in the Dominican Republic.
Ireland
Ireland first began to operate a Torrens Title system in 1892. So-called registered land (i.e. land held under a Torrens title) is recorded in the Republic of Ireland using a system of numbered county-level folios. The land registry is operated by the Property Registration Authority, a government agency, and records both freehold and leasehold titles, along with easements/profits-a-prendre, mortgages, and any other charges over land. It is compulsory to create a folio in the land registry if land is sold/transferred/subdivided, multi-storey buildings are erected, or a new lease (over five years) is created. The vast majority of land in Ireland (by acreage) is held under Torrens title as compulsory registration in the land registry upon sale has been a requirement in rural areas for many years. Compulsory registration was extended to the (more urban) counties of Cork, Dublin, Galway, Limerick and Waterford in 2010, thus extending mandatory Torrens title to every part of the Republic of Ireland.
Israel
A Torrens title system was implemented by the British in Mandatory Palestine, and has continued in use since Israel's foundation in 1948. As of 2016, about 4% of the country's land area is still registered under a pre-Torrens, deeds registration system.
Malaysia
Malaysia has adopted three versions of the Torrens system:
For Peninsular Malaysia, this is enacted in the National Land Code, Act 56 of 1965.
For the state of Sarawak, this is enacted in the Sarawak Land Code, Chapter 81 of 1958.
For the state of Sabah, this is enacted in the Land Ordinance (Sabah Chapter 68). Unlike the National Land Code and the Sarawak Land Code, the Land Ordinance (Sabah Chapter 68) does not provide any indefeasibility of title.
New Zealand
New Zealand adopted a similar system from 1870 under the Land Transfer Act, 1870 The Land Transfer (Compulsory Registration of Titles) Act 1924 brought most of the remaining land in the country under the Torrens system and by 1951 the register was considered complete, although small remnants of land may still exist under the deeds system. The Land Transfer Act 1952 further implemented the Torrens system. In the 20th century, academics and judges disagreed about whether to interpret indefeasibility as "deferred" or "immediate". In 1967, the Privy Council in Frazer v Walker decided that a registered owner will obtain an indefeasible title to an interest or estate as soon as they become the registered owner of the interest or estate (the principle of immediate indefeasibility).
The 1952 Act was superseded by the Land Transfer Act 2017. The 2017 Act introduces a judicial discretion to cancel an owner's registration of title in cases of "manifest injustice", which arguably frustrates the certainty of title considered fundamental to the principle of immediate indefeasibility.
In New Zealand most land is held under the Torrens Title system, although remnants of the old system of land title still remain. Māori customary title (native title) is recognised as a separate form of ownership. Some land remains as Crown Land (i.e. in New Zealand, public land).
Philippines
The Torrens system was established in the Philippines on November 6, 1902, by the enactment of Act No. 496, "The Land Registration Act", which was virtually identical to the Real Property Act of Massachusetts of 1898.
Russia
Russia adopted the Torrens system soon after the founding of the Soviet Union. Currently, the accounting and registration system for rights to immovable property in Russia is governed by two federal laws, which have adopted some of the elements and principles of the Torrens system. Accounting for land, buildings and natural sites is recorded in a database of real estate cadastre under federal law of 2007 No. 221-FZ "On State Real Estate Cadastre". Transactions by the account holder of these facilities is recorded in another database: “the Unified State Register of rights to immovable property and transactions with them” on the basis of federal law of 1997 No. 122-FZ "On State Registration of Rights to Real Estate and Transactions Therewith". Both laws established openness cadastre and registry information, and assigned to a single organization responsible for their management - Rosreestr . Entry in the Unified State Register of real property rights is a necessary and sufficient condition for the emergence of property rights to real estate. For information about the property, contained in the cadastre and registry, sufficiently detailed and structured cover most essential information about an object runs open cadastral map. With a fairly simple web forms can be found and read a part of the information on any object property. These laws are not, however, establish an immediate full liability of the state for the correctness of the information contained in databases.
In 2015, the State Duma has been registered a bill that covers public access to information about the owners of the property. The bill was supported by the Government. According to some experts, the restriction of information openness reduces the chances of identifying the public cases of illegal enrichment and increases business risks.
Saudi Arabia
Saudi Arabia introduced a Torrens system in 2002 with The Realty in Kind Registration Law, issued by Royal Decree No. 6 on 9/21423H
Singapore
Singapore adopted a version of the Torrens system beginning in 1960 with the Land Titles Act, Chapter 157. Conversion of all titles was completed in 2001.
Sri Lanka
Sri Lanka has introduced a version of the Torrens system known as Bim Saviya under the Registration of Title Act No. 21 of 1998. The Survey Department of Sri Lanka had started the process of surveying government and private own land for the entry into the Bim Saviya registration. As of date the process has not finished in land surveying and converting land owners original deeds into Certificate of Titles. The program has become highly controversial, with claims that it mirrors the reclamation of crown land by the British colonial government of Ceylon under the Prevention of Encroachments upon Crown Lands Ordinance No 12 of 1840 with the government taking over ownership of land its occupants cannot prove ownership of and the high possibility of fraud, lack of recognition of Certificate of Title issued under the Bim Saviya program and the lack of provisions for co-ownership.
Thailand
Thailand adopted the Torrens system in 1901 after King Chulalongkorn established The Royal Thai Survey Department, a Special Services Group of the Royal Thai Armed Forces, engaged in Cadastral survey, which is the survey of specific land parcels to define ownership for land registration, and for equitable taxation.
United States
The Torrens system is used in the U.S. territory of Guam. States with a limited implementation include Minnesota, Virginia, Massachusetts, Colorado, Georgia, Hawaii, New York, North Carolina, Ohio, and Washington.
The state of Illinois was the first state to adopt a Torrens Title Act, which used a limited Torrens system in Cook County after the Great Chicago Fire, but the system was allowed to expire on January 1, 1992, after it was found to be unpopular with lenders and other institutions.
California adopted the Torrens System in 1914 pursuant to an initiative statute. Although participation in the system was voluntary, once an owner had registered his land, he could not withdraw from the system. The Torrens System, as adopted in California, did not protect buyers from defects caused by federal tax liens, federal bankruptcy proceedings, or from incompetency, divorce, or probate proceedings affecting the seller. Since the system had been adopted by initiative, the legislature had no authority to correct those deficiencies. By an initiative adopted in 1954, the legislature was given authority to amend or repeal the system, and, in 1955, it was repealed.
Virginia enacted a Torrens system option. However, it never became popular and the Torrens Act was abolished in 2019. Record title is now the only form of land title registration in Virginia.
Washington had voluntary Torrens registration until June 2022, at which time new registrations were discontinued. Existing registrations will be terminated on July 1, 2023.
See also
Cadastre, the equivalent concept in the French civil law
Strata title, an enhancement of Torrens Title intended for apartment buildings and house-typed units.
References
Further reading
Real property law
Property law of New Zealand
Australian property law
History of South Australia
Australian inventions
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The Ball State Cardinals men's basketball statistical leaders are individual statistical leaders of the Ball State Cardinals men's basketball program in various categories, including points, rebounds, assists, steals, and blocks. Within those areas, the lists identify single-game, single-season, and career leaders. The Cardinals represent Ball State University in the NCAA's Mid-American Conference.
Ball State began competing in intercollegiate basketball in 1920. However, the school's record book does not generally list records from before the 1950s, as records from before this period are often incomplete and inconsistent. Since scoring was much lower in this era, and teams played much fewer games during a typical season, it is likely that few or no players from this era would appear on these lists anyway.
The NCAA did not officially record assists as a stat until the 1983–84 season, and blocks and steals until the 1985–86 season, but Ball State's record books includes players in these stats before these seasons. These lists are updated through the end of the 2020–21 season.
Scoring
Rebounds
Assists
Steals
Blocks
References
Lists of college basketball statistical leaders by team
Statistical
|
```objective-c
//
//
// path_to_url
//
#ifndef PXR_USD_IMAGING_USD_IMAGING_TET_MESH_ADAPTER_H
#define PXR_USD_IMAGING_USD_IMAGING_TET_MESH_ADAPTER_H
/// \file usdImaging/tetMeshAdapter.h
#include "pxr/pxr.h"
#include "pxr/usdImaging/usdImaging/api.h"
#include "pxr/usdImaging/usdImaging/primAdapter.h"
#include "pxr/usdImaging/usdImaging/gprimAdapter.h"
PXR_NAMESPACE_OPEN_SCOPE
/// \class UsdImagingTetMeshAdapter
///
/// Delegate support for UsdGeomTetMesh.
///
class UsdImagingTetMeshAdapter : public UsdImagingGprimAdapter
{
public:
using BaseAdapter = UsdImagingGprimAdapter;
UsdImagingTetMeshAdapter()
: UsdImagingGprimAdapter()
{}
USDIMAGING_API
~UsdImagingTetMeshAdapter() override;
// your_sha256_hash------ //
/// \name Scene Index Support
// your_sha256_hash------ //
USDIMAGING_API
TfTokenVector GetImagingSubprims(UsdPrim const& prim) override;
USDIMAGING_API
TfToken GetImagingSubprimType(
UsdPrim const& prim,
TfToken const& subprim) override;
USDIMAGING_API
HdContainerDataSourceHandle GetImagingSubprimData(
UsdPrim const& prim,
TfToken const& subprim,
const UsdImagingDataSourceStageGlobals &stageGlobals) override;
USDIMAGING_API
HdDataSourceLocatorSet InvalidateImagingSubprim(
UsdPrim const& prim,
TfToken const& subprim,
TfTokenVector const& properties,
UsdImagingPropertyInvalidationType invalidationType) override;
// your_sha256_hash------ //
/// \name Initialization
// your_sha256_hash------ //
USDIMAGING_API
SdfPath Populate(
UsdPrim const& prim,
UsdImagingIndexProxy* index,
UsdImagingInstancerContext const* instancerContext = nullptr) override;
USDIMAGING_API
bool IsSupported(UsdImagingIndexProxy const* index) const override;
// your_sha256_hash------ //
/// \name Parallel Setup and Resolve
// your_sha256_hash------ //
/// Thread Safe.
USDIMAGING_API
void TrackVariability(UsdPrim const& prim,
SdfPath const& cachePath,
HdDirtyBits* timeVaryingBits,
UsdImagingInstancerContext const*
instancerContext = nullptr) const;
// your_sha256_hash------ //
/// \name Change Processing
// your_sha256_hash------ //
USDIMAGING_API
HdDirtyBits ProcessPropertyChange(UsdPrim const& prim,
SdfPath const& cachePath,
TfToken const& propertyName) override;
// your_sha256_hash------ //
/// \name Data access
// your_sha256_hash------ //
USDIMAGING_API
VtValue GetTopology(UsdPrim const& prim,
SdfPath const& cachePath,
UsdTimeCode time) const override;
};
PXR_NAMESPACE_CLOSE_SCOPE
#endif // PXR_USD_IMAGING_USD_IMAGING_TET_MESH_ADAPTER_H
```
|
Joe Fowler is an American sportscaster, actor, and infomercial pitchman who has worked for KSAT-TV, WTTG, WCAU, KCAL-TV, and the World Wrestling Federation.
Career
Fowler attended American University from 1976 to 1977, but left school become an announcer for the San Antonio Dodgers. In 1980, he became the weekend sports anchor at San Antonio's KSAT-TV, and quickly became the station's sports director. In 1984 he moved to New York City to pursue an acting career. He appeared in the Sylvester Stallone film Cobra and on HBO's First and Ten.
Unable to make ends meet as an actor, Fowler took a part-time job at KMOX-TV in St. Louis. In 1986 he replaced Bernie Smilovitz as the sports anchor on WTTG-TV's The Ten O'Clock News. After a stint at Philadelphia's WCAU-TV, Fowler became a report for KCAL-TV in Los Angeles. While there, he appeared in two episodes of Coach as sportscaster Bob Clifton. He also hosted Tuesday Night Muscle, a weekly women's bodybuilding show, on ESPN. In 1992 he hosted Knights and Warriors, a syndicated American Gladiators-type show produced by Welk Entertainment Group.
In 1993, Fowler joined the World Wrestling Federation as a replacement for interviewer Gene Okerlund. He made his debut at that year's SummerSlam pay-per-view and left the company a few months later.
In 1994, Fowler has hosted Maximum Drive on The Family Channel. He has since worked as an infomercial pitchman, advertising such products as the Lizard Hose and the Omelette Express, and hosted programming for ShopHQ.
References
American actors
American game show hosts
Infomercial pitchmen
Professional wrestling announcers
Television anchors from Washington, D.C.
|
Ernst Kreidolf or Konrad Ernst Theophil Kreidolf (9 February 1863 – 12 August 1956) was a Swiss painter largely known for illustrating children's books about flower fairies.
Early life and education
Konrad Ernst Theophil Kreidolf, the second eldest child of the Kreidolf family, was born on 9 February 1863 in Berne, Switzerland.
The family relocated to Konstanz in Germany, where his father opened a toy shop. Ernst Kreidolf was raised by his grandparents in Tägerwilen, Switzerland. In Konstanz, he began an apprenticeship as a lithographer at the Lithographische Anstalt Schmidt-Pecht (Lithographic Institute JA Pecht) while simultaneously studying drawing. Following the completion of his apprenticeship, Kreidolf kept working for Schmidt-Pecht as an assistant in order to provide for his family following the bankruptcy of his parents' shop.
In Munich, he attended the Kunstgewerbeschule. He supplemented his income by working as a lithographic draftsman. Beginning in 1885, he studied art at Paul Nauen's private art school. On his second application in 1887, the Akademie der Bildenden Künste München accepted Kreidolf as a student. He studied under Gabriel von Hackl and Ludwig von Löfftz.
Career
He was a leading figure in the Jugendstil movement. His work as picture books demonstrates a high level of technical proficiency as well as exact botanical and zoological knowledge. Almost all of his illustrations include animals and plants given human characteristics.
Kreidolf's work often features dogs in significant or prominent roles. The Dachshund belonging to Kreidolf's friend and author Leopold Weber, whom he met in Partkirchen, served as inspiration for a large number of quite varied sketches, watercolors, paintings, and a whole illustrated book.
Death
Kreidolf died on 12 August 1956 in Berne. He is interred in Bern's Schosshalden cemetery.
Gallery
References
19th-century Swiss painters
Swiss male painters
20th-century Swiss painters
1863 births
1956 deaths
19th-century Swiss male artists
20th-century Swiss male artists
|
Jonathan Michael Petrie (born 19 October 1976) is a Scottish rugby union executive and former player. During his active career he played at flanker for Glasgow Warriors and Scotland.
Petrie had two seasons in Scotland's under-21 team, making his debut against the Irish in 1997 while he was playing in France with Colomiers. Petrie's Scotland A debut was in the 99–0 win over the Netherlands at Murrayfield in December 1999. He won his first cap in the second test on the tour of New Zealand in 2000, his first try for Scotland came in 31–8 November 2000 win against Samoa. He was given the captaincy by then Scotland coach Frank Hadden in 2005 leading Scotland to their first ever victory against the Barbarians.
Petrie was Club Captain of Glasgow Warriors from 2004 to 2006.
Jon Petrie was denied his first Test series as captain by injury ahead of the matches against Argentina, Samoa and New Zealand in November 2005.
His later career was blighted by injury and he was eventually replaced as captain by Jason White.
Jon Petrie announced his retirement as a player from Rugby Union in March 2007.
On 16 July 2015 it was announced that he would take over as managing director of Edinburgh Rugby.
Since January 2019 he is Chief Executive of Ulster Rugby.
Notes
1976 births
Living people
Scottish rugby union players
Rugby union players from Dundee
People educated at the High School of Dundee
Alumni of the University of St Andrews
University of St Andrews RFC players
Scotland international rugby union players
Dundee HSFP players
Glasgow Warriors players
Rugby union flankers
Ulster Rugby non-playing staff
2003 Rugby World Cup players
|
Comodactylus is a genus of "rhamphorhynchoid" pterosaur from the Kimmeridgian-Tithonian-age Upper Jurassic Morrison Formation of Wyoming, United States, named for a single wing metacarpal.
In 1879 collector William Harlow Reed sent some fossil material he had excavated at Como Bluff in Quarry N° 9, or the "Mammal Quarry," to his employer Professor Othniel Charles Marsh at New Haven. Among it was the bone of a pterosaur that was subsequently filed, stored and forgotten.
In 1981 Peter Galton erected the genus Comodactylus based on this bone. The type species is Comodactylus ostromi. The genus name is derived from Como Bluff and Greek daktylos, meaning "finger," referring to the dramatically extended wing finger that is unique to pterosaurs. The specific name honors John Ostrom.
The holotype is YPM 9150, consisting of an intact fourth metacarpal measuring long. This holotype is the only known material from the animal. The metacarpal is quite robust, with the proximal end being very expanded. Such proportions are typical for basal pterosaurs such as Rhamphorhynchus, suggesting Comodactylus was not a member of the advanced Pterodactyloidea. However, assigning it to a pterosaur clade beyond the paraphyletic group "Rhamphorhynchoidea" has proven difficult due to a lack of diagnostic material. In 1989, James Jensen and Kevin Padian considered Comodactylus a nomen dubium. David Unwin in 1993 suggested an affinity with Nesodactylus.
The wingspan has been estimated at 2.5 meters (8.2 ft), exceptionally large for a pterosaur not belonging to the Pterodactyloidea. Comodactylus was also the first non-pterodactyloid pterosaur that was found in the Americas.
See also
List of pterosaur genera
Timeline of pterosaur research
References
Pterosaurs
Late Jurassic pterosaurs of North America
Morrison fauna
Taxa named by Peter Galton
Fossil taxa described in 1981
|
Melton Secondary College was the first secondary school built in Melton, Victoria, Australia. The school currently offers studies in 34 VCE subjects and 23 VET subjects.
Houses
Interhouse competitions remain an integral part of the school's ethos.
The four Houses with their associated colours are:
Yangardook (Red)
Kororoit (Blue)
Djerriwarrh (Green)
Pywheitjorrk (Yellow)
The names for the houses were derived from local waterways.
The houses compete in 2 Major Competitions:
Athletics
Swimming
Kororoit current champions for athletics and swimming in 2013
Music
There is a Concert Band which reached a peak in 2006 with more than 75 members attending regular rehearsals and music lessons.
Other Major Ensembles
Jazz
Woodwind
Brass
Flute
Guitar
Vocal
WORKSHOPS with outstanding ARTISTS
Major Pat Picket,
Don Burrows,
James Morrison,
Graeme Lylall,
Gary Hommelhoff,
New Zealand Army Band,
Australian Army Band,
Majoe Peter Grant,
Mark Summerbell- Orchestra Victoria,
Peter Moore - Orchestra Victoria,
2005-2009 ORCHESTRA VICTORIA
AWARDS
1st School from Victoria to perform at "Movieworld". (2000)
1st School in the Western Suburbs to make a CD at Tamworth, N.S.W. (2000)
1st School in the Western suburbs to win the Boorandara Eistedfod. (1998)
1st School in the Western Suburbs to win the State "C" Grade Championship. (1999, 2005)
1st School in the Western Suburbs to win the State "Novice" Grade Championship.(2002)
Bendigo Eistedfod – Won "C grade" Concert Band and Jazz Ensemble, (2004–2006, 2007)
2nd Boxhill State Championships "B" Grade. (2006)
"Music Play for Life" - Guitars in schools Project (2006)
1st State Championships "C" Grade. (2008)
Rock Eisteddfod Challenge
Melton Secondary College had a very successful Rock Eisteddfod team for many years. Among the achievements:
1994: The Beatles
1995: Space Impressions (Junior Team)
1995: Body Image (Senior Team)
1996: Special Days (Junior Team)
1996: Casanova (Senior Team)
1997: Gold Rush (Junior Team)
1997: Elvis (Senior Team)
1998: From the Tsar With Love - Revolution (Based on the Russian Revolution and the Tsar Nicholas II): 1st Place, Open Division
1999: What's For Dinner? (Based on the Addams Family): 5th Place, Premier Division - The first Victorian school in its state to obtain a place in their first year in Premier Division
2000: De Amor En Espana - Love in Spain (Roughly based in the musical Carmen): 5th Place, Premier Division
2001: Rock'n'the River (Roughly based on Showboat): 6th Place, Premier Division
2002: Gentleman Prefer Blondes (Based on the life of Marilyn Monroe): 2nd Place, Premier Division and Victorian finalist for Nationals
2003: Deutchland - From Hope to Heartbreak (Based on the musical Cabaret): 4th Place, Premier Division
2004: Free as a bird (based on Aladdin) 11th Place Premier Division
2005: Isadora Duncan - Mother of Modern Dance - Premier Division, 5th Place
2006: Toulouse Lautrec - A Lost Time
2007: HOPE - Live Life. Be Strong (A tribute the cancer charities)
- 2007 welcomed a new team for including Jennifer Toner (Director and Head Choreographer), Jarryd Pentony, Taneesha Pentony, Natalie Desmond, Jessica McMurrie, Leigh Walker, Amanda Cini, Chris Ferreira (set designer)
2008: Do You Think We're Joking (based on Batman) Marilyn Sorensen (Director) and Kate Mainwaring (Assistant Director)
Previous production team included, among others:
Debra Dunn (liaison 1990-1998)
Mik Pollard (liaison 1999-2001, 2004-2005 and motivator involved for a period of 13 years)
Janice Kot (Producer, Director and Head Choreographer 1994-2004)
Olivia Tardio (Lead Choreographer 1 year)
Melissa Barker, Paul Rizzo (who went onto a successful career as a world touring and award winning Michael Jackson tribute artist), Nova Stelarc, Fiona Pettett, Belinda Guban, Janelle Mace, Stephen Wakefield (Choreographers)
Mark Baddeley, Helen Beynon, Kate Kershaw, David Tait, Chris Egan, Peter Hendrickson, John McConchie and many others(Teachers)
Alan Marsh (Set Designer 1999-2003)
The 'Dad's Army' (Set Construction 1999-2003)
Tony Glover (Soundtrack Producer)
Judy Marsh, Carol Harraden, Dianne Glover, Heather Tyrell (Costume Designers)
The Kot, Marsh, Harraden, Glover, Tyrell, Jones, Rizzo and Carroll families
Sister schools
A sister school relationship exists internationally with Showa Junior High School, Okayama in Japan.
See also
List of schools in Victoria
Victorian Certificate of Education
External links
Official website
Public high schools in Victoria (state)
Rock Eisteddfod Challenge participants
Buildings and structures in the City of Melton
Educational institutions established in 1975
1975 establishments in Australia
|
"You Are the One," written by D. Gaskins and K. Lowery, was a single from the soundtrack to the 1989 film Lean on Me. The following year, it was included on their second album Louder Than Love.
Track listing
US 12" single
US Maxi Single
Charts
References
1989 singles
TKA songs
1989 songs
Tommy Boy Records singles
|
```java
*
* path_to_url
*
* Unless required by applicable law or agreed to in writing, software
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
*/
package org.flowable.engine.delegate;
import org.flowable.bpmn.model.FlowElement;
import org.flowable.common.engine.api.variable.VariableContainer;
/**
* @author Filip Hrisafov
*/
public interface ReadOnlyDelegateExecution extends VariableContainer {
/**
* Unique id of this path of execution that can be used as a handle to provide external signals back into the engine after wait states.
*/
String getId();
/**
* Reference to the overall process instance
*/
String getProcessInstanceId();
/**
* The 'root' process instance. When using call activity for example, the processInstance set will not always be the root. This method returns the topmost process instance.
*/
String getRootProcessInstanceId();
/**
* Will contain the event name in case this execution is passed in for an {@link ExecutionListener}.
*/
String getEventName();
/**
* The business key for the process instance this execution is associated with.
*/
String getProcessInstanceBusinessKey();
/**
* The business status for the process instance this execution is associated with.
*/
String getProcessInstanceBusinessStatus();
/**
* The process definition key for the process instance this execution is associated with.
*/
String getProcessDefinitionId();
/**
* If this execution runs in the context of a case and stage, this method returns it's closest parent stage instance id (the stage plan item instance id to be
* precise).
*
* @return the stage instance id this execution belongs to or null, if this execution is not part of a case at all or is not a child element of a stage
*/
String getPropagatedStageInstanceId();
/**
* Gets the id of the parent of this execution. If null, the execution represents a process-instance.
*/
String getParentId();
/**
* Gets the id of the calling execution. If not null, the execution is part of a subprocess.
*/
String getSuperExecutionId();
/**
* Gets the id of the current activity.
*/
String getCurrentActivityId();
/**
* The BPMN element where the execution currently is at.
*/
FlowElement getCurrentFlowElement();
/* State management */
/**
* returns whether this execution is currently active.
*/
boolean isActive();
/**
* returns whether this execution has ended or not.
*/
boolean isEnded();
/**
* returns whether this execution is concurrent or not.
*/
boolean isConcurrent();
/**
* returns whether this execution is a process instance or not.
*/
boolean isProcessInstanceType();
/**
* Returns whether this execution is a scope.
*/
boolean isScope();
/**
* Returns whether this execution is the root of a multi instance execution.
*/
boolean isMultiInstanceRoot();
@Override
default void setVariable(String variableName, Object variableValue) {
throw new UnsupportedOperationException("Setting variable is not supported for read only delegate execution");
}
@Override
default void setTransientVariable(String variableName, Object variableValue) {
throw new UnsupportedOperationException("Setting transient variable is not supported for read only delegate execution");
}
}
```
|
Levodopa-induced dyskinesia (LID) is a form of dyskinesia associated with levodopa (l-DOPA), used to treat Parkinson's disease. It often involves hyperkinetic movements, including chorea, dystonia, and athetosis.
In the context of Parkinson's disease (PD), dyskinesia is often the result of long-term dopamine therapy. These motor fluctuations occur in up to 80% of PD patients after 5–10 years of l-DOPA treatment, with the percentage of affected patients increasing over time. Based on the relationship with levodopa dosing, dyskinesia most commonly occurs at the time of peak l-DOPA plasma concentrations and is thus referred to as peak-dose dyskinesia (PDD). As patients advance, they may present with symptoms of diphasic dyskinesia (DD), which occurs when the drug concentration rises or falls. If dyskinesia becomes too severe or impairs the patient's quality of life, a reduction in l-Dopa might be necessary, however this may be accompanied by a worsening of motor performance. Therefore, once established, LID is difficult to treat. Amongst pharmacological treatments, N-methyl-D-aspartate (NMDA) antagonist, (a glutamate receptor), amantadine, has been proven to be clinically effective in a small number of placebo controlled randomized controlled trials, while many others have only shown promise in animal models. Attempts to moderate dyskinesia by the use of other treatments such as bromocriptine (Parlodel), a dopamine agonist, appears to be ineffective. In order to avoid dyskinesia, patients with the young-onset form of the disease or young-onset Parkinson's disease (YOPD) are often hesitant to commence l-DOPA therapy until absolutely necessary for fear of suffering severe dyskinesia later on. Alternatives include the use of DA agonists (i.e. ropinirole or pramipexole) in lieu of early l-DOPA treatment which delays the use of l-DOPA. Additionally, a review shows that highly soluble l-DOPA prodrugs may be effective in avoiding the in vivo blood concentration swings that potentially lead to motor fluctuations and dyskinesia.
Mechanism
Levodopa-induced dyskinesia has long been thought to arise through pathological alterations in pre-synaptic and post-synaptic signal transduction in the nigrostriatal pathway (dorsal striatum). It is thought that the stage of illness, dosage of l-DOPA, frequency of l-DOPA treatment and the youth of the patient at the onset of symptoms contribute to the severity of the involuntary movements associated with LID.
In experiments employing real-time electrophysiological recordings in awake and active animals, LIDs have been shown to be strongly associated with cortical gamma-oscillations with accompanying Δc-fos overexpression, proposedly due to a dysregulation of dopamine signaling in the cortico-basal ganglia circuitry. This was concluded partially from reduced tyrosine hydroxylase (TH) staining in the cortex - and the fact that a dopamine receptor 1 antagonist, delivered exclusively to the cortex, relieved the dyskinesia at its peak-time.
ΔFosB overexpression in the dorsal striatum (nigrostriatal dopamine pathway) via viral vectors generates levodopa-induced dyskinesia in animal models of Parkinson's disease. Dorsal striatal ΔFosB is overexpressed in rodents and primates with dyskinesias; moreover, postmortem studies of individuals with Parkinson's disease that were treated with levodopa have also observed similar dorsal striatal ΔFosB overexpression.
Treatment
Levetiracetam, an antiepileptic drug which has been demonstrated to reduce the severity of levodopa-induced dyskinesias, has been shown to dose-dependently decrease the induction of dorsal striatal ΔFosB expression in rats when co-administered with levodopa. Although the signal transduction mechanism involved in this effect is unknown.
Nicotine (administered by dermal adhesive patches) has also been shown to improve Levodopa-induced dyskinesia and other PD symptoms.
Patients with prominent dyskinesia resulting from high doses of antiparkinsonian medications may benefit from deep brain stimulation (DBS), which may benefit the patient in two ways: 1) DBS theoretically allows a reduction in l-DOPA dosage of 50–60% (tackling the underlying cause); 2) DBS treatment itself (in the subthalamic nucleus or globus pallidus) has been shown to reduce dyskinesia.
In 2017, the FDA approved the first treatment for levodopa-induced dyskinesia for Parkinson's patients: Gocovri, amantadine manufactured by Adamas Pharmaceuticals. Mavoglurant and ketamine are also currently studied for the treatment of this disease.
References
External links
Parkinson's disease
|
```c
/****************************************************************
The author of this software is David M. Gay.
All Rights Reserved
Permission to use, copy, modify, and distribute this software and
its documentation for any purpose and without fee is hereby
granted, provided that the above copyright notice appear in all
copies and that both that the copyright notice and this
permission notice and warranty disclaimer appear in supporting
documentation, and that the name of Lucent or any of its entities
not be used in advertising or publicity pertaining to
distribution of the software without specific, written prior
permission.
LUCENT DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE,
INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS.
IN NO EVENT SHALL LUCENT OR ANY OF ITS ENTITIES BE LIABLE FOR ANY
SPECIAL, INDIRECT OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER
IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION,
ARISING OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF
THIS SOFTWARE.
****************************************************************/
/* Please send bug reports to David M. Gay (dmg at acm dot org,
* with " at " changed at "@" and " dot " changed to "."). */
#include "gdtoaimp.h"
float
#ifdef KR_headers
strtof(s, sp) CONST char *s; char **sp;
#else
strtof(CONST char *s, char **sp)
#endif
{
static FPI fpi0 = { 24, 1-127-24+1, 254-127-24+1, 1, SI };
ULong bits[1];
Long exp;
int k;
union { ULong L[1]; float f; } u;
#ifdef Honor_FLT_ROUNDS
#include "gdtoa_fltrnds.h"
#else
#define fpi &fpi0
#endif
k = strtodg(s, sp, fpi, &exp, bits);
switch(k & STRTOG_Retmask) {
case STRTOG_NoNumber:
case STRTOG_Zero:
u.L[0] = 0;
break;
case STRTOG_Normal:
case STRTOG_NaNbits:
u.L[0] = (bits[0] & 0x7fffff) | ((exp + 0x7f + 23) << 23);
break;
case STRTOG_Denormal:
u.L[0] = bits[0];
break;
case STRTOG_NoMemory:
errno = ERANGE;
/* FALLTHROUGH */
case STRTOG_Infinite:
u.L[0] = 0x7f800000;
break;
case STRTOG_NaN:
u.L[0] = f_QNAN;
}
if (k & STRTOG_Neg)
u.L[0] |= 0x80000000L;
return u.f;
}
DEF_STRONG(strtof);
```
|
Fressain () is a commune in the Nord department in northern France.
Heraldry
See also
Communes of the Nord department
References
Communes of Nord (French department)
|
```css
/* line 3, ../../src/scss/sidr/_base.scss */
.sidr {
/* Default Settings */
display: none;
position: absolute;
position: fixed;
top: 0;
height: 100%;
z-index: 999999;
width: 260px;
overflow-x: none;
overflow-y: auto;
/* Theme Settings */
font-family: "lucida grande", tahoma, verdana, arial, sans-serif;
font-size: 15px;
background: #f8f8f8;
color: #333333;
-webkit-box-shadow: inset 0 0 5px 5px #ebebeb;
-moz-box-shadow: inset 0 0 5px 5px #ebebeb;
box-shadow: inset 0 0 5px 5px #ebebeb;
}
/* line 15, ../../src/scss/sidr/_base.scss */
.sidr .sidr-inner {
padding: 0 0 15px;
}
/* line 18, ../../src/scss/sidr/_base.scss */
.sidr .sidr-inner > p {
margin-left: 15px;
margin-right: 15px;
}
/* line 24, ../../src/scss/sidr/_base.scss */
.sidr.right {
left: auto;
right: -260px;
}
/* line 29, ../../src/scss/sidr/_base.scss */
.sidr.left {
left: -260px;
right: auto;
}
/* line 41, ../../src/scss/sidr/_base.scss */
.sidr h1, .sidr h2, .sidr h3, .sidr h4, .sidr h5, .sidr h6 {
font-size: 11px;
font-weight: normal;
padding: 0 15px;
margin: 0 0 5px;
color: #333333;
line-height: 24px;
background-image: -webkit-gradient(linear, 50% 0%, 50% 100%, color-stop(0%, #ffffff), color-stop(100%, #dfdfdf));
background-image: -webkit-linear-gradient(#ffffff, #dfdfdf);
background-image: -moz-linear-gradient(#ffffff, #dfdfdf);
background-image: -o-linear-gradient(#ffffff, #dfdfdf);
background-image: linear-gradient(#ffffff, #dfdfdf);
-webkit-box-shadow: 0 5px 5px 3px rgba(0, 0, 0, 0.2);
-moz-box-shadow: 0 5px 5px 3px rgba(0, 0, 0, 0.2);
box-shadow: 0 5px 5px 3px rgba(0, 0, 0, 0.2);
}
/* line 52, ../../src/scss/sidr/_base.scss */
.sidr p {
font-size: 13px;
margin: 0 0 12px;
}
/* line 55, ../../src/scss/sidr/_base.scss */
.sidr p a {
color: rgba(51, 51, 51, 0.9);
}
/* line 60, ../../src/scss/sidr/_base.scss */
.sidr > p {
margin-left: 15px;
margin-right: 15px;
}
/* line 65, ../../src/scss/sidr/_base.scss */
.sidr ul {
display: block;
margin: 0 0 15px;
padding: 0;
border-top: 1px solid #dfdfdf;
border-bottom: 1px solid white;
}
/* line 72, ../../src/scss/sidr/_base.scss */
.sidr ul li {
display: block;
margin: 0;
line-height: 48px;
border-top: 1px solid white;
border-bottom: 1px solid #dfdfdf;
}
/* line 81, ../../src/scss/sidr/_base.scss */
.sidr ul li:hover, .sidr ul li.active, .sidr ul li.sidr-class-active {
border-top: none;
line-height: 49px;
}
/* line 85, ../../src/scss/sidr/_base.scss */
.sidr ul li:hover > a, .sidr ul li:hover > span, .sidr ul li.active > a, .sidr ul li.active > span, .sidr ul li.sidr-class-active > a, .sidr ul li.sidr-class-active > span {
-webkit-box-shadow: inset 0 0 15px 3px #ebebeb;
-moz-box-shadow: inset 0 0 15px 3px #ebebeb;
box-shadow: inset 0 0 15px 3px #ebebeb;
}
/* line 90, ../../src/scss/sidr/_base.scss */
.sidr ul li a, .sidr ul li span {
padding: 0 15px;
display: block;
text-decoration: none;
color: #333333;
}
/* line 97, ../../src/scss/sidr/_base.scss */
.sidr ul li ul {
border-bottom: none;
margin: 0;
}
/* line 100, ../../src/scss/sidr/_base.scss */
.sidr ul li ul li {
line-height: 40px;
font-size: 13px;
}
/* line 104, ../../src/scss/sidr/_base.scss */
.sidr ul li ul li:last-child {
border-bottom: none;
}
/* line 110, ../../src/scss/sidr/_base.scss */
.sidr ul li ul li:hover, .sidr ul li ul li.active, .sidr ul li ul li.sidr-class-active {
border-top: none;
line-height: 41px;
}
/* line 114, ../../src/scss/sidr/_base.scss */
.sidr ul li ul li:hover > a, .sidr ul li ul li:hover > span, .sidr ul li ul li.active > a, .sidr ul li ul li.active > span, .sidr ul li ul li.sidr-class-active > a, .sidr ul li ul li.sidr-class-active > span {
-webkit-box-shadow: inset 0 0 15px 3px #ebebeb;
-moz-box-shadow: inset 0 0 15px 3px #ebebeb;
box-shadow: inset 0 0 15px 3px #ebebeb;
}
/* line 119, ../../src/scss/sidr/_base.scss */
.sidr ul li ul li a, .sidr ul li ul li span {
color: rgba(51, 51, 51, 0.8);
padding-left: 30px;
}
/* line 128, ../../src/scss/sidr/_base.scss */
.sidr form {
margin: 0 15px;
}
/* line 132, ../../src/scss/sidr/_base.scss */
.sidr label {
font-size: 13px;
}
/* line 146, ../../src/scss/sidr/_base.scss */
.sidr input[type="text"],
.sidr input[type="password"],
.sidr input[type="date"],
.sidr input[type="datetime"],
.sidr input[type="email"],
.sidr input[type="number"],
.sidr input[type="search"],
.sidr input[type="tel"],
.sidr input[type="time"],
.sidr input[type="url"],
.sidr textarea, .sidr select {
width: 100%;
font-size: 13px;
padding: 5px;
-webkit-box-sizing: border-box;
-moz-box-sizing: border-box;
box-sizing: border-box;
margin: 0 0 10px;
-webkit-border-radius: 2px;
-moz-border-radius: 2px;
-ms-border-radius: 2px;
-o-border-radius: 2px;
border-radius: 2px;
border: none;
background: rgba(0, 0, 0, 0.1);
color: rgba(51, 51, 51, 0.6);
display: block;
clear: both;
}
/* line 160, ../../src/scss/sidr/_base.scss */
.sidr input[type=checkbox] {
width: auto;
display: inline;
clear: none;
}
/* line 167, ../../src/scss/sidr/_base.scss */
.sidr input[type=button],
.sidr input[type=submit] {
color: #f8f8f8;
background: #333333;
}
/* line 171, ../../src/scss/sidr/_base.scss */
.sidr input[type=button]:hover,
.sidr input[type=submit]:hover {
background: rgba(51, 51, 51, 0.9);
}
```
|
```turing
#!./perl
our $DBM_Class = 'SDBM_File';
require '../../t/lib/dbmt_common.pl';
```
|
```java
/* ===========================================================
* JFreeChart : a free chart library for the Java(tm) platform
* ===========================================================
*
*
* Project Info: path_to_url
*
* This library is free software; you can redistribute it and/or modify it
* (at your option) any later version.
*
* This library is distributed in the hope that it will be useful, but
* WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
* or FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public
*
* You should have received a copy of the GNU Lesser General Public
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301,
* USA.
*
* [Oracle and Java are registered trademarks of Oracle and/or its affiliates.
* Other names may be trademarks of their respective owners.]
*
* ------------
* Overlay.java
* ------------
*
* Original Author: David Gilbert;
* Contributor(s): -;
*
*/
package org.jfree.chart.swing;
import java.awt.Graphics2D;
/**
* An {@code Overlay} is anything that can be drawn over top of a chart to add
* additional information to the chart. This interface defines the operations
* that must be supported for an overlay that can be added to a
* {@link ChartPanel} in Swing.
* <br><br>
* Note: if you are using JavaFX rather than Swing, then you need to look at
* the {@code OverlayFX} interface in the <b>JFreeChart-FX</b> project.
*/
public interface Overlay {
/**
* Paints the visual representation of the overlay. This method will be
* called by the {@link ChartPanel} after the underlying chart has been
* fully rendered. When implementing this method, the {@code chartPanel}
* argument can be used to get state information from the chart (you can,
* for example, extract the axis ranges for the chart).
*
* @param g2 the graphics target (never {@code null}).
* @param chartPanel the chart panel (never {@code null}).
*/
void paintOverlay(Graphics2D g2, ChartPanel chartPanel);
/**
* Registers a change listener with the overlay. Typically this method
* not be called by user code, it exists so that the {@link ChartPanel}
* can register and receive notification of changes to the overlay (such
* changes will trigger an automatic repaint of the chart).
*
* @param listener the listener ({@code null} not permitted).
*
* @see #removeChangeListener(org.jfree.chart.event.OverlayChangeListener)
*/
void addChangeListener(OverlayChangeListener listener);
/**
* Deregisters a listener from the overlay.
*
* @param listener the listener ({@code null} not permitted).
*
* @see #addChangeListener(org.jfree.chart.event.OverlayChangeListener)
*/
void removeChangeListener(OverlayChangeListener listener);
}
```
|
```java
/*
This library is free software; you can redistribute it and/or
modify it under the terms of the GNU General Public
version 2 of the license, or (at your option) any later version.
*/
package ee.ioc.cs.jbe.browser.detail.attributes.code;
import javax.swing.JTextField;
import javax.swing.tree.TreePath;
import org.gjt.jclasslib.util.ExtendedJLabel;
import ee.ioc.cs.jbe.browser.BrowserServices;
import ee.ioc.cs.jbe.browser.codeedit.InputFieldException;
import ee.ioc.cs.jbe.browser.detail.FixedListDetailPane;
/**
Detail pane showing miscellaneous information of a <tt>Code</tt> attribute
without substructure.
@author <a href="mailto:jclasslib@ej-technologies.com">Ingo Kegel</a>
@author Ando Saabas
@version $Revision: 1.8 $ $Date: 2006/09/04 15:43:18 $
Edited by Ando Saabas
*/
public class MiscDetailPane extends FixedListDetailPane {
private ExtendedJLabel lblCodeLength;
private JTextField maxLocalsField;
private JTextField maxStackField;
/**
Constructor.
@param services the associated browser services.
*/
public MiscDetailPane(BrowserServices services) {
super(services);
}
protected void setupLabels() {
maxLocalsField = new JTextField(4);
maxStackField = new JTextField(4);
addDetailPaneEntry(normalLabel("Maximum stack depth:"),
maxStackField);
addDetailPaneEntry(normalLabel("Maximum local variables:"),
maxLocalsField);
addDetailPaneEntry(normalLabel("Code length:"),
lblCodeLength = highlightLabel());
}
public void show(TreePath treePath) {
super.show(treePath);
}
public void setMaxStack(int maxStack) {
maxStackField.setText(Integer.toString(maxStack));
}
public void setMaxLocals(int maxLocals) {
maxLocalsField.setText(Integer.toString(maxLocals));
}
public void setCodeLength(int codeLength) {
lblCodeLength.setText(codeLength);
}
public int getMaxStack() throws InputFieldException{
try {
int i = Integer.parseInt(maxStackField.getText());
return i;
} catch (NumberFormatException nfe) {
throw new InputFieldException(maxStackField.getText(), "Maximum stack");
}
}
public int getMaxLocals() throws InputFieldException{
try {
int i = Integer.parseInt(maxLocalsField.getText());
return i;
} catch (NumberFormatException nfe) {
throw new InputFieldException(maxLocalsField.getText(), "Maximum locals");
}
}
}
```
|
The Sacred Band of Thebes (Ancient Greek: , Hierós Lókhos) was a troop of select soldiers, consisting of 150 pairs of male lovers which formed the elite force of the Theban army in the 4th century BC, ending Spartan domination. Its predominance began with its crucial role in the Battle of Leuctra in 371 BC. It was annihilated by Philip II of Macedon in the Battle of Chaeronea in 338 BC.
Formation
The earliest surviving record of the Sacred Band by name was in 324 BC, in the oration Against Demosthenes by the Athenian logographer Dinarchus. He mentions the Sacred Band as being led by the general Pelopidas and, alongside Epaminondas who commanded the army of Thebes (Boeotia), were responsible for the defeat of the Spartans at the decisive Battle of Leuctra (371 BC).
Plutarch (46–120 AD), a native of the village of Chaeronea, is the source of the most substantial surviving account of the Sacred Band. He records that the Sacred Band was originally formed by the boeotarch Gorgidas, shortly after the expulsion of the Spartan garrison occupying the Theban citadel of Cadmea. The 2nd century AD Macedonian author Polyaenus in his Stratagems in War also records Gorgidas as the founder of the Sacred Band. However, Dio Chrysostom (c. 40–120 AD), Hieronymus of Rhodes (c. 290–230 BC), and Athenaeus of Naucratis (c. 200 AD) credit Epaminondas instead.
The exact date of the Sacred Band's creation, and whether it was created before or after the Symposium of Plato (c. 424–347 BC) and the similarly titled Symposium by his rival Xenophon (c. 430–354 BC), has also long been debated. The generally accepted date of the Sacred Band's creation is between 379 and 378 BC. Prior to this, there were references to elite Theban forces also numbering 300. Herodotus (c.484–425 BC) and Thucydides (c. 460–395 BC) both record an elite force of 300 Thebans allied with the Persians, who were annihilated by Athenians in the Battle of Plataea (479 BC). Herodotus describes them as "the first and the finest" () among Thebans. Diodorus also records 300 picked men () present in the Battle of Delium (424 BC), composed of heníochoi (, "charioteers") and parabátai (, "those who walk beside"). Though none of these mention the Sacred Band by name, these may have referred to the Sacred Band or at least its precursors. Historian John Kinloch Anderson believes that the Sacred Band was indeed present in Delium, and that Gorgidas did not establish it, but merely reformed it.
In the old debate surrounding Xenophon's and Plato's works, the Sacred Band has figured prominently as a possible way of dating which of the two wrote their version of Symposium first. Xenophon's Socrates in his Symposium disapprovingly mentions the practice of placing lovers beside each other in battle in the city-states of Thebes and Elis, arguing that while the practice was acceptable to them, it was shameful for Athenians. Both Plato and Xenophon were Athenians. According to the British classical scholar Sir Kenneth Dover, this was a clear allusion to the Sacred Band, reflecting Xenophon's contemporary, albeit anachronistic, awareness of the Theban practice, as the dramatic date of the work itself is c. 421 BC.
However, it is the speech of the character Phaedrus in Plato's Symposium referring to an "army of lovers" that is most famously connected with the Sacred Band; even though it does not technically refer to the Sacred Band, since the army referred to is hypothetical. Dover argues Plato wrote his Symposium first since Plato's Phaedrus uses language that implies that the organization does not yet exist. He acknowledges, however, that Plato may have simply put the hypothesis in the mouth of Phaedrus according to the supposed earlier dramatic date of the work (c. 416 BC). It only shows that Plato was more mindful of his chronology in his Symposium than Xenophon, and proves that he was actually quite aware of the Sacred Band in his time.
Composition
According to Plutarch, the 300 hand-picked men were chosen by Gorgidas purely for ability and merit, regardless of social class. It was composed of 150 male couples, each pair consisting of an older erastês (, "lover") and a younger erômenos (, "beloved"). Athenaeus of Naucratis also records the Sacred Band as being composed of "lovers and their favorites, thus indicating the dignity of the god Eros in that they embrace a glorious death in preference to a dishonorable and reprehensible life", while Polyaenus describes the Sacred Band as being composed of men "devoted to each other by mutual obligations of love". The origin of the "sacred" appellation of the Sacred Band is unexplained by Dinarchus and other historians. But Plutarch claims that it was due to an exchange of sacred vows between lover and beloved at the shrine of Iolaus (one of the lovers of Heracles) at Thebes. He also tangentially mentions Plato's characterization of the lover as a "friend inspired of God".
The Sacred Band was stationed in Cadmea as a standing force, likely as defense against future attempts by foreign forces to take the citadel. It was occasionally referred to as the "City Band" (), due to their military training and housing being provided at the expense of the Boeotian polis. Their regular training included wrestling and dance. The historian James G. DeVoto points out that Gorgidas previously served as a hipparch (cavalry officer), therefore equestrian training was also likely provided. The exact ages of the unit's members are not recorded in ancient testimonies. However, comparing them with the Spartan elite unit hippeis () and the Athenian epheboi (ἔφηβοι) recruits, DeVoto estimates that trainees were inducted as full members to the Sacred Band at the ages of 20 to 21, whereupon they were given a full set of armor by their erastai. They likely ended their service at age 30.
Military history
According to Plutarch, Gorgidas originally distributed the members of the Sacred Band among the front ranks of the phalanxes of regular infantry. In 375 BC, the command of the band was transferred to the younger boeotarch Pelopidas, one of the original Theban exiles who had led the forces who recaptured Cadmea. Under Pelopidas, the Sacred Band was united as a single unit of shock troops. Their main function was to cripple the enemy by engaging and killing their best men and leaders in battle.
Invasions of Agesilaus II
The Sacred Band first saw action in 378 BC, at the beginning of the Boeotian War. It was during the famous stand-off between the Athenian mercenary commander (and later strategos) Chabrias (d. 357 BC) and the Spartan King Agesilaus II (444 BC–360 BC). Prior to the creation of the Sacred Band under Gorgidas, the Athenians had helped the Theban exiles retake control of Thebes and the citadel of Cadmea from Sparta. This was followed by Athens openly entering into an alliance with Thebes against Sparta. In the summer of 378 BC, Agesilaus led a Spartan expedition against Thebes from the Boeotian city of Thespiae (then still allied to Sparta).
The Spartan forces were held up for several days by Theban forces manning the earthen stockades at the perimeter of Theban territory. The Spartans eventually breached the fortifications and entered the Theban countryside, devastating the Theban fields in their wake. Though the Athenians had by this time joined the Theban forces, they were still outnumbered by the Spartans. With the fall of the stockades, they were left with two choices, either to retreat back to the defensible walls of Thebes or to hold their ground and face the Spartans in the open. They chose the latter and arrayed their forces along the crest of a low sloping hill, opposite the Spartan forces. Gorgidas and the Sacred Band occupied the front ranks of the Theban forces on the right, while Chabrias and an experienced force of mercenary hoplites occupied the front ranks of the Athenian forces on the left.
Agesilaus first sent out skirmishers to test the combined Theban and Athenian lines. These were easily dispatched by the Theban and Athenian forces, probably by their more numerous cavalry. Agesilaus then commanded the entire Spartan army to advance. He may have hoped that the sight of the massed Spartan forces resolutely moving forward would be enough to intimidate the Theban and Athenian forces into breaking ranks. The same tactic had worked for Agesilaus against Argive forces in the Battle of Coronea (394 BC).
It was during this time that Chabrias gave his most famous command. With scarcely separating the two armies, Agesilaus was expecting the Theban and Athenian forces to charge at any moment. Instead, Chabrias ordered his men to stand at ease. In unison, his mercenary hoplites immediately assumed the resting posture—with the spear remaining pointing upwards instead of towards the enemy, and the shield propped against the left knee instead of being hoisted at the shoulders. Gorgidas, on seeing this, also commanded the Sacred Band to follow suit, which they did with the same military drill precision and confidence. The audacity of the maneuver and the discipline of the execution was such that Agesilaus halted the advance. Seeing that his attempts to provoke the Theban and Athenian forces to fight on lower ground were unsuccessful, Agesilaus eventually thought it wiser to withdraw his forces back to Thespiae.
Shortly after the stand-off in Thebes, Agesilaus disbanded his army in Thespiae and returned to Peloponnesos through Megara. He left the general Phoebidas as his harmost (military governor) at Thespiae, the same general responsible for the Spartan seizure of the citadel of Cadmea in 382 BC. Phoebidas began making various raids into Theban territory using the Spartans under his command and Thespian conscripts. These forays became so destructive that by the end of the summer, the Thebans went out in force against Thespiae under the command of Gorgidas.
Phoebidas engaged the advancing Theban army with his peltasts. The harrying of the light infantry apparently proved too much for the Thebans and they started to retreat. Phoebidas, hoping for a rout, rashly pursued them closely. However, the Theban forces suddenly turned around and charged Phoebidas' forces. Phoebidas was killed by the Theban cavalry. His peltasts broke ranks and fled back to Thespiae pursued by Theban forces. Aside from Polyaenus, none of these accounts mention the Sacred Band by name, but given that they were under the command of Gorgidas, they are likely to have been part of Theban forces involved.
Not long afterwards, Agesilaus mounted a second expedition against Thebes. After a series of skirmishes which he won with some difficulty, he was forced again to withdraw when the Theban army came out full force as he approached the city. Diodorus observes at this point that the Thebans thereafter faced the Spartans with confidence. Gorgidas disappears from history between 377 and 375, during which the command of the Sacred Band was apparently transferred to Pelopidas.
Battle of Tegyra
As a single unit under Pelopidas, the first recorded victory of the Sacred Band was at the Battle of Tegyra (375 BC). It occurred near the Boeotian city of Orchomenus, then still an ally of Sparta. Hearing reports that the Spartan garrison in Orchomenus had left for Locris, Pelopidas quickly set out with the Sacred Band and a few cavalry, hoping to capture it in their absence. They approached the city through the northeastern route since the waters of Lake Copais were at their fullest during that season. Upon reaching the city, they learned that a new mora had been sent from Sparta to reinforce Orchomenus. Unwilling to engage the new garrison, Pelopidas decided to retreat back to Thebes, retracing their northeastern route along Lake Copais. However, they only reached as far as the shrine of Apollo of Tegyra before encountering the returning Spartan forces from Locris.
The Spartans were composed of two morai led by the polemarchoi Gorgoleon and Theopompus. They outnumbered the Thebans at least two to one. According to Plutarch, upon seeing the Spartans, one Theban allegedly told Pelopidas "We are fallen into our enemy's hands" to which Pelopidas replied, "And why not they into ours?" He then ordered his cavalry to ride up from the rear and charge while he reformed the Sacred Band into an abnormally dense formation, hoping to at least cut through the numerically superior Spartan lines. The Spartans advanced, confident in their numbers, only to have their leaders killed immediately in the opening clashes. Leaderless and encountering forces equal in discipline and training for the first time in the Sacred Band, the Spartans faltered and opened their ranks, expecting the Thebans to pass through and escape. Instead, Pelopidas surprised them by using the opening to flank the Spartans. The Spartans were completely routed, with considerable loss of life. The Thebans didn't pursue the fleeing survivors, mindful of the remaining Spartan mora stationed in Orchomenus less than away. They stripped the dead and set up a tropaion (τρόπαιον, a commemorative trophy left at the site of a battle victory) before continuing on to Thebes. Having proven their worth, Pelopidas kept the Sacred Band as a separate tactical unit in all subsequent battles.
An account of the battle was mentioned both by Diodorus and Plutarch, both based heavily on the report by Ephorus. Xenophon conspicuously omits any mention of the Theban victory in his Hellenica, though this has traditionally been ascribed to Xenophon's strong anti-Theban and pro-Spartan sentiments. An obscure allusion to Orchomenus in Hellenica, however, implies that Xenophon was aware of the Spartan defeat.
The exact number of the belligerents on each side varies by account. Diodorus puts the number of Thebans at 500 against the Spartans' 1,000 (each mora consisting of 500 men), apparently basing it on Ephorus' original figures. Plutarch puts the number of the Thebans at 300, and acknowledges three sources for the number of Spartans: 1000 by the account of Ephorus; 1,400 by Callisthenes (c. 360–328 BC); or 1,800 by Polybius (c. 200–118 BC). Some of these numbers may have been exaggerated due to the overall significance of the battle. The battle, while minor, was remarkable for being the first time a Spartan force had been defeated in pitched battle, dispelling the myth of Spartan invincibility. It left a deep impression in Greece and boosted the morale among Boeotians, foreshadowing the later Battle of Leuctra. In Plutarch's own words:
Shortly after this, the Athenians initiated the Common Peace of 375 BC (Κοινὴ Εἰρήνη, Koine Eirene) among Greek city-states. According to Xenophon, they were alarmed at the growing power of Thebes and weary of fending off Spartan fleets alone as the Thebans were not contributing any money to maintaining the Athenian fleet. However this broke down soon after in 374 BC, when Athens and Sparta resumed hostilities over Korkyra (modern Corfu). During this time period, Athens also gradually became hostile to Thebes. While Athens and Sparta were busy fighting each other, Thebes resumed her campaigns against the autonomous pro-Spartan Boeotian poleis. Thespiae and Tanagra were subjugated and formally became part of the reestablished democratic Boeotian confederacy. In 373 BC, Thebans under the command of the boeotarch Neocles attacked and razed its traditional rival, the Boeotian city of Plataea. The Plataean citizens were allowed to leave alive, but they were reduced to being refugees and sought sanctuary in Athens. Of the pro-Spartan Boeotian poleis, only Orchomenus remained.
By this time, Thebes had also started attacking Phocian poleis allied to Sparta. Pelopidas is again mentioned as the commander of the abortive Theban siege of the Phocian city of Elateia (c. 372 BC). In response to the Theban army outside the city's walls, the Phocian general Onomarchus brought out all the inhabitants of the city (including the elderly, women, and children) and locked the gates. He then placed the non-combatants directly behind the defenders of Elateia. On seeing this, Pelopidas withdrew his forces, recognizing that the Phocians would fight to the death to protect their loved ones.
By 371 BC, there was another attempt to revive the King's Peace to curb the rise of Thebes. It was initiated by either the Athenians or the Persians (perhaps at the prompting of the Spartans). The Spartans also sent a large force led by King Cleombrotus I (Sparta having two kings simultaneously for most of its history) to Phocis, ready to invade Boeotia if the Thebans refused to attend the peace conference or accept its terms.
Battle of Leuctra
Epaminondas' refusal to accept the terms of the peace conference of 371 BC excluded Thebes from the peace treaty and provided Sparta with the excuse to declare war.
Shortly thereafter the army of Cleombrotus was ordered to invade Boeotia. Cleombrotus' army crossed the Phocian-Boeotian border into Chaeronea then halted, perhaps hoping that the Thebans might change their mind. The Thebans however were committed to a fight. Cleombrotus then moved inland, following the eastward road towards Thebes, until he reached the Boeotian village of Leuctra (modern Lefktra, Plataies) near the southwestern end of the Theban plain. There they were met by the main Theban army. The two armies pitched their camps opposite each other on two low ridges respectively. The battleground between them was about wide.
The Spartan army numbered about 10,000 hoplites, 1,000 light infantry, and 1,000 cavalry. However, only about 700 hoplites of the Spartan army were composed of spartiates (Spartan citizens), the rest were conscripted troops from Spartan subject states (the perioeci) forced to fight. They were arrayed traditionally, in which the hoplites were formed into phalanxes about eight to twelve men deep. Cleombrotus positioned himself and the spartiate hoplites (including the elite royal guard of 300 Hippeis) in the Spartan right wing, the traditional position of honor in Greek armies. Cleombrotus' only tactical innovation was the placing of his cavalry in front of his troops.
The Theban army was outnumbered by the Spartans, being composed of only about 6,000 hoplites (including the Sacred Band), 1,500 light infantry, and 1,000 cavalry. Anticipating the standard Spartan tactic of flanking enemy armies with their right wing, Epaminondas concentrated his forces on his own left wing, directly opposite the strongest Spartiate phalanx, led by Cleombrotus. Here, the massed Theban phalanx was arrayed into a highly unconventional depth of fifty men. The rest of the Theban lines were reduced to depths of only four to at most eight men because of this. Epaminondas also copied Cleombrotus by placing his cavalry in front of the Theban lines. The original position of the Sacred Band being led by Pelopidas is unknown. Some military historians believe Epaminondas placed Pelopidas and the Sacred Band behind the main hoplite phalanx, others believe he put it in front of the main hoplite phalanx and behind the cavalry, while others put it on the front left corner of the main hoplite phalanx (the most likely). Either way, the Sacred Band is definitely known to have been on the left wing, close to the main Theban forces and detached enough to be able to maneuver freely.
The battle opened with a cavalry charge by both armies. The Spartan cavalry were quickly defeated by the superior Theban cavalry and were chased back to their own side. Their disorderly retreat disrupted the battle lines of the Spartan heavy infantry and, because of the resulting chaos and the dust stirred up, the Spartans were unable to observe the highly unusual advance of the Theban army until the last moment. Epaminondas had ordered his troops to advance diagonally, such that the left wing of the Theban army (with its concentration of forces) would impact with the right wing of the Spartan army well before the other weaker phalanxes. The furthest right wing of the Theban phalanx was even retreating to make this possible. This is the first recorded instance of the military formation later known as the oblique order. The Theban cavalry also helped by continuing to carry out intermittent attacks along the Spartan battle lines, holding their advance back.
By the time the Spartans realized that something unusual was happening it was already too late. Shortly before the Theban left wing made contact, the Spartans hastily stretched out their right wing in an attempt to outflank and engulf the rapidly approaching Thebans. This was a traditional tactic and, once the Thebans were in range, the stretched wing would then be brought back in an encircling movement. Acting under his own initiative, Pelopidas quickly led the Sacred Band ahead of the Theban left wing to intercept the Spartan maneuver before it could be completed. They succeeded in fixing the Spartans in place until the rest of the Theban heavy infantry finally smashed into the Spartan right wing. The sheer number of Thebans overwhelmed the Spartan right wing quickly. The number of Spartan casualties amounted to about 1,000 dead, among whom were 400 Spartiates and their own king. The Spartan right flank were forced to retreat (after retrieving the body of Cleombrotus). Seeing the Spartiates fleeing in disarray, the Perioeci phalanxes also broke ranks and retreated. Although some Spartans were in favor of resuming the battle in order to recover the bodies of their dead, the allied Perioeci of the Spartan left wing were less than willing to continue fighting (indeed some of them were quite pleased at the turn of events). The remaining polemarchoi eventually decided to request a truce, which the Thebans readily granted. The Spartan dead were returned and a tropaion was set up on the battlefield by the Thebans to commemorate their victory.
According to Pausanias (c. 2nd century AD), the Battle of Leuctra was the most decisive battle ever fought by Greeks against Greeks. Leuctra established Theban independence from Spartan rule and laid the groundwork for the expansion of Theban power, but possibly also for the eventual supremacy of Philip II of Macedon.
Battle of Chaeronea
Defeat came at the Battle of Chaeronea (338 BC), the decisive contest in which Philip II of Macedon, with his son Alexander, extinguished Theban hegemony. The battle is the culmination of Philip's campaign into central Greece in preparation for a war against Persia. It was fought between the Macedonians and their allies and an alliance of Greek city-states led by Athens and Thebes. Diodorus records that the numbers involved for the two armies were more or less equal, both having around 30,000 men and 2,000 cavalry.
The traditional hoplite infantry was no match for the novel long-speared Macedonian phalanx: the Theban army and its allies broke and fled, but the Sacred Band, although surrounded and overwhelmed, refused to surrender. The Thebans of the Sacred Band held their ground and Plutarch records that all 300 fell where they stood beside their last commander, Theagenes. Their defeat at the battle was a significant victory for Philip, since until then, the Sacred Band was regarded as invincible throughout all of Ancient Greece. Plutarch records that Philip II, on encountering the corpses "heaped one upon another", understanding who they were, wept and exclaimed,
Though the significance of the battle was well-documented by ancient scholars, there is little surviving information on the deployment of the armies involved. Most modern scholars (including N.G.L. Hammond and George Cawkwell) credit Alexander as having led a cavalry wing. James G. DeVoto, likewise, says in The Theban Sacred Band that Alexander had deployed his cavalry behind the Macedonian hoplites, apparently permitting "a Theban break-through in order to effect a cavalry assault while his hoplites regrouped". Other historians however argue that Alexander actually commanded hoplites armed with sarissas (pikes), rather than cavalry, especially since Plutarch also mentions that the Sacred Band fell to "lances of the Macedonian phalanx". Plutarch and Diodorus both credit Alexander as being the first to engage the Sacred Band.
Archaeology
Trophy of the Battle of Leuctra
After the defeat of Cleombrotus' forces in the Battle of Leuctra, a tropaion was set up on the battlefield by the Thebans to commemorate their victory. The tropaion was later replaced by a permanent monument, an unprecedented move by the Thebans as tropaia were designed to be ephemeral. The original appearance of the monument is attested by contemporary coins of the period and showed that it took the form of a tree trunk mounted upon a cylindrical pedestal carved with metopes, triglyphs, and a series of stone shields. On the tree trunk itself is affixed the shields, weapons, and armor of the defeated Spartans. The base of the monument still survives to this day.
Lion of Chaeronea
Pausanias in his Description of Greece mentions that the Thebans had erected a gigantic statue of a lion near the village of Chaeronea, surmounting the polyandrion (, common tomb) of the Thebans killed in battle against Philip. The Greek historian Strabo (c. 64 BC–24 AD) also mentions "tombs of those who fell in the battle" erected at public expense in Chaeronea.
In 1818, a British architect named George Ledwell Taylor spent a summer in Greece with two friends at Livadeia. On June 3, they decided to go horseback riding to the nearby village of Chaeronea using Pausanias' Description of Greece as a guidebook. Two hours away from the village, Taylor's horse momentarily stumbled on a piece of marble jutting from the ground. Looking back at the rock, he was struck by its appearance of being sculpted and called for their party to stop. They dismounted and dug at it with their riding-whips, ascertaining that it was indeed sculpture. They enlisted the help of some nearby farmers until they finally uncovered the massive head of a stone lion which they recognized as the same lion mentioned by Pausanias. Parts of the statue had broken off and a good deal of it still remained buried. They immediately reported their discovery when they returned to Athens.
A common story, still often reported to this day, is that the lion was smashed to pieces during the subsequent Greek War of Independence (1821–1829), even using dynamite, by the klepht leader Odysseas Androutsos, who supposedly hoped to find it filled with treasure. This tale was current already in the 1830s, but has been strongly refuted. The five pieces (head, neck, chest, and forelegs) into which the statue was divided for most of the 19th century, before its reconstruction in 1902, bore no evidence of an explosion, but were cleanly cut, likely being the original pieces that formed the statue. Androutsos is held to have been the one to unearth the statue during his tenure as local military governor by Ali Pasha of Yanina in 1819, but the statue had likely fallen apart due to the poor quality of the pedestal's material.
Offers in the late 19th century by the British archeologist Cecil Harcourt Smith to fund the restoration of Lion of Chaeronea were initially refused by the Greeks. In 1902, however, permission was granted and the monument was pieced back together with funding by the Order of Chaeronea. The lion, which stands about high, was mounted on a reconstructed pedestal about high.
In the late 19th century, excavations in the area revealed that the monument stood at the edge of a quadrangular enclosure. The skeletons of 254 men laid out in seven rows were found buried within it. A tumulus near the monument was also tentatively identified as the site of the Macedonian polyandrion where the Macedonian dead were cremated. Excavation of the tumulus between 1902 and 1903 by the archeologist Georgios Soteriades confirmed this. At the center of the mound, about deep, was a layer of ashes, charred logs, and bones about thick. Recovered among these were vases and coins dated to the 4th century BC. Swords and remarkably long spearheads measuring about were also discovered, which Soteriades identified as the Macedonian sarissas.
The skeletons within the enclosure of the lion monument are generally accepted to be the remains of the Sacred Band, as the number given by Plutarch was probably an approximation. However, historians such as Nicholas Geoffrey Lemprière Hammond, Karl Julius Beloch, and Vincenzo Costanzi do not believe that the lion monument marks the location of the Sacred Band dead. Hammond claims it was the place where Philip turned his army around during the Battle of Chaeronea and believes that it contains the members of the Macedonian right flank who perished. He argues that it is highly improbable that the Thebans would be able to commemorate their dead within Philip's lifetime with such a massive and obviously expensive monument.
The historian William K. Pritchett criticizes Hammond's rationale as "subjective" and counters it with a passage from Historiarum Philippicarum Libri XLIV of the 3rd-century AD Roman historian Justin. In addition to Pausanias and Strabo, Justin also clearly says that Philip forced the Thebans to pay for the privilege of burying (not cremating) their dead. Therefore, the cremated remains are likely to be Macedonian, while the remains around the lion were the Sacred Band. Philip, after all, was known for his ability to inflict unnecessary cruelty when it served a greater purpose. He further points out that questioning the honesty of Pausanias is unwarranted, as any well-informed Greek then would probably know the ascription of the monument even centuries after the battle; Pausanias' knowledge of topography was not second-hand and his testimony was echoed independently by other ancient sources such as Strabo and Justin. Indeed, Pausanias' Description of Greece has proved to be an accurate and important guide to modern archeologists in rediscovering the locations of other ancient Greek monuments and buildings.
Historicity
The historicity of the Sacred Band is largely accepted by historians; it is detailed in the writings of numerous classical authors, especially Plutarch. Noted classical historians such as John Kinloch Anderson and George Cawkwell accept Plutarch's Life of Pelopidas, which contains the most detailed account of the Sacred Band, as a highly reliable account of the events, in contrast to Xenophon's patchy treatment of Theban history. Other noted classical scholars like Frank William Walbank and Felix Jacoby have also defended Callisthenes' descriptions of land battles in the past. Walbank commented that his depictions of the Battle of the Eurymedon, Gaugamela, and Tegyra (all surviving through Plutarch) are quite adequate. While Jacoby, responding to claims that Callisthenes was unreliable in accounts of land battles in contrast to Xenophon, pointed out that Callisthenes did accurately describe the details on the Battle of Tegyra. He summarized his opinion of Callisthenes' account with "Sie ist panegyrisch gehalten, aber sachlich nicht unrichtig. [It is panegyrical, but it is not factually incorrect.]" This is echoed by the historians John Buckler and Hans Beck who conclude that "In sum, Plutarch's description of the battle of Tegyra does justice both to the terrain of Polygyra and to the information gleaned from his fourth-century sources. There is nothing implausible or unusual in Plutarch's account, and every reason to consider it one of the best of his battle pieces." They also had the same opinion of his account on Leuctra, dismissing assertions that his accounts were confused or rhetorical.
Some archaeologists have claimed that the group was actually Macedonian, and did not consist of male lovers.
The historian Gordon S. Shrimpton further provides an explanation for Xenophon's silence on much of Theban history. He notes that all the surviving contemporary accounts of Thebes during the period of Theban hegemony between 371 and 341 BC were often highly critical; with their failures ridiculed and their accomplishments usually being downplayed or omitted altogether. For instance, the Athenian Isocrates (436–338 BC) in his Plataicus (which details the destruction of Plataea by the Thebans), makes no mention of the Theban victory in Leuctra, and harshly reviles Thebes throughout. His later work Archidamus mention Leuctra briefly, and only to criticize Thebans as being incompetent and incapable of capitalizing on their rise to power. The same sentiments are echoed by the Athenians Demosthenes (384–322 BC) and Antisthenes (c. 445–365 BC). Xenophon, another Athenian, is the only contemporary who grudgingly notes some Theban accomplishments, and even then, never in-depth and with numerous omissions. His only mentions of Pelopidas and Epaminondas by name, for example, were very brief and shed no light on their previous accomplishments. Indeed, the historians Bruce LaForse and John Buckler have noted that the character and accomplishments of Epaminondas were so unassailable that there is no known hostile account of him in ancient sources. The most unfriendly writers like Xenophon and Isocrates could do was omit his accomplishments in their work altogether.
Shrimpton believes that the apparent indifference of earlier authors was due to the general hatred by other Greeks against the Thebans who had medized (i.e. allied with the Persians) in the second Persian invasion in 480 BC and again in 368 BC. Athenians, in particular, held a special contempt for Thebes due to the latter's actions in the Peloponnesian War; as well as the Thebans' destruction of Plataea in 373 BC, and the invasion of the Athenian-allied Boeotian city of Oropus in 366 BC. Demosthenes records this sentiment very clearly in a disclaimer in his speech On the Navy (354 BC): "It is difficult to speak to you about [Thebans], because you have such a hearty dislike of them that you would not care to hear any good of them, even if it were true."
This sentiment changed in 339 BC, when Thebes abruptly severed its alliance with Philip II (after being convinced by a speech from Demosthenes) and joined the Athenian-led Pan-Hellenic alliance against Macedonia, with the result being the annihilation of the Sacred Band in Chaeronea and the destruction of the city of Thebes itself in 335 BC by the Macedonians. In light of these actions, Athenians eventually changed their opinions on Thebes, now regarding it in a sympathetic light as a fallen ally. It was during this period that much of the accounts favorable to Thebans were at last written. Works by authors like Anaximenes of Lampsacus, Aristoxenus, Callisthenes, Daimachus, Dinarchus, and Ephorus are believed to have been written between 330 and 310 BC. Except for Dinarchus, almost all of them have been lost to history or survive only in fragments. Among them are Ephorus and Callisthenes, who were contemporaries of the Theban hegemony and the Sacred Band. The works of the latter two, however, survived long enough for later authors like Plutarch, Diodorus, and Polyaenus to base their works on.
See also
Homosexuality in the militaries of ancient Greece
Homosexuality in ancient Greece
Blood brother
The Sacred Band of Stepsons
Sacred Band of Carthage
Sacred Band (1821) – Greek battalion in the Greek war of independence
Sacred Band (World War II) – Greek special forces unit in World War II
Notes
References
External links
Ancient Greek infantry types
Sexuality in ancient Greece
LGBT history in Greece
Ancient LGBT history
Ancient LGBT people
Gay history
Theban hegemony
4th-century BC establishments in Greece
LGBT military or paramilitary units
Philip II of Macedon
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The SsangYong Korando (Korean: 쌍용 코란도) is a mini SUV or compact crossover SUV built by the South Korean automobile manufacturer SsangYong from 1983 to 2006 and from 2010 onwards. The name Korando is a contraction of "Korea Can Do".
The Korando brand is listed in the Guinness Book of Records as Korea’s longest surviving name plate.
First generation (1982)
In 1964, Ha Dong-hwan Motor Company began to assemble Jeeps, trucks, and buses for the US armed forces and for the United Nations Command.
In November 1969, the CJ-5 entered production with the Willys Hurricane inline-four engine and in 1971, a ten-seater version and a pickup model were introduced. In April 1974, American Motors and Shinjin Motors formed a joint venture, Shinjin Jeep Motors, to build local Jeeps. Sold under the Asia Motors badge, military Jeeps were built (M38A1, M606) as the Asia KM410. This range eventually developed into the Asia Rocsta. The civilian CJ-5 Jeep was built as the Asia Landmaster from September 1974, with a long-wheelbase model added in 1977. These originally had a locally built AMC 258 ci straight-six engine with SAE, but after the oil crises of the seventies Isuzu's 2.8-liter 4BA1 diesel engine with SAE was introduced in July 1979.
Troubled AMC withdrew from South Korea in August 1978. Shinjin Motors sold a shipment of Jeeps to Libya in 1979, in spite of the embargo, and this led to another ownership shakeup as it invalidated the license. Keohwa Co Ltd took over production in March 1981, and rotated the bars in the grille to minimize the resemblance to a Jeep. It remained available on two wheelbases of , with the AMC inline-six or the Isuzu 2.8-liter diesel. In November 1982, the nine-seater "Family Deluxe" was introduced, and the range was renamed "Korando" in March 1983.
Keohwa was absorbed by Dong-A Motor in December 1984, and a facelift followed in March 1985. The new model had a changed interior and the large diesel was replaced by the 2238 cc Isuzu C223 engine. The pickup version was discontinued. In June, Isuzu's 2-liter G200Z petrol engine was added. In 1986, Korandos were exported to Japan; and in 1988, SsangYong began exporting them to Europe. In November 1986 Dong-A was integrated into the SsangYong Group, who changed the company's name to SsangYong Motor Company in March 1988.
Unlike the CJ-7, a 9-seat extended version was also available, called the Korando K9. In late 1988 a new SUV on the chassis of the Isuzu Trooper was introduced, called the SsangYong Korando Family, but this car has no relation to the Jeep CJ-7 beyond the "Korando" nameplate. Production of the Jeep-based Korando ended in 1996.
Second generation (1996–2006)
The second generation "New" Korando was released in Asia in 1996 to complement the SsangYong Musso (released in 1993), released in Europe in 1997 and in Australia in 1998 and was based on a shortened version of the Musso's chassis. The 1.8 tonne 3-door mini SUV was designed by Professor Ken Greenley.
It features a choice of 2.3- and 3.2-liter gasoline engines, or 2.3- and 2.9-liter diesel engines, all produced on license from Mercedes-Benz, accompanied by a five-speed manual Borg-Warner gearbox. The interior of the second generation Korando was unique because it had a steering wheel arch on either side. This was to make converting to right-hand-drive easier and to cut down on production costs. On the passenger's side, a handle was fitted in the arch.
This generation was sold as the Daewoo Korando from 1999 to 2001, as Daewoo bought a majority stake in SsangYong, but was later forced to sell its shares.
Revision
Production of the second generation ended in 2006. Sales however in many markets continued through to 2007 due to remaining stock. It was available with a variety of petrol and diesel engines, including a 2.9-liter five-cylinder diesel from Mercedes-Benz. In 2008, Russian TagAZ, under license, began to assemble the Korando as the TagAZ Tager, not only three-door guise, but also in a specific five-door long-wheelbase version.
Gallery
Third generation (C200; 2010)
The third generation Korando, codenamed the SsangYong C200 began production in late 2010. It is to be the first car to be released as part of SsangYong's revised lineup. It has slightly longer wheelbase than its rivals, the Hyundai ix35 and Kia Sportage. The decision to name the C200 the Korando was done so by SsangYong. The car will be sold in Russia as the SsangYong New Actyon.
In 2013, SsangYong introduced facelift version of Korando. They re-designed front grille with new headlights include LED daytime running lamp, and rear combination lamp. In 2016, SsangYong replaced Korando's 2.0 liter diesel engine to 2.2 liter diesel engine with Euro 6 compliance. In 2017, 2nd facelift version revealed.
Features
The third generation Korando was initially released with a 6-speed manual transmission and a 6-speed M11 automatic transmission and is in production from May 2011 to 2015. Since 2015, SsangYong replaced Korando's automatic gearbox to Aisin 6-speed transmission. It is also to be offered as a front-wheel-drive or four-wheel-drive from launch. Its combined fuel consumption is 5.5 L/100 km and acceleration from 0–100 km/h takes less than 10 seconds. The engine available upon release was a 2.0 liter turbodiesel producing 175 horsepower. Petrol engine was introduced in 2012.
The Korando comes with 6 airbags as standard. The trunk capacity is 480 liters; however this can be expanded to 1300 liters when the seats are folded down.
Reception
The new Korando was well received from a design perspective with many reviewers noting design improvements over previous models. Interior space too, was praised, as was the all-new monocoque chassis.
It became SUV of the year in Macedonia for 2012.
Concept models
Since 2008, five concept cars (some named C200) have been unveiled:
C200
The original concept, the C200, debuted at the 2008 Paris Motor Show and has since been shown at many others. The concept received mostly positive feedback and was thought by many to be the vehicle that can turn SsangYong's reputation for having cars with questionable styling around.
C200 Aero
The concept car C200 Aero made its debut at the 2009 Seoul Motor Show. It was released one year later as Korando C with almost no modification of the original Giugiaro design.
C200 Eco
The C200 Eco made its debut at the 2009 Seoul Motor Show. It is a hybrid which uses both a diesel engine and an electric one (powered by a 340 volt battery). It also uses a stop-start system which shuts off the engine during stops. Fuel saving will be around 25%. The interior features a green trim and an airy cabin.
Korando C
Launched at the 2010 Busan International Motor Show, the new Korando C concept has stayed mostly the same as the previous concepts but has more aggressive styling and is said to be a representation of the production version. Performance-wise, the new concept has a 2.0-liter turbo-diesel engine and a confirmed power output of and of torque. The interior is similar to that of the C200 Eco. It was also displayed as an Actyon at the 2010 Moscow International Automobile Salon, wearing SsangYong's global logo instead of their domestic logo.
Korando EV
Launched at the 2010 Busan International Motor Show, the Korando EV was a fully electric concept car based on the Korando C. It has a top speed of 150 km/h, and a range of 180 km.
Korando C Art Car
Launched at the 2010 Busan International Motor Show alongside the Korando C and Korando EV concepts was an Atomouse-themed art car, in collaboration with Korean pop artist Dongi Lee and the Gana Art Centre. It was also displayed as an Actyon at the 2010 Moscow International Automobile Salon, wearing SsangYong's global logo instead of their domestic logo.
Fourth generation (C300; 2019)
On January 28, 2019, SsangYong released a teaser image and video of the new Korando. The Korando was launched in South Korea on February 26, and debuted to the global market in Geneva Motor Show 2019.
The Korando is offered with a choice of 163 horsepower 1.5-liter turbo petrol or 136 horsepower 1.6-liter diesel engine and is available in two or four-wheel drive. And it is equipped with 6-speed manual transmission or 6-speed AISIN automatic gearbox.
Korando E-Motion
The Korando E-motion is a fully electric version of the Korando and the first fully electric SsangYong. It was made available from the 2022 model year. The vehicle features a 61.5 kWh battery allowing for 339 km of WLTP range, which powers a , 360 Nm front-wheel driving electric motor.
Safety
Euro NCAP test results for a SsangYong Korando 1.6 diesel, LHD, 5-door SUV variant with standard safety equipment on a 2019 registration:
References
External links
(Korando e-motion)
SsangYong Motor > Product (제품) > Korando (코란도)
Korando
Cars introduced in 1996
Compact sport utility vehicles
Crossover sport utility vehicles
Mini sport utility vehicles
Euro NCAP small family cars
2000s cars
2010s cars
|
Kenneth Bernard Gibler (January 31, 1931 – November 23, 1990) was an American football and track coach. He served as the head football coach at Missouri Valley College in Marshall, Missouri from 1968 to 1990, compiling a record of 162–64–8.
A native of Grain Valley, Missouri, Gibler attended Missouri Valley College, where he played college football as an end for four seasons before graduating in 1957. He was the head football coach at Blue Springs High School in Blue Springs, Missouri from 1957 to 1961, tallying a mark of 27–18–4. Gibler returned to Missouri Valley as after working as an assistant football coach at Northern Arizona University for six seasons under head coaches Max Spilsbury and Andy MacDonald.
Gibler died of cancer on November 23, 1990, in Marshall.
Head coaching record
College football
Notes
References
External links
1931 births
1990 deaths
American football ends
Missouri Valley Vikings football coaches
Missouri Valley Vikings football players
Northern Arizona Lumberjacks football coaches
High school football coaches in Missouri
People from Jackson County, Missouri
Coaches of American football from Missouri
Players of American football from Missouri
Deaths from cancer in Missouri
|
```yaml
version: "1.0"
type: navigation-item
data:
path: "network.general"
position: 10
text: _("General")
icon: tune
url: "/network/general"
```
|
Iranian singer-songwriter and producer Shervin Hajipour has released thirty-three songs, three soundtrack songs, four music videos, forty-eight unreleased songs and three songs as featured artist. After auditioning in New Era on March 22, 2019 with "Maybe Paradise" which he himself wrote and performed, he released the song as his debut single on all platforms and gained recognition among Iranian young generation. After releasing many songs, he released his worldwide hit "For" on September 28, 2022. The song was inspired by the Death of Mahsa Amini. It was first released on Hajipour's Instagram account and it was taken down from the platform in less than 48 hours following Hajipour's arrest by the authorities on September 29. In less than 48 hours the song received about 40 million views. It was later described as "the anthem" of the Mahsa Amini protests. Due to Hajipour's rising popularity, his other songs including "After Us", "Spring Has Come" and "Close Your Eyes" went viral and became popular among fans.
Released songs
As featured artist
Soundtrack songs
Unreleased songs
Music videos
References
Pop music discographies
Discographies of Iranian artists
|
Nevada County Air Park is a public airport in Nevada County, California, three miles east of Grass Valley, California. It is also known as Nevada County Airport.
Most U.S. airports use the same three-letter location identifier for the Federal Aviation Administration (FAA) and IATA, but this airport is GOO to the FAA and has no IATA code. (IATA assigned GOO to an airport in Goondiwindi, Queensland, Australia.)
History
The air park was built by local entrepreneur Errol MacBoyle to fly gold mined by his Idaho–Maryland Mine Corporation to Mills Field, now known as San Francisco International Airport. From there it was driven to the San Francisco Mint by the company's treasurer. Located on MacBoyle's Loma Rica Ranch property, Loma Rica Airport was a mile east of MacBoyle's residence. By 1934, the airstrip included a hangar, shops, and a full time radio operator. Eventually, the airport included lights for night landings on its 2400 foot airstrip.
The airport was closed down at the onset of World War II due in part to the government shutdown of mining operations along with the wartime ban on civilian flight within 150 miles of the coast of California. The airport property was purchased from the MacBoyle estate by Charles Litton Sr. in 1955. Litton had previously moved his company's engineering laboratory to Grass Valley in 1953. After acquiring the property, Litton spent $10,000 to repair the runway that had fallen into disrepair and partnered with local government and businesses through the Grass Valley Chamber of Commerce to reopen the airport and build an industrial park in order to attract new business to the region.
The airport was reopened in 1956 and renamed Loma Rica Airport. In 1957, the airport and access roads were given to Nevada County. The United States Forest Service and California Department of Forestry and Fire Protection began using the airport as a base for their wildfire air attack operations in 1958. A major renovation took place in 1965 when the landing strip was lengthened to 4,000 feet (1,200 m). In 1994 a 3000 square foot terminal was added and the following year the landing strip was again extended.
Facilities
Nevada County Air Park covers at an elevation of 3,154 feet (961 m). Its single runway, 7/25, is 4,351 by 75 feet (1,326 x 23 m).
In 2015 the airport had 27,750 aircraft operations, average 76 per day: 96% general aviation and 4% air taxi. 142 aircraft were then based at this airport — 95% single-engine, 4% multi-engine and 1% helicopter.
References
External links
Official site
Aerial photo as of 16 August 1998 from United States Geological Survey The National Map
airfest.wixsite.com/airfest — Grass Valley Airshow and Brewfest
Airports in Nevada County, California
Airports established in 1933
1933 establishments in California
|
is a Japanese voice actor from Tokyo, Japan.
Voice roles
Anime
Video games
Flash Hiders, (1993) Horow
Mega Man: The Power Battle, (1995) Proto Man, Guts Man
Street Fighter Alpha 2, (1996) Rolento
Mega Man 2: The Power Fighters, (1996) Proto Man, Centaur Man, Guts Man, Shadow Man, Air Man, Dive Man
Mega Man X4 (1997) Colonel
Legend of Legaia, (1998) Gala
Street Fighter EX2 Plus, (1999) Vulcano Rosso
Persona 2, (1999) Philemon and Nyarlathotep
Street Fighter EX3, (2000) Vulcano Rosso
Tokusatsu
Narration
Overseas dubbing
References
External links
Official agency profile
1962 births
Living people
Japanese male video game actors
Japanese male voice actors
Male voice actors from Tokyo
20th-century Japanese male actors
21st-century Japanese male actors
|
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<div class="title">CSV Parsing<div class="ingroups"><a class="el" href="group__util.html">Utilities Library (jetson-utils)</a></div></div> </div>
</div><!--header-->
<div class="contents">
<p>Text file parsing for Comma-Separated Value (CSV) formats, with user-defined delimiters beyond just commas, including spaces, tabs, or other symbols.
<a href="#details">More...</a></p>
<table class="memberdecls">
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Namespaces</h2></td></tr>
<tr class="memitem:namespacecsv"><td class="memItemLeft" align="right" valign="top">  </td><td class="memItemRight" valign="bottom"><a class="el" href="namespacecsv.html">csv</a></td></tr>
<tr class="memdesc:namespacecsv"><td class="mdescLeft"> </td><td class="mdescRight">csv stream manipulators <br /></td></tr>
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Classes</h2></td></tr>
<tr class="memitem:classcsvData"><td class="memItemLeft" align="right" valign="top">class  </td><td class="memItemRight" valign="bottom"><a class="el" href="group__csv.html#classcsvData">csvData</a></td></tr>
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<p>Text file parsing for Comma-Separated Value (CSV) formats, with user-defined delimiters beyond just commas, including spaces, tabs, or other symbols. </p>
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<a name="classcsvData" id="classcsvData"></a>
<h2 class="memtitle"><span class="permalink"><a href="#classcsvData">◆ </a></span>csvData</h2>
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<tr class="memitem:a28194fda658f5bc263d862e8dd017c5b"><td class="memItemLeft" align="right" valign="top"> </td><td class="memItemRight" valign="bottom"><a class="el" href="group__csv.html#a28194fda658f5bc263d862e8dd017c5b">csvData</a> (char *str)</td></tr>
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<tr class="memitem:aa27c3ab454656f541d7487656c00967f"><td class="memTemplParams" colspan="2">template<typename T > </td></tr>
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<tr class="memitem:a158f12744612a3f252f46c663f61dbf0"><td class="memTemplParams" colspan="2">template<typename T > </td></tr>
<tr class="memitem:a158f12744612a3f252f46c663f61dbf0"><td class="memTemplItemLeft" align="right" valign="top">void </td><td class="memTemplItemRight" valign="bottom"><a class="el" href="group__csv.html#a158f12744612a3f252f46c663f61dbf0">set</a> (T value)</td></tr>
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<tr class="memitem:a29ae8537c34b0fda676bf46e734427e4"><td class="memItemLeft" align="right" valign="top"> </td><td class="memItemRight" valign="bottom"><a class="el" href="group__csv.html#a29ae8537c34b0fda676bf46e734427e4">operator float</a> () const</td></tr>
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<tr class="memitem:a1a5cb3464e8ca3187e054a7e9885b1f1"><td class="memItemLeft" align="right" valign="top">bool </td><td class="memItemRight" valign="bottom"><a class="el" href="group__csv.html#a1a5cb3464e8ca3187e054a7e9885b1f1">toInt</a> (int *value) const</td></tr>
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<tr class="memitem:a9d73ddf7f68ca2f0ee1fa0e9b3995c15"><td class="memItemLeft" align="right" valign="top">bool </td><td class="memItemRight" valign="bottom"><a class="el" href="group__csv.html#a9d73ddf7f68ca2f0ee1fa0e9b3995c15">toDouble</a> (double *value) const</td></tr>
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<tr class="memitem:a3d6dc285e98818232258d8d58399fe2c"><td class="memItemLeft" align="right" valign="top">int </td><td class="memItemRight" valign="bottom"><a class="el" href="group__csv.html#a3d6dc285e98818232258d8d58399fe2c">toInt</a> (bool *valid=NULL) const</td></tr>
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<tr class="memitem:a95534b3a8d2c01dcaf8abcc8c8f3ed6a"><td class="memItemLeft" align="right" valign="top">float </td><td class="memItemRight" valign="bottom"><a class="el" href="group__csv.html#a95534b3a8d2c01dcaf8abcc8c8f3ed6a">toFloat</a> (bool *valid=NULL) const</td></tr>
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<tr><td colspan="2"><h3>Static Public Member Functions</h3></td></tr>
<tr class="memitem:ae143a669456c777fc1f4a5822c9e9152"><td class="memItemLeft" align="right" valign="top">static std::vector< <a class="el" href="group__csv.html#classcsvData">csvData</a> > </td><td class="memItemRight" valign="bottom"><a class="el" href="group__csv.html#ae143a669456c777fc1f4a5822c9e9152">Parse</a> (const char *str, const char *delimiters=",;\t ")</td></tr>
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<tr class="memitem:a84835cfce3b66bb91ed634bb7ce54f1d"><td class="memItemLeft" align="right" valign="top">static bool </td><td class="memItemRight" valign="bottom"><a class="el" href="group__csv.html#a84835cfce3b66bb91ed634bb7ce54f1d">Parse</a> (std::vector< <a class="el" href="group__csv.html#classcsvData">csvData</a> > &data, const char *str, const char *delimiters=",;\t ")</td></tr>
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<tr class="memitem:a0b8a168b80460cdf91c7e926a76b1346"><td class="memItemLeft" align="right" valign="top">std::string </td><td class="memItemRight" valign="bottom"><a class="el" href="group__csv.html#a0b8a168b80460cdf91c7e926a76b1346">string</a></td></tr>
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<h4 class="groupheader">Friends And Related Function Documentation</h4>
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<h2 class="memtitle"><span class="permalink"><a href="#ad84e240af33c6c6f9ffb32c2f8ea373d">◆ </a></span>operator<<</h2>
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<td class="memname">class csvReader</td>
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<div class="textblock"><p><a class="el" href="group__csv.html#classcsvReader" title="csvReader">csvReader</a> </p>
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<tr class="memitem:aa152f1c1f2c298782ef00dbc0ab44659"><td class="memItemLeft" align="right" valign="top"> </td><td class="memItemRight" valign="bottom"><a class="el" href="group__csv.html#aa152f1c1f2c298782ef00dbc0ab44659">csvReader</a> (const char *filename, const char *delimiters=",;\t ")</td></tr>
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<tr class="memitem:ad9bcff499b2864cba243ad89e71c0561"><td class="memItemLeft" align="right" valign="top"> </td><td class="memItemRight" valign="bottom"><a class="el" href="group__csv.html#ad9bcff499b2864cba243ad89e71c0561">~csvReader</a> ()</td></tr>
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<tr class="memitem:a4fc10c933a0f7ae36a6bb892259f6cc2"><td class="memItemLeft" align="right" valign="top">void </td><td class="memItemRight" valign="bottom"><a class="el" href="group__csv.html#a4fc10c933a0f7ae36a6bb892259f6cc2">Close</a> ()</td></tr>
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<tr class="memitem:a2b9910b8116c3cb84b84dcfd828f13cd"><td class="memItemLeft" align="right" valign="top">bool </td><td class="memItemRight" valign="bottom"><a class="el" href="group__csv.html#a2b9910b8116c3cb84b84dcfd828f13cd">IsOpen</a> () const</td></tr>
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<tr class="memitem:a046a28a013f4b0ef06487cb264d9d702"><td class="memItemLeft" align="right" valign="top">bool </td><td class="memItemRight" valign="bottom"><a class="el" href="group__csv.html#a046a28a013f4b0ef06487cb264d9d702">IsClosed</a> () const</td></tr>
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<tr class="memitem:a04d0a5fc7425485a2aab823f42c983c1"><td class="memItemLeft" align="right" valign="top">std::vector< <a class="el" href="group__csv.html#classcsvData">csvData</a> > </td><td class="memItemRight" valign="bottom"><a class="el" href="group__csv.html#a04d0a5fc7425485a2aab823f42c983c1">Read</a> ()</td></tr>
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<tr class="memitem:a1249df7246ae79204479cd2f8f72a420"><td class="memItemLeft" align="right" valign="top">std::vector< <a class="el" href="group__csv.html#classcsvData">csvData</a> > </td><td class="memItemRight" valign="bottom"><a class="el" href="group__csv.html#a1249df7246ae79204479cd2f8f72a420">Read</a> (const char *delimiters)</td></tr>
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<tr class="memitem:ae90ffbd5178a78da9be92ffa7399d798"><td class="memItemLeft" align="right" valign="top">bool </td><td class="memItemRight" valign="bottom"><a class="el" href="group__csv.html#ae90ffbd5178a78da9be92ffa7399d798">Read</a> (std::vector< <a class="el" href="group__csv.html#classcsvData">csvData</a> > &data)</td></tr>
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<tr class="memitem:ab58d3d20b21ab6abf05adbd54b1c9175"><td class="memItemLeft" align="right" valign="top">bool </td><td class="memItemRight" valign="bottom"><a class="el" href="group__csv.html#ab58d3d20b21ab6abf05adbd54b1c9175">Read</a> (std::vector< <a class="el" href="group__csv.html#classcsvData">csvData</a> > &data, const char *delimiters)</td></tr>
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<tr class="memitem:a0a65b04b1268f0a36ff826a3abdfcfba"><td class="memItemLeft" align="right" valign="top">void </td><td class="memItemRight" valign="bottom"><a class="el" href="group__csv.html#a0a65b04b1268f0a36ff826a3abdfcfba">SetDelimiters</a> (const char *delimiters)</td></tr>
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<tr class="memitem:aebd2551a4d24767f51ac7b2601af86c2"><td class="memItemLeft" align="right" valign="top">const char * </td><td class="memItemRight" valign="bottom"><a class="el" href="group__csv.html#aebd2551a4d24767f51ac7b2601af86c2">GetDelimiters</a> () const</td></tr>
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<tr class="memitem:a88be003aa0289f664c204d65c78324cc"><td class="memItemLeft" align="right" valign="top">const char * </td><td class="memItemRight" valign="bottom"><a class="el" href="group__csv.html#a88be003aa0289f664c204d65c78324cc">GetFilename</a> () const</td></tr>
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<tr><td colspan="2"><h3>Static Public Member Functions</h3></td></tr>
<tr class="memitem:ab670710bb54fc4c3bfd6afd06f0bcd25"><td class="memItemLeft" align="right" valign="top">static <a class="el" href="group__csv.html#classcsvReader">csvReader</a> * </td><td class="memItemRight" valign="bottom"><a class="el" href="group__csv.html#ab670710bb54fc4c3bfd6afd06f0bcd25">Open</a> (const char *filename, const char *delimiters=",;\t ")</td></tr>
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<tr class="memitem:a033e3f7ca4e60c535ffe45085dc5ebe4"><td class="memItemLeft" align="right" valign="top">const size_t </td><td class="memItemRight" valign="bottom"><a class="el" href="group__csv.html#a033e3f7ca4e60c535ffe45085dc5ebe4">MaxLineLength</a> =2048</td></tr>
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<h4 class="groupheader">Constructor & Destructor Documentation</h4>
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<h2 class="memtitle"><span class="permalink"><a href="#ad9bcff499b2864cba243ad89e71c0561">◆ </a></span>~csvReader()</h2>
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<h4 class="groupheader">Member Function Documentation</h4>
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<h2 class="memtitle"><span class="permalink"><a href="#a4fc10c933a0f7ae36a6bb892259f6cc2">◆ </a></span>Close()</h2>
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<td class="memname">void csvReader::Close </td>
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<td class="memname">const char * csvReader::GetDelimiters </td>
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<td class="memname"><a class="el" href="group__csv.html#classcsvReader">csvReader</a> * csvReader::Open </td>
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<td class="memname">void csvReader::SetDelimiters </td>
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<td class="memname">class csvWriter</td>
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<tr class="memitem:a8eb033c5726ebce7f710370ee88f20e1"><td class="memItemLeft" align="right" valign="top"> </td><td class="memItemRight" valign="bottom"><a class="el" href="group__csv.html#a8eb033c5726ebce7f710370ee88f20e1">csvWriter</a> (const char *filename, const char *delimiter=", ")</td></tr>
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<tr class="memitem:ab5c1096c5dfb02fbc62b649270023661"><td class="memItemLeft" align="right" valign="top"> </td><td class="memItemRight" valign="bottom"><a class="el" href="group__csv.html#ab5c1096c5dfb02fbc62b649270023661">~csvWriter</a> ()</td></tr>
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<tr class="memitem:a737aaa1bcff9100fe4fd85a4f2e1c96b"><td class="memItemLeft" align="right" valign="top">void </td><td class="memItemRight" valign="bottom"><a class="el" href="group__csv.html#a737aaa1bcff9100fe4fd85a4f2e1c96b">Close</a> ()</td></tr>
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<tr class="memitem:a0c0d722fdf9d2e5e7858a6a02a7b3b16"><td class="memItemLeft" align="right" valign="top">void </td><td class="memItemRight" valign="bottom"><a class="el" href="group__csv.html#a0c0d722fdf9d2e5e7858a6a02a7b3b16">Flush</a> ()</td></tr>
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<tr class="memitem:a68f9695f0b44e0dea7881d4b30cb07b0"><td class="memItemLeft" align="right" valign="top">bool </td><td class="memItemRight" valign="bottom"><a class="el" href="group__csv.html#a68f9695f0b44e0dea7881d4b30cb07b0">IsOpen</a> () const</td></tr>
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<tr class="memitem:a05b74805269f855765a0220da794437d"><td class="memItemLeft" align="right" valign="top">bool </td><td class="memItemRight" valign="bottom"><a class="el" href="group__csv.html#a05b74805269f855765a0220da794437d">IsClosed</a> () const</td></tr>
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<tr class="memitem:a6df7216f13b759d95163fd40e93d40eb"><td class="memItemLeft" align="right" valign="top">void </td><td class="memItemRight" valign="bottom"><a class="el" href="group__csv.html#a6df7216f13b759d95163fd40e93d40eb">EndLine</a> ()</td></tr>
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<tr class="memitem:af5774438f4bb36e3df26ba3b095a7e11"><td class="memTemplParams" colspan="2">template<typename T > </td></tr>
<tr class="memitem:af5774438f4bb36e3df26ba3b095a7e11"><td class="memTemplItemLeft" align="right" valign="top"><a class="el" href="group__csv.html#classcsvWriter">csvWriter</a> & </td><td class="memTemplItemRight" valign="bottom"><a class="el" href="group__csv.html#af5774438f4bb36e3df26ba3b095a7e11">Write</a> (const T &value)</td></tr>
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<tr class="memitem:a5d36157859bf6d4df6f9adb5bb3a0aee"><td class="memTemplParams" colspan="2">template<typename T , typename... Args> </td></tr>
<tr class="memitem:a5d36157859bf6d4df6f9adb5bb3a0aee"><td class="memTemplItemLeft" align="right" valign="top"><a class="el" href="group__csv.html#classcsvWriter">csvWriter</a> & </td><td class="memTemplItemRight" valign="bottom"><a class="el" href="group__csv.html#a5d36157859bf6d4df6f9adb5bb3a0aee">Write</a> (const T &value, const Args &... args)</td></tr>
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<tr class="memitem:a905853accd1505280d753a0dfe139b51"><td class="memTemplParams" colspan="2">template<typename T , typename... Args> </td></tr>
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<tr class="memitem:afc57daf012a071592ec2c63d6613c086"><td class="memItemLeft" align="right" valign="top"><a class="el" href="group__csv.html#classcsvWriter">csvWriter</a> & </td><td class="memItemRight" valign="bottom"><a class="el" href="group__csv.html#afc57daf012a071592ec2c63d6613c086">operator<<</a> (<a class="el" href="group__csv.html#classcsvWriter">csvWriter</a> &(*value)(<a class="el" href="group__csv.html#classcsvWriter">csvWriter</a> &))</td></tr>
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<tr class="memitem:ae4d435117e0e9a2d9696e3bb39765c77"><td class="memItemLeft" align="right" valign="top">void </td><td class="memItemRight" valign="bottom"><a class="el" href="group__csv.html#ae4d435117e0e9a2d9696e3bb39765c77">SetDelimiter</a> (const char *delimiters)</td></tr>
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<tr class="memitem:af2234cef4c0c90bb06fa4c6d2e3fe468"><td class="memItemLeft" align="right" valign="top">const char * </td><td class="memItemRight" valign="bottom"><a class="el" href="group__csv.html#af2234cef4c0c90bb06fa4c6d2e3fe468">GetDelimiter</a> () const</td></tr>
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<tr class="memitem:a98fe1121694cd78539727c5a0a3057b6"><td class="memItemLeft" align="right" valign="top">const char * </td><td class="memItemRight" valign="bottom"><a class="el" href="group__csv.html#a98fe1121694cd78539727c5a0a3057b6">GetFilename</a> () const</td></tr>
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<tr><td colspan="2"><h3>Static Public Member Functions</h3></td></tr>
<tr class="memitem:a25f9d40d542e804dce5a0519bdff4340"><td class="memItemLeft" align="right" valign="top">static <a class="el" href="group__csv.html#classcsvWriter">csvWriter</a> * </td><td class="memItemRight" valign="bottom"><a class="el" href="group__csv.html#a25f9d40d542e804dce5a0519bdff4340">Open</a> (const char *filename, const char *delimiter=", ")</td></tr>
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<h4 class="groupheader">Constructor & Destructor Documentation</h4>
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<h2 class="memtitle"><span class="permalink"><a href="#a8eb033c5726ebce7f710370ee88f20e1">◆ </a></span>csvWriter()</h2>
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<td class="paramtype">const char * </td>
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<h2 class="memtitle"><span class="permalink"><a href="#ab5c1096c5dfb02fbc62b649270023661">◆ </a></span>~csvWriter()</h2>
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<td class="memname">csvWriter::~csvWriter </td>
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<h4 class="groupheader">Member Function Documentation</h4>
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<h2 class="memtitle"><span class="permalink"><a href="#a737aaa1bcff9100fe4fd85a4f2e1c96b">◆ </a></span>Close()</h2>
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<td class="memname">void csvWriter::Close </td>
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<h2 class="memtitle"><span class="permalink"><a href="#a6df7216f13b759d95163fd40e93d40eb">◆ </a></span>EndLine()</h2>
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<td class="memname">void csvWriter::EndLine </td>
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<h2 class="memtitle"><span class="permalink"><a href="#a0c0d722fdf9d2e5e7858a6a02a7b3b16">◆ </a></span>Flush()</h2>
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<td class="memname">void csvWriter::Flush </td>
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<h2 class="memtitle"><span class="permalink"><a href="#af2234cef4c0c90bb06fa4c6d2e3fe468">◆ </a></span>GetDelimiter()</h2>
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<h2 class="memtitle"><span class="permalink"><a href="#a05b74805269f855765a0220da794437d">◆ </a></span>IsClosed()</h2>
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Mulkhola is a village development committee in Salyan District in the Rapti Zone of western-central Nepal. At the time of the 1991 Nepal census it had a population of 4076 people living in 674 individual households.
References
External links
UN map of the municipalities of Salyan District
Populated places in Salyan District, Nepal
|
James John Thomas (1868 – August 6, 1947) was a Republican politician from the U.S. state of Ohio. He was the 40th mayor of Columbus, Ohio and the 36th person to serve in that office. He was elected on Tuesday, November 4, 1919 and defeated incumbent Democratic mayor George J. Karb. He served Columbus immediately after World War I and throughout the 1920s.
After three consecutive terms in office he was defeated in the 1931 mayoral election by Henry W. Worley.
References
Bibliography
External links
James J. Thomas at Political Graveyard
Mayors of Columbus, Ohio
1868 births
1947 deaths
People from Wrexham
Welsh emigrants to the United States
Ohio Republicans
Columbus City Council members
|
The Easton Historic District is a historic district that covers most of the core of the town of Easton, Maryland. The town is the county seat of Talbot County. The state of Maryland is nearly split by the Chesapeake Bay, and Easton is located on the east side of the bay that is known as Maryland's Eastern Shore. Although the town is part of the east coast of the United States, the region's history goes back to a time when Maryland was a colonial province of England.
The Easton Historic District was added to the National Register of Historic Places in 1980. It contains approximately 900 buildings mostly built in the 18th, 19th, and early 20th centuries. Many of these buildings are residential, but the original business district, located on the west side, is also included. A notable exception to the continuity of the historic district and the construction dates is the original Quaker Third Haven Meeting House, which was constructed in the 1680s southeast of the main portion of the district.
Background
Beginning
Talbot County, as part of the Province of Maryland, began being settled during the mid-1600s with land grants from Lord Baltimore (Cecilius Calvert). Early settlers established tobacco plantations along rivers such as the Choptank, Tred Avon, St. Michaels (now Miles), and Wye rivers. Some of the larger 17th and 18th century plantations within the county were owned by the Goldsborough, Lloyd (Wye Plantation), and Hollyday (Ratcliffe Manor) families. Other early settlers included members of the Society of Friends, also known as Quakers. Politics and society for the next two centuries were strongly influenced by members of the Goldsborough, Hollyday, Kerr, Lloyd, and Tilghman families. In 1706, a portion of Talbot County was broken off to help form Queen Anne's county. This made the county seat in York close to the county border, which was inconvenient for the population in now-smaller Talbot County. Court was held in private residences located in Oxford, which was closer to the population—but a courthouse was never built. Instead, construction of a courthouse began in 1710 near what was known then as "Pitt's Bridge". At the time, the only other nearby building of importance was the Quaker Third Haven Meeting House, which was built in 1682. The village around the courthouse became known as Talbot Courthouse. After the American Revolution, the village became more important as the state of Maryland chose to establish administrative offices for the Eastern Shore at Talbot Courthouse. The town became, in effect, the "capital" of Maryland's Eastern Shore. Its nearest waterfront (Tred Avon River) was about away, and eventually became known as Easton Point.
In 1788, the Maryland General Assembly gave Talbot Courthouse a name: Easton. The town prospered, and the Maryland Eastern Shore's first newspaper was established in 1790. The original courthouse became too small for state offices and local, state, and federal courts, so a new courthouse was constructed. The new courthouse was completed in 1794. Growth continued as the Eastern Shore's first bank was established in 1805 in Easton. During the War of 1812, Fort Stoakes was constructed on a plantation overlooking the Tred Avon River for protection from an attack by the British, and the local bank moved currency to a more secure place in Pennsylvania. In 1817, the Eastern Shore's first steamboat line to Baltimore was established at Easton Point. As more farmland was developed on the west side of the Chesapeake Bay, Maryland's Eastern Shore declined in prosperity—and the American Civil War accelerated this decline. In 1869, a railroad line from Delaware connected Easton with major population centers in the eastern United States. This brought prosperity back to the town that continued until the Great Depression of the 1930s. The Chesapeake Bay Bridge connected Annapolis with Maryland's Eastern Shore in 1952.
Easton today
Traveling by automobile from major Maryland cities such as Annapolis or Baltimore, the most direct route to Easton involves crossing the bay using the Chesapeake Bay Bridge and traveling east and south on U.S. Route 50. The town is small to medium-sized, with a population of about 17,000 using the 2020 United States census. Its original street plan was created in 1785, and Colonel Jeremiah Banning named the main street that runs through the business district (and past the courthouse) after George Washington. The town has grown from Banning's time, and annexations include land along the Tred Avon River. Easton remains the county seat of Talbot County, and its courthouse was enlarged in 1958 by adding two wings. Despite the town's early existence, most of the buildings in the Easton Historic District were constructed in the late 19th and early 20th centuries. The district contains about 9,000 buildings located in residential areas and the central business district. The Easton Historic District was nominated for the National Register of Historic Places in 1980. It is significant for its collection of buildings from the 18th, 19th and early 20th centuries.
Contributing structures
In the original 1980 nomination form, the Easton Historic District consisted of approximately 900 buildings and structures within approximately . Twenty-three were contributing, two non–contributing, and numerous others had not yet been evaluated. The sortable table below contains the original contributing structures that are part of the historic district. If the year built is a range of years, the middle of the range is used.
Other structures of interest within the historic district
Bishop's House was built around 1880 by Philip Francis Thomas, former governor of Maryland and former Secretary of the Treasury under President James Buchanan. The house was built after Thomas' retirement. After his death in 1890, his widow sold the house to the Diocese of Easton, and it was used as the home of the Bishop of Easton until 1956. The tall structure with gabled pavilions on the major facades is located at the corner of Aurora and Goldsborough streets. Although it has facades on both streets, the house's address is 214 Goldsborough Street, and it contributes to the Historic District.
Bullitt/Chamberlain House, one of Easton's most elegant buildings, is located at 102 East Dover Street (corner of Dover and Harrison, sometimes list as 100 East Dover). Lawyer Thomas James Bullitt built this brick house in 1801. Granddaughter Elizabeth Chamberlaine and descendants owned the property into the 20th century. House is a contributing Federal architecture property to the Historic District. It is currently the headquarters of the Mid-Shore Community Foundation.
Foxley Hall is located at 24 North Aurora Street (corner of Aurora and Goldsborough, across Aurora Street from the Bishop's House). It has a Flemish Bond brick facade built in the 1790s. The name "Foxley" is in honor of Mary Foxley Tilghman, daughter of Colonel Oswald Tilghman. The building has had numerous additions, and the interior was altered in the late 19th century. In 1816, the property was sold to John Leeds Kerr, who's daughter married General Tench Tilghman, grandson of the Tench Tilghman that was an aide-de-camp to George Washington in the American Revolution. This began a multi-generation ownership by the Tilghman family. Foxley Hall is a contributing property to the Historic District, and is a well–preserved example of the town's early architecture.
James Neall House is located at 27 South Washington Street, and is owned by the Talbot County Historical Society. Quakers James and Rachael Cox Neall constructed the house around 1805. The Federal-style brick townhouse is three-and-a-half stories high and has a two-story rear addition. The Historical Society has furnished the kitchen and major rooms in this three-story museum brick home. The house is a contributing property to the Easton Historic District.
Tidewater Inn is located at the corner of Dover and Harrison streets. Constructed in the late 1940s, it is outside of the Historic District's period of significance, but it is still considered a contributing property. The four-story structure houses a hotel and restaurant. It is architecturally significant for its Colonial Revival architecture, and it is historically significant for its contribution to the mid-20th century development of Easton and Talbot County. By itself it was listed on the National Register of Historic Places in 2007.
Victorian Store is located at 25 South Washington Street, and is the home of the Talbot County Historical Society. Constructed circa 1880, the Historical Society maintains a museum and small library in the building.
Historic District Borders
The Easton Historic District includes the core of the town that began with a courthouse in the 18th century. Many of the buildings are residential, but the original business district is also included. The business district is located on the northern part of the west side of the district near the courthouse along Washington Street. Additional businesses are on Goldsborough and Dover streets close to Washington Street. Most of the town's buildings in the historic section are brick structures from the late 19th and early 20th centuries. Less than a dozen buildings are from the 18th century, and about 50 date from the early 19th century.
The Talbot County Courthouse, with an address of 11 North Washington Street, occupies most of a block surrounded by Washington, Dover, West, and Federal streets. Three churches are original contributing properties to the district. Trinity Cathedral is located on Goldsborough Street and Locust Lane, east of Aurora Street. The Bishop's House and Foxley Hall are about a block away. Christ Church is in the west central portion of the district at South Street and South Harrison Street. The Christ Church Rectory is next door, and the Armory Building is across the street. The Ashbury Methodist Episcopal Church is in the east central portion of the district, about one block south of Dover Street on South Higgins Street. At the extreme southwestern portion of the historic district is a non-contiguous section near Border Lane, and this is the location of the two Third Haven Meeting House buildings.
See also
List of the oldest buildings in Maryland
Notes
Footnotes
Citations
References
External links
Easton Business District 1936 - Library of Congress
Chronology of Talbot County - Maryland Manual On-line
Easton Walking Tour - from 2019
Historic District Commission - Easton, Maryland
Historic Easton, Maryland - Annapolis Landscape TV - YouTube Video from 2010 (nearly 4 minutes)
Maryland Railroad Map 1876 - Library of Congress (shows Easton's railroad connection to Delaware)
Buildings and structures in Easton, Maryland
Historic districts in Talbot County, Maryland
Federal architecture in Maryland
Greek Revival architecture in Maryland
Italianate architecture in Maryland
Historic districts on the National Register of Historic Places in Maryland
National Register of Historic Places in Talbot County, Maryland
1980 establishments in Maryland
|
```html
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<path
fill-rule="evenodd"
d="M4 9h1v1H4c-1.5 0-3-1.69-3-3.5S2.55 3 4 3h4c1.45 0 3 1.69 3 3.5 0 1.41-.91 2.72-2 3.25V8.59c.58-.45 1-1.27 1-2.09C10 5.22 8.98 4 8 4H4c-.98 0-2 1.22-2 2.5S3 9 4 9zm9-3h-1v1h1c1 0 2 1.22 2 2.5S13.98 12 13 12H9c-.98 0-2-1.22-2-2.5 0-.83.42-1.64 1-2.09V6.25c-1.09.53-2 1.84-2 3.25C6 11.31 7.55 13 9 13h4c1.45 0 3-1.69 3-3.5S14.5 6 13 6z"
></path></svg></a
>How to migrate from React Native X to 0.60.x
</h4>
<ol>
<li>
<p>
For more fast upgrade use Upgrade Helper. Just select your total RN
version and target RN version. Implement diff changes into your
application
<a href="path_to_url"
>path_to_url
>
</p>
</li>
<li><p>Need to disable auto linking. Add into react-native.config.js</p></li>
</ol>
<pre><code class="hljs css language-js"><span class="hljs-built_in">module</span>.exports = {
<span class="hljs-attr">dependencies</span>: {
<span class="hljs-string">'react-native-fbsdk'</span>: {
<span class="hljs-attr">platforms</span>: {
<span class="hljs-attr">android</span>: <span class="hljs-literal">null</span>,
<span class="hljs-attr">ios</span>: <span class="hljs-literal">null</span>,
}
}
}
}
</code></pre>
<ol start="3">
<li>Also read this additional information</li>
</ol>
<p>
<a
href="path_to_url"
>path_to_url
>
<a href="path_to_url"
>path_to_url
>
</p>
<ol start="4">
<li>For build Android before building app use Jetify. Run</li>
</ol>
<pre><code class="hljs css language-bash">npx jetify
</code></pre>
<pre><code class="hljs css language-bash">npx react-native run-android
</code></pre>
<h2>
<a class="anchor" aria-hidden="true" id="troubleshooting"></a
><a href="#troubleshooting" aria-hidden="true" class="hash-link"
><svg
class="hash-link-icon"
aria-hidden="true"
height="16"
version="1.1"
viewBox="0 0 16 16"
width="16"
>
<path
fill-rule="evenodd"
d="M4 9h1v1H4c-1.5 0-3-1.69-3-3.5S2.55 3 4 3h4c1.45 0 3 1.69 3 3.5 0 1.41-.91 2.72-2 3.25V8.59c.58-.45 1-1.27 1-2.09C10 5.22 8.98 4 8 4H4c-.98 0-2 1.22-2 2.5S3 9 4 9zm9-3h-1v1h1c1 0 2 1.22 2 2.5S13.98 12 13 12H9c-.98 0-2-1.22-2-2.5 0-.83.42-1.64 1-2.09V6.25c-1.09.53-2 1.84-2 3.25C6 11.31 7.55 13 9 13h4c1.45 0 3-1.69 3-3.5S14.5 6 13 6z"
></path></svg></a
>Troubleshooting
</h2>
<p>####Android</p>
<p>Issue:</p>
<pre><code class="hljs">Could not <span class="hljs-built_in">get</span> unknown property <span class="hljs-string">'mergeResourcesProvider'</span> <span class="hljs-keyword">for</span> object of <span class="hljs-built_in">type</span> <span class="hljs-keyword">com</span>.android.build.gradle.internal.api.ApplicationVariantImpl.
http<span class="hljs-variable">s:</span>//github.<span class="hljs-keyword">com</span>/wix/react-native-navigation/issues/<span class="hljs-number">4757</span>
> Could not <span class="hljs-built_in">resolve</span> <span class="hljs-keyword">all</span> artifacts <span class="hljs-keyword">for</span> configuration <span class="hljs-string">':classpath'</span>.
> Could not <span class="hljs-keyword">find</span> io.fabric.tool<span class="hljs-variable">s:gradle</span>:<span class="hljs-number">1.25</span>.<span class="hljs-number">4</span>.
Searched in the following location<span class="hljs-variable">s:</span>
- http<span class="hljs-variable">s:</span>//<span class="hljs-keyword">dl</span>.google.<span class="hljs-keyword">com</span>/<span class="hljs-keyword">dl</span>/android/maven2/io/fabric/tools/gradle/<span class="hljs-number">1.25</span>.<span class="hljs-number">4</span>/gradle-<span class="hljs-number">1.25</span>.<span class="hljs-number">4</span>.pom
- http<span class="hljs-variable">s:</span>//<span class="hljs-keyword">dl</span>.google.<span class="hljs-keyword">com</span>/<span class="hljs-keyword">dl</span>/android/maven2/io/fabric/tools/gradle/<span class="hljs-number">1.25</span>.<span class="hljs-number">4</span>/gradle-<span class="hljs-number">1.25</span>.<span class="hljs-number">4</span>.jar
- http<span class="hljs-variable">s:</span>//jcenter.bintray.<span class="hljs-keyword">com</span>/io/fabric/tools/gradle/<span class="hljs-number">1.25</span>.<span class="hljs-number">4</span>/gradle-<span class="hljs-number">1.25</span>.<span class="hljs-number">4</span>.pom
- http<span class="hljs-variable">s:</span>//jcenter.bintray.<span class="hljs-keyword">com</span>/io/fabric/tools/gradle/<span class="hljs-number">1.25</span>.<span class="hljs-number">4</span>/gradle-<span class="hljs-number">1.25</span>.<span class="hljs-number">4</span>.jar
Required by:
project :
</code></pre>
<p>
Solution:
<code
>path_to_url
>
</p>
<hr />
<p>Issue:</p>
<pre><code class="hljs">A problem occurred evaluating script.
> Could <span class="hljs-keyword">not</span> find <span class="hljs-function"><span class="hljs-keyword">method</span> <span class="hljs-title">leftShift</span><span class="hljs-params">()</span> <span class="hljs-title">for</span> <span class="hljs-title">arguments</span> [<span class="hljs-title">setup_eyrc4t7859zi4o3488yvdtnd5</span>$_<span class="hljs-title">run_closure2</span>@3<span class="hljs-title">d71a0b7</span>] <span class="hljs-title">on</span> <span class="hljs-title">task</span> ':</span>app:preBuild<span class="hljs-string">' of type org.gradle.api.DefaultTask.
</span></code></pre>
<p>
Solution:
<code
>path_to_url
>
</p>
<hr />
<p>Issue:</p>
<pre><code class="hljs">* What went wrong:
A problem occurred configuring project <span class="hljs-string">':app'</span>.
> compileSdkVersion <span class="hljs-keyword">is</span> <span class="hljs-keyword">not</span> specified.
</code></pre>
<p>
Solution:
<code
>path_to_url
>
</p>
<hr />
<p>Issue:</p>
<pre><code class="hljs"><span class="hljs-regexp">/Users/</span>igor<span class="hljs-regexp">/Work/</span>Tipsi<span class="hljs-regexp">/tipsi/</span>packages<span class="hljs-regexp">/app/</span>android<span class="hljs-regexp">/app/</span>src<span class="hljs-regexp">/main/</span>java<span class="hljs-regexp">/com/</span>tipsi/MainApplication.<span class="hljs-string">java:</span><span class="hljs-number">10</span>: <span class="hljs-string">error:</span> <span class="hljs-keyword">package</span> android.support.multidex does not exist
<span class="hljs-keyword">import</span> android.support.multidex.MultiDexApplication;
</code></pre>
<p>
Solution:
<code
>path_to_url
>
</p>
<hr />
<p>Issue:</p>
<pre><code class="hljs">/Users<span class="hljs-meta-keyword">/igor/</span>Work/Tipsi<span class="hljs-meta-keyword">/tipsi/</span>packages<span class="hljs-meta-keyword">/app/</span>android<span class="hljs-meta-keyword">/app/</span>src<span class="hljs-meta-keyword">/main/</span>java<span class="hljs-meta-keyword">/com/</span>tipsi/MainApplication.java:<span class="hljs-number">11</span>: error: cannot find symbol
import com.facebook.CallbackManager;
^
<span class="hljs-symbol"> symbol:</span> class CallbackManager
<span class="hljs-symbol"> location:</span> package com.facebook
/Users<span class="hljs-meta-keyword">/igor/</span>Work/Tipsi<span class="hljs-meta-keyword">/tipsi/</span>packages<span class="hljs-meta-keyword">/app/</span>android<span class="hljs-meta-keyword">/app/</span>src<span class="hljs-meta-keyword">/main/</span>java<span class="hljs-meta-keyword">/com/</span>tipsi/MainApplication.java:<span class="hljs-number">12</span>: error: cannot find symbol
import com.facebook.FacebookSdk;
^
<span class="hljs-symbol"> symbol:</span> class FacebookSdk
<span class="hljs-symbol"> location:</span> package com.facebook
/Users<span class="hljs-meta-keyword">/igor/</span>Work/Tipsi<span class="hljs-meta-keyword">/tipsi/</span>packages<span class="hljs-meta-keyword">/app/</span>android<span class="hljs-meta-keyword">/app/</span>src<span class="hljs-meta-keyword">/main/</span>java<span class="hljs-meta-keyword">/com/</span>tipsi/MainApplication.java:<span class="hljs-number">13</span>: error: package com.facebook.appevents does not exist
import com.facebook.appevents.AppEventsLogger;
</code></pre>
<p>Solution: Downgrade FBSDK to 0.10.1</p>
<hr />
<p>Issue:</p>
<pre><code class="hljs"><span class="hljs-regexp">/Users/</span>igor<span class="hljs-regexp">/Work/</span>Tipsi<span class="hljs-regexp">/tipsi/</span>packages<span class="hljs-regexp">/app/</span>node_modules<span class="hljs-regexp">/react-native-fbsdk/</span>android<span class="hljs-regexp">/src/</span>main<span class="hljs-regexp">/java/</span>com<span class="hljs-regexp">/facebook/</span>reactnative<span class="hljs-regexp">/androidsdk/</span>Utility.<span class="hljs-string">java:</span><span class="hljs-number">52</span>: <span class="hljs-string">error:</span> <span class="hljs-keyword">package</span> android.support.annotation does not exist
<span class="hljs-keyword">import</span> android.support.annotation.Nullable;
^
<span class="hljs-regexp">/Users/</span>igor<span class="hljs-regexp">/Work/</span>Tipsi<span class="hljs-regexp">/tipsi/</span>packages<span class="hljs-regexp">/app/</span>node_modules<span class="hljs-regexp">/react-native-fbsdk/</span>android<span class="hljs-regexp">/src/</span>main<span class="hljs-regexp">/java/</span>com<span class="hljs-regexp">/facebook/</span>reactnative<span class="hljs-regexp">/androidsdk/</span>FBAppEventsLoggerModule.<span class="hljs-string">java:</span><span class="hljs-number">23</span>: <span class="hljs-string">error:</span> <span class="hljs-keyword">package</span> android.support.annotation does not exist
<span class="hljs-keyword">import</span> android.support.annotation.Nullable;
</code></pre>
<p>
Solution: Add to <code>MainApplication.java</code> this
<code>import androidx.annotation.Nullable;</code>
</p>
<hr />
<p>Issue:</p>
<pre><code class="hljs">/Users/your_sha512_hash/facebook/react/PackageList.java:<span class="hljs-number">70</span>: error: <span class="hljs-function"><span class="hljs-keyword">constructor</span> <span class="hljs-title">FBSDKPackage</span> <span class="hljs-title">in</span> <span class="hljs-title">class</span> <span class="hljs-title">FBSDKPackage</span> <span class="hljs-title">cannot</span> <span class="hljs-title">be</span> <span class="hljs-title">applied</span> <span class="hljs-title">to</span> <span class="hljs-title">given</span> <span class="hljs-title">types</span>;</span>
<span class="hljs-keyword">new</span> FBSDKPackage(),
^
required: CallbackManager
found: no arguments
reason: actual <span class="hljs-keyword">and</span> formal argument lists differ <span class="hljs-keyword">in</span> length
<span class="hljs-number">1</span> error
</code></pre>
<p>Solution: Downgrade FBSDK to 0.10.1</p>
</span>
</div>
</article>
</div>
<div class="docs-prevnext">
<a class="docs-prev button" href="/tipsi-stripe/docs/createCardOrSubscription.html"
><span class="arrow-prev"> </span><span>Save Card/Subscription</span></a
><a class="docs-next button" href="/tipsi-stripe/docs/changelog.html"
><span>Changelog</span><span class="arrow-next"> </span></a
>
</div>
</div>
</div>
</div>
<footer class="nav-footer" id="footer">
<section class="sitemap">
<a href="/tipsi-stripe/" class="nav-home"></a>
<div>
<h5>Docs</h5>
<a href="/tipsi-stripe/docs/en/index.html">Getting Started</a
><a href="/tipsi-stripe/docs/en/running-apple-pay-on-a-real-device.html"
>Running on Device</a
><a href="/tipsi-stripe/docs/en/index.html">API Reference</a>
</div>
<div>
<h5>More</h5>
<a href="/tipsi-stripe/blog">Blog</a><a href="path_to_url">GitHub</a
><a
data-show-count="true"
class="github-button"
href="path_to_url"
data-icon="octicon-star"
data-count-href="/tipsi/tipsi-stripe/stargazers"
data-count-aria-label="# stargazers on GitHub"
aria-label="Star this project on GitHub"
>Star</a
>
</div>
</section>
</footer>
</div>
</body>
</html>
```
|
```xml
import React, {useMemo, useState, useCallback} from 'react';
import {StyleSheet, View, Switch, Text} from 'react-native';
import {NewCalendarList} from 'react-native-calendars';
import testIDs from '../testIDs';
const initialDate = '2020-05-16';
const NewCalendarListScreen = () => {
const [selected, setSelected] = useState(initialDate);
const [isHorizontal, setIsHorizontal] = useState(false);
const onValueChange = useCallback((value) => {
setIsHorizontal(value);
}, [isHorizontal]);
const markedDates = useMemo(() => {
return {
[selected]: {
selected: true,
selectedColor: '#DFA460'
}
};
}, [selected]);
const onDayPress = useCallback(day => {
console.warn('dayPress: ', day);
setSelected(day.dateString);
}, [setSelected]);
const calendarProps = useMemo(() => {
return {
markedDates: markedDates,
onDayPress: onDayPress
};
}, [selected, markedDates, onDayPress]);
return (
<View style={styles.container}>
<View style={styles.switchView}>
<Text style={styles.switchText}>Horizontal</Text>
<Switch value={isHorizontal} onValueChange={onValueChange}/>
</View>
<NewCalendarList
key={Number(isHorizontal)} // only for this example - to force rerender
horizontal={isHorizontal}
staticHeader
// initialDate={initialDate}
// scrollRange={10}
calendarProps={calendarProps}
testID={testIDs.horizontalList.CONTAINER}
/>
</View>
);
};
export default NewCalendarListScreen;
const styles = StyleSheet.create({
container: {
flex: 1
},
switchView: {
flexDirection: 'row',
height: 70,
padding: 10,
paddingBottom: 30,
backgroundColor: 'white',
alignItems: 'center',
position: 'absolute',
borderTopWidth: 1,
bottom: 0,
right: 0,
left: 0,
zIndex: 100
},
switchText: {
marginRight: 20,
fontSize: 16
}
});
```
|
```ruby
require_relative "../../../spec_helper"
platform_is :windows do
require 'win32ole'
describe "WIN32OLE_METHOD#offset_vtbl" do
before :each do
ole_type = WIN32OLE_TYPE.new("Microsoft Scripting Runtime", "File")
@m_file_name = WIN32OLE_METHOD.new(ole_type, "name")
end
it "raises ArgumentError if argument is given" do
-> { @m_file_name.offset_vtbl(1) }.should raise_error ArgumentError
end
it "returns expected value for Scripting Runtime's 'name' method" do
pointer_size = PlatformGuard::POINTER_SIZE
@m_file_name.offset_vtbl.should == pointer_size
end
end
end
```
|
The Bundesstraße 199 is the name of two German federal roads or Bundesstraße. The first road runs between Klixbüll, Flensburg and Kappeln in the northern part of the state of Schleswig-Holstein.
The second road runs between Klempenow and Anklam in the eastern part of Mecklenburg-Vorpommern.
Route
Route in Schleswig-Holstein
The B 199 begins at the villiage of Klixbüll north of the town of Niebüll at the B 5. It then runs parallel to the German-Danish border through the Villages of Leck, Stadum, Schafflund and Handewitt, where it crosses the A 7 motorway until it reaches the city of Flensburg. It bypasses the city together with the B 200. After leaving Flensburg it meets the villages of Langballig, Steinbergkirche and Gelting until it ends in at an intersection with the B 201 and B 203 in the western part of Kappeln
Route in Mecklenburg-Vorpommern
The B 199 beginns in the villiage of Klempenow. Shortly after it has a junction with the A 20 motorway. It runs straight to the city of Anklam where it meets the B 110 near the Anklam bypass.
Major junctions
See also
List of federal roads in Germany
References
199
B 199
B 199
|
Bruce Douglas Anderson (born March 12, 1950) is an American politician and member of the Minnesota Senate. A member of the Republican Party of Minnesota, he represents District 29, which includes portions of Hennepin and Wright Counties in central Minnesota.
Early life, education, and career
Anderson attended North Hennepin Junior College in Brooklyn Park in 1968–69, and received aviation electronics training during his time in the United States Navy in 1970–73. He received an A.A. in agribusiness from Willmar Technical College in 1976, and later earned a B.S. in business management from Northwestern College. He was a sales manager for Centra Sota Cooperative from 1976 to 1986. He was a member of the Minnesota Governor's Advisory Board for Technology for Persons with Disabilities in the 1990s.
Anderson was a member of the Minnesota Air National Guard, and a former Master Sergeant in the United States Air National Guard. He was the 1990 Republican-endorsed candidate for the United States House of Representatives in the old 6th Congressional District.
Minnesota Legislature
Anderson was first elected to the House in 1994, and was reelected every two years until 2010. Before the 2002 legislative redistricting, he represented the old District 19B. He was a member of the House Public Safety Policy and Oversight Committee and the Rules and Legislative Administration Committee. He also served on the Finance subcommittees for the Bioscience and Workforce Development Policy and Oversight Division, the Capital Investment Finance Division, and the Energy Finance and Policy Division.
Anderson was first elected to the Minnesota Senate in 2012.
Personal life
Anderson was married to Dottie until her death in September 2006. He later married Ruth. He has five children and resides in Buffalo Township, Minnesota.
References
External links
Official Senate website
Official campaign website
Minnesota Public Radio Votetracker: Rep. Bruce Anderson
Project Votesmart – Rep. Bruce Anderson Profile
1950 births
Living people
People from Buffalo, Minnesota
Military personnel from Minnesota
Republican Party Minnesota state senators
Republican Party members of the Minnesota House of Representatives
University of Northwestern – St. Paul alumni
Politicians from Saint Paul, Minnesota
21st-century American politicians
|
```xml
import assert from 'assert';
import vscode from 'vscode';
import { showFile } from '../../../editorHelper';
import { sameLineRange } from '../../../util';
import { getDocUri } from '../../path';
describe('Should do documentLink', () => {
const docUri = getDocUri('documentLink/Basic.vue');
it('shows all documentLinks for Basic.vue', async () => {
await testLink(docUri, [
{ target: vscode.Uri.parse('path_to_url range: sameLineRange(2, 14, 47) },
{ target: getDocUri('documentLink/foo'), range: sameLineRange(3, 13, 18) },
{ target: getDocUri('documentLink/foo.js'), range: sameLineRange(7, 13, 21) }
]);
});
});
async function testLink(docUri: vscode.Uri, expectedLinks: vscode.DocumentLink[]) {
await showFile(docUri);
const result = (await vscode.commands.executeCommand('vscode.executeLinkProvider', docUri)) as vscode.DocumentLink[];
expectedLinks.forEach(el => {
assert.ok(
result.some(l => isEqualLink(l, el)),
`Failed to find same link as ${el.target!.fsPath}. Seen links are:\n${JSON.stringify(result, null, 2)}`
);
});
function isEqualLink(h1: vscode.DocumentLink, h2: vscode.DocumentLink) {
return h1.target!.fsPath === h2.target!.fsPath && h1.range.isEqual(h2.range);
}
}
```
|
```xml
import basicSpawnAsync, { SpawnResult, SpawnOptions, SpawnPromise } from '@expo/spawn-async';
import chalk from 'chalk';
import { glob, GlobOptions } from 'glob';
import ora from 'ora';
import { EXPO_DIR } from './Constants';
export { SpawnResult, SpawnOptions };
/**
* Asynchronously spawns a process with given command, args and options. Working directory is set to repo's root by default.
*/
export function spawnAsync(
command: string,
args: Readonly<string[]> = [],
options: SpawnOptions = {}
): SpawnPromise<SpawnResult> {
return basicSpawnAsync(command, args, {
env: { ...process.env },
cwd: EXPO_DIR,
...options,
});
}
/**
* Does the same as `spawnAsync` but parses the output to JSON object.
*/
export async function spawnJSONCommandAsync<T = object>(
command: string,
args: Readonly<string[]> = [],
options: SpawnOptions = {}
): Promise<T> {
const child = await spawnAsync(command, args, options);
try {
return JSON.parse(child.stdout);
} catch (e) {
e.message +=
'\n' + chalk.red('Cannot parse this output as JSON: ') + chalk.yellow(child.stdout.trim());
throw e;
}
}
/**
* Deeply clones an object. It's used to make a backup of home's `app.json` file.
*/
export function deepCloneObject<ObjectType extends object = object>(
object: ObjectType
): ObjectType {
return JSON.parse(JSON.stringify(object));
}
/**
* Waits given amount of time (in milliseconds).
*/
export function sleepAsync(duration: number): Promise<void> {
return new Promise((resolve) => {
setTimeout(resolve, duration);
});
}
/**
* Filters an array asynchronously.
*/
export async function filterAsync<T = any>(
arr: T[],
filter: (item: T, index: number) => boolean | Promise<boolean>
): Promise<T[]> {
const results = await Promise.all(arr.map(filter));
return arr.filter((item, index) => results[index]);
}
/**
* Retries executing the function with given interval and with given retry limit.
* It resolves immediately once the callback returns anything else than `undefined`.
*/
export async function retryAsync<T = any>(
interval: number,
limit: number,
callback: () => T | Promise<T>
): Promise<T | undefined> {
return new Promise((resolve) => {
let count = 0;
const timeoutCallback = async () => {
const result = await callback();
if (result !== undefined) {
resolve(result);
return;
}
if (++count < limit) {
setTimeout(timeoutCallback, interval);
} else {
resolve(undefined);
}
};
timeoutCallback();
});
}
/**
* Executes regular expression against a string until the last match is found.
*/
export function execAll(rgx: RegExp, str: string, index: number = 0): string[] {
const globalRgx = new RegExp(rgx.source, 'g' + rgx.flags.replace('g', ''));
const matches: string[] = [];
let match;
while ((match = globalRgx.exec(str))) {
matches.push(match[index]);
}
return matches;
}
/**
* Searches for files matching given glob patterns.
*/
export async function searchFilesAsync(
rootPath: string,
patterns: string | string[],
options?: Omit<GlobOptions, 'withFileTypes'>
): Promise<Set<string>> {
const files = await Promise.all(
arrayize(patterns).map((pattern) =>
glob(pattern, {
cwd: rootPath,
nodir: true,
...options,
})
)
);
return new Set(([] as string[]).concat(...files));
}
/**
* Ensures the value is an array.
*/
export function arrayize<T>(value: T | T[]): T[] {
if (Array.isArray(value)) {
return value;
}
return value != null ? [value] : [];
}
/**
* Execute `patch` command for given patch content
*/
export async function applyPatchAsync(options: {
patchContent: string;
cwd: string;
reverse?: boolean;
stripPrefixNum?: number;
}) {
const args: string[] = [];
if (options.stripPrefixNum != null) {
// -pN passing to the `patch` command for striping slashed prefixes
args.push(`-p${options.stripPrefixNum}`);
}
if (options.reverse) {
args.push('-R');
}
const procPromise = spawnAsync('patch', args, {
cwd: options.cwd,
});
procPromise.child.stdin?.write(options.patchContent);
procPromise.child.stdin?.end();
await procPromise;
}
export async function runWithSpinner<Result>(
title: string,
action: (step: ora.Ora) => Promise<Result> | Result,
succeedText: string | null = null,
options: ora.Options = {}
): Promise<Result> {
const disabled = process.env.CI || process.env.EXPO_DEBUG;
const step = ora({
text: chalk.bold(title),
isEnabled: !disabled,
stream: disabled ? process.stdout : process.stderr,
...options,
});
step.start();
try {
const result = await action(step);
if (step.isSpinning && succeedText) {
step.succeed(succeedText);
}
return result;
} catch (error) {
step.fail();
console.error(error);
process.exit(1);
}
}
```
|
```smalltalk
Extension { #name : 'SortedCollection' }
{ #category : '*STON-Core' }
SortedCollection >> fromSton: stonReader [
"Overwritten to get back the standard object behavior"
stonReader parseNamedInstVarsFor: self
]
{ #category : '*STON-Core' }
SortedCollection class >> fromSton: stonReader [
"Overwritten to get back the standard object behavior"
^ self new
fromSton: stonReader;
yourself
]
{ #category : '*STON-Core' }
SortedCollection >> stonOn: stonWriter [
"Overwritten to get back the standard object behavior"
stonWriter writeObject: self
]
```
|
WDVE (102.5 FM) is a classic rock music-formatted radio station in Pittsburgh, Pennsylvania, United States at 102.5 MHz. It is often referred to by Pittsburghers as simply "DVE". Its studios and offices are located on Abele Rd. in Bridgeville next to I-79, along with its sister stations. The former studios in Green Tree still features WDVE's branding on the building. Its transmitter is located on Pittsburgh's North Side. Since 2006, the station has been the highest-rated radio station in the Pittsburgh market, surpassing longtime market leader KDKA. The station is currently owned by iHeartMedia, and (along with WBGG) serves as the flagship radio station of the Pittsburgh Steelers radio network.
WDVE is designated a superpower station by the Federal Communications Commission. The station's effective radiated power of 55,000 watts exceeds the maximum limit set by the FCC for a Class B FM radio station.
WDVE uses HD Radio and broadcasts a sports format on its HD2 subchannel branded as Steelers Nation Radio.
History
The station has aired rock music since 1969, when it was owned by ABC. Previously, it was known as KQV-FM and simulcasted then-sister station KQV. The new programming was a tape service of a freeform rock format entitled "Love", created by ABC official Allen Shaw designed specifically for airing on the 7 FM stations owned by ABC. Shaw changed the format from the automated "Love" format to live Freeform AOR in 1970. The station's current call letters were chosen in December 1970 at the height of the "hippie" era.
"WDVE" was derived from the word "Wonderful Dove", the bird of peace, though the station has never had an easy listening, Christian contemporary music, or soft rock format which would soon be more associated with future "Dove"-branded stations like Tampa's WDUV, or WDVV in Wilmington, North Carolina.
In the fall of 1971, Shaw, along with ABC Radio programming executive Bob Henaberry, replaced the freeform rock programming with the very first AOR format, playing only the best cuts from the best selling rock albums with minimal disc jockey talk. WDVE was the most successful FM radio station in Pittsburgh throughout the 1970s. In early print marketing, the phrase Rock 'N' Stereo! Pittsburgh's Pure Rock WDVE 102½ FM, The Radio Station, was set in white text against a black oval background surrounded by vivid rainbow like colors. Years later, the logo was rendered in white and yellow with red accents against a black background, generally using the slogan 102.5 WDVE Rocks.
Starting in the 1980s, the station started playing the Beat Farmers song Happy Boy every Friday around 3 p.m. at the start of the afternoon drive time shift to signal the end of the work week and the start of the weekend. On Fridays at noon, they air a recording of the band KISS saying; "Hey yinz guys! It's FRIDAY!!", immediately followed by "Rock and Roll All Nite".
Radio personality and WEBN alum Maxwell Slater "Max" Logan (Ben Bornstein), formerly heard on WMMS, WNCX in Cleveland and now on WLUP-FM in Chicago as host of The Maxwell Show, spent time at WDVE in the mid-1990s.
In addition to its status as flagship station of the Steelers, WDVE served for years as the flagship station of the Pittsburgh Penguins (until 2006 when sister station WXDX-FM became the Penguins' flagship), promoting itself with such oddities as a young Jaromír Jágr reading the morning weather forecast in heavily accented English during his suspension from the NHL.
Because of the station having a largely male audience, the station refers to fellow iHeartMedia stations WXDX-FM and WPGB as "brother" stations as opposed to the more commonly used term "sister" station, since WXDX-FM also has a predominantly male audience and all three have younger listeners. In recent years, the station's format has gradually drifted towards classic rock, with current releases rarely incorporated into the playlist. Pittsburgh had been without a full-time classic rock station since the flip of WRRK to adult hits, even though iHeartMedia considers the station as a classic rocker; however, since 2016, WDVE has added more newer rock tracks that were not being played on co-owned WXDX, with the station gradually shifting to a more mainstream rock direction.
Currently, the station air staff consists of morning show host Randy Baumann, morning News Reader and Saturday morning host Val Porter, morning sportscaster Mike Prisuta, morning show comedian Bill Crawford, mid-day host Michele Michaels, afternoon and weekend host Chad Tyson, evening host Russ “Whip” Rose, and weekend hosts Frank Cindrich and Eric Taylor. To fill out the rest of their schedule, the station uses iHeartMedia’s Premium Choice service, which provides additional weekend and overnight dayparts hosted by air talent from across the country. The station was one of the few iHeartRadio stations not affected by the company’s mass layoffs in January 2020.
Morning Show
As of January 2012 Randy Baumann and the DVE Morning Show airs on weekdays from 6 a.m. to 10 a.m.. The rest of the morning show team are newsreader Val Porter, sportscaster Mike Prisuta, and comedian Bill Crawford. The show features a variety of comedy skits, musical parodies, and music.
Prior to hosting solo, Baumann was teamed with Jim Krenn starting in early 2000. Prior to that, Krenn had been on with Scott Paulsen, who along with "News Goddess" Lauri Githens had hosted the morning show from 1986-1988 (after "Little Jimmy" Roach and "Big Steve" Hansen of "The DVE Morning Alternative" were not offered a new contract after their 1980-1986 stint).
On January 18, 2010, the morning show returned to the air without Randy Baumann and used the name "DVE Morning Show" (rather than "Jim and Randy and the DVE Morning Show"). Randy Baumann's contract had expired at the beginning of 2010 and he returned to the airwaves on February 17, 2010 after contract negotiations had been settled. The show resumed its previous title "Jim and Randy and the DVE Morning Show".
On December 31, 2011, iHeartMedia (then known as Clear Channel Communications) announced that Jim Krenn would no longer be part of the DVE Morning show but would still be employed at the station. According to a statement made by Dennis Lamme, President and Market Manager of Clear Channel Media & Entertainment-Pittsburgh, "We are currently in discussion with Jim about his role with the station moving forward.". They are again using the name "DVE Morning Show". Krenn's official departure from Clear Channel was announced on January 19, 2012. As of February 23, 2012, WDVE has branded the morning show "Randy Baumann and the DVE Morning Show".
Other media
Staff at WDVE provided voices for the segment Action League Now! on Nickelodeon's KaBlam!.
An extra in the 1986 movie Gung Ho wore a WDVE t-shirt on-screen. The movie, starring Coraopolis native Michael Keaton, was largely shot in Beaver County, just a short drive up Interstate 376 from WDVE's studios.
Bumper stickers for the station appear in the Mark Wahlberg movie, Rock Star, set in Pittsburgh.
WDVE HD2
WDVE broadcasts on its HD2 subchannel dates back to 2006, when the subchannel launched a format focusing on Blues music. In August 2011, HD2 became a 24-hour channel devoted to Steelers coverage, billed as "Steelers Nation Radio."
References
External links
WDVE official website
List of "grandfathered" FM radio stations in the U.S.
DVE
Classic rock radio stations in the United States
Radio stations established in 1962
Taft Broadcasting
IHeartMedia radio stations
|
Krásný Dvůr () is a municipality and village in Louny District in the Ústí nad Labem Region of the Czech Republic. It has about 700 inhabitants.
Administrative parts
Villages of Brody, Chotěbudice, Chrašťany, Němčany, Vysoké Třebušice and Zlovědice are administrative parts of Krásný Dvůr.
Sights
Krásný Dvůr is known for the Krásný Dvůr Castle.
References
External links
Villages in Louny District
|
```prolog
#! /usr/bin/env perl
#
# in the file LICENSE in the source distribution or at
# path_to_url
# ====================================================================
# Written by Andy Polyakov <appro@openssl.org> for the OpenSSL
# project. The module is, however, dual licensed under OpenSSL and
# CRYPTOGAMS licenses depending on where you obtain it. For further
# details see path_to_url~appro/cryptogams/.
# ====================================================================
# I let hardware handle unaligned input, except on page boundaries
# (see below for details). Otherwise straightforward implementation
# with X vector in register bank.
# sha256 | sha512
# -m64 -m32 | -m64 -m32
# --------------------------------------+-----------------------
# PPC970,gcc-4.0.0 +50% +38% | +40% +410%(*)
# Power6,xlc-7 +150% +90% | +100% +430%(*)
#
# (*) 64-bit code in 32-bit application context, which actually is
# on TODO list. It should be noted that for safe deployment in
# 32-bit *multi-threaded* context asynchronous signals should be
# blocked upon entry to SHA512 block routine. This is because
# 32-bit signaling procedure invalidates upper halves of GPRs.
# Context switch procedure preserves them, but not signaling:-(
# Second version is true multi-thread safe. Trouble with the original
# version was that it was using thread local storage pointer register.
# Well, it scrupulously preserved it, but the problem would arise the
# moment asynchronous signal was delivered and signal handler would
# dereference the TLS pointer. While it's never the case in openssl
# application or test suite, we have to respect this scenario and not
# use TLS pointer register. Alternative would be to require caller to
# block signals prior calling this routine. For the record, in 32-bit
# context R2 serves as TLS pointer, while in 64-bit context - R13.
$flavour=shift;
$output =shift;
if ($flavour =~ /64/) {
$SIZE_T=8;
$LRSAVE=2*$SIZE_T;
$STU="stdu";
$UCMP="cmpld";
$SHL="sldi";
$POP="ld";
$PUSH="std";
} elsif ($flavour =~ /32/) {
$SIZE_T=4;
$LRSAVE=$SIZE_T;
$STU="stwu";
$UCMP="cmplw";
$SHL="slwi";
$POP="lwz";
$PUSH="stw";
} else { die "nonsense $flavour"; }
$LITTLE_ENDIAN = ($flavour=~/le$/) ? $SIZE_T : 0;
$0 =~ m/(.*[\/\\])[^\/\\]+$/; $dir=$1;
( $xlate="${dir}ppc-xlate.pl" and -f $xlate ) or
( $xlate="${dir}../../perlasm/ppc-xlate.pl" and -f $xlate) or
die "can't locate ppc-xlate.pl";
open STDOUT,"| $^X $xlate $flavour $output" || die "can't call $xlate: $!";
if ($output =~ /512/) {
$func="sha512_block_ppc";
$SZ=8;
@Sigma0=(28,34,39);
@Sigma1=(14,18,41);
@sigma0=(1, 8, 7);
@sigma1=(19,61, 6);
$rounds=80;
$LD="ld";
$ST="std";
$ROR="rotrdi";
$SHR="srdi";
} else {
$func="sha256_block_ppc";
$SZ=4;
@Sigma0=( 2,13,22);
@Sigma1=( 6,11,25);
@sigma0=( 7,18, 3);
@sigma1=(17,19,10);
$rounds=64;
$LD="lwz";
$ST="stw";
$ROR="rotrwi";
$SHR="srwi";
}
$FRAME=32*$SIZE_T+16*$SZ;
$LOCALS=6*$SIZE_T;
$sp ="r1";
$toc="r2";
$ctx="r3"; # zapped by $a0
$inp="r4"; # zapped by $a1
$num="r5"; # zapped by $t0
$T ="r0";
$a0 ="r3";
$a1 ="r4";
$t0 ="r5";
$t1 ="r6";
$Tbl="r7";
$A ="r8";
$B ="r9";
$C ="r10";
$D ="r11";
$E ="r12";
$F =$t1; $t1 = "r0"; # stay away from "r13";
$G ="r14";
$H ="r15";
@V=($A,$B,$C,$D,$E,$F,$G,$H);
@X=("r16","r17","r18","r19","r20","r21","r22","r23",
"r24","r25","r26","r27","r28","r29","r30","r31");
$inp="r31" if($SZ==4 || $SIZE_T==8); # reassigned $inp! aliases with @X[15]
sub ROUND_00_15 {
my ($i,$a,$b,$c,$d,$e,$f,$g,$h)=@_;
$code.=<<___;
$ROR $a0,$e,$Sigma1[0]
$ROR $a1,$e,$Sigma1[1]
and $t0,$f,$e
xor $a0,$a0,$a1
add $h,$h,$t1
andc $t1,$g,$e
$ROR $a1,$a1,`$Sigma1[2]-$Sigma1[1]`
or $t0,$t0,$t1 ; Ch(e,f,g)
add $h,$h,@X[$i%16]
xor $a0,$a0,$a1 ; Sigma1(e)
add $h,$h,$t0
add $h,$h,$a0
$ROR $a0,$a,$Sigma0[0]
$ROR $a1,$a,$Sigma0[1]
and $t0,$a,$b
and $t1,$a,$c
xor $a0,$a0,$a1
$ROR $a1,$a1,`$Sigma0[2]-$Sigma0[1]`
xor $t0,$t0,$t1
and $t1,$b,$c
xor $a0,$a0,$a1 ; Sigma0(a)
add $d,$d,$h
xor $t0,$t0,$t1 ; Maj(a,b,c)
___
$code.=<<___ if ($i<15);
$LD $t1,`($i+1)*$SZ`($Tbl)
___
$code.=<<___;
add $h,$h,$a0
add $h,$h,$t0
___
}
sub ROUND_16_xx {
my ($i,$a,$b,$c,$d,$e,$f,$g,$h)=@_;
$i-=16;
$code.=<<___;
$ROR $a0,@X[($i+1)%16],$sigma0[0]
$ROR $a1,@X[($i+1)%16],$sigma0[1]
$ROR $t0,@X[($i+14)%16],$sigma1[0]
$ROR $t1,@X[($i+14)%16],$sigma1[1]
xor $a0,$a0,$a1
$SHR $a1,@X[($i+1)%16],$sigma0[2]
xor $t0,$t0,$t1
$SHR $t1,@X[($i+14)%16],$sigma1[2]
add @X[$i],@X[$i],@X[($i+9)%16]
xor $a0,$a0,$a1 ; sigma0(X[(i+1)&0x0f])
xor $t0,$t0,$t1 ; sigma1(X[(i+14)&0x0f])
$LD $t1,`$i*$SZ`($Tbl)
add @X[$i],@X[$i],$a0
add @X[$i],@X[$i],$t0
___
&ROUND_00_15($i+16,$a,$b,$c,$d,$e,$f,$g,$h);
}
$code=<<___;
.machine "any"
.text
.globl $func
.align 6
$func:
$STU $sp,-$FRAME($sp)
mflr r0
$SHL $num,$num,`log(16*$SZ)/log(2)`
$PUSH $ctx,`$FRAME-$SIZE_T*22`($sp)
$PUSH r14,`$FRAME-$SIZE_T*18`($sp)
$PUSH r15,`$FRAME-$SIZE_T*17`($sp)
$PUSH r16,`$FRAME-$SIZE_T*16`($sp)
$PUSH r17,`$FRAME-$SIZE_T*15`($sp)
$PUSH r18,`$FRAME-$SIZE_T*14`($sp)
$PUSH r19,`$FRAME-$SIZE_T*13`($sp)
$PUSH r20,`$FRAME-$SIZE_T*12`($sp)
$PUSH r21,`$FRAME-$SIZE_T*11`($sp)
$PUSH r22,`$FRAME-$SIZE_T*10`($sp)
$PUSH r23,`$FRAME-$SIZE_T*9`($sp)
$PUSH r24,`$FRAME-$SIZE_T*8`($sp)
$PUSH r25,`$FRAME-$SIZE_T*7`($sp)
$PUSH r26,`$FRAME-$SIZE_T*6`($sp)
$PUSH r27,`$FRAME-$SIZE_T*5`($sp)
$PUSH r28,`$FRAME-$SIZE_T*4`($sp)
$PUSH r29,`$FRAME-$SIZE_T*3`($sp)
$PUSH r30,`$FRAME-$SIZE_T*2`($sp)
$PUSH r31,`$FRAME-$SIZE_T*1`($sp)
$PUSH r0,`$FRAME+$LRSAVE`($sp)
___
if ($SZ==4 || $SIZE_T==8) {
$code.=<<___;
$LD $A,`0*$SZ`($ctx)
mr $inp,r4 ; incarnate $inp
$LD $B,`1*$SZ`($ctx)
$LD $C,`2*$SZ`($ctx)
$LD $D,`3*$SZ`($ctx)
$LD $E,`4*$SZ`($ctx)
$LD $F,`5*$SZ`($ctx)
$LD $G,`6*$SZ`($ctx)
$LD $H,`7*$SZ`($ctx)
___
} else {
for ($i=16;$i<32;$i++) {
$code.=<<___;
lwz r$i,`$LITTLE_ENDIAN^(4*($i-16))`($ctx)
___
}
}
$code.=<<___;
bl LPICmeup
LPICedup:
andi. r0,$inp,3
bne Lunaligned
Laligned:
add $num,$inp,$num
$PUSH $num,`$FRAME-$SIZE_T*24`($sp) ; end pointer
$PUSH $inp,`$FRAME-$SIZE_T*23`($sp) ; inp pointer
bl Lsha2_block_private
b Ldone
; PowerPC specification allows an implementation to be ill-behaved
; upon unaligned access which crosses page boundary. "Better safe
; than sorry" principle makes me treat it specially. But I don't
; look for particular offending word, but rather for the input
; block which crosses the boundary. Once found that block is aligned
; and hashed separately...
.align 4
Lunaligned:
subfic $t1,$inp,4096
andi. $t1,$t1,`4096-16*$SZ` ; distance to closest page boundary
beq Lcross_page
$UCMP $num,$t1
ble Laligned ; didn't cross the page boundary
subfc $num,$t1,$num
add $t1,$inp,$t1
$PUSH $num,`$FRAME-$SIZE_T*25`($sp) ; save real remaining num
$PUSH $t1,`$FRAME-$SIZE_T*24`($sp) ; intermediate end pointer
$PUSH $inp,`$FRAME-$SIZE_T*23`($sp) ; inp pointer
bl Lsha2_block_private
; $inp equals to the intermediate end pointer here
$POP $num,`$FRAME-$SIZE_T*25`($sp) ; restore real remaining num
Lcross_page:
li $t1,`16*$SZ/4`
mtctr $t1
___
if ($SZ==4 || $SIZE_T==8) {
$code.=<<___;
addi r20,$sp,$LOCALS ; aligned spot below the frame
Lmemcpy:
lbz r16,0($inp)
lbz r17,1($inp)
lbz r18,2($inp)
lbz r19,3($inp)
addi $inp,$inp,4
stb r16,0(r20)
stb r17,1(r20)
stb r18,2(r20)
stb r19,3(r20)
addi r20,r20,4
bdnz Lmemcpy
___
} else {
$code.=<<___;
addi r12,$sp,$LOCALS ; aligned spot below the frame
Lmemcpy:
lbz r8,0($inp)
lbz r9,1($inp)
lbz r10,2($inp)
lbz r11,3($inp)
addi $inp,$inp,4
stb r8,0(r12)
stb r9,1(r12)
stb r10,2(r12)
stb r11,3(r12)
addi r12,r12,4
bdnz Lmemcpy
___
}
$code.=<<___;
$PUSH $inp,`$FRAME-$SIZE_T*26`($sp) ; save real inp
addi $t1,$sp,`$LOCALS+16*$SZ` ; fictitious end pointer
addi $inp,$sp,$LOCALS ; fictitious inp pointer
$PUSH $num,`$FRAME-$SIZE_T*25`($sp) ; save real num
$PUSH $t1,`$FRAME-$SIZE_T*24`($sp) ; end pointer
$PUSH $inp,`$FRAME-$SIZE_T*23`($sp) ; inp pointer
bl Lsha2_block_private
$POP $inp,`$FRAME-$SIZE_T*26`($sp) ; restore real inp
$POP $num,`$FRAME-$SIZE_T*25`($sp) ; restore real num
addic. $num,$num,`-16*$SZ` ; num--
bne Lunaligned
Ldone:
$POP r0,`$FRAME+$LRSAVE`($sp)
$POP r14,`$FRAME-$SIZE_T*18`($sp)
$POP r15,`$FRAME-$SIZE_T*17`($sp)
$POP r16,`$FRAME-$SIZE_T*16`($sp)
$POP r17,`$FRAME-$SIZE_T*15`($sp)
$POP r18,`$FRAME-$SIZE_T*14`($sp)
$POP r19,`$FRAME-$SIZE_T*13`($sp)
$POP r20,`$FRAME-$SIZE_T*12`($sp)
$POP r21,`$FRAME-$SIZE_T*11`($sp)
$POP r22,`$FRAME-$SIZE_T*10`($sp)
$POP r23,`$FRAME-$SIZE_T*9`($sp)
$POP r24,`$FRAME-$SIZE_T*8`($sp)
$POP r25,`$FRAME-$SIZE_T*7`($sp)
$POP r26,`$FRAME-$SIZE_T*6`($sp)
$POP r27,`$FRAME-$SIZE_T*5`($sp)
$POP r28,`$FRAME-$SIZE_T*4`($sp)
$POP r29,`$FRAME-$SIZE_T*3`($sp)
$POP r30,`$FRAME-$SIZE_T*2`($sp)
$POP r31,`$FRAME-$SIZE_T*1`($sp)
mtlr r0
addi $sp,$sp,$FRAME
blr
.long 0
.byte 0,12,4,1,0x80,18,3,0
.long 0
___
if ($SZ==4 || $SIZE_T==8) {
$code.=<<___;
.align 4
Lsha2_block_private:
$LD $t1,0($Tbl)
___
for($i=0;$i<16;$i++) {
$code.=<<___ if ($SZ==4 && !$LITTLE_ENDIAN);
lwz @X[$i],`$i*$SZ`($inp)
___
$code.=<<___ if ($SZ==4 && $LITTLE_ENDIAN);
lwz $a0,`$i*$SZ`($inp)
rotlwi @X[$i],$a0,8
rlwimi @X[$i],$a0,24,0,7
rlwimi @X[$i],$a0,24,16,23
___
# 64-bit loads are split to 2x32-bit ones, as CPU can't handle
# unaligned 64-bit loads, only 32-bit ones...
$code.=<<___ if ($SZ==8 && !$LITTLE_ENDIAN);
lwz $t0,`$i*$SZ`($inp)
lwz @X[$i],`$i*$SZ+4`($inp)
insrdi @X[$i],$t0,32,0
___
$code.=<<___ if ($SZ==8 && $LITTLE_ENDIAN);
lwz $a0,`$i*$SZ`($inp)
lwz $a1,`$i*$SZ+4`($inp)
rotlwi $t0,$a0,8
rotlwi @X[$i],$a1,8
rlwimi $t0,$a0,24,0,7
rlwimi @X[$i],$a1,24,0,7
rlwimi $t0,$a0,24,16,23
rlwimi @X[$i],$a1,24,16,23
insrdi @X[$i],$t0,32,0
___
&ROUND_00_15($i,@V);
unshift(@V,pop(@V));
}
$code.=<<___;
li $t0,`$rounds/16-1`
mtctr $t0
.align 4
Lrounds:
addi $Tbl,$Tbl,`16*$SZ`
___
for(;$i<32;$i++) {
&ROUND_16_xx($i,@V);
unshift(@V,pop(@V));
}
$code.=<<___;
bdnz Lrounds
$POP $ctx,`$FRAME-$SIZE_T*22`($sp)
$POP $inp,`$FRAME-$SIZE_T*23`($sp) ; inp pointer
$POP $num,`$FRAME-$SIZE_T*24`($sp) ; end pointer
subi $Tbl,$Tbl,`($rounds-16)*$SZ` ; rewind Tbl
$LD r16,`0*$SZ`($ctx)
$LD r17,`1*$SZ`($ctx)
$LD r18,`2*$SZ`($ctx)
$LD r19,`3*$SZ`($ctx)
$LD r20,`4*$SZ`($ctx)
$LD r21,`5*$SZ`($ctx)
$LD r22,`6*$SZ`($ctx)
addi $inp,$inp,`16*$SZ` ; advance inp
$LD r23,`7*$SZ`($ctx)
add $A,$A,r16
add $B,$B,r17
$PUSH $inp,`$FRAME-$SIZE_T*23`($sp)
add $C,$C,r18
$ST $A,`0*$SZ`($ctx)
add $D,$D,r19
$ST $B,`1*$SZ`($ctx)
add $E,$E,r20
$ST $C,`2*$SZ`($ctx)
add $F,$F,r21
$ST $D,`3*$SZ`($ctx)
add $G,$G,r22
$ST $E,`4*$SZ`($ctx)
add $H,$H,r23
$ST $F,`5*$SZ`($ctx)
$ST $G,`6*$SZ`($ctx)
$UCMP $inp,$num
$ST $H,`7*$SZ`($ctx)
bne Lsha2_block_private
blr
.long 0
.byte 0,12,0x14,0,0,0,0,0
.size $func,.-$func
___
} else {
########################################################################
# SHA512 for PPC32, X vector is off-loaded to stack...
#
# | sha512
# | -m32
# ----------------------+-----------------------
# PPC74x0,gcc-4.0.1 | +48%
# POWER6,gcc-4.4.6 | +124%(*)
# POWER7,gcc-4.4.6 | +79%(*)
# e300,gcc-4.1.0 | +167%
#
# (*) ~1/3 of -m64 result [and ~20% better than -m32 code generated
# by xlc-12.1]
my $XOFF=$LOCALS;
my @V=map("r$_",(16..31)); # A..H
my ($s0,$s1,$t0,$t1,$t2,$t3,$a0,$a1,$a2,$a3)=map("r$_",(0,5,6,8..12,14,15));
my ($x0,$x1)=("r3","r4"); # zaps $ctx and $inp
sub ROUND_00_15_ppc32 {
my ($i, $ahi,$alo,$bhi,$blo,$chi,$clo,$dhi,$dlo,
$ehi,$elo,$fhi,$flo,$ghi,$glo,$hhi,$hlo)=@_;
$code.=<<___;
lwz $t2,`$SZ*($i%16)+($LITTLE_ENDIAN^4)`($Tbl)
xor $a0,$flo,$glo
lwz $t3,`$SZ*($i%16)+($LITTLE_ENDIAN^0)`($Tbl)
xor $a1,$fhi,$ghi
addc $hlo,$hlo,$t0 ; h+=x[i]
stw $t0,`$XOFF+0+$SZ*($i%16)`($sp) ; save x[i]
srwi $s0,$elo,$Sigma1[0]
srwi $s1,$ehi,$Sigma1[0]
and $a0,$a0,$elo
adde $hhi,$hhi,$t1
and $a1,$a1,$ehi
stw $t1,`$XOFF+4+$SZ*($i%16)`($sp)
srwi $t0,$elo,$Sigma1[1]
srwi $t1,$ehi,$Sigma1[1]
addc $hlo,$hlo,$t2 ; h+=K512[i]
insrwi $s0,$ehi,$Sigma1[0],0
insrwi $s1,$elo,$Sigma1[0],0
xor $a0,$a0,$glo ; Ch(e,f,g)
adde $hhi,$hhi,$t3
xor $a1,$a1,$ghi
insrwi $t0,$ehi,$Sigma1[1],0
insrwi $t1,$elo,$Sigma1[1],0
addc $hlo,$hlo,$a0 ; h+=Ch(e,f,g)
srwi $t2,$ehi,$Sigma1[2]-32
srwi $t3,$elo,$Sigma1[2]-32
xor $s0,$s0,$t0
xor $s1,$s1,$t1
insrwi $t2,$elo,$Sigma1[2]-32,0
insrwi $t3,$ehi,$Sigma1[2]-32,0
xor $a0,$alo,$blo ; a^b, b^c in next round
adde $hhi,$hhi,$a1
xor $a1,$ahi,$bhi
xor $s0,$s0,$t2 ; Sigma1(e)
xor $s1,$s1,$t3
srwi $t0,$alo,$Sigma0[0]
and $a2,$a2,$a0
addc $hlo,$hlo,$s0 ; h+=Sigma1(e)
and $a3,$a3,$a1
srwi $t1,$ahi,$Sigma0[0]
srwi $s0,$ahi,$Sigma0[1]-32
adde $hhi,$hhi,$s1
srwi $s1,$alo,$Sigma0[1]-32
insrwi $t0,$ahi,$Sigma0[0],0
insrwi $t1,$alo,$Sigma0[0],0
xor $a2,$a2,$blo ; Maj(a,b,c)
addc $dlo,$dlo,$hlo ; d+=h
xor $a3,$a3,$bhi
insrwi $s0,$alo,$Sigma0[1]-32,0
insrwi $s1,$ahi,$Sigma0[1]-32,0
adde $dhi,$dhi,$hhi
srwi $t2,$ahi,$Sigma0[2]-32
srwi $t3,$alo,$Sigma0[2]-32
xor $s0,$s0,$t0
addc $hlo,$hlo,$a2 ; h+=Maj(a,b,c)
xor $s1,$s1,$t1
insrwi $t2,$alo,$Sigma0[2]-32,0
insrwi $t3,$ahi,$Sigma0[2]-32,0
adde $hhi,$hhi,$a3
___
$code.=<<___ if ($i>=15);
lwz $t0,`$XOFF+0+$SZ*(($i+2)%16)`($sp)
lwz $t1,`$XOFF+4+$SZ*(($i+2)%16)`($sp)
___
$code.=<<___ if ($i<15 && !$LITTLE_ENDIAN);
lwz $t1,`$SZ*($i+1)+0`($inp)
lwz $t0,`$SZ*($i+1)+4`($inp)
___
$code.=<<___ if ($i<15 && $LITTLE_ENDIAN);
lwz $a2,`$SZ*($i+1)+0`($inp)
lwz $a3,`$SZ*($i+1)+4`($inp)
rotlwi $t1,$a2,8
rotlwi $t0,$a3,8
rlwimi $t1,$a2,24,0,7
rlwimi $t0,$a3,24,0,7
rlwimi $t1,$a2,24,16,23
rlwimi $t0,$a3,24,16,23
___
$code.=<<___;
xor $s0,$s0,$t2 ; Sigma0(a)
xor $s1,$s1,$t3
addc $hlo,$hlo,$s0 ; h+=Sigma0(a)
adde $hhi,$hhi,$s1
___
$code.=<<___ if ($i==15);
lwz $x0,`$XOFF+0+$SZ*(($i+1)%16)`($sp)
lwz $x1,`$XOFF+4+$SZ*(($i+1)%16)`($sp)
___
}
sub ROUND_16_xx_ppc32 {
my ($i, $ahi,$alo,$bhi,$blo,$chi,$clo,$dhi,$dlo,
$ehi,$elo,$fhi,$flo,$ghi,$glo,$hhi,$hlo)=@_;
$code.=<<___;
srwi $s0,$t0,$sigma0[0]
srwi $s1,$t1,$sigma0[0]
srwi $t2,$t0,$sigma0[1]
srwi $t3,$t1,$sigma0[1]
insrwi $s0,$t1,$sigma0[0],0
insrwi $s1,$t0,$sigma0[0],0
srwi $a0,$t0,$sigma0[2]
insrwi $t2,$t1,$sigma0[1],0
insrwi $t3,$t0,$sigma0[1],0
insrwi $a0,$t1,$sigma0[2],0
xor $s0,$s0,$t2
lwz $t2,`$XOFF+0+$SZ*(($i+14)%16)`($sp)
srwi $a1,$t1,$sigma0[2]
xor $s1,$s1,$t3
lwz $t3,`$XOFF+4+$SZ*(($i+14)%16)`($sp)
xor $a0,$a0,$s0
srwi $s0,$t2,$sigma1[0]
xor $a1,$a1,$s1
srwi $s1,$t3,$sigma1[0]
addc $x0,$x0,$a0 ; x[i]+=sigma0(x[i+1])
srwi $a0,$t3,$sigma1[1]-32
insrwi $s0,$t3,$sigma1[0],0
insrwi $s1,$t2,$sigma1[0],0
adde $x1,$x1,$a1
srwi $a1,$t2,$sigma1[1]-32
insrwi $a0,$t2,$sigma1[1]-32,0
srwi $t2,$t2,$sigma1[2]
insrwi $a1,$t3,$sigma1[1]-32,0
insrwi $t2,$t3,$sigma1[2],0
xor $s0,$s0,$a0
lwz $a0,`$XOFF+0+$SZ*(($i+9)%16)`($sp)
srwi $t3,$t3,$sigma1[2]
xor $s1,$s1,$a1
lwz $a1,`$XOFF+4+$SZ*(($i+9)%16)`($sp)
xor $s0,$s0,$t2
addc $x0,$x0,$a0 ; x[i]+=x[i+9]
xor $s1,$s1,$t3
adde $x1,$x1,$a1
addc $x0,$x0,$s0 ; x[i]+=sigma1(x[i+14])
adde $x1,$x1,$s1
___
($t0,$t1,$x0,$x1) = ($x0,$x1,$t0,$t1);
&ROUND_00_15_ppc32(@_);
}
$code.=<<___;
.align 4
Lsha2_block_private:
___
$code.=<<___ if (!$LITTLE_ENDIAN);
lwz $t1,0($inp)
xor $a2,@V[3],@V[5] ; B^C, magic seed
lwz $t0,4($inp)
xor $a3,@V[2],@V[4]
___
$code.=<<___ if ($LITTLE_ENDIAN);
lwz $a1,0($inp)
xor $a2,@V[3],@V[5] ; B^C, magic seed
lwz $a0,4($inp)
xor $a3,@V[2],@V[4]
rotlwi $t1,$a1,8
rotlwi $t0,$a0,8
rlwimi $t1,$a1,24,0,7
rlwimi $t0,$a0,24,0,7
rlwimi $t1,$a1,24,16,23
rlwimi $t0,$a0,24,16,23
___
for($i=0;$i<16;$i++) {
&ROUND_00_15_ppc32($i,@V);
unshift(@V,pop(@V)); unshift(@V,pop(@V));
($a0,$a1,$a2,$a3) = ($a2,$a3,$a0,$a1);
}
$code.=<<___;
li $a0,`$rounds/16-1`
mtctr $a0
.align 4
Lrounds:
addi $Tbl,$Tbl,`16*$SZ`
___
for(;$i<32;$i++) {
&ROUND_16_xx_ppc32($i,@V);
unshift(@V,pop(@V)); unshift(@V,pop(@V));
($a0,$a1,$a2,$a3) = ($a2,$a3,$a0,$a1);
}
$code.=<<___;
bdnz Lrounds
$POP $ctx,`$FRAME-$SIZE_T*22`($sp)
$POP $inp,`$FRAME-$SIZE_T*23`($sp) ; inp pointer
$POP $num,`$FRAME-$SIZE_T*24`($sp) ; end pointer
subi $Tbl,$Tbl,`($rounds-16)*$SZ` ; rewind Tbl
lwz $t0,`$LITTLE_ENDIAN^0`($ctx)
lwz $t1,`$LITTLE_ENDIAN^4`($ctx)
lwz $t2,`$LITTLE_ENDIAN^8`($ctx)
lwz $t3,`$LITTLE_ENDIAN^12`($ctx)
lwz $a0,`$LITTLE_ENDIAN^16`($ctx)
lwz $a1,`$LITTLE_ENDIAN^20`($ctx)
lwz $a2,`$LITTLE_ENDIAN^24`($ctx)
addc @V[1],@V[1],$t1
lwz $a3,`$LITTLE_ENDIAN^28`($ctx)
adde @V[0],@V[0],$t0
lwz $t0,`$LITTLE_ENDIAN^32`($ctx)
addc @V[3],@V[3],$t3
lwz $t1,`$LITTLE_ENDIAN^36`($ctx)
adde @V[2],@V[2],$t2
lwz $t2,`$LITTLE_ENDIAN^40`($ctx)
addc @V[5],@V[5],$a1
lwz $t3,`$LITTLE_ENDIAN^44`($ctx)
adde @V[4],@V[4],$a0
lwz $a0,`$LITTLE_ENDIAN^48`($ctx)
addc @V[7],@V[7],$a3
lwz $a1,`$LITTLE_ENDIAN^52`($ctx)
adde @V[6],@V[6],$a2
lwz $a2,`$LITTLE_ENDIAN^56`($ctx)
addc @V[9],@V[9],$t1
lwz $a3,`$LITTLE_ENDIAN^60`($ctx)
adde @V[8],@V[8],$t0
stw @V[0],`$LITTLE_ENDIAN^0`($ctx)
stw @V[1],`$LITTLE_ENDIAN^4`($ctx)
addc @V[11],@V[11],$t3
stw @V[2],`$LITTLE_ENDIAN^8`($ctx)
stw @V[3],`$LITTLE_ENDIAN^12`($ctx)
adde @V[10],@V[10],$t2
stw @V[4],`$LITTLE_ENDIAN^16`($ctx)
stw @V[5],`$LITTLE_ENDIAN^20`($ctx)
addc @V[13],@V[13],$a1
stw @V[6],`$LITTLE_ENDIAN^24`($ctx)
stw @V[7],`$LITTLE_ENDIAN^28`($ctx)
adde @V[12],@V[12],$a0
stw @V[8],`$LITTLE_ENDIAN^32`($ctx)
stw @V[9],`$LITTLE_ENDIAN^36`($ctx)
addc @V[15],@V[15],$a3
stw @V[10],`$LITTLE_ENDIAN^40`($ctx)
stw @V[11],`$LITTLE_ENDIAN^44`($ctx)
adde @V[14],@V[14],$a2
stw @V[12],`$LITTLE_ENDIAN^48`($ctx)
stw @V[13],`$LITTLE_ENDIAN^52`($ctx)
stw @V[14],`$LITTLE_ENDIAN^56`($ctx)
stw @V[15],`$LITTLE_ENDIAN^60`($ctx)
addi $inp,$inp,`16*$SZ` ; advance inp
$PUSH $inp,`$FRAME-$SIZE_T*23`($sp)
$UCMP $inp,$num
bne Lsha2_block_private
blr
.long 0
.byte 0,12,0x14,0,0,0,0,0
.size $func,.-$func
___
}
# Ugly hack here, because PPC assembler syntax seem to vary too
# much from platforms to platform...
$code.=<<___;
.align 6
LPICmeup:
mflr r0
bcl 20,31,\$+4
mflr $Tbl ; vvvvvv "distance" between . and 1st data entry
addi $Tbl,$Tbl,`64-8`
mtlr r0
blr
.long 0
.byte 0,12,0x14,0,0,0,0,0
.space `64-9*4`
___
$code.=<<___ if ($SZ==8);
.quad 0x428a2f98d728ae22,0x7137449123ef65cd
.quad 0xb5c0fbcfec4d3b2f,0xe9b5dba58189dbbc
.quad 0x3956c25bf348b538,0x59f111f1b605d019
.quad 0x923f82a4af194f9b,0xab1c5ed5da6d8118
.quad 0xd807aa98a3030242,0x12835b0145706fbe
.quad 0x243185be4ee4b28c,0x550c7dc3d5ffb4e2
.quad 0x72be5d74f27b896f,0x80deb1fe3b1696b1
.quad 0x9bdc06a725c71235,0xc19bf174cf692694
.quad 0xe49b69c19ef14ad2,0xefbe4786384f25e3
.quad 0x0fc19dc68b8cd5b5,0x240ca1cc77ac9c65
.quad 0x2de92c6f592b0275,0x4a7484aa6ea6e483
.quad 0x5cb0a9dcbd41fbd4,0x76f988da831153b5
.quad 0x983e5152ee66dfab,0xa831c66d2db43210
.quad 0xb00327c898fb213f,0xbf597fc7beef0ee4
.quad 0xc6e00bf33da88fc2,0xd5a79147930aa725
.quad 0x06ca6351e003826f,0x142929670a0e6e70
.quad 0x27b70a8546d22ffc,0x2e1b21385c26c926
.quad 0x4d2c6dfc5ac42aed,0x53380d139d95b3df
.quad 0x650a73548baf63de,0x766a0abb3c77b2a8
.quad 0x81c2c92e47edaee6,0x92722c851482353b
.quad 0xa2bfe8a14cf10364,0xa81a664bbc423001
.quad 0xc24b8b70d0f89791,0xc76c51a30654be30
.quad 0xd192e819d6ef5218,0xd69906245565a910
.quad 0xf40e35855771202a,0x106aa07032bbd1b8
.quad 0x19a4c116b8d2d0c8,0x1e376c085141ab53
.quad 0x2748774cdf8eeb99,0x34b0bcb5e19b48a8
.quad 0x391c0cb3c5c95a63,0x4ed8aa4ae3418acb
.quad 0x5b9cca4f7763e373,0x682e6ff3d6b2b8a3
.quad 0x748f82ee5defb2fc,0x78a5636f43172f60
.quad 0x84c87814a1f0ab72,0x8cc702081a6439ec
.quad 0x90befffa23631e28,0xa4506cebde82bde9
.quad 0xbef9a3f7b2c67915,0xc67178f2e372532b
.quad 0xca273eceea26619c,0xd186b8c721c0c207
.quad 0xeada7dd6cde0eb1e,0xf57d4f7fee6ed178
.quad 0x06f067aa72176fba,0x0a637dc5a2c898a6
.quad 0x113f9804bef90dae,0x1b710b35131c471b
.quad 0x28db77f523047d84,0x32caab7b40c72493
.quad 0x3c9ebe0a15c9bebc,0x431d67c49c100d4c
.quad 0x4cc5d4becb3e42b6,0x597f299cfc657e2a
.quad 0x5fcb6fab3ad6faec,0x6c44198c4a475817
___
$code.=<<___ if ($SZ==4);
.long 0x428a2f98,0x71374491,0xb5c0fbcf,0xe9b5dba5
.long 0x3956c25b,0x59f111f1,0x923f82a4,0xab1c5ed5
.long 0xd807aa98,0x12835b01,0x243185be,0x550c7dc3
.long 0x72be5d74,0x80deb1fe,0x9bdc06a7,0xc19bf174
.long 0xe49b69c1,0xefbe4786,0x0fc19dc6,0x240ca1cc
.long 0x2de92c6f,0x4a7484aa,0x5cb0a9dc,0x76f988da
.long 0x983e5152,0xa831c66d,0xb00327c8,0xbf597fc7
.long 0xc6e00bf3,0xd5a79147,0x06ca6351,0x14292967
.long 0x27b70a85,0x2e1b2138,0x4d2c6dfc,0x53380d13
.long 0x650a7354,0x766a0abb,0x81c2c92e,0x92722c85
.long 0xa2bfe8a1,0xa81a664b,0xc24b8b70,0xc76c51a3
.long 0xd192e819,0xd6990624,0xf40e3585,0x106aa070
.long 0x19a4c116,0x1e376c08,0x2748774c,0x34b0bcb5
.long 0x391c0cb3,0x4ed8aa4a,0x5b9cca4f,0x682e6ff3
.long 0x748f82ee,0x78a5636f,0x84c87814,0x8cc70208
.long 0x90befffa,0xa4506ceb,0xbef9a3f7,0xc67178f2
___
$code =~ s/\`([^\`]*)\`/eval $1/gem;
print $code;
close STDOUT or die "error closing STDOUT: $!";
```
|
```xml
import {
GoogleFontsDownloadError,
GoogleFontsLoadingError,
} from 'storybook/internal/server-errors';
import { fetchCSSFromGoogleFonts } from 'next/dist/compiled/@next/font/dist/google/fetch-css-from-google-fonts';
import { getFontAxes } from 'next/dist/compiled/@next/font/dist/google/get-font-axes';
import { getGoogleFontsUrl } from 'next/dist/compiled/@next/font/dist/google/get-google-fonts-url';
import { validateGoogleFontFunctionCall } from 'next/dist/compiled/@next/font/dist/google/validate-google-font-function-call';
// eslint-disable-next-line @typescript-eslint/ban-ts-comment
// @ts-expect-error
import loaderUtils from 'next/dist/compiled/loader-utils3';
import type { LoaderOptions } from '../types';
const cssCache = new Map<string, string>();
export async function getFontFaceDeclarations(options: LoaderOptions) {
const { fontFamily, weights, styles, selectedVariableAxes, display, variable } =
validateGoogleFontFunctionCall(options.fontFamily, options.props);
const fontAxes = getFontAxes(fontFamily, weights, styles, selectedVariableAxes);
const url = getGoogleFontsUrl(fontFamily, fontAxes, display);
try {
const hasCachedCSS = cssCache.has(url);
const fontFaceCSS = hasCachedCSS
? cssCache.get(url)
: await fetchCSSFromGoogleFonts(url, fontFamily, true).catch(() => null);
if (!hasCachedCSS) {
cssCache.set(url, fontFaceCSS as string);
} else {
cssCache.delete(url);
}
if (fontFaceCSS === null) {
throw new GoogleFontsDownloadError({
fontFamily,
url,
});
}
return {
id: loaderUtils.getHashDigest(url, 'md5', 'hex', 6),
fontFamily,
fontFaceCSS,
weights,
styles,
variable,
};
} catch (error) {
throw new GoogleFontsLoadingError({ error, url });
}
}
```
|
```xml
<manifest xmlns:android="path_to_url"
package="com.roger.catloadinglibrary">
<application
android:allowBackup="true"
android:label="@string/app_name"
android:supportsRtl="true">
</application>
</manifest>
```
|
```batchfile
:: Keystone assembler engine (www.keystone-engine.org)
:: Build Keystone static library (keystone.lib) on Windows with CMake & Nmake
:: By Nguyen Anh Quynh, 2016
:: This generates .\llvm\lib\keystone.lib
:: Usage: nmake-dll.bat [x86 arm aarch64 m68k mips sparc], default build all.
@echo off
set flags="-DCMAKE_BUILD_TYPE=Release -DBUILD_SHARED_LIBS=OFF"
set allparams=
:loop
set str=%1
if "%str%"=="" (
goto end
)
set allparams=%allparams% %str%
shift /0
goto loop
:end
if "%allparams%"=="" (
goto eof
)
:: remove left, right blank
:intercept_left
if "%allparams:~0,1%"==" " set "allparams=%allparams:~1%" & goto intercept_left
:intercept_right
if "%allparams:~-1%"==" " set "allparams=%allparams:~0,-1%" & goto intercept_right
:eof
if "%allparams%"=="" (
cmake "%flags%" -DLLVM_TARGETS_TO_BUILD="all" -G "NMake Makefiles" ..
) else (
cmake "%flags%" "-DLLVM_TARGETS_TO_BUILD=%allparams%" -G "NMake Makefiles" ..
)
nmake
```
|
```yaml
key: digitalocean
title: DigitalOcean Spaces
description: DigitalOcean provides developers and businesses a reliable, easy-to-use cloud computing platform of virtual servers (Droplets), object storage (Spaces) and more.
author: andrewsim
logo: path_to_url
website: path_to_url
isAvailable: true
supportedModes:
- push
defaultMode: push
schedule: false
props:
endpoint:
type: String
title: Endpoint
hint: The DigitalOcean spaces endpoint that has the form ${REGION}.digitaloceanspaces.com
default: nyc3.digitaloceanspaces.com
enum:
- ams3.digitaloceanspaces.com
- fra1.digitaloceanspaces.com
- nyc3.digitaloceanspaces.com
- sfo2.digitaloceanspaces.com
- sfo3.digitaloceanspaces.com
- sgp1.digitaloceanspaces.com
order: 1
bucket:
type: String
title: Space Unique Name
hint: The unique space name to create (e.g. wiki-johndoe)
order: 2
accessKeyId:
type: String
title: Access Key ID
hint: The Access Key (Generated in API > Tokens/Keys > Spaces access keys).
order: 3
secretAccessKey :
type: String
title: Access Key Secret
hint: The Access Key Secret for the Access Key ID you created above.
sensitive: true
order: 4
actions:
- handler: exportAll
label: Export All
hint: Output all content from the DB to DigitalOcean Spaces, overwriting any existing data. If you enabled DigitalOcean Spaces after content was created or you temporarily disabled it, you'll want to execute this action to add the missing content.
```
|
Patrick Raymond Fugit (; born October 27, 1982) is an American actor. He has appeared in the films Almost Famous (2000), White Oleander (2002), Spun (2003), Saved! (2004) and Wristcutters: A Love Story (2006), and portrayed Kyle Barnes in the Cinemax series Outcast. He also played Owen in the video game The Last of Us Part II.
Early life
Fugit was born in Salt Lake City, Utah and lived briefly in Danbury, New Hampshire. His mother, Jan Clark-Fugit, is a dance teacher, and his father, Bruce Fugit, is an electrical engineer. Fugit is the oldest of three children: he has a younger sister and a younger brother. Fugit attended East High School. He appeared in a school production of The Twelve Dancing Princesses as the shoemaker when he was in seventh grade. He has been a skateboarder since he was fifteen.
Career
Fugit's career launched when he was cast as the young rock-fan-turned-reporter in Cameron Crowe's Almost Famous. Fugit said that he did not have any knowledge of 1970s rock music before starting the music-laden project.
Fugit played an aspiring comic book artist in White Oleander (2002) and a naive drug addict in the dark comedy Spun (2003).
His next film, Saved! (2004), was a satirical look at the religious right in high schools. Fugit's character was originally a surfer, but it changed into a skateboarder due to his skateboarding experience.
Fugit starred in The Amateurs and played Evra Von in Cirque du Freak: The Vampire's Assistant (2009).
In 2011, Fugit was cast in We Bought A Zoo, another Cameron Crowe film.
In 2016, he joined the cast of Cinemax's television series Outcast. He stated he enjoyed playing a father but worried that not being one in real life at the time might make him seem awkward.
In 2020, Fugit was cast in a lead role on ABC's pilot for Thirtysomething(else), a sequel to Thirtysomething; however, the pilot was scrapped by ABC later that same year.
Personal life
Fugit and his best friend, David Fetzer, formed a folk rock band, Mushman, in which Fugit played the guitar and sometimes sang. Fetzer died in 2012. Fugit studies flamenco guitar, which he played on the Cavedoll song "Mayday" and the Mushman song "Brennan's Theme" for the ending scene in Wristcutters: A Love Story.
Growing up in Salt Lake City, Fugit says he was "the weird kid" in school because he learned ballet as his mother was a ballet teacher and because he was not Mormon but attended a predominantly Mormon school.
Fugit has a child with his long-term partner, actress Jennifer Del Rosario.
Filmography
Film
Television
Video games
References
External links
1982 births
20th-century American male actors
21st-century American male actors
American male film actors
American male television actors
American male voice actors
American skateboarders
Living people
Male actors from Salt Lake City
|
```smalltalk
namespace GameServerCore.Enums
{
public enum DamageType : byte
{
DAMAGE_TYPE_PHYSICAL = 0x0,
DAMAGE_TYPE_MAGICAL = 0x1,
DAMAGE_TYPE_TRUE = 0x2,
DAMAGE_TYPE_MIXED = 0x3
}
}
```
|
```vue
<template>
<section class="page page--ui-switch">
<h2 class="page__title">UiSwitch</h2>
<p>UiSwitch shows a switch that allows the user to toggle between two states. It supports keyboard focus and a disabled state.</p>
<p>The position of the switch relative to the label can be customized.</p>
<h3 class="page__section-title">
Examples <a href="path_to_url" target="_blank" rel="noopener">View Source</a>
</h3>
<div class="page__examples">
<h4 class="page__demo-title">Basic</h4>
<div class="page__demo-group">
<ui-switch v-model="switch1">Bluetooth</ui-switch>
<ui-switch v-model="switch2">WiFi</ui-switch>
<ui-switch v-model="switch3">Location</ui-switch>
<ui-switch v-model="switch4" disabled>Can't change this</ui-switch>
<ui-switch v-model="switch5" disabled>Can't change this too</ui-switch>
</div>
<h4 class="page__demo-title">Color: accent</h4>
<div class="page__demo-group">
<ui-switch v-model="switch1" color="accent">Bluetooth</ui-switch>
<ui-switch v-model="switch2" color="accent">WiFi</ui-switch>
<ui-switch v-model="switch3" color="accent">Location</ui-switch>
<ui-switch v-model="switch4" color="accent" disabled>Can't change this</ui-switch>
<ui-switch v-model="switch5" color="accent" disabled>Can't change this too</ui-switch>
</div>
<h4 class="page__demo-title">Switch position: right</h4>
<div class="page__demo-group has-switch-right">
<ui-switch v-model="switch1" switch-position="right">Bluetooth</ui-switch>
<ui-switch v-model="switch2" switch-position="right">WiFi</ui-switch>
<ui-switch v-model="switch3" switch-position="right">Location</ui-switch>
<ui-switch v-model="switch4" switch-position="right" disabled>Can't change this</ui-switch>
<ui-switch v-model="switch5" switch-position="right" disabled>Can't change this too</ui-switch>
</div>
</div>
<h3 class="page__section-title">API</h3>
<ui-tabs raised>
<ui-tab title="Props">
<div class="table-responsive">
<table class="table">
<thead>
<tr>
<th>Name</th>
<th>Type</th>
<th>Default</th>
<th>Description</th>
</tr>
</thead>
<tbody>
<tr>
<td>name</td>
<td>String</td>
<td></td>
<td>The <code>name</code> attribute of the switch input element.</td>
</tr>
<tr>
<td>label</td>
<td>String</td>
<td></td>
<td>
<p>The switch label (text only). For HTML, use the <code>default</code> slot.</p>
</td>
</tr>
<tr>
<td class="no-wrap">modelValue, v-model *</td>
<td></td>
<td></td>
<td>
<p>The model that the switch value syncs to.</p>
<p>The <code>trueValue</code> prop will be written to this model when the switch is turned on and the <code>falseValue</code> prop will be written to it when the switch is turned off.</p>
<p>If you are not using <code>v-model</code>, you should listen for the <code>update:modelValue</code> event and update <code>modelValue</code>.</p>
</td>
</tr>
<tr>
<td>checked</td>
<td>Boolean</td>
<td><code>false</code></td>
<td>Whether or not the switch is on by default.</td>
</tr>
<tr>
<td>trueValue</td>
<td></td>
<td><code>true</code></td>
<td>The value that will be written to the model when the switch is turned on.</td>
</tr>
<tr>
<td>falseValue</td>
<td></td>
<td><code>false</code></td>
<td>The value that will be written to the model when the switch is turned off.</td>
</tr>
<tr>
<td>submittedValue</td>
<td></td>
<td><code>"on"</code></td>
<td>The value that will be submitted for the switch when it is turned on. Applied as the <code>modelValue</code> attribute of the switch's input element.</td>
</tr>
<tr>
<td>color</td>
<td>String</td>
<td><code>"primary"</code></td>
<td>The color of the switch when turned on. One of <code>primary</code> or <code>accent</code>.</td>
</tr>
<tr>
<td>switchPosition</td>
<td>String</td>
<td><code>"left"</code></td>
<td>
<p>The position of the switch relative to the label.</p>
<p>One of <code>left</code> or <code>right</code>.</p>
</td>
</tr>
<tr>
<td>tabindex</td>
<td>Number, String</td>
<td></td>
<td>The switch input <code>tabindex</code>.</td>
</tr>
<tr>
<td>disabled</td>
<td>Boolean</td>
<td><code>false</code></td>
<td>
<p>Whether or not the switch is disabled.</p>
<p>Set to <code>true</code> to disable the switch.</p>
</td>
</tr>
</tbody>
</table>
</div>
* Required prop
</ui-tab>
<ui-tab title="Slots">
<div class="table-responsive">
<table class="table">
<thead>
<tr>
<th>Name</th>
<th>Description</th>
</tr>
</thead>
<tbody>
<tr>
<td>(default)</td>
<td>Holds the switch label and can contain HTML.</td>
</tr>
</tbody>
</table>
</div>
</ui-tab>
<ui-tab title="Events">
<div class="table-responsive">
<table class="table">
<thead>
<tr>
<th>Name</th>
<th>Description</th>
</tr>
</thead>
<tbody>
<tr>
<td>focus</td>
<td>
<p>Emitted when the switch is focused.</p>
<p>Listen for it using <code>@focus</code>.</p>
</td>
</tr>
<tr>
<td>blur</td>
<td>
<p>Emitted when the switch loses focus.</p>
<p>Listen for it using <code>@blur</code>.</p>
</td>
</tr>
<tr>
<td>update:modelValue</td>
<td>
<p>Emitted when the switch value is changed. The handler is called with the new value.</p>
<p>If you are not using <code>v-model</code>, you should listen for this event and update the <code>modelValue</code> prop.</p>
<p>Listen for it using <code>@update:modelValue</code>.</p>
</td>
</tr>
<tr>
<td>change</td>
<td>
<p>Emitted when the value of the switch is changed. The handler is called with the new value.</p>
<p>Listen for it using <code>@change</code>.</p>
</td>
</tr>
</tbody>
</table>
</div>
</ui-tab>
<ui-tab title="Methods">
<div class="table-responsive">
<table class="table">
<thead>
<tr>
<th>Name</th>
<th>Description</th>
</tr>
</thead>
<tbody>
<tr>
<td><code>focus()</code></td>
<td>
<p>Call this method to programmatically focus the switch.</p>
<p>Note that the focus ring will not be shown if the user's current <a href="path_to_url" rel="noopener" target="_blank">input modality</a> is not keyboard.</p>
</td>
</tr>
</tbody>
</table>
</div>
</ui-tab>
</ui-tabs>
</section>
</template>
<script>
import UiSwitch from '@/UiSwitch.vue';
import UiTab from '@/UiTab.vue';
import UiTabs from '@/UiTabs.vue';
export default {
components: {
UiSwitch,
UiTab,
UiTabs
},
data() {
return {
switch1: true,
switch2: false,
switch3: true,
switch4: false,
switch5: true
};
}
};
</script>
<style lang="scss">
@import '@/styles/imports';
.page--ui-switch {
.ui-switch {
margin-bottom: rem(8px);
}
.page__demo-group {
margin-bottom: rem(32px);
&.has-switch-right {
max-width: rem(208px);
}
}
}
</style>
```
|
The Strand Theater is a vaudeville theater located at 400 Clifton Avenue in Lakewood Township, Ocean County, New Jersey. It was added to the National Register of Historic Places on April 22, 1982, for its significance in architecture, art, and theater.
History
The theater was designed by Thomas W. Lamb, and built for the Ferber Amusement Company in 1922 as a place for pre-Broadway runs of shows. The first event at the theater was a showing of a silent film, Peacock Alley starring Mae Murray. The next show was a pre-Broadway run of "The Devine Cook" starring Florence Reed.
Within a few years of its opening, the Strand began to host vaudeville shows and silent films. Among the stars who appeared on the Strand's stage early in their careers included Burns and Allen, Milton Berle, and Ray Bolger.
During World War II, the theater became a cinema house, and omitted the vaudeville acts. As suburban multiplex movie theaters were built, the single screen theater lost its audience. During its economic decline it became an adult movie theater in the 1970s. In 1981 the theater was added to the List of Registered Historic Places in New Jersey. The theater received a $2.4 million grant from the New Jersey Economic Development Authority in 1994 for restoration of its Neo-classical and Art Deco interiors. The theater serves as the Ocean County Center for the Arts.
References
External links
Official website
1922 establishments in New Jersey
Buildings and structures in Ocean County, New Jersey
Lakewood Township, New Jersey
National Register of Historic Places in Ocean County, New Jersey
Theatres completed in 1922
Theatres on the National Register of Historic Places in New Jersey
Thomas W. Lamb buildings
New Jersey Register of Historic Places
|
Jason Abbott Abantao Sabio (born 30 June 1986) is a Filipino soccer player who plays as a center-back or a right-back. He is more comfortable at central defense because of his leap, speed, and communication skills.
Born in the Philippines, he migrated to the United States as a child and played collegiate soccer for Birmingham–Southern College. He then played in the semi-professional National Premier Soccer League before moving to the Philippines to play for Kaya and Ceres in the United Football League.
He represented the Philippines national team in the 2012 AFC Challenge Cup in which they finished third, and in the 2012 AFF Championship where they were semi-finalists.
Early life
Sabio was born in Manila, Philippines whose parents are physicians. His mother is originally from Koronadal and his father is from Marikina. In 1989 Sabio's father started working in the United States, and by 1991, Sabio and his mother followed. They were originally based in Long Island, New York but moved to Huntsville, Alabama when Sabio was in the 5th grade. Growing up in Huntsville, he spent a lot of time at his best friend's (named Edward Wills) house due to his parents working a lot. Wills was a soccer player and he was the one who got Sabio into the sport by the 7th grade.
Playing career
College career
Sabio was recruited from Grissom High School by Birmingham-Southern College (BSC) where he received an academic and athletic scholarship. He played for BSC's soccer team, the Panthers from 2004–2007 and won two NCAA Division 1 Big South Conference championships. Sabio revealed that after two years, he took classes at Northwestern University and almost transferred there but decided to stay at BSC due to their better paying scholarship. After graduation, he was offered a contract to play professionally in Germany but declined the offer due to personal obligations and opting to teach and coach in a high school.
Club career
A former Alabama Spirit player, he was signed by Rocket City United (RCU) for the 2009 NPSL season in late April 2009. He made his debut in RCU's opening game on 2 May 2009 as he conceded two goals in their 2–1 defeat to Saturn FC. He would concede another two goals in their following match against Pumas FC but RCU were able to win 5–2. It would be his last match until their 1–1 away draw to Chattanooga FC on 21 June as Sabio had other commitments which included trying out for the Philippines national team. During his absence, RCU suffered a second league defeat, losing 2–0 to Atlanta FC. This would be their last defeat in the regular season and Sabio would be part of RCU's undefeated run which led them to win the Southeast Division Championship. However, he conceded four goals in a 4–2 defeat to the Erie Admirals in the NPSL National semi-finals.
Sabio was bound to play for RCU in the 2010 NPSL season but was unable due to commitments to his law firm work. However, the club reported on 1 February 2011 that he will be returning for the 2011 NPSL season. His first game back came on the opening day of the season. He got an assist and a clean sheet as RCU defeated Knoxville Force 2–0. He would practically the miss the rest the season due to being on international duty with the Philippines national team.
On 13 August 2011, it was reported that Sabio had signed for Kaya in the Philippines.
International career
Sabio was discovered by Philippines national team captain Aly Borromeo. Sabio met him in the summer of 2009 and since then, Borromeo has been getting him to join the Philippines national team. He was not able to do so due to commitments in law school. By January 2011, as the Philippines were preparing for their 2012 AFC Challenge Cup qualification first leg play-off match against Mongolia on 9 February, it was reported that Sabio was one of six new foreign based players that would be trying out for the team. He joined the team on 31 January, just nine days before their match against Mongolia but was still named in the final roster. During the match, he came on as a 70th-minute substitute for Anton del Rosario at right back and provided the assist to Phil Younghusband's injury time goal, as the Philippines eventually won 2–0. Due to the absence of regular central defender Rob Gier, Sabio started and completed the 90 minutes in the second leg against Mongolia. However, he gave away a penalty and eventually conceded two goals, as the Philippines lost 2–1. They still advanced to the group stage of the qualification by winning 3–2 on aggregate.
Coaching career
In the spring of 2008, Sabio was on the coaching staff of John Carroll High School's junior varsity team and varsity team where they won the state championship. While at John Carroll he was also accused multiple times of engaging in sexual misconduct with underage students. In 2009, he also coached the Huntsville High School girls soccer team, Huntsville United soccer club, and an under-12 boys team.
Personal life
He graduated cum laude with a bachelor's degree in biochemistry from Birmingham–Southern College. He then taught physics and environmental science at a high school. As of 2011, he was attending the University of Alabama School of Law and was a player-coach of their soccer team.
Honors
Club
Kaya
UFL Division 1: Runner-up 2012
National team
AFC Challenge Cup: Third 2012
Philippine Peace Cup: 2012
References
External links
Jason Sabio profile at Kaya FC
1986 births
Living people
Filipino emigrants to the United States
Sportspeople from Huntsville, Alabama
Footballers from Metro Manila
People from Marikina
Filipino men's footballers
Filipino expatriate men's footballers
Philippines men's international footballers
Men's association football central defenders
United City F.C. players
Birmingham–Southern College alumni
Rocket City United players
|
```kotlin
package com.reactnativenavigation.views.element.animators
import android.animation.Animator
import android.animation.ObjectAnimator
import android.view.View
import com.facebook.react.views.image.ReactImageView
import com.reactnativenavigation.options.SharedElementTransitionOptions
class RotationAnimator(from: View, to: View) : PropertyAnimatorCreator<ReactImageView>(from, to) {
private val fromRotation = from.rotation
private val toRotation = to.rotation
override fun shouldAnimateProperty(fromChild: ReactImageView, toChild: ReactImageView): Boolean {
return fromRotation != toRotation
}
override fun create(options: SharedElementTransitionOptions): Animator {
to.rotation = fromRotation
to.pivotX = 0f
to.pivotY = 0f
return ObjectAnimator.ofFloat(to, View.ROTATION, fromRotation, toRotation)
}
}
```
|
Artazostre (or Artozostre) (Old Persian *Artazauštrī) was a Persian princess, daughter of king Darius the Great (521-485 BC) by Artystone, daughter of Cyrus the Great.
According to the Greek historian Herodotus (VI, 43) Artazostre was given in marriage to Mardonius, young son of the noble Gobryas, not much before he took the command of the Persian army in Thrace and Macedon (c. 493/492 BC).
Artazostre seems not to be mentioned by name in the Persepolis Fortification Tablets (administrative documents found at Persepolis), but there are references (in tablets dated on the year 498 BC) to a "wife of Mardonius, daughter of the king", who received rations for a trip she made with Gobryas and a woman called Radušnamuya or Ardušnamuya, perhaps Gobryas' wife. However, another interpretation of the text suggests that Ardušnamuya was actually the anonymous "wife of Mardonius"
Mardonius had a son, probably by Artazostre, named Artontes.
Notes
References
Brosius, M: Women in Ancient Persia, 559-331 BC, Clarendon Press, Oxford, 1998.
Kellens, J: "Artazostra", in Encyclopaedia Iranica
Lendering, J: "Mardonius", in http://www.livius.org.
Lewis, D: "Persians in Herodotus", in Selected Papers in Greek and Near Eastern History, pp. 345–362, Cambridge University Press, 1997.
Persepolis Fortification Archive Project
Achaemenid princesses
5th-century BC women
5th-century BC Iranian people
Family of Darius the Great
|
Würzburger Kickers is a German association football club playing in Würzburg, Bavaria. In pre-World War II football, the club competed briefly at the highest level in the Bezirksliga Bayern, and during the war, in the Gauliga Bayern. Post-war, it made a single appearance in professional football in the southern division of the 2. Bundesliga in 1977–78. After a long stint in amateur football, dropping as low as the seventh tier, the club began a recovery. The Kickers reached professional football again in 2014–15 after winning promotion to the 3. Liga and the following season were promoted to the 2. Bundesliga.
History
Foundation and early years
FC Würzburger Kickers was founded on 17 November 1907 by local high school students under chairman Georg Beer, soon replaced by Alfred Günzburger. The club gained promotion to the Kreisliga Bayern in 1912 and establish themselves in the league.
Founded in 1907 by high school students, the team has played for most of its history as an unknown local side, although they did manage three seasons in the Bezirksliga Bayern, from 1930 to 1933, and two single season appearances in the Gauliga Bayern (1940–41, 1942–43) one of sixteen top-flight division established in the re-organization of German football under the Third Reich.
1920s to the Second World War
Until the Second World War, Kickers continued to be the determining force in Würzburg football, with FV 04 Würzburg only being able to catch up in the late 1920s.
The club was relegated in the 1922/23 season and subsequently missed out on joining the newly formed Bezirksliga Bayern the next season. Kickers were eventually promoted back to the top division for the 1930/31 season, joining rivals FV 04, where they remained until the league was dissolved in 1933.
Kickers were not selected to join the new Gauliga Bayern and did not reach the top division again until 1940/41 where they were subsequently relegated. Towards the end of World War II, Kickers were forced into a merger with FV 04 to play together as the wartime side (Kriegspielgemeinschaft) KSG Würzburg. The unified club spent two seasons in last place in the Gauliga Bayern (Gruppe Nord). Play was interrupted as the war progressed and the team was disbanded at the end of the conflict.
Kicker's stadium at Randerackerer Straße was also completely destroyed by a bombing raid during the war.
Post-war football and rise to the 2. Bundesliga Süd
After the Second World War, TSV Würzburg joined the Kickers and the club was renamed SV Würzburger Kickers. The club became part of the Landesliga Bayern (II) and put on some strong performances through the 1950s in the Amateurliga Bayern (II-III) but never quite managed a breakthrough. During this time the club moved to the newly built Stadion am Dallenberg in 1967. The club was finally promoted in 1976/77 to the 2. Bundesliga Süd, however they were relegated back to the renamed Bayernliga the following 1977/78 season.
1980s to 2012
Kickers stayed in the Bayernliga until they were relegated in 1983 due to financial difficulties contributed to the fourth division Landesliga Bayern-Nord, which became a fifth tier league in 1994. The club remained in the lower tiers of amateur football with the exception of brief appearances in the Bayernliga in 1990/91 and 1997/98.
Two difficult seasons over 2002–2004 saw the club descend through the Bezirksoberliga Unterfranken (VI) to the Bezirksliga Unterfranken (VII). Kickers recovered and returned to the Oberliga Bayern on the strength of a 2nd place in the 2007–08 Landesliga season where the club met local rival Würzburger FV there for the first Würzburg league derby since 1998–99.
The 2008–09 season proved no success, with Kickers immediately relegated again to the Landesliga, taking until 2012 to win the league again. The team was one of two clubs in the league to apply for a licence in the new tier four Regionalliga Bayern Taking part in the promotion play-off, Kickers earned a bye in the first round and defeated BC Aichach in the second to play in the Regionalliga from 2012. The club was thereby also able to win promotion from the sixth tier to the fourth without playing in the fifth.
Promotions and successes
Since promotion in 2012 Kickers have enjoyed a period of renewed success including winning the 2013–14 Bavarian Cup on penalties in the final against SV Schalding-Heining and thereby qualified for the first round of the 2014–15 DFB-Pokal. In the league, the club finished tenth in 2013 and eleventh in 2014. In the 2014–15 DFB Pokal, Kickers knocked-out Fortuna Düsseldorf in the first round but was defeated by Eintracht Braunschweig in the second round. In the 2014–15 season, Kickers won the Regionalliga Bayern and earned the right to take part in the promotion round to the 3. Liga. They faced 1. FC Saarbrücken, runners-up of the Regionalliga Südwest, and won 1–0 away but also lost 1–0 at home. In the necessary penalty shoot-out, Kickers won 6–5 and were promoted to the 3. Liga.
In March 2016, the club's fans protested against a potential merger with local rival Würzburger FV. Kickers had been asked by the Mayor of Würzburg to hold talks about mergers and cooperation with a number of local clubs in order to receive the city's support in a stadium expansion. Kickers finished the inaugural 3. Liga season in third place, thereby qualifying for the promotion play-off and the 2016–17 DFB-Pokal. The club ensured promotion to the 2. Bundesliga for the first time in almost 40 years by winning 4–1 (2–0/2–1) on aggregate against MSV Duisburg. Despite a strong start to the season, finishing the first half in sixth place, Kickers were relegated in seventeenth place back to the 3. Liga at the end of the season.
The club won the 2018–19 Bavarian Cup following a 3–0 victory in the final over neighbours and rivals Viktoria Aschaffenburg.
In January 2020, it was announced that Felix Magath would serve as sporting director of Flyeralarm Global Soccer group, including Admira Wacker Mödling and Würzburger Kickers.
Kickers returned to the 2. Bundesliga after the 2019–20 season, finishing runners-up behind Bayern Munich II who were ineligible for promotion.
Return to Regionalliga
After promotion to the 2. Bundesliga in 2020, Würzburger Kickers were on a downward trajectory. They suffered relegation after one season in the 3. Liga in 2021, before being relegated again in the 2021–22 season – their second successive relegation – marking a return to the fourth-tier Regionalliga.
Honours
League
3. Liga (III)
Runners-up: 2019–20
Third: 2015–16 (Promoted after play-off)
Bayernliga (III)
Champions: 1977
Bayernliga-Nord (III)
Runners-up: 1955, 1960
Regionalliga Bayern (IV)
Champions: 2014–15
Landesliga Bayern-Nord (IV-V)
Champions: 1990, 1997, 2012
Runners-up: 2008
Bezirksoberliga Unterfranken (VI)
Champions: 2005
Bezirksliga Unterfranken (VII)
Champions: 2004
Cup
Bavarian Cup
Winners: 2014, 2016, 2019
Players
Current squad
Recent managers
Recent managers of the club:
Recent seasons
The recent season-by-season performance of the club:
With the introduction of the Bezirksoberligas in 1988 as the new fifth tier, below the Landesligas, all leagues below dropped one tier. With the introduction of the Regionalligas in 1994 and the 3. Liga in 2008 as the new third tier, below the 2. Bundesliga, all leagues below dropped one tier. With the establishment of the Regionalliga Bayern as the new fourth tier in Bavaria in 2012 the Bayernliga was split into a northern and a southern division, the number of Landesligas expanded from three to five and the Bezirksoberligas abolished. All leagues from the Bezirksligas onwards were elevated one tier.
Key
Stadium
Kickers have played in three different home grounds through their history beginning with Galgenberg, also known as Kugelfang, for two years sharing the ground with local rivals Würzburger FV (formally known as FV 04 Würzburg).
From 1909 to 1967 the club played in Sanderau at the Randersacker Straße stadium before being forced to move due to the expanding city.
Since 1967 the club have played at the Stadion am Dallenberg which currently has a capacity of 13,090 (4,000 seated). In 2013 flyeralarm acquired the naming rights to the stadium which has since been known as flyeralarm Arena. The facility was renovated in 2005 and equipped with floodlights in 2014. In preparation for the 2016/17 season in the 2. Bundesliga the stadium was expanded and under soil heating was added at a cost of €2 million.
Supporters and rivalries
The Würzburg derby is a fierce local rivalry with Würzburger FV, and the fans have a hostility with fans of 1. FC Schweinfurt 05.
Reserve team
The club's reserve team won promotion to the tier five Bayernliga for the first time after defeating VfL Frohnlach in the play-off for the 2016–17 Bayernliga.
The Würzburg derby
The Würzburg derby between Würzburger Kickers and FV Würzburg 04 was first played in 1908 with Kickers winning 5–0. The 2009–10 season was the 19th time, the two clubs played in the same league since 1963, during which time FV folded in 1981 before being reformed. The derby has only beenplayed on professional level only once, in the 1977–78 2. Bundesliga Süd season.
Results since 1963
DFB Cup appearances
The club has qualified for the first round of the German Cup ten times:
Source:
References
External links
Abseits Guide to German Soccer
Football clubs in Germany
Football clubs in Bavaria
Association football clubs established in 1907
Würzburg
Football in Lower Franconia
1907 establishments in Germany
2. Bundesliga clubs
3. Liga clubs
|
Environmental sociology is the study of interactions between societies and their natural environment. The field emphasizes the social factors that influence environmental resource management and cause environmental issues, the processes by which these environmental problems are socially constructed and define as social issues, and societal responses to these problems.
Environmental sociology emerged as a subfield of sociology in the late 1970s in response to the emergence of the environmental movement in the 1960s. It represents a relatively new area of inquiry focusing on an extension of earlier sociology through inclusion of physical context as related to social factors.
Definition
Environmental sociology is typically defined as the sociological study of socio-environmental interactions, although this definition immediately presents the problem of integrating human cultures with the rest of the environment. Different aspects of human interaction with the natural environment are studied by environmental sociologists including population and demography, organizations and institutions, science and technology, health and illness, consumption and sustainability practices, culture and identity, and social inequality and environmental justice. Although the focus of the field is the relationship between society and environment in general, environmental sociologists typically place special emphasis on studying the social factors that cause environmental problems, the societal impacts of those problems, and efforts to solve the problems. In addition, considerable attention is paid to the social processes by which certain environmental conditions become socially defined as problems. Most research in environmental sociology examines contemporary societies.
History
Environmental sociology emerged as a coherent subfield of inquiry after the environmental movement of the 1960s and early 1970s. The works of William R. Catton, Jr. and Riley Dunlap, among others, challenged the constricted anthropocentrism of classical sociology. In the late 1970s, they called for a new holistic, or systems perspective. Since the 1970s, general sociology has noticeably transformed to include environmental forces in social explanations. Environmental sociology has now solidified as a respected, interdisciplinary field of study in academia.
Concepts
Existential dualism
The duality of the human condition rests with cultural uniqueness and evolutionary traits. From one perspective, humans are embedded in the ecosphere and co-evolved alongside other species. Humans share the same basic ecological dependencies as other inhabitants of nature. From the other perspectives, humans are distinguished from other species because of their innovative capacities, distinct cultures and varied institutions. Human creations have the power to independently manipulate, destroy, and transcend the limits of the natural environment.
According to Buttel (2004), there are five major traditions in environmental sociology today: the treadmill of production and other eco-Marxisms, ecological modernization and other sociologies of environmental reform, cultural-environmental sociologies, neo-Malthusianisms, and the new ecological paradigm. In practice, this means five different theories of what to blame for environmental degradation, i.e., what to research or consider as important. These ideas are listed below in the order in which they were invented. Ideas that emerged later built on earlier ideas, and contradicted them.
Neo-Malthusianism
Works such as Hardin's "Tragedy of the Commons" (1969) reformulated Malthusian thought about abstract population increases causing famines into a model of individual selfishness at larger scales causing degradation of common pool resources such as the air, water, the oceans, or general environmental conditions. Hardin offered privatization of resources or government regulation as solutions to environmental degradation caused by tragedy of the commons conditions. Many other sociologists shared this view of solutions well into the 1970s (see Ophuls). There have been many critiques of this view particularly political scientist Elinor Ostrom, or economists Amartya Sen and Ester Boserup.
Even though much of mainstream journalism considers Malthusianism the only view of environmentalism, most sociologists would disagree with Malthusianism since social organizational issues of environmental degradation are more demonstrated to cause environmental problems than abstract population or selfishness per se. For examples of this critique, Ostrom in her book Governing the Commons: The Evolution of Institutions for Collective Action (1990) argues that instead of self-interest always causing degradation, it can sometimes motivate people to take care of their common property resources. To do this they must change the basic organizational rules of resource use. Her research provides evidence for sustainable resource management systems, around common pool resources that have lasted for centuries in some areas of the world.
Amartya Sen argues in his book Poverty and Famines: An Essay on Entitlement and Deprivation (1980) that population expansion fails to cause famines or degradation as Malthusians or Neo-Malthusians argue. Instead, in documented cases a lack of political entitlement to resources that exist in abundance, causes famines in some populations. He documents how famines can occur even in the midst of plenty or in the context of low populations. He argues that famines (and environmental degradation) would only occur in non-functioning democracies or unrepresentative states.
Ester Boserup argues in her book The Conditions of Agricultural Growth: The Economics of Agrarian Change under Population Pressure (1965) from inductive, empirical case analysis that Malthus's more deductive conception of a presumed one-to-one relationship with agricultural scale and population is actually reversed. Instead of agricultural technology and scale determining and limiting population as Malthus attempted to argue, Boserup argued the world is full of cases of the direct opposite: that population changes and expands agricultural methods.
Eco-Marxist scholar Allan Schnaiberg (below) argues against Malthusianism with the rationale that under larger capitalist economies, human degradation moved from localized, population-based degradation to organizationally caused degradation of capitalist political economies to blame. He gives the example of the organized degradation of rainforest areas which states and capitalists push people off the land before it is degraded by organizational means. Thus, many authors are critical of Malthusianism, from sociologists (Schnaiberg) to economists (Sen and Boserup), to political scientists (Ostrom), and all focus on how a country's social organization of its extraction can degrade the environment independent of abstract population.
New Ecological Paradigm
In the 1970s, the New Ecological Paradigm (NEP) conception critiqued the claimed lack of human-environmental focus in the classical sociologists and the sociological priorities their followers created. This was critiqued as the Human Exemptionalism Paradigm (HEP). The HEP viewpoint claims that human-environmental relationships were unimportant sociologically because humans are 'exempt' from environmental forces via cultural change. This view was shaped by the leading Western worldview of the time and the desire for sociology to establish itself as an independent discipline against the then popular racist-biological environmental determinism where environment was all. In this HEP view, human dominance was felt to be justified by the uniqueness of culture, argued to be more adaptable than biological traits. Furthermore, culture also has the capacity to accumulate and innovate, making it capable of solving all natural problems. Therefore, as humans were not conceived of as governed by natural conditions, they were felt to have complete control of their own destiny. Any potential limitation posed by the natural world was felt to be surpassed using human ingenuity. Research proceeded accordingly without environmental analysis.
In the 1970s, sociological scholars Riley Dunlap and William R. Catton, Jr. began recognizing the limits of what would be termed the Human Excemptionalism Paradigm. Catton and Dunlap (1978) suggested a new perspective that took environmental variables into full account. They coined a new theoretical outlook for sociology, the New Ecological Paradigm, with assumptions contrary to HEP.
The NEP recognizes the innovative capacity of humans, but says that humans are still ecologically interdependent as with other species. The NEP notes the power of social and cultural forces but does not profess social determinism. Instead, humans are impacted by the cause, effect, and feedback loops of ecosystems. The Earth has a finite level of natural resources and waste repositories. Thus, the biophysical environment can impose constraints on human activity. They discussed a few harbingers of this NEP in 'hybridized' theorizing about topics that were neither exclusively social nor environmental explanations of environmental conditions. It was additionally a critique of Malthusian views of the 1960s and 1970s.
Dunlap and Catton's work immediately received a critique from Buttel who argued to the contrary that classical sociological foundations could be found for environmental sociology, particularly in Weber's work on ancient "agrarian civilizations" and Durkheim's view of the division of labor as built on a material premise of specialization/specialization in response to material scarcity. This environmental aspect of Durkheim has been discussed by Schnaiberg (1971) as well.
Treadmill of Production Theory
The Treadmill of Production is a theory coined and popularized by Schnaiberg as a way to answer for the increase in U.S. environmental degradation post World War II. At its simplest, this theory states that the more product or commodities are created, the more resources will be used, and the higher the impact will be.
Eco-Marxism
In the middle of the HEP/NEP debate Neo-Marxist ideas of conflict sociology were applied to environmental conflicts. Therefore, some sociologists wanted to stretch Marxist ideas of social conflict to analyze environmental social movements from the Marxist materialist framework instead of interpreting them as a cultural "New Social Movement", separate from material concerns. So "Eco-Marxism" was developed based on using Neo-Marxist Conflict theories concepts of the relative autonomy of the state and applying them to environmental conflict.
Two people following this school were James O'Connor (The Fiscal Crisis of the State, 1971) and later Allan Schnaiberg.
Later, a different trend developed in eco-Marxism via the attention brought to the importance of metabolic analysis in Marx's thought by John Bellamy Foster. Contrary to previous assumptions that classical theorists in sociology all had fallen within a Human Exemptionalist Paradigm, Foster argued that Marx's materialism lead him to theorize labor as the metabolic process between humanity and the rest of nature. In Promethean interpretations of Marx that Foster critiques, there was an assumption his analysis was very similar to the anthropocentric views critiqued by early environmental sociologists. Instead, Foster argued Marx himself was concerned about the Metabolic rift generated by capitalist society's social metabolism, particularly in industrial agriculture—Marx had identified an "irreparable rift in the interdependent process of social metabolism," created by capitalist agriculture that was destroying the productivity of the land and creating wastes in urban sites that failed to be reintegrated into the land and thus lead toward destruction of urban workers health simultaneously. Reviewing the contribution of this thread of eco-marxism to current environmental sociology, Pellow and Brehm conclude, "The metabolic rift is a productive development in the field because it connects current research to classical theory and links sociology with an interdisciplinary array of scientific literatures focused on ecosystem dynamics."
Foster emphasized that his argument presupposed the "magisterial work" of Paul Burkett, who had developed a closely related "red-green" perspective rooted in a direct examination of Marx's value theory. Burkett and Foster proceeded to write a number of articles together on Marx's ecological conceptions, reflecting their shared perspective
More recently, Jason W. Moore, inspired by Burkett's value-analytical approach to Marx's ecology and arguing that Foster's work did not in itself go far enough, has sought to integrate the notion of metabolic rift with world systems theory, incorporating Marxian value-related conceptions. For Moore, the modern world-system is a capitalist world-ecology, joining the accumulation of capital, the pursuit of power, and the production of nature in dialectical unity. Central to Moore's perspective is a philosophical re-reading of Marx's value theory, through which abstract social labor and abstract social nature are dialectically bound. Moore argues that the emergent law of value, from the sixteenth century, was evident in the extraordinary shift in the scale, scope, and speed of environmental change. What took premodern civilizations centuries to achieve—such as the deforestation of Europe in the medieval era—capitalism realized in mere decades. This world-historical rupture, argues Moore, can be explained through a law of value that regards labor productivity as the decisive metric of wealth and power in the modern world. From this standpoint, the genius of capitalist development has been to appropriate uncommodified natures—including uncommodified human natures—as a means of advancing labor productivity in the commodity system.
Societal-environmental dialectic
In 1975, the highly influential work of Allan Schnaiberg transfigured environmental sociology, proposing a societal-environmental dialectic, though within the 'neo-Marxist' framework of the relative autonomy of the state as well. This conflictual concept has overwhelming political salience. First, the economic synthesis states that the desire for economic expansion will prevail over ecological concerns. Policy will decide to maximize immediate economic growth at the expense of environmental disruption. Secondly, the managed scarcity synthesis concludes that governments will attempt to control only the most dire of environmental problems to prevent health and economic disasters. This will give the appearance that governments act more environmentally consciously than they really do. Third, the ecological synthesis generates a hypothetical case where environmental degradation is so severe that political forces would respond with sustainable policies. The driving factor would be economic damage caused by environmental degradation. The economic engine would be based on renewable resources at this point. Production and consumption methods would adhere to sustainability regulations.
These conflict-based syntheses have several potential outcomes. One is that the most powerful economic and political forces will preserve the status quo and bolster their dominance. Historically, this is the most common occurrence. Another potential outcome is for contending powerful parties to fall into a stalemate. Lastly, tumultuous social events may result that redistribute economic and political resources.
In 1980, the highly influential work of Allan Schnaiberg entitled The Environment: From Surplus to Scarcity (1980)
was a large contribution to this theme of a societal-environmental dialectic.
Ecological modernization and reflexive modernization
By the 1980s, a critique of eco-Marxism was in the offing, given empirical data from countries (mostly in Western Europe like the Netherlands, Western Germany and somewhat the United Kingdom) that were attempting to wed environmental protection with economic growth instead of seeing them as separate. This was done through both state and capital restructuring. Major proponents of this school of research are Arthur P.J. Mol and Gert Spaargaren. Popular examples of ecological modernization would be "cradle to cradle" production cycles, industrial ecology, large-scale organic agriculture, biomimicry, permaculture, agroecology and certain strands of sustainable development—all implying that economic growth is possible if that growth is well organized with the environment in mind.
Reflexive modernization
The many volumes of the German sociologist Ulrich Beck first argued from the late 1980s that our risk society is potentially being transformed by the environmental social movements of the world into structural change without rejecting the benefits of modernization and industrialization. This is leading to a form of 'reflexive modernization' with a world of reduced risk and better modernization process in economics, politics, and scientific practices as they are made less beholden to a cycle of protecting risk from correction (which he calls our state's organized irresponsibility)—politics creates ecodisasters, then claims responsibility in an accident, yet nothing remains corrected because it challenges the very structure of the operation of the economy and the private dominance of development, for example. Beck's idea of a reflexive modernization looks forward to how our ecological and social crises in the late 20th century are leading toward transformations of the whole political and economic system's institutions, making them more "rational" with ecology in mind.
Neo-Liberalism
Neo-liberalism includes deregulation, free market capitalism, and aims at reducing government spending. These Neo-liberal policies greatly affect environmental sociology. Since Neo-liberalism includes deregulation and essentially less government involvement, this leads to the commodification and privatization of unowned, state-owned, or common property resources. Diana Liverman and Silvina Vilas mentions that this results in payments for environmental services; deregulation and cuts in public expenditure for environmental management; the opening up of trade and investment; and transfer of environmental management to local or nongovernmental institutions. The privatization of these resources have impacts on society, the economy, and to the environment. An example that has greatly affected society is the privatization of water.
Social construction of the environment
Additionally in the 1980s, with the rise of postmodernism in the western academy and the appreciation of discourse as a form of power, some sociologists turned to analyzing environmental claims as a form of social construction more than a 'material' requirement. Proponents of this school include John A. Hannigan, particularly in Environmental Sociology: A Social Constructionist Perspective (1995). Hannigan argues for a 'soft constructionism' (environmental problems are materially real though they require social construction to be noticed) over a 'hard constructionism' (the claim that environmental problems are entirely social constructs).
Although there was sometimes acrimonious debate between the constructivist and realist "camps" within environmental sociology in the 1990s, the two sides have found considerable common ground as both increasingly accept that while most environmental problems have a material reality they nonetheless become known only via human processes such as scientific knowledge, activists' efforts, and media attention. In other words, most environmental problems have a real ontological status despite our knowledge/awareness of them stemming from social processes, processes by which various conditions are constructed as problems by scientists, activists, media and other social actors. Correspondingly, environmental problems must all be understood via social processes, despite any material basis they may have external to humans. This interactiveness is now broadly accepted, but many aspects of the debate continue in contemporary research in the field.
Events
Modern environmentalism
United States
The 1960s built strong cultural momentum for environmental causes, giving birth to the modern environmental movement and large questioning in sociologists interested in analyzing the movement. Widespread green consciousness moved vertically within society, resulting in a series of policy changes across many states in the U.S. and Europe in the 1970s. In the United States, this period was known as the "Environmental Decade" with the creation of the United States Environmental Protection Agency and passing of the Endangered Species Act, Clean Water Act, and amendments to the Clean Air Act. Earth Day of 1970, celebrated by millions of participants, represented the modern age of environmental thought. The environmental movement continued with incidences such as Love Canal.
Historical studies
While the current mode of thought expressed in environmental sociology was not prevalent until the 1970s, its application is now used in analysis of ancient peoples. Societies including Easter Island, the Anaszi, and the Mayans were argued to have ended abruptly, largely due to poor environmental management. This has been challenged in later work however as the exclusive cause (biologically trained Jared Diamond's Collapse (2005); or more modern work on Easter Island). The collapse of the Mayans sent a historic message that even advanced cultures are vulnerable to ecological suicide—though Diamond argues now it was less of a suicide than an environmental climate change that led to a lack of an ability to adapt—and a lack of elite willingness to adapt even when faced with the signs much earlier of nearing ecological problems. At the same time, societal successes for Diamond included New Guinea and Tikopia island whose inhabitants have lived sustainably for 46,000 years.
John Dryzek et al. argue in Green States and Social Movements: Environmentalism in the United States, United Kingdom, Germany, and Norway (2003) that there may be a common global green environmental social movement, though its specific outcomes are nationalist, falling into four 'ideal types' of interaction between environmental movements and state power. They use as their case studies environmental social movements and state interaction from Norway, the United Kingdom, the United States, and Germany. They analyze the past 30 years of environmentalism and the different outcomes that the green movement has taken in different state contexts and cultures.
Recently and roughly in temporal order below, much longer-term comparative historical studies of environmental degradation are found by sociologists. There are two general trends: many employ world systems theory—analyzing environmental issues over long periods of time and space; and others employ comparative historical methods. Some utilize both methods simultaneously, sometimes without reference to world systems theory (like Whitaker, see below).
Stephen G. Bunker (d. 2005) and Paul S. Ciccantell collaborated on two books from a world-systems theory view, following commodity chains through history of the modern world system, charting the changing importance of space, time, and scale of extraction and how these variables influenced the shape and location of the main nodes of the world economy over the past 500 years. Their view of the world was grounded in extraction economies and the politics of different states that seek to dominate the world's resources and each other through gaining hegemonic control of major resources or restructuring global flows in them to benefit their locations.
The three volume work of environmental world-systems theory by Sing C. Chew analyzed how "Nature and Culture" interact over long periods of time, starting with World Ecological Degradation (2001) In later books, Chew argued that there were three "Dark Ages" in world environmental history characterized by periods of state collapse and reorientation in the world economy associated with more localist frameworks of community, economy, and identity coming to dominate the nature/culture relationships after state-facilitated environmental destruction delegitimized other forms. Thus recreated communities were founded in these so-called 'Dark Ages,' novel religions were popularized, and perhaps most importantly to him the environment had several centuries to recover from previous destruction. Chew argues that modern green politics and bioregionalism is the start of a similar movement of the present day potentially leading to wholesale system transformation. Therefore, we may be on the edge of yet another global "dark age" which is bright instead of dark on many levels since he argues for human community returning with environmental healing as empires collapse.
More case oriented studies were conducted by historical environmental sociologist Mark D. Whitaker analyzing China, Japan, and Europe over 2,500 years in his book Ecological Revolution (2009). He argued that instead of environmental movements being "New Social Movements" peculiar to current societies, environmental movements are very old—being expressed via religious movements in the past (or in the present like in ecotheology) that begin to focus on material concerns of health, local ecology, and economic protest against state policy and its extractions. He argues past or present is very similar: that we have participated with a tragic common civilizational process of environmental degradation, economic consolidation, and lack of political representation for many millennia which has predictable outcomes. He argues that a form of bioregionalism, the bioregional state, is required to deal with political corruption in present or in past societies connected to environmental degradation.
After looking at the world history of environmental degradation from very different methods, both sociologists Sing Chew and Mark D. Whitaker came to similar conclusions and are proponents of (different forms of) bioregionalism.
Related journals
Among the key journals in this field are:
Environmental Sociology
Human Ecology
Human Ecology Review
Nature and Culture
Organization & Environment
Population and Environment
Rural Sociology
Society and Natural Resources
See also
Bibliography of sociology
Ecological anthropology
Ecological design
Ecological economics
Ecological modernization theory
Enactivism
Environmental design
Environmental design and planning
Environmental economics
Environmental policy
Environmental racism
Environmental racism in Europe
Environmental social science
Ethnoecology
Political ecology
Sociology of architecture
Sociology of disaster
Climate change
References
Notes
Dunlap, Riley E., Frederick H. Buttel, Peter Dickens, and August Gijswijt (eds.) 2002. Sociological Theory and the Environment: Classical Foundations, Contemporary Insights (Rowman & Littlefield, ).
Dunlap, Riley E., and William Michelson (eds.) 2002.Handbook of Environmental Sociology (Greenwood Press, )
Freudenburg, William R., and Robert Gramling. 1989. "The Emergence of Environmental Sociology: Contributions of Riley E. Dunlap and William R. Catton, Jr.", Sociological Inquiry 59(4): 439–452
Harper, Charles. 2004. Environment and Society: Human Perspectives on Environmental Issues. Upper Saddle River, New Jersey: Pearson Education, Inc.
Humphrey, Craig R., and Frederick H. Buttel. 1982.Environment, Energy, and Society. Belmont, California: Wadsworth Publishing Company.
Humphrey, Craig R., Tammy L. Lewis and Frederick H. Buttel. 2002. Environment, Energy and Society: A New Synthesis. Belmont, California: Wadsworth/Thompson Learning.
Mehta, Michael, and Eric Ouellet. 1995. Environmental Sociology: Theory and Practice, Toronto: Captus Press.
Redclift, Michael, and Graham Woodgate, eds. 1997.International Handbook of Environmental Sociology (Edgar Elgar, 1997; )
Schnaiberg, Allan. 1980. The Environment: From Surplus to Scarcity. New York: Oxford University Press.
Further reading
Hannigan, John, "Environmental Sociology", Routledge, 2014.
Zehner, Ozzie, Green Illusions: The Dirty Secrets of Clean Energy and the Future of Environmentalism, University of Nebraska Press, 2012. An environmental sociology text forming a critique of energy production and green consumerism.
External links
ASA Section on Environment and Technology
ESA Environment & Society Research Network
ISA Research Committee on Environment and Society (RC24)
Canadian Sociological Association (CSA) Environment Research Cluster
|
Bombus rufocinctus is a species of bumblebee known commonly as the "red-belted bumblebee." It is native to North America where it has a wide distribution across Canada and the western, midwestern, and northeastern United States. It may occur in Mexico.
The queen is 1.6 to 1.8 centimeters long and just under a centimeter wide at the abdomen. It is black with scattered gray and yellowish hairs on the head. The abdomen has many bright yellow hairs and areas of reddish hairs. The worker is 1.1 to 1.2 centimeters long and half a centimeter wide at the abdomen. It is similar to the queen but it may have longer hairs. The male is 1.2 to 1.3 centimeters long and half a centimeter wide at the abdomen. It is mostly black with more yellow on the head and abdomen. This species displays four genetically controlled color polymorphisms: the second and third abdominal terga may have red or black hairs, and the fourth and fifth may be either yellow or black.
This small, short-tongued bee lives in and around wooded areas and it can be found in urban parks and gardens. It feeds on several kinds of plants, including chicories, snakeroots, strawberries, gumweeds, sunflowers, goldenrods, clovers, vetches, and goldeneyes. It usually nests on or above ground level.
References
External links
Bombus rufocinctus. E-Fauna BC: Electronic Atlas of the Fauna of British Columbia. University of British Columbia, Vancouver. Accessed 10 March 2016.
Bumblebees
Hymenoptera of North America
Insects described in 1863
|
42nd Avenue station could refer to:
42nd Avenue station (TriMet)
42nd Avenue station (Muni Metro)
|
The list of shipwrecks in January 1875 includes ships sunk, foundered, grounded, or otherwise lost during January 1875.
1 January
2 January
3 January
4 January
5 January
6 January
7 January
8 January
9 January
10 January
11 January
12 January
13 January
14 January
15 January
16 January
17 January
18 January
19 January
20 January
21 January
22 January
23 January
24 January
25 January
26 January
27 January
28 January
29 January
30 January
31 January
Unknown date
References
1875-01
Maritime incidents in January 1875
|
Events from the year 1562 in France
Incumbents
Monarch – Charles IX
Events
January – Edict of Saint-Germain
1 March – Massacre of Vassy
22 September – Treaty of Hampton Court
28 September to 26 October – Siege of Rouen
19 December – Battle of Dreux
Births
19 August – Charles II de Bourbon-Vendôme, Cardinal (died 1594)
10 December – Roger de Saint-Lary de Termes, duke (died 1646)
Full date missing
Charles de Gontaut, duc de Biron, soldier (died 1602)
Deaths
13 October – Claudin de Sermisy, composer (born c.1490)
31 October – Augustin Marlorat. Protestant reformer (born 1506)
19 December – Jacques Dalbon, Seigneur de Saint Andre, soldier (born c.1505)
Full date missing
Omer Talon, humanist (born c.1510)
See also
References
1560s in France
|
```shell
load 'libs/bats-support/load'
load 'libs/bats-assert/load'
assert_exists() {
assert [ -e "$1" ]
}
refute_exists() {
assert [ ! -e "$1" ]
}
assert_contains() {
local item
for item in "${@:2}"; do
if [[ "$item" == "$1" ]]; then
return 0
fi
done
batslib_print_kv_single_or_multi 8 \
'expected' "$1" \
'actual' "$(echo ${@:2})" \
| batslib_decorate 'item was not found in the array' \
| fail
}
setupNotesEnv() {
export NOTES_DIRECTORY="$(mktemp -d)"
export NOTES_HOME="$(mktemp -d)"
export HOME=$NOTES_HOME
}
teardownNotesEnv() {
if [ $BATS_TEST_COMPLETED ]; then
rm -rf $NOTES_DIRECTORY
rm -rf $NOTES_HOME
else
echo "** Did not delete $NOTES_DIRECTORY, as test failed **"
fi
}
```
|
Proteuxoa gypsina is a moth of the family Noctuidae. It is found in South Australia and Western Australia.
External links
Australian Faunal Directory
Proteuxoa
Moths of Australia
Moths described in 1897
|
```java
/*
* one or more contributor license agreements. See the NOTICE file distributed
* with this work for additional information regarding copyright ownership.
*/
package io.camunda.zeebe.restore;
import io.camunda.application.MainSupport;
import io.camunda.application.Profile;
import io.camunda.application.commons.configuration.BrokerBasedConfiguration;
import io.camunda.application.commons.configuration.WorkingDirectoryConfiguration;
import io.camunda.zeebe.backup.api.BackupStore;
import io.camunda.zeebe.broker.system.configuration.BrokerCfg;
import org.slf4j.Logger;
import org.slf4j.LoggerFactory;
import org.springframework.beans.factory.annotation.Autowired;
import org.springframework.beans.factory.annotation.Value;
import org.springframework.boot.ApplicationArguments;
import org.springframework.boot.ApplicationRunner;
import org.springframework.boot.WebApplicationType;
import org.springframework.boot.autoconfigure.SpringBootApplication;
import org.springframework.boot.context.properties.ConfigurationPropertiesScan;
import org.springframework.context.annotation.Import;
@SpringBootApplication(scanBasePackages = {"io.camunda.zeebe.restore"})
@ConfigurationPropertiesScan(basePackages = {"io.camunda.zeebe.restore"})
@Import(value = {BrokerBasedConfiguration.class, WorkingDirectoryConfiguration.class})
public class RestoreApp implements ApplicationRunner {
private static final Logger LOG = LoggerFactory.getLogger(RestoreApp.class);
private final BrokerCfg configuration;
private final BackupStore backupStore;
@Value("${backupId}")
// Parsed from commandline Eg:-`--backupId=100`
private long backupId;
private final RestoreConfiguration restoreConfiguration;
@Autowired
public RestoreApp(
final BrokerBasedConfiguration configuration,
final BackupStore backupStore,
final RestoreConfiguration restoreConfiguration) {
this.configuration = configuration.config();
this.backupStore = backupStore;
this.restoreConfiguration = restoreConfiguration;
}
public static void main(final String[] args) {
MainSupport.setDefaultGlobalConfiguration();
final var application =
MainSupport.createDefaultApplicationBuilder()
.web(WebApplicationType.NONE)
.sources(RestoreApp.class)
.profiles(Profile.RESTORE.getId())
.build();
application.run(args);
}
@Override
public void run(final ApplicationArguments args) {
LOG.info("Starting to restore from backup {}", backupId);
new RestoreManager(configuration, backupStore)
.restore(backupId, restoreConfiguration.validateConfig())
.join();
LOG.info("Successfully restored broker from backup {}", backupId);
}
}
```
|
```go
/*
path_to_url
Unless required by applicable law or agreed to in writing, software
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
*/
// +k8s:deepcopy-gen=package
// +k8s:protobuf-gen=package
// +k8s:openapi-gen=true
package v2beta2 // import "k8s.io/api/autoscaling/v2beta2"
```
|
Mandiru (, also Romanized as Māndīrū; also known as Mandevīr) is a village in Polan Rural District, Polan District, Chabahar County, Sistan and Baluchestan Province, Iran. At the 2006 census, its population was 727, in 149 families.
References
Populated places in Chabahar County
|
Chris Geile (born April 14, 1964) is a retired United States professional American football offensive lineman who played 1 season in the National Football League with the Detroit Lions in 1987. He played college football for Eastern Illinois University.
References
1964 births
Living people
American football offensive linemen
Eastern Illinois Panthers football players
Detroit Lions players
Sportspeople from Pleasanton, California
Players of American football from Alameda County, California
Amador Valley High School alumni
Players of American football from Anaheim, California
|
Anu Irmeli Palevaara (born 14 August 1971 in Helsinki) is a Finnish actress, choreographer and dancer. She is best known for her role as Jenni Vainio in the Finnish soap opera Salatut elämät which airs on MTV3. Palevaara has been with the series from the beginning, but in year 2001 she had a child and left for maternity leave. Palevaara's pregnancy was written in the series so that her character Jenni had a child. Palevaara returned to the series after her maternity leave. Palevaara's character Jenni was killed off in 2013.
Anu Palevaara studied dance, drama and singing in the Laine Theatre Arts - music theater school in England 1990–1994. Palevaara has made choreographies for the municipal theatre of Lahti and to Hot Club Company, to name a few. She also starred as the leading woman in the successful Finnish film Kuningasjätkä (1998) directed by Markku Pölönen as well as in the TV series Iskelmäprinssi. In 1998, she hosted Tangomarkkinat with Heikki Hietamies.
Filmography
References
20th-century Finnish actresses
Finnish choreographers
Finnish women choreographers
1971 births
Living people
Actresses from Helsinki
21st-century Finnish actresses
Finnish film actresses
Finnish television actresses
Finnish soap opera actresses
|
Leon Eric Brooks III, better known by his stage name Kix Brooks (born May 12, 1955), is an American country music artist, actor, and film producer best known for being one half of the duo Brooks & Dunn and host of radio's American Country Countdown. Prior to the duo's foundation, he was a singer and songwriter, charting twice on Hot Country Songs and releasing an album for Capitol Records. Brooks and Ronnie Dunn comprised Brooks & Dunn for twenty years, then both members began solo careers. Brooks’ solo career after Brooks & Dunn includes the album New to This Town.
In 2019, Brooks was inducted into the Country Music Hall of Fame as a member of Brooks & Dunn.
Early life
Brooks grew up in Shreveport, Louisiana. He has a sister, a half-sister, and a half-brother; his father also adopted a son of his third wife. After graduating from the former Sewanee Military Academy, an Episcopal school in Sewanee, Tennessee, Brooks attended Louisiana Tech University in Ruston as a theatre arts major. He moved to Alaska to work with his father on an oil pipeline for one summer, then returned to Louisiana Tech to finish his education. After graduating, he moved to Maine to write advertising for a company owned by his sister and brother-in-law.
Musical career
Brooks' father urged him to pursue his desire to become a musician, and he moved to Nashville, Tennessee, in the early 1980s. His then-girlfriend (now wife Barbara, with whom he has a son and daughter) followed shortly thereafter. He worked for Tree Publishing as a staff songwriter. He recorded his first solo single, "Baby, When Your Heart Breaks Down", for Avion in 1983, but returned to songwriting after it only reached number 73 on the Hot Country Songs chart. Brooks and Dan Tyler co-wrote "Modern Day Romance", released by Nitty Gritty Dirt Band in June 1985; it became the band's second No. 1 hit on the country chart.
Brooks released an album, Kix Brooks, in 1989 on Capitol Records. This album also featured the song "Sacred Ground" which became a No. 2 country hit for McBride & the Ride in 1992.
He was one half of country music duo Brooks & Dunn. Their 1991 debut album, Brand New Man, generated four number-one hit singles on the country charts. Brooks usually provided backing vocals on their songs and singles. The singles featuring Brooks on lead vocals include, "You're Gonna Miss Me When I'm Gone" (the only Brooks & Dunn single featuring Brooks on lead vocals to reach No. 1), "Lost and Found", "Rock My World (Little Country Girl)", "Mama Don't Get Dressed Up for Nothing", "South of Santa Fe", and "Why Would I Say Goodbye".
On August 10, 2009, Brooks & Dunn announced to their fans, via their website they intended to disband after twenty years of touring. According to the short statement released on their web site, Brooks & Dunn intended to release a greatest hits album, tour during the rest of 2009, and have a farewell tour in 2010.
Brooks resumed his solo career in 2012, releasing a new 12-track album on September 11, 2012. New to This Town features nine songs co-written by Brooks, including the album's first single, the title track. He followed his second album with the soundtrack to the western film Ambush at Dark Canyon in 2014. Brooks composed the majority of the musical score as well as starring in the film.
On December 3, 2014, Brooks & Dunn reunited, and along with Reba McEntire, performed a series of concerts in Las Vegas, Nevada, throughout the summer and fall of 2015.
Brooks performed at the 2019 Musicians Hall of Fame and Museum Concert and Induction Ceremony.
Awards
In 2005, Brooks, along with timber industrialist Roy O. Martin Jr., and the Louisiana State University sports legends Paul Dietzel, and Sue Gunter were among those named a "Louisiana Legend" by Louisiana Public Broadcasting.
Other achievements
Since January 2006, Brooks has hosted American Country Countdown, a syndicated radio countdown show based on Mediabase (originally was BILLBOARD, from 2006 to August 2009), country charts. Brooks succeeded the show's former host, Bob Kingsley. Brooks is also co-owner of Arrington Vineyards, a Nashville winery with winemaker Kip Summers and businessmen John Russell.
In 2013, Kix launched the film company Team Two Entertainment along with Eric Brooks. The company makes independent films Kix produces, and Kix occasionally appears as an actor.
In 2015, Brooks contracted with Cooking Channel to host Steak Out with Kix Brooks, in which he travels around America in search of the best steakhouses.
Discography
Albums
Singles
As a featured artist
Music videos
Filmography
Film
Television
Notes
References
Louisiana Tech University alumni
American country singer-songwriters
American male singer-songwriters
American radio personalities
Grammy Award winners
American mandolinists
Louisiana Republicans
Tennessee Republicans
Musicians from Shreveport, Louisiana
1955 births
Living people
Brooks & Dunn members
Country musicians from Louisiana
Capitol Records artists
Arista Nashville artists
Actors from Shreveport, Louisiana
Singer-songwriters from Louisiana
|
```yaml
id: hashicorp_test
version: -1
name: hashicorp_test
starttaskid: '0'
tasks:
'0':
id: '0'
taskid: e26c1a8a-a9f2-4b21-886d-39eb298181c9
type: start
task:
id: e26c1a8a-a9f2-4b21-886d-39eb298181c9
version: -1
name: ''
iscommand: false
brand: ''
description: ''
nexttasks:
'#none#':
- '1'
separatecontext: false
view: "{\n \"position\": {\n \"x\": 50,\n \"y\": 50\n }\n}"
note: false
timertriggers: []
ignoreworker: false
'1':
id: '1'
taskid: d8caa391-a351-42c5-8cbc-db60e34113bb
type: regular
task:
id: d8caa391-a351-42c5-8cbc-db60e34113bb
version: -1
name: Delete Context
description: Delete field from context
scriptName: DeleteContext
type: regular
iscommand: false
brand: ''
nexttasks:
'#none#':
- '2'
scriptarguments:
all:
simple: yes
index: {}
key: {}
keysToKeep: {}
subplaybook: {}
separatecontext: false
view: "{\n \"position\": {\n \"x\": 50,\n \"y\": 195\n }\n}"
note: false
timertriggers: []
ignoreworker: false
'2':
id: '2'
taskid: 33e66e93-8eee-4493-8572-d4ec6f0d9f7b
type: regular
task:
id: 33e66e93-8eee-4493-8572-d4ec6f0d9f7b
version: -1
name: hashicorp-list-secrets-engines
description: List all secrets engines that exist in HashiCorp Vault
script: HashiCorp Vault|||hashicorp-list-secrets-engines
type: regular
iscommand: true
brand: HashiCorp Vault
nexttasks:
'#none#':
- '3'
separatecontext: false
view: "{\n \"position\": {\n \"x\": 50,\n \"y\": 370\n }\n}"
note: false
timertriggers: []
ignoreworker: false
'3':
id: '3'
taskid: 30242859-98e0-4219-86cc-5471f3187e1e
type: regular
task:
id: 30242859-98e0-4219-86cc-5471f3187e1e
version: -1
name: hashicorp-list-secrets
description: List secrets (names) for a specified KV engine
script: HashiCorp Vault|||hashicorp-list-secrets
type: regular
iscommand: true
brand: HashiCorp Vault
nexttasks:
'#none#':
- '4'
scriptarguments:
engine:
complex:
root: HashiCorp
accessor: Engine
transformers:
- operator: WhereFieldEquals
args:
equalTo:
value:
simple: secret/
field:
value:
simple: Path
getField:
value:
simple: Path
version:
simple: '2'
separatecontext: false
view: "{\n \"position\": {\n \"x\": 50,\n \"y\": 545\n }\n}"
note: false
timertriggers: []
ignoreworker: false
'4':
id: '4'
taskid: 83416e0a-4e8d-44d1-8536-ad006381a31a
type: regular
task:
id: 83416e0a-4e8d-44d1-8536-ad006381a31a
version: -1
name: hashicorp-get-secret-metadata
description: Returns information about a specified secret in a specified KV
V2 engine
script: HashiCorp Vault|||hashicorp-get-secret-metadata
type: regular
iscommand: true
brand: HashiCorp Vault
nexttasks:
'#none#':
- '5'
scriptarguments:
engine_path:
simple: secret/
secret_path:
complex:
root: HashiCorp
accessor: Secret
transformers:
- operator: WhereFieldEquals
args:
equalTo:
value:
simple: test_secret
field:
value:
simple: Path
getField:
value:
simple: Path
separatecontext: false
view: "{\n \"position\": {\n \"x\": 50,\n \"y\": 720\n }\n}"
note: false
timertriggers: []
ignoreworker: false
'5':
id: '5'
taskid: e277fc28-820e-41c4-8c52-dd815accf363
type: condition
task:
id: e277fc28-820e-41c4-8c52-dd815accf363
version: -1
name: Is deleted
type: condition
iscommand: false
brand: ''
description: ''
nexttasks:
'#default#':
- '7'
yes:
- '6'
separatecontext: false
conditions:
- label: yes
condition:
- - operator: isExists
left:
value:
complex:
root: HashiCorp
accessor: Secret.Version
transformers:
- operator: WhereFieldEquals
args:
equalTo:
value:
simple: '2'
field:
value:
simple: Number
getField:
value:
simple: Deleted
iscontext: true
view: "{\n \"position\": {\n \"x\": 50,\n \"y\": 895\n }\n}"
note: false
timertriggers: []
ignoreworker: false
'6':
id: '6'
taskid: d5dcec3c-588b-46a0-8a4f-01f3a486bbc7
type: regular
task:
id: d5dcec3c-588b-46a0-8a4f-01f3a486bbc7
version: -1
name: hashicorp-undelete-secret
description: Undeletes (restores) a secret on HashiCorp (for KV engine version
2)
script: HashiCorp Vault|||hashicorp-undelete-secret
type: regular
iscommand: true
brand: HashiCorp Vault
nexttasks:
'#none#':
- '7'
scriptarguments:
engine_path:
simple: secret/
secret_path:
simple: test_secret
versions:
simple: '2'
separatecontext: false
view: "{\n \"position\": {\n \"x\": 162.5,\n \"y\": 1070\n }\n}"
note: false
timertriggers: []
ignoreworker: false
'7':
id: '7'
taskid: 3d06fa8a-8b6a-47a6-8ae0-f69e6faef56a
type: regular
task:
id: 3d06fa8a-8b6a-47a6-8ae0-f69e6faef56a
version: -1
name: hashicorp-delete-secret
description: Deletes the data under a specified secret given the secret path.
Performs a soft delete that allows you to run the hashicorp-undelete-secret
command if necessary (for KV engine version 2)
script: HashiCorp Vault|||hashicorp-delete-secret
type: regular
iscommand: true
brand: HashiCorp Vault
nexttasks:
'#none#':
- '8'
scriptarguments:
engine_path:
simple: secret/
secret_path:
simple: test_secret
versions:
simple: '2'
separatecontext: false
view: "{\n \"position\": {\n \"x\": 50,\n \"y\": 1245\n }\n}"
note: false
timertriggers: []
ignoreworker: false
'8':
id: '8'
taskid: 82abb548-deed-4dec-8b35-5335cf1c81d6
type: regular
task:
id: 82abb548-deed-4dec-8b35-5335cf1c81d6
version: -1
name: hashicorp-undelete-secret
description: Undeletes (restores) a secret on HashiCorp (for KV engine version
2)
script: HashiCorp Vault|||hashicorp-undelete-secret
type: regular
iscommand: true
brand: HashiCorp Vault
nexttasks:
'#none#':
- '9'
scriptarguments:
engine_path:
simple: secret/
secret_path:
simple: test_secret
versions:
simple: '2'
separatecontext: false
view: "{\n \"position\": {\n \"x\": 50,\n \"y\": 1420\n }\n}"
note: false
timertriggers: []
ignoreworker: false
'9':
id: '9'
taskid: 18c3323d-44c0-4ed6-8cb0-356bbecdc49e
type: regular
task:
id: 18c3323d-44c0-4ed6-8cb0-356bbecdc49e
version: -1
name: hashicorp-destroy-secret
description: Permanently deletes a secret (for KV engine version 2)
script: HashiCorp Vault|||hashicorp-destroy-secret
type: regular
iscommand: true
brand: HashiCorp Vault
nexttasks:
'#none#':
- '16'
scriptarguments:
engine_path:
simple: secret/
secret_path:
simple: test_secret
versions:
simple: '1'
separatecontext: false
view: "{\n \"position\": {\n \"x\": 50,\n \"y\": 1595\n }\n}"
note: false
timertriggers: []
ignoreworker: false
'10':
id: '10'
taskid: 635b40e6-2966-4764-887a-1c89ccfe9196
type: regular
task:
id: 635b40e6-2966-4764-887a-1c89ccfe9196
version: -1
name: hashicorp-enable-engine
description: Enables a new secrets engine at the specified path
script: HashiCorp Vault|||hashicorp-enable-engine
type: regular
iscommand: true
brand: HashiCorp Vault
nexttasks:
'#none#':
- '11'
scriptarguments:
audit_non_hmac_request_keys: {}
audit_non_hmac_response_keys: {}
default_lease_ttl: {}
description: {}
force_no_cache: {}
kv_version: {}
listing_visibility: {}
local: {}
max_lease_ttl: {}
passthrough_request_headers: {}
path:
simple: 'test_${TimeNowUnix} '
seal_wrap: {}
type:
simple: kv
separatecontext: false
view: "{\n \"position\": {\n \"x\": 50,\n \"y\": 1945\n }\n}"
note: false
timertriggers: []
ignoreworker: false
'11':
id: '11'
taskid: fda2ed0d-6b78-4065-86a2-baa0f15ce8bd
type: regular
task:
id: fda2ed0d-6b78-4065-86a2-baa0f15ce8bd
version: -1
name: hashicorp-disable-engine
description: When a secrets engine is no longer needed, it can be disabled. All
secrets under the engine are revoked and the corresponding vault data and
configurations are removed.
script: HashiCorp Vault|||hashicorp-disable-engine
type: regular
iscommand: true
brand: HashiCorp Vault
nexttasks:
'#none#':
- '12'
scriptarguments:
path:
simple: test_${TimeNowUnix} /
separatecontext: false
view: "{\n \"position\": {\n \"x\": 50,\n \"y\": 2120\n }\n}"
note: false
timertriggers: []
ignoreworker: false
'12':
id: '12'
taskid: 0656f23f-ff62-4ea4-8512-954739fb5228
type: regular
task:
id: 0656f23f-ff62-4ea4-8512-954739fb5228
version: -1
name: hashicorp-list-policies
description: List all configured policies
script: HashiCorp Vault|||hashicorp-list-policies
type: regular
iscommand: true
brand: HashiCorp Vault
nexttasks:
'#none#':
- '13'
separatecontext: false
view: "{\n \"position\": {\n \"x\": 50,\n \"y\": 2295\n }\n}"
note: false
timertriggers: []
ignoreworker: false
'13':
id: '13'
taskid: 756429e7-ab70-495a-8798-a36e2c94e0bb
type: regular
task:
id: 756429e7-ab70-495a-8798-a36e2c94e0bb
version: -1
name: hashicorp-get-policy
description: Get information for a policy
script: '|||hashicorp-get-policy'
type: regular
iscommand: true
brand: ''
nexttasks:
'#none#':
- '14'
scriptarguments:
name:
complex:
root: HashiCorp
accessor: Policy
transformers:
- operator: WhereFieldEquals
args:
equalTo:
value:
simple: default
field:
value:
simple: Name
getField:
value:
simple: Name
separatecontext: false
view: "{\n \"position\": {\n \"x\": 50,\n \"y\": 2470\n }\n}"
note: false
timertriggers: []
ignoreworker: false
'14':
id: '14'
taskid: d6906fce-6b76-4bb9-871c-889f986f18a3
type: regular
task:
id: d6906fce-6b76-4bb9-871c-889f986f18a3
version: -1
name: hashicorp-create-token
description: Creates a new authentication token
script: HashiCorp Vault|||hashicorp-create-token
type: regular
iscommand: true
brand: HashiCorp Vault
nexttasks:
'#none#':
- '15'
scriptarguments:
display_name:
simple: test
explicit_max_ttl: {}
meta: {}
no_default_policy: {}
no_parent: {}
num_uses: {}
period: {}
policies:
simple: ${HashiCorp.Policy.Name}
renewable: {}
role_name:
simple: test
ttl:
simple: 10m
separatecontext: false
view: "{\n \"position\": {\n \"x\": 50,\n \"y\": 2645\n }\n}"
note: false
timertriggers: []
ignoreworker: false
'15':
id: '15'
taskid: adf833e9-c1e1-41c8-8632-fb5f93610e56
type: regular
task:
id: adf833e9-c1e1-41c8-8632-fb5f93610e56
version: -1
name: hashicorp-configure-engine
description: Configure a secrets engine to fetch secrets from
script: HashiCorp Vault|||hashicorp-configure-engine
type: regular
iscommand: true
brand: HashiCorp Vault
nexttasks:
'#none#':
- '17'
scriptarguments:
path:
simple: secret/
type:
simple: kv
version:
simple: '2'
separatecontext: false
view: "{\n \"position\": {\n \"x\": 50,\n \"y\": 2820\n }\n}"
note: false
timertriggers: []
ignoreworker: false
'16':
id: '16'
taskid: 458e042c-19bb-45c8-8cf3-a35ef0eea37f
type: regular
task:
id: 458e042c-19bb-45c8-8cf3-a35ef0eea37f
version: -1
name: GetTime
description: "Retrieves the current date and time.\n"
scriptName: GetTime
type: regular
iscommand: false
brand: ''
nexttasks:
'#none#':
- '10'
scriptarguments:
contextKey: {}
date: {}
dateFormat: {}
hoursAgo: {}
minutesAgo: {}
monthsAgo: {}
separatecontext: false
view: "{\n \"position\": {\n \"x\": 50,\n \"y\": 1770\n }\n}"
note: false
timertriggers: []
ignoreworker: false
'17':
id: '17'
taskid: caa0912b-aef8-4d5a-8c90-0189955ea97f
type: regular
task:
id: caa0912b-aef8-4d5a-8c90-0189955ea97f
version: -1
name: hashicorp-reset-configuration
description: Reset the engines configuration
script: HashiCorp Vault|||hashicorp-reset-configuration
type: regular
iscommand: true
brand: HashiCorp Vault
separatecontext: false
view: "{\n \"position\": {\n \"x\": 50,\n \"y\": 2995\n }\n}"
note: false
timertriggers: []
ignoreworker: false
view: "{\n \"linkLabelsPosition\": {},\n \"paper\": {\n \"dimensions\": {\n \
\ \"height\": 3040,\n \"width\": 492.5,\n \"x\": 50,\n \"y\"\
: 50\n }\n }\n}"
inputs: []
outputs: []
fromversion: 5.0.0
description: ''
```
|
```javascript
Async and defer scripts
CSS for when JavaScript is enabled
FileReader.readAsDataURL()
`Window.localStorage`
Drag and Drop API
```
|
Great apes are apes in the family Hominidae.
Great apes may also refer to:
Great Apes (novel), a novel by Will Self
Pongidae, or "great apes", an obsolete taxonomic family
|
```c++
/*your_sha256_hash-------------+
+your_sha256_hash--------------+
(See accompanying file LICENCE.txt or copy at
path_to_url
+your_sha256_hash-------------*/
#define BOOST_TEST_MODULE icl::interval_map unit test
#include <libs/icl/test/disable_test_warnings.hpp>
#include <string>
#include <boost/mpl/list.hpp>
#include "../unit_test_unwarned.hpp"
// interval instance types
#include "../test_type_lists.hpp"
#include "../test_value_maker.hpp"
#include "../test_functions.hpp"
#include <boost/icl/separate_interval_set.hpp>
#include <boost/icl/split_interval_set.hpp>
#include <boost/icl/interval_map.hpp>
#include <boost/icl/split_interval_map.hpp>
using namespace std;
using namespace boost;
using namespace unit_test;
using namespace boost::icl;
// your_sha256_hash-------------
// test_interval_map_shared are tests that should give identical results for all
// interval_maps: interval_map and split_interval_map.
#include "../test_interval_map_shared.hpp"
#define INTERVAL_MAP interval_map
#include "../test_interval_map_cases.hpp"
```
|
```java
/*
*
*
* path_to_url
*
* Unless required by applicable law or agreed to in writing, software
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
*
*/
package com.haulmont.cuba.gui.config;
import com.haulmont.cuba.gui.components.AbstractWindow;
import com.haulmont.cuba.gui.components.compatibility.LegacyFragmentAdapter;
import com.haulmont.cuba.gui.screen.FrameOwner;
import com.haulmont.cuba.gui.screen.Screen;
import com.haulmont.cuba.gui.screen.ScreenFragment;
import com.haulmont.cuba.gui.sys.RouteDefinition;
import org.dom4j.Element;
import javax.annotation.Nonnull;
import javax.annotation.Nullable;
import static com.haulmont.bali.util.Preconditions.checkNotNullArgument;
/**
* Screen's registration information.
*
* @see WindowConfig
*/
public class WindowInfo {
private final String id;
private final WindowAttributesProvider windowAttributesProvider;
private final Element descriptor;
private final String screenClassName;
private final RouteDefinition routeDefinition;
protected WindowInfo(String id, @Nullable WindowAttributesProvider windowAttributesProvider,
@Nullable Element descriptor, @Nullable String screenClassName, RouteDefinition routeDefinition) {
this.id = id;
this.windowAttributesProvider = windowAttributesProvider;
this.descriptor = descriptor;
this.screenClassName = screenClassName;
this.routeDefinition = routeDefinition;
}
public WindowInfo(String id, WindowAttributesProvider windowAttributesProvider, Element descriptor) {
this(id, windowAttributesProvider, descriptor, null);
}
public WindowInfo(String id, WindowAttributesProvider windowAttributesProvider, Element descriptor,
@Nullable RouteDefinition routeDefinition) {
checkNotNullArgument(id);
checkNotNullArgument(descriptor);
this.id = id;
this.windowAttributesProvider = windowAttributesProvider;
this.descriptor = descriptor;
this.screenClassName = null;
this.routeDefinition = routeDefinition;
}
public WindowInfo(String id, WindowAttributesProvider windowAttributesProvider,
String screenClassName, RouteDefinition routeDefinition) {
checkNotNullArgument(id);
checkNotNullArgument(screenClassName);
this.id = id;
this.windowAttributesProvider = windowAttributesProvider;
this.screenClassName = screenClassName;
this.descriptor = null;
this.routeDefinition = routeDefinition;
}
/**
* Screen ID as set in <code>screens.xml</code>
*/
public String getId() {
return id;
}
/**
* @return type of registered window: SCREEN or FRAGMENT
*/
public Type getType() {
return windowAttributesProvider.getType(this);
}
/**
* @return detached window info instance
*/
public WindowInfo resolve() {
return windowAttributesProvider.resolve(this);
}
@Nonnull
public Class<? extends FrameOwner> getControllerClass() {
return windowAttributesProvider.getControllerClass(this);
}
@SuppressWarnings("unchecked")
public Class<? extends Screen> asScreen() {
Class<? extends FrameOwner> controllerClass = getControllerClass();
if (!Screen.class.isAssignableFrom(controllerClass)) {
throw new IllegalStateException("WindowInfo is not Screen - " + this.toString());
}
return (Class<? extends Screen>) controllerClass;
}
@SuppressWarnings("unchecked")
public Class<? extends ScreenFragment> asFragment() {
Class<? extends FrameOwner> controllerClass = getControllerClass();
if (!ScreenFragment.class.isAssignableFrom(controllerClass)) {
throw new IllegalStateException("WindowInfo is not ScreenFragment - " + this.toString());
}
return (Class<? extends ScreenFragment>) controllerClass;
}
/**
* The whole XML element of the screen as set in <code>screens.xml</code>
*/
@Nullable
public Element getDescriptor() {
return descriptor;
}
/**
* Screen class as set in <code>screens.xml</code>
*
* @return screen class name
*/
@Nullable
public String getControllerClassName() {
return screenClassName;
}
/**
* Screen template path as set in <code>screens.xml</code>
*
* @return screen template path
*/
@Nullable
public String getTemplate() {
return windowAttributesProvider.getTemplate(this);
}
/**
* @return route definition configured with {@link com.haulmont.cuba.gui.Route} annotation
*/
public RouteDefinition getRouteDefinition() {
return routeDefinition;
}
@Override
public String toString() {
return "WindowInfo{" +
"id='" + id + '\'' +
(descriptor != null ? ", descriptor=" + descriptor : "") +
(screenClassName != null ? ", screenClass=" + screenClassName : "") +
"}";
}
/**
* Type of registered controller.
*/
public enum Type {
SCREEN,
FRAGMENT
}
}
```
|
George E. Beedle (1864-1927) from Embarrass, Wisconsin was a member of the Wisconsin State Assembly. He died in USA at age 62 in January 1927
Biography
Beedle was born on , in Shawano, Wisconsin.
Career
Beedle was a member of the Assembly from 1903 to 1906. Additionally, he served as a member of the Waupaca County, Wisconsin Board of Supervisors and Insurance Commissioner of Wisconsin. He was a Republican.
References
External links
The Political Graveyard
1864 births
County supervisors in Wisconsin
Republican Party members of the Wisconsin State Assembly
People from Shawano, Wisconsin
People from Waupaca County, Wisconsin
Year of death missing
|
The 2010 Indian Federation Cup Final was the 32nd final of the Indian Federation Cup, the top knock-out competition in India, and was contested between arch-rivals East Bengal and Mohun Bagan on 2 October 2010.
East Bengal won the final 1–0, to successfully retain and claim their seventh Federation Cup title. Reisangmei Vashum scored the solitary goal for the Red and Gold brigade in the 53rd minute from Robin Singh's lay-off pass.
Route to the final
East Bengal
East Bengal entered the 2010 Indian Federation Cup automatically as they were already in the I-League. They were placed in Group A along with Air India, HAL, and Pune FC and their matches were played in Cuttack. The tournament got off to a great start for East Bengal as they defeated Air India in their opening match by 3–1 with Tolgay Ozbey scoring a brace and Robin Singh scoring the third. Bijith Setty scored a consolation goal in the 89th minute for Air India. In the second match, East Bengal came from behind to defeat HAL by 2–1 with Penn Orji and Tolgay Ozbey finding the back of the net in the 13th and 33rd minute respectively after Hamza put HAL ahead in the 9th minute. In the last game of the group stages, East Bengal pipped Pune FC by 1–0 with Penn Orji finding the back of the net once again in the 67th minute as the Red and Gold brigade confirmed the top spot in the group with 3 wins and progressed to the Semi-finals where they would face Churchill Brothers. Tolgay Ozbey's 11th-minute strike was enough for Trevor Morgan's men to reach the final.
Mohun Bagan
Mohun Bagan entered the 2010 Indian Federation Cup automatically as they were already in the I-League. They were placed in Group D along with Mumbai, Salgaocar and Shillong Lajong and their matches were played in Cuttack.The tournament got off to a mix start as well for Bagan as they won against Shillong Lajong 1–0 in their first match with Muritala Ali scoring the winner for Bagan and then drew goalless with Mumbai FC in their second match. In the last game of the group they required a win against Salgaocar to qualify and Bagan thrashed the Goan club by 6–1 with José Ramirez Barreto and Muritala Ali scoring hattricks each. In the semi-finals Mohun Bagan took on Dempo and the game ended 1–1 after 120 minutes. Ranti Martins put Dempo ahead in the 2nd minute while Chidi Edeh scored the equaliser in the 66th minute for Bagan. In the penalty shootout, Sangram Mukherjee saved Ogba Kalu Nnanna's shot as they won 5–3 to reach the finals.
Match
Details
References
1
East Bengal Club matches
Mohun Bagan SG matches
Indian Federation Cup finals
|
```c
/* $OpenBSD: lpf.c,v 1.13 2015/02/09 23:00:14 deraadt Exp $ */
/* $NetBSD: lpf.c,v 1.8 2000/04/29 00:12:32 abs Exp $ */
/*
* The Regents of the University of California. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. Neither the name of the University nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*/
/*
* filter which reads the output of nroff and converts lines
* with ^H's to overwritten lines. Thus this works like 'ul'
* but is much better: it can handle more than 2 overwrites
* and it is written with some style.
*/
#include <signal.h>
#include <stdlib.h>
#include <stdio.h>
#include <string.h>
#include <unistd.h>
#define MAXWIDTH 132
#define MAXREP 10
char buf[MAXREP][MAXWIDTH];
int maxcol[MAXREP] = {-1};
int lineno;
int width = 132; /* default line length */
int length = 66; /* page length */
int indent; /* indentation length */
int npages = 1;
int literal; /* print control characters */
int onlcr; /* map nl->cr-nl */
char *name; /* user's login name */
char *host; /* user's machine name */
char *acctfile; /* accounting information file */
__dead void usage(void);
int
main(int argc, char **argv)
{
FILE *p = stdin, *o = stdout;
int i, col;
char *cp;
int done, linedone, maxrep, ch;
char *limit;
while ((ch = getopt(argc, argv, "crh:i:j:l:n:w:")) != -1) {
switch (ch) {
case 'n':
name = optarg;
break;
case 'h':
host = optarg;
break;
case 'w':
if ((i = atoi(optarg)) > 0 && i <= MAXWIDTH)
width = i;
break;
case 'l':
length = atoi(optarg);
break;
case 'i':
indent = atoi(optarg);
break;
case 'r': /* map nl->cr-nl */
onlcr = 1;
break;
case 'c': /* Print control chars */
literal++;
break;
case 'j': /* ignore job name */
break;
default:
usage();
}
}
argc -= optind;
argv += optind;
if (argc)
acctfile = *argv;
memset(buf, ' ', sizeof(buf));
done = 0;
while (!done) {
col = indent;
maxrep = -1;
linedone = 0;
while (!linedone) {
switch (ch = getc(p)) {
case EOF:
linedone = done = 1;
ch = '\n';
break;
case '\f':
lineno = length;
case '\n':
if (maxrep < 0)
maxrep = 0;
linedone = 1;
break;
case '\b':
if (--col < indent)
col = indent;
break;
case '\r':
col = indent;
break;
case '\t':
col = ((col - indent) | 07) + indent + 1;
break;
case '\031':
/*
* lpd needs to use a different filter to
* print data so stop what we are doing and
* wait for lpd to restart us.
*/
if ((ch = getchar()) == '\1') {
fflush(stdout);
kill(getpid(), SIGSTOP);
break;
} else {
ungetc(ch, stdin);
ch = '\031';
}
default:
if (col >= width || (!literal && ch < ' ')) {
col++;
break;
}
cp = &buf[0][col];
for (i = 0; i < MAXREP; i++) {
if (i > maxrep)
maxrep = i;
if (*cp == ' ') {
*cp = ch;
if (col > maxcol[i])
maxcol[i] = col;
break;
}
cp += MAXWIDTH;
}
col++;
break;
}
}
/* print out lines */
for (i = 0; i <= maxrep; i++) {
for (cp = buf[i], limit = cp+maxcol[i]; cp <= limit;) {
putc(*cp, o);
*cp++ = ' ';
}
if (i < maxrep)
putc('\r', o);
else {
if (onlcr)
putc('\r', o);
putc(ch, o);
}
if (++lineno >= length) {
fflush(o);
npages++;
lineno = 0;
}
maxcol[i] = -1;
}
}
if (lineno) { /* be sure to end on a page boundary */
putchar('\f');
npages++;
}
if (name && acctfile && access(acctfile, 02) >= 0 &&
freopen(acctfile, "a", stdout) != NULL) {
printf("%7.2f\t%s:%s\n", (float)npages, host, name);
}
exit(0);
}
__dead void
usage(void)
{
extern char *__progname;
fprintf(stderr, "usage: %s [-c] [-r] [-h host] [-i indent] [-l length]"
" [-n name] [-w width] [acctfile]\n", __progname);
exit(1);
}
```
|
```java
//your_sha256_hash--------------------------------//
// //
// B o a r d //
// //
//your_sha256_hash--------------------------------//
// <editor-fold defaultstate="collapsed" desc="hdr">
//
//
// This program is free software: you can redistribute it and/or modify it under the terms of the
//
// This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY;
// without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
//
// program. If not, see <path_to_url
//your_sha256_hash--------------------------------//
// </editor-fold>
package org.audiveris.omr.ui;
import org.audiveris.omr.ui.field.LCheckBox;
import org.audiveris.omr.ui.selection.SelectionService;
import org.audiveris.omr.ui.selection.UserEvent;
import org.audiveris.omr.ui.util.Panel;
import org.audiveris.omr.ui.util.UIUtil;
import org.audiveris.omr.util.ClassUtil;
import org.jdesktop.application.Application;
import org.jdesktop.application.ResourceMap;
import org.slf4j.Logger;
import org.slf4j.LoggerFactory;
import org.bushe.swing.event.EventSubscriber;
import com.jgoodies.forms.builder.PanelBuilder;
import com.jgoodies.forms.layout.CellConstraints;
import com.jgoodies.forms.layout.FormLayout;
import java.awt.Component;
import java.util.Comparator;
import javax.swing.JButton;
import javax.swing.JComponent;
import javax.swing.JLabel;
import javax.swing.JPanel;
import javax.swing.JSplitPane;
import javax.swing.JTextField;
import javax.swing.border.TitledBorder;
import javax.swing.text.JTextComponent;
/**
* Class <code>Board</code> defines the common properties of any user board such as
* PixelBoard, SectionBoard, and the like.
* <p>
* Each board has a standard header composed of a title, a horizontal separator and optionally a
* dump button. The board body is handled by the subclass.
* </p>
* <p>
* Any board can be (de)selected in its containing {@link BoardsPane}. This can be done
* programmatically using {@link #setSelected(boolean)} and manually (via a right-click in the
* BoardsPane).
* </p>
* <p>
* Only selected boards can be seen in the BoardsPane display. A selected board can be made
* currently (in)visible programmatically using {@link #setVisible(boolean)}.
* Typically, {@link org.audiveris.omr.check.CheckBoard}'s are visible only when they carry
* glyph information.
* </p>
* <p>
* By default, any board can have a related SelectionService, used for subscribe (input) and publish
* (output). When {@link #connect} is called, the board instance is subscribed to its
* SelectionService for a specific collection of event classes. Similarly, {@link #disconnect}
* unsubscribes the Board instance from the same event classes.
* </p>
* <p>
* This <code>Board</code> class is still an abstract class, since the onEvent() method must be
* provided by every subclass.
* </p>
*
* @author Herv Bitteur
*/
public abstract class Board
implements EventSubscriber<UserEvent>
{
//~ Static fields/initializers your_sha256_hash-
private static final Logger logger = LoggerFactory.getLogger(Board.class);
private static final ResourceMap resources = Application.getInstance().getContext()
.getResourceMap(Board.class);
/** Minimum width available for a board. */
public static final int MIN_BOARD_WIDTH = UIUtil.adjustedSize(350);
// Predefined boards names with preferred display positions
public static final Desc PIXEL = new Desc("Pixel", 100);
public static final Desc BINARIZATION = new Desc("Binarization", 150);
public static final Desc RUN = new Desc("Run", 200);
public static final Desc SECTION = new Desc("Section", 250);
public static final Desc FILAMENT = new Desc("Filament", 300);
public static final Desc SAMPLE = new Desc("Sample", 400);
public static final Desc GLYPH = new Desc("Glyph", 500);
public static final Desc INTER = new Desc("Inter", 550);
public static final Desc TEMPLATE = new Desc("Template", 575);
public static final Desc FOCUS = new Desc("Focus", 600);
public static final Desc SHAPE = new Desc("Shape", 700);
public static final Desc EVAL = new Desc("Eval", 800);
public static final Desc CHECK = new Desc("Check", 900);
/** To sort boards by their position. */
public static final Comparator<Board> byPosition = (Board b1,
Board b2) -> Integer.compare(
b1.position,
b2.position);
//~ Instance fields your_sha256_hash------------
/** The board instance name. */
private final String name;
/** The hosting BoardsPane, if any. */
private BoardsPane parent;
/** The board header. */
private final Header header;
/** The body part of the component. */
private final Panel body = new Panel();
/** The swing component of the board instance. */
private final Panel component = new Panel();
/**
* The event service this board interacts with.
* It can serve different event classes, like a list of entities or an entity ID.
*/
private final SelectionService selectionService;
/** The collection of event classes to be observed. */
private final Class<?>[] eventsRead;
/** The preferred position in BoardsPane sequence. */
private final int position;
/** The split container that will contain the boards pane. */
private JSplitPane splitContainer;
/** Board is selected? (it appears in boards pane). */
private boolean selected;
//~ Constructors your_sha256_hash---------------
/**
* Create a board from a pre-defined descriptor (name + position).
*
* @param desc the board descriptor
* @param selectionService the related selection service for input and output
* @param eventsRead the collection of event classes to observe
* @param selected true to pre-select the board
* @param useCount true for a count field
* @param useVip true for a VIP label and field
* @param useDump true for a dump button
*/
public Board (Desc desc,
SelectionService selectionService,
Class<?>[] eventsRead,
boolean selected,
boolean useCount,
boolean useVip,
boolean useDump)
{
this(
desc.name,
desc.position,
selectionService,
eventsRead,
selected,
useCount,
useVip,
useDump);
}
/**
* Create a board, with (dynamic) name and position.
*
* @param name a name assigned to the board
* @param position the preferred position within BoardsPane display
* @param selectionService the related selection service for input and output
* @param eventsRead the collection of event classes to observe
* @param selected true to pre-select the board
* @param useCount true for a count field
* @param useVip true for a VIP label and field
* @param useDump true for a dump button
*/
public Board (String name,
int position,
SelectionService selectionService,
Class[] eventsRead,
boolean selected,
boolean useCount,
boolean useVip,
boolean useDump)
{
this.name = name;
this.position = position;
this.selectionService = selectionService;
this.eventsRead = eventsRead;
this.selected = selected;
// Layout header and body parts
header = (useCount || useVip || useDump) ? new Header(useCount, useVip, useDump) : null;
if (header != null) {
header.setInsets(0, 0, UIUtil.adjustedSize(3), 0); // TLBR
}
defineLayout();
}
//~ Methods your_sha256_hash--------------------
//---------//
// connect //
//---------//
/**
* Connect to input selections.
*/
public void connect ()
{
logger.debug("connect {}", this);
if (eventsRead != null) {
for (Class<?> eventClass : eventsRead) {
selectionService.subscribeStrongly(eventClass, this);
// Refresh with latest data for this event class
UserEvent event = (UserEvent) selectionService.getLastEvent(eventClass);
if (event != null) {
event.movement = null;
onEvent(event);
}
}
}
// Update action if any
update();
}
//--------------//
// defineLayout //
//--------------//
private void defineLayout ()
{
component.setName(name + " board");
component.setBorder(new TitledBorder(name));
component.setInsets(
UIUtil.adjustedSize(12),
UIUtil.adjustedSize(10),
UIUtil.adjustedSize(5),
UIUtil.adjustedSize(5)); // TLBR sides
body.setNoInsets();
CellConstraints cst = new CellConstraints();
StringBuilder rowsSpec = new StringBuilder();
if (header != null) {
rowsSpec.append("pref,").append(Panel.getFieldInterline()).append(',');
}
rowsSpec.append("pref");
FormLayout layout = new FormLayout("fill:pref:grow", rowsSpec.toString());
PanelBuilder builder = new PanelBuilder(layout, component);
if (header != null) {
builder.add(header, cst.xy(1, 1));
}
builder.add(body, cst.xy(1, (header != null) ? 3 : 1));
}
//------------//
// disconnect //
//------------//
/**
* Disconnect from input selections.
*/
public void disconnect ()
{
logger.debug("disconnect {}", this);
if (eventsRead != null) {
for (Class<?> eventClass : eventsRead) {
selectionService.unsubscribe(eventClass, this);
}
}
}
//---------//
// getBody //
//---------//
/**
* Report the body part of the board.
*
* @return the body
*/
protected JPanel getBody ()
{
return body;
}
//--------------//
// getComponent //
//--------------//
/**
* Report the UI component.
*
* @return the concrete component
*/
public JPanel getComponent ()
{
return component;
}
//---------------//
// getCountField //
//---------------//
protected JLabel getCountField ()
{
if (header == null) {
return null;
}
return header.count;
}
//---------------//
// getDumpButton //
//---------------//
/**
* Report the Dump button of the board, if any.
*
* @return the dump button, or null
*/
protected JButton getDumpButton ()
{
if (header == null) {
return null;
}
return header.dump;
}
//---------//
// getName //
//---------//
/**
* Report the name for this board instance.
*
* @return an instance name
*/
public String getName ()
{
return name;
}
//---------------------//
// getSelectionService //
//---------------------//
/**
* Report the selection service this board is linked to.
*
* @return the selectionService
*/
protected SelectionService getSelectionService ()
{
return selectionService;
}
//-------------------//
// getSplitContainer //
//-------------------//
/**
* Report the JSplitPane that will contain the boards pane.
*
* @return the related split container
*/
public JSplitPane getSplitContainer ()
{
return splitContainer;
}
//-----------//
// getVipBox //
//-----------//
/**
* Get access to the VIP box, if any.
*
* @return the vip label+field
*/
protected LCheckBox getVipBox ()
{
if (header == null) {
return null;
}
return header.vip;
}
//------------//
// isSelected //
//------------//
/**
* Report whether this board is currently selected.
*
* @return true if selected
*/
public boolean isSelected ()
{
return selected;
}
//-------------//
// resizeBoard //
//-------------//
/**
* Resize board component, to adapt to its new composition.
*/
public void resizeBoard ()
{
component.invalidate();
component.validate();
component.repaint();
}
//-----------//
// setParent //
//-----------//
public void setParent (BoardsPane parent)
{
this.parent = parent;
}
//-------------//
// setSelected //
//-------------//
/**
* Select or not this board in its containing BoardsPane.
*
* @param selected true for selected, false for de-selected
*/
public void setSelected (boolean selected)
{
// No modification?
if (selected == this.selected) {
return;
}
if (selected) {
connect();
} else {
disconnect();
}
this.selected = selected;
if (parent != null) {
parent.update();
}
}
//-------------------//
// setSplitContainer //
//-------------------//
/**
* Set the JSplitPane that will contain the boards pane.
*
* @param sp the related split container
*/
public void setSplitContainer (JSplitPane sp)
{
splitContainer = sp;
}
//------------//
// setVisible //
//------------//
/**
* Make this board visible or not.
*
* @param bool true for visible
*/
public void setVisible (boolean bool)
{
component.setVisible(bool);
}
//----------//
// toString //
//----------//
@Override
public String toString ()
{
return "{" + ClassUtil.nameOf(this) + " " + name + "}";
}
//--------//
// update //
//--------//
/**
* Trigger an update of the board.
*/
public void update ()
{
// Void by default
}
//~ Static Methods your_sha256_hash-------------
//-------------//
// emptyFields //
//-------------//
/**
* Convenient method to empty all the text fields of a given JComponent.
*
* @param component the component to "blank".
*/
public static void emptyFields (JComponent component)
{
for (Component comp : component.getComponents()) {
if (comp instanceof JTextField) {
((JTextComponent) comp).setText("");
}
}
}
//~ Inner Classes your_sha256_hash--------------
//------//
// Desc //
//------//
/**
* A way to describe a board kind.
*/
public static class Desc
{
/** Default name for this board. */
public final String name;
/** Preferred position within its containing BoardsPane. */
public final int position;
public Desc (String name,
int position)
{
this.name = name;
this.position = position;
}
}
//--------//
// Header //
//--------//
/**
* The board header provides a line of perhaps count, vip, dump button.
*/
private static class Header
extends Panel
{
/** Output: Count of entities, if any. */
private final JLabel count;
/** Input / Output : VIP flag, if any. */
private final LCheckBox vip;
/** Dump button, if any. */
private final JButton dump;
Header (boolean withCount,
boolean withVip,
boolean withDump)
{
count = withCount ? new JLabel("") : null;
vip = withVip ? new LCheckBox(
resources.getString("vip.text"),
resources.getString("vip.toolTipText")) : null;
dump = withDump ? new JButton("Dump") : null;
defineLayout();
}
private void defineLayout ()
{
CellConstraints cst = new CellConstraints();
StringBuilder sb = new StringBuilder();
// count label
sb.append("15dlu:grow");
// vip label+field
sb.append(",").append(Panel.getFieldInterval()).append(",12dlu,").append(
Panel.getLabelInterval()).append(",10dlu");
// dump button
sb.append(",").append(Panel.getFieldInterval()).append(",35dlu");
FormLayout layout = new FormLayout(sb.toString(), "pref");
PanelBuilder builder = new PanelBuilder(layout, this);
if (dump != null) {
builder.add(dump, cst.xyw(7, 1, 1));
}
if (vip != null) {
builder.add(vip.getLabel(), cst.xy(3, 1));
builder.add(vip.getField(), cst.xy(5, 1));
}
if (count != null) {
builder.add(count, cst.xy(1, 1, "right, center"));
}
}
}
}
```
|
```c++
//file LICENSE_1_0.txt or copy at path_to_url
#ifndef BOOST_QVM_FA16BB11ADAE248879FE52DB2543E53C
#define BOOST_QVM_FA16BB11ADAE248879FE52DB2543E53C
//This file was generated by a program. Do not edit manually.
#include <boost/qvm/detail/swizzle_traits.hpp>
#include <boost/qvm/enable_if.hpp>
#include <boost/qvm/inline.hpp>
namespace
boost
{
namespace
qvm
{
BOOST_QVM_INLINE_TRIVIAL
qvm_detail::sw01_<qvm_detail::swizzle_idx<-2,qvm_detail::swizzle_idx<-2,qvm_detail::swizzle_idx<-2 > > > > const &
_111()
{
return *reinterpret_cast<qvm_detail::sw01_<qvm_detail::swizzle_idx<-2,qvm_detail::swizzle_idx<-2,qvm_detail::swizzle_idx<-2 > > > > const *>(qvm_detail::get_null());
}
BOOST_QVM_INLINE_TRIVIAL
qvm_detail::sw01_<qvm_detail::swizzle_idx<-1,qvm_detail::swizzle_idx<-2,qvm_detail::swizzle_idx<-2 > > > > const &
_011()
{
return *reinterpret_cast<qvm_detail::sw01_<qvm_detail::swizzle_idx<-1,qvm_detail::swizzle_idx<-2,qvm_detail::swizzle_idx<-2 > > > > const *>(qvm_detail::get_null());
}
template <class V>
BOOST_QVM_INLINE_TRIVIAL
typename enable_if_c<
is_vec<V>::value && vec_traits<V>::dim>=4,
qvm_detail::sw_<V,qvm_detail::swizzle_idx<3,qvm_detail::swizzle_idx<-2,qvm_detail::swizzle_idx<-2 > > > > const &>::type
W11( V const & a )
{
return reinterpret_cast<qvm_detail::sw_<V,qvm_detail::swizzle_idx<3,qvm_detail::swizzle_idx<-2,qvm_detail::swizzle_idx<-2 > > > > const &>(a);
}
template <class V>
BOOST_QVM_INLINE_TRIVIAL
typename enable_if_c<
is_vec<V>::value && vec_traits<V>::dim>=4,
qvm_detail::sw_<V,qvm_detail::swizzle_idx<3,qvm_detail::swizzle_idx<-2,qvm_detail::swizzle_idx<-2 > > > > &>::type
W11( V & a )
{
return reinterpret_cast<qvm_detail::sw_<V,qvm_detail::swizzle_idx<3,qvm_detail::swizzle_idx<-2,qvm_detail::swizzle_idx<-2 > > > > &>(a);
}
template <class V>
BOOST_QVM_INLINE_TRIVIAL
typename enable_if_c<
is_vec<V>::value && vec_traits<V>::dim>=3,
qvm_detail::sw_<V,qvm_detail::swizzle_idx<2,qvm_detail::swizzle_idx<-2,qvm_detail::swizzle_idx<-2 > > > > const &>::type
Z11( V const & a )
{
return reinterpret_cast<qvm_detail::sw_<V,qvm_detail::swizzle_idx<2,qvm_detail::swizzle_idx<-2,qvm_detail::swizzle_idx<-2 > > > > const &>(a);
}
template <class V>
BOOST_QVM_INLINE_TRIVIAL
typename enable_if_c<
is_vec<V>::value && vec_traits<V>::dim>=3,
qvm_detail::sw_<V,qvm_detail::swizzle_idx<2,qvm_detail::swizzle_idx<-2,qvm_detail::swizzle_idx<-2 > > > > &>::type
Z11( V & a )
{
return reinterpret_cast<qvm_detail::sw_<V,qvm_detail::swizzle_idx<2,qvm_detail::swizzle_idx<-2,qvm_detail::swizzle_idx<-2 > > > > &>(a);
}
template <class V>
BOOST_QVM_INLINE_TRIVIAL
typename enable_if_c<
is_vec<V>::value && vec_traits<V>::dim>=2,
qvm_detail::sw_<V,qvm_detail::swizzle_idx<1,qvm_detail::swizzle_idx<-2,qvm_detail::swizzle_idx<-2 > > > > const &>::type
Y11( V const & a )
{
return reinterpret_cast<qvm_detail::sw_<V,qvm_detail::swizzle_idx<1,qvm_detail::swizzle_idx<-2,qvm_detail::swizzle_idx<-2 > > > > const &>(a);
}
template <class V>
BOOST_QVM_INLINE_TRIVIAL
typename enable_if_c<
is_vec<V>::value && vec_traits<V>::dim>=2,
qvm_detail::sw_<V,qvm_detail::swizzle_idx<1,qvm_detail::swizzle_idx<-2,qvm_detail::swizzle_idx<-2 > > > > &>::type
Y11( V & a )
{
return reinterpret_cast<qvm_detail::sw_<V,qvm_detail::swizzle_idx<1,qvm_detail::swizzle_idx<-2,qvm_detail::swizzle_idx<-2 > > > > &>(a);
}
template <class V>
BOOST_QVM_INLINE_TRIVIAL
typename enable_if_c<
is_vec<V>::value && vec_traits<V>::dim>=1,
qvm_detail::sw_<V,qvm_detail::swizzle_idx<0,qvm_detail::swizzle_idx<-2,qvm_detail::swizzle_idx<-2 > > > > const &>::type
X11( V const & a )
{
return reinterpret_cast<qvm_detail::sw_<V,qvm_detail::swizzle_idx<0,qvm_detail::swizzle_idx<-2,qvm_detail::swizzle_idx<-2 > > > > const &>(a);
}
template <class S>
BOOST_QVM_INLINE_TRIVIAL
typename enable_if_c<
is_scalar<S>::value,
qvm_detail::sws_<S,qvm_detail::swizzle_idx<0,qvm_detail::swizzle_idx<-2,qvm_detail::swizzle_idx<-2 > > > > const &>::type
X11( S const & a )
{
return reinterpret_cast<qvm_detail::sws_<S,qvm_detail::swizzle_idx<0,qvm_detail::swizzle_idx<-2,qvm_detail::swizzle_idx<-2 > > > > const &>(a);
}
template <class V>
BOOST_QVM_INLINE_TRIVIAL
typename enable_if_c<
is_vec<V>::value && vec_traits<V>::dim>=1,
qvm_detail::sw_<V,qvm_detail::swizzle_idx<0,qvm_detail::swizzle_idx<-2,qvm_detail::swizzle_idx<-2 > > > > &>::type
X11( V & a )
{
return reinterpret_cast<qvm_detail::sw_<V,qvm_detail::swizzle_idx<0,qvm_detail::swizzle_idx<-2,qvm_detail::swizzle_idx<-2 > > > > &>(a);
}
template <class S>
BOOST_QVM_INLINE_TRIVIAL
typename enable_if_c<
is_scalar<S>::value,
qvm_detail::sws_<S,qvm_detail::swizzle_idx<0,qvm_detail::swizzle_idx<-2,qvm_detail::swizzle_idx<-2 > > > > &>::type
X11( S & a )
{
return reinterpret_cast<qvm_detail::sws_<S,qvm_detail::swizzle_idx<0,qvm_detail::swizzle_idx<-2,qvm_detail::swizzle_idx<-2 > > > > &>(a);
}
BOOST_QVM_INLINE_TRIVIAL
qvm_detail::sw01_<qvm_detail::swizzle_idx<-2,qvm_detail::swizzle_idx<-1,qvm_detail::swizzle_idx<-2 > > > > const &
_101()
{
return *reinterpret_cast<qvm_detail::sw01_<qvm_detail::swizzle_idx<-2,qvm_detail::swizzle_idx<-1,qvm_detail::swizzle_idx<-2 > > > > const *>(qvm_detail::get_null());
}
BOOST_QVM_INLINE_TRIVIAL
qvm_detail::sw01_<qvm_detail::swizzle_idx<-1,qvm_detail::swizzle_idx<-1,qvm_detail::swizzle_idx<-2 > > > > const &
_001()
{
return *reinterpret_cast<qvm_detail::sw01_<qvm_detail::swizzle_idx<-1,qvm_detail::swizzle_idx<-1,qvm_detail::swizzle_idx<-2 > > > > const *>(qvm_detail::get_null());
}
template <class V>
BOOST_QVM_INLINE_TRIVIAL
typename enable_if_c<
is_vec<V>::value && vec_traits<V>::dim>=4,
qvm_detail::sw_<V,qvm_detail::swizzle_idx<3,qvm_detail::swizzle_idx<-1,qvm_detail::swizzle_idx<-2 > > > > const &>::type
W01( V const & a )
{
return reinterpret_cast<qvm_detail::sw_<V,qvm_detail::swizzle_idx<3,qvm_detail::swizzle_idx<-1,qvm_detail::swizzle_idx<-2 > > > > const &>(a);
}
template <class V>
BOOST_QVM_INLINE_TRIVIAL
typename enable_if_c<
is_vec<V>::value && vec_traits<V>::dim>=4,
qvm_detail::sw_<V,qvm_detail::swizzle_idx<3,qvm_detail::swizzle_idx<-1,qvm_detail::swizzle_idx<-2 > > > > &>::type
W01( V & a )
{
return reinterpret_cast<qvm_detail::sw_<V,qvm_detail::swizzle_idx<3,qvm_detail::swizzle_idx<-1,qvm_detail::swizzle_idx<-2 > > > > &>(a);
}
template <class V>
BOOST_QVM_INLINE_TRIVIAL
typename enable_if_c<
is_vec<V>::value && vec_traits<V>::dim>=3,
qvm_detail::sw_<V,qvm_detail::swizzle_idx<2,qvm_detail::swizzle_idx<-1,qvm_detail::swizzle_idx<-2 > > > > const &>::type
Z01( V const & a )
{
return reinterpret_cast<qvm_detail::sw_<V,qvm_detail::swizzle_idx<2,qvm_detail::swizzle_idx<-1,qvm_detail::swizzle_idx<-2 > > > > const &>(a);
}
template <class V>
BOOST_QVM_INLINE_TRIVIAL
typename enable_if_c<
is_vec<V>::value && vec_traits<V>::dim>=3,
qvm_detail::sw_<V,qvm_detail::swizzle_idx<2,qvm_detail::swizzle_idx<-1,qvm_detail::swizzle_idx<-2 > > > > &>::type
Z01( V & a )
{
return reinterpret_cast<qvm_detail::sw_<V,qvm_detail::swizzle_idx<2,qvm_detail::swizzle_idx<-1,qvm_detail::swizzle_idx<-2 > > > > &>(a);
}
template <class V>
BOOST_QVM_INLINE_TRIVIAL
typename enable_if_c<
is_vec<V>::value && vec_traits<V>::dim>=2,
qvm_detail::sw_<V,qvm_detail::swizzle_idx<1,qvm_detail::swizzle_idx<-1,qvm_detail::swizzle_idx<-2 > > > > const &>::type
Y01( V const & a )
{
return reinterpret_cast<qvm_detail::sw_<V,qvm_detail::swizzle_idx<1,qvm_detail::swizzle_idx<-1,qvm_detail::swizzle_idx<-2 > > > > const &>(a);
}
template <class V>
BOOST_QVM_INLINE_TRIVIAL
typename enable_if_c<
is_vec<V>::value && vec_traits<V>::dim>=2,
qvm_detail::sw_<V,qvm_detail::swizzle_idx<1,qvm_detail::swizzle_idx<-1,qvm_detail::swizzle_idx<-2 > > > > &>::type
Y01( V & a )
{
return reinterpret_cast<qvm_detail::sw_<V,qvm_detail::swizzle_idx<1,qvm_detail::swizzle_idx<-1,qvm_detail::swizzle_idx<-2 > > > > &>(a);
}
template <class V>
BOOST_QVM_INLINE_TRIVIAL
typename enable_if_c<
is_vec<V>::value && vec_traits<V>::dim>=1,
qvm_detail::sw_<V,qvm_detail::swizzle_idx<0,qvm_detail::swizzle_idx<-1,qvm_detail::swizzle_idx<-2 > > > > const &>::type
X01( V const & a )
{
return reinterpret_cast<qvm_detail::sw_<V,qvm_detail::swizzle_idx<0,qvm_detail::swizzle_idx<-1,qvm_detail::swizzle_idx<-2 > > > > const &>(a);
}
template <class S>
BOOST_QVM_INLINE_TRIVIAL
typename enable_if_c<
is_scalar<S>::value,
qvm_detail::sws_<S,qvm_detail::swizzle_idx<0,qvm_detail::swizzle_idx<-1,qvm_detail::swizzle_idx<-2 > > > > const &>::type
X01( S const & a )
{
return reinterpret_cast<qvm_detail::sws_<S,qvm_detail::swizzle_idx<0,qvm_detail::swizzle_idx<-1,qvm_detail::swizzle_idx<-2 > > > > const &>(a);
}
template <class V>
BOOST_QVM_INLINE_TRIVIAL
typename enable_if_c<
is_vec<V>::value && vec_traits<V>::dim>=1,
qvm_detail::sw_<V,qvm_detail::swizzle_idx<0,qvm_detail::swizzle_idx<-1,qvm_detail::swizzle_idx<-2 > > > > &>::type
X01( V & a )
{
return reinterpret_cast<qvm_detail::sw_<V,qvm_detail::swizzle_idx<0,qvm_detail::swizzle_idx<-1,qvm_detail::swizzle_idx<-2 > > > > &>(a);
}
template <class S>
BOOST_QVM_INLINE_TRIVIAL
typename enable_if_c<
is_scalar<S>::value,
qvm_detail::sws_<S,qvm_detail::swizzle_idx<0,qvm_detail::swizzle_idx<-1,qvm_detail::swizzle_idx<-2 > > > > &>::type
X01( S & a )
{
return reinterpret_cast<qvm_detail::sws_<S,qvm_detail::swizzle_idx<0,qvm_detail::swizzle_idx<-1,qvm_detail::swizzle_idx<-2 > > > > &>(a);
}
template <class V>
BOOST_QVM_INLINE_TRIVIAL
typename enable_if_c<
is_vec<V>::value && vec_traits<V>::dim>=4,
qvm_detail::sw_<V,qvm_detail::swizzle_idx<-2,qvm_detail::swizzle_idx<3,qvm_detail::swizzle_idx<-2 > > > > const &>::type
_1W1( V const & a )
{
return reinterpret_cast<qvm_detail::sw_<V,qvm_detail::swizzle_idx<-2,qvm_detail::swizzle_idx<3,qvm_detail::swizzle_idx<-2 > > > > const &>(a);
}
template <class V>
BOOST_QVM_INLINE_TRIVIAL
typename enable_if_c<
is_vec<V>::value && vec_traits<V>::dim>=4,
qvm_detail::sw_<V,qvm_detail::swizzle_idx<-2,qvm_detail::swizzle_idx<3,qvm_detail::swizzle_idx<-2 > > > > &>::type
_1W1( V & a )
{
return reinterpret_cast<qvm_detail::sw_<V,qvm_detail::swizzle_idx<-2,qvm_detail::swizzle_idx<3,qvm_detail::swizzle_idx<-2 > > > > &>(a);
}
template <class V>
BOOST_QVM_INLINE_TRIVIAL
typename enable_if_c<
is_vec<V>::value && vec_traits<V>::dim>=4,
qvm_detail::sw_<V,qvm_detail::swizzle_idx<-1,qvm_detail::swizzle_idx<3,qvm_detail::swizzle_idx<-2 > > > > const &>::type
_0W1( V const & a )
{
return reinterpret_cast<qvm_detail::sw_<V,qvm_detail::swizzle_idx<-1,qvm_detail::swizzle_idx<3,qvm_detail::swizzle_idx<-2 > > > > const &>(a);
}
template <class V>
BOOST_QVM_INLINE_TRIVIAL
typename enable_if_c<
is_vec<V>::value && vec_traits<V>::dim>=4,
qvm_detail::sw_<V,qvm_detail::swizzle_idx<-1,qvm_detail::swizzle_idx<3,qvm_detail::swizzle_idx<-2 > > > > &>::type
_0W1( V & a )
{
return reinterpret_cast<qvm_detail::sw_<V,qvm_detail::swizzle_idx<-1,qvm_detail::swizzle_idx<3,qvm_detail::swizzle_idx<-2 > > > > &>(a);
}
template <class V>
BOOST_QVM_INLINE_TRIVIAL
typename enable_if_c<
is_vec<V>::value && vec_traits<V>::dim>=4,
qvm_detail::sw_<V,qvm_detail::swizzle_idx<3,qvm_detail::swizzle_idx<3,qvm_detail::swizzle_idx<-2 > > > > const &>::type
WW1( V const & a )
{
return reinterpret_cast<qvm_detail::sw_<V,qvm_detail::swizzle_idx<3,qvm_detail::swizzle_idx<3,qvm_detail::swizzle_idx<-2 > > > > const &>(a);
}
template <class V>
BOOST_QVM_INLINE_TRIVIAL
typename enable_if_c<
is_vec<V>::value && vec_traits<V>::dim>=4,
qvm_detail::sw_<V,qvm_detail::swizzle_idx<3,qvm_detail::swizzle_idx<3,qvm_detail::swizzle_idx<-2 > > > > &>::type
WW1( V & a )
{
return reinterpret_cast<qvm_detail::sw_<V,qvm_detail::swizzle_idx<3,qvm_detail::swizzle_idx<3,qvm_detail::swizzle_idx<-2 > > > > &>(a);
}
template <class V>
BOOST_QVM_INLINE_TRIVIAL
typename enable_if_c<
is_vec<V>::value && vec_traits<V>::dim>=4,
qvm_detail::sw_<V,qvm_detail::swizzle_idx<2,qvm_detail::swizzle_idx<3,qvm_detail::swizzle_idx<-2 > > > > const &>::type
ZW1( V const & a )
{
return reinterpret_cast<qvm_detail::sw_<V,qvm_detail::swizzle_idx<2,qvm_detail::swizzle_idx<3,qvm_detail::swizzle_idx<-2 > > > > const &>(a);
}
template <class V>
BOOST_QVM_INLINE_TRIVIAL
typename enable_if_c<
is_vec<V>::value && vec_traits<V>::dim>=4,
qvm_detail::sw_<V,qvm_detail::swizzle_idx<2,qvm_detail::swizzle_idx<3,qvm_detail::swizzle_idx<-2 > > > > &>::type
ZW1( V & a )
{
return reinterpret_cast<qvm_detail::sw_<V,qvm_detail::swizzle_idx<2,qvm_detail::swizzle_idx<3,qvm_detail::swizzle_idx<-2 > > > > &>(a);
}
template <class V>
BOOST_QVM_INLINE_TRIVIAL
typename enable_if_c<
is_vec<V>::value && vec_traits<V>::dim>=4,
qvm_detail::sw_<V,qvm_detail::swizzle_idx<1,qvm_detail::swizzle_idx<3,qvm_detail::swizzle_idx<-2 > > > > const &>::type
YW1( V const & a )
{
return reinterpret_cast<qvm_detail::sw_<V,qvm_detail::swizzle_idx<1,qvm_detail::swizzle_idx<3,qvm_detail::swizzle_idx<-2 > > > > const &>(a);
}
template <class V>
BOOST_QVM_INLINE_TRIVIAL
typename enable_if_c<
is_vec<V>::value && vec_traits<V>::dim>=4,
qvm_detail::sw_<V,qvm_detail::swizzle_idx<1,qvm_detail::swizzle_idx<3,qvm_detail::swizzle_idx<-2 > > > > &>::type
YW1( V & a )
{
return reinterpret_cast<qvm_detail::sw_<V,qvm_detail::swizzle_idx<1,qvm_detail::swizzle_idx<3,qvm_detail::swizzle_idx<-2 > > > > &>(a);
}
template <class V>
BOOST_QVM_INLINE_TRIVIAL
typename enable_if_c<
is_vec<V>::value && vec_traits<V>::dim>=4,
qvm_detail::sw_<V,qvm_detail::swizzle_idx<0,qvm_detail::swizzle_idx<3,qvm_detail::swizzle_idx<-2 > > > > const &>::type
XW1( V const & a )
{
return reinterpret_cast<qvm_detail::sw_<V,qvm_detail::swizzle_idx<0,qvm_detail::swizzle_idx<3,qvm_detail::swizzle_idx<-2 > > > > const &>(a);
}
template <class V>
BOOST_QVM_INLINE_TRIVIAL
typename enable_if_c<
is_vec<V>::value && vec_traits<V>::dim>=4,
qvm_detail::sw_<V,qvm_detail::swizzle_idx<0,qvm_detail::swizzle_idx<3,qvm_detail::swizzle_idx<-2 > > > > &>::type
XW1( V & a )
{
return reinterpret_cast<qvm_detail::sw_<V,qvm_detail::swizzle_idx<0,qvm_detail::swizzle_idx<3,qvm_detail::swizzle_idx<-2 > > > > &>(a);
}
template <class V>
BOOST_QVM_INLINE_TRIVIAL
typename enable_if_c<
is_vec<V>::value && vec_traits<V>::dim>=3,
qvm_detail::sw_<V,qvm_detail::swizzle_idx<-2,qvm_detail::swizzle_idx<2,qvm_detail::swizzle_idx<-2 > > > > const &>::type
_1Z1( V const & a )
{
return reinterpret_cast<qvm_detail::sw_<V,qvm_detail::swizzle_idx<-2,qvm_detail::swizzle_idx<2,qvm_detail::swizzle_idx<-2 > > > > const &>(a);
}
template <class V>
BOOST_QVM_INLINE_TRIVIAL
typename enable_if_c<
is_vec<V>::value && vec_traits<V>::dim>=3,
qvm_detail::sw_<V,qvm_detail::swizzle_idx<-2,qvm_detail::swizzle_idx<2,qvm_detail::swizzle_idx<-2 > > > > &>::type
_1Z1( V & a )
{
return reinterpret_cast<qvm_detail::sw_<V,qvm_detail::swizzle_idx<-2,qvm_detail::swizzle_idx<2,qvm_detail::swizzle_idx<-2 > > > > &>(a);
}
template <class V>
BOOST_QVM_INLINE_TRIVIAL
typename enable_if_c<
is_vec<V>::value && vec_traits<V>::dim>=3,
qvm_detail::sw_<V,qvm_detail::swizzle_idx<-1,qvm_detail::swizzle_idx<2,qvm_detail::swizzle_idx<-2 > > > > const &>::type
_0Z1( V const & a )
{
return reinterpret_cast<qvm_detail::sw_<V,qvm_detail::swizzle_idx<-1,qvm_detail::swizzle_idx<2,qvm_detail::swizzle_idx<-2 > > > > const &>(a);
}
template <class V>
BOOST_QVM_INLINE_TRIVIAL
typename enable_if_c<
is_vec<V>::value && vec_traits<V>::dim>=3,
qvm_detail::sw_<V,qvm_detail::swizzle_idx<-1,qvm_detail::swizzle_idx<2,qvm_detail::swizzle_idx<-2 > > > > &>::type
_0Z1( V & a )
{
return reinterpret_cast<qvm_detail::sw_<V,qvm_detail::swizzle_idx<-1,qvm_detail::swizzle_idx<2,qvm_detail::swizzle_idx<-2 > > > > &>(a);
}
template <class V>
BOOST_QVM_INLINE_TRIVIAL
typename enable_if_c<
is_vec<V>::value && vec_traits<V>::dim>=4,
qvm_detail::sw_<V,qvm_detail::swizzle_idx<3,qvm_detail::swizzle_idx<2,qvm_detail::swizzle_idx<-2 > > > > const &>::type
WZ1( V const & a )
{
return reinterpret_cast<qvm_detail::sw_<V,qvm_detail::swizzle_idx<3,qvm_detail::swizzle_idx<2,qvm_detail::swizzle_idx<-2 > > > > const &>(a);
}
template <class V>
BOOST_QVM_INLINE_TRIVIAL
typename enable_if_c<
is_vec<V>::value && vec_traits<V>::dim>=4,
qvm_detail::sw_<V,qvm_detail::swizzle_idx<3,qvm_detail::swizzle_idx<2,qvm_detail::swizzle_idx<-2 > > > > &>::type
WZ1( V & a )
{
return reinterpret_cast<qvm_detail::sw_<V,qvm_detail::swizzle_idx<3,qvm_detail::swizzle_idx<2,qvm_detail::swizzle_idx<-2 > > > > &>(a);
}
template <class V>
BOOST_QVM_INLINE_TRIVIAL
typename enable_if_c<
is_vec<V>::value && vec_traits<V>::dim>=3,
qvm_detail::sw_<V,qvm_detail::swizzle_idx<2,qvm_detail::swizzle_idx<2,qvm_detail::swizzle_idx<-2 > > > > const &>::type
ZZ1( V const & a )
{
return reinterpret_cast<qvm_detail::sw_<V,qvm_detail::swizzle_idx<2,qvm_detail::swizzle_idx<2,qvm_detail::swizzle_idx<-2 > > > > const &>(a);
}
template <class V>
BOOST_QVM_INLINE_TRIVIAL
typename enable_if_c<
is_vec<V>::value && vec_traits<V>::dim>=3,
qvm_detail::sw_<V,qvm_detail::swizzle_idx<2,qvm_detail::swizzle_idx<2,qvm_detail::swizzle_idx<-2 > > > > &>::type
ZZ1( V & a )
{
return reinterpret_cast<qvm_detail::sw_<V,qvm_detail::swizzle_idx<2,qvm_detail::swizzle_idx<2,qvm_detail::swizzle_idx<-2 > > > > &>(a);
}
template <class V>
BOOST_QVM_INLINE_TRIVIAL
typename enable_if_c<
is_vec<V>::value && vec_traits<V>::dim>=3,
qvm_detail::sw_<V,qvm_detail::swizzle_idx<1,qvm_detail::swizzle_idx<2,qvm_detail::swizzle_idx<-2 > > > > const &>::type
YZ1( V const & a )
{
return reinterpret_cast<qvm_detail::sw_<V,qvm_detail::swizzle_idx<1,qvm_detail::swizzle_idx<2,qvm_detail::swizzle_idx<-2 > > > > const &>(a);
}
template <class V>
BOOST_QVM_INLINE_TRIVIAL
typename enable_if_c<
is_vec<V>::value && vec_traits<V>::dim>=3,
qvm_detail::sw_<V,qvm_detail::swizzle_idx<1,qvm_detail::swizzle_idx<2,qvm_detail::swizzle_idx<-2 > > > > &>::type
YZ1( V & a )
{
return reinterpret_cast<qvm_detail::sw_<V,qvm_detail::swizzle_idx<1,qvm_detail::swizzle_idx<2,qvm_detail::swizzle_idx<-2 > > > > &>(a);
}
template <class V>
BOOST_QVM_INLINE_TRIVIAL
typename enable_if_c<
is_vec<V>::value && vec_traits<V>::dim>=3,
qvm_detail::sw_<V,qvm_detail::swizzle_idx<0,qvm_detail::swizzle_idx<2,qvm_detail::swizzle_idx<-2 > > > > const &>::type
XZ1( V const & a )
{
return reinterpret_cast<qvm_detail::sw_<V,qvm_detail::swizzle_idx<0,qvm_detail::swizzle_idx<2,qvm_detail::swizzle_idx<-2 > > > > const &>(a);
}
template <class V>
BOOST_QVM_INLINE_TRIVIAL
typename enable_if_c<
is_vec<V>::value && vec_traits<V>::dim>=3,
qvm_detail::sw_<V,qvm_detail::swizzle_idx<0,qvm_detail::swizzle_idx<2,qvm_detail::swizzle_idx<-2 > > > > &>::type
XZ1( V & a )
{
return reinterpret_cast<qvm_detail::sw_<V,qvm_detail::swizzle_idx<0,qvm_detail::swizzle_idx<2,qvm_detail::swizzle_idx<-2 > > > > &>(a);
}
template <class V>
BOOST_QVM_INLINE_TRIVIAL
typename enable_if_c<
is_vec<V>::value && vec_traits<V>::dim>=2,
qvm_detail::sw_<V,qvm_detail::swizzle_idx<-2,qvm_detail::swizzle_idx<1,qvm_detail::swizzle_idx<-2 > > > > const &>::type
_1Y1( V const & a )
{
return reinterpret_cast<qvm_detail::sw_<V,qvm_detail::swizzle_idx<-2,qvm_detail::swizzle_idx<1,qvm_detail::swizzle_idx<-2 > > > > const &>(a);
}
template <class V>
BOOST_QVM_INLINE_TRIVIAL
typename enable_if_c<
is_vec<V>::value && vec_traits<V>::dim>=2,
qvm_detail::sw_<V,qvm_detail::swizzle_idx<-2,qvm_detail::swizzle_idx<1,qvm_detail::swizzle_idx<-2 > > > > &>::type
_1Y1( V & a )
{
return reinterpret_cast<qvm_detail::sw_<V,qvm_detail::swizzle_idx<-2,qvm_detail::swizzle_idx<1,qvm_detail::swizzle_idx<-2 > > > > &>(a);
}
template <class V>
BOOST_QVM_INLINE_TRIVIAL
typename enable_if_c<
is_vec<V>::value && vec_traits<V>::dim>=2,
qvm_detail::sw_<V,qvm_detail::swizzle_idx<-1,qvm_detail::swizzle_idx<1,qvm_detail::swizzle_idx<-2 > > > > const &>::type
_0Y1( V const & a )
{
return reinterpret_cast<qvm_detail::sw_<V,qvm_detail::swizzle_idx<-1,qvm_detail::swizzle_idx<1,qvm_detail::swizzle_idx<-2 > > > > const &>(a);
}
template <class V>
BOOST_QVM_INLINE_TRIVIAL
typename enable_if_c<
is_vec<V>::value && vec_traits<V>::dim>=2,
qvm_detail::sw_<V,qvm_detail::swizzle_idx<-1,qvm_detail::swizzle_idx<1,qvm_detail::swizzle_idx<-2 > > > > &>::type
_0Y1( V & a )
{
return reinterpret_cast<qvm_detail::sw_<V,qvm_detail::swizzle_idx<-1,qvm_detail::swizzle_idx<1,qvm_detail::swizzle_idx<-2 > > > > &>(a);
}
template <class V>
BOOST_QVM_INLINE_TRIVIAL
typename enable_if_c<
is_vec<V>::value && vec_traits<V>::dim>=4,
qvm_detail::sw_<V,qvm_detail::swizzle_idx<3,qvm_detail::swizzle_idx<1,qvm_detail::swizzle_idx<-2 > > > > const &>::type
WY1( V const & a )
{
return reinterpret_cast<qvm_detail::sw_<V,qvm_detail::swizzle_idx<3,qvm_detail::swizzle_idx<1,qvm_detail::swizzle_idx<-2 > > > > const &>(a);
}
template <class V>
BOOST_QVM_INLINE_TRIVIAL
typename enable_if_c<
is_vec<V>::value && vec_traits<V>::dim>=4,
qvm_detail::sw_<V,qvm_detail::swizzle_idx<3,qvm_detail::swizzle_idx<1,qvm_detail::swizzle_idx<-2 > > > > &>::type
WY1( V & a )
{
return reinterpret_cast<qvm_detail::sw_<V,qvm_detail::swizzle_idx<3,qvm_detail::swizzle_idx<1,qvm_detail::swizzle_idx<-2 > > > > &>(a);
}
template <class V>
BOOST_QVM_INLINE_TRIVIAL
typename enable_if_c<
is_vec<V>::value && vec_traits<V>::dim>=3,
qvm_detail::sw_<V,qvm_detail::swizzle_idx<2,qvm_detail::swizzle_idx<1,qvm_detail::swizzle_idx<-2 > > > > const &>::type
ZY1( V const & a )
{
return reinterpret_cast<qvm_detail::sw_<V,qvm_detail::swizzle_idx<2,qvm_detail::swizzle_idx<1,qvm_detail::swizzle_idx<-2 > > > > const &>(a);
}
template <class V>
BOOST_QVM_INLINE_TRIVIAL
typename enable_if_c<
is_vec<V>::value && vec_traits<V>::dim>=3,
qvm_detail::sw_<V,qvm_detail::swizzle_idx<2,qvm_detail::swizzle_idx<1,qvm_detail::swizzle_idx<-2 > > > > &>::type
ZY1( V & a )
{
return reinterpret_cast<qvm_detail::sw_<V,qvm_detail::swizzle_idx<2,qvm_detail::swizzle_idx<1,qvm_detail::swizzle_idx<-2 > > > > &>(a);
}
template <class V>
BOOST_QVM_INLINE_TRIVIAL
typename enable_if_c<
is_vec<V>::value && vec_traits<V>::dim>=2,
qvm_detail::sw_<V,qvm_detail::swizzle_idx<1,qvm_detail::swizzle_idx<1,qvm_detail::swizzle_idx<-2 > > > > const &>::type
YY1( V const & a )
{
return reinterpret_cast<qvm_detail::sw_<V,qvm_detail::swizzle_idx<1,qvm_detail::swizzle_idx<1,qvm_detail::swizzle_idx<-2 > > > > const &>(a);
}
template <class V>
BOOST_QVM_INLINE_TRIVIAL
typename enable_if_c<
is_vec<V>::value && vec_traits<V>::dim>=2,
qvm_detail::sw_<V,qvm_detail::swizzle_idx<1,qvm_detail::swizzle_idx<1,qvm_detail::swizzle_idx<-2 > > > > &>::type
YY1( V & a )
{
return reinterpret_cast<qvm_detail::sw_<V,qvm_detail::swizzle_idx<1,qvm_detail::swizzle_idx<1,qvm_detail::swizzle_idx<-2 > > > > &>(a);
}
template <class V>
BOOST_QVM_INLINE_TRIVIAL
typename enable_if_c<
is_vec<V>::value && vec_traits<V>::dim>=2,
qvm_detail::sw_<V,qvm_detail::swizzle_idx<0,qvm_detail::swizzle_idx<1,qvm_detail::swizzle_idx<-2 > > > > const &>::type
XY1( V const & a )
{
return reinterpret_cast<qvm_detail::sw_<V,qvm_detail::swizzle_idx<0,qvm_detail::swizzle_idx<1,qvm_detail::swizzle_idx<-2 > > > > const &>(a);
}
template <class V>
BOOST_QVM_INLINE_TRIVIAL
typename enable_if_c<
is_vec<V>::value && vec_traits<V>::dim>=2,
qvm_detail::sw_<V,qvm_detail::swizzle_idx<0,qvm_detail::swizzle_idx<1,qvm_detail::swizzle_idx<-2 > > > > &>::type
XY1( V & a )
{
return reinterpret_cast<qvm_detail::sw_<V,qvm_detail::swizzle_idx<0,qvm_detail::swizzle_idx<1,qvm_detail::swizzle_idx<-2 > > > > &>(a);
}
template <class V>
BOOST_QVM_INLINE_TRIVIAL
typename enable_if_c<
is_vec<V>::value && vec_traits<V>::dim>=1,
qvm_detail::sw_<V,qvm_detail::swizzle_idx<-2,qvm_detail::swizzle_idx<0,qvm_detail::swizzle_idx<-2 > > > > const &>::type
_1X1( V const & a )
{
return reinterpret_cast<qvm_detail::sw_<V,qvm_detail::swizzle_idx<-2,qvm_detail::swizzle_idx<0,qvm_detail::swizzle_idx<-2 > > > > const &>(a);
}
template <class S>
BOOST_QVM_INLINE_TRIVIAL
typename enable_if_c<
is_scalar<S>::value,
qvm_detail::sws_<S,qvm_detail::swizzle_idx<-2,qvm_detail::swizzle_idx<0,qvm_detail::swizzle_idx<-2 > > > > const &>::type
_1X1( S const & a )
{
return reinterpret_cast<qvm_detail::sws_<S,qvm_detail::swizzle_idx<-2,qvm_detail::swizzle_idx<0,qvm_detail::swizzle_idx<-2 > > > > const &>(a);
}
template <class V>
BOOST_QVM_INLINE_TRIVIAL
typename enable_if_c<
is_vec<V>::value && vec_traits<V>::dim>=1,
qvm_detail::sw_<V,qvm_detail::swizzle_idx<-2,qvm_detail::swizzle_idx<0,qvm_detail::swizzle_idx<-2 > > > > &>::type
_1X1( V & a )
{
return reinterpret_cast<qvm_detail::sw_<V,qvm_detail::swizzle_idx<-2,qvm_detail::swizzle_idx<0,qvm_detail::swizzle_idx<-2 > > > > &>(a);
}
template <class S>
BOOST_QVM_INLINE_TRIVIAL
typename enable_if_c<
is_scalar<S>::value,
qvm_detail::sws_<S,qvm_detail::swizzle_idx<-2,qvm_detail::swizzle_idx<0,qvm_detail::swizzle_idx<-2 > > > > &>::type
_1X1( S & a )
{
return reinterpret_cast<qvm_detail::sws_<S,qvm_detail::swizzle_idx<-2,qvm_detail::swizzle_idx<0,qvm_detail::swizzle_idx<-2 > > > > &>(a);
}
template <class V>
BOOST_QVM_INLINE_TRIVIAL
typename enable_if_c<
is_vec<V>::value && vec_traits<V>::dim>=1,
qvm_detail::sw_<V,qvm_detail::swizzle_idx<-1,qvm_detail::swizzle_idx<0,qvm_detail::swizzle_idx<-2 > > > > const &>::type
_0X1( V const & a )
{
return reinterpret_cast<qvm_detail::sw_<V,qvm_detail::swizzle_idx<-1,qvm_detail::swizzle_idx<0,qvm_detail::swizzle_idx<-2 > > > > const &>(a);
}
template <class S>
BOOST_QVM_INLINE_TRIVIAL
typename enable_if_c<
is_scalar<S>::value,
qvm_detail::sws_<S,qvm_detail::swizzle_idx<-1,qvm_detail::swizzle_idx<0,qvm_detail::swizzle_idx<-2 > > > > const &>::type
_0X1( S const & a )
{
return reinterpret_cast<qvm_detail::sws_<S,qvm_detail::swizzle_idx<-1,qvm_detail::swizzle_idx<0,qvm_detail::swizzle_idx<-2 > > > > const &>(a);
}
template <class V>
BOOST_QVM_INLINE_TRIVIAL
typename enable_if_c<
is_vec<V>::value && vec_traits<V>::dim>=1,
qvm_detail::sw_<V,qvm_detail::swizzle_idx<-1,qvm_detail::swizzle_idx<0,qvm_detail::swizzle_idx<-2 > > > > &>::type
_0X1( V & a )
{
return reinterpret_cast<qvm_detail::sw_<V,qvm_detail::swizzle_idx<-1,qvm_detail::swizzle_idx<0,qvm_detail::swizzle_idx<-2 > > > > &>(a);
}
template <class S>
BOOST_QVM_INLINE_TRIVIAL
typename enable_if_c<
is_scalar<S>::value,
qvm_detail::sws_<S,qvm_detail::swizzle_idx<-1,qvm_detail::swizzle_idx<0,qvm_detail::swizzle_idx<-2 > > > > &>::type
_0X1( S & a )
{
return reinterpret_cast<qvm_detail::sws_<S,qvm_detail::swizzle_idx<-1,qvm_detail::swizzle_idx<0,qvm_detail::swizzle_idx<-2 > > > > &>(a);
}
template <class V>
BOOST_QVM_INLINE_TRIVIAL
typename enable_if_c<
is_vec<V>::value && vec_traits<V>::dim>=4,
qvm_detail::sw_<V,qvm_detail::swizzle_idx<3,qvm_detail::swizzle_idx<0,qvm_detail::swizzle_idx<-2 > > > > const &>::type
WX1( V const & a )
{
return reinterpret_cast<qvm_detail::sw_<V,qvm_detail::swizzle_idx<3,qvm_detail::swizzle_idx<0,qvm_detail::swizzle_idx<-2 > > > > const &>(a);
}
template <class V>
BOOST_QVM_INLINE_TRIVIAL
typename enable_if_c<
is_vec<V>::value && vec_traits<V>::dim>=4,
qvm_detail::sw_<V,qvm_detail::swizzle_idx<3,qvm_detail::swizzle_idx<0,qvm_detail::swizzle_idx<-2 > > > > &>::type
WX1( V & a )
{
return reinterpret_cast<qvm_detail::sw_<V,qvm_detail::swizzle_idx<3,qvm_detail::swizzle_idx<0,qvm_detail::swizzle_idx<-2 > > > > &>(a);
}
template <class V>
BOOST_QVM_INLINE_TRIVIAL
typename enable_if_c<
is_vec<V>::value && vec_traits<V>::dim>=3,
qvm_detail::sw_<V,qvm_detail::swizzle_idx<2,qvm_detail::swizzle_idx<0,qvm_detail::swizzle_idx<-2 > > > > const &>::type
ZX1( V const & a )
{
return reinterpret_cast<qvm_detail::sw_<V,qvm_detail::swizzle_idx<2,qvm_detail::swizzle_idx<0,qvm_detail::swizzle_idx<-2 > > > > const &>(a);
}
template <class V>
BOOST_QVM_INLINE_TRIVIAL
typename enable_if_c<
is_vec<V>::value && vec_traits<V>::dim>=3,
qvm_detail::sw_<V,qvm_detail::swizzle_idx<2,qvm_detail::swizzle_idx<0,qvm_detail::swizzle_idx<-2 > > > > &>::type
ZX1( V & a )
{
return reinterpret_cast<qvm_detail::sw_<V,qvm_detail::swizzle_idx<2,qvm_detail::swizzle_idx<0,qvm_detail::swizzle_idx<-2 > > > > &>(a);
}
template <class V>
BOOST_QVM_INLINE_TRIVIAL
typename enable_if_c<
is_vec<V>::value && vec_traits<V>::dim>=2,
qvm_detail::sw_<V,qvm_detail::swizzle_idx<1,qvm_detail::swizzle_idx<0,qvm_detail::swizzle_idx<-2 > > > > const &>::type
YX1( V const & a )
{
return reinterpret_cast<qvm_detail::sw_<V,qvm_detail::swizzle_idx<1,qvm_detail::swizzle_idx<0,qvm_detail::swizzle_idx<-2 > > > > const &>(a);
}
template <class V>
BOOST_QVM_INLINE_TRIVIAL
typename enable_if_c<
is_vec<V>::value && vec_traits<V>::dim>=2,
qvm_detail::sw_<V,qvm_detail::swizzle_idx<1,qvm_detail::swizzle_idx<0,qvm_detail::swizzle_idx<-2 > > > > &>::type
YX1( V & a )
{
return reinterpret_cast<qvm_detail::sw_<V,qvm_detail::swizzle_idx<1,qvm_detail::swizzle_idx<0,qvm_detail::swizzle_idx<-2 > > > > &>(a);
}
template <class V>
BOOST_QVM_INLINE_TRIVIAL
typename enable_if_c<
is_vec<V>::value && vec_traits<V>::dim>=1,
qvm_detail::sw_<V,qvm_detail::swizzle_idx<0,qvm_detail::swizzle_idx<0,qvm_detail::swizzle_idx<-2 > > > > const &>::type
XX1( V const & a )
{
return reinterpret_cast<qvm_detail::sw_<V,qvm_detail::swizzle_idx<0,qvm_detail::swizzle_idx<0,qvm_detail::swizzle_idx<-2 > > > > const &>(a);
}
template <class S>
BOOST_QVM_INLINE_TRIVIAL
typename enable_if_c<
is_scalar<S>::value,
qvm_detail::sws_<S,qvm_detail::swizzle_idx<0,qvm_detail::swizzle_idx<0,qvm_detail::swizzle_idx<-2 > > > > const &>::type
XX1( S const & a )
{
return reinterpret_cast<qvm_detail::sws_<S,qvm_detail::swizzle_idx<0,qvm_detail::swizzle_idx<0,qvm_detail::swizzle_idx<-2 > > > > const &>(a);
}
template <class V>
BOOST_QVM_INLINE_TRIVIAL
typename enable_if_c<
is_vec<V>::value && vec_traits<V>::dim>=1,
qvm_detail::sw_<V,qvm_detail::swizzle_idx<0,qvm_detail::swizzle_idx<0,qvm_detail::swizzle_idx<-2 > > > > &>::type
XX1( V & a )
{
return reinterpret_cast<qvm_detail::sw_<V,qvm_detail::swizzle_idx<0,qvm_detail::swizzle_idx<0,qvm_detail::swizzle_idx<-2 > > > > &>(a);
}
template <class S>
BOOST_QVM_INLINE_TRIVIAL
typename enable_if_c<
is_scalar<S>::value,
qvm_detail::sws_<S,qvm_detail::swizzle_idx<0,qvm_detail::swizzle_idx<0,qvm_detail::swizzle_idx<-2 > > > > &>::type
XX1( S & a )
{
return reinterpret_cast<qvm_detail::sws_<S,qvm_detail::swizzle_idx<0,qvm_detail::swizzle_idx<0,qvm_detail::swizzle_idx<-2 > > > > &>(a);
}
BOOST_QVM_INLINE_TRIVIAL
qvm_detail::sw01_<qvm_detail::swizzle_idx<-2,qvm_detail::swizzle_idx<-2,qvm_detail::swizzle_idx<-1 > > > > const &
_110()
{
return *reinterpret_cast<qvm_detail::sw01_<qvm_detail::swizzle_idx<-2,qvm_detail::swizzle_idx<-2,qvm_detail::swizzle_idx<-1 > > > > const *>(qvm_detail::get_null());
}
BOOST_QVM_INLINE_TRIVIAL
qvm_detail::sw01_<qvm_detail::swizzle_idx<-1,qvm_detail::swizzle_idx<-2,qvm_detail::swizzle_idx<-1 > > > > const &
_010()
{
return *reinterpret_cast<qvm_detail::sw01_<qvm_detail::swizzle_idx<-1,qvm_detail::swizzle_idx<-2,qvm_detail::swizzle_idx<-1 > > > > const *>(qvm_detail::get_null());
}
template <class V>
BOOST_QVM_INLINE_TRIVIAL
typename enable_if_c<
is_vec<V>::value && vec_traits<V>::dim>=4,
qvm_detail::sw_<V,qvm_detail::swizzle_idx<3,qvm_detail::swizzle_idx<-2,qvm_detail::swizzle_idx<-1 > > > > const &>::type
W10( V const & a )
{
return reinterpret_cast<qvm_detail::sw_<V,qvm_detail::swizzle_idx<3,qvm_detail::swizzle_idx<-2,qvm_detail::swizzle_idx<-1 > > > > const &>(a);
}
template <class V>
BOOST_QVM_INLINE_TRIVIAL
typename enable_if_c<
is_vec<V>::value && vec_traits<V>::dim>=4,
qvm_detail::sw_<V,qvm_detail::swizzle_idx<3,qvm_detail::swizzle_idx<-2,qvm_detail::swizzle_idx<-1 > > > > &>::type
W10( V & a )
{
return reinterpret_cast<qvm_detail::sw_<V,qvm_detail::swizzle_idx<3,qvm_detail::swizzle_idx<-2,qvm_detail::swizzle_idx<-1 > > > > &>(a);
}
template <class V>
BOOST_QVM_INLINE_TRIVIAL
typename enable_if_c<
is_vec<V>::value && vec_traits<V>::dim>=3,
qvm_detail::sw_<V,qvm_detail::swizzle_idx<2,qvm_detail::swizzle_idx<-2,qvm_detail::swizzle_idx<-1 > > > > const &>::type
Z10( V const & a )
{
return reinterpret_cast<qvm_detail::sw_<V,qvm_detail::swizzle_idx<2,qvm_detail::swizzle_idx<-2,qvm_detail::swizzle_idx<-1 > > > > const &>(a);
}
template <class V>
BOOST_QVM_INLINE_TRIVIAL
typename enable_if_c<
is_vec<V>::value && vec_traits<V>::dim>=3,
qvm_detail::sw_<V,qvm_detail::swizzle_idx<2,qvm_detail::swizzle_idx<-2,qvm_detail::swizzle_idx<-1 > > > > &>::type
Z10( V & a )
{
return reinterpret_cast<qvm_detail::sw_<V,qvm_detail::swizzle_idx<2,qvm_detail::swizzle_idx<-2,qvm_detail::swizzle_idx<-1 > > > > &>(a);
}
template <class V>
BOOST_QVM_INLINE_TRIVIAL
typename enable_if_c<
is_vec<V>::value && vec_traits<V>::dim>=2,
qvm_detail::sw_<V,qvm_detail::swizzle_idx<1,qvm_detail::swizzle_idx<-2,qvm_detail::swizzle_idx<-1 > > > > const &>::type
Y10( V const & a )
{
return reinterpret_cast<qvm_detail::sw_<V,qvm_detail::swizzle_idx<1,qvm_detail::swizzle_idx<-2,qvm_detail::swizzle_idx<-1 > > > > const &>(a);
}
template <class V>
BOOST_QVM_INLINE_TRIVIAL
typename enable_if_c<
is_vec<V>::value && vec_traits<V>::dim>=2,
qvm_detail::sw_<V,qvm_detail::swizzle_idx<1,qvm_detail::swizzle_idx<-2,qvm_detail::swizzle_idx<-1 > > > > &>::type
Y10( V & a )
{
return reinterpret_cast<qvm_detail::sw_<V,qvm_detail::swizzle_idx<1,qvm_detail::swizzle_idx<-2,qvm_detail::swizzle_idx<-1 > > > > &>(a);
}
template <class V>
BOOST_QVM_INLINE_TRIVIAL
typename enable_if_c<
is_vec<V>::value && vec_traits<V>::dim>=1,
qvm_detail::sw_<V,qvm_detail::swizzle_idx<0,qvm_detail::swizzle_idx<-2,qvm_detail::swizzle_idx<-1 > > > > const &>::type
X10( V const & a )
{
return reinterpret_cast<qvm_detail::sw_<V,qvm_detail::swizzle_idx<0,qvm_detail::swizzle_idx<-2,qvm_detail::swizzle_idx<-1 > > > > const &>(a);
}
template <class S>
BOOST_QVM_INLINE_TRIVIAL
typename enable_if_c<
is_scalar<S>::value,
qvm_detail::sws_<S,qvm_detail::swizzle_idx<0,qvm_detail::swizzle_idx<-2,qvm_detail::swizzle_idx<-1 > > > > const &>::type
X10( S const & a )
{
return reinterpret_cast<qvm_detail::sws_<S,qvm_detail::swizzle_idx<0,qvm_detail::swizzle_idx<-2,qvm_detail::swizzle_idx<-1 > > > > const &>(a);
}
template <class V>
BOOST_QVM_INLINE_TRIVIAL
typename enable_if_c<
is_vec<V>::value && vec_traits<V>::dim>=1,
qvm_detail::sw_<V,qvm_detail::swizzle_idx<0,qvm_detail::swizzle_idx<-2,qvm_detail::swizzle_idx<-1 > > > > &>::type
X10( V & a )
{
return reinterpret_cast<qvm_detail::sw_<V,qvm_detail::swizzle_idx<0,qvm_detail::swizzle_idx<-2,qvm_detail::swizzle_idx<-1 > > > > &>(a);
}
template <class S>
BOOST_QVM_INLINE_TRIVIAL
typename enable_if_c<
is_scalar<S>::value,
qvm_detail::sws_<S,qvm_detail::swizzle_idx<0,qvm_detail::swizzle_idx<-2,qvm_detail::swizzle_idx<-1 > > > > &>::type
X10( S & a )
{
return reinterpret_cast<qvm_detail::sws_<S,qvm_detail::swizzle_idx<0,qvm_detail::swizzle_idx<-2,qvm_detail::swizzle_idx<-1 > > > > &>(a);
}
BOOST_QVM_INLINE_TRIVIAL
qvm_detail::sw01_<qvm_detail::swizzle_idx<-2,qvm_detail::swizzle_idx<-1,qvm_detail::swizzle_idx<-1 > > > > const &
_100()
{
return *reinterpret_cast<qvm_detail::sw01_<qvm_detail::swizzle_idx<-2,qvm_detail::swizzle_idx<-1,qvm_detail::swizzle_idx<-1 > > > > const *>(qvm_detail::get_null());
}
BOOST_QVM_INLINE_TRIVIAL
qvm_detail::sw01_<qvm_detail::swizzle_idx<-1,qvm_detail::swizzle_idx<-1,qvm_detail::swizzle_idx<-1 > > > > const &
_000()
{
return *reinterpret_cast<qvm_detail::sw01_<qvm_detail::swizzle_idx<-1,qvm_detail::swizzle_idx<-1,qvm_detail::swizzle_idx<-1 > > > > const *>(qvm_detail::get_null());
}
template <class V>
BOOST_QVM_INLINE_TRIVIAL
typename enable_if_c<
is_vec<V>::value && vec_traits<V>::dim>=4,
qvm_detail::sw_<V,qvm_detail::swizzle_idx<3,qvm_detail::swizzle_idx<-1,qvm_detail::swizzle_idx<-1 > > > > const &>::type
W00( V const & a )
{
return reinterpret_cast<qvm_detail::sw_<V,qvm_detail::swizzle_idx<3,qvm_detail::swizzle_idx<-1,qvm_detail::swizzle_idx<-1 > > > > const &>(a);
}
template <class V>
BOOST_QVM_INLINE_TRIVIAL
typename enable_if_c<
is_vec<V>::value && vec_traits<V>::dim>=4,
qvm_detail::sw_<V,qvm_detail::swizzle_idx<3,qvm_detail::swizzle_idx<-1,qvm_detail::swizzle_idx<-1 > > > > &>::type
W00( V & a )
{
return reinterpret_cast<qvm_detail::sw_<V,qvm_detail::swizzle_idx<3,qvm_detail::swizzle_idx<-1,qvm_detail::swizzle_idx<-1 > > > > &>(a);
}
template <class V>
BOOST_QVM_INLINE_TRIVIAL
typename enable_if_c<
is_vec<V>::value && vec_traits<V>::dim>=3,
qvm_detail::sw_<V,qvm_detail::swizzle_idx<2,qvm_detail::swizzle_idx<-1,qvm_detail::swizzle_idx<-1 > > > > const &>::type
Z00( V const & a )
{
return reinterpret_cast<qvm_detail::sw_<V,qvm_detail::swizzle_idx<2,qvm_detail::swizzle_idx<-1,qvm_detail::swizzle_idx<-1 > > > > const &>(a);
}
template <class V>
BOOST_QVM_INLINE_TRIVIAL
typename enable_if_c<
is_vec<V>::value && vec_traits<V>::dim>=3,
qvm_detail::sw_<V,qvm_detail::swizzle_idx<2,qvm_detail::swizzle_idx<-1,qvm_detail::swizzle_idx<-1 > > > > &>::type
Z00( V & a )
{
return reinterpret_cast<qvm_detail::sw_<V,qvm_detail::swizzle_idx<2,qvm_detail::swizzle_idx<-1,qvm_detail::swizzle_idx<-1 > > > > &>(a);
}
template <class V>
BOOST_QVM_INLINE_TRIVIAL
typename enable_if_c<
is_vec<V>::value && vec_traits<V>::dim>=2,
qvm_detail::sw_<V,qvm_detail::swizzle_idx<1,qvm_detail::swizzle_idx<-1,qvm_detail::swizzle_idx<-1 > > > > const &>::type
Y00( V const & a )
{
return reinterpret_cast<qvm_detail::sw_<V,qvm_detail::swizzle_idx<1,qvm_detail::swizzle_idx<-1,qvm_detail::swizzle_idx<-1 > > > > const &>(a);
}
template <class V>
BOOST_QVM_INLINE_TRIVIAL
typename enable_if_c<
is_vec<V>::value && vec_traits<V>::dim>=2,
qvm_detail::sw_<V,qvm_detail::swizzle_idx<1,qvm_detail::swizzle_idx<-1,qvm_detail::swizzle_idx<-1 > > > > &>::type
Y00( V & a )
{
return reinterpret_cast<qvm_detail::sw_<V,qvm_detail::swizzle_idx<1,qvm_detail::swizzle_idx<-1,qvm_detail::swizzle_idx<-1 > > > > &>(a);
}
template <class V>
BOOST_QVM_INLINE_TRIVIAL
typename enable_if_c<
is_vec<V>::value && vec_traits<V>::dim>=1,
qvm_detail::sw_<V,qvm_detail::swizzle_idx<0,qvm_detail::swizzle_idx<-1,qvm_detail::swizzle_idx<-1 > > > > const &>::type
X00( V const & a )
{
return reinterpret_cast<qvm_detail::sw_<V,qvm_detail::swizzle_idx<0,qvm_detail::swizzle_idx<-1,qvm_detail::swizzle_idx<-1 > > > > const &>(a);
}
template <class S>
BOOST_QVM_INLINE_TRIVIAL
typename enable_if_c<
is_scalar<S>::value,
qvm_detail::sws_<S,qvm_detail::swizzle_idx<0,qvm_detail::swizzle_idx<-1,qvm_detail::swizzle_idx<-1 > > > > const &>::type
X00( S const & a )
{
return reinterpret_cast<qvm_detail::sws_<S,qvm_detail::swizzle_idx<0,qvm_detail::swizzle_idx<-1,qvm_detail::swizzle_idx<-1 > > > > const &>(a);
}
template <class V>
BOOST_QVM_INLINE_TRIVIAL
typename enable_if_c<
is_vec<V>::value && vec_traits<V>::dim>=1,
qvm_detail::sw_<V,qvm_detail::swizzle_idx<0,qvm_detail::swizzle_idx<-1,qvm_detail::swizzle_idx<-1 > > > > &>::type
X00( V & a )
{
return reinterpret_cast<qvm_detail::sw_<V,qvm_detail::swizzle_idx<0,qvm_detail::swizzle_idx<-1,qvm_detail::swizzle_idx<-1 > > > > &>(a);
}
template <class S>
BOOST_QVM_INLINE_TRIVIAL
typename enable_if_c<
is_scalar<S>::value,
qvm_detail::sws_<S,qvm_detail::swizzle_idx<0,qvm_detail::swizzle_idx<-1,qvm_detail::swizzle_idx<-1 > > > > &>::type
X00( S & a )
{
return reinterpret_cast<qvm_detail::sws_<S,qvm_detail::swizzle_idx<0,qvm_detail::swizzle_idx<-1,qvm_detail::swizzle_idx<-1 > > > > &>(a);
}
template <class V>
BOOST_QVM_INLINE_TRIVIAL
typename enable_if_c<
is_vec<V>::value && vec_traits<V>::dim>=4,
qvm_detail::sw_<V,qvm_detail::swizzle_idx<-2,qvm_detail::swizzle_idx<3,qvm_detail::swizzle_idx<-1 > > > > const &>::type
_1W0( V const & a )
{
return reinterpret_cast<qvm_detail::sw_<V,qvm_detail::swizzle_idx<-2,qvm_detail::swizzle_idx<3,qvm_detail::swizzle_idx<-1 > > > > const &>(a);
}
template <class V>
BOOST_QVM_INLINE_TRIVIAL
typename enable_if_c<
is_vec<V>::value && vec_traits<V>::dim>=4,
qvm_detail::sw_<V,qvm_detail::swizzle_idx<-2,qvm_detail::swizzle_idx<3,qvm_detail::swizzle_idx<-1 > > > > &>::type
_1W0( V & a )
{
return reinterpret_cast<qvm_detail::sw_<V,qvm_detail::swizzle_idx<-2,qvm_detail::swizzle_idx<3,qvm_detail::swizzle_idx<-1 > > > > &>(a);
}
template <class V>
BOOST_QVM_INLINE_TRIVIAL
typename enable_if_c<
is_vec<V>::value && vec_traits<V>::dim>=4,
qvm_detail::sw_<V,qvm_detail::swizzle_idx<-1,qvm_detail::swizzle_idx<3,qvm_detail::swizzle_idx<-1 > > > > const &>::type
_0W0( V const & a )
{
return reinterpret_cast<qvm_detail::sw_<V,qvm_detail::swizzle_idx<-1,qvm_detail::swizzle_idx<3,qvm_detail::swizzle_idx<-1 > > > > const &>(a);
}
template <class V>
BOOST_QVM_INLINE_TRIVIAL
typename enable_if_c<
is_vec<V>::value && vec_traits<V>::dim>=4,
qvm_detail::sw_<V,qvm_detail::swizzle_idx<-1,qvm_detail::swizzle_idx<3,qvm_detail::swizzle_idx<-1 > > > > &>::type
_0W0( V & a )
{
return reinterpret_cast<qvm_detail::sw_<V,qvm_detail::swizzle_idx<-1,qvm_detail::swizzle_idx<3,qvm_detail::swizzle_idx<-1 > > > > &>(a);
}
template <class V>
BOOST_QVM_INLINE_TRIVIAL
typename enable_if_c<
is_vec<V>::value && vec_traits<V>::dim>=4,
qvm_detail::sw_<V,qvm_detail::swizzle_idx<3,qvm_detail::swizzle_idx<3,qvm_detail::swizzle_idx<-1 > > > > const &>::type
WW0( V const & a )
{
return reinterpret_cast<qvm_detail::sw_<V,qvm_detail::swizzle_idx<3,qvm_detail::swizzle_idx<3,qvm_detail::swizzle_idx<-1 > > > > const &>(a);
}
template <class V>
BOOST_QVM_INLINE_TRIVIAL
typename enable_if_c<
is_vec<V>::value && vec_traits<V>::dim>=4,
qvm_detail::sw_<V,qvm_detail::swizzle_idx<3,qvm_detail::swizzle_idx<3,qvm_detail::swizzle_idx<-1 > > > > &>::type
WW0( V & a )
{
return reinterpret_cast<qvm_detail::sw_<V,qvm_detail::swizzle_idx<3,qvm_detail::swizzle_idx<3,qvm_detail::swizzle_idx<-1 > > > > &>(a);
}
template <class V>
BOOST_QVM_INLINE_TRIVIAL
typename enable_if_c<
is_vec<V>::value && vec_traits<V>::dim>=4,
qvm_detail::sw_<V,qvm_detail::swizzle_idx<2,qvm_detail::swizzle_idx<3,qvm_detail::swizzle_idx<-1 > > > > const &>::type
ZW0( V const & a )
{
return reinterpret_cast<qvm_detail::sw_<V,qvm_detail::swizzle_idx<2,qvm_detail::swizzle_idx<3,qvm_detail::swizzle_idx<-1 > > > > const &>(a);
}
template <class V>
BOOST_QVM_INLINE_TRIVIAL
typename enable_if_c<
is_vec<V>::value && vec_traits<V>::dim>=4,
qvm_detail::sw_<V,qvm_detail::swizzle_idx<2,qvm_detail::swizzle_idx<3,qvm_detail::swizzle_idx<-1 > > > > &>::type
ZW0( V & a )
{
return reinterpret_cast<qvm_detail::sw_<V,qvm_detail::swizzle_idx<2,qvm_detail::swizzle_idx<3,qvm_detail::swizzle_idx<-1 > > > > &>(a);
}
template <class V>
BOOST_QVM_INLINE_TRIVIAL
typename enable_if_c<
is_vec<V>::value && vec_traits<V>::dim>=4,
qvm_detail::sw_<V,qvm_detail::swizzle_idx<1,qvm_detail::swizzle_idx<3,qvm_detail::swizzle_idx<-1 > > > > const &>::type
YW0( V const & a )
{
return reinterpret_cast<qvm_detail::sw_<V,qvm_detail::swizzle_idx<1,qvm_detail::swizzle_idx<3,qvm_detail::swizzle_idx<-1 > > > > const &>(a);
}
template <class V>
BOOST_QVM_INLINE_TRIVIAL
typename enable_if_c<
is_vec<V>::value && vec_traits<V>::dim>=4,
qvm_detail::sw_<V,qvm_detail::swizzle_idx<1,qvm_detail::swizzle_idx<3,qvm_detail::swizzle_idx<-1 > > > > &>::type
YW0( V & a )
{
return reinterpret_cast<qvm_detail::sw_<V,qvm_detail::swizzle_idx<1,qvm_detail::swizzle_idx<3,qvm_detail::swizzle_idx<-1 > > > > &>(a);
}
template <class V>
BOOST_QVM_INLINE_TRIVIAL
typename enable_if_c<
is_vec<V>::value && vec_traits<V>::dim>=4,
qvm_detail::sw_<V,qvm_detail::swizzle_idx<0,qvm_detail::swizzle_idx<3,qvm_detail::swizzle_idx<-1 > > > > const &>::type
XW0( V const & a )
{
return reinterpret_cast<qvm_detail::sw_<V,qvm_detail::swizzle_idx<0,qvm_detail::swizzle_idx<3,qvm_detail::swizzle_idx<-1 > > > > const &>(a);
}
template <class V>
BOOST_QVM_INLINE_TRIVIAL
typename enable_if_c<
is_vec<V>::value && vec_traits<V>::dim>=4,
qvm_detail::sw_<V,qvm_detail::swizzle_idx<0,qvm_detail::swizzle_idx<3,qvm_detail::swizzle_idx<-1 > > > > &>::type
XW0( V & a )
{
return reinterpret_cast<qvm_detail::sw_<V,qvm_detail::swizzle_idx<0,qvm_detail::swizzle_idx<3,qvm_detail::swizzle_idx<-1 > > > > &>(a);
}
template <class V>
BOOST_QVM_INLINE_TRIVIAL
typename enable_if_c<
is_vec<V>::value && vec_traits<V>::dim>=3,
qvm_detail::sw_<V,qvm_detail::swizzle_idx<-2,qvm_detail::swizzle_idx<2,qvm_detail::swizzle_idx<-1 > > > > const &>::type
_1Z0( V const & a )
{
return reinterpret_cast<qvm_detail::sw_<V,qvm_detail::swizzle_idx<-2,qvm_detail::swizzle_idx<2,qvm_detail::swizzle_idx<-1 > > > > const &>(a);
}
template <class V>
BOOST_QVM_INLINE_TRIVIAL
typename enable_if_c<
is_vec<V>::value && vec_traits<V>::dim>=3,
qvm_detail::sw_<V,qvm_detail::swizzle_idx<-2,qvm_detail::swizzle_idx<2,qvm_detail::swizzle_idx<-1 > > > > &>::type
_1Z0( V & a )
{
return reinterpret_cast<qvm_detail::sw_<V,qvm_detail::swizzle_idx<-2,qvm_detail::swizzle_idx<2,qvm_detail::swizzle_idx<-1 > > > > &>(a);
}
template <class V>
BOOST_QVM_INLINE_TRIVIAL
typename enable_if_c<
is_vec<V>::value && vec_traits<V>::dim>=3,
qvm_detail::sw_<V,qvm_detail::swizzle_idx<-1,qvm_detail::swizzle_idx<2,qvm_detail::swizzle_idx<-1 > > > > const &>::type
_0Z0( V const & a )
{
return reinterpret_cast<qvm_detail::sw_<V,qvm_detail::swizzle_idx<-1,qvm_detail::swizzle_idx<2,qvm_detail::swizzle_idx<-1 > > > > const &>(a);
}
template <class V>
BOOST_QVM_INLINE_TRIVIAL
typename enable_if_c<
is_vec<V>::value && vec_traits<V>::dim>=3,
qvm_detail::sw_<V,qvm_detail::swizzle_idx<-1,qvm_detail::swizzle_idx<2,qvm_detail::swizzle_idx<-1 > > > > &>::type
_0Z0( V & a )
{
return reinterpret_cast<qvm_detail::sw_<V,qvm_detail::swizzle_idx<-1,qvm_detail::swizzle_idx<2,qvm_detail::swizzle_idx<-1 > > > > &>(a);
}
template <class V>
BOOST_QVM_INLINE_TRIVIAL
typename enable_if_c<
is_vec<V>::value && vec_traits<V>::dim>=4,
qvm_detail::sw_<V,qvm_detail::swizzle_idx<3,qvm_detail::swizzle_idx<2,qvm_detail::swizzle_idx<-1 > > > > const &>::type
WZ0( V const & a )
{
return reinterpret_cast<qvm_detail::sw_<V,qvm_detail::swizzle_idx<3,qvm_detail::swizzle_idx<2,qvm_detail::swizzle_idx<-1 > > > > const &>(a);
}
template <class V>
BOOST_QVM_INLINE_TRIVIAL
typename enable_if_c<
is_vec<V>::value && vec_traits<V>::dim>=4,
qvm_detail::sw_<V,qvm_detail::swizzle_idx<3,qvm_detail::swizzle_idx<2,qvm_detail::swizzle_idx<-1 > > > > &>::type
WZ0( V & a )
{
return reinterpret_cast<qvm_detail::sw_<V,qvm_detail::swizzle_idx<3,qvm_detail::swizzle_idx<2,qvm_detail::swizzle_idx<-1 > > > > &>(a);
}
template <class V>
BOOST_QVM_INLINE_TRIVIAL
typename enable_if_c<
is_vec<V>::value && vec_traits<V>::dim>=3,
qvm_detail::sw_<V,qvm_detail::swizzle_idx<2,qvm_detail::swizzle_idx<2,qvm_detail::swizzle_idx<-1 > > > > const &>::type
ZZ0( V const & a )
{
return reinterpret_cast<qvm_detail::sw_<V,qvm_detail::swizzle_idx<2,qvm_detail::swizzle_idx<2,qvm_detail::swizzle_idx<-1 > > > > const &>(a);
}
template <class V>
BOOST_QVM_INLINE_TRIVIAL
typename enable_if_c<
is_vec<V>::value && vec_traits<V>::dim>=3,
qvm_detail::sw_<V,qvm_detail::swizzle_idx<2,qvm_detail::swizzle_idx<2,qvm_detail::swizzle_idx<-1 > > > > &>::type
ZZ0( V & a )
{
return reinterpret_cast<qvm_detail::sw_<V,qvm_detail::swizzle_idx<2,qvm_detail::swizzle_idx<2,qvm_detail::swizzle_idx<-1 > > > > &>(a);
}
template <class V>
BOOST_QVM_INLINE_TRIVIAL
typename enable_if_c<
is_vec<V>::value && vec_traits<V>::dim>=3,
qvm_detail::sw_<V,qvm_detail::swizzle_idx<1,qvm_detail::swizzle_idx<2,qvm_detail::swizzle_idx<-1 > > > > const &>::type
YZ0( V const & a )
{
return reinterpret_cast<qvm_detail::sw_<V,qvm_detail::swizzle_idx<1,qvm_detail::swizzle_idx<2,qvm_detail::swizzle_idx<-1 > > > > const &>(a);
}
template <class V>
BOOST_QVM_INLINE_TRIVIAL
typename enable_if_c<
is_vec<V>::value && vec_traits<V>::dim>=3,
qvm_detail::sw_<V,qvm_detail::swizzle_idx<1,qvm_detail::swizzle_idx<2,qvm_detail::swizzle_idx<-1 > > > > &>::type
YZ0( V & a )
{
return reinterpret_cast<qvm_detail::sw_<V,qvm_detail::swizzle_idx<1,qvm_detail::swizzle_idx<2,qvm_detail::swizzle_idx<-1 > > > > &>(a);
}
template <class V>
BOOST_QVM_INLINE_TRIVIAL
typename enable_if_c<
is_vec<V>::value && vec_traits<V>::dim>=3,
qvm_detail::sw_<V,qvm_detail::swizzle_idx<0,qvm_detail::swizzle_idx<2,qvm_detail::swizzle_idx<-1 > > > > const &>::type
XZ0( V const & a )
{
return reinterpret_cast<qvm_detail::sw_<V,qvm_detail::swizzle_idx<0,qvm_detail::swizzle_idx<2,qvm_detail::swizzle_idx<-1 > > > > const &>(a);
}
template <class V>
BOOST_QVM_INLINE_TRIVIAL
typename enable_if_c<
is_vec<V>::value && vec_traits<V>::dim>=3,
qvm_detail::sw_<V,qvm_detail::swizzle_idx<0,qvm_detail::swizzle_idx<2,qvm_detail::swizzle_idx<-1 > > > > &>::type
XZ0( V & a )
{
return reinterpret_cast<qvm_detail::sw_<V,qvm_detail::swizzle_idx<0,qvm_detail::swizzle_idx<2,qvm_detail::swizzle_idx<-1 > > > > &>(a);
}
template <class V>
BOOST_QVM_INLINE_TRIVIAL
typename enable_if_c<
is_vec<V>::value && vec_traits<V>::dim>=2,
qvm_detail::sw_<V,qvm_detail::swizzle_idx<-2,qvm_detail::swizzle_idx<1,qvm_detail::swizzle_idx<-1 > > > > const &>::type
_1Y0( V const & a )
{
return reinterpret_cast<qvm_detail::sw_<V,qvm_detail::swizzle_idx<-2,qvm_detail::swizzle_idx<1,qvm_detail::swizzle_idx<-1 > > > > const &>(a);
}
template <class V>
BOOST_QVM_INLINE_TRIVIAL
typename enable_if_c<
is_vec<V>::value && vec_traits<V>::dim>=2,
qvm_detail::sw_<V,qvm_detail::swizzle_idx<-2,qvm_detail::swizzle_idx<1,qvm_detail::swizzle_idx<-1 > > > > &>::type
_1Y0( V & a )
{
return reinterpret_cast<qvm_detail::sw_<V,qvm_detail::swizzle_idx<-2,qvm_detail::swizzle_idx<1,qvm_detail::swizzle_idx<-1 > > > > &>(a);
}
template <class V>
BOOST_QVM_INLINE_TRIVIAL
typename enable_if_c<
is_vec<V>::value && vec_traits<V>::dim>=2,
qvm_detail::sw_<V,qvm_detail::swizzle_idx<-1,qvm_detail::swizzle_idx<1,qvm_detail::swizzle_idx<-1 > > > > const &>::type
_0Y0( V const & a )
{
return reinterpret_cast<qvm_detail::sw_<V,qvm_detail::swizzle_idx<-1,qvm_detail::swizzle_idx<1,qvm_detail::swizzle_idx<-1 > > > > const &>(a);
}
template <class V>
BOOST_QVM_INLINE_TRIVIAL
typename enable_if_c<
is_vec<V>::value && vec_traits<V>::dim>=2,
qvm_detail::sw_<V,qvm_detail::swizzle_idx<-1,qvm_detail::swizzle_idx<1,qvm_detail::swizzle_idx<-1 > > > > &>::type
_0Y0( V & a )
{
return reinterpret_cast<qvm_detail::sw_<V,qvm_detail::swizzle_idx<-1,qvm_detail::swizzle_idx<1,qvm_detail::swizzle_idx<-1 > > > > &>(a);
}
template <class V>
BOOST_QVM_INLINE_TRIVIAL
typename enable_if_c<
is_vec<V>::value && vec_traits<V>::dim>=4,
qvm_detail::sw_<V,qvm_detail::swizzle_idx<3,qvm_detail::swizzle_idx<1,qvm_detail::swizzle_idx<-1 > > > > const &>::type
WY0( V const & a )
{
return reinterpret_cast<qvm_detail::sw_<V,qvm_detail::swizzle_idx<3,qvm_detail::swizzle_idx<1,qvm_detail::swizzle_idx<-1 > > > > const &>(a);
}
template <class V>
BOOST_QVM_INLINE_TRIVIAL
typename enable_if_c<
is_vec<V>::value && vec_traits<V>::dim>=4,
qvm_detail::sw_<V,qvm_detail::swizzle_idx<3,qvm_detail::swizzle_idx<1,qvm_detail::swizzle_idx<-1 > > > > &>::type
WY0( V & a )
{
return reinterpret_cast<qvm_detail::sw_<V,qvm_detail::swizzle_idx<3,qvm_detail::swizzle_idx<1,qvm_detail::swizzle_idx<-1 > > > > &>(a);
}
template <class V>
BOOST_QVM_INLINE_TRIVIAL
typename enable_if_c<
is_vec<V>::value && vec_traits<V>::dim>=3,
qvm_detail::sw_<V,qvm_detail::swizzle_idx<2,qvm_detail::swizzle_idx<1,qvm_detail::swizzle_idx<-1 > > > > const &>::type
ZY0( V const & a )
{
return reinterpret_cast<qvm_detail::sw_<V,qvm_detail::swizzle_idx<2,qvm_detail::swizzle_idx<1,qvm_detail::swizzle_idx<-1 > > > > const &>(a);
}
template <class V>
BOOST_QVM_INLINE_TRIVIAL
typename enable_if_c<
is_vec<V>::value && vec_traits<V>::dim>=3,
qvm_detail::sw_<V,qvm_detail::swizzle_idx<2,qvm_detail::swizzle_idx<1,qvm_detail::swizzle_idx<-1 > > > > &>::type
ZY0( V & a )
{
return reinterpret_cast<qvm_detail::sw_<V,qvm_detail::swizzle_idx<2,qvm_detail::swizzle_idx<1,qvm_detail::swizzle_idx<-1 > > > > &>(a);
}
template <class V>
BOOST_QVM_INLINE_TRIVIAL
typename enable_if_c<
is_vec<V>::value && vec_traits<V>::dim>=2,
qvm_detail::sw_<V,qvm_detail::swizzle_idx<1,qvm_detail::swizzle_idx<1,qvm_detail::swizzle_idx<-1 > > > > const &>::type
YY0( V const & a )
{
return reinterpret_cast<qvm_detail::sw_<V,qvm_detail::swizzle_idx<1,qvm_detail::swizzle_idx<1,qvm_detail::swizzle_idx<-1 > > > > const &>(a);
}
template <class V>
BOOST_QVM_INLINE_TRIVIAL
typename enable_if_c<
is_vec<V>::value && vec_traits<V>::dim>=2,
qvm_detail::sw_<V,qvm_detail::swizzle_idx<1,qvm_detail::swizzle_idx<1,qvm_detail::swizzle_idx<-1 > > > > &>::type
YY0( V & a )
{
return reinterpret_cast<qvm_detail::sw_<V,qvm_detail::swizzle_idx<1,qvm_detail::swizzle_idx<1,qvm_detail::swizzle_idx<-1 > > > > &>(a);
}
template <class V>
BOOST_QVM_INLINE_TRIVIAL
typename enable_if_c<
is_vec<V>::value && vec_traits<V>::dim>=2,
qvm_detail::sw_<V,qvm_detail::swizzle_idx<0,qvm_detail::swizzle_idx<1,qvm_detail::swizzle_idx<-1 > > > > const &>::type
XY0( V const & a )
{
return reinterpret_cast<qvm_detail::sw_<V,qvm_detail::swizzle_idx<0,qvm_detail::swizzle_idx<1,qvm_detail::swizzle_idx<-1 > > > > const &>(a);
}
template <class V>
BOOST_QVM_INLINE_TRIVIAL
typename enable_if_c<
is_vec<V>::value && vec_traits<V>::dim>=2,
qvm_detail::sw_<V,qvm_detail::swizzle_idx<0,qvm_detail::swizzle_idx<1,qvm_detail::swizzle_idx<-1 > > > > &>::type
XY0( V & a )
{
return reinterpret_cast<qvm_detail::sw_<V,qvm_detail::swizzle_idx<0,qvm_detail::swizzle_idx<1,qvm_detail::swizzle_idx<-1 > > > > &>(a);
}
template <class V>
BOOST_QVM_INLINE_TRIVIAL
typename enable_if_c<
is_vec<V>::value && vec_traits<V>::dim>=1,
qvm_detail::sw_<V,qvm_detail::swizzle_idx<-2,qvm_detail::swizzle_idx<0,qvm_detail::swizzle_idx<-1 > > > > const &>::type
_1X0( V const & a )
{
return reinterpret_cast<qvm_detail::sw_<V,qvm_detail::swizzle_idx<-2,qvm_detail::swizzle_idx<0,qvm_detail::swizzle_idx<-1 > > > > const &>(a);
}
template <class S>
BOOST_QVM_INLINE_TRIVIAL
typename enable_if_c<
is_scalar<S>::value,
qvm_detail::sws_<S,qvm_detail::swizzle_idx<-2,qvm_detail::swizzle_idx<0,qvm_detail::swizzle_idx<-1 > > > > const &>::type
_1X0( S const & a )
{
return reinterpret_cast<qvm_detail::sws_<S,qvm_detail::swizzle_idx<-2,qvm_detail::swizzle_idx<0,qvm_detail::swizzle_idx<-1 > > > > const &>(a);
}
template <class V>
BOOST_QVM_INLINE_TRIVIAL
typename enable_if_c<
is_vec<V>::value && vec_traits<V>::dim>=1,
qvm_detail::sw_<V,qvm_detail::swizzle_idx<-2,qvm_detail::swizzle_idx<0,qvm_detail::swizzle_idx<-1 > > > > &>::type
_1X0( V & a )
{
return reinterpret_cast<qvm_detail::sw_<V,qvm_detail::swizzle_idx<-2,qvm_detail::swizzle_idx<0,qvm_detail::swizzle_idx<-1 > > > > &>(a);
}
template <class S>
BOOST_QVM_INLINE_TRIVIAL
typename enable_if_c<
is_scalar<S>::value,
qvm_detail::sws_<S,qvm_detail::swizzle_idx<-2,qvm_detail::swizzle_idx<0,qvm_detail::swizzle_idx<-1 > > > > &>::type
_1X0( S & a )
{
return reinterpret_cast<qvm_detail::sws_<S,qvm_detail::swizzle_idx<-2,qvm_detail::swizzle_idx<0,qvm_detail::swizzle_idx<-1 > > > > &>(a);
}
template <class V>
BOOST_QVM_INLINE_TRIVIAL
typename enable_if_c<
is_vec<V>::value && vec_traits<V>::dim>=1,
qvm_detail::sw_<V,qvm_detail::swizzle_idx<-1,qvm_detail::swizzle_idx<0,qvm_detail::swizzle_idx<-1 > > > > const &>::type
_0X0( V const & a )
{
return reinterpret_cast<qvm_detail::sw_<V,qvm_detail::swizzle_idx<-1,qvm_detail::swizzle_idx<0,qvm_detail::swizzle_idx<-1 > > > > const &>(a);
}
template <class S>
BOOST_QVM_INLINE_TRIVIAL
typename enable_if_c<
is_scalar<S>::value,
qvm_detail::sws_<S,qvm_detail::swizzle_idx<-1,qvm_detail::swizzle_idx<0,qvm_detail::swizzle_idx<-1 > > > > const &>::type
_0X0( S const & a )
{
return reinterpret_cast<qvm_detail::sws_<S,qvm_detail::swizzle_idx<-1,qvm_detail::swizzle_idx<0,qvm_detail::swizzle_idx<-1 > > > > const &>(a);
}
template <class V>
BOOST_QVM_INLINE_TRIVIAL
typename enable_if_c<
is_vec<V>::value && vec_traits<V>::dim>=1,
qvm_detail::sw_<V,qvm_detail::swizzle_idx<-1,qvm_detail::swizzle_idx<0,qvm_detail::swizzle_idx<-1 > > > > &>::type
_0X0( V & a )
{
return reinterpret_cast<qvm_detail::sw_<V,qvm_detail::swizzle_idx<-1,qvm_detail::swizzle_idx<0,qvm_detail::swizzle_idx<-1 > > > > &>(a);
}
template <class S>
BOOST_QVM_INLINE_TRIVIAL
typename enable_if_c<
is_scalar<S>::value,
qvm_detail::sws_<S,qvm_detail::swizzle_idx<-1,qvm_detail::swizzle_idx<0,qvm_detail::swizzle_idx<-1 > > > > &>::type
_0X0( S & a )
{
return reinterpret_cast<qvm_detail::sws_<S,qvm_detail::swizzle_idx<-1,qvm_detail::swizzle_idx<0,qvm_detail::swizzle_idx<-1 > > > > &>(a);
}
template <class V>
BOOST_QVM_INLINE_TRIVIAL
typename enable_if_c<
is_vec<V>::value && vec_traits<V>::dim>=4,
qvm_detail::sw_<V,qvm_detail::swizzle_idx<3,qvm_detail::swizzle_idx<0,qvm_detail::swizzle_idx<-1 > > > > const &>::type
WX0( V const & a )
{
return reinterpret_cast<qvm_detail::sw_<V,qvm_detail::swizzle_idx<3,qvm_detail::swizzle_idx<0,qvm_detail::swizzle_idx<-1 > > > > const &>(a);
}
template <class V>
BOOST_QVM_INLINE_TRIVIAL
typename enable_if_c<
is_vec<V>::value && vec_traits<V>::dim>=4,
qvm_detail::sw_<V,qvm_detail::swizzle_idx<3,qvm_detail::swizzle_idx<0,qvm_detail::swizzle_idx<-1 > > > > &>::type
WX0( V & a )
{
return reinterpret_cast<qvm_detail::sw_<V,qvm_detail::swizzle_idx<3,qvm_detail::swizzle_idx<0,qvm_detail::swizzle_idx<-1 > > > > &>(a);
}
template <class V>
BOOST_QVM_INLINE_TRIVIAL
typename enable_if_c<
is_vec<V>::value && vec_traits<V>::dim>=3,
qvm_detail::sw_<V,qvm_detail::swizzle_idx<2,qvm_detail::swizzle_idx<0,qvm_detail::swizzle_idx<-1 > > > > const &>::type
ZX0( V const & a )
{
return reinterpret_cast<qvm_detail::sw_<V,qvm_detail::swizzle_idx<2,qvm_detail::swizzle_idx<0,qvm_detail::swizzle_idx<-1 > > > > const &>(a);
}
template <class V>
BOOST_QVM_INLINE_TRIVIAL
typename enable_if_c<
is_vec<V>::value && vec_traits<V>::dim>=3,
qvm_detail::sw_<V,qvm_detail::swizzle_idx<2,qvm_detail::swizzle_idx<0,qvm_detail::swizzle_idx<-1 > > > > &>::type
ZX0( V & a )
{
return reinterpret_cast<qvm_detail::sw_<V,qvm_detail::swizzle_idx<2,qvm_detail::swizzle_idx<0,qvm_detail::swizzle_idx<-1 > > > > &>(a);
}
template <class V>
BOOST_QVM_INLINE_TRIVIAL
typename enable_if_c<
is_vec<V>::value && vec_traits<V>::dim>=2,
qvm_detail::sw_<V,qvm_detail::swizzle_idx<1,qvm_detail::swizzle_idx<0,qvm_detail::swizzle_idx<-1 > > > > const &>::type
YX0( V const & a )
{
return reinterpret_cast<qvm_detail::sw_<V,qvm_detail::swizzle_idx<1,qvm_detail::swizzle_idx<0,qvm_detail::swizzle_idx<-1 > > > > const &>(a);
}
template <class V>
BOOST_QVM_INLINE_TRIVIAL
typename enable_if_c<
is_vec<V>::value && vec_traits<V>::dim>=2,
qvm_detail::sw_<V,qvm_detail::swizzle_idx<1,qvm_detail::swizzle_idx<0,qvm_detail::swizzle_idx<-1 > > > > &>::type
YX0( V & a )
{
return reinterpret_cast<qvm_detail::sw_<V,qvm_detail::swizzle_idx<1,qvm_detail::swizzle_idx<0,qvm_detail::swizzle_idx<-1 > > > > &>(a);
}
template <class V>
BOOST_QVM_INLINE_TRIVIAL
typename enable_if_c<
is_vec<V>::value && vec_traits<V>::dim>=1,
qvm_detail::sw_<V,qvm_detail::swizzle_idx<0,qvm_detail::swizzle_idx<0,qvm_detail::swizzle_idx<-1 > > > > const &>::type
XX0( V const & a )
{
return reinterpret_cast<qvm_detail::sw_<V,qvm_detail::swizzle_idx<0,qvm_detail::swizzle_idx<0,qvm_detail::swizzle_idx<-1 > > > > const &>(a);
}
template <class S>
BOOST_QVM_INLINE_TRIVIAL
typename enable_if_c<
is_scalar<S>::value,
qvm_detail::sws_<S,qvm_detail::swizzle_idx<0,qvm_detail::swizzle_idx<0,qvm_detail::swizzle_idx<-1 > > > > const &>::type
XX0( S const & a )
{
return reinterpret_cast<qvm_detail::sws_<S,qvm_detail::swizzle_idx<0,qvm_detail::swizzle_idx<0,qvm_detail::swizzle_idx<-1 > > > > const &>(a);
}
template <class V>
BOOST_QVM_INLINE_TRIVIAL
typename enable_if_c<
is_vec<V>::value && vec_traits<V>::dim>=1,
qvm_detail::sw_<V,qvm_detail::swizzle_idx<0,qvm_detail::swizzle_idx<0,qvm_detail::swizzle_idx<-1 > > > > &>::type
XX0( V & a )
{
return reinterpret_cast<qvm_detail::sw_<V,qvm_detail::swizzle_idx<0,qvm_detail::swizzle_idx<0,qvm_detail::swizzle_idx<-1 > > > > &>(a);
}
template <class S>
BOOST_QVM_INLINE_TRIVIAL
typename enable_if_c<
is_scalar<S>::value,
qvm_detail::sws_<S,qvm_detail::swizzle_idx<0,qvm_detail::swizzle_idx<0,qvm_detail::swizzle_idx<-1 > > > > &>::type
XX0( S & a )
{
return reinterpret_cast<qvm_detail::sws_<S,qvm_detail::swizzle_idx<0,qvm_detail::swizzle_idx<0,qvm_detail::swizzle_idx<-1 > > > > &>(a);
}
template <class V>
BOOST_QVM_INLINE_TRIVIAL
typename enable_if_c<
is_vec<V>::value && vec_traits<V>::dim>=4,
qvm_detail::sw_<V,qvm_detail::swizzle_idx<-2,qvm_detail::swizzle_idx<-2,qvm_detail::swizzle_idx<3 > > > > const &>::type
_11W( V const & a )
{
return reinterpret_cast<qvm_detail::sw_<V,qvm_detail::swizzle_idx<-2,qvm_detail::swizzle_idx<-2,qvm_detail::swizzle_idx<3 > > > > const &>(a);
}
template <class V>
BOOST_QVM_INLINE_TRIVIAL
typename enable_if_c<
is_vec<V>::value && vec_traits<V>::dim>=4,
qvm_detail::sw_<V,qvm_detail::swizzle_idx<-2,qvm_detail::swizzle_idx<-2,qvm_detail::swizzle_idx<3 > > > > &>::type
_11W( V & a )
{
return reinterpret_cast<qvm_detail::sw_<V,qvm_detail::swizzle_idx<-2,qvm_detail::swizzle_idx<-2,qvm_detail::swizzle_idx<3 > > > > &>(a);
}
template <class V>
BOOST_QVM_INLINE_TRIVIAL
typename enable_if_c<
is_vec<V>::value && vec_traits<V>::dim>=4,
qvm_detail::sw_<V,qvm_detail::swizzle_idx<-1,qvm_detail::swizzle_idx<-2,qvm_detail::swizzle_idx<3 > > > > const &>::type
_01W( V const & a )
{
return reinterpret_cast<qvm_detail::sw_<V,qvm_detail::swizzle_idx<-1,qvm_detail::swizzle_idx<-2,qvm_detail::swizzle_idx<3 > > > > const &>(a);
}
template <class V>
BOOST_QVM_INLINE_TRIVIAL
typename enable_if_c<
is_vec<V>::value && vec_traits<V>::dim>=4,
qvm_detail::sw_<V,qvm_detail::swizzle_idx<-1,qvm_detail::swizzle_idx<-2,qvm_detail::swizzle_idx<3 > > > > &>::type
_01W( V & a )
{
return reinterpret_cast<qvm_detail::sw_<V,qvm_detail::swizzle_idx<-1,qvm_detail::swizzle_idx<-2,qvm_detail::swizzle_idx<3 > > > > &>(a);
}
template <class V>
BOOST_QVM_INLINE_TRIVIAL
typename enable_if_c<
is_vec<V>::value && vec_traits<V>::dim>=4,
qvm_detail::sw_<V,qvm_detail::swizzle_idx<3,qvm_detail::swizzle_idx<-2,qvm_detail::swizzle_idx<3 > > > > const &>::type
W1W( V const & a )
{
return reinterpret_cast<qvm_detail::sw_<V,qvm_detail::swizzle_idx<3,qvm_detail::swizzle_idx<-2,qvm_detail::swizzle_idx<3 > > > > const &>(a);
}
template <class V>
BOOST_QVM_INLINE_TRIVIAL
typename enable_if_c<
is_vec<V>::value && vec_traits<V>::dim>=4,
qvm_detail::sw_<V,qvm_detail::swizzle_idx<3,qvm_detail::swizzle_idx<-2,qvm_detail::swizzle_idx<3 > > > > &>::type
W1W( V & a )
{
return reinterpret_cast<qvm_detail::sw_<V,qvm_detail::swizzle_idx<3,qvm_detail::swizzle_idx<-2,qvm_detail::swizzle_idx<3 > > > > &>(a);
}
template <class V>
BOOST_QVM_INLINE_TRIVIAL
typename enable_if_c<
is_vec<V>::value && vec_traits<V>::dim>=4,
qvm_detail::sw_<V,qvm_detail::swizzle_idx<2,qvm_detail::swizzle_idx<-2,qvm_detail::swizzle_idx<3 > > > > const &>::type
Z1W( V const & a )
{
return reinterpret_cast<qvm_detail::sw_<V,qvm_detail::swizzle_idx<2,qvm_detail::swizzle_idx<-2,qvm_detail::swizzle_idx<3 > > > > const &>(a);
}
template <class V>
BOOST_QVM_INLINE_TRIVIAL
typename enable_if_c<
is_vec<V>::value && vec_traits<V>::dim>=4,
qvm_detail::sw_<V,qvm_detail::swizzle_idx<2,qvm_detail::swizzle_idx<-2,qvm_detail::swizzle_idx<3 > > > > &>::type
Z1W( V & a )
{
return reinterpret_cast<qvm_detail::sw_<V,qvm_detail::swizzle_idx<2,qvm_detail::swizzle_idx<-2,qvm_detail::swizzle_idx<3 > > > > &>(a);
}
template <class V>
BOOST_QVM_INLINE_TRIVIAL
typename enable_if_c<
is_vec<V>::value && vec_traits<V>::dim>=4,
qvm_detail::sw_<V,qvm_detail::swizzle_idx<1,qvm_detail::swizzle_idx<-2,qvm_detail::swizzle_idx<3 > > > > const &>::type
Y1W( V const & a )
{
return reinterpret_cast<qvm_detail::sw_<V,qvm_detail::swizzle_idx<1,qvm_detail::swizzle_idx<-2,qvm_detail::swizzle_idx<3 > > > > const &>(a);
}
template <class V>
BOOST_QVM_INLINE_TRIVIAL
typename enable_if_c<
is_vec<V>::value && vec_traits<V>::dim>=4,
qvm_detail::sw_<V,qvm_detail::swizzle_idx<1,qvm_detail::swizzle_idx<-2,qvm_detail::swizzle_idx<3 > > > > &>::type
Y1W( V & a )
{
return reinterpret_cast<qvm_detail::sw_<V,qvm_detail::swizzle_idx<1,qvm_detail::swizzle_idx<-2,qvm_detail::swizzle_idx<3 > > > > &>(a);
}
template <class V>
BOOST_QVM_INLINE_TRIVIAL
typename enable_if_c<
is_vec<V>::value && vec_traits<V>::dim>=4,
qvm_detail::sw_<V,qvm_detail::swizzle_idx<0,qvm_detail::swizzle_idx<-2,qvm_detail::swizzle_idx<3 > > > > const &>::type
X1W( V const & a )
{
return reinterpret_cast<qvm_detail::sw_<V,qvm_detail::swizzle_idx<0,qvm_detail::swizzle_idx<-2,qvm_detail::swizzle_idx<3 > > > > const &>(a);
}
template <class V>
BOOST_QVM_INLINE_TRIVIAL
typename enable_if_c<
is_vec<V>::value && vec_traits<V>::dim>=4,
qvm_detail::sw_<V,qvm_detail::swizzle_idx<0,qvm_detail::swizzle_idx<-2,qvm_detail::swizzle_idx<3 > > > > &>::type
X1W( V & a )
{
return reinterpret_cast<qvm_detail::sw_<V,qvm_detail::swizzle_idx<0,qvm_detail::swizzle_idx<-2,qvm_detail::swizzle_idx<3 > > > > &>(a);
}
template <class V>
BOOST_QVM_INLINE_TRIVIAL
typename enable_if_c<
is_vec<V>::value && vec_traits<V>::dim>=4,
qvm_detail::sw_<V,qvm_detail::swizzle_idx<-2,qvm_detail::swizzle_idx<-1,qvm_detail::swizzle_idx<3 > > > > const &>::type
_10W( V const & a )
{
return reinterpret_cast<qvm_detail::sw_<V,qvm_detail::swizzle_idx<-2,qvm_detail::swizzle_idx<-1,qvm_detail::swizzle_idx<3 > > > > const &>(a);
}
template <class V>
BOOST_QVM_INLINE_TRIVIAL
typename enable_if_c<
is_vec<V>::value && vec_traits<V>::dim>=4,
qvm_detail::sw_<V,qvm_detail::swizzle_idx<-2,qvm_detail::swizzle_idx<-1,qvm_detail::swizzle_idx<3 > > > > &>::type
_10W( V & a )
{
return reinterpret_cast<qvm_detail::sw_<V,qvm_detail::swizzle_idx<-2,qvm_detail::swizzle_idx<-1,qvm_detail::swizzle_idx<3 > > > > &>(a);
}
template <class V>
BOOST_QVM_INLINE_TRIVIAL
typename enable_if_c<
is_vec<V>::value && vec_traits<V>::dim>=4,
qvm_detail::sw_<V,qvm_detail::swizzle_idx<-1,qvm_detail::swizzle_idx<-1,qvm_detail::swizzle_idx<3 > > > > const &>::type
_00W( V const & a )
{
return reinterpret_cast<qvm_detail::sw_<V,qvm_detail::swizzle_idx<-1,qvm_detail::swizzle_idx<-1,qvm_detail::swizzle_idx<3 > > > > const &>(a);
}
template <class V>
BOOST_QVM_INLINE_TRIVIAL
typename enable_if_c<
is_vec<V>::value && vec_traits<V>::dim>=4,
qvm_detail::sw_<V,qvm_detail::swizzle_idx<-1,qvm_detail::swizzle_idx<-1,qvm_detail::swizzle_idx<3 > > > > &>::type
_00W( V & a )
{
return reinterpret_cast<qvm_detail::sw_<V,qvm_detail::swizzle_idx<-1,qvm_detail::swizzle_idx<-1,qvm_detail::swizzle_idx<3 > > > > &>(a);
}
template <class V>
BOOST_QVM_INLINE_TRIVIAL
typename enable_if_c<
is_vec<V>::value && vec_traits<V>::dim>=4,
qvm_detail::sw_<V,qvm_detail::swizzle_idx<3,qvm_detail::swizzle_idx<-1,qvm_detail::swizzle_idx<3 > > > > const &>::type
W0W( V const & a )
{
return reinterpret_cast<qvm_detail::sw_<V,qvm_detail::swizzle_idx<3,qvm_detail::swizzle_idx<-1,qvm_detail::swizzle_idx<3 > > > > const &>(a);
}
template <class V>
BOOST_QVM_INLINE_TRIVIAL
typename enable_if_c<
is_vec<V>::value && vec_traits<V>::dim>=4,
qvm_detail::sw_<V,qvm_detail::swizzle_idx<3,qvm_detail::swizzle_idx<-1,qvm_detail::swizzle_idx<3 > > > > &>::type
W0W( V & a )
{
return reinterpret_cast<qvm_detail::sw_<V,qvm_detail::swizzle_idx<3,qvm_detail::swizzle_idx<-1,qvm_detail::swizzle_idx<3 > > > > &>(a);
}
template <class V>
BOOST_QVM_INLINE_TRIVIAL
typename enable_if_c<
is_vec<V>::value && vec_traits<V>::dim>=4,
qvm_detail::sw_<V,qvm_detail::swizzle_idx<2,qvm_detail::swizzle_idx<-1,qvm_detail::swizzle_idx<3 > > > > const &>::type
Z0W( V const & a )
{
return reinterpret_cast<qvm_detail::sw_<V,qvm_detail::swizzle_idx<2,qvm_detail::swizzle_idx<-1,qvm_detail::swizzle_idx<3 > > > > const &>(a);
}
template <class V>
BOOST_QVM_INLINE_TRIVIAL
typename enable_if_c<
is_vec<V>::value && vec_traits<V>::dim>=4,
qvm_detail::sw_<V,qvm_detail::swizzle_idx<2,qvm_detail::swizzle_idx<-1,qvm_detail::swizzle_idx<3 > > > > &>::type
Z0W( V & a )
{
return reinterpret_cast<qvm_detail::sw_<V,qvm_detail::swizzle_idx<2,qvm_detail::swizzle_idx<-1,qvm_detail::swizzle_idx<3 > > > > &>(a);
}
template <class V>
BOOST_QVM_INLINE_TRIVIAL
typename enable_if_c<
is_vec<V>::value && vec_traits<V>::dim>=4,
qvm_detail::sw_<V,qvm_detail::swizzle_idx<1,qvm_detail::swizzle_idx<-1,qvm_detail::swizzle_idx<3 > > > > const &>::type
Y0W( V const & a )
{
return reinterpret_cast<qvm_detail::sw_<V,qvm_detail::swizzle_idx<1,qvm_detail::swizzle_idx<-1,qvm_detail::swizzle_idx<3 > > > > const &>(a);
}
template <class V>
BOOST_QVM_INLINE_TRIVIAL
typename enable_if_c<
is_vec<V>::value && vec_traits<V>::dim>=4,
qvm_detail::sw_<V,qvm_detail::swizzle_idx<1,qvm_detail::swizzle_idx<-1,qvm_detail::swizzle_idx<3 > > > > &>::type
Y0W( V & a )
{
return reinterpret_cast<qvm_detail::sw_<V,qvm_detail::swizzle_idx<1,qvm_detail::swizzle_idx<-1,qvm_detail::swizzle_idx<3 > > > > &>(a);
}
template <class V>
BOOST_QVM_INLINE_TRIVIAL
typename enable_if_c<
is_vec<V>::value && vec_traits<V>::dim>=4,
qvm_detail::sw_<V,qvm_detail::swizzle_idx<0,qvm_detail::swizzle_idx<-1,qvm_detail::swizzle_idx<3 > > > > const &>::type
X0W( V const & a )
{
return reinterpret_cast<qvm_detail::sw_<V,qvm_detail::swizzle_idx<0,qvm_detail::swizzle_idx<-1,qvm_detail::swizzle_idx<3 > > > > const &>(a);
}
template <class V>
BOOST_QVM_INLINE_TRIVIAL
typename enable_if_c<
is_vec<V>::value && vec_traits<V>::dim>=4,
qvm_detail::sw_<V,qvm_detail::swizzle_idx<0,qvm_detail::swizzle_idx<-1,qvm_detail::swizzle_idx<3 > > > > &>::type
X0W( V & a )
{
return reinterpret_cast<qvm_detail::sw_<V,qvm_detail::swizzle_idx<0,qvm_detail::swizzle_idx<-1,qvm_detail::swizzle_idx<3 > > > > &>(a);
}
template <class V>
BOOST_QVM_INLINE_TRIVIAL
typename enable_if_c<
is_vec<V>::value && vec_traits<V>::dim>=4,
qvm_detail::sw_<V,qvm_detail::swizzle_idx<-2,qvm_detail::swizzle_idx<3,qvm_detail::swizzle_idx<3 > > > > const &>::type
_1WW( V const & a )
{
return reinterpret_cast<qvm_detail::sw_<V,qvm_detail::swizzle_idx<-2,qvm_detail::swizzle_idx<3,qvm_detail::swizzle_idx<3 > > > > const &>(a);
}
template <class V>
BOOST_QVM_INLINE_TRIVIAL
typename enable_if_c<
is_vec<V>::value && vec_traits<V>::dim>=4,
qvm_detail::sw_<V,qvm_detail::swizzle_idx<-2,qvm_detail::swizzle_idx<3,qvm_detail::swizzle_idx<3 > > > > &>::type
_1WW( V & a )
{
return reinterpret_cast<qvm_detail::sw_<V,qvm_detail::swizzle_idx<-2,qvm_detail::swizzle_idx<3,qvm_detail::swizzle_idx<3 > > > > &>(a);
}
template <class V>
BOOST_QVM_INLINE_TRIVIAL
typename enable_if_c<
is_vec<V>::value && vec_traits<V>::dim>=4,
qvm_detail::sw_<V,qvm_detail::swizzle_idx<-1,qvm_detail::swizzle_idx<3,qvm_detail::swizzle_idx<3 > > > > const &>::type
_0WW( V const & a )
{
return reinterpret_cast<qvm_detail::sw_<V,qvm_detail::swizzle_idx<-1,qvm_detail::swizzle_idx<3,qvm_detail::swizzle_idx<3 > > > > const &>(a);
}
template <class V>
BOOST_QVM_INLINE_TRIVIAL
typename enable_if_c<
is_vec<V>::value && vec_traits<V>::dim>=4,
qvm_detail::sw_<V,qvm_detail::swizzle_idx<-1,qvm_detail::swizzle_idx<3,qvm_detail::swizzle_idx<3 > > > > &>::type
_0WW( V & a )
{
return reinterpret_cast<qvm_detail::sw_<V,qvm_detail::swizzle_idx<-1,qvm_detail::swizzle_idx<3,qvm_detail::swizzle_idx<3 > > > > &>(a);
}
template <class V>
BOOST_QVM_INLINE_TRIVIAL
typename enable_if_c<
is_vec<V>::value && vec_traits<V>::dim>=4,
qvm_detail::sw_<V,qvm_detail::swizzle_idx<3,qvm_detail::swizzle_idx<3,qvm_detail::swizzle_idx<3 > > > > const &>::type
WWW( V const & a )
{
return reinterpret_cast<qvm_detail::sw_<V,qvm_detail::swizzle_idx<3,qvm_detail::swizzle_idx<3,qvm_detail::swizzle_idx<3 > > > > const &>(a);
}
template <class V>
BOOST_QVM_INLINE_TRIVIAL
typename enable_if_c<
is_vec<V>::value && vec_traits<V>::dim>=4,
qvm_detail::sw_<V,qvm_detail::swizzle_idx<3,qvm_detail::swizzle_idx<3,qvm_detail::swizzle_idx<3 > > > > &>::type
WWW( V & a )
{
return reinterpret_cast<qvm_detail::sw_<V,qvm_detail::swizzle_idx<3,qvm_detail::swizzle_idx<3,qvm_detail::swizzle_idx<3 > > > > &>(a);
}
template <class V>
BOOST_QVM_INLINE_TRIVIAL
typename enable_if_c<
is_vec<V>::value && vec_traits<V>::dim>=4,
qvm_detail::sw_<V,qvm_detail::swizzle_idx<2,qvm_detail::swizzle_idx<3,qvm_detail::swizzle_idx<3 > > > > const &>::type
ZWW( V const & a )
{
return reinterpret_cast<qvm_detail::sw_<V,qvm_detail::swizzle_idx<2,qvm_detail::swizzle_idx<3,qvm_detail::swizzle_idx<3 > > > > const &>(a);
}
template <class V>
BOOST_QVM_INLINE_TRIVIAL
typename enable_if_c<
is_vec<V>::value && vec_traits<V>::dim>=4,
qvm_detail::sw_<V,qvm_detail::swizzle_idx<2,qvm_detail::swizzle_idx<3,qvm_detail::swizzle_idx<3 > > > > &>::type
ZWW( V & a )
{
return reinterpret_cast<qvm_detail::sw_<V,qvm_detail::swizzle_idx<2,qvm_detail::swizzle_idx<3,qvm_detail::swizzle_idx<3 > > > > &>(a);
}
template <class V>
BOOST_QVM_INLINE_TRIVIAL
typename enable_if_c<
is_vec<V>::value && vec_traits<V>::dim>=4,
qvm_detail::sw_<V,qvm_detail::swizzle_idx<1,qvm_detail::swizzle_idx<3,qvm_detail::swizzle_idx<3 > > > > const &>::type
YWW( V const & a )
{
return reinterpret_cast<qvm_detail::sw_<V,qvm_detail::swizzle_idx<1,qvm_detail::swizzle_idx<3,qvm_detail::swizzle_idx<3 > > > > const &>(a);
}
template <class V>
BOOST_QVM_INLINE_TRIVIAL
typename enable_if_c<
is_vec<V>::value && vec_traits<V>::dim>=4,
qvm_detail::sw_<V,qvm_detail::swizzle_idx<1,qvm_detail::swizzle_idx<3,qvm_detail::swizzle_idx<3 > > > > &>::type
YWW( V & a )
{
return reinterpret_cast<qvm_detail::sw_<V,qvm_detail::swizzle_idx<1,qvm_detail::swizzle_idx<3,qvm_detail::swizzle_idx<3 > > > > &>(a);
}
template <class V>
BOOST_QVM_INLINE_TRIVIAL
typename enable_if_c<
is_vec<V>::value && vec_traits<V>::dim>=4,
qvm_detail::sw_<V,qvm_detail::swizzle_idx<0,qvm_detail::swizzle_idx<3,qvm_detail::swizzle_idx<3 > > > > const &>::type
XWW( V const & a )
{
return reinterpret_cast<qvm_detail::sw_<V,qvm_detail::swizzle_idx<0,qvm_detail::swizzle_idx<3,qvm_detail::swizzle_idx<3 > > > > const &>(a);
}
template <class V>
BOOST_QVM_INLINE_TRIVIAL
typename enable_if_c<
is_vec<V>::value && vec_traits<V>::dim>=4,
qvm_detail::sw_<V,qvm_detail::swizzle_idx<0,qvm_detail::swizzle_idx<3,qvm_detail::swizzle_idx<3 > > > > &>::type
XWW( V & a )
{
return reinterpret_cast<qvm_detail::sw_<V,qvm_detail::swizzle_idx<0,qvm_detail::swizzle_idx<3,qvm_detail::swizzle_idx<3 > > > > &>(a);
}
template <class V>
BOOST_QVM_INLINE_TRIVIAL
typename enable_if_c<
is_vec<V>::value && vec_traits<V>::dim>=4,
qvm_detail::sw_<V,qvm_detail::swizzle_idx<-2,qvm_detail::swizzle_idx<2,qvm_detail::swizzle_idx<3 > > > > const &>::type
_1ZW( V const & a )
{
return reinterpret_cast<qvm_detail::sw_<V,qvm_detail::swizzle_idx<-2,qvm_detail::swizzle_idx<2,qvm_detail::swizzle_idx<3 > > > > const &>(a);
}
template <class V>
BOOST_QVM_INLINE_TRIVIAL
typename enable_if_c<
is_vec<V>::value && vec_traits<V>::dim>=4,
qvm_detail::sw_<V,qvm_detail::swizzle_idx<-2,qvm_detail::swizzle_idx<2,qvm_detail::swizzle_idx<3 > > > > &>::type
_1ZW( V & a )
{
return reinterpret_cast<qvm_detail::sw_<V,qvm_detail::swizzle_idx<-2,qvm_detail::swizzle_idx<2,qvm_detail::swizzle_idx<3 > > > > &>(a);
}
template <class V>
BOOST_QVM_INLINE_TRIVIAL
typename enable_if_c<
is_vec<V>::value && vec_traits<V>::dim>=4,
qvm_detail::sw_<V,qvm_detail::swizzle_idx<-1,qvm_detail::swizzle_idx<2,qvm_detail::swizzle_idx<3 > > > > const &>::type
_0ZW( V const & a )
{
return reinterpret_cast<qvm_detail::sw_<V,qvm_detail::swizzle_idx<-1,qvm_detail::swizzle_idx<2,qvm_detail::swizzle_idx<3 > > > > const &>(a);
}
template <class V>
BOOST_QVM_INLINE_TRIVIAL
typename enable_if_c<
is_vec<V>::value && vec_traits<V>::dim>=4,
qvm_detail::sw_<V,qvm_detail::swizzle_idx<-1,qvm_detail::swizzle_idx<2,qvm_detail::swizzle_idx<3 > > > > &>::type
_0ZW( V & a )
{
return reinterpret_cast<qvm_detail::sw_<V,qvm_detail::swizzle_idx<-1,qvm_detail::swizzle_idx<2,qvm_detail::swizzle_idx<3 > > > > &>(a);
}
template <class V>
BOOST_QVM_INLINE_TRIVIAL
typename enable_if_c<
is_vec<V>::value && vec_traits<V>::dim>=4,
qvm_detail::sw_<V,qvm_detail::swizzle_idx<3,qvm_detail::swizzle_idx<2,qvm_detail::swizzle_idx<3 > > > > const &>::type
WZW( V const & a )
{
return reinterpret_cast<qvm_detail::sw_<V,qvm_detail::swizzle_idx<3,qvm_detail::swizzle_idx<2,qvm_detail::swizzle_idx<3 > > > > const &>(a);
}
template <class V>
BOOST_QVM_INLINE_TRIVIAL
typename enable_if_c<
is_vec<V>::value && vec_traits<V>::dim>=4,
qvm_detail::sw_<V,qvm_detail::swizzle_idx<3,qvm_detail::swizzle_idx<2,qvm_detail::swizzle_idx<3 > > > > &>::type
WZW( V & a )
{
return reinterpret_cast<qvm_detail::sw_<V,qvm_detail::swizzle_idx<3,qvm_detail::swizzle_idx<2,qvm_detail::swizzle_idx<3 > > > > &>(a);
}
template <class V>
BOOST_QVM_INLINE_TRIVIAL
typename enable_if_c<
is_vec<V>::value && vec_traits<V>::dim>=4,
qvm_detail::sw_<V,qvm_detail::swizzle_idx<2,qvm_detail::swizzle_idx<2,qvm_detail::swizzle_idx<3 > > > > const &>::type
ZZW( V const & a )
{
return reinterpret_cast<qvm_detail::sw_<V,qvm_detail::swizzle_idx<2,qvm_detail::swizzle_idx<2,qvm_detail::swizzle_idx<3 > > > > const &>(a);
}
template <class V>
BOOST_QVM_INLINE_TRIVIAL
typename enable_if_c<
is_vec<V>::value && vec_traits<V>::dim>=4,
qvm_detail::sw_<V,qvm_detail::swizzle_idx<2,qvm_detail::swizzle_idx<2,qvm_detail::swizzle_idx<3 > > > > &>::type
ZZW( V & a )
{
return reinterpret_cast<qvm_detail::sw_<V,qvm_detail::swizzle_idx<2,qvm_detail::swizzle_idx<2,qvm_detail::swizzle_idx<3 > > > > &>(a);
}
template <class V>
BOOST_QVM_INLINE_TRIVIAL
typename enable_if_c<
is_vec<V>::value && vec_traits<V>::dim>=4,
qvm_detail::sw_<V,qvm_detail::swizzle_idx<1,qvm_detail::swizzle_idx<2,qvm_detail::swizzle_idx<3 > > > > const &>::type
YZW( V const & a )
{
return reinterpret_cast<qvm_detail::sw_<V,qvm_detail::swizzle_idx<1,qvm_detail::swizzle_idx<2,qvm_detail::swizzle_idx<3 > > > > const &>(a);
}
template <class V>
BOOST_QVM_INLINE_TRIVIAL
typename enable_if_c<
is_vec<V>::value && vec_traits<V>::dim>=4,
qvm_detail::sw_<V,qvm_detail::swizzle_idx<1,qvm_detail::swizzle_idx<2,qvm_detail::swizzle_idx<3 > > > > &>::type
YZW( V & a )
{
return reinterpret_cast<qvm_detail::sw_<V,qvm_detail::swizzle_idx<1,qvm_detail::swizzle_idx<2,qvm_detail::swizzle_idx<3 > > > > &>(a);
}
template <class V>
BOOST_QVM_INLINE_TRIVIAL
typename enable_if_c<
is_vec<V>::value && vec_traits<V>::dim>=4,
qvm_detail::sw_<V,qvm_detail::swizzle_idx<0,qvm_detail::swizzle_idx<2,qvm_detail::swizzle_idx<3 > > > > const &>::type
XZW( V const & a )
{
return reinterpret_cast<qvm_detail::sw_<V,qvm_detail::swizzle_idx<0,qvm_detail::swizzle_idx<2,qvm_detail::swizzle_idx<3 > > > > const &>(a);
}
template <class V>
BOOST_QVM_INLINE_TRIVIAL
typename enable_if_c<
is_vec<V>::value && vec_traits<V>::dim>=4,
qvm_detail::sw_<V,qvm_detail::swizzle_idx<0,qvm_detail::swizzle_idx<2,qvm_detail::swizzle_idx<3 > > > > &>::type
XZW( V & a )
{
return reinterpret_cast<qvm_detail::sw_<V,qvm_detail::swizzle_idx<0,qvm_detail::swizzle_idx<2,qvm_detail::swizzle_idx<3 > > > > &>(a);
}
template <class V>
BOOST_QVM_INLINE_TRIVIAL
typename enable_if_c<
is_vec<V>::value && vec_traits<V>::dim>=4,
qvm_detail::sw_<V,qvm_detail::swizzle_idx<-2,qvm_detail::swizzle_idx<1,qvm_detail::swizzle_idx<3 > > > > const &>::type
_1YW( V const & a )
{
return reinterpret_cast<qvm_detail::sw_<V,qvm_detail::swizzle_idx<-2,qvm_detail::swizzle_idx<1,qvm_detail::swizzle_idx<3 > > > > const &>(a);
}
template <class V>
BOOST_QVM_INLINE_TRIVIAL
typename enable_if_c<
is_vec<V>::value && vec_traits<V>::dim>=4,
qvm_detail::sw_<V,qvm_detail::swizzle_idx<-2,qvm_detail::swizzle_idx<1,qvm_detail::swizzle_idx<3 > > > > &>::type
_1YW( V & a )
{
return reinterpret_cast<qvm_detail::sw_<V,qvm_detail::swizzle_idx<-2,qvm_detail::swizzle_idx<1,qvm_detail::swizzle_idx<3 > > > > &>(a);
}
template <class V>
BOOST_QVM_INLINE_TRIVIAL
typename enable_if_c<
is_vec<V>::value && vec_traits<V>::dim>=4,
qvm_detail::sw_<V,qvm_detail::swizzle_idx<-1,qvm_detail::swizzle_idx<1,qvm_detail::swizzle_idx<3 > > > > const &>::type
_0YW( V const & a )
{
return reinterpret_cast<qvm_detail::sw_<V,qvm_detail::swizzle_idx<-1,qvm_detail::swizzle_idx<1,qvm_detail::swizzle_idx<3 > > > > const &>(a);
}
template <class V>
BOOST_QVM_INLINE_TRIVIAL
typename enable_if_c<
is_vec<V>::value && vec_traits<V>::dim>=4,
qvm_detail::sw_<V,qvm_detail::swizzle_idx<-1,qvm_detail::swizzle_idx<1,qvm_detail::swizzle_idx<3 > > > > &>::type
_0YW( V & a )
{
return reinterpret_cast<qvm_detail::sw_<V,qvm_detail::swizzle_idx<-1,qvm_detail::swizzle_idx<1,qvm_detail::swizzle_idx<3 > > > > &>(a);
}
template <class V>
BOOST_QVM_INLINE_TRIVIAL
typename enable_if_c<
is_vec<V>::value && vec_traits<V>::dim>=4,
qvm_detail::sw_<V,qvm_detail::swizzle_idx<3,qvm_detail::swizzle_idx<1,qvm_detail::swizzle_idx<3 > > > > const &>::type
WYW( V const & a )
{
return reinterpret_cast<qvm_detail::sw_<V,qvm_detail::swizzle_idx<3,qvm_detail::swizzle_idx<1,qvm_detail::swizzle_idx<3 > > > > const &>(a);
}
template <class V>
BOOST_QVM_INLINE_TRIVIAL
typename enable_if_c<
is_vec<V>::value && vec_traits<V>::dim>=4,
qvm_detail::sw_<V,qvm_detail::swizzle_idx<3,qvm_detail::swizzle_idx<1,qvm_detail::swizzle_idx<3 > > > > &>::type
WYW( V & a )
{
return reinterpret_cast<qvm_detail::sw_<V,qvm_detail::swizzle_idx<3,qvm_detail::swizzle_idx<1,qvm_detail::swizzle_idx<3 > > > > &>(a);
}
template <class V>
BOOST_QVM_INLINE_TRIVIAL
typename enable_if_c<
is_vec<V>::value && vec_traits<V>::dim>=4,
qvm_detail::sw_<V,qvm_detail::swizzle_idx<2,qvm_detail::swizzle_idx<1,qvm_detail::swizzle_idx<3 > > > > const &>::type
ZYW( V const & a )
{
return reinterpret_cast<qvm_detail::sw_<V,qvm_detail::swizzle_idx<2,qvm_detail::swizzle_idx<1,qvm_detail::swizzle_idx<3 > > > > const &>(a);
}
template <class V>
BOOST_QVM_INLINE_TRIVIAL
typename enable_if_c<
is_vec<V>::value && vec_traits<V>::dim>=4,
qvm_detail::sw_<V,qvm_detail::swizzle_idx<2,qvm_detail::swizzle_idx<1,qvm_detail::swizzle_idx<3 > > > > &>::type
ZYW( V & a )
{
return reinterpret_cast<qvm_detail::sw_<V,qvm_detail::swizzle_idx<2,qvm_detail::swizzle_idx<1,qvm_detail::swizzle_idx<3 > > > > &>(a);
}
template <class V>
BOOST_QVM_INLINE_TRIVIAL
typename enable_if_c<
is_vec<V>::value && vec_traits<V>::dim>=4,
qvm_detail::sw_<V,qvm_detail::swizzle_idx<1,qvm_detail::swizzle_idx<1,qvm_detail::swizzle_idx<3 > > > > const &>::type
YYW( V const & a )
{
return reinterpret_cast<qvm_detail::sw_<V,qvm_detail::swizzle_idx<1,qvm_detail::swizzle_idx<1,qvm_detail::swizzle_idx<3 > > > > const &>(a);
}
template <class V>
BOOST_QVM_INLINE_TRIVIAL
typename enable_if_c<
is_vec<V>::value && vec_traits<V>::dim>=4,
qvm_detail::sw_<V,qvm_detail::swizzle_idx<1,qvm_detail::swizzle_idx<1,qvm_detail::swizzle_idx<3 > > > > &>::type
YYW( V & a )
{
return reinterpret_cast<qvm_detail::sw_<V,qvm_detail::swizzle_idx<1,qvm_detail::swizzle_idx<1,qvm_detail::swizzle_idx<3 > > > > &>(a);
}
template <class V>
BOOST_QVM_INLINE_TRIVIAL
typename enable_if_c<
is_vec<V>::value && vec_traits<V>::dim>=4,
qvm_detail::sw_<V,qvm_detail::swizzle_idx<0,qvm_detail::swizzle_idx<1,qvm_detail::swizzle_idx<3 > > > > const &>::type
XYW( V const & a )
{
return reinterpret_cast<qvm_detail::sw_<V,qvm_detail::swizzle_idx<0,qvm_detail::swizzle_idx<1,qvm_detail::swizzle_idx<3 > > > > const &>(a);
}
template <class V>
BOOST_QVM_INLINE_TRIVIAL
typename enable_if_c<
is_vec<V>::value && vec_traits<V>::dim>=4,
qvm_detail::sw_<V,qvm_detail::swizzle_idx<0,qvm_detail::swizzle_idx<1,qvm_detail::swizzle_idx<3 > > > > &>::type
XYW( V & a )
{
return reinterpret_cast<qvm_detail::sw_<V,qvm_detail::swizzle_idx<0,qvm_detail::swizzle_idx<1,qvm_detail::swizzle_idx<3 > > > > &>(a);
}
template <class V>
BOOST_QVM_INLINE_TRIVIAL
typename enable_if_c<
is_vec<V>::value && vec_traits<V>::dim>=4,
qvm_detail::sw_<V,qvm_detail::swizzle_idx<-2,qvm_detail::swizzle_idx<0,qvm_detail::swizzle_idx<3 > > > > const &>::type
_1XW( V const & a )
{
return reinterpret_cast<qvm_detail::sw_<V,qvm_detail::swizzle_idx<-2,qvm_detail::swizzle_idx<0,qvm_detail::swizzle_idx<3 > > > > const &>(a);
}
template <class V>
BOOST_QVM_INLINE_TRIVIAL
typename enable_if_c<
is_vec<V>::value && vec_traits<V>::dim>=4,
qvm_detail::sw_<V,qvm_detail::swizzle_idx<-2,qvm_detail::swizzle_idx<0,qvm_detail::swizzle_idx<3 > > > > &>::type
_1XW( V & a )
{
return reinterpret_cast<qvm_detail::sw_<V,qvm_detail::swizzle_idx<-2,qvm_detail::swizzle_idx<0,qvm_detail::swizzle_idx<3 > > > > &>(a);
}
template <class V>
BOOST_QVM_INLINE_TRIVIAL
typename enable_if_c<
is_vec<V>::value && vec_traits<V>::dim>=4,
qvm_detail::sw_<V,qvm_detail::swizzle_idx<-1,qvm_detail::swizzle_idx<0,qvm_detail::swizzle_idx<3 > > > > const &>::type
_0XW( V const & a )
{
return reinterpret_cast<qvm_detail::sw_<V,qvm_detail::swizzle_idx<-1,qvm_detail::swizzle_idx<0,qvm_detail::swizzle_idx<3 > > > > const &>(a);
}
template <class V>
BOOST_QVM_INLINE_TRIVIAL
typename enable_if_c<
is_vec<V>::value && vec_traits<V>::dim>=4,
qvm_detail::sw_<V,qvm_detail::swizzle_idx<-1,qvm_detail::swizzle_idx<0,qvm_detail::swizzle_idx<3 > > > > &>::type
_0XW( V & a )
{
return reinterpret_cast<qvm_detail::sw_<V,qvm_detail::swizzle_idx<-1,qvm_detail::swizzle_idx<0,qvm_detail::swizzle_idx<3 > > > > &>(a);
}
template <class V>
BOOST_QVM_INLINE_TRIVIAL
typename enable_if_c<
is_vec<V>::value && vec_traits<V>::dim>=4,
qvm_detail::sw_<V,qvm_detail::swizzle_idx<3,qvm_detail::swizzle_idx<0,qvm_detail::swizzle_idx<3 > > > > const &>::type
WXW( V const & a )
{
return reinterpret_cast<qvm_detail::sw_<V,qvm_detail::swizzle_idx<3,qvm_detail::swizzle_idx<0,qvm_detail::swizzle_idx<3 > > > > const &>(a);
}
template <class V>
BOOST_QVM_INLINE_TRIVIAL
typename enable_if_c<
is_vec<V>::value && vec_traits<V>::dim>=4,
qvm_detail::sw_<V,qvm_detail::swizzle_idx<3,qvm_detail::swizzle_idx<0,qvm_detail::swizzle_idx<3 > > > > &>::type
WXW( V & a )
{
return reinterpret_cast<qvm_detail::sw_<V,qvm_detail::swizzle_idx<3,qvm_detail::swizzle_idx<0,qvm_detail::swizzle_idx<3 > > > > &>(a);
}
template <class V>
BOOST_QVM_INLINE_TRIVIAL
typename enable_if_c<
is_vec<V>::value && vec_traits<V>::dim>=4,
qvm_detail::sw_<V,qvm_detail::swizzle_idx<2,qvm_detail::swizzle_idx<0,qvm_detail::swizzle_idx<3 > > > > const &>::type
ZXW( V const & a )
{
return reinterpret_cast<qvm_detail::sw_<V,qvm_detail::swizzle_idx<2,qvm_detail::swizzle_idx<0,qvm_detail::swizzle_idx<3 > > > > const &>(a);
}
template <class V>
BOOST_QVM_INLINE_TRIVIAL
typename enable_if_c<
is_vec<V>::value && vec_traits<V>::dim>=4,
qvm_detail::sw_<V,qvm_detail::swizzle_idx<2,qvm_detail::swizzle_idx<0,qvm_detail::swizzle_idx<3 > > > > &>::type
ZXW( V & a )
{
return reinterpret_cast<qvm_detail::sw_<V,qvm_detail::swizzle_idx<2,qvm_detail::swizzle_idx<0,qvm_detail::swizzle_idx<3 > > > > &>(a);
}
template <class V>
BOOST_QVM_INLINE_TRIVIAL
typename enable_if_c<
is_vec<V>::value && vec_traits<V>::dim>=4,
qvm_detail::sw_<V,qvm_detail::swizzle_idx<1,qvm_detail::swizzle_idx<0,qvm_detail::swizzle_idx<3 > > > > const &>::type
YXW( V const & a )
{
return reinterpret_cast<qvm_detail::sw_<V,qvm_detail::swizzle_idx<1,qvm_detail::swizzle_idx<0,qvm_detail::swizzle_idx<3 > > > > const &>(a);
}
template <class V>
BOOST_QVM_INLINE_TRIVIAL
typename enable_if_c<
is_vec<V>::value && vec_traits<V>::dim>=4,
qvm_detail::sw_<V,qvm_detail::swizzle_idx<1,qvm_detail::swizzle_idx<0,qvm_detail::swizzle_idx<3 > > > > &>::type
YXW( V & a )
{
return reinterpret_cast<qvm_detail::sw_<V,qvm_detail::swizzle_idx<1,qvm_detail::swizzle_idx<0,qvm_detail::swizzle_idx<3 > > > > &>(a);
}
template <class V>
BOOST_QVM_INLINE_TRIVIAL
typename enable_if_c<
is_vec<V>::value && vec_traits<V>::dim>=4,
qvm_detail::sw_<V,qvm_detail::swizzle_idx<0,qvm_detail::swizzle_idx<0,qvm_detail::swizzle_idx<3 > > > > const &>::type
XXW( V const & a )
{
return reinterpret_cast<qvm_detail::sw_<V,qvm_detail::swizzle_idx<0,qvm_detail::swizzle_idx<0,qvm_detail::swizzle_idx<3 > > > > const &>(a);
}
template <class V>
BOOST_QVM_INLINE_TRIVIAL
typename enable_if_c<
is_vec<V>::value && vec_traits<V>::dim>=4,
qvm_detail::sw_<V,qvm_detail::swizzle_idx<0,qvm_detail::swizzle_idx<0,qvm_detail::swizzle_idx<3 > > > > &>::type
XXW( V & a )
{
return reinterpret_cast<qvm_detail::sw_<V,qvm_detail::swizzle_idx<0,qvm_detail::swizzle_idx<0,qvm_detail::swizzle_idx<3 > > > > &>(a);
}
template <class V>
BOOST_QVM_INLINE_TRIVIAL
typename enable_if_c<
is_vec<V>::value && vec_traits<V>::dim>=3,
qvm_detail::sw_<V,qvm_detail::swizzle_idx<-2,qvm_detail::swizzle_idx<-2,qvm_detail::swizzle_idx<2 > > > > const &>::type
_11Z( V const & a )
{
return reinterpret_cast<qvm_detail::sw_<V,qvm_detail::swizzle_idx<-2,qvm_detail::swizzle_idx<-2,qvm_detail::swizzle_idx<2 > > > > const &>(a);
}
template <class V>
BOOST_QVM_INLINE_TRIVIAL
typename enable_if_c<
is_vec<V>::value && vec_traits<V>::dim>=3,
qvm_detail::sw_<V,qvm_detail::swizzle_idx<-2,qvm_detail::swizzle_idx<-2,qvm_detail::swizzle_idx<2 > > > > &>::type
_11Z( V & a )
{
return reinterpret_cast<qvm_detail::sw_<V,qvm_detail::swizzle_idx<-2,qvm_detail::swizzle_idx<-2,qvm_detail::swizzle_idx<2 > > > > &>(a);
}
template <class V>
BOOST_QVM_INLINE_TRIVIAL
typename enable_if_c<
is_vec<V>::value && vec_traits<V>::dim>=3,
qvm_detail::sw_<V,qvm_detail::swizzle_idx<-1,qvm_detail::swizzle_idx<-2,qvm_detail::swizzle_idx<2 > > > > const &>::type
_01Z( V const & a )
{
return reinterpret_cast<qvm_detail::sw_<V,qvm_detail::swizzle_idx<-1,qvm_detail::swizzle_idx<-2,qvm_detail::swizzle_idx<2 > > > > const &>(a);
}
template <class V>
BOOST_QVM_INLINE_TRIVIAL
typename enable_if_c<
is_vec<V>::value && vec_traits<V>::dim>=3,
qvm_detail::sw_<V,qvm_detail::swizzle_idx<-1,qvm_detail::swizzle_idx<-2,qvm_detail::swizzle_idx<2 > > > > &>::type
_01Z( V & a )
{
return reinterpret_cast<qvm_detail::sw_<V,qvm_detail::swizzle_idx<-1,qvm_detail::swizzle_idx<-2,qvm_detail::swizzle_idx<2 > > > > &>(a);
}
template <class V>
BOOST_QVM_INLINE_TRIVIAL
typename enable_if_c<
is_vec<V>::value && vec_traits<V>::dim>=4,
qvm_detail::sw_<V,qvm_detail::swizzle_idx<3,qvm_detail::swizzle_idx<-2,qvm_detail::swizzle_idx<2 > > > > const &>::type
W1Z( V const & a )
{
return reinterpret_cast<qvm_detail::sw_<V,qvm_detail::swizzle_idx<3,qvm_detail::swizzle_idx<-2,qvm_detail::swizzle_idx<2 > > > > const &>(a);
}
template <class V>
BOOST_QVM_INLINE_TRIVIAL
typename enable_if_c<
is_vec<V>::value && vec_traits<V>::dim>=4,
qvm_detail::sw_<V,qvm_detail::swizzle_idx<3,qvm_detail::swizzle_idx<-2,qvm_detail::swizzle_idx<2 > > > > &>::type
W1Z( V & a )
{
return reinterpret_cast<qvm_detail::sw_<V,qvm_detail::swizzle_idx<3,qvm_detail::swizzle_idx<-2,qvm_detail::swizzle_idx<2 > > > > &>(a);
}
template <class V>
BOOST_QVM_INLINE_TRIVIAL
typename enable_if_c<
is_vec<V>::value && vec_traits<V>::dim>=3,
qvm_detail::sw_<V,qvm_detail::swizzle_idx<2,qvm_detail::swizzle_idx<-2,qvm_detail::swizzle_idx<2 > > > > const &>::type
Z1Z( V const & a )
{
return reinterpret_cast<qvm_detail::sw_<V,qvm_detail::swizzle_idx<2,qvm_detail::swizzle_idx<-2,qvm_detail::swizzle_idx<2 > > > > const &>(a);
}
template <class V>
BOOST_QVM_INLINE_TRIVIAL
typename enable_if_c<
is_vec<V>::value && vec_traits<V>::dim>=3,
qvm_detail::sw_<V,qvm_detail::swizzle_idx<2,qvm_detail::swizzle_idx<-2,qvm_detail::swizzle_idx<2 > > > > &>::type
Z1Z( V & a )
{
return reinterpret_cast<qvm_detail::sw_<V,qvm_detail::swizzle_idx<2,qvm_detail::swizzle_idx<-2,qvm_detail::swizzle_idx<2 > > > > &>(a);
}
template <class V>
BOOST_QVM_INLINE_TRIVIAL
typename enable_if_c<
is_vec<V>::value && vec_traits<V>::dim>=3,
qvm_detail::sw_<V,qvm_detail::swizzle_idx<1,qvm_detail::swizzle_idx<-2,qvm_detail::swizzle_idx<2 > > > > const &>::type
Y1Z( V const & a )
{
return reinterpret_cast<qvm_detail::sw_<V,qvm_detail::swizzle_idx<1,qvm_detail::swizzle_idx<-2,qvm_detail::swizzle_idx<2 > > > > const &>(a);
}
template <class V>
BOOST_QVM_INLINE_TRIVIAL
typename enable_if_c<
is_vec<V>::value && vec_traits<V>::dim>=3,
qvm_detail::sw_<V,qvm_detail::swizzle_idx<1,qvm_detail::swizzle_idx<-2,qvm_detail::swizzle_idx<2 > > > > &>::type
Y1Z( V & a )
{
return reinterpret_cast<qvm_detail::sw_<V,qvm_detail::swizzle_idx<1,qvm_detail::swizzle_idx<-2,qvm_detail::swizzle_idx<2 > > > > &>(a);
}
template <class V>
BOOST_QVM_INLINE_TRIVIAL
typename enable_if_c<
is_vec<V>::value && vec_traits<V>::dim>=3,
qvm_detail::sw_<V,qvm_detail::swizzle_idx<0,qvm_detail::swizzle_idx<-2,qvm_detail::swizzle_idx<2 > > > > const &>::type
X1Z( V const & a )
{
return reinterpret_cast<qvm_detail::sw_<V,qvm_detail::swizzle_idx<0,qvm_detail::swizzle_idx<-2,qvm_detail::swizzle_idx<2 > > > > const &>(a);
}
template <class V>
BOOST_QVM_INLINE_TRIVIAL
typename enable_if_c<
is_vec<V>::value && vec_traits<V>::dim>=3,
qvm_detail::sw_<V,qvm_detail::swizzle_idx<0,qvm_detail::swizzle_idx<-2,qvm_detail::swizzle_idx<2 > > > > &>::type
X1Z( V & a )
{
return reinterpret_cast<qvm_detail::sw_<V,qvm_detail::swizzle_idx<0,qvm_detail::swizzle_idx<-2,qvm_detail::swizzle_idx<2 > > > > &>(a);
}
template <class V>
BOOST_QVM_INLINE_TRIVIAL
typename enable_if_c<
is_vec<V>::value && vec_traits<V>::dim>=3,
qvm_detail::sw_<V,qvm_detail::swizzle_idx<-2,qvm_detail::swizzle_idx<-1,qvm_detail::swizzle_idx<2 > > > > const &>::type
_10Z( V const & a )
{
return reinterpret_cast<qvm_detail::sw_<V,qvm_detail::swizzle_idx<-2,qvm_detail::swizzle_idx<-1,qvm_detail::swizzle_idx<2 > > > > const &>(a);
}
template <class V>
BOOST_QVM_INLINE_TRIVIAL
typename enable_if_c<
is_vec<V>::value && vec_traits<V>::dim>=3,
qvm_detail::sw_<V,qvm_detail::swizzle_idx<-2,qvm_detail::swizzle_idx<-1,qvm_detail::swizzle_idx<2 > > > > &>::type
_10Z( V & a )
{
return reinterpret_cast<qvm_detail::sw_<V,qvm_detail::swizzle_idx<-2,qvm_detail::swizzle_idx<-1,qvm_detail::swizzle_idx<2 > > > > &>(a);
}
template <class V>
BOOST_QVM_INLINE_TRIVIAL
typename enable_if_c<
is_vec<V>::value && vec_traits<V>::dim>=3,
qvm_detail::sw_<V,qvm_detail::swizzle_idx<-1,qvm_detail::swizzle_idx<-1,qvm_detail::swizzle_idx<2 > > > > const &>::type
_00Z( V const & a )
{
return reinterpret_cast<qvm_detail::sw_<V,qvm_detail::swizzle_idx<-1,qvm_detail::swizzle_idx<-1,qvm_detail::swizzle_idx<2 > > > > const &>(a);
}
template <class V>
BOOST_QVM_INLINE_TRIVIAL
typename enable_if_c<
is_vec<V>::value && vec_traits<V>::dim>=3,
qvm_detail::sw_<V,qvm_detail::swizzle_idx<-1,qvm_detail::swizzle_idx<-1,qvm_detail::swizzle_idx<2 > > > > &>::type
_00Z( V & a )
{
return reinterpret_cast<qvm_detail::sw_<V,qvm_detail::swizzle_idx<-1,qvm_detail::swizzle_idx<-1,qvm_detail::swizzle_idx<2 > > > > &>(a);
}
template <class V>
BOOST_QVM_INLINE_TRIVIAL
typename enable_if_c<
is_vec<V>::value && vec_traits<V>::dim>=4,
qvm_detail::sw_<V,qvm_detail::swizzle_idx<3,qvm_detail::swizzle_idx<-1,qvm_detail::swizzle_idx<2 > > > > const &>::type
W0Z( V const & a )
{
return reinterpret_cast<qvm_detail::sw_<V,qvm_detail::swizzle_idx<3,qvm_detail::swizzle_idx<-1,qvm_detail::swizzle_idx<2 > > > > const &>(a);
}
template <class V>
BOOST_QVM_INLINE_TRIVIAL
typename enable_if_c<
is_vec<V>::value && vec_traits<V>::dim>=4,
qvm_detail::sw_<V,qvm_detail::swizzle_idx<3,qvm_detail::swizzle_idx<-1,qvm_detail::swizzle_idx<2 > > > > &>::type
W0Z( V & a )
{
return reinterpret_cast<qvm_detail::sw_<V,qvm_detail::swizzle_idx<3,qvm_detail::swizzle_idx<-1,qvm_detail::swizzle_idx<2 > > > > &>(a);
}
template <class V>
BOOST_QVM_INLINE_TRIVIAL
typename enable_if_c<
is_vec<V>::value && vec_traits<V>::dim>=3,
qvm_detail::sw_<V,qvm_detail::swizzle_idx<2,qvm_detail::swizzle_idx<-1,qvm_detail::swizzle_idx<2 > > > > const &>::type
Z0Z( V const & a )
{
return reinterpret_cast<qvm_detail::sw_<V,qvm_detail::swizzle_idx<2,qvm_detail::swizzle_idx<-1,qvm_detail::swizzle_idx<2 > > > > const &>(a);
}
template <class V>
BOOST_QVM_INLINE_TRIVIAL
typename enable_if_c<
is_vec<V>::value && vec_traits<V>::dim>=3,
qvm_detail::sw_<V,qvm_detail::swizzle_idx<2,qvm_detail::swizzle_idx<-1,qvm_detail::swizzle_idx<2 > > > > &>::type
Z0Z( V & a )
{
return reinterpret_cast<qvm_detail::sw_<V,qvm_detail::swizzle_idx<2,qvm_detail::swizzle_idx<-1,qvm_detail::swizzle_idx<2 > > > > &>(a);
}
template <class V>
BOOST_QVM_INLINE_TRIVIAL
typename enable_if_c<
is_vec<V>::value && vec_traits<V>::dim>=3,
qvm_detail::sw_<V,qvm_detail::swizzle_idx<1,qvm_detail::swizzle_idx<-1,qvm_detail::swizzle_idx<2 > > > > const &>::type
Y0Z( V const & a )
{
return reinterpret_cast<qvm_detail::sw_<V,qvm_detail::swizzle_idx<1,qvm_detail::swizzle_idx<-1,qvm_detail::swizzle_idx<2 > > > > const &>(a);
}
template <class V>
BOOST_QVM_INLINE_TRIVIAL
typename enable_if_c<
is_vec<V>::value && vec_traits<V>::dim>=3,
qvm_detail::sw_<V,qvm_detail::swizzle_idx<1,qvm_detail::swizzle_idx<-1,qvm_detail::swizzle_idx<2 > > > > &>::type
Y0Z( V & a )
{
return reinterpret_cast<qvm_detail::sw_<V,qvm_detail::swizzle_idx<1,qvm_detail::swizzle_idx<-1,qvm_detail::swizzle_idx<2 > > > > &>(a);
}
template <class V>
BOOST_QVM_INLINE_TRIVIAL
typename enable_if_c<
is_vec<V>::value && vec_traits<V>::dim>=3,
qvm_detail::sw_<V,qvm_detail::swizzle_idx<0,qvm_detail::swizzle_idx<-1,qvm_detail::swizzle_idx<2 > > > > const &>::type
X0Z( V const & a )
{
return reinterpret_cast<qvm_detail::sw_<V,qvm_detail::swizzle_idx<0,qvm_detail::swizzle_idx<-1,qvm_detail::swizzle_idx<2 > > > > const &>(a);
}
template <class V>
BOOST_QVM_INLINE_TRIVIAL
typename enable_if_c<
is_vec<V>::value && vec_traits<V>::dim>=3,
qvm_detail::sw_<V,qvm_detail::swizzle_idx<0,qvm_detail::swizzle_idx<-1,qvm_detail::swizzle_idx<2 > > > > &>::type
X0Z( V & a )
{
return reinterpret_cast<qvm_detail::sw_<V,qvm_detail::swizzle_idx<0,qvm_detail::swizzle_idx<-1,qvm_detail::swizzle_idx<2 > > > > &>(a);
}
template <class V>
BOOST_QVM_INLINE_TRIVIAL
typename enable_if_c<
is_vec<V>::value && vec_traits<V>::dim>=4,
qvm_detail::sw_<V,qvm_detail::swizzle_idx<-2,qvm_detail::swizzle_idx<3,qvm_detail::swizzle_idx<2 > > > > const &>::type
_1WZ( V const & a )
{
return reinterpret_cast<qvm_detail::sw_<V,qvm_detail::swizzle_idx<-2,qvm_detail::swizzle_idx<3,qvm_detail::swizzle_idx<2 > > > > const &>(a);
}
template <class V>
BOOST_QVM_INLINE_TRIVIAL
typename enable_if_c<
is_vec<V>::value && vec_traits<V>::dim>=4,
qvm_detail::sw_<V,qvm_detail::swizzle_idx<-2,qvm_detail::swizzle_idx<3,qvm_detail::swizzle_idx<2 > > > > &>::type
_1WZ( V & a )
{
return reinterpret_cast<qvm_detail::sw_<V,qvm_detail::swizzle_idx<-2,qvm_detail::swizzle_idx<3,qvm_detail::swizzle_idx<2 > > > > &>(a);
}
template <class V>
BOOST_QVM_INLINE_TRIVIAL
typename enable_if_c<
is_vec<V>::value && vec_traits<V>::dim>=4,
qvm_detail::sw_<V,qvm_detail::swizzle_idx<-1,qvm_detail::swizzle_idx<3,qvm_detail::swizzle_idx<2 > > > > const &>::type
_0WZ( V const & a )
{
return reinterpret_cast<qvm_detail::sw_<V,qvm_detail::swizzle_idx<-1,qvm_detail::swizzle_idx<3,qvm_detail::swizzle_idx<2 > > > > const &>(a);
}
template <class V>
BOOST_QVM_INLINE_TRIVIAL
typename enable_if_c<
is_vec<V>::value && vec_traits<V>::dim>=4,
qvm_detail::sw_<V,qvm_detail::swizzle_idx<-1,qvm_detail::swizzle_idx<3,qvm_detail::swizzle_idx<2 > > > > &>::type
_0WZ( V & a )
{
return reinterpret_cast<qvm_detail::sw_<V,qvm_detail::swizzle_idx<-1,qvm_detail::swizzle_idx<3,qvm_detail::swizzle_idx<2 > > > > &>(a);
}
template <class V>
BOOST_QVM_INLINE_TRIVIAL
typename enable_if_c<
is_vec<V>::value && vec_traits<V>::dim>=4,
qvm_detail::sw_<V,qvm_detail::swizzle_idx<3,qvm_detail::swizzle_idx<3,qvm_detail::swizzle_idx<2 > > > > const &>::type
WWZ( V const & a )
{
return reinterpret_cast<qvm_detail::sw_<V,qvm_detail::swizzle_idx<3,qvm_detail::swizzle_idx<3,qvm_detail::swizzle_idx<2 > > > > const &>(a);
}
template <class V>
BOOST_QVM_INLINE_TRIVIAL
typename enable_if_c<
is_vec<V>::value && vec_traits<V>::dim>=4,
qvm_detail::sw_<V,qvm_detail::swizzle_idx<3,qvm_detail::swizzle_idx<3,qvm_detail::swizzle_idx<2 > > > > &>::type
WWZ( V & a )
{
return reinterpret_cast<qvm_detail::sw_<V,qvm_detail::swizzle_idx<3,qvm_detail::swizzle_idx<3,qvm_detail::swizzle_idx<2 > > > > &>(a);
}
template <class V>
BOOST_QVM_INLINE_TRIVIAL
typename enable_if_c<
is_vec<V>::value && vec_traits<V>::dim>=4,
qvm_detail::sw_<V,qvm_detail::swizzle_idx<2,qvm_detail::swizzle_idx<3,qvm_detail::swizzle_idx<2 > > > > const &>::type
ZWZ( V const & a )
{
return reinterpret_cast<qvm_detail::sw_<V,qvm_detail::swizzle_idx<2,qvm_detail::swizzle_idx<3,qvm_detail::swizzle_idx<2 > > > > const &>(a);
}
template <class V>
BOOST_QVM_INLINE_TRIVIAL
typename enable_if_c<
is_vec<V>::value && vec_traits<V>::dim>=4,
qvm_detail::sw_<V,qvm_detail::swizzle_idx<2,qvm_detail::swizzle_idx<3,qvm_detail::swizzle_idx<2 > > > > &>::type
ZWZ( V & a )
{
return reinterpret_cast<qvm_detail::sw_<V,qvm_detail::swizzle_idx<2,qvm_detail::swizzle_idx<3,qvm_detail::swizzle_idx<2 > > > > &>(a);
}
template <class V>
BOOST_QVM_INLINE_TRIVIAL
typename enable_if_c<
is_vec<V>::value && vec_traits<V>::dim>=4,
qvm_detail::sw_<V,qvm_detail::swizzle_idx<1,qvm_detail::swizzle_idx<3,qvm_detail::swizzle_idx<2 > > > > const &>::type
YWZ( V const & a )
{
return reinterpret_cast<qvm_detail::sw_<V,qvm_detail::swizzle_idx<1,qvm_detail::swizzle_idx<3,qvm_detail::swizzle_idx<2 > > > > const &>(a);
}
template <class V>
BOOST_QVM_INLINE_TRIVIAL
typename enable_if_c<
is_vec<V>::value && vec_traits<V>::dim>=4,
qvm_detail::sw_<V,qvm_detail::swizzle_idx<1,qvm_detail::swizzle_idx<3,qvm_detail::swizzle_idx<2 > > > > &>::type
YWZ( V & a )
{
return reinterpret_cast<qvm_detail::sw_<V,qvm_detail::swizzle_idx<1,qvm_detail::swizzle_idx<3,qvm_detail::swizzle_idx<2 > > > > &>(a);
}
template <class V>
BOOST_QVM_INLINE_TRIVIAL
typename enable_if_c<
is_vec<V>::value && vec_traits<V>::dim>=4,
qvm_detail::sw_<V,qvm_detail::swizzle_idx<0,qvm_detail::swizzle_idx<3,qvm_detail::swizzle_idx<2 > > > > const &>::type
XWZ( V const & a )
{
return reinterpret_cast<qvm_detail::sw_<V,qvm_detail::swizzle_idx<0,qvm_detail::swizzle_idx<3,qvm_detail::swizzle_idx<2 > > > > const &>(a);
}
template <class V>
BOOST_QVM_INLINE_TRIVIAL
typename enable_if_c<
is_vec<V>::value && vec_traits<V>::dim>=4,
qvm_detail::sw_<V,qvm_detail::swizzle_idx<0,qvm_detail::swizzle_idx<3,qvm_detail::swizzle_idx<2 > > > > &>::type
XWZ( V & a )
{
return reinterpret_cast<qvm_detail::sw_<V,qvm_detail::swizzle_idx<0,qvm_detail::swizzle_idx<3,qvm_detail::swizzle_idx<2 > > > > &>(a);
}
template <class V>
BOOST_QVM_INLINE_TRIVIAL
typename enable_if_c<
is_vec<V>::value && vec_traits<V>::dim>=3,
qvm_detail::sw_<V,qvm_detail::swizzle_idx<-2,qvm_detail::swizzle_idx<2,qvm_detail::swizzle_idx<2 > > > > const &>::type
_1ZZ( V const & a )
{
return reinterpret_cast<qvm_detail::sw_<V,qvm_detail::swizzle_idx<-2,qvm_detail::swizzle_idx<2,qvm_detail::swizzle_idx<2 > > > > const &>(a);
}
template <class V>
BOOST_QVM_INLINE_TRIVIAL
typename enable_if_c<
is_vec<V>::value && vec_traits<V>::dim>=3,
qvm_detail::sw_<V,qvm_detail::swizzle_idx<-2,qvm_detail::swizzle_idx<2,qvm_detail::swizzle_idx<2 > > > > &>::type
_1ZZ( V & a )
{
return reinterpret_cast<qvm_detail::sw_<V,qvm_detail::swizzle_idx<-2,qvm_detail::swizzle_idx<2,qvm_detail::swizzle_idx<2 > > > > &>(a);
}
template <class V>
BOOST_QVM_INLINE_TRIVIAL
typename enable_if_c<
is_vec<V>::value && vec_traits<V>::dim>=3,
qvm_detail::sw_<V,qvm_detail::swizzle_idx<-1,qvm_detail::swizzle_idx<2,qvm_detail::swizzle_idx<2 > > > > const &>::type
_0ZZ( V const & a )
{
return reinterpret_cast<qvm_detail::sw_<V,qvm_detail::swizzle_idx<-1,qvm_detail::swizzle_idx<2,qvm_detail::swizzle_idx<2 > > > > const &>(a);
}
template <class V>
BOOST_QVM_INLINE_TRIVIAL
typename enable_if_c<
is_vec<V>::value && vec_traits<V>::dim>=3,
qvm_detail::sw_<V,qvm_detail::swizzle_idx<-1,qvm_detail::swizzle_idx<2,qvm_detail::swizzle_idx<2 > > > > &>::type
_0ZZ( V & a )
{
return reinterpret_cast<qvm_detail::sw_<V,qvm_detail::swizzle_idx<-1,qvm_detail::swizzle_idx<2,qvm_detail::swizzle_idx<2 > > > > &>(a);
}
template <class V>
BOOST_QVM_INLINE_TRIVIAL
typename enable_if_c<
is_vec<V>::value && vec_traits<V>::dim>=4,
qvm_detail::sw_<V,qvm_detail::swizzle_idx<3,qvm_detail::swizzle_idx<2,qvm_detail::swizzle_idx<2 > > > > const &>::type
WZZ( V const & a )
{
return reinterpret_cast<qvm_detail::sw_<V,qvm_detail::swizzle_idx<3,qvm_detail::swizzle_idx<2,qvm_detail::swizzle_idx<2 > > > > const &>(a);
}
template <class V>
BOOST_QVM_INLINE_TRIVIAL
typename enable_if_c<
is_vec<V>::value && vec_traits<V>::dim>=4,
qvm_detail::sw_<V,qvm_detail::swizzle_idx<3,qvm_detail::swizzle_idx<2,qvm_detail::swizzle_idx<2 > > > > &>::type
WZZ( V & a )
{
return reinterpret_cast<qvm_detail::sw_<V,qvm_detail::swizzle_idx<3,qvm_detail::swizzle_idx<2,qvm_detail::swizzle_idx<2 > > > > &>(a);
}
template <class V>
BOOST_QVM_INLINE_TRIVIAL
typename enable_if_c<
is_vec<V>::value && vec_traits<V>::dim>=3,
qvm_detail::sw_<V,qvm_detail::swizzle_idx<2,qvm_detail::swizzle_idx<2,qvm_detail::swizzle_idx<2 > > > > const &>::type
ZZZ( V const & a )
{
return reinterpret_cast<qvm_detail::sw_<V,qvm_detail::swizzle_idx<2,qvm_detail::swizzle_idx<2,qvm_detail::swizzle_idx<2 > > > > const &>(a);
}
template <class V>
BOOST_QVM_INLINE_TRIVIAL
typename enable_if_c<
is_vec<V>::value && vec_traits<V>::dim>=3,
qvm_detail::sw_<V,qvm_detail::swizzle_idx<2,qvm_detail::swizzle_idx<2,qvm_detail::swizzle_idx<2 > > > > &>::type
ZZZ( V & a )
{
return reinterpret_cast<qvm_detail::sw_<V,qvm_detail::swizzle_idx<2,qvm_detail::swizzle_idx<2,qvm_detail::swizzle_idx<2 > > > > &>(a);
}
template <class V>
BOOST_QVM_INLINE_TRIVIAL
typename enable_if_c<
is_vec<V>::value && vec_traits<V>::dim>=3,
qvm_detail::sw_<V,qvm_detail::swizzle_idx<1,qvm_detail::swizzle_idx<2,qvm_detail::swizzle_idx<2 > > > > const &>::type
YZZ( V const & a )
{
return reinterpret_cast<qvm_detail::sw_<V,qvm_detail::swizzle_idx<1,qvm_detail::swizzle_idx<2,qvm_detail::swizzle_idx<2 > > > > const &>(a);
}
template <class V>
BOOST_QVM_INLINE_TRIVIAL
typename enable_if_c<
is_vec<V>::value && vec_traits<V>::dim>=3,
qvm_detail::sw_<V,qvm_detail::swizzle_idx<1,qvm_detail::swizzle_idx<2,qvm_detail::swizzle_idx<2 > > > > &>::type
YZZ( V & a )
{
return reinterpret_cast<qvm_detail::sw_<V,qvm_detail::swizzle_idx<1,qvm_detail::swizzle_idx<2,qvm_detail::swizzle_idx<2 > > > > &>(a);
}
template <class V>
BOOST_QVM_INLINE_TRIVIAL
typename enable_if_c<
is_vec<V>::value && vec_traits<V>::dim>=3,
qvm_detail::sw_<V,qvm_detail::swizzle_idx<0,qvm_detail::swizzle_idx<2,qvm_detail::swizzle_idx<2 > > > > const &>::type
XZZ( V const & a )
{
return reinterpret_cast<qvm_detail::sw_<V,qvm_detail::swizzle_idx<0,qvm_detail::swizzle_idx<2,qvm_detail::swizzle_idx<2 > > > > const &>(a);
}
template <class V>
BOOST_QVM_INLINE_TRIVIAL
typename enable_if_c<
is_vec<V>::value && vec_traits<V>::dim>=3,
qvm_detail::sw_<V,qvm_detail::swizzle_idx<0,qvm_detail::swizzle_idx<2,qvm_detail::swizzle_idx<2 > > > > &>::type
XZZ( V & a )
{
return reinterpret_cast<qvm_detail::sw_<V,qvm_detail::swizzle_idx<0,qvm_detail::swizzle_idx<2,qvm_detail::swizzle_idx<2 > > > > &>(a);
}
template <class V>
BOOST_QVM_INLINE_TRIVIAL
typename enable_if_c<
is_vec<V>::value && vec_traits<V>::dim>=3,
qvm_detail::sw_<V,qvm_detail::swizzle_idx<-2,qvm_detail::swizzle_idx<1,qvm_detail::swizzle_idx<2 > > > > const &>::type
_1YZ( V const & a )
{
return reinterpret_cast<qvm_detail::sw_<V,qvm_detail::swizzle_idx<-2,qvm_detail::swizzle_idx<1,qvm_detail::swizzle_idx<2 > > > > const &>(a);
}
template <class V>
BOOST_QVM_INLINE_TRIVIAL
typename enable_if_c<
is_vec<V>::value && vec_traits<V>::dim>=3,
qvm_detail::sw_<V,qvm_detail::swizzle_idx<-2,qvm_detail::swizzle_idx<1,qvm_detail::swizzle_idx<2 > > > > &>::type
_1YZ( V & a )
{
return reinterpret_cast<qvm_detail::sw_<V,qvm_detail::swizzle_idx<-2,qvm_detail::swizzle_idx<1,qvm_detail::swizzle_idx<2 > > > > &>(a);
}
template <class V>
BOOST_QVM_INLINE_TRIVIAL
typename enable_if_c<
is_vec<V>::value && vec_traits<V>::dim>=3,
qvm_detail::sw_<V,qvm_detail::swizzle_idx<-1,qvm_detail::swizzle_idx<1,qvm_detail::swizzle_idx<2 > > > > const &>::type
_0YZ( V const & a )
{
return reinterpret_cast<qvm_detail::sw_<V,qvm_detail::swizzle_idx<-1,qvm_detail::swizzle_idx<1,qvm_detail::swizzle_idx<2 > > > > const &>(a);
}
template <class V>
BOOST_QVM_INLINE_TRIVIAL
typename enable_if_c<
is_vec<V>::value && vec_traits<V>::dim>=3,
qvm_detail::sw_<V,qvm_detail::swizzle_idx<-1,qvm_detail::swizzle_idx<1,qvm_detail::swizzle_idx<2 > > > > &>::type
_0YZ( V & a )
{
return reinterpret_cast<qvm_detail::sw_<V,qvm_detail::swizzle_idx<-1,qvm_detail::swizzle_idx<1,qvm_detail::swizzle_idx<2 > > > > &>(a);
}
template <class V>
BOOST_QVM_INLINE_TRIVIAL
typename enable_if_c<
is_vec<V>::value && vec_traits<V>::dim>=4,
qvm_detail::sw_<V,qvm_detail::swizzle_idx<3,qvm_detail::swizzle_idx<1,qvm_detail::swizzle_idx<2 > > > > const &>::type
WYZ( V const & a )
{
return reinterpret_cast<qvm_detail::sw_<V,qvm_detail::swizzle_idx<3,qvm_detail::swizzle_idx<1,qvm_detail::swizzle_idx<2 > > > > const &>(a);
}
template <class V>
BOOST_QVM_INLINE_TRIVIAL
typename enable_if_c<
is_vec<V>::value && vec_traits<V>::dim>=4,
qvm_detail::sw_<V,qvm_detail::swizzle_idx<3,qvm_detail::swizzle_idx<1,qvm_detail::swizzle_idx<2 > > > > &>::type
WYZ( V & a )
{
return reinterpret_cast<qvm_detail::sw_<V,qvm_detail::swizzle_idx<3,qvm_detail::swizzle_idx<1,qvm_detail::swizzle_idx<2 > > > > &>(a);
}
template <class V>
BOOST_QVM_INLINE_TRIVIAL
typename enable_if_c<
is_vec<V>::value && vec_traits<V>::dim>=3,
qvm_detail::sw_<V,qvm_detail::swizzle_idx<2,qvm_detail::swizzle_idx<1,qvm_detail::swizzle_idx<2 > > > > const &>::type
ZYZ( V const & a )
{
return reinterpret_cast<qvm_detail::sw_<V,qvm_detail::swizzle_idx<2,qvm_detail::swizzle_idx<1,qvm_detail::swizzle_idx<2 > > > > const &>(a);
}
template <class V>
BOOST_QVM_INLINE_TRIVIAL
typename enable_if_c<
is_vec<V>::value && vec_traits<V>::dim>=3,
qvm_detail::sw_<V,qvm_detail::swizzle_idx<2,qvm_detail::swizzle_idx<1,qvm_detail::swizzle_idx<2 > > > > &>::type
ZYZ( V & a )
{
return reinterpret_cast<qvm_detail::sw_<V,qvm_detail::swizzle_idx<2,qvm_detail::swizzle_idx<1,qvm_detail::swizzle_idx<2 > > > > &>(a);
}
template <class V>
BOOST_QVM_INLINE_TRIVIAL
typename enable_if_c<
is_vec<V>::value && vec_traits<V>::dim>=3,
qvm_detail::sw_<V,qvm_detail::swizzle_idx<1,qvm_detail::swizzle_idx<1,qvm_detail::swizzle_idx<2 > > > > const &>::type
YYZ( V const & a )
{
return reinterpret_cast<qvm_detail::sw_<V,qvm_detail::swizzle_idx<1,qvm_detail::swizzle_idx<1,qvm_detail::swizzle_idx<2 > > > > const &>(a);
}
template <class V>
BOOST_QVM_INLINE_TRIVIAL
typename enable_if_c<
is_vec<V>::value && vec_traits<V>::dim>=3,
qvm_detail::sw_<V,qvm_detail::swizzle_idx<1,qvm_detail::swizzle_idx<1,qvm_detail::swizzle_idx<2 > > > > &>::type
YYZ( V & a )
{
return reinterpret_cast<qvm_detail::sw_<V,qvm_detail::swizzle_idx<1,qvm_detail::swizzle_idx<1,qvm_detail::swizzle_idx<2 > > > > &>(a);
}
template <class V>
BOOST_QVM_INLINE_TRIVIAL
typename enable_if_c<
is_vec<V>::value && vec_traits<V>::dim>=3,
qvm_detail::sw_<V,qvm_detail::swizzle_idx<0,qvm_detail::swizzle_idx<1,qvm_detail::swizzle_idx<2 > > > > const &>::type
XYZ( V const & a )
{
return reinterpret_cast<qvm_detail::sw_<V,qvm_detail::swizzle_idx<0,qvm_detail::swizzle_idx<1,qvm_detail::swizzle_idx<2 > > > > const &>(a);
}
template <class V>
BOOST_QVM_INLINE_TRIVIAL
typename enable_if_c<
is_vec<V>::value && vec_traits<V>::dim>=3,
qvm_detail::sw_<V,qvm_detail::swizzle_idx<0,qvm_detail::swizzle_idx<1,qvm_detail::swizzle_idx<2 > > > > &>::type
XYZ( V & a )
{
return reinterpret_cast<qvm_detail::sw_<V,qvm_detail::swizzle_idx<0,qvm_detail::swizzle_idx<1,qvm_detail::swizzle_idx<2 > > > > &>(a);
}
template <class V>
BOOST_QVM_INLINE_TRIVIAL
typename enable_if_c<
is_vec<V>::value && vec_traits<V>::dim>=3,
qvm_detail::sw_<V,qvm_detail::swizzle_idx<-2,qvm_detail::swizzle_idx<0,qvm_detail::swizzle_idx<2 > > > > const &>::type
_1XZ( V const & a )
{
return reinterpret_cast<qvm_detail::sw_<V,qvm_detail::swizzle_idx<-2,qvm_detail::swizzle_idx<0,qvm_detail::swizzle_idx<2 > > > > const &>(a);
}
template <class V>
BOOST_QVM_INLINE_TRIVIAL
typename enable_if_c<
is_vec<V>::value && vec_traits<V>::dim>=3,
qvm_detail::sw_<V,qvm_detail::swizzle_idx<-2,qvm_detail::swizzle_idx<0,qvm_detail::swizzle_idx<2 > > > > &>::type
_1XZ( V & a )
{
return reinterpret_cast<qvm_detail::sw_<V,qvm_detail::swizzle_idx<-2,qvm_detail::swizzle_idx<0,qvm_detail::swizzle_idx<2 > > > > &>(a);
}
template <class V>
BOOST_QVM_INLINE_TRIVIAL
typename enable_if_c<
is_vec<V>::value && vec_traits<V>::dim>=3,
qvm_detail::sw_<V,qvm_detail::swizzle_idx<-1,qvm_detail::swizzle_idx<0,qvm_detail::swizzle_idx<2 > > > > const &>::type
_0XZ( V const & a )
{
return reinterpret_cast<qvm_detail::sw_<V,qvm_detail::swizzle_idx<-1,qvm_detail::swizzle_idx<0,qvm_detail::swizzle_idx<2 > > > > const &>(a);
}
template <class V>
BOOST_QVM_INLINE_TRIVIAL
typename enable_if_c<
is_vec<V>::value && vec_traits<V>::dim>=3,
qvm_detail::sw_<V,qvm_detail::swizzle_idx<-1,qvm_detail::swizzle_idx<0,qvm_detail::swizzle_idx<2 > > > > &>::type
_0XZ( V & a )
{
return reinterpret_cast<qvm_detail::sw_<V,qvm_detail::swizzle_idx<-1,qvm_detail::swizzle_idx<0,qvm_detail::swizzle_idx<2 > > > > &>(a);
}
template <class V>
BOOST_QVM_INLINE_TRIVIAL
typename enable_if_c<
is_vec<V>::value && vec_traits<V>::dim>=4,
qvm_detail::sw_<V,qvm_detail::swizzle_idx<3,qvm_detail::swizzle_idx<0,qvm_detail::swizzle_idx<2 > > > > const &>::type
WXZ( V const & a )
{
return reinterpret_cast<qvm_detail::sw_<V,qvm_detail::swizzle_idx<3,qvm_detail::swizzle_idx<0,qvm_detail::swizzle_idx<2 > > > > const &>(a);
}
template <class V>
BOOST_QVM_INLINE_TRIVIAL
typename enable_if_c<
is_vec<V>::value && vec_traits<V>::dim>=4,
qvm_detail::sw_<V,qvm_detail::swizzle_idx<3,qvm_detail::swizzle_idx<0,qvm_detail::swizzle_idx<2 > > > > &>::type
WXZ( V & a )
{
return reinterpret_cast<qvm_detail::sw_<V,qvm_detail::swizzle_idx<3,qvm_detail::swizzle_idx<0,qvm_detail::swizzle_idx<2 > > > > &>(a);
}
template <class V>
BOOST_QVM_INLINE_TRIVIAL
typename enable_if_c<
is_vec<V>::value && vec_traits<V>::dim>=3,
qvm_detail::sw_<V,qvm_detail::swizzle_idx<2,qvm_detail::swizzle_idx<0,qvm_detail::swizzle_idx<2 > > > > const &>::type
ZXZ( V const & a )
{
return reinterpret_cast<qvm_detail::sw_<V,qvm_detail::swizzle_idx<2,qvm_detail::swizzle_idx<0,qvm_detail::swizzle_idx<2 > > > > const &>(a);
}
template <class V>
BOOST_QVM_INLINE_TRIVIAL
typename enable_if_c<
is_vec<V>::value && vec_traits<V>::dim>=3,
qvm_detail::sw_<V,qvm_detail::swizzle_idx<2,qvm_detail::swizzle_idx<0,qvm_detail::swizzle_idx<2 > > > > &>::type
ZXZ( V & a )
{
return reinterpret_cast<qvm_detail::sw_<V,qvm_detail::swizzle_idx<2,qvm_detail::swizzle_idx<0,qvm_detail::swizzle_idx<2 > > > > &>(a);
}
template <class V>
BOOST_QVM_INLINE_TRIVIAL
typename enable_if_c<
is_vec<V>::value && vec_traits<V>::dim>=3,
qvm_detail::sw_<V,qvm_detail::swizzle_idx<1,qvm_detail::swizzle_idx<0,qvm_detail::swizzle_idx<2 > > > > const &>::type
YXZ( V const & a )
{
return reinterpret_cast<qvm_detail::sw_<V,qvm_detail::swizzle_idx<1,qvm_detail::swizzle_idx<0,qvm_detail::swizzle_idx<2 > > > > const &>(a);
}
template <class V>
BOOST_QVM_INLINE_TRIVIAL
typename enable_if_c<
is_vec<V>::value && vec_traits<V>::dim>=3,
qvm_detail::sw_<V,qvm_detail::swizzle_idx<1,qvm_detail::swizzle_idx<0,qvm_detail::swizzle_idx<2 > > > > &>::type
YXZ( V & a )
{
return reinterpret_cast<qvm_detail::sw_<V,qvm_detail::swizzle_idx<1,qvm_detail::swizzle_idx<0,qvm_detail::swizzle_idx<2 > > > > &>(a);
}
template <class V>
BOOST_QVM_INLINE_TRIVIAL
typename enable_if_c<
is_vec<V>::value && vec_traits<V>::dim>=3,
qvm_detail::sw_<V,qvm_detail::swizzle_idx<0,qvm_detail::swizzle_idx<0,qvm_detail::swizzle_idx<2 > > > > const &>::type
XXZ( V const & a )
{
return reinterpret_cast<qvm_detail::sw_<V,qvm_detail::swizzle_idx<0,qvm_detail::swizzle_idx<0,qvm_detail::swizzle_idx<2 > > > > const &>(a);
}
template <class V>
BOOST_QVM_INLINE_TRIVIAL
typename enable_if_c<
is_vec<V>::value && vec_traits<V>::dim>=3,
qvm_detail::sw_<V,qvm_detail::swizzle_idx<0,qvm_detail::swizzle_idx<0,qvm_detail::swizzle_idx<2 > > > > &>::type
XXZ( V & a )
{
return reinterpret_cast<qvm_detail::sw_<V,qvm_detail::swizzle_idx<0,qvm_detail::swizzle_idx<0,qvm_detail::swizzle_idx<2 > > > > &>(a);
}
template <class V>
BOOST_QVM_INLINE_TRIVIAL
typename enable_if_c<
is_vec<V>::value && vec_traits<V>::dim>=2,
qvm_detail::sw_<V,qvm_detail::swizzle_idx<-2,qvm_detail::swizzle_idx<-2,qvm_detail::swizzle_idx<1 > > > > const &>::type
_11Y( V const & a )
{
return reinterpret_cast<qvm_detail::sw_<V,qvm_detail::swizzle_idx<-2,qvm_detail::swizzle_idx<-2,qvm_detail::swizzle_idx<1 > > > > const &>(a);
}
template <class V>
BOOST_QVM_INLINE_TRIVIAL
typename enable_if_c<
is_vec<V>::value && vec_traits<V>::dim>=2,
qvm_detail::sw_<V,qvm_detail::swizzle_idx<-2,qvm_detail::swizzle_idx<-2,qvm_detail::swizzle_idx<1 > > > > &>::type
_11Y( V & a )
{
return reinterpret_cast<qvm_detail::sw_<V,qvm_detail::swizzle_idx<-2,qvm_detail::swizzle_idx<-2,qvm_detail::swizzle_idx<1 > > > > &>(a);
}
template <class V>
BOOST_QVM_INLINE_TRIVIAL
typename enable_if_c<
is_vec<V>::value && vec_traits<V>::dim>=2,
qvm_detail::sw_<V,qvm_detail::swizzle_idx<-1,qvm_detail::swizzle_idx<-2,qvm_detail::swizzle_idx<1 > > > > const &>::type
_01Y( V const & a )
{
return reinterpret_cast<qvm_detail::sw_<V,qvm_detail::swizzle_idx<-1,qvm_detail::swizzle_idx<-2,qvm_detail::swizzle_idx<1 > > > > const &>(a);
}
template <class V>
BOOST_QVM_INLINE_TRIVIAL
typename enable_if_c<
is_vec<V>::value && vec_traits<V>::dim>=2,
qvm_detail::sw_<V,qvm_detail::swizzle_idx<-1,qvm_detail::swizzle_idx<-2,qvm_detail::swizzle_idx<1 > > > > &>::type
_01Y( V & a )
{
return reinterpret_cast<qvm_detail::sw_<V,qvm_detail::swizzle_idx<-1,qvm_detail::swizzle_idx<-2,qvm_detail::swizzle_idx<1 > > > > &>(a);
}
template <class V>
BOOST_QVM_INLINE_TRIVIAL
typename enable_if_c<
is_vec<V>::value && vec_traits<V>::dim>=4,
qvm_detail::sw_<V,qvm_detail::swizzle_idx<3,qvm_detail::swizzle_idx<-2,qvm_detail::swizzle_idx<1 > > > > const &>::type
W1Y( V const & a )
{
return reinterpret_cast<qvm_detail::sw_<V,qvm_detail::swizzle_idx<3,qvm_detail::swizzle_idx<-2,qvm_detail::swizzle_idx<1 > > > > const &>(a);
}
template <class V>
BOOST_QVM_INLINE_TRIVIAL
typename enable_if_c<
is_vec<V>::value && vec_traits<V>::dim>=4,
qvm_detail::sw_<V,qvm_detail::swizzle_idx<3,qvm_detail::swizzle_idx<-2,qvm_detail::swizzle_idx<1 > > > > &>::type
W1Y( V & a )
{
return reinterpret_cast<qvm_detail::sw_<V,qvm_detail::swizzle_idx<3,qvm_detail::swizzle_idx<-2,qvm_detail::swizzle_idx<1 > > > > &>(a);
}
template <class V>
BOOST_QVM_INLINE_TRIVIAL
typename enable_if_c<
is_vec<V>::value && vec_traits<V>::dim>=3,
qvm_detail::sw_<V,qvm_detail::swizzle_idx<2,qvm_detail::swizzle_idx<-2,qvm_detail::swizzle_idx<1 > > > > const &>::type
Z1Y( V const & a )
{
return reinterpret_cast<qvm_detail::sw_<V,qvm_detail::swizzle_idx<2,qvm_detail::swizzle_idx<-2,qvm_detail::swizzle_idx<1 > > > > const &>(a);
}
template <class V>
BOOST_QVM_INLINE_TRIVIAL
typename enable_if_c<
is_vec<V>::value && vec_traits<V>::dim>=3,
qvm_detail::sw_<V,qvm_detail::swizzle_idx<2,qvm_detail::swizzle_idx<-2,qvm_detail::swizzle_idx<1 > > > > &>::type
Z1Y( V & a )
{
return reinterpret_cast<qvm_detail::sw_<V,qvm_detail::swizzle_idx<2,qvm_detail::swizzle_idx<-2,qvm_detail::swizzle_idx<1 > > > > &>(a);
}
template <class V>
BOOST_QVM_INLINE_TRIVIAL
typename enable_if_c<
is_vec<V>::value && vec_traits<V>::dim>=2,
qvm_detail::sw_<V,qvm_detail::swizzle_idx<1,qvm_detail::swizzle_idx<-2,qvm_detail::swizzle_idx<1 > > > > const &>::type
Y1Y( V const & a )
{
return reinterpret_cast<qvm_detail::sw_<V,qvm_detail::swizzle_idx<1,qvm_detail::swizzle_idx<-2,qvm_detail::swizzle_idx<1 > > > > const &>(a);
}
template <class V>
BOOST_QVM_INLINE_TRIVIAL
typename enable_if_c<
is_vec<V>::value && vec_traits<V>::dim>=2,
qvm_detail::sw_<V,qvm_detail::swizzle_idx<1,qvm_detail::swizzle_idx<-2,qvm_detail::swizzle_idx<1 > > > > &>::type
Y1Y( V & a )
{
return reinterpret_cast<qvm_detail::sw_<V,qvm_detail::swizzle_idx<1,qvm_detail::swizzle_idx<-2,qvm_detail::swizzle_idx<1 > > > > &>(a);
}
template <class V>
BOOST_QVM_INLINE_TRIVIAL
typename enable_if_c<
is_vec<V>::value && vec_traits<V>::dim>=2,
qvm_detail::sw_<V,qvm_detail::swizzle_idx<0,qvm_detail::swizzle_idx<-2,qvm_detail::swizzle_idx<1 > > > > const &>::type
X1Y( V const & a )
{
return reinterpret_cast<qvm_detail::sw_<V,qvm_detail::swizzle_idx<0,qvm_detail::swizzle_idx<-2,qvm_detail::swizzle_idx<1 > > > > const &>(a);
}
template <class V>
BOOST_QVM_INLINE_TRIVIAL
typename enable_if_c<
is_vec<V>::value && vec_traits<V>::dim>=2,
qvm_detail::sw_<V,qvm_detail::swizzle_idx<0,qvm_detail::swizzle_idx<-2,qvm_detail::swizzle_idx<1 > > > > &>::type
X1Y( V & a )
{
return reinterpret_cast<qvm_detail::sw_<V,qvm_detail::swizzle_idx<0,qvm_detail::swizzle_idx<-2,qvm_detail::swizzle_idx<1 > > > > &>(a);
}
template <class V>
BOOST_QVM_INLINE_TRIVIAL
typename enable_if_c<
is_vec<V>::value && vec_traits<V>::dim>=2,
qvm_detail::sw_<V,qvm_detail::swizzle_idx<-2,qvm_detail::swizzle_idx<-1,qvm_detail::swizzle_idx<1 > > > > const &>::type
_10Y( V const & a )
{
return reinterpret_cast<qvm_detail::sw_<V,qvm_detail::swizzle_idx<-2,qvm_detail::swizzle_idx<-1,qvm_detail::swizzle_idx<1 > > > > const &>(a);
}
template <class V>
BOOST_QVM_INLINE_TRIVIAL
typename enable_if_c<
is_vec<V>::value && vec_traits<V>::dim>=2,
qvm_detail::sw_<V,qvm_detail::swizzle_idx<-2,qvm_detail::swizzle_idx<-1,qvm_detail::swizzle_idx<1 > > > > &>::type
_10Y( V & a )
{
return reinterpret_cast<qvm_detail::sw_<V,qvm_detail::swizzle_idx<-2,qvm_detail::swizzle_idx<-1,qvm_detail::swizzle_idx<1 > > > > &>(a);
}
template <class V>
BOOST_QVM_INLINE_TRIVIAL
typename enable_if_c<
is_vec<V>::value && vec_traits<V>::dim>=2,
qvm_detail::sw_<V,qvm_detail::swizzle_idx<-1,qvm_detail::swizzle_idx<-1,qvm_detail::swizzle_idx<1 > > > > const &>::type
_00Y( V const & a )
{
return reinterpret_cast<qvm_detail::sw_<V,qvm_detail::swizzle_idx<-1,qvm_detail::swizzle_idx<-1,qvm_detail::swizzle_idx<1 > > > > const &>(a);
}
template <class V>
BOOST_QVM_INLINE_TRIVIAL
typename enable_if_c<
is_vec<V>::value && vec_traits<V>::dim>=2,
qvm_detail::sw_<V,qvm_detail::swizzle_idx<-1,qvm_detail::swizzle_idx<-1,qvm_detail::swizzle_idx<1 > > > > &>::type
_00Y( V & a )
{
return reinterpret_cast<qvm_detail::sw_<V,qvm_detail::swizzle_idx<-1,qvm_detail::swizzle_idx<-1,qvm_detail::swizzle_idx<1 > > > > &>(a);
}
template <class V>
BOOST_QVM_INLINE_TRIVIAL
typename enable_if_c<
is_vec<V>::value && vec_traits<V>::dim>=4,
qvm_detail::sw_<V,qvm_detail::swizzle_idx<3,qvm_detail::swizzle_idx<-1,qvm_detail::swizzle_idx<1 > > > > const &>::type
W0Y( V const & a )
{
return reinterpret_cast<qvm_detail::sw_<V,qvm_detail::swizzle_idx<3,qvm_detail::swizzle_idx<-1,qvm_detail::swizzle_idx<1 > > > > const &>(a);
}
template <class V>
BOOST_QVM_INLINE_TRIVIAL
typename enable_if_c<
is_vec<V>::value && vec_traits<V>::dim>=4,
qvm_detail::sw_<V,qvm_detail::swizzle_idx<3,qvm_detail::swizzle_idx<-1,qvm_detail::swizzle_idx<1 > > > > &>::type
W0Y( V & a )
{
return reinterpret_cast<qvm_detail::sw_<V,qvm_detail::swizzle_idx<3,qvm_detail::swizzle_idx<-1,qvm_detail::swizzle_idx<1 > > > > &>(a);
}
template <class V>
BOOST_QVM_INLINE_TRIVIAL
typename enable_if_c<
is_vec<V>::value && vec_traits<V>::dim>=3,
qvm_detail::sw_<V,qvm_detail::swizzle_idx<2,qvm_detail::swizzle_idx<-1,qvm_detail::swizzle_idx<1 > > > > const &>::type
Z0Y( V const & a )
{
return reinterpret_cast<qvm_detail::sw_<V,qvm_detail::swizzle_idx<2,qvm_detail::swizzle_idx<-1,qvm_detail::swizzle_idx<1 > > > > const &>(a);
}
template <class V>
BOOST_QVM_INLINE_TRIVIAL
typename enable_if_c<
is_vec<V>::value && vec_traits<V>::dim>=3,
qvm_detail::sw_<V,qvm_detail::swizzle_idx<2,qvm_detail::swizzle_idx<-1,qvm_detail::swizzle_idx<1 > > > > &>::type
Z0Y( V & a )
{
return reinterpret_cast<qvm_detail::sw_<V,qvm_detail::swizzle_idx<2,qvm_detail::swizzle_idx<-1,qvm_detail::swizzle_idx<1 > > > > &>(a);
}
template <class V>
BOOST_QVM_INLINE_TRIVIAL
typename enable_if_c<
is_vec<V>::value && vec_traits<V>::dim>=2,
qvm_detail::sw_<V,qvm_detail::swizzle_idx<1,qvm_detail::swizzle_idx<-1,qvm_detail::swizzle_idx<1 > > > > const &>::type
Y0Y( V const & a )
{
return reinterpret_cast<qvm_detail::sw_<V,qvm_detail::swizzle_idx<1,qvm_detail::swizzle_idx<-1,qvm_detail::swizzle_idx<1 > > > > const &>(a);
}
template <class V>
BOOST_QVM_INLINE_TRIVIAL
typename enable_if_c<
is_vec<V>::value && vec_traits<V>::dim>=2,
qvm_detail::sw_<V,qvm_detail::swizzle_idx<1,qvm_detail::swizzle_idx<-1,qvm_detail::swizzle_idx<1 > > > > &>::type
Y0Y( V & a )
{
return reinterpret_cast<qvm_detail::sw_<V,qvm_detail::swizzle_idx<1,qvm_detail::swizzle_idx<-1,qvm_detail::swizzle_idx<1 > > > > &>(a);
}
template <class V>
BOOST_QVM_INLINE_TRIVIAL
typename enable_if_c<
is_vec<V>::value && vec_traits<V>::dim>=2,
qvm_detail::sw_<V,qvm_detail::swizzle_idx<0,qvm_detail::swizzle_idx<-1,qvm_detail::swizzle_idx<1 > > > > const &>::type
X0Y( V const & a )
{
return reinterpret_cast<qvm_detail::sw_<V,qvm_detail::swizzle_idx<0,qvm_detail::swizzle_idx<-1,qvm_detail::swizzle_idx<1 > > > > const &>(a);
}
template <class V>
BOOST_QVM_INLINE_TRIVIAL
typename enable_if_c<
is_vec<V>::value && vec_traits<V>::dim>=2,
qvm_detail::sw_<V,qvm_detail::swizzle_idx<0,qvm_detail::swizzle_idx<-1,qvm_detail::swizzle_idx<1 > > > > &>::type
X0Y( V & a )
{
return reinterpret_cast<qvm_detail::sw_<V,qvm_detail::swizzle_idx<0,qvm_detail::swizzle_idx<-1,qvm_detail::swizzle_idx<1 > > > > &>(a);
}
template <class V>
BOOST_QVM_INLINE_TRIVIAL
typename enable_if_c<
is_vec<V>::value && vec_traits<V>::dim>=4,
qvm_detail::sw_<V,qvm_detail::swizzle_idx<-2,qvm_detail::swizzle_idx<3,qvm_detail::swizzle_idx<1 > > > > const &>::type
_1WY( V const & a )
{
return reinterpret_cast<qvm_detail::sw_<V,qvm_detail::swizzle_idx<-2,qvm_detail::swizzle_idx<3,qvm_detail::swizzle_idx<1 > > > > const &>(a);
}
template <class V>
BOOST_QVM_INLINE_TRIVIAL
typename enable_if_c<
is_vec<V>::value && vec_traits<V>::dim>=4,
qvm_detail::sw_<V,qvm_detail::swizzle_idx<-2,qvm_detail::swizzle_idx<3,qvm_detail::swizzle_idx<1 > > > > &>::type
_1WY( V & a )
{
return reinterpret_cast<qvm_detail::sw_<V,qvm_detail::swizzle_idx<-2,qvm_detail::swizzle_idx<3,qvm_detail::swizzle_idx<1 > > > > &>(a);
}
template <class V>
BOOST_QVM_INLINE_TRIVIAL
typename enable_if_c<
is_vec<V>::value && vec_traits<V>::dim>=4,
qvm_detail::sw_<V,qvm_detail::swizzle_idx<-1,qvm_detail::swizzle_idx<3,qvm_detail::swizzle_idx<1 > > > > const &>::type
_0WY( V const & a )
{
return reinterpret_cast<qvm_detail::sw_<V,qvm_detail::swizzle_idx<-1,qvm_detail::swizzle_idx<3,qvm_detail::swizzle_idx<1 > > > > const &>(a);
}
template <class V>
BOOST_QVM_INLINE_TRIVIAL
typename enable_if_c<
is_vec<V>::value && vec_traits<V>::dim>=4,
qvm_detail::sw_<V,qvm_detail::swizzle_idx<-1,qvm_detail::swizzle_idx<3,qvm_detail::swizzle_idx<1 > > > > &>::type
_0WY( V & a )
{
return reinterpret_cast<qvm_detail::sw_<V,qvm_detail::swizzle_idx<-1,qvm_detail::swizzle_idx<3,qvm_detail::swizzle_idx<1 > > > > &>(a);
}
template <class V>
BOOST_QVM_INLINE_TRIVIAL
typename enable_if_c<
is_vec<V>::value && vec_traits<V>::dim>=4,
qvm_detail::sw_<V,qvm_detail::swizzle_idx<3,qvm_detail::swizzle_idx<3,qvm_detail::swizzle_idx<1 > > > > const &>::type
WWY( V const & a )
{
return reinterpret_cast<qvm_detail::sw_<V,qvm_detail::swizzle_idx<3,qvm_detail::swizzle_idx<3,qvm_detail::swizzle_idx<1 > > > > const &>(a);
}
template <class V>
BOOST_QVM_INLINE_TRIVIAL
typename enable_if_c<
is_vec<V>::value && vec_traits<V>::dim>=4,
qvm_detail::sw_<V,qvm_detail::swizzle_idx<3,qvm_detail::swizzle_idx<3,qvm_detail::swizzle_idx<1 > > > > &>::type
WWY( V & a )
{
return reinterpret_cast<qvm_detail::sw_<V,qvm_detail::swizzle_idx<3,qvm_detail::swizzle_idx<3,qvm_detail::swizzle_idx<1 > > > > &>(a);
}
template <class V>
BOOST_QVM_INLINE_TRIVIAL
typename enable_if_c<
is_vec<V>::value && vec_traits<V>::dim>=4,
qvm_detail::sw_<V,qvm_detail::swizzle_idx<2,qvm_detail::swizzle_idx<3,qvm_detail::swizzle_idx<1 > > > > const &>::type
ZWY( V const & a )
{
return reinterpret_cast<qvm_detail::sw_<V,qvm_detail::swizzle_idx<2,qvm_detail::swizzle_idx<3,qvm_detail::swizzle_idx<1 > > > > const &>(a);
}
template <class V>
BOOST_QVM_INLINE_TRIVIAL
typename enable_if_c<
is_vec<V>::value && vec_traits<V>::dim>=4,
qvm_detail::sw_<V,qvm_detail::swizzle_idx<2,qvm_detail::swizzle_idx<3,qvm_detail::swizzle_idx<1 > > > > &>::type
ZWY( V & a )
{
return reinterpret_cast<qvm_detail::sw_<V,qvm_detail::swizzle_idx<2,qvm_detail::swizzle_idx<3,qvm_detail::swizzle_idx<1 > > > > &>(a);
}
template <class V>
BOOST_QVM_INLINE_TRIVIAL
typename enable_if_c<
is_vec<V>::value && vec_traits<V>::dim>=4,
qvm_detail::sw_<V,qvm_detail::swizzle_idx<1,qvm_detail::swizzle_idx<3,qvm_detail::swizzle_idx<1 > > > > const &>::type
YWY( V const & a )
{
return reinterpret_cast<qvm_detail::sw_<V,qvm_detail::swizzle_idx<1,qvm_detail::swizzle_idx<3,qvm_detail::swizzle_idx<1 > > > > const &>(a);
}
template <class V>
BOOST_QVM_INLINE_TRIVIAL
typename enable_if_c<
is_vec<V>::value && vec_traits<V>::dim>=4,
qvm_detail::sw_<V,qvm_detail::swizzle_idx<1,qvm_detail::swizzle_idx<3,qvm_detail::swizzle_idx<1 > > > > &>::type
YWY( V & a )
{
return reinterpret_cast<qvm_detail::sw_<V,qvm_detail::swizzle_idx<1,qvm_detail::swizzle_idx<3,qvm_detail::swizzle_idx<1 > > > > &>(a);
}
template <class V>
BOOST_QVM_INLINE_TRIVIAL
typename enable_if_c<
is_vec<V>::value && vec_traits<V>::dim>=4,
qvm_detail::sw_<V,qvm_detail::swizzle_idx<0,qvm_detail::swizzle_idx<3,qvm_detail::swizzle_idx<1 > > > > const &>::type
XWY( V const & a )
{
return reinterpret_cast<qvm_detail::sw_<V,qvm_detail::swizzle_idx<0,qvm_detail::swizzle_idx<3,qvm_detail::swizzle_idx<1 > > > > const &>(a);
}
template <class V>
BOOST_QVM_INLINE_TRIVIAL
typename enable_if_c<
is_vec<V>::value && vec_traits<V>::dim>=4,
qvm_detail::sw_<V,qvm_detail::swizzle_idx<0,qvm_detail::swizzle_idx<3,qvm_detail::swizzle_idx<1 > > > > &>::type
XWY( V & a )
{
return reinterpret_cast<qvm_detail::sw_<V,qvm_detail::swizzle_idx<0,qvm_detail::swizzle_idx<3,qvm_detail::swizzle_idx<1 > > > > &>(a);
}
template <class V>
BOOST_QVM_INLINE_TRIVIAL
typename enable_if_c<
is_vec<V>::value && vec_traits<V>::dim>=3,
qvm_detail::sw_<V,qvm_detail::swizzle_idx<-2,qvm_detail::swizzle_idx<2,qvm_detail::swizzle_idx<1 > > > > const &>::type
_1ZY( V const & a )
{
return reinterpret_cast<qvm_detail::sw_<V,qvm_detail::swizzle_idx<-2,qvm_detail::swizzle_idx<2,qvm_detail::swizzle_idx<1 > > > > const &>(a);
}
template <class V>
BOOST_QVM_INLINE_TRIVIAL
typename enable_if_c<
is_vec<V>::value && vec_traits<V>::dim>=3,
qvm_detail::sw_<V,qvm_detail::swizzle_idx<-2,qvm_detail::swizzle_idx<2,qvm_detail::swizzle_idx<1 > > > > &>::type
_1ZY( V & a )
{
return reinterpret_cast<qvm_detail::sw_<V,qvm_detail::swizzle_idx<-2,qvm_detail::swizzle_idx<2,qvm_detail::swizzle_idx<1 > > > > &>(a);
}
template <class V>
BOOST_QVM_INLINE_TRIVIAL
typename enable_if_c<
is_vec<V>::value && vec_traits<V>::dim>=3,
qvm_detail::sw_<V,qvm_detail::swizzle_idx<-1,qvm_detail::swizzle_idx<2,qvm_detail::swizzle_idx<1 > > > > const &>::type
_0ZY( V const & a )
{
return reinterpret_cast<qvm_detail::sw_<V,qvm_detail::swizzle_idx<-1,qvm_detail::swizzle_idx<2,qvm_detail::swizzle_idx<1 > > > > const &>(a);
}
template <class V>
BOOST_QVM_INLINE_TRIVIAL
typename enable_if_c<
is_vec<V>::value && vec_traits<V>::dim>=3,
qvm_detail::sw_<V,qvm_detail::swizzle_idx<-1,qvm_detail::swizzle_idx<2,qvm_detail::swizzle_idx<1 > > > > &>::type
_0ZY( V & a )
{
return reinterpret_cast<qvm_detail::sw_<V,qvm_detail::swizzle_idx<-1,qvm_detail::swizzle_idx<2,qvm_detail::swizzle_idx<1 > > > > &>(a);
}
template <class V>
BOOST_QVM_INLINE_TRIVIAL
typename enable_if_c<
is_vec<V>::value && vec_traits<V>::dim>=4,
qvm_detail::sw_<V,qvm_detail::swizzle_idx<3,qvm_detail::swizzle_idx<2,qvm_detail::swizzle_idx<1 > > > > const &>::type
WZY( V const & a )
{
return reinterpret_cast<qvm_detail::sw_<V,qvm_detail::swizzle_idx<3,qvm_detail::swizzle_idx<2,qvm_detail::swizzle_idx<1 > > > > const &>(a);
}
template <class V>
BOOST_QVM_INLINE_TRIVIAL
typename enable_if_c<
is_vec<V>::value && vec_traits<V>::dim>=4,
qvm_detail::sw_<V,qvm_detail::swizzle_idx<3,qvm_detail::swizzle_idx<2,qvm_detail::swizzle_idx<1 > > > > &>::type
WZY( V & a )
{
return reinterpret_cast<qvm_detail::sw_<V,qvm_detail::swizzle_idx<3,qvm_detail::swizzle_idx<2,qvm_detail::swizzle_idx<1 > > > > &>(a);
}
template <class V>
BOOST_QVM_INLINE_TRIVIAL
typename enable_if_c<
is_vec<V>::value && vec_traits<V>::dim>=3,
qvm_detail::sw_<V,qvm_detail::swizzle_idx<2,qvm_detail::swizzle_idx<2,qvm_detail::swizzle_idx<1 > > > > const &>::type
ZZY( V const & a )
{
return reinterpret_cast<qvm_detail::sw_<V,qvm_detail::swizzle_idx<2,qvm_detail::swizzle_idx<2,qvm_detail::swizzle_idx<1 > > > > const &>(a);
}
template <class V>
BOOST_QVM_INLINE_TRIVIAL
typename enable_if_c<
is_vec<V>::value && vec_traits<V>::dim>=3,
qvm_detail::sw_<V,qvm_detail::swizzle_idx<2,qvm_detail::swizzle_idx<2,qvm_detail::swizzle_idx<1 > > > > &>::type
ZZY( V & a )
{
return reinterpret_cast<qvm_detail::sw_<V,qvm_detail::swizzle_idx<2,qvm_detail::swizzle_idx<2,qvm_detail::swizzle_idx<1 > > > > &>(a);
}
template <class V>
BOOST_QVM_INLINE_TRIVIAL
typename enable_if_c<
is_vec<V>::value && vec_traits<V>::dim>=3,
qvm_detail::sw_<V,qvm_detail::swizzle_idx<1,qvm_detail::swizzle_idx<2,qvm_detail::swizzle_idx<1 > > > > const &>::type
YZY( V const & a )
{
return reinterpret_cast<qvm_detail::sw_<V,qvm_detail::swizzle_idx<1,qvm_detail::swizzle_idx<2,qvm_detail::swizzle_idx<1 > > > > const &>(a);
}
template <class V>
BOOST_QVM_INLINE_TRIVIAL
typename enable_if_c<
is_vec<V>::value && vec_traits<V>::dim>=3,
qvm_detail::sw_<V,qvm_detail::swizzle_idx<1,qvm_detail::swizzle_idx<2,qvm_detail::swizzle_idx<1 > > > > &>::type
YZY( V & a )
{
return reinterpret_cast<qvm_detail::sw_<V,qvm_detail::swizzle_idx<1,qvm_detail::swizzle_idx<2,qvm_detail::swizzle_idx<1 > > > > &>(a);
}
template <class V>
BOOST_QVM_INLINE_TRIVIAL
typename enable_if_c<
is_vec<V>::value && vec_traits<V>::dim>=3,
qvm_detail::sw_<V,qvm_detail::swizzle_idx<0,qvm_detail::swizzle_idx<2,qvm_detail::swizzle_idx<1 > > > > const &>::type
XZY( V const & a )
{
return reinterpret_cast<qvm_detail::sw_<V,qvm_detail::swizzle_idx<0,qvm_detail::swizzle_idx<2,qvm_detail::swizzle_idx<1 > > > > const &>(a);
}
template <class V>
BOOST_QVM_INLINE_TRIVIAL
typename enable_if_c<
is_vec<V>::value && vec_traits<V>::dim>=3,
qvm_detail::sw_<V,qvm_detail::swizzle_idx<0,qvm_detail::swizzle_idx<2,qvm_detail::swizzle_idx<1 > > > > &>::type
XZY( V & a )
{
return reinterpret_cast<qvm_detail::sw_<V,qvm_detail::swizzle_idx<0,qvm_detail::swizzle_idx<2,qvm_detail::swizzle_idx<1 > > > > &>(a);
}
template <class V>
BOOST_QVM_INLINE_TRIVIAL
typename enable_if_c<
is_vec<V>::value && vec_traits<V>::dim>=2,
qvm_detail::sw_<V,qvm_detail::swizzle_idx<-2,qvm_detail::swizzle_idx<1,qvm_detail::swizzle_idx<1 > > > > const &>::type
_1YY( V const & a )
{
return reinterpret_cast<qvm_detail::sw_<V,qvm_detail::swizzle_idx<-2,qvm_detail::swizzle_idx<1,qvm_detail::swizzle_idx<1 > > > > const &>(a);
}
template <class V>
BOOST_QVM_INLINE_TRIVIAL
typename enable_if_c<
is_vec<V>::value && vec_traits<V>::dim>=2,
qvm_detail::sw_<V,qvm_detail::swizzle_idx<-2,qvm_detail::swizzle_idx<1,qvm_detail::swizzle_idx<1 > > > > &>::type
_1YY( V & a )
{
return reinterpret_cast<qvm_detail::sw_<V,qvm_detail::swizzle_idx<-2,qvm_detail::swizzle_idx<1,qvm_detail::swizzle_idx<1 > > > > &>(a);
}
template <class V>
BOOST_QVM_INLINE_TRIVIAL
typename enable_if_c<
is_vec<V>::value && vec_traits<V>::dim>=2,
qvm_detail::sw_<V,qvm_detail::swizzle_idx<-1,qvm_detail::swizzle_idx<1,qvm_detail::swizzle_idx<1 > > > > const &>::type
_0YY( V const & a )
{
return reinterpret_cast<qvm_detail::sw_<V,qvm_detail::swizzle_idx<-1,qvm_detail::swizzle_idx<1,qvm_detail::swizzle_idx<1 > > > > const &>(a);
}
template <class V>
BOOST_QVM_INLINE_TRIVIAL
typename enable_if_c<
is_vec<V>::value && vec_traits<V>::dim>=2,
qvm_detail::sw_<V,qvm_detail::swizzle_idx<-1,qvm_detail::swizzle_idx<1,qvm_detail::swizzle_idx<1 > > > > &>::type
_0YY( V & a )
{
return reinterpret_cast<qvm_detail::sw_<V,qvm_detail::swizzle_idx<-1,qvm_detail::swizzle_idx<1,qvm_detail::swizzle_idx<1 > > > > &>(a);
}
template <class V>
BOOST_QVM_INLINE_TRIVIAL
typename enable_if_c<
is_vec<V>::value && vec_traits<V>::dim>=4,
qvm_detail::sw_<V,qvm_detail::swizzle_idx<3,qvm_detail::swizzle_idx<1,qvm_detail::swizzle_idx<1 > > > > const &>::type
WYY( V const & a )
{
return reinterpret_cast<qvm_detail::sw_<V,qvm_detail::swizzle_idx<3,qvm_detail::swizzle_idx<1,qvm_detail::swizzle_idx<1 > > > > const &>(a);
}
template <class V>
BOOST_QVM_INLINE_TRIVIAL
typename enable_if_c<
is_vec<V>::value && vec_traits<V>::dim>=4,
qvm_detail::sw_<V,qvm_detail::swizzle_idx<3,qvm_detail::swizzle_idx<1,qvm_detail::swizzle_idx<1 > > > > &>::type
WYY( V & a )
{
return reinterpret_cast<qvm_detail::sw_<V,qvm_detail::swizzle_idx<3,qvm_detail::swizzle_idx<1,qvm_detail::swizzle_idx<1 > > > > &>(a);
}
template <class V>
BOOST_QVM_INLINE_TRIVIAL
typename enable_if_c<
is_vec<V>::value && vec_traits<V>::dim>=3,
qvm_detail::sw_<V,qvm_detail::swizzle_idx<2,qvm_detail::swizzle_idx<1,qvm_detail::swizzle_idx<1 > > > > const &>::type
ZYY( V const & a )
{
return reinterpret_cast<qvm_detail::sw_<V,qvm_detail::swizzle_idx<2,qvm_detail::swizzle_idx<1,qvm_detail::swizzle_idx<1 > > > > const &>(a);
}
template <class V>
BOOST_QVM_INLINE_TRIVIAL
typename enable_if_c<
is_vec<V>::value && vec_traits<V>::dim>=3,
qvm_detail::sw_<V,qvm_detail::swizzle_idx<2,qvm_detail::swizzle_idx<1,qvm_detail::swizzle_idx<1 > > > > &>::type
ZYY( V & a )
{
return reinterpret_cast<qvm_detail::sw_<V,qvm_detail::swizzle_idx<2,qvm_detail::swizzle_idx<1,qvm_detail::swizzle_idx<1 > > > > &>(a);
}
template <class V>
BOOST_QVM_INLINE_TRIVIAL
typename enable_if_c<
is_vec<V>::value && vec_traits<V>::dim>=2,
qvm_detail::sw_<V,qvm_detail::swizzle_idx<1,qvm_detail::swizzle_idx<1,qvm_detail::swizzle_idx<1 > > > > const &>::type
YYY( V const & a )
{
return reinterpret_cast<qvm_detail::sw_<V,qvm_detail::swizzle_idx<1,qvm_detail::swizzle_idx<1,qvm_detail::swizzle_idx<1 > > > > const &>(a);
}
template <class V>
BOOST_QVM_INLINE_TRIVIAL
typename enable_if_c<
is_vec<V>::value && vec_traits<V>::dim>=2,
qvm_detail::sw_<V,qvm_detail::swizzle_idx<1,qvm_detail::swizzle_idx<1,qvm_detail::swizzle_idx<1 > > > > &>::type
YYY( V & a )
{
return reinterpret_cast<qvm_detail::sw_<V,qvm_detail::swizzle_idx<1,qvm_detail::swizzle_idx<1,qvm_detail::swizzle_idx<1 > > > > &>(a);
}
template <class V>
BOOST_QVM_INLINE_TRIVIAL
typename enable_if_c<
is_vec<V>::value && vec_traits<V>::dim>=2,
qvm_detail::sw_<V,qvm_detail::swizzle_idx<0,qvm_detail::swizzle_idx<1,qvm_detail::swizzle_idx<1 > > > > const &>::type
XYY( V const & a )
{
return reinterpret_cast<qvm_detail::sw_<V,qvm_detail::swizzle_idx<0,qvm_detail::swizzle_idx<1,qvm_detail::swizzle_idx<1 > > > > const &>(a);
}
template <class V>
BOOST_QVM_INLINE_TRIVIAL
typename enable_if_c<
is_vec<V>::value && vec_traits<V>::dim>=2,
qvm_detail::sw_<V,qvm_detail::swizzle_idx<0,qvm_detail::swizzle_idx<1,qvm_detail::swizzle_idx<1 > > > > &>::type
XYY( V & a )
{
return reinterpret_cast<qvm_detail::sw_<V,qvm_detail::swizzle_idx<0,qvm_detail::swizzle_idx<1,qvm_detail::swizzle_idx<1 > > > > &>(a);
}
template <class V>
BOOST_QVM_INLINE_TRIVIAL
typename enable_if_c<
is_vec<V>::value && vec_traits<V>::dim>=2,
qvm_detail::sw_<V,qvm_detail::swizzle_idx<-2,qvm_detail::swizzle_idx<0,qvm_detail::swizzle_idx<1 > > > > const &>::type
_1XY( V const & a )
{
return reinterpret_cast<qvm_detail::sw_<V,qvm_detail::swizzle_idx<-2,qvm_detail::swizzle_idx<0,qvm_detail::swizzle_idx<1 > > > > const &>(a);
}
template <class V>
BOOST_QVM_INLINE_TRIVIAL
typename enable_if_c<
is_vec<V>::value && vec_traits<V>::dim>=2,
qvm_detail::sw_<V,qvm_detail::swizzle_idx<-2,qvm_detail::swizzle_idx<0,qvm_detail::swizzle_idx<1 > > > > &>::type
_1XY( V & a )
{
return reinterpret_cast<qvm_detail::sw_<V,qvm_detail::swizzle_idx<-2,qvm_detail::swizzle_idx<0,qvm_detail::swizzle_idx<1 > > > > &>(a);
}
template <class V>
BOOST_QVM_INLINE_TRIVIAL
typename enable_if_c<
is_vec<V>::value && vec_traits<V>::dim>=2,
qvm_detail::sw_<V,qvm_detail::swizzle_idx<-1,qvm_detail::swizzle_idx<0,qvm_detail::swizzle_idx<1 > > > > const &>::type
_0XY( V const & a )
{
return reinterpret_cast<qvm_detail::sw_<V,qvm_detail::swizzle_idx<-1,qvm_detail::swizzle_idx<0,qvm_detail::swizzle_idx<1 > > > > const &>(a);
}
template <class V>
BOOST_QVM_INLINE_TRIVIAL
typename enable_if_c<
is_vec<V>::value && vec_traits<V>::dim>=2,
qvm_detail::sw_<V,qvm_detail::swizzle_idx<-1,qvm_detail::swizzle_idx<0,qvm_detail::swizzle_idx<1 > > > > &>::type
_0XY( V & a )
{
return reinterpret_cast<qvm_detail::sw_<V,qvm_detail::swizzle_idx<-1,qvm_detail::swizzle_idx<0,qvm_detail::swizzle_idx<1 > > > > &>(a);
}
template <class V>
BOOST_QVM_INLINE_TRIVIAL
typename enable_if_c<
is_vec<V>::value && vec_traits<V>::dim>=4,
qvm_detail::sw_<V,qvm_detail::swizzle_idx<3,qvm_detail::swizzle_idx<0,qvm_detail::swizzle_idx<1 > > > > const &>::type
WXY( V const & a )
{
return reinterpret_cast<qvm_detail::sw_<V,qvm_detail::swizzle_idx<3,qvm_detail::swizzle_idx<0,qvm_detail::swizzle_idx<1 > > > > const &>(a);
}
template <class V>
BOOST_QVM_INLINE_TRIVIAL
typename enable_if_c<
is_vec<V>::value && vec_traits<V>::dim>=4,
qvm_detail::sw_<V,qvm_detail::swizzle_idx<3,qvm_detail::swizzle_idx<0,qvm_detail::swizzle_idx<1 > > > > &>::type
WXY( V & a )
{
return reinterpret_cast<qvm_detail::sw_<V,qvm_detail::swizzle_idx<3,qvm_detail::swizzle_idx<0,qvm_detail::swizzle_idx<1 > > > > &>(a);
}
template <class V>
BOOST_QVM_INLINE_TRIVIAL
typename enable_if_c<
is_vec<V>::value && vec_traits<V>::dim>=3,
qvm_detail::sw_<V,qvm_detail::swizzle_idx<2,qvm_detail::swizzle_idx<0,qvm_detail::swizzle_idx<1 > > > > const &>::type
ZXY( V const & a )
{
return reinterpret_cast<qvm_detail::sw_<V,qvm_detail::swizzle_idx<2,qvm_detail::swizzle_idx<0,qvm_detail::swizzle_idx<1 > > > > const &>(a);
}
template <class V>
BOOST_QVM_INLINE_TRIVIAL
typename enable_if_c<
is_vec<V>::value && vec_traits<V>::dim>=3,
qvm_detail::sw_<V,qvm_detail::swizzle_idx<2,qvm_detail::swizzle_idx<0,qvm_detail::swizzle_idx<1 > > > > &>::type
ZXY( V & a )
{
return reinterpret_cast<qvm_detail::sw_<V,qvm_detail::swizzle_idx<2,qvm_detail::swizzle_idx<0,qvm_detail::swizzle_idx<1 > > > > &>(a);
}
template <class V>
BOOST_QVM_INLINE_TRIVIAL
typename enable_if_c<
is_vec<V>::value && vec_traits<V>::dim>=2,
qvm_detail::sw_<V,qvm_detail::swizzle_idx<1,qvm_detail::swizzle_idx<0,qvm_detail::swizzle_idx<1 > > > > const &>::type
YXY( V const & a )
{
return reinterpret_cast<qvm_detail::sw_<V,qvm_detail::swizzle_idx<1,qvm_detail::swizzle_idx<0,qvm_detail::swizzle_idx<1 > > > > const &>(a);
}
template <class V>
BOOST_QVM_INLINE_TRIVIAL
typename enable_if_c<
is_vec<V>::value && vec_traits<V>::dim>=2,
qvm_detail::sw_<V,qvm_detail::swizzle_idx<1,qvm_detail::swizzle_idx<0,qvm_detail::swizzle_idx<1 > > > > &>::type
YXY( V & a )
{
return reinterpret_cast<qvm_detail::sw_<V,qvm_detail::swizzle_idx<1,qvm_detail::swizzle_idx<0,qvm_detail::swizzle_idx<1 > > > > &>(a);
}
template <class V>
BOOST_QVM_INLINE_TRIVIAL
typename enable_if_c<
is_vec<V>::value && vec_traits<V>::dim>=2,
qvm_detail::sw_<V,qvm_detail::swizzle_idx<0,qvm_detail::swizzle_idx<0,qvm_detail::swizzle_idx<1 > > > > const &>::type
XXY( V const & a )
{
return reinterpret_cast<qvm_detail::sw_<V,qvm_detail::swizzle_idx<0,qvm_detail::swizzle_idx<0,qvm_detail::swizzle_idx<1 > > > > const &>(a);
}
template <class V>
BOOST_QVM_INLINE_TRIVIAL
typename enable_if_c<
is_vec<V>::value && vec_traits<V>::dim>=2,
qvm_detail::sw_<V,qvm_detail::swizzle_idx<0,qvm_detail::swizzle_idx<0,qvm_detail::swizzle_idx<1 > > > > &>::type
XXY( V & a )
{
return reinterpret_cast<qvm_detail::sw_<V,qvm_detail::swizzle_idx<0,qvm_detail::swizzle_idx<0,qvm_detail::swizzle_idx<1 > > > > &>(a);
}
template <class V>
BOOST_QVM_INLINE_TRIVIAL
typename enable_if_c<
is_vec<V>::value && vec_traits<V>::dim>=1,
qvm_detail::sw_<V,qvm_detail::swizzle_idx<-2,qvm_detail::swizzle_idx<-2,qvm_detail::swizzle_idx<0 > > > > const &>::type
_11X( V const & a )
{
return reinterpret_cast<qvm_detail::sw_<V,qvm_detail::swizzle_idx<-2,qvm_detail::swizzle_idx<-2,qvm_detail::swizzle_idx<0 > > > > const &>(a);
}
template <class S>
BOOST_QVM_INLINE_TRIVIAL
typename enable_if_c<
is_scalar<S>::value,
qvm_detail::sws_<S,qvm_detail::swizzle_idx<-2,qvm_detail::swizzle_idx<-2,qvm_detail::swizzle_idx<0 > > > > const &>::type
_11X( S const & a )
{
return reinterpret_cast<qvm_detail::sws_<S,qvm_detail::swizzle_idx<-2,qvm_detail::swizzle_idx<-2,qvm_detail::swizzle_idx<0 > > > > const &>(a);
}
template <class V>
BOOST_QVM_INLINE_TRIVIAL
typename enable_if_c<
is_vec<V>::value && vec_traits<V>::dim>=1,
qvm_detail::sw_<V,qvm_detail::swizzle_idx<-2,qvm_detail::swizzle_idx<-2,qvm_detail::swizzle_idx<0 > > > > &>::type
_11X( V & a )
{
return reinterpret_cast<qvm_detail::sw_<V,qvm_detail::swizzle_idx<-2,qvm_detail::swizzle_idx<-2,qvm_detail::swizzle_idx<0 > > > > &>(a);
}
template <class S>
BOOST_QVM_INLINE_TRIVIAL
typename enable_if_c<
is_scalar<S>::value,
qvm_detail::sws_<S,qvm_detail::swizzle_idx<-2,qvm_detail::swizzle_idx<-2,qvm_detail::swizzle_idx<0 > > > > &>::type
_11X( S & a )
{
return reinterpret_cast<qvm_detail::sws_<S,qvm_detail::swizzle_idx<-2,qvm_detail::swizzle_idx<-2,qvm_detail::swizzle_idx<0 > > > > &>(a);
}
template <class V>
BOOST_QVM_INLINE_TRIVIAL
typename enable_if_c<
is_vec<V>::value && vec_traits<V>::dim>=1,
qvm_detail::sw_<V,qvm_detail::swizzle_idx<-1,qvm_detail::swizzle_idx<-2,qvm_detail::swizzle_idx<0 > > > > const &>::type
_01X( V const & a )
{
return reinterpret_cast<qvm_detail::sw_<V,qvm_detail::swizzle_idx<-1,qvm_detail::swizzle_idx<-2,qvm_detail::swizzle_idx<0 > > > > const &>(a);
}
template <class S>
BOOST_QVM_INLINE_TRIVIAL
typename enable_if_c<
is_scalar<S>::value,
qvm_detail::sws_<S,qvm_detail::swizzle_idx<-1,qvm_detail::swizzle_idx<-2,qvm_detail::swizzle_idx<0 > > > > const &>::type
_01X( S const & a )
{
return reinterpret_cast<qvm_detail::sws_<S,qvm_detail::swizzle_idx<-1,qvm_detail::swizzle_idx<-2,qvm_detail::swizzle_idx<0 > > > > const &>(a);
}
template <class V>
BOOST_QVM_INLINE_TRIVIAL
typename enable_if_c<
is_vec<V>::value && vec_traits<V>::dim>=1,
qvm_detail::sw_<V,qvm_detail::swizzle_idx<-1,qvm_detail::swizzle_idx<-2,qvm_detail::swizzle_idx<0 > > > > &>::type
_01X( V & a )
{
return reinterpret_cast<qvm_detail::sw_<V,qvm_detail::swizzle_idx<-1,qvm_detail::swizzle_idx<-2,qvm_detail::swizzle_idx<0 > > > > &>(a);
}
template <class S>
BOOST_QVM_INLINE_TRIVIAL
typename enable_if_c<
is_scalar<S>::value,
qvm_detail::sws_<S,qvm_detail::swizzle_idx<-1,qvm_detail::swizzle_idx<-2,qvm_detail::swizzle_idx<0 > > > > &>::type
_01X( S & a )
{
return reinterpret_cast<qvm_detail::sws_<S,qvm_detail::swizzle_idx<-1,qvm_detail::swizzle_idx<-2,qvm_detail::swizzle_idx<0 > > > > &>(a);
}
template <class V>
BOOST_QVM_INLINE_TRIVIAL
typename enable_if_c<
is_vec<V>::value && vec_traits<V>::dim>=4,
qvm_detail::sw_<V,qvm_detail::swizzle_idx<3,qvm_detail::swizzle_idx<-2,qvm_detail::swizzle_idx<0 > > > > const &>::type
W1X( V const & a )
{
return reinterpret_cast<qvm_detail::sw_<V,qvm_detail::swizzle_idx<3,qvm_detail::swizzle_idx<-2,qvm_detail::swizzle_idx<0 > > > > const &>(a);
}
template <class V>
BOOST_QVM_INLINE_TRIVIAL
typename enable_if_c<
is_vec<V>::value && vec_traits<V>::dim>=4,
qvm_detail::sw_<V,qvm_detail::swizzle_idx<3,qvm_detail::swizzle_idx<-2,qvm_detail::swizzle_idx<0 > > > > &>::type
W1X( V & a )
{
return reinterpret_cast<qvm_detail::sw_<V,qvm_detail::swizzle_idx<3,qvm_detail::swizzle_idx<-2,qvm_detail::swizzle_idx<0 > > > > &>(a);
}
template <class V>
BOOST_QVM_INLINE_TRIVIAL
typename enable_if_c<
is_vec<V>::value && vec_traits<V>::dim>=3,
qvm_detail::sw_<V,qvm_detail::swizzle_idx<2,qvm_detail::swizzle_idx<-2,qvm_detail::swizzle_idx<0 > > > > const &>::type
Z1X( V const & a )
{
return reinterpret_cast<qvm_detail::sw_<V,qvm_detail::swizzle_idx<2,qvm_detail::swizzle_idx<-2,qvm_detail::swizzle_idx<0 > > > > const &>(a);
}
template <class V>
BOOST_QVM_INLINE_TRIVIAL
typename enable_if_c<
is_vec<V>::value && vec_traits<V>::dim>=3,
qvm_detail::sw_<V,qvm_detail::swizzle_idx<2,qvm_detail::swizzle_idx<-2,qvm_detail::swizzle_idx<0 > > > > &>::type
Z1X( V & a )
{
return reinterpret_cast<qvm_detail::sw_<V,qvm_detail::swizzle_idx<2,qvm_detail::swizzle_idx<-2,qvm_detail::swizzle_idx<0 > > > > &>(a);
}
template <class V>
BOOST_QVM_INLINE_TRIVIAL
typename enable_if_c<
is_vec<V>::value && vec_traits<V>::dim>=2,
qvm_detail::sw_<V,qvm_detail::swizzle_idx<1,qvm_detail::swizzle_idx<-2,qvm_detail::swizzle_idx<0 > > > > const &>::type
Y1X( V const & a )
{
return reinterpret_cast<qvm_detail::sw_<V,qvm_detail::swizzle_idx<1,qvm_detail::swizzle_idx<-2,qvm_detail::swizzle_idx<0 > > > > const &>(a);
}
template <class V>
BOOST_QVM_INLINE_TRIVIAL
typename enable_if_c<
is_vec<V>::value && vec_traits<V>::dim>=2,
qvm_detail::sw_<V,qvm_detail::swizzle_idx<1,qvm_detail::swizzle_idx<-2,qvm_detail::swizzle_idx<0 > > > > &>::type
Y1X( V & a )
{
return reinterpret_cast<qvm_detail::sw_<V,qvm_detail::swizzle_idx<1,qvm_detail::swizzle_idx<-2,qvm_detail::swizzle_idx<0 > > > > &>(a);
}
template <class V>
BOOST_QVM_INLINE_TRIVIAL
typename enable_if_c<
is_vec<V>::value && vec_traits<V>::dim>=1,
qvm_detail::sw_<V,qvm_detail::swizzle_idx<0,qvm_detail::swizzle_idx<-2,qvm_detail::swizzle_idx<0 > > > > const &>::type
X1X( V const & a )
{
return reinterpret_cast<qvm_detail::sw_<V,qvm_detail::swizzle_idx<0,qvm_detail::swizzle_idx<-2,qvm_detail::swizzle_idx<0 > > > > const &>(a);
}
template <class S>
BOOST_QVM_INLINE_TRIVIAL
typename enable_if_c<
is_scalar<S>::value,
qvm_detail::sws_<S,qvm_detail::swizzle_idx<0,qvm_detail::swizzle_idx<-2,qvm_detail::swizzle_idx<0 > > > > const &>::type
X1X( S const & a )
{
return reinterpret_cast<qvm_detail::sws_<S,qvm_detail::swizzle_idx<0,qvm_detail::swizzle_idx<-2,qvm_detail::swizzle_idx<0 > > > > const &>(a);
}
template <class V>
BOOST_QVM_INLINE_TRIVIAL
typename enable_if_c<
is_vec<V>::value && vec_traits<V>::dim>=1,
qvm_detail::sw_<V,qvm_detail::swizzle_idx<0,qvm_detail::swizzle_idx<-2,qvm_detail::swizzle_idx<0 > > > > &>::type
X1X( V & a )
{
return reinterpret_cast<qvm_detail::sw_<V,qvm_detail::swizzle_idx<0,qvm_detail::swizzle_idx<-2,qvm_detail::swizzle_idx<0 > > > > &>(a);
}
template <class S>
BOOST_QVM_INLINE_TRIVIAL
typename enable_if_c<
is_scalar<S>::value,
qvm_detail::sws_<S,qvm_detail::swizzle_idx<0,qvm_detail::swizzle_idx<-2,qvm_detail::swizzle_idx<0 > > > > &>::type
X1X( S & a )
{
return reinterpret_cast<qvm_detail::sws_<S,qvm_detail::swizzle_idx<0,qvm_detail::swizzle_idx<-2,qvm_detail::swizzle_idx<0 > > > > &>(a);
}
template <class V>
BOOST_QVM_INLINE_TRIVIAL
typename enable_if_c<
is_vec<V>::value && vec_traits<V>::dim>=1,
qvm_detail::sw_<V,qvm_detail::swizzle_idx<-2,qvm_detail::swizzle_idx<-1,qvm_detail::swizzle_idx<0 > > > > const &>::type
_10X( V const & a )
{
return reinterpret_cast<qvm_detail::sw_<V,qvm_detail::swizzle_idx<-2,qvm_detail::swizzle_idx<-1,qvm_detail::swizzle_idx<0 > > > > const &>(a);
}
template <class S>
BOOST_QVM_INLINE_TRIVIAL
typename enable_if_c<
is_scalar<S>::value,
qvm_detail::sws_<S,qvm_detail::swizzle_idx<-2,qvm_detail::swizzle_idx<-1,qvm_detail::swizzle_idx<0 > > > > const &>::type
_10X( S const & a )
{
return reinterpret_cast<qvm_detail::sws_<S,qvm_detail::swizzle_idx<-2,qvm_detail::swizzle_idx<-1,qvm_detail::swizzle_idx<0 > > > > const &>(a);
}
template <class V>
BOOST_QVM_INLINE_TRIVIAL
typename enable_if_c<
is_vec<V>::value && vec_traits<V>::dim>=1,
qvm_detail::sw_<V,qvm_detail::swizzle_idx<-2,qvm_detail::swizzle_idx<-1,qvm_detail::swizzle_idx<0 > > > > &>::type
_10X( V & a )
{
return reinterpret_cast<qvm_detail::sw_<V,qvm_detail::swizzle_idx<-2,qvm_detail::swizzle_idx<-1,qvm_detail::swizzle_idx<0 > > > > &>(a);
}
template <class S>
BOOST_QVM_INLINE_TRIVIAL
typename enable_if_c<
is_scalar<S>::value,
qvm_detail::sws_<S,qvm_detail::swizzle_idx<-2,qvm_detail::swizzle_idx<-1,qvm_detail::swizzle_idx<0 > > > > &>::type
_10X( S & a )
{
return reinterpret_cast<qvm_detail::sws_<S,qvm_detail::swizzle_idx<-2,qvm_detail::swizzle_idx<-1,qvm_detail::swizzle_idx<0 > > > > &>(a);
}
template <class V>
BOOST_QVM_INLINE_TRIVIAL
typename enable_if_c<
is_vec<V>::value && vec_traits<V>::dim>=1,
qvm_detail::sw_<V,qvm_detail::swizzle_idx<-1,qvm_detail::swizzle_idx<-1,qvm_detail::swizzle_idx<0 > > > > const &>::type
_00X( V const & a )
{
return reinterpret_cast<qvm_detail::sw_<V,qvm_detail::swizzle_idx<-1,qvm_detail::swizzle_idx<-1,qvm_detail::swizzle_idx<0 > > > > const &>(a);
}
template <class S>
BOOST_QVM_INLINE_TRIVIAL
typename enable_if_c<
is_scalar<S>::value,
qvm_detail::sws_<S,qvm_detail::swizzle_idx<-1,qvm_detail::swizzle_idx<-1,qvm_detail::swizzle_idx<0 > > > > const &>::type
_00X( S const & a )
{
return reinterpret_cast<qvm_detail::sws_<S,qvm_detail::swizzle_idx<-1,qvm_detail::swizzle_idx<-1,qvm_detail::swizzle_idx<0 > > > > const &>(a);
}
template <class V>
BOOST_QVM_INLINE_TRIVIAL
typename enable_if_c<
is_vec<V>::value && vec_traits<V>::dim>=1,
qvm_detail::sw_<V,qvm_detail::swizzle_idx<-1,qvm_detail::swizzle_idx<-1,qvm_detail::swizzle_idx<0 > > > > &>::type
_00X( V & a )
{
return reinterpret_cast<qvm_detail::sw_<V,qvm_detail::swizzle_idx<-1,qvm_detail::swizzle_idx<-1,qvm_detail::swizzle_idx<0 > > > > &>(a);
}
template <class S>
BOOST_QVM_INLINE_TRIVIAL
typename enable_if_c<
is_scalar<S>::value,
qvm_detail::sws_<S,qvm_detail::swizzle_idx<-1,qvm_detail::swizzle_idx<-1,qvm_detail::swizzle_idx<0 > > > > &>::type
_00X( S & a )
{
return reinterpret_cast<qvm_detail::sws_<S,qvm_detail::swizzle_idx<-1,qvm_detail::swizzle_idx<-1,qvm_detail::swizzle_idx<0 > > > > &>(a);
}
template <class V>
BOOST_QVM_INLINE_TRIVIAL
typename enable_if_c<
is_vec<V>::value && vec_traits<V>::dim>=4,
qvm_detail::sw_<V,qvm_detail::swizzle_idx<3,qvm_detail::swizzle_idx<-1,qvm_detail::swizzle_idx<0 > > > > const &>::type
W0X( V const & a )
{
return reinterpret_cast<qvm_detail::sw_<V,qvm_detail::swizzle_idx<3,qvm_detail::swizzle_idx<-1,qvm_detail::swizzle_idx<0 > > > > const &>(a);
}
template <class V>
BOOST_QVM_INLINE_TRIVIAL
typename enable_if_c<
is_vec<V>::value && vec_traits<V>::dim>=4,
qvm_detail::sw_<V,qvm_detail::swizzle_idx<3,qvm_detail::swizzle_idx<-1,qvm_detail::swizzle_idx<0 > > > > &>::type
W0X( V & a )
{
return reinterpret_cast<qvm_detail::sw_<V,qvm_detail::swizzle_idx<3,qvm_detail::swizzle_idx<-1,qvm_detail::swizzle_idx<0 > > > > &>(a);
}
template <class V>
BOOST_QVM_INLINE_TRIVIAL
typename enable_if_c<
is_vec<V>::value && vec_traits<V>::dim>=3,
qvm_detail::sw_<V,qvm_detail::swizzle_idx<2,qvm_detail::swizzle_idx<-1,qvm_detail::swizzle_idx<0 > > > > const &>::type
Z0X( V const & a )
{
return reinterpret_cast<qvm_detail::sw_<V,qvm_detail::swizzle_idx<2,qvm_detail::swizzle_idx<-1,qvm_detail::swizzle_idx<0 > > > > const &>(a);
}
template <class V>
BOOST_QVM_INLINE_TRIVIAL
typename enable_if_c<
is_vec<V>::value && vec_traits<V>::dim>=3,
qvm_detail::sw_<V,qvm_detail::swizzle_idx<2,qvm_detail::swizzle_idx<-1,qvm_detail::swizzle_idx<0 > > > > &>::type
Z0X( V & a )
{
return reinterpret_cast<qvm_detail::sw_<V,qvm_detail::swizzle_idx<2,qvm_detail::swizzle_idx<-1,qvm_detail::swizzle_idx<0 > > > > &>(a);
}
template <class V>
BOOST_QVM_INLINE_TRIVIAL
typename enable_if_c<
is_vec<V>::value && vec_traits<V>::dim>=2,
qvm_detail::sw_<V,qvm_detail::swizzle_idx<1,qvm_detail::swizzle_idx<-1,qvm_detail::swizzle_idx<0 > > > > const &>::type
Y0X( V const & a )
{
return reinterpret_cast<qvm_detail::sw_<V,qvm_detail::swizzle_idx<1,qvm_detail::swizzle_idx<-1,qvm_detail::swizzle_idx<0 > > > > const &>(a);
}
template <class V>
BOOST_QVM_INLINE_TRIVIAL
typename enable_if_c<
is_vec<V>::value && vec_traits<V>::dim>=2,
qvm_detail::sw_<V,qvm_detail::swizzle_idx<1,qvm_detail::swizzle_idx<-1,qvm_detail::swizzle_idx<0 > > > > &>::type
Y0X( V & a )
{
return reinterpret_cast<qvm_detail::sw_<V,qvm_detail::swizzle_idx<1,qvm_detail::swizzle_idx<-1,qvm_detail::swizzle_idx<0 > > > > &>(a);
}
template <class V>
BOOST_QVM_INLINE_TRIVIAL
typename enable_if_c<
is_vec<V>::value && vec_traits<V>::dim>=1,
qvm_detail::sw_<V,qvm_detail::swizzle_idx<0,qvm_detail::swizzle_idx<-1,qvm_detail::swizzle_idx<0 > > > > const &>::type
X0X( V const & a )
{
return reinterpret_cast<qvm_detail::sw_<V,qvm_detail::swizzle_idx<0,qvm_detail::swizzle_idx<-1,qvm_detail::swizzle_idx<0 > > > > const &>(a);
}
template <class S>
BOOST_QVM_INLINE_TRIVIAL
typename enable_if_c<
is_scalar<S>::value,
qvm_detail::sws_<S,qvm_detail::swizzle_idx<0,qvm_detail::swizzle_idx<-1,qvm_detail::swizzle_idx<0 > > > > const &>::type
X0X( S const & a )
{
return reinterpret_cast<qvm_detail::sws_<S,qvm_detail::swizzle_idx<0,qvm_detail::swizzle_idx<-1,qvm_detail::swizzle_idx<0 > > > > const &>(a);
}
template <class V>
BOOST_QVM_INLINE_TRIVIAL
typename enable_if_c<
is_vec<V>::value && vec_traits<V>::dim>=1,
qvm_detail::sw_<V,qvm_detail::swizzle_idx<0,qvm_detail::swizzle_idx<-1,qvm_detail::swizzle_idx<0 > > > > &>::type
X0X( V & a )
{
return reinterpret_cast<qvm_detail::sw_<V,qvm_detail::swizzle_idx<0,qvm_detail::swizzle_idx<-1,qvm_detail::swizzle_idx<0 > > > > &>(a);
}
template <class S>
BOOST_QVM_INLINE_TRIVIAL
typename enable_if_c<
is_scalar<S>::value,
qvm_detail::sws_<S,qvm_detail::swizzle_idx<0,qvm_detail::swizzle_idx<-1,qvm_detail::swizzle_idx<0 > > > > &>::type
X0X( S & a )
{
return reinterpret_cast<qvm_detail::sws_<S,qvm_detail::swizzle_idx<0,qvm_detail::swizzle_idx<-1,qvm_detail::swizzle_idx<0 > > > > &>(a);
}
template <class V>
BOOST_QVM_INLINE_TRIVIAL
typename enable_if_c<
is_vec<V>::value && vec_traits<V>::dim>=4,
qvm_detail::sw_<V,qvm_detail::swizzle_idx<-2,qvm_detail::swizzle_idx<3,qvm_detail::swizzle_idx<0 > > > > const &>::type
_1WX( V const & a )
{
return reinterpret_cast<qvm_detail::sw_<V,qvm_detail::swizzle_idx<-2,qvm_detail::swizzle_idx<3,qvm_detail::swizzle_idx<0 > > > > const &>(a);
}
template <class V>
BOOST_QVM_INLINE_TRIVIAL
typename enable_if_c<
is_vec<V>::value && vec_traits<V>::dim>=4,
qvm_detail::sw_<V,qvm_detail::swizzle_idx<-2,qvm_detail::swizzle_idx<3,qvm_detail::swizzle_idx<0 > > > > &>::type
_1WX( V & a )
{
return reinterpret_cast<qvm_detail::sw_<V,qvm_detail::swizzle_idx<-2,qvm_detail::swizzle_idx<3,qvm_detail::swizzle_idx<0 > > > > &>(a);
}
template <class V>
BOOST_QVM_INLINE_TRIVIAL
typename enable_if_c<
is_vec<V>::value && vec_traits<V>::dim>=4,
qvm_detail::sw_<V,qvm_detail::swizzle_idx<-1,qvm_detail::swizzle_idx<3,qvm_detail::swizzle_idx<0 > > > > const &>::type
_0WX( V const & a )
{
return reinterpret_cast<qvm_detail::sw_<V,qvm_detail::swizzle_idx<-1,qvm_detail::swizzle_idx<3,qvm_detail::swizzle_idx<0 > > > > const &>(a);
}
template <class V>
BOOST_QVM_INLINE_TRIVIAL
typename enable_if_c<
is_vec<V>::value && vec_traits<V>::dim>=4,
qvm_detail::sw_<V,qvm_detail::swizzle_idx<-1,qvm_detail::swizzle_idx<3,qvm_detail::swizzle_idx<0 > > > > &>::type
_0WX( V & a )
{
return reinterpret_cast<qvm_detail::sw_<V,qvm_detail::swizzle_idx<-1,qvm_detail::swizzle_idx<3,qvm_detail::swizzle_idx<0 > > > > &>(a);
}
template <class V>
BOOST_QVM_INLINE_TRIVIAL
typename enable_if_c<
is_vec<V>::value && vec_traits<V>::dim>=4,
qvm_detail::sw_<V,qvm_detail::swizzle_idx<3,qvm_detail::swizzle_idx<3,qvm_detail::swizzle_idx<0 > > > > const &>::type
WWX( V const & a )
{
return reinterpret_cast<qvm_detail::sw_<V,qvm_detail::swizzle_idx<3,qvm_detail::swizzle_idx<3,qvm_detail::swizzle_idx<0 > > > > const &>(a);
}
template <class V>
BOOST_QVM_INLINE_TRIVIAL
typename enable_if_c<
is_vec<V>::value && vec_traits<V>::dim>=4,
qvm_detail::sw_<V,qvm_detail::swizzle_idx<3,qvm_detail::swizzle_idx<3,qvm_detail::swizzle_idx<0 > > > > &>::type
WWX( V & a )
{
return reinterpret_cast<qvm_detail::sw_<V,qvm_detail::swizzle_idx<3,qvm_detail::swizzle_idx<3,qvm_detail::swizzle_idx<0 > > > > &>(a);
}
template <class V>
BOOST_QVM_INLINE_TRIVIAL
typename enable_if_c<
is_vec<V>::value && vec_traits<V>::dim>=4,
qvm_detail::sw_<V,qvm_detail::swizzle_idx<2,qvm_detail::swizzle_idx<3,qvm_detail::swizzle_idx<0 > > > > const &>::type
ZWX( V const & a )
{
return reinterpret_cast<qvm_detail::sw_<V,qvm_detail::swizzle_idx<2,qvm_detail::swizzle_idx<3,qvm_detail::swizzle_idx<0 > > > > const &>(a);
}
template <class V>
BOOST_QVM_INLINE_TRIVIAL
typename enable_if_c<
is_vec<V>::value && vec_traits<V>::dim>=4,
qvm_detail::sw_<V,qvm_detail::swizzle_idx<2,qvm_detail::swizzle_idx<3,qvm_detail::swizzle_idx<0 > > > > &>::type
ZWX( V & a )
{
return reinterpret_cast<qvm_detail::sw_<V,qvm_detail::swizzle_idx<2,qvm_detail::swizzle_idx<3,qvm_detail::swizzle_idx<0 > > > > &>(a);
}
template <class V>
BOOST_QVM_INLINE_TRIVIAL
typename enable_if_c<
is_vec<V>::value && vec_traits<V>::dim>=4,
qvm_detail::sw_<V,qvm_detail::swizzle_idx<1,qvm_detail::swizzle_idx<3,qvm_detail::swizzle_idx<0 > > > > const &>::type
YWX( V const & a )
{
return reinterpret_cast<qvm_detail::sw_<V,qvm_detail::swizzle_idx<1,qvm_detail::swizzle_idx<3,qvm_detail::swizzle_idx<0 > > > > const &>(a);
}
template <class V>
BOOST_QVM_INLINE_TRIVIAL
typename enable_if_c<
is_vec<V>::value && vec_traits<V>::dim>=4,
qvm_detail::sw_<V,qvm_detail::swizzle_idx<1,qvm_detail::swizzle_idx<3,qvm_detail::swizzle_idx<0 > > > > &>::type
YWX( V & a )
{
return reinterpret_cast<qvm_detail::sw_<V,qvm_detail::swizzle_idx<1,qvm_detail::swizzle_idx<3,qvm_detail::swizzle_idx<0 > > > > &>(a);
}
template <class V>
BOOST_QVM_INLINE_TRIVIAL
typename enable_if_c<
is_vec<V>::value && vec_traits<V>::dim>=4,
qvm_detail::sw_<V,qvm_detail::swizzle_idx<0,qvm_detail::swizzle_idx<3,qvm_detail::swizzle_idx<0 > > > > const &>::type
XWX( V const & a )
{
return reinterpret_cast<qvm_detail::sw_<V,qvm_detail::swizzle_idx<0,qvm_detail::swizzle_idx<3,qvm_detail::swizzle_idx<0 > > > > const &>(a);
}
template <class V>
BOOST_QVM_INLINE_TRIVIAL
typename enable_if_c<
is_vec<V>::value && vec_traits<V>::dim>=4,
qvm_detail::sw_<V,qvm_detail::swizzle_idx<0,qvm_detail::swizzle_idx<3,qvm_detail::swizzle_idx<0 > > > > &>::type
XWX( V & a )
{
return reinterpret_cast<qvm_detail::sw_<V,qvm_detail::swizzle_idx<0,qvm_detail::swizzle_idx<3,qvm_detail::swizzle_idx<0 > > > > &>(a);
}
template <class V>
BOOST_QVM_INLINE_TRIVIAL
typename enable_if_c<
is_vec<V>::value && vec_traits<V>::dim>=3,
qvm_detail::sw_<V,qvm_detail::swizzle_idx<-2,qvm_detail::swizzle_idx<2,qvm_detail::swizzle_idx<0 > > > > const &>::type
_1ZX( V const & a )
{
return reinterpret_cast<qvm_detail::sw_<V,qvm_detail::swizzle_idx<-2,qvm_detail::swizzle_idx<2,qvm_detail::swizzle_idx<0 > > > > const &>(a);
}
template <class V>
BOOST_QVM_INLINE_TRIVIAL
typename enable_if_c<
is_vec<V>::value && vec_traits<V>::dim>=3,
qvm_detail::sw_<V,qvm_detail::swizzle_idx<-2,qvm_detail::swizzle_idx<2,qvm_detail::swizzle_idx<0 > > > > &>::type
_1ZX( V & a )
{
return reinterpret_cast<qvm_detail::sw_<V,qvm_detail::swizzle_idx<-2,qvm_detail::swizzle_idx<2,qvm_detail::swizzle_idx<0 > > > > &>(a);
}
template <class V>
BOOST_QVM_INLINE_TRIVIAL
typename enable_if_c<
is_vec<V>::value && vec_traits<V>::dim>=3,
qvm_detail::sw_<V,qvm_detail::swizzle_idx<-1,qvm_detail::swizzle_idx<2,qvm_detail::swizzle_idx<0 > > > > const &>::type
_0ZX( V const & a )
{
return reinterpret_cast<qvm_detail::sw_<V,qvm_detail::swizzle_idx<-1,qvm_detail::swizzle_idx<2,qvm_detail::swizzle_idx<0 > > > > const &>(a);
}
template <class V>
BOOST_QVM_INLINE_TRIVIAL
typename enable_if_c<
is_vec<V>::value && vec_traits<V>::dim>=3,
qvm_detail::sw_<V,qvm_detail::swizzle_idx<-1,qvm_detail::swizzle_idx<2,qvm_detail::swizzle_idx<0 > > > > &>::type
_0ZX( V & a )
{
return reinterpret_cast<qvm_detail::sw_<V,qvm_detail::swizzle_idx<-1,qvm_detail::swizzle_idx<2,qvm_detail::swizzle_idx<0 > > > > &>(a);
}
template <class V>
BOOST_QVM_INLINE_TRIVIAL
typename enable_if_c<
is_vec<V>::value && vec_traits<V>::dim>=4,
qvm_detail::sw_<V,qvm_detail::swizzle_idx<3,qvm_detail::swizzle_idx<2,qvm_detail::swizzle_idx<0 > > > > const &>::type
WZX( V const & a )
{
return reinterpret_cast<qvm_detail::sw_<V,qvm_detail::swizzle_idx<3,qvm_detail::swizzle_idx<2,qvm_detail::swizzle_idx<0 > > > > const &>(a);
}
template <class V>
BOOST_QVM_INLINE_TRIVIAL
typename enable_if_c<
is_vec<V>::value && vec_traits<V>::dim>=4,
qvm_detail::sw_<V,qvm_detail::swizzle_idx<3,qvm_detail::swizzle_idx<2,qvm_detail::swizzle_idx<0 > > > > &>::type
WZX( V & a )
{
return reinterpret_cast<qvm_detail::sw_<V,qvm_detail::swizzle_idx<3,qvm_detail::swizzle_idx<2,qvm_detail::swizzle_idx<0 > > > > &>(a);
}
template <class V>
BOOST_QVM_INLINE_TRIVIAL
typename enable_if_c<
is_vec<V>::value && vec_traits<V>::dim>=3,
qvm_detail::sw_<V,qvm_detail::swizzle_idx<2,qvm_detail::swizzle_idx<2,qvm_detail::swizzle_idx<0 > > > > const &>::type
ZZX( V const & a )
{
return reinterpret_cast<qvm_detail::sw_<V,qvm_detail::swizzle_idx<2,qvm_detail::swizzle_idx<2,qvm_detail::swizzle_idx<0 > > > > const &>(a);
}
template <class V>
BOOST_QVM_INLINE_TRIVIAL
typename enable_if_c<
is_vec<V>::value && vec_traits<V>::dim>=3,
qvm_detail::sw_<V,qvm_detail::swizzle_idx<2,qvm_detail::swizzle_idx<2,qvm_detail::swizzle_idx<0 > > > > &>::type
ZZX( V & a )
{
return reinterpret_cast<qvm_detail::sw_<V,qvm_detail::swizzle_idx<2,qvm_detail::swizzle_idx<2,qvm_detail::swizzle_idx<0 > > > > &>(a);
}
template <class V>
BOOST_QVM_INLINE_TRIVIAL
typename enable_if_c<
is_vec<V>::value && vec_traits<V>::dim>=3,
qvm_detail::sw_<V,qvm_detail::swizzle_idx<1,qvm_detail::swizzle_idx<2,qvm_detail::swizzle_idx<0 > > > > const &>::type
YZX( V const & a )
{
return reinterpret_cast<qvm_detail::sw_<V,qvm_detail::swizzle_idx<1,qvm_detail::swizzle_idx<2,qvm_detail::swizzle_idx<0 > > > > const &>(a);
}
template <class V>
BOOST_QVM_INLINE_TRIVIAL
typename enable_if_c<
is_vec<V>::value && vec_traits<V>::dim>=3,
qvm_detail::sw_<V,qvm_detail::swizzle_idx<1,qvm_detail::swizzle_idx<2,qvm_detail::swizzle_idx<0 > > > > &>::type
YZX( V & a )
{
return reinterpret_cast<qvm_detail::sw_<V,qvm_detail::swizzle_idx<1,qvm_detail::swizzle_idx<2,qvm_detail::swizzle_idx<0 > > > > &>(a);
}
template <class V>
BOOST_QVM_INLINE_TRIVIAL
typename enable_if_c<
is_vec<V>::value && vec_traits<V>::dim>=3,
qvm_detail::sw_<V,qvm_detail::swizzle_idx<0,qvm_detail::swizzle_idx<2,qvm_detail::swizzle_idx<0 > > > > const &>::type
XZX( V const & a )
{
return reinterpret_cast<qvm_detail::sw_<V,qvm_detail::swizzle_idx<0,qvm_detail::swizzle_idx<2,qvm_detail::swizzle_idx<0 > > > > const &>(a);
}
template <class V>
BOOST_QVM_INLINE_TRIVIAL
typename enable_if_c<
is_vec<V>::value && vec_traits<V>::dim>=3,
qvm_detail::sw_<V,qvm_detail::swizzle_idx<0,qvm_detail::swizzle_idx<2,qvm_detail::swizzle_idx<0 > > > > &>::type
XZX( V & a )
{
return reinterpret_cast<qvm_detail::sw_<V,qvm_detail::swizzle_idx<0,qvm_detail::swizzle_idx<2,qvm_detail::swizzle_idx<0 > > > > &>(a);
}
template <class V>
BOOST_QVM_INLINE_TRIVIAL
typename enable_if_c<
is_vec<V>::value && vec_traits<V>::dim>=2,
qvm_detail::sw_<V,qvm_detail::swizzle_idx<-2,qvm_detail::swizzle_idx<1,qvm_detail::swizzle_idx<0 > > > > const &>::type
_1YX( V const & a )
{
return reinterpret_cast<qvm_detail::sw_<V,qvm_detail::swizzle_idx<-2,qvm_detail::swizzle_idx<1,qvm_detail::swizzle_idx<0 > > > > const &>(a);
}
template <class V>
BOOST_QVM_INLINE_TRIVIAL
typename enable_if_c<
is_vec<V>::value && vec_traits<V>::dim>=2,
qvm_detail::sw_<V,qvm_detail::swizzle_idx<-2,qvm_detail::swizzle_idx<1,qvm_detail::swizzle_idx<0 > > > > &>::type
_1YX( V & a )
{
return reinterpret_cast<qvm_detail::sw_<V,qvm_detail::swizzle_idx<-2,qvm_detail::swizzle_idx<1,qvm_detail::swizzle_idx<0 > > > > &>(a);
}
template <class V>
BOOST_QVM_INLINE_TRIVIAL
typename enable_if_c<
is_vec<V>::value && vec_traits<V>::dim>=2,
qvm_detail::sw_<V,qvm_detail::swizzle_idx<-1,qvm_detail::swizzle_idx<1,qvm_detail::swizzle_idx<0 > > > > const &>::type
_0YX( V const & a )
{
return reinterpret_cast<qvm_detail::sw_<V,qvm_detail::swizzle_idx<-1,qvm_detail::swizzle_idx<1,qvm_detail::swizzle_idx<0 > > > > const &>(a);
}
template <class V>
BOOST_QVM_INLINE_TRIVIAL
typename enable_if_c<
is_vec<V>::value && vec_traits<V>::dim>=2,
qvm_detail::sw_<V,qvm_detail::swizzle_idx<-1,qvm_detail::swizzle_idx<1,qvm_detail::swizzle_idx<0 > > > > &>::type
_0YX( V & a )
{
return reinterpret_cast<qvm_detail::sw_<V,qvm_detail::swizzle_idx<-1,qvm_detail::swizzle_idx<1,qvm_detail::swizzle_idx<0 > > > > &>(a);
}
template <class V>
BOOST_QVM_INLINE_TRIVIAL
typename enable_if_c<
is_vec<V>::value && vec_traits<V>::dim>=4,
qvm_detail::sw_<V,qvm_detail::swizzle_idx<3,qvm_detail::swizzle_idx<1,qvm_detail::swizzle_idx<0 > > > > const &>::type
WYX( V const & a )
{
return reinterpret_cast<qvm_detail::sw_<V,qvm_detail::swizzle_idx<3,qvm_detail::swizzle_idx<1,qvm_detail::swizzle_idx<0 > > > > const &>(a);
}
template <class V>
BOOST_QVM_INLINE_TRIVIAL
typename enable_if_c<
is_vec<V>::value && vec_traits<V>::dim>=4,
qvm_detail::sw_<V,qvm_detail::swizzle_idx<3,qvm_detail::swizzle_idx<1,qvm_detail::swizzle_idx<0 > > > > &>::type
WYX( V & a )
{
return reinterpret_cast<qvm_detail::sw_<V,qvm_detail::swizzle_idx<3,qvm_detail::swizzle_idx<1,qvm_detail::swizzle_idx<0 > > > > &>(a);
}
template <class V>
BOOST_QVM_INLINE_TRIVIAL
typename enable_if_c<
is_vec<V>::value && vec_traits<V>::dim>=3,
qvm_detail::sw_<V,qvm_detail::swizzle_idx<2,qvm_detail::swizzle_idx<1,qvm_detail::swizzle_idx<0 > > > > const &>::type
ZYX( V const & a )
{
return reinterpret_cast<qvm_detail::sw_<V,qvm_detail::swizzle_idx<2,qvm_detail::swizzle_idx<1,qvm_detail::swizzle_idx<0 > > > > const &>(a);
}
template <class V>
BOOST_QVM_INLINE_TRIVIAL
typename enable_if_c<
is_vec<V>::value && vec_traits<V>::dim>=3,
qvm_detail::sw_<V,qvm_detail::swizzle_idx<2,qvm_detail::swizzle_idx<1,qvm_detail::swizzle_idx<0 > > > > &>::type
ZYX( V & a )
{
return reinterpret_cast<qvm_detail::sw_<V,qvm_detail::swizzle_idx<2,qvm_detail::swizzle_idx<1,qvm_detail::swizzle_idx<0 > > > > &>(a);
}
template <class V>
BOOST_QVM_INLINE_TRIVIAL
typename enable_if_c<
is_vec<V>::value && vec_traits<V>::dim>=2,
qvm_detail::sw_<V,qvm_detail::swizzle_idx<1,qvm_detail::swizzle_idx<1,qvm_detail::swizzle_idx<0 > > > > const &>::type
YYX( V const & a )
{
return reinterpret_cast<qvm_detail::sw_<V,qvm_detail::swizzle_idx<1,qvm_detail::swizzle_idx<1,qvm_detail::swizzle_idx<0 > > > > const &>(a);
}
template <class V>
BOOST_QVM_INLINE_TRIVIAL
typename enable_if_c<
is_vec<V>::value && vec_traits<V>::dim>=2,
qvm_detail::sw_<V,qvm_detail::swizzle_idx<1,qvm_detail::swizzle_idx<1,qvm_detail::swizzle_idx<0 > > > > &>::type
YYX( V & a )
{
return reinterpret_cast<qvm_detail::sw_<V,qvm_detail::swizzle_idx<1,qvm_detail::swizzle_idx<1,qvm_detail::swizzle_idx<0 > > > > &>(a);
}
template <class V>
BOOST_QVM_INLINE_TRIVIAL
typename enable_if_c<
is_vec<V>::value && vec_traits<V>::dim>=2,
qvm_detail::sw_<V,qvm_detail::swizzle_idx<0,qvm_detail::swizzle_idx<1,qvm_detail::swizzle_idx<0 > > > > const &>::type
XYX( V const & a )
{
return reinterpret_cast<qvm_detail::sw_<V,qvm_detail::swizzle_idx<0,qvm_detail::swizzle_idx<1,qvm_detail::swizzle_idx<0 > > > > const &>(a);
}
template <class V>
BOOST_QVM_INLINE_TRIVIAL
typename enable_if_c<
is_vec<V>::value && vec_traits<V>::dim>=2,
qvm_detail::sw_<V,qvm_detail::swizzle_idx<0,qvm_detail::swizzle_idx<1,qvm_detail::swizzle_idx<0 > > > > &>::type
XYX( V & a )
{
return reinterpret_cast<qvm_detail::sw_<V,qvm_detail::swizzle_idx<0,qvm_detail::swizzle_idx<1,qvm_detail::swizzle_idx<0 > > > > &>(a);
}
template <class V>
BOOST_QVM_INLINE_TRIVIAL
typename enable_if_c<
is_vec<V>::value && vec_traits<V>::dim>=1,
qvm_detail::sw_<V,qvm_detail::swizzle_idx<-2,qvm_detail::swizzle_idx<0,qvm_detail::swizzle_idx<0 > > > > const &>::type
_1XX( V const & a )
{
return reinterpret_cast<qvm_detail::sw_<V,qvm_detail::swizzle_idx<-2,qvm_detail::swizzle_idx<0,qvm_detail::swizzle_idx<0 > > > > const &>(a);
}
template <class S>
BOOST_QVM_INLINE_TRIVIAL
typename enable_if_c<
is_scalar<S>::value,
qvm_detail::sws_<S,qvm_detail::swizzle_idx<-2,qvm_detail::swizzle_idx<0,qvm_detail::swizzle_idx<0 > > > > const &>::type
_1XX( S const & a )
{
return reinterpret_cast<qvm_detail::sws_<S,qvm_detail::swizzle_idx<-2,qvm_detail::swizzle_idx<0,qvm_detail::swizzle_idx<0 > > > > const &>(a);
}
template <class V>
BOOST_QVM_INLINE_TRIVIAL
typename enable_if_c<
is_vec<V>::value && vec_traits<V>::dim>=1,
qvm_detail::sw_<V,qvm_detail::swizzle_idx<-2,qvm_detail::swizzle_idx<0,qvm_detail::swizzle_idx<0 > > > > &>::type
_1XX( V & a )
{
return reinterpret_cast<qvm_detail::sw_<V,qvm_detail::swizzle_idx<-2,qvm_detail::swizzle_idx<0,qvm_detail::swizzle_idx<0 > > > > &>(a);
}
template <class S>
BOOST_QVM_INLINE_TRIVIAL
typename enable_if_c<
is_scalar<S>::value,
qvm_detail::sws_<S,qvm_detail::swizzle_idx<-2,qvm_detail::swizzle_idx<0,qvm_detail::swizzle_idx<0 > > > > &>::type
_1XX( S & a )
{
return reinterpret_cast<qvm_detail::sws_<S,qvm_detail::swizzle_idx<-2,qvm_detail::swizzle_idx<0,qvm_detail::swizzle_idx<0 > > > > &>(a);
}
template <class V>
BOOST_QVM_INLINE_TRIVIAL
typename enable_if_c<
is_vec<V>::value && vec_traits<V>::dim>=1,
qvm_detail::sw_<V,qvm_detail::swizzle_idx<-1,qvm_detail::swizzle_idx<0,qvm_detail::swizzle_idx<0 > > > > const &>::type
_0XX( V const & a )
{
return reinterpret_cast<qvm_detail::sw_<V,qvm_detail::swizzle_idx<-1,qvm_detail::swizzle_idx<0,qvm_detail::swizzle_idx<0 > > > > const &>(a);
}
template <class S>
BOOST_QVM_INLINE_TRIVIAL
typename enable_if_c<
is_scalar<S>::value,
qvm_detail::sws_<S,qvm_detail::swizzle_idx<-1,qvm_detail::swizzle_idx<0,qvm_detail::swizzle_idx<0 > > > > const &>::type
_0XX( S const & a )
{
return reinterpret_cast<qvm_detail::sws_<S,qvm_detail::swizzle_idx<-1,qvm_detail::swizzle_idx<0,qvm_detail::swizzle_idx<0 > > > > const &>(a);
}
template <class V>
BOOST_QVM_INLINE_TRIVIAL
typename enable_if_c<
is_vec<V>::value && vec_traits<V>::dim>=1,
qvm_detail::sw_<V,qvm_detail::swizzle_idx<-1,qvm_detail::swizzle_idx<0,qvm_detail::swizzle_idx<0 > > > > &>::type
_0XX( V & a )
{
return reinterpret_cast<qvm_detail::sw_<V,qvm_detail::swizzle_idx<-1,qvm_detail::swizzle_idx<0,qvm_detail::swizzle_idx<0 > > > > &>(a);
}
template <class S>
BOOST_QVM_INLINE_TRIVIAL
typename enable_if_c<
is_scalar<S>::value,
qvm_detail::sws_<S,qvm_detail::swizzle_idx<-1,qvm_detail::swizzle_idx<0,qvm_detail::swizzle_idx<0 > > > > &>::type
_0XX( S & a )
{
return reinterpret_cast<qvm_detail::sws_<S,qvm_detail::swizzle_idx<-1,qvm_detail::swizzle_idx<0,qvm_detail::swizzle_idx<0 > > > > &>(a);
}
template <class V>
BOOST_QVM_INLINE_TRIVIAL
typename enable_if_c<
is_vec<V>::value && vec_traits<V>::dim>=4,
qvm_detail::sw_<V,qvm_detail::swizzle_idx<3,qvm_detail::swizzle_idx<0,qvm_detail::swizzle_idx<0 > > > > const &>::type
WXX( V const & a )
{
return reinterpret_cast<qvm_detail::sw_<V,qvm_detail::swizzle_idx<3,qvm_detail::swizzle_idx<0,qvm_detail::swizzle_idx<0 > > > > const &>(a);
}
template <class V>
BOOST_QVM_INLINE_TRIVIAL
typename enable_if_c<
is_vec<V>::value && vec_traits<V>::dim>=4,
qvm_detail::sw_<V,qvm_detail::swizzle_idx<3,qvm_detail::swizzle_idx<0,qvm_detail::swizzle_idx<0 > > > > &>::type
WXX( V & a )
{
return reinterpret_cast<qvm_detail::sw_<V,qvm_detail::swizzle_idx<3,qvm_detail::swizzle_idx<0,qvm_detail::swizzle_idx<0 > > > > &>(a);
}
template <class V>
BOOST_QVM_INLINE_TRIVIAL
typename enable_if_c<
is_vec<V>::value && vec_traits<V>::dim>=3,
qvm_detail::sw_<V,qvm_detail::swizzle_idx<2,qvm_detail::swizzle_idx<0,qvm_detail::swizzle_idx<0 > > > > const &>::type
ZXX( V const & a )
{
return reinterpret_cast<qvm_detail::sw_<V,qvm_detail::swizzle_idx<2,qvm_detail::swizzle_idx<0,qvm_detail::swizzle_idx<0 > > > > const &>(a);
}
template <class V>
BOOST_QVM_INLINE_TRIVIAL
typename enable_if_c<
is_vec<V>::value && vec_traits<V>::dim>=3,
qvm_detail::sw_<V,qvm_detail::swizzle_idx<2,qvm_detail::swizzle_idx<0,qvm_detail::swizzle_idx<0 > > > > &>::type
ZXX( V & a )
{
return reinterpret_cast<qvm_detail::sw_<V,qvm_detail::swizzle_idx<2,qvm_detail::swizzle_idx<0,qvm_detail::swizzle_idx<0 > > > > &>(a);
}
template <class V>
BOOST_QVM_INLINE_TRIVIAL
typename enable_if_c<
is_vec<V>::value && vec_traits<V>::dim>=2,
qvm_detail::sw_<V,qvm_detail::swizzle_idx<1,qvm_detail::swizzle_idx<0,qvm_detail::swizzle_idx<0 > > > > const &>::type
YXX( V const & a )
{
return reinterpret_cast<qvm_detail::sw_<V,qvm_detail::swizzle_idx<1,qvm_detail::swizzle_idx<0,qvm_detail::swizzle_idx<0 > > > > const &>(a);
}
template <class V>
BOOST_QVM_INLINE_TRIVIAL
typename enable_if_c<
is_vec<V>::value && vec_traits<V>::dim>=2,
qvm_detail::sw_<V,qvm_detail::swizzle_idx<1,qvm_detail::swizzle_idx<0,qvm_detail::swizzle_idx<0 > > > > &>::type
YXX( V & a )
{
return reinterpret_cast<qvm_detail::sw_<V,qvm_detail::swizzle_idx<1,qvm_detail::swizzle_idx<0,qvm_detail::swizzle_idx<0 > > > > &>(a);
}
template <class V>
BOOST_QVM_INLINE_TRIVIAL
typename enable_if_c<
is_vec<V>::value && vec_traits<V>::dim>=1,
qvm_detail::sw_<V,qvm_detail::swizzle_idx<0,qvm_detail::swizzle_idx<0,qvm_detail::swizzle_idx<0 > > > > const &>::type
XXX( V const & a )
{
return reinterpret_cast<qvm_detail::sw_<V,qvm_detail::swizzle_idx<0,qvm_detail::swizzle_idx<0,qvm_detail::swizzle_idx<0 > > > > const &>(a);
}
template <class S>
BOOST_QVM_INLINE_TRIVIAL
typename enable_if_c<
is_scalar<S>::value,
qvm_detail::sws_<S,qvm_detail::swizzle_idx<0,qvm_detail::swizzle_idx<0,qvm_detail::swizzle_idx<0 > > > > const &>::type
XXX( S const & a )
{
return reinterpret_cast<qvm_detail::sws_<S,qvm_detail::swizzle_idx<0,qvm_detail::swizzle_idx<0,qvm_detail::swizzle_idx<0 > > > > const &>(a);
}
template <class V>
BOOST_QVM_INLINE_TRIVIAL
typename enable_if_c<
is_vec<V>::value && vec_traits<V>::dim>=1,
qvm_detail::sw_<V,qvm_detail::swizzle_idx<0,qvm_detail::swizzle_idx<0,qvm_detail::swizzle_idx<0 > > > > &>::type
XXX( V & a )
{
return reinterpret_cast<qvm_detail::sw_<V,qvm_detail::swizzle_idx<0,qvm_detail::swizzle_idx<0,qvm_detail::swizzle_idx<0 > > > > &>(a);
}
template <class S>
BOOST_QVM_INLINE_TRIVIAL
typename enable_if_c<
is_scalar<S>::value,
qvm_detail::sws_<S,qvm_detail::swizzle_idx<0,qvm_detail::swizzle_idx<0,qvm_detail::swizzle_idx<0 > > > > &>::type
XXX( S & a )
{
return reinterpret_cast<qvm_detail::sws_<S,qvm_detail::swizzle_idx<0,qvm_detail::swizzle_idx<0,qvm_detail::swizzle_idx<0 > > > > &>(a);
}
}
}
#endif
```
|
Fernando Toro (born January 31, 1941 in Santiago, Chile) is a retired US Hall of Fame Thoroughbred horse racing jockey about whom Santa Anita Park called one of Southern California's most successful jockeys in the 1970s and '80s.
On November 19, 1956, Fernando Toro won the first race of his riding career at the Club Hípico de Santiago in Santiago, Chile. He was the leading rider in Chile when he decided to emigrate to the United States in 1966 where he would retire from riding in 1990 having won 3,555 North American races.
In 1975, Fernando Toro was voted the George Woolf Memorial Jockey Award. The award has been given annually since 1950 to a thoroughbred horse racing jockey in North America who demonstrates high standards of personal and professional conduct both on and off the racetrack.
Widely respected for his expertise in turf races, among his many successes Fernando Toro rode the filly Royal Heroine to victory in the 1984 inaugural running of the Breeders' Cup Mile.
In 2023, Toro was inducted into the National Museum of Racing and Hall of Fame as a selection by the Historic Review Committee. Since he was unable to make the journey from California to Saratoga Springs for the induction ceremony, Toro will receive his Hall of Fame jacket and plaque at Del Mar on August 19, 2023.
References
1941 births
Living people
American jockeys
Chilean jockeys
Sportspeople from Santiago
Chilean emigrants to the United States
Sportspeople from California
|
```smalltalk
"
Exception for signaling login failures of protocol clients.
"
Class {
#name : 'LoginFailedException',
#superclass : 'ProtocolClientError',
#category : 'Network-Protocols-Exceptions',
#package : 'Network-Protocols',
#tag : 'Exceptions'
}
{ #category : 'testing' }
LoginFailedException >> isResumable [
"Resumable so we can give the user another chance to login"
^ true
]
```
|
```batchfile
./configure --without-cuda
make
```
|
The United States Navy reclassified many of its surface vessels in 1975, changing terminology and hull classification symbols for cruisers, frigates, and ocean escorts.
Classification prior to 1975
From the 1950s to 1975, the US Navy had three types of fast task force escorts and one type of convoy escort. The task force escorts were cruisers (hull classification symbols CAG/CLG/CG), frigates or destroyer-leaders (DL/DLG), and destroyers (DD/DDG); the convoy escorts were ocean escorts (DE/DEG), often called destroyer escorts as they retained the designation and number series of the World War II vessels. Added in the early 1970s was a new ocean escort called the patrol frigate (PF), another designation previously used in World War II, which was the initial designation of the . In 1975, these classifications were simplified to cruiser (CG), destroyer (DD/DDG), and frigate (FF/FFG).
Under the pre-1975 classification, cruisers were large vessels, the size of World War II gun cruisers, intended as the primary surface combatants. All but one () were converted World War II gun cruisers (CL/CLG or CA/CAG), carrying either Talos or Terrier surface-to-air missiles (SAMs), and in some cases also Tartar missiles. The primary mission of these ships and the guided missile frigates was to intercept Soviet anti-ship cruise missiles. One cruiser was to be assigned to each carrier group. Most of the cruiser conversions were performed to rapidly deploy the new naval SAMs while the guided missile frigates were being designed and built. There were relatively few cruiser conversions, due to their cost and because the frigates could carry almost as many weapons as a cruiser.
From 1950 to 1975, frigates were a new type, midway between cruiser and destroyer sizes, intended as major task force escorts. The first ship of the type was a redesignated ASW cruiser; the next four were very large AAW (gun) destroyers (DL), and the remainder were essentially oversize guided missile destroyers classified as DLGs. They carried the mid-range Terrier missile, but no offensive (strategic) weapons.
Destroyers were developed from the World War II designs as the smallest fast task force escorts. DDs were fast ASW ships; DDGs were AAW ships carrying the short-range Tartar missile.
Ocean escorts were an evolution of the World War II destroyer escort types. They were intended as convoy escorts and were designed for mobilization production in wartime or low-cost mass production in peacetime. DEs were ASW vessels; DEGs were AAW vessels with Tartar missiles.
The U.S. frigate classification was not used by any other navy; similar vessels were either cruisers or destroyers in foreign service. The ocean escort type corresponded to foreign frigates (convoy escorts).
The "cruiser gap"
The Soviets defined "guided missile cruisers" as large warships armed with long range anti-ship missiles. The term "cruiser" included also two large helicopter carriers (Moskva class). The ships equivalent to U.S. frigates were classified as "large anti-submarine ships", but the larger of them were designated as "cruisers" by Western navies. This led to a conclusion, that by 1974, there were only six ships in U.S. service classified as cruisers, but the Soviets had 19 cruisers in service with seven more being built. (All totals exclude gun-only cruisers). All but two of the Soviet ships were relatively small vessels, roughly equivalent to U.S. frigates and far smaller than U.S. cruisers. However, most included a heavy anti-ship cruise missile battery that US surface combatants lacked until the introduction of the Harpoon missile circa 1980.
The differing U.S. and Soviet definitions of "cruiser" caused political problems when comparisons were made between U.S. and Soviet naval forces. A table comparing U.S. and Soviet cruiser forces showed six U.S. ships vs. 19 Soviet ships, despite the existence of 21 U.S. "frigates" equal or superior in size to the Soviet "cruisers". This led to the perception of a non-existent "cruiser gap".
Closing the gap
To close this "gap," the U.S. frigate (DL/DLG) classification was eliminated on 30 June 1975. All the gun frigates (DL) had already been stricken or converted to DDGs. Most of the DLGs became cruisers (CG), but the smaller Farraguts became destroyers (DDG). All of the nuclear-powered DLGNs, existing or in construction, were redesignated as CGNs. The change from DLG to CG redefined "cruiser" as smaller ships, more like large destroyers. Cruiser classifications were also simplified, with the guided missile light cruisers (CLG) simply becoming CGs. Gun cruisers retained the "CA" designation although the last remaining gun cruiser, Newport News, was decommissioned three days earlier on 27 June 1975.
The ocean escorts (DE/DEG) and patrol frigates (PF) became frigates (FF) or guided missile frigates (FFG).
These changes brought U.S. Navy classifications into line with foreign classifications, and eliminated the perceived "cruiser gap."
A final change came on 1 January 1980, when the guided missile destroyers (DDG) became guided missile cruisers (CG).
References
Sources
.
United States Navy in the 20th century
Ships of the United States Navy
1975 in the United States
Ship naming conventions
|
```yaml
# UTF-8
# YAML #
# name
name:
# inner
inner: [, , , , , ]
# outer
outer: [, , ]
# relations YAML list
# list[from, to, desc]
# desc
relations:
- [, , ]
- [, , ]
- [, , ]
- [, , ]
- [, , ]
- [, , ]
- [, , ]
- [, , ]
```
|
Nicolás Gabriel Albarracín Basil (born 11 June 1993) is an Uruguayan footballer who plays as a right winger for Montevideo Wanderers. He also holds an Italian passport.
Club career
Born in Montevideo, Albarracín graduated from Montevideo Wanderers F.C.'s youth setup. On 21 November 2010, he played his first match as a professional, coming on as a late substitute in a 1–2 home loss against local rivals Club Atlético River Plate for the Uruguayan Primera División championship.
In January 2013, he was sent on a one-year loan to Italian side Spezia Calcio. He could not play much due to a long injury he suffered and left the club after finishing his contract, staying some months without playing.
International career
Albarracín played various international friendly matches with the Uruguayan U20 team, but was finally desafected from the squad selected for the 2013 South American Youth Championship.
In 2015, he was named to participate in the Uruguay U22 squad for the 2015 Pan American Games.
Honours
Uruguay U-23
Pan American Games:
Champion : 2015
References
External links
1993 births
Living people
Footballers from Montevideo
Uruguayan people of Italian descent
Uruguayan men's footballers
Uruguayan expatriate men's footballers
Men's association football wingers
Uruguayan Primera División players
Bolivian Primera División players
Argentine Primera División players
Serie B players
Categoría Primera A players
Segunda División players
Liga MX players
Montevideo Wanderers F.C. players
Spezia Calcio players
Peñarol players
Deportivo Cali footballers
CD Lugo players
Atlante F.C. footballers
Querétaro F.C. footballers
Club Plaza Colonia de Deportes players
Club Atlético Patronato footballers
Pan American Games gold medalists for Uruguay
Footballers at the 2015 Pan American Games
Pan American Games medalists in football
Uruguayan expatriate sportspeople in Italy
Uruguayan expatriate sportspeople in Spain
Uruguayan expatriate sportspeople in Colombia
Uruguayan expatriate sportspeople in Mexico
Uruguayan expatriate sportspeople in Argentina
Uruguayan expatriate sportspeople in Bolivia
Expatriate men's footballers in Italy
Expatriate men's footballers in Spain
Expatriate men's footballers in Colombia
Expatriate men's footballers in Mexico
Expatriate men's footballers in Argentina
Expatriate men's footballers in Bolivia
Medalists at the 2015 Pan American Games
|
```java
/*
* or more contributor license agreements. See the NOTICE file
* distributed with this work for additional information
* regarding copyright ownership. The ASF licenses this file
*
* path_to_url
*
* Unless required by applicable law or agreed to in writing,
* "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
* specific language governing permissions and limitations
*/
package org.apache.weex.uitest.TC_AG;
import org.apache.weex.WXPageActivity;
import org.apache.weex.util.TestFlow;
import java.util.TreeMap;
import org.junit.Before;
import org.junit.Test;
public class AG_Border_Div_Border_Style extends TestFlow {
public AG_Border_Div_Border_Style() {
super(WXPageActivity.class);
}
@Before
public void setUp() throws InterruptedException {
super.setUp();
TreeMap testMap = new <String, Object> TreeMap();
testMap.put("testComponet", "AG_Border");
testMap.put("testChildCaseInit", "AG_Border_Div_Border_Style");
testMap.put("step1",new TreeMap(){
{
put("click", "solid");
put("screenshot", "AG_Border_Div_Border_Style_01_solid");
}
});
testMap.put("step2",new TreeMap(){
{
put("click", "dashed");
put("screenshot", "AG_Border_Div_Border_Style_02_dashed");
}
});
testMap.put("step3",new TreeMap(){
{
put("click", "dotted");
put("screenshot", "AG_Border_Div_Border_Style_03_dotted");
}
});
super.setTestMap(testMap);
}
@Test
public void doTest(){
super.testByTestMap();
}
}
```
|
```assembly
;
;
#include "ksarm64.h"
#include "arm64/arm64asmsymbolname.h"
AREA |.text|,ALIGN=5,CODE,READONLY
;
; void *memcpy(void *dst, const void *src, size_t length)
; void *memmove(void *dst, const void *src, size_t length)
; void *_memcpy_strict_align(void *dst, const void *src, size_t length)
;
; Copy a block of memory in a forward direction.
;
#if !defined(_BOOTCRT_)
LEAF_ENTRY A64NAME(memcpy), "", 5
ALTERNATE_ENTRY A64NAME(memmove)
sub x3, x0, x1 ; compute dest - source
cmp x3, x2 ; compare against size
blo __memcpy_reverse ; if overlap, we must do it in reverse
cbz x3, __memcpy_ret ; if dest==source, no work to do.
ALTERNATE_ENTRY A64NAME(_memcpy_strict_align)
ALTERNATE_ENTRY A64NAME(__memcpy_forward)
prfm pldl1strm, [x1] ; preload the first cache line
cmp x2, #8 ; less than 8 bytes?
mov x3, x0 ; use r3 as our destination
bhs __memcpy_forward_large_neon ; if not, just do the large copy case
tbz x2, #2, %F16 ; if not enough remaining, skip this load/store
ld4 {v0.b,v1.b,v2.b,v3.b}[0], [x1], #4 ; load 4 bytes
st4 {v0.b,v1.b,v2.b,v3.b}[0], [x3], #4 ; store 4 bytes
16
tbz x2, #1, %F17 ; if not enough remaining, skip this load/store
ld2 {v0.b,v1.b}[0], [x1], #2 ; load 2 bytes
st2 {v0.b,v1.b}[0], [x3], #2 ; store 2 bytes
17
tbz x2, #0, %F18 ; if not enough remaining, skip this load/store
ldrb w2, [x1] ; load 1 byte
strb w2, [x3] ; store 1 byte
18
__memcpy_ret
ret ; return
LEAF_END A64NAME(memcpy)
;
; __memcpy_forward_large_neon (internal calling convention)
;
; Copy large (>= 16 bytes) blocks of memory in a forward direction,
; using NEON registers.
;
LEAF_ENTRY __memcpy_forward_large_neon, "", 5
subs x2, x2, #32 ; pre-decrement to simplify the loop
blo %F13 ; skip over the loop if we don't have enough
subs x2, x2, #32 ; pre-decrement to simplify the loop
blo %F12 ; skip over the loop if we don't have enough
prfm pldl1strm, [x1, #64] ; prefetch the next cacheline
subs x2, x2, #64 ; pre-decrement to simplify the loop
blo %F11 ; skip over the loop if we don't have enough
tst x1, #15 ; x1 = (src mod 16)
bne %F9 ; no q-register if src not 16 byte aligned
tst x3, #15 ; x3 = (dst mod 16)
beq %F10 ; no q-register if dst not 16 byte aligned
9
ld1 {v0.16b,v1.16b,v2.16b,v3.16b}, [x1], #64; load 64 bytes
ld1 {v4.16b,v5.16b,v6.16b,v7.16b}, [x1], #64; load 64 bytes
prfm pldl1strm, [x1, #128] ; prefetch a cacheline one block ahead
prfm pldl1strm, [x1, #192] ; prefetch another cacheline ahead
st1 {v0.16b,v1.16b,v2.16b,v3.16b}, [x3], #64; store 64 bytes
st1 {v4.16b,v5.16b,v6.16b,v7.16b}, [x3], #64; store 64 bytes
subs x2, x2, #128 ; count the bytes for this block
bhs %B9 ; keep going until we're done
;; use tbz instead of incrementing counter
tbz x2, #6, %F12 ; if not enough remaining, skip this load/store
b %F11
10
ldp q0, q1, [x1]
ldp q2, q3, [x1, #32]
ldp q4, q5, [x1, #64]
ldp q6, q7, [x1, #96]
add x1, x1, #128
prfm pldl1strm, [x1, #128] ; prefetch a cacheline one block ahead
prfm pldl1strm, [x1, #192] ; prefetch another cacheline ahead
stp q0, q1, [x3]
stp q2, q3, [x3, #32]
stp q4, q5, [x3, #64]
stp q6, q7, [x3, #96]
add x3, x3, #128
subs x2, x2, #128 ; count the bytes for this block
bhs %B10 ; keep going until we're done
;; use tbz instead of incrementing counter
tbz x2, #6, %F12 ; if not enough remaining, skip this load/store
11
ld1 {v0.16b,v1.16b,v2.16b,v3.16b}, [x1], #64; load 64 bytes
st1 {v0.16b,v1.16b,v2.16b,v3.16b}, [x3], #64; store 64 bytes
12
tbz x2, #5, %F13 ; if not enough remaining, skip this load/store
ld1 {v0.16b,v1.16b}, [x1], #32 ; load 32 bytes
st1 {v0.16b,v1.16b}, [x3], #32 ; store 32 bytes
13
tbz x2, #4, %F14 ; if not enough remaining, skip this load/store
ld1 {v0.16b}, [x1], #16 ; load 16 bytes
st1 {v0.16b}, [x3], #16 ; store 16 bytes
14
tbz x2, #3, %F15 ; if not enough remaining, skip this load/store
ld1 {v0.8b}, [x1], #8 ; load 8 bytes
st1 {v0.8b}, [x3], #8 ; store 8 bytes
15
tbz x2, #2, %F16 ; if not enough remaining, skip this loop
ld4 {v0.b,v1.b,v2.b,v3.b}[0], [x1], #4 ; load 4 bytes
st4 {v0.b,v1.b,v2.b,v3.b}[0], [x3], #4 ; store 4 bytes
16
tbz x2, #1, %F17 ; if not enough remaining, skip this load/store
ld2 {v0.b,v1.b}[0], [x1], #2 ; load 2 bytes
st2 {v0.b,v1.b}[0], [x3], #2 ; store 2 bytes
17
tbz x2, #0, %F18 ; if not enough remaining, skip this load/store
ldrb w2, [x1] ; load 1 byte
strb w2, [x3] ; store 1 byte
18
ret
LEAF_END __memcpy_forward_large_neon
;
; void *memmove(void *dst, const void *src, size_t length)
;
; Copy a block of memory in a forward or reverse direction, ensuring that
; overlapping source/destination regions are copied correctly.
;
LEAF_ENTRY __memcpy_reverse, "", 5
add x1, x1, x2 ; advance source to end
prfum pldl1strm, [x1,#-1] ; preload the first cache line
cmp x2, #8 ; less than 8 bytes?
add x3, x0, x2 ; advance destination to end
bhs __memcpy_reverse_large_neon ; go to the small copy case directly
;; use tbz instead of decrementing counter
tbz x2, #2, %F16 ; if not enough remaining, skip this load/store
sub x1, x1, #4
sub x3, x3, #4
ld4 {v0.b,v1.b,v2.b,v3.b}[0], [x1] ; load 4 bytes
st4 {v0.b,v1.b,v2.b,v3.b}[0], [x3] ; store 4 bytes
16
tbz x2, #1, %F17 ; if not enough remaining, skip this load/store
sub x1, x1, #2
sub x3, x3, #2
ld2 {v0.b,v1.b}[0], [x1] ; load 2 bytes
st2 {v0.b,v1.b}[0], [x3] ; store 2 bytes
17
tbz x2, #0, %F18 ; if not enough remaining, skip this load/store
ldrb w2, [x1, #-1]! ; load 1 byte
strb w2, [x3, #-1]! ; store 1 byte
18
ret ; return
LEAF_END __memcpy_reverse
;
; __memcpy_reverse_large_neon (internal calling convention)
;
; Copy large (>= 16 bytes) block of memory in a reverse direction,
; using NEON registers.
;
LEAF_ENTRY __memcpy_reverse_large_neon, "", 5
subs x2, x2, #32 ; pre-decrement to simplify the loop
blo %F13 ; skip over the loop if we don't have enough
subs x2, x2, #32 ; pre-decrement to simplify the loop
blo %F12 ; skip over the loop if we don't have enough
prfum pldl1strm, [x1, #-65] ; prefetch the next cacheline backwards
subs x2, x2, #64 ; pre-decrement to simplify the loop
blo %F11 ; skip over the loop if we don't have enough
tst x1, #15 ; x1 = (src mod 16)
bne %F9 ; no q-register if src not 16 byte aligned
tst x3, #15 ; x3 = (dst mod 16)
beq %F10 ; no q-register if dst not 16 byte aligned
9
sub x1, x1, #64
ld1 {v0.16b,v1.16b,v2.16b,v3.16b}, [x1] ; load 64 bytes
sub x1, x1, #64
ld1 {v4.16b,v5.16b,v6.16b,v7.16b}, [x1] ; load 64 bytes
prfum pldl1strm, [x1, #-129] ; prefetch a cacheline one block backwards
prfum pldl1strm, [x1, #-193] ; prefetch another cacheline backwards
sub x3, x3, #64
st1 {v0.16b,v1.16b,v2.16b,v3.16b}, [x3] ; store 64 bytes
sub x3, x3, #64
st1 {v4.16b,v5.16b,v6.16b,v7.16b}, [x3] ; store 64 bytes
subs x2, x2, #128 ; count the bytes for this block
bhs %B9 ; keep going until we're done
b %F11
10
sub x1, x1, #128
ldp q6, q7, [x1, #96]
ldp q4, q5, [x1, #64]
sub x3, x3, #128
ldp q2, q3, [x1, #32]
ldp q0, q1, [x1]
prfum pldl1strm, [x1, #-129] ; prefetch a cacheline one block backwards
prfum pldl1strm, [x1, #-193] ; prefetch another cacheline backwards
stp q6, q7, [x3, #96]
stp q4, q5, [x3, #64]
stp q2, q3, [x3, #32]
stp q0, q1, [x3]
subs x2, x2, #128 ; count the bytes for this block
bhs %B10 ; keep going until we're done
11
tbz x2, #6, %F12 ; if not enough remaining, skip this load/store
sub x1, x1, #64
sub x3, x3, #64
ld1 {v0.16b,v1.16b,v2.16b,v3.16b}, [x1] ; load 64 bytes
st1 {v0.16b,v1.16b,v2.16b,v3.16b}, [x3] ; store 64 bytes
12
tbz x2, #5, %F13 ; if not enough remaining, skip this load/store
sub x1, x1, #32
sub x3, x3, #32
ld1 {v0.16b,v1.16b}, [x1] ; load 32 bytes
st1 {v0.16b,v1.16b}, [x3] ; store 32 bytes
13
tbz x2, #4, %F14 ; if not enough remaining, skip this load/store
sub x1, x1, #16
sub x3, x3, #16
ld1 {v0.16b}, [x1] ; load 16 bytes
st1 {v0.16b}, [x3] ; store 16 bytes
14
tbz x2, #3, %F15 ; if not enough remaining, skip this load/store
sub x1, x1, #8
sub x3, x3, #8
ld1 {v0.8b}, [x1] ; load 8 bytes
st1 {v0.8b}, [x3] ; store 8 bytes
15
tbz x2, #2, %F16 ; if not enough remaining, skip this load/store
sub x1, x1, #4
sub x3, x3, #4
ld4 {v0.b,v1.b,v2.b,v3.b}[0], [x1] ; load 4 bytes
st4 {v0.b,v1.b,v2.b,v3.b}[0], [x3] ; store 4 bytes
16
tbz x2, #1, %F17 ; if not enough remaining, skip this load/store
sub x1, x1, #2
sub x3, x3, #2
ld2 {v0.b,v1.b}[0], [x1] ; load 2 bytes
st2 {v0.b,v1.b}[0], [x3] ; store 2 bytes
17
tbz x2, #0, %F18 ; if not enough remaining, skip this load/store
ldrb w2, [x1, #-1]! ; load 1 byte
strb w2, [x3, #-1]! ; store 1 byte
18
ret
LEAF_END __memcpy_reverse_large_neon
#else /* defined(_BOOTCRT_) */
AREA |.text|,ALIGN=5,CODE,READONLY
;
; void *memcpy(void *dst, const void *src, size_t length)
; void *memmove(void *dst, const void *src, size_t length)
; void *_memcpy_strict_align(void *dst, const void *src, size_t length)
;
; Copy a block of memory in a forward direction, only performing naturally-aligned
; accesses.
;
NESTED_ENTRY memcpy, "", "", 5
ALTERNATE_ENTRY memmove
sub x3, x0, x1 ; compute dest - source
cmp x3, x2 ; compare against size
blo __memcpy_reverse ; if overlap, we must do it in reverse
ALTERNATE_ENTRY _memcpy_strict_align
ALTERNATE_ENTRY __memcpy_forward
;
; Verify alignment between source and destination
;
sub x4, x0, x1 ; get relative alignment of source and destination
neg x5, x0 ; neg -dest in x4
cbz x2, CopyExit ; exit if 0 count
and x4, x4, #7 ; relative alignment
and x5, x5, #7 ; determine how many bytes to align dest
subs x2, x2, x5 ; pre-decrement by the bytes needed to align
mov x3, x0 ; use x3 as dest
ble CantEvenAlign ; if that's too many, just use the final copy
; x4 is untrusted and feeds into an indir, but
; does not need a speculation block because
; it's already bounded 0-7
adr x6, Table ; point to lookup table
ldrb w7, [x6, x4] ; get offset to code
cbz x5, %F2 ; skip if no alignment needed
1
subs x5, x5, #1 ; count this byte
ldrb w8, [x1], #1 ; fetch byte
strb w8, [x3], #1 ; store it
bne %B1 ; loop until done
2
add x6, x6, x7, lsl #2 ; compute final destination
br x6 ; go there
Table dcb (CopyMisaligned_0 - Table) / 4
dcb (CopyMisaligned_1 - Table) / 4
dcb (CopyMisaligned_2 - Table) / 4
dcb (CopyMisaligned_3 - Table) / 4
dcb (CopyMisaligned_4 - Table) / 4
dcb (CopyMisaligned_5 - Table) / 4
dcb (CopyMisaligned_6 - Table) / 4
dcb (CopyMisaligned_7 - Table) / 4
CantEvenAlign
add x2, x2, x5 ; recover the original count
CopyFinalBytes
subs x2, x2, #1 ; count this byte
ldrb w8, [x1], #1 ; fetch byte
strb w8, [x3], #1 ; store it
bne CopyFinalBytes ; loop until done
CopyExit
ret
MACRO
COPY_MISALIGNED $Align
CopyMisaligned_$Align
subs x2, x2, #8+$Align ; at least 8 + $Align bytes remaining?
blt %F2 ; if so, skip the main loop
IF $Align==1
ldrb w8, [x1], #1 ; preload source
ENDIF
IF $Align==2
ldrh w8, [x1], #2 ; preload source
ENDIF
IF $Align==3
ldrb w8, [x1], #1 ; preload source
ldrh w9, [x1], #2 ; preload source
orr x8, x8, x9, lsl #8 ; combine
ENDIF
IF $Align==4
ldr w8, [x1], #4 ; preload source
ENDIF
IF $Align==5
ldrb w8, [x1], #1 ; preload source
ldr w9, [x1], #4 ; preload source
orr x8, x8, x9, lsl #8 ; combine
ENDIF
IF $Align==6
ldrh w8, [x1], #2 ; preload source
ldr w9, [x1], #4 ; preload source
orr x8, x8, x9, lsl #16 ; combine
ENDIF
IF $Align==7
ldrb w8, [x1], #1 ; preload source
ldrh w9, [x1], #2 ; preload source
ldr w10, [x1], #4 ; preload source
orr x8, x8, x9, lsl #8 ; combine
orr x8, x8, x10, lsl #24 ; combine
ENDIF
IF $Align!=0
sub x2, x2, #$Align ; count what we just loaded
ENDIF
1
subs x2, x2, #8 ; decrement count
ldr x9, [x1], #8 ; fetch dword
IF $Align==0
str x9, [x3], #8 ; store it
ELSE
orr x8, x8, x9, lsl #(8*$Align) ; copy low bits to upper bits of x8
str x8, [x3], #8 ; store it
lsr x8, x9, #(64 - 8*$Align) ; copy upper 8 bits to lower 8 of x8
ENDIF
bge %B1 ; stop if done
IF $Align==1
strb w8, [x3], #1 ; write to destination
ENDIF
IF $Align==2
strh w8, [x3], #2 ; write to destination
ENDIF
IF $Align==3
lsr x9, x8, #16 ; extract
strh w8, [x3], #2 ; write to destination
strb w9, [x3], #1 ; write to destination
ENDIF
IF $Align==4
str w8, [x3], #4 ; write to destination
ENDIF
IF $Align==5
lsr x9, x8, #32 ; extract
str w8, [x3], #4 ; write to destination
strb w9, [x3], #1 ; write to destination
ENDIF
IF $Align==6
lsr x9, x8, #32 ; extract
str w8, [x3], #4 ; write to destination
strh w9, [x3], #2 ; write to destination
ENDIF
IF $Align==7
lsr x9, x8, #32 ; extract
lsr x10, x8, #48 ; extract
str w8, [x3], #4 ; write to destination
strh w9, [x3], #2 ; write to destination
strb w10, [x3], #1 ; write to destination
ENDIF
2
adds x2, x2, #8+$Align ; recover the extra 5 we subtracted
beq CopyExit ; stop if that's everything
b CopyFinalBytes ; otherwise, copy remainder
MEND
COPY_MISALIGNED 0
COPY_MISALIGNED 1
COPY_MISALIGNED 2
COPY_MISALIGNED 3
COPY_MISALIGNED 4
COPY_MISALIGNED 5
COPY_MISALIGNED 6
COPY_MISALIGNED 7
LEAF_END
;
; void *memmove(void *dst, const void *src, size_t length)
;
; Copy a block of memory in a forward or reverse direction, ensuring that
; overlapping source/destination regions are copied correctly.
;
LEAF_ENTRY __memcpy_reverse, "", 5
;
; This is a limited-case scenario, just do the simplest thing
;
add x3, x0, x2 ; advance destination to end
add x1, x1, x2 ; advance source to end
cbz x2, %F2 ; skip if nothing to copy
1
subs x2, x2, #1 ; decrement count
ldrb w8, [x1, #-1]! ; load
strb w8, [x3, #-1]! ; store
bne %B1 ; loop until done
2
ret
LEAF_END
#endif /* defined(_BOOTCRT_) */
END
```
|
```javascript
import { PermissionStatus } from 'expo-modules-core';
import { RecordingOptionsPresets } from './RecordingConstants';
const nextId = (() => {
let id = 0;
return () => id++;
})();
async function getPermissionWithQueryAsync(name) {
if (!navigator || !navigator.permissions || !navigator.permissions.query)
return null;
try {
const { state } = await navigator.permissions.query({ name });
switch (state) {
case 'granted':
return PermissionStatus.GRANTED;
case 'denied':
return PermissionStatus.DENIED;
default:
return PermissionStatus.UNDETERMINED;
}
}
catch {
// Firefox - TypeError: 'microphone' (value of 'name' member of PermissionDescriptor) is not a valid value for enumeration PermissionName.
return PermissionStatus.UNDETERMINED;
}
}
function getUserMedia(constraints) {
if (navigator.mediaDevices && navigator.mediaDevices.getUserMedia) {
return navigator.mediaDevices.getUserMedia(constraints);
}
// Some browsers partially implement mediaDevices. We can't just assign an object
// with getUserMedia as it would overwrite existing properties.
// Here, we will just add the getUserMedia property if it's missing.
// First get ahold of the legacy getUserMedia, if present
const getUserMedia =
// TODO: this method is deprecated, migrate to path_to_url
navigator.getUserMedia ||
navigator.webkitGetUserMedia ||
navigator.mozGetUserMedia ||
function () {
const error = new Error('Permission unimplemented');
error.code = 0;
error.name = 'NotAllowedError';
throw error;
};
return new Promise((resolve, reject) => {
getUserMedia.call(navigator, constraints, resolve, reject);
});
}
function getStatusFromMedia(media, id) {
const isPlaying = !!(media.currentTime > 0 &&
!media.paused &&
!media.ended &&
media.readyState > 2);
const status = {
id,
isLoaded: true,
duration: media.duration * 1000,
currentTime: media.currentTime * 1000,
playbackState: '',
timeControlStatus: isPlaying ? 'playing' : 'paused',
reasonForWaitingToPlay: '',
playing: isPlaying,
isBuffering: false,
playbackRate: media.playbackRate,
shouldCorrectPitch: false,
mute: media.muted,
loop: media.loop,
};
return status;
}
export class AudioPlayerWeb extends globalThis.expo.SharedObject {
constructor(source, interval) {
super();
this._src = source;
this._interval = interval;
this._media = this._createMediaElement(source);
}
id = nextId();
_src = null;
_media;
_interval = 100;
_playing = false;
_paused = false;
_isLoaded = false;
isAudioSamplingSupported = false;
isBuffering = false;
shouldCorrectPitch = false;
get playing() {
return this._playing;
}
get muted() {
return this._media.muted;
}
set muted(value) {
this._media.muted = value;
}
get loop() {
return this._media.loop;
}
set loop(value) {
this._media.loop = value;
}
get duration() {
return this._media.duration * 1000;
}
get currentTime() {
return this._media.currentTime * 1000;
}
get paused() {
return this._media.paused;
}
get isLoaded() {
return this._isLoaded;
}
get playbackRate() {
return this._media.playbackRate;
}
set playbackRate(value) {
this._media.playbackRate = value;
}
get volume() {
return this._media.volume;
}
set volume(value) {
this._media.volume = value;
}
get currentStatus() {
return getStatusFromMedia(this._media, this.id);
}
play() {
this._media.play();
this._playing = true;
}
pause() {
this._media.pause();
this._playing = false;
}
async seekTo(seconds) {
this._media.currentTime = seconds / 1000;
}
setAudioSamplingEnabled(enabled) {
this.isAudioSamplingSupported = false;
}
setPlaybackRate(second, pitchCorrectionQuality) {
this._media.playbackRate = second;
this.shouldCorrectPitch = pitchCorrectionQuality === 'high';
this._media.preservesPitch = this.shouldCorrectPitch;
}
remove() {
this._media.pause();
this._media.removeAttribute('src');
this._media.load();
getStatusFromMedia(this._media, this.id);
}
_createMediaElement(source) {
const newSource = typeof source === 'string' ? source : source?.uri ?? '';
const media = new Audio(newSource);
media.ontimeupdate = () => {
this.emit('onPlaybackStatusUpdate', getStatusFromMedia(media, this.id));
};
media.onloadeddata = () => {
this._isLoaded = true;
this.emit('onPlaybackStatusUpdate', {
...getStatusFromMedia(media, this.id),
isLoaded: this._isLoaded,
});
};
return media;
}
}
export class AudioRecorderWeb extends globalThis.expo.SharedObject {
constructor(options) {
super();
this._options = options;
this.setup();
}
async setup() {
this._mediaRecorder = await this._createMediaRecorder(this._options);
}
id = nextId();
_options;
_mediaRecorder;
_mediaRecorderUptimeOfLastStartResume = 0;
_mediaRecorderDurationAlreadyRecorded = 0;
_mediaRecorderIsRecording = false;
currentTime = 0;
isRecording = false;
uri = null;
record() {
if (this._mediaRecorder === null) {
throw new Error('Cannot start an audio recording without initializing a MediaRecorder. Run prepareToRecordAsync() before attempting to start an audio recording.');
}
if (this._mediaRecorder?.state === 'paused') {
this._mediaRecorder.resume();
}
else {
this._mediaRecorder?.start();
}
}
getAvailableInputs() {
return [];
}
getCurrentInput() {
return {
type: 'Default',
name: 'Default',
uid: 'Default',
};
}
getStatus() {
return {
canRecord: this._mediaRecorder?.state === 'recording' || this._mediaRecorder?.state === 'inactive',
isRecording: this._mediaRecorder?.state === 'recording',
durationMillis: this._getAudioRecorderDurationMillis(),
mediaServicesDidReset: false,
url: this.uri,
};
}
pause() {
if (this._mediaRecorder === null) {
throw new Error('Cannot start an audio recording without initializing a MediaRecorder. Run prepareToRecordAsync() before attempting to start an audio recording.');
}
this._mediaRecorder?.pause();
}
recordForDuration(seconds) { }
setInput(input) { }
startRecordingAtTime(seconds) { }
async stop() {
if (this._mediaRecorder === null) {
throw new Error('Cannot start an audio recording without initializing a MediaRecorder. Run prepareToRecordAsync() before attempting to start an audio recording.');
}
const dataPromise = new Promise((resolve) => this._mediaRecorder?.addEventListener('dataavailable', (e) => resolve(e.data)));
this._mediaRecorder?.stop();
const data = await dataPromise;
const url = URL.createObjectURL(data);
this.uri = url;
this.emit('onRecordingStatusUpdate', {
id: this.id,
isFinished: true,
hasError: false,
error: null,
url,
});
}
async _createMediaRecorder(options) {
if (typeof navigator !== 'undefined' && !navigator.mediaDevices) {
throw new Error('No media devices available');
}
this._mediaRecorderUptimeOfLastStartResume = 0;
this._mediaRecorderDurationAlreadyRecorded = 0;
const stream = await getUserMedia({ audio: true });
const mediaRecorder = new window.MediaRecorder(stream, options?.web || RecordingOptionsPresets.HIGH_QUALITY.web);
mediaRecorder.addEventListener('pause', () => {
this._mediaRecorderDurationAlreadyRecorded = this._getAudioRecorderDurationMillis();
this._mediaRecorderIsRecording = false;
});
mediaRecorder.addEventListener('resume', () => {
this._mediaRecorderUptimeOfLastStartResume = Date.now();
this._mediaRecorderIsRecording = true;
});
mediaRecorder.addEventListener('start', () => {
this._mediaRecorderUptimeOfLastStartResume = Date.now();
this._mediaRecorderDurationAlreadyRecorded = 0;
this._mediaRecorderIsRecording = true;
});
mediaRecorder?.addEventListener('stop', () => {
this._mediaRecorderDurationAlreadyRecorded = this._getAudioRecorderDurationMillis();
this._mediaRecorderIsRecording = false;
// Clears recording icon in Chrome tab
stream.getTracks().forEach((track) => track.stop());
});
return mediaRecorder;
}
_getAudioRecorderDurationMillis() {
let duration = this._mediaRecorderDurationAlreadyRecorded;
if (this._mediaRecorderIsRecording && this._mediaRecorderUptimeOfLastStartResume > 0) {
duration += Date.now() - this._mediaRecorderUptimeOfLastStartResume;
}
return duration;
}
}
export async function setAudioModeAsync(mode) { }
export async function setIsAudioActiveAsync(active) { }
export async function getRecordingPermissionsAsync() {
const maybeStatus = await getPermissionWithQueryAsync('microphone');
switch (maybeStatus) {
case PermissionStatus.GRANTED:
return {
status: PermissionStatus.GRANTED,
expires: 'never',
canAskAgain: true,
granted: true,
};
case PermissionStatus.DENIED:
return {
status: PermissionStatus.DENIED,
expires: 'never',
canAskAgain: true,
granted: false,
};
default:
return await requestRecordingPermissionsAsync();
}
}
export async function requestRecordingPermissionsAsync() {
try {
const stream = await getUserMedia({ audio: true });
stream.getTracks().forEach((track) => track.stop());
return {
status: PermissionStatus.GRANTED,
expires: 'never',
canAskAgain: true,
granted: true,
};
}
catch {
return {
status: PermissionStatus.DENIED,
expires: 'never',
canAskAgain: true,
granted: false,
};
}
}
//# sourceMappingURL=AudioModule.web.js.map
```
|
Cantieri Riuniti dell'Adriatico ("United Shipbuilders of the Adriatic") was an Italian manufacturer in the sea and air industry which was active from 1930 to 1966. This shipyard is now owned by Fincantieri.
History
In 1930, Stabilimento Tecnico Triestino based at Trieste merged with another Italian company, the Cantiere Navale Triestino of Monfalcone, forming the Cantieri Riuniti dell'Adriatico (CRDA). The new company built a number of light and heavy cruisers for the Regia Marina (Royal Italian Navy) between the wars, as well as some 27 submarines. The ocean liner Conte di Savoia was also constructed in 1932.
During the World War II, CRDA Trieste built two battleships for the Regia Marina, Vittorio Veneto and Roma. CRDA survived the postwar shakeup in the shipbuilding industry and went on to build several more commercial liners in the 1950s and 1960s, as well as a few naval vessels. In 1984, CRDA was sold to the Fincantieri Group.
For the Olympic regattas of 1960 the firm produced 55 Finn sailboats for the single-handed event in the Gulf of Naples.
Ships built
The following table lists ships built at the former STT shipyards after the company's 1929 merger with Cantieri Navale Triestino to form CRDA.
Reference: Winklareth p. 292-293
See also
Cantiere Navale Triestino
Stabilimento Tecnico Triestino
References
Bibliography
1930 establishments in Italy
1966 disestablishments in Italy
Vehicle manufacturing companies established in 1930
Vehicle manufacturing companies disestablished in 1966
Shipbuilding companies of Italy
Italian brands
Fincantieri
|
```go
// +build linux
package devmapper
import (
"fmt"
"io/ioutil"
"os"
"path"
"strconv"
"github.com/sirupsen/logrus"
"github.com/containers/storage/drivers"
"github.com/containers/storage/pkg/devicemapper"
"github.com/containers/storage/pkg/idtools"
"github.com/containers/storage/pkg/locker"
"github.com/containers/storage/pkg/mount"
"github.com/containers/storage/pkg/system"
units "github.com/docker/go-units"
)
func init() {
graphdriver.Register("devicemapper", Init)
}
// Driver contains the device set mounted and the home directory
type Driver struct {
*DeviceSet
home string
uidMaps []idtools.IDMap
gidMaps []idtools.IDMap
ctr *graphdriver.RefCounter
locker *locker.Locker
}
// Init creates a driver with the given home and the set of options.
func Init(home string, options []string, uidMaps, gidMaps []idtools.IDMap) (graphdriver.Driver, error) {
deviceSet, err := NewDeviceSet(home, true, options, uidMaps, gidMaps)
if err != nil {
return nil, err
}
if err := mount.MakePrivate(home); err != nil {
return nil, err
}
d := &Driver{
DeviceSet: deviceSet,
home: home,
uidMaps: uidMaps,
gidMaps: gidMaps,
ctr: graphdriver.NewRefCounter(graphdriver.NewDefaultChecker()),
locker: locker.New(),
}
return graphdriver.NewNaiveDiffDriver(d, graphdriver.NewNaiveLayerIDMapUpdater(d)), nil
}
func (d *Driver) String() string {
return "devicemapper"
}
// Status returns the status about the driver in a printable format.
// Information returned contains Pool Name, Data File, Metadata file, disk usage by
// the data and metadata, etc.
func (d *Driver) Status() [][2]string {
s := d.DeviceSet.Status()
status := [][2]string{
{"Pool Name", s.PoolName},
{"Pool Blocksize", units.HumanSize(float64(s.SectorSize))},
{"Base Device Size", units.HumanSize(float64(s.BaseDeviceSize))},
{"Backing Filesystem", s.BaseDeviceFS},
{"Data file", s.DataFile},
{"Metadata file", s.MetadataFile},
{"Data Space Used", units.HumanSize(float64(s.Data.Used))},
{"Data Space Total", units.HumanSize(float64(s.Data.Total))},
{"Data Space Available", units.HumanSize(float64(s.Data.Available))},
{"Metadata Space Used", units.HumanSize(float64(s.Metadata.Used))},
{"Metadata Space Total", units.HumanSize(float64(s.Metadata.Total))},
{"Metadata Space Available", units.HumanSize(float64(s.Metadata.Available))},
{"Thin Pool Minimum Free Space", units.HumanSize(float64(s.MinFreeSpace))},
{"Udev Sync Supported", fmt.Sprintf("%v", s.UdevSyncSupported)},
{"Deferred Removal Enabled", fmt.Sprintf("%v", s.DeferredRemoveEnabled)},
{"Deferred Deletion Enabled", fmt.Sprintf("%v", s.DeferredDeleteEnabled)},
{"Deferred Deleted Device Count", fmt.Sprintf("%v", s.DeferredDeletedDeviceCount)},
}
if len(s.DataLoopback) > 0 {
status = append(status, [2]string{"Data loop file", s.DataLoopback})
}
if len(s.MetadataLoopback) > 0 {
status = append(status, [2]string{"Metadata loop file", s.MetadataLoopback})
}
if vStr, err := devicemapper.GetLibraryVersion(); err == nil {
status = append(status, [2]string{"Library Version", vStr})
}
return status
}
// Metadata returns a map of information about the device.
func (d *Driver) Metadata(id string) (map[string]string, error) {
m, err := d.DeviceSet.exportDeviceMetadata(id)
if err != nil {
return nil, err
}
metadata := make(map[string]string)
metadata["DeviceId"] = strconv.Itoa(m.deviceID)
metadata["DeviceSize"] = strconv.FormatUint(m.deviceSize, 10)
metadata["DeviceName"] = m.deviceName
return metadata, nil
}
// Cleanup unmounts a device.
func (d *Driver) Cleanup() error {
err := d.DeviceSet.Shutdown(d.home)
if err2 := mount.Unmount(d.home); err == nil {
err = err2
}
return err
}
// CreateReadWrite creates a layer that is writable for use as a container
// file system.
func (d *Driver) CreateReadWrite(id, parent string, opts *graphdriver.CreateOpts) error {
return d.Create(id, parent, opts)
}
// Create adds a device with a given id and the parent.
func (d *Driver) Create(id, parent string, opts *graphdriver.CreateOpts) error {
var storageOpt map[string]string
if opts != nil {
storageOpt = opts.StorageOpt
}
if err := d.DeviceSet.AddDevice(id, parent, storageOpt); err != nil {
return err
}
return nil
}
// Remove removes a device with a given id, unmounts the filesystem.
func (d *Driver) Remove(id string) error {
d.locker.Lock(id)
defer d.locker.Unlock(id)
if !d.DeviceSet.HasDevice(id) {
// Consider removing a non-existing device a no-op
// This is useful to be able to progress on container removal
// if the underlying device has gone away due to earlier errors
return nil
}
// This assumes the device has been properly Get/Put:ed and thus is unmounted
if err := d.DeviceSet.DeleteDevice(id, false); err != nil {
return fmt.Errorf("failed to remove device %s: %v", id, err)
}
return system.EnsureRemoveAll(path.Join(d.home, "mnt", id))
}
// Get mounts a device with given id into the root filesystem
func (d *Driver) Get(id, mountLabel string, uidMaps, gidMaps []idtools.IDMap) (string, error) {
d.locker.Lock(id)
defer d.locker.Unlock(id)
mp := path.Join(d.home, "mnt", id)
rootFs := path.Join(mp, "rootfs")
if count := d.ctr.Increment(mp); count > 1 {
return rootFs, nil
}
uid, gid, err := idtools.GetRootUIDGID(d.uidMaps, d.gidMaps)
if err != nil {
d.ctr.Decrement(mp)
return "", err
}
// Create the target directories if they don't exist
if err := idtools.MkdirAllAs(path.Join(d.home, "mnt"), 0755, uid, gid); err != nil && !os.IsExist(err) {
d.ctr.Decrement(mp)
return "", err
}
if err := idtools.MkdirAs(mp, 0755, uid, gid); err != nil && !os.IsExist(err) {
d.ctr.Decrement(mp)
return "", err
}
// Mount the device
if err := d.DeviceSet.MountDevice(id, mp, mountLabel); err != nil {
d.ctr.Decrement(mp)
return "", err
}
if err := idtools.MkdirAllAs(rootFs, 0755, uid, gid); err != nil && !os.IsExist(err) {
d.ctr.Decrement(mp)
d.DeviceSet.UnmountDevice(id, mp)
return "", err
}
idFile := path.Join(mp, "id")
if _, err := os.Stat(idFile); err != nil && os.IsNotExist(err) {
// Create an "id" file with the container/image id in it to help reconstruct this in case
// of later problems
if err := ioutil.WriteFile(idFile, []byte(id), 0600); err != nil {
d.ctr.Decrement(mp)
d.DeviceSet.UnmountDevice(id, mp)
return "", err
}
}
return rootFs, nil
}
// Put unmounts a device and removes it.
func (d *Driver) Put(id string) error {
d.locker.Lock(id)
defer d.locker.Unlock(id)
mp := path.Join(d.home, "mnt", id)
if count := d.ctr.Decrement(mp); count > 0 {
return nil
}
err := d.DeviceSet.UnmountDevice(id, mp)
if err != nil {
logrus.Errorf("devmapper: Error unmounting device %s: %s", id, err)
}
return err
}
// Exists checks to see if the device exists.
func (d *Driver) Exists(id string) bool {
return d.DeviceSet.HasDevice(id)
}
// AdditionalImageStores returns additional image stores supported by the driver
func (d *Driver) AdditionalImageStores() []string {
return nil
}
```
|
```objective-c
//
//
// path_to_url
//
// Unless required by applicable law or agreed to in writing, software
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
#pragma once
#include <exception>
#include <string>
namespace ray {
namespace internal {
class RayException : public std::exception {
public:
RayException(const std::string &msg) : msg_(msg){};
const char *what() const noexcept override { return msg_.c_str(); };
std::string msg_;
};
class RayActorException : public RayException {
public:
RayActorException(const std::string &msg) : RayException(msg){};
};
class RayTaskException : public RayException {
public:
RayTaskException(const std::string &msg) : RayException(msg){};
};
class RayWorkerException : public RayException {
public:
RayWorkerException(const std::string &msg) : RayException(msg){};
};
class UnreconstructableException : public RayException {
public:
UnreconstructableException(const std::string &msg) : RayException(msg){};
};
class RayFunctionNotFound : public RayException {
public:
RayFunctionNotFound(const std::string &msg) : RayException(msg){};
};
class RayRuntimeEnvException : public RayException {
public:
RayRuntimeEnvException(const std::string &msg) : RayException(msg){};
};
class RayTimeoutException : public RayException {
public:
RayTimeoutException(const std::string &msg) : RayException(msg){};
};
} // namespace internal
} // namespace ray
```
|
Li Xin (李信), courtesy name Youcheng (有成), was a Chinese military general of Qin during the Warring States era. Alongside Wang Jian, Wang Ben and other generals, Li Xin served under Qin Shi Huang (Ying Zheng) in his conquest of the six Warring States. He is also the great-great-grandfather of Li Guang, a Han dynasty general.
Early life
As a son of the governor of Nanjun Commandery, Li Yao, he served during Qin Shi Huang's reign, initially as a footsoldier, then rose through the ranks through sheer determination and his background.
Wang Jian ordered Li to capture Handan to finalize the fall of Zhao, which he did successfully.
Yan state
After the fall of Zhao in 228 BCE, Wang Jian's army stationed in Zhongshan started preparations for an offensive war against Yan. Ju Wu (鞠武), a Yan minister, proposed to Xi, King of Yan, to form alliances with the Dai, Qi, and Chu states, and make peace with the Xiongnu in the north, as a preemptive measure in preparation for the Qin invasion. However, Crown Prince Dan felt that the alliance strategy was unlikely to succeed, so he sent Jing Ke to assassinate Ying Zheng, the king of Qin. Jing Ke entered Qin disguised as an envoy, bringing with him a map of Dukang and the head of , a turncoat Qin general. The assassination attempt failed and Jing Ke was killed.
In 227 BCE, using the assassination attempt as casus belli, Ying Zheng ordered Wang Jian to lead an assault against Yan, with Meng Wu (蒙武) as Wang's deputy. The Qin defeated the Yan army as well as Yan's reinforcements from Dai in a battle on the eastern bank of the Yi River (易水), after which they captured the Yan capital, Ji (薊; present-day Beijing). Xi, King of Yan and his son, Crown Prince Dan, fled with their remaining forces to the Liaodong Peninsula. The Qin army pursued the retreating Yan to the Yan River (衍水; present-day Hun River, Liaoning), where they engaged with enemy forces and destroyed the bulk of Yan's army. Later, Xi ordered Crown Prince Dan's execution and sent his son's head to Qin as an "apology" for the assassination attempt. Qin accepted the offer and did not attack Yan for the next three years.
In 222 BCE, Wang Ben (王賁) & Li Xin led a Qin army to invade Liaodong, destroying Yan's remaining forces and ending the state of Yan. The former territories of Yan were partitioned and re-organized into the Qin dynasty's Yuyang (漁陽), Beiping (北平), Liaoxi (遼西) and Liaodong (遼東) commanderies.
Chu state
In 224 BCE, Qin began preparations for an invasion of Chu, one of its rivals among the six states. During a discussion between Ying Zheng and his subjects, the veteran general Wang Jian claimed that the invasion force needed to be at least 600,000 strong to succeed against Chu, but the younger general Li Xin believed that 200,000 men would be sufficient. Ying Zheng ordered Li Xin and the Qin army to attack Chu.
The Chu, led by Xiang Yan, took Li Xin's army by surprise with a 500,000 men army and completely annihilated Li's force in the unfamiliar territory of Huaiyang, modern-day northern Jiangsu and Anhui provinces. Xiang Yan achieved victory by luring the Qin army away by allowing them a few initial victories.
But then once again, Li Xin's army was ambushed by Lord Changping's army (Lord Changping was the former prime minister of the Qin state). Xiang Yan's army burnt two large Qin camps and killed seven commandants. This incident was considered the greatest setback out of all of Qin's campaigns.
Henceforth, Ying Zheng replaced Li and assigned Wang Jian the command of a 600,000-strong army in the following year as he had requested and ordered him to lead another attack on Chu. High in morale after their victory in the previous year, the Chu forces were content to sit back and defend against what they expected to be a siege of Chu. In response, Wang Jian decided to lull the Chu garrisons into a false sense of security by appearing to idle in his fortifications while secretly training his troops to fight in Chu territory. After a year, a great portion of the Chu garrisons decided to disband and demobilize due to an apparent lack of action from the Qin. Wang Jian invaded at this point, having prepared for war the entire time, and overran Huaiyang and the diminished Chu forces. Chu was swept away by the momentum of the swift assault and could only sustain local guerrilla-style resistance until it was fully conquered with the capture of Shouchun and the death of its last leader, who was either Lord Changping or Fuchu depending on different accounts, in 223 BCE. Conflicting narratives of the battle in the Records of the Grand Historian state that Xiang Yan was either killed in action or committed suicide. Thus the state of Chu was brought to an end. In 222 BCE, the Qin army advanced southward and annexed the Wuyue region (covering present-day Zhejiang and Jiangsu provinces).
Qi state
In 264 BCE, Tian Jian ascended the throne of Qi and was assisted by his mother, the queen dowager, in managing state affairs. Qin bribed Hou Sheng, the Qi chancellor, to dissuade King Jian from helping the other states while they were being attacked by Qin. By 221 BCE, Qi was the only state in China that had yet to be conquered by Qin. Qi hurriedly mobilized its armies to its western borders as a safeguard against a possible Qin invasion.
In the same year, Ying Zheng used Qi's rejection of a meeting with a Qin envoy as an excuse to attack Qi. Along with Wang Ben, Li Xin, and the Qin Army, avoided direct confrontation with enemy forces stationed on Qi's western borders and advanced into Qi's heartland via a southern detour from Yan. The Qin forces met with little resistance as they passed through Qi territory and eventually arrived at Linzi (north of present-day Zibo, Shandong), the capital of Qi. King Jian was caught by surprise and, after being persuaded by Hou Sheng, he surrendered to Qin without putting up a fight. The former territories of Qi were reorganized to form the Qin Empire's Qi and Langya commanderies.
Aftermath
Li Xin retired after Qin's unification, choosing to live in the area of modern Gansu. However, before doing so, he has bestowed the title of 'Marquis of Longxi' by Qin Shi Huang due to his military achievements during Qin's unification war.
In popular culture
Li Xin (Ri Shin) is the protagonist of anime/manga "Kingdom", one of the best-selling manga of all time. In Kingdom, he is depicted as a former slave who seeks to accomplish his dream of becoming the "Greatest General under the Heavens" during the Chinese Warring States Period.
Citations
Sources
3rd-century BC Chinese people
Qin dynasty generals
Qin Shi Huang
|
```xml
import { testHover } from '../../../hoverHelper';
import { position, sameLineRange } from '../../../util';
import { getDocUri } from '../../path';
describe('Should do hover', () => {
const docUri = getDocUri('hover/Basic.vue');
it('shows hover for <img> tag', async () => {
await testHover(docUri, position(4, 7), {
contents: ['An img element represents an image.'],
range: sameLineRange(4, 7, 10)
});
});
it('shows hover for this.msg', async () => {
await testHover(docUri, position(33, 23), {
contents: ['\n```ts\n(property) msg: string\n```\n'],
range: sameLineRange(33, 23, 26)
});
});
it('shows hover for `width` in <style>', async () => {
const hoverText = `
Specifies the width of the content area, padding area or border area \\(depending on 'box\\-sizing'\\) of certain boxes\\.
(Edge 12, Firefox 1, Safari 1, Chrome 1, IE 4, Opera 3)
Syntax: <viewport\\-length>\\{1,2\\}
[MDN Reference](path_to_url
`.trim();
await testHover(docUri, position(47, 3), {
contents: [hoverText],
range: sameLineRange(47, 2, 14)
});
});
});
```
|
```go
// cgo -godefs -- -Wall -Werror -static -I/tmp/include linux/types.go | go run mkpost.go
// Code generated by the command above; see README.md. DO NOT EDIT.
// +build mipsle,linux
package unix
const (
SizeofPtr = 0x4
SizeofLong = 0x4
)
type (
_C_long int32
)
type Timespec struct {
Sec int32
Nsec int32
}
type Timeval struct {
Sec int32
Usec int32
}
type Timex struct {
Modes uint32
Offset int32
Freq int32
Maxerror int32
Esterror int32
Status int32
Constant int32
Precision int32
Tolerance int32
Time Timeval
Tick int32
Ppsfreq int32
Jitter int32
Shift int32
Stabil int32
Jitcnt int32
Calcnt int32
Errcnt int32
Stbcnt int32
Tai int32
_ [44]byte
}
type Time_t int32
type Tms struct {
Utime int32
Stime int32
Cutime int32
Cstime int32
}
type Utimbuf struct {
Actime int32
Modtime int32
}
type Rusage struct {
Utime Timeval
Stime Timeval
Maxrss int32
Ixrss int32
Idrss int32
Isrss int32
Minflt int32
Majflt int32
Nswap int32
Inblock int32
Oublock int32
Msgsnd int32
Msgrcv int32
Nsignals int32
Nvcsw int32
Nivcsw int32
}
type Stat_t struct {
Dev uint32
Pad1 [3]int32
Ino uint64
Mode uint32
Nlink uint32
Uid uint32
Gid uint32
Rdev uint32
Pad2 [3]int32
Size int64
Atim Timespec
Mtim Timespec
Ctim Timespec
Blksize int32
Pad4 int32
Blocks int64
Pad5 [14]int32
}
type Dirent struct {
Ino uint64
Off int64
Reclen uint16
Type uint8
Name [256]int8
_ [5]byte
}
type Flock_t struct {
Type int16
Whence int16
_ [4]byte
Start int64
Len int64
Pid int32
_ [4]byte
}
const (
FADV_DONTNEED = 0x4
FADV_NOREUSE = 0x5
)
type RawSockaddr struct {
Family uint16
Data [14]int8
}
type RawSockaddrAny struct {
Addr RawSockaddr
Pad [96]int8
}
type Iovec struct {
Base *byte
Len uint32
}
type Msghdr struct {
Name *byte
Namelen uint32
Iov *Iovec
Iovlen uint32
Control *byte
Controllen uint32
Flags int32
}
type Cmsghdr struct {
Len uint32
Level int32
Type int32
}
const (
SizeofIovec = 0x8
SizeofMsghdr = 0x1c
SizeofCmsghdr = 0xc
)
const (
SizeofSockFprog = 0x8
)
type PtraceRegs struct {
Regs [32]uint64
Lo uint64
Hi uint64
Epc uint64
Badvaddr uint64
Status uint64
Cause uint64
}
type FdSet struct {
Bits [32]int32
}
type Sysinfo_t struct {
Uptime int32
Loads [3]uint32
Totalram uint32
Freeram uint32
Sharedram uint32
Bufferram uint32
Totalswap uint32
Freeswap uint32
Procs uint16
Pad uint16
Totalhigh uint32
Freehigh uint32
Unit uint32
_ [8]int8
}
type Ustat_t struct {
Tfree int32
Tinode uint32
Fname [6]int8
Fpack [6]int8
}
type EpollEvent struct {
Events uint32
PadFd int32
Fd int32
Pad int32
}
const (
POLLRDHUP = 0x2000
)
type Sigset_t struct {
Val [32]uint32
}
const _C__NSIG = 0x80
type Termios struct {
Iflag uint32
Oflag uint32
Cflag uint32
Lflag uint32
Line uint8
Cc [23]uint8
Ispeed uint32
Ospeed uint32
}
type Taskstats struct {
Version uint16
Ac_exitcode uint32
Ac_flag uint8
Ac_nice uint8
_ [4]byte
Cpu_count uint64
Cpu_delay_total uint64
Blkio_count uint64
Blkio_delay_total uint64
Swapin_count uint64
Swapin_delay_total uint64
Cpu_run_real_total uint64
Cpu_run_virtual_total uint64
Ac_comm [32]int8
Ac_sched uint8
Ac_pad [3]uint8
_ [4]byte
Ac_uid uint32
Ac_gid uint32
Ac_pid uint32
Ac_ppid uint32
Ac_btime uint32
_ [4]byte
Ac_etime uint64
Ac_utime uint64
Ac_stime uint64
Ac_minflt uint64
Ac_majflt uint64
Coremem uint64
Virtmem uint64
Hiwater_rss uint64
Hiwater_vm uint64
Read_char uint64
Write_char uint64
Read_syscalls uint64
Write_syscalls uint64
Read_bytes uint64
Write_bytes uint64
Cancelled_write_bytes uint64
Nvcsw uint64
Nivcsw uint64
Ac_utimescaled uint64
Ac_stimescaled uint64
Cpu_scaled_run_real_total uint64
Freepages_count uint64
Freepages_delay_total uint64
Thrashing_count uint64
Thrashing_delay_total uint64
Ac_btime64 uint64
}
type cpuMask uint32
const (
_NCPUBITS = 0x20
)
const (
CBitFieldMaskBit0 = 0x1
CBitFieldMaskBit1 = 0x2
CBitFieldMaskBit2 = 0x4
CBitFieldMaskBit3 = 0x8
CBitFieldMaskBit4 = 0x10
CBitFieldMaskBit5 = 0x20
CBitFieldMaskBit6 = 0x40
CBitFieldMaskBit7 = 0x80
CBitFieldMaskBit8 = 0x100
CBitFieldMaskBit9 = 0x200
CBitFieldMaskBit10 = 0x400
CBitFieldMaskBit11 = 0x800
CBitFieldMaskBit12 = 0x1000
CBitFieldMaskBit13 = 0x2000
CBitFieldMaskBit14 = 0x4000
CBitFieldMaskBit15 = 0x8000
CBitFieldMaskBit16 = 0x10000
CBitFieldMaskBit17 = 0x20000
CBitFieldMaskBit18 = 0x40000
CBitFieldMaskBit19 = 0x80000
CBitFieldMaskBit20 = 0x100000
CBitFieldMaskBit21 = 0x200000
CBitFieldMaskBit22 = 0x400000
CBitFieldMaskBit23 = 0x800000
CBitFieldMaskBit24 = 0x1000000
CBitFieldMaskBit25 = 0x2000000
CBitFieldMaskBit26 = 0x4000000
CBitFieldMaskBit27 = 0x8000000
CBitFieldMaskBit28 = 0x10000000
CBitFieldMaskBit29 = 0x20000000
CBitFieldMaskBit30 = 0x40000000
CBitFieldMaskBit31 = 0x80000000
CBitFieldMaskBit32 = 0x100000000
CBitFieldMaskBit33 = 0x200000000
CBitFieldMaskBit34 = 0x400000000
CBitFieldMaskBit35 = 0x800000000
CBitFieldMaskBit36 = 0x1000000000
CBitFieldMaskBit37 = 0x2000000000
CBitFieldMaskBit38 = 0x4000000000
CBitFieldMaskBit39 = 0x8000000000
CBitFieldMaskBit40 = 0x10000000000
CBitFieldMaskBit41 = 0x20000000000
CBitFieldMaskBit42 = 0x40000000000
CBitFieldMaskBit43 = 0x80000000000
CBitFieldMaskBit44 = 0x100000000000
CBitFieldMaskBit45 = 0x200000000000
CBitFieldMaskBit46 = 0x400000000000
CBitFieldMaskBit47 = 0x800000000000
CBitFieldMaskBit48 = 0x1000000000000
CBitFieldMaskBit49 = 0x2000000000000
CBitFieldMaskBit50 = 0x4000000000000
CBitFieldMaskBit51 = 0x8000000000000
CBitFieldMaskBit52 = 0x10000000000000
CBitFieldMaskBit53 = 0x20000000000000
CBitFieldMaskBit54 = 0x40000000000000
CBitFieldMaskBit55 = 0x80000000000000
CBitFieldMaskBit56 = 0x100000000000000
CBitFieldMaskBit57 = 0x200000000000000
CBitFieldMaskBit58 = 0x400000000000000
CBitFieldMaskBit59 = 0x800000000000000
CBitFieldMaskBit60 = 0x1000000000000000
CBitFieldMaskBit61 = 0x2000000000000000
CBitFieldMaskBit62 = 0x4000000000000000
CBitFieldMaskBit63 = 0x8000000000000000
)
type SockaddrStorage struct {
Family uint16
_ [122]int8
_ uint32
}
type HDGeometry struct {
Heads uint8
Sectors uint8
Cylinders uint16
Start uint32
}
type Statfs_t struct {
Type int32
Bsize int32
Frsize int32
_ [4]byte
Blocks uint64
Bfree uint64
Files uint64
Ffree uint64
Bavail uint64
Fsid Fsid
Namelen int32
Flags int32
Spare [5]int32
_ [4]byte
}
type TpacketHdr struct {
Status uint32
Len uint32
Snaplen uint32
Mac uint16
Net uint16
Sec uint32
Usec uint32
}
const (
SizeofTpacketHdr = 0x18
)
type RTCPLLInfo struct {
Ctrl int32
Value int32
Max int32
Min int32
Posmult int32
Negmult int32
Clock int32
}
type BlkpgPartition struct {
Start int64
Length int64
Pno int32
Devname [64]uint8
Volname [64]uint8
_ [4]byte
}
const (
BLKPG = 0x20001269
)
type XDPUmemReg struct {
Addr uint64
Len uint64
Size uint32
Headroom uint32
Flags uint32
_ [4]byte
}
type CryptoUserAlg struct {
Name [64]int8
Driver_name [64]int8
Module_name [64]int8
Type uint32
Mask uint32
Refcnt uint32
Flags uint32
}
type CryptoStatAEAD struct {
Type [64]int8
Encrypt_cnt uint64
Encrypt_tlen uint64
Decrypt_cnt uint64
Decrypt_tlen uint64
Err_cnt uint64
}
type CryptoStatAKCipher struct {
Type [64]int8
Encrypt_cnt uint64
Encrypt_tlen uint64
Decrypt_cnt uint64
Decrypt_tlen uint64
Verify_cnt uint64
Sign_cnt uint64
Err_cnt uint64
}
type CryptoStatCipher struct {
Type [64]int8
Encrypt_cnt uint64
Encrypt_tlen uint64
Decrypt_cnt uint64
Decrypt_tlen uint64
Err_cnt uint64
}
type CryptoStatCompress struct {
Type [64]int8
Compress_cnt uint64
Compress_tlen uint64
Decompress_cnt uint64
Decompress_tlen uint64
Err_cnt uint64
}
type CryptoStatHash struct {
Type [64]int8
Hash_cnt uint64
Hash_tlen uint64
Err_cnt uint64
}
type CryptoStatKPP struct {
Type [64]int8
Setsecret_cnt uint64
Generate_public_key_cnt uint64
Compute_shared_secret_cnt uint64
Err_cnt uint64
}
type CryptoStatRNG struct {
Type [64]int8
Generate_cnt uint64
Generate_tlen uint64
Seed_cnt uint64
Err_cnt uint64
}
type CryptoStatLarval struct {
Type [64]int8
}
type CryptoReportLarval struct {
Type [64]int8
}
type CryptoReportHash struct {
Type [64]int8
Blocksize uint32
Digestsize uint32
}
type CryptoReportCipher struct {
Type [64]int8
Blocksize uint32
Min_keysize uint32
Max_keysize uint32
}
type CryptoReportBlkCipher struct {
Type [64]int8
Geniv [64]int8
Blocksize uint32
Min_keysize uint32
Max_keysize uint32
Ivsize uint32
}
type CryptoReportAEAD struct {
Type [64]int8
Geniv [64]int8
Blocksize uint32
Maxauthsize uint32
Ivsize uint32
}
type CryptoReportComp struct {
Type [64]int8
}
type CryptoReportRNG struct {
Type [64]int8
Seedsize uint32
}
type CryptoReportAKCipher struct {
Type [64]int8
}
type CryptoReportKPP struct {
Type [64]int8
}
type CryptoReportAcomp struct {
Type [64]int8
}
type LoopInfo struct {
Number int32
Device uint32
Inode uint32
Rdevice uint32
Offset int32
Encrypt_type int32
Encrypt_key_size int32
Flags int32
Name [64]int8
Encrypt_key [32]uint8
Init [2]uint32
Reserved [4]int8
}
type TIPCSubscr struct {
Seq TIPCServiceRange
Timeout uint32
Filter uint32
Handle [8]int8
}
type TIPCSIOCLNReq struct {
Peer uint32
Id uint32
Linkname [68]int8
}
type TIPCSIOCNodeIDReq struct {
Peer uint32
Id [16]int8
}
```
|
```objective-c
#pragma once
#include "configkey.h"
#include <vespa/vespalib/util/time.h>
namespace config {
class ConfigSubscription;
struct SubscribeHandler
{
/**
* Subscribes to a spesific config given by a subscription.
* If the subscribe call is successful, the callback handler will be called
* with the new config.
*
* @param key the subscription key to subscribe to.
* @param timeout the timeout of the subscribe call.
* @return subscription object containing data relevant to client
*/
virtual std::shared_ptr<ConfigSubscription> subscribe(const ConfigKey & key, vespalib::duration timeout) = 0;
virtual ~SubscribeHandler() = default;
};
}
```
|
Malik or Malak is a gotra of Jats found in Pakistan and India.
The Malik Jats were originally called Ghatwal (or Gathwala); they proudly started calling themselves malik ("lord"). They were zamindars (landowners) during the Mughal era.
References
Jat clans of Haryana
|
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