text stringlengths 9 39.2M | dir stringlengths 25 226 | lang stringclasses 163
values | created_date timestamp[s] | updated_date timestamp[s] | repo_name stringclasses 751
values | repo_full_name stringclasses 752
values | star int64 1.01k 183k | len_tokens int64 1 18.5M |
|---|---|---|---|---|---|---|---|---|
```objective-c
/*
*
*/
#ifndef _MEC_PECI_H
#define _MEC_PECI_H
#include <stdint.h>
#include <stddef.h>
/* Write Data register */
#define MCHP_PECI_WR_DATA_REG_OFS 0u
#define MCHP_PECI_WR_DATA_MASK 0xffu
/* Read Data register */
#define MCHP_PECI_RD_DATA_REG_OFS 4u
#define MCHP_PECI_RD_DATA_MASK 0xffu
/* Contro... | /content/code_sandbox/soc/microchip/mec/common/reg/mec_peci.h | objective-c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 2,019 |
```objective-c
/*
*
*/
#ifndef _MEC_GPIO_H
#define _MEC_GPIO_H
#include <stdint.h>
#include <stddef.h>
#define MCHP_XEC_PINCTRL_REG_IDX(pin) ((pin >> 5) * 32 + (pin & 0x1f))
/** @brief All GPIO register as arrays of registers */
struct gpio_regs {
volatile uint32_t CTRL[174];
uint32_t RESERVED[18];
volatile ... | /content/code_sandbox/soc/microchip/mec/common/reg/mec_gpio.h | objective-c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 169 |
```objective-c
/*
*
*/
#ifndef _MEC_VCI_H
#define _MEC_VCI_H
#include <stdint.h>
#include <stddef.h>
/* VCI Config register */
#define MCHP_VCI_CFG_REG_OFS 0u
#define MCHP_VCI_CFG_REG_MASK 0x71f8fu
#define MCHP_VCI_CFG_IN_MASK 0x7fu
#define MCHP_VCI_CFG_IN0_HI 0x01u
#define MCHP_VCI_CFG_IN1_HI 0x02u
#define M... | /content/code_sandbox/soc/microchip/mec/common/reg/mec_vci.h | objective-c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 1,311 |
```objective-c
/*
*
*/
#ifndef _MEC_KSCAN_H
#define _MEC_KSCAN_H
#include <stdint.h>
#include <stddef.h>
/* KSO_SEL */
#define MCHP_KSCAN_KSO_SEL_REG_MASK 0xffu
#define MCHP_KSCAN_KSO_LINES_POS 0u
#define MCHP_KSCAN_KSO_LINES_MASK0 0x1fu
#define MCHP_KSCAN_KSO_LINES_MASK 0x1fu
#define MCHP_KSCAN_KSO_ALL_POS 5u
#d... | /content/code_sandbox/soc/microchip/mec/common/reg/mec_keyscan.h | objective-c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 371 |
```objective-c
/*
*
*/
#ifndef _MEC_TACH_H
#define _MEC_TACH_H
#include <stdint.h>
#include <stddef.h>
#define MCHP_TACH_INST_SPACING 0x10ul
#define MCHP_TACH_INST_SPACING_P2 4u
/* TACH Control register */
#define MCHP_TACH_CONTROL_REG_OFS 0U
#define MCHP_TACH_CONTROL_MASK 0xffffdd03U
/* Enable exceed high o... | /content/code_sandbox/soc/microchip/mec/common/reg/mec_tach.h | objective-c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 892 |
```objective-c
/*
*
*/
#ifndef _MEC_WDT_H
#define _MEC_WDT_H
#include <stdint.h>
#include <stddef.h>
/* Load register */
#define MCHP_WDT_LOAD_REG_OFS 0x00u
#define MCHP_WDT_LOAD_REG_MASK 0xffffu
/* Control register */
#define MCHP_WDT_CTRL_REG_OFS 0x04u
#define MCHP_WDT_CTRL_REG_MASK 0x021du
#define MCHP_WDT... | /content/code_sandbox/soc/microchip/mec/common/reg/mec_wdt.h | objective-c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 905 |
```objective-c
/*
*
*/
#ifndef _MEC_TIMERS_H
#define _MEC_TIMERS_H
#include <stdint.h>
#include <stddef.h>
/* Basic timers */
/* Offset between instances of the Basic Timer blocks */
#define MCHP_BTMR_INSTANCE_POS 5ul
#define MCHP_BTMR_INSTANCE_OFS 0x20u
/* Base frequency of all basic timers is AHB clock */
#d... | /content/code_sandbox/soc/microchip/mec/common/reg/mec_timers.h | objective-c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 3,180 |
```objective-c
/*
*
*/
#ifndef _MEC_PWM_H
#define _MEC_PWM_H
#include <stdint.h>
#include <stddef.h>
#define MCHP_PWM_INST_SPACING 0x10u
#define MCHP_PWM_INST_SPACING_P2 4u
/* PWM Count On register */
#define MCHP_PWM_COUNT_ON_REG_OFS 0u
#define MCHP_PWM_COUNT_ON_MASK 0xffffu
/* PWM Count Off register */
#defi... | /content/code_sandbox/soc/microchip/mec/common/reg/mec_pwm.h | objective-c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 599 |
```objective-c
/*
*
*/
#ifndef _MEC_TFDP_H
#define _MEC_TFDP_H
#include <stdint.h>
#include <stddef.h>
#define MCHP_TFDP_CTRL_REG_MASK 0x7fu
#define MCHP_TFDP_CTRL_EN_POS 0u
#define MCHP_TFDP_CTRL_EDGE_SEL_POS 1u
#define MCHP_TFDP_CTRL_DIV_SEL_POS 2u
#define MCHP_TFDP_CTRL_IP_DLY_POS 4u
#define MCHP_TFDP_CTRL_E... | /content/code_sandbox/soc/microchip/mec/common/reg/mec_tfdp.h | objective-c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 451 |
```objective-c
/*
*
*/
#ifndef _MEC_UART_H
#define _MEC_UART_H
#include <stdint.h>
#include <stddef.h>
#define MCHP_UART_RX_FIFO_MAX_LEN 16u
#define MCHP_UART_TX_FIFO_MAX_LEN 16u
#define MCHP_UART_BAUD_RATE_MIN 50u
#define MCHP_UART_BAUD_RATE_MAX 1500000u
#define MCHP_UART_SPACING 0x400u
/*
* LCR DLAB=0
* ... | /content/code_sandbox/soc/microchip/mec/common/reg/mec_uart.h | objective-c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 2,190 |
```objective-c
/*
*
*/
#ifndef _MEC_ACPI_EC_H
#define _MEC_ACPI_EC_H
#include <stdint.h>
#include <stddef.h>
#define MCHP_ACPI_EC_SPACING 0x0400u
#define MCHP_ACPI_EC_SPACING_PWROF2 10
/* EC_STS and OS_CMD_STS(read) bit definitions */
#define MCHP_ACPI_EC_STS_OBF_POS 0
#define MCHP_ACPI_EC_STS_OBF BIT(MCHP_ACPI... | /content/code_sandbox/soc/microchip/mec/common/reg/mec_acpi_ec.h | objective-c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 1,610 |
```objective-c
/*
*
*/
#ifndef _MEC_KBC_H
#define _MEC_KBC_H
#include <stdint.h>
#include <stddef.h>
/* ---- EM8042 Keyboard Controller (KBC) ---- */
/* EC_KBC_STS and KBC_STS_RD bit definitions */
#define MCHP_KBC_STS_OBF_POS 0u
#define MCHP_KBC_STS_OBF BIT(MCHP_KBC_STS_OBF_POS)
#define MCHP_KBC_STS_IBF_POS 1u
#... | /content/code_sandbox/soc/microchip/mec/common/reg/mec_kbc.h | objective-c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 1,301 |
```unknown
# Microchip MEC174x MCU core series
config SOC_SERIES_MEC174X
bool
select SOC_FAMILY_MICROCHIP_MEC
help
Enable support for Microchip MEC Cortex-M4F MCU series
config SOC_SERIES
default "mec174x" if SOC_SERIES_MEC174X
config SOC_MEC1743_QLJ
bool
select SOC_SERIES_MEC174X
config SOC_MEC1743_QSZ
... | /content/code_sandbox/soc/microchip/mec/mec174x/Kconfig.soc | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 153 |
```unknown
# Microchip MEC174x MCU series configuration options
if SOC_SERIES_MEC174X
config NUM_IRQS
# must be >= the highest interrupt number used
# - include the UART interrupts
# All NVIC external sources.
default 194
rsource "Kconfig.defconfig.mec174*"
config CORTEX_M_SYSTICK
depends on !RTOS_TIMER
endi... | /content/code_sandbox/soc/microchip/mec/mec174x/Kconfig.defconfig.series | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 95 |
```unknown
# Microchip MEC1743QLJ MCU using MEC5 HAL
# Q = 480KB total SRAM
# LJ = 176 pin package
if SOC_MEC1743_QLJ
config GPIO
default y
config PINCTRL
default y
endif # SOC_MEC1743_QLJ
``` | /content/code_sandbox/soc/microchip/mec/mec174x/Kconfig.defconfig.mec1743qlj | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 70 |
```c
/*
*
*/
#include <zephyr/device.h>
#include <zephyr/init.h>
#include <zephyr/kernel.h>
#include <soc.h>
#include <soc_cmn_init.h>
static int soc_init(void)
{
mec5_soc_common_init();
return 0;
}
/* Enabling HW debug and initializing the MEC interrupt aggregator should be done
* before driver are loaded to n... | /content/code_sandbox/soc/microchip/mec/mec174x/soc.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 131 |
```unknown
# Microchip MEC1743QSZ MCU using MEC5 HAL
# Q = 480KB total SRAM
# SZ = 144 pin package
if SOC_MEC1743_QSZ
config GPIO
default y
config PINCTRL
default y
endif # SOC_MEC1743_QSZ
``` | /content/code_sandbox/soc/microchip/mec/mec174x/Kconfig.defconfig.mec1743qsz | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 68 |
```objective-c
/*
*
*/
#ifndef __MEC5_SOC_H
#define __MEC5_SOC_H
#define SYSCLK_DEFAULT_IOSC_HZ MHZ(96)
#ifndef _ASMLANGUAGE
#include "device_mec5.h"
/* common SoC API */
#include "soc_dt.h"
#include "soc_espi_channels.h"
#include "soc_gpio.h"
#include "soc_pcr.h"
#include "soc_pins.h"
#endif
#endif
``` | /content/code_sandbox/soc/microchip/mec/mec174x/soc.h | objective-c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 90 |
```unknown
# Microchip MEC174X MCU core series
config SOC_SERIES_MEC174X
select ARM
select CPU_CORTEX_M4
select CPU_CORTEX_M_HAS_DWT
select CPU_HAS_FPU
select CPU_HAS_ARM_MPU
select HAS_SWO
select HAS_MEC5_HAL
select HAS_PM
if SOC_SERIES_MEC174X
config RTOS_TIMER
bool "MEC174x RTOS Timer(32KHz) as kernel t... | /content/code_sandbox/soc/microchip/mec/mec174x/Kconfig | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 111 |
```unknown
# Microchip MECH172x MCU core series
config SOC_SERIES_MECH172X
bool
select SOC_FAMILY_MICROCHIP_MEC
help
Enable support for Microchip MEC Cortex-M4F MCU series
config SOC_SERIES
default "mech172x" if SOC_SERIES_MECH172X
config SOC_MECH1723_NLJ
bool
select SOC_SERIES_MECH172X
config SOC_MECH172... | /content/code_sandbox/soc/microchip/mec/mech172x/Kconfig.soc | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 152 |
```unknown
# Microchip MECH172x MCU series configuration options
if SOC_SERIES_MECH172X
config NUM_IRQS
# must be >= the highest interrupt number used
# - include the UART interrupts
# All NVIC external sources.
default 181
rsource "Kconfig.defconfig.mech172*"
config CORTEX_M_SYSTICK
depends on !RTOS_TIMER
e... | /content/code_sandbox/soc/microchip/mec/mech172x/Kconfig.defconfig.series | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 95 |
```unknown
# Microchip MECH1723N-SZ MCU using MEC5 HAL
# N = 416KB total SRAM
# SZ = 144 pin package
if SOC_MECH1723_NSZ
config GPIO
default y
config PINCTRL
default y
endif # SOC_MECH1723_NSZ
``` | /content/code_sandbox/soc/microchip/mec/mech172x/Kconfig.defconfig.mech1723nsz | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 69 |
```c
/*
*
*/
#include <zephyr/device.h>
#include <zephyr/init.h>
#include <zephyr/kernel.h>
#include <soc.h>
#include <soc_cmn_init.h>
static int soc_init(void)
{
mec5_soc_common_init();
return 0;
}
/* Enabling HW debug and initializing the MEC interrupt aggregator should be done
* before driver are loaded to n... | /content/code_sandbox/soc/microchip/mec/mech172x/soc.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 131 |
```objective-c
/*
*
*/
#ifndef __MEC5_SOC_H
#define __MEC5_SOC_H
#define SYSCLK_DEFAULT_IOSC_HZ MHZ(96)
#ifndef _ASMLANGUAGE
#include "device_mec5.h"
/* common SoC API */
#include "soc_dt.h"
#include "soc_espi_channels.h"
#include "soc_gpio.h"
#include "soc_pcr.h"
#include "soc_pins.h"
#endif
#endif
``` | /content/code_sandbox/soc/microchip/mec/mech172x/soc.h | objective-c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 90 |
```unknown
# Microchip MECH172X MCU core series using MEC5 HAL and DTSI
config SOC_SERIES_MECH172X
select ARM
select CPU_CORTEX_M4
select CPU_CORTEX_M_HAS_DWT
select CPU_HAS_FPU
select CPU_HAS_ARM_MPU
select HAS_SWO
select HAS_MEC5_HAL
select HAS_PM
if SOC_SERIES_MECH172X
config RTOS_TIMER
bool "MECH172x R... | /content/code_sandbox/soc/microchip/mec/mech172x/Kconfig | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 120 |
```unknown
# Microchip MECH1723N-LJ MCU using MEC5 HAL
# N = 416KB total SRAM
# LJ = 176 pin package
if SOC_MECH1723_NLJ
config GPIO
default y
config PINCTRL
default y
endif # SOC_MECH1723_NLJ
``` | /content/code_sandbox/soc/microchip/mec/mech172x/Kconfig.defconfig.mech1723nlj | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 71 |
```unknown
# Microchip MEC1501 MCU core series
config SOC_SERIES_MEC15XX
bool
select SOC_FAMILY_MICROCHIP_MEC
help
Enable support for Microchip MEC Cortex-M4 MCU series
config SOC_SERIES
default "mec15xx" if SOC_SERIES_MEC15XX
config SOC_MEC1501_HSZ
bool
select SOC_SERIES_MEC15XX
config SOC
default "mec1... | /content/code_sandbox/soc/microchip/mec/mec15xx/Kconfig.soc | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 110 |
```unknown
# Microchip MEC1501HSZ MCU
if SOC_MEC1501_HSZ
config GPIO
default y
config ESPI_XEC
default y
depends on ESPI
config PS2_XEC
default y
depends on PS2
endif # SOC_MEC1501_HSZ
``` | /content/code_sandbox/soc/microchip/mec/mec15xx/Kconfig.defconfig.mec1501hsz | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 67 |
```unknown
# Microchip MEC MCU series configuration options
if SOC_SERIES_MEC15XX
config NUM_IRQS
# must be >= the highest interrupt number used
# - include the UART interrupts
# All NVIC external sources.
default 174
rsource "Kconfig.defconfig.mec1501*"
if RTOS_TIMER
config SOC_HAS_TIMING_FUNCTIONS
default ... | /content/code_sandbox/soc/microchip/mec/mec15xx/Kconfig.defconfig.series | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 131 |
```python
#!/usr/bin/env python3
import sys
import argparse
import hashlib
verbose_mode = False
# Header parameters
HDR_SIZE = 0x140
HDR_VER_MEC172X = 0x03
HDR_VER_MEC152X = 0x02
HDR_SPI_CLK_12MHZ = 0x3
HDR_SPI_CLK_16MHZ = 0x2
HDR_SPI_CLK_24MHZ = 0x1
HDR_SPI_CLK_48MHZ = 0
HDR_SPI_DRV_STR_1X = 0
HDR_SPI_DRV_STR_2X =... | /content/code_sandbox/soc/microchip/mec/common/spigen/mec_spi_gen.py | python | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 4,942 |
```c
/*
*
*/
#include <zephyr/kernel.h>
#include <zephyr/sys/sys_io.h>
#include <zephyr/sys/__assert.h>
#include <zephyr/pm/pm.h>
#include <soc.h>
/*
* CPU will spin up to DEEP_SLEEP_WAIT_SPIN_CLK_REQ times
* waiting for PCR CLK_REQ bits to clear except for the
* CPU bit itself. This is not necessary as the slee... | /content/code_sandbox/soc/microchip/mec/mec15xx/device_power.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 1,586 |
```objective-c
/*
*
*/
/**
* @file Header containing definitions for MCHP eSPI SAF
*/
#ifndef _SOC_ESPI_SAF_H_
#define _SOC_ESPI_SAF_H_
#include <stdint.h>
#include <zephyr/sys/util.h>
#include <soc.h>
#define MCHP_SAF_MAX_FLASH_DEVICES 2U
/*
* SAF hardware state machine timings
* poll timeout is in 32KHz cl... | /content/code_sandbox/soc/microchip/mec/mec15xx/soc_espi_saf_v1.h | objective-c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 4,989 |
```objective-c
/*
*
*/
#ifndef __DEVICE_POWER_H
#define __DEVICE_POWER_H
#ifndef _ASMLANGUAGE
void soc_lite_sleep_enable(void);
void soc_deep_sleep_enable(void);
void soc_deep_sleep_disable(void);
void soc_deep_sleep_periph_save(void);
void soc_deep_sleep_periph_restore(void);
void soc_deep_sleep_wait_clk_idle(vo... | /content/code_sandbox/soc/microchip/mec/mec15xx/device_power.h | objective-c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 94 |
```c
/*
*
*/
#include <zephyr/device.h>
#include <zephyr/init.h>
#include <soc.h>
#include <zephyr/drivers/pinctrl.h>
#include <zephyr/kernel.h>
#include <zephyr/arch/cpu.h>
#include <cmsis_core.h>
/*
* Initialize MEC1501 EC Interrupt Aggregator (ECIA) and external NVIC
* inputs.
*/
static int soc_ecia_init(void... | /content/code_sandbox/soc/microchip/mec/mec15xx/soc.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 731 |
```objective-c
/*
*
*/
#ifndef __MEC_SOC_H
#define __MEC_SOC_H
#define SYSCLK_DEFAULT_IOSC_HZ MHZ(48)
#ifndef _ASMLANGUAGE
#include "MEC1501hsz.h"
#include "regaccess.h"
/* common SoC API */
#include "../common/soc_dt.h"
#include "../common/soc_gpio.h"
#include "../common/soc_pcr.h"
#include "../common/soc_pins.... | /content/code_sandbox/soc/microchip/mec/mec15xx/soc.h | objective-c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 132 |
```c
/*
*
*/
#include <zephyr/arch/arm/arch.h>
#include <zephyr/kernel.h>
#include <zephyr/sys_clock.h>
#include <zephyr/timing/timing.h>
#include <soc.h>
void soc_timing_init(void)
{
/* Setup counter */
B32TMR1_REGS->CTRL = MCHP_BTMR_CTRL_ENABLE |
MCHP_BTMR_CTRL_AUTO_RESTART |
MCHP_BTMR_CTRL_COUN... | /content/code_sandbox/soc/microchip/mec/mec15xx/timing.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 396 |
```unknown
# Microchip MEC1501 MCU core series
config SOC_SERIES_MEC15XX
select ARM
select CPU_CORTEX_M4
select CPU_CORTEX_M_HAS_DWT
select CPU_HAS_ARM_MPU
select HAS_PM
config SOC_MEC1501_HSZ
select HAS_MEC_HAL
if SOC_SERIES_MEC15XX
config RTOS_TIMER
bool "MEC1501 RTOS timer"
config SOC_MEC1501_PROC_CLK_D... | /content/code_sandbox/soc/microchip/mec/mec15xx/Kconfig | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 734 |
```unknown
# Microchip MEC172x MCU core series
config SOC_SERIES_MEC172X
bool
select SOC_FAMILY_MICROCHIP_MEC
help
Enable support for Microchip MEC Cortex-M4F MCU series
config SOC_SERIES
default "mec172x" if SOC_SERIES_MEC172X
config SOC_MEC172X_NSZ
bool
select SOC_SERIES_MEC172X
config SOC_MEC172X_NLJ
... | /content/code_sandbox/soc/microchip/mec/mec172x/Kconfig.soc | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 151 |
```c
/*
*
*/
#include <zephyr/kernel.h>
#include <zephyr/sys/sys_io.h>
#include <zephyr/sys/__assert.h>
#include <zephyr/sys/barrier.h>
#include <zephyr/pm/pm.h>
#include <soc.h>
#include "device_power.h"
/*
* Deep Sleep
* Pros:
* Lower power dissipation, 48MHz PLL is off
* Cons:
* Longer wake latency. CPU sta... | /content/code_sandbox/soc/microchip/mec/mec15xx/power.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 932 |
```unknown
# Microchip MEC MCU series configuration options
if SOC_SERIES_MEC172X
config NUM_IRQS
# must be >= the highest interrupt number used
# - include the UART interrupts
# All NVIC external sources.
default 181
rsource "Kconfig.defconfig.mec172x*"
if RTOS_TIMER
config SOC_HAS_TIMING_FUNCTIONS
default ... | /content/code_sandbox/soc/microchip/mec/mec172x/Kconfig.defconfig.series | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 146 |
```unknown
# Microchip MEC172XNLJ MCU
if SOC_MEC172X_NLJ
config GPIO
default y
config ESPI_XEC_V2
default y
depends on ESPI
config EEPROM_XEC
default y
depends on EEPROM
endif # SOC_MEC172X_NLJ
``` | /content/code_sandbox/soc/microchip/mec/mec172x/Kconfig.defconfig.mec172xnlj | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 69 |
```objective-c
/*
*
*/
#ifndef __SOC_POWER_DEBUG_H__
#define __SOC_POWER_DEBUG_H__
/* #define SOC_SLEEP_STATE_GPIO_MARKER_DEBUG */
#ifdef SOC_SLEEP_STATE_GPIO_MARKER_DEBUG
/* Select a gpio not used. LED4 on EVB. High = ON */
#define DP_GPIO_ID MCHP_GPIO_0241_ID
/* output drive high */
#define PM_DP_ENTER_GPIO_V... | /content/code_sandbox/soc/microchip/mec/mec172x/soc_power_debug.h | objective-c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 221 |
```c
/*
*
*/
#include <zephyr/kernel.h>
#include <zephyr/sys/sys_io.h>
#include <zephyr/sys/__assert.h>
#include <zephyr/pm/pm.h>
#include <soc.h>
#include "device_power.h"
#define ADC_0_XEC_REG_BASE \
((struct adc_regs *)(DT_REG_ADDR(DT_NODELABEL(adc0))))
#define ECIA_XEC_REG_BASE \
((struct ecia_named... | /content/code_sandbox/soc/microchip/mec/mec172x/device_power.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 3,181 |
```c
/*
*
*/
#include <zephyr/sys/__assert.h>
#include <zephyr/device.h>
#include <zephyr/init.h>
#include <soc.h>
#include <zephyr/kernel.h>
#include <zephyr/arch/cpu.h>
#include <cmsis_core.h>
/* Enable SWD and ETM debug interface and pins.
* NOTE: ETM TRACE pins exposed on MEC172x EVB J30 12,14,16,18,20.
*/
st... | /content/code_sandbox/soc/microchip/mec/mec172x/soc.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 396 |
```objective-c
/*
*
*/
/**
* @file Header containing definitions for MCHP eSPI SAF
*/
#ifndef _SOC_ESPI_SAF_H_
#define _SOC_ESPI_SAF_H_
#include <stdint.h>
#include <zephyr/sys/util.h>
#define MCHP_SAF_MAX_FLASH_DEVICES 2U
/*
* SAF hardware state machine timings
* poll timeout is in 32KHz clock periods
* p... | /content/code_sandbox/soc/microchip/mec/mec172x/soc_espi_saf_v2.h | objective-c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 6,813 |
```objective-c
/*
*
*/
#ifndef __DEVICE_POWER_H
#define __DEVICE_POWER_H
#ifndef _ASMLANGUAGE
#define DEBUG_SLEEP
#define DEBUG_DEEP_SLEEP_CLK_REQ
/*
* Disable UART deep sleep save/restore. If a UART TX FIFO has data on deep
* sleep entry it will de-assert its CLK_REQ once TX FIFO empties. If the
* UART has T... | /content/code_sandbox/soc/microchip/mec/mec172x/device_power.h | objective-c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 574 |
```c
/*
*
*/
#include <zephyr/arch/arm/arch.h>
#include <zephyr/kernel.h>
#include <zephyr/sys_clock.h>
#include <zephyr/timing/timing.h>
#include <soc.h>
/*
* This code is conditionally built please refer to the SoC cmake file and
* is not built normally. If this is not built then timer5 is available
* for othe... | /content/code_sandbox/soc/microchip/mec/mec172x/timing.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 441 |
```unknown
# Microchip MEC172X MCU core series
config SOC_SERIES_MEC172X
select ARM
select CPU_CORTEX_M4
select CPU_CORTEX_M_HAS_DWT
select CPU_HAS_FPU
select CPU_HAS_ARM_MPU
select HAS_SWO
select HAS_PM
if SOC_SERIES_MEC172X
config RTOS_TIMER
bool "MEC172x RTOS Timer(32KHz) as kernel timer"
choice
prompt... | /content/code_sandbox/soc/microchip/mec/mec172x/Kconfig | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 548 |
```unknown
# Microchip MEC172XNSZ MCU
if SOC_MEC172X_NSZ
config GPIO
default y
endif # SOC_MEC172X_NSZ
``` | /content/code_sandbox/soc/microchip/mec/mec172x/Kconfig.defconfig.mec172xnsz | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 37 |
```c
/*
*
*/
#include <zephyr/kernel.h>
#include <zephyr/sys/sys_io.h>
#include <zephyr/sys/__assert.h>
#include <zephyr/pm/pm.h>
#include <soc.h>
#include <zephyr/arch/cpu.h>
#include <cmsis_core.h>
#include "device_power.h"
#include "soc_power_debug.h"
#define HTMR_0_XEC_REG_BASE \
((struct htmr_regs *)(DT... | /content/code_sandbox/soc/microchip/mec/mec172x/power.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 1,377 |
```objective-c
/*
*
*/
#ifndef __MEC_SOC_H
#define __MEC_SOC_H
#ifndef _ASMLANGUAGE
/*
* MEC172x includes the ARM single precision FPU and the ARM MPU with
* eight regions. Zephyr has an in-tree CMSIS header located in the arch
* include hierarchy that includes the correct ARM CMSIS core_xxx header
* from hal_... | /content/code_sandbox/soc/microchip/mec/mec172x/soc.h | objective-c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 4,335 |
```objective-c
/*
*
*/
#ifndef _MEC172X_ECIA_H
#define _MEC172X_ECIA_H
#include <stdint.h>
#include <stddef.h>
#include <zephyr/devicetree.h>
#define ECIA_BASE_ADDR DT_REG_ADDR(DT_NODELABEL(ecia))
#define MCHP_FIRST_GIRQ_NOS 8u
#define MCHP_LAST_GIRQ_NOS 26u
/*
* GIRQ22 is not connected to the NVIC. GIRQ22 ... | /content/code_sandbox/soc/microchip/mec/mec172x/reg/mec172x_ecia.h | objective-c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 17,227 |
```objective-c
/*
*
*/
#ifndef _MEC172X_ESPI_IO_H
#define _MEC172X_ESPI_IO_H
#include <stdint.h>
#include <stddef.h>
/* Offsets from base for various register groups */
#define MCHP_ESPI_IO_PC_OFS 0x0100u
#define MCHP_ESPI_IO_HOST_BAR_OFS 0x0120u
#define MCHP_ESPI_IO_LTR_OFS 0x0220u
#define MCHP_ESPI_IO_OOB_OFS ... | /content/code_sandbox/soc/microchip/mec/mec172x/reg/mec172x_espi_iom.h | objective-c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 14,275 |
```objective-c
/*
*
*/
#ifndef _MEC172X_EMI_H
#define _MEC172X_EMI_H
#include <stdint.h>
#include <stddef.h>
/** @brief Embedded Memory Interface (EMI) Registers */
struct emi_regs {
volatile uint8_t RT_HOST_TO_EC;
volatile uint8_t RT_EC_TO_HOST;
volatile uint8_t EC_ADDR_LSB;
volatile uint8_t EC_ADDR_MSB;
vol... | /content/code_sandbox/soc/microchip/mec/mec172x/reg/mec172x_emi.h | objective-c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 468 |
```objective-c
/*
*
*/
#ifndef _MEC172X_GPIO_H
#define _MEC172X_GPIO_H
#include <stdint.h>
#include <stddef.h>
#if defined(CONFIG_SOC_MEC172X_NSZ)
#include "gpio_pkg_sz.h"
#elif defined(CONFIG_SOC_MEC172X_NLJ)
#include "gpio_pkg_lj.h"
#endif
#define NUM_MCHP_GPIO_PORTS 6u
#define MAX_NUM_MCHP_GPIO (NUM_MCHP_GPIO_... | /content/code_sandbox/soc/microchip/mec/mec172x/reg/mec172x_gpio.h | objective-c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 2,333 |
```objective-c
/*
*
*/
#ifndef _MEC172X_ESPI_VW_H
#define _MEC172X_ESPI_VW_H
#include <stdint.h>
#include <stddef.h>
/* Master to Slave VW register: 96-bit (3 32 bit registers) */
/* 32-bit word 0 (bits[31:0]) */
#define ESPI_M2SW0_OFS 0u
#define ESPI_M2SW0_IDX_POS 0
#define ESPI_M2SW0_IDX_MASK 0xffu
#define E... | /content/code_sandbox/soc/microchip/mec/mec172x/reg/mec172x_espi_vw.h | objective-c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 4,002 |
```objective-c
/*
*
*/
#ifndef _MEC172X_ESPI_SAF_H_
#define _MEC172X_ESPI_SAF_H_
#include <stdint.h>
#include <stddef.h>
#define MCHP_ESPI_SAF_BASE_ADDR 0x40008000u
#define MCHP_ESPI_SAF_COMM_BASE_ADDR 0x40071000u
/* SAF hardware supports up to 2 external SPI flash devices */
#define MCHP_ESPI_SAF_CS_MAX 2
/* ... | /content/code_sandbox/soc/microchip/mec/mec172x/reg/mec172x_espi_saf.h | objective-c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 9,445 |
```objective-c
/*
*
*/
#ifndef _MEC_QSPI_H_
#define _MEC_QSPI_H_
#include <stdint.h>
#include <stddef.h>
#define QMPSPI_HW_VER 4u
#define MCHP_QMSPI_BASE_ADDR 0x40070000u
#define MCHP_QMSPI_MAX_DESCR 16u
#define MCHP_QMSPI_INPUT_CLOCK_FREQ_HZ 96000000u
#define MCHP_QMSPI_MAX_FREQ_KHZ \
((MCHP_QMSPI_INPUT_CLOC... | /content/code_sandbox/soc/microchip/mec/mec172x/reg/mec172x_qspi.h | objective-c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 7,057 |
```objective-c
/*
*
*/
#ifndef _MEC172X_GPIO_SZ_H
#define _MEC172X_GPIO_SZ_H
#include <stdint.h>
#include <stddef.h>
/* MEC172XH-B0-SZ (144-pin) */
#define MCHP_GPIO_PORT_A_BITMAP 0x7FFFFF9Du /* GPIO_0000 - 0036 GIRQ11 */
#define MCHP_GPIO_PORT_B_BITMAP 0x7FFFFFFDu /* GPIO_0040 - 0076 GIRQ10 */
#define MCHP_GPIO... | /content/code_sandbox/soc/microchip/mec/mec172x/reg/gpio_pkg_sz.h | objective-c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 238 |
```objective-c
/*
*
*/
#ifndef _MEC172X_VBAT_H
#define _MEC172X_VBAT_H
#include <stdint.h>
#include <stddef.h>
/* VBAT Registers Registers */
#define MCHP_VBAT_MEMORY_SIZE 128u
/* Offset 0x00 Power-Fail and Reset Status */
#define MCHP_VBATR_PFRS_OFS 0u
#define MCHP_VBATR_PFRS_MASK 0x7cu
#define MCHP_VBATR_PFR... | /content/code_sandbox/soc/microchip/mec/mec172x/reg/mec172x_vbat.h | objective-c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 1,259 |
```objective-c
/*
*
*/
#include <stdint.h>
#include <stddef.h>
#ifndef _MEC172X_ECS_H
#define _MEC172X_ECS_H
/* AHB Error Address, write any value to clear */
#define MCHP_ECS_AHB_ERR_ADDR_OFS 0x04u
/* AHB Error Control */
#define MCHP_ECS_AHB_ERR_CTRL_OFS 0x14u
#define MCHP_ECS_AHB_ERR_CTRL_DIS_POS 0
#define MCH... | /content/code_sandbox/soc/microchip/mec/mec172x/reg/mec172x_ecs.h | objective-c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 2,408 |
```objective-c
/*
*
*/
#ifndef _MEC172X_P80BD_H
#define _MEC172X_P80BD_H
#include <stdint.h>
#include <stddef.h>
#define MCHP_P80BD_0_BASE_ADDR 0x400f8000u
/* HDATA - Write-Only 32-bit */
#define MCHP_P80BD_HDATA_OFS 0x00u
#define MCHP_P80BD_HDATA_MASK GENMASK(31, 0)
/*
* EC-only Data/Attributes 16-bit
* b[... | /content/code_sandbox/soc/microchip/mec/mec172x/reg/mec172x_p80bd.h | objective-c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 1,217 |
```objective-c
/*
*
*/
#include <stdint.h>
#include <stddef.h>
#ifndef _MEC172X_PCR_H
#define _MEC172X_PCR_H
#define MCHP_PCR_SYS_SLP_CTRL_OFS 0x00u
#define MCHP_PCR_SYS_CLK_CTRL_OFS 0x04u
#define MCHP_PCR_SLOW_CLK_CTRL_OFS 0x08u
#define MCHP_PCR_OSC_ID_OFS 0x0cu
#define MCHP_PCR_PRS_OFS 0x10u
#define MCHP_PCR_P... | /content/code_sandbox/soc/microchip/mec/mec172x/reg/mec172x_pcr.h | objective-c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 4,517 |
```objective-c
/*
*
*/
#ifndef _MEC172X_GPIO_LJ_H
#define _MEC172X_GPIO_LJ_H
#define MCHP_GPIO_PORT_A_BITMAP 0x7FFFFFFFu /* GPIO_0000 - 0036 GIRQ11 */
#define MCHP_GPIO_PORT_B_BITMAP 0x7FFFFFFFu /* GPIO_0040 - 0076 GIRQ10 */
#define MCHP_GPIO_PORT_C_BITMAP 0x3FFFFFF7u /* GPIO_0100 - 0136 GIRQ09 */
#define MCHP_G... | /content/code_sandbox/soc/microchip/mec/mec172x/reg/gpio_pkg_lj.h | objective-c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 213 |
```objective-c
/*
*
*/
#ifndef MEC172X_DEFS_H
#define MEC172X_DEFS_H
#include <stddef.h>
#include <stdint.h>
#ifdef __cplusplus
extern "C" {
#endif
/*
* Delay register address. Write n to delay for n + 1 microseconds where
* 0 <= n <= 31.
* Implementation stalls the CPU fetching instructions including blocking... | /content/code_sandbox/soc/microchip/mec/mec172x/reg/mec172x_defs.h | objective-c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 781 |
```unknown
config SOC_FAMILY_MICROCHIP_MIV
bool
config SOC_FAMILY
default "microchip_miv" if SOC_FAMILY_MICROCHIP_MIV
rsource "*/Kconfig.soc"
``` | /content/code_sandbox/soc/microchip/miv/Kconfig.soc | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 42 |
```yaml
family:
- name: microchip_miv
series:
- name: miv
socs:
- name: miv
- name: polarfire
socs:
- name: polarfire
``` | /content/code_sandbox/soc/microchip/miv/soc.yml | yaml | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 50 |
```unknown
if SOC_FAMILY_MICROCHIP_MIV
rsource "*/Kconfig.defconfig"
endif # SOC_FAMILY_MICROCHIP_MIV
``` | /content/code_sandbox/soc/microchip/miv/Kconfig.defconfig | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 30 |
```unknown
if SOC_FAMILY_MICROCHIP_MIV
rsource "*/Kconfig"
endif # SOC_FAMILY_MICROCHIP_MIV
``` | /content/code_sandbox/soc/microchip/miv/Kconfig | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 28 |
```unknown
# RISCV64_MIV Microchip Polarfire SOC configuration options
config SOC_SERIES_POLARFIRE
bool
select SOC_FAMILY_MICROCHIP_MIV
help
Microchip RV64 implementation
config SOC_POLARFIRE
bool
select SOC_SERIES_POLARFIRE
help
Microchip MPFS system implementation
config SOC_SERIES
default "polarfire... | /content/code_sandbox/soc/microchip/miv/polarfire/Kconfig.soc | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 109 |
```unknown
if SOC_SERIES_POLARFIRE
# MPFS should be configured so that the mtimer clock is 1MHz independent of the CPU clock...
config SYS_CLOCK_HW_CYCLES_PER_SEC
default 1000000
config RISCV_SOC_INTERRUPT_INIT
default y
config RISCV_GP
default y
config 2ND_LVL_ISR_TBL_OFFSET
default 13
config 2ND_LVL_INTR_0... | /content/code_sandbox/soc/microchip/miv/polarfire/Kconfig.defconfig | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 128 |
```unknown
# RISCV64_MIV Microchip Polarfire SOC configuration options
config SOC_SERIES_POLARFIRE
select RISCV
select RISCV_PRIVILEGED
select RISCV_HAS_PLIC
config SOC_POLARFIRE
select ATOMIC_OPERATIONS_BUILTIN
select RISCV_GP
select USE_SWITCH_SUPPORTED
select USE_SWITCH
select CPU_HAS_FPU
select SCHED_IP... | /content/code_sandbox/soc/microchip/miv/polarfire/Kconfig | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 182 |
```objective-c
/*
*
*/
#ifndef _MEC172X_I2C_SMB_H
#define _MEC172X_I2C_SMB_H
#include <stdint.h>
#include <stddef.h>
/* Version 3.7 MCHP I2C/SMBus Controller specification */
#define MCHP_I2C_BAUD_CLK_HZ 16000000u
#define MCHP_I2C_SMB_INST_SPACING 0x400u
#define MCHP_I2C_SMB_INST_SPACING_P2 10u
#define MCHP_I2... | /content/code_sandbox/soc/microchip/mec/mec172x/reg/mec172x_i2c_smb.h | objective-c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 4,338 |
```unknown
# RISCV32_MIV configuration options
config SOC_SERIES_MIV
bool
select SOC_FAMILY_MICROCHIP_MIV
help
Microchip Mi-V implementation#
config SOC_MIV
bool
select SOC_SERIES_MIV
help
Microchip Mi-V system implementation
config SOC_SERIES
default "miv" if SOC_SERIES_MIV
config SOC
default "miv" ... | /content/code_sandbox/soc/microchip/miv/miv/Kconfig.soc | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 92 |
```unknown
if SOC_SERIES_MIV
config SYS_CLOCK_HW_CYCLES_PER_SEC
default 4000000
config RISCV_SOC_INTERRUPT_INIT
default y
config RISCV_GP
default y
config 2ND_LVL_ISR_TBL_OFFSET
default 12
config 2ND_LVL_INTR_00_OFFSET
default 11
config MAX_IRQ_PER_AGGREGATOR
default 30
config NUM_IRQS
default 42
endif ... | /content/code_sandbox/soc/microchip/miv/miv/Kconfig.defconfig | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 102 |
```unknown
# RISCV32_MIV configuration options
config SOC_SERIES_MIV
select RISCV
select RISCV_PRIVILEGED
select RISCV_HAS_PLIC
config SOC_MIV
select ATOMIC_OPERATIONS_BUILTIN
select INCLUDE_RESET_VECTOR
select RISCV_ISA_RV32I
select RISCV_ISA_EXT_M
select RISCV_ISA_EXT_A
select RISCV_ISA_EXT_ZICSR
select ... | /content/code_sandbox/soc/microchip/miv/miv/Kconfig | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 109 |
```restructuredtext
.. _built-in-snippets:
Built-in snippets
#################
.. toctree::
:maxdepth: 1
:glob:
**/*
``` | /content/code_sandbox/snippets/index.rst | restructuredtext | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 34 |
```unknown
/*
*
*/
/ {
chosen {
zephyr,console = &bt_nus_console_uart;
zephyr,shell-uart = &bt_nus_console_uart;
};
bt_nus_console_uart: bt_nus_console_uart {
compatible = "zephyr,nus-uart";
rx-fifo-size = <1024>;
tx-fifo-size = <1024>;
};
};
``` | /content/code_sandbox/snippets/nus-console/nus-console.overlay | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 90 |
```yaml
name: nus-console
append:
EXTRA_CONF_FILE: nus-console.conf
EXTRA_DTC_OVERLAY_FILE: nus-console.overlay
``` | /content/code_sandbox/snippets/nus-console/snippet.yml | yaml | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 32 |
```unknown
CONFIG_SERIAL=y
CONFIG_CONSOLE=y
CONFIG_UART_CONSOLE=y
CONFIG_BT=y
CONFIG_BT_PERIPHERAL=y
CONFIG_BT_ZEPHYR_NUS=y
CONFIG_UART_BT=y
CONFIG_BT_ZEPHYR_NUS_AUTO_START_BLUETOOTH=y
# Bluetooth optimizations to allow larger data packets.
CONFIG_BT_RX_STACK_SIZE=2048
CONFIG_BT_L2CAP_TX_MTU=512
CONFIG_BT_BUF_ACL_RX_... | /content/code_sandbox/snippets/nus-console/nus-console.conf | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 113 |
```unknown
CONFIG_XEN_DOM0=y
CONFIG_UART_INTERRUPT_DRIVEN=n
``` | /content/code_sandbox/snippets/xen_dom0/xen_dom0.conf | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 15 |
```restructuredtext
.. _snippet-nus-console:
NUS Console Snippet (nus-console)
########################################
.. code-block:: console
west build -S nus-console [...]
Overview
********
This snippet redirects serial console output to a UART over NUS (Bluetooth LE) instance.
The Bluetooth Serial device u... | /content/code_sandbox/snippets/nus-console/README.rst | restructuredtext | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 152 |
```unknown
/*
*
*/
/ {
interrupt-parent = <&gic>;
#address-cells = <2>;
#size-cells = <2>;
chosen {
zephyr,console = &xen_consoleio_hvc;
zephyr,shell-uart = &xen_consoleio_hvc;
};
psci {
method = "hvc";
};
xen_consoleio_hvc: hvc {
compatible = "xen,hvc-consoleio";
status = "okay";
};
};
``` | /content/code_sandbox/snippets/xen_dom0/xen_dom0.overlay | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 113 |
```yaml
name: xen_dom0
append:
EXTRA_DTC_OVERLAY_FILE: xen_dom0.overlay
EXTRA_CONF_FILE: xen_dom0.conf
boards:
qemu_cortex_a53/qemu_cortex_a53:
append:
EXTRA_DTC_OVERLAY_FILE: boards/qemu_cortex_a53.overlay
rcar_h3ulcb/r8a77951/a57:
append:
EXTRA_DTC_OVERLAY_FILE: boards/rcar_h3ulcb_r8a7795... | /content/code_sandbox/snippets/xen_dom0/snippet.yml | yaml | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 186 |
```unknown
/*
*
*/
/delete-node/ &ram;
/delete-node/ &scif2;
/ {
/*
* This node may differs on different setups, please check
* following line in Xen boot log to set it right:
* (XEN) Grant table range: 0x00000088080000-0x000000880c0000
*
* Xen passes actual values for setup in domain device tree, but Ze... | /content/code_sandbox/snippets/xen_dom0/boards/rcar_salvator_xs.overlay | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 365 |
```restructuredtext
.. _xen_dom0:
Xen Dom0: universal snippet for XEN control domain
##################################################
Overview
********
This snippet allows user to build Zephyr as a Xen initial domain (Dom0). The feature
is implemented as configuration snippet to allow support for any compatible pl... | /content/code_sandbox/snippets/xen_dom0/README.rst | restructuredtext | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 492 |
```unknown
/*
*
*/
/delete-node/ &ram;
/delete-node/ &scif2;
/ {
/*
* This node may differs on different setups, please check
* following line in Xen boot log to set it right:
* (XEN) Grant table range: 0x00000088080000-0x000000880c0000
*
* Xen passes actual values for setup in domain device tree, but Ze... | /content/code_sandbox/snippets/xen_dom0/boards/rcar_h3ulcb_r8a77951_a57.overlay | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 365 |
```unknown
/*
*
*/
/delete-node/ &ram;
/delete-node/ &hscif0;
/ {
/*
* This node may differs on different setups, please check
* following line in Xen boot log to set it right:
* (XEN) Grant table range: 0x00000078080000-0x000000780c0000
* Also, add extended region 1:
* (XEN) Extended region 1: 0x4000000... | /content/code_sandbox/snippets/xen_dom0/boards/rcar_spider_s4_r8a779f0_a55.overlay | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 422 |
```unknown
/*
*/
&cpuflpr_vpr {
status = "okay";
};
``` | /content/code_sandbox/snippets/nordic-flpr-xip/nordic-flpr-xip.overlay | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 16 |
```yaml
name: nordic-flpr-xip
append:
EXTRA_DTC_OVERLAY_FILE: nordic-flpr-xip.overlay
boards:
nrf54l15pdk/nrf54l15/cpuapp:
append:
EXTRA_DTC_OVERLAY_FILE: boards/nrf54l15pdk_nrf54l15_cpuapp.overlay
nrf54h20dk/nrf54h20/cpuapp:
append:
EXTRA_DTC_OVERLAY_FILE: boards/nrf54h20dk_nrf54h20_cpuapp.o... | /content/code_sandbox/snippets/nordic-flpr-xip/snippet.yml | yaml | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 116 |
```restructuredtext
.. _nordic-flpr-xip:
Nordic FLPR snippet with execution in place (nordic-flpr-xip)
#############################################################
Overview
********
This snippet allows users to build Zephyr with the capability to boot Nordic FLPR
(Fast Lightweight Peripheral Processor) from applica... | /content/code_sandbox/snippets/nordic-flpr-xip/README.rst | restructuredtext | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 107 |
```unknown
/*
*/
&cpuflpr_vpr {
execution-memory = <&cpuflpr_code_partition>;
/delete-property/ source-memory;
};
&uart120 {
status = "reserved";
interrupt-parent = <&cpuflpr_clic>;
};
``` | /content/code_sandbox/snippets/nordic-flpr-xip/boards/nrf54h20dk_nrf54h20_cpuapp.overlay | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 52 |
```unknown
/*
*/
/ {
soc {
reserved-memory {
#address-cells = <1>;
#size-cells = <1>;
cpuflpr_code_partition: image@165000 {
/* FLPR core code partition */
reg = <0x165000 DT_SIZE_K(96)>;
};
};
};
};
&uart30 {
status = "reserved";
};
&cpuflpr_vpr {
execution-memory = <&cpuflpr_code_parti... | /content/code_sandbox/snippets/nordic-flpr-xip/boards/nrf54l15pdk_nrf54l15_cpuapp.overlay | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 122 |
```unknown
/*
*/
&cpuppr_vpr {
status = "okay";
};
``` | /content/code_sandbox/snippets/nordic-ppr/nordic-ppr.overlay | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 16 |
```yaml
name: nordic-ppr
append:
EXTRA_DTC_OVERLAY_FILE: nordic-ppr.overlay
boards:
nrf54h20dk/nrf54h20/cpuapp:
append:
EXTRA_DTC_OVERLAY_FILE: boards/nrf54h20dk_nrf54h20_cpuapp.overlay
``` | /content/code_sandbox/snippets/nordic-ppr/snippet.yml | yaml | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 70 |
```unknown
/*
*
*/
/delete-node/ &sram0;
&uart0 {
/* Xen consoleio will be used */
status = "disabled";
};
/ {
/*
* This node may differs on different setups, please check
* following line in Xen boot log to set it right:
* (XEN) Grant table range: 0x00000040200000-0x00000040240000
*
* Xen passes actu... | /content/code_sandbox/snippets/xen_dom0/boards/qemu_cortex_a53.overlay | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 385 |
```unknown
/*
*/
&cpuppr_ram3x_region {
status = "okay";
};
&uart135 {
status = "reserved";
};
``` | /content/code_sandbox/snippets/nordic-ppr/boards/nrf54h20dk_nrf54h20_cpuapp.overlay | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 28 |
```yaml
name: nordic-flpr
append:
EXTRA_DTC_OVERLAY_FILE: nordic-flpr.overlay
boards:
nrf54l15pdk/nrf54l15/cpuapp:
append:
EXTRA_DTC_OVERLAY_FILE: boards/nrf54l15pdk_nrf54l15_cpuapp.overlay
nrf54h20dk/nrf54h20/cpuapp:
append:
EXTRA_DTC_OVERLAY_FILE: boards/nrf54h20dk_nrf54h20_cpuapp.overlay
... | /content/code_sandbox/snippets/nordic-flpr/snippet.yml | yaml | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 112 |
```restructuredtext
.. _nordic-flpr:
Nordic FLPR snippet with execution from SRAM (nordic-flpr)
##########################################################
Overview
********
This snippet allows users to build Zephyr with the capability to boot Nordic FLPR
(Fast Lightweight Peripheral Processor) from application core.... | /content/code_sandbox/snippets/nordic-flpr/README.rst | restructuredtext | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 104 |
```unknown
/*
*/
&cpuflpr_vpr {
status = "okay";
};
``` | /content/code_sandbox/snippets/nordic-flpr/nordic-flpr.overlay | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 16 |
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