text stringlengths 9 39.2M | dir stringlengths 25 226 | lang stringclasses 163
values | created_date timestamp[s] | updated_date timestamp[s] | repo_name stringclasses 751
values | repo_full_name stringclasses 752
values | star int64 1.01k 183k | len_tokens int64 1 18.5M |
|---|---|---|---|---|---|---|---|---|
```unknown
/*
*
*/
/dts-v1/;
#include "nsim.dtsi"
#include "nsim-flat-mem.dtsi"
#include "nsim-uart-ns16550.dtsi"
/ {
model = "snps,nsim_hs";
compatible = "snps,nsim_hs";
cpus {
#address-cells = <1>;
#size-cells = <0>;
cpu@0 {
device_type = "cpu";
compatible = "snps,arcv3-hs";
reg = <0>;
};
... | /content/code_sandbox/boards/snps/nsim/arc_classic/nsim_nsim_hs5x.dts | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 127 |
```unknown
/*
*
*/
/dts-v1/;
#include "nsim.dtsi"
#include "nsim-ccm-mem.dtsi"
#include "nsim-uart-ns16550.dtsi"
/ {
model = "snps,nsim_hs";
compatible = "snps,nsim_hs";
cpus {
#address-cells = <1>;
#size-cells = <0>;
cpu@0 {
device_type = "cpu";
compatible = "snps,archs";
reg = <0>;
};
};
}... | /content/code_sandbox/boards/snps/nsim/arc_classic/nsim_nsim_hs_mpuv6.dts | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 125 |
```yaml
board:
name: nsim
vendor: snps
socs:
- name: nsim_em
- name: nsim_em7d_v22
- name: nsim_em11d
- name: nsim_hs
variants:
- name: sram
- name: smp
- name: flash_xip
- name: mpuv6
- name: hostlink
- name: nsim_hs5x
variants:
- name: smp
variants:
- name: ... | /content/code_sandbox/boards/snps/nsim/arc_classic/board.yml | yaml | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 190 |
```unknown
/*
*
*/
/dts-v1/;
#include "nsim.dtsi"
#include "nsim-flat-mem.dtsi"
#include "nsim-uart-ns16550.dtsi"
/ {
model = "snps,nsim_hs";
compatible = "snps,nsim_hs";
cpus {
#address-cells = <1>;
#size-cells = <0>;
cpu@0 {
device_type = "cpu";
compatible = "snps,archs";
reg = <0>;
};
};
... | /content/code_sandbox/boards/snps/nsim/arc_classic/nsim_nsim_hs6x.dts | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 123 |
```yaml
identifier: nsim/nsim_hs5x
name: HS5x nSIM simulator
type: sim
simulation: nsim
simulation_exec: nsimdrv
arch: arc
toolchain:
- zephyr
- arcmwdt
- cross-compile
testing:
ignore_tags:
- net
- bluetooth
vendor: snps
``` | /content/code_sandbox/boards/snps/nsim/arc_classic/nsim_nsim_hs5x.yaml | yaml | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 81 |
```unknown
CONFIG_ISA_ARCV3=y
CONFIG_SYS_CLOCK_TICKS_PER_SEC=100
CONFIG_BUILD_OUTPUT_BIN=n
CONFIG_ARCV2_INTERRUPT_UNIT=y
CONFIG_ARCV2_TIMER=y
CONFIG_CONSOLE=y
CONFIG_UART_CONSOLE=y
CONFIG_SERIAL=y
CONFIG_MP_MAX_NUM_CPUS=12
``` | /content/code_sandbox/boards/snps/nsim/arc_classic/nsim_nsim_hs5x_smp_12cores_defconfig | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 63 |
```unknown
/*
*/
#include "nsim.dtsi"
#include "nsim-uart-ns16550.dtsi"
/ {
ici: intercore-interrupt-unit {
compatible = "snps,archs-ici";
interrupts = <19 1>;
interrupt-parent = <&intc>;
};
};
``` | /content/code_sandbox/boards/snps/nsim/arc_classic/nsim-smp.dtsi | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 71 |
```unknown
/*
*
*/
/dts-v1/;
#include "nsim.dtsi"
#include "nsim-flat-mem.dtsi"
#include "nsim-uart-ns16550.dtsi"
/ {
model = "snps,nsim_hs";
compatible = "snps,nsim_hs";
cpus {
#address-cells = <1>;
#size-cells = <0>;
cpu@0 {
device_type = "cpu";
compatible = "snps,archs";
reg = <0>;
};
};
... | /content/code_sandbox/boards/snps/nsim/arc_classic/nsim_nsim_hs_sram.dts | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 123 |
```yaml
identifier: nsim/nsim_hs
name: HS nSIM simulator
type: sim
simulation: nsim
simulation_exec: nsimdrv
arch: arc
toolchain:
- zephyr
- cross-compile
- arcmwdt
testing:
ignore_tags:
- net
- bluetooth
vendor: snps
``` | /content/code_sandbox/boards/snps/nsim/arc_classic/nsim_nsim_hs.yaml | yaml | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 77 |
```unknown
CONFIG_ISA_ARCV3=y
CONFIG_SYS_CLOCK_TICKS_PER_SEC=100
CONFIG_BUILD_OUTPUT_BIN=n
CONFIG_ARCV2_INTERRUPT_UNIT=y
CONFIG_ARCV2_TIMER=y
CONFIG_CONSOLE=y
CONFIG_UART_CONSOLE=y
CONFIG_SERIAL=y
CONFIG_SMP=y
CONFIG_MP_MAX_NUM_CPUS=2
CONFIG_TICKET_SPINLOCKS=y
CONFIG_XIP=n
``` | /content/code_sandbox/boards/snps/nsim/arc_classic/nsim_nsim_hs6x_smp_defconfig | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 81 |
```unknown
/*
*/
#include "nsim_em.dtsi"
/ {
sectimer0: sectimer0 {
compatible = "snps,arc-timer";
interrupts = <20 1>;
interrupt-parent = <&intc>;
};
};
``` | /content/code_sandbox/boards/snps/nsim/arc_classic/nsim_em-sec.dtsi | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 58 |
```unknown
/*
*
*/
/dts-v1/;
#include "nsim-smp.dtsi"
#include "nsim-flat-mem.dtsi"
/ {
model = "snps,nsim_hs";
compatible = "snps,nsim_hs";
cpus {
#address-cells = <1>;
#size-cells = <0>;
cpu@0 {
device_type = "cpu";
compatible = "snps,arcv3-hs";
reg = <0>;
};
cpu@1 {
device_type = "cp... | /content/code_sandbox/boards/snps/nsim/arc_classic/nsim_nsim_hs6x_smp.dts | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 150 |
```unknown
# DesignWare ARC nSIM simulated platform configuration
config BOARD_NSIM
select HAS_COVERAGE_SUPPORT
``` | /content/code_sandbox/boards/snps/nsim/arc_classic/Kconfig | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 22 |
```unknown
/*
*
*/
/dts-v1/;
#include "nsim_em.dtsi"
/ {
model = "snps,nsim_em";
compatible = "snps,nsim_em";
};
&cpu0 {
clock-frequency = <5000000>;
};
``` | /content/code_sandbox/boards/snps/nsim/arc_classic/nsim_nsim_em7d_v22.dts | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 56 |
```unknown
# DesignWare ARC nSIM simulated platform configuration
config BOARD_NSIM
select SOC_NSIM_EM if BOARD_NSIM_NSIM_EM
select SOC_NSIM_EM7D_V22 if BOARD_NSIM_NSIM_EM7D_V22
select SOC_NSIM_EM11D if BOARD_NSIM_NSIM_EM11D
select SOC_NSIM_HS if BOARD_NSIM_NSIM_HS
select SOC_NSIM_HS if BOARD_NSIM_NSIM_HS_SRAM
... | /content/code_sandbox/boards/snps/nsim/arc_classic/Kconfig.nsim | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 386 |
```yaml
identifier: nsim/nsim_hs/flash_xip
name: HS nSIM simulator (FLASH XIP)
type: sim
simulation: nsim
simulation_exec: nsimdrv
arch: arc
toolchain:
- zephyr
- cross-compile
- arcmwdt
testing:
ignore_tags:
- net
- bluetooth
vendor: snps
``` | /content/code_sandbox/boards/snps/nsim/arc_classic/nsim_nsim_hs_flash_xip.yaml | yaml | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 85 |
```yaml
identifier: nsim/nsim_hs6x
name: HS6x nSIM simulator
type: sim
simulation: nsim
simulation_exec: nsimdrv
arch: arc
toolchain:
- arcmwdt
- cross-compile
- zephyr
testing:
ignore_tags:
- net
- bluetooth
vendor: snps
``` | /content/code_sandbox/boards/snps/nsim/arc_classic/nsim_nsim_hs6x.yaml | yaml | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 81 |
```unknown
CONFIG_SYS_CLOCK_TICKS_PER_SEC=100
CONFIG_BUILD_OUTPUT_BIN=n
CONFIG_ARCV2_INTERRUPT_UNIT=y
CONFIG_ARCV2_TIMER=y
CONFIG_CONSOLE=y
CONFIG_UART_CONSOLE=y
CONFIG_SERIAL=y
CONFIG_ARC_MPU_ENABLE=y
CONFIG_HARVARD=n
CONFIG_XIP=n
``` | /content/code_sandbox/boards/snps/nsim/arc_classic/nsim_nsim_hs_sram_defconfig | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 66 |
```unknown
/*
*
*/
/dts-v1/;
#include "nsim-smp.dtsi"
#include "nsim-flat-mem.dtsi"
/ {
model = "snps,nsim_hs";
compatible = "snps,nsim_hs";
cpus {
#address-cells = <1>;
#size-cells = <0>;
cpu@0 {
device_type = "cpu";
compatible = "snps,archs";
reg = <0>;
};
cpu@1 {
device_type = "cpu";... | /content/code_sandbox/boards/snps/nsim/arc_classic/nsim_nsim_hs_smp.dts | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 142 |
```unknown
/*
*
*/
/dts-v1/;
#include "nsim_em.dtsi"
/ {
model = "snps,nsim_em";
compatible = "snps,nsim_em";
};
&cpu0 {
clock-frequency = <5000000>;
};
``` | /content/code_sandbox/boards/snps/nsim/arc_classic/nsim_nsim_em.dts | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 56 |
```yaml
identifier: nsim/nsim_em11d
name: EM11D Nsim simulator
type: sim
simulation: nsim
simulation_exec: nsimdrv
arch: arc
toolchain:
- zephyr
- cross-compile
- arcmwdt
testing:
ignore_tags:
- net
- bluetooth
vendor: snps
``` | /content/code_sandbox/boards/snps/nsim/arc_classic/nsim_nsim_em11d.yaml | yaml | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 81 |
```unknown
/*
*
*/
/dts-v1/;
#include "nsim.dtsi"
#include "nsim-ccm-mem.dtsi"
#include "nsim-uart-hostlink.dtsi"
/ {
model = "snps,nsim_hs";
compatible = "snps,nsim_hs";
cpus {
#address-cells = <1>;
#size-cells = <0>;
cpu@0 {
device_type = "cpu";
compatible = "snps,archs";
reg = <0>;
};
};
... | /content/code_sandbox/boards/snps/nsim/arc_classic/nsim_nsim_hs_hostlink.dts | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 123 |
```unknown
/*
*
*/
/dts-v1/;
#include "nsim_em-sec.dtsi"
/ {
model = "snps,nsim_sem_mpu_stack_guard";
compatible = "snps,nsim_sem_mpu_stack_guard.dts";
};
``` | /content/code_sandbox/boards/snps/nsim/arc_classic/nsim_nsim_sem_mpu_stack_guard.dts | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 55 |
```unknown
CONFIG_ISA_ARCV3=y
CONFIG_SYS_CLOCK_TICKS_PER_SEC=100
CONFIG_BUILD_OUTPUT_BIN=n
CONFIG_ARCV2_INTERRUPT_UNIT=y
CONFIG_ARCV2_TIMER=y
CONFIG_CONSOLE=y
CONFIG_UART_CONSOLE=y
CONFIG_SERIAL=y
CONFIG_XIP=n
``` | /content/code_sandbox/boards/snps/nsim/arc_classic/nsim_nsim_hs6x_defconfig | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 59 |
```yaml
identifier: nsim/nsim_sem
name: SEM Nsim simulator
type: sim
arch: arc
simulation: nsim
simulation_exec: nsimdrv
toolchain:
- zephyr
- cross-compile
- arcmwdt
testing:
default: true
ignore_tags:
- net
- bluetooth
vendor: snps
``` | /content/code_sandbox/boards/snps/nsim/arc_classic/nsim_nsim_sem.yaml | yaml | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 82 |
```unknown
-arcv2hs
-core2
-arcnum=3
-rgf_num_banks=2
-rgf_banked_regs=32
-rgf_num_wr_ports=2
-Xatomic
-Xll64
-Xunaligned
-Xcode_density
-Xdiv_rem=radix4
-Xswap
-Xbitscan
-Xmpy_option=qmpyh
-Xshift_assist
-Xbarrel_shifter
-Xfpud_div
-Xfpu_mac
-Xtimer0
-Xtimer0_level=1
-Xtimer1
-Xtimer1_level=0
-X... | /content/code_sandbox/boards/snps/nsim/arc_classic/support/mdb_hs.args | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 355 |
```unknown
/*
*
*/
/dts-v1/;
#include "nsim-smp.dtsi"
#include "nsim-flat-mem.dtsi"
/ {
model = "snps,nsim_hs";
compatible = "snps,nsim_hs";
cpus {
#address-cells = <1>;
#size-cells = <0>;
cpu@0 {
device_type = "cpu";
compatible = "snps,arcv3-hs";
reg = <0>;
};
cpu@1 {
device_type = "cp... | /content/code_sandbox/boards/snps/nsim/arc_classic/nsim_nsim_hs5x_smp_12cores.dts | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 499 |
```xml
nsim_isa_family=av3hs
nsim_isa_core=0
arcver=0x60
nsim_isa_dual_issue_option=1
nsim_isa_uarch_rev_major=0
nsim_isa_uarch_rev_minor=0
nsim_isa_rgf_num_banks=1
nsim_isa_rgf_num_regs=32
nsim_isa_rgf_num_wr_ports=2
nsim_isa_big_endian=0
nsim_isa_lpc_size=0
nsim_isa_pc_size=32
nsim_isa_addr_size=32
nsim... | /content/code_sandbox/boards/snps/nsim/arc_classic/support/nsim_hs5x.props | xml | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 605 |
```xml
nsim_isa_family=av2hs
nsim_isa_core=2
arcver=0x52
nsim_isa_rgf_num_banks=2
nsim_isa_rgf_banked_regs=32
nsim_isa_rgf_num_regs=32
nsim_isa_rgf_num_wr_ports=2
nsim_isa_big_endian=0
nsim_isa_lpc_size=32
nsim_isa_pc_size=32
nsim_isa_addr_size=32
nsim_isa_atomic_option=1
nsim_isa_ll64_option=1
nsim_isa_u... | /content/code_sandbox/boards/snps/nsim/arc_classic/support/nsim_hs_sram.props | xml | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 453 |
```unknown
-arcv3hs
-core0
-Xdual_issue
-uarch_rev=0:0
-rgf_num_banks=1
-rgf_num_wr_ports=2
-lpc_width=0
-Xatomic=2
-Xll64
-Xunaligned
-Xdiv_rem=radix4
-Xmpy_option=qmpyh
-Xtimer0
-Xtimer0_level=0
-Xtimer1
-Xtimer1_level=0
-Xrtc
-action_points=8
-ap_feature=1
-Xstack_check
-bpu_bc_entries=2048
-bpu_pt_entries=16384
-bp... | /content/code_sandbox/boards/snps/nsim/arc_classic/support/mdb_hs5x_smp_12cores.args | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 454 |
```unknown
-nogoifmain
-noprofile
-arc64
-core0
-Xdual_issue
-uarch_rev=0:0
-rgf_num_banks=1
-rgf_num_wr_ports=2
-Xm128
-Xatomic=2
-Xunaligned
-Xmpy_cycles=3
-Xtimer0
-Xtimer0_level=0
-Xtimer1
-Xtimer1_level=0
-Xrtc
-action_points=8
-ap_feature=1
-Xstack_check
-bpu_bc_entries=2048
-bpu_pt_entries=... | /content/code_sandbox/boards/snps/nsim/arc_classic/support/mdb_hs6x.args | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 403 |
```xml
maxlastpc=0
trace_enabled=0
nsim_isa_family=arc64
nsim_isa_core=0
arcver=0x70
nsim_isa_dual_issue_option=1
nsim_isa_uarch_rev_major=0
nsim_isa_uarch_rev_minor=0
nsim_isa_rgf_num_banks=1
nsim_isa_rgf_num_regs=32
nsim_isa_rgf_num_wr_ports=2
nsim_isa_big_endian=0
nsim_isa_m128_option=1
nsim_isa_atomic... | /content/code_sandbox/boards/snps/nsim/arc_classic/support/nsim_hs6x.props | xml | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 585 |
```unknown
-arcv2em
-core2
-rgf_num_banks=1
-rgf_num_wr_ports=1
-Xcode_density
-Xdiv_rem=radix2
-turbo_boost
-Xswap
-Xbitscan
-Xmpy_option=mpyd
-Xshift_assist
-Xbarrel_shifter
-Xdsp2
-Xdsp_complex
-Xdsp_divsqrt=radix2
-Xdsp_accshift=limited
-Xfpus_div
-Xfpu_mac
-Xfpuda
-Xfpus_mpy_slow
-Xfpus_div_sl... | /content/code_sandbox/boards/snps/nsim/arc_classic/support/mdb_em7d_v22.args | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 418 |
```xml
nsim_isa_family=av2hs
nsim_isa_core=2
arcver=0x52
nsim_isa_rgf_num_banks=2
nsim_isa_rgf_banked_regs=32
nsim_isa_rgf_num_regs=32
nsim_isa_rgf_num_wr_ports=2
nsim_isa_big_endian=0
nsim_isa_lpc_size=32
nsim_isa_pc_size=32
nsim_isa_addr_size=32
nsim_isa_atomic_option=1
nsim_isa_ll64_option=1
nsim_isa_u... | /content/code_sandbox/boards/snps/nsim/arc_classic/support/nsim_hs_mpuv6.props | xml | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 509 |
```xml
nsim_isa_family=av2hs
nsim_isa_core=2
arcver=0x52
nsim_isa_rgf_num_banks=2
nsim_isa_rgf_banked_regs=32
nsim_isa_rgf_num_regs=32
nsim_isa_rgf_num_wr_ports=2
nsim_isa_big_endian=0
nsim_isa_lpc_size=32
nsim_isa_pc_size=32
nsim_isa_addr_size=32
nsim_isa_atomic_option=1
nsim_isa_ll64_option=1
nsim_isa_u... | /content/code_sandbox/boards/snps/nsim/arc_classic/support/nsim_hs_hostlink.props | xml | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 484 |
```unknown
-nogoifmain
-noprofile
-arc64
-core0
-Xdual_issue
-uarch_rev=0:0
-rgf_num_banks=1
-rgf_num_wr_ports=2
-Xm128
-Xatomic=2
-Xunaligned
-Xmpy_cycles=3
-Xtimer0
-Xtimer0_level=0
-Xtimer1
-Xtimer1_level=0
-Xrtc
-action_points=8
-ap_feature=1
-Xstack_check
-bpu_bc_entries=2048
-bpu_pt_entries=... | /content/code_sandbox/boards/snps/nsim/arc_classic/support/mdb_hs6x_smp.args | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 506 |
```unknown
-arcv2hs
-core2
-arcnum=3
-rgf_num_banks=2
-rgf_banked_regs=32
-rgf_num_wr_ports=2
-Xatomic
-Xll64
-Xunaligned
-Xcode_density
-Xdiv_rem=radix4
-Xswap
-Xbitscan
-Xmpy_option=qmpyh
-Xshift_assist
-Xbarrel_shifter
-Xfpud_div
-Xfpu_mac
-Xtimer0
-Xtimer0_level=1
-Xtimer1
-Xtimer1_level=0
-X... | /content/code_sandbox/boards/snps/nsim/arc_classic/support/mdb_hs_hostlink.args | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 327 |
```unknown
-arcv3hs
-core0
-Xdual_issue
-uarch_rev=0:0
-rgf_num_banks=1
-rgf_num_wr_ports=2
-lpc_width=0
-Xatomic=2
-Xll64
-Xunaligned
-Xdiv_rem=radix4
-Xmpy_option=qmpyh
-Xtimer0
-Xtimer0_level=0
-Xtimer1
-Xtimer1_level=0
-Xrtc
-action_points=8
-ap_feature=1
-Xstack_check
-bpu_bc_entries=2048
-bpu_pt_entries=16384
-bp... | /content/code_sandbox/boards/snps/nsim/arc_classic/support/mdb_hs5x.args | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 360 |
```xml
nsim_isa_family=av2em
nsim_isa_core=3
arcver=0x3
nsim_isa_rgf_num_banks=1
nsim_isa_rgf_banked_regs=32
nsim_isa_rgf_num_regs=32
nsim_isa_rgf_num_wr_ports=2
nsim_isa_big_endian=0
nsim_isa_lpc_size=32
nsim_isa_pc_size=32
nsim_isa_addr_size=32
nsim_isa_code_density_option=2
nsim_isa_div_rem_option=1
ns... | /content/code_sandbox/boards/snps/nsim/arc_classic/support/nsim_em11d.props | xml | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 769 |
```xml
nsim_isa_family=av2hs
nsim_isa_core=2
arcver=0x52
nsim_isa_rgf_num_banks=2
nsim_isa_rgf_banked_regs=32
nsim_isa_rgf_num_regs=32
nsim_isa_rgf_num_wr_ports=2
nsim_isa_big_endian=0
nsim_isa_lpc_size=32
nsim_isa_pc_size=32
nsim_isa_addr_size=32
nsim_isa_atomic_option=1
nsim_isa_ll64_option=1
nsim_isa_u... | /content/code_sandbox/boards/snps/nsim/arc_classic/support/nsim_hs.props | xml | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 509 |
```unknown
-arcv2hs
-core2
-arcnum=3
-rgf_num_banks=2
-rgf_banked_regs=32
-rgf_num_wr_ports=2
-Xatomic
-Xll64
-Xunaligned
-Xcode_density
-Xdiv_rem=radix4
-Xswap
-Xbitscan
-Xmpy_option=qmpyh
-Xshift_assist
-Xbarrel_shifter
-Xfpud_div
-Xfpu_mac
-Xtimer0
-Xtimer0_level=1
-Xtimer1
-Xtimer1_level=0
-X... | /content/code_sandbox/boards/snps/nsim/arc_classic/support/mdb_hs_flash_xip.args | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 297 |
```xml
nsim_isa_family=av2em
nsim_isa_core=2
arcver=0x42
nsim_isa_rgf_num_banks=1
nsim_isa_rgf_num_regs=32
nsim_isa_rgf_num_wr_ports=1
nsim_isa_big_endian=0
nsim_isa_lpc_size=32
nsim_isa_pc_size=32
nsim_isa_addr_size=32
nsim_isa_code_density_option=2
nsim_isa_div_rem_option=1
nsim_isa_turbo_boost=1
nsim_i... | /content/code_sandbox/boards/snps/nsim/arc_classic/support/nsim_em7d_v22.props | xml | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 622 |
```unknown
-arcv2em
-core3
-rgf_num_banks=1
-rgf_banked_regs=32
-rgf_num_wr_ports=2
-Xcode_density
-Xdiv_rem=radix2
-turbo_boost
-Xswap
-Xbitscan
-Xmpy_option=mpyd
-mpu
-mpu_regions=16
-Xshift_assist
-Xbarrel_shifter
-Xdsp2
-Xdsp_complex
-Xdsp_divsqrt=radix2
-Xdsp_itu
-Xdsp_accshift=full
-Xagu_larg... | /content/code_sandbox/boards/snps/nsim/arc_classic/support/mdb_em11d.args | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 502 |
```unknown
-arcv2hs
-core2
-rgf_num_banks=2
-rgf_banked_regs=32
-rgf_num_wr_ports=2
-Xatomic
-Xll64
-Xunaligned
-Xcode_density
-Xdiv_rem=radix4
-Xswap
-Xbitscan
-Xmpy_option=qmpyh
-Xshift_assist
-Xbarrel_shifter
-Xfpud_div
-Xfpu_mac
-Xtimer0
-Xtimer0_level=1
-Xtimer1
-Xtimer1_level=0
-Xrtc
-actio... | /content/code_sandbox/boards/snps/nsim/arc_classic/support/mdb_hs_smp.args | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 402 |
```xml
nsim_isa_family=av2em
nsim_isa_core=3
arcver=0x43
nsim_isa_rgf_num_banks=1
nsim_isa_rgf_num_regs=32
nsim_isa_rgf_num_wr_ports=1
nsim_isa_big_endian=0
nsim_isa_lpc_size=32
nsim_isa_pc_size=32
nsim_isa_addr_size=32
nsim_isa_code_density_option=2
nsim_isa_div_rem_option=1
nsim_isa_turbo_boost=1
nsim_i... | /content/code_sandbox/boards/snps/nsim/arc_classic/support/nsim_sem_mpu_stack_guard.props | xml | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 674 |
```xml
nsim_isa_family=av2hs
nsim_isa_core=4
arcver=0x54
nsim_isa_uarch_rev_major=1
nsim_isa_uarch_rev_minor=4
nsim_isa_code_density_option=2
nsim_isa_rgf_num_banks=1
nsim_isa_rgf_num_regs=32
nsim_isa_rgf_num_wr_ports=2
nsim_isa_big_endian=0
nsim_isa_lpc_size=32
nsim_isa_pc_size=32
nsim_isa_addr_size=32
n... | /content/code_sandbox/boards/snps/nsim/arc_classic/support/nsim_vpx5.props | xml | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 1,080 |
```unknown
-arcv2hs
-core4
-uarch_rev=1:4
-Xcode_density
-rgf_num_banks=1
-rgf_num_wr_ports=2
-Xatomic
-Xll64
-Xunaligned
-Xdiv_rem=radix4
-Xswap
-Xbitscan
-Xmpy_option=qmpyh
-Xshift_assist
-Xbarrel_shifter
-Xtimer0
-Xtimer0_level=0
-Xtimer1
-Xtimer1_level=0
-Xrtc
-action_points=8
-ap_feature=1
-... | /content/code_sandbox/boards/snps/nsim/arc_classic/support/mdb_vpx5.args | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 762 |
```unknown
-arcv3hs
-core0
-Xdual_issue
-uarch_rev=0:0
-rgf_num_banks=1
-rgf_num_wr_ports=2
-lpc_width=0
-Xatomic=2
-Xll64
-Xunaligned
-Xdiv_rem=radix4
-Xmpy_option=qmpyh
-Xtimer0
-Xtimer0_level=0
-Xtimer1
-Xtimer1_level=0
-Xrtc
-action_points=8
-ap_feature=1
-Xstack_check
-bpu_bc_entries=2048
-bpu_pt_entries=16384
-bp... | /content/code_sandbox/boards/snps/nsim/arc_classic/support/mdb_hs5x_smp.args | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 454 |
```unknown
-arcv2em
-core3
-rgf_num_banks=1
-rgf_num_wr_ports=1
-Xcode_density
-Xdiv_rem=radix2
-turbo_boost
-Xswap
-Xbitscan
-Xmpy_option=mpyd
-Xshift_assist
-Xbarrel_shifter
-Xdsp2
-Xdsp_complex
-Xdsp_divsqrt=radix2
-Xdsp_accshift=limited
-Xfpus_div
-Xfpu_mac
-Xfpuda
-Xfpus_mpy_slow
-Xfpus_div_sl... | /content/code_sandbox/boards/snps/nsim/arc_classic/support/mdb_sem_mpu_stack_guard.args | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 464 |
```xml
nsim_isa_family=av2hs
nsim_isa_core=2
arcver=0x52
nsim_isa_rgf_num_banks=2
nsim_isa_rgf_banked_regs=32
nsim_isa_rgf_num_regs=32
nsim_isa_rgf_num_wr_ports=2
nsim_isa_big_endian=0
nsim_isa_lpc_size=32
nsim_isa_pc_size=32
nsim_isa_addr_size=32
nsim_isa_atomic_option=1
nsim_isa_ll64_option=1
nsim_isa_u... | /content/code_sandbox/boards/snps/nsim/arc_classic/support/nsim_hs_flash_xip.props | xml | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 453 |
```unknown
-arcv2em
-core3
-rgf_num_banks=2
-rgf_banked_regs=32
-rgf_num_wr_ports=2
-Xcode_density
-Xdiv_rem=radix2
-turbo_boost
-Xswap
-Xbitscan
-Xmpy_option=mpyd
-mpu
-mpu_regions=16
-Xshift_assist
-Xbarrel_shifter
-Xdsp2
-Xdsp_complex
-Xdsp_divsqrt=radix2
-Xdsp_itu
-Xdsp_accshift=full
-Xagu_larg... | /content/code_sandbox/boards/snps/nsim/arc_classic/support/mdb_em.args | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 493 |
```unknown
-arcv2hs
-core2
-arcnum=3
-rgf_num_banks=2
-rgf_banked_regs=32
-rgf_num_wr_ports=2
-Xatomic
-Xll64
-Xunaligned
-Xcode_density
-Xdiv_rem=radix4
-Xswap
-Xbitscan
-Xmpy_option=qmpyh
-Xshift_assist
-Xbarrel_shifter
-Xfpud_div
-Xfpu_mac
-Xtimer0
-Xtimer0_level=1
-Xtimer1
-Xtimer1_level=0
-X... | /content/code_sandbox/boards/snps/nsim/arc_classic/support/mdb_hs_sram.args | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 297 |
```xml
nsim_isa_family=av2em
nsim_isa_core=3
arcver=0x3
nsim_isa_rgf_num_banks=2
nsim_isa_rgf_banked_regs=32
nsim_isa_rgf_num_regs=32
nsim_isa_rgf_num_wr_ports=2
nsim_isa_big_endian=0
nsim_isa_lpc_size=32
nsim_isa_pc_size=32
nsim_isa_addr_size=32
nsim_isa_code_density_option=2
nsim_isa_div_rem_option=1
ns... | /content/code_sandbox/boards/snps/nsim/arc_classic/support/nsim_em.props | xml | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 754 |
```unknown
-arcv2hs
-core2
-arcnum=3
-rgf_num_banks=2
-rgf_banked_regs=32
-rgf_num_wr_ports=2
-Xatomic
-Xll64
-Xunaligned
-Xcode_density
-Xdiv_rem=radix4
-Xswap
-Xbitscan
-Xmpy_option=qmpyh
-mpuv6
-mpu_regions=32
-Xshift_assist
-Xbarrel_shifter
-Xfpud_div
-Xfpu_mac
-Xtimer0
-Xtimer0_level=1
-Xtim... | /content/code_sandbox/boards/snps/nsim/arc_classic/support/mdb_hs_mpuv6.args | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 355 |
```xml
nsim_isa_family=av2em
nsim_isa_core=3
arcver=0x43
nsim_isa_rgf_num_banks=1
nsim_isa_rgf_num_regs=32
nsim_isa_rgf_num_wr_ports=1
nsim_isa_big_endian=0
nsim_isa_lpc_size=32
nsim_isa_pc_size=32
nsim_isa_addr_size=32
nsim_isa_code_density_option=2
nsim_isa_div_rem_option=1
nsim_isa_turbo_boost=1
nsim_i... | /content/code_sandbox/boards/snps/nsim/arc_classic/support/nsim_sem.props | xml | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 674 |
```unknown
-arc64
-core0
-Xdual_issue
-uarch_rev=0:0
-rgf_num_banks=1
-rgf_num_wr_ports=2
-Xm128
-Xatomic=2
-Xunaligned
-Xmpy_cycles=3
-Xtimer0
-Xtimer0_level=0
-Xtimer1
-Xtimer1_level=0
-Xrtc
-action_points=8
-ap_feature=1
-Xstack_check
-bpu_bc_entries=2048
-bpu_pt_entries=16384
-bpu_rs_entries=4
... | /content/code_sandbox/boards/snps/nsim/arc_classic/support/mdb_hs6x_smp_12cores.args | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 506 |
```unknown
-arcv2em
-core3
-rgf_num_banks=1
-rgf_num_wr_ports=1
-Xcode_density
-Xdiv_rem=radix2
-turbo_boost
-Xswap
-Xbitscan
-Xmpy_option=mpyd
-Xshift_assist
-Xbarrel_shifter
-Xdsp2
-Xdsp_complex
-Xdsp_divsqrt=radix2
-Xdsp_accshift=limited
-Xfpus_div
-Xfpu_mac
-Xfpuda
-Xfpus_mpy_slow
-Xfpus_div_sl... | /content/code_sandbox/boards/snps/nsim/arc_classic/support/mdb_sem.args | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 464 |
```cmake
set(SUPPORTED_EMU_PLATFORMS nsim)
string(SUBSTRING "${BOARD_QUALIFIERS}" 1 -1 NSIM_BASE_FILENAME)
string(REPLACE "/" "_" NSIM_BASE_FILENAME "${NSIM_BASE_FILENAME}")
board_set_flasher_ifnset(arc-nsim)
board_set_debugger_ifnset(arc-nsim)
set(NSIM_PROPS "${NSIM_BASE_FILENAME}.props")
board_runner_args(arc-nsi... | /content/code_sandbox/boards/snps/nsim/arc_v/board.cmake | cmake | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 144 |
```unknown
CONFIG_XIP=n
CONFIG_CONSOLE=y
CONFIG_SERIAL=y
CONFIG_UART_CONSOLE=y
CONFIG_BUILD_OUTPUT_HEX=y
CONFIG_INCLUDE_RESET_VECTOR=y
CONFIG_LOG=y
``` | /content/code_sandbox/boards/snps/nsim/arc_v/nsim_arc_v_rmx100_defconfig | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 36 |
```yaml
identifier: nsim_arc_v/rmx100
name: Synopsys rmx100
simulation: nsim
simulation_exec: nsimdrv
type: sim
arch: riscv
toolchain:
- zephyr
- cross-compile
- arcmwdt
testing:
ignore_tags:
- net
- bluetooth
vendor: snps
``` | /content/code_sandbox/boards/snps/nsim/arc_v/nsim_arc_v_rmx100.yaml | yaml | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 83 |
```unknown
/dts-v1/;
#include "rmx100.dtsi"
/ {
model = "Synopsys RMX100";
compatible = "snps,rmx100";
aliases {
uart-0 = &uart0;
};
chosen {
zephyr,sram = &ddr0;
zephyr,console = &uart0;
zephyr,shell-uart = &uart0;
};
};
&uart0 {
status = "okay";
current-speed = <115200>;
};
``` | /content/code_sandbox/boards/snps/nsim/arc_v/nsim_arc_v_rmx100.dts | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 113 |
```yaml
board:
name: nsim_arc_v
vendor: snps
socs:
- name: rmx100
``` | /content/code_sandbox/boards/snps/nsim/arc_v/board.yml | yaml | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 29 |
```unknown
#include "rmx1xx.dtsi"
/ {
ddr0: memory@80000000 {
device_type = "memory";
reg = <0x80000000 0x10000000>; /* 256 MB */
};
};
``` | /content/code_sandbox/boards/snps/nsim/arc_v/rmx100.dtsi | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 55 |
```unknown
if BOARD_NSIM_ARC_V_RMX100
config SYS_CLOCK_TICKS_PER_SEC
default 1000
config SYS_CLOCK_HW_CYCLES_PER_SEC
default 5000000
endif # BOARD_NSIM_ARC_V_RMX100
``` | /content/code_sandbox/boards/snps/nsim/arc_v/Kconfig.defconfig | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 54 |
```unknown
config BOARD_NSIM_ARC_V
select SOC_RMX100 if BOARD_NSIM_ARC_V_RMX100
``` | /content/code_sandbox/boards/snps/nsim/arc_v/Kconfig.nsim_arc_v | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 26 |
```unknown
/ {
#address-cells = <1>;
#size-cells = <1>;
cpus {
timebase-frequency = <5000000>;
#address-cells = <1>;
#size-cells = <0>;
cpu0: cpu@0 {
compatible = "snps,av5rmx", "riscv";
device_type = "cpu";
reg = <0>;
clock-frequency = <5000000>;
riscv,isa = "rv32imac_zicsr_zifence... | /content/code_sandbox/boards/snps/nsim/arc_v/rmx1xx.dtsi | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 436 |
```xml
nsim_isa_family=rv32
nsim_isa_ext=-all.i.zicsr.zifencei.zihintpause.a.m.zba.zbb.zbs.zca.zcb.zcmp.zcmt.zicbom
nsim_isa_big_endian=0
nsim_mem-dev=clint,base=0x2000000,size=4096
nsim_mem-dev=uart0,kind=16550,base=0x10000000,irq=24
nsim_mem-dev=plic,base=0xc000000,size=0x04000000,interrupts=128,priorities=16
... | /content/code_sandbox/boards/snps/nsim/arc_v/support/rmx100.props | xml | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 156 |
```restructuredtext
.. _nsim:
DesignWare ARC nSIM and HAPS FPGA boards
########################################
Overview
********
This platform can be used to run Zephyr RTOS on the widest possible range of ARC processors in
simulation with `Designware ARC nSIM`_ or run same images on FPGA prototyping platform `HAPS... | /content/code_sandbox/boards/snps/nsim/arc_classic/doc/index.rst | restructuredtext | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 3,880 |
```restructuredtext
.. _boards-olimex:
OLIMEX Ltd.
###########
.. toctree::
:maxdepth: 1
:glob:
**/*
``` | /content/code_sandbox/boards/olimex/index.rst | restructuredtext | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 36 |
```cmake
board_runner_args(pyocd "--target=stm32wle5ccux")
board_runner_args(pyocd "--flash-opt=-O cmsis_dap.limit_packets=1")
board_runner_args(jlink "--device=STM32WLE5CC" "--speed=4000" "--reset-after-load")
include(${ZEPHYR_BASE}/boards/common/pyocd.board.cmake)
include(${ZEPHYR_BASE}/boards/common/jlink.board.cm... | /content/code_sandbox/boards/olimex/lora_stm32wl_devkit/board.cmake | cmake | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 117 |
```yaml
identifier: olimex_lora_stm32wl_devkit
name: Olimex LoRa STM32WL DevKit
type: mcu
arch: arm
toolchain:
- zephyr
- gnuarmemb
- xtools
ram: 64
flash: 256
supported:
- counter
- gpio
- i2c
- nvs
- spi
- uart
- watchdog
- lora
vendor: olimex
``` | /content/code_sandbox/boards/olimex/lora_stm32wl_devkit/olimex_lora_stm32wl_devkit_C.yaml | yaml | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 112 |
```yaml
identifier: olimex_lora_stm32wl_devkit@D
name: Olimex LoRa STM32WL DevKit (rev. D)
type: mcu
arch: arm
toolchain:
- zephyr
- gnuarmemb
- xtools
ram: 64
flash: 256
supported:
- counter
- gpio
- i2c
- nvs
- spi
- uart
- watchdog
- lora
vendor: olimex
``` | /content/code_sandbox/boards/olimex/lora_stm32wl_devkit/olimex_lora_stm32wl_devkit_D.yaml | yaml | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 118 |
```restructuredtext
.. _nsim_arc_v:
DesignWare RISC-V nSIM and HAPS FPGA boards
###########################################
Overview
********
This platform can be used to run Zephyr RTOS on the widest possible range of Synopsys RISC-V processors in
simulation with `Designware ARC nSIM`_ or run same images on FPGA pr... | /content/code_sandbox/boards/snps/nsim/arc_v/doc/index.rst | restructuredtext | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 1,954 |
```unknown
# enable uart driver
CONFIG_SERIAL=y
# enable GPIO
CONFIG_GPIO=y
# Enable Clocks
CONFIG_CLOCK_CONTROL=y
# console
CONFIG_CONSOLE=y
CONFIG_UART_CONSOLE=y
# Enable MPU
CONFIG_ARM_MPU=y
# Enable HW stack protection
CONFIG_HW_STACK_PROTECTION=y
# enable pin controller
CONFIG_PINCTRL=y
``` | /content/code_sandbox/boards/olimex/lora_stm32wl_devkit/olimex_lora_stm32wl_devkit_defconfig | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 73 |
```unknown
# Regulator support
CONFIG_REGULATOR=y
``` | /content/code_sandbox/boards/olimex/lora_stm32wl_devkit/olimex_lora_stm32wl_devkit_D.conf | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 11 |
```yaml
board:
name: olimex_lora_stm32wl_devkit
vendor: olimex
revision:
format: letter
default: "C"
revisions:
- name: "C"
- name: "D"
socs:
- name: stm32wle5xx
``` | /content/code_sandbox/boards/olimex/lora_stm32wl_devkit/board.yml | yaml | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 71 |
```unknown
/*
*
*/
#include "olimex_lora_stm32wl_devkit_C.overlay"
``` | /content/code_sandbox/boards/olimex/lora_stm32wl_devkit/olimex_lora_stm32wl_devkit_D.overlay | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 20 |
```unknown
config BOARD_OLIMEX_LORA_STM32WL_DEVKIT
select SOC_STM32WLE5XX
``` | /content/code_sandbox/boards/olimex/lora_stm32wl_devkit/Kconfig.olimex_lora_stm32wl_devkit | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 27 |
```unknown
# Regulator support
CONFIG_REGULATOR=y
``` | /content/code_sandbox/boards/olimex/lora_stm32wl_devkit/olimex_lora_stm32wl_devkit_C.conf | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 11 |
```unknown
/*
*
*/
/dts-v1/;
#include <olimex/bb-stm32wl.dtsi>
#include <zephyr/dt-bindings/input/input-event-codes.h>
/ {
model = "Olimex LoRa STM32WL DevKit";
compatible = "olimex,lora-stm32wl-devkit";
chosen {
zephyr,console = &usart1;
zephyr,shell-uart = &usart1;
zephyr,sram = &sram0;
zephyr,flash =... | /content/code_sandbox/boards/olimex/lora_stm32wl_devkit/olimex_lora_stm32wl_devkit.dts | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 1,046 |
```unknown
/*
*
*/
/ {
/* Controls 3.3V VDDIO supply for UEXT1 connector and CON1 header */
vddio_reg: fet2_regulator {
compatible = "regulator-fixed";
enable-gpios = <&gpiob 12 (GPIO_ACTIVE_LOW | GPIO_OPEN_DRAIN)>;
regulator-name = "fet2_regulator";
regulator-boot-on;
};
};
``` | /content/code_sandbox/boards/olimex/lora_stm32wl_devkit/olimex_lora_stm32wl_devkit_C.overlay | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 91 |
```unknown
config BOARD_OLIMEX_STM32_P405
select SOC_STM32F405XX
``` | /content/code_sandbox/boards/olimex/stm32_p405/Kconfig.olimex_stm32_p405 | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 23 |
```cmake
board_runner_args(jlink "--device=STM32F405RG" "--speed=4000")
include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake)
include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake)
``` | /content/code_sandbox/boards/olimex/stm32_p405/board.cmake | cmake | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 55 |
```unknown
/*
*
*/
/dts-v1/;
#include <st/f4/stm32f405Xg.dtsi>
#include <st/f4/stm32f405rgtx-pinctrl.dtsi>
#include <zephyr/dt-bindings/input/input-event-codes.h>
/ {
model = "Olimex STM32-P405 board";
compatible = "olimex,stm32-p405";
chosen {
zephyr,console = &usart2;
zephyr,shell-uart = &usart2;
zephyr... | /content/code_sandbox/boards/olimex/stm32_p405/olimex_stm32_p405.dts | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 578 |
```yaml
identifier: olimex_stm32_p405
name: OLIMEX-STM32-P405
type: mcu
arch: arm
toolchain:
- zephyr
- gnuarmemb
- xtools
ram: 128
flash: 1024
supported:
- counter
- can
vendor: olimex
``` | /content/code_sandbox/boards/olimex/stm32_p405/olimex_stm32_p405.yaml | yaml | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 80 |
```yaml
board:
name: olimex_stm32_p405
vendor: olimex
socs:
- name: stm32f405xx
``` | /content/code_sandbox/boards/olimex/stm32_p405/board.yml | yaml | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 36 |
```unknown
# Enable MPU
CONFIG_ARM_MPU=y
# Enable HW stack protection
CONFIG_HW_STACK_PROTECTION=y
CONFIG_SERIAL=y
# console
CONFIG_CONSOLE=y
CONFIG_UART_CONSOLE=y
# enable GPIO
CONFIG_GPIO=y
# Enable Clocks
CONFIG_CLOCK_CONTROL=y
CONFIG_ENTROPY_GENERATOR=y
# enable pin controller
CONFIG_PINCTRL=y
``` | /content/code_sandbox/boards/olimex/stm32_p405/olimex_stm32_p405_defconfig | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 77 |
```ini
source [find interface/stlink.cfg]
set WORKAREASIZE 0x10000
transport select hla_swd
source [find target/stm32f4x.cfg]
adapter speed 1000
adapter srst delay 100
jtag_ntrst_delay 100
reset_config srst_only srst_nogate
$_TARGETNAME configure -event gdb-attach {
echo "Debugger attaching: halting execution"
... | /content/code_sandbox/boards/olimex/stm32_p405/support/openocd.cfg | ini | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 126 |
```restructuredtext
.. _olimex_lora_stm32wl_devkit:
Olimex LoRa STM32WL DevKit
##########################
Overview
********
LoRaWAN development kit based on Olimex BB-STM32WL module using the
STM32WLE5CCU6 MCU.
.. figure:: olimex-stm32wl-devkit.jpg
:align: center
:alt: Olimex LoRa STM32WL DevKit
Oli... | /content/code_sandbox/boards/olimex/lora_stm32wl_devkit/doc/olimex_lora_stm32wl_devkit.rst | restructuredtext | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 1,373 |
```yaml
identifier: olimex_stm32_h103
name: OLIMEX-STM32-H103
type: mcu
arch: arm
toolchain:
- zephyr
- gnuarmemb
- xtools
ram: 20
flash: 128
supported:
- gpio
- uart
- watchdog
testing:
ignore_tags:
- bluetooth
- net
vendor: olimex
``` | /content/code_sandbox/boards/olimex/stm32_h103/olimex_stm32_h103.yaml | yaml | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 97 |
```cmake
board_runner_args(blackmagicprobe "--connect-rst")
board_runner_args(jlink "--device=STM32F103RB" "--speed=4000")
include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake)
include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake)
include(${ZEPHYR_BASE}/boards/common/blackmagicprobe.board.cmake)
``` | /content/code_sandbox/boards/olimex/stm32_h103/board.cmake | cmake | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 84 |
```unknown
# enable uart driver
CONFIG_SERIAL=y
# enable console
CONFIG_CONSOLE=y
CONFIG_UART_CONSOLE=y
# enable GPIO
CONFIG_GPIO=y
# enable clocks
CONFIG_CLOCK_CONTROL=y
# enable pin controller
CONFIG_PINCTRL=y
``` | /content/code_sandbox/boards/olimex/stm32_h103/olimex_stm32_h103_defconfig | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 51 |
```unknown
/*
*/
/dts-v1/;
#include <st/f1/stm32f103Xb.dtsi>
#include <st/f1/stm32f103r(8-b)tx-pinctrl.dtsi>
#include <zephyr/dt-bindings/input/input-event-codes.h>
/ {
model = "Olimex STM32-H103 board";
compatible = "olimex,stm32-h103";
chosen {
zephyr,console = &usart2;
zephyr,shell-uart = &usart2;
zephy... | /content/code_sandbox/boards/olimex/stm32_h103/olimex_stm32_h103.dts | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 852 |
```unknown
config BOARD_OLIMEX_STM32_H103
select SOC_STM32F103XB
``` | /content/code_sandbox/boards/olimex/stm32_h103/Kconfig.olimex_stm32_h103 | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 23 |
```yaml
board:
name: olimex_stm32_h103
vendor: olimex
socs:
- name: stm32f103xb
``` | /content/code_sandbox/boards/olimex/stm32_h103/board.yml | yaml | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 36 |
```ini
source [find interface/stlink.cfg]
transport select hla_swd
source [find board/olimex_stm32_h103.cfg]
$_TARGETNAME configure -event gdb-attach {
echo "Debugger attaching: halting execution"
reset halt
gdb_breakpoint_override hard
}
$_TARGETNAME configure -event gdb-detach {
ec... | /content/code_sandbox/boards/olimex/stm32_h103/support/openocd.cfg | ini | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 88 |
```ini
source [find interface/ftdi/olimex-arm-usb-ocd-h.cfg]
transport select jtag
source [find board/olimex_stm32_h103.cfg]
adapter speed 1000
adapter srst delay 100
jtag_ntrst_delay 100
reset_config srst_only srst_nogate
$_TARGETNAME configure -event gdb-attach {
echo "Debugger attaching: halting executi... | /content/code_sandbox/boards/olimex/stm32_h103/support/openocd_olimex_jtag.cfg | ini | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 131 |
```ini
source [find interface/stlink.cfg]
transport select hla_swd
source [find board/olimex_stm32_h103.cfg]
$_TARGETNAME configure -event gdb-attach {
echo "Debugger attaching: halting execution"
reset halt
gdb_breakpoint_override hard
}
$_TARGETNAME configure -event gdb-detach {
ec... | /content/code_sandbox/boards/olimex/stm32_h103/support/openocd_stlink.cfg | ini | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 88 |
```restructuredtext
.. _olimex_stm32_p405:
OLIMEX-STM32-P405
#################
Overview
********
The OLIMEX-STM32-P405 board is based on the STMicroelectronics STM32F405RG ARM
Cortex-M4 CPU.
.. figure:: img/olimex_stm32_p405.jpg
:align: center
:alt: OLIMEX-STM32-P405
OLIMEX-STM32-P405
Hardware
****... | /content/code_sandbox/boards/olimex/stm32_p405/doc/index.rst | restructuredtext | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 2,292 |
```unknown
config BOARD_OLIMEX_STM32_E407
select SOC_STM32F407XG
``` | /content/code_sandbox/boards/olimex/stm32_e407/Kconfig.olimex_stm32_e407 | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 24 |
Subsets and Splits
No community queries yet
The top public SQL queries from the community will appear here once available.