text stringlengths 9 39.2M | dir stringlengths 25 226 | lang stringclasses 163 values | created_date timestamp[s] | updated_date timestamp[s] | repo_name stringclasses 751 values | repo_full_name stringclasses 752 values | star int64 1.01k 183k | len_tokens int64 1 18.5M |
|---|---|---|---|---|---|---|---|---|
```objective-c
/*
*
*/
#ifndef ZEPHYR_DRIVERS_SERIAL_UART_S32_LINFLEXD_H_
#define ZEPHYR_DRIVERS_SERIAL_UART_S32_LINFLEXD_H_
struct uart_nxp_s32_config {
uint32_t instance;
LINFLEXD_Type *base;
const struct pinctrl_dev_config *pincfg;
Linflexd_Uart_Ip_UserConfigType hw_cfg;
};
#ifdef CONFIG_UART_INTERRUPT_DRIVEN
struct uart_nxp_s32_int {
bool tx_fifo_busy;
bool rx_fifo_busy;
bool irq_tx_enable;
bool irq_rx_enable;
uint8_t rx_fifo_data;
};
#endif
#ifdef CONFIG_UART_INTERRUPT_DRIVEN
struct uart_nxp_s32_data {
struct uart_nxp_s32_int int_data;
uart_irq_callback_user_data_t callback;
void *cb_data;
};
#endif /* CONFIG_UART_INTERRUPT_DRIVEN */
extern Linflexd_Uart_Ip_StateStructureType
Linflexd_Uart_Ip_apStateStructure[LINFLEXD_UART_IP_NUMBER_OF_INSTANCES];
#endif /* ZEPHYR_DRIVERS_SERIAL_UART_S32_LINFLEXD_H_ */
``` | /content/code_sandbox/drivers/serial/uart_nxp_s32_linflexd.h | objective-c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 231 |
```unknown
# Atmel SAM USART configuration options
config USART_SAM
bool "Atmel SAM MCU family USART driver"
default y
depends on DT_HAS_ATMEL_SAM_USART_ENABLED
select SERIAL_HAS_DRIVER
select SERIAL_SUPPORT_INTERRUPT
help
This option enables the USARTx driver for Atmel SAM MCUs.
``` | /content/code_sandbox/drivers/serial/Kconfig.usart_sam | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 67 |
```objective-c
/*
*
*/
#ifndef ZEPHYR_DRIVERS_SERIAL_UART_PL011_REGISTERS_H_
#define ZEPHYR_DRIVERS_SERIAL_UART_PL011_REGISTERS_H_
#include <zephyr/device.h>
/*
* UART PL011 register map structure
*/
struct pl011_regs {
uint32_t dr; /* data register */
union {
uint32_t rsr;
uint32_t ecr;
};
uint32_t reserved_0[4];
uint32_t fr; /* flags register */
uint32_t reserved_1;
uint32_t ilpr;
uint32_t ibrd;
uint32_t fbrd;
uint32_t lcr_h;
uint32_t cr;
uint32_t ifls;
uint32_t imsc;
uint32_t ris;
uint32_t mis;
uint32_t icr;
uint32_t dmacr;
};
static inline
volatile struct pl011_regs *get_uart(const struct device *dev)
{
return (volatile struct pl011_regs *)DEVICE_MMIO_GET(dev);
}
#define PL011_BIT_MASK(x, y) (((2 << x) - 1) << y)
/* PL011 Uart Flags Register */
#define PL011_FR_CTS BIT(0) /* clear to send - inverted */
#define PL011_FR_DSR BIT(1) /* data set ready - inverted */
#define PL011_FR_DCD BIT(2) /* data carrier detect - inverted */
#define PL011_FR_BUSY BIT(3) /* busy transmitting data */
#define PL011_FR_RXFE BIT(4) /* receive FIFO empty */
#define PL011_FR_TXFF BIT(5) /* transmit FIFO full */
#define PL011_FR_RXFF BIT(6) /* receive FIFO full */
#define PL011_FR_TXFE BIT(7) /* transmit FIFO empty */
#define PL011_FR_RI BIT(8) /* ring indicator - inverted */
/* PL011 Integer baud rate register */
#define PL011_IBRD_BAUD_DIVINT_MASK 0xff /* 16 bits of divider */
/* PL011 Fractional baud rate register */
#define PL011_FBRD_BAUD_DIVFRAC 0x3f
#define PL011_FBRD_WIDTH 6u
/* PL011 Receive status register / error clear register */
#define PL011_RSR_ECR_FE BIT(0) /* framing error */
#define PL011_RSR_ECR_PE BIT(1) /* parity error */
#define PL011_RSR_ECR_BE BIT(2) /* break error */
#define PL011_RSR_ECR_OE BIT(3) /* overrun error */
#define PL011_RSR_ERROR_MASK (PL011_RSR_ECR_FE | PL011_RSR_ECR_PE | \
PL011_RSR_ECR_BE | PL011_RSR_ECR_OE)
/* PL011 Line Control Register */
#define PL011_LCRH_BRK BIT(0) /* send break */
#define PL011_LCRH_PEN BIT(1) /* enable parity */
#define PL011_LCRH_EPS BIT(2) /* select even parity */
#define PL011_LCRH_STP2 BIT(3) /* select two stop bits */
#define PL011_LCRH_FEN BIT(4) /* enable FIFOs */
#define PL011_LCRH_WLEN_SHIFT 5 /* word length */
#define PL011_LCRH_WLEN_WIDTH 2
#define PL011_LCRH_SPS BIT(7) /* stick parity bit */
#define PL011_LCRH_WLEN_SIZE(x) (x - 5)
#define PL011_LCRH_FORMAT_MASK (PL011_LCRH_PEN | PL011_LCRH_EPS | \
PL011_LCRH_SPS | \
PL011_BIT_MASK(PL011_LCRH_WLEN_WIDTH, PL011_LCRH_WLEN_SHIFT))
#define PL011_LCRH_PARTIY_EVEN (PL011_LCRH_PEN | PL011_LCRH_EPS)
#define PL011_LCRH_PARITY_ODD (PL011_LCRH_PEN)
#define PL011_LCRH_PARITY_NONE (0)
/* PL011 Control Register */
#define PL011_CR_UARTEN BIT(0) /* enable uart operations */
#define PL011_CR_SIREN BIT(1) /* enable IrDA SIR */
#define PL011_CR_SIRLP BIT(2) /* IrDA SIR low power mode */
#define PL011_CR_LBE BIT(7) /* loop back enable */
#define PL011_CR_TXE BIT(8) /* transmit enable */
#define PL011_CR_RXE BIT(9) /* receive enable */
#define PL011_CR_DTR BIT(10) /* data transmit ready */
#define PL011_CR_RTS BIT(11) /* request to send */
#define PL011_CR_Out1 BIT(12)
#define PL011_CR_Out2 BIT(13)
#define PL011_CR_RTSEn BIT(14) /* RTS hw flow control enable */
#define PL011_CR_CTSEn BIT(15) /* CTS hw flow control enable */
/* PL011 Control Register - vendor-specific fields */
#define PL011_CR_AMBIQ_CLKEN BIT(3) /* clock enable */
#define PL011_CR_AMBIQ_CLKSEL GENMASK(6, 4) /* clock select */
#define PL011_CR_AMBIQ_CLKSEL_NOCLK 0
#define PL011_CR_AMBIQ_CLKSEL_24MHZ 1
#define PL011_CR_AMBIQ_CLKSEL_12MHZ 2
#define PL011_CR_AMBIQ_CLKSEL_6MHZ 3
#define PL011_CR_AMBIQ_CLKSEL_3MHZ 4
#define PL011_CR_AMBIQ_CLKSEL_48MHZ 5
/* PL011 Interrupt Fifo Level Select Register */
#define PL011_IFLS_RXIFLSEL_M GENMASK(5, 3)
#define RXIFLSEL_1_2_FULL 2UL
#define PL011_IFLS_TXIFLSEL_M GENMASK(2, 0)
#define TXIFLSEL_1_8_FULL 0UL
/* PL011 Interrupt Mask Set/Clear Register */
#define PL011_IMSC_RIMIM BIT(0) /* RTR modem interrupt mask */
#define PL011_IMSC_CTSMIM BIT(1) /* CTS modem interrupt mask */
#define PL011_IMSC_DCDMIM BIT(2) /* DCD modem interrupt mask */
#define PL011_IMSC_DSRMIM BIT(3) /* DSR modem interrupt mask */
#define PL011_IMSC_RXIM BIT(4) /* receive interrupt mask */
#define PL011_IMSC_TXIM BIT(5) /* transmit interrupt mask */
#define PL011_IMSC_RTIM BIT(6) /* receive timeout interrupt mask */
#define PL011_IMSC_FEIM BIT(7) /* framing error interrupt mask */
#define PL011_IMSC_PEIM BIT(8) /* parity error interrupt mask */
#define PL011_IMSC_BEIM BIT(9) /* break error interrupt mask */
#define PL011_IMSC_OEIM BIT(10) /* overrun error interrupt mask */
#define PL011_IMSC_ERROR_MASK (PL011_IMSC_FEIM | \
PL011_IMSC_PEIM | PL011_IMSC_BEIM | \
PL011_IMSC_OEIM)
#define PL011_IMSC_MASK_ALL (PL011_IMSC_OEIM | PL011_IMSC_BEIM | \
PL011_IMSC_PEIM | PL011_IMSC_FEIM | \
PL011_IMSC_RIMIM | PL011_IMSC_CTSMIM | \
PL011_IMSC_DCDMIM | PL011_IMSC_DSRMIM | \
PL011_IMSC_RXIM | PL011_IMSC_TXIM | \
PL011_IMSC_RTIM)
/* PL011 Raw Interrupt Status Register */
#define PL011_RIS_TXRIS BIT(5) /* Transmit interrupt status */
#endif /* ZEPHYR_DRIVERS_SERIAL_UART_PL011_REGISTERS_H_ */
``` | /content/code_sandbox/drivers/serial/uart_pl011_registers.h | objective-c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 1,736 |
```c
/*
*
*/
#define DT_DRV_COMPAT neorv32_uart
#include <zephyr/device.h>
#include <zephyr/drivers/syscon.h>
#include <zephyr/drivers/uart.h>
#include <zephyr/pm/device.h>
#include <zephyr/sys/sys_io.h>
#include <zephyr/logging/log.h>
#include <zephyr/irq.h>
#include <soc.h>
LOG_MODULE_REGISTER(uart_neorv32, CONFIG_UART_LOG_LEVEL);
/* NEORV32 UART registers offsets */
#define NEORV32_UART_CTRL_OFFSET 0x00
#define NEORV32_UART_DATA_OFFSET 0x04
/* UART_CTRL register bits */
#define NEORV32_UART_CTRL_EN BIT(0)
#define NEORV32_UART_CTRL_SIM_MODE BIT(1)
#define NEORV32_UART_CTRL_HWFC_EN BIT(2)
#define NEORV32_UART_CTRL_PRSC_POS 3U
#define NEORV32_UART_CTRL_PRSC_MASK BIT_MASK(3)
#define NEORV32_UART_CTRL_BAUD_POS 6U
#define NEORV32_UART_CTRL_BAUD_MASK BIT_MASK(10)
#define NEORV32_UART_CTRL_RX_NEMPTY BIT(16)
#define NEORV32_UART_CTRL_RX_HALF BIT(17)
#define NEORV32_UART_CTRL_RX_FULL BIT(18)
#define NEORV32_UART_CTRL_TX_NEMPTY BIT(19)
#define NEORV32_UART_CTRL_TX_HALF BIT(20)
#define NEORV32_UART_CTRL_TX_FULL BIT(21)
#define NEORV32_UART_CTRL_IRQ_RX_NEMPTY BIT(22)
#define NEORV32_UART_CTRL_IRQ_RX_HALF BIT(23)
#define NEORV32_UART_CTRL_IRQ_RX_FULL BIT(24)
#define NEORV32_UART_CTRL_IRQ_TX_EMPTY BIT(25)
#define NEORV32_UART_CTRL_IRQ_TX_NHALF BIT(26)
#define NEORV32_UART_CTRL_RX_OVER BIT(30)
#define NEORV32_UART_CTRL_TX_BUSY BIT(31)
struct neorv32_uart_config {
const struct device *syscon;
uint32_t feature_mask;
mm_reg_t base;
#ifdef CONFIG_UART_INTERRUPT_DRIVEN
void (*irq_config_func)(const struct device *dev);
unsigned int tx_irq;
unsigned int rx_irq;
#endif /* CONFIG_UART_INTERRUPT_DRIVEN */
};
struct neorv32_uart_data {
struct uart_config uart_cfg;
uint32_t last_data;
#ifdef CONFIG_UART_INTERRUPT_DRIVEN
struct k_timer timer;
uart_irq_callback_user_data_t callback;
void *callback_data;
#endif /* CONFIG_UART_INTERRUPT_DRIVEN */
};
static inline uint32_t neorv32_uart_read_ctrl(const struct device *dev)
{
const struct neorv32_uart_config *config = dev->config;
return sys_read32(config->base + NEORV32_UART_CTRL_OFFSET);
}
static inline void neorv32_uart_write_ctrl(const struct device *dev, uint32_t ctrl)
{
const struct neorv32_uart_config *config = dev->config;
sys_write32(ctrl, config->base + NEORV32_UART_CTRL_OFFSET);
}
static inline uint32_t neorv32_uart_read_data(const struct device *dev)
{
const struct neorv32_uart_config *config = dev->config;
struct neorv32_uart_data *data = dev->data;
uint32_t reg;
/* Cache status bits as they are cleared upon read */
reg = sys_read32(config->base + NEORV32_UART_DATA_OFFSET);
data->last_data = reg;
return reg;
}
static inline void neorv32_uart_write_data(const struct device *dev, uint32_t data)
{
const struct neorv32_uart_config *config = dev->config;
sys_write32(data, config->base + NEORV32_UART_DATA_OFFSET);
}
static int neorv32_uart_poll_in(const struct device *dev, unsigned char *c)
{
uint32_t data;
data = neorv32_uart_read_data(dev);
if ((data & NEORV32_UART_CTRL_RX_NEMPTY) != 0) {
*c = data & BIT_MASK(8);
return 0;
}
return -1;
}
static void neorv32_uart_poll_out(const struct device *dev, unsigned char c)
{
while ((neorv32_uart_read_ctrl(dev) & NEORV32_UART_CTRL_TX_BUSY) != 0) {
}
neorv32_uart_write_data(dev, c);
}
static int neorv32_uart_configure(const struct device *dev, const struct uart_config *cfg)
{
const struct neorv32_uart_config *config = dev->config;
struct neorv32_uart_data *data = dev->data;
uint32_t ctrl = NEORV32_UART_CTRL_EN;
uint16_t baudxx = 0;
uint8_t prscx = 0;
uint32_t clk;
int err;
__ASSERT_NO_MSG(cfg != NULL);
if (cfg->stop_bits != UART_CFG_STOP_BITS_1) {
LOG_ERR("hardware only supports one stop bit");
return -ENOTSUP;
}
if (cfg->data_bits != UART_CFG_DATA_BITS_8) {
LOG_ERR("hardware only supports 8 data bits");
return -ENOTSUP;
}
switch (cfg->parity) {
case UART_CFG_PARITY_NONE:
break;
default:
LOG_ERR("unsupported parity mode %d", cfg->parity);
return -ENOTSUP;
}
switch (cfg->flow_ctrl) {
case UART_CFG_FLOW_CTRL_NONE:
ctrl |= 0;
break;
case UART_CFG_FLOW_CTRL_RTS_CTS:
ctrl |= NEORV32_UART_CTRL_HWFC_EN;
break;
default:
LOG_ERR("unsupported flow control mode %d", cfg->flow_ctrl);
return -ENOTSUP;
}
err = syscon_read_reg(config->syscon, NEORV32_SYSINFO_CLK, &clk);
if (err < 0) {
LOG_ERR("failed to determine clock rate (err %d)", err);
return -EIO;
}
if (cfg->baudrate == 0) {
LOG_ERR("invalid baud rate 0");
return -EINVAL;
}
/*
* Calculate clock prescaler and baud prescaler. Initial prscx = 0 is
* clock / 2.
*/
baudxx = clk / (2 * cfg->baudrate);
while (baudxx >= NEORV32_UART_CTRL_BAUD_MASK) {
if ((prscx == 2) || (prscx == 4)) {
baudxx >>= 3;
} else {
baudxx >>= 1;
}
prscx++;
}
if (prscx > NEORV32_UART_CTRL_PRSC_MASK) {
LOG_ERR("unsupported baud rate %d", cfg->baudrate);
return -ENOTSUP;
}
ctrl |= (baudxx - 1) << NEORV32_UART_CTRL_BAUD_POS;
ctrl |= prscx << NEORV32_UART_CTRL_PRSC_POS;
data->uart_cfg = *cfg;
neorv32_uart_write_ctrl(dev, ctrl);
return 0;
}
static int neorv32_uart_config_get(const struct device *dev, struct uart_config *cfg)
{
struct neorv32_uart_data *data = dev->data;
__ASSERT_NO_MSG(cfg != NULL);
*cfg = data->uart_cfg;
return 0;
}
#ifdef CONFIG_UART_INTERRUPT_DRIVEN
static int neorv32_uart_fifo_fill(const struct device *dev, const uint8_t *tx_data, int len)
{
uint32_t ctrl;
if (len <= 0) {
return 0;
}
__ASSERT_NO_MSG(tx_data != NULL);
ctrl = neorv32_uart_read_ctrl(dev);
if ((ctrl & NEORV32_UART_CTRL_TX_BUSY) == 0) {
neorv32_uart_write_data(dev, *tx_data);
return 1;
}
return 0;
}
static int neorv32_uart_fifo_read(const struct device *dev, uint8_t *rx_data, const int size)
{
struct neorv32_uart_data *data = dev->data;
int count = 0;
if (size <= 0) {
return 0;
}
__ASSERT_NO_MSG(rx_data != NULL);
while ((data->last_data & NEORV32_UART_CTRL_RX_NEMPTY) != 0) {
rx_data[count++] = data->last_data & BIT_MASK(8);
data->last_data &= ~(NEORV32_UART_CTRL_RX_NEMPTY);
if (count >= size) {
break;
}
(void)neorv32_uart_read_data(dev);
}
return count;
}
static void neorv32_uart_tx_soft_isr(struct k_timer *timer)
{
const struct device *dev = k_timer_user_data_get(timer);
struct neorv32_uart_data *data = dev->data;
uart_irq_callback_user_data_t callback = data->callback;
if (callback) {
callback(dev, data->callback_data);
}
}
static void neorv32_uart_irq_tx_enable(const struct device *dev)
{
const struct neorv32_uart_config *config = dev->config;
struct neorv32_uart_data *data = dev->data;
uint32_t ctrl;
irq_enable(config->tx_irq);
ctrl = neorv32_uart_read_ctrl(dev);
if ((ctrl & NEORV32_UART_CTRL_TX_BUSY) == 0) {
/*
* TX done event already generated an edge interrupt. Generate a
* soft interrupt and have it call the callback function in
* timer isr context.
*/
k_timer_start(&data->timer, K_NO_WAIT, K_NO_WAIT);
}
}
static void neorv32_uart_irq_tx_disable(const struct device *dev)
{
const struct neorv32_uart_config *config = dev->config;
irq_disable(config->tx_irq);
}
static int neorv32_uart_irq_tx_ready(const struct device *dev)
{
const struct neorv32_uart_config *config = dev->config;
uint32_t ctrl;
if (!irq_is_enabled(config->tx_irq)) {
return 0;
}
ctrl = neorv32_uart_read_ctrl(dev);
return (ctrl & NEORV32_UART_CTRL_TX_BUSY) == 0;
}
static void neorv32_uart_irq_rx_enable(const struct device *dev)
{
const struct neorv32_uart_config *config = dev->config;
irq_enable(config->rx_irq);
}
static void neorv32_uart_irq_rx_disable(const struct device *dev)
{
const struct neorv32_uart_config *config = dev->config;
irq_disable(config->rx_irq);
}
static int neorv32_uart_irq_tx_complete(const struct device *dev)
{
uint32_t ctrl;
ctrl = neorv32_uart_read_ctrl(dev);
return (ctrl & NEORV32_UART_CTRL_TX_BUSY) == 0;
}
static int neorv32_uart_irq_rx_ready(const struct device *dev)
{
const struct neorv32_uart_config *config = dev->config;
struct neorv32_uart_data *data = dev->data;
if (!irq_is_enabled(config->rx_irq)) {
return 0;
}
return (data->last_data & NEORV32_UART_CTRL_RX_NEMPTY) != 0;
}
static int neorv32_uart_irq_is_pending(const struct device *dev)
{
return (neorv32_uart_irq_tx_ready(dev) ||
neorv32_uart_irq_rx_ready(dev));
}
static int neorv32_uart_irq_update(const struct device *dev)
{
const struct neorv32_uart_config *config = dev->config;
if (irq_is_enabled(config->rx_irq)) {
/* Cache data for use by rx_ready() and fifo_read() */
(void)neorv32_uart_read_data(dev);
}
return 1;
}
static void neorv32_uart_irq_callback_set(const struct device *dev,
uart_irq_callback_user_data_t cb, void *user_data)
{
struct neorv32_uart_data *data = dev->data;
data->callback = cb;
data->callback_data = user_data;
}
static void neorv32_uart_isr(const struct device *dev)
{
struct neorv32_uart_data *data = dev->data;
uart_irq_callback_user_data_t callback = data->callback;
if (callback) {
callback(dev, data->callback_data);
}
}
#endif /* CONFIG_UART_INTERRUPT_DRIVEN */
static int neorv32_uart_init(const struct device *dev)
{
const struct neorv32_uart_config *config = dev->config;
struct neorv32_uart_data *data = dev->data;
uint32_t features;
int err;
if (!device_is_ready(config->syscon)) {
LOG_ERR("syscon device not ready");
return -EINVAL;
}
err = syscon_read_reg(config->syscon, NEORV32_SYSINFO_FEATURES, &features);
if (err < 0) {
LOG_ERR("failed to determine implemented features (err %d)", err);
return -EIO;
}
if ((features & config->feature_mask) == 0) {
LOG_ERR("neorv32 uart instance not supported");
return -ENODEV;
}
#ifdef CONFIG_UART_INTERRUPT_DRIVEN
k_timer_init(&data->timer, &neorv32_uart_tx_soft_isr, NULL);
k_timer_user_data_set(&data->timer, (void *)dev);
config->irq_config_func(dev);
#endif /* CONFIG_UART_INTERRUPT_DRIVEN */
return neorv32_uart_configure(dev, &data->uart_cfg);
}
#ifdef CONFIG_PM_DEVICE
static int neorv32_uart_pm_action(const struct device *dev,
enum pm_device_action action)
{
uint32_t ctrl = neorv32_uart_read_ctrl(dev);
switch (action) {
case PM_DEVICE_ACTION_SUSPEND:
ctrl &= ~(NEORV32_UART_CTRL_EN);
break;
case PM_DEVICE_ACTION_RESUME:
ctrl |= NEORV32_UART_CTRL_EN;
break;
default:
return -ENOTSUP;
}
neorv32_uart_write_ctrl(dev, ctrl);
return 0;
}
#endif /* CONFIG_PM_DEVICE */
static const struct uart_driver_api neorv32_uart_driver_api = {
.poll_in = neorv32_uart_poll_in,
.poll_out = neorv32_uart_poll_out,
#ifdef CONFIG_UART_USE_RUNTIME_CONFIGURE
.configure = neorv32_uart_configure,
.config_get = neorv32_uart_config_get,
#endif /* CONFIG_UART_USE_RUNTIME_CONFIGURE */
#ifdef CONFIG_UART_INTERRUPT_DRIVEN
.fifo_fill = neorv32_uart_fifo_fill,
.fifo_read = neorv32_uart_fifo_read,
.irq_tx_enable = neorv32_uart_irq_tx_enable,
.irq_tx_disable = neorv32_uart_irq_tx_disable,
.irq_tx_ready = neorv32_uart_irq_tx_ready,
.irq_rx_enable = neorv32_uart_irq_rx_enable,
.irq_rx_disable = neorv32_uart_irq_rx_disable,
.irq_tx_complete = neorv32_uart_irq_tx_complete,
.irq_rx_ready = neorv32_uart_irq_rx_ready,
.irq_is_pending = neorv32_uart_irq_is_pending,
.irq_update = neorv32_uart_irq_update,
.irq_callback_set = neorv32_uart_irq_callback_set,
#endif /* CONFIG_UART_INTERRUPT_DRIVEN */
};
#ifdef CONFIG_UART_INTERRUPT_DRIVEN
#define NEORV32_UART_CONFIG_FUNC(node_id, n) \
static void neorv32_uart_config_func_##n(const struct device *dev) \
{ \
IRQ_CONNECT(DT_IRQ_BY_NAME(node_id, tx, irq), \
DT_IRQ_BY_NAME(node_id, tx, priority), \
neorv32_uart_isr, \
DEVICE_DT_GET(node_id), 0); \
\
IRQ_CONNECT(DT_IRQ_BY_NAME(node_id, rx, irq), \
DT_IRQ_BY_NAME(node_id, rx, priority), \
neorv32_uart_isr, \
DEVICE_DT_GET(node_id), 0); \
}
#define NEORV32_UART_CONFIG_INIT(node_id, n) \
.irq_config_func = neorv32_uart_config_func_##n, \
.tx_irq = DT_IRQ_BY_NAME(node_id, tx, irq), \
.rx_irq = DT_IRQ_BY_NAME(node_id, rx, irq),
#else
#define NEORV32_UART_CONFIG_FUNC(node_id, n)
#define NEORV32_UART_CONFIG_INIT(node_id, n)
#endif /* CONFIG_UART_INTERRUPT_DRIVEN */
#define NEORV32_UART_INIT(node_id, n) \
NEORV32_UART_CONFIG_FUNC(node_id, n) \
\
static struct neorv32_uart_data neorv32_uart_##n##_data = { \
.uart_cfg = { \
.baudrate = DT_PROP(node_id, current_speed), \
.parity = DT_ENUM_IDX_OR(node_id, parity, \
UART_CFG_PARITY_NONE), \
.stop_bits = UART_CFG_STOP_BITS_1, \
.data_bits = UART_CFG_DATA_BITS_8, \
.flow_ctrl = DT_PROP(node_id, hw_flow_control) ? \
UART_CFG_FLOW_CTRL_RTS_CTS : \
UART_CFG_FLOW_CTRL_NONE, \
}, \
}; \
\
static const struct neorv32_uart_config neorv32_uart_##n##_config = { \
.syscon = DEVICE_DT_GET(DT_PHANDLE(node_id, syscon)), \
.feature_mask = NEORV32_SYSINFO_FEATURES_IO_UART##n, \
.base = DT_REG_ADDR(node_id), \
NEORV32_UART_CONFIG_INIT(node_id, n) \
}; \
\
PM_DEVICE_DT_DEFINE(node_id, neorv32_uart_pm_action); \
\
DEVICE_DT_DEFINE(node_id, &neorv32_uart_init, \
PM_DEVICE_DT_GET(node_id), \
&neorv32_uart_##n##_data, \
&neorv32_uart_##n##_config, \
PRE_KERNEL_1, \
CONFIG_SERIAL_INIT_PRIORITY, \
&neorv32_uart_driver_api)
#if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(uart0), DT_DRV_COMPAT, okay)
NEORV32_UART_INIT(DT_NODELABEL(uart0), 0);
#endif
#if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(uart1), DT_DRV_COMPAT, okay)
NEORV32_UART_INIT(DT_NODELABEL(uart1), 1);
#endif
``` | /content/code_sandbox/drivers/serial/uart_neorv32.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 4,073 |
```c
/*
*
*/
#include <zephyr/drivers/uart.h>
#include <zephyr/internal/syscall_handler.h>
#define UART_SIMPLE(op_) \
static inline int z_vrfy_uart_##op_(const struct device *dev) \
{ \
K_OOPS(K_SYSCALL_DRIVER_UART(dev, op_)); \
return z_impl_uart_ ## op_(dev); \
}
#define UART_SIMPLE_VOID(op_) \
static inline void z_vrfy_uart_##op_(const struct device *dev) \
{ \
K_OOPS(K_SYSCALL_DRIVER_UART(dev, op_)); \
z_impl_uart_ ## op_(dev); \
}
UART_SIMPLE(err_check)
#include <zephyr/syscalls/uart_err_check_mrsh.c>
static inline int z_vrfy_uart_poll_in(const struct device *dev,
unsigned char *p_char)
{
K_OOPS(K_SYSCALL_DRIVER_UART(dev, poll_in));
K_OOPS(K_SYSCALL_MEMORY_WRITE(p_char, sizeof(unsigned char)));
return z_impl_uart_poll_in(dev, p_char);
}
#include <zephyr/syscalls/uart_poll_in_mrsh.c>
static inline int z_vrfy_uart_poll_in_u16(const struct device *dev,
uint16_t *p_u16)
{
K_OOPS(K_SYSCALL_DRIVER_UART(dev, poll_in));
K_OOPS(K_SYSCALL_MEMORY_WRITE(p_u16, sizeof(uint16_t)));
return z_impl_uart_poll_in_u16(dev, p_u16);
}
#include <zephyr/syscalls/uart_poll_in_u16_mrsh.c>
static inline void z_vrfy_uart_poll_out(const struct device *dev,
unsigned char out_char)
{
K_OOPS(K_SYSCALL_DRIVER_UART(dev, poll_out));
z_impl_uart_poll_out((const struct device *)dev, out_char);
}
#include <zephyr/syscalls/uart_poll_out_mrsh.c>
static inline void z_vrfy_uart_poll_out_u16(const struct device *dev,
uint16_t out_u16)
{
K_OOPS(K_SYSCALL_DRIVER_UART(dev, poll_out));
z_impl_uart_poll_out_u16((const struct device *)dev, out_u16);
}
#include <zephyr/syscalls/uart_poll_out_u16_mrsh.c>
#ifdef CONFIG_UART_USE_RUNTIME_CONFIGURE
static inline int z_vrfy_uart_config_get(const struct device *dev,
struct uart_config *cfg)
{
K_OOPS(K_SYSCALL_DRIVER_UART(dev, config_get));
K_OOPS(K_SYSCALL_MEMORY_WRITE(cfg, sizeof(struct uart_config)));
return z_impl_uart_config_get(dev, cfg);
}
#include <zephyr/syscalls/uart_config_get_mrsh.c>
static inline int z_vrfy_uart_configure(const struct device *dev,
const struct uart_config *cfg)
{
K_OOPS(K_SYSCALL_DRIVER_UART(dev, config_get));
K_OOPS(K_SYSCALL_MEMORY_READ(cfg, sizeof(struct uart_config)));
return z_impl_uart_configure(dev, cfg);
}
#include <zephyr/syscalls/uart_configure_mrsh.c>
#endif
#ifdef CONFIG_UART_ASYNC_API
/* callback_set() excluded as we don't allow ISR callback installation from
* user mode
*
* rx_buf_rsp() excluded as it's designed to be called from ISR callbacks
*/
static inline int z_vrfy_uart_tx(const struct device *dev, const uint8_t *buf,
size_t len, int32_t timeout)
{
K_OOPS(K_SYSCALL_DRIVER_UART(dev, tx));
K_OOPS(K_SYSCALL_MEMORY_READ(buf, len));
return z_impl_uart_tx(dev, buf, len, timeout);
}
#include <zephyr/syscalls/uart_tx_mrsh.c>
#ifdef CONFIG_UART_WIDE_DATA
static inline int z_vrfy_uart_tx_u16(const struct device *dev,
const uint16_t *buf,
size_t len, int32_t timeout)
{
K_OOPS(K_SYSCALL_DRIVER_UART(dev, tx));
K_OOPS(K_SYSCALL_MEMORY_ARRAY_READ(buf, len, sizeof(uint16_t)));
return z_impl_uart_tx_u16(dev, buf, len, timeout);
}
#include <zephyr/syscalls/uart_tx_u16_mrsh.c>
#endif
UART_SIMPLE(tx_abort);
#include <zephyr/syscalls/uart_tx_abort_mrsh.c>
static inline int z_vrfy_uart_rx_enable(const struct device *dev,
uint8_t *buf,
size_t len, int32_t timeout)
{
K_OOPS(K_SYSCALL_DRIVER_UART(dev, rx_enable));
K_OOPS(K_SYSCALL_MEMORY_WRITE(buf, len));
return z_impl_uart_rx_enable(dev, buf, len, timeout);
}
#include <zephyr/syscalls/uart_rx_enable_mrsh.c>
#ifdef CONFIG_UART_WIDE_DATA
static inline int z_vrfy_uart_rx_enable_u16(const struct device *dev,
uint16_t *buf,
size_t len, int32_t timeout)
{
K_OOPS(K_SYSCALL_DRIVER_UART(dev, rx_enable));
K_OOPS(K_SYSCALL_MEMORY_ARRAY_WRITE(buf, len, sizeof(uint16_t)));
return z_impl_uart_rx_enable_u16(dev, buf, len, timeout);
}
#include <zephyr/syscalls/uart_rx_enable_u16_mrsh.c>
#endif
UART_SIMPLE(rx_disable);
#include <zephyr/syscalls/uart_rx_disable_mrsh.c>
#endif /* CONFIG_UART_ASYNC_API */
#ifdef CONFIG_UART_INTERRUPT_DRIVEN
UART_SIMPLE_VOID(irq_tx_enable)
UART_SIMPLE_VOID(irq_tx_disable)
UART_SIMPLE_VOID(irq_rx_enable)
UART_SIMPLE_VOID(irq_rx_disable)
UART_SIMPLE_VOID(irq_err_enable)
UART_SIMPLE_VOID(irq_err_disable)
UART_SIMPLE(irq_is_pending)
UART_SIMPLE(irq_update)
#include <zephyr/syscalls/uart_irq_tx_enable_mrsh.c>
#include <zephyr/syscalls/uart_irq_tx_disable_mrsh.c>
#include <zephyr/syscalls/uart_irq_rx_enable_mrsh.c>
#include <zephyr/syscalls/uart_irq_rx_disable_mrsh.c>
#include <zephyr/syscalls/uart_irq_err_enable_mrsh.c>
#include <zephyr/syscalls/uart_irq_err_disable_mrsh.c>
#include <zephyr/syscalls/uart_irq_is_pending_mrsh.c>
#include <zephyr/syscalls/uart_irq_update_mrsh.c>
#endif /* CONFIG_UART_INTERRUPT_DRIVEN */
#ifdef CONFIG_UART_LINE_CTRL
static inline int z_vrfy_uart_line_ctrl_set(const struct device *dev,
uint32_t ctrl, uint32_t val)
{
K_OOPS(K_SYSCALL_DRIVER_UART(dev, line_ctrl_set));
return z_impl_uart_line_ctrl_set((const struct device *)dev, ctrl,
val);
}
#include <zephyr/syscalls/uart_line_ctrl_set_mrsh.c>
static inline int z_vrfy_uart_line_ctrl_get(const struct device *dev,
uint32_t ctrl, uint32_t *val)
{
K_OOPS(K_SYSCALL_DRIVER_UART(dev, line_ctrl_get));
K_OOPS(K_SYSCALL_MEMORY_WRITE(val, sizeof(uint32_t)));
return z_impl_uart_line_ctrl_get((const struct device *)dev, ctrl,
(uint32_t *)val);
}
#include <zephyr/syscalls/uart_line_ctrl_get_mrsh.c>
#endif /* CONFIG_UART_LINE_CTRL */
#ifdef CONFIG_UART_DRV_CMD
static inline int z_vrfy_uart_drv_cmd(const struct device *dev, uint32_t cmd,
uint32_t p)
{
K_OOPS(K_SYSCALL_DRIVER_UART(dev, drv_cmd));
return z_impl_uart_drv_cmd((const struct device *)dev, cmd, p);
}
#include <zephyr/syscalls/uart_drv_cmd_mrsh.c>
#endif /* CONFIG_UART_DRV_CMD */
``` | /content/code_sandbox/drivers/serial/uart_handlers.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 1,600 |
```unknown
# iMX7 M4 UART
config UART_IMX
bool "NXP i.MX7 family processor UART driver"
default y
depends on DT_HAS_NXP_IMX_UART_ENABLED
select SERIAL_HAS_DRIVER
select SERIAL_SUPPORT_INTERRUPT
help
This option enables the UART driver for NXP i.MX7
family processors.
``` | /content/code_sandbox/drivers/serial/Kconfig.imx | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 73 |
```unknown
config UART_APBUART
bool "ABPUART serial driver"
default y
depends on DT_HAS_GAISLER_APBUART_ENABLED
select SERIAL_HAS_DRIVER
select SERIAL_SUPPORT_INTERRUPT
help
This option enables the APBUART driver for LEON processors.
``` | /content/code_sandbox/drivers/serial/Kconfig.apbuart | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 59 |
```unknown
config UART_ALTERA_JTAG
bool "Nios II/NiosV JTAG UART driver"
default y
depends on DT_HAS_ALTR_JTAG_UART_ENABLED
select SERIAL_HAS_DRIVER
help
Enable the Altera JTAG UART driver, built in to many Nios II/NiosV CPU
designs.
config UART_ALTERA_JTAG_HAL
bool "JTAG UART driver using Altera HAL API"
depends on UART_ALTERA_JTAG && NIOS2
help
This is not available for NiosV CPU, as only the HAL for Nios II CPU is ported.
Enabling this will disable poll_in and interrupt driven api.
config UART_ALTERA_JTAG_SUPPORT_INTERRUPT
bool
depends on UART_ALTERA_JTAG
default y if !UART_ALTERA_JTAG_HAL
select SERIAL_SUPPORT_INTERRUPT
help
This is a helper config. Altera JTAG UART driver will support interrupt,
if UART_ALTERA_JTAG_HAL is disabled.
``` | /content/code_sandbox/drivers/serial/Kconfig.altera_jtag | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 214 |
```unknown
menuconfig UART_NS16550
bool "NS16550 serial driver"
default y
depends on DT_HAS_NS16550_ENABLED
select SERIAL_HAS_DRIVER
select SERIAL_SUPPORT_INTERRUPT
help
This option enables the NS16550 serial driver.
This driver can be used for the serial hardware
available on x86 boards.
if UART_NS16550
config UART_NS16550_LINE_CTRL
bool "Serial Line Control for Apps"
depends on UART_LINE_CTRL
help
This enables the API for apps to control the serial line,
such as CTS and RTS.
Says n if not sure.
config UART_NS16550_DRV_CMD
bool "Driver Commands"
depends on UART_DRV_CMD
help
This enables the API for apps to send commands to driver.
Says n if not sure.
config UART_NS16550_INTEL_LPSS_DMA
bool "INTEL LPSS support for NS16550"
select SERIAL_SUPPORT_ASYNC
select DMA if UART_ASYNC_API
help
This enables the usage of INTEL LPSS internal DMA for Async operations.
choice UART_NS16550_VARIANT
prompt "UART variant"
default UART_NS16550_VARIANT_NS16550
help
Select UART device variant
config UART_NS16550_VARIANT_NS16550
bool "UART 16550 (16-bytes FIFO)"
help
This enables support for 16-bytes FIFO if UART controller is 16550.
config UART_NS16550_VARIANT_NS16750
bool "UART 16750 (64-bytes FIFO and auto flow control)"
help
This enables support for 64-bytes FIFO and automatic hardware
flow control if UART controller is 16750.
config UART_NS16550_VARIANT_NS16950
bool "UART 16950 (128-bytes FIFO and auto flow control)"
help
This enables support for 128-bytes FIFO and automatic hardware flow control.
endchoice
config UART_NS16550_ACCESS_WORD_ONLY
bool "NS16550 only allows word access"
help
In some case, e.g. ARC HS Development kit, the peripheral space of ns
16550 (DesignWare UART) only allows word access, byte access will raise
exception.
config UART_NS16550_TI_K3
bool "Add support for NS16550 variant specific to TI K3 SoCs"
help
Enabling this configuration allows the users to use the UART port in
Texas Instruments K3 SoCs by enabling a vendor specific extended register
set.
config UART_NS16550_ITE_HIGH_SPEED_BAUDRATE
bool "IT8XXX2 specific baud rate configuration"
help
Enable IT8XXX2 specific baud rate configuration.
This applies to high-speed baud rate configuration.
menu "NS16550 Workarounds"
config UART_NS16550_WA_ISR_REENABLE_INTERRUPT
bool "Re-enable interrupts by toggling IER at end of ISR"
depends on UART_INTERRUPT_DRIVEN
help
In some configurations (e.g. edge interrupt triggers),
an interruptible event occurs during ISR and the host interrupt
controller does not see the new event due to IIR is constantly
asserting interrupts. For example, the callback handles RX and
then TX. If another character comes in before end of TX processing
(TX interrupt still asserts while raising RX interrupt), the host
interrupt controller may not see this new event. So if needed,
the IER is being toggled to re-assert interrupts at the end of ISR
to nudge the host interrupt controller to fire the ISR again.
endmenu
endif # UART_NS16550
``` | /content/code_sandbox/drivers/serial/Kconfig.ns16550 | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 758 |
```unknown
# Serial driver configuration options
menuconfig SERIAL
bool "Serial drivers"
help
Enable options for serial drivers.
if SERIAL
comment "Capabilities"
config SERIAL_HAS_DRIVER
bool
help
This is an option to be enabled by individual serial driver
to signal that there is a serial driver. This is being used
by other drivers which are dependent on serial.
config SERIAL_SUPPORT_ASYNC
bool
help
This is an option to be enabled by individual serial driver
to signal that the driver and hardware supports async operation.
config SERIAL_SUPPORT_INTERRUPT
bool
help
This is an option to be enabled by individual serial driver
to signal that the driver and hardware supports interrupts.
config SERIAL_INIT_PRIORITY
int "Serial init priority"
default KERNEL_INIT_PRIORITY_DEVICE
help
Serial driver device initialization priority.
module = UART
module-str = uart
source "subsys/logging/Kconfig.template.log_config"
config SERIAL_SUPPORT_WIDE_DATA
bool
help
This is an option to be enabled by individual serial driver
to signal that the driver and hardware support data longer
than 8-bit.
config UART_USE_RUNTIME_CONFIGURE
bool "Runtime configuration for UART controllers"
default y
help
Enable runtime configuration of UART controllers.
This allows applications to call uart_configure() to
configure the UART controllers at runtime, and calling
uart_config_get() to retrieve configuration. If this is
disabled, UART controllers rely on UART driver's
initialization function to properly configure
the controller.
Say y if unsure. Disable this to reduce footprint for
applications that do not require runtime UART configuration.
config UART_ASYNC_API
bool "Asynchronous UART API"
depends on SERIAL_SUPPORT_ASYNC
help
This option enables asynchronous UART API.
config UART_INTERRUPT_DRIVEN
bool "UART Interrupt support"
depends on SERIAL_SUPPORT_INTERRUPT
help
This option enables interrupt support for UART allowing console
input and other UART based drivers.
config UART_EXCLUSIVE_API_CALLBACKS
bool "Use exclusive callbacks for multiple APIs"
depends on UART_ASYNC_API && UART_INTERRUPT_DRIVEN
default y
help
When multiple set of APIs support callbacks, enabling this
option will result in only the callbacks of one set of API
being active at a time. Setting a new callback to one set of
API will remove callbacks to other set of APIs. For example,
calling uart_callback_set() would disable the callback
previously set via uart_irq_callback_set().
Says yes unless you are absolutely sure you know what you are
doing and promise not to file bug when things do not work out.
config UART_LINE_CTRL
bool "Serial Line Control API"
help
This enables the API for apps to control the serial line,
such as baud rate, CTS and RTS.
Implementation is up to individual driver.
Says no if not sure.
config UART_DRV_CMD
bool "Driver commands API"
help
This enables the API to send extra commands to drivers.
This allows drivers to expose hardware specific functions.
Says no if not sure.
config UART_WIDE_DATA
bool "API to support data longer than 8-bit"
help
This enables the API to process data longer than 8-bit.
This is up to the driver to implement the necessary functions
to properly support this.
config UART_PIPE
bool "Pipe UART driver"
select UART_INTERRUPT_DRIVEN
help
Enable pipe UART driver. This driver allows application to communicate
over UART with custom defined protocol. Driver doesn't inspect received
data (as contrary to console UART driver) and all aspects of received
protocol data are handled by application provided callback.
config UART_ASYNC_RX_HELPER
bool "Helper for UART asynchronous reception"
help
Module implements handling of reception of variable length data using
Asynchronous UART API. It can be used in cases where received data processing
is delayed. Module implements zero-copy approach with multiple reception
buffers.
config UART_ASYNC_TO_INT_DRIVEN_API
bool
select UART_ASYNC_RX_HELPER
help
Asynchronous to Interrupt driven adaptation layer. When enabled device
which implements only asynchronous API can be used with interrupt driven
API implemented by the generic adaptation layer.
config UART_ASYNC_TO_INT_DRIVEN_RX_TIMEOUT
int "Receiver timeout (in bauds)"
depends on UART_ASYNC_TO_INT_DRIVEN_API
default 100
help
Receiver inactivity timeout. It is used to calculate timeout in microseconds.
comment "Serial Drivers"
rsource "Kconfig.b91"
rsource "Kconfig.ns16550"
rsource "Kconfig.mcux"
rsource "Kconfig.mcux_flexcomm"
rsource "Kconfig.mcux_iuart"
rsource "Kconfig.mcux_lpsci"
rsource "Kconfig.mcux_lpuart"
rsource "Kconfig.miv"
rsource "Kconfig.imx"
rsource "Kconfig.it8xxx2"
rsource "Kconfig.stellaris"
rsource "Kconfig.native_posix"
rsource "Kconfig.usart_sam"
rsource "Kconfig.uart_sam"
rsource "Kconfig.stm32"
rsource "Kconfig.nrfx"
rsource "Kconfig.altera_jtag"
rsource "Kconfig.cc13xx_cc26xx"
rsource "Kconfig.cc32xx"
rsource "Kconfig.cmsdk_apb"
rsource "Kconfig.sifive"
rsource "Kconfig.esp32"
rsource "Kconfig.gecko"
rsource "Kconfig.leuart_gecko"
rsource "Kconfig.msp432p4xx"
rsource "Kconfig.numicro"
rsource "Kconfig.sam0"
rsource "Kconfig.psoc6"
rsource "Kconfig.pl011"
rsource "Kconfig.ql_usbserialport_s3b"
rsource "Kconfig.rv32m1_lpuart"
rsource "Kconfig.rpi_pico"
rsource "Kconfig.litex"
rsource "Kconfig.rtt"
rsource "Kconfig.bt"
rsource "Kconfig.xlnx"
rsource "Kconfig.xmc4xxx"
rsource "Kconfig.lpc11u6x"
rsource "Kconfig.npcx"
rsource "Kconfig.apbuart"
rsource "Kconfig.rcar"
rsource "Kconfig.xec"
rsource "Kconfig.gd32"
rsource "Kconfig.test"
rsource "Kconfig.neorv32"
rsource "Kconfig.xen"
rsource "Kconfig.ifx_cat1"
rsource "Kconfig.smartbond"
rsource "Kconfig.nxp_s32"
rsource "Kconfig.cdns"
rsource "Kconfig.opentitan"
rsource "Kconfig.altera"
rsource "Kconfig.hostlink"
rsource "Kconfig.emul"
rsource "Kconfig.native_tty"
rsource "Kconfig.numaker"
rsource "Kconfig.efinix_sapphire"
rsource "Kconfig.sedi"
rsource "Kconfig.max32"
rsource "Kconfig.bcm2711"
rsource "Kconfig.intel_lw"
rsource "Kconfig.renesas_ra"
rsource "Kconfig.ene"
rsource "Kconfig.rzt2m"
rsource "Kconfig.renesas_ra8"
endif # SERIAL
``` | /content/code_sandbox/drivers/serial/Kconfig | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 1,549 |
```unknown
# MCUXpresso SDK USART
config UART_MCUX_FLEXCOMM
bool "MCUX FLEXCOMM UART driver"
default y
depends on DT_HAS_NXP_LPC_USART_ENABLED
select SERIAL_HAS_DRIVER
select SERIAL_SUPPORT_INTERRUPT
select SERIAL_SUPPORT_ASYNC if \
DT_HAS_NXP_LPC_DMA_ENABLED
select DMA if UART_ASYNC_API
select PINCTRL
help
Enable the MCUX USART driver.
config UART_MCUX_FLEXCOMM_ISR_SUPPORT
bool
depends on UART_MCUX_FLEXCOMM
default y if UART_INTERRUPT_DRIVEN || UART_ASYNC_API
help
Enable UART interrupt service routine.
``` | /content/code_sandbox/drivers/serial/Kconfig.mcux_flexcomm | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 132 |
```unknown
config UART_CC32XX
bool "CC32XX UART driver"
default y
depends on DT_HAS_TI_CC32XX_UART_ENABLED
select SERIAL_HAS_DRIVER
select SERIAL_SUPPORT_INTERRUPT
select PINCTRL
help
This option enables the CC32XX UART driver, for UART_0.
``` | /content/code_sandbox/drivers/serial/Kconfig.cc32xx | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 63 |
```unknown
config UART_EFINIX_SAPPIHIRE
bool "EFINIX_SAPPIHIRE serial driver"
default y
depends on DT_HAS_EFINIX_SAPPHIRE_UART0_ENABLED
select SERIAL_HAS_DRIVER
help
This option enables Efinix sapphire serial driver.
``` | /content/code_sandbox/drivers/serial/Kconfig.efinix_sapphire | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 64 |
```unknown
# MCUXpresso SDK LPUART
config UART_MCUX_LPUART
bool "MCUX LPUART driver"
default y
depends on DT_HAS_NXP_KINETIS_LPUART_ENABLED
depends on CLOCK_CONTROL
select SERIAL_HAS_DRIVER
select SERIAL_SUPPORT_INTERRUPT
select SERIAL_SUPPORT_ASYNC
select DMA if UART_ASYNC_API
select PINCTRL
help
Enable the MCUX LPUART driver.
config UART_MCUX_LPUART_ISR_SUPPORT
bool
depends on UART_MCUX_LPUART
default y if UART_INTERRUPT_DRIVEN || PM || UART_ASYNC_API
help
Enable UART interrupt service routine.
``` | /content/code_sandbox/drivers/serial/Kconfig.mcux_lpuart | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 134 |
```unknown
config UART_NATIVE_TTY
bool "UART driver for interacting with host serial ports"
default y
depends on DT_HAS_ZEPHYR_NATIVE_TTY_UART_ENABLED
select SERIAL_HAS_DRIVER
select SERIAL_SUPPORT_INTERRUPT
``` | /content/code_sandbox/drivers/serial/Kconfig.native_tty | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 46 |
```unknown
# ARM CMSDK APB SoC UART configuration options
config UART_CMSDK_APB
bool "ARM CMSDK APB UART driver"
default y
depends on DT_HAS_ARM_CMSDK_UART_ENABLED
select SERIAL_HAS_DRIVER
select SERIAL_SUPPORT_INTERRUPT
help
This option enables the UART driver for ARM CMSDK APB UART.
``` | /content/code_sandbox/drivers/serial/Kconfig.cmsdk_apb | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 72 |
```c
/*
*
*/
/*
* This is not a real serial driver. It is used to instantiate struct
* devices for the "vnd,serial" devicetree compatible used in test code.
*/
#include <stdbool.h>
#include <zephyr/sys/__assert.h>
#include <zephyr/device.h>
#include <zephyr/drivers/uart.h>
#include <zephyr/drivers/uart/serial_test.h>
#include <zephyr/kernel.h>
#include <zephyr/logging/log.h>
#include <zephyr/sys/ring_buffer.h>
LOG_MODULE_REGISTER(mock_serial, CONFIG_LOG_DEFAULT_LEVEL);
#define DT_DRV_COMPAT vnd_serial
struct serial_vnd_data {
#ifdef CONFIG_RING_BUFFER
struct ring_buf *written;
struct ring_buf *read_queue;
#endif
serial_vnd_write_cb_t callback;
void *callback_data;
#ifdef CONFIG_UART_INTERRUPT_DRIVEN
uart_irq_callback_user_data_t irq_isr;
bool irq_rx_enabled;
bool irq_tx_enabled;
#endif
#ifdef CONFIG_UART_ASYNC_API
uart_callback_t async_cb;
void *async_cb_user_data;
uint8_t *read_buf;
size_t read_size;
size_t read_position;
#endif
};
#ifdef CONFIG_UART_INTERRUPT_DRIVEN
static bool is_irq_rx_pending(const struct device *dev)
{
struct serial_vnd_data *data = dev->data;
return !ring_buf_is_empty(data->read_queue);
}
static bool is_irq_tx_pending(const struct device *dev)
{
struct serial_vnd_data *data = dev->data;
return ring_buf_space_get(data->written) != 0;
}
static void irq_process(const struct device *dev)
{
struct serial_vnd_data *data = dev->data;
for (;;) {
bool rx_rdy = is_irq_rx_pending(dev);
bool tx_rdy = is_irq_tx_pending(dev);
bool rx_int = rx_rdy && data->irq_rx_enabled;
bool tx_int = tx_rdy && data->irq_tx_enabled;
LOG_DBG("rx_rdy %d tx_rdy %d", rx_rdy, tx_rdy);
LOG_DBG("rx_int %d tx_int %d", rx_int, tx_int);
if (!(rx_int || tx_int)) {
break;
}
LOG_DBG("isr");
if (!data->irq_isr) {
LOG_ERR("no isr registered");
break;
}
data->irq_isr(dev, NULL);
};
}
static void irq_rx_enable(const struct device *dev)
{
struct serial_vnd_data *data = dev->data;
data->irq_rx_enabled = true;
LOG_DBG("rx enabled");
irq_process(dev);
}
static void irq_rx_disable(const struct device *dev)
{
struct serial_vnd_data *data = dev->data;
data->irq_rx_enabled = false;
LOG_DBG("rx disabled");
}
static int irq_rx_ready(const struct device *dev)
{
struct serial_vnd_data *data = dev->data;
bool ready = !ring_buf_is_empty(data->read_queue);
LOG_DBG("rx ready: %d", ready);
return ready;
}
static void irq_tx_enable(const struct device *dev)
{
struct serial_vnd_data *data = dev->data;
LOG_DBG("tx enabled");
data->irq_tx_enabled = true;
irq_process(dev);
}
static void irq_tx_disable(const struct device *dev)
{
struct serial_vnd_data *data = dev->data;
data->irq_tx_enabled = false;
LOG_DBG("tx disabled");
}
static int irq_tx_ready(const struct device *dev)
{
struct serial_vnd_data *data = dev->data;
bool ready = (ring_buf_space_get(data->written) != 0);
LOG_DBG("tx ready: %d", ready);
return ready;
}
static void irq_callback_set(const struct device *dev, uart_irq_callback_user_data_t cb,
void *user_data)
{
struct serial_vnd_data *data = dev->data;
/* Not implemented. Ok because `user_data` is always NULL in the current
* implementation of core UART API.
*/
__ASSERT_NO_MSG(user_data == NULL);
#if defined(CONFIG_UART_EXCLUSIVE_API_CALLBACKS) && defined(CONFIG_UART_ASYNC_API)
if (data->read_buf) {
LOG_ERR("Setting callback to NULL while asynchronous API is in use.");
}
data->async_cb = NULL;
data->async_cb_user_data = NULL;
#endif
data->irq_isr = cb;
LOG_DBG("callback set");
}
static int fifo_fill(const struct device *dev, const uint8_t *tx_data, int size)
{
struct serial_vnd_data *data = dev->data;
uint32_t write_len = ring_buf_put(data->written, tx_data, size);
if (data->callback) {
data->callback(dev, data->callback_data);
}
return write_len;
}
static int fifo_read(const struct device *dev, uint8_t *rx_data, const int size)
{
struct serial_vnd_data *data = dev->data;
int read_len = ring_buf_get(data->read_queue, rx_data, size);
LOG_HEXDUMP_DBG(rx_data, read_len, "");
return read_len;
}
#endif /* CONFIG_UART_INTERRUPT_DRIVEN */
static int serial_vnd_poll_in(const struct device *dev, unsigned char *c)
{
#ifdef CONFIG_RING_BUFFER
struct serial_vnd_data *data = dev->data;
uint32_t bytes_read;
if (data == NULL || data->read_queue == NULL) {
return -ENOTSUP;
}
bytes_read = ring_buf_get(data->read_queue, c, 1);
if (bytes_read == 1) {
return 0;
}
return -1;
#else
return -ENOTSUP;
#endif
}
static void serial_vnd_poll_out(const struct device *dev, unsigned char c)
{
struct serial_vnd_data *data = dev->data;
#ifdef CONFIG_RING_BUFFER
if (data == NULL || data->written == NULL) {
return;
}
ring_buf_put(data->written, &c, 1);
#endif
if (data->callback) {
data->callback(dev, data->callback_data);
}
}
#ifdef CONFIG_UART_ASYNC_API
static void async_rx_run(const struct device *dev);
#endif
#ifdef CONFIG_RING_BUFFER
int serial_vnd_queue_in_data(const struct device *dev, const unsigned char *c, uint32_t size)
{
struct serial_vnd_data *data = dev->data;
int write_size;
if (data == NULL || data->read_queue == NULL) {
return -ENOTSUP;
}
write_size = ring_buf_put(data->read_queue, c, size);
LOG_DBG("size %u write_size %u", size, write_size);
LOG_HEXDUMP_DBG(c, write_size, "");
#ifdef CONFIG_UART_INTERRUPT_DRIVEN
if (write_size > 0) {
irq_process(dev);
}
#endif
#ifdef CONFIG_UART_ASYNC_API
async_rx_run(dev);
#endif
return write_size;
}
uint32_t serial_vnd_out_data_size_get(const struct device *dev)
{
struct serial_vnd_data *data = dev->data;
if (data == NULL || data->written == NULL) {
return -ENOTSUP;
}
return ring_buf_size_get(data->written);
}
uint32_t serial_vnd_read_out_data(const struct device *dev, unsigned char *out_data, uint32_t size)
{
struct serial_vnd_data *data = dev->data;
if (data == NULL || data->written == NULL) {
return -ENOTSUP;
}
return ring_buf_get(data->written, out_data, size);
}
uint32_t serial_vnd_peek_out_data(const struct device *dev, unsigned char *out_data, uint32_t size)
{
struct serial_vnd_data *data = dev->data;
if (data == NULL || data->written == NULL) {
return -ENOTSUP;
}
return ring_buf_peek(data->written, out_data, size);
}
#endif
void serial_vnd_set_callback(const struct device *dev, serial_vnd_write_cb_t callback,
void *user_data)
{
struct serial_vnd_data *data = dev->data;
if (data == NULL) {
return;
}
data->callback = callback;
data->callback_data = user_data;
}
static int serial_vnd_err_check(const struct device *dev)
{
return -ENOTSUP;
}
#ifdef CONFIG_UART_USE_RUNTIME_CONFIGURE
static int serial_vnd_configure(const struct device *dev, const struct uart_config *cfg)
{
return -ENOTSUP;
}
static int serial_vnd_config_get(const struct device *dev, struct uart_config *cfg)
{
return -ENOTSUP;
}
#endif /* CONFIG_UART_USE_RUNTIME_CONFIGURE */
#ifdef CONFIG_UART_ASYNC_API
static int serial_vnd_callback_set(const struct device *dev, uart_callback_t callback,
void *user_data)
{
struct serial_vnd_data *data = dev->data;
if (data == NULL) {
return -ENOTSUP;
}
#if defined(CONFIG_UART_EXCLUSIVE_API_CALLBACKS) && defined(CONFIG_UART_INTERRUPT_DRIVEN)
data->irq_isr = NULL;
#endif
if (callback == NULL && data->read_buf) {
LOG_ERR("Setting callback to NULL while asynchronous API is in use.");
}
data->async_cb = callback;
data->async_cb_user_data = user_data;
return 0;
}
static int serial_vnd_api_tx(const struct device *dev, const uint8_t *tx_data, size_t len,
int32_t timeout)
{
struct serial_vnd_data *data = dev->data;
struct uart_event evt;
uint32_t write_len;
if (data == NULL) {
return -ENOTSUP;
}
if (data->async_cb == NULL) {
return -EINVAL;
}
write_len = ring_buf_put(data->written, tx_data, len);
if (data->callback) {
data->callback(dev, data->callback_data);
}
__ASSERT(write_len == len, "Ring buffer full. Async wait not implemented.");
evt = (struct uart_event){
.type = UART_TX_DONE,
.data.tx.buf = tx_data,
.data.tx.len = len,
};
data->async_cb(dev, &evt, data->async_cb_user_data);
return 0;
}
static void async_rx_run(const struct device *dev)
{
struct serial_vnd_data *data = dev->data;
struct uart_event evt;
uint32_t read_len;
uint32_t read_remaining;
if (!data->read_buf) {
return;
}
__ASSERT_NO_MSG(data->async_cb);
read_remaining = data->read_size - data->read_position;
read_len = ring_buf_get(data->read_queue, &data->read_buf[data->read_position],
read_remaining);
if (read_len != 0) {
evt = (struct uart_event){
.type = UART_RX_RDY,
.data.rx.buf = data->read_buf,
.data.rx.len = read_len,
.data.rx.offset = data->read_position,
};
data->async_cb(dev, &evt, data->async_cb_user_data);
}
data->read_position += read_len;
if (data->read_position == data->read_size) {
data->read_buf = NULL;
evt = (struct uart_event){
.type = UART_RX_DISABLED,
};
data->async_cb(dev, &evt, data->async_cb_user_data);
}
}
static int serial_vnd_rx_enable(const struct device *dev, uint8_t *read_buf, size_t read_size,
int32_t timeout)
{
struct serial_vnd_data *data = dev->data;
LOG_WRN("read_size %zd", read_size);
if (data == NULL) {
return -ENOTSUP;
}
if (data->async_cb == NULL) {
return -EINVAL;
}
__ASSERT(timeout == SYS_FOREVER_MS, "Async timeout not implemented.");
data->read_buf = read_buf;
data->read_size = read_size;
data->read_position = 0;
async_rx_run(dev);
return 0;
}
#endif /* CONFIG_UART_ASYNC_API */
static const struct uart_driver_api serial_vnd_api = {
.poll_in = serial_vnd_poll_in,
.poll_out = serial_vnd_poll_out,
.err_check = serial_vnd_err_check,
#ifdef CONFIG_UART_USE_RUNTIME_CONFIGURE
.configure = serial_vnd_configure,
.config_get = serial_vnd_config_get,
#endif /* CONFIG_UART_USE_RUNTIME_CONFIGURE */
#ifdef CONFIG_UART_INTERRUPT_DRIVEN
.irq_callback_set = irq_callback_set,
.irq_rx_enable = irq_rx_enable,
.irq_rx_disable = irq_rx_disable,
.irq_rx_ready = irq_rx_ready,
.irq_tx_enable = irq_tx_enable,
.irq_tx_disable = irq_tx_disable,
.irq_tx_ready = irq_tx_ready,
.fifo_read = fifo_read,
.fifo_fill = fifo_fill,
#endif /* CONFIG_UART_INTERRUPT_DRIVEN */
#ifdef CONFIG_UART_ASYNC_API
.callback_set = serial_vnd_callback_set,
.tx = serial_vnd_api_tx,
.rx_enable = serial_vnd_rx_enable,
#endif /* CONFIG_UART_ASYNC_API */
};
#define VND_SERIAL_DATA_BUFFER(n) \
RING_BUF_DECLARE(written_data_##n, DT_INST_PROP(n, buffer_size)); \
RING_BUF_DECLARE(read_queue_##n, DT_INST_PROP(n, buffer_size)); \
static struct serial_vnd_data serial_vnd_data_##n = { \
.written = &written_data_##n, \
.read_queue = &read_queue_##n, \
};
#define VND_SERIAL_DATA(n) static struct serial_vnd_data serial_vnd_data_##n = {};
#define VND_SERIAL_INIT(n) \
COND_CODE_1(DT_INST_NODE_HAS_PROP(n, buffer_size), (VND_SERIAL_DATA_BUFFER(n)), \
(VND_SERIAL_DATA(n))) \
DEVICE_DT_INST_DEFINE(n, NULL, NULL, &serial_vnd_data_##n, NULL, POST_KERNEL, \
CONFIG_SERIAL_INIT_PRIORITY, &serial_vnd_api);
DT_INST_FOREACH_STATUS_OKAY(VND_SERIAL_INIT)
``` | /content/code_sandbox/drivers/serial/serial_test.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 2,992 |
```unknown
config UART_RA8_SCI_B
bool "Renesas RA SCI_B UART"
default y
depends on DT_HAS_RENESAS_RA8_UART_SCI_B_ENABLED
select SERIAL_HAS_DRIVER
select SERIAL_SUPPORT_INTERRUPT
select SERIAL_SUPPORT_ASYNC
select USE_RA_FSP_SCI_B_UART
select USE_RA_FSP_DTC if UART_ASYNC_API
help
Enable Renesas RA SCI_B UART Driver.
if UART_RA8_SCI_B && (UART_INTERRUPT_DRIVEN || UART_ASYNC_API)
config UART_RA_SCI_B_UART_FIFO_ENABLE
bool "RA SCI_B UART FIFO usage enable"
default y if UART_INTERRUPT_DRIVEN
default n if UART_ASYNC_API
help
Enable RA SCI_B FIFO
endif
``` | /content/code_sandbox/drivers/serial/Kconfig.renesas_ra8 | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 153 |
```unknown
#nRF UART(E) instance configuration
config UART_$(nrfx_uart_num)_INTERRUPT_DRIVEN
bool "Interrupt support on port $(nrfx_uart_num)"
depends on UART_INTERRUPT_DRIVEN
select UART_ASYNC_TO_INT_DRIVEN_API if !UART_NRFX_UARTE_LEGACY_SHIM
default y
help
This option enables UART interrupt support on port $(nrfx_uart_num).
config UART_$(nrfx_uart_num)_ASYNC
bool "Asynchronous API support on port $(nrfx_uart_num)"
depends on UART_ASYNC_API && !UART_$(nrfx_uart_num)_INTERRUPT_DRIVEN
default y
help
This option enables UART Asynchronous API support on port $(nrfx_uart_num).
config UART_$(nrfx_uart_num)_ENHANCED_POLL_OUT
bool "Efficient poll out on port $(nrfx_uart_num)"
depends on !SOC_SERIES_NRF54LX
default y
depends on HAS_HW_NRF_UARTE$(nrfx_uart_num)
depends on HAS_HW_NRF_PPI || HAS_HW_NRF_DPPIC
select NRFX_PPI if HAS_HW_NRF_PPI
select NRFX_DPPI if HAS_HW_NRF_DPPIC
help
When enabled, polling out does not trigger interrupt which stops TX.
Feature uses a PPI channel.
config NRFX_UARTE$(nrfx_uart_num)
def_bool y if HAS_HW_NRF_UARTE$(nrfx_uart_num) && !UART_NRFX_UARTE_LEGACY_SHIM
config UART_$(nrfx_uart_num)_NRF_PARITY_BIT
bool "Parity bit"
help
Enable parity bit.
config UART_$(nrfx_uart_num)_NRF_TX_BUFFER_SIZE
int "Size of RAM buffer"
depends on HAS_HW_NRF_UARTE$(nrfx_uart_num)
depends on UART_NRFX_UARTE_LEGACY_SHIM
range 1 $(UINT16_MAX)
default 32
help
Size of the transmit buffer for API function: fifo_fill.
This value is limited by range of TXD.MAXCNT register for
particular SoC.
config UART_$(nrfx_uart_num)_NRF_HW_ASYNC
bool "Use hardware RX byte counting"
depends on HAS_HW_NRF_UARTE$(nrfx_uart_num)
depends on UART_ASYNC_API
depends on UART_NRFX_UARTE_LEGACY_SHIM
depends on HAS_HW_NRF_PPI || HAS_HW_NRF_DPPIC
select NRFX_PPI if HAS_HW_NRF_PPI
select NRFX_DPPI if HAS_HW_NRF_DPPIC
help
If default driver uses interrupts to count incoming bytes, it is possible
that with higher speeds and/or high cpu load some data can be lost.
It is recommended to use hardware byte counting in such scenarios.
Hardware RX byte counting requires timer instance and one PPI channel.
config UART_$(nrfx_uart_num)_NRF_ASYNC_LOW_POWER
bool "Low power mode"
depends on HAS_HW_NRF_UARTE$(nrfx_uart_num)
depends on UART_ASYNC_API
depends on UART_NRFX_UARTE_LEGACY_SHIM
help
When enabled, UARTE is enabled before each TX or RX usage and disabled
when not used. Disabling UARTE while in idle allows to achieve lowest
power consumption. It is only feasible if receiver is not always on.
config UART_$(nrfx_uart_num)_NRF_HW_ASYNC_TIMER
int "Timer instance"
depends on UART_$(nrfx_uart_num)_NRF_HW_ASYNC
config UART_$(nrfx_uart_num)_HAS_RX_CACHE_SECTION
def_bool $(dt_nodelabel_has_prop,uart$(nrfx_uart_num),memory-regions)
imply NRFX_UARTE_CONFIG_RX_CACHE_ENABLED
help
This helper symbol indicates the existence of a linker section which
can be dedicated to an RX cache buffer.
config UART_$(nrfx_uart_num)_TX_CACHE_SIZE
int "TX cache buffer size"
depends on !UART_NRFX_UARTE_LEGACY_SHIM
default 8
help
For UARTE, TX cache buffer is used when provided TX buffer is not located
in memory which can be used by the EasyDMA.
config UART_$(nrfx_uart_num)_RX_CACHE_SIZE
int "RX cache buffer size"
depends on !UART_NRFX_UARTE_LEGACY_SHIM
default 32 if UART_$(nrfx_uart_num)_HAS_RX_CACHE_SECTION
default 5
range 5 $(UINT8_MAX)
help
For UARTE, RX cache buffer is used when provided RX buffer is not located
in memory which can be used by the EasyDMA. It is also used to store
flushed data.
config UART_$(nrfx_uart_num)_A2I_RX_SIZE
depends on !UART_NRFX_UARTE_LEGACY_SHIM
int "Asynchronous to interrupt driven adaptation layer RX buffer size"
default 64 if UART_$(nrfx_uart_num)_INTERRUPT_DRIVEN
default 0
help
Amount of space dedicated for RX. It is divided into chunks with some
amount of that space used for control data.
config UART_$(nrfx_uart_num)_A2I_RX_BUF_COUNT
depends on !UART_NRFX_UARTE_LEGACY_SHIM
int "Asynchronous to interrupt driven adaptation layer RX buffer count"
default 8 if UART_$(nrfx_uart_num)_INTERRUPT_DRIVEN
default 0
help
Number of chunks into RX space is divided.
config UART_$(nrfx_uart_num)_GPIO_MANAGEMENT
bool "GPIO management on port $(nrfx_uart_num)"
depends on PM_DEVICE
default y
help
If enabled, the driver will configure the GPIOs used by the uart to
their default configuration when device is powered down. The GPIOs
will be configured back to correct state when UART is powered up.
``` | /content/code_sandbox/drivers/serial/Kconfig.nrfx_uart_instance | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 1,298 |
```c
/*
*
*/
/**
* @brief UART driver for Intel FPGA UART Core IP
* Reference : Embedded Peripherals IP User Guide (22.3 and above): 55.
* Lightweight UART Core
*/
#define DT_DRV_COMPAT intel_lw_uart
#include <zephyr/kernel.h>
#include <zephyr/drivers/uart.h>
#include <zephyr/drivers/serial/uart_intel_lw.h>
/* register offsets */
#define INTEL_LW_UART_OFFSET (0x4)
#define INTEL_LW_UART_RXDATA_REG_OFFSET (0 * INTEL_LW_UART_OFFSET)
#define INTEL_LW_UART_TXDATA_REG_OFFSET (1 * INTEL_LW_UART_OFFSET)
#define INTEL_LW_UART_STATUS_REG_OFFSET (2 * INTEL_LW_UART_OFFSET)
#define INTEL_LW_UART_CONTROL_REG_OFFSET (3 * INTEL_LW_UART_OFFSET)
#define INTEL_LW_UART_DIVISOR_REG_OFFSET (4 * INTEL_LW_UART_OFFSET)
#define INTEL_LW_UART_EOP_REG_OFFSET (5 * INTEL_LW_UART_OFFSET)
/*status register mask */
#define INTEL_LW_UART_STATUS_PE_MSK (0x1)
#define INTEL_LW_UART_STATUS_FE_MSK (0x2)
#define INTEL_LW_UART_STATUS_BRK_MSK (0x4)
#define INTEL_LW_UART_STATUS_ROE_MSK (0x8)
#define INTEL_LW_UART_STATUS_TOE_MSK (0x10)
#define INTEL_LW_UART_STATUS_TMT_MSK (0x20)
#define INTEL_LW_UART_STATUS_TRDY_MSK (0x40)
#define INTEL_LW_UART_STATUS_RRDY_MSK (0x80)
#define INTEL_LW_UART_STATUS_DCTS_MSK (0x400)
#define INTEL_LW_UART_STATUS_CTS_MSK (0x800)
#define INTEL_LW_UART_STATUS_E_MSK (0x100)
#define INTEL_LW_UART_STATUS_EOP_MSK (0x1000)
/* control register mask */
#define INTEL_LW_UART_CONTROL_TMT_MSK (0x20)
#define INTEL_LW_UART_CONTROL_TRDY_MSK (0x40)
#define INTEL_LW_UART_CONTROL_RRDY_MSK (0x80)
#define INTEL_LW_UART_CONTROL_E_MSK (0x100)
#define INTEL_LW_UART_CONTROL_TRBK_MSK (0x200)
#define INTEL_LW_UART_CONTROL_DCTS_MSK (0x400)
#define INTEL_LW_UART_CONTROL_RTS_MSK (0x800)
#define INTEL_LW_UART_CONTROL_EOP_MSK (0x1000)
/* defined values */
#define UART_INTEL_LW_NO_ERROR (0u)
#define INTEL_LW_UART_CLEAR_STATUS_VAL (0u)
#define INTEL_LW_UART_PENDING_MASK (INTEL_LW_UART_STATUS_RRDY_MSK | \
INTEL_LW_UART_STATUS_TRDY_MSK | INTEL_LW_UART_STATUS_E_MSK \
| INTEL_LW_UART_STATUS_EOP_MSK)
/***********************/
/* configuration flags */
/*
* The value INTEL_LW_UART_FB is a value set in the devices flag field to
* indicate that the device has a fixed baud rate; i.e. if this flag is set
* software can not control the baud rate of the device.
*/
#define INTEL_LW_UART_FB 0x1
/*
* The value INTEL_LW_UART_FC is a value set in the device flag field to
* indicate the device is using flow control, i.e. the driver must
* throttle on transmit if the nCTS pin is low.
*/
#define INTEL_LW_UART_FC 0x2
/* end of configuration flags */
/******************************/
/* device data */
struct uart_intel_lw_device_data {
struct uart_config uart_cfg; /* stores uart config from device tree*/
struct k_spinlock lock;
uint32_t status_act; /* stores value of status register. */
#ifdef CONFIG_UART_INTERRUPT_DRIVEN
uart_irq_callback_user_data_t cb; /**< Callback function pointer */
void *cb_data; /**< Callback function arg */
#ifdef CONFIG_UART_INTEL_LW_EOP
uint8_t set_eop_cb;
uart_irq_callback_user_data_t cb_eop; /**< Callback function pointer */
void *cb_data_eop; /**< Callback function arg */
#endif /* CONFIG_UART_INTEL_LW_EOP */
uint32_t control_val; /* stores value to set control register. */
#endif /* CONFIG_UART_INTERRUPT_DRIVEN */
};
/*
* device config:
* stores data that cannot be changed during run time.
*/
struct uart_intel_lw_device_config {
mm_reg_t base;
uint32_t flags; /* refer to configuration flags */
#ifdef CONFIG_UART_INTERRUPT_DRIVEN
uart_irq_config_func_t irq_config_func;
unsigned int irq_num;
#endif /* CONFIG_UART_INTERRUPT_DRIVEN */
};
#ifdef CONFIG_UART_INTERRUPT_DRIVEN
/**
* function prototypes
*/
static int uart_intel_lw_irq_update(const struct device *dev);
static int uart_intel_lw_irq_tx_ready(const struct device *dev);
static int uart_intel_lw_irq_rx_ready(const struct device *dev);
#endif /* CONFIG_UART_INTERRUPT_DRIVEN */
/**
* @brief Poll the device for input.
*
* This is a non-blocking function.
*
* This driver supports interrupt driven api.
* Polling for data under normal operation, might cause unexpected behaviour.
* If users wish to poll in for data, please ensure that the data is not retrieved
* in interrupt.
*
* If UART_LINE_CTRL is enabled, please do not disable the hardware
* interrupt for this uart device, as the flow control is handled in uart_intel_lw_dcts_isr.
*
* @param dev UART device instance
* @param p_char Pointer to character
*
* @return 0 if a character arrived, -1 if input buffer is empty.
* -EINVAL if p_char is null pointer
*/
static int uart_intel_lw_poll_in(const struct device *dev, unsigned char *p_char)
{
const struct uart_intel_lw_device_config *config = dev->config;
struct uart_intel_lw_device_data *data = dev->data;
int ret_val = -1;
uint32_t status;
/* generate fatal error if CONFIG_ASSERT is enabled. */
__ASSERT(p_char != NULL, "p_char is null pointer!");
/* Stop, if p_char is null pointer */
if (p_char == NULL) {
return -EINVAL;
}
k_spinlock_key_t key = k_spin_lock(&data->lock);
/* check if received character is ready.*/
status = sys_read32(config->base + INTEL_LW_UART_STATUS_REG_OFFSET);
if (status & INTEL_LW_UART_STATUS_RRDY_MSK) {
/* got a character */
*p_char = sys_read32(config->base + INTEL_LW_UART_RXDATA_REG_OFFSET);
ret_val = 0;
}
k_spin_unlock(&data->lock, key);
return ret_val;
}
/**
* @brief Output a character in polled mode.
*
* This function will block until transmitter is ready.
* Then, a character will be transmitted.
*
* This driver supports interrupt driven api.
* Polling for data under normal operation, might cause unexpected behaviour.
* If users wish to poll out data, please ensure that the data is not transmitted
* in interrupt.
*
* If UART_LINE_CTRL is enabled and users wish to poll out only 1 character,
* please enable UART_INTEL_LW_AUTO_LINE_CTRL_POLL. Please note that this might
* be inefficient, in case of polling out several characters. Instead of using
* UART_INTEL_LW_AUTO_LINE_CTRL_POLL, please consider using the api: uart_drv_cmd
* with CMD_POLL_ASSERT_RTS before polling out. Then use CMD_POLL_DEASSERT_RTS to
* resume normal operation after all characters are polled out.
*
* Please do not set CMD_TRBK_EN, when polling out data.
*
* @param dev UART device instance
* @param c Character to send
*/
static void uart_intel_lw_poll_out(const struct device *dev, unsigned char c)
{
const struct uart_intel_lw_device_config *config = dev->config;
struct uart_intel_lw_device_data *data = dev->data;
uint32_t status;
bool tx_is_free = false;
bool poll_out_done = false;
k_spinlock_key_t key;
/* wait until uart is free to transmit.*/
do {
key = k_spin_lock(&data->lock);
if (tx_is_free == false) {
status = sys_read32(config->base + INTEL_LW_UART_STATUS_REG_OFFSET);
/* wait until there is space in fifo. */
if (status & INTEL_LW_UART_STATUS_TRDY_MSK) {
#ifdef CONFIG_UART_INTEL_LW_AUTO_LINE_CTRL_POLL
data->control_val |= INTEL_LW_UART_CONTROL_RTS_MSK;
sys_write32(data->control_val, config->base
+ INTEL_LW_UART_CONTROL_REG_OFFSET);
#endif
sys_write32(c, config->base + INTEL_LW_UART_TXDATA_REG_OFFSET);
tx_is_free = true;
}
} else {
status = sys_read32(config->base + INTEL_LW_UART_STATUS_REG_OFFSET);
/* wait until fifo data is shifted out. */
if (status & INTEL_LW_UART_STATUS_TMT_MSK) {
#ifdef CONFIG_UART_INTEL_LW_AUTO_LINE_CTRL_POLL
data->control_val &= ~INTEL_LW_UART_CONTROL_RTS_MSK;
sys_write32(data->control_val, config->base
+ INTEL_LW_UART_CONTROL_REG_OFFSET);
#endif
poll_out_done = true;
}
}
k_spin_unlock(&data->lock, key);
} while (!poll_out_done);
}
/**
* @brief Initialise an instance of the driver
*
* This function initialise the interrupt configuration for the driver.
*
* @param dev UART device instance
*
* @return 0 to indicate success.
*/
static int uart_intel_lw_init(const struct device *dev)
{
#ifdef CONFIG_UART_INTERRUPT_DRIVEN
struct uart_intel_lw_device_data *data = dev->data;
const struct uart_intel_lw_device_config *config = dev->config;
/* clear status to ensure, that interrupts are not triggered due to old status. */
sys_write32(INTEL_LW_UART_CLEAR_STATUS_VAL, config->base
+ INTEL_LW_UART_STATUS_REG_OFFSET);
/*
* Enable hardware interrupt.
* The corresponding csr from IP still needs to be set,
* so that the IP generates interrupt signal.
*/
config->irq_config_func(dev);
#ifdef CONFIG_UART_LINE_CTRL
/* Enable DCTS interrupt. */
data->control_val = INTEL_LW_UART_CONTROL_DCTS_MSK;
#endif /* CONFIG_UART_LINE_CTRL */
sys_write32(data->control_val, config->base + INTEL_LW_UART_CONTROL_REG_OFFSET);
#endif /* CONFIG_UART_INTERRUPT_DRIVEN */
return 0;
}
/**
* @brief Check if an error was received
* If error is received, it will be mapped to uart_rx_stop_reason.
* This function should be called after irq_update.
* If interrupt driven API is not enabled,
* this function will read and clear the status register.
*
* @param dev UART device struct
*
* @return UART_ERROR_OVERRUN, UART_ERROR_PARITY, UART_ERROR_FRAMING,
* UART_BREAK if an error was detected, 0 otherwise.
*/
static int uart_intel_lw_err_check(const struct device *dev)
{
struct uart_intel_lw_device_data *data = dev->data;
int err = UART_INTEL_LW_NO_ERROR;
#ifndef CONFIG_UART_INTERRUPT_DRIVEN
const struct uart_intel_lw_device_config *config = dev->config;
k_spinlock_key_t key = k_spin_lock(&data->lock);
data->status_act = sys_read32(config->base + INTEL_LW_UART_STATUS_REG_OFFSET);
#endif
if (data->status_act & INTEL_LW_UART_STATUS_E_MSK) {
if (data->status_act & INTEL_LW_UART_STATUS_PE_MSK) {
err |= UART_ERROR_PARITY;
}
if (data->status_act & INTEL_LW_UART_STATUS_FE_MSK) {
err |= UART_ERROR_FRAMING;
}
if (data->status_act & INTEL_LW_UART_STATUS_BRK_MSK) {
err |= UART_BREAK;
}
if (data->status_act & INTEL_LW_UART_STATUS_ROE_MSK) {
err |= UART_ERROR_OVERRUN;
}
}
#ifndef CONFIG_UART_INTERRUPT_DRIVEN
/* clear status */
sys_write32(INTEL_LW_UART_CLEAR_STATUS_VAL, config->base
+ INTEL_LW_UART_STATUS_REG_OFFSET);
k_spin_unlock(&data->lock, key);
#endif
return err;
}
#ifdef CONFIG_UART_USE_RUNTIME_CONFIGURE
/***
* @brief helper function to check, if the configuration is support.
* The only parameter that can be changed during runtime is the baudrate.
*
* @param cfg_stored The original configuration.
* @param cfg_in The input configuration.
* @return true if parameter other than baudrate remains the same. otherwise, false.
*/
static bool uart_intel_lw_check_configuration(const struct uart_config *cfg_stored,
const struct uart_config *cfg_in)
{
bool ret_val = false;
if ((cfg_stored->parity == cfg_in->parity)
&& (cfg_stored->stop_bits == cfg_in->stop_bits)
&& (cfg_stored->data_bits == cfg_in->data_bits)
&& (cfg_stored->flow_ctrl == cfg_in->flow_ctrl)) {
ret_val = true;
}
return ret_val;
}
/**
* @brief Set UART configuration using data from *cfg_in.
*
* @param dev UART Device struct
* @param cfg_in The input configuration.
*
* @return 0 if success, -ENOTSUP, if input from cfg_in is not configurable.
* -EINVAL if cfg_in is null pointer
*/
static int uart_intel_lw_configure(const struct device *dev,
const struct uart_config *cfg_in)
{
const struct uart_intel_lw_device_config *config = dev->config;
struct uart_intel_lw_device_data * const data = dev->data;
struct uart_config * const cfg_stored = &data->uart_cfg;
uint32_t divisor_val;
int ret_val;
/* generate fatal error if CONFIG_ASSERT is enabled. */
__ASSERT(cfg_in != NULL, "cfg_in is null pointer!");
/* Stop, if cfg_in is null pointer */
if (cfg_in == NULL) {
return -EINVAL;
}
/* check if configuration is supported. */
if (uart_intel_lw_check_configuration(cfg_stored, cfg_in)
&& !(config->flags & INTEL_LW_UART_FB)) {
/* parameter is valid, just return ok if baudrate is the same. */
if (cfg_stored->baudrate != cfg_in->baudrate) {
/* calculate and set baudrate. */
divisor_val = (CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC/cfg_in->baudrate) - 1;
sys_write32(divisor_val, config->base + INTEL_LW_UART_DIVISOR_REG_OFFSET);
/* update stored data. */
cfg_stored->baudrate = cfg_in->baudrate;
}
ret_val = 0;
} else {
/* return not supported */
ret_val = -ENOTSUP;
}
return ret_val;
}
#endif /* CONFIG_UART_USE_RUNTIME_CONFIGURE */
/**
* @brief Get UART configuration and stores in *cfg_out.
*
* @param dev UART Device struct
* @param cfg_out The output configuration.
*
* @return 0 if success.
* -EINVAL if cfg_out is null pointer
*/
static int uart_intel_lw_config_get(const struct device *dev,
struct uart_config *cfg_out)
{
const struct uart_intel_lw_device_data *data = dev->data;
/* generate fatal error if CONFIG_ASSERT is enabled. */
__ASSERT(cfg_out != NULL, "cfg_out is null pointer!");
/* Stop, if cfg_out is null pointer */
if (cfg_out == NULL) {
return -EINVAL;
}
*cfg_out = data->uart_cfg;
return 0;
}
#ifdef CONFIG_UART_INTERRUPT_DRIVEN
/**
* @brief Fill FIFO with data
* This function is expected to be called from UART interrupt handler (ISR),
* if uart_irq_tx_ready() returns true. This function does not block!
*
* @param dev UART device struct
* @param tx_data Data to transmit
* @param size Number of bytes to send
*
* @return Number of bytes sent
*/
static int uart_intel_lw_fifo_fill(const struct device *dev,
const uint8_t *tx_data,
int size)
{
const struct uart_intel_lw_device_config *config = dev->config;
struct uart_intel_lw_device_data *data = dev->data;
int ret_val = 0;
k_spinlock_key_t key;
/* generate fatal error if CONFIG_ASSERT is enabled. */
__ASSERT(tx_data != NULL, "tx_data is null pointer!");
/* Stop, if tx_data is null pointer */
if (tx_data == NULL) {
return 0;
}
/* Stop, if transmit break is set */
if (data->control_val & INTEL_LW_UART_CONTROL_TRBK_MSK) {
return 0;
}
do {
if (data->status_act & INTEL_LW_UART_STATUS_TRDY_MSK) {
key = k_spin_lock(&data->lock);
sys_write32(tx_data[ret_val++], config->base
+ INTEL_LW_UART_TXDATA_REG_OFFSET);
data->status_act = sys_read32(config->base
+ INTEL_LW_UART_STATUS_REG_OFFSET);
k_spin_unlock(&data->lock, key);
} else {
/* stop because tx fifo is full! */
break;
}
} while ((size - ret_val) > 0);
return ret_val;
}
/**
* @brief Read data from FIFO
* This function is expected to be called from UART interrupt handler (ISR),
* if uart_irq_rx_ready() returns true.
*
* @param dev UART device struct
* @param rx_data Data container
* @param size Container size
*
* @return Number of bytes read
*/
static int uart_intel_lw_fifo_read(const struct device *dev, uint8_t *rx_data,
const int size)
{
const struct uart_intel_lw_device_config *config = dev->config;
struct uart_intel_lw_device_data *data = dev->data;
int ret_val = 0;
k_spinlock_key_t key;
/* generate fatal error if CONFIG_ASSERT is enabled. */
__ASSERT(rx_data != NULL, "rx_data is null pointer!");
/* Stop, if rx_data is null pointer */
if (rx_data == NULL) {
return 0;
}
do {
if (data->status_act & INTEL_LW_UART_STATUS_RRDY_MSK) {
key = k_spin_lock(&data->lock);
rx_data[ret_val++] = sys_read32(config->base +
INTEL_LW_UART_RXDATA_REG_OFFSET);
data->status_act = sys_read32(config->base
+ INTEL_LW_UART_STATUS_REG_OFFSET);
k_spin_unlock(&data->lock, key);
} else {
break;
}
} while ((size - ret_val) > 0);
return ret_val;
}
/**
* @brief Enable TX interrupt
*
* @param dev UART device struct
*/
static void uart_intel_lw_irq_tx_enable(const struct device *dev)
{
struct uart_intel_lw_device_data *data = dev->data;
const struct uart_intel_lw_device_config *config = dev->config;
k_spinlock_key_t key = k_spin_lock(&data->lock);
data->control_val |= INTEL_LW_UART_CONTROL_TRDY_MSK;
#ifdef CONFIG_UART_LINE_CTRL
/* also enable RTS, if flow control is enabled. */
data->control_val |= INTEL_LW_UART_CONTROL_RTS_MSK;
#endif
sys_write32(data->control_val, config->base + INTEL_LW_UART_CONTROL_REG_OFFSET);
k_spin_unlock(&data->lock, key);
}
/**
* @brief Disable TX interrupt
*
* @param dev UART device struct
*/
static void uart_intel_lw_irq_tx_disable(const struct device *dev)
{
struct uart_intel_lw_device_data *data = dev->data;
const struct uart_intel_lw_device_config *config = dev->config;
k_spinlock_key_t key = k_spin_lock(&data->lock);
data->control_val &= ~INTEL_LW_UART_CONTROL_TRDY_MSK;
#ifdef CONFIG_UART_LINE_CTRL
/* also disable RTS, if flow control is enabled. */
data->control_val &= ~INTEL_LW_UART_CONTROL_RTS_MSK;
#endif
sys_write32(data->control_val, config->base + INTEL_LW_UART_CONTROL_REG_OFFSET);
k_spin_unlock(&data->lock, key);
}
/**
* @brief Check if UART TX buffer can accept a new char.
*
* @param dev UART device struct
*
* @return 1 if TX interrupt is enabled and at least one char can be written to UART.
* 0 if device is not ready to write a new byte.
*/
static int uart_intel_lw_irq_tx_ready(const struct device *dev)
{
struct uart_intel_lw_device_data *data = dev->data;
int ret_val = 0;
k_spinlock_key_t key = k_spin_lock(&data->lock);
/* if TX interrupt is enabled */
if (data->control_val & INTEL_LW_UART_CONTROL_TRDY_MSK) {
/* IP core does not have fifo. Wait until tx data is completely shifted. */
if (data->status_act & INTEL_LW_UART_STATUS_TMT_MSK) {
ret_val = 1;
}
}
#ifdef CONFIG_UART_LINE_CTRL
/* if flow control is enabled, set tx not ready, if CTS is low. */
if ((data->status_act & INTEL_LW_UART_STATUS_CTS_MSK) == 0) {
ret_val = 0;
}
#endif /* CONFIG_UART_LINE_CTRL */
k_spin_unlock(&data->lock, key);
return ret_val;
}
/**
* @brief Check if nothing remains to be transmitted
*
* @param dev UART device struct
*
* @return 1 if nothing remains to be transmitted, 0 otherwise
*/
static int uart_intel_lw_irq_tx_complete(const struct device *dev)
{
struct uart_intel_lw_device_data *data = dev->data;
int ret_val = 0;
k_spinlock_key_t key = k_spin_lock(&data->lock);
if (data->status_act & INTEL_LW_UART_STATUS_TMT_MSK) {
ret_val = 1;
}
k_spin_unlock(&data->lock, key);
return ret_val;
}
/**
* @brief Enable RX interrupt in
*
* @param dev UART device struct
*/
static void uart_intel_lw_irq_rx_enable(const struct device *dev)
{
struct uart_intel_lw_device_data *data = dev->data;
const struct uart_intel_lw_device_config *config = dev->config;
k_spinlock_key_t key = k_spin_lock(&data->lock);
data->control_val |= INTEL_LW_UART_CONTROL_RRDY_MSK;
sys_write32(data->control_val, config->base + INTEL_LW_UART_CONTROL_REG_OFFSET);
k_spin_unlock(&data->lock, key);
}
/**
* @brief Disable RX interrupt
*
* @param dev UART device struct
*/
static void uart_intel_lw_irq_rx_disable(const struct device *dev)
{
struct uart_intel_lw_device_data *data = dev->data;
const struct uart_intel_lw_device_config *config = dev->config;
k_spinlock_key_t key = k_spin_lock(&data->lock);
data->control_val &= ~INTEL_LW_UART_CONTROL_RRDY_MSK;
sys_write32(data->control_val, config->base + INTEL_LW_UART_CONTROL_REG_OFFSET);
k_spin_unlock(&data->lock, key);
}
/**
* @brief Check if Rx IRQ has been raised
*
* @param dev UART device struct
*
* @return 1 if an IRQ is ready, 0 otherwise
*/
static int uart_intel_lw_irq_rx_ready(const struct device *dev)
{
struct uart_intel_lw_device_data *data = dev->data;
int ret_val = 0;
k_spinlock_key_t key = k_spin_lock(&data->lock);
/* if RX interrupt is enabled */
if (data->control_val & INTEL_LW_UART_CONTROL_RRDY_MSK) {
/* check for space in rx data register */
if (data->status_act & INTEL_LW_UART_STATUS_RRDY_MSK) {
ret_val = 1;
}
}
k_spin_unlock(&data->lock, key);
return ret_val;
}
/**
* @brief This function will cache the status register.
*
* @param dev UART device struct
*
* @return 1 for success.
*/
static int uart_intel_lw_irq_update(const struct device *dev)
{
struct uart_intel_lw_device_data *data = dev->data;
const struct uart_intel_lw_device_config *config = dev->config;
k_spinlock_key_t key = k_spin_lock(&data->lock);
data->status_act = sys_read32(config->base + INTEL_LW_UART_STATUS_REG_OFFSET);
k_spin_unlock(&data->lock, key);
return 1;
}
/**
* @brief Check if any IRQ is pending
*
* @param dev UART device struct
*
* @return 1 if an IRQ is pending, 0 otherwise
*/
static int uart_intel_lw_irq_is_pending(const struct device *dev)
{
struct uart_intel_lw_device_data *data = dev->data;
int ret_val = 0;
k_spinlock_key_t key = k_spin_lock(&data->lock);
if (data->status_act & data->control_val & INTEL_LW_UART_PENDING_MASK) {
ret_val = 1;
}
k_spin_unlock(&data->lock, key);
return ret_val;
}
/**
* @brief Set the callback function pointer for IRQ.
*
* @param dev UART device struct
* @param cb Callback function pointer.
* @param cb_data Data to pass to callback function.
*/
static void uart_intel_lw_irq_callback_set(const struct device *dev,
uart_irq_callback_user_data_t cb,
void *cb_data)
{
struct uart_intel_lw_device_data *data = dev->data;
k_spinlock_key_t key = k_spin_lock(&data->lock);
#ifdef CONFIG_UART_INTEL_LW_EOP
if (data->set_eop_cb) {
data->cb_eop = cb;
data->cb_data_eop = cb_data;
data->set_eop_cb = 0;
} else {
data->cb = cb;
data->cb_data = cb_data;
}
#else
data->cb = cb;
data->cb_data = cb_data;
#endif /* CONFIG_UART_INTEL_LW_EOP */
k_spin_unlock(&data->lock, key);
}
#ifdef CONFIG_UART_LINE_CTRL
/**
* @brief DCTS Interrupt service routine.
*
* Handles assertion and deassettion of CTS/RTS stignal
*
* @param dev Pointer to UART device struct
*/
static void uart_intel_lw_dcts_isr(const struct device *dev)
{
struct uart_intel_lw_device_data *data = dev->data;
const struct uart_intel_lw_device_config *config = dev->config;
k_spinlock_key_t key = k_spin_lock(&data->lock);
/* Assume that user follows zephyr requirement and update status in their call back. */
if (data->status_act & INTEL_LW_UART_STATUS_CTS_MSK) {
/* Assert RTS to inform other UART. */
data->control_val |= INTEL_LW_UART_CONTROL_RTS_MSK;
sys_write32(data->control_val, config->base
+ INTEL_LW_UART_CONTROL_REG_OFFSET);
} else {
/* other UART deasserts RTS */
if (data->status_act & INTEL_LW_UART_STATUS_TMT_MSK) {
/* only deasserts if not transmitting. */
data->control_val &= ~INTEL_LW_UART_CONTROL_RTS_MSK;
sys_write32(data->control_val, config->base
+ INTEL_LW_UART_CONTROL_REG_OFFSET);
}
}
k_spin_unlock(&data->lock, key);
}
#endif /* CONFIG_UART_LINE_CTRL */
/**
* @brief Interrupt service routine.
*
* This simply calls the callback function, if one exists.
*
* @param dev Pointer to UART device struct
*
*/
static void uart_intel_lw_isr(const struct device *dev)
{
struct uart_intel_lw_device_data *data = dev->data;
const struct uart_intel_lw_device_config *config = dev->config;
uart_irq_callback_user_data_t callback = data->cb;
if (callback) {
callback(dev, data->cb_data);
}
/* Post ISR */
#if CONFIG_UART_INTEL_LW_EOP
data->status_act = sys_read32(config->base + INTEL_LW_UART_STATUS_REG_OFFSET);
if (data->status_act & INTEL_LW_UART_STATUS_EOP_MSK) {
callback = data->cb_eop;
if (callback) {
callback(dev, data->cb_data_eop);
}
}
#endif /* CONFIG_UART_INTEL_LW_EOP */
#ifdef CONFIG_UART_LINE_CTRL
data->status_act = sys_read32(config->base + INTEL_LW_UART_STATUS_REG_OFFSET);
/* handles RTS/CTS signal */
if (data->status_act & INTEL_LW_UART_STATUS_DCTS_MSK) {
uart_intel_lw_dcts_isr(dev);
}
#endif
/* clear status after all interrupts are handled. */
sys_write32(INTEL_LW_UART_CLEAR_STATUS_VAL, config->base
+ INTEL_LW_UART_STATUS_REG_OFFSET);
}
#ifdef CONFIG_UART_DRV_CMD
/**
* @brief Send extra command to driver
*
* @param dev UART device struct
* @param cmd Command to driver
* @param p Parameter to the command
*
* @return 0 if successful, failed otherwise
*/
static int uart_intel_lw_drv_cmd(const struct device *dev, uint32_t cmd,
uint32_t p)
{
struct uart_intel_lw_device_data *data = dev->data;
const struct uart_intel_lw_device_config *config = dev->config;
int ret_val = -ENOTSUP;
k_spinlock_key_t key = k_spin_lock(&data->lock);
switch (cmd) {
#if CONFIG_UART_INTEL_LW_EOP
case CMD_ENABLE_EOP:
/* enable EOP interrupt */
data->control_val |= INTEL_LW_UART_CONTROL_EOP_MSK;
sys_write32(data->control_val, config->base
+ INTEL_LW_UART_CONTROL_REG_OFFSET);
/* set EOP character */
sys_write32((uint8_t) p, config->base + INTEL_LW_UART_EOP_REG_OFFSET);
/* after this, user needs to call uart_irq_callback_set
* to set data->cb_eop and data->cb_data_eop!
*/
data->set_eop_cb = 1;
ret_val = 0;
break;
case CMD_DISABLE_EOP:
/* disable EOP interrupt */
data->control_val &= ~INTEL_LW_UART_CONTROL_EOP_MSK;
sys_write32(data->control_val, config->base
+ INTEL_LW_UART_CONTROL_REG_OFFSET);
/* clear call back */
data->cb_eop = NULL;
data->cb_data_eop = NULL;
ret_val = 0;
break;
#endif /* CONFIG_UART_INTEL_LW_EOP */
case CMD_TRBK_EN:
/* enable transmit break */
data->control_val |= INTEL_LW_UART_CONTROL_TRBK_MSK;
sys_write32(data->control_val, config->base
+ INTEL_LW_UART_CONTROL_REG_OFFSET);
ret_val = 0;
break;
case CMD_TRBK_DIS:
/* disable transmit break */
data->control_val &= ~INTEL_LW_UART_CONTROL_TRBK_MSK;
sys_write32(data->control_val, config->base
+ INTEL_LW_UART_CONTROL_REG_OFFSET);
ret_val = 0;
break;
case CMD_POLL_ASSERT_RTS:
/* assert RTS */
data->control_val |= INTEL_LW_UART_CONTROL_RTS_MSK;
sys_write32(data->control_val, config->base
+ INTEL_LW_UART_CONTROL_REG_OFFSET);
ret_val = 0;
break;
case CMD_POLL_DEASSERT_RTS:
/* deassert RTS */
data->control_val &= ~INTEL_LW_UART_CONTROL_RTS_MSK;
sys_write32(data->control_val, config->base
+ INTEL_LW_UART_CONTROL_REG_OFFSET);
ret_val = 0;
break;
default:
ret_val = -ENOTSUP;
break;
};
k_spin_unlock(&data->lock, key);
return ret_val;
}
#endif /* CONFIG_UART_DRV_CMD */
#endif /* CONFIG_UART_INTERRUPT_DRIVEN */
static const struct uart_driver_api uart_intel_lw_driver_api = {
.poll_in = uart_intel_lw_poll_in,
.poll_out = uart_intel_lw_poll_out,
.err_check = uart_intel_lw_err_check,
#ifdef CONFIG_UART_USE_RUNTIME_CONFIGURE
.configure = uart_intel_lw_configure,
#endif /* CONFIG_UART_USE_RUNTIME_CONFIGURE */
.config_get = uart_intel_lw_config_get,
#ifdef CONFIG_UART_INTERRUPT_DRIVEN
.fifo_fill = uart_intel_lw_fifo_fill,
.fifo_read = uart_intel_lw_fifo_read,
.irq_tx_enable = uart_intel_lw_irq_tx_enable,
.irq_tx_disable = uart_intel_lw_irq_tx_disable,
.irq_tx_ready = uart_intel_lw_irq_tx_ready,
.irq_tx_complete = uart_intel_lw_irq_tx_complete,
.irq_rx_enable = uart_intel_lw_irq_rx_enable,
.irq_rx_disable = uart_intel_lw_irq_rx_disable,
.irq_rx_ready = uart_intel_lw_irq_rx_ready,
.irq_is_pending = uart_intel_lw_irq_is_pending,
.irq_update = uart_intel_lw_irq_update,
.irq_callback_set = uart_intel_lw_irq_callback_set,
#endif
#ifdef CONFIG_UART_DRV_CMD
.drv_cmd = uart_intel_lw_drv_cmd,
#endif
};
#ifdef CONFIG_UART_INTERRUPT_DRIVEN
#define UART_INTEL_LW_IRQ_CONFIG_FUNC(n) \
static void uart_intel_lw_irq_config_func_##n(const struct device *dev) \
{ \
IRQ_CONNECT(DT_INST_IRQN(n), \
DT_INST_IRQ(n, priority), \
uart_intel_lw_isr, \
DEVICE_DT_INST_GET(n), 0); \
\
irq_enable(DT_INST_IRQN(n)); \
}
#define UART_INTEL_LW_IRQ_CONFIG_INIT(n) \
.irq_config_func = uart_intel_lw_irq_config_func_##n, \
.irq_num = DT_INST_IRQN(n),
#else
#define UART_INTEL_LW_IRQ_CONFIG_FUNC(n)
#define UART_INTEL_LW_IRQ_CONFIG_INIT(n)
#endif /* CONFIG_UART_INTERRUPT_DRIVEN */
#define UART_INTEL_LW_DEVICE_INIT(n) \
UART_INTEL_LW_IRQ_CONFIG_FUNC(n) \
static struct uart_intel_lw_device_data uart_intel_lw_dev_data_##n = { \
.uart_cfg = \
{ \
.baudrate = DT_INST_PROP(n, current_speed), \
.parity = DT_INST_ENUM_IDX_OR(n, parity, \
UART_CFG_PARITY_NONE), \
.stop_bits = DT_INST_ENUM_IDX_OR(n, stop_bits, \
UART_CFG_STOP_BITS_1), \
.data_bits = DT_INST_ENUM_IDX_OR(n, data_bits, \
UART_CFG_DATA_BITS_8), \
.flow_ctrl = DT_INST_PROP(n, hw_flow_control) ? \
UART_CFG_FLOW_CTRL_RTS_CTS : \
UART_CFG_FLOW_CTRL_NONE, \
}, \
}; \
\
static const struct uart_intel_lw_device_config uart_intel_lw_dev_cfg_##n = { \
.base = DT_INST_REG_ADDR(n), \
.flags = ((DT_INST_PROP(n, fixed_baudrate)?INTEL_LW_UART_FB:0) \
|(DT_INST_PROP(n, hw_flow_control)?INTEL_LW_UART_FC:0)),\
UART_INTEL_LW_IRQ_CONFIG_INIT(n) \
}; \
\
DEVICE_DT_INST_DEFINE(n, \
uart_intel_lw_init, \
NULL, \
&uart_intel_lw_dev_data_##n, \
&uart_intel_lw_dev_cfg_##n, \
PRE_KERNEL_1, \
CONFIG_SERIAL_INIT_PRIORITY, \
&uart_intel_lw_driver_api);
DT_INST_FOREACH_STATUS_OKAY(UART_INTEL_LW_DEVICE_INIT)
``` | /content/code_sandbox/drivers/serial/uart_intel_lw.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 8,034 |
```unknown
# Infineon CAT1 UART configuration options
# an affiliate of Cypress Semiconductor Corporation
config UART_INFINEON_CAT1
bool "Infineon CAT1 UART driver"
default y
depends on DT_HAS_INFINEON_CAT1_UART_ENABLED
select SERIAL_HAS_DRIVER
select SERIAL_SUPPORT_INTERRUPT
select USE_INFINEON_UART
help
This option enables the UART driver for Infineon CAT1 family.
``` | /content/code_sandbox/drivers/serial/Kconfig.ifx_cat1 | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 87 |
```unknown
#
# Author: Parthiban Nallathambi <parthiban@linumiz.com>
config UART_XMC4XXX
bool "XMC4XX UART driver"
default y
depends on DT_HAS_INFINEON_XMC4XXX_UART_ENABLED
select SERIAL_HAS_DRIVER
select SERIAL_SUPPORT_INTERRUPT
select SERIAL_SUPPORT_ASYNC if DT_HAS_INFINEON_XMC4XXX_DMA_ENABLED
select DMA if UART_ASYNC_API
help
This option enables the XMC4XX UART driver.
if UART_XMC4XXX
config UART_XMC4XXX_RX_FIFO_INT_TRIGGER
bool "Continue to trigger fifo rx interrupt"
default n
help
When this option is enabled, an interrupt will continue to trigger
if there is data in the receive fifo. Otherwise, an interrupt will
trigger only once on the first received byte. The receive fifo will
need to be fully flushed so that the interrupt will trigger again.
endif
``` | /content/code_sandbox/drivers/serial/Kconfig.xmc4xxx | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 197 |
```unknown
# Atmel SAM SERCOM configuration options
config UART_SAM0
bool "Atmel SAM0 series SERCOM USART driver"
default y
depends on DT_HAS_ATMEL_SAM0_UART_ENABLED
select SERIAL_HAS_DRIVER
select SERIAL_SUPPORT_INTERRUPT
select SERIAL_SUPPORT_ASYNC if DT_HAS_ATMEL_SAM0_DMAC_ENABLED
help
This option enables the SERCOMx USART driver for Atmel SAM0 MCUs.
config UART_SAM0_ASYNC
bool "Async UART support for Atmel SAM0 series."
depends on DMA_SAM0
depends on UART_SAM0
depends on UART_ASYNC_API
``` | /content/code_sandbox/drivers/serial/Kconfig.sam0 | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 134 |
```c
/*
*
*/
#define DT_DRV_COMPAT atmel_sam0_uart
#include <zephyr/device.h>
#include <errno.h>
#include <zephyr/init.h>
#include <zephyr/sys/__assert.h>
#include <soc.h>
#include <zephyr/drivers/uart.h>
#include <zephyr/drivers/dma.h>
#include <zephyr/drivers/pinctrl.h>
#include <string.h>
#include <zephyr/irq.h>
#ifndef SERCOM_USART_CTRLA_MODE_USART_INT_CLK
#define SERCOM_USART_CTRLA_MODE_USART_INT_CLK SERCOM_USART_CTRLA_MODE(0x1)
#endif
/*
* Interrupt error flag is only supported in devices with
* SERCOM revision 0x500
*/
#if defined(SERCOM_U2201) && (REV_SERCOM == 0x500)
#define SERCOM_REV500
#endif
/* Device constant configuration parameters */
struct uart_sam0_dev_cfg {
SercomUsart *regs;
uint32_t baudrate;
uint32_t pads;
bool collision_detect;
#ifdef MCLK
volatile uint32_t *mclk;
uint32_t mclk_mask;
uint16_t gclk_core_id;
#else
uint32_t pm_apbcmask;
uint16_t gclk_clkctrl_id;
#endif
#if CONFIG_UART_INTERRUPT_DRIVEN || CONFIG_UART_SAM0_ASYNC
void (*irq_config_func)(const struct device *dev);
#endif
#if CONFIG_UART_SAM0_ASYNC
const struct device *dma_dev;
uint8_t tx_dma_request;
uint8_t tx_dma_channel;
uint8_t rx_dma_request;
uint8_t rx_dma_channel;
#endif
const struct pinctrl_dev_config *pcfg;
};
/* Device run time data */
struct uart_sam0_dev_data {
struct uart_config config_cache;
#ifdef CONFIG_UART_INTERRUPT_DRIVEN
uart_irq_callback_user_data_t cb;
void *cb_data;
uint8_t txc_cache;
#endif
#if CONFIG_UART_SAM0_ASYNC
const struct device *dev;
const struct uart_sam0_dev_cfg *cfg;
uart_callback_t async_cb;
void *async_cb_data;
struct k_work_delayable tx_timeout_work;
const uint8_t *tx_buf;
size_t tx_len;
struct k_work_delayable rx_timeout_work;
size_t rx_timeout_time;
size_t rx_timeout_chunk;
uint32_t rx_timeout_start;
uint8_t *rx_buf;
size_t rx_len;
size_t rx_processed_len;
uint8_t *rx_next_buf;
size_t rx_next_len;
bool rx_waiting_for_irq;
bool rx_timeout_from_isr;
#endif
};
static void wait_synchronization(SercomUsart *const usart)
{
#if defined(SERCOM_USART_SYNCBUSY_MASK)
/* SYNCBUSY is a register */
while ((usart->SYNCBUSY.reg & SERCOM_USART_SYNCBUSY_MASK) != 0) {
}
#elif defined(SERCOM_USART_STATUS_SYNCBUSY)
/* SYNCBUSY is a bit */
while ((usart->STATUS.reg & SERCOM_USART_STATUS_SYNCBUSY) != 0) {
}
#else
#error Unsupported device
#endif
}
static int uart_sam0_set_baudrate(SercomUsart *const usart, uint32_t baudrate,
uint32_t clk_freq_hz)
{
uint64_t tmp;
uint16_t baud;
tmp = (uint64_t)baudrate << 20;
tmp = (tmp + (clk_freq_hz >> 1)) / clk_freq_hz;
/* Verify that the calculated result is within range */
if (tmp < 1 || tmp > UINT16_MAX) {
return -ERANGE;
}
baud = 65536 - (uint16_t)tmp;
usart->BAUD.reg = baud;
wait_synchronization(usart);
return 0;
}
#if CONFIG_UART_SAM0_ASYNC
static void uart_sam0_dma_tx_done(const struct device *dma_dev, void *arg,
uint32_t id, int error_code)
{
ARG_UNUSED(dma_dev);
ARG_UNUSED(id);
ARG_UNUSED(error_code);
struct uart_sam0_dev_data *const dev_data =
(struct uart_sam0_dev_data *const) arg;
const struct uart_sam0_dev_cfg *const cfg = dev_data->cfg;
SercomUsart * const regs = cfg->regs;
regs->INTENSET.reg = SERCOM_USART_INTENSET_TXC;
}
static int uart_sam0_tx_halt(struct uart_sam0_dev_data *dev_data)
{
const struct uart_sam0_dev_cfg *const cfg = dev_data->cfg;
unsigned int key = irq_lock();
size_t tx_active = dev_data->tx_len;
struct dma_status st;
struct uart_event evt = {
.type = UART_TX_ABORTED,
.data.tx = {
.buf = dev_data->tx_buf,
.len = 0U,
},
};
dev_data->tx_buf = NULL;
dev_data->tx_len = 0U;
dma_stop(cfg->dma_dev, cfg->tx_dma_channel);
irq_unlock(key);
if (dma_get_status(cfg->dma_dev, cfg->tx_dma_channel, &st) == 0) {
evt.data.tx.len = tx_active - st.pending_length;
}
if (tx_active) {
if (dev_data->async_cb) {
dev_data->async_cb(dev_data->dev,
&evt, dev_data->async_cb_data);
}
} else {
return -EINVAL;
}
return 0;
}
static void uart_sam0_tx_timeout(struct k_work *work)
{
struct k_work_delayable *dwork = k_work_delayable_from_work(work);
struct uart_sam0_dev_data *dev_data = CONTAINER_OF(dwork,
struct uart_sam0_dev_data, tx_timeout_work);
uart_sam0_tx_halt(dev_data);
}
static void uart_sam0_notify_rx_processed(struct uart_sam0_dev_data *dev_data,
size_t processed)
{
if (!dev_data->async_cb) {
return;
}
if (dev_data->rx_processed_len == processed) {
return;
}
struct uart_event evt = {
.type = UART_RX_RDY,
.data.rx = {
.buf = dev_data->rx_buf,
.offset = dev_data->rx_processed_len,
.len = processed - dev_data->rx_processed_len,
},
};
dev_data->rx_processed_len = processed;
dev_data->async_cb(dev_data->dev,
&evt, dev_data->async_cb_data);
}
static void uart_sam0_dma_rx_done(const struct device *dma_dev, void *arg,
uint32_t id, int error_code)
{
ARG_UNUSED(dma_dev);
ARG_UNUSED(id);
ARG_UNUSED(error_code);
struct uart_sam0_dev_data *const dev_data =
(struct uart_sam0_dev_data *const)arg;
const struct device *dev = dev_data->dev;
const struct uart_sam0_dev_cfg *const cfg = dev_data->cfg;
SercomUsart * const regs = cfg->regs;
unsigned int key = irq_lock();
if (dev_data->rx_len == 0U) {
irq_unlock(key);
return;
}
uart_sam0_notify_rx_processed(dev_data, dev_data->rx_len);
if (dev_data->async_cb) {
struct uart_event evt = {
.type = UART_RX_BUF_RELEASED,
.data.rx_buf = {
.buf = dev_data->rx_buf,
},
};
dev_data->async_cb(dev, &evt, dev_data->async_cb_data);
}
/* No next buffer, so end the transfer */
if (!dev_data->rx_next_len) {
dev_data->rx_buf = NULL;
dev_data->rx_len = 0U;
if (dev_data->async_cb) {
struct uart_event evt = {
.type = UART_RX_DISABLED,
};
dev_data->async_cb(dev, &evt, dev_data->async_cb_data);
}
irq_unlock(key);
return;
}
dev_data->rx_buf = dev_data->rx_next_buf;
dev_data->rx_len = dev_data->rx_next_len;
dev_data->rx_next_buf = NULL;
dev_data->rx_next_len = 0U;
dev_data->rx_processed_len = 0U;
dma_reload(cfg->dma_dev, cfg->rx_dma_channel,
(uint32_t)(&(regs->DATA.reg)),
(uint32_t)dev_data->rx_buf, dev_data->rx_len);
/*
* If there should be a timeout, handle starting the DMA in the
* ISR, since reception resets it and DMA completion implies
* reception. This also catches the case of DMA completion during
* timeout handling.
*/
if (dev_data->rx_timeout_time != SYS_FOREVER_US) {
dev_data->rx_waiting_for_irq = true;
regs->INTENSET.reg = SERCOM_USART_INTENSET_RXC;
irq_unlock(key);
return;
}
/* Otherwise, start the transfer immediately. */
dma_start(cfg->dma_dev, cfg->rx_dma_channel);
struct uart_event evt = {
.type = UART_RX_BUF_REQUEST,
};
dev_data->async_cb(dev, &evt, dev_data->async_cb_data);
irq_unlock(key);
}
static void uart_sam0_rx_timeout(struct k_work *work)
{
struct k_work_delayable *dwork = k_work_delayable_from_work(work);
struct uart_sam0_dev_data *dev_data = CONTAINER_OF(dwork,
struct uart_sam0_dev_data, rx_timeout_work);
const struct uart_sam0_dev_cfg *const cfg = dev_data->cfg;
SercomUsart * const regs = cfg->regs;
struct dma_status st;
unsigned int key = irq_lock();
if (dev_data->rx_len == 0U) {
irq_unlock(key);
return;
}
/*
* Stop the DMA transfer and restart the interrupt read
* component (so the timeout restarts if there's still data).
* However, just ignore it if the transfer has completed (nothing
* pending) that means the DMA ISR is already pending, so just let
* it handle things instead when we re-enable IRQs.
*/
dma_stop(cfg->dma_dev, cfg->rx_dma_channel);
if (dma_get_status(cfg->dma_dev, cfg->rx_dma_channel,
&st) == 0 && st.pending_length == 0U) {
irq_unlock(key);
return;
}
uint8_t *rx_dma_start = dev_data->rx_buf + dev_data->rx_len -
st.pending_length;
size_t rx_processed = rx_dma_start - dev_data->rx_buf;
/*
* We know we still have space, since the above will catch the
* empty buffer, so always restart the transfer.
*/
dma_reload(cfg->dma_dev, cfg->rx_dma_channel,
(uint32_t)(&(regs->DATA.reg)),
(uint32_t)rx_dma_start,
dev_data->rx_len - rx_processed);
dev_data->rx_waiting_for_irq = true;
regs->INTENSET.reg = SERCOM_USART_INTENSET_RXC;
/*
* Never do a notify on a timeout started from the ISR: timing
* granularity means the first timeout can be in the middle
* of reception but still have the total elapsed time exhausted.
* So we require a timeout chunk with no data seen at all
* (i.e. no ISR entry).
*/
if (dev_data->rx_timeout_from_isr) {
dev_data->rx_timeout_from_isr = false;
k_work_reschedule(&dev_data->rx_timeout_work,
K_USEC(dev_data->rx_timeout_chunk));
irq_unlock(key);
return;
}
uint32_t now = k_uptime_get_32();
uint32_t elapsed = now - dev_data->rx_timeout_start;
if (elapsed >= dev_data->rx_timeout_time) {
/*
* No time left, so call the handler, and let the ISR
* restart the timeout when it sees data.
*/
uart_sam0_notify_rx_processed(dev_data, rx_processed);
} else {
/*
* Still have time left, so start another timeout.
*/
uint32_t remaining = MIN(dev_data->rx_timeout_time - elapsed,
dev_data->rx_timeout_chunk);
k_work_reschedule(&dev_data->rx_timeout_work,
K_USEC(remaining));
}
irq_unlock(key);
}
#endif
#ifdef CONFIG_UART_USE_RUNTIME_CONFIGURE
static int uart_sam0_configure(const struct device *dev,
const struct uart_config *new_cfg)
{
int retval;
const struct uart_sam0_dev_cfg *const cfg = dev->config;
struct uart_sam0_dev_data *const dev_data = dev->data;
SercomUsart * const usart = cfg->regs;
wait_synchronization(usart);
usart->CTRLA.bit.ENABLE = 0;
wait_synchronization(usart);
if (new_cfg->flow_ctrl != UART_CFG_FLOW_CTRL_NONE) {
/* Flow control not yet supported though in principle possible
* on this soc family.
*/
return -ENOTSUP;
}
dev_data->config_cache.flow_ctrl = new_cfg->flow_ctrl;
SERCOM_USART_CTRLA_Type CTRLA_temp = usart->CTRLA;
SERCOM_USART_CTRLB_Type CTRLB_temp = usart->CTRLB;
switch (new_cfg->parity) {
case UART_CFG_PARITY_NONE:
CTRLA_temp.bit.FORM = 0x0;
break;
case UART_CFG_PARITY_ODD:
CTRLA_temp.bit.FORM = 0x1;
CTRLB_temp.bit.PMODE = 1;
break;
case UART_CFG_PARITY_EVEN:
CTRLA_temp.bit.FORM = 0x1;
CTRLB_temp.bit.PMODE = 0;
break;
default:
return -ENOTSUP;
}
dev_data->config_cache.parity = new_cfg->parity;
switch (new_cfg->stop_bits) {
case UART_CFG_STOP_BITS_1:
CTRLB_temp.bit.SBMODE = 0;
break;
case UART_CFG_STOP_BITS_2:
CTRLB_temp.bit.SBMODE = 1;
break;
default:
return -ENOTSUP;
}
dev_data->config_cache.stop_bits = new_cfg->stop_bits;
switch (new_cfg->data_bits) {
case UART_CFG_DATA_BITS_5:
CTRLB_temp.bit.CHSIZE = 0x5;
break;
case UART_CFG_DATA_BITS_6:
CTRLB_temp.bit.CHSIZE = 0x6;
break;
case UART_CFG_DATA_BITS_7:
CTRLB_temp.bit.CHSIZE = 0x7;
break;
case UART_CFG_DATA_BITS_8:
CTRLB_temp.bit.CHSIZE = 0x0;
break;
case UART_CFG_DATA_BITS_9:
CTRLB_temp.bit.CHSIZE = 0x1;
break;
default:
return -ENOTSUP;
}
dev_data->config_cache.data_bits = new_cfg->data_bits;
#if defined(SERCOM_REV500)
CTRLB_temp.bit.COLDEN = cfg->pads;
#endif
usart->CTRLA = CTRLA_temp;
wait_synchronization(usart);
usart->CTRLB = CTRLB_temp;
wait_synchronization(usart);
retval = uart_sam0_set_baudrate(usart, new_cfg->baudrate,
SOC_ATMEL_SAM0_GCLK0_FREQ_HZ);
if (retval != 0) {
return retval;
}
dev_data->config_cache.baudrate = new_cfg->baudrate;
usart->CTRLA.bit.ENABLE = 1;
wait_synchronization(usart);
return 0;
}
static int uart_sam0_config_get(const struct device *dev,
struct uart_config *out_cfg)
{
struct uart_sam0_dev_data *const dev_data = dev->data;
memcpy(out_cfg, &(dev_data->config_cache),
sizeof(dev_data->config_cache));
return 0;
}
#endif /* CONFIG_UART_USE_RUNTIME_CONFIGURE */
static int uart_sam0_init(const struct device *dev)
{
int retval;
const struct uart_sam0_dev_cfg *const cfg = dev->config;
struct uart_sam0_dev_data *const dev_data = dev->data;
SercomUsart * const usart = cfg->regs;
#ifdef MCLK
/* Enable the GCLK */
GCLK->PCHCTRL[cfg->gclk_core_id].reg = GCLK_PCHCTRL_GEN_GCLK0 |
GCLK_PCHCTRL_CHEN;
/* Enable SERCOM clock in MCLK */
*cfg->mclk |= cfg->mclk_mask;
#else
/* Enable the GCLK */
GCLK->CLKCTRL.reg = cfg->gclk_clkctrl_id | GCLK_CLKCTRL_GEN_GCLK0 |
GCLK_CLKCTRL_CLKEN;
/* Enable SERCOM clock in PM */
PM->APBCMASK.reg |= cfg->pm_apbcmask;
#endif
/* Disable all USART interrupts */
usart->INTENCLR.reg = SERCOM_USART_INTENCLR_MASK;
wait_synchronization(usart);
/* 8 bits of data, no parity, 1 stop bit in normal mode */
usart->CTRLA.reg =
cfg->pads
/* Internal clock */
| SERCOM_USART_CTRLA_MODE_USART_INT_CLK
#if defined(SERCOM_USART_CTRLA_SAMPR)
/* 16x oversampling with arithmetic baud rate generation */
| SERCOM_USART_CTRLA_SAMPR(0)
#endif
| SERCOM_USART_CTRLA_FORM(0) |
SERCOM_USART_CTRLA_CPOL | SERCOM_USART_CTRLA_DORD;
wait_synchronization(usart);
/* Enable PINMUX based on PINCTRL */
retval = pinctrl_apply_state(cfg->pcfg, PINCTRL_STATE_DEFAULT);
if (retval < 0) {
return retval;
}
dev_data->config_cache.flow_ctrl = UART_CFG_FLOW_CTRL_NONE;
dev_data->config_cache.parity = UART_CFG_PARITY_NONE;
dev_data->config_cache.stop_bits = UART_CFG_STOP_BITS_1;
dev_data->config_cache.data_bits = UART_CFG_DATA_BITS_8;
/* Enable receiver and transmitter */
usart->CTRLB.reg = SERCOM_USART_CTRLB_CHSIZE(0) |
SERCOM_USART_CTRLB_RXEN | SERCOM_USART_CTRLB_TXEN;
wait_synchronization(usart);
retval = uart_sam0_set_baudrate(usart, cfg->baudrate,
SOC_ATMEL_SAM0_GCLK0_FREQ_HZ);
if (retval != 0) {
return retval;
}
dev_data->config_cache.baudrate = cfg->baudrate;
#if CONFIG_UART_INTERRUPT_DRIVEN || CONFIG_UART_SAM0_ASYNC
cfg->irq_config_func(dev);
#endif
#ifdef CONFIG_UART_SAM0_ASYNC
dev_data->dev = dev;
dev_data->cfg = cfg;
if (!device_is_ready(cfg->dma_dev)) {
return -ENODEV;
}
k_work_init_delayable(&dev_data->tx_timeout_work, uart_sam0_tx_timeout);
k_work_init_delayable(&dev_data->rx_timeout_work, uart_sam0_rx_timeout);
if (cfg->tx_dma_channel != 0xFFU) {
struct dma_config dma_cfg = { 0 };
struct dma_block_config dma_blk = { 0 };
dma_cfg.channel_direction = MEMORY_TO_PERIPHERAL;
dma_cfg.source_data_size = 1;
dma_cfg.dest_data_size = 1;
dma_cfg.user_data = dev_data;
dma_cfg.dma_callback = uart_sam0_dma_tx_done;
dma_cfg.block_count = 1;
dma_cfg.head_block = &dma_blk;
dma_cfg.dma_slot = cfg->tx_dma_request;
dma_blk.block_size = 1;
dma_blk.dest_address = (uint32_t)(&(usart->DATA.reg));
dma_blk.dest_addr_adj = DMA_ADDR_ADJ_NO_CHANGE;
retval = dma_config(cfg->dma_dev, cfg->tx_dma_channel,
&dma_cfg);
if (retval != 0) {
return retval;
}
}
if (cfg->rx_dma_channel != 0xFFU) {
struct dma_config dma_cfg = { 0 };
struct dma_block_config dma_blk = { 0 };
dma_cfg.channel_direction = PERIPHERAL_TO_MEMORY;
dma_cfg.source_data_size = 1;
dma_cfg.dest_data_size = 1;
dma_cfg.user_data = dev_data;
dma_cfg.dma_callback = uart_sam0_dma_rx_done;
dma_cfg.block_count = 1;
dma_cfg.head_block = &dma_blk;
dma_cfg.dma_slot = cfg->rx_dma_request;
dma_blk.block_size = 1;
dma_blk.source_address = (uint32_t)(&(usart->DATA.reg));
dma_blk.source_addr_adj = DMA_ADDR_ADJ_NO_CHANGE;
retval = dma_config(cfg->dma_dev, cfg->rx_dma_channel,
&dma_cfg);
if (retval != 0) {
return retval;
}
}
#endif
usart->CTRLA.bit.ENABLE = 1;
wait_synchronization(usart);
return 0;
}
static int uart_sam0_poll_in(const struct device *dev, unsigned char *c)
{
const struct uart_sam0_dev_cfg *config = dev->config;
SercomUsart * const usart = config->regs;
if (!usart->INTFLAG.bit.RXC) {
return -EBUSY;
}
*c = (unsigned char)usart->DATA.reg;
return 0;
}
static void uart_sam0_poll_out(const struct device *dev, unsigned char c)
{
const struct uart_sam0_dev_cfg *config = dev->config;
SercomUsart * const usart = config->regs;
while (!usart->INTFLAG.bit.DRE) {
}
/* send a character */
usart->DATA.reg = c;
}
static int uart_sam0_err_check(const struct device *dev)
{
const struct uart_sam0_dev_cfg *config = dev->config;
SercomUsart * const regs = config->regs;
uint32_t err = 0U;
if (regs->STATUS.reg & SERCOM_USART_STATUS_BUFOVF) {
err |= UART_ERROR_OVERRUN;
}
if (regs->STATUS.reg & SERCOM_USART_STATUS_FERR) {
err |= UART_ERROR_PARITY;
}
if (regs->STATUS.reg & SERCOM_USART_STATUS_PERR) {
err |= UART_ERROR_FRAMING;
}
#if defined(SERCOM_REV500)
if (regs->STATUS.reg & SERCOM_USART_STATUS_ISF) {
err |= UART_BREAK;
}
if (regs->STATUS.reg & SERCOM_USART_STATUS_COLL) {
err |= UART_ERROR_COLLISION;
}
regs->STATUS.reg |= SERCOM_USART_STATUS_BUFOVF
| SERCOM_USART_STATUS_FERR
| SERCOM_USART_STATUS_PERR
| SERCOM_USART_STATUS_COLL
| SERCOM_USART_STATUS_ISF;
#else
regs->STATUS.reg |= SERCOM_USART_STATUS_BUFOVF
| SERCOM_USART_STATUS_FERR
| SERCOM_USART_STATUS_PERR;
#endif
wait_synchronization(regs);
return err;
}
#if CONFIG_UART_INTERRUPT_DRIVEN || CONFIG_UART_SAM0_ASYNC
static void uart_sam0_isr(const struct device *dev)
{
struct uart_sam0_dev_data *const dev_data = dev->data;
#if CONFIG_UART_INTERRUPT_DRIVEN
if (dev_data->cb) {
dev_data->cb(dev, dev_data->cb_data);
}
#endif
#if CONFIG_UART_SAM0_ASYNC
const struct uart_sam0_dev_cfg *const cfg = dev->config;
SercomUsart * const regs = cfg->regs;
if (dev_data->tx_len && regs->INTFLAG.bit.TXC) {
regs->INTENCLR.reg = SERCOM_USART_INTENCLR_TXC;
k_work_cancel_delayable(&dev_data->tx_timeout_work);
unsigned int key = irq_lock();
struct uart_event evt = {
.type = UART_TX_DONE,
.data.tx = {
.buf = dev_data->tx_buf,
.len = dev_data->tx_len,
},
};
dev_data->tx_buf = NULL;
dev_data->tx_len = 0U;
if (evt.data.tx.len != 0U && dev_data->async_cb) {
dev_data->async_cb(dev, &evt, dev_data->async_cb_data);
}
irq_unlock(key);
}
if (dev_data->rx_len && regs->INTFLAG.bit.RXC &&
dev_data->rx_waiting_for_irq) {
dev_data->rx_waiting_for_irq = false;
regs->INTENCLR.reg = SERCOM_USART_INTENCLR_RXC;
/* Receive started, so request the next buffer */
if (dev_data->rx_next_len == 0U && dev_data->async_cb) {
struct uart_event evt = {
.type = UART_RX_BUF_REQUEST,
};
dev_data->async_cb(dev, &evt, dev_data->async_cb_data);
}
/*
* If we have a timeout, restart the time remaining whenever
* we see data.
*/
if (dev_data->rx_timeout_time != SYS_FOREVER_US) {
dev_data->rx_timeout_from_isr = true;
dev_data->rx_timeout_start = k_uptime_get_32();
k_work_reschedule(&dev_data->rx_timeout_work,
K_USEC(dev_data->rx_timeout_chunk));
}
/* DMA will read the currently ready byte out */
dma_start(cfg->dma_dev, cfg->rx_dma_channel);
}
#endif
}
#endif
#if CONFIG_UART_INTERRUPT_DRIVEN
static int uart_sam0_fifo_fill(const struct device *dev,
const uint8_t *tx_data, int len)
{
const struct uart_sam0_dev_cfg *config = dev->config;
SercomUsart *regs = config->regs;
if (regs->INTFLAG.bit.DRE && len >= 1) {
regs->DATA.reg = tx_data[0];
return 1;
} else {
return 0;
}
}
static void uart_sam0_irq_tx_enable(const struct device *dev)
{
const struct uart_sam0_dev_cfg *config = dev->config;
SercomUsart * const regs = config->regs;
regs->INTENSET.reg = SERCOM_USART_INTENSET_DRE
| SERCOM_USART_INTENSET_TXC;
}
static void uart_sam0_irq_tx_disable(const struct device *dev)
{
const struct uart_sam0_dev_cfg *config = dev->config;
SercomUsart * const regs = config->regs;
regs->INTENCLR.reg = SERCOM_USART_INTENCLR_DRE
| SERCOM_USART_INTENCLR_TXC;
}
static int uart_sam0_irq_tx_ready(const struct device *dev)
{
const struct uart_sam0_dev_cfg *config = dev->config;
SercomUsart * const regs = config->regs;
return (regs->INTFLAG.bit.DRE != 0) && (regs->INTENSET.bit.DRE != 0);
}
static int uart_sam0_irq_tx_complete(const struct device *dev)
{
const struct uart_sam0_dev_cfg *config = dev->config;
struct uart_sam0_dev_data *const dev_data = dev->data;
SercomUsart * const regs = config->regs;
return (dev_data->txc_cache != 0) && (regs->INTENSET.bit.TXC != 0);
}
static void uart_sam0_irq_rx_enable(const struct device *dev)
{
const struct uart_sam0_dev_cfg *config = dev->config;
SercomUsart * const regs = config->regs;
regs->INTENSET.reg = SERCOM_USART_INTENSET_RXC;
}
static void uart_sam0_irq_rx_disable(const struct device *dev)
{
const struct uart_sam0_dev_cfg *config = dev->config;
SercomUsart * const regs = config->regs;
regs->INTENCLR.reg = SERCOM_USART_INTENCLR_RXC;
}
static int uart_sam0_irq_rx_ready(const struct device *dev)
{
const struct uart_sam0_dev_cfg *config = dev->config;
SercomUsart * const regs = config->regs;
return regs->INTFLAG.bit.RXC != 0;
}
static int uart_sam0_fifo_read(const struct device *dev, uint8_t *rx_data,
const int size)
{
const struct uart_sam0_dev_cfg *config = dev->config;
SercomUsart * const regs = config->regs;
if (regs->INTFLAG.bit.RXC) {
uint8_t ch = regs->DATA.reg;
if (size >= 1) {
*rx_data = ch;
return 1;
} else {
return -EINVAL;
}
}
return 0;
}
static int uart_sam0_irq_is_pending(const struct device *dev)
{
const struct uart_sam0_dev_cfg *config = dev->config;
SercomUsart * const regs = config->regs;
return (regs->INTENSET.reg & regs->INTFLAG.reg) != 0;
}
#if defined(SERCOM_REV500)
static void uart_sam0_irq_err_enable(const struct device *dev)
{
const struct uart_sam0_dev_cfg *config = dev->config;
SercomUsart * const regs = config->regs;
regs->INTENSET.reg |= SERCOM_USART_INTENCLR_ERROR;
wait_synchronization(regs);
}
static void uart_sam0_irq_err_disable(const struct device *dev)
{
const struct uart_sam0_dev_cfg *config = dev->config;
SercomUsart * const regs = config->regs;
regs->INTENCLR.reg |= SERCOM_USART_INTENSET_ERROR;
wait_synchronization(regs);
}
#endif
static int uart_sam0_irq_update(const struct device *dev)
{
/* Clear sticky interrupts */
const struct uart_sam0_dev_cfg *config = dev->config;
SercomUsart * const regs = config->regs;
#if defined(SERCOM_REV500)
/*
* Cache the TXC flag, and use this cached value to clear the interrupt
* if we do not used the cached value, there is a chance TXC will set
* after caching...this will cause TXC to never cached.
*/
struct uart_sam0_dev_data *const dev_data = dev->data;
dev_data->txc_cache = regs->INTFLAG.bit.TXC;
regs->INTFLAG.reg = SERCOM_USART_INTENCLR_ERROR
| SERCOM_USART_INTENCLR_RXBRK
| SERCOM_USART_INTENCLR_CTSIC
| SERCOM_USART_INTENCLR_RXS
| (dev_data->txc_cache << SERCOM_USART_INTENCLR_TXC_Pos);
#else
regs->INTFLAG.reg = SERCOM_USART_INTENCLR_RXS;
#endif
return 1;
}
static void uart_sam0_irq_callback_set(const struct device *dev,
uart_irq_callback_user_data_t cb,
void *cb_data)
{
struct uart_sam0_dev_data *const dev_data = dev->data;
dev_data->cb = cb;
dev_data->cb_data = cb_data;
#if defined(CONFIG_UART_SAM0_ASYNC) && defined(CONFIG_UART_EXCLUSIVE_API_CALLBACKS)
dev_data->async_cb = NULL;
dev_data->async_cb_data = NULL;
#endif
}
#endif
#ifdef CONFIG_UART_SAM0_ASYNC
static int uart_sam0_callback_set(const struct device *dev,
uart_callback_t callback,
void *user_data)
{
struct uart_sam0_dev_data *const dev_data = dev->data;
dev_data->async_cb = callback;
dev_data->async_cb_data = user_data;
#if defined(CONFIG_UART_EXCLUSIVE_API_CALLBACKS)
dev_data->cb = NULL;
dev_data->cb_data = NULL;
#endif
return 0;
}
static int uart_sam0_tx(const struct device *dev, const uint8_t *buf,
size_t len,
int32_t timeout)
{
struct uart_sam0_dev_data *const dev_data = dev->data;
const struct uart_sam0_dev_cfg *const cfg = dev->config;
SercomUsart *regs = cfg->regs;
int retval;
if (cfg->tx_dma_channel == 0xFFU) {
return -ENOTSUP;
}
if (len > 0xFFFFU) {
return -EINVAL;
}
unsigned int key = irq_lock();
if (dev_data->tx_len != 0U) {
retval = -EBUSY;
goto err;
}
dev_data->tx_buf = buf;
dev_data->tx_len = len;
irq_unlock(key);
retval = dma_reload(cfg->dma_dev, cfg->tx_dma_channel, (uint32_t)buf,
(uint32_t)(&(regs->DATA.reg)), len);
if (retval != 0U) {
return retval;
}
if (timeout != SYS_FOREVER_US) {
k_work_reschedule(&dev_data->tx_timeout_work,
K_USEC(timeout));
}
return dma_start(cfg->dma_dev, cfg->tx_dma_channel);
err:
irq_unlock(key);
return retval;
}
static int uart_sam0_tx_abort(const struct device *dev)
{
struct uart_sam0_dev_data *const dev_data = dev->data;
const struct uart_sam0_dev_cfg *const cfg = dev->config;
if (cfg->tx_dma_channel == 0xFFU) {
return -ENOTSUP;
}
k_work_cancel_delayable(&dev_data->tx_timeout_work);
return uart_sam0_tx_halt(dev_data);
}
static int uart_sam0_rx_enable(const struct device *dev, uint8_t *buf,
size_t len,
int32_t timeout)
{
struct uart_sam0_dev_data *const dev_data = dev->data;
const struct uart_sam0_dev_cfg *const cfg = dev->config;
SercomUsart *regs = cfg->regs;
int retval;
if (cfg->rx_dma_channel == 0xFFU) {
return -ENOTSUP;
}
if (len > 0xFFFFU) {
return -EINVAL;
}
unsigned int key = irq_lock();
if (dev_data->rx_len != 0U) {
retval = -EBUSY;
goto err;
}
/* Read off anything that was already there */
while (regs->INTFLAG.bit.RXC) {
char discard = regs->DATA.reg;
(void)discard;
}
retval = dma_reload(cfg->dma_dev, cfg->rx_dma_channel,
(uint32_t)(&(regs->DATA.reg)),
(uint32_t)buf, len);
if (retval != 0) {
return retval;
}
dev_data->rx_buf = buf;
dev_data->rx_len = len;
dev_data->rx_processed_len = 0U;
dev_data->rx_waiting_for_irq = true;
dev_data->rx_timeout_from_isr = true;
dev_data->rx_timeout_time = timeout;
dev_data->rx_timeout_chunk = MAX(timeout / 4U, 1);
regs->INTENSET.reg = SERCOM_USART_INTENSET_RXC;
irq_unlock(key);
return 0;
err:
irq_unlock(key);
return retval;
}
static int uart_sam0_rx_buf_rsp(const struct device *dev, uint8_t *buf,
size_t len)
{
if (len > 0xFFFFU) {
return -EINVAL;
}
struct uart_sam0_dev_data *const dev_data = dev->data;
unsigned int key = irq_lock();
int retval = 0;
if (dev_data->rx_len == 0U) {
retval = -EACCES;
goto err;
}
if (dev_data->rx_next_len != 0U) {
retval = -EBUSY;
goto err;
}
dev_data->rx_next_buf = buf;
dev_data->rx_next_len = len;
irq_unlock(key);
return 0;
err:
irq_unlock(key);
return retval;
}
static int uart_sam0_rx_disable(const struct device *dev)
{
struct uart_sam0_dev_data *const dev_data = dev->data;
const struct uart_sam0_dev_cfg *const cfg = dev->config;
SercomUsart * const regs = cfg->regs;
struct dma_status st;
k_work_cancel_delayable(&dev_data->rx_timeout_work);
unsigned int key = irq_lock();
if (dev_data->rx_len == 0U) {
irq_unlock(key);
return -EINVAL;
}
regs->INTENCLR.reg = SERCOM_USART_INTENCLR_RXC;
dma_stop(cfg->dma_dev, cfg->rx_dma_channel);
if (dma_get_status(cfg->dma_dev, cfg->rx_dma_channel,
&st) == 0 && st.pending_length != 0U) {
size_t rx_processed = dev_data->rx_len - st.pending_length;
uart_sam0_notify_rx_processed(dev_data, rx_processed);
}
struct uart_event evt = {
.type = UART_RX_BUF_RELEASED,
.data.rx_buf = {
.buf = dev_data->rx_buf,
},
};
dev_data->rx_buf = NULL;
dev_data->rx_len = 0U;
if (dev_data->async_cb) {
dev_data->async_cb(dev, &evt, dev_data->async_cb_data);
}
if (dev_data->rx_next_len) {
struct uart_event next_evt = {
.type = UART_RX_BUF_RELEASED,
.data.rx_buf = {
.buf = dev_data->rx_next_buf,
},
};
dev_data->rx_next_buf = NULL;
dev_data->rx_next_len = 0U;
if (dev_data->async_cb) {
dev_data->async_cb(dev, &next_evt, dev_data->async_cb_data);
}
}
evt.type = UART_RX_DISABLED;
if (dev_data->async_cb) {
dev_data->async_cb(dev, &evt, dev_data->async_cb_data);
}
irq_unlock(key);
return 0;
}
#endif
static const struct uart_driver_api uart_sam0_driver_api = {
.poll_in = uart_sam0_poll_in,
.poll_out = uart_sam0_poll_out,
#ifdef CONFIG_UART_USE_RUNTIME_CONFIGURE
.configure = uart_sam0_configure,
.config_get = uart_sam0_config_get,
#endif
.err_check = uart_sam0_err_check,
#if CONFIG_UART_INTERRUPT_DRIVEN
.fifo_fill = uart_sam0_fifo_fill,
.fifo_read = uart_sam0_fifo_read,
.irq_tx_enable = uart_sam0_irq_tx_enable,
.irq_tx_disable = uart_sam0_irq_tx_disable,
.irq_tx_ready = uart_sam0_irq_tx_ready,
.irq_tx_complete = uart_sam0_irq_tx_complete,
.irq_rx_enable = uart_sam0_irq_rx_enable,
.irq_rx_disable = uart_sam0_irq_rx_disable,
.irq_rx_ready = uart_sam0_irq_rx_ready,
.irq_is_pending = uart_sam0_irq_is_pending,
#if defined(SERCOM_REV500)
.irq_err_enable = uart_sam0_irq_err_enable,
.irq_err_disable = uart_sam0_irq_err_disable,
#endif
.irq_update = uart_sam0_irq_update,
.irq_callback_set = uart_sam0_irq_callback_set,
#endif
#if CONFIG_UART_SAM0_ASYNC
.callback_set = uart_sam0_callback_set,
.tx = uart_sam0_tx,
.tx_abort = uart_sam0_tx_abort,
.rx_enable = uart_sam0_rx_enable,
.rx_buf_rsp = uart_sam0_rx_buf_rsp,
.rx_disable = uart_sam0_rx_disable,
#endif
};
#if CONFIG_UART_INTERRUPT_DRIVEN || CONFIG_UART_SAM0_ASYNC
#define SAM0_UART_IRQ_CONNECT(n, m) \
do { \
IRQ_CONNECT(DT_INST_IRQ_BY_IDX(n, m, irq), \
DT_INST_IRQ_BY_IDX(n, m, priority), \
uart_sam0_isr, \
DEVICE_DT_INST_GET(n), 0); \
irq_enable(DT_INST_IRQ_BY_IDX(n, m, irq)); \
} while (false)
#define UART_SAM0_IRQ_HANDLER_DECL(n) \
static void uart_sam0_irq_config_##n(const struct device *dev)
#define UART_SAM0_IRQ_HANDLER_FUNC(n) \
.irq_config_func = uart_sam0_irq_config_##n,
#if DT_INST_IRQ_HAS_IDX(0, 3)
#define UART_SAM0_IRQ_HANDLER(n) \
static void uart_sam0_irq_config_##n(const struct device *dev) \
{ \
SAM0_UART_IRQ_CONNECT(n, 0); \
SAM0_UART_IRQ_CONNECT(n, 1); \
SAM0_UART_IRQ_CONNECT(n, 2); \
SAM0_UART_IRQ_CONNECT(n, 3); \
}
#else
#define UART_SAM0_IRQ_HANDLER(n) \
static void uart_sam0_irq_config_##n(const struct device *dev) \
{ \
SAM0_UART_IRQ_CONNECT(n, 0); \
}
#endif
#else
#define UART_SAM0_IRQ_HANDLER_DECL(n)
#define UART_SAM0_IRQ_HANDLER_FUNC(n)
#define UART_SAM0_IRQ_HANDLER(n)
#endif
#if CONFIG_UART_SAM0_ASYNC
#define UART_SAM0_DMA_CHANNELS(n) \
.dma_dev = DEVICE_DT_GET(ATMEL_SAM0_DT_INST_DMA_CTLR(n, tx)), \
.tx_dma_request = ATMEL_SAM0_DT_INST_DMA_TRIGSRC(n, tx), \
.tx_dma_channel = ATMEL_SAM0_DT_INST_DMA_CHANNEL(n, tx), \
.rx_dma_request = ATMEL_SAM0_DT_INST_DMA_TRIGSRC(n, rx), \
.rx_dma_channel = ATMEL_SAM0_DT_INST_DMA_CHANNEL(n, rx),
#else
#define UART_SAM0_DMA_CHANNELS(n)
#endif
#define UART_SAM0_SERCOM_PADS(n) \
(DT_INST_PROP(n, rxpo) << SERCOM_USART_CTRLA_RXPO_Pos) | \
(DT_INST_PROP(n, txpo) << SERCOM_USART_CTRLA_TXPO_Pos)
#define UART_SAM0_SERCOM_COLLISION_DETECT(n) \
(DT_INST_PROP(n, collision_detection))
#ifdef MCLK
#define UART_SAM0_CONFIG_DEFN(n) \
static const struct uart_sam0_dev_cfg uart_sam0_config_##n = { \
.regs = (SercomUsart *)DT_INST_REG_ADDR(n), \
.baudrate = DT_INST_PROP(n, current_speed), \
.mclk = (volatile uint32_t *)MCLK_MASK_DT_INT_REG_ADDR(n), \
.mclk_mask = BIT(DT_INST_CLOCKS_CELL_BY_NAME(n, mclk, bit)), \
.gclk_core_id = DT_INST_CLOCKS_CELL_BY_NAME(n, gclk, periph_ch),\
.pads = UART_SAM0_SERCOM_PADS(n), \
.collision_detect = UART_SAM0_SERCOM_COLLISION_DETECT(n), \
.pcfg = PINCTRL_DT_INST_DEV_CONFIG_GET(n), \
UART_SAM0_IRQ_HANDLER_FUNC(n) \
UART_SAM0_DMA_CHANNELS(n) \
}
#else
#define UART_SAM0_CONFIG_DEFN(n) \
static const struct uart_sam0_dev_cfg uart_sam0_config_##n = { \
.regs = (SercomUsart *)DT_INST_REG_ADDR(n), \
.baudrate = DT_INST_PROP(n, current_speed), \
.pm_apbcmask = BIT(DT_INST_CLOCKS_CELL_BY_NAME(n, pm, bit)), \
.gclk_clkctrl_id = DT_INST_CLOCKS_CELL_BY_NAME(n, gclk, clkctrl_id),\
.pads = UART_SAM0_SERCOM_PADS(n), \
.collision_detect = UART_SAM0_SERCOM_COLLISION_DETECT(n), \
.pcfg = PINCTRL_DT_INST_DEV_CONFIG_GET(n), \
UART_SAM0_IRQ_HANDLER_FUNC(n) \
UART_SAM0_DMA_CHANNELS(n) \
}
#endif
#define UART_SAM0_DEVICE_INIT(n) \
PINCTRL_DT_INST_DEFINE(n); \
static struct uart_sam0_dev_data uart_sam0_data_##n; \
UART_SAM0_IRQ_HANDLER_DECL(n); \
UART_SAM0_CONFIG_DEFN(n); \
DEVICE_DT_INST_DEFINE(n, uart_sam0_init, NULL, \
&uart_sam0_data_##n, \
&uart_sam0_config_##n, PRE_KERNEL_1, \
CONFIG_SERIAL_INIT_PRIORITY, \
&uart_sam0_driver_api); \
UART_SAM0_IRQ_HANDLER(n)
DT_INST_FOREACH_STATUS_OKAY(UART_SAM0_DEVICE_INIT)
``` | /content/code_sandbox/drivers/serial/uart_sam0.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 9,813 |
```unknown
config UART_NATIVE_POSIX
bool "UART driver for native_sim/posix"
default y
depends on DT_HAS_ZEPHYR_NATIVE_POSIX_UART_ENABLED
select SERIAL_HAS_DRIVER
help
This enables a UART driver for the POSIX ARCH with up to 2 UARTs.
For the first UART port, the driver can be configured
to either connect to the terminal from which the executable was run, or into
one dedicated pseudoterminal for that UART.
if UART_NATIVE_POSIX
choice NATIVE_UART_0
prompt "Native UART Port 0 connection"
default NATIVE_UART_0_ON_OWN_PTY
config NATIVE_UART_0_ON_OWN_PTY
bool "Connect the UART to its own pseudo terminal"
help
Connect this UART to its own pseudoterminal. This is the preferred
option for users who want to use Zephyr's shell.
Moreover this option does not conflict with any other native
backend which may use the invoking shell standard input/output.
config NATIVE_UART_0_ON_STDINOUT
bool "Connect the UART to the invoking shell stdin/stdout"
help
Connect this UART to the stdin & stdout of the calling shell/terminal
which invoked the native executable. This is good enough for
automated testing, or when feeding from a file/pipe.
Note that other, non UART messages, will also be printed to the
terminal.
It is strongly discouraged to try to use this option with the new
shell interactively, as the default terminal configuration is NOT
appropriate for interactive use.
endchoice
config UART_NATIVE_WAIT_PTS_READY_ENABLE
bool "Support waiting for pseudo terminal client readiness"
depends on NATIVE_UART_0_ON_OWN_PTY || UART_NATIVE_POSIX_PORT_1_ENABLE
help
When this option is selected a new command line switch is provided:
``--wait_uart``
When ``--wait_uart`` is used, writes to the UART will be held until a
client has connected to the slave side of the pseudoterminal.
Otherwise writes are sent irrespectively.
config UART_NATIVE_POSIX_PORT_1_ENABLE
bool "Second UART port"
help
Useful if you need to have another serial connection to host.
This is used for example in PPP (Point-to-Point Protocol)
implementation.
config NATIVE_UART_AUTOATTACH_DEFAULT_CMD
string "Default command to attach the UART to a new terminal"
default "xterm -e screen %s &"
help
If the native executable is called with the --attach_uart
command line option, this will be the default command which will be
run to attach a new terminal to the 1st UART.
Note that this command must have one, and only one, '%s' as
placeholder for the pseudoterminal device name (e.g. /dev/pts/35)
This is only applicable if the UART_0 is configured to use its own
PTY with NATIVE_UART_0_ON_OWN_PTY.
The 2nd UART will not be affected by this option.
If you are using GNOME, then you can use this command string
'gnome-terminal -- screen %s'
endif # UART_NATIVE_POSIX
``` | /content/code_sandbox/drivers/serial/Kconfig.native_posix | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 693 |
```unknown
# NEORV32 UART configuration
config UART_NEORV32
bool "NEORV32 UART"
default y
depends on DT_HAS_NEORV32_UART_ENABLED
depends on SYSCON
select SERIAL_HAS_DRIVER
select SERIAL_SUPPORT_INTERRUPT
help
This option enables the UART driver for the NEORV32.
``` | /content/code_sandbox/drivers/serial/Kconfig.neorv32 | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 72 |
```c
/*
*
*/
/**
* @brief UART driver for the SiFive Freedom Processor
*/
#define DT_DRV_COMPAT sifive_uart0
#include <zephyr/kernel.h>
#include <zephyr/arch/cpu.h>
#include <zephyr/drivers/uart.h>
#include <zephyr/drivers/pinctrl.h>
#include <soc.h>
#include <zephyr/irq.h>
#define RXDATA_EMPTY (1 << 31) /* Receive FIFO Empty */
#define RXDATA_MASK 0xFF /* Receive Data Mask */
#define TXDATA_FULL (1 << 31) /* Transmit FIFO Full */
#define TXCTRL_TXEN (1 << 0) /* Activate Tx Channel */
#define RXCTRL_RXEN (1 << 0) /* Activate Rx Channel */
#define IE_TXWM (1 << 0) /* TX Interrupt Enable/Pending */
#define IE_RXWM (1 << 1) /* RX Interrupt Enable/Pending */
/*
* RX/TX Threshold count to generate TX/RX Interrupts.
* Used by txctrl and rxctrl registers
*/
#define CTRL_CNT(x) (((x) & 0x07) << 16)
struct uart_sifive_regs_t {
uint32_t tx;
uint32_t rx;
uint32_t txctrl;
uint32_t rxctrl;
uint32_t ie;
uint32_t ip;
uint32_t div;
};
#ifdef CONFIG_UART_INTERRUPT_DRIVEN
typedef void (*irq_cfg_func_t)(void);
#endif
struct uart_sifive_device_config {
uintptr_t port;
uint32_t sys_clk_freq;
uint32_t baud_rate;
uint32_t rxcnt_irq;
uint32_t txcnt_irq;
const struct pinctrl_dev_config *pcfg;
#ifdef CONFIG_UART_INTERRUPT_DRIVEN
irq_cfg_func_t cfg_func;
#endif
};
struct uart_sifive_data {
#ifdef CONFIG_UART_INTERRUPT_DRIVEN
uart_irq_callback_user_data_t callback;
void *cb_data;
#endif
};
#define DEV_UART(dev) \
((struct uart_sifive_regs_t *) \
((const struct uart_sifive_device_config * const)(dev)->config)->port)
/**
* @brief Output a character in polled mode.
*
* Writes data to tx register if transmitter is not full.
*
* @param dev UART device struct
* @param c Character to send
*/
static void uart_sifive_poll_out(const struct device *dev,
unsigned char c)
{
volatile struct uart_sifive_regs_t *uart = DEV_UART(dev);
/* Wait while TX FIFO is full */
while (uart->tx & TXDATA_FULL) {
}
uart->tx = (int)c;
}
/**
* @brief Poll the device for input.
*
* @param dev UART device struct
* @param c Pointer to character
*
* @return 0 if a character arrived, -1 if the input buffer if empty.
*/
static int uart_sifive_poll_in(const struct device *dev, unsigned char *c)
{
volatile struct uart_sifive_regs_t *uart = DEV_UART(dev);
uint32_t val = uart->rx;
if (val & RXDATA_EMPTY) {
return -1;
}
*c = (unsigned char)(val & RXDATA_MASK);
return 0;
}
#ifdef CONFIG_UART_INTERRUPT_DRIVEN
/**
* @brief Fill FIFO with data
*
* @param dev UART device struct
* @param tx_data Data to transmit
* @param size Number of bytes to send
*
* @return Number of bytes sent
*/
static int uart_sifive_fifo_fill(const struct device *dev,
const uint8_t *tx_data,
int size)
{
volatile struct uart_sifive_regs_t *uart = DEV_UART(dev);
int i;
for (i = 0; i < size && !(uart->tx & TXDATA_FULL); i++)
uart->tx = (int)tx_data[i];
return i;
}
/**
* @brief Read data from FIFO
*
* @param dev UART device struct
* @param rxData Data container
* @param size Container size
*
* @return Number of bytes read
*/
static int uart_sifive_fifo_read(const struct device *dev,
uint8_t *rx_data,
const int size)
{
volatile struct uart_sifive_regs_t *uart = DEV_UART(dev);
int i;
uint32_t val;
for (i = 0; i < size; i++) {
val = uart->rx;
if (val & RXDATA_EMPTY)
break;
rx_data[i] = (uint8_t)(val & RXDATA_MASK);
}
return i;
}
/**
* @brief Enable TX interrupt in ie register
*
* @param dev UART device struct
*/
static void uart_sifive_irq_tx_enable(const struct device *dev)
{
volatile struct uart_sifive_regs_t *uart = DEV_UART(dev);
uart->ie |= IE_TXWM;
}
/**
* @brief Disable TX interrupt in ie register
*
* @param dev UART device struct
*/
static void uart_sifive_irq_tx_disable(const struct device *dev)
{
volatile struct uart_sifive_regs_t *uart = DEV_UART(dev);
uart->ie &= ~IE_TXWM;
}
/**
* @brief Check if Tx IRQ has been raised
*
* @param dev UART device struct
*
* @return 1 if an IRQ is ready, 0 otherwise
*/
static int uart_sifive_irq_tx_ready(const struct device *dev)
{
volatile struct uart_sifive_regs_t *uart = DEV_UART(dev);
return !!(uart->ip & IE_TXWM);
}
/**
* @brief Check if nothing remains to be transmitted
*
* @param dev UART device struct
*
* @return 1 if nothing remains to be transmitted, 0 otherwise
*/
static int uart_sifive_irq_tx_complete(const struct device *dev)
{
volatile struct uart_sifive_regs_t *uart = DEV_UART(dev);
/*
* No TX EMPTY flag for this controller,
* just check if TX FIFO is not full
*/
return !(uart->tx & TXDATA_FULL);
}
/**
* @brief Enable RX interrupt in ie register
*
* @param dev UART device struct
*/
static void uart_sifive_irq_rx_enable(const struct device *dev)
{
volatile struct uart_sifive_regs_t *uart = DEV_UART(dev);
uart->ie |= IE_RXWM;
}
/**
* @brief Disable RX interrupt in ie register
*
* @param dev UART device struct
*/
static void uart_sifive_irq_rx_disable(const struct device *dev)
{
volatile struct uart_sifive_regs_t *uart = DEV_UART(dev);
uart->ie &= ~IE_RXWM;
}
/**
* @brief Check if Rx IRQ has been raised
*
* @param dev UART device struct
*
* @return 1 if an IRQ is ready, 0 otherwise
*/
static int uart_sifive_irq_rx_ready(const struct device *dev)
{
volatile struct uart_sifive_regs_t *uart = DEV_UART(dev);
return !!(uart->ip & IE_RXWM);
}
/* No error interrupt for this controller */
static void uart_sifive_irq_err_enable(const struct device *dev)
{
ARG_UNUSED(dev);
}
static void uart_sifive_irq_err_disable(const struct device *dev)
{
ARG_UNUSED(dev);
}
/**
* @brief Check if any IRQ is pending
*
* @param dev UART device struct
*
* @return 1 if an IRQ is pending, 0 otherwise
*/
static int uart_sifive_irq_is_pending(const struct device *dev)
{
volatile struct uart_sifive_regs_t *uart = DEV_UART(dev);
return !!(uart->ip & (IE_RXWM | IE_TXWM));
}
static int uart_sifive_irq_update(const struct device *dev)
{
return 1;
}
/**
* @brief Set the callback function pointer for IRQ.
*
* @param dev UART device struct
* @param cb Callback function pointer.
*/
static void uart_sifive_irq_callback_set(const struct device *dev,
uart_irq_callback_user_data_t cb,
void *cb_data)
{
struct uart_sifive_data *data = dev->data;
data->callback = cb;
data->cb_data = cb_data;
}
static void uart_sifive_irq_handler(const struct device *dev)
{
struct uart_sifive_data *data = dev->data;
if (data->callback)
data->callback(dev, data->cb_data);
}
#endif /* CONFIG_UART_INTERRUPT_DRIVEN */
static int uart_sifive_init(const struct device *dev)
{
const struct uart_sifive_device_config * const cfg = dev->config;
volatile struct uart_sifive_regs_t *uart = DEV_UART(dev);
#ifdef CONFIG_PINCTRL
int ret;
#endif
/* Enable TX and RX channels */
uart->txctrl = TXCTRL_TXEN | CTRL_CNT(cfg->txcnt_irq);
uart->rxctrl = RXCTRL_RXEN | CTRL_CNT(cfg->rxcnt_irq);
/* Set baud rate */
uart->div = cfg->sys_clk_freq / cfg->baud_rate - 1;
#ifdef CONFIG_UART_INTERRUPT_DRIVEN
/* Ensure that uart IRQ is disabled initially */
uart->ie = 0U;
/* Setup IRQ handler */
cfg->cfg_func();
#endif
#ifdef CONFIG_PINCTRL
ret = pinctrl_apply_state(cfg->pcfg, PINCTRL_STATE_DEFAULT);
if (ret < 0) {
return ret;
}
#endif
return 0;
}
static const struct uart_driver_api uart_sifive_driver_api = {
.poll_in = uart_sifive_poll_in,
.poll_out = uart_sifive_poll_out,
.err_check = NULL,
#ifdef CONFIG_UART_INTERRUPT_DRIVEN
.fifo_fill = uart_sifive_fifo_fill,
.fifo_read = uart_sifive_fifo_read,
.irq_tx_enable = uart_sifive_irq_tx_enable,
.irq_tx_disable = uart_sifive_irq_tx_disable,
.irq_tx_ready = uart_sifive_irq_tx_ready,
.irq_tx_complete = uart_sifive_irq_tx_complete,
.irq_rx_enable = uart_sifive_irq_rx_enable,
.irq_rx_disable = uart_sifive_irq_rx_disable,
.irq_rx_ready = uart_sifive_irq_rx_ready,
.irq_err_enable = uart_sifive_irq_err_enable,
.irq_err_disable = uart_sifive_irq_err_disable,
.irq_is_pending = uart_sifive_irq_is_pending,
.irq_update = uart_sifive_irq_update,
.irq_callback_set = uart_sifive_irq_callback_set,
#endif
};
#ifdef CONFIG_UART_SIFIVE_PORT_0
static struct uart_sifive_data uart_sifive_data_0;
#ifdef CONFIG_UART_INTERRUPT_DRIVEN
static void uart_sifive_irq_cfg_func_0(void);
#endif
PINCTRL_DT_INST_DEFINE(0);
static const struct uart_sifive_device_config uart_sifive_dev_cfg_0 = {
.port = DT_INST_REG_ADDR(0),
.sys_clk_freq = SIFIVE_PERIPHERAL_CLOCK_FREQUENCY,
.baud_rate = DT_INST_PROP(0, current_speed),
.rxcnt_irq = CONFIG_UART_SIFIVE_PORT_0_RXCNT_IRQ,
.txcnt_irq = CONFIG_UART_SIFIVE_PORT_0_TXCNT_IRQ,
.pcfg = PINCTRL_DT_INST_DEV_CONFIG_GET(0),
#ifdef CONFIG_UART_INTERRUPT_DRIVEN
.cfg_func = uart_sifive_irq_cfg_func_0,
#endif
};
DEVICE_DT_INST_DEFINE(0,
uart_sifive_init,
NULL,
&uart_sifive_data_0, &uart_sifive_dev_cfg_0,
PRE_KERNEL_1, CONFIG_SERIAL_INIT_PRIORITY,
(void *)&uart_sifive_driver_api);
#ifdef CONFIG_UART_INTERRUPT_DRIVEN
static void uart_sifive_irq_cfg_func_0(void)
{
IRQ_CONNECT(DT_INST_IRQN(0), DT_INST_IRQ(0, priority),
uart_sifive_irq_handler, DEVICE_DT_INST_GET(0),
0);
irq_enable(DT_INST_IRQN(0));
}
#endif
#endif /* CONFIG_UART_SIFIVE_PORT_0 */
#ifdef CONFIG_UART_SIFIVE_PORT_1
static struct uart_sifive_data uart_sifive_data_1;
#ifdef CONFIG_UART_INTERRUPT_DRIVEN
static void uart_sifive_irq_cfg_func_1(void);
#endif
PINCTRL_DT_INST_DEFINE(1);
static const struct uart_sifive_device_config uart_sifive_dev_cfg_1 = {
.port = DT_INST_REG_ADDR(1),
.sys_clk_freq = SIFIVE_PERIPHERAL_CLOCK_FREQUENCY,
.baud_rate = DT_INST_PROP(1, current_speed),
.rxcnt_irq = CONFIG_UART_SIFIVE_PORT_1_RXCNT_IRQ,
.txcnt_irq = CONFIG_UART_SIFIVE_PORT_1_TXCNT_IRQ,
.pcfg = PINCTRL_DT_INST_DEV_CONFIG_GET(1),
#ifdef CONFIG_UART_INTERRUPT_DRIVEN
.cfg_func = uart_sifive_irq_cfg_func_1,
#endif
};
DEVICE_DT_INST_DEFINE(1,
uart_sifive_init,
NULL,
&uart_sifive_data_1, &uart_sifive_dev_cfg_1,
PRE_KERNEL_1, CONFIG_SERIAL_INIT_PRIORITY,
(void *)&uart_sifive_driver_api);
#ifdef CONFIG_UART_INTERRUPT_DRIVEN
static void uart_sifive_irq_cfg_func_1(void)
{
IRQ_CONNECT(DT_INST_IRQN(1), DT_INST_IRQ(1, priority),
uart_sifive_irq_handler, DEVICE_DT_INST_GET(1),
0);
irq_enable(DT_INST_IRQN(1));
}
#endif
#endif /* CONFIG_UART_SIFIVE_PORT_1 */
``` | /content/code_sandbox/drivers/serial/uart_sifive.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 2,936 |
```c
/*
*
*/
#define DT_DRV_COMPAT zephyr_uart_emul
#include <errno.h>
#include <zephyr/drivers/emul.h>
#include <zephyr/drivers/uart.h>
#include <zephyr/drivers/serial/uart_emul.h>
#include <zephyr/kernel.h>
#include <zephyr/logging/log.h>
#include <zephyr/sys/ring_buffer.h>
#include <zephyr/sys/util.h>
LOG_MODULE_REGISTER(uart_emul, CONFIG_UART_LOG_LEVEL);
struct uart_emul_config {
/* emul_list has to be the first member */
struct emul_list_for_bus emul_list;
bool loopback;
size_t latch_buffer_size;
};
BUILD_ASSERT(offsetof(struct uart_emul_config, emul_list) == 0);
/* Device run time data */
struct uart_emul_data {
/* List of struct uart_emul associated with the device */
sys_slist_t emuls;
const struct device *dev;
struct uart_config cfg;
int errors;
struct ring_buf *rx_rb;
struct k_spinlock rx_lock;
uart_emul_callback_tx_data_ready_t tx_data_ready_cb;
void *user_data;
struct ring_buf *tx_rb;
struct k_spinlock tx_lock;
#ifdef CONFIG_UART_INTERRUPT_DRIVEN
bool rx_irq_en;
bool tx_irq_en;
struct k_work irq_work;
uart_irq_callback_user_data_t irq_cb;
void *irq_cb_udata;
#endif /* CONFIG_UART_INTERRUPT_DRIVEN */
#ifdef CONFIG_UART_ASYNC_API
bool rx_async_en;
bool rx_stopping;
bool rx_release_on_timeout;
struct k_work tx_work;
struct k_work rx_work;
struct k_work rx_disable_work;
struct k_work_delayable rx_timeout_work;
uart_callback_t uart_callback;
void *callback_user_data;
const uint8_t *tx_buf;
size_t tx_buf_len;
size_t tx_buf_offset;
uint8_t *rx_buf;
size_t rx_buf_len;
size_t rx_buf_offset;
size_t rx_buf_data_len;
int32_t rx_buf_timeout;
uint8_t *rx_buf_next;
size_t rx_buf_next_len;
#endif /* CONFIG_UART_ASYNC_API */
};
/*
* Define local thread to emulate different thread priorities.
*
* A UART driver may call back from within a thread with higher or lower priority
* than the thread calling the UART API. This can hide potential concurrency issues,
* especially if the thread priorities are the same, or even using the same thread
* in case the system work queue.
*/
K_THREAD_STACK_DEFINE(uart_emul_stack_area, CONFIG_UART_EMUL_WORK_Q_STACK_SIZE);
struct k_work_q uart_emul_work_q;
int uart_emul_init_work_q(void)
{
k_work_queue_init(&uart_emul_work_q);
k_work_queue_start(&uart_emul_work_q, uart_emul_stack_area,
K_THREAD_STACK_SIZEOF(uart_emul_stack_area),
CONFIG_UART_EMUL_WORK_Q_PRIORITY, NULL);
return 0;
}
SYS_INIT(uart_emul_init_work_q, POST_KERNEL, 0);
static void uart_emul_tx_data_ready(const struct device *dev)
{
struct uart_emul_data *data = dev->data;
sys_snode_t *node;
if (data->tx_data_ready_cb) {
(data->tx_data_ready_cb)(dev, ring_buf_size_get(data->tx_rb), data->user_data);
}
SYS_SLIST_FOR_EACH_NODE(&data->emuls, node) {
struct uart_emul *emul = CONTAINER_OF(node, struct uart_emul, node);
__ASSERT_NO_MSG(emul->api != NULL);
__ASSERT_NO_MSG(emul->api->tx_data_ready != NULL);
emul->api->tx_data_ready(dev, ring_buf_size_get(data->tx_rb), emul->target);
}
}
static int uart_emul_poll_in(const struct device *dev, unsigned char *p_char)
{
struct uart_emul_data *drv_data = dev->data;
k_spinlock_key_t key;
uint32_t read;
key = k_spin_lock(&drv_data->rx_lock);
read = ring_buf_get(drv_data->rx_rb, p_char, 1);
k_spin_unlock(&drv_data->rx_lock, key);
if (!read) {
LOG_DBG("Rx buffer is empty");
return -1;
}
return 0;
}
static void uart_emul_poll_out(const struct device *dev, unsigned char out_char)
{
struct uart_emul_data *drv_data = dev->data;
const struct uart_emul_config *drv_cfg = dev->config;
k_spinlock_key_t key;
uint32_t written;
key = k_spin_lock(&drv_data->tx_lock);
written = ring_buf_put(drv_data->tx_rb, &out_char, 1);
k_spin_unlock(&drv_data->tx_lock, key);
if (!written) {
LOG_DBG("Tx buffer is full");
return;
}
if (drv_cfg->loopback) {
uart_emul_put_rx_data(dev, &out_char, 1);
}
uart_emul_tx_data_ready(dev);
}
static int uart_emul_err_check(const struct device *dev)
{
struct uart_emul_data *drv_data = dev->data;
int errors = drv_data->errors;
drv_data->errors = 0;
return errors;
}
#ifdef CONFIG_UART_USE_RUNTIME_CONFIGURE
static int uart_emul_configure(const struct device *dev, const struct uart_config *cfg)
{
struct uart_emul_data *drv_data = dev->data;
memcpy(&drv_data->cfg, cfg, sizeof(struct uart_config));
return 0;
}
static int uart_emul_config_get(const struct device *dev, struct uart_config *cfg)
{
const struct uart_emul_data *drv_data = dev->data;
memcpy(cfg, &drv_data->cfg, sizeof(struct uart_config));
return 0;
}
#endif /* CONFIG_UART_USE_RUNTIME_CONFIGURE */
#ifdef CONFIG_UART_INTERRUPT_DRIVEN
static int uart_emul_fifo_fill(const struct device *dev, const uint8_t *tx_data, int size)
{
int ret;
struct uart_emul_data *data = dev->data;
const struct uart_emul_config *config = dev->config;
uint32_t put_size = MIN(config->latch_buffer_size, size);
K_SPINLOCK(&data->tx_lock) {
ret = ring_buf_put(data->tx_rb, tx_data, put_size);
}
if (config->loopback) {
uart_emul_put_rx_data(dev, (uint8_t *)tx_data, put_size);
}
uart_emul_tx_data_ready(dev);
return ret;
}
static int uart_emul_fifo_read(const struct device *dev, uint8_t *rx_data, int size)
{
struct uart_emul_data *data = dev->data;
const struct uart_emul_config *config = dev->config;
uint32_t bytes_to_read;
K_SPINLOCK(&data->rx_lock) {
bytes_to_read = MIN(config->latch_buffer_size, ring_buf_size_get(data->rx_rb));
bytes_to_read = MIN(bytes_to_read, size);
ring_buf_get(data->rx_rb, rx_data, bytes_to_read);
}
return bytes_to_read;
}
static int uart_emul_irq_tx_ready(const struct device *dev)
{
bool ready = false;
struct uart_emul_data *data = dev->data;
K_SPINLOCK(&data->tx_lock) {
if (!data->tx_irq_en) {
K_SPINLOCK_BREAK;
}
ready = ring_buf_space_get(data->tx_rb) > 0;
}
return ready;
}
static int uart_emul_irq_rx_ready(const struct device *dev)
{
bool ready = false;
struct uart_emul_data *data = dev->data;
K_SPINLOCK(&data->rx_lock) {
if (!data->rx_irq_en) {
K_SPINLOCK_BREAK;
}
ready = !ring_buf_is_empty(data->rx_rb);
}
return ready;
}
static void uart_emul_irq_handler(struct k_work *work)
{
struct uart_emul_data *data = CONTAINER_OF(work, struct uart_emul_data, irq_work);
const struct device *dev = data->dev;
uart_irq_callback_user_data_t cb = data->irq_cb;
void *udata = data->irq_cb_udata;
if (cb == NULL) {
LOG_DBG("No IRQ callback configured for uart_emul device %p", dev);
return;
}
while (true) {
bool have_work = false;
K_SPINLOCK(&data->tx_lock) {
if (!data->tx_irq_en) {
K_SPINLOCK_BREAK;
}
have_work = have_work || ring_buf_space_get(data->tx_rb) > 0;
}
K_SPINLOCK(&data->rx_lock) {
if (!data->rx_irq_en) {
K_SPINLOCK_BREAK;
}
have_work = have_work || !ring_buf_is_empty(data->rx_rb);
}
if (!have_work) {
break;
}
cb(dev, udata);
}
}
static int uart_emul_irq_is_pending(const struct device *dev)
{
return uart_emul_irq_tx_ready(dev) || uart_emul_irq_rx_ready(dev);
}
static void uart_emul_irq_tx_enable(const struct device *dev)
{
bool submit_irq_work;
struct uart_emul_data *const data = dev->data;
K_SPINLOCK(&data->tx_lock) {
data->tx_irq_en = true;
submit_irq_work = ring_buf_space_get(data->tx_rb) > 0;
}
if (submit_irq_work) {
(void)k_work_submit_to_queue(&uart_emul_work_q, &data->irq_work);
}
}
static void uart_emul_irq_rx_enable(const struct device *dev)
{
bool submit_irq_work;
struct uart_emul_data *const data = dev->data;
K_SPINLOCK(&data->rx_lock) {
data->rx_irq_en = true;
submit_irq_work = !ring_buf_is_empty(data->rx_rb);
}
if (submit_irq_work) {
(void)k_work_submit_to_queue(&uart_emul_work_q, &data->irq_work);
}
}
static void uart_emul_irq_tx_disable(const struct device *dev)
{
struct uart_emul_data *const data = dev->data;
K_SPINLOCK(&data->tx_lock) {
data->tx_irq_en = false;
}
}
static void uart_emul_irq_rx_disable(const struct device *dev)
{
struct uart_emul_data *const data = dev->data;
K_SPINLOCK(&data->rx_lock) {
data->rx_irq_en = false;
}
}
static int uart_emul_irq_tx_complete(const struct device *dev)
{
bool tx_complete = false;
struct uart_emul_data *const data = dev->data;
K_SPINLOCK(&data->tx_lock) {
tx_complete = ring_buf_is_empty(data->tx_rb);
}
return tx_complete;
}
static void uart_emul_irq_callback_set(const struct device *dev, uart_irq_callback_user_data_t cb,
void *user_data)
{
struct uart_emul_data *const data = dev->data;
data->irq_cb = cb;
data->irq_cb_udata = user_data;
}
static int uart_emul_irq_update(const struct device *dev)
{
return 1;
}
#endif /* CONFIG_UART_INTERRUPT_DRIVEN */
#ifdef CONFIG_UART_ASYNC_API
static void uart_emul_post_event(const struct device *dev, struct uart_event *evt)
{
struct uart_emul_data *data = dev->data;
if (!data->uart_callback) {
LOG_DBG("No async callback configured for uart_emul device %p", dev);
}
data->uart_callback(dev, evt, data->callback_user_data);
}
static void uart_emul_simple_event(const struct device *dev, enum uart_event_type type)
{
uart_emul_post_event(dev, &(struct uart_event){.type = type});
}
static void uart_emul_async_switch_buf_nolock(struct uart_emul_data *data)
{
data->rx_buf = data->rx_buf_next;
data->rx_buf_len = data->rx_buf_next_len;
data->rx_buf_offset = 0;
data->rx_buf_data_len = 0;
data->rx_buf_next = NULL;
data->rx_buf_next_len = 0;
}
static void uart_emul_async_rx_timeout_handler(struct k_work *_work)
{
struct k_work_delayable *work = k_work_delayable_from_work(_work);
struct uart_emul_data *data = CONTAINER_OF(work, struct uart_emul_data, rx_timeout_work);
const struct device *dev = data->dev;
uint8_t *rx_buf;
size_t rx_buf_len;
size_t rx_buf_offset;
size_t rx_buf_data_len;
bool rx_en;
bool rx_buf_released = false;
bool rx_stopped = false;
K_SPINLOCK(&data->rx_lock) {
rx_en = data->rx_async_en;
rx_buf = data->rx_buf;
rx_buf_len = data->rx_buf_len;
rx_buf_offset = data->rx_buf_offset;
rx_buf_data_len = data->rx_buf_data_len;
data->rx_buf_offset += rx_buf_data_len;
data->rx_buf_data_len = 0;
if (data->rx_buf_offset >= rx_buf_len ||
(rx_buf_data_len > 0 && data->rx_release_on_timeout)) {
rx_buf_released = true;
uart_emul_async_switch_buf_nolock(data);
if (data->rx_buf == NULL) {
/* There was no second buffer scheduled, so stop receiving */
rx_stopped = true;
data->rx_async_en = false;
}
}
}
if (!rx_en || rx_buf == NULL || rx_buf_data_len == 0) {
return;
}
struct uart_event rx_rdy_event = {
.type = UART_RX_RDY,
.data.rx = {
.buf = rx_buf,
.offset = rx_buf_offset,
.len = rx_buf_data_len,
},
};
uart_emul_post_event(dev, &rx_rdy_event);
if (rx_buf_released) {
struct uart_event rx_buf_released_event = {
.type = UART_RX_BUF_RELEASED,
.data.rx_buf.buf = rx_buf,
};
uart_emul_post_event(dev, &rx_buf_released_event);
}
if (rx_stopped) {
uart_emul_simple_event(dev, UART_RX_DISABLED);
}
}
static void uart_emul_async_rx_handler(struct k_work *work)
{
struct uart_emul_data *data = CONTAINER_OF(work, struct uart_emul_data, rx_work);
const struct device *dev = data->dev;
bool rx_en = false;
bool empty = true;
do {
bool rx_rdy = false;
bool buf_request = false;
uint8_t *rx_buf = NULL;
size_t buf_len;
size_t offset;
size_t data_len;
K_SPINLOCK(&data->rx_lock) {
rx_en = data->rx_async_en;
rx_buf = data->rx_buf;
buf_len = data->rx_buf_len;
offset = data->rx_buf_offset;
data_len = data->rx_buf_data_len;
empty = ring_buf_is_empty(data->rx_rb);
if (!rx_en) {
K_SPINLOCK_BREAK;
}
if (rx_buf == NULL) {
uart_emul_async_switch_buf_nolock(data);
rx_buf = data->rx_buf;
buf_len = data->rx_buf_len;
offset = data->rx_buf_offset;
data_len = data->rx_buf_data_len;
}
if (rx_buf == NULL) {
/* During the last iteration the buffer was released but the
* application did not provide a new buffer. Stop RX and quit now.
*/
data->rx_async_en = false;
K_SPINLOCK_BREAK;
}
if (empty) {
K_SPINLOCK_BREAK;
}
buf_request = data_len == 0 && data->rx_buf_next == NULL;
uint32_t read = ring_buf_get(data->rx_rb, &rx_buf[offset + data_len],
buf_len - (offset + data_len));
data_len += read;
data->rx_buf_data_len = data_len;
if (offset + data_len >= data->rx_buf_len) {
rx_rdy = true;
data->rx_buf = NULL;
data->rx_buf_len = 0;
data->rx_buf_offset = 0;
data->rx_buf_data_len = 0;
}
}
if (!rx_en) {
break;
}
if (rx_buf == NULL) {
uart_emul_simple_event(dev, UART_RX_DISABLED);
break;
}
if (empty && data->rx_buf_timeout != SYS_FOREVER_US) {
(void)k_work_reschedule_for_queue(&uart_emul_work_q, &data->rx_timeout_work,
K_USEC(data->rx_buf_timeout));
}
if (buf_request) {
uart_emul_simple_event(dev, UART_RX_BUF_REQUEST);
}
if (rx_rdy) {
struct uart_event rx_rdy_event = {
.type = UART_RX_RDY,
.data.rx = {
.buf = rx_buf,
.offset = offset,
.len = data_len,
},
};
uart_emul_post_event(dev, &rx_rdy_event);
struct uart_event rx_buf_released_event = {
.type = UART_RX_BUF_RELEASED,
.data.rx_buf.buf = rx_buf,
};
uart_emul_post_event(dev, &rx_buf_released_event);
}
} while (rx_en && !empty);
}
static void uart_emul_async_tx_handler(struct k_work *work)
{
struct uart_emul_data *data = CONTAINER_OF(work, struct uart_emul_data, tx_work);
const struct device *dev = data->dev;
const struct uart_emul_config *config = dev->config;
uint32_t written;
const uint8_t *tx_buf = NULL;
size_t tx_buf_len = 0;
size_t tx_buf_offset = 0;
bool tx_done = true;
K_SPINLOCK(&data->tx_lock) {
tx_buf = data->tx_buf;
tx_buf_len = data->tx_buf_len;
tx_buf_offset = data->tx_buf_offset;
if (!tx_buf) {
K_SPINLOCK_BREAK;
}
written = ring_buf_put(data->tx_rb, &data->tx_buf[tx_buf_offset],
tx_buf_len - tx_buf_offset);
tx_done = written == (tx_buf_len - tx_buf_offset);
if (!tx_done) {
data->tx_buf_offset += written;
K_SPINLOCK_BREAK;
}
data->tx_buf = NULL;
data->tx_buf_len = 0;
data->tx_buf_offset = 0;
}
if (!tx_buf) {
return;
}
if (config->loopback && written) {
uint32_t loop_written = uart_emul_put_rx_data(dev, &tx_buf[tx_buf_offset], written);
if (loop_written < written) {
LOG_WRN("Lost %" PRIu32 " bytes on loopback", written - loop_written);
}
}
uart_emul_tx_data_ready(dev);
if ((config->loopback && written) || !written) {
/* When using the loopback fixture, just allow to drop all bytes in the ring buffer
* not consumed by tx_data_ready_cb().
*/
uint32_t flushed = uart_emul_flush_tx_data(dev);
if (flushed) {
if (written) {
LOG_DBG("Flushed %" PRIu32 " unused bytes from tx buffer", flushed);
} else {
LOG_WRN("Flushed %" PRIu32
" unused bytes from tx buffer to break out of infinite "
"loop! Consume or flush the bytes from the tx ring buffer "
"in your test case to prevent this!",
flushed);
}
}
}
if (!tx_done) {
/* We are not done yet, yield back into workqueue.
*
* This would basically be an infinite loop when tx_data_ready_cb() does not consume
* the bytes in the tx ring buffer.
*/
k_work_submit_to_queue(&uart_emul_work_q, &data->tx_work);
return;
}
struct uart_event tx_done_event = {
.type = UART_TX_DONE,
.data.tx = {
.buf = tx_buf,
.len = tx_buf_len,
},
};
uart_emul_post_event(dev, &tx_done_event);
}
static void uart_emul_rx_stop(const struct device *dev, struct uart_emul_data *data)
{
uint8_t *rx_buf = NULL;
size_t rx_buf_offset = 0;
size_t rx_buf_data_len = 0;
k_work_cancel_delayable(&data->rx_timeout_work);
K_SPINLOCK(&data->rx_lock) {
if (!data->rx_async_en) {
K_SPINLOCK_BREAK;
}
rx_buf = data->rx_buf;
rx_buf_offset = data->rx_buf_offset;
rx_buf_data_len = data->rx_buf_data_len;
data->rx_buf = NULL;
data->rx_buf_len = 0;
data->rx_buf_offset = 0;
data->rx_buf_data_len = 0;
data->rx_buf_next = NULL;
data->rx_buf_next_len = 0;
data->rx_async_en = false;
data->rx_stopping = false;
}
if (rx_buf == NULL) {
return;
}
if (rx_buf_data_len > 0) {
struct uart_event rx_rdy_event = {
.type = UART_RX_RDY,
.data.rx = {
.buf = rx_buf,
.offset = rx_buf_offset,
.len = rx_buf_data_len,
},
};
uart_emul_post_event(dev, &rx_rdy_event);
}
struct uart_event rx_buf_released_event = {
.type = UART_RX_BUF_RELEASED,
.data.rx_buf.buf = rx_buf,
};
uart_emul_post_event(dev, &rx_buf_released_event);
uart_emul_simple_event(dev, UART_RX_DISABLED);
}
static void uart_emul_async_rx_disable_handler(struct k_work *work)
{
struct uart_emul_data *data = CONTAINER_OF(work, struct uart_emul_data, rx_disable_work);
const struct device *dev = data->dev;
uart_emul_rx_stop(dev, data);
}
static int uart_emul_callback_set(const struct device *dev, uart_callback_t callback,
void *user_data)
{
struct uart_emul_data *data = dev->data;
data->uart_callback = callback;
data->callback_user_data = user_data;
return 0;
}
static int uart_emul_tx(const struct device *dev, const uint8_t *buf, size_t len, int32_t timeout)
{
struct uart_emul_data *data = dev->data;
int ret = 0;
K_SPINLOCK(&data->tx_lock) {
if (data->tx_buf) {
ret = -EBUSY;
K_SPINLOCK_BREAK;
}
data->tx_buf = buf;
data->tx_buf_len = len;
data->tx_buf_offset = 0;
k_work_submit_to_queue(&uart_emul_work_q, &data->tx_work);
}
return ret;
}
static int uart_emul_tx_abort(const struct device *dev)
{
struct uart_emul_data *data = dev->data;
const uint8_t *tx_buf = NULL;
size_t tx_buf_sent;
K_SPINLOCK(&data->tx_lock) {
tx_buf = data->tx_buf;
tx_buf_sent = data->tx_buf_offset;
data->tx_buf = NULL;
data->tx_buf_len = 0;
data->tx_buf_offset = 0;
k_work_cancel(&data->tx_work);
}
if (!tx_buf) {
return -EFAULT;
}
struct uart_event tx_aborted_event = {
.type = UART_TX_ABORTED,
.data.tx = {
.buf = tx_buf,
.len = tx_buf_sent,
},
};
uart_emul_post_event(dev, &tx_aborted_event);
return 0;
}
static int uart_emul_rx_buf_rsp(const struct device *dev, uint8_t *buf, size_t len)
{
struct uart_emul_data *data = dev->data;
int ret = 0;
K_SPINLOCK(&data->rx_lock) {
if (!data->rx_async_en) {
ret = -EACCES;
K_SPINLOCK_BREAK;
}
if (data->rx_buf_next != NULL) {
ret = -EBUSY;
K_SPINLOCK_BREAK;
}
data->rx_buf_next = buf;
data->rx_buf_next_len = len;
}
return ret;
}
static int uart_emul_rx_enable(const struct device *dev, uint8_t *buf, size_t len, int32_t timeout)
{
struct uart_emul_data *data = dev->data;
int ret = 0;
bool rx_stopping;
K_SPINLOCK(&data->rx_lock) {
rx_stopping = data->rx_stopping;
k_work_cancel(&data->rx_disable_work);
}
if (rx_stopping) {
uart_emul_rx_stop(dev, data);
}
K_SPINLOCK(&data->rx_lock) {
if (data->rx_async_en) {
ret = -EBUSY;
K_SPINLOCK_BREAK;
}
data->rx_async_en = true;
data->rx_buf = buf;
data->rx_buf_len = len;
data->rx_buf_timeout = timeout;
data->rx_buf_offset = 0;
data->rx_buf_data_len = 0;
data->rx_buf_next = NULL;
data->rx_buf_next_len = 0;
if (!ring_buf_is_empty(data->rx_rb)) {
(void)k_work_submit_to_queue(&uart_emul_work_q, &data->rx_work);
}
}
return ret;
}
static int uart_emul_rx_disable(const struct device *dev)
{
struct uart_emul_data *data = dev->data;
int ret = 0;
K_SPINLOCK(&data->rx_lock) {
if (!data->rx_async_en) {
ret = -EFAULT;
K_SPINLOCK_BREAK;
}
data->rx_stopping = true;
k_work_submit_to_queue(&uart_emul_work_q, &data->rx_disable_work);
}
return ret;
}
#endif /* CONFIG_UART_ASYNC_API */
static const struct uart_driver_api uart_emul_api = {
.poll_in = uart_emul_poll_in,
.poll_out = uart_emul_poll_out,
#ifdef CONFIG_UART_USE_RUNTIME_CONFIGURE
.config_get = uart_emul_config_get,
.configure = uart_emul_configure,
#endif /* CONFIG_UART_USE_RUNTIME_CONFIGURE */
.err_check = uart_emul_err_check,
#ifdef CONFIG_UART_INTERRUPT_DRIVEN
.fifo_fill = uart_emul_fifo_fill,
.fifo_read = uart_emul_fifo_read,
.irq_tx_enable = uart_emul_irq_tx_enable,
.irq_rx_enable = uart_emul_irq_rx_enable,
.irq_tx_disable = uart_emul_irq_tx_disable,
.irq_rx_disable = uart_emul_irq_rx_disable,
.irq_tx_ready = uart_emul_irq_tx_ready,
.irq_rx_ready = uart_emul_irq_rx_ready,
.irq_tx_complete = uart_emul_irq_tx_complete,
.irq_callback_set = uart_emul_irq_callback_set,
.irq_update = uart_emul_irq_update,
.irq_is_pending = uart_emul_irq_is_pending,
#endif /* CONFIG_UART_INTERRUPT_DRIVEN */
#ifdef CONFIG_UART_ASYNC_API
.callback_set = uart_emul_callback_set,
.tx = uart_emul_tx,
.tx_abort = uart_emul_tx_abort,
.rx_enable = uart_emul_rx_enable,
.rx_buf_rsp = uart_emul_rx_buf_rsp,
.rx_disable = uart_emul_rx_disable,
#endif /* CONFIG_UART_ASYNC_API */
};
void uart_emul_callback_tx_data_ready_set(const struct device *dev,
uart_emul_callback_tx_data_ready_t cb, void *user_data)
{
struct uart_emul_data *drv_data = dev->data;
drv_data->tx_data_ready_cb = cb;
drv_data->user_data = user_data;
}
uint32_t uart_emul_put_rx_data(const struct device *dev, const uint8_t *data, size_t size)
{
struct uart_emul_data *drv_data = dev->data;
uint32_t count;
__unused bool empty;
__unused bool irq_en;
__unused bool rx_en;
K_SPINLOCK(&drv_data->rx_lock) {
count = ring_buf_put(drv_data->rx_rb, data, size);
empty = ring_buf_is_empty(drv_data->rx_rb);
IF_ENABLED(CONFIG_UART_INTERRUPT_DRIVEN, (irq_en = drv_data->rx_irq_en;));
IF_ENABLED(CONFIG_UART_ASYNC_API, (rx_en = drv_data->rx_async_en;));
}
if (count < size) {
uart_emul_set_errors(dev, UART_ERROR_OVERRUN);
}
IF_ENABLED(CONFIG_UART_INTERRUPT_DRIVEN, (
if (count > 0 && irq_en && !empty) {
(void)k_work_submit_to_queue(&uart_emul_work_q, &drv_data->irq_work);
}
))
IF_ENABLED(CONFIG_UART_ASYNC_API, (
if (count > 0 && rx_en && !empty) {
(void)k_work_submit_to_queue(&uart_emul_work_q, &drv_data->rx_work);
}
))
return count;
}
uint32_t uart_emul_get_tx_data(const struct device *dev, uint8_t *data, size_t size)
{
struct uart_emul_data *drv_data = dev->data;
k_spinlock_key_t key;
uint32_t count;
key = k_spin_lock(&drv_data->tx_lock);
count = ring_buf_get(drv_data->tx_rb, data, size);
k_spin_unlock(&drv_data->tx_lock, key);
return count;
}
uint32_t uart_emul_flush_rx_data(const struct device *dev)
{
struct uart_emul_data *drv_data = dev->data;
k_spinlock_key_t key;
uint32_t count;
key = k_spin_lock(&drv_data->rx_lock);
count = ring_buf_size_get(drv_data->rx_rb);
ring_buf_reset(drv_data->rx_rb);
k_spin_unlock(&drv_data->rx_lock, key);
return count;
}
uint32_t uart_emul_flush_tx_data(const struct device *dev)
{
struct uart_emul_data *drv_data = dev->data;
k_spinlock_key_t key;
uint32_t count;
key = k_spin_lock(&drv_data->tx_lock);
count = ring_buf_size_get(drv_data->tx_rb);
ring_buf_reset(drv_data->tx_rb);
k_spin_unlock(&drv_data->tx_lock, key);
return count;
}
void uart_emul_set_errors(const struct device *dev, int errors)
{
struct uart_emul_data *drv_data = dev->data;
drv_data->errors |= errors;
}
void uart_emul_set_release_buffer_on_timeout(const struct device *dev, bool release_on_timeout)
{
__unused struct uart_emul_data *drv_data = dev->data;
IF_ENABLED(CONFIG_UART_ASYNC_API, (drv_data->rx_release_on_timeout = release_on_timeout;));
}
int uart_emul_register(const struct device *dev, struct uart_emul *emul)
{
struct uart_emul_data *data = dev->data;
sys_slist_append(&data->emuls, &emul->node);
return 0;
}
#define UART_EMUL_RX_FIFO_SIZE(inst) (DT_INST_PROP(inst, rx_fifo_size))
#define UART_EMUL_TX_FIFO_SIZE(inst) (DT_INST_PROP(inst, tx_fifo_size))
#define EMUL_LINK_AND_COMMA(node_id) \
{ \
.dev = DEVICE_DT_GET(node_id), \
},
#define DEFINE_UART_EMUL(inst) \
static const struct emul_link_for_bus emuls_##inst[] = { \
DT_FOREACH_CHILD_STATUS_OKAY(DT_DRV_INST(inst), EMUL_LINK_AND_COMMA)}; \
\
RING_BUF_DECLARE(uart_emul_##inst##_rx_rb, UART_EMUL_RX_FIFO_SIZE(inst)); \
RING_BUF_DECLARE(uart_emul_##inst##_tx_rb, UART_EMUL_TX_FIFO_SIZE(inst)); \
\
static const struct uart_emul_config uart_emul_cfg_##inst = { \
.loopback = DT_INST_PROP(inst, loopback), \
.latch_buffer_size = DT_INST_PROP(inst, latch_buffer_size), \
.emul_list = { \
.children = emuls_##inst, \
.num_children = ARRAY_SIZE(emuls_##inst), \
}, \
}; \
static struct uart_emul_data uart_emul_data_##inst = { \
.emuls = SYS_SLIST_STATIC_INIT(&_CONCAT(uart_emul_data_, inst).emuls), \
.dev = DEVICE_DT_INST_GET(inst), \
.rx_rb = &uart_emul_##inst##_rx_rb, \
.tx_rb = &uart_emul_##inst##_tx_rb, \
IF_ENABLED(CONFIG_UART_INTERRUPT_DRIVEN, \
(.irq_work = Z_WORK_INITIALIZER(uart_emul_irq_handler),)) \
IF_ENABLED(CONFIG_UART_ASYNC_API, \
(.tx_work = Z_WORK_INITIALIZER(uart_emul_async_tx_handler), \
.rx_timeout_work = Z_WORK_DELAYABLE_INITIALIZER( \
uart_emul_async_rx_timeout_handler), \
.rx_work = Z_WORK_INITIALIZER(uart_emul_async_rx_handler), \
.rx_disable_work = Z_WORK_INITIALIZER( \
uart_emul_async_rx_disable_handler),)) \
}; \
\
static int uart_emul_post_init_##inst(void) \
{ \
return emul_init_for_bus(DEVICE_DT_INST_GET(inst)); \
} \
SYS_INIT(uart_emul_post_init_##inst, POST_KERNEL, CONFIG_UART_EMUL_DEVICE_INIT_PRIORITY); \
\
DEVICE_DT_INST_DEFINE(inst, NULL, NULL, &uart_emul_data_##inst, &uart_emul_cfg_##inst, \
PRE_KERNEL_1, CONFIG_SERIAL_INIT_PRIORITY, &uart_emul_api);
DT_INST_FOREACH_STATUS_OKAY(DEFINE_UART_EMUL)
``` | /content/code_sandbox/drivers/serial/uart_emul.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 7,523 |
```objective-c
/*
*
*/
#ifndef ZEPHYR_DRIVERS_SERIAL_UART_LPC11U6X_H_
#define ZEPHYR_DRIVERS_SERIAL_UART_LPC11U6X_H_
#include <zephyr/drivers/pinctrl.h>
#define LPC11U6X_UART0_CLK 14745600
#define LPC11U6X_UART0_LCR_WLS_5BITS 0
#define LPC11U6X_UART0_LCR_WLS_6BITS 1
#define LPC11U6X_UART0_LCR_WLS_7BITS 2
#define LPC11U6X_UART0_LCR_WLS_8BITS 3
#define LPC11U6X_UART0_LCR_STOP_1BIT (0 << 2)
#define LPC11U6X_UART0_LCR_STOP_2BIT (1 << 2)
#define LPC11U6X_UART0_LCR_PARTIY_ENABLE (1 << 3)
#define LPC11U6X_UART0_LCR_PARTIY_ODD (0 << 4)
#define LPC11U6X_UART0_LCR_PARTIY_EVEN (1 << 4)
#define LPC11U6X_UART0_LCR_DLAB (1 << 7)
#define LPC11U6X_UART0_FCR_FIFO_EN (1 << 0)
#define LPC11U6X_UART0_LSR_RDR (1 << 0)
#define LPC11U6X_UART0_LSR_OE (1 << 1)
#define LPC11U6X_UART0_LSR_PE (1 << 2)
#define LPC11U6X_UART0_LSR_FE (1 << 3)
#define LPC11U6X_UART0_LSR_BI (1 << 4)
#define LPC11U6X_UART0_LSR_THRE (1 << 5)
#define LPC11U6X_UART0_LSR_TEMT (1 << 6)
#define LPC11U6X_UART0_LSR_RXFE (1 << 7)
#define LPC11U6X_UART0_IER_RBRINTEN (1 << 0)
#define LPC11U6X_UART0_IER_THREINTEN (1 << 1)
#define LPC11U6X_UART0_IER_RLSINTEN (1 << 2)
#define LPC11U6X_UART0_IER_MASK (0x30F)
#define LPC11U6X_UART0_IIR_STATUS (0x1 << 0)
#define LPC11U6X_UART0_IIR_INTID(x) (((x) >> 1) & 0x7)
#define LPC11U6X_UART0_IIR_INTID_RLS 0x3
#define LPC11U6X_UART0_IIR_INTID_RDA 0x2
#define LPC11U6X_UART0_IIR_INTID_CTI 0x6
#define LPC11U6X_UART0_IIR_INTID_THRE 0x1
#define LPC11U6X_UART0_FIFO_SIZE 16
#define LPC11U6X_UARTX_CFG_ENABLE (0x1 << 0)
#define LPC11U6X_UARTX_CFG_DATALEN_7BIT (0x0 << 2)
#define LPC11U6X_UARTX_CFG_DATALEN_8BIT (0x1 << 2)
#define LPC11U6X_UARTX_CFG_DATALEN_9BIT (0x2 << 2)
#define LPC11U6X_UARTX_CFG_PARITY_NONE (0x0 << 4)
#define LPC11U6X_UARTX_CFG_PARITY_EVEN (0x2 << 4)
#define LPC11U6X_UARTX_CFG_PARITY_ODD (0x3 << 4)
#define LPC11U6X_UARTX_CFG_STOP_1BIT (0x0 << 6)
#define LPC11U6X_UARTX_CFG_STOP_2BIT (0x1 << 6)
#define LPC11U6X_UARTX_CFG_RXPOL(x) (((x) & 0x1) << 22)
#define LPC11U6X_UARTX_CFG_TXPOL(x) (((x) & 0x1) << 23)
#define LPC11U6X_UARTX_CFG_MASK (0x00FCDAFD)
#define LPC11U6X_UARTX_STAT_RXRDY (1 << 0)
#define LPC11U6X_UARTX_STAT_TXRDY (1 << 2)
#define LPC11U6X_UARTX_STAT_TXIDLE (1 << 3)
#define LPC11U6X_UARTX_STAT_OVERRUNINT (1 << 8)
#define LPC11U6X_UARTX_STAT_FRAMERRINT (1 << 13)
#define LPC11U6X_UARTX_STAT_PARITYERRINT (1 << 14)
#define LPC11U6X_UARTX_BRG_MASK (0xFFFF)
#define LPC11U6X_UARTX_INT_EN_SET_RXRDYEN (1 << 0)
#define LPC11U6X_UARTX_INT_EN_SET_TXRDYEN (1 << 2)
#define LPC11U6X_UARTX_INT_EN_SET_OVERRUNEN (1 << 8)
#define LPC11U6X_UARTX_INT_EN_SET_FRAMERREN (1 << 13)
#define LPC11U6X_UARTX_INT_EN_SET_PARITYERREN (1 << 14)
#define LPC11U6X_UARTX_INT_EN_SET_MASK (0x0001F96D)
#define LPC11U6X_UARTX_INT_EN_CLR_RXRDYCLR (1 << 0)
#define LPC11U6X_UARTX_INT_EN_CLR_TXRDYCLR (1 << 2)
#define LPC11U6X_UARTX_INT_EN_CLR_OVERRUNCLR (1 << 8)
#define LPC11U6X_UARTX_INT_EN_CLR_FRAMERRCLR (1 << 13)
#define LPC11U6X_UARTX_INT_EN_CLR_PARITYERRCLR (1 << 14)
#define LPC11U6X_UARTX_INT_STAT_RXRDY (1 << 0)
#define LPC11U6X_UARTX_INT_STAT_TXRDY (1 << 2)
#define LPC11U6X_UARTX_INT_STAT_OVERRUN (1 << 8)
#define LPC11U6X_UARTX_INT_STAT_FRAMERR (1 << 13)
#define LPC11U6X_UARTX_INT_STAT_PARITYERR (1 << 14)
#define LPC11U6X_UARTX_DEVICE_PER_IRQ 2
struct lpc11u6x_uart0_regs {
union {
volatile const uint32_t rbr; /* RX buffer (RO) */
volatile uint32_t thr; /* TX buffer (WO) */
volatile uint32_t dll; /* Divisor latch LSB */
};
union {
volatile uint32_t dlm; /* Divisor latch MSB */
volatile uint32_t ier; /* Interrupt enable */
};
union {
volatile uint32_t iir; /* Interrupt ID */
volatile uint32_t fcr; /* FIFO Control */
};
volatile uint32_t lcr; /* Line Control */
volatile uint32_t mcr; /* Modem Control */
volatile uint32_t lsr; /* Line Status */
volatile uint32_t msr; /* Modem Status */
volatile uint32_t scr; /* Scratch pad */
volatile uint32_t acr; /* Auto-baud Control */
volatile uint32_t icr; /* IrDA Control */
volatile uint32_t fdr; /* Fractional Divider */
volatile uint32_t osr; /* Oversampling register */
volatile uint32_t ter; /* Transmit enable */
volatile uint32_t reserved1[3];
volatile uint32_t hden; /* Half duplex */
volatile uint32_t reserved2;
volatile uint32_t sci_ctrl; /* Smart card interface */
volatile uint32_t rs485_ctrl; /* RS-485 control */
volatile uint32_t rs485_addr_match; /* RS-485 address match */
volatile uint32_t rs485_dly; /* RS-485 delay direction control
* delay
*/
volatile uint32_t sync_ctrl; /* Synchronous mode control */
};
struct lpc11u6x_uart0_config {
struct lpc11u6x_uart0_regs *uart0;
const struct device *clock_dev;
uint32_t baudrate;
uint32_t clkid;
const struct pinctrl_dev_config *pincfg;
#ifdef CONFIG_UART_INTERRUPT_DRIVEN
void (*irq_config_func)(const struct device *dev);
#endif /* CONFIG_UART_INTERRUPT_DRIVEN */
};
struct lpc11u6x_uart0_data {
uint32_t baudrate;
uint8_t parity;
uint8_t stop_bits;
uint8_t data_bits;
uint8_t flow_ctrl;
#ifdef CONFIG_UART_INTERRUPT_DRIVEN
uart_irq_callback_user_data_t cb;
void *cb_data;
uint32_t cached_iir;
#endif /* CONFIG_UART_INTERRUPT_DRIVEN */
};
struct lpc11u6x_uartx_regs {
volatile uint32_t cfg; /* Configuration register */
volatile uint32_t ctl; /* Control register */
volatile uint32_t stat; /* Status register */
volatile uint32_t int_en_set; /* Interrupt enable and set */
volatile uint32_t int_en_clr; /* Interrupt enable clear */
volatile const uint32_t rx_dat; /* Receiver data */
volatile const uint32_t rx_dat_stat; /* Receiver data status */
volatile uint32_t tx_dat; /* Transmit data */
volatile uint32_t brg; /* Baud rate generator */
volatile const uint32_t int_stat; /* Interrupt status */
volatile uint32_t osr; /* Oversample selection */
volatile uint32_t addr; /* Address register*/
};
struct lpc11u6x_uartx_config {
struct lpc11u6x_uartx_regs *base;
const struct device *clock_dev;
uint32_t baudrate;
uint32_t clkid;
bool rx_invert;
bool tx_invert;
const struct pinctrl_dev_config *pincfg;
};
struct lpc11u6x_uartx_data {
uint32_t baudrate;
uint8_t parity;
uint8_t stop_bits;
uint8_t data_bits;
uint8_t flow_ctrl;
#ifdef CONFIG_UART_INTERRUPT_DRIVEN
uart_irq_callback_user_data_t cb;
void *cb_data;
#endif /* CONFIG_UART_INTERRUPT_DRIVEN */
};
/* Since UART1 and UART4 share the same IRQ (as well as UART2 and UART3),
* we need to give the ISR a way to know all the devices that should be
* notified when said IRQ is raised
*/
struct lpc11u6x_uartx_shared_irq {
const struct device *devices[LPC11U6X_UARTX_DEVICE_PER_IRQ];
};
#if CONFIG_UART_INTERRUPT_DRIVEN && \
(DT_NODE_HAS_STATUS(DT_NODELABEL(uart1), okay) || \
DT_NODE_HAS_STATUS(DT_NODELABEL(uart4), okay))
static void lpc11u6x_uartx_isr_config_1(const struct device *dev);
#endif /* CONFIG_UART_INTERRUPT_DRIVEN &&
* (DT_NODE_HAS_STATUS(DT_NODELABEL(uart2), okay) ||
* DT_NODE_HAS_STATUS(DT_NODELABEL(uart3), okay))
*/
#if CONFIG_UART_INTERRUPT_DRIVEN && \
(DT_NODE_HAS_STATUS(DT_NODELABEL(uart2), okay) || \
DT_NODE_HAS_STATUS(DT_NODELABEL(uart3), okay))
static void lpc11u6x_uartx_isr_config_2(const struct device *dev);
#endif /* CONFIG_UART_INTERRUPT_DRIVEN &&
* (DT_NODE_HAS_STATUS(DT_NODELABEL(uart2), okay) ||
* DT_NODE_HAS_STATUS(DT_NODELABEL(uart3), okay))
*/
#endif /* ZEPHYR_DRIVERS_SERIAL_UART_LPC11U6X_H_ */
``` | /content/code_sandbox/drivers/serial/uart_lpc11u6x.h | objective-c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 2,551 |
```c
/*
*
*/
#include <zephyr/drivers/serial/uart_async_to_irq.h>
#include <string.h>
#include <zephyr/logging/log.h>
LOG_MODULE_REGISTER(UART_ASYNC_TO_IRQ_LOG_NAME, CONFIG_UART_LOG_LEVEL);
/* Internal state flags. */
/* RX interrupt enabled. */
#define A2I_RX_IRQ_ENABLED BIT(0)
/* TX interrupt enabled. */
#define A2I_TX_IRQ_ENABLED BIT(1)
/* Error interrupt enabled. */
#define A2I_ERR_IRQ_ENABLED BIT(2)
/* Receiver to be kept enabled. */
#define A2I_RX_ENABLE BIT(3)
/* TX busy. */
#define A2I_TX_BUSY BIT(4)
static struct uart_async_to_irq_data *get_data(const struct device *dev)
{
struct uart_async_to_irq_data **data = dev->data;
return *data;
}
static const struct uart_async_to_irq_config *get_config(const struct device *dev)
{
const struct uart_async_to_irq_config * const *config = dev->config;
return *config;
}
/* Function calculates RX timeout based on baudrate. */
static uint32_t get_rx_timeout(const struct device *dev)
{
struct uart_config cfg = { 0 };
int err;
uint32_t baudrate;
err = uart_config_get(dev, &cfg);
if (err == 0) {
baudrate = cfg.baudrate;
} else {
baudrate = get_config(dev)->baudrate;
}
uint32_t us = (CONFIG_UART_ASYNC_TO_INT_DRIVEN_RX_TIMEOUT * 1000000) / baudrate;
return us;
}
static int rx_enable(const struct device *dev,
struct uart_async_to_irq_data *data,
uint8_t *buf,
size_t len)
{
int err;
const struct uart_async_to_irq_config *config = get_config(dev);
err = config->api->rx_enable(dev, buf, len, get_rx_timeout(dev));
return err;
}
static int try_rx_enable(const struct device *dev, struct uart_async_to_irq_data *data)
{
uint8_t *buf = uart_async_rx_buf_req(&data->rx.async_rx);
size_t len = uart_async_rx_get_buf_len(&data->rx.async_rx);
if (buf == NULL) {
return -EBUSY;
}
return rx_enable(dev, data, buf, len);
}
static void on_rx_buf_req(const struct device *dev,
const struct uart_async_to_irq_config *config,
struct uart_async_to_irq_data *data)
{
struct uart_async_rx *async_rx = &data->rx.async_rx;
uint8_t *buf = uart_async_rx_buf_req(async_rx);
size_t len = uart_async_rx_get_buf_len(async_rx);
if (buf) {
int err = config->api->rx_buf_rsp(dev, buf, len);
if (err < 0) {
uart_async_rx_on_buf_rel(async_rx, buf);
}
} else {
atomic_inc(&data->rx.pending_buf_req);
}
}
static void on_rx_dis(const struct device *dev, struct uart_async_to_irq_data *data)
{
if (data->flags & A2I_RX_ENABLE) {
int err;
if (data->rx.async_rx.pending_bytes == 0) {
uart_async_rx_reset(&data->rx.async_rx);
}
err = try_rx_enable(dev, data);
if (err == 0) {
data->rx.pending_buf_req = 0;
}
LOG_INST_DBG(get_config(dev)->log, "Reenabling RX from RX_DISABLED (err:%d)", err);
__ASSERT((err >= 0) || (err == -EBUSY), "err: %d", err);
return;
}
k_sem_give(&data->rx.sem);
}
static void uart_async_to_irq_callback(const struct device *dev,
struct uart_event *evt,
void *user_data)
{
struct uart_async_to_irq_data *data = (struct uart_async_to_irq_data *)user_data;
const struct uart_async_to_irq_config *config = get_config(dev);
bool call_handler = false;
switch (evt->type) {
case UART_TX_DONE:
atomic_and(&data->flags, ~A2I_TX_BUSY);
call_handler = data->flags & A2I_TX_IRQ_ENABLED;
break;
case UART_RX_RDY:
uart_async_rx_on_rdy(&data->rx.async_rx, evt->data.rx.buf, evt->data.rx.len);
call_handler = data->flags & A2I_RX_IRQ_ENABLED;
break;
case UART_RX_BUF_REQUEST:
on_rx_buf_req(dev, config, data);
break;
case UART_RX_BUF_RELEASED:
uart_async_rx_on_buf_rel(&data->rx.async_rx, evt->data.rx_buf.buf);
break;
case UART_RX_STOPPED:
call_handler = data->flags & A2I_ERR_IRQ_ENABLED;
break;
case UART_RX_DISABLED:
on_rx_dis(dev, data);
break;
default:
break;
}
if (data->callback && call_handler) {
atomic_inc(&data->irq_req);
config->trampoline(dev);
}
}
int z_uart_async_to_irq_fifo_fill(const struct device *dev, const uint8_t *buf, int len)
{
struct uart_async_to_irq_data *data = get_data(dev);
const struct uart_async_to_irq_config *config = get_config(dev);
int err;
len = MIN(len, data->tx.len);
if (atomic_or(&data->flags, A2I_TX_BUSY) & A2I_TX_BUSY) {
return 0;
}
memcpy(data->tx.buf, buf, len);
err = config->api->tx(dev, data->tx.buf, len, SYS_FOREVER_US);
if (err < 0) {
atomic_and(&data->flags, ~A2I_TX_BUSY);
return 0;
}
return len;
}
/** Interrupt driven FIFO read function */
int z_uart_async_to_irq_fifo_read(const struct device *dev,
uint8_t *buf,
const int len)
{
struct uart_async_to_irq_data *data = get_data(dev);
const struct uart_async_to_irq_config *config = get_config(dev);
struct uart_async_rx *async_rx = &data->rx.async_rx;
size_t claim_len;
uint8_t *claim_buf;
claim_len = uart_async_rx_data_claim(async_rx, &claim_buf, len);
if (claim_len == 0) {
return 0;
}
memcpy(buf, claim_buf, claim_len);
bool buf_available = uart_async_rx_data_consume(async_rx, claim_len);
if (data->rx.pending_buf_req && buf_available) {
buf = uart_async_rx_buf_req(async_rx);
__ASSERT_NO_MSG(buf != NULL);
int err;
size_t rx_len = uart_async_rx_get_buf_len(async_rx);
atomic_dec(&data->rx.pending_buf_req);
err = config->api->rx_buf_rsp(dev, buf, rx_len);
if (err < 0) {
if (err == -EACCES) {
data->rx.pending_buf_req = 0;
err = rx_enable(dev, data, buf, rx_len);
}
if (err < 0) {
return err;
}
}
}
return (int)claim_len;
}
static void dir_disable(const struct device *dev, uint32_t flag)
{
struct uart_async_to_irq_data *data = get_data(dev);
atomic_and(&data->flags, ~flag);
}
static void dir_enable(const struct device *dev, uint32_t flag)
{
struct uart_async_to_irq_data *data = get_data(dev);
atomic_or(&data->flags, flag);
atomic_inc(&data->irq_req);
get_config(dev)->trampoline(dev);
}
/** Interrupt driven transfer enabling function */
void z_uart_async_to_irq_irq_tx_enable(const struct device *dev)
{
dir_enable(dev, A2I_TX_IRQ_ENABLED);
}
/** Interrupt driven transfer disabling function */
void z_uart_async_to_irq_irq_tx_disable(const struct device *dev)
{
dir_disable(dev, A2I_TX_IRQ_ENABLED);
}
/** Interrupt driven transfer ready function */
int z_uart_async_to_irq_irq_tx_ready(const struct device *dev)
{
struct uart_async_to_irq_data *data = get_data(dev);
return (data->flags & A2I_TX_IRQ_ENABLED) && !(data->flags & A2I_TX_BUSY);
}
/** Interrupt driven receiver enabling function */
void z_uart_async_to_irq_irq_rx_enable(const struct device *dev)
{
dir_enable(dev, A2I_RX_IRQ_ENABLED);
}
/** Interrupt driven receiver disabling function */
void z_uart_async_to_irq_irq_rx_disable(const struct device *dev)
{
dir_disable(dev, A2I_RX_IRQ_ENABLED);
}
/** Interrupt driven transfer complete function */
int z_uart_async_to_irq_irq_tx_complete(const struct device *dev)
{
return z_uart_async_to_irq_irq_tx_ready(dev);
}
/** Interrupt driven receiver ready function */
int z_uart_async_to_irq_irq_rx_ready(const struct device *dev)
{
struct uart_async_to_irq_data *data = get_data(dev);
return (data->flags & A2I_RX_IRQ_ENABLED) && (data->rx.async_rx.pending_bytes > 0);
}
/** Interrupt driven error enabling function */
void z_uart_async_to_irq_irq_err_enable(const struct device *dev)
{
dir_enable(dev, A2I_ERR_IRQ_ENABLED);
}
/** Interrupt driven error disabling function */
void z_uart_async_to_irq_irq_err_disable(const struct device *dev)
{
dir_disable(dev, A2I_ERR_IRQ_ENABLED);
}
/** Interrupt driven pending status function */
int z_uart_async_to_irq_irq_is_pending(const struct device *dev)
{
return z_uart_async_to_irq_irq_tx_ready(dev) || z_uart_async_to_irq_irq_rx_ready(dev);
}
/** Interrupt driven interrupt update function */
int z_uart_async_to_irq_irq_update(const struct device *dev)
{
return 1;
}
/** Set the irq callback function */
void z_uart_async_to_irq_irq_callback_set(const struct device *dev,
uart_irq_callback_user_data_t cb,
void *user_data)
{
struct uart_async_to_irq_data *data = get_data(dev);
data->callback = cb;
data->user_data = user_data;
}
int uart_async_to_irq_rx_enable(const struct device *dev)
{
struct uart_async_to_irq_data *data = get_data(dev);
const struct uart_async_to_irq_config *config = get_config(dev);
int err;
err = config->api->callback_set(dev, uart_async_to_irq_callback, data);
if (err < 0) {
return err;
}
err = try_rx_enable(dev, data);
if (err == 0) {
atomic_or(&data->flags, A2I_RX_ENABLE);
}
return err;
}
int uart_async_to_irq_rx_disable(const struct device *dev)
{
struct uart_async_to_irq_data *data = get_data(dev);
const struct uart_async_to_irq_config *config = get_config(dev);
int err;
if (atomic_and(&data->flags, ~A2I_RX_ENABLE) & A2I_RX_ENABLE) {
err = config->api->rx_disable(dev);
if (err < 0) {
return err;
}
k_sem_take(&data->rx.sem, K_FOREVER);
}
uart_async_rx_reset(&data->rx.async_rx);
return 0;
}
void uart_async_to_irq_trampoline_cb(const struct device *dev)
{
struct uart_async_to_irq_data *data = get_data(dev);
do {
data->callback(dev, data->user_data);
} while (atomic_dec(&data->irq_req) > 1);
}
int uart_async_to_irq_init(struct uart_async_to_irq_data *data,
const struct uart_async_to_irq_config *config)
{
data->tx.buf = config->tx_buf;
data->tx.len = config->tx_len;
k_sem_init(&data->rx.sem, 0, 1);
return uart_async_rx_init(&data->rx.async_rx, &config->async_rx);
}
``` | /content/code_sandbox/drivers/serial/uart_async_to_irq.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 2,541 |
```unknown
config UART_ENE_KB1200
bool "ENE KB1200 serial driver"
default y
depends on DT_HAS_ENE_KB1200_UART_ENABLED
select SERIAL_HAS_DRIVER
select SERIAL_SUPPORT_INTERRUPT
select PINCTRL
help
This option enables the KB1200 serial driver.
``` | /content/code_sandbox/drivers/serial/Kconfig.ene | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 64 |
```unknown
# Telink B91 UART configuration options
config UART_TELINK_B91
bool "Telink B91 UART driver"
default y
depends on DT_HAS_TELINK_B91_UART_ENABLED
select SERIAL_HAS_DRIVER
select SERIAL_SUPPORT_INTERRUPT
help
This option enables the B91 serial driver.
``` | /content/code_sandbox/drivers/serial/Kconfig.b91 | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 66 |
```unknown
config UART_RPI_PICO_PIO
bool "Raspberry Pi PIO UART driver"
default y
depends on DT_HAS_RASPBERRYPI_PICO_UART_PIO_ENABLED
select SERIAL_HAS_DRIVER
select PICOSDK_USE_PIO
select PICOSDK_USE_CLAIM
depends on RESET
``` | /content/code_sandbox/drivers/serial/Kconfig.rpi_pico | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 66 |
```c
/*
*
*/
#define DT_DRV_COMPAT openisa_rv32m1_lpuart
#include <errno.h>
#include <zephyr/device.h>
#include <zephyr/drivers/uart.h>
#include <zephyr/drivers/clock_control.h>
#include <zephyr/irq.h>
#include <fsl_lpuart.h>
#include <soc.h>
#include <zephyr/drivers/pinctrl.h>
struct rv32m1_lpuart_config {
LPUART_Type *base;
const struct device *clock_dev;
clock_control_subsys_t clock_subsys;
clock_ip_name_t clock_ip_name;
uint32_t clock_ip_src;
uint32_t baud_rate;
uint8_t hw_flow_control;
#ifdef CONFIG_UART_INTERRUPT_DRIVEN
void (*irq_config_func)(const struct device *dev);
#endif
const struct pinctrl_dev_config *pincfg;
};
struct rv32m1_lpuart_data {
#ifdef CONFIG_UART_INTERRUPT_DRIVEN
uart_irq_callback_user_data_t callback;
void *cb_data;
#endif
};
static int rv32m1_lpuart_poll_in(const struct device *dev, unsigned char *c)
{
const struct rv32m1_lpuart_config *config = dev->config;
uint32_t flags = LPUART_GetStatusFlags(config->base);
int ret = -1;
if (flags & kLPUART_RxDataRegFullFlag) {
*c = LPUART_ReadByte(config->base);
ret = 0;
}
return ret;
}
static void rv32m1_lpuart_poll_out(const struct device *dev, unsigned char c)
{
const struct rv32m1_lpuart_config *config = dev->config;
while (!(LPUART_GetStatusFlags(config->base)
& kLPUART_TxDataRegEmptyFlag)) {
}
LPUART_WriteByte(config->base, c);
}
static int rv32m1_lpuart_err_check(const struct device *dev)
{
const struct rv32m1_lpuart_config *config = dev->config;
uint32_t flags = LPUART_GetStatusFlags(config->base);
int err = 0;
if (flags & kLPUART_RxOverrunFlag) {
err |= UART_ERROR_OVERRUN;
}
if (flags & kLPUART_ParityErrorFlag) {
err |= UART_ERROR_PARITY;
}
if (flags & kLPUART_FramingErrorFlag) {
err |= UART_ERROR_FRAMING;
}
LPUART_ClearStatusFlags(config->base, kLPUART_RxOverrunFlag |
kLPUART_ParityErrorFlag |
kLPUART_FramingErrorFlag);
return err;
}
#ifdef CONFIG_UART_INTERRUPT_DRIVEN
static int rv32m1_lpuart_fifo_fill(const struct device *dev,
const uint8_t *tx_data,
int len)
{
const struct rv32m1_lpuart_config *config = dev->config;
uint8_t num_tx = 0U;
while ((len - num_tx > 0) &&
(LPUART_GetStatusFlags(config->base)
& kLPUART_TxDataRegEmptyFlag)) {
LPUART_WriteByte(config->base, tx_data[num_tx++]);
}
return num_tx;
}
static int rv32m1_lpuart_fifo_read(const struct device *dev, uint8_t *rx_data,
const int len)
{
const struct rv32m1_lpuart_config *config = dev->config;
uint8_t num_rx = 0U;
while ((len - num_rx > 0) &&
(LPUART_GetStatusFlags(config->base)
& kLPUART_RxDataRegFullFlag)) {
rx_data[num_rx++] = LPUART_ReadByte(config->base);
}
return num_rx;
}
static void rv32m1_lpuart_irq_tx_enable(const struct device *dev)
{
const struct rv32m1_lpuart_config *config = dev->config;
uint32_t mask = kLPUART_TxDataRegEmptyInterruptEnable;
LPUART_EnableInterrupts(config->base, mask);
}
static void rv32m1_lpuart_irq_tx_disable(const struct device *dev)
{
const struct rv32m1_lpuart_config *config = dev->config;
uint32_t mask = kLPUART_TxDataRegEmptyInterruptEnable;
LPUART_DisableInterrupts(config->base, mask);
}
static int rv32m1_lpuart_irq_tx_complete(const struct device *dev)
{
const struct rv32m1_lpuart_config *config = dev->config;
uint32_t flags = LPUART_GetStatusFlags(config->base);
return (flags & kLPUART_TxDataRegEmptyFlag) != 0U;
}
static int rv32m1_lpuart_irq_tx_ready(const struct device *dev)
{
const struct rv32m1_lpuart_config *config = dev->config;
uint32_t mask = kLPUART_TxDataRegEmptyInterruptEnable;
return (LPUART_GetEnabledInterrupts(config->base) & mask)
&& rv32m1_lpuart_irq_tx_complete(dev);
}
static void rv32m1_lpuart_irq_rx_enable(const struct device *dev)
{
const struct rv32m1_lpuart_config *config = dev->config;
uint32_t mask = kLPUART_RxDataRegFullInterruptEnable;
LPUART_EnableInterrupts(config->base, mask);
}
static void rv32m1_lpuart_irq_rx_disable(const struct device *dev)
{
const struct rv32m1_lpuart_config *config = dev->config;
uint32_t mask = kLPUART_RxDataRegFullInterruptEnable;
LPUART_DisableInterrupts(config->base, mask);
}
static int rv32m1_lpuart_irq_rx_full(const struct device *dev)
{
const struct rv32m1_lpuart_config *config = dev->config;
uint32_t flags = LPUART_GetStatusFlags(config->base);
return (flags & kLPUART_RxDataRegFullFlag) != 0U;
}
static int rv32m1_lpuart_irq_rx_pending(const struct device *dev)
{
const struct rv32m1_lpuart_config *config = dev->config;
uint32_t mask = kLPUART_RxDataRegFullInterruptEnable;
return (LPUART_GetEnabledInterrupts(config->base) & mask)
&& rv32m1_lpuart_irq_rx_full(dev);
}
static void rv32m1_lpuart_irq_err_enable(const struct device *dev)
{
const struct rv32m1_lpuart_config *config = dev->config;
uint32_t mask = kLPUART_NoiseErrorInterruptEnable |
kLPUART_FramingErrorInterruptEnable |
kLPUART_ParityErrorInterruptEnable;
LPUART_EnableInterrupts(config->base, mask);
}
static void rv32m1_lpuart_irq_err_disable(const struct device *dev)
{
const struct rv32m1_lpuart_config *config = dev->config;
uint32_t mask = kLPUART_NoiseErrorInterruptEnable |
kLPUART_FramingErrorInterruptEnable |
kLPUART_ParityErrorInterruptEnable;
LPUART_DisableInterrupts(config->base, mask);
}
static int rv32m1_lpuart_irq_is_pending(const struct device *dev)
{
return (rv32m1_lpuart_irq_tx_ready(dev)
|| rv32m1_lpuart_irq_rx_pending(dev));
}
static int rv32m1_lpuart_irq_update(const struct device *dev)
{
return 1;
}
static void rv32m1_lpuart_irq_callback_set(const struct device *dev,
uart_irq_callback_user_data_t cb,
void *cb_data)
{
struct rv32m1_lpuart_data *data = dev->data;
data->callback = cb;
data->cb_data = cb_data;
}
static void rv32m1_lpuart_isr(const struct device *dev)
{
struct rv32m1_lpuart_data *data = dev->data;
if (data->callback) {
data->callback(dev, data->cb_data);
}
}
#endif /* CONFIG_UART_INTERRUPT_DRIVEN */
static int rv32m1_lpuart_init(const struct device *dev)
{
const struct rv32m1_lpuart_config *config = dev->config;
lpuart_config_t uart_config;
uint32_t clock_freq;
int err;
/* set clock source */
/* TODO: Don't change if another core has configured */
CLOCK_SetIpSrc(config->clock_ip_name, config->clock_ip_src);
if (!device_is_ready(config->clock_dev)) {
return -ENODEV;
}
if (clock_control_get_rate(config->clock_dev, config->clock_subsys,
&clock_freq)) {
return -EINVAL;
}
LPUART_GetDefaultConfig(&uart_config);
uart_config.enableTx = true;
uart_config.enableRx = true;
if (config->hw_flow_control) {
uart_config.enableRxRTS = true;
uart_config.enableTxCTS = true;
}
uart_config.baudRate_Bps = config->baud_rate;
LPUART_Init(config->base, &uart_config, clock_freq);
err = pinctrl_apply_state(config->pincfg, PINCTRL_STATE_DEFAULT);
if (err != 0) {
return err;
}
#ifdef CONFIG_UART_INTERRUPT_DRIVEN
config->irq_config_func(dev);
#endif
return 0;
}
static const struct uart_driver_api rv32m1_lpuart_driver_api = {
.poll_in = rv32m1_lpuart_poll_in,
.poll_out = rv32m1_lpuart_poll_out,
.err_check = rv32m1_lpuart_err_check,
#ifdef CONFIG_UART_INTERRUPT_DRIVEN
.fifo_fill = rv32m1_lpuart_fifo_fill,
.fifo_read = rv32m1_lpuart_fifo_read,
.irq_tx_enable = rv32m1_lpuart_irq_tx_enable,
.irq_tx_disable = rv32m1_lpuart_irq_tx_disable,
.irq_tx_complete = rv32m1_lpuart_irq_tx_complete,
.irq_tx_ready = rv32m1_lpuart_irq_tx_ready,
.irq_rx_enable = rv32m1_lpuart_irq_rx_enable,
.irq_rx_disable = rv32m1_lpuart_irq_rx_disable,
.irq_rx_ready = rv32m1_lpuart_irq_rx_full,
.irq_err_enable = rv32m1_lpuart_irq_err_enable,
.irq_err_disable = rv32m1_lpuart_irq_err_disable,
.irq_is_pending = rv32m1_lpuart_irq_is_pending,
.irq_update = rv32m1_lpuart_irq_update,
.irq_callback_set = rv32m1_lpuart_irq_callback_set,
#endif
};
#define RV32M1_LPUART_DECLARE_CFG(n, IRQ_FUNC_INIT) \
static const struct rv32m1_lpuart_config rv32m1_lpuart_##n##_cfg = {\
.base = (LPUART_Type *)DT_INST_REG_ADDR(n), \
.clock_dev = DEVICE_DT_GET(DT_INST_CLOCKS_CTLR(n)), \
.clock_subsys = \
(clock_control_subsys_t)DT_INST_CLOCKS_CELL(n, name),\
.clock_ip_name = INST_DT_CLOCK_IP_NAME(n), \
.clock_ip_src = kCLOCK_IpSrcFircAsync, \
.baud_rate = DT_INST_PROP(n, current_speed), \
.hw_flow_control = DT_INST_PROP(n, hw_flow_control), \
.pincfg = PINCTRL_DT_INST_DEV_CONFIG_GET(n), \
IRQ_FUNC_INIT \
}
#ifdef CONFIG_UART_INTERRUPT_DRIVEN
#define RV32M1_LPUART_CONFIG_FUNC(n) \
static void rv32m1_lpuart_config_func_##n(const struct device *dev) \
{ \
IRQ_CONNECT(DT_INST_IRQN(n), 0, rv32m1_lpuart_isr, \
DEVICE_DT_INST_GET(n), 0); \
\
irq_enable(DT_INST_IRQN(n)); \
}
#define RV32M1_LPUART_IRQ_CFG_FUNC_INIT(n) \
.irq_config_func = rv32m1_lpuart_config_func_##n,
#define RV32M1_LPUART_INIT_CFG(n) \
RV32M1_LPUART_DECLARE_CFG(n, RV32M1_LPUART_IRQ_CFG_FUNC_INIT(n))
#else
#define RV32M1_LPUART_CONFIG_FUNC(n)
#define RV32M1_LPUART_IRQ_CFG_FUNC_INIT
#define RV32M1_LPUART_INIT_CFG(n) \
RV32M1_LPUART_DECLARE_CFG(n, RV32M1_LPUART_IRQ_CFG_FUNC_INIT)
#endif
#define RV32M1_LPUART_INIT(n) \
PINCTRL_DT_INST_DEFINE(n); \
\
static struct rv32m1_lpuart_data rv32m1_lpuart_##n##_data; \
\
static const struct rv32m1_lpuart_config rv32m1_lpuart_##n##_cfg;\
\
DEVICE_DT_INST_DEFINE(n, \
rv32m1_lpuart_init, \
NULL, \
&rv32m1_lpuart_##n##_data, \
&rv32m1_lpuart_##n##_cfg, \
PRE_KERNEL_1, \
CONFIG_SERIAL_INIT_PRIORITY, \
&rv32m1_lpuart_driver_api); \
\
RV32M1_LPUART_CONFIG_FUNC(n) \
\
RV32M1_LPUART_INIT_CFG(n);
DT_INST_FOREACH_STATUS_OKAY(RV32M1_LPUART_INIT)
``` | /content/code_sandbox/drivers/serial/uart_rv32m1_lpuart.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 3,031 |
```unknown
config LP5562
bool "LP5562 LED driver"
default y
depends on DT_HAS_TI_LP5562_ENABLED
select I2C
help
Enable LED driver for LP5562.
LP5562 LED driver has 4 channels (RGBW). Each channel can drive up to
25.5 mA per LED.
``` | /content/code_sandbox/drivers/led/Kconfig.lp5562 | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 75 |
```c
/*
*
*/
#define DT_DRV_COMPAT gpio_leds
/**
* @file
* @brief GPIO driven LEDs
*/
#include <zephyr/drivers/led.h>
#include <zephyr/drivers/gpio.h>
#include <zephyr/device.h>
#include <zephyr/kernel.h>
#include <zephyr/logging/log.h>
LOG_MODULE_REGISTER(led_gpio, CONFIG_LED_LOG_LEVEL);
struct led_gpio_config {
size_t num_leds;
const struct gpio_dt_spec *led;
};
static int led_gpio_set_brightness(const struct device *dev, uint32_t led, uint8_t value)
{
const struct led_gpio_config *config = dev->config;
const struct gpio_dt_spec *led_gpio;
if ((led >= config->num_leds) || (value > 100)) {
return -EINVAL;
}
led_gpio = &config->led[led];
return gpio_pin_set_dt(led_gpio, value > 0);
}
static int led_gpio_on(const struct device *dev, uint32_t led)
{
return led_gpio_set_brightness(dev, led, 100);
}
static int led_gpio_off(const struct device *dev, uint32_t led)
{
return led_gpio_set_brightness(dev, led, 0);
}
static int led_gpio_init(const struct device *dev)
{
const struct led_gpio_config *config = dev->config;
int err = 0;
if (!config->num_leds) {
LOG_ERR("%s: no LEDs found (DT child nodes missing)", dev->name);
err = -ENODEV;
}
for (size_t i = 0; (i < config->num_leds) && !err; i++) {
const struct gpio_dt_spec *led = &config->led[i];
if (device_is_ready(led->port)) {
err = gpio_pin_configure_dt(led, GPIO_OUTPUT_INACTIVE);
if (err) {
LOG_ERR("Cannot configure GPIO (err %d)", err);
}
} else {
LOG_ERR("%s: GPIO device not ready", dev->name);
err = -ENODEV;
}
}
return err;
}
static const struct led_driver_api led_gpio_api = {
.on = led_gpio_on,
.off = led_gpio_off,
.set_brightness = led_gpio_set_brightness,
};
#define LED_GPIO_DEVICE(i) \
\
static const struct gpio_dt_spec gpio_dt_spec_##i[] = { \
DT_INST_FOREACH_CHILD_SEP_VARGS(i, GPIO_DT_SPEC_GET, (,), gpios) \
}; \
\
static const struct led_gpio_config led_gpio_config_##i = { \
.num_leds = ARRAY_SIZE(gpio_dt_spec_##i), \
.led = gpio_dt_spec_##i, \
}; \
\
DEVICE_DT_INST_DEFINE(i, &led_gpio_init, NULL, \
NULL, &led_gpio_config_##i, \
POST_KERNEL, CONFIG_LED_INIT_PRIORITY, \
&led_gpio_api);
DT_INST_FOREACH_STATUS_OKAY(LED_GPIO_DEVICE)
``` | /content/code_sandbox/drivers/led/led_gpio.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 656 |
```unknown
config IS31FL3194
bool "IS31FL3194 LED driver"
default y
depends on DT_HAS_ISSI_IS31FL3194_ENABLED
select I2C
help
Enable LED driver for Lumissil Microsystems (a division of ISSI)
IS31FL3194. This chip supports one RGB LED or 3 independent LEDs.
``` | /content/code_sandbox/drivers/led/Kconfig.is31fl3194 | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 78 |
```unknown
config LP50XX
bool "LP50XX LED controller"
default y
depends on DT_HAS_TI_LP5009_ENABLED || DT_HAS_TI_LP5012_ENABLED || \
DT_HAS_TI_LP5018_ENABLED || DT_HAS_TI_LP5024_ENABLED || \
DT_HAS_TI_LP5030_ENABLED || DT_HAS_TI_LP5036_ENABLED
select I2C
help
Enable driver for the Texas Instruments LP50XX I2C LED
controllers. It supports: LP5009, LP5012, LP5018, LP5024,
LP5030 and LP5036.
``` | /content/code_sandbox/drivers/led/Kconfig.lp50xx | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 126 |
```c
/*
*
*/
#define DT_DRV_COMPAT ti_lp3943
/**
* @file
* @brief LP3943 LED driver
*
* Limitations:
* - Blink period and brightness value are controlled by two sets of PSCx/PWMx
* registers. This driver partitions the available LEDs into two groups as
* 0 to 7 and 8 to 15 and assigns PSC0/PWM0 to LEDs from 0 to 7 and PSC1/PWM1
* to LEDs from 8 to 15. So, it is not possible to set unique blink period
* and brightness value for LEDs in a group, changing either of these
* values for a LED will affect other LEDs also.
*/
#include <zephyr/drivers/i2c.h>
#include <zephyr/drivers/led.h>
#include <zephyr/sys/util.h>
#include <zephyr/kernel.h>
#define LOG_LEVEL CONFIG_LED_LOG_LEVEL
#include <zephyr/logging/log.h>
LOG_MODULE_REGISTER(lp3943);
#include "led_context.h"
/* LP3943 Registers */
#define LP3943_INPUT_1 0x00
#define LP3943_INPUT_2 0x01
#define LP3943_PSC0 0x02
#define LP3943_PWM0 0x03
#define LP3943_PSC1 0x04
#define LP3943_PWM1 0x05
#define LP3943_LS0 0x06
#define LP3943_LS1 0x07
#define LP3943_LS2 0x08
#define LP3943_LS3 0x09
#define LP3943_MASK 0x03
enum lp3943_modes {
LP3943_OFF,
LP3943_ON,
LP3943_DIM0,
LP3943_DIM1,
};
struct lp3943_config {
struct i2c_dt_spec bus;
};
struct lp3943_data {
struct led_data dev_data;
};
static int lp3943_get_led_reg(uint32_t *led, uint8_t *reg)
{
switch (*led) {
case 0:
case 1:
case 2:
__fallthrough;
case 3:
*reg = LP3943_LS0;
break;
case 4:
case 5:
case 6:
__fallthrough;
case 7:
*reg = LP3943_LS1;
*led -= 4U;
break;
case 8:
case 9:
case 10:
__fallthrough;
case 11:
*reg = LP3943_LS2;
*led -= 8U;
break;
case 12:
case 13:
case 14:
__fallthrough;
case 15:
*reg = LP3943_LS3;
*led -= 12U;
break;
default:
LOG_ERR("Invalid LED specified");
return -EINVAL;
}
return 0;
}
static int lp3943_set_dim_states(const struct lp3943_config *config,
uint32_t led, uint8_t mode)
{
int ret;
uint8_t reg;
ret = lp3943_get_led_reg(&led, ®);
if (ret) {
return ret;
}
/* Set DIMx states for the LEDs */
if (i2c_reg_update_byte_dt(&config->bus, reg, LP3943_MASK << (led << 1),
mode << (led << 1))) {
LOG_ERR("LED reg update failed");
return -EIO;
}
return 0;
}
static int lp3943_led_blink(const struct device *dev, uint32_t led,
uint32_t delay_on, uint32_t delay_off)
{
const struct lp3943_config *config = dev->config;
struct lp3943_data *data = dev->data;
struct led_data *dev_data = &data->dev_data;
int ret;
uint16_t period;
uint8_t reg, val, mode;
period = delay_on + delay_off;
if (period < dev_data->min_period || period > dev_data->max_period) {
return -EINVAL;
}
/* Use DIM0 for LEDs 0 to 7 and DIM1 for LEDs 8 to 15 */
if (led < 8) {
mode = LP3943_DIM0;
} else {
mode = LP3943_DIM1;
}
if (mode == LP3943_DIM0) {
reg = LP3943_PSC0;
} else {
reg = LP3943_PSC1;
}
val = (period * 255U) / dev_data->max_period;
if (i2c_reg_write_byte_dt(&config->bus, reg, val)) {
LOG_ERR("LED write failed");
return -EIO;
}
ret = lp3943_set_dim_states(config, led, mode);
if (ret) {
return ret;
}
return 0;
}
static int lp3943_led_set_brightness(const struct device *dev, uint32_t led,
uint8_t value)
{
const struct lp3943_config *config = dev->config;
struct lp3943_data *data = dev->data;
struct led_data *dev_data = &data->dev_data;
int ret;
uint8_t reg, val, mode;
if (value < dev_data->min_brightness ||
value > dev_data->max_brightness) {
return -EINVAL;
}
/* Use DIM0 for LEDs 0 to 7 and DIM1 for LEDs 8 to 15 */
if (led < 8) {
mode = LP3943_DIM0;
} else {
mode = LP3943_DIM1;
}
if (mode == LP3943_DIM0) {
reg = LP3943_PWM0;
} else {
reg = LP3943_PWM1;
}
val = (value * 255U) / dev_data->max_brightness;
if (i2c_reg_write_byte_dt(&config->bus, reg, val)) {
LOG_ERR("LED write failed");
return -EIO;
}
ret = lp3943_set_dim_states(config, led, mode);
if (ret) {
return ret;
}
return 0;
}
static inline int lp3943_led_on(const struct device *dev, uint32_t led)
{
const struct lp3943_config *config = dev->config;
int ret;
uint8_t reg, mode;
ret = lp3943_get_led_reg(&led, ®);
if (ret) {
return ret;
}
/* Set LED state to ON */
mode = LP3943_ON;
if (i2c_reg_update_byte_dt(&config->bus, reg, LP3943_MASK << (led << 1),
mode << (led << 1))) {
LOG_ERR("LED reg update failed");
return -EIO;
}
return 0;
}
static inline int lp3943_led_off(const struct device *dev, uint32_t led)
{
const struct lp3943_config *config = dev->config;
int ret;
uint8_t reg;
ret = lp3943_get_led_reg(&led, ®);
if (ret) {
return ret;
}
/* Set LED state to OFF */
if (i2c_reg_update_byte_dt(&config->bus, reg, LP3943_MASK << (led << 1),
0)) {
LOG_ERR("LED reg update failed");
return -EIO;
}
return 0;
}
static int lp3943_led_init(const struct device *dev)
{
const struct lp3943_config *config = dev->config;
struct lp3943_data *data = dev->data;
struct led_data *dev_data = &data->dev_data;
if (!device_is_ready(config->bus.bus)) {
LOG_ERR("I2C device not ready");
return -ENODEV;
}
/* Hardware specific limits */
dev_data->min_period = 0U;
dev_data->max_period = 1600U;
dev_data->min_brightness = 0U;
dev_data->max_brightness = 100U;
return 0;
}
static struct lp3943_data lp3943_led_data;
static const struct lp3943_config lp3943_led_config = {
.bus = I2C_DT_SPEC_INST_GET(0),
};
static const struct led_driver_api lp3943_led_api = {
.blink = lp3943_led_blink,
.set_brightness = lp3943_led_set_brightness,
.on = lp3943_led_on,
.off = lp3943_led_off,
};
DEVICE_DT_INST_DEFINE(0, &lp3943_led_init, NULL, &lp3943_led_data,
&lp3943_led_config, POST_KERNEL, CONFIG_LED_INIT_PRIORITY,
&lp3943_led_api);
``` | /content/code_sandbox/drivers/led/lp3943.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 1,876 |
```unknown
config LED_GPIO
bool "GPIO LED driver"
default y
depends on GPIO && DT_HAS_GPIO_LEDS_ENABLED
help
Enable driver for GPIO LEDs.
``` | /content/code_sandbox/drivers/led/Kconfig.gpio | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 36 |
```c
/*
*
*/
#include <zephyr/internal/syscall_handler.h>
#include <zephyr/drivers/led.h>
static inline int z_vrfy_led_blink(const struct device *dev, uint32_t led,
uint32_t delay_on, uint32_t delay_off)
{
K_OOPS(K_SYSCALL_DRIVER_LED(dev, blink));
return z_impl_led_blink((const struct device *)dev, led, delay_on,
delay_off);
}
#include <zephyr/syscalls/led_blink_mrsh.c>
static inline int z_vrfy_led_get_info(const struct device *dev, uint32_t led,
const struct led_info **info)
{
K_OOPS(K_SYSCALL_OBJ(dev, K_OBJ_DRIVER_LED));
K_OOPS(K_SYSCALL_MEMORY_WRITE(info, sizeof(*info)));
return z_impl_led_get_info(dev, led, info);
}
#include <zephyr/syscalls/led_get_info_mrsh.c>
static inline int z_vrfy_led_set_brightness(const struct device *dev,
uint32_t led,
uint8_t value)
{
K_OOPS(K_SYSCALL_DRIVER_LED(dev, set_brightness));
return z_impl_led_set_brightness((const struct device *)dev, led,
value);
}
#include <zephyr/syscalls/led_set_brightness_mrsh.c>
static inline int
z_vrfy_led_write_channels(const struct device *dev, uint32_t start_channel,
uint32_t num_channels, const uint8_t *buf)
{
K_OOPS(K_SYSCALL_OBJ(dev, K_OBJ_DRIVER_LED));
K_OOPS(K_SYSCALL_MEMORY_READ(buf, num_channels));
return z_impl_led_write_channels(dev, start_channel, num_channels, buf);
}
#include <zephyr/syscalls/led_write_channels_mrsh.c>
static inline int z_vrfy_led_set_channel(const struct device *dev,
uint32_t channel, uint8_t value)
{
K_OOPS(K_SYSCALL_OBJ(dev, K_OBJ_DRIVER_LED));
return z_impl_led_set_channel(dev, channel, value);
}
#include <zephyr/syscalls/led_set_channel_mrsh.c>
static inline int z_vrfy_led_set_color(const struct device *dev, uint32_t led,
uint8_t num_colors, const uint8_t *color)
{
K_OOPS(K_SYSCALL_OBJ(dev, K_OBJ_DRIVER_LED));
K_OOPS(K_SYSCALL_MEMORY_READ(color, num_colors));
return z_impl_led_set_color(dev, led, num_colors, color);
}
#include <zephyr/syscalls/led_set_color_mrsh.c>
static inline int z_vrfy_led_on(const struct device *dev, uint32_t led)
{
K_OOPS(K_SYSCALL_DRIVER_LED(dev, on));
return z_impl_led_on((const struct device *)dev, led);
}
#include <zephyr/syscalls/led_on_mrsh.c>
static inline int z_vrfy_led_off(const struct device *dev, uint32_t led)
{
K_OOPS(K_SYSCALL_DRIVER_LED(dev, off));
return z_impl_led_off((const struct device *)dev, led);
}
#include <zephyr/syscalls/led_off_mrsh.c>
``` | /content/code_sandbox/drivers/led/led_handlers.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 657 |
```c
/*
*
*/
#define DT_DRV_COMPAT issi_is31fl3194
/**
* @file
* @brief IS31FL3194 LED driver
*
* The IS31FL3194 is a 3-channel LED driver that communicates over I2C.
*/
#include <zephyr/device.h>
#include <zephyr/drivers/i2c.h>
#include <zephyr/drivers/led.h>
#include <zephyr/kernel.h>
#include <zephyr/logging/log.h>
#include <zephyr/dt-bindings/led/led.h>
LOG_MODULE_REGISTER(is31fl3194, CONFIG_LED_LOG_LEVEL);
#define IS31FL3194_PROD_ID_REG 0x00
#define IS31FL3194_CONF_REG 0x01
#define IS31FL3194_CURRENT_REG 0x03
#define IS31FL3194_OUT1_REG 0x10
#define IS31FL3194_OUT2_REG 0x21
#define IS31FL3194_OUT3_REG 0x32
#define IS31FL3194_UPDATE_REG 0x40
#define IS31FL3194_PROD_ID_VAL 0xce
#define IS31FL3194_CONF_ENABLE 0x01
#define IS31FL3194_UPDATE_VAL 0xc5
#define IS31FL3194_CHANNEL_COUNT 3
static const uint8_t led_channels[] = {
IS31FL3194_OUT1_REG,
IS31FL3194_OUT2_REG,
IS31FL3194_OUT3_REG
};
struct is31fl3194_config {
struct i2c_dt_spec bus;
uint8_t num_leds;
const struct led_info *led_infos;
const uint8_t *current_limits;
};
static const struct led_info *is31fl3194_led_to_info(const struct is31fl3194_config *config,
uint32_t led)
{
if (led < config->num_leds) {
return &config->led_infos[led];
}
return NULL;
}
static int is31fl3194_get_info(const struct device *dev,
uint32_t led,
const struct led_info **info_out)
{
const struct is31fl3194_config *config = dev->config;
const struct led_info *info = is31fl3194_led_to_info(config, led);
if (info == NULL) {
return -EINVAL;
}
*info_out = info;
return 0;
}
static int is31fl3194_set_color(const struct device *dev, uint32_t led, uint8_t num_colors,
const uint8_t *color)
{
const struct is31fl3194_config *config = dev->config;
const struct led_info *info = is31fl3194_led_to_info(config, led);
int ret;
if (info == NULL) {
return -ENODEV;
}
if (info->num_colors != 3) {
return -ENOTSUP;
}
if (num_colors != 3) {
return -EINVAL;
}
for (int i = 0; i < 3; i++) {
uint8_t value;
switch (info->color_mapping[i]) {
case LED_COLOR_ID_RED:
value = color[0];
break;
case LED_COLOR_ID_GREEN:
value = color[1];
break;
case LED_COLOR_ID_BLUE:
value = color[2];
break;
default:
/* unreachable: mapping already tested in is31fl3194_check_config */
continue;
}
ret = i2c_reg_write_byte_dt(&config->bus, led_channels[i], value);
if (ret != 0) {
break;
}
}
if (ret == 0) {
ret = i2c_reg_write_byte_dt(&config->bus,
IS31FL3194_UPDATE_REG,
IS31FL3194_UPDATE_VAL);
}
if (ret != 0) {
LOG_ERR("%s: LED write failed: %d", dev->name, ret);
}
return ret;
}
static int is31fl3194_set_brightness(const struct device *dev, uint32_t led, uint8_t value)
{
const struct is31fl3194_config *config = dev->config;
const struct led_info *info = is31fl3194_led_to_info(config, led);
int ret = 0;
if (info == NULL) {
return -ENODEV;
}
if (info->num_colors != 1) {
return -ENOTSUP;
}
if (value > 100) {
return -EINVAL;
}
/* Rescale 0..100 to 0..255 */
value = value * 255 / 100;
ret = i2c_reg_write_byte_dt(&config->bus, led_channels[led], value);
if (ret == 0) {
ret = i2c_reg_write_byte_dt(&config->bus,
IS31FL3194_UPDATE_REG,
IS31FL3194_UPDATE_VAL);
}
if (ret != 0) {
LOG_ERR("%s: LED write failed", dev->name);
}
return ret;
}
static inline int is31fl3194_led_on(const struct device *dev, uint32_t led)
{
return is31fl3194_set_brightness(dev, led, 100);
}
static inline int is31fl3194_led_off(const struct device *dev, uint32_t led)
{
return is31fl3194_set_brightness(dev, led, 0);
}
/*
* Counts red, green, blue channels; returns true if color_id is valid
* and no more than one channel maps to the same color
*/
static bool is31fl3194_count_colors(const struct device *dev,
uint8_t color_id, uint8_t *rgb_counts)
{
bool ret = false;
switch (color_id) {
case LED_COLOR_ID_RED:
ret = (++rgb_counts[0] == 1);
break;
case LED_COLOR_ID_GREEN:
ret = (++rgb_counts[1] == 1);
break;
case LED_COLOR_ID_BLUE:
ret = (++rgb_counts[2] == 1);
break;
}
if (!ret) {
LOG_ERR("%s: invalid color %d (duplicate or not RGB)",
dev->name, color_id);
}
return ret;
}
static int is31fl3194_check_config(const struct device *dev)
{
const struct is31fl3194_config *config = dev->config;
const struct led_info *info;
uint8_t rgb_counts[3] = { 0 };
uint8_t i;
switch (config->num_leds) {
case 1:
/* check that it is a three-channel LED */
info = &config->led_infos[0];
if (info->num_colors != 3) {
LOG_ERR("%s: invalid number of colors %d "
"(must be 3 for RGB LED)",
dev->name, info->num_colors);
return -EINVAL;
}
for (i = 0; i < 3; i++) {
if (!is31fl3194_count_colors(dev, info->color_mapping[i], rgb_counts)) {
return -EINVAL;
}
}
break;
case 3:
/* check that each LED is single-color */
for (i = 0; i < 3; i++) {
info = &config->led_infos[i];
if (info->num_colors != 1) {
LOG_ERR("%s: invalid number of colors %d "
"(must be 1 when defining multiple LEDs)",
dev->name, info->num_colors);
return -EINVAL;
}
if (!is31fl3194_count_colors(dev, info->color_mapping[0], rgb_counts)) {
return -EINVAL;
}
}
break;
default:
LOG_ERR("%s: invalid number of LEDs %d (must be 1 or 3)",
dev->name, config->num_leds);
return -EINVAL;
}
return 0;
}
static int is31fl3194_init(const struct device *dev)
{
const struct is31fl3194_config *config = dev->config;
const struct led_info *info = NULL;
int i, ret;
uint8_t prod_id, band;
uint8_t current_reg = 0;
ret = is31fl3194_check_config(dev);
if (ret != 0) {
return ret;
}
if (!i2c_is_ready_dt(&config->bus)) {
LOG_ERR("%s: I2C device not ready", dev->name);
return -ENODEV;
}
ret = i2c_reg_read_byte_dt(&config->bus, IS31FL3194_PROD_ID_REG, &prod_id);
if (ret != 0) {
LOG_ERR("%s: failed to read product ID", dev->name);
return ret;
}
if (prod_id != IS31FL3194_PROD_ID_VAL) {
LOG_ERR("%s: invalid product ID 0x%02x (expected 0x%02x)", dev->name, prod_id,
IS31FL3194_PROD_ID_VAL);
return -ENODEV;
}
/* calc current limit register value */
info = &config->led_infos[0];
if (info->num_colors == IS31FL3194_CHANNEL_COUNT) {
/* one RGB LED: set all channels to the same current limit */
band = (config->current_limits[0] / 10) - 1;
for (i = 0; i < IS31FL3194_CHANNEL_COUNT; i++) {
current_reg |= band << (2 * i);
}
} else {
/* single-channel LEDs: independent limits */
for (i = 0; i < config->num_leds; i++) {
band = (config->current_limits[i] / 10) - 1;
current_reg |= band << (2 * i);
}
}
ret = i2c_reg_write_byte_dt(&config->bus, IS31FL3194_CURRENT_REG, current_reg);
if (ret != 0) {
LOG_ERR("%s: failed to set current limit", dev->name);
return ret;
}
/* enable device */
return i2c_reg_write_byte_dt(&config->bus, IS31FL3194_CONF_REG, IS31FL3194_CONF_ENABLE);
}
static const struct led_driver_api is31fl3194_led_api = {
.set_brightness = is31fl3194_set_brightness,
.on = is31fl3194_led_on,
.off = is31fl3194_led_off,
.get_info = is31fl3194_get_info,
.set_color = is31fl3194_set_color,
};
#define COLOR_MAPPING(led_node_id) \
static const uint8_t color_mapping_##led_node_id[] = \
DT_PROP(led_node_id, color_mapping);
#define LED_INFO(led_node_id) \
{ \
.label = DT_PROP(led_node_id, label), \
.num_colors = DT_PROP_LEN(led_node_id, color_mapping), \
.color_mapping = color_mapping_##led_node_id, \
},
#define LED_CURRENT(led_node_id) \
DT_PROP(led_node_id, current_limit),
#define IS31FL3194_DEFINE(id) \
\
DT_INST_FOREACH_CHILD(id, COLOR_MAPPING) \
\
static const struct led_info is31fl3194_leds_##id[] = \
{ DT_INST_FOREACH_CHILD(id, LED_INFO) }; \
static const uint8_t is31fl3194_currents_##id[] = \
{ DT_INST_FOREACH_CHILD(id, LED_CURRENT) }; \
BUILD_ASSERT(ARRAY_SIZE(is31fl3194_leds_##id) > 0, \
"No LEDs defined for " #id); \
\
static const struct is31fl3194_config is31fl3194_config_##id = { \
.bus = I2C_DT_SPEC_INST_GET(id), \
.num_leds = ARRAY_SIZE(is31fl3194_leds_##id), \
.led_infos = is31fl3194_leds_##id, \
.current_limits = is31fl3194_currents_##id, \
}; \
DEVICE_DT_INST_DEFINE(id, &is31fl3194_init, NULL, NULL, \
&is31fl3194_config_##id, POST_KERNEL, \
CONFIG_LED_INIT_PRIORITY, &is31fl3194_led_api);
DT_INST_FOREACH_STATUS_OKAY(IS31FL3194_DEFINE)
``` | /content/code_sandbox/drivers/led/is31fl3194.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 2,741 |
```unknown
config LP3943
bool "LP3943 LED driver"
default y
depends on DT_HAS_TI_LP3943_ENABLED
select I2C
help
Enable LED driver for LP3943.
LP3943 LED driver has 16 channels each with multi-programmable
states at a specified rate. Each channel can drive up to 25 mA
per LED.
``` | /content/code_sandbox/drivers/led/Kconfig.lp3943 | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 83 |
```c
/*
*
*/
#define DT_DRV_COMPAT issi_is31fl3733
#include <zephyr/drivers/gpio.h>
#include <zephyr/drivers/i2c.h>
#include <zephyr/drivers/led.h>
#include <zephyr/kernel.h>
#include <zephyr/drivers/led/is31fl3733.h>
#include <zephyr/logging/log.h>
LOG_MODULE_REGISTER(is31fl3733, CONFIG_LED_LOG_LEVEL);
/* IS31FL3733 register definitions */
#define CMD_SEL_REG 0xFD /* Command/page selection reg */
#define CMD_SEL_LED 0x0 /* LED configuration page */
#define CMD_SEL_PWM 0x1 /* PWM configuration page */
#define CMD_SEL_FUNC 0x3 /* Function configuration page */
#define CMD_LOCK_REG 0xFE /* Command selection lock reg */
#define CMD_LOCK_UNLOCK 0xC5 /* Command sel unlock value */
/* IS31FL3733 page specific register definitions */
/* Function configuration page */
#define CONF_REG 0x0 /* configuration register */
#define CONF_REG_SSD_MASK 0x1 /* Software shutdown mask */
#define CONF_REG_SSD_SHIFT 0x0 /* Software shutdown shift */
#define CONF_REG_SYNC_SHIFT 0x6 /* Sync mode shift */
#define CONF_REG_SYNC_MASK 0xC /* Sync mode mask */
#define GLOBAL_CURRENT_CTRL_REG 0x1 /* global current control register */
#define RESET_REG 0x11 /* Reset all registers to POR state */
/* Matrix Layout definitions */
#define IS31FL3733_ROW_COUNT 12
#define IS31FL3733_COL_COUNT 16
#define IS31FL3733_MAX_LED (IS31FL3733_ROW_COUNT * IS31FL3733_COL_COUNT)
/* Max brightness */
#define IS31FL3733_MAX_BRIGHTNESS 100
struct is31fl3733_config {
struct i2c_dt_spec bus;
struct gpio_dt_spec sdb;
uint8_t current_limit;
uint8_t sync;
};
struct is31fl3733_data {
/* Active configuration page */
uint32_t selected_page;
/* Scratch buffer, used for bulk controller writes */
uint8_t scratch_buf[IS31FL3733_MAX_LED + 1];
/* LED config reg state, IS31FL3733 conf reg is write only */
uint8_t conf_reg;
};
/* Selects target register page for IS31FL3733. After setting the
* target page, all I2C writes will use the selected page until the selected
* page is changed.
*/
static int is31fl3733_select_page(const struct device *dev, uint8_t page)
{
const struct is31fl3733_config *config = dev->config;
struct is31fl3733_data *data = dev->data;
int ret = 0U;
if (data->selected_page == page) {
/* No change necessary */
return 0;
}
/* Unlock page selection register */
ret = i2c_reg_write_byte_dt(&config->bus, CMD_LOCK_REG, CMD_LOCK_UNLOCK);
if (ret < 0) {
LOG_ERR("Could not unlock page selection register");
return ret;
}
/* Write to function select to select active page */
ret = i2c_reg_write_byte_dt(&config->bus, CMD_SEL_REG, page);
if (ret < 0) {
LOG_ERR("Could not select active page");
return ret;
}
data->selected_page = page;
return ret;
}
static int is31fl3733_led_set_brightness(const struct device *dev, uint32_t led, uint8_t value)
{
const struct is31fl3733_config *config = dev->config;
int ret;
uint8_t led_brightness = (uint8_t)(((uint32_t)value * 255) / 100);
if (led >= IS31FL3733_MAX_LED) {
return -EINVAL;
}
/* Configure PWM mode */
ret = is31fl3733_select_page(dev, CMD_SEL_PWM);
if (ret < 0) {
return ret;
}
return i2c_reg_write_byte_dt(&config->bus, led, led_brightness);
}
static int is31fl3733_led_on(const struct device *dev, uint32_t led)
{
return is31fl3733_led_set_brightness(dev, led, IS31FL3733_MAX_BRIGHTNESS);
}
static int is31fl3733_led_off(const struct device *dev, uint32_t led)
{
return is31fl3733_led_set_brightness(dev, led, 0);
}
static int is31fl3733_led_write_channels(const struct device *dev, uint32_t start_channel,
uint32_t num_channels, const uint8_t *buf)
{
const struct is31fl3733_config *config = dev->config;
struct is31fl3733_data *data = dev->data;
int ret = 0U;
uint8_t *pwm_start;
if ((start_channel + num_channels) > IS31FL3733_MAX_LED) {
return -EINVAL;
}
pwm_start = data->scratch_buf + start_channel;
/* Set PWM and LED target registers as first byte of each transfer */
*pwm_start = start_channel;
memcpy((pwm_start + 1), buf, num_channels);
/* Write LED PWM states */
ret = is31fl3733_select_page(dev, CMD_SEL_PWM);
if (ret < 0) {
return ret;
}
LOG_HEXDUMP_DBG(pwm_start, (num_channels + 1), "PWM states");
return i2c_write_dt(&config->bus, pwm_start, num_channels + 1);
}
static int is31fl3733_init(const struct device *dev)
{
const struct is31fl3733_config *config = dev->config;
struct is31fl3733_data *data = dev->data;
int ret = 0U;
uint8_t dummy;
if (!i2c_is_ready_dt(&config->bus)) {
LOG_ERR("I2C device not ready");
return -ENODEV;
}
if (config->sdb.port != NULL) {
if (!gpio_is_ready_dt(&config->sdb)) {
LOG_ERR("GPIO SDB pin not ready");
return -ENODEV;
}
/* Set SDB pin high to exit hardware shutdown */
ret = gpio_pin_configure_dt(&config->sdb, GPIO_OUTPUT_ACTIVE);
if (ret < 0) {
return ret;
}
}
ret = is31fl3733_select_page(dev, CMD_SEL_FUNC);
if (ret < 0) {
return ret;
}
/*
* read reset reg to reset all registers to POR state,
* in case we are booting from a warm reset.
*/
ret = i2c_reg_read_byte_dt(&config->bus, RESET_REG, &dummy);
if (ret < 0) {
return ret;
}
/* Select function page after LED controller reset */
ret = is31fl3733_select_page(dev, CMD_SEL_FUNC);
if (ret < 0) {
return ret;
}
/* Set global current control register based off devicetree value */
ret = i2c_reg_write_byte_dt(&config->bus, GLOBAL_CURRENT_CTRL_REG,
config->current_limit);
if (ret < 0) {
return ret;
}
/* As a final step, we exit software shutdown, disabling display
* blanking. We also set the LED controller sync mode here.
*/
data->conf_reg = (config->sync << CONF_REG_SYNC_SHIFT) | CONF_REG_SSD_MASK;
ret = i2c_reg_write_byte_dt(&config->bus, CONF_REG, data->conf_reg);
if (ret < 0) {
return ret;
}
/* Enable all LEDs. We only control LED brightness in this driver. */
data->scratch_buf[0] = 0x0;
memset(data->scratch_buf + 1, 0xFF, (IS31FL3733_MAX_LED / 8));
ret = is31fl3733_select_page(dev, CMD_SEL_LED);
if (ret < 0) {
return ret;
}
return i2c_write_dt(&config->bus, data->scratch_buf,
(IS31FL3733_MAX_LED / 8) + 1);
}
/* Custom IS31FL3733 specific APIs */
/**
* @brief Blanks IS31FL3733 LED display.
*
* When blank_en is set, the LED display will be disabled. This can be used for
* flicker-free display updates, or power saving.
*
* @param dev: LED device structure
* @param blank_en: should blanking be enabled
* @return 0 on success, or negative value on error.
*/
int is31fl3733_blank(const struct device *dev, bool blank_en)
{
const struct is31fl3733_config *config = dev->config;
struct is31fl3733_data *data = dev->data;
int ret;
ret = is31fl3733_select_page(dev, CMD_SEL_FUNC);
if (ret < 0) {
return ret;
}
if (blank_en) {
data->conf_reg &= ~CONF_REG_SSD_MASK;
} else {
data->conf_reg |= CONF_REG_SSD_MASK;
}
return i2c_reg_write_byte_dt(&config->bus, CONF_REG, data->conf_reg);
}
/**
* @brief Sets led current limit
*
* Sets the current limit for the LED driver. This is a separate value
* from per-led brightness, and applies to all LEDs.
* This value sets the output current limit according
* to the following formula: (840/R_ISET) * (limit/256)
* See table 14 of the datasheet for additional details.
* @param dev: LED device structure
* @param limit: current limit to apply
* @return 0 on success, or negative value on error.
*/
int is31fl3733_current_limit(const struct device *dev, uint8_t limit)
{
const struct is31fl3733_config *config = dev->config;
int ret;
ret = is31fl3733_select_page(dev, CMD_SEL_FUNC);
if (ret < 0) {
return ret;
}
/* Set global current control register */
return i2c_reg_write_byte_dt(&config->bus, GLOBAL_CURRENT_CTRL_REG, limit);
}
static const struct led_driver_api is31fl3733_api = {
.on = is31fl3733_led_on,
.off = is31fl3733_led_off,
.set_brightness = is31fl3733_led_set_brightness,
.write_channels = is31fl3733_led_write_channels,
};
#define IS31FL3733_DEVICE(n) \
static const struct is31fl3733_config is31fl3733_config_##n = { \
.bus = I2C_DT_SPEC_INST_GET(n), \
.sdb = GPIO_DT_SPEC_INST_GET_OR(n, sdb_gpios, {}), \
.current_limit = DT_INST_PROP(n, current_limit), \
.sync = DT_INST_ENUM_IDX(n, sync_mode), \
}; \
\
static struct is31fl3733_data is31fl3733_data_##n = { \
.selected_page = CMD_SEL_LED, \
}; \
\
DEVICE_DT_INST_DEFINE(n, &is31fl3733_init, NULL, &is31fl3733_data_##n, \
&is31fl3733_config_##n, POST_KERNEL, CONFIG_LED_INIT_PRIORITY, \
&is31fl3733_api);
DT_INST_FOREACH_STATUS_OKAY(IS31FL3733_DEVICE)
``` | /content/code_sandbox/drivers/led/is31fl3733.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 2,477 |
```c
/*
*
*/
#define DT_DRV_COMPAT issi_is31fl3216a
#include <zephyr/drivers/i2c.h>
#include <zephyr/drivers/led.h>
#include <zephyr/logging/log.h>
#define IS31FL3216A_REG_CONFIG 0x00
#define IS31FL3216A_REG_CTL_1 0x01
#define IS31FL3216A_REG_CTL_2 0x02
#define IS31FL3216A_REG_LIGHT_EFFECT 0x03
#define IS31FL3216A_REG_CHANNEL_CONFIG 0x04
#define IS31FL3216A_REG_GPIO_CONFIG 0x05
#define IS31FL3216A_REG_OUTPUT_PORT 0x06
#define IS31FL3216A_REG_INT_CONTROL 0x07
#define IS31FL3216A_REG_ADC_SAMPLE_RATE 0x09
#define IS31FL3216A_REG_PWM_FIRST 0x10
#define IS31FL3216A_REG_PWM_LAST 0x1F
#define IS31FL3216A_REG_UPDATE 0xB0
#define IS31FL3216A_REG_FRAME_DELAY 0xB6
#define IS31FL3216A_REG_FRAME_START 0xB7
#define IS31FL3216A_MAX_LEDS 16
LOG_MODULE_REGISTER(is31fl3216a, CONFIG_LED_LOG_LEVEL);
struct is31fl3216a_cfg {
struct i2c_dt_spec i2c;
};
static int is31fl3216a_write_buffer(const struct i2c_dt_spec *i2c,
const uint8_t *buffer, uint32_t num_bytes)
{
int status;
status = i2c_write_dt(i2c, buffer, num_bytes);
if (status < 0) {
LOG_ERR("Could not write buffer: %i", status);
return status;
}
return 0;
}
static int is31fl3216a_write_reg(const struct i2c_dt_spec *i2c, uint8_t reg,
uint8_t val)
{
uint8_t buffer[2] = {reg, val};
return is31fl3216a_write_buffer(i2c, buffer, sizeof(buffer));
}
static int is31fl3216a_update_pwm(const struct i2c_dt_spec *i2c)
{
return is31fl3216a_write_reg(i2c, IS31FL3216A_REG_UPDATE, 0);
}
static uint8_t is31fl3216a_brightness_to_pwm(uint8_t brightness)
{
return (0xFFU * brightness) / 100;
}
static int is31fl3216a_led_write_channels(const struct device *dev,
uint32_t start_channel,
uint32_t num_channels,
const uint8_t *buf)
{
const struct is31fl3216a_cfg *config = dev->config;
uint8_t i2c_buffer[IS31FL3216A_MAX_LEDS + 1];
int status;
int i;
if (num_channels == 0) {
return 0;
}
if (start_channel + num_channels > IS31FL3216A_MAX_LEDS) {
return -EINVAL;
}
/* Invert channels, last register is channel 0 */
i2c_buffer[0] = IS31FL3216A_REG_PWM_LAST - start_channel -
(num_channels - 1);
for (i = 0; i < num_channels; i++) {
if (buf[num_channels - i - 1] > 100) {
return -EINVAL;
}
i2c_buffer[i + 1] = is31fl3216a_brightness_to_pwm(
buf[num_channels - i - 1]);
}
status = is31fl3216a_write_buffer(&config->i2c, i2c_buffer,
num_channels + 1);
if (status < 0) {
return status;
}
return is31fl3216a_update_pwm(&config->i2c);
}
static int is31fl3216a_led_set_brightness(const struct device *dev,
uint32_t led, uint8_t value)
{
const struct is31fl3216a_cfg *config = dev->config;
uint8_t pwm_reg = IS31FL3216A_REG_PWM_LAST - led;
int status;
uint8_t pwm_value;
if (led > IS31FL3216A_MAX_LEDS - 1 || value > 100) {
return -EINVAL;
}
pwm_value = is31fl3216a_brightness_to_pwm(value);
status = is31fl3216a_write_reg(&config->i2c, pwm_reg, pwm_value);
if (status < 0) {
return status;
}
return is31fl3216a_update_pwm(&config->i2c);
}
static int is31fl3216a_led_on(const struct device *dev, uint32_t led)
{
return is31fl3216a_led_set_brightness(dev, led, 100);
}
static int is31fl3216a_led_off(const struct device *dev, uint32_t led)
{
return is31fl3216a_led_set_brightness(dev, led, 0);
}
static int is31fl3216a_init_registers(const struct i2c_dt_spec *i2c)
{
int i;
int status;
status = is31fl3216a_write_reg(i2c, IS31FL3216A_REG_CTL_1, 0xFF);
if (status < 0) {
return status;
}
status = is31fl3216a_write_reg(i2c, IS31FL3216A_REG_CTL_2, 0xFF);
if (status < 0) {
return status;
}
status = is31fl3216a_write_reg(i2c, IS31FL3216A_REG_LIGHT_EFFECT, 0x00);
if (status < 0) {
return status;
}
status = is31fl3216a_write_reg(i2c, IS31FL3216A_REG_CHANNEL_CONFIG,
0x00);
if (status < 0) {
return status;
}
status = is31fl3216a_write_reg(i2c, IS31FL3216A_REG_GPIO_CONFIG, 0x00);
if (status < 0) {
return status;
}
status = is31fl3216a_write_reg(i2c, IS31FL3216A_REG_OUTPUT_PORT, 0x00);
if (status < 0) {
return status;
}
status = is31fl3216a_write_reg(i2c, IS31FL3216A_REG_INT_CONTROL, 0x00);
if (status < 0) {
return status;
}
status = is31fl3216a_write_reg(i2c, IS31FL3216A_REG_ADC_SAMPLE_RATE,
0x00);
if (status < 0) {
return status;
}
status = is31fl3216a_write_reg(i2c, IS31FL3216A_REG_FRAME_DELAY, 0x00);
if (status < 0) {
return status;
}
status = is31fl3216a_write_reg(i2c, IS31FL3216A_REG_FRAME_START, 0x00);
if (status < 0) {
return status;
}
for (i = IS31FL3216A_REG_PWM_FIRST;
i <= IS31FL3216A_REG_PWM_LAST;
i++) {
status = is31fl3216a_write_reg(i2c, i, 0);
if (status < 0) {
return status;
}
}
status = is31fl3216a_write_reg(i2c, IS31FL3216A_REG_UPDATE, 0);
if (status < 0) {
return status;
}
return is31fl3216a_write_reg(i2c, IS31FL3216A_REG_CONFIG, 0x00);
}
static int is31fl3216a_init(const struct device *dev)
{
const struct is31fl3216a_cfg *config = dev->config;
LOG_DBG("Initializing @0x%x...", config->i2c.addr);
if (!i2c_is_ready_dt(&config->i2c)) {
LOG_ERR("I2C device not ready");
return -ENODEV;
}
return is31fl3216a_init_registers(&config->i2c);
}
static const struct led_driver_api is31fl3216a_led_api = {
.set_brightness = is31fl3216a_led_set_brightness,
.on = is31fl3216a_led_on,
.off = is31fl3216a_led_off,
.write_channels = is31fl3216a_led_write_channels
};
#define IS31FL3216A_INIT(id) \
static const struct is31fl3216a_cfg is31fl3216a_##id##_cfg = { \
.i2c = I2C_DT_SPEC_INST_GET(id), \
}; \
DEVICE_DT_INST_DEFINE(id, &is31fl3216a_init, NULL, NULL, \
&is31fl3216a_##id##_cfg, POST_KERNEL, \
CONFIG_LED_INIT_PRIORITY, &is31fl3216a_led_api);
DT_INST_FOREACH_STATUS_OKAY(IS31FL3216A_INIT)
``` | /content/code_sandbox/drivers/led/is31fl3216a.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 1,998 |
```unknown
config LP5569
bool "LP5569 LED driver"
default y
depends on DT_HAS_TI_LP5569_ENABLED
select I2C
help
Enable LED driver for LP5569. LP5569 LED driver has 9 channels.
Each channel can drive up to 25.5 mA per LED.
``` | /content/code_sandbox/drivers/led/Kconfig.lp5569 | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 70 |
```c
/*
*
*/
#define DT_DRV_COMPAT microchip_xec_bbled
/**
* @file
* @brief Microchip Breathing-Blinking LED controller
*/
#include <soc.h>
#ifndef CONFIG_SOC_SERIES_MEC15XX
#include <zephyr/drivers/clock_control/mchp_xec_clock_control.h>
#include <zephyr/drivers/interrupt_controller/intc_mchp_xec_ecia.h>
#endif
#include <zephyr/drivers/led.h>
#include <zephyr/drivers/pinctrl.h>
#include <zephyr/device.h>
#include <zephyr/kernel.h>
#include <zephyr/logging/log.h>
LOG_MODULE_REGISTER(led_xec, CONFIG_LED_LOG_LEVEL);
/* Same BBLED hardware block in MEC15xx and MEC172x families
* Config register
*/
#define XEC_BBLED_CFG_MSK 0x1ffffu
#define XEC_BBLED_CFG_MODE_POS 0
#define XEC_BBLED_CFG_MODE_MSK 0x3u
#define XEC_BBLED_CFG_MODE_OFF 0
#define XEC_BBLED_CFG_MODE_BREATHING 0x1u
#define XEC_BBLED_CFG_MODE_PWM 0x2u
#define XEC_BBLED_CFG_MODE_ALWAYS_ON 0x3u
#define XEC_BBLED_CFG_CLK_SRC_48M_POS 2
#define XEC_BBLED_CFG_EN_UPDATE_POS 6
#define XEC_BBLED_CFG_RST_PWM_POS 7
#define XEC_BBLED_CFG_WDT_RLD_POS 8
#define XEC_BBLED_CFG_WDT_RLD_MSK0 0xffu
#define XEC_BBLED_CFG_WDT_RLD_MSK 0xff00u
#define XEC_BBLED_CFG_WDT_RLD_DFLT 0x1400u
/* Limits register */
#define XEC_BBLED_LIM_MSK 0xffffu
#define XEC_BBLED_LIM_MIN_POS 0
#define XEC_BBLED_LIM_MIN_MSK 0xffu
#define XEC_BBLED_LIM_MAX_POS 8
#define XEC_BBLED_LIM_MAX_MSK 0xff00u
/* Delay register */
#define XEC_BBLED_DLY_MSK 0xffffffu
#define XEC_BBLED_DLY_LO_POS 0
#define XEC_BBLED_DLY_LO_MSK 0xfffu
#define XEC_BBLED_DLY_HI_POS 12
#define XEC_BBLED_DLY_HI_MSK 0xfff000u
/* Update step size and update interval registers implement
* eight 4-bit fields numbered 0 to 7
*/
#define XEC_BBLED_UPD_SSI_POS(n) ((uint32_t)(n) * 4u)
#define XEC_BBLED_UPD_SSI0_MSK(n) ((uint32_t)0xfu << XEC_BBLED_UPD_SSI_POS(n))
/* Output delay register: b[7:0] is delay in clock source units */
#define XEC_BBLED_OUT_DLY_MSK 0xffu
/* Delay.Lo register field */
#define XEC_BBLED_MAX_PRESCALER 4095u
/* Blink mode source frequency is 32768 Hz */
#define XEC_BBLED_BLINK_CLK_SRC_HZ 32768u
/* Fblink = 32768 / (256 * (prescaler+1))
* prescaler is 12 bit.
* Maximum Fblink = 128 Hz or 7.8125 ms
* Minimum Fblink = 32.25 mHz or 32000 ms
*/
#define XEC_BBLED_BLINK_PERIOD_MAX_MS 32000u
#define XEC_BBLED_BLINK_PERIOD_MIN_MS 8u
struct xec_bbled_regs {
volatile uint32_t config;
volatile uint32_t limits;
volatile uint32_t delay;
volatile uint32_t update_step_size;
volatile uint32_t update_interval;
volatile uint32_t output_delay;
};
struct xec_bbled_config {
struct xec_bbled_regs * const regs;
const struct pinctrl_dev_config *pcfg;
uint8_t pcr_id;
uint8_t pcr_pos;
};
/* delay_on and delay_off are in milliseconds
* (prescale+1) = (32768 * Tblink_ms) / (256 * 1000)
* requires caller to limit delay_on and delay_off based
* on BBLED 32KHz minimum/maximum values.
*/
static uint32_t calc_blink_32k_prescaler(uint32_t delay_on, uint32_t delay_off)
{
uint32_t temp = ((delay_on + delay_off) * XEC_BBLED_BLINK_CLK_SRC_HZ) / (256U * 1000U);
uint32_t prescaler = 0;
if (temp) {
temp--;
if (temp > XEC_BBLED_MAX_PRESCALER) {
prescaler = XEC_BBLED_MAX_PRESCALER;
} else {
prescaler = (uint32_t)temp;
}
}
return prescaler;
}
/* return duty cycle scaled to [0, 255]
* caller must insure delay_on and delay_off are in hardware range.
*/
static uint32_t calc_blink_duty_cycle(uint32_t delay_on, uint32_t delay_off)
{
return (256U * delay_on) / (delay_on + delay_off);
}
/* Enable HW blinking of the LED.
* delay_on = on time in milliseconds
* delay_off = off time in milliseconds
* BBLED blinking mode uses an 8-bit accumulator and an 8-bit duty cycle
* register. The duty cycle register is programmed once and the
* accumulator is used as an 8-bit up counter.
* The counter uses the 32768 Hz clock and is pre-scaled by the delay
* counter. Maximum blink rate is 128Hz to 32.25 mHz (7.8 ms to 32 seconds).
* 8-bit duty cycle values: 0x00 = full off, 0xff = full on.
* Fblink = 32768 / ((prescale + 1) * 256)
* HiWidth (seconds) = (1/Fblink) * (duty_cycle / 256)
* LoWidth (seconds) = (1/Fblink) * ((1 - duty_cycle) / 256)
* duty_cycle in [0, 1]. Register value for duty cycle is
* scaled to [0, 255].
* prescale is delay register low delay field, bits[11:0]
* duty_cycle is limits register minimum field, bits[7:0]
*/
static int xec_bbled_blink(const struct device *dev, uint32_t led,
uint32_t delay_on, uint32_t delay_off)
{
const struct xec_bbled_config * const config = dev->config;
struct xec_bbled_regs * const regs = config->regs;
uint32_t period, prescaler, dcs;
if (led) {
return -EINVAL;
}
/* insure period will not overflow uin32_t */
if ((delay_on > XEC_BBLED_BLINK_PERIOD_MAX_MS)
|| (delay_off > XEC_BBLED_BLINK_PERIOD_MAX_MS)) {
return -EINVAL;
}
period = delay_on + delay_off;
if ((period < XEC_BBLED_BLINK_PERIOD_MIN_MS)
|| (period > XEC_BBLED_BLINK_PERIOD_MAX_MS)) {
return -EINVAL;
}
prescaler = calc_blink_32k_prescaler(delay_on, delay_off);
dcs = calc_blink_duty_cycle(delay_on, delay_off);
regs->config = (regs->config & ~(XEC_BBLED_CFG_MODE_MSK))
| XEC_BBLED_CFG_MODE_OFF;
regs->delay = (regs->delay & ~(XEC_BBLED_DLY_LO_MSK))
| (prescaler & XEC_BBLED_DLY_LO_MSK);
regs->limits = (regs->limits & ~(XEC_BBLED_LIM_MIN_MSK))
| (dcs & XEC_BBLED_LIM_MIN_MSK);
regs->config = (regs->config & ~(XEC_BBLED_CFG_MODE_MSK))
| XEC_BBLED_CFG_MODE_PWM;
regs->config |= BIT(XEC_BBLED_CFG_EN_UPDATE_POS);
return 0;
}
static int xec_bbled_on(const struct device *dev, uint32_t led)
{
const struct xec_bbled_config * const config = dev->config;
struct xec_bbled_regs * const regs = config->regs;
if (led) {
return -EINVAL;
}
regs->config = (regs->config & ~(XEC_BBLED_CFG_MODE_MSK))
| XEC_BBLED_CFG_MODE_ALWAYS_ON;
return 0;
}
static int xec_bbled_off(const struct device *dev, uint32_t led)
{
const struct xec_bbled_config * const config = dev->config;
struct xec_bbled_regs * const regs = config->regs;
if (led) {
return -EINVAL;
}
regs->config = (regs->config & ~(XEC_BBLED_CFG_MODE_MSK))
| XEC_BBLED_CFG_MODE_OFF;
return 0;
}
#ifdef CONFIG_SOC_SERIES_MEC15XX
static inline void xec_bbled_slp_en_clr(const struct device *dev)
{
const struct xec_bbled_config * const cfg = dev->config;
enum pcr_id pcr_val = PCR_MAX_ID;
switch (cfg->pcr_pos) {
case MCHP_PCR3_LED0_POS:
pcr_val = PCR_LED0;
break;
case MCHP_PCR3_LED1_POS:
pcr_val = PCR_LED1;
break;
case MCHP_PCR3_LED2_POS:
pcr_val = PCR_LED2;
break;
default:
return;
}
mchp_pcr_periph_slp_ctrl(pcr_val, 0);
}
#else
static inline void xec_bbled_slp_en_clr(const struct device *dev)
{
const struct xec_bbled_config * const cfg = dev->config;
z_mchp_xec_pcr_periph_sleep(cfg->pcr_id, cfg->pcr_pos, 0);
}
#endif
static int xec_bbled_init(const struct device *dev)
{
const struct xec_bbled_config * const config = dev->config;
struct xec_bbled_regs * const regs = config->regs;
int ret;
xec_bbled_slp_en_clr(dev);
/* soft reset, disable BBLED WDT, set clock source to default (32KHz domain) */
regs->config |= BIT(XEC_BBLED_CFG_RST_PWM_POS);
regs->config = XEC_BBLED_CFG_MODE_OFF;
ret = pinctrl_apply_state(config->pcfg, PINCTRL_STATE_DEFAULT);
if (ret != 0) {
LOG_ERR("XEC BBLED pinctrl setup failed (%d)", ret);
}
return ret;
}
static const struct led_driver_api xec_bbled_api = {
.on = xec_bbled_on,
.off = xec_bbled_off,
.blink = xec_bbled_blink,
};
#define XEC_BBLED_PINCTRL_DEF(i) PINCTRL_DT_INST_DEFINE(i)
#define XEC_BBLED_CONFIG(i) \
static struct xec_bbled_config xec_bbled_config_##i = { \
.regs = (struct xec_bbled_regs * const)DT_INST_REG_ADDR(i), \
.pcfg = PINCTRL_DT_INST_DEV_CONFIG_GET(i), \
.pcr_id = (uint8_t)DT_INST_PROP_BY_IDX(i, pcrs, 0), \
.pcr_pos = (uint8_t)DT_INST_PROP_BY_IDX(i, pcrs, 1), \
}
#define XEC_BBLED_DEVICE(i) \
\
XEC_BBLED_PINCTRL_DEF(i); \
\
XEC_BBLED_CONFIG(i); \
\
DEVICE_DT_INST_DEFINE(i, &xec_bbled_init, NULL, \
NULL, &xec_bbled_config_##i, \
POST_KERNEL, CONFIG_LED_INIT_PRIORITY, \
&xec_bbled_api);
DT_INST_FOREACH_STATUS_OKAY(XEC_BBLED_DEVICE)
``` | /content/code_sandbox/drivers/led/led_mchp_xec.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 2,615 |
```c
/*
*
*/
#define DT_DRV_COMPAT onnn_ncp5623
/**
* @file
* @brief NCP5623 LED driver
*
* The NCP5623 is a 3-channel LED driver that communicates over I2C.
*/
#include <zephyr/device.h>
#include <zephyr/drivers/i2c.h>
#include <zephyr/drivers/led.h>
#include <zephyr/kernel.h>
#include <zephyr/logging/log.h>
LOG_MODULE_REGISTER(ncp5623, CONFIG_LED_LOG_LEVEL);
#define NCP5623_LED_CURRENT 0x20
#define NCP5623_LED_PWM0 0x40
#define NCP5623_LED_PWM1 0x60
#define NCP5623_LED_PWM2 0x80
#define NCP5623_CHANNEL_COUNT 3
/* Brightness limits */
#define NCP5623_MIN_BRIGHTNESS 0
#define NCP5623_MAX_BRIGHTNESS 0x1f
static const uint8_t led_channels[] = {NCP5623_LED_PWM0, NCP5623_LED_PWM1, NCP5623_LED_PWM2};
struct ncp5623_config {
struct i2c_dt_spec bus;
uint8_t num_leds;
const struct led_info *leds_info;
};
static const struct led_info *ncp5623_led_to_info(const struct ncp5623_config *config, uint32_t led)
{
if (led < config->num_leds) {
return &config->leds_info[led];
}
return NULL;
}
static int ncp5623_get_info(const struct device *dev, uint32_t led, const struct led_info **info)
{
const struct ncp5623_config *config = dev->config;
const struct led_info *led_info = ncp5623_led_to_info(config, led);
if (!led_info) {
return -EINVAL;
}
*info = led_info;
return 0;
}
static int ncp5623_set_color(const struct device *dev, uint32_t led, uint8_t num_colors,
const uint8_t *color)
{
const struct ncp5623_config *config = dev->config;
const struct led_info *led_info = ncp5623_led_to_info(config, led);
uint8_t buf[6] = {0x70, NCP5623_LED_PWM0, 0x70, NCP5623_LED_PWM1, 0x70, NCP5623_LED_PWM2};
if (!led_info) {
return -ENODEV;
}
if (led_info->num_colors != 3) {
return -ENOTSUP;
}
if (num_colors != 3) {
return -EINVAL;
}
buf[1] = buf[1] | color[0] / 8;
buf[3] = buf[3] | color[1] / 8;
buf[5] = buf[5] | color[2] / 8;
return i2c_burst_write_dt(&config->bus, NCP5623_LED_CURRENT | NCP5623_MAX_BRIGHTNESS, buf,
sizeof(buf));
}
static int ncp5623_set_brightness(const struct device *dev, uint32_t led, uint8_t value)
{
const struct ncp5623_config *config = dev->config;
const struct led_info *led_info = ncp5623_led_to_info(config, led);
int ret = 0;
if (!led_info) {
return -ENODEV;
}
if (value > 100) {
return -EINVAL;
}
if (led_info->num_colors != 1) {
return -ENOTSUP;
}
/* Rescale 0..100 to 0..31 */
value = value * NCP5623_MAX_BRIGHTNESS / 100;
ret = i2c_reg_write_byte_dt(&config->bus, led_channels[led] | value, 0x70);
if (ret < 0) {
LOG_ERR("%s: LED write failed", dev->name);
}
return ret;
}
static inline int ncp5623_led_on(const struct device *dev, uint32_t led)
{
return ncp5623_set_brightness(dev, led, 100);
}
static inline int ncp5623_led_off(const struct device *dev, uint32_t led)
{
return ncp5623_set_brightness(dev, led, 0);
}
static int ncp5623_led_init(const struct device *dev)
{
const struct ncp5623_config *config = dev->config;
const struct led_info *led_info = NULL;
int i;
uint8_t buf[6] = {0x70, NCP5623_LED_PWM0, 0x70, NCP5623_LED_PWM1, 0x70, NCP5623_LED_PWM2};
if (!i2c_is_ready_dt(&config->bus)) {
LOG_ERR("%s: I2C device not ready", dev->name);
return -ENODEV;
}
if (config->num_leds == 1) { /* one three-channel (RGB) LED */
led_info = ncp5623_led_to_info(config, 0);
if (!led_info) {
return -ENODEV;
}
if (led_info->num_colors != NCP5623_CHANNEL_COUNT) {
LOG_ERR("%s: invalid number of colors %d (must be %d with a single LED)",
dev->name, led_info->num_colors, NCP5623_CHANNEL_COUNT);
return -EINVAL;
}
} else if (config->num_leds <= 3) { /* three single-channel LEDs */
for (i = 0; i < config->num_leds; i++) {
led_info = ncp5623_led_to_info(config, i);
if (!led_info) {
return -ENODEV;
}
if (led_info->num_colors > 1) {
LOG_ERR("%s: invalid number of colors %d (must be 1 when defining "
"multiple leds)",
dev->name, led_info->num_colors);
return -EINVAL;
}
}
} else {
LOG_ERR("%s: invalid number of leds %d (max %d)", dev->name, config->num_leds,
NCP5623_CHANNEL_COUNT);
return -EINVAL;
}
if (i2c_burst_write_dt(&config->bus, NCP5623_LED_CURRENT | NCP5623_MAX_BRIGHTNESS, buf,
6)) {
LOG_ERR("%s: LED write failed", dev->name);
return -EIO;
}
return 0;
}
static const struct led_driver_api ncp5623_led_api = {
.set_brightness = ncp5623_set_brightness,
.on = ncp5623_led_on,
.off = ncp5623_led_off,
.get_info = ncp5623_get_info,
.set_color = ncp5623_set_color,
};
#define COLOR_MAPPING(led_node_id) \
static const uint8_t color_mapping_##led_node_id[] = DT_PROP(led_node_id, color_mapping);
#define LED_INFO(led_node_id) \
{ \
.label = DT_PROP(led_node_id, label), \
.index = DT_PROP(led_node_id, index), \
.num_colors = DT_PROP_LEN(led_node_id, color_mapping), \
.color_mapping = color_mapping_##led_node_id, \
},
#define NCP5623_DEFINE(id) \
\
DT_INST_FOREACH_CHILD(id, COLOR_MAPPING) \
\
static const struct led_info ncp5623_leds_##id[] = {DT_INST_FOREACH_CHILD(id, LED_INFO)}; \
\
static const struct ncp5623_config ncp5623_config_##id = { \
.bus = I2C_DT_SPEC_INST_GET(id), \
.num_leds = ARRAY_SIZE(ncp5623_leds_##id), \
.leds_info = ncp5623_leds_##id, \
}; \
DEVICE_DT_INST_DEFINE(id, &ncp5623_led_init, NULL, NULL, &ncp5623_config_##id, \
POST_KERNEL, CONFIG_LED_INIT_PRIORITY, &ncp5623_led_api);
DT_INST_FOREACH_STATUS_OKAY(NCP5623_DEFINE)
``` | /content/code_sandbox/drivers/led/ncp5623.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 1,805 |
```unknown
menuconfig HT16K33
bool "HT16K33 LED driver"
default y
depends on DT_HAS_HOLTEK_HT16K33_ENABLED
select I2C
help
Enable LED driver for HT16K33.
The HT16K33 is a memory mapping, multifunction LED
controller driver. The controller supports up to 128 LEDs
(up to 16 rows and 8 commons).
config HT16K33_KEYSCAN
bool "Keyscan support"
depends on (HT16K33 && INPUT)
help
Enable keyscan child device support in the HT16K33 LED
driver.
The keyscan functionality itself is handled by the
HT16K33 keyscan driver.
if HT16K33_KEYSCAN
config HT16K33_KEYSCAN_IRQ_THREAD_STACK_SIZE
int "Stack size for keyscan interrupt request handler thread"
default 400
help
Size of the stack used for internal thread for keyscan
interrupt processing.
config HT16K33_KEYSCAN_IRQ_THREAD_PRIO
int "Priority for keyscan interrupt request handler thread"
default 2
help
Priority level for internal thread for keyscan interrupt
processing.
config HT16K33_KEYSCAN_DEBOUNCE_MSEC
int "Keyscan debounce interval in milliseconds"
default 50
range 20 1000
help
Keyscan debounce interval in milliseconds.
config HT16K33_KEYSCAN_POLL_MSEC
int "Keyscan poll interval in milliseconds"
default 200
range 20 10000
help
Keyscan poll interval in milliseconds. Polling is only used
if no interrupt line is present.
endif # HT16K33_KEYSCAN
``` | /content/code_sandbox/drivers/led/Kconfig.ht16k33 | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 364 |
```unknown
config NCP5623
bool "NCP5623 LED driver"
default y
depends on DT_HAS_ONNN_NCP5623_ENABLED
select I2C
help
Enable driver for the Onsemi NCP5623 I2C LED controller.
The controller and the driver support two hardware configurations:
- one three-channel (RGB) LED
- or three single-channel LEDs
``` | /content/code_sandbox/drivers/led/Kconfig.ncp5623 | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 86 |
```objective-c
/*
*
*/
/**
* @file
* @brief Private LED driver APIs
*/
#ifndef ZEPHYR_DRIVERS_LED_LED_CONTEXT_H_
#define ZEPHYR_DRIVERS_LED_LED_CONTEXT_H_
#ifdef __cplusplus
extern "C" {
#endif
/**
* @brief Internal driver specific representation of an LED device
*/
struct led_data {
/* Minimum acceptable LED blinking time period (in ms) */
uint32_t min_period;
/* Maximum acceptable LED blinking time period (in ms) */
uint32_t max_period;
/* Minimum acceptable LED brightness value */
uint16_t min_brightness;
/* Maximum acceptable LED brightness value */
uint16_t max_brightness;
};
#ifdef __cplusplus
}
#endif
#endif /* ZEPHYR_DRIVERS_LED_LED_CONTEXT_H_ */
``` | /content/code_sandbox/drivers/led/led_context.h | objective-c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 159 |
```c
/*
*
*/
#define DT_DRV_COMPAT ti_lp5569
/**
* @file
* @brief LP5569 LED controller
*
* The LP5569 is a 9-channel LED driver that communicates over I2C.
*/
#include <zephyr/drivers/i2c.h>
#include <zephyr/drivers/led.h>
#include <zephyr/device.h>
#include <zephyr/pm/device.h>
#include <zephyr/kernel.h>
#include <zephyr/logging/log.h>
LOG_MODULE_REGISTER(lp5569, CONFIG_LED_LOG_LEVEL);
#define LP5569_NUM_LEDS 9
/* General Registers */
#define LP5569_CONFIG 0x00
#define LP5569_CHIP_EN BIT(6)
#define LP5569_MISC 0x2F
#define LP5569_POWERSAVE_EN BIT(5)
/* PWM base Register for controlling the duty-cycle */
#define LP5569_LED0_PWM 0x16
struct lp5569_config {
struct i2c_dt_spec bus;
};
static int lp5569_led_set_brightness(const struct device *dev, uint32_t led,
uint8_t brightness)
{
const struct lp5569_config *config = dev->config;
uint8_t val;
int ret;
if (led >= LP5569_NUM_LEDS || brightness > 100) {
return -EINVAL;
}
/* Map 0-100 % to 0-255 pwm register value */
val = brightness * 255 / 100;
ret = i2c_reg_write_byte_dt(&config->bus, LP5569_LED0_PWM + led, val);
if (ret < 0) {
LOG_ERR("LED reg update failed");
return ret;
}
return 0;
}
static inline int lp5569_led_on(const struct device *dev, uint32_t led)
{
/* Set LED brightness to 100 % */
return lp5569_led_set_brightness(dev, led, 100);
}
static inline int lp5569_led_off(const struct device *dev, uint32_t led)
{
/* Set LED brightness to 0 % */
return lp5569_led_set_brightness(dev, led, 0);
}
static int lp5569_enable(const struct device *dev)
{
const struct lp5569_config *config = dev->config;
int ret;
if (!i2c_is_ready_dt(&config->bus)) {
LOG_ERR("I2C device not ready");
return -ENODEV;
}
ret = i2c_reg_write_byte_dt(&config->bus, LP5569_CONFIG,
LP5569_CHIP_EN);
if (ret < 0) {
LOG_ERR("Enable LP5569 failed");
return ret;
}
ret = i2c_reg_write_byte_dt(&config->bus, LP5569_MISC,
LP5569_POWERSAVE_EN);
if (ret < 0) {
LOG_ERR("LED reg update failed");
return ret;
}
return 0;
}
static int lp5569_init(const struct device *dev)
{
/* If the device is behind a power domain, it will start in
* PM_DEVICE_STATE_OFF.
*/
if (pm_device_on_power_domain(dev)) {
pm_device_init_off(dev);
LOG_INF("Init %s as PM_DEVICE_STATE_OFF", dev->name);
return 0;
}
return lp5569_enable(dev);
}
#ifdef CONFIG_PM_DEVICE
static int lp5569_pm_action(const struct device *dev,
enum pm_device_action action)
{
const struct lp5569_config *config = dev->config;
int ret;
switch (action) {
case PM_DEVICE_ACTION_TURN_ON:
case PM_DEVICE_ACTION_RESUME:
ret = lp5569_enable(dev);
if (ret < 0) {
LOG_ERR("Enable LP5569 failed");
return ret;
}
break;
case PM_DEVICE_ACTION_TURN_OFF:
case PM_DEVICE_ACTION_SUSPEND:
ret = i2c_reg_update_byte_dt(&config->bus, LP5569_CONFIG,
LP5569_CHIP_EN, 0);
if (ret < 0) {
LOG_ERR("Disable LP5569 failed");
return ret;
}
break;
default:
return -ENOTSUP;
}
return 0;
}
#endif /* CONFIG_PM_DEVICE */
static const struct led_driver_api lp5569_led_api = {
.set_brightness = lp5569_led_set_brightness,
.on = lp5569_led_on,
.off = lp5569_led_off,
};
#define LP5569_DEFINE(id) \
static const struct lp5569_config lp5569_config_##id = { \
.bus = I2C_DT_SPEC_INST_GET(id), \
}; \
\
PM_DEVICE_DT_INST_DEFINE(id, lp5569_pm_action); \
\
DEVICE_DT_INST_DEFINE(id, &lp5569_init, \
PM_DEVICE_DT_INST_GET(id), \
NULL, \
&lp5569_config_##id, POST_KERNEL, \
CONFIG_LED_INIT_PRIORITY, \
&lp5569_led_api);
DT_INST_FOREACH_STATUS_OKAY(LP5569_DEFINE)
``` | /content/code_sandbox/drivers/led/lp5569.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 1,097 |
```unknown
config IS31FL3733
bool "IS31FL3733 LED driver"
default y
depends on DT_HAS_ISSI_IS31FL3733_ENABLED
select I2C
help
Enable LED driver for IS31FL3733.
IS31FL3733 is a matrix LED driver, capable of a maximum of 3.29 mA
per LED, or 42 mA total across all LEDs in the 12x16 dot matrix.
``` | /content/code_sandbox/drivers/led/Kconfig.is31fl3733 | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 98 |
```unknown
config LED_PWM
bool "PWM LED driver"
default y
depends on PWM && DT_HAS_PWM_LEDS_ENABLED
help
Enable driver for PWM LEDs.
``` | /content/code_sandbox/drivers/led/Kconfig.pwm | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 36 |
```unknown
config LED_XEC
bool "Microchip XEC BB-LED driver"
default y
depends on DT_HAS_MICROCHIP_XEC_BBLED_ENABLED
help
Enable driver for the Microchip XEC Breathing-Blinking
LED controller for MEC15xx and MEC172x
``` | /content/code_sandbox/drivers/led/Kconfig.xec | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 66 |
```c
/*
*/
#define DT_DRV_COMPAT nordic_npm1300_led
#include <errno.h>
#include <zephyr/device.h>
#include <zephyr/drivers/led.h>
#include <zephyr/drivers/mfd/npm1300.h>
/* nPM1300 LED base address */
#define NPM_LED_BASE 0x0AU
/* nPM1300 LED register offsets */
#define NPM_LED_OFFSET_MODE 0x00U
#define NPM_LED_OFFSET_SET 0x03U
#define NPM_LED_OFFSET_CLR 0x04U
/* nPM1300 Channel counts */
#define NPM1300_LED_PINS 3U
/* nPM1300 LED modes */
#define NPM_LED_HOST 2U
struct led_npm1300_config {
const struct device *mfd;
uint8_t mode[NPM1300_LED_PINS];
};
static int led_npm1300_on(const struct device *dev, uint32_t led)
{
const struct led_npm1300_config *config = dev->config;
if (led >= NPM1300_LED_PINS) {
return -EINVAL;
}
if (config->mode[led] != NPM_LED_HOST) {
return -EPERM;
}
return mfd_npm1300_reg_write(config->mfd, NPM_LED_BASE, NPM_LED_OFFSET_SET + (led * 2U),
1U);
}
static int led_npm1300_off(const struct device *dev, uint32_t led)
{
const struct led_npm1300_config *config = dev->config;
if (led >= NPM1300_LED_PINS) {
return -EINVAL;
}
if (config->mode[led] != NPM_LED_HOST) {
return -EPERM;
}
return mfd_npm1300_reg_write(config->mfd, NPM_LED_BASE, NPM_LED_OFFSET_CLR + (led * 2U),
1U);
}
static const struct led_driver_api led_npm1300_api = {
.on = led_npm1300_on,
.off = led_npm1300_off,
};
static int led_npm1300_init(const struct device *dev)
{
const struct led_npm1300_config *config = dev->config;
if (!device_is_ready(config->mfd)) {
return -ENODEV;
}
for (uint8_t led = 0U; led < NPM1300_LED_PINS; led++) {
int ret = mfd_npm1300_reg_write(config->mfd, NPM_LED_BASE,
NPM_LED_OFFSET_MODE + led, config->mode[led]);
if (ret < 0) {
return ret;
}
}
return 0;
}
#define LED_NPM1300_DEFINE(n) \
static const struct led_npm1300_config led_npm1300_config##n = { \
.mfd = DEVICE_DT_GET(DT_INST_PARENT(n)), \
.mode = {DT_INST_ENUM_IDX(n, nordic_led0_mode), \
DT_INST_ENUM_IDX(n, nordic_led1_mode), \
DT_INST_ENUM_IDX(n, nordic_led2_mode)}}; \
\
DEVICE_DT_INST_DEFINE(n, &led_npm1300_init, NULL, NULL, &led_npm1300_config##n, \
POST_KERNEL, CONFIG_LED_INIT_PRIORITY, &led_npm1300_api);
DT_INST_FOREACH_STATUS_OKAY(LED_NPM1300_DEFINE)
``` | /content/code_sandbox/drivers/led/led_npm1300.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 745 |
```unknown
config IS31FL3216A
bool "IS31FL3216A LED driver"
default y
depends on DT_HAS_ISSI_IS31FL3216A_ENABLED
select I2C
help
Enable LED driver for Lumissil Microsystems (a division of ISSI)
IS31FL3216A. This chip supports up to 16 PWM controlled LEDs.
``` | /content/code_sandbox/drivers/led/Kconfig.is31fl3216a | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 81 |
```c
/*
*
*/
#define DT_DRV_COMPAT pwm_leds
/**
* @file
* @brief PWM driven LEDs
*/
#include <zephyr/drivers/led.h>
#include <zephyr/drivers/pwm.h>
#include <zephyr/device.h>
#include <zephyr/pm/device.h>
#include <zephyr/kernel.h>
#include <zephyr/sys/math_extras.h>
#include <zephyr/logging/log.h>
LOG_MODULE_REGISTER(led_pwm, CONFIG_LED_LOG_LEVEL);
struct led_pwm_config {
int num_leds;
const struct pwm_dt_spec *led;
};
static int led_pwm_blink(const struct device *dev, uint32_t led,
uint32_t delay_on, uint32_t delay_off)
{
const struct led_pwm_config *config = dev->config;
const struct pwm_dt_spec *dt_led;
uint32_t period_usec, pulse_usec;
if (led >= config->num_leds) {
return -EINVAL;
}
/*
* Convert delays (in ms) into PWM period and pulse (in us) and check
* for overflows.
*/
if (u32_add_overflow(delay_on, delay_off, &period_usec) ||
u32_mul_overflow(period_usec, 1000, &period_usec) ||
u32_mul_overflow(delay_on, 1000, &pulse_usec)) {
return -EINVAL;
}
dt_led = &config->led[led];
return pwm_set_dt(dt_led, PWM_USEC(period_usec), PWM_USEC(pulse_usec));
}
static int led_pwm_set_brightness(const struct device *dev,
uint32_t led, uint8_t value)
{
const struct led_pwm_config *config = dev->config;
const struct pwm_dt_spec *dt_led;
if (led >= config->num_leds || value > 100) {
return -EINVAL;
}
dt_led = &config->led[led];
return pwm_set_pulse_dt(&config->led[led],
(uint32_t) ((uint64_t) dt_led->period * value / 100));
}
static int led_pwm_on(const struct device *dev, uint32_t led)
{
return led_pwm_set_brightness(dev, led, 100);
}
static int led_pwm_off(const struct device *dev, uint32_t led)
{
return led_pwm_set_brightness(dev, led, 0);
}
static int led_pwm_init(const struct device *dev)
{
const struct led_pwm_config *config = dev->config;
int i;
if (!config->num_leds) {
LOG_ERR("%s: no LEDs found (DT child nodes missing)",
dev->name);
return -ENODEV;
}
for (i = 0; i < config->num_leds; i++) {
const struct pwm_dt_spec *led = &config->led[i];
if (!device_is_ready(led->dev)) {
LOG_ERR("%s: pwm device not ready", led->dev->name);
return -ENODEV;
}
}
return 0;
}
#ifdef CONFIG_PM_DEVICE
static int led_pwm_pm_action(const struct device *dev,
enum pm_device_action action)
{
const struct led_pwm_config *config = dev->config;
/* switch all underlying PWM devices to the new state */
for (size_t i = 0; i < config->num_leds; i++) {
int err;
const struct pwm_dt_spec *led = &config->led[i];
LOG_DBG("PWM %p running pm action %" PRIu32, led->dev, action);
err = pm_device_action_run(led->dev, action);
if (err && (err != -EALREADY)) {
LOG_DBG("Cannot switch PWM %p power state (err = %d)", led->dev, err);
}
}
return 0;
}
#endif /* CONFIG_PM_DEVICE */
static const struct led_driver_api led_pwm_api = {
.on = led_pwm_on,
.off = led_pwm_off,
.blink = led_pwm_blink,
.set_brightness = led_pwm_set_brightness,
};
#define LED_PWM_DEVICE(id) \
\
static const struct pwm_dt_spec led_pwm_##id[] = { \
DT_INST_FOREACH_CHILD_SEP(id, PWM_DT_SPEC_GET, (,)) \
}; \
\
static const struct led_pwm_config led_pwm_config_##id = { \
.num_leds = ARRAY_SIZE(led_pwm_##id), \
.led = led_pwm_##id, \
}; \
\
PM_DEVICE_DT_INST_DEFINE(id, led_pwm_pm_action); \
\
DEVICE_DT_INST_DEFINE(id, &led_pwm_init, \
PM_DEVICE_DT_INST_GET(id), NULL, \
&led_pwm_config_##id, POST_KERNEL, \
CONFIG_LED_INIT_PRIORITY, &led_pwm_api);
DT_INST_FOREACH_STATUS_OKAY(LED_PWM_DEVICE)
``` | /content/code_sandbox/drivers/led/led_pwm.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 1,045 |
```c
/*
*
*/
#define DT_DRV_COMPAT holtek_ht16k33
/**
* @file
* @brief LED driver for the HT16K33 I2C LED driver with keyscan
*/
#include <zephyr/drivers/gpio.h>
#include <zephyr/drivers/i2c.h>
#include <zephyr/input/input.h>
#include <zephyr/kernel.h>
#include <zephyr/drivers/led.h>
#include <zephyr/sys/byteorder.h>
#include <zephyr/logging/log.h>
LOG_MODULE_REGISTER(ht16k33, CONFIG_LED_LOG_LEVEL);
#include "led_context.h"
/* HT16K33 commands and options */
#define HT16K33_CMD_DISP_DATA_ADDR 0x00
#define HT16K33_CMD_SYSTEM_SETUP 0x20
#define HT16K33_OPT_S BIT(0)
#define HT16K33_CMD_KEY_DATA_ADDR 0x40
#define HT16K33_CMD_INT_FLAG_ADDR 0x60
#define HT16K33_CMD_DISP_SETUP 0x80
#define HT16K33_OPT_D BIT(0)
#define HT16K33_OPT_B0 BIT(1)
#define HT16K33_OPT_B1 BIT(2)
#define HT16K33_OPT_BLINK_OFF 0
#define HT16K33_OPT_BLINK_2HZ HT16K33_OPT_B0
#define HT16K33_OPT_BLINK_1HZ HT16K33_OPT_B1
#define HT16K33_OPT_BLINK_05HZ (HT16K33_OPT_B1 | HT16K33_OPT_B0)
#define HT16K33_CMD_ROW_INT_SET 0xa0
#define HT16K33_OPT_ROW_INT BIT(0)
#define HT16K33_OPT_ACT BIT(1)
#define HT16K33_OPT_ROW 0
#define HT16K33_OPT_INT_LOW HT16K33_OPT_ROW_INT
#define HT16K33_OPT_INT_HIGH (HT16K33_OPT_ACT | HT16K33_OPT_ROW_INT)
#define HT16K33_CMD_DIMMING_SET 0xe0
/* HT16K33 size definitions */
#define HT16K33_DISP_ROWS 16
#define HT16K33_DISP_COLS 8
#define HT16K33_DISP_DATA_SIZE HT16K33_DISP_ROWS
#define HT16K33_DISP_SEGMENTS (HT16K33_DISP_ROWS * HT16K33_DISP_COLS)
#define HT16K33_DIMMING_LEVELS 16
#define HT16K33_KEYSCAN_ROWS 3
#define HT16K33_KEYSCAN_COLS 13
#define HT16K33_KEYSCAN_DATA_SIZE 6
struct ht16k33_cfg {
struct i2c_dt_spec i2c;
bool irq_enabled;
#ifdef CONFIG_HT16K33_KEYSCAN
struct gpio_dt_spec irq;
#endif /* CONFIG_HT16K33_KEYSCAN */
};
struct ht16k33_data {
const struct device *dev;
struct led_data dev_data;
/* Shadow buffer for the display data RAM */
uint8_t buffer[HT16K33_DISP_DATA_SIZE];
#ifdef CONFIG_HT16K33_KEYSCAN
struct k_mutex lock;
const struct device *child;
struct gpio_callback irq_cb;
struct k_thread irq_thread;
struct k_sem irq_sem;
struct k_timer timer;
uint16_t key_state[HT16K33_KEYSCAN_ROWS];
K_KERNEL_STACK_MEMBER(irq_thread_stack,
CONFIG_HT16K33_KEYSCAN_IRQ_THREAD_STACK_SIZE);
#endif /* CONFIG_HT16K33_KEYSCAN */
};
static int ht16k33_led_blink(const struct device *dev, uint32_t led,
uint32_t delay_on, uint32_t delay_off)
{
/* The HT16K33 blinks all LEDs at the same frequency */
ARG_UNUSED(led);
const struct ht16k33_cfg *config = dev->config;
struct ht16k33_data *data = dev->data;
struct led_data *dev_data = &data->dev_data;
uint32_t period;
uint8_t cmd;
period = delay_on + delay_off;
if (period < dev_data->min_period || period > dev_data->max_period) {
return -EINVAL;
}
cmd = HT16K33_CMD_DISP_SETUP | HT16K33_OPT_D;
if (delay_off == 0) {
cmd |= HT16K33_OPT_BLINK_OFF;
} else if (period > 1500) {
cmd |= HT16K33_OPT_BLINK_05HZ;
} else if (period > 750) {
cmd |= HT16K33_OPT_BLINK_1HZ;
} else {
cmd |= HT16K33_OPT_BLINK_2HZ;
}
if (i2c_write_dt(&config->i2c, &cmd, sizeof(cmd))) {
LOG_ERR("Setting HT16K33 blink frequency failed");
return -EIO;
}
return 0;
}
static int ht16k33_led_set_brightness(const struct device *dev, uint32_t led,
uint8_t value)
{
ARG_UNUSED(led);
const struct ht16k33_cfg *config = dev->config;
struct ht16k33_data *data = dev->data;
struct led_data *dev_data = &data->dev_data;
uint8_t dim;
uint8_t cmd;
if (value < dev_data->min_brightness ||
value > dev_data->max_brightness) {
return -EINVAL;
}
dim = (value * (HT16K33_DIMMING_LEVELS - 1)) / dev_data->max_brightness;
cmd = HT16K33_CMD_DIMMING_SET | dim;
if (i2c_write_dt(&config->i2c, &cmd, sizeof(cmd))) {
LOG_ERR("Setting HT16K33 brightness failed");
return -EIO;
}
return 0;
}
static int ht16k33_led_set_state(const struct device *dev, uint32_t led,
bool on)
{
const struct ht16k33_cfg *config = dev->config;
struct ht16k33_data *data = dev->data;
uint8_t cmd[2];
uint8_t addr;
uint8_t bit;
if (led >= HT16K33_DISP_SEGMENTS) {
return -EINVAL;
}
addr = led / HT16K33_DISP_COLS;
bit = led % HT16K33_DISP_COLS;
cmd[0] = HT16K33_CMD_DISP_DATA_ADDR | addr;
if (on) {
cmd[1] = data->buffer[addr] | BIT(bit);
} else {
cmd[1] = data->buffer[addr] & ~BIT(bit);
}
if (data->buffer[addr] == cmd[1]) {
return 0;
}
if (i2c_write_dt(&config->i2c, cmd, sizeof(cmd))) {
LOG_ERR("Setting HT16K33 LED %s failed", on ? "on" : "off");
return -EIO;
}
data->buffer[addr] = cmd[1];
return 0;
}
static int ht16k33_led_on(const struct device *dev, uint32_t led)
{
return ht16k33_led_set_state(dev, led, true);
}
static int ht16k33_led_off(const struct device *dev, uint32_t led)
{
return ht16k33_led_set_state(dev, led, false);
}
#ifdef CONFIG_HT16K33_KEYSCAN
static bool ht16k33_process_keyscan_data(const struct device *dev)
{
const struct ht16k33_cfg *config = dev->config;
struct ht16k33_data *data = dev->data;
uint8_t keys[HT16K33_KEYSCAN_DATA_SIZE];
bool pressed = false;
uint16_t state;
uint16_t changed;
int row;
int col;
int err;
err = i2c_burst_read_dt(&config->i2c, HT16K33_CMD_KEY_DATA_ADDR, keys, sizeof(keys));
if (err) {
LOG_WRN("Failed to read HT16K33 key data (err %d)", err);
/* Reprocess */
return true;
}
k_mutex_lock(&data->lock, K_FOREVER);
for (row = 0; row < HT16K33_KEYSCAN_ROWS; row++) {
state = sys_get_le16(&keys[row * 2]);
changed = data->key_state[row] ^ state;
data->key_state[row] = state;
if (state) {
pressed = true;
}
for (col = 0; col < HT16K33_KEYSCAN_COLS; col++) {
if ((changed & BIT(col)) == 0) {
continue;
}
input_report_abs(dev, INPUT_ABS_X, col, false, K_FOREVER);
input_report_abs(dev, INPUT_ABS_Y, row, false, K_FOREVER);
input_report_key(dev, INPUT_BTN_TOUCH, state & BIT(col), true, K_FOREVER);
}
}
k_mutex_unlock(&data->lock);
return pressed;
}
static void ht16k33_irq_thread(void *p1, void *p2, void *p3)
{
ARG_UNUSED(p2);
ARG_UNUSED(p3);
struct ht16k33_data *data = p1;
bool pressed;
while (true) {
k_sem_take(&data->irq_sem, K_FOREVER);
do {
k_sem_reset(&data->irq_sem);
pressed = ht16k33_process_keyscan_data(data->dev);
k_msleep(CONFIG_HT16K33_KEYSCAN_DEBOUNCE_MSEC);
} while (pressed);
}
}
static void ht16k33_irq_callback(const struct device *gpiob,
struct gpio_callback *cb, uint32_t pins)
{
struct ht16k33_data *data;
ARG_UNUSED(gpiob);
ARG_UNUSED(pins);
data = CONTAINER_OF(cb, struct ht16k33_data, irq_cb);
k_sem_give(&data->irq_sem);
}
static void ht16k33_timer_callback(struct k_timer *timer)
{
struct ht16k33_data *data;
data = CONTAINER_OF(timer, struct ht16k33_data, timer);
k_sem_give(&data->irq_sem);
}
#endif /* CONFIG_HT16K33_KEYSCAN */
static int ht16k33_init(const struct device *dev)
{
const struct ht16k33_cfg *config = dev->config;
struct ht16k33_data *data = dev->data;
struct led_data *dev_data = &data->dev_data;
uint8_t cmd[1 + HT16K33_DISP_DATA_SIZE]; /* 1 byte command + data */
int err;
data->dev = dev;
if (!device_is_ready(config->i2c.bus)) {
LOG_ERR("I2C bus device not ready");
return -EINVAL;
}
memset(&data->buffer, 0, sizeof(data->buffer));
/* Hardware specific limits */
dev_data->min_period = 0U;
dev_data->max_period = 2000U;
dev_data->min_brightness = 0U;
dev_data->max_brightness = 100U;
/* System oscillator on */
cmd[0] = HT16K33_CMD_SYSTEM_SETUP | HT16K33_OPT_S;
err = i2c_write_dt(&config->i2c, cmd, 1);
if (err) {
LOG_ERR("Enabling HT16K33 system oscillator failed (err %d)",
err);
return -EIO;
}
/* Clear display RAM */
memset(cmd, 0, sizeof(cmd));
cmd[0] = HT16K33_CMD_DISP_DATA_ADDR;
err = i2c_write_dt(&config->i2c, cmd, sizeof(cmd));
if (err) {
LOG_ERR("Clearing HT16K33 display RAM failed (err %d)", err);
return -EIO;
}
/* Full brightness */
cmd[0] = HT16K33_CMD_DIMMING_SET | 0x0f;
err = i2c_write_dt(&config->i2c, cmd, 1);
if (err) {
LOG_ERR("Setting HT16K33 brightness failed (err %d)", err);
return -EIO;
}
/* Display on, blinking off */
cmd[0] = HT16K33_CMD_DISP_SETUP | HT16K33_OPT_D | HT16K33_OPT_BLINK_OFF;
err = i2c_write_dt(&config->i2c, cmd, 1);
if (err) {
LOG_ERR("Enabling HT16K33 display failed (err %d)", err);
return -EIO;
}
#ifdef CONFIG_HT16K33_KEYSCAN
k_mutex_init(&data->lock);
k_sem_init(&data->irq_sem, 0, 1);
/* Configure interrupt */
if (config->irq_enabled) {
uint8_t keys[HT16K33_KEYSCAN_DATA_SIZE];
if (!gpio_is_ready_dt(&config->irq)) {
LOG_ERR("IRQ device not ready");
return -EINVAL;
}
err = gpio_pin_configure_dt(&config->irq, GPIO_INPUT);
if (err) {
LOG_ERR("Failed to configure IRQ pin (err %d)", err);
return -EINVAL;
}
gpio_init_callback(&data->irq_cb, &ht16k33_irq_callback,
BIT(config->irq.pin));
err = gpio_add_callback(config->irq.port, &data->irq_cb);
if (err) {
LOG_ERR("Failed to add IRQ callback (err %d)", err);
return -EINVAL;
}
/* Enable interrupt pin */
cmd[0] = HT16K33_CMD_ROW_INT_SET | HT16K33_OPT_INT_LOW;
if (i2c_write_dt(&config->i2c, cmd, 1)) {
LOG_ERR("Enabling HT16K33 IRQ output failed");
return -EIO;
}
/* Flush key data before enabling interrupt */
err = i2c_burst_read_dt(&config->i2c, HT16K33_CMD_KEY_DATA_ADDR, keys,
sizeof(keys));
if (err) {
LOG_ERR("Failed to read HT16K33 key data");
return -EIO;
}
err = gpio_pin_interrupt_configure_dt(&config->irq,
GPIO_INT_EDGE_FALLING);
if (err) {
LOG_ERR("Failed to configure IRQ pin flags (err %d)",
err);
return -EINVAL;
}
} else {
/* No interrupt pin, enable ROW15 */
cmd[0] = HT16K33_CMD_ROW_INT_SET | HT16K33_OPT_ROW;
if (i2c_write_dt(&config->i2c, cmd, 1)) {
LOG_ERR("Enabling HT16K33 ROW15 output failed");
return -EIO;
}
/* Setup timer for polling key data */
k_timer_init(&data->timer, ht16k33_timer_callback, NULL);
k_timer_start(&data->timer, K_NO_WAIT,
K_MSEC(CONFIG_HT16K33_KEYSCAN_POLL_MSEC));
}
k_thread_create(&data->irq_thread, data->irq_thread_stack,
CONFIG_HT16K33_KEYSCAN_IRQ_THREAD_STACK_SIZE,
ht16k33_irq_thread, data, NULL, NULL,
K_PRIO_COOP(CONFIG_HT16K33_KEYSCAN_IRQ_THREAD_PRIO),
0, K_NO_WAIT);
#endif /* CONFIG_HT16K33_KEYSCAN */
return 0;
}
static const struct led_driver_api ht16k33_leds_api = {
.blink = ht16k33_led_blink,
.set_brightness = ht16k33_led_set_brightness,
.on = ht16k33_led_on,
.off = ht16k33_led_off,
};
#define HT16K33_DEVICE(id) \
static const struct ht16k33_cfg ht16k33_##id##_cfg = { \
.i2c = I2C_DT_SPEC_INST_GET(id), \
.irq_enabled = false, \
}; \
\
static struct ht16k33_data ht16k33_##id##_data; \
\
DEVICE_DT_INST_DEFINE(id, &ht16k33_init, NULL, \
&ht16k33_##id##_data, \
&ht16k33_##id##_cfg, POST_KERNEL, \
CONFIG_LED_INIT_PRIORITY, &ht16k33_leds_api)
#ifdef CONFIG_HT16K33_KEYSCAN
#define HT16K33_DEVICE_WITH_IRQ(id) \
static const struct ht16k33_cfg ht16k33_##id##_cfg = { \
.i2c = I2C_DT_SPEC_INST_GET(id), \
.irq_enabled = true, \
.irq = GPIO_DT_SPEC_INST_GET(id, irq_gpios), \
}; \
\
static struct ht16k33_data ht16k33_##id##_data; \
\
DEVICE_DT_INST_DEFINE(id, &ht16k33_init, NULL, \
&ht16k33_##id##_data, \
&ht16k33_##id##_cfg, POST_KERNEL, \
CONFIG_LED_INIT_PRIORITY, &ht16k33_leds_api)
#else /* ! CONFIG_HT16K33_KEYSCAN */
#define HT16K33_DEVICE_WITH_IRQ(id) HT16K33_DEVICE(id)
#endif /* ! CONFIG_HT16K33_KEYSCAN */
#define HT16K33_INSTANTIATE(id) \
COND_CODE_1(DT_INST_NODE_HAS_PROP(id, irq_gpios), \
(HT16K33_DEVICE_WITH_IRQ(id)), \
(HT16K33_DEVICE(id)));
DT_INST_FOREACH_STATUS_OKAY(HT16K33_INSTANTIATE)
``` | /content/code_sandbox/drivers/led/ht16k33.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 3,839 |
```c
/*
*
*/
#define DT_DRV_COMPAT ti_lp5562
/**
* @file
* @brief LP5562 LED driver
*
* The LP5562 is a 4-channel LED driver that communicates over I2C. The four
* channels are expected to be connected to a red, green, blue and white LED.
* Each LED can be driven by two different sources.
*
* 1. The brightness of each LED can be configured directly by setting a
* register that drives the PWM of the connected LED.
*
* 2. A program can be transferred to the driver and run by one of the three
* available execution engines. Up to 16 commands can be defined in each
* program. Possible commands are:
* - Set the brightness.
* - Fade the brightness over time.
* - Loop parts of the program or the whole program.
* - Add delays.
* - Synchronize between the engines.
*
* After the program has been transferred, it can run infinitely without
* communication between the host MCU and the driver.
*/
#include <zephyr/drivers/i2c.h>
#include <zephyr/drivers/led.h>
#include <zephyr/device.h>
#include <zephyr/kernel.h>
#define LOG_LEVEL CONFIG_LED_LOG_LEVEL
#include <zephyr/logging/log.h>
LOG_MODULE_REGISTER(lp5562);
#include "led_context.h"
/* Registers */
#define LP5562_ENABLE 0x00
#define LP5562_OP_MODE 0x01
#define LP5562_B_PWM 0x02
#define LP5562_G_PWM 0x03
#define LP5562_R_PWM 0x04
#define LP5562_B_CURRENT 0x05
#define LP5562_G_CURRENT 0x06
#define LP5562_R_CURRENT 0x07
#define LP5562_CONFIG 0x08
#define LP5562_ENG1_PC 0x09
#define LP5562_ENG2_PC 0x0A
#define LP5562_ENG3_PC 0x0B
#define LP5562_STATUS 0x0C
#define LP5562_RESET 0x0D
#define LP5562_W_PWM 0x0E
#define LP5562_W_CURRENT 0x0F
#define LP5562_PROG_MEM_ENG1_BASE 0x10
#define LP5562_PROG_MEM_ENG2_BASE 0x30
#define LP5562_PROG_MEM_ENG3_BASE 0x50
#define LP5562_LED_MAP 0x70
/*
* The wait command has six bits for the number of steps (max 63) with up to
* 15.6ms per step if the prescaler is set to 1. We round the step length
* however to 16ms for easier handling, so the maximum blinking period is
* therefore (16 * 63) = 1008ms. We round it down to 1000ms to be on the safe
* side.
*/
#define LP5562_MAX_BLINK_PERIOD 1000
/*
* The minimum waiting period is 0.49ms with the prescaler set to 0 and one
* step. We round up to a full millisecond.
*/
#define LP5562_MIN_BLINK_PERIOD 1
/* Brightness limits in percent */
#define LP5562_MIN_BRIGHTNESS 0
#define LP5562_MAX_BRIGHTNESS 100
/* Output current limits in 0.1 mA */
#define LP5562_MIN_CURRENT_SETTING 0
#define LP5562_MAX_CURRENT_SETTING 255
/* Values for ENABLE register. */
#define LP5562_ENABLE_CHIP_EN (1 << 6)
#define LP5562_ENABLE_LOG_EN (1 << 7)
/* Values for CONFIG register. */
#define LP5562_CONFIG_EXTERNAL_CLOCK 0x00
#define LP5562_CONFIG_INTERNAL_CLOCK 0x01
#define LP5562_CONFIG_CLOCK_AUTOMATIC_SELECT 0x02
#define LP5562_CONFIG_PWRSAVE_EN (1 << 5)
/* Enable 558 Hz frequency for PWM. Default is 256. */
#define LP5562_CONFIG_PWM_HW_FREQ_558 (1 << 6)
/* Values for execution engine programs. */
#define LP5562_PROG_COMMAND_SET_PWM (1 << 6)
#define LP5562_PROG_COMMAND_RAMP_TIME(prescale, step_time) \
(((prescale) << 6) | (step_time))
#define LP5562_PROG_COMMAND_STEP_COUNT(fade_direction, count) \
(((fade_direction) << 7) | (count))
/* Helper definitions. */
#define LP5562_PROG_MAX_COMMANDS 16
#define LP5562_MASK 0x03
#define LP5562_CHANNEL_MASK(channel) ((LP5562_MASK) << (channel << 1))
/*
* Available channels. There are four LED channels usable with the LP5562. While
* they can be mapped to LEDs of any color, the driver's typical application is
* with a red, a green, a blue and a white LED. Since the data sheet's
* nomenclature uses RGBW, we keep it that way.
*/
enum lp5562_led_channels {
LP5562_CHANNEL_B,
LP5562_CHANNEL_G,
LP5562_CHANNEL_R,
LP5562_CHANNEL_W,
LP5562_CHANNEL_COUNT,
};
/*
* Each channel can be driven by directly assigning a value between 0 and 255 to
* it to drive the PWM or by one of the three execution engines that can be
* programmed for custom lighting patterns in order to reduce the I2C traffic
* for repetitive patterns.
*/
enum lp5562_led_sources {
LP5562_SOURCE_PWM,
LP5562_SOURCE_ENGINE_1,
LP5562_SOURCE_ENGINE_2,
LP5562_SOURCE_ENGINE_3,
LP5562_SOURCE_COUNT,
};
/* Operational modes of the execution engines. */
enum lp5562_engine_op_modes {
LP5562_OP_MODE_DISABLED = 0x00,
LP5562_OP_MODE_LOAD = 0x01,
LP5562_OP_MODE_RUN = 0x02,
LP5562_OP_MODE_DIRECT_CTRL = 0x03,
};
/* Execution state of the engines. */
enum lp5562_engine_exec_states {
LP5562_ENGINE_MODE_HOLD = 0x00,
LP5562_ENGINE_MODE_STEP = 0x01,
LP5562_ENGINE_MODE_RUN = 0x02,
LP5562_ENGINE_MODE_EXEC = 0x03,
};
/* Fading directions for programs executed by the engines. */
enum lp5562_engine_fade_dirs {
LP5562_FADE_UP = 0x00,
LP5562_FADE_DOWN = 0x01,
};
struct lp5562_config {
struct i2c_dt_spec bus;
uint8_t r_current;
uint8_t g_current;
uint8_t b_current;
uint8_t w_current;
};
struct lp5562_data {
struct led_data dev_data;
};
/*
* @brief Get the register for the given LED channel used to directly write a
* brightness value instead of using the execution engines.
*
* @param channel LED channel.
* @param reg Pointer to the register address.
*
* @retval 0 On success.
* @retval -EINVAL If an invalid channel is given.
*/
static int lp5562_get_pwm_reg(enum lp5562_led_channels channel, uint8_t *reg)
{
switch (channel) {
case LP5562_CHANNEL_W:
*reg = LP5562_W_PWM;
break;
case LP5562_CHANNEL_R:
*reg = LP5562_R_PWM;
break;
case LP5562_CHANNEL_G:
*reg = LP5562_G_PWM;
break;
case LP5562_CHANNEL_B:
*reg = LP5562_B_PWM;
break;
default:
LOG_ERR("Invalid channel given.");
return -EINVAL;
}
return 0;
}
/*
* @brief Get the base address for programs of the given execution engine.
*
* @param engine Engine the base address is requested for.
* @param base_addr Pointer to the base address.
*
* @retval 0 On success.
* @retval -EINVAL If a source is given that is not a valid engine.
*/
static int lp5562_get_engine_ram_base_addr(enum lp5562_led_sources engine,
uint8_t *base_addr)
{
switch (engine) {
case LP5562_SOURCE_ENGINE_1:
*base_addr = LP5562_PROG_MEM_ENG1_BASE;
break;
case LP5562_SOURCE_ENGINE_2:
*base_addr = LP5562_PROG_MEM_ENG2_BASE;
break;
case LP5562_SOURCE_ENGINE_3:
*base_addr = LP5562_PROG_MEM_ENG3_BASE;
break;
default:
return -EINVAL;
}
return 0;
}
/*
* @brief Helper to get the register bit shift for the execution engines.
*
* The engine with the highest index is placed on the lowest two bits in the
* OP_MODE and ENABLE registers.
*
* @param engine Engine the shift is requested for.
* @param shift Pointer to the shift value.
*
* @retval 0 On success.
* @retval -EINVAL If a source is given that is not a valid engine.
*/
static int lp5562_get_engine_reg_shift(enum lp5562_led_sources engine,
uint8_t *shift)
{
switch (engine) {
case LP5562_SOURCE_ENGINE_1:
*shift = 4U;
break;
case LP5562_SOURCE_ENGINE_2:
*shift = 2U;
break;
case LP5562_SOURCE_ENGINE_3:
*shift = 0U;
break;
default:
return -EINVAL;
}
return 0;
}
/*
* @brief Convert a time in milliseconds to a combination of prescale and
* step_time for the execution engine programs.
*
* This function expects the given time in milliseconds to be in the allowed
* range the device can handle (0ms to 1000ms).
*
* @param data Capabilities of the driver.
* @param ms Time to be converted in milliseconds [0..1000].
* @param prescale Pointer to the prescale value.
* @param step_time Pointer to the step_time value.
*/
static void lp5562_ms_to_prescale_and_step(struct led_data *data, uint32_t ms,
uint8_t *prescale, uint8_t *step_time)
{
/*
* One step with the prescaler set to 0 takes 0.49ms. The max value for
* step_time is 63, so we just double the millisecond value. That way
* the step_time value never goes above the allowed 63.
*/
if (ms < 31) {
*prescale = 0U;
*step_time = ms << 1;
return;
}
/*
* With a prescaler value set to 1 one step takes 15.6ms. So by dividing
* through 16 we get a decent enough result with low effort.
*/
*prescale = 1U;
*step_time = ms >> 4;
return;
}
/*
* @brief Assign a source to the given LED channel.
*
* @param dev LP5562 device.
* @param channel LED channel the source is assigned to.
* @param source Source for the channel.
*
* @retval 0 On success.
* @retval -EIO If the underlying I2C call fails.
*/
static int lp5562_set_led_source(const struct device *dev,
enum lp5562_led_channels channel,
enum lp5562_led_sources source)
{
const struct lp5562_config *config = dev->config;
if (i2c_reg_update_byte_dt(&config->bus, LP5562_LED_MAP,
LP5562_CHANNEL_MASK(channel),
source << (channel << 1))) {
LOG_ERR("LED reg update failed.");
return -EIO;
}
return 0;
}
/*
* @brief Get the assigned source of the given LED channel.
*
* @param dev LP5562 device.
* @param channel Requested LED channel.
* @param source Pointer to the source of the channel.
*
* @retval 0 On success.
* @retval -EIO If the underlying I2C call fails.
*/
static int lp5562_get_led_source(const struct device *dev,
enum lp5562_led_channels channel,
enum lp5562_led_sources *source)
{
const struct lp5562_config *config = dev->config;
uint8_t led_map;
if (i2c_reg_read_byte_dt(&config->bus, LP5562_LED_MAP, &led_map)) {
return -EIO;
}
*source = (led_map >> (channel << 1)) & LP5562_MASK;
return 0;
}
/*
* @brief Request whether an engine is currently running.
*
* @param dev LP5562 device.
* @param engine Engine to check.
*
* @return Indication of the engine execution state.
*
* @retval true If the engine is currently running.
* @retval false If the engine is not running or an error occurred.
*/
static bool lp5562_is_engine_executing(const struct device *dev,
enum lp5562_led_sources engine)
{
const struct lp5562_config *config = dev->config;
uint8_t enabled, shift;
int ret;
ret = lp5562_get_engine_reg_shift(engine, &shift);
if (ret) {
return false;
}
if (i2c_reg_read_byte_dt(&config->bus, LP5562_ENABLE, &enabled)) {
LOG_ERR("Failed to read ENABLE register.");
return false;
}
enabled = (enabled >> shift) & LP5562_MASK;
if (enabled == LP5562_ENGINE_MODE_RUN) {
return true;
}
return false;
}
/*
* @brief Get an available execution engine that is currently unused.
*
* @param dev LP5562 device.
* @param engine Pointer to the engine ID.
*
* @retval 0 On success.
* @retval -ENODEV If all engines are busy.
*/
static int lp5562_get_available_engine(const struct device *dev,
enum lp5562_led_sources *engine)
{
enum lp5562_led_sources src;
for (src = LP5562_SOURCE_ENGINE_1; src < LP5562_SOURCE_COUNT; src++) {
if (!lp5562_is_engine_executing(dev, src)) {
LOG_DBG("Available engine: %d", src);
*engine = src;
return 0;
}
}
LOG_ERR("No unused engine available");
return -ENODEV;
}
/*
* @brief Set an register shifted for the given execution engine.
*
* @param dev LP5562 device.
* @param engine Engine the value is shifted for.
* @param reg Register address to set.
* @param val Value to set.
*
* @retval 0 On success.
* @retval -EIO If the underlying I2C call fails.
*/
static int lp5562_set_engine_reg(const struct device *dev,
enum lp5562_led_sources engine,
uint8_t reg, uint8_t val)
{
const struct lp5562_config *config = dev->config;
uint8_t shift;
int ret;
ret = lp5562_get_engine_reg_shift(engine, &shift);
if (ret) {
return ret;
}
if (i2c_reg_update_byte_dt(&config->bus, reg, LP5562_MASK << shift,
val << shift)) {
return -EIO;
}
return 0;
}
/*
* @brief Set the operational mode of the given engine.
*
* @param dev LP5562 device.
* @param engine Engine the operational mode is changed for.
* @param mode Mode to set.
*
* @retval 0 On success.
* @retval -EIO If the underlying I2C call fails.
*/
static inline int lp5562_set_engine_op_mode(const struct device *dev,
enum lp5562_led_sources engine,
enum lp5562_engine_op_modes mode)
{
return lp5562_set_engine_reg(dev, engine, LP5562_OP_MODE, mode);
}
/*
* @brief Set the execution state of the given engine.
*
* @param dev LP5562 device.
* @param engine Engine the execution state is changed for.
* @param state State to set.
*
* @retval 0 On success.
* @retval -EIO If the underlying I2C call fails.
*/
static inline int lp5562_set_engine_exec_state(const struct device *dev,
enum lp5562_led_sources engine,
enum lp5562_engine_exec_states state)
{
int ret;
ret = lp5562_set_engine_reg(dev, engine, LP5562_ENABLE, state);
/*
* Delay between consecutive I2C writes to
* ENABLE register (00h) need to be longer than 488s (typ.).
*/
k_sleep(K_MSEC(1));
return ret;
}
/*
* @brief Start the execution of the program of the given engine.
*
* @param dev LP5562 device.
* @param engine Engine that is started.
*
* @retval 0 On success.
* @retval -EIO If the underlying I2C call fails.
*/
static inline int lp5562_start_program_exec(const struct device *dev,
enum lp5562_led_sources engine)
{
if (lp5562_set_engine_op_mode(dev, engine, LP5562_OP_MODE_RUN)) {
return -EIO;
}
return lp5562_set_engine_exec_state(dev, engine,
LP5562_ENGINE_MODE_RUN);
}
/*
* @brief Stop the execution of the program of the given engine.
*
* @param dev LP5562 device.
* @param engine Engine that is stopped.
*
* @retval 0 On success.
* @retval -EIO If the underlying I2C call fails.
*/
static inline int lp5562_stop_program_exec(const struct device *dev,
enum lp5562_led_sources engine)
{
if (lp5562_set_engine_op_mode(dev, engine, LP5562_OP_MODE_DISABLED)) {
return -EIO;
}
return lp5562_set_engine_exec_state(dev, engine,
LP5562_ENGINE_MODE_HOLD);
}
/*
* @brief Program a command to the memory of the given execution engine.
*
* @param dev LP5562 device.
* @param engine Engine that is programmed.
* @param command_index Index of the command that is programmed.
* @param command_msb Most significant byte of the command.
* @param command_lsb Least significant byte of the command.
*
* @retval 0 On success.
* @retval -EINVAL If the given command index is out of range or an invalid
* engine is passed.
* @retval -EIO If the underlying I2C call fails.
*/
static int lp5562_program_command(const struct device *dev,
enum lp5562_led_sources engine,
uint8_t command_index,
uint8_t command_msb,
uint8_t command_lsb)
{
const struct lp5562_config *config = dev->config;
uint8_t prog_base_addr;
int ret;
if (command_index >= LP5562_PROG_MAX_COMMANDS) {
return -EINVAL;
}
ret = lp5562_get_engine_ram_base_addr(engine, &prog_base_addr);
if (ret) {
LOG_ERR("Failed to get base RAM address.");
return ret;
}
if (i2c_reg_write_byte_dt(&config->bus,
prog_base_addr + (command_index << 1),
command_msb)) {
LOG_ERR("Failed to update LED.");
return -EIO;
}
if (i2c_reg_write_byte_dt(&config->bus,
prog_base_addr + (command_index << 1) + 1,
command_lsb)) {
LOG_ERR("Failed to update LED.");
return -EIO;
}
return 0;
}
/*
* @brief Program a command to set a fixed brightness to the given engine.
*
* @param dev LP5562 device.
* @param engine Engine to be programmed.
* @param command_index Index of the command in the program sequence.
* @param brightness Brightness to be set for the LED in percent.
*
* @retval 0 On success.
* @retval -EINVAL If the passed arguments are invalid or out of range.
* @retval -EIO If the underlying I2C call fails.
*/
static int lp5562_program_set_brightness(const struct device *dev,
enum lp5562_led_sources engine,
uint8_t command_index,
uint8_t brightness)
{
struct lp5562_data *data = dev->data;
struct led_data *dev_data = &data->dev_data;
uint8_t val;
if ((brightness < dev_data->min_brightness) ||
(brightness > dev_data->max_brightness)) {
return -EINVAL;
}
val = (brightness * 0xFF) / dev_data->max_brightness;
return lp5562_program_command(dev, engine, command_index,
LP5562_PROG_COMMAND_SET_PWM, val);
}
/*
* @brief Program a command to ramp the brightness over time.
*
* In each step the PWM value is increased or decreased by 1/255th until the
* maximum or minimum value is reached or step_count steps have been done.
*
* @param dev LP5562 device.
* @param engine Engine to be programmed.
* @param command_index Index of the command in the program sequence.
* @param time_per_step Time each step takes in milliseconds.
* @param step_count Number of steps to perform.
* @param fade_dir Direction of the ramp (in-/decrease brightness).
*
* @retval 0 On success.
* @retval -EINVAL If the passed arguments are invalid or out of range.
* @retval -EIO If the underlying I2C call fails.
*/
static int lp5562_program_ramp(const struct device *dev,
enum lp5562_led_sources engine,
uint8_t command_index,
uint32_t time_per_step,
uint8_t step_count,
enum lp5562_engine_fade_dirs fade_dir)
{
struct lp5562_data *data = dev->data;
struct led_data *dev_data = &data->dev_data;
uint8_t prescale, step_time;
if ((time_per_step < dev_data->min_period) ||
(time_per_step > dev_data->max_period)) {
return -EINVAL;
}
lp5562_ms_to_prescale_and_step(dev_data, time_per_step,
&prescale, &step_time);
return lp5562_program_command(dev, engine, command_index,
LP5562_PROG_COMMAND_RAMP_TIME(prescale, step_time),
LP5562_PROG_COMMAND_STEP_COUNT(fade_dir, step_count));
}
/*
* @brief Program a command to do nothing for the given time.
*
* @param dev LP5562 device.
* @param engine Engine to be programmed.
* @param command_index Index of the command in the program sequence.
* @param time Time to do nothing in milliseconds.
*
* @retval 0 On success.
* @retval -EINVAL If the passed arguments are invalid or out of range.
* @retval -EIO If the underlying I2C call fails.
*/
static inline int lp5562_program_wait(const struct device *dev,
enum lp5562_led_sources engine,
uint8_t command_index,
uint32_t time)
{
/*
* A wait command is a ramp with the step_count set to 0. The fading
* direction does not matter in this case.
*/
return lp5562_program_ramp(dev, engine, command_index,
time, 0, LP5562_FADE_UP);
}
/*
* @brief Program a command to go back to the beginning of the program.
*
* Can be used at the end of a program to loop it infinitely.
*
* @param dev LP5562 device.
* @param engine Engine to be programmed.
* @param command_index Index of the command in the program sequence.
*
* @retval 0 On success.
* @retval -EINVAL If the given command index is out of range or an invalid
* engine is passed.
* @retval -EIO If the underlying I2C call fails.
*/
static inline int lp5562_program_go_to_start(const struct device *dev,
enum lp5562_led_sources engine,
uint8_t command_index)
{
return lp5562_program_command(dev, engine, command_index, 0x00, 0x00);
}
/*
* @brief Change the brightness of a running blink program.
*
* We know that the current program executes a blinking pattern
* consisting of following commands:
*
* - set_brightness high
* - wait on_delay
* - set_brightness low
* - wait off_delay
* - return to start
*
* In order to change the brightness during blinking, we overwrite only
* the first command and start execution again.
*
* @param dev LP5562 device.
* @param engine Engine running the blinking program.
* @param brightness_on New brightness value.
*
* @retval 0 On Success.
* @retval -EINVAL If the engine ID or brightness is out of range.
* @retval -EIO If the underlying I2C call fails.
*/
static int lp5562_update_blinking_brightness(const struct device *dev,
enum lp5562_led_sources engine,
uint8_t brightness_on)
{
int ret;
ret = lp5562_stop_program_exec(dev, engine);
if (ret) {
return ret;
}
ret = lp5562_set_engine_op_mode(dev, engine, LP5562_OP_MODE_LOAD);
if (ret) {
return ret;
}
ret = lp5562_program_set_brightness(dev, engine, 0, brightness_on);
if (ret) {
return ret;
}
ret = lp5562_start_program_exec(dev, engine);
if (ret) {
LOG_ERR("Failed to execute program.");
return ret;
}
return 0;
}
static int lp5562_led_blink(const struct device *dev, uint32_t led,
uint32_t delay_on, uint32_t delay_off)
{
struct lp5562_data *data = dev->data;
struct led_data *dev_data = &data->dev_data;
int ret;
enum lp5562_led_sources engine;
uint8_t command_index = 0U;
ret = lp5562_get_available_engine(dev, &engine);
if (ret) {
return ret;
}
ret = lp5562_set_led_source(dev, led, engine);
if (ret) {
LOG_ERR("Failed to set LED source.");
return ret;
}
ret = lp5562_set_engine_op_mode(dev, engine, LP5562_OP_MODE_LOAD);
if (ret) {
return ret;
}
ret = lp5562_program_set_brightness(dev, engine, command_index,
dev_data->max_brightness);
if (ret) {
return ret;
}
ret = lp5562_program_wait(dev, engine, ++command_index, delay_on);
if (ret) {
return ret;
}
ret = lp5562_program_set_brightness(dev, engine, ++command_index,
dev_data->min_brightness);
if (ret) {
return ret;
}
ret = lp5562_program_wait(dev, engine, ++command_index, delay_off);
if (ret) {
return ret;
}
ret = lp5562_program_go_to_start(dev, engine, ++command_index);
if (ret) {
return ret;
}
ret = lp5562_start_program_exec(dev, engine);
if (ret) {
LOG_ERR("Failed to execute program.");
return ret;
}
return 0;
}
static int lp5562_led_set_brightness(const struct device *dev, uint32_t led,
uint8_t value)
{
const struct lp5562_config *config = dev->config;
struct lp5562_data *data = dev->data;
struct led_data *dev_data = &data->dev_data;
int ret;
uint8_t val, reg;
enum lp5562_led_sources current_source;
if ((value < dev_data->min_brightness) ||
(value > dev_data->max_brightness)) {
return -EINVAL;
}
ret = lp5562_get_led_source(dev, led, ¤t_source);
if (ret) {
return ret;
}
if (current_source != LP5562_SOURCE_PWM) {
if (lp5562_is_engine_executing(dev, current_source)) {
/*
* LED is blinking currently. Restart the blinking with
* the passed brightness.
*/
return lp5562_update_blinking_brightness(dev,
current_source, value);
}
ret = lp5562_set_led_source(dev, led, LP5562_SOURCE_PWM);
if (ret) {
return ret;
}
}
val = (value * 0xFF) / dev_data->max_brightness;
ret = lp5562_get_pwm_reg(led, ®);
if (ret) {
return ret;
}
if (i2c_reg_write_byte_dt(&config->bus, reg, val)) {
LOG_ERR("LED write failed");
return -EIO;
}
return 0;
}
static inline int lp5562_led_on(const struct device *dev, uint32_t led)
{
struct lp5562_data *data = dev->data;
struct led_data *dev_data = &data->dev_data;
return lp5562_led_set_brightness(dev, led, dev_data->max_brightness);
}
static inline int lp5562_led_off(const struct device *dev, uint32_t led)
{
struct lp5562_data *data = dev->data;
struct led_data *dev_data = &data->dev_data;
int ret;
enum lp5562_led_sources current_source;
ret = lp5562_get_led_source(dev, led, ¤t_source);
if (ret) {
return ret;
}
if (current_source != LP5562_SOURCE_PWM) {
ret = lp5562_stop_program_exec(dev, current_source);
if (ret) {
return ret;
}
}
return lp5562_led_set_brightness(dev, led, dev_data->min_brightness);
}
static int lp5562_led_update_current(const struct device *dev)
{
const struct lp5562_config *config = dev->config;
int ret;
uint8_t tx_buf[4] = {
LP5562_B_CURRENT,
config->b_current,
config->g_current,
config->r_current };
ret = i2c_write_dt(&config->bus, tx_buf, sizeof(tx_buf));
if (ret == 0) {
ret = i2c_reg_write_byte_dt(&config->bus, LP5562_W_CURRENT, config->w_current);
}
return ret;
}
static int lp5562_led_init(const struct device *dev)
{
const struct lp5562_config *config = dev->config;
struct lp5562_data *data = dev->data;
struct led_data *dev_data = &data->dev_data;
int ret;
if (!device_is_ready(config->bus.bus)) {
LOG_ERR("I2C device not ready");
return -ENODEV;
}
/* Hardware specific limits */
dev_data->min_period = LP5562_MIN_BLINK_PERIOD;
dev_data->max_period = LP5562_MAX_BLINK_PERIOD;
dev_data->min_brightness = LP5562_MIN_BRIGHTNESS;
dev_data->max_brightness = LP5562_MAX_BRIGHTNESS;
ret = lp5562_led_update_current(dev);
if (ret) {
LOG_ERR("Setting current setting LP5562 LED chip failed.");
return ret;
}
if (i2c_reg_write_byte_dt(&config->bus, LP5562_ENABLE,
LP5562_ENABLE_CHIP_EN)) {
LOG_ERR("Enabling LP5562 LED chip failed.");
return -EIO;
}
if (i2c_reg_write_byte_dt(&config->bus, LP5562_CONFIG,
(LP5562_CONFIG_INTERNAL_CLOCK |
LP5562_CONFIG_PWRSAVE_EN))) {
LOG_ERR("Configuring LP5562 LED chip failed.");
return -EIO;
}
if (i2c_reg_write_byte_dt(&config->bus, LP5562_OP_MODE, 0x00)) {
LOG_ERR("Disabling all engines failed.");
return -EIO;
}
if (i2c_reg_write_byte_dt(&config->bus, LP5562_LED_MAP, 0x00)) {
LOG_ERR("Setting all LEDs to manual control failed.");
return -EIO;
}
return 0;
}
static const struct led_driver_api lp5562_led_api = {
.blink = lp5562_led_blink,
.set_brightness = lp5562_led_set_brightness,
.on = lp5562_led_on,
.off = lp5562_led_off,
};
#define LP5562_DEFINE(id) \
BUILD_ASSERT(DT_INST_PROP(id, red_output_current) <= LP5562_MAX_CURRENT_SETTING,\
"Red channel current must be between 0 and 25.5 mA."); \
BUILD_ASSERT(DT_INST_PROP(id, green_output_current) <= LP5562_MAX_CURRENT_SETTING,\
"Green channel current must be between 0 and 25.5 mA."); \
BUILD_ASSERT(DT_INST_PROP(id, blue_output_current) <= LP5562_MAX_CURRENT_SETTING,\
"Blue channel current must be between 0 and 25.5 mA."); \
BUILD_ASSERT(DT_INST_PROP(id, white_output_current) <= LP5562_MAX_CURRENT_SETTING,\
"White channel current must be between 0 and 25.5 mA."); \
static const struct lp5562_config lp5562_config_##id = { \
.bus = I2C_DT_SPEC_INST_GET(id), \
.r_current = DT_INST_PROP(id, red_output_current), \
.g_current = DT_INST_PROP(id, green_output_current), \
.b_current = DT_INST_PROP(id, blue_output_current), \
.w_current = DT_INST_PROP(id, white_output_current), \
}; \
\
struct lp5562_data lp5562_data_##id; \
DEVICE_DT_INST_DEFINE(id, &lp5562_led_init, NULL, \
&lp5562_data_##id, \
&lp5562_config_##id, POST_KERNEL, \
CONFIG_LED_INIT_PRIORITY, \
&lp5562_led_api); \
DT_INST_FOREACH_STATUS_OKAY(LP5562_DEFINE)
``` | /content/code_sandbox/drivers/led/lp5562.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 7,435 |
```unknown
config TLC59108
bool "TLC59108 LED driver"
default y
depends on DT_HAS_TI_TLC59108_ENABLED
select I2C
help
Enable LED driver for TLC59108.
``` | /content/code_sandbox/drivers/led/Kconfig.tlc59108 | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 47 |
```unknown
# Top-level configuration file for LED drivers.
menuconfig LED
bool "Light-Emitting Diode (LED) drivers"
help
Include LED drivers in the system configuration.
if LED
module = LED
module-str = led
source "subsys/logging/Kconfig.template.log_config"
config LED_INIT_PRIORITY
int "LED initialization priority"
default 90
help
System initialization priority for LED drivers.
config LED_SHELL
bool "LED shell"
depends on SHELL
help
Enable LED shell for testing.
source "drivers/led/Kconfig.gpio"
source "drivers/led/Kconfig.ht16k33"
source "drivers/led/Kconfig.is31fl3216a"
source "drivers/led/Kconfig.lp3943"
source "drivers/led/Kconfig.lp50xx"
source "drivers/led/Kconfig.lp5562"
source "drivers/led/Kconfig.lp5569"
source "drivers/led/Kconfig.ncp5623"
source "drivers/led/Kconfig.npm1300"
source "drivers/led/Kconfig.pca9633"
source "drivers/led/Kconfig.pwm"
source "drivers/led/Kconfig.tlc59108"
source "drivers/led/Kconfig.xec"
source "drivers/led/Kconfig.is31fl3733"
source "drivers/led/Kconfig.is31fl3194"
endif # LED
``` | /content/code_sandbox/drivers/led/Kconfig | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 290 |
```c
/*
*
*/
#include <zephyr/shell/shell.h>
#include <zephyr/drivers/led.h>
#include <zephyr/dt-bindings/led/led.h>
#include <stdlib.h>
#define LOG_LEVEL CONFIG_LOG_DEFAULT_LEVEL
#include <zephyr/logging/log.h>
LOG_MODULE_REGISTER(led_shell);
#define MAX_CHANNEL_ARGS 8
enum {
arg_idx_dev = 1,
arg_idx_led = 2,
arg_idx_value = 3,
};
static int parse_common_args(const struct shell *sh, char **argv,
const struct device * *dev, uint32_t *led)
{
char *end_ptr;
*dev = device_get_binding(argv[arg_idx_dev]);
if (!*dev) {
shell_error(sh,
"LED device %s not found", argv[arg_idx_dev]);
return -ENODEV;
}
*led = strtoul(argv[arg_idx_led], &end_ptr, 0);
if (*end_ptr != '\0') {
shell_error(sh, "Invalid LED number parameter %s",
argv[arg_idx_led]);
return -EINVAL;
}
return 0;
}
static int cmd_off(const struct shell *sh, size_t argc, char **argv)
{
const struct device *dev;
uint32_t led;
int err;
err = parse_common_args(sh, argv, &dev, &led);
if (err < 0) {
return err;
}
shell_print(sh, "%s: turning off LED %d", dev->name, led);
err = led_off(dev, led);
if (err) {
shell_error(sh, "Error: %d", err);
}
return err;
}
static int cmd_on(const struct shell *sh, size_t argc, char **argv)
{
const struct device *dev;
uint32_t led;
int err;
err = parse_common_args(sh, argv, &dev, &led);
if (err < 0) {
return err;
}
shell_print(sh, "%s: turning on LED %d", dev->name, led);
err = led_on(dev, led);
if (err) {
shell_error(sh, "Error: %d", err);
}
return err;
}
static const char *led_color_to_str(uint8_t color)
{
switch (color) {
case LED_COLOR_ID_WHITE:
return "white";
case LED_COLOR_ID_RED:
return "red";
case LED_COLOR_ID_GREEN:
return "green";
case LED_COLOR_ID_BLUE:
return "blue";
case LED_COLOR_ID_VIOLET:
return "violet";
case LED_COLOR_ID_YELLOW:
return "yellow";
case LED_COLOR_ID_IR:
return "IR";
default:
return "unknown";
}
}
static int cmd_get_info(const struct shell *sh, size_t argc, char **argv)
{
const struct device *dev;
uint32_t led;
int err;
const struct led_info *info;
int i;
err = parse_common_args(sh, argv, &dev, &led);
if (err < 0) {
return err;
}
shell_print(sh, "%s: getting LED %d information", dev->name, led);
err = led_get_info(dev, led, &info);
if (err) {
shell_error(sh, "Error: %d", err);
return err;
}
shell_print(sh, "Label : %s", info->label ? : "<NULL>");
shell_print(sh, "Index : %d", info->index);
shell_print(sh, "Num colors : %d", info->num_colors);
if (info->color_mapping) {
shell_fprintf(sh, SHELL_NORMAL, "Colors : %s",
led_color_to_str(info->color_mapping[0]));
for (i = 1; i < info->num_colors; i++) {
shell_fprintf(sh, SHELL_NORMAL, ":%s",
led_color_to_str(info->color_mapping[i]));
}
shell_fprintf(sh, SHELL_NORMAL, "\n");
}
return 0;
}
static int cmd_set_brightness(const struct shell *sh,
size_t argc, char **argv)
{
const struct device *dev;
uint32_t led;
int err;
char *end_ptr;
unsigned long value;
err = parse_common_args(sh, argv, &dev, &led);
if (err < 0) {
return err;
}
value = strtoul(argv[arg_idx_value], &end_ptr, 0);
if (*end_ptr != '\0') {
shell_error(sh, "Invalid LED brightness parameter %s",
argv[arg_idx_value]);
return -EINVAL;
}
if (value > 100) {
shell_error(sh, "Invalid LED brightness value %lu (max 100)",
value);
return -EINVAL;
}
shell_print(sh, "%s: setting LED %d brightness to %lu",
dev->name, led, value);
err = led_set_brightness(dev, led, (uint8_t) value);
if (err) {
shell_error(sh, "Error: %d", err);
}
return err;
}
static int cmd_set_color(const struct shell *sh, size_t argc, char **argv)
{
const struct device *dev;
uint32_t led;
int err;
size_t num_colors;
uint8_t i;
uint8_t color[MAX_CHANNEL_ARGS];
err = parse_common_args(sh, argv, &dev, &led);
if (err < 0) {
return err;
}
num_colors = argc - arg_idx_value;
if (num_colors > MAX_CHANNEL_ARGS) {
shell_error(sh,
"Invalid number of colors %d (max %d)",
num_colors, MAX_CHANNEL_ARGS);
return -EINVAL;
}
for (i = 0; i < num_colors; i++) {
char *end_ptr;
unsigned long col;
col = strtoul(argv[arg_idx_value + i], &end_ptr, 0);
if (*end_ptr != '\0') {
shell_error(sh, "Invalid LED color parameter %s",
argv[arg_idx_value + i]);
return -EINVAL;
}
if (col > 255) {
shell_error(sh,
"Invalid LED color value %lu (max 255)",
col);
return -EINVAL;
}
color[i] = col;
}
shell_fprintf(sh, SHELL_NORMAL, "%s: setting LED %d color to %d",
dev->name, led, color[0]);
for (i = 1; i < num_colors; i++) {
shell_fprintf(sh, SHELL_NORMAL, ":%d", color[i]);
}
shell_fprintf(sh, SHELL_NORMAL, "\n");
err = led_set_color(dev, led, num_colors, color);
if (err) {
shell_error(sh, "Error: %d", err);
}
return err;
}
static int cmd_set_channel(const struct shell *sh, size_t argc, char **argv)
{
const struct device *dev;
uint32_t channel;
int err;
char *end_ptr;
unsigned long value;
err = parse_common_args(sh, argv, &dev, &channel);
if (err < 0) {
return err;
}
value = strtoul(argv[arg_idx_value], &end_ptr, 0);
if (*end_ptr != '\0') {
shell_error(sh, "Invalid channel value parameter %s",
argv[arg_idx_value]);
return -EINVAL;
}
if (value > 255) {
shell_error(sh, "Invalid channel value %lu (max 255)",
value);
return -EINVAL;
}
shell_print(sh, "%s: setting channel %d to %lu",
dev->name, channel, value);
err = led_set_channel(dev, channel, (uint8_t) value);
if (err) {
shell_error(sh, "Error: %d", err);
}
return err;
}
static int
cmd_write_channels(const struct shell *sh, size_t argc, char **argv)
{
const struct device *dev;
uint32_t start_channel;
int err;
size_t num_channels;
uint8_t i;
uint8_t value[MAX_CHANNEL_ARGS];
err = parse_common_args(sh, argv, &dev, &start_channel);
if (err < 0) {
return err;
}
num_channels = argc - arg_idx_value;
if (num_channels > MAX_CHANNEL_ARGS) {
shell_error(sh,
"Can't write %d channels (max %d)",
num_channels, MAX_CHANNEL_ARGS);
return -EINVAL;
}
for (i = 0; i < num_channels; i++) {
char *end_ptr;
unsigned long val;
val = strtoul(argv[arg_idx_value + i], &end_ptr, 0);
if (*end_ptr != '\0') {
shell_error(sh,
"Invalid channel value parameter %s",
argv[arg_idx_value + i]);
return -EINVAL;
}
if (val > 255) {
shell_error(sh,
"Invalid channel value %lu (max 255)", val);
return -EINVAL;
}
value[i] = val;
}
shell_fprintf(sh, SHELL_NORMAL, "%s: writing from channel %d: %d",
dev->name, start_channel, value[0]);
for (i = 1; i < num_channels; i++) {
shell_fprintf(sh, SHELL_NORMAL, " %d", value[i]);
}
shell_fprintf(sh, SHELL_NORMAL, "\n");
err = led_write_channels(dev, start_channel, num_channels, value);
if (err) {
shell_error(sh, "Error: %d", err);
}
return err;
}
static void device_name_get(size_t idx, struct shell_static_entry *entry)
{
const struct device *dev = shell_device_lookup(idx, NULL);
entry->syntax = (dev != NULL) ? dev->name : NULL;
entry->handler = NULL;
entry->help = NULL;
entry->subcmd = NULL;
}
SHELL_DYNAMIC_CMD_CREATE(dsub_device_name, device_name_get);
SHELL_STATIC_SUBCMD_SET_CREATE(
sub_led, SHELL_CMD_ARG(off, &dsub_device_name, "<device> <led>", cmd_off, 3, 0),
SHELL_CMD_ARG(on, &dsub_device_name, "<device> <led>", cmd_on, 3, 0),
SHELL_CMD_ARG(get_info, &dsub_device_name, "<device> <led>", cmd_get_info, 3, 0),
SHELL_CMD_ARG(set_brightness, &dsub_device_name, "<device> <led> <value [0-100]>",
cmd_set_brightness, 4, 0),
SHELL_CMD_ARG(set_color, &dsub_device_name,
"<device> <led> <color 0 [0-255]> ... <color N>", cmd_set_color, 4,
MAX_CHANNEL_ARGS - 1),
SHELL_CMD_ARG(set_channel, &dsub_device_name, "<device> <channel> <value [0-255]>",
cmd_set_channel, 4, 0),
SHELL_CMD_ARG(write_channels, &dsub_device_name,
"<device> <chan> <value 0 [0-255]> ... <value N>", cmd_write_channels, 4,
MAX_CHANNEL_ARGS - 1),
SHELL_SUBCMD_SET_END);
SHELL_CMD_REGISTER(led, &sub_led, "LED commands", NULL);
``` | /content/code_sandbox/drivers/led/led_shell.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 2,477 |
```unknown
config LED_NPM1300
bool "nPM1300 LED driver"
default y
depends on DT_HAS_NORDIC_NPM1300_LED_ENABLED
select I2C
select MFD
help
Enable the nPM1300 LED driver.
``` | /content/code_sandbox/drivers/led/Kconfig.npm1300 | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 57 |
```c
/*
*
*/
#define DT_DRV_COMPAT nxp_pca9633
/**
* @file
* @brief LED driver for the PCA9633 I2C LED driver (7-bit slave address 0x62)
*/
#include <zephyr/drivers/i2c.h>
#include <zephyr/drivers/led.h>
#include <zephyr/sys/util.h>
#include <zephyr/kernel.h>
#define LOG_LEVEL CONFIG_LED_LOG_LEVEL
#include <zephyr/logging/log.h>
LOG_MODULE_REGISTER(pca9633);
#include "led_context.h"
/* PCA9633 select registers determine the source that drives LED outputs */
#define PCA9633_LED_OFF 0x0 /* LED driver off */
#define PCA9633_LED_ON 0x1 /* LED driver on */
#define PCA9633_LED_PWM 0x2 /* Controlled through PWM */
#define PCA9633_LED_GRP_PWM 0x3 /* Controlled through PWM/GRPPWM */
/* PCA9633 control register */
#define PCA9633_MODE1 0x00
#define PCA9633_MODE2 0x01
#define PCA9633_PWM_BASE 0x02 /* Reg 0x02-0x05 for brightness control LED01-04 */
#define PCA9633_GRPPWM 0x06
#define PCA9633_GRPFREQ 0x07
#define PCA9633_LEDOUT 0x08
/* PCA9633 mode register 1 */
#define PCA9633_MODE1_ALLCAL 0x01 /* All Call Address enabled */
#define PCA9633_MODE1_SLEEP 0x10 /* Sleep Mode */
/* PCA9633 mode register 2 */
#define PCA9633_MODE2_DMBLNK 0x20 /* Enable blinking */
#define PCA9633_MASK 0x03
struct pca9633_config {
struct i2c_dt_spec i2c;
bool disable_allcall;
};
struct pca9633_data {
struct led_data dev_data;
};
static int pca9633_led_blink(const struct device *dev, uint32_t led,
uint32_t delay_on, uint32_t delay_off)
{
struct pca9633_data *data = dev->data;
const struct pca9633_config *config = dev->config;
struct led_data *dev_data = &data->dev_data;
uint8_t gdc, gfrq;
uint32_t period;
period = delay_on + delay_off;
if (period < dev_data->min_period || period > dev_data->max_period) {
return -EINVAL;
}
/*
* From manual:
* duty cycle = (GDC / 256) ->
* (time_on / period) = (GDC / 256) ->
* GDC = ((time_on * 256) / period)
*/
gdc = delay_on * 256U / period;
if (i2c_reg_write_byte_dt(&config->i2c,
PCA9633_GRPPWM,
gdc)) {
LOG_ERR("LED reg write failed");
return -EIO;
}
/*
* From manual:
* period = ((GFRQ + 1) / 24) in seconds.
* So, period (in ms) = (((GFRQ + 1) / 24) * 1000) ->
* GFRQ = ((period * 24 / 1000) - 1)
*/
gfrq = (period * 24U / 1000) - 1;
if (i2c_reg_write_byte_dt(&config->i2c,
PCA9633_GRPFREQ,
gfrq)) {
LOG_ERR("LED reg write failed");
return -EIO;
}
/* Enable blinking mode */
if (i2c_reg_update_byte_dt(&config->i2c,
PCA9633_MODE2,
PCA9633_MODE2_DMBLNK,
PCA9633_MODE2_DMBLNK)) {
LOG_ERR("LED reg update failed");
return -EIO;
}
/* Select the GRPPWM source to drive the LED output */
if (i2c_reg_update_byte_dt(&config->i2c,
PCA9633_LEDOUT,
PCA9633_MASK << (led << 1),
PCA9633_LED_GRP_PWM << (led << 1))) {
LOG_ERR("LED reg update failed");
return -EIO;
}
return 0;
}
static int pca9633_led_set_brightness(const struct device *dev, uint32_t led,
uint8_t value)
{
const struct pca9633_config *config = dev->config;
struct pca9633_data *data = dev->data;
struct led_data *dev_data = &data->dev_data;
uint8_t val;
if (value < dev_data->min_brightness ||
value > dev_data->max_brightness) {
return -EINVAL;
}
/* Set the LED brightness value */
val = (value * 255U) / dev_data->max_brightness;
if (i2c_reg_write_byte_dt(&config->i2c,
PCA9633_PWM_BASE + led,
val)) {
LOG_ERR("LED reg write failed");
return -EIO;
}
/* Set the LED driver to be controlled through its PWMx register. */
if (i2c_reg_update_byte_dt(&config->i2c,
PCA9633_LEDOUT,
PCA9633_MASK << (led << 1),
PCA9633_LED_PWM << (led << 1))) {
LOG_ERR("LED reg update failed");
return -EIO;
}
return 0;
}
static inline int pca9633_led_on(const struct device *dev, uint32_t led)
{
const struct pca9633_config *config = dev->config;
/* Set LED state to ON */
if (i2c_reg_update_byte_dt(&config->i2c,
PCA9633_LEDOUT,
PCA9633_MASK << (led << 1),
PCA9633_LED_ON << (led << 1))) {
LOG_ERR("LED reg update failed");
return -EIO;
}
return 0;
}
static inline int pca9633_led_off(const struct device *dev, uint32_t led)
{
const struct pca9633_config *config = dev->config;
/* Set LED state to OFF */
if (i2c_reg_update_byte_dt(&config->i2c,
PCA9633_LEDOUT,
PCA9633_MASK << (led << 1),
PCA9633_LED_OFF)) {
LOG_ERR("LED reg update failed");
return -EIO;
}
return 0;
}
static int pca9633_led_init(const struct device *dev)
{
const struct pca9633_config *config = dev->config;
struct pca9633_data *data = dev->data;
struct led_data *dev_data = &data->dev_data;
if (!device_is_ready(config->i2c.bus)) {
LOG_ERR("I2C bus is not ready");
return -ENODEV;
}
/*
* Take the LED driver out from Sleep mode and disable All Call Address
* if specified in DT.
*/
if (i2c_reg_update_byte_dt(
&config->i2c, PCA9633_MODE1,
config->disable_allcall ? PCA9633_MODE1_SLEEP | PCA9633_MODE1_ALLCAL
: PCA9633_MODE1_SLEEP,
config->disable_allcall ? ~(PCA9633_MODE1_SLEEP | PCA9633_MODE1_ALLCAL)
: ~PCA9633_MODE1_SLEEP)) {
LOG_ERR("LED reg update failed");
return -EIO;
}
/* Hardware specific limits */
dev_data->min_period = 41U;
dev_data->max_period = 10667U;
dev_data->min_brightness = 0U;
dev_data->max_brightness = 100U;
return 0;
}
static const struct led_driver_api pca9633_led_api = {
.blink = pca9633_led_blink,
.set_brightness = pca9633_led_set_brightness,
.on = pca9633_led_on,
.off = pca9633_led_off,
};
#define PCA9633_DEVICE(id) \
static const struct pca9633_config pca9633_##id##_cfg = { \
.i2c = I2C_DT_SPEC_INST_GET(id), \
.disable_allcall = DT_INST_PROP(id, disable_allcall), \
}; \
static struct pca9633_data pca9633_##id##_data; \
\
DEVICE_DT_INST_DEFINE(id, &pca9633_led_init, NULL, \
&pca9633_##id##_data, \
&pca9633_##id##_cfg, POST_KERNEL, \
CONFIG_LED_INIT_PRIORITY, \
&pca9633_led_api);
DT_INST_FOREACH_STATUS_OKAY(PCA9633_DEVICE)
``` | /content/code_sandbox/drivers/led/pca9633.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 1,934 |
```c
/*
*
*/
/**
* @file
* @brief LP50xx LED controller
*/
#include <errno.h>
#include <zephyr/device.h>
#include <zephyr/devicetree.h>
#include <zephyr/drivers/gpio.h>
#include <zephyr/drivers/i2c.h>
#include <zephyr/drivers/led.h>
#include <zephyr/drivers/led/lp50xx.h>
#include <zephyr/kernel.h>
#include <zephyr/pm/device.h>
#include <zephyr/sys/util.h>
#include <zephyr/logging/log.h>
LOG_MODULE_REGISTER(lp50xx, CONFIG_LED_LOG_LEVEL);
#define LP50XX_MAX_BRIGHTNESS 100U
/*
* Number of supported RGB led modules per chipset.
*
* For each module, there are 4 associated registers:
* - 1 brightness register
* - 3 color registers (RGB)
*
* A chipset can have more modules than leds. In this case, the
* associated registers will simply be inactive.
*/
#define LP5012_NUM_MODULES 4
#define LP5024_NUM_MODULES 8
#define LP5036_NUM_MODULES 12
/* Maximum number of channels */
#define LP50XX_MAX_CHANNELS(nmodules) \
((LP50XX_COLORS_PER_LED + 1) * ((nmodules) + 1))
#define LP50XX_DISABLE_DELAY_US 3
#define LP50XX_ENABLE_DELAY_US 500
/* Base registers */
#define LP50XX_DEVICE_CONFIG0 0x00
#define LP50XX_DEVICE_CONFIG1 0x01
#define LP50XX_LED_CONFIG0 0x02
#define LP50XX_BANK_BASE(nmodules) \
(0x03 + (((nmodules) - 1) / 8))
#define LP50XX_LED0_BRIGHTNESS(nmodules) \
((LP50XX_BANK_BASE(nmodules)) + 4)
#define LP50XX_OUT0_COLOR(nmodules) \
(LP50XX_LED0_BRIGHTNESS(nmodules) + (nmodules))
#define LP50XX_RESET(nmodules) \
(LP50XX_OUT0_COLOR(nmodules) + LP50XX_COLORS_PER_LED * (nmodules))
/* Register values */
#define CONFIG0_CHIP_EN BIT(6)
#define CONFIG1_LED_GLOBAL_OFF BIT(0)
#define CONFIG1_MAX_CURRENT_OPT BIT(1)
#define CONFIG1_PWM_DITHERING_EN BIT(2)
#define CONFIG1_AUTO_INCR_EN BIT(3)
#define CONFIG1_POWER_SAVE_EN BIT(4)
#define CONFIG1_LOG_SCALE_EN BIT(5)
#define RESET_SW 0xFF
struct lp50xx_config {
struct i2c_dt_spec bus;
const struct gpio_dt_spec gpio_enable;
uint8_t num_modules;
uint8_t max_leds;
uint8_t num_leds;
bool log_scale_en;
bool max_curr_opt;
const struct led_info *leds_info;
};
struct lp50xx_data {
uint8_t *chan_buf;
};
static const struct led_info *lp50xx_led_to_info(
const struct lp50xx_config *config, uint32_t led)
{
if (led < config->num_leds) {
return &config->leds_info[led];
}
return NULL;
}
static int lp50xx_get_info(const struct device *dev, uint32_t led,
const struct led_info **info)
{
const struct lp50xx_config *config = dev->config;
const struct led_info *led_info = lp50xx_led_to_info(config, led);
if (!led_info) {
return -EINVAL;
}
*info = led_info;
return 0;
}
static int lp50xx_set_brightness(const struct device *dev,
uint32_t led, uint8_t value)
{
const struct lp50xx_config *config = dev->config;
const struct led_info *led_info = lp50xx_led_to_info(config, led);
uint8_t buf[2];
if (!led_info) {
return -ENODEV;
}
if (value > LP50XX_MAX_BRIGHTNESS) {
LOG_ERR("%s: brightness value out of bounds: val=%d, max=%d",
dev->name, value, LP50XX_MAX_BRIGHTNESS);
return -EINVAL;
}
buf[0] = LP50XX_LED0_BRIGHTNESS(config->num_modules) + led_info->index;
buf[1] = (value * 0xff) / 100;
return i2c_write_dt(&config->bus, buf, sizeof(buf));
}
static int lp50xx_on(const struct device *dev, uint32_t led)
{
return lp50xx_set_brightness(dev, led, 100);
}
static int lp50xx_off(const struct device *dev, uint32_t led)
{
return lp50xx_set_brightness(dev, led, 0);
}
static int lp50xx_set_color(const struct device *dev, uint32_t led,
uint8_t num_colors, const uint8_t *color)
{
const struct lp50xx_config *config = dev->config;
const struct led_info *led_info = lp50xx_led_to_info(config, led);
uint8_t buf[4];
if (!led_info) {
return -ENODEV;
}
if (num_colors != led_info->num_colors) {
LOG_ERR("%s: invalid number of colors: got=%d, expected=%d",
dev->name,
num_colors,
led_info->num_colors);
return -EINVAL;
}
buf[0] = LP50XX_OUT0_COLOR(config->num_modules);
buf[0] += LP50XX_COLORS_PER_LED * led_info->index;
buf[1] = color[0];
buf[2] = color[1];
buf[3] = color[2];
return i2c_write_dt(&config->bus, buf, sizeof(buf));
}
static int lp50xx_write_channels(const struct device *dev,
uint32_t start_channel,
uint32_t num_channels, const uint8_t *buf)
{
const struct lp50xx_config *config = dev->config;
struct lp50xx_data *data = dev->data;
uint8_t base_channel, end_channel, max_channels;
base_channel = LP50XX_BANK_BASE(config->num_modules);
end_channel = base_channel + start_channel + num_channels;
max_channels = base_channel + LP50XX_MAX_CHANNELS(config->num_modules);
if (end_channel > max_channels) {
return -EINVAL;
}
/*
* Unfortunately this controller doesn't support commands split into
* two I2C messages.
*/
data->chan_buf[0] = base_channel + start_channel;
memcpy(data->chan_buf + 1, buf, num_channels);
return i2c_write_dt(&config->bus, data->chan_buf, num_channels + 1);
}
static int lp50xx_reset(const struct device *dev)
{
const struct lp50xx_config *config = dev->config;
uint8_t buf[2];
int err;
/* Software reset */
buf[0] = LP50XX_RESET(config->num_modules);
buf[1] = RESET_SW;
err = i2c_write_dt(&config->bus, buf, 2);
if (err < 0) {
return err;
}
/* After reset, apply configuration since all registers are reset. */
buf[0] = LP50XX_DEVICE_CONFIG1;
buf[1] = CONFIG1_PWM_DITHERING_EN | CONFIG1_AUTO_INCR_EN
| CONFIG1_POWER_SAVE_EN;
if (config->max_curr_opt) {
buf[1] |= CONFIG1_MAX_CURRENT_OPT;
}
if (config->log_scale_en) {
buf[1] |= CONFIG1_LOG_SCALE_EN;
}
return i2c_write_dt(&config->bus, buf, 2);
}
static int lp50xx_hw_enable(const struct device *dev, bool enable)
{
const struct lp50xx_config *config = dev->config;
int err;
if (config->gpio_enable.port == NULL) {
/* Nothing to do */
return 0;
}
err = gpio_pin_set_dt(&config->gpio_enable, enable);
if (err < 0) {
LOG_ERR("%s: failed to set enable gpio", dev->name);
return err;
}
k_usleep(enable ? LP50XX_ENABLE_DELAY_US : LP50XX_DISABLE_DELAY_US);
return 0;
}
static int lp50xx_enable(const struct device *dev, bool enable)
{
const struct lp50xx_config *config = dev->config;
uint8_t value = enable ? CONFIG0_CHIP_EN : 0;
return i2c_reg_update_byte_dt(&config->bus,
LP50XX_DEVICE_CONFIG0,
CONFIG0_CHIP_EN,
value);
}
static int lp50xx_init(const struct device *dev)
{
const struct lp50xx_config *config = dev->config;
int err;
if (!i2c_is_ready_dt(&config->bus)) {
LOG_ERR("%s: I2C device not ready", dev->name);
return -ENODEV;
}
if (config->num_leds > config->max_leds) {
LOG_ERR("%s: invalid number of LEDs %d (max %d)",
dev->name,
config->num_leds,
config->max_leds);
return -EINVAL;
}
/* Configure GPIO if present */
if (config->gpio_enable.port != NULL) {
if (!gpio_is_ready_dt(&config->gpio_enable)) {
LOG_ERR("%s: enable gpio is not ready", dev->name);
return -ENODEV;
}
err = gpio_pin_configure_dt(&config->gpio_enable,
GPIO_OUTPUT_INACTIVE);
if (err < 0) {
LOG_ERR("%s: failed to initialize enable gpio",
dev->name);
return err;
}
}
/* Enable hardware */
err = lp50xx_hw_enable(dev, true);
if (err < 0) {
LOG_ERR("%s: failed to enable hardware", dev->name);
return err;
}
/* Reset device */
err = lp50xx_reset(dev);
if (err < 0) {
LOG_ERR("%s: failed to reset", dev->name);
return err;
}
/* Enable device */
err = lp50xx_enable(dev, true);
if (err < 0) {
LOG_ERR("%s: failed to enable", dev->name);
return err;
}
return 0;
}
#ifdef CONFIG_PM_DEVICE
static int lp50xx_pm_action(const struct device *dev,
enum pm_device_action action)
{
switch (action) {
case PM_DEVICE_ACTION_SUSPEND:
return lp50xx_enable(dev, false);
case PM_DEVICE_ACTION_RESUME:
return lp50xx_enable(dev, true);
default:
return -ENOTSUP;
}
return 0;
}
#endif /* CONFIG_PM_DEVICE */
static const struct led_driver_api lp50xx_led_api = {
.on = lp50xx_on,
.off = lp50xx_off,
.get_info = lp50xx_get_info,
.set_brightness = lp50xx_set_brightness,
.set_color = lp50xx_set_color,
.write_channels = lp50xx_write_channels,
};
#define COLOR_MAPPING(led_node_id) \
const uint8_t color_mapping_##led_node_id[] = \
DT_PROP(led_node_id, color_mapping);
#define LED_INFO(led_node_id) \
{ \
.label = DT_PROP(led_node_id, label), \
.index = DT_PROP(led_node_id, index), \
.num_colors = \
DT_PROP_LEN(led_node_id, color_mapping), \
.color_mapping = color_mapping_##led_node_id, \
},
#define LP50XX_DEVICE(n, id, nmodules) \
DT_INST_FOREACH_CHILD(n, COLOR_MAPPING) \
\
static const struct led_info lp##id##_leds_##n[] = { \
DT_INST_FOREACH_CHILD(n, LED_INFO) \
}; \
\
static const struct lp50xx_config lp##id##_config_##n = { \
.bus = I2C_DT_SPEC_INST_GET(n), \
.gpio_enable = \
GPIO_DT_SPEC_INST_GET_OR(n, enable_gpios, {0}), \
.num_modules = nmodules, \
.max_leds = LP##id##_MAX_LEDS, \
.num_leds = ARRAY_SIZE(lp##id##_leds_##n), \
.log_scale_en = DT_INST_PROP(n, log_scale_en), \
.max_curr_opt = DT_INST_PROP(n, max_curr_opt), \
.leds_info = lp##id##_leds_##n, \
}; \
\
static uint8_t lp##id##_chan_buf_##n[LP50XX_MAX_CHANNELS(nmodules) + 1];\
\
static struct lp50xx_data lp##id##_data_##n = { \
.chan_buf = lp##id##_chan_buf_##n, \
}; \
\
PM_DEVICE_DT_INST_DEFINE(n, lp50xx_pm_action); \
\
DEVICE_DT_INST_DEFINE(n, \
lp50xx_init, \
PM_DEVICE_DT_INST_GET(n), \
&lp##id##_data_##n, \
&lp##id##_config_##n, \
POST_KERNEL, CONFIG_LED_INIT_PRIORITY, \
&lp50xx_led_api);
#undef DT_DRV_COMPAT
#define DT_DRV_COMPAT ti_lp5009
DT_INST_FOREACH_STATUS_OKAY_VARGS(LP50XX_DEVICE, 5009, LP5012_NUM_MODULES)
#undef DT_DRV_COMPAT
#define DT_DRV_COMPAT ti_lp5012
DT_INST_FOREACH_STATUS_OKAY_VARGS(LP50XX_DEVICE, 5012, LP5012_NUM_MODULES)
#undef DT_DRV_COMPAT
#define DT_DRV_COMPAT ti_lp5018
DT_INST_FOREACH_STATUS_OKAY_VARGS(LP50XX_DEVICE, 5018, LP5024_NUM_MODULES)
#undef DT_DRV_COMPAT
#define DT_DRV_COMPAT ti_lp5024
DT_INST_FOREACH_STATUS_OKAY_VARGS(LP50XX_DEVICE, 5024, LP5024_NUM_MODULES)
#undef DT_DRV_COMPAT
#define DT_DRV_COMPAT ti_lp5030
DT_INST_FOREACH_STATUS_OKAY_VARGS(LP50XX_DEVICE, 5030, LP5036_NUM_MODULES)
#undef DT_DRV_COMPAT
#define DT_DRV_COMPAT ti_lp5036
DT_INST_FOREACH_STATUS_OKAY_VARGS(LP50XX_DEVICE, 5036, LP5036_NUM_MODULES)
``` | /content/code_sandbox/drivers/led/lp50xx.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 3,182 |
```unknown
config PCA9633
bool "PCA9633 LED driver"
default y
depends on DT_HAS_NXP_PCA9633_ENABLED
select I2C
help
Enable LED driver for PCA9633.
PCA9633 LED driver has 4 channels each with multi-programmable
states. Each channel can drive up to 25 mA per LED.
``` | /content/code_sandbox/drivers/led/Kconfig.pca9633 | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 79 |
```c
/*
*
*/
#define DT_DRV_COMPAT ti_tlc59108
/**
* @file
* @brief LED driver for the TLC59108 I2C LED driver
*/
#include <zephyr/drivers/i2c.h>
#include <zephyr/drivers/led.h>
#include <zephyr/sys/util.h>
#include <zephyr/kernel.h>
#include <zephyr/logging/log.h>
LOG_MODULE_REGISTER(tlc59108, CONFIG_LED_LOG_LEVEL);
#include "led_context.h"
/* TLC59108 max supported LED id */
#define TLC59108_MAX_LED 7
/* TLC59108 select registers determine the source that drives LED outputs */
#define TLC59108_LED_OFF 0x0 /* LED driver off */
#define TLC59108_LED_ON 0x1 /* LED driver on */
#define TLC59108_LED_PWM 0x2 /* Controlled through PWM */
#define TLC59108_LED_GRP_PWM 0x3 /* Controlled through PWM/GRPPWM */
/* TLC59108 control register */
#define TLC59108_MODE1 0x00
#define TLC59108_MODE2 0x01
#define TLC59108_PWM_BASE 0x02
#define TLC59108_GRPPWM 0x0A
#define TLC59108_GRPFREQ 0x0B
#define TLC59108_LEDOUT0 0x0C
#define TLC59108_LEDOUT1 0x0D
/* TLC59108 mode register 1 */
#define TLC59108_MODE1_OSC 0x10
/* TLC59108 mode register 2 */
#define TLC59108_MODE2_DMBLNK 0x20 /* Enable blinking */
#define TLC59108_MASK 0x03
struct tlc59108_cfg {
struct i2c_dt_spec i2c;
};
struct tlc59108_data {
struct led_data dev_data;
};
static int tlc59108_set_ledout(const struct device *dev, uint32_t led,
uint8_t val)
{
const struct tlc59108_cfg *config = dev->config;
if (led < 4) {
if (i2c_reg_update_byte_dt(&config->i2c, TLC59108_LEDOUT0,
TLC59108_MASK << (led << 1), val << (led << 1))) {
LOG_ERR("LED reg 0x%x update failed", TLC59108_LEDOUT0);
return -EIO;
}
} else {
if (i2c_reg_update_byte_dt(&config->i2c, TLC59108_LEDOUT1,
TLC59108_MASK << ((led - 4) << 1),
val << ((led - 4) << 1))) {
LOG_ERR("LED reg 0x%x update failed", TLC59108_LEDOUT1);
return -EIO;
}
}
return 0;
}
static int tlc59108_led_blink(const struct device *dev, uint32_t led,
uint32_t delay_on, uint32_t delay_off)
{
const struct tlc59108_cfg *config = dev->config;
struct tlc59108_data *data = dev->data;
struct led_data *dev_data = &data->dev_data;
uint8_t gdc, gfrq;
uint32_t period;
period = delay_on + delay_off;
if (led > TLC59108_MAX_LED) {
return -EINVAL;
}
if (period < dev_data->min_period || period > dev_data->max_period) {
return -EINVAL;
}
/*
* From manual:
* duty cycle = (GDC / 256) ->
* (time_on / period) = (GDC / 256) ->
* GDC = ((time_on * 256) / period)
*/
gdc = delay_on * 256U / period;
if (i2c_reg_write_byte_dt(&config->i2c, TLC59108_GRPPWM, gdc)) {
LOG_ERR("LED reg 0x%x write failed", TLC59108_GRPPWM);
return -EIO;
}
/*
* From manual:
* period = ((GFRQ + 1) / 24) in seconds.
* So, period (in ms) = (((GFRQ + 1) / 24) * 1000) ->
* GFRQ = ((period * 24 / 1000) - 1)
*/
gfrq = (period * 24U / 1000) - 1;
if (i2c_reg_write_byte_dt(&config->i2c, TLC59108_GRPFREQ, gfrq)) {
LOG_ERR("LED reg 0x%x write failed", TLC59108_GRPFREQ);
return -EIO;
}
/* Enable blinking mode */
if (i2c_reg_update_byte_dt(&config->i2c, TLC59108_MODE2, TLC59108_MODE2_DMBLNK,
TLC59108_MODE2_DMBLNK)) {
LOG_ERR("LED reg 0x%x update failed", TLC59108_MODE2);
return -EIO;
}
/* Select the GRPPWM source to drive the LED output */
return tlc59108_set_ledout(dev, led, TLC59108_LED_GRP_PWM);
}
static int tlc59108_led_set_brightness(const struct device *dev, uint32_t led,
uint8_t value)
{
const struct tlc59108_cfg *config = dev->config;
struct tlc59108_data *data = dev->data;
struct led_data *dev_data = &data->dev_data;
uint8_t val;
if (led > TLC59108_MAX_LED) {
return -EINVAL;
}
if (value < dev_data->min_brightness ||
value > dev_data->max_brightness) {
return -EINVAL;
}
/* Set the LED brightness value */
val = (value * 255U) / dev_data->max_brightness;
if (i2c_reg_write_byte_dt(&config->i2c, TLC59108_PWM_BASE + led, val)) {
LOG_ERR("LED 0x%x reg write failed", TLC59108_PWM_BASE + led);
return -EIO;
}
/* Set the LED driver to be controlled through its PWMx register. */
return tlc59108_set_ledout(dev, led, TLC59108_LED_PWM);
}
static inline int tlc59108_led_on(const struct device *dev, uint32_t led)
{
if (led > TLC59108_MAX_LED) {
return -EINVAL;
}
/* Set LED state to ON */
return tlc59108_set_ledout(dev, led, TLC59108_LED_ON);
}
static inline int tlc59108_led_off(const struct device *dev, uint32_t led)
{
if (led > TLC59108_MAX_LED) {
return -EINVAL;
}
/* Set LED state to OFF */
return tlc59108_set_ledout(dev, led, TLC59108_LED_OFF);
}
static int tlc59108_led_init(const struct device *dev)
{
const struct tlc59108_cfg *config = dev->config;
struct tlc59108_data *data = dev->data;
struct led_data *dev_data = &data->dev_data;
if (!device_is_ready(config->i2c.bus)) {
LOG_ERR("I2C bus device %s is not ready", config->i2c.bus->name);
return -ENODEV;
}
/* Wake up from sleep mode */
if (i2c_reg_update_byte_dt(&config->i2c, TLC59108_MODE1, TLC59108_MODE1_OSC, 0)) {
LOG_ERR("LED reg 0x%x update failed", TLC59108_MODE1);
return -EIO;
}
/* Hardware specific limits */
dev_data->min_period = 41U;
dev_data->max_period = 10730U;
dev_data->min_brightness = 0U;
dev_data->max_brightness = 100U;
return 0;
}
static const struct led_driver_api tlc59108_led_api = {
.blink = tlc59108_led_blink,
.set_brightness = tlc59108_led_set_brightness,
.on = tlc59108_led_on,
.off = tlc59108_led_off,
};
#define TLC59108_DEVICE(id) \
static const struct tlc59108_cfg tlc59108_##id##_cfg = { \
.i2c = I2C_DT_SPEC_INST_GET(id), \
}; \
static struct tlc59108_data tlc59108_##id##_data; \
\
DEVICE_DT_INST_DEFINE(id, &tlc59108_led_init, NULL, \
&tlc59108_##id##_data, \
&tlc59108_##id##_cfg, POST_KERNEL, \
CONFIG_LED_INIT_PRIORITY, \
&tlc59108_led_api);
DT_INST_FOREACH_STATUS_OKAY(TLC59108_DEVICE)
``` | /content/code_sandbox/drivers/led/tlc59108.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 1,947 |
```c
/*
*
*/
#define DT_DRV_COMPAT analog_axis
#include <stdlib.h>
#include <zephyr/device.h>
#include <zephyr/drivers/adc.h>
#include <zephyr/input/input.h>
#include <zephyr/input/input_analog_axis.h>
#include <zephyr/kernel.h>
#include <zephyr/logging/log.h>
#include <zephyr/pm/device.h>
#include <zephyr/pm/device_runtime.h>
#include <zephyr/sys/atomic.h>
#include <zephyr/sys/util.h>
LOG_MODULE_REGISTER(analog_axis, CONFIG_INPUT_LOG_LEVEL);
struct analog_axis_channel_config {
struct adc_dt_spec adc;
int16_t out_min;
int16_t out_max;
uint16_t axis;
bool invert_input;
bool invert_output;
};
struct analog_axis_channel_data {
int last_out;
};
struct analog_axis_config {
uint32_t poll_period_ms;
const struct analog_axis_channel_config *channel_cfg;
struct analog_axis_channel_data *channel_data;
struct analog_axis_calibration *calibration;
const uint8_t num_channels;
};
struct analog_axis_data {
struct k_sem cal_lock;
analog_axis_raw_data_t raw_data_cb;
struct k_timer timer;
struct k_thread thread;
K_KERNEL_STACK_MEMBER(thread_stack,
CONFIG_INPUT_ANALOG_AXIS_THREAD_STACK_SIZE);
#ifdef CONFIG_PM_DEVICE
atomic_t suspended;
struct k_sem wakeup;
#endif
};
int analog_axis_num_axes(const struct device *dev)
{
const struct analog_axis_config *cfg = dev->config;
return cfg->num_channels;
}
int analog_axis_calibration_get(const struct device *dev,
int channel,
struct analog_axis_calibration *out_cal)
{
const struct analog_axis_config *cfg = dev->config;
struct analog_axis_data *data = dev->data;
struct analog_axis_calibration *cal = &cfg->calibration[channel];
if (channel >= cfg->num_channels) {
return -EINVAL;
}
k_sem_take(&data->cal_lock, K_FOREVER);
memcpy(out_cal, cal, sizeof(struct analog_axis_calibration));
k_sem_give(&data->cal_lock);
return 0;
}
void analog_axis_set_raw_data_cb(const struct device *dev, analog_axis_raw_data_t cb)
{
struct analog_axis_data *data = dev->data;
k_sem_take(&data->cal_lock, K_FOREVER);
data->raw_data_cb = cb;
k_sem_give(&data->cal_lock);
}
int analog_axis_calibration_set(const struct device *dev,
int channel,
struct analog_axis_calibration *new_cal)
{
const struct analog_axis_config *cfg = dev->config;
struct analog_axis_data *data = dev->data;
struct analog_axis_calibration *cal = &cfg->calibration[channel];
if (channel >= cfg->num_channels) {
return -EINVAL;
}
k_sem_take(&data->cal_lock, K_FOREVER);
memcpy(cal, new_cal, sizeof(struct analog_axis_calibration));
k_sem_give(&data->cal_lock);
return 0;
}
static int32_t analog_axis_out_deadzone(const struct device *dev,
int channel,
int32_t raw_val)
{
const struct analog_axis_config *cfg = dev->config;
const struct analog_axis_channel_config *axis_cfg = &cfg->channel_cfg[channel];
struct analog_axis_calibration *cal = &cfg->calibration[channel];
int16_t in_range = cal->in_max - cal->in_min;
int16_t out_range = axis_cfg->out_max - axis_cfg->out_min;
int16_t in_mid = DIV_ROUND_CLOSEST(cal->in_min + cal->in_max, 2);
int16_t in_min = cal->in_min;
if (abs(raw_val - in_mid) < cal->in_deadzone) {
return DIV_ROUND_CLOSEST(axis_cfg->out_max + axis_cfg->out_min, 2);
}
in_range -= cal->in_deadzone * 2;
in_min += cal->in_deadzone;
if (raw_val < in_mid) {
raw_val += cal->in_deadzone;
} else {
raw_val -= cal->in_deadzone;
}
return DIV_ROUND_CLOSEST((raw_val - in_min) * out_range, in_range) + axis_cfg->out_min;
}
static int32_t analog_axis_out_linear(const struct device *dev,
int channel,
int32_t raw_val)
{
const struct analog_axis_config *cfg = dev->config;
const struct analog_axis_channel_config *axis_cfg = &cfg->channel_cfg[channel];
struct analog_axis_calibration *cal = &cfg->calibration[channel];
int16_t in_range = cal->in_max - cal->in_min;
int16_t out_range = axis_cfg->out_max - axis_cfg->out_min;
return DIV_ROUND_CLOSEST((raw_val - cal->in_min) * out_range, in_range) + axis_cfg->out_min;
}
static void analog_axis_loop(const struct device *dev)
{
const struct analog_axis_config *cfg = dev->config;
struct analog_axis_data *data = dev->data;
int16_t bufs[cfg->num_channels];
int32_t out;
struct adc_sequence sequence = {
.buffer = bufs,
.buffer_size = sizeof(bufs),
};
const struct analog_axis_channel_config *axis_cfg_0 = &cfg->channel_cfg[0];
int err;
int i;
adc_sequence_init_dt(&axis_cfg_0->adc, &sequence);
for (i = 0; i < cfg->num_channels; i++) {
const struct analog_axis_channel_config *axis_cfg = &cfg->channel_cfg[i];
sequence.channels |= BIT(axis_cfg->adc.channel_id);
}
err = adc_read(axis_cfg_0->adc.dev, &sequence);
if (err < 0) {
LOG_ERR("Could not read (%d)", err);
return;
}
k_sem_take(&data->cal_lock, K_FOREVER);
for (i = 0; i < cfg->num_channels; i++) {
const struct analog_axis_channel_config *axis_cfg = &cfg->channel_cfg[i];
struct analog_axis_channel_data *axis_data = &cfg->channel_data[i];
struct analog_axis_calibration *cal = &cfg->calibration[i];
int32_t raw_val = bufs[i];
if (axis_cfg->invert_input) {
raw_val *= -1;
}
if (data->raw_data_cb != NULL) {
data->raw_data_cb(dev, i, raw_val);
}
LOG_DBG("%s: ch %d: raw_val: %d", dev->name, i, raw_val);
if (cal->in_deadzone > 0) {
out = analog_axis_out_deadzone(dev, i, raw_val);
} else {
out = analog_axis_out_linear(dev, i, raw_val);
}
out = CLAMP(out, axis_cfg->out_min, axis_cfg->out_max);
if (axis_cfg->invert_output) {
out = axis_cfg->out_max - out;
}
if (axis_data->last_out != out) {
input_report_abs(dev, axis_cfg->axis, out, true, K_FOREVER);
}
axis_data->last_out = out;
}
k_sem_give(&data->cal_lock);
}
static void analog_axis_thread(void *arg1, void *arg2, void *arg3)
{
const struct device *dev = arg1;
const struct analog_axis_config *cfg = dev->config;
struct analog_axis_data *data = dev->data;
int err;
int i;
for (i = 0; i < cfg->num_channels; i++) {
const struct analog_axis_channel_config *axis_cfg = &cfg->channel_cfg[i];
if (!adc_is_ready_dt(&axis_cfg->adc)) {
LOG_ERR("ADC controller device not ready");
return;
}
err = adc_channel_setup_dt(&axis_cfg->adc);
if (err < 0) {
LOG_ERR("Could not setup channel #%d (%d)", i, err);
return;
}
}
while (true) {
#ifdef CONFIG_PM_DEVICE
if (atomic_get(&data->suspended) == 1) {
k_sem_take(&data->wakeup, K_FOREVER);
}
#endif
analog_axis_loop(dev);
k_timer_status_sync(&data->timer);
}
}
static int analog_axis_init(const struct device *dev)
{
struct analog_axis_data *data = dev->data;
k_tid_t tid;
k_sem_init(&data->cal_lock, 1, 1);
k_timer_init(&data->timer, NULL, NULL);
#ifdef CONFIG_PM_DEVICE
k_sem_init(&data->wakeup, 0, 1);
#endif
tid = k_thread_create(&data->thread, data->thread_stack,
K_KERNEL_STACK_SIZEOF(data->thread_stack),
analog_axis_thread, (void *)dev, NULL, NULL,
CONFIG_INPUT_ANALOG_AXIS_THREAD_PRIORITY,
0, K_NO_WAIT);
if (!tid) {
LOG_ERR("thread creation failed");
return -ENODEV;
}
k_thread_name_set(&data->thread, dev->name);
#ifndef CONFIG_PM_DEVICE_RUNTIME
const struct analog_axis_config *cfg = dev->config;
k_timer_start(&data->timer,
K_MSEC(cfg->poll_period_ms), K_MSEC(cfg->poll_period_ms));
#else
int ret;
atomic_set(&data->suspended, 1);
pm_device_init_suspended(dev);
ret = pm_device_runtime_enable(dev);
if (ret < 0) {
LOG_ERR("Failed to enable runtime power management");
return ret;
}
#endif
return 0;
}
#ifdef CONFIG_PM_DEVICE
static int analog_axis_pm_action(const struct device *dev,
enum pm_device_action action)
{
const struct analog_axis_config *cfg = dev->config;
struct analog_axis_data *data = dev->data;
switch (action) {
case PM_DEVICE_ACTION_SUSPEND:
atomic_set(&data->suspended, 1);
k_timer_stop(&data->timer);
break;
case PM_DEVICE_ACTION_RESUME:
k_timer_start(&data->timer,
K_MSEC(cfg->poll_period_ms),
K_MSEC(cfg->poll_period_ms));
atomic_set(&data->suspended, 0);
k_sem_give(&data->wakeup);
break;
default:
return -ENOTSUP;
}
return 0;
}
#endif
#define ANALOG_AXIS_CHANNEL_CFG_DEF(node_id) \
{ \
.adc = ADC_DT_SPEC_GET(node_id), \
.out_min = (int16_t)DT_PROP(node_id, out_min), \
.out_max = (int16_t)DT_PROP(node_id, out_max), \
.axis = DT_PROP(node_id, zephyr_axis), \
.invert_input = DT_PROP(node_id, invert_input), \
.invert_output = DT_PROP(node_id, invert_output), \
}
#define ANALOG_AXIS_CHANNEL_CAL_DEF(node_id) \
{ \
.in_min = (int16_t)DT_PROP(node_id, in_min), \
.in_max = (int16_t)DT_PROP(node_id, in_max), \
.in_deadzone = DT_PROP(node_id, in_deadzone), \
}
#define ANALOG_AXIS_INIT(inst) \
static const struct analog_axis_channel_config analog_axis_channel_cfg_##inst[] = { \
DT_INST_FOREACH_CHILD_STATUS_OKAY_SEP(inst, ANALOG_AXIS_CHANNEL_CFG_DEF, (,)) \
}; \
\
static struct analog_axis_channel_data \
analog_axis_channel_data_##inst[ARRAY_SIZE(analog_axis_channel_cfg_##inst)]; \
\
static struct analog_axis_calibration \
analog_axis_calibration_##inst[ARRAY_SIZE(analog_axis_channel_cfg_##inst)] = { \
DT_INST_FOREACH_CHILD_STATUS_OKAY_SEP( \
inst, ANALOG_AXIS_CHANNEL_CAL_DEF, (,)) \
}; \
\
static const struct analog_axis_config analog_axis_cfg_##inst = { \
.poll_period_ms = DT_INST_PROP(inst, poll_period_ms), \
.channel_cfg = analog_axis_channel_cfg_##inst, \
.channel_data = analog_axis_channel_data_##inst, \
.calibration = analog_axis_calibration_##inst, \
.num_channels = ARRAY_SIZE(analog_axis_channel_cfg_##inst), \
}; \
\
static struct analog_axis_data analog_axis_data_##inst; \
\
PM_DEVICE_DT_INST_DEFINE(inst, analog_axis_pm_action); \
\
DEVICE_DT_INST_DEFINE(inst, analog_axis_init, PM_DEVICE_DT_INST_GET(inst), \
&analog_axis_data_##inst, &analog_axis_cfg_##inst, \
POST_KERNEL, CONFIG_INPUT_INIT_PRIORITY, NULL);
DT_INST_FOREACH_STATUS_OKAY(ANALOG_AXIS_INIT)
``` | /content/code_sandbox/drivers/input/input_analog_axis.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 2,756 |
```c
/*
*
*/
#define DT_DRV_COMPAT xptek_xpt2046
#include <zephyr/drivers/spi.h>
#include <zephyr/input/input.h>
#include <zephyr/kernel.h>
#include <zephyr/logging/log.h>
LOG_MODULE_REGISTER(xpt2046, CONFIG_INPUT_LOG_LEVEL);
struct xpt2046_config {
const struct spi_dt_spec bus;
const struct gpio_dt_spec int_gpio;
uint16_t min_x;
uint16_t min_y;
uint16_t max_x;
uint16_t max_y;
uint16_t threshold;
uint16_t screen_size_x;
uint16_t screen_size_y;
uint16_t reads;
};
struct xpt2046_data {
const struct device *dev;
struct gpio_callback int_gpio_cb;
struct k_work work;
struct k_work_delayable dwork;
uint8_t rbuf[9];
uint32_t last_x;
uint32_t last_y;
bool pressed;
};
enum xpt2046_channel {
CH_TEMP0 = 0,
CH_Y,
CH_VBAT,
CH_Z1,
CH_Z2,
CH_X,
CH_AUXIN,
CH_TEMP1
};
struct measurement {
uint32_t x;
uint32_t y;
uint32_t z;
};
#define START BIT(7)
#define CHANNEL(ch) ((ch & 0x7) << 4)
#define MODE_8_BIT BIT(3)
#define SINGLE_ENDED BIT(2)
#define POWER_OFF 0
#define POWER_ON 0x03
#define CONVERT_U16(buf, idx) ((uint16_t)((buf[idx] & 0x7f) << 5) | (buf[idx + 1] >> 3))
/* Read all Z1, X, Y, Z2 channels using 16 Clocks-per-Conversion mode.
* See the manual path_to_url for details.
* Each follow-up command interleaves with previous conversion.
* So first command starts at byte 0. Second command starts at byte 2.
*/
static uint8_t tbuf[9] = {
[0] = START | CHANNEL(CH_Z1) | POWER_ON,
[2] = START | CHANNEL(CH_Z2) | POWER_ON,
[4] = START | CHANNEL(CH_X) | POWER_ON,
[6] = START | CHANNEL(CH_Y) | POWER_OFF,
};
static void xpt2046_isr_handler(const struct device *dev, struct gpio_callback *cb, uint32_t pins)
{
struct xpt2046_data *data = CONTAINER_OF(cb, struct xpt2046_data, int_gpio_cb);
const struct xpt2046_config *config = data->dev->config;
gpio_remove_callback(config->int_gpio.port, &data->int_gpio_cb);
k_work_submit(&data->work);
}
static int xpt2046_read_and_cumulate(const struct spi_dt_spec *bus, const struct spi_buf_set *tx,
const struct spi_buf_set *rx, struct measurement *meas)
{
int ret = spi_transceive_dt(bus, tx, rx);
if (ret < 0) {
LOG_ERR("spi_transceive() %d\n", ret);
return ret;
}
uint8_t *buf = rx->buffers->buf;
meas->z += CONVERT_U16(buf, 1) + 4096 - CONVERT_U16(buf, 3);
meas->x += CONVERT_U16(buf, 5);
meas->y += CONVERT_U16(buf, 7);
return 0;
}
static void xpt2046_release_handler(struct k_work *kw)
{
struct k_work_delayable *dw = k_work_delayable_from_work(kw);
struct xpt2046_data *data = CONTAINER_OF(dw, struct xpt2046_data, dwork);
struct xpt2046_config *config = (struct xpt2046_config *)data->dev->config;
if (!data->pressed) {
return;
}
/* Check if touch is still pressed */
if (gpio_pin_get_dt(&config->int_gpio) == 0) {
data->pressed = false;
input_report_key(data->dev, INPUT_BTN_TOUCH, 0, true, K_FOREVER);
} else {
/* Re-check later */
k_work_reschedule(&data->dwork, K_MSEC(10));
}
}
static void xpt2046_work_handler(struct k_work *kw)
{
struct xpt2046_data *data = CONTAINER_OF(kw, struct xpt2046_data, work);
struct xpt2046_config *config = (struct xpt2046_config *)data->dev->config;
int ret;
const struct spi_buf txb = {.buf = tbuf, .len = sizeof(tbuf)};
const struct spi_buf rxb = {.buf = data->rbuf, .len = sizeof(data->rbuf)};
const struct spi_buf_set tx_bufs = {.buffers = &txb, .count = 1};
const struct spi_buf_set rx_bufs = {.buffers = &rxb, .count = 1};
/* Run number of reads and calculate average */
int rounds = config->reads;
struct measurement meas = {0};
for (int i = 0; i < rounds; i++) {
if (xpt2046_read_and_cumulate(&config->bus, &tx_bufs, &rx_bufs, &meas) != 0) {
return;
}
}
meas.x /= rounds;
meas.y /= rounds;
meas.z /= rounds;
/* Calculate Xp = M * Xt + C using fixed point aritchmetics, where
* Xp is the point in screen coordinates, Xt is the touch coordinates.
* Use signed int32_t for calculation to ensure that we cover the roll-over to negative
* values and return zero instead.
*/
int32_t mx = (config->screen_size_x << 16) / (config->max_x - config->min_x);
int32_t cx = (config->screen_size_x << 16) - mx * config->max_x;
int32_t x = mx * meas.x + cx;
x = (x < 0 ? 0 : x) >> 16;
int32_t my = (config->screen_size_y << 16) / (config->max_y - config->min_y);
int32_t cy = (config->screen_size_y << 16) - my * config->max_y;
int32_t y = my * meas.y + cy;
y = (y < 0 ? 0 : y) >> 16;
bool pressed = meas.z > config->threshold;
/* Don't send any other than "pressed" events.
* releasing seem to cause just random noise
*/
if (pressed) {
LOG_DBG("raw: x=%4u y=%4u ==> x=%4d y=%4d", meas.x, meas.y, x, y);
input_report_abs(data->dev, INPUT_ABS_X, x, false, K_FOREVER);
input_report_abs(data->dev, INPUT_ABS_Y, y, false, K_FOREVER);
input_report_key(data->dev, INPUT_BTN_TOUCH, 1, true, K_FOREVER);
data->last_x = x;
data->last_y = y;
data->pressed = pressed;
/* Ensure that we send released event */
k_work_reschedule(&data->dwork, K_MSEC(100));
}
ret = gpio_add_callback(config->int_gpio.port, &data->int_gpio_cb);
if (ret < 0) {
LOG_ERR("Could not set gpio callback");
return;
}
}
static int xpt2046_init(const struct device *dev)
{
int r;
const struct xpt2046_config *config = dev->config;
struct xpt2046_data *data = dev->data;
if (!spi_is_ready_dt(&config->bus)) {
LOG_ERR("SPI controller device not ready");
return -ENODEV;
}
data->dev = dev;
k_work_init(&data->work, xpt2046_work_handler);
k_work_init_delayable(&data->dwork, xpt2046_release_handler);
if (!gpio_is_ready_dt(&config->int_gpio)) {
LOG_ERR("Interrupt GPIO controller device not ready");
return -ENODEV;
}
r = gpio_pin_configure_dt(&config->int_gpio, GPIO_INPUT);
if (r < 0) {
LOG_ERR("Could not configure interrupt GPIO pin");
return r;
}
r = gpio_pin_interrupt_configure_dt(&config->int_gpio, GPIO_INT_EDGE_TO_ACTIVE);
if (r < 0) {
LOG_ERR("Could not configure interrupt GPIO interrupt.");
return r;
}
gpio_init_callback(&data->int_gpio_cb, xpt2046_isr_handler, BIT(config->int_gpio.pin));
r = gpio_add_callback(config->int_gpio.port, &data->int_gpio_cb);
if (r < 0) {
LOG_ERR("Could not set gpio callback");
return r;
}
LOG_INF("Init '%s' device", dev->name);
return 0;
}
#define XPT2046_INIT(index) \
static const struct xpt2046_config xpt2046_config_##index = { \
.bus = SPI_DT_SPEC_INST_GET( \
index, SPI_OP_MODE_MASTER | SPI_TRANSFER_MSB | SPI_WORD_SET(8), 0), \
.int_gpio = GPIO_DT_SPEC_INST_GET(index, int_gpios), \
.min_x = DT_INST_PROP(index, min_x), \
.min_y = DT_INST_PROP(index, min_y), \
.max_x = DT_INST_PROP(index, max_x), \
.max_y = DT_INST_PROP(index, max_y), \
.threshold = DT_INST_PROP(index, z_threshold), \
.screen_size_x = DT_INST_PROP(index, touchscreen_size_x), \
.screen_size_y = DT_INST_PROP(index, touchscreen_size_y), \
.reads = DT_INST_PROP(index, reads), \
}; \
static struct xpt2046_data xpt2046_data_##index; \
DEVICE_DT_INST_DEFINE(index, xpt2046_init, NULL, &xpt2046_data_##index, \
&xpt2046_config_##index, POST_KERNEL, CONFIG_INPUT_INIT_PRIORITY, \
NULL); \
BUILD_ASSERT(DT_INST_PROP(index, min_x) < DT_INST_PROP(index, max_x), \
"min_x must be less than max_x"); \
BUILD_ASSERT(DT_INST_PROP(index, min_y) < DT_INST_PROP(index, max_y), \
"min_y must be less than max_y"); \
BUILD_ASSERT(DT_INST_PROP(index, z_threshold) > 10, "Too small threshold"); \
BUILD_ASSERT(DT_INST_PROP(index, touchscreen_size_x) > 1 && \
DT_INST_PROP(index, touchscreen_size_y) > 1, \
"Screen size undefined"); \
BUILD_ASSERT(DT_INST_PROP(index, reads) > 0, "Number of reads must be at least one");
DT_INST_FOREACH_STATUS_OKAY(XPT2046_INIT)
``` | /content/code_sandbox/drivers/input/input_xpt2046.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 2,388 |
```c
/*
*
*/
#include <zephyr/device.h>
#include <zephyr/input/input.h>
#include <zephyr/input/input_kbd_matrix.h>
#include <zephyr/kernel.h>
#include <zephyr/kernel.h>
#include <zephyr/logging/log.h>
#include <zephyr/sys/util.h>
LOG_MODULE_REGISTER(input_kbd_matrix, CONFIG_INPUT_LOG_LEVEL);
void input_kbd_matrix_poll_start(const struct device *dev)
{
struct input_kbd_matrix_common_data *data = dev->data;
k_sem_give(&data->poll_lock);
}
static bool input_kbd_matrix_ghosting(const struct device *dev)
{
const struct input_kbd_matrix_common_config *cfg = dev->config;
const kbd_row_t *state = cfg->matrix_new_state;
/*
* Matrix keyboard designs are suceptible to ghosting.
* An extra key appears to be pressed when 3 keys belonging to the same
* block are pressed. For example, in the following block:
*
* . . w . q .
* . . . . . .
* . . . . . .
* . . m . a .
*
* the key m would look as pressed if the user pressed keys w, q and a
* simultaneously. A block can also be formed, with not adjacent
* columns.
*/
for (int c = 0; c < cfg->col_size; c++) {
if (!state[c]) {
continue;
}
for (int c_next = c + 1; c_next < cfg->col_size; c_next++) {
/*
* We AND the columns to detect a "block". This is an
* indication of ghosting, due to current flowing from
* a key which was never pressed. In our case, current
* flowing is a bit set to 1 as we flipped the bits
* when the matrix was scanned. Now we OR the colums
* using z&(z-1) which is non-zero only if z has more
* than one bit set.
*/
kbd_row_t common_row_bits = state[c] & state[c_next];
if (common_row_bits & (common_row_bits - 1)) {
return true;
}
}
}
return false;
}
static void input_kbd_matrix_drive_column(const struct device *dev, int col)
{
const struct input_kbd_matrix_common_config *cfg = dev->config;
const struct input_kbd_matrix_api *api = cfg->api;
api->drive_column(dev, col);
#ifdef CONFIG_INPUT_KBD_DRIVE_COLUMN_HOOK
input_kbd_matrix_drive_column_hook(dev, col);
#endif
}
static bool input_kbd_matrix_scan(const struct device *dev)
{
const struct input_kbd_matrix_common_config *cfg = dev->config;
const struct input_kbd_matrix_api *api = cfg->api;
kbd_row_t row;
kbd_row_t key_event = 0U;
for (int col = 0; col < cfg->col_size; col++) {
if (cfg->actual_key_mask != NULL &&
cfg->actual_key_mask[col] == 0) {
continue;
}
input_kbd_matrix_drive_column(dev, col);
/* Allow the matrix to stabilize before reading it */
k_busy_wait(cfg->settle_time_us);
row = api->read_row(dev);
if (cfg->actual_key_mask != NULL) {
row &= cfg->actual_key_mask[col];
}
cfg->matrix_new_state[col] = row;
key_event |= row;
}
input_kbd_matrix_drive_column(dev, INPUT_KBD_MATRIX_COLUMN_DRIVE_NONE);
return key_event != 0U;
}
static void input_kbd_matrix_update_state(const struct device *dev)
{
const struct input_kbd_matrix_common_config *cfg = dev->config;
struct input_kbd_matrix_common_data *data = dev->data;
kbd_row_t *matrix_new_state = cfg->matrix_new_state;
uint32_t cycles_now;
kbd_row_t row_changed;
kbd_row_t deb_col;
cycles_now = k_cycle_get_32();
data->scan_clk_cycle[data->scan_cycles_idx] = cycles_now;
/*
* The intent of this loop is to gather information related to key
* changes.
*/
for (int c = 0; c < cfg->col_size; c++) {
/* Check if there was an update from the previous scan */
row_changed = matrix_new_state[c] ^ cfg->matrix_previous_state[c];
if (!row_changed) {
continue;
}
for (int r = 0; r < cfg->row_size; r++) {
uint8_t cyc_idx = c * cfg->row_size + r;
/*
* Index all they keys that changed for each row in
* order to debounce each key in terms of it
*/
if (row_changed & BIT(r)) {
cfg->scan_cycle_idx[cyc_idx] = data->scan_cycles_idx;
}
}
cfg->matrix_unstable_state[c] |= row_changed;
cfg->matrix_previous_state[c] = matrix_new_state[c];
}
for (int c = 0; c < cfg->col_size; c++) {
deb_col = cfg->matrix_unstable_state[c];
if (!deb_col) {
continue;
}
/* Debouncing for each row key occurs here */
for (int r = 0; r < cfg->row_size; r++) {
kbd_row_t mask = BIT(r);
kbd_row_t row_bit = matrix_new_state[c] & mask;
/* Continue if we already debounce a key */
if (!(deb_col & mask)) {
continue;
}
uint8_t cyc_idx = c * cfg->row_size + r;
uint8_t scan_cyc_idx = cfg->scan_cycle_idx[cyc_idx];
uint32_t scan_clk_cycle = data->scan_clk_cycle[scan_cyc_idx];
/* Convert the clock cycle differences to usec */
uint32_t deb_t_us = k_cyc_to_us_floor32(cycles_now - scan_clk_cycle);
/* Does the key requires more time to be debounced? */
if (deb_t_us < (row_bit ? cfg->debounce_down_us : cfg->debounce_up_us)) {
/* Need more time to debounce */
continue;
}
cfg->matrix_unstable_state[c] &= ~mask;
/* Check if there was a change in the stable state */
if ((cfg->matrix_stable_state[c] & mask) == row_bit) {
/* Key state did not change */
continue;
}
/*
* The current row has been debounced, therefore update
* the stable state. Then, proceed to notify the
* application about the keys pressed.
*/
cfg->matrix_stable_state[c] ^= mask;
input_report_abs(dev, INPUT_ABS_X, c, false, K_FOREVER);
input_report_abs(dev, INPUT_ABS_Y, r, false, K_FOREVER);
input_report_key(dev, INPUT_BTN_TOUCH, row_bit, true, K_FOREVER);
}
}
data->scan_cycles_idx = (data->scan_cycles_idx + 1) % INPUT_KBD_MATRIX_SCAN_OCURRENCES;
}
static bool input_kbd_matrix_check_key_events(const struct device *dev)
{
const struct input_kbd_matrix_common_config *cfg = dev->config;
bool key_pressed;
/* Scan the matrix */
key_pressed = input_kbd_matrix_scan(dev);
for (int c = 0; c < cfg->col_size; c++) {
LOG_DBG("c=%2d u=%" PRIkbdrow " p=%" PRIkbdrow " n=%" PRIkbdrow,
c,
cfg->matrix_unstable_state[c],
cfg->matrix_previous_state[c],
cfg->matrix_new_state[c]);
}
/* Abort if ghosting is detected */
if (cfg->ghostkey_check && input_kbd_matrix_ghosting(dev)) {
return key_pressed;
}
input_kbd_matrix_update_state(dev);
return key_pressed;
}
static k_timepoint_t input_kbd_matrix_poll_timeout(const struct device *dev)
{
const struct input_kbd_matrix_common_config *cfg = dev->config;
if (cfg->poll_timeout_ms == 0) {
return sys_timepoint_calc(K_FOREVER);
}
return sys_timepoint_calc(K_MSEC(cfg->poll_timeout_ms));
}
static void input_kbd_matrix_poll(const struct device *dev)
{
const struct input_kbd_matrix_common_config *cfg = dev->config;
k_timepoint_t poll_time_end;
uint32_t current_cycles;
uint32_t cycles_diff;
uint32_t wait_period_us;
poll_time_end = input_kbd_matrix_poll_timeout(dev);
while (true) {
uint32_t start_period_cycles = k_cycle_get_32();
if (input_kbd_matrix_check_key_events(dev)) {
poll_time_end = input_kbd_matrix_poll_timeout(dev);
} else if (sys_timepoint_expired(poll_time_end)) {
break;
}
/*
* Subtract the time invested from the sleep period in order to
* compensate for the time invested in debouncing a key
*/
current_cycles = k_cycle_get_32();
cycles_diff = current_cycles - start_period_cycles;
wait_period_us = cfg->poll_period_us - k_cyc_to_us_floor32(cycles_diff);
wait_period_us = CLAMP(wait_period_us,
USEC_PER_MSEC, cfg->poll_period_us);
LOG_DBG("wait_period_us: %d", wait_period_us);
/* Allow other threads to run while we sleep */
k_usleep(wait_period_us);
}
}
static void input_kbd_matrix_polling_thread(void *arg1, void *unused2, void *unused3)
{
const struct device *dev = arg1;
const struct input_kbd_matrix_common_config *cfg = dev->config;
const struct input_kbd_matrix_api *api = cfg->api;
struct input_kbd_matrix_common_data *data = dev->data;
ARG_UNUSED(unused2);
ARG_UNUSED(unused3);
while (true) {
input_kbd_matrix_drive_column(dev, INPUT_KBD_MATRIX_COLUMN_DRIVE_ALL);
api->set_detect_mode(dev, true);
/* Check the rows again after enabling the interrupt to catch
* any potential press since the last read.
*/
if (api->read_row(dev) != 0) {
input_kbd_matrix_poll_start(dev);
}
k_sem_take(&data->poll_lock, K_FOREVER);
LOG_DBG("scan start");
/* Disable interrupt of KSI pins and start polling */
api->set_detect_mode(dev, false);
input_kbd_matrix_poll(dev);
}
}
int input_kbd_matrix_common_init(const struct device *dev)
{
struct input_kbd_matrix_common_data *data = dev->data;
k_sem_init(&data->poll_lock, 0, 1);
k_thread_create(&data->thread, data->thread_stack,
K_KERNEL_STACK_SIZEOF(data->thread_stack),
input_kbd_matrix_polling_thread, (void *)dev, NULL, NULL,
CONFIG_INPUT_KBD_MATRIX_THREAD_PRIORITY, 0, K_NO_WAIT);
k_thread_name_set(&data->thread, dev->name);
return 0;
}
#if CONFIG_INPUT_KBD_ACTUAL_KEY_MASK_DYNAMIC
int input_kbd_matrix_actual_key_mask_set(const struct device *dev,
uint8_t row, uint8_t col, bool enabled)
{
const struct input_kbd_matrix_common_config *cfg = dev->config;
if (row >= cfg->row_size || col >= cfg->col_size) {
return -EINVAL;
}
if (cfg->actual_key_mask == NULL) {
LOG_WRN("actual-key-mask not defined for %s", dev->name);
return -EINVAL;
}
WRITE_BIT(cfg->actual_key_mask[col], row, enabled);
return 0;
}
#endif
``` | /content/code_sandbox/drivers/input/input_kbd_matrix.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 2,590 |
```unknown
config INPUT_SDL_TOUCH
bool "SDL event filter for touch panel emulation"
default y
depends on DT_HAS_ZEPHYR_INPUT_SDL_TOUCH_ENABLED
depends on HAS_SDL
help
Enable driver for the SDL mouse event filter.
``` | /content/code_sandbox/drivers/input/Kconfig.sdl | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 55 |
```unknown
menuconfig INPUT_GT911
bool "GT9xx / GT9xxx capacitive touch panel driver"
default y
depends on DT_HAS_GOODIX_GT911_ENABLED
select I2C
help
Enable driver for multiple Goodix capacitive touch panel controllers.
This driver should support gt9110, gt912, gt927, gt9271, gt928,
gt967.
if INPUT_GT911
config INPUT_GT911_PERIOD_MS
int "Sample period"
depends on !INPUT_GT911_INTERRUPT
default 10
help
Sample period in milliseconds when in polling mode.
config INPUT_GT911_INTERRUPT
bool "Interrupt"
help
Enable interrupt support (requires GPIO).
config INPUT_GT911_MAX_TOUCH_POINTS
int "Touch Number"
default 1
range 1 5
help
Maximum number of touch points to be handled.
Multitouch is ignored if equal to 1.
endif # INPUT_GT911
``` | /content/code_sandbox/drivers/input/Kconfig.gt911 | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 198 |
```c
/*
*
*/
#define DT_DRV_COMPAT pixart_pmw3610
#include <stdint.h>
#include <stdlib.h>
#include <zephyr/device.h>
#include <zephyr/drivers/gpio.h>
#include <zephyr/drivers/spi.h>
#include <zephyr/input/input.h>
#include <zephyr/input/input_pmw3610.h>
#include <zephyr/kernel.h>
#include <zephyr/logging/log.h>
#include <zephyr/pm/device.h>
#include <zephyr/pm/device_runtime.h>
#include <zephyr/sys/byteorder.h>
#include <zephyr/sys/util.h>
LOG_MODULE_REGISTER(input_pmw3610, CONFIG_INPUT_LOG_LEVEL);
/* Page 0 */
#define PMW3610_PROD_ID 0x00
#define PMW3610_REV_ID 0x01
#define PMW3610_MOTION 0x02
#define PMW3610_DELTA_X_L 0x03
#define PMW3610_DELTA_Y_L 0x04
#define PMW3610_DELTA_XY_H 0x05
#define PMW3610_PERFORMANCE 0x11
#define PMW3610_BURST_READ 0x12
#define PMW3610_RUN_DOWNSHIFT 0x1b
#define PMW3610_REST1_RATE 0x1c
#define PMW3610_REST1_DOWNSHIFT 0x1d
#define PMW3610_OBSERVATION1 0x2d
#define PMW3610_SMART_MODE 0x32
#define PMW3610_POWER_UP_RESET 0x3a
#define PMW3610_SHUTDOWN 0x3b
#define PMW3610_SPI_CLK_ON_REQ 0x41
#define PWM3610_SPI_PAGE0 0x7f
/* Page 1 */
#define PMW3610_RES_STEP 0x05
#define PWM3610_SPI_PAGE1 0x7f
/* Burst register offsets */
#define BURST_MOTION 0
#define BURST_DELTA_X_L 1
#define BURST_DELTA_Y_L 2
#define BURST_DELTA_XY_H 3
#define BURST_SQUAL 4
#define BURST_SHUTTER_HI 5
#define BURST_SHUTTER_LO 6
#define BURST_DATA_LEN_NORMAL (BURST_DELTA_XY_H + 1)
#define BURST_DATA_LEN_SMART (BURST_SHUTTER_LO + 1)
#define BURST_DATA_LEN_MAX MAX(BURST_DATA_LEN_NORMAL, BURST_DATA_LEN_SMART)
/* Init sequence values */
#define OBSERVATION1_INIT_MASK 0x0f
#define PERFORMANCE_INIT 0x0d
#define RUN_DOWNSHIFT_INIT 0x04
#define REST1_RATE_INIT 0x04
#define REST1_DOWNSHIFT_INIT 0x0f
#define PRODUCT_ID_PMW3610 0x3e
#define SPI_WRITE BIT(7)
#define MOTION_STATUS_MOTION BIT(7)
#define SPI_CLOCK_ON_REQ_ON 0xba
#define SPI_CLOCK_ON_REQ_OFF 0xb5
#define RES_STEP_INV_X_BIT 6
#define RES_STEP_INV_Y_BIT 5
#define RES_STEP_RES_MASK 0x1f
#define PERFORMANCE_FMODE_MASK (0x0f << 4)
#define PERFORMANCE_FMODE_NORMAL (0x00 << 4)
#define PERFORMANCE_FMODE_FORCE_AWAKE (0x0f << 4)
#define POWER_UP_WAKEUP 0x96
#define SHUTDOWN_ENABLE 0xe7
#define SPI_PAGE0_1 0xff
#define SPI_PAGE1_0 0x00
#define SHUTTER_SMART_THRESHOLD 45
#define SMART_MODE_ENABLE 0x00
#define SMART_MODE_DISABLE 0x80
#define PMW3610_DATA_SIZE_BITS 12
#define RESET_DELAY_MS 10
#define INIT_OBSERVATION_DELAY_MS 10
#define CLOCK_ON_DELAY_US 300
#define RES_STEP 200
#define RES_MIN 200
#define RES_MAX 3200
struct pmw3610_config {
struct spi_dt_spec spi;
struct gpio_dt_spec motion_gpio;
struct gpio_dt_spec reset_gpio;
uint16_t axis_x;
uint16_t axis_y;
int16_t res_cpi;
bool invert_x;
bool invert_y;
bool force_awake;
bool smart_mode;
};
struct pmw3610_data {
const struct device *dev;
struct k_work motion_work;
struct gpio_callback motion_cb;
bool smart_flag;
};
static int pmw3610_read(const struct device *dev,
uint8_t addr, uint8_t *value, uint8_t len)
{
const struct pmw3610_config *cfg = dev->config;
const struct spi_buf tx_buf = {
.buf = &addr,
.len = sizeof(addr),
};
const struct spi_buf_set tx = {
.buffers = &tx_buf,
.count = 1,
};
struct spi_buf rx_buf[] = {
{
.buf = NULL,
.len = sizeof(addr),
},
{
.buf = value,
.len = len,
},
};
const struct spi_buf_set rx = {
.buffers = rx_buf,
.count = ARRAY_SIZE(rx_buf),
};
return spi_transceive_dt(&cfg->spi, &tx, &rx);
}
static int pmw3610_read_reg(const struct device *dev, uint8_t addr, uint8_t *value)
{
return pmw3610_read(dev, addr, value, 1);
}
static int pmw3610_write_reg(const struct device *dev, uint8_t addr, uint8_t value)
{
const struct pmw3610_config *cfg = dev->config;
uint8_t write_buf[] = {addr | SPI_WRITE, value};
const struct spi_buf tx_buf = {
.buf = write_buf,
.len = sizeof(write_buf),
};
const struct spi_buf_set tx = {
.buffers = &tx_buf,
.count = 1,
};
return spi_write_dt(&cfg->spi, &tx);
}
static int pmw3610_spi_clk_on(const struct device *dev)
{
int ret;
ret = pmw3610_write_reg(dev, PMW3610_SPI_CLK_ON_REQ, SPI_CLOCK_ON_REQ_ON);
k_sleep(K_USEC(CLOCK_ON_DELAY_US));
return ret;
}
static int pmw3610_spi_clk_off(const struct device *dev)
{
return pmw3610_write_reg(dev, PMW3610_SPI_CLK_ON_REQ, SPI_CLOCK_ON_REQ_OFF);
}
static void pmw3610_motion_work_handler(struct k_work *work)
{
struct pmw3610_data *data = CONTAINER_OF(
work, struct pmw3610_data, motion_work);
const struct device *dev = data->dev;
const struct pmw3610_config *cfg = dev->config;
uint8_t burst_data[BURST_DATA_LEN_MAX];
uint8_t burst_data_len;
int32_t x, y;
int ret;
if (cfg->smart_mode) {
burst_data_len = BURST_DATA_LEN_SMART;
} else {
burst_data_len = BURST_DATA_LEN_NORMAL;
}
ret = pmw3610_read(dev, PMW3610_BURST_READ, burst_data, burst_data_len);
if (ret < 0) {
return;
}
if ((burst_data[BURST_MOTION] & MOTION_STATUS_MOTION) == 0x00) {
return;
}
x = ((burst_data[BURST_DELTA_XY_H] << 4) & 0xf00) | burst_data[BURST_DELTA_X_L];
y = ((burst_data[BURST_DELTA_XY_H] << 8) & 0xf00) | burst_data[BURST_DELTA_Y_L];
x = sign_extend(x, PMW3610_DATA_SIZE_BITS - 1);
y = sign_extend(y, PMW3610_DATA_SIZE_BITS - 1);
input_report_rel(data->dev, cfg->axis_x, x, false, K_FOREVER);
input_report_rel(data->dev, cfg->axis_y, y, true, K_FOREVER);
if (cfg->smart_mode) {
uint16_t shutter_val = sys_get_be16(&burst_data[BURST_SHUTTER_HI]);
if (data->smart_flag && shutter_val < SHUTTER_SMART_THRESHOLD) {
pmw3610_spi_clk_on(dev);
ret = pmw3610_write_reg(dev, PMW3610_SMART_MODE, SMART_MODE_ENABLE);
if (ret < 0) {
return;
}
pmw3610_spi_clk_off(dev);
data->smart_flag = false;
} else if (!data->smart_flag && shutter_val > SHUTTER_SMART_THRESHOLD) {
pmw3610_spi_clk_on(dev);
ret = pmw3610_write_reg(dev, PMW3610_SMART_MODE, SMART_MODE_DISABLE);
if (ret < 0) {
return;
}
pmw3610_spi_clk_off(dev);
data->smart_flag = true;
}
}
}
static void pmw3610_motion_handler(const struct device *gpio_dev,
struct gpio_callback *cb,
uint32_t pins)
{
struct pmw3610_data *data = CONTAINER_OF(
cb, struct pmw3610_data, motion_cb);
k_work_submit(&data->motion_work);
}
int pmw3610_set_resolution(const struct device *dev, uint16_t res_cpi)
{
uint8_t val;
int ret;
if (!IN_RANGE(res_cpi, RES_MIN, RES_MAX)) {
LOG_ERR("res_cpi out of range: %d", res_cpi);
return -EINVAL;
}
ret = pmw3610_spi_clk_on(dev);
if (ret < 0) {
return ret;
}
ret = pmw3610_write_reg(dev, PWM3610_SPI_PAGE0, SPI_PAGE0_1);
if (ret < 0) {
return ret;
}
ret = pmw3610_read_reg(dev, PMW3610_RES_STEP, &val);
if (ret < 0) {
return ret;
}
val &= ~RES_STEP_RES_MASK;
val |= res_cpi / RES_STEP;
ret = pmw3610_write_reg(dev, PMW3610_RES_STEP, val);
if (ret < 0) {
return ret;
}
ret = pmw3610_write_reg(dev, PWM3610_SPI_PAGE1, SPI_PAGE1_0);
if (ret < 0) {
return ret;
}
ret = pmw3610_spi_clk_off(dev);
if (ret < 0) {
return ret;
}
return 0;
}
int pmw3610_force_awake(const struct device *dev, bool enable)
{
uint8_t val;
int ret;
ret = pmw3610_read_reg(dev, PMW3610_PERFORMANCE, &val);
if (ret < 0) {
return ret;
}
val &= ~PERFORMANCE_FMODE_MASK;
if (enable) {
val |= PERFORMANCE_FMODE_FORCE_AWAKE;
} else {
val |= PERFORMANCE_FMODE_NORMAL;
}
ret = pmw3610_spi_clk_on(dev);
if (ret < 0) {
return ret;
}
ret = pmw3610_write_reg(dev, PMW3610_PERFORMANCE, val);
if (ret < 0) {
return ret;
}
ret = pmw3610_spi_clk_off(dev);
if (ret < 0) {
return ret;
}
return 0;
}
static int pmw3610_configure(const struct device *dev)
{
const struct pmw3610_config *cfg = dev->config;
uint8_t val;
int ret;
if (cfg->reset_gpio.port != NULL) {
if (!gpio_is_ready_dt(&cfg->reset_gpio)) {
LOG_ERR("%s is not ready", cfg->reset_gpio.port->name);
return -ENODEV;
}
ret = gpio_pin_configure_dt(&cfg->reset_gpio, GPIO_OUTPUT_ACTIVE);
if (ret != 0) {
LOG_ERR("Reset pin configuration failed: %d", ret);
return ret;
}
k_sleep(K_MSEC(RESET_DELAY_MS));
gpio_pin_set_dt(&cfg->reset_gpio, 0);
k_sleep(K_MSEC(RESET_DELAY_MS));
}
ret = pmw3610_read_reg(dev, PMW3610_PROD_ID, &val);
if (ret < 0) {
return ret;
}
if (val != PRODUCT_ID_PMW3610) {
LOG_ERR("Invalid product id: %02x", val);
return -ENOTSUP;
}
/* Power-up init sequence */
ret = pmw3610_spi_clk_on(dev);
if (ret < 0) {
return ret;
}
ret = pmw3610_write_reg(dev, PMW3610_OBSERVATION1, 0);
if (ret < 0) {
return ret;
}
k_sleep(K_MSEC(INIT_OBSERVATION_DELAY_MS));
ret = pmw3610_read_reg(dev, PMW3610_OBSERVATION1, &val);
if (ret < 0) {
return ret;
}
if ((val & OBSERVATION1_INIT_MASK) != OBSERVATION1_INIT_MASK) {
LOG_ERR("Unexpected OBSERVATION1 value: %02x", val);
return -EINVAL;
}
for (uint8_t reg = PMW3610_MOTION; reg <= PMW3610_DELTA_XY_H; reg++) {
ret = pmw3610_read_reg(dev, reg, &val);
if (ret < 0) {
return ret;
}
}
ret = pmw3610_write_reg(dev, PMW3610_PERFORMANCE, PERFORMANCE_INIT);
if (ret < 0) {
return ret;
}
ret = pmw3610_write_reg(dev, PMW3610_RUN_DOWNSHIFT, RUN_DOWNSHIFT_INIT);
if (ret < 0) {
return ret;
}
ret = pmw3610_write_reg(dev, PMW3610_REST1_RATE, REST1_RATE_INIT);
if (ret < 0) {
return ret;
}
ret = pmw3610_write_reg(dev, PMW3610_REST1_DOWNSHIFT, REST1_DOWNSHIFT_INIT);
if (ret < 0) {
return ret;
}
/* Configuration */
if (cfg->invert_x || cfg->invert_y) {
ret = pmw3610_write_reg(dev, PWM3610_SPI_PAGE0, SPI_PAGE0_1);
if (ret < 0) {
return ret;
}
ret = pmw3610_read_reg(dev, PMW3610_RES_STEP, &val);
if (ret < 0) {
return ret;
}
WRITE_BIT(val, RES_STEP_INV_X_BIT, cfg->invert_x);
WRITE_BIT(val, RES_STEP_INV_Y_BIT, cfg->invert_y);
ret = pmw3610_write_reg(dev, PMW3610_RES_STEP, val);
if (ret < 0) {
return ret;
}
ret = pmw3610_write_reg(dev, PWM3610_SPI_PAGE1, SPI_PAGE1_0);
if (ret < 0) {
return ret;
}
}
ret = pmw3610_spi_clk_off(dev);
if (ret < 0) {
return ret;
}
/* The remaining functions call spi_clk_on/off independently. */
if (cfg->res_cpi > 0) {
pmw3610_set_resolution(dev, cfg->res_cpi);
}
pmw3610_force_awake(dev, cfg->force_awake);
return 0;
}
static int pmw3610_init(const struct device *dev)
{
const struct pmw3610_config *cfg = dev->config;
struct pmw3610_data *data = dev->data;
int ret;
if (!spi_is_ready_dt(&cfg->spi)) {
LOG_ERR("%s is not ready", cfg->spi.bus->name);
return -ENODEV;
}
data->dev = dev;
k_work_init(&data->motion_work, pmw3610_motion_work_handler);
if (!gpio_is_ready_dt(&cfg->motion_gpio)) {
LOG_ERR("%s is not ready", cfg->motion_gpio.port->name);
return -ENODEV;
}
ret = gpio_pin_configure_dt(&cfg->motion_gpio, GPIO_INPUT);
if (ret != 0) {
LOG_ERR("Motion pin configuration failed: %d", ret);
return ret;
}
gpio_init_callback(&data->motion_cb, pmw3610_motion_handler,
BIT(cfg->motion_gpio.pin));
ret = gpio_add_callback_dt(&cfg->motion_gpio, &data->motion_cb);
if (ret < 0) {
LOG_ERR("Could not set motion callback: %d", ret);
return ret;
}
ret = pmw3610_configure(dev);
if (ret != 0) {
LOG_ERR("Device configuration failed: %d", ret);
return ret;
}
ret = gpio_pin_interrupt_configure_dt(&cfg->motion_gpio,
GPIO_INT_EDGE_TO_ACTIVE);
if (ret != 0) {
LOG_ERR("Motion interrupt configuration failed: %d", ret);
return ret;
}
ret = pm_device_runtime_enable(dev);
if (ret < 0) {
LOG_ERR("Failed to enable runtime power management: %d", ret);
return ret;
}
return 0;
}
#ifdef CONFIG_PM_DEVICE
static int pmw3610_pm_action(const struct device *dev,
enum pm_device_action action)
{
int ret;
switch (action) {
case PM_DEVICE_ACTION_SUSPEND:
ret = pmw3610_write_reg(dev, PMW3610_SHUTDOWN, SHUTDOWN_ENABLE);
if (ret < 0) {
return ret;
}
break;
case PM_DEVICE_ACTION_RESUME:
ret = pmw3610_write_reg(dev, PMW3610_POWER_UP_RESET, POWER_UP_WAKEUP);
if (ret < 0) {
return ret;
}
break;
default:
return -ENOTSUP;
}
return 0;
}
#endif
#define PMW3610_SPI_MODE (SPI_OP_MODE_MASTER | SPI_WORD_SET(8) | \
SPI_MODE_CPOL | SPI_MODE_CPHA | SPI_TRANSFER_MSB)
#define PMW3610_INIT(n) \
BUILD_ASSERT(IN_RANGE(DT_INST_PROP_OR(n, res_cpi, RES_MIN), \
RES_MIN, RES_MAX), "invalid res-cpi"); \
\
static const struct pmw3610_config pmw3610_cfg_##n = { \
.spi = SPI_DT_SPEC_INST_GET(n, PMW3610_SPI_MODE, 0), \
.motion_gpio = GPIO_DT_SPEC_INST_GET(n, motion_gpios), \
.reset_gpio = GPIO_DT_SPEC_INST_GET_OR(n, reset_gpios, {}), \
.axis_x = DT_INST_PROP(n, zephyr_axis_x), \
.axis_y = DT_INST_PROP(n, zephyr_axis_y), \
.res_cpi = DT_INST_PROP_OR(n, res_cpi, -1), \
.invert_x = DT_INST_PROP(n, invert_x), \
.invert_y = DT_INST_PROP(n, invert_y), \
.force_awake = DT_INST_PROP(n, force_awake), \
.smart_mode = DT_INST_PROP(n, smart_mode), \
}; \
\
static struct pmw3610_data pmw3610_data_##n; \
\
PM_DEVICE_DT_INST_DEFINE(n, pmw3610_pm_action); \
\
DEVICE_DT_INST_DEFINE(n, pmw3610_init, PM_DEVICE_DT_INST_GET(n), \
&pmw3610_data_##n, &pmw3610_cfg_##n, \
POST_KERNEL, CONFIG_INPUT_INIT_PRIORITY, \
NULL);
DT_INST_FOREACH_STATUS_OKAY(PMW3610_INIT)
``` | /content/code_sandbox/drivers/input/input_pmw3610.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 4,366 |
```unknown
config INPUT_GPIO_QDEC
bool "GPIO based QDEC input driver"
default y
depends on DT_HAS_GPIO_QDEC_ENABLED
help
GPIO Quadrature Decoder input driver.
``` | /content/code_sandbox/drivers/input/Kconfig.gpio_qdec | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 40 |
```objective-c
/*
*
*
* "Bottom" of the SDL input driver.
* When built with the native_simulator this will be built in the runner context,
* that is, with the host C library, and with the host include paths.
*/
#ifndef DRIVERS_INPUT_INPUT_SDL_TOUCH_BOTTOM_H
#define DRIVERS_INPUT_INPUT_SDL_TOUCH_BOTTOM_H
#include <stdint.h>
#include <stdbool.h>
#ifdef __cplusplus
extern "C" {
#endif
/* Note: None of these are public interfaces. But internal to the SDL input driver */
struct sdl_input_data {
const void *dev; /* device structure pointer */
void (*callback)(struct sdl_input_data *data);
int x;
int y;
bool pressed;
bool just_released;
};
void sdl_input_init_bottom(struct sdl_input_data *data);
#ifdef __cplusplus
}
#endif
#endif /* DRIVERS_INPUT_INPUT_SDL_TOUCH_BOTTOM_H */
``` | /content/code_sandbox/drivers/input/input_sdl_touch_bottom.h | objective-c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 182 |
```c
/*
*
*/
#define DT_DRV_COMPAT nuvoton_npcx_kbd
#include "soc_miwu.h"
#include <zephyr/drivers/clock_control.h>
#include <zephyr/drivers/pinctrl.h>
#include <zephyr/input/input_kbd_matrix.h>
#include <zephyr/kernel.h>
#include <zephyr/logging/log.h>
#include <zephyr/sys/util.h>
#include <zephyr/toolchain.h>
#include <soc.h>
LOG_MODULE_REGISTER(input_npcx_kbd, CONFIG_INPUT_LOG_LEVEL);
#define ROW_SIZE DT_INST_PROP(0, row_size)
/* Driver config */
struct npcx_kbd_config {
struct input_kbd_matrix_common_config common;
/* Keyboard scan controller base address */
struct kbs_reg *base;
/* Clock configuration */
struct npcx_clk_cfg clk_cfg;
/* Pinmux configuration */
const struct pinctrl_dev_config *pcfg;
/* Keyboard scan input (KSI) wake-up irq */
int irq;
/* Size of keyboard inputs-wui mapping array */
int wui_size;
/* Mapping table between keyboard inputs and wui */
struct npcx_wui wui_maps[];
};
struct npcx_kbd_data {
struct input_kbd_matrix_common_data common;
struct miwu_callback ksi_callback[ROW_SIZE];
};
INPUT_KBD_STRUCT_CHECK(struct npcx_kbd_config, struct npcx_kbd_data);
/* Keyboard scan local functions */
static void npcx_kbd_ksi_isr(const struct device *dev, struct npcx_wui *wui)
{
ARG_UNUSED(wui);
input_kbd_matrix_poll_start(dev);
}
static void npcx_kbd_set_detect_mode(const struct device *dev, bool enabled)
{
const struct npcx_kbd_config *const config = dev->config;
const struct input_kbd_matrix_common_config *common = &config->common;
if (enabled) {
for (int i = 0; i < common->row_size; i++) {
npcx_miwu_irq_get_and_clear_pending(&config->wui_maps[i]);
}
irq_enable(config->irq);
} else {
irq_disable(config->irq);
}
}
static void npcx_kbd_drive_column(const struct device *dev, int col)
{
const struct npcx_kbd_config *config = dev->config;
const struct input_kbd_matrix_common_config *common = &config->common;
struct kbs_reg *const inst = config->base;
uint32_t mask;
if (col >= common->col_size) {
LOG_ERR("invalid column: %d", col);
return;
}
if (col == INPUT_KBD_MATRIX_COLUMN_DRIVE_NONE) {
/* Drive all lines to high: key detection is disabled */
mask = ~0;
} else if (col == INPUT_KBD_MATRIX_COLUMN_DRIVE_ALL) {
/* Drive all lines to low for detection any key press */
mask = ~BIT_MASK(common->col_size);
} else {
/*
* Drive one line to low for determining which key's state
* changed.
*/
mask = ~BIT(col);
}
LOG_DBG("Drive col mask: %x", mask);
inst->KBSOUT0 = (mask & 0xFFFF);
inst->KBSOUT1 = ((mask >> 16) & 0x03);
}
static kbd_row_t npcx_kbd_read_row(const struct device *dev)
{
const struct npcx_kbd_config *config = dev->config;
const struct input_kbd_matrix_common_config *common = &config->common;
struct kbs_reg *const inst = config->base;
kbd_row_t val;
val = inst->KBSIN;
/* 1 means key pressed, otherwise means key released. */
val = ~val & BIT_MASK(common->row_size);
return val;
}
static void npcx_kbd_init_ksi_wui_callback(const struct device *dev,
struct miwu_callback *callback,
const struct npcx_wui *wui,
miwu_dev_callback_handler_t handler)
{
/* KSI signal which has no wake-up input source */
if (wui->table == NPCX_MIWU_TABLE_NONE) {
return;
}
/* Install callback function */
npcx_miwu_init_dev_callback(callback, wui, handler, dev);
npcx_miwu_manage_callback(callback, 1);
/* Configure MIWU setting and enable its interrupt */
npcx_miwu_interrupt_configure(wui, NPCX_MIWU_MODE_EDGE, NPCX_MIWU_TRIG_LOW);
npcx_miwu_irq_enable(wui);
}
static int npcx_kbd_init(const struct device *dev)
{
const struct device *clk_dev = DEVICE_DT_GET(NPCX_CLK_CTRL_NODE);
const struct npcx_kbd_config *const config = dev->config;
const struct input_kbd_matrix_common_config *common = &config->common;
struct npcx_kbd_data *const data = dev->data;
struct kbs_reg *const inst = config->base;
int ret;
if (!device_is_ready(clk_dev)) {
LOG_ERR("%s device not ready", clk_dev->name);
return -ENODEV;
}
/* Turn on KBSCAN controller device clock */
ret = clock_control_on(clk_dev, (clock_control_subsys_t)&config->clk_cfg);
if (ret < 0) {
LOG_ERR("Turn on KBSCAN clock fail %d", ret);
return -EIO;
}
/* Pull-up KBSIN0-7 internally */
inst->KBSINPU = 0xFF;
/*
* Keyboard Scan Control Register
*
* [6:7] - KBHDRV KBSOUTn signals output buffers are open-drain.
* [3] - KBSINC Auto-increment of Buffer Data register is disabled
* [2] - KBSIEN Interrupt of Auto-Scan is disabled
* [1] - KBSMODE Key detection mechanism is implemented by firmware
* [0] - START Write 0 to this field is not affected
*/
inst->KBSCTL = 0x00;
/*
* Select quasi-bidirectional buffers for KSO pins. It reduces the
* low-to-high transition time. This feature only supports in npcx7.
*/
if (IS_ENABLED(CONFIG_INPUT_NPCX_KBD_KSO_HIGH_DRIVE)) {
SET_FIELD(inst->KBSCTL, NPCX_KBSCTL_KBHDRV_FIELD, 0x01);
}
/* Drive all column lines to low for detection any key press */
npcx_kbd_drive_column(dev, INPUT_KBD_MATRIX_COLUMN_DRIVE_NONE);
if (common->row_size != ROW_SIZE) {
LOG_ERR("Unexpected ROW_SIZE: %d != %d", common->row_size, ROW_SIZE);
return -EINVAL;
}
/* Configure wake-up input and callback for keyboard input signal */
for (int i = 0; i < common->row_size; i++) {
npcx_kbd_init_ksi_wui_callback(
dev, &data->ksi_callback[i], &config->wui_maps[i],
npcx_kbd_ksi_isr);
}
/* Configure pin-mux for keyboard scan device */
ret = pinctrl_apply_state(config->pcfg, PINCTRL_STATE_DEFAULT);
if (ret < 0) {
LOG_ERR("keyboard scan pinctrl setup failed (%d)", ret);
return ret;
}
return input_kbd_matrix_common_init(dev);
}
PINCTRL_DT_INST_DEFINE(0);
INPUT_KBD_MATRIX_DT_INST_DEFINE(0);
static const struct input_kbd_matrix_api npcx_kbd_api = {
.drive_column = npcx_kbd_drive_column,
.read_row = npcx_kbd_read_row,
.set_detect_mode = npcx_kbd_set_detect_mode,
};
static const struct npcx_kbd_config npcx_kbd_cfg_0 = {
.common = INPUT_KBD_MATRIX_DT_INST_COMMON_CONFIG_INIT(0, &npcx_kbd_api),
.base = (struct kbs_reg *)DT_INST_REG_ADDR(0),
.pcfg = PINCTRL_DT_INST_DEV_CONFIG_GET(0),
.clk_cfg = NPCX_DT_CLK_CFG_ITEM(0),
.irq = DT_INST_IRQN(0),
.wui_size = NPCX_DT_WUI_ITEMS_LEN(0),
.wui_maps = NPCX_DT_WUI_ITEMS_LIST(0),
};
static struct npcx_kbd_data npcx_kbd_data_0;
DEVICE_DT_INST_DEFINE(0, npcx_kbd_init, NULL,
&npcx_kbd_data_0, &npcx_kbd_cfg_0,
POST_KERNEL, CONFIG_INPUT_INIT_PRIORITY, NULL);
BUILD_ASSERT(DT_NUM_INST_STATUS_OKAY(DT_DRV_COMPAT) == 1,
"only one nuvoton,npcx-kbd compatible node can be supported");
BUILD_ASSERT(IN_RANGE(DT_INST_PROP(0, row_size), 1, 8), "invalid row-size");
BUILD_ASSERT(IN_RANGE(DT_INST_PROP(0, col_size), 1, 18), "invalid col-size");
``` | /content/code_sandbox/drivers/input/input_npcx_kbd.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 1,934 |
```c
/**
*/
#define DT_DRV_COMPAT st_stmpe811
#include <zephyr/kernel.h>
#include <zephyr/drivers/gpio.h>
#include <zephyr/drivers/i2c.h>
#include <zephyr/input/input.h>
#include <zephyr/sys/byteorder.h>
#include <zephyr/logging/log.h>
LOG_MODULE_REGISTER(stmpe811, CONFIG_INPUT_LOG_LEVEL);
#define CHIP_ID 0x0811U
/* Touch Screen Pins definition */
#define STMPE811_GPIO_PIN_4 BIT(4)
#define STMPE811_GPIO_PIN_5 BIT(5)
#define STMPE811_GPIO_PIN_6 BIT(6)
#define STMPE811_GPIO_PIN_7 BIT(7)
#define STMPE811_TOUCH_YD STMPE811_GPIO_PIN_7
#define STMPE811_TOUCH_XD STMPE811_GPIO_PIN_6
#define STMPE811_TOUCH_YU STMPE811_GPIO_PIN_5
#define STMPE811_TOUCH_XU STMPE811_GPIO_PIN_4
#define STMPE811_TOUCH_IO_ALL \
(STMPE811_TOUCH_YD | STMPE811_TOUCH_XD | STMPE811_TOUCH_YU | STMPE811_TOUCH_XU)
/* Registers */
#define STMPE811_CHP_ID_LSB_REG 0x00U
#define STMPE811_ADC_CTRL1_REG 0x20U
#define STMPE811_ADC_CTRL2_REG 0x21U
#define STMPE811_SYS_CTRL1_REG 0x03U
#define STMPE811_SYS_CTRL2_REG 0x04U
#define STMPE811_TSC_CFG_REG 0x41U
#define STMPE811_IO_AF_REG 0x17U
#define STMPE811_FIFO_TH_REG 0x4AU
#define STMPE811_FIFO_STA_REG 0x4BU
#define STMPE811_FIFO_SIZE_REG 0x4CU
#define STMPE811_TSC_FRACT_XYZ_REG 0x56U
#define STMPE811_TSC_I_DRIVE_REG 0x58U
#define STMPE811_TSC_CTRL_REG 0x40U
#define STMPE811_INT_STA_REG 0x0BU
#define STMPE811_TSC_DATA_NON_INC_REG 0xD7U
#define STMPE811_INT_CTRL_REG 0x09U
#define STMPE811_INT_EN_REG 0x0AU
/* Touch detected bit */
#define STMPE811_TSC_CTRL_BIT_TOUCH_DET BIT(7)
/* Global interrupt enable bit */
#define STMPE811_INT_CTRL_BIT_GLOBAL_INT BIT(0)
/* IO expander functionalities */
#define STMPE811_SYS_CTRL2_BIT_ADC_FCT BIT(0)
#define STMPE811_SYS_CTRL2_BIT_TS_FCT BIT(1)
#define STMPE811_SYS_CTRL2_BIT_IO_FCT BIT(2)
/* Global Interrupts definitions */
#define STMPE811_INT_BIT_FIFO_THRESHOLD BIT(1) /* FIFO above threshold interrupt */
#define STMPE811_INT_BIT_TOUCH BIT(0) /* Touch/release is detected interrupt */
#define STMPE811_INT_ALL BIT_MASK(8) /* All interrupts */
/* Reset control */
#define STMPE811_SYS_CTRL1_RESET_ON 0
#define STMPE811_SYS_CTRL1_RESET_SOFT BIT(1) /* Soft reset */
/* Delays to ensure registers erasing */
#define STMPE811_RESET_DELAY_MS 10
#define STMPE811_WAIT_DELAY_MS 2
/* Configuration */
#define STMPE811_FIFO_TH_SINGLE_POINT 1
#define STMPE811_FIFO_STA_CLEAR 1
#define STMPE811_FIFO_STA_OPERATIONAL 0
#define STMPE811_TSC_I_DRIVE_LIMIT 1
/**
* Touch Screen Control
*
* - bits [1-3] X, Y only acquisition mode
*/
#define STMPE811_TSC_CTRL_CONF 3U
/**
* Analog-to-digital Converter
*
* - bit [3] selects 12 bit ADC
* - bits [4-6] select ADC conversion time = 80
*/
#define STMPE811_ADC_CTRL1_CONF 0x48U
/**
* ADC clock speed: 3.25 MHz
*
* - 00 : 1.625 MHz
* - 01 : 3.25 MHz
* - 10 : 6.5 MHz
* - 11 : 6.5 MHz
*/
#define STMPE811_ADC_CLOCK_SPEED 1
/**
* Range and accuracy of the pressure measurement (Z)
*
* - Fractional part : 7
* - Whole part : 1
*/
#define STMPE811_TSC_FRACT_XYZ_CONF 1
struct stmpe811_config {
struct i2c_dt_spec bus;
struct gpio_dt_spec int_gpio;
uint8_t panel_driver_settling_time_us;
uint8_t touch_detect_delay_us;
uint8_t touch_average_control;
uint8_t tracking_index;
uint16_t screen_width;
uint16_t screen_height;
int raw_x_min;
int raw_y_min;
uint16_t raw_x_max;
uint16_t raw_y_max;
};
struct stmpe811_data {
const struct device *dev;
struct k_work processing_work;
struct gpio_callback int_gpio_cb;
uint32_t touch_x;
uint32_t touch_y;
};
static int stmpe811_reset(const struct device *dev)
{
const struct stmpe811_config *config = dev->config;
/* Power down the stmpe811 */
int ret = i2c_reg_write_byte_dt(&config->bus, STMPE811_SYS_CTRL1_REG,
STMPE811_SYS_CTRL1_RESET_SOFT);
if (ret < 0) {
return ret;
}
k_msleep(STMPE811_RESET_DELAY_MS);
/* Power on the stmpe811 after the power off => all registers are reinitialized */
ret = i2c_reg_write_byte_dt(&config->bus, STMPE811_SYS_CTRL1_REG,
STMPE811_SYS_CTRL1_RESET_ON);
if (ret < 0) {
return ret;
}
k_msleep(STMPE811_WAIT_DELAY_MS);
return 0;
}
static int stmpe811_io_enable_af(const struct device *dev, uint32_t io_pin)
{
const struct stmpe811_config *config = dev->config;
/* Apply ~io_pin as a mask to the current register value */
return i2c_reg_update_byte_dt(&config->bus, STMPE811_IO_AF_REG, io_pin, 0);
}
static uint8_t stmpe811_tsc_config_bits(const struct device *dev)
{
const struct stmpe811_config *config = dev->config;
/**
* Configuration:
* - bits [0-2] : panel driver settling time
* - bits [3-5] : touch detect delay
* - bits [6-7] : touch average control
*/
return config->panel_driver_settling_time_us | config->touch_detect_delay_us << 3 |
config->touch_average_control << 6;
}
static uint8_t stmpe811_tsc_control_bits(const struct device *dev)
{
const struct stmpe811_config *config = dev->config;
/**
* Touch Screen Control
*
* - bit [0] enables TSC
* - bits [1-3] X, Y only acquisition mode
* - bits [4-6] window tracking index (set from config)
* - bit [7] TSC status (writing has no effect)
*/
return STMPE811_TSC_CTRL_CONF | config->tracking_index << 4;
}
static int stmpe811_ts_init(const struct device *dev)
{
const struct stmpe811_config *config = dev->config;
int err;
err = stmpe811_reset(dev);
if (err < 0) {
return err;
}
/* Select TSC pins in TSC alternate mode */
err = stmpe811_io_enable_af(dev, STMPE811_TOUCH_IO_ALL);
if (err < 0) {
return err;
}
/**
* Set the functionalities to be enabled
* Bits [0-3] disable functionalities if set to 1 (reset value: 0x0f)
*
* Apply inverted sum of chosen FCT bits as a mask to the currect register value
*/
err = i2c_reg_update_byte_dt(&config->bus, STMPE811_SYS_CTRL2_REG,
STMPE811_SYS_CTRL2_BIT_IO_FCT | STMPE811_SYS_CTRL2_BIT_TS_FCT |
STMPE811_SYS_CTRL2_BIT_ADC_FCT, 0);
if (err < 0) {
return err;
}
/* Select sample time, bit number and ADC reference */
err = i2c_reg_write_byte_dt(&config->bus, STMPE811_ADC_CTRL1_REG, STMPE811_ADC_CTRL1_CONF);
if (err < 0) {
return err;
}
/* Select the ADC clock speed */
err = i2c_reg_write_byte_dt(&config->bus, STMPE811_ADC_CTRL2_REG, STMPE811_ADC_CLOCK_SPEED);
if (err < 0) {
return err;
}
/* Touch screen configuration */
err = i2c_reg_write_byte_dt(&config->bus, STMPE811_TSC_CFG_REG,
stmpe811_tsc_config_bits(dev));
if (err < 0) {
return err;
}
/* Configure the touch FIFO threshold */
err = i2c_reg_write_byte_dt(&config->bus, STMPE811_FIFO_TH_REG,
STMPE811_FIFO_TH_SINGLE_POINT);
if (err < 0) {
return err;
}
/* Clear the FIFO memory content */
err = i2c_reg_write_byte_dt(&config->bus, STMPE811_FIFO_STA_REG, STMPE811_FIFO_STA_CLEAR);
if (err < 0) {
return err;
}
/* Set the range and accuracy of the pressure measurement (Z) */
err = i2c_reg_write_byte_dt(&config->bus, STMPE811_TSC_FRACT_XYZ_REG,
STMPE811_TSC_FRACT_XYZ_CONF);
if (err < 0) {
return err;
}
/* Set the driving capability (limit) of the device for TSC pins */
err = i2c_reg_write_byte_dt(&config->bus, STMPE811_TSC_I_DRIVE_REG,
STMPE811_TSC_I_DRIVE_LIMIT);
if (err < 0) {
return err;
}
/* Touch screen control configuration */
err = i2c_reg_write_byte_dt(&config->bus, STMPE811_TSC_CTRL_REG,
stmpe811_tsc_control_bits(dev));
if (err < 0) {
return err;
}
/**
* Clear all the status pending bits if any.
* Writing '1' to this register clears the corresponding bits.
* This is an 8-bit register, so writing 0xFF clears all.
*/
err = i2c_reg_write_byte_dt(&config->bus, STMPE811_INT_STA_REG, STMPE811_INT_ALL);
if (err < 0) {
return err;
}
/* Put the FIFO back into operation mode */
err = i2c_reg_write_byte_dt(&config->bus, STMPE811_FIFO_STA_REG,
STMPE811_FIFO_STA_OPERATIONAL);
if (err < 0) {
return err;
}
/* Enable FIFO and touch interrupts */
err = i2c_reg_write_byte_dt(&config->bus, STMPE811_INT_EN_REG,
STMPE811_INT_BIT_TOUCH | STMPE811_INT_BIT_FIFO_THRESHOLD);
if (err < 0) {
LOG_ERR("Could not enable interrupt types (%d)", err);
return err;
}
return 0;
}
static int stmpe811_ts_get_data(const struct device *dev)
{
const struct stmpe811_config *config = dev->config;
struct stmpe811_data *data = dev->data;
uint8_t data_xy[3];
uint32_t uldata_xy;
int ret = i2c_burst_read_dt(&config->bus, STMPE811_TSC_DATA_NON_INC_REG, data_xy,
sizeof(data_xy));
if (ret < 0) {
return ret;
}
/* Calculate positions values */
uldata_xy = (data_xy[0] << 16) | (data_xy[1] << 8) | data_xy[2];
data->touch_x = (uldata_xy >> 12U) & BIT_MASK(12);
data->touch_y = uldata_xy & BIT_MASK(12);
return 0;
}
static void stmpe811_report_touch(const struct device *dev)
{
const struct stmpe811_config *config = dev->config;
struct stmpe811_data *data = dev->data;
int x = data->touch_x;
int y = data->touch_y;
if (config->screen_width > 0 && config->screen_height > 0) {
x = (((int)data->touch_x - config->raw_x_min) * config->screen_width) /
(config->raw_x_max - config->raw_x_min);
y = (((int)data->touch_y - config->raw_y_min) * config->screen_height) /
(config->raw_y_max - config->raw_y_min);
x = CLAMP(x, 0, config->screen_width);
y = CLAMP(y, 0, config->screen_height);
}
input_report_abs(dev, INPUT_ABS_X, x, false, K_FOREVER);
input_report_abs(dev, INPUT_ABS_Y, y, false, K_FOREVER);
input_report_key(dev, INPUT_BTN_TOUCH, 1, true, K_FOREVER);
}
static int stmpe811_process(const struct device *dev)
{
const struct stmpe811_config *config = dev->config;
int err;
uint8_t int_sta, fifo_size, tsc_ctrl;
err = i2c_reg_read_byte_dt(&config->bus, STMPE811_INT_STA_REG, &int_sta);
if (err < 0) {
return err;
}
/* Clear processed interrupts */
err = i2c_reg_write_byte_dt(&config->bus, STMPE811_INT_STA_REG, int_sta);
if (err < 0) {
return err;
}
if (int_sta & STMPE811_INT_BIT_FIFO_THRESHOLD) {
/**
* Report every element in FIFO
*
* This requires a while loop to avoid a race condition
* in which an element is added after reading FIFO_SIZE.
*
* Exiting ISR without handling every element in FIFO
* would prevent FIFO_THRESHOLD interrupt from being triggered again.
*/
while (true) {
err = i2c_reg_read_byte_dt(&config->bus, STMPE811_FIFO_SIZE_REG,
&fifo_size);
if (err < 0) {
return err;
}
if (fifo_size == 0) {
break;
}
for (int i = 0; i < fifo_size; i++) {
err = stmpe811_ts_get_data(dev);
if (err < 0) {
return err;
}
stmpe811_report_touch(dev);
}
}
}
/* TOUCH interrupt also gets triggered at release */
if (int_sta & STMPE811_INT_BIT_TOUCH) {
err = i2c_reg_read_byte_dt(&config->bus, STMPE811_TSC_CTRL_REG, &tsc_ctrl);
if (err < 0) {
return err;
}
/* TOUCH interrupt + no touch detected in TSC_CTRL reg <=> release */
if (!(tsc_ctrl & STMPE811_TSC_CTRL_BIT_TOUCH_DET)) {
input_report_key(dev, INPUT_BTN_TOUCH, 0, true, K_FOREVER);
}
}
return 0;
}
static void stmpe811_work_handler(struct k_work *work)
{
struct stmpe811_data *data = CONTAINER_OF(work, struct stmpe811_data, processing_work);
const struct stmpe811_config *config = data->dev->config;
stmpe811_process(data->dev);
/**
* Reschedule ISR if there was an interrupt triggered during handling (race condition).
* IRQ is edge-triggered, so otherwise it would never be triggered again.
*/
if (gpio_pin_get_dt(&config->int_gpio)) {
k_work_submit(&data->processing_work);
}
}
static void stmpe811_interrupt_handler(const struct device *dev, struct gpio_callback *cb,
uint32_t pins)
{
struct stmpe811_data *data = CONTAINER_OF(cb, struct stmpe811_data, int_gpio_cb);
k_work_submit(&data->processing_work);
}
static int stmpe811_verify_chip_id(const struct device *dev)
{
const struct stmpe811_config *config = dev->config;
uint8_t buf[2];
i2c_burst_read_dt(&config->bus, STMPE811_CHP_ID_LSB_REG, buf, 2);
if (sys_get_be16(buf) != CHIP_ID) {
return -EINVAL;
}
return 0;
}
static int stmpe811_init(const struct device *dev)
{
const struct stmpe811_config *config = dev->config;
struct stmpe811_data *data = dev->data;
int err;
if (!i2c_is_ready_dt(&config->bus)) {
LOG_ERR("I2C controller device not ready");
return -ENODEV;
}
data->dev = dev;
k_work_init(&data->processing_work, stmpe811_work_handler);
/* Verify CHIP_ID */
err = stmpe811_verify_chip_id(dev);
if (err) {
LOG_ERR("CHIP ID verification failed (%d)", err);
return err;
}
/* Initialize */
err = stmpe811_ts_init(dev);
if (err) {
LOG_ERR("Touch screen controller initialization failed (%d)", err);
return err;
}
/* Initialize GPIO interrupt */
if (!gpio_is_ready_dt(&config->int_gpio)) {
LOG_ERR("Interrupt GPIO controller device not ready");
return -ENODEV;
}
err = gpio_pin_configure_dt(&config->int_gpio, GPIO_INPUT);
if (err < 0) {
LOG_ERR("Could not configure interrupt GPIO pin (%d)", err);
return err;
}
err = gpio_pin_interrupt_configure_dt(&config->int_gpio, GPIO_INT_EDGE_TO_ACTIVE);
if (err < 0) {
LOG_ERR("Could not configure GPIO interrupt (%d)", err);
return err;
}
gpio_init_callback(&data->int_gpio_cb, stmpe811_interrupt_handler,
BIT(config->int_gpio.pin));
err = gpio_add_callback_dt(&config->int_gpio, &data->int_gpio_cb);
if (err < 0) {
LOG_ERR("Could not set GPIO callback (%d)", err);
return err;
}
/* Enable global interrupts */
err = i2c_reg_write_byte_dt(&config->bus, STMPE811_INT_CTRL_REG,
STMPE811_INT_CTRL_BIT_GLOBAL_INT);
if (err < 0) {
LOG_ERR("Could not enable global interrupts (%d)", err);
return err;
}
return 0;
}
#define STMPE811_DEFINE(index) \
BUILD_ASSERT(DT_INST_PROP_OR(index, raw_x_max, 4096) > \
DT_INST_PROP_OR(index, raw_x_min, 0), \
"raw-x-max should be larger than raw-x-min"); \
BUILD_ASSERT(DT_INST_PROP_OR(index, raw_y_max, 4096) > \
DT_INST_PROP_OR(index, raw_y_min, 0), \
"raw-y-max should be larger than raw-y-min"); \
static const struct stmpe811_config stmpe811_config_##index = { \
.bus = I2C_DT_SPEC_INST_GET(index), \
.int_gpio = GPIO_DT_SPEC_INST_GET(index, int_gpios), \
.panel_driver_settling_time_us = \
DT_INST_ENUM_IDX(index, panel_driver_settling_time_us), \
.screen_width = DT_INST_PROP(index, screen_width), \
.screen_height = DT_INST_PROP(index, screen_height), \
.raw_x_min = DT_INST_PROP_OR(index, raw_x_min, 0), \
.raw_y_min = DT_INST_PROP_OR(index, raw_y_min, 0), \
.raw_x_max = DT_INST_PROP_OR(index, raw_x_max, 4096), \
.raw_y_max = DT_INST_PROP_OR(index, raw_y_max, 4096), \
.touch_detect_delay_us = DT_INST_ENUM_IDX(index, touch_detect_delay_us), \
.touch_average_control = DT_INST_ENUM_IDX(index, touch_average_control), \
.tracking_index = DT_INST_ENUM_IDX(index, tracking_index)}; \
static struct stmpe811_data stmpe811_data_##index; \
DEVICE_DT_INST_DEFINE(index, stmpe811_init, NULL, &stmpe811_data_##index, \
&stmpe811_config_##index, POST_KERNEL, CONFIG_INPUT_INIT_PRIORITY, \
NULL);
DT_INST_FOREACH_STATUS_OKAY(STMPE811_DEFINE)
``` | /content/code_sandbox/drivers/input/input_stmpe811.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 4,517 |
```c
/*
*
*/
#define DT_DRV_COMPAT pixart_pat912x
#include <stdint.h>
#include <stdlib.h>
#include <zephyr/device.h>
#include <zephyr/drivers/gpio.h>
#include <zephyr/drivers/i2c.h>
#include <zephyr/input/input.h>
#include <zephyr/input/input_pat912x.h>
#include <zephyr/kernel.h>
#include <zephyr/logging/log.h>
#include <zephyr/pm/device.h>
#include <zephyr/pm/device_runtime.h>
#include <zephyr/sys/byteorder.h>
#include <zephyr/sys/util.h>
LOG_MODULE_REGISTER(input_pat912x, CONFIG_INPUT_LOG_LEVEL);
#define PAT912X_PRODUCT_ID1 0x00
#define PAT912X_PRODUCT_ID2 0x01
#define PAT912X_MOTION_STATUS 0x02
#define PAT912X_DELTA_X_LO 0x03
#define PAT912X_DELTA_Y_LO 0x04
#define PAT912X_OPERATION_MODE 0x05
#define PAT912X_CONFIGURATION 0x06
#define PAT912X_WRITE_PROTECT 0x09
#define PAT912X_SLEEP1 0x0a
#define PAT912X_SLEEP2 0x0b
#define PAT912X_RES_X 0x0d
#define PAT912X_RES_Y 0x0e
#define PAT912X_DELTA_XY_HI 0x12
#define PAT912X_SHUTTER 0x14
#define PAT912X_FRAME_AVG 0x17
#define PAT912X_ORIENTATION 0x19
#define PRODUCT_ID_PAT9125EL 0x3191
#define CONFIGURATION_RESET 0x97
#define CONFIGURATION_CLEAR 0x17
#define CONFIGURATION_PD_ENH BIT(3)
#define WRITE_PROTECT_ENABLE 0x00
#define WRITE_PROTECT_DISABLE 0x5a
#define MOTION_STATUS_MOTION BIT(7)
#define RES_SCALING_FACTOR 5
#define RES_MAX (UINT8_MAX * RES_SCALING_FACTOR)
#define OPERATION_MODE_SLEEP_1_EN BIT(4)
#define OPERATION_MODE_SLEEP_12_EN (BIT(4) | BIT(3))
#define PAT912X_DATA_SIZE_BITS 12
#define RESET_DELAY_MS 2
struct pat912x_config {
struct i2c_dt_spec i2c;
struct gpio_dt_spec motion_gpio;
int32_t axis_x;
int32_t axis_y;
int16_t res_x_cpi;
int16_t res_y_cpi;
bool invert_x;
bool invert_y;
bool sleep1_enable;
bool sleep2_enable;
};
struct pat912x_data {
const struct device *dev;
struct k_work motion_work;
struct gpio_callback motion_cb;
};
static void pat912x_motion_work_handler(struct k_work *work)
{
struct pat912x_data *data = CONTAINER_OF(
work, struct pat912x_data, motion_work);
const struct device *dev = data->dev;
const struct pat912x_config *cfg = dev->config;
int32_t x, y;
uint8_t val;
uint8_t xy[2];
int ret;
ret = i2c_reg_read_byte_dt(&cfg->i2c, PAT912X_MOTION_STATUS, &val);
if (ret < 0) {
return;
}
if ((val & MOTION_STATUS_MOTION) == 0x00) {
return;
}
ret = i2c_burst_read_dt(&cfg->i2c, PAT912X_DELTA_X_LO, xy, sizeof(xy));
if (ret < 0) {
return;
}
x = xy[0];
y = xy[1];
ret = i2c_reg_read_byte_dt(&cfg->i2c, PAT912X_DELTA_XY_HI, &val);
if (ret < 0) {
return;
}
y |= (val << 8) & 0xf00;
x |= (val << 4) & 0xf00;
x = sign_extend(x, PAT912X_DATA_SIZE_BITS - 1);
y = sign_extend(y, PAT912X_DATA_SIZE_BITS - 1);
if (cfg->invert_x) {
x *= -1;
}
if (cfg->invert_y) {
y *= -1;
}
LOG_DBG("x=%4d y=%4d", x, y);
if (cfg->axis_x >= 0) {
bool sync = cfg->axis_y < 0;
input_report_rel(data->dev, cfg->axis_x, x, sync, K_FOREVER);
}
if (cfg->axis_y >= 0) {
input_report_rel(data->dev, cfg->axis_y, y, true, K_FOREVER);
}
/* Trigger one more scan in case more data is available. */
k_work_submit(&data->motion_work);
}
static void pat912x_motion_handler(const struct device *gpio_dev,
struct gpio_callback *cb,
uint32_t pins)
{
struct pat912x_data *data = CONTAINER_OF(
cb, struct pat912x_data, motion_cb);
k_work_submit(&data->motion_work);
}
int pat912x_set_resolution(const struct device *dev,
int16_t res_x_cpi, int16_t res_y_cpi)
{
const struct pat912x_config *cfg = dev->config;
int ret;
if (res_x_cpi >= 0) {
if (!IN_RANGE(res_x_cpi, 0, RES_MAX)) {
LOG_ERR("res_x_cpi out of range: %d", res_x_cpi);
return -EINVAL;
}
ret = i2c_reg_write_byte_dt(&cfg->i2c, PAT912X_RES_X,
res_x_cpi / RES_SCALING_FACTOR);
if (ret < 0) {
return ret;
}
}
if (res_y_cpi >= 0) {
if (!IN_RANGE(res_y_cpi, 0, RES_MAX)) {
LOG_ERR("res_y_cpi out of range: %d", res_y_cpi);
return -EINVAL;
}
ret = i2c_reg_write_byte_dt(&cfg->i2c, PAT912X_RES_Y,
res_y_cpi / RES_SCALING_FACTOR);
if (ret < 0) {
return ret;
}
}
return 0;
}
static int pat912x_configure(const struct device *dev)
{
const struct pat912x_config *cfg = dev->config;
uint8_t id[2];
int ret;
ret = i2c_burst_read_dt(&cfg->i2c, PAT912X_PRODUCT_ID1, id, sizeof(id));
if (ret < 0) {
return ret;
}
if (sys_get_be16(id) != PRODUCT_ID_PAT9125EL) {
LOG_ERR("Invalid product id: %04x", sys_get_be16(id));
return -ENOTSUP;
}
/* Software reset */
i2c_reg_write_byte_dt(&cfg->i2c, PAT912X_CONFIGURATION, CONFIGURATION_RESET);
/* no ret value check, the device NACKs */
k_sleep(K_MSEC(RESET_DELAY_MS));
ret = i2c_reg_write_byte_dt(&cfg->i2c, PAT912X_CONFIGURATION, CONFIGURATION_CLEAR);
if (ret < 0) {
return ret;
}
ret = pat912x_set_resolution(dev, cfg->res_x_cpi, cfg->res_y_cpi);
if (ret < 0) {
return ret;
}
if (cfg->sleep1_enable && cfg->sleep2_enable) {
ret = i2c_reg_update_byte_dt(&cfg->i2c,
PAT912X_OPERATION_MODE,
OPERATION_MODE_SLEEP_12_EN,
OPERATION_MODE_SLEEP_12_EN);
if (ret < 0) {
return ret;
}
} else if (cfg->sleep1_enable) {
ret = i2c_reg_update_byte_dt(&cfg->i2c,
PAT912X_OPERATION_MODE,
OPERATION_MODE_SLEEP_12_EN,
OPERATION_MODE_SLEEP_1_EN);
if (ret < 0) {
return ret;
}
}
return 0;
}
static int pat912x_init(const struct device *dev)
{
const struct pat912x_config *cfg = dev->config;
struct pat912x_data *data = dev->data;
int ret;
if (!i2c_is_ready_dt(&cfg->i2c)) {
LOG_ERR("%s is not ready", cfg->i2c.bus->name);
return -ENODEV;
}
data->dev = dev;
k_work_init(&data->motion_work, pat912x_motion_work_handler);
if (!gpio_is_ready_dt(&cfg->motion_gpio)) {
LOG_ERR("%s is not ready", cfg->motion_gpio.port->name);
return -ENODEV;
}
ret = gpio_pin_configure_dt(&cfg->motion_gpio, GPIO_INPUT);
if (ret != 0) {
LOG_ERR("Motion pin configuration failed: %d", ret);
return ret;
}
ret = gpio_pin_interrupt_configure_dt(&cfg->motion_gpio,
GPIO_INT_EDGE_TO_ACTIVE);
if (ret != 0) {
LOG_ERR("Motion interrupt configuration failed: %d", ret);
return ret;
}
gpio_init_callback(&data->motion_cb, pat912x_motion_handler,
BIT(cfg->motion_gpio.pin));
ret = pat912x_configure(dev);
if (ret != 0) {
LOG_ERR("Device configuration failed: %d", ret);
return ret;
}
ret = gpio_add_callback_dt(&cfg->motion_gpio, &data->motion_cb);
if (ret < 0) {
LOG_ERR("Could not set motion callback: %d", ret);
return ret;
}
/* Trigger an initial read to clear any pending motion status.*/
k_work_submit(&data->motion_work);
ret = pm_device_runtime_enable(dev);
if (ret < 0) {
LOG_ERR("Failed to enable runtime power management");
return ret;
}
return 0;
}
#ifdef CONFIG_PM_DEVICE
static int pat912x_pm_action(const struct device *dev,
enum pm_device_action action)
{
const struct pat912x_config *cfg = dev->config;
uint8_t val;
int ret;
switch (action) {
case PM_DEVICE_ACTION_SUSPEND:
val = CONFIGURATION_PD_ENH;
break;
case PM_DEVICE_ACTION_RESUME:
val = 0;
break;
default:
return -ENOTSUP;
}
ret = i2c_reg_update_byte_dt(&cfg->i2c, PAT912X_CONFIGURATION,
CONFIGURATION_PD_ENH, val);
if (ret < 0) {
return ret;
}
return 0;
}
#endif
#define PAT912X_INIT(n) \
BUILD_ASSERT(IN_RANGE(DT_INST_PROP_OR(n, res_x_cpi, 0), 0, RES_MAX), \
"invalid res-x-cpi"); \
BUILD_ASSERT(IN_RANGE(DT_INST_PROP_OR(n, res_y_cpi, 0), 0, RES_MAX), \
"invalid res-y-cpi"); \
BUILD_ASSERT(DT_INST_PROP(n, sleep1_enable) || \
!DT_INST_PROP(n, sleep2_enable), \
"invalid sleep configuration"); \
\
static const struct pat912x_config pat912x_cfg_##n = { \
.i2c = I2C_DT_SPEC_INST_GET(n), \
.motion_gpio = GPIO_DT_SPEC_INST_GET(n, motion_gpios), \
.axis_x = DT_INST_PROP_OR(n, zephyr_axis_x, -1), \
.axis_y = DT_INST_PROP_OR(n, zephyr_axis_y, -1), \
.res_x_cpi = DT_INST_PROP_OR(n, res_x_cpi, -1), \
.res_y_cpi = DT_INST_PROP_OR(n, res_y_cpi, -1), \
.invert_x = DT_INST_PROP(n, invert_x), \
.invert_y = DT_INST_PROP(n, invert_y), \
.sleep1_enable = DT_INST_PROP(n, sleep1_enable), \
.sleep2_enable = DT_INST_PROP(n, sleep2_enable), \
}; \
\
static struct pat912x_data pat912x_data_##n; \
\
PM_DEVICE_DT_INST_DEFINE(n, pat912x_pm_action); \
\
DEVICE_DT_INST_DEFINE(n, pat912x_init, PM_DEVICE_DT_INST_GET(n), \
&pat912x_data_##n, &pat912x_cfg_##n, \
POST_KERNEL, CONFIG_INPUT_INIT_PRIORITY, \
NULL);
DT_INST_FOREACH_STATUS_OKAY(PAT912X_INIT)
``` | /content/code_sandbox/drivers/input/input_pat912x.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 2,761 |
```c
/*
*
*/
#define DT_DRV_COMPAT goodix_gt911
#include <zephyr/drivers/gpio.h>
#include <zephyr/drivers/i2c.h>
#include <zephyr/input/input.h>
#include <zephyr/sys/byteorder.h>
#include <zephyr/logging/log.h>
LOG_MODULE_REGISTER(gt911, CONFIG_INPUT_LOG_LEVEL);
/* GT911 used registers */
#define DEVICE_ID BSWAP_16(0x8140U)
#define REG_STATUS BSWAP_16(0x814EU)
/* REG_TD_STATUS: Touch points. */
#define TOUCH_POINTS_MSK 0x0FU
/* REG_TD_STATUS: Pressed. */
#define TOUCH_STATUS_MSK (1 << 7U)
/* The GT911's config */
#define REG_GT911_CONFIG BSWAP_16(0x8047U)
#define REG_CONFIG_VERSION REG_GT911_CONFIG
#define REG_CONFIG_TOUCH_NUM_OFFSET 0x5
#define REG_CONFIG_SIZE 186U
#define GT911_PRODUCT_ID 0x00313139U
/* Points registers */
#define REG_POINT_0 0x814F
#define POINT_OFFSET 0x8
#define REG_POINT_ADDR(n) BSWAP_16(REG_POINT_0 + POINT_OFFSET * n)
/** GT911 configuration (DT). */
struct gt911_config {
/** I2C bus. */
struct i2c_dt_spec bus;
struct gpio_dt_spec rst_gpio;
/** Interrupt GPIO information. */
struct gpio_dt_spec int_gpio;
/* Alternate fallback I2C address */
uint8_t alt_addr;
};
/** GT911 data. */
struct gt911_data {
/** Device pointer. */
const struct device *dev;
/** Work queue (for deferred read). */
struct k_work work;
/** Actual device I2C address */
uint8_t actual_address;
#ifdef CONFIG_INPUT_GT911_INTERRUPT
/** Interrupt GPIO callback. */
struct gpio_callback int_gpio_cb;
#else
/** Timer (polling mode). */
struct k_timer timer;
#endif
};
/** gt911 point reg */
struct gt911_point_reg {
uint8_t id; /*!< Track ID. */
uint8_t low_x; /*!< Low byte of x coordinate. */
uint8_t high_x; /*!< High byte of x coordinate. */
uint8_t low_y; /*!< Low byte of y coordinate. */
uint8_t high_y; /*!< High byte of x coordinate. */
uint8_t low_size; /*!< Low byte of point size. */
uint8_t high_size; /*!< High byte of point size. */
uint8_t reserved; /*!< Reserved. */
};
/*
* Device-specific wrappers around i2c_write_dt and i2c_write_read_dt.
* These wrappers handle the case where the GT911 did not accept the requested
* I2C address, and the alternate I2C address is used.
*/
static int gt911_i2c_write(const struct device *dev, const uint8_t *buf, uint32_t num_bytes)
{
const struct gt911_config *config = dev->config;
struct gt911_data *data = dev->data;
return i2c_write(config->bus.bus, buf, num_bytes, data->actual_address);
}
static int gt911_i2c_write_read(const struct device *dev, const void *write_buf, size_t num_write,
void *read_buf, size_t num_read)
{
const struct gt911_config *config = dev->config;
struct gt911_data *data = dev->data;
return i2c_write_read(config->bus.bus, data->actual_address, write_buf, num_write, read_buf,
num_read);
}
static int gt911_process(const struct device *dev)
{
int r;
uint16_t reg_addr;
uint8_t status;
uint8_t i;
uint8_t j;
uint16_t row;
uint16_t col;
uint8_t points;
static uint8_t prev_points;
struct gt911_point_reg point_reg[CONFIG_INPUT_GT911_MAX_TOUCH_POINTS];
static struct gt911_point_reg prev_point_reg[CONFIG_INPUT_GT911_MAX_TOUCH_POINTS];
/* obtain number of touch points */
reg_addr = REG_STATUS;
r = gt911_i2c_write_read(dev, ®_addr, sizeof(reg_addr), &status, sizeof(status));
if (r < 0) {
return r;
}
if (!(status & TOUCH_STATUS_MSK)) {
/* Status bit not set, ignore this event */
return 0;
}
points = status & TOUCH_POINTS_MSK;
/* need to clear the status */
uint8_t clear_buffer[3] = {(uint8_t)REG_STATUS, (uint8_t)(REG_STATUS >> 8), 0};
r = gt911_i2c_write(dev, clear_buffer, sizeof(clear_buffer));
if (r < 0) {
return r;
}
/* current points array */
for (i = 0; i <= points; i++) {
reg_addr = REG_POINT_ADDR(i);
r = gt911_i2c_write_read(dev, ®_addr, sizeof(reg_addr), &point_reg[i],
sizeof(point_reg[i]));
if (r < 0) {
return r;
}
}
/* touch events */
for (i = 0; i < points; i++) {
if (CONFIG_INPUT_GT911_MAX_TOUCH_POINTS > 1) {
input_report_abs(dev, INPUT_ABS_MT_SLOT, point_reg[i].id, true, K_FOREVER);
}
row = ((point_reg[i].high_y) << 8U) | point_reg[i].low_y;
col = ((point_reg[i].high_x) << 8U) | point_reg[i].low_x;
input_report_abs(dev, INPUT_ABS_X, col, false, K_FOREVER);
input_report_abs(dev, INPUT_ABS_Y, row, false, K_FOREVER);
input_report_key(dev, INPUT_BTN_TOUCH, 1, true, K_FOREVER);
}
/* release events */
for (i = 0; i < prev_points; i++) {
/* We look for the prev_point in the current points list */
for (j = 0; j < points; j++) {
if (prev_point_reg[i].id == point_reg[j].id) {
break;
}
}
if (j == points) {
if (CONFIG_INPUT_GT911_MAX_TOUCH_POINTS > 1) {
input_report_abs(dev, INPUT_ABS_MT_SLOT, prev_point_reg[i].id, true,
K_FOREVER);
}
row = ((prev_point_reg[i].high_y) << 8U) | prev_point_reg[i].low_y;
col = ((prev_point_reg[i].high_x) << 8U) | prev_point_reg[i].low_x;
input_report_abs(dev, INPUT_ABS_X, col, false, K_FOREVER);
input_report_abs(dev, INPUT_ABS_Y, row, false, K_FOREVER);
input_report_key(dev, INPUT_BTN_TOUCH, 0, true, K_FOREVER);
}
}
memcpy(prev_point_reg, point_reg, sizeof(point_reg));
prev_points = points;
return 0;
}
static void gt911_work_handler(struct k_work *work)
{
struct gt911_data *data = CONTAINER_OF(work, struct gt911_data, work);
gt911_process(data->dev);
}
#ifdef CONFIG_INPUT_GT911_INTERRUPT
static void gt911_isr_handler(const struct device *dev, struct gpio_callback *cb, uint32_t pins)
{
struct gt911_data *data = CONTAINER_OF(cb, struct gt911_data, int_gpio_cb);
k_work_submit(&data->work);
}
#else
static void gt911_timer_handler(struct k_timer *timer)
{
struct gt911_data *data = CONTAINER_OF(timer, struct gt911_data, timer);
k_work_submit(&data->work);
}
#endif
static uint8_t gt911_get_firmware_checksum(const uint8_t *firmware)
{
uint8_t sum = 0;
uint16_t i = 0;
for (i = 0; i < REG_CONFIG_SIZE - 2U; i++) {
sum += (*firmware);
firmware++;
}
return (~sum + 1U);
}
static bool gt911_verify_firmware(const uint8_t *firmware)
{
return ((firmware[REG_CONFIG_VERSION - REG_GT911_CONFIG] != 0U) &&
(gt911_get_firmware_checksum(firmware) == firmware[REG_CONFIG_SIZE - 2U]));
}
static int gt911_init(const struct device *dev)
{
const struct gt911_config *config = dev->config;
struct gt911_data *data = dev->data;
if (!i2c_is_ready_dt(&config->bus)) {
LOG_ERR("I2C controller device not ready");
return -ENODEV;
}
data->dev = dev;
data->actual_address = config->bus.addr;
k_work_init(&data->work, gt911_work_handler);
int r;
if (!gpio_is_ready_dt(&config->int_gpio)) {
LOG_ERR("Interrupt GPIO controller device not ready");
return -ENODEV;
}
if (config->rst_gpio.port != NULL) {
if (!gpio_is_ready_dt(&config->rst_gpio)) {
LOG_ERR("Reset GPIO controller device not ready");
return -ENODEV;
}
r = gpio_pin_configure_dt(&config->rst_gpio, GPIO_OUTPUT_ACTIVE);
if (r < 0) {
LOG_ERR("Could not configure reset GPIO pin");
return r;
}
}
if (config->alt_addr == 0x0) {
/*
* We need to configure the int-pin to 0, in order to enter the
* AddressMode0. Keeping the INT pin low during the reset sequence
* should result in the device selecting an I2C address of 0x5D.
* Note we skip this step if an alternate I2C address is set,
* and fall through to probing for the actual address.
*/
r = gpio_pin_configure_dt(&config->int_gpio, GPIO_OUTPUT_INACTIVE);
if (r < 0) {
LOG_ERR("Could not configure int GPIO pin");
return r;
}
}
/* Delay at least 10 ms after power on before we configure gt911 */
k_sleep(K_MSEC(20));
if (config->rst_gpio.port != NULL) {
/* reset the device and confgiure the addr mode0 */
gpio_pin_set_dt(&config->rst_gpio, 1);
/* hold down at least 1us, 1ms here */
k_sleep(K_MSEC(1));
gpio_pin_set_dt(&config->rst_gpio, 0);
/* hold down at least 5ms. This is the point the INT pin must be low. */
k_sleep(K_MSEC(5));
}
/* hold down 50ms to make sure the address available */
k_sleep(K_MSEC(50));
r = gpio_pin_configure_dt(&config->int_gpio, GPIO_INPUT);
if (r < 0) {
LOG_ERR("Could not configure interrupt GPIO pin");
return r;
}
#ifdef CONFIG_INPUT_GT911_INTERRUPT
r = gpio_pin_interrupt_configure_dt(&config->int_gpio, GPIO_INT_EDGE_TO_ACTIVE);
if (r < 0) {
LOG_ERR("Could not configure interrupt GPIO interrupt.");
return r;
}
gpio_init_callback(&data->int_gpio_cb, gt911_isr_handler, BIT(config->int_gpio.pin));
#else
k_timer_init(&data->timer, gt911_timer_handler, NULL);
#endif
/* check the Device ID first: '911' */
uint32_t reg_id = 0;
uint16_t reg_addr = DEVICE_ID;
if (config->alt_addr != 0x0) {
/*
* The level of the INT pin during reset is used by the GT911
* to select the I2C address mode. If an alternate I2C address
* is set, we should probe the GT911 to determine which address
* it actually selected. This is useful for boards that do not
* route the INT pin, or can only read it as an input (IE when
* using a level shifter).
*/
r = gt911_i2c_write_read(dev, ®_addr, sizeof(reg_addr), ®_id, sizeof(reg_id));
if (r < 0) {
/* Try alternate address */
data->actual_address = config->alt_addr;
r = gt911_i2c_write_read(dev, ®_addr, sizeof(reg_addr), ®_id,
sizeof(reg_id));
LOG_INF("Device did not accept I2C address, "
"updated to 0x%02X",
data->actual_address);
}
} else {
r = gt911_i2c_write_read(dev, ®_addr, sizeof(reg_addr), ®_id, sizeof(reg_id));
}
if (r < 0) {
LOG_ERR("Device did not respond to I2C request");
return r;
}
if (reg_id != GT911_PRODUCT_ID) {
LOG_ERR("The Device ID is not correct");
return -ENODEV;
}
/* need to setup the firmware first: read and write */
uint8_t gt911_config_firmware[REG_CONFIG_SIZE + 2] = {(uint8_t)REG_GT911_CONFIG,
(uint8_t)(REG_GT911_CONFIG >> 8)};
reg_addr = REG_GT911_CONFIG;
r = gt911_i2c_write_read(dev, ®_addr, sizeof(reg_addr), gt911_config_firmware + 2,
REG_CONFIG_SIZE);
if (r < 0) {
return r;
}
if (!gt911_verify_firmware(gt911_config_firmware + 2)) {
return -ENODEV;
}
gt911_config_firmware[REG_CONFIG_TOUCH_NUM_OFFSET + 2] =
CONFIG_INPUT_GT911_MAX_TOUCH_POINTS;
gt911_config_firmware[REG_CONFIG_SIZE] =
gt911_get_firmware_checksum(gt911_config_firmware + 2);
gt911_config_firmware[REG_CONFIG_SIZE + 1] = 1;
r = gt911_i2c_write(dev, gt911_config_firmware, sizeof(gt911_config_firmware));
if (r < 0) {
return r;
}
#ifdef CONFIG_INPUT_GT911_INTERRUPT
r = gpio_add_callback(config->int_gpio.port, &data->int_gpio_cb);
if (r < 0) {
LOG_ERR("Could not set gpio callback");
return r;
}
#else
k_timer_start(&data->timer, K_MSEC(CONFIG_INPUT_GT911_PERIOD_MS),
K_MSEC(CONFIG_INPUT_GT911_PERIOD_MS));
#endif
return 0;
}
#define GT911_INIT(index) \
static const struct gt911_config gt911_config_##index = { \
.bus = I2C_DT_SPEC_INST_GET(index), \
.rst_gpio = GPIO_DT_SPEC_INST_GET_OR(index, reset_gpios, {0}), \
.int_gpio = GPIO_DT_SPEC_INST_GET(index, irq_gpios), \
.alt_addr = DT_INST_PROP_OR(index, alt_addr, 0), \
}; \
static struct gt911_data gt911_data_##index; \
DEVICE_DT_INST_DEFINE(index, gt911_init, NULL, >911_data_##index, >911_config_##index, \
POST_KERNEL, CONFIG_INPUT_INIT_PRIORITY, NULL);
DT_INST_FOREACH_STATUS_OKAY(GT911_INIT)
``` | /content/code_sandbox/drivers/input/input_gt911.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 3,317 |
```c
/*
*
*/
#define DT_DRV_COMPAT chipsemi_chsc6x
#include <zephyr/sys/byteorder.h>
#include <zephyr/input/input.h>
#include <zephyr/drivers/i2c.h>
#include <zephyr/drivers/gpio.h>
#include <zephyr/logging/log.h>
struct chsc6x_config {
struct i2c_dt_spec i2c;
const struct gpio_dt_spec int_gpio;
};
struct chsc6x_data {
const struct device *dev;
struct k_work work;
struct gpio_callback int_gpio_cb;
};
#define CHSC6X_READ_ADDR 0
#define CHSC6X_READ_LENGTH 5
#define CHSC6X_OUTPUT_POINTS_PRESSED 0
#define CHSC6X_OUTPUT_COL 2
#define CHSC6X_OUTPUT_ROW 4
LOG_MODULE_REGISTER(chsc6x, CONFIG_INPUT_LOG_LEVEL);
static int chsc6x_process(const struct device *dev)
{
uint8_t output[CHSC6X_READ_LENGTH];
uint8_t row, col;
bool is_pressed;
int ret;
const struct chsc6x_config *cfg = dev->config;
ret = i2c_burst_read_dt(&cfg->i2c, CHSC6X_READ_ADDR, output, CHSC6X_READ_LENGTH);
if (ret < 0) {
LOG_ERR("Could not read data: %i", ret);
return -ENODATA;
}
is_pressed = output[CHSC6X_OUTPUT_POINTS_PRESSED];
col = output[CHSC6X_OUTPUT_COL];
row = output[CHSC6X_OUTPUT_ROW];
if (is_pressed) {
input_report_abs(dev, INPUT_ABS_X, col, false, K_FOREVER);
input_report_abs(dev, INPUT_ABS_Y, row, false, K_FOREVER);
input_report_key(dev, INPUT_BTN_TOUCH, 1, true, K_FOREVER);
} else {
input_report_key(dev, INPUT_BTN_TOUCH, 0, true, K_FOREVER);
}
return 0;
}
static void chsc6x_work_handler(struct k_work *work)
{
struct chsc6x_data *data = CONTAINER_OF(work, struct chsc6x_data, work);
chsc6x_process(data->dev);
}
static void chsc6x_isr_handler(const struct device *dev, struct gpio_callback *cb, uint32_t mask)
{
struct chsc6x_data *data = CONTAINER_OF(cb, struct chsc6x_data, int_gpio_cb);
k_work_submit(&data->work);
}
static int chsc6x_chip_init(const struct device *dev)
{
const struct chsc6x_config *cfg = dev->config;
if (!i2c_is_ready_dt(&cfg->i2c)) {
LOG_ERR("I2C bus %s not ready", cfg->i2c.bus->name);
return -ENODEV;
}
return 0;
}
static int chsc6x_init(const struct device *dev)
{
struct chsc6x_data *data = dev->data;
int ret;
data->dev = dev;
k_work_init(&data->work, chsc6x_work_handler);
const struct chsc6x_config *config = dev->config;
if (!gpio_is_ready_dt(&config->int_gpio)) {
LOG_ERR("GPIO port %s not ready", config->int_gpio.port->name);
return -ENODEV;
}
ret = gpio_pin_configure_dt(&config->int_gpio, GPIO_INPUT);
if (ret < 0) {
LOG_ERR("Could not configure interrupt GPIO pin: %d", ret);
return ret;
}
ret = gpio_pin_interrupt_configure_dt(&config->int_gpio, GPIO_INT_EDGE_TO_ACTIVE);
if (ret < 0) {
LOG_ERR("Could not configure interrupt GPIO interrupt: %d", ret);
return ret;
}
gpio_init_callback(&data->int_gpio_cb, chsc6x_isr_handler, BIT(config->int_gpio.pin));
ret = gpio_add_callback(config->int_gpio.port, &data->int_gpio_cb);
if (ret < 0) {
LOG_ERR("Could not set gpio callback: %d", ret);
return ret;
}
return chsc6x_chip_init(dev);
};
#define CHSC6X_DEFINE(index) \
static const struct chsc6x_config chsc6x_config_##index = { \
.i2c = I2C_DT_SPEC_INST_GET(index), \
.int_gpio = GPIO_DT_SPEC_INST_GET(index, irq_gpios), \
}; \
static struct chsc6x_data chsc6x_data_##index; \
DEVICE_DT_INST_DEFINE(index, chsc6x_init, NULL, &chsc6x_data_##index, \
&chsc6x_config_##index, POST_KERNEL, CONFIG_INPUT_INIT_PRIORITY, \
NULL);
DT_INST_FOREACH_STATUS_OKAY(CHSC6X_DEFINE)
``` | /content/code_sandbox/drivers/input/input_chsc6x.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 1,044 |
```c
/*
*/
#define DT_DRV_COMPAT adc_keys
#include <stdlib.h>
#include <stdbool.h>
#include <zephyr/device.h>
#include <zephyr/drivers/adc.h>
#include <zephyr/input/input.h>
#include <zephyr/kernel.h>
#include <zephyr/logging/log.h>
#include <zephyr/sys/util.h>
LOG_MODULE_REGISTER(adc_keys, CONFIG_INPUT_LOG_LEVEL);
struct adc_keys_code_config {
int32_t press_mv;
uint8_t key_index;
};
struct adc_keys_key_state {
bool last_state;
bool curr_state;
};
struct adc_keys_config {
struct adc_dt_spec channel;
uint32_t sample_period_ms;
int32_t keyup_mv;
const struct adc_keys_code_config *code_cfg;
const uint16_t *key_code;
struct adc_keys_key_state *key_state;
uint8_t code_cnt;
uint8_t key_cnt;
};
struct adc_keys_data {
const struct device *self;
struct k_work_delayable dwork;
struct adc_sequence seq;
};
static inline int32_t adc_keys_read(const struct device *dev)
{
const struct adc_keys_config *cfg = dev->config;
struct adc_keys_data *data = dev->data;
uint16_t sample_raw;
int32_t sample_mv;
int ret;
data->seq.buffer = &sample_raw;
data->seq.buffer_size = sizeof(sample_raw);
ret = adc_read(cfg->channel.dev, &data->seq);
if (ret) {
LOG_ERR("ADC read failed %d", ret);
return cfg->keyup_mv;
}
sample_mv = (int32_t)sample_raw;
adc_raw_to_millivolts_dt(&cfg->channel, &sample_mv);
return sample_mv;
}
static inline void adc_keys_process(const struct device *dev)
{
const struct adc_keys_config *cfg = dev->config;
int32_t sample_mv, closest_mv = 0;
uint32_t diff, closest_diff = UINT32_MAX;
const struct adc_keys_code_config *code_cfg;
struct adc_keys_key_state *key_state;
uint16_t key_code;
sample_mv = adc_keys_read(dev);
/*
* Find the closest key press threshold to the sample value.
*/
for (uint8_t i = 0; i < cfg->code_cnt; i++) {
diff = abs(sample_mv - cfg->code_cfg[i].press_mv);
if (diff < closest_diff) {
closest_diff = diff;
closest_mv = cfg->code_cfg[i].press_mv;
}
}
diff = abs(sample_mv - cfg->keyup_mv);
if (diff < closest_diff) {
closest_diff = diff;
closest_mv = cfg->keyup_mv;
}
LOG_DBG("sample=%d mV, closest=%d mV, diff=%d mV", sample_mv, closest_mv, closest_diff);
/*
* Update cached key states according to the closest key press threshold.
*
* Note that multiple keys may have the same press threshold, which is
* the mixed voltage that these keys are simultaneously pressed.
*/
for (uint8_t i = 0; i < cfg->code_cnt; i++) {
code_cfg = &cfg->code_cfg[i];
key_state = &cfg->key_state[code_cfg->key_index];
/*
* Only update curr_state if the key is pressed to prevent
* being overwritten by another threshold configuration.
*/
if (closest_mv == code_cfg->press_mv) {
key_state->curr_state = true;
}
}
/*
* Report the key event if the key state has changed.
*/
for (uint8_t i = 0; i < cfg->key_cnt; i++) {
key_state = &cfg->key_state[i];
key_code = cfg->key_code[i];
if (key_state->last_state != key_state->curr_state) {
LOG_DBG("Report event %s %d, code=%d", dev->name, key_state->curr_state,
key_code);
input_report_key(dev, key_code, key_state->curr_state, true, K_FOREVER);
key_state->last_state = key_state->curr_state;
}
/*
* Reset the state so that it can be updated in the next
* iteration.
*/
key_state->curr_state = false;
}
}
static void adc_keys_work_handler(struct k_work *work)
{
struct k_work_delayable *dwork = k_work_delayable_from_work(work);
struct adc_keys_data *data = CONTAINER_OF(dwork, struct adc_keys_data, dwork);
const struct device *dev = data->self;
const struct adc_keys_config *cfg = dev->config;
adc_keys_process(dev);
k_work_schedule(&data->dwork, K_MSEC(cfg->sample_period_ms));
}
static int adc_keys_init(const struct device *dev)
{
const struct adc_keys_config *cfg = dev->config;
struct adc_keys_data *data = dev->data;
int ret;
if (!adc_is_ready_dt(&cfg->channel)) {
LOG_ERR("ADC controller device %s not ready", cfg->channel.dev->name);
return -ENODEV;
}
ret = adc_channel_setup_dt(&cfg->channel);
if (ret) {
LOG_ERR("ADC channel setup failed %d", ret);
return ret;
}
ret = adc_sequence_init_dt(&cfg->channel, &data->seq);
if (ret) {
LOG_ERR("ADC sequence init failed %d", ret);
return ret;
}
data->self = dev;
k_work_init_delayable(&data->dwork, adc_keys_work_handler);
if (IS_ENABLED(CONFIG_INPUT_LOG_LEVEL_DBG)) {
for (uint8_t i = 0; i < cfg->code_cnt; i++) {
LOG_DBG("* code %d: key_index=%d threshold=%d mV code=%d", i,
cfg->code_cfg[i].key_index, cfg->code_cfg[i].press_mv,
cfg->key_code[cfg->code_cfg[i].key_index]);
}
}
k_work_schedule(&data->dwork, K_MSEC(cfg->sample_period_ms));
return 0;
}
#define ADC_KEYS_CODE_CFG_ITEM(node_id, prop, idx) \
{ \
.key_index = DT_NODE_CHILD_IDX(node_id) /* include disabled nodes */, \
.press_mv = DT_PROP_BY_IDX(node_id, prop, idx), \
}
#define ADC_KEYS_CODE_CFG(node_id) \
DT_FOREACH_PROP_ELEM_SEP(node_id, press_thresholds_mv, ADC_KEYS_CODE_CFG_ITEM, (,))
#define ADC_KEYS_KEY_CODE(node_id) DT_PROP(node_id, zephyr_code)
#define ADC_KEYS_INST(n) \
static struct adc_keys_data adc_keys_data_##n; \
\
static const struct adc_keys_code_config adc_keys_code_cfg_##n[] = { \
DT_INST_FOREACH_CHILD_STATUS_OKAY_SEP(n, ADC_KEYS_CODE_CFG, (,))}; \
\
static const uint16_t adc_keys_key_code_##n[] = { \
DT_INST_FOREACH_CHILD_SEP(n, ADC_KEYS_KEY_CODE, (,))}; \
\
static struct adc_keys_key_state \
adc_keys_key_state_##n[ARRAY_SIZE(adc_keys_key_code_##n)]; \
\
static const struct adc_keys_config adc_keys_cfg_##n = { \
.channel = ADC_DT_SPEC_INST_GET(n), \
.sample_period_ms = DT_INST_PROP(n, sample_period_ms), \
.keyup_mv = DT_INST_PROP(n, keyup_threshold_mv), \
.code_cfg = adc_keys_code_cfg_##n, \
.key_code = adc_keys_key_code_##n, \
.key_state = adc_keys_key_state_##n, \
.code_cnt = ARRAY_SIZE(adc_keys_code_cfg_##n), \
.key_cnt = ARRAY_SIZE(adc_keys_key_code_##n), \
}; \
\
DEVICE_DT_INST_DEFINE(n, adc_keys_init, NULL, &adc_keys_data_##n, &adc_keys_cfg_##n, \
POST_KERNEL, CONFIG_INPUT_INIT_PRIORITY, NULL);
DT_INST_FOREACH_STATUS_OKAY(ADC_KEYS_INST)
``` | /content/code_sandbox/drivers/input/input_adc_keys.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 1,756 |
```unknown
config INPUT_ESP32_TOUCH_SENSOR
bool "Espressif Touch Sensor input driver"
default n
depends on DT_HAS_ESPRESSIF_ESP32_TOUCH_ENABLED
help
Enable support for Espressif Touch Sensor input driver.
``` | /content/code_sandbox/drivers/input/Kconfig.esp32 | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 51 |
```c
/*
*/
#define DT_DRV_COMPAT ite_it8xxx2_kbd
#include <errno.h>
#include <soc.h>
#include <soc_dt.h>
#include <zephyr/device.h>
#include <zephyr/drivers/gpio.h>
#include <zephyr/drivers/interrupt_controller/wuc_ite_it8xxx2.h>
#include <zephyr/drivers/pinctrl.h>
#include <zephyr/dt-bindings/interrupt-controller/it8xxx2-wuc.h>
#include <zephyr/input/input.h>
#include <zephyr/input/input_kbd_matrix.h>
#include <zephyr/kernel.h>
#include <zephyr/sys/util_macro.h>
#include <zephyr/logging/log.h>
LOG_MODULE_REGISTER(input_ite_it8xxx2_kbd);
#define KEYBOARD_KSI_PIN_COUNT IT8XXX2_DT_INST_WUCCTRL_LEN(0)
struct it8xxx2_kbd_wuc_map_cfg {
/* WUC control device structure */
const struct device *wucs;
/* WUC pin mask */
uint8_t mask;
};
struct it8xxx2_kbd_config {
struct input_kbd_matrix_common_config common;
/* Keyboard scan controller base address */
struct kscan_it8xxx2_regs *base;
/* Keyboard scan input (KSI) wake-up irq */
int irq;
/* KSI[7:0] wake-up input source configuration list */
const struct it8xxx2_kbd_wuc_map_cfg *wuc_map_list;
/* KSI[7:0]/KSO[17:0] keyboard scan alternate configuration */
const struct pinctrl_dev_config *pcfg;
/* KSO16 GPIO cells */
struct gpio_dt_spec kso16_gpios;
/* KSO17 GPIO cells */
struct gpio_dt_spec kso17_gpios;
};
struct it8xxx2_kbd_data {
struct input_kbd_matrix_common_data common;
/* KSI[7:0] wake-up interrupt status mask */
uint8_t ksi_pin_mask;
};
INPUT_KBD_STRUCT_CHECK(struct it8xxx2_kbd_config, struct it8xxx2_kbd_data);
static void it8xxx2_kbd_drive_column(const struct device *dev, int col)
{
const struct it8xxx2_kbd_config *const config = dev->config;
const struct input_kbd_matrix_common_config *common = &config->common;
struct kscan_it8xxx2_regs *const inst = config->base;
const uint32_t kso_mask = BIT_MASK(common->col_size);
const uint8_t ksol_mask = kso_mask & 0xff;
const uint8_t ksoh1_mask = (kso_mask >> 8) & 0xff;
uint32_t kso_val;
unsigned int key;
/* Tri-state all outputs */
if (col == INPUT_KBD_MATRIX_COLUMN_DRIVE_NONE) {
kso_val = kso_mask;
/* Assert all outputs */
} else if (col == INPUT_KBD_MATRIX_COLUMN_DRIVE_ALL) {
kso_val = 0;
/* Assert a single output */
} else {
kso_val = kso_mask ^ BIT(col);
}
/* Set KSO[17:0] output data */
inst->KBS_KSOL = (inst->KBS_KSOL & ~ksol_mask) | (kso_val & ksol_mask);
/*
* Disable global interrupts for critical section
* The KBS_KSOH1 register contains both keyboard and GPIO output settings.
* Not all bits are for the keyboard will be driven, so a critical section
* is needed to avoid race conditions.
*/
key = irq_lock();
inst->KBS_KSOH1 = (inst->KBS_KSOH1 & ~ksoh1_mask) | ((kso_val >> 8) & ksoh1_mask);
/* Restore interrupts */
irq_unlock(key);
if (common->col_size > 16) {
inst->KBS_KSOH2 = (kso_val >> 16) & 0xff;
}
}
static kbd_row_t it8xxx2_kbd_read_row(const struct device *dev)
{
const struct it8xxx2_kbd_config *const config = dev->config;
struct kscan_it8xxx2_regs *const inst = config->base;
/* Bits are active-low, so toggle it (return 1 means key pressed) */
return (inst->KBS_KSI ^ 0xff);
}
static void it8xxx2_kbd_isr(const struct device *dev)
{
const struct it8xxx2_kbd_config *const config = dev->config;
struct it8xxx2_kbd_data *data = dev->data;
/*
* W/C wakeup interrupt status of KSI[7:0] pins
*
* NOTE: We want to clear the status as soon as possible,
* so clear KSI[7:0] pins at a time.
*/
it8xxx2_wuc_clear_status(config->wuc_map_list[0].wucs,
data->ksi_pin_mask);
/* W/C interrupt status of KSI[7:0] pins */
ite_intc_isr_clear(config->irq);
input_kbd_matrix_poll_start(dev);
}
static void it8xxx2_kbd_set_detect_mode(const struct device *dev, bool enable)
{
const struct it8xxx2_kbd_config *const config = dev->config;
struct it8xxx2_kbd_data *data = dev->data;
if (enable) {
/*
* W/C wakeup interrupt status of KSI[7:0] pins
*
* NOTE: We want to clear the status as soon as possible,
* so clear KSI[7:0] pins at a time.
*/
it8xxx2_wuc_clear_status(config->wuc_map_list[0].wucs,
data->ksi_pin_mask);
/* W/C interrupt status of KSI[7:0] pins */
ite_intc_isr_clear(config->irq);
irq_enable(config->irq);
} else {
irq_disable(config->irq);
}
}
static int it8xxx2_kbd_init(const struct device *dev)
{
const struct it8xxx2_kbd_config *const config = dev->config;
const struct input_kbd_matrix_common_config *common = &config->common;
struct it8xxx2_kbd_data *data = dev->data;
struct kscan_it8xxx2_regs *const inst = config->base;
const uint32_t kso_mask = BIT_MASK(common->col_size);
const uint8_t ksol_mask = kso_mask & 0xff;
const uint8_t ksoh1_mask = (kso_mask >> 8) & 0xff;
int status;
/* Disable wakeup and interrupt of KSI pins before configuring */
it8xxx2_kbd_set_detect_mode(dev, false);
if (common->col_size > 16) {
/*
* For KSO[16] and KSO[17]:
* 1.GPOTRC:
* Bit[x] = 1b: Enable the open-drain mode of KSO pin
* 2.GPCRCx:
* Bit[7:6] = 00b: Select alternate KSO function
* Bit[2] = 1b: Enable the internal pull-up of KSO pin
*
* NOTE: Set input temporarily for gpio_pin_configure(), after
* that pinctrl_apply_state() set to alternate function
* immediately.
*/
gpio_pin_configure_dt(&config->kso16_gpios, GPIO_INPUT);
gpio_pin_configure_dt(&config->kso17_gpios, GPIO_INPUT);
}
/*
* Enable the internal pull-up and kbs mode of the KSI[7:0] pins.
* Enable the internal pull-up and kbs mode of the KSO[15:0] pins.
* Enable the open-drain mode of the KSO[17:0] pins.
*/
status = pinctrl_apply_state(config->pcfg, PINCTRL_STATE_DEFAULT);
if (status < 0) {
LOG_ERR("Failed to configure KSI[7:0] and KSO[17:0] pins");
return status;
}
/* KSO[17:0] pins output low */
inst->KBS_KSOL = inst->KBS_KSOL & ~ksol_mask;
inst->KBS_KSOH1 = inst->KBS_KSOH1 & ~ksoh1_mask;
if (common->col_size > 16) {
inst->KBS_KSOH2 = 0x00;
}
for (int i = 0; i < KEYBOARD_KSI_PIN_COUNT; i++) {
/* Select wakeup interrupt falling-edge triggered of KSI[7:0] pins */
it8xxx2_wuc_set_polarity(config->wuc_map_list[i].wucs,
config->wuc_map_list[i].mask,
WUC_TYPE_EDGE_FALLING);
/* W/C wakeup interrupt status of KSI[7:0] pins */
it8xxx2_wuc_clear_status(config->wuc_map_list[i].wucs,
config->wuc_map_list[i].mask);
/* Enable wakeup interrupt of KSI[7:0] pins */
it8xxx2_wuc_enable(config->wuc_map_list[i].wucs,
config->wuc_map_list[i].mask);
/*
* We want to clear KSI[7:0] pins status at a time when wakeup
* interrupt fire, so gather the KSI[7:0] pin mask value here.
*/
if (config->wuc_map_list[i].wucs != config->wuc_map_list[0].wucs) {
LOG_ERR("KSI%d pin isn't in the same wuc node!", i);
}
data->ksi_pin_mask |= config->wuc_map_list[i].mask;
}
/* W/C interrupt status of KSI[7:0] pins */
ite_intc_isr_clear(config->irq);
irq_connect_dynamic(DT_INST_IRQN(0), 0,
(void (*)(const void *))it8xxx2_kbd_isr,
(const void *)dev, 0);
return input_kbd_matrix_common_init(dev);
}
static const struct it8xxx2_kbd_wuc_map_cfg
it8xxx2_kbd_wuc[IT8XXX2_DT_INST_WUCCTRL_LEN(0)] = IT8XXX2_DT_WUC_ITEMS_LIST(0);
PINCTRL_DT_INST_DEFINE(0);
INPUT_KBD_MATRIX_DT_INST_DEFINE(0);
static const struct input_kbd_matrix_api it8xxx2_kbd_api = {
.drive_column = it8xxx2_kbd_drive_column,
.read_row = it8xxx2_kbd_read_row,
.set_detect_mode = it8xxx2_kbd_set_detect_mode,
};
static const struct it8xxx2_kbd_config it8xxx2_kbd_cfg_0 = {
.common = INPUT_KBD_MATRIX_DT_INST_COMMON_CONFIG_INIT(0, &it8xxx2_kbd_api),
.base = (struct kscan_it8xxx2_regs *)DT_INST_REG_ADDR_BY_IDX(0, 0),
.irq = DT_INST_IRQN(0),
.wuc_map_list = it8xxx2_kbd_wuc,
.pcfg = PINCTRL_DT_INST_DEV_CONFIG_GET(0),
.kso16_gpios = GPIO_DT_SPEC_INST_GET(0, kso16_gpios),
.kso17_gpios = GPIO_DT_SPEC_INST_GET(0, kso17_gpios),
};
static struct it8xxx2_kbd_data it8xxx2_kbd_data_0;
DEVICE_DT_INST_DEFINE(0, &it8xxx2_kbd_init, NULL,
&it8xxx2_kbd_data_0, &it8xxx2_kbd_cfg_0,
POST_KERNEL, CONFIG_INPUT_INIT_PRIORITY, NULL);
BUILD_ASSERT(DT_NUM_INST_STATUS_OKAY(DT_DRV_COMPAT) == 1,
"only one ite,it8xxx2-kbd compatible node can be supported");
BUILD_ASSERT(IN_RANGE(DT_INST_PROP(0, row_size), 1, 8), "invalid row-size");
BUILD_ASSERT(IN_RANGE(DT_INST_PROP(0, col_size), 1, 18), "invalid col-size");
``` | /content/code_sandbox/drivers/input/input_ite_it8xxx2_kbd.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 2,653 |
```unknown
config INPUT_GPIO_KBD_MATRIX
bool "GPIO based keyboard matrix input driver"
default y
depends on DT_HAS_GPIO_KBD_MATRIX_ENABLED
select INPUT_KBD_MATRIX
help
GPIO keyboard matrix input driver.
``` | /content/code_sandbox/drivers/input/Kconfig.gpio_kbd_matrix | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 47 |
```c
/*
*
*/
#define DT_DRV_COMPAT pixart_paw32xx
#include <stdint.h>
#include <stdlib.h>
#include <zephyr/device.h>
#include <zephyr/drivers/gpio.h>
#include <zephyr/drivers/spi.h>
#include <zephyr/input/input.h>
#include <zephyr/input/input_paw32xx.h>
#include <zephyr/kernel.h>
#include <zephyr/logging/log.h>
#include <zephyr/pm/device.h>
#include <zephyr/pm/device_runtime.h>
#include <zephyr/sys/util.h>
LOG_MODULE_REGISTER(input_paw32xx, CONFIG_INPUT_LOG_LEVEL);
#define PAW32XX_PRODUCT_ID1 0x00
#define PAW32XX_PRODUCT_ID2 0x01
#define PAW32XX_MOTION 0x02
#define PAW32XX_DELTA_X 0x03
#define PAW32XX_DELTA_Y 0x04
#define PAW32XX_OPERATION_MODE 0x05
#define PAW32XX_CONFIGURATION 0x06
#define PAW32XX_WRITE_PROTECT 0x09
#define PAW32XX_SLEEP1 0x0a
#define PAW32XX_SLEEP2 0x0b
#define PAW32XX_SLEEP3 0x0c
#define PAW32XX_CPI_X 0x0d
#define PAW32XX_CPI_Y 0x0e
#define PAW32XX_DELTA_XY_HI 0x12
#define PAW32XX_MOUSE_OPTION 0x19
#define PRODUCT_ID_PAW32XX 0x30
#define SPI_WRITE BIT(7)
#define MOTION_STATUS_MOTION BIT(7)
#define OPERATION_MODE_SLP_ENH BIT(4)
#define OPERATION_MODE_SLP2_ENH BIT(3)
#define OPERATION_MODE_SLP_MASK (OPERATION_MODE_SLP_ENH | OPERATION_MODE_SLP2_ENH)
#define CONFIGURATION_PD_ENH BIT(3)
#define CONFIGURATION_RESET BIT(7)
#define WRITE_PROTECT_ENABLE 0x00
#define WRITE_PROTECT_DISABLE 0x5a
#define MOUSE_OPTION_MOVX_INV_BIT 3
#define MOUSE_OPTION_MOVY_INV_BIT 4
#define PAW32XX_DATA_SIZE_BITS 12
#define RESET_DELAY_MS 2
#define RES_STEP 38
#define RES_MIN (16 * RES_STEP)
#define RES_MAX (127 * RES_STEP)
struct paw32xx_config {
struct spi_dt_spec spi;
struct gpio_dt_spec motion_gpio;
uint16_t axis_x;
uint16_t axis_y;
int16_t res_cpi;
bool invert_x;
bool invert_y;
bool force_awake;
};
struct paw32xx_data {
const struct device *dev;
struct k_work motion_work;
struct gpio_callback motion_cb;
};
static int paw32xx_read_reg(const struct device *dev, uint8_t addr, uint8_t *value)
{
const struct paw32xx_config *cfg = dev->config;
const struct spi_buf tx_buf = {
.buf = &addr,
.len = sizeof(addr),
};
const struct spi_buf_set tx = {
.buffers = &tx_buf,
.count = 1,
};
struct spi_buf rx_buf[] = {
{
.buf = NULL,
.len = sizeof(addr),
},
{
.buf = value,
.len = 1,
},
};
const struct spi_buf_set rx = {
.buffers = rx_buf,
.count = ARRAY_SIZE(rx_buf),
};
return spi_transceive_dt(&cfg->spi, &tx, &rx);
}
static int paw32xx_write_reg(const struct device *dev, uint8_t addr, uint8_t value)
{
const struct paw32xx_config *cfg = dev->config;
uint8_t write_buf[] = {addr | SPI_WRITE, value};
const struct spi_buf tx_buf = {
.buf = write_buf,
.len = sizeof(write_buf),
};
const struct spi_buf_set tx = {
.buffers = &tx_buf,
.count = 1,
};
return spi_write_dt(&cfg->spi, &tx);
}
static int paw32xx_update_reg(const struct device *dev, uint8_t addr, uint8_t mask, uint8_t value)
{
uint8_t val;
int ret;
ret = paw32xx_read_reg(dev, addr, &val);
if (ret < 0) {
return ret;
}
val = (val & ~mask) | (value & mask);
ret = paw32xx_write_reg(dev, addr, val);
if (ret < 0) {
return ret;
}
return 0;
}
static int paw32xx_read_xy(const struct device *dev, int16_t *x, int16_t *y)
{
const struct paw32xx_config *cfg = dev->config;
int ret;
uint8_t tx_data[] = {
PAW32XX_DELTA_X,
0xff,
PAW32XX_DELTA_Y,
0xff,
PAW32XX_DELTA_XY_HI,
0xff,
};
uint8_t rx_data[sizeof(tx_data)];
const struct spi_buf tx_buf = {
.buf = tx_data,
.len = sizeof(tx_data),
};
const struct spi_buf_set tx = {
.buffers = &tx_buf,
.count = 1,
};
struct spi_buf rx_buf = {
.buf = rx_data,
.len = sizeof(rx_data),
};
const struct spi_buf_set rx = {
.buffers = &rx_buf,
.count = 1,
};
ret = spi_transceive_dt(&cfg->spi, &tx, &rx);
if (ret < 0) {
return ret;
}
*x = ((rx_data[5] << 4) & 0xf00) | rx_data[1];
*y = ((rx_data[5] << 8) & 0xf00) | rx_data[3];
*x = sign_extend(*x, PAW32XX_DATA_SIZE_BITS - 1);
*y = sign_extend(*y, PAW32XX_DATA_SIZE_BITS - 1);
return 0;
}
static void paw32xx_motion_work_handler(struct k_work *work)
{
struct paw32xx_data *data = CONTAINER_OF(
work, struct paw32xx_data, motion_work);
const struct device *dev = data->dev;
const struct paw32xx_config *cfg = dev->config;
uint8_t val;
int16_t x, y;
int ret;
ret = paw32xx_read_reg(dev, PAW32XX_MOTION, &val);
if (ret < 0) {
return;
}
if ((val & MOTION_STATUS_MOTION) == 0x00) {
return;
}
ret = paw32xx_read_xy(dev, &x, &y);
if (ret < 0) {
return;
}
LOG_DBG("x=%4d y=%4d", x, y);
input_report_rel(data->dev, cfg->axis_x, x, false, K_FOREVER);
input_report_rel(data->dev, cfg->axis_y, y, true, K_FOREVER);
/* Trigger one more scan if more data is available. */
if (gpio_pin_get_dt(&cfg->motion_gpio)) {
k_work_submit(&data->motion_work);
}
}
static void paw32xx_motion_handler(const struct device *gpio_dev,
struct gpio_callback *cb,
uint32_t pins)
{
struct paw32xx_data *data = CONTAINER_OF(
cb, struct paw32xx_data, motion_cb);
k_work_submit(&data->motion_work);
}
int paw32xx_set_resolution(const struct device *dev, uint16_t res_cpi)
{
uint8_t val;
int ret;
if (!IN_RANGE(res_cpi, RES_MIN, RES_MAX)) {
LOG_ERR("res_cpi out of range: %d", res_cpi);
return -EINVAL;
}
val = res_cpi / RES_STEP;
ret = paw32xx_write_reg(dev, PAW32XX_WRITE_PROTECT, WRITE_PROTECT_DISABLE);
if (ret < 0) {
return ret;
}
ret = paw32xx_write_reg(dev, PAW32XX_CPI_X, val);
if (ret < 0) {
return ret;
}
ret = paw32xx_write_reg(dev, PAW32XX_CPI_Y, val);
if (ret < 0) {
return ret;
}
ret = paw32xx_write_reg(dev, PAW32XX_WRITE_PROTECT, WRITE_PROTECT_ENABLE);
if (ret < 0) {
return ret;
}
return 0;
}
int paw32xx_force_awake(const struct device *dev, bool enable)
{
uint8_t val = enable ? 0 : OPERATION_MODE_SLP_MASK;
int ret;
ret = paw32xx_write_reg(dev, PAW32XX_WRITE_PROTECT, WRITE_PROTECT_DISABLE);
if (ret < 0) {
return ret;
}
ret = paw32xx_update_reg(dev, PAW32XX_OPERATION_MODE,
OPERATION_MODE_SLP_MASK, val);
if (ret < 0) {
return ret;
}
ret = paw32xx_write_reg(dev, PAW32XX_WRITE_PROTECT, WRITE_PROTECT_ENABLE);
if (ret < 0) {
return ret;
}
return 0;
}
static int paw32xx_configure(const struct device *dev)
{
const struct paw32xx_config *cfg = dev->config;
uint8_t val;
int ret;
ret = paw32xx_read_reg(dev, PAW32XX_PRODUCT_ID1, &val);
if (ret < 0) {
return ret;
}
if (val != PRODUCT_ID_PAW32XX) {
LOG_ERR("Invalid product id: %02x", val);
return -ENOTSUP;
}
ret = paw32xx_update_reg(dev, PAW32XX_CONFIGURATION,
CONFIGURATION_RESET, CONFIGURATION_RESET);
if (ret < 0) {
return ret;
}
k_sleep(K_MSEC(RESET_DELAY_MS));
if (cfg->invert_x || cfg->invert_y) {
ret = paw32xx_write_reg(dev, PAW32XX_WRITE_PROTECT, WRITE_PROTECT_DISABLE);
if (ret < 0) {
return ret;
}
ret = paw32xx_read_reg(dev, PAW32XX_MOUSE_OPTION, &val);
if (ret < 0) {
return ret;
}
WRITE_BIT(val, MOUSE_OPTION_MOVX_INV_BIT, cfg->invert_x);
WRITE_BIT(val, MOUSE_OPTION_MOVY_INV_BIT, cfg->invert_y);
ret = paw32xx_write_reg(dev, PAW32XX_MOUSE_OPTION, val);
if (ret < 0) {
return ret;
}
ret = paw32xx_write_reg(dev, PAW32XX_WRITE_PROTECT, WRITE_PROTECT_ENABLE);
if (ret < 0) {
return ret;
}
}
if (cfg->res_cpi > 0) {
paw32xx_set_resolution(dev, cfg->res_cpi);
}
paw32xx_force_awake(dev, cfg->force_awake);
return 0;
}
static int paw32xx_init(const struct device *dev)
{
const struct paw32xx_config *cfg = dev->config;
struct paw32xx_data *data = dev->data;
int ret;
if (!spi_is_ready_dt(&cfg->spi)) {
LOG_ERR("%s is not ready", cfg->spi.bus->name);
return -ENODEV;
}
data->dev = dev;
k_work_init(&data->motion_work, paw32xx_motion_work_handler);
if (!gpio_is_ready_dt(&cfg->motion_gpio)) {
LOG_ERR("%s is not ready", cfg->motion_gpio.port->name);
return -ENODEV;
}
ret = gpio_pin_configure_dt(&cfg->motion_gpio, GPIO_INPUT);
if (ret != 0) {
LOG_ERR("Motion pin configuration failed: %d", ret);
return ret;
}
gpio_init_callback(&data->motion_cb, paw32xx_motion_handler,
BIT(cfg->motion_gpio.pin));
ret = gpio_add_callback_dt(&cfg->motion_gpio, &data->motion_cb);
if (ret < 0) {
LOG_ERR("Could not set motion callback: %d", ret);
return ret;
}
ret = paw32xx_configure(dev);
if (ret != 0) {
LOG_ERR("Device configuration failed: %d", ret);
return ret;
}
ret = gpio_pin_interrupt_configure_dt(&cfg->motion_gpio,
GPIO_INT_EDGE_TO_ACTIVE);
if (ret != 0) {
LOG_ERR("Motion interrupt configuration failed: %d", ret);
return ret;
}
ret = pm_device_runtime_enable(dev);
if (ret < 0) {
LOG_ERR("Failed to enable runtime power management: %d", ret);
return ret;
}
return 0;
}
#ifdef CONFIG_PM_DEVICE
static int paw32xx_pm_action(const struct device *dev,
enum pm_device_action action)
{
int ret;
uint8_t val;
switch (action) {
case PM_DEVICE_ACTION_SUSPEND:
val = CONFIGURATION_PD_ENH;
break;
case PM_DEVICE_ACTION_RESUME:
val = 0;
break;
default:
return -ENOTSUP;
}
ret = paw32xx_update_reg(dev, PAW32XX_CONFIGURATION,
CONFIGURATION_PD_ENH, val);
if (ret < 0) {
return ret;
}
return 0;
}
#endif
#define PAW32XX_SPI_MODE (SPI_OP_MODE_MASTER | SPI_WORD_SET(8) | \
SPI_MODE_CPOL | SPI_MODE_CPHA | SPI_TRANSFER_MSB)
#define PAW32XX_INIT(n) \
BUILD_ASSERT(IN_RANGE(DT_INST_PROP_OR(n, res_cpi, RES_MIN), \
RES_MIN, RES_MAX), "invalid res-cpi"); \
\
static const struct paw32xx_config paw32xx_cfg_##n = { \
.spi = SPI_DT_SPEC_INST_GET(n, PAW32XX_SPI_MODE, 0), \
.motion_gpio = GPIO_DT_SPEC_INST_GET(n, motion_gpios), \
.axis_x = DT_INST_PROP(n, zephyr_axis_x), \
.axis_y = DT_INST_PROP(n, zephyr_axis_y), \
.res_cpi = DT_INST_PROP_OR(n, res_cpi, -1), \
.invert_x = DT_INST_PROP(n, invert_x), \
.invert_y = DT_INST_PROP(n, invert_y), \
.force_awake = DT_INST_PROP(n, force_awake), \
}; \
\
static struct paw32xx_data paw32xx_data_##n; \
\
PM_DEVICE_DT_INST_DEFINE(n, paw32xx_pm_action); \
\
DEVICE_DT_INST_DEFINE(n, paw32xx_init, PM_DEVICE_DT_INST_GET(n), \
&paw32xx_data_##n, &paw32xx_cfg_##n, \
POST_KERNEL, CONFIG_INPUT_INIT_PRIORITY, \
NULL);
DT_INST_FOREACH_STATUS_OKAY(PAW32XX_INIT)
``` | /content/code_sandbox/drivers/input/input_paw32xx.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 3,294 |
```c
/*
*
*/
#define DT_DRV_COMPAT gpio_keys
#include <zephyr/device.h>
#include <zephyr/drivers/gpio.h>
#include <zephyr/input/input.h>
#include <zephyr/kernel.h>
#include <zephyr/logging/log.h>
#include <zephyr/pm/device.h>
#include <zephyr/pm/device_runtime.h>
#include <zephyr/sys/atomic.h>
LOG_MODULE_REGISTER(gpio_keys, CONFIG_INPUT_LOG_LEVEL);
struct gpio_keys_callback {
struct gpio_callback gpio_cb;
int8_t pin_state;
};
struct gpio_keys_pin_config {
/** GPIO specification from devicetree */
struct gpio_dt_spec spec;
/** Zephyr code from devicetree */
uint32_t zephyr_code;
};
struct gpio_keys_pin_data {
const struct device *dev;
struct gpio_keys_callback cb_data;
struct k_work_delayable work;
int8_t pin_state;
};
struct gpio_keys_config {
/** Debounce interval in milliseconds from devicetree */
uint32_t debounce_interval_ms;
const int num_keys;
const struct gpio_keys_pin_config *pin_cfg;
struct gpio_keys_pin_data *pin_data;
k_work_handler_t handler;
bool polling_mode;
};
struct gpio_keys_data {
#ifdef CONFIG_PM_DEVICE
atomic_t suspended;
#endif
};
/**
* Handle debounced gpio pin state.
*/
static void gpio_keys_poll_pin(const struct device *dev, int key_index)
{
const struct gpio_keys_config *cfg = dev->config;
const struct gpio_keys_pin_config *pin_cfg = &cfg->pin_cfg[key_index];
struct gpio_keys_pin_data *pin_data = &cfg->pin_data[key_index];
int new_pressed;
new_pressed = gpio_pin_get_dt(&pin_cfg->spec);
LOG_DBG("%s: pin_state=%d, new_pressed=%d, key_index=%d", dev->name,
pin_data->cb_data.pin_state, new_pressed, key_index);
/* If gpio changed, report the event */
if (new_pressed != pin_data->cb_data.pin_state) {
pin_data->cb_data.pin_state = new_pressed;
LOG_DBG("Report event %s %d, code=%d", dev->name, new_pressed,
pin_cfg->zephyr_code);
input_report_key(dev, pin_cfg->zephyr_code, new_pressed, true, K_FOREVER);
}
}
static __maybe_unused void gpio_keys_poll_pins(struct k_work *work)
{
struct k_work_delayable *dwork = k_work_delayable_from_work(work);
struct gpio_keys_pin_data *pin_data = CONTAINER_OF(dwork, struct gpio_keys_pin_data, work);
const struct device *dev = pin_data->dev;
const struct gpio_keys_config *cfg = dev->config;
#ifdef CONFIG_PM_DEVICE
struct gpio_keys_data *data = dev->data;
if (atomic_get(&data->suspended) == 1) {
return;
}
#endif
for (int i = 0; i < cfg->num_keys; i++) {
gpio_keys_poll_pin(dev, i);
}
k_work_reschedule(dwork, K_MSEC(cfg->debounce_interval_ms));
}
static __maybe_unused void gpio_keys_change_deferred(struct k_work *work)
{
struct k_work_delayable *dwork = k_work_delayable_from_work(work);
struct gpio_keys_pin_data *pin_data = CONTAINER_OF(dwork, struct gpio_keys_pin_data, work);
const struct device *dev = pin_data->dev;
const struct gpio_keys_config *cfg = dev->config;
int key_index = pin_data - (struct gpio_keys_pin_data *)cfg->pin_data;
#ifdef CONFIG_PM_DEVICE
struct gpio_keys_data *data = dev->data;
if (atomic_get(&data->suspended) == 1) {
return;
}
#endif
gpio_keys_poll_pin(dev, key_index);
}
static void gpio_keys_interrupt(const struct device *dev, struct gpio_callback *cbdata,
uint32_t pins)
{
struct gpio_keys_callback *keys_cb = CONTAINER_OF(
cbdata, struct gpio_keys_callback, gpio_cb);
struct gpio_keys_pin_data *pin_data = CONTAINER_OF(
keys_cb, struct gpio_keys_pin_data, cb_data);
const struct gpio_keys_config *cfg = pin_data->dev->config;
ARG_UNUSED(dev); /* GPIO device pointer. */
ARG_UNUSED(pins);
k_work_reschedule(&pin_data->work, K_MSEC(cfg->debounce_interval_ms));
}
static int gpio_keys_interrupt_configure(const struct gpio_dt_spec *gpio_spec,
struct gpio_keys_callback *cb, uint32_t zephyr_code)
{
int ret;
gpio_init_callback(&cb->gpio_cb, gpio_keys_interrupt, BIT(gpio_spec->pin));
ret = gpio_add_callback(gpio_spec->port, &cb->gpio_cb);
if (ret < 0) {
LOG_ERR("Could not set gpio callback");
return ret;
}
cb->pin_state = gpio_pin_get_dt(gpio_spec);
LOG_DBG("port=%s, pin=%d", gpio_spec->port->name, gpio_spec->pin);
ret = gpio_pin_interrupt_configure_dt(gpio_spec, GPIO_INT_EDGE_BOTH);
if (ret < 0) {
LOG_ERR("interrupt configuration failed: %d", ret);
return ret;
}
return 0;
}
static int gpio_keys_init(const struct device *dev)
{
const struct gpio_keys_config *cfg = dev->config;
struct gpio_keys_pin_data *pin_data = cfg->pin_data;
int ret;
for (int i = 0; i < cfg->num_keys; i++) {
const struct gpio_dt_spec *gpio = &cfg->pin_cfg[i].spec;
if (!gpio_is_ready_dt(gpio)) {
LOG_ERR("%s is not ready", gpio->port->name);
return -ENODEV;
}
ret = gpio_pin_configure_dt(gpio, GPIO_INPUT);
if (ret != 0) {
LOG_ERR("Pin %d configuration failed: %d", i, ret);
return ret;
}
pin_data[i].dev = dev;
k_work_init_delayable(&pin_data[i].work, cfg->handler);
if (cfg->polling_mode) {
continue;
}
ret = gpio_keys_interrupt_configure(&cfg->pin_cfg[i].spec,
&pin_data[i].cb_data,
cfg->pin_cfg[i].zephyr_code);
if (ret != 0) {
LOG_ERR("Pin %d interrupt configuration failed: %d", i, ret);
return ret;
}
}
if (cfg->polling_mode) {
/* use pin 0 work to poll all the pins periodically */
k_work_reschedule(&pin_data[0].work, K_MSEC(cfg->debounce_interval_ms));
}
ret = pm_device_runtime_enable(dev);
if (ret < 0) {
LOG_ERR("Failed to enable runtime power management");
return ret;
}
return 0;
}
#ifdef CONFIG_PM_DEVICE
static int gpio_keys_pm_action(const struct device *dev,
enum pm_device_action action)
{
const struct gpio_keys_config *cfg = dev->config;
struct gpio_keys_data *data = dev->data;
struct gpio_keys_pin_data *pin_data = cfg->pin_data;
int ret;
switch (action) {
case PM_DEVICE_ACTION_SUSPEND:
atomic_set(&data->suspended, 1);
for (int i = 0; i < cfg->num_keys; i++) {
const struct gpio_dt_spec *gpio = &cfg->pin_cfg[i].spec;
if (!cfg->polling_mode) {
ret = gpio_pin_interrupt_configure_dt(gpio, GPIO_INT_DISABLE);
if (ret < 0) {
LOG_ERR("interrupt configuration failed: %d", ret);
return ret;
}
}
ret = gpio_pin_configure_dt(gpio, GPIO_DISCONNECTED);
if (ret != 0) {
LOG_ERR("Pin %d configuration failed: %d", i, ret);
return ret;
}
}
return 0;
case PM_DEVICE_ACTION_RESUME:
atomic_set(&data->suspended, 0);
for (int i = 0; i < cfg->num_keys; i++) {
const struct gpio_dt_spec *gpio = &cfg->pin_cfg[i].spec;
ret = gpio_pin_configure_dt(gpio, GPIO_INPUT);
if (ret != 0) {
LOG_ERR("Pin %d configuration failed: %d", i, ret);
return ret;
}
if (cfg->polling_mode) {
k_work_reschedule(&pin_data[0].work,
K_MSEC(cfg->debounce_interval_ms));
} else {
ret = gpio_pin_interrupt_configure_dt(gpio, GPIO_INT_EDGE_BOTH);
if (ret < 0) {
LOG_ERR("interrupt configuration failed: %d", ret);
return ret;
}
}
}
return 0;
default:
return -ENOTSUP;
}
}
#endif
#define GPIO_KEYS_CFG_CHECK(node_id) \
BUILD_ASSERT(DT_NODE_HAS_PROP(node_id, zephyr_code), \
"zephyr-code must be specified to use the input-gpio-keys driver");
#define GPIO_KEYS_CFG_DEF(node_id) \
{ \
.spec = GPIO_DT_SPEC_GET(node_id, gpios), \
.zephyr_code = DT_PROP(node_id, zephyr_code), \
}
#define GPIO_KEYS_INIT(i) \
DT_INST_FOREACH_CHILD_STATUS_OKAY(i, GPIO_KEYS_CFG_CHECK); \
\
static const struct gpio_keys_pin_config gpio_keys_pin_config_##i[] = { \
DT_INST_FOREACH_CHILD_STATUS_OKAY_SEP(i, GPIO_KEYS_CFG_DEF, (,))}; \
\
static struct gpio_keys_pin_data \
gpio_keys_pin_data_##i[ARRAY_SIZE(gpio_keys_pin_config_##i)]; \
\
static const struct gpio_keys_config gpio_keys_config_##i = { \
.debounce_interval_ms = DT_INST_PROP(i, debounce_interval_ms), \
.num_keys = ARRAY_SIZE(gpio_keys_pin_config_##i), \
.pin_cfg = gpio_keys_pin_config_##i, \
.pin_data = gpio_keys_pin_data_##i, \
.handler = COND_CODE_1(DT_INST_PROP(i, polling_mode), \
(gpio_keys_poll_pins), (gpio_keys_change_deferred)), \
.polling_mode = DT_INST_PROP(i, polling_mode), \
}; \
\
static struct gpio_keys_data gpio_keys_data_##i; \
\
PM_DEVICE_DT_INST_DEFINE(i, gpio_keys_pm_action); \
\
DEVICE_DT_INST_DEFINE(i, &gpio_keys_init, PM_DEVICE_DT_INST_GET(i), \
&gpio_keys_data_##i, &gpio_keys_config_##i, \
POST_KERNEL, CONFIG_INPUT_INIT_PRIORITY, NULL);
DT_INST_FOREACH_STATUS_OKAY(GPIO_KEYS_INIT)
``` | /content/code_sandbox/drivers/input/input_gpio_keys.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 2,355 |
```unknown
# Cirque Pinnacle 1CA027 touch controller based device configuration options
#
config INPUT_PINNACLE
bool "Cirque Pinnacle 1CA027 Touch Controller Based Device"
default y
depends on DT_HAS_CIRQUE_PINNACLE_ENABLED
select GPIO
select I2C if $(dt_compat_on_bus,$(DT_COMPAT_CIRQUE_PINNACLE),i2c)
select SPI if $(dt_compat_on_bus,$(DT_COMPAT_CIRQUE_PINNACLE),spi)
help
Enable driver for Cirque Pinnacle 1CA027 tracked input device.
``` | /content/code_sandbox/drivers/input/Kconfig.pinnacle | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 123 |
```c
/*
*
*/
#include <stdlib.h>
#include <zephyr/device.h>
#include <zephyr/input/input_analog_axis.h>
#include <zephyr/input/input_analog_axis_settings.h>
#include <zephyr/logging/log.h>
#include <zephyr/settings/settings.h>
#include <zephyr/sys/printk.h>
LOG_MODULE_REGISTER(analog_axis_settings, CONFIG_INPUT_LOG_LEVEL);
#define ANALOG_AXIS_SETTINGS_PATH_MAX 32
#define MAX_AXES CONFIG_INPUT_ANALOG_AXIS_SETTINGS_MAX_AXES
static void analog_axis_calibration_log(const struct device *dev)
{
struct analog_axis_calibration cal;
int i;
for (i = 0; i < analog_axis_num_axes(dev); i++) {
analog_axis_calibration_get(dev, i, &cal);
LOG_INF("%s: ch: %d min: %d max: %d deadzone: %d",
dev->name, i, cal.in_min, cal.in_max, cal.in_deadzone);
}
}
static int analog_axis_calibration_load(const char *key, size_t len_rd,
settings_read_cb read_cb, void *cb_arg)
{
const struct device *dev;
struct analog_axis_calibration cal[MAX_AXES];
int axes;
char dev_name[ANALOG_AXIS_SETTINGS_PATH_MAX];
const char *next;
int nlen;
ssize_t len;
nlen = settings_name_next(key, &next);
if (nlen + 1 > sizeof(dev_name)) {
LOG_ERR("Setting name too long: %d", nlen);
return -EINVAL;
}
memcpy(dev_name, key, nlen);
dev_name[nlen] = '\0';
dev = device_get_binding(dev_name);
if (dev == NULL) {
LOG_ERR("Cannot restore: device %s not available", dev_name);
return -ENODEV;
}
len = read_cb(cb_arg, cal, sizeof(cal));
if (len < 0) {
LOG_ERR("Data restore error: %d", len);
}
axes = analog_axis_num_axes(dev);
if (len != sizeof(struct analog_axis_calibration) * axes) {
LOG_ERR("Invalid settings data length: %d, expected %d",
len, sizeof(struct analog_axis_calibration) * axes);
return -EIO;
}
for (int i = 0; i < axes; i++) {
analog_axis_calibration_set(dev, i, &cal[i]);
}
analog_axis_calibration_log(dev);
return 0;
}
SETTINGS_STATIC_HANDLER_DEFINE(analog_axis, "aa-cal", NULL,
analog_axis_calibration_load, NULL, NULL);
int analog_axis_calibration_save(const struct device *dev)
{
struct analog_axis_calibration cal[MAX_AXES];
int axes;
char path[ANALOG_AXIS_SETTINGS_PATH_MAX];
int ret;
analog_axis_calibration_log(dev);
ret = snprintk(path, sizeof(path), "aa-cal/%s", dev->name);
if (ret < 0) {
return -EINVAL;
}
axes = analog_axis_num_axes(dev);
for (int i = 0; i < axes; i++) {
analog_axis_calibration_get(dev, i, &cal[i]);
}
ret = settings_save_one(path, &cal[0],
sizeof(struct analog_axis_calibration) * axes);
if (ret < 0) {
LOG_ERR("Settings save errord: %d", ret);
return ret;
}
return 0;
}
``` | /content/code_sandbox/drivers/input/input_analog_axis_settings.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 719 |
```unknown
config INPUT_PAW32XX
bool "PAW32xx ultra low power wireless mouse chip"
default y
depends on DT_HAS_PIXART_PAW32XX_ENABLED
select SPI
help
PAW32XX low power laser mouse sensor input driver
``` | /content/code_sandbox/drivers/input/Kconfig.paw32xx | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 56 |
```c
/*
*
*/
/* Address by default is 0x55 */
#define DT_DRV_COMPAT sitronix_cf1133
#include <zephyr/drivers/gpio.h>
#include <zephyr/drivers/i2c.h>
#include <zephyr/input/input.h>
#include <zephyr/logging/log.h>
#include <stdbool.h>
LOG_MODULE_REGISTER(cf1133, CONFIG_INPUT_LOG_LEVEL);
/* cf1133 used registers */
#define FIRMWARE_VERSION 0x0
#define STATUS_REG 0x1
#define DEVICE_CONTROL_REG 0x2
#define TIMEOUT_TO_IDLE_REG 0x3
#define XY_RESOLUTION_HIGH 0x4
#define X_RESOLUTION_LOW 0x5
#define Y_RESOLUTION_LOW 0x6
#define DEVICE_CONTROL_REG2 0x09
#define FIRMWARE_REVISION_3 0x0C
#define FIRMWARE_REVISION_2 0x0D
#define FIRMWARE_REVISION_1 0x0E
#define FIRMWARE_REVISION_0 0x0F
#define FINGERS 0x10
#define KEYS_REG 0x11
#define XY0_COORD_H 0x12
#define X0_COORD_L 0x13
#define Y0_COORD_L 0x14
#define I2C_PROTOCOL 0x3E
#define MAX_NUM_TOUCHES 0x3F
#define DATA_0_HIGH 0x40
#define DATA_0_LOW 0x41
#define MISC_CONTROL 0xF1
#define SMART_WAKE_UP_REG 0xF2
#define CHIP_ID 0xF4
#define PAGE_REG 0xFF
/* Constants */
#define SUPPORTED_POINT 0x1
#define PIXEL_DATA_LENGTH_B 0x3
#define PIXEL_DATA_LENGTH_A 0x4
#define SITRONIX_RESERVED_TYPE_0 0x0
#define SITRONIX_A_TYPE 0x1
#define SITRONIX_B_TYPE 0x2
/* Mask */
#define ONE_D_SENSING_CONTROL_SHFT GENMASK(1, 1)
#define ONE_D_SENSING_CONTROL_BMSK GENMASK(1, 0)
#define I2C_PROTOCOL_BMSK GENMASK(1, 0)
#define TOUCH_POINT_VALID_MSK GENMASK(7, 7)
/* Offset for coordinates registers */
#define XY_COORD_H 0x0
#define X_COORD_L 0x1
#define Y_COORD_L 0x2
/* CF1133 configuration (DT) */
struct cf1133_config {
/** I2C bus. */
struct i2c_dt_spec bus;
#ifdef CONFIG_INPUT_CF1133_INTERRUPT
/** Interrupt GPIO information. */
struct gpio_dt_spec int_gpio;
#endif
};
/* CF1133 data */
struct cf1133_data {
/** Device pointer. */
const struct device *dev;
/** Work queue (for deferred read). */
struct k_work work;
#ifdef CONFIG_INPUT_CF1133_INTERRUPT
/** Interrupt GPIO callback. */
struct gpio_callback int_gpio_cb;
#else
/* Timer (polling mode) */
struct k_timer timer;
#endif
/* Last pressed state */
uint8_t pressed_old : 1;
uint8_t pressed : 1;
int resolution_x;
int resolution_y;
uint8_t touch_protocol_type;
uint8_t pixel_length;
uint8_t chip_id;
};
static int cf1133_get_chip_id(const struct device *dev)
{
int ret;
uint8_t buffer[3];
uint8_t num_x;
uint8_t num_y;
const struct cf1133_config *config = dev->config;
struct cf1133_data *data = dev->data;
ret = i2c_burst_read_dt(&config->bus, CHIP_ID, buffer, sizeof(buffer));
if (ret < 0) {
LOG_ERR("Read burst failed: %d", ret);
return ret;
}
if (buffer[0] == 0) {
if (buffer[1] + buffer[2] > 32) {
data->chip_id = 2;
} else {
data->chip_id = 0;
}
} else {
data->chip_id = buffer[0];
}
num_x = buffer[1];
num_y = buffer[2];
LOG_DBG("Chip ID = %d, num_x = %d, num_y = %d", data->chip_id, num_x, num_y);
return 0;
}
static int cf1133_get_protocol_type(const struct device *dev)
{
int ret;
uint8_t buffer;
uint8_t sensing_mode;
const struct cf1133_config *config = dev->config;
struct cf1133_data *data = dev->data;
if (data->chip_id <= 3) {
ret = i2c_reg_read_byte_dt(&config->bus, I2C_PROTOCOL, &buffer);
if (ret < 0) {
LOG_ERR("read i2c protocol failed: %d", ret);
return ret;
}
data->touch_protocol_type = FIELD_GET(I2C_PROTOCOL_BMSK, buffer);
LOG_DBG("i2c protocol = %d", data->touch_protocol_type);
sensing_mode = FIELD_GET(ONE_D_SENSING_CONTROL_BMSK << ONE_D_SENSING_CONTROL_SHFT,
buffer);
LOG_DBG("sensing mode = %d", sensing_mode);
} else {
data->touch_protocol_type = SITRONIX_A_TYPE;
LOG_DBG("i2c protocol = %d", data->touch_protocol_type);
ret = i2c_reg_read_byte_dt(&config->bus, 0xf0, &buffer);
if (ret < 0) {
LOG_ERR("read sensing mode failed: (%d)", ret);
return ret;
}
sensing_mode = FIELD_GET(ONE_D_SENSING_CONTROL_BMSK, buffer);
LOG_DBG("sensing mode = %d", sensing_mode);
}
return 0;
}
static int cf1133_ts_init(const struct device *dev)
{
struct cf1133_data *data = dev->data;
int ret;
/* Get device status before use to do at least once */
ret = cf1133_get_chip_id(dev);
if (ret < 0) {
LOG_ERR("Read chip id failed: %d", ret);
return ret;
}
ret = cf1133_get_protocol_type(dev);
if (ret < 0) {
LOG_ERR("Read protocol failed: %d", ret);
return ret;
}
if (data->touch_protocol_type == SITRONIX_A_TYPE) {
data->pixel_length = PIXEL_DATA_LENGTH_A;
} else {
data->pixel_length = PIXEL_DATA_LENGTH_B;
}
LOG_DBG("Pixel length: %d", data->pixel_length);
return ret;
}
static int cf1133_process(const struct device *dev)
{
const struct cf1133_config *config = dev->config;
struct cf1133_data *data = dev->data;
uint16_t y;
uint16_t x;
int ret;
uint8_t buffer[1 + SUPPORTED_POINT * PIXEL_DATA_LENGTH_A];
/* Coordinates are retrieved for one valid touch point detected*/
ret = i2c_burst_read_dt(&config->bus, KEYS_REG, buffer,
1 + SUPPORTED_POINT * data->pixel_length);
if (ret < 0) {
LOG_ERR("Read coordinates failed: %d", ret);
return ret;
}
/* Coordinates for one valid touch point */
if (buffer[1 + XY_COORD_H] & TOUCH_POINT_VALID_MSK) {
x = (uint16_t)(buffer[1 + XY_COORD_H] & 0x70) << 4 | buffer[1 + X_COORD_L];
y = (uint16_t)(buffer[1 + XY_COORD_H] & 0x07) << 8 | buffer[1 + Y_COORD_L];
data->pressed = true;
if (!data->pressed_old) {
/* Finger pressed */
input_report_abs(dev, INPUT_ABS_X, x, false, K_FOREVER);
input_report_abs(dev, INPUT_ABS_Y, y, false, K_FOREVER);
input_report_key(dev, INPUT_BTN_TOUCH, 1, true, K_FOREVER);
LOG_DBG("Finger is touching x = %i y = %i", x, y);
} else if (data->pressed_old) {
/* Continuous pressed */
input_report_abs(dev, INPUT_ABS_X, x, false, K_FOREVER);
input_report_abs(dev, INPUT_ABS_Y, y, false, K_FOREVER);
LOG_DBG("Finger keeps touching x = %i y = %i", x, y);
}
} else {
data->pressed = false;
if (data->pressed_old) {
/* Finger removed */
input_report_key(dev, INPUT_BTN_TOUCH, 0, true, K_FOREVER);
LOG_DBG("Finger is removed");
}
}
data->pressed_old = data->pressed;
return 0;
}
static void cf1133_work_handler(struct k_work *work)
{
struct cf1133_data *data = CONTAINER_OF(work, struct cf1133_data, work);
cf1133_process(data->dev);
}
#ifdef CONFIG_INPUT_CF1133_INTERRUPT
static void cf1133_isr_handler(const struct device *dev, struct gpio_callback *cb, uint32_t pins)
{
struct cf1133_data *data = CONTAINER_OF(cb, struct cf1133_data, int_gpio_cb);
k_work_submit(&data->work);
}
#else
static void cf1133_timer_handler(struct k_timer *timer)
{
struct cf1133_data *data = CONTAINER_OF(timer, struct cf1133_data, timer);
k_work_submit(&data->work);
}
#endif
static int cf1133_init(const struct device *dev)
{
const struct cf1133_config *config = dev->config;
struct cf1133_data *data = dev->data;
int ret;
if (!i2c_is_ready_dt(&config->bus)) {
LOG_ERR("I2C controller device not ready");
return -ENODEV;
}
data->dev = dev;
k_work_init(&data->work, cf1133_work_handler);
#ifdef CONFIG_INPUT_CF1133_INTERRUPT
LOG_DBG("Int conf for TS gpio: %d", &config->int_gpio);
if (!gpio_is_ready_dt(&config->int_gpio)) {
LOG_ERR("Interrupt GPIO controller device not ready");
return -ENODEV;
}
ret = gpio_pin_configure_dt(&config->int_gpio, GPIO_INPUT);
if (ret < 0) {
LOG_ERR("Could not configure interrupt GPIO pin");
return ret;
}
gpio_init_callback(&data->int_gpio_cb, cf1133_isr_handler, BIT(config->int_gpio.pin));
ret = gpio_add_callback(config->int_gpio.port, &data->int_gpio_cb);
if (ret < 0) {
LOG_ERR("Could not set gpio callback");
return ret;
}
ret = gpio_pin_interrupt_configure_dt(&config->int_gpio, GPIO_INT_EDGE_TO_ACTIVE);
if (ret < 0) {
LOG_ERR("Could not configure interrupt GPIO interrupt.");
return ret;
}
#else
LOG_DBG("Timer Mode");
k_timer_init(&data->timer, cf1133_timer_handler, NULL);
k_timer_start(&data->timer, K_MSEC(CONFIG_INPUT_CF1133_PERIOD_MS),
K_MSEC(CONFIG_INPUT_CF1133_PERIOD_MS));
#endif
ret = cf1133_ts_init(dev);
if (ret < 0) {
LOG_ERR("Init information of sensor failed: %d", ret);
return ret;
}
return 0;
}
#define CF1133_INIT(index) \
static const struct cf1133_config cf1133_config_##index = { \
.bus = I2C_DT_SPEC_INST_GET(index), \
IF_ENABLED(CONFIG_INPUT_CF1133_INTERRUPT, \
(.int_gpio = GPIO_DT_SPEC_INST_GET(index, int_gpios), \
)) \
}; \
static struct cf1133_data cf1133_data_##index; \
\
DEVICE_DT_INST_DEFINE(index, cf1133_init, NULL, &cf1133_data_##index, \
&cf1133_config_##index, POST_KERNEL, \
CONFIG_INPUT_INIT_PRIORITY, NULL);
DT_INST_FOREACH_STATUS_OKAY(CF1133_INIT);
``` | /content/code_sandbox/drivers/input/input_cf1133.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 2,668 |
```objective-c
/*
*
*/
#ifndef ZEPHYR_DRIVERS_INPUT_LINUX_EVDEV_BOTTOM_H_
#define ZEPHYR_DRIVERS_INPUT_LINUX_EVDEV_BOTTOM_H_
#include <stdint.h>
#define NATIVE_LINUX_EVDEV_NO_DATA INT32_MIN
int linux_evdev_read(int fd, uint16_t *type, uint16_t *code, int32_t *value);
int linux_evdev_open(const char *path);
#endif /* ZEPHYR_DRIVERS_INPUT_LINUX_EVDEV_BOTTOM_H_ */
``` | /content/code_sandbox/drivers/input/linux_evdev_bottom.h | objective-c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 101 |
```unknown
menuconfig INPUT_CF1133
bool "CF1133 capacitive touch panel driver"
default y
depends on DT_HAS_SITRONIX_CF1133_ENABLED
select I2C
help
Enable driver for Sitronix capacitive touch panel
controller. This driver should support CF1133.
if INPUT_CF1133
config INPUT_CF1133_INTERRUPT
bool "Interrupt"
default y
help
Enable interrupt support (requires all instances
of CF1133 have the INT gpio connected).
config INPUT_CF1133_PERIOD_MS
int "Sample period"
depends on !INPUT_CF1133_INTERRUPT
default 10
help
Sample period in milliseconds when in polling mode.
endif # INPUT_CF1133
``` | /content/code_sandbox/drivers/input/Kconfig.cf1133 | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 155 |
```c
/*
*
*/
#define DT_DRV_COMPAT hynitron_cst816s
#include <zephyr/sys/byteorder.h>
#include <zephyr/input/input.h>
#include <zephyr/drivers/i2c.h>
#include <zephyr/drivers/gpio.h>
#include <zephyr/logging/log.h>
#include <zephyr/dt-bindings/input/cst816s-gesture-codes.h>
LOG_MODULE_REGISTER(cst816s, CONFIG_INPUT_LOG_LEVEL);
#define CST816S_CHIP_ID1 0xB4
#define CST816S_CHIP_ID2 0xB5
#define CST816S_CHIP_ID3 0xB6
#define CST816S_REG_DATA 0x00
#define CST816S_REG_GESTURE_ID 0x01
#define CST816S_REG_FINGER_NUM 0x02
#define CST816S_REG_XPOS_H 0x03
#define CST816S_REG_XPOS_L 0x04
#define CST816S_REG_YPOS_H 0x05
#define CST816S_REG_YPOS_L 0x06
#define CST816S_REG_BPC0H 0xB0
#define CST816S_REG_BPC0L 0xB1
#define CST816S_REG_BPC1H 0xB2
#define CST816S_REG_BPC1L 0xB3
#define CST816S_REG_POWER_MODE 0xA5
#define CST816S_REG_CHIP_ID 0xA7
#define CST816S_REG_PROJ_ID 0xA8
#define CST816S_REG_FW_VERSION 0xA9
#define CST816S_REG_MOTION_MASK 0xEC
#define CST816S_REG_IRQ_PULSE_WIDTH 0xED
#define CST816S_REG_NOR_SCAN_PER 0xEE
#define CST816S_REG_MOTION_S1_ANGLE 0xEF
#define CST816S_REG_LP_SCAN_RAW1H 0xF0
#define CST816S_REG_LP_SCAN_RAW1L 0xF1
#define CST816S_REG_LP_SCAN_RAW2H 0xF2
#define CST816S_REG_LP_SCAN_RAW2L 0xF3
#define CST816S_REG_LP_AUTO_WAKEUP_TIME 0xF4
#define CST816S_REG_LP_SCAN_TH 0xF5
#define CST816S_REG_LP_SCAN_WIN 0xF6
#define CST816S_REG_LP_SCAN_FREQ 0xF7
#define CST816S_REG_LP_SCAN_I_DAC 0xF8
#define CST816S_REG_AUTOSLEEP_TIME 0xF9
#define CST816S_REG_IRQ_CTL 0xFA
#define CST816S_REG_DEBOUNCE_TIME 0xFB
#define CST816S_REG_LONG_PRESS_TIME 0xFC
#define CST816S_REG_IOCTL 0xFD
#define CST816S_REG_DIS_AUTO_SLEEP 0xFE
#define CST816S_MOTION_EN_CON_LR BIT(2)
#define CST816S_MOTION_EN_CON_UR BIT(1)
#define CST816S_MOTION_EN_DCLICK BIT(0)
#define CST816S_IRQ_EN_TEST BIT(7)
#define CST816S_IRQ_EN_TOUCH BIT(6)
#define CST816S_IRQ_EN_CHANGE BIT(5)
#define CST816S_IRQ_EN_MOTION BIT(4)
#define CST816S_IRQ_ONCE_WLP BIT(0)
#define CST816S_IOCTL_SOFT_RTS BIT(2)
#define CST816S_IOCTL_IIC_OD BIT(1)
#define CST816S_IOCTL_EN_1V8 BIT(0)
#define CST816S_POWER_MODE_SLEEP (0x03)
#define CST816S_POWER_MODE_EXPERIMENTAL (0x05)
#define CST816S_EVENT_BITS_POS (0x06)
#define CST816S_RESET_DELAY (5) /* in ms */
#define CST816S_WAIT_DELAY (50) /* in ms */
#define EVENT_PRESS_DOWN 0x00U
#define EVENT_LIFT_UP 0x01U
#define EVENT_CONTACT 0x02U
#define EVENT_NONE 0x03U
/** cst816s configuration (DT). */
struct cst816s_config {
struct i2c_dt_spec i2c;
const struct gpio_dt_spec rst_gpio;
#ifdef CONFIG_INPUT_CST816S_INTERRUPT
const struct gpio_dt_spec int_gpio;
#endif
};
/** cst816s data. */
struct cst816s_data {
/** Device pointer. */
const struct device *dev;
/** Work queue (for deferred read). */
struct k_work work;
#ifdef CONFIG_INPUT_CST816S_INTERRUPT
/** Interrupt GPIO callback. */
struct gpio_callback int_gpio_cb;
#else
/** Timer (polling mode). */
struct k_timer timer;
#endif
};
static int cst816s_process(const struct device *dev)
{
const struct cst816s_config *cfg = dev->config;
int r;
uint8_t event;
uint16_t row, col;
bool pressed;
uint16_t x;
uint16_t y;
#ifdef CONFIG_INPUT_CST816S_EV_DEVICE
uint8_t gesture;
r = i2c_burst_read_dt(&cfg->i2c, CST816S_REG_GESTURE_ID, &gesture, sizeof(gesture));
if (r < 0) {
LOG_ERR("Could not read gesture-ID data");
return r;
}
#endif
r = i2c_burst_read_dt(&cfg->i2c, CST816S_REG_XPOS_H, (uint8_t *)&x, sizeof(x));
if (r < 0) {
LOG_ERR("Could not read x data");
return r;
}
r = i2c_burst_read_dt(&cfg->i2c, CST816S_REG_YPOS_H, (uint8_t *)&y, sizeof(y));
if (r < 0) {
LOG_ERR("Could not read y data");
return r;
}
col = sys_be16_to_cpu(x) & 0x0fff;
row = sys_be16_to_cpu(y) & 0x0fff;
event = (x & 0xff) >> CST816S_EVENT_BITS_POS;
pressed = (event == EVENT_PRESS_DOWN) || (event == EVENT_CONTACT);
LOG_DBG("event: %d, row: %d, col: %d", event, row, col);
if (pressed) {
input_report_abs(dev, INPUT_ABS_X, col, false, K_FOREVER);
input_report_abs(dev, INPUT_ABS_Y, row, false, K_FOREVER);
input_report_key(dev, INPUT_BTN_TOUCH, 1, true, K_FOREVER);
} else {
input_report_key(dev, INPUT_BTN_TOUCH, 0, true, K_FOREVER);
}
#ifdef CONFIG_INPUT_CST816S_EV_DEVICE
/* Also put the custom touch gestures into the input queue,
* some applications may want to process it
*/
LOG_DBG("gesture: %d", gesture);
if (gesture != CST816S_GESTURE_CODE_NONE) {
input_report(dev, INPUT_EV_DEVICE, (uint16_t)gesture, 0, true, K_FOREVER);
}
#endif
return r;
}
static void cst816s_work_handler(struct k_work *work)
{
struct cst816s_data *data = CONTAINER_OF(work, struct cst816s_data, work);
cst816s_process(data->dev);
}
#ifdef CONFIG_INPUT_CST816S_INTERRUPT
static void cst816s_isr_handler(const struct device *dev, struct gpio_callback *cb, uint32_t pins)
{
struct cst816s_data *data = CONTAINER_OF(cb, struct cst816s_data, int_gpio_cb);
k_work_submit(&data->work);
}
#else
static void cst816s_timer_handler(struct k_timer *timer)
{
struct cst816s_data *data = CONTAINER_OF(timer, struct cst816s_data, timer);
k_work_submit(&data->work);
}
#endif
static void cst816s_chip_reset(const struct device *dev)
{
const struct cst816s_config *config = dev->config;
int ret;
if (gpio_is_ready_dt(&config->rst_gpio)) {
ret = gpio_pin_configure_dt(&config->rst_gpio, GPIO_OUTPUT_ACTIVE);
if (ret < 0) {
LOG_ERR("Could not configure reset GPIO pin");
return;
}
k_msleep(CST816S_RESET_DELAY);
gpio_pin_set_dt(&config->rst_gpio, 0);
k_msleep(CST816S_WAIT_DELAY);
}
}
static int cst816s_chip_init(const struct device *dev)
{
const struct cst816s_config *cfg = dev->config;
int ret = 0;
uint8_t chip_id = 0;
cst816s_chip_reset(dev);
if (!device_is_ready(cfg->i2c.bus)) {
LOG_ERR("I2C bus %s not ready", cfg->i2c.bus->name);
return -ENODEV;
}
ret = i2c_reg_read_byte_dt(&cfg->i2c, CST816S_REG_CHIP_ID, &chip_id);
if (ret < 0) {
LOG_ERR("failed reading chip id");
return ret;
}
if ((chip_id != CST816S_CHIP_ID1) && (chip_id != CST816S_CHIP_ID2) &&
(chip_id != CST816S_CHIP_ID3)) {
LOG_ERR("CST816S wrong chip id: returned 0x%x", chip_id);
return -ENODEV;
}
ret = i2c_reg_update_byte_dt(&cfg->i2c, CST816S_REG_IRQ_CTL,
CST816S_IRQ_EN_TOUCH | CST816S_IRQ_EN_CHANGE,
CST816S_IRQ_EN_TOUCH | CST816S_IRQ_EN_CHANGE);
if (ret < 0) {
LOG_ERR("Could not enable irq");
return ret;
}
return ret;
}
static int cst816s_init(const struct device *dev)
{
struct cst816s_data *data = dev->data;
int ret;
data->dev = dev;
k_work_init(&data->work, cst816s_work_handler);
ret = cst816s_chip_init(dev);
if (ret < 0) {
return ret;
}
#ifdef CONFIG_INPUT_CST816S_INTERRUPT
const struct cst816s_config *config = dev->config;
if (!gpio_is_ready_dt(&config->int_gpio)) {
LOG_ERR("GPIO port %s not ready", config->int_gpio.port->name);
return -ENODEV;
}
ret = gpio_pin_configure_dt(&config->int_gpio, GPIO_INPUT);
if (ret < 0) {
LOG_ERR("Could not configure interrupt GPIO pin");
return ret;
}
ret = gpio_pin_interrupt_configure_dt(&config->int_gpio, GPIO_INT_EDGE_TO_ACTIVE);
if (ret < 0) {
LOG_ERR("Could not configure interrupt GPIO interrupt.");
return ret;
}
gpio_init_callback(&data->int_gpio_cb, cst816s_isr_handler, BIT(config->int_gpio.pin));
ret = gpio_add_callback(config->int_gpio.port, &data->int_gpio_cb);
if (ret < 0) {
LOG_ERR("Could not set gpio callback");
return ret;
}
#else
k_timer_init(&data->timer, cst816s_timer_handler, NULL);
k_timer_start(&data->timer, K_MSEC(CONFIG_INPUT_CST816S_PERIOD),
K_MSEC(CONFIG_INPUT_CST816S_PERIOD));
#endif
return ret;
}
#define CST816S_DEFINE(index) \
static const struct cst816s_config cst816s_config_##index = { \
.i2c = I2C_DT_SPEC_INST_GET(index), \
COND_CODE_1(CONFIG_INPUT_CST816S_INTERRUPT, \
(.int_gpio = GPIO_DT_SPEC_INST_GET(index, irq_gpios),), ()) \
.rst_gpio = GPIO_DT_SPEC_INST_GET_OR(index, rst_gpios, {}), \
}; \
static struct cst816s_data cst816s_data_##index; \
DEVICE_DT_INST_DEFINE(index, cst816s_init, NULL, &cst816s_data_##index, \
&cst816s_config_##index, POST_KERNEL, CONFIG_INPUT_INIT_PRIORITY, \
NULL);
DT_INST_FOREACH_STATUS_OKAY(CST816S_DEFINE)
``` | /content/code_sandbox/drivers/input/input_cst816s.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 2,604 |
```c
/*
*
*/
#define DT_DRV_COMPAT cirque_pinnacle
#include <zephyr/device.h>
#include <zephyr/drivers/gpio.h>
#if DT_ANY_INST_ON_BUS_STATUS_OKAY(i2c)
#include <zephyr/drivers/i2c.h>
#endif
#if DT_ANY_INST_ON_BUS_STATUS_OKAY(spi)
#include <zephyr/drivers/spi.h>
#endif
#include <zephyr/init.h>
#include <zephyr/input/input.h>
#include <zephyr/kernel.h>
#include <zephyr/logging/log.h>
#include <zephyr/sys/util.h>
LOG_MODULE_REGISTER(pinnacle, CONFIG_INPUT_LOG_LEVEL);
/*
* Register Access Protocol Standard Registers.
* Standard registers have 5-bit addresses, BIT[4:0], that range from
* 0x00 to 0x1F. For reading, a register address has to be combined with
* 0xA0 for reading and 0x80 for writing bits, BIT[7:5].
*/
#define PINNACLE_REG_FIRMWARE_ID 0x00 /* R */
#define PINNACLE_REG_FIRMWARE_VERSION 0x01 /* R */
#define PINNACLE_REG_STATUS1 0x02 /* R/W */
#define PINNACLE_REG_SYS_CONFIG1 0x03 /* R/W */
#define PINNACLE_REG_FEED_CONFIG1 0x04 /* R/W */
#define PINNACLE_REG_FEED_CONFIG2 0x05 /* R/W */
#define PINNACLE_REG_FEED_CONFIG3 0x06 /* R/W */
#define PINNACLE_REG_CAL_CONFIG1 0x07 /* R/W */
#define PINNACLE_REG_PS2_AUX_CONTROL 0x08 /* R/W */
#define PINNACLE_REG_SAMPLE_RATE 0x09 /* R/W */
#define PINNACLE_REG_Z_IDLE 0x0A /* R/W */
#define PINNACLE_REG_Z_SCALER 0x0B /* R/W */
#define PINNACLE_REG_SLEEP_INTERVAL 0x0C /* R/W */
#define PINNACLE_REG_SLEEP_TIMER 0x0D /* R/W */
#define PINNACLE_REG_EMI_THRESHOLD 0x0E /* R/W */
#define PINNACLE_REG_PACKET_BYTE0 0x12 /* R */
#define PINNACLE_REG_PACKET_BYTE1 0x13 /* R */
#define PINNACLE_REG_PACKET_BYTE2 0x14 /* R */
#define PINNACLE_REG_PACKET_BYTE3 0x15 /* R */
#define PINNACLE_REG_PACKET_BYTE4 0x16 /* R */
#define PINNACLE_REG_PACKET_BYTE5 0x17 /* R */
#define PINNACLE_REG_GPIO_A_CTRL 0x18 /* R/W */
#define PINNACLE_REG_GPIO_A_DATA 0x19 /* R/W */
#define PINNACLE_REG_GPIO_B_CTRL_DATA 0x1A /* R/W */
/* Value of the extended register */
#define PINNACLE_REG_ERA_VALUE 0x1B /* R/W */
/* High byte BIT[15:8] of the 16 bit extended register */
#define PINNACLE_REG_ERA_ADDR_HIGH 0x1C /* R/W */
/* Low byte BIT[7:0] of the 16 bit extended register */
#define PINNACLE_REG_ERA_ADDR_LOW 0x1D /* R/W */
#define PINNACLE_REG_ERA_CTRL 0x1E /* R/W */
#define PINNACLE_REG_PRODUCT_ID 0x1F /* R */
/* Extended Register Access */
#define PINNACLE_ERA_REG_CONFIG 0x0187 /* R/W */
/* Firmware ASIC ID value */
#define PINNACLE_FIRMWARE_ID 0x07
/* Status1 definition */
#define PINNACLE_STATUS1_SW_DR BIT(2)
#define PINNACLE_STATUS1_SW_CC BIT(3)
/* SysConfig1 definition */
#define PINNACLE_SYS_CONFIG1_RESET BIT(0)
#define PINNACLE_SYS_CONFIG1_SHUTDOWN BIT(1)
#define PINNACLE_SYS_CONFIG1_LOW_POWER_MODE BIT(2)
/* FeedConfig1 definition */
#define PINNACLE_FEED_CONFIG1_FEED_ENABLE BIT(0)
#define PINNACLE_FEED_CONFIG1_DATA_MODE_ABSOLUTE BIT(1)
#define PINNACLE_FEED_CONFIG1_FILTER_DISABLE BIT(2)
#define PINNACLE_FEED_CONFIG1_X_DISABLE BIT(3)
#define PINNACLE_FEED_CONFIG1_Y_DISABLE BIT(4)
#define PINNACLE_FEED_CONFIG1_X_INVERT BIT(6)
#define PINNACLE_FEED_CONFIG1_Y_INVERT BIT(7)
/* X max to 0 */
#define PINNACLE_FEED_CONFIG1_X_DATA_INVERT BIT(6)
/* Y max to 0 */
#define PINNACLE_FEED_CONFIG1_Y_DATA_INVERT BIT(7)
/* FeedConfig2 definition */
#define PINNACLE_FEED_CONFIG2_INTELLIMOUSE_ENABLE BIT(0)
#define PINNACLE_FEED_CONFIG2_ALL_TAPS_DISABLE BIT(1)
#define PINNACLE_FEED_CONFIG2_SECONDARY_TAP_DISABLE BIT(2)
#define PINNACLE_FEED_CONFIG2_SCROLL_DISABLE BIT(3)
#define PINNACLE_FEED_CONFIG2_GLIDE_EXTEND_DISABLE BIT(4)
/* 90 degrees rotation */
#define PINNACLE_FEED_CONFIG2_SWAP_X_AND_Y BIT(7)
/* Relative position status in PacketByte0 */
#define PINNACLE_PACKET_BYTE0_BTN_PRIMARY BIT(0)
#define PINNACLE_PACKET_BYTE0_BTN_SECONDRY BIT(1)
/* Extended Register Access Control */
#define PINNACLE_ERA_CTRL_READ BIT(0)
#define PINNACLE_ERA_CTRL_WRITE BIT(1)
#define PINNACLE_ERA_CTRL_READ_AUTO_INC BIT(2)
#define PINNACLE_ERA_CTRL_WRITE_AUTO_INC BIT(3)
/* Asserting both BIT(1) and BIT(0) means WRITE/Verify */
#define PINNACLE_ERA_CTRL_WRITE_VERIFY (BIT(1) | BIT(0))
#define PINNACLE_ERA_CTRL_COMPLETE 0x00
/* Extended Register Access Config */
#define PINNACLE_ERA_CONFIG_ADC_ATTENUATION_X1 0x00
#define PINNACLE_ERA_CONFIG_ADC_ATTENUATION_X2 0x40
#define PINNACLE_ERA_CONFIG_ADC_ATTENUATION_X3 0x80
#define PINNACLE_ERA_CONFIG_ADC_ATTENUATION_X4 0xC0
/*
* Delay and retry count for waiting completion of calibration with 200 ms of
* timeout.
*/
#define PINNACLE_CALIBRATION_AWAIT_DELAY_POLL_US 50000
#define PINNACLE_CALIBRATION_AWAIT_RETRY_COUNT 4
/*
* Delay and retry count for waiting completion of ERA command with 50 ms of
* timeout.
*/
#define PINNACLE_ERA_AWAIT_DELAY_POLL_US 10000
#define PINNACLE_ERA_AWAIT_RETRY_COUNT 5
/* Special definitions */
#define PINNACLE_SPI_FB 0xFB /* Filler byte */
#define PINNACLE_SPI_FC 0xFC /* Auto-increment byte */
/* Read and write masks */
#define PINNACLE_READ_MSK 0xA0
#define PINNACLE_WRITE_MSK 0x80
/* Read and write register addresses */
#define PINNACLE_READ_REG(addr) (PINNACLE_READ_MSK | addr)
#define PINNACLE_WRITE_REG(addr) (PINNACLE_WRITE_MSK | addr)
struct pinnacle_bus {
union {
#if DT_ANY_INST_ON_BUS_STATUS_OKAY(i2c)
struct i2c_dt_spec i2c;
#endif
#if DT_ANY_INST_ON_BUS_STATUS_OKAY(spi)
struct spi_dt_spec spi;
#endif
};
bool (*is_ready)(const struct pinnacle_bus *bus);
int (*write)(const struct pinnacle_bus *bus, uint8_t address, uint8_t value);
int (*seq_write)(const struct pinnacle_bus *bus, uint8_t *address, uint8_t *value,
uint8_t count);
int (*read)(const struct pinnacle_bus *bus, uint8_t address, uint8_t *value);
int (*seq_read)(const struct pinnacle_bus *bus, uint8_t address, uint8_t *data,
uint8_t count);
};
enum pinnacle_sensitivity {
PINNACLE_SENSITIVITY_X1,
PINNACLE_SENSITIVITY_X2,
PINNACLE_SENSITIVITY_X3,
PINNACLE_SENSITIVITY_X4,
};
struct pinnacle_config {
const struct pinnacle_bus bus;
struct gpio_dt_spec dr_gpio;
enum pinnacle_sensitivity sensitivity;
bool relative_mode;
uint8_t idle_packets_count;
bool clipping_enabled;
bool scaling_enabled;
bool invert_x;
bool invert_y;
bool primary_tap_enabled;
bool swap_xy;
uint16_t active_range_x_min;
uint16_t active_range_x_max;
uint16_t active_range_y_min;
uint16_t active_range_y_max;
uint16_t resolution_x;
uint16_t resolution_y;
};
union pinnacle_sample {
struct {
uint16_t abs_x;
uint16_t abs_y;
uint8_t abs_z;
};
struct {
int16_t rel_x;
int16_t rel_y;
bool btn_primary;
};
};
struct pinnacle_data {
union pinnacle_sample sample;
const struct device *dev;
struct gpio_callback dr_cb_data;
struct k_work work;
};
static inline bool pinnacle_bus_is_ready(const struct device *dev)
{
const struct pinnacle_config *config = dev->config;
return config->bus.is_ready(&config->bus);
}
static inline int pinnacle_write(const struct device *dev, uint8_t address, uint8_t value)
{
const struct pinnacle_config *config = dev->config;
return config->bus.write(&config->bus, address, value);
}
static inline int pinnacle_seq_write(const struct device *dev, uint8_t *address, uint8_t *value,
uint8_t count)
{
const struct pinnacle_config *config = dev->config;
return config->bus.seq_write(&config->bus, address, value, count);
}
static inline int pinnacle_read(const struct device *dev, uint8_t address, uint8_t *value)
{
const struct pinnacle_config *config = dev->config;
return config->bus.read(&config->bus, address, value);
}
static inline int pinnacle_seq_read(const struct device *dev, uint8_t address, uint8_t *data,
uint8_t count)
{
const struct pinnacle_config *config = dev->config;
return config->bus.seq_read(&config->bus, address, data, count);
}
static inline int pinnacle_clear_cmd_complete(const struct device *dev)
{
const struct pinnacle_config *config = dev->config;
return config->bus.write(&config->bus, PINNACLE_REG_STATUS1, 0x00);
}
static int pinnacle_era_wait_for_completion(const struct device *dev)
{
bool ret;
uint8_t value;
ret = WAIT_FOR(pinnacle_read(dev, PINNACLE_REG_ERA_CTRL, &value) == 0 &&
value == PINNACLE_ERA_CTRL_COMPLETE,
PINNACLE_ERA_AWAIT_RETRY_COUNT * PINNACLE_ERA_AWAIT_DELAY_POLL_US,
k_sleep(K_USEC(PINNACLE_ERA_AWAIT_DELAY_POLL_US)));
if (!ret) {
return -EIO;
}
return 0;
}
static int pinnacle_era_write(const struct device *dev, uint16_t address, uint8_t value)
{
uint8_t address_buf[] = {
PINNACLE_REG_ERA_VALUE,
PINNACLE_REG_ERA_ADDR_HIGH,
PINNACLE_REG_ERA_ADDR_LOW,
PINNACLE_REG_ERA_CTRL,
};
uint8_t value_buf[] = {
value,
address >> 8,
address & 0xFF,
PINNACLE_ERA_CTRL_WRITE,
};
int rc;
rc = pinnacle_seq_write(dev, address_buf, value_buf, sizeof(address_buf));
if (rc) {
return rc;
}
return pinnacle_era_wait_for_completion(dev);
}
static int pinnacle_era_read(const struct device *dev, uint16_t address, uint8_t *value)
{
uint8_t address_buf[] = {
PINNACLE_REG_ERA_ADDR_HIGH,
PINNACLE_REG_ERA_ADDR_LOW,
PINNACLE_REG_ERA_CTRL,
};
uint8_t value_buf[] = {
address >> 8,
address & 0xFF,
PINNACLE_ERA_CTRL_READ,
};
int rc;
rc = pinnacle_seq_write(dev, address_buf, value_buf, sizeof(address_buf));
if (rc) {
return rc;
}
rc = pinnacle_era_wait_for_completion(dev);
if (rc) {
return rc;
}
return pinnacle_read(dev, PINNACLE_REG_ERA_VALUE, value);
}
static int pinnacle_set_sensitivity(const struct device *dev)
{
const struct pinnacle_config *config = dev->config;
uint8_t value;
int rc;
rc = pinnacle_era_read(dev, PINNACLE_ERA_REG_CONFIG, &value);
if (rc) {
return rc;
}
/* Clear BIT(7) and BIT(6) */
value &= 0x3F;
switch (config->sensitivity) {
case PINNACLE_SENSITIVITY_X1:
value |= PINNACLE_ERA_CONFIG_ADC_ATTENUATION_X1;
break;
case PINNACLE_SENSITIVITY_X2:
value |= PINNACLE_ERA_CONFIG_ADC_ATTENUATION_X2;
break;
case PINNACLE_SENSITIVITY_X3:
value |= PINNACLE_ERA_CONFIG_ADC_ATTENUATION_X3;
break;
case PINNACLE_SENSITIVITY_X4:
value |= PINNACLE_ERA_CONFIG_ADC_ATTENUATION_X4;
break;
}
rc = pinnacle_era_write(dev, PINNACLE_ERA_REG_CONFIG, value);
if (rc) {
return rc;
}
/* Clear SW_CC after setting sensitivity */
rc = pinnacle_clear_cmd_complete(dev);
if (rc) {
return rc;
}
return 0;
}
#if DT_ANY_INST_ON_BUS_STATUS_OKAY(i2c)
static bool pinnacle_is_ready_i2c(const struct pinnacle_bus *bus)
{
if (!i2c_is_ready_dt(&bus->i2c)) {
LOG_ERR("I2C bus %s is not ready", bus->i2c.bus->name);
return false;
}
return true;
}
static int pinnacle_write_i2c(const struct pinnacle_bus *bus, uint8_t address, uint8_t value)
{
uint8_t buf[] = {PINNACLE_WRITE_REG(address), value};
return i2c_write_dt(&bus->i2c, buf, 2);
}
static int pinnacle_seq_write_i2c(const struct pinnacle_bus *bus, uint8_t *address, uint8_t *value,
uint8_t count)
{
uint8_t buf[count * 2];
for (uint8_t i = 0; i < count; ++i) {
buf[i * 2] = PINNACLE_WRITE_REG(address[i]);
buf[i * 2 + 1] = value[i];
}
return i2c_write_dt(&bus->i2c, buf, count * 2);
}
static int pinnacle_read_i2c(const struct pinnacle_bus *bus, uint8_t address, uint8_t *value)
{
uint8_t reg = PINNACLE_READ_REG(address);
return i2c_write_read_dt(&bus->i2c, ®, 1, value, 1);
}
static int pinnacle_seq_read_i2c(const struct pinnacle_bus *bus, uint8_t address, uint8_t *buf,
uint8_t count)
{
uint8_t reg = PINNACLE_READ_REG(address);
return i2c_burst_read_dt(&bus->i2c, reg, buf, count);
}
#endif /* DT_ANY_INST_ON_BUS_STATUS_OKAY(i2c) */
#if DT_ANY_INST_ON_BUS_STATUS_OKAY(spi)
static bool pinnacle_is_ready_spi(const struct pinnacle_bus *bus)
{
if (!spi_is_ready_dt(&bus->spi)) {
LOG_ERR("SPI bus %s is not ready", bus->spi.bus->name);
return false;
}
return true;
}
static int pinnacle_write_spi(const struct pinnacle_bus *bus, uint8_t address, uint8_t value)
{
uint8_t tx_data[] = {
PINNACLE_WRITE_REG(address),
value,
};
const struct spi_buf tx_buf[] = {{
.buf = tx_data,
.len = sizeof(tx_data),
}};
const struct spi_buf_set tx_set = {
.buffers = tx_buf,
.count = ARRAY_SIZE(tx_buf),
};
return spi_write_dt(&bus->spi, &tx_set);
}
static int pinnacle_seq_write_spi(const struct pinnacle_bus *bus, uint8_t *address, uint8_t *value,
uint8_t count)
{
uint8_t tx_data[count * 2];
const struct spi_buf tx_buf[] = {{
.buf = tx_data,
.len = sizeof(tx_data),
}};
const struct spi_buf_set tx_set = {
.buffers = tx_buf,
.count = ARRAY_SIZE(tx_buf),
};
for (uint8_t i = 0; i < count; ++i) {
tx_data[i * 2] = PINNACLE_WRITE_REG(address[i]);
tx_data[i * 2 + 1] = value[i];
}
return spi_write_dt(&bus->spi, &tx_set);
}
static int pinnacle_read_spi(const struct pinnacle_bus *bus, uint8_t address, uint8_t *value)
{
uint8_t tx_data[] = {
PINNACLE_READ_REG(address),
PINNACLE_SPI_FB,
PINNACLE_SPI_FB,
PINNACLE_SPI_FB,
};
const struct spi_buf tx_buf[] = {{
.buf = tx_data,
.len = sizeof(tx_data),
}};
const struct spi_buf_set tx_set = {
.buffers = tx_buf,
.count = ARRAY_SIZE(tx_buf),
};
const struct spi_buf rx_buf[] = {
{
.buf = NULL,
.len = 3,
},
{
.buf = value,
.len = 1,
},
};
const struct spi_buf_set rx_set = {
.buffers = rx_buf,
.count = ARRAY_SIZE(rx_buf),
};
int rc;
rc = spi_transceive_dt(&bus->spi, &tx_set, &rx_set);
if (rc) {
LOG_ERR("Failed to read from SPI %s", bus->spi.bus->name);
return rc;
}
return 0;
}
static int pinnacle_seq_read_spi(const struct pinnacle_bus *bus, uint8_t address, uint8_t *buf,
uint8_t count)
{
uint8_t size = count + 3;
uint8_t tx_data[size];
tx_data[0] = PINNACLE_READ_REG(address);
tx_data[1] = PINNACLE_SPI_FC;
tx_data[2] = PINNACLE_SPI_FC;
uint8_t i = 3;
for (; i < (count + 2); ++i) {
tx_data[i] = PINNACLE_SPI_FC;
}
tx_data[i++] = PINNACLE_SPI_FB;
const struct spi_buf tx_buf[] = {{
.buf = tx_data,
.len = size,
}};
const struct spi_buf_set tx_set = {
.buffers = tx_buf,
.count = 1,
};
const struct spi_buf rx_buf[] = {
{
.buf = NULL,
.len = 3,
},
{
.buf = buf,
.len = count,
},
};
const struct spi_buf_set rx_set = {
.buffers = rx_buf,
.count = ARRAY_SIZE(rx_buf),
};
int rc;
rc = spi_transceive_dt(&bus->spi, &tx_set, &rx_set);
if (rc) {
LOG_ERR("Failed to read from SPI %s", bus->spi.bus->name);
return rc;
}
return 0;
}
#endif /* DT_ANY_INST_ON_BUS_STATUS_OKAY(spi) */
static void pinnacle_decode_sample(const struct device *dev, uint8_t *rx,
union pinnacle_sample *sample)
{
const struct pinnacle_config *config = dev->config;
if (config->relative_mode) {
if (config->primary_tap_enabled) {
sample->btn_primary = (rx[0] & BIT(0)) == BIT(0);
}
sample->rel_x = ((rx[0] & BIT(4)) == BIT(4)) ? -(256 - rx[1]) : rx[1];
sample->rel_y = ((rx[0] & BIT(5)) == BIT(5)) ? -(256 - rx[2]) : rx[2];
} else {
sample->abs_x = ((rx[2] & 0x0F) << 8) | rx[0];
sample->abs_y = ((rx[2] & 0xF0) << 4) | rx[1];
sample->abs_z = rx[3] & 0x3F;
}
}
static bool pinnacle_is_idle_sample(const union pinnacle_sample *sample)
{
return (sample->abs_x == 0 && sample->abs_y == 0 && sample->abs_z == 0);
}
static void pinnacle_clip_sample(const struct device *dev, union pinnacle_sample *sample)
{
const struct pinnacle_config *config = dev->config;
if (sample->abs_x < config->active_range_x_min) {
sample->abs_x = config->active_range_x_min;
}
if (sample->abs_x > config->active_range_x_max) {
sample->abs_x = config->active_range_x_max;
}
if (sample->abs_y < config->active_range_y_min) {
sample->abs_y = config->active_range_y_min;
}
if (sample->abs_y > config->active_range_y_max) {
sample->abs_y = config->active_range_y_max;
}
}
static void pinnacle_scale_sample(const struct device *dev, union pinnacle_sample *sample)
{
const struct pinnacle_config *config = dev->config;
uint16_t range_x = config->active_range_x_max - config->active_range_x_min;
uint16_t range_y = config->active_range_y_max - config->active_range_y_min;
sample->abs_x = (uint16_t)((uint32_t)(sample->abs_x - config->active_range_x_min) *
config->resolution_x / range_x);
sample->abs_y = (uint16_t)((uint32_t)(sample->abs_y - config->active_range_y_min) *
config->resolution_y / range_y);
}
static int pinnacle_sample_fetch(const struct device *dev, union pinnacle_sample *sample)
{
const struct pinnacle_config *config = dev->config;
uint8_t rx[4];
int rc;
if (config->relative_mode) {
rc = pinnacle_seq_read(dev, PINNACLE_REG_PACKET_BYTE0, rx, 3);
} else {
rc = pinnacle_seq_read(dev, PINNACLE_REG_PACKET_BYTE2, rx, 4);
}
if (rc) {
LOG_ERR("Failed to read data from SPI device");
return rc;
}
pinnacle_decode_sample(dev, rx, sample);
rc = pinnacle_write(dev, PINNACLE_REG_STATUS1, 0x00);
if (rc) {
LOG_ERR("Failed to clear SW_CC and SW_DR");
return rc;
}
return 0;
}
static int pinnacle_handle_interrupt(const struct device *dev)
{
const struct pinnacle_config *config = dev->config;
struct pinnacle_data *drv_data = dev->data;
union pinnacle_sample *sample = &drv_data->sample;
int rc;
rc = pinnacle_sample_fetch(dev, sample);
if (rc) {
LOG_ERR("Failed to read data packets");
return rc;
}
if (config->relative_mode) {
input_report_rel(dev, INPUT_REL_X, sample->rel_x, false, K_FOREVER);
input_report_rel(dev, INPUT_REL_Y, sample->rel_y, !config->primary_tap_enabled,
K_FOREVER);
if (config->primary_tap_enabled) {
input_report_key(dev, INPUT_BTN_TOUCH, sample->btn_primary, true,
K_FOREVER);
}
} else {
if (config->clipping_enabled && !pinnacle_is_idle_sample(sample)) {
pinnacle_clip_sample(dev, sample);
if (config->scaling_enabled) {
pinnacle_scale_sample(dev, sample);
}
}
input_report_abs(dev, INPUT_ABS_X, sample->abs_x, false, K_FOREVER);
input_report_abs(dev, INPUT_ABS_Y, sample->abs_y, false, K_FOREVER);
input_report_abs(dev, INPUT_ABS_Z, sample->abs_z, true, K_FOREVER);
}
return 0;
}
static void pinnacle_data_ready_gpio_callback(const struct device *dev, struct gpio_callback *cb,
uint32_t pins)
{
struct pinnacle_data *drv_data = CONTAINER_OF(cb, struct pinnacle_data, dr_cb_data);
k_work_submit(&drv_data->work);
}
static void pinnacle_work_cb(struct k_work *work)
{
struct pinnacle_data *drv_data = CONTAINER_OF(work, struct pinnacle_data, work);
pinnacle_handle_interrupt(drv_data->dev);
}
int pinnacle_init_interrupt(const struct device *dev)
{
struct pinnacle_data *drv_data = dev->data;
const struct pinnacle_config *config = dev->config;
const struct gpio_dt_spec *gpio = &config->dr_gpio;
int rc;
drv_data->dev = dev;
drv_data->work.handler = pinnacle_work_cb;
/* Configure GPIO pin for HW_DR signal */
rc = gpio_is_ready_dt(gpio);
if (!rc) {
LOG_ERR("GPIO device %s/%d is not ready", gpio->port->name, gpio->pin);
return -ENODEV;
}
rc = gpio_pin_configure_dt(gpio, GPIO_INPUT);
if (rc) {
LOG_ERR("Failed to configure %s/%d as input", gpio->port->name, gpio->pin);
return rc;
}
rc = gpio_pin_interrupt_configure_dt(gpio, GPIO_INT_EDGE_TO_ACTIVE);
if (rc) {
LOG_ERR("Failed to configured interrupt for %s/%d", gpio->port->name, gpio->pin);
return rc;
}
gpio_init_callback(&drv_data->dr_cb_data, pinnacle_data_ready_gpio_callback,
BIT(gpio->pin));
rc = gpio_add_callback(gpio->port, &drv_data->dr_cb_data);
if (rc) {
LOG_ERR("Failed to configured interrupt for %s/%d", gpio->port->name, gpio->pin);
return rc;
}
return 0;
}
static int pinnacle_init(const struct device *dev)
{
const struct pinnacle_config *config = dev->config;
int rc;
bool ret;
uint8_t value;
if (!pinnacle_bus_is_ready(dev)) {
return -ENODEV;
}
rc = pinnacle_read(dev, PINNACLE_REG_FIRMWARE_ID, &value);
if (rc) {
LOG_ERR("Failed to read FirmwareId");
return rc;
}
if (value != PINNACLE_FIRMWARE_ID) {
LOG_ERR("Incorrect Firmware ASIC ID %x", value);
return -ENODEV;
}
/* Wait until the calibration is completed (SW_CC is asserted) */
ret = WAIT_FOR(pinnacle_read(dev, PINNACLE_REG_STATUS1, &value) == 0 &&
(value & PINNACLE_STATUS1_SW_CC) == PINNACLE_STATUS1_SW_CC,
PINNACLE_CALIBRATION_AWAIT_RETRY_COUNT *
PINNACLE_CALIBRATION_AWAIT_DELAY_POLL_US,
k_sleep(K_USEC(PINNACLE_CALIBRATION_AWAIT_DELAY_POLL_US)));
if (!ret) {
LOG_ERR("Failed to wait for calibration complition");
return -EIO;
}
/* Clear SW_CC after Power on Reset */
rc = pinnacle_clear_cmd_complete(dev);
if (rc) {
LOG_ERR("Failed to clear SW_CC in Status1");
return -EIO;
}
/* Set trackpad sensitivity */
rc = pinnacle_set_sensitivity(dev);
if (rc) {
LOG_ERR("Failed to set sensitivity");
return -EIO;
}
rc = pinnacle_write(dev, PINNACLE_REG_SYS_CONFIG1, 0x00);
if (rc) {
LOG_ERR("Failed to write SysConfig1");
return rc;
}
/* Relative mode features */
if (config->relative_mode) {
value = (PINNACLE_FEED_CONFIG2_GLIDE_EXTEND_DISABLE |
PINNACLE_FEED_CONFIG2_SCROLL_DISABLE |
PINNACLE_FEED_CONFIG2_SECONDARY_TAP_DISABLE);
if (config->swap_xy) {
value |= PINNACLE_FEED_CONFIG2_SWAP_X_AND_Y;
}
if (!config->primary_tap_enabled) {
value |= PINNACLE_FEED_CONFIG2_ALL_TAPS_DISABLE;
}
} else {
value = (PINNACLE_FEED_CONFIG2_GLIDE_EXTEND_DISABLE |
PINNACLE_FEED_CONFIG2_SCROLL_DISABLE |
PINNACLE_FEED_CONFIG2_SECONDARY_TAP_DISABLE |
PINNACLE_FEED_CONFIG2_ALL_TAPS_DISABLE);
}
rc = pinnacle_write(dev, PINNACLE_REG_FEED_CONFIG2, value);
if (rc) {
LOG_ERR("Failed to write FeedConfig2");
return rc;
}
/* Data output flags */
value = PINNACLE_FEED_CONFIG1_FEED_ENABLE;
if (!config->relative_mode) {
value |= PINNACLE_FEED_CONFIG1_DATA_MODE_ABSOLUTE;
if (config->invert_x) {
value |= PINNACLE_FEED_CONFIG1_X_INVERT;
}
if (config->invert_y) {
value |= PINNACLE_FEED_CONFIG1_Y_INVERT;
}
}
rc = pinnacle_write(dev, PINNACLE_REG_FEED_CONFIG1, value);
if (rc) {
LOG_ERR("Failed to enable Feed in FeedConfig1");
return rc;
}
/* Configure count of Z-Idle packets */
rc = pinnacle_write(dev, PINNACLE_REG_Z_IDLE, config->idle_packets_count);
if (rc) {
LOG_ERR("Failed to set count of Z-idle packets");
return rc;
}
rc = pinnacle_init_interrupt(dev);
if (rc) {
LOG_ERR("Failed to initialize interrupts");
return rc;
}
return 0;
}
#define PINNACLE_CONFIG_BUS_I2C(inst) \
.bus = { \
.i2c = I2C_DT_SPEC_INST_GET(inst), \
.is_ready = pinnacle_is_ready_i2c, \
.write = pinnacle_write_i2c, \
.seq_write = pinnacle_seq_write_i2c, \
.read = pinnacle_read_i2c, \
.seq_read = pinnacle_seq_read_i2c, \
}
#define PINNACLE_SPI_OP (SPI_OP_MODE_MASTER | SPI_TRANSFER_MSB | SPI_MODE_CPHA | SPI_WORD_SET(8))
#define PINNACLE_CONFIG_BUS_SPI(inst) \
.bus = { \
.spi = SPI_DT_SPEC_INST_GET(inst, PINNACLE_SPI_OP, 0U), \
.is_ready = pinnacle_is_ready_spi, \
.write = pinnacle_write_spi, \
.seq_write = pinnacle_seq_write_spi, \
.read = pinnacle_read_spi, \
.seq_read = pinnacle_seq_read_spi, \
}
#define PINNACLE_DEFINE(inst) \
static const struct pinnacle_config pinnacle_config_##inst = { \
COND_CODE_1(DT_INST_ON_BUS(inst, i2c), (PINNACLE_CONFIG_BUS_I2C(inst),), ()) \
COND_CODE_1(DT_INST_ON_BUS(inst, spi), (PINNACLE_CONFIG_BUS_SPI(inst),), ()) \
.dr_gpio = GPIO_DT_SPEC_INST_GET_OR(inst, data_ready_gpios, {}), \
.relative_mode = DT_INST_ENUM_IDX(inst, data_mode), \
.sensitivity = DT_INST_ENUM_IDX(inst, sensitivity), \
.idle_packets_count = DT_INST_PROP(inst, idle_packets_count), \
.clipping_enabled = DT_INST_PROP(inst, clipping_enable), \
.active_range_x_min = DT_INST_PROP(inst, active_range_x_min), \
.active_range_x_max = DT_INST_PROP(inst, active_range_x_max), \
.active_range_y_min = DT_INST_PROP(inst, active_range_y_min), \
.active_range_y_max = DT_INST_PROP(inst, active_range_y_max), \
.scaling_enabled = DT_INST_PROP(inst, scaling_enable), \
.resolution_x = DT_INST_PROP(inst, scaling_x_resolution), \
.resolution_y = DT_INST_PROP(inst, scaling_y_resolution), \
.invert_x = DT_INST_PROP(inst, invert_x), \
.invert_y = DT_INST_PROP(inst, invert_y), \
.primary_tap_enabled = DT_INST_PROP(inst, primary_tap_enable), \
.swap_xy = DT_INST_PROP(inst, swap_xy), \
}; \
static struct pinnacle_data pinnacle_data_##inst; \
DEVICE_DT_INST_DEFINE(inst, pinnacle_init, NULL, &pinnacle_data_##inst, \
&pinnacle_config_##inst, POST_KERNEL, CONFIG_INPUT_INIT_PRIORITY, \
NULL); \
BUILD_ASSERT(DT_INST_PROP(inst, active_range_x_min) < \
DT_INST_PROP(inst, active_range_x_max), \
"active-range-x-min must be less than active-range-x-max"); \
BUILD_ASSERT(DT_INST_PROP(inst, active_range_y_min) < \
DT_INST_PROP(inst, active_range_y_max), \
"active_range-y-min must be less than active_range-y-max"); \
BUILD_ASSERT(DT_INST_PROP(inst, scaling_x_resolution) > 0, \
"scaling-x-resolution must be positive"); \
BUILD_ASSERT(DT_INST_PROP(inst, scaling_y_resolution) > 0, \
"scaling-y-resolution must be positive"); \
BUILD_ASSERT(IN_RANGE(DT_INST_PROP(inst, idle_packets_count), 0, UINT8_MAX), \
"idle-packets-count must be in range [0:255]");
DT_INST_FOREACH_STATUS_OKAY(PINNACLE_DEFINE)
``` | /content/code_sandbox/drivers/input/input_pinnacle.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 7,378 |
```unknown
config INPUT_ITE_IT8XXX2_KBD
bool "ITE keyboard scanning driver"
default y
depends on DT_HAS_ITE_IT8XXX2_KBD_ENABLED
select INPUT_KBD_MATRIX
help
This option enables the ITE keyboard scan driver.
``` | /content/code_sandbox/drivers/input/Kconfig.it8xxx2 | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 56 |
```c
/*
*
*/
#define DT_DRV_COMPAT zephyr_input_sdl_touch
#include <stdbool.h>
#include <zephyr/input/input.h>
#include <zephyr/logging/log.h>
#include "input_sdl_touch_bottom.h"
LOG_MODULE_REGISTER(sdl_input, CONFIG_INPUT_LOG_LEVEL);
static void sdl_input_callback(struct sdl_input_data *data)
{
if (data->just_released == true) {
input_report_key(data->dev, INPUT_BTN_TOUCH, 0, true, K_FOREVER);
data->just_released = false;
}
if (data->pressed) {
input_report_abs(data->dev, INPUT_ABS_X, data->x, false, K_FOREVER);
input_report_abs(data->dev, INPUT_ABS_Y, data->y, false, K_FOREVER);
input_report_key(data->dev, INPUT_BTN_TOUCH, 1, true, K_FOREVER);
}
}
static int sdl_init(const struct device *dev)
{
struct sdl_input_data *data = dev->data;
LOG_INF("Init '%s' device", dev->name);
data->dev = dev;
data->callback = sdl_input_callback;
sdl_input_init_bottom(data);
return 0;
}
static struct sdl_input_data sdl_data_0;
DEVICE_DT_INST_DEFINE(0, sdl_init, NULL, &sdl_data_0, NULL,
POST_KERNEL, CONFIG_INPUT_INIT_PRIORITY, NULL);
``` | /content/code_sandbox/drivers/input/input_sdl_touch.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 294 |
```c
/*
*
*/
#include <SDL.h>
#include "input_sdl_touch_bottom.h"
static int sdl_filter(void *arg, SDL_Event *event)
{
struct sdl_input_data *data = arg;
switch (event->type) {
case SDL_MOUSEBUTTONUP:
data->pressed = false;
data->just_released = true;
break;
case SDL_MOUSEBUTTONDOWN:
data->pressed = true;
break;
case SDL_MOUSEMOTION:
data->x = event->button.x;
data->y = event->button.y;
break;
default:
return 1;
}
data->callback(data);
return 1;
}
void sdl_input_init_bottom(struct sdl_input_data *data)
{
SDL_AddEventWatch(sdl_filter, data);
}
``` | /content/code_sandbox/drivers/input/input_sdl_touch_bottom.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 160 |
```unknown
menuconfig INPUT_FT5336
bool "FT3267/FT5XX6/FT6XX6 capacitive touch panel driver"
default y
depends on DT_HAS_FOCALTECH_FT5336_ENABLED
select I2C
help
Enable driver for multiple Focaltech capacitive touch panel
controllers. This driver should support FT5x06, FT5606, FT5x16,
FT6x06, Ft6x36, FT5x06i, FT5336, FT3316, FT5436i, FT3267,
FT5336i and FT5x46.
if INPUT_FT5336
config INPUT_FT5336_PERIOD
int "Sample period"
depends on !INPUT_FT5336_INTERRUPT
default 10
help
Sample period in milliseconds when in polling mode.
config INPUT_FT5336_INTERRUPT
bool "Interrupt"
help
Enable interrupt support (requires GPIO).
endif # INPUT_FT5336
``` | /content/code_sandbox/drivers/input/Kconfig.ft5336 | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 206 |
```unknown
config INPUT_ADC_KEYS
bool "ADC attached resistor ladder buttons"
default y
depends on DT_HAS_ADC_KEYS_ENABLED
depends on ADC
help
Enable support for ADC attached resistor ladder buttons.
``` | /content/code_sandbox/drivers/input/Kconfig.adc_keys | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 44 |
Subsets and Splits
No community queries yet
The top public SQL queries from the community will appear here once available.