text stringlengths 9 39.2M | dir stringlengths 25 226 | lang stringclasses 163 values | created_date timestamp[s] | updated_date timestamp[s] | repo_name stringclasses 751 values | repo_full_name stringclasses 752 values | star int64 1.01k 183k | len_tokens int64 1 18.5M |
|---|---|---|---|---|---|---|---|---|
```c
/* ST Microelectronics LPS22HH pressure and temperature sensor
*
*
*
* Datasheet:
* path_to_url
*/
#define DT_DRV_COMPAT st_lps22hh
#include <zephyr/drivers/sensor.h>
#include <zephyr/kernel.h>
#include <zephyr/device.h>
#include <zephyr/init.h>
#include <zephyr/sys/byteorder.h>
#include <zephyr/sys/__assert.h>
#include <zephyr/logging/log.h>
#include "lps22hh.h"
LOG_MODULE_REGISTER(LPS22HH, CONFIG_SENSOR_LOG_LEVEL);
static inline int lps22hh_set_odr_raw(const struct device *dev, uint8_t odr)
{
const struct lps22hh_config * const cfg = dev->config;
stmdev_ctx_t *ctx = (stmdev_ctx_t *)&cfg->ctx;
return lps22hh_data_rate_set(ctx, odr);
}
static int lps22hh_sample_fetch(const struct device *dev,
enum sensor_channel chan)
{
struct lps22hh_data *data = dev->data;
const struct lps22hh_config * const cfg = dev->config;
stmdev_ctx_t *ctx = (stmdev_ctx_t *)&cfg->ctx;
uint32_t raw_press;
int16_t raw_temp;
__ASSERT_NO_MSG(chan == SENSOR_CHAN_ALL
|| chan == SENSOR_CHAN_PRESS
|| chan == SENSOR_CHAN_AMBIENT_TEMP);
switch (chan) {
case SENSOR_CHAN_PRESS:
if (lps22hh_pressure_raw_get(ctx, &raw_press) < 0) {
LOG_DBG("Failed to read sample");
return -EIO;
}
break;
case SENSOR_CHAN_AMBIENT_TEMP:
if (lps22hh_temperature_raw_get(ctx, &raw_temp) < 0) {
LOG_DBG("Failed to read sample");
return -EIO;
}
break;
case SENSOR_CHAN_ALL:
if (lps22hh_pressure_raw_get(ctx, &raw_press) < 0) {
LOG_DBG("Failed to read sample");
return -EIO;
}
if (lps22hh_temperature_raw_get(ctx, &raw_temp) < 0) {
LOG_DBG("Failed to read sample");
return -EIO;
}
break;
default:
LOG_ERR("Unsupported sensor channel");
return -ENOTSUP;
}
/** Prevent overwriting values that weren't fetched */
if (chan == SENSOR_CHAN_PRESS || chan == SENSOR_CHAN_ALL) {
data->sample_press = raw_press;
}
if (chan == SENSOR_CHAN_AMBIENT_TEMP || chan == SENSOR_CHAN_ALL) {
data->sample_temp = raw_temp;
}
return 0;
}
static inline void lps22hh_press_convert(struct sensor_value *val,
int32_t raw_val)
{
int32_t press_tmp = raw_val >> 8; /* raw value is left aligned (24 msb) */
/* Pressure sensitivity is 4096 LSB/hPa */
/* Also convert hPa into kPa */
val->val1 = press_tmp / 40960;
/* For the decimal part use (3125 / 128) as a factor instead of
* (1000000 / 40960) to avoid int32 overflow
*/
val->val2 = (press_tmp % 40960) * 3125 / 128;
}
static inline void lps22hh_temp_convert(struct sensor_value *val,
int16_t raw_val)
{
/* Temperature sensitivity is 100 LSB/deg C */
val->val1 = raw_val / 100;
val->val2 = ((int32_t)raw_val % 100) * 10000;
}
static int lps22hh_channel_get(const struct device *dev,
enum sensor_channel chan,
struct sensor_value *val)
{
struct lps22hh_data *data = dev->data;
if (chan == SENSOR_CHAN_PRESS) {
lps22hh_press_convert(val, data->sample_press);
} else if (chan == SENSOR_CHAN_AMBIENT_TEMP) {
lps22hh_temp_convert(val, data->sample_temp);
} else {
return -ENOTSUP;
}
return 0;
}
static const uint16_t lps22hh_map[] = {0, 1, 10, 25, 50, 75, 100, 200};
static int lps22hh_odr_set(const struct device *dev, uint16_t freq)
{
int odr;
for (odr = 0; odr < ARRAY_SIZE(lps22hh_map); odr++) {
if (freq == lps22hh_map[odr]) {
break;
}
}
if (odr == ARRAY_SIZE(lps22hh_map)) {
LOG_DBG("bad frequency");
return -EINVAL;
}
if (lps22hh_set_odr_raw(dev, odr) < 0) {
LOG_DBG("failed to set sampling rate");
return -EIO;
}
return 0;
}
static int lps22hh_attr_set(const struct device *dev,
enum sensor_channel chan,
enum sensor_attribute attr,
const struct sensor_value *val)
{
if (chan != SENSOR_CHAN_ALL) {
LOG_WRN("attr_set() not supported on this channel.");
return -ENOTSUP;
}
switch (attr) {
case SENSOR_ATTR_SAMPLING_FREQUENCY:
return lps22hh_odr_set(dev, val->val1);
default:
LOG_DBG("operation not supported.");
return -ENOTSUP;
}
return 0;
}
static const struct sensor_driver_api lps22hh_driver_api = {
.attr_set = lps22hh_attr_set,
.sample_fetch = lps22hh_sample_fetch,
.channel_get = lps22hh_channel_get,
#if CONFIG_LPS22HH_TRIGGER
.trigger_set = lps22hh_trigger_set,
#endif
};
static int lps22hh_init_chip(const struct device *dev)
{
const struct lps22hh_config * const cfg = dev->config;
struct lps22hh_data *data = dev->data;
stmdev_ctx_t *ctx = (stmdev_ctx_t *)&cfg->ctx;
uint8_t chip_id;
int ret;
#if DT_ANY_INST_ON_BUS_STATUS_OKAY(i3c)
if (cfg->i3c.bus != NULL) {
/*
* Need to grab the pointer to the I3C device descriptor
* before we can talk to the sensor.
*/
data->i3c_dev = i3c_device_find(cfg->i3c.bus, &cfg->i3c.dev_id);
if (data->i3c_dev == NULL) {
LOG_ERR("Cannot find I3C device descriptor");
return -ENODEV;
}
}
#endif
if (lps22hh_device_id_get(ctx, &chip_id) < 0) {
LOG_ERR("%s: Not able to read dev id", dev->name);
return -EIO;
}
if (chip_id != LPS22HH_ID) {
LOG_ERR("%s: Invalid chip ID 0x%02x", dev->name, chip_id);
return -EIO;
}
LOG_DBG("%s: chip id 0x%x", dev->name, chip_id);
#if DT_ANY_INST_ON_BUS_STATUS_OKAY(i3c)
if (cfg->i3c.bus != NULL) {
/*
* Enabling I3C and disabling I2C are required
* for I3C IBI to work, or else the sensor will not
* send any IBIs.
*/
ret = lps22hh_i3c_interface_set(ctx, LPS22HH_I3C_ENABLE);
if (ret < 0) {
LOG_ERR("Cannot enable I3C interface");
return ret;
}
ret = lps22hh_i2c_interface_set(ctx, LPS22HH_I2C_DISABLE);
if (ret < 0) {
LOG_ERR("Cannot disable I2C interface");
return ret;
}
}
#else
ARG_UNUSED(data);
#endif
/* set sensor default odr */
LOG_DBG("%s: odr: %d", dev->name, cfg->odr);
ret = lps22hh_set_odr_raw(dev, cfg->odr);
if (ret < 0) {
LOG_ERR("%s: Failed to set odr %d", dev->name, cfg->odr);
return ret;
}
if (lps22hh_block_data_update_set(ctx, PROPERTY_ENABLE) < 0) {
LOG_ERR("%s: Failed to set BDU", dev->name);
return ret;
}
return 0;
}
static int lps22hh_init(const struct device *dev)
{
if (lps22hh_init_chip(dev) < 0) {
LOG_DBG("Failed to initialize chip");
return -EIO;
}
#ifdef CONFIG_LPS22HH_TRIGGER
if (lps22hh_init_interrupt(dev) < 0) {
LOG_ERR("Failed to initialize interrupt.");
return -EIO;
}
#endif
return 0;
}
#if DT_NUM_INST_STATUS_OKAY(DT_DRV_COMPAT) == 0
#warning "LPS22HH driver enabled without any devices"
#endif
/*
* Instantiation macros used when a device is on a SPI bus.
*/
#ifdef CONFIG_LPS22HH_TRIGGER
#define LPS22HH_CFG_IRQ(inst) \
.gpio_int = GPIO_DT_SPEC_INST_GET(inst, drdy_gpios),
#else
#define LPS22HH_CFG_IRQ(inst)
#endif /* CONFIG_LPS22HH_TRIGGER */
#define LPS22HH_CONFIG_COMMON(inst) \
.odr = DT_INST_PROP(inst, odr), \
COND_CODE_1(DT_INST_NODE_HAS_PROP(inst, drdy_gpios), \
(LPS22HH_CFG_IRQ(inst)), ())
#define LPS22HH_SPI_OPERATION (SPI_WORD_SET(8) | \
SPI_OP_MODE_MASTER | \
SPI_MODE_CPOL | \
SPI_MODE_CPHA) \
#define LPS22HH_CONFIG_SPI(inst) \
{ \
STMEMSC_CTX_SPI(&lps22hh_config_##inst.stmemsc_cfg), \
.stmemsc_cfg = { \
.spi = SPI_DT_SPEC_INST_GET(inst, \
LPS22HH_SPI_OPERATION, \
0), \
}, \
LPS22HH_CONFIG_COMMON(inst) \
}
/*
* Instantiation macros used when a device is on an I2C bus.
*/
#define LPS22HH_CONFIG_I2C(inst) \
{ \
STMEMSC_CTX_I2C(&lps22hh_config_##inst.stmemsc_cfg), \
.stmemsc_cfg = { \
.i2c = I2C_DT_SPEC_INST_GET(inst), \
}, \
LPS22HH_CONFIG_COMMON(inst) \
}
/*
* Instantiation macros used when a device is on an I#C bus.
*/
#define LPS22HH_CONFIG_I3C(inst) \
{ \
STMEMSC_CTX_I3C(&lps22hh_config_##inst.stmemsc_cfg), \
.stmemsc_cfg = { \
.i3c = &lps22hh_data_##inst.i3c_dev, \
}, \
.i3c.bus = DEVICE_DT_GET(DT_INST_BUS(inst)), \
.i3c.dev_id = I3C_DEVICE_ID_DT_INST(inst), \
LPS22HH_CONFIG_COMMON(inst) \
}
#define LPS22HH_CONFIG_I3C_OR_I2C(inst) \
COND_CODE_0(DT_INST_PROP_BY_IDX(inst, reg, 1), \
(LPS22HH_CONFIG_I2C(inst)), \
(LPS22HH_CONFIG_I3C(inst)))
/*
* Main instantiation macro. Use of COND_CODE_1() selects the right
* bus-specific macro at preprocessor time.
*/
#define LPS22HH_DEFINE(inst) \
static struct lps22hh_data lps22hh_data_##inst; \
static const struct lps22hh_config lps22hh_config_##inst = \
COND_CODE_1(DT_INST_ON_BUS(inst, spi), \
(LPS22HH_CONFIG_SPI(inst)), \
(COND_CODE_1(DT_INST_ON_BUS(inst, i3c), \
(LPS22HH_CONFIG_I3C_OR_I2C(inst)), \
(LPS22HH_CONFIG_I2C(inst))))); \
SENSOR_DEVICE_DT_INST_DEFINE(inst, lps22hh_init, NULL, &lps22hh_data_##inst, \
&lps22hh_config_##inst, POST_KERNEL, \
CONFIG_SENSOR_INIT_PRIORITY, &lps22hh_driver_api);
DT_INST_FOREACH_STATUS_OKAY(LPS22HH_DEFINE)
``` | /content/code_sandbox/drivers/sensor/st/lps22hh/lps22hh.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 2,839 |
```objective-c
/* ST Microelectronics IIS2DLPC 3-axis accelerometer driver
*
*
*
* Datasheet:
* path_to_url
*/
#ifndef ZEPHYR_DRIVERS_SENSOR_IIS2DLPC_IIS2DLPC_H_
#define ZEPHYR_DRIVERS_SENSOR_IIS2DLPC_IIS2DLPC_H_
#include <zephyr/drivers/gpio.h>
#include <zephyr/sys/util.h>
#include <zephyr/drivers/sensor.h>
#include <stmemsc.h>
#include "iis2dlpc_reg.h"
#if DT_ANY_INST_ON_BUS_STATUS_OKAY(spi)
#include <zephyr/drivers/spi.h>
#endif /* DT_ANY_INST_ON_BUS_STATUS_OKAY(spi) */
#if DT_ANY_INST_ON_BUS_STATUS_OKAY(i2c)
#include <zephyr/drivers/i2c.h>
#endif /* DT_ANY_INST_ON_BUS_STATUS_OKAY(i2c) */
/* Return ODR reg value based on data rate set */
#define IIS2DLPC_ODR_TO_REG(_odr) \
((_odr <= 1) ? IIS2DLPC_XL_ODR_1Hz6_LP_ONLY : \
(_odr <= 12) ? IIS2DLPC_XL_ODR_12Hz5 : \
((31 - __builtin_clz(_odr / 25))) + 3)
/* FS reg value from Full Scale */
#define IIS2DLPC_FS_TO_REG(_fs) (30 - __builtin_clz(_fs))
/* Acc Gain value in ug/LSB in High Perf mode */
#define IIS2DLPC_FS_2G_GAIN 244
#define IIS2DLPC_FS_4G_GAIN 488
#define IIS2DLPC_FS_8G_GAIN 976
#define IIS2DLPC_FS_16G_GAIN 1952
#define IIS2DLPC_SHFT_GAIN_NOLP1 2
#define IIS2DLPC_ACCEL_GAIN_DEFAULT_VAL IIS2DLPC_FS_2G_GAIN
#define IIS2DLPC_FS_TO_GAIN(_fs, _lp1) \
(IIS2DLPC_FS_2G_GAIN << ((_fs) + (_lp1)))
/* shift value for power mode */
#define IIS2DLPC_SHIFT_PM1 4
#define IIS2DLPC_SHIFT_PMOTHER 2
/**
* struct iis2dlpc_dev_config - iis2dlpc hw configuration
* @bus_name: Pointer to bus master identifier.
* @pm: Power mode (lis2dh_powermode).
* @irq_dev_name: Pointer to GPIO PORT identifier.
* @irq_pin: GPIO pin number connected to sensor int pin.
* @drdy_int: Sensor drdy int (int1/int2).
*/
struct iis2dlpc_config {
stmdev_ctx_t ctx;
union {
#if DT_ANY_INST_ON_BUS_STATUS_OKAY(i2c)
const struct i2c_dt_spec i2c;
#endif
#if DT_ANY_INST_ON_BUS_STATUS_OKAY(spi)
const struct spi_dt_spec spi;
#endif
} stmemsc_cfg;
iis2dlpc_mode_t pm;
uint8_t range;
#ifdef CONFIG_IIS2DLPC_TRIGGER
const struct gpio_dt_spec gpio_drdy;
uint8_t drdy_int;
#ifdef CONFIG_IIS2DLPC_TAP
uint8_t tap_mode;
uint8_t tap_threshold[3];
uint8_t tap_shock;
uint8_t tap_latency;
uint8_t tap_quiet;
#endif /* CONFIG_IIS2DLPC_TAP */
#endif /* CONFIG_IIS2DLPC_TRIGGER */
};
/* sensor data */
struct iis2dlpc_data {
const struct device *dev;
int16_t acc[3];
/* save sensitivity */
uint16_t gain;
#ifdef CONFIG_IIS2DLPC_TRIGGER
const struct device *gpio;
uint8_t gpio_pin;
struct gpio_callback gpio_cb;
sensor_trigger_handler_t drdy_handler;
const struct sensor_trigger *drdy_trig;
#ifdef CONFIG_IIS2DLPC_TAP
sensor_trigger_handler_t tap_handler;
const struct sensor_trigger *tap_trig;
sensor_trigger_handler_t double_tap_handler;
const struct sensor_trigger *double_tap_trig;
#endif /* CONFIG_IIS2DLPC_TAP */
#ifdef CONFIG_IIS2DLPC_ACTIVITY
sensor_trigger_handler_t activity_handler;
const struct sensor_trigger *activity_trig;
#endif /* CONFIG_IIS2DLPC_ACTIVITY */
#if defined(CONFIG_IIS2DLPC_TRIGGER_OWN_THREAD)
K_KERNEL_STACK_MEMBER(thread_stack, CONFIG_IIS2DLPC_THREAD_STACK_SIZE);
struct k_thread thread;
struct k_sem gpio_sem;
#elif defined(CONFIG_IIS2DLPC_TRIGGER_GLOBAL_THREAD)
struct k_work work;
#endif /* CONFIG_IIS2DLPC_TRIGGER_GLOBAL_THREAD */
#endif /* CONFIG_IIS2DLPC_TRIGGER */
};
#ifdef CONFIG_IIS2DLPC_TRIGGER
int iis2dlpc_init_interrupt(const struct device *dev);
int iis2dlpc_trigger_set(const struct device *dev,
const struct sensor_trigger *trig,
sensor_trigger_handler_t handler);
#endif /* CONFIG_IIS2DLPC_TRIGGER */
#endif /* ZEPHYR_DRIVERS_SENSOR_IIS2DLPC_IIS2DLPC_H_ */
``` | /content/code_sandbox/drivers/sensor/st/iis2dlpc/iis2dlpc.h | objective-c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 1,108 |
```c
/* ST Microelectronics IIS2DLPC 3-axis accelerometer driver
*
*
*
* Datasheet:
* path_to_url
*/
#define DT_DRV_COMPAT st_iis2dlpc
#include <zephyr/init.h>
#include <zephyr/sys/__assert.h>
#include <zephyr/sys/byteorder.h>
#include <zephyr/logging/log.h>
#include <zephyr/drivers/sensor.h>
#if DT_ANY_INST_ON_BUS_STATUS_OKAY(spi)
#include <zephyr/drivers/spi.h>
#elif DT_ANY_INST_ON_BUS_STATUS_OKAY(i2c)
#include <zephyr/drivers/i2c.h>
#endif
#include "iis2dlpc.h"
LOG_MODULE_REGISTER(IIS2DLPC, CONFIG_SENSOR_LOG_LEVEL);
/**
* iis2dlpc_set_range - set full scale range for acc
* @dev: Pointer to instance of struct device (I2C or SPI)
* @range: Full scale range (2, 4, 8 and 16 G)
*/
static int iis2dlpc_set_range(const struct device *dev, uint8_t fs)
{
int err;
struct iis2dlpc_data *iis2dlpc = dev->data;
const struct iis2dlpc_config *cfg = dev->config;
stmdev_ctx_t *ctx = (stmdev_ctx_t *)&cfg->ctx;
uint8_t shift_gain = 0U;
err = iis2dlpc_full_scale_set(ctx, fs);
if (cfg->pm == IIS2DLPC_CONT_LOW_PWR_12bit) {
shift_gain = IIS2DLPC_SHFT_GAIN_NOLP1;
}
if (!err) {
/* save internally gain for optimization */
iis2dlpc->gain = IIS2DLPC_FS_TO_GAIN(fs, shift_gain);
}
return err;
}
/**
* iis2dlpc_set_odr - set new sampling frequency
* @dev: Pointer to instance of struct device (I2C or SPI)
* @odr: Output data rate
*/
static int iis2dlpc_set_odr(const struct device *dev, uint16_t odr)
{
const struct iis2dlpc_config *cfg = dev->config;
stmdev_ctx_t *ctx = (stmdev_ctx_t *)&cfg->ctx;
uint8_t val;
/* check if power off */
if (odr == 0U) {
return iis2dlpc_data_rate_set(ctx, IIS2DLPC_XL_ODR_OFF);
}
val = IIS2DLPC_ODR_TO_REG(odr);
if (val > IIS2DLPC_XL_ODR_1k6Hz) {
LOG_ERR("ODR too high");
return -ENOTSUP;
}
return iis2dlpc_data_rate_set(ctx, val);
}
static inline void iis2dlpc_convert(struct sensor_value *val, int raw_val,
float gain)
{
int64_t dval;
/* Gain is in ug/LSB */
/* Convert to m/s^2 */
dval = ((int64_t)raw_val * gain * SENSOR_G) / 1000000LL;
val->val1 = dval / 1000000LL;
val->val2 = dval % 1000000LL;
}
static inline void iis2dlpc_channel_get_acc(const struct device *dev,
enum sensor_channel chan,
struct sensor_value *val)
{
int i;
uint8_t ofs_start, ofs_stop;
struct iis2dlpc_data *iis2dlpc = dev->data;
struct sensor_value *pval = val;
switch (chan) {
case SENSOR_CHAN_ACCEL_X:
ofs_start = ofs_stop = 0U;
break;
case SENSOR_CHAN_ACCEL_Y:
ofs_start = ofs_stop = 1U;
break;
case SENSOR_CHAN_ACCEL_Z:
ofs_start = ofs_stop = 2U;
break;
default:
ofs_start = 0U; ofs_stop = 2U;
break;
}
for (i = ofs_start; i <= ofs_stop ; i++) {
iis2dlpc_convert(pval++, iis2dlpc->acc[i], iis2dlpc->gain);
}
}
static int iis2dlpc_channel_get(const struct device *dev,
enum sensor_channel chan,
struct sensor_value *val)
{
switch (chan) {
case SENSOR_CHAN_ACCEL_X:
case SENSOR_CHAN_ACCEL_Y:
case SENSOR_CHAN_ACCEL_Z:
case SENSOR_CHAN_ACCEL_XYZ:
iis2dlpc_channel_get_acc(dev, chan, val);
return 0;
default:
LOG_DBG("Channel not supported");
break;
}
return -ENOTSUP;
}
#ifdef CONFIG_IIS2DLPC_ACTIVITY
static int iis2dlpc_set_slope_th(const struct device *dev, uint16_t th)
{
int err;
const struct iis2dlpc_config *cfg = dev->config;
stmdev_ctx_t *ctx = (stmdev_ctx_t *) &cfg->ctx;
err = iis2dlpc_wkup_threshold_set(ctx, th & 0x3F);
if (err) {
LOG_ERR("Could not set WK_THS to 0x%02X, error %d",
th & 0x3F, err);
return err;
}
return 0;
}
static int iis2dlpc_set_slope_dur(const struct device *dev, uint16_t dur)
{
int err;
const struct iis2dlpc_config *cfg = dev->config;
stmdev_ctx_t *ctx = (stmdev_ctx_t *) &cfg->ctx;
uint8_t val;
val = (dur & 0x0F);
err = iis2dlpc_act_sleep_dur_set(ctx, val);
if (err) {
LOG_ERR("Could not set SLEEP_DUR to 0x%02X, error %d",
val, err);
return err;
}
val = ((dur >> 5) & 0x03);
err = iis2dlpc_wkup_dur_set(ctx, val);
if (err) {
LOG_ERR("Could not set WAKE_DUR to 0x%02X, error %d",
val, err);
return err;
}
return 0;
}
#endif /* CONFIG_IIS2DLPC_ACTIVITY */
static int iis2dlpc_dev_config(const struct device *dev,
enum sensor_channel chan,
enum sensor_attribute attr,
const struct sensor_value *val)
{
switch (attr) {
case SENSOR_ATTR_FULL_SCALE:
return iis2dlpc_set_range(dev,
IIS2DLPC_FS_TO_REG(sensor_ms2_to_g(val)));
case SENSOR_ATTR_SAMPLING_FREQUENCY:
return iis2dlpc_set_odr(dev, val->val1);
#ifdef CONFIG_IIS2DLPC_ACTIVITY
case SENSOR_ATTR_SLOPE_TH:
return iis2dlpc_set_slope_th(dev, val->val1);
case SENSOR_ATTR_SLOPE_DUR:
return iis2dlpc_set_slope_dur(dev, val->val1);
#endif /* CONFIG_IIS2DLPC_ACTIVITY */
default:
LOG_DBG("Acc attribute not supported");
break;
}
return -ENOTSUP;
}
static int iis2dlpc_attr_set(const struct device *dev,
enum sensor_channel chan,
enum sensor_attribute attr,
const struct sensor_value *val)
{
switch (chan) {
case SENSOR_CHAN_ACCEL_X:
case SENSOR_CHAN_ACCEL_Y:
case SENSOR_CHAN_ACCEL_Z:
case SENSOR_CHAN_ACCEL_XYZ:
return iis2dlpc_dev_config(dev, chan, attr, val);
default:
LOG_DBG("Attr not supported on %d channel", chan);
break;
}
return -ENOTSUP;
}
static int iis2dlpc_sample_fetch(const struct device *dev,
enum sensor_channel chan)
{
struct iis2dlpc_data *iis2dlpc = dev->data;
const struct iis2dlpc_config *cfg = dev->config;
stmdev_ctx_t *ctx = (stmdev_ctx_t *)&cfg->ctx;
uint8_t shift;
int16_t buf[3];
/* fetch raw data sample */
if (iis2dlpc_acceleration_raw_get(ctx, buf) < 0) {
LOG_DBG("Failed to fetch raw data sample");
return -EIO;
}
/* adjust to resolution */
if (cfg->pm == IIS2DLPC_CONT_LOW_PWR_12bit) {
shift = IIS2DLPC_SHIFT_PM1;
} else {
shift = IIS2DLPC_SHIFT_PMOTHER;
}
iis2dlpc->acc[0] = sys_le16_to_cpu(buf[0]) >> shift;
iis2dlpc->acc[1] = sys_le16_to_cpu(buf[1]) >> shift;
iis2dlpc->acc[2] = sys_le16_to_cpu(buf[2]) >> shift;
return 0;
}
static const struct sensor_driver_api iis2dlpc_driver_api = {
.attr_set = iis2dlpc_attr_set,
#if CONFIG_IIS2DLPC_TRIGGER
.trigger_set = iis2dlpc_trigger_set,
#endif /* CONFIG_IIS2DLPC_TRIGGER */
.sample_fetch = iis2dlpc_sample_fetch,
.channel_get = iis2dlpc_channel_get,
};
static int iis2dlpc_set_power_mode(stmdev_ctx_t *ctx, iis2dlpc_mode_t pm)
{
uint8_t regval = IIS2DLPC_CONT_LOW_PWR_12bit;
switch (pm) {
case IIS2DLPC_CONT_LOW_PWR_2:
case IIS2DLPC_CONT_LOW_PWR_3:
case IIS2DLPC_CONT_LOW_PWR_4:
case IIS2DLPC_HIGH_PERFORMANCE:
regval = pm;
break;
default:
LOG_DBG("Apply default Power Mode");
break;
}
return iis2dlpc_write_reg(ctx, IIS2DLPC_CTRL1, ®val, 1);
}
static int iis2dlpc_init(const struct device *dev)
{
struct iis2dlpc_data *iis2dlpc = dev->data;
const struct iis2dlpc_config *cfg = dev->config;
stmdev_ctx_t *ctx = (stmdev_ctx_t *)&cfg->ctx;
uint8_t wai;
iis2dlpc->dev = dev;
/* check chip ID */
if (iis2dlpc_device_id_get(ctx, &wai) < 0) {
return -EIO;
}
if (wai != IIS2DLPC_ID) {
LOG_ERR("Invalid chip ID");
return -EINVAL;
}
/* reset device */
if (iis2dlpc_reset_set(ctx, PROPERTY_ENABLE) < 0) {
return -EIO;
}
k_busy_wait(100);
if (iis2dlpc_block_data_update_set(ctx, PROPERTY_ENABLE) < 0) {
return -EIO;
}
/* set power mode */
LOG_INF("power-mode is %d", cfg->pm);
if (iis2dlpc_set_power_mode(ctx, cfg->pm)) {
return -EIO;
}
/* set default odr to 12.5Hz acc */
if (iis2dlpc_set_odr(dev, 12) < 0) {
LOG_ERR("odr init error (12.5 Hz)");
return -EIO;
}
LOG_INF("range is %d", cfg->range);
if (iis2dlpc_set_range(dev, IIS2DLPC_FS_TO_REG(cfg->range)) < 0) {
LOG_ERR("range init error %d", cfg->range);
return -EIO;
}
#ifdef CONFIG_IIS2DLPC_TRIGGER
if (iis2dlpc_init_interrupt(dev) < 0) {
LOG_ERR("Failed to initialize interrupts");
return -EIO;
}
#ifdef CONFIG_IIS2DLPC_TAP
LOG_INF("TAP: tap mode is %d", cfg->tap_mode);
if (iis2dlpc_tap_mode_set(ctx, cfg->tap_mode) < 0) {
LOG_ERR("Failed to select tap trigger mode");
return -EIO;
}
LOG_INF("TAP: ths_x is %02x", cfg->tap_threshold[0]);
if (iis2dlpc_tap_threshold_x_set(ctx, cfg->tap_threshold[0]) < 0) {
LOG_ERR("Failed to set tap X axis threshold");
return -EIO;
}
LOG_INF("TAP: ths_y is %02x", cfg->tap_threshold[1]);
if (iis2dlpc_tap_threshold_y_set(ctx, cfg->tap_threshold[1]) < 0) {
LOG_ERR("Failed to set tap Y axis threshold");
return -EIO;
}
LOG_INF("TAP: ths_z is %02x", cfg->tap_threshold[2]);
if (iis2dlpc_tap_threshold_z_set(ctx, cfg->tap_threshold[2]) < 0) {
LOG_ERR("Failed to set tap Z axis threshold");
return -EIO;
}
if (cfg->tap_threshold[0] > 0) {
LOG_INF("TAP: tap_x enabled");
if (iis2dlpc_tap_detection_on_x_set(ctx, 1) < 0) {
LOG_ERR("Failed to set tap detection on X axis");
return -EIO;
}
}
if (cfg->tap_threshold[1] > 0) {
LOG_INF("TAP: tap_y enabled");
if (iis2dlpc_tap_detection_on_y_set(ctx, 1) < 0) {
LOG_ERR("Failed to set tap detection on Y axis");
return -EIO;
}
}
if (cfg->tap_threshold[2] > 0) {
LOG_INF("TAP: tap_z enabled");
if (iis2dlpc_tap_detection_on_z_set(ctx, 1) < 0) {
LOG_ERR("Failed to set tap detection on Z axis");
return -EIO;
}
}
LOG_INF("TAP: shock is %02x", cfg->tap_shock);
if (iis2dlpc_tap_shock_set(ctx, cfg->tap_shock) < 0) {
LOG_ERR("Failed to set tap shock duration");
return -EIO;
}
LOG_INF("TAP: latency is %02x", cfg->tap_latency);
if (iis2dlpc_tap_dur_set(ctx, cfg->tap_latency) < 0) {
LOG_ERR("Failed to set tap latency");
return -EIO;
}
LOG_INF("TAP: quiet time is %02x", cfg->tap_quiet);
if (iis2dlpc_tap_quiet_set(ctx, cfg->tap_quiet) < 0) {
LOG_ERR("Failed to set tap quiet time");
return -EIO;
}
#endif /* CONFIG_IIS2DLPC_TAP */
#endif /* CONFIG_IIS2DLPC_TRIGGER */
return 0;
}
#if DT_NUM_INST_STATUS_OKAY(DT_DRV_COMPAT) == 0
#warning "IIS2DLPC driver enabled without any devices"
#endif
/*
* Device creation macro, shared by IIS2DLPC_DEFINE_SPI() and
* IIS2DLPC_DEFINE_I2C().
*/
#define IIS2DLPC_DEVICE_INIT(inst) \
SENSOR_DEVICE_DT_INST_DEFINE(inst, \
iis2dlpc_init, \
NULL, \
&iis2dlpc_data_##inst, \
&iis2dlpc_config_##inst, \
POST_KERNEL, \
CONFIG_SENSOR_INIT_PRIORITY, \
&iis2dlpc_driver_api);
/*
* Instantiation macros used when a device is on a SPI bus.
*/
#ifdef CONFIG_IIS2DLPC_TAP
#define IIS2DLPC_CONFIG_TAP(inst) \
.tap_mode = DT_INST_PROP(inst, tap_mode), \
.tap_threshold = DT_INST_PROP(inst, tap_threshold), \
.tap_shock = DT_INST_PROP(inst, tap_shock), \
.tap_latency = DT_INST_PROP(inst, tap_latency), \
.tap_quiet = DT_INST_PROP(inst, tap_quiet),
#else
#define IIS2DLPC_CONFIG_TAP(inst)
#endif /* CONFIG_IIS2DLPC_TAP */
#ifdef CONFIG_IIS2DLPC_TRIGGER
#define IIS2DLPC_CFG_IRQ(inst) \
.gpio_drdy = GPIO_DT_SPEC_INST_GET(inst, drdy_gpios), \
.drdy_int = DT_INST_PROP(inst, drdy_int),
#else
#define IIS2DLPC_CFG_IRQ(inst)
#endif /* CONFIG_IIS2DLPC_TRIGGER */
#define IIS2DLPC_CONFIG_COMMON(inst) \
.pm = DT_INST_PROP(inst, power_mode), \
.range = DT_INST_PROP(inst, range), \
IIS2DLPC_CONFIG_TAP(inst) \
COND_CODE_1(DT_INST_NODE_HAS_PROP(inst, drdy_gpios), \
(IIS2DLPC_CFG_IRQ(inst)), ())
#define IIS2DLPC_SPI_OPERATION (SPI_WORD_SET(8) | \
SPI_OP_MODE_MASTER | \
SPI_MODE_CPOL | \
SPI_MODE_CPHA) \
#define IIS2DLPC_CONFIG_SPI(inst) \
{ \
STMEMSC_CTX_SPI(&iis2dlpc_config_##inst.stmemsc_cfg), \
.stmemsc_cfg = { \
.spi = SPI_DT_SPEC_INST_GET(inst, \
IIS2DLPC_SPI_OPERATION, \
0), \
}, \
IIS2DLPC_CONFIG_COMMON(inst) \
}
/*
* Instantiation macros used when a device is on an I2C bus.
*/
#define IIS2DLPC_CONFIG_I2C(inst) \
{ \
STMEMSC_CTX_I2C(&iis2dlpc_config_##inst.stmemsc_cfg), \
.stmemsc_cfg = { \
.i2c = I2C_DT_SPEC_INST_GET(inst), \
}, \
IIS2DLPC_CONFIG_COMMON(inst) \
}
/*
* Main instantiation macro. Use of COND_CODE_1() selects the right
* bus-specific macro at preprocessor time.
*/
#define IIS2DLPC_DEFINE(inst) \
static struct iis2dlpc_data iis2dlpc_data_##inst; \
static const struct iis2dlpc_config iis2dlpc_config_##inst = \
COND_CODE_1(DT_INST_ON_BUS(inst, spi), \
(IIS2DLPC_CONFIG_SPI(inst)), \
(IIS2DLPC_CONFIG_I2C(inst))); \
IIS2DLPC_DEVICE_INIT(inst)
DT_INST_FOREACH_STATUS_OKAY(IIS2DLPC_DEFINE)
``` | /content/code_sandbox/drivers/sensor/st/iis2dlpc/iis2dlpc.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 4,163 |
```c
/* ST Microelectronics LPS28DFW pressure and temperature sensor
*
*
*/
#include "lps2xdf.h"
#include "lps28dfw.h"
#include <zephyr/logging/log.h>
LOG_MODULE_DECLARE(LPS2XDF, CONFIG_SENSOR_LOG_LEVEL);
static inline int lps28dfw_mode_set_odr_raw(const struct device *dev, uint8_t odr)
{
const struct lps2xdf_config *const cfg = dev->config;
stmdev_ctx_t *ctx = (stmdev_ctx_t *)&cfg->ctx;
lps28dfw_md_t md;
md.odr = odr;
md.avg = cfg->avg;
md.lpf = cfg->lpf;
md.fs = cfg->fs;
return lps28dfw_mode_set(ctx, &md);
}
static int lps28dfw_sample_fetch(const struct device *dev, enum sensor_channel chan)
{
struct lps2xdf_data *data = dev->data;
const struct lps2xdf_config *const cfg = dev->config;
stmdev_ctx_t *ctx = (stmdev_ctx_t *)&cfg->ctx;
lps28dfw_data_t raw_data;
lps28dfw_md_t md;
md.fs = cfg->fs;
if (lps28dfw_data_get(ctx, &md, &raw_data) < 0) {
LOG_DBG("Failed to read sample");
return -EIO;
}
data->sample_press = raw_data.pressure.raw;
data->sample_temp = raw_data.heat.raw;
return 0;
}
/**
* lps28dfw_handle_interrupt - handle the drdy event
* read data and call handler if registered any
*/
#ifdef CONFIG_LPS2XDF_TRIGGER
static void lps28dfw_handle_interrupt(const struct device *dev)
{
int ret;
struct lps2xdf_data *lps28dfw = dev->data;
const struct lps2xdf_config *cfg = dev->config;
stmdev_ctx_t *ctx = (stmdev_ctx_t *)&cfg->ctx;
lps28dfw_all_sources_t status;
if (lps28dfw_all_sources_get(ctx, &status) < 0) {
LOG_DBG("failed reading status reg");
goto exit;
}
if (status.drdy_pres == 0) {
goto exit; /* spurious interrupt */
}
if (lps28dfw->handler_drdy != NULL) {
lps28dfw->handler_drdy(dev, lps28dfw->data_ready_trigger);
}
if (ON_I3C_BUS(cfg)) {
/*
* I3C IBI does not rely on GPIO.
* So no need to enable GPIO pin for interrupt trigger.
*/
return;
}
exit:
ret = gpio_pin_interrupt_configure_dt(&cfg->gpio_int,
GPIO_INT_EDGE_TO_ACTIVE);
if (ret < 0) {
LOG_ERR("%s: Not able to configure pin_int", dev->name);
}
}
/**
* lps28dfw_enable_int - enable selected int pin to generate interrupt
*/
static int lps28dfw_enable_int(const struct device *dev, int enable)
{
const struct lps2xdf_config * const cfg = dev->config;
stmdev_ctx_t *ctx = (stmdev_ctx_t *)&cfg->ctx;
lps28dfw_pin_int_route_t int_route;
/* set interrupt */
lps28dfw_pin_int_route_get(ctx, &int_route);
int_route.drdy_pres = enable;
return lps28dfw_pin_int_route_set(ctx, &int_route);
}
/**
* lps22df_trigger_set - link external trigger to event data ready
*/
static int lps28dfw_trigger_set(const struct device *dev,
const struct sensor_trigger *trig,
sensor_trigger_handler_t handler)
{
struct lps2xdf_data *lps28dfw = dev->data;
const struct lps2xdf_config * const cfg = dev->config;
stmdev_ctx_t *ctx = (stmdev_ctx_t *)&cfg->ctx;
lps28dfw_data_t raw_data;
lps28dfw_md_t md;
md.fs = cfg->fs;
if (trig->chan != SENSOR_CHAN_ALL) {
LOG_WRN("trigger set not supported on this channel.");
return -ENOTSUP;
}
lps28dfw->handler_drdy = handler;
lps28dfw->data_ready_trigger = trig;
if (handler) {
/* dummy read: re-trigger interrupt */
if (lps28dfw_data_get(ctx, &md, &raw_data) < 0) {
LOG_DBG("Failed to read sample");
return -EIO;
}
return lps28dfw_enable_int(dev, 1);
} else {
return lps28dfw_enable_int(dev, 0);
}
return -ENOTSUP;
}
#endif /* CONFIG_LPS2XDF_TRIGGER */
const struct lps2xdf_chip_api st_lps28dfw_chip_api = {
.mode_set_odr_raw = lps28dfw_mode_set_odr_raw,
.sample_fetch = lps28dfw_sample_fetch,
#if CONFIG_LPS2XDF_TRIGGER
.handle_interrupt = lps28dfw_handle_interrupt,
.trigger_set = lps28dfw_trigger_set,
#endif
};
int st_lps28dfw_init(const struct device *dev)
{
const struct lps2xdf_config *const cfg = dev->config;
stmdev_ctx_t *ctx = (stmdev_ctx_t *)&cfg->ctx;
lps28dfw_id_t id;
lps28dfw_stat_t status;
uint8_t tries = 10;
int ret;
#if DT_HAS_COMPAT_ON_BUS_STATUS_OKAY(st_lps28dfw, i3c)
if (cfg->i3c.bus != NULL) {
struct lps2xdf_data *data = dev->data;
/*
* Need to grab the pointer to the I3C device descriptor
* before we can talk to the sensor.
*/
data->i3c_dev = i3c_device_find(cfg->i3c.bus, &cfg->i3c.dev_id);
if (data->i3c_dev == NULL) {
LOG_ERR("Cannot find I3C device descriptor");
return -ENODEV;
}
}
#endif
if (lps28dfw_id_get(ctx, &id) < 0) {
LOG_ERR("%s: Not able to read dev id", dev->name);
return -EIO;
}
if (id.whoami != LPS28DFW_ID) {
LOG_ERR("%s: Invalid chip ID 0x%02x", dev->name, id.whoami);
return -EIO;
}
LOG_DBG("%s: chip id 0x%x", dev->name, id.whoami);
/* Restore default configuration */
if (lps28dfw_init_set(ctx, LPS28DFW_RESET) < 0) {
LOG_ERR("%s: Not able to reset device", dev->name);
return -EIO;
}
do {
if (!--tries) {
LOG_DBG("sw reset timed out");
return -ETIMEDOUT;
}
k_usleep(LPS2XDF_SWRESET_WAIT_TIME_US);
if (lps28dfw_status_get(ctx, &status) < 0) {
return -EIO;
}
} while (status.sw_reset);
/* Set bdu and if_inc recommended for driver usage */
if (lps28dfw_init_set(ctx, LPS28DFW_DRV_RDY) < 0) {
LOG_ERR("%s: Not able to set device to ready state", dev->name);
return -EIO;
}
if (ON_I3C_BUS(cfg)) {
lps28dfw_bus_mode_t bus_mode;
/* Select bus interface */
lps28dfw_bus_mode_get(ctx, &bus_mode);
bus_mode.filter = LPS28DFW_AUTO;
bus_mode.interface = LPS28DFW_SEL_BY_HW;
lps28dfw_bus_mode_set(ctx, &bus_mode);
}
/* set sensor default odr */
LOG_DBG("%s: odr: %d", dev->name, cfg->odr);
ret = lps28dfw_mode_set_odr_raw(dev, cfg->odr);
if (ret < 0) {
LOG_ERR("%s: Failed to set odr %d", dev->name, cfg->odr);
return ret;
}
#ifdef CONFIG_LPS2XDF_TRIGGER
if (cfg->trig_enabled) {
if (lps2xdf_init_interrupt(dev, DEVICE_VARIANT_LPS28DFW) < 0) {
LOG_ERR("Failed to initialize interrupt.");
return -EIO;
}
}
#endif
return 0;
}
``` | /content/code_sandbox/drivers/sensor/st/lps2xdf/lps28dfw.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 1,918 |
```c
/* ST Microelectronics LPS2XDF pressure and temperature sensor
*
*
*
* Datasheet:
* path_to_url
* path_to_url
*/
#include <zephyr/kernel.h>
#include <zephyr/drivers/sensor.h>
#include <zephyr/drivers/gpio.h>
#include <zephyr/logging/log.h>
#include "lps2xdf.h"
#if DT_HAS_COMPAT_STATUS_OKAY(st_lps22df)
#include "lps22df.h"
#endif
#if DT_HAS_COMPAT_STATUS_OKAY(st_lps28dfw)
#include "lps28dfw.h"
#endif
LOG_MODULE_DECLARE(LPS2XDF, CONFIG_SENSOR_LOG_LEVEL);
int lps2xdf_trigger_set(const struct device *dev,
const struct sensor_trigger *trig,
sensor_trigger_handler_t handler)
{
const struct lps2xdf_config *const cfg = dev->config;
const struct lps2xdf_chip_api *chip_api = cfg->chip_api;
return chip_api->trigger_set(dev, trig, handler);
}
static void lps2xdf_intr_callback(struct lps2xdf_data *lps2xdf)
{
#if defined(CONFIG_LPS2XDF_TRIGGER_OWN_THREAD)
k_sem_give(&lps2xdf->intr_sem);
#elif defined(CONFIG_LPS2XDF_TRIGGER_GLOBAL_THREAD)
k_work_submit(&lps2xdf->work);
#endif /* CONFIG_LPS2XDF_TRIGGER_OWN_THREAD */
}
static void lps2xdf_gpio_callback(const struct device *dev,
struct gpio_callback *cb, uint32_t pins)
{
struct lps2xdf_data *lps2xdf =
CONTAINER_OF(cb, struct lps2xdf_data, gpio_cb);
ARG_UNUSED(pins);
const struct lps2xdf_config *cfg = lps2xdf->dev->config;
int ret;
ret = gpio_pin_interrupt_configure_dt(&cfg->gpio_int, GPIO_INT_DISABLE);
if (ret < 0) {
LOG_ERR("%s: Not able to configure pin_int", dev->name);
}
lps2xdf_intr_callback(lps2xdf);
}
#ifdef CONFIG_LPS2XDF_TRIGGER_OWN_THREAD
static void lps2xdf_thread(struct lps2xdf_data *lps2xdf)
{
const struct device *dev = lps2xdf->dev;
const struct lps2xdf_config *const cfg = dev->config;
const struct lps2xdf_chip_api *chip_api = cfg->chip_api;
while (1) {
k_sem_take(&lps2xdf->intr_sem, K_FOREVER);
chip_api->handle_interrupt(dev);
}
}
#endif /* CONFIG_LPS2XDF_TRIGGER_OWN_THREAD */
#ifdef CONFIG_LPS2XDF_TRIGGER_GLOBAL_THREAD
static void lps2xdf_work_cb(struct k_work *work)
{
struct lps2xdf_data *lps2xdf =
CONTAINER_OF(work, struct lps2xdf_data, work);
const struct device *dev = lps2xdf->dev;
const struct lps2xdf_config *const cfg = dev->config;
const struct lps2xdf_chip_api *chip_api = cfg->chip_api;
chip_api->handle_interrupt(dev);
}
#endif /* CONFIG_LPS2XDF_TRIGGER_GLOBAL_THREAD */
#if (DT_HAS_COMPAT_ON_BUS_STATUS_OKAY(st_lps22df, i3c) ||\
DT_HAS_COMPAT_ON_BUS_STATUS_OKAY(st_lps28dfw, i3c))
static int lps2xdf_ibi_cb(struct i3c_device_desc *target,
struct i3c_ibi_payload *payload)
{
const struct device *dev = target->dev;
struct lps2xdf_data *lps2xdf = dev->data;
ARG_UNUSED(payload);
lps2xdf_intr_callback(lps2xdf);
return 0;
}
#endif
int lps2xdf_init_interrupt(const struct device *dev, enum sensor_variant variant)
{
struct lps2xdf_data *lps2xdf = dev->data;
const struct lps2xdf_config *cfg = dev->config;
stmdev_ctx_t *ctx = (stmdev_ctx_t *)&cfg->ctx;
int ret;
/* setup data ready gpio interrupt */
if (!gpio_is_ready_dt(&cfg->gpio_int) && !ON_I3C_BUS(cfg)) {
if (cfg->gpio_int.port) {
LOG_ERR("%s: device %s is not ready", dev->name,
cfg->gpio_int.port->name);
return -ENODEV;
}
LOG_DBG("%s: gpio_int not defined in DT", dev->name);
return 0;
}
lps2xdf->dev = dev;
#if defined(CONFIG_LPS2XDF_TRIGGER_OWN_THREAD)
k_sem_init(&lps2xdf->intr_sem, 0, K_SEM_MAX_LIMIT);
k_thread_create(&lps2xdf->thread, lps2xdf->thread_stack,
CONFIG_LPS2XDF_THREAD_STACK_SIZE,
(k_thread_entry_t)lps2xdf_thread, lps2xdf,
NULL, NULL, K_PRIO_COOP(CONFIG_LPS2XDF_THREAD_PRIORITY),
0, K_NO_WAIT);
#elif defined(CONFIG_LPS2XDF_TRIGGER_GLOBAL_THREAD)
lps2xdf->work.handler = lps2xdf_work_cb;
#endif /* CONFIG_LPS2XDF_TRIGGER_OWN_THREAD */
if (!ON_I3C_BUS(cfg)) {
ret = gpio_pin_configure_dt(&cfg->gpio_int, GPIO_INPUT);
if (ret < 0) {
LOG_ERR("Could not configure gpio");
return ret;
}
LOG_INF("%s: int on %s.%02u", dev->name, cfg->gpio_int.port->name,
cfg->gpio_int.pin);
gpio_init_callback(&lps2xdf->gpio_cb,
lps2xdf_gpio_callback,
BIT(cfg->gpio_int.pin));
ret = gpio_add_callback(cfg->gpio_int.port, &lps2xdf->gpio_cb);
if (ret < 0) {
LOG_ERR("Could not set gpio callback");
return ret;
}
}
LOG_DBG("drdy_pulsed is %d", (int)cfg->drdy_pulsed);
/* enable drdy in pulsed/latched mode */
if (variant == DEVICE_VARIANT_LPS22DF) {
#if DT_HAS_COMPAT_STATUS_OKAY(st_lps22df)
lps22df_int_mode_t mode;
if (lps22df_interrupt_mode_get(ctx, &mode) < 0) {
return -EIO;
}
mode.drdy_latched = ~cfg->drdy_pulsed;
if (lps22df_interrupt_mode_set(ctx, &mode) < 0) {
return -EIO;
}
#endif
} else if (variant == DEVICE_VARIANT_LPS28DFW) {
#if DT_HAS_COMPAT_STATUS_OKAY(st_lps28dfw)
lps28dfw_int_mode_t mode;
if (lps28dfw_interrupt_mode_get(ctx, &mode) < 0) {
return -EIO;
}
mode.drdy_latched = ~cfg->drdy_pulsed;
if (lps28dfw_interrupt_mode_set(ctx, &mode) < 0) {
return -EIO;
}
#endif
} else {
return -ENOTSUP;
}
#if (DT_HAS_COMPAT_ON_BUS_STATUS_OKAY(st_lps22df, i3c) ||\
DT_HAS_COMPAT_ON_BUS_STATUS_OKAY(st_lps28dfw, i3c))
if (cfg->i3c.bus == NULL) {
/* I3C IBI does not utilize GPIO interrupt. */
lps2xdf->i3c_dev->ibi_cb = lps2xdf_ibi_cb;
if (i3c_ibi_enable(lps2xdf->i3c_dev) != 0) {
LOG_DBG("Could not enable I3C IBI");
return -EIO;
}
return 0;
}
#endif
return gpio_pin_interrupt_configure_dt(&cfg->gpio_int,
GPIO_INT_EDGE_TO_ACTIVE);
}
``` | /content/code_sandbox/drivers/sensor/st/lps2xdf/lps2xdf_trigger.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 1,741 |
```objective-c
/* ST Microelectronics LPS2XDF pressure and temperature sensor
*
*
*
* Datasheets:
* path_to_url
* path_to_url
*/
#ifndef ZEPHYR_DRIVERS_SENSOR_LPS2XDF_LPS2XDF_H_
#define ZEPHYR_DRIVERS_SENSOR_LPS2XDF_LPS2XDF_H_
#include <stdint.h>
#include <stmemsc.h>
#if DT_HAS_COMPAT_STATUS_OKAY(st_lps28dfw)
#include "lps28dfw_reg.h"
#endif
#if DT_HAS_COMPAT_STATUS_OKAY(st_lps22df)
#include "lps22df_reg.h"
#endif
#include <zephyr/drivers/spi.h>
#include <zephyr/drivers/i2c.h>
#include <zephyr/drivers/i3c.h>
#include <zephyr/drivers/sensor.h>
#define LPS2XDF_SWRESET_WAIT_TIME_US 50
#if (DT_HAS_COMPAT_ON_BUS_STATUS_OKAY(st_lps22df, i3c) || \
DT_HAS_COMPAT_ON_BUS_STATUS_OKAY(st_lps28dfw, i3c))
#define ON_I3C_BUS(cfg) (cfg->i3c.bus != NULL)
#else
#define ON_I3C_BUS(cfg) (false)
#endif
typedef int32_t (*api_lps2xdf_mode_set_odr_raw)(const struct device *dev, uint8_t odr);
typedef int32_t (*api_lps2xdf_sample_fetch)(const struct device *dev, enum sensor_channel chan);
typedef void (*api_lps2xdf_handle_interrupt)(const struct device *dev);
#ifdef CONFIG_LPS2XDF_TRIGGER
typedef int (*api_lps2xdf_trigger_set)(const struct device *dev,
const struct sensor_trigger *trig,
sensor_trigger_handler_t handler);
#endif
struct lps2xdf_chip_api {
api_lps2xdf_mode_set_odr_raw mode_set_odr_raw;
api_lps2xdf_sample_fetch sample_fetch;
api_lps2xdf_handle_interrupt handle_interrupt;
#ifdef CONFIG_LPS2XDF_TRIGGER
api_lps2xdf_trigger_set trigger_set;
#endif
};
enum sensor_variant {
DEVICE_VARIANT_LPS22DF = 0,
DEVICE_VARIANT_LPS28DFW = 1,
};
struct lps2xdf_config {
stmdev_ctx_t ctx;
union {
#if (DT_HAS_COMPAT_ON_BUS_STATUS_OKAY(st_lps22df, i2c) || \
DT_HAS_COMPAT_ON_BUS_STATUS_OKAY(st_lps28dfw, i2c))
const struct i2c_dt_spec i2c;
#endif
#if DT_HAS_COMPAT_ON_BUS_STATUS_OKAY(st_lps22df, spi)
const struct spi_dt_spec spi;
#endif
#if (DT_HAS_COMPAT_ON_BUS_STATUS_OKAY(st_lps22df, i3c) || \
DT_HAS_COMPAT_ON_BUS_STATUS_OKAY(st_lps28dfw, i3c))
struct i3c_device_desc **i3c;
#endif
} stmemsc_cfg;
uint8_t odr;
uint8_t lpf;
uint8_t avg;
uint8_t drdy_pulsed;
bool fs;
#ifdef CONFIG_LPS2XDF_TRIGGER
struct gpio_dt_spec gpio_int;
bool trig_enabled;
#endif
#if (DT_HAS_COMPAT_ON_BUS_STATUS_OKAY(st_lps22df, i3c) || \
DT_HAS_COMPAT_ON_BUS_STATUS_OKAY(st_lps28dfw, i3c))
struct {
const struct device *bus;
const struct i3c_device_id dev_id;
} i3c;
#endif
const struct lps2xdf_chip_api *chip_api;
};
struct lps2xdf_data {
int32_t sample_press;
int16_t sample_temp;
#ifdef CONFIG_LPS2XDF_TRIGGER
struct gpio_callback gpio_cb;
const struct sensor_trigger *data_ready_trigger;
sensor_trigger_handler_t handler_drdy;
const struct device *dev;
#if defined(CONFIG_LPS2XDF_TRIGGER_OWN_THREAD)
K_KERNEL_STACK_MEMBER(thread_stack, CONFIG_LPS2XDF_THREAD_STACK_SIZE);
struct k_thread thread;
struct k_sem intr_sem;
#elif defined(CONFIG_LPS2XDF_TRIGGER_GLOBAL_THREAD)
struct k_work work;
#endif
#endif /* CONFIG_LPS2XDF_TRIGGER */
#if (DT_HAS_COMPAT_ON_BUS_STATUS_OKAY(st_lps22df, i3c) || \
DT_HAS_COMPAT_ON_BUS_STATUS_OKAY(st_lps28dfw, i3c))
struct i3c_device_desc *i3c_dev;
#endif
};
#ifdef CONFIG_LPS2XDF_TRIGGER
int lps2xdf_trigger_set(const struct device *dev,
const struct sensor_trigger *trig,
sensor_trigger_handler_t handler);
int lps2xdf_init_interrupt(const struct device *dev, enum sensor_variant variant);
#endif
#endif /* ZEPHYR_DRIVERS_SENSOR_LPS2XDF_H_ */
``` | /content/code_sandbox/drivers/sensor/st/lps2xdf/lps2xdf.h | objective-c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 1,036 |
```objective-c
/* ST Microelectronics LPS22DF pressure and temperature sensor
*
*
*/
#include <stdint.h>
#include <stmemsc.h>
#include "lps22df_reg.h"
#include <zephyr/drivers/sensor.h>
#ifndef ZEPHYR_DRIVERS_SENSOR_LPS22DF_LPS22DF_H_
#define ZEPHYR_DRIVERS_SENSOR_LPS22DF_LPS22DF_H_
extern const struct lps2xdf_chip_api st_lps22df_chip_api;
int st_lps22df_init(const struct device *dev);
#endif /* ZEPHYR_DRIVERS_SENSOR_LPS22DF_H_ */
``` | /content/code_sandbox/drivers/sensor/st/lps2xdf/lps22df.h | objective-c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 130 |
```objective-c
/* ST Microelectronics LPS28DFW pressure and temperature sensor
*
*
*/
#include <stdint.h>
#include <stmemsc.h>
#include <zephyr/drivers/sensor.h>
#include "lps28dfw_reg.h"
#ifndef ZEPHYR_DRIVERS_SENSOR_LPS28DFW_LPS28DFW_H_
#define ZEPHYR_DRIVERS_SENSOR_LPS28DFW_LPS28DFW_H_
extern const struct lps2xdf_chip_api st_lps28dfw_chip_api;
int st_lps28dfw_init(const struct device *dev);
#endif /* ZEPHYR_DRIVERS_SENSOR_LPS28DFW_H_ */
``` | /content/code_sandbox/drivers/sensor/st/lps2xdf/lps28dfw.h | objective-c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 139 |
```unknown
# ST Microelectronics LPS2xDF pressure and temperature sensor
menuconfig LPS2XDF
bool "LPS2xDF pressure and temperature"
default y
depends on DT_HAS_ST_LPS22DF_ENABLED || DT_HAS_ST_LPS28DFW_ENABLED
depends on ZEPHYR_HAL_ST_MODULE
select I2C if $(dt_compat_on_bus,$(DT_COMPAT_ST_LPS22DF),i2c) ||\
$(dt_compat_on_bus,$(DT_COMPAT_ST_LPS28DFW),i2c)
select I2C if $(dt_compat_on_bus,$(DT_COMPAT_ST_LPS22DF),i3c) ||\
$(dt_compat_on_bus,$(DT_COMPAT_ST_LPS28DFW),i3c)
select SPI if $(dt_compat_on_bus,$(DT_COMPAT_ST_LPS22DF),spi)
select HAS_STMEMSC
select USE_STDC_LPS22DF if DT_HAS_ST_LPS22DF_ENABLED
select USE_STDC_LPS28DFW if DT_HAS_ST_LPS28DFW_ENABLED
help
Enable driver for LPS2xDF I2C-based pressure and temperature
sensor.
if LPS2XDF
choice LPS2XDF_TRIGGER_MODE
prompt "Trigger mode"
default LPS2XDF_TRIGGER_GLOBAL_THREAD
help
Specify the type of triggering to be used by the driver.
config LPS2XDF_TRIGGER_NONE
bool "No trigger"
config LPS2XDF_TRIGGER_GLOBAL_THREAD
bool "Use global thread"
depends on GPIO
select LPS2XDF_TRIGGER
config LPS2XDF_TRIGGER_OWN_THREAD
bool "Use own thread"
depends on GPIO
select LPS2XDF_TRIGGER
endchoice # LPS2XDF_TRIGGER_MODE
config LPS2XDF_TRIGGER
bool
config LPS2XDF_THREAD_PRIORITY
int "Thread priority"
depends on LPS2XDF_TRIGGER_OWN_THREAD
default 10
help
Priority of thread used by the driver to handle interrupts.
config LPS2XDF_THREAD_STACK_SIZE
int "Thread stack size"
depends on LPS2XDF_TRIGGER_OWN_THREAD
default 1024
help
Stack size of thread used by the driver to handle interrupts.
endif # LPS2XDF
``` | /content/code_sandbox/drivers/sensor/st/lps2xdf/Kconfig | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 490 |
```c
/* ST Microelectronics LPS22DF pressure and temperature sensor
*
*
*/
#include "lps2xdf.h"
#include "lps22df.h"
#include <zephyr/logging/log.h>
LOG_MODULE_DECLARE(LPS2XDF, CONFIG_SENSOR_LOG_LEVEL);
static inline int lps22df_mode_set_odr_raw(const struct device *dev, uint8_t odr)
{
const struct lps2xdf_config *const cfg = dev->config;
stmdev_ctx_t *ctx = (stmdev_ctx_t *)&cfg->ctx;
lps22df_md_t md;
md.odr = odr;
md.avg = cfg->avg;
md.lpf = cfg->lpf;
return lps22df_mode_set(ctx, &md);
}
static int lps22df_sample_fetch(const struct device *dev, enum sensor_channel chan)
{
struct lps2xdf_data *data = dev->data;
const struct lps2xdf_config *const cfg = dev->config;
stmdev_ctx_t *ctx = (stmdev_ctx_t *)&cfg->ctx;
lps22df_data_t raw_data;
if (lps22df_data_get(ctx, &raw_data) < 0) {
LOG_DBG("Failed to read sample");
return -EIO;
}
data->sample_press = raw_data.pressure.raw;
data->sample_temp = raw_data.heat.raw;
return 0;
}
/**
* lps22df_handle_interrupt - handle the drdy event
* read data and call handler if registered any
*/
#ifdef CONFIG_LPS2XDF_TRIGGER
static void lps22df_handle_interrupt(const struct device *dev)
{
int ret;
struct lps2xdf_data *lps22df = dev->data;
const struct lps2xdf_config *cfg = dev->config;
stmdev_ctx_t *ctx = (stmdev_ctx_t *)&cfg->ctx;
lps22df_all_sources_t status;
if (lps22df_all_sources_get(ctx, &status) < 0) {
LOG_DBG("failed reading status reg");
goto exit;
}
if (status.drdy_pres == 0) {
goto exit; /* spurious interrupt */
}
if (lps22df->handler_drdy != NULL) {
lps22df->handler_drdy(dev, lps22df->data_ready_trigger);
}
if (ON_I3C_BUS(cfg)) {
/*
* I3C IBI does not rely on GPIO.
* So no need to enable GPIO pin for interrupt trigger.
*/
return;
}
exit:
ret = gpio_pin_interrupt_configure_dt(&cfg->gpio_int,
GPIO_INT_EDGE_TO_ACTIVE);
if (ret < 0) {
LOG_ERR("%s: Not able to configure pin_int", dev->name);
}
}
/**
* lps22df_enable_int - enable selected int pin to generate interrupt
*/
static int lps22df_enable_int(const struct device *dev, int enable)
{
const struct lps2xdf_config * const cfg = dev->config;
stmdev_ctx_t *ctx = (stmdev_ctx_t *)&cfg->ctx;
lps22df_pin_int_route_t int_route;
/* set interrupt */
lps22df_pin_int_route_get(ctx, &int_route);
int_route.drdy_pres = enable;
return lps22df_pin_int_route_set(ctx, &int_route);
}
/**
* lps22df_trigger_set - link external trigger to event data ready
*/
static int lps22df_trigger_set(const struct device *dev,
const struct sensor_trigger *trig,
sensor_trigger_handler_t handler)
{
struct lps2xdf_data *lps22df = dev->data;
const struct lps2xdf_config * const cfg = dev->config;
stmdev_ctx_t *ctx = (stmdev_ctx_t *)&cfg->ctx;
lps22df_data_t raw_data;
if (trig->chan != SENSOR_CHAN_ALL) {
LOG_WRN("trigger set not supported on this channel.");
return -ENOTSUP;
}
lps22df->handler_drdy = handler;
lps22df->data_ready_trigger = trig;
if (handler) {
/* dummy read: re-trigger interrupt */
if (lps22df_data_get(ctx, &raw_data) < 0) {
LOG_DBG("Failed to read sample");
return -EIO;
}
return lps22df_enable_int(dev, 1);
} else {
return lps22df_enable_int(dev, 0);
}
return -ENOTSUP;
}
#endif /* CONFIG_LPS2XDF_TRIGGER */
const struct lps2xdf_chip_api st_lps22df_chip_api = {
.mode_set_odr_raw = lps22df_mode_set_odr_raw,
.sample_fetch = lps22df_sample_fetch,
#if CONFIG_LPS2XDF_TRIGGER
.handle_interrupt = lps22df_handle_interrupt,
.trigger_set = lps22df_trigger_set,
#endif
};
int st_lps22df_init(const struct device *dev)
{
const struct lps2xdf_config *const cfg = dev->config;
stmdev_ctx_t *ctx = (stmdev_ctx_t *)&cfg->ctx;
lps22df_id_t id;
lps22df_stat_t status;
uint8_t tries = 10;
int ret;
#if DT_HAS_COMPAT_ON_BUS_STATUS_OKAY(st_lps22df, i3c)
if (cfg->i3c.bus != NULL) {
struct lps2xdf_data *data = dev->data;
/*
* Need to grab the pointer to the I3C device descriptor
* before we can talk to the sensor.
*/
data->i3c_dev = i3c_device_find(cfg->i3c.bus, &cfg->i3c.dev_id);
if (data->i3c_dev == NULL) {
LOG_ERR("Cannot find I3C device descriptor");
return -ENODEV;
}
}
#endif
if (lps22df_id_get(ctx, &id) < 0) {
LOG_ERR("%s: Not able to read dev id", dev->name);
return -EIO;
}
if (id.whoami != LPS22DF_ID) {
LOG_ERR("%s: Invalid chip ID 0x%02x", dev->name, id.whoami);
return -EIO;
}
LOG_DBG("%s: chip id 0x%x", dev->name, id.whoami);
/* Restore default configuration */
if (lps22df_init_set(ctx, LPS22DF_RESET) < 0) {
LOG_ERR("%s: Not able to reset device", dev->name);
return -EIO;
}
do {
if (!--tries) {
LOG_DBG("sw reset timed out");
return -ETIMEDOUT;
}
k_usleep(LPS2XDF_SWRESET_WAIT_TIME_US);
if (lps22df_status_get(ctx, &status) < 0) {
return -EIO;
}
} while (status.sw_reset);
/* Set bdu and if_inc recommended for driver usage */
if (lps22df_init_set(ctx, LPS22DF_DRV_RDY) < 0) {
LOG_ERR("%s: Not able to set device to ready state", dev->name);
return -EIO;
}
if (ON_I3C_BUS(cfg)) {
lps22df_bus_mode_t bus_mode;
/* Select bus interface */
lps22df_bus_mode_get(ctx, &bus_mode);
bus_mode.filter = LPS22DF_AUTO;
bus_mode.interface = LPS22DF_SEL_BY_HW;
lps22df_bus_mode_set(ctx, &bus_mode);
}
/* set sensor default odr */
LOG_DBG("%s: odr: %d", dev->name, cfg->odr);
ret = lps22df_mode_set_odr_raw(dev, cfg->odr);
if (ret < 0) {
LOG_ERR("%s: Failed to set odr %d", dev->name, cfg->odr);
return ret;
}
#ifdef CONFIG_LPS2XDF_TRIGGER
if (cfg->trig_enabled) {
if (lps2xdf_init_interrupt(dev, DEVICE_VARIANT_LPS22DF) < 0) {
LOG_ERR("Failed to initialize interrupt.");
return -EIO;
}
}
#endif
return 0;
}
``` | /content/code_sandbox/drivers/sensor/st/lps2xdf/lps22df.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 1,821 |
```c
/* ST Microelectronics LPS2XDF pressure and temperature sensor
*
*
*
* Datasheet:
* path_to_url
* path_to_url
*/
#include <zephyr/drivers/sensor.h>
#include <zephyr/kernel.h>
#include <zephyr/device.h>
#include <zephyr/init.h>
#include <zephyr/sys/byteorder.h>
#include <zephyr/sys/__assert.h>
#include <zephyr/logging/log.h>
#include "lps2xdf.h"
#if DT_HAS_COMPAT_STATUS_OKAY(st_lps22df)
#include "lps22df.h"
#endif
#if DT_HAS_COMPAT_STATUS_OKAY(st_lps28dfw)
#include "lps28dfw.h"
#endif
LOG_MODULE_REGISTER(LPS2XDF, CONFIG_SENSOR_LOG_LEVEL);
static const uint16_t lps2xdf_map[] = {0, 1, 4, 10, 25, 50, 75, 100, 200};
static int lps2xdf_odr_set(const struct device *dev, uint16_t freq)
{
int odr;
const struct lps2xdf_config *const cfg = dev->config;
const struct lps2xdf_chip_api *chip_api = cfg->chip_api;
for (odr = 0; odr < ARRAY_SIZE(lps2xdf_map); odr++) {
if (freq == lps2xdf_map[odr]) {
break;
}
}
if (odr == ARRAY_SIZE(lps2xdf_map)) {
LOG_DBG("bad frequency");
return -EINVAL;
}
if (chip_api->mode_set_odr_raw(dev, odr)) {
LOG_DBG("failed to set sampling rate");
return -EIO;
}
return 0;
}
static int lps2xdf_attr_set(const struct device *dev, enum sensor_channel chan,
enum sensor_attribute attr, const struct sensor_value *val)
{
if (chan != SENSOR_CHAN_ALL) {
LOG_WRN("attr_set() not supported on this channel.");
return -ENOTSUP;
}
switch (attr) {
case SENSOR_ATTR_SAMPLING_FREQUENCY:
return lps2xdf_odr_set(dev, val->val1);
default:
LOG_DBG("operation not supported.");
return -ENOTSUP;
}
return 0;
}
static inline void lps2xdf_press_convert(const struct device *dev,
struct sensor_value *val,
int32_t raw_val)
{
const struct lps2xdf_config *const cfg = dev->config;
int32_t press_tmp = raw_val >> 8; /* raw value is left aligned (24 msb) */
int divider;
/* Pressure sensitivity is:
* - 4096 LSB/hPa for Full-Scale of 260 - 1260 hPa:
* - 2048 LSB/hPa for Full-Scale of 260 - 4060 hPa:
* Also convert hPa into kPa
*/
if (cfg->fs == 0) {
divider = 40960;
} else {
divider = 20480;
}
val->val1 = press_tmp / divider;
/* For the decimal part use (3125 / 128) as a factor instead of
* (1000000 / 40960) to avoid int32 overflow
*/
val->val2 = (press_tmp % divider) * 3125 / 128;
}
static inline void lps2xdf_temp_convert(struct sensor_value *val, int16_t raw_val)
{
/* Temperature sensitivity is 100 LSB/deg C */
val->val1 = raw_val / 100;
val->val2 = ((int32_t)raw_val % 100) * 10000;
}
static int lps2xdf_channel_get(const struct device *dev, enum sensor_channel chan,
struct sensor_value *val)
{
struct lps2xdf_data *data = dev->data;
if (chan == SENSOR_CHAN_PRESS) {
lps2xdf_press_convert(dev, val, data->sample_press);
} else if (chan == SENSOR_CHAN_AMBIENT_TEMP) {
lps2xdf_temp_convert(val, data->sample_temp);
} else {
return -ENOTSUP;
}
return 0;
}
static int lps2xdf_sample_fetch(const struct device *dev, enum sensor_channel chan)
{
const struct lps2xdf_config *const cfg = dev->config;
const struct lps2xdf_chip_api *chip_api = cfg->chip_api;
__ASSERT_NO_MSG(chan == SENSOR_CHAN_ALL);
return chip_api->sample_fetch(dev, chan);
}
static const struct sensor_driver_api lps2xdf_driver_api = {
.attr_set = lps2xdf_attr_set,
.sample_fetch = lps2xdf_sample_fetch,
.channel_get = lps2xdf_channel_get,
#if CONFIG_LPS2XDF_TRIGGER
.trigger_set = lps2xdf_trigger_set,
#endif
};
#ifdef CONFIG_LPS2XDF_TRIGGER
#define LPS2XDF_CFG_IRQ(inst) \
.trig_enabled = true, \
.gpio_int = GPIO_DT_SPEC_INST_GET(inst, drdy_gpios), \
.drdy_pulsed = DT_INST_PROP(inst, drdy_pulsed)
#else
#define LPS2XDF_CFG_IRQ(inst)
#endif /* CONFIG_LPS2XDF_TRIGGER */
#define LPS2XDF_CONFIG_COMMON(inst, name) \
.odr = DT_INST_PROP(inst, odr), \
.lpf = DT_INST_PROP(inst, lpf), \
.avg = DT_INST_PROP(inst, avg), \
.chip_api = &name##_chip_api, \
IF_ENABLED(DT_INST_NODE_HAS_COMPAT(inst, st_lps28dfw), \
(.fs = DT_INST_PROP(inst, fs),)) \
IF_ENABLED(DT_INST_NODE_HAS_PROP(inst, drdy_gpios), \
(LPS2XDF_CFG_IRQ(inst)))
#define LPS2XDF_SPI_OPERATION (SPI_WORD_SET(8) | SPI_OP_MODE_MASTER | \
SPI_MODE_CPOL | SPI_MODE_CPHA)
#define LPS2XDF_CONFIG_SPI(inst, name) \
{ \
STMEMSC_CTX_SPI(&lps2xdf_config_##name##_##inst.stmemsc_cfg), \
.stmemsc_cfg = { \
.spi = SPI_DT_SPEC_INST_GET(inst, LPS2XDF_SPI_OPERATION, 0), \
}, \
LPS2XDF_CONFIG_COMMON(inst, name) \
}
#define LPS2XDF_CONFIG_I2C(inst, name) \
{ \
STMEMSC_CTX_I2C(&lps2xdf_config_##name##_##inst.stmemsc_cfg), \
.stmemsc_cfg = { \
.i2c = I2C_DT_SPEC_INST_GET(inst), \
}, \
LPS2XDF_CONFIG_COMMON(inst, name) \
}
#define LPS2XDF_CONFIG_I3C(inst, name) \
{ \
STMEMSC_CTX_I3C(&lps2xdf_config_##name##_##inst.stmemsc_cfg), \
.stmemsc_cfg = { \
.i3c = &lps2xdf_data_##name##_##inst.i3c_dev, \
}, \
.i3c.bus = DEVICE_DT_GET(DT_INST_BUS(inst)), \
.i3c.dev_id = I3C_DEVICE_ID_DT_INST(inst), \
LPS2XDF_CONFIG_COMMON(inst, name) \
}
#define LPS2XDF_CONFIG_I3C_OR_I2C(inst, name) \
COND_CODE_0(DT_INST_PROP_BY_IDX(inst, reg, 1), \
(LPS2XDF_CONFIG_I2C(inst, name)), \
(LPS2XDF_CONFIG_I3C(inst, name)))
#define LPS2XDF_DEFINE(inst, name) \
static struct lps2xdf_data lps2xdf_data_##name##_##inst; \
static const struct lps2xdf_config lps2xdf_config_##name##_##inst = COND_CODE_1( \
DT_INST_ON_BUS(inst, spi), \
(LPS2XDF_CONFIG_SPI(inst, name)), \
(COND_CODE_1(DT_INST_ON_BUS(inst, i3c), \
(LPS2XDF_CONFIG_I3C_OR_I2C(inst, name)), \
(LPS2XDF_CONFIG_I2C(inst, name))))); \
\
SENSOR_DEVICE_DT_INST_DEFINE(inst, name##_init, NULL, &lps2xdf_data_##name##_##inst, \
&lps2xdf_config_##name##_##inst, POST_KERNEL, \
CONFIG_SENSOR_INIT_PRIORITY, &lps2xdf_driver_api);
#define DT_DRV_COMPAT st_lps22df
DT_INST_FOREACH_STATUS_OKAY_VARGS(LPS2XDF_DEFINE, DT_DRV_COMPAT)
#undef DT_DRV_COMPAT
#define DT_DRV_COMPAT st_lps28dfw
DT_INST_FOREACH_STATUS_OKAY_VARGS(LPS2XDF_DEFINE, DT_DRV_COMPAT)
#undef DT_DRV_COMPAT
``` | /content/code_sandbox/drivers/sensor/st/lps2xdf/lps2xdf.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 1,963 |
```unknown
# zephyr-keep-sorted-start
source "drivers/sensor/microchip/mchp_tach_xec/Kconfig"
source "drivers/sensor/microchip/mcp9600/Kconfig"
source "drivers/sensor/microchip/mcp970x/Kconfig"
source "drivers/sensor/microchip/mcp9808/Kconfig"
source "drivers/sensor/microchip/tcn75a/Kconfig"
# zephyr-keep-sorted-stop
``` | /content/code_sandbox/drivers/sensor/microchip/Kconfig | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 100 |
```unknown
# Microchip mec15xx tachometer sensor configuration options
config TACH_XEC
bool "XEC Tachometer sensor"
default y
depends on DT_HAS_MICROCHIP_XEC_TACH_ENABLED
depends on SOC_FAMILY_MICROCHIP_MEC
select PINCTRL
help
Enable the Microchip XEC tachometer sensor.
if TACH_XEC
choice
prompt "Number of tach edges"
default TACH_XEC_5_TACH_EDGES
help
This value represents the number of Tach edges that
will be used to determine the interval for which the number of
100KHz pulses will be counted.
config TACH_XEC_9_TACH_EDGES
bool "Configure 9 tach edges or 4 tach periods"
config TACH_XEC_5_TACH_EDGES
bool "Configure 5 tach edges or 2 tach periods"
config TACH_XEC_3_TACH_EDGES
bool "Configure 3 tach edges or 1 tach period"
config TACH_XEC_2_TACH_EDGES
bool "Configure 2 tach edges or 1/2 tach period"
endchoice
config TACH_XEC_EDGES
int
range 0 3
default 0 if TACH_XEC_2_TACH_EDGES
default 1 if TACH_XEC_3_TACH_EDGES
default 2 if TACH_XEC_5_TACH_EDGES
default 3 if TACH_XEC_9_TACH_EDGES
endif #TACH_XEC
``` | /content/code_sandbox/drivers/sensor/microchip/mchp_tach_xec/Kconfig | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 338 |
```c
/*
*
*/
#define DT_DRV_COMPAT microchip_xec_tach
#include <errno.h>
#include <zephyr/kernel.h>
#include <zephyr/device.h>
#include <zephyr/arch/cpu.h>
#ifdef CONFIG_SOC_SERIES_MEC172X
#include <zephyr/drivers/clock_control/mchp_xec_clock_control.h>
#include <zephyr/drivers/interrupt_controller/intc_mchp_xec_ecia.h>
#endif
#include <zephyr/drivers/pinctrl.h>
#include <zephyr/drivers/sensor.h>
#include <soc.h>
#include <zephyr/sys/sys_io.h>
#include <zephyr/logging/log.h>
#include <zephyr/pm/device.h>
#include <zephyr/pm/policy.h>
LOG_MODULE_REGISTER(tach_xec, CONFIG_SENSOR_LOG_LEVEL);
struct tach_xec_config {
struct tach_regs * const regs;
uint8_t girq;
uint8_t girq_pos;
uint8_t pcr_idx;
uint8_t pcr_pos;
const struct pinctrl_dev_config *pcfg;
};
struct tach_xec_data {
uint32_t control;
uint16_t count;
};
#define FAN_STOPPED 0xFFFFU
#define COUNT_100KHZ_SEC 100000U
#define SEC_TO_MINUTE 60U
#define PIN_STS_TIMEOUT 20U
#define TACH_CTRL_EDGES (CONFIG_TACH_XEC_EDGES << \
MCHP_TACH_CTRL_NUM_EDGES_POS)
int tach_xec_sample_fetch(const struct device *dev, enum sensor_channel chan)
{
ARG_UNUSED(chan);
const struct tach_xec_config * const cfg = dev->config;
struct tach_xec_data * const data = dev->data;
struct tach_regs * const tach = cfg->regs;
uint8_t poll_count = 0;
pm_policy_state_lock_get(PM_STATE_SUSPEND_TO_IDLE, PM_ALL_SUBSTATES);
while (poll_count < PIN_STS_TIMEOUT) {
/* See whether internal counter is already latched */
if (tach->STATUS & MCHP_TACH_STS_CNT_RDY) {
data->count =
tach->CONTROL >> MCHP_TACH_CTRL_COUNTER_POS;
break;
}
poll_count++;
/* Allow other threads to run while we sleep */
k_usleep(USEC_PER_MSEC);
}
pm_policy_state_lock_put(PM_STATE_SUSPEND_TO_IDLE, PM_ALL_SUBSTATES);
if (poll_count == PIN_STS_TIMEOUT) {
return -EINVAL;
}
/* We interpret a fan stopped or jammed as 0 */
if (data->count == FAN_STOPPED) {
data->count = 0U;
}
return 0;
}
static int tach_xec_channel_get(const struct device *dev,
enum sensor_channel chan,
struct sensor_value *val)
{
struct tach_xec_data * const data = dev->data;
if (chan != SENSOR_CHAN_RPM) {
return -ENOTSUP;
}
/* Convert the count per 100khz cycles to rpm */
if (data->count != FAN_STOPPED && data->count != 0U) {
val->val1 = (SEC_TO_MINUTE * COUNT_100KHZ_SEC)/data->count;
val->val2 = 0U;
} else {
val->val1 = 0U;
}
val->val2 = 0U;
return 0;
}
static void tach_xec_sleep_clr(const struct device *dev)
{
const struct tach_xec_config * const cfg = dev->config;
struct pcr_regs * const pcr = (struct pcr_regs * const)(
DT_REG_ADDR_BY_IDX(DT_NODELABEL(pcr), 0));
#ifdef CONFIG_SOC_SERIES_MEC172X
pcr->SLP_EN[cfg->pcr_idx] &= ~BIT(cfg->pcr_pos);
#else
uintptr_t addr = (uintptr_t)&pcr->SLP_EN0 + (4u * cfg->pcr_idx);
uint32_t pcr_val = sys_read32(addr) & ~BIT(cfg->pcr_pos);
sys_write32(pcr_val, addr);
#endif
}
#ifdef CONFIG_PM_DEVICE
static int tach_xec_pm_action(const struct device *dev, enum pm_device_action action)
{
const struct tach_xec_config * const cfg = dev->config;
struct tach_xec_data * const data = dev->data;
struct tach_regs * const tach = cfg->regs;
int ret = 0;
switch (action) {
case PM_DEVICE_ACTION_RESUME:
if (data->control & MCHP_TACH_CTRL_EN) {
tach->CONTROL |= MCHP_TACH_CTRL_EN;
data->control &= (~MCHP_TACH_CTRL_EN);
}
break;
case PM_DEVICE_ACTION_SUSPEND:
if (tach->CONTROL & MCHP_TACH_CTRL_EN) {
/* Take a backup */
data->control = tach->CONTROL;
tach->CONTROL &= (~MCHP_TACH_CTRL_EN);
}
break;
default:
ret = -ENOTSUP;
}
return ret;
}
#endif /* CONFIG_PM_DEVICE */
static int tach_xec_init(const struct device *dev)
{
const struct tach_xec_config * const cfg = dev->config;
struct tach_regs * const tach = cfg->regs;
int ret = pinctrl_apply_state(cfg->pcfg, PINCTRL_STATE_DEFAULT);
if (ret != 0) {
LOG_ERR("XEC TACH pinctrl init failed (%d)", ret);
return ret;
}
tach_xec_sleep_clr(dev);
tach->CONTROL = MCHP_TACH_CTRL_READ_MODE_100K_CLOCK |
TACH_CTRL_EDGES |
MCHP_TACH_CTRL_FILTER_EN |
MCHP_TACH_CTRL_EN;
return 0;
}
static const struct sensor_driver_api tach_xec_driver_api = {
.sample_fetch = tach_xec_sample_fetch,
.channel_get = tach_xec_channel_get,
};
#define XEC_TACH_CONFIG(inst) \
static const struct tach_xec_config tach_xec_config_##inst = { \
.regs = (struct tach_regs * const)DT_INST_REG_ADDR(inst), \
.girq = DT_INST_PROP_BY_IDX(inst, girqs, 0), \
.girq_pos = DT_INST_PROP_BY_IDX(inst, girqs, 1), \
.pcr_idx = DT_INST_PROP_BY_IDX(inst, pcrs, 0), \
.pcr_pos = DT_INST_PROP_BY_IDX(inst, pcrs, 1), \
.pcfg = PINCTRL_DT_INST_DEV_CONFIG_GET(inst), \
}
#define TACH_XEC_DEVICE(id) \
static struct tach_xec_data tach_xec_data_##id; \
\
PINCTRL_DT_INST_DEFINE(id); \
\
XEC_TACH_CONFIG(id); \
\
PM_DEVICE_DT_INST_DEFINE(id, tach_xec_pm_action); \
\
SENSOR_DEVICE_DT_INST_DEFINE(id, \
tach_xec_init, \
PM_DEVICE_DT_INST_GET(id), \
&tach_xec_data_##id, \
&tach_xec_config_##id, \
POST_KERNEL, \
CONFIG_SENSOR_INIT_PRIORITY, \
&tach_xec_driver_api);
DT_INST_FOREACH_STATUS_OKAY(TACH_XEC_DEVICE)
``` | /content/code_sandbox/drivers/sensor/microchip/mchp_tach_xec/tach_mchp_xec.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 1,639 |
```unknown
# I2C Compatible, Thermocouple EMF to Temperature Converter
#
#
config MCP9600
bool "MCP9600 i2c thermocouple temperature sensor"
default y
depends on DT_HAS_MICROCHIP_MCP9600_ENABLED
select I2C
help
Enable driver for MCP9600 i2c thermocouple temperature sensor.
``` | /content/code_sandbox/drivers/sensor/microchip/mcp9600/Kconfig | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 78 |
```c
/*
*
*/
#define DT_DRV_COMPAT microchip_mcp9600
#include <zephyr/device.h>
#include <zephyr/drivers/i2c.h>
#include <zephyr/drivers/sensor.h>
#include <zephyr/kernel.h>
#include <zephyr/logging/log.h>
LOG_MODULE_REGISTER(MCP9600, CONFIG_SENSOR_LOG_LEVEL);
#define MCP9600_REG_TEMP_HOT 0x00
#define MCP9600_REG_TEMP_DIFF 0x01
#define MCP9600_REG_TEMP_COLD 0x02
#define MCP9600_REG_RAW_ADC 0x03
#define MCP9600_REG_STATUS 0x04
#define MCP9600_REG_TC_CONFIG 0x05
#define MCP9600_REG_DEV_CONFIG 0x06
#define MCP9600_REG_A1_CONFIG 0x08
#define MCP9600_REG_A2_CONFIG 0x09
#define MCP9600_REG_A3_CONFIG 0x0A
#define MCP9600_REG_A4_CONFIG 0x0B
#define MCP9600_A1_HYST 0x0C
#define MCP9600_A2_HYST 0x0D
#define MCP9600_A3_HYST 0x0E
#define MCP9600_A4_HYST 0x0F
#define MCP9600_A1_LIMIT 0x10
#define MCP9600_A2_LIMIT 0x11
#define MCP9600_A3_LIMIT 0x12
#define MCP9600_A4_LIMIT 0x13
#define MCP9600_REG_ID_REVISION 0x20
struct mcp9600_data {
int32_t temp;
};
struct mcp9600_config {
const struct i2c_dt_spec bus;
};
static int mcp9600_reg_read(const struct device *dev, uint8_t start, uint8_t *buf, int size)
{
const struct mcp9600_config *cfg = dev->config;
return i2c_burst_read_dt(&cfg->bus, start, buf, size);
}
static int mcp9600_sample_fetch(const struct device *dev, enum sensor_channel chan)
{
struct mcp9600_data *data = dev->data;
uint8_t buf[2];
int ret;
if (chan != SENSOR_CHAN_ALL && chan != SENSOR_CHAN_AMBIENT_TEMP) {
LOG_ERR("Unsupported sensor channel");
return -ENOTSUP;
}
/* read signed 16 bit double-buffered register value */
ret = mcp9600_reg_read(dev, MCP9600_REG_TEMP_HOT, buf, sizeof(buf));
if (ret < 0) {
data->temp = 1;
return ret;
}
/* device's hot junction register is a signed int */
data->temp = (int32_t)(int16_t)(buf[0] << 8) | buf[1];
/* 0.0625C resolution per LSB */
data->temp *= 62500;
return 0;
}
static int mcp9600_channel_get(const struct device *dev, enum sensor_channel chan,
struct sensor_value *val)
{
struct mcp9600_data *data = dev->data;
if (chan != SENSOR_CHAN_AMBIENT_TEMP) {
return -ENOTSUP;
}
if (data->temp == 1) {
return -EINVAL;
}
val->val1 = data->temp / 1000000;
val->val2 = data->temp % 1000000;
return 0;
}
static const struct sensor_driver_api mcp9600_api = {
.sample_fetch = mcp9600_sample_fetch,
.channel_get = mcp9600_channel_get,
};
static int mcp9600_init(const struct device *dev)
{
const struct mcp9600_config *cfg = dev->config;
uint8_t buf[2];
int ret;
if (!i2c_is_ready_dt(&cfg->bus)) {
LOG_ERR("mcp9600 i2c bus %s not ready", cfg->bus.bus->name);
return -ENODEV;
}
ret = mcp9600_reg_read(dev, MCP9600_REG_ID_REVISION, buf, sizeof(buf));
LOG_DBG("id: 0x%02x version: 0x%02x", buf[0], buf[1]);
return ret;
}
#define MCP9600_DEFINE(id) \
static struct mcp9600_data mcp9600_data_##id; \
\
static const struct mcp9600_config mcp9600_config_##id = { \
.bus = I2C_DT_SPEC_INST_GET(id), \
}; \
\
SENSOR_DEVICE_DT_INST_DEFINE(id, mcp9600_init, NULL, &mcp9600_data_##id, \
&mcp9600_config_##id, POST_KERNEL, \
CONFIG_SENSOR_INIT_PRIORITY, &mcp9600_api);
DT_INST_FOREACH_STATUS_OKAY(MCP9600_DEFINE)
``` | /content/code_sandbox/drivers/sensor/microchip/mcp9600/mcp9600.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 1,050 |
```objective-c
/*
*
*/
#ifndef _DRIVERS_SENSOR_TCN75A_H_
#define _DRIVERS_SENSOR_TCN75A_H_
#include <zephyr/drivers/gpio.h>
#include <zephyr/drivers/i2c.h>
#include <zephyr/drivers/sensor.h>
#include <zephyr/sys/byteorder.h>
#define TCN75A_TEMP_REG 0x0
#define TCN75A_CONFIG_REG 0x1
#define TCN75A_THYST_REG 0x2
#define TCN75A_TSET_REG 0x3
/* TCN75A TEMP register constants */
#define TCN75A_TEMP_MSB_POS 8
#define TCN75A_TEMP_MSB_MASK 0xFF00
#define TCN75A_TEMP_LSB_MASK 0xFF
#define TCN75A_TEMP_LSB_POS 0
/* TCN75A CONFIG register constants */
#define TCN75A_CONFIG_ONEDOWN BIT(7)
#define TCN75A_CONFIG_RES(x) (((x) & 0x3) << 5)
#define TCN75A_CONFIG_INT_EN 0x2
#define TCN75A_CONFIG_SHUTDOWN 0x1
struct tcn75a_config {
struct i2c_dt_spec i2c_spec;
bool oneshot_mode;
uint8_t resolution;
#ifdef CONFIG_TCN75A_TRIGGER
struct gpio_dt_spec alert_gpios;
#endif
};
struct tcn75a_data {
uint16_t temp_sample;
#ifdef CONFIG_TCN75A_TRIGGER
const struct device *dev;
struct gpio_callback gpio_cb;
sensor_trigger_handler_t sensor_cb;
const struct sensor_trigger *sensor_trig;
#endif
#ifdef CONFIG_TCN75A_TRIGGER_GLOBAL_THREAD
struct k_work work;
#endif
#ifdef CONFIG_TCN75A_TRIGGER_OWN_THREAD
K_KERNEL_STACK_MEMBER(thread_stack, CONFIG_TCN75A_THREAD_STACK_SIZE);
struct k_thread thread;
struct k_sem trig_sem;
#endif
};
/* Helpers to convert from TCN75A temperature fixed point format
* to sensor val2 format. When the LSB of the TCN75A temperature sample
* is treated as an integer, the format to convert to sensor val2 is
* FIXED_POINT_VAL * 3906.25
*/
#define TCN75A_FIXED_PT_TO_SENSOR(x) (((x)*3906) + ((x) >> 2))
/* This conversion is imprecise, but because the 4 least significant bits
* of the temperature register aren't used, it doesn't matter.
*/
#define TCN75A_SENSOR_TO_FIXED_PT(x) ((x) / 3906)
#ifdef CONFIG_TCN75A_TRIGGER
int tcn75a_trigger_init(const struct device *dev);
int tcn75a_attr_get(const struct device *dev, enum sensor_channel chan, enum sensor_attribute attr,
struct sensor_value *val);
int tcn75a_attr_set(const struct device *dev, enum sensor_channel chan, enum sensor_attribute attr,
const struct sensor_value *val);
int tcn75a_trigger_set(const struct device *dev, const struct sensor_trigger *trig,
sensor_trigger_handler_t handler);
#endif
int tcn75a_sample_fetch(const struct device *dev, enum sensor_channel chan);
#endif /* _DRIVERS_SENSOR_TCN75A_H_ */
``` | /content/code_sandbox/drivers/sensor/microchip/tcn75a/tcn75a.h | objective-c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 688 |
```unknown
config TCN75A
bool "TCN75A Ambient Temperature Sensor"
default y
depends on DT_HAS_MICROCHIP_TCN75A_ENABLED
select I2C
help
Enable TCN75A ambient temperature to digital converter
if TCN75A
choice
prompt "TCN75A Trigger mode"
default TCN75A_TRIGGER_NONE
config TCN75A_TRIGGER_NONE
bool "No trigger"
config TCN75A_TRIGGER_OWN_THREAD
bool "Use own thread"
select TCN75A_TRIGGER
config TCN75A_TRIGGER_GLOBAL_THREAD
bool "Use global thread"
select TCN75A_TRIGGER
endchoice
config TCN75A_TRIGGER
bool
help
Enable interrupt based trigger support for TCN75A. Requires that
the sensor be set to continuous sample mode.
if TCN75A_TRIGGER_OWN_THREAD
config TCN75A_THREAD_PRIORITY
int "Own thread priority"
default 10
config TCN75A_THREAD_STACK_SIZE
int "Own thread stack size"
default 1024
endif # TCN75A_TRIGGER_OWN_THREAD
endif # TCN75A
``` | /content/code_sandbox/drivers/sensor/microchip/tcn75a/Kconfig | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 244 |
```c
/*
*
*/
#include <zephyr/logging/log.h>
LOG_MODULE_DECLARE(tcn75a, CONFIG_SENSOR_LOG_LEVEL);
#include "tcn75a.h"
int tcn75a_trigger_set(const struct device *dev, const struct sensor_trigger *trig,
sensor_trigger_handler_t handler)
{
const struct tcn75a_config *config = dev->config;
struct tcn75a_data *data = dev->data;
int ret;
if (trig->type != SENSOR_TRIG_THRESHOLD) {
return -ENOTSUP;
}
if ((trig->chan != SENSOR_CHAN_ALL) && (trig->chan != SENSOR_CHAN_AMBIENT_TEMP)) {
return -ENOTSUP;
}
data->sensor_cb = handler;
data->sensor_trig = trig;
/* TCN75A starts in comparator mode by default, switch it to
* use interrupt mode.
*/
ret = i2c_reg_update_byte_dt(&config->i2c_spec, TCN75A_CONFIG_REG, TCN75A_CONFIG_INT_EN,
TCN75A_CONFIG_INT_EN);
if (ret < 0) {
return ret;
}
ret = gpio_pin_interrupt_configure_dt(&config->alert_gpios, GPIO_INT_EDGE_TO_ACTIVE);
if (ret < 0) {
return ret;
}
return ret;
}
int tcn75a_attr_set(const struct device *dev, enum sensor_channel chan, enum sensor_attribute attr,
const struct sensor_value *val)
{
const struct tcn75a_config *config = dev->config;
uint8_t tx_buf[3];
if ((chan != SENSOR_CHAN_AMBIENT_TEMP) && (chan != SENSOR_CHAN_ALL)) {
return -ENOTSUP;
}
switch (attr) {
case SENSOR_ATTR_LOWER_THRESH:
tx_buf[0] = TCN75A_THYST_REG;
break;
case SENSOR_ATTR_UPPER_THRESH:
tx_buf[0] = TCN75A_TSET_REG;
break;
default:
return -ENOTSUP;
}
/* Convert sensor val to fixed point */
tx_buf[1] = (uint8_t)val->val1;
tx_buf[2] = TCN75A_SENSOR_TO_FIXED_PT(val->val2);
LOG_DBG("Writing 0x%02X to limit reg %s", *(uint16_t *)(tx_buf + 1),
tx_buf[0] == TCN75A_THYST_REG ? "THYST" : "TSET");
return i2c_write_dt(&config->i2c_spec, tx_buf, 3);
}
int tcn75a_attr_get(const struct device *dev, enum sensor_channel chan, enum sensor_attribute attr,
struct sensor_value *val)
{
const struct tcn75a_config *config = dev->config;
uint8_t config_reg;
uint8_t rx_buf[2];
uint16_t limit, temp_lsb;
int ret;
if ((chan != SENSOR_CHAN_AMBIENT_TEMP) && (chan != SENSOR_CHAN_ALL)) {
return -ENOTSUP;
}
switch (attr) {
case SENSOR_ATTR_LOWER_THRESH:
config_reg = TCN75A_THYST_REG;
break;
case SENSOR_ATTR_UPPER_THRESH:
config_reg = TCN75A_TSET_REG;
break;
default:
return -ENOTSUP;
}
ret = i2c_write_read_dt(&config->i2c_spec, &config_reg, 1, rx_buf, 2);
if (ret < 0) {
return ret;
}
limit = sys_get_be16(rx_buf);
LOG_DBG("Read 0x%02X from %s", limit, config_reg == TCN75A_THYST_REG ? "THYST" : "TSET");
/* Convert fixed point to sensor value */
val->val1 = limit >> TCN75A_TEMP_MSB_POS;
temp_lsb = (limit & TCN75A_TEMP_LSB_MASK);
val->val2 = TCN75A_FIXED_PT_TO_SENSOR(temp_lsb);
return ret;
}
static void tcn75a_handle_int(const struct device *dev)
{
struct tcn75a_data *data = dev->data;
/* Note that once the temperature rises
* above T_SET, the sensor will not trigger another interrupt until
* it falls below T_HYST (or vice versa for falling below T_HYST).
*
* Reading from any register will de-assert the interrupt.
*/
if (data->sensor_cb) {
data->sensor_cb(dev, data->sensor_trig);
}
}
static void tcn75a_gpio_callback(const struct device *dev, struct gpio_callback *cb,
uint32_t pin_mask)
{
struct tcn75a_data *data = CONTAINER_OF(cb, struct tcn75a_data, gpio_cb);
const struct tcn75a_config *config = data->dev->config;
if ((pin_mask & BIT(config->alert_gpios.pin)) == 0U) {
return;
}
#if defined(CONFIG_TCN75A_TRIGGER_OWN_THREAD)
k_sem_give(&data->trig_sem);
#elif defined(CONFIG_TCN75A_TRIGGER_GLOBAL_THREAD)
k_work_submit(&data->work);
#endif
}
#ifdef CONFIG_TCN75A_TRIGGER_OWN_THREAD
static void tcn75a_thread_main(void *p1, void *p2, void *p3)
{
ARG_UNUSED(p2);
ARG_UNUSED(p3);
struct tcn75a_data *data = p1;
while (true) {
k_sem_take(&data->trig_sem, K_FOREVER);
tcn75a_handle_int(data->dev);
}
}
#endif
#ifdef CONFIG_TCN75A_TRIGGER_GLOBAL_THREAD
static void tcn75a_work_handler(struct k_work *work)
{
struct tcn75a_data *data = CONTAINER_OF(work, struct tcn75a_data, work);
tcn75a_handle_int(data->dev);
}
#endif
int tcn75a_trigger_init(const struct device *dev)
{
const struct tcn75a_config *config = dev->config;
struct tcn75a_data *data = dev->data;
int ret;
/* Save config pointer */
data->dev = dev;
if (!gpio_is_ready_dt(&config->alert_gpios)) {
LOG_ERR("alert GPIO device is not ready");
return -ENODEV;
}
ret = gpio_pin_configure_dt(&config->alert_gpios, GPIO_INPUT);
if (ret < 0) {
return ret;
}
gpio_init_callback(&data->gpio_cb, tcn75a_gpio_callback, BIT(config->alert_gpios.pin));
ret = gpio_add_callback(config->alert_gpios.port, &data->gpio_cb);
#if defined(CONFIG_TCN75A_TRIGGER_OWN_THREAD)
k_sem_init(&data->trig_sem, 0, K_SEM_MAX_LIMIT);
k_thread_create(&data->thread, data->thread_stack, CONFIG_TCN75A_THREAD_STACK_SIZE,
tcn75a_thread_main, data, NULL, NULL,
K_PRIO_COOP(CONFIG_TCN75A_THREAD_PRIORITY), 0, K_NO_WAIT);
#elif defined(CONFIG_TCN75A_TRIGGER_GLOBAL_THREAD)
data->work.handler = tcn75a_work_handler;
#endif
return ret;
}
``` | /content/code_sandbox/drivers/sensor/microchip/tcn75a/tcn75a_trigger.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 1,537 |
```c
/*
*
*/
#define DT_DRV_COMPAT microchip_tcn75a
#include <zephyr/logging/log.h>
LOG_MODULE_REGISTER(tcn75a, CONFIG_SENSOR_LOG_LEVEL);
#include "tcn75a.h"
int tcn75a_sample_fetch(const struct device *dev, enum sensor_channel chan)
{
const struct tcn75a_config *config = dev->config;
struct tcn75a_data *data = dev->data;
int ret;
uint8_t temp_reg = TCN75A_TEMP_REG;
uint8_t rx_buf[2];
uint8_t adc_conf[2] = {TCN75A_CONFIG_REG, 0x0};
/* This sensor only supports ambient temperature */
if ((chan != SENSOR_CHAN_ALL) && (chan != SENSOR_CHAN_AMBIENT_TEMP)) {
return -ENOTSUP;
}
if (config->oneshot_mode) {
/* Oneshot mode, requires one shot bit to be set in config register */
adc_conf[1] = TCN75A_CONFIG_ONEDOWN;
ret = i2c_write_dt(&config->i2c_spec, adc_conf, 2);
if (ret < 0) {
return ret;
}
}
/* Fetch a sample from the 2 byte ambient temperature register */
ret = i2c_write_read_dt(&config->i2c_spec, &temp_reg, sizeof(temp_reg),
rx_buf, sizeof(rx_buf));
if (ret < 0) {
return ret;
}
data->temp_sample = sys_get_be16(rx_buf);
LOG_DBG("Raw sample: 0x%04x", data->temp_sample);
return ret;
}
static int tcn75a_channel_get(const struct device *dev, enum sensor_channel chan,
struct sensor_value *val)
{
struct tcn75a_data *data = dev->data;
uint32_t temp_lsb;
if (chan != SENSOR_CHAN_AMBIENT_TEMP) {
return -ENOTSUP;
}
/* Convert fixed point to sensor value */
val->val1 = data->temp_sample >> TCN75A_TEMP_MSB_POS;
temp_lsb = (data->temp_sample & TCN75A_TEMP_LSB_MASK);
val->val2 = TCN75A_FIXED_PT_TO_SENSOR(temp_lsb);
return 0;
}
static const struct sensor_driver_api tcn75a_api = {
.sample_fetch = &tcn75a_sample_fetch,
.channel_get = &tcn75a_channel_get,
#ifdef CONFIG_TCN75A_TRIGGER
.attr_get = &tcn75a_attr_get,
.attr_set = &tcn75a_attr_set,
.trigger_set = &tcn75a_trigger_set,
#endif
};
static int tcn75a_init(const struct device *dev)
{
const struct tcn75a_config *config = dev->config;
uint8_t adc_conf[2] = {TCN75A_CONFIG_REG, 0x0};
if (!i2c_is_ready_dt(&config->i2c_spec)) {
LOG_ERR("I2C bus is not ready");
return -ENODEV;
}
/* Set user selected resolution */
adc_conf[1] |= TCN75A_CONFIG_RES(config->resolution);
if (config->oneshot_mode) {
if (adc_conf[1] != 0) {
/* Oneshot mode only supports 9 bit resolution */
LOG_ERR("Oneshot mode requires 9 bit resolution");
return -ENODEV;
}
adc_conf[1] |= TCN75A_CONFIG_SHUTDOWN;
}
#ifdef CONFIG_TCN75A_TRIGGER
/* If user supplies an ALERT gpio, assume they want trigger support. */
if (config->alert_gpios.port != NULL) {
int ret;
if (config->oneshot_mode) {
LOG_ERR("Oneshot mode not supported with trigger");
return -ENODEV;
}
ret = tcn75a_trigger_init(dev);
if (ret < 0) {
return ret;
}
}
#endif
return i2c_write_dt(&config->i2c_spec, adc_conf, 2);
}
#ifdef CONFIG_TCN75A_TRIGGER
#define TCN75A_TRIGGER(n) .alert_gpios = GPIO_DT_SPEC_INST_GET_OR(n, alert_gpios, {}),
#else
#define TCN75A_TRIGGER(n)
#endif
#define TCN75A_INIT(n) \
static struct tcn75a_data tcn75a_data_##n; \
static const struct tcn75a_config tcn75a_config_##n = { \
.i2c_spec = I2C_DT_SPEC_INST_GET(n), \
.resolution = DT_INST_ENUM_IDX(n, resolution), \
.oneshot_mode = DT_INST_PROP(n, oneshot_mode), \
TCN75A_TRIGGER(n) \
}; \
SENSOR_DEVICE_DT_INST_DEFINE(n, &tcn75a_init, NULL, &tcn75a_data_##n, &tcn75a_config_##n, \
POST_KERNEL, CONFIG_SENSOR_INIT_PRIORITY, &tcn75a_api);
DT_INST_FOREACH_STATUS_OKAY(TCN75A_INIT)
``` | /content/code_sandbox/drivers/sensor/microchip/tcn75a/tcn75a.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 1,110 |
```unknown
# Microchip MCP970X ADC driver
#
#
config MCP970X
bool "MCP9700/9700A and MCP9701/9701A sensor"
default y
depends on DT_HAS_MICROCHIP_MCP970X_ENABLED
select ADC
help
Enables Low-Power Linear Active Thermistor IC driver.
``` | /content/code_sandbox/drivers/sensor/microchip/mcp970x/Kconfig | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 71 |
```c
/*
*
*/
#define DT_DRV_COMPAT microchip_mcp970x
#include <zephyr/drivers/adc.h>
#include <zephyr/drivers/sensor.h>
#include <zephyr/logging/log.h>
LOG_MODULE_REGISTER(mcp970x, CONFIG_SENSOR_LOG_LEVEL);
enum ic_family {
FAMILY_MCP9700_9700A,
FAMILY_MCP9701_9701A
};
/* Milli degrees C per degree C */
#define MC_PER_C 1000
#define MV_AT_0C_MCP9700_9700A 500
#define MV_AT_0C_MCP9701_9701A 400
#define T_COEFF_MCP9700_9700A 10
#define T_COEFF_MCP9701_9701A 19.5
struct mcp970x_config {
struct adc_dt_spec adc;
enum ic_family family;
};
struct mcp970x_data {
struct adc_sequence sequence;
int16_t raw;
};
static int fetch(const struct device *dev, enum sensor_channel chan)
{
const struct mcp970x_config *config = dev->config;
struct mcp970x_data *data = dev->data;
int ret;
if ((chan != SENSOR_CHAN_AMBIENT_TEMP) && (chan != SENSOR_CHAN_ALL)) {
return -ENOTSUP;
}
ret = adc_read_dt(&config->adc, &data->sequence);
if (ret != 0) {
LOG_ERR("adc_read: %d", ret);
}
return ret;
}
static int get(const struct device *dev, enum sensor_channel chan, struct sensor_value *val)
{
const struct mcp970x_config *config = dev->config;
struct mcp970x_data *data = dev->data;
int32_t raw_val = data->raw;
int32_t t;
int ret;
__ASSERT_NO_MSG(val != NULL);
if (chan != SENSOR_CHAN_AMBIENT_TEMP) {
return -ENOTSUP;
}
ret = adc_raw_to_millivolts_dt(&config->adc, &raw_val);
if (ret != 0) {
LOG_ERR("to_mv: %d", ret);
return ret;
}
if (config->family == FAMILY_MCP9700_9700A) {
t = (MC_PER_C * (raw_val - MV_AT_0C_MCP9700_9700A)) / T_COEFF_MCP9700_9700A;
} else {
int32_t t_coeff = 10 * T_COEFF_MCP9701_9701A; /* float to int */
t = (MC_PER_C * 10 * (raw_val - MV_AT_0C_MCP9701_9701A)) / t_coeff;
}
val->val1 = t / MC_PER_C;
val->val2 = 1000 * (t % MC_PER_C);
LOG_DBG("%d of %d, %dmV, %dmC", data->raw, (1 << data->sequence.resolution) - 1, raw_val,
t);
return 0;
}
static const struct sensor_driver_api mcp970x_api = {
.sample_fetch = fetch,
.channel_get = get,
};
static int init(const struct device *dev)
{
const struct mcp970x_config *config = dev->config;
struct mcp970x_data *data = dev->data;
int ret;
if (!adc_is_ready_dt(&config->adc)) {
LOG_ERR("ADC is not ready");
return -ENODEV;
}
ret = adc_channel_setup_dt(&config->adc);
if (ret != 0) {
LOG_ERR("setup: %d", ret);
return ret;
}
ret = adc_sequence_init_dt(&config->adc, &data->sequence);
if (ret != 0) {
LOG_ERR("sequence: %d", ret);
return ret;
}
data->sequence.buffer = &data->raw;
data->sequence.buffer_size = sizeof(data->raw);
return 0;
}
#define MCP970X_INIT(inst) \
static struct mcp970x_data mcp970x_##inst##_data = {0}; \
\
static const struct mcp970x_config mcp970x_##inst##_config = { \
.adc = ADC_DT_SPEC_INST_GET(inst), \
.family = DT_INST_ENUM_IDX(inst, family), \
}; \
\
SENSOR_DEVICE_DT_INST_DEFINE(inst, &init, NULL, &mcp970x_##inst##_data, \
&mcp970x_##inst##_config, POST_KERNEL, \
CONFIG_SENSOR_INIT_PRIORITY, &mcp970x_api);
DT_INST_FOREACH_STATUS_OKAY(MCP970X_INIT)
``` | /content/code_sandbox/drivers/sensor/microchip/mcp970x/mcp970x.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 1,004 |
```c
/*
*
*/
#include <errno.h>
#include <zephyr/kernel.h>
#include <zephyr/drivers/i2c.h>
#include <zephyr/sys/byteorder.h>
#include <zephyr/sys/__assert.h>
#include <zephyr/logging/log.h>
#include "mcp9808.h"
LOG_MODULE_DECLARE(MCP9808, CONFIG_SENSOR_LOG_LEVEL);
int mcp9808_attr_set(const struct device *dev, enum sensor_channel chan,
enum sensor_attribute attr,
const struct sensor_value *val)
{
const struct mcp9808_config *cfg = dev->config;
uint8_t reg_addr;
int temp;
__ASSERT_NO_MSG(chan == SENSOR_CHAN_AMBIENT_TEMP);
if (!cfg->int_gpio.port) {
return -ENOTSUP;
}
switch (attr) {
case SENSOR_ATTR_LOWER_THRESH:
reg_addr = MCP9808_REG_LOWER_LIMIT;
break;
case SENSOR_ATTR_UPPER_THRESH:
reg_addr = MCP9808_REG_UPPER_LIMIT;
break;
default:
return -EINVAL;
}
/* Convert temperature to a signed scaled value, then write
* the 12-bit 2s complement-plus-sign-bit register value.
*/
temp = val->val1 * MCP9808_TEMP_SCALE_CEL;
temp += (MCP9808_TEMP_SCALE_CEL * val->val2) / 1000000;
return mcp9808_reg_write_16bit(dev, reg_addr,
mcp9808_temp_reg_from_signed(temp));
}
static inline void setup_int(const struct device *dev,
bool enable)
{
const struct mcp9808_config *cfg = dev->config;
unsigned int flags = enable
? GPIO_INT_EDGE_TO_ACTIVE
: GPIO_INT_DISABLE;
gpio_pin_interrupt_configure_dt(&cfg->int_gpio, flags);
}
static void handle_int(const struct device *dev)
{
struct mcp9808_data *data = dev->data;
setup_int(dev, false);
#if defined(CONFIG_MCP9808_TRIGGER_OWN_THREAD)
k_sem_give(&data->sem);
#elif defined(CONFIG_MCP9808_TRIGGER_GLOBAL_THREAD)
k_work_submit(&data->work);
#endif
}
static void process_int(const struct device *dev)
{
struct mcp9808_data *data = dev->data;
if (data->trigger_handler) {
data->trigger_handler(dev, data->trig);
}
if (data->trigger_handler) {
setup_int(dev, true);
}
}
int mcp9808_trigger_set(const struct device *dev,
const struct sensor_trigger *trig,
sensor_trigger_handler_t handler)
{
struct mcp9808_data *data = dev->data;
const struct mcp9808_config *cfg = dev->config;
int rv = 0;
if (!cfg->int_gpio.port) {
return -ENOTSUP;
}
setup_int(dev, false);
data->trig = trig;
data->trigger_handler = handler;
if (handler != NULL) {
setup_int(dev, true);
rv = gpio_pin_get_dt(&cfg->int_gpio);
if (rv > 0) {
handle_int(dev);
rv = 0;
}
}
return rv;
}
static void alert_cb(const struct device *dev, struct gpio_callback *cb,
uint32_t pins)
{
struct mcp9808_data *data =
CONTAINER_OF(cb, struct mcp9808_data, alert_cb);
ARG_UNUSED(pins);
handle_int(data->dev);
}
#ifdef CONFIG_MCP9808_TRIGGER_OWN_THREAD
static void mcp9808_thread_main(void *p1, void *p2, void *p3)
{
ARG_UNUSED(p2);
ARG_UNUSED(p3);
struct mcp9808_data *data = p1;
while (true) {
k_sem_take(&data->sem, K_FOREVER);
process_int(data->dev);
}
}
static K_KERNEL_STACK_DEFINE(mcp9808_thread_stack, CONFIG_MCP9808_THREAD_STACK_SIZE);
static struct k_thread mcp9808_thread;
#else /* CONFIG_MCP9808_TRIGGER_GLOBAL_THREAD */
static void mcp9808_gpio_thread_cb(struct k_work *work)
{
struct mcp9808_data *data =
CONTAINER_OF(work, struct mcp9808_data, work);
process_int(data->dev);
}
#endif /* CONFIG_MCP9808_TRIGGER_GLOBAL_THREAD */
int mcp9808_setup_interrupt(const struct device *dev)
{
struct mcp9808_data *data = dev->data;
const struct mcp9808_config *cfg = dev->config;
int rc = mcp9808_reg_write_16bit(dev, MCP9808_REG_CRITICAL,
MCP9808_TEMP_ABS_MASK);
if (rc == 0) {
rc = mcp9808_reg_write_16bit(dev, MCP9808_REG_CONFIG,
MCP9808_CFG_ALERT_ENA);
}
data->dev = dev;
#ifdef CONFIG_MCP9808_TRIGGER_OWN_THREAD
k_sem_init(&data->sem, 0, K_SEM_MAX_LIMIT);
k_thread_create(&mcp9808_thread, mcp9808_thread_stack,
CONFIG_MCP9808_THREAD_STACK_SIZE,
mcp9808_thread_main, data, NULL, NULL,
K_PRIO_COOP(CONFIG_MCP9808_THREAD_PRIORITY),
0, K_NO_WAIT);
#else /* CONFIG_MCP9808_TRIGGER_GLOBAL_THREAD */
data->work.handler = mcp9808_gpio_thread_cb;
#endif /* trigger type */
if (!gpio_is_ready_dt(&cfg->int_gpio)) {
LOG_ERR("GPIO device not ready");
return -ENODEV;
}
if (rc == 0) {
rc = gpio_pin_configure_dt(&cfg->int_gpio, GPIO_INPUT);
}
if (rc == 0) {
gpio_init_callback(&data->alert_cb, alert_cb, BIT(cfg->int_gpio.pin));
rc = gpio_add_callback(cfg->int_gpio.port, &data->alert_cb);
}
return rc;
}
``` | /content/code_sandbox/drivers/sensor/microchip/mcp9808/mcp9808_trigger.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 1,271 |
```c
/*
*
*/
#define DT_DRV_COMPAT microchip_mcp9808
#include <errno.h>
#include <zephyr/kernel.h>
#include <zephyr/drivers/i2c.h>
#include <zephyr/init.h>
#include <zephyr/sys/byteorder.h>
#include <zephyr/sys/__assert.h>
#include <zephyr/logging/log.h>
#include "mcp9808.h"
LOG_MODULE_REGISTER(MCP9808, CONFIG_SENSOR_LOG_LEVEL);
int mcp9808_reg_read(const struct device *dev, uint8_t reg, uint16_t *val)
{
const struct mcp9808_config *cfg = dev->config;
int rc = i2c_write_read_dt(&cfg->i2c, ®, sizeof(reg), val,
sizeof(*val));
if (rc == 0) {
*val = sys_be16_to_cpu(*val);
}
return rc;
}
int mcp9808_reg_write_16bit(const struct device *dev, uint8_t reg,
uint16_t val)
{
const struct mcp9808_config *cfg = dev->config;
uint8_t buf[3];
buf[0] = reg;
sys_put_be16(val, &buf[1]);
return i2c_write_dt(&cfg->i2c, buf, sizeof(buf));
}
int mcp9808_reg_write_8bit(const struct device *dev, uint8_t reg,
uint8_t val)
{
const struct mcp9808_config *cfg = dev->config;
uint8_t buf[2] = {
reg,
val,
};
return i2c_write_dt(&cfg->i2c, buf, sizeof(buf));
}
static int mcp9808_set_temperature_resolution(const struct device *dev,
uint8_t resolution)
{
return mcp9808_reg_write_8bit(dev, MCP9808_REG_RESOLUTION, resolution);
}
static int mcp9808_sample_fetch(const struct device *dev,
enum sensor_channel chan)
{
struct mcp9808_data *data = dev->data;
__ASSERT_NO_MSG(chan == SENSOR_CHAN_ALL || chan == SENSOR_CHAN_AMBIENT_TEMP);
return mcp9808_reg_read(dev, MCP9808_REG_TEMP_AMB, &data->reg_val);
}
static int mcp9808_channel_get(const struct device *dev,
enum sensor_channel chan,
struct sensor_value *val)
{
const struct mcp9808_data *data = dev->data;
int temp = mcp9808_temp_signed_from_reg(data->reg_val);
__ASSERT_NO_MSG(chan == SENSOR_CHAN_AMBIENT_TEMP);
if (chan != SENSOR_CHAN_AMBIENT_TEMP) {
return -ENOTSUP;
}
val->val1 = temp / MCP9808_TEMP_SCALE_CEL;
temp -= val->val1 * MCP9808_TEMP_SCALE_CEL;
val->val2 = (temp * 1000000) / MCP9808_TEMP_SCALE_CEL;
return 0;
}
static const struct sensor_driver_api mcp9808_api_funcs = {
.sample_fetch = mcp9808_sample_fetch,
.channel_get = mcp9808_channel_get,
#ifdef CONFIG_MCP9808_TRIGGER
.attr_set = mcp9808_attr_set,
.trigger_set = mcp9808_trigger_set,
#endif /* CONFIG_MCP9808_TRIGGER */
};
int mcp9808_init(const struct device *dev)
{
const struct mcp9808_config *cfg = dev->config;
int rc = 0;
if (!device_is_ready(cfg->i2c.bus)) {
LOG_ERR("Bus device is not ready");
return -ENODEV;
}
rc = mcp9808_set_temperature_resolution(dev, cfg->resolution);
if (rc) {
LOG_ERR("Could not set the resolution of mcp9808 module");
return rc;
}
#ifdef CONFIG_MCP9808_TRIGGER
if (cfg->int_gpio.port) {
rc = mcp9808_setup_interrupt(dev);
}
#endif /* CONFIG_MCP9808_TRIGGER */
return rc;
}
#define MCP9808_DEFINE(inst) \
static struct mcp9808_data mcp9808_data_##inst; \
\
static const struct mcp9808_config mcp9808_config_##inst = { \
.i2c = I2C_DT_SPEC_INST_GET(inst), \
.resolution = DT_INST_PROP(inst, resolution), \
IF_ENABLED(CONFIG_MCP9808_TRIGGER, \
(.int_gpio = GPIO_DT_SPEC_INST_GET_OR(inst, int_gpios, { 0 }),)) \
}; \
\
SENSOR_DEVICE_DT_INST_DEFINE(inst, mcp9808_init, NULL, \
&mcp9808_data_##inst, &mcp9808_config_##inst, POST_KERNEL, \
CONFIG_SENSOR_INIT_PRIORITY, &mcp9808_api_funcs); \
DT_INST_FOREACH_STATUS_OKAY(MCP9808_DEFINE)
``` | /content/code_sandbox/drivers/sensor/microchip/mcp9808/mcp9808.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 1,055 |
```unknown
# MCP9808 temperature sensor configuration options
menuconfig MCP9808
bool "MCP9808 temperature sensor"
default y
depends on DT_HAS_MICROCHIP_MCP9808_ENABLED
select I2C
help
Enable driver for MCP9808 temperature sensor.
if MCP9808
choice
prompt "MCP9808 trigger mode"
default MCP9808_TRIGGER_NONE
config MCP9808_TRIGGER_NONE
bool "No trigger"
config MCP9808_TRIGGER_GLOBAL_THREAD
depends on GPIO
select MCP9808_TRIGGER
bool "Use global thread"
config MCP9808_TRIGGER_OWN_THREAD
depends on GPIO
select MCP9808_TRIGGER
bool "Use own thread"
endchoice
config MCP9808_TRIGGER
bool
config MCP9808_THREAD_STACK_SIZE
int "Sensor delayed work thread stack size"
depends on MCP9808_TRIGGER_OWN_THREAD
default 1024
config MCP9808_THREAD_PRIORITY
int "MCP9808 thread priority"
depends on MCP9808_TRIGGER_OWN_THREAD
default 10
endif # MCP9808
``` | /content/code_sandbox/drivers/sensor/microchip/mcp9808/Kconfig | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 227 |
```objective-c
/*
*
*/
#ifndef ZEPHYR_DRIVERS_SENSOR_MCP9808_MCP9808_H_
#define ZEPHYR_DRIVERS_SENSOR_MCP9808_MCP9808_H_
#include <errno.h>
#include <zephyr/types.h>
#include <zephyr/device.h>
#include <zephyr/drivers/sensor.h>
#include <zephyr/sys/util.h>
#include <zephyr/drivers/i2c.h>
#include <zephyr/drivers/gpio.h>
#define MCP9808_REG_CONFIG 0x01
#define MCP9808_REG_UPPER_LIMIT 0x02
#define MCP9808_REG_LOWER_LIMIT 0x03
#define MCP9808_REG_CRITICAL 0x04
#define MCP9808_REG_TEMP_AMB 0x05
/* 16 bits control configuration and state.
*
* * Bit 0 controls alert signal output mode
* * Bit 1 controls interrupt polarity
* * Bit 2 disables upper and lower threshold checking
* * Bit 3 enables alert signal output
* * Bit 4 records alert status
* * Bit 5 records interrupt status
* * Bit 6 locks the upper/lower window registers
* * Bit 7 locks the critical register
* * Bit 8 enters shutdown mode
* * Bits 9-10 control threshold hysteresis
*/
#define MCP9808_CFG_ALERT_MODE_INT BIT(0)
#define MCP9808_CFG_ALERT_ENA BIT(3)
#define MCP9808_CFG_ALERT_STATE BIT(4)
#define MCP9808_CFG_INT_CLEAR BIT(5)
/* 16 bits are used for temperature and state encoding:
* * Bits 0..11 encode the temperature in a 2s complement signed value
* in Celsius with 1/16 Cel resolution
* * Bit 12 is set to indicate a negative temperature
* * Bit 13 is set to indicate a temperature below the lower threshold
* * Bit 14 is set to indicate a temperature above the upper threshold
* * Bit 15 is set to indicate a temperature above the critical threshold
*/
#define MCP9808_TEMP_SCALE_CEL 16 /* signed */
#define MCP9808_TEMP_SIGN_BIT BIT(12)
#define MCP9808_TEMP_ABS_MASK ((uint16_t)(MCP9808_TEMP_SIGN_BIT - 1U))
#define MCP9808_TEMP_LWR_BIT BIT(13)
#define MCP9808_TEMP_UPR_BIT BIT(14)
#define MCP9808_TEMP_CRT_BIT BIT(15)
#define MCP9808_REG_RESOLUTION 0x08
struct mcp9808_data {
uint16_t reg_val;
#ifdef CONFIG_MCP9808_TRIGGER
struct gpio_callback alert_cb;
const struct device *dev;
const struct sensor_trigger *trig;
sensor_trigger_handler_t trigger_handler;
#endif
#ifdef CONFIG_MCP9808_TRIGGER_OWN_THREAD
struct k_sem sem;
#endif
#ifdef CONFIG_MCP9808_TRIGGER_GLOBAL_THREAD
struct k_work work;
#endif
};
struct mcp9808_config {
struct i2c_dt_spec i2c;
uint8_t resolution;
#ifdef CONFIG_MCP9808_TRIGGER
struct gpio_dt_spec int_gpio;
#endif /* CONFIG_MCP9808_TRIGGER */
};
int mcp9808_reg_read(const struct device *dev, uint8_t reg, uint16_t *val);
int mcp9808_reg_write_16bit(const struct device *dev, uint8_t reg,
uint16_t val);
int mcp9808_reg_write_8bit(const struct device *dev, uint8_t reg,
uint8_t val);
#ifdef CONFIG_MCP9808_TRIGGER
int mcp9808_attr_set(const struct device *dev, enum sensor_channel chan,
enum sensor_attribute attr,
const struct sensor_value *val);
int mcp9808_trigger_set(const struct device *dev,
const struct sensor_trigger *trig,
sensor_trigger_handler_t handler);
int mcp9808_setup_interrupt(const struct device *dev);
#endif /* CONFIG_MCP9808_TRIGGER */
/* Encode a signed temperature in scaled Celsius to the format used in
* register values.
*/
static inline uint16_t mcp9808_temp_reg_from_signed(int temp)
{
/* Get the 12-bit 2s complement value */
uint16_t rv = temp & MCP9808_TEMP_ABS_MASK;
if (temp < 0) {
rv |= MCP9808_TEMP_SIGN_BIT;
}
return rv;
}
/* Decode a register temperature value to a signed temperature in
* scaled Celsius.
*/
static inline int mcp9808_temp_signed_from_reg(uint16_t reg)
{
int rv = reg & MCP9808_TEMP_ABS_MASK;
if (reg & MCP9808_TEMP_SIGN_BIT) {
/* Convert 12-bit 2s complement to signed negative
* value.
*/
rv = -(1U + (rv ^ MCP9808_TEMP_ABS_MASK));
}
return rv;
}
#endif /* ZEPHYR_DRIVERS_SENSOR_MCP9808_MCP9808_H_ */
``` | /content/code_sandbox/drivers/sensor/microchip/mcp9808/mcp9808.h | objective-c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 1,051 |
```unknown
#
config NXP_LP_FLEXCOMM
bool "Driver for the NXP Low Power FlexComm Interface"
default y
depends on DT_HAS_NXP_LP_FLEXCOMM_ENABLED
help
Enabled the Low Power FlexComm shim driver.
LP FLexcomm allows enablement of LPUART and LPI2C
at the same time with reduced interface. This driver
checks concurrent enablement and returns and error for
unsupported concurrent enablement.
``` | /content/code_sandbox/drivers/mfd/Kconfig.lpflexcomm | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 98 |
```unknown
config MFD_TLE9104
bool "Infineon TLE9104 SPI powertrain switch"
default y
depends on DT_HAS_INFINEON_TLE9104_ENABLED
# using select SPI at this point introduces a cyclic dependency
depends on SPI
help
Enable driver for TLE9104 SPI-based powertrain switch.
``` | /content/code_sandbox/drivers/mfd/Kconfig.tle9104 | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 75 |
```c
/*
*
*/
#define DT_DRV_COMPAT nxp_lp_flexcomm
#include <errno.h>
#include <zephyr/device.h>
#include <zephyr/irq.h>
#include <zephyr/kernel.h>
#include <zephyr/logging/log.h>
#include <zephyr/drivers/mfd/nxp_lp_flexcomm.h>
LOG_MODULE_REGISTER(mfd_nxp_lp_flexcomm, CONFIG_MFD_LOG_LEVEL);
struct nxp_lp_flexcomm_child {
const struct device *dev;
uint8_t periph;
child_isr_t lp_flexcomm_child_isr;
};
struct nxp_lp_flexcomm_data {
struct nxp_lp_flexcomm_child *children;
size_t num_children;
};
struct nxp_lp_flexcomm_config {
LP_FLEXCOMM_Type *base;
void (*irq_config_func)(const struct device *dev);
};
void nxp_lp_flexcomm_isr(const struct device *dev)
{
uint32_t interrupt_status;
const struct nxp_lp_flexcomm_config *config = dev->config;
struct nxp_lp_flexcomm_data *data = dev->data;
uint32_t instance = LP_FLEXCOMM_GetInstance(config->base);
struct nxp_lp_flexcomm_child *child;
interrupt_status = LP_FLEXCOMM_GetInterruptStatus(instance);
if ((interrupt_status &
((uint32_t)kLPFLEXCOMM_I2cSlaveInterruptFlag |
(uint32_t)kLPFLEXCOMM_I2cMasterInterruptFlag)) != 0U) {
child = &data->children[LP_FLEXCOMM_PERIPH_LPI2C];
if (child->lp_flexcomm_child_isr != NULL) {
child->lp_flexcomm_child_isr(child->dev);
}
}
if ((interrupt_status &
((uint32_t)kLPFLEXCOMM_UartRxInterruptFlag |
(uint32_t)kLPFLEXCOMM_UartTxInterruptFlag)) != 0U) {
child = &data->children[LP_FLEXCOMM_PERIPH_LPUART];
if (child->lp_flexcomm_child_isr != NULL) {
child->lp_flexcomm_child_isr(child->dev);
}
}
if (((interrupt_status &
(uint32_t)kLPFLEXCOMM_SpiInterruptFlag)) != 0U) {
child = &data->children[LP_FLEXCOMM_PERIPH_LPSPI];
if (child->lp_flexcomm_child_isr != NULL) {
child->lp_flexcomm_child_isr(child->dev);
}
}
}
void nxp_lp_flexcomm_setirqhandler(const struct device *dev, const struct device *child_dev,
LP_FLEXCOMM_PERIPH_T periph, child_isr_t handler)
{
struct nxp_lp_flexcomm_data *data = dev->data;
struct nxp_lp_flexcomm_child *child;
child = &data->children[periph];
/* Store the interrupt handler and the child device node */
child->lp_flexcomm_child_isr = handler;
child->dev = child_dev;
}
static int nxp_lp_flexcomm_init(const struct device *dev)
{
const struct nxp_lp_flexcomm_config *config = dev->config;
struct nxp_lp_flexcomm_data *data = dev->data;
uint32_t instance;
struct nxp_lp_flexcomm_child *child = NULL;
bool spi_found = false;
bool uart_found = false;
bool i2c_found = false;
for (int i = 1; i < data->num_children; i++) {
child = &data->children[i];
if (child->periph == LP_FLEXCOMM_PERIPH_LPSPI) {
spi_found = true;
}
if (child->periph == LP_FLEXCOMM_PERIPH_LPI2C) {
i2c_found = true;
}
if (child->periph == LP_FLEXCOMM_PERIPH_LPUART) {
uart_found = true;
}
}
/* If SPI is enabled with another interface type return an error */
if (spi_found && (i2c_found || uart_found)) {
return -EINVAL;
}
instance = LP_FLEXCOMM_GetInstance(config->base);
if (uart_found && i2c_found) {
LP_FLEXCOMM_Init(instance, LP_FLEXCOMM_PERIPH_LPI2CAndLPUART);
} else if (uart_found) {
LP_FLEXCOMM_Init(instance, LP_FLEXCOMM_PERIPH_LPUART);
} else if (i2c_found) {
LP_FLEXCOMM_Init(instance, LP_FLEXCOMM_PERIPH_LPI2C);
} else if (spi_found) {
LP_FLEXCOMM_Init(instance, LP_FLEXCOMM_PERIPH_LPSPI);
}
config->irq_config_func(dev);
return 0;
}
#define MCUX_FLEXCOMM_CHILD_INIT(child_node_id) \
[DT_NODE_CHILD_IDX(child_node_id) + 1] = { \
.periph = DT_NODE_CHILD_IDX(child_node_id) + 1, \
},
#define NXP_LP_FLEXCOMM_INIT(n) \
\
static struct nxp_lp_flexcomm_child \
nxp_lp_flexcomm_children_##n[LP_FLEXCOMM_PERIPH_LPI2C + 1] = { \
DT_INST_FOREACH_CHILD_STATUS_OKAY(n, MCUX_FLEXCOMM_CHILD_INIT) \
}; \
\
static void nxp_lp_flexcomm_config_func_##n(const struct device *dev); \
\
static const struct nxp_lp_flexcomm_config nxp_lp_flexcomm_config_##n = { \
.base = (LP_FLEXCOMM_Type *)DT_INST_REG_ADDR(n), \
.irq_config_func = nxp_lp_flexcomm_config_func_##n, \
}; \
\
static struct nxp_lp_flexcomm_data nxp_lp_flexcomm_data_##n = { \
.children = nxp_lp_flexcomm_children_##n, \
.num_children = ARRAY_SIZE(nxp_lp_flexcomm_children_##n), \
}; \
\
DEVICE_DT_INST_DEFINE(n, \
&nxp_lp_flexcomm_init, \
NULL, \
&nxp_lp_flexcomm_data_##n, \
&nxp_lp_flexcomm_config_##n, \
PRE_KERNEL_1, \
CONFIG_KERNEL_INIT_PRIORITY_DEFAULT, \
NULL); \
\
static void nxp_lp_flexcomm_config_func_##n(const struct device *dev) \
{ \
IRQ_CONNECT(DT_INST_IRQN(n), DT_INST_IRQ(n, priority), \
nxp_lp_flexcomm_isr, DEVICE_DT_INST_GET(n), 0); \
irq_enable(DT_INST_IRQN(n)); \
}
DT_INST_FOREACH_STATUS_OKAY(NXP_LP_FLEXCOMM_INIT)
``` | /content/code_sandbox/drivers/mfd/mfd_nxp_lp_flexcomm.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 1,517 |
```unknown
config MFD_NPM6001
bool "nPM6001 PMIC multi-function device driver"
default y
depends on DT_HAS_NORDIC_NPM6001_ENABLED
select I2C
help
Enable the Nordic nPM6001 PMIC multi-function device driver
config MFD_NPM6001_INIT_PRIORITY
int "nPM6001 MFD initialization priority"
default MFD_INIT_PRIORITY
depends on MFD_NPM6001
help
Multi-function device initialization priority for nPM6001.
``` | /content/code_sandbox/drivers/mfd/Kconfig.npm6001 | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 113 |
```c
/*
*/
#define DT_DRV_COMPAT adi_adp5585
#include <zephyr/drivers/gpio.h>
#include <zephyr/drivers/gpio/gpio_utils.h>
#include <zephyr/drivers/i2c.h>
#include <zephyr/logging/log.h>
#include <zephyr/kernel.h>
#include <zephyr/sys/byteorder.h>
#include <zephyr/drivers/mfd/adp5585.h>
LOG_MODULE_REGISTER(adp5585, CONFIG_GPIO_LOG_LEVEL);
static int mfd_adp5585_software_reset(const struct device *dev)
{
const struct mfd_adp5585_config *config = dev->config;
int ret = 0;
/** Set CONFIG to gpio by default */
uint8_t pin_config_buf[] = { ADP5585_PIN_CONFIG_A, 0x00U, 0x00U };
ret = i2c_write_dt(&config->i2c_bus, pin_config_buf, sizeof(pin_config_buf));
if (ret) {
goto out;
}
out:
if (ret) {
LOG_ERR("%s: software reset failed: %d", dev->name, ret);
}
return ret;
}
static void mfd_adp5585_int_gpio_handler(const struct device *dev, struct gpio_callback *gpio_cb,
uint32_t pins)
{
ARG_UNUSED(dev);
ARG_UNUSED(pins);
struct mfd_adp5585_data *data = CONTAINER_OF(gpio_cb, struct mfd_adp5585_data, int_gpio_cb);
k_work_submit(&data->work);
}
static void mfd_adp5585_work_handler(struct k_work *work)
{
struct mfd_adp5585_data *data = CONTAINER_OF(work, struct mfd_adp5585_data, work);
const struct mfd_adp5585_config *config = data->dev->config;
uint8_t reg_int_status;
int ret = 0;
k_sem_take(&data->lock, K_FOREVER);
/* Read Interrput Flag */
if (ret == 0) {
ret = i2c_reg_read_byte_dt(&config->i2c_bus, ADP5585_INT_STATUS, ®_int_status);
}
/* Clear Interrput Flag */
if (ret == 0) {
ret = i2c_reg_write_byte_dt(&config->i2c_bus, ADP5585_INT_STATUS, reg_int_status);
}
k_sem_give(&data->lock);
#ifdef CONFIG_GPIO_ADP5585
if ((reg_int_status & ADP5585_INT_GPI) && device_is_ready(data->child.gpio_dev)) {
(void)gpio_adp5585_irq_handler(data->child.gpio_dev);
}
#endif /* CONFIG_GPIO_ADP5585 */
}
static int mfd_adp5585_init(const struct device *dev)
{
const struct mfd_adp5585_config *config = dev->config;
struct mfd_adp5585_data *data = dev->data;
int ret;
if (!i2c_is_ready_dt(&config->i2c_bus)) {
return -ENODEV;
}
/* reset gpio can be left float */
if (gpio_is_ready_dt(&config->reset_gpio)) {
ret = gpio_pin_configure_dt(&config->reset_gpio, GPIO_OUTPUT_INACTIVE);
if (ret) {
LOG_ERR("%s: configure reset pin failed: %d", dev->name, ret);
return ret;
}
} else {
LOG_WRN("%s: reset pin not configured", dev->name);
}
ret = mfd_adp5585_software_reset(dev);
if (ret) {
return ret;
}
if (gpio_is_ready_dt(&config->nint_gpio)) {
ret = gpio_pin_configure_dt(&config->nint_gpio, GPIO_INPUT);
if (ret < 0) {
return ret;
}
ret = gpio_pin_interrupt_configure_dt(&config->nint_gpio, GPIO_INT_EDGE_TO_ACTIVE);
if (ret != 0) {
LOG_ERR("%s: failed to configure INT interrupt: %d", dev->name, ret);
return ret;
}
gpio_init_callback(&data->int_gpio_cb, mfd_adp5585_int_gpio_handler,
BIT(config->nint_gpio.pin));
ret = gpio_add_callback_dt(&config->nint_gpio, &data->int_gpio_cb);
if (ret != 0) {
LOG_ERR("%s: failed to add INT callback: %d", dev->name, ret);
return ret;
}
} else {
LOG_WRN("%s: nint pin not configured", dev->name);
}
LOG_DBG("%s: init ok\r\n", dev->name);
return 0;
}
#define MFD_ADP5585_DEFINE(inst) \
static const struct mfd_adp5585_config mfd_adp5585_config_##inst = { \
.reset_gpio = GPIO_DT_SPEC_INST_GET_OR(inst, reset_gpios, {0}), \
.nint_gpio = GPIO_DT_SPEC_INST_GET_OR(n, nint_gpios, {0}), \
.i2c_bus = I2C_DT_SPEC_INST_GET(inst), \
}; \
static struct mfd_adp5585_data mfd_adp5585_data_##inst = { \
.work = Z_WORK_INITIALIZER(mfd_adp5585_work_handler), \
.lock = Z_SEM_INITIALIZER(mfd_adp5585_data_##inst.lock, 1, 1), \
.dev = DEVICE_DT_INST_GET(inst), \
}; \
\
DEVICE_DT_INST_DEFINE(inst, mfd_adp5585_init, NULL, &mfd_adp5585_data_##inst, \
&mfd_adp5585_config_##inst, POST_KERNEL, \
CONFIG_MFD_ADP5585_INIT_PRIORITY, NULL);
DT_INST_FOREACH_STATUS_OKAY(MFD_ADP5585_DEFINE);
``` | /content/code_sandbox/drivers/mfd/mfd_adp5585.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 1,274 |
```c
/*
*/
#define DT_DRV_COMPAT nordic_npm6001
#include <errno.h>
#include <zephyr/drivers/i2c.h>
#include <zephyr/sys/util.h>
/* nPM6001 registers */
#define NPM6001_SWREADY 0x01U
#define NPM6001_BUCK3SELDAC 0x44U
#define NPM6001_BUCKMODEPADCONF 0x4EU
#define NPM6001_PADDRIVESTRENGTH 0x53U
/* nPM6001 BUCKMODEPADCONF fields */
#define NPM6001_BUCKMODEPADCONF_BUCKMODE0PADTYPE_CMOS BIT(0)
#define NPM6001_BUCKMODEPADCONF_BUCKMODE1PADTYPE_CMOS BIT(1)
#define NPM6001_BUCKMODEPADCONF_BUCKMODE2PADTYPE_CMOS BIT(2)
#define NPM6001_BUCKMODEPADCONF_BUCKMODE0PULLD_ENABLED BIT(4)
#define NPM6001_BUCKMODEPADCONF_BUCKMODE1PULLD_ENABLED BIT(5)
#define NPM6001_BUCKMODEPADCONF_BUCKMODE2PULLD_ENABLED BIT(6)
/* nPM6001 PADDRIVESTRENGTH fields */
#define NPM6001_PADDRIVESTRENGTH_READY_HIGH BIT(2)
#define NPM6001_PADDRIVESTRENGTH_NINT_HIGH BIT(3)
#define NPM6001_PADDRIVESTRENGTH_SDA_HIGH BIT(5)
struct mfd_npm6001_config {
struct i2c_dt_spec i2c;
uint8_t buck_pad_val;
uint8_t pad_val;
};
static int mfd_npm6001_init(const struct device *dev)
{
const struct mfd_npm6001_config *config = dev->config;
int ret;
if (!i2c_is_ready_dt(&config->i2c)) {
return -ENODEV;
}
/* always select BUCK3 DAC (does not increase power consumption) */
ret = i2c_reg_write_byte_dt(&config->i2c, NPM6001_BUCK3SELDAC, 1U);
if (ret < 0) {
return ret;
}
/* configure pad properties */
ret = i2c_reg_write_byte_dt(&config->i2c, NPM6001_BUCKMODEPADCONF, config->buck_pad_val);
if (ret < 0) {
return ret;
}
ret = i2c_reg_write_byte_dt(&config->i2c, NPM6001_PADDRIVESTRENGTH, config->pad_val);
if (ret < 0) {
return ret;
}
/* Enable switching to hysteresis mode */
ret = i2c_reg_write_byte_dt(&config->i2c, NPM6001_SWREADY, 1U);
if (ret < 0) {
return ret;
}
return 0;
}
#define MFD_NPM6001_DEFINE(inst) \
static const struct mfd_npm6001_config config##inst = { \
.i2c = I2C_DT_SPEC_INST_GET(inst), \
.buck_pad_val = ((DT_INST_ENUM_IDX(inst, nordic_buck_mode0_input_type) * \
NPM6001_BUCKMODEPADCONF_BUCKMODE0PADTYPE_CMOS) | \
(DT_INST_ENUM_IDX(inst, nordic_buck_mode1_input_type) * \
NPM6001_BUCKMODEPADCONF_BUCKMODE1PADTYPE_CMOS) | \
(DT_INST_ENUM_IDX(inst, nordic_buck_mode2_input_type) * \
NPM6001_BUCKMODEPADCONF_BUCKMODE2PADTYPE_CMOS) | \
(DT_INST_PROP(inst, nordic_buck_mode0_pull_down) * \
NPM6001_BUCKMODEPADCONF_BUCKMODE0PULLD_ENABLED) | \
(DT_INST_PROP(inst, nordic_buck_mode1_pull_down) * \
NPM6001_BUCKMODEPADCONF_BUCKMODE1PULLD_ENABLED) | \
(DT_INST_PROP(inst, nordic_buck_mode2_pull_down) * \
NPM6001_BUCKMODEPADCONF_BUCKMODE2PULLD_ENABLED)), \
.pad_val = ((DT_INST_PROP(inst, nordic_ready_high_drive) * \
NPM6001_PADDRIVESTRENGTH_READY_HIGH) | \
(DT_INST_PROP(inst, nordic_nint_high_drive) * \
NPM6001_PADDRIVESTRENGTH_NINT_HIGH) | \
(DT_INST_PROP(inst, nordic_sda_high_drive) * \
NPM6001_PADDRIVESTRENGTH_SDA_HIGH)), \
}; \
\
DEVICE_DT_INST_DEFINE(inst, mfd_npm6001_init, NULL, NULL, &config##inst, POST_KERNEL, \
CONFIG_MFD_NPM6001_INIT_PRIORITY, NULL);
DT_INST_FOREACH_STATUS_OKAY(MFD_NPM6001_DEFINE)
``` | /content/code_sandbox/drivers/mfd/mfd_npm6001.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 1,106 |
```unknown
config MFD_BD8LB600FS
bool "BD8LB600FS low side switch multi-function device driver"
default y
depends on DT_HAS_ROHM_BD8LB600FS_ENABLED
# using select SPI at this point introduces a cyclic dependency
depends on SPI
help
Enable the Rohm BD8LB600FS low side switch multi-function device driver
``` | /content/code_sandbox/drivers/mfd/Kconfig.bd8lb600fs | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 83 |
```unknown
config MFD_MAX20335
bool "MAX20335 PMIC multi-function device driver"
default y
depends on DT_HAS_MAXIM_MAX20335_ENABLED
select I2C
help
Enable the Maxim MAX20335 PMIC multi-function device driver
``` | /content/code_sandbox/drivers/mfd/Kconfig.max20335 | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 57 |
```c
/*
*
*/
#define DT_DRV_COMPAT maxim_max31790
#include <zephyr/device.h>
#include <zephyr/drivers/i2c.h>
#include <zephyr/drivers/mfd/max31790.h>
#include <zephyr/sys/util.h>
#include <zephyr/kernel.h>
#include <zephyr/logging/log.h>
LOG_MODULE_REGISTER(max_max31790, CONFIG_MFD_LOG_LEVEL);
struct max31790_config {
struct i2c_dt_spec i2c;
};
static void max31790_set_globalconfiguration_i2cwatchdog(uint8_t *destination, uint8_t value)
{
uint8_t length = MAX37190_GLOBALCONFIGURATION_I2CWATCHDOG_LENGTH;
uint8_t pos = MAX37190_GLOBALCONFIGURATION_I2CWATCHDOG_POS;
*destination &= ~GENMASK(pos + length - 1, pos);
*destination |= FIELD_PREP(GENMASK(pos + length - 1, pos), value);
}
static int max31790_init(const struct device *dev)
{
const struct max31790_config *config = dev->config;
int result;
uint8_t reg_value;
if (!i2c_is_ready_dt(&config->i2c)) {
LOG_ERR("I2C device not ready");
return -ENODEV;
}
reg_value = 0;
reg_value &= ~MAX37190_GLOBALCONFIGURATION_STANDBY_BIT;
reg_value |= MAX37190_GLOBALCONFIGURATION_RESET_BIT;
reg_value |= MAX37190_GLOBALCONFIGURATION_BUSTIMEOUT_BIT;
reg_value &= ~MAX37190_GLOBALCONFIGURATION_OSCILLATORSELECTION_BIT;
max31790_set_globalconfiguration_i2cwatchdog(®_value, 0);
reg_value &= ~MAX37190_GLOBALCONFIGURATION_I2CWATCHDOGSTATUS_BIT;
result = i2c_reg_write_byte_dt(&config->i2c, MAX37190_REGISTER_GLOBALCONFIGURATION,
reg_value);
if (result != 0) {
return result;
}
k_sleep(K_USEC(MAX31790_RESET_TIMEOUT_IN_US));
result = i2c_reg_read_byte_dt(&config->i2c, MAX37190_REGISTER_GLOBALCONFIGURATION,
®_value);
if (result != 0) {
return result;
}
if ((reg_value & MAX37190_GLOBALCONFIGURATION_STANDBY_BIT) != 0) {
LOG_ERR("PWM controller is still in standby");
return -ENODEV;
}
return 0;
}
#define MAX31790_INIT(inst) \
static const struct max31790_config max31790_##inst##_config = { \
.i2c = I2C_DT_SPEC_INST_GET(inst), \
}; \
\
DEVICE_DT_INST_DEFINE(inst, max31790_init, NULL, NULL, &max31790_##inst##_config, \
POST_KERNEL, CONFIG_MFD_INIT_PRIORITY, NULL);
DT_INST_FOREACH_STATUS_OKAY(MAX31790_INIT);
``` | /content/code_sandbox/drivers/mfd/mfd_max31790.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 620 |
```unknown
menuconfig MFD_ADP5585
bool "Analog ADP5585 I2C configurable GPIO/PWM/KeyScan chip"
default y
depends on DT_HAS_ADI_ADP5585_ENABLED
depends on I2C
help
Enable driver for Analog ADP5585.
config MFD_ADP5585_INIT_PRIORITY
int "Init priority"
default 65
depends on MFD_ADP5585
help
Device driver initialization priority.
``` | /content/code_sandbox/drivers/mfd/Kconfig.adp5585 | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 103 |
```unknown
menuconfig MFD_AD559X
bool "Analog AD559x I2C/SPI configurable ADC/DAC/GPIO chip"
default y
depends on DT_HAS_ADI_AD559X_ENABLED
help
Enable driver for Analog AD5592 or Analog AD5593.
if MFD_AD559X
config MFD_AD559X_BUS_I2C
bool "Analog AD559x I2C bus support"
default y
depends on $(dt_compat_on_bus,$(DT_COMPAT_ADI_AD559X),i2c)
depends on I2C
config MFD_AD559X_BUS_SPI
bool "Analog AD559x SPI bus support"
default y
depends on $(dt_compat_on_bus,$(DT_COMPAT_ADI_AD559X),spi)
depends on SPI
endif # MFD_AD559X
``` | /content/code_sandbox/drivers/mfd/Kconfig.ad559x | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 180 |
```c
/*
*
*/
#define DT_DRV_COMPAT infineon_tle9104
#include <errno.h>
#include <zephyr/kernel.h>
#include <zephyr/device.h>
#include <zephyr/init.h>
#include <zephyr/drivers/gpio.h>
#include <zephyr/drivers/mfd/tle9104.h>
#include <zephyr/drivers/spi.h>
#include <zephyr/logging/log.h>
#include <zephyr/sys/byteorder.h>
/*
* The values for the defines below as well as the register definitions were
* taken from the datasheet, which can be found at:
* path_to_url
*/
#define TLE9104_RESET_DURATION_TIME_US 10
#define TLE9104_RESET_DURATION_WAIT_TIME_SAFETY_MARGIN_US 200
#define TLE9104_RESET_DURATION_WAIT_TIME_US 10
#define TLE9104_INITIALIZATION_TIMEOUT_MS 1
#define TLE9104_ICVERSIONID 0xB1
#define TLE9104_FRAME_RW_POS 15
#define TLE9104_FRAME_PARITY_POS 14
#define TLE9104_FRAME_FAULTCOMMUNICATION_POS 13
#define TLE9104_FRAME_FAULTGLOBAL_POS 12
#define TLE9104_FRAME_ADDRESS_POS 8
#define TLE9104_FRAME_DATA_POS 0
#define TLE9104_CFG_CWDTIME_LENGTH 2
#define TLE9104_CFG_CWDTIME_POS 6
#define TLE9104_OFFDIAGCFG_DIAGFILTCFG_LENGTH 2
#define TLE9104_OFFDIAGCFG_DIAGFILTCFG_POS 4
#define TLE9104_OFFDIAGCFG_OUT4DIAGEN_BIT BIT(3)
#define TLE9104_OFFDIAGCFG_OUT3DIAGEN_BIT BIT(2)
#define TLE9104_OFFDIAGCFG_OUT2DIAGEN_BIT BIT(1)
#define TLE9104_OFFDIAGCFG_OUT1DIAGEN_BIT BIT(0)
#define TLE9104_ONDIAGCFG_OCFILTCFG_LENGTH 3
#define TLE9104_ONDIAGCFG_OCFILTCFG_POS 2
#define TLE9104_ONDIAGCFG_OCTH_LENGTH 2
#define TLE9104_ONDIAGCFG_OCTH_POS 0
#define TLE9104_DIAGOUT12ON_OUT2STAT_BIT BIT(7)
#define TLE9104_DIAGOUT12ON_OUT1STAT_BIT BIT(6)
#define TLE9104_DIAGOUT12ON_DIAGCH2ON_LENGTH 3
#define TLE9104_DIAGOUT12ON_DIAGCH2ON_POS 3
#define TLE9104_DIAGOUT12ON_DIAGCH1ON_LENGTH 3
#define TLE9104_DIAGOUT12ON_DIAGCH1ON_POS 0
#define TLE9104_DIAGOUT34ON_OUT4STAT_BIT BIT(7)
#define TLE9104_DIAGOUT34ON_OUT3STAT_BIT BIT(6)
#define TLE9104_DIAGOUT34ON_DIAGCH4ON_LENGTH 3
#define TLE9104_DIAGOUT34ON_DIAGCH4ON_POS 3
#define TLE9104_DIAGOUT34ON_DIAGCH3ON_LENGTH 3
#define TLE9104_DIAGOUT34ON_DIAGCH3ON_POS 0
#define TLE9104_DIAGOFF_DIAGCH4OFF_LENGTH 2
#define TLE9104_DIAGOFF_DIAGCH4OFF_POS 6
#define TLE9104_DIAGOFF_DIAGCH3OFF_LENGTH 2
#define TLE9104_DIAGOFF_DIAGCH3OFF_POS 4
#define TLE9104_DIAGOFF_DIAGCH2OFF_LENGTH 2
#define TLE9104_DIAGOFF_DIAGCH2OFF_POS 2
#define TLE9104_DIAGOFF_DIAGCH1OFF_LENGTH 2
#define TLE9104_DIAGOFF_DIAGCH1OFF_POS 0
#define TLE9104_CTRL_OUT1ONS_BIT BIT(1)
#define TLE9104_CTRL_OUT1ONC_BIT BIT(0)
#define TLE9104_CFG_OUT1DD_BIT BIT(0)
#define TLE9104_GLOBALSTATUS_OUTEN_BIT BIT(7)
#define TLE9104_GLOBALSTATUS_POR_LATCH_BIT BIT(0)
#define TLE9104_SPIFRAME_FAULTCOMMUNICATION_BIT BIT(13)
enum tle9104_register {
TLE9104REGISTER_CTRL = 0x00,
TLE9104REGISTER_CFG = 0x01,
TLE9104REGISTER_OFFDIAGCFG = 0x02,
TLE9104REGISTER_ONDIAGCFG = 0x03,
TLE9104REGISTER_DIAGOUT12ON = 0x04,
TLE9104REGISTER_DIAGOUT34ON = 0x05,
TLE9104REGISTER_DIAGOFF = 0x06,
TLE9104REGISTER_GLOBALSTATUS = 0x07,
TLE9104REGISTER_ICVID = 0x08,
};
LOG_MODULE_REGISTER(infineon_tle9104, CONFIG_MFD_LOG_LEVEL);
struct tle9104_config {
struct spi_dt_spec bus;
const struct gpio_dt_spec gpio_reset;
const struct gpio_dt_spec gpio_enable;
const struct gpio_dt_spec gpio_control[TLE9104_GPIO_COUNT];
uint16_t diagnostic_filter_time;
uint16_t overcurrent_shutdown_delay_time;
uint16_t overcurrent_shutdown_threshold;
};
struct tle9104_data {
/* communication watchdog is getting ignored */
bool cwd_ignore;
/* each bit is one output channel, bit 0 = OUT1, ... */
uint8_t previous_state;
struct k_mutex lock;
};
static void tle9104_set_register_bits(uint8_t *destination, uint8_t pos, uint8_t length,
uint8_t value)
{
*destination &= ~GENMASK(pos + length - 1, pos);
*destination |= FIELD_PREP(GENMASK(pos + length - 1, pos), value);
}
static uint8_t tle9104_get_register_bits(uint8_t value, uint8_t pos, uint8_t length)
{
return FIELD_GET(GENMASK(pos + length - 1, pos), value);
}
static int tle9104_calculate_parity(uint16_t value)
{
int parity = 1 + POPCOUNT(value);
if ((value & BIT(TLE9104_FRAME_PARITY_POS)) != 0) {
parity--;
}
return parity % 2;
}
static void tle9104_apply_parity(uint16_t *value)
{
int parity = tle9104_calculate_parity(*value);
WRITE_BIT(*value, TLE9104_FRAME_PARITY_POS, parity);
}
static bool tle9104_check_parity(uint16_t value)
{
int parity = tle9104_calculate_parity(value);
return ((value & BIT(TLE9104_FRAME_PARITY_POS)) >> TLE9104_FRAME_PARITY_POS) == parity;
}
static int tle9104_transceive_frame(const struct device *dev, bool write,
enum tle9104_register write_reg, uint8_t write_data,
enum tle9104_register *read_reg, uint8_t *read_data)
{
const struct tle9104_config *config = dev->config;
struct tle9104_data *data = dev->data;
uint16_t write_frame;
uint16_t read_frame;
int result;
uint8_t buffer_tx[2];
uint8_t buffer_rx[ARRAY_SIZE(buffer_tx)];
const struct spi_buf tx_buf[] = {{
.buf = buffer_tx,
.len = ARRAY_SIZE(buffer_tx),
}};
const struct spi_buf rx_buf[] = {{
.buf = buffer_rx,
.len = ARRAY_SIZE(buffer_rx),
}};
const struct spi_buf_set tx = {
.buffers = tx_buf,
.count = ARRAY_SIZE(tx_buf),
};
const struct spi_buf_set rx = {
.buffers = rx_buf,
.count = ARRAY_SIZE(rx_buf),
};
write_frame = write_data << TLE9104_FRAME_DATA_POS;
write_frame |= write_reg << TLE9104_FRAME_ADDRESS_POS;
WRITE_BIT(write_frame, TLE9104_FRAME_RW_POS, write);
tle9104_apply_parity(&write_frame);
sys_put_be16(write_frame, buffer_tx);
LOG_DBG("writing in register 0x%02X of TLE9104 value 0x%02X, complete frame 0x%04X",
write_reg, write_data, write_frame);
result = spi_transceive_dt(&config->bus, &tx, &rx);
if (result != 0) {
LOG_ERR("spi_write failed with error %i", result);
return result;
}
read_frame = sys_get_be16(buffer_rx);
LOG_DBG("received complete frame 0x%04X", read_frame);
if (!tle9104_check_parity(read_frame)) {
LOG_ERR("parity check for received frame of TLE9104 failed");
return -EIO;
}
if (!data->cwd_ignore) {
if ((TLE9104_SPIFRAME_FAULTCOMMUNICATION_BIT & read_frame) != 0) {
LOG_WRN("%s: communication fault reported by TLE9104", dev->name);
}
}
*read_reg = FIELD_GET(GENMASK(TLE9104_FRAME_FAULTGLOBAL_POS - 1, TLE9104_FRAME_ADDRESS_POS),
read_frame);
*read_data = FIELD_GET(GENMASK(TLE9104_FRAME_ADDRESS_POS - 1, TLE9104_FRAME_DATA_POS),
read_frame);
return 0;
}
static int tle9104_write_register(const struct device *dev, enum tle9104_register reg,
uint8_t value)
{
enum tle9104_register read_reg;
uint8_t read_data;
return tle9104_transceive_frame(dev, true, reg, value, &read_reg, &read_data);
}
static int tle9104_write_state_internal(const struct device *dev, uint8_t state)
{
const struct tle9104_config *config = dev->config;
struct tle9104_data *data = dev->data;
bool spi_update_required = false;
uint8_t register_ctrl = 0x00;
int result;
LOG_DBG("writing state 0x%02X to TLE9104", state);
for (size_t i = 0; i < TLE9104_GPIO_COUNT; ++i) {
uint8_t mask = GENMASK(i, i);
bool current_value = (state & mask) != 0;
bool previous_value = (data->previous_state & mask) != 0;
/*
* Setting the OUTx_ON bits results in a high impedance output,
* clearing them pulls the output to ground. Therefore the
* meaning here is intentionally inverted, as this will then turn
* out for a low active open drain output to be pulled to ground
* if set to off.
*/
if (current_value == 0) {
register_ctrl |= TLE9104_CTRL_OUT1ONS_BIT << (2 * i);
} else {
register_ctrl |= TLE9104_CTRL_OUT1ONC_BIT << (2 * i);
}
if (current_value == previous_value) {
continue;
}
if (config->gpio_control[i].port == NULL) {
spi_update_required = true;
continue;
}
result = gpio_pin_set_dt(&config->gpio_control[i], current_value);
if (result != 0) {
LOG_ERR("unable to set control GPIO");
return result;
}
}
if (spi_update_required) {
result = tle9104_write_register(dev, TLE9104REGISTER_CTRL, register_ctrl);
if (result != 0) {
LOG_ERR("unable to set control register");
return result;
}
}
data->previous_state = state;
return 0;
}
int tle9104_write_state(const struct device *dev, uint8_t state)
{
struct tle9104_data *data = dev->data;
int result;
k_mutex_lock(&data->lock, K_FOREVER);
result = tle9104_write_state_internal(dev, state);
k_mutex_unlock(&data->lock);
return result;
}
static int
tle9104_get_diagnostics_internal(const struct device *dev,
struct gpio_tle9104_channel_diagnostics diag[TLE9104_GPIO_COUNT])
{
enum tle9104_register read_reg;
uint8_t diag_out12_on;
uint8_t diag_out34_on;
uint8_t diag_off;
int result = tle9104_transceive_frame(dev, false, TLE9104REGISTER_DIAGOUT12ON, 0x00,
&read_reg, &diag_out12_on);
if (result != 0) {
return result;
}
result = tle9104_transceive_frame(dev, false, TLE9104REGISTER_DIAGOUT34ON, 0x00, &read_reg,
&diag_out12_on);
if (result != 0) {
return result;
}
if (read_reg != TLE9104REGISTER_DIAGOUT12ON) {
LOG_ERR("expected to read different register");
return -EFAULT;
}
result = tle9104_transceive_frame(dev, false, TLE9104REGISTER_DIAGOFF, 0x00, &read_reg,
&diag_out34_on);
if (result != 0) {
return result;
}
if (read_reg != TLE9104REGISTER_DIAGOUT34ON) {
LOG_ERR("expected to read different register");
return -EFAULT;
}
result = tle9104_transceive_frame(dev, false, TLE9104REGISTER_DIAGOFF, 0x00, &read_reg,
&diag_off);
if (result != 0) {
return result;
}
if (read_reg != TLE9104REGISTER_DIAGOFF) {
LOG_ERR("expected to read different register");
return -EFAULT;
}
diag[0].on = tle9104_get_register_bits(diag_out12_on, TLE9104_DIAGOUT12ON_DIAGCH1ON_POS,
TLE9104_DIAGOUT12ON_DIAGCH1ON_LENGTH);
diag[1].on = tle9104_get_register_bits(diag_out12_on, TLE9104_DIAGOUT12ON_DIAGCH2ON_POS,
TLE9104_DIAGOUT12ON_DIAGCH2ON_LENGTH);
diag[2].on = tle9104_get_register_bits(diag_out34_on, TLE9104_DIAGOUT34ON_DIAGCH3ON_POS,
TLE9104_DIAGOUT34ON_DIAGCH3ON_LENGTH);
diag[3].on = tle9104_get_register_bits(diag_out34_on, TLE9104_DIAGOUT34ON_DIAGCH4ON_POS,
TLE9104_DIAGOUT34ON_DIAGCH4ON_LENGTH);
diag[0].off = tle9104_get_register_bits(diag_off, TLE9104_DIAGOFF_DIAGCH1OFF_POS,
TLE9104_DIAGOFF_DIAGCH1OFF_LENGTH);
diag[1].off = tle9104_get_register_bits(diag_off, TLE9104_DIAGOFF_DIAGCH2OFF_POS,
TLE9104_DIAGOFF_DIAGCH2OFF_LENGTH);
diag[2].off = tle9104_get_register_bits(diag_off, TLE9104_DIAGOFF_DIAGCH3OFF_POS,
TLE9104_DIAGOFF_DIAGCH3OFF_LENGTH);
diag[3].off = tle9104_get_register_bits(diag_off, TLE9104_DIAGOFF_DIAGCH4OFF_POS,
TLE9104_DIAGOFF_DIAGCH4OFF_LENGTH);
return 0;
}
int tle9104_get_diagnostics(const struct device *dev,
struct gpio_tle9104_channel_diagnostics diag[TLE9104_GPIO_COUNT])
{
struct tle9104_data *data = dev->data;
int result;
k_mutex_lock(&data->lock, K_FOREVER);
result = tle9104_get_diagnostics_internal(dev, diag);
k_mutex_unlock(&data->lock);
return result;
}
static int tle9104_clear_diagnostics_internal(const struct device *dev)
{
enum tle9104_register read_reg;
uint8_t temp;
int result;
result = tle9104_transceive_frame(dev, true, TLE9104REGISTER_DIAGOUT12ON, 0x00, &read_reg,
&temp);
if (result != 0) {
return result;
}
result = tle9104_transceive_frame(dev, true, TLE9104REGISTER_DIAGOUT34ON, 0x00, &read_reg,
&temp);
if (result != 0) {
return result;
}
result = tle9104_transceive_frame(dev, true, TLE9104REGISTER_DIAGOFF, 0x00, &read_reg,
&temp);
if (result != 0) {
return result;
}
return 0;
}
int tle9104_clear_diagnostics(const struct device *dev)
{
struct tle9104_data *data = dev->data;
int result;
k_mutex_lock(&data->lock, K_FOREVER);
result = tle9104_clear_diagnostics_internal(dev);
k_mutex_unlock(&data->lock);
return result;
}
static int tle9104_init(const struct device *dev)
{
const struct tle9104_config *config = dev->config;
struct tle9104_data *data = dev->data;
uint8_t register_cfg;
uint8_t register_globalstatus;
uint8_t register_icvid;
enum tle9104_register read_reg;
int result;
LOG_DBG("initialize TLE9104 instance %s", dev->name);
data->cwd_ignore = true;
result = k_mutex_init(&data->lock);
if (result != 0) {
LOG_ERR("unable to initialize mutex");
return result;
}
if (!spi_is_ready_dt(&config->bus)) {
LOG_ERR("SPI bus %s is not ready", config->bus.bus->name);
return -ENODEV;
}
register_cfg = 0x00;
for (int i = 0; i < TLE9104_GPIO_COUNT; ++i) {
const struct gpio_dt_spec *current = config->gpio_control + i;
if (current->port == NULL) {
LOG_DBG("got no control port for output %i, will control it via SPI", i);
continue;
}
register_cfg |= TLE9104_CFG_OUT1DD_BIT << i;
if (!gpio_is_ready_dt(current)) {
LOG_ERR("%s: control GPIO is not ready", dev->name);
return -ENODEV;
}
result = gpio_pin_configure_dt(current, GPIO_OUTPUT_INACTIVE);
if (result != 0) {
LOG_ERR("failed to initialize control GPIO %i", i);
return result;
}
}
if (config->gpio_enable.port != NULL) {
if (!gpio_is_ready_dt(&config->gpio_enable)) {
LOG_ERR("%s: enable GPIO is not ready", dev->name);
return -ENODEV;
}
result = gpio_pin_configure_dt(&config->gpio_enable, GPIO_OUTPUT_ACTIVE);
if (result != 0) {
LOG_ERR("failed to enable TLE9104");
return result;
}
}
if (config->gpio_reset.port != NULL) {
if (!gpio_is_ready_dt(&config->gpio_reset)) {
LOG_ERR("%s: reset GPIO is not yet ready", dev->name);
return -ENODEV;
}
result = gpio_pin_configure_dt(&config->gpio_reset, GPIO_OUTPUT_ACTIVE);
if (result != 0) {
LOG_ERR("failed to initialize GPIO for reset");
return result;
}
k_busy_wait(TLE9104_RESET_DURATION_TIME_US);
gpio_pin_set_dt(&config->gpio_reset, 0);
k_busy_wait(TLE9104_RESET_DURATION_WAIT_TIME_US +
TLE9104_RESET_DURATION_WAIT_TIME_SAFETY_MARGIN_US);
}
/*
* The first read value should be the ICVID, this acts also as the setup of the
* global status register address.
*/
result = tle9104_transceive_frame(dev, false, TLE9104REGISTER_GLOBALSTATUS, 0x00, &read_reg,
®ister_icvid);
if (result != 0) {
return result;
}
if (read_reg != TLE9104REGISTER_ICVID) {
LOG_ERR("expected to read register ICVID, got instead 0x%02X", read_reg);
return -EIO;
}
if (register_icvid != TLE9104_ICVERSIONID) {
LOG_ERR("got unexpected IC version id 0x%02X", register_icvid);
return -EIO;
}
result = tle9104_transceive_frame(dev, false, TLE9104REGISTER_GLOBALSTATUS, 0x00, &read_reg,
®ister_globalstatus);
if (result != 0) {
return result;
}
if (read_reg != TLE9104REGISTER_GLOBALSTATUS) {
LOG_ERR("expected to read register GLOBALSTATUS, got instead 0x%02X", read_reg);
return -EIO;
}
if ((register_globalstatus & TLE9104_GLOBALSTATUS_POR_LATCH_BIT) == 0) {
LOG_ERR("no power on reset detected");
return -EIO;
}
/* disable communication watchdog */
tle9104_set_register_bits(®ister_cfg, TLE9104_CFG_CWDTIME_POS,
TLE9104_CFG_CWDTIME_LENGTH, 0);
result = tle9104_write_register(dev, TLE9104REGISTER_CFG, register_cfg);
if (result != 0) {
LOG_ERR("unable to write configuration");
return result;
}
register_cfg = 0x00;
tle9104_set_register_bits(®ister_cfg, TLE9104_OFFDIAGCFG_DIAGFILTCFG_POS,
TLE9104_OFFDIAGCFG_DIAGFILTCFG_LENGTH,
config->diagnostic_filter_time);
register_cfg |= TLE9104_OFFDIAGCFG_OUT4DIAGEN_BIT;
register_cfg |= TLE9104_OFFDIAGCFG_OUT3DIAGEN_BIT;
register_cfg |= TLE9104_OFFDIAGCFG_OUT2DIAGEN_BIT;
register_cfg |= TLE9104_OFFDIAGCFG_OUT1DIAGEN_BIT;
result = tle9104_write_register(dev, TLE9104REGISTER_OFFDIAGCFG, register_cfg);
if (result != 0) {
LOG_ERR("unable to write OFF-diag configuration");
return result;
}
register_cfg = 0x00;
tle9104_set_register_bits(®ister_cfg, TLE9104_ONDIAGCFG_OCFILTCFG_POS,
TLE9104_ONDIAGCFG_OCFILTCFG_LENGTH,
config->overcurrent_shutdown_delay_time);
tle9104_set_register_bits(®ister_cfg, TLE9104_ONDIAGCFG_OCTH_POS,
TLE9104_ONDIAGCFG_OCTH_LENGTH,
config->overcurrent_shutdown_threshold);
result = tle9104_write_register(dev, TLE9104REGISTER_ONDIAGCFG, register_cfg);
if (result != 0) {
LOG_ERR("unable to write ON-diag configuration");
return result;
}
register_globalstatus = 0x00;
/* enable outputs */
register_globalstatus |= TLE9104_GLOBALSTATUS_OUTEN_BIT;
result = tle9104_write_register(dev, TLE9104REGISTER_GLOBALSTATUS, register_globalstatus);
if (result != 0) {
LOG_ERR("unable to write global status");
return result;
}
data->cwd_ignore = false;
return 0;
}
#define TLE9104_INIT_GPIO_FIELDS(inst, gpio) \
COND_CODE_1(DT_INST_NODE_HAS_PROP(inst, gpio), \
(GPIO_DT_SPEC_GET_BY_IDX(DT_DRV_INST(inst), gpio, 0)), ({0}))
#define TLE9104_INIT(inst) \
static const struct tle9104_config tle9104_##inst##_config = { \
.bus = SPI_DT_SPEC_INST_GET( \
inst, SPI_OP_MODE_MASTER | SPI_MODE_CPHA | SPI_WORD_SET(8), 0), \
.gpio_enable = TLE9104_INIT_GPIO_FIELDS(inst, en_gpios), \
.gpio_reset = TLE9104_INIT_GPIO_FIELDS(inst, resn_gpios), \
.gpio_control = { \
TLE9104_INIT_GPIO_FIELDS(inst, in1_gpios), \
TLE9104_INIT_GPIO_FIELDS(inst, in2_gpios), \
TLE9104_INIT_GPIO_FIELDS(inst, in3_gpios), \
TLE9104_INIT_GPIO_FIELDS(inst, in4_gpios), \
}, \
.diagnostic_filter_time = DT_INST_ENUM_IDX(inst, diagnostic_filter_time), \
.overcurrent_shutdown_delay_time = \
DT_INST_ENUM_IDX(inst, overcurrent_shutdown_delay_time), \
.overcurrent_shutdown_threshold = \
DT_INST_ENUM_IDX(inst, overcurrent_shutdown_threshold), \
}; \
\
static struct tle9104_data tle9104_##inst##_data; \
\
DEVICE_DT_INST_DEFINE(inst, tle9104_init, NULL, &tle9104_##inst##_data, \
&tle9104_##inst##_config, POST_KERNEL, CONFIG_MFD_INIT_PRIORITY, \
NULL);
DT_INST_FOREACH_STATUS_OKAY(TLE9104_INIT);
``` | /content/code_sandbox/drivers/mfd/mfd_tle9104.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 5,506 |
```c
/*
*/
#include <zephyr/device.h>
#include <zephyr/drivers/mfd/ad559x.h>
#include <zephyr/drivers/i2c.h>
#include <zephyr/sys/byteorder.h>
#include <zephyr/sys/util_macro.h>
#include "mfd_ad559x.h"
static int mfd_ad559x_i2c_read_raw(const struct device *dev, uint8_t *val, size_t len)
{
const struct mfd_ad559x_config *config = dev->config;
return i2c_read_dt(&config->i2c, val, len);
}
static int mfd_ad559x_i2c_write_raw(const struct device *dev, uint8_t *val, size_t len)
{
const struct mfd_ad559x_config *config = dev->config;
return i2c_write_dt(&config->i2c, val, len);
}
static int mfd_ad559x_i2c_read_reg(const struct device *dev, uint8_t reg, uint8_t reg_data,
uint16_t *val)
{
const struct mfd_ad559x_config *config = dev->config;
uint8_t buf[sizeof(*val)];
int ret;
ARG_UNUSED(reg_data);
__ASSERT((reg & 0xf0) == 0, "reg bits [7:4] should be 0: 0x%x", reg);
ret = i2c_write_read_dt(&config->i2c, ®, sizeof(reg), buf, sizeof(buf));
if (ret < 0) {
return ret;
}
*val = sys_get_be16(buf);
return 0;
}
static int mfd_ad559x_i2c_write_reg(const struct device *dev, uint8_t reg, uint16_t val)
{
uint8_t buf[sizeof(reg) + sizeof(val)];
buf[0] = reg;
sys_put_be16(val, &buf[1]);
return mfd_ad559x_i2c_write_raw(dev, buf, sizeof(buf));
}
static const struct mfd_ad559x_transfer_function mfd_ad559x_i2c_transfer_function = {
.read_raw = mfd_ad559x_i2c_read_raw,
.write_raw = mfd_ad559x_i2c_write_raw,
.read_reg = mfd_ad559x_i2c_read_reg,
.write_reg = mfd_ad559x_i2c_write_reg,
};
int mfd_ad559x_i2c_init(const struct device *dev)
{
const struct mfd_ad559x_config *config = dev->config;
struct mfd_ad559x_data *data = dev->data;
data->transfer_function = &mfd_ad559x_i2c_transfer_function;
if (!i2c_is_ready_dt(&config->i2c)) {
return -ENODEV;
}
return 0;
}
``` | /content/code_sandbox/drivers/mfd/mfd_ad559x_i2c.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 600 |
```c
/*
*/
#define DT_DRV_COMPAT maxim_max20335
#include <errno.h>
#include <zephyr/drivers/i2c.h>
#include <zephyr/sys/util.h>
#define MAX20335_REG_CHIP_ID 0x00
#define MAX20335_CHIP_ID_VAL 0x04
struct mfd_max20335_config {
struct i2c_dt_spec bus;
};
static int mfd_max20335_init(const struct device *dev)
{
const struct mfd_max20335_config *config = dev->config;
uint8_t val;
int ret;
if (!i2c_is_ready_dt(&config->bus)) {
return -ENODEV;
}
ret = i2c_reg_read_byte_dt(&config->bus, MAX20335_REG_CHIP_ID, &val);
if (ret < 0) {
return ret;
}
if (val != MAX20335_CHIP_ID_VAL) {
return -ENODEV;
}
return 0;
}
#define MFD_MA20335_DEFINE(inst) \
static const struct mfd_max20335_config mfd_max20335_config##inst = { \
.bus = I2C_DT_SPEC_INST_GET(inst), \
}; \
\
DEVICE_DT_INST_DEFINE(inst, mfd_max20335_init, NULL, NULL, \
&mfd_max20335_config##inst, POST_KERNEL, \
CONFIG_MFD_INIT_PRIORITY, NULL);
DT_INST_FOREACH_STATUS_OKAY(MFD_MA20335_DEFINE)
``` | /content/code_sandbox/drivers/mfd/mfd_max20335.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 315 |
```c
/*
*
*/
#define DT_DRV_COMPAT rohm_bd8lb600fs
#include <zephyr/kernel.h>
#include <zephyr/device.h>
#include <zephyr/init.h>
#include <zephyr/drivers/gpio.h>
#include <zephyr/drivers/gpio/gpio_utils.h>
#include <zephyr/drivers/mfd/bd8lb600fs.h>
#include <zephyr/drivers/spi.h>
#include <zephyr/logging/log.h>
#include <zephyr/sys/byteorder.h>
LOG_MODULE_REGISTER(rohm_bd8lb600fs, CONFIG_MFD_LOG_LEVEL);
#define OUTPUT_OFF_WITH_OPEN_LOAD_DETECTION 0b11
#define OUTPUT_ON 0b10
#define WAIT_TIME_RESET_ACTIVE_IN_US 1000
#define WAIT_TIME_RESET_INACTIVE_TO_CS_IN_US 10
struct bd8lb600fs_config {
struct spi_dt_spec bus;
const struct gpio_dt_spec gpio_reset;
size_t instance_count;
};
struct bd8lb600fs_data {
/* each bit is one output channel, bit 0 = channel 1, ... */
uint32_t state;
/* each bit defines if an open load was detected, see state */
uint32_t old;
/* each bit defines if an over current or over temperature was detected, see state */
uint32_t ocp_or_tsd;
struct k_mutex lock;
};
static void bd8lb600fs_fill_tx_buffer(const struct device *dev, uint8_t *buffer, size_t buffer_size)
{
const struct bd8lb600fs_config *config = dev->config;
struct bd8lb600fs_data *data = dev->data;
uint16_t state_converted = 0;
LOG_DBG("%s: writing state 0x%08X to BD8LB600FS", dev->name, data->state);
memset(buffer, 0x00, buffer_size);
for (size_t j = 0; j < config->instance_count; ++j) {
int instance_position = (config->instance_count - j - 1) * 2;
state_converted = 0;
for (size_t i = 0; i < 8; ++i) {
if ((data->state & BIT(i + j * 8)) == 0) {
state_converted |= OUTPUT_OFF_WITH_OPEN_LOAD_DETECTION << (i * 2);
} else {
state_converted |= OUTPUT_ON << (i * 2);
}
}
LOG_DBG("%s: configuration for instance %zu: %04X (position %i)", dev->name, j,
state_converted, instance_position);
sys_put_be16(state_converted, buffer + instance_position);
}
}
static void bd8lb600fs_parse_rx_buffer(const struct device *dev, uint8_t *buffer)
{
const struct bd8lb600fs_config *config = dev->config;
struct bd8lb600fs_data *data = dev->data;
data->old = 0;
data->ocp_or_tsd = 0;
for (size_t j = 0; j < config->instance_count; ++j) {
int instance_position = (config->instance_count - j - 1) * 2;
uint16_t current = sys_get_be16(buffer + instance_position);
for (size_t i = 0; i < 8; ++i) {
if ((BIT(2 * i + 1) & current) != 0) {
WRITE_BIT(data->old, i + j * 8, 1);
}
if ((BIT(2 * i) & current) != 0) {
WRITE_BIT(data->ocp_or_tsd, i + j * 8, 1);
}
}
}
LOG_DBG("%s: received 0x%08X open load state from BD8LB600FS", dev->name, data->old);
LOG_DBG("%s: received 0x%08X OCP or TSD state from BD8LB600FS", dev->name,
data->ocp_or_tsd);
}
static int bd8lb600fs_transceive_state(const struct device *dev)
{
const struct bd8lb600fs_config *config = dev->config;
uint8_t buffer_tx[8];
const struct spi_buf tx_buf = {
.buf = buffer_tx,
.len = config->instance_count * sizeof(uint16_t),
};
const struct spi_buf_set tx = {
.buffers = &tx_buf,
.count = 1,
};
uint8_t buffer_rx[8];
const struct spi_buf rx_buf = {
.buf = buffer_rx,
.len = config->instance_count * sizeof(uint16_t),
};
const struct spi_buf_set rx = {
.buffers = &rx_buf,
.count = 1,
};
bd8lb600fs_fill_tx_buffer(dev, buffer_tx, ARRAY_SIZE(buffer_tx));
int result = spi_transceive_dt(&config->bus, &tx, &rx);
if (result != 0) {
LOG_ERR("spi_transceive failed with error %i", result);
return result;
}
bd8lb600fs_parse_rx_buffer(dev, buffer_rx);
return 0;
}
static int bd8lb600fs_write_state(const struct device *dev)
{
const struct bd8lb600fs_config *config = dev->config;
uint8_t buffer_tx[8];
const struct spi_buf tx_buf = {
.buf = buffer_tx,
.len = config->instance_count * sizeof(uint16_t),
};
const struct spi_buf_set tx = {
.buffers = &tx_buf,
.count = 1,
};
bd8lb600fs_fill_tx_buffer(dev, buffer_tx, ARRAY_SIZE(buffer_tx));
int result = spi_write_dt(&config->bus, &tx);
if (result != 0) {
LOG_ERR("spi_transceive failed with error %i", result);
return result;
}
return 0;
}
int mfd_bd8lb600fs_set_outputs(const struct device *dev, uint32_t values)
{
struct bd8lb600fs_data *data = dev->data;
int result;
k_mutex_lock(&data->lock, K_FOREVER);
data->state = values;
result = bd8lb600fs_write_state(dev);
k_mutex_unlock(&data->lock);
return result;
}
int mfd_bd8lb600fs_get_output_diagnostics(const struct device *dev, uint32_t *old,
uint32_t *ocp_or_tsd)
{
struct bd8lb600fs_data *data = dev->data;
int result;
k_mutex_lock(&data->lock, K_FOREVER);
result = bd8lb600fs_transceive_state(dev);
*old = data->old;
*ocp_or_tsd = data->ocp_or_tsd;
k_mutex_unlock(&data->lock);
return result;
}
static int bd8lb600fs_init(const struct device *dev)
{
const struct bd8lb600fs_config *config = dev->config;
struct bd8lb600fs_data *data = dev->data;
if (!spi_is_ready_dt(&config->bus)) {
LOG_ERR("SPI bus %s not ready", config->bus.bus->name);
return -ENODEV;
}
if (!gpio_is_ready_dt(&config->gpio_reset)) {
LOG_ERR("%s: reset GPIO is not ready", dev->name);
return -ENODEV;
}
int result = k_mutex_init(&data->lock);
if (result != 0) {
LOG_ERR("unable to initialize mutex");
return result;
}
result = gpio_pin_configure_dt(&config->gpio_reset, GPIO_OUTPUT_ACTIVE);
if (result != 0) {
LOG_ERR("failed to initialize GPIO for reset");
return result;
}
k_busy_wait(WAIT_TIME_RESET_ACTIVE_IN_US);
gpio_pin_set_dt(&config->gpio_reset, 0);
k_busy_wait(WAIT_TIME_RESET_INACTIVE_TO_CS_IN_US);
return 0;
}
#define BD8LB600FS_INIT(inst) \
static const struct bd8lb600fs_config bd8lb600fs_##inst##_config = { \
.bus = SPI_DT_SPEC_INST_GET( \
inst, SPI_OP_MODE_MASTER | SPI_MODE_CPHA | SPI_WORD_SET(8), 0), \
.gpio_reset = GPIO_DT_SPEC_GET_BY_IDX(DT_DRV_INST(inst), reset_gpios, 0), \
.instance_count = DT_INST_PROP(inst, instance_count), \
}; \
\
static struct bd8lb600fs_data bd8lb600fs_##inst##_data = { \
.state = 0x00, \
}; \
\
/* This has to be initialized after the SPI peripheral. */ \
DEVICE_DT_INST_DEFINE(inst, bd8lb600fs_init, NULL, &bd8lb600fs_##inst##_data, \
&bd8lb600fs_##inst##_config, POST_KERNEL, CONFIG_MFD_INIT_PRIORITY, \
NULL);
DT_INST_FOREACH_STATUS_OKAY(BD8LB600FS_INIT)
``` | /content/code_sandbox/drivers/mfd/mfd_bd8lb600fs.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 1,956 |
```objective-c
/*
*/
#ifndef ZEPHYR_DRIVERS_MFD_AD559X_H_
#define ZEPHYR_DRIVERS_MFD_AD559X_H_
#ifdef __cplusplus
extern "C" {
#endif
#define DT_DRV_COMPAT adi_ad559x
#include <zephyr/device.h>
#include <zephyr/drivers/gpio.h>
#if DT_ANY_INST_ON_BUS_STATUS_OKAY(i2c)
#include <zephyr/drivers/i2c.h>
#endif /* DT_ANY_INST_ON_BUS_STATUS_OKAY(i2c) */
#if DT_ANY_INST_ON_BUS_STATUS_OKAY(spi)
#include <zephyr/drivers/spi.h>
#endif /* DT_ANY_INST_ON_BUS_STATUS_OKAY(spi) */
#define AD559X_GPIO_READBACK_EN BIT(10)
#define AD559X_LDAC_READBACK_EN BIT(6)
#define AD559X_REG_SOFTWARE_RESET 0x0FU
#define AD559X_SOFTWARE_RESET_MAGIC_VAL 0x5AC
#define AD559X_REG_VAL_MASK 0x3FF
#define AD559X_REG_RESET_VAL_MASK 0x7FF
#define AD559X_REG_SHIFT_VAL 11
#define AD559X_REG_READBACK_SHIFT_VAL 2
struct mfd_ad559x_transfer_function {
int (*read_raw)(const struct device *dev, uint8_t *val, size_t len);
int (*write_raw)(const struct device *dev, uint8_t *val, size_t len);
int (*read_reg)(const struct device *dev, uint8_t reg, uint8_t reg_data, uint16_t *val);
int (*write_reg)(const struct device *dev, uint8_t reg, uint16_t val);
};
struct mfd_ad559x_config {
struct gpio_dt_spec reset_gpio;
#if DT_ANY_INST_ON_BUS_STATUS_OKAY(i2c)
struct i2c_dt_spec i2c;
#endif /* DT_ANY_INST_ON_BUS_STATUS_OKAY(i2c) */
#if DT_ANY_INST_ON_BUS_STATUS_OKAY(spi)
struct spi_dt_spec spi;
#endif /* DT_ANY_INST_ON_BUS_STATUS_OKAY(spi) */
int (*bus_init)(const struct device *dev);
bool has_pointer_byte_map;
};
struct mfd_ad559x_data {
const struct mfd_ad559x_transfer_function *transfer_function;
};
int mfd_ad559x_i2c_init(const struct device *dev);
int mfd_ad559x_spi_init(const struct device *dev);
#ifdef __cplusplus
}
#endif
#endif /* ZEPHYR_DRIVERS_MFD_AD559X_H_*/
``` | /content/code_sandbox/drivers/mfd/mfd_ad559x.h | objective-c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 533 |
```c
/*
*/
#include <zephyr/device.h>
#include <zephyr/drivers/mfd/ad559x.h>
#include <zephyr/drivers/spi.h>
#include <zephyr/sys/byteorder.h>
#include "mfd_ad559x.h"
static int mfd_ad559x_spi_read_raw(const struct device *dev, uint8_t *val, size_t len)
{
const struct mfd_ad559x_config *config = dev->config;
uint16_t nop_msg = 0;
struct spi_buf tx_buf[] = {{.buf = &nop_msg, .len = sizeof(nop_msg)}};
const struct spi_buf_set tx = {.buffers = tx_buf, .count = 1};
struct spi_buf rx_buf[] = {{.buf = val, .len = len}};
const struct spi_buf_set rx = {.buffers = rx_buf, .count = 1};
return spi_transceive_dt(&config->spi, &tx, &rx);
}
static int mfd_ad559x_spi_write_raw(const struct device *dev, uint8_t *val, size_t len)
{
const struct mfd_ad559x_config *config = dev->config;
struct spi_buf tx_buf[] = {{.buf = val, .len = len}};
const struct spi_buf_set tx = {.buffers = tx_buf, .count = 1};
return spi_write_dt(&config->spi, &tx);
}
static int mfd_ad559x_spi_read_reg(const struct device *dev, uint8_t reg, uint8_t reg_data,
uint16_t *val)
{
uint16_t data;
uint16_t msg;
int ret;
switch (reg) {
case AD559X_REG_GPIO_INPUT_EN:
msg = sys_cpu_to_be16(AD559X_GPIO_READBACK_EN |
(AD559X_REG_GPIO_INPUT_EN << AD559X_REG_SHIFT_VAL) |
reg_data);
break;
default:
msg = sys_cpu_to_be16(AD559X_LDAC_READBACK_EN |
(AD559X_REG_READ_AND_LDAC << AD559X_REG_SHIFT_VAL) |
reg << AD559X_REG_READBACK_SHIFT_VAL);
break;
}
ret = mfd_ad559x_spi_write_raw(dev, (uint8_t *)&msg, sizeof(msg));
if (ret < 0) {
return ret;
}
ret = mfd_ad559x_spi_read_raw(dev, (uint8_t *)&data, sizeof(data));
if (ret < 0) {
return ret;
}
*val = sys_be16_to_cpu(data);
return 0;
}
static int mfd_ad559x_spi_write_reg(const struct device *dev, uint8_t reg, uint16_t val)
{
uint16_t write_mask;
uint16_t msg;
switch (reg) {
case AD559X_REG_SOFTWARE_RESET:
write_mask = AD559X_REG_RESET_VAL_MASK;
break;
default:
write_mask = AD559X_REG_VAL_MASK;
break;
}
msg = sys_cpu_to_be16((reg << AD559X_REG_SHIFT_VAL) | (val & write_mask));
return mfd_ad559x_spi_write_raw(dev, (uint8_t *)&msg, sizeof(msg));
}
static const struct mfd_ad559x_transfer_function mfd_ad559x_spi_transfer_function = {
.read_raw = mfd_ad559x_spi_read_raw,
.write_raw = mfd_ad559x_spi_write_raw,
.read_reg = mfd_ad559x_spi_read_reg,
.write_reg = mfd_ad559x_spi_write_reg,
};
int mfd_ad559x_spi_init(const struct device *dev)
{
const struct mfd_ad559x_config *config = dev->config;
struct mfd_ad559x_data *data = dev->data;
data->transfer_function = &mfd_ad559x_spi_transfer_function;
if (!spi_is_ready_dt(&config->spi)) {
return -ENODEV;
}
return 0;
}
``` | /content/code_sandbox/drivers/mfd/mfd_ad559x_spi.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 832 |
```unknown
config MFD_AXP192
bool "AXP192 PMIC multi-function device driver"
default y
depends on DT_HAS_X_POWERS_AXP192_ENABLED
select I2C
help
Enable the X-Powers AXP192 PMIC multi-function device driver
``` | /content/code_sandbox/drivers/mfd/Kconfig.axp192 | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 61 |
```unknown
config MFD_NCT38XX
bool "Nuvton NCT38xx multi-function device driver"
default y
depends on DT_HAS_NUVOTON_NCT38XX_ENABLED
select I2C
help
Enable the Nuvoton NCT38xx TCPC multi-function device driver.
``` | /content/code_sandbox/drivers/mfd/Kconfig.nct38xx | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 66 |
```c
/*
*/
#define DT_DRV_COMPAT adi_ad559x
#include <zephyr/drivers/gpio.h>
#include <zephyr/kernel.h>
#include <zephyr/sys/byteorder.h>
#include <zephyr/drivers/mfd/ad559x.h>
#include "mfd_ad559x.h"
bool mfd_ad559x_has_pointer_byte_map(const struct device *dev)
{
const struct mfd_ad559x_config *config = dev->config;
return config->has_pointer_byte_map;
}
int mfd_ad559x_read_raw(const struct device *dev, uint8_t *val, size_t len)
{
struct mfd_ad559x_data *data = dev->data;
return data->transfer_function->read_raw(dev, val, len);
}
int mfd_ad559x_write_raw(const struct device *dev, uint8_t *val, size_t len)
{
struct mfd_ad559x_data *data = dev->data;
return data->transfer_function->write_raw(dev, val, len);
}
int mfd_ad559x_read_reg(const struct device *dev, uint8_t reg, uint8_t reg_data, uint16_t *val)
{
struct mfd_ad559x_data *data = dev->data;
return data->transfer_function->read_reg(dev, reg, reg_data, val);
}
int mfd_ad559x_write_reg(const struct device *dev, uint8_t reg, uint16_t val)
{
struct mfd_ad559x_data *data = dev->data;
return data->transfer_function->write_reg(dev, reg, val);
}
static int mfd_add559x_software_reset(const struct device *dev)
{
return mfd_ad559x_write_reg(dev, AD559X_REG_SOFTWARE_RESET,
AD559X_SOFTWARE_RESET_MAGIC_VAL);
}
static int mfd_ad559x_init(const struct device *dev)
{
const struct mfd_ad559x_config *config = dev->config;
int ret;
ret = config->bus_init(dev);
if (ret < 0) {
return ret;
}
if (!gpio_is_ready_dt(&config->reset_gpio)) {
return -ENODEV;
}
ret = gpio_pin_configure_dt(&config->reset_gpio, GPIO_OUTPUT_INACTIVE);
if (ret < 0) {
return ret;
}
ret = mfd_add559x_software_reset(dev);
if (ret < 0) {
return ret;
}
return 0;
}
#define MDF_AD559X_DEFINE_I2C_BUS(inst) \
.i2c = I2C_DT_SPEC_INST_GET(inst), .bus_init = mfd_ad559x_i2c_init, \
.has_pointer_byte_map = true
#define MDF_AD559X_DEFINE_SPI_BUS_FLAGS \
(SPI_WORD_SET(8) | SPI_TRANSFER_MSB | SPI_OP_MODE_MASTER | SPI_MODE_CPOL)
#define MDF_AD559X_DEFINE_SPI_BUS(inst) \
.spi = SPI_DT_SPEC_INST_GET(inst, MDF_AD559X_DEFINE_SPI_BUS_FLAGS, 0), \
.bus_init = mfd_ad559x_spi_init, .has_pointer_byte_map = false
#define MFD_AD559X_DEFINE_BUS(inst) \
COND_CODE_1(DT_INST_ON_BUS(inst, i2c), (MDF_AD559X_DEFINE_I2C_BUS(inst)), \
(MDF_AD559X_DEFINE_SPI_BUS(inst)))
#define MFD_AD559X_DEFINE(inst) \
static struct mfd_ad559x_data mfd_ad559x_data_##inst; \
static const struct mfd_ad559x_config mfd_ad559x_config_##inst = { \
.reset_gpio = GPIO_DT_SPEC_INST_GET(inst, reset_gpios), \
MFD_AD559X_DEFINE_BUS(inst), \
}; \
\
DEVICE_DT_INST_DEFINE(inst, mfd_ad559x_init, NULL, &mfd_ad559x_data_##inst, \
&mfd_ad559x_config_##inst, POST_KERNEL, CONFIG_MFD_INIT_PRIORITY, \
NULL);
DT_INST_FOREACH_STATUS_OKAY(MFD_AD559X_DEFINE);
``` | /content/code_sandbox/drivers/mfd/mfd_ad559x.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 870 |
```unknown
config MFD_MAX31790
bool "Maxim Integrated MAX31790 I2C configurable PWM controller"
default y
depends on DT_HAS_MAXIM_MAX31790_ENABLED
select I2C
help
Enable driver for Maxim Integrated MAX31790.
``` | /content/code_sandbox/drivers/mfd/Kconfig.max31790 | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 56 |
```unknown
menuconfig MFD
bool "Multi-function device (MFD) drivers"
help
Include drivers for multi-function devices
if MFD
module = MFD
module-str = mfd
source "subsys/logging/Kconfig.template.log_config"
config MFD_INIT_PRIORITY
int "Initialization priority"
default 80
help
Multi-function devices initialization priority.
source "drivers/mfd/Kconfig.ad559x"
source "drivers/mfd/Kconfig.adp5585"
source "drivers/mfd/Kconfig.axp192"
source "drivers/mfd/Kconfig.bd8lb600fs"
source "drivers/mfd/Kconfig.max20335"
source "drivers/mfd/Kconfig.max31790"
source "drivers/mfd/Kconfig.nct38xx"
source "drivers/mfd/Kconfig.npm1300"
source "drivers/mfd/Kconfig.npm6001"
source "drivers/mfd/Kconfig.lpflexcomm"
source "drivers/mfd/Kconfig.tle9104"
endif # MFD
``` | /content/code_sandbox/drivers/mfd/Kconfig | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 211 |
```c
/*
*/
#define DT_DRV_COMPAT nordic_npm1300
#include <errno.h>
#include <zephyr/drivers/i2c.h>
#include <zephyr/sys/util.h>
#include <zephyr/sys/byteorder.h>
#include <zephyr/drivers/gpio.h>
#include <zephyr/drivers/gpio/gpio_utils.h>
#include <zephyr/drivers/mfd/npm1300.h>
#define TIME_BASE 0x07U
#define MAIN_BASE 0x00U
#define SHIP_BASE 0x0BU
#define GPIO_BASE 0x06U
#define TIME_OFFSET_LOAD 0x03U
#define TIME_OFFSET_TIMER 0x08U
#define MAIN_OFFSET_RESET 0x01U
#define MAIN_OFFSET_SET 0x00U
#define MAIN_OFFSET_CLR 0x01U
#define MAIN_OFFSET_INTENSET 0x02U
#define MAIN_OFFSET_INTENCLR 0x03U
#define SHIP_OFFSET_HIBERNATE 0x00U
#define SHIP_OFFSET_CFGSTROBE 0x01U
#define SHIP_OFFSET_CONFIG 0x04U
#define SHIP_OFFSET_LPCONFIG 0x06U
#define GPIO_OFFSET_MODE 0x00U
#define TIMER_PRESCALER_MS 16U
#define TIMER_MAX 0xFFFFFFU
#define MAIN_SIZE 0x26U
#define GPIO_MODE_GPOIRQ 5
struct mfd_npm1300_config {
struct i2c_dt_spec i2c;
struct gpio_dt_spec host_int_gpios;
uint8_t pmic_int_pin;
uint8_t active_time;
uint8_t lp_reset;
};
struct mfd_npm1300_data {
struct k_mutex mutex;
const struct device *dev;
struct gpio_callback gpio_cb;
struct k_work work;
sys_slist_t callbacks;
};
struct event_reg_t {
uint8_t offset;
uint8_t mask;
};
static const struct event_reg_t event_reg[NPM1300_EVENT_MAX] = {
[NPM1300_EVENT_CHG_COMPLETED] = {0x0AU, 0x10U},
[NPM1300_EVENT_CHG_ERROR] = {0x0AU, 0x20U},
[NPM1300_EVENT_BATTERY_DETECTED] = {0x0EU, 0x01U},
[NPM1300_EVENT_BATTERY_REMOVED] = {0x0EU, 0x02U},
[NPM1300_EVENT_SHIPHOLD_PRESS] = {0x12U, 0x01U},
[NPM1300_EVENT_SHIPHOLD_RELEASE] = {0x12U, 0x02U},
[NPM1300_EVENT_WATCHDOG_WARN] = {0x12U, 0x08U},
[NPM1300_EVENT_VBUS_DETECTED] = {0x16U, 0x01U},
[NPM1300_EVENT_VBUS_REMOVED] = {0x16U, 0x02U},
[NPM1300_EVENT_GPIO0_EDGE] = {0x22U, 0x01U},
[NPM1300_EVENT_GPIO1_EDGE] = {0x22U, 0x02U},
[NPM1300_EVENT_GPIO2_EDGE] = {0x22U, 0x04U},
[NPM1300_EVENT_GPIO3_EDGE] = {0x22U, 0x08U},
[NPM1300_EVENT_GPIO4_EDGE] = {0x22U, 0x10U},
};
static void gpio_callback(const struct device *dev, struct gpio_callback *cb, uint32_t pins)
{
struct mfd_npm1300_data *data = CONTAINER_OF(cb, struct mfd_npm1300_data, gpio_cb);
k_work_submit(&data->work);
}
static void work_callback(struct k_work *work)
{
struct mfd_npm1300_data *data = CONTAINER_OF(work, struct mfd_npm1300_data, work);
const struct mfd_npm1300_config *config = data->dev->config;
uint8_t buf[MAIN_SIZE];
int ret;
/* Read all MAIN registers into temporary buffer */
ret = mfd_npm1300_reg_read_burst(data->dev, MAIN_BASE, 0U, buf, sizeof(buf));
if (ret < 0) {
k_work_submit(&data->work);
return;
}
for (int i = 0; i < NPM1300_EVENT_MAX; i++) {
int offset = event_reg[i].offset + MAIN_OFFSET_CLR;
if ((buf[offset] & event_reg[i].mask) != 0U) {
gpio_fire_callbacks(&data->callbacks, data->dev, BIT(i));
ret = mfd_npm1300_reg_write(data->dev, MAIN_BASE, offset,
event_reg[i].mask);
if (ret < 0) {
k_work_submit(&data->work);
return;
}
}
}
/* Resubmit handler to queue if interrupt is still active */
if (gpio_pin_get_dt(&config->host_int_gpios) != 0) {
k_work_submit(&data->work);
}
}
static int mfd_npm1300_init(const struct device *dev)
{
const struct mfd_npm1300_config *config = dev->config;
struct mfd_npm1300_data *mfd_data = dev->data;
int ret;
if (!i2c_is_ready_dt(&config->i2c)) {
return -ENODEV;
}
k_mutex_init(&mfd_data->mutex);
mfd_data->dev = dev;
if (config->host_int_gpios.port != NULL) {
/* Set specified PMIC pin to be interrupt output */
ret = mfd_npm1300_reg_write(dev, GPIO_BASE, GPIO_OFFSET_MODE + config->pmic_int_pin,
GPIO_MODE_GPOIRQ);
if (ret < 0) {
return ret;
}
/* Configure host interrupt GPIO */
if (!gpio_is_ready_dt(&config->host_int_gpios)) {
return -ENODEV;
}
ret = gpio_pin_configure_dt(&config->host_int_gpios, GPIO_INPUT);
if (ret < 0) {
return ret;
}
gpio_init_callback(&mfd_data->gpio_cb, gpio_callback,
BIT(config->host_int_gpios.pin));
ret = gpio_add_callback(config->host_int_gpios.port, &mfd_data->gpio_cb);
if (ret < 0) {
return ret;
}
mfd_data->work.handler = work_callback;
ret = gpio_pin_interrupt_configure_dt(&config->host_int_gpios,
GPIO_INT_EDGE_TO_ACTIVE);
if (ret < 0) {
return ret;
}
}
ret = mfd_npm1300_reg_write(dev, SHIP_BASE, SHIP_OFFSET_CONFIG, config->active_time);
if (ret < 0) {
return ret;
}
ret = mfd_npm1300_reg_write(dev, SHIP_BASE, SHIP_OFFSET_LPCONFIG, config->lp_reset);
if (ret < 0) {
return ret;
}
return mfd_npm1300_reg_write(dev, SHIP_BASE, SHIP_OFFSET_CFGSTROBE, 1U);
}
int mfd_npm1300_reg_read_burst(const struct device *dev, uint8_t base, uint8_t offset, void *data,
size_t len)
{
const struct mfd_npm1300_config *config = dev->config;
uint8_t buff[] = {base, offset};
return i2c_write_read_dt(&config->i2c, buff, sizeof(buff), data, len);
}
int mfd_npm1300_reg_read(const struct device *dev, uint8_t base, uint8_t offset, uint8_t *data)
{
return mfd_npm1300_reg_read_burst(dev, base, offset, data, 1U);
}
int mfd_npm1300_reg_write(const struct device *dev, uint8_t base, uint8_t offset, uint8_t data)
{
const struct mfd_npm1300_config *config = dev->config;
uint8_t buff[] = {base, offset, data};
return i2c_write_dt(&config->i2c, buff, sizeof(buff));
}
int mfd_npm1300_reg_write2(const struct device *dev, uint8_t base, uint8_t offset, uint8_t data1,
uint8_t data2)
{
const struct mfd_npm1300_config *config = dev->config;
uint8_t buff[] = {base, offset, data1, data2};
return i2c_write_dt(&config->i2c, buff, sizeof(buff));
}
int mfd_npm1300_reg_update(const struct device *dev, uint8_t base, uint8_t offset, uint8_t data,
uint8_t mask)
{
struct mfd_npm1300_data *mfd_data = dev->data;
uint8_t reg;
int ret;
k_mutex_lock(&mfd_data->mutex, K_FOREVER);
ret = mfd_npm1300_reg_read(dev, base, offset, ®);
if (ret == 0) {
reg = (reg & ~mask) | (data & mask);
ret = mfd_npm1300_reg_write(dev, base, offset, reg);
}
k_mutex_unlock(&mfd_data->mutex);
return ret;
}
int mfd_npm1300_set_timer(const struct device *dev, uint32_t time_ms)
{
const struct mfd_npm1300_config *config = dev->config;
uint8_t buff[5] = {TIME_BASE, TIME_OFFSET_TIMER};
uint32_t ticks = time_ms / TIMER_PRESCALER_MS;
if (ticks > TIMER_MAX) {
return -EINVAL;
}
sys_put_be24(ticks, &buff[2]);
int ret = i2c_write_dt(&config->i2c, buff, sizeof(buff));
if (ret != 0) {
return ret;
}
return mfd_npm1300_reg_write(dev, TIME_BASE, TIME_OFFSET_LOAD, 1U);
}
int mfd_npm1300_reset(const struct device *dev)
{
return mfd_npm1300_reg_write(dev, MAIN_BASE, MAIN_OFFSET_RESET, 1U);
}
int mfd_npm1300_hibernate(const struct device *dev, uint32_t time_ms)
{
int ret = mfd_npm1300_set_timer(dev, time_ms);
if (ret != 0) {
return ret;
}
return mfd_npm1300_reg_write(dev, SHIP_BASE, SHIP_OFFSET_HIBERNATE, 1U);
}
int mfd_npm1300_add_callback(const struct device *dev, struct gpio_callback *callback)
{
struct mfd_npm1300_data *data = dev->data;
/* Enable interrupts for specified events */
for (int i = 0; i < NPM1300_EVENT_MAX; i++) {
if ((callback->pin_mask & BIT(i)) != 0U) {
/* Clear pending interrupt */
int ret = mfd_npm1300_reg_write(data->dev, MAIN_BASE,
event_reg[i].offset + MAIN_OFFSET_CLR,
event_reg[i].mask);
if (ret < 0) {
return ret;
}
ret = mfd_npm1300_reg_write(data->dev, MAIN_BASE,
event_reg[i].offset + MAIN_OFFSET_INTENSET,
event_reg[i].mask);
if (ret < 0) {
return ret;
}
}
}
return gpio_manage_callback(&data->callbacks, callback, true);
}
int mfd_npm1300_remove_callback(const struct device *dev, struct gpio_callback *callback)
{
struct mfd_npm1300_data *data = dev->data;
return gpio_manage_callback(&data->callbacks, callback, false);
}
#define MFD_NPM1300_DEFINE(inst) \
static struct mfd_npm1300_data data_##inst; \
\
static const struct mfd_npm1300_config config##inst = { \
.i2c = I2C_DT_SPEC_INST_GET(inst), \
.host_int_gpios = GPIO_DT_SPEC_INST_GET_OR(inst, host_int_gpios, {0}), \
.pmic_int_pin = DT_INST_PROP_OR(inst, pmic_int_pin, 0), \
.active_time = DT_INST_ENUM_IDX(inst, ship_to_active_time_ms), \
.lp_reset = DT_INST_ENUM_IDX_OR(inst, long_press_reset, 0), \
}; \
\
DEVICE_DT_INST_DEFINE(inst, mfd_npm1300_init, NULL, &data_##inst, &config##inst, \
POST_KERNEL, CONFIG_MFD_NPM1300_INIT_PRIORITY, NULL);
DT_INST_FOREACH_STATUS_OKAY(MFD_NPM1300_DEFINE)
``` | /content/code_sandbox/drivers/mfd/mfd_npm1300.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 2,792 |
```unknown
config MFD_NPM1300
bool "nPM1300 PMIC multi-function device driver"
default y
depends on DT_HAS_NORDIC_NPM1300_ENABLED
select I2C
help
Enable the Nordic nPM1300 PMIC multi-function device driver
config MFD_NPM1300_INIT_PRIORITY
int "nPM1300 MFD initialization priority"
default MFD_INIT_PRIORITY
depends on MFD_NPM1300
help
Multi-function device initialization priority for nPM1300.
``` | /content/code_sandbox/drivers/mfd/Kconfig.npm1300 | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 113 |
```c
/*
*/
#define DT_DRV_COMPAT x_powers_axp192
#include <errno.h>
#include <stdbool.h>
#include <zephyr/drivers/mfd/axp192.h>
#include <zephyr/drivers/i2c.h>
#include <zephyr/sys/util.h>
#include <zephyr/logging/log.h>
LOG_MODULE_REGISTER(mfd_axp192, CONFIG_MFD_LOG_LEVEL);
/* Chip ID value */
#define AXP192_CHIP_ID 0x03U
/* Registers definitions */
#define AXP192_REG_CHIP_ID 0x03U
/* AXP192 GPIO register addresses */
#define AXP192_EXTEN_DCDC2_CONTROL_REG 0x10U
#define AXP192_VBUS_CFG_REG 0x30U
#define AXP192_GPIO0_FUNC_REG 0x90U
#define AXP192_GPIO1_FUNC_REG 0x92U
#define AXP192_GPIO2_FUNC_REG 0x93U
#define AXP192_GPIO34_FUNC_REG 0x95U
#define AXP192_GPIO012_PINVAL_REG 0x94U
#define AXP192_GPIO34_PINVAL_REG 0x96U
#define AXP192_GPIO012_PULLDOWN_REG 0x97U
/* VBUS control reg values */
#define AXP192_VBUS_CFG_VAL_VBUSEN_DISABLE 0x80U
/* GPIO function control parameters */
#define AXP192_GPIO012_FUNC_VAL_OUTPUT_OD 0x00U
#define AXP192_GPIO012_FUNC_VAL_INPUT 0x01U
#define AXP192_GPIO012_FUNC_VAL_LDO 0x02U /* only applicable for GPIO0 */
#define AXP192_GPIO012_FUNC_VAL_ADC 0x04U
#define AXP192_GPIO012_FUNC_VAL_OUTPUT_LOW 0x05U
#define AXP192_GPIO012_FUNC_VAL_FLOAT 0x06U
#define AXP192_GPIO012_FUNC_MASK \
(AXP192_GPIO012_FUNC_VAL_OUTPUT_OD | AXP192_GPIO012_FUNC_VAL_INPUT | \
AXP192_GPIO012_FUNC_VAL_LDO | AXP192_GPIO012_FUNC_VAL_ADC | \
AXP192_GPIO012_FUNC_VAL_OUTPUT_LOW | AXP192_GPIO012_FUNC_VAL_FLOAT)
#define AXP192_GPIO34_FUNC_ENA 0x80U
#define AXP192_GPIO3_FUNC_VAL_CHARGE_CTL 0x00U
#define AXP192_GPIO3_FUNC_VAL_OUTPUT_OD 0x01U
#define AXP192_GPIO3_FUNC_VAL_INPUT 0x02U
#define AXP192_GPIO3_FUNC_MASK \
(AXP192_GPIO34_FUNC_ENA | AXP192_GPIO3_FUNC_VAL_CHARGE_CTL | \
AXP192_GPIO3_FUNC_VAL_OUTPUT_OD | AXP192_GPIO3_FUNC_VAL_INPUT)
#define AXP192_GPIO4_FUNC_VAL_CHARGE_CTL 0x00U
#define AXP192_GPIO4_FUNC_VAL_OUTPUT_OD 0x04U
#define AXP192_GPIO4_FUNC_VAL_INPUT 0x08U
#define AXP192_GPIO4_FUNC_VAL_ADC 0x0CU
#define AXP192_GPIO4_FUNC_MASK \
(AXP192_GPIO34_FUNC_ENA | AXP192_GPIO4_FUNC_VAL_CHARGE_CTL | \
AXP192_GPIO4_FUNC_VAL_OUTPUT_OD | AXP192_GPIO4_FUNC_VAL_INPUT)
#define AXP192_EXTEN_ENA 0x04U
#define AXP192_EXTEN_MASK 0x04U
/* Pull-Down enable parameters */
#define AXP192_GPIO0_PULLDOWN_ENABLE 0x01U
#define AXP192_GPIO1_PULLDOWN_ENABLE 0x02U
#define AXP192_GPIO2_PULLDOWN_ENABLE 0x04U
/* GPIO Value parameters */
#define AXP192_GPIO0_INPUT_VAL 0x10U
#define AXP192_GPIO1_INPUT_VAL 0x20U
#define AXP192_GPIO2_INPUT_VAL 0x40U
#define AXP192_GPIO012_INTPUT_SHIFT 4U
#define AXP192_GPIO012_INTPUT_MASK \
(AXP192_GPIO0_INPUT_VAL | AXP192_GPIO1_INPUT_VAL | AXP192_GPIO2_INPUT_VAL)
#define AXP192_GPIO3_INPUT_VAL 0x10U
#define AXP192_GPIO4_INPUT_VAL 0x20U
#define AXP192_GPIO34_INTPUT_SHIFT 4U
#define AXP192_GPIO34_INTPUT_MASK (AXP192_GPIO3_INPUT_VAL | AXP192_GPIO4_INPUT_VAL)
#define AXP192_GPIO0_OUTPUT_VAL 0x01U
#define AXP192_GPIO1_OUTPUT_VAL 0x02U
#define AXP192_GPIO2_OUTPUT_VAL 0x04U
#define AXP192_GPIO012_OUTPUT_MASK \
(AXP192_GPIO0_OUTPUT_VAL | AXP192_GPIO1_OUTPUT_VAL | AXP192_GPIO2_OUTPUT_VAL)
#define AXP192_GPIO3_OUTPUT_VAL 0x01U
#define AXP192_GPIO4_OUTPUT_VAL 0x02U
#define AXP192_GPIO34_OUTPUT_MASK (AXP192_GPIO3_OUTPUT_VAL | AXP192_GPIO4_OUTPUT_VAL)
#define AXP192_GPIO5_OUTPUT_MASK 0x04U
#define AXP192_GPIO5_OUTPUT_VAL 0x04U
#define AXP192_GPIO5_OUTPUT_SHIFT 3U
struct mfd_axp192_config {
struct i2c_dt_spec i2c;
bool vbusen_disable;
};
struct mfd_axp192_data {
const struct device *gpio_mask_used[AXP192_GPIO_MAX_NUM];
uint8_t gpio_mask_output;
};
struct mfd_axp192_func_reg_desc {
uint8_t reg;
uint8_t mask;
};
const struct mfd_axp192_func_reg_desc gpio_reg_desc[AXP192_GPIO_MAX_NUM] = {
{
/* GPIO0 */
.reg = AXP192_GPIO0_FUNC_REG,
.mask = AXP192_GPIO012_FUNC_MASK,
},
{
/* GPIO1 */
.reg = AXP192_GPIO1_FUNC_REG,
.mask = AXP192_GPIO012_FUNC_MASK,
},
{
/* GPIO2 */
.reg = AXP192_GPIO2_FUNC_REG,
.mask = AXP192_GPIO012_FUNC_MASK,
},
{
/* GPIO3 */
.reg = AXP192_GPIO34_FUNC_REG,
.mask = AXP192_GPIO3_FUNC_MASK,
},
{
/* GPIO4 */
.reg = AXP192_GPIO34_FUNC_REG,
.mask = AXP192_GPIO4_FUNC_MASK,
},
};
static int mfd_axp192_init(const struct device *dev)
{
const struct mfd_axp192_config *config = dev->config;
uint8_t chip_id;
uint8_t vbus_val;
int ret;
LOG_DBG("Initializing instance");
if (!i2c_is_ready_dt(&config->i2c)) {
LOG_ERR("I2C bus not ready");
return -ENODEV;
}
/* Check if axp192 chip is available */
ret = i2c_reg_read_byte_dt(&config->i2c, AXP192_REG_CHIP_ID, &chip_id);
if (ret < 0) {
return ret;
}
if (chip_id != AXP192_CHIP_ID) {
LOG_ERR("Invalid Chip detected (%d)", chip_id);
return -EINVAL;
}
/* Disable N_VBUSEN */
vbus_val = 0;
if (config->vbusen_disable) {
vbus_val = AXP192_VBUS_CFG_VAL_VBUSEN_DISABLE;
}
ret = i2c_reg_update_byte_dt(&config->i2c, AXP192_VBUS_CFG_REG,
AXP192_VBUS_CFG_VAL_VBUSEN_DISABLE, vbus_val);
if (ret < 0) {
return ret;
}
return 0;
}
int mfd_axp192_gpio_func_get(const struct device *dev, uint8_t gpio, enum axp192_gpio_func *func)
{
const struct mfd_axp192_config *config = dev->config;
int ret;
uint8_t reg_fnc;
if (gpio >= AXP192_GPIO_MAX_NUM) {
LOG_ERR("Invalid gpio (%d)", gpio);
return -EINVAL;
}
if (gpio < ARRAY_SIZE(gpio_reg_desc)) {
ret = i2c_reg_read_byte_dt(&(config->i2c), gpio_reg_desc[gpio].reg, ®_fnc);
if (ret != 0) {
return ret;
}
}
switch (gpio) {
case 0U:
__fallthrough;
case 1U:
__fallthrough;
case 2U:
/* GPIO 0-2*/
switch (reg_fnc) {
case AXP192_GPIO012_FUNC_VAL_INPUT:
*func = AXP192_GPIO_FUNC_INPUT;
break;
case AXP192_GPIO012_FUNC_VAL_OUTPUT_OD:
*func = AXP192_GPIO_FUNC_OUTPUT_OD;
break;
case AXP192_GPIO012_FUNC_VAL_OUTPUT_LOW:
*func = AXP192_GPIO_FUNC_OUTPUT_LOW;
break;
case AXP192_GPIO012_FUNC_VAL_LDO:
if (gpio == 0) {
/* LDO is only applicable on GPIO0 */
*func = AXP192_GPIO_FUNC_LDO;
} else {
ret = -ENOTSUP;
}
break;
case AXP192_GPIO012_FUNC_VAL_ADC:
*func = AXP192_GPIO_FUNC_ADC;
break;
case AXP192_GPIO012_FUNC_VAL_FLOAT:
*func = AXP192_GPIO_FUNC_FLOAT;
break;
default:
ret = -ENOTSUP;
break;
}
break;
case 3U:
/* GPIO3 */
switch (reg_fnc) {
case (AXP192_GPIO3_FUNC_VAL_INPUT | AXP192_GPIO34_FUNC_ENA):
*func = AXP192_GPIO_FUNC_INPUT;
break;
case (AXP192_GPIO3_FUNC_VAL_OUTPUT_OD | AXP192_GPIO34_FUNC_ENA):
*func = AXP192_GPIO_FUNC_OUTPUT_OD;
break;
case AXP192_GPIO3_FUNC_VAL_CHARGE_CTL:
*func = AXP192_GPIO_FUNC_CHARGE_CTL;
break;
default:
ret = -ENOTSUP;
break;
}
break;
case 4U:
/* GPIO4 */
switch (reg_fnc) {
case (AXP192_GPIO4_FUNC_VAL_INPUT | AXP192_GPIO34_FUNC_ENA):
*func = AXP192_GPIO_FUNC_INPUT;
break;
case (AXP192_GPIO4_FUNC_VAL_OUTPUT_OD | AXP192_GPIO34_FUNC_ENA):
*func = AXP192_GPIO_FUNC_OUTPUT_OD;
break;
case (AXP192_GPIO4_FUNC_VAL_ADC | AXP192_GPIO34_FUNC_ENA):
*func = AXP192_GPIO_FUNC_ADC;
break;
case AXP192_GPIO4_FUNC_VAL_CHARGE_CTL:
*func = AXP192_GPIO_FUNC_CHARGE_CTL;
break;
default:
ret = -ENOTSUP;
break;
}
break;
case 5U:
/* EXTEN is an output only pin */
*func = AXP192_GPIO_FUNC_OUTPUT_LOW;
break;
default:
ret = -EINVAL;
}
return ret;
}
int mfd_axp192_gpio_func_ctrl(const struct device *dev, const struct device *client_dev,
uint8_t gpio, enum axp192_gpio_func func)
{
const struct mfd_axp192_config *config = dev->config;
struct mfd_axp192_data *data = dev->data;
bool is_output = false;
int ret = 0;
uint8_t reg_cfg = 0;
if (!AXP192_GPIO_FUNC_VALID(func)) {
LOG_ERR("Invalid function");
return -EINVAL;
}
if (gpio >= AXP192_GPIO_MAX_NUM) {
LOG_ERR("Invalid gpio (%d)", gpio);
return -EINVAL;
}
if ((data->gpio_mask_used[gpio] != 0) && (data->gpio_mask_used[gpio] != client_dev)) {
LOG_INF("Warning: Pin already configured. Please check dt configuration");
}
switch (gpio) {
case 0U:
__fallthrough;
case 1U:
__fallthrough;
case 2U:
/* GPIO 0-2*/
switch (func) {
case AXP192_GPIO_FUNC_INPUT:
reg_cfg = AXP192_GPIO012_FUNC_VAL_INPUT;
break;
case AXP192_GPIO_FUNC_OUTPUT_OD:
reg_cfg = AXP192_GPIO012_FUNC_VAL_OUTPUT_OD;
is_output = true;
break;
case AXP192_GPIO_FUNC_OUTPUT_LOW:
reg_cfg = AXP192_GPIO012_FUNC_VAL_OUTPUT_LOW;
is_output = true;
break;
case AXP192_GPIO_FUNC_LDO:
if (gpio == 0) {
/* LDO is only applicable on GPIO0 */
reg_cfg = AXP192_GPIO012_FUNC_VAL_LDO;
} else {
ret = -ENOTSUP;
}
break;
case AXP192_GPIO_FUNC_ADC:
reg_cfg = AXP192_GPIO012_FUNC_VAL_ADC;
break;
case AXP192_GPIO_FUNC_FLOAT:
reg_cfg = AXP192_GPIO012_FUNC_VAL_FLOAT;
break;
default:
ret = -ENOTSUP;
break;
}
break;
case 3U:
/* GPIO3 */
switch (func) {
case AXP192_GPIO_FUNC_INPUT:
reg_cfg = AXP192_GPIO3_FUNC_VAL_INPUT | AXP192_GPIO34_FUNC_ENA;
break;
case AXP192_GPIO_FUNC_OUTPUT_OD:
reg_cfg = AXP192_GPIO3_FUNC_VAL_OUTPUT_OD | AXP192_GPIO34_FUNC_ENA;
is_output = true;
break;
case AXP192_GPIO_FUNC_CHARGE_CTL:
reg_cfg = AXP192_GPIO3_FUNC_VAL_CHARGE_CTL;
break;
default:
ret = -ENOTSUP;
break;
}
break;
case 4U:
/* GPIO4 */
switch (func) {
case AXP192_GPIO_FUNC_INPUT:
reg_cfg = AXP192_GPIO4_FUNC_VAL_INPUT | AXP192_GPIO34_FUNC_ENA;
break;
case AXP192_GPIO_FUNC_OUTPUT_OD:
reg_cfg = AXP192_GPIO4_FUNC_VAL_OUTPUT_OD | AXP192_GPIO34_FUNC_ENA;
is_output = true;
break;
case AXP192_GPIO_FUNC_ADC:
reg_cfg = AXP192_GPIO4_FUNC_VAL_ADC | AXP192_GPIO34_FUNC_ENA;
break;
case AXP192_GPIO_FUNC_CHARGE_CTL:
reg_cfg = AXP192_GPIO4_FUNC_VAL_CHARGE_CTL;
break;
default:
ret = -ENOTSUP;
break;
}
break;
case 5U:
/* EXTEN is an output only pin */
break;
default:
ret = -EINVAL;
}
if (ret != 0) {
LOG_ERR("Invalid function (0x%x) for gpio %d", func, gpio);
return ret;
}
if (gpio < ARRAY_SIZE(gpio_reg_desc)) {
ret = i2c_reg_update_byte_dt(&(config->i2c), gpio_reg_desc[gpio].reg,
gpio_reg_desc[gpio].mask, reg_cfg);
if (ret != 0) {
return ret;
}
}
/* Save gpio configuration state */
data->gpio_mask_used[gpio] = client_dev;
if (is_output) {
data->gpio_mask_output |= (1u << gpio);
} else {
data->gpio_mask_output &= ~(1u << gpio);
}
LOG_DBG("GPIO %d configured successfully (func=0x%x)", gpio, reg_cfg);
return 0;
}
int mfd_axp192_gpio_pd_get(const struct device *dev, uint8_t gpio, bool *enabled)
{
const struct mfd_axp192_config *config = dev->config;
uint8_t gpio_val;
uint8_t pd_reg_mask = 0;
int ret = 0;
switch (gpio) {
case 0U:
pd_reg_mask = AXP192_GPIO0_PULLDOWN_ENABLE;
break;
case 1U:
pd_reg_mask = AXP192_GPIO1_PULLDOWN_ENABLE;
break;
case 2U:
pd_reg_mask = AXP192_GPIO2_PULLDOWN_ENABLE;
break;
case 3U:
__fallthrough;
case 4U:
__fallthrough;
case 5U:
LOG_DBG("Pull-Down not support on gpio %d", gpio);
return -ENOTSUP;
default:
LOG_ERR("Invalid gpio (%d)", gpio);
return -EINVAL;
}
ret = i2c_reg_read_byte_dt(&(config->i2c), AXP192_GPIO012_PULLDOWN_REG, &gpio_val);
if (ret == 0) {
*enabled = ((gpio_val & pd_reg_mask) != 0);
LOG_DBG("Pull-Down stats of gpio %d: %d", gpio, *enabled);
}
return 0;
}
int mfd_axp192_gpio_pd_ctrl(const struct device *dev, uint8_t gpio, bool enable)
{
uint8_t reg_pd_val = 0;
uint8_t reg_pd_mask = 0;
const struct mfd_axp192_config *config = dev->config;
int ret = 0;
/* Configure pull-down. Pull-down is only supported by GPIO3 and GPIO4 */
switch (gpio) {
case 0U:
reg_pd_mask = AXP192_GPIO0_PULLDOWN_ENABLE;
if (enable) {
reg_pd_val = AXP192_GPIO0_PULLDOWN_ENABLE;
}
break;
case 1U:
reg_pd_mask = AXP192_GPIO1_PULLDOWN_ENABLE;
if (enable) {
reg_pd_val = AXP192_GPIO1_PULLDOWN_ENABLE;
}
break;
case 2U:
reg_pd_mask = AXP192_GPIO2_PULLDOWN_ENABLE;
if (enable) {
reg_pd_val = AXP192_GPIO2_PULLDOWN_ENABLE;
}
break;
case 3U:
__fallthrough;
case 4U:
__fallthrough;
case 5U:
LOG_ERR("Pull-Down not support on gpio %d", gpio);
return -ENOTSUP;
default:
LOG_ERR("Invalid gpio (%d)", gpio);
return -EINVAL;
}
ret = i2c_reg_update_byte_dt(&(config->i2c), AXP192_GPIO012_PULLDOWN_REG, reg_pd_mask,
reg_pd_val);
return ret;
}
int mfd_axp192_gpio_read_port(const struct device *dev, uint8_t *value)
{
const struct mfd_axp192_config *config = dev->config;
const struct mfd_axp192_data *data = dev->data;
int ret;
uint8_t gpio012_val;
uint8_t gpio34_val;
uint8_t gpio5_val;
uint8_t gpio_input_val;
uint8_t gpio_output_val;
/* read gpio0-2 */
ret = i2c_reg_read_byte_dt(&(config->i2c), AXP192_GPIO012_PINVAL_REG, &gpio012_val);
if (ret != 0) {
return ret;
}
/* read gpio3-4 */
ret = i2c_reg_read_byte_dt(&(config->i2c), AXP192_GPIO34_PINVAL_REG, &gpio34_val);
if (ret != 0) {
return ret;
}
/* read gpio5 */
ret = i2c_reg_read_byte_dt(&(config->i2c), AXP192_EXTEN_DCDC2_CONTROL_REG, &gpio5_val);
if (ret != 0) {
return ret;
}
LOG_DBG("GPIO012 pinval-reg=0x%x", gpio012_val);
LOG_DBG("GPIO34 pinval-reg =0x%x", gpio34_val);
LOG_DBG("GPIO5 pinval-reg =0x%x", gpio5_val);
LOG_DBG("Output-Mask =0x%x", data->gpio_mask_output);
gpio_input_val =
((gpio012_val & AXP192_GPIO012_INTPUT_MASK) >> AXP192_GPIO012_INTPUT_SHIFT);
gpio_input_val |=
(((gpio34_val & AXP192_GPIO34_INTPUT_MASK) >> AXP192_GPIO34_INTPUT_SHIFT) << 3u);
gpio_output_val = (gpio012_val & AXP192_GPIO012_OUTPUT_MASK);
gpio_output_val |= ((gpio34_val & AXP192_GPIO34_OUTPUT_MASK) << 3u);
gpio_output_val |=
(((gpio5_val & AXP192_GPIO5_OUTPUT_MASK) >> AXP192_GPIO5_OUTPUT_SHIFT) << 5u);
*value = gpio_input_val & ~(data->gpio_mask_output);
*value |= (gpio_output_val & data->gpio_mask_output);
return 0;
}
int mfd_axp192_gpio_write_port(const struct device *dev, uint8_t value, uint8_t mask)
{
const struct mfd_axp192_config *config = dev->config;
int ret;
uint8_t gpio_reg_val;
uint8_t gpio_reg_mask;
/* Write gpio0-2. Mask out other port pins */
gpio_reg_val = (value & AXP192_GPIO012_OUTPUT_MASK);
gpio_reg_mask = (mask & AXP192_GPIO012_OUTPUT_MASK);
if (gpio_reg_mask != 0) {
ret = i2c_reg_update_byte_dt(&(config->i2c), AXP192_GPIO012_PINVAL_REG,
gpio_reg_mask, gpio_reg_val);
if (ret != 0) {
return ret;
}
LOG_DBG("GPIO012 pinval-reg=0x%x mask=0x%x", gpio_reg_val, gpio_reg_mask);
}
/* Write gpio3-4. Mask out other port pins */
gpio_reg_val = value >> 3U;
gpio_reg_mask = (mask >> 3U) & AXP192_GPIO34_OUTPUT_MASK;
if (gpio_reg_mask != 0) {
ret = i2c_reg_update_byte_dt(&(config->i2c), AXP192_GPIO34_PINVAL_REG,
gpio_reg_mask, gpio_reg_val);
if (ret != 0) {
return ret;
}
LOG_DBG("GPIO34 pinval-reg =0x%x mask=0x%x", gpio_reg_val, gpio_reg_mask);
}
/* Write gpio5. Mask out other port pins */
if ((mask & BIT(5)) != 0) {
gpio_reg_mask = AXP192_EXTEN_MASK;
gpio_reg_val = (value & BIT(5)) ? AXP192_EXTEN_ENA : 0U;
ret = i2c_reg_update_byte_dt(&(config->i2c), AXP192_EXTEN_DCDC2_CONTROL_REG,
gpio_reg_mask, gpio_reg_val);
if (ret != 0) {
return ret;
}
LOG_DBG("GPIO5 pinval-reg =0x%x mask=0x%x\n", gpio_reg_val, gpio_reg_mask);
}
return 0;
}
#define MFD_AXP192_DEFINE(inst) \
static const struct mfd_axp192_config config##inst = { \
.i2c = I2C_DT_SPEC_INST_GET(inst), \
.vbusen_disable = DT_INST_PROP_OR(inst, vbusen_disable, false), \
}; \
\
static struct mfd_axp192_data data##inst; \
\
DEVICE_DT_INST_DEFINE(inst, mfd_axp192_init, NULL, &data##inst, &config##inst, \
POST_KERNEL, CONFIG_MFD_INIT_PRIORITY, NULL);
DT_INST_FOREACH_STATUS_OKAY(MFD_AXP192_DEFINE);
``` | /content/code_sandbox/drivers/mfd/mfd_axp192.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 5,196 |
```c
/*
*/
#define DT_DRV_COMPAT nuvoton_nct38xx
#include <zephyr/drivers/i2c.h>
struct mfd_nct38xx_config {
const struct i2c_dt_spec i2c_dev;
};
struct mfd_nct38xx_data {
/* lock NC38xx register access */
struct k_sem lock;
};
static int mfd_nct38xx_init(const struct device *dev)
{
const struct mfd_nct38xx_config *config = dev->config;
struct mfd_nct38xx_data *data = dev->data;
if (!device_is_ready(config->i2c_dev.bus)) {
return -ENODEV;
}
k_sem_init(&data->lock, 1, 1);
return 0;
}
struct k_sem *mfd_nct38xx_get_lock_reference(const struct device *dev)
{
struct mfd_nct38xx_data *data = dev->data;
return &data->lock;
}
const struct i2c_dt_spec *mfd_nct38xx_get_i2c_dt_spec(const struct device *dev)
{
const struct mfd_nct38xx_config *config = dev->config;
return &config->i2c_dev;
}
#define MFD_NCT38XX_DEFINE(inst) \
static struct mfd_nct38xx_data nct38xx_data_##inst; \
static const struct mfd_nct38xx_config nct38xx_cfg_##inst = { \
.i2c_dev = I2C_DT_SPEC_INST_GET(inst), \
}; \
\
DEVICE_DT_INST_DEFINE(inst, mfd_nct38xx_init, NULL, &nct38xx_data_##inst, \
&nct38xx_cfg_##inst, POST_KERNEL, CONFIG_MFD_INIT_PRIORITY, NULL);
DT_INST_FOREACH_STATUS_OKAY(MFD_NCT38XX_DEFINE)
``` | /content/code_sandbox/drivers/mfd/mfd_nct38xx.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 396 |
```c
/*
*/
#include <zephyr/arch/arm64/hypercall.h>
#include <zephyr/xen/generic.h>
#include <zephyr/xen/public/memory.h>
#include <zephyr/xen/public/xen.h>
#include <zephyr/kernel.h>
int xendom_add_to_physmap(int domid, unsigned long idx,
unsigned int space, xen_pfn_t gpfn)
{
struct xen_add_to_physmap xatp = {
.domid = domid,
.idx = idx,
.space = space,
.gpfn = gpfn,
};
return HYPERVISOR_memory_op(XENMEM_add_to_physmap, &xatp);
}
int xendom_add_to_physmap_batch(int domid, int foreign_domid,
unsigned int space, unsigned int size,
xen_ulong_t *idxs, xen_pfn_t *gpfns, int *errs)
{
struct xen_add_to_physmap_batch xatpb = {
.domid = domid,
.u.foreign_domid = foreign_domid,
.space = space,
.size = size,
};
set_xen_guest_handle(xatpb.gpfns, gpfns);
set_xen_guest_handle(xatpb.idxs, idxs);
set_xen_guest_handle(xatpb.errs, errs);
return HYPERVISOR_memory_op(XENMEM_add_to_physmap_batch, &xatpb);
}
int xendom_remove_from_physmap(int domid, xen_pfn_t gpfn)
{
struct xen_remove_from_physmap xrfp = {
.domid = domid,
.gpfn = gpfn,
};
return HYPERVISOR_memory_op(XENMEM_remove_from_physmap, &xrfp);
}
int xendom_populate_physmap(int domid, unsigned int extent_order,
unsigned int nr_extents, unsigned int mem_flags,
xen_pfn_t *extent_start)
{
struct xen_memory_reservation reservation = {
.domid = domid,
.extent_order = extent_order,
.nr_extents = nr_extents,
.mem_flags = mem_flags,
};
set_xen_guest_handle(reservation.extent_start, extent_start);
return HYPERVISOR_memory_op(XENMEM_populate_physmap, &reservation);
}
``` | /content/code_sandbox/drivers/xen/memory.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 496 |
```unknown
if XEN
menu "Xen drivers"
config XEN_GRANT_TABLE
bool "Xen grant table driver"
depends on HEAP_MEM_POOL_SIZE > 0
default y
help
Xen grant table driver. Please note that driver uses dynamic memory
allocation with k_malloc(), so CONFIG_HEAP_MEM_POOL_SIZE should be
>= number of pages, that you want to alloc and grant or foreign frames
that you want to map.
config XEN_GRANT_TABLE_INIT_PRIORITY
int "Grant table driver init priority"
depends on XEN_GRANT_TABLE
default 50
endmenu
endif # XEN
``` | /content/code_sandbox/drivers/xen/Kconfig | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 134 |
```c
/*
*
*/
#include <zephyr/arch/arm64/hypercall.h>
#include <zephyr/xen/hvm.h>
#include <zephyr/xen/public/hvm/hvm_op.h>
#include <zephyr/xen/public/hvm/params.h>
#include <zephyr/kernel.h>
int hvm_set_parameter(int idx, int domid, uint64_t value)
{
struct xen_hvm_param xhv;
xhv.domid = domid;
xhv.index = idx;
xhv.value = value;
return HYPERVISOR_hvm_op(HVMOP_set_param, &xhv);
}
int hvm_get_parameter(int idx, int domid, uint64_t *value)
{
int ret = 0;
struct xen_hvm_param xhv;
xhv.domid = domid;
xhv.index = idx;
ret = HYPERVISOR_hvm_op(HVMOP_get_param, &xhv);
if (ret < 0) {
return ret;
}
*value = xhv.value;
return ret;
}
``` | /content/code_sandbox/drivers/xen/hvm.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 222 |
```c
/*
****************************************************************************
* (C) 2006 - Cambridge University
* (C) 2021-2022 - EPAM Systems
****************************************************************************
*
* File: gnttab.c
* Author: Steven Smith (sos22@cam.ac.uk)
* Changes: Grzegorz Milos (gm281@cam.ac.uk)
*
* Date: July 2006
*
* Environment: Xen Minimal OS
* Description: Simple grant tables implementation. About as stupid as it's
* possible to be and still work.
*
****************************************************************************
*/
#include <zephyr/arch/arm64/hypercall.h>
#include <zephyr/xen/generic.h>
#include <zephyr/xen/gnttab.h>
#include <zephyr/xen/public/grant_table.h>
#include <zephyr/xen/public/memory.h>
#include <zephyr/xen/public/xen.h>
#include <zephyr/sys/barrier.h>
#include <zephyr/init.h>
#include <zephyr/kernel.h>
#include <zephyr/logging/log.h>
#include <zephyr/sys/device_mmio.h>
LOG_MODULE_REGISTER(xen_gnttab);
/* Timeout for grant table ops retrying */
#define GOP_RETRY_DELAY 200
#define GNTTAB_SIZE DT_REG_SIZE_BY_IDX(DT_INST(0, xen_xen), 0)
BUILD_ASSERT(!(GNTTAB_SIZE % XEN_PAGE_SIZE), "Size of gnttab have to be aligned on XEN_PAGE_SIZE");
/* NR_GRANT_FRAMES must be less than or equal to that configured in Xen */
#define NR_GRANT_FRAMES (GNTTAB_SIZE / XEN_PAGE_SIZE)
#define NR_GRANT_ENTRIES \
(NR_GRANT_FRAMES * XEN_PAGE_SIZE / sizeof(grant_entry_v1_t))
BUILD_ASSERT(GNTTAB_SIZE <= CONFIG_KERNEL_VM_SIZE);
DEVICE_MMIO_TOPLEVEL_STATIC(grant_tables, DT_INST(0, xen_xen));
static struct gnttab {
struct k_sem sem;
grant_entry_v1_t *table;
grant_ref_t gref_list[NR_GRANT_ENTRIES];
} gnttab;
static grant_ref_t get_free_entry(void)
{
grant_ref_t gref;
unsigned int flags;
k_sem_take(&gnttab.sem, K_FOREVER);
flags = irq_lock();
gref = gnttab.gref_list[0];
__ASSERT((gref >= GNTTAB_NR_RESERVED_ENTRIES &&
gref < NR_GRANT_ENTRIES), "Invalid gref = %d", gref);
gnttab.gref_list[0] = gnttab.gref_list[gref];
irq_unlock(flags);
return gref;
}
static void put_free_entry(grant_ref_t gref)
{
unsigned int flags;
flags = irq_lock();
gnttab.gref_list[gref] = gnttab.gref_list[0];
gnttab.gref_list[0] = gref;
irq_unlock(flags);
k_sem_give(&gnttab.sem);
}
static void gnttab_grant_permit_access(grant_ref_t gref, domid_t domid,
unsigned long gfn, bool readonly)
{
uint16_t flags = GTF_permit_access;
if (readonly) {
flags |= GTF_readonly;
}
gnttab.table[gref].frame = gfn;
gnttab.table[gref].domid = domid;
/* Need to be sure that gfn and domid will be set before flags */
barrier_dmem_fence_full();
gnttab.table[gref].flags = flags;
}
grant_ref_t gnttab_grant_access(domid_t domid, unsigned long gfn,
bool readonly)
{
grant_ref_t gref = get_free_entry();
gnttab_grant_permit_access(gref, domid, gfn, readonly);
return gref;
}
/* Reset flags to zero in order to stop using the grant */
static int gnttab_reset_flags(grant_ref_t gref)
{
uint16_t flags, nflags;
uint16_t *pflags;
pflags = &gnttab.table[gref].flags;
nflags = *pflags;
do {
flags = nflags;
if (flags & (GTF_reading | GTF_writing)) {
LOG_WRN("gref = %u still in use! (0x%x)\n",
gref, flags);
return 1;
}
nflags = synch_cmpxchg(pflags, flags, 0);
} while (nflags != flags);
return 0;
}
int gnttab_end_access(grant_ref_t gref)
{
int rc;
__ASSERT((gref >= GNTTAB_NR_RESERVED_ENTRIES &&
gref < NR_GRANT_ENTRIES), "Invalid gref = %d", gref);
rc = gnttab_reset_flags(gref);
if (!rc) {
return rc;
}
put_free_entry(gref);
return 0;
}
int32_t gnttab_alloc_and_grant(void **map, bool readonly)
{
void *page;
unsigned long gfn;
grant_ref_t gref;
__ASSERT_NO_MSG(map != NULL);
page = k_aligned_alloc(XEN_PAGE_SIZE, XEN_PAGE_SIZE);
if (page == NULL) {
return -ENOMEM;
}
gfn = xen_virt_to_gfn(page);
gref = gnttab_grant_access(0, gfn, readonly);
*map = page;
return gref;
}
static void gop_eagain_retry(int cmd, struct gnttab_map_grant_ref *gref)
{
unsigned int step = 10, delay = step;
int16_t *status = &gref->status;
do {
HYPERVISOR_grant_table_op(cmd, gref, 1);
if (*status == GNTST_eagain) {
k_sleep(K_MSEC(delay));
}
delay += step;
} while ((*status == GNTST_eagain) && (delay < GOP_RETRY_DELAY));
if (delay >= GOP_RETRY_DELAY) {
LOG_ERR("Failed to map grant, timeout reached\n");
*status = GNTST_bad_page;
}
}
void *gnttab_get_page(void)
{
int ret;
void *page_addr;
struct xen_remove_from_physmap rfpm;
page_addr = k_aligned_alloc(XEN_PAGE_SIZE, XEN_PAGE_SIZE);
if (!page_addr) {
LOG_WRN("Failed to allocate memory for gnttab page!\n");
return NULL;
}
rfpm.domid = DOMID_SELF;
rfpm.gpfn = xen_virt_to_gfn(page_addr);
/*
* GNTTABOP_map_grant_ref will simply replace the entry in the P2M
* and not release any RAM that may have been associated with
* page_addr, so we release this memory before mapping.
*/
ret = HYPERVISOR_memory_op(XENMEM_remove_from_physmap, &rfpm);
if (ret) {
LOG_WRN("Failed to remove gnttab page from physmap, ret = %d\n", ret);
return NULL;
}
return page_addr;
}
void gnttab_put_page(void *page_addr)
{
int ret, nr_extents = 1;
struct xen_memory_reservation reservation;
xen_pfn_t page = xen_virt_to_gfn(page_addr);
/*
* After unmapping there will be a 4Kb holes in address space
* at 'page_addr' positions. To keep it contiguous and be able
* to return such addresses to memory allocator we need to
* populate memory on unmapped positions here.
*/
memset(&reservation, 0, sizeof(reservation));
reservation.domid = DOMID_SELF;
reservation.extent_order = 0;
reservation.nr_extents = nr_extents;
set_xen_guest_handle(reservation.extent_start, &page);
ret = HYPERVISOR_memory_op(XENMEM_populate_physmap, &reservation);
if (ret != nr_extents) {
LOG_WRN("failed to populate physmap on gfn = 0x%llx, ret = %d\n",
page, ret);
return;
}
k_free(page_addr);
}
int gnttab_map_refs(struct gnttab_map_grant_ref *map_ops, unsigned int count)
{
int i, ret;
ret = HYPERVISOR_grant_table_op(GNTTABOP_map_grant_ref, map_ops, count);
if (ret) {
return ret;
}
for (i = 0; i < count; i++) {
switch (map_ops[i].status) {
case GNTST_no_device_space:
LOG_WRN("map_grant_ref failed, no device space for page #%d\n", i);
break;
case GNTST_eagain:
/* Operation not done; need to try again */
gop_eagain_retry(GNTTABOP_map_grant_ref, &map_ops[i]);
/* Need to re-check status for current page */
i--;
break;
default:
break;
}
}
return 0;
}
int gnttab_unmap_refs(struct gnttab_map_grant_ref *unmap_ops, unsigned int count)
{
return HYPERVISOR_grant_table_op(GNTTABOP_unmap_grant_ref, unmap_ops, count);
}
static const char * const gnttab_error_msgs[] = GNTTABOP_error_msgs;
const char *gnttabop_error(int16_t status)
{
status = -status;
if (status < 0 || (uint16_t) status >= ARRAY_SIZE(gnttab_error_msgs)) {
return "bad status";
} else {
return gnttab_error_msgs[status];
}
}
static int gnttab_init(void)
{
grant_ref_t gref;
struct xen_add_to_physmap xatp;
struct gnttab_setup_table setup;
xen_pfn_t frames[NR_GRANT_FRAMES];
int rc = 0, i;
/* Will be taken/given during gnt_refs allocation/release */
k_sem_init(&gnttab.sem, 0, NR_GRANT_ENTRIES - GNTTAB_NR_RESERVED_ENTRIES);
for (
gref = GNTTAB_NR_RESERVED_ENTRIES;
gref < NR_GRANT_ENTRIES;
gref++
) {
put_free_entry(gref);
}
for (i = 0; i < NR_GRANT_FRAMES; i++) {
xatp.domid = DOMID_SELF;
xatp.size = 0;
xatp.space = XENMAPSPACE_grant_table;
xatp.idx = i;
xatp.gpfn = xen_virt_to_gfn(Z_TOPLEVEL_ROM_NAME(grant_tables).phys_addr) + i;
rc = HYPERVISOR_memory_op(XENMEM_add_to_physmap, &xatp);
__ASSERT(!rc, "add_to_physmap failed; status = %d\n", rc);
}
setup.dom = DOMID_SELF;
setup.nr_frames = NR_GRANT_FRAMES;
set_xen_guest_handle(setup.frame_list, frames);
rc = HYPERVISOR_grant_table_op(GNTTABOP_setup_table, &setup, 1);
__ASSERT((!rc) && (!setup.status), "Table setup failed; status = %s\n",
gnttabop_error(setup.status));
DEVICE_MMIO_TOPLEVEL_MAP(grant_tables, K_MEM_CACHE_WB | K_MEM_PERM_RW);
gnttab.table = (grant_entry_v1_t *)DEVICE_MMIO_TOPLEVEL_GET(grant_tables);
LOG_DBG("%s: grant table mapped\n", __func__);
return 0;
}
SYS_INIT(gnttab_init, POST_KERNEL, CONFIG_KERNEL_INIT_PRIORITY_DEVICE);
``` | /content/code_sandbox/drivers/xen/gnttab.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 2,506 |
```c
/*
*
*/
#include <zephyr/arch/arm64/hypercall.h>
#include <zephyr/xen/public/xen.h>
#include <zephyr/xen/public/event_channel.h>
#include <zephyr/xen/events.h>
#include <zephyr/sys/barrier.h>
#include <errno.h>
#include <zephyr/kernel.h>
#include <zephyr/logging/log.h>
#include <zephyr/irq.h>
LOG_MODULE_REGISTER(xen_events);
extern shared_info_t *HYPERVISOR_shared_info;
static evtchn_handle_t event_channels[EVTCHN_2L_NR_CHANNELS];
static bool events_missed[EVTCHN_2L_NR_CHANNELS];
static void empty_callback(void *data)
{
/* data is the event_channels entry, subtracting the base, it's the port */
unsigned int port = (((evtchn_handle_t *)data) - event_channels);
events_missed[port] = true;
}
int alloc_unbound_event_channel(domid_t remote_dom)
{
int rc;
struct evtchn_alloc_unbound alloc = {
.dom = DOMID_SELF,
.remote_dom = remote_dom,
};
rc = HYPERVISOR_event_channel_op(EVTCHNOP_alloc_unbound, &alloc);
if (rc == 0) {
rc = alloc.port;
}
return rc;
}
#ifdef CONFIG_XEN_DOM0
int alloc_unbound_event_channel_dom0(domid_t dom, domid_t remote_dom)
{
int rc;
struct evtchn_alloc_unbound alloc = {
.dom = dom,
.remote_dom = remote_dom,
};
rc = HYPERVISOR_event_channel_op(EVTCHNOP_alloc_unbound, &alloc);
if (rc == 0) {
rc = alloc.port;
}
return rc;
}
#endif /* CONFIG_XEN_DOM0 */
int bind_interdomain_event_channel(domid_t remote_dom, evtchn_port_t remote_port,
evtchn_cb_t cb, void *data)
{
int rc;
struct evtchn_bind_interdomain bind = {
.remote_dom = remote_dom,
.remote_port = remote_port,
};
rc = HYPERVISOR_event_channel_op(EVTCHNOP_bind_interdomain, &bind);
if (rc < 0) {
return rc;
}
rc = bind_event_channel(bind.local_port, cb, data);
if (rc < 0) {
return rc;
}
return bind.local_port;
}
int evtchn_status(evtchn_status_t *status)
{
return HYPERVISOR_event_channel_op(EVTCHNOP_status, status);
}
int evtchn_close(evtchn_port_t port)
{
struct evtchn_close close = {
.port = port,
};
return HYPERVISOR_event_channel_op(EVTCHNOP_close, &close);
}
int evtchn_set_priority(evtchn_port_t port, uint32_t priority)
{
struct evtchn_set_priority set = {
.port = port,
.priority = priority,
};
return HYPERVISOR_event_channel_op(EVTCHNOP_set_priority, &set);
}
void notify_evtchn(evtchn_port_t port)
{
struct evtchn_send send;
__ASSERT(port < EVTCHN_2L_NR_CHANNELS,
"%s: trying to send notify for invalid evtchn #%u\n",
__func__, port);
send.port = port;
HYPERVISOR_event_channel_op(EVTCHNOP_send, &send);
}
int bind_event_channel(evtchn_port_t port, evtchn_cb_t cb, void *data)
{
__ASSERT(port < EVTCHN_2L_NR_CHANNELS,
"%s: trying to bind invalid evtchn #%u\n",
__func__, port);
__ASSERT(cb != NULL, "%s: NULL callback for evtchn #%u\n",
__func__, port);
if (event_channels[port].cb != empty_callback) {
LOG_WRN("%s: re-bind callback for evtchn #%u\n",
__func__, port);
}
event_channels[port].priv = data;
event_channels[port].cb = cb;
return 0;
}
int unbind_event_channel(evtchn_port_t port)
{
__ASSERT(port < EVTCHN_2L_NR_CHANNELS,
"%s: trying to unbind invalid evtchn #%u\n",
__func__, port);
event_channels[port].cb = empty_callback;
event_channels[port].priv = &event_channels[port];
events_missed[port] = false;
return 0;
}
int get_missed_events(evtchn_port_t port)
{
__ASSERT(port < EVTCHN_2L_NR_CHANNELS,
"%s: trying to get missed event from invalid port #%u\n",
__func__, port);
if (events_missed[port]) {
events_missed[port] = false;
return 1;
}
return 0;
}
int mask_event_channel(evtchn_port_t port)
{
shared_info_t *s = HYPERVISOR_shared_info;
__ASSERT(port < EVTCHN_2L_NR_CHANNELS,
"%s: trying to mask invalid evtchn #%u\n",
__func__, port);
sys_bitfield_set_bit((mem_addr_t) s->evtchn_mask, port);
return 0;
}
int unmask_event_channel(evtchn_port_t port)
{
shared_info_t *s = HYPERVISOR_shared_info;
__ASSERT(port < EVTCHN_2L_NR_CHANNELS,
"%s: trying to unmask invalid evtchn #%u\n",
__func__, port);
sys_bitfield_clear_bit((mem_addr_t) s->evtchn_mask, port);
return 0;
}
static void clear_event_channel(evtchn_port_t port)
{
shared_info_t *s = HYPERVISOR_shared_info;
sys_bitfield_clear_bit((mem_addr_t) s->evtchn_pending, port);
}
static inline xen_ulong_t get_pending_events(xen_ulong_t pos)
{
shared_info_t *s = HYPERVISOR_shared_info;
return (s->evtchn_pending[pos] & ~(s->evtchn_mask[pos]));
}
static void process_event(evtchn_port_t port)
{
evtchn_handle_t channel = event_channels[port];
clear_event_channel(port);
channel.cb(channel.priv);
}
static void events_isr(void *data)
{
ARG_UNUSED(data);
/* Needed for 2-level unwrapping */
xen_ulong_t pos_selector; /* bits are positions in pending array */
xen_ulong_t events_pending; /* bits - events in pos_selector element */
uint32_t pos_index, event_index; /* bit indexes */
evtchn_port_t port; /* absolute event index */
/* TODO: SMP? XEN_LEGACY_MAX_VCPUS == 1*/
vcpu_info_t *vcpu = &HYPERVISOR_shared_info->vcpu_info[0];
/*
* Need to set it to 0 /before/ checking for pending work, thus
* avoiding a set-and-check race (check struct vcpu_info_t)
*/
vcpu->evtchn_upcall_pending = 0;
barrier_dmem_fence_full();
/* Can not use system atomic_t/atomic_set() due to 32-bit casting */
pos_selector = __atomic_exchange_n(&vcpu->evtchn_pending_sel,
0, __ATOMIC_SEQ_CST);
while (pos_selector) {
/* Find first position, clear it in selector and process */
pos_index = __builtin_ffsl(pos_selector) - 1;
pos_selector &= ~(((xen_ulong_t) 1) << pos_index);
/* Find all active evtchn on selected position */
while ((events_pending = get_pending_events(pos_index)) != 0) {
event_index = __builtin_ffsl(events_pending) - 1;
events_pending &= (((xen_ulong_t) 1) << event_index);
port = (pos_index * 8 * sizeof(xen_ulong_t))
+ event_index;
process_event(port);
}
}
}
int xen_events_init(void)
{
int i;
if (!HYPERVISOR_shared_info) {
/* shared info was not mapped */
LOG_ERR("%s: shared_info - NULL, can't setup events\n", __func__);
return -EINVAL;
}
/* bind all ports with default callback */
for (i = 0; i < EVTCHN_2L_NR_CHANNELS; i++) {
event_channels[i].cb = empty_callback;
event_channels[i].priv = &event_channels[i];
events_missed[i] = false;
}
IRQ_CONNECT(DT_IRQ_BY_IDX(DT_INST(0, xen_xen), 0, irq),
DT_IRQ_BY_IDX(DT_INST(0, xen_xen), 0, priority), events_isr,
NULL, DT_IRQ_BY_IDX(DT_INST(0, xen_xen), 0, flags));
irq_enable(DT_IRQ_BY_IDX(DT_INST(0, xen_xen), 0, irq));
LOG_INF("%s: events inited\n", __func__);
return 0;
}
``` | /content/code_sandbox/drivers/xen/events.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 1,922 |
```c
/*
*
*/
#include <zephyr/arch/arm64/hypercall.h>
#include <zephyr/xen/dom0/domctl.h>
#include <zephyr/xen/generic.h>
#include <zephyr/xen/public/domctl.h>
#include <zephyr/xen/public/xen.h>
#include <zephyr/init.h>
#include <zephyr/kernel.h>
#include <string.h>
static int do_domctl(xen_domctl_t *domctl)
{
domctl->interface_version = XEN_DOMCTL_INTERFACE_VERSION;
return HYPERVISOR_domctl(domctl);
}
int xen_domctl_scheduler_op(int domid, struct xen_domctl_scheduler_op *sched_op)
{
xen_domctl_t domctl = {
.cmd = XEN_DOMCTL_scheduler_op,
.domain = domid,
.u.scheduler_op = *sched_op,
};
return do_domctl(&domctl);
}
int xen_domctl_pausedomain(int domid)
{
xen_domctl_t domctl = {
.cmd = XEN_DOMCTL_pausedomain,
.domain = domid,
};
return do_domctl(&domctl);
}
int xen_domctl_unpausedomain(int domid)
{
xen_domctl_t domctl = {
.cmd = XEN_DOMCTL_unpausedomain,
.domain = domid,
};
return do_domctl(&domctl);
}
int xen_domctl_resumedomain(int domid)
{
xen_domctl_t domctl = {
.cmd = XEN_DOMCTL_resumedomain,
.domain = domid,
};
return do_domctl(&domctl);
}
int xen_domctl_getvcpucontext(int domid, int vcpu, vcpu_guest_context_t *ctxt)
{
xen_domctl_t domctl = {
.cmd = XEN_DOMCTL_getvcpucontext,
.domain = domid,
.u.vcpucontext.vcpu = 0,
};
set_xen_guest_handle(domctl.u.vcpucontext.ctxt, ctxt);
return do_domctl(&domctl);
}
int xen_domctl_setvcpucontext(int domid, int vcpu, vcpu_guest_context_t *ctxt)
{
xen_domctl_t domctl = {
.cmd = XEN_DOMCTL_setvcpucontext,
.domain = domid,
.u.vcpucontext.vcpu = 0,
};
set_xen_guest_handle(domctl.u.vcpucontext.ctxt, ctxt);
return do_domctl(&domctl);
}
int xen_domctl_getdomaininfo(int domid, xen_domctl_getdomaininfo_t *dom_info)
{
int rc;
xen_domctl_t domctl = {
.cmd = XEN_DOMCTL_getdomaininfo,
.domain = domid,
};
rc = do_domctl(&domctl);
if (rc) {
return rc;
}
memcpy(dom_info, &domctl.u.getdomaininfo, sizeof(*dom_info));
return 0;
}
int xen_domctl_get_paging_mempool_size(int domid, uint64_t *size_mb)
{
int rc;
xen_domctl_t domctl = {
.cmd = XEN_DOMCTL_get_paging_mempool_size,
.domain = domid,
};
rc = do_domctl(&domctl);
if (rc) {
return rc;
}
*size_mb = domctl.u.paging_mempool.size;
return 0;
}
int xen_domctl_set_paging_mempool_size(int domid, uint64_t size_mb)
{
xen_domctl_t domctl = {
.cmd = XEN_DOMCTL_set_paging_mempool_size,
.domain = domid,
.u.paging_mempool.size = size_mb,
};
return do_domctl(&domctl);
}
int xen_domctl_max_mem(int domid, uint64_t max_memkb)
{
xen_domctl_t domctl = {
.cmd = XEN_DOMCTL_max_mem,
.domain = domid,
.u.max_mem.max_memkb = max_memkb,
};
return do_domctl(&domctl);
}
int xen_domctl_set_address_size(int domid, int addr_size)
{
xen_domctl_t domctl = {
.domain = domid,
.cmd = XEN_DOMCTL_set_address_size,
.u.address_size.size = addr_size,
};
return do_domctl(&domctl);
}
int xen_domctl_iomem_permission(int domid, uint64_t first_mfn,
uint64_t nr_mfns, uint8_t allow_access)
{
xen_domctl_t domctl = {
.domain = domid,
.cmd = XEN_DOMCTL_iomem_permission,
.u.iomem_permission.first_mfn = first_mfn,
.u.iomem_permission.nr_mfns = nr_mfns,
.u.iomem_permission.allow_access = allow_access,
};
return do_domctl(&domctl);
}
int xen_domctl_memory_mapping(int domid, uint64_t first_gfn, uint64_t first_mfn,
uint64_t nr_mfns, uint32_t add_mapping)
{
int ret;
uint64_t curr, nr_max, done;
xen_domctl_t domctl = {
.domain = domid,
.cmd = XEN_DOMCTL_memory_mapping,
.u.memory_mapping.add_mapping = add_mapping,
};
if (!nr_mfns) {
return 0;
}
/* nr_mfns can be big and we need to handle this here */
done = 0;
nr_max = nr_mfns;
do {
domctl.u.memory_mapping.first_gfn = first_gfn + done;
domctl.u.memory_mapping.first_mfn = first_mfn + done;
curr = MIN(nr_mfns - done, nr_max);
domctl.u.memory_mapping.nr_mfns = curr;
ret = do_domctl(&domctl);
if (ret < 0) {
if (ret == -E2BIG) {
/* Check if we not reach min amount */
if (nr_max <= 1) {
break;
}
/* Decrease amount twice and try again */
nr_max = nr_max >> 1;
continue;
} else {
break;
}
}
done += curr;
} while (done < nr_mfns);
/* We may come here when get E2BIG and reach 1 at nr_max */
if (!done) {
ret = -1;
}
return ret;
}
int xen_domctl_assign_dt_device(int domid, char *dtdev_path)
{
xen_domctl_t domctl = {
.domain = domid,
.cmd = XEN_DOMCTL_assign_device,
.u.assign_device.flags = 0,
.u.assign_device.dev = XEN_DOMCTL_DEV_DT,
.u.assign_device.u.dt.size = strlen(dtdev_path),
};
set_xen_guest_handle(domctl.u.assign_device.u.dt.path, dtdev_path);
return do_domctl(&domctl);
}
int xen_domctl_bind_pt_irq(int domid, uint32_t machine_irq, uint8_t irq_type,
uint8_t bus, uint8_t device, uint8_t intx, uint8_t isa_irq,
uint16_t spi)
{
xen_domctl_t domctl = {
.domain = domid,
.cmd = XEN_DOMCTL_bind_pt_irq,
};
struct xen_domctl_bind_pt_irq *bind = &(domctl.u.bind_pt_irq);
switch (irq_type) {
case PT_IRQ_TYPE_SPI:
bind->irq_type = irq_type;
bind->machine_irq = machine_irq;
bind->u.spi.spi = spi;
break;
default:
/* TODO: implement other types */
return -ENOTSUP;
}
return do_domctl(&domctl);
}
int xen_domctl_max_vcpus(int domid, int max_vcpus)
{
xen_domctl_t domctl = {
.cmd = XEN_DOMCTL_max_vcpus,
.domain = domid,
.u.max_vcpus.max = max_vcpus,
};
return do_domctl(&domctl);
}
int xen_domctl_createdomain(int domid, struct xen_domctl_createdomain *config)
{
xen_domctl_t domctl = {
.cmd = XEN_DOMCTL_createdomain,
.domain = domid,
.u.createdomain = *config,
};
return do_domctl(&domctl);
}
int xen_domctl_destroydomain(int domid)
{
xen_domctl_t domctl = {
.cmd = XEN_DOMCTL_destroydomain,
.domain = domid,
};
return do_domctl(&domctl);
}
int xen_domctl_cacheflush(int domid, struct xen_domctl_cacheflush *cacheflush)
{
xen_domctl_t domctl = {
.cmd = XEN_DOMCTL_cacheflush,
.domain = domid,
.u.cacheflush = *cacheflush,
};
return do_domctl(&domctl);
}
``` | /content/code_sandbox/drivers/xen/dom0/domctl.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 1,970 |
```c
/*
*
*/
#define DT_DRV_COMPAT nxp_lpc11u6x_eeprom
/**
* @file
* @brief EEPROM driver for NXP LPC11U6X MCUs
*
* This driver supports the on-chip EEPROM found on NXP LPC11U6x MCUs.
*
* @note This driver is only a wrapper for the IAP (In-Application Programming)
* EEPROM functions.
*/
#include <zephyr/kernel.h>
#include <zephyr/drivers/eeprom.h>
#include <iap.h>
#define LOG_LEVEL CONFIG_EEPROM_LOG_LEVEL
#include <zephyr/logging/log.h>
LOG_MODULE_REGISTER(eeprom_lpc11u6x);
struct eeprom_lpc11u6x_config {
size_t size;
};
static int eeprom_lpc11u6x_read(const struct device *dev,
off_t offset, void *data, size_t len)
{
const struct eeprom_lpc11u6x_config *config = dev->config;
uint32_t cmd[5];
int ret;
if (!len) {
return 0;
}
if ((offset + len) > config->size) {
LOG_WRN("attempt to read past device boundary");
return -EINVAL;
}
cmd[0] = IAP_CMD_EEPROM_READ;
cmd[1] = offset;
cmd[2] = (uint32_t) data;
cmd[3] = len;
cmd[4] = CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC / 1000;
ret = iap_cmd(cmd);
if (ret != IAP_STATUS_CMD_SUCCESS) {
LOG_ERR("failed to read EEPROM (offset=%08x len=%d err=%d)",
(unsigned int) offset, len, ret);
return -EINVAL;
}
return 0;
}
static int eeprom_lpc11u6x_write(const struct device *dev,
off_t offset, const void *data, size_t len)
{
const struct eeprom_lpc11u6x_config *config = dev->config;
uint32_t cmd[5];
int ret;
if (!len) {
return 0;
}
if ((offset + len) > config->size) {
LOG_WRN("attempt to write past device boundary");
return -EINVAL;
}
cmd[0] = IAP_CMD_EEPROM_WRITE;
cmd[1] = offset;
cmd[2] = (uint32_t) data;
cmd[3] = len;
cmd[4] = CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC / 1000;
ret = iap_cmd(cmd);
if (ret != IAP_STATUS_CMD_SUCCESS) {
LOG_ERR("failed to write EEPROM (offset=%08x len=%d err=%d)",
(unsigned int) offset, len, ret);
return -EINVAL;
}
return 0;
}
static size_t eeprom_lpc11u6x_size(const struct device *dev)
{
const struct eeprom_lpc11u6x_config *config = dev->config;
return config->size;
}
static const struct eeprom_driver_api eeprom_lpc11u6x_api = {
.read = eeprom_lpc11u6x_read,
.write = eeprom_lpc11u6x_write,
.size = eeprom_lpc11u6x_size,
};
static const struct eeprom_lpc11u6x_config eeprom_config = {
.size = DT_INST_PROP(0, size),
};
DEVICE_DT_INST_DEFINE(0, NULL, NULL, NULL, &eeprom_config, POST_KERNEL,
CONFIG_EEPROM_INIT_PRIORITY, &eeprom_lpc11u6x_api);
``` | /content/code_sandbox/drivers/eeprom/eeprom_lpc11u6x.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 768 |
```unknown
config EEPROM_MB85RCXX
bool "FUJITSU mb85rcxx i2c FRAM"
default y
depends on DT_HAS_FUJITSU_MB85RCXX_ENABLED
select I2C
help
Enable FUJITSU mb85rcxx i2c FRAM
``` | /content/code_sandbox/drivers/eeprom/Kconfig.mb85rcxx | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 67 |
```unknown
config EEPROM_LPC11U6X
bool "LPC11U6x EEPROM driver"
default y
depends on DT_HAS_NXP_LPC11U6X_EEPROM_ENABLED
help
Enable support for the on-chip EEPROM found on NXP LPC11U6x MCUs.
``` | /content/code_sandbox/drivers/eeprom/Kconfig.lpc11u6x | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 65 |
```unknown
config EEPROM_EMULATOR
bool "Emulated EEPROM driver"
default y
depends on DT_HAS_ZEPHYR_EMU_EEPROM_ENABLED
select FLASH
help
Enable emulated (on flash) EEPROM support. This mimics an external
EEPROM on a flash partition. The number of writes that can be
performed to the EEPROM is maximized by using a flash area that is
larger than the EEPROM area and by storing only changes to the EEPROM
data.
``` | /content/code_sandbox/drivers/eeprom/Kconfig.eeprom_emu | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 103 |
```c
/*
*
*/
/**
* @file
* @brief Driver for Atmel AT24 I2C and Atmel AT25 SPI EEPROMs.
*/
#include <zephyr/drivers/eeprom.h>
#include <zephyr/drivers/gpio.h>
#include <zephyr/drivers/i2c.h>
#include <zephyr/drivers/spi.h>
#include <zephyr/sys/byteorder.h>
#include <zephyr/kernel.h>
#define LOG_LEVEL CONFIG_EEPROM_LOG_LEVEL
#include <zephyr/logging/log.h>
LOG_MODULE_REGISTER(eeprom_at2x);
/* AT25 instruction set */
#define EEPROM_AT25_WRSR 0x01U /* Write STATUS register */
#define EEPROM_AT25_WRITE 0x02U /* Write data to memory array */
#define EEPROM_AT25_READ 0x03U /* Read data from memory array */
#define EEPROM_AT25_WRDI 0x04U /* Reset the write enable latch */
#define EEPROM_AT25_RDSR 0x05U /* Read STATUS register */
#define EEPROM_AT25_WREN 0x06U /* Set the write enable latch */
/* AT25 status register bits */
#define EEPROM_AT25_STATUS_WIP BIT(0) /* Write-In-Process (RO) */
#define EEPROM_AT25_STATUS_WEL BIT(1) /* Write Enable Latch (RO) */
#define EEPROM_AT25_STATUS_BP0 BIT(2) /* Block Protection 0 (RW) */
#define EEPROM_AT25_STATUS_BP1 BIT(3) /* Block Protection 1 (RW) */
#define HAS_WP_OR(id) DT_NODE_HAS_PROP(id, wp_gpios) ||
#define ANY_INST_HAS_WP_GPIOS (DT_FOREACH_STATUS_OKAY(atmel_at24, HAS_WP_OR) \
DT_FOREACH_STATUS_OKAY(atmel_at25, HAS_WP_OR) 0)
struct eeprom_at2x_config {
union {
#ifdef CONFIG_EEPROM_AT24
struct i2c_dt_spec i2c;
#endif /* CONFIG_EEPROM_AT24 */
#ifdef CONFIG_EEPROM_AT25
struct spi_dt_spec spi;
#endif /* CONFIG_EEPROM_AT25 */
} bus;
#if ANY_INST_HAS_WP_GPIOS
struct gpio_dt_spec wp_gpio;
#endif /* ANY_INST_HAS_WP_GPIOS */
size_t size;
size_t pagesize;
uint8_t addr_width;
bool readonly;
uint16_t timeout;
bool (*bus_is_ready)(const struct device *dev);
eeprom_api_read read_fn;
eeprom_api_write write_fn;
};
struct eeprom_at2x_data {
struct k_mutex lock;
};
#if ANY_INST_HAS_WP_GPIOS
static inline int eeprom_at2x_write_protect(const struct device *dev)
{
const struct eeprom_at2x_config *config = dev->config;
if (!config->wp_gpio.port) {
return 0;
}
return gpio_pin_set_dt(&config->wp_gpio, 1);
}
static inline int eeprom_at2x_write_enable(const struct device *dev)
{
const struct eeprom_at2x_config *config = dev->config;
if (!config->wp_gpio.port) {
return 0;
}
return gpio_pin_set_dt(&config->wp_gpio, 0);
}
#endif /* ANY_INST_HAS_WP_GPIOS */
static int eeprom_at2x_read(const struct device *dev, off_t offset, void *buf,
size_t len)
{
const struct eeprom_at2x_config *config = dev->config;
struct eeprom_at2x_data *data = dev->data;
uint8_t *pbuf = buf;
int ret;
if (!len) {
return 0;
}
if ((offset + len) > config->size) {
LOG_WRN("attempt to read past device boundary");
return -EINVAL;
}
k_mutex_lock(&data->lock, K_FOREVER);
while (len) {
ret = config->read_fn(dev, offset, pbuf, len);
if (ret < 0) {
LOG_ERR("failed to read EEPROM (err %d)", ret);
k_mutex_unlock(&data->lock);
return ret;
}
pbuf += ret;
offset += ret;
len -= ret;
}
k_mutex_unlock(&data->lock);
return 0;
}
static size_t eeprom_at2x_limit_write_count(const struct device *dev,
off_t offset,
size_t len)
{
const struct eeprom_at2x_config *config = dev->config;
size_t count = len;
off_t page_boundary;
/* We can at most write one page at a time */
if (count > config->pagesize) {
count = config->pagesize;
}
/* Writes can not cross a page boundary */
page_boundary = ROUND_UP(offset + 1, config->pagesize);
if (offset + count > page_boundary) {
count = page_boundary - offset;
}
return count;
}
static int eeprom_at2x_write(const struct device *dev, off_t offset,
const void *buf,
size_t len)
{
const struct eeprom_at2x_config *config = dev->config;
struct eeprom_at2x_data *data = dev->data;
const uint8_t *pbuf = buf;
int ret;
if (config->readonly) {
LOG_WRN("attempt to write to read-only device");
return -EACCES;
}
if (!len) {
return 0;
}
if ((offset + len) > config->size) {
LOG_WRN("attempt to write past device boundary");
return -EINVAL;
}
k_mutex_lock(&data->lock, K_FOREVER);
#if ANY_INST_HAS_WP_GPIOS
ret = eeprom_at2x_write_enable(dev);
if (ret) {
LOG_ERR("failed to write-enable EEPROM (err %d)", ret);
k_mutex_unlock(&data->lock);
return ret;
}
#endif /* ANY_INST_HAS_WP_GPIOS */
while (len) {
ret = config->write_fn(dev, offset, pbuf, len);
if (ret < 0) {
LOG_ERR("failed to write to EEPROM (err %d)", ret);
#if ANY_INST_HAS_WP_GPIOS
eeprom_at2x_write_protect(dev);
#endif /* ANY_INST_HAS_WP_GPIOS */
k_mutex_unlock(&data->lock);
return ret;
}
pbuf += ret;
offset += ret;
len -= ret;
}
#if ANY_INST_HAS_WP_GPIOS
ret = eeprom_at2x_write_protect(dev);
if (ret) {
LOG_ERR("failed to write-protect EEPROM (err %d)", ret);
}
#else
ret = 0;
#endif /* ANY_INST_HAS_WP_GPIOS */
k_mutex_unlock(&data->lock);
return ret;
}
static size_t eeprom_at2x_size(const struct device *dev)
{
const struct eeprom_at2x_config *config = dev->config;
return config->size;
}
#ifdef CONFIG_EEPROM_AT24
static bool eeprom_at24_bus_is_ready(const struct device *dev)
{
const struct eeprom_at2x_config *config = dev->config;
return device_is_ready(config->bus.i2c.bus);
}
/**
* @brief translate an offset to a device address / offset pair
*
* It allows to address several devices as a continuous memory region
* but also to address higher part of eeprom for chips
* with more than 2^(addr_width) adressable word.
*/
static uint16_t eeprom_at24_translate_offset(const struct device *dev,
off_t *offset)
{
const struct eeprom_at2x_config *config = dev->config;
const uint16_t addr_incr = *offset >> config->addr_width;
*offset &= BIT_MASK(config->addr_width);
return config->bus.i2c.addr + addr_incr;
}
static size_t eeprom_at24_adjust_read_count(const struct device *dev,
off_t offset, size_t len)
{
const struct eeprom_at2x_config *config = dev->config;
const size_t remainder = BIT(config->addr_width) - offset;
if (len > remainder) {
len = remainder;
}
return len;
}
static int eeprom_at24_read(const struct device *dev, off_t offset, void *buf,
size_t len)
{
const struct eeprom_at2x_config *config = dev->config;
int64_t timeout;
uint8_t addr[2];
uint16_t bus_addr;
int err;
bus_addr = eeprom_at24_translate_offset(dev, &offset);
if (config->addr_width == 16) {
sys_put_be16(offset, addr);
} else {
addr[0] = offset & BIT_MASK(8);
}
len = eeprom_at24_adjust_read_count(dev, offset, len);
/*
* A write cycle may be in progress so reads must be attempted
* until the current write cycle should be completed.
*/
timeout = k_uptime_get() + config->timeout;
while (1) {
int64_t now = k_uptime_get();
err = i2c_write_read(config->bus.i2c.bus, bus_addr,
addr, config->addr_width / 8,
buf, len);
if (!err || now > timeout) {
break;
}
k_sleep(K_MSEC(1));
}
if (err < 0) {
return err;
}
return len;
}
static int eeprom_at24_write(const struct device *dev, off_t offset,
const void *buf, size_t len)
{
const struct eeprom_at2x_config *config = dev->config;
int count = eeprom_at2x_limit_write_count(dev, offset, len);
uint8_t block[config->addr_width / 8 + count];
int64_t timeout;
uint16_t bus_addr;
int i = 0;
int err;
bus_addr = eeprom_at24_translate_offset(dev, &offset);
/*
* Not all I2C EEPROMs support repeated start so the
* address (offset) and data (buf) must be provided in one
* write transaction (block).
*/
if (config->addr_width == 16) {
block[i++] = offset >> 8;
}
block[i++] = offset;
memcpy(&block[i], buf, count);
/*
* A write cycle may already be in progress so writes must be
* attempted until the previous write cycle should be
* completed.
*/
timeout = k_uptime_get() + config->timeout;
while (1) {
int64_t now = k_uptime_get();
err = i2c_write(config->bus.i2c.bus, block, sizeof(block),
bus_addr);
if (!err || now > timeout) {
break;
}
k_sleep(K_MSEC(1));
}
if (err < 0) {
return err;
}
return count;
}
#endif /* CONFIG_EEPROM_AT24 */
#ifdef CONFIG_EEPROM_AT25
static bool eeprom_at25_bus_is_ready(const struct device *dev)
{
const struct eeprom_at2x_config *config = dev->config;
return spi_is_ready_dt(&config->bus.spi);
}
static int eeprom_at25_rdsr(const struct device *dev, uint8_t *status)
{
const struct eeprom_at2x_config *config = dev->config;
uint8_t rdsr[2] = { EEPROM_AT25_RDSR, 0 };
uint8_t sr[2];
int err;
const struct spi_buf tx_buf = {
.buf = rdsr,
.len = sizeof(rdsr),
};
const struct spi_buf_set tx = {
.buffers = &tx_buf,
.count = 1,
};
const struct spi_buf rx_buf = {
.buf = sr,
.len = sizeof(sr),
};
const struct spi_buf_set rx = {
.buffers = &rx_buf,
.count = 1,
};
err = spi_transceive_dt(&config->bus.spi, &tx, &rx);
if (!err) {
*status = sr[1];
}
return err;
}
static int eeprom_at25_wait_for_idle(const struct device *dev)
{
const struct eeprom_at2x_config *config = dev->config;
int64_t timeout;
uint8_t status;
int err;
timeout = k_uptime_get() + config->timeout;
while (1) {
int64_t now = k_uptime_get();
err = eeprom_at25_rdsr(dev, &status);
if (err) {
LOG_ERR("Could not read status register (err %d)", err);
return err;
}
if (!(status & EEPROM_AT25_STATUS_WIP)) {
return 0;
}
if (now > timeout) {
break;
}
k_sleep(K_MSEC(1));
}
return -EBUSY;
}
static int eeprom_at25_read(const struct device *dev, off_t offset, void *buf,
size_t len)
{
const struct eeprom_at2x_config *config = dev->config;
struct eeprom_at2x_data *data = dev->data;
size_t cmd_len = 1 + config->addr_width / 8;
uint8_t cmd[4] = { EEPROM_AT25_READ, 0, 0, 0 };
uint8_t *paddr;
int err;
const struct spi_buf tx_buf = {
.buf = cmd,
.len = cmd_len,
};
const struct spi_buf_set tx = {
.buffers = &tx_buf,
.count = 1,
};
const struct spi_buf rx_bufs[2] = {
{
.buf = NULL,
.len = cmd_len,
},
{
.buf = buf,
.len = len,
},
};
const struct spi_buf_set rx = {
.buffers = rx_bufs,
.count = ARRAY_SIZE(rx_bufs),
};
if (!len) {
return 0;
}
if ((offset + len) > config->size) {
LOG_WRN("attempt to read past device boundary");
return -EINVAL;
}
paddr = &cmd[1];
switch (config->addr_width) {
case 24:
*paddr++ = offset >> 16;
__fallthrough;
case 16:
*paddr++ = offset >> 8;
__fallthrough;
case 8:
*paddr++ = offset;
break;
default:
__ASSERT(0, "invalid address width");
}
err = eeprom_at25_wait_for_idle(dev);
if (err) {
LOG_ERR("EEPROM idle wait failed (err %d)", err);
k_mutex_unlock(&data->lock);
return err;
}
err = spi_transceive_dt(&config->bus.spi, &tx, &rx);
if (err < 0) {
return err;
}
return len;
}
static int eeprom_at25_wren(const struct device *dev)
{
const struct eeprom_at2x_config *config = dev->config;
uint8_t cmd = EEPROM_AT25_WREN;
const struct spi_buf tx_buf = {
.buf = &cmd,
.len = 1,
};
const struct spi_buf_set tx = {
.buffers = &tx_buf,
.count = 1,
};
return spi_write_dt(&config->bus.spi, &tx);
}
static int eeprom_at25_write(const struct device *dev, off_t offset,
const void *buf, size_t len)
{
const struct eeprom_at2x_config *config = dev->config;
int count = eeprom_at2x_limit_write_count(dev, offset, len);
uint8_t cmd[4] = { EEPROM_AT25_WRITE, 0, 0, 0 };
size_t cmd_len = 1 + config->addr_width / 8;
uint8_t *paddr;
int err;
const struct spi_buf tx_bufs[2] = {
{
.buf = cmd,
.len = cmd_len,
},
{
.buf = (void *)buf,
.len = count,
},
};
const struct spi_buf_set tx = {
.buffers = tx_bufs,
.count = ARRAY_SIZE(tx_bufs),
};
paddr = &cmd[1];
switch (config->addr_width) {
case 24:
*paddr++ = offset >> 16;
__fallthrough;
case 16:
*paddr++ = offset >> 8;
__fallthrough;
case 8:
*paddr++ = offset;
break;
default:
__ASSERT(0, "invalid address width");
}
err = eeprom_at25_wait_for_idle(dev);
if (err) {
LOG_ERR("EEPROM idle wait failed (err %d)", err);
return err;
}
err = eeprom_at25_wren(dev);
if (err) {
LOG_ERR("failed to disable write protection (err %d)", err);
return err;
}
err = spi_transceive_dt(&config->bus.spi, &tx, NULL);
if (err) {
return err;
}
return count;
}
#endif /* CONFIG_EEPROM_AT25 */
static int eeprom_at2x_init(const struct device *dev)
{
const struct eeprom_at2x_config *config = dev->config;
struct eeprom_at2x_data *data = dev->data;
k_mutex_init(&data->lock);
if (!config->bus_is_ready(dev)) {
LOG_ERR("parent bus device not ready");
return -EINVAL;
}
#if ANY_INST_HAS_WP_GPIOS
if (config->wp_gpio.port) {
int err;
if (!gpio_is_ready_dt(&config->wp_gpio)) {
LOG_ERR("wp gpio device not ready");
return -EINVAL;
}
err = gpio_pin_configure_dt(&config->wp_gpio, GPIO_OUTPUT_ACTIVE);
if (err) {
LOG_ERR("failed to configure WP GPIO pin (err %d)", err);
return err;
}
}
#endif /* ANY_INST_HAS_WP_GPIOS */
return 0;
}
static const struct eeprom_driver_api eeprom_at2x_api = {
.read = eeprom_at2x_read,
.write = eeprom_at2x_write,
.size = eeprom_at2x_size,
};
#define ASSERT_AT24_ADDR_W_VALID(w) \
BUILD_ASSERT(w == 8U || w == 16U, \
"Unsupported address width")
#define ASSERT_AT25_ADDR_W_VALID(w) \
BUILD_ASSERT(w == 8U || w == 16U || w == 24U, \
"Unsupported address width")
#define ASSERT_PAGESIZE_IS_POWER_OF_2(page) \
BUILD_ASSERT((page != 0U) && ((page & (page - 1)) == 0U), \
"Page size is not a power of two")
#define ASSERT_SIZE_PAGESIZE_VALID(size, page) \
BUILD_ASSERT(size % page == 0U, \
"Size is not an integer multiple of page size")
#define INST_DT_AT2X(inst, t) DT_INST(inst, atmel_at##t)
#define EEPROM_AT24_BUS(n, t) \
{ .i2c = I2C_DT_SPEC_GET(INST_DT_AT2X(n, t)) }
#define EEPROM_AT25_BUS(n, t) \
{ .spi = SPI_DT_SPEC_GET(INST_DT_AT2X(n, t), \
SPI_OP_MODE_MASTER | SPI_TRANSFER_MSB | \
SPI_WORD_SET(8), 0) }
#define EEPROM_AT2X_WP_GPIOS(id) \
IF_ENABLED(DT_NODE_HAS_PROP(id, wp_gpios), \
(.wp_gpio = GPIO_DT_SPEC_GET(id, wp_gpios),))
#define EEPROM_AT2X_DEVICE(n, t) \
ASSERT_PAGESIZE_IS_POWER_OF_2(DT_PROP(INST_DT_AT2X(n, t), pagesize)); \
ASSERT_SIZE_PAGESIZE_VALID(DT_PROP(INST_DT_AT2X(n, t), size), \
DT_PROP(INST_DT_AT2X(n, t), pagesize)); \
ASSERT_AT##t##_ADDR_W_VALID(DT_PROP(INST_DT_AT2X(n, t), \
address_width)); \
static const struct eeprom_at2x_config eeprom_at##t##_config_##n = { \
.bus = EEPROM_AT##t##_BUS(n, t), \
EEPROM_AT2X_WP_GPIOS(INST_DT_AT2X(n, t)) \
.size = DT_PROP(INST_DT_AT2X(n, t), size), \
.pagesize = DT_PROP(INST_DT_AT2X(n, t), pagesize), \
.addr_width = DT_PROP(INST_DT_AT2X(n, t), address_width), \
.readonly = DT_PROP(INST_DT_AT2X(n, t), read_only), \
.timeout = DT_PROP(INST_DT_AT2X(n, t), timeout), \
.bus_is_ready = eeprom_at##t##_bus_is_ready, \
.read_fn = eeprom_at##t##_read, \
.write_fn = eeprom_at##t##_write, \
}; \
static struct eeprom_at2x_data eeprom_at##t##_data_##n; \
DEVICE_DT_DEFINE(INST_DT_AT2X(n, t), &eeprom_at2x_init, \
NULL, &eeprom_at##t##_data_##n, \
&eeprom_at##t##_config_##n, POST_KERNEL, \
CONFIG_EEPROM_AT2X_INIT_PRIORITY, \
&eeprom_at2x_api)
#define EEPROM_AT24_DEVICE(n) EEPROM_AT2X_DEVICE(n, 24)
#define EEPROM_AT25_DEVICE(n) EEPROM_AT2X_DEVICE(n, 25)
#define CALL_WITH_ARG(arg, expr) expr(arg);
#define INST_DT_AT2X_FOREACH(t, inst_expr) \
LISTIFY(DT_NUM_INST_STATUS_OKAY(atmel_at##t), \
CALL_WITH_ARG, (), inst_expr)
#ifdef CONFIG_EEPROM_AT24
INST_DT_AT2X_FOREACH(24, EEPROM_AT24_DEVICE);
#endif
#ifdef CONFIG_EEPROM_AT25
INST_DT_AT2X_FOREACH(25, EEPROM_AT25_DEVICE);
#endif
``` | /content/code_sandbox/drivers/eeprom/eeprom_at2x.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 4,805 |
```unknown
config EEPROM_STM32
bool "STM32 EEPROM driver"
default y
depends on DT_HAS_ST_STM32_EEPROM_ENABLED
select USE_STM32_HAL_FLASH
select USE_STM32_HAL_FLASH_EX
help
Enable EEPROM support on the STM32 L0, L1 family of processors.
``` | /content/code_sandbox/drivers/eeprom/Kconfig.stm32 | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 67 |
```c
/*
*
*/
#include <zephyr/device.h>
#include <zephyr/drivers/eeprom.h>
#include <zephyr/drivers/eeprom/eeprom_fake.h>
#include <zephyr/fff.h>
#ifdef CONFIG_ZTEST
#include <zephyr/ztest.h>
#endif /* CONFIG_ZTEST */
#define DT_DRV_COMPAT zephyr_fake_eeprom
struct fake_eeprom_config {
size_t size;
};
DEFINE_FAKE_VALUE_FUNC(int, fake_eeprom_read, const struct device *, off_t, void *, size_t);
DEFINE_FAKE_VALUE_FUNC(int, fake_eeprom_write, const struct device *, off_t, const void *, size_t);
DEFINE_FAKE_VALUE_FUNC(size_t, fake_eeprom_size, const struct device *);
size_t fake_eeprom_size_delegate(const struct device *dev)
{
const struct fake_eeprom_config *config = dev->config;
return config->size;
}
#ifdef CONFIG_ZTEST
static void fake_eeprom_reset_rule_before(const struct ztest_unit_test *test, void *fixture)
{
ARG_UNUSED(test);
ARG_UNUSED(fixture);
RESET_FAKE(fake_eeprom_read);
RESET_FAKE(fake_eeprom_write);
RESET_FAKE(fake_eeprom_size);
/* Re-install default delegate for reporting the EEPROM size */
fake_eeprom_size_fake.custom_fake = fake_eeprom_size_delegate;
}
ZTEST_RULE(fake_eeprom_reset_rule, fake_eeprom_reset_rule_before, NULL);
#endif /* CONFIG_ZTEST */
static const struct eeprom_driver_api fake_eeprom_driver_api = {
.read = fake_eeprom_read,
.write = fake_eeprom_write,
.size = fake_eeprom_size,
};
static int fake_eeprom_init(const struct device *dev)
{
ARG_UNUSED(dev);
/* Install default delegate for reporting the EEPROM size */
fake_eeprom_size_fake.custom_fake = fake_eeprom_size_delegate;
return 0;
}
#define FAKE_EEPROM_INIT(inst) \
static const struct fake_eeprom_config fake_eeprom_config_##inst = { \
.size = DT_INST_PROP(inst, size), \
}; \
\
DEVICE_DT_INST_DEFINE(inst, &fake_eeprom_init, NULL, NULL, \
&fake_eeprom_config_##inst, \
POST_KERNEL, CONFIG_EEPROM_INIT_PRIORITY, \
&fake_eeprom_driver_api);
DT_INST_FOREACH_STATUS_OKAY(FAKE_EEPROM_INIT)
``` | /content/code_sandbox/drivers/eeprom/eeprom_fake.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 505 |
```c
/*
*
*/
#define DT_DRV_COMPAT fujitsu_mb85rcxx
#include <zephyr/device.h>
#include <zephyr/drivers/eeprom.h>
#include <zephyr/drivers/gpio.h>
#include <zephyr/drivers/i2c.h>
#include <zephyr/kernel.h>
#include <zephyr/sys/byteorder.h>
#include <zephyr/logging/log.h>
LOG_MODULE_REGISTER(EEPROM_MB85RCXX, CONFIG_EEPROM_LOG_LEVEL);
struct mb85rcxx_config {
struct i2c_dt_spec i2c;
struct gpio_dt_spec wp_gpio;
size_t size;
size_t pagesize;
uint8_t addr_width;
bool readonly;
};
struct mb85rcxx_data {
struct k_mutex lock;
};
static int mb85rcxx_write_protect_set(const struct device *dev, int value)
{
const struct mb85rcxx_config *cfg = dev->config;
if (!cfg->wp_gpio.port) {
return 0;
}
return gpio_pin_set_dt(&cfg->wp_gpio, value);
}
static uint16_t mb85rcxx_translate_address(const struct device *dev, off_t offset, uint8_t *addr)
{
const struct mb85rcxx_config *cfg = dev->config;
off_t page_offset = offset % cfg->pagesize;
if (cfg->addr_width > 8) {
sys_put_be16(page_offset, addr);
addr[0] &= BIT_MASK(cfg->addr_width - 8);
} else {
addr[0] = page_offset & BIT_MASK(cfg->addr_width);
}
return cfg->i2c.addr + (offset >> cfg->addr_width);
}
static size_t mb85rcxx_remaining_len_in_page(const struct device *dev, off_t offset, size_t len)
{
const struct mb85rcxx_config *cfg = dev->config;
off_t page_offset = offset % cfg->pagesize;
size_t rem = cfg->pagesize - page_offset;
if (rem > len) {
rem = len;
}
return rem;
}
static int mb85rcxx_init(const struct device *dev)
{
const struct mb85rcxx_config *cfg = dev->config;
struct mb85rcxx_data *data = dev->data;
k_mutex_init(&data->lock);
if (!i2c_is_ready_dt(&cfg->i2c)) {
LOG_ERR("i2c bus device not ready");
return -EINVAL;
}
if (cfg->wp_gpio.port) {
if (!gpio_is_ready_dt(&cfg->wp_gpio)) {
LOG_ERR("wp gpio device not ready");
return -EINVAL;
}
int err = gpio_pin_configure_dt(&cfg->wp_gpio, GPIO_OUTPUT_ACTIVE);
if (err) {
LOG_ERR("failed to configure WP GPIO pin (err %d)", err);
return err;
}
}
return 0;
}
static int mb85rcxx_read(const struct device *dev, off_t offset, void *buf, size_t len)
{
const struct mb85rcxx_config *cfg = dev->config;
struct mb85rcxx_data *data = dev->data;
uint8_t addr[2];
uint16_t i2c_addr;
size_t len_in_page;
int ret;
if (offset + len > cfg->size) {
LOG_ERR("attempt to read past device boundary");
return -EINVAL;
}
k_mutex_lock(&data->lock, K_FOREVER);
while (len) {
i2c_addr = mb85rcxx_translate_address(dev, offset, addr);
len_in_page = mb85rcxx_remaining_len_in_page(dev, offset, len);
ret = i2c_write_read(cfg->i2c.bus, i2c_addr, addr, DIV_ROUND_UP(cfg->addr_width, 8),
buf, len_in_page);
if (ret < 0) {
LOG_ERR("failed to read FRAM (err %d)", ret);
k_mutex_unlock(&data->lock);
return ret;
}
len -= len_in_page;
*(char *)&buf += len_in_page;
offset += len_in_page;
}
k_mutex_unlock(&data->lock);
return 0;
}
static int mb85rcxx_i2c_write(const struct device *dev, uint16_t i2c_addr, uint8_t *addr,
const void *buf, size_t len)
{
const struct mb85rcxx_config *cfg = dev->config;
struct i2c_msg msgs[2];
msgs[0].buf = addr;
msgs[0].len = DIV_ROUND_UP(cfg->addr_width, 8);
msgs[0].flags = I2C_MSG_WRITE;
msgs[1].buf = (void *)buf;
msgs[1].len = len;
msgs[1].flags = I2C_MSG_WRITE | I2C_MSG_STOP;
return i2c_transfer(cfg->i2c.bus, &msgs[0], 2, i2c_addr);
}
static int mb85rcxx_write(const struct device *dev, off_t offset, const void *buf, size_t len)
{
const struct mb85rcxx_config *cfg = dev->config;
struct mb85rcxx_data *data = dev->data;
uint8_t addr[2];
uint16_t i2c_addr;
size_t len_in_page;
int ret;
if (cfg->readonly) {
LOG_ERR("attempt to write to read-only device");
return -EACCES;
}
if (offset + len > cfg->size) {
LOG_ERR("attempt to write past device boundary");
return -EINVAL;
}
ret = mb85rcxx_write_protect_set(dev, 0);
if (ret) {
LOG_ERR("failed to write-enable FRAM (err %d)", ret);
return ret;
}
k_mutex_lock(&data->lock, K_FOREVER);
while (len) {
i2c_addr = mb85rcxx_translate_address(dev, offset, addr);
len_in_page = mb85rcxx_remaining_len_in_page(dev, offset, len);
ret = mb85rcxx_i2c_write(dev, i2c_addr, addr, buf, len);
if (ret < 0) {
LOG_ERR("failed to write to FRAM (err %d)", ret);
k_mutex_unlock(&data->lock);
return ret;
}
len -= len_in_page;
*(char *)&buf += len_in_page;
offset += len_in_page;
}
k_mutex_unlock(&data->lock);
mb85rcxx_write_protect_set(dev, 1);
return ret;
}
static size_t mb85rcxx_get_size(const struct device *dev)
{
const struct mb85rcxx_config *cfg = dev->config;
return cfg->size;
}
static const struct eeprom_driver_api mb85rcxx_driver_api = {
.read = &mb85rcxx_read,
.write = &mb85rcxx_write,
.size = &mb85rcxx_get_size,
};
#define MB85RCXX_DEFINE(inst) \
static struct mb85rcxx_data mb85rcxx_data_##inst; \
\
static const struct mb85rcxx_config mb85rcxx_config_##inst = { \
.i2c = I2C_DT_SPEC_INST_GET(inst), \
IF_ENABLED(DT_INST_NODE_HAS_PROP(inst, wp_gpios), \
(.wp_gpio = GPIO_DT_SPEC_INST_GET(inst, wp_gpios),)) \
.size = DT_INST_PROP(inst, size), \
.pagesize = \
COND_CODE_1(DT_INST_NODE_HAS_PROP(inst, pagesize), \
(DT_INST_PROP(inst, pagesize)), (DT_INST_PROP(inst, size))), \
.addr_width = DT_INST_PROP(inst, address_width), \
.readonly = DT_INST_PROP(inst, read_only)}; \
\
DEVICE_DT_INST_DEFINE(inst, mb85rcxx_init, NULL, &mb85rcxx_data_##inst, \
&mb85rcxx_config_##inst, POST_KERNEL, CONFIG_EEPROM_INIT_PRIORITY, \
&mb85rcxx_driver_api);
DT_INST_FOREACH_STATUS_OKAY(MB85RCXX_DEFINE)
``` | /content/code_sandbox/drivers/eeprom/eeprom_mb85rcxx.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 1,760 |
```c
/*
*
*/
#include <errno.h>
#include <zephyr/devicetree.h>
#include <zephyr/drivers/eeprom.h>
#include <zephyr/drivers/sensor/tmp116.h>
#define DT_DRV_COMPAT ti_tmp116_eeprom
struct eeprom_tmp116_config {
const struct device *parent;
};
BUILD_ASSERT(CONFIG_EEPROM_INIT_PRIORITY >
CONFIG_SENSOR_INIT_PRIORITY,
"TMP116 eeprom driver must be initialized after TMP116 sensor "
"driver");
static size_t eeprom_tmp116_size(const struct device *dev)
{
return EEPROM_TMP116_SIZE;
}
static int eeprom_tmp116_write(const struct device *dev, off_t offset,
const void *data, size_t len)
{
const struct eeprom_tmp116_config *config = dev->config;
return tmp116_eeprom_write(config->parent, offset, data, len);
}
static int eeprom_tmp116_read(const struct device *dev, off_t offset, void *data,
size_t len)
{
const struct eeprom_tmp116_config *config = dev->config;
return tmp116_eeprom_read(config->parent, offset, data, len);
}
static int eeprom_tmp116_init(const struct device *dev)
{
const struct eeprom_tmp116_config *config = dev->config;
if (!device_is_ready(config->parent)) {
return -ENODEV;
}
return 0;
}
static const struct eeprom_driver_api eeprom_tmp116_api = {
.read = eeprom_tmp116_read,
.write = eeprom_tmp116_write,
.size = eeprom_tmp116_size,
};
#define DEFINE_TMP116(_num) \
static const struct eeprom_tmp116_config eeprom_tmp116_config##_num = { \
.parent = DEVICE_DT_GET(DT_INST_BUS(_num)) \
}; \
DEVICE_DT_INST_DEFINE(_num, eeprom_tmp116_init, NULL, \
NULL, &eeprom_tmp116_config##_num, POST_KERNEL, \
CONFIG_EEPROM_INIT_PRIORITY, &eeprom_tmp116_api);
DT_INST_FOREACH_STATUS_OKAY(DEFINE_TMP116);
``` | /content/code_sandbox/drivers/eeprom/eeprom_tmp116.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 441 |
```c
/*
*
*/
#include <zephyr/internal/syscall_handler.h>
#include <zephyr/drivers/eeprom.h>
static inline int z_vrfy_eeprom_read(const struct device *dev, off_t offset,
void *data, size_t len)
{
K_OOPS(K_SYSCALL_DRIVER_EEPROM(dev, read));
K_OOPS(K_SYSCALL_MEMORY_WRITE(data, len));
return z_impl_eeprom_read((const struct device *)dev, offset,
(void *)data,
len);
}
#include <zephyr/syscalls/eeprom_read_mrsh.c>
static inline int z_vrfy_eeprom_write(const struct device *dev, off_t offset,
const void *data, size_t len)
{
K_OOPS(K_SYSCALL_DRIVER_EEPROM(dev, write));
K_OOPS(K_SYSCALL_MEMORY_READ(data, len));
return z_impl_eeprom_write((const struct device *)dev, offset,
(const void *)data, len);
}
#include <zephyr/syscalls/eeprom_write_mrsh.c>
static inline size_t z_vrfy_eeprom_get_size(const struct device *dev)
{
K_OOPS(K_SYSCALL_DRIVER_EEPROM(dev, size));
return z_impl_eeprom_get_size((const struct device *)dev);
}
#include <zephyr/syscalls/eeprom_get_size_mrsh.c>
``` | /content/code_sandbox/drivers/eeprom/eeprom_handlers.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 276 |
```unknown
# Microchip XEC EEPROM
config EEPROM_XEC
bool "MCHP XEC EEPROM driver"
default y
depends on DT_HAS_MICROCHIP_XEC_EEPROM_ENABLED
select PINCTRL
help
Enable support for Microchip XEC EEPROM driver.
``` | /content/code_sandbox/drivers/eeprom/Kconfig.xec | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 57 |
```c
/*
*
*/
#define DT_DRV_COMPAT st_stm32_eeprom
#include <zephyr/drivers/eeprom.h>
#include <soc.h>
#include <zephyr/kernel.h>
#define LOG_LEVEL CONFIG_EEPROM_LOG_LEVEL
#include <zephyr/logging/log.h>
LOG_MODULE_REGISTER(eeprom_stm32);
K_MUTEX_DEFINE(lock);
struct eeprom_stm32_config {
uint32_t addr;
size_t size;
};
static int eeprom_stm32_read(const struct device *dev, off_t offset,
void *buf,
size_t len)
{
const struct eeprom_stm32_config *config = dev->config;
uint8_t *pbuf = buf;
if (!len) {
return 0;
}
if ((offset + len) > config->size) {
LOG_WRN("attempt to read past device boundary");
return -EINVAL;
}
k_mutex_lock(&lock, K_FOREVER);
while (len) {
*pbuf = *(__IO uint8_t*)(config->addr + offset);
pbuf++;
offset++;
len--;
}
k_mutex_unlock(&lock);
return 0;
}
static int eeprom_stm32_write(const struct device *dev, off_t offset,
const void *buf, size_t len)
{
const struct eeprom_stm32_config *config = dev->config;
const uint8_t *pbuf = buf;
HAL_StatusTypeDef ret = HAL_OK;
if (!len) {
return 0;
}
if ((offset + len) > config->size) {
LOG_WRN("attempt to write past device boundary");
return -EINVAL;
}
k_mutex_lock(&lock, K_FOREVER);
HAL_FLASHEx_DATAEEPROM_Unlock();
while (len) {
ret = HAL_FLASHEx_DATAEEPROM_Program(
FLASH_TYPEPROGRAMDATA_BYTE,
config->addr + offset, *pbuf);
if (ret) {
LOG_ERR("failed to write to EEPROM (err %d)", ret);
HAL_FLASHEx_DATAEEPROM_Lock();
k_mutex_unlock(&lock);
return ret;
}
pbuf++;
offset++;
len--;
}
ret = HAL_FLASHEx_DATAEEPROM_Lock();
if (ret) {
LOG_ERR("failed to lock EEPROM (err %d)", ret);
k_mutex_unlock(&lock);
return ret;
}
k_mutex_unlock(&lock);
return ret;
}
static size_t eeprom_stm32_size(const struct device *dev)
{
const struct eeprom_stm32_config *config = dev->config;
return config->size;
}
static const struct eeprom_driver_api eeprom_stm32_api = {
.read = eeprom_stm32_read,
.write = eeprom_stm32_write,
.size = eeprom_stm32_size,
};
static const struct eeprom_stm32_config eeprom_config = {
.addr = DT_INST_REG_ADDR(0),
.size = DT_INST_REG_SIZE(0),
};
DEVICE_DT_INST_DEFINE(0, NULL, NULL, NULL, &eeprom_config, POST_KERNEL,
CONFIG_EEPROM_INIT_PRIORITY, &eeprom_stm32_api);
``` | /content/code_sandbox/drivers/eeprom/eeprom_stm32.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 666 |
```unknown
config EEPROM_TMP116
bool "TMP116 EEPROM driver"
default y
depends on DT_HAS_TI_TMP116_EEPROM_ENABLED
depends on TMP116
help
Enable support for the on-chip EEPROM found on
Texas instrument TMP116 temperature sensor
``` | /content/code_sandbox/drivers/eeprom/Kconfig.tmp116 | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 57 |
```c
/*
*
*/
/**
* @file
* @brief EEPROM shell commands.
*/
#include <zephyr/shell/shell.h>
#include <zephyr/drivers/eeprom.h>
#include <stdlib.h>
struct args_index {
uint8_t device;
uint8_t offset;
uint8_t length;
uint8_t data;
uint8_t pattern;
};
static const struct args_index args_indx = {
.device = 1,
.offset = 2,
.length = 3,
.data = 3,
.pattern = 4,
};
static int cmd_read(const struct shell *sh, size_t argc, char **argv)
{
const struct device *eeprom;
size_t addr;
size_t len;
size_t pending;
size_t upto;
int err;
addr = strtoul(argv[args_indx.offset], NULL, 0);
len = strtoul(argv[args_indx.length], NULL, 0);
eeprom = device_get_binding(argv[args_indx.device]);
if (!eeprom) {
shell_error(sh, "EEPROM device not found");
return -EINVAL;
}
shell_print(sh, "Reading %zu bytes from EEPROM, offset %zu...", len,
addr);
for (upto = 0; upto < len; upto += pending) {
uint8_t data[SHELL_HEXDUMP_BYTES_IN_LINE];
pending = MIN(len - upto, SHELL_HEXDUMP_BYTES_IN_LINE);
err = eeprom_read(eeprom, addr, data, pending);
if (err) {
shell_error(sh, "EEPROM read failed (err %d)", err);
return err;
}
shell_hexdump_line(sh, addr, data, pending);
addr += pending;
}
shell_print(sh, "");
return 0;
}
static int cmd_write(const struct shell *sh, size_t argc, char **argv)
{
uint8_t wr_buf[CONFIG_EEPROM_SHELL_BUFFER_SIZE];
uint8_t rd_buf[CONFIG_EEPROM_SHELL_BUFFER_SIZE];
const struct device *eeprom;
unsigned long byte;
off_t offset;
size_t len;
int err;
int i;
offset = strtoul(argv[args_indx.offset], NULL, 0);
len = argc - args_indx.data;
if (len > sizeof(wr_buf)) {
shell_error(sh, "Write buffer size (%zu bytes) exceeded",
sizeof(wr_buf));
return -EINVAL;
}
for (i = 0; i < len; i++) {
byte = strtoul(argv[args_indx.data + i], NULL, 0);
if (byte > UINT8_MAX) {
shell_error(sh, "Error parsing data byte %d", i);
return -EINVAL;
}
wr_buf[i] = byte;
}
eeprom = device_get_binding(argv[args_indx.device]);
if (!eeprom) {
shell_error(sh, "EEPROM device not found");
return -EINVAL;
}
shell_print(sh, "Writing %zu bytes to EEPROM...", len);
err = eeprom_write(eeprom, offset, wr_buf, len);
if (err) {
shell_error(sh, "EEPROM write failed (err %d)", err);
return err;
}
shell_print(sh, "Verifying...");
err = eeprom_read(eeprom, offset, rd_buf, len);
if (err) {
shell_error(sh, "EEPROM read failed (err %d)", err);
return err;
}
if (memcmp(wr_buf, rd_buf, len) != 0) {
shell_error(sh, "Verify failed");
return -EIO;
}
shell_print(sh, "Verify OK");
return 0;
}
static int cmd_size(const struct shell *sh, size_t argc, char **argv)
{
const struct device *eeprom;
eeprom = device_get_binding(argv[args_indx.device]);
if (!eeprom) {
shell_error(sh, "EEPROM device not found");
return -EINVAL;
}
shell_print(sh, "%zu bytes", eeprom_get_size(eeprom));
return 0;
}
static int cmd_fill(const struct shell *sh, size_t argc, char **argv)
{
uint8_t wr_buf[CONFIG_EEPROM_SHELL_BUFFER_SIZE];
uint8_t rd_buf[CONFIG_EEPROM_SHELL_BUFFER_SIZE];
const struct device *eeprom;
unsigned long pattern;
size_t addr;
size_t initial_offset;
size_t len;
size_t pending;
size_t upto;
int err;
initial_offset = strtoul(argv[args_indx.offset], NULL, 0);
len = strtoul(argv[args_indx.length], NULL, 0);
pattern = strtoul(argv[args_indx.pattern], NULL, 0);
if (pattern > UINT8_MAX) {
shell_error(sh, "Error parsing pattern byte");
return -EINVAL;
}
memset(wr_buf, pattern, MIN(len, CONFIG_EEPROM_SHELL_BUFFER_SIZE));
eeprom = device_get_binding(argv[args_indx.device]);
if (!eeprom) {
shell_error(sh, "EEPROM device not found");
return -EINVAL;
}
shell_print(sh, "Writing %zu bytes of 0x%02lx to EEPROM...", len,
pattern);
addr = initial_offset;
for (upto = 0; upto < len; upto += pending) {
pending = MIN(len - upto, CONFIG_EEPROM_SHELL_BUFFER_SIZE);
err = eeprom_write(eeprom, addr, wr_buf, pending);
if (err) {
shell_error(sh, "EEPROM write failed (err %d)", err);
return err;
}
addr += pending;
}
addr = initial_offset;
shell_print(sh, "Verifying...");
for (upto = 0; upto < len; upto += pending) {
pending = MIN(len - upto, CONFIG_EEPROM_SHELL_BUFFER_SIZE);
err = eeprom_read(eeprom, addr, rd_buf, pending);
if (err) {
shell_error(sh, "EEPROM read failed (err %d)", err);
return err;
}
if (memcmp(wr_buf, rd_buf, pending) != 0) {
shell_error(sh, "Verify failed");
return -EIO;
}
addr += pending;
}
shell_print(sh, "Verify OK");
return 0;
}
/* Device name autocompletion support */
static void device_name_get(size_t idx, struct shell_static_entry *entry)
{
const struct device *dev = shell_device_lookup(idx, NULL);
entry->syntax = (dev != NULL) ? dev->name : NULL;
entry->handler = NULL;
entry->help = NULL;
entry->subcmd = NULL;
}
SHELL_DYNAMIC_CMD_CREATE(dsub_device_name, device_name_get);
SHELL_STATIC_SUBCMD_SET_CREATE(eeprom_cmds,
SHELL_CMD_ARG(read, &dsub_device_name,
"<device> <offset> <length>", cmd_read, 4, 0),
SHELL_CMD_ARG(write, &dsub_device_name,
"<device> <offset> [byte0] <byte1> .. <byteN>", cmd_write,
4, CONFIG_EEPROM_SHELL_BUFFER_SIZE - 1),
SHELL_CMD_ARG(size, &dsub_device_name, "<device>", cmd_size, 2, 0),
SHELL_CMD_ARG(fill, &dsub_device_name,
"<device> <offset> <length> <pattern>", cmd_fill, 5, 0),
SHELL_SUBCMD_SET_END
);
SHELL_CMD_REGISTER(eeprom, &eeprom_cmds, "EEPROM shell commands", NULL);
``` | /content/code_sandbox/drivers/eeprom/eeprom_shell.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 1,610 |
```unknown
# EEPROM driver configuration options
menuconfig EEPROM
bool "Electrically Erasable Programmable Read-Only Memory (EEPROM) drivers"
help
Enable support for EEPROM hardware.
if EEPROM
module = EEPROM
module-str = eeprom
source "subsys/logging/Kconfig.template.log_config"
config EEPROM_INIT_PRIORITY
int "EEPROM init priority"
default KERNEL_INIT_PRIORITY_DEVICE
help
EEPROM driver device initialization priority. This initialization
priority is used unless the driver implementation has its own
initialization priority.
config EEPROM_SHELL
bool "EEPROM shell"
depends on SHELL
help
Enable the EEPROM shell with EEPROM related commands.
config EEPROM_SHELL_BUFFER_SIZE
int "EEPROM shell buffer size"
default 256
depends on EEPROM_SHELL
help
Size of the buffer used for EEPROM read/write commands in
the EEPROM shell.
config EEPROM_AT2X
bool
help
Enable support for Atmel AT2x (and compatible) I2C/SPI
EEPROMs.
config EEPROM_AT2X_EMUL
bool "Emulate an Atmel AT24 I2C chip"
depends on EMUL
help
This is an emulator for the Atmel AT24 series of I2C-attached EEPROMs.
At present it only supports 8-bit addressing. The size of the EEPROM
is given by the 'size' property. See the binding for further details.
config EEPROM_AT24
bool "I2C EEPROMs compatible with Atmel's AT24 family"
default y
depends on DT_HAS_ATMEL_AT24_ENABLED
select I2C
select EEPROM_AT2X
help
Enable support for I2C EEPROMs compatible with Atmel's AT24 family.
There are multiple vendors manufacturing I2C EEPROMs compatible with
the programming model of the Atmel AT24.
Examples of compatible EEPROM families:
- Microchip AT24xxx
- ST M24xxx
config EEPROM_AT25
bool "SPI EEPROMs compatibile with Atmel's AT25 family"
default y
depends on DT_HAS_ATMEL_AT25_ENABLED
select SPI
select EEPROM_AT2X
help
Enable support for SPI EEPROMs compatible with Atmel's AT25 family.
There are multiple vendors manufacturing SPI EEPROMs compatible with
the programming model of the Atmel AT25.
Examples of compatible EEPROM families:
- Microchip AT25xxx
- ST M95xxx
config EEPROM_AT2X_INIT_PRIORITY
int "AT2X EEPROM init priority"
default 80
depends on EEPROM_AT2X
help
AT2X EEPROM driver device initialization priority.
The EEPROM is connected to I2C or SPI bus an has to be initialized
after I2C/SPI driver.
source "drivers/eeprom/Kconfig.lpc11u6x"
source "drivers/eeprom/Kconfig.stm32"
source "drivers/eeprom/Kconfig.eeprom_emu"
source "drivers/eeprom/Kconfig.tmp116"
source "drivers/eeprom/Kconfig.xec"
source "drivers/eeprom/Kconfig.mb85rcxx"
config EEPROM_SIMULATOR
bool "Simulated EEPROM driver"
default y
depends on DT_HAS_ZEPHYR_SIM_EEPROM_ENABLED
depends on !(ARCH_POSIX && !EXTERNAL_LIBC)
select STATS
select STATS_NAMES
help
Enable Simulated EEPROM driver.
config EEPROM_SIMULATOR_SIMULATE_TIMING
bool "Hardware timing simulation"
depends on EEPROM_SIMULATOR
help
Enable Simulated hardware timing.
if EEPROM_SIMULATOR_SIMULATE_TIMING
config EEPROM_SIMULATOR_MIN_READ_TIME_US
int
prompt "Minimum read time (S)"
default 2
range 1 1000000
config EEPROM_SIMULATOR_MIN_WRITE_TIME_US
int
prompt "Minimum write time (S)"
default 100
range 1 1000000
endif # EEPROM_SIMULATOR_SIMULATE_TIMING
config EEPROM_FAKE
bool "Fake EEPROM driver"
default y
depends on DT_HAS_ZEPHYR_FAKE_EEPROM_ENABLED
help
Enable support for the FFF-based fake EEPROM driver.
endif # EEPROM
``` | /content/code_sandbox/drivers/eeprom/Kconfig | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 879 |
```c
/*
*
*/
/*
* This driver emulates an EEPROM device in flash.
*
* The emulation represents the EEPROM in flash as a region that is a direct
* map of the EEPROM data (EEPROM data) followed by a region where changes to
* the EEPROM data (EEPROM changes) are stored. The combination of EEPROM data
* and EEPROM changes form a EEPROM page (see drawing below). Changes to EEPROM
* data are written as address-data combinations. The size of such a combination
* is determined by the flash write block size and the size of the EEPROM
* (required address space), with a minimum of 4 byte.
*
* When there is no more space to store changes a new EEPROM page is taken into
* use. This copies the existing data to the EEPROM data area of the new page.
* During this copying the write that is performed is applied at the same time.
* The old page is then invalidated.
*
* The EEPROM page needs to be a multiple of a flash page size. Multiple EEPROM
* pages are also supported and increases the number of writes that can be
* performed.
*
* The representation of the EEPROM on flash is shown in the next graph.
*
* |your_sha256_hash-------|
* ||----------------------| |----------------------| |-------------------||
* || EEPROM data | | | |-Flash page--------||
* || | | | |
* || size = EEPROM size | | | |
* ||----------------------| |----------------------| ... |
* || EEPROM changes: | | | |
* || (address, new data) | | | |
* || | | | |
* || XX| | XX| |
* ||--EEPROM page 0-------| |--EEPROM page 1-------| |
* |your_sha256_hashition--|
* XX: page validity marker: all 0x00: page invalid
*
* Internally the address of an EEPROM byte is represented by a uint32_t (this
* should be sufficient in all cases). In case the EEPROM size is smaller than
* 64kB only a uint16_t is used to store changes. In this case the change stored
* for a 4 byte flash write block size are a combination of 2 byte address and
* 2 byte data.
*
* The EEPROM size, pagesize and the flash partition used for the EEPROM are
* defined in the dts. The flash partition should allow at least two EEPROM
* pages.
*
*/
#define DT_DRV_COMPAT zephyr_emu_eeprom
#define EEPROM_EMU_VERSION 0
#define EEPROM_EMU_MAGIC 0x45454d55 /* EEMU in hex */
#include <zephyr/drivers/eeprom.h>
#include <zephyr/drivers/flash.h>
#include <zephyr/kernel.h>
#define LOG_LEVEL CONFIG_EEPROM_LOG_LEVEL
#include <zephyr/logging/log.h>
LOG_MODULE_REGISTER(eeprom_emulator);
struct eeprom_emu_config {
/* EEPROM size */
size_t size;
/* EEPROM is read-only */
bool readonly;
/* Page size used to emulate the EEPROM, contains one area of EEPROM
* size and a area to store changes.
*/
size_t page_size;
/* Offset of the flash partition used to emulate the EEPROM */
off_t flash_offset;
/* Size of the flash partition to emulate the EEPROM */
size_t flash_size;
/* Delay the erase of EEPROM pages until the complete partition is used.
*/
bool partitionerase;
/* Size of a change block */
uint8_t flash_cbs;
uint8_t *rambuf;
/* Device of the flash partition used to emulate the EEPROM */
const struct device *flash_dev;
};
struct eeprom_emu_data {
/* Offset in current (EEPROM) page where next change is written */
off_t write_offset;
/* Offset of the current (EEPROM) page */
off_t page_offset;
struct k_mutex lock;
};
/* read/write context */
struct eeprom_emu_ctx {
const void *data; /* pointer to data */
const size_t len; /* data length */
const off_t address; /* eeprom address */
size_t rlen; /* data remaining (unprocessed) length */
};
/*
* basic flash read, only used with offset aligned to flash write block size
*/
static inline int eeprom_emu_flash_read(const struct device *dev, off_t offset,
uint8_t *blk, size_t len)
{
const struct eeprom_emu_config *dev_config = dev->config;
return flash_read(dev_config->flash_dev, dev_config->flash_offset +
offset, blk, len);
}
/*
* basic flash write, only used with offset aligned to flash write block size
*/
static inline int eeprom_emu_flash_write(const struct device *dev, off_t offset,
const uint8_t *blk, size_t len)
{
const struct eeprom_emu_config *dev_config = dev->config;
int rc;
rc = flash_write(dev_config->flash_dev, dev_config->flash_offset +
offset, blk, len);
return rc;
}
/*
* basic flash erase, only used with offset aligned to flash page and len a
* multiple of the flash page size
*/
static inline int eeprom_emu_flash_erase(const struct device *dev, off_t offset,
size_t len)
{
const struct eeprom_emu_config *dev_config = dev->config;
int rc;
rc = flash_erase(dev_config->flash_dev, dev_config->flash_offset +
offset, len);
return rc;
}
/*
* eeprom_emu_page_invalidate: invalidate a page by writing all zeros at the end
*/
static int eeprom_emu_page_invalidate(const struct device *dev, off_t offset)
{
const struct eeprom_emu_config *dev_config = dev->config;
uint8_t buf[dev_config->flash_cbs];
LOG_DBG("Invalidating page at [0x%tx]", (ptrdiff_t)offset);
memset(buf, 0x00, sizeof(buf));
offset += (dev_config->page_size - sizeof(buf));
return eeprom_emu_flash_write(dev, offset, buf, sizeof(buf));
}
/*
* eeprom_emu_get_address: read the address from a change block
*/
static uint32_t eeprom_emu_get_address(const struct device *dev,
const uint8_t *blk)
{
const struct eeprom_emu_config *dev_config = dev->config;
uint32_t address = 0U;
blk += dev_config->flash_cbs / 2;
for (int i = 0; i < sizeof(address); i++) {
if (2 * i == dev_config->flash_cbs) {
break;
}
address += ((uint32_t)(*blk) << (8 * i));
blk++;
}
return address;
}
/*
* eeprom_emu_set_change: create change blocks from data in blk and address
*/
static void eeprom_emu_set_change(const struct device *dev,
const uint32_t address, const uint8_t *data,
uint8_t *blk)
{
const struct eeprom_emu_config *dev_config = dev->config;
for (int i = 0; i < (dev_config->flash_cbs / 2); i++) {
(*blk++) = (*data++);
}
for (int i = 0; i < (dev_config->flash_cbs / 2); i++) {
if (i < sizeof(address)) {
(*blk++) = (uint8_t)(((address >> (8 * i)) & 0xff));
} else {
(*blk++) = 0xff;
}
}
}
/*
* eeprom_emu_is_word_used: check if word is not empty
*/
static int eeprom_emu_is_word_used(const struct device *dev, const uint8_t *blk)
{
const struct eeprom_emu_config *dev_config = dev->config;
for (int i = 0; i < dev_config->flash_cbs; i++) {
if ((*blk++) != 0xff) {
return 1;
}
}
return 0;
}
/*
* eeprom_emu_word_read: read basic word (cbs byte of data) item from
* address directly from flash.
*/
static int eeprom_emu_word_read(const struct device *dev, off_t address,
uint8_t *data)
{
const struct eeprom_emu_config *dev_config = dev->config;
const struct eeprom_emu_data *dev_data = dev->data;
uint8_t buf[dev_config->flash_cbs];
off_t direct_address;
int rc;
direct_address = dev_data->page_offset + address;
/* Direct flash read */
rc = eeprom_emu_flash_read(dev, direct_address, data, sizeof(buf));
if (rc) {
return rc;
}
/* Process changes written to flash */
off_t offset, ch_address;
bool mc1 = false, mc2 = false;
offset = dev_data->write_offset;
while (((!mc1) || (!mc2)) && (offset > dev_config->size)) {
offset -= sizeof(buf);
/* read the change */
rc = eeprom_emu_flash_read(dev, dev_data->page_offset + offset,
buf, sizeof(buf));
if (rc) {
return rc;
}
/* get the address from a change block */
ch_address = eeprom_emu_get_address(dev, buf);
if ((!mc1) && (ch_address == address)) {
memcpy(data, buf, sizeof(buf)/2);
mc1 = true;
}
if ((!mc2) && (ch_address == (address + sizeof(buf)/2))) {
memcpy(data + sizeof(buf)/2, buf, sizeof(buf)/2);
mc2 = true;
}
}
return rc;
}
/* Update data specified in ctx from flash */
static int eeprom_emu_flash_get(const struct device *dev,
struct eeprom_emu_ctx *ctx)
{
const struct eeprom_emu_config *dev_config = dev->config;
off_t address = ctx->address + ctx->len - ctx->rlen;
uint8_t *data8 = (uint8_t *)(ctx->data);
uint8_t buf[dev_config->flash_cbs];
const off_t addr_jmp = address & (sizeof(buf) - 1);
size_t len;
int rc;
data8 += (ctx->len - ctx->rlen);
len = MIN((sizeof(buf) - addr_jmp), ctx->rlen);
rc = eeprom_emu_word_read(dev, address - addr_jmp, buf);
if (rc) {
return rc;
}
memcpy(data8, buf + addr_jmp, len);
ctx->rlen -= len;
return rc;
}
/*
* eeprom_emu_compactor: start a new EEPROM page and copy existing data to the
* new page. During copy update the data with present write data. Invalidate
* the old page.
*/
static int eeprom_emu_compactor(const struct device *dev,
struct eeprom_emu_ctx *ctx)
{
const struct eeprom_emu_config *dev_config = dev->config;
struct eeprom_emu_data *dev_data = dev->data;
off_t next_page_offset;
int rc = 0;
LOG_DBG("Compactor called for page at [0x%tx]",
(ptrdiff_t)dev_data->page_offset);
next_page_offset = dev_data->page_offset + dev_config->page_size;
if (next_page_offset >= dev_config->flash_size) {
next_page_offset = 0;
}
if (!dev_config->partitionerase) {
/* erase the new page */
rc = eeprom_emu_flash_erase(dev, next_page_offset,
dev_config->page_size);
} else if (next_page_offset == 0) {
/* erase the entire partition */
rc = eeprom_emu_flash_erase(dev, next_page_offset,
dev_config->flash_size);
} else {
rc = 0;
}
if (rc) {
return rc;
}
if (dev_config->rambuf && (ctx != NULL)) {
rc = eeprom_emu_flash_write(dev, next_page_offset,
dev_config->rambuf,
dev_config->size);
if (rc) {
return rc;
}
ctx->rlen = 0;
} else {
off_t rd_offset = 0;
uint8_t buf[dev_config->flash_cbs];
/* reset the context if available */
if (ctx != NULL) {
ctx->rlen = ctx->len;
}
/* copy existing data */
while (rd_offset < dev_config->size) {
rc = eeprom_emu_word_read(dev, rd_offset, buf);
if (rc) {
return rc;
}
if ((ctx != NULL) && (ctx->len) &&
(rd_offset > (ctx->address - sizeof(buf)))) {
/* overwrite buf data with context data */
uint8_t *data8 = (uint8_t *)(ctx->data);
off_t address, addr_jmp;
size_t len;
address = ctx->address + ctx->len - ctx->rlen;
addr_jmp = address & (sizeof(buf) - 1);
len = MIN((sizeof(buf) - addr_jmp), ctx->rlen);
data8 += (ctx->len - ctx->rlen);
memcpy(buf + addr_jmp, data8, len);
ctx->rlen -= len;
}
if (eeprom_emu_is_word_used(dev, buf)) {
rc = eeprom_emu_flash_write(dev,
next_page_offset +
rd_offset, buf,
sizeof(buf));
if (rc) {
return rc;
}
}
rd_offset += sizeof(buf);
}
}
if ((dev_config->partitionerase) && (next_page_offset == 0)) {
/* no need to invalidate previous page as it has been deleted */
rc = 0;
} else {
/* invalidate the old page */
rc = eeprom_emu_page_invalidate(dev, dev_data->page_offset);
}
if (!rc) {
dev_data->write_offset = dev_config->size;
dev_data->page_offset = next_page_offset;
}
return rc;
}
/*
* eeprom_emu_word_write: write basic word (cbs bytes of data) item to address,
*/
static int eeprom_emu_word_write(const struct device *dev, off_t address,
const uint8_t *data,
struct eeprom_emu_ctx *ctx)
{
const struct eeprom_emu_config *dev_config = dev->config;
struct eeprom_emu_data *dev_data = dev->data;
uint8_t buf[dev_config->flash_cbs], tmp[dev_config->flash_cbs];
off_t direct_address, wraddr;
int rc;
direct_address = dev_data->page_offset + address;
rc = eeprom_emu_flash_read(dev, direct_address, buf, sizeof(buf));
if (rc) {
return rc;
}
if (!eeprom_emu_is_word_used(dev, buf)) {
if (eeprom_emu_is_word_used(dev, data)) {
rc = eeprom_emu_flash_write(dev, direct_address, data,
sizeof(buf));
}
return rc;
}
rc = eeprom_emu_word_read(dev, address, buf);
if (rc) {
return rc;
}
if (!memcmp(buf, data, sizeof(buf))) {
/* data has not changed */
return rc;
}
wraddr = address;
/* store change */
for (uint8_t i = 0; i < 2; i++) {
if (memcmp(&buf[i*sizeof(buf)/2], data, sizeof(buf)/2)) {
eeprom_emu_set_change(dev, wraddr, data, tmp);
rc = eeprom_emu_flash_write(dev, dev_data->page_offset +
dev_data->write_offset, tmp,
sizeof(buf));
if (rc) {
return rc;
}
dev_data->write_offset += sizeof(buf);
if ((dev_data->write_offset + sizeof(buf)) >=
dev_config->page_size) {
rc = eeprom_emu_compactor(dev, ctx);
return rc;
}
}
data += sizeof(buf)/2;
wraddr += sizeof(buf)/2;
}
return rc;
}
/* Update flash with data specified in ctx */
static int eeprom_emu_flash_set(const struct device *dev,
struct eeprom_emu_ctx *ctx)
{
const struct eeprom_emu_config *dev_config = dev->config;
off_t address = ctx->address + ctx->len - ctx->rlen;
uint8_t *data8 = (uint8_t *)(ctx->data);
uint8_t buf[dev_config->flash_cbs];
const off_t addr_jmp = address & (sizeof(buf) - 1);
size_t len;
int rc;
data8 += (ctx->len - ctx->rlen);
len = MIN((sizeof(buf) - addr_jmp), ctx->rlen);
rc = eeprom_emu_word_read(dev, address - addr_jmp, buf);
if (rc) {
return rc;
}
memcpy(buf + addr_jmp, data8, len);
rc = eeprom_emu_word_write(dev, address - addr_jmp, buf, ctx);
if (rc) {
return rc;
}
if (ctx->rlen) {
ctx->rlen -= len;
}
return rc;
}
static int eeprom_emu_range_is_valid(const struct device *dev, off_t address,
size_t len)
{
const struct eeprom_emu_config *dev_config = dev->config;
if ((address + len) <= dev_config->size) {
return 1;
}
return 0;
}
static int eeprom_emu_read(const struct device *dev, off_t address, void *data,
size_t len)
{
const struct eeprom_emu_config *dev_config = dev->config;
struct eeprom_emu_data *dev_data = dev->data;
struct eeprom_emu_ctx ctx = {
.data = data,
.len = len,
.address = address,
.rlen = len,
};
int rc = 0;
/* Nothing to do */
if (!len) {
return 0;
}
/* Error checking */
if ((!data) || (!eeprom_emu_range_is_valid(dev, address, len))) {
return -EINVAL;
}
if (!device_is_ready(dev_config->flash_dev)) {
LOG_ERR("flash device is not ready");
return -EIO;
}
/* Handle normal case */
LOG_DBG("EEPROM read at [0x%tx] length[%zu]", (ptrdiff_t)address, len);
k_mutex_lock(&dev_data->lock, K_FOREVER);
/* read from rambuffer if possible */
if (dev_config->rambuf) {
memcpy(data, dev_config->rambuf + address, len);
} else {
/* read from flash if no rambuffer */
while (ctx.rlen) {
rc = eeprom_emu_flash_get(dev, &ctx);
if (rc) {
break;
}
}
}
k_mutex_unlock(&dev_data->lock);
return rc;
}
static int eeprom_emu_write(const struct device *dev, off_t address,
const void *data, size_t len)
{
const struct eeprom_emu_config *dev_config = dev->config;
struct eeprom_emu_data *dev_data = dev->data;
struct eeprom_emu_ctx ctx = {
.data = data,
.len = len,
.address = address,
.rlen = len,
};
int rc = 0;
/* Nothing to do */
if (!len) {
return 0;
}
/* Error checking */
if ((!data) || (!eeprom_emu_range_is_valid(dev, address, len))) {
return -EINVAL;
}
if (dev_config->readonly) {
LOG_ERR("attempt to write to read-only device");
return -EACCES;
}
if (!device_is_ready(dev_config->flash_dev)) {
LOG_ERR("flash device is not ready");
return -EIO;
}
/* Handle normal case */
LOG_DBG("EEPROM write at [0x%tx] length[%zu]", (ptrdiff_t)address, len);
k_mutex_lock(&dev_data->lock, K_FOREVER);
/* first update the rambuffer */
if (dev_config->rambuf) {
memcpy(dev_config->rambuf + address, data, len);
}
/* second update the flash */
while (ctx.rlen) {
rc = eeprom_emu_flash_set(dev, &ctx);
if (rc) {
break;
}
}
k_mutex_unlock(&dev_data->lock);
return rc;
}
static size_t eeprom_emu_size(const struct device *dev)
{
const struct eeprom_emu_config *dev_config = dev->config;
return dev_config->size;
}
static int eeprom_emu_init(const struct device *dev)
{
const struct eeprom_emu_config *dev_config = dev->config;
struct eeprom_emu_data *dev_data = dev->data;
off_t offset;
uint8_t buf[dev_config->flash_cbs];
int rc = 0;
k_mutex_init(&dev_data->lock);
if (!device_is_ready(dev_config->flash_dev)) {
__ASSERT(0, "Could not get flash device binding");
return -ENODEV;
}
/* Find the page offset */
dev_data->page_offset = 0U;
dev_data->write_offset = dev_config->page_size - sizeof(buf);
while (dev_data->page_offset < dev_config->flash_size) {
offset = dev_data->page_offset + dev_data->write_offset;
rc = eeprom_emu_flash_read(dev, offset, buf, sizeof(buf));
if (rc) {
return rc;
}
if (!eeprom_emu_is_word_used(dev, buf)) {
break;
}
dev_data->page_offset += dev_config->page_size;
}
if (dev_data->page_offset == dev_config->flash_size) {
__ASSERT(0, "All pages are invalid, is this a EEPROM area?");
return -EINVAL;
}
dev_data->write_offset = dev_config->size;
/* Update the write offset */
while ((dev_data->write_offset + sizeof(buf)) < dev_config->page_size) {
offset = dev_data->page_offset + dev_data->write_offset;
rc = eeprom_emu_flash_read(dev, offset, buf, sizeof(buf));
if (rc) {
return rc;
}
if (!eeprom_emu_is_word_used(dev, buf)) {
break;
}
dev_data->write_offset += sizeof(buf);
}
/* dev_data->write_offset reaches last possible location, compaction
* might have been interrupted: call eeprom_emu_compactor again, but
* only in case we are using a write-enabled eeprom
*/
if ((!dev_config->readonly) &&
((dev_data->write_offset + sizeof(buf)) >= dev_config->page_size)) {
rc = eeprom_emu_compactor(dev, NULL);
if (rc) {
return rc;
}
}
/* Fill the ram buffer if enabled */
if (dev_config->rambuf) {
offset = 0;
while (offset < dev_config->size) {
rc = eeprom_emu_word_read(dev, offset, buf);
if (rc) {
return rc;
}
memcpy(dev_config->rambuf + offset, buf, sizeof(buf));
offset += sizeof(buf);
}
}
return rc;
}
static const struct eeprom_driver_api eeprom_emu_api = {
.read = eeprom_emu_read,
.write = eeprom_emu_write,
.size = eeprom_emu_size,
};
#define EEPROM_PARTITION(n) DT_INST_PHANDLE_BY_IDX(n, partition, 0)
#define PART_WBS(part) \
DT_PROP(COND_CODE_1(DT_NODE_HAS_COMPAT(DT_GPARENT(part), soc_nv_flash),\
(DT_GPARENT(part)), (DT_PARENT(part))), write_block_size)
#define PART_CBS(part, size) (PART_WBS(part) < 4) ? \
((size > KB(64)) ? 8 : 4) : PART_WBS(part)
#define PART_DEV_ID(part) \
COND_CODE_1(DT_NODE_HAS_COMPAT(DT_GPARENT(part), soc_nv_flash), \
(DT_PARENT(DT_GPARENT(part))), (DT_GPARENT(part)))
#define PART_DEV(part) \
DEVICE_DT_GET(PART_DEV_ID(part))
#define RECALC_SIZE(size, cbs) \
(size % cbs) ? ((size + cbs - 1) & ~(cbs - 1)) : size
#define ASSERT_SIZE_PAGESIZE_VALID(size, pagesize, readonly) \
BUILD_ASSERT(readonly ? (size <= pagesize) : (4*size <= 3*pagesize), \
"EEPROM size to big for pagesize")
#define ASSERT_PAGESIZE_PARTSIZE_VALID(pagesize, partsize) \
BUILD_ASSERT(partsize % pagesize == 0U, \
"Partition size not a multiple of pagesize")
#define ASSERT_PAGESIZE_SIZE(pagesize, partsize, onepage) \
BUILD_ASSERT(onepage ? (partsize >= pagesize) : (partsize > pagesize),\
"Partition size to small")
#define EEPROM_EMU_READ_ONLY(n) \
DT_INST_PROP(n, read_only) || \
DT_PROP(EEPROM_PARTITION(n), read_only)
#define EEPROM_EMU_ONEPAGE(n) \
EEPROM_EMU_READ_ONLY(n) || DT_INST_PROP(n, partition_erase)
#define EEPROM_EMU_ENABLE_RAMBUF(n) \
COND_CODE_1(DT_INST_PROP(n, rambuf), (1), \
(COND_CODE_1(DT_INST_PROP(n, partition_erase), (1), (0))))
#define EEPROM_EMU_RAMBUF(n) \
COND_CODE_0(EEPROM_EMU_ENABLE_RAMBUF(n), (), \
(static uint8_t eeprom_emu_##n##_rambuf[DT_INST_PROP(n, size)];))
#define EEPROM_EMU_RAMBUF_LINK(n) \
COND_CODE_0(EEPROM_EMU_ENABLE_RAMBUF(n), (NULL), \
(eeprom_emu_##n##_rambuf))
#define EEPROM_EMU_INIT(n) \
ASSERT_SIZE_PAGESIZE_VALID(DT_INST_PROP(n, size), \
DT_INST_PROP(n, pagesize), EEPROM_EMU_ONEPAGE(n)); \
ASSERT_PAGESIZE_PARTSIZE_VALID(DT_INST_PROP(n, pagesize), \
DT_REG_SIZE(EEPROM_PARTITION(n))); \
ASSERT_PAGESIZE_SIZE(DT_INST_PROP(n, pagesize), \
DT_REG_SIZE(EEPROM_PARTITION(n)), EEPROM_EMU_ONEPAGE(n)); \
EEPROM_EMU_RAMBUF(n) \
static const struct eeprom_emu_config eeprom_emu_##n##_config = { \
.size = RECALC_SIZE( \
DT_INST_PROP(n, size), \
(PART_CBS(EEPROM_PARTITION(n), DT_INST_PROP(n, size))) \
), \
.readonly = EEPROM_EMU_READ_ONLY(n), \
.page_size = DT_INST_PROP(n, pagesize), \
.flash_offset = DT_REG_ADDR(EEPROM_PARTITION(n)), \
.flash_size = DT_REG_SIZE(EEPROM_PARTITION(n)), \
.partitionerase = DT_INST_PROP(n, partition_erase), \
.flash_cbs = PART_CBS(EEPROM_PARTITION(n), \
DT_INST_PROP(n, size)), \
.flash_dev = PART_DEV(EEPROM_PARTITION(n)),\
.rambuf = EEPROM_EMU_RAMBUF_LINK(n), \
}; \
static struct eeprom_emu_data eeprom_emu_##n##_data; \
DEVICE_DT_INST_DEFINE(n, &eeprom_emu_init, \
NULL, &eeprom_emu_##n##_data, \
&eeprom_emu_##n##_config, POST_KERNEL, \
CONFIG_EEPROM_INIT_PRIORITY, &eeprom_emu_api); \
DT_INST_FOREACH_STATUS_OKAY(EEPROM_EMU_INIT)
``` | /content/code_sandbox/drivers/eeprom/eeprom_emulator.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 6,112 |
```c
/*
*
*/
#define DT_DRV_COMPAT zephyr_sim_eeprom
#ifdef CONFIG_ARCH_POSIX
#undef _POSIX_C_SOURCE
/* Note: This is used only for interaction with the host C library, and is therefore exempt of
* coding guidelines rule A.4&5 which applies to the embedded code using embedded libraries
*/
#define _POSIX_C_SOURCE 200809L
#include <unistd.h>
#include <sys/types.h>
#include <sys/mman.h>
#include <fcntl.h>
#include "cmdline.h"
#include "soc.h"
#endif
#include <zephyr/device.h>
#include <zephyr/drivers/eeprom.h>
#include <zephyr/init.h>
#include <zephyr/kernel.h>
#include <zephyr/sys/util.h>
#include <zephyr/stats/stats.h>
#include <string.h>
#include <errno.h>
#define LOG_LEVEL CONFIG_EEPROM_LOG_LEVEL
#include <zephyr/logging/log.h>
LOG_MODULE_REGISTER(eeprom_simulator);
struct eeprom_sim_config {
size_t size;
bool readonly;
};
#define EEPROM(addr) (mock_eeprom + (addr))
#if defined(CONFIG_MULTITHREADING)
/* semaphore for locking flash resources (tickers) */
static struct k_sem sem_lock;
#define SYNC_INIT() k_sem_init(&sem_lock, 1, 1)
#define SYNC_LOCK() k_sem_take(&sem_lock, K_FOREVER)
#define SYNC_UNLOCK() k_sem_give(&sem_lock)
#else
#define SYNC_INIT()
#define SYNC_LOCK()
#define SYNC_UNLOCK()
#endif
/* simulator statistics */
STATS_SECT_START(eeprom_sim_stats)
STATS_SECT_ENTRY32(bytes_read) /* total bytes read */
STATS_SECT_ENTRY32(bytes_written) /* total bytes written */
STATS_SECT_ENTRY32(eeprom_read_calls) /* calls to eeprom_read() */
STATS_SECT_ENTRY32(eeprom_read_time_us) /* time spent in eeprom_read() */
STATS_SECT_ENTRY32(eeprom_write_calls) /* calls to eeprom_write() */
STATS_SECT_ENTRY32(eeprom_write_time_us)/* time spent in eeprom_write() */
STATS_SECT_END;
STATS_SECT_DECL(eeprom_sim_stats) eeprom_sim_stats;
STATS_NAME_START(eeprom_sim_stats)
STATS_NAME(eeprom_sim_stats, bytes_read)
STATS_NAME(eeprom_sim_stats, bytes_written)
STATS_NAME(eeprom_sim_stats, eeprom_read_calls)
STATS_NAME(eeprom_sim_stats, eeprom_read_time_us)
STATS_NAME(eeprom_sim_stats, eeprom_write_calls)
STATS_NAME(eeprom_sim_stats, eeprom_write_time_us)
STATS_NAME_END(eeprom_sim_stats);
/* simulator dynamic thresholds */
STATS_SECT_START(eeprom_sim_thresholds)
STATS_SECT_ENTRY32(max_write_calls)
STATS_SECT_ENTRY32(max_len)
STATS_SECT_END;
STATS_SECT_DECL(eeprom_sim_thresholds) eeprom_sim_thresholds;
STATS_NAME_START(eeprom_sim_thresholds)
STATS_NAME(eeprom_sim_thresholds, max_write_calls)
STATS_NAME(eeprom_sim_thresholds, max_len)
STATS_NAME_END(eeprom_sim_thresholds);
#ifdef CONFIG_ARCH_POSIX
static uint8_t *mock_eeprom;
static int eeprom_fd = -1;
static const char *eeprom_file_path;
static const char default_eeprom_file_path[] = "eeprom.bin";
#else
static uint8_t mock_eeprom[DT_INST_PROP(0, size)];
#endif /* CONFIG_ARCH_POSIX */
static int eeprom_range_is_valid(const struct device *dev, off_t offset,
size_t len)
{
const struct eeprom_sim_config *config = dev->config;
if ((offset + len) <= config->size) {
return 1;
}
return 0;
}
static int eeprom_sim_read(const struct device *dev, off_t offset, void *data,
size_t len)
{
if (!len) {
return 0;
}
if (!eeprom_range_is_valid(dev, offset, len)) {
LOG_WRN("attempt to read past device boundary");
return -EINVAL;
}
SYNC_LOCK();
STATS_INC(eeprom_sim_stats, eeprom_read_calls);
memcpy(data, EEPROM(offset), len);
STATS_INCN(eeprom_sim_stats, bytes_read, len);
SYNC_UNLOCK();
#ifdef CONFIG_EEPROM_SIMULATOR_SIMULATE_TIMING
k_busy_wait(CONFIG_EEPROM_SIMULATOR_MIN_READ_TIME_US);
STATS_INCN(eeprom_sim_stats, eeprom_read_time_us,
CONFIG_EEPROM_SIMULATOR_MIN_READ_TIME_US);
#endif
return 0;
}
static int eeprom_sim_write(const struct device *dev, off_t offset,
const void *data,
size_t len)
{
const struct eeprom_sim_config *config = dev->config;
if (config->readonly) {
LOG_WRN("attempt to write to read-only device");
return -EACCES;
}
if (!len) {
return 0;
}
if (!eeprom_range_is_valid(dev, offset, len)) {
LOG_WRN("attempt to write past device boundary");
return -EINVAL;
}
SYNC_LOCK();
STATS_INC(eeprom_sim_stats, eeprom_write_calls);
bool data_part_ignored = false;
if (eeprom_sim_thresholds.max_write_calls != 0) {
if (eeprom_sim_stats.eeprom_write_calls >
eeprom_sim_thresholds.max_write_calls) {
goto end;
} else if (eeprom_sim_stats.eeprom_write_calls ==
eeprom_sim_thresholds.max_write_calls) {
if (eeprom_sim_thresholds.max_len == 0) {
goto end;
}
data_part_ignored = true;
}
}
if ((data_part_ignored) && (len > eeprom_sim_thresholds.max_len)) {
len = eeprom_sim_thresholds.max_len;
}
memcpy(EEPROM(offset), data, len);
STATS_INCN(eeprom_sim_stats, bytes_written, len);
#ifdef CONFIG_EEPROM_SIMULATOR_SIMULATE_TIMING
/* wait before returning */
k_busy_wait(CONFIG_EEPROM_SIMULATOR_MIN_WRITE_TIME_US);
STATS_INCN(eeprom_sim_stats, eeprom_write_time_us,
CONFIG_EEPROM_SIMULATOR_MIN_WRITE_TIME_US);
#endif
end:
SYNC_UNLOCK();
return 0;
}
static size_t eeprom_sim_size(const struct device *dev)
{
const struct eeprom_sim_config *config = dev->config;
return config->size;
}
static const struct eeprom_driver_api eeprom_sim_api = {
.read = eeprom_sim_read,
.write = eeprom_sim_write,
.size = eeprom_sim_size,
};
static const struct eeprom_sim_config eeprom_sim_config_0 = {
.size = DT_INST_PROP(0, size),
.readonly = DT_INST_PROP(0, read_only),
};
#ifdef CONFIG_ARCH_POSIX
static int eeprom_mock_init(const struct device *dev)
{
if (eeprom_file_path == NULL) {
eeprom_file_path = default_eeprom_file_path;
}
eeprom_fd = open(eeprom_file_path, O_RDWR | O_CREAT, (mode_t)0600);
if (eeprom_fd == -1) {
posix_print_warning("Failed to open eeprom device file "
"%s: %s\n",
eeprom_file_path, strerror(errno));
return -EIO;
}
if (ftruncate(eeprom_fd, DT_INST_PROP(0, size)) == -1) {
posix_print_warning("Failed to resize eeprom device file "
"%s: %s\n",
eeprom_file_path, strerror(errno));
return -EIO;
}
mock_eeprom = mmap(NULL, DT_INST_PROP(0, size),
PROT_WRITE | PROT_READ, MAP_SHARED, eeprom_fd, 0);
if (mock_eeprom == MAP_FAILED) {
posix_print_warning("Failed to mmap eeprom device file "
"%s: %s\n",
eeprom_file_path, strerror(errno));
return -EIO;
}
return 0;
}
#else
static int eeprom_mock_init(const struct device *dev)
{
memset(mock_eeprom, 0xFF, ARRAY_SIZE(mock_eeprom));
return 0;
}
#endif /* CONFIG_ARCH_POSIX */
static int eeprom_sim_init(const struct device *dev)
{
SYNC_INIT();
STATS_INIT_AND_REG(eeprom_sim_stats, STATS_SIZE_32, "eeprom_sim_stats");
STATS_INIT_AND_REG(eeprom_sim_thresholds, STATS_SIZE_32,
"eeprom_sim_thresholds");
return eeprom_mock_init(dev);
}
DEVICE_DT_INST_DEFINE(0, &eeprom_sim_init, NULL,
NULL, &eeprom_sim_config_0, POST_KERNEL,
CONFIG_EEPROM_INIT_PRIORITY, &eeprom_sim_api);
#ifdef CONFIG_ARCH_POSIX
static void eeprom_native_cleanup(void)
{
if ((mock_eeprom != MAP_FAILED) && (mock_eeprom != NULL)) {
munmap(mock_eeprom, DT_INST_PROP(0, size));
}
if (eeprom_fd != -1) {
close(eeprom_fd);
}
}
static void eeprom_native_options(void)
{
static struct args_struct_t eeprom_options[] = {
{ .manual = false,
.is_mandatory = false,
.is_switch = false,
.option = "eeprom",
.name = "path",
.type = 's',
.dest = (void *)&eeprom_file_path,
.call_when_found = NULL,
.descript = "Path to binary file to be used as eeprom" },
ARG_TABLE_ENDMARKER
};
native_add_command_line_opts(eeprom_options);
}
NATIVE_TASK(eeprom_native_options, PRE_BOOT_1, 1);
NATIVE_TASK(eeprom_native_cleanup, ON_EXIT, 1);
#endif /* CONFIG_ARCH_POSIX */
``` | /content/code_sandbox/drivers/eeprom/eeprom_simulator.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 2,098 |
```c
/*
*
*/
#define DT_DRV_COMPAT microchip_xec_eeprom
#include <zephyr/device.h>
#include <zephyr/drivers/eeprom.h>
#include <zephyr/kernel.h>
#include <soc.h>
#include <zephyr/drivers/pinctrl.h>
#include <zephyr/logging/log.h>
#include <zephyr/pm/device.h>
#include <zephyr/pm/policy.h>
LOG_MODULE_REGISTER(eeprom_xec, CONFIG_EEPROM_LOG_LEVEL);
/* EEPROM Mode Register */
#define XEC_EEPROM_MODE_ACTIVATE BIT(0)
/* EEPROM Status Register */
#define XEC_EEPROM_STS_TRANSFER_COMPL BIT(0)
/* EEPROM Execute Register - Transfer size bit position */
#define XEC_EEPROM_EXC_TRANSFER_SZ_BITPOS (24)
/* EEPROM Execute Register - Commands */
#define XEC_EEPROM_EXC_CMD_READ 0x00000U
#define XEC_EEPROM_EXC_CMD_WRITE 0x10000U
#define XEC_EEPROM_EXC_CMD_READ_STS 0x20000U
#define XEC_EEPROM_EXC_CMD_WRITE_STS 0x30000U
/* EEPROM Execute Register - Address mask */
#define XEC_EEPROM_EXC_ADDR_MASK 0x7FFU
/* EEPROM Status Byte */
#define XEC_EEPROM_STS_BYTE_WIP BIT(0)
#define XEC_EEPROM_STS_BYTE_WENB BIT(1)
/* EEPROM Read/Write Transfer Size */
#define XEC_EEPROM_PAGE_SIZE 32U
#define XEC_EEPROM_TRANSFER_SIZE_READ XEC_EEPROM_PAGE_SIZE
#define XEC_EEPROM_TRANSFER_SIZE_WRITE XEC_EEPROM_PAGE_SIZE
#define XEC_EEPROM_DELAY_US 500U
#define XEC_EEPROM_DELAY_BUSY_POLL_US 50U
#define XEC_EEPROM_XFER_COMPL_RETRY_COUNT 10U
struct eeprom_xec_regs {
uint32_t mode;
uint32_t execute;
uint32_t status;
uint32_t intr_enable;
uint32_t password;
uint32_t unlock;
uint32_t lock;
uint32_t _reserved;
uint8_t buffer[XEC_EEPROM_PAGE_SIZE];
};
struct eeprom_xec_config {
struct eeprom_xec_regs * const regs;
size_t size;
const struct pinctrl_dev_config *pcfg;
};
struct eeprom_xec_data {
struct k_mutex lock_mtx;
};
static void eeprom_xec_execute_reg_set(struct eeprom_xec_regs * const regs,
uint32_t transfer_size, uint32_t command,
uint16_t eeprom_addr)
{
uint32_t temp = command + (eeprom_addr & XEC_EEPROM_EXC_ADDR_MASK);
if (transfer_size != XEC_EEPROM_PAGE_SIZE) {
temp += (transfer_size << XEC_EEPROM_EXC_TRANSFER_SZ_BITPOS);
}
regs->execute = temp;
}
static uint8_t eeprom_xec_data_buffer_read(struct eeprom_xec_regs * const regs,
uint8_t transfer_size, uint8_t *destination_ptr)
{
uint8_t count;
if (transfer_size > XEC_EEPROM_PAGE_SIZE) {
transfer_size = XEC_EEPROM_PAGE_SIZE;
}
for (count = 0; count < transfer_size; count++) {
*destination_ptr = regs->buffer[count];
destination_ptr++;
}
return transfer_size;
}
static uint8_t eeprom_xec_data_buffer_write(struct eeprom_xec_regs * const regs,
uint8_t transfer_size, uint8_t *source_ptr)
{
uint8_t count;
if (transfer_size > XEC_EEPROM_PAGE_SIZE) {
transfer_size = XEC_EEPROM_PAGE_SIZE;
}
for (count = 0; count < transfer_size; count++) {
regs->buffer[count] = *source_ptr;
source_ptr++;
}
return transfer_size;
}
static void eeprom_xec_wait_transfer_compl(struct eeprom_xec_regs * const regs)
{
uint8_t sts = 0;
uint8_t retry_count = 0;
k_sleep(K_USEC(XEC_EEPROM_DELAY_US));
do {
if (retry_count >= XEC_EEPROM_XFER_COMPL_RETRY_COUNT) {
LOG_ERR("XEC EEPROM retry count exceeded");
break;
}
k_sleep(K_USEC(XEC_EEPROM_DELAY_BUSY_POLL_US));
sts = XEC_EEPROM_STS_TRANSFER_COMPL & regs->status;
retry_count++;
} while (sts == 0);
if (sts != 0) {
/* Clear the appropriate status bits */
regs->status = XEC_EEPROM_STS_TRANSFER_COMPL;
}
}
static void eeprom_xec_wait_write_compl(struct eeprom_xec_regs * const regs)
{
uint8_t sts = 0;
uint8_t retry_count = 0;
do {
if (retry_count >= XEC_EEPROM_XFER_COMPL_RETRY_COUNT) {
LOG_ERR("XEC EEPROM retry count exceeded");
break;
}
regs->buffer[0] = 0;
/* Issue the READ_STS command */
regs->execute = XEC_EEPROM_EXC_CMD_READ_STS;
eeprom_xec_wait_transfer_compl(regs);
sts = regs->buffer[0] & (XEC_EEPROM_STS_BYTE_WIP |
XEC_EEPROM_STS_BYTE_WENB);
retry_count++;
} while (sts != 0);
}
static void eeprom_xec_data_read_32_bytes(struct eeprom_xec_regs * const regs,
uint8_t *buf, size_t len, off_t offset)
{
/* Issue the READ command to transfer buffer to EEPROM memory */
eeprom_xec_execute_reg_set(regs, len, XEC_EEPROM_EXC_CMD_READ, offset);
/* Wait until the read operation has completed */
eeprom_xec_wait_transfer_compl(regs);
/* Read the data in to the software buffer */
eeprom_xec_data_buffer_read(regs, len, buf);
}
static void eeprom_xec_data_write_32_bytes(struct eeprom_xec_regs * const regs,
uint8_t *buf, size_t len, off_t offset)
{
uint16_t sz;
uint16_t rem_bytes;
sz = offset % XEC_EEPROM_PAGE_SIZE;
/* If EEPROM Addr is not on page boundary */
if (sz != 0) {
/* Check if we are crossing page boundary */
if ((sz + len) > XEC_EEPROM_PAGE_SIZE) {
rem_bytes = (XEC_EEPROM_PAGE_SIZE - sz);
/* Update the EEPROM buffer */
eeprom_xec_data_buffer_write(regs, rem_bytes, buf);
/* Issue the WRITE command to transfer buffer to EEPROM memory */
eeprom_xec_execute_reg_set(regs, rem_bytes,
XEC_EEPROM_EXC_CMD_WRITE, offset);
eeprom_xec_wait_transfer_compl(regs);
eeprom_xec_wait_write_compl(regs);
offset += rem_bytes;
buf += rem_bytes;
len = (len - rem_bytes);
}
}
/* Update the EEPROM buffer */
eeprom_xec_data_buffer_write(regs, len, buf);
/* Issue the WRITE command to transfer buffer to EEPROM memory */
eeprom_xec_execute_reg_set(regs, len, XEC_EEPROM_EXC_CMD_WRITE, offset);
eeprom_xec_wait_transfer_compl(regs);
eeprom_xec_wait_write_compl(regs);
}
static int eeprom_xec_read(const struct device *dev, off_t offset,
void *buf,
size_t len)
{
const struct eeprom_xec_config *config = dev->config;
struct eeprom_xec_data * const data = dev->data;
struct eeprom_xec_regs * const regs = config->regs;
uint8_t *data_buf = (uint8_t *)buf;
uint32_t chunk_idx = 0;
uint32_t chunk_size = XEC_EEPROM_TRANSFER_SIZE_READ;
if (len == 0) {
return 0;
}
if ((offset + len) > config->size) {
LOG_WRN("attempt to read past device boundary");
return -EINVAL;
}
k_mutex_lock(&data->lock_mtx, K_FOREVER);
pm_policy_state_lock_get(PM_STATE_SUSPEND_TO_IDLE, PM_ALL_SUBSTATES);
/* EEPROM HW READ */
for (chunk_idx = 0; chunk_idx < len; chunk_idx += XEC_EEPROM_TRANSFER_SIZE_READ) {
if ((len-chunk_idx) < XEC_EEPROM_TRANSFER_SIZE_READ) {
chunk_size = (len-chunk_idx);
}
eeprom_xec_data_read_32_bytes(regs, &data_buf[chunk_idx],
chunk_size, (offset+chunk_idx));
}
pm_policy_state_lock_put(PM_STATE_SUSPEND_TO_IDLE, PM_ALL_SUBSTATES);
k_mutex_unlock(&data->lock_mtx);
return 0;
}
static int eeprom_xec_write(const struct device *dev, off_t offset,
const void *buf, size_t len)
{
const struct eeprom_xec_config *config = dev->config;
struct eeprom_xec_data * const data = dev->data;
struct eeprom_xec_regs * const regs = config->regs;
uint8_t *data_buf = (uint8_t *)buf;
uint32_t chunk_idx = 0;
uint32_t chunk_size = XEC_EEPROM_TRANSFER_SIZE_WRITE;
if (len == 0) {
return 0;
}
if ((offset + len) > config->size) {
LOG_WRN("attempt to write past device boundary");
return -EINVAL;
}
k_mutex_lock(&data->lock_mtx, K_FOREVER);
pm_policy_state_lock_get(PM_STATE_SUSPEND_TO_IDLE, PM_ALL_SUBSTATES);
/* EEPROM HW WRITE */
for (chunk_idx = 0; chunk_idx < len; chunk_idx += XEC_EEPROM_TRANSFER_SIZE_WRITE) {
if ((len-chunk_idx) < XEC_EEPROM_TRANSFER_SIZE_WRITE) {
chunk_size = (len-chunk_idx);
}
eeprom_xec_data_write_32_bytes(regs, &data_buf[chunk_idx],
chunk_size, (offset+chunk_idx));
}
pm_policy_state_lock_put(PM_STATE_SUSPEND_TO_IDLE, PM_ALL_SUBSTATES);
k_mutex_unlock(&data->lock_mtx);
return 0;
}
static size_t eeprom_xec_size(const struct device *dev)
{
const struct eeprom_xec_config *config = dev->config;
return config->size;
}
#ifdef CONFIG_PM_DEVICE
static int eeprom_xec_pm_action(const struct device *dev, enum pm_device_action action)
{
const struct eeprom_xec_config *const devcfg = dev->config;
struct eeprom_xec_regs * const regs = devcfg->regs;
int ret;
switch (action) {
case PM_DEVICE_ACTION_RESUME:
ret = pinctrl_apply_state(devcfg->pcfg, PINCTRL_STATE_DEFAULT);
if (ret != 0) {
LOG_ERR("XEC EEPROM pinctrl setup failed (%d)", ret);
return ret;
}
regs->mode |= XEC_EEPROM_MODE_ACTIVATE;
break;
case PM_DEVICE_ACTION_SUSPEND:
/* Disable EEPROM Controller */
regs->mode &= (~XEC_EEPROM_MODE_ACTIVATE);
ret = pinctrl_apply_state(devcfg->pcfg, PINCTRL_STATE_SLEEP);
/* pinctrl-1 does not exist. */
if (ret == -ENOENT) {
ret = 0;
}
break;
default:
ret = -ENOTSUP;
}
return ret;
}
#endif /* CONFIG_PM_DEVICE */
static int eeprom_xec_init(const struct device *dev)
{
const struct eeprom_xec_config *config = dev->config;
struct eeprom_xec_data * const data = dev->data;
struct eeprom_xec_regs * const regs = config->regs;
k_mutex_init(&data->lock_mtx);
int ret = pinctrl_apply_state(config->pcfg, PINCTRL_STATE_DEFAULT);
if (ret != 0) {
LOG_ERR("XEC EEPROM pinctrl init failed (%d)", ret);
return ret;
}
regs->mode |= XEC_EEPROM_MODE_ACTIVATE;
return 0;
}
static const struct eeprom_driver_api eeprom_xec_api = {
.read = eeprom_xec_read,
.write = eeprom_xec_write,
.size = eeprom_xec_size,
};
PINCTRL_DT_INST_DEFINE(0);
static const struct eeprom_xec_config eeprom_config = {
.regs = (struct eeprom_xec_regs * const)DT_INST_REG_ADDR(0),
.size = DT_INST_PROP(0, size),
.pcfg = PINCTRL_DT_INST_DEV_CONFIG_GET(0),
};
static struct eeprom_xec_data eeprom_data;
PM_DEVICE_DT_INST_DEFINE(0, eeprom_xec_pm_action);
DEVICE_DT_INST_DEFINE(0, &eeprom_xec_init, PM_DEVICE_DT_INST_GET(0), &eeprom_data,
&eeprom_config, POST_KERNEL,
CONFIG_EEPROM_INIT_PRIORITY, &eeprom_xec_api);
``` | /content/code_sandbox/drivers/eeprom/eeprom_mchp_xec.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 2,811 |
```c
/*
*
*/
#define DT_DRV_COMPAT atmel_at24
#define LOG_LEVEL CONFIG_I2C_LOG_LEVEL
#include <zephyr/logging/log.h>
LOG_MODULE_REGISTER(atmel_at24);
#include <zephyr/device.h>
#include <zephyr/drivers/emul.h>
#include <zephyr/drivers/i2c.h>
#include <zephyr/drivers/i2c_emul.h>
/** Run-time data used by the emulator */
struct at24_emul_data {
/** I2C emulator detail */
struct i2c_emul emul;
/** AT24 device being emulated */
const struct device *i2c;
/** Current register to read (address) */
uint32_t cur_reg;
};
/** Static configuration for the emulator */
struct at24_emul_cfg {
/** EEPROM data contents */
uint8_t *buf;
/** Size of EEPROM in bytes */
uint32_t size;
/** Address of EEPROM on i2c bus */
uint16_t addr;
/** Address width for EEPROM in bits (only 8 is supported at present) */
uint8_t addr_width;
};
/**
* Emulator an I2C transfer to an AT24 chip
*
* This handles simple reads and writes
*
* @param emul I2C emulation information
* @param msgs List of messages to process. For 'read' messages, this function
* updates the 'buf' member with the data that was read
* @param num_msgs Number of messages to process
* @param addr Address of the I2C target device. This is assumed to be correct,
* due to the
* @retval 0 If successful
* @retval -EIO General input / output error
*/
static int at24_emul_transfer(const struct emul *target, struct i2c_msg *msgs,
int num_msgs, int addr)
{
struct at24_emul_data *data;
const struct at24_emul_cfg *cfg;
unsigned int len;
bool too_fast;
uint32_t i2c_cfg;
data = target->data;
cfg = target->cfg;
if (cfg->addr != addr) {
LOG_ERR("Address mismatch, expected %02x, got %02x", cfg->addr,
addr);
return -EIO;
}
if (i2c_get_config(data->i2c, &i2c_cfg)) {
LOG_ERR("i2c_get_config failed");
return -EIO;
}
/* For testing purposes, fail if the bus speed is above standard */
too_fast = (I2C_SPEED_GET(i2c_cfg) > I2C_SPEED_STANDARD);
if (too_fast) {
LOG_ERR("Speed too high");
return -EIO;
}
i2c_dump_msgs_rw(target->dev, msgs, num_msgs, addr, false);
switch (num_msgs) {
case 1:
if (msgs->flags & I2C_MSG_READ) {
/* handle read */
break;
}
data->cur_reg = msgs->buf[0];
len = MIN(msgs->len - 1, cfg->size - data->cur_reg);
memcpy(&cfg->buf[data->cur_reg], &msgs->buf[1], len);
return 0;
case 2:
if (msgs->flags & I2C_MSG_READ) {
LOG_ERR("Unexpected read");
return -EIO;
}
data->cur_reg = msgs->buf[0];
/* Now process the 'read' part of the message */
msgs++;
if (!(msgs->flags & I2C_MSG_READ)) {
LOG_ERR("Unexpected write");
return -EIO;
}
break;
default:
LOG_ERR("Invalid number of messages");
return -EIO;
}
/* Read data from the EEPROM into the buffer */
len = MIN(msgs->len, cfg->size - data->cur_reg);
memcpy(msgs->buf, &cfg->buf[data->cur_reg], len);
data->cur_reg += len;
return 0;
}
/* Device instantiation */
static struct i2c_emul_api bus_api = {
.transfer = at24_emul_transfer,
};
/**
* Set up a new AT24 emulator
*
* This should be called for each AT24 device that needs to be emulated. It
* registers it with the I2C emulation controller.
*
* @param target Emulation information
* @param parent Device to emulate (must use AT24 driver)
* @return 0 indicating success (always)
*/
static int emul_atmel_at24_init(const struct emul *target, const struct device *parent)
{
const struct at24_emul_cfg *cfg = target->cfg;
struct at24_emul_data *data = target->data;
data->emul.api = &bus_api;
data->emul.addr = cfg->addr;
data->emul.target = target;
data->i2c = parent;
data->cur_reg = 0;
/* Start with an erased EEPROM, assuming all 0xff */
memset(cfg->buf, 0xff, cfg->size);
return 0;
}
#define EEPROM_AT24_EMUL(n) \
static uint8_t at24_emul_buf_##n[DT_INST_PROP(n, size)]; \
static struct at24_emul_data at24_emul_data_##n; \
static const struct at24_emul_cfg at24_emul_cfg_##n = { \
.buf = at24_emul_buf_##n, \
.size = DT_INST_PROP(n, size), \
.addr = DT_INST_REG_ADDR(n), \
.addr_width = 8, \
}; \
EMUL_DT_INST_DEFINE(n, emul_atmel_at24_init, &at24_emul_data_##n, &at24_emul_cfg_##n, \
&bus_api, NULL)
DT_INST_FOREACH_STATUS_OKAY(EEPROM_AT24_EMUL)
``` | /content/code_sandbox/drivers/eeprom/eeprom_at2x_emul.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 1,265 |
```objective-c
/* ieee802154_cc1200.h - Registers definition for TI CC1200 */
/*
*
*/
#ifndef ZEPHYR_DRIVERS_IEEE802154_IEEE802154_CC1200_H_
#define ZEPHYR_DRIVERS_IEEE802154_IEEE802154_CC1200_H_
#include <zephyr/linker/sections.h>
#include <zephyr/sys/atomic.h>
#include <zephyr/drivers/gpio.h>
#include <zephyr/drivers/spi.h>
#include <zephyr/drivers/ieee802154/cc1200.h>
/* Compile time config structure
*******************************
*/
/* Note for EMK & EM adapter booster pack users:
* SPI pins are easy, RESET as well, but when it comes to GPIO:
* CHIP -> EM adapter
* GPIO0 -> GPIOA
* GPIO1 -> reserved (it's SPI MISO)
* GPIO2 -> GPIOB
* GPIO3 -> GPIO3
*/
struct cc1200_config {
struct spi_dt_spec bus;
struct gpio_dt_spec interrupt;
};
/* Runtime context structure
***************************
*/
struct cc1200_context {
struct net_if *iface;
/**************************/
struct gpio_callback rx_tx_cb;
uint8_t mac_addr[8];
/************RF************/
const struct cc1200_rf_registers_set *rf_settings;
/************TX************/
struct k_sem tx_sync;
atomic_t tx;
atomic_t tx_start;
/************RX************/
K_KERNEL_STACK_MEMBER(rx_stack,
CONFIG_IEEE802154_CC1200_RX_STACK_SIZE);
struct k_thread rx_thread;
struct k_sem rx_lock;
atomic_t rx;
};
#include "ieee802154_cc1200_regs.h"
/* Registers useful routines
***************************
*/
bool z_cc1200_access_reg(const struct device *dev, bool read, uint8_t addr,
void *data, size_t length, bool extended, bool burst);
static inline uint8_t cc1200_read_single_reg(const struct device *dev,
uint8_t addr, bool extended)
{
uint8_t val;
if (z_cc1200_access_reg(dev, true, addr, &val, 1, extended, false)) {
return val;
}
return 0;
}
static inline bool cc1200_write_single_reg(const struct device *dev,
uint8_t addr, uint8_t val, bool extended)
{
return z_cc1200_access_reg(dev, false, addr, &val, 1, extended, false);
}
static inline bool cc1200_instruct(const struct device *dev, uint8_t addr)
{
return z_cc1200_access_reg(dev, false, addr, NULL, 0, false, false);
}
#define DEFINE_REG_READ(__reg_name, __reg_addr, __ext) \
static inline uint8_t read_reg_##__reg_name(const struct device *dev) \
{ \
return cc1200_read_single_reg(dev, __reg_addr, __ext); \
}
#define DEFINE_REG_WRITE(__reg_name, __reg_addr, __ext) \
static inline bool write_reg_##__reg_name(const struct device *dev, \
uint8_t val) \
{ \
return cc1200_write_single_reg(dev, __reg_addr, \
val, __ext); \
}
DEFINE_REG_WRITE(iocfg3, CC1200_REG_IOCFG3, false)
DEFINE_REG_WRITE(iocfg2, CC1200_REG_IOCFG2, false)
DEFINE_REG_WRITE(iocfg0, CC1200_REG_IOCFG0, false)
DEFINE_REG_WRITE(pa_cfg1, CC1200_REG_PA_CFG1, false)
DEFINE_REG_WRITE(pkt_len, CC1200_REG_PKT_LEN, false)
DEFINE_REG_READ(fs_cfg, CC1200_REG_FS_CFG, false)
DEFINE_REG_READ(rssi0, CC1200_REG_RSSI0, true)
DEFINE_REG_READ(pa_cfg1, CC1200_REG_PA_CFG1, false)
DEFINE_REG_READ(num_txbytes, CC1200_REG_NUM_TXBYTES, true)
DEFINE_REG_READ(num_rxbytes, CC1200_REG_NUM_RXBYTES, true)
/* Instructions useful routines
******************************
*/
#define DEFINE_STROBE_INSTRUCTION(__ins_name, __ins_addr) \
static inline bool instruct_##__ins_name(const struct device *dev) \
{ \
return cc1200_instruct(dev, __ins_addr); \
}
DEFINE_STROBE_INSTRUCTION(sres, CC1200_INS_SRES)
DEFINE_STROBE_INSTRUCTION(sfstxon, CC1200_INS_SFSTXON)
DEFINE_STROBE_INSTRUCTION(sxoff, CC1200_INS_SXOFF)
DEFINE_STROBE_INSTRUCTION(scal, CC1200_INS_SCAL)
DEFINE_STROBE_INSTRUCTION(srx, CC1200_INS_SRX)
DEFINE_STROBE_INSTRUCTION(stx, CC1200_INS_STX)
DEFINE_STROBE_INSTRUCTION(sidle, CC1200_INS_SIDLE)
DEFINE_STROBE_INSTRUCTION(safc, CC1200_INS_SAFC)
DEFINE_STROBE_INSTRUCTION(swor, CC1200_INS_SWOR)
DEFINE_STROBE_INSTRUCTION(spwd, CC1200_INS_SPWD)
DEFINE_STROBE_INSTRUCTION(sfrx, CC1200_INS_SFRX)
DEFINE_STROBE_INSTRUCTION(sftx, CC1200_INS_SFTX)
DEFINE_STROBE_INSTRUCTION(sworrst, CC1200_INS_SWORRST)
DEFINE_STROBE_INSTRUCTION(snop, CC1200_INS_SNOP)
#define CC1200_INVALID_RSSI INT8_MIN
#endif /* ZEPHYR_DRIVERS_IEEE802154_IEEE802154_CC1200_H_ */
``` | /content/code_sandbox/drivers/ieee802154/ieee802154_cc1200.h | objective-c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 1,186 |
```c
/* ieee802154_rf2xx_iface.c - ATMEL RF2XX IEEE 802.15.4 Interface */
/*
*
*/
#define LOG_MODULE_NAME ieee802154_rf2xx_iface
#define LOG_LEVEL CONFIG_IEEE802154_DRIVER_LOG_LEVEL
#include <zephyr/logging/log.h>
LOG_MODULE_REGISTER(LOG_MODULE_NAME);
#include <errno.h>
#include <zephyr/device.h>
#include <zephyr/drivers/spi.h>
#include <zephyr/drivers/gpio.h>
#include <zephyr/net/ieee802154_radio.h>
#include "ieee802154_rf2xx.h"
#include "ieee802154_rf2xx_regs.h"
#include "ieee802154_rf2xx_iface.h"
void rf2xx_iface_phy_rst(const struct device *dev)
{
const struct rf2xx_config *conf = dev->config;
/* Ensure control lines have correct levels. */
gpio_pin_set_dt(&conf->reset_gpio, 0);
gpio_pin_set_dt(&conf->slptr_gpio, 0);
/* Wait typical time of timer TR1. */
k_busy_wait(330);
gpio_pin_set_dt(&conf->reset_gpio, 1);
k_busy_wait(10);
gpio_pin_set_dt(&conf->reset_gpio, 0);
}
void rf2xx_iface_phy_tx_start(const struct device *dev)
{
const struct rf2xx_config *conf = dev->config;
/* Start TX transmission at rise edge */
gpio_pin_set_dt(&conf->slptr_gpio, 1);
/* 16.125[s] delay to detect signal */
k_busy_wait(20);
/* restore initial pin state */
gpio_pin_set_dt(&conf->slptr_gpio, 0);
}
uint8_t rf2xx_iface_reg_read(const struct device *dev,
uint8_t addr)
{
const struct rf2xx_config *conf = dev->config;
uint8_t status;
uint8_t regval = 0;
addr |= RF2XX_RF_CMD_REG_R;
const struct spi_buf tx_buf = {
.buf = &addr,
.len = 1
};
const struct spi_buf_set tx = {
.buffers = &tx_buf,
.count = 1
};
const struct spi_buf rx_buf[2] = {
{
.buf = &status,
.len = 1
},
{
.buf = ®val,
.len = 1
},
};
const struct spi_buf_set rx = {
.buffers = rx_buf,
.count = 2
};
if (spi_transceive_dt(&conf->spi, &tx, &rx) != 0) {
LOG_ERR("Failed to exec rf2xx_reg_read CMD at address %d",
addr);
}
LOG_DBG("Read Address: %02X, PhyStatus: %02X, RegVal: %02X",
(addr & ~(RF2XX_RF_CMD_REG_R)), status, regval);
return regval;
}
void rf2xx_iface_reg_write(const struct device *dev,
uint8_t addr,
uint8_t data)
{
const struct rf2xx_config *conf = dev->config;
uint8_t status;
addr |= RF2XX_RF_CMD_REG_W;
const struct spi_buf tx_buf[2] = {
{
.buf = &addr,
.len = 1
},
{
.buf = &data,
.len = 1
}
};
const struct spi_buf_set tx = {
.buffers = tx_buf,
.count = 2
};
const struct spi_buf rx_buf = {
.buf = &status,
.len = 1
};
const struct spi_buf_set rx = {
.buffers = &rx_buf,
.count = 1
};
if (spi_transceive_dt(&conf->spi, &tx, &rx) != 0) {
LOG_ERR("Failed to exec rf2xx_reg_write at address %d",
addr);
}
LOG_DBG("Write Address: %02X, PhyStatus: %02X, RegVal: %02X",
(addr & ~(RF2XX_RF_CMD_REG_W)), status, data);
}
uint8_t rf2xx_iface_bit_read(const struct device *dev,
uint8_t addr,
uint8_t mask,
uint8_t pos)
{
uint8_t ret;
ret = rf2xx_iface_reg_read(dev, addr);
ret &= mask;
ret >>= pos;
return ret;
}
void rf2xx_iface_bit_write(const struct device *dev,
uint8_t reg_addr,
uint8_t mask,
uint8_t pos,
uint8_t new_value)
{
uint8_t current_reg_value;
current_reg_value = rf2xx_iface_reg_read(dev, reg_addr);
current_reg_value &= ~mask;
new_value <<= pos;
new_value &= mask;
new_value |= current_reg_value;
rf2xx_iface_reg_write(dev, reg_addr, new_value);
}
void rf2xx_iface_frame_read(const struct device *dev,
uint8_t *data,
uint8_t length)
{
const struct rf2xx_config *conf = dev->config;
uint8_t cmd = RF2XX_RF_CMD_FRAME_R;
const struct spi_buf tx_buf = {
.buf = &cmd,
.len = 1
};
const struct spi_buf_set tx = {
.buffers = &tx_buf,
.count = 1
};
const struct spi_buf rx_buf = {
.buf = data,
.len = length
};
const struct spi_buf_set rx = {
.buffers = &rx_buf,
.count = 1
};
if (spi_transceive_dt(&conf->spi, &tx, &rx) != 0) {
LOG_ERR("Failed to exec rf2xx_frame_read PHR");
}
LOG_DBG("Frame R: PhyStatus: %02X. length: %02X", data[0], length);
LOG_HEXDUMP_DBG(data + RX2XX_FRAME_HEADER_SIZE, length, "payload");
}
void rf2xx_iface_frame_write(const struct device *dev,
uint8_t *data,
uint8_t length)
{
const struct rf2xx_config *conf = dev->config;
uint8_t cmd = RF2XX_RF_CMD_FRAME_W;
uint8_t status;
uint8_t phr;
/* Sanity check */
if (length > 125) {
length = 125;
}
phr = length + RX2XX_FRAME_FCS_LENGTH;
const struct spi_buf tx_buf[3] = {
{
.buf = &cmd,
.len = 1
},
{
.buf = &phr, /* PHR */
.len = 1
},
{
.buf = data, /* PSDU */
.len = length
},
};
const struct spi_buf_set tx = {
.buffers = tx_buf,
.count = 3
};
const struct spi_buf rx_buf = {
.buf = &status,
.len = 1
};
const struct spi_buf_set rx = {
.buffers = &rx_buf,
.count = 1
};
if (spi_transceive_dt(&conf->spi, &tx, &rx) != 0) {
LOG_ERR("Failed to exec rf2xx_frame_write");
}
LOG_DBG("Frame W: PhyStatus: %02X. length: %02X", status, length);
LOG_HEXDUMP_DBG(data, length, "payload");
}
void rf2xx_iface_sram_read(const struct device *dev,
uint8_t address,
uint8_t *data,
uint8_t length)
{
const struct rf2xx_config *conf = dev->config;
uint8_t cmd = RF2XX_RF_CMD_SRAM_R;
uint8_t status[2];
const struct spi_buf tx_buf[2] = {
{
.buf = &cmd,
.len = 1
},
{
.buf = &address,
.len = 1
},
};
const struct spi_buf_set tx = {
.buffers = tx_buf,
.count = 2
};
const struct spi_buf rx_buf[2] = {
{
.buf = status,
.len = 2
},
{
.buf = data,
.len = length
},
};
const struct spi_buf_set rx = {
.buffers = rx_buf,
.count = 2
};
if (spi_transceive_dt(&conf->spi, &tx, &rx) != 0) {
LOG_ERR("Failed to exec rf2xx_sram_read");
}
LOG_DBG("SRAM R: length: %02X, status: %02X", length, status[0]);
LOG_HEXDUMP_DBG(data, length, "content");
}
``` | /content/code_sandbox/drivers/ieee802154/ieee802154_rf2xx_iface.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 1,926 |
```c
/*
*
*/
#define DT_DRV_COMPAT zephyr_ieee802154_uart_pipe
#define LOG_MODULE_NAME ieee802154_uart_pipe
#define LOG_LEVEL CONFIG_IEEE802154_DRIVER_LOG_LEVEL
#include <zephyr/logging/log.h>
LOG_MODULE_REGISTER(LOG_MODULE_NAME);
#include <errno.h>
#include <zephyr/kernel.h>
#include <zephyr/arch/cpu.h>
#include <zephyr/device.h>
#include <zephyr/init.h>
#include <zephyr/net/net_if.h>
#include <zephyr/net/net_pkt.h>
#include <zephyr/random/random.h>
#include <zephyr/drivers/uart_pipe.h>
#include <zephyr/net/ieee802154_radio.h>
#include "ieee802154_uart_pipe.h"
#define PAN_ID_OFFSET 3 /* Pan Id offset */
#define DEST_ADDR_OFFSET 5 /* Destination offset address*/
#define DEST_ADDR_TYPE_OFFSET 1 /* Destination address type */
#define DEST_ADDR_TYPE_MASK 0x0c /* Mask for destination address type */
#define DEST_ADDR_TYPE_SHORT 0x08 /* Short destination address type */
#define DEST_ADDR_TYPE_EXTENDED 0x0c /* Extended destination address type */
#define PAN_ID_SIZE 2 /* Size of Pan Id */
#define SHORT_ADDRESS_SIZE 2 /* Size of Short Mac Address */
#define EXTENDED_ADDRESS_SIZE 8 /* Size of Extended Mac Address */
/* Broadcast Short Address */
#define BROADCAST_ADDRESS ((uint8_t [SHORT_ADDRESS_SIZE]) {0xff, 0xff})
static uint8_t dev_pan_id[PAN_ID_SIZE]; /* Device Pan Id */
static uint8_t dev_short_addr[SHORT_ADDRESS_SIZE]; /* Device Short Address */
static uint8_t dev_ext_addr[EXTENDED_ADDRESS_SIZE]; /* Device Extended Address */
/** Singleton device used in uart pipe callback */
static const struct device *upipe_dev;
#if defined(CONFIG_IEEE802154_UPIPE_HW_FILTER)
static bool received_dest_addr_matched(uint8_t *rx_buffer)
{
struct upipe_context *upipe = upipe_dev->data;
/* Check destination PAN Id */
if (memcmp(&rx_buffer[PAN_ID_OFFSET],
dev_pan_id, PAN_ID_SIZE) != 0 &&
memcmp(&rx_buffer[PAN_ID_OFFSET],
BROADCAST_ADDRESS, PAN_ID_SIZE) != 0) {
return false;
}
/* Check destination address */
switch (rx_buffer[DEST_ADDR_TYPE_OFFSET] & DEST_ADDR_TYPE_MASK) {
case DEST_ADDR_TYPE_SHORT:
/* First check if the destination is broadcast */
/* If not broadcast, check if length and address matches */
if (memcmp(&rx_buffer[DEST_ADDR_OFFSET],
BROADCAST_ADDRESS,
SHORT_ADDRESS_SIZE) != 0 &&
(net_if_get_link_addr(upipe->iface)->len !=
SHORT_ADDRESS_SIZE ||
memcmp(&rx_buffer[DEST_ADDR_OFFSET],
dev_short_addr,
SHORT_ADDRESS_SIZE) != 0)) {
return false;
}
break;
case DEST_ADDR_TYPE_EXTENDED:
/* If not broadcast, check if length and address matches */
if (net_if_get_link_addr(upipe->iface)->len !=
EXTENDED_ADDRESS_SIZE ||
memcmp(&rx_buffer[DEST_ADDR_OFFSET],
dev_ext_addr, EXTENDED_ADDRESS_SIZE) != 0) {
return false;
}
break;
default:
return false;
}
return true;
}
#endif
static uint8_t *upipe_rx(uint8_t *buf, size_t *off)
{
struct net_pkt *pkt = NULL;
struct upipe_context *upipe;
if (!upipe_dev) {
goto done;
}
upipe = upipe_dev->data;
if (!upipe->rx && *buf == UART_PIPE_RADIO_15_4_FRAME_TYPE) {
upipe->rx = true;
goto done;
}
if (!upipe->rx_len) {
if (*buf > IEEE802154_MAX_PHY_PACKET_SIZE) {
goto flush;
}
upipe->rx_len = *buf;
goto done;
}
upipe->rx_buf[upipe->rx_off++] = *buf;
if (upipe->rx_len == upipe->rx_off) {
pkt = net_pkt_rx_alloc_with_buffer(upipe->iface, upipe->rx_len,
AF_UNSPEC, 0, K_NO_WAIT);
if (!pkt) {
LOG_DBG("No pkt available");
goto flush;
}
if (net_pkt_write(pkt, upipe->rx_buf, upipe->rx_len)) {
LOG_DBG("No content read?");
goto out;
}
#if defined(CONFIG_IEEE802154_UPIPE_HW_FILTER)
if (received_dest_addr_matched(pkt->buffer->data) == false) {
LOG_DBG("Packet received is not addressed to me");
goto out;
}
#endif
if (ieee802154_handle_ack(upipe->iface, pkt) == NET_OK) {
LOG_DBG("ACK packet handled");
goto out;
}
LOG_DBG("Caught a packet (%u)", upipe->rx_len);
if (net_recv_data(upipe->iface, pkt) < 0) {
LOG_DBG("Packet dropped by NET stack");
goto out;
}
goto flush;
out:
net_pkt_unref(pkt);
flush:
upipe->rx = false;
upipe->rx_len = 0U;
upipe->rx_off = 0U;
}
done:
*off = 0;
return buf;
}
static enum ieee802154_hw_caps upipe_get_capabilities(const struct device *dev)
{
return IEEE802154_HW_FCS | IEEE802154_HW_FILTER;
}
static int upipe_cca(const struct device *dev)
{
struct upipe_context *upipe = dev->data;
if (upipe->stopped) {
return -EIO;
}
return 0;
}
static int upipe_set_channel(const struct device *dev, uint16_t channel)
{
ARG_UNUSED(dev);
ARG_UNUSED(channel);
return 0;
}
static int upipe_set_pan_id(const struct device *dev, uint16_t pan_id)
{
uint8_t pan_id_le[2];
ARG_UNUSED(dev);
sys_put_le16(pan_id, pan_id_le);
memcpy(dev_pan_id, pan_id_le, PAN_ID_SIZE);
return 0;
}
static int upipe_set_short_addr(const struct device *dev, uint16_t short_addr)
{
uint8_t short_addr_le[2];
ARG_UNUSED(dev);
sys_put_le16(short_addr, short_addr_le);
memcpy(dev_short_addr, short_addr_le, SHORT_ADDRESS_SIZE);
return 0;
}
static int upipe_set_ieee_addr(const struct device *dev,
const uint8_t *ieee_addr)
{
ARG_UNUSED(dev);
memcpy(dev_ext_addr, ieee_addr, EXTENDED_ADDRESS_SIZE);
return 0;
}
static int upipe_filter(const struct device *dev,
bool set,
enum ieee802154_filter_type type,
const struct ieee802154_filter *filter)
{
LOG_DBG("Applying filter %u", type);
if (!set) {
return -ENOTSUP;
}
if (type == IEEE802154_FILTER_TYPE_IEEE_ADDR) {
return upipe_set_ieee_addr(dev, filter->ieee_addr);
} else if (type == IEEE802154_FILTER_TYPE_SHORT_ADDR) {
return upipe_set_short_addr(dev, filter->short_addr);
} else if (type == IEEE802154_FILTER_TYPE_PAN_ID) {
return upipe_set_pan_id(dev, filter->pan_id);
}
return -ENOTSUP;
}
static int upipe_set_txpower(const struct device *dev, int16_t dbm)
{
ARG_UNUSED(dev);
ARG_UNUSED(dbm);
return 0;
}
static int upipe_tx(const struct device *dev,
enum ieee802154_tx_mode mode,
struct net_pkt *pkt,
struct net_buf *frag)
{
struct upipe_context *upipe = dev->data;
uint8_t *pkt_buf = frag->data;
uint8_t len = frag->len;
uint8_t i, data;
if (mode != IEEE802154_TX_MODE_DIRECT) {
NET_ERR("TX mode %d not supported", mode);
return -ENOTSUP;
}
LOG_DBG("%p (%u)", frag, len);
if (upipe->stopped) {
return -EIO;
}
data = UART_PIPE_RADIO_15_4_FRAME_TYPE;
uart_pipe_send(&data, 1);
data = len;
uart_pipe_send(&data, 1);
for (i = 0U; i < len; i++) {
uart_pipe_send(pkt_buf+i, 1);
}
return 0;
}
static int upipe_start(const struct device *dev)
{
struct upipe_context *upipe = dev->data;
if (!upipe->stopped) {
return -EALREADY;
}
upipe->stopped = false;
return 0;
}
static int upipe_stop(const struct device *dev)
{
struct upipe_context *upipe = dev->data;
if (upipe->stopped) {
return -EALREADY;
}
upipe->stopped = true;
return 0;
}
/* driver-allocated attribute memory - constant across all driver instances */
IEEE802154_DEFINE_PHY_SUPPORTED_CHANNELS(drv_attr, 11, 26);
/* API implementation: attr_get */
static int upipe_attr_get(const struct device *dev, enum ieee802154_attr attr,
struct ieee802154_attr_value *value)
{
ARG_UNUSED(dev);
return ieee802154_attr_get_channel_page_and_range(
attr, IEEE802154_ATTR_PHY_CHANNEL_PAGE_ZERO_OQPSK_2450_BPSK_868_915,
&drv_attr.phy_supported_channels, value);
}
static int upipe_init(const struct device *dev)
{
struct upipe_context *upipe = dev->data;
(void)memset(upipe, 0, sizeof(struct upipe_context));
uart_pipe_register(upipe->uart_pipe_buf, 1, upipe_rx);
upipe_stop(dev);
return 0;
}
static inline uint8_t *get_mac(const struct device *dev)
{
struct upipe_context *upipe = dev->data;
upipe->mac_addr[0] = 0x00;
upipe->mac_addr[1] = 0x10;
upipe->mac_addr[2] = 0x20;
upipe->mac_addr[3] = 0x30;
#if defined(CONFIG_IEEE802154_UPIPE_RANDOM_MAC)
sys_rand_get(&upipe->mac_addr[4], 4U);
#else
upipe->mac_addr[4] = CONFIG_IEEE802154_UPIPE_MAC4;
upipe->mac_addr[5] = CONFIG_IEEE802154_UPIPE_MAC5;
upipe->mac_addr[6] = CONFIG_IEEE802154_UPIPE_MAC6;
upipe->mac_addr[7] = CONFIG_IEEE802154_UPIPE_MAC7;
#endif
return upipe->mac_addr;
}
static void upipe_iface_init(struct net_if *iface)
{
const struct device *dev = net_if_get_device(iface);
struct upipe_context *upipe = dev->data;
uint8_t *mac = get_mac(dev);
net_if_set_link_addr(iface, mac, 8, NET_LINK_IEEE802154);
upipe_dev = dev;
upipe->iface = iface;
ieee802154_init(iface);
}
static struct upipe_context upipe_context_data;
static const struct ieee802154_radio_api upipe_radio_api = {
.iface_api.init = upipe_iface_init,
.get_capabilities = upipe_get_capabilities,
.cca = upipe_cca,
.set_channel = upipe_set_channel,
.filter = upipe_filter,
.set_txpower = upipe_set_txpower,
.tx = upipe_tx,
.start = upipe_start,
.stop = upipe_stop,
.attr_get = upipe_attr_get,
};
NET_DEVICE_DT_INST_DEFINE(0, upipe_init, NULL, &upipe_context_data, NULL,
CONFIG_KERNEL_INIT_PRIORITY_DEFAULT, &upipe_radio_api,
IEEE802154_L2, NET_L2_GET_CTX_TYPE(IEEE802154_L2),
125);
``` | /content/code_sandbox/drivers/ieee802154/ieee802154_uart_pipe.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 2,626 |
```objective-c
/* ieee802154_rf2xx_iface.h - ATMEL RF2XX transceiver interface */
/*
*
*/
#ifndef ZEPHYR_DRIVERS_IEEE802154_IEEE802154_RF2XX_IFACE_H_
#define ZEPHYR_DRIVERS_IEEE802154_IEEE802154_RF2XX_IFACE_H_
/**
* @brief Resets the TRX radio
*
* @param[in] dev Transceiver device instance
*/
void rf2xx_iface_phy_rst(const struct device *dev);
/**
* @brief Start TX transmission
*
* @param[in] dev Transceiver device instance
*/
void rf2xx_iface_phy_tx_start(const struct device *dev);
/**
* @brief Reads current value from a transceiver register
*
* This function reads the current value from a transceiver register.
*
* @param[in] dev Transceiver device instance
* @param[in] addr Specifies the address of the trx register
* from which the data shall be read
*
* @return value of the register read
*/
uint8_t rf2xx_iface_reg_read(const struct device *dev,
uint8_t addr);
/**
* @brief Writes data into a transceiver register
*
* This function writes a value into transceiver register.
*
* @param[in] dev Transceiver device instance
* @param[in] addr Address of the trx register
* @param[in] data Data to be written to trx register
*
*/
void rf2xx_iface_reg_write(const struct device *dev,
uint8_t addr,
uint8_t data);
/**
* @brief Subregister read
*
* @param[in] dev Transceiver device instance
* @param[in] addr offset of the register
* @param[in] mask bit mask of the subregister
* @param[in] pos bit position of the subregister
*
* @return value of the read bit(s)
*/
uint8_t rf2xx_iface_bit_read(const struct device *dev,
uint8_t addr,
uint8_t mask,
uint8_t pos);
/**
* @brief Subregister write
*
* @param[in] dev Transceiver device instance
* @param[in] reg_addr Offset of the register
* @param[in] mask Bit mask of the subregister
* @param[in] pos Bit position of the subregister
* @param[out] new_value Data, which is muxed into the register
*/
void rf2xx_iface_bit_write(const struct device *dev,
uint8_t reg_addr,
uint8_t mask,
uint8_t pos,
uint8_t new_value);
/**
* @brief Reads frame buffer of the transceiver
*
* This function reads the frame buffer of the transceiver.
*
* @param[in] dev Transceiver device instance
* @param[out] data Pointer to the location to store frame
* @param[in] length Number of bytes to be read from the frame
*/
void rf2xx_iface_frame_read(const struct device *dev,
uint8_t *data,
uint8_t length);
/**
* @brief Writes data into frame buffer of the transceiver
*
* This function writes data into the frame buffer of the transceiver
*
* @param[in] dev Transceiver device instance
* @param[in] data Pointer to data to be written into frame buffer
* @param[in] length Number of bytes to be written into frame buffer
*/
void rf2xx_iface_frame_write(const struct device *dev,
uint8_t *data,
uint8_t length);
/**
* @brief Reads sram data from the transceiver
*
* This function reads the sram data of the transceiver.
*
* @param[in] dev Transceiver device instance
* @param[in] address Start address to be read
* @param[out] data Pointer to the location to store data
* @param[in] length Number of bytes to be read from the sram space
*/
void rf2xx_iface_sram_read(const struct device *dev,
uint8_t address,
uint8_t *data,
uint8_t length);
#endif /* ZEPHYR_DRIVERS_IEEE802154_IEEE802154_RF2XX_IFACE_H_ */
``` | /content/code_sandbox/drivers/ieee802154/ieee802154_rf2xx_iface.h | objective-c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 910 |
```objective-c
/* ieee802154_rf2xx.h - IEEE 802.15.4 Driver definition for ATMEL RF2XX */
/*
*
*/
#ifndef ZEPHYR_DRIVERS_IEEE802154_IEEE802154_RF2XX_H_
#define ZEPHYR_DRIVERS_IEEE802154_IEEE802154_RF2XX_H_
/* Runtime context structure
***************************
*/
enum rf2xx_trx_state_cmd_t {
RF2XX_TRX_PHY_STATE_CMD_NOP = 0x00,
RF2XX_TRX_PHY_STATE_CMD_TX_START = 0x02,
RF2XX_TRX_PHY_STATE_CMD_FORCE_TRX_OFF = 0x03,
RF2XX_TRX_PHY_STATE_CMD_FORCE_PLL_ON = 0x04,
RF2XX_TRX_PHY_STATE_CMD_RX_ON = 0x06,
RF2XX_TRX_PHY_STATE_CMD_TRX_OFF = 0x08,
RF2XX_TRX_PHY_STATE_CMD_PLL_ON = 0x09,
RF2XX_TRX_PHY_STATE_CMD_PREP_DEEP_SLEEP = 0x10,
RF2XX_TRX_PHY_STATE_CMD_RX_AACK_ON = 0x16,
RF2XX_TRX_PHY_STATE_CMD_TX_ARET_ON = 0x19,
/* Implemented by Software */
RF2XX_TRX_PHY_STATE_CMD_SLEEP = 0x0f,
RF2XX_TRX_PHY_STATE_CMD_DEEP_SLEEP = 0x20,
};
enum rf2xx_trx_state_status_t {
RF2XX_TRX_PHY_STATUS_P_ON = 0x00,
RF2XX_TRX_PHY_STATUS_BUSY_RX = 0x01,
RF2XX_TRX_PHY_STATUS_BUSY_TX = 0x02,
RF2XX_TRX_PHY_STATUS_RX_ON = 0x06,
RF2XX_TRX_PHY_STATUS_TRX_OFF = 0x08,
RF2XX_TRX_PHY_STATUS_PLL_ON = 0x09,
RF2XX_TRX_PHY_STATUS_SLEEP = 0x0f,
RF2XX_TRX_PHY_STATUS_BUSY_RX_AACK = 0x11,
RF2XX_TRX_PHY_STATUS_BUSY_TX_ARET = 0x12,
RF2XX_TRX_PHY_STATUS_RX_AACK_ON = 0x16,
RF2XX_TRX_PHY_STATUS_TX_ARET_ON = 0x19,
RF2XX_TRX_PHY_STATUS_RX_ON_NOCLK = 0x1c,
RF2XX_TRX_PHY_STATUS_RX_AACK_ON_NOCLK = 0x1d,
RF2XX_TRX_PHY_STATUS_BUSY_RX_AACK_NOCLK = 0x1e,
RF2XX_TRX_PHY_STATUS_STATE_TRANSITION = 0x1f,
RF2XX_TRX_PHY_STATUS_MASK = 0x1f
};
/**
* TRAC STATE RX_AACK TX_ARET
* SUCCESS X X
* SUCCESS_DATA_PENDING X
* SUCCESS_WAIT_FOR_ACK X
* CHANNEL_ACCESS_FAILED X
* NO_ACK X
* INVALID X X
*/
enum rf2xx_trx_state_trac_t {
RF2XX_TRX_PHY_STATE_TRAC_SUCCESS = 0x00,
RF2XX_TRX_PHY_STATE_TRAC_SUCCESS_DATA_PENDING = 0x01,
RF2XX_TRX_PHY_STATE_TRAC_SUCCESS_WAIT_FOR_ACK = 0x02,
RF2XX_TRX_PHY_STATE_TRAC_CHANNEL_ACCESS_FAILED = 0x03,
RF2XX_TRX_PHY_STATE_TRAC_NO_ACK = 0x05,
RF2XX_TRX_PHY_STATE_TRAC_INVALID = 0x07,
};
enum rf2xx_trx_model_t {
RF2XX_TRX_MODEL_INV = 0x00,
RF2XX_TRX_MODEL_230 = 0x02,
RF2XX_TRX_MODEL_231 = 0x03,
RF2XX_TRX_MODEL_212 = 0x07,
RF2XX_TRX_MODEL_232 = 0x0A,
RF2XX_TRX_MODEL_233 = 0x0B,
};
struct rf2xx_config {
struct gpio_dt_spec irq_gpio;
struct gpio_dt_spec reset_gpio;
struct gpio_dt_spec slptr_gpio;
struct gpio_dt_spec dig2_gpio;
struct gpio_dt_spec clkm_gpio;
struct spi_dt_spec spi;
uint8_t inst;
uint8_t has_mac;
uint8_t const *tx_pwr_table;
uint8_t tx_pwr_table_size;
int8_t tx_pwr_min[2];
int8_t tx_pwr_max[2];
};
struct rf2xx_context {
struct net_if *iface;
const struct device *dev;
struct gpio_callback irq_cb;
struct k_thread trx_thread;
K_KERNEL_STACK_MEMBER(trx_stack,
CONFIG_IEEE802154_RF2XX_RX_STACK_SIZE);
struct k_sem trx_isr_lock;
struct k_sem trx_tx_sync;
enum rf2xx_trx_model_t trx_model;
/* PHY specific driver attributes */
enum ieee802154_phy_channel_page cc_page;
struct ieee802154_phy_channel_range cc_range;
struct ieee802154_phy_supported_channels cc_channels;
enum rf2xx_trx_state_trac_t trx_trac;
enum ieee802154_tx_mode tx_mode;
uint8_t mac_addr[8];
uint8_t pkt_lqi;
uint8_t pkt_ed;
int8_t trx_rssi_base;
uint8_t trx_version;
uint8_t rx_phr;
bool promiscuous;
};
#endif /* ZEPHYR_DRIVERS_IEEE802154_IEEE802154_RF2XX_H_ */
``` | /content/code_sandbox/drivers/ieee802154/ieee802154_rf2xx.h | objective-c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 1,231 |
```objective-c
/*
*
* Portions of this file are derived from ieee802154_cc2520.h that is
*
*/
#ifndef ZEPHYR_DRIVERS_IEEE802154_IEEE802154_MCR20A_H_
#define ZEPHYR_DRIVERS_IEEE802154_IEEE802154_MCR20A_H_
#include <zephyr/linker/sections.h>
#include <zephyr/sys/atomic.h>
#include <zephyr/drivers/spi.h>
struct mcr20a_config {
struct spi_dt_spec bus;
struct gpio_dt_spec irq_gpio;
struct gpio_dt_spec reset_gpio;
};
/* Runtime context structure
***************************
*/
struct mcr20a_context {
struct net_if *iface;
/**************************/
struct gpio_callback irqb_cb;
const struct device *spi;
struct spi_config spi_cfg;
uint8_t mac_addr[8];
struct k_mutex phy_mutex;
struct k_sem isr_sem;
/*********TX + CCA*********/
struct k_sem seq_sync;
atomic_t seq_retval;
/************RX************/
K_KERNEL_STACK_MEMBER(mcr20a_rx_stack,
CONFIG_IEEE802154_MCR20A_RX_STACK_SIZE);
struct k_thread mcr20a_rx_thread;
};
#include "ieee802154_mcr20a_regs.h"
uint8_t z_mcr20a_read_reg(const struct device *dev, bool dreg, uint8_t addr);
bool z_mcr20a_write_reg(const struct device *dev, bool dreg, uint8_t addr,
uint8_t value);
bool z_mcr20a_write_burst(const struct device *dev, bool dreg, uint16_t addr,
uint8_t *data_buf, uint8_t len);
bool z_mcr20a_read_burst(const struct device *dev, bool dreg, uint16_t addr,
uint8_t *data_buf, uint8_t len);
#define DEFINE_REG_READ(__reg_name, __reg_addr, __dreg) \
static inline uint8_t read_reg_##__reg_name(const struct device *dev) \
{ \
return z_mcr20a_read_reg(dev, __dreg, __reg_addr); \
}
#define DEFINE_REG_WRITE(__reg_name, __reg_addr, __dreg) \
static inline bool write_reg_##__reg_name(const struct device *dev, \
uint8_t value) \
{ \
return z_mcr20a_write_reg(dev, __dreg, __reg_addr, value); \
}
#define DEFINE_DREG_READ(__reg_name, __reg_addr) \
DEFINE_REG_READ(__reg_name, __reg_addr, true)
#define DEFINE_DREG_WRITE(__reg_name, __reg_addr) \
DEFINE_REG_WRITE(__reg_name, __reg_addr, true)
#define DEFINE_IREG_READ(__reg_name, __reg_addr) \
DEFINE_REG_READ(__reg_name, __reg_addr, false)
#define DEFINE_IREG_WRITE(__reg_name, __reg_addr) \
DEFINE_REG_WRITE(__reg_name, __reg_addr, false)
DEFINE_DREG_READ(irqsts1, MCR20A_IRQSTS1)
DEFINE_DREG_READ(irqsts2, MCR20A_IRQSTS2)
DEFINE_DREG_READ(irqsts3, MCR20A_IRQSTS3)
DEFINE_DREG_READ(phy_ctrl1, MCR20A_PHY_CTRL1)
DEFINE_DREG_READ(phy_ctrl2, MCR20A_PHY_CTRL2)
DEFINE_DREG_READ(phy_ctrl3, MCR20A_PHY_CTRL3)
DEFINE_DREG_READ(rx_frm_len, MCR20A_RX_FRM_LEN)
DEFINE_DREG_READ(phy_ctrl4, MCR20A_PHY_CTRL4)
DEFINE_DREG_READ(src_ctrl, MCR20A_SRC_CTRL)
DEFINE_DREG_READ(cca1_ed_fnl, MCR20A_CCA1_ED_FNL)
DEFINE_DREG_READ(pll_int0, MCR20A_PLL_INT0)
DEFINE_DREG_READ(pa_pwr, MCR20A_PA_PWR)
DEFINE_DREG_READ(seq_state, MCR20A_SEQ_STATE)
DEFINE_DREG_READ(lqi_value, MCR20A_LQI_VALUE)
DEFINE_DREG_READ(rssi_cca_cnt, MCR20A_RSSI_CCA_CNT)
DEFINE_DREG_READ(asm_ctrl1, MCR20A_ASM_CTRL1)
DEFINE_DREG_READ(asm_ctrl2, MCR20A_ASM_CTRL2)
DEFINE_DREG_READ(overwrite_ver, MCR20A_OVERWRITE_VER)
DEFINE_DREG_READ(clk_out_ctrl, MCR20A_CLK_OUT_CTRL)
DEFINE_DREG_READ(pwr_modes, MCR20A_PWR_MODES)
DEFINE_DREG_WRITE(irqsts1, MCR20A_IRQSTS1)
DEFINE_DREG_WRITE(irqsts2, MCR20A_IRQSTS2)
DEFINE_DREG_WRITE(irqsts3, MCR20A_IRQSTS3)
DEFINE_DREG_WRITE(phy_ctrl1, MCR20A_PHY_CTRL1)
DEFINE_DREG_WRITE(phy_ctrl2, MCR20A_PHY_CTRL2)
DEFINE_DREG_WRITE(phy_ctrl3, MCR20A_PHY_CTRL3)
DEFINE_DREG_WRITE(phy_ctrl4, MCR20A_PHY_CTRL4)
DEFINE_DREG_WRITE(src_ctrl, MCR20A_SRC_CTRL)
DEFINE_DREG_WRITE(pll_int0, MCR20A_PLL_INT0)
DEFINE_DREG_WRITE(pa_pwr, MCR20A_PA_PWR)
DEFINE_DREG_WRITE(asm_ctrl1, MCR20A_ASM_CTRL1)
DEFINE_DREG_WRITE(asm_ctrl2, MCR20A_ASM_CTRL2)
DEFINE_DREG_WRITE(overwrite_ver, MCR20A_OVERWRITE_VER)
DEFINE_DREG_WRITE(clk_out_ctrl, MCR20A_CLK_OUT_CTRL)
DEFINE_DREG_WRITE(pwr_modes, MCR20A_PWR_MODES)
DEFINE_IREG_READ(part_id, MCR20A_PART_ID)
DEFINE_IREG_READ(rx_frame_filter, MCR20A_RX_FRAME_FILTER)
DEFINE_IREG_READ(cca1_thresh, MCR20A_CCA1_THRESH)
DEFINE_IREG_READ(cca1_ed_offset_comp, MCR20A_CCA1_ED_OFFSET_COMP)
DEFINE_IREG_READ(lqi_offset_comp, MCR20A_LQI_OFFSET_COMP)
DEFINE_IREG_READ(cca_ctrl, MCR20A_CCA_CTRL)
DEFINE_IREG_READ(cca2_corr_peaks, MCR20A_CCA2_CORR_PEAKS)
DEFINE_IREG_READ(cca2_thresh, MCR20A_CCA2_THRESH)
DEFINE_IREG_READ(tmr_prescale, MCR20A_TMR_PRESCALE)
DEFINE_IREG_READ(rx_byte_count, MCR20A_RX_BYTE_COUNT)
DEFINE_IREG_READ(rx_wtr_mark, MCR20A_RX_WTR_MARK)
DEFINE_IREG_WRITE(part_id, MCR20A_PART_ID)
DEFINE_IREG_WRITE(rx_frame_filter, MCR20A_RX_FRAME_FILTER)
DEFINE_IREG_WRITE(cca1_thresh, MCR20A_CCA1_THRESH)
DEFINE_IREG_WRITE(cca1_ed_offset_comp, MCR20A_CCA1_ED_OFFSET_COMP)
DEFINE_IREG_WRITE(lqi_offset_comp, MCR20A_LQI_OFFSET_COMP)
DEFINE_IREG_WRITE(cca_ctrl, MCR20A_CCA_CTRL)
DEFINE_IREG_WRITE(cca2_corr_peaks, MCR20A_CCA2_CORR_PEAKS)
DEFINE_IREG_WRITE(cca2_thresh, MCR20A_CCA2_THRESH)
DEFINE_IREG_WRITE(tmr_prescale, MCR20A_TMR_PRESCALE)
DEFINE_IREG_WRITE(rx_byte_count, MCR20A_RX_BYTE_COUNT)
DEFINE_IREG_WRITE(rx_wtr_mark, MCR20A_RX_WTR_MARK)
#define DEFINE_BITS_SET(__reg_name, __reg_addr, __nibble) \
static inline uint8_t set_bits_##__reg_name(uint8_t value) \
{ \
value = (value << __reg_addr##__nibble##_SHIFT) & \
__reg_addr##__nibble##_MASK; \
return value; \
}
DEFINE_BITS_SET(phy_ctrl1_xcvseq, MCR20A_PHY_CTRL1, _XCVSEQ)
DEFINE_BITS_SET(phy_ctrl4_ccatype, MCR20A_PHY_CTRL4, _CCATYPE)
DEFINE_BITS_SET(pll_int0_val, MCR20A_PLL_INT0, _VAL)
DEFINE_BITS_SET(pa_pwr_val, MCR20A_PA_PWR, _VAL)
DEFINE_BITS_SET(tmr_prescale, MCR20A_TMR_PRESCALE, _VAL)
DEFINE_BITS_SET(clk_out_div, MCR20A_CLK_OUT, _DIV)
#define DEFINE_BURST_WRITE(__reg_addr, __addr, __sz, __dreg) \
static inline bool write_burst_##__reg_addr( \
const struct device *dev, uint8_t *buf) \
{ \
return z_mcr20a_write_burst(dev, __dreg, __addr, buf, __sz); \
}
#define DEFINE_BURST_READ(__reg_addr, __addr, __sz, __dreg) \
static inline bool read_burst_##__reg_addr(const struct device *dev, \
uint8_t *buf) \
{ \
return z_mcr20a_read_burst(dev, __dreg, __addr, buf, __sz); \
}
DEFINE_BURST_WRITE(t1cmp, MCR20A_T1CMP_LSB, 3, true)
DEFINE_BURST_WRITE(t2cmp, MCR20A_T2CMP_LSB, 3, true)
DEFINE_BURST_WRITE(t3cmp, MCR20A_T3CMP_LSB, 3, true)
DEFINE_BURST_WRITE(t4cmp, MCR20A_T4CMP_LSB, 3, true)
DEFINE_BURST_WRITE(t2primecmp, MCR20A_T2PRIMECMP_LSB, 2, true)
DEFINE_BURST_WRITE(pll_int0, MCR20A_PLL_INT0, 3, true)
DEFINE_BURST_WRITE(irqsts1_irqsts3, MCR20A_IRQSTS1, 3, true)
DEFINE_BURST_WRITE(irqsts1_ctrl1, MCR20A_IRQSTS1, 4, true)
DEFINE_BURST_WRITE(pan_id, MCR20A_MACPANID0_LSB, 2, false)
DEFINE_BURST_WRITE(short_addr, MCR20A_MACSHORTADDRS0_LSB, 2, false)
DEFINE_BURST_WRITE(ext_addr, MCR20A_MACLONGADDRS0_0, 8, false)
DEFINE_BURST_READ(event_timer, MCR20A_EVENT_TIMER_LSB, 3, true)
DEFINE_BURST_READ(irqsts1_ctrl4, MCR20A_IRQSTS1, 8, true)
#endif /* ZEPHYR_DRIVERS_IEEE802154_IEEE802154_MCR20A_H_ */
``` | /content/code_sandbox/drivers/ieee802154/ieee802154_mcr20a.h | objective-c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 2,360 |
```unknown
# TI CC1200 configuration options
menuconfig IEEE802154_CC1200
bool "TI CC1200 Driver support"
default y
depends on DT_HAS_TI_CC1200_ENABLED
if IEEE802154_CC1200
config IEEE802154_CC1200_RX_STACK_SIZE
int "Driver's internal RX thread stack size"
default 800
help
This option sets the driver's stack size for its internal RX thread.
The default value should be sufficient, but in case it proves to be
a too little one, this option makes it easy to play with the size.
config IEEE802154_CC1200_INIT_PRIO
int "CC1200 initialization priority"
default 80
help
Set the initialization priority number. Do not mess with it unless
you know what you are doing. Beware cc1200 requires gpio and spi to
be ready first (and sometime gpio should be the very first as spi
might need it too). And of course it has to start before the net stack.
config IEEE802154_CC1200_RANDOM_MAC
bool "Random MAC address"
default y
help
Generate a random MAC address dynamically.
if ! IEEE802154_CC1200_RANDOM_MAC
config IEEE802154_CC1200_MAC4
hex "MAC Address Byte 4"
default 0
range 0 0xff
help
This is the byte 4 of the MAC address.
config IEEE802154_CC1200_MAC5
hex "MAC Address Byte 5"
default 0
range 0 0xff
help
This is the byte 5 of the MAC address.
config IEEE802154_CC1200_MAC6
hex "MAC Address Byte 6"
default 0
range 0 0xff
help
This is the byte 6 of the MAC address.
config IEEE802154_CC1200_MAC7
hex "MAC Address Byte 7"
default 0
range 0 0xff
help
This is the byte 7 of the MAC address.
endif # IEEE802154_CC1200_RANDOM_MAC
config IEEE802154_CC1200_XOSC
int "Value of the Crystal oscillator in kHz"
default 40000
help
This sets the XOSC value, it must be between 38400 and 40000.
This value should follow what has been set in the RF settings via
SmartRF tool. Do not touch this unless you know what you are doing.
config IEEE802154_CC1200_RF_PRESET
bool "Use TI CC1200 RF pre-sets"
default y
choice
prompt "TI CC1200 RF preset"
default IEEE802154_CC1200_RF_SET_0
depends on IEEE802154_CC1200_RF_PRESET
help
Set the RF preset you want to use.
config IEEE802154_CC1200_RF_SET_0
bool "IEEE 802.15.4g SUN MR-FSK, 863MHz band, mode #1 - channel page 9, 34 channels, 50Kbps (ETSI)"
help
This is a legacy IEEE 802.15.4g-2012 SUN MR-FSK PHY that does no
longer exist in recent standards (IEEE 802.15.4-2015+).
config IEEE802154_CC1200_RF_SET_1
bool "IEEE 802.15.4g SUN MR-FSK 920MHz band, mode #1 - channel page 9, 39 channels, 50Kbps (ARIB)"
help
This is a legacy IEEE 802.15.4g-2012 SUN MR-FSK PHY that does no
longer exist in recent standards (IEEE 802.15.4-2015+).
config IEEE802154_CC1200_RF_SET_2
bool "IEEE 802.15.4 Non-Standard 2-GFSK 433MHz band - channel page 9, 15 channels, 50Kbps (ETSI)"
help
This is a non-standard PHY similar to the IEEE 802.15.4g-2012 SUN
MR-FSK PHY but not in one of the standard bands.
endchoice
config IEEE802154_CC1200_CCA_THRESHOLD
int "Value in dbm of the CCA threshold"
default -91
help
Set the CCA threshold. See datasheet's AGC_CS_THR register for
more information. Do not touch this unless you know what you are doing.
config IEEE802154_CC1200_RSSI_OFFSET
int "Value in dbm of the RSSI offset"
default -81
help
Set the gain adjustment. See datasheet's AGC_GAIN_ADJUST register for
more information. Do not touch this unless you know what you are doing.
# Do no touch below settings unless you know what you are doing
config IEEE802154_CC1200_SETTLING_CFG
hex
default 0x03
config IEEE802154_CC1200_PKTCFG0
hex
default 0x20
config IEEE802154_CC1200_PKTCFG1
hex
default 0x03
config IEEE802154_CC1200_PKTCFG2
hex
default 0x00
config IEEE802154_CC1200_RFEND_CFG1
hex
default 0x3F
config IEEE802154_CC1200_RFEND_CFG0
hex
default 0x00
endif # IEEE802154_CC1200
``` | /content/code_sandbox/drivers/ieee802154/Kconfig.cc1200 | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 1,164 |
```c
/*
*
*/
#define DT_DRV_COMPAT ti_cc13xx_cc26xx_ieee802154_subghz
#define LOG_LEVEL CONFIG_IEEE802154_DRIVER_LOG_LEVEL
#include <zephyr/logging/log.h>
LOG_MODULE_REGISTER(ieee802154_cc13xx_cc26xx_subg);
#include <errno.h>
#include <string.h>
#include <zephyr/device.h>
#include <zephyr/net/ieee802154.h>
#include <zephyr/net/ieee802154_radio.h>
#include <zephyr/net/net_pkt.h>
#include <zephyr/random/random.h>
#include <zephyr/sys/byteorder.h>
#include <zephyr/sys/crc.h>
#include <zephyr/sys/sys_io.h>
#include <driverlib/rf_mailbox.h>
#include <driverlib/rf_prop_mailbox.h>
#include <driverlib/rfc.h>
#include <inc/hw_ccfg.h>
#include <inc/hw_fcfg1.h>
#include <rf_patches/rf_patch_cpe_multi_protocol.h>
#include <ti/drivers/rf/RF.h>
#include "ieee802154_cc13xx_cc26xx_subg.h"
static int drv_start_rx(const struct device *dev);
static int drv_stop_rx(const struct device *dev);
#ifndef CMD_PROP_RADIO_DIV_SETUP_PA
/* workaround for older HAL TI SDK (less than 4.40) */
#define CMD_PROP_RADIO_DIV_SETUP_PA CMD_PROP_RADIO_DIV_SETUP
#endif
#if defined(CONFIG_IEEE802154_CC13XX_CC26XX_SUB_GHZ_CUSTOM_RADIO_SETUP)
/* User-defined CMD_PROP_RADIO_DIV_SETUP structures */
#if defined(CONFIG_SOC_CC1352R)
extern volatile rfc_CMD_PROP_RADIO_DIV_SETUP_t ieee802154_cc13xx_subg_radio_div_setup;
#elif defined(CONFIG_SOC_CC1352P) || defined(CONFIG_SOC_CC1352P7)
extern volatile rfc_CMD_PROP_RADIO_DIV_SETUP_PA_t ieee802154_cc13xx_subg_radio_div_setup;
#endif /* CONFIG_SOC_CC1352x, extern RADIO_DIV_SETUP */
#else
#if defined(CONFIG_SOC_CC1352R)
/* Radio register overrides for CC13x2R (note: CC26x2 does not support sub-GHz radio)
* from SmartRF Studio (200kbps, 50kHz deviation, 2-GFSK, 311.8kHz Rx BW),
* approximates SUN FSK PHY, 915 MHz band, operating mode #3.
*/
static uint32_t ieee802154_cc13xx_overrides_sub_ghz[] = {
/* DC/DC regulator: In Tx, use DCDCCTL5[3:0]=0x7 (DITHER_EN=0 and IPEAK=7). */
(uint32_t)0x00F788D3,
/* Set RF_FSCA.ANADIV.DIV_SEL_BIAS = 1. Bits [0:16, 24, 30] are don't care.. */
(uint32_t)0x4001405D,
/* Set RF_FSCA.ANADIV.DIV_SEL_BIAS = 1. Bits [0:16, 24, 30] are don't care.. */
(uint32_t)0x08141131,
/* Tx: Configure PA ramp time, PACTL2.RC=0x3 (in ADI0, set PACTL2[4:3]=0x3) */
ADI_2HALFREG_OVERRIDE(0, 16, 0x8, 0x8, 17, 0x1, 0x1),
/* Tx: Configure PA ramping, set wait time before turning off
* (0x1A ticks of 16/24 us = 17.3 us).
*/
HW_REG_OVERRIDE(0x6028, 0x001A),
/* Rx: Set AGC reference level to 0x16 (default: 0x2E) */
HW_REG_OVERRIDE(0x609C, 0x0016),
/* Rx: Set RSSI offset to adjust reported RSSI by -1 dB (default: -2),
* trimmed for external bias and differential configuration
*/
(uint32_t)0x000188A3,
/* Rx: Set anti-aliasing filter bandwidth to 0x8 (in ADI0, set IFAMPCTL3[7:4]=0x8) */
ADI_HALFREG_OVERRIDE(0, 61, 0xF, 0x8),
/* Tx: Set PA trim to max to maximize its output power (in ADI0, set PACTL0=0xF8) */
ADI_REG_OVERRIDE(0, 12, 0xF8),
(uint32_t)0xFFFFFFFF
};
/* Radio values for CC13X2P */
#elif defined(CONFIG_SOC_CC1352P) || defined(CONFIG_SOC_CC1352P7)
/* CC1352P overrides from SmartRF Studio (200kbps, 50kHz deviation, 2-GFSK, 311.8kHz Rx BW) */
static uint32_t ieee802154_cc13xx_overrides_sub_ghz[] = {
/* Tx: Configure PA ramp time, PACTL2.RC=0x3 (in ADI0, set PACTL2[4:3]=0x1) */
ADI_2HALFREG_OVERRIDE(0, 16, 0x8, 0x8, 17, 0x1, 0x0),
/* Rx: Set AGC reference level to 0x16 (default: 0x2E) */
HW_REG_OVERRIDE(0x609C, 0x0016),
/* Rx: Set RSSI offset to adjust reported RSSI by -1 dB (default: -2),
* trimmed for external bias and differential configuration.
*/
(uint32_t)0x000188A3,
/* Rx: Set anti-aliasing filter bandwidth to 0x6 (in ADI0, set IFAMPCTL3[7:4]=0x8) */
ADI_HALFREG_OVERRIDE(0, 61, 0xF, 0x8),
/* override_prop_common_sub1g.xml */
/* Set RF_FSCA.ANADIV.DIV_SEL_BIAS = 1. Bits [0:16, 24, 30] are don't care.. */
(uint32_t)0x4001405D,
/* Set RF_FSCA.ANADIV.DIV_SEL_BIAS = 1. Bits [0:16, 24, 30] are don't care.. */
(uint32_t)0x08141131,
/* override_prop_common.xml */
/* DC/DC regulator: In Tx with 14 dBm PA setting, use DCDCCTL5[3:0]=0xF */
/* (DITHER_EN=1 and IPEAK=7). In Rx, use default settings. */
(uint32_t)0x00F788D3,
(uint32_t)0xFFFFFFFF
};
static uint32_t rf_prop_overrides_tx_std[] = {
/* The TX Power element should always be the first in the list */
TX_STD_POWER_OVERRIDE(0x013F),
/* The ANADIV radio parameter based on the LO divider (0) and front-end (0) settings */
(uint32_t)0x11310703,
/* override_phy_tx_pa_ramp_genfsk_std.xml */
/* Tx: Configure PA ramping, set wait time before turning off */
/* (0x1A ticks of 16/24 us = 17.3 us). */
HW_REG_OVERRIDE(0x6028, 0x001A),
/* Set TXRX pin to 0 in RX and high impedance in idle/TX. */
HW_REG_OVERRIDE(0x60A8, 0x0401),
(uint32_t)0xFFFFFFFF
};
static uint32_t rf_prop_overrides_tx_20[] = {
/* The TX Power element should always be the first in the list */
TX20_POWER_OVERRIDE(0x001B8ED2),
/* The ANADIV radio parameter based on the LO divider (0) and front-end (0) settings */
(uint32_t)0x11C10703,
/* override_phy_tx_pa_ramp_genfsk_hpa.xml */
/* Tx: Configure PA ramping, set wait time before turning off */
/* (0x1F ticks of 16/24 us = 20.3 us). */
HW_REG_OVERRIDE(0x6028, 0x001F),
/* Set TXRX pin to 0 in RX/TX and high impedance in idle. */
HW_REG_OVERRIDE(0x60A8, 0x0001),
(uint32_t)0xFFFFFFFF
};
#else
#error "unsupported CC13xx SoC"
#endif /* CONFIG_SOC_CC1352x */
/* Radio setup command for CC13xx */
#if defined(CONFIG_SOC_CC1352R)
static volatile rfc_CMD_PROP_RADIO_DIV_SETUP_t ieee802154_cc13xx_subg_radio_div_setup = {
.commandNo = CMD_PROP_RADIO_DIV_SETUP,
#elif defined(CONFIG_SOC_CC1352P) || defined(CONFIG_SOC_CC1352P7)
static volatile rfc_CMD_PROP_RADIO_DIV_SETUP_PA_t ieee802154_cc13xx_subg_radio_div_setup = {
.commandNo = CMD_PROP_RADIO_DIV_SETUP_PA,
#endif /* CONFIG_SOC_CC1352x */
.condition.rule = COND_NEVER,
.modulation = {
.modType = 1, /* 2-GFSK - non-standard modulation */
.deviation = 200, /* +/- 200*250 = 50kHz deviation (modulation index 0.5) */
},
.symbolRate = {
.preScale = 15,
.rateWord = 131072, /* 200 kBit, see TRM, section 25.10.5.2, formula 15 */
},
.rxBw = 0x59, /* 310.8 kHz RX bandwidth, see TRM, section 25.10.5.2, table 25-183 */
.preamConf.nPreamBytes = 7, /* phyFskPreambleLength = 7 + 1, also see nSwBits below */
.formatConf = {
.nSwBits = 24, /* 24-bit (1 byte preamble + 16 bit SFD) */
.bMsbFirst = true,
.whitenMode = 7, /* Determine whitening and CRC from PHY header */
},
.config.biasMode = true, /* Rely on an external antenna biasing network. */
.txPower = 0x013f, /* 14 dBm, see TRM 25.3.3.2.16 */
.centerFreq = 906, /* Set channel page zero, channel 1 by default, see IEEE 802.15.4,
* section 10.1.3.3.
* TODO: Use compliant SUN PHY frequencies from channel page 9.
*/
.intFreq = 0x8000, /* Use default intermediate frequency. */
.loDivider = 5,
.pRegOverride = ieee802154_cc13xx_overrides_sub_ghz,
#if defined(CONFIG_SOC_CC1352P) || defined(CONFIG_SOC_CC1352P7)
.pRegOverrideTxStd = rf_prop_overrides_tx_std,
.pRegOverrideTx20 = rf_prop_overrides_tx_20,
#endif /* CONFIG_SOC_CC1352P, CONFIG_SOC_CC1352P7 */
};
#endif /* CONFIG_IEEE802154_CC13XX_CC26XX_SUB_GHZ_CUSTOM_RADIO_SETUP */
/* Sub GHz power tables */
#if defined(CONFIG_IEEE802154_CC13XX_CC26XX_SUB_GHZ_CUSTOM_POWER_TABLE)
extern RF_TxPowerTable_Entry ieee802154_cc13xx_subg_power_table[];
#elif defined(CONFIG_SOC_CC1352R)
static const RF_TxPowerTable_Entry ieee802154_cc13xx_subg_power_table[] = {
{ -20, RF_TxPowerTable_DEFAULT_PA_ENTRY(0, 3, 0, 2) },
{ -15, RF_TxPowerTable_DEFAULT_PA_ENTRY(1, 3, 0, 3) },
{ -10, RF_TxPowerTable_DEFAULT_PA_ENTRY(2, 3, 0, 5) },
{ -5, RF_TxPowerTable_DEFAULT_PA_ENTRY(4, 3, 0, 5) },
{ 0, RF_TxPowerTable_DEFAULT_PA_ENTRY(8, 3, 0, 8) },
{ 1, RF_TxPowerTable_DEFAULT_PA_ENTRY(9, 3, 0, 9) },
{ 2, RF_TxPowerTable_DEFAULT_PA_ENTRY(10, 3, 0, 9) },
{ 3, RF_TxPowerTable_DEFAULT_PA_ENTRY(11, 3, 0, 10) },
{ 4, RF_TxPowerTable_DEFAULT_PA_ENTRY(13, 3, 0, 11) },
{ 5, RF_TxPowerTable_DEFAULT_PA_ENTRY(14, 3, 0, 14) },
{ 6, RF_TxPowerTable_DEFAULT_PA_ENTRY(17, 3, 0, 16) },
{ 7, RF_TxPowerTable_DEFAULT_PA_ENTRY(20, 3, 0, 19) },
{ 8, RF_TxPowerTable_DEFAULT_PA_ENTRY(24, 3, 0, 22) },
{ 9, RF_TxPowerTable_DEFAULT_PA_ENTRY(28, 3, 0, 31) },
{ 10, RF_TxPowerTable_DEFAULT_PA_ENTRY(18, 2, 0, 31) },
{ 11, RF_TxPowerTable_DEFAULT_PA_ENTRY(26, 2, 0, 51) },
{ 12, RF_TxPowerTable_DEFAULT_PA_ENTRY(16, 0, 0, 82) },
{ 13, RF_TxPowerTable_DEFAULT_PA_ENTRY(36, 0, 0, 89) },
#ifdef CONFIG_CC13X2_CC26X2_BOOST_MODE
{ 14, RF_TxPowerTable_DEFAULT_PA_ENTRY(63, 0, 1, 0) },
#endif
RF_TxPowerTable_TERMINATION_ENTRY
};
#elif defined(CONFIG_SOC_CC1352P) || defined(CONFIG_SOC_CC1352P7)
/* Sub GHz power table */
static const RF_TxPowerTable_Entry ieee802154_cc13xx_subg_power_table[] = {
{ -20, RF_TxPowerTable_DEFAULT_PA_ENTRY(0, 3, 0, 2) },
{ -15, RF_TxPowerTable_DEFAULT_PA_ENTRY(1, 3, 0, 3) },
{ -10, RF_TxPowerTable_DEFAULT_PA_ENTRY(2, 3, 0, 5) },
{ -5, RF_TxPowerTable_DEFAULT_PA_ENTRY(4, 3, 0, 5) },
{ 0, RF_TxPowerTable_DEFAULT_PA_ENTRY(8, 3, 0, 8) },
{ 1, RF_TxPowerTable_DEFAULT_PA_ENTRY(9, 3, 0, 9) },
{ 2, RF_TxPowerTable_DEFAULT_PA_ENTRY(10, 3, 0, 9) },
{ 3, RF_TxPowerTable_DEFAULT_PA_ENTRY(11, 3, 0, 10) },
{ 4, RF_TxPowerTable_DEFAULT_PA_ENTRY(13, 3, 0, 11) },
{ 5, RF_TxPowerTable_DEFAULT_PA_ENTRY(14, 3, 0, 14) },
{ 6, RF_TxPowerTable_DEFAULT_PA_ENTRY(17, 3, 0, 16) },
{ 7, RF_TxPowerTable_DEFAULT_PA_ENTRY(20, 3, 0, 19) },
{ 8, RF_TxPowerTable_DEFAULT_PA_ENTRY(24, 3, 0, 22) },
{ 9, RF_TxPowerTable_DEFAULT_PA_ENTRY(28, 3, 0, 31) },
{ 10, RF_TxPowerTable_DEFAULT_PA_ENTRY(18, 2, 0, 31) },
{ 11, RF_TxPowerTable_DEFAULT_PA_ENTRY(26, 2, 0, 51) },
{ 12, RF_TxPowerTable_DEFAULT_PA_ENTRY(16, 0, 0, 82) },
{ 13, RF_TxPowerTable_DEFAULT_PA_ENTRY(36, 0, 0, 89) },
#ifdef CONFIG_CC13X2_CC26X2_BOOST_MODE
{ 14, RF_TxPowerTable_DEFAULT_PA_ENTRY(63, 0, 1, 0) },
#endif
{ 15, RF_TxPowerTable_HIGH_PA_ENTRY(18, 0, 0, 36, 0) },
{ 16, RF_TxPowerTable_HIGH_PA_ENTRY(24, 0, 0, 43, 0) },
{ 17, RF_TxPowerTable_HIGH_PA_ENTRY(28, 0, 0, 51, 2) },
{ 18, RF_TxPowerTable_HIGH_PA_ENTRY(34, 0, 0, 64, 4) },
{ 19, RF_TxPowerTable_HIGH_PA_ENTRY(15, 3, 0, 36, 4) },
{ 20, RF_TxPowerTable_HIGH_PA_ENTRY(18, 3, 0, 71, 27) },
RF_TxPowerTable_TERMINATION_ENTRY
};
#endif /* CONFIG_SOC_CC1352x power table */
#define LOCK_TIMEOUT (k_is_in_isr() ? K_NO_WAIT : K_FOREVER)
/** RF patches to use (note: RF core keeps a pointer to this, so no stack). */
static RF_Mode rf_mode = {
.rfMode = RF_MODE_MULTIPLE,
.cpePatchFxn = &rf_patch_cpe_multi_protocol,
};
static inline int drv_channel_frequency(uint16_t channel, uint16_t *frequency, uint16_t *fractFreq)
{
__ASSERT_NO_MSG(frequency != NULL);
__ASSERT_NO_MSG(fractFreq != NULL);
/* See IEEE 802.15.4-2020, section 10.1.3.3. */
if (channel == 0) {
*frequency = 868;
/*
* uint16_t fractional part of 868.3 MHz
* equivalent to (0.3 * 1000 * BIT(16)) / 1000, rounded up
*/
*fractFreq = 0x4ccd;
} else if (channel <= 10) {
*frequency = 906 + 2 * (channel - 1);
*fractFreq = 0;
} else {
*frequency = 0;
*fractFreq = 0;
return channel <= 26 ? -ENOTSUP : -EINVAL;
}
/* TODO: This incorrectly mixes up legacy BPSK SubGHz PHY channel page
* zero frequency calculation with SUN FSK operating mode #3 PHY radio
* settings.
*
* The correct channel frequency calculation for this PHY is on channel page 9,
* using the formula ChanCenterFreq = ChanCenterFreq0 + channel * ChanSpacing.
*
* Assuming operating mode #3, the parameters for some frequently used bands
* on this channel page are:
* 863 MHz: ChanSpacing 0.2, TotalNumChan 35, ChanCenterFreq0 863.1
* 915 MHz: ChanSpacing 0.4, TotalNumChan 64, ChanCenterFreq0 902.4
*
* See IEEE 802.15.4, section 10.1.3.9.
*
* Setting the PHY, channel page, band and operating mode requires additional
* radio configuration settings.
*
* Making derived MAC/PHY PIB attributes available to L2 requires an additional
* attribute getter, see
* path_to_url#issuecomment-1251122582.
*
* We resolve this bug right now by basing all timing on SUN FSK
* parameters while maintaining the channel/channel page assignment of a
* BPSK PHY.
*/
return 0;
}
static inline int drv_power_down(const struct device *const dev)
{
struct ieee802154_cc13xx_cc26xx_subg_data *drv_data = dev->data;
(void)RF_yield(drv_data->rf_handle);
return 0;
}
static void cmd_prop_tx_adv_callback(RF_Handle h, RF_CmdHandle ch,
RF_EventMask e)
{
const struct device *const dev = DEVICE_DT_INST_GET(0);
struct ieee802154_cc13xx_cc26xx_subg_data *drv_data = dev->data;
RF_Op *op = RF_getCmdOp(h, ch);
/* No need for locking as the RX status is volatile and there's no race. */
LOG_DBG("ch: %u cmd: %04x cs st: %04x tx st: %04x e: 0x%" PRIx64, ch,
op->commandNo, op->status, drv_data->cmd_prop_tx_adv.status, e);
}
static void drv_rx_done(struct ieee802154_cc13xx_cc26xx_subg_data *drv_data)
{
int8_t rssi, status;
struct net_pkt *pkt;
uint8_t len;
uint8_t *sdu;
/* No need for locking as only immutable data is accessed from drv_data.
* The rx queue itself (entries and data) are managed and protected
* internally by TI's RF driver.
*/
for (int i = 0; i < CC13XX_CC26XX_NUM_RX_BUF; i++) {
if (drv_data->rx_entry[i].status == DATA_ENTRY_FINISHED) {
len = drv_data->rx_data[i][0];
sdu = drv_data->rx_data[i] + 1;
status = drv_data->rx_data[i][len--];
rssi = drv_data->rx_data[i][len--];
/* TODO: Configure firmware to include CRC in raw mode. */
if (IS_ENABLED(CONFIG_IEEE802154_RAW_MODE) && len > 0) {
/* append CRC-16/CCITT */
uint16_t crc = 0;
crc = crc16_ccitt(0, sdu, len);
sdu[len++] = crc;
sdu[len++] = crc >> 8;
}
LOG_DBG("Received: len = %u, rssi = %d status = %u",
len, rssi, status);
pkt = net_pkt_rx_alloc_with_buffer(
drv_data->iface, len, AF_UNSPEC, 0, K_NO_WAIT);
if (!pkt) {
LOG_WRN("Cannot allocate packet");
continue;
}
if (net_pkt_write(pkt, sdu, len)) {
LOG_WRN("Cannot write packet");
net_pkt_unref(pkt);
continue;
}
drv_data->rx_entry[i].status = DATA_ENTRY_PENDING;
/* TODO: Determine LQI in PROP mode. */
net_pkt_set_ieee802154_lqi(pkt, 0xff);
net_pkt_set_ieee802154_rssi_dbm(pkt,
rssi == CC13XX_CC26XX_INVALID_RSSI
? IEEE802154_MAC_RSSI_DBM_UNDEFINED
: rssi);
if (ieee802154_handle_ack(drv_data->iface, pkt) == NET_OK) {
net_pkt_unref(pkt);
continue;
}
if (net_recv_data(drv_data->iface, pkt)) {
LOG_WRN("Packet dropped");
net_pkt_unref(pkt);
}
} else if (drv_data->rx_entry[i].status ==
DATA_ENTRY_UNFINISHED) {
LOG_WRN("Frame not finished");
drv_data->rx_entry[i].status = DATA_ENTRY_PENDING;
}
}
}
static void cmd_prop_rx_adv_callback(RF_Handle h, RF_CmdHandle ch,
RF_EventMask e)
{
const struct device *const dev = DEVICE_DT_INST_GET(0);
struct ieee802154_cc13xx_cc26xx_subg_data *drv_data = dev->data;
RF_Op *op = RF_getCmdOp(h, ch);
LOG_DBG("ch: %u cmd: %04x st: %04x e: 0x%" PRIx64, ch,
op->commandNo, op->status, e);
/* If PROP_ERROR_RXBUF is returned, then RF_EventRxEntryDone is never
* triggered. So finished buffers need to be cleaned up even on this
* status.
*/
if (e & RF_EventRxEntryDone || op->status == PROP_ERROR_RXBUF) {
drv_rx_done(drv_data);
}
if (op->status == PROP_ERROR_RXBUF
|| op->status == PROP_ERROR_RXFULL
|| op->status == PROP_ERROR_RXOVF) {
LOG_DBG("RX Error %x", op->status);
/* Restart RX */
if (k_sem_take(&drv_data->lock, LOCK_TIMEOUT)) {
return;
}
(void)drv_start_rx(dev);
k_sem_give(&drv_data->lock);
}
}
static void client_error_callback(RF_Handle h, RF_CmdHandle ch,
RF_EventMask e)
{
ARG_UNUSED(h);
ARG_UNUSED(ch);
LOG_ERR("client error: 0x%" PRIx64, e);
}
static void client_event_callback(RF_Handle h, RF_ClientEvent event,
void *arg)
{
ARG_UNUSED(h);
LOG_DBG("event: %d arg: %p", event, arg);
}
static enum ieee802154_hw_caps
ieee802154_cc13xx_cc26xx_subg_get_capabilities(const struct device *dev)
{
/* TODO: enable IEEE802154_HW_FILTER */
return IEEE802154_HW_FCS;
}
static int ieee802154_cc13xx_cc26xx_subg_cca(const struct device *dev)
{
struct ieee802154_cc13xx_cc26xx_subg_data *drv_data = dev->data;
bool was_rx_on = false;
RF_EventMask events;
int ret;
if (k_sem_take(&drv_data->lock, LOCK_TIMEOUT)) {
return -EWOULDBLOCK;
}
if (!drv_data->is_up) {
ret = -ENETDOWN;
goto out;
}
drv_data->cmd_prop_cs.status = IDLE;
was_rx_on = drv_data->cmd_prop_rx_adv.status == ACTIVE;
if (was_rx_on) {
ret = drv_stop_rx(dev);
if (ret) {
ret = -EIO;
goto out;
}
}
events = RF_runCmd(drv_data->rf_handle, (RF_Op *)&drv_data->cmd_prop_cs, RF_PriorityNormal,
NULL, 0);
if (events != RF_EventLastCmdDone) {
LOG_DBG("Failed to request CCA: 0x%" PRIx64, events);
ret = -EIO;
goto out;
}
switch (drv_data->cmd_prop_cs.status) {
case PROP_DONE_IDLE:
/* Do not re-enable RX when the channel is idle as
* this usually means we want to TX directly after
* and cannot afford any extra latency.
*/
ret = 0;
break;
case PROP_DONE_BUSY:
case PROP_DONE_BUSYTIMEOUT:
ret = -EBUSY;
break;
default:
ret = -EIO;
}
out:
/* Re-enable RX if we found it on initially
* and the channel is busy (or another error
* occurred) as this usually means we back off
* and want to be able to receive packets in
* the meantime.
*/
if (ret && was_rx_on) {
drv_start_rx(dev);
}
k_sem_give(&drv_data->lock);
return ret;
}
/* This method must be called with the lock held. */
static int drv_start_rx(const struct device *dev)
{
struct ieee802154_cc13xx_cc26xx_subg_data *drv_data = dev->data;
RF_CmdHandle cmd_handle;
if (drv_data->cmd_prop_rx_adv.status == ACTIVE) {
return -EALREADY;
}
#ifdef CONFIG_ASSERT
if (CONFIG_ASSERT_LEVEL > 0) {
/* ensure that all RX buffers are initialized and pending. */
for (int i = 0; i < CC13XX_CC26XX_NUM_RX_BUF; i++) {
__ASSERT_NO_MSG(drv_data->rx_entry[i].pNextEntry != NULL);
__ASSERT_NO_MSG(drv_data->rx_entry[i].status == DATA_ENTRY_PENDING);
}
}
#endif
drv_data->cmd_prop_rx_adv.status = IDLE;
cmd_handle = RF_postCmd(drv_data->rf_handle,
(RF_Op *)&drv_data->cmd_prop_rx_adv, RF_PriorityNormal,
cmd_prop_rx_adv_callback, RF_EventRxEntryDone);
if (cmd_handle < 0) {
LOG_DBG("Failed to post RX command (%d)", cmd_handle);
return -EIO;
}
drv_data->rx_cmd_handle = cmd_handle;
return 0;
}
/* This method must be called with the lock held. */
static int drv_stop_rx(const struct device *dev)
{
struct ieee802154_cc13xx_cc26xx_subg_data *drv_data = dev->data;
RF_Stat status;
if (drv_data->cmd_prop_rx_adv.status != ACTIVE) {
return -EALREADY;
}
/* Stop RX without aborting ongoing reception of packets. */
status = RF_cancelCmd(drv_data->rf_handle, drv_data->rx_cmd_handle, RF_ABORT_GRACEFULLY);
switch (status) {
case RF_StatSuccess:
case RF_StatCmdEnded:
return 0;
default:
return -EIO;
}
}
static int ieee802154_cc13xx_cc26xx_subg_set_channel(
const struct device *dev, uint16_t channel)
{
struct ieee802154_cc13xx_cc26xx_subg_data *drv_data = dev->data;
uint16_t freq, fract;
RF_EventMask events;
bool was_rx_on;
int ret;
ret = drv_channel_frequency(channel, &freq, &fract);
if (ret < 0) {
return ret;
}
if (k_sem_take(&drv_data->lock, LOCK_TIMEOUT)) {
return -EWOULDBLOCK;
}
was_rx_on = drv_data->cmd_prop_rx_adv.status == ACTIVE;
if (was_rx_on) {
ret = drv_stop_rx(dev);
if (ret) {
ret = -EIO;
goto out;
}
}
/* Set the frequency */
drv_data->cmd_fs.status = IDLE;
drv_data->cmd_fs.frequency = freq;
drv_data->cmd_fs.fractFreq = fract;
events = RF_runCmd(drv_data->rf_handle, (RF_Op *)&drv_data->cmd_fs,
RF_PriorityNormal, NULL, 0);
if (events != RF_EventLastCmdDone || drv_data->cmd_fs.status != DONE_OK) {
LOG_DBG("Failed to set frequency: 0x%" PRIx64, events);
ret = -EIO;
}
out:
if (was_rx_on) {
/* Re-enable RX if we found it on initially. */
(void)drv_start_rx(dev);
} else if (!drv_data->is_up) {
ret = drv_power_down(dev);
}
k_sem_give(&drv_data->lock);
return ret;
}
static int
ieee802154_cc13xx_cc26xx_subg_filter(const struct device *dev, bool set,
enum ieee802154_filter_type type,
const struct ieee802154_filter *filter)
{
ARG_UNUSED(dev);
ARG_UNUSED(set);
ARG_UNUSED(type);
ARG_UNUSED(filter);
return -ENOTSUP;
}
static int ieee802154_cc13xx_cc26xx_subg_set_txpower(
const struct device *dev, int16_t dbm)
{
struct ieee802154_cc13xx_cc26xx_subg_data *drv_data = dev->data;
RF_TxPowerTable_Value power_table_value;
RF_Stat status;
int ret = 0;
power_table_value = RF_TxPowerTable_findValue(
(RF_TxPowerTable_Entry *)ieee802154_cc13xx_subg_power_table, dbm);
if (power_table_value.rawValue == RF_TxPowerTable_INVALID_VALUE) {
LOG_DBG("RF_TxPowerTable_findValue() failed");
return -EINVAL;
}
/* No need for locking: rf_handle is immutable after initialization. */
status = RF_setTxPower(drv_data->rf_handle, power_table_value);
if (status != RF_StatSuccess) {
LOG_DBG("RF_setTxPower() failed: %d", status);
return -EIO;
}
if (k_sem_take(&drv_data->lock, LOCK_TIMEOUT)) {
return -EWOULDBLOCK;
}
if (!drv_data->is_up) {
ret = drv_power_down(dev);
}
k_sem_give(&drv_data->lock);
return ret;
}
/* See IEEE 802.15.4 section 6.7.1 and TRM section 25.5.4.3 */
static int ieee802154_cc13xx_cc26xx_subg_tx(const struct device *dev,
enum ieee802154_tx_mode mode,
struct net_pkt *pkt,
struct net_buf *buf)
{
struct ieee802154_cc13xx_cc26xx_subg_data *drv_data = dev->data;
RF_EventMask events;
int ret = 0;
if (buf->len > (CC13XX_CC26XX_TX_BUF_SIZE - IEEE802154_PHY_SUN_FSK_PHR_LEN)) {
return -EINVAL;
}
if (mode != IEEE802154_TX_MODE_DIRECT) {
/* For backwards compatibility we only log an error but do not bail. */
NET_ERR("TX mode %d not supported - sending directly instead.", mode);
}
if (k_sem_take(&drv_data->lock, K_FOREVER)) {
return -EIO;
}
if (!drv_data->is_up) {
ret = -ENETDOWN;
goto out;
}
if (drv_data->cmd_prop_rx_adv.status == ACTIVE) {
ret = drv_stop_rx(dev);
if (ret) {
ret = -EIO;
goto out;
}
}
/* Complete the SUN FSK PHY header, see IEEE 802.15.4, section 19.2.4. */
drv_data->tx_data[0] = buf->len + IEEE802154_FCS_LENGTH;
/* Set TX data
*
* TODO: Zero-copy TX, see discussion in #49775.
*/
memcpy(&drv_data->tx_data[IEEE802154_PHY_SUN_FSK_PHR_LEN], buf->data, buf->len);
drv_data->cmd_prop_tx_adv.pktLen = buf->len + IEEE802154_PHY_SUN_FSK_PHR_LEN;
drv_data->cmd_prop_tx_adv.status = IDLE;
events = RF_runCmd(drv_data->rf_handle, (RF_Op *)&drv_data->cmd_prop_tx_adv,
RF_PriorityNormal, cmd_prop_tx_adv_callback, RF_EventLastCmdDone);
if ((events & RF_EventLastCmdDone) == 0) {
LOG_DBG("Failed to run command (%" PRIx64 ")", events);
ret = -EIO;
goto out;
}
if (drv_data->cmd_prop_tx_adv.status != PROP_DONE_OK) {
LOG_DBG("Transmit failed (0x%x)", drv_data->cmd_prop_tx_adv.status);
ret = -EIO;
}
out:
(void)drv_start_rx(dev);
k_sem_give(&drv_data->lock);
return ret;
}
/* driver-allocated attribute memory - constant across all driver instances */
IEEE802154_DEFINE_PHY_SUPPORTED_CHANNELS(drv_attr, 0, 10);
static int ieee802154_cc13xx_cc26xx_subg_attr_get(const struct device *dev,
enum ieee802154_attr attr,
struct ieee802154_attr_value *value)
{
ARG_UNUSED(dev);
/* We claim channel page nine with channel page zero channel range to
* ensure SUN-FSK timing, see the TODO in
* ieee802154_cc13xx_cc26xx_subg_channel_to_frequency().
*/
return ieee802154_attr_get_channel_page_and_range(
attr, IEEE802154_ATTR_PHY_CHANNEL_PAGE_NINE_SUN_PREDEFINED,
&drv_attr.phy_supported_channels, value);
}
static int ieee802154_cc13xx_cc26xx_subg_start(const struct device *dev)
{
struct ieee802154_cc13xx_cc26xx_subg_data *drv_data = dev->data;
int ret;
if (k_sem_take(&drv_data->lock, LOCK_TIMEOUT)) {
return -EIO;
}
if (drv_data->is_up) {
ret = -EALREADY;
goto out;
}
ret = drv_start_rx(dev);
if (ret) {
goto out;
}
drv_data->is_up = true;
out:
k_sem_give(&drv_data->lock);
return ret;
}
/* Aborts all radio commands in the RF queue. Requires the lock to be held. */
static int drv_abort_commands(const struct device *dev)
{
struct ieee802154_cc13xx_cc26xx_subg_data *drv_data = dev->data;
RF_Stat status;
status = RF_flushCmd(drv_data->rf_handle, RF_CMDHANDLE_FLUSH_ALL, 0);
if (!(status == RF_StatCmdDoneSuccess
|| status == RF_StatSuccess
|| status == RF_StatRadioInactiveError
|| status == RF_StatInvalidParamsError)) {
LOG_DBG("Failed to abort radio operations (%d)", status);
return -EIO;
}
return 0;
}
/**
* Stops the sub-GHz interface and yields the radio (tells RF module to power
* down).
*/
static int ieee802154_cc13xx_cc26xx_subg_stop_if(const struct device *dev)
{
struct ieee802154_cc13xx_cc26xx_subg_data *drv_data = dev->data;
int ret;
if (k_sem_take(&drv_data->lock, LOCK_TIMEOUT)) {
return -EIO;
}
if (!drv_data->is_up) {
ret = -EALREADY;
goto out;
}
ret = drv_abort_commands(dev);
if (ret) {
goto out;
}
ret = drv_power_down(dev);
if (ret) {
goto out;
}
drv_data->is_up = false;
out:
k_sem_give(&drv_data->lock);
return ret;
}
static int
ieee802154_cc13xx_cc26xx_subg_configure(const struct device *dev,
enum ieee802154_config_type type,
const struct ieee802154_config *config)
{
return -ENOTSUP;
}
static void drv_setup_rx_buffers(struct ieee802154_cc13xx_cc26xx_subg_data *drv_data)
{
/* No need to zero buffers as they are zeroed on initialization and no
* need for locking as initialization is done with exclusive access.
*/
for (size_t i = 0; i < CC13XX_CC26XX_NUM_RX_BUF; ++i) {
if (i < CC13XX_CC26XX_NUM_RX_BUF - 1) {
drv_data->rx_entry[i].pNextEntry =
(uint8_t *) &drv_data->rx_entry[i + 1];
} else {
drv_data->rx_entry[i].pNextEntry =
(uint8_t *) &drv_data->rx_entry[0];
}
drv_data->rx_entry[i].config.type = DATA_ENTRY_TYPE_PTR;
drv_data->rx_entry[i].config.lenSz = 1;
drv_data->rx_entry[i].length = sizeof(drv_data->rx_data[0]);
drv_data->rx_entry[i].pData = drv_data->rx_data[i];
}
drv_data->rx_queue.pCurrEntry = (uint8_t *)&drv_data->rx_entry[0];
drv_data->rx_queue.pLastEntry = NULL;
}
static void drv_setup_tx_buffer(struct ieee802154_cc13xx_cc26xx_subg_data *drv_data)
{
/* No need to zero buffers as they are zeroed on initialization and no
* need for locking as initialization is done with exclusive access.
*/
/* Part of the SUN FSK PHY header, see IEEE 802.15.4, section 19.2.4. */
drv_data->tx_data[1] = BIT(3) | /* FCS Type: 2-octet FCS */
BIT(4); /* DW: Enable Data Whitening */
drv_data->cmd_prop_tx_adv.pPkt = drv_data->tx_data;
}
static void drv_data_init(struct ieee802154_cc13xx_cc26xx_subg_data *drv_data)
{
uint8_t *mac;
/* TODO: Do multi-protocol devices need more than one IEEE MAC? */
if (sys_read32(CCFG_BASE + CCFG_O_IEEE_MAC_0) != 0xFFFFFFFF &&
sys_read32(CCFG_BASE + CCFG_O_IEEE_MAC_1) != 0xFFFFFFFF) {
mac = (uint8_t *)(CCFG_BASE + CCFG_O_IEEE_MAC_0);
} else {
mac = (uint8_t *)(FCFG1_BASE + FCFG1_O_MAC_15_4_0);
}
sys_memcpy_swap(&drv_data->mac, mac, sizeof(drv_data->mac));
/* Setup circular RX queue (TRM 25.3.2.7) */
drv_setup_rx_buffers(drv_data);
/* Setup TX buffer (TRM 25.10.2.1.1, table 25-171) */
drv_setup_tx_buffer(drv_data);
k_sem_init(&drv_data->lock, 1, 1);
}
static void ieee802154_cc13xx_cc26xx_subg_iface_init(struct net_if *iface)
{
const struct device *dev = net_if_get_device(iface);
struct ieee802154_cc13xx_cc26xx_subg_data *drv_data = dev->data;
net_if_set_link_addr(iface, drv_data->mac, sizeof(drv_data->mac),
NET_LINK_IEEE802154);
drv_data->iface = iface;
ieee802154_init(iface);
}
static const struct ieee802154_radio_api
ieee802154_cc13xx_cc26xx_subg_radio_api = {
.iface_api.init = ieee802154_cc13xx_cc26xx_subg_iface_init,
.get_capabilities = ieee802154_cc13xx_cc26xx_subg_get_capabilities,
.cca = ieee802154_cc13xx_cc26xx_subg_cca,
.set_channel = ieee802154_cc13xx_cc26xx_subg_set_channel,
.filter = ieee802154_cc13xx_cc26xx_subg_filter,
.set_txpower = ieee802154_cc13xx_cc26xx_subg_set_txpower,
.tx = ieee802154_cc13xx_cc26xx_subg_tx,
.start = ieee802154_cc13xx_cc26xx_subg_start,
.stop = ieee802154_cc13xx_cc26xx_subg_stop_if,
.configure = ieee802154_cc13xx_cc26xx_subg_configure,
.attr_get = ieee802154_cc13xx_cc26xx_subg_attr_get,
};
static int ieee802154_cc13xx_cc26xx_subg_init(const struct device *dev)
{
struct ieee802154_cc13xx_cc26xx_subg_data *drv_data = dev->data;
uint16_t freq, fract;
RF_Params rf_params;
RF_EventMask events;
/* No need for locking - initialization is exclusive. */
/* Initialize driver data */
drv_data_init(drv_data);
/* Setup radio */
RF_Params_init(&rf_params);
rf_params.pErrCb = client_error_callback;
rf_params.pClientEventCb = client_event_callback;
drv_data->rf_handle = RF_open(&drv_data->rf_object,
&rf_mode, (RF_RadioSetup *)&ieee802154_cc13xx_subg_radio_div_setup,
&rf_params);
if (drv_data->rf_handle == NULL) {
LOG_ERR("RF_open() failed");
return -EIO;
}
/* Run CMD_FS for channel 0 to place a valid CMD_FS command in the
* driver's internal state which it requires for proper operation.
*/
(void)drv_channel_frequency(0, &freq, &fract);
drv_data->cmd_fs.status = IDLE;
drv_data->cmd_fs.frequency = freq;
drv_data->cmd_fs.fractFreq = fract;
events = RF_runCmd(drv_data->rf_handle, (RF_Op *)&drv_data->cmd_fs,
RF_PriorityNormal, NULL, 0);
if (events != RF_EventLastCmdDone || drv_data->cmd_fs.status != DONE_OK) {
LOG_ERR("Failed to set frequency: 0x%" PRIx64, events);
return -EIO;
}
return drv_power_down(dev);
}
static struct ieee802154_cc13xx_cc26xx_subg_data ieee802154_cc13xx_cc26xx_subg_data = {
/* Common Radio Commands */
.cmd_fs = {
.commandNo = CMD_FS,
.condition.rule = COND_NEVER,
},
.cmd_prop_rx_adv = {
.commandNo = CMD_PROP_RX_ADV,
.condition.rule = COND_NEVER,
.pktConf = {
.bRepeatOk = true,
.bRepeatNok = true,
.bUseCrc = true,
.filterOp = true,
},
.rxConf = {
.bAutoFlushIgnored = true,
.bAutoFlushCrcErr = true,
.bAppendRssi = true,
.bAppendStatus = true,
},
/* Last preamble byte and SFD for uncoded 2-FSK SUN PHY, phySunFskSfd = 0,
* see IEEE 802.15.4, section 19.2.3.2, table 19-2.
*/
.syncWord0 = 0x55904E,
.maxPktLen = IEEE802154_MAX_PHY_PACKET_SIZE,
/* PHR field format, see IEEE 802.15.4, section 19.2.4 */
.hdrConf = {
.numHdrBits = 16,
.numLenBits = 11,
},
.lenOffset = -4,
.endTrigger.triggerType = TRIG_NEVER,
.pQueue = &ieee802154_cc13xx_cc26xx_subg_data.rx_queue,
.pOutput =
(uint8_t *) &ieee802154_cc13xx_cc26xx_subg_data
.cmd_prop_rx_adv_output,
},
.cmd_prop_cs = {
.commandNo = CMD_PROP_CS,
.condition.rule = COND_NEVER,
.csConf = {
/* CCA Mode 1: Energy above threshold, see section 10.2.8.
* CC13/26xx SubG does not support correlation mode.
*/
.bEnaRssi = true,
/* Abort as soon as any energy above the ED threshold is detected. */
.busyOp = true,
/* Continue sensing until the timeout is reached. */
.idleOp = false,
},
.rssiThr = CONFIG_IEEE802154_CC13XX_CC26XX_SUB_GHZ_CS_THRESHOLD,
.csEndTrigger.triggerType = TRIG_REL_START,
/* see IEEE 802.15.4, section 11.3, table 11-1 and section 10.2.8 */
.csEndTime = RF_convertUsToRatTicks(
IEEE802154_PHY_A_CCA_TIME *
(IEEE802154_PHY_SUN_FSK_863MHZ_915MHZ_SYMBOL_PERIOD_NS /
NSEC_PER_USEC)
),
},
.cmd_prop_tx_adv = {
.commandNo = CMD_PROP_TX_ADV,
.startTrigger.triggerType = TRIG_NOW,
.startTrigger.pastTrig = true,
.condition.rule = COND_NEVER,
.pktConf.bUseCrc = true,
/* PHR field format, see IEEE 802.15.4, section 19.2.4 */
.numHdrBits = 16,
.preTrigger.triggerType =
TRIG_REL_START, /* workaround for CC13_RF_ROM_FW_CPE--BUG00016 */
.preTrigger.pastTrig = true,
/* Last preamble byte and SFD for uncoded 2-FSK SUN PHY, phySunFskSfd = 0,
* see IEEE 802.15.4, section 19.2.3.2, table 19-2.
*/
.syncWord = 0x55904E,
},
};
#if defined(CONFIG_NET_L2_IEEE802154)
NET_DEVICE_DT_INST_DEFINE(0, ieee802154_cc13xx_cc26xx_subg_init, NULL,
&ieee802154_cc13xx_cc26xx_subg_data, NULL,
CONFIG_IEEE802154_CC13XX_CC26XX_SUB_GHZ_INIT_PRIO,
&ieee802154_cc13xx_cc26xx_subg_radio_api,
IEEE802154_L2, NET_L2_GET_CTX_TYPE(IEEE802154_L2),
IEEE802154_MTU);
#else
DEVICE_DT_INST_DEFINE(0, ieee802154_cc13xx_cc26xx_subg_init, NULL,
&ieee802154_cc13xx_cc26xx_subg_data, NULL, POST_KERNEL,
CONFIG_IEEE802154_CC13XX_CC26XX_SUB_GHZ_INIT_PRIO,
&ieee802154_cc13xx_cc26xx_subg_radio_api);
#endif
``` | /content/code_sandbox/drivers/ieee802154/ieee802154_cc13xx_cc26xx_subg.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 10,892 |
```objective-c
/* ieee802154_rf2xx_regs.h - ATMEL RF2XX transceiver registers */
/*
*
*/
#ifndef ZEPHYR_DRIVERS_IEEE802154_IEEE802154_RF2XX_REGS_H_
#define ZEPHYR_DRIVERS_IEEE802154_IEEE802154_RF2XX_REGS_H_
/*- Definitions ------------------------------------------------------------*/
#define RF2XX_AES_BLOCK_SIZE 16
#define RF2XX_AES_CORE_CYCLE_TIME 24 /* us */
#define RF2XX_RANDOM_NUMBER_UPDATE_INTERVAL 1 /* us */
#define RX2XX_FRAME_HEADER_SIZE 2
#define RX2XX_FRAME_FOOTER_SIZE 3
#define RX2XX_FRAME_FCS_LENGTH 2
#define RX2XX_FRAME_MIN_PHR_SIZE 5
#define RX2XX_FRAME_PHR_INDEX 1
#define RX2XX_FRAME_LQI_INDEX 2
#define RX2XX_FRAME_ED_INDEX 3
#define RX2XX_FRAME_TRAC_INDEX 4
#define RF2XX_MAX_PSDU_LENGTH 127
#define RX2XX_MAX_FRAME_SIZE 132
#define RF2XX_RSSI_BPSK_20 -100
#define RF2XX_RSSI_BPSK_40 -99
#define RF2XX_RSSI_OQPSK_SIN_RC_100 -98
#define RF2XX_RSSI_OQPSK_SIN_250 -97
#define RF2XX_RSSI_OQPSK_RC_250 -97
/*- Types your_sha256_hash--*/
#define RF2XX_TRX_STATUS_REG 0x01
#define RF2XX_TRX_STATE_REG 0x02
#define RF2XX_TRX_CTRL_0_REG 0x03
#define RF2XX_TRX_CTRL_1_REG 0x04
#define RF2XX_PHY_TX_PWR_REG 0x05
#define RF2XX_PHY_RSSI_REG 0x06
#define RF2XX_PHY_ED_LEVEL_REG 0x07
#define RF2XX_PHY_CC_CCA_REG 0x08
#define RF2XX_CCA_THRES_REG 0x09
#define RF2XX_RX_CTRL_REG 0x0a
#define RF2XX_SFD_VALUE_REG 0x0b
#define RF2XX_TRX_CTRL_2_REG 0x0c
#define RF2XX_ANT_DIV_REG 0x0d
#define RF2XX_IRQ_MASK_REG 0x0e
#define RF2XX_IRQ_STATUS_REG 0x0f
#define RF2XX_VREG_CTRL_REG 0x10
#define RF2XX_BATMON_REG 0x11
#define RF2XX_XOSC_CTRL_REG 0x12
#define RF2XX_CC_CTRL_0_REG 0x13
#define RF2XX_CC_CTRL_1_REG 0x14
#define RF2XX_RX_SYN_REG 0x15
#define RF2XX_TRX_RPC_REG 0x16
#define RF2XX_RF_CTRL_0_REG 0x16
#define RF2XX_XAH_CTRL_1_REG 0x17
#define RF2XX_FTN_CTRL_REG 0x18
#define RF2XX_RF_CTRL_1_REG 0x19
#define RF2XX_XAH_CTRL_2_REG 0x19
#define RF2XX_PLL_CF_REG 0x1a
#define RF2XX_PLL_DCU_REG 0x1b
#define RF2XX_PART_NUM_REG 0x1c
#define RF2XX_VERSION_NUM_REG 0x1d
#define RF2XX_MAN_ID_0_REG 0x1e
#define RF2XX_MAN_ID_1_REG 0x1f
#define RF2XX_SHORT_ADDR_0_REG 0x20
#define RF2XX_SHORT_ADDR_1_REG 0x21
#define RF2XX_PAN_ID_0_REG 0x22
#define RF2XX_PAN_ID_1_REG 0x23
#define RF2XX_IEEE_ADDR_0_REG 0x24
#define RF2XX_IEEE_ADDR_1_REG 0x25
#define RF2XX_IEEE_ADDR_2_REG 0x26
#define RF2XX_IEEE_ADDR_3_REG 0x27
#define RF2XX_IEEE_ADDR_4_REG 0x28
#define RF2XX_IEEE_ADDR_5_REG 0x29
#define RF2XX_IEEE_ADDR_6_REG 0x2a
#define RF2XX_IEEE_ADDR_7_REG 0x2b
#define RF2XX_XAH_CTRL_0_REG 0x2c
#define RF2XX_CSMA_SEED_0_REG 0x2d
#define RF2XX_CSMA_SEED_1_REG 0x2e
#define RF2XX_CSMA_BE_REG 0x2f
#define RF2XX_TST_CTRL_DIGI_REG 0x36
#define RF2XX_PHY_TX_TIME_REG 0x3b
#define RF2XX_PHY_PMU_VALUE_REG 0x3b
#define RF2XX_TST_AGC_REG 0x3c
#define RF2XX_TST_SDM_REG 0x3d
#define RF2XX_AES_STATUS_REG 0x82
#define RF2XX_AES_CTRL_REG 0x83
#define RF2XX_AES_KEY_REG 0x84
#define RF2XX_AES_STATE_REG 0x84
#define RF2XX_AES_CTRL_M_REG 0x94
/* TRX_STATUS */
#define RF2XX_CCA_DONE 7
#define RF2XX_CCA_STATUS 6
#define RF2XX_TRX_STATUS 0
/* TRX_STATE */
#define RF2XX_TRAC_STATUS 5
#define RF2XX_TRX_CMD 0
#define RF2XX_TRAC_BIT_MASK 7
/* TRX_CTRL_0 */
#define RF2XX_TOM_EN 7
#define RF2XX_PAD_IO 6
#define RF2XX_PAD_IO_CLKM 4
#define RF2XX_PMU_EN 4
#define RF2XX_PMU_IF_INVERSE 4
#define RF2XX_CLKM_SHA_SEL 3
#define RF2XX_CLKM_CTRL 0
/* TRX_CTRL_1 */
#define RF2XX_PA_EXT_EN 7
#define RF2XX_IRQ_2_EXT_EN 6
#define RF2XX_TX_AUTO_CRC_ON 5
#define RF2XX_RX_BL_CTRL 4
#define RF2XX_SPI_CMD_MODE 2
#define RF2XX_IRQ_MASK_MODE 1
#define RF2XX_IRQ_POLARITY 0
/* PHY_TX_PWR */
#define RF2XX_PA_BOOST 7
#define RF2XX_PA_BUF_LT 6
#define RF2XX_GC_PA 5
#define RF2XX_PA_SHR_LT 4
#define RF2XX_TX_PWR 0
/* PHY_RSSI */
#define RF2XX_RX_CRC_VALID 7
#define RF2XX_RND_VALUE 5
#define RF2XX_RSSI 0
#define RF2XX_RSSI_MASK 0x1F
/* PHY_CC_CCA */
#define RF2XX_CCA_REQUEST 7
#define RF2XX_CCA_MODE 5
#define RF2XX_CHANNEL 0
/* CCA_THRES */
#define RF2XX_CCA_CS_THRES 4
#define RF2XX_CCA_ED_THRES 0
/* RX_CTRL_REG */
#define RF2XX_PEL_SHIFT_VALUE 6
#define RF2XX_JCM_EN 5
#define RF2XX_PDT_THRES 0
/* TRX_CTRL_2 */
#define RF2XX_RX_SAFE_MODE 7
#define RF2XX_TRX_OFF_AVDD_EN 6
#define RF2XX_OQPSK_SCRAM_EN 5
#define RF2XX_OQPSK_SUB1_RC_EN 4
#define RF2XX_ALT_SPECTRUM 4
#define RF2XX_BPSK_OQPSK 3
#define RF2XX_SUB_MODE 2
#define RF2XX_OQPSK_DATA_RATE 0
#define RF2XX_SUB_CHANNEL_MASK 0x3F
#define RF2XX_CC_BPSK_20 0x00
#define RF2XX_CC_BPSK_40 0x04
#define RF2XX_CC_OQPSK_SIN_RC_100 0x08
#define RF2XX_CC_OQPSK_SIN_250 0x0C
#define RF2XX_CC_OQPSK_RC_250 0x1C
/* ANT_DIV */
#define RF2XX_ANT_SEL 7
#define RF2XX_ANT_DIV_EN 3
#define RF2XX_ANT_EXT_SW_EN 2
#define RF2XX_ANT_CTRL 0
/* IRQ_MASK, IRQ_STATUS */
#define RF2XX_BAT_LOW 7
#define RF2XX_TRX_UR 6
#define RF2XX_AMI 5
#define RF2XX_CCA_ED_DONE 4
#define RF2XX_TRX_END 3
#define RF2XX_RX_START 2
#define RF2XX_PLL_UNLOCK 1
#define RF2XX_PLL_LOCK 0
/* VREG_CTRL */
#define RF2XX_AVREG_EXT 7
#define RF2XX_AVDD_OK 6
#define RF2XX_DVREG_EXT 3
#define RF2XX_DVDD_OK 2
/* BATMON */
#define RF2XX_PLL_LOCK_CP 7
#define RF2XX_BATMON_OK 5
#define RF2XX_BATMON_HR 4
#define RF2XX_BATMON_VTH 0
/* XOSC_CTRL */
#define RF2XX_XTAL_MODE 4
#define RF2XX_XTAL_TRIM 0
/* CC_CTRL_1 */
#define RF2XX_CC_BAND 0
/* RX_SYN */
#define RF2XX_RX_PDT_DIS 7
#define RF2XX_RX_OVERRIDE 4
#define RF2XX_RX_PDT_LEVEL 0
/* TRX_RPC */
#define RF2XX_RX_RPC_CTRL 6
#define RF2XX_RX_RPC_EN 5
#define RF2XX_PDT_RPC_EN 4
#define RF2XX_PLL_RPC_EN 3
#define RF2XX_XAH_TX_RPC_EN 2
#define RF2XX_IPAN_RPC_EN 1
/* RF_CTRL_0 */
#define RF2XX_PA_CHIP_LT 6
#define RF2XX_F_SHIFT_MODE 2
#define RF2XX_GC_TX_OFFS 0
#define RF2XX_GC_TX_OFFS_MASK 3
/* XAH_CTRL_1 */
#define RF2XX_ARET_TX_TS_EN 7
#define RF2XX_CSMA_LBT_MODE 6
#define RF2XX_AACK_FLTR_RES_FT 5
#define RF2XX_AACK_UPLD_RES_FT 4
#define RF2XX_AACK_ACK_TIME 2
#define RF2XX_AACK_PROM_MODE 1
#define RF2XX_AACK_SPC_EN 0
/* FTN_CTRL */
#define RF2XX_FTN_START 7
#define RF2XX_FTNV 0
/* RF_CTRL_1 */
#define RF2XX_RF_MC 4
/* XAH_CTRL_2 */
#define RF2XX_ARET_FRAME_RETRIES 4
#define RF2XX_ARET_CSMA_RETRIES 1
/* PLL_CF */
#define RF2XX_PLL_CF_START 7
#define RF2XX_PLL_CF 0
/* PLL_DCU */
#define RF2XX_PLL_DCU_START 7
/* XAH_CTRL_0 */
#define RF2XX_MAX_FRAME_RETRES 4
#define RF2XX_MAX_CSMA_RETRES 1
#define RF2XX_SLOTTED_OPERATION 0
/* CSMA_SEED_1 */
#define RF2XX_AACK_FVN_MODE 6
#define RF2XX_AACK_SET_PD 5
#define RF2XX_AACK_DIS_ACK 4
#define RF2XX_AACK_I_AM_COORD 3
#define RF2XX_CSMA_SEED_1 0
/* CSMA_BE */
#define RF2XX_MAX_BE 4
#define RF2XX_MIN_BE 0
/* TST_CTRL_DIGI */
#define RF2XX_TST_CTRL_DIG 0
/* PHY_TX_TIME_REG */
#define RF2XX_IRC_TX_TIME 0
/* TST_AGC_REG */
#define RF2XX_AGC_HOLD_SEL 5
#define RF2XX_AGC_RST 4
#define RF2XX_AGC_OFF 3
#define RF2XX_AGC_HOLD 2
#define RF2XX_GC 0
/* TST_SDM_REG */
#define RF2XX_MOD_SEL 7
#define RF2XX_MOD 6
#define RF2XX_TX_RX 5
#define RF2XX_TX_RX_SEL 4
/* AES_CTRL */
#define RF2XX_AES_CTRL_DIR 3
#define RF2XX_AES_CTRL_MODE 4
#define RF2XX_AES_CTRL_REQUEST 7
/* AES_STATUS */
#define RF2XX_AES_STATUS_DONE 0
#define RF2XX_AES_STATUS_ER 7
#define RF2XX_RF_CMD_REG_W ((1 << 7) | (1 << 6))
#define RF2XX_RF_CMD_REG_R ((1 << 7) | (0 << 6))
#define RF2XX_RF_CMD_FRAME_W ((0 << 7) | (1 << 6) | (1 << 5))
#define RF2XX_RF_CMD_FRAME_R ((0 << 7) | (0 << 6) | (1 << 5))
#define RF2XX_RF_CMD_SRAM_W ((0 << 7) | (1 << 6) | (0 << 5))
#define RF2XX_RF_CMD_SRAM_R ((0 << 7) | (0 << 6) | (0 << 5))
/* RX_STATUS */
#define RF2XX_RX_TRAC_STATUS 4
#define RF2XX_RX_TRAC_BIT_MASK RF2XX_TRAC_BIT_MASK
#endif /* ZEPHYR_DRIVERS_IEEE802154_IEEE802154_RF2XX_REGS_H_ */
``` | /content/code_sandbox/drivers/ieee802154/ieee802154_rf2xx_regs.h | objective-c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 3,146 |
```unknown
# TI CC13xx / CC26xx IEEE 802.15.4 configuration options
menuconfig IEEE802154_CC13XX_CC26XX
bool "TI CC13xx / CC26xx IEEE 802.15.4 driver support"
select CRC
default y
depends on DT_HAS_TI_CC13XX_CC26XX_IEEE802154_ENABLED
if IEEE802154_CC13XX_CC26XX
config IEEE802154_CC13XX_CC26XX_INIT_PRIO
int "TI CC13xx / CC26xx IEEE 802.15.4 initialization priority"
default 80
help
Set the initialization priority number.
config IEEE802154_CC13XX_CC26XX_RADIO_TX_RETRIES
int "Radio Transmission attempts"
default NET_L2_IEEE802154_RADIO_TX_RETRIES if NET_L2_IEEE802154
default 3
range 1 7
help
Number of transmission attempts radio driver should do, before
replying it could not send the packet.
config IEEE802154_CC13XX_CC26XX_RADIO_CSMA_CA_MAX_BO
int "CSMA maximum backoffs"
default NET_L2_IEEE802154_RADIO_CSMA_CA_MAX_BO if NET_L2_IEEE802154_RADIO_CSMA_CA
default 4
range 1 5
help
The maximum number of backoffs the CSMA-CA algorithm will attempt
before declaring a channel access failure.
config IEEE802154_CC13XX_CC26XX_RADIO_CSMA_CA_MIN_BE
int "CSMA MAC minimum backoff exponent"
default NET_L2_IEEE802154_RADIO_CSMA_CA_MIN_BE if NET_L2_IEEE802154_RADIO_CSMA_CA
default 3
range 1 8
help
The minimum value of the backoff exponent (BE) in the CSMA-CA
algorithm.
config IEEE802154_CC13XX_CC26XX_RADIO_CSMA_CA_MAX_BE
int "CSMA MAC maximum backoff exponent"
default NET_L2_IEEE802154_RADIO_CSMA_CA_MAX_BE if NET_L2_IEEE802154_RADIO_CSMA_CA
default 5
range 1 8
help
The maximum value of the backoff exponent (BE) in the CSMA-CA
algorithm.
endif # IEEE802154_CC13XX_CC26XX
menuconfig IEEE802154_CC13XX_CC26XX_SUB_GHZ
bool "TI CC13xx / CC26xx IEEE 802.15.4g driver support"
default y
depends on DT_HAS_TI_CC13XX_CC26XX_IEEE802154_SUBGHZ_ENABLED
if IEEE802154_CC13XX_CC26XX_SUB_GHZ
config IEEE802154_CC13XX_CC26XX_SUB_GHZ_NUM_RX_BUF
int "TI CC13xx / CC26xx IEEE 802.15.4g receive buffer count"
default 2
help
This option allows the user to configure the number of
receive buffers.
config IEEE802154_CC13XX_CC26XX_SUB_GHZ_CS_THRESHOLD
int "TI CC13xx / CC26xx IEEE 802.15.4g Carrier Sense ED Threshold in dBm"
default -80 # Based on SUN FSK, 200 kHz bit rate, no FEC, see IEEE 802.15.4-2020, section 19.6.7
help
This option sets the energy detection (ED) threshold for
clear channel assessment (CCA) modes 1 or 3 in the CSMA/CA
algorithm. Except for the SUN O-QPSK PHY, the ED threshold
shall correspond to a received signal power of at most 10 dB
greater than the specified receiver sensitivity for that PHY,
or in accordance with local regulations (see IEEE 802.15.4-2020,
section 10.2.8). For the SUN O-QPSK PHY, the ED threshold shall
comply with IEEE 802.15.4-2020, section 21.5.13.
config IEEE802154_CC13XX_CC26XX_SUB_GHZ_INIT_PRIO
int "TI CC13xx / CC26xx IEEE 802.15.4g initialization priority"
default 80
help
Set the initialization priority number.
config IEEE802154_CC13XX_CC26XX_SUB_GHZ_CUSTOM_RADIO_SETUP
bool "Use custom radio setup structures (advanced)"
default n
help
Imports the radio setup structure from an external module instead of using
the default one.
Allows overriding the RF modulation / protocol settings.
config IEEE802154_CC13XX_CC26XX_SUB_GHZ_CUSTOM_POWER_TABLE
bool "Use custom power table structure (advanced)"
default n
help
Imports the radio power table from an external module.
Allows overriding the RF modulation settings.
endif # IEEE802154_CC13XX_CC26XX_SUB_GHZ
``` | /content/code_sandbox/drivers/ieee802154/Kconfig.cc13xx_cc26xx | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 1,023 |
```c
/*
*
*/
#include <zephyr/logging/log.h>
LOG_MODULE_REGISTER(dw1000, LOG_LEVEL_INF);
#include <errno.h>
#include <zephyr/kernel.h>
#include <zephyr/arch/cpu.h>
#include <zephyr/debug/stack.h>
#include <zephyr/device.h>
#include <zephyr/init.h>
#include <zephyr/net/net_if.h>
#include <zephyr/net/net_pkt.h>
#include <zephyr/sys/byteorder.h>
#include <string.h>
#include <zephyr/random/random.h>
#include <zephyr/debug/stack.h>
#include <math.h>
#include <zephyr/drivers/gpio.h>
#include <zephyr/drivers/spi.h>
#include <zephyr/net/ieee802154_radio.h>
#include "ieee802154_dw1000_regs.h"
#define DT_DRV_COMPAT decawave_dw1000
#define DWT_FCS_LENGTH 2U
#define DWT_SPI_CSWAKEUP_FREQ 500000U
#define DWT_SPI_SLOW_FREQ 2000000U
#define DWT_SPI_TRANS_MAX_HDR_LEN 3
#define DWT_SPI_TRANS_REG_MAX_RANGE 0x3F
#define DWT_SPI_TRANS_SHORT_MAX_OFFSET 0x7F
#define DWT_SPI_TRANS_WRITE_OP BIT(7)
#define DWT_SPI_TRANS_SUB_ADDR BIT(6)
#define DWT_SPI_TRANS_EXTEND_ADDR BIT(7)
#define DWT_TS_TIME_UNITS_FS 15650U /* DWT_TIME_UNITS in fs */
#define DW1000_TX_ANT_DLY 16450
#define DW1000_RX_ANT_DLY 16450
/* SHR Symbol Duration in ns */
#define UWB_PHY_TPSYM_PRF64 IEEE802154_PHY_HRP_UWB_PRF64_TPSYM_SYMBOL_PERIOD_NS
#define UWB_PHY_TPSYM_PRF16 IEEE802154_PHY_HRP_UWB_PRF16_TPSYM_SYMBOL_PERIOD_NS
#define UWB_PHY_NUMOF_SYM_SHR_SFD 8
/* PHR Symbol Duration Tdsym in ns */
#define UWB_PHY_TDSYM_PHR_110K 8205.13
#define UWB_PHY_TDSYM_PHR_850K 1025.64
#define UWB_PHY_TDSYM_PHR_6M8 1025.64
#define UWB_PHY_NUMOF_SYM_PHR 18
/* Data Symbol Duration Tdsym in ns */
#define UWB_PHY_TDSYM_DATA_110K 8205.13
#define UWB_PHY_TDSYM_DATA_850K 1025.64
#define UWB_PHY_TDSYM_DATA_6M8 128.21
#define DWT_WORK_QUEUE_STACK_SIZE 512
static struct k_work_q dwt_work_queue;
static K_KERNEL_STACK_DEFINE(dwt_work_queue_stack,
DWT_WORK_QUEUE_STACK_SIZE);
struct dwt_phy_config {
uint8_t channel; /* Channel 1, 2, 3, 4, 5, 7 */
uint8_t dr; /* Data rate DWT_BR_110K, DWT_BR_850K, DWT_BR_6M8 */
uint8_t prf; /* PRF DWT_PRF_16M or DWT_PRF_64M */
uint8_t rx_pac_l; /* DWT_PAC8..DWT_PAC64 */
uint8_t rx_shr_code; /* RX SHR preamble code */
uint8_t rx_ns_sfd; /* non-standard SFD */
uint16_t rx_sfd_to; /* SFD timeout value (in symbols)
* (tx_shr_nsync + 1 + SFD_length - rx_pac_l)
*/
uint8_t tx_shr_code; /* TX SHR preamble code */
uint32_t tx_shr_nsync; /* PLEN index, e.g. DWT_PLEN_64 */
float t_shr;
float t_phr;
float t_dsym;
};
struct dwt_hi_cfg {
struct spi_dt_spec bus;
struct gpio_dt_spec irq_gpio;
struct gpio_dt_spec rst_gpio;
};
#define DWT_STATE_TX 0
#define DWT_STATE_CCA 1
#define DWT_STATE_RX_DEF_ON 2
struct dwt_context {
const struct device *dev;
struct net_if *iface;
const struct spi_config *spi_cfg;
struct spi_config spi_cfg_slow;
struct gpio_callback gpio_cb;
struct k_sem dev_lock;
struct k_sem phy_sem;
struct k_work irq_cb_work;
struct k_thread thread;
struct dwt_phy_config rf_cfg;
atomic_t state;
bool cca_busy;
uint16_t sleep_mode;
uint8_t mac_addr[8];
};
static const struct dwt_hi_cfg dw1000_0_config = {
.bus = SPI_DT_SPEC_INST_GET(0, SPI_WORD_SET(8), 0),
.irq_gpio = GPIO_DT_SPEC_INST_GET(0, int_gpios),
.rst_gpio = GPIO_DT_SPEC_INST_GET(0, reset_gpios),
};
static struct dwt_context dwt_0_context = {
.dev_lock = Z_SEM_INITIALIZER(dwt_0_context.dev_lock, 1, 1),
.phy_sem = Z_SEM_INITIALIZER(dwt_0_context.phy_sem, 0, 1),
.rf_cfg = {
.channel = 5,
.dr = DWT_BR_6M8,
.prf = DWT_PRF_64M,
.rx_pac_l = DWT_PAC8,
.rx_shr_code = 10,
.rx_ns_sfd = 0,
.rx_sfd_to = (129 + 8 - 8),
.tx_shr_code = 10,
.tx_shr_nsync = DWT_PLEN_128,
},
};
/* This struct is used to read all additional RX frame info at one push */
struct dwt_rx_info_regs {
uint8_t rx_fqual[DWT_RX_FQUAL_LEN];
uint8_t rx_ttcki[DWT_RX_TTCKI_LEN];
uint8_t rx_ttcko[DWT_RX_TTCKO_LEN];
/* RX_TIME without RX_RAWST */
uint8_t rx_time[DWT_RX_TIME_FP_RAWST_OFFSET];
} _packed;
static int dwt_configure_rf_phy(const struct device *dev);
static int dwt_spi_read(const struct device *dev,
uint16_t hdr_len, const uint8_t *hdr_buf,
uint32_t data_len, uint8_t *data)
{
struct dwt_context *ctx = dev->data;
const struct dwt_hi_cfg *hi_cfg = dev->config;
const struct spi_buf tx_buf = {
.buf = (uint8_t *)hdr_buf,
.len = hdr_len
};
const struct spi_buf_set tx = {
.buffers = &tx_buf,
.count = 1
};
struct spi_buf rx_buf[2] = {
{
.buf = NULL,
.len = hdr_len,
},
{
.buf = (uint8_t *)data,
.len = data_len,
},
};
const struct spi_buf_set rx = {
.buffers = rx_buf,
.count = 2
};
LOG_DBG("spi read, header length %u, data length %u",
(uint16_t)hdr_len, (uint32_t)data_len);
LOG_HEXDUMP_DBG(hdr_buf, (uint16_t)hdr_len, "rd: header");
if (spi_transceive(hi_cfg->bus.bus, ctx->spi_cfg, &tx, &rx)) {
LOG_ERR("SPI transfer failed");
return -EIO;
}
LOG_HEXDUMP_DBG(data, (uint32_t)data_len, "rd: data");
return 0;
}
static int dwt_spi_write(const struct device *dev,
uint16_t hdr_len, const uint8_t *hdr_buf,
uint32_t data_len, const uint8_t *data)
{
struct dwt_context *ctx = dev->data;
const struct dwt_hi_cfg *hi_cfg = dev->config;
struct spi_buf buf[2] = {
{.buf = (uint8_t *)hdr_buf, .len = hdr_len},
{.buf = (uint8_t *)data, .len = data_len}
};
struct spi_buf_set buf_set = {.buffers = buf, .count = 2};
LOG_DBG("spi write, header length %u, data length %u",
(uint16_t)hdr_len, (uint32_t)data_len);
LOG_HEXDUMP_DBG(hdr_buf, (uint16_t)hdr_len, "wr: header");
LOG_HEXDUMP_DBG(data, (uint32_t)data_len, "wr: data");
if (spi_write(hi_cfg->bus.bus, ctx->spi_cfg, &buf_set)) {
LOG_ERR("SPI read failed");
return -EIO;
}
return 0;
}
/* See 2.2.1.2 Transaction formats of the SPI interface */
static int dwt_spi_transfer(const struct device *dev,
uint8_t reg, uint16_t offset,
size_t buf_len, uint8_t *buf, bool write)
{
uint8_t hdr[DWT_SPI_TRANS_MAX_HDR_LEN] = {0};
size_t hdr_len = 0;
hdr[0] = reg & DWT_SPI_TRANS_REG_MAX_RANGE;
hdr_len += 1;
if (offset != 0) {
hdr[0] |= DWT_SPI_TRANS_SUB_ADDR;
hdr[1] = (uint8_t)offset & DWT_SPI_TRANS_SHORT_MAX_OFFSET;
hdr_len += 1;
if (offset > DWT_SPI_TRANS_SHORT_MAX_OFFSET) {
hdr[1] |= DWT_SPI_TRANS_EXTEND_ADDR;
hdr[2] = (uint8_t)(offset >> 7);
hdr_len += 1;
}
}
if (write) {
hdr[0] |= DWT_SPI_TRANS_WRITE_OP;
return dwt_spi_write(dev, hdr_len, hdr, buf_len, buf);
} else {
return dwt_spi_read(dev, hdr_len, hdr, buf_len, buf);
}
}
static int dwt_register_read(const struct device *dev,
uint8_t reg, uint16_t offset, size_t buf_len, uint8_t *buf)
{
return dwt_spi_transfer(dev, reg, offset, buf_len, buf, false);
}
static int dwt_register_write(const struct device *dev,
uint8_t reg, uint16_t offset, size_t buf_len, uint8_t *buf)
{
return dwt_spi_transfer(dev, reg, offset, buf_len, buf, true);
}
static inline uint32_t dwt_reg_read_u32(const struct device *dev,
uint8_t reg, uint16_t offset)
{
uint8_t buf[sizeof(uint32_t)];
dwt_spi_transfer(dev, reg, offset, sizeof(buf), buf, false);
return sys_get_le32(buf);
}
static inline uint16_t dwt_reg_read_u16(const struct device *dev,
uint8_t reg, uint16_t offset)
{
uint8_t buf[sizeof(uint16_t)];
dwt_spi_transfer(dev, reg, offset, sizeof(buf), buf, false);
return sys_get_le16(buf);
}
static inline uint8_t dwt_reg_read_u8(const struct device *dev,
uint8_t reg, uint16_t offset)
{
uint8_t buf;
dwt_spi_transfer(dev, reg, offset, sizeof(buf), &buf, false);
return buf;
}
static inline void dwt_reg_write_u32(const struct device *dev,
uint8_t reg, uint16_t offset, uint32_t val)
{
uint8_t buf[sizeof(uint32_t)];
sys_put_le32(val, buf);
dwt_spi_transfer(dev, reg, offset, sizeof(buf), buf, true);
}
static inline void dwt_reg_write_u16(const struct device *dev,
uint8_t reg, uint16_t offset, uint16_t val)
{
uint8_t buf[sizeof(uint16_t)];
sys_put_le16(val, buf);
dwt_spi_transfer(dev, reg, offset, sizeof(buf), buf, true);
}
static inline void dwt_reg_write_u8(const struct device *dev,
uint8_t reg, uint16_t offset, uint8_t val)
{
dwt_spi_transfer(dev, reg, offset, sizeof(uint8_t), &val, true);
}
static ALWAYS_INLINE void dwt_setup_int(const struct device *dev,
bool enable)
{
const struct dwt_hi_cfg *hi_cfg = dev->config;
unsigned int flags = enable
? GPIO_INT_EDGE_TO_ACTIVE
: GPIO_INT_DISABLE;
gpio_pin_interrupt_configure_dt(&hi_cfg->irq_gpio, flags);
}
static void dwt_reset_rfrx(const struct device *dev)
{
/*
* Apply a receiver-only soft reset,
* see SOFTRESET field description in DW1000 User Manual.
*/
dwt_reg_write_u8(dev, DWT_PMSC_ID, DWT_PMSC_CTRL0_SOFTRESET_OFFSET,
DWT_PMSC_CTRL0_RESET_RX);
dwt_reg_write_u8(dev, DWT_PMSC_ID, DWT_PMSC_CTRL0_SOFTRESET_OFFSET,
DWT_PMSC_CTRL0_RESET_CLEAR);
}
static void dwt_disable_txrx(const struct device *dev)
{
dwt_setup_int(dev, false);
dwt_reg_write_u8(dev, DWT_SYS_CTRL_ID, DWT_SYS_CTRL_OFFSET,
DWT_SYS_CTRL_TRXOFF);
dwt_reg_write_u32(dev, DWT_SYS_STATUS_ID, DWT_SYS_STATUS_OFFSET,
(DWT_SYS_STATUS_ALL_RX_GOOD |
DWT_SYS_STATUS_ALL_RX_TO |
DWT_SYS_STATUS_ALL_RX_ERR |
DWT_SYS_STATUS_ALL_TX));
dwt_setup_int(dev, true);
}
/* timeout time in units of 1.026 microseconds */
static int dwt_enable_rx(const struct device *dev, uint16_t timeout)
{
uint32_t sys_cfg;
uint16_t sys_ctrl = DWT_SYS_CTRL_RXENAB;
sys_cfg = dwt_reg_read_u32(dev, DWT_SYS_CFG_ID, 0);
if (timeout != 0) {
dwt_reg_write_u16(dev, DWT_RX_FWTO_ID, DWT_RX_FWTO_OFFSET,
timeout);
sys_cfg |= DWT_SYS_CFG_RXWTOE;
} else {
sys_cfg &= ~DWT_SYS_CFG_RXWTOE;
}
dwt_reg_write_u32(dev, DWT_SYS_CFG_ID, 0, sys_cfg);
dwt_reg_write_u16(dev, DWT_SYS_CTRL_ID, DWT_SYS_CTRL_OFFSET, sys_ctrl);
return 0;
}
static inline void dwt_irq_handle_rx_cca(const struct device *dev)
{
struct dwt_context *ctx = dev->data;
k_sem_give(&ctx->phy_sem);
ctx->cca_busy = true;
/* Clear all RX event bits */
dwt_reg_write_u32(dev, DWT_SYS_STATUS_ID, 0,
DWT_SYS_STATUS_ALL_RX_GOOD);
}
static inline void dwt_irq_handle_rx(const struct device *dev, uint32_t sys_stat)
{
struct dwt_context *ctx = dev->data;
struct net_pkt *pkt = NULL;
struct dwt_rx_info_regs rx_inf_reg;
float a_const;
uint32_t rx_finfo;
uint32_t ttcki;
uint32_t rx_pacc;
uint32_t cir_pwr;
uint32_t flags_to_clear;
int32_t ttcko;
uint16_t pkt_len;
uint8_t *fctrl;
int8_t rx_level = INT8_MIN;
LOG_DBG("RX OK event, SYS_STATUS 0x%08x", sys_stat);
flags_to_clear = sys_stat & DWT_SYS_STATUS_ALL_RX_GOOD;
rx_finfo = dwt_reg_read_u32(dev, DWT_RX_FINFO_ID, DWT_RX_FINFO_OFFSET);
pkt_len = rx_finfo & DWT_RX_FINFO_RXFLEN_MASK;
rx_pacc = (rx_finfo & DWT_RX_FINFO_RXPACC_MASK) >>
DWT_RX_FINFO_RXPACC_SHIFT;
if (!(IS_ENABLED(CONFIG_IEEE802154_RAW_MODE))) {
pkt_len -= DWT_FCS_LENGTH;
}
pkt = net_pkt_rx_alloc_with_buffer(ctx->iface, pkt_len,
AF_UNSPEC, 0, K_NO_WAIT);
if (!pkt) {
LOG_ERR("No buf available");
goto rx_out_enable_rx;
}
dwt_register_read(dev, DWT_RX_BUFFER_ID, 0, pkt_len, pkt->buffer->data);
dwt_register_read(dev, DWT_RX_FQUAL_ID, 0, sizeof(rx_inf_reg),
(uint8_t *)&rx_inf_reg);
net_buf_add(pkt->buffer, pkt_len);
fctrl = pkt->buffer->data;
/*
* Get Ranging tracking offset and tracking interval
* for Crystal characterization
*/
ttcki = sys_get_le32(rx_inf_reg.rx_ttcki);
ttcko = sys_get_le32(rx_inf_reg.rx_ttcko) & DWT_RX_TTCKO_RXTOFS_MASK;
/* Tracking offset value is a 19-bit signed integer */
if (ttcko & BIT(18)) {
ttcko |= ~DWT_RX_TTCKO_RXTOFS_MASK;
}
/* TODO add:
* net_pkt_set_ieee802154_tcki(pkt, ttcki);
* net_pkt_set_ieee802154_tcko(pkt, ttcko);
*/
LOG_DBG("ttcko %d ttcki: 0x%08x", ttcko, ttcki);
if (IS_ENABLED(CONFIG_NET_PKT_TIMESTAMP)) {
uint8_t ts_buf[sizeof(uint64_t)] = {0};
uint64_t ts_nsec;
memcpy(ts_buf, rx_inf_reg.rx_time, DWT_RX_TIME_RX_STAMP_LEN);
ts_nsec = (sys_get_le64(ts_buf) * DWT_TS_TIME_UNITS_FS) / 1000000U;
net_pkt_set_timestamp_ns(pkt, ts_nsec);
}
/* See 4.7.2 Estimating the receive signal power */
cir_pwr = sys_get_le16(&rx_inf_reg.rx_fqual[6]);
if (ctx->rf_cfg.prf == DWT_PRF_16M) {
a_const = DWT_RX_SIG_PWR_A_CONST_PRF16;
} else {
a_const = DWT_RX_SIG_PWR_A_CONST_PRF64;
}
if (rx_pacc != 0) {
#if defined(CONFIG_NEWLIB_LIBC)
/* From 4.7.2 Estimating the receive signal power */
rx_level = 10.0 * log10f(cir_pwr * BIT(17) /
(rx_pacc * rx_pacc)) - a_const;
#endif
}
net_pkt_set_ieee802154_rssi_dbm(pkt, rx_level);
/*
* Workaround for AAT status bit issue,
* From 5.3.5 Host Notification in DW1000 User Manual:
* "Note: there is a situation that can result in the AAT bit being set
* for the current frame as a result of a previous frame that was
* received and rejected due to frame filtering."
*/
if ((sys_stat & DWT_SYS_STATUS_AAT) && ((fctrl[0] & 0x20) == 0)) {
flags_to_clear |= DWT_SYS_STATUS_AAT;
}
if (ieee802154_handle_ack(ctx->iface, pkt) == NET_OK) {
LOG_INF("ACK packet handled");
goto rx_out_unref_pkt;
}
/* LQI not implemented */
LOG_DBG("Caught a packet (%u) (RSSI: %d)", pkt_len, rx_level);
LOG_HEXDUMP_DBG(pkt->buffer->data, pkt_len, "RX buffer:");
if (net_recv_data(ctx->iface, pkt) == NET_OK) {
goto rx_out_enable_rx;
} else {
LOG_DBG("Packet dropped by NET stack");
}
rx_out_unref_pkt:
if (pkt) {
net_pkt_unref(pkt);
}
rx_out_enable_rx:
dwt_reg_write_u32(dev, DWT_SYS_STATUS_ID, 0, flags_to_clear);
LOG_DBG("Cleared SYS_STATUS flags 0x%08x", flags_to_clear);
if (atomic_test_bit(&ctx->state, DWT_STATE_RX_DEF_ON)) {
/*
* Re-enable reception but in contrast to dwt_enable_rx()
* without to read SYS_STATUS and set delayed option.
*/
dwt_reg_write_u16(dev, DWT_SYS_CTRL_ID, DWT_SYS_CTRL_OFFSET,
DWT_SYS_CTRL_RXENAB);
}
}
static void dwt_irq_handle_tx(const struct device *dev, uint32_t sys_stat)
{
struct dwt_context *ctx = dev->data;
/* Clear TX event bits */
dwt_reg_write_u32(dev, DWT_SYS_STATUS_ID, 0,
DWT_SYS_STATUS_ALL_TX);
LOG_DBG("TX confirmed event");
k_sem_give(&ctx->phy_sem);
}
static void dwt_irq_handle_rxto(const struct device *dev, uint32_t sys_stat)
{
struct dwt_context *ctx = dev->data;
/* Clear RX timeout event bits */
dwt_reg_write_u32(dev, DWT_SYS_STATUS_ID, 0,
DWT_SYS_STATUS_RXRFTO);
dwt_disable_txrx(dev);
/* Receiver reset necessary, see 4.1.6 RX Message timestamp */
dwt_reset_rfrx(dev);
LOG_DBG("RX timeout event");
if (atomic_test_bit(&ctx->state, DWT_STATE_CCA)) {
k_sem_give(&ctx->phy_sem);
ctx->cca_busy = false;
}
}
static void dwt_irq_handle_error(const struct device *dev, uint32_t sys_stat)
{
struct dwt_context *ctx = dev->data;
/* Clear RX error event bits */
dwt_reg_write_u32(dev, DWT_SYS_STATUS_ID, 0, DWT_SYS_STATUS_ALL_RX_ERR);
dwt_disable_txrx(dev);
/* Receiver reset necessary, see 4.1.6 RX Message timestamp */
dwt_reset_rfrx(dev);
LOG_INF("RX error event");
if (atomic_test_bit(&ctx->state, DWT_STATE_CCA)) {
k_sem_give(&ctx->phy_sem);
ctx->cca_busy = true;
return;
}
if (atomic_test_bit(&ctx->state, DWT_STATE_RX_DEF_ON)) {
dwt_enable_rx(dev, 0);
}
}
static void dwt_irq_work_handler(struct k_work *item)
{
struct dwt_context *ctx = CONTAINER_OF(item, struct dwt_context,
irq_cb_work);
const struct device *dev = ctx->dev;
uint32_t sys_stat;
k_sem_take(&ctx->dev_lock, K_FOREVER);
sys_stat = dwt_reg_read_u32(dev, DWT_SYS_STATUS_ID, 0);
if (sys_stat & DWT_SYS_STATUS_RXFCG) {
if (atomic_test_bit(&ctx->state, DWT_STATE_CCA)) {
dwt_irq_handle_rx_cca(dev);
} else {
dwt_irq_handle_rx(dev, sys_stat);
}
}
if (sys_stat & DWT_SYS_STATUS_TXFRS) {
dwt_irq_handle_tx(dev, sys_stat);
}
if (sys_stat & DWT_SYS_STATUS_ALL_RX_TO) {
dwt_irq_handle_rxto(dev, sys_stat);
}
if (sys_stat & DWT_SYS_STATUS_ALL_RX_ERR) {
dwt_irq_handle_error(dev, sys_stat);
}
k_sem_give(&ctx->dev_lock);
}
static void dwt_gpio_callback(const struct device *dev,
struct gpio_callback *cb, uint32_t pins)
{
struct dwt_context *ctx = CONTAINER_OF(cb, struct dwt_context, gpio_cb);
LOG_DBG("IRQ callback triggered %p", ctx);
k_work_submit_to_queue(&dwt_work_queue, &ctx->irq_cb_work);
}
static enum ieee802154_hw_caps dwt_get_capabilities(const struct device *dev)
{
/* TODO: Implement HW-supported AUTOACK + frame pending bit handling. */
return IEEE802154_HW_FCS | IEEE802154_HW_FILTER |
IEEE802154_HW_TXTIME;
}
static uint32_t dwt_get_pkt_duration_ns(struct dwt_context *ctx, uint8_t psdu_len)
{
struct dwt_phy_config *rf_cfg = &ctx->rf_cfg;
float t_psdu = rf_cfg->t_dsym * psdu_len * 8;
return (rf_cfg->t_shr + rf_cfg->t_phr + t_psdu);
}
static int dwt_cca(const struct device *dev)
{
struct dwt_context *ctx = dev->data;
uint32_t cca_dur = (dwt_get_pkt_duration_ns(ctx, 127) +
dwt_get_pkt_duration_ns(ctx, 5)) /
UWB_PHY_TDSYM_PHR_6M8;
if (atomic_test_and_set_bit(&ctx->state, DWT_STATE_CCA)) {
LOG_ERR("Transceiver busy");
return -EBUSY;
}
/* Perform CCA Mode 5 */
k_sem_take(&ctx->dev_lock, K_FOREVER);
dwt_disable_txrx(dev);
LOG_DBG("CCA duration %u us", cca_dur);
dwt_enable_rx(dev, cca_dur);
k_sem_give(&ctx->dev_lock);
k_sem_take(&ctx->phy_sem, K_FOREVER);
LOG_DBG("CCA finished %p", ctx);
atomic_clear_bit(&ctx->state, DWT_STATE_CCA);
if (atomic_test_bit(&ctx->state, DWT_STATE_RX_DEF_ON)) {
k_sem_take(&ctx->dev_lock, K_FOREVER);
dwt_enable_rx(dev, 0);
k_sem_give(&ctx->dev_lock);
}
return ctx->cca_busy ? -EBUSY : 0;
}
static int dwt_ed(const struct device *dev, uint16_t duration,
energy_scan_done_cb_t done_cb)
{
/* TODO: see description Sub-Register 0x23:02 AGC_CTRL1 */
return -ENOTSUP;
}
static int dwt_set_channel(const struct device *dev, uint16_t channel)
{
struct dwt_context *ctx = dev->data;
struct dwt_phy_config *rf_cfg = &ctx->rf_cfg;
if (channel > 15) {
return -EINVAL;
}
if (channel == 0 || channel == 6 || channel > 7) {
return -ENOTSUP;
}
rf_cfg->channel = channel;
LOG_INF("Set channel %u", channel);
k_sem_take(&ctx->dev_lock, K_FOREVER);
dwt_disable_txrx(dev);
dwt_configure_rf_phy(dev);
if (atomic_test_bit(&ctx->state, DWT_STATE_RX_DEF_ON)) {
dwt_enable_rx(dev, 0);
}
k_sem_give(&ctx->dev_lock);
return 0;
}
static int dwt_set_pan_id(const struct device *dev, uint16_t pan_id)
{
struct dwt_context *ctx = dev->data;
k_sem_take(&ctx->dev_lock, K_FOREVER);
dwt_reg_write_u16(dev, DWT_PANADR_ID, DWT_PANADR_PAN_ID_OFFSET, pan_id);
k_sem_give(&ctx->dev_lock);
LOG_INF("Set PAN ID 0x%04x %p", pan_id, ctx);
return 0;
}
static int dwt_set_short_addr(const struct device *dev, uint16_t short_addr)
{
struct dwt_context *ctx = dev->data;
k_sem_take(&ctx->dev_lock, K_FOREVER);
dwt_reg_write_u16(dev, DWT_PANADR_ID, DWT_PANADR_SHORT_ADDR_OFFSET,
short_addr);
k_sem_give(&ctx->dev_lock);
LOG_INF("Set short 0x%x %p", short_addr, ctx);
return 0;
}
static int dwt_set_ieee_addr(const struct device *dev,
const uint8_t *ieee_addr)
{
struct dwt_context *ctx = dev->data;
LOG_INF("IEEE address %02x:%02x:%02x:%02x:%02x:%02x:%02x:%02x",
ieee_addr[7], ieee_addr[6], ieee_addr[5], ieee_addr[4],
ieee_addr[3], ieee_addr[2], ieee_addr[1], ieee_addr[0]);
k_sem_take(&ctx->dev_lock, K_FOREVER);
dwt_register_write(dev, DWT_EUI_64_ID, DWT_EUI_64_OFFSET,
DWT_EUI_64_LEN, (uint8_t *)ieee_addr);
k_sem_give(&ctx->dev_lock);
return 0;
}
static int dwt_filter(const struct device *dev,
bool set,
enum ieee802154_filter_type type,
const struct ieee802154_filter *filter)
{
if (!set) {
return -ENOTSUP;
}
if (type == IEEE802154_FILTER_TYPE_IEEE_ADDR) {
return dwt_set_ieee_addr(dev, filter->ieee_addr);
} else if (type == IEEE802154_FILTER_TYPE_SHORT_ADDR) {
return dwt_set_short_addr(dev, filter->short_addr);
} else if (type == IEEE802154_FILTER_TYPE_PAN_ID) {
return dwt_set_pan_id(dev, filter->pan_id);
}
return -ENOTSUP;
}
static int dwt_set_power(const struct device *dev, int16_t dbm)
{
struct dwt_context *ctx = dev->data;
LOG_INF("set_txpower not supported %p", ctx);
return 0;
}
static int dwt_tx(const struct device *dev, enum ieee802154_tx_mode tx_mode,
struct net_pkt *pkt, struct net_buf *frag)
{
struct dwt_context *ctx = dev->data;
size_t len = frag->len;
uint32_t tx_time = 0;
uint64_t tmp_fs;
uint32_t tx_fctrl;
uint8_t sys_ctrl = DWT_SYS_CTRL_TXSTRT;
if (atomic_test_and_set_bit(&ctx->state, DWT_STATE_TX)) {
LOG_ERR("Transceiver busy");
return -EBUSY;
}
k_sem_reset(&ctx->phy_sem);
k_sem_take(&ctx->dev_lock, K_FOREVER);
switch (tx_mode) {
case IEEE802154_TX_MODE_DIRECT:
break;
case IEEE802154_TX_MODE_TXTIME:
/*
* tx_time is the high 32-bit of the 40-bit system
* time value at which to send the message.
*/
tmp_fs = net_pkt_timestamp_ns(pkt);
tmp_fs *= 1000U * 1000U;
tx_time = (tmp_fs / DWT_TS_TIME_UNITS_FS) >> 8;
sys_ctrl |= DWT_SYS_CTRL_TXDLYS;
/* DX_TIME is 40-bit register */
dwt_reg_write_u32(dev, DWT_DX_TIME_ID, 1, tx_time);
LOG_DBG("ntx hi32 %x", tx_time);
LOG_DBG("sys hi32 %x",
dwt_reg_read_u32(dev, DWT_SYS_TIME_ID, 1));
break;
default:
LOG_ERR("TX mode %d not supported", tx_mode);
goto error;
}
LOG_HEXDUMP_DBG(frag->data, len, "TX buffer:");
/*
* See "3 Message Transmission" in DW1000 User Manual for
* more details about transmission configuration.
*/
if (dwt_register_write(dev, DWT_TX_BUFFER_ID, 0, len, frag->data)) {
LOG_ERR("Failed to write TX data");
goto error;
}
tx_fctrl = dwt_reg_read_u32(dev, DWT_TX_FCTRL_ID, 0);
/* Clear TX buffer index offset, frame length, and length extension */
tx_fctrl &= ~(DWT_TX_FCTRL_TFLEN_MASK | DWT_TX_FCTRL_TFLE_MASK |
DWT_TX_FCTRL_TXBOFFS_MASK);
/* Set frame length and ranging flag */
tx_fctrl |= (len + DWT_FCS_LENGTH) & DWT_TX_FCTRL_TFLEN_MASK;
tx_fctrl |= DWT_TX_FCTRL_TR;
/* Update Transmit Frame Control register */
dwt_reg_write_u32(dev, DWT_TX_FCTRL_ID, 0, tx_fctrl);
dwt_disable_txrx(dev);
/* Begin transmission */
dwt_reg_write_u8(dev, DWT_SYS_CTRL_ID, DWT_SYS_CTRL_OFFSET, sys_ctrl);
if (sys_ctrl & DWT_SYS_CTRL_TXDLYS) {
uint32_t sys_stat = dwt_reg_read_u32(dev, DWT_SYS_STATUS_ID, 0);
if (sys_stat & DWT_SYS_STATUS_HPDWARN) {
LOG_WRN("Half Period Delay Warning");
}
}
k_sem_give(&ctx->dev_lock);
/* Wait for the TX confirmed event */
k_sem_take(&ctx->phy_sem, K_FOREVER);
if (IS_ENABLED(CONFIG_NET_PKT_TIMESTAMP)) {
uint8_t ts_buf[sizeof(uint64_t)] = {0};
k_sem_take(&ctx->dev_lock, K_FOREVER);
dwt_register_read(dev, DWT_TX_TIME_ID,
DWT_TX_TIME_TX_STAMP_OFFSET,
DWT_TX_TIME_TX_STAMP_LEN,
ts_buf);
LOG_DBG("ts hi32 %x", (uint32_t)(sys_get_le64(ts_buf) >> 8));
LOG_DBG("sys hi32 %x",
dwt_reg_read_u32(dev, DWT_SYS_TIME_ID, 1));
k_sem_give(&ctx->dev_lock);
tmp_fs = sys_get_le64(ts_buf) * DWT_TS_TIME_UNITS_FS;
net_pkt_set_timestamp_ns(pkt, tmp_fs / 1000000U);
}
atomic_clear_bit(&ctx->state, DWT_STATE_TX);
if (atomic_test_bit(&ctx->state, DWT_STATE_RX_DEF_ON)) {
k_sem_take(&ctx->dev_lock, K_FOREVER);
dwt_enable_rx(dev, 0);
k_sem_give(&ctx->dev_lock);
}
return 0;
error:
atomic_clear_bit(&ctx->state, DWT_STATE_TX);
k_sem_give(&ctx->dev_lock);
return -EIO;
}
static void dwt_set_frame_filter(const struct device *dev,
bool ff_enable, uint8_t ff_type)
{
uint32_t sys_cfg_ff = ff_enable ? DWT_SYS_CFG_FFE : 0;
sys_cfg_ff |= ff_type & DWT_SYS_CFG_FF_ALL_EN;
dwt_reg_write_u8(dev, DWT_SYS_CFG_ID, 0, (uint8_t)sys_cfg_ff);
}
static int dwt_configure(const struct device *dev,
enum ieee802154_config_type type,
const struct ieee802154_config *config)
{
struct dwt_context *ctx = dev->data;
LOG_DBG("API configure %p", ctx);
switch (type) {
case IEEE802154_CONFIG_AUTO_ACK_FPB:
LOG_DBG("IEEE802154_CONFIG_AUTO_ACK_FPB");
break;
case IEEE802154_CONFIG_ACK_FPB:
LOG_DBG("IEEE802154_CONFIG_ACK_FPB");
break;
case IEEE802154_CONFIG_PAN_COORDINATOR:
LOG_DBG("IEEE802154_CONFIG_PAN_COORDINATOR");
break;
case IEEE802154_CONFIG_PROMISCUOUS:
LOG_DBG("IEEE802154_CONFIG_PROMISCUOUS");
break;
case IEEE802154_CONFIG_EVENT_HANDLER:
LOG_DBG("IEEE802154_CONFIG_EVENT_HANDLER");
break;
default:
return -EINVAL;
}
return -ENOTSUP;
}
/* driver-allocated attribute memory - constant across all driver instances */
static const struct {
const struct ieee802154_phy_channel_range phy_channel_range[2];
const struct ieee802154_phy_supported_channels phy_supported_channels;
} drv_attr = {
.phy_channel_range = {
{ .from_channel = 1, .to_channel = 5 },
{ .from_channel = 7, .to_channel = 7 },
},
.phy_supported_channels = {
.ranges = drv_attr.phy_channel_range,
.num_ranges = 2U,
},
};
static int dwt_attr_get(const struct device *dev, enum ieee802154_attr attr,
struct ieee802154_attr_value *value)
{
if (ieee802154_attr_get_channel_page_and_range(
attr, IEEE802154_ATTR_PHY_CHANNEL_PAGE_FOUR_HRP_UWB,
&drv_attr.phy_supported_channels, value) == 0) {
return 0;
}
switch (attr) {
case IEEE802154_ATTR_PHY_HRP_UWB_SUPPORTED_PRFS: {
struct dwt_context *ctx = dev->data;
struct dwt_phy_config *rf_cfg = &ctx->rf_cfg;
value->phy_hrp_uwb_supported_nominal_prfs =
rf_cfg->prf == DWT_PRF_64M ? IEEE802154_PHY_HRP_UWB_NOMINAL_64_M
: IEEE802154_PHY_HRP_UWB_NOMINAL_16_M;
return 0;
}
default:
return -ENOENT;
}
}
/*
* Note, the DW_RESET pin should not be driven high externally.
*/
static int dwt_hw_reset(const struct device *dev)
{
const struct dwt_hi_cfg *hi_cfg = dev->config;
if (gpio_pin_configure_dt(&hi_cfg->rst_gpio, GPIO_OUTPUT_ACTIVE)) {
LOG_ERR("Failed to configure GPIO pin %u", hi_cfg->rst_gpio.pin);
return -EINVAL;
}
k_sleep(K_MSEC(1));
gpio_pin_set_dt(&hi_cfg->rst_gpio, 0);
k_sleep(K_MSEC(5));
if (gpio_pin_configure_dt(&hi_cfg->rst_gpio, GPIO_INPUT)) {
LOG_ERR("Failed to configure GPIO pin %u", hi_cfg->rst_gpio.pin);
return -EINVAL;
}
return 0;
}
/*
* SPI speed in INIT state or for wake-up sequence,
* see 2.3.2 Overview of main operational states
*/
static void dwt_set_spi_slow(const struct device *dev, const uint32_t freq)
{
struct dwt_context *ctx = dev->data;
ctx->spi_cfg_slow.frequency = freq;
ctx->spi_cfg = &ctx->spi_cfg_slow;
}
/* SPI speed in IDLE, RX, and TX state */
static void dwt_set_spi_fast(const struct device *dev)
{
const struct dwt_hi_cfg *hi_cfg = dev->config;
struct dwt_context *ctx = dev->data;
ctx->spi_cfg = &hi_cfg->bus.config;
}
static void dwt_set_rx_mode(const struct device *dev)
{
struct dwt_context *ctx = dev->data;
struct dwt_phy_config *rf_cfg = &ctx->rf_cfg;
uint32_t pmsc_ctrl0;
uint32_t t_on_us;
uint8_t rx_sniff[2];
/* SNIFF Mode ON time in units of PAC */
rx_sniff[0] = CONFIG_IEEE802154_DW1000_SNIFF_ONT &
DWT_RX_SNIFF_SNIFF_ONT_MASK;
/* SNIFF Mode OFF time in microseconds */
rx_sniff[1] = CONFIG_IEEE802154_DW1000_SNIFF_OFFT;
t_on_us = (rx_sniff[0] + 1) * (BIT(3) << rf_cfg->rx_pac_l);
LOG_INF("RX duty cycle %u%%", t_on_us * 100 / (t_on_us + rx_sniff[1]));
dwt_register_write(dev, DWT_RX_SNIFF_ID, DWT_RX_SNIFF_OFFSET,
sizeof(rx_sniff), rx_sniff);
pmsc_ctrl0 = dwt_reg_read_u32(dev, DWT_PMSC_ID, DWT_PMSC_CTRL0_OFFSET);
/* Enable PLL2 on/off sequencing for SNIFF mode */
pmsc_ctrl0 |= DWT_PMSC_CTRL0_PLL2_SEQ_EN;
dwt_reg_write_u32(dev, DWT_PMSC_ID, DWT_PMSC_CTRL0_OFFSET, pmsc_ctrl0);
}
static int dwt_start(const struct device *dev)
{
struct dwt_context *ctx = dev->data;
uint8_t cswakeup_buf[32] = {0};
k_sem_take(&ctx->dev_lock, K_FOREVER);
/* Set SPI clock to lowest frequency */
dwt_set_spi_slow(dev, DWT_SPI_CSWAKEUP_FREQ);
if (dwt_reg_read_u32(dev, DWT_DEV_ID_ID, 0) != DWT_DEVICE_ID) {
/* Keep SPI CS line low for 500 microseconds */
dwt_register_read(dev, 0, 0, sizeof(cswakeup_buf),
cswakeup_buf);
/* Give device time to initialize */
k_sleep(K_MSEC(5));
if (dwt_reg_read_u32(dev, DWT_DEV_ID_ID, 0) != DWT_DEVICE_ID) {
LOG_ERR("Failed to wake-up %p", dev);
k_sem_give(&ctx->dev_lock);
return -1;
}
} else {
LOG_WRN("Device not in a sleep mode");
}
/* Restore SPI clock settings */
dwt_set_spi_slow(dev, DWT_SPI_SLOW_FREQ);
dwt_set_spi_fast(dev);
dwt_setup_int(dev, true);
dwt_disable_txrx(dev);
dwt_reset_rfrx(dev);
if (CONFIG_IEEE802154_DW1000_SNIFF_ONT != 0) {
dwt_set_rx_mode(dev);
}
/* Re-enable RX after packet reception */
atomic_set_bit(&ctx->state, DWT_STATE_RX_DEF_ON);
dwt_enable_rx(dev, 0);
k_sem_give(&ctx->dev_lock);
LOG_INF("Started %p", dev);
return 0;
}
static int dwt_stop(const struct device *dev)
{
struct dwt_context *ctx = dev->data;
k_sem_take(&ctx->dev_lock, K_FOREVER);
dwt_disable_txrx(dev);
dwt_reset_rfrx(dev);
dwt_setup_int(dev, false);
/* Copy the user configuration and enter sleep mode */
dwt_reg_write_u8(dev, DWT_AON_ID, DWT_AON_CTRL_OFFSET,
DWT_AON_CTRL_SAVE);
k_sem_give(&ctx->dev_lock);
LOG_INF("Stopped %p", dev);
return 0;
}
static inline void dwt_set_sysclks_xti(const struct device *dev, bool ldeload)
{
uint16_t clks = BIT(9) | DWT_PMSC_CTRL0_SYSCLKS_19M;
/*
* See Table 4: Register accesses required to load LDE microcode,
* set PMSC_CTRL0 0x0301, load LDE, set PMSC_CTRL0 0x0200.
*/
if (ldeload) {
clks |= BIT(8);
}
/* Force system clock to be the 19.2 MHz XTI clock */
dwt_reg_write_u16(dev, DWT_PMSC_ID, DWT_PMSC_CTRL0_OFFSET, clks);
}
static inline void dwt_set_sysclks_auto(const struct device *dev)
{
uint8_t sclks = DWT_PMSC_CTRL0_SYSCLKS_AUTO |
DWT_PMSC_CTRL0_RXCLKS_AUTO |
DWT_PMSC_CTRL0_TXCLKS_AUTO;
dwt_reg_write_u8(dev, DWT_PMSC_ID, DWT_PMSC_CTRL0_OFFSET, sclks);
}
static uint32_t dwt_otpmem_read(const struct device *dev, uint16_t otp_addr)
{
dwt_reg_write_u16(dev, DWT_OTP_IF_ID, DWT_OTP_ADDR, otp_addr);
dwt_reg_write_u8(dev, DWT_OTP_IF_ID, DWT_OTP_CTRL,
DWT_OTP_CTRL_OTPREAD | DWT_OTP_CTRL_OTPRDEN);
/* OTPREAD is self clearing but OTPRDEN is not */
dwt_reg_write_u8(dev, DWT_OTP_IF_ID, DWT_OTP_CTRL, 0x00);
/* Read read data, available 40ns after rising edge of OTP_READ */
return dwt_reg_read_u32(dev, DWT_OTP_IF_ID, DWT_OTP_RDAT);
}
static int dwt_initialise_dev(const struct device *dev)
{
struct dwt_context *ctx = dev->data;
uint32_t otp_val = 0;
uint8_t xtal_trim;
dwt_set_sysclks_xti(dev, false);
ctx->sleep_mode = 0;
/* Disable PMSC control of analog RF subsystem */
dwt_reg_write_u16(dev, DWT_PMSC_ID, DWT_PMSC_CTRL1_OFFSET,
DWT_PMSC_CTRL1_PKTSEQ_DISABLE);
/* Clear all status flags */
dwt_reg_write_u32(dev, DWT_SYS_STATUS_ID, 0, DWT_SYS_STATUS_MASK_32);
/*
* Apply soft reset,
* see SOFTRESET field description in DW1000 User Manual.
*/
dwt_reg_write_u8(dev, DWT_PMSC_ID, DWT_PMSC_CTRL0_SOFTRESET_OFFSET,
DWT_PMSC_CTRL0_RESET_ALL);
k_sleep(K_MSEC(1));
dwt_reg_write_u8(dev, DWT_PMSC_ID, DWT_PMSC_CTRL0_SOFTRESET_OFFSET,
DWT_PMSC_CTRL0_RESET_CLEAR);
dwt_set_sysclks_xti(dev, false);
/*
* This bit (a.k.a PLLLDT) should be set to ensure reliable
* operation of the CPLOCK bit.
*/
dwt_reg_write_u8(dev, DWT_EXT_SYNC_ID, DWT_EC_CTRL_OFFSET,
DWT_EC_CTRL_PLLLCK);
/* Kick LDO if there is a value programmed. */
otp_val = dwt_otpmem_read(dev, DWT_OTP_LDOTUNE_ADDR);
if ((otp_val & 0xFF) != 0) {
dwt_reg_write_u8(dev, DWT_OTP_IF_ID, DWT_OTP_SF,
DWT_OTP_SF_LDO_KICK);
ctx->sleep_mode |= DWT_AON_WCFG_ONW_LLDO;
LOG_INF("Load LDOTUNE_CAL parameter");
}
otp_val = dwt_otpmem_read(dev, DWT_OTP_XTRIM_ADDR);
xtal_trim = otp_val & DWT_FS_XTALT_MASK;
LOG_INF("OTP Revision 0x%02x, XTAL Trim 0x%02x",
(uint8_t)(otp_val >> 8), xtal_trim);
LOG_DBG("CHIP ID 0x%08x", dwt_otpmem_read(dev, DWT_OTP_PARTID_ADDR));
LOG_DBG("LOT ID 0x%08x", dwt_otpmem_read(dev, DWT_OTP_LOTID_ADDR));
LOG_DBG("Vbat 0x%02x", dwt_otpmem_read(dev, DWT_OTP_VBAT_ADDR));
LOG_DBG("Vtemp 0x%02x", dwt_otpmem_read(dev, DWT_OTP_VTEMP_ADDR));
if (xtal_trim == 0) {
/* Set to default */
xtal_trim = DWT_FS_XTALT_MIDRANGE;
}
/* For FS_XTALT bits 7:5 must always be set to binary 011 */
xtal_trim |= BIT(6) | BIT(5);
dwt_reg_write_u8(dev, DWT_FS_CTRL_ID, DWT_FS_XTALT_OFFSET, xtal_trim);
/* Load LDE microcode into RAM, see 2.5.5.10 LDELOAD */
dwt_set_sysclks_xti(dev, true);
dwt_reg_write_u16(dev, DWT_OTP_IF_ID, DWT_OTP_CTRL,
DWT_OTP_CTRL_LDELOAD);
k_sleep(K_MSEC(1));
dwt_set_sysclks_xti(dev, false);
ctx->sleep_mode |= DWT_AON_WCFG_ONW_LLDE;
dwt_set_sysclks_auto(dev);
if (!(dwt_reg_read_u8(dev, DWT_SYS_STATUS_ID, 0) &
DWT_SYS_STATUS_CPLOCK)) {
LOG_WRN("PLL has not locked");
return -EIO;
}
dwt_set_spi_fast(dev);
/* Setup antenna delay values */
dwt_reg_write_u16(dev, DWT_LDE_IF_ID, DWT_LDE_RXANTD_OFFSET,
DW1000_RX_ANT_DLY);
dwt_reg_write_u16(dev, DWT_TX_ANTD_ID, DWT_TX_ANTD_OFFSET,
DW1000_TX_ANT_DLY);
/* Clear AON_CFG1 register */
dwt_reg_write_u8(dev, DWT_AON_ID, DWT_AON_CFG1_OFFSET, 0);
/*
* Configure sleep mode:
* - On wake-up load configurations from the AON memory
* - preserve sleep mode configuration
* - On Wake-up load the LDE microcode
* - When available, on wake-up load the LDO tune value
*/
ctx->sleep_mode |= DWT_AON_WCFG_ONW_LDC |
DWT_AON_WCFG_PRES_SLEEP;
dwt_reg_write_u16(dev, DWT_AON_ID, DWT_AON_WCFG_OFFSET,
ctx->sleep_mode);
LOG_DBG("sleep mode 0x%04x", ctx->sleep_mode);
/* Enable sleep and wake using SPI CSn */
dwt_reg_write_u8(dev, DWT_AON_ID, DWT_AON_CFG0_OFFSET,
DWT_AON_CFG0_WAKE_SPI | DWT_AON_CFG0_SLEEP_EN);
return 0;
}
/*
* RF PHY configuration. Must be carried out as part of initialization and
* for every channel change. See also 2.5 Default Configuration on Power Up.
*/
static int dwt_configure_rf_phy(const struct device *dev)
{
struct dwt_context *ctx = dev->data;
struct dwt_phy_config *rf_cfg = &ctx->rf_cfg;
uint8_t chan = rf_cfg->channel;
uint8_t prf_idx = rf_cfg->prf;
uint32_t chan_ctrl = 0;
uint8_t rxctrlh;
uint8_t pll_tune;
uint8_t tune4h;
uint8_t pgdelay;
uint16_t lde_repc;
uint16_t agc_tune1;
uint16_t sfdto;
uint16_t tune1a;
uint16_t tune0b;
uint16_t tune1b;
uint32_t txctrl;
uint32_t pll_cfg;
uint32_t tune2;
uint32_t sys_cfg;
uint32_t tx_fctrl;
uint32_t power;
if ((chan < 1) || (chan > 7) || (chan == 6)) {
LOG_ERR("Channel not supported %u", chan);
return -ENOTSUP;
}
if (rf_cfg->rx_shr_code >= ARRAY_SIZE(dwt_lde_repc_defs)) {
LOG_ERR("Preamble code not supported %u",
rf_cfg->rx_shr_code);
return -ENOTSUP;
}
if (prf_idx >= DWT_NUMOF_PRFS) {
LOG_ERR("PRF not supported %u", prf_idx);
return -ENOTSUP;
}
if (rf_cfg->rx_pac_l >= DWT_NUMOF_PACS) {
LOG_ERR("RX PAC not supported %u", rf_cfg->rx_pac_l);
return -ENOTSUP;
}
if (rf_cfg->rx_ns_sfd > 1) {
LOG_ERR("Wrong NS SFD configuration");
return -ENOTSUP;
}
if (rf_cfg->tx_shr_nsync >= DWT_NUM_OF_PLEN) {
LOG_ERR("Wrong SHR configuration");
return -ENOTSUP;
}
lde_repc = dwt_lde_repc_defs[rf_cfg->rx_shr_code];
agc_tune1 = dwt_agc_tune1_defs[prf_idx];
sfdto = rf_cfg->rx_sfd_to;
rxctrlh = dwt_rxctrlh_defs[dwt_ch_to_cfg[chan]];
txctrl = dwt_txctrl_defs[dwt_ch_to_cfg[chan]];
pll_tune = dwt_plltune_defs[dwt_ch_to_cfg[chan]];
pll_cfg = dwt_pllcfg_defs[dwt_ch_to_cfg[chan]];
tune2 = dwt_tune2_defs[prf_idx][rf_cfg->rx_pac_l];
tune1a = dwt_tune1a_defs[prf_idx];
tune0b = dwt_tune0b_defs[rf_cfg->dr][rf_cfg->rx_ns_sfd];
pgdelay = dwt_pgdelay_defs[dwt_ch_to_cfg[chan]];
sys_cfg = dwt_reg_read_u32(dev, DWT_SYS_CFG_ID, 0);
tx_fctrl = dwt_reg_read_u32(dev, DWT_TX_FCTRL_ID, 0);
/* Don't allow 0 - SFD timeout will always be enabled */
if (sfdto == 0) {
sfdto = DWT_SFDTOC_DEF;
}
/* Set IEEE 802.15.4 compliant mode */
sys_cfg &= ~DWT_SYS_CFG_PHR_MODE_11;
if (rf_cfg->dr == DWT_BR_110K) {
/* Set Receiver Mode 110 kbps data rate */
sys_cfg |= DWT_SYS_CFG_RXM110K;
lde_repc = lde_repc >> 3;
tune1b = DWT_DRX_TUNE1b_110K;
tune4h = DWT_DRX_TUNE4H_PRE64;
} else {
sys_cfg &= ~DWT_SYS_CFG_RXM110K;
if (rf_cfg->tx_shr_nsync == DWT_PLEN_64) {
tune1b = DWT_DRX_TUNE1b_6M8_PRE64;
tune4h = DWT_DRX_TUNE4H_PRE64;
} else {
tune1b = DWT_DRX_TUNE1b_850K_6M8;
tune4h = DWT_DRX_TUNE4H_PRE128PLUS;
}
}
if (sys_cfg & DWT_SYS_CFG_DIS_STXP) {
if (rf_cfg->prf == DWT_PRF_64M) {
power = dwt_txpwr_stxp1_64[dwt_ch_to_cfg[chan]];
} else {
power = dwt_txpwr_stxp1_16[dwt_ch_to_cfg[chan]];
}
} else {
if (rf_cfg->prf == DWT_PRF_64M) {
power = dwt_txpwr_stxp0_64[dwt_ch_to_cfg[chan]];
} else {
power = dwt_txpwr_stxp0_16[dwt_ch_to_cfg[chan]];
}
}
dwt_reg_write_u32(dev, DWT_SYS_CFG_ID, 0, sys_cfg);
LOG_DBG("SYS_CFG: 0x%08x", sys_cfg);
dwt_reg_write_u16(dev, DWT_LDE_IF_ID, DWT_LDE_REPC_OFFSET, lde_repc);
LOG_DBG("LDE_REPC: 0x%04x", lde_repc);
dwt_reg_write_u8(dev, DWT_LDE_IF_ID, DWT_LDE_CFG1_OFFSET,
DWT_DEFAULT_LDE_CFG1);
if (rf_cfg->prf == DWT_PRF_64M) {
dwt_reg_write_u16(dev, DWT_LDE_IF_ID, DWT_LDE_CFG2_OFFSET,
DWT_DEFAULT_LDE_CFG2_PRF64);
LOG_DBG("LDE_CFG2: 0x%04x", DWT_DEFAULT_LDE_CFG2_PRF64);
} else {
dwt_reg_write_u16(dev, DWT_LDE_IF_ID, DWT_LDE_CFG2_OFFSET,
DWT_DEFAULT_LDE_CFG2_PRF16);
LOG_DBG("LDE_CFG2: 0x%04x", DWT_DEFAULT_LDE_CFG2_PRF16);
}
/* Configure PLL2/RF PLL block CFG/TUNE (for a given channel) */
dwt_reg_write_u32(dev, DWT_FS_CTRL_ID, DWT_FS_PLLCFG_OFFSET, pll_cfg);
LOG_DBG("PLLCFG: 0x%08x", pll_cfg);
dwt_reg_write_u8(dev, DWT_FS_CTRL_ID, DWT_FS_PLLTUNE_OFFSET, pll_tune);
LOG_DBG("PLLTUNE: 0x%02x", pll_tune);
/* Configure RF RX blocks (for specified channel/bandwidth) */
dwt_reg_write_u8(dev, DWT_RF_CONF_ID, DWT_RF_RXCTRLH_OFFSET, rxctrlh);
LOG_DBG("RXCTRLH: 0x%02x", rxctrlh);
/* Configure RF/TX blocks for specified channel and PRF */
dwt_reg_write_u32(dev, DWT_RF_CONF_ID, DWT_RF_TXCTRL_OFFSET, txctrl);
LOG_DBG("TXCTRL: 0x%08x", txctrl);
/* Digital receiver configuration, DRX_CONF */
dwt_reg_write_u16(dev, DWT_DRX_CONF_ID, DWT_DRX_TUNE0b_OFFSET, tune0b);
LOG_DBG("DRX_TUNE0b: 0x%04x", tune0b);
dwt_reg_write_u16(dev, DWT_DRX_CONF_ID, DWT_DRX_TUNE1a_OFFSET, tune1a);
LOG_DBG("DRX_TUNE1a: 0x%04x", tune1a);
dwt_reg_write_u16(dev, DWT_DRX_CONF_ID, DWT_DRX_TUNE1b_OFFSET, tune1b);
LOG_DBG("DRX_TUNE1b: 0x%04x", tune1b);
dwt_reg_write_u32(dev, DWT_DRX_CONF_ID, DWT_DRX_TUNE2_OFFSET, tune2);
LOG_DBG("DRX_TUNE2: 0x%08x", tune2);
dwt_reg_write_u8(dev, DWT_DRX_CONF_ID, DWT_DRX_TUNE4H_OFFSET, tune4h);
LOG_DBG("DRX_TUNE4H: 0x%02x", tune4h);
dwt_reg_write_u16(dev, DWT_DRX_CONF_ID, DWT_DRX_SFDTOC_OFFSET, sfdto);
LOG_DBG("DRX_SFDTOC: 0x%04x", sfdto);
/* Automatic Gain Control configuration and control, AGC_CTRL */
dwt_reg_write_u16(dev, DWT_AGC_CTRL_ID, DWT_AGC_TUNE1_OFFSET,
agc_tune1);
LOG_DBG("AGC_TUNE1: 0x%04x", agc_tune1);
dwt_reg_write_u32(dev, DWT_AGC_CTRL_ID, DWT_AGC_TUNE2_OFFSET,
DWT_AGC_TUNE2_VAL);
if (rf_cfg->rx_ns_sfd) {
/*
* SFD_LENGTH, length of the SFD sequence used when
* the data rate is 850 kbps or 6.8 Mbps,
* must be set to either 8 or 16.
*/
dwt_reg_write_u8(dev, DWT_USR_SFD_ID, 0x00,
dwt_ns_sfdlen[rf_cfg->dr]);
LOG_DBG("USR_SFDLEN: 0x%02x", dwt_ns_sfdlen[rf_cfg->dr]);
chan_ctrl |= DWT_CHAN_CTRL_DWSFD;
}
/* Set RX_CHAN and TX CHAN */
chan_ctrl |= (chan & DWT_CHAN_CTRL_TX_CHAN_MASK) |
((chan << DWT_CHAN_CTRL_RX_CHAN_SHIFT) &
DWT_CHAN_CTRL_RX_CHAN_MASK);
/* Set RXPRF */
chan_ctrl |= (BIT(rf_cfg->prf) << DWT_CHAN_CTRL_RXFPRF_SHIFT) &
DWT_CHAN_CTRL_RXFPRF_MASK;
/* Set TX_PCOD */
chan_ctrl |= (rf_cfg->tx_shr_code << DWT_CHAN_CTRL_TX_PCOD_SHIFT) &
DWT_CHAN_CTRL_TX_PCOD_MASK;
/* Set RX_PCOD */
chan_ctrl |= (rf_cfg->rx_shr_code << DWT_CHAN_CTRL_RX_PCOD_SHIFT) &
DWT_CHAN_CTRL_RX_PCOD_MASK;
/* Set Channel Control */
dwt_reg_write_u32(dev, DWT_CHAN_CTRL_ID, 0, chan_ctrl);
LOG_DBG("CHAN_CTRL 0x%08x", chan_ctrl);
/* Set up TX Preamble Size, PRF and Data Rate */
tx_fctrl = dwt_plen_cfg[rf_cfg->tx_shr_nsync] |
(BIT(rf_cfg->prf) << DWT_TX_FCTRL_TXPRF_SHFT) |
(rf_cfg->dr << DWT_TX_FCTRL_TXBR_SHFT);
dwt_reg_write_u32(dev, DWT_TX_FCTRL_ID, 0, tx_fctrl);
LOG_DBG("TX_FCTRL 0x%08x", tx_fctrl);
/* Set the Pulse Generator Delay */
dwt_reg_write_u8(dev, DWT_TX_CAL_ID, DWT_TC_PGDELAY_OFFSET, pgdelay);
LOG_DBG("PGDELAY 0x%02x", pgdelay);
/* Set Transmit Power Control */
dwt_reg_write_u32(dev, DWT_TX_POWER_ID, 0, power);
LOG_DBG("TX_POWER 0x%08x", power);
/*
* From 5.3.1.2 SFD Initialisation,
* SFD sequence initialisation for Auto ACK frame.
*/
dwt_reg_write_u8(dev, DWT_SYS_CTRL_ID, DWT_SYS_CTRL_OFFSET,
DWT_SYS_CTRL_TXSTRT | DWT_SYS_CTRL_TRXOFF);
/*
* Calculate PHY timing parameters
*
* From (9.4) Std 802.15.4-2011
* Tshr = Tpsym * (NSYNC + NSFD )
* Tphr = NPHR * Tdsym1m
* Tpsdu = Tdsym * NPSDU * NSYMPEROCTET / Rfec
*
* PRF: pulse repetition frequency
* PSR: preamble symbol repetitions
* SFD: start of frame delimiter
* SHR: synchronisation header (SYNC + SFD)
* PHR: PHY header
*/
uint16_t nsync = BIT(rf_cfg->tx_shr_nsync + 6);
if (rf_cfg->prf == DWT_PRF_64M) {
rf_cfg->t_shr = UWB_PHY_TPSYM_PRF64 *
(nsync + UWB_PHY_NUMOF_SYM_SHR_SFD);
} else {
rf_cfg->t_shr = UWB_PHY_TPSYM_PRF16 *
(nsync + UWB_PHY_NUMOF_SYM_SHR_SFD);
}
if (rf_cfg->dr == DWT_BR_6M8) {
rf_cfg->t_phr = UWB_PHY_NUMOF_SYM_PHR * UWB_PHY_TDSYM_PHR_6M8;
rf_cfg->t_dsym = UWB_PHY_TDSYM_DATA_6M8 / 0.44;
} else if (rf_cfg->dr == DWT_BR_850K) {
rf_cfg->t_phr = UWB_PHY_NUMOF_SYM_PHR * UWB_PHY_TDSYM_PHR_850K;
rf_cfg->t_dsym = UWB_PHY_TDSYM_DATA_850K / 0.44;
} else {
rf_cfg->t_phr = UWB_PHY_NUMOF_SYM_PHR * UWB_PHY_TDSYM_PHR_110K;
rf_cfg->t_dsym = UWB_PHY_TDSYM_DATA_110K / 0.44;
}
return 0;
}
static int dw1000_init(const struct device *dev)
{
struct dwt_context *ctx = dev->data;
const struct dwt_hi_cfg *hi_cfg = dev->config;
LOG_INF("Initialize DW1000 Transceiver");
k_sem_init(&ctx->phy_sem, 0, 1);
/* slow SPI config */
memcpy(&ctx->spi_cfg_slow, &hi_cfg->bus.config, sizeof(ctx->spi_cfg_slow));
ctx->spi_cfg_slow.frequency = DWT_SPI_SLOW_FREQ;
if (!spi_is_ready_dt(&hi_cfg->bus)) {
LOG_ERR("SPI device not ready");
return -ENODEV;
}
dwt_set_spi_slow(dev, DWT_SPI_SLOW_FREQ);
/* Initialize IRQ GPIO */
if (!gpio_is_ready_dt(&hi_cfg->irq_gpio)) {
LOG_ERR("IRQ GPIO device not ready");
return -ENODEV;
}
if (gpio_pin_configure_dt(&hi_cfg->irq_gpio, GPIO_INPUT)) {
LOG_ERR("Unable to configure GPIO pin %u", hi_cfg->irq_gpio.pin);
return -EINVAL;
}
gpio_init_callback(&(ctx->gpio_cb), dwt_gpio_callback,
BIT(hi_cfg->irq_gpio.pin));
if (gpio_add_callback(hi_cfg->irq_gpio.port, &(ctx->gpio_cb))) {
LOG_ERR("Failed to add IRQ callback");
return -EINVAL;
}
/* Initialize RESET GPIO */
if (!gpio_is_ready_dt(&hi_cfg->rst_gpio)) {
LOG_ERR("Reset GPIO device not ready");
return -ENODEV;
}
if (gpio_pin_configure_dt(&hi_cfg->rst_gpio, GPIO_INPUT)) {
LOG_ERR("Unable to configure GPIO pin %u", hi_cfg->rst_gpio.pin);
return -EINVAL;
}
LOG_INF("GPIO and SPI configured");
dwt_hw_reset(dev);
if (dwt_reg_read_u32(dev, DWT_DEV_ID_ID, 0) != DWT_DEVICE_ID) {
LOG_ERR("Failed to read device ID %p", dev);
return -ENODEV;
}
if (dwt_initialise_dev(dev)) {
LOG_ERR("Failed to initialize DW1000");
return -EIO;
}
if (dwt_configure_rf_phy(dev)) {
LOG_ERR("Failed to configure RF PHY");
return -EIO;
}
/* Allow Beacon, Data, Acknowledgement, MAC command */
dwt_set_frame_filter(dev, true, DWT_SYS_CFG_FFAB | DWT_SYS_CFG_FFAD |
DWT_SYS_CFG_FFAA | DWT_SYS_CFG_FFAM);
/*
* Enable system events:
* - transmit frame sent,
* - receiver FCS good,
* - receiver PHY header error,
* - receiver FCS error,
* - receiver Reed Solomon Frame Sync Loss,
* - receive Frame Wait Timeout,
* - preamble detection timeout,
* - receive SFD timeout
*/
dwt_reg_write_u32(dev, DWT_SYS_MASK_ID, 0,
DWT_SYS_MASK_MTXFRS |
DWT_SYS_MASK_MRXFCG |
DWT_SYS_MASK_MRXPHE |
DWT_SYS_MASK_MRXFCE |
DWT_SYS_MASK_MRXRFSL |
DWT_SYS_MASK_MRXRFTO |
DWT_SYS_MASK_MRXPTO |
DWT_SYS_MASK_MRXSFDTO);
/* Initialize IRQ event work queue */
ctx->dev = dev;
k_work_queue_start(&dwt_work_queue, dwt_work_queue_stack,
K_KERNEL_STACK_SIZEOF(dwt_work_queue_stack),
CONFIG_SYSTEM_WORKQUEUE_PRIORITY, NULL);
k_work_init(&ctx->irq_cb_work, dwt_irq_work_handler);
dwt_setup_int(dev, true);
LOG_INF("DW1000 device initialized and configured");
return 0;
}
static inline uint8_t *get_mac(const struct device *dev)
{
struct dwt_context *dw1000 = dev->data;
sys_rand_get(dw1000->mac_addr, sizeof(dw1000->mac_addr));
dw1000->mac_addr[0] = (dw1000->mac_addr[0] & ~0x01) | 0x02;
return dw1000->mac_addr;
}
static void dwt_iface_api_init(struct net_if *iface)
{
const struct device *dev = net_if_get_device(iface);
struct dwt_context *dw1000 = dev->data;
uint8_t *mac = get_mac(dev);
net_if_set_link_addr(iface, mac, 8, NET_LINK_IEEE802154);
dw1000->iface = iface;
ieee802154_init(iface);
LOG_INF("Iface initialized");
}
static const struct ieee802154_radio_api dwt_radio_api = {
.iface_api.init = dwt_iface_api_init,
.get_capabilities = dwt_get_capabilities,
.cca = dwt_cca,
.set_channel = dwt_set_channel,
.filter = dwt_filter,
.set_txpower = dwt_set_power,
.start = dwt_start,
.stop = dwt_stop,
.configure = dwt_configure,
.ed_scan = dwt_ed,
.tx = dwt_tx,
.attr_get = dwt_attr_get,
};
#define DWT_PSDU_LENGTH (127 - DWT_FCS_LENGTH)
#if defined(CONFIG_IEEE802154_RAW_MODE)
DEVICE_DT_INST_DEFINE(0, dw1000_init, NULL,
&dwt_0_context, &dw1000_0_config,
POST_KERNEL, CONFIG_IEEE802154_DW1000_INIT_PRIO,
&dwt_radio_api);
#else
NET_DEVICE_DT_INST_DEFINE(0,
dw1000_init,
NULL,
&dwt_0_context,
&dw1000_0_config,
CONFIG_IEEE802154_DW1000_INIT_PRIO,
&dwt_radio_api,
IEEE802154_L2,
NET_L2_GET_CTX_TYPE(IEEE802154_L2),
DWT_PSDU_LENGTH);
#endif
``` | /content/code_sandbox/drivers/ieee802154/ieee802154_dw1000.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 15,166 |
```objective-c
/* ieee802154_mcr20a_regs.h - Registers definition for NXP MCR20A */
/*
*
*
* This file is based on MCR20reg.h, it was modified to meet the
* coding style and restructured to make it easier to read.
* Additional identifiers was inserted (_MASK and _SHIFT endings),
* which are used in the macros for the bit field manipulation.
*
* This file are derived from material that is
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* o Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* o Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* o Neither the name of Freescale Semiconductor, Inc. nor the names of its
* contributors may be used to endorse or promote products derived from this
* software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef ZEPHYR_DRIVERS_IEEE802154_IEEE802154_MCR20A_REGS_H_
#define ZEPHYR_DRIVERS_IEEE802154_IEEE802154_MCR20A_REGS_H_
#define MCR20A_REG_READ (BIT(7))
#define MCR20A_BUF_READ (BIT(7) | BIT(6))
#define MCR20A_BUF_BYTE_READ (BIT(7) | BIT(6) | BIT(5))
#define MCR20A_REG_WRITE (0)
#define MCR20A_BUF_WRITE (BIT(6))
#define MCR20A_BUF_BYTE_WRITE (BIT(6) | BIT(5))
#define MCR20A_IRQSTS1 (0x0)
#define MCR20A_IRQSTS2 (0x1)
#define MCR20A_IRQSTS3 (0x2)
#define MCR20A_PHY_CTRL1 (0x3)
#define MCR20A_PHY_CTRL2 (0x4)
#define MCR20A_PHY_CTRL3 (0x5)
#define MCR20A_RX_FRM_LEN (0x6)
#define MCR20A_PHY_CTRL4 (0x7)
#define MCR20A_SRC_CTRL (0x8)
#define MCR20A_SRC_ADDRS_SUM_LSB (0x9)
#define MCR20A_SRC_ADDRS_SUM_MSB (0xa)
#define MCR20A_CCA1_ED_FNL (0xb)
#define MCR20A_EVENT_TIMER_LSB (0xc)
#define MCR20A_EVENT_TIMER_MSB (0xd)
#define MCR20A_EVENT_TIMER_USB (0xe)
#define MCR20A_TIMESTAMP_LSB (0xf)
#define MCR20A_TIMESTAMP_MSB (0x10)
#define MCR20A_TIMESTAMP_USB (0x11)
#define MCR20A_T3CMP_LSB (0x12)
#define MCR20A_T3CMP_MSB (0x13)
#define MCR20A_T3CMP_USB (0x14)
#define MCR20A_T2PRIMECMP_LSB (0x15)
#define MCR20A_T2PRIMECMP_MSB (0x16)
#define MCR20A_T1CMP_LSB (0x17)
#define MCR20A_T1CMP_MSB (0x18)
#define MCR20A_T1CMP_USB (0x19)
#define MCR20A_T2CMP_LSB (0x1a)
#define MCR20A_T2CMP_MSB (0x1b)
#define MCR20A_T2CMP_USB (0x1c)
#define MCR20A_T4CMP_LSB (0x1d)
#define MCR20A_T4CMP_MSB (0x1e)
#define MCR20A_T4CMP_USB (0x1f)
#define MCR20A_PLL_INT0 (0x20)
#define MCR20A_PLL_FRAC0_LSB (0x21)
#define MCR20A_PLL_FRAC0_MSB (0x22)
#define MCR20A_PA_PWR (0x23)
#define MCR20A_SEQ_STATE (0x24)
#define MCR20A_LQI_VALUE (0x25)
#define MCR20A_RSSI_CCA_CNT (0x26)
/* ---------------- (0x27) */
#define MCR20A_ASM_CTRL1 (0x28)
#define MCR20A_ASM_CTRL2 (0x29)
#define MCR20A_ASM_DATA_0 (0x2a)
#define MCR20A_ASM_DATA_1 (0x2b)
#define MCR20A_ASM_DATA_2 (0x2c)
#define MCR20A_ASM_DATA_3 (0x2d)
#define MCR20A_ASM_DATA_4 (0x2e)
#define MCR20A_ASM_DATA_5 (0x2f)
#define MCR20A_ASM_DATA_6 (0x30)
#define MCR20A_ASM_DATA_7 (0x31)
#define MCR20A_ASM_DATA_8 (0x32)
#define MCR20A_ASM_DATA_9 (0x33)
#define MCR20A_ASM_DATA_A (0x34)
#define MCR20A_ASM_DATA_B (0x35)
#define MCR20A_ASM_DATA_C (0x36)
#define MCR20A_ASM_DATA_D (0x37)
#define MCR20A_ASM_DATA_E (0x38)
#define MCR20A_ASM_DATA_F (0x39)
/* ---------------- (0x3a) */
#define MCR20A_OVERWRITE_VER (0x3b)
#define MCR20A_CLK_OUT_CTRL (0x3c)
#define MCR20A_PWR_MODES (0x3d)
#define MCR20A_IAR_INDEX (0x3e)
#define MCR20A_IAR_DATA (0x3f)
#define MCR20A_IRQSTS1_RX_FRM_PEND BIT(7)
#define MCR20A_IRQSTS1_PLL_UNLOCK_IRQ BIT(6)
#define MCR20A_IRQSTS1_FILTERFAIL_IRQ BIT(5)
#define MCR20A_IRQSTS1_RXWTRMRKIRQ BIT(4)
#define MCR20A_IRQSTS1_CCAIRQ BIT(3)
#define MCR20A_IRQSTS1_RXIRQ BIT(2)
#define MCR20A_IRQSTS1_TXIRQ BIT(1)
#define MCR20A_IRQSTS1_SEQIRQ BIT(0)
#define MCR20A_IRQSTS1_IRQ_MASK (0x7f)
#define MCR20A_IRQSTS2_CRCVALID BIT(7)
#define MCR20A_IRQSTS2_CCA BIT(6)
#define MCR20A_IRQSTS2_SRCADDR BIT(5)
#define MCR20A_IRQSTS2_PI BIT(4)
#define MCR20A_IRQSTS2_TMRSTATUS BIT(3)
#define MCR20A_IRQSTS2_ASM_IRQ BIT(2)
#define MCR20A_IRQSTS2_PB_ERR_IRQ BIT(1)
#define MCR20A_IRQSTS2_WAKE_IRQ BIT(0)
#define MCR20A_IRQSTS2_IRQ_MASK (0x7)
#define MCR20A_IRQSTS3_TMR4MSK BIT(7)
#define MCR20A_IRQSTS3_TMR3MSK BIT(6)
#define MCR20A_IRQSTS3_TMR2MSK BIT(5)
#define MCR20A_IRQSTS3_TMR1MSK BIT(4)
#define MCR20A_IRQSTS3_TMR_MASK (0xf0)
#define MCR20A_IRQSTS3_TMR4IRQ BIT(3)
#define MCR20A_IRQSTS3_TMR3IRQ BIT(2)
#define MCR20A_IRQSTS3_TMR2IRQ BIT(1)
#define MCR20A_IRQSTS3_TMR1IRQ BIT(0)
#define MCR20A_IRQSTS3_IRQ_MASK (0xf)
#define MCR20A_IRQSTS3_IRQ_SHIFT (0)
#define MCR20A_PHY_CTRL1_TMRTRIGEN BIT(7)
#define MCR20A_PHY_CTRL1_SLOTTED BIT(6)
#define MCR20A_PHY_CTRL1_CCABFRTX BIT(5)
#define MCR20A_PHY_CTRL1_RXACKRQD BIT(4)
#define MCR20A_PHY_CTRL1_AUTOACK BIT(3)
#define MCR20A_PHY_CTRL1_XCVSEQ_MASK (0x7)
#define MCR20A_PHY_CTRL1_XCVSEQ_SHIFT (0)
#define MCR20A_XCVSEQ_IDLE (0)
#define MCR20A_XCVSEQ_RECEIVE (1)
#define MCR20A_XCVSEQ_TX (2)
#define MCR20A_XCVSEQ_CCA (3)
#define MCR20A_XCVSEQ_TX_RX (4)
#define MCR20A_XCVSEQ_CONTINUOUS_CCA (5)
#define MCR20A_PHY_CTRL2_CRC_MSK BIT(7)
#define MCR20A_PHY_CTRL2_PLL_UNLOCK_MSK BIT(6)
#define MCR20A_PHY_CTRL2_FILTERFAIL_MSK BIT(5)
#define MCR20A_PHY_CTRL2_RX_WMRK_MSK BIT(4)
#define MCR20A_PHY_CTRL2_CCAMSK BIT(3)
#define MCR20A_PHY_CTRL2_RXMSK BIT(2)
#define MCR20A_PHY_CTRL2_TXMSK BIT(1)
#define MCR20A_PHY_CTRL2_SEQMSK BIT(0)
#define MCR20A_PHY_CTRL3_TMR4CMP_EN BIT(7)
#define MCR20A_PHY_CTRL3_TMR3CMP_EN BIT(6)
#define MCR20A_PHY_CTRL3_TMR2CMP_EN BIT(5)
#define MCR20A_PHY_CTRL3_TMR1CMP_EN BIT(4)
#define MCR20A_PHY_CTRL3_ASM_MSK BIT(2)
#define MCR20A_PHY_CTRL3_PB_ERR_MSK BIT(1)
#define MCR20A_PHY_CTRL3_WAKE_MSK BIT(0)
#define MCR20A_RX_FRM_LENGTH_MASK (0x7f)
#define MCR20A_PHY_CTRL4_TRCV_MSK BIT(7)
#define MCR20A_PHY_CTRL4_TC3TMOUT BIT(6)
#define MCR20A_PHY_CTRL4_PANCORDNTR0 BIT(5)
#define MCR20A_PHY_CTRL4_CCATYPE_MASK (0x18)
#define MCR20A_PHY_CTRL4_CCATYPE_SHIFT (3)
#define MCR20A_PHY_CTRL4_TMRLOAD BIT(2)
#define MCR20A_PHY_CTRL4_PROMISCUOUS BIT(1)
#define MCR20A_PHY_CTRL4_TC2PRIME_EN BIT(0)
#define MCR20A_SRC_CTRL_INDEX_MASK (0xf0)
#define MCR20A_SRC_CTRL_INDEX_SHIFT (4)
#define MCR20A_SRC_CTRL_ACK_FRM_PND BIT(3)
#define MCR20A_SRC_CTRL_SRCADDR_EN BIT(2)
#define MCR20A_SRC_CTRL_INDEX_EN BIT(1)
#define MCR20A_SRC_CTRL_INDEX_DISABLE BIT(0)
#define MCR20A_PLL_INT0_VAL_MASK (0x1f)
#define MCR20A_PLL_INT0_VAL_SHIFT (0)
#define MCR20A_PA_PWR_VAL_MASK (0x1f)
#define MCR20A_PA_PWR_VAL_SHIFT (0)
#define MCR20A_SEQ_STATE_MASK (0x1f)
#define MCR20A_ASM_CTRL1_CLEAR BIT(7)
#define MCR20A_ASM_CTRL1_START BIT(6)
#define MCR20A_ASM_CTRL1_SELFTST BIT(5)
#define MCR20A_ASM_CTRL1_CTR BIT(4)
#define MCR20A_ASM_CTRL1_CBC BIT(3)
#define MCR20A_ASM_CTRL1_AES BIT(2)
#define MCR20A_ASM_CTRL1_LOAD_MAC BIT(1)
#define MCR20A_ASM_CTRL2_DATA_REG_TYPE_SELECT_MASK (0x7)
#define MCR20A_ASM_CTRL2_DATA_REG_TYPE_SELECT_SHIFT (5)
#define MCR20A_ASM_CTRL2_TSTPAS BIT(1)
#define MCR20A_CLK_OUT_EXTEND BIT(7)
#define MCR20A_CLK_OUT_HIZ BIT(6)
#define MCR20A_CLK_OUT_SR BIT(5)
#define MCR20A_CLK_OUT_DS BIT(4)
#define MCR20A_CLK_OUT_EN BIT(3)
#define MCR20A_CLK_OUT_DIV_MASK (0x07)
#define MCR20A_CLK_OUT_DIV_SHIFT (0)
#define MCR20A_PWR_MODES_XTAL_READY BIT(5)
#define MCR20A_PWR_MODES_XTALEN BIT(4)
#define MCR20A_PWR_MODES_ASM_CLK_EN BIT(3)
#define MCR20A_PWR_MODES_AUTODOZE BIT(1)
#define MCR20A_PWR_MODES_PMC_MODE BIT(0)
#define MCR20A_PART_ID (0x00)
#define MCR20A_XTAL_TRIM (0x01)
#define MCR20A_PMC_LP_TRIM (0x02)
#define MCR20A_MACPANID0_LSB (0x03)
#define MCR20A_MACPANID0_MSB (0x04)
#define MCR20A_MACSHORTADDRS0_LSB (0x05)
#define MCR20A_MACSHORTADDRS0_MSB (0x06)
#define MCR20A_MACLONGADDRS0_0 (0x07)
#define MCR20A_MACLONGADDRS0_1 (0x08)
#define MCR20A_MACLONGADDRS0_2 (0x09)
#define MCR20A_MACLONGADDRS0_3 (0x0a)
#define MCR20A_MACLONGADDRS0_4 (0x0b)
#define MCR20A_MACLONGADDRS0_5 (0x0c)
#define MCR20A_MACLONGADDRS0_6 (0x0d)
#define MCR20A_MACLONGADDRS0_7 (0x0e)
#define MCR20A_RX_FRAME_FILTER (0x0f)
#define MCR20A_PLL_INT1 (0x10)
#define MCR20A_PLL_FRAC1_LSB (0x11)
#define MCR20A_PLL_FRAC1_MSB (0x12)
#define MCR20A_MACPANID1_LSB (0x13)
#define MCR20A_MACPANID1_MSB (0x14)
#define MCR20A_MACSHORTADDRS1_LSB (0x15)
#define MCR20A_MACSHORTADDRS1_MSB (0x16)
#define MCR20A_MACLONGADDRS1_0 (0x17)
#define MCR20A_MACLONGADDRS1_1 (0x18)
#define MCR20A_MACLONGADDRS1_2 (0x19)
#define MCR20A_MACLONGADDRS1_3 (0x1a)
#define MCR20A_MACLONGADDRS1_4 (0x1b)
#define MCR20A_MACLONGADDRS1_5 (0x1c)
#define MCR20A_MACLONGADDRS1_6 (0x1d)
#define MCR20A_MACLONGADDRS1_7 (0x1e)
#define MCR20A_DUAL_PAN_CTRL (0x1f)
#define MCR20A_DUAL_PAN_DWELL (0x20)
#define MCR20A_DUAL_PAN_STS (0x21)
#define MCR20A_CCA1_THRESH (0x22)
#define MCR20A_CCA1_ED_OFFSET_COMP (0x23)
#define MCR20A_LQI_OFFSET_COMP (0x24)
#define MCR20A_CCA_CTRL (0x25)
#define MCR20A_CCA2_CORR_PEAKS (0x26)
#define MCR20A_CCA2_THRESH (0x27)
#define MCR20A_TMR_PRESCALE (0x28)
/* ---------------- (0x29) */
#define MCR20A_GPIO_DATA (0x2a)
#define MCR20A_GPIO_DIR (0x2b)
#define MCR20A_GPIO_PUL_EN (0x2c)
#define MCR20A_GPIO_SEL (0x2d)
#define MCR20A_GPIO_DS (0x2e)
/* ---------------- (0x2f) */
#define MCR20A_ANT_PAD_CTRL (0x30)
#define MCR20A_MISC_PAD_CTRL (0x31)
#define MCR20A_BSM_CTRL (0x32)
/* ---------------- (0x33) */
#define MCR20A_RNG (0x34)
#define MCR20A_RX_BYTE_COUNT (0x35)
#define MCR20A_RX_WTR_MARK (0x36)
#define MCR20A_SOFT_RESET (0x37)
#define MCR20A_TXDELAY (0x38)
#define MCR20A_ACKDELAY (0x39)
#define MCR20A_SEQ_MGR_CTRL (0x3a)
#define MCR20A_SEQ_MGR_STS (0x3b)
#define MCR20A_SEQ_T_STS (0x3c)
#define MCR20A_ABORT_STS (0x3d)
#define MCR20A_CCCA_BUSY_CNT (0x3e)
#define MCR20A_SRC_ADDR_CHECKSUM1 (0x3f)
#define MCR20A_SRC_ADDR_CHECKSUM2 (0x40)
#define MCR20A_SRC_TBL_VALID1 (0x41)
#define MCR20A_SRC_TBL_VALID2 (0x42)
#define MCR20A_FILTERFAIL_CODE1 (0x43)
#define MCR20A_FILTERFAIL_CODE2 (0x44)
#define MCR20A_SLOT_PRELOAD (0x45)
/* ---------------- (0x46) */
#define MCR20A_CORR_VT (0x47)
#define MCR20A_SYNC_CTRL (0x48)
#define MCR20A_PN_LSB_0 (0x49)
#define MCR20A_PN_LSB_1 (0x4a)
#define MCR20A_PN_MSB_0 (0x4b)
#define MCR20A_PN_MSB_1 (0x4c)
#define MCR20A_CORR_NVAL (0x4d)
#define MCR20A_TX_MODE_CTRL (0x4e)
#define MCR20A_SNF_THR (0x4f)
#define MCR20A_FAD_THR (0x50)
#define MCR20A_ANT_AGC_CTRL (0x51)
#define MCR20A_AGC_THR1 (0x52)
#define MCR20A_AGC_THR2 (0x53)
#define MCR20A_AGC_HYS (0x54)
#define MCR20A_AFC (0x55)
#define MCR20A_LPPS_CTRL (0x56)
/* ---------------- (0x57) */
#define MCR20A_PHY_STS (0x58)
#define MCR20A_RX_MAX_CORR (0x59)
#define MCR20A_RX_MAX_PREAMBLE (0x5a)
#define MCR20A_RSSI (0x5b)
/* ---------------- (0x5c) */
/* ---------------- (0x5d) */
#define MCR20A_PLL_DIG_CTRL (0x5e)
#define MCR20A_VCO_CAL (0x5f)
#define MCR20A_VCO_BEST_DIFF (0x60)
#define MCR20A_VCO_BIAS (0x61)
#define MCR20A_KMOD_CTRL (0x62)
#define MCR20A_KMOD_CAL (0x63)
#define MCR20A_PA_CAL (0x64)
#define MCR20A_PA_PWRCAL (0x65)
#define MCR20A_ATT_RSSI1 (0x66)
#define MCR20A_ATT_RSSI2 (0x67)
#define MCR20A_RSSI_OFFSET (0x68)
#define MCR20A_RSSI_SLOPE (0x69)
#define MCR20A_RSSI_CAL1 (0x6a)
#define MCR20A_RSSI_CAL2 (0x6b)
/* ---------------- (0x6c) */
/* ---------------- (0x6d) */
#define MCR20A_XTAL_CTRL (0x6e)
#define MCR20A_XTAL_COMP_MIN (0x6f)
#define MCR20A_XTAL_COMP_MAX (0x70)
#define MCR20A_XTAL_GM (0x71)
/* ---------------- (0x72) */
/* ---------------- (0x73) */
#define MCR20A_LNA_TUNE (0x74)
#define MCR20A_LNA_AGCGAIN (0x75)
/* ---------------- (0x76) */
/* ---------------- (0x77) */
#define MCR20A_CHF_PMA_GAIN (0x78)
#define MCR20A_CHF_IBUF (0x79)
#define MCR20A_CHF_QBUF (0x7a)
#define MCR20A_CHF_IRIN (0x7b)
#define MCR20A_CHF_QRIN (0x7c)
#define MCR20A_CHF_IL (0x7d)
#define MCR20A_CHF_QL (0x7e)
#define MCR20A_CHF_CC1 (0x7f)
#define MCR20A_CHF_CCL (0x80)
#define MCR20A_CHF_CC2 (0x81)
#define MCR20A_CHF_IROUT (0x82)
#define MCR20A_CHF_QROUT (0x83)
/* ---------------- (0x84) */
/* ---------------- (0x85) */
#define MCR20A_RSSI_CTRL (0x86)
/* ---------------- (0x87) */
/* ---------------- (0x88) */
#define MCR20A_PA_BIAS (0x89)
#define MCR20A_PA_TUNING (0x8a)
/* ---------------- (0x8b) */
/* ---------------- (0x8c) */
#define MCR20A_PMC_HP_TRIM (0x8d)
#define MCR20A_VREGA_TRIM (0x8e)
/* ---------------- (0x8f) */
/* ---------------- (0x90) */
#define MCR20A_VCO_CTRL1 (0x91)
#define MCR20A_VCO_CTRL2 (0x92)
/* ---------------- (0x93) */
/* ---------------- (0x94) */
#define MCR20A_ANA_SPARE_OUT1 (0x95)
#define MCR20A_ANA_SPARE_OUT2 (0x96)
#define MCR20A_ANA_SPARE_IN (0x97)
#define MCR20A_MISCELLANEOUS (0x98)
/* ---------------- (0x99) */
#define MCR20A_SEQ_MGR_OVRD0 (0x9a)
#define MCR20A_SEQ_MGR_OVRD1 (0x9b)
#define MCR20A_SEQ_MGR_OVRD2 (0x9c)
#define MCR20A_SEQ_MGR_OVRD3 (0x9d)
#define MCR20A_SEQ_MGR_OVRD4 (0x9e)
#define MCR20A_SEQ_MGR_OVRD5 (0x9f)
#define MCR20A_SEQ_MGR_OVRD6 (0xa0)
#define MCR20A_SEQ_MGR_OVRD7 (0xa1)
/* ---------------- (0xa2) */
#define MCR20A_TESTMODE_CTRL (0xa3)
#define MCR20A_DTM_CTRL1 (0xa4)
#define MCR20A_DTM_CTRL2 (0xa5)
#define MCR20A_ATM_CTRL1 (0xa6)
#define MCR20A_ATM_CTRL2 (0xa7)
#define MCR20A_ATM_CTRL3 (0xa8)
/* ---------------- (0xa9) */
#define MCR20A_LIM_FE_TEST_CTRL (0xaa)
#define MCR20A_CHF_TEST_CTRL (0xab)
#define MCR20A_VCO_TEST_CTRL (0xac)
#define MCR20A_PLL_TEST_CTRL (0xad)
#define MCR20A_PA_TEST_CTRL (0xae)
#define MCR20A_PMC_TEST_CTRL (0xaf)
#define MCR20A_SCAN_DTM_PROTECT_1 (0xfe)
#define MCR20A_SCAN_DTM_PROTECT_0 (0xff)
#define MCR20A_RX_FRAME_FILTER_FRM_VER_MASK (0xc0)
#define MCR20A_RX_FRAME_FILTER_FRM_VER_SHIFT (6)
#define MCR20A_RX_FRAME_FILTER_ACTIVE_PROMISCUOUS BIT(5)
#define MCR20A_RX_FRAME_FILTER_NS_FT BIT(4)
#define MCR20A_RX_FRAME_FILTER_CMD_FT BIT(3)
#define MCR20A_RX_FRAME_FILTER_ACK_FT BIT(2)
#define MCR20A_RX_FRAME_FILTER_DATA_FT BIT(1)
#define MCR20A_RX_FRAME_FILTER_BEACON_FT BIT(0)
#define MCR20A_PLL_INT1_MASK (0x1f)
#define MCR20A_DUAL_PAN_CTRL_DUAL_PAN_SAM_LVL_MASK (0xf0)
#define MCR20A_DUAL_PAN_CTRL_DUAL_PAN_SAM_LVL_SHIFT (4)
#define MCR20A_DUAL_PAN_CTRL_CURRENT_NETWORK BIT(3)
#define MCR20A_DUAL_PAN_CTRL_PANCORDNTR1 BIT(2)
#define MCR20A_DUAL_PAN_CTRL_DUAL_PAN_AUTO BIT(1)
#define MCR20A_DUAL_PAN_CTRL_ACTIVE_NETWORK BIT(0)
#define MCR20A_DUAL_PAN_STS_RECD_ON_PAN1 BIT(7)
#define MCR20A_DUAL_PAN_STS_RECD_ON_PAN0 BIT(6)
#define MCR20A_DUAL_PAN_STS_DUAL_PAN_REMAIN_MASK (0x3f)
#define MCR20A_CCA_CTRL_AGC_FRZ_EN BIT(6)
#define MCR20A_CCA_CTRL_CONT_RSSI_EN BIT(5)
#define MCR20A_CCA_CTRL_QI_RSSI_NOT_CORR BIT(4)
#define MCR20A_CCA_CTRL_CCA3_AND_NOT_OR BIT(3)
#define MCR20A_CCA_CTRL_OWER_COMP_EN_LQI BIT(2)
#define MCR20A_CCA_CTRL_OWER_COMP_EN_ED BIT(1)
#define MCR20A_CCA_CTRL_OWER_COMP_EN_CCA1 BIT(0)
#define MCR20A_CCA2_CORR_PEAKS_CCA2_MIN_NUM_CORR_TH_MASK (0x70)
#define MCR20A_CCA2_CORR_PEAKS_CCA2_MIN_NUM_CORR_TH_SHIFT (4)
#define MCR20A_CCA2_CORR_PEAKS_CCA2_NUM_CORR_PEAKS_MASK (0x0f)
#define MCR20A_TMR_PRESCALE_VAL_MASK (0x7)
#define MCR20A_TMR_PRESCALE_VAL_SHIFT (0)
#define MCR20A_TIMEBASE_500000HZ (2)
#define MCR20A_TIMEBASE_250000HZ (3)
#define MCR20A_TIMEBASE_125000HZ (4)
#define MCR20A_TIMEBASE_62500HZ (5)
#define MCR20A_TIMEBASE_31250HZ (6)
#define MCR20A_TIMEBASE_15625HZ (7)
#define MCR20A_GPIO_DATA8 BIT(7)
#define MCR20A_GPIO_DATA7 BIT(6)
#define MCR20A_GPIO_DATA6 BIT(5)
#define MCR20A_GPIO_DATA5 BIT(4)
#define MCR20A_GPIO_DATA4 BIT(3)
#define MCR20A_GPIO_DATA3 BIT(2)
#define MCR20A_GPIO_DATA2 BIT(1)
#define MCR20A_GPIO_DATA1 BIT(0)
#define MCR20A_GPIO_DIR8 BIT(7)
#define MCR20A_GPIO_DIR7 BIT(6)
#define MCR20A_GPIO_DIR6 BIT(5)
#define MCR20A_GPIO_DIR5 BIT(4)
#define MCR20A_GPIO_DIR4 BIT(3)
#define MCR20A_GPIO_DIR3 BIT(2)
#define MCR20A_GPIO_DIR2 BIT(1)
#define MCR20A_GPIO_DIR1 BIT(0)
#define MCR20A_GPIO_PUL_EN8 BIT(7)
#define MCR20A_GPIO_PUL_EN7 BIT(6)
#define MCR20A_GPIO_PUL_EN6 BIT(5)
#define MCR20A_GPIO_PUL_EN5 BIT(4)
#define MCR20A_GPIO_PUL_EN4 BIT(3)
#define MCR20A_GPIO_PUL_EN3 BIT(2)
#define MCR20A_GPIO_PUL_EN2 BIT(1)
#define MCR20A_GPIO_PUL_EN1 BIT(0)
#define MCR20A_GPIO_PUL_SEL8 BIT(7)
#define MCR20A_GPIO_PUL_SEL7 BIT(6)
#define MCR20A_GPIO_PUL_SEL6 BIT(5)
#define MCR20A_GPIO_PUL_SEL5 BIT(4)
#define MCR20A_GPIO_PUL_SEL4 BIT(3)
#define MCR20A_GPIO_PUL_SEL3 BIT(2)
#define MCR20A_GPIO_PUL_SEL2 BIT(1)
#define MCR20A_GPIO_PUL_SEL1 BIT(0)
#define MCR20A_GPIO_DS8 BIT(7)
#define MCR20A_GPIO_DS7 BIT(6)
#define MCR20A_GPIO_DS6 BIT(5)
#define MCR20A_GPIO_DS5 BIT(4)
#define MCR20A_GPIO_DS4 BIT(3)
#define MCR20A_GPIO_DS3 BIT(2)
#define MCR20A_GPIO_DS2 BIT(1)
#define MCR20A_GPIO_DS1 BIT(0)
#define MCR20A_ANT_PAD_CTRL_ANTX_POL3 BIT(7)
#define MCR20A_ANT_PAD_CTRL_ANTX_POL2 BIT(6)
#define MCR20A_ANT_PAD_CTRL_ANTX_POL1 BIT(5)
#define MCR20A_ANT_PAD_CTRL_ANTX_POL0 BIT(4)
#define MCR20A_ANT_PAD_CTRL_ANTX_CTRLMODE BIT(3)
#define MCR20A_ANT_PAD_CTRL_ANTX_HZ BIT(2)
#define MCR20A_ANT_PAD_CTRL_ANTX_EN_MASK (0x03)
#define MCR20A_ANT_PAD_CTRL_ANTX_EN_SHIFT (0)
#define MCR20A_MISC_PAD_CTRL_MISO_HIZ_EN BIT(3)
#define MCR20A_MISC_PAD_CTRL_IRQ_B_OD BIT(2)
#define MCR20A_MISC_PAD_CTRL_NON_GPIO_DS BIT(1)
#define MCR20A_MISC_PAD_CTRL_ANTX_CURR BIT(0)
#define MCR20A_ANT_AGC_CTRL_SNF_EN BIT(7)
#define MCR20A_ANT_AGC_CTRL_AGC_EN BIT(6)
#define MCR20A_ANT_AGC_CTRL_AGC_LEVEL_MASK (0x30)
#define MCR20A_ANT_AGC_CTRL_AGC_LEVEL_SHIFT (4)
#define MCR20A_ANT_AGC_CTRL_ANTX BIT(1)
#define MCR20A_ANT_AGC_CTRL_AD_EN BIT(0)
#define MCR20A_LPPS_BUFMIX_EN BIT(4)
#define MCR20A_LPPS_LIM_EN BIT(3)
#define MCR20A_LPPS_RSSI_EN BIT(2)
#define MCR20A_LPPS_LNA_EN BIT(1)
#define MCR20A_LPPS_CTRL_LPPS_EN BIT(0)
/* Undocumented part copied from MCR20reg.h */
#define MCR20A_SOFT_RESET_SOG_RST BIT(7)
#define MCR20A_SOFT_RESET_REGS_RST BIT(4)
#define MCR20A_SOFT_RESET_PLL_RST BIT(3)
#define MCR20A_SOFT_RESET_TX_RST BIT(2)
#define MCR20A_SOFT_RESET_RX_RST BIT(1)
#define MCR20A_SOFT_RESET_SEQ_MGR_RST BIT(0)
#define MCR20A_SEQ_MGR_CTRL_SEQ_STATE_CTRL_MASK (0x3)
#define MCR20A_SEQ_MGR_CTRL_SEQ_STATE_CTRL_SHIFT (6)
#define MCR20A_SEQ_MGR_CTRL_NO_RX_RECYCLE BIT(5)
#define MCR20A_SEQ_MGR_CTRL_LATCH_PREAMBLE BIT(4)
#define MCR20A_SEQ_MGR_CTRL_EVENT_TMR_DO_NOT_LATCH BIT(3)
#define MCR20A_SEQ_MGR_CTRL_CLR_NEW_SEQ_INHIBIT BIT(2)
#define MCR20A_SEQ_MGR_CTRL_PSM_LOCK_DIS BIT(1)
#define MCR20A_SEQ_MGR_CTRL_PLL_ABORT_OVRD BIT(0)
#define MCR20A_SEQ_MGR_STS_TMR2_SEQ_TRIG_ARMED BIT(7)
#define MCR20A_SEQ_MGR_STS_RX_MODE BIT(6)
#define MCR20A_SEQ_MGR_STS_RX_TIMEOUT_PENDING BIT(5)
#define MCR20A_SEQ_MGR_STS_NEW_SEQ_INHIBIT BIT(4)
#define MCR20A_SEQ_MGR_STS_SEQ_IDLE BIT(3)
#define MCR20A_SEQ_MGR_STS_XCVSEQ_ACTUAL_MASK (0x7)
#define MCR20A_SEQ_MGR_STS_XCVSEQ_ACTUAL_SHIFT (0)
#define MCR20A_ABORT_STS_PLL_ABORTED BIT(2)
#define MCR20A_ABORT_STS_TC3_ABORTED BIT(1)
#define MCR20A_ABORT_STS_SW_ABORTED BIT(0)
#define MCR20A_PHY_STS_PLL_UNLOCK BIT(7)
#define MCR20A_PHY_STS_PLL_LOCK_ERR BIT(6)
#define MCR20A_PHY_STS_PLL_LOCK BIT(5)
#define MCR20A_PHY_STS_CRCVALID BIT(3)
#define MCR20A_PHY_STS_FILTERFAIL_FLAG_SEL BIT(2)
#define MCR20A_PHY_STS_SFD_DET BIT(1)
#define MCR20A_PHY_STS_PREAMBLE_DET BIT(0)
#define MCR20A_TESTMODE_CTRL_HOT_ANT BIT(4)
#define MCR20A_TESTMODE_CTRL_IDEAL_RSSI_EN BIT(3)
#define MCR20A_TESTMODE_CTRL_IDEAL_PFC_EN BIT(2)
#define MCR20A_TESTMODE_CTRL_CONTINUOUS_EN BIT(1)
#define MCR20A_TESTMODE_CTRL_FPGA_EN BIT(0)
#define MCR20A_DTM_CTRL1_ATM_LOCKED BIT(7)
#define MCR20A_DTM_CTRL1_DTM_EN BIT(6)
#define MCR20A_DTM_CTRL1_PAGE5 BIT(5)
#define MCR20A_DTM_CTRL1_PAGE4 BIT(4)
#define MCR20A_DTM_CTRL1_PAGE3 BIT(3)
#define MCR20A_DTM_CTRL1_PAGE2 BIT(2)
#define MCR20A_DTM_CTRL1_PAGE1 BIT(1)
#define MCR20A_DTM_CTRL1_PAGE0 BIT(0)
#define MCR20A_TX_MODE_CTRL_TX_INV BIT(4)
#define MCR20A_TX_MODE_CTRL_BT_EN BIT(3)
#define MCR20A_TX_MODE_CTRL_DTS2 BIT(2)
#define MCR20A_TX_MODE_CTRL_DTS1 BIT(1)
#define MCR20A_TX_MODE_CTRL_DTS0 BIT(0)
#define MCR20A_TX_MODE_CTRL_DTS_MASK (7)
#endif /* ZEPHYR_DRIVERS_IEEE802154_IEEE802154_MCR20A_REGS_H_ */
``` | /content/code_sandbox/drivers/ieee802154/ieee802154_mcr20a_regs.h | objective-c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 8,465 |
```c
/*
*
*/
#define DT_DRV_COMPAT ti_cc13xx_cc26xx_ieee802154
#define LOG_LEVEL CONFIG_IEEE802154_DRIVER_LOG_LEVEL
#include <zephyr/logging/log.h>
LOG_MODULE_REGISTER(ieee802154_cc13xx_cc26xx);
#include <zephyr/device.h>
#include <errno.h>
#include <zephyr/sys/byteorder.h>
#include <zephyr/net/ieee802154_radio.h>
#include <zephyr/net/ieee802154.h>
#include <zephyr/net/net_pkt.h>
#include <zephyr/random/random.h>
#include <string.h>
#include <zephyr/sys/sys_io.h>
#include <driverlib/rf_ieee_mailbox.h>
#include <driverlib/rfc.h>
#include <inc/hw_ccfg.h>
#include <inc/hw_fcfg1.h>
#include <rf_patches/rf_patch_cpe_multi_protocol.h>
#include <ti/drivers/rf/RF.h>
#include "ieee802154_cc13xx_cc26xx.h"
/* Overrides from SmartRF Studio 7 2.13.0 */
static uint32_t overrides[] = {
/* DC/DC regulator: In Tx, use DCDCCTL5[3:0]=0x3 (DITHER_EN=0 and IPEAK=3). */
0x00F388D3,
/* Rx: Set LNA bias current offset to +15 to saturate trim to max (default: 0) */
0x000F8883,
0xFFFFFFFF
};
/* 2.4 GHz power table */
static const RF_TxPowerTable_Entry txPowerTable_2_4[] = {
{-20, RF_TxPowerTable_DEFAULT_PA_ENTRY(6, 3, 0, 2)},
{-15, RF_TxPowerTable_DEFAULT_PA_ENTRY(10, 3, 0, 3)},
{-10, RF_TxPowerTable_DEFAULT_PA_ENTRY(15, 3, 0, 5)},
{-5, RF_TxPowerTable_DEFAULT_PA_ENTRY(22, 3, 0, 9)},
{0, RF_TxPowerTable_DEFAULT_PA_ENTRY(19, 1, 0, 20)},
{1, RF_TxPowerTable_DEFAULT_PA_ENTRY(22, 1, 0, 20)},
{2, RF_TxPowerTable_DEFAULT_PA_ENTRY(25, 1, 0, 25)},
{3, RF_TxPowerTable_DEFAULT_PA_ENTRY(29, 1, 0, 28)},
{4, RF_TxPowerTable_DEFAULT_PA_ENTRY(35, 1, 0, 39)},
{5, RF_TxPowerTable_DEFAULT_PA_ENTRY(23, 0, 0, 57)},
RF_TxPowerTable_TERMINATION_ENTRY,
};
static void ieee802154_cc13xx_cc26xx_rx_done(
struct ieee802154_cc13xx_cc26xx_data *drv_data);
static int ieee802154_cc13xx_cc26xx_stop(const struct device *dev);
/* TODO remove when rf driver bugfix is pulled in */
static void update_saved_cmdhandle(RF_CmdHandle ch, RF_CmdHandle *saved)
{
*saved = MAX(ch, *saved);
}
/* This is really the TX callback, because CSMA and TX are chained */
static void cmd_ieee_csma_callback(RF_Handle h, RF_CmdHandle ch, RF_EventMask e)
{
ARG_UNUSED(h);
const struct device *const dev = DEVICE_DT_INST_GET(0);
struct ieee802154_cc13xx_cc26xx_data *drv_data = dev->data;
update_saved_cmdhandle(ch, (RF_CmdHandle *) &drv_data->saved_cmdhandle);
LOG_DBG("e: 0x%" PRIx64, e);
if (e & RF_EventInternalError) {
LOG_ERR("Internal error");
}
}
static void cmd_ieee_rx_callback(RF_Handle h, RF_CmdHandle ch, RF_EventMask e)
{
ARG_UNUSED(h);
const struct device *const dev = DEVICE_DT_INST_GET(0);
struct ieee802154_cc13xx_cc26xx_data *drv_data = dev->data;
update_saved_cmdhandle(ch, (RF_CmdHandle *) &drv_data->saved_cmdhandle);
LOG_DBG("e: 0x%" PRIx64, e);
if (e & RF_EventRxBufFull) {
LOG_WRN("RX buffer is full");
}
if (e & RF_EventInternalError) {
LOG_ERR("Internal error");
}
if (e & RF_EventRxEntryDone) {
ieee802154_cc13xx_cc26xx_rx_done(drv_data);
}
}
static void client_error_callback(RF_Handle h, RF_CmdHandle ch, RF_EventMask e)
{
ARG_UNUSED(h);
ARG_UNUSED(ch);
LOG_DBG("e: 0x%" PRIx64, e);
}
static void client_event_callback(RF_Handle h, RF_ClientEvent event, void *arg)
{
ARG_UNUSED(h);
LOG_DBG("event: %d arg: %p", event, arg);
}
static enum ieee802154_hw_caps
ieee802154_cc13xx_cc26xx_get_capabilities(const struct device *dev)
{
return IEEE802154_HW_FCS | IEEE802154_HW_FILTER |
IEEE802154_HW_RX_TX_ACK | IEEE802154_HW_TX_RX_ACK | IEEE802154_HW_CSMA |
IEEE802154_HW_RETRANSMISSION;
}
static int ieee802154_cc13xx_cc26xx_cca(const struct device *dev)
{
struct ieee802154_cc13xx_cc26xx_data *drv_data = dev->data;
RF_Stat status;
status = RF_runImmediateCmd(drv_data->rf_handle,
(uint32_t *)&drv_data->cmd_ieee_cca_req);
if (status != RF_StatSuccess) {
LOG_ERR("Failed to request CCA (0x%x)", status);
return -EIO;
}
switch (drv_data->cmd_ieee_cca_req.ccaInfo.ccaState) {
case 0:
return 0;
case 1:
return -EBUSY;
default:
return -EIO;
}
}
static inline int ieee802154_cc13xx_cc26xx_channel_to_frequency(
uint16_t channel, uint16_t *frequency, uint16_t *fractFreq)
{
__ASSERT_NO_MSG(frequency != NULL);
__ASSERT_NO_MSG(fractFreq != NULL);
/* See IEEE 802.15.4-2020, section 10.1.3.3. */
if (channel >= 11 && channel <= 26) {
*frequency = 2405 + 5 * (channel - 11);
*fractFreq = 0;
return 0;
} else {
/* TODO: Support sub-GHz for CC13xx rather than having separate drivers */
*frequency = 0;
*fractFreq = 0;
return channel < 11 ? -ENOTSUP : -EINVAL;
}
}
static int ieee802154_cc13xx_cc26xx_set_channel(const struct device *dev,
uint16_t channel)
{
int ret;
RF_CmdHandle cmd_handle;
RF_EventMask reason;
uint16_t freq, fract;
struct ieee802154_cc13xx_cc26xx_data *drv_data = dev->data;
ret = ieee802154_cc13xx_cc26xx_channel_to_frequency(channel, &freq, &fract);
if (ret < 0) {
return ret;
}
/* Abort FG and BG processes */
if (ieee802154_cc13xx_cc26xx_stop(dev) < 0) {
ret = -EIO;
goto out;
}
/* Block TX while changing channel */
k_mutex_lock(&drv_data->tx_mutex, K_FOREVER);
/* Set the frequency */
drv_data->cmd_fs.status = IDLE;
drv_data->cmd_fs.frequency = freq;
drv_data->cmd_fs.fractFreq = fract;
reason = RF_runCmd(drv_data->rf_handle, (RF_Op *)&drv_data->cmd_fs,
RF_PriorityNormal, NULL, 0);
if (reason != RF_EventLastCmdDone) {
LOG_ERR("Failed to set frequency: 0x%" PRIx64, reason);
ret = -EIO;
goto out;
}
/* Run BG receive process on requested channel */
drv_data->cmd_ieee_rx.status = IDLE;
drv_data->cmd_ieee_rx.channel = channel;
cmd_handle = RF_postCmd(drv_data->rf_handle,
(RF_Op *)&drv_data->cmd_ieee_rx, RF_PriorityNormal,
cmd_ieee_rx_callback, RF_EventRxEntryDone);
if (cmd_handle < 0) {
LOG_ERR("Failed to post RX command (%d)", cmd_handle);
ret = -EIO;
goto out;
}
ret = 0;
out:
k_mutex_unlock(&drv_data->tx_mutex);
return ret;
}
/* TODO remove when rf driver bugfix is pulled in */
static int ieee802154_cc13xx_cc26xx_reset_channel(
const struct device *dev)
{
uint8_t channel;
struct ieee802154_cc13xx_cc26xx_data *drv_data = dev->data;
/* extract the channel from cmd_ieee_rx */
channel = drv_data->cmd_ieee_rx.channel;
__ASSERT_NO_MSG(11 <= channel && channel <= 26);
LOG_DBG("re-setting channel to %u", channel);
return ieee802154_cc13xx_cc26xx_set_channel(dev, channel);
}
static int
ieee802154_cc13xx_cc26xx_filter(const struct device *dev, bool set,
enum ieee802154_filter_type type,
const struct ieee802154_filter *filter)
{
struct ieee802154_cc13xx_cc26xx_data *drv_data = dev->data;
if (!set) {
return -ENOTSUP;
}
if (type == IEEE802154_FILTER_TYPE_IEEE_ADDR) {
memcpy((uint8_t *)&drv_data->cmd_ieee_rx.localExtAddr,
filter->ieee_addr,
sizeof(drv_data->cmd_ieee_rx.localExtAddr));
} else if (type == IEEE802154_FILTER_TYPE_SHORT_ADDR) {
drv_data->cmd_ieee_rx.localShortAddr = filter->short_addr;
} else if (type == IEEE802154_FILTER_TYPE_PAN_ID) {
drv_data->cmd_ieee_rx.localPanID = filter->pan_id;
} else {
return -ENOTSUP;
}
return 0;
}
static int ieee802154_cc13xx_cc26xx_set_txpower(const struct device *dev,
int16_t dbm)
{
RF_Stat status;
const RF_TxPowerTable_Entry *table;
struct ieee802154_cc13xx_cc26xx_data *drv_data = dev->data;
/* TODO Support sub-GHz for CC13xx */
table = txPowerTable_2_4;
RF_TxPowerTable_Value power_table_value = RF_TxPowerTable_findValue(
(RF_TxPowerTable_Entry *)table, dbm);
if (power_table_value.rawValue == RF_TxPowerTable_INVALID_VALUE) {
LOG_ERR("RF_TxPowerTable_findValue() failed");
return -EINVAL;
}
status = RF_setTxPower(drv_data->rf_handle, power_table_value);
if (status != RF_StatSuccess) {
LOG_ERR("RF_setTxPower() failed: %d", status);
return -EIO;
}
return 0;
}
/* See IEEE 802.15.4 section 6.2.5.1 and TRM section 25.5.4.3 */
static int ieee802154_cc13xx_cc26xx_tx(const struct device *dev,
enum ieee802154_tx_mode mode,
struct net_pkt *pkt,
struct net_buf *frag)
{
int r;
RF_EventMask reason;
RF_ScheduleCmdParams sched_params = {
.allowDelay = true,
};
struct ieee802154_cc13xx_cc26xx_data *drv_data = dev->data;
bool ack = ieee802154_is_ar_flag_set(frag);
int retry = CONFIG_IEEE802154_CC13XX_CC26XX_RADIO_TX_RETRIES;
if (mode != IEEE802154_TX_MODE_CSMA_CA) {
NET_ERR("TX mode %d not supported", mode);
return -ENOTSUP;
}
k_mutex_lock(&drv_data->tx_mutex, K_FOREVER);
/* Workaround for Issue #29418 where the driver stalls after
* wrapping around RF command handle 4096. This change
* effectively empties the RF command queue every ~4 minutes
* but otherwise causes the system to incur little overhead.
* A subsequent SimpleLink SDK release should resolve the issue.
*/
if (drv_data->saved_cmdhandle >= BIT(12) - 5) {
r = ieee802154_cc13xx_cc26xx_reset_channel(dev);
if (r < 0) {
goto out;
}
drv_data->saved_cmdhandle = -1;
}
do {
drv_data->cmd_ieee_csma.status = IDLE;
drv_data->cmd_ieee_csma.randomState = sys_rand32_get();
drv_data->cmd_ieee_tx.status = IDLE;
drv_data->cmd_ieee_tx.payloadLen = frag->len;
drv_data->cmd_ieee_tx.pPayload = frag->data;
drv_data->cmd_ieee_tx.condition.rule =
ack ? COND_STOP_ON_FALSE : COND_NEVER;
if (ack) {
drv_data->cmd_ieee_rx_ack.status = IDLE;
drv_data->cmd_ieee_rx_ack.seqNo = frag->data[2];
}
reason = RF_runScheduleCmd(drv_data->rf_handle,
(RF_Op *)&drv_data->cmd_ieee_csma, &sched_params,
cmd_ieee_csma_callback,
RF_EventLastFGCmdDone | RF_EventLastCmdDone);
if ((reason & (RF_EventLastFGCmdDone | RF_EventLastCmdDone))
== 0) {
LOG_DBG("Failed to run command (0x%" PRIx64 ")",
reason);
continue;
}
if (drv_data->cmd_ieee_csma.status != IEEE_DONE_OK) {
/* TODO: According to IEEE 802.15.4 CSMA/CA failure
* fails TX immediately and should not trigger
* attempt (which is reserved for ACK timeouts).
*/
LOG_DBG("Channel access failure (0x%x)",
drv_data->cmd_ieee_csma.status);
continue;
}
if (drv_data->cmd_ieee_tx.status != IEEE_DONE_OK) {
/* TODO: According to IEEE 802.15.4 transmission failure
* fails TX immediately and should not trigger
* attempt (which is reserved for ACK timeouts).
*/
LOG_DBG("Transmit failed (0x%x)",
drv_data->cmd_ieee_tx.status);
continue;
}
if (!ack || drv_data->cmd_ieee_rx_ack.status == IEEE_DONE_ACK ||
drv_data->cmd_ieee_rx_ack.status == IEEE_DONE_ACKPEND) {
r = 0;
goto out;
}
LOG_DBG("No acknowledgment (0x%x)",
drv_data->cmd_ieee_rx_ack.status);
} while (retry-- > 0);
LOG_DBG("Failed to TX");
r = -EIO;
out:
k_mutex_unlock(&drv_data->tx_mutex);
return r;
}
static void ieee802154_cc13xx_cc26xx_rx_done(
struct ieee802154_cc13xx_cc26xx_data *drv_data)
{
struct net_pkt *pkt;
uint8_t len, seq, corr, lqi;
int8_t rssi;
uint8_t *sdu;
for (int i = 0; i < CC13XX_CC26XX_NUM_RX_BUF; i++) {
if (drv_data->rx_entry[i].status == DATA_ENTRY_FINISHED) {
/* rx_data contains length, psdu, fcs, rssi, corr */
len = drv_data->rx_data[i][0];
sdu = drv_data->rx_data[i] + 1;
seq = drv_data->rx_data[i][3];
corr = drv_data->rx_data[i][len--] & 0x3F;
rssi = drv_data->rx_data[i][len--];
/* remove fcs as it is not expected by L2
* But keep it for RAW mode
*/
if (IS_ENABLED(CONFIG_NET_L2_IEEE802154)) {
len -= 2;
}
/* scale 6-bit corr to 8-bit lqi */
lqi = corr << 2;
LOG_DBG("Received: len = %u, seq = %u, rssi = %d, lqi = %u",
len, seq, rssi, lqi);
pkt = net_pkt_rx_alloc_with_buffer(
drv_data->iface, len, AF_UNSPEC, 0, K_NO_WAIT);
if (!pkt) {
LOG_WRN("Cannot allocate packet");
continue;
}
if (net_pkt_write(pkt, sdu, len)) {
LOG_WRN("Cannot write packet");
net_pkt_unref(pkt);
continue;
}
drv_data->rx_entry[i].status = DATA_ENTRY_PENDING;
net_pkt_set_ieee802154_lqi(pkt, lqi);
net_pkt_set_ieee802154_rssi_dbm(pkt,
rssi == CC13XX_CC26XX_INVALID_RSSI
? IEEE802154_MAC_RSSI_DBM_UNDEFINED
: rssi);
if (net_recv_data(drv_data->iface, pkt)) {
LOG_WRN("Packet dropped");
net_pkt_unref(pkt);
}
} else if (drv_data->rx_entry[i].status ==
DATA_ENTRY_UNFINISHED) {
LOG_WRN("Frame not finished");
drv_data->rx_entry[i].status = DATA_ENTRY_PENDING;
}
}
}
static int ieee802154_cc13xx_cc26xx_start(const struct device *dev)
{
ARG_UNUSED(dev);
return 0;
}
static int ieee802154_cc13xx_cc26xx_stop(const struct device *dev)
{
struct ieee802154_cc13xx_cc26xx_data *drv_data = dev->data;
RF_Stat status;
status = RF_flushCmd(drv_data->rf_handle, RF_CMDHANDLE_FLUSH_ALL, 0);
if (!(status == RF_StatCmdDoneSuccess
|| status == RF_StatSuccess
|| status == RF_StatRadioInactiveError
|| status == RF_StatInvalidParamsError)) {
LOG_DBG("Failed to abort radio operations (%d)", status);
return -EIO;
}
return 0;
}
/**
* Stops the sub-GHz interface and yields the radio (tells RF module to power
* down).
*/
static int ieee802154_cc13xx_cc26xx_stop_if(const struct device *dev)
{
struct ieee802154_cc13xx_cc26xx_data *drv_data = dev->data;
int ret;
ret = ieee802154_cc13xx_cc26xx_stop(dev);
if (ret < 0) {
return ret;
}
/* power down radio */
RF_yield(drv_data->rf_handle);
return 0;
}
static int
ieee802154_cc13xx_cc26xx_configure(const struct device *dev,
enum ieee802154_config_type type,
const struct ieee802154_config *config)
{
return -ENOTSUP;
}
/* driver-allocated attribute memory - constant across all driver instances */
IEEE802154_DEFINE_PHY_SUPPORTED_CHANNELS(drv_attr, 11, 26);
static int ieee802154_cc13xx_cc26xx_attr_get(const struct device *dev, enum ieee802154_attr attr,
struct ieee802154_attr_value *value)
{
ARG_UNUSED(dev);
return ieee802154_attr_get_channel_page_and_range(
attr, IEEE802154_ATTR_PHY_CHANNEL_PAGE_ZERO_OQPSK_2450_BPSK_868_915,
&drv_attr.phy_supported_channels, value);
}
static void ieee802154_cc13xx_cc26xx_data_init(const struct device *dev)
{
struct ieee802154_cc13xx_cc26xx_data *drv_data = dev->data;
uint8_t *mac;
if (sys_read32(CCFG_BASE + CCFG_O_IEEE_MAC_0) != 0xFFFFFFFF &&
sys_read32(CCFG_BASE + CCFG_O_IEEE_MAC_1) != 0xFFFFFFFF) {
mac = (uint8_t *)(CCFG_BASE + CCFG_O_IEEE_MAC_0);
} else {
mac = (uint8_t *)(FCFG1_BASE + FCFG1_O_MAC_15_4_0);
}
sys_memcpy_swap(&drv_data->mac, mac, sizeof(drv_data->mac));
/* Setup circular RX queue (TRM 25.3.2.7) */
memset(&drv_data->rx_entry[0], 0, sizeof(drv_data->rx_entry[0]));
memset(&drv_data->rx_entry[1], 0, sizeof(drv_data->rx_entry[1]));
drv_data->rx_entry[0].pNextEntry = (uint8_t *)&drv_data->rx_entry[1];
drv_data->rx_entry[0].config.type = DATA_ENTRY_TYPE_PTR;
drv_data->rx_entry[0].config.lenSz = 1;
drv_data->rx_entry[0].length = sizeof(drv_data->rx_data[0]);
drv_data->rx_entry[0].pData = drv_data->rx_data[0];
drv_data->rx_entry[1].pNextEntry = (uint8_t *)&drv_data->rx_entry[0];
drv_data->rx_entry[1].config.type = DATA_ENTRY_TYPE_PTR;
drv_data->rx_entry[1].config.lenSz = 1;
drv_data->rx_entry[1].length = sizeof(drv_data->rx_data[1]);
drv_data->rx_entry[1].pData = drv_data->rx_data[1];
drv_data->rx_queue.pCurrEntry = (uint8_t *)&drv_data->rx_entry[0];
drv_data->rx_queue.pLastEntry = NULL;
k_mutex_init(&drv_data->tx_mutex);
}
static void ieee802154_cc13xx_cc26xx_iface_init(struct net_if *iface)
{
const struct device *dev = net_if_get_device(iface);
struct ieee802154_cc13xx_cc26xx_data *drv_data = dev->data;
net_if_set_link_addr(iface, drv_data->mac, sizeof(drv_data->mac),
NET_LINK_IEEE802154);
drv_data->iface = iface;
ieee802154_init(iface);
}
static const struct ieee802154_radio_api ieee802154_cc13xx_cc26xx_radio_api = {
.iface_api.init = ieee802154_cc13xx_cc26xx_iface_init,
.get_capabilities = ieee802154_cc13xx_cc26xx_get_capabilities,
.cca = ieee802154_cc13xx_cc26xx_cca,
.set_channel = ieee802154_cc13xx_cc26xx_set_channel,
.filter = ieee802154_cc13xx_cc26xx_filter,
.set_txpower = ieee802154_cc13xx_cc26xx_set_txpower,
.tx = ieee802154_cc13xx_cc26xx_tx,
.start = ieee802154_cc13xx_cc26xx_start,
.stop = ieee802154_cc13xx_cc26xx_stop_if,
.configure = ieee802154_cc13xx_cc26xx_configure,
.attr_get = ieee802154_cc13xx_cc26xx_attr_get,
};
/** RF patches to use (note: RF core keeps a pointer to this, so no stack). */
static RF_Mode rf_mode = {
.rfMode = RF_MODE_MULTIPLE,
.cpePatchFxn = &rf_patch_cpe_multi_protocol,
};
static int ieee802154_cc13xx_cc26xx_init(const struct device *dev)
{
RF_Params rf_params;
RF_EventMask reason;
struct ieee802154_cc13xx_cc26xx_data *drv_data = dev->data;
/* Initialize driver data */
ieee802154_cc13xx_cc26xx_data_init(dev);
/* Setup radio */
RF_Params_init(&rf_params);
rf_params.pErrCb = client_error_callback;
rf_params.pClientEventCb = client_event_callback;
drv_data->rf_handle = RF_open(&drv_data->rf_object,
&rf_mode, (RF_RadioSetup *)&drv_data->cmd_radio_setup,
&rf_params);
if (drv_data->rf_handle == NULL) {
LOG_ERR("RF_open() failed");
return -EIO;
}
/*
* Run CMD_FS with frequency 0 to ensure RF_currClient is not NULL.
* RF_currClient is a static variable in the TI RF Driver library.
* If this is not done, then even CMD_ABORT fails.
*/
drv_data->cmd_fs.status = IDLE;
drv_data->cmd_fs.pNextOp = NULL;
drv_data->cmd_fs.condition.rule = COND_NEVER;
drv_data->cmd_fs.synthConf.bTxMode = false;
drv_data->cmd_fs.frequency = 0;
drv_data->cmd_fs.fractFreq = 0;
reason = RF_runCmd(drv_data->rf_handle, (RF_Op *)&drv_data->cmd_fs,
RF_PriorityNormal, NULL, 0);
if (reason != RF_EventLastCmdDone) {
LOG_ERR("Failed to set frequency: 0x%" PRIx64, reason);
return -EIO;
}
return 0;
}
static struct ieee802154_cc13xx_cc26xx_data ieee802154_cc13xx_cc26xx_data = {
.cmd_fs = {
.commandNo = CMD_FS,
},
.cmd_ieee_cca_req = {
.commandNo = CMD_IEEE_CCA_REQ,
},
.cmd_ieee_rx = {
.commandNo = CMD_IEEE_RX,
.status = IDLE,
.pNextOp = NULL,
.startTrigger.triggerType = TRIG_NOW,
.condition.rule = COND_NEVER,
.channel = 0,
.rxConfig = {
.bAutoFlushCrc = 1,
.bAutoFlushIgn = 1,
.bIncludePhyHdr = 0,
.bIncludeCrc = 1,
.bAppendRssi = 1,
.bAppendCorrCrc = 1,
.bAppendSrcInd = 0,
.bAppendTimestamp = 0
},
.pRxQ = &ieee802154_cc13xx_cc26xx_data.rx_queue,
.pOutput = NULL,
.frameFiltOpt = {
.frameFiltEn = 1,
.frameFiltStop = 0,
.autoAckEn = 1,
.slottedAckEn = 0,
.autoPendEn = 0,
.defaultPend = 0,
.bPendDataReqOnly = 0,
.bPanCoord = 0,
.maxFrameVersion = 3,
.fcfReservedMask = 0,
.modifyFtFilter = 0,
.bStrictLenFilter = 1
},
.frameTypes = {
.bAcceptFt0Beacon = 0,
.bAcceptFt1Data = 1,
.bAcceptFt2Ack = 0,
.bAcceptFt3MacCmd = 1,
.bAcceptFt4Reserved = 0,
.bAcceptFt5Reserved = 0,
.bAcceptFt6Reserved = 0,
.bAcceptFt7Reserved = 0
},
.ccaOpt = {
#if IEEE802154_PHY_CCA_MODE == 1
.ccaEnEnergy = 1,
.ccaEnCorr = 0,
#elif IEEE802154_PHY_CCA_MODE == 2
.ccaEnEnergy = 0,
.ccaEnCorr = 1,
#elif IEEE802154_PHY_CCA_MODE == 3
.ccaEnEnergy = 1,
.ccaEnCorr = 1,
#else
#error "Invalid CCA mode"
#endif
.ccaEnSync = 1,
.ccaSyncOp = 0,
.ccaCorrOp = 0,
.ccaCorrThr = 3,
},
/* See IEEE 802.15.4-2006 6.9.9*/
.ccaRssiThr = CC13XX_CC26XX_RECEIVER_SENSITIVITY + 10,
.numExtEntries = 0x00,
.numShortEntries = 0x00,
.pExtEntryList = NULL,
.pShortEntryList = NULL,
.localExtAddr = 0x0000000000000000,
.localShortAddr = 0x0000,
.localPanID = 0x0000,
.endTrigger.triggerType = TRIG_NEVER
},
.cmd_ieee_csma = {
.commandNo = CMD_IEEE_CSMA,
.status = IDLE,
.pNextOp = (rfc_radioOp_t *)&ieee802154_cc13xx_cc26xx_data.cmd_ieee_tx,
.startTrigger.triggerType = TRIG_NOW,
.condition.rule = COND_STOP_ON_FALSE,
.randomState = 0,
.macMaxBE =
CONFIG_IEEE802154_CC13XX_CC26XX_RADIO_CSMA_CA_MAX_BE,
.macMaxCSMABackoffs =
CONFIG_IEEE802154_CC13XX_CC26XX_RADIO_CSMA_CA_MAX_BO,
.csmaConfig = {
/* Initial value of CW for unslotted CSMA */
.initCW = 1,
/* Unslotted CSMA for non-beacon enabled PAN */
.bSlotted = 0,
/* RX stays on during CSMA backoffs */
.rxOffMode = 0,
},
.NB = 0,
.BE = CONFIG_IEEE802154_CC13XX_CC26XX_RADIO_CSMA_CA_MIN_BE,
.remainingPeriods = 0,
.endTrigger.triggerType = TRIG_NEVER,
},
.cmd_ieee_tx = {
.commandNo = CMD_IEEE_TX,
.status = IDLE,
.pNextOp = (rfc_radioOp_t *)&ieee802154_cc13xx_cc26xx_data.cmd_ieee_rx_ack,
.startTrigger.triggerType = TRIG_NOW,
.condition.rule = COND_NEVER,
.txOpt = {
/* Automatically insert PHY header */
.bIncludePhyHdr = 0x0,
/* Automatically append CRC */
.bIncludeCrc = 0x0,
/* Disable long frame testing */
.payloadLenMsb = 0x0,
},
.payloadLen = 0x0,
.pPayload = NULL,
},
.cmd_ieee_rx_ack = {
.commandNo = CMD_IEEE_RX_ACK,
.status = IDLE,
.pNextOp = NULL,
.startTrigger.triggerType = TRIG_NOW,
.condition.rule = COND_NEVER,
.seqNo = 0,
.endTrigger = {
.triggerType = TRIG_REL_START,
.pastTrig = 1,
},
.endTime = IEEE802154_MAC_ACK_WAIT_DURATION *
CC13XX_CC26XX_RAT_CYCLES_PER_SECOND /
IEEE802154_2450MHZ_OQPSK_SYMBOLS_PER_SECOND,
},
.cmd_radio_setup = {
.commandNo = CMD_RADIO_SETUP,
.status = IDLE,
.pNextOp = NULL,
.startTrigger.triggerType = TRIG_NOW,
.condition.rule = COND_NEVER,
.mode = 0x01, /* IEEE 802.15.4 */
.loDivider = 0x00,
.config = {
.frontEndMode = 0x0,
.biasMode = 0x0,
.analogCfgMode = 0x0,
.bNoFsPowerUp = 0x0,
},
.txPower = 0x2853, /* 0 dBm */
.pRegOverride = overrides
},
};
#if defined(CONFIG_NET_L2_IEEE802154)
NET_DEVICE_DT_INST_DEFINE(0, ieee802154_cc13xx_cc26xx_init, NULL,
&ieee802154_cc13xx_cc26xx_data, NULL,
CONFIG_IEEE802154_CC13XX_CC26XX_INIT_PRIO,
&ieee802154_cc13xx_cc26xx_radio_api, IEEE802154_L2,
NET_L2_GET_CTX_TYPE(IEEE802154_L2), IEEE802154_MTU);
#else
DEVICE_DT_INST_DEFINE(0, ieee802154_cc13xx_cc26xx_init, NULL,
&ieee802154_cc13xx_cc26xx_data, NULL, POST_KERNEL,
CONFIG_IEEE802154_CC13XX_CC26XX_INIT_PRIO,
&ieee802154_cc13xx_cc26xx_radio_api);
#endif
``` | /content/code_sandbox/drivers/ieee802154/ieee802154_cc13xx_cc26xx.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 7,250 |
```unknown
menuconfig IEEE802154_UPIPE
bool "UART PIPE fake radio driver support for QEMU"
default y
depends on (BOARD_QEMU_X86 || BOARD_QEMU_CORTEX_M3) && \
DT_HAS_ZEPHYR_IEEE802154_UART_PIPE_ENABLED
select UART_PIPE
if IEEE802154_UPIPE
config IEEE802154_UPIPE_HW_FILTER
bool "Hw Filtering"
default y
help
This option assure the driver will process just frames addressed to him.
config IEEE802154_UPIPE_RANDOM_MAC
bool "Random MAC address"
default y
help
Generate a random MAC address dynamically.
if ! IEEE802154_UPIPE_RANDOM_MAC
config IEEE802154_UPIPE_MAC4
hex "MAC Address Byte 4"
default 0
range 0 0xff
help
This is the byte 4 of the MAC address.
config IEEE802154_UPIPE_MAC5
hex "MAC Address Byte 5"
default 0
range 0 0xff
help
This is the byte 5 of the MAC address.
config IEEE802154_UPIPE_MAC6
hex "MAC Address Byte 6"
default 0
range 0 0xff
help
This is the byte 6 of the MAC address.
config IEEE802154_UPIPE_MAC7
hex "MAC Address Byte 7"
default 0
range 0 0xff
help
This is the byte 7 of the MAC address.
endif # IEEE802154_UPIPE_RANDOM_MAC
endif # IEEE802154_UPIPE
``` | /content/code_sandbox/drivers/ieee802154/Kconfig.uart_pipe | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 333 |
```c
/* ieee802154_cc2520.c - TI CC2520 driver */
#define DT_DRV_COMPAT ti_cc2520
/*
*
*/
#define LOG_MODULE_NAME ieee802154_cc2520
#define LOG_LEVEL CONFIG_IEEE802154_DRIVER_LOG_LEVEL
#include <zephyr/logging/log.h>
LOG_MODULE_REGISTER(LOG_MODULE_NAME);
#include <errno.h>
#include <zephyr/kernel.h>
#include <zephyr/arch/cpu.h>
#include <zephyr/debug/stack.h>
#include <zephyr/device.h>
#include <zephyr/init.h>
#include <zephyr/net/net_if.h>
#include <zephyr/net/net_pkt.h>
#include <zephyr/sys/byteorder.h>
#include <string.h>
#include <zephyr/random/random.h>
#include <zephyr/drivers/gpio.h>
#ifdef CONFIG_IEEE802154_CC2520_CRYPTO
#include <zephyr/crypto/crypto.h>
#include <zephyr/crypto/cipher.h>
#endif /* CONFIG_IEEE802154_CC2520_CRYPTO */
#include <zephyr/net/ieee802154_radio.h>
#include "ieee802154_cc2520.h"
/**
* Content is split as follows:
* 1 - Debug related functions
* 2 - Generic helper functions (for any parts)
* 3 - GPIO related functions
* 4 - TX related helper functions
* 5 - RX related helper functions
* 6 - Radio device API functions
* 7 - Legacy radio device API functions
* 8 - Initialization
*/
#define CC2520_AUTOMATISM (FRMCTRL0_AUTOCRC | FRMCTRL0_AUTOACK)
#define CC2520_TX_THRESHOLD (0x7F)
#define CC2520_FCS_LENGTH (2)
/*********
* DEBUG *
********/
#if LOG_LEVEL == LOG_LEVEL_DBG
static inline void cc2520_print_gpio_config(const struct device *dev)
{
struct cc2520_context *cc2520 = dev->data;
LOG_DBG("GPIOCTRL0/1/2/3/4/5 = 0x%x/0x%x/0x%x/0x%x/0x%x/0x%x",
read_reg_gpioctrl0(cc2520),
read_reg_gpioctrl1(cc2520),
read_reg_gpioctrl2(cc2520),
read_reg_gpioctrl3(cc2520),
read_reg_gpioctrl4(cc2520),
read_reg_gpioctrl5(cc2520));
LOG_DBG("GPIOPOLARITY: 0x%x",
read_reg_gpiopolarity(cc2520));
LOG_DBG("GPIOCTRL: 0x%x",
read_reg_gpioctrl(cc2520));
}
static inline void cc2520_print_exceptions(struct cc2520_context *cc2520)
{
uint8_t flag = read_reg_excflag0(cc2520);
LOG_DBG("EXCFLAG0:");
if (flag & EXCFLAG0_RF_IDLE) {
LOG_DBG(" RF_IDLE");
}
if (flag & EXCFLAG0_TX_FRM_DONE) {
LOG_DBG(" TX_FRM_DONE");
}
if (flag & EXCFLAG0_TX_ACK_DONE) {
LOG_DBG(" TX_ACK_DONE");
}
if (flag & EXCFLAG0_TX_UNDERFLOW) {
LOG_DBG(" TX_UNDERFLOW");
}
if (flag & EXCFLAG0_TX_OVERFLOW) {
LOG_DBG(" TX_OVERFLOW");
}
if (flag & EXCFLAG0_RX_UNDERFLOW) {
LOG_DBG(" RX_UNDERFLOW");
}
if (flag & EXCFLAG0_RX_OVERFLOW) {
LOG_DBG(" RX_OVERFLOW");
}
if (flag & EXCFLAG0_RXENABLE_ZERO) {
LOG_DBG(" RXENABLE_ZERO");
}
flag = read_reg_excflag1(cc2520);
LOG_DBG("EXCFLAG1:");
if (flag & EXCFLAG1_RX_FRM_DONE) {
LOG_DBG(" RX_FRM_DONE");
}
if (flag & EXCFLAG1_RX_FRM_ACCEPTED) {
LOG_DBG(" RX_FRM_ACCEPTED");
}
if (flag & EXCFLAG1_SRC_MATCH_DONE) {
LOG_DBG(" SRC_MATCH_DONE");
}
if (flag & EXCFLAG1_SRC_MATCH_FOUND) {
LOG_DBG(" SRC_MATCH_FOUND");
}
if (flag & EXCFLAG1_FIFOP) {
LOG_DBG(" FIFOP");
}
if (flag & EXCFLAG1_SFD) {
LOG_DBG(" SFD");
}
if (flag & EXCFLAG1_DPU_DONE_L) {
LOG_DBG(" DPU_DONE_L");
}
if (flag & EXCFLAG1_DPU_DONE_H) {
LOG_DBG(" DPU_DONE_H");
}
}
static inline void cc2520_print_errors(struct cc2520_context *cc2520)
{
uint8_t flag = read_reg_excflag2(cc2520);
LOG_DBG("EXCFLAG2:");
if (flag & EXCFLAG2_MEMADDR_ERROR) {
LOG_DBG(" MEMADDR_ERROR");
}
if (flag & EXCFLAG2_USAGE_ERROR) {
LOG_DBG(" USAGE_ERROR");
}
if (flag & EXCFLAG2_OPERAND_ERROR) {
LOG_DBG(" OPERAND_ERROR");
}
if (flag & EXCFLAG2_SPI_ERROR) {
LOG_DBG(" SPI_ERROR");
}
if (flag & EXCFLAG2_RF_NO_LOCK) {
LOG_DBG(" RF_NO_LOCK");
}
if (flag & EXCFLAG2_RX_FRM_ABORTED) {
LOG_DBG(" RX_FRM_ABORTED");
}
if (flag & EXCFLAG2_RFBUFMOV_TIMEOUT) {
LOG_DBG(" RFBUFMOV_TIMEOUT");
}
}
#else
#define cc2520_print_gpio_config(...)
#define cc2520_print_exceptions(...)
#define cc2520_print_errors(...)
#endif /* LOG_LEVEL == LOG_LEVEL_DBG */
/*********************
* Generic functions *
********************/
#define z_usleep(usec) k_busy_wait(usec)
bool z_cc2520_access(const struct device *dev, bool read, uint8_t ins,
uint16_t addr, void *data, size_t length)
{
const struct cc2520_config *cfg = dev->config;
uint8_t cmd_buf[2];
struct spi_buf buf[2] = {
{
.buf = cmd_buf,
.len = 1,
},
{
.buf = data,
.len = length,
}
};
struct spi_buf_set tx = {
.buffers = buf,
};
cmd_buf[0] = ins;
if (ins == CC2520_INS_MEMRD || ins == CC2520_INS_MEMWR) {
buf[0].len = 2;
cmd_buf[0] |= (uint8_t)(addr >> 8);
cmd_buf[1] = (uint8_t)(addr & 0xff);
} else if (ins == CC2520_INS_REGRD || ins == CC2520_INS_REGWR) {
cmd_buf[0] |= (uint8_t)(addr & 0xff);
}
if (read) {
const struct spi_buf_set rx = {
.buffers = buf,
.count = 2
};
tx.count = 1;
return (spi_transceive_dt(&cfg->bus, &tx, &rx) == 0);
}
tx.count = data ? 2 : 1;
return (spi_write_dt(&cfg->bus, &tx) == 0);
}
static inline uint8_t cc2520_status(const struct device *dev)
{
uint8_t status;
if (z_cc2520_access(dev, true, CC2520_INS_SNOP, 0, &status, 1)) {
return status;
}
return 0;
}
static bool verify_osc_stabilization(const struct device *dev)
{
uint8_t timeout = 100U;
uint8_t status;
do {
status = cc2520_status(dev);
z_usleep(1);
timeout--;
} while (!(status & CC2520_STATUS_XOSC_STABLE_N_RUNNING) && timeout);
return !!(status & CC2520_STATUS_XOSC_STABLE_N_RUNNING);
}
static inline uint8_t *get_mac(const struct device *dev)
{
struct cc2520_context *cc2520 = dev->data;
#if defined(CONFIG_IEEE802154_CC2520_RANDOM_MAC)
sys_rand_get(&cc2520->mac_addr[4], 4U);
cc2520->mac_addr[7] = (cc2520->mac_addr[7] & ~0x01) | 0x02;
#else
cc2520->mac_addr[4] = CONFIG_IEEE802154_CC2520_MAC4;
cc2520->mac_addr[5] = CONFIG_IEEE802154_CC2520_MAC5;
cc2520->mac_addr[6] = CONFIG_IEEE802154_CC2520_MAC6;
cc2520->mac_addr[7] = CONFIG_IEEE802154_CC2520_MAC7;
#endif
cc2520->mac_addr[0] = 0x00;
cc2520->mac_addr[1] = 0x12;
cc2520->mac_addr[2] = 0x4b;
cc2520->mac_addr[3] = 0x00;
return cc2520->mac_addr;
}
static int cc2520_set_pan_id(const struct device *dev, uint16_t pan_id)
{
LOG_DBG("0x%x", pan_id);
pan_id = sys_le16_to_cpu(pan_id);
if (!write_mem_pan_id(dev, (uint8_t *) &pan_id)) {
LOG_ERR("Failed");
return -EIO;
}
return 0;
}
static int cc2520_set_short_addr(const struct device *dev,
uint16_t short_addr)
{
LOG_DBG("0x%x", short_addr);
short_addr = sys_le16_to_cpu(short_addr);
if (!write_mem_short_addr(dev, (uint8_t *) &short_addr)) {
LOG_ERR("Failed");
return -EIO;
}
return 0;
}
static int cc2520_set_ieee_addr(const struct device *dev,
const uint8_t *ieee_addr)
{
if (!write_mem_ext_addr(dev, (void *)ieee_addr)) {
LOG_ERR("Failed");
return -EIO;
}
LOG_DBG("IEEE address %02x:%02x:%02x:%02x:%02x:%02x:%02x:%02x",
ieee_addr[7], ieee_addr[6], ieee_addr[5], ieee_addr[4],
ieee_addr[3], ieee_addr[2], ieee_addr[1], ieee_addr[0]);
return 0;
}
/******************
* GPIO functions *
*****************/
static inline void set_reset(const struct device *dev, uint32_t value)
{
const struct cc2520_config *cfg = dev->config;
gpio_pin_set_raw(cfg->reset.port, cfg->reset.pin, value);
}
static inline void set_vreg_en(const struct device *dev, uint32_t value)
{
const struct cc2520_config *cfg = dev->config;
gpio_pin_set_raw(cfg->vreg_en.port, cfg->vreg_en.pin, value);
}
static inline uint32_t get_fifo(const struct device *dev)
{
const struct cc2520_config *cfg = dev->config;
return gpio_pin_get_raw(cfg->fifo.port, cfg->fifo.pin);
}
static inline uint32_t get_fifop(const struct device *dev)
{
const struct cc2520_config *cfg = dev->config;
return gpio_pin_get_raw(cfg->fifop.port, cfg->fifop.pin);
}
static inline uint32_t get_cca(const struct device *dev)
{
const struct cc2520_config *cfg = dev->config;
return gpio_pin_get_raw(cfg->cca.port, cfg->cca.pin);
}
static inline void sfd_int_handler(const struct device *port,
struct gpio_callback *cb, uint32_t pins)
{
struct cc2520_context *cc2520 =
CONTAINER_OF(cb, struct cc2520_context, sfd_cb);
if (atomic_get(&cc2520->tx) == 1) {
atomic_set(&cc2520->tx, 0);
k_sem_give(&cc2520->tx_sync);
}
}
static inline void fifop_int_handler(const struct device *port,
struct gpio_callback *cb, uint32_t pins)
{
struct cc2520_context *cc2520 =
CONTAINER_OF(cb, struct cc2520_context, fifop_cb);
/* Note: Errata document - 1.2 */
if (!get_fifop(cc2520->dev) && !get_fifop(cc2520->dev)) {
return;
}
if (!get_fifo(cc2520->dev)) {
cc2520->overflow = true;
}
k_sem_give(&cc2520->rx_lock);
}
static void enable_fifop_interrupt(const struct device *dev,
bool enable)
{
const struct cc2520_config *cfg = dev->config;
gpio_flags_t mode = enable ? GPIO_INT_EDGE_TO_ACTIVE : GPIO_INT_DISABLE;
gpio_pin_interrupt_configure_dt(&cfg->fifop, mode);
}
static void enable_sfd_interrupt(const struct device *dev,
bool enable)
{
const struct cc2520_config *cfg = dev->config;
gpio_flags_t mode = enable ? GPIO_INT_EDGE_TO_ACTIVE : GPIO_INT_DISABLE;
gpio_pin_interrupt_configure_dt(&cfg->sfd, mode);
}
static inline int setup_gpio_callbacks(const struct device *dev)
{
const struct cc2520_config *cfg = dev->config;
struct cc2520_context *cc2520 = dev->data;
gpio_init_callback(&cc2520->sfd_cb, sfd_int_handler, BIT(cfg->sfd.pin));
if (gpio_add_callback(cfg->sfd.port, &cc2520->sfd_cb) != 0) {
return -EIO;
}
gpio_init_callback(&cc2520->fifop_cb, fifop_int_handler, BIT(cfg->fifop.pin));
if (gpio_add_callback(cfg->fifop.port, &cc2520->fifop_cb) != 0) {
return -EIO;
}
return 0;
}
/****************
* TX functions *
***************/
static inline bool write_txfifo_length(const struct device *dev, uint8_t len)
{
uint8_t length = len + CC2520_FCS_LENGTH;
return z_cc2520_access(dev, false, CC2520_INS_TXBUF, 0, &length, 1);
}
static inline bool write_txfifo_content(const struct device *dev,
uint8_t *frame, uint8_t len)
{
return z_cc2520_access(dev, false, CC2520_INS_TXBUF, 0, frame, len);
}
static inline bool verify_txfifo_status(const struct device *dev,
uint8_t len)
{
if (read_reg_txfifocnt(dev) < len ||
(read_reg_excflag0(dev) & EXCFLAG0_TX_UNDERFLOW)) {
return false;
}
return true;
}
static inline bool verify_tx_done(const struct device *dev)
{
uint8_t timeout = 10U;
uint8_t status;
do {
z_usleep(1);
timeout--;
status = read_reg_excflag0(dev);
} while (!(status & EXCFLAG0_TX_FRM_DONE) && timeout);
return !!(status & EXCFLAG0_TX_FRM_DONE);
}
/****************
* RX functions *
***************/
static inline void flush_rxfifo(const struct device *dev)
{
/* Note: Errata document - 1.1 */
enable_fifop_interrupt(dev, false);
instruct_sflushrx(dev);
instruct_sflushrx(dev);
enable_fifop_interrupt(dev, true);
write_reg_excflag0(dev, EXCFLAG0_RESET_RX_FLAGS);
}
static inline uint8_t read_rxfifo_length(const struct device *dev)
{
uint8_t len;
if (z_cc2520_access(dev, true, CC2520_INS_RXBUF, 0, &len, 1)) {
return len;
}
return 0;
}
static inline bool read_rxfifo_content(const struct device *dev,
struct net_buf *buf, uint8_t len)
{
if (!z_cc2520_access(dev, true, CC2520_INS_RXBUF, 0, buf->data, len)) {
return false;
}
if (read_reg_excflag0(dev) & EXCFLAG0_RX_UNDERFLOW) {
LOG_ERR("RX underflow!");
return false;
}
net_buf_add(buf, len);
return true;
}
static inline void insert_radio_noise_details(struct net_pkt *pkt, uint8_t *status)
{
uint8_t lqi;
net_pkt_set_ieee802154_rssi_dbm(pkt, (int8_t) status[0]);
/**
* CC2520 does not provide an LQI but a correlation factor.
* See Section 20.6
* Such calculation can be loosely used to transform it to lqi:
* corr <= 50 ? lqi = 0
* or:
* corr >= 110 ? lqi = 255
* else:
* lqi = (lqi - 50) * 4
*/
lqi = status[1] & CC2520_FCS_CORRELATION;
if (lqi <= 50U) {
lqi = 0U;
} else if (lqi >= 110U) {
lqi = 255U;
} else {
lqi = (lqi - 50U) << 2;
}
net_pkt_set_ieee802154_lqi(pkt, lqi);
}
static inline bool verify_crc(const struct device *dev, struct net_pkt *pkt)
{
uint8_t status[2];
if (!z_cc2520_access(dev, true, CC2520_INS_RXBUF, 0, &status, 2)) {
return false;
}
if (!(status[1] & CC2520_FCS_CRC_OK)) {
return false;
}
insert_radio_noise_details(pkt, status);
return true;
}
static inline bool verify_rxfifo_validity(const struct device *dev,
uint8_t pkt_len)
{
if (pkt_len < 2 || read_reg_rxfifocnt(dev) != pkt_len) {
return false;
}
return true;
}
static void cc2520_rx(void *p1, void *p2, void *p3)
{
ARG_UNUSED(p2);
ARG_UNUSED(p3);
const struct device *dev = p1;
struct cc2520_context *cc2520 = dev->data;
struct net_pkt *pkt;
uint8_t pkt_len;
while (1) {
pkt = NULL;
k_sem_take(&cc2520->rx_lock, K_FOREVER);
if (cc2520->overflow) {
LOG_ERR("RX overflow!");
cc2520->overflow = false;
goto flush;
}
pkt_len = read_rxfifo_length(dev) & 0x7f;
if (!verify_rxfifo_validity(dev, pkt_len)) {
LOG_ERR("Invalid content");
goto flush;
}
pkt = net_pkt_rx_alloc_with_buffer(cc2520->iface, pkt_len,
AF_UNSPEC, 0, K_NO_WAIT);
if (!pkt) {
LOG_ERR("No pkt available");
goto flush;
}
if (!IS_ENABLED(CONFIG_IEEE802154_RAW_MODE)) {
pkt_len -= 2U;
}
if (!read_rxfifo_content(dev, pkt->buffer, pkt_len)) {
LOG_ERR("No content read");
goto flush;
}
if (!verify_crc(dev, pkt)) {
LOG_ERR("Bad packet CRC");
goto out;
}
if (ieee802154_handle_ack(cc2520->iface, pkt) == NET_OK) {
LOG_DBG("ACK packet handled");
goto out;
}
LOG_DBG("Caught a packet (%u)", pkt_len);
if (net_recv_data(cc2520->iface, pkt) < 0) {
LOG_DBG("Packet dropped by NET stack");
goto out;
}
log_stack_usage(&cc2520->cc2520_rx_thread);
continue;
flush:
cc2520_print_exceptions(cc2520);
cc2520_print_errors(cc2520);
flush_rxfifo(dev);
out:
if (pkt) {
net_pkt_unref(pkt);
}
}
}
/********************
* Radio device API *
*******************/
static enum ieee802154_hw_caps cc2520_get_capabilities(const struct device *dev)
{
/* TODO: Add support for IEEE802154_HW_PROMISC */
return IEEE802154_HW_FCS | IEEE802154_HW_FILTER |
IEEE802154_HW_RX_TX_ACK;
}
static int cc2520_cca(const struct device *dev)
{
if (!get_cca(dev)) {
LOG_WRN("Busy");
return -EBUSY;
}
return 0;
}
static int cc2520_set_channel(const struct device *dev, uint16_t channel)
{
LOG_DBG("%u", channel);
if (channel > 26) {
return -EINVAL;
}
if (channel < 11) {
return -ENOTSUP;
}
/* See chapter 16 */
channel = 11 + (channel - 11) * 5U;
if (!write_reg_freqctrl(dev, FREQCTRL_FREQ(channel))) {
LOG_ERR("Failed");
return -EIO;
}
return 0;
}
static int cc2520_filter(const struct device *dev,
bool set,
enum ieee802154_filter_type type,
const struct ieee802154_filter *filter)
{
LOG_DBG("Applying filter %u", type);
if (!set) {
return -ENOTSUP;
}
if (type == IEEE802154_FILTER_TYPE_IEEE_ADDR) {
return cc2520_set_ieee_addr(dev, filter->ieee_addr);
} else if (type == IEEE802154_FILTER_TYPE_SHORT_ADDR) {
return cc2520_set_short_addr(dev, filter->short_addr);
} else if (type == IEEE802154_FILTER_TYPE_PAN_ID) {
return cc2520_set_pan_id(dev, filter->pan_id);
}
return -ENOTSUP;
}
static int cc2520_set_txpower(const struct device *dev, int16_t dbm)
{
uint8_t pwr;
LOG_DBG("%d", dbm);
/* See chapter 19 part 8 */
switch (dbm) {
case 5:
pwr = 0xF7;
break;
case 3:
pwr = 0xF2;
break;
case 2:
pwr = 0xAB;
break;
case 1:
pwr = 0x13;
break;
case 0:
pwr = 0x32;
break;
case -2:
pwr = 0x81;
break;
case -4:
pwr = 0x88;
break;
case -7:
pwr = 0x2C;
break;
case -18:
pwr = 0x03;
break;
default:
goto error;
}
if (!write_reg_txpower(dev, pwr)) {
goto error;
}
return 0;
error:
LOG_ERR("Failed");
return -EIO;
}
static int cc2520_tx(const struct device *dev,
enum ieee802154_tx_mode mode,
struct net_pkt *pkt,
struct net_buf *frag)
{
uint8_t *frame = frag->data;
uint8_t len = frag->len;
struct cc2520_context *cc2520 = dev->data;
uint8_t retry = 2U;
bool status;
if (mode != IEEE802154_TX_MODE_DIRECT) {
NET_ERR("TX mode %d not supported", mode);
return -ENOTSUP;
}
LOG_DBG("%p (%u)", frag, len);
if (!write_reg_excflag0(dev, EXCFLAG0_RESET_TX_FLAGS) ||
!write_txfifo_length(dev, len) ||
!write_txfifo_content(dev, frame, len)) {
LOG_ERR("Cannot feed in TX fifo");
goto error;
}
if (!verify_txfifo_status(dev, len)) {
LOG_ERR("Did not write properly into TX FIFO");
goto error;
}
#ifdef CONFIG_IEEE802154_CC2520_CRYPTO
k_sem_take(&cc2520->access_lock, K_FOREVER);
#endif
/* 1 retry is allowed here */
do {
atomic_set(&cc2520->tx, 1);
k_sem_init(&cc2520->tx_sync, 0, K_SEM_MAX_LIMIT);
if (!instruct_stxoncca(dev)) {
LOG_ERR("Cannot start transmission");
goto error;
}
/* TODO: Implement standard conforming CSMA/CA or use the soft MAC's default. */
k_sem_take(&cc2520->tx_sync, K_MSEC(10));
retry--;
status = verify_tx_done(dev);
} while (!status && retry);
#ifdef CONFIG_IEEE802154_CC2520_CRYPTO
k_sem_give(&cc2520->access_lock);
#endif
if (status) {
return 0;
}
error:
#ifdef CONFIG_IEEE802154_CC2520_CRYPTO
k_sem_give(&cc2520->access_lock);
#endif
LOG_ERR("No TX_FRM_DONE");
cc2520_print_exceptions(cc2520);
cc2520_print_errors(cc2520);
atomic_set(&cc2520->tx, 0);
instruct_sflushtx(dev);
return -EIO;
}
static int cc2520_start(const struct device *dev)
{
if (!instruct_sxoscon(dev) ||
!instruct_srxon(dev) ||
!verify_osc_stabilization(dev)) {
LOG_ERR("Error starting CC2520");
return -EIO;
}
flush_rxfifo(dev);
enable_fifop_interrupt(dev, true);
enable_sfd_interrupt(dev, true);
return 0;
}
static int cc2520_stop(const struct device *dev)
{
flush_rxfifo(dev);
enable_fifop_interrupt(dev, false);
enable_sfd_interrupt(dev, false);
if (!instruct_srfoff(dev) ||
!instruct_sxoscoff(dev)) {
LOG_ERR("Error stopping CC2520");
return -EIO;
}
return 0;
}
/* driver-allocated attribute memory - constant across all driver instances */
IEEE802154_DEFINE_PHY_SUPPORTED_CHANNELS(drv_attr, 11, 26);
static int cc2520_attr_get(const struct device *dev, enum ieee802154_attr attr,
struct ieee802154_attr_value *value)
{
ARG_UNUSED(dev);
return ieee802154_attr_get_channel_page_and_range(
attr, IEEE802154_ATTR_PHY_CHANNEL_PAGE_ZERO_OQPSK_2450_BPSK_868_915,
&drv_attr.phy_supported_channels, value);
}
/******************
* Initialization *
*****************/
static int power_on_and_setup(const struct device *dev)
{
/* Switching to LPM2 mode */
set_reset(dev, 0);
z_usleep(150);
set_vreg_en(dev, 0);
z_usleep(250);
/* Then to ACTIVE mode */
set_vreg_en(dev, 1);
z_usleep(250);
set_reset(dev, 1);
z_usleep(150);
if (!verify_osc_stabilization(dev)) {
return -EIO;
}
/* Default settings to always write (see chapter 28 part 1) */
if (!write_reg_txpower(dev, CC2520_TXPOWER_DEFAULT) ||
!write_reg_ccactrl0(dev, CC2520_CCACTRL0_DEFAULT) ||
!write_reg_mdmctrl0(dev, CC2520_MDMCTRL0_DEFAULT) ||
!write_reg_mdmctrl1(dev, CC2520_MDMCTRL1_DEFAULT) ||
!write_reg_rxctrl(dev, CC2520_RXCTRL_DEFAULT) ||
!write_reg_fsctrl(dev, CC2520_FSCTRL_DEFAULT) ||
!write_reg_fscal1(dev, CC2520_FSCAL1_DEFAULT) ||
!write_reg_agcctrl1(dev, CC2520_AGCCTRL1_DEFAULT) ||
!write_reg_adctest0(dev, CC2520_ADCTEST0_DEFAULT) ||
!write_reg_adctest1(dev, CC2520_ADCTEST1_DEFAULT) ||
!write_reg_adctest2(dev, CC2520_ADCTEST2_DEFAULT)) {
return -EIO;
}
/* EXTCLOCK0: Disabling external clock
* FRMCTRL0: AUTOACK and AUTOCRC enabled
* FRMCTRL1: SET_RXENMASK_ON_TX and IGNORE_TX_UNDERF
* FRMFILT0: Frame filtering (setting CC2520_FRAME_FILTERING)
* FIFOPCTRL: Set TX threshold (setting CC2520_TX_THRESHOLD)
*/
if (!write_reg_extclock(dev, 0) ||
!write_reg_frmctrl0(dev, CC2520_AUTOMATISM) ||
!write_reg_frmctrl1(dev, FRMCTRL1_IGNORE_TX_UNDERF |
FRMCTRL1_SET_RXENMASK_ON_TX) ||
!write_reg_frmfilt0(dev, FRMFILT0_FRAME_FILTER_EN |
FRMFILT0_MAX_FRAME_VERSION(3)) ||
!write_reg_frmfilt1(dev, FRMFILT1_ACCEPT_ALL) ||
!write_reg_srcmatch(dev, SRCMATCH_DEFAULTS) ||
!write_reg_fifopctrl(dev,
FIFOPCTRL_FIFOP_THR(CC2520_TX_THRESHOLD))) {
return -EIO;
}
/* Cleaning up TX fifo */
instruct_sflushtx(dev);
if (setup_gpio_callbacks(dev) != 0) {
return -EIO;
}
cc2520_print_gpio_config(dev);
return 0;
}
static int configure_gpios(const struct device *dev)
{
const struct cc2520_config *cfg = dev->config;
if (!gpio_is_ready_dt(&cfg->vreg_en) ||
!gpio_is_ready_dt(&cfg->reset) ||
!gpio_is_ready_dt(&cfg->fifo) ||
!gpio_is_ready_dt(&cfg->cca) ||
!gpio_is_ready_dt(&cfg->sfd) ||
!gpio_is_ready_dt(&cfg->fifop)) {
return -ENODEV;
}
gpio_pin_configure_dt(&cfg->vreg_en, GPIO_OUTPUT_LOW);
gpio_pin_configure_dt(&cfg->reset, GPIO_OUTPUT_LOW);
gpio_pin_configure_dt(&cfg->fifo, GPIO_INPUT);
gpio_pin_configure_dt(&cfg->cca, GPIO_INPUT);
gpio_pin_configure_dt(&cfg->sfd, GPIO_INPUT);
gpio_pin_configure_dt(&cfg->fifop, GPIO_INPUT);
return 0;
}
static int cc2520_init(const struct device *dev)
{
const struct cc2520_config *cfg = dev->config;
struct cc2520_context *cc2520 = dev->data;
cc2520->dev = dev;
atomic_set(&cc2520->tx, 0);
k_sem_init(&cc2520->rx_lock, 0, K_SEM_MAX_LIMIT);
#ifdef CONFIG_IEEE802154_CC2520_CRYPTO
k_sem_init(&cc2520->access_lock, 1, 1);
#endif
if (configure_gpios(dev) != 0) {
LOG_ERR("Configuring GPIOS failed");
return -EIO;
}
if (!spi_is_ready_dt(&cfg->bus)) {
LOG_ERR("SPI bus %s not ready", cfg->bus.bus->name);
return -EIO;
}
LOG_DBG("GPIO and SPI configured");
if (power_on_and_setup(dev) != 0) {
LOG_ERR("Configuring CC2520 failed");
return -EIO;
}
k_thread_create(&cc2520->cc2520_rx_thread, cc2520->cc2520_rx_stack,
CONFIG_IEEE802154_CC2520_RX_STACK_SIZE,
cc2520_rx,
(void *)dev, NULL, NULL, K_PRIO_COOP(2), 0, K_NO_WAIT);
k_thread_name_set(&cc2520->cc2520_rx_thread, "cc2520_rx");
LOG_INF("CC2520 initialized");
return 0;
}
static void cc2520_iface_init(struct net_if *iface)
{
const struct device *dev = net_if_get_device(iface);
struct cc2520_context *cc2520 = dev->data;
uint8_t *mac = get_mac(dev);
net_if_set_link_addr(iface, mac, 8, NET_LINK_IEEE802154);
cc2520->iface = iface;
ieee802154_init(iface);
}
static const struct cc2520_config cc2520_config = {
.bus = SPI_DT_SPEC_INST_GET(0, SPI_WORD_SET(8), 0),
.vreg_en = GPIO_DT_SPEC_INST_GET(0, vreg_en_gpios),
.reset = GPIO_DT_SPEC_INST_GET(0, reset_gpios),
.fifo = GPIO_DT_SPEC_INST_GET(0, fifo_gpios),
.cca = GPIO_DT_SPEC_INST_GET(0, cca_gpios),
.sfd = GPIO_DT_SPEC_INST_GET(0, sfd_gpios),
.fifop = GPIO_DT_SPEC_INST_GET(0, fifop_gpios)
};
static struct cc2520_context cc2520_context_data;
static const struct ieee802154_radio_api cc2520_radio_api = {
.iface_api.init = cc2520_iface_init,
.get_capabilities = cc2520_get_capabilities,
.cca = cc2520_cca,
.set_channel = cc2520_set_channel,
.filter = cc2520_filter,
.set_txpower = cc2520_set_txpower,
.start = cc2520_start,
.stop = cc2520_stop,
.tx = cc2520_tx,
.attr_get = cc2520_attr_get,
};
#if defined(CONFIG_IEEE802154_RAW_MODE)
DEVICE_DT_INST_DEFINE(0, cc2520_init, NULL, &cc2520_context_data, NULL,
POST_KERNEL, CONFIG_IEEE802154_CC2520_INIT_PRIO,
&cc2520_radio_api);
#else
NET_DEVICE_DT_INST_DEFINE(0, cc2520_init, NULL, &cc2520_context_data,
&cc2520_config, CONFIG_IEEE802154_CC2520_INIT_PRIO,
&cc2520_radio_api, IEEE802154_L2,
NET_L2_GET_CTX_TYPE(IEEE802154_L2), 125);
#endif
#ifdef CONFIG_IEEE802154_CC2520_CRYPTO
static inline bool cc2520_read_ram(const struct device *dev, uint16_t addr,
uint8_t *data_buf, uint8_t len)
{
return z_cc2520_access(dev, true, CC2520_INS_MEMRD,
addr, data_buf, len);
}
static inline bool cc2520_write_ram(const struct device *dev, uint16_t addr,
uint8_t *data_buf, uint8_t len)
{
return z_cc2520_access(dev, false, CC2520_INS_MEMWR,
addr, data_buf, len);
}
static inline bool instruct_uccm_ccm(const struct device *dev,
bool uccm,
uint8_t key_addr,
uint8_t auth_crypt,
uint8_t nonce_addr,
uint16_t input_addr,
uint16_t output_addr,
uint8_t in_len,
uint8_t m)
{
const struct cc2520_config *cfg = dev->config;
struct cc2520_context *ctx = dev->data;
uint8_t cmd[9];
const struct spi_buf buf[1] = {
{
.buf = cmd,
.len = 9,
},
};
const struct spi_buf_set tx = {
.buffers = buf,
.count = 1
};
int ret;
LOG_DBG("%sCCM(P={01} K={%02x} C={%02x} N={%02x}"
" A={%03x} E={%03x} F{%02x} M={%02x})",
uccm ? "U" : "", key_addr, auth_crypt, nonce_addr,
input_addr, output_addr, in_len, m);
cmd[0] = uccm ? CC2520_INS_UCCM | 1 : CC2520_INS_CCM | 1;
cmd[1] = key_addr;
cmd[2] = (auth_crypt & 0x7f);
cmd[3] = nonce_addr;
cmd[4] = (uint8_t)(((input_addr & 0x0f00) >> 4) |
((output_addr & 0x0f00) >> 8));
cmd[5] = (uint8_t)(input_addr & 0x00ff);
cmd[6] = (uint8_t)(output_addr & 0x00ff);
cmd[7] = (in_len & 0x7f);
cmd[8] = (m & 0x03);
k_sem_take(&ctx->access_lock, K_FOREVER);
ret = spi_write_dt(&cfg->bus, &tx);
k_sem_give(&ctx->access_lock);
if (ret) {
LOG_ERR("%sCCM Failed", uccm ? "U" : "");
return false;
}
return true;
}
static inline void generate_nonce(uint8_t *ccm_nonce, uint8_t *nonce,
struct cipher_aead_pkt *apkt, uint8_t m)
{
nonce[0] = 0 | (apkt->ad_len ? 0x40 : 0) | (m << 3) | 1;
memcpy(&nonce[1], ccm_nonce, 13);
nonce[14] = (uint8_t)(apkt->pkt->in_len >> 8);
nonce[15] = (uint8_t)(apkt->pkt->in_len);
/* See section 26.8.1 */
sys_mem_swap(nonce, 16);
}
static int insert_crypto_parameters(struct cipher_ctx *ctx,
struct cipher_aead_pkt *apkt,
uint8_t *ccm_nonce, uint8_t *auth_crypt)
{
const struct device *cc2520 = ctx->device;
uint8_t data[128];
uint8_t *in_buf;
uint8_t in_len;
uint8_t m = 0U;
if (!apkt->pkt->out_buf || !apkt->pkt->out_buf_max) {
LOG_ERR("Out buffer needs to be set");
return -EINVAL;
}
if (!ctx->key.bit_stream || !ctx->keylen) {
LOG_ERR("No key installed");
return -EINVAL;
}
if (!(ctx->flags & CAP_INPLACE_OPS)) {
LOG_ERR("It supports only in-place operation");
return -EINVAL;
}
if (!apkt->ad || !apkt->ad_len) {
LOG_ERR("CCM needs associated data");
return -EINVAL;
}
if (apkt->pkt->in_buf && apkt->pkt->in_buf - apkt->ad_len != apkt->ad) {
LOG_ERR("In-place needs ad and input in same memory");
return -EINVAL;
}
if (!apkt->pkt->in_buf) {
if (!ctx->mode_params.ccm_info.tag_len) {
LOG_ERR("Auth only needs a tag length");
return -EINVAL;
}
in_buf = apkt->ad;
in_len = apkt->ad_len;
*auth_crypt = 0U;
} else {
in_buf = data;
memcpy(in_buf, apkt->ad, apkt->ad_len);
memcpy(in_buf + apkt->ad_len,
apkt->pkt->in_buf, apkt->pkt->in_len);
in_len = apkt->ad_len + apkt->pkt->in_len;
*auth_crypt = !apkt->tag ? apkt->pkt->in_len :
apkt->pkt->in_len - ctx->mode_params.ccm_info.tag_len;
}
if (ctx->mode_params.ccm_info.tag_len) {
if ((ctx->mode_params.ccm_info.tag_len >> 2) > 3) {
m = 3U;
} else {
m = ctx->mode_params.ccm_info.tag_len >> 2;
}
}
/* Writing the frame in RAM */
if (!cc2520_write_ram(cc2520, CC2520_MEM_DATA, in_buf, in_len)) {
LOG_ERR("Cannot write the frame in RAM");
return -EIO;
}
/* See section 26.8.1 */
sys_memcpy_swap(data, ctx->key.bit_stream, ctx->keylen);
/* Writing the key in RAM */
if (!cc2520_write_ram(cc2520, CC2520_MEM_KEY, data, 16)) {
LOG_ERR("Cannot write the key in RAM");
return -EIO;
}
generate_nonce(ccm_nonce, data, apkt, m);
/* Writing the nonce in RAM */
if (!cc2520_write_ram(cc2520, CC2520_MEM_NONCE, data, 16)) {
LOG_ERR("Cannot write the nonce in RAM");
return -EIO;
}
return m;
}
static int cc2520_crypto_ccm(struct cipher_ctx *ctx,
struct cipher_aead_pkt *apkt,
uint8_t *ccm_nonce)
{
const struct device *cc2520 = ctx->device;
uint8_t auth_crypt;
int m;
if (!apkt || !apkt->pkt) {
LOG_ERR("Invalid crypto packet to operate with");
return -EINVAL;
}
m = insert_crypto_parameters(ctx, apkt, ccm_nonce, &auth_crypt);
if (m < 0) {
LOG_ERR("Inserting crypto parameters failed");
return m;
}
apkt->pkt->out_len = apkt->pkt->in_len + apkt->ad_len +
(m ? ctx->mode_params.ccm_info.tag_len : 0);
if (apkt->pkt->out_len > apkt->pkt->out_buf_max) {
LOG_ERR("Result will not fit into out buffer %u vs %u",
apkt->pkt->out_len, apkt->pkt->out_buf_max);
return -ENOBUFS;
}
if (!instruct_uccm_ccm(cc2520, false, CC2520_MEM_KEY >> 4, auth_crypt,
CC2520_MEM_NONCE >> 4, CC2520_MEM_DATA,
0x000, apkt->ad_len, m) ||
!cc2520_read_ram(cc2520, CC2520_MEM_DATA,
apkt->pkt->out_buf, apkt->pkt->out_len)) {
LOG_ERR("CCM or reading result from RAM failed");
return -EIO;
}
if (apkt->tag) {
memcpy(apkt->tag, apkt->pkt->out_buf + apkt->pkt->in_len,
ctx->mode_params.ccm_info.tag_len);
}
return 0;
}
static int cc2520_crypto_uccm(struct cipher_ctx *ctx,
struct cipher_aead_pkt *apkt,
uint8_t *ccm_nonce)
{
const struct device *cc2520 = ctx->device;
uint8_t auth_crypt;
int m;
if (!apkt || !apkt->pkt) {
LOG_ERR("Invalid crypto packet to operate with");
return -EINVAL;
}
if (ctx->mode_params.ccm_info.tag_len && !apkt->tag) {
LOG_ERR("In case of MIC you need to provide a tag");
return -EINVAL;
}
m = insert_crypto_parameters(ctx, apkt, ccm_nonce, &auth_crypt);
if (m < 0) {
return m;
}
apkt->pkt->out_len = apkt->pkt->in_len + apkt->ad_len;
if (!instruct_uccm_ccm(cc2520, true, CC2520_MEM_KEY >> 4, auth_crypt,
CC2520_MEM_NONCE >> 4, CC2520_MEM_DATA,
0x000, apkt->ad_len, m) ||
!cc2520_read_ram(cc2520, CC2520_MEM_DATA,
apkt->pkt->out_buf, apkt->pkt->out_len)) {
LOG_ERR("UCCM or reading result from RAM failed");
return -EIO;
}
if (m && (!(read_reg_dpustat(cc2520) & DPUSTAT_AUTHSTAT_H))) {
LOG_ERR("Authentication of the frame failed");
return -EBADMSG;
}
return 0;
}
static int cc2520_crypto_hw_caps(const struct device *dev)
{
return CAP_RAW_KEY | CAP_INPLACE_OPS | CAP_SYNC_OPS;
}
static int cc2520_crypto_begin_session(const struct device *dev,
struct cipher_ctx *ctx,
enum cipher_algo algo,
enum cipher_mode mode,
enum cipher_op op_type)
{
if (algo != CRYPTO_CIPHER_ALGO_AES || mode != CRYPTO_CIPHER_MODE_CCM) {
LOG_ERR("Wrong algo (%u) or mode (%u)", algo, mode);
return -EINVAL;
}
if (ctx->mode_params.ccm_info.nonce_len != 13U) {
LOG_ERR("Nonce length erroneous (%u)",
ctx->mode_params.ccm_info.nonce_len);
return -EINVAL;
}
if (op_type == CRYPTO_CIPHER_OP_ENCRYPT) {
ctx->ops.ccm_crypt_hndlr = cc2520_crypto_ccm;
} else {
ctx->ops.ccm_crypt_hndlr = cc2520_crypto_uccm;
}
ctx->ops.cipher_mode = mode;
ctx->device = dev;
return 0;
}
static int cc2520_crypto_free_session(const struct device *dev,
struct cipher_ctx *ctx)
{
ARG_UNUSED(dev);
ctx->ops.ccm_crypt_hndlr = NULL;
ctx->device = NULL;
return 0;
}
static int cc2520_crypto_init(const struct device *dev)
{
LOG_INF("CC2520 crypto part initialized");
return 0;
}
struct crypto_driver_api cc2520_crypto_api = {
.query_hw_caps = cc2520_crypto_hw_caps,
.cipher_begin_session = cc2520_crypto_begin_session,
.cipher_free_session = cc2520_crypto_free_session,
.cipher_async_callback_set = NULL
};
DEVICE_DEFINE(cc2520_crypto, "cc2520_crypto",
cc2520_crypto_init, NULL,
&cc2520_context_data, NULL, POST_KERNEL,
CONFIG_IEEE802154_CC2520_CRYPTO_INIT_PRIO, &cc2520_crypto_api);
#endif /* CONFIG_IEEE802154_CC2520_CRYPTO */
``` | /content/code_sandbox/drivers/ieee802154/ieee802154_cc2520.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 10,138 |
```objective-c
/* ieee802154_nrf5.h - nRF5 802.15.4 driver */
/*
*
*/
#ifndef ZEPHYR_DRIVERS_IEEE802154_IEEE802154_NRF5_H_
#define ZEPHYR_DRIVERS_IEEE802154_IEEE802154_NRF5_H_
#include <zephyr/net/ieee802154_radio.h>
#define NRF5_PHR_LENGTH (1)
struct nrf5_802154_rx_frame {
void *fifo_reserved; /* 1st word reserved for use by fifo. */
uint8_t *psdu; /* Pointer to a received frame. */
uint64_t time; /* RX timestamp. */
uint8_t lqi; /* Last received frame LQI value. */
int8_t rssi; /* Last received frame RSSI value. */
bool ack_fpb; /* FPB value in ACK sent for the received frame. */
bool ack_seb; /* SEB value in ACK sent for the received frame. */
};
struct nrf5_802154_data {
/* Pointer to the network interface. */
struct net_if *iface;
/* 802.15.4 HW address. */
uint8_t mac[8];
/* RX thread stack. */
K_KERNEL_STACK_MEMBER(rx_stack, CONFIG_IEEE802154_NRF5_RX_STACK_SIZE);
/* RX thread control block. */
struct k_thread rx_thread;
/* RX fifo queue. */
struct k_fifo rx_fifo;
/* Buffers for passing received frame pointers and data to the
* RX thread via rx_fifo object.
*/
struct nrf5_802154_rx_frame rx_frames[CONFIG_NRF_802154_RX_BUFFERS];
/* Frame pending bit value in ACK sent for the last received frame. */
bool last_frame_ack_fpb;
/* Security Enabled bit value in ACK sent for the last received frame. */
bool last_frame_ack_seb;
/* CCA complete semaphore. Unlocked when CCA is complete. */
struct k_sem cca_wait;
/* CCA result. Holds information whether channel is free or not. */
bool channel_free;
/* TX synchronization semaphore. Unlocked when frame has been
* sent or send procedure failed.
*/
struct k_sem tx_wait;
/* TX buffer. First byte is PHR (length), remaining bytes are
* MPDU data.
*/
uint8_t tx_psdu[NRF5_PHR_LENGTH + IEEE802154_MAX_PHY_PACKET_SIZE];
/* TX result, updated in radio transmit callbacks. */
uint8_t tx_result;
/* A buffer for the received ACK frame. psdu pointer be NULL if no
* ACK was requested/received.
*/
struct nrf5_802154_rx_frame ack_frame;
/* Callback handler of the currently ongoing energy scan.
* It shall be NULL if energy scan is not in progress.
*/
energy_scan_done_cb_t energy_scan_done;
/* Callback handler to notify of any important radio events.
* Can be NULL if event notification is not needed.
*/
ieee802154_event_cb_t event_handler;
/* Capabilities of the network interface. */
enum ieee802154_hw_caps capabilities;
/* Indicates if currently processed TX frame is secured. */
bool tx_frame_is_secured;
/* Indicates if currently processed TX frame has dynamic data updated. */
bool tx_frame_mac_hdr_rdy;
#if defined(CONFIG_IEEE802154_NRF5_MULTIPLE_CCA)
/* The maximum number of extra CCA attempts to be performed before transmission. */
uint8_t max_extra_cca_attempts;
#endif
/* The TX power in dBm. */
int8_t txpwr;
#if defined(CONFIG_NRF_802154_SER_HOST) && defined(CONFIG_IEEE802154_CSL_ENDPOINT)
/* The last configured value of CSL period in units of 10 symbols. */
uint32_t csl_period;
/* The last configured value of CSL phase time in nanoseconds. */
net_time_t csl_rx_time;
#endif /* CONFIG_NRF_802154_SER_HOST && CONFIG_IEEE802154_CSL_ENDPOINT */
/* Indicates if RxOnWhenIdle mode is enabled. */
bool rx_on_when_idle;
};
#endif /* ZEPHYR_DRIVERS_IEEE802154_IEEE802154_NRF5_H_ */
``` | /content/code_sandbox/drivers/ieee802154/ieee802154_nrf5.h | objective-c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 894 |
```c
/* ieee802154_rf2xx.c - ATMEL RF2XX IEEE 802.15.4 Driver */
#define DT_DRV_COMPAT atmel_rf2xx
/*
*
*/
#define LOG_MODULE_NAME ieee802154_rf2xx
#define LOG_LEVEL CONFIG_IEEE802154_DRIVER_LOG_LEVEL
#include <zephyr/logging/log.h>
LOG_MODULE_REGISTER(LOG_MODULE_NAME);
#include <errno.h>
#include <stdio.h>
#include <stdlib.h>
#include <zephyr/kernel.h>
#include <zephyr/arch/cpu.h>
#include <zephyr/debug/stack.h>
#include <zephyr/device.h>
#include <zephyr/init.h>
#include <zephyr/net/net_if.h>
#include <zephyr/net/net_pkt.h>
#include <zephyr/sys/byteorder.h>
#include <string.h>
#include <zephyr/random/random.h>
#include <zephyr/linker/sections.h>
#include <zephyr/sys/atomic.h>
#include <zephyr/drivers/spi.h>
#include <zephyr/drivers/gpio.h>
#include <zephyr/net/ieee802154_radio.h>
#include "ieee802154_rf2xx.h"
#include "ieee802154_rf2xx_regs.h"
#include "ieee802154_rf2xx_iface.h"
#if defined(CONFIG_NET_L2_OPENTHREAD)
#include <zephyr/net/openthread.h>
#define RF2XX_OT_PSDU_LENGTH 1280
#define RF2XX_ACK_FRAME_LEN 3
#define RF2XX_ACK_FRAME_TYPE (2 << 0)
#define RF2XX_ACK_FRAME_PENDING_BIT (1 << 4)
#define RF2XX_FRAME_CTRL_ACK_REQUEST_BIT (1 << 5)
static uint8_t rf2xx_ack_psdu[RF2XX_ACK_FRAME_LEN] = { 0 };
static struct net_buf rf2xx_ack_frame = {
.data = rf2xx_ack_psdu,
.size = RF2XX_ACK_FRAME_LEN,
.len = RF2XX_ACK_FRAME_LEN,
.__buf = rf2xx_ack_psdu,
.frags = NULL,
};
static struct net_pkt rf2xx_ack_pkt = {
.buffer = &rf2xx_ack_frame,
.cb = {
.lqi = 80,
.rssi = -40,
}
};
#endif /* CONFIG_NET_L2_OPENTHREAD */
/* Radio Transceiver ISR */
static inline void trx_isr_handler(const struct device *port,
struct gpio_callback *cb,
uint32_t pins)
{
struct rf2xx_context *ctx = CONTAINER_OF(cb,
struct rf2xx_context,
irq_cb);
ARG_UNUSED(port);
ARG_UNUSED(pins);
k_sem_give(&ctx->trx_isr_lock);
}
static void rf2xx_trx_set_state(const struct device *dev,
enum rf2xx_trx_state_cmd_t state)
{
do {
rf2xx_iface_reg_write(dev, RF2XX_TRX_STATE_REG,
RF2XX_TRX_PHY_STATE_CMD_FORCE_TRX_OFF);
} while (RF2XX_TRX_PHY_STATUS_TRX_OFF !=
(rf2xx_iface_reg_read(dev, RF2XX_TRX_STATUS_REG) &
RF2XX_TRX_PHY_STATUS_MASK));
do {
rf2xx_iface_reg_write(dev, RF2XX_TRX_STATE_REG, state);
} while (state !=
(rf2xx_iface_reg_read(dev, RF2XX_TRX_STATUS_REG) &
RF2XX_TRX_PHY_STATUS_MASK));
}
static void rf2xx_trx_set_tx_state(const struct device *dev)
{
uint8_t status;
/**
* Ensures that RX automatically ACK will be sent when requested.
* Datasheet: Chapter 7.2.3 RX_AACK_ON Receive with Automatic ACK
* Datasheet: Figure 7-13. Timing Example of an RX_AACK Transaction
* for Slotted Operation.
*
* This will create a spin lock that wait transceiver be free from
* current receive frame process
*/
do {
status = (rf2xx_iface_reg_read(dev, RF2XX_TRX_STATUS_REG) &
RF2XX_TRX_PHY_STATUS_MASK);
} while (status == RF2XX_TRX_PHY_STATUS_BUSY_RX_AACK ||
status == RF2XX_TRX_PHY_STATUS_STATE_TRANSITION);
rf2xx_trx_set_state(dev, RF2XX_TRX_PHY_STATE_CMD_TRX_OFF);
rf2xx_iface_reg_read(dev, RF2XX_IRQ_STATUS_REG);
rf2xx_trx_set_state(dev, RF2XX_TRX_PHY_STATE_CMD_TX_ARET_ON);
}
static void rf2xx_trx_set_rx_state(const struct device *dev)
{
rf2xx_trx_set_state(dev, RF2XX_TRX_PHY_STATE_CMD_TRX_OFF);
rf2xx_iface_reg_read(dev, RF2XX_IRQ_STATUS_REG);
/**
* Set extended RX mode
* Datasheet: chapter 7.2 Extended Operating Mode
*/
rf2xx_trx_set_state(dev, RF2XX_TRX_PHY_STATE_CMD_RX_AACK_ON);
}
static void rf2xx_set_rssi_base(const struct device *dev, uint16_t channel)
{
struct rf2xx_context *ctx = dev->data;
int8_t base;
if (ctx->cc_page == IEEE802154_ATTR_PHY_CHANNEL_PAGE_ZERO_OQPSK_2450_BPSK_868_915) {
base = channel == 0
? RF2XX_RSSI_BPSK_20
: RF2XX_RSSI_BPSK_40;
} else if (ctx->cc_page == IEEE802154_ATTR_PHY_CHANNEL_PAGE_TWO_OQPSK_868_915) {
base = channel == 0
? RF2XX_RSSI_OQPSK_SIN_RC_100
: RF2XX_RSSI_OQPSK_SIN_250;
} else {
base = RF2XX_RSSI_OQPSK_RC_250;
}
ctx->trx_rssi_base = base;
}
static void rf2xx_trx_rx(const struct device *dev)
{
struct rf2xx_context *ctx = dev->data;
struct net_pkt *pkt = NULL;
uint8_t rx_buf[RX2XX_MAX_FRAME_SIZE];
uint8_t pkt_len;
uint8_t frame_len;
uint8_t trac;
/*
* The rf2xx frame buffer can have length > 128 bytes. The
* net_pkt_rx_alloc_with_buffer allocates max value of 128 bytes.
*
* This obligate the driver to have rx_buf statically allocated with
* RX2XX_MAX_FRAME_SIZE.
*/
if (ctx->trx_model != RF2XX_TRX_MODEL_231) {
pkt_len = ctx->rx_phr;
} else {
rf2xx_iface_frame_read(dev, rx_buf, RX2XX_FRAME_HEADER_SIZE);
pkt_len = rx_buf[RX2XX_FRAME_PHR_INDEX];
}
if (!ctx->promiscuous && pkt_len < RX2XX_FRAME_MIN_PHR_SIZE) {
LOG_ERR("Invalid RX frame length");
return;
}
frame_len = RX2XX_FRAME_HEADER_SIZE + pkt_len +
RX2XX_FRAME_FOOTER_SIZE;
rf2xx_iface_frame_read(dev, rx_buf, frame_len);
if (ctx->trx_model != RF2XX_TRX_MODEL_231) {
trac = rx_buf[pkt_len + RX2XX_FRAME_TRAC_INDEX];
trac = (trac >> RF2XX_RX_TRAC_STATUS) & RF2XX_RX_TRAC_BIT_MASK;
ctx->pkt_ed = rx_buf[pkt_len + RX2XX_FRAME_ED_INDEX];
} else {
trac = (rf2xx_iface_reg_read(dev, RF2XX_TRX_STATE_REG)
>> RF2XX_TRAC_STATUS) & RF2XX_TRAC_BIT_MASK;
ctx->pkt_ed = (rf2xx_iface_reg_read(dev, RF2XX_PHY_RSSI_REG)
>> RF2XX_RSSI) & RF2XX_RSSI_MASK;
}
ctx->pkt_lqi = rx_buf[pkt_len + RX2XX_FRAME_LQI_INDEX];
if (!ctx->promiscuous && trac == RF2XX_TRX_PHY_STATE_TRAC_INVALID) {
LOG_ERR("Invalid RX frame");
return;
}
if (!IS_ENABLED(CONFIG_IEEE802154_RAW_MODE) &&
!IS_ENABLED(CONFIG_NET_L2_OPENTHREAD) &&
pkt_len >= RX2XX_FRAME_FCS_LENGTH) {
pkt_len -= RX2XX_FRAME_FCS_LENGTH;
}
pkt = net_pkt_rx_alloc_with_buffer(ctx->iface, pkt_len,
AF_UNSPEC, 0, K_NO_WAIT);
if (!pkt) {
LOG_ERR("No RX buffer available");
return;
}
memcpy(pkt->buffer->data, rx_buf + RX2XX_FRAME_HEADER_SIZE, pkt_len);
net_buf_add(pkt->buffer, pkt_len);
net_pkt_set_ieee802154_lqi(pkt, ctx->pkt_lqi);
net_pkt_set_ieee802154_rssi_dbm(pkt, ctx->pkt_ed + ctx->trx_rssi_base);
LOG_DBG("Caught a packet (%02X) (LQI: %02X, RSSI: %d, ED: %02X)",
pkt_len, ctx->pkt_lqi, ctx->trx_rssi_base + ctx->pkt_ed,
ctx->pkt_ed);
if (net_recv_data(ctx->iface, pkt) < 0) {
LOG_DBG("RX Packet dropped by NET stack");
net_pkt_unref(pkt);
return;
}
if (LOG_LEVEL >= LOG_LEVEL_DBG) {
log_stack_usage(&ctx->trx_thread);
}
}
static void rf2xx_process_rx_frame(const struct device *dev)
{
struct rf2xx_context *ctx = dev->data;
/*
* NOTE: In promiscuous mode invalid frames will be processed.
*/
if (ctx->trx_model != RF2XX_TRX_MODEL_231) {
rf2xx_trx_rx(dev);
} else {
/* Ensures that automatically ACK will be sent
* when requested
*/
while (rf2xx_iface_reg_read(dev, RF2XX_TRX_STATUS_REG) ==
RF2XX_TRX_PHY_STATUS_BUSY_RX_AACK) {
;
}
/* Set PLL_ON to avoid transceiver receive
* new data until finish reading process
*/
rf2xx_trx_set_state(dev, RF2XX_TRX_PHY_STATE_CMD_PLL_ON);
rf2xx_trx_rx(dev);
rf2xx_trx_set_state(dev, RF2XX_TRX_PHY_STATE_CMD_RX_AACK_ON);
}
}
static void rf2xx_process_tx_frame(const struct device *dev)
{
struct rf2xx_context *ctx = dev->data;
ctx->trx_trac = (rf2xx_iface_reg_read(dev, RF2XX_TRX_STATE_REG) >>
RF2XX_TRAC_STATUS) & RF2XX_TRAC_BIT_MASK;
k_sem_give(&ctx->trx_tx_sync);
rf2xx_trx_set_rx_state(dev);
}
static void rf2xx_process_trx_end(const struct device *dev)
{
uint8_t trx_status = (rf2xx_iface_reg_read(dev, RF2XX_TRX_STATUS_REG) &
RF2XX_TRX_PHY_STATUS_MASK);
if (trx_status == RF2XX_TRX_PHY_STATUS_TX_ARET_ON) {
rf2xx_process_tx_frame(dev);
} else {
rf2xx_process_rx_frame(dev);
}
}
static void rf2xx_thread_main(void *p1, void *p2, void *p3)
{
ARG_UNUSED(p2);
ARG_UNUSED(p3);
struct rf2xx_context *ctx = p1;
uint8_t isr_status;
while (true) {
k_sem_take(&ctx->trx_isr_lock, K_FOREVER);
isr_status = rf2xx_iface_reg_read(ctx->dev,
RF2XX_IRQ_STATUS_REG);
/*
* IRQ_7 (BAT_LOW) Indicates a supply voltage below the
* programmed threshold. 9.5.4
* IRQ_6 (TRX_UR) Indicates a Frame Buffer access
* violation. 9.3.3
* IRQ_5 (AMI) Indicates address matching. 8.2
* IRQ_4 (CCA_ED_DONE) Multi-functional interrupt:
* 1. AWAKE_END: 7.1.2.5
* Indicates finished transition to TRX_OFF state
* from P_ON, SLEEP, DEEP_SLEEP, or RESET state.
* 2. CCA_ED_DONE: 8.5.4
* Indicates the end of a CCA or ED
* measurement. 8.6.4
* IRQ_3 (TRX_END)
* RX: Indicates the completion of a frame
* reception. 7.1.3
* TX: Indicates the completion of a frame
* transmission. 7.1.3
* IRQ_2 (RX_START) Indicates the start of a PSDU
* reception; the AT86RF233 state changed to BUSY_RX;
* the PHR can be read from Frame Buffer. 7.1.3
* IRQ_1 (PLL_UNLOCK) Indicates PLL unlock. If the radio
* transceiver is in BUSY_TX / BUSY_TX_ARET state, the
* PA is turned off immediately. 9.7.5
* IRQ_0 (PLL_LOCK) Indicates PLL lock.
*/
if (isr_status & (1 << RF2XX_RX_START)) {
if (ctx->trx_model != RF2XX_TRX_MODEL_231) {
rf2xx_iface_sram_read(ctx->dev, 0,
&ctx->rx_phr, 1);
}
}
if (isr_status & (1 << RF2XX_TRX_END)) {
rf2xx_process_trx_end(ctx->dev);
}
}
}
static inline uint8_t *get_mac(const struct device *dev)
{
const struct rf2xx_config *conf = dev->config;
struct rf2xx_context *ctx = dev->data;
if (!conf->has_mac) {
sys_rand_get(ctx->mac_addr, sizeof(ctx->mac_addr));
}
/*
* Clear bit 0 to ensure it isn't a multicast address and set
* bit 1 to indicate address is locally administered and may
* not be globally unique.
*/
ctx->mac_addr[0] = (ctx->mac_addr[0] & ~0x01) | 0x02;
return ctx->mac_addr;
}
static enum ieee802154_hw_caps rf2xx_get_capabilities(const struct device *dev)
{
LOG_DBG("HW Caps");
return IEEE802154_HW_FCS |
IEEE802154_HW_PROMISC |
IEEE802154_HW_FILTER |
IEEE802154_HW_CSMA |
IEEE802154_HW_RETRANSMISSION |
IEEE802154_HW_TX_RX_ACK |
IEEE802154_HW_RX_TX_ACK;
}
static int rf2xx_configure_sub_channel(const struct device *dev, uint16_t channel)
{
struct rf2xx_context *ctx = dev->data;
uint8_t reg;
uint8_t cc_mask;
if (ctx->cc_page == IEEE802154_ATTR_PHY_CHANNEL_PAGE_ZERO_OQPSK_2450_BPSK_868_915) {
cc_mask = channel == 0
? RF2XX_CC_BPSK_20
: RF2XX_CC_BPSK_40;
} else if (ctx->cc_page == IEEE802154_ATTR_PHY_CHANNEL_PAGE_TWO_OQPSK_868_915) {
cc_mask = channel == 0
? RF2XX_CC_OQPSK_SIN_RC_100
: RF2XX_CC_OQPSK_SIN_250;
} else {
cc_mask = RF2XX_CC_OQPSK_RC_250;
}
reg = rf2xx_iface_reg_read(dev, RF2XX_TRX_CTRL_2_REG)
& ~RF2XX_SUB_CHANNEL_MASK;
rf2xx_iface_reg_write(dev, RF2XX_TRX_CTRL_2_REG, reg | cc_mask);
return 0;
}
static int rf2xx_configure_trx_path(const struct device *dev)
{
struct rf2xx_context *ctx = dev->data;
uint8_t reg;
uint8_t gc_tx_offset;
if (ctx->cc_page == IEEE802154_ATTR_PHY_CHANNEL_PAGE_ZERO_OQPSK_2450_BPSK_868_915) {
gc_tx_offset = 0x03;
} else {
gc_tx_offset = 0x02;
}
reg = rf2xx_iface_reg_read(dev, RF2XX_RF_CTRL_0_REG)
& ~RF2XX_GC_TX_OFFS_MASK;
rf2xx_iface_reg_write(dev, RF2XX_RF_CTRL_0_REG, reg | gc_tx_offset);
return 0;
}
static int rf2xx_cca(const struct device *dev)
{
ARG_UNUSED(dev);
LOG_DBG("CCA");
return 0;
}
static int rf2xx_set_channel(const struct device *dev, uint16_t channel)
{
struct rf2xx_context *ctx = dev->data;
uint8_t reg;
LOG_DBG("Set Channel %d", channel);
if (ctx->trx_model == RF2XX_TRX_MODEL_212) {
if ((ctx->cc_page == IEEE802154_ATTR_PHY_CHANNEL_PAGE_ZERO_OQPSK_2450_BPSK_868_915
|| ctx->cc_page == IEEE802154_ATTR_PHY_CHANNEL_PAGE_TWO_OQPSK_868_915)
&& channel > 10) {
LOG_ERR("Unsupported channel %u", channel);
return channel > 26 ? -EINVAL : -ENOTSUP;
}
if (ctx->cc_page == IEEE802154_ATTR_PHY_CHANNEL_PAGE_FIVE_OQPSK_780 &&
channel > 3) {
LOG_ERR("Unsupported channel %u", channel);
return channel > 7 ? -EINVAL : -ENOTSUP;
}
rf2xx_configure_sub_channel(dev, channel);
rf2xx_configure_trx_path(dev);
rf2xx_set_rssi_base(dev, channel);
} else {
/* 2.4G O-QPSK, channel page zero */
if (channel < 11 || channel > 26) {
LOG_ERR("Unsupported channel %u", channel);
return channel < 11 ? -ENOTSUP : -EINVAL;
}
}
reg = rf2xx_iface_reg_read(dev, RF2XX_PHY_CC_CCA_REG) & ~0x1f;
rf2xx_iface_reg_write(dev, RF2XX_PHY_CC_CCA_REG, reg | channel);
return 0;
}
static int rf2xx_set_txpower(const struct device *dev, int16_t dbm)
{
const struct rf2xx_config *conf = dev->config;
struct rf2xx_context *ctx = dev->data;
float min, max, step;
uint8_t reg;
uint8_t idx;
uint8_t val;
LOG_DBG("Try set Power to %d", dbm);
/**
* if table size is equal 1 the code assumes a table was not defined. In
* this case the transceiver PHY_TX_PWR register will be set with value
* zero. This is a safe value for all variants and represents an output
* power above 0 dBm.
*
* Note: This is a special case too which avoid division by zero when
* computing the step variable.
*/
if (conf->tx_pwr_table_size == 1) {
rf2xx_iface_reg_write(dev, RF2XX_PHY_TX_PWR_REG, 0);
return 0;
}
min = conf->tx_pwr_min[1];
if (conf->tx_pwr_min[0] == 0x01) {
min *= -1.0f;
}
max = conf->tx_pwr_max[1];
if (conf->tx_pwr_max[0] == 0x01) {
min *= -1.0f;
}
step = (max - min) / ((float)conf->tx_pwr_table_size - 1.0f);
if (step == 0.0f) {
step = 1.0f;
}
LOG_DBG("Tx-power values: min %f, max %f, step %f, entries %d",
(double)min, (double)max, (double)step, conf->tx_pwr_table_size);
if (dbm < min) {
LOG_INF("TX-power %d dBm below min of %f dBm, using %f dBm",
dbm, (double)min, (double)max);
dbm = min;
} else if (dbm > max) {
LOG_INF("TX-power %d dBm above max of %f dBm, using %f dBm",
dbm, (double)min, (double)max);
dbm = max;
}
idx = abs((int) (((float)(dbm - max) / step)));
LOG_DBG("Tx-power idx: %d", idx);
if (idx >= conf->tx_pwr_table_size) {
idx = conf->tx_pwr_table_size - 1;
}
val = conf->tx_pwr_table[idx];
if (ctx->trx_model != RF2XX_TRX_MODEL_212) {
reg = rf2xx_iface_reg_read(dev, RF2XX_PHY_TX_PWR_REG) & 0xf0;
val = reg + (val & 0x0f);
}
LOG_DBG("Tx-power normalized: %d dBm, PHY_TX_PWR 0x%02x, idx %d",
dbm, val, idx);
rf2xx_iface_reg_write(dev, RF2XX_PHY_TX_PWR_REG, val);
return 0;
}
static int rf2xx_set_ieee_addr(const struct device *dev, bool set,
const uint8_t *ieee_addr)
{
const uint8_t *ptr_to_reg = ieee_addr;
LOG_DBG("IEEE address %02x:%02x:%02x:%02x:%02x:%02x:%02x:%02x",
ieee_addr[7], ieee_addr[6], ieee_addr[5], ieee_addr[4],
ieee_addr[3], ieee_addr[2], ieee_addr[1], ieee_addr[0]);
if (set) {
for (uint8_t i = 0; i < 8; i++, ptr_to_reg++) {
rf2xx_iface_reg_write(dev, (RF2XX_IEEE_ADDR_0_REG + i),
*ptr_to_reg);
}
} else {
for (uint8_t i = 0; i < 8; i++) {
rf2xx_iface_reg_write(dev, (RF2XX_IEEE_ADDR_0_REG + i),
0);
}
}
return 0;
}
static int rf2xx_set_short_addr(const struct device *dev, bool set,
uint16_t short_addr)
{
uint8_t short_addr_le[2] = { 0xFF, 0xFF };
if (set) {
sys_put_le16(short_addr, short_addr_le);
}
rf2xx_iface_reg_write(dev, RF2XX_SHORT_ADDR_0_REG, short_addr_le[0]);
rf2xx_iface_reg_write(dev, RF2XX_SHORT_ADDR_1_REG, short_addr_le[1]);
rf2xx_iface_reg_write(dev, RF2XX_CSMA_SEED_0_REG,
short_addr_le[0] + short_addr_le[1]);
LOG_DBG("Short Address: 0x%02X%02X", short_addr_le[1],
short_addr_le[0]);
return 0;
}
static int rf2xx_set_pan_id(const struct device *dev, bool set,
uint16_t pan_id)
{
uint8_t pan_id_le[2] = { 0xFF, 0xFF };
if (set) {
sys_put_le16(pan_id, pan_id_le);
}
rf2xx_iface_reg_write(dev, RF2XX_PAN_ID_0_REG, pan_id_le[0]);
rf2xx_iface_reg_write(dev, RF2XX_PAN_ID_1_REG, pan_id_le[1]);
LOG_DBG("Pan Id: 0x%02X%02X", pan_id_le[1], pan_id_le[0]);
return 0;
}
static int rf2xx_filter(const struct device *dev,
bool set, enum ieee802154_filter_type type,
const struct ieee802154_filter *filter)
{
LOG_DBG("Applying filter %u", type);
if (type == IEEE802154_FILTER_TYPE_IEEE_ADDR) {
return rf2xx_set_ieee_addr(dev, set, filter->ieee_addr);
} else if (type == IEEE802154_FILTER_TYPE_SHORT_ADDR) {
return rf2xx_set_short_addr(dev, set, filter->short_addr);
} else if (type == IEEE802154_FILTER_TYPE_PAN_ID) {
return rf2xx_set_pan_id(dev, set, filter->pan_id);
}
return -ENOTSUP;
}
#if defined(CONFIG_NET_L2_OPENTHREAD)
static void rf2xx_handle_ack(struct rf2xx_context *ctx, struct net_buf *frag)
{
if ((frag->data[0] & RF2XX_FRAME_CTRL_ACK_REQUEST_BIT) == 0) {
return;
}
rf2xx_ack_psdu[0] = RF2XX_ACK_FRAME_TYPE;
rf2xx_ack_psdu[2] = frag->data[2];
if (ctx->trx_trac == RF2XX_TRX_PHY_STATE_TRAC_SUCCESS_DATA_PENDING) {
rf2xx_ack_psdu[0] |= RF2XX_ACK_FRAME_PENDING_BIT;
}
net_pkt_cursor_init(&rf2xx_ack_pkt);
if (ieee802154_handle_ack(ctx->iface, &rf2xx_ack_pkt) != NET_OK) {
LOG_INF("ACK packet not handled.");
}
}
#else
#define rf2xx_handle_ack(...)
#endif
static int rf2xx_tx(const struct device *dev,
enum ieee802154_tx_mode mode,
struct net_pkt *pkt,
struct net_buf *frag)
{
ARG_UNUSED(pkt);
struct rf2xx_context *ctx = dev->data;
int response = 0;
LOG_DBG("TX");
if (ctx->tx_mode != mode) {
switch (mode) {
case IEEE802154_TX_MODE_DIRECT:
/* skip retries & csma/ca algorithm */
rf2xx_iface_reg_write(dev, RF2XX_XAH_CTRL_0_REG, 0x0E);
break;
case IEEE802154_TX_MODE_CSMA_CA:
/* backoff maxBE = 5, minBE = 3 */
rf2xx_iface_reg_write(dev, RF2XX_CSMA_BE_REG, 0x53);
/* max frame retries = 3, csma/ca retries = 4 */
rf2xx_iface_reg_write(dev, RF2XX_XAH_CTRL_0_REG, 0x38);
break;
case IEEE802154_TX_MODE_CCA:
/* backoff period = 0 */
rf2xx_iface_reg_write(dev, RF2XX_CSMA_BE_REG, 0x00);
/* no frame retries & no csma/ca retries */
rf2xx_iface_reg_write(dev, RF2XX_XAH_CTRL_0_REG, 0x00);
break;
case IEEE802154_TX_MODE_TXTIME:
case IEEE802154_TX_MODE_TXTIME_CCA:
default:
NET_ERR("TX mode %d not supported", mode);
return -ENOTSUP;
}
ctx->tx_mode = mode;
}
rf2xx_trx_set_tx_state(dev);
rf2xx_iface_reg_read(dev, RF2XX_IRQ_STATUS_REG);
k_sem_reset(&ctx->trx_tx_sync);
rf2xx_iface_frame_write(dev, frag->data, frag->len);
rf2xx_iface_phy_tx_start(dev);
k_sem_take(&ctx->trx_tx_sync, K_FOREVER);
switch (ctx->trx_trac) {
/* Channel is still busy after attempting MAX_CSMA_RETRIES of
* CSMA-CA
*/
case RF2XX_TRX_PHY_STATE_TRAC_CHANNEL_ACCESS_FAILED:
response = -EBUSY;
break;
/* No acknowledgment frames were received during all retry
* attempts
*/
case RF2XX_TRX_PHY_STATE_TRAC_NO_ACK:
response = -EAGAIN;
break;
/* Transaction not yet finished */
case RF2XX_TRX_PHY_STATE_TRAC_INVALID:
response = -EINTR;
break;
/* RF2XX_TRX_PHY_STATE_TRAC_SUCCESS:
* The transaction was responded to by a valid ACK, or, if no
* ACK is requested, after a successful frame transmission.
*
* RF2XX_TRX_PHY_STATE_TRAC_SUCCESS_DATA_PENDING:
* Equivalent to SUCCESS and indicating that the Frame
* Pending bit (see Section 8.1.2.2) of the received
* acknowledgment frame was set.
*/
default:
rf2xx_handle_ack(ctx, frag);
break;
}
return response;
}
static int rf2xx_start(const struct device *dev)
{
const struct rf2xx_config *conf = dev->config;
LOG_DBG("Start");
rf2xx_trx_set_state(dev, RF2XX_TRX_PHY_STATE_CMD_TRX_OFF);
rf2xx_iface_reg_read(dev, RF2XX_IRQ_STATUS_REG);
gpio_pin_interrupt_configure_dt(&conf->irq_gpio,
GPIO_INT_EDGE_TO_ACTIVE);
rf2xx_trx_set_rx_state(dev);
return 0;
}
static int rf2xx_stop(const struct device *dev)
{
const struct rf2xx_config *conf = dev->config;
LOG_DBG("Stop");
gpio_pin_interrupt_configure_dt(&conf->irq_gpio, GPIO_INT_DISABLE);
rf2xx_trx_set_state(dev, RF2XX_TRX_PHY_STATE_CMD_TRX_OFF);
rf2xx_iface_reg_read(dev, RF2XX_IRQ_STATUS_REG);
return 0;
}
static int rf2xx_pan_coord_set(const struct device *dev, bool pan_coordinator)
{
uint8_t reg;
if (pan_coordinator) {
reg = rf2xx_iface_reg_read(dev, RF2XX_CSMA_SEED_1_REG);
reg |= (1 << RF2XX_AACK_I_AM_COORD);
rf2xx_iface_reg_write(dev, RF2XX_CSMA_SEED_1_REG, reg);
} else {
reg = rf2xx_iface_reg_read(dev, RF2XX_CSMA_SEED_1_REG);
reg &= ~(1 << RF2XX_AACK_I_AM_COORD);
rf2xx_iface_reg_write(dev, RF2XX_CSMA_SEED_1_REG, reg);
}
return 0;
}
static int rf2xx_promiscuous_set(const struct device *dev, bool promiscuous)
{
struct rf2xx_context *ctx = dev->data;
uint8_t reg;
ctx->promiscuous = promiscuous;
if (promiscuous) {
reg = rf2xx_iface_reg_read(dev, RF2XX_XAH_CTRL_1_REG);
reg |= (1 << RF2XX_AACK_PROM_MODE);
rf2xx_iface_reg_write(dev, RF2XX_XAH_CTRL_1_REG, reg);
reg = rf2xx_iface_reg_read(dev, RF2XX_CSMA_SEED_1_REG);
reg |= (1 << RF2XX_AACK_DIS_ACK);
rf2xx_iface_reg_write(dev, RF2XX_CSMA_SEED_1_REG, reg);
} else {
reg = rf2xx_iface_reg_read(dev, RF2XX_XAH_CTRL_1_REG);
reg &= ~(1 << RF2XX_AACK_PROM_MODE);
rf2xx_iface_reg_write(dev, RF2XX_XAH_CTRL_1_REG, reg);
reg = rf2xx_iface_reg_read(dev, RF2XX_CSMA_SEED_1_REG);
reg &= ~(1 << RF2XX_AACK_DIS_ACK);
rf2xx_iface_reg_write(dev, RF2XX_CSMA_SEED_1_REG, reg);
}
return 0;
}
int rf2xx_configure(const struct device *dev,
enum ieee802154_config_type type,
const struct ieee802154_config *config)
{
int ret = -EINVAL;
LOG_DBG("Configure %d", type);
switch (type) {
case IEEE802154_CONFIG_AUTO_ACK_FPB:
case IEEE802154_CONFIG_ACK_FPB:
break;
case IEEE802154_CONFIG_PAN_COORDINATOR:
ret = rf2xx_pan_coord_set(dev, config->pan_coordinator);
break;
case IEEE802154_CONFIG_PROMISCUOUS:
ret = rf2xx_promiscuous_set(dev, config->promiscuous);
break;
case IEEE802154_CONFIG_EVENT_HANDLER:
default:
break;
}
return ret;
}
static int rf2xx_attr_get(const struct device *dev, enum ieee802154_attr attr,
struct ieee802154_attr_value *value)
{
struct rf2xx_context *ctx = dev->data;
switch (attr) {
case IEEE802154_ATTR_PHY_SUPPORTED_CHANNEL_PAGES:
value->phy_supported_channel_pages = ctx->cc_page;
return 0;
case IEEE802154_ATTR_PHY_SUPPORTED_CHANNEL_RANGES:
value->phy_supported_channels = &ctx->cc_channels;
return 0;
default:
return -ENOENT;
}
}
static int power_on_and_setup(const struct device *dev)
{
const struct rf2xx_config *conf = dev->config;
struct rf2xx_context *ctx = dev->data;
uint8_t config;
rf2xx_iface_phy_rst(dev);
/* Sync transceiver state */
do {
rf2xx_iface_reg_write(dev, RF2XX_TRX_STATE_REG,
RF2XX_TRX_PHY_STATE_CMD_TRX_OFF);
} while (RF2XX_TRX_PHY_STATUS_TRX_OFF !=
(rf2xx_iface_reg_read(dev, RF2XX_TRX_STATUS_REG) &
RF2XX_TRX_PHY_STATUS_MASK));
/* get device identification */
ctx->trx_model = rf2xx_iface_reg_read(dev, RF2XX_PART_NUM_REG);
ctx->trx_version = rf2xx_iface_reg_read(dev, RF2XX_VERSION_NUM_REG);
/**
* Valid transceiver are:
* 231-Rev-A (Version 0x02)
* 232-Rev-A (Version 0x02)
* 233-Rev-A (Version 0x01) (Warning)
* 233-Rev-B (Version 0x02)
*/
if (ctx->trx_model <= RF2XX_TRX_MODEL_230) {
LOG_DBG("Invalid or not supported transceiver");
return -ENODEV;
}
if (ctx->trx_model == RF2XX_TRX_MODEL_233 && ctx->trx_version == 0x01) {
LOG_DBG("Transceiver is old and unstable release");
}
/* Set RSSI base */
if (ctx->trx_model == RF2XX_TRX_MODEL_212) {
ctx->trx_rssi_base = -100;
} else if (ctx->trx_model == RF2XX_TRX_MODEL_233) {
ctx->trx_rssi_base = -94;
} else if (ctx->trx_model == RF2XX_TRX_MODEL_231) {
ctx->trx_rssi_base = -91;
} else {
ctx->trx_rssi_base = -90;
}
/* Disable All Features of TRX_CTRL_0 */
config = 0;
rf2xx_iface_reg_write(dev, RF2XX_TRX_CTRL_0_REG, config);
/* Configure PHY behaviour */
config = (1 << RF2XX_TX_AUTO_CRC_ON) |
(3 << RF2XX_SPI_CMD_MODE) |
(1 << RF2XX_IRQ_MASK_MODE);
rf2xx_iface_reg_write(dev, RF2XX_TRX_CTRL_1_REG, config);
config = (1 << RF2XX_RX_SAFE_MODE);
if (ctx->trx_model != RF2XX_TRX_MODEL_232) {
config |= (1 << RF2XX_OQPSK_SCRAM_EN);
}
rf2xx_iface_reg_write(dev, RF2XX_TRX_CTRL_2_REG, config);
if (ctx->trx_model == RF2XX_TRX_MODEL_212) {
rf2xx_configure_trx_path(dev);
rf2xx_iface_reg_write(dev, RF2XX_CC_CTRL_1_REG, 0);
}
ctx->tx_mode = IEEE802154_TX_MODE_CSMA_CA;
ctx->promiscuous = false;
/* Configure INT behaviour */
config = (1 << RF2XX_RX_START) |
(1 << RF2XX_TRX_END);
rf2xx_iface_reg_write(dev, RF2XX_IRQ_MASK_REG, config);
gpio_init_callback(&ctx->irq_cb, trx_isr_handler,
BIT(conf->irq_gpio.pin));
if (gpio_add_callback(conf->irq_gpio.port, &ctx->irq_cb) < 0) {
LOG_ERR("Could not set IRQ callback.");
return -ENXIO;
}
return 0;
}
static inline int configure_gpios(const struct device *dev)
{
const struct rf2xx_config *conf = dev->config;
/* Chip IRQ line */
if (!gpio_is_ready_dt(&conf->irq_gpio)) {
LOG_ERR("IRQ GPIO device not ready");
return -ENODEV;
}
gpio_pin_configure_dt(&conf->irq_gpio, GPIO_INPUT);
gpio_pin_interrupt_configure_dt(&conf->irq_gpio,
GPIO_INT_EDGE_TO_ACTIVE);
/* Chip RESET line */
if (!gpio_is_ready_dt(&conf->reset_gpio)) {
LOG_ERR("RESET GPIO device not ready");
return -ENODEV;
}
gpio_pin_configure_dt(&conf->reset_gpio, GPIO_OUTPUT_INACTIVE);
/* Chip SLPTR line */
if (!gpio_is_ready_dt(&conf->slptr_gpio)) {
LOG_ERR("SLPTR GPIO device not ready");
return -ENODEV;
}
gpio_pin_configure_dt(&conf->slptr_gpio, GPIO_OUTPUT_INACTIVE);
/* Chip DIG2 line (Optional feature) */
if (conf->dig2_gpio.port != NULL) {
if (!gpio_is_ready_dt(&conf->dig2_gpio)) {
LOG_ERR("DIG2 GPIO device not ready");
return -ENODEV;
}
LOG_INF("Optional instance of %s device activated",
conf->dig2_gpio.port->name);
gpio_pin_configure_dt(&conf->dig2_gpio, GPIO_INPUT);
gpio_pin_interrupt_configure_dt(&conf->dig2_gpio,
GPIO_INT_EDGE_TO_ACTIVE);
}
/* Chip CLKM line (Optional feature) */
if (conf->clkm_gpio.port != NULL) {
if (!gpio_is_ready_dt(&conf->clkm_gpio)) {
LOG_ERR("CLKM GPIO device not ready");
return -ENODEV;
}
LOG_INF("Optional instance of %s device activated",
conf->clkm_gpio.port->name);
gpio_pin_configure_dt(&conf->clkm_gpio, GPIO_INPUT);
}
return 0;
}
static inline int configure_spi(const struct device *dev)
{
const struct rf2xx_config *conf = dev->config;
if (!spi_is_ready_dt(&conf->spi)) {
LOG_ERR("SPI bus %s is not ready",
conf->spi.bus->name);
return -ENODEV;
}
return 0;
}
static int rf2xx_init(const struct device *dev)
{
struct rf2xx_context *ctx = dev->data;
const struct rf2xx_config *conf = dev->config;
char thread_name[20];
LOG_DBG("\nInitialize RF2XX Transceiver\n");
ctx->dev = dev;
k_sem_init(&ctx->trx_tx_sync, 0, 1);
k_sem_init(&ctx->trx_isr_lock, 0, 1);
if (configure_gpios(dev) != 0) {
LOG_ERR("Configuring GPIOS failed");
return -EIO;
}
if (configure_spi(dev) != 0) {
LOG_ERR("Configuring SPI failed");
return -EIO;
}
LOG_DBG("GPIO and SPI configured");
if (power_on_and_setup(dev) != 0) {
LOG_ERR("Configuring RF2XX failed");
return -EIO;
}
LOG_DBG("RADIO configured");
k_thread_create(&ctx->trx_thread,
ctx->trx_stack,
CONFIG_IEEE802154_RF2XX_RX_STACK_SIZE,
rf2xx_thread_main,
ctx, NULL, NULL,
K_PRIO_COOP(2), 0, K_NO_WAIT);
snprintk(thread_name, sizeof(thread_name),
"rf2xx_trx [%d]", conf->inst);
k_thread_name_set(&ctx->trx_thread, thread_name);
LOG_DBG("Thread OK");
return 0;
}
static void rf2xx_iface_init(struct net_if *iface)
{
const struct device *dev = net_if_get_device(iface);
struct rf2xx_context *ctx = dev->data;
uint8_t *mac = get_mac(dev);
net_if_set_link_addr(iface, mac, 8, NET_LINK_IEEE802154);
ctx->iface = iface;
if (ctx->trx_model == RF2XX_TRX_MODEL_212) {
if (ctx->cc_page == IEEE802154_ATTR_PHY_CHANNEL_PAGE_ZERO_OQPSK_2450_BPSK_868_915 ||
ctx->cc_page == IEEE802154_ATTR_PHY_CHANNEL_PAGE_TWO_OQPSK_868_915) {
ctx->cc_range.from_channel = 0U;
ctx->cc_range.to_channel = 10U;
} else if (ctx->cc_page == IEEE802154_ATTR_PHY_CHANNEL_PAGE_FIVE_OQPSK_780) {
ctx->cc_range.from_channel = 0U;
ctx->cc_range.to_channel = 3U;
} else {
__ASSERT(false, "Unsupported channel page %u.", ctx->cc_page);
}
} else {
__ASSERT(ctx->cc_page ==
IEEE802154_ATTR_PHY_CHANNEL_PAGE_ZERO_OQPSK_2450_BPSK_868_915,
"Unsupported channel page %u.", ctx->cc_page);
ctx->cc_range.from_channel = 11U;
ctx->cc_range.to_channel = 26U;
}
ieee802154_init(iface);
}
static const struct ieee802154_radio_api rf2xx_radio_api = {
.iface_api.init = rf2xx_iface_init,
.get_capabilities = rf2xx_get_capabilities,
.cca = rf2xx_cca,
.set_channel = rf2xx_set_channel,
.filter = rf2xx_filter,
.set_txpower = rf2xx_set_txpower,
.tx = rf2xx_tx,
.start = rf2xx_start,
.stop = rf2xx_stop,
.configure = rf2xx_configure,
.attr_get = rf2xx_attr_get,
};
#if !defined(CONFIG_IEEE802154_RAW_MODE)
#if defined(CONFIG_NET_L2_IEEE802154)
#define L2 IEEE802154_L2
#define L2_CTX_TYPE NET_L2_GET_CTX_TYPE(IEEE802154_L2)
#define MTU RF2XX_MAX_PSDU_LENGTH
#elif defined(CONFIG_NET_L2_OPENTHREAD)
#define L2 OPENTHREAD_L2
#define L2_CTX_TYPE NET_L2_GET_CTX_TYPE(OPENTHREAD_L2)
#define MTU RF2XX_OT_PSDU_LENGTH
#endif
#endif /* CONFIG_IEEE802154_RAW_MODE */
#define DRV_INST_LOCAL_MAC_ADDRESS(n) \
UTIL_AND(DT_INST_NODE_HAS_PROP(n, local_mac_address), \
UTIL_AND(DT_INST_PROP_LEN(n, local_mac_address) == 8, \
DT_INST_PROP(n, local_mac_address)))
#define IEEE802154_RF2XX_DEVICE_CONFIG(n) \
BUILD_ASSERT(DT_INST_PROP_LEN(n, tx_pwr_min) == 2, \
"rf2xx: Error TX-PWR-MIN len is different of two"); \
BUILD_ASSERT(DT_INST_PROP_LEN(n, tx_pwr_max) == 2, \
"rf2xx: Error TX-PWR-MAX len is different of two"); \
BUILD_ASSERT(DT_INST_PROP_LEN(n, tx_pwr_table) != 0, \
"rf2xx: Error TX-PWR-TABLE len must be greater than zero"); \
static const uint8_t rf2xx_pwr_table_##n[] = \
DT_INST_PROP_OR(n, tx_pwr_table, 0); \
static const struct rf2xx_config rf2xx_ctx_config_##n = { \
.inst = n, \
.has_mac = DT_INST_NODE_HAS_PROP(n, local_mac_address), \
.irq_gpio = GPIO_DT_SPEC_INST_GET(n, irq_gpios), \
.reset_gpio = GPIO_DT_SPEC_INST_GET(n, reset_gpios), \
.slptr_gpio = GPIO_DT_SPEC_INST_GET(n, slptr_gpios), \
.dig2_gpio = GPIO_DT_SPEC_INST_GET_OR(n, dig2_gpios, {}), \
.clkm_gpio = GPIO_DT_SPEC_INST_GET_OR(n, clkm_gpios, {}), \
.spi = SPI_DT_SPEC_INST_GET(n, SPI_WORD_SET(8) | \
SPI_TRANSFER_MSB, 0), \
\
.tx_pwr_min = DT_INST_PROP_OR(n, tx_pwr_min, 0), \
.tx_pwr_max = DT_INST_PROP_OR(n, tx_pwr_max, 0), \
.tx_pwr_table = rf2xx_pwr_table_##n, \
.tx_pwr_table_size = DT_INST_PROP_LEN(n, tx_pwr_table), \
}
#define IEEE802154_RF2XX_DEVICE_DATA(n) \
static struct rf2xx_context rf2xx_ctx_data_##n = { \
.mac_addr = { DRV_INST_LOCAL_MAC_ADDRESS(n) }, \
.cc_page = BIT(DT_INST_ENUM_IDX_OR(n, channel_page, 0)),\
.cc_channels = { \
.ranges = &rf2xx_ctx_data_##n.cc_range, \
.num_ranges = 1U, \
} \
}
#define IEEE802154_RF2XX_RAW_DEVICE_INIT(n) \
DEVICE_DT_INST_DEFINE( \
n, \
&rf2xx_init, \
NULL, \
&rf2xx_ctx_data_##n, \
&rf2xx_ctx_config_##n, \
POST_KERNEL, \
CONFIG_IEEE802154_RF2XX_INIT_PRIO, \
&rf2xx_radio_api)
#define IEEE802154_RF2XX_NET_DEVICE_INIT(n) \
NET_DEVICE_DT_INST_DEFINE( \
n, \
&rf2xx_init, \
NULL, \
&rf2xx_ctx_data_##n, \
&rf2xx_ctx_config_##n, \
CONFIG_IEEE802154_RF2XX_INIT_PRIO, \
&rf2xx_radio_api, \
L2, \
L2_CTX_TYPE, \
MTU)
#define IEEE802154_RF2XX_INIT(inst) \
IEEE802154_RF2XX_DEVICE_CONFIG(inst); \
IEEE802154_RF2XX_DEVICE_DATA(inst); \
\
COND_CODE_1(CONFIG_IEEE802154_RAW_MODE, \
(IEEE802154_RF2XX_RAW_DEVICE_INIT(inst);), \
(IEEE802154_RF2XX_NET_DEVICE_INIT(inst);))
DT_INST_FOREACH_STATUS_OKAY(IEEE802154_RF2XX_INIT)
``` | /content/code_sandbox/drivers/ieee802154/ieee802154_rf2xx.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 10,461 |
```objective-c
/*
*
*/
#ifndef ZEPHYR_DRIVERS_IEEE802154_IEEE802154_CC1200_RF_H_
#define ZEPHYR_DRIVERS_IEEE802154_IEEE802154_CC1200_RF_H_
#include <zephyr/drivers/ieee802154/cc1200.h>
#define CC1200_RF_NON_EXT_SPACE_REGS 42
#define CC1200_RF_EXT_SPACE_REGS 58
/* About PKTCFGn from Kconfig:
* CONFIG_IEEE802154_CC1200_PKTCFG0 LENGTH_VAR_1
* CONFIG_IEEE802154_CC1200_PKTCFG1 (APPEND_STATUS | CRC_FFFF | ADDR_NO_CHK)
* We do not enable 802.15.4g mode yet:
* CONFIG_IEEE802154_CC1200_PKTCFG2 (PKT_FORMAT_NORMAL_MODE | CCA_ALWAYS_CLEAR)
**/
#ifdef CONFIG_IEEE802154_CC1200_RF_PRESET
#if defined(CONFIG_IEEE802154_CC1200_RF_SET_0)
#define IEEE802154_CC1200_CHANNEL_LIMIT 33
const struct cc1200_rf_registers_set cc1200_rf_settings = {
.chan_center_freq0 = 863125,
.channel_spacing = 2000, /* 200 KHz */
.registers = {
0x6F, /* SYNC3 */
0x4E,
0x90,
0x4E,
0xE5,
0x23,
0x47,
0x0B,
0x56,
0x19, /* 0x14 */
0xBA,
0xC8,
0x84,
0x42,
0x05,
0x94,
0x7A,
0xE1,
0x27,
CONFIG_IEEE802154_CC1200_CCA_THRESHOLD,
CONFIG_IEEE802154_CC1200_RSSI_OFFSET,
0xB1,
0x20,
0x11,
0x90,
0x00,
0x00,
CONFIG_IEEE802154_CC1200_SETTLING_CFG,
0x12,
0x08,
0x21,
0x00,
0x00,
0x00,
CONFIG_IEEE802154_CC1200_PKTCFG2,
CONFIG_IEEE802154_CC1200_PKTCFG1,
CONFIG_IEEE802154_CC1200_PKTCFG0,
CONFIG_IEEE802154_CC1200_RFEND_CFG1,
CONFIG_IEEE802154_CC1200_RFEND_CFG0,
0x7F,
0x56,
0x0F, /* ASK_CFG */
0x18, /* IF_MIX_CFG */
0x20,
0x03,
0x00,
0x00,
0x02,
0x01,
0x00,
0x00,
0x00,
0x00,
0x00,
0x56,
0xCC,
0xCC,
0x02,
0xEE,
0x10,
0x04,
0x50,
0x00,
0x20,
0x40,
0x0E,
0x28,
0x03,
0x00,
0x33,
0xF7,
0x0F,
0x00,
0x00,
0x6E,
0x1C,
0xAC,
0x14,
0x00,
0x00,
0x00,
0xB5,
0x00,
0x02,
0x00,
0x00,
0x10,
0x00,
0x00,
0x05,
0x01,
0x01,
0x0E,
0xA0,
0x03,
0x04,
0x03,
0x00,
0x00,
0x00, /* PA_CFG3 */
}
};
#elif defined(CONFIG_IEEE802154_CC1200_RF_SET_1)
#define IEEE802154_CC1200_CHANNEL_LIMIT 38
const struct cc1200_rf_registers_set cc1200_rf_settings = {
.chan_center_freq0 = 920600,
.channel_spacing = 2000, /* 200 KHz */
.registers = {
0x6F, /* SYNC3 */
0x4E,
0x90,
0x4E,
0xE5,
0x23,
0x47,
0x0B,
0x56,
0x14,
0xBA,
0xC8,
0x84,
0x42,
0x05,
0x94,
0x7A,
0xE1,
0x27,
CONFIG_IEEE802154_CC1200_CCA_THRESHOLD,
CONFIG_IEEE802154_CC1200_RSSI_OFFSET,
0xB1,
0x20,
0x11,
0x90,
0x00,
0x00,
CONFIG_IEEE802154_CC1200_SETTLING_CFG,
0x12,
0x08,
0x21,
0x00,
0x00,
0x00,
CONFIG_IEEE802154_CC1200_PKTCFG2,
CONFIG_IEEE802154_CC1200_PKTCFG1,
CONFIG_IEEE802154_CC1200_PKTCFG0,
CONFIG_IEEE802154_CC1200_RFEND_CFG1,
CONFIG_IEEE802154_CC1200_RFEND_CFG0
0x7F,
0x56,
0x0F, /* ASK_CFG */
0x18, /* IF_MIX_CFG */
0x20,
0x03,
0x00,
0x00,
0x02,
0x01,
0x00,
0x00,
0x00,
0x00,
0x00,
0x5C,
0x0F,
0x5C,
0x02,
0xEE,
0x10,
0x04,
0x55,
0x00,
0x20,
0x40,
0x0E,
0x28,
0x03,
0x00,
0x33,
0xFF,
0x17,
0x00,
0x00,
0x6E,
0x1C,
0xAC,
0x14,
0x00,
0x00,
0x00,
0xB5,
0x00,
0x02,
0x00,
0x00,
0x10,
0x00,
0x00,
0x05,
0x01,
0x01,
0x0E,
0xA0,
0x03,
0x04,
0x03,
0x00,
0x00,
0x00, /* PA_CFG3 */
}
};
#elif defined(CONFIG_IEEE802154_CC1200_RF_SET_2)
#define IEEE802154_CC1200_CHANNEL_LIMIT 14
const struct cc1200_rf_registers_set cc1200_rf_settings = {
.chan_center_freq0 = 433164,
.channel_spacing = 2000, /* 200 KHz */
.registers = {
0x6F, /* SYNC3 */
0x4E,
0x90,
0x4E,
0xE5,
0x23,
0x47,
0x0B,
0x56,
0x14,
0xBA,
0xC8,
0x84,
0x42,
0x05,
0x94,
0x7A,
0xE1,
0x27,
CONFIG_IEEE802154_CC1200_CCA_THRESHOLD,
CONFIG_IEEE802154_CC1200_RSSI_OFFSET,
0xB1,
0x20,
0x11,
0x90,
0x00,
0x00,
CONFIG_IEEE802154_CC1200_SETTLING_CFG,
0x14,
0x08,
0x21,
0x00,
0x00,
0x00,
CONFIG_IEEE802154_CC1200_PKTCFG2,
CONFIG_IEEE802154_CC1200_PKTCFG1,
CONFIG_IEEE802154_CC1200_PKTCFG0,
CONFIG_IEEE802154_CC1200_RFEND_CFG1,
CONFIG_IEEE802154_CC1200_RFEND_CFG0,
0x7F,
0x56,
0x0F, /* ASK_CFG */
0x18, /* IF_MIX_CFG */
0x20,
0x03,
0x00,
0x00,
0x02,
0x01,
0x00,
0x00,
0x00,
0x00,
0x00,
0x56,
0xCC,
0xCC,
0x02,
0xEE,
0x10,
0x04,
0x50,
0x00,
0x20,
0x40,
0x0E,
0x28,
0x03,
0x00,
0x33,
0xF7,
0x0F,
0x00,
0x00,
0x6E,
0x1C,
0xAC,
0x14,
0x00,
0x00,
0x00,
0xB5,
0x00,
0x02,
0x00,
0x00,
0x10,
0x00,
0x00,
0x05,
0x01,
0x01,
0x0E,
0xA0,
0x03,
0x04,
0x03,
0x00,
0x00,
0x00, /* PA_CFG3 */
}
};
#endif /* CONFIG_IEEE802154_CC1200_RF_SET_n */
#endif /* CONFIG_IEEE802154_CC1200_RF_PRESET */
#endif /* ZEPHYR_DRIVERS_IEEE802154_IEEE802154_CC1200_RF_H_ */
``` | /content/code_sandbox/drivers/ieee802154/ieee802154_cc1200_rf.h | objective-c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 2,565 |
```unknown
# TI CC2520 configuration options
menuconfig IEEE802154_CC2520
bool "TI CC2520 Driver support"
default y
depends on DT_HAS_TI_CC2520_ENABLED
if IEEE802154_CC2520
config IEEE802154_CC2520_RX_STACK_SIZE
int "Driver's internal RX thread stack size"
default 800
help
This option sets the driver's stack size for its internal RX thread.
The default value should be sufficient, but in case it proves to be
a too little one, this option makes it easy to play with the size.
config IEEE802154_CC2520_INIT_PRIO
int "CC2520 initialization priority"
default 80
help
Set the initialization priority number. Do not mess with it unless
you know what you are doing. Beware cc2520 requires gpio and spi to
be ready first (and sometime gpio should be the very first as spi
might need it too). And of course it has to start before the net stack.
config IEEE802154_CC2520_RANDOM_MAC
bool "Random MAC address"
default y
help
Generate a random MAC address dynamically.
if ! IEEE802154_CC2520_RANDOM_MAC
config IEEE802154_CC2520_MAC4
hex "MAC Address Byte 4"
default 0
range 0 0xff
help
This is the byte 4 of the MAC address.
config IEEE802154_CC2520_MAC5
hex "MAC Address Byte 5"
default 0
range 0 0xff
help
This is the byte 5 of the MAC address.
config IEEE802154_CC2520_MAC6
hex "MAC Address Byte 6"
default 0
range 0 0xff
help
This is the byte 6 of the MAC address.
config IEEE802154_CC2520_MAC7
hex "MAC Address Byte 7"
default 0
range 0 0xff
help
This is the byte 7 of the MAC address.
endif # IEEE802154_CC2520_RANDOM_MAC
config IEEE802154_CC2520_CRYPTO
bool "Hardware crypto helper on cc2520"
default y
depends on NET_L2_IEEE802154_SECURITY
help
This option will expose the hardware AES encryption from CC2520.
Such feature should not be used for anything but 802.15.4 security.
The crypto device exposed will only support synchronous CCM operation.
config IEEE802154_CC2520_CRYPTO_INIT_PRIO
int "TI CC2520 crypto device initialization priority"
default 81
depends on IEEE802154_CC2520_CRYPTO
help
Set the initialization priority number. Do not mess with it unless
you know what you are doing. It should be initialized after CC2520
as it shares the same runtime context.
endif # IEEE802154_CC2520
``` | /content/code_sandbox/drivers/ieee802154/Kconfig.cc2520 | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 613 |
```objective-c
/*
*
*/
#ifndef ZEPHYR_DRIVERS_IEEE802154_IEEE802154_B91_H_
#define ZEPHYR_DRIVERS_IEEE802154_IEEE802154_B91_H_
/* Timeouts */
#define B91_TX_WAIT_TIME_MS (10)
#define B91_ACK_WAIT_TIME_MS (10)
/* Received data parsing */
#define B91_PAYLOAD_OFFSET (5)
#define B91_PAYLOAD_MIN (5)
#define B91_PAYLOAD_MAX (127)
#define B91_FRAME_TYPE_OFFSET (0)
#define B91_FRAME_TYPE_MASK (0x07)
#define B91_DEST_ADDR_TYPE_OFFSET (1)
#define B91_DEST_ADDR_TYPE_MASK (0x0c)
#define B91_DEST_ADDR_TYPE_SHORT (8)
#define B91_DEST_ADDR_TYPE_IEEE (0x0c)
#define B91_PAN_ID_OFFSET (3)
#define B91_PAN_ID_SIZE (2)
#define B91_DEST_ADDR_OFFSET (5)
#define B91_SHORT_ADDRESS_SIZE (2)
#define B91_IEEE_ADDRESS_SIZE (8)
#define B91_LENGTH_OFFSET (4)
#define B91_RSSI_OFFSET (11)
#define B91_BROADCAST_ADDRESS ((uint8_t [2]) { 0xff, 0xff })
#define B91_ACK_FRAME_LEN (3)
#define B91_ACK_TYPE (2)
#define B91_ACK_REQUEST (1 << 5)
#define B91_DSN_OFFSET (2)
#define B91_FCS_LENGTH (2)
/* Generic */
#define B91_TRX_LENGTH (256)
#define B91_RSSI_TO_LQI_SCALE (3)
#define B91_RSSI_TO_LQI_MIN (-87)
#define B91_CCA_TIME_MAX_US (200)
#define B91_LOGIC_CHANNEL_TO_PHYSICAL(p) (((p) - 10) * 5)
/* TX power lookup table */
#define B91_TX_POWER_MIN (-30)
#define B91_TX_POWER_MAX (9)
static const uint8_t b91_tx_pwr_lt[] = {
RF_POWER_N30dBm, /* -30.0 dBm: -30 */
RF_POWER_N30dBm, /* -30.0 dBm: -29 */
RF_POWER_N30dBm, /* -30.0 dBm: -28 */
RF_POWER_N30dBm, /* -30.0 dBm: -27 */
RF_POWER_N30dBm, /* -30.0 dBm: -26 */
RF_POWER_N23p54dBm, /* -23.5 dBm: -25 */
RF_POWER_N23p54dBm, /* -23.5 dBm: -24 */
RF_POWER_N23p54dBm, /* -23.5 dBm: -23 */
RF_POWER_N23p54dBm, /* -23.5 dBm: -22 */
RF_POWER_N23p54dBm, /* -23.5 dBm: -21 */
RF_POWER_N17p83dBm, /* -17.8 dBm: -20 */
RF_POWER_N17p83dBm, /* -17.8 dBm: -19 */
RF_POWER_N17p83dBm, /* -17.8 dBm: -18 */
RF_POWER_N17p83dBm, /* -17.8 dBm: -17 */
RF_POWER_N17p83dBm, /* -17.8 dBm: -16 */
RF_POWER_N12p06dBm, /* -12.0 dBm: -15 */
RF_POWER_N12p06dBm, /* -12.0 dBm: -14 */
RF_POWER_N12p06dBm, /* -12.0 dBm: -13 */
RF_POWER_N12p06dBm, /* -12.0 dBm: -12 */
RF_POWER_N12p06dBm, /* -12.0 dBm: -11 */
RF_POWER_N8p78dBm, /* -8.7 dBm: -10 */
RF_POWER_N8p78dBm, /* -8.7 dBm: -9 */
RF_POWER_N8p78dBm, /* -8.7 dBm: -8 */
RF_POWER_N6p54dBm, /* -6.5 dBm: -7 */
RF_POWER_N6p54dBm, /* -6.5 dBm: -6 */
RF_POWER_N4p77dBm, /* -4.7 dBm: -5 */
RF_POWER_N4p77dBm, /* -4.7 dBm: -4 */
RF_POWER_N3p37dBm, /* -3.3 dBm: -3 */
RF_POWER_N2p01dBm, /* -2.0 dBm: -2 */
RF_POWER_N1p37dBm, /* -1.3 dBm: -1 */
RF_POWER_P0p01dBm, /* 0.0 dBm: 0 */
RF_POWER_P0p80dBm, /* 0.8 dBm: 1 */
RF_POWER_P2p32dBm, /* 2.3 dBm: 2 */
RF_POWER_P3p25dBm, /* 3.2 dBm: 3 */
RF_POWER_P4p35dBm, /* 4.3 dBm: 4 */
RF_POWER_P5p68dBm, /* 5.6 dBm: 5 */
RF_POWER_P5p68dBm, /* 5.6 dBm: 6 */
RF_POWER_P6p98dBm, /* 6.9 dBm: 7 */
RF_POWER_P8p05dBm, /* 8.0 dBm: 8 */
RF_POWER_P9p11dBm, /* 9.1 dBm: 9 */
};
/* data structure */
struct b91_data {
uint8_t mac_addr[B91_IEEE_ADDRESS_SIZE];
uint8_t rx_buffer[B91_TRX_LENGTH];
uint8_t tx_buffer[B91_TRX_LENGTH];
struct net_if *iface;
struct k_sem tx_wait;
struct k_sem ack_wait;
uint8_t filter_pan_id[B91_PAN_ID_SIZE];
uint8_t filter_short_addr[B91_SHORT_ADDRESS_SIZE];
uint8_t filter_ieee_addr[B91_IEEE_ADDRESS_SIZE];
bool is_started;
bool ack_handler_en;
uint16_t current_channel;
};
#endif
``` | /content/code_sandbox/drivers/ieee802154/ieee802154_b91.h | objective-c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 1,463 |
```unknown
# Nordic Semiconductor nRF5 802.15.4 configuration options
menuconfig IEEE802154_NRF5
bool "nRF52 series IEEE 802.15.4 Driver"
default y
depends on DT_HAS_NORDIC_NRF_IEEE802154_ENABLED
select NRF_802154_RADIO_DRIVER if HAS_HW_NRF_RADIO_IEEE802154
select NRF_802154_SER_HOST if !HAS_HW_NRF_RADIO_IEEE802154
if IEEE802154_NRF5
config IEEE802154_NRF5_RX_STACK_SIZE
int "Driver's internal RX thread stack size"
default 800
help
This option sets the driver's stack size for its internal RX thread.
The default value should be sufficient, but in case it proves to be
a too little one, this option makes it easy to play with the size.
config IEEE802154_NRF5_INIT_PRIO
int "nRF52 IEEE 802.15.4 initialization priority"
default 80
help
Set the initialization priority number. Do not mess with it unless
you know what you are doing.
config IEEE802154_NRF5_EXT_IRQ_MGMT
bool
help
The driver may manage radio IRQs by itself, or use an external
radio IRQ provider. When radio IRQs are managed by an external
provider, the driver shall not configure radio IRQs.
Enable this option when external radio IRQ provider is enabled in
the system. One example of external radio IRQ provider could be
a radio arbiter used in dynamic multiprotocol applications.
config IEEE802154_NRF5_UICR_EUI64_ENABLE
bool "Support usage of EUI64 value stored in UICR registers"
depends on !IEEE802154_VENDOR_OUI_ENABLE
depends on SOC_SERIES_NRF52X || SOC_SERIES_NRF53X
help
This option enables setting custom vendor EUI64 value
stored in User information configuration registers (UICR).
Notice that this disables the default setting of EUI64
value from Factory information configuration registers
(FICR).
if IEEE802154_NRF5_UICR_EUI64_ENABLE
config IEEE802154_NRF5_UICR_EUI64_REG
int "UICR base register for the EUI64 value"
range 0 30 if SOC_SERIES_NRF52X
range 0 190 if SOC_SERIES_NRF53X
default 0
help
Base of the two consecutive registers from the UICR customer
section in which custom EUI64 is stored.
endif # IEEE802154_NRF5_UICR_EUI64_ENABLE
config IEEE802154_NRF5_FCS_IN_LENGTH
bool "Include FCS field in the overall packet length"
default y if IEEE802154_RAW_MODE || NET_L2_OPENTHREAD
help
Some 802.15.4 L2 implementations expect that FCS length is included in
the overall packet length while others not. Allow to configure this
behavior, based on the selected upper layer.
config IEEE802154_NRF5_DELAY_TRX_ACC
int "Clock accuracy for delayed operations"
default CLOCK_CONTROL_NRF_ACCURACY if (CLOCK_CONTROL_NRF && (CLOCK_CONTROL_NRF_ACCURACY < $(UINT8_MAX)))
default $(UINT8_MAX)
help
Accuracy of the clock used for scheduling radio delayed operations (delayed transmission
or delayed reception), in ppm.
config IEEE802154_NRF5_LOG_RX_FAILURES
bool "Frame reception failures logging"
help
There are few cases where the frame reception failure can happen because of
internal cause. These cases are reported forward by general code error.
This options enables logging the reason of frame reception failure.
It can be helpful for the network traffic analyze but it generates also
a lot of log records in a stress environment.
config IEEE802154_NRF5_MULTIPLE_CCA
bool "Support for multiple CCA attempts before transmission"
help
When this option is enabled the OpenThread capability
IEEE802154_OPENTHREAD_HW_MULTIPLE_CCA is supported by the ieee802154_nrf5.
endif
``` | /content/code_sandbox/drivers/ieee802154/Kconfig.nrf5 | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 886 |
```objective-c
/* ieee802154_cc2520.h - Registers definition for TI CC2520 */
/*
*
*/
#ifndef ZEPHYR_DRIVERS_IEEE802154_IEEE802154_CC2520_H_
#define ZEPHYR_DRIVERS_IEEE802154_IEEE802154_CC2520_H_
#include <zephyr/linker/sections.h>
#include <zephyr/sys/atomic.h>
#include <zephyr/drivers/gpio.h>
#include <zephyr/drivers/spi.h>
/* Compile time config structure
*******************************
*/
struct cc2520_config {
struct spi_dt_spec bus;
struct gpio_dt_spec vreg_en;
struct gpio_dt_spec reset;
struct gpio_dt_spec fifo;
struct gpio_dt_spec cca;
struct gpio_dt_spec sfd;
struct gpio_dt_spec fifop;
};
/* Runtime context structure
***************************
*/
struct cc2520_context {
struct net_if *iface;
/**************************/
const struct device *dev;
struct gpio_callback sfd_cb;
struct gpio_callback fifop_cb;
uint8_t mac_addr[8];
/************TX************/
struct k_sem tx_sync;
atomic_t tx;
/************RX************/
K_KERNEL_STACK_MEMBER(cc2520_rx_stack,
CONFIG_IEEE802154_CC2520_RX_STACK_SIZE);
struct k_thread cc2520_rx_thread;
struct k_sem rx_lock;
#ifdef CONFIG_IEEE802154_CC2520_CRYPTO
struct k_sem access_lock;
#endif
bool overflow;
};
#include "ieee802154_cc2520_regs.h"
/* Registers useful routines
***************************
*/
bool z_cc2520_access(const struct device *dev, bool read, uint8_t ins,
uint16_t addr, void *data, size_t length);
#define DEFINE_SREG_READ(__reg_name, __reg_addr) \
static inline uint8_t read_reg_##__reg_name(const struct device *dev) \
{ \
uint8_t val; \
\
if (z_cc2520_access(dev, true, CC2520_INS_MEMRD, \
__reg_addr, &val, 1)) { \
return val; \
} \
\
return 0; \
}
#define DEFINE_SREG_WRITE(__reg_name, __reg_addr) \
static inline bool write_reg_##__reg_name(const struct device *dev, \
uint8_t val) \
{ \
return z_cc2520_access(dev, false, CC2520_INS_MEMWR, \
__reg_addr, &val, 1); \
}
#define DEFINE_FREG_READ(__reg_name, __reg_addr) \
static inline uint8_t read_reg_##__reg_name(const struct device *dev) \
{ \
uint8_t val; \
\
if (z_cc2520_access(dev, true, CC2520_INS_REGRD, \
__reg_addr, &val, 1)) { \
return val; \
} \
\
return 0; \
}
#define DEFINE_FREG_WRITE(__reg_name, __reg_addr) \
static inline bool write_reg_##__reg_name(const struct device *dev, \
uint8_t val) \
{ \
return z_cc2520_access(dev, false, CC2520_INS_REGWR, \
__reg_addr, &val, 1); \
}
DEFINE_FREG_READ(excflag0, CC2520_FREG_EXCFLAG0)
DEFINE_FREG_READ(excflag1, CC2520_FREG_EXCFLAG1)
DEFINE_FREG_READ(excflag2, CC2520_FREG_EXCFLAG2)
DEFINE_FREG_READ(gpioctrl0, CC2520_FREG_GPIOCTRL0)
DEFINE_FREG_READ(gpioctrl1, CC2520_FREG_GPIOCTRL1)
DEFINE_FREG_READ(gpioctrl2, CC2520_FREG_GPIOCTRL2)
DEFINE_FREG_READ(gpioctrl3, CC2520_FREG_GPIOCTRL3)
DEFINE_FREG_READ(gpioctrl4, CC2520_FREG_GPIOCTRL4)
DEFINE_FREG_READ(gpioctrl5, CC2520_FREG_GPIOCTRL5)
DEFINE_FREG_READ(gpiopolarity, CC2520_FREG_GPIOPOLARITY)
DEFINE_FREG_READ(gpioctrl, CC2520_FREG_GPIOCTRL)
DEFINE_FREG_READ(txfifocnt, CC2520_FREG_TXFIFOCNT)
DEFINE_FREG_READ(rxfifocnt, CC2520_FREG_RXFIFOCNT)
DEFINE_FREG_READ(dpustat, CC2520_FREG_DPUSTAT)
DEFINE_FREG_WRITE(frmctrl0, CC2520_FREG_FRMCTRL0)
DEFINE_FREG_WRITE(frmctrl1, CC2520_FREG_FRMCTRL1)
DEFINE_FREG_WRITE(excflag0, CC2520_FREG_EXCFLAG0)
DEFINE_FREG_WRITE(excflag1, CC2520_FREG_EXCFLAG1)
DEFINE_FREG_WRITE(excflag2, CC2520_FREG_EXCFLAG2)
DEFINE_FREG_WRITE(frmfilt0, CC2520_FREG_FRMFILT0)
DEFINE_FREG_WRITE(frmfilt1, CC2520_FREG_FRMFILT1)
DEFINE_FREG_WRITE(srcmatch, CC2520_FREG_SRCMATCH)
DEFINE_FREG_WRITE(fifopctrl, CC2520_FREG_FIFOPCTRL)
DEFINE_FREG_WRITE(freqctrl, CC2520_FREG_FREQCTRL)
DEFINE_FREG_WRITE(txpower, CC2520_FREG_TXPOWER)
DEFINE_FREG_WRITE(ccactrl0, CC2520_FREG_CCACTRL0)
DEFINE_SREG_WRITE(mdmctrl0, CC2520_SREG_MDMCTRL0)
DEFINE_SREG_WRITE(mdmctrl1, CC2520_SREG_MDMCTRL1)
DEFINE_SREG_WRITE(rxctrl, CC2520_SREG_RXCTRL)
DEFINE_SREG_WRITE(fsctrl, CC2520_SREG_FSCTRL)
DEFINE_SREG_WRITE(fscal1, CC2520_SREG_FSCAL1)
DEFINE_SREG_WRITE(agcctrl1, CC2520_SREG_AGCCTRL1)
DEFINE_SREG_WRITE(adctest0, CC2520_SREG_ADCTEST0)
DEFINE_SREG_WRITE(adctest1, CC2520_SREG_ADCTEST1)
DEFINE_SREG_WRITE(adctest2, CC2520_SREG_ADCTEST2)
DEFINE_SREG_WRITE(extclock, CC2520_SREG_EXTCLOCK)
/* Memory useful routines
************************
*/
#define DEFINE_MEM_WRITE(__mem_name, __addr, __sz) \
static inline bool write_mem_##__mem_name(const struct device *dev, \
uint8_t *buf) \
{ \
return z_cc2520_access(dev, false, CC2520_INS_MEMWR, \
__addr, buf, __sz); \
}
DEFINE_MEM_WRITE(short_addr, CC2520_MEM_SHORT_ADDR, 2)
DEFINE_MEM_WRITE(pan_id, CC2520_MEM_PAN_ID, 2)
DEFINE_MEM_WRITE(ext_addr, CC2520_MEM_EXT_ADDR, 8)
/* Instructions useful routines
******************************
*/
static inline bool cc2520_command_strobe(const struct device *dev,
uint8_t instruction)
{
return z_cc2520_access(dev, false, instruction, 0, NULL, 0);
}
static inline bool cc2520_command_strobe_snop(const struct device *dev,
uint8_t instruction)
{
uint8_t snop[1] = { CC2520_INS_SNOP };
return z_cc2520_access(dev, false, instruction, 0, snop, 1);
}
#define DEFINE_STROBE_INSTRUCTION(__ins_name, __ins) \
static inline bool instruct_##__ins_name(const struct device *dev) \
{ \
return cc2520_command_strobe(dev, __ins); \
}
#define DEFINE_STROBE_SNOP_INSTRUCTION(__ins_name, __ins) \
static inline bool instruct_##__ins_name(const struct device *dev) \
{ \
return cc2520_command_strobe_snop(dev, __ins); \
}
DEFINE_STROBE_INSTRUCTION(srxon, CC2520_INS_SRXON)
DEFINE_STROBE_INSTRUCTION(srfoff, CC2520_INS_SRFOFF)
DEFINE_STROBE_INSTRUCTION(stxon, CC2520_INS_STXON)
DEFINE_STROBE_INSTRUCTION(stxoncca, CC2520_INS_STXONCCA)
DEFINE_STROBE_INSTRUCTION(sflushrx, CC2520_INS_SFLUSHRX)
DEFINE_STROBE_INSTRUCTION(sflushtx, CC2520_INS_SFLUSHTX)
DEFINE_STROBE_INSTRUCTION(sxoscoff, CC2520_INS_SXOSCOFF)
DEFINE_STROBE_SNOP_INSTRUCTION(sxoscon, CC2520_INS_SXOSCON)
#endif /* ZEPHYR_DRIVERS_IEEE802154_IEEE802154_CC2520_H_ */
``` | /content/code_sandbox/drivers/ieee802154/ieee802154_cc2520.h | objective-c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 1,914 |
```c
/* ieee802154_mcr20a.c - NXP MCR20A driver */
#define DT_DRV_COMPAT nxp_mcr20a
/*
*
*/
#define LOG_MODULE_NAME ieee802154_mcr20a
#define LOG_LEVEL CONFIG_IEEE802154_DRIVER_LOG_LEVEL
#include <zephyr/logging/log.h>
LOG_MODULE_REGISTER(LOG_MODULE_NAME);
#include <errno.h>
#include <zephyr/kernel.h>
#include <zephyr/arch/cpu.h>
#include <zephyr/debug/stack.h>
#include <zephyr/device.h>
#include <zephyr/init.h>
#include <zephyr/net/net_if.h>
#include <zephyr/net/net_pkt.h>
#include <zephyr/sys/byteorder.h>
#include <string.h>
#include <zephyr/random/random.h>
#include <zephyr/debug/stack.h>
#include <zephyr/drivers/gpio.h>
#include <zephyr/net/ieee802154_radio.h>
#include "ieee802154_mcr20a.h"
#include "MCR20Overwrites.h"
/*
* max. TX duration = (PR + SFD + FLI + PDU + FCS)
* + RX_warmup + cca + TX_warmup
* TODO: Calculate the value from frame length.
* Invalid for the SLOTTED mode.
*/
#define _MAX_PKT_TX_DURATION (133 + 9 + 8 + 9)
#if LOG_LEVEL == LOG_LEVEL_DBG
/* Prevent timer overflow during LOG_* output */
#define _MACACKWAITDURATION (864 / 16 + 11625)
#define MCR20A_SEQ_SYNC_TIMEOUT (200)
#else
#define MCR20A_SEQ_SYNC_TIMEOUT (20)
#define _MACACKWAITDURATION (864 / 16) /* 864us * 62500Hz */
#endif
#define MCR20A_FCS_LENGTH (2)
#define MCR20A_PSDU_LENGTH (125)
#define MCR20A_GET_SEQ_STATE_RETRIES (3)
/* Values for the clock output (CLK_OUT) configuration */
#ifdef CONFIG_MCR20A_CLK_OUT_DISABLED
#define MCR20A_CLK_OUT_CONFIG (MCR20A_CLK_OUT_HIZ)
#elif CONFIG_MCR20A_CLK_OUT_32MHZ
#define MCR20A_CLK_OUT_CONFIG (set_bits_clk_out_div(0) | MCR20A_CLK_OUT_DS |\
MCR20A_CLK_OUT_EN)
#elif CONFIG_MCR20A_CLK_OUT_16MHZ
#define MCR20A_CLK_OUT_CONFIG (set_bits_clk_out_div(1) | MCR20A_CLK_OUT_DS |\
MCR20A_CLK_OUT_EN)
#elif CONFIG_MCR20A_CLK_OUT_8MHZ
#define MCR20A_CLK_OUT_CONFIG (set_bits_clk_out_div(2) | MCR20A_CLK_OUT_EN)
#elif CONFIG_MCR20A_CLK_OUT_4MHZ
#define MCR20A_CLK_OUT_CONFIG (set_bits_clk_out_div(3) | MCR20A_CLK_OUT_EN)
#elif CONFIG_MCR20A_CLK_OUT_1MHZ
#define MCR20A_CLK_OUT_CONFIG (set_bits_clk_out_div(4) | MCR20A_CLK_OUT_EN)
#elif CONFIG_MCR20A_CLK_OUT_250KHZ
#define MCR20A_CLK_OUT_CONFIG (set_bits_clk_out_div(5) | MCR20A_CLK_OUT_EN)
#elif CONFIG_MCR20A_CLK_OUT_62500HZ
#define MCR20A_CLK_OUT_CONFIG (set_bits_clk_out_div(6) | MCR20A_CLK_OUT_EN)
#elif CONFIG_MCR20A_CLK_OUT_32768HZ
#define MCR20A_CLK_OUT_CONFIG (set_bits_clk_out_div(7) | MCR20A_CLK_OUT_EN)
#endif
#ifdef CONFIG_MCR20A_IS_PART_OF_KW2XD_SIP
#define PART_OF_KW2XD_SIP 1
#else
#define PART_OF_KW2XD_SIP 0
#endif
/* Values for the power mode (PM) configuration */
#define MCR20A_PM_HIBERNATE 0
#define MCR20A_PM_DOZE MCR20A_PWR_MODES_XTALEN
#define MCR20A_PM_IDLE (MCR20A_PWR_MODES_XTALEN |\
MCR20A_PWR_MODES_PMC_MODE)
#define MCR20A_PM_AUTODOZE (MCR20A_PWR_MODES_XTALEN |\
MCR20A_PWR_MODES_AUTODOZE)
/* Default settings for the device initialization */
#define MCR20A_DEFAULT_TX_POWER (0)
#define MCR20A_DEFAULT_CHANNEL (26)
/* RF TX power max/min values (dBm) */
#define MCR20A_OUTPUT_POWER_MAX (8)
#define MCR20A_OUTPUT_POWER_MIN (-35)
/* Lookup table for the Power Control register */
static const uint8_t pow_lt[44] = {
3, 4, 5, 6,
6, 7, 7, 8,
8, 9, 9, 10,
11, 11, 12, 13,
13, 14, 14, 15,
16, 16, 17, 18,
18, 19, 20, 20,
21, 21, 22, 23,
23, 24, 25, 25,
26, 27, 27, 28,
28, 29, 30, 31
};
/* PLL integer and fractional lookup tables
*
* Fc = 2405 + 5(k - 11) , k = 11,12,...,26
*
* Equation for PLL frequency, MKW2xD Reference Manual, p.255 :
* F = ((PLL_INT0 + 64) + (PLL_FRAC0/65536))32MHz
*
*/
static const uint8_t pll_int_lt[16] = {
11, 11, 11, 11,
11, 11, 12, 12,
12, 12, 12, 12,
13, 13, 13, 13
};
static const uint16_t pll_frac_lt[16] = {
10240, 20480, 30720, 40960,
51200, 61440, 6144, 16384,
26624, 36864, 47104, 57344,
2048, 12288, 22528, 32768
};
#define z_usleep(usec) k_busy_wait(usec)
/* Read direct (dreg is true) or indirect register (dreg is false) */
uint8_t z_mcr20a_read_reg(const struct device *dev, bool dreg, uint8_t addr)
{
const struct mcr20a_config *config = dev->config;
uint8_t cmd_buf[3] = {
dreg ? (MCR20A_REG_READ | addr) :
(MCR20A_IAR_INDEX | MCR20A_REG_WRITE),
dreg ? 0 : (addr | MCR20A_REG_READ),
0
};
uint8_t len = dreg ? 2 : 3;
const struct spi_buf buf = {
.buf = cmd_buf,
.len = len
};
const struct spi_buf_set tx = {
.buffers = &buf,
.count = 1
};
const struct spi_buf_set rx = {
.buffers = &buf,
.count = 1
};
if (spi_transceive_dt(&config->bus, &tx, &rx) == 0) {
return cmd_buf[len - 1];
}
LOG_ERR("Failed");
return 0;
}
/* Write direct (dreg is true) or indirect register (dreg is false) */
bool z_mcr20a_write_reg(const struct device *dev, bool dreg, uint8_t addr,
uint8_t value)
{
const struct mcr20a_config *config = dev->config;
uint8_t cmd_buf[3] = {
dreg ? (MCR20A_REG_WRITE | addr) :
(MCR20A_IAR_INDEX | MCR20A_REG_WRITE),
dreg ? value : (addr | MCR20A_REG_WRITE),
dreg ? 0 : value
};
const struct spi_buf buf = {
.buf = cmd_buf,
.len = dreg ? 2 : 3
};
const struct spi_buf_set tx = {
.buffers = &buf,
.count = 1
};
return (spi_write_dt(&config->bus, &tx) == 0);
}
/* Write multiple bytes to direct or indirect register */
bool z_mcr20a_write_burst(const struct device *dev, bool dreg, uint16_t addr,
uint8_t *data_buf, uint8_t len)
{
const struct mcr20a_config *config = dev->config;
uint8_t cmd_buf[2] = {
dreg ? MCR20A_REG_WRITE | addr :
MCR20A_IAR_INDEX | MCR20A_REG_WRITE,
dreg ? 0 : addr | MCR20A_REG_WRITE
};
struct spi_buf bufs[2] = {
{
.buf = cmd_buf,
.len = dreg ? 1 : 2
},
{
.buf = data_buf,
.len = len
}
};
const struct spi_buf_set tx = {
.buffers = bufs,
.count = 2
};
return (spi_write_dt(&config->bus, &tx) == 0);
}
/* Read multiple bytes from direct or indirect register */
bool z_mcr20a_read_burst(const struct device *dev, bool dreg, uint16_t addr,
uint8_t *data_buf, uint8_t len)
{
const struct mcr20a_config *config = dev->config;
uint8_t cmd_buf[2] = {
dreg ? MCR20A_REG_READ | addr :
MCR20A_IAR_INDEX | MCR20A_REG_WRITE,
dreg ? 0 : addr | MCR20A_REG_READ
};
struct spi_buf bufs[2] = {
{
.buf = cmd_buf,
.len = dreg ? 1 : 2
},
{
.buf = data_buf,
.len = len
}
};
const struct spi_buf_set tx = {
.buffers = bufs,
.count = 1
};
const struct spi_buf_set rx = {
.buffers = bufs,
.count = 2
};
return (spi_transceive_dt(&config->bus, &tx, &rx) == 0);
}
/* Mask (msk is true) or unmask all interrupts from asserting IRQ_B */
static bool mcr20a_mask_irqb(const struct device *dev, bool msk)
{
uint8_t ctrl4 = read_reg_phy_ctrl4(dev);
if (msk) {
ctrl4 |= MCR20A_PHY_CTRL4_TRCV_MSK;
} else {
ctrl4 &= ~MCR20A_PHY_CTRL4_TRCV_MSK;
}
return write_reg_phy_ctrl4(dev, ctrl4);
}
/** Set an timeout value for the given compare register */
static int mcr20a_timer_set(const struct device *dev,
uint8_t cmp_reg,
uint32_t timeout)
{
uint32_t now = 0U;
uint32_t next;
bool retval;
if (!read_burst_event_timer(dev, (uint8_t *)&now)) {
goto error;
}
now = sys_le32_to_cpu(now);
next = now + timeout;
LOG_DBG("now: 0x%x set 0x%x", now, next);
next = sys_cpu_to_le32(next);
switch (cmp_reg) {
case 1:
retval = write_burst_t1cmp(dev, (uint8_t *)&next);
break;
case 2:
retval = write_burst_t2cmp(dev, (uint8_t *)&next);
break;
case 3:
retval = write_burst_t3cmp(dev, (uint8_t *)&next);
break;
case 4:
retval = write_burst_t4cmp(dev, (uint8_t *)&next);
break;
default:
goto error;
}
if (!retval) {
goto error;
}
return 0;
error:
LOG_ERR("Failed");
return -EIO;
}
static int mcr20a_timer_init(const struct device *dev, uint8_t tb)
{
uint8_t buf[3] = {0, 0, 0};
uint8_t ctrl4;
if (!write_reg_tmr_prescale(dev,
set_bits_tmr_prescale(tb))) {
goto error;
}
if (!write_burst_t1cmp(dev, buf)) {
goto error;
}
ctrl4 = read_reg_phy_ctrl4(dev);
ctrl4 |= MCR20A_PHY_CTRL4_TMRLOAD;
if (!write_reg_phy_ctrl4(dev, ctrl4)) {
goto error;
}
LOG_DBG("done, timebase %d", tb);
return 0;
error:
LOG_ERR("Failed");
return -EIO;
}
/* Set Timer Comparator 4 */
static int mcr20a_t4cmp_set(const struct device *dev,
uint32_t timeout)
{
uint8_t irqsts3;
uint8_t ctrl3;
if (mcr20a_timer_set(dev, 4, timeout)) {
goto error;
}
/* enable and clear irq for the timer 4 */
irqsts3 = read_reg_irqsts3(dev);
irqsts3 &= ~MCR20A_IRQSTS3_TMR4MSK;
irqsts3 |= MCR20A_IRQSTS3_TMR4IRQ;
if (!write_reg_irqsts3(dev, irqsts3)) {
goto error;
}
ctrl3 = read_reg_phy_ctrl3(dev);
ctrl3 |= MCR20A_PHY_CTRL3_TMR4CMP_EN;
if (!write_reg_phy_ctrl3(dev, ctrl3)) {
goto error;
}
return 0;
error:
LOG_DBG("Failed");
return -EIO;
}
/* Clear Timer Comparator 4 */
static int mcr20a_t4cmp_clear(const struct device *dev)
{
uint8_t irqsts3;
uint8_t ctrl3;
ctrl3 = read_reg_phy_ctrl3(dev);
ctrl3 &= ~MCR20A_PHY_CTRL3_TMR4CMP_EN;
if (!write_reg_phy_ctrl3(dev, ctrl3)) {
goto error;
}
irqsts3 = read_reg_irqsts3(dev);
irqsts3 |= MCR20A_IRQSTS3_TMR4IRQ;
if (!write_reg_irqsts3(dev, irqsts3)) {
goto error;
}
return 0;
error:
LOG_DBG("Failed");
return -EIO;
}
static inline void xcvseq_wait_until_idle(const struct device *dev)
{
uint8_t state;
uint8_t retries = MCR20A_GET_SEQ_STATE_RETRIES;
do {
state = read_reg_seq_state(dev);
retries--;
} while ((state & MCR20A_SEQ_STATE_MASK) && retries);
if (state & MCR20A_SEQ_STATE_MASK) {
LOG_ERR("Timeout");
}
}
static inline int mcr20a_abort_sequence(const struct device *dev,
bool force)
{
uint8_t ctrl1;
ctrl1 = read_reg_phy_ctrl1(dev);
LOG_DBG("CTRL1 0x%02x", ctrl1);
if (((ctrl1 & MCR20A_PHY_CTRL1_XCVSEQ_MASK) == MCR20A_XCVSEQ_TX) ||
((ctrl1 & MCR20A_PHY_CTRL1_XCVSEQ_MASK) == MCR20A_XCVSEQ_TX_RX)) {
if (!force) {
return -1;
}
}
/* Abort ongoing sequence */
ctrl1 &= ~MCR20A_PHY_CTRL1_XCVSEQ_MASK;
if (!write_reg_phy_ctrl1(dev, ctrl1)) {
return -1;
}
xcvseq_wait_until_idle(dev);
/* Clear relevant interrupt flags */
if (!write_reg_irqsts1(dev, MCR20A_IRQSTS1_IRQ_MASK)) {
return -1;
}
return 0;
}
/* Initiate a (new) Transceiver Sequence */
static inline int mcr20a_set_sequence(const struct device *dev,
uint8_t seq)
{
uint8_t ctrl1 = 0U;
seq = set_bits_phy_ctrl1_xcvseq(seq);
ctrl1 = read_reg_phy_ctrl1(dev);
ctrl1 &= ~MCR20A_PHY_CTRL1_XCVSEQ_MASK;
if ((seq == MCR20A_XCVSEQ_TX_RX) &&
(ctrl1 & MCR20A_PHY_CTRL1_RXACKRQD)) {
/* RXACKRQD enabled, timer should be set. */
mcr20a_t4cmp_set(dev, _MACACKWAITDURATION +
_MAX_PKT_TX_DURATION);
}
ctrl1 |= seq;
if (!write_reg_phy_ctrl1(dev, ctrl1)) {
return -EIO;
}
return 0;
}
#define DIV_ROUND_CLOSEST_WITH_OPPOSITE_SIGNS(n, d) (((n) - (d)/2)/(d))
static inline int16_t mcr20a_get_rssi(uint8_t lqi)
{
/* Calculate the RSSI (Received Signal Strength Indicator)
* in dBm from the LQI (Link Quality Indicator) value.
*
* There are two different equations for the RF value (which
* we use as the RSSI value) in the reference manuals:
*
* RF = (LQI 286.6) / 2.69333 (MKW2xD Reference Manual)
* RF = (LQI 295.4) / 2.84 (MCR20A Reference Manual)
*
* The second is derived from empiric values (see Figure 3-10)
* so we use that one.
*
* Since we want to avoid floating point computation and
* the result needs to be rounded to a signed integer value
* anyways, we take the numerator and denominator times 100
* each and round the end result of the division:
* RF = (LQI 295.4) / 2.84
* = (100 * (LQI 295.4)) / (100 * 2.84)
* = (100 * LQI 29540) / 284
*/
int16_t numerator = ((int16_t)100 * lqi) - 29540; /* always negative */
return DIV_ROUND_CLOSEST_WITH_OPPOSITE_SIGNS(numerator, 284);
}
static inline uint8_t *get_mac(const struct device *dev)
{
struct mcr20a_context *mcr20a = dev->data;
sys_rand_get(mcr20a->mac_addr, sizeof(mcr20a->mac_addr));
mcr20a->mac_addr[0] = (mcr20a->mac_addr[0] & ~0x01) | 0x02;
return mcr20a->mac_addr;
}
static inline bool read_rxfifo_content(const struct device *dev,
struct net_buf *buf, uint8_t len)
{
const struct mcr20a_config *config = dev->config;
uint8_t cmd = MCR20A_BUF_READ;
struct spi_buf bufs[2] = {
{
.buf = &cmd,
.len = 1
},
{
.buf = buf->data,
.len = len
}
};
const struct spi_buf_set tx = {
.buffers = bufs,
.count = 1
};
const struct spi_buf_set rx = {
.buffers = bufs,
.count = 2
};
if (spi_transceive_dt(&config->bus, &tx, &rx) != 0) {
return false;
}
net_buf_add(buf, len);
return true;
}
static inline void mcr20a_rx(const struct device *dev, uint8_t len)
{
struct mcr20a_context *mcr20a = dev->data;
struct net_pkt *pkt = NULL;
uint8_t pkt_len;
uint16_t rssi;
uint8_t lqi;
pkt_len = len - MCR20A_FCS_LENGTH;
pkt = net_pkt_rx_alloc_with_buffer(mcr20a->iface, pkt_len,
AF_UNSPEC, 0, K_NO_WAIT);
if (!pkt) {
LOG_ERR("No buf available");
goto out;
}
if (!read_rxfifo_content(dev, pkt->buffer, pkt_len)) {
LOG_ERR("No content read");
goto out;
}
/* TODO: ieee802154_handle_ack() expects an ACK package. */
if (ieee802154_handle_ack(mcr20a->iface, pkt) == NET_OK) {
LOG_DBG("ACK packet handled");
goto out;
}
lqi = read_reg_lqi_value(dev);
net_pkt_set_ieee802154_lqi(pkt, lqi);
rssi = mcr20a_get_rssi(lqi);
net_pkt_set_ieee802154_rssi_dbm(pkt, rssi);
LOG_DBG("Caught a packet (%u) (LQI: %u, RSSI: %d)", pkt_len, lqi, rssi);
if (net_recv_data(mcr20a->iface, pkt) < 0) {
LOG_DBG("Packet dropped by NET stack");
goto out;
}
log_stack_usage(&mcr20a->mcr20a_rx_thread);
return;
out:
if (pkt) {
net_pkt_unref(pkt);
}
}
/*
* The function checks how the XCV sequence has been completed
* and sets the variable seq_retval accordingly. It returns true
* if a new sequence is to be set. This function is only to be called
* when a sequence has been completed.
*/
static inline bool irqsts1_event(const struct device *dev,
uint8_t *dregs)
{
struct mcr20a_context *mcr20a = dev->data;
uint8_t seq = dregs[MCR20A_PHY_CTRL1] & MCR20A_PHY_CTRL1_XCVSEQ_MASK;
uint8_t new_seq = MCR20A_XCVSEQ_RECEIVE;
bool retval = false;
switch (seq) {
case MCR20A_XCVSEQ_RECEIVE:
if ((dregs[MCR20A_IRQSTS1] & MCR20A_IRQSTS1_RXIRQ)) {
if ((dregs[MCR20A_IRQSTS1] & MCR20A_IRQSTS1_TXIRQ)) {
LOG_DBG("Finished RxSeq + TxAck");
} else {
LOG_DBG("Finished RxSeq");
}
mcr20a_rx(dev, dregs[MCR20A_RX_FRM_LEN]);
retval = true;
}
break;
case MCR20A_XCVSEQ_TX:
case MCR20A_XCVSEQ_TX_RX:
if (dregs[MCR20A_IRQSTS1] & MCR20A_IRQSTS1_CCAIRQ) {
if (dregs[MCR20A_IRQSTS2] & MCR20A_IRQSTS2_CCA) {
LOG_DBG("Finished CCA, CH busy");
atomic_set(&mcr20a->seq_retval, -EBUSY);
retval = true;
break;
}
}
if (dregs[MCR20A_IRQSTS1] & MCR20A_IRQSTS1_TXIRQ) {
atomic_set(&mcr20a->seq_retval, 0);
if ((dregs[MCR20A_IRQSTS1] & MCR20A_IRQSTS1_RXIRQ)) {
LOG_DBG("Finished TxSeq + RxAck");
/* Got Ack, timer should be disabled. */
mcr20a_t4cmp_clear(dev);
} else {
LOG_DBG("Finished TxSeq");
}
retval = true;
}
break;
case MCR20A_XCVSEQ_CONTINUOUS_CCA:
case MCR20A_XCVSEQ_CCA:
if ((dregs[MCR20A_IRQSTS1] & MCR20A_IRQSTS1_CCAIRQ)) {
/* If CCCA, then timer should be disabled. */
/* mcr20a_t4cmp_clear(dev); */
if (dregs[MCR20A_IRQSTS2] & MCR20A_IRQSTS2_CCA) {
LOG_DBG("Finished CCA, CH busy");
atomic_set(&mcr20a->seq_retval, -EBUSY);
} else {
/**
* Assume that after the CCA,
* a transmit sequence follows and
* set here the sequence manager to Idle.
*/
LOG_DBG("Finished CCA, CH idle");
new_seq = MCR20A_XCVSEQ_IDLE;
atomic_set(&mcr20a->seq_retval, 0);
}
retval = true;
}
break;
case MCR20A_XCVSEQ_IDLE:
default:
LOG_ERR("SEQ triggered, but XCVSEQ is in the Idle state");
LOG_ERR("IRQSTS: 0x%02x", dregs[MCR20A_IRQSTS1]);
break;
}
dregs[MCR20A_PHY_CTRL1] &= ~MCR20A_PHY_CTRL1_XCVSEQ_MASK;
dregs[MCR20A_PHY_CTRL1] |= new_seq;
return retval;
}
/*
* Check the Timer Comparator IRQ register IRQSTS3.
* Currently we use only T4CMP to cancel the running sequence,
* usually the TR.
*/
static inline bool irqsts3_event(const struct device *dev,
uint8_t *dregs)
{
struct mcr20a_context *mcr20a = dev->data;
bool retval = false;
if (dregs[MCR20A_IRQSTS3] & MCR20A_IRQSTS3_TMR4IRQ) {
LOG_DBG("Sequence timeout, IRQSTSs 0x%02x 0x%02x 0x%02x",
dregs[MCR20A_IRQSTS1],
dregs[MCR20A_IRQSTS2],
dregs[MCR20A_IRQSTS3]);
atomic_set(&mcr20a->seq_retval, -EBUSY);
mcr20a_t4cmp_clear(dev);
dregs[MCR20A_PHY_CTRL1] &= ~MCR20A_PHY_CTRL1_XCVSEQ_MASK;
dregs[MCR20A_PHY_CTRL1] |= MCR20A_XCVSEQ_RECEIVE;
/* Clear all interrupts */
dregs[MCR20A_IRQSTS1] = MCR20A_IRQSTS1_IRQ_MASK;
retval = true;
} else {
LOG_ERR("IRQSTS3 contains untreated IRQs: 0x%02x",
dregs[MCR20A_IRQSTS3]);
}
return retval;
}
static void mcr20a_thread_main(void *p1, void *p2, void *p3)
{
ARG_UNUSED(p2);
ARG_UNUSED(p3);
const struct device *dev = p1;
struct mcr20a_context *mcr20a = dev->data;
uint8_t dregs[MCR20A_PHY_CTRL4 + 1];
bool set_new_seq;
uint8_t ctrl1 = 0U;
while (true) {
k_sem_take(&mcr20a->isr_sem, K_FOREVER);
k_mutex_lock(&mcr20a->phy_mutex, K_FOREVER);
set_new_seq = false;
if (!mcr20a_mask_irqb(dev, true)) {
LOG_ERR("Failed to mask IRQ_B");
goto unmask_irqb;
}
/* Read the register from IRQSTS1 until CTRL4 */
if (!read_burst_irqsts1_ctrl4(dev, dregs)) {
LOG_ERR("Failed to read register");
goto unmask_irqb;
}
/* make backup from PHY_CTRL1 register */
ctrl1 = dregs[MCR20A_PHY_CTRL1];
if (dregs[MCR20A_IRQSTS3] & MCR20A_IRQSTS3_IRQ_MASK) {
set_new_seq = irqsts3_event(dev, dregs);
} else if (dregs[MCR20A_IRQSTS1] & MCR20A_IRQSTS1_SEQIRQ) {
set_new_seq = irqsts1_event(dev, dregs);
}
if (dregs[MCR20A_IRQSTS2] & MCR20A_IRQSTS2_IRQ_MASK) {
LOG_ERR("IRQSTS2 contains untreated IRQs: 0x%02x",
dregs[MCR20A_IRQSTS2]);
}
LOG_DBG("WB: 0x%02x | 0x%02x | 0x%02x",
dregs[MCR20A_IRQSTS1],
dregs[MCR20A_IRQSTS2],
dregs[MCR20A_IRQSTS3]);
/* Write back register, clear IRQs and set new sequence */
if (set_new_seq) {
/* Reset sequence manager */
ctrl1 &= ~MCR20A_PHY_CTRL1_XCVSEQ_MASK;
if (!write_reg_phy_ctrl1(dev, ctrl1)) {
LOG_ERR("Failed to reset SEQ manager");
}
xcvseq_wait_until_idle(dev);
if (!write_burst_irqsts1_ctrl1(dev, dregs)) {
LOG_ERR("Failed to write CTRL1");
}
} else {
if (!write_burst_irqsts1_irqsts3(dev, dregs)) {
LOG_ERR("Failed to write IRQSTS3");
}
}
unmask_irqb:
if (!mcr20a_mask_irqb(dev, false)) {
LOG_ERR("Failed to unmask IRQ_B");
}
k_mutex_unlock(&mcr20a->phy_mutex);
if (set_new_seq) {
k_sem_give(&mcr20a->seq_sync);
}
}
}
static inline void irqb_int_handler(const struct device *port,
struct gpio_callback *cb, uint32_t pins)
{
struct mcr20a_context *mcr20a = CONTAINER_OF(cb,
struct mcr20a_context,
irqb_cb);
k_sem_give(&mcr20a->isr_sem);
}
static void enable_irqb_interrupt(const struct device *dev,
bool enable)
{
const struct mcr20a_config *config = dev->config;
gpio_flags_t flags = enable
? GPIO_INT_EDGE_TO_ACTIVE
: GPIO_INT_DISABLE;
gpio_pin_interrupt_configure_dt(&config->irq_gpio, flags);
}
static inline void setup_gpio_callbacks(const struct device *dev)
{
const struct mcr20a_config *config = dev->config;
struct mcr20a_context *mcr20a = dev->data;
gpio_init_callback(&mcr20a->irqb_cb,
irqb_int_handler,
BIT(config->irq_gpio.pin));
gpio_add_callback(config->irq_gpio.port, &mcr20a->irqb_cb);
}
static int mcr20a_set_cca_mode(const struct device *dev, uint8_t mode)
{
uint8_t ctrl4;
ctrl4 = read_reg_phy_ctrl4(dev);
ctrl4 &= ~MCR20A_PHY_CTRL4_CCATYPE_MASK;
ctrl4 |= set_bits_phy_ctrl4_ccatype(mode);
if (!write_reg_phy_ctrl4(dev, ctrl4)) {
LOG_ERR("Failed");
return -EIO;
}
return 0;
}
static enum ieee802154_hw_caps mcr20a_get_capabilities(const struct device *dev)
{
return IEEE802154_HW_FCS | IEEE802154_HW_TX_RX_ACK |
IEEE802154_HW_RX_TX_ACK | IEEE802154_HW_FILTER;
}
/* Note: CCA before TX is enabled by default */
static int mcr20a_cca(const struct device *dev)
{
struct mcr20a_context *mcr20a = dev->data;
int retval;
k_mutex_lock(&mcr20a->phy_mutex, K_FOREVER);
if (!mcr20a_mask_irqb(dev, true)) {
LOG_ERR("Failed to mask IRQ_B");
goto error;
}
k_sem_init(&mcr20a->seq_sync, 0, 1);
if (mcr20a_abort_sequence(dev, false)) {
LOG_ERR("Failed to reset XCV sequence");
goto error;
}
LOG_DBG("start CCA sequence");
if (mcr20a_set_sequence(dev, MCR20A_XCVSEQ_CCA)) {
LOG_ERR("Failed to reset XCV sequence");
goto error;
}
if (!mcr20a_mask_irqb(dev, false)) {
LOG_ERR("Failed to unmask IRQ_B");
goto error;
}
k_mutex_unlock(&mcr20a->phy_mutex);
retval = k_sem_take(&mcr20a->seq_sync,
K_MSEC(MCR20A_SEQ_SYNC_TIMEOUT));
if (retval) {
LOG_ERR("Timeout occurred, %d", retval);
return retval;
}
LOG_DBG("done");
return mcr20a->seq_retval;
error:
k_mutex_unlock(&mcr20a->phy_mutex);
return -EIO;
}
static int mcr20a_set_channel(const struct device *dev, uint16_t channel)
{
struct mcr20a_context *mcr20a = dev->data;
uint8_t buf[3];
uint8_t ctrl1;
int retval = -EIO;
if (channel < 11 || channel > 26) {
LOG_ERR("Unsupported channel %u", channel);
return channel < 11 ? -ENOTSUP : -EINVAL;
}
k_mutex_lock(&mcr20a->phy_mutex, K_FOREVER);
if (!mcr20a_mask_irqb(dev, true)) {
LOG_ERR("Failed to mask IRQ_B");
goto out;
}
ctrl1 = read_reg_phy_ctrl1(dev);
if (mcr20a_abort_sequence(dev, true)) {
LOG_ERR("Failed to reset XCV sequence");
goto out;
}
LOG_DBG("%u", channel);
channel -= 11U;
buf[0] = set_bits_pll_int0_val(pll_int_lt[channel]);
buf[1] = (uint8_t)pll_frac_lt[channel];
buf[2] = (uint8_t)(pll_frac_lt[channel] >> 8);
if (!write_burst_pll_int0(dev, buf)) {
LOG_ERR("Failed to set PLL");
goto out;
}
if (mcr20a_set_sequence(dev, ctrl1)) {
LOG_ERR("Failed to restore XCV sequence");
goto out;
}
retval = 0;
out:
if (!mcr20a_mask_irqb(dev, false)) {
LOG_ERR("Failed to unmask IRQ_B");
retval = -EIO;
}
k_mutex_unlock(&mcr20a->phy_mutex);
return retval;
}
static int mcr20a_set_pan_id(const struct device *dev, uint16_t pan_id)
{
struct mcr20a_context *mcr20a = dev->data;
pan_id = sys_le16_to_cpu(pan_id);
k_mutex_lock(&mcr20a->phy_mutex, K_FOREVER);
if (!write_burst_pan_id(dev, (uint8_t *) &pan_id)) {
LOG_ERR("Failed");
k_mutex_unlock(&mcr20a->phy_mutex);
return -EIO;
}
k_mutex_unlock(&mcr20a->phy_mutex);
LOG_DBG("0x%x", pan_id);
return 0;
}
static int mcr20a_set_short_addr(const struct device *dev,
uint16_t short_addr)
{
struct mcr20a_context *mcr20a = dev->data;
short_addr = sys_le16_to_cpu(short_addr);
k_mutex_lock(&mcr20a->phy_mutex, K_FOREVER);
if (!write_burst_short_addr(dev, (uint8_t *) &short_addr)) {
LOG_ERR("Failed");
k_mutex_unlock(&mcr20a->phy_mutex);
return -EIO;
}
k_mutex_unlock(&mcr20a->phy_mutex);
LOG_DBG("0x%x", short_addr);
return 0;
}
static int mcr20a_set_ieee_addr(const struct device *dev,
const uint8_t *ieee_addr)
{
struct mcr20a_context *mcr20a = dev->data;
k_mutex_lock(&mcr20a->phy_mutex, K_FOREVER);
if (!write_burst_ext_addr(dev, (void *)ieee_addr)) {
LOG_ERR("Failed");
k_mutex_unlock(&mcr20a->phy_mutex);
return -EIO;
}
k_mutex_unlock(&mcr20a->phy_mutex);
LOG_DBG("IEEE address %02x:%02x:%02x:%02x:%02x:%02x:%02x:%02x",
ieee_addr[7], ieee_addr[6], ieee_addr[5], ieee_addr[4],
ieee_addr[3], ieee_addr[2], ieee_addr[1], ieee_addr[0]);
return 0;
}
static int mcr20a_filter(const struct device *dev,
bool set,
enum ieee802154_filter_type type,
const struct ieee802154_filter *filter)
{
LOG_DBG("Applying filter %u", type);
if (!set) {
return -ENOTSUP;
}
if (type == IEEE802154_FILTER_TYPE_IEEE_ADDR) {
return mcr20a_set_ieee_addr(dev, filter->ieee_addr);
} else if (type == IEEE802154_FILTER_TYPE_SHORT_ADDR) {
return mcr20a_set_short_addr(dev, filter->short_addr);
} else if (type == IEEE802154_FILTER_TYPE_PAN_ID) {
return mcr20a_set_pan_id(dev, filter->pan_id);
}
return -ENOTSUP;
}
static int mcr20a_set_txpower(const struct device *dev, int16_t dbm)
{
struct mcr20a_context *mcr20a = dev->data;
uint8_t pwr;
k_mutex_lock(&mcr20a->phy_mutex, K_FOREVER);
LOG_DBG("%d", dbm);
if ((dbm > MCR20A_OUTPUT_POWER_MAX) ||
(dbm < MCR20A_OUTPUT_POWER_MIN)) {
goto error;
}
pwr = pow_lt[dbm - MCR20A_OUTPUT_POWER_MIN];
if (!write_reg_pa_pwr(dev, set_bits_pa_pwr_val(pwr))) {
goto error;
}
k_mutex_unlock(&mcr20a->phy_mutex);
return 0;
error:
k_mutex_unlock(&mcr20a->phy_mutex);
LOG_DBG("Failed");
return -EIO;
}
static inline bool write_txfifo_content(const struct device *dev,
struct net_pkt *pkt,
struct net_buf *frag)
{
const struct mcr20a_config *config = dev->config;
size_t payload_len = frag->len;
uint8_t cmd_buf[2] = {
MCR20A_BUF_WRITE,
payload_len + MCR20A_FCS_LENGTH
};
const struct spi_buf bufs[2] = {
{
.buf = cmd_buf,
.len = 2
},
{
.buf = frag->data,
.len = payload_len
}
};
const struct spi_buf_set tx = {
.buffers = bufs,
.count = 2
};
if (payload_len > MCR20A_PSDU_LENGTH) {
LOG_ERR("Payload too long");
return 0;
}
return (spi_write_dt(&config->bus, &tx) == 0);
}
static int mcr20a_tx(const struct device *dev,
enum ieee802154_tx_mode mode,
struct net_pkt *pkt,
struct net_buf *frag)
{
struct mcr20a_context *mcr20a = dev->data;
uint8_t seq = ieee802154_is_ar_flag_set(frag) ? MCR20A_XCVSEQ_TX_RX :
MCR20A_XCVSEQ_TX;
int retval;
if (mode != IEEE802154_TX_MODE_DIRECT) {
NET_ERR("TX mode %d not supported", mode);
return -ENOTSUP;
}
k_mutex_lock(&mcr20a->phy_mutex, K_FOREVER);
LOG_DBG("%p (%u)", frag, frag->len);
if (!mcr20a_mask_irqb(dev, true)) {
LOG_ERR("Failed to mask IRQ_B");
goto error;
}
if (mcr20a_abort_sequence(dev, false)) {
LOG_ERR("Failed to reset XCV sequence");
goto error;
}
if (!write_txfifo_content(dev, pkt, frag)) {
LOG_ERR("Did not write properly into TX FIFO");
goto error;
}
k_sem_init(&mcr20a->seq_sync, 0, 1);
if (mcr20a_set_sequence(dev, seq)) {
LOG_ERR("Cannot start transmission");
goto error;
}
if (!mcr20a_mask_irqb(dev, false)) {
LOG_ERR("Failed to unmask IRQ_B");
goto error;
}
k_mutex_unlock(&mcr20a->phy_mutex);
retval = k_sem_take(&mcr20a->seq_sync,
K_MSEC(MCR20A_SEQ_SYNC_TIMEOUT));
if (retval) {
LOG_ERR("Timeout occurred, %d", retval);
return retval;
}
LOG_DBG("done");
return mcr20a->seq_retval;
error:
k_mutex_unlock(&mcr20a->phy_mutex);
return -EIO;
}
static int mcr20a_start(const struct device *dev)
{
struct mcr20a_context *mcr20a = dev->data;
uint8_t timeout = 6U;
uint8_t status;
k_mutex_lock(&mcr20a->phy_mutex, K_FOREVER);
enable_irqb_interrupt(dev, false);
if (!write_reg_pwr_modes(dev, MCR20A_PM_AUTODOZE)) {
LOG_ERR("Error starting MCR20A");
goto error;
}
do {
z_usleep(50);
timeout--;
status = read_reg_pwr_modes(dev);
} while (!(status & MCR20A_PWR_MODES_XTAL_READY) && timeout);
if (!(status & MCR20A_PWR_MODES_XTAL_READY)) {
LOG_ERR("Timeout, failed to wake up");
goto error;
}
/* Clear all interrupt flags */
write_reg_irqsts1(dev, MCR20A_IRQSTS1_IRQ_MASK);
write_reg_irqsts2(dev, MCR20A_IRQSTS2_IRQ_MASK);
write_reg_irqsts3(dev, MCR20A_IRQSTS3_IRQ_MASK |
MCR20A_IRQSTS3_TMR_MASK);
if (mcr20a_abort_sequence(dev, true)) {
LOG_ERR("Failed to reset XCV sequence");
goto error;
}
if (mcr20a_set_sequence(dev, MCR20A_XCVSEQ_RECEIVE)) {
LOG_ERR("Failed to set XCV sequence");
goto error;
}
enable_irqb_interrupt(dev, true);
if (!mcr20a_mask_irqb(dev, false)) {
LOG_ERR("Failed to unmask IRQ_B");
goto error;
}
k_mutex_unlock(&mcr20a->phy_mutex);
LOG_DBG("started");
return 0;
error:
k_mutex_unlock(&mcr20a->phy_mutex);
return -EIO;
}
static int mcr20a_stop(const struct device *dev)
{
struct mcr20a_context *mcr20a = dev->data;
uint8_t power_mode;
k_mutex_lock(&mcr20a->phy_mutex, K_FOREVER);
if (!mcr20a_mask_irqb(dev, true)) {
LOG_ERR("Failed to mask IRQ_B");
goto error;
}
if (mcr20a_abort_sequence(dev, true)) {
LOG_ERR("Failed to reset XCV sequence");
goto error;
}
enable_irqb_interrupt(dev, false);
if (PART_OF_KW2XD_SIP) {
power_mode = MCR20A_PM_DOZE;
} else {
power_mode = MCR20A_PM_HIBERNATE;
}
if (!write_reg_pwr_modes(dev, power_mode)) {
goto error;
}
LOG_DBG("stopped");
k_mutex_unlock(&mcr20a->phy_mutex);
return 0;
error:
k_mutex_unlock(&mcr20a->phy_mutex);
LOG_ERR("Error stopping MCR20A");
return -EIO;
}
/* driver-allocated attribute memory - constant across all driver instances */
IEEE802154_DEFINE_PHY_SUPPORTED_CHANNELS(drv_attr, 11, 26);
static int mcr20a_attr_get(const struct device *dev, enum ieee802154_attr attr,
struct ieee802154_attr_value *value)
{
ARG_UNUSED(dev);
return ieee802154_attr_get_channel_page_and_range(
attr, IEEE802154_ATTR_PHY_CHANNEL_PAGE_ZERO_OQPSK_2450_BPSK_868_915,
&drv_attr.phy_supported_channels, value);
}
static int mcr20a_update_overwrites(const struct device *dev)
{
if (!write_reg_overwrite_ver(dev, overwrites_direct[0].data)) {
goto error;
}
for (uint8_t i = 0;
i < sizeof(overwrites_indirect) / sizeof(overwrites_t);
i++) {
if (!z_mcr20a_write_reg(dev, false,
overwrites_indirect[i].address,
overwrites_indirect[i].data)) {
goto error;
}
}
return 0;
error:
LOG_ERR("Error update overwrites");
return -EIO;
}
static int power_on_and_setup(const struct device *dev)
{
const struct mcr20a_config *config = dev->config;
uint8_t timeout = 6U;
int pin;
uint8_t tmp = 0U;
if (!PART_OF_KW2XD_SIP) {
gpio_pin_set_dt(&config->reset_gpio, 1);
z_usleep(150);
gpio_pin_set_dt(&config->reset_gpio, 0);
do {
z_usleep(50);
timeout--;
pin = gpio_pin_get_dt(&config->irq_gpio);
} while (pin > 0 && timeout);
if (pin) {
LOG_ERR("Timeout, failed to get WAKE IRQ");
return -EIO;
}
}
tmp = MCR20A_CLK_OUT_CONFIG | MCR20A_CLK_OUT_EXTEND;
write_reg_clk_out_ctrl(dev, tmp);
if (read_reg_clk_out_ctrl(dev) != tmp) {
LOG_ERR("Failed to get device up");
return -EIO;
}
/* Clear all interrupt flags */
write_reg_irqsts1(dev, MCR20A_IRQSTS1_IRQ_MASK);
write_reg_irqsts2(dev, MCR20A_IRQSTS2_IRQ_MASK);
write_reg_irqsts3(dev, MCR20A_IRQSTS3_IRQ_MASK |
MCR20A_IRQSTS3_TMR_MASK);
mcr20a_update_overwrites(dev);
mcr20a_timer_init(dev, MCR20A_TIMEBASE_62500HZ);
mcr20a_set_txpower(dev, MCR20A_DEFAULT_TX_POWER);
mcr20a_set_channel(dev, MCR20A_DEFAULT_CHANNEL);
mcr20a_set_cca_mode(dev, 1);
write_reg_rx_wtr_mark(dev, 8);
/* Configure PHY behaviour */
tmp = MCR20A_PHY_CTRL1_CCABFRTX |
MCR20A_PHY_CTRL1_AUTOACK |
MCR20A_PHY_CTRL1_RXACKRQD;
write_reg_phy_ctrl1(dev, tmp);
/* Enable Sequence-end interrupt */
tmp = MCR20A_PHY_CTRL2_SEQMSK;
write_reg_phy_ctrl2(dev, ~tmp);
setup_gpio_callbacks(dev);
return 0;
}
static inline int configure_gpios(const struct device *dev)
{
const struct mcr20a_config *config = dev->config;
/* setup gpio for the modem interrupt */
if (!gpio_is_ready_dt(&config->irq_gpio)) {
LOG_ERR("IRQ GPIO device not ready");
return -ENODEV;
}
gpio_pin_configure_dt(&config->irq_gpio, GPIO_INPUT);
if (!PART_OF_KW2XD_SIP) {
/* setup gpio for the modems reset */
if (!gpio_is_ready_dt(&config->reset_gpio)) {
LOG_ERR("Reset GPIO device not ready");
return -EINVAL;
}
gpio_pin_configure_dt(&config->reset_gpio, GPIO_OUTPUT_ACTIVE);
}
return 0;
}
static int mcr20a_init(const struct device *dev)
{
const struct mcr20a_config *config = dev->config;
struct mcr20a_context *mcr20a = dev->data;
k_mutex_init(&mcr20a->phy_mutex);
k_sem_init(&mcr20a->isr_sem, 0, 1);
LOG_DBG("\nInitialize MCR20A Transceiver\n");
if (configure_gpios(dev) != 0) {
LOG_ERR("Configuring GPIOS failed");
return -EIO;
}
if (!spi_is_ready_dt(&config->bus)) {
LOG_ERR("Configuring SPI failed");
return -EIO;
}
LOG_DBG("GPIO and SPI configured");
if (power_on_and_setup(dev) != 0) {
LOG_ERR("Configuring MCR20A failed");
return -EIO;
}
k_thread_create(&mcr20a->mcr20a_rx_thread, mcr20a->mcr20a_rx_stack,
CONFIG_IEEE802154_MCR20A_RX_STACK_SIZE,
mcr20a_thread_main,
(void *)dev, NULL, NULL, K_PRIO_COOP(2), 0, K_NO_WAIT);
k_thread_name_set(&mcr20a->mcr20a_rx_thread, "mcr20a_rx");
return 0;
}
static void mcr20a_iface_init(struct net_if *iface)
{
const struct device *dev = net_if_get_device(iface);
struct mcr20a_context *mcr20a = dev->data;
uint8_t *mac = get_mac(dev);
net_if_set_link_addr(iface, mac, 8, NET_LINK_IEEE802154);
mcr20a->iface = iface;
ieee802154_init(iface);
LOG_DBG("done");
}
static const struct mcr20a_config mcr20a_config = {
.bus = SPI_DT_SPEC_INST_GET(0, SPI_WORD_SET(8), 0),
.irq_gpio = GPIO_DT_SPEC_INST_GET(0, irqb_gpios),
.reset_gpio = GPIO_DT_SPEC_INST_GET(0, reset_gpios),
};
static struct mcr20a_context mcr20a_context_data;
static const struct ieee802154_radio_api mcr20a_radio_api = {
.iface_api.init = mcr20a_iface_init,
.get_capabilities = mcr20a_get_capabilities,
.cca = mcr20a_cca,
.set_channel = mcr20a_set_channel,
.filter = mcr20a_filter,
.set_txpower = mcr20a_set_txpower,
.start = mcr20a_start,
.stop = mcr20a_stop,
.tx = mcr20a_tx,
.attr_get = mcr20a_attr_get,
};
#if defined(CONFIG_IEEE802154_RAW_MODE)
DEVICE_DT_INST_DEFINE(0, mcr20a_init, NULL, &mcr20a_context_data,
&mcr20a_config, POST_KERNEL,
CONFIG_IEEE802154_MCR20A_INIT_PRIO, &mcr20a_radio_api);
#else
NET_DEVICE_DT_INST_DEFINE(0, mcr20a_init, NULL, &mcr20a_context_data,
&mcr20a_config, CONFIG_IEEE802154_MCR20A_INIT_PRIO,
&mcr20a_radio_api, IEEE802154_L2,
NET_L2_GET_CTX_TYPE(IEEE802154_L2),
MCR20A_PSDU_LENGTH);
#endif
``` | /content/code_sandbox/drivers/ieee802154/ieee802154_mcr20a.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 11,336 |
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