text stringlengths 9 39.2M | dir stringlengths 26 295 | lang stringclasses 185
values | created_date timestamp[us] | updated_date timestamp[us] | repo_name stringlengths 1 97 | repo_full_name stringlengths 7 106 | star int64 1k 183k | len_tokens int64 1 13.8M |
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```c++
// Permission is hereby granted, free of charge, to any person obtaining a copy
// of this software and associated documentation files (the "Software"), to deal
// in the Software without restriction, including without limitation the rights
// to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
// copies of the Software, and to permit persons to whom the Software is
// furnished to do so, subject to the following conditions:
// The above copyright notice and this permission notice shall be included in
// all copies or substantial portions of the Software.
// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
// AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
// LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
// OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
// THE SOFTWARE.
#include <cmath> // For float std::abs(float).
#include <iostream>
#include <map>
#include "NativeJIT/CodeGen/ExecutionBuffer.h"
#include "NativeJIT/CodeGen/FunctionBuffer.h"
#include "NativeJIT/Function.h"
#include "TestSetup.h"
namespace NativeJIT
{
namespace BitFunnelAcceptanceTest
{
TEST_FIXTURE_START(Acceptance)
public:
Acceptance() : TestFixture(5000, 64 * 1024, TestFixture::c_defaultDiagnosticsStream)
{
}
protected:
static const unsigned c_bitsForAnchor = 4;
static const unsigned c_bitsForBody = 4;
static const unsigned c_bitsForTitle = 1;
static const unsigned c_bitsForUrl = 1;
static const unsigned c_bitsForPosition = 4;
static const unsigned c_bitsForShard = 4;
typedef Packed<c_bitsForAnchor, c_bitsForBody, c_bitsForTitle, c_bitsForUrl> TermFrequencies;
typedef Packed<c_bitsForAnchor, c_bitsForBody, c_bitsForTitle, c_bitsForUrl, c_bitsForPosition, c_bitsForShard> TermFeatures;
typedef Model<TermFeatures> TermModel;
typedef Packed<2> ClickFeature;
typedef Model<ClickFeature> ClickModel;
typedef Packed<1> BoolFeature;
typedef Model<BoolFeature> LanguageModel;
typedef Model<BoolFeature> LocationModel;
typedef uint64_t TermHash;
typedef uint64_t DocId;
typedef uint32_t Shard;
typedef uint32_t DocIndex;
struct MarketData
{
uint32_t m_languageHash;
uint32_t m_locationHash;
};
struct QueryContext
{
MarketData m_queryMarket;
};
typedef bool (*HashLookupFunc)(void const * buffer, unsigned slotCount, uint64_t key, uint64_t& value);
#pragma pack(push, 1)
struct WebDocData
{
float m_staticScore;
float m_advancedPreferScore;
MarketData m_documentMarket;
// Extracted from a metaword used to store the FILETIME of document's discovery.
uint64_t m_discoveryTimeTicks;
unsigned m_termSlotCount;
unsigned m_clickSlotCount;
};
#pragma pack(pop)
typedef unsigned FixedSizeBlobId;
typedef unsigned VariableSizeBlobId;
class DocumentHandle : NonCopyable
{
public:
DocumentHandle(std::map<FixedSizeBlobId, void*> const & fixedSizeBlobs,
std::map<VariableSizeBlobId, void*> const & variableSizeBlobs)
: m_fixedSizeBlobs(fixedSizeBlobs),
m_variableSizeBlobs(variableSizeBlobs)
{
}
// Note: at least in this test, the blobs are accessed through
// a function call instead of JITGetFixedSizeBlob() method
// creating a Node to do so.
void* GetFixedSizeBlob(FixedSizeBlobId blobId) const
{
auto blobIt = m_fixedSizeBlobs.find(blobId);
LogThrowAssert(blobIt != m_fixedSizeBlobs.end(),
"Unknown fixed size blob ID %u",
blobId);
return blobIt->second;
}
void* GetVariableSizeBlob(VariableSizeBlobId blobId) const
{
auto blobIt = m_variableSizeBlobs.find(blobId);
LogThrowAssert(blobIt != m_variableSizeBlobs.end(),
"Unknown variable size blob ID %u",
blobId);
return blobIt->second;
}
private:
std::map<FixedSizeBlobId, void*> const & m_fixedSizeBlobs;
std::map<VariableSizeBlobId, void*> const & m_variableSizeBlobs;
};
struct WebModelSetV1
{
LanguageModel* m_languageModel;
LocationModel* m_locationModel;
TermModel* m_termModel;
ClickModel* m_clickModel;
};
// The CommonRankerContext tries to simulate a scenario where
// the code is being compiled on MLA and executed on OS, so it
// tries to keep the size of the context fixed for compatibility.
struct CommonRankerContext
{
void* (*m_getFixedSizeBlobFunc)(DocumentHandle const * handle,
FixedSizeBlobId id);
void* (*m_getVariableSizeBlobFunc)(DocumentHandle const * handle,
VariableSizeBlobId id);
void* m_modelSet;
char m_fixedSizePadding[64 - 3 * sizeof(void*)];
};
static_assert(std::is_pod<CommonRankerContext>::value,
"CommonRankerContext must be a POD");
static_assert(sizeof(CommonRankerContext) == 64,
"CommonRankerContext must have a fixed size");
struct WebRankerContext
{
struct CommonRankerContext m_commonContext;
FixedSizeBlobId m_docDataBlobId;
VariableSizeBlobId m_termFreqTableBlobId;
VariableSizeBlobId m_clickFreqTableBlobId;
HashLookupFunc m_termLookupFunc;
HashLookupFunc m_clickLookupFunc;
};
static_assert(std::is_pod<WebRankerContext>::value,
"WebRankerContext must be a POD");
static const TermFrequencies c_defaultTermFrequencies;
// Creates term features out of frequencies and position and shard.
static TermFeatures MakeTermFeatures(TermFrequencies const & frequencies,
uint8_t position,
Shard shard)
{
return frequencies
.InsertRightmost<c_bitsForPosition>(position)
.InsertRightmost<c_bitsForShard>(shard);
}
// Some test constants.
static const TermHash c_redHash;
static const TermHash c_dogHash;
static const TermHash c_dogsHash;
static const TermHash c_houseHash;
static const TermHash c_housesHash;
static const float c_anyIdf1;
static const float c_anyIdf2;
static const float c_anyIdf3;
static const float c_anyIdf4;
// For click phrase bigram.
static const TermHash c_dogHouseHash = 0x5236264;
static const TermHash c_nonExistentPhraseHash = 0x3475897234;
static const unsigned c_expectedSlotCount = 0xC0DE;
// A single term anywhere inside the query (on its own, as a part of
// phrase, inside word: operator).
struct TermInfo
{
TermInfo(TermHash hash, float idf)
: m_hash(hash),
m_idf(idf)
{
}
TermHash m_hash;
float m_idf;
};
// Unigram ("dog"), bigram ("dog house") etc. to represent a single
// word or a multi-word phrase.
struct QueryNGram
{
QueryNGram(std::initializer_list<TermInfo> list)
: m_terms(list)
{
}
std::vector<TermInfo> m_terms;
};
// A query component at a certain position. A single n-gram represents
// a single word or a phrase, whereas multiple n-grams represent
// various candidates. For example, word:(ny "new york") is a query
// component with two n-grams: a unigram "ny" and a bigram "new york".
struct QueryComponent
{
QueryComponent(std::initializer_list<QueryNGram> list)
: m_candidates(list)
{
}
std::vector<QueryNGram> m_candidates;
};
// All the word components that make up a query from the scoring
// perspective.
struct QueryWords
{
QueryWords(std::initializer_list<QueryComponent> list)
: m_components(list)
{
}
std::vector<QueryComponent> m_components;
};
// A simple class to handle values that may or may not be provided.
template <typename T>
class Nullable
{
public:
Nullable()
: m_hasValue(false),
m_value()
{
}
Nullable(T const & value)
: m_hasValue(true),
m_value(value)
{
}
void Set(T const & value)
{
m_value = value;
m_hasValue = true;
}
bool HasValue() const
{
return m_hasValue;
}
T& Get()
{
LogThrowAssert(m_hasValue, "Cannot Get() null value");
return m_value;
}
T const & Get() const
{
LogThrowAssert(m_hasValue, "Cannot Get() null value");
return m_value;
}
private:
bool m_hasValue;
T m_value;
};
// A constant used in rangeconstraint: behavior simulation.
static const float c_discardedDocumentScore;
static const MarketData c_anyMarketData;
static const MarketData c_anyOtherMarketDataWithSameLanguage;
static const MarketData c_anyOtherFullyDifferentMarketData;
static const MarketData c_clickPhraseMarketData;
struct ParsedQuery
{
ParsedQuery(QueryWords const & queryWords, MarketData const & queryMarket)
: m_queryWords(queryWords),
m_queryMarket(queryMarket)
{
}
ParsedQuery& SetClickPhrase(TermHash clickPhrase)
{
m_clickPhrase.Set(clickPhrase);
return *this;
}
ParsedQuery& RequireDiscoveryTimeTicksLessThan(uint64_t value)
{
m_discoveryTimeTicksLessThanConstraint.Set(value);
return *this;
}
QueryWords m_queryWords;
MarketData m_queryMarket;
Nullable<TermHash> m_clickPhrase;
// Used in rangeconstraint operator simulation: if non-null then
// DocData::m_discoveryTimeTicks must match the constraint (its value
// must be lower than the value inside the nullable).
Nullable<uint64_t> m_discoveryTimeTicksLessThanConstraint;
};
// A class used to evaluate query words through the term model using
// the C++ constructs, to be compared against the NativeJIT version.
class TermEvaluationContextCPlusPlus : private NonCopyable
{
public:
TermEvaluationContextCPlusPlus(
WebRankerContext const * rankerContext,
TermModel* termModel,
WebDocData const * docData,
void const * termFreqTable,
Shard shard)
: m_termFreqTable(termFreqTable),
m_termSlotCount(docData->m_termSlotCount),
m_termLookupFunc(rankerContext->m_termLookupFunc),
m_termModel(termModel),
m_shard(shard)
{
}
float CalculateQueryWordsScore(QueryWords const & queryWords)
{
auto const & components = queryWords.m_components;
float score = 0;
for(uint8_t position = 0;
position < components.size();
++position)
{
float idf;
TermFrequencies frequencies
= EstimateQueryComponentFrequencyAndIDF(components[position],
idf);
TermFeatures termFeatures = MakeTermFeatures(frequencies, position, m_shard);
auto termModelScore = m_termModel->Apply(termFeatures);
score += termModelScore * idf;
}
return score;
}
private:
// Per-component aggregation of two TermFrequencies using the
// specified function.
TermFrequencies Aggregate(TermFrequencies f1ABTU,
TermFrequencies f2ABTU,
PackedUnderlyingType (*aggFunc)(PackedUnderlyingType,
PackedUnderlyingType))
{
auto anchor = aggFunc(f1ABTU.Leftmost(), f2ABTU.Leftmost());
auto f1BTU = f1ABTU.WithoutLeftmost();
auto f2BTU = f2ABTU.WithoutLeftmost();
auto body = aggFunc(f1BTU.Leftmost(), f2BTU.Leftmost());
auto f1TU = f1BTU.WithoutLeftmost();
auto f2TU = f2BTU.WithoutLeftmost();
auto title = aggFunc(f1TU.Leftmost(), f2TU.Leftmost());
auto f1U = f1TU.WithoutLeftmost();
auto f2U = f2TU.WithoutLeftmost();
auto url = aggFunc(f1U.Leftmost(), f2U.Leftmost());
return TermFrequencies::FromComponents(anchor, body, title, url);
}
TermFrequencies PackedMin(TermFrequencies f1ABTU, TermFrequencies f2ABTU)
{
return Aggregate(f1ABTU,
f2ABTU,
[](PackedUnderlyingType a, PackedUnderlyingType b)
{
return (std::min)(a, b);
});
}
TermFrequencies PackedMax(TermFrequencies f1ABTU, TermFrequencies f2ABTU)
{
return Aggregate(f1ABTU,
f2ABTU,
[](PackedUnderlyingType a, PackedUnderlyingType b)
{
return (std::max)(a, b);
});
}
TermFrequencies LookupTermFrequencies(TermHash termHash)
{
uint64_t termFrequenciesRaw;
const bool lookupSuccessful = m_termLookupFunc(m_termFreqTable,
m_termSlotCount,
termHash,
termFrequenciesRaw);
if (!lookupSuccessful)
{
termFrequenciesRaw = c_defaultTermFrequencies;
}
return TermFrequencies::FromBits(static_cast<PackedUnderlyingType>(termFrequenciesRaw));
}
TermFrequencies
EstimateNGramFrequencyAndIDF(QueryNGram const & nGram,
float & estimatedIdf)
{
auto const & termInfos = nGram.m_terms;
LogThrowAssert(termInfos.size() > 0, "Cannot process n-gram with zero words");
TermFrequencies currFrequencies = LookupTermFrequencies(termInfos[0].m_hash);
float currentIdf = termInfos[0].m_idf;
// See the Node version of this method for details about the
// logic.
for (unsigned i = 1; i < termInfos.size(); ++i)
{
TermFrequencies frequencies = LookupTermFrequencies(termInfos[i].m_hash);
currFrequencies = PackedMin(currFrequencies, frequencies);
currentIdf = (std::max)(currentIdf, termInfos[i].m_idf);
}
estimatedIdf = currentIdf;
return currFrequencies;
}
TermFrequencies
EstimateQueryComponentFrequencyAndIDF(QueryComponent const & component,
float & estimatedIdf)
{
auto const & candidates = component.m_candidates;
LogThrowAssert(candidates.size() > 0, "Cannot process an empty query component");
float currentIdf;
TermFrequencies currFrequencies
= EstimateNGramFrequencyAndIDF(candidates[0], currentIdf);
// See the Node version of this method for details about the
// logic.
for (unsigned i = 1; i < candidates.size(); ++i)
{
// Get the data for the current candidate.
float idf;
TermFrequencies frequencies
= EstimateNGramFrequencyAndIDF(candidates[i], idf);
currFrequencies = PackedMax(currFrequencies, frequencies);
currentIdf = (std::min)(currentIdf, idf);
}
estimatedIdf = currentIdf;
return currFrequencies;
}
void const * m_termFreqTable;
unsigned m_termSlotCount;
HashLookupFunc m_termLookupFunc;
TermModel const * m_termModel;
Shard m_shard;
};
static uint16_t ComputeClickHash(uint32_t queryLanguageHash,
uint32_t queryLocationHash,
TermHash clickPhrase)
{
const uint64_t lang64 = queryLanguageHash;
const uint64_t loc64 = queryLocationHash;
// (language64 | (location64 << 32)) + clickPhrase)
const uint64_t clickHash64
= (lang64 | (loc64 << 32)) + clickPhrase;
// Keep only the lowest 16 bits.
// Note: the original calculation uses % 65521 (the largest
// prime 16-bit number) to calculate the value.
return static_cast<uint16_t>(clickHash64);
}
static float GetClickPhraseScore(WebRankerContext const * rankerContext,
ClickModel* clickModel,
WebDocData const * docData,
void const * clickFreqTable,
uint32_t queryLanguageHash,
uint32_t queryLocationHash,
TermHash clickPhrase)
{
auto const clickHash = ComputeClickHash(queryLanguageHash,
queryLocationHash,
clickPhrase);
uint64_t clickFeatureRaw;
const bool lookupSuccessful
= rankerContext->m_clickLookupFunc(clickFreqTable,
docData->m_clickSlotCount,
clickHash,
clickFeatureRaw);
if (!lookupSuccessful)
{
clickFeatureRaw = 0;
}
auto clickFeature = ClickFeature::FromBits(static_cast<PackedUnderlyingType>(clickFeatureRaw));
return clickModel->Apply(clickFeature);
}
static float CalculateScore(ParsedQuery const & parsedQuery,
Shard shard,
DocumentHandle const * docHandle,
void const * rankerContextRaw,
QueryContext const * queryContext)
{
auto const rankerContext = static_cast<WebRankerContext const *>(rankerContextRaw);
auto & commonRankerContext = rankerContext->m_commonContext;
// Get WebDocData with static score and advance prefer score.
auto getFixedSizedBlobFunc = commonRankerContext.m_getFixedSizeBlobFunc;
auto docData = reinterpret_cast<WebDocData const *>(
getFixedSizedBlobFunc(docHandle, rankerContext->m_docDataBlobId));
// Check if the document should be discarded.
if (parsedQuery.m_discoveryTimeTicksLessThanConstraint.HasValue()
&& !(docData->m_discoveryTimeTicks
< parsedQuery.m_discoveryTimeTicksLessThanConstraint.Get()))
{
return c_discardedDocumentScore;
}
auto const * modelSet = reinterpret_cast<WebModelSetV1 const *>(commonRankerContext.m_modelSet);
// Initialize the score to the static score.
float totalScore = docData->m_staticScore;
// Get query and document language and compare them.
auto docLanguage = docData->m_documentMarket.m_languageHash;
auto queryLanguage = queryContext->m_queryMarket.m_languageHash;
const unsigned languageMatches = docLanguage == queryLanguage ? 1 : 0;
totalScore += modelSet->m_languageModel->Apply(BoolFeature::FromBits(languageMatches));
// Do the same for the location.
auto docLocation = docData->m_documentMarket.m_locationHash;
auto queryLocation = queryContext->m_queryMarket.m_locationHash;
const unsigned locationMatches = docLocation == queryLocation ? 1: 0;
totalScore += modelSet->m_locationModel->Apply(BoolFeature::FromBits(locationMatches));
// If both language and location match, use the advanced prefer score.
if (languageMatches && locationMatches)
{
totalScore += docData->m_advancedPreferScore;
}
auto getVarSizedBlobFunc = commonRankerContext.m_getVariableSizeBlobFunc;
auto & queryWords = parsedQuery.m_queryWords;
// Prepare to evaluate term and click models.
if (!queryWords.m_components.empty())
{
auto termHashTable = getVarSizedBlobFunc(docHandle, rankerContext->m_termFreqTableBlobId);
auto termModel = modelSet->m_termModel;
// Evaluate the term model.
TermEvaluationContextCPlusPlus termContext(rankerContext,
termModel,
docData,
termHashTable,
shard);
totalScore += termContext.CalculateQueryWordsScore(queryWords);
}
if (parsedQuery.m_clickPhrase.HasValue())
{
auto clickHashTable = getVarSizedBlobFunc(docHandle, rankerContext->m_clickFreqTableBlobId);
auto clickModel = modelSet->m_clickModel;
totalScore += GetClickPhraseScore(rankerContext,
clickModel,
docData,
clickHashTable,
queryLanguage,
queryLocation,
parsedQuery.m_clickPhrase.Get());
}
return totalScore;
}
// A class used to evaluate query words through the term model using
// the NativeJIT constructs, to be compared against the C++ version.
class TermEvaluationContextNativeJIT : private NonCopyable
{
public:
TermEvaluationContextNativeJIT(ExpressionNodeFactory& e,
Node<WebRankerContext const *>& rankerContext,
Node<TermModel*>& termModel,
Node<WebDocData const *>& docData,
Node<void const *>& termFreqTable,
Node<Shard>& shard)
: m_termFreqTable(termFreqTable),
m_termSlotCount(e.Deref(e.FieldPointer(docData, &WebDocData::m_termSlotCount))),
m_termLookupFunc(e.Deref(e.FieldPointer(rankerContext, &WebRankerContext::m_termLookupFunc))),
m_defaultTermFrequencies(e.Immediate(c_defaultTermFrequencies)),
m_termModel(termModel),
m_shardShiftedToMSB(e.Shl(e.Cast<PackedUnderlyingType>(shard),
static_cast<uint8_t>(sizeof(PackedUnderlyingType) * 8 - c_bitsForShard)))
{
}
Node<float>& AddQueryWordsScore(ExpressionNodeFactory& e,
QueryWords const & queryWords,
Node<float>& currentScore)
{
Node<float>* updatedScore = ¤tScore;
auto & components = queryWords.m_components;
for(uint8_t position = 0;
position < components.size();
++position)
{
float idf;
auto & frequencies
= EstimateQueryComponentFrequencyAndIDF(e,
components[position],
idf);
auto & termFeatures = GetTermFeatures(e,
frequencies,
position);
auto & termModelScore = e.ApplyModel(m_termModel, termFeatures);
auto & componentScore = e.Mul(termModelScore, e.Immediate(idf));
updatedScore = &e.Add(*updatedScore, componentScore);
}
return *updatedScore;
}
private:
// Given a term hash, lookup the corresponding term frequencies
// from the hash table.
Node<TermFrequencies>& LookupTermFrequencies(ExpressionNodeFactory& e,
TermHash term)
{
auto & termFrequenciesRaw = e.StackVariable<uint64_t>();
auto & termHash = e.Immediate(term);
auto & termLookupSuccessful = e.Call(m_termLookupFunc,
m_termFreqTable,
m_termSlotCount,
termHash,
termFrequenciesRaw);
auto & dereferencedRawFrequencies
= e.Dependent(e.Deref(termFrequenciesRaw),
termLookupSuccessful);
auto & termFrequencies = e.If(termLookupSuccessful,
e.Cast<TermFrequencies>(dereferencedRawFrequencies),
m_defaultTermFrequencies);
return termFrequencies;
}
Node<TermFeatures>& GetTermFeatures(ExpressionNodeFactory& e,
Node<TermFrequencies>& frequencies,
uint8_t position)
{
const PackedUnderlyingType positionShiftedToMSB
= static_cast<PackedUnderlyingType>(position) << (sizeof(PackedUnderlyingType) * 8 - c_bitsForPosition);
// Shift the position from the MSB position into the
// LSB position in the target variable.
auto & frequenciesAndShard
= e.Shld(e.Cast<PackedUnderlyingType>(frequencies),
e.Immediate(positionShiftedToMSB),
c_bitsForPosition);
// Do the same for shard to finalize the full term features.
auto & rawTermFeatures
= e.Shld(frequenciesAndShard,
m_shardShiftedToMSB,
c_bitsForShard);
return e.Cast<TermFeatures>(rawTermFeatures);
}
Node<TermFrequencies>&
EstimateNGramFrequencyAndIDF(ExpressionNodeFactory& e,
QueryNGram const & nGram,
float & estimatedIdf)
{
auto & termInfos = nGram.m_terms;
LogThrowAssert(termInfos.size() > 0, "Cannot process n-gram with zero words");
Node<TermFrequencies>* currFrequencies
= &LookupTermFrequencies(e, termInfos[0].m_hash);
float currentIdf = termInfos[0].m_idf;
for (unsigned i = 1; i < termInfos.size(); ++i)
{
// The "word1 word2" phrase can appear at most min(word1AppearanceCount,
// word2AppearanceCount) times in the document.
auto & frequencies = LookupTermFrequencies(e, termInfos[i].m_hash);
currFrequencies = &e.PackedMin(*currFrequencies, frequencies);
// IDF is a measure of term's value with regard to its unambiguity - if
// a term is rare (and thus its IDF is high) then the search is more
// specific and the term adds more value to it.
// A phrase search is more specific and thus has more value than each
// of the terms on their own. That value is approximated by taking a
// maximum of the two IDFs.
currentIdf = (std::max)(currentIdf, termInfos[i].m_idf);
}
estimatedIdf = currentIdf;
return *currFrequencies;
}
Node<TermFrequencies>&
EstimateQueryComponentFrequencyAndIDF(ExpressionNodeFactory& e,
QueryComponent const & component,
float & estimatedIdf)
{
auto & candidates = component.m_candidates;
LogThrowAssert(candidates.size() > 0, "Cannot process an empty query component");
float currentIdf;
Node<TermFrequencies>* currFrequencies
= &EstimateNGramFrequencyAndIDF(e,
candidates[0],
currentIdf);
for (unsigned i = 1; i < candidates.size(); ++i)
{
// Get the data for the current candidate.
float idf;
auto & frequencies = EstimateNGramFrequencyAndIDF(e,
candidates[i],
idf);
// Use a maximum of the two term's frequencies as term frequency for
// word candidates. Note: the sum of the frequencies may seem like
// a better fit but it is a bit more complicated to calculate when term
// frequencies are log conditioned and also experiments show almost
// nonexistent relevance difference when it is used.
currFrequencies = &e.PackedMax(*currFrequencies, frequencies);
// IDF is a measure of term's value with regard to its unambiguity - if
// a term is rare (and thus its IDF is high) then the search is more
// specific and the term adds more value to it.
// A search with word candidates is less specific and thus has less
// value than each of the terms on their own. That value is approximated
// by taking a minimum of the two IDFs.
currentIdf = (std::min)(currentIdf, idf);
}
estimatedIdf = currentIdf;
return *currFrequencies;
}
Node<void const *>& m_termFreqTable;
Node<unsigned>& m_termSlotCount;
Node<HashLookupFunc>& m_termLookupFunc;
Node<TermFrequencies>& m_defaultTermFrequencies;
Node<TermModel*>& m_termModel;
Node<PackedUnderlyingType>& m_shardShiftedToMSB;
};
Node<uint16_t>& ComputeClickHash(
ExpressionNodeFactory& e,
Node<uint32_t>& queryLanguageHash,
Node<uint32_t>& queryLocationHash,
TermHash clickPhrase)
{
auto & lang64 = e.Cast<uint64_t>(queryLanguageHash);
auto & loc64 = e.Cast<uint64_t>(queryLocationHash);
// (language64 | (location64 << 32)) + clickPhrase)
auto & clickHash64 = e.Add(e.Or(lang64,
e.Shl(loc64, static_cast<uint8_t>(32))),
e.Immediate(clickPhrase));
// Keep only the lowest 16 bits.
// Note: the original calculation uses % 65521 (the largest
// prime 16-bit number) to calculate the value.
return e.Cast<uint16_t>(clickHash64);
}
Node<float>&
GetClickPhraseScore(ExpressionNodeFactory& e,
Node<WebRankerContext const *>& rankerContext,
Node<ClickModel*>& clickModel,
Node<WebDocData const *>& docData,
Node<void const *>& clickFreqTable,
Node<uint32_t>& queryLanguageHash,
Node<uint32_t>& queryLocationHash,
TermHash clickPhrase)
{
auto & clickHash = ComputeClickHash(e, queryLanguageHash, queryLocationHash, clickPhrase);
auto & clickFeatureRaw = e.StackVariable<uint64_t>();
auto & clickLookupSuccessful = e.Call(e.Deref(e.FieldPointer(rankerContext, &WebRankerContext::m_clickLookupFunc)),
clickFreqTable,
e.Deref(e.FieldPointer(docData, &WebDocData::m_clickSlotCount)),
e.Cast<uint64_t>(clickHash),
clickFeatureRaw);
auto & dereferencedRawFeature
= e.Dependent(e.Deref(clickFeatureRaw),
clickLookupSuccessful);
auto & clickFeature = e.If(clickLookupSuccessful,
e.Cast<ClickFeature>(dereferencedRawFeature),
e.Immediate(ClickFeature::FromBits(0)));
return e.ApplyModel(clickModel, clickFeature);
}
typedef float (*ScoringFunction)(Shard, DocumentHandle const *, void const *, QueryContext const *);
ScoringFunction
BuildAndCompileScoringFunction(ParsedQuery const & parsedQuery,
TestCaseSetup& setup)
{
Function<float, Shard, DocumentHandle const *, void const *, QueryContext const *>
e(setup.GetAllocator(), setup.GetCode());
auto & shard = e.GetP1();
auto & docHandle = e.GetP2();
auto & rankerContext = e.Cast<WebRankerContext const *>(e.GetP3());
auto & queryContext = e.GetP4();
auto & commonRankerContext = e.FieldPointer(rankerContext, &WebRankerContext::m_commonContext);
auto & modelSet = e.Cast<WebModelSetV1 const *>(e.Deref(e.FieldPointer(commonRankerContext, &CommonRankerContext::m_modelSet)));
auto & floatZero = e.Immediate<float>(0);
// Get WebDocData with static score and advance prefer score.
auto & getFixedSizedBlobFunc = e.Deref(e.FieldPointer(commonRankerContext, &CommonRankerContext::m_getFixedSizeBlobFunc));
auto & docDataBlobId = e.Deref(e.FieldPointer(rankerContext, &WebRankerContext::m_docDataBlobId));
auto & docData = e.Cast<WebDocData const *>(e.Call(getFixedSizedBlobFunc, docHandle, docDataBlobId));
// Initialize the score to the static score.
auto & staticScore = e.Deref(e.FieldPointer(docData, &WebDocData::m_staticScore));
auto totalScore = &staticScore;
// Get query and document market.
auto & docMarket = e.FieldPointer(docData, &WebDocData::m_documentMarket);
auto & queryMarket = e.FieldPointer(queryContext, &QueryContext::m_queryMarket);
// Get query and document language and compare them.
auto & docLanguage = e.Deref(e.FieldPointer(docMarket, &MarketData::m_languageHash));
auto & queryLanguage = e.Deref(e.FieldPointer(queryMarket, &MarketData::m_languageHash));
auto & languageMatches = e.Compare<JccType::JE>(docLanguage, queryLanguage);
auto & languageModel = e.Deref(e.FieldPointer(modelSet, &WebModelSetV1::m_languageModel));
// Evaluate the language model.
totalScore = &e.Add(*totalScore,
e.ApplyModel(languageModel,
e.Cast<BoolFeature>(e.Cast<PackedUnderlyingType>(languageMatches))));
// Do the same for the location.
auto & docLocation = e.Deref(e.FieldPointer(docMarket, &MarketData::m_locationHash));
auto & queryLocation = e.Deref(e.FieldPointer(queryMarket, &MarketData::m_locationHash));
auto & locationMatches = e.Compare<JccType::JE>(docLocation, queryLocation);
auto & locationModel = e.Deref(e.FieldPointer(modelSet, &WebModelSetV1::m_locationModel));
totalScore = &e.Add(*totalScore,
e.ApplyModel(locationModel,
e.Cast<BoolFeature>(e.Cast<PackedUnderlyingType>(locationMatches))));
// If both language and location match, add the advanced prefer score.
auto & marketMatches = e.And(languageMatches, locationMatches);
auto & advPreferScore = e.Deref(e.FieldPointer(docData, &WebDocData::m_advancedPreferScore));
totalScore = &e.Add(*totalScore,
e.If(marketMatches, advPreferScore, floatZero));
auto & queryWords = parsedQuery.m_queryWords;
// Prepare to evaluate term and click models.
if (!queryWords.m_components.empty()
|| parsedQuery.m_clickPhrase.HasValue())
{
auto & getVarSizedBlobFunc = e.Deref(e.FieldPointer(commonRankerContext, &CommonRankerContext::m_getVariableSizeBlobFunc));
if (!queryWords.m_components.empty())
{
auto & termFreqTableBlobId = e.Deref(e.FieldPointer(rankerContext, &WebRankerContext::m_termFreqTableBlobId));
auto & termHashTable = e.Call(getVarSizedBlobFunc, docHandle, termFreqTableBlobId);
auto & termModel = e.Deref(e.FieldPointer(modelSet, &WebModelSetV1::m_termModel));
// Evaluate the term model.
TermEvaluationContextNativeJIT termContext(e,
rankerContext,
termModel,
docData,
e.AddTargetConstCast(termHashTable),
shard);
totalScore = &termContext.AddQueryWordsScore(e,
queryWords,
*totalScore);
}
if (parsedQuery.m_clickPhrase.HasValue())
{
auto & clickFreqTableBlobId = e.Deref(e.FieldPointer(rankerContext, &WebRankerContext::m_clickFreqTableBlobId));
auto & clickHashTable = e.Call(getVarSizedBlobFunc, docHandle, clickFreqTableBlobId);
auto & clickModel = e.Deref(e.FieldPointer(modelSet, &WebModelSetV1::m_clickModel));
totalScore = &e.Add(*totalScore,
GetClickPhraseScore(e,
rankerContext,
clickModel,
docData,
e.AddTargetConstCast(clickHashTable),
queryLanguage,
queryLocation,
parsedQuery.m_clickPhrase.Get()));
}
}
// If there's a discovery ticks constraint, the expression should
// only be evaluated if discovery ticks are below the constraint,
// otherwise a constant value will be returned.
if (parsedQuery.m_discoveryTimeTicksLessThanConstraint.HasValue())
{
auto & discoveryTicks = e.Deref(e.FieldPointer(docData, &WebDocData::m_discoveryTimeTicks));
e.AddExecuteOnlyIfStatement(e.Compare<JccType::JB>(discoveryTicks,
e.Immediate(parsedQuery.m_discoveryTimeTicksLessThanConstraint.Get())),
e.Immediate(c_discardedDocumentScore));
}
return e.Compile(*totalScore);
}
struct DocumentDescriptor : NonCopyable
{
DocumentDescriptor(MarketData const & docMarket)
: m_documentMarket(docMarket),
m_discoveryTimeTicks(0)
{
}
DocumentDescriptor& SetDiscoveryTimeTicks(uint64_t value)
{
m_discoveryTimeTicks = value;
return *this;
}
const MarketData m_documentMarket;
uint64_t m_discoveryTimeTicks;
};
struct TestData
{
TestData(DocumentDescriptor const & docDescriptor,
ParsedQuery const & parsedQuery)
: m_shard(3),
m_docHandle(m_fixedSizeBlobs, m_variableSizeBlobs)
{
m_termFreqMap[c_redHash] = TermFrequencies::FromComponents(4, 3, 1, 1);
// c_dogHash not placed into the map to signify a trivial term.
m_termFreqMap[c_dogsHash] = TermFrequencies::FromComponents(2, 3, 0, 1);
m_termFreqMap[c_houseHash] = TermFrequencies::FromComponents(0, 2, 0, 0);
m_termFreqMap[c_housesHash] = TermFrequencies::FromComponents(1, 2, 1, 0);
auto const clickHash
= ComputeClickHash(c_clickPhraseMarketData.m_languageHash,
c_clickPhraseMarketData.m_locationHash,
c_dogHouseHash);
m_clickFreqMap[clickHash] = ClickFeature::FromBits(2);
m_docData.m_staticScore = 5.7f;
m_docData.m_advancedPreferScore = 1.3f;
m_docData.m_documentMarket = docDescriptor.m_documentMarket;
m_docData.m_discoveryTimeTicks = docDescriptor.m_discoveryTimeTicks;
m_docData.m_termSlotCount = c_expectedSlotCount;
m_docData.m_clickSlotCount = c_expectedSlotCount;
m_modelSet.m_clickModel = &m_clickModel;
m_modelSet.m_languageModel = &m_languageModel;
m_modelSet.m_locationModel = &m_locationModel;
m_modelSet.m_termModel = &m_termModel;
m_fixedSizeBlobs[c_docDataBlobId] = &m_docData;
m_variableSizeBlobs[c_termFreqTableBlobId] = &m_termFreqMap;
m_variableSizeBlobs[c_clickFreqTableBlobId] = &m_clickFreqMap;
m_rankerContext.m_commonContext.m_getFixedSizeBlobFunc = &GetFixedSizeBlobFunc;
m_rankerContext.m_commonContext.m_getVariableSizeBlobFunc = &GetVariableSizeBlobFunc;
m_rankerContext.m_commonContext.m_modelSet = &m_modelSet;
m_rankerContext.m_docDataBlobId = c_docDataBlobId;
m_rankerContext.m_termFreqTableBlobId = c_termFreqTableBlobId;
m_rankerContext.m_clickFreqTableBlobId = c_clickFreqTableBlobId;
m_rankerContext.m_termLookupFunc = &HashLookupFunc<TermFrequencies>;
m_rankerContext.m_clickLookupFunc = &HashLookupFunc<ClickFeature>;
m_queryContext.m_queryMarket = parsedQuery.m_queryMarket;
InitModel(m_languageModel, 0.37f, 0.72f);
InitModel(m_locationModel, 0.12f, 0.05f);
InitModel(m_clickModel, 1.23f, 0.26f);
InitModel(m_termModel, 1, 0.01f);
}
const Shard m_shard;
DocumentHandle m_docHandle;
WebRankerContext m_rankerContext;
QueryContext m_queryContext;
private:
FixedSizeBlobId c_docDataBlobId = 2;
VariableSizeBlobId c_termFreqTableBlobId = 5;
VariableSizeBlobId c_clickFreqTableBlobId = 6;
WebDocData m_docData;
LanguageModel m_languageModel;
LocationModel m_locationModel;
TermModel m_termModel;
ClickModel m_clickModel;
WebModelSetV1 m_modelSet;
std::map<FixedSizeBlobId, void*> m_fixedSizeBlobs;
std::map<VariableSizeBlobId, void*> m_variableSizeBlobs;
std::map<uint64_t, TermFrequencies> m_termFreqMap;
std::map<uint64_t, ClickFeature> m_clickFreqMap;
static void* GetFixedSizeBlobFunc(DocumentHandle const * handle,
FixedSizeBlobId id)
{
return handle->GetFixedSizeBlob(id);
}
static void* GetVariableSizeBlobFunc(DocumentHandle const * handle,
VariableSizeBlobId id)
{
return handle->GetVariableSizeBlob(id);
}
template <typename VALUE>
static bool HashLookupFunc(void const * buffer,
unsigned slotCount,
uint64_t key,
uint64_t& value)
{
LogThrowAssert(c_expectedSlotCount == slotCount,
"Mismatched slot count, %u vs %u",
c_expectedSlotCount,
slotCount);
auto map = reinterpret_cast<std::map<uint64_t, VALUE> const *>(buffer);
auto it = map->find(key);
bool found = it != map->end();
if (found)
{
value = it->second;
}
return found;
}
template <typename T>
static void InitModel(T& model, float startValue, float stepValue)
{
float currValue = startValue;
for (unsigned i = 0; i < T::c_size; ++i)
{
model[i] = currValue;
currValue += stepValue;
}
}
};
void RunTestCase(DocumentDescriptor const & docDescriptor,
ParsedQuery const & parsedQuery)
{
auto setup = GetSetup();
{
ASSERT_EQ(0u, offsetof(WebRankerContext, m_commonContext))
<< "Invalid WebRankerContext structure layout";
// TestData is large, allocate from heap to avoid stack overflow.
auto testData = std::make_unique<TestData>(docDescriptor, parsedQuery);
auto expected = CalculateScore(parsedQuery,
testData->m_shard,
&testData->m_docHandle,
&testData->m_rankerContext.m_commonContext,
&testData->m_queryContext);
auto function = BuildAndCompileScoringFunction(parsedQuery, *setup);
auto actual = function(testData->m_shard,
&testData->m_docHandle,
&testData->m_rankerContext.m_commonContext,
&testData->m_queryContext);
ASSERT_TRUE(std::abs(actual - expected) < 0.0001) <<
"Expected score: " << expected << " Actual score: " << actual;
}
}
TEST_FIXTURE_END_TEST_CASES_BEGIN
TEST_F(Acceptance, SingleWord)
{
// house
QueryWords queryWords
{
{
QueryComponent
{
QueryNGram { TermInfo(c_houseHash, c_anyIdf2) }
}
}
};
const MarketData market = c_anyMarketData;
DocumentDescriptor docDescriptor(market);
ParsedQuery query(queryWords, market);
RunTestCase(docDescriptor, query);
}
TEST_F(Acceptance, MultipleWords)
{
// red dog house
QueryWords queryWords
{
{
QueryComponent
{
QueryNGram { TermInfo(c_redHash, c_anyIdf1) }
},
QueryComponent
{
QueryNGram { TermInfo(c_dogHash, c_anyIdf2) }
},
QueryComponent
{
QueryNGram { TermInfo(c_houseHash, c_anyIdf3) }
}
}
};
const MarketData market = c_anyMarketData;
DocumentDescriptor docDescriptor(market);
ParsedQuery query(queryWords, market);
RunTestCase(docDescriptor, query);
}
TEST_F(Acceptance, Phrase)
{
// red "dog house"
QueryWords queryWords
{
{
QueryComponent
{
QueryNGram { TermInfo(c_redHash, c_anyIdf1) }
},
QueryComponent
{
QueryNGram
{
TermInfo(c_dogHash, c_anyIdf1),
TermInfo(c_houseHash, c_anyIdf2)
}
}
}
};
const MarketData market = c_anyMarketData;
DocumentDescriptor docDescriptor(market);
ParsedQuery query(queryWords, market);
RunTestCase(docDescriptor, query);
}
TEST_F(Acceptance, WordCandidates)
{
// red word:("dog house" houses)
QueryWords queryWords
{
{
QueryComponent
{
QueryNGram { TermInfo(c_redHash, c_anyIdf4) },
},
QueryComponent
{
QueryNGram
{
TermInfo(c_dogHash, c_anyIdf1),
TermInfo(c_houseHash, c_anyIdf3)
},
QueryNGram { TermInfo(c_housesHash, c_anyIdf4) }
}
}
};
const MarketData market = c_anyMarketData;
DocumentDescriptor docDescriptor(market);
ParsedQuery query(queryWords, market);
RunTestCase(docDescriptor, query);
}
TEST_F(Acceptance, ClickPhrase)
{
QueryWords queryWords
{
{
QueryComponent
{
QueryNGram { TermInfo(c_dogHash, c_anyIdf1) },
QueryNGram { TermInfo(c_dogsHash, c_anyIdf2) }
},
QueryComponent
{
QueryNGram { TermInfo(c_houseHash, c_anyIdf3) },
}
}
};
DocumentDescriptor docDescriptor(c_anyMarketData);
// Click phrase in the click table.
{
ParsedQuery query(queryWords, c_clickPhraseMarketData);
query.SetClickPhrase(c_dogHouseHash);
RunTestCase(docDescriptor, query);
}
// Click phrase not in the click table.
{
ParsedQuery query(queryWords, c_clickPhraseMarketData);
query.SetClickPhrase(c_nonExistentPhraseHash);
RunTestCase(docDescriptor, query);
}
}
TEST_F(Acceptance, ConstraintDiscard)
{
QueryWords queryWords
{
{
QueryComponent
{
QueryNGram { TermInfo(c_houseHash, c_anyIdf2) }
}
}
};
const MarketData market = c_anyMarketData;
ParsedQuery query(queryWords, market);
query.RequireDiscoveryTimeTicksLessThan(10);
// The following document should not be discarded.
{
DocumentDescriptor docDescriptorNoDiscard(market);
docDescriptorNoDiscard.SetDiscoveryTimeTicks(9);
RunTestCase(docDescriptorNoDiscard, query);
}
// The following document should be discarded.
{
DocumentDescriptor docDescriptorDiscard(market);
docDescriptorDiscard.SetDiscoveryTimeTicks(10);
RunTestCase(docDescriptorDiscard, query);
}
}
TEST_F(Acceptance, CompletelyDifferentMarket)
{
QueryWords queryWords
{
{
QueryComponent
{
QueryNGram { TermInfo(c_houseHash, c_anyIdf2) }
}
}
};
DocumentDescriptor docDescriptor(c_anyMarketData);
ParsedQuery query(queryWords, c_anyOtherFullyDifferentMarketData);
RunTestCase(docDescriptor, query);
}
TEST_F(Acceptance, DifferentMarketWithSameLanguage)
{
QueryWords queryWords
{
{
QueryComponent
{
QueryNGram { TermInfo(c_houseHash, c_anyIdf2) }
}
}
};
DocumentDescriptor docDescriptor(c_anyMarketData);
ParsedQuery query(queryWords, c_anyOtherMarketDataWithSameLanguage);
RunTestCase(docDescriptor, query);
}
TEST_CASES_END
const Acceptance::TermFrequencies Acceptance::c_defaultTermFrequencies = Acceptance::TermFrequencies::FromComponents(0, 1, 0, 0);
const float Acceptance::c_discardedDocumentScore = std::numeric_limits<float>::lowest();
const Acceptance::MarketData Acceptance::c_anyMarketData = {0x01234567, 0x11112222};
const Acceptance::MarketData Acceptance::c_anyOtherMarketDataWithSameLanguage = {0x01234567, 0x22222222};
const Acceptance::MarketData Acceptance::c_anyOtherFullyDifferentMarketData = {0x89ABCDEF, 0x33334444};
const Acceptance::MarketData Acceptance::c_clickPhraseMarketData = {0xC11CC, 0xDA7ADA7A};
const uint64_t Acceptance::c_redHash = 0x54342434;
const uint64_t Acceptance::c_dogHash = 0x1233333333;
const uint64_t Acceptance::c_dogsHash = 0x1255555555;
const uint64_t Acceptance::c_houseHash = 0x23444444444;
const uint64_t Acceptance::c_housesHash = 0x2500000001;
const float Acceptance::c_anyIdf1 = 0.1f;
const float Acceptance::c_anyIdf2 = 0.23f;
const float Acceptance::c_anyIdf3 = 0.67f;
const float Acceptance::c_anyIdf4 = 1.5f;
}
}
``` | /content/code_sandbox/test/NativeJIT/BitFunnelAcceptanceTest.cpp | c++ | 2016-04-09T23:53:19 | 2024-06-29T07:05:56 | NativeJIT | BitFunnel/NativeJIT | 1,133 | 11,029 |
```c++
// Permission is hereby granted, free of charge, to any person obtaining a copy
// of this software and associated documentation files (the "Software"), to deal
// in the Software without restriction, including without limitation the rights
// to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
// copies of the Software, and to permit persons to whom the Software is
// furnished to do so, subject to the following conditions:
// The above copyright notice and this permission notice shall be included in
// all copies or substantial portions of the Software.
// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
// AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
// LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
// OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
// THE SOFTWARE.
#include <iostream>
#include "NativeJIT/CodeGen/ExecutionBuffer.h"
#include "NativeJIT/CodeGen/FunctionBuffer.h"
#include "NativeJIT/Function.h"
#include "TestSetup.h"
namespace NativeJIT
{
namespace CastUnitTest
{
TEST_FIXTURE_START(CastTest)
protected:
template <typename FROM>
void TestCasts(FROM testValue)
{
TestCast<int8_t>(testValue);
TestCast<int16_t>(testValue);
TestCast<int32_t>(testValue);
TestCast<int64_t>(testValue);
TestCast<uint8_t>(testValue);
TestCast<uint16_t>(testValue);
TestCast<uint32_t>(testValue);
TestCast<uint64_t>(testValue);
TestCast<float>(testValue);
TestCast<double>(testValue);
}
template <typename TO, typename FROM>
void TestCast(FROM testValue)
{
TestCastImmediate<TO>(testValue);
TestCastDirect<TO>(testValue);
TestCastIndirect<TO>(testValue);
}
template <typename TO, typename FROM>
void TestCastImmediate(FROM testValue)
{
auto setup = GetSetup();
Function<TO> expression(setup->GetAllocator(), setup->GetCode());
auto & immediate = expression.Immediate(testValue);
auto & cast = expression.template Cast<TO>(immediate);
auto function = expression.Compile(cast);
auto expected = ForcedCast<TO>(testValue);
auto observed = function();
ASSERT_EQ(expected, observed)
<< "Incorrect cast from "
<< typeid(FROM).name()
<< " to "
<< typeid(TO).name();
}
template <typename TO, typename FROM>
void TestCastDirect(FROM testValue)
{
auto setup = GetSetup();
Function<TO, FROM> expression(setup->GetAllocator(), setup->GetCode());
auto & cast = expression.template Cast<TO>(expression.GetP1());
auto function = expression.Compile(cast);
auto expected = ForcedCast<TO>(testValue);
auto observed = function(testValue);
ASSERT_EQ(expected, observed)
<< "Incorrect cast from "
<< typeid(FROM).name()
<< " to "
<< typeid(TO).name();
}
template <typename TO, typename FROM>
void TestCastIndirect(FROM testValue)
{
auto setup = GetSetup();
struct TestInput
{
void* m_dummy;
FROM m_value;
};
TestInput input = { nullptr, testValue };
Function<TO, TestInput*> expression(setup->GetAllocator(), setup->GetCode());
auto & valueField = expression.FieldPointer(expression.GetP1(),
&TestInput::m_value);
auto & from = expression.Deref(valueField);
auto & cast = expression.template Cast<TO>(from);
auto function = expression.Compile(cast);
auto expected = ForcedCast<TO>(testValue);
auto observed = function(&input);
ASSERT_EQ(expected, observed)
<< "Incorrect cast from "
<< typeid(FROM).name()
<< " to "
<< typeid(TO).name();
}
// Dummy function, to test casting from/to function pointers.
static uint64_t DummyFunc(uint64_t x)
{
return x * 2;
}
TEST_FIXTURE_END_TEST_CASES_BEGIN
// A no-op test which ensures that the type returned by
// Add/RemoveTargetConstCast is correct by getting compiled.
TEST_F(CastTest, TargetCast)
{
auto setup = GetSetup();
Function<void const *, void*> add(setup->GetAllocator(), setup->GetCode());
add.Return(add.AddTargetConstCast(add.GetP1()));
Function<void*, void const *> rem(setup->GetAllocator(), setup->GetCode());
rem.Return(rem.RemoveTargetConstCast(rem.GetP1()));
}
TEST_F(CastTest, ConstCastNonReference)
{
auto setup = GetSetup();
Function<int const, int> add(setup->GetAllocator(), setup->GetCode());
add.Return(add.AddConstCast(add.GetP1()));
Function<int, int const> rem(setup->GetAllocator(), setup->GetCode());
rem.Return(rem.RemoveConstCast(rem.GetP1()));
}
TEST_F(CastTest, ConstCastReference)
{
auto setup = GetSetup();
Function<int const &, int &> add(setup->GetAllocator(), setup->GetCode());
add.Return(add.AddConstCast(add.GetP1()));
Function<int &, int const &> rem(setup->GetAllocator(), setup->GetCode());
rem.Return(rem.RemoveConstCast<int const &>(rem.GetP1()));
}
TEST_F(CastTest, FromInt8)
{
TestCasts<int8_t>(-1);
TestCasts<uint8_t>(0xFF);
}
TEST_F(CastTest, FromInt16)
{
TestCasts<int16_t>(-1);
TestCasts<uint16_t>(0xFFFF);
}
TEST_F(CastTest, FromInt32)
{
TestCasts<int32_t>(-1);
TestCasts<uint32_t>(0xFFFFFFFF);
}
TEST_F(CastTest, FromInt64)
{
TestCasts<int64_t>(-1);
TestCasts<uint64_t>(0xFFFFFFFFFFFFFFFFul);
}
TEST_F(CastTest, FromFloat)
{
TestCasts<float>(-123.7f);
TestCasts<float>(123.7f);
// Special case, target is an UInt64 that has the MSB bit set.
TestCast<uint64_t>(static_cast<float>(0xA000000000000000));
}
TEST_F(CastTest, FromDouble)
{
TestCasts<double>(-123.7);
TestCasts<double>(123.7);
// Special case, target is an UInt64 that has the MSB bit set.
TestCast<uint64_t>(static_cast<double>(0xA000000000000000));
}
TEST_F(CastTest, Packed)
{
auto packed = Packed<3, 4, 5>::FromComponents(7, 15, 31);
TestCast<PackedUnderlyingType, decltype(packed)>(packed);
TestCast<decltype(packed), PackedUnderlyingType>(123456);
}
TEST_F(CastTest, VoidPointer)
{
TestCast<uint64_t, void*>(this);
}
TEST_F(CastTest, FuncPointer)
{
auto funcPtr = &DummyFunc;
TestCast<decltype(funcPtr), void*>(reinterpret_cast<void*>(funcPtr));
}
TEST_CASES_END
}
}
``` | /content/code_sandbox/test/NativeJIT/CastTest.cpp | c++ | 2016-04-09T23:53:19 | 2024-06-29T07:05:56 | NativeJIT | BitFunnel/NativeJIT | 1,133 | 1,691 |
```c++
// Permission is hereby granted, free of charge, to any person obtaining a copy
// of this software and associated documentation files (the "Software"), to deal
// in the Software without restriction, including without limitation the rights
// to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
// copies of the Software, and to permit persons to whom the Software is
// furnished to do so, subject to the following conditions:
// The above copyright notice and this permission notice shall be included in
// all copies or substantial portions of the Software.
// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
// AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
// LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
// OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
// THE SOFTWARE.
#include <iostream>
#include "NativeJIT/CodeGen/ExecutionBuffer.h"
#include "NativeJIT/CodeGen/FunctionBuffer.h"
#include "NativeJIT/Function.h"
#include "TestSetup.h"
namespace NativeJIT
{
namespace ExpressionTreeUnitTest
{
template <typename T>
using DirectRegister = typename Storage<T>::DirectRegister;
template <typename T>
using BaseRegister = typename Storage<T>::BaseRegister;
#define AssertSizeAndType(REG_TYPE, EXPECTED_SIZE, EXPECTED_IS_FLOAT) \
static_assert(REG_TYPE::c_size == EXPECTED_SIZE, #REG_TYPE " should require " #EXPECTED_SIZE " bytes"); \
static_assert(REG_TYPE::c_isFloat == EXPECTED_IS_FLOAT, "IsFloat property for " #REG_TYPE " should be " #EXPECTED_IS_FLOAT)
// These tests can only fail during compilation, never during runtime.
TEST(ExpressionTreeBasic, StorageDefinition)
{
struct SmallerThanQuadword
{
uint8_t m_x1;
uint8_t m_x2;
};
struct LargerThanQuadword
{
uint64_t m_x1;
uint16_t m_x2;
};
// Direct register for primitive and small types.
AssertSizeAndType(DirectRegister<char>, 1, false);
AssertSizeAndType(DirectRegister<const char>, 1, false);
AssertSizeAndType(DirectRegister<uint64_t>, 8, false);
AssertSizeAndType(DirectRegister<float>, 4, true);
AssertSizeAndType(DirectRegister<double>, 8, true);
AssertSizeAndType(DirectRegister<const float>, 4, true);
AssertSizeAndType(DirectRegister<SmallerThanQuadword>, 2, false);
// Direct register for pointers.
AssertSizeAndType(DirectRegister<char*>, 8, false);
AssertSizeAndType(DirectRegister<char const *>, 8, false);
AssertSizeAndType(DirectRegister<char const * const>, 8, false);
AssertSizeAndType(DirectRegister<void*>, 8, false);
AssertSizeAndType(DirectRegister<float*>, 8, false);
AssertSizeAndType(DirectRegister<double*>, 8, false);
// Direct register for references.
AssertSizeAndType(DirectRegister<char&>, 8, false);
AssertSizeAndType(DirectRegister<const char&>, 8, false);
AssertSizeAndType(DirectRegister<float &>, 8, false);
// Direct register for arrays.
AssertSizeAndType(DirectRegister<int[1024]>, 8, false);
AssertSizeAndType(DirectRegister<float[1024]>, 8, false);
// Direct register for structures larger than quadword.
AssertSizeAndType(DirectRegister<LargerThanQuadword>, 8, false);
// Base register for various types.
AssertSizeAndType(BaseRegister<char>, 8, false);
AssertSizeAndType(BaseRegister<uint64_t>, 8, false);
AssertSizeAndType(BaseRegister<float>, 8, false);
AssertSizeAndType(BaseRegister<float[1024]>, 8, false);
}
#undef AssertSizeAndType
#define AssertImmediateCategory(TYPE, EXPECTED_CATEGORY) \
static_assert(ImmediateCategoryOf<TYPE>::value == EXPECTED_CATEGORY, \
#TYPE " should be in " #EXPECTED_CATEGORY)
TEST(ExpressionTreeBasic, ImmediateTypes)
{
AssertImmediateCategory(void, ImmediateCategory::NonImmediate);
AssertImmediateCategory(char, ImmediateCategory::InlineImmediate);
AssertImmediateCategory(const char, ImmediateCategory::InlineImmediate);
AssertImmediateCategory(int32_t, ImmediateCategory::InlineImmediate);
AssertImmediateCategory(uint32_t, ImmediateCategory::InlineImmediate);
AssertImmediateCategory(uint64_t, ImmediateCategory::RIPRelativeImmediate);
AssertImmediateCategory(float, ImmediateCategory::RIPRelativeImmediate);
AssertImmediateCategory(double, ImmediateCategory::RIPRelativeImmediate);
AssertImmediateCategory(void*, ImmediateCategory::RIPRelativeImmediate);
AssertImmediateCategory(void(*)(int), ImmediateCategory::RIPRelativeImmediate);
// These decay to pointers when passed as arguments.
typedef char ArrayLargerThanQuadword[123];
struct StructLargerThanQuadword { ArrayLargerThanQuadword m_x;};
AssertImmediateCategory(ArrayLargerThanQuadword, ImmediateCategory::RIPRelativeImmediate);
AssertImmediateCategory(StructLargerThanQuadword, ImmediateCategory::RIPRelativeImmediate);
}
#undef AssertImmediateCategory
TEST_FIXTURE_START(ExpressionTree)
TEST_FIXTURE_END_TEST_CASES_BEGIN
// Verify that the sole owner of an indirect storage will reuse the
// base register for the direct register after dereferencing.
TEST_F(ExpressionTree, BaseRegisterReuse)
{
auto setup = GetSetup();
ExpressionNodeFactory e(setup->GetAllocator(), setup->GetCode());
// Create indirect storage to reference an integer.
struct Test { int m_dummy; };
Test testStruct;
auto & structNode = e.Immediate(&testStruct);
auto & indirectNode = e.Deref(e.FieldPointer(structNode, &Test::m_dummy));
indirectNode.IncrementParentCount();
structNode.CodeGenCache(e);
indirectNode.CodeGenCache(e);
auto storage = indirectNode.CodeGen(e);
auto baseRegister = storage.GetBaseRegister();
ASSERT_TRUE(storage.ConvertToDirect(false).IsSameHardwareRegister(baseRegister));
}
// Verify that the sole owner will not reuse the base register in
// cases when it's not possible (floating point value, reserved
// base pointer, RIP relative addressing).
TEST_F(ExpressionTree, NoBaseRegisterReuseRIPRelative)
{
auto setup = GetSetup();
ExpressionNodeFactory e(setup->GetAllocator(), setup->GetCode());
auto storage = e.RIPRelative<int>(16);
ASSERT_TRUE(storage.GetBaseRegister().IsRIP());
ASSERT_FALSE(storage.ConvertToDirect(false).IsRIP());
}
TEST_F(ExpressionTree, NoBaseRegisterReuseBasePointer)
{
auto setup = GetSetup();
ExpressionNodeFactory e(setup->GetAllocator(), setup->GetCode());
auto storage = e.Temporary<int>();
auto baseRegister = storage.GetBaseRegister();
ASSERT_FALSE(storage.ConvertToDirect(false).IsSameHardwareRegister(baseRegister));
}
TEST_F(ExpressionTree, NoBaseRegisterReuseFloat)
{
auto setup = GetSetup();
ExpressionNodeFactory e(setup->GetAllocator(), setup->GetCode());
// Create indirect storage to reference a float.
struct Test { float m_dummy; };
Test testStruct;
auto & structNode = e.Immediate(&testStruct);
auto & indirectNode = e.Deref(e.FieldPointer(structNode, &Test::m_dummy));
indirectNode.IncrementParentCount();
structNode.CodeGenCache(e);
indirectNode.CodeGenCache(e);
auto storage = indirectNode.CodeGen(e);
auto baseRegister = storage.GetBaseRegister();
ASSERT_FALSE(storage.ConvertToDirect(false).IsSameHardwareRegister(baseRegister));
}
// Make sure that expression tree allows multiple references to
// the reserved base pointers.
TEST_F(ExpressionTree, MultipleReferencesToBasePointer)
{
auto setup = GetSetup();
ExpressionNodeFactory e(setup->GetAllocator(), setup->GetCode());
auto temp1 = e.Temporary<int>();
auto temp2 = e.Temporary<int>();
ASSERT_EQ(temp1.GetBaseRegister(), temp2.GetBaseRegister());
ASSERT_NE(temp1.GetOffset(), temp2.GetOffset());
}
TEST_F(ExpressionTree, MultipleReferencesToRIP)
{
auto setup = GetSetup();
ExpressionNodeFactory e(setup->GetAllocator(), setup->GetCode());
auto temp1 = e.RIPRelative<int>(0);
auto temp2 = e.RIPRelative<int>(16);
ASSERT_TRUE(temp1.GetBaseRegister().IsRIP());
ASSERT_EQ(temp1.GetBaseRegister(), temp2.GetBaseRegister());
}
TEST_F(ExpressionTree, ReferenceCounter)
{
unsigned count = 0;
ReferenceCounter ref1(count);
ASSERT_EQ(1u, count);
ReferenceCounter ref2(count);
ASSERT_EQ(2u, count);
ReferenceCounter ref3;
ASSERT_EQ(2u, count);
ref3 = ref2;
ASSERT_EQ(3u, count);
ref3.Reset();
ASSERT_EQ(2u, count);
ref2 = ReferenceCounter();
ASSERT_EQ(1u, count);
ref1.Reset();
ASSERT_EQ(0u, count);
}
TEST_F(ExpressionTree, RegisterSpillingInteger)
{
auto setup = GetSetup();
ExpressionNodeFactory e(setup->GetAllocator(), setup->GetCode());
std::vector<Storage<int>> storages;
const unsigned totalRegisterCount = RegisterBase::c_maxIntegerRegisterID + 1;
// Try to obtain totalRegisterCount direct registers.
for (unsigned i = 0; i < totalRegisterCount; ++i)
{
storages.push_back(e.Direct<int>());
ASSERT_EQ(storages.back().GetStorageClass(), StorageClass::Direct);
}
// There won't be enough registers for all storages to stay
// direct since reserved base pointers can't be obtained. Thus,
// some of the storages should have their registers spilled.
// Three reserved registers are RBP, RSP and RIP. Note: this
// assumes that RBP is a base register - if RSP is used instead
// of RBP, the test will need to be adjusted.
// Alternatively, ExpressionTree::IsAnyBaseRegister could be
// made accessible and used to count the reserved registers.
const unsigned reservedRegisterCount = 3;
unsigned directCount = 0;
unsigned indirectCount = 0;
unsigned indexOfFirstDirect = 0;
for (unsigned i = 0; i < storages.size(); ++i)
{
if (storages[i].GetStorageClass() == StorageClass::Direct)
{
directCount++;
if (directCount == 1)
{
indexOfFirstDirect = i;
}
}
else
{
indirectCount++;
}
}
// Most storages should be direct, some corresponding to the
// reserved registers should not.
ASSERT_EQ(totalRegisterCount - reservedRegisterCount, directCount);
ASSERT_EQ(reservedRegisterCount, indirectCount);
// A new direct storage should cause the oldest reserved register
// to be spilled (note: this assumes current allocation strategy).
ASSERT_EQ(storages[indexOfFirstDirect].GetStorageClass(), StorageClass::Direct);
Storage<int> spillTrigger = e.Direct<int>();
ASSERT_EQ(spillTrigger.GetStorageClass(), StorageClass::Direct);
ASSERT_EQ(storages[indexOfFirstDirect].GetStorageClass(), StorageClass::Indirect);
}
TEST_F(ExpressionTree, RegisterSpillingFloat)
{
auto setup = GetSetup();
ExpressionNodeFactory e(setup->GetAllocator(), setup->GetCode());
std::vector<Storage<float>> storages;
const unsigned totalRegisterCount = RegisterBase::c_maxFloatRegisterID + 1;
// Try to obtain totalRegisterCount direct registers.
for (unsigned i = 0; i < totalRegisterCount; ++i)
{
storages.push_back(e.Direct<float>());
ASSERT_EQ(storages.back().GetStorageClass(), StorageClass::Direct);
}
// There are no reserved registers for floats, so no register
// should have been bumped.
for (auto const & s : storages)
{
ASSERT_EQ(s.GetStorageClass(), StorageClass::Direct);
}
// A new direct storage should cause the oldest reserved register
// to be spilled (note: this assumes current allocation strategy).
Storage<float> spillTrigger = e.Direct<float>();
ASSERT_EQ(spillTrigger.GetStorageClass(), StorageClass::Direct);
ASSERT_EQ(storages[0].GetStorageClass(), StorageClass::Indirect);
Storage<float> spillTrigger2 = e.Direct<float>();
ASSERT_EQ(spillTrigger2.GetStorageClass(), StorageClass::Direct);
ASSERT_EQ(storages[1].GetStorageClass(), StorageClass::Indirect);
// Make sure that a released register will be used for a new
// direct rather than spilling storages[2] for it.
ASSERT_EQ(storages[2].GetStorageClass(), StorageClass::Direct);
spillTrigger2.Reset();
spillTrigger2 = e.Direct<float>();
ASSERT_EQ(storages[2].GetStorageClass(), StorageClass::Direct);
}
template <typename T>
void TestRegisterPinning(TestCaseSetup& setup)
{
ExpressionNodeFactory e(setup.GetAllocator(), setup.GetCode());
// Get a direct register and pin it.
Storage<T> storage = e.Direct<T>();
ReferenceCounter pin = storage.GetPin();
auto reg = storage.GetDirectRegister();
// Attempt to obtain that specific register should now fail.
try
{
e.Direct<T>(reg);
FAIL() << "It should not have been possible to obtain a pinned register";
}
catch (std::exception const & e)
{
std::string msg = e.what();
ASSERT_TRUE(msg.find("Attempted to obtain the pinned register") !=
std::string::npos) <<
"Unexpected exception received";
}
catch (...)
{
FAIL() << "Unexpected exception type";
}
// Unpin the register and try obtaining it again (should succceed now).
pin.Reset();
Storage<T> storage2 = e.Direct<T>(reg);
// The new storage should own the register, the old not should not.
ASSERT_EQ(storage2.GetStorageClass(), StorageClass::Direct);
ASSERT_EQ(storage2.GetDirectRegister(), reg);
ASSERT_FALSE((storage.GetStorageClass() == StorageClass::Direct
&& storage.GetDirectRegister() == reg));
}
TEST_F(ExpressionTree, RegisterPinning)
{
auto setup = GetSetup();
TestRegisterPinning<int>(*setup);
TestRegisterPinning<float>(*setup);
}
TEST_F(ExpressionTree, SoleDataOwner)
{
auto setup = GetSetup();
ExpressionNodeFactory e(setup->GetAllocator(), setup->GetCode());
Storage<int> empty;
ASSERT_TRUE(empty.IsSoleDataOwner());
auto s = e.Direct<int>();
ASSERT_TRUE(s.IsSoleDataOwner());
auto s2 = s;
ASSERT_FALSE(s.IsSoleDataOwner());
ASSERT_FALSE(s2.IsSoleDataOwner());
s2.Reset();
ASSERT_TRUE(s.IsSoleDataOwner());
ASSERT_TRUE(s2.IsSoleDataOwner());
// Different indirects that refer to stack are sole owners of their storage.
auto stack1 = e.Temporary<int>();
ASSERT_TRUE(stack1.IsSoleDataOwner());
auto stack2 = e.Temporary<int>();
ASSERT_TRUE(stack2.IsSoleDataOwner());
}
TEST_F(ExpressionTree, TakeSoleOwnershipOfDirect)
{
auto setup = GetSetup();
ExpressionNodeFactory e(setup->GetAllocator(), setup->GetCode());
auto s = e.Direct<int>(eax);
ASSERT_TRUE(s.IsSoleDataOwner());
ASSERT_EQ(s.GetStorageClass(), StorageClass::Direct);
ASSERT_EQ(s.GetDirectRegister(), eax);
auto s2 = s;
ASSERT_FALSE(s.IsSoleDataOwner());
ASSERT_FALSE(s2.IsSoleDataOwner());
ASSERT_EQ(s2.GetStorageClass(), StorageClass::Direct);
ASSERT_EQ(s2.GetDirectRegister(), eax);
s.TakeSoleOwnershipOfDirect();
ASSERT_TRUE(s.IsSoleDataOwner());
ASSERT_EQ(s.GetStorageClass(), StorageClass::Direct);
ASSERT_EQ(s.GetDirectRegister(), eax);
ASSERT_TRUE(s2.IsSoleDataOwner());
ASSERT_EQ(s2.GetStorageClass(), StorageClass::Direct);
// ASSERT_NE(s2.GetDirectRegister(), eax); Doesn't compile!
ASSERT_FALSE((s2.GetDirectRegister() == eax));
}
TEST_CASES_END
}
}
``` | /content/code_sandbox/test/NativeJIT/ExpressionTreeTest.cpp | c++ | 2016-04-09T23:53:19 | 2024-06-29T07:05:56 | NativeJIT | BitFunnel/NativeJIT | 1,133 | 3,695 |
```c++
// Permission is hereby granted, free of charge, to any person obtaining a copy
// of this software and associated documentation files (the "Software"), to deal
// in the Software without restriction, including without limitation the rights
// to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
// copies of the Software, and to permit persons to whom the Software is
// furnished to do so, subject to the following conditions:
// The above copyright notice and this permission notice shall be included in
// all copies or substantial portions of the Software.
// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
// AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
// LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
// OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
// THE SOFTWARE.
#include "NativeJIT/CodeGen/ExecutionBuffer.h"
#include "NativeJIT/CodeGen/FunctionBuffer.h"
#include "NativeJIT/Function.h"
#include "TestSetup.h"
namespace NativeJIT
{
namespace PackedUnitTest
{
TEST_FIXTURE_START(PackedTest)
protected:
typedef Packed<3, 4, 5> PackedType;
PackedType MakePacked(uint8_t threeBitValue,
uint8_t fourBitValue,
uint8_t fiveBitValue)
{
return PackedType::FromComponents(threeBitValue, fourBitValue, fiveBitValue);
}
TEST_FIXTURE_END_TEST_CASES_BEGIN
TEST_F(PackedTest, Basic)
{
auto setup = GetSetup();
{
// Initialization from bits.
const auto packed1FromBits = Packed<8>::FromBits(0xE0);
const auto packed2FromBits = Packed<4, 8>::FromBits(0x2E0);
ASSERT_EQ(0xE0u, packed1FromBits.m_bits);
ASSERT_EQ(0x2E0u, packed2FromBits.m_bits);
// Operations on a single-component packed.
const auto packed1 = Packed<8>::FromComponents(0xE0);
static_assert(1 == packed1.c_componentCount, "Invalid component count");
static_assert(8 == packed1.c_totalBitCount, "Invalid total bit count");
static_assert(8 == packed1.c_leftmostBitCount, "Invalid leftmost bit count");
static_assert(8 == packed1.c_rightmostBitCount, "Invalid rightmost bit count");
ASSERT_EQ(0xE0u, packed1.m_bits);
ASSERT_EQ(0xE0u, packed1.Leftmost());
ASSERT_EQ(0xE0u, packed1.Rightmost());
// No WithoutLeftmost() operation available.
ASSERT_EQ(0x1E0u, packed1.InsertLeftmost<4>(0x1).m_bits);
ASSERT_EQ(0xE03u, packed1.InsertRightmost<4>(0x3).m_bits);
// Operations on two-component packed.
const auto packed2 = Packed<4, 8>::FromComponents(0x2, 0xE0);
static_assert(2 == packed2.c_componentCount, "Invalid component count");
static_assert(12 == packed2.c_totalBitCount, "Invalid total bit count");
static_assert(4 == packed2.c_leftmostBitCount, "Invalid leftmost bit count");
static_assert(8 == packed2.c_rightmostBitCount, "Invalid rightmost bit count");
ASSERT_EQ(0x2E0u, packed2.m_bits);
ASSERT_EQ(0x2u, packed2.Leftmost());
ASSERT_EQ(0xE0u, packed2.Rightmost());
ASSERT_EQ(0xE0u, packed2.WithoutLeftmost());
ASSERT_EQ(0x12E0u, packed2.InsertLeftmost<4>(0x1).m_bits);
ASSERT_EQ(0x2E01u, packed2.InsertRightmost<4>(0x1).m_bits);
}
}
TEST_F(PackedTest, ModelApply)
{
auto setup = GetSetup();
{
typedef Model<PackedType> ModelType;
Function<float, ModelType*, PackedType> expression(setup->GetAllocator(), setup->GetCode());
auto & a = expression.ApplyModel(expression.GetP1(), expression.GetP2());
auto function = expression.Compile(a);
ModelType model;
auto packed = MakePacked(7, 6, 5);
auto expected = model.Apply(packed);
auto observed = function(&model, packed);
ASSERT_EQ(observed, expected);
}
}
TEST_F(PackedTest, PackedMax)
{
auto setup = GetSetup();
PackedType packed1 = MakePacked((1 << 3) - 1, 1, (1 << 5) - 1);
PackedType packed2 = MakePacked(1, (1 << 4) - 1, 1);
PackedType expected = MakePacked((1 << 3) - 1, (1 << 4) - 1, (1 << 5) - 1);
Function<PackedType, PackedType, PackedType> expression(setup->GetAllocator(), setup->GetCode());
auto & a = expression.PackedMax(expression.GetP1(), expression.GetP2());;
auto function = expression.Compile(a);
auto observed = function(packed1, packed2);
ASSERT_EQ(expected.m_bits, observed.m_bits);
}
TEST_F(PackedTest, PackedMin)
{
auto setup = GetSetup();
PackedType packed1 = MakePacked((1 << 3) - 1, 1, (1 << 5) - 1);
PackedType packed2 = MakePacked(1, (1 << 4) - 1, 1);
PackedType expected = MakePacked(1, 1, 1);
Function<PackedType, PackedType, PackedType> expression(setup->GetAllocator(), setup->GetCode());
auto & a = expression.PackedMin(expression.GetP1(), expression.GetP2());;
auto function = expression.Compile(a);
auto observed = function(packed1, packed2);
ASSERT_EQ(expected.m_bits, observed.m_bits);
}
TEST_CASES_END
}
}
``` | /content/code_sandbox/test/NativeJIT/PackedTest.cpp | c++ | 2016-04-09T23:53:19 | 2024-06-29T07:05:56 | NativeJIT | BitFunnel/NativeJIT | 1,133 | 1,420 |
```c++
// Permission is hereby granted, free of charge, to any person obtaining a copy
// of this software and associated documentation files (the "Software"), to deal
// in the Software without restriction, including without limitation the rights
// to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
// copies of the Software, and to permit persons to whom the Software is
// furnished to do so, subject to the following conditions:
// The above copyright notice and this permission notice shall be included in
// all copies or substantial portions of the Software.
// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
// AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
// LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
// OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
// THE SOFTWARE.
// Auto generated from CondTest.go. Do not modify directly.
#include "NativeJIT/CodeGen/ExecutionBuffer.h"
#include "NativeJIT/CodeGen/FunctionBuffer.h"
#include "NativeJIT/Function.h"
#include "TestSetup.h"
namespace NativeJIT
{
namespace ConditionalUnitTest
{
TEST_FIXTURE_START(ConditionalAutoGen)
TEST_FIXTURE_END_TEST_CASES_BEGIN
TEST_F(ConditionalAutoGen, AutoGenJGSigned)
{
auto setup = GetSetup();
{
Function<uint64_t, uint64_t, uint64_t> expression(setup->GetAllocator(), setup->GetCode());
uint64_t trueValue = 1;
uint64_t falseValue = 128;
auto & a = expression.Compare<JccType::JG>(expression.GetP1(), expression.GetP2());
auto & b = expression.Conditional(a, expression.Immediate(trueValue), expression.Immediate(falseValue));
auto function = expression.Compile(b);
for (int64_t p1 = -1; p1 <= 1; ++p1) {
for (int64_t p2 = -1; p2 <= 1; ++p2) {
auto expected = (p1 > p2) ? trueValue : falseValue;
auto observed = function(p1, p2);
ASSERT_EQ(expected, observed);
}
}
}
}
TEST_F(ConditionalAutoGen, AutoGenJZUnsigned)
{
auto setup = GetSetup();
{
Function<uint64_t, uint64_t, uint64_t> expression(setup->GetAllocator(), setup->GetCode());
uint64_t trueValue = 1;
uint64_t falseValue = 128;
auto & a = expression.Compare<JccType::JZ>(expression.GetP1(), expression.GetP2());
auto & b = expression.Conditional(a, expression.Immediate(trueValue), expression.Immediate(falseValue));
auto function = expression.Compile(b);
for (uint64_t p1 = 0; p1 <= 1; ++p1) {
for (uint64_t p2 = 0; p2 <= 1; ++p2) {
auto expected = (p1 == p2) ? trueValue : falseValue;
auto observed = function(p1, p2);
ASSERT_EQ(expected, observed);
}
}
}
}
TEST_F(ConditionalAutoGen, AutoGenJZSigned)
{
auto setup = GetSetup();
{
Function<uint64_t, uint64_t, uint64_t> expression(setup->GetAllocator(), setup->GetCode());
uint64_t trueValue = 1;
uint64_t falseValue = 128;
auto & a = expression.Compare<JccType::JZ>(expression.GetP1(), expression.GetP2());
auto & b = expression.Conditional(a, expression.Immediate(trueValue), expression.Immediate(falseValue));
auto function = expression.Compile(b);
for (int64_t p1 = -1; p1 <= 1; ++p1) {
for (int64_t p2 = -1; p2 <= 1; ++p2) {
auto expected = (p1 == p2) ? trueValue : falseValue;
auto observed = function(p1, p2);
ASSERT_EQ(expected, observed);
}
}
}
}
TEST_F(ConditionalAutoGen, AutoGenJBUnsigned)
{
auto setup = GetSetup();
{
Function<uint64_t, uint64_t, uint64_t> expression(setup->GetAllocator(), setup->GetCode());
uint64_t trueValue = 1;
uint64_t falseValue = 128;
auto & a = expression.Compare<JccType::JB>(expression.GetP1(), expression.GetP2());
auto & b = expression.Conditional(a, expression.Immediate(trueValue), expression.Immediate(falseValue));
auto function = expression.Compile(b);
for (uint64_t p1 = 0; p1 <= 1; ++p1) {
for (uint64_t p2 = 0; p2 <= 1; ++p2) {
auto expected = (p1 < p2) ? trueValue : falseValue;
auto observed = function(p1, p2);
ASSERT_EQ(expected, observed);
}
}
}
}
TEST_F(ConditionalAutoGen, AutoGenJNBEUnsigned)
{
auto setup = GetSetup();
{
Function<uint64_t, uint64_t, uint64_t> expression(setup->GetAllocator(), setup->GetCode());
uint64_t trueValue = 1;
uint64_t falseValue = 128;
auto & a = expression.Compare<JccType::JNBE>(expression.GetP1(), expression.GetP2());
auto & b = expression.Conditional(a, expression.Immediate(trueValue), expression.Immediate(falseValue));
auto function = expression.Compile(b);
for (uint64_t p1 = 0; p1 <= 1; ++p1) {
for (uint64_t p2 = 0; p2 <= 1; ++p2) {
auto expected = (p1 > p2) ? trueValue : falseValue;
auto observed = function(p1, p2);
ASSERT_EQ(expected, observed);
}
}
}
}
TEST_F(ConditionalAutoGen, AutoGenJGESigned)
{
auto setup = GetSetup();
{
Function<uint64_t, uint64_t, uint64_t> expression(setup->GetAllocator(), setup->GetCode());
uint64_t trueValue = 1;
uint64_t falseValue = 128;
auto & a = expression.Compare<JccType::JGE>(expression.GetP1(), expression.GetP2());
auto & b = expression.Conditional(a, expression.Immediate(trueValue), expression.Immediate(falseValue));
auto function = expression.Compile(b);
for (int64_t p1 = -1; p1 <= 1; ++p1) {
for (int64_t p2 = -1; p2 <= 1; ++p2) {
auto expected = (p1 >= p2) ? trueValue : falseValue;
auto observed = function(p1, p2);
ASSERT_EQ(expected, observed);
}
}
}
}
TEST_F(ConditionalAutoGen, AutoGenJLESigned)
{
auto setup = GetSetup();
{
Function<uint64_t, uint64_t, uint64_t> expression(setup->GetAllocator(), setup->GetCode());
uint64_t trueValue = 1;
uint64_t falseValue = 128;
auto & a = expression.Compare<JccType::JLE>(expression.GetP1(), expression.GetP2());
auto & b = expression.Conditional(a, expression.Immediate(trueValue), expression.Immediate(falseValue));
auto function = expression.Compile(b);
for (int64_t p1 = -1; p1 <= 1; ++p1) {
for (int64_t p2 = -1; p2 <= 1; ++p2) {
auto expected = (p1 <= p2) ? trueValue : falseValue;
auto observed = function(p1, p2);
ASSERT_EQ(expected, observed);
}
}
}
}
TEST_F(ConditionalAutoGen, AutoGenJNGSigned)
{
auto setup = GetSetup();
{
Function<uint64_t, uint64_t, uint64_t> expression(setup->GetAllocator(), setup->GetCode());
uint64_t trueValue = 1;
uint64_t falseValue = 128;
auto & a = expression.Compare<JccType::JNG>(expression.GetP1(), expression.GetP2());
auto & b = expression.Conditional(a, expression.Immediate(trueValue), expression.Immediate(falseValue));
auto function = expression.Compile(b);
for (int64_t p1 = -1; p1 <= 1; ++p1) {
for (int64_t p2 = -1; p2 <= 1; ++p2) {
auto expected = (p1 <= p2) ? trueValue : falseValue;
auto observed = function(p1, p2);
ASSERT_EQ(expected, observed);
}
}
}
}
TEST_F(ConditionalAutoGen, AutoGenJNLESigned)
{
auto setup = GetSetup();
{
Function<uint64_t, uint64_t, uint64_t> expression(setup->GetAllocator(), setup->GetCode());
uint64_t trueValue = 1;
uint64_t falseValue = 128;
auto & a = expression.Compare<JccType::JNLE>(expression.GetP1(), expression.GetP2());
auto & b = expression.Conditional(a, expression.Immediate(trueValue), expression.Immediate(falseValue));
auto function = expression.Compile(b);
for (int64_t p1 = -1; p1 <= 1; ++p1) {
for (int64_t p2 = -1; p2 <= 1; ++p2) {
auto expected = (p1 > p2) ? trueValue : falseValue;
auto observed = function(p1, p2);
ASSERT_EQ(expected, observed);
}
}
}
}
TEST_F(ConditionalAutoGen, AutoGenJNZUnsigned)
{
auto setup = GetSetup();
{
Function<uint64_t, uint64_t, uint64_t> expression(setup->GetAllocator(), setup->GetCode());
uint64_t trueValue = 1;
uint64_t falseValue = 128;
auto & a = expression.Compare<JccType::JNZ>(expression.GetP1(), expression.GetP2());
auto & b = expression.Conditional(a, expression.Immediate(trueValue), expression.Immediate(falseValue));
auto function = expression.Compile(b);
for (uint64_t p1 = 0; p1 <= 1; ++p1) {
for (uint64_t p2 = 0; p2 <= 1; ++p2) {
auto expected = (p1 != p2) ? trueValue : falseValue;
auto observed = function(p1, p2);
ASSERT_EQ(expected, observed);
}
}
}
}
TEST_F(ConditionalAutoGen, AutoGenJNZSigned)
{
auto setup = GetSetup();
{
Function<uint64_t, uint64_t, uint64_t> expression(setup->GetAllocator(), setup->GetCode());
uint64_t trueValue = 1;
uint64_t falseValue = 128;
auto & a = expression.Compare<JccType::JNZ>(expression.GetP1(), expression.GetP2());
auto & b = expression.Conditional(a, expression.Immediate(trueValue), expression.Immediate(falseValue));
auto function = expression.Compile(b);
for (int64_t p1 = -1; p1 <= 1; ++p1) {
for (int64_t p2 = -1; p2 <= 1; ++p2) {
auto expected = (p1 != p2) ? trueValue : falseValue;
auto observed = function(p1, p2);
ASSERT_EQ(expected, observed);
}
}
}
}
TEST_F(ConditionalAutoGen, AutoGenJNAUnsigned)
{
auto setup = GetSetup();
{
Function<uint64_t, uint64_t, uint64_t> expression(setup->GetAllocator(), setup->GetCode());
uint64_t trueValue = 1;
uint64_t falseValue = 128;
auto & a = expression.Compare<JccType::JNA>(expression.GetP1(), expression.GetP2());
auto & b = expression.Conditional(a, expression.Immediate(trueValue), expression.Immediate(falseValue));
auto function = expression.Compile(b);
for (uint64_t p1 = 0; p1 <= 1; ++p1) {
for (uint64_t p2 = 0; p2 <= 1; ++p2) {
auto expected = (p1 <= p2) ? trueValue : falseValue;
auto observed = function(p1, p2);
ASSERT_EQ(expected, observed);
}
}
}
}
TEST_F(ConditionalAutoGen, AutoGenJNGESigned)
{
auto setup = GetSetup();
{
Function<uint64_t, uint64_t, uint64_t> expression(setup->GetAllocator(), setup->GetCode());
uint64_t trueValue = 1;
uint64_t falseValue = 128;
auto & a = expression.Compare<JccType::JNGE>(expression.GetP1(), expression.GetP2());
auto & b = expression.Conditional(a, expression.Immediate(trueValue), expression.Immediate(falseValue));
auto function = expression.Compile(b);
for (int64_t p1 = -1; p1 <= 1; ++p1) {
for (int64_t p2 = -1; p2 <= 1; ++p2) {
auto expected = (p1 < p2) ? trueValue : falseValue;
auto observed = function(p1, p2);
ASSERT_EQ(expected, observed);
}
}
}
}
TEST_F(ConditionalAutoGen, AutoGenJBEUnsigned)
{
auto setup = GetSetup();
{
Function<uint64_t, uint64_t, uint64_t> expression(setup->GetAllocator(), setup->GetCode());
uint64_t trueValue = 1;
uint64_t falseValue = 128;
auto & a = expression.Compare<JccType::JBE>(expression.GetP1(), expression.GetP2());
auto & b = expression.Conditional(a, expression.Immediate(trueValue), expression.Immediate(falseValue));
auto function = expression.Compile(b);
for (uint64_t p1 = 0; p1 <= 1; ++p1) {
for (uint64_t p2 = 0; p2 <= 1; ++p2) {
auto expected = (p1 <= p2) ? trueValue : falseValue;
auto observed = function(p1, p2);
ASSERT_EQ(expected, observed);
}
}
}
}
TEST_F(ConditionalAutoGen, AutoGenJAUnsigned)
{
auto setup = GetSetup();
{
Function<uint64_t, uint64_t, uint64_t> expression(setup->GetAllocator(), setup->GetCode());
uint64_t trueValue = 1;
uint64_t falseValue = 128;
auto & a = expression.Compare<JccType::JA>(expression.GetP1(), expression.GetP2());
auto & b = expression.Conditional(a, expression.Immediate(trueValue), expression.Immediate(falseValue));
auto function = expression.Compile(b);
for (uint64_t p1 = 0; p1 <= 1; ++p1) {
for (uint64_t p2 = 0; p2 <= 1; ++p2) {
auto expected = (p1 > p2) ? trueValue : falseValue;
auto observed = function(p1, p2);
ASSERT_EQ(expected, observed);
}
}
}
}
TEST_F(ConditionalAutoGen, AutoGenJLSigned)
{
auto setup = GetSetup();
{
Function<uint64_t, uint64_t, uint64_t> expression(setup->GetAllocator(), setup->GetCode());
uint64_t trueValue = 1;
uint64_t falseValue = 128;
auto & a = expression.Compare<JccType::JL>(expression.GetP1(), expression.GetP2());
auto & b = expression.Conditional(a, expression.Immediate(trueValue), expression.Immediate(falseValue));
auto function = expression.Compile(b);
for (int64_t p1 = -1; p1 <= 1; ++p1) {
for (int64_t p2 = -1; p2 <= 1; ++p2) {
auto expected = (p1 < p2) ? trueValue : falseValue;
auto observed = function(p1, p2);
ASSERT_EQ(expected, observed);
}
}
}
}
TEST_F(ConditionalAutoGen, AutoGenJNLSigned)
{
auto setup = GetSetup();
{
Function<uint64_t, uint64_t, uint64_t> expression(setup->GetAllocator(), setup->GetCode());
uint64_t trueValue = 1;
uint64_t falseValue = 128;
auto & a = expression.Compare<JccType::JNL>(expression.GetP1(), expression.GetP2());
auto & b = expression.Conditional(a, expression.Immediate(trueValue), expression.Immediate(falseValue));
auto function = expression.Compile(b);
for (int64_t p1 = -1; p1 <= 1; ++p1) {
for (int64_t p2 = -1; p2 <= 1; ++p2) {
auto expected = (p1 >= p2) ? trueValue : falseValue;
auto observed = function(p1, p2);
ASSERT_EQ(expected, observed);
}
}
}
}
TEST_F(ConditionalAutoGen, AutoGenJNEUnsigned)
{
auto setup = GetSetup();
{
Function<uint64_t, uint64_t, uint64_t> expression(setup->GetAllocator(), setup->GetCode());
uint64_t trueValue = 1;
uint64_t falseValue = 128;
auto & a = expression.Compare<JccType::JNE>(expression.GetP1(), expression.GetP2());
auto & b = expression.Conditional(a, expression.Immediate(trueValue), expression.Immediate(falseValue));
auto function = expression.Compile(b);
for (uint64_t p1 = 0; p1 <= 1; ++p1) {
for (uint64_t p2 = 0; p2 <= 1; ++p2) {
auto expected = (p1 != p2) ? trueValue : falseValue;
auto observed = function(p1, p2);
ASSERT_EQ(expected, observed);
}
}
}
}
TEST_F(ConditionalAutoGen, AutoGenJNESigned)
{
auto setup = GetSetup();
{
Function<uint64_t, uint64_t, uint64_t> expression(setup->GetAllocator(), setup->GetCode());
uint64_t trueValue = 1;
uint64_t falseValue = 128;
auto & a = expression.Compare<JccType::JNE>(expression.GetP1(), expression.GetP2());
auto & b = expression.Conditional(a, expression.Immediate(trueValue), expression.Immediate(falseValue));
auto function = expression.Compile(b);
for (int64_t p1 = -1; p1 <= 1; ++p1) {
for (int64_t p2 = -1; p2 <= 1; ++p2) {
auto expected = (p1 != p2) ? trueValue : falseValue;
auto observed = function(p1, p2);
ASSERT_EQ(expected, observed);
}
}
}
}
TEST_F(ConditionalAutoGen, AutoGenJEUnsigned)
{
auto setup = GetSetup();
{
Function<uint64_t, uint64_t, uint64_t> expression(setup->GetAllocator(), setup->GetCode());
uint64_t trueValue = 1;
uint64_t falseValue = 128;
auto & a = expression.Compare<JccType::JE>(expression.GetP1(), expression.GetP2());
auto & b = expression.Conditional(a, expression.Immediate(trueValue), expression.Immediate(falseValue));
auto function = expression.Compile(b);
for (uint64_t p1 = 0; p1 <= 1; ++p1) {
for (uint64_t p2 = 0; p2 <= 1; ++p2) {
auto expected = (p1 == p2) ? trueValue : falseValue;
auto observed = function(p1, p2);
ASSERT_EQ(expected, observed);
}
}
}
}
TEST_F(ConditionalAutoGen, AutoGenJESigned)
{
auto setup = GetSetup();
{
Function<uint64_t, uint64_t, uint64_t> expression(setup->GetAllocator(), setup->GetCode());
uint64_t trueValue = 1;
uint64_t falseValue = 128;
auto & a = expression.Compare<JccType::JE>(expression.GetP1(), expression.GetP2());
auto & b = expression.Conditional(a, expression.Immediate(trueValue), expression.Immediate(falseValue));
auto function = expression.Compile(b);
for (int64_t p1 = -1; p1 <= 1; ++p1) {
for (int64_t p2 = -1; p2 <= 1; ++p2) {
auto expected = (p1 == p2) ? trueValue : falseValue;
auto observed = function(p1, p2);
ASSERT_EQ(expected, observed);
}
}
}
}
TEST_CASES_END
}
}
``` | /content/code_sandbox/test/NativeJIT/ConditionalAutoGenTest.cpp | c++ | 2016-04-09T23:53:19 | 2024-06-29T07:05:56 | NativeJIT | BitFunnel/NativeJIT | 1,133 | 4,828 |
```c++
// Permission is hereby granted, free of charge, to any person obtaining a copy
// of this software and associated documentation files (the "Software"), to deal
// in the Software without restriction, including without limitation the rights
// to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
// copies of the Software, and to permit persons to whom the Software is
// furnished to do so, subject to the following conditions:
// The above copyright notice and this permission notice shall be included in
// all copies or substantial portions of the Software.
// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
// AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
// LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
// OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
// THE SOFTWARE.
#include <cmath> // For float std::abs(float).
#include <iostream>
#include "NativeJIT/CodeGen/ExecutionBuffer.h"
#include "NativeJIT/CodeGen/FunctionBuffer.h"
#include "NativeJIT/Function.h"
#include "TestSetup.h"
#ifndef _MSC_VER
#define _AddressOfReturnAddress() __builtin_frame_address(0)
#endif
namespace NativeJIT
{
namespace FunctionUnitTest
{
TEST_FIXTURE_START(FunctionTest)
protected:
static int s_sampleFunctionCalls;
static int s_intParameter1;
static int s_intParameter2;
static char s_charParameter1;
static int64_t s_int64Parameter3;
static bool s_boolParameter4;
static unsigned s_regPreserveTestFuncCallCount;
static int SampleFunction0()
{
++s_sampleFunctionCalls;
return 12345;
}
static int SampleFunction1(char p1)
{
s_charParameter1 = p1;
++s_sampleFunctionCalls;
return p1 + 3;
}
static int SampleFunction2(int p1, int p2)
{
s_intParameter1 = p1;
s_intParameter2 = p2;
++s_sampleFunctionCalls;
return p1 + p2;
}
static int SampleFunction2DifferentTypes(char p1, int p2)
{
s_charParameter1 = p1;
s_intParameter2 = p2;
++s_sampleFunctionCalls;
return p1 + p2;
}
static int64_t SampleFunction3(char p1, int p2, int64_t p3)
{
s_charParameter1 = p1;
s_intParameter2 = p2;
s_int64Parameter3 = p3;
++s_sampleFunctionCalls;
return p1 + p2 + p3;
}
static int64_t SampleFunction4(char p1, int p2, int64_t p3, bool p4)
{
s_charParameter1 = p1;
s_intParameter2 = p2;
s_int64Parameter3 = p3;
s_boolParameter4 = p4;
++s_sampleFunctionCalls;
return p1 + p2 + p3 + (p4 ? 123 : 456);
}
// These helper functions are used to overwrite the EAX/XMM0s
// registers with a specific value, different than some special value
// that other functions return.
template <int VAL>
static int ReturnInt()
{
return VAL;
}
static float Return7Point7()
{
return 7.7f;
}
static float Return3Point3()
{
return 3.3f;
}
// These two functions return a fixed value in EAX/XMM0s and overwrite
// the opposite register (XMM0s/EAX) with an unrelated value using
// the functions above. This makes it possible to verify that XMM0s/EAX
// is preserved when necessary (f. ex. for its re-use in cache).
// Since the order of the calls is important in such tests, they
// ensure that the call is made when expected.
// A wrapper assert method for GTest which has a void return type
// so that test asserts can compile.
static void AssertCallOrder(char const * s_methodName,
unsigned expectedCallNumber,
unsigned actualCallNumber)
{
static_cast<void>(s_methodName); // Unreferenced parameter for GTest.
EXPECT_EQ(expectedCallNumber, actualCallNumber)
<< "unexpected call order "
<< s_methodName;
}
template <unsigned CALLNUMBER>
static int Return10()
{
++s_regPreserveTestFuncCallCount;
AssertCallOrder("Return10", CALLNUMBER, s_regPreserveTestFuncCallCount);
// Call any function which returns a float other than 1.3 used
// in the function below to make sure that xmm0s is overwritten.
// This will ensure that the test will succeed only if the caller
// which needs to re-use the original value correctly preserved it.
Return7Point7();
return 10;
}
template <unsigned CALLNUMBER>
static float Return1Point3()
{
++s_regPreserveTestFuncCallCount;
AssertCallOrder("Return1Point3", CALLNUMBER, s_regPreserveTestFuncCallCount);
// Call any function which returns an integer other than 10 used
// in the function above to make sure eax is overwritten.
// This will ensure that the test will succeed only if the caller
// which needs to re-use the original value correctly preserved it.
ReturnInt<999>();
return 1.3f;
}
TEST_FIXTURE_END_TEST_CASES_BEGIN
//
// JIT Functions with 0, 1, 2, 3, and 4 parameters.
//
TEST_F(FunctionTest, FunctionZeroParameters)
{
auto setup = GetSetup();
{
Function<int64_t> expression(setup->GetAllocator(), setup->GetCode());
int64_t expected = 1234ll;
auto & a = expression.Immediate(expected);
auto function = expression.Compile(a);
auto observed = function();
EXPECT_EQ(expected, observed);
}
}
TEST_F(FunctionTest, FunctionOneParameter)
{
auto setup = GetSetup();
{
Function<int64_t, int64_t> expression(setup->GetAllocator(), setup->GetCode());
auto & a = expression.GetP1();
auto function = expression.Compile(a);
int64_t p1 = 1234ll;
auto expected = p1;
auto observed = function(p1);
EXPECT_EQ(expected, observed);
}
}
TEST_F(FunctionTest, FunctionTwoParameters)
{
auto setup = GetSetup();
{
Function<int64_t, int64_t, int64_t> expression(setup->GetAllocator(), setup->GetCode());
auto & a = expression.Add(expression.GetP1(), expression.GetP2());
auto function = expression.Compile(a);
int64_t p1 = 12340000ll;
int64_t p2 = 5678ll;
auto expected = p1 + p2;
auto observed = function(p1, p2);
EXPECT_EQ(expected, observed);
}
}
TEST_F(FunctionTest, FunctionThreeParameters)
{
auto setup = GetSetup();
{
Function<int, int, int, int> expression(setup->GetAllocator(), setup->GetCode());
auto & a = expression.Sub(expression.GetP2(), expression.GetP1());
auto & b = expression.Add(expression.GetP3(), a);
auto function = expression.Compile(b);
int p1 = 0x12340000;
int p2 = 0x5678;
int p3 = 0x11111111;
auto expected = p2 - p1 + p3;
auto observed = function(p1, p2, p3);
EXPECT_EQ(expected, observed);
}
}
TEST_F(FunctionTest, FunctionFourParameters)
{
auto setup = GetSetup();
{
Function<char, char, char, char, char> expression(setup->GetAllocator(), setup->GetCode());
auto & a = expression.Sub(expression.GetP1(), expression.GetP2());
auto & b = expression.Sub(expression.GetP3(), expression.GetP4());
auto & c = expression.Sub(a, b);
auto function = expression.Compile(c);
char p1 = 100;
char p2 = 50;
char p3 = 10;
char p4 = 5;
auto expected = (p1 - p2) - (p3 - p4);
auto observed = function(p1, p2, p3, p4);
EXPECT_EQ(expected, observed);
}
}
// The Windows x64 ABI and the System V ABI handle parameter passing
// differently. This test case verifies that a function with int and
// float parameters works correctly.
TEST_F(FunctionTest, FunctionTwoMixedParameters)
{
auto setup = GetSetup();
{
Function<float, int, float> expression(setup->GetAllocator(), setup->GetCode());
float c10 = 10.0f;
auto & a = expression.Mul(expression.GetP2(), expression.Immediate<float>(c10));
auto & b = expression.Add(expression.Cast<float>(expression.GetP1()), a);
auto function = expression.Compile(b);
int p1 = 1;
float p2 = 2.0;
auto expected = static_cast<float>(p1) + (p2 * 10.0f);
auto observed = function(p1, p2);
EXPECT_EQ(expected, observed);
}
}
// The Windows x64 ABI and the System V ABI handle parameter passing
// differently. This test case verifies that a function with int and
// float parameters works correctly.
TEST_F(FunctionTest, FunctionThreeMixedParameters)
{
auto setup = GetSetup();
{
Function<float, int, float, int> expression(setup->GetAllocator(), setup->GetCode());
float c10 = 10.0f;
float c100 = 100.0f;
auto & a = expression.Mul(expression.GetP2(), expression.Immediate<float>(c10));
auto & b = expression.Mul(expression.Cast<float>(expression.GetP3()), expression.Immediate<float>(c100));
auto & c = expression.Add(expression.Cast<float>(expression.GetP1()), a);
auto & d = expression.Add(c, b);
auto function = expression.Compile(d);
int p1 = 1;
float p2 = 2.0;
int p3 = 3;
auto expected = static_cast<float>(p1) + (p2 * 10.0f) + (p3 * 100);
auto observed = function(p1, p2, p3);
EXPECT_EQ(expected, observed);
}
}
// The Windows x64 ABI and the System V ABI handle parameter passing
// differently. This test case verifies that a function with int and
// float parameters works correctly.
TEST_F(FunctionTest, FunctionFourMixedParameters)
{
auto setup = GetSetup();
{
Function<float, int, float, int, float> expression(setup->GetAllocator(), setup->GetCode());
float c10 = 10.0f;
float c100 = 100.0f;
float c1000 = 1000.0f;
auto & a = expression.Mul(expression.GetP2(), expression.Immediate<float>(c10));
auto & b = expression.Mul(expression.Cast<float>(expression.GetP3()), expression.Immediate<float>(c100));
auto & c = expression.Mul(expression.GetP4(), expression.Immediate<float>(c1000));
auto & d = expression.Add(expression.Cast<float>(expression.GetP1()), a);
auto & e = expression.Add(d, b);
auto & f = expression.Add(e, c);
auto function = expression.Compile(f);
int p1 = 1;
float p2 = 2.0;
int p3 = 3;
float p4 = 4.0;
auto expected = static_cast<float>(p1) + (p2 * 10.0f) + (p3 * 100) + (p4 * 1000.0f);
auto observed = function(p1, p2, p3, p4);
EXPECT_EQ(expected, observed);
}
}
//
// Calling C functions with 0, 1, 2, 3, and 4 parameters.
//
TEST_F(FunctionTest, CallZeroParameters)
{
auto setup = GetSetup();
{
Function<int> expression(setup->GetAllocator(), setup->GetCode());
typedef int (*F)();
auto & sampleFunction = expression.Immediate<F>(SampleFunction0);
auto & a = expression.Call(sampleFunction);
auto function = expression.Compile(a);
auto expected = SampleFunction0();
s_sampleFunctionCalls = 0;
auto observed = function();
EXPECT_EQ(expected, observed);
EXPECT_EQ(1, s_sampleFunctionCalls);
}
}
TEST_F(FunctionTest, CallOneParameter)
{
auto setup = GetSetup();
{
Function<int, char> expression(setup->GetAllocator(), setup->GetCode());
typedef int (*F)(char);
auto & sampleFunction = expression.Immediate<F>(SampleFunction1);
auto & a = expression.Call(sampleFunction, expression.GetP1());
auto function = expression.Compile(a);
const char p1 = 0x73;
auto expected = SampleFunction1(p1);
// Anything other than p1 will do.
s_charParameter1 = p1 + 1;
s_sampleFunctionCalls = 0;
auto observed = function(p1);
EXPECT_EQ(expected, observed);
EXPECT_EQ(1, s_sampleFunctionCalls);
EXPECT_EQ(s_charParameter1, p1);
}
}
TEST_F(FunctionTest, CallTwoParameters)
{
auto setup = GetSetup();
{
Function<int, int, int> expression(setup->GetAllocator(), setup->GetCode());
typedef int (*F)(int, int);
auto & sampleFunction = expression.Immediate<F>(SampleFunction2);
auto & a = expression.Call(sampleFunction, expression.GetP2(), expression.GetP1());
auto function = expression.Compile(a);
const int p1 = 12340000;
const int p2 = 5678;
auto expected = SampleFunction2(p1, p2);
// Anything other than p1/p2 will do.
s_intParameter1 = p1 + 1;
s_intParameter2 = p2 + 1;
s_sampleFunctionCalls = 0;
auto observed = function(p2, p1);
EXPECT_EQ(expected, observed);
EXPECT_EQ(1, s_sampleFunctionCalls);
EXPECT_EQ(s_intParameter1, p1);
EXPECT_EQ(s_intParameter2, p2);
}
}
// WARNING: These tests are disabled due to a long-standing NativeJIT
// bug having to do with the function passing ABI. Mike has had a fix
// for this in mind since 11/2016, but hasn't had time to implement the
// fix. Having these flaky failing tests checked in has prevented us
// from enabling MacOS CI for 5 months and counting, so I'm disabling
// these because I believe the lesser of two evils to not have a test
// for this and have MacOS CI for our other tests. See
// path_to_url for further
// discussion.
// TEST_F(FunctionTest, CallTwoParametersDifferentTypes)
// {
// auto setup = GetSetup();
// {
// Function<int, int, char> expression(setup->GetAllocator(), setup->GetCode());
// typedef int (*F)(char, int);
// auto & sampleFunction = expression.Immediate<F>(SampleFunction2DifferentTypes);
// auto & a = expression.Call(sampleFunction, expression.GetP2(), expression.GetP1());
// auto function = expression.Compile(a);
// const char p1 = 0x74;
// const int p2 = 5678;
// auto expected = SampleFunction2DifferentTypes(p1, p2);
// // Anything other than p1/p2 will do.
// s_charParameter1 = p1 + 1;
// s_intParameter2 = p2 + 1;
// s_sampleFunctionCalls = 0;
// auto observed = function(p2, p1);
// EXPECT_EQ(expected, observed);
// EXPECT_EQ(1, s_sampleFunctionCalls);
// EXPECT_EQ(s_charParameter1, p1);
// EXPECT_EQ(s_intParameter2, p2);
// }
// }
// TEST_F(FunctionTest, CallThreeParameters)
// {
// auto setup = GetSetup();
// {
// Function<int64_t, int64_t, int, char> expression(setup->GetAllocator(), setup->GetCode());
// typedef int64_t (*F)(char, int, int64_t);
// auto & sampleFunction = expression.Immediate<F>(SampleFunction3);
// auto & a = expression.Call(sampleFunction,
// expression.GetP3(),
// expression.GetP2(),
// expression.GetP1());
// auto function = expression.Compile(a);
// const char p1 = 0x73;
// const int p2 = 5678;
// const int64_t p3 = 12340000ll;
// auto expected = SampleFunction3(p1, p2, p3);
// // Anything other than p1/p2/p3 will do.
// s_charParameter1 = p1 + 1;
// s_intParameter2 = p2 + 1;
// s_int64Parameter3 = p3 + 1;
// s_sampleFunctionCalls = 0;
// auto observed = function(p3, p2, p1);
// EXPECT_EQ(expected, observed);
// EXPECT_EQ(1, s_sampleFunctionCalls);
// EXPECT_EQ(s_charParameter1, p1);
// EXPECT_EQ(s_intParameter2, p2);
// EXPECT_EQ(s_int64Parameter3, p3);
// }
// }
TEST_F(FunctionTest, CallFourParameters)
{
auto setup = GetSetup();
{
Function<int64_t, bool, int64_t, int, char> expression(setup->GetAllocator(), setup->GetCode());
typedef int64_t (*F)(char, int, int64_t, bool);
auto & sampleFunction = expression.Immediate<F>(SampleFunction4);
auto & a = expression.Call(sampleFunction,
expression.GetP4(),
expression.GetP3(),
expression.GetP2(),
expression.GetP1());
auto function = expression.Compile(a);
const char p1 = 0x73;
const int p2 = 5678;
const int64_t p3 = 12340000;
const bool p4 = true;
auto expected = SampleFunction4(p1, p2, p3, p4);
// Anything other than p1/p2/p3/p4 will do.
s_charParameter1 = p1 + 1;
s_intParameter2 = p2 + 1;
s_int64Parameter3 = p3 + 1;
s_boolParameter4 = !p4;
s_sampleFunctionCalls = 0;
auto observed = function(p4, p3, p2, p1);
EXPECT_EQ(expected, observed);
EXPECT_EQ(1, s_sampleFunctionCalls);
EXPECT_EQ(s_charParameter1, p1);
EXPECT_EQ(s_intParameter2, p2);
EXPECT_EQ(s_int64Parameter3, p3);
EXPECT_EQ(s_boolParameter4, p4);
}
}
// Verifies that the references to stack variables are in a sane
// memory range.
// The *Internal method is needed because GTest requires a void method
// and NativeJIT requires a method which returns a value (which is ignored
// for this test).
static void VerifyStackVariableAddressesInternal(uint32_t& intRef,
float& floatRef,
void const * addressOfReturnAddress)
{
// Since the stack pointer moves downwards, the upper limit of
// this function's stack range represents the lower limit of
// the previous function's stack range in the call stack.
// The previous function is the jitted function whose stack
// variable address we are trying to verify. The size of its
// stack range is small (64 bytes or so), but more buffer
// is added to account for different compilers and settings.
// Note: it would also be possible to define the range as the
// value between _AddressOfReturnAddress() as returned here
// and _AddressOfReturnAddress() as returned by the caller of the
// jitted function (that value would be passed as an argument).
auto const bufferStart = static_cast<uint8_t const *>(addressOfReturnAddress);
auto const bufferLimit = bufferStart + 1024;
auto const intPtr = reinterpret_cast<unsigned char const *>(&intRef);
auto const floatPtr = reinterpret_cast<unsigned char const *>(&floatRef);
ASSERT_TRUE(intPtr >= bufferStart && intPtr < bufferLimit) <<
"Expected range: [" <<
bufferStart <<
"," <<
bufferLimit <<
") found:" <<
intPtr;
ASSERT_TRUE(floatPtr >= bufferStart && floatPtr < bufferLimit) <<
"Expected range: [" <<
bufferStart <<
"," <<
bufferLimit <<
") found:" <<
floatPtr;
}
static int VerifyStackVariableAddresses(uint32_t& intRef, float& floatRef)
{
VerifyStackVariableAddressesInternal(intRef, floatRef, _AddressOfReturnAddress());
return 1;
}
TEST_F(FunctionTest, StackVariableAddressRange)
{
auto setup = GetSetup();
Function<int> e(setup->GetAllocator(), setup->GetCode());
auto & sampleFunction = e.Immediate(VerifyStackVariableAddresses);
auto & intVariable = e.StackVariable<uint32_t>();
auto & floatVariable = e.StackVariable<float>();
auto & call = e.Call(sampleFunction, intVariable, floatVariable);
auto function = e.Compile(call);
function();
}
// Verifies that pointer and reference arguments refer to the same
// memory location and that it contains the expected value.
// The *Internal method is needed because GTest requires a void method
// and NativeJIT requires a method which returns a value (which is ignored
// for this test).
static void VerifyPointerVsReferenceInternal(uint32_t* intPtr,
uint32_t& intRef,
unsigned int expectedValue)
{
EXPECT_EQ(intPtr, &intRef) <<
"Pointer and reference should have referred to the same address";
EXPECT_EQ(expectedValue, intRef) << "Unexpected target value";
}
static int VerifyPointerVsReference(uint32_t* intPtr,
uint32_t& intRef,
unsigned int expectedValue)
{
VerifyPointerVsReferenceInternal(intPtr, intRef, expectedValue);
return 1;
}
TEST_F(FunctionTest, PointerToReferenceConversion)
{
auto setup = GetSetup();
Function<int> e(setup->GetAllocator(), setup->GetCode());
uint32_t testValue = 7;
auto & testFunction = e.Immediate(VerifyPointerVsReference);
auto & intPtrArgument = e.Immediate(&testValue);
auto & intRefArgument = e.AsReference(intPtrArgument);
auto & call = e.Call(testFunction,
intPtrArgument,
intRefArgument,
e.Immediate(testValue));
auto function = e.Compile(call);
function();
}
static int& Return10ByReference()
{
static int ten = 10;
return ten;
}
TEST_F(FunctionTest, ReturnReference)
{
auto setup = GetSetup();
Function<int&> e(setup->GetAllocator(), setup->GetCode());
auto & return10 = e.Immediate(Return10ByReference);
auto & call = e.Call(return10);
auto function = e.Compile(call);
int& result = function();
EXPECT_EQ(10, result);
}
// Verify that the return register is preserved accross two
// consecutive calls.
TEST_F(FunctionTest, PreserveReturnRegisterInt)
{
auto setup = GetSetup();
Function<int> e(setup->GetAllocator(), setup->GetCode());
auto & return7 = e.Call(e.Immediate(ReturnInt<7>));
auto & return8 = e.Call(e.Immediate(ReturnInt<8>));
// Ensure that 7 is preserved before the call that would overwrite
// it with 8.
auto & sum = e.Add(return7, return8);
auto function = e.Compile(sum);
int result = function();
EXPECT_EQ(7 + 8, result);
}
TEST_F(FunctionTest, PreserveReturnRegisterFloat)
{
auto setup = GetSetup();
Function<float> e(setup->GetAllocator(), setup->GetCode());
auto & return7Point7 = e.Call(e.Immediate(Return7Point7));
auto & return3Point3 = e.Call(e.Immediate(Return3Point3));
// Ensure that 7.7 is preserved before the call that would overwrite
// it with 3.3.
auto & sum = e.Add(return7Point7, return3Point3);
auto function = e.Compile(sum);
float result = function();
EXPECT_EQ(7.7 + 3.3, result);
}
// Verify that the return register is treated volatile only when it's
// actually used (i.e. don't treat EAX as volatile and presereve it
// if a function returning in XMM0 is called).
TEST_F(FunctionTest, SaveOtherReturnRegisterIntFloat)
{
s_regPreserveTestFuncCallCount = 0;
auto setup = GetSetup();
Function<int> e(setup->GetAllocator(), setup->GetCode());
// Call the function returning 10 in EAX first, followed by
// a function returning 1.3 in XMM0s. Since EAX will be referenced
// later and it's not used for calling the float function, it
// must be preserved accross that call (i.e. not treated as volatile).
auto & return10 = e.Immediate(Return10<1>);
auto & call10 = e.Call(return10);
auto & return1Point3 = e.Immediate(Return1Point3<2>);
auto & call1Point3 = e.Dependent(e.Call(return1Point3),
call10);
// Convert 1.3 to 1. This is to ensure that the call is referenced
// and the value is then used since it's convenient.
auto & int1 = e.Cast<int>(call1Point3);
// Sum 10, 1 and 10, expecting to get 21. If the cached value
// of 10 is not preserved correctly accross the call, the result
// will be incorrect.
auto & sum = e.Add(e.Add(call10, int1), call10);
auto function = e.Compile(sum);
int result = function();
EXPECT_EQ(21, result);
}
// Verify that return register is treated volatile only when it's
// actually used (i.e. don't treat EAX as volatile and preserve it
// if a function returning in XMM0 is called).
TEST_F(FunctionTest, SaveOtherReturnRegisterFloatInt)
{
s_regPreserveTestFuncCallCount = 0;
auto setup = GetSetup();
Function<float> e(setup->GetAllocator(), setup->GetCode());
// Call the function returning 1.3 in XMM0s first, followed by
// a function returning 10 in EAX. Since XMM0s will be referenced
// later and it's not used for calling the int function, it
// must be preserved accross that call (i.e. not treated as volatile).
auto & return1Point3 = e.Immediate(Return1Point3<1>);
auto & call1Point3 = e.Call(return1Point3);
auto & return10 = e.Immediate(Return10<2>);
auto & call10 = e.Dependent(e.Call(return10),
call1Point3);
// Convert 10 to 10.0. This is to ensure that the call is referenced
// and the value is then used since it's convenient.
auto & float10 = e.Cast<float>(call10);
// Sum 1.3, 10.0 and 1.3, expecting to get 12.6. If the cached value
// of 1.3 is not preserved correctly accross the call, the result
// will be incorrect.
auto & sum = e.Add(e.Add(call1Point3, float10), call1Point3);
auto function = e.Compile(sum);
float result = function();
ASSERT_TRUE(std::abs(12.6 - result) < 0.01) <<
"Result should be around 12.6, but found " <<
result;
}
// These two functions are used to ensure zero is placed inside
// ECX/XMM1s when they are called. It is important that they
// are not inlined to achieve this.
#ifdef NATIVEJIT_PLATFORM_WINDOWS
__declspec(noinline)
static void TakeZeroIntArg(int arg)
#else
static void __attribute__ ((noinline)) TakeZeroIntArg(int arg)
#endif
{
EXPECT_EQ(0, arg);
}
#ifdef NATIVEJIT_PLATFORM_WINDOWS
__declspec(noinline)
static void TakeZeroFloatArg(float /* arg1 */, float arg2)
#else
static void __attribute__ ((noinline)) TakeZeroFloatArg(float /* arg1 */, float arg2)
#endif
{
EXPECT_EQ(0.0f, arg2);
}
// These two helper functions return their argument and, as a
// side-effect, ensure that zero is placed inside ECX/XMM0s to
// demonstrate the volatility of these registers.
static int ZeroRcxAndReturnArg(int arg)
{
TakeZeroIntArg(0);
return arg;
}
static float ZeroXmm1AndReturnArg1(float arg1, float /* arg2 */)
{
TakeZeroFloatArg(0.0, 0.0);
return arg1;
}
// When function parameter happens to be in the desired register,
// if there are other references to it (f. ex. later in the expression),
// it should be preserved.
TEST_F(FunctionTest, VerifyFunctionParameterReuseInt)
{
auto setup = GetSetup();
Function<int, int> e(setup->GetAllocator(), setup->GetCode());
auto & zeroRcxAndReturnArg = e.Immediate(ZeroRcxAndReturnArg);
// Param1 is in ECX which happens to be the register where CALL
// needs it to be, but it needs to be re-used later as well.
// Since RCX is volatile, the other instance must be preserved
// before the call for the test to succeed.
auto & param1 = e.GetP1();
auto & call = e.Call(zeroRcxAndReturnArg, param1);
auto & sum = e.Add(call, param1);
auto function = e.Compile(sum);
int result = function(7);
// The first 7 comes from the return value from the call and the
// other 7 comes from the preserved value of ECX.
EXPECT_EQ(7 + 7, result);
}
TEST_F(FunctionTest, VerifyFunctionParameterReuseFloat)
{
auto setup = GetSetup();
Function<float, float, float> e(setup->GetAllocator(), setup->GetCode());
auto & zeroXmm1AndReturnArg1 = e.Immediate(ZeroXmm1AndReturnArg1);
// Param2 is in XMM1s which happens to be the register where CALL
// needs it to be, but it needs to be re-used later as well.
// Since XMM1s is volatile, the other instance must be preserved
// before the call for the test to succeed.
auto & param2 = e.GetP2();
auto & call = e.Call(zeroXmm1AndReturnArg1, e.GetP1(), param2);
auto & sum = e.Add(call, param2);
auto function = e.Compile(sum);
float result = function(2.5f, 7.5f);
// The 2.5 value comes from the return value from the call and
// 7.5 comes from the preserved value of XMM1s.
EXPECT_EQ(2.5f + 7.5f, result);
}
// Verify that no asserts are hit when using a function which doesn't
// reference some of its parameters.
TEST_F(FunctionTest, FunctionWithUnusedParameter)
{
auto setup = GetSetup();
Function<int64_t, int64_t, int64_t> expression(setup->GetAllocator(), setup->GetCode());
auto function = expression.Compile(expression.GetP2());
int64_t p1Unused = 0;
int64_t p2 = 123;
auto observed = function(p1Unused, p2);
EXPECT_EQ(p2, observed);
}
TEST_F(FunctionTest, ExecuteOnlyIf)
{
auto setup = GetSetup();
Function<float, uint64_t> e(setup->GetAllocator(), setup->GetCode());
// Regular value is argument + 2.5.
auto & regularValue = e.Add(e.Cast<float>(e.GetP1()),
e.Immediate(2.5f));
// Execute the regular expression only if argument is less than
// 7, otherwise abort and return 0.
auto & argLessThan7 = e.Compare<JccType::JB>(e.GetP1(), e.Immediate(static_cast<uint64_t>(7)));
e.AddExecuteOnlyIfStatement(argLessThan7, e.Immediate(0.0f));
auto function = e.Compile(regularValue);
// Argument is less than 7, the regular value should be returned.
auto observed = function(5);
EXPECT_EQ(5.0f + 2.5f, observed);
// Argument is not less than 7, 0 should be returned.
observed = function(10);
EXPECT_EQ(0.0f, observed);
}
TEST_CASES_END
int FunctionTest::s_sampleFunctionCalls;
int FunctionTest::s_intParameter1;
int FunctionTest::s_intParameter2;
char FunctionTest::s_charParameter1;
int64_t FunctionTest::s_int64Parameter3;
bool FunctionTest::s_boolParameter4;
unsigned FunctionTest::s_regPreserveTestFuncCallCount;
}
}
``` | /content/code_sandbox/test/NativeJIT/FunctionTest.cpp | c++ | 2016-04-09T23:53:19 | 2024-06-29T07:05:56 | NativeJIT | BitFunnel/NativeJIT | 1,133 | 7,736 |
```go
// Permission is hereby granted, free of charge, to any person obtaining a copy
// of this software and associated documentation files (the "Software"), to deal
// in the Software without restriction, including without limitation the rights
// to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
// copies of the Software, and to permit persons to whom the Software is
// furnished to do so, subject to the following conditions:
// The above copyright notice and this permission notice shall be included in
// all copies or substantial portions of the Software.
// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
// AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
// LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
// OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
// THE SOFTWARE.
package main
// Quick hack script to generate tests for conditionals.
import (
"fmt"
"strings"
)
// TODO: conditionals listed below aren't tested.
/*
JO
JNO
JAE
JNB
JNC
JS
JNS
JP
JPE
JNP
JPO
*/
type CppType int
const (
SIGNED CppType = iota
UNSIGNED
BOTH
)
var (
template = ` TEST_CASE_F(ConditionalAutoGen, REPLACE_NAME)
{
auto setup = GetSetup();
{
Function<uint64_t, uint64_t, uint64_t> expression(setup->GetAllocator(), setup->GetCode());
uint64_t trueValue = 1;
uint64_t falseValue = 128;
auto & a = expression.Compare<JccType::REPLACE_COND>(expression.GetP1(), expression.GetP2());
auto & b = expression.Conditional(a, expression.Immediate(trueValue), expression.Immediate(falseValue));
auto function = expression.Compile(b);
for (REPLACE_TYPE p1 = REPLACE_STARTVAL; p1 <= 1; ++p1) {
for (REPLACE_TYPE p2 = REPLACE_STARTVAL; p2 <= 1; ++p2) {
auto expected = (REPLACE_EXPR) ? trueValue : falseValue;
auto observed = function(p1, p2);
TestEqual(expected, observed);
}
}
}
}
`
// path_to_url
condExpr = map[string]string{
"JNE": "p1 != p2",
"JNZ": "p1 != p2",
"JE": "p1 == p2",
"JZ": "p1 == p2",
"JB": "p1 < p2",
// JC (same as JB) appears to be missing. Is that a bug?
"JBE": "p1 <= p2",
"JNA": "p1 <= p2",
"JA": "p1 > p2",
"JNBE": "p1 > p2",
"JL": "p1 < p2",
"JNGE": "p1 < p2",
"JGE": "p1 >= p2",
"JNL": "p1 >= p2",
"JLE": "p1 <= p2",
"JNG": "p1 <= p2",
"JG": "p1 > p2",
"JNLE": "p1 > p2",
}
condType = map[string]CppType{
"JNE": BOTH,
"JNZ": BOTH,
"JE": BOTH,
"JZ": BOTH,
"JB": UNSIGNED,
"JBE": UNSIGNED,
"JNA": UNSIGNED,
"JA": UNSIGNED,
"JNBE": UNSIGNED,
"JL": SIGNED,
"JNGE": SIGNED,
"JGE": SIGNED,
"JNL": SIGNED,
"JLE": SIGNED,
"JNG": SIGNED,
"JG": SIGNED,
"JNLE": SIGNED,
}
)
func createTest(testName string, expr string, cond string, typeInTest string, startVal string) {
thisTest := strings.Replace(template, "REPLACE_NAME", testName, 1)
thisTest = strings.Replace(thisTest, "REPLACE_EXPR", expr, 1)
thisTest = strings.Replace(thisTest, "REPLACE_COND", cond, 1)
thisTest = strings.Replace(thisTest, "REPLACE_TYPE", typeInTest, -1)
thisTest = strings.Replace(thisTest, "REPLACE_STARTVAL", startVal, -1)
fmt.Println(thisTest)
}
func main() {
for cond, expr := range condExpr {
testName := "AutoGen" + cond
if condType[cond] == UNSIGNED || condType[cond] == BOTH {
createTest(testName+"Unsigned", expr, cond, "uint64_t", "0")
}
if condType[cond] == SIGNED || condType[cond] == BOTH {
createTest(testName+"Signed", expr, cond, "int64_t", "-1")
}
}
}
``` | /content/code_sandbox/src/Scripts/CondTest.go | go | 2016-04-09T23:53:19 | 2024-06-29T07:05:56 | NativeJIT | BitFunnel/NativeJIT | 1,133 | 1,206 |
```objective-c
// Permission is hereby granted, free of charge, to any person obtaining a copy
// of this software and associated documentation files (the "Software"), to deal
// in the Software without restriction, including without limitation the rights
// to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
// copies of the Software, and to permit persons to whom the Software is
// furnished to do so, subject to the following conditions:
// The above copyright notice and this permission notice shall be included in
// all copies or substantial portions of the Software.
// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
// AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
// LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
// OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
// THE SOFTWARE.
#pragma once
#include <cstdint>
#include <ostream>
#include <type_traits>
// _M_X64 is defined by VC, as well as icc on Windows.
// __amd64__ is defined by gcc/clang.
// __x86_64__ is defined by icc.
#if !defined(_M_X64) && !defined(__amd64__) && !defined(__x86_64__)
#error This code must be compiled for _AMD64_
#endif
#ifdef NATIVEJIT_PLATFORM_WINDOWS
#include <windows.h>
#else
typedef uint64_t DWORD64;
#endif
namespace NativeJIT
{
//*************************************************************************
//
// Windows unwind structure definitions.
// From MSDN: path_to_url
// Page title is "Unwind Data Definitions in C"
//
// Unwind information explanation: path_to_url
// Stack frame annotation explanation: path_to_url
//
//*************************************************************************
enum class UnwindCodeOp
{
UWOP_PUSH_NONVOL = 0, // info == register number
UWOP_ALLOC_LARGE, // no info, alloc size in next 2 slots
UWOP_ALLOC_SMALL, // info == size of allocation / 8 - 1
UWOP_SET_FPREG, // no info, FP = RSP + UNWIND_INFO.FPRegOffset*16
UWOP_SAVE_NONVOL, // info == register number, offset in next slot
UWOP_SAVE_NONVOL_FAR, // info == register number, offset in next 2 slots
UWOP_SAVE_XMM128, // info == XMM reg number, offset in next slot
UWOP_SAVE_XMM128_FAR, // info == XMM reg number, offset in next 2 slots
UWOP_PUSH_MACHFRAME // info == 0: no error-code, 1: error-code
};
// MSDN struct UNWIND_CODE: path_to_url
struct UnwindCode
{
UnwindCode();
UnwindCode(uint8_t codeOffset, UnwindCodeOp op, uint8_t info);
UnwindCode(uint16_t frameOffset);
union
{
// Note: C++ doesn't allow nameless structures, so naming this one
// m_operation.
struct
{
// MSDN: Offset from the beginning of the prolog of the end of
// the instruction that performs this operation, plus 1 (that is,
// the offset of the start of the next instruction).
uint8_t m_codeOffset;
uint8_t m_unwindOp : 4;
uint8_t m_opInfo : 4;
} m_operation;
uint16_t m_frameOffset;
};
};
static_assert(std::is_standard_layout<UnwindCode>::value, "UnwindCode must be standard layout.");
static_assert(sizeof(UnwindCode) == 2, "UnwindCode must be exactly two bytes");
// MSDN struct UNWIND_INFO: path_to_url
// Notable points: "The UNWIND_INFO structure must be DWORD aligned in memory."
// "For alignment purposes, [unwind codes] array will always have an even number
// of entries, with the final entry potentially unused (in which case the array
// will be one longer than indicated by the count of unwind codes field)."
struct UnwindInfo
{
UnwindInfo();
uint8_t m_version : 3;
uint8_t m_flags : 5;
uint8_t m_sizeOfProlog;
uint8_t m_countOfCodes;
uint8_t m_frameRegister : 4;
uint8_t m_frameOffset : 4;
// Additional codes follow after the end of the structure.
UnwindCode m_firstUnwindCode;
};
static_assert(std::is_standard_layout<UnwindInfo>::value,
"UnwindInfo must be standard layout.");
static_assert(sizeof(UnwindInfo) == 4 + sizeof(UnwindCode),
"Invalid UnwindInfo size, unexpected padding or extra members present");
namespace UnwindUtils
{
// Creates a function table identifier for a dynamically generated function.
// The identifier is used for RtlInstallFunctionTableCallback and
// RtlDeleteFunctionTable calls. Per their requirements, the two low-order
// bits of the identifier will be set.
//
// The provided address must uniquely identify the buffer containing the
// function code. Some examples include the address of the buffer itself
// or the address of a class instance that owns the buffer.
DWORD64 MakeFunctionTableIdentifier(void* objectAddress);
}
}
``` | /content/code_sandbox/src/CodeGen/UnwindCode.h | objective-c | 2016-04-09T23:53:19 | 2024-06-29T07:05:56 | NativeJIT | BitFunnel/NativeJIT | 1,133 | 1,221 |
```c++
// Permission is hereby granted, free of charge, to any person obtaining a copy
// of this software and associated documentation files (the "Software"), to deal
// in the Software without restriction, including without limitation the rights
// to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
// copies of the Software, and to permit persons to whom the Software is
// furnished to do so, subject to the following conditions:
// The above copyright notice and this permission notice shall be included in
// all copies or substantial portions of the Software.
// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
// AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
// LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
// OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
// THE SOFTWARE.
#include "NativeJIT/CodeGen/ValuePredicates.h"
namespace NativeJIT
{
unsigned Size(uint8_t value)
{
return (value == 0) ? 0 : 1;
}
unsigned Size(uint16_t value)
{
return (value == 0) ? 0 : ((value <= 0xff) ? 1 : 2);
}
unsigned Size(uint32_t value)
{
return (value == 0) ? 0 : ((value <= 0xff) ? 1 : ((value <= 0xffff) ? 2 : 4));
}
unsigned Size(uint64_t value)
{
return (value == 0) ? 0 : ((value <= 0xff)? 1 : ((value <= 0xffff) ? 2 : ((value <= 0xffffffff) ? 4 : 8)));
}
unsigned Size(int8_t value)
{
return (value == 0) ? 0 : 1;
}
unsigned Size(int16_t value)
{
return (value == 0) ? 0 : ((value >= -0x80 && value <= 0x7f)? 1 : 2);
}
unsigned Size(int32_t value)
{
return (value == 0)? 0 : ((value >= -0x80 && value <= 0x7f)? 1 : ((value >= -0x8000 && value <= 0x7fff) ? 2 : 4));
}
unsigned Size(int64_t value)
{
return (value == 0) ? 0 : ((value >= -0x80LL && value <= 0x7fLL)? 1 : ((value >= -0x8000LL && value <= 0x7fffLL) ? 2 : ((value >= -0x80000000LL && value <= 0x7fffffffLL) ? 4 : 8)));
}
}
``` | /content/code_sandbox/src/CodeGen/ValuePredicates.cpp | c++ | 2016-04-09T23:53:19 | 2024-06-29T07:05:56 | NativeJIT | BitFunnel/NativeJIT | 1,133 | 646 |
```c++
// Permission is hereby granted, free of charge, to any person obtaining a copy
// of this software and associated documentation files (the "Software"), to deal
// in the Software without restriction, including without limitation the rights
// to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
// copies of the Software, and to permit persons to whom the Software is
// furnished to do so, subject to the following conditions:
// The above copyright notice and this permission notice shall be included in
// all copies or substantial portions of the Software.
// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
// AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
// LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
// OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
// THE SOFTWARE.
#include <iomanip>
#include <iostream>
#include "NativeJIT/CodeGen/X64CodeGenerator.h"
namespace NativeJIT
{
//*************************************************************************
//
// Label
//
//*************************************************************************
Label::Label()
: m_id(0)
{
}
Label::Label(size_t id)
: m_id(id)
{
}
size_t Label::GetId() const
{
return m_id;
}
//*************************************************************************
//
// X64CodeGenerator public methods
//
//*************************************************************************
X64CodeGenerator::X64CodeGenerator(Allocators::IAllocator& codeAllocator,
unsigned capacity)
: CodeBuffer(codeAllocator, capacity),
m_diagnosticsStream(nullptr)
{
}
void X64CodeGenerator::EnableDiagnostics(std::ostream& out)
{
m_diagnosticsStream = &out;
}
void X64CodeGenerator::DisableDiagnostics()
{
m_diagnosticsStream = nullptr;
}
void X64CodeGenerator::PlaceLabel(Label l)
{
CodePrinter printer(*this);
CodeBuffer::PlaceLabel(l);
printer.PlaceLabel(l);
}
void X64CodeGenerator::Call(Label label)
{
CodePrinter printer(*this);
Emit8(0xe8);
EmitCallSite(label, 4);
printer.PrintJump(label);
}
void X64CodeGenerator::Jmp(Label label)
{
CodePrinter printer(*this);
Emit8(0xe9);
EmitCallSite(label, 4);
printer.PrintJump(label);
}
void X64CodeGenerator::Jmp(void* functionPtr)
{
CodePrinter printer(*this);
Emit8(0xe9);
Emit64(reinterpret_cast<uint64_t>(functionPtr));
printer.PrintJump(functionPtr);
}
char const * X64CodeGenerator::OpCodeName(OpCode op)
{
static char const * names[] = {
"add",
"and",
"bsf",
"bsr",
"bt",
"btc",
"btr",
"bts",
"call",
"cmp",
"cvtfp2fp",
"cvtfp2si",
"cvtsi2fp",
"dec",
"imul",
"inc",
"lea",
"mov",
"movsx",
"movzx",
"movap",
"neg",
"nop",
"not",
"or",
"pop",
"push",
"rep",
"ret",
"rol",
"shl",
"shld",
"shr",
"stosq",
"sub",
"xor",
};
static_assert(static_cast<unsigned>(OpCode::OpCodeCount) == std::extent<decltype(names)>::value,
"Mismatched number of opcode names.");
LogThrowAssert(static_cast<unsigned>(op) < std::extent<decltype(names)>::value, "Invalid OpCode");
return names[static_cast<unsigned>(op)];
}
char const * X64CodeGenerator::JccName(JccType jcc)
{
static char const * names[] = {
"jo",
"jno",
"jb",
"jae",
"je",
"jne",
"jbe",
"ja",
"js",
"jns",
"jp",
"jnp",
"jl",
"jnl",
"jle",
"jnle"
};
static_assert(static_cast<unsigned>(JccType::JccCount) == std::extent<decltype(names)>::value,
"Mismatched number of JCC names.");
LogThrowAssert(static_cast<unsigned>(jcc) < std::extent<decltype(names)>::value, "Invalid JCC");
return names[static_cast<unsigned>(jcc)];
}
bool X64CodeGenerator::IsDiagnosticsStreamAvailable() const
{
return m_diagnosticsStream != nullptr;
}
std::ostream& X64CodeGenerator::GetDiagnosticsStream() const
{
LogThrowAssert(m_diagnosticsStream != nullptr, "Diagnostics are disabled");
return *m_diagnosticsStream;
}
void X64CodeGenerator::Call(Register<8, false> r)
{
// EmitRex() would set REX.W, but this instruction defaults to
// 64-bit operands in 64-bit mode and doesn't need it.
if (r.IsExtended())
{
Emit8(0x41);
}
Emit8(0xff);
Emit8(0xD0 | r.GetId8());
}
void X64CodeGenerator::Pop(Register<8, false> r)
{
// EmitRex() would set REX.W, but this instruction defaults to
// 64-bit operands in 64-bit mode and doesn't need it.
if (r.IsExtended())
{
Emit8(0x41);
}
Emit8(0x58 + r.GetId8());
}
void X64CodeGenerator::Push(Register<8, false> r)
{
// EmitRex() would set REX.W, but this instruction defaults to
// 64-bit operands in 64-bit mode and doesn't need it.
if (r.IsExtended())
{
Emit8(0x41);
}
Emit8(0x50 + r.GetId8());
}
void X64CodeGenerator::Ret()
{
Emit8(0xc3);
}
//*************************************************************************
//
// X64CodeGenerator::Helper<Op> methods.
//
//*************************************************************************
template <>
template <>
template <>
void X64CodeGenerator::Helper<OpCode::Call>::ArgTypes1<false>::Emit(X64CodeGenerator& code, Register<8, false> dest)
{
code.Call(dest);
}
template <>
template <>
template <>
void X64CodeGenerator::Helper<OpCode::Pop>::ArgTypes1<false>::Emit(X64CodeGenerator& code, Register<8, false> dest)
{
code.Pop(dest);
}
template <>
template <>
template <>
void X64CodeGenerator::Helper<OpCode::Push>::ArgTypes1<false>::Emit(X64CodeGenerator& code, Register<8, false> dest)
{
code.Push(dest);
}
template <> void X64CodeGenerator::Helper<OpCode::Rep>::Emit(X64CodeGenerator& code)
{
code.Emit8(0xf3);
}
template <> void X64CodeGenerator::Helper<OpCode::Ret>::Emit(X64CodeGenerator& code)
{
code.Ret();
}
template <> void X64CodeGenerator::Helper<OpCode::Stosq>::Emit(X64CodeGenerator& code)
{
code.Emit8(0x48);
code.Emit8(0xab);
}
template <>
template <>
template <>
void X64CodeGenerator::Helper<OpCode::MovZX>::ArgTypes2<false, false>::Emit(
X64CodeGenerator& code,
Register<4, false> dest,
Register<4, false> src)
{
Helper<OpCode::Mov>::ArgTypes1<false>::Emit<4>(code, dest, src);
}
// Full specialization of MovZX opcode for "movzx dest64, src32" which is
// implemented in terms of "mov dest32, src32".
template <>
template <>
template <>
void X64CodeGenerator::Helper<OpCode::MovZX>::ArgTypes2<false, false>::Emit(
X64CodeGenerator& code,
Register<8, false> dest,
Register<4, false> src)
{
const Register<4, false> dest4(dest);
Helper<OpCode::Mov>::ArgTypes1<false>::Emit<4>(code, dest4, src);
}
template <>
template <>
template <>
void X64CodeGenerator::Helper<OpCode::MovZX>::ArgTypes2<false, false>::Emit<8, 4>(
X64CodeGenerator& code,
Register<8, false> dest,
Register<8, false> src,
int32_t srcOffset)
{
const Register<4, false> dest4(dest);
Helper<OpCode::Mov>::ArgTypes1<false>::Emit<4>(code, dest4, src, srcOffset);
}
//
// IosMiniStateRestorer
//
IosMiniStateRestorer::IosMiniStateRestorer(std::ios& stream)
: m_stream(stream),
m_flags(stream.flags()),
m_width(stream.width()),
m_fillChar(stream.fill())
{
}
IosMiniStateRestorer::~IosMiniStateRestorer()
{
m_stream.flags(m_flags);
m_stream.width(m_width);
m_stream.fill(m_fillChar);
}
//*************************************************************************
//
// Helper code printing methods.
//
//*************************************************************************
X64CodeGenerator::CodePrinter::CodePrinter(X64CodeGenerator& code)
: m_code(code),
m_out(code.IsDiagnosticsStreamAvailable()
? &code.GetDiagnosticsStream()
: nullptr)
{
NoteStartPosition();
}
void X64CodeGenerator::CodePrinter::NoteStartPosition()
{
m_startPosition = m_code.CurrentPosition();
}
void X64CodeGenerator::CodePrinter::PlaceLabel(Label label)
{
if (m_out != nullptr)
{
*m_out << "L" << label.GetId() << ":" << std::endl;
}
}
void X64CodeGenerator::CodePrinter::PrintJump(Label label)
{
if (m_out != nullptr)
{
PrintBytes(m_startPosition, m_code.CurrentPosition());
*m_out << "jmp L" << label.GetId() << std::endl;
}
}
void X64CodeGenerator::CodePrinter::PrintJump(void* function)
{
if (m_out != nullptr)
{
IosMiniStateRestorer state(*m_out);
PrintBytes(m_startPosition, m_code.CurrentPosition());
*m_out << "jmp " << std::uppercase << std::hex << function << 'h' << std::endl;
}
}
void X64CodeGenerator::CodePrinter::Print(OpCode op)
{
if (m_out != nullptr)
{
PrintBytes(m_startPosition, m_code.CurrentPosition());
*m_out << OpCodeName(op) << std::endl;
}
}
char const * X64CodeGenerator::CodePrinter::GetPointerName(unsigned pointerSize)
{
switch (pointerSize)
{
case 1: return "byte";
case 2: return "word";
case 4: return "dword";
case 8: return "qword";
default: return "*** UNKNOWN ***";
}
}
const unsigned c_asmDataWidth = 36;
void X64CodeGenerator::CodePrinter::PrintBytes(unsigned start, unsigned end)
{
IosMiniStateRestorer state(*m_out);
// TODO: Support for printing '/' after REX prefixes?
// Alternative is unit test function can strip out white space and '/'.
uint8_t* startPtr = m_code.BufferStart() + start;
uint8_t* endPtr = m_code.BufferStart() + end;
m_out->fill('0');
*m_out << " ";
*m_out << std::uppercase << std::hex << std::setw(8) << start << " ";
unsigned column = 11;
while (startPtr < endPtr)
{
*m_out << std::setw(2) << static_cast<unsigned>(*startPtr++);
*m_out << " ";
column += 3;
}
while (column < c_asmDataWidth)
{
*m_out << ' ';
column++;
}
}
}
``` | /content/code_sandbox/src/CodeGen/X64CodeGenerator.cpp | c++ | 2016-04-09T23:53:19 | 2024-06-29T07:05:56 | NativeJIT | BitFunnel/NativeJIT | 1,133 | 2,839 |
```c++
// Permission is hereby granted, free of charge, to any person obtaining a copy
// of this software and associated documentation files (the "Software"), to deal
// in the Software without restriction, including without limitation the rights
// to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
// copies of the Software, and to permit persons to whom the Software is
// furnished to do so, subject to the following conditions:
// The above copyright notice and this permission notice shall be included in
// all copies or substantial portions of the Software.
// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
// AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
// LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
// OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
// THE SOFTWARE.
#include <algorithm> // For std::min.
#include <stdexcept>
#include "NativeJIT/BitOperations.h"
#include "NativeJIT/CodeGen/CallingConvention.h"
#include "NativeJIT/CodeGen/FunctionBuffer.h"
#include "NativeJIT/CodeGen/FunctionSpecification.h"
#include "UnwindCode.h"
namespace NativeJIT
{
//
// FunctionSpecificationBase
//
// Note: defining in .cpp file to avoid the need to include UnwindCode.h
// in FunctionSpecification.h.
const unsigned FunctionSpecification::c_maxUnwindInfoBufferSize
= sizeof(UnwindInfo)
- sizeof(UnwindCode) // Included in UnwindInfo.
+ c_maxUnwindCodes * sizeof(UnwindCode);
FunctionSpecification::FunctionSpecification(Allocators::IAllocator& allocator,
int maxFunctionCallParameters,
unsigned localStackSlotCount,
unsigned savedRxxNonVolatilesMask,
unsigned savedXmmNonVolatilesMask,
BaseRegisterType baseRegisterType,
std::ostream* diagnosticsStream)
: m_stlAllocator(allocator),
m_unwindInfoBuffer(m_stlAllocator),
m_prologCode(m_stlAllocator),
m_epilogCode(m_stlAllocator)
{
// The code in this buffer will not be executed directly, so the general
// allocator can be used for code buffer allocation.
X64CodeGenerator code(allocator, c_maxPrologOrEpilogSize);
if (diagnosticsStream != nullptr)
{
code.EnableDiagnostics(*diagnosticsStream);
}
BuildUnwindInfoAndProlog(maxFunctionCallParameters,
localStackSlotCount,
savedRxxNonVolatilesMask,
savedXmmNonVolatilesMask,
baseRegisterType,
code,
m_unwindInfoBuffer,
m_offsetToOriginalRsp);
m_prologCode.assign(code.BufferStart(),
code.BufferStart() + code.CurrentPosition());
code.Reset();
BuildEpilog(*reinterpret_cast<UnwindInfo*>(m_unwindInfoBuffer.data()),
code);
m_epilogCode.assign(code.BufferStart(),
code.BufferStart() + code.CurrentPosition());
}
namespace
{
// Populates the current UnwindCode with the provided values and updates
// the pointer to the predecessor unwind code (to facilitate reverse,
// epilog-like order of unwind codes). Verifies that the current code does
// not come before the starting boundary.
void AddCodeAndBackDown(UnwindCode const * unwindCodesStart,
UnwindCode*& currUnwindCode,
unsigned codeOffset,
UnwindCodeOp op,
uint8_t info)
{
LogThrowAssert(currUnwindCode >= unwindCodesStart, "Unwind codes overflow");
LogThrowAssert(codeOffset <= (std::numeric_limits<uint8_t>::max)(),
"Code offset overflow: %u",
codeOffset);
*currUnwindCode-- = UnwindCode(static_cast<uint8_t>(codeOffset),
op,
info);
}
// The flavor which populates unwind data that requires two unwind codes:
// one with core information and the other one with 16-bit value.
void AddCodeAndBackDown(UnwindCode const * unwindCodesStart,
UnwindCode*& currUnwindCode,
unsigned codeOffset,
UnwindCodeOp op,
uint8_t info,
uint16_t frameOffset)
{
// Since the codes are filled in reverse (epilog) order, place the
// second operand first.
LogThrowAssert(currUnwindCode >= unwindCodesStart, "Unwind codes overflow");
*currUnwindCode-- = UnwindCode(frameOffset);
AddCodeAndBackDown(unwindCodesStart, currUnwindCode, codeOffset, op, info);
}
}
void FunctionSpecification::BuildUnwindInfoAndProlog(int maxFunctionCallParameters,
unsigned localStackSlotCount,
unsigned savedRxxNonVolatilesMask,
unsigned savedXmmNonVolatilesMask,
BaseRegisterType baseRegisterType,
X64CodeGenerator& prologCode,
AllocatorVector<uint8_t>& unwindInfoBuffer,
int32_t& offsetToOriginalRsp)
{
LogThrowAssert((savedRxxNonVolatilesMask & ~CallingConvention::c_rxxWritableRegistersMask) == 0,
"Saving/restoring of non-writable RXX registers is not allowed: 0x%Ix",
savedRxxNonVolatilesMask & ~CallingConvention::c_rxxWritableRegistersMask);
LogThrowAssert((savedXmmNonVolatilesMask & ~CallingConvention::c_xmmWritableRegistersMask) == 0,
"Saving/restoring of non-writable XMM registers is not allowed: 0x%Ix",
savedXmmNonVolatilesMask & ~CallingConvention::c_xmmWritableRegistersMask);
// Stack pointer is always saved/restored. However, unlike for the other
// registers, it's done by subtracting/adding a value in the prolog/epilog.
savedRxxNonVolatilesMask &= ~rsp.GetMask();
// Ensure that the frame register is saved if used.
if (baseRegisterType == BaseRegisterType::SetRbpToOriginalRsp)
{
savedRxxNonVolatilesMask |= rbp.GetMask();
}
const unsigned codeStartPos = prologCode.CurrentPosition();
// If there are any function calls, at least 4 parameter slots need to
// be allocated regardless of the actual parameter count.
const unsigned functionParamsSlotCount
= maxFunctionCallParameters >= 0
? (std::max)(maxFunctionCallParameters, 4)
: 0;
const unsigned rxxSavesCount = BitOp::GetNonZeroBitCount(savedRxxNonVolatilesMask);
const unsigned xmmSavesCount = BitOp::GetNonZeroBitCount(savedXmmNonVolatilesMask);
// All 128 bits of XMM registers need to saved in the prolog, so each
// XMM register needs two slots. Also, XMM slots need to be 16-byte aligned,
// so reserve one additional slot which may be needed for alignment.
const unsigned regSavesSlotCount = rxxSavesCount
+ 2 * xmmSavesCount
+ (xmmSavesCount > 0 ? 1 : 0);
// Calculate the total number of allocated stack slots. Ensure it's odd
// since the stack pointer needs to be 16-byte aligned but it already
// has one slot used for the return address.
//
// Note: there are some cases when it's not required to align the stack.
// However, for simplicity and because the documentation is contradictory
// (some sources say alignment is unnecessary only when there are no
// function calls, some only when there is no stack allocation of any
// type) the stack is always aligned here.
//
// Stack layout after setup:
// [address 0] ---> [...]
// ---> [beginning of stack, 16-byte aligned; RSP adjusted by prolog points here]
// ---> [home space, empty or max(4, maxParametersInCallsByFunction); must be placed here]
// ---> [registers saved by prolog]
// ---> [local stack for temporaries etc]
// ---> [end of stack; original RSP pointed here; RBP points here if SetRbpToOriginalRsp]
// ---> [return address and parameters to the function]
const unsigned totalStackSlotCount
= (functionParamsSlotCount
+ regSavesSlotCount
+ localStackSlotCount)
| 1;
const unsigned totalStackBytes = totalStackSlotCount * sizeof(void*);
offsetToOriginalRsp = totalStackBytes;
LogThrowAssert(totalStackBytes > 0 && totalStackBytes <= c_maxStackSize,
"Invalid request for %u stack slots",
totalStackSlotCount);
// Need to use UWOP_ALLOC_SMALL for stack sizes from 8 to 128 bytes and
// UWOP_ALLOC_LARGE otherwise. If using UWOP_ALLOC_LARGE, currently only
// the version which uses two unwind codes is supported. That version
// can allocate almost 512 kB, which is far more than the 4 kB limit
// which would require a chkstk call.
const bool isSmallStackAlloc = totalStackBytes <= 128;
// Compute number of unwind codes needed. Each RXX/XMM save takes two
// codes and stack allocation takes 1 for UWOP_ALLOC_SMALL and 2 for
// UWOP_ALLOC_LARGE (also see the previous comment).
const unsigned actualUnwindCodeCount
= (rxxSavesCount + xmmSavesCount) * 2
+ (isSmallStackAlloc ? 1 : 2);
LogThrowAssert(actualUnwindCodeCount > 0
&& actualUnwindCodeCount <= c_maxUnwindCodes,
"Invalid number of unwind codes: %u",
actualUnwindCodeCount);
// From MSDN UNWIND_INFO documentation for unwind codes array:
// "For alignment purposes, this array will always have an even number
// of entries, with the final entry potentially unused (in which case
// the array will be one longer than indicated by the count of unwind
// codes field)."
const unsigned alignedCodeCount = (actualUnwindCodeCount + 1) & ~1u;
// Allocate the memory. Account for the fact that one unwind code is
// already included in UnwindInfo. Due to the check above that unwind
// count is positive, the calculation will not overflow.
unwindInfoBuffer.resize(sizeof(UnwindInfo)
+ (alignedCodeCount - 1)
* sizeof(UnwindCode));
UnwindInfo* unwindInfo = reinterpret_cast<UnwindInfo*>(unwindInfoBuffer.data());
// Initialize UnwindInfo.
unwindInfo->m_countOfCodes = static_cast<unsigned char>(actualUnwindCodeCount);
unwindInfo->m_version = 1;
unwindInfo->m_flags = 0;
unwindInfo->m_frameRegister = 0;
unwindInfo->m_frameOffset = 0;
// Unwind codes are placed to the array of codes in order that will be
// used in epilog (i.e. reverse order of steps), so locate the end first.
UnwindCode* unwindCodes = &unwindInfo->m_firstUnwindCode;
UnwindCode* currUnwindCode = &unwindCodes[actualUnwindCodeCount - 1];
// Start emitting the unwind codes and the opcodes for prolog. First,
// adjust the stack pointer.
prologCode.EmitImmediate<OpCode::Sub>(rsp, offsetToOriginalRsp);
// Emit the matching unwind codes.
if (isSmallStackAlloc)
{
LogThrowAssert(totalStackSlotCount >= 1 && totalStackSlotCount <= 16,
"Logic error, alloc small slot count %u",
totalStackSlotCount);
// The slot count values 1-16 are encoded as 0-15, so subtract one.
AddCodeAndBackDown(unwindCodes,
currUnwindCode,
prologCode.CurrentPosition() - codeStartPos,
UnwindCodeOp::UWOP_ALLOC_SMALL,
static_cast<uint8_t>(totalStackSlotCount - 1));
}
else
{
LogThrowAssert(totalStackSlotCount >= 17
&& totalStackSlotCount <= (std::numeric_limits<uint16_t>::max)(),
"Logic error, alloc large slot count %u",
totalStackSlotCount);
// Value of 0 for info argument signifies two-code version of
// UWOP_ALLOC_LARGE which is used for allocations from 136 to
// 512 kB - 8 bytes (i.e. 17 to 65535 slots).
AddCodeAndBackDown(unwindCodes,
currUnwindCode,
prologCode.CurrentPosition() - codeStartPos,
UnwindCodeOp::UWOP_ALLOC_LARGE,
static_cast<uint8_t>(0),
static_cast<uint16_t>(totalStackSlotCount));
}
// Save registers into the reserved area. The area comes right after
// the initial slots reserved for parameters for function calls.
unsigned currStackSlotOffset = functionParamsSlotCount;
unsigned regId = 0;
unsigned registersMask = savedRxxNonVolatilesMask;
// Save the RXX registers.
while (BitOp::GetLowestBitSet(registersMask, ®Id))
{
prologCode.Emit<OpCode::Mov>(rsp,
currStackSlotOffset * sizeof(void*),
Register<8, false>(regId));
AddCodeAndBackDown(unwindCodes,
currUnwindCode,
prologCode.CurrentPosition() - codeStartPos,
UnwindCodeOp::UWOP_SAVE_NONVOL,
static_cast<uint8_t>(regId),
static_cast<uint16_t>(currStackSlotOffset));
BitOp::ClearBit(®istersMask, regId);
currStackSlotOffset++;
}
// Save XMM registers.
if (xmmSavesCount > 0)
{
// Ensure that slot offset is even (16-byte aligned). The additional
// slot was already reserved for this case.
if ((currStackSlotOffset & 1) != 0)
{
currStackSlotOffset++;
}
registersMask = savedXmmNonVolatilesMask;
while (BitOp::GetLowestBitSet(registersMask, ®Id))
{
// Both movaps and movapd can be used here, but according to
// external tests, movaps is more performant.
prologCode.Emit<OpCode::MovAP>(
rsp,
currStackSlotOffset * sizeof(void*),
Register<4, true>(regId));
// The offset specifies 16-byte slots, thus the divide by two.
// The offset was previously verified to be even.
AddCodeAndBackDown(unwindCodes,
currUnwindCode,
prologCode.CurrentPosition() - codeStartPos,
UnwindCodeOp::UWOP_SAVE_XMM128,
static_cast<uint8_t>(regId),
static_cast<uint16_t>(currStackSlotOffset / 2));
BitOp::ClearBit(®istersMask, regId);
currStackSlotOffset += 2;
}
}
// Ensure that the unwind codes were filled exactly as planned by
// comparing the last filled code with the beginning of the array. Since
// currUnwindCode points to the place where the *next* code would have
// been placed, currUnwindCode + 1 points to the last placed code.
LogThrowAssert(currUnwindCode + 1 == unwindCodes,
"Mismatched count of unwind codes: %Id",
currUnwindCode + 1 - unwindCodes);
// Point the RBP to the original RSP value. Note: not using UWOP_SET_FPREG
// since 1) it's not necessary on x64 as setting the base pointer is
// only an optional convenience 2) The offset is limited to [0, 240] range,
// which may not be enough and 3) some documentation sources state that
// if used, UWOP_SET_FPREG must occur before any register saves that
// specify offset, which complicates this function needlessly.
if (baseRegisterType == BaseRegisterType::SetRbpToOriginalRsp)
{
// It's necessary to extend the last unwind code that recorded an
// instruction offset into prolog to account for the instruction
// to be added to set up RBP.
LogThrowAssert(unwindCodes[0].m_operation.m_codeOffset
== prologCode.CurrentPosition() - codeStartPos,
"Logical error in RBP adjustment, instruction offset %u vs %u",
unwindCodes[0].m_operation.m_codeOffset,
prologCode.CurrentPosition() - codeStartPos);
prologCode.Emit<OpCode::Lea>(rbp, rsp, offsetToOriginalRsp);
// Note: the cast is safe, the code buffer is length limited to
// max size for prolog/epilog.
unwindCodes[0].m_operation.m_codeOffset
= static_cast<uint8_t>(prologCode.CurrentPosition() - codeStartPos);
}
// Code offset points to the next instruction after the end of prolog,
// so (given that prolog starts from offset 0) it also specifies the
// size of prolog.
unwindInfo->m_sizeOfProlog = unwindCodes[0].m_operation.m_codeOffset;
}
// A helper function to return the number of unwind codes for an opcode.
static unsigned GetUnwindOpCodeCount(UnwindCode code)
{
switch (static_cast<UnwindCodeOp>(code.m_operation.m_unwindOp))
{
case UnwindCodeOp::UWOP_ALLOC_SMALL:
case UnwindCodeOp::UWOP_PUSH_MACHFRAME:
case UnwindCodeOp::UWOP_PUSH_NONVOL:
case UnwindCodeOp::UWOP_SET_FPREG:
return 1;
case UnwindCodeOp::UWOP_SAVE_NONVOL:
case UnwindCodeOp::UWOP_SAVE_XMM128:
return 2;
case UnwindCodeOp::UWOP_SAVE_NONVOL_FAR:
case UnwindCodeOp::UWOP_SAVE_XMM128_FAR:
return 3;
case UnwindCodeOp::UWOP_ALLOC_LARGE:
LogThrowAssert(code.m_operation.m_opInfo <= 1,
"Invalid OpInfo for UWOP_ALLOC_LARGE: %u",
code.m_operation.m_opInfo);
return code.m_operation.m_opInfo == 0 ? 2 : 3;
default:
LogThrowAbort("Unknown unwind operation %u", code.m_operation.m_unwindOp);
// Silence the "not all paths return a value" warning.
return 0;
}
}
void FunctionSpecification::BuildEpilog(UnwindInfo const & unwindInfo,
X64CodeGenerator& epilogCode)
{
UnwindCode const * codes = &unwindInfo.m_firstUnwindCode;
unsigned i = 0;
while (i < unwindInfo.m_countOfCodes)
{
const UnwindCode unwindCode = codes[i];
// Check how many codes the operation needs.
const unsigned codeCount = GetUnwindOpCodeCount(unwindCode);
LogThrowAssert(i + codeCount <= unwindInfo.m_countOfCodes,
"Not enough unwind codes for op %u",
unwindCode.m_operation.m_unwindOp);
// For 2 or more codes, read the data for the second code (always
// the m_frameOffset union member).
const unsigned code2Offset = codeCount >= 2
? codes[i + 1].m_frameOffset
: 0;
switch (static_cast<UnwindCodeOp>(unwindCode.m_operation.m_unwindOp))
{
case UnwindCodeOp::UWOP_ALLOC_LARGE:
LogThrowAssert(codeCount == 2, "Unexpected %u-code UWOP_ALLOC_LARGE", codeCount);
// The second code contains the offset in quadwords.
epilogCode.EmitImmediate<OpCode::Add>(rsp,
static_cast<int32_t>(code2Offset
* sizeof(void*)));
break;
case UnwindCodeOp::UWOP_ALLOC_SMALL:
// The second code contains the slot count (in quadwords)
// decreased by one.
epilogCode.EmitImmediate<OpCode::Add>(
rsp,
static_cast<int32_t>((unwindCode.m_operation.m_opInfo + 1)
* sizeof(void*)));
break;
case UnwindCodeOp::UWOP_SAVE_NONVOL:
// The second code contains the offset in quadwords.
epilogCode.Emit<OpCode::Mov>(Register<8, false>(unwindCode.m_operation.m_opInfo),
rsp,
code2Offset * sizeof(void*));
break;
case UnwindCodeOp::UWOP_SAVE_XMM128:
// The second code contains the halved offset in quadwords.
epilogCode.Emit<OpCode::MovAP>(
Register<4, true>(unwindCode.m_operation.m_opInfo),
rsp,
code2Offset * 2 * sizeof(void*));
break;
default:
LogThrowAbort("Unsupported unwind operation %u", unwindCode.m_operation.m_unwindOp);
break;
}
i += codeCount;
}
// Return to caller.
epilogCode.Emit<OpCode::Ret>();
}
int32_t FunctionSpecification::GetOffsetToOriginalRsp() const
{
return m_offsetToOriginalRsp;
}
uint8_t const * FunctionSpecification::GetUnwindInfoBuffer() const
{
return m_unwindInfoBuffer.data();
}
unsigned FunctionSpecification::GetUnwindInfoByteLength() const
{
return static_cast<unsigned>(m_unwindInfoBuffer.size());
}
uint8_t const * FunctionSpecification::GetProlog() const
{
return m_prologCode.data();
}
unsigned FunctionSpecification::GetPrologLength() const
{
return static_cast<unsigned>(m_prologCode.size());
}
uint8_t const * FunctionSpecification::GetEpilog() const
{
return m_epilogCode.data();
}
unsigned FunctionSpecification::GetEpilogLength() const
{
return static_cast<unsigned>(m_epilogCode.size());
}
}
``` | /content/code_sandbox/src/CodeGen/FunctionSpecification.cpp | c++ | 2016-04-09T23:53:19 | 2024-06-29T07:05:56 | NativeJIT | BitFunnel/NativeJIT | 1,133 | 4,949 |
```c++
// Permission is hereby granted, free of charge, to any person obtaining a copy
// of this software and associated documentation files (the "Software"), to deal
// in the Software without restriction, including without limitation the rights
// to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
// copies of the Software, and to permit persons to whom the Software is
// furnished to do so, subject to the following conditions:
// The above copyright notice and this permission notice shall be included in
// all copies or substantial portions of the Software.
// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
// AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
// LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
// OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
// THE SOFTWARE.
#include <stdexcept>
#include "NativeJIT/CodeGen/FunctionBuffer.h"
#include "NativeJIT/CodeGen/FunctionSpecification.h"
#include "UnwindCode.h"
// linux x64 stack unwinding
// path_to_url
// path_to_url
// path_to_url
// path_to_url
// path_to_url#JIT-Interface
// linux x64 ABI
// path_to_url
namespace NativeJIT
{
//*************************************************************************
//
// FunctionBuffer
//
//*************************************************************************
#ifdef NATIVEJIT_PLATFORM_WINDOWS
RUNTIME_FUNCTION*
FunctionBuffer::WindowsGetRuntimeFunctionCallback(DWORD64 controlPc, void* context)
{
auto const pc = reinterpret_cast<uint8_t const *>(controlPc);
auto const fb = reinterpret_cast<FunctionBuffer /* const */ *>(context);
auto const runtime = &fb->m_runtimeFunction;
// Check whether program counter is inside function's code.
return ((fb->BufferStart() + runtime->BeginAddress <= pc)
&& (pc < fb->BufferStart() + runtime->EndAddress))
? runtime
: nullptr;
}
#endif
FunctionBuffer::FunctionBuffer(Allocators::IAllocator& codeAllocator,
unsigned capacity)
: X64CodeGenerator(codeAllocator, capacity),
m_runtimeFunction(),
m_unwindInfoStartOffset(0),
m_unwindInfoByteLength(0),
m_prologStartOffset(0),
m_prologLength(0),
m_isCodeGenerationCompleted(false)
{
LogThrowAssert(reinterpret_cast<size_t>(&m_runtimeFunction) % sizeof(DWORD) == 0,
"RUNTIME_FUNCTION must be DWORD aligned");
#ifdef NATIVEJIT_PLATFORM_WINDOWS
// Register a callback to return the RUNTIME_FUNCTION when Windows
// asks for it during exception handling.
if (!RtlInstallFunctionTableCallback(UnwindUtils::MakeFunctionTableIdentifier(this),
reinterpret_cast<DWORD64>(BufferStart()),
GetCapacity(),
&FunctionBuffer::WindowsGetRuntimeFunctionCallback,
this,
nullptr))
{
throw std::runtime_error("Couldn't install function table callback");
}
#endif
}
FunctionBuffer::~FunctionBuffer()
{
#ifdef NATIVEJIT_PLATFORM_WINDOWS
// From MSDN about the argument to RtlDeleteFunctionTable: "A pointer to
// ... or an identifier previously passed to RtlInstallFunctionTableCallback."
// TODO: return code not checked as there's nothing else to do on error but
// log, however no logging facility is available right now.
auto entry = reinterpret_cast<RUNTIME_FUNCTION*>(
UnwindUtils::MakeFunctionTableIdentifier(this));
RtlDeleteFunctionTable(entry);
#endif
}
void const * FunctionBuffer::GetEntryPoint() const
{
LogThrowAssert(m_isCodeGenerationCompleted,
"Cannot get entry point until code generation is finalized");
return BufferStart() + m_runtimeFunction.BeginAddress;
}
unsigned FunctionBuffer::GetFunctionCodeStartOffset() const
{
LogThrowAssert(m_isCodeGenerationCompleted,
"Cannot get start offset until code generation is finalized");
return m_runtimeFunction.BeginAddress;
}
unsigned FunctionBuffer::GetFunctionCodeEndOffset() const
{
LogThrowAssert(m_isCodeGenerationCompleted,
"Cannot get end offset until code generation is finalized");
return m_runtimeFunction.EndAddress;
}
unsigned FunctionBuffer::GetUnwindInfoStartOffset() const
{
LogThrowAssert(m_isCodeGenerationCompleted,
"Cannot get unwind info offset until code generation is finalized");
return m_runtimeFunction.UnwindData;
}
void FunctionBuffer::BeginFunctionBodyGeneration(FunctionSpecification const & spec)
{
BeginFunctionBodyGeneration(spec.GetUnwindInfoByteLength(),
spec.GetPrologLength());
}
void FunctionBuffer::BeginFunctionBodyGeneration()
{
// Function specification is unknown at this point. Reserve enough
// space for unwind info and prolog to be filled in after it's known.
BeginFunctionBodyGeneration(FunctionSpecification::c_maxUnwindInfoBufferSize,
FunctionSpecification::c_maxPrologOrEpilogSize);
}
void FunctionBuffer::BeginFunctionBodyGeneration(unsigned reservedUnwindInfoLength,
unsigned reservedPrologLength)
{
LogThrowAssert(!m_isCodeGenerationCompleted, "Code generation has already been completed");
LogThrowAssert(reservedUnwindInfoLength % sizeof(DWORD) == 0,
"Unaligned reserved UnwindInfo length of %u bytes",
reservedUnwindInfoLength);
// Begining of UnwindInfo must be DWORD-aligned.
AdvanceToAlignment<DWORD>();
m_unwindInfoStartOffset = CurrentPosition();
m_unwindInfoByteLength = reservedUnwindInfoLength;
Advance(m_unwindInfoByteLength);
m_prologStartOffset = CurrentPosition();
m_prologLength = reservedPrologLength;
Advance(m_prologLength);
}
void FunctionBuffer::EndFunctionBodyGeneration(FunctionSpecification const & spec)
{
LogThrowAssert(spec.GetUnwindInfoByteLength() <= m_unwindInfoByteLength,
"Unwind info length of %u bytes is larger than the reserved %u bytes",
spec.GetUnwindInfoByteLength(),
m_unwindInfoByteLength);
LogThrowAssert(spec.GetPrologLength() <= m_prologLength,
"Prolog length of %u bytes is larger than the reserved %u bytes",
spec.GetPrologLength(),
m_prologLength);
// Write the unwind info to the buffer.
// Note: alignment for start and max size of the target has already been
// verified in BeginFunctionBodyGeneration().
ReplaceBytes(m_unwindInfoStartOffset,
spec.GetUnwindInfoBuffer(),
spec.GetUnwindInfoByteLength());
m_unwindInfoByteLength = spec.GetUnwindInfoByteLength();
// If more bytes was reserved than was needed for the prolog, adjust
// the offset and length so that the end of the prolog is adjascent to
// the beginning of the body of the function.
if (spec.GetPrologLength() < m_prologLength)
{
const unsigned delta = m_prologLength - spec.GetPrologLength();
m_prologStartOffset += delta;
m_prologLength -= delta;
}
ReplaceBytes(m_prologStartOffset,
spec.GetProlog(),
spec.GetPrologLength());
// Emit the epilog at the current position.
EmitBytes(spec.GetEpilog(), spec.GetEpilogLength());
// Patch any references to labels.
PatchCallSites();
// Fill in information about the function.
m_runtimeFunction.BeginAddress = m_prologStartOffset;
m_runtimeFunction.EndAddress = CurrentPosition();
m_runtimeFunction.UnwindData = m_unwindInfoStartOffset;
m_isCodeGenerationCompleted = true;
}
void FunctionBuffer::Reset()
{
X64CodeGenerator::Reset();
m_unwindInfoStartOffset
= m_unwindInfoByteLength
= m_prologStartOffset
= m_prologLength
= 0;
m_isCodeGenerationCompleted = false;
m_runtimeFunction = {0, 0, 0};
}
}
``` | /content/code_sandbox/src/CodeGen/FunctionBuffer.cpp | c++ | 2016-04-09T23:53:19 | 2024-06-29T07:05:56 | NativeJIT | BitFunnel/NativeJIT | 1,133 | 1,767 |
```c++
// Permission is hereby granted, free of charge, to any person obtaining a copy
// of this software and associated documentation files (the "Software"), to deal
// in the Software without restriction, including without limitation the rights
// to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
// copies of the Software, and to permit persons to whom the Software is
// furnished to do so, subject to the following conditions:
// The above copyright notice and this permission notice shall be included in
// all copies or substantial portions of the Software.
// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
// AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
// LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
// OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
// THE SOFTWARE.
#include "NativeJIT/CodeGen/Register.h"
#include "UnwindCode.h"
namespace NativeJIT
{
//*************************************************************************
//
// UnwindCode
//
//*************************************************************************
UnwindCode::UnwindCode()
{
}
UnwindCode::UnwindCode(uint16_t frameOffset)
: m_frameOffset(frameOffset)
{
}
UnwindCode::UnwindCode(uint8_t codeOffset,
UnwindCodeOp op,
uint8_t info)
{
// Note: cannot use initializer list as VC++ doesn't support it (error
// C2797 "List initialization inside member initializer list or
// non-static data member initializer is not implemented."
m_operation.m_codeOffset = codeOffset;
m_operation.m_unwindOp = static_cast<uint8_t>(op);
m_operation.m_opInfo = info;
}
namespace UnwindUtils
{
DWORD64 MakeFunctionTableIdentifier(void* objectAddress)
{
// Per MSDN RtlInstallFunctionTableCallback() documentation:
// "The two low-order bits must be set. For example, BaseAddress|0x3."
return reinterpret_cast<DWORD64>(objectAddress) | 3;
}
}
}
``` | /content/code_sandbox/src/CodeGen/UnwindCode.cpp | c++ | 2016-04-09T23:53:19 | 2024-06-29T07:05:56 | NativeJIT | BitFunnel/NativeJIT | 1,133 | 486 |
```c++
// Permission is hereby granted, free of charge, to any person obtaining a copy
// of this software and associated documentation files (the "Software"), to deal
// in the Software without restriction, including without limitation the rights
// to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
// copies of the Software, and to permit persons to whom the Software is
// furnished to do so, subject to the following conditions:
// The above copyright notice and this permission notice shall be included in
// all copies or substantial portions of the Software.
// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
// AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
// LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
// OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
// THE SOFTWARE.
#include "NativeJIT/CodeGen/Register.h"
namespace NativeJIT
{
unsigned RegisterBase::c_sizes[c_maxSize + 1] = {
0,
0, // 1 bytes
1, // 2 bytes
0,
2, // 4 bytes
0,
0,
0,
3 // 8 bytes
};
// TODO: These names are not in the same order as the declarations below.
char const * RegisterBase::c_names[c_typesCount][c_validSizesCount][c_maxRegisterID + 1] =
{
{
{ "al", "cl", "dl", "bl", "spl", "bpl", "dil", "sil", "r8b", "r9b", "r10b", "r11b", "r12b", "r13b", "r14b", "r15b" },
{ "ax", "cx", "dx", "bx", "sp", "bp", "si", "di", "r8w", "r9w", "r10w", "r11w", "r12w", "r13w", "r14w", "r15w" },
{ "eax", "ecx", "edx", "ebx", "esp", "ebp", "esi", "edi", "r8d", "r9d", "r10d", "r11d", "r12d", "r13d", "r14d", "r15d" },
{ "rax", "rcx", "rdx", "rbx", "rsp", "rbp", "rsi", "rdi", "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", "rip" },
},
{
{},
{},
{ "xmm0s", "xmm1s", "xmm2s", "xmm3s", "xmm4s", "xmm5s", "xmm6s", "xmm7s",
"xmm8s", "xmm9s", "xmm10s", "xmm11s", "xmm12s", "xmm13s", "xmm14s", "xmm15s"},
{ "xmm0d", "xmm1d", "xmm2d", "xmm3d", "xmm4d", "xmm5d", "xmm6d", "xmm7d",
"xmm8d", "xmm9d", "xmm10d", "xmm11d", "xmm12d", "xmm13d", "xmm14d", "xmm15d"}
}
};
Register<1, false> al(0);
Register<1, false> cl(1);
Register<1, false> dl(2);
Register<1, false> bl(3);
Register<1, false> spl(4);
Register<1, false> bpl(5);
Register<1, false> sil(6);
Register<1, false> dil(7);
Register<1, false> r8b(8);
Register<1, false> r9b(9);
Register<1, false> r10b(10);
Register<1, false> r11b(11);
Register<1, false> r12b(12);
Register<1, false> r13b(13);
Register<1, false> r14b(14);
Register<1, false> r15b(15);
Register<2, false> ax(0);
Register<2, false> cx(1);
Register<2, false> dx(2);
Register<2, false> bx(3);
Register<2, false> sp(4);
Register<2, false> bp(5);
Register<2, false> si(6);
Register<2, false> di(7);
Register<2, false> r8w(8);
Register<2, false> r9w(9);
Register<2, false> r10w(10);
Register<2, false> r11w(11);
Register<2, false> r12w(12);
Register<2, false> r13w(13);
Register<2, false> r14w(14);
Register<2, false> r15w(15);
Register<4, false> eax(0);
Register<4, false> ecx(1);
Register<4, false> edx(2);
Register<4, false> ebx(3);
Register<4, false> esp(4);
Register<4, false> ebp(5);
Register<4, false> esi(6);
Register<4, false> edi(7);
Register<4, false> r8d(8);
Register<4, false> r9d(9);
Register<4, false> r10d(10);
Register<4, false> r11d(11);
Register<4, false> r12d(12);
Register<4, false> r13d(13);
Register<4, false> r14d(14);
Register<4, false> r15d(15);
Register<8, false> rax(0);
Register<8, false> rcx(1);
Register<8, false> rdx(2);
Register<8, false> rbx(3);
Register<8, false> rsp(4);
Register<8, false> rbp(5);
Register<8, false> rsi(6);
Register<8, false> rdi(7);
Register<8, false> r8(8);
Register<8, false> r9(9);
Register<8, false> r10(10);
Register<8, false> r11(11);
Register<8, false> r12(12);
Register<8, false> r13(13);
Register<8, false> r14(14);
Register<8, false> r15(15);
Register<8, false> rip(16);
Register<4, true> xmm0s(0);
Register<4, true> xmm1s(1);
Register<4, true> xmm2s(2);
Register<4, true> xmm3s(3);
Register<4, true> xmm4s(4);
Register<4, true> xmm5s(5);
Register<4, true> xmm6s(6);
Register<4, true> xmm7s(7);
Register<4, true> xmm8s(8);
Register<4, true> xmm9s(9);
Register<4, true> xmm10s(10);
Register<4, true> xmm11s(11);
Register<4, true> xmm12s(12);
Register<4, true> xmm13s(13);
Register<4, true> xmm14s(14);
Register<4, true> xmm15s(15);
Register<8, true> xmm0(0);
Register<8, true> xmm1(1);
Register<8, true> xmm2(2);
Register<8, true> xmm3(3);
Register<8, true> xmm4(4);
Register<8, true> xmm5(5);
Register<8, true> xmm6(6);
Register<8, true> xmm7(7);
Register<8, true> xmm8(8);
Register<8, true> xmm9(9);
Register<8, true> xmm10(10);
Register<8, true> xmm11(11);
Register<8, true> xmm12(12);
Register<8, true> xmm13(13);
Register<8, true> xmm14(14);
Register<8, true> xmm15(15);
}
``` | /content/code_sandbox/src/CodeGen/Register.cpp | c++ | 2016-04-09T23:53:19 | 2024-06-29T07:05:56 | NativeJIT | BitFunnel/NativeJIT | 1,133 | 1,989 |
```c++
// Permission is hereby granted, free of charge, to any person obtaining a copy
// of this software and associated documentation files (the "Software"), to deal
// in the Software without restriction, including without limitation the rights
// to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
// copies of the Software, and to permit persons to whom the Software is
// furnished to do so, subject to the following conditions:
// The above copyright notice and this permission notice shall be included in
// all copies or substantial portions of the Software.
// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
// AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
// LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
// OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
// THE SOFTWARE.
#include <cstddef>
#include <limits>
#include <stdexcept>
#include "Temporary/Assert.h"
#include "NativeJIT/CodeGen/JumpTable.h"
namespace NativeJIT
{
const unsigned c_labelsReserveCount = 512;
const unsigned c_callSitesReserveCount = 512;
JumpTable::JumpTable()
{
m_labels.reserve(c_labelsReserveCount);
m_callSites.reserve(c_callSitesReserveCount);
}
void JumpTable::Clear()
{
m_labels.clear();
m_callSites.clear();
}
Label JumpTable::AllocateLabel()
{
Label label = Label(m_labels.size());
m_labels.push_back(NULL);
return label;
}
void JumpTable::PlaceLabel(Label label, const uint8_t* address)
{
if (LabelIsDefined(label))
{
throw std::runtime_error("CodeBuffer: attempting to place label more than once.");
}
m_labels[label.GetId()] = address;
}
void JumpTable::AddCallSite(Label label, uint8_t* site, unsigned size)
{
m_callSites.push_back(CallSite(label, size, site));
}
bool JumpTable::LabelIsDefined(Label label) const
{
return m_labels.at(label.GetId()) != NULL;
}
const uint8_t* JumpTable::AddressOfLabel(Label label) const
{
if (!LabelIsDefined(label))
{
throw std::runtime_error("CodeBuffer: attempting to use a label that hasn't been placed.");
}
return m_labels[label.GetId()];
}
// WARNING: Non portable. Assumes little endian machine architecture.
// WARNING: Non portable. Assumes that fixup value is labelAddress - siteAddress - size.Size().
void JumpTable::PatchCallSites()
{
for (size_t i=0; i < m_callSites.size(); ++i)
{
const CallSite& site = m_callSites[i];
const uint8_t* labelAddress = AddressOfLabel(site.GetLabel());
uint8_t* siteAddress = site.Site();
ptrdiff_t delta = labelAddress - siteAddress - site.Size();
// TODO: Evaluate whether special cases for size == 2 and size == 4 actually improve performance.
size_t size = site.Size();
if (size == 2)
{
LogThrowAssert(delta <= std::numeric_limits<int16_t>::max() &&
delta >= std::numeric_limits<int16_t>::min(),
"Overflow/underflow in cast to int16_t.");
*(reinterpret_cast<int16_t*>(siteAddress)) = static_cast<int16_t>(delta);
siteAddress += size;
}
else if (size == 4)
{
LogThrowAssert(delta <= std::numeric_limits<int32_t>::max() &&
delta >= std::numeric_limits<int32_t>::min(),
"Overflow/underflow in cast to int32_t.");
*(reinterpret_cast<int32_t*>(siteAddress)) = static_cast<int32_t>(delta);
siteAddress += size;
}
else
{
while (size > 0)
{
*siteAddress++ = static_cast<uint8_t>(delta);
delta = delta >> 8;
size--;
}
}
}
}
//*************************************************************************
//
// CallSite
//
//*************************************************************************
CallSite::CallSite()
: m_label(0)
{
m_site = NULL;
}
CallSite::CallSite(Label label, unsigned size, uint8_t* site)
: m_label(label)
{
m_size = size;
m_site = site;
}
Label CallSite::GetLabel() const
{
return m_label;
}
size_t CallSite::Size() const
{
return m_size;
}
uint8_t* CallSite::Site() const
{
return m_site;
}
}
``` | /content/code_sandbox/src/CodeGen/JumpTable.cpp | c++ | 2016-04-09T23:53:19 | 2024-06-29T07:05:56 | NativeJIT | BitFunnel/NativeJIT | 1,133 | 1,062 |
```c++
// Permission is hereby granted, free of charge, to any person obtaining a copy
// of this software and associated documentation files (the "Software"), to deal
// in the Software without restriction, including without limitation the rights
// to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
// copies of the Software, and to permit persons to whom the Software is
// furnished to do so, subject to the following conditions:
// The above copyright notice and this permission notice shall be included in
// all copies or substantial portions of the Software.
// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
// AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
// LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
// OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
// THE SOFTWARE.
#include <cstring>
#include "Temporary/Allocator.h"
#include "Temporary/Assert.h"
namespace NativeJIT
{
//*************************************************************************
//
// Allocator
//
//*************************************************************************
Allocator::Allocator(size_t bufferSize)
: m_bufferSize(bufferSize),
m_bytesAllocated(0),
m_buffer(new char[bufferSize])
{
DebugInitialize();
}
Allocator::~Allocator()
{
}
void* Allocator::Allocate(size_t size)
{
LogThrowAssert(m_bytesAllocated + size <= m_bufferSize, "Out of memory");
void* result = static_cast<void*>(m_buffer.get() + m_bytesAllocated);
m_bytesAllocated += size;
return result;
}
void Allocator::Deallocate(void* block)
{
LogThrowAssert(static_cast<char*>(block) >= m_buffer.get() &&
static_cast<char*>(block) < m_buffer.get() + m_bytesAllocated,
"Attempting to deallocate memory not owned by this allocator.");
// Intentional NOP
}
size_t Allocator::MaxSize() const
{
return m_bufferSize;
}
void Allocator::Reset()
{
m_bytesAllocated = 0;
DebugInitialize();
}
void Allocator::DebugInitialize()
{
memset(m_buffer.get(), 0xcc, m_bufferSize);
}
}
``` | /content/code_sandbox/src/CodeGen/Allocator.cpp | c++ | 2016-04-09T23:53:19 | 2024-06-29T07:05:56 | NativeJIT | BitFunnel/NativeJIT | 1,133 | 511 |
```c++
// Permission is hereby granted, free of charge, to any person obtaining a copy
// of this software and associated documentation files (the "Software"), to deal
// in the Software without restriction, including without limitation the rights
// to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
// copies of the Software, and to permit persons to whom the Software is
// furnished to do so, subject to the following conditions:
// The above copyright notice and this permission notice shall be included in
// all copies or substantial portions of the Software.
// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
// AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
// LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
// OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
// THE SOFTWARE.
#include <stdexcept>
#ifdef NATIVEJIT_PLATFORM_WINDOWS
#include <Windows.h>
#else
#include <sys/mman.h>
#include <unistd.h>
#endif
#include "NativeJIT/CodeGen/ExecutionBuffer.h"
namespace NativeJIT
{
//*************************************************************************
//
// ExecutionBuffer
//
//*************************************************************************
// Rounds x up to the nearest size, where size is a power of 2.
size_t RoundUp(size_t x, size_t powerOfTwo)
{
return (x + powerOfTwo - 1) & (~(powerOfTwo - 1));
}
// path_to_url
#ifdef NATIVEJIT_PLATFORM_WINDOWS
ExecutionBuffer::ExecutionBuffer(size_t bufferSize)
: m_buffer(nullptr),
m_bytesAllocated(0)
{
SYSTEM_INFO systemInfo;
GetSystemInfo(&systemInfo);
m_bufferSize = RoundUp(bufferSize, systemInfo.dwPageSize);
// Allocate m_bufferSize bytes plus one extra page that will act as
// a write-guard to detect buffer overruns.
m_buffer = (unsigned char*)VirtualAlloc(NULL, m_bufferSize + systemInfo.dwPageSize,
MEM_COMMIT, PAGE_EXECUTE_READWRITE);
if (m_buffer == NULL)
{
throw std::runtime_error("CodeBuffer: out of memory.");
}
// Set protection on the guard page.
DWORD oldProtection;
if (!VirtualProtect(m_buffer + m_bufferSize, systemInfo.dwPageSize,
PAGE_NOACCESS, &oldProtection))
{
// TODO: Fix memory leaks by f. ex. using unique_ptr with custom deleter
// for m_buffer. See bug#13
throw std::runtime_error("CodeBuffer: failed to set protection on guard page.");
}
DebugInitialize();
}
#else
ExecutionBuffer::ExecutionBuffer(size_t bufferSize)
: m_bytesAllocated(0),
m_buffer(nullptr)
{
m_bufferSize = RoundUp(bufferSize, getpagesize());
m_buffer = static_cast<unsigned char*>(
mmap(nullptr,
m_bufferSize,
PROT_READ | PROT_WRITE | PROT_EXEC,
MAP_PRIVATE | MAP_ANON,
-1,
0));
if (m_buffer == MAP_FAILED) {
// TODO: Fix memory leaks by f. ex. using unique_ptr with custom deleter
// for m_buffer. See bug#13
throw std::runtime_error("CodeBuffer: failed to set protection on guard page.");
}
}
#endif
#ifdef NATIVEJIT_PLATFORM_WINDOWS
ExecutionBuffer::~ExecutionBuffer()
{
if (m_buffer != nullptr)
{
if (VirtualFree(m_buffer, 0, MEM_RELEASE) == 0)
{
// TODO: Fix this See bug#13
// throw std::runtime_error("CodeBuffer: VirtualFree failed.");
}
}
}
#else
ExecutionBuffer::~ExecutionBuffer()
{
if (m_buffer != nullptr)
{
if (munmap(m_buffer, m_bufferSize) != 0)
{
// TODO: Fix this. See bug#13
// throw std::runtime_error("CodeBuffer: munmap failed.");
}
}
}
#endif
//
// IAllocator methods
//
// Allocates a block of a specified byte size.
void* ExecutionBuffer::Allocate(size_t size)
{
LogThrowAssert(m_bytesAllocated + size <= m_bufferSize, "Out of memory");
void* result = static_cast<void*>(m_buffer + m_bytesAllocated);
m_bytesAllocated += size;
return result;
}
// Frees a block.
void ExecutionBuffer::Deallocate(void* /*block*/)
{
// Intentional NOP
}
// Returns the maximum legal allocation size in bytes.
size_t ExecutionBuffer::MaxSize() const
{
return m_bufferSize;
}
// Frees all blocks that have been allocated since construction or the
// last call to Reset().
void ExecutionBuffer::Reset()
{
m_bytesAllocated = 0;
DebugInitialize();
}
void ExecutionBuffer::DebugInitialize()
{
#ifdef _DEBUG
// Fill the buffer with break code (i.e. INT 3 software breakpoint).
memset(m_buffer, 0xcc, m_bufferSize);
#endif
}
}
``` | /content/code_sandbox/src/CodeGen/ExecutionBuffer.cpp | c++ | 2016-04-09T23:53:19 | 2024-06-29T07:05:56 | NativeJIT | BitFunnel/NativeJIT | 1,133 | 1,146 |
```c++
// Permission is hereby granted, free of charge, to any person obtaining a copy
// of this software and associated documentation files (the "Software"), to deal
// in the Software without restriction, including without limitation the rights
// to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
// copies of the Software, and to permit persons to whom the Software is
// furnished to do so, subject to the following conditions:
// The above copyright notice and this permission notice shall be included in
// all copies or substantial portions of the Software.
// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
// AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
// LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
// OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
// THE SOFTWARE.
#include <cstdarg>
#include <stdexcept>
#include <sstream>
#include <vector>
#include "Temporary/Assert.h"
namespace NativeJIT
{
void LogThrowImpl(char const * filename,
char const * function,
unsigned lineNumber,
char const * title,
char const * format,
...)
{
const unsigned messageBufferSize = 1024;
char message[messageBufferSize];
va_list arguments;
va_start(arguments, format);
#ifdef _MSC_VER
vsnprintf_s(message, _TRUNCATE, format, arguments);
#else
vsnprintf(&message[0], messageBufferSize, format, arguments);
#endif
va_end(arguments);
std::stringstream sstream;
sstream << "Assertion " << title << " failed in " << function
<< " at " << filename << ":" << lineNumber << ": " << message;
throw std::runtime_error(sstream.str().c_str());
}
}
``` | /content/code_sandbox/src/CodeGen/Assert.cpp | c++ | 2016-04-09T23:53:19 | 2024-06-29T07:05:56 | NativeJIT | BitFunnel/NativeJIT | 1,133 | 417 |
```c++
// Permission is hereby granted, free of charge, to any person obtaining a copy
// of this software and associated documentation files (the "Software"), to deal
// in the Software without restriction, including without limitation the rights
// to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
// copies of the Software, and to permit persons to whom the Software is
// furnished to do so, subject to the following conditions:
// The above copyright notice and this permission notice shall be included in
// all copies or substantial portions of the Software.
// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
// AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
// LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
// OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
// THE SOFTWARE.
#include <cstring>
#include "NativeJIT/CodeGen/CodeBuffer.h"
#include "Temporary/IAllocator.h"
namespace NativeJIT
{
CodeBuffer::CodeBuffer(Allocators::IAllocator& codeAllocator, unsigned capacity)
: m_codeAllocator(codeAllocator),
m_capacity(capacity),
m_bufferStart(nullptr)
{
m_bufferStart = static_cast<uint8_t*>(codeAllocator.Allocate(capacity));
m_bufferEnd = m_bufferStart + capacity;
m_current = m_bufferStart;
}
CodeBuffer::~CodeBuffer()
{
m_codeAllocator.Deallocate(m_bufferStart);
}
Label CodeBuffer::AllocateLabel()
{
return m_localJumpTable.AllocateLabel();
}
void CodeBuffer::PlaceLabel(Label label)
{
m_localJumpTable.PlaceLabel(label, m_current);
}
void CodeBuffer::EmitBytes(uint8_t const *data, unsigned length)
{
VerifyNoBufferOverflow(length);
memcpy(m_current, data, length);
m_current += length;
}
void CodeBuffer::Emit8(uint8_t x)
{
EmitBytes(x);
}
void CodeBuffer::Emit16(uint16_t x)
{
EmitBytes(x);
}
void CodeBuffer::Emit32(uint32_t x)
{
EmitBytes(x);
}
void CodeBuffer::Emit64(uint64_t x)
{
EmitBytes(x);
}
void CodeBuffer::ReplaceBytes(unsigned startPosition,
uint8_t const *data,
unsigned length)
{
LogThrowAssert(startPosition + length <= CurrentPosition(),
"Cannot replace parts of the buffer that have not been populated "
"(populated: [0, %u), wanted [%u, %u))",
CurrentPosition(),
startPosition,
startPosition + length);
memmove(&m_bufferStart[startPosition], data, length);
}
unsigned CodeBuffer::GetCapacity() const
{
return m_capacity;
}
uint8_t* CodeBuffer::BufferStart() const
{
return m_bufferStart;
}
unsigned CodeBuffer::CurrentPosition() const
{
return static_cast<unsigned>(m_current - m_bufferStart);
}
void CodeBuffer::Reset()
{
m_current = m_bufferStart;
m_localJumpTable.Clear();
}
uint8_t* CodeBuffer::Advance(int byteCount)
{
VerifyNoBufferOverflow(byteCount);
uint8_t* start = m_current;
m_current += byteCount;
return start;
}
void CodeBuffer::Fill(unsigned start, unsigned length, uint8_t value)
{
VerifyNoBufferOverflow(length);
memset(m_bufferStart + start, value, length);
}
void CodeBuffer::PatchCallSites()
{
m_localJumpTable.PatchCallSites();
}
void CodeBuffer::EmitCallSite(Label label, unsigned size)
{
m_localJumpTable.AddCallSite(label, m_current, size);
#ifdef _DEBUG
while (size-- > 0)
{
Emit8(0);
}
#else
Advance(size);
#endif
}
}
``` | /content/code_sandbox/src/CodeGen/CodeBuffer.cpp | c++ | 2016-04-09T23:53:19 | 2024-06-29T07:05:56 | NativeJIT | BitFunnel/NativeJIT | 1,133 | 896 |
```assembly
; Permission is hereby granted, free of charge, to any person obtaining a copy
; of this software and associated documentation files (the "Software"), to deal
; in the Software without restriction, including without limitation the rights
; to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
; copies of the Software, and to permit persons to whom the Software is
; furnished to do so, subject to the following conditions:
; The above copyright notice and this permission notice shall be included in
; all copies or substantial portions of the Software.
; THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
; IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
; FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
; AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
; LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
; OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
; THE SOFTWARE.
.code
instructions PROC
; Int <-> Int
; Source: rax, target: rax
mov al, 1
mov ax, 1
mov eax, 1
mov rax, 1
mov al, al
mov ax, ax
mov eax, eax
mov rax, rax
mov al, byte ptr [rax - 4]
mov al, byte ptr [rax + 4]
mov ax, word ptr [rax + 4]
mov eax, dword ptr [rax + 4]
mov rax, qword ptr [rax + 4]
mov byte ptr [rax - 4], al
mov byte ptr [rax + 4], al
mov word ptr [rax + 4], ax
mov dword ptr [rax + 4], eax
mov qword ptr [rax + 4], rax
movzx ax, al
movzx ax, byte ptr [rax + 4]
movzx eax, al
movzx eax, ax
movzx eax, byte ptr [rax + 4]
movzx eax, word ptr [rax + 4]
movzx rax, al
movzx rax, ax
movzx rax, byte ptr [rax + 4]
movzx rax, word ptr [rax + 4]
; Source: rax, target: rcx
mov cl, 1
mov cx, 1
mov ecx, 1
mov rcx, 1
mov cl, al
mov cx, ax
mov ecx, eax
mov rcx, rax
mov cl, byte ptr [rax - 4]
mov cl, byte ptr [rax + 4]
mov cx, word ptr [rax + 4]
mov ecx, dword ptr [rax + 4]
mov rcx, qword ptr [rax + 4]
mov byte ptr [rcx - 4], al
mov byte ptr [rcx + 4], al
mov word ptr [rcx + 4], ax
mov dword ptr [rcx + 4], eax
mov qword ptr [rcx + 4], rax
movzx cx, al
movzx cx, byte ptr [rax + 4]
movzx ecx, al
movzx ecx, ax
movzx ecx, byte ptr [rax + 4]
movzx ecx, word ptr [rax + 4]
movzx rcx, al
movzx rcx, ax
movzx rcx, byte ptr [rax + 4]
movzx rcx, word ptr [rax + 4]
; Source: rax, target: rdx
mov dl, 1
mov dx, 1
mov edx, 1
mov rdx, 1
mov dl, al
mov dx, ax
mov edx, eax
mov rdx, rax
mov dl, byte ptr [rax - 4]
mov dl, byte ptr [rax + 4]
mov dx, word ptr [rax + 4]
mov edx, dword ptr [rax + 4]
mov rdx, qword ptr [rax + 4]
mov byte ptr [rdx - 4], al
mov byte ptr [rdx + 4], al
mov word ptr [rdx + 4], ax
mov dword ptr [rdx + 4], eax
mov qword ptr [rdx + 4], rax
movzx dx, al
movzx dx, byte ptr [rax + 4]
movzx edx, al
movzx edx, ax
movzx edx, byte ptr [rax + 4]
movzx edx, word ptr [rax + 4]
movzx rdx, al
movzx rdx, ax
movzx rdx, byte ptr [rax + 4]
movzx rdx, word ptr [rax + 4]
; Source: rax, target: rbx
mov bl, 1
mov bx, 1
mov ebx, 1
mov rbx, 1
mov bl, al
mov bx, ax
mov ebx, eax
mov rbx, rax
mov bl, byte ptr [rax - 4]
mov bl, byte ptr [rax + 4]
mov bx, word ptr [rax + 4]
mov ebx, dword ptr [rax + 4]
mov rbx, qword ptr [rax + 4]
mov byte ptr [rbx - 4], al
mov byte ptr [rbx + 4], al
mov word ptr [rbx + 4], ax
mov dword ptr [rbx + 4], eax
mov qword ptr [rbx + 4], rax
movzx bx, al
movzx bx, byte ptr [rax + 4]
movzx ebx, al
movzx ebx, ax
movzx ebx, byte ptr [rax + 4]
movzx ebx, word ptr [rax + 4]
movzx rbx, al
movzx rbx, ax
movzx rbx, byte ptr [rax + 4]
movzx rbx, word ptr [rax + 4]
; Source: rax, target: rsp
mov spl, 1
mov sp, 1
mov esp, 1
mov rsp, 1
mov spl, al
mov sp, ax
mov esp, eax
mov rsp, rax
mov spl, byte ptr [rax - 4]
mov spl, byte ptr [rax + 4]
mov sp, word ptr [rax + 4]
mov esp, dword ptr [rax + 4]
mov rsp, qword ptr [rax + 4]
mov byte ptr [rsp - 4], al
mov byte ptr [rsp + 4], al
mov word ptr [rsp + 4], ax
mov dword ptr [rsp + 4], eax
mov qword ptr [rsp + 4], rax
movzx sp, al
movzx sp, byte ptr [rax + 4]
movzx esp, al
movzx esp, ax
movzx esp, byte ptr [rax + 4]
movzx esp, word ptr [rax + 4]
movzx rsp, al
movzx rsp, ax
movzx rsp, byte ptr [rax + 4]
movzx rsp, word ptr [rax + 4]
; Source: rax, target: rbp
mov bpl, 1
mov bp, 1
mov ebp, 1
mov rbp, 1
mov bpl, al
mov bp, ax
mov ebp, eax
mov rbp, rax
mov bpl, byte ptr [rax - 4]
mov bpl, byte ptr [rax + 4]
mov bp, word ptr [rax + 4]
mov ebp, dword ptr [rax + 4]
mov rbp, qword ptr [rax + 4]
mov byte ptr [rbp - 4], al
mov byte ptr [rbp + 4], al
mov word ptr [rbp + 4], ax
mov dword ptr [rbp + 4], eax
mov qword ptr [rbp + 4], rax
movzx bp, al
movzx bp, byte ptr [rax + 4]
movzx ebp, al
movzx ebp, ax
movzx ebp, byte ptr [rax + 4]
movzx ebp, word ptr [rax + 4]
movzx rbp, al
movzx rbp, ax
movzx rbp, byte ptr [rax + 4]
movzx rbp, word ptr [rax + 4]
; Source: rax, target: rsi
mov dil, 1
mov si, 1
mov esi, 1
mov rsi, 1
mov dil, al
mov si, ax
mov esi, eax
mov rsi, rax
mov dil, byte ptr [rax - 4]
mov dil, byte ptr [rax + 4]
mov si, word ptr [rax + 4]
mov esi, dword ptr [rax + 4]
mov rsi, qword ptr [rax + 4]
mov byte ptr [rsi - 4], al
mov byte ptr [rsi + 4], al
mov word ptr [rsi + 4], ax
mov dword ptr [rsi + 4], eax
mov qword ptr [rsi + 4], rax
movzx si, al
movzx si, byte ptr [rax + 4]
movzx esi, al
movzx esi, ax
movzx esi, byte ptr [rax + 4]
movzx esi, word ptr [rax + 4]
movzx rsi, al
movzx rsi, ax
movzx rsi, byte ptr [rax + 4]
movzx rsi, word ptr [rax + 4]
; Source: rax, target: rdi
mov sil, 1
mov di, 1
mov edi, 1
mov rdi, 1
mov sil, al
mov di, ax
mov edi, eax
mov rdi, rax
mov sil, byte ptr [rax - 4]
mov sil, byte ptr [rax + 4]
mov di, word ptr [rax + 4]
mov edi, dword ptr [rax + 4]
mov rdi, qword ptr [rax + 4]
mov byte ptr [rdi - 4], al
mov byte ptr [rdi + 4], al
mov word ptr [rdi + 4], ax
mov dword ptr [rdi + 4], eax
mov qword ptr [rdi + 4], rax
movzx di, al
movzx di, byte ptr [rax + 4]
movzx edi, al
movzx edi, ax
movzx edi, byte ptr [rax + 4]
movzx edi, word ptr [rax + 4]
movzx rdi, al
movzx rdi, ax
movzx rdi, byte ptr [rax + 4]
movzx rdi, word ptr [rax + 4]
; Source: rax, target: r8
mov r8b, 1
mov r8w, 1
mov r8d, 1
mov r8, 1
mov r8b, al
mov r8w, ax
mov r8d, eax
mov r8, rax
mov r8b, byte ptr [rax - 4]
mov r8b, byte ptr [rax + 4]
mov r8w, word ptr [rax + 4]
mov r8d, dword ptr [rax + 4]
mov r8, qword ptr [rax + 4]
mov byte ptr [r8 - 4], al
mov byte ptr [r8 + 4], al
mov word ptr [r8 + 4], ax
mov dword ptr [r8 + 4], eax
mov qword ptr [r8 + 4], rax
movzx r8w, al
movzx r8w, byte ptr [rax + 4]
movzx r8d, al
movzx r8d, ax
movzx r8d, byte ptr [rax + 4]
movzx r8d, word ptr [rax + 4]
movzx r8, al
movzx r8, ax
movzx r8, byte ptr [rax + 4]
movzx r8, word ptr [rax + 4]
; Source: rax, target: r9
mov r9b, 1
mov r9w, 1
mov r9d, 1
mov r9, 1
mov r9b, al
mov r9w, ax
mov r9d, eax
mov r9, rax
mov r9b, byte ptr [rax - 4]
mov r9b, byte ptr [rax + 4]
mov r9w, word ptr [rax + 4]
mov r9d, dword ptr [rax + 4]
mov r9, qword ptr [rax + 4]
mov byte ptr [r9 - 4], al
mov byte ptr [r9 + 4], al
mov word ptr [r9 + 4], ax
mov dword ptr [r9 + 4], eax
mov qword ptr [r9 + 4], rax
movzx r9w, al
movzx r9w, byte ptr [rax + 4]
movzx r9d, al
movzx r9d, ax
movzx r9d, byte ptr [rax + 4]
movzx r9d, word ptr [rax + 4]
movzx r9, al
movzx r9, ax
movzx r9, byte ptr [rax + 4]
movzx r9, word ptr [rax + 4]
; Source: rax, target: r10
mov r10b, 1
mov r10w, 1
mov r10d, 1
mov r10, 1
mov r10b, al
mov r10w, ax
mov r10d, eax
mov r10, rax
mov r10b, byte ptr [rax - 4]
mov r10b, byte ptr [rax + 4]
mov r10w, word ptr [rax + 4]
mov r10d, dword ptr [rax + 4]
mov r10, qword ptr [rax + 4]
mov byte ptr [r10 - 4], al
mov byte ptr [r10 + 4], al
mov word ptr [r10 + 4], ax
mov dword ptr [r10 + 4], eax
mov qword ptr [r10 + 4], rax
movzx r10w, al
movzx r10w, byte ptr [rax + 4]
movzx r10d, al
movzx r10d, ax
movzx r10d, byte ptr [rax + 4]
movzx r10d, word ptr [rax + 4]
movzx r10, al
movzx r10, ax
movzx r10, byte ptr [rax + 4]
movzx r10, word ptr [rax + 4]
; Source: rax, target: r11
mov r11b, 1
mov r11w, 1
mov r11d, 1
mov r11, 1
mov r11b, al
mov r11w, ax
mov r11d, eax
mov r11, rax
mov r11b, byte ptr [rax - 4]
mov r11b, byte ptr [rax + 4]
mov r11w, word ptr [rax + 4]
mov r11d, dword ptr [rax + 4]
mov r11, qword ptr [rax + 4]
mov byte ptr [r11 - 4], al
mov byte ptr [r11 + 4], al
mov word ptr [r11 + 4], ax
mov dword ptr [r11 + 4], eax
mov qword ptr [r11 + 4], rax
movzx r11w, al
movzx r11w, byte ptr [rax + 4]
movzx r11d, al
movzx r11d, ax
movzx r11d, byte ptr [rax + 4]
movzx r11d, word ptr [rax + 4]
movzx r11, al
movzx r11, ax
movzx r11, byte ptr [rax + 4]
movzx r11, word ptr [rax + 4]
; Source: rax, target: r12
mov r12b, 1
mov r12w, 1
mov r12d, 1
mov r12, 1
mov r12b, al
mov r12w, ax
mov r12d, eax
mov r12, rax
mov r12b, byte ptr [rax - 4]
mov r12b, byte ptr [rax + 4]
mov r12w, word ptr [rax + 4]
mov r12d, dword ptr [rax + 4]
mov r12, qword ptr [rax + 4]
mov byte ptr [r12 - 4], al
mov byte ptr [r12 + 4], al
mov word ptr [r12 + 4], ax
mov dword ptr [r12 + 4], eax
mov qword ptr [r12 + 4], rax
movzx r12w, al
movzx r12w, byte ptr [rax + 4]
movzx r12d, al
movzx r12d, ax
movzx r12d, byte ptr [rax + 4]
movzx r12d, word ptr [rax + 4]
movzx r12, al
movzx r12, ax
movzx r12, byte ptr [rax + 4]
movzx r12, word ptr [rax + 4]
; Source: rax, target: r13
mov r13b, 1
mov r13w, 1
mov r13d, 1
mov r13, 1
mov r13b, al
mov r13w, ax
mov r13d, eax
mov r13, rax
mov r13b, byte ptr [rax - 4]
mov r13b, byte ptr [rax + 4]
mov r13w, word ptr [rax + 4]
mov r13d, dword ptr [rax + 4]
mov r13, qword ptr [rax + 4]
mov byte ptr [r13 - 4], al
mov byte ptr [r13 + 4], al
mov word ptr [r13 + 4], ax
mov dword ptr [r13 + 4], eax
mov qword ptr [r13 + 4], rax
movzx r13w, al
movzx r13w, byte ptr [rax + 4]
movzx r13d, al
movzx r13d, ax
movzx r13d, byte ptr [rax + 4]
movzx r13d, word ptr [rax + 4]
movzx r13, al
movzx r13, ax
movzx r13, byte ptr [rax + 4]
movzx r13, word ptr [rax + 4]
; Source: rax, target: r14
mov r14b, 1
mov r14w, 1
mov r14d, 1
mov r14, 1
mov r14b, al
mov r14w, ax
mov r14d, eax
mov r14, rax
mov r14b, byte ptr [rax - 4]
mov r14b, byte ptr [rax + 4]
mov r14w, word ptr [rax + 4]
mov r14d, dword ptr [rax + 4]
mov r14, qword ptr [rax + 4]
mov byte ptr [r14 - 4], al
mov byte ptr [r14 + 4], al
mov word ptr [r14 + 4], ax
mov dword ptr [r14 + 4], eax
mov qword ptr [r14 + 4], rax
movzx r14w, al
movzx r14w, byte ptr [rax + 4]
movzx r14d, al
movzx r14d, ax
movzx r14d, byte ptr [rax + 4]
movzx r14d, word ptr [rax + 4]
movzx r14, al
movzx r14, ax
movzx r14, byte ptr [rax + 4]
movzx r14, word ptr [rax + 4]
; Source: rax, target: r15
mov r15b, 1
mov r15w, 1
mov r15d, 1
mov r15, 1
mov r15b, al
mov r15w, ax
mov r15d, eax
mov r15, rax
mov r15b, byte ptr [rax - 4]
mov r15b, byte ptr [rax + 4]
mov r15w, word ptr [rax + 4]
mov r15d, dword ptr [rax + 4]
mov r15, qword ptr [rax + 4]
mov byte ptr [r15 - 4], al
mov byte ptr [r15 + 4], al
mov word ptr [r15 + 4], ax
mov dword ptr [r15 + 4], eax
mov qword ptr [r15 + 4], rax
movzx r15w, al
movzx r15w, byte ptr [rax + 4]
movzx r15d, al
movzx r15d, ax
movzx r15d, byte ptr [rax + 4]
movzx r15d, word ptr [rax + 4]
movzx r15, al
movzx r15, ax
movzx r15, byte ptr [rax + 4]
movzx r15, word ptr [rax + 4]
; Source: rcx, target: rax
mov al, 1
mov ax, 1
mov eax, 1
mov rax, 1
mov al, cl
mov ax, cx
mov eax, ecx
mov rax, rcx
mov al, byte ptr [rcx - 4]
mov al, byte ptr [rcx + 4]
mov ax, word ptr [rcx + 4]
mov eax, dword ptr [rcx + 4]
mov rax, qword ptr [rcx + 4]
mov byte ptr [rax - 4], cl
mov byte ptr [rax + 4], cl
mov word ptr [rax + 4], cx
mov dword ptr [rax + 4], ecx
mov qword ptr [rax + 4], rcx
movzx ax, cl
movzx ax, byte ptr [rcx + 4]
movzx eax, cl
movzx eax, cx
movzx eax, byte ptr [rcx + 4]
movzx eax, word ptr [rcx + 4]
movzx rax, cl
movzx rax, cx
movzx rax, byte ptr [rcx + 4]
movzx rax, word ptr [rcx + 4]
; Source: rcx, target: rcx
mov cl, 1
mov cx, 1
mov ecx, 1
mov rcx, 1
mov cl, cl
mov cx, cx
mov ecx, ecx
mov rcx, rcx
mov cl, byte ptr [rcx - 4]
mov cl, byte ptr [rcx + 4]
mov cx, word ptr [rcx + 4]
mov ecx, dword ptr [rcx + 4]
mov rcx, qword ptr [rcx + 4]
mov byte ptr [rcx - 4], cl
mov byte ptr [rcx + 4], cl
mov word ptr [rcx + 4], cx
mov dword ptr [rcx + 4], ecx
mov qword ptr [rcx + 4], rcx
movzx cx, cl
movzx cx, byte ptr [rcx + 4]
movzx ecx, cl
movzx ecx, cx
movzx ecx, byte ptr [rcx + 4]
movzx ecx, word ptr [rcx + 4]
movzx rcx, cl
movzx rcx, cx
movzx rcx, byte ptr [rcx + 4]
movzx rcx, word ptr [rcx + 4]
; Source: rcx, target: rdx
mov dl, 1
mov dx, 1
mov edx, 1
mov rdx, 1
mov dl, cl
mov dx, cx
mov edx, ecx
mov rdx, rcx
mov dl, byte ptr [rcx - 4]
mov dl, byte ptr [rcx + 4]
mov dx, word ptr [rcx + 4]
mov edx, dword ptr [rcx + 4]
mov rdx, qword ptr [rcx + 4]
mov byte ptr [rdx - 4], cl
mov byte ptr [rdx + 4], cl
mov word ptr [rdx + 4], cx
mov dword ptr [rdx + 4], ecx
mov qword ptr [rdx + 4], rcx
movzx dx, cl
movzx dx, byte ptr [rcx + 4]
movzx edx, cl
movzx edx, cx
movzx edx, byte ptr [rcx + 4]
movzx edx, word ptr [rcx + 4]
movzx rdx, cl
movzx rdx, cx
movzx rdx, byte ptr [rcx + 4]
movzx rdx, word ptr [rcx + 4]
; Source: rcx, target: rbx
mov bl, 1
mov bx, 1
mov ebx, 1
mov rbx, 1
mov bl, cl
mov bx, cx
mov ebx, ecx
mov rbx, rcx
mov bl, byte ptr [rcx - 4]
mov bl, byte ptr [rcx + 4]
mov bx, word ptr [rcx + 4]
mov ebx, dword ptr [rcx + 4]
mov rbx, qword ptr [rcx + 4]
mov byte ptr [rbx - 4], cl
mov byte ptr [rbx + 4], cl
mov word ptr [rbx + 4], cx
mov dword ptr [rbx + 4], ecx
mov qword ptr [rbx + 4], rcx
movzx bx, cl
movzx bx, byte ptr [rcx + 4]
movzx ebx, cl
movzx ebx, cx
movzx ebx, byte ptr [rcx + 4]
movzx ebx, word ptr [rcx + 4]
movzx rbx, cl
movzx rbx, cx
movzx rbx, byte ptr [rcx + 4]
movzx rbx, word ptr [rcx + 4]
; Source: rcx, target: rsp
mov spl, 1
mov sp, 1
mov esp, 1
mov rsp, 1
mov spl, cl
mov sp, cx
mov esp, ecx
mov rsp, rcx
mov spl, byte ptr [rcx - 4]
mov spl, byte ptr [rcx + 4]
mov sp, word ptr [rcx + 4]
mov esp, dword ptr [rcx + 4]
mov rsp, qword ptr [rcx + 4]
mov byte ptr [rsp - 4], cl
mov byte ptr [rsp + 4], cl
mov word ptr [rsp + 4], cx
mov dword ptr [rsp + 4], ecx
mov qword ptr [rsp + 4], rcx
movzx sp, cl
movzx sp, byte ptr [rcx + 4]
movzx esp, cl
movzx esp, cx
movzx esp, byte ptr [rcx + 4]
movzx esp, word ptr [rcx + 4]
movzx rsp, cl
movzx rsp, cx
movzx rsp, byte ptr [rcx + 4]
movzx rsp, word ptr [rcx + 4]
; Source: rcx, target: rbp
mov bpl, 1
mov bp, 1
mov ebp, 1
mov rbp, 1
mov bpl, cl
mov bp, cx
mov ebp, ecx
mov rbp, rcx
mov bpl, byte ptr [rcx - 4]
mov bpl, byte ptr [rcx + 4]
mov bp, word ptr [rcx + 4]
mov ebp, dword ptr [rcx + 4]
mov rbp, qword ptr [rcx + 4]
mov byte ptr [rbp - 4], cl
mov byte ptr [rbp + 4], cl
mov word ptr [rbp + 4], cx
mov dword ptr [rbp + 4], ecx
mov qword ptr [rbp + 4], rcx
movzx bp, cl
movzx bp, byte ptr [rcx + 4]
movzx ebp, cl
movzx ebp, cx
movzx ebp, byte ptr [rcx + 4]
movzx ebp, word ptr [rcx + 4]
movzx rbp, cl
movzx rbp, cx
movzx rbp, byte ptr [rcx + 4]
movzx rbp, word ptr [rcx + 4]
; Source: rcx, target: rsi
mov dil, 1
mov si, 1
mov esi, 1
mov rsi, 1
mov dil, cl
mov si, cx
mov esi, ecx
mov rsi, rcx
mov dil, byte ptr [rcx - 4]
mov dil, byte ptr [rcx + 4]
mov si, word ptr [rcx + 4]
mov esi, dword ptr [rcx + 4]
mov rsi, qword ptr [rcx + 4]
mov byte ptr [rsi - 4], cl
mov byte ptr [rsi + 4], cl
mov word ptr [rsi + 4], cx
mov dword ptr [rsi + 4], ecx
mov qword ptr [rsi + 4], rcx
movzx si, cl
movzx si, byte ptr [rcx + 4]
movzx esi, cl
movzx esi, cx
movzx esi, byte ptr [rcx + 4]
movzx esi, word ptr [rcx + 4]
movzx rsi, cl
movzx rsi, cx
movzx rsi, byte ptr [rcx + 4]
movzx rsi, word ptr [rcx + 4]
; Source: rcx, target: rdi
mov sil, 1
mov di, 1
mov edi, 1
mov rdi, 1
mov sil, cl
mov di, cx
mov edi, ecx
mov rdi, rcx
mov sil, byte ptr [rcx - 4]
mov sil, byte ptr [rcx + 4]
mov di, word ptr [rcx + 4]
mov edi, dword ptr [rcx + 4]
mov rdi, qword ptr [rcx + 4]
mov byte ptr [rdi - 4], cl
mov byte ptr [rdi + 4], cl
mov word ptr [rdi + 4], cx
mov dword ptr [rdi + 4], ecx
mov qword ptr [rdi + 4], rcx
movzx di, cl
movzx di, byte ptr [rcx + 4]
movzx edi, cl
movzx edi, cx
movzx edi, byte ptr [rcx + 4]
movzx edi, word ptr [rcx + 4]
movzx rdi, cl
movzx rdi, cx
movzx rdi, byte ptr [rcx + 4]
movzx rdi, word ptr [rcx + 4]
; Source: rcx, target: r8
mov r8b, 1
mov r8w, 1
mov r8d, 1
mov r8, 1
mov r8b, cl
mov r8w, cx
mov r8d, ecx
mov r8, rcx
mov r8b, byte ptr [rcx - 4]
mov r8b, byte ptr [rcx + 4]
mov r8w, word ptr [rcx + 4]
mov r8d, dword ptr [rcx + 4]
mov r8, qword ptr [rcx + 4]
mov byte ptr [r8 - 4], cl
mov byte ptr [r8 + 4], cl
mov word ptr [r8 + 4], cx
mov dword ptr [r8 + 4], ecx
mov qword ptr [r8 + 4], rcx
movzx r8w, cl
movzx r8w, byte ptr [rcx + 4]
movzx r8d, cl
movzx r8d, cx
movzx r8d, byte ptr [rcx + 4]
movzx r8d, word ptr [rcx + 4]
movzx r8, cl
movzx r8, cx
movzx r8, byte ptr [rcx + 4]
movzx r8, word ptr [rcx + 4]
; Source: rcx, target: r9
mov r9b, 1
mov r9w, 1
mov r9d, 1
mov r9, 1
mov r9b, cl
mov r9w, cx
mov r9d, ecx
mov r9, rcx
mov r9b, byte ptr [rcx - 4]
mov r9b, byte ptr [rcx + 4]
mov r9w, word ptr [rcx + 4]
mov r9d, dword ptr [rcx + 4]
mov r9, qword ptr [rcx + 4]
mov byte ptr [r9 - 4], cl
mov byte ptr [r9 + 4], cl
mov word ptr [r9 + 4], cx
mov dword ptr [r9 + 4], ecx
mov qword ptr [r9 + 4], rcx
movzx r9w, cl
movzx r9w, byte ptr [rcx + 4]
movzx r9d, cl
movzx r9d, cx
movzx r9d, byte ptr [rcx + 4]
movzx r9d, word ptr [rcx + 4]
movzx r9, cl
movzx r9, cx
movzx r9, byte ptr [rcx + 4]
movzx r9, word ptr [rcx + 4]
; Source: rcx, target: r10
mov r10b, 1
mov r10w, 1
mov r10d, 1
mov r10, 1
mov r10b, cl
mov r10w, cx
mov r10d, ecx
mov r10, rcx
mov r10b, byte ptr [rcx - 4]
mov r10b, byte ptr [rcx + 4]
mov r10w, word ptr [rcx + 4]
mov r10d, dword ptr [rcx + 4]
mov r10, qword ptr [rcx + 4]
mov byte ptr [r10 - 4], cl
mov byte ptr [r10 + 4], cl
mov word ptr [r10 + 4], cx
mov dword ptr [r10 + 4], ecx
mov qword ptr [r10 + 4], rcx
movzx r10w, cl
movzx r10w, byte ptr [rcx + 4]
movzx r10d, cl
movzx r10d, cx
movzx r10d, byte ptr [rcx + 4]
movzx r10d, word ptr [rcx + 4]
movzx r10, cl
movzx r10, cx
movzx r10, byte ptr [rcx + 4]
movzx r10, word ptr [rcx + 4]
; Source: rcx, target: r11
mov r11b, 1
mov r11w, 1
mov r11d, 1
mov r11, 1
mov r11b, cl
mov r11w, cx
mov r11d, ecx
mov r11, rcx
mov r11b, byte ptr [rcx - 4]
mov r11b, byte ptr [rcx + 4]
mov r11w, word ptr [rcx + 4]
mov r11d, dword ptr [rcx + 4]
mov r11, qword ptr [rcx + 4]
mov byte ptr [r11 - 4], cl
mov byte ptr [r11 + 4], cl
mov word ptr [r11 + 4], cx
mov dword ptr [r11 + 4], ecx
mov qword ptr [r11 + 4], rcx
movzx r11w, cl
movzx r11w, byte ptr [rcx + 4]
movzx r11d, cl
movzx r11d, cx
movzx r11d, byte ptr [rcx + 4]
movzx r11d, word ptr [rcx + 4]
movzx r11, cl
movzx r11, cx
movzx r11, byte ptr [rcx + 4]
movzx r11, word ptr [rcx + 4]
; Source: rcx, target: r12
mov r12b, 1
mov r12w, 1
mov r12d, 1
mov r12, 1
mov r12b, cl
mov r12w, cx
mov r12d, ecx
mov r12, rcx
mov r12b, byte ptr [rcx - 4]
mov r12b, byte ptr [rcx + 4]
mov r12w, word ptr [rcx + 4]
mov r12d, dword ptr [rcx + 4]
mov r12, qword ptr [rcx + 4]
mov byte ptr [r12 - 4], cl
mov byte ptr [r12 + 4], cl
mov word ptr [r12 + 4], cx
mov dword ptr [r12 + 4], ecx
mov qword ptr [r12 + 4], rcx
movzx r12w, cl
movzx r12w, byte ptr [rcx + 4]
movzx r12d, cl
movzx r12d, cx
movzx r12d, byte ptr [rcx + 4]
movzx r12d, word ptr [rcx + 4]
movzx r12, cl
movzx r12, cx
movzx r12, byte ptr [rcx + 4]
movzx r12, word ptr [rcx + 4]
; Source: rcx, target: r13
mov r13b, 1
mov r13w, 1
mov r13d, 1
mov r13, 1
mov r13b, cl
mov r13w, cx
mov r13d, ecx
mov r13, rcx
mov r13b, byte ptr [rcx - 4]
mov r13b, byte ptr [rcx + 4]
mov r13w, word ptr [rcx + 4]
mov r13d, dword ptr [rcx + 4]
mov r13, qword ptr [rcx + 4]
mov byte ptr [r13 - 4], cl
mov byte ptr [r13 + 4], cl
mov word ptr [r13 + 4], cx
mov dword ptr [r13 + 4], ecx
mov qword ptr [r13 + 4], rcx
movzx r13w, cl
movzx r13w, byte ptr [rcx + 4]
movzx r13d, cl
movzx r13d, cx
movzx r13d, byte ptr [rcx + 4]
movzx r13d, word ptr [rcx + 4]
movzx r13, cl
movzx r13, cx
movzx r13, byte ptr [rcx + 4]
movzx r13, word ptr [rcx + 4]
; Source: rcx, target: r14
mov r14b, 1
mov r14w, 1
mov r14d, 1
mov r14, 1
mov r14b, cl
mov r14w, cx
mov r14d, ecx
mov r14, rcx
mov r14b, byte ptr [rcx - 4]
mov r14b, byte ptr [rcx + 4]
mov r14w, word ptr [rcx + 4]
mov r14d, dword ptr [rcx + 4]
mov r14, qword ptr [rcx + 4]
mov byte ptr [r14 - 4], cl
mov byte ptr [r14 + 4], cl
mov word ptr [r14 + 4], cx
mov dword ptr [r14 + 4], ecx
mov qword ptr [r14 + 4], rcx
movzx r14w, cl
movzx r14w, byte ptr [rcx + 4]
movzx r14d, cl
movzx r14d, cx
movzx r14d, byte ptr [rcx + 4]
movzx r14d, word ptr [rcx + 4]
movzx r14, cl
movzx r14, cx
movzx r14, byte ptr [rcx + 4]
movzx r14, word ptr [rcx + 4]
; Source: rcx, target: r15
mov r15b, 1
mov r15w, 1
mov r15d, 1
mov r15, 1
mov r15b, cl
mov r15w, cx
mov r15d, ecx
mov r15, rcx
mov r15b, byte ptr [rcx - 4]
mov r15b, byte ptr [rcx + 4]
mov r15w, word ptr [rcx + 4]
mov r15d, dword ptr [rcx + 4]
mov r15, qword ptr [rcx + 4]
mov byte ptr [r15 - 4], cl
mov byte ptr [r15 + 4], cl
mov word ptr [r15 + 4], cx
mov dword ptr [r15 + 4], ecx
mov qword ptr [r15 + 4], rcx
movzx r15w, cl
movzx r15w, byte ptr [rcx + 4]
movzx r15d, cl
movzx r15d, cx
movzx r15d, byte ptr [rcx + 4]
movzx r15d, word ptr [rcx + 4]
movzx r15, cl
movzx r15, cx
movzx r15, byte ptr [rcx + 4]
movzx r15, word ptr [rcx + 4]
; Source: rdx, target: rax
mov al, 1
mov ax, 1
mov eax, 1
mov rax, 1
mov al, dl
mov ax, dx
mov eax, edx
mov rax, rdx
mov al, byte ptr [rdx - 4]
mov al, byte ptr [rdx + 4]
mov ax, word ptr [rdx + 4]
mov eax, dword ptr [rdx + 4]
mov rax, qword ptr [rdx + 4]
mov byte ptr [rax - 4], dl
mov byte ptr [rax + 4], dl
mov word ptr [rax + 4], dx
mov dword ptr [rax + 4], edx
mov qword ptr [rax + 4], rdx
movzx ax, dl
movzx ax, byte ptr [rdx + 4]
movzx eax, dl
movzx eax, dx
movzx eax, byte ptr [rdx + 4]
movzx eax, word ptr [rdx + 4]
movzx rax, dl
movzx rax, dx
movzx rax, byte ptr [rdx + 4]
movzx rax, word ptr [rdx + 4]
; Source: rdx, target: rcx
mov cl, 1
mov cx, 1
mov ecx, 1
mov rcx, 1
mov cl, dl
mov cx, dx
mov ecx, edx
mov rcx, rdx
mov cl, byte ptr [rdx - 4]
mov cl, byte ptr [rdx + 4]
mov cx, word ptr [rdx + 4]
mov ecx, dword ptr [rdx + 4]
mov rcx, qword ptr [rdx + 4]
mov byte ptr [rcx - 4], dl
mov byte ptr [rcx + 4], dl
mov word ptr [rcx + 4], dx
mov dword ptr [rcx + 4], edx
mov qword ptr [rcx + 4], rdx
movzx cx, dl
movzx cx, byte ptr [rdx + 4]
movzx ecx, dl
movzx ecx, dx
movzx ecx, byte ptr [rdx + 4]
movzx ecx, word ptr [rdx + 4]
movzx rcx, dl
movzx rcx, dx
movzx rcx, byte ptr [rdx + 4]
movzx rcx, word ptr [rdx + 4]
; Source: rdx, target: rdx
mov dl, 1
mov dx, 1
mov edx, 1
mov rdx, 1
mov dl, dl
mov dx, dx
mov edx, edx
mov rdx, rdx
mov dl, byte ptr [rdx - 4]
mov dl, byte ptr [rdx + 4]
mov dx, word ptr [rdx + 4]
mov edx, dword ptr [rdx + 4]
mov rdx, qword ptr [rdx + 4]
mov byte ptr [rdx - 4], dl
mov byte ptr [rdx + 4], dl
mov word ptr [rdx + 4], dx
mov dword ptr [rdx + 4], edx
mov qword ptr [rdx + 4], rdx
movzx dx, dl
movzx dx, byte ptr [rdx + 4]
movzx edx, dl
movzx edx, dx
movzx edx, byte ptr [rdx + 4]
movzx edx, word ptr [rdx + 4]
movzx rdx, dl
movzx rdx, dx
movzx rdx, byte ptr [rdx + 4]
movzx rdx, word ptr [rdx + 4]
; Source: rdx, target: rbx
mov bl, 1
mov bx, 1
mov ebx, 1
mov rbx, 1
mov bl, dl
mov bx, dx
mov ebx, edx
mov rbx, rdx
mov bl, byte ptr [rdx - 4]
mov bl, byte ptr [rdx + 4]
mov bx, word ptr [rdx + 4]
mov ebx, dword ptr [rdx + 4]
mov rbx, qword ptr [rdx + 4]
mov byte ptr [rbx - 4], dl
mov byte ptr [rbx + 4], dl
mov word ptr [rbx + 4], dx
mov dword ptr [rbx + 4], edx
mov qword ptr [rbx + 4], rdx
movzx bx, dl
movzx bx, byte ptr [rdx + 4]
movzx ebx, dl
movzx ebx, dx
movzx ebx, byte ptr [rdx + 4]
movzx ebx, word ptr [rdx + 4]
movzx rbx, dl
movzx rbx, dx
movzx rbx, byte ptr [rdx + 4]
movzx rbx, word ptr [rdx + 4]
; Source: rdx, target: rsp
mov spl, 1
mov sp, 1
mov esp, 1
mov rsp, 1
mov spl, dl
mov sp, dx
mov esp, edx
mov rsp, rdx
mov spl, byte ptr [rdx - 4]
mov spl, byte ptr [rdx + 4]
mov sp, word ptr [rdx + 4]
mov esp, dword ptr [rdx + 4]
mov rsp, qword ptr [rdx + 4]
mov byte ptr [rsp - 4], dl
mov byte ptr [rsp + 4], dl
mov word ptr [rsp + 4], dx
mov dword ptr [rsp + 4], edx
mov qword ptr [rsp + 4], rdx
movzx sp, dl
movzx sp, byte ptr [rdx + 4]
movzx esp, dl
movzx esp, dx
movzx esp, byte ptr [rdx + 4]
movzx esp, word ptr [rdx + 4]
movzx rsp, dl
movzx rsp, dx
movzx rsp, byte ptr [rdx + 4]
movzx rsp, word ptr [rdx + 4]
; Source: rdx, target: rbp
mov bpl, 1
mov bp, 1
mov ebp, 1
mov rbp, 1
mov bpl, dl
mov bp, dx
mov ebp, edx
mov rbp, rdx
mov bpl, byte ptr [rdx - 4]
mov bpl, byte ptr [rdx + 4]
mov bp, word ptr [rdx + 4]
mov ebp, dword ptr [rdx + 4]
mov rbp, qword ptr [rdx + 4]
mov byte ptr [rbp - 4], dl
mov byte ptr [rbp + 4], dl
mov word ptr [rbp + 4], dx
mov dword ptr [rbp + 4], edx
mov qword ptr [rbp + 4], rdx
movzx bp, dl
movzx bp, byte ptr [rdx + 4]
movzx ebp, dl
movzx ebp, dx
movzx ebp, byte ptr [rdx + 4]
movzx ebp, word ptr [rdx + 4]
movzx rbp, dl
movzx rbp, dx
movzx rbp, byte ptr [rdx + 4]
movzx rbp, word ptr [rdx + 4]
; Source: rdx, target: rsi
mov dil, 1
mov si, 1
mov esi, 1
mov rsi, 1
mov dil, dl
mov si, dx
mov esi, edx
mov rsi, rdx
mov dil, byte ptr [rdx - 4]
mov dil, byte ptr [rdx + 4]
mov si, word ptr [rdx + 4]
mov esi, dword ptr [rdx + 4]
mov rsi, qword ptr [rdx + 4]
mov byte ptr [rsi - 4], dl
mov byte ptr [rsi + 4], dl
mov word ptr [rsi + 4], dx
mov dword ptr [rsi + 4], edx
mov qword ptr [rsi + 4], rdx
movzx si, dl
movzx si, byte ptr [rdx + 4]
movzx esi, dl
movzx esi, dx
movzx esi, byte ptr [rdx + 4]
movzx esi, word ptr [rdx + 4]
movzx rsi, dl
movzx rsi, dx
movzx rsi, byte ptr [rdx + 4]
movzx rsi, word ptr [rdx + 4]
; Source: rdx, target: rdi
mov sil, 1
mov di, 1
mov edi, 1
mov rdi, 1
mov sil, dl
mov di, dx
mov edi, edx
mov rdi, rdx
mov sil, byte ptr [rdx - 4]
mov sil, byte ptr [rdx + 4]
mov di, word ptr [rdx + 4]
mov edi, dword ptr [rdx + 4]
mov rdi, qword ptr [rdx + 4]
mov byte ptr [rdi - 4], dl
mov byte ptr [rdi + 4], dl
mov word ptr [rdi + 4], dx
mov dword ptr [rdi + 4], edx
mov qword ptr [rdi + 4], rdx
movzx di, dl
movzx di, byte ptr [rdx + 4]
movzx edi, dl
movzx edi, dx
movzx edi, byte ptr [rdx + 4]
movzx edi, word ptr [rdx + 4]
movzx rdi, dl
movzx rdi, dx
movzx rdi, byte ptr [rdx + 4]
movzx rdi, word ptr [rdx + 4]
; Source: rdx, target: r8
mov r8b, 1
mov r8w, 1
mov r8d, 1
mov r8, 1
mov r8b, dl
mov r8w, dx
mov r8d, edx
mov r8, rdx
mov r8b, byte ptr [rdx - 4]
mov r8b, byte ptr [rdx + 4]
mov r8w, word ptr [rdx + 4]
mov r8d, dword ptr [rdx + 4]
mov r8, qword ptr [rdx + 4]
mov byte ptr [r8 - 4], dl
mov byte ptr [r8 + 4], dl
mov word ptr [r8 + 4], dx
mov dword ptr [r8 + 4], edx
mov qword ptr [r8 + 4], rdx
movzx r8w, dl
movzx r8w, byte ptr [rdx + 4]
movzx r8d, dl
movzx r8d, dx
movzx r8d, byte ptr [rdx + 4]
movzx r8d, word ptr [rdx + 4]
movzx r8, dl
movzx r8, dx
movzx r8, byte ptr [rdx + 4]
movzx r8, word ptr [rdx + 4]
; Source: rdx, target: r9
mov r9b, 1
mov r9w, 1
mov r9d, 1
mov r9, 1
mov r9b, dl
mov r9w, dx
mov r9d, edx
mov r9, rdx
mov r9b, byte ptr [rdx - 4]
mov r9b, byte ptr [rdx + 4]
mov r9w, word ptr [rdx + 4]
mov r9d, dword ptr [rdx + 4]
mov r9, qword ptr [rdx + 4]
mov byte ptr [r9 - 4], dl
mov byte ptr [r9 + 4], dl
mov word ptr [r9 + 4], dx
mov dword ptr [r9 + 4], edx
mov qword ptr [r9 + 4], rdx
movzx r9w, dl
movzx r9w, byte ptr [rdx + 4]
movzx r9d, dl
movzx r9d, dx
movzx r9d, byte ptr [rdx + 4]
movzx r9d, word ptr [rdx + 4]
movzx r9, dl
movzx r9, dx
movzx r9, byte ptr [rdx + 4]
movzx r9, word ptr [rdx + 4]
; Source: rdx, target: r10
mov r10b, 1
mov r10w, 1
mov r10d, 1
mov r10, 1
mov r10b, dl
mov r10w, dx
mov r10d, edx
mov r10, rdx
mov r10b, byte ptr [rdx - 4]
mov r10b, byte ptr [rdx + 4]
mov r10w, word ptr [rdx + 4]
mov r10d, dword ptr [rdx + 4]
mov r10, qword ptr [rdx + 4]
mov byte ptr [r10 - 4], dl
mov byte ptr [r10 + 4], dl
mov word ptr [r10 + 4], dx
mov dword ptr [r10 + 4], edx
mov qword ptr [r10 + 4], rdx
movzx r10w, dl
movzx r10w, byte ptr [rdx + 4]
movzx r10d, dl
movzx r10d, dx
movzx r10d, byte ptr [rdx + 4]
movzx r10d, word ptr [rdx + 4]
movzx r10, dl
movzx r10, dx
movzx r10, byte ptr [rdx + 4]
movzx r10, word ptr [rdx + 4]
; Source: rdx, target: r11
mov r11b, 1
mov r11w, 1
mov r11d, 1
mov r11, 1
mov r11b, dl
mov r11w, dx
mov r11d, edx
mov r11, rdx
mov r11b, byte ptr [rdx - 4]
mov r11b, byte ptr [rdx + 4]
mov r11w, word ptr [rdx + 4]
mov r11d, dword ptr [rdx + 4]
mov r11, qword ptr [rdx + 4]
mov byte ptr [r11 - 4], dl
mov byte ptr [r11 + 4], dl
mov word ptr [r11 + 4], dx
mov dword ptr [r11 + 4], edx
mov qword ptr [r11 + 4], rdx
movzx r11w, dl
movzx r11w, byte ptr [rdx + 4]
movzx r11d, dl
movzx r11d, dx
movzx r11d, byte ptr [rdx + 4]
movzx r11d, word ptr [rdx + 4]
movzx r11, dl
movzx r11, dx
movzx r11, byte ptr [rdx + 4]
movzx r11, word ptr [rdx + 4]
; Source: rdx, target: r12
mov r12b, 1
mov r12w, 1
mov r12d, 1
mov r12, 1
mov r12b, dl
mov r12w, dx
mov r12d, edx
mov r12, rdx
mov r12b, byte ptr [rdx - 4]
mov r12b, byte ptr [rdx + 4]
mov r12w, word ptr [rdx + 4]
mov r12d, dword ptr [rdx + 4]
mov r12, qword ptr [rdx + 4]
mov byte ptr [r12 - 4], dl
mov byte ptr [r12 + 4], dl
mov word ptr [r12 + 4], dx
mov dword ptr [r12 + 4], edx
mov qword ptr [r12 + 4], rdx
movzx r12w, dl
movzx r12w, byte ptr [rdx + 4]
movzx r12d, dl
movzx r12d, dx
movzx r12d, byte ptr [rdx + 4]
movzx r12d, word ptr [rdx + 4]
movzx r12, dl
movzx r12, dx
movzx r12, byte ptr [rdx + 4]
movzx r12, word ptr [rdx + 4]
; Source: rdx, target: r13
mov r13b, 1
mov r13w, 1
mov r13d, 1
mov r13, 1
mov r13b, dl
mov r13w, dx
mov r13d, edx
mov r13, rdx
mov r13b, byte ptr [rdx - 4]
mov r13b, byte ptr [rdx + 4]
mov r13w, word ptr [rdx + 4]
mov r13d, dword ptr [rdx + 4]
mov r13, qword ptr [rdx + 4]
mov byte ptr [r13 - 4], dl
mov byte ptr [r13 + 4], dl
mov word ptr [r13 + 4], dx
mov dword ptr [r13 + 4], edx
mov qword ptr [r13 + 4], rdx
movzx r13w, dl
movzx r13w, byte ptr [rdx + 4]
movzx r13d, dl
movzx r13d, dx
movzx r13d, byte ptr [rdx + 4]
movzx r13d, word ptr [rdx + 4]
movzx r13, dl
movzx r13, dx
movzx r13, byte ptr [rdx + 4]
movzx r13, word ptr [rdx + 4]
; Source: rdx, target: r14
mov r14b, 1
mov r14w, 1
mov r14d, 1
mov r14, 1
mov r14b, dl
mov r14w, dx
mov r14d, edx
mov r14, rdx
mov r14b, byte ptr [rdx - 4]
mov r14b, byte ptr [rdx + 4]
mov r14w, word ptr [rdx + 4]
mov r14d, dword ptr [rdx + 4]
mov r14, qword ptr [rdx + 4]
mov byte ptr [r14 - 4], dl
mov byte ptr [r14 + 4], dl
mov word ptr [r14 + 4], dx
mov dword ptr [r14 + 4], edx
mov qword ptr [r14 + 4], rdx
movzx r14w, dl
movzx r14w, byte ptr [rdx + 4]
movzx r14d, dl
movzx r14d, dx
movzx r14d, byte ptr [rdx + 4]
movzx r14d, word ptr [rdx + 4]
movzx r14, dl
movzx r14, dx
movzx r14, byte ptr [rdx + 4]
movzx r14, word ptr [rdx + 4]
; Source: rdx, target: r15
mov r15b, 1
mov r15w, 1
mov r15d, 1
mov r15, 1
mov r15b, dl
mov r15w, dx
mov r15d, edx
mov r15, rdx
mov r15b, byte ptr [rdx - 4]
mov r15b, byte ptr [rdx + 4]
mov r15w, word ptr [rdx + 4]
mov r15d, dword ptr [rdx + 4]
mov r15, qword ptr [rdx + 4]
mov byte ptr [r15 - 4], dl
mov byte ptr [r15 + 4], dl
mov word ptr [r15 + 4], dx
mov dword ptr [r15 + 4], edx
mov qword ptr [r15 + 4], rdx
movzx r15w, dl
movzx r15w, byte ptr [rdx + 4]
movzx r15d, dl
movzx r15d, dx
movzx r15d, byte ptr [rdx + 4]
movzx r15d, word ptr [rdx + 4]
movzx r15, dl
movzx r15, dx
movzx r15, byte ptr [rdx + 4]
movzx r15, word ptr [rdx + 4]
; Source: rbx, target: rax
mov al, 1
mov ax, 1
mov eax, 1
mov rax, 1
mov al, bl
mov ax, bx
mov eax, ebx
mov rax, rbx
mov al, byte ptr [rbx - 4]
mov al, byte ptr [rbx + 4]
mov ax, word ptr [rbx + 4]
mov eax, dword ptr [rbx + 4]
mov rax, qword ptr [rbx + 4]
mov byte ptr [rax - 4], bl
mov byte ptr [rax + 4], bl
mov word ptr [rax + 4], bx
mov dword ptr [rax + 4], ebx
mov qword ptr [rax + 4], rbx
movzx ax, bl
movzx ax, byte ptr [rbx + 4]
movzx eax, bl
movzx eax, bx
movzx eax, byte ptr [rbx + 4]
movzx eax, word ptr [rbx + 4]
movzx rax, bl
movzx rax, bx
movzx rax, byte ptr [rbx + 4]
movzx rax, word ptr [rbx + 4]
; Source: rbx, target: rcx
mov cl, 1
mov cx, 1
mov ecx, 1
mov rcx, 1
mov cl, bl
mov cx, bx
mov ecx, ebx
mov rcx, rbx
mov cl, byte ptr [rbx - 4]
mov cl, byte ptr [rbx + 4]
mov cx, word ptr [rbx + 4]
mov ecx, dword ptr [rbx + 4]
mov rcx, qword ptr [rbx + 4]
mov byte ptr [rcx - 4], bl
mov byte ptr [rcx + 4], bl
mov word ptr [rcx + 4], bx
mov dword ptr [rcx + 4], ebx
mov qword ptr [rcx + 4], rbx
movzx cx, bl
movzx cx, byte ptr [rbx + 4]
movzx ecx, bl
movzx ecx, bx
movzx ecx, byte ptr [rbx + 4]
movzx ecx, word ptr [rbx + 4]
movzx rcx, bl
movzx rcx, bx
movzx rcx, byte ptr [rbx + 4]
movzx rcx, word ptr [rbx + 4]
; Source: rbx, target: rdx
mov dl, 1
mov dx, 1
mov edx, 1
mov rdx, 1
mov dl, bl
mov dx, bx
mov edx, ebx
mov rdx, rbx
mov dl, byte ptr [rbx - 4]
mov dl, byte ptr [rbx + 4]
mov dx, word ptr [rbx + 4]
mov edx, dword ptr [rbx + 4]
mov rdx, qword ptr [rbx + 4]
mov byte ptr [rdx - 4], bl
mov byte ptr [rdx + 4], bl
mov word ptr [rdx + 4], bx
mov dword ptr [rdx + 4], ebx
mov qword ptr [rdx + 4], rbx
movzx dx, bl
movzx dx, byte ptr [rbx + 4]
movzx edx, bl
movzx edx, bx
movzx edx, byte ptr [rbx + 4]
movzx edx, word ptr [rbx + 4]
movzx rdx, bl
movzx rdx, bx
movzx rdx, byte ptr [rbx + 4]
movzx rdx, word ptr [rbx + 4]
; Source: rbx, target: rbx
mov bl, 1
mov bx, 1
mov ebx, 1
mov rbx, 1
mov bl, bl
mov bx, bx
mov ebx, ebx
mov rbx, rbx
mov bl, byte ptr [rbx - 4]
mov bl, byte ptr [rbx + 4]
mov bx, word ptr [rbx + 4]
mov ebx, dword ptr [rbx + 4]
mov rbx, qword ptr [rbx + 4]
mov byte ptr [rbx - 4], bl
mov byte ptr [rbx + 4], bl
mov word ptr [rbx + 4], bx
mov dword ptr [rbx + 4], ebx
mov qword ptr [rbx + 4], rbx
movzx bx, bl
movzx bx, byte ptr [rbx + 4]
movzx ebx, bl
movzx ebx, bx
movzx ebx, byte ptr [rbx + 4]
movzx ebx, word ptr [rbx + 4]
movzx rbx, bl
movzx rbx, bx
movzx rbx, byte ptr [rbx + 4]
movzx rbx, word ptr [rbx + 4]
; Source: rbx, target: rsp
mov spl, 1
mov sp, 1
mov esp, 1
mov rsp, 1
mov spl, bl
mov sp, bx
mov esp, ebx
mov rsp, rbx
mov spl, byte ptr [rbx - 4]
mov spl, byte ptr [rbx + 4]
mov sp, word ptr [rbx + 4]
mov esp, dword ptr [rbx + 4]
mov rsp, qword ptr [rbx + 4]
mov byte ptr [rsp - 4], bl
mov byte ptr [rsp + 4], bl
mov word ptr [rsp + 4], bx
mov dword ptr [rsp + 4], ebx
mov qword ptr [rsp + 4], rbx
movzx sp, bl
movzx sp, byte ptr [rbx + 4]
movzx esp, bl
movzx esp, bx
movzx esp, byte ptr [rbx + 4]
movzx esp, word ptr [rbx + 4]
movzx rsp, bl
movzx rsp, bx
movzx rsp, byte ptr [rbx + 4]
movzx rsp, word ptr [rbx + 4]
; Source: rbx, target: rbp
mov bpl, 1
mov bp, 1
mov ebp, 1
mov rbp, 1
mov bpl, bl
mov bp, bx
mov ebp, ebx
mov rbp, rbx
mov bpl, byte ptr [rbx - 4]
mov bpl, byte ptr [rbx + 4]
mov bp, word ptr [rbx + 4]
mov ebp, dword ptr [rbx + 4]
mov rbp, qword ptr [rbx + 4]
mov byte ptr [rbp - 4], bl
mov byte ptr [rbp + 4], bl
mov word ptr [rbp + 4], bx
mov dword ptr [rbp + 4], ebx
mov qword ptr [rbp + 4], rbx
movzx bp, bl
movzx bp, byte ptr [rbx + 4]
movzx ebp, bl
movzx ebp, bx
movzx ebp, byte ptr [rbx + 4]
movzx ebp, word ptr [rbx + 4]
movzx rbp, bl
movzx rbp, bx
movzx rbp, byte ptr [rbx + 4]
movzx rbp, word ptr [rbx + 4]
; Source: rbx, target: rsi
mov dil, 1
mov si, 1
mov esi, 1
mov rsi, 1
mov dil, bl
mov si, bx
mov esi, ebx
mov rsi, rbx
mov dil, byte ptr [rbx - 4]
mov dil, byte ptr [rbx + 4]
mov si, word ptr [rbx + 4]
mov esi, dword ptr [rbx + 4]
mov rsi, qword ptr [rbx + 4]
mov byte ptr [rsi - 4], bl
mov byte ptr [rsi + 4], bl
mov word ptr [rsi + 4], bx
mov dword ptr [rsi + 4], ebx
mov qword ptr [rsi + 4], rbx
movzx si, bl
movzx si, byte ptr [rbx + 4]
movzx esi, bl
movzx esi, bx
movzx esi, byte ptr [rbx + 4]
movzx esi, word ptr [rbx + 4]
movzx rsi, bl
movzx rsi, bx
movzx rsi, byte ptr [rbx + 4]
movzx rsi, word ptr [rbx + 4]
; Source: rbx, target: rdi
mov sil, 1
mov di, 1
mov edi, 1
mov rdi, 1
mov sil, bl
mov di, bx
mov edi, ebx
mov rdi, rbx
mov sil, byte ptr [rbx - 4]
mov sil, byte ptr [rbx + 4]
mov di, word ptr [rbx + 4]
mov edi, dword ptr [rbx + 4]
mov rdi, qword ptr [rbx + 4]
mov byte ptr [rdi - 4], bl
mov byte ptr [rdi + 4], bl
mov word ptr [rdi + 4], bx
mov dword ptr [rdi + 4], ebx
mov qword ptr [rdi + 4], rbx
movzx di, bl
movzx di, byte ptr [rbx + 4]
movzx edi, bl
movzx edi, bx
movzx edi, byte ptr [rbx + 4]
movzx edi, word ptr [rbx + 4]
movzx rdi, bl
movzx rdi, bx
movzx rdi, byte ptr [rbx + 4]
movzx rdi, word ptr [rbx + 4]
; Source: rbx, target: r8
mov r8b, 1
mov r8w, 1
mov r8d, 1
mov r8, 1
mov r8b, bl
mov r8w, bx
mov r8d, ebx
mov r8, rbx
mov r8b, byte ptr [rbx - 4]
mov r8b, byte ptr [rbx + 4]
mov r8w, word ptr [rbx + 4]
mov r8d, dword ptr [rbx + 4]
mov r8, qword ptr [rbx + 4]
mov byte ptr [r8 - 4], bl
mov byte ptr [r8 + 4], bl
mov word ptr [r8 + 4], bx
mov dword ptr [r8 + 4], ebx
mov qword ptr [r8 + 4], rbx
movzx r8w, bl
movzx r8w, byte ptr [rbx + 4]
movzx r8d, bl
movzx r8d, bx
movzx r8d, byte ptr [rbx + 4]
movzx r8d, word ptr [rbx + 4]
movzx r8, bl
movzx r8, bx
movzx r8, byte ptr [rbx + 4]
movzx r8, word ptr [rbx + 4]
; Source: rbx, target: r9
mov r9b, 1
mov r9w, 1
mov r9d, 1
mov r9, 1
mov r9b, bl
mov r9w, bx
mov r9d, ebx
mov r9, rbx
mov r9b, byte ptr [rbx - 4]
mov r9b, byte ptr [rbx + 4]
mov r9w, word ptr [rbx + 4]
mov r9d, dword ptr [rbx + 4]
mov r9, qword ptr [rbx + 4]
mov byte ptr [r9 - 4], bl
mov byte ptr [r9 + 4], bl
mov word ptr [r9 + 4], bx
mov dword ptr [r9 + 4], ebx
mov qword ptr [r9 + 4], rbx
movzx r9w, bl
movzx r9w, byte ptr [rbx + 4]
movzx r9d, bl
movzx r9d, bx
movzx r9d, byte ptr [rbx + 4]
movzx r9d, word ptr [rbx + 4]
movzx r9, bl
movzx r9, bx
movzx r9, byte ptr [rbx + 4]
movzx r9, word ptr [rbx + 4]
; Source: rbx, target: r10
mov r10b, 1
mov r10w, 1
mov r10d, 1
mov r10, 1
mov r10b, bl
mov r10w, bx
mov r10d, ebx
mov r10, rbx
mov r10b, byte ptr [rbx - 4]
mov r10b, byte ptr [rbx + 4]
mov r10w, word ptr [rbx + 4]
mov r10d, dword ptr [rbx + 4]
mov r10, qword ptr [rbx + 4]
mov byte ptr [r10 - 4], bl
mov byte ptr [r10 + 4], bl
mov word ptr [r10 + 4], bx
mov dword ptr [r10 + 4], ebx
mov qword ptr [r10 + 4], rbx
movzx r10w, bl
movzx r10w, byte ptr [rbx + 4]
movzx r10d, bl
movzx r10d, bx
movzx r10d, byte ptr [rbx + 4]
movzx r10d, word ptr [rbx + 4]
movzx r10, bl
movzx r10, bx
movzx r10, byte ptr [rbx + 4]
movzx r10, word ptr [rbx + 4]
; Source: rbx, target: r11
mov r11b, 1
mov r11w, 1
mov r11d, 1
mov r11, 1
mov r11b, bl
mov r11w, bx
mov r11d, ebx
mov r11, rbx
mov r11b, byte ptr [rbx - 4]
mov r11b, byte ptr [rbx + 4]
mov r11w, word ptr [rbx + 4]
mov r11d, dword ptr [rbx + 4]
mov r11, qword ptr [rbx + 4]
mov byte ptr [r11 - 4], bl
mov byte ptr [r11 + 4], bl
mov word ptr [r11 + 4], bx
mov dword ptr [r11 + 4], ebx
mov qword ptr [r11 + 4], rbx
movzx r11w, bl
movzx r11w, byte ptr [rbx + 4]
movzx r11d, bl
movzx r11d, bx
movzx r11d, byte ptr [rbx + 4]
movzx r11d, word ptr [rbx + 4]
movzx r11, bl
movzx r11, bx
movzx r11, byte ptr [rbx + 4]
movzx r11, word ptr [rbx + 4]
; Source: rbx, target: r12
mov r12b, 1
mov r12w, 1
mov r12d, 1
mov r12, 1
mov r12b, bl
mov r12w, bx
mov r12d, ebx
mov r12, rbx
mov r12b, byte ptr [rbx - 4]
mov r12b, byte ptr [rbx + 4]
mov r12w, word ptr [rbx + 4]
mov r12d, dword ptr [rbx + 4]
mov r12, qword ptr [rbx + 4]
mov byte ptr [r12 - 4], bl
mov byte ptr [r12 + 4], bl
mov word ptr [r12 + 4], bx
mov dword ptr [r12 + 4], ebx
mov qword ptr [r12 + 4], rbx
movzx r12w, bl
movzx r12w, byte ptr [rbx + 4]
movzx r12d, bl
movzx r12d, bx
movzx r12d, byte ptr [rbx + 4]
movzx r12d, word ptr [rbx + 4]
movzx r12, bl
movzx r12, bx
movzx r12, byte ptr [rbx + 4]
movzx r12, word ptr [rbx + 4]
; Source: rbx, target: r13
mov r13b, 1
mov r13w, 1
mov r13d, 1
mov r13, 1
mov r13b, bl
mov r13w, bx
mov r13d, ebx
mov r13, rbx
mov r13b, byte ptr [rbx - 4]
mov r13b, byte ptr [rbx + 4]
mov r13w, word ptr [rbx + 4]
mov r13d, dword ptr [rbx + 4]
mov r13, qword ptr [rbx + 4]
mov byte ptr [r13 - 4], bl
mov byte ptr [r13 + 4], bl
mov word ptr [r13 + 4], bx
mov dword ptr [r13 + 4], ebx
mov qword ptr [r13 + 4], rbx
movzx r13w, bl
movzx r13w, byte ptr [rbx + 4]
movzx r13d, bl
movzx r13d, bx
movzx r13d, byte ptr [rbx + 4]
movzx r13d, word ptr [rbx + 4]
movzx r13, bl
movzx r13, bx
movzx r13, byte ptr [rbx + 4]
movzx r13, word ptr [rbx + 4]
; Source: rbx, target: r14
mov r14b, 1
mov r14w, 1
mov r14d, 1
mov r14, 1
mov r14b, bl
mov r14w, bx
mov r14d, ebx
mov r14, rbx
mov r14b, byte ptr [rbx - 4]
mov r14b, byte ptr [rbx + 4]
mov r14w, word ptr [rbx + 4]
mov r14d, dword ptr [rbx + 4]
mov r14, qword ptr [rbx + 4]
mov byte ptr [r14 - 4], bl
mov byte ptr [r14 + 4], bl
mov word ptr [r14 + 4], bx
mov dword ptr [r14 + 4], ebx
mov qword ptr [r14 + 4], rbx
movzx r14w, bl
movzx r14w, byte ptr [rbx + 4]
movzx r14d, bl
movzx r14d, bx
movzx r14d, byte ptr [rbx + 4]
movzx r14d, word ptr [rbx + 4]
movzx r14, bl
movzx r14, bx
movzx r14, byte ptr [rbx + 4]
movzx r14, word ptr [rbx + 4]
; Source: rbx, target: r15
mov r15b, 1
mov r15w, 1
mov r15d, 1
mov r15, 1
mov r15b, bl
mov r15w, bx
mov r15d, ebx
mov r15, rbx
mov r15b, byte ptr [rbx - 4]
mov r15b, byte ptr [rbx + 4]
mov r15w, word ptr [rbx + 4]
mov r15d, dword ptr [rbx + 4]
mov r15, qword ptr [rbx + 4]
mov byte ptr [r15 - 4], bl
mov byte ptr [r15 + 4], bl
mov word ptr [r15 + 4], bx
mov dword ptr [r15 + 4], ebx
mov qword ptr [r15 + 4], rbx
movzx r15w, bl
movzx r15w, byte ptr [rbx + 4]
movzx r15d, bl
movzx r15d, bx
movzx r15d, byte ptr [rbx + 4]
movzx r15d, word ptr [rbx + 4]
movzx r15, bl
movzx r15, bx
movzx r15, byte ptr [rbx + 4]
movzx r15, word ptr [rbx + 4]
; Source: rsp, target: rax
mov al, 1
mov ax, 1
mov eax, 1
mov rax, 1
mov al, spl
mov ax, sp
mov eax, esp
mov rax, rsp
mov al, byte ptr [rsp - 4]
mov al, byte ptr [rsp + 4]
mov ax, word ptr [rsp + 4]
mov eax, dword ptr [rsp + 4]
mov rax, qword ptr [rsp + 4]
mov byte ptr [rax - 4], spl
mov byte ptr [rax + 4], spl
mov word ptr [rax + 4], sp
mov dword ptr [rax + 4], esp
mov qword ptr [rax + 4], rsp
movzx ax, spl
movzx ax, byte ptr [rsp + 4]
movzx eax, spl
movzx eax, sp
movzx eax, byte ptr [rsp + 4]
movzx eax, word ptr [rsp + 4]
movzx rax, spl
movzx rax, sp
movzx rax, byte ptr [rsp + 4]
movzx rax, word ptr [rsp + 4]
; Source: rsp, target: rcx
mov cl, 1
mov cx, 1
mov ecx, 1
mov rcx, 1
mov cl, spl
mov cx, sp
mov ecx, esp
mov rcx, rsp
mov cl, byte ptr [rsp - 4]
mov cl, byte ptr [rsp + 4]
mov cx, word ptr [rsp + 4]
mov ecx, dword ptr [rsp + 4]
mov rcx, qword ptr [rsp + 4]
mov byte ptr [rcx - 4], spl
mov byte ptr [rcx + 4], spl
mov word ptr [rcx + 4], sp
mov dword ptr [rcx + 4], esp
mov qword ptr [rcx + 4], rsp
movzx cx, spl
movzx cx, byte ptr [rsp + 4]
movzx ecx, spl
movzx ecx, sp
movzx ecx, byte ptr [rsp + 4]
movzx ecx, word ptr [rsp + 4]
movzx rcx, spl
movzx rcx, sp
movzx rcx, byte ptr [rsp + 4]
movzx rcx, word ptr [rsp + 4]
; Source: rsp, target: rdx
mov dl, 1
mov dx, 1
mov edx, 1
mov rdx, 1
mov dl, spl
mov dx, sp
mov edx, esp
mov rdx, rsp
mov dl, byte ptr [rsp - 4]
mov dl, byte ptr [rsp + 4]
mov dx, word ptr [rsp + 4]
mov edx, dword ptr [rsp + 4]
mov rdx, qword ptr [rsp + 4]
mov byte ptr [rdx - 4], spl
mov byte ptr [rdx + 4], spl
mov word ptr [rdx + 4], sp
mov dword ptr [rdx + 4], esp
mov qword ptr [rdx + 4], rsp
movzx dx, spl
movzx dx, byte ptr [rsp + 4]
movzx edx, spl
movzx edx, sp
movzx edx, byte ptr [rsp + 4]
movzx edx, word ptr [rsp + 4]
movzx rdx, spl
movzx rdx, sp
movzx rdx, byte ptr [rsp + 4]
movzx rdx, word ptr [rsp + 4]
; Source: rsp, target: rbx
mov bl, 1
mov bx, 1
mov ebx, 1
mov rbx, 1
mov bl, spl
mov bx, sp
mov ebx, esp
mov rbx, rsp
mov bl, byte ptr [rsp - 4]
mov bl, byte ptr [rsp + 4]
mov bx, word ptr [rsp + 4]
mov ebx, dword ptr [rsp + 4]
mov rbx, qword ptr [rsp + 4]
mov byte ptr [rbx - 4], spl
mov byte ptr [rbx + 4], spl
mov word ptr [rbx + 4], sp
mov dword ptr [rbx + 4], esp
mov qword ptr [rbx + 4], rsp
movzx bx, spl
movzx bx, byte ptr [rsp + 4]
movzx ebx, spl
movzx ebx, sp
movzx ebx, byte ptr [rsp + 4]
movzx ebx, word ptr [rsp + 4]
movzx rbx, spl
movzx rbx, sp
movzx rbx, byte ptr [rsp + 4]
movzx rbx, word ptr [rsp + 4]
; Source: rsp, target: rsp
mov spl, 1
mov sp, 1
mov esp, 1
mov rsp, 1
mov spl, spl
mov sp, sp
mov esp, esp
mov rsp, rsp
mov spl, byte ptr [rsp - 4]
mov spl, byte ptr [rsp + 4]
mov sp, word ptr [rsp + 4]
mov esp, dword ptr [rsp + 4]
mov rsp, qword ptr [rsp + 4]
mov byte ptr [rsp - 4], spl
mov byte ptr [rsp + 4], spl
mov word ptr [rsp + 4], sp
mov dword ptr [rsp + 4], esp
mov qword ptr [rsp + 4], rsp
movzx sp, spl
movzx sp, byte ptr [rsp + 4]
movzx esp, spl
movzx esp, sp
movzx esp, byte ptr [rsp + 4]
movzx esp, word ptr [rsp + 4]
movzx rsp, spl
movzx rsp, sp
movzx rsp, byte ptr [rsp + 4]
movzx rsp, word ptr [rsp + 4]
; Source: rsp, target: rbp
mov bpl, 1
mov bp, 1
mov ebp, 1
mov rbp, 1
mov bpl, spl
mov bp, sp
mov ebp, esp
mov rbp, rsp
mov bpl, byte ptr [rsp - 4]
mov bpl, byte ptr [rsp + 4]
mov bp, word ptr [rsp + 4]
mov ebp, dword ptr [rsp + 4]
mov rbp, qword ptr [rsp + 4]
mov byte ptr [rbp - 4], spl
mov byte ptr [rbp + 4], spl
mov word ptr [rbp + 4], sp
mov dword ptr [rbp + 4], esp
mov qword ptr [rbp + 4], rsp
movzx bp, spl
movzx bp, byte ptr [rsp + 4]
movzx ebp, spl
movzx ebp, sp
movzx ebp, byte ptr [rsp + 4]
movzx ebp, word ptr [rsp + 4]
movzx rbp, spl
movzx rbp, sp
movzx rbp, byte ptr [rsp + 4]
movzx rbp, word ptr [rsp + 4]
; Source: rsp, target: rsi
mov dil, 1
mov si, 1
mov esi, 1
mov rsi, 1
mov dil, spl
mov si, sp
mov esi, esp
mov rsi, rsp
mov dil, byte ptr [rsp - 4]
mov dil, byte ptr [rsp + 4]
mov si, word ptr [rsp + 4]
mov esi, dword ptr [rsp + 4]
mov rsi, qword ptr [rsp + 4]
mov byte ptr [rsi - 4], spl
mov byte ptr [rsi + 4], spl
mov word ptr [rsi + 4], sp
mov dword ptr [rsi + 4], esp
mov qword ptr [rsi + 4], rsp
movzx si, spl
movzx si, byte ptr [rsp + 4]
movzx esi, spl
movzx esi, sp
movzx esi, byte ptr [rsp + 4]
movzx esi, word ptr [rsp + 4]
movzx rsi, spl
movzx rsi, sp
movzx rsi, byte ptr [rsp + 4]
movzx rsi, word ptr [rsp + 4]
; Source: rsp, target: rdi
mov sil, 1
mov di, 1
mov edi, 1
mov rdi, 1
mov sil, spl
mov di, sp
mov edi, esp
mov rdi, rsp
mov sil, byte ptr [rsp - 4]
mov sil, byte ptr [rsp + 4]
mov di, word ptr [rsp + 4]
mov edi, dword ptr [rsp + 4]
mov rdi, qword ptr [rsp + 4]
mov byte ptr [rdi - 4], spl
mov byte ptr [rdi + 4], spl
mov word ptr [rdi + 4], sp
mov dword ptr [rdi + 4], esp
mov qword ptr [rdi + 4], rsp
movzx di, spl
movzx di, byte ptr [rsp + 4]
movzx edi, spl
movzx edi, sp
movzx edi, byte ptr [rsp + 4]
movzx edi, word ptr [rsp + 4]
movzx rdi, spl
movzx rdi, sp
movzx rdi, byte ptr [rsp + 4]
movzx rdi, word ptr [rsp + 4]
; Source: rsp, target: r8
mov r8b, 1
mov r8w, 1
mov r8d, 1
mov r8, 1
mov r8b, spl
mov r8w, sp
mov r8d, esp
mov r8, rsp
mov r8b, byte ptr [rsp - 4]
mov r8b, byte ptr [rsp + 4]
mov r8w, word ptr [rsp + 4]
mov r8d, dword ptr [rsp + 4]
mov r8, qword ptr [rsp + 4]
mov byte ptr [r8 - 4], spl
mov byte ptr [r8 + 4], spl
mov word ptr [r8 + 4], sp
mov dword ptr [r8 + 4], esp
mov qword ptr [r8 + 4], rsp
movzx r8w, spl
movzx r8w, byte ptr [rsp + 4]
movzx r8d, spl
movzx r8d, sp
movzx r8d, byte ptr [rsp + 4]
movzx r8d, word ptr [rsp + 4]
movzx r8, spl
movzx r8, sp
movzx r8, byte ptr [rsp + 4]
movzx r8, word ptr [rsp + 4]
; Source: rsp, target: r9
mov r9b, 1
mov r9w, 1
mov r9d, 1
mov r9, 1
mov r9b, spl
mov r9w, sp
mov r9d, esp
mov r9, rsp
mov r9b, byte ptr [rsp - 4]
mov r9b, byte ptr [rsp + 4]
mov r9w, word ptr [rsp + 4]
mov r9d, dword ptr [rsp + 4]
mov r9, qword ptr [rsp + 4]
mov byte ptr [r9 - 4], spl
mov byte ptr [r9 + 4], spl
mov word ptr [r9 + 4], sp
mov dword ptr [r9 + 4], esp
mov qword ptr [r9 + 4], rsp
movzx r9w, spl
movzx r9w, byte ptr [rsp + 4]
movzx r9d, spl
movzx r9d, sp
movzx r9d, byte ptr [rsp + 4]
movzx r9d, word ptr [rsp + 4]
movzx r9, spl
movzx r9, sp
movzx r9, byte ptr [rsp + 4]
movzx r9, word ptr [rsp + 4]
; Source: rsp, target: r10
mov r10b, 1
mov r10w, 1
mov r10d, 1
mov r10, 1
mov r10b, spl
mov r10w, sp
mov r10d, esp
mov r10, rsp
mov r10b, byte ptr [rsp - 4]
mov r10b, byte ptr [rsp + 4]
mov r10w, word ptr [rsp + 4]
mov r10d, dword ptr [rsp + 4]
mov r10, qword ptr [rsp + 4]
mov byte ptr [r10 - 4], spl
mov byte ptr [r10 + 4], spl
mov word ptr [r10 + 4], sp
mov dword ptr [r10 + 4], esp
mov qword ptr [r10 + 4], rsp
movzx r10w, spl
movzx r10w, byte ptr [rsp + 4]
movzx r10d, spl
movzx r10d, sp
movzx r10d, byte ptr [rsp + 4]
movzx r10d, word ptr [rsp + 4]
movzx r10, spl
movzx r10, sp
movzx r10, byte ptr [rsp + 4]
movzx r10, word ptr [rsp + 4]
; Source: rsp, target: r11
mov r11b, 1
mov r11w, 1
mov r11d, 1
mov r11, 1
mov r11b, spl
mov r11w, sp
mov r11d, esp
mov r11, rsp
mov r11b, byte ptr [rsp - 4]
mov r11b, byte ptr [rsp + 4]
mov r11w, word ptr [rsp + 4]
mov r11d, dword ptr [rsp + 4]
mov r11, qword ptr [rsp + 4]
mov byte ptr [r11 - 4], spl
mov byte ptr [r11 + 4], spl
mov word ptr [r11 + 4], sp
mov dword ptr [r11 + 4], esp
mov qword ptr [r11 + 4], rsp
movzx r11w, spl
movzx r11w, byte ptr [rsp + 4]
movzx r11d, spl
movzx r11d, sp
movzx r11d, byte ptr [rsp + 4]
movzx r11d, word ptr [rsp + 4]
movzx r11, spl
movzx r11, sp
movzx r11, byte ptr [rsp + 4]
movzx r11, word ptr [rsp + 4]
; Source: rsp, target: r12
mov r12b, 1
mov r12w, 1
mov r12d, 1
mov r12, 1
mov r12b, spl
mov r12w, sp
mov r12d, esp
mov r12, rsp
mov r12b, byte ptr [rsp - 4]
mov r12b, byte ptr [rsp + 4]
mov r12w, word ptr [rsp + 4]
mov r12d, dword ptr [rsp + 4]
mov r12, qword ptr [rsp + 4]
mov byte ptr [r12 - 4], spl
mov byte ptr [r12 + 4], spl
mov word ptr [r12 + 4], sp
mov dword ptr [r12 + 4], esp
mov qword ptr [r12 + 4], rsp
movzx r12w, spl
movzx r12w, byte ptr [rsp + 4]
movzx r12d, spl
movzx r12d, sp
movzx r12d, byte ptr [rsp + 4]
movzx r12d, word ptr [rsp + 4]
movzx r12, spl
movzx r12, sp
movzx r12, byte ptr [rsp + 4]
movzx r12, word ptr [rsp + 4]
; Source: rsp, target: r13
mov r13b, 1
mov r13w, 1
mov r13d, 1
mov r13, 1
mov r13b, spl
mov r13w, sp
mov r13d, esp
mov r13, rsp
mov r13b, byte ptr [rsp - 4]
mov r13b, byte ptr [rsp + 4]
mov r13w, word ptr [rsp + 4]
mov r13d, dword ptr [rsp + 4]
mov r13, qword ptr [rsp + 4]
mov byte ptr [r13 - 4], spl
mov byte ptr [r13 + 4], spl
mov word ptr [r13 + 4], sp
mov dword ptr [r13 + 4], esp
mov qword ptr [r13 + 4], rsp
movzx r13w, spl
movzx r13w, byte ptr [rsp + 4]
movzx r13d, spl
movzx r13d, sp
movzx r13d, byte ptr [rsp + 4]
movzx r13d, word ptr [rsp + 4]
movzx r13, spl
movzx r13, sp
movzx r13, byte ptr [rsp + 4]
movzx r13, word ptr [rsp + 4]
; Source: rsp, target: r14
mov r14b, 1
mov r14w, 1
mov r14d, 1
mov r14, 1
mov r14b, spl
mov r14w, sp
mov r14d, esp
mov r14, rsp
mov r14b, byte ptr [rsp - 4]
mov r14b, byte ptr [rsp + 4]
mov r14w, word ptr [rsp + 4]
mov r14d, dword ptr [rsp + 4]
mov r14, qword ptr [rsp + 4]
mov byte ptr [r14 - 4], spl
mov byte ptr [r14 + 4], spl
mov word ptr [r14 + 4], sp
mov dword ptr [r14 + 4], esp
mov qword ptr [r14 + 4], rsp
movzx r14w, spl
movzx r14w, byte ptr [rsp + 4]
movzx r14d, spl
movzx r14d, sp
movzx r14d, byte ptr [rsp + 4]
movzx r14d, word ptr [rsp + 4]
movzx r14, spl
movzx r14, sp
movzx r14, byte ptr [rsp + 4]
movzx r14, word ptr [rsp + 4]
; Source: rsp, target: r15
mov r15b, 1
mov r15w, 1
mov r15d, 1
mov r15, 1
mov r15b, spl
mov r15w, sp
mov r15d, esp
mov r15, rsp
mov r15b, byte ptr [rsp - 4]
mov r15b, byte ptr [rsp + 4]
mov r15w, word ptr [rsp + 4]
mov r15d, dword ptr [rsp + 4]
mov r15, qword ptr [rsp + 4]
mov byte ptr [r15 - 4], spl
mov byte ptr [r15 + 4], spl
mov word ptr [r15 + 4], sp
mov dword ptr [r15 + 4], esp
mov qword ptr [r15 + 4], rsp
movzx r15w, spl
movzx r15w, byte ptr [rsp + 4]
movzx r15d, spl
movzx r15d, sp
movzx r15d, byte ptr [rsp + 4]
movzx r15d, word ptr [rsp + 4]
movzx r15, spl
movzx r15, sp
movzx r15, byte ptr [rsp + 4]
movzx r15, word ptr [rsp + 4]
; Source: rbp, target: rax
mov al, 1
mov ax, 1
mov eax, 1
mov rax, 1
mov al, bpl
mov ax, bp
mov eax, ebp
mov rax, rbp
mov al, byte ptr [rbp - 4]
mov al, byte ptr [rbp + 4]
mov ax, word ptr [rbp + 4]
mov eax, dword ptr [rbp + 4]
mov rax, qword ptr [rbp + 4]
mov byte ptr [rax - 4], bpl
mov byte ptr [rax + 4], bpl
mov word ptr [rax + 4], bp
mov dword ptr [rax + 4], ebp
mov qword ptr [rax + 4], rbp
movzx ax, bpl
movzx ax, byte ptr [rbp + 4]
movzx eax, bpl
movzx eax, bp
movzx eax, byte ptr [rbp + 4]
movzx eax, word ptr [rbp + 4]
movzx rax, bpl
movzx rax, bp
movzx rax, byte ptr [rbp + 4]
movzx rax, word ptr [rbp + 4]
; Source: rbp, target: rcx
mov cl, 1
mov cx, 1
mov ecx, 1
mov rcx, 1
mov cl, bpl
mov cx, bp
mov ecx, ebp
mov rcx, rbp
mov cl, byte ptr [rbp - 4]
mov cl, byte ptr [rbp + 4]
mov cx, word ptr [rbp + 4]
mov ecx, dword ptr [rbp + 4]
mov rcx, qword ptr [rbp + 4]
mov byte ptr [rcx - 4], bpl
mov byte ptr [rcx + 4], bpl
mov word ptr [rcx + 4], bp
mov dword ptr [rcx + 4], ebp
mov qword ptr [rcx + 4], rbp
movzx cx, bpl
movzx cx, byte ptr [rbp + 4]
movzx ecx, bpl
movzx ecx, bp
movzx ecx, byte ptr [rbp + 4]
movzx ecx, word ptr [rbp + 4]
movzx rcx, bpl
movzx rcx, bp
movzx rcx, byte ptr [rbp + 4]
movzx rcx, word ptr [rbp + 4]
; Source: rbp, target: rdx
mov dl, 1
mov dx, 1
mov edx, 1
mov rdx, 1
mov dl, bpl
mov dx, bp
mov edx, ebp
mov rdx, rbp
mov dl, byte ptr [rbp - 4]
mov dl, byte ptr [rbp + 4]
mov dx, word ptr [rbp + 4]
mov edx, dword ptr [rbp + 4]
mov rdx, qword ptr [rbp + 4]
mov byte ptr [rdx - 4], bpl
mov byte ptr [rdx + 4], bpl
mov word ptr [rdx + 4], bp
mov dword ptr [rdx + 4], ebp
mov qword ptr [rdx + 4], rbp
movzx dx, bpl
movzx dx, byte ptr [rbp + 4]
movzx edx, bpl
movzx edx, bp
movzx edx, byte ptr [rbp + 4]
movzx edx, word ptr [rbp + 4]
movzx rdx, bpl
movzx rdx, bp
movzx rdx, byte ptr [rbp + 4]
movzx rdx, word ptr [rbp + 4]
; Source: rbp, target: rbx
mov bl, 1
mov bx, 1
mov ebx, 1
mov rbx, 1
mov bl, bpl
mov bx, bp
mov ebx, ebp
mov rbx, rbp
mov bl, byte ptr [rbp - 4]
mov bl, byte ptr [rbp + 4]
mov bx, word ptr [rbp + 4]
mov ebx, dword ptr [rbp + 4]
mov rbx, qword ptr [rbp + 4]
mov byte ptr [rbx - 4], bpl
mov byte ptr [rbx + 4], bpl
mov word ptr [rbx + 4], bp
mov dword ptr [rbx + 4], ebp
mov qword ptr [rbx + 4], rbp
movzx bx, bpl
movzx bx, byte ptr [rbp + 4]
movzx ebx, bpl
movzx ebx, bp
movzx ebx, byte ptr [rbp + 4]
movzx ebx, word ptr [rbp + 4]
movzx rbx, bpl
movzx rbx, bp
movzx rbx, byte ptr [rbp + 4]
movzx rbx, word ptr [rbp + 4]
; Source: rbp, target: rsp
mov spl, 1
mov sp, 1
mov esp, 1
mov rsp, 1
mov spl, bpl
mov sp, bp
mov esp, ebp
mov rsp, rbp
mov spl, byte ptr [rbp - 4]
mov spl, byte ptr [rbp + 4]
mov sp, word ptr [rbp + 4]
mov esp, dword ptr [rbp + 4]
mov rsp, qword ptr [rbp + 4]
mov byte ptr [rsp - 4], bpl
mov byte ptr [rsp + 4], bpl
mov word ptr [rsp + 4], bp
mov dword ptr [rsp + 4], ebp
mov qword ptr [rsp + 4], rbp
movzx sp, bpl
movzx sp, byte ptr [rbp + 4]
movzx esp, bpl
movzx esp, bp
movzx esp, byte ptr [rbp + 4]
movzx esp, word ptr [rbp + 4]
movzx rsp, bpl
movzx rsp, bp
movzx rsp, byte ptr [rbp + 4]
movzx rsp, word ptr [rbp + 4]
; Source: rbp, target: rbp
mov bpl, 1
mov bp, 1
mov ebp, 1
mov rbp, 1
mov bpl, bpl
mov bp, bp
mov ebp, ebp
mov rbp, rbp
mov bpl, byte ptr [rbp - 4]
mov bpl, byte ptr [rbp + 4]
mov bp, word ptr [rbp + 4]
mov ebp, dword ptr [rbp + 4]
mov rbp, qword ptr [rbp + 4]
mov byte ptr [rbp - 4], bpl
mov byte ptr [rbp + 4], bpl
mov word ptr [rbp + 4], bp
mov dword ptr [rbp + 4], ebp
mov qword ptr [rbp + 4], rbp
movzx bp, bpl
movzx bp, byte ptr [rbp + 4]
movzx ebp, bpl
movzx ebp, bp
movzx ebp, byte ptr [rbp + 4]
movzx ebp, word ptr [rbp + 4]
movzx rbp, bpl
movzx rbp, bp
movzx rbp, byte ptr [rbp + 4]
movzx rbp, word ptr [rbp + 4]
; Source: rbp, target: rsi
mov dil, 1
mov si, 1
mov esi, 1
mov rsi, 1
mov dil, bpl
mov si, bp
mov esi, ebp
mov rsi, rbp
mov dil, byte ptr [rbp - 4]
mov dil, byte ptr [rbp + 4]
mov si, word ptr [rbp + 4]
mov esi, dword ptr [rbp + 4]
mov rsi, qword ptr [rbp + 4]
mov byte ptr [rsi - 4], bpl
mov byte ptr [rsi + 4], bpl
mov word ptr [rsi + 4], bp
mov dword ptr [rsi + 4], ebp
mov qword ptr [rsi + 4], rbp
movzx si, bpl
movzx si, byte ptr [rbp + 4]
movzx esi, bpl
movzx esi, bp
movzx esi, byte ptr [rbp + 4]
movzx esi, word ptr [rbp + 4]
movzx rsi, bpl
movzx rsi, bp
movzx rsi, byte ptr [rbp + 4]
movzx rsi, word ptr [rbp + 4]
; Source: rbp, target: rdi
mov sil, 1
mov di, 1
mov edi, 1
mov rdi, 1
mov sil, bpl
mov di, bp
mov edi, ebp
mov rdi, rbp
mov sil, byte ptr [rbp - 4]
mov sil, byte ptr [rbp + 4]
mov di, word ptr [rbp + 4]
mov edi, dword ptr [rbp + 4]
mov rdi, qword ptr [rbp + 4]
mov byte ptr [rdi - 4], bpl
mov byte ptr [rdi + 4], bpl
mov word ptr [rdi + 4], bp
mov dword ptr [rdi + 4], ebp
mov qword ptr [rdi + 4], rbp
movzx di, bpl
movzx di, byte ptr [rbp + 4]
movzx edi, bpl
movzx edi, bp
movzx edi, byte ptr [rbp + 4]
movzx edi, word ptr [rbp + 4]
movzx rdi, bpl
movzx rdi, bp
movzx rdi, byte ptr [rbp + 4]
movzx rdi, word ptr [rbp + 4]
; Source: rbp, target: r8
mov r8b, 1
mov r8w, 1
mov r8d, 1
mov r8, 1
mov r8b, bpl
mov r8w, bp
mov r8d, ebp
mov r8, rbp
mov r8b, byte ptr [rbp - 4]
mov r8b, byte ptr [rbp + 4]
mov r8w, word ptr [rbp + 4]
mov r8d, dword ptr [rbp + 4]
mov r8, qword ptr [rbp + 4]
mov byte ptr [r8 - 4], bpl
mov byte ptr [r8 + 4], bpl
mov word ptr [r8 + 4], bp
mov dword ptr [r8 + 4], ebp
mov qword ptr [r8 + 4], rbp
movzx r8w, bpl
movzx r8w, byte ptr [rbp + 4]
movzx r8d, bpl
movzx r8d, bp
movzx r8d, byte ptr [rbp + 4]
movzx r8d, word ptr [rbp + 4]
movzx r8, bpl
movzx r8, bp
movzx r8, byte ptr [rbp + 4]
movzx r8, word ptr [rbp + 4]
; Source: rbp, target: r9
mov r9b, 1
mov r9w, 1
mov r9d, 1
mov r9, 1
mov r9b, bpl
mov r9w, bp
mov r9d, ebp
mov r9, rbp
mov r9b, byte ptr [rbp - 4]
mov r9b, byte ptr [rbp + 4]
mov r9w, word ptr [rbp + 4]
mov r9d, dword ptr [rbp + 4]
mov r9, qword ptr [rbp + 4]
mov byte ptr [r9 - 4], bpl
mov byte ptr [r9 + 4], bpl
mov word ptr [r9 + 4], bp
mov dword ptr [r9 + 4], ebp
mov qword ptr [r9 + 4], rbp
movzx r9w, bpl
movzx r9w, byte ptr [rbp + 4]
movzx r9d, bpl
movzx r9d, bp
movzx r9d, byte ptr [rbp + 4]
movzx r9d, word ptr [rbp + 4]
movzx r9, bpl
movzx r9, bp
movzx r9, byte ptr [rbp + 4]
movzx r9, word ptr [rbp + 4]
; Source: rbp, target: r10
mov r10b, 1
mov r10w, 1
mov r10d, 1
mov r10, 1
mov r10b, bpl
mov r10w, bp
mov r10d, ebp
mov r10, rbp
mov r10b, byte ptr [rbp - 4]
mov r10b, byte ptr [rbp + 4]
mov r10w, word ptr [rbp + 4]
mov r10d, dword ptr [rbp + 4]
mov r10, qword ptr [rbp + 4]
mov byte ptr [r10 - 4], bpl
mov byte ptr [r10 + 4], bpl
mov word ptr [r10 + 4], bp
mov dword ptr [r10 + 4], ebp
mov qword ptr [r10 + 4], rbp
movzx r10w, bpl
movzx r10w, byte ptr [rbp + 4]
movzx r10d, bpl
movzx r10d, bp
movzx r10d, byte ptr [rbp + 4]
movzx r10d, word ptr [rbp + 4]
movzx r10, bpl
movzx r10, bp
movzx r10, byte ptr [rbp + 4]
movzx r10, word ptr [rbp + 4]
; Source: rbp, target: r11
mov r11b, 1
mov r11w, 1
mov r11d, 1
mov r11, 1
mov r11b, bpl
mov r11w, bp
mov r11d, ebp
mov r11, rbp
mov r11b, byte ptr [rbp - 4]
mov r11b, byte ptr [rbp + 4]
mov r11w, word ptr [rbp + 4]
mov r11d, dword ptr [rbp + 4]
mov r11, qword ptr [rbp + 4]
mov byte ptr [r11 - 4], bpl
mov byte ptr [r11 + 4], bpl
mov word ptr [r11 + 4], bp
mov dword ptr [r11 + 4], ebp
mov qword ptr [r11 + 4], rbp
movzx r11w, bpl
movzx r11w, byte ptr [rbp + 4]
movzx r11d, bpl
movzx r11d, bp
movzx r11d, byte ptr [rbp + 4]
movzx r11d, word ptr [rbp + 4]
movzx r11, bpl
movzx r11, bp
movzx r11, byte ptr [rbp + 4]
movzx r11, word ptr [rbp + 4]
; Source: rbp, target: r12
mov r12b, 1
mov r12w, 1
mov r12d, 1
mov r12, 1
mov r12b, bpl
mov r12w, bp
mov r12d, ebp
mov r12, rbp
mov r12b, byte ptr [rbp - 4]
mov r12b, byte ptr [rbp + 4]
mov r12w, word ptr [rbp + 4]
mov r12d, dword ptr [rbp + 4]
mov r12, qword ptr [rbp + 4]
mov byte ptr [r12 - 4], bpl
mov byte ptr [r12 + 4], bpl
mov word ptr [r12 + 4], bp
mov dword ptr [r12 + 4], ebp
mov qword ptr [r12 + 4], rbp
movzx r12w, bpl
movzx r12w, byte ptr [rbp + 4]
movzx r12d, bpl
movzx r12d, bp
movzx r12d, byte ptr [rbp + 4]
movzx r12d, word ptr [rbp + 4]
movzx r12, bpl
movzx r12, bp
movzx r12, byte ptr [rbp + 4]
movzx r12, word ptr [rbp + 4]
; Source: rbp, target: r13
mov r13b, 1
mov r13w, 1
mov r13d, 1
mov r13, 1
mov r13b, bpl
mov r13w, bp
mov r13d, ebp
mov r13, rbp
mov r13b, byte ptr [rbp - 4]
mov r13b, byte ptr [rbp + 4]
mov r13w, word ptr [rbp + 4]
mov r13d, dword ptr [rbp + 4]
mov r13, qword ptr [rbp + 4]
mov byte ptr [r13 - 4], bpl
mov byte ptr [r13 + 4], bpl
mov word ptr [r13 + 4], bp
mov dword ptr [r13 + 4], ebp
mov qword ptr [r13 + 4], rbp
movzx r13w, bpl
movzx r13w, byte ptr [rbp + 4]
movzx r13d, bpl
movzx r13d, bp
movzx r13d, byte ptr [rbp + 4]
movzx r13d, word ptr [rbp + 4]
movzx r13, bpl
movzx r13, bp
movzx r13, byte ptr [rbp + 4]
movzx r13, word ptr [rbp + 4]
; Source: rbp, target: r14
mov r14b, 1
mov r14w, 1
mov r14d, 1
mov r14, 1
mov r14b, bpl
mov r14w, bp
mov r14d, ebp
mov r14, rbp
mov r14b, byte ptr [rbp - 4]
mov r14b, byte ptr [rbp + 4]
mov r14w, word ptr [rbp + 4]
mov r14d, dword ptr [rbp + 4]
mov r14, qword ptr [rbp + 4]
mov byte ptr [r14 - 4], bpl
mov byte ptr [r14 + 4], bpl
mov word ptr [r14 + 4], bp
mov dword ptr [r14 + 4], ebp
mov qword ptr [r14 + 4], rbp
movzx r14w, bpl
movzx r14w, byte ptr [rbp + 4]
movzx r14d, bpl
movzx r14d, bp
movzx r14d, byte ptr [rbp + 4]
movzx r14d, word ptr [rbp + 4]
movzx r14, bpl
movzx r14, bp
movzx r14, byte ptr [rbp + 4]
movzx r14, word ptr [rbp + 4]
; Source: rbp, target: r15
mov r15b, 1
mov r15w, 1
mov r15d, 1
mov r15, 1
mov r15b, bpl
mov r15w, bp
mov r15d, ebp
mov r15, rbp
mov r15b, byte ptr [rbp - 4]
mov r15b, byte ptr [rbp + 4]
mov r15w, word ptr [rbp + 4]
mov r15d, dword ptr [rbp + 4]
mov r15, qword ptr [rbp + 4]
mov byte ptr [r15 - 4], bpl
mov byte ptr [r15 + 4], bpl
mov word ptr [r15 + 4], bp
mov dword ptr [r15 + 4], ebp
mov qword ptr [r15 + 4], rbp
movzx r15w, bpl
movzx r15w, byte ptr [rbp + 4]
movzx r15d, bpl
movzx r15d, bp
movzx r15d, byte ptr [rbp + 4]
movzx r15d, word ptr [rbp + 4]
movzx r15, bpl
movzx r15, bp
movzx r15, byte ptr [rbp + 4]
movzx r15, word ptr [rbp + 4]
; Source: rsi, target: rax
mov al, 1
mov ax, 1
mov eax, 1
mov rax, 1
mov al, dil
mov ax, si
mov eax, esi
mov rax, rsi
mov al, byte ptr [rsi - 4]
mov al, byte ptr [rsi + 4]
mov ax, word ptr [rsi + 4]
mov eax, dword ptr [rsi + 4]
mov rax, qword ptr [rsi + 4]
mov byte ptr [rax - 4], dil
mov byte ptr [rax + 4], dil
mov word ptr [rax + 4], si
mov dword ptr [rax + 4], esi
mov qword ptr [rax + 4], rsi
movzx ax, dil
movzx ax, byte ptr [rsi + 4]
movzx eax, dil
movzx eax, si
movzx eax, byte ptr [rsi + 4]
movzx eax, word ptr [rsi + 4]
movzx rax, dil
movzx rax, si
movzx rax, byte ptr [rsi + 4]
movzx rax, word ptr [rsi + 4]
; Source: rsi, target: rcx
mov cl, 1
mov cx, 1
mov ecx, 1
mov rcx, 1
mov cl, dil
mov cx, si
mov ecx, esi
mov rcx, rsi
mov cl, byte ptr [rsi - 4]
mov cl, byte ptr [rsi + 4]
mov cx, word ptr [rsi + 4]
mov ecx, dword ptr [rsi + 4]
mov rcx, qword ptr [rsi + 4]
mov byte ptr [rcx - 4], dil
mov byte ptr [rcx + 4], dil
mov word ptr [rcx + 4], si
mov dword ptr [rcx + 4], esi
mov qword ptr [rcx + 4], rsi
movzx cx, dil
movzx cx, byte ptr [rsi + 4]
movzx ecx, dil
movzx ecx, si
movzx ecx, byte ptr [rsi + 4]
movzx ecx, word ptr [rsi + 4]
movzx rcx, dil
movzx rcx, si
movzx rcx, byte ptr [rsi + 4]
movzx rcx, word ptr [rsi + 4]
; Source: rsi, target: rdx
mov dl, 1
mov dx, 1
mov edx, 1
mov rdx, 1
mov dl, dil
mov dx, si
mov edx, esi
mov rdx, rsi
mov dl, byte ptr [rsi - 4]
mov dl, byte ptr [rsi + 4]
mov dx, word ptr [rsi + 4]
mov edx, dword ptr [rsi + 4]
mov rdx, qword ptr [rsi + 4]
mov byte ptr [rdx - 4], dil
mov byte ptr [rdx + 4], dil
mov word ptr [rdx + 4], si
mov dword ptr [rdx + 4], esi
mov qword ptr [rdx + 4], rsi
movzx dx, dil
movzx dx, byte ptr [rsi + 4]
movzx edx, dil
movzx edx, si
movzx edx, byte ptr [rsi + 4]
movzx edx, word ptr [rsi + 4]
movzx rdx, dil
movzx rdx, si
movzx rdx, byte ptr [rsi + 4]
movzx rdx, word ptr [rsi + 4]
; Source: rsi, target: rbx
mov bl, 1
mov bx, 1
mov ebx, 1
mov rbx, 1
mov bl, dil
mov bx, si
mov ebx, esi
mov rbx, rsi
mov bl, byte ptr [rsi - 4]
mov bl, byte ptr [rsi + 4]
mov bx, word ptr [rsi + 4]
mov ebx, dword ptr [rsi + 4]
mov rbx, qword ptr [rsi + 4]
mov byte ptr [rbx - 4], dil
mov byte ptr [rbx + 4], dil
mov word ptr [rbx + 4], si
mov dword ptr [rbx + 4], esi
mov qword ptr [rbx + 4], rsi
movzx bx, dil
movzx bx, byte ptr [rsi + 4]
movzx ebx, dil
movzx ebx, si
movzx ebx, byte ptr [rsi + 4]
movzx ebx, word ptr [rsi + 4]
movzx rbx, dil
movzx rbx, si
movzx rbx, byte ptr [rsi + 4]
movzx rbx, word ptr [rsi + 4]
; Source: rsi, target: rsp
mov spl, 1
mov sp, 1
mov esp, 1
mov rsp, 1
mov spl, dil
mov sp, si
mov esp, esi
mov rsp, rsi
mov spl, byte ptr [rsi - 4]
mov spl, byte ptr [rsi + 4]
mov sp, word ptr [rsi + 4]
mov esp, dword ptr [rsi + 4]
mov rsp, qword ptr [rsi + 4]
mov byte ptr [rsp - 4], dil
mov byte ptr [rsp + 4], dil
mov word ptr [rsp + 4], si
mov dword ptr [rsp + 4], esi
mov qword ptr [rsp + 4], rsi
movzx sp, dil
movzx sp, byte ptr [rsi + 4]
movzx esp, dil
movzx esp, si
movzx esp, byte ptr [rsi + 4]
movzx esp, word ptr [rsi + 4]
movzx rsp, dil
movzx rsp, si
movzx rsp, byte ptr [rsi + 4]
movzx rsp, word ptr [rsi + 4]
; Source: rsi, target: rbp
mov bpl, 1
mov bp, 1
mov ebp, 1
mov rbp, 1
mov bpl, dil
mov bp, si
mov ebp, esi
mov rbp, rsi
mov bpl, byte ptr [rsi - 4]
mov bpl, byte ptr [rsi + 4]
mov bp, word ptr [rsi + 4]
mov ebp, dword ptr [rsi + 4]
mov rbp, qword ptr [rsi + 4]
mov byte ptr [rbp - 4], dil
mov byte ptr [rbp + 4], dil
mov word ptr [rbp + 4], si
mov dword ptr [rbp + 4], esi
mov qword ptr [rbp + 4], rsi
movzx bp, dil
movzx bp, byte ptr [rsi + 4]
movzx ebp, dil
movzx ebp, si
movzx ebp, byte ptr [rsi + 4]
movzx ebp, word ptr [rsi + 4]
movzx rbp, dil
movzx rbp, si
movzx rbp, byte ptr [rsi + 4]
movzx rbp, word ptr [rsi + 4]
; Source: rsi, target: rsi
mov dil, 1
mov si, 1
mov esi, 1
mov rsi, 1
mov dil, dil
mov si, si
mov esi, esi
mov rsi, rsi
mov dil, byte ptr [rsi - 4]
mov dil, byte ptr [rsi + 4]
mov si, word ptr [rsi + 4]
mov esi, dword ptr [rsi + 4]
mov rsi, qword ptr [rsi + 4]
mov byte ptr [rsi - 4], dil
mov byte ptr [rsi + 4], dil
mov word ptr [rsi + 4], si
mov dword ptr [rsi + 4], esi
mov qword ptr [rsi + 4], rsi
movzx si, dil
movzx si, byte ptr [rsi + 4]
movzx esi, dil
movzx esi, si
movzx esi, byte ptr [rsi + 4]
movzx esi, word ptr [rsi + 4]
movzx rsi, dil
movzx rsi, si
movzx rsi, byte ptr [rsi + 4]
movzx rsi, word ptr [rsi + 4]
; Source: rsi, target: rdi
mov sil, 1
mov di, 1
mov edi, 1
mov rdi, 1
mov sil, dil
mov di, si
mov edi, esi
mov rdi, rsi
mov sil, byte ptr [rsi - 4]
mov sil, byte ptr [rsi + 4]
mov di, word ptr [rsi + 4]
mov edi, dword ptr [rsi + 4]
mov rdi, qword ptr [rsi + 4]
mov byte ptr [rdi - 4], dil
mov byte ptr [rdi + 4], dil
mov word ptr [rdi + 4], si
mov dword ptr [rdi + 4], esi
mov qword ptr [rdi + 4], rsi
movzx di, dil
movzx di, byte ptr [rsi + 4]
movzx edi, dil
movzx edi, si
movzx edi, byte ptr [rsi + 4]
movzx edi, word ptr [rsi + 4]
movzx rdi, dil
movzx rdi, si
movzx rdi, byte ptr [rsi + 4]
movzx rdi, word ptr [rsi + 4]
; Source: rsi, target: r8
mov r8b, 1
mov r8w, 1
mov r8d, 1
mov r8, 1
mov r8b, dil
mov r8w, si
mov r8d, esi
mov r8, rsi
mov r8b, byte ptr [rsi - 4]
mov r8b, byte ptr [rsi + 4]
mov r8w, word ptr [rsi + 4]
mov r8d, dword ptr [rsi + 4]
mov r8, qword ptr [rsi + 4]
mov byte ptr [r8 - 4], dil
mov byte ptr [r8 + 4], dil
mov word ptr [r8 + 4], si
mov dword ptr [r8 + 4], esi
mov qword ptr [r8 + 4], rsi
movzx r8w, dil
movzx r8w, byte ptr [rsi + 4]
movzx r8d, dil
movzx r8d, si
movzx r8d, byte ptr [rsi + 4]
movzx r8d, word ptr [rsi + 4]
movzx r8, dil
movzx r8, si
movzx r8, byte ptr [rsi + 4]
movzx r8, word ptr [rsi + 4]
; Source: rsi, target: r9
mov r9b, 1
mov r9w, 1
mov r9d, 1
mov r9, 1
mov r9b, dil
mov r9w, si
mov r9d, esi
mov r9, rsi
mov r9b, byte ptr [rsi - 4]
mov r9b, byte ptr [rsi + 4]
mov r9w, word ptr [rsi + 4]
mov r9d, dword ptr [rsi + 4]
mov r9, qword ptr [rsi + 4]
mov byte ptr [r9 - 4], dil
mov byte ptr [r9 + 4], dil
mov word ptr [r9 + 4], si
mov dword ptr [r9 + 4], esi
mov qword ptr [r9 + 4], rsi
movzx r9w, dil
movzx r9w, byte ptr [rsi + 4]
movzx r9d, dil
movzx r9d, si
movzx r9d, byte ptr [rsi + 4]
movzx r9d, word ptr [rsi + 4]
movzx r9, dil
movzx r9, si
movzx r9, byte ptr [rsi + 4]
movzx r9, word ptr [rsi + 4]
; Source: rsi, target: r10
mov r10b, 1
mov r10w, 1
mov r10d, 1
mov r10, 1
mov r10b, dil
mov r10w, si
mov r10d, esi
mov r10, rsi
mov r10b, byte ptr [rsi - 4]
mov r10b, byte ptr [rsi + 4]
mov r10w, word ptr [rsi + 4]
mov r10d, dword ptr [rsi + 4]
mov r10, qword ptr [rsi + 4]
mov byte ptr [r10 - 4], dil
mov byte ptr [r10 + 4], dil
mov word ptr [r10 + 4], si
mov dword ptr [r10 + 4], esi
mov qword ptr [r10 + 4], rsi
movzx r10w, dil
movzx r10w, byte ptr [rsi + 4]
movzx r10d, dil
movzx r10d, si
movzx r10d, byte ptr [rsi + 4]
movzx r10d, word ptr [rsi + 4]
movzx r10, dil
movzx r10, si
movzx r10, byte ptr [rsi + 4]
movzx r10, word ptr [rsi + 4]
; Source: rsi, target: r11
mov r11b, 1
mov r11w, 1
mov r11d, 1
mov r11, 1
mov r11b, dil
mov r11w, si
mov r11d, esi
mov r11, rsi
mov r11b, byte ptr [rsi - 4]
mov r11b, byte ptr [rsi + 4]
mov r11w, word ptr [rsi + 4]
mov r11d, dword ptr [rsi + 4]
mov r11, qword ptr [rsi + 4]
mov byte ptr [r11 - 4], dil
mov byte ptr [r11 + 4], dil
mov word ptr [r11 + 4], si
mov dword ptr [r11 + 4], esi
mov qword ptr [r11 + 4], rsi
movzx r11w, dil
movzx r11w, byte ptr [rsi + 4]
movzx r11d, dil
movzx r11d, si
movzx r11d, byte ptr [rsi + 4]
movzx r11d, word ptr [rsi + 4]
movzx r11, dil
movzx r11, si
movzx r11, byte ptr [rsi + 4]
movzx r11, word ptr [rsi + 4]
; Source: rsi, target: r12
mov r12b, 1
mov r12w, 1
mov r12d, 1
mov r12, 1
mov r12b, dil
mov r12w, si
mov r12d, esi
mov r12, rsi
mov r12b, byte ptr [rsi - 4]
mov r12b, byte ptr [rsi + 4]
mov r12w, word ptr [rsi + 4]
mov r12d, dword ptr [rsi + 4]
mov r12, qword ptr [rsi + 4]
mov byte ptr [r12 - 4], dil
mov byte ptr [r12 + 4], dil
mov word ptr [r12 + 4], si
mov dword ptr [r12 + 4], esi
mov qword ptr [r12 + 4], rsi
movzx r12w, dil
movzx r12w, byte ptr [rsi + 4]
movzx r12d, dil
movzx r12d, si
movzx r12d, byte ptr [rsi + 4]
movzx r12d, word ptr [rsi + 4]
movzx r12, dil
movzx r12, si
movzx r12, byte ptr [rsi + 4]
movzx r12, word ptr [rsi + 4]
; Source: rsi, target: r13
mov r13b, 1
mov r13w, 1
mov r13d, 1
mov r13, 1
mov r13b, dil
mov r13w, si
mov r13d, esi
mov r13, rsi
mov r13b, byte ptr [rsi - 4]
mov r13b, byte ptr [rsi + 4]
mov r13w, word ptr [rsi + 4]
mov r13d, dword ptr [rsi + 4]
mov r13, qword ptr [rsi + 4]
mov byte ptr [r13 - 4], dil
mov byte ptr [r13 + 4], dil
mov word ptr [r13 + 4], si
mov dword ptr [r13 + 4], esi
mov qword ptr [r13 + 4], rsi
movzx r13w, dil
movzx r13w, byte ptr [rsi + 4]
movzx r13d, dil
movzx r13d, si
movzx r13d, byte ptr [rsi + 4]
movzx r13d, word ptr [rsi + 4]
movzx r13, dil
movzx r13, si
movzx r13, byte ptr [rsi + 4]
movzx r13, word ptr [rsi + 4]
; Source: rsi, target: r14
mov r14b, 1
mov r14w, 1
mov r14d, 1
mov r14, 1
mov r14b, dil
mov r14w, si
mov r14d, esi
mov r14, rsi
mov r14b, byte ptr [rsi - 4]
mov r14b, byte ptr [rsi + 4]
mov r14w, word ptr [rsi + 4]
mov r14d, dword ptr [rsi + 4]
mov r14, qword ptr [rsi + 4]
mov byte ptr [r14 - 4], dil
mov byte ptr [r14 + 4], dil
mov word ptr [r14 + 4], si
mov dword ptr [r14 + 4], esi
mov qword ptr [r14 + 4], rsi
movzx r14w, dil
movzx r14w, byte ptr [rsi + 4]
movzx r14d, dil
movzx r14d, si
movzx r14d, byte ptr [rsi + 4]
movzx r14d, word ptr [rsi + 4]
movzx r14, dil
movzx r14, si
movzx r14, byte ptr [rsi + 4]
movzx r14, word ptr [rsi + 4]
; Source: rsi, target: r15
mov r15b, 1
mov r15w, 1
mov r15d, 1
mov r15, 1
mov r15b, dil
mov r15w, si
mov r15d, esi
mov r15, rsi
mov r15b, byte ptr [rsi - 4]
mov r15b, byte ptr [rsi + 4]
mov r15w, word ptr [rsi + 4]
mov r15d, dword ptr [rsi + 4]
mov r15, qword ptr [rsi + 4]
mov byte ptr [r15 - 4], dil
mov byte ptr [r15 + 4], dil
mov word ptr [r15 + 4], si
mov dword ptr [r15 + 4], esi
mov qword ptr [r15 + 4], rsi
movzx r15w, dil
movzx r15w, byte ptr [rsi + 4]
movzx r15d, dil
movzx r15d, si
movzx r15d, byte ptr [rsi + 4]
movzx r15d, word ptr [rsi + 4]
movzx r15, dil
movzx r15, si
movzx r15, byte ptr [rsi + 4]
movzx r15, word ptr [rsi + 4]
; Source: rdi, target: rax
mov al, 1
mov ax, 1
mov eax, 1
mov rax, 1
mov al, sil
mov ax, di
mov eax, edi
mov rax, rdi
mov al, byte ptr [rdi - 4]
mov al, byte ptr [rdi + 4]
mov ax, word ptr [rdi + 4]
mov eax, dword ptr [rdi + 4]
mov rax, qword ptr [rdi + 4]
mov byte ptr [rax - 4], sil
mov byte ptr [rax + 4], sil
mov word ptr [rax + 4], di
mov dword ptr [rax + 4], edi
mov qword ptr [rax + 4], rdi
movzx ax, sil
movzx ax, byte ptr [rdi + 4]
movzx eax, sil
movzx eax, di
movzx eax, byte ptr [rdi + 4]
movzx eax, word ptr [rdi + 4]
movzx rax, sil
movzx rax, di
movzx rax, byte ptr [rdi + 4]
movzx rax, word ptr [rdi + 4]
; Source: rdi, target: rcx
mov cl, 1
mov cx, 1
mov ecx, 1
mov rcx, 1
mov cl, sil
mov cx, di
mov ecx, edi
mov rcx, rdi
mov cl, byte ptr [rdi - 4]
mov cl, byte ptr [rdi + 4]
mov cx, word ptr [rdi + 4]
mov ecx, dword ptr [rdi + 4]
mov rcx, qword ptr [rdi + 4]
mov byte ptr [rcx - 4], sil
mov byte ptr [rcx + 4], sil
mov word ptr [rcx + 4], di
mov dword ptr [rcx + 4], edi
mov qword ptr [rcx + 4], rdi
movzx cx, sil
movzx cx, byte ptr [rdi + 4]
movzx ecx, sil
movzx ecx, di
movzx ecx, byte ptr [rdi + 4]
movzx ecx, word ptr [rdi + 4]
movzx rcx, sil
movzx rcx, di
movzx rcx, byte ptr [rdi + 4]
movzx rcx, word ptr [rdi + 4]
; Source: rdi, target: rdx
mov dl, 1
mov dx, 1
mov edx, 1
mov rdx, 1
mov dl, sil
mov dx, di
mov edx, edi
mov rdx, rdi
mov dl, byte ptr [rdi - 4]
mov dl, byte ptr [rdi + 4]
mov dx, word ptr [rdi + 4]
mov edx, dword ptr [rdi + 4]
mov rdx, qword ptr [rdi + 4]
mov byte ptr [rdx - 4], sil
mov byte ptr [rdx + 4], sil
mov word ptr [rdx + 4], di
mov dword ptr [rdx + 4], edi
mov qword ptr [rdx + 4], rdi
movzx dx, sil
movzx dx, byte ptr [rdi + 4]
movzx edx, sil
movzx edx, di
movzx edx, byte ptr [rdi + 4]
movzx edx, word ptr [rdi + 4]
movzx rdx, sil
movzx rdx, di
movzx rdx, byte ptr [rdi + 4]
movzx rdx, word ptr [rdi + 4]
; Source: rdi, target: rbx
mov bl, 1
mov bx, 1
mov ebx, 1
mov rbx, 1
mov bl, sil
mov bx, di
mov ebx, edi
mov rbx, rdi
mov bl, byte ptr [rdi - 4]
mov bl, byte ptr [rdi + 4]
mov bx, word ptr [rdi + 4]
mov ebx, dword ptr [rdi + 4]
mov rbx, qword ptr [rdi + 4]
mov byte ptr [rbx - 4], sil
mov byte ptr [rbx + 4], sil
mov word ptr [rbx + 4], di
mov dword ptr [rbx + 4], edi
mov qword ptr [rbx + 4], rdi
movzx bx, sil
movzx bx, byte ptr [rdi + 4]
movzx ebx, sil
movzx ebx, di
movzx ebx, byte ptr [rdi + 4]
movzx ebx, word ptr [rdi + 4]
movzx rbx, sil
movzx rbx, di
movzx rbx, byte ptr [rdi + 4]
movzx rbx, word ptr [rdi + 4]
; Source: rdi, target: rsp
mov spl, 1
mov sp, 1
mov esp, 1
mov rsp, 1
mov spl, sil
mov sp, di
mov esp, edi
mov rsp, rdi
mov spl, byte ptr [rdi - 4]
mov spl, byte ptr [rdi + 4]
mov sp, word ptr [rdi + 4]
mov esp, dword ptr [rdi + 4]
mov rsp, qword ptr [rdi + 4]
mov byte ptr [rsp - 4], sil
mov byte ptr [rsp + 4], sil
mov word ptr [rsp + 4], di
mov dword ptr [rsp + 4], edi
mov qword ptr [rsp + 4], rdi
movzx sp, sil
movzx sp, byte ptr [rdi + 4]
movzx esp, sil
movzx esp, di
movzx esp, byte ptr [rdi + 4]
movzx esp, word ptr [rdi + 4]
movzx rsp, sil
movzx rsp, di
movzx rsp, byte ptr [rdi + 4]
movzx rsp, word ptr [rdi + 4]
; Source: rdi, target: rbp
mov bpl, 1
mov bp, 1
mov ebp, 1
mov rbp, 1
mov bpl, sil
mov bp, di
mov ebp, edi
mov rbp, rdi
mov bpl, byte ptr [rdi - 4]
mov bpl, byte ptr [rdi + 4]
mov bp, word ptr [rdi + 4]
mov ebp, dword ptr [rdi + 4]
mov rbp, qword ptr [rdi + 4]
mov byte ptr [rbp - 4], sil
mov byte ptr [rbp + 4], sil
mov word ptr [rbp + 4], di
mov dword ptr [rbp + 4], edi
mov qword ptr [rbp + 4], rdi
movzx bp, sil
movzx bp, byte ptr [rdi + 4]
movzx ebp, sil
movzx ebp, di
movzx ebp, byte ptr [rdi + 4]
movzx ebp, word ptr [rdi + 4]
movzx rbp, sil
movzx rbp, di
movzx rbp, byte ptr [rdi + 4]
movzx rbp, word ptr [rdi + 4]
; Source: rdi, target: rsi
mov dil, 1
mov si, 1
mov esi, 1
mov rsi, 1
mov dil, sil
mov si, di
mov esi, edi
mov rsi, rdi
mov dil, byte ptr [rdi - 4]
mov dil, byte ptr [rdi + 4]
mov si, word ptr [rdi + 4]
mov esi, dword ptr [rdi + 4]
mov rsi, qword ptr [rdi + 4]
mov byte ptr [rsi - 4], sil
mov byte ptr [rsi + 4], sil
mov word ptr [rsi + 4], di
mov dword ptr [rsi + 4], edi
mov qword ptr [rsi + 4], rdi
movzx si, sil
movzx si, byte ptr [rdi + 4]
movzx esi, sil
movzx esi, di
movzx esi, byte ptr [rdi + 4]
movzx esi, word ptr [rdi + 4]
movzx rsi, sil
movzx rsi, di
movzx rsi, byte ptr [rdi + 4]
movzx rsi, word ptr [rdi + 4]
; Source: rdi, target: rdi
mov sil, 1
mov di, 1
mov edi, 1
mov rdi, 1
mov sil, sil
mov di, di
mov edi, edi
mov rdi, rdi
mov sil, byte ptr [rdi - 4]
mov sil, byte ptr [rdi + 4]
mov di, word ptr [rdi + 4]
mov edi, dword ptr [rdi + 4]
mov rdi, qword ptr [rdi + 4]
mov byte ptr [rdi - 4], sil
mov byte ptr [rdi + 4], sil
mov word ptr [rdi + 4], di
mov dword ptr [rdi + 4], edi
mov qword ptr [rdi + 4], rdi
movzx di, sil
movzx di, byte ptr [rdi + 4]
movzx edi, sil
movzx edi, di
movzx edi, byte ptr [rdi + 4]
movzx edi, word ptr [rdi + 4]
movzx rdi, sil
movzx rdi, di
movzx rdi, byte ptr [rdi + 4]
movzx rdi, word ptr [rdi + 4]
; Source: rdi, target: r8
mov r8b, 1
mov r8w, 1
mov r8d, 1
mov r8, 1
mov r8b, sil
mov r8w, di
mov r8d, edi
mov r8, rdi
mov r8b, byte ptr [rdi - 4]
mov r8b, byte ptr [rdi + 4]
mov r8w, word ptr [rdi + 4]
mov r8d, dword ptr [rdi + 4]
mov r8, qword ptr [rdi + 4]
mov byte ptr [r8 - 4], sil
mov byte ptr [r8 + 4], sil
mov word ptr [r8 + 4], di
mov dword ptr [r8 + 4], edi
mov qword ptr [r8 + 4], rdi
movzx r8w, sil
movzx r8w, byte ptr [rdi + 4]
movzx r8d, sil
movzx r8d, di
movzx r8d, byte ptr [rdi + 4]
movzx r8d, word ptr [rdi + 4]
movzx r8, sil
movzx r8, di
movzx r8, byte ptr [rdi + 4]
movzx r8, word ptr [rdi + 4]
; Source: rdi, target: r9
mov r9b, 1
mov r9w, 1
mov r9d, 1
mov r9, 1
mov r9b, sil
mov r9w, di
mov r9d, edi
mov r9, rdi
mov r9b, byte ptr [rdi - 4]
mov r9b, byte ptr [rdi + 4]
mov r9w, word ptr [rdi + 4]
mov r9d, dword ptr [rdi + 4]
mov r9, qword ptr [rdi + 4]
mov byte ptr [r9 - 4], sil
mov byte ptr [r9 + 4], sil
mov word ptr [r9 + 4], di
mov dword ptr [r9 + 4], edi
mov qword ptr [r9 + 4], rdi
movzx r9w, sil
movzx r9w, byte ptr [rdi + 4]
movzx r9d, sil
movzx r9d, di
movzx r9d, byte ptr [rdi + 4]
movzx r9d, word ptr [rdi + 4]
movzx r9, sil
movzx r9, di
movzx r9, byte ptr [rdi + 4]
movzx r9, word ptr [rdi + 4]
; Source: rdi, target: r10
mov r10b, 1
mov r10w, 1
mov r10d, 1
mov r10, 1
mov r10b, sil
mov r10w, di
mov r10d, edi
mov r10, rdi
mov r10b, byte ptr [rdi - 4]
mov r10b, byte ptr [rdi + 4]
mov r10w, word ptr [rdi + 4]
mov r10d, dword ptr [rdi + 4]
mov r10, qword ptr [rdi + 4]
mov byte ptr [r10 - 4], sil
mov byte ptr [r10 + 4], sil
mov word ptr [r10 + 4], di
mov dword ptr [r10 + 4], edi
mov qword ptr [r10 + 4], rdi
movzx r10w, sil
movzx r10w, byte ptr [rdi + 4]
movzx r10d, sil
movzx r10d, di
movzx r10d, byte ptr [rdi + 4]
movzx r10d, word ptr [rdi + 4]
movzx r10, sil
movzx r10, di
movzx r10, byte ptr [rdi + 4]
movzx r10, word ptr [rdi + 4]
; Source: rdi, target: r11
mov r11b, 1
mov r11w, 1
mov r11d, 1
mov r11, 1
mov r11b, sil
mov r11w, di
mov r11d, edi
mov r11, rdi
mov r11b, byte ptr [rdi - 4]
mov r11b, byte ptr [rdi + 4]
mov r11w, word ptr [rdi + 4]
mov r11d, dword ptr [rdi + 4]
mov r11, qword ptr [rdi + 4]
mov byte ptr [r11 - 4], sil
mov byte ptr [r11 + 4], sil
mov word ptr [r11 + 4], di
mov dword ptr [r11 + 4], edi
mov qword ptr [r11 + 4], rdi
movzx r11w, sil
movzx r11w, byte ptr [rdi + 4]
movzx r11d, sil
movzx r11d, di
movzx r11d, byte ptr [rdi + 4]
movzx r11d, word ptr [rdi + 4]
movzx r11, sil
movzx r11, di
movzx r11, byte ptr [rdi + 4]
movzx r11, word ptr [rdi + 4]
; Source: rdi, target: r12
mov r12b, 1
mov r12w, 1
mov r12d, 1
mov r12, 1
mov r12b, sil
mov r12w, di
mov r12d, edi
mov r12, rdi
mov r12b, byte ptr [rdi - 4]
mov r12b, byte ptr [rdi + 4]
mov r12w, word ptr [rdi + 4]
mov r12d, dword ptr [rdi + 4]
mov r12, qword ptr [rdi + 4]
mov byte ptr [r12 - 4], sil
mov byte ptr [r12 + 4], sil
mov word ptr [r12 + 4], di
mov dword ptr [r12 + 4], edi
mov qword ptr [r12 + 4], rdi
movzx r12w, sil
movzx r12w, byte ptr [rdi + 4]
movzx r12d, sil
movzx r12d, di
movzx r12d, byte ptr [rdi + 4]
movzx r12d, word ptr [rdi + 4]
movzx r12, sil
movzx r12, di
movzx r12, byte ptr [rdi + 4]
movzx r12, word ptr [rdi + 4]
; Source: rdi, target: r13
mov r13b, 1
mov r13w, 1
mov r13d, 1
mov r13, 1
mov r13b, sil
mov r13w, di
mov r13d, edi
mov r13, rdi
mov r13b, byte ptr [rdi - 4]
mov r13b, byte ptr [rdi + 4]
mov r13w, word ptr [rdi + 4]
mov r13d, dword ptr [rdi + 4]
mov r13, qword ptr [rdi + 4]
mov byte ptr [r13 - 4], sil
mov byte ptr [r13 + 4], sil
mov word ptr [r13 + 4], di
mov dword ptr [r13 + 4], edi
mov qword ptr [r13 + 4], rdi
movzx r13w, sil
movzx r13w, byte ptr [rdi + 4]
movzx r13d, sil
movzx r13d, di
movzx r13d, byte ptr [rdi + 4]
movzx r13d, word ptr [rdi + 4]
movzx r13, sil
movzx r13, di
movzx r13, byte ptr [rdi + 4]
movzx r13, word ptr [rdi + 4]
; Source: rdi, target: r14
mov r14b, 1
mov r14w, 1
mov r14d, 1
mov r14, 1
mov r14b, sil
mov r14w, di
mov r14d, edi
mov r14, rdi
mov r14b, byte ptr [rdi - 4]
mov r14b, byte ptr [rdi + 4]
mov r14w, word ptr [rdi + 4]
mov r14d, dword ptr [rdi + 4]
mov r14, qword ptr [rdi + 4]
mov byte ptr [r14 - 4], sil
mov byte ptr [r14 + 4], sil
mov word ptr [r14 + 4], di
mov dword ptr [r14 + 4], edi
mov qword ptr [r14 + 4], rdi
movzx r14w, sil
movzx r14w, byte ptr [rdi + 4]
movzx r14d, sil
movzx r14d, di
movzx r14d, byte ptr [rdi + 4]
movzx r14d, word ptr [rdi + 4]
movzx r14, sil
movzx r14, di
movzx r14, byte ptr [rdi + 4]
movzx r14, word ptr [rdi + 4]
; Source: rdi, target: r15
mov r15b, 1
mov r15w, 1
mov r15d, 1
mov r15, 1
mov r15b, sil
mov r15w, di
mov r15d, edi
mov r15, rdi
mov r15b, byte ptr [rdi - 4]
mov r15b, byte ptr [rdi + 4]
mov r15w, word ptr [rdi + 4]
mov r15d, dword ptr [rdi + 4]
mov r15, qword ptr [rdi + 4]
mov byte ptr [r15 - 4], sil
mov byte ptr [r15 + 4], sil
mov word ptr [r15 + 4], di
mov dword ptr [r15 + 4], edi
mov qword ptr [r15 + 4], rdi
movzx r15w, sil
movzx r15w, byte ptr [rdi + 4]
movzx r15d, sil
movzx r15d, di
movzx r15d, byte ptr [rdi + 4]
movzx r15d, word ptr [rdi + 4]
movzx r15, sil
movzx r15, di
movzx r15, byte ptr [rdi + 4]
movzx r15, word ptr [rdi + 4]
; Source: r8, target: rax
mov al, 1
mov ax, 1
mov eax, 1
mov rax, 1
mov al, r8b
mov ax, r8w
mov eax, r8d
mov rax, r8
mov al, byte ptr [r8 - 4]
mov al, byte ptr [r8 + 4]
mov ax, word ptr [r8 + 4]
mov eax, dword ptr [r8 + 4]
mov rax, qword ptr [r8 + 4]
mov byte ptr [rax - 4], r8b
mov byte ptr [rax + 4], r8b
mov word ptr [rax + 4], r8w
mov dword ptr [rax + 4], r8d
mov qword ptr [rax + 4], r8
movzx ax, r8b
movzx ax, byte ptr [r8 + 4]
movzx eax, r8b
movzx eax, r8w
movzx eax, byte ptr [r8 + 4]
movzx eax, word ptr [r8 + 4]
movzx rax, r8b
movzx rax, r8w
movzx rax, byte ptr [r8 + 4]
movzx rax, word ptr [r8 + 4]
; Source: r8, target: rcx
mov cl, 1
mov cx, 1
mov ecx, 1
mov rcx, 1
mov cl, r8b
mov cx, r8w
mov ecx, r8d
mov rcx, r8
mov cl, byte ptr [r8 - 4]
mov cl, byte ptr [r8 + 4]
mov cx, word ptr [r8 + 4]
mov ecx, dword ptr [r8 + 4]
mov rcx, qword ptr [r8 + 4]
mov byte ptr [rcx - 4], r8b
mov byte ptr [rcx + 4], r8b
mov word ptr [rcx + 4], r8w
mov dword ptr [rcx + 4], r8d
mov qword ptr [rcx + 4], r8
movzx cx, r8b
movzx cx, byte ptr [r8 + 4]
movzx ecx, r8b
movzx ecx, r8w
movzx ecx, byte ptr [r8 + 4]
movzx ecx, word ptr [r8 + 4]
movzx rcx, r8b
movzx rcx, r8w
movzx rcx, byte ptr [r8 + 4]
movzx rcx, word ptr [r8 + 4]
; Source: r8, target: rdx
mov dl, 1
mov dx, 1
mov edx, 1
mov rdx, 1
mov dl, r8b
mov dx, r8w
mov edx, r8d
mov rdx, r8
mov dl, byte ptr [r8 - 4]
mov dl, byte ptr [r8 + 4]
mov dx, word ptr [r8 + 4]
mov edx, dword ptr [r8 + 4]
mov rdx, qword ptr [r8 + 4]
mov byte ptr [rdx - 4], r8b
mov byte ptr [rdx + 4], r8b
mov word ptr [rdx + 4], r8w
mov dword ptr [rdx + 4], r8d
mov qword ptr [rdx + 4], r8
movzx dx, r8b
movzx dx, byte ptr [r8 + 4]
movzx edx, r8b
movzx edx, r8w
movzx edx, byte ptr [r8 + 4]
movzx edx, word ptr [r8 + 4]
movzx rdx, r8b
movzx rdx, r8w
movzx rdx, byte ptr [r8 + 4]
movzx rdx, word ptr [r8 + 4]
; Source: r8, target: rbx
mov bl, 1
mov bx, 1
mov ebx, 1
mov rbx, 1
mov bl, r8b
mov bx, r8w
mov ebx, r8d
mov rbx, r8
mov bl, byte ptr [r8 - 4]
mov bl, byte ptr [r8 + 4]
mov bx, word ptr [r8 + 4]
mov ebx, dword ptr [r8 + 4]
mov rbx, qword ptr [r8 + 4]
mov byte ptr [rbx - 4], r8b
mov byte ptr [rbx + 4], r8b
mov word ptr [rbx + 4], r8w
mov dword ptr [rbx + 4], r8d
mov qword ptr [rbx + 4], r8
movzx bx, r8b
movzx bx, byte ptr [r8 + 4]
movzx ebx, r8b
movzx ebx, r8w
movzx ebx, byte ptr [r8 + 4]
movzx ebx, word ptr [r8 + 4]
movzx rbx, r8b
movzx rbx, r8w
movzx rbx, byte ptr [r8 + 4]
movzx rbx, word ptr [r8 + 4]
; Source: r8, target: rsp
mov spl, 1
mov sp, 1
mov esp, 1
mov rsp, 1
mov spl, r8b
mov sp, r8w
mov esp, r8d
mov rsp, r8
mov spl, byte ptr [r8 - 4]
mov spl, byte ptr [r8 + 4]
mov sp, word ptr [r8 + 4]
mov esp, dword ptr [r8 + 4]
mov rsp, qword ptr [r8 + 4]
mov byte ptr [rsp - 4], r8b
mov byte ptr [rsp + 4], r8b
mov word ptr [rsp + 4], r8w
mov dword ptr [rsp + 4], r8d
mov qword ptr [rsp + 4], r8
movzx sp, r8b
movzx sp, byte ptr [r8 + 4]
movzx esp, r8b
movzx esp, r8w
movzx esp, byte ptr [r8 + 4]
movzx esp, word ptr [r8 + 4]
movzx rsp, r8b
movzx rsp, r8w
movzx rsp, byte ptr [r8 + 4]
movzx rsp, word ptr [r8 + 4]
; Source: r8, target: rbp
mov bpl, 1
mov bp, 1
mov ebp, 1
mov rbp, 1
mov bpl, r8b
mov bp, r8w
mov ebp, r8d
mov rbp, r8
mov bpl, byte ptr [r8 - 4]
mov bpl, byte ptr [r8 + 4]
mov bp, word ptr [r8 + 4]
mov ebp, dword ptr [r8 + 4]
mov rbp, qword ptr [r8 + 4]
mov byte ptr [rbp - 4], r8b
mov byte ptr [rbp + 4], r8b
mov word ptr [rbp + 4], r8w
mov dword ptr [rbp + 4], r8d
mov qword ptr [rbp + 4], r8
movzx bp, r8b
movzx bp, byte ptr [r8 + 4]
movzx ebp, r8b
movzx ebp, r8w
movzx ebp, byte ptr [r8 + 4]
movzx ebp, word ptr [r8 + 4]
movzx rbp, r8b
movzx rbp, r8w
movzx rbp, byte ptr [r8 + 4]
movzx rbp, word ptr [r8 + 4]
; Source: r8, target: rsi
mov dil, 1
mov si, 1
mov esi, 1
mov rsi, 1
mov dil, r8b
mov si, r8w
mov esi, r8d
mov rsi, r8
mov dil, byte ptr [r8 - 4]
mov dil, byte ptr [r8 + 4]
mov si, word ptr [r8 + 4]
mov esi, dword ptr [r8 + 4]
mov rsi, qword ptr [r8 + 4]
mov byte ptr [rsi - 4], r8b
mov byte ptr [rsi + 4], r8b
mov word ptr [rsi + 4], r8w
mov dword ptr [rsi + 4], r8d
mov qword ptr [rsi + 4], r8
movzx si, r8b
movzx si, byte ptr [r8 + 4]
movzx esi, r8b
movzx esi, r8w
movzx esi, byte ptr [r8 + 4]
movzx esi, word ptr [r8 + 4]
movzx rsi, r8b
movzx rsi, r8w
movzx rsi, byte ptr [r8 + 4]
movzx rsi, word ptr [r8 + 4]
; Source: r8, target: rdi
mov sil, 1
mov di, 1
mov edi, 1
mov rdi, 1
mov sil, r8b
mov di, r8w
mov edi, r8d
mov rdi, r8
mov sil, byte ptr [r8 - 4]
mov sil, byte ptr [r8 + 4]
mov di, word ptr [r8 + 4]
mov edi, dword ptr [r8 + 4]
mov rdi, qword ptr [r8 + 4]
mov byte ptr [rdi - 4], r8b
mov byte ptr [rdi + 4], r8b
mov word ptr [rdi + 4], r8w
mov dword ptr [rdi + 4], r8d
mov qword ptr [rdi + 4], r8
movzx di, r8b
movzx di, byte ptr [r8 + 4]
movzx edi, r8b
movzx edi, r8w
movzx edi, byte ptr [r8 + 4]
movzx edi, word ptr [r8 + 4]
movzx rdi, r8b
movzx rdi, r8w
movzx rdi, byte ptr [r8 + 4]
movzx rdi, word ptr [r8 + 4]
; Source: r8, target: r8
mov r8b, 1
mov r8w, 1
mov r8d, 1
mov r8, 1
mov r8b, r8b
mov r8w, r8w
mov r8d, r8d
mov r8, r8
mov r8b, byte ptr [r8 - 4]
mov r8b, byte ptr [r8 + 4]
mov r8w, word ptr [r8 + 4]
mov r8d, dword ptr [r8 + 4]
mov r8, qword ptr [r8 + 4]
mov byte ptr [r8 - 4], r8b
mov byte ptr [r8 + 4], r8b
mov word ptr [r8 + 4], r8w
mov dword ptr [r8 + 4], r8d
mov qword ptr [r8 + 4], r8
movzx r8w, r8b
movzx r8w, byte ptr [r8 + 4]
movzx r8d, r8b
movzx r8d, r8w
movzx r8d, byte ptr [r8 + 4]
movzx r8d, word ptr [r8 + 4]
movzx r8, r8b
movzx r8, r8w
movzx r8, byte ptr [r8 + 4]
movzx r8, word ptr [r8 + 4]
; Source: r8, target: r9
mov r9b, 1
mov r9w, 1
mov r9d, 1
mov r9, 1
mov r9b, r8b
mov r9w, r8w
mov r9d, r8d
mov r9, r8
mov r9b, byte ptr [r8 - 4]
mov r9b, byte ptr [r8 + 4]
mov r9w, word ptr [r8 + 4]
mov r9d, dword ptr [r8 + 4]
mov r9, qword ptr [r8 + 4]
mov byte ptr [r9 - 4], r8b
mov byte ptr [r9 + 4], r8b
mov word ptr [r9 + 4], r8w
mov dword ptr [r9 + 4], r8d
mov qword ptr [r9 + 4], r8
movzx r9w, r8b
movzx r9w, byte ptr [r8 + 4]
movzx r9d, r8b
movzx r9d, r8w
movzx r9d, byte ptr [r8 + 4]
movzx r9d, word ptr [r8 + 4]
movzx r9, r8b
movzx r9, r8w
movzx r9, byte ptr [r8 + 4]
movzx r9, word ptr [r8 + 4]
; Source: r8, target: r10
mov r10b, 1
mov r10w, 1
mov r10d, 1
mov r10, 1
mov r10b, r8b
mov r10w, r8w
mov r10d, r8d
mov r10, r8
mov r10b, byte ptr [r8 - 4]
mov r10b, byte ptr [r8 + 4]
mov r10w, word ptr [r8 + 4]
mov r10d, dword ptr [r8 + 4]
mov r10, qword ptr [r8 + 4]
mov byte ptr [r10 - 4], r8b
mov byte ptr [r10 + 4], r8b
mov word ptr [r10 + 4], r8w
mov dword ptr [r10 + 4], r8d
mov qword ptr [r10 + 4], r8
movzx r10w, r8b
movzx r10w, byte ptr [r8 + 4]
movzx r10d, r8b
movzx r10d, r8w
movzx r10d, byte ptr [r8 + 4]
movzx r10d, word ptr [r8 + 4]
movzx r10, r8b
movzx r10, r8w
movzx r10, byte ptr [r8 + 4]
movzx r10, word ptr [r8 + 4]
; Source: r8, target: r11
mov r11b, 1
mov r11w, 1
mov r11d, 1
mov r11, 1
mov r11b, r8b
mov r11w, r8w
mov r11d, r8d
mov r11, r8
mov r11b, byte ptr [r8 - 4]
mov r11b, byte ptr [r8 + 4]
mov r11w, word ptr [r8 + 4]
mov r11d, dword ptr [r8 + 4]
mov r11, qword ptr [r8 + 4]
mov byte ptr [r11 - 4], r8b
mov byte ptr [r11 + 4], r8b
mov word ptr [r11 + 4], r8w
mov dword ptr [r11 + 4], r8d
mov qword ptr [r11 + 4], r8
movzx r11w, r8b
movzx r11w, byte ptr [r8 + 4]
movzx r11d, r8b
movzx r11d, r8w
movzx r11d, byte ptr [r8 + 4]
movzx r11d, word ptr [r8 + 4]
movzx r11, r8b
movzx r11, r8w
movzx r11, byte ptr [r8 + 4]
movzx r11, word ptr [r8 + 4]
; Source: r8, target: r12
mov r12b, 1
mov r12w, 1
mov r12d, 1
mov r12, 1
mov r12b, r8b
mov r12w, r8w
mov r12d, r8d
mov r12, r8
mov r12b, byte ptr [r8 - 4]
mov r12b, byte ptr [r8 + 4]
mov r12w, word ptr [r8 + 4]
mov r12d, dword ptr [r8 + 4]
mov r12, qword ptr [r8 + 4]
mov byte ptr [r12 - 4], r8b
mov byte ptr [r12 + 4], r8b
mov word ptr [r12 + 4], r8w
mov dword ptr [r12 + 4], r8d
mov qword ptr [r12 + 4], r8
movzx r12w, r8b
movzx r12w, byte ptr [r8 + 4]
movzx r12d, r8b
movzx r12d, r8w
movzx r12d, byte ptr [r8 + 4]
movzx r12d, word ptr [r8 + 4]
movzx r12, r8b
movzx r12, r8w
movzx r12, byte ptr [r8 + 4]
movzx r12, word ptr [r8 + 4]
; Source: r8, target: r13
mov r13b, 1
mov r13w, 1
mov r13d, 1
mov r13, 1
mov r13b, r8b
mov r13w, r8w
mov r13d, r8d
mov r13, r8
mov r13b, byte ptr [r8 - 4]
mov r13b, byte ptr [r8 + 4]
mov r13w, word ptr [r8 + 4]
mov r13d, dword ptr [r8 + 4]
mov r13, qword ptr [r8 + 4]
mov byte ptr [r13 - 4], r8b
mov byte ptr [r13 + 4], r8b
mov word ptr [r13 + 4], r8w
mov dword ptr [r13 + 4], r8d
mov qword ptr [r13 + 4], r8
movzx r13w, r8b
movzx r13w, byte ptr [r8 + 4]
movzx r13d, r8b
movzx r13d, r8w
movzx r13d, byte ptr [r8 + 4]
movzx r13d, word ptr [r8 + 4]
movzx r13, r8b
movzx r13, r8w
movzx r13, byte ptr [r8 + 4]
movzx r13, word ptr [r8 + 4]
; Source: r8, target: r14
mov r14b, 1
mov r14w, 1
mov r14d, 1
mov r14, 1
mov r14b, r8b
mov r14w, r8w
mov r14d, r8d
mov r14, r8
mov r14b, byte ptr [r8 - 4]
mov r14b, byte ptr [r8 + 4]
mov r14w, word ptr [r8 + 4]
mov r14d, dword ptr [r8 + 4]
mov r14, qword ptr [r8 + 4]
mov byte ptr [r14 - 4], r8b
mov byte ptr [r14 + 4], r8b
mov word ptr [r14 + 4], r8w
mov dword ptr [r14 + 4], r8d
mov qword ptr [r14 + 4], r8
movzx r14w, r8b
movzx r14w, byte ptr [r8 + 4]
movzx r14d, r8b
movzx r14d, r8w
movzx r14d, byte ptr [r8 + 4]
movzx r14d, word ptr [r8 + 4]
movzx r14, r8b
movzx r14, r8w
movzx r14, byte ptr [r8 + 4]
movzx r14, word ptr [r8 + 4]
; Source: r8, target: r15
mov r15b, 1
mov r15w, 1
mov r15d, 1
mov r15, 1
mov r15b, r8b
mov r15w, r8w
mov r15d, r8d
mov r15, r8
mov r15b, byte ptr [r8 - 4]
mov r15b, byte ptr [r8 + 4]
mov r15w, word ptr [r8 + 4]
mov r15d, dword ptr [r8 + 4]
mov r15, qword ptr [r8 + 4]
mov byte ptr [r15 - 4], r8b
mov byte ptr [r15 + 4], r8b
mov word ptr [r15 + 4], r8w
mov dword ptr [r15 + 4], r8d
mov qword ptr [r15 + 4], r8
movzx r15w, r8b
movzx r15w, byte ptr [r8 + 4]
movzx r15d, r8b
movzx r15d, r8w
movzx r15d, byte ptr [r8 + 4]
movzx r15d, word ptr [r8 + 4]
movzx r15, r8b
movzx r15, r8w
movzx r15, byte ptr [r8 + 4]
movzx r15, word ptr [r8 + 4]
; Source: r9, target: rax
mov al, 1
mov ax, 1
mov eax, 1
mov rax, 1
mov al, r9b
mov ax, r9w
mov eax, r9d
mov rax, r9
mov al, byte ptr [r9 - 4]
mov al, byte ptr [r9 + 4]
mov ax, word ptr [r9 + 4]
mov eax, dword ptr [r9 + 4]
mov rax, qword ptr [r9 + 4]
mov byte ptr [rax - 4], r9b
mov byte ptr [rax + 4], r9b
mov word ptr [rax + 4], r9w
mov dword ptr [rax + 4], r9d
mov qword ptr [rax + 4], r9
movzx ax, r9b
movzx ax, byte ptr [r9 + 4]
movzx eax, r9b
movzx eax, r9w
movzx eax, byte ptr [r9 + 4]
movzx eax, word ptr [r9 + 4]
movzx rax, r9b
movzx rax, r9w
movzx rax, byte ptr [r9 + 4]
movzx rax, word ptr [r9 + 4]
; Source: r9, target: rcx
mov cl, 1
mov cx, 1
mov ecx, 1
mov rcx, 1
mov cl, r9b
mov cx, r9w
mov ecx, r9d
mov rcx, r9
mov cl, byte ptr [r9 - 4]
mov cl, byte ptr [r9 + 4]
mov cx, word ptr [r9 + 4]
mov ecx, dword ptr [r9 + 4]
mov rcx, qword ptr [r9 + 4]
mov byte ptr [rcx - 4], r9b
mov byte ptr [rcx + 4], r9b
mov word ptr [rcx + 4], r9w
mov dword ptr [rcx + 4], r9d
mov qword ptr [rcx + 4], r9
movzx cx, r9b
movzx cx, byte ptr [r9 + 4]
movzx ecx, r9b
movzx ecx, r9w
movzx ecx, byte ptr [r9 + 4]
movzx ecx, word ptr [r9 + 4]
movzx rcx, r9b
movzx rcx, r9w
movzx rcx, byte ptr [r9 + 4]
movzx rcx, word ptr [r9 + 4]
; Source: r9, target: rdx
mov dl, 1
mov dx, 1
mov edx, 1
mov rdx, 1
mov dl, r9b
mov dx, r9w
mov edx, r9d
mov rdx, r9
mov dl, byte ptr [r9 - 4]
mov dl, byte ptr [r9 + 4]
mov dx, word ptr [r9 + 4]
mov edx, dword ptr [r9 + 4]
mov rdx, qword ptr [r9 + 4]
mov byte ptr [rdx - 4], r9b
mov byte ptr [rdx + 4], r9b
mov word ptr [rdx + 4], r9w
mov dword ptr [rdx + 4], r9d
mov qword ptr [rdx + 4], r9
movzx dx, r9b
movzx dx, byte ptr [r9 + 4]
movzx edx, r9b
movzx edx, r9w
movzx edx, byte ptr [r9 + 4]
movzx edx, word ptr [r9 + 4]
movzx rdx, r9b
movzx rdx, r9w
movzx rdx, byte ptr [r9 + 4]
movzx rdx, word ptr [r9 + 4]
; Source: r9, target: rbx
mov bl, 1
mov bx, 1
mov ebx, 1
mov rbx, 1
mov bl, r9b
mov bx, r9w
mov ebx, r9d
mov rbx, r9
mov bl, byte ptr [r9 - 4]
mov bl, byte ptr [r9 + 4]
mov bx, word ptr [r9 + 4]
mov ebx, dword ptr [r9 + 4]
mov rbx, qword ptr [r9 + 4]
mov byte ptr [rbx - 4], r9b
mov byte ptr [rbx + 4], r9b
mov word ptr [rbx + 4], r9w
mov dword ptr [rbx + 4], r9d
mov qword ptr [rbx + 4], r9
movzx bx, r9b
movzx bx, byte ptr [r9 + 4]
movzx ebx, r9b
movzx ebx, r9w
movzx ebx, byte ptr [r9 + 4]
movzx ebx, word ptr [r9 + 4]
movzx rbx, r9b
movzx rbx, r9w
movzx rbx, byte ptr [r9 + 4]
movzx rbx, word ptr [r9 + 4]
; Source: r9, target: rsp
mov spl, 1
mov sp, 1
mov esp, 1
mov rsp, 1
mov spl, r9b
mov sp, r9w
mov esp, r9d
mov rsp, r9
mov spl, byte ptr [r9 - 4]
mov spl, byte ptr [r9 + 4]
mov sp, word ptr [r9 + 4]
mov esp, dword ptr [r9 + 4]
mov rsp, qword ptr [r9 + 4]
mov byte ptr [rsp - 4], r9b
mov byte ptr [rsp + 4], r9b
mov word ptr [rsp + 4], r9w
mov dword ptr [rsp + 4], r9d
mov qword ptr [rsp + 4], r9
movzx sp, r9b
movzx sp, byte ptr [r9 + 4]
movzx esp, r9b
movzx esp, r9w
movzx esp, byte ptr [r9 + 4]
movzx esp, word ptr [r9 + 4]
movzx rsp, r9b
movzx rsp, r9w
movzx rsp, byte ptr [r9 + 4]
movzx rsp, word ptr [r9 + 4]
; Source: r9, target: rbp
mov bpl, 1
mov bp, 1
mov ebp, 1
mov rbp, 1
mov bpl, r9b
mov bp, r9w
mov ebp, r9d
mov rbp, r9
mov bpl, byte ptr [r9 - 4]
mov bpl, byte ptr [r9 + 4]
mov bp, word ptr [r9 + 4]
mov ebp, dword ptr [r9 + 4]
mov rbp, qword ptr [r9 + 4]
mov byte ptr [rbp - 4], r9b
mov byte ptr [rbp + 4], r9b
mov word ptr [rbp + 4], r9w
mov dword ptr [rbp + 4], r9d
mov qword ptr [rbp + 4], r9
movzx bp, r9b
movzx bp, byte ptr [r9 + 4]
movzx ebp, r9b
movzx ebp, r9w
movzx ebp, byte ptr [r9 + 4]
movzx ebp, word ptr [r9 + 4]
movzx rbp, r9b
movzx rbp, r9w
movzx rbp, byte ptr [r9 + 4]
movzx rbp, word ptr [r9 + 4]
; Source: r9, target: rsi
mov dil, 1
mov si, 1
mov esi, 1
mov rsi, 1
mov dil, r9b
mov si, r9w
mov esi, r9d
mov rsi, r9
mov dil, byte ptr [r9 - 4]
mov dil, byte ptr [r9 + 4]
mov si, word ptr [r9 + 4]
mov esi, dword ptr [r9 + 4]
mov rsi, qword ptr [r9 + 4]
mov byte ptr [rsi - 4], r9b
mov byte ptr [rsi + 4], r9b
mov word ptr [rsi + 4], r9w
mov dword ptr [rsi + 4], r9d
mov qword ptr [rsi + 4], r9
movzx si, r9b
movzx si, byte ptr [r9 + 4]
movzx esi, r9b
movzx esi, r9w
movzx esi, byte ptr [r9 + 4]
movzx esi, word ptr [r9 + 4]
movzx rsi, r9b
movzx rsi, r9w
movzx rsi, byte ptr [r9 + 4]
movzx rsi, word ptr [r9 + 4]
; Source: r9, target: rdi
mov sil, 1
mov di, 1
mov edi, 1
mov rdi, 1
mov sil, r9b
mov di, r9w
mov edi, r9d
mov rdi, r9
mov sil, byte ptr [r9 - 4]
mov sil, byte ptr [r9 + 4]
mov di, word ptr [r9 + 4]
mov edi, dword ptr [r9 + 4]
mov rdi, qword ptr [r9 + 4]
mov byte ptr [rdi - 4], r9b
mov byte ptr [rdi + 4], r9b
mov word ptr [rdi + 4], r9w
mov dword ptr [rdi + 4], r9d
mov qword ptr [rdi + 4], r9
movzx di, r9b
movzx di, byte ptr [r9 + 4]
movzx edi, r9b
movzx edi, r9w
movzx edi, byte ptr [r9 + 4]
movzx edi, word ptr [r9 + 4]
movzx rdi, r9b
movzx rdi, r9w
movzx rdi, byte ptr [r9 + 4]
movzx rdi, word ptr [r9 + 4]
; Source: r9, target: r8
mov r8b, 1
mov r8w, 1
mov r8d, 1
mov r8, 1
mov r8b, r9b
mov r8w, r9w
mov r8d, r9d
mov r8, r9
mov r8b, byte ptr [r9 - 4]
mov r8b, byte ptr [r9 + 4]
mov r8w, word ptr [r9 + 4]
mov r8d, dword ptr [r9 + 4]
mov r8, qword ptr [r9 + 4]
mov byte ptr [r8 - 4], r9b
mov byte ptr [r8 + 4], r9b
mov word ptr [r8 + 4], r9w
mov dword ptr [r8 + 4], r9d
mov qword ptr [r8 + 4], r9
movzx r8w, r9b
movzx r8w, byte ptr [r9 + 4]
movzx r8d, r9b
movzx r8d, r9w
movzx r8d, byte ptr [r9 + 4]
movzx r8d, word ptr [r9 + 4]
movzx r8, r9b
movzx r8, r9w
movzx r8, byte ptr [r9 + 4]
movzx r8, word ptr [r9 + 4]
; Source: r9, target: r9
mov r9b, 1
mov r9w, 1
mov r9d, 1
mov r9, 1
mov r9b, r9b
mov r9w, r9w
mov r9d, r9d
mov r9, r9
mov r9b, byte ptr [r9 - 4]
mov r9b, byte ptr [r9 + 4]
mov r9w, word ptr [r9 + 4]
mov r9d, dword ptr [r9 + 4]
mov r9, qword ptr [r9 + 4]
mov byte ptr [r9 - 4], r9b
mov byte ptr [r9 + 4], r9b
mov word ptr [r9 + 4], r9w
mov dword ptr [r9 + 4], r9d
mov qword ptr [r9 + 4], r9
movzx r9w, r9b
movzx r9w, byte ptr [r9 + 4]
movzx r9d, r9b
movzx r9d, r9w
movzx r9d, byte ptr [r9 + 4]
movzx r9d, word ptr [r9 + 4]
movzx r9, r9b
movzx r9, r9w
movzx r9, byte ptr [r9 + 4]
movzx r9, word ptr [r9 + 4]
; Source: r9, target: r10
mov r10b, 1
mov r10w, 1
mov r10d, 1
mov r10, 1
mov r10b, r9b
mov r10w, r9w
mov r10d, r9d
mov r10, r9
mov r10b, byte ptr [r9 - 4]
mov r10b, byte ptr [r9 + 4]
mov r10w, word ptr [r9 + 4]
mov r10d, dword ptr [r9 + 4]
mov r10, qword ptr [r9 + 4]
mov byte ptr [r10 - 4], r9b
mov byte ptr [r10 + 4], r9b
mov word ptr [r10 + 4], r9w
mov dword ptr [r10 + 4], r9d
mov qword ptr [r10 + 4], r9
movzx r10w, r9b
movzx r10w, byte ptr [r9 + 4]
movzx r10d, r9b
movzx r10d, r9w
movzx r10d, byte ptr [r9 + 4]
movzx r10d, word ptr [r9 + 4]
movzx r10, r9b
movzx r10, r9w
movzx r10, byte ptr [r9 + 4]
movzx r10, word ptr [r9 + 4]
; Source: r9, target: r11
mov r11b, 1
mov r11w, 1
mov r11d, 1
mov r11, 1
mov r11b, r9b
mov r11w, r9w
mov r11d, r9d
mov r11, r9
mov r11b, byte ptr [r9 - 4]
mov r11b, byte ptr [r9 + 4]
mov r11w, word ptr [r9 + 4]
mov r11d, dword ptr [r9 + 4]
mov r11, qword ptr [r9 + 4]
mov byte ptr [r11 - 4], r9b
mov byte ptr [r11 + 4], r9b
mov word ptr [r11 + 4], r9w
mov dword ptr [r11 + 4], r9d
mov qword ptr [r11 + 4], r9
movzx r11w, r9b
movzx r11w, byte ptr [r9 + 4]
movzx r11d, r9b
movzx r11d, r9w
movzx r11d, byte ptr [r9 + 4]
movzx r11d, word ptr [r9 + 4]
movzx r11, r9b
movzx r11, r9w
movzx r11, byte ptr [r9 + 4]
movzx r11, word ptr [r9 + 4]
; Source: r9, target: r12
mov r12b, 1
mov r12w, 1
mov r12d, 1
mov r12, 1
mov r12b, r9b
mov r12w, r9w
mov r12d, r9d
mov r12, r9
mov r12b, byte ptr [r9 - 4]
mov r12b, byte ptr [r9 + 4]
mov r12w, word ptr [r9 + 4]
mov r12d, dword ptr [r9 + 4]
mov r12, qword ptr [r9 + 4]
mov byte ptr [r12 - 4], r9b
mov byte ptr [r12 + 4], r9b
mov word ptr [r12 + 4], r9w
mov dword ptr [r12 + 4], r9d
mov qword ptr [r12 + 4], r9
movzx r12w, r9b
movzx r12w, byte ptr [r9 + 4]
movzx r12d, r9b
movzx r12d, r9w
movzx r12d, byte ptr [r9 + 4]
movzx r12d, word ptr [r9 + 4]
movzx r12, r9b
movzx r12, r9w
movzx r12, byte ptr [r9 + 4]
movzx r12, word ptr [r9 + 4]
; Source: r9, target: r13
mov r13b, 1
mov r13w, 1
mov r13d, 1
mov r13, 1
mov r13b, r9b
mov r13w, r9w
mov r13d, r9d
mov r13, r9
mov r13b, byte ptr [r9 - 4]
mov r13b, byte ptr [r9 + 4]
mov r13w, word ptr [r9 + 4]
mov r13d, dword ptr [r9 + 4]
mov r13, qword ptr [r9 + 4]
mov byte ptr [r13 - 4], r9b
mov byte ptr [r13 + 4], r9b
mov word ptr [r13 + 4], r9w
mov dword ptr [r13 + 4], r9d
mov qword ptr [r13 + 4], r9
movzx r13w, r9b
movzx r13w, byte ptr [r9 + 4]
movzx r13d, r9b
movzx r13d, r9w
movzx r13d, byte ptr [r9 + 4]
movzx r13d, word ptr [r9 + 4]
movzx r13, r9b
movzx r13, r9w
movzx r13, byte ptr [r9 + 4]
movzx r13, word ptr [r9 + 4]
; Source: r9, target: r14
mov r14b, 1
mov r14w, 1
mov r14d, 1
mov r14, 1
mov r14b, r9b
mov r14w, r9w
mov r14d, r9d
mov r14, r9
mov r14b, byte ptr [r9 - 4]
mov r14b, byte ptr [r9 + 4]
mov r14w, word ptr [r9 + 4]
mov r14d, dword ptr [r9 + 4]
mov r14, qword ptr [r9 + 4]
mov byte ptr [r14 - 4], r9b
mov byte ptr [r14 + 4], r9b
mov word ptr [r14 + 4], r9w
mov dword ptr [r14 + 4], r9d
mov qword ptr [r14 + 4], r9
movzx r14w, r9b
movzx r14w, byte ptr [r9 + 4]
movzx r14d, r9b
movzx r14d, r9w
movzx r14d, byte ptr [r9 + 4]
movzx r14d, word ptr [r9 + 4]
movzx r14, r9b
movzx r14, r9w
movzx r14, byte ptr [r9 + 4]
movzx r14, word ptr [r9 + 4]
; Source: r9, target: r15
mov r15b, 1
mov r15w, 1
mov r15d, 1
mov r15, 1
mov r15b, r9b
mov r15w, r9w
mov r15d, r9d
mov r15, r9
mov r15b, byte ptr [r9 - 4]
mov r15b, byte ptr [r9 + 4]
mov r15w, word ptr [r9 + 4]
mov r15d, dword ptr [r9 + 4]
mov r15, qword ptr [r9 + 4]
mov byte ptr [r15 - 4], r9b
mov byte ptr [r15 + 4], r9b
mov word ptr [r15 + 4], r9w
mov dword ptr [r15 + 4], r9d
mov qword ptr [r15 + 4], r9
movzx r15w, r9b
movzx r15w, byte ptr [r9 + 4]
movzx r15d, r9b
movzx r15d, r9w
movzx r15d, byte ptr [r9 + 4]
movzx r15d, word ptr [r9 + 4]
movzx r15, r9b
movzx r15, r9w
movzx r15, byte ptr [r9 + 4]
movzx r15, word ptr [r9 + 4]
; Source: r10, target: rax
mov al, 1
mov ax, 1
mov eax, 1
mov rax, 1
mov al, r10b
mov ax, r10w
mov eax, r10d
mov rax, r10
mov al, byte ptr [r10 - 4]
mov al, byte ptr [r10 + 4]
mov ax, word ptr [r10 + 4]
mov eax, dword ptr [r10 + 4]
mov rax, qword ptr [r10 + 4]
mov byte ptr [rax - 4], r10b
mov byte ptr [rax + 4], r10b
mov word ptr [rax + 4], r10w
mov dword ptr [rax + 4], r10d
mov qword ptr [rax + 4], r10
movzx ax, r10b
movzx ax, byte ptr [r10 + 4]
movzx eax, r10b
movzx eax, r10w
movzx eax, byte ptr [r10 + 4]
movzx eax, word ptr [r10 + 4]
movzx rax, r10b
movzx rax, r10w
movzx rax, byte ptr [r10 + 4]
movzx rax, word ptr [r10 + 4]
; Source: r10, target: rcx
mov cl, 1
mov cx, 1
mov ecx, 1
mov rcx, 1
mov cl, r10b
mov cx, r10w
mov ecx, r10d
mov rcx, r10
mov cl, byte ptr [r10 - 4]
mov cl, byte ptr [r10 + 4]
mov cx, word ptr [r10 + 4]
mov ecx, dword ptr [r10 + 4]
mov rcx, qword ptr [r10 + 4]
mov byte ptr [rcx - 4], r10b
mov byte ptr [rcx + 4], r10b
mov word ptr [rcx + 4], r10w
mov dword ptr [rcx + 4], r10d
mov qword ptr [rcx + 4], r10
movzx cx, r10b
movzx cx, byte ptr [r10 + 4]
movzx ecx, r10b
movzx ecx, r10w
movzx ecx, byte ptr [r10 + 4]
movzx ecx, word ptr [r10 + 4]
movzx rcx, r10b
movzx rcx, r10w
movzx rcx, byte ptr [r10 + 4]
movzx rcx, word ptr [r10 + 4]
; Source: r10, target: rdx
mov dl, 1
mov dx, 1
mov edx, 1
mov rdx, 1
mov dl, r10b
mov dx, r10w
mov edx, r10d
mov rdx, r10
mov dl, byte ptr [r10 - 4]
mov dl, byte ptr [r10 + 4]
mov dx, word ptr [r10 + 4]
mov edx, dword ptr [r10 + 4]
mov rdx, qword ptr [r10 + 4]
mov byte ptr [rdx - 4], r10b
mov byte ptr [rdx + 4], r10b
mov word ptr [rdx + 4], r10w
mov dword ptr [rdx + 4], r10d
mov qword ptr [rdx + 4], r10
movzx dx, r10b
movzx dx, byte ptr [r10 + 4]
movzx edx, r10b
movzx edx, r10w
movzx edx, byte ptr [r10 + 4]
movzx edx, word ptr [r10 + 4]
movzx rdx, r10b
movzx rdx, r10w
movzx rdx, byte ptr [r10 + 4]
movzx rdx, word ptr [r10 + 4]
; Source: r10, target: rbx
mov bl, 1
mov bx, 1
mov ebx, 1
mov rbx, 1
mov bl, r10b
mov bx, r10w
mov ebx, r10d
mov rbx, r10
mov bl, byte ptr [r10 - 4]
mov bl, byte ptr [r10 + 4]
mov bx, word ptr [r10 + 4]
mov ebx, dword ptr [r10 + 4]
mov rbx, qword ptr [r10 + 4]
mov byte ptr [rbx - 4], r10b
mov byte ptr [rbx + 4], r10b
mov word ptr [rbx + 4], r10w
mov dword ptr [rbx + 4], r10d
mov qword ptr [rbx + 4], r10
movzx bx, r10b
movzx bx, byte ptr [r10 + 4]
movzx ebx, r10b
movzx ebx, r10w
movzx ebx, byte ptr [r10 + 4]
movzx ebx, word ptr [r10 + 4]
movzx rbx, r10b
movzx rbx, r10w
movzx rbx, byte ptr [r10 + 4]
movzx rbx, word ptr [r10 + 4]
; Source: r10, target: rsp
mov spl, 1
mov sp, 1
mov esp, 1
mov rsp, 1
mov spl, r10b
mov sp, r10w
mov esp, r10d
mov rsp, r10
mov spl, byte ptr [r10 - 4]
mov spl, byte ptr [r10 + 4]
mov sp, word ptr [r10 + 4]
mov esp, dword ptr [r10 + 4]
mov rsp, qword ptr [r10 + 4]
mov byte ptr [rsp - 4], r10b
mov byte ptr [rsp + 4], r10b
mov word ptr [rsp + 4], r10w
mov dword ptr [rsp + 4], r10d
mov qword ptr [rsp + 4], r10
movzx sp, r10b
movzx sp, byte ptr [r10 + 4]
movzx esp, r10b
movzx esp, r10w
movzx esp, byte ptr [r10 + 4]
movzx esp, word ptr [r10 + 4]
movzx rsp, r10b
movzx rsp, r10w
movzx rsp, byte ptr [r10 + 4]
movzx rsp, word ptr [r10 + 4]
; Source: r10, target: rbp
mov bpl, 1
mov bp, 1
mov ebp, 1
mov rbp, 1
mov bpl, r10b
mov bp, r10w
mov ebp, r10d
mov rbp, r10
mov bpl, byte ptr [r10 - 4]
mov bpl, byte ptr [r10 + 4]
mov bp, word ptr [r10 + 4]
mov ebp, dword ptr [r10 + 4]
mov rbp, qword ptr [r10 + 4]
mov byte ptr [rbp - 4], r10b
mov byte ptr [rbp + 4], r10b
mov word ptr [rbp + 4], r10w
mov dword ptr [rbp + 4], r10d
mov qword ptr [rbp + 4], r10
movzx bp, r10b
movzx bp, byte ptr [r10 + 4]
movzx ebp, r10b
movzx ebp, r10w
movzx ebp, byte ptr [r10 + 4]
movzx ebp, word ptr [r10 + 4]
movzx rbp, r10b
movzx rbp, r10w
movzx rbp, byte ptr [r10 + 4]
movzx rbp, word ptr [r10 + 4]
; Source: r10, target: rsi
mov dil, 1
mov si, 1
mov esi, 1
mov rsi, 1
mov dil, r10b
mov si, r10w
mov esi, r10d
mov rsi, r10
mov dil, byte ptr [r10 - 4]
mov dil, byte ptr [r10 + 4]
mov si, word ptr [r10 + 4]
mov esi, dword ptr [r10 + 4]
mov rsi, qword ptr [r10 + 4]
mov byte ptr [rsi - 4], r10b
mov byte ptr [rsi + 4], r10b
mov word ptr [rsi + 4], r10w
mov dword ptr [rsi + 4], r10d
mov qword ptr [rsi + 4], r10
movzx si, r10b
movzx si, byte ptr [r10 + 4]
movzx esi, r10b
movzx esi, r10w
movzx esi, byte ptr [r10 + 4]
movzx esi, word ptr [r10 + 4]
movzx rsi, r10b
movzx rsi, r10w
movzx rsi, byte ptr [r10 + 4]
movzx rsi, word ptr [r10 + 4]
; Source: r10, target: rdi
mov sil, 1
mov di, 1
mov edi, 1
mov rdi, 1
mov sil, r10b
mov di, r10w
mov edi, r10d
mov rdi, r10
mov sil, byte ptr [r10 - 4]
mov sil, byte ptr [r10 + 4]
mov di, word ptr [r10 + 4]
mov edi, dword ptr [r10 + 4]
mov rdi, qword ptr [r10 + 4]
mov byte ptr [rdi - 4], r10b
mov byte ptr [rdi + 4], r10b
mov word ptr [rdi + 4], r10w
mov dword ptr [rdi + 4], r10d
mov qword ptr [rdi + 4], r10
movzx di, r10b
movzx di, byte ptr [r10 + 4]
movzx edi, r10b
movzx edi, r10w
movzx edi, byte ptr [r10 + 4]
movzx edi, word ptr [r10 + 4]
movzx rdi, r10b
movzx rdi, r10w
movzx rdi, byte ptr [r10 + 4]
movzx rdi, word ptr [r10 + 4]
; Source: r10, target: r8
mov r8b, 1
mov r8w, 1
mov r8d, 1
mov r8, 1
mov r8b, r10b
mov r8w, r10w
mov r8d, r10d
mov r8, r10
mov r8b, byte ptr [r10 - 4]
mov r8b, byte ptr [r10 + 4]
mov r8w, word ptr [r10 + 4]
mov r8d, dword ptr [r10 + 4]
mov r8, qword ptr [r10 + 4]
mov byte ptr [r8 - 4], r10b
mov byte ptr [r8 + 4], r10b
mov word ptr [r8 + 4], r10w
mov dword ptr [r8 + 4], r10d
mov qword ptr [r8 + 4], r10
movzx r8w, r10b
movzx r8w, byte ptr [r10 + 4]
movzx r8d, r10b
movzx r8d, r10w
movzx r8d, byte ptr [r10 + 4]
movzx r8d, word ptr [r10 + 4]
movzx r8, r10b
movzx r8, r10w
movzx r8, byte ptr [r10 + 4]
movzx r8, word ptr [r10 + 4]
; Source: r10, target: r9
mov r9b, 1
mov r9w, 1
mov r9d, 1
mov r9, 1
mov r9b, r10b
mov r9w, r10w
mov r9d, r10d
mov r9, r10
mov r9b, byte ptr [r10 - 4]
mov r9b, byte ptr [r10 + 4]
mov r9w, word ptr [r10 + 4]
mov r9d, dword ptr [r10 + 4]
mov r9, qword ptr [r10 + 4]
mov byte ptr [r9 - 4], r10b
mov byte ptr [r9 + 4], r10b
mov word ptr [r9 + 4], r10w
mov dword ptr [r9 + 4], r10d
mov qword ptr [r9 + 4], r10
movzx r9w, r10b
movzx r9w, byte ptr [r10 + 4]
movzx r9d, r10b
movzx r9d, r10w
movzx r9d, byte ptr [r10 + 4]
movzx r9d, word ptr [r10 + 4]
movzx r9, r10b
movzx r9, r10w
movzx r9, byte ptr [r10 + 4]
movzx r9, word ptr [r10 + 4]
; Source: r10, target: r10
mov r10b, 1
mov r10w, 1
mov r10d, 1
mov r10, 1
mov r10b, r10b
mov r10w, r10w
mov r10d, r10d
mov r10, r10
mov r10b, byte ptr [r10 - 4]
mov r10b, byte ptr [r10 + 4]
mov r10w, word ptr [r10 + 4]
mov r10d, dword ptr [r10 + 4]
mov r10, qword ptr [r10 + 4]
mov byte ptr [r10 - 4], r10b
mov byte ptr [r10 + 4], r10b
mov word ptr [r10 + 4], r10w
mov dword ptr [r10 + 4], r10d
mov qword ptr [r10 + 4], r10
movzx r10w, r10b
movzx r10w, byte ptr [r10 + 4]
movzx r10d, r10b
movzx r10d, r10w
movzx r10d, byte ptr [r10 + 4]
movzx r10d, word ptr [r10 + 4]
movzx r10, r10b
movzx r10, r10w
movzx r10, byte ptr [r10 + 4]
movzx r10, word ptr [r10 + 4]
; Source: r10, target: r11
mov r11b, 1
mov r11w, 1
mov r11d, 1
mov r11, 1
mov r11b, r10b
mov r11w, r10w
mov r11d, r10d
mov r11, r10
mov r11b, byte ptr [r10 - 4]
mov r11b, byte ptr [r10 + 4]
mov r11w, word ptr [r10 + 4]
mov r11d, dword ptr [r10 + 4]
mov r11, qword ptr [r10 + 4]
mov byte ptr [r11 - 4], r10b
mov byte ptr [r11 + 4], r10b
mov word ptr [r11 + 4], r10w
mov dword ptr [r11 + 4], r10d
mov qword ptr [r11 + 4], r10
movzx r11w, r10b
movzx r11w, byte ptr [r10 + 4]
movzx r11d, r10b
movzx r11d, r10w
movzx r11d, byte ptr [r10 + 4]
movzx r11d, word ptr [r10 + 4]
movzx r11, r10b
movzx r11, r10w
movzx r11, byte ptr [r10 + 4]
movzx r11, word ptr [r10 + 4]
; Source: r10, target: r12
mov r12b, 1
mov r12w, 1
mov r12d, 1
mov r12, 1
mov r12b, r10b
mov r12w, r10w
mov r12d, r10d
mov r12, r10
mov r12b, byte ptr [r10 - 4]
mov r12b, byte ptr [r10 + 4]
mov r12w, word ptr [r10 + 4]
mov r12d, dword ptr [r10 + 4]
mov r12, qword ptr [r10 + 4]
mov byte ptr [r12 - 4], r10b
mov byte ptr [r12 + 4], r10b
mov word ptr [r12 + 4], r10w
mov dword ptr [r12 + 4], r10d
mov qword ptr [r12 + 4], r10
movzx r12w, r10b
movzx r12w, byte ptr [r10 + 4]
movzx r12d, r10b
movzx r12d, r10w
movzx r12d, byte ptr [r10 + 4]
movzx r12d, word ptr [r10 + 4]
movzx r12, r10b
movzx r12, r10w
movzx r12, byte ptr [r10 + 4]
movzx r12, word ptr [r10 + 4]
; Source: r10, target: r13
mov r13b, 1
mov r13w, 1
mov r13d, 1
mov r13, 1
mov r13b, r10b
mov r13w, r10w
mov r13d, r10d
mov r13, r10
mov r13b, byte ptr [r10 - 4]
mov r13b, byte ptr [r10 + 4]
mov r13w, word ptr [r10 + 4]
mov r13d, dword ptr [r10 + 4]
mov r13, qword ptr [r10 + 4]
mov byte ptr [r13 - 4], r10b
mov byte ptr [r13 + 4], r10b
mov word ptr [r13 + 4], r10w
mov dword ptr [r13 + 4], r10d
mov qword ptr [r13 + 4], r10
movzx r13w, r10b
movzx r13w, byte ptr [r10 + 4]
movzx r13d, r10b
movzx r13d, r10w
movzx r13d, byte ptr [r10 + 4]
movzx r13d, word ptr [r10 + 4]
movzx r13, r10b
movzx r13, r10w
movzx r13, byte ptr [r10 + 4]
movzx r13, word ptr [r10 + 4]
; Source: r10, target: r14
mov r14b, 1
mov r14w, 1
mov r14d, 1
mov r14, 1
mov r14b, r10b
mov r14w, r10w
mov r14d, r10d
mov r14, r10
mov r14b, byte ptr [r10 - 4]
mov r14b, byte ptr [r10 + 4]
mov r14w, word ptr [r10 + 4]
mov r14d, dword ptr [r10 + 4]
mov r14, qword ptr [r10 + 4]
mov byte ptr [r14 - 4], r10b
mov byte ptr [r14 + 4], r10b
mov word ptr [r14 + 4], r10w
mov dword ptr [r14 + 4], r10d
mov qword ptr [r14 + 4], r10
movzx r14w, r10b
movzx r14w, byte ptr [r10 + 4]
movzx r14d, r10b
movzx r14d, r10w
movzx r14d, byte ptr [r10 + 4]
movzx r14d, word ptr [r10 + 4]
movzx r14, r10b
movzx r14, r10w
movzx r14, byte ptr [r10 + 4]
movzx r14, word ptr [r10 + 4]
; Source: r10, target: r15
mov r15b, 1
mov r15w, 1
mov r15d, 1
mov r15, 1
mov r15b, r10b
mov r15w, r10w
mov r15d, r10d
mov r15, r10
mov r15b, byte ptr [r10 - 4]
mov r15b, byte ptr [r10 + 4]
mov r15w, word ptr [r10 + 4]
mov r15d, dword ptr [r10 + 4]
mov r15, qword ptr [r10 + 4]
mov byte ptr [r15 - 4], r10b
mov byte ptr [r15 + 4], r10b
mov word ptr [r15 + 4], r10w
mov dword ptr [r15 + 4], r10d
mov qword ptr [r15 + 4], r10
movzx r15w, r10b
movzx r15w, byte ptr [r10 + 4]
movzx r15d, r10b
movzx r15d, r10w
movzx r15d, byte ptr [r10 + 4]
movzx r15d, word ptr [r10 + 4]
movzx r15, r10b
movzx r15, r10w
movzx r15, byte ptr [r10 + 4]
movzx r15, word ptr [r10 + 4]
; Source: r11, target: rax
mov al, 1
mov ax, 1
mov eax, 1
mov rax, 1
mov al, r11b
mov ax, r11w
mov eax, r11d
mov rax, r11
mov al, byte ptr [r11 - 4]
mov al, byte ptr [r11 + 4]
mov ax, word ptr [r11 + 4]
mov eax, dword ptr [r11 + 4]
mov rax, qword ptr [r11 + 4]
mov byte ptr [rax - 4], r11b
mov byte ptr [rax + 4], r11b
mov word ptr [rax + 4], r11w
mov dword ptr [rax + 4], r11d
mov qword ptr [rax + 4], r11
movzx ax, r11b
movzx ax, byte ptr [r11 + 4]
movzx eax, r11b
movzx eax, r11w
movzx eax, byte ptr [r11 + 4]
movzx eax, word ptr [r11 + 4]
movzx rax, r11b
movzx rax, r11w
movzx rax, byte ptr [r11 + 4]
movzx rax, word ptr [r11 + 4]
; Source: r11, target: rcx
mov cl, 1
mov cx, 1
mov ecx, 1
mov rcx, 1
mov cl, r11b
mov cx, r11w
mov ecx, r11d
mov rcx, r11
mov cl, byte ptr [r11 - 4]
mov cl, byte ptr [r11 + 4]
mov cx, word ptr [r11 + 4]
mov ecx, dword ptr [r11 + 4]
mov rcx, qword ptr [r11 + 4]
mov byte ptr [rcx - 4], r11b
mov byte ptr [rcx + 4], r11b
mov word ptr [rcx + 4], r11w
mov dword ptr [rcx + 4], r11d
mov qword ptr [rcx + 4], r11
movzx cx, r11b
movzx cx, byte ptr [r11 + 4]
movzx ecx, r11b
movzx ecx, r11w
movzx ecx, byte ptr [r11 + 4]
movzx ecx, word ptr [r11 + 4]
movzx rcx, r11b
movzx rcx, r11w
movzx rcx, byte ptr [r11 + 4]
movzx rcx, word ptr [r11 + 4]
; Source: r11, target: rdx
mov dl, 1
mov dx, 1
mov edx, 1
mov rdx, 1
mov dl, r11b
mov dx, r11w
mov edx, r11d
mov rdx, r11
mov dl, byte ptr [r11 - 4]
mov dl, byte ptr [r11 + 4]
mov dx, word ptr [r11 + 4]
mov edx, dword ptr [r11 + 4]
mov rdx, qword ptr [r11 + 4]
mov byte ptr [rdx - 4], r11b
mov byte ptr [rdx + 4], r11b
mov word ptr [rdx + 4], r11w
mov dword ptr [rdx + 4], r11d
mov qword ptr [rdx + 4], r11
movzx dx, r11b
movzx dx, byte ptr [r11 + 4]
movzx edx, r11b
movzx edx, r11w
movzx edx, byte ptr [r11 + 4]
movzx edx, word ptr [r11 + 4]
movzx rdx, r11b
movzx rdx, r11w
movzx rdx, byte ptr [r11 + 4]
movzx rdx, word ptr [r11 + 4]
; Source: r11, target: rbx
mov bl, 1
mov bx, 1
mov ebx, 1
mov rbx, 1
mov bl, r11b
mov bx, r11w
mov ebx, r11d
mov rbx, r11
mov bl, byte ptr [r11 - 4]
mov bl, byte ptr [r11 + 4]
mov bx, word ptr [r11 + 4]
mov ebx, dword ptr [r11 + 4]
mov rbx, qword ptr [r11 + 4]
mov byte ptr [rbx - 4], r11b
mov byte ptr [rbx + 4], r11b
mov word ptr [rbx + 4], r11w
mov dword ptr [rbx + 4], r11d
mov qword ptr [rbx + 4], r11
movzx bx, r11b
movzx bx, byte ptr [r11 + 4]
movzx ebx, r11b
movzx ebx, r11w
movzx ebx, byte ptr [r11 + 4]
movzx ebx, word ptr [r11 + 4]
movzx rbx, r11b
movzx rbx, r11w
movzx rbx, byte ptr [r11 + 4]
movzx rbx, word ptr [r11 + 4]
; Source: r11, target: rsp
mov spl, 1
mov sp, 1
mov esp, 1
mov rsp, 1
mov spl, r11b
mov sp, r11w
mov esp, r11d
mov rsp, r11
mov spl, byte ptr [r11 - 4]
mov spl, byte ptr [r11 + 4]
mov sp, word ptr [r11 + 4]
mov esp, dword ptr [r11 + 4]
mov rsp, qword ptr [r11 + 4]
mov byte ptr [rsp - 4], r11b
mov byte ptr [rsp + 4], r11b
mov word ptr [rsp + 4], r11w
mov dword ptr [rsp + 4], r11d
mov qword ptr [rsp + 4], r11
movzx sp, r11b
movzx sp, byte ptr [r11 + 4]
movzx esp, r11b
movzx esp, r11w
movzx esp, byte ptr [r11 + 4]
movzx esp, word ptr [r11 + 4]
movzx rsp, r11b
movzx rsp, r11w
movzx rsp, byte ptr [r11 + 4]
movzx rsp, word ptr [r11 + 4]
; Source: r11, target: rbp
mov bpl, 1
mov bp, 1
mov ebp, 1
mov rbp, 1
mov bpl, r11b
mov bp, r11w
mov ebp, r11d
mov rbp, r11
mov bpl, byte ptr [r11 - 4]
mov bpl, byte ptr [r11 + 4]
mov bp, word ptr [r11 + 4]
mov ebp, dword ptr [r11 + 4]
mov rbp, qword ptr [r11 + 4]
mov byte ptr [rbp - 4], r11b
mov byte ptr [rbp + 4], r11b
mov word ptr [rbp + 4], r11w
mov dword ptr [rbp + 4], r11d
mov qword ptr [rbp + 4], r11
movzx bp, r11b
movzx bp, byte ptr [r11 + 4]
movzx ebp, r11b
movzx ebp, r11w
movzx ebp, byte ptr [r11 + 4]
movzx ebp, word ptr [r11 + 4]
movzx rbp, r11b
movzx rbp, r11w
movzx rbp, byte ptr [r11 + 4]
movzx rbp, word ptr [r11 + 4]
; Source: r11, target: rsi
mov dil, 1
mov si, 1
mov esi, 1
mov rsi, 1
mov dil, r11b
mov si, r11w
mov esi, r11d
mov rsi, r11
mov dil, byte ptr [r11 - 4]
mov dil, byte ptr [r11 + 4]
mov si, word ptr [r11 + 4]
mov esi, dword ptr [r11 + 4]
mov rsi, qword ptr [r11 + 4]
mov byte ptr [rsi - 4], r11b
mov byte ptr [rsi + 4], r11b
mov word ptr [rsi + 4], r11w
mov dword ptr [rsi + 4], r11d
mov qword ptr [rsi + 4], r11
movzx si, r11b
movzx si, byte ptr [r11 + 4]
movzx esi, r11b
movzx esi, r11w
movzx esi, byte ptr [r11 + 4]
movzx esi, word ptr [r11 + 4]
movzx rsi, r11b
movzx rsi, r11w
movzx rsi, byte ptr [r11 + 4]
movzx rsi, word ptr [r11 + 4]
; Source: r11, target: rdi
mov sil, 1
mov di, 1
mov edi, 1
mov rdi, 1
mov sil, r11b
mov di, r11w
mov edi, r11d
mov rdi, r11
mov sil, byte ptr [r11 - 4]
mov sil, byte ptr [r11 + 4]
mov di, word ptr [r11 + 4]
mov edi, dword ptr [r11 + 4]
mov rdi, qword ptr [r11 + 4]
mov byte ptr [rdi - 4], r11b
mov byte ptr [rdi + 4], r11b
mov word ptr [rdi + 4], r11w
mov dword ptr [rdi + 4], r11d
mov qword ptr [rdi + 4], r11
movzx di, r11b
movzx di, byte ptr [r11 + 4]
movzx edi, r11b
movzx edi, r11w
movzx edi, byte ptr [r11 + 4]
movzx edi, word ptr [r11 + 4]
movzx rdi, r11b
movzx rdi, r11w
movzx rdi, byte ptr [r11 + 4]
movzx rdi, word ptr [r11 + 4]
; Source: r11, target: r8
mov r8b, 1
mov r8w, 1
mov r8d, 1
mov r8, 1
mov r8b, r11b
mov r8w, r11w
mov r8d, r11d
mov r8, r11
mov r8b, byte ptr [r11 - 4]
mov r8b, byte ptr [r11 + 4]
mov r8w, word ptr [r11 + 4]
mov r8d, dword ptr [r11 + 4]
mov r8, qword ptr [r11 + 4]
mov byte ptr [r8 - 4], r11b
mov byte ptr [r8 + 4], r11b
mov word ptr [r8 + 4], r11w
mov dword ptr [r8 + 4], r11d
mov qword ptr [r8 + 4], r11
movzx r8w, r11b
movzx r8w, byte ptr [r11 + 4]
movzx r8d, r11b
movzx r8d, r11w
movzx r8d, byte ptr [r11 + 4]
movzx r8d, word ptr [r11 + 4]
movzx r8, r11b
movzx r8, r11w
movzx r8, byte ptr [r11 + 4]
movzx r8, word ptr [r11 + 4]
; Source: r11, target: r9
mov r9b, 1
mov r9w, 1
mov r9d, 1
mov r9, 1
mov r9b, r11b
mov r9w, r11w
mov r9d, r11d
mov r9, r11
mov r9b, byte ptr [r11 - 4]
mov r9b, byte ptr [r11 + 4]
mov r9w, word ptr [r11 + 4]
mov r9d, dword ptr [r11 + 4]
mov r9, qword ptr [r11 + 4]
mov byte ptr [r9 - 4], r11b
mov byte ptr [r9 + 4], r11b
mov word ptr [r9 + 4], r11w
mov dword ptr [r9 + 4], r11d
mov qword ptr [r9 + 4], r11
movzx r9w, r11b
movzx r9w, byte ptr [r11 + 4]
movzx r9d, r11b
movzx r9d, r11w
movzx r9d, byte ptr [r11 + 4]
movzx r9d, word ptr [r11 + 4]
movzx r9, r11b
movzx r9, r11w
movzx r9, byte ptr [r11 + 4]
movzx r9, word ptr [r11 + 4]
; Source: r11, target: r10
mov r10b, 1
mov r10w, 1
mov r10d, 1
mov r10, 1
mov r10b, r11b
mov r10w, r11w
mov r10d, r11d
mov r10, r11
mov r10b, byte ptr [r11 - 4]
mov r10b, byte ptr [r11 + 4]
mov r10w, word ptr [r11 + 4]
mov r10d, dword ptr [r11 + 4]
mov r10, qword ptr [r11 + 4]
mov byte ptr [r10 - 4], r11b
mov byte ptr [r10 + 4], r11b
mov word ptr [r10 + 4], r11w
mov dword ptr [r10 + 4], r11d
mov qword ptr [r10 + 4], r11
movzx r10w, r11b
movzx r10w, byte ptr [r11 + 4]
movzx r10d, r11b
movzx r10d, r11w
movzx r10d, byte ptr [r11 + 4]
movzx r10d, word ptr [r11 + 4]
movzx r10, r11b
movzx r10, r11w
movzx r10, byte ptr [r11 + 4]
movzx r10, word ptr [r11 + 4]
; Source: r11, target: r11
mov r11b, 1
mov r11w, 1
mov r11d, 1
mov r11, 1
mov r11b, r11b
mov r11w, r11w
mov r11d, r11d
mov r11, r11
mov r11b, byte ptr [r11 - 4]
mov r11b, byte ptr [r11 + 4]
mov r11w, word ptr [r11 + 4]
mov r11d, dword ptr [r11 + 4]
mov r11, qword ptr [r11 + 4]
mov byte ptr [r11 - 4], r11b
mov byte ptr [r11 + 4], r11b
mov word ptr [r11 + 4], r11w
mov dword ptr [r11 + 4], r11d
mov qword ptr [r11 + 4], r11
movzx r11w, r11b
movzx r11w, byte ptr [r11 + 4]
movzx r11d, r11b
movzx r11d, r11w
movzx r11d, byte ptr [r11 + 4]
movzx r11d, word ptr [r11 + 4]
movzx r11, r11b
movzx r11, r11w
movzx r11, byte ptr [r11 + 4]
movzx r11, word ptr [r11 + 4]
; Source: r11, target: r12
mov r12b, 1
mov r12w, 1
mov r12d, 1
mov r12, 1
mov r12b, r11b
mov r12w, r11w
mov r12d, r11d
mov r12, r11
mov r12b, byte ptr [r11 - 4]
mov r12b, byte ptr [r11 + 4]
mov r12w, word ptr [r11 + 4]
mov r12d, dword ptr [r11 + 4]
mov r12, qword ptr [r11 + 4]
mov byte ptr [r12 - 4], r11b
mov byte ptr [r12 + 4], r11b
mov word ptr [r12 + 4], r11w
mov dword ptr [r12 + 4], r11d
mov qword ptr [r12 + 4], r11
movzx r12w, r11b
movzx r12w, byte ptr [r11 + 4]
movzx r12d, r11b
movzx r12d, r11w
movzx r12d, byte ptr [r11 + 4]
movzx r12d, word ptr [r11 + 4]
movzx r12, r11b
movzx r12, r11w
movzx r12, byte ptr [r11 + 4]
movzx r12, word ptr [r11 + 4]
; Source: r11, target: r13
mov r13b, 1
mov r13w, 1
mov r13d, 1
mov r13, 1
mov r13b, r11b
mov r13w, r11w
mov r13d, r11d
mov r13, r11
mov r13b, byte ptr [r11 - 4]
mov r13b, byte ptr [r11 + 4]
mov r13w, word ptr [r11 + 4]
mov r13d, dword ptr [r11 + 4]
mov r13, qword ptr [r11 + 4]
mov byte ptr [r13 - 4], r11b
mov byte ptr [r13 + 4], r11b
mov word ptr [r13 + 4], r11w
mov dword ptr [r13 + 4], r11d
mov qword ptr [r13 + 4], r11
movzx r13w, r11b
movzx r13w, byte ptr [r11 + 4]
movzx r13d, r11b
movzx r13d, r11w
movzx r13d, byte ptr [r11 + 4]
movzx r13d, word ptr [r11 + 4]
movzx r13, r11b
movzx r13, r11w
movzx r13, byte ptr [r11 + 4]
movzx r13, word ptr [r11 + 4]
; Source: r11, target: r14
mov r14b, 1
mov r14w, 1
mov r14d, 1
mov r14, 1
mov r14b, r11b
mov r14w, r11w
mov r14d, r11d
mov r14, r11
mov r14b, byte ptr [r11 - 4]
mov r14b, byte ptr [r11 + 4]
mov r14w, word ptr [r11 + 4]
mov r14d, dword ptr [r11 + 4]
mov r14, qword ptr [r11 + 4]
mov byte ptr [r14 - 4], r11b
mov byte ptr [r14 + 4], r11b
mov word ptr [r14 + 4], r11w
mov dword ptr [r14 + 4], r11d
mov qword ptr [r14 + 4], r11
movzx r14w, r11b
movzx r14w, byte ptr [r11 + 4]
movzx r14d, r11b
movzx r14d, r11w
movzx r14d, byte ptr [r11 + 4]
movzx r14d, word ptr [r11 + 4]
movzx r14, r11b
movzx r14, r11w
movzx r14, byte ptr [r11 + 4]
movzx r14, word ptr [r11 + 4]
; Source: r11, target: r15
mov r15b, 1
mov r15w, 1
mov r15d, 1
mov r15, 1
mov r15b, r11b
mov r15w, r11w
mov r15d, r11d
mov r15, r11
mov r15b, byte ptr [r11 - 4]
mov r15b, byte ptr [r11 + 4]
mov r15w, word ptr [r11 + 4]
mov r15d, dword ptr [r11 + 4]
mov r15, qword ptr [r11 + 4]
mov byte ptr [r15 - 4], r11b
mov byte ptr [r15 + 4], r11b
mov word ptr [r15 + 4], r11w
mov dword ptr [r15 + 4], r11d
mov qword ptr [r15 + 4], r11
movzx r15w, r11b
movzx r15w, byte ptr [r11 + 4]
movzx r15d, r11b
movzx r15d, r11w
movzx r15d, byte ptr [r11 + 4]
movzx r15d, word ptr [r11 + 4]
movzx r15, r11b
movzx r15, r11w
movzx r15, byte ptr [r11 + 4]
movzx r15, word ptr [r11 + 4]
; Source: r12, target: rax
mov al, 1
mov ax, 1
mov eax, 1
mov rax, 1
mov al, r12b
mov ax, r12w
mov eax, r12d
mov rax, r12
mov al, byte ptr [r12 - 4]
mov al, byte ptr [r12 + 4]
mov ax, word ptr [r12 + 4]
mov eax, dword ptr [r12 + 4]
mov rax, qword ptr [r12 + 4]
mov byte ptr [rax - 4], r12b
mov byte ptr [rax + 4], r12b
mov word ptr [rax + 4], r12w
mov dword ptr [rax + 4], r12d
mov qword ptr [rax + 4], r12
movzx ax, r12b
movzx ax, byte ptr [r12 + 4]
movzx eax, r12b
movzx eax, r12w
movzx eax, byte ptr [r12 + 4]
movzx eax, word ptr [r12 + 4]
movzx rax, r12b
movzx rax, r12w
movzx rax, byte ptr [r12 + 4]
movzx rax, word ptr [r12 + 4]
; Source: r12, target: rcx
mov cl, 1
mov cx, 1
mov ecx, 1
mov rcx, 1
mov cl, r12b
mov cx, r12w
mov ecx, r12d
mov rcx, r12
mov cl, byte ptr [r12 - 4]
mov cl, byte ptr [r12 + 4]
mov cx, word ptr [r12 + 4]
mov ecx, dword ptr [r12 + 4]
mov rcx, qword ptr [r12 + 4]
mov byte ptr [rcx - 4], r12b
mov byte ptr [rcx + 4], r12b
mov word ptr [rcx + 4], r12w
mov dword ptr [rcx + 4], r12d
mov qword ptr [rcx + 4], r12
movzx cx, r12b
movzx cx, byte ptr [r12 + 4]
movzx ecx, r12b
movzx ecx, r12w
movzx ecx, byte ptr [r12 + 4]
movzx ecx, word ptr [r12 + 4]
movzx rcx, r12b
movzx rcx, r12w
movzx rcx, byte ptr [r12 + 4]
movzx rcx, word ptr [r12 + 4]
; Source: r12, target: rdx
mov dl, 1
mov dx, 1
mov edx, 1
mov rdx, 1
mov dl, r12b
mov dx, r12w
mov edx, r12d
mov rdx, r12
mov dl, byte ptr [r12 - 4]
mov dl, byte ptr [r12 + 4]
mov dx, word ptr [r12 + 4]
mov edx, dword ptr [r12 + 4]
mov rdx, qword ptr [r12 + 4]
mov byte ptr [rdx - 4], r12b
mov byte ptr [rdx + 4], r12b
mov word ptr [rdx + 4], r12w
mov dword ptr [rdx + 4], r12d
mov qword ptr [rdx + 4], r12
movzx dx, r12b
movzx dx, byte ptr [r12 + 4]
movzx edx, r12b
movzx edx, r12w
movzx edx, byte ptr [r12 + 4]
movzx edx, word ptr [r12 + 4]
movzx rdx, r12b
movzx rdx, r12w
movzx rdx, byte ptr [r12 + 4]
movzx rdx, word ptr [r12 + 4]
; Source: r12, target: rbx
mov bl, 1
mov bx, 1
mov ebx, 1
mov rbx, 1
mov bl, r12b
mov bx, r12w
mov ebx, r12d
mov rbx, r12
mov bl, byte ptr [r12 - 4]
mov bl, byte ptr [r12 + 4]
mov bx, word ptr [r12 + 4]
mov ebx, dword ptr [r12 + 4]
mov rbx, qword ptr [r12 + 4]
mov byte ptr [rbx - 4], r12b
mov byte ptr [rbx + 4], r12b
mov word ptr [rbx + 4], r12w
mov dword ptr [rbx + 4], r12d
mov qword ptr [rbx + 4], r12
movzx bx, r12b
movzx bx, byte ptr [r12 + 4]
movzx ebx, r12b
movzx ebx, r12w
movzx ebx, byte ptr [r12 + 4]
movzx ebx, word ptr [r12 + 4]
movzx rbx, r12b
movzx rbx, r12w
movzx rbx, byte ptr [r12 + 4]
movzx rbx, word ptr [r12 + 4]
; Source: r12, target: rsp
mov spl, 1
mov sp, 1
mov esp, 1
mov rsp, 1
mov spl, r12b
mov sp, r12w
mov esp, r12d
mov rsp, r12
mov spl, byte ptr [r12 - 4]
mov spl, byte ptr [r12 + 4]
mov sp, word ptr [r12 + 4]
mov esp, dword ptr [r12 + 4]
mov rsp, qword ptr [r12 + 4]
mov byte ptr [rsp - 4], r12b
mov byte ptr [rsp + 4], r12b
mov word ptr [rsp + 4], r12w
mov dword ptr [rsp + 4], r12d
mov qword ptr [rsp + 4], r12
movzx sp, r12b
movzx sp, byte ptr [r12 + 4]
movzx esp, r12b
movzx esp, r12w
movzx esp, byte ptr [r12 + 4]
movzx esp, word ptr [r12 + 4]
movzx rsp, r12b
movzx rsp, r12w
movzx rsp, byte ptr [r12 + 4]
movzx rsp, word ptr [r12 + 4]
; Source: r12, target: rbp
mov bpl, 1
mov bp, 1
mov ebp, 1
mov rbp, 1
mov bpl, r12b
mov bp, r12w
mov ebp, r12d
mov rbp, r12
mov bpl, byte ptr [r12 - 4]
mov bpl, byte ptr [r12 + 4]
mov bp, word ptr [r12 + 4]
mov ebp, dword ptr [r12 + 4]
mov rbp, qword ptr [r12 + 4]
mov byte ptr [rbp - 4], r12b
mov byte ptr [rbp + 4], r12b
mov word ptr [rbp + 4], r12w
mov dword ptr [rbp + 4], r12d
mov qword ptr [rbp + 4], r12
movzx bp, r12b
movzx bp, byte ptr [r12 + 4]
movzx ebp, r12b
movzx ebp, r12w
movzx ebp, byte ptr [r12 + 4]
movzx ebp, word ptr [r12 + 4]
movzx rbp, r12b
movzx rbp, r12w
movzx rbp, byte ptr [r12 + 4]
movzx rbp, word ptr [r12 + 4]
; Source: r12, target: rsi
mov dil, 1
mov si, 1
mov esi, 1
mov rsi, 1
mov dil, r12b
mov si, r12w
mov esi, r12d
mov rsi, r12
mov dil, byte ptr [r12 - 4]
mov dil, byte ptr [r12 + 4]
mov si, word ptr [r12 + 4]
mov esi, dword ptr [r12 + 4]
mov rsi, qword ptr [r12 + 4]
mov byte ptr [rsi - 4], r12b
mov byte ptr [rsi + 4], r12b
mov word ptr [rsi + 4], r12w
mov dword ptr [rsi + 4], r12d
mov qword ptr [rsi + 4], r12
movzx si, r12b
movzx si, byte ptr [r12 + 4]
movzx esi, r12b
movzx esi, r12w
movzx esi, byte ptr [r12 + 4]
movzx esi, word ptr [r12 + 4]
movzx rsi, r12b
movzx rsi, r12w
movzx rsi, byte ptr [r12 + 4]
movzx rsi, word ptr [r12 + 4]
; Source: r12, target: rdi
mov sil, 1
mov di, 1
mov edi, 1
mov rdi, 1
mov sil, r12b
mov di, r12w
mov edi, r12d
mov rdi, r12
mov sil, byte ptr [r12 - 4]
mov sil, byte ptr [r12 + 4]
mov di, word ptr [r12 + 4]
mov edi, dword ptr [r12 + 4]
mov rdi, qword ptr [r12 + 4]
mov byte ptr [rdi - 4], r12b
mov byte ptr [rdi + 4], r12b
mov word ptr [rdi + 4], r12w
mov dword ptr [rdi + 4], r12d
mov qword ptr [rdi + 4], r12
movzx di, r12b
movzx di, byte ptr [r12 + 4]
movzx edi, r12b
movzx edi, r12w
movzx edi, byte ptr [r12 + 4]
movzx edi, word ptr [r12 + 4]
movzx rdi, r12b
movzx rdi, r12w
movzx rdi, byte ptr [r12 + 4]
movzx rdi, word ptr [r12 + 4]
; Source: r12, target: r8
mov r8b, 1
mov r8w, 1
mov r8d, 1
mov r8, 1
mov r8b, r12b
mov r8w, r12w
mov r8d, r12d
mov r8, r12
mov r8b, byte ptr [r12 - 4]
mov r8b, byte ptr [r12 + 4]
mov r8w, word ptr [r12 + 4]
mov r8d, dword ptr [r12 + 4]
mov r8, qword ptr [r12 + 4]
mov byte ptr [r8 - 4], r12b
mov byte ptr [r8 + 4], r12b
mov word ptr [r8 + 4], r12w
mov dword ptr [r8 + 4], r12d
mov qword ptr [r8 + 4], r12
movzx r8w, r12b
movzx r8w, byte ptr [r12 + 4]
movzx r8d, r12b
movzx r8d, r12w
movzx r8d, byte ptr [r12 + 4]
movzx r8d, word ptr [r12 + 4]
movzx r8, r12b
movzx r8, r12w
movzx r8, byte ptr [r12 + 4]
movzx r8, word ptr [r12 + 4]
; Source: r12, target: r9
mov r9b, 1
mov r9w, 1
mov r9d, 1
mov r9, 1
mov r9b, r12b
mov r9w, r12w
mov r9d, r12d
mov r9, r12
mov r9b, byte ptr [r12 - 4]
mov r9b, byte ptr [r12 + 4]
mov r9w, word ptr [r12 + 4]
mov r9d, dword ptr [r12 + 4]
mov r9, qword ptr [r12 + 4]
mov byte ptr [r9 - 4], r12b
mov byte ptr [r9 + 4], r12b
mov word ptr [r9 + 4], r12w
mov dword ptr [r9 + 4], r12d
mov qword ptr [r9 + 4], r12
movzx r9w, r12b
movzx r9w, byte ptr [r12 + 4]
movzx r9d, r12b
movzx r9d, r12w
movzx r9d, byte ptr [r12 + 4]
movzx r9d, word ptr [r12 + 4]
movzx r9, r12b
movzx r9, r12w
movzx r9, byte ptr [r12 + 4]
movzx r9, word ptr [r12 + 4]
; Source: r12, target: r10
mov r10b, 1
mov r10w, 1
mov r10d, 1
mov r10, 1
mov r10b, r12b
mov r10w, r12w
mov r10d, r12d
mov r10, r12
mov r10b, byte ptr [r12 - 4]
mov r10b, byte ptr [r12 + 4]
mov r10w, word ptr [r12 + 4]
mov r10d, dword ptr [r12 + 4]
mov r10, qword ptr [r12 + 4]
mov byte ptr [r10 - 4], r12b
mov byte ptr [r10 + 4], r12b
mov word ptr [r10 + 4], r12w
mov dword ptr [r10 + 4], r12d
mov qword ptr [r10 + 4], r12
movzx r10w, r12b
movzx r10w, byte ptr [r12 + 4]
movzx r10d, r12b
movzx r10d, r12w
movzx r10d, byte ptr [r12 + 4]
movzx r10d, word ptr [r12 + 4]
movzx r10, r12b
movzx r10, r12w
movzx r10, byte ptr [r12 + 4]
movzx r10, word ptr [r12 + 4]
; Source: r12, target: r11
mov r11b, 1
mov r11w, 1
mov r11d, 1
mov r11, 1
mov r11b, r12b
mov r11w, r12w
mov r11d, r12d
mov r11, r12
mov r11b, byte ptr [r12 - 4]
mov r11b, byte ptr [r12 + 4]
mov r11w, word ptr [r12 + 4]
mov r11d, dword ptr [r12 + 4]
mov r11, qword ptr [r12 + 4]
mov byte ptr [r11 - 4], r12b
mov byte ptr [r11 + 4], r12b
mov word ptr [r11 + 4], r12w
mov dword ptr [r11 + 4], r12d
mov qword ptr [r11 + 4], r12
movzx r11w, r12b
movzx r11w, byte ptr [r12 + 4]
movzx r11d, r12b
movzx r11d, r12w
movzx r11d, byte ptr [r12 + 4]
movzx r11d, word ptr [r12 + 4]
movzx r11, r12b
movzx r11, r12w
movzx r11, byte ptr [r12 + 4]
movzx r11, word ptr [r12 + 4]
; Source: r12, target: r12
mov r12b, 1
mov r12w, 1
mov r12d, 1
mov r12, 1
mov r12b, r12b
mov r12w, r12w
mov r12d, r12d
mov r12, r12
mov r12b, byte ptr [r12 - 4]
mov r12b, byte ptr [r12 + 4]
mov r12w, word ptr [r12 + 4]
mov r12d, dword ptr [r12 + 4]
mov r12, qword ptr [r12 + 4]
mov byte ptr [r12 - 4], r12b
mov byte ptr [r12 + 4], r12b
mov word ptr [r12 + 4], r12w
mov dword ptr [r12 + 4], r12d
mov qword ptr [r12 + 4], r12
movzx r12w, r12b
movzx r12w, byte ptr [r12 + 4]
movzx r12d, r12b
movzx r12d, r12w
movzx r12d, byte ptr [r12 + 4]
movzx r12d, word ptr [r12 + 4]
movzx r12, r12b
movzx r12, r12w
movzx r12, byte ptr [r12 + 4]
movzx r12, word ptr [r12 + 4]
; Source: r12, target: r13
mov r13b, 1
mov r13w, 1
mov r13d, 1
mov r13, 1
mov r13b, r12b
mov r13w, r12w
mov r13d, r12d
mov r13, r12
mov r13b, byte ptr [r12 - 4]
mov r13b, byte ptr [r12 + 4]
mov r13w, word ptr [r12 + 4]
mov r13d, dword ptr [r12 + 4]
mov r13, qword ptr [r12 + 4]
mov byte ptr [r13 - 4], r12b
mov byte ptr [r13 + 4], r12b
mov word ptr [r13 + 4], r12w
mov dword ptr [r13 + 4], r12d
mov qword ptr [r13 + 4], r12
movzx r13w, r12b
movzx r13w, byte ptr [r12 + 4]
movzx r13d, r12b
movzx r13d, r12w
movzx r13d, byte ptr [r12 + 4]
movzx r13d, word ptr [r12 + 4]
movzx r13, r12b
movzx r13, r12w
movzx r13, byte ptr [r12 + 4]
movzx r13, word ptr [r12 + 4]
; Source: r12, target: r14
mov r14b, 1
mov r14w, 1
mov r14d, 1
mov r14, 1
mov r14b, r12b
mov r14w, r12w
mov r14d, r12d
mov r14, r12
mov r14b, byte ptr [r12 - 4]
mov r14b, byte ptr [r12 + 4]
mov r14w, word ptr [r12 + 4]
mov r14d, dword ptr [r12 + 4]
mov r14, qword ptr [r12 + 4]
mov byte ptr [r14 - 4], r12b
mov byte ptr [r14 + 4], r12b
mov word ptr [r14 + 4], r12w
mov dword ptr [r14 + 4], r12d
mov qword ptr [r14 + 4], r12
movzx r14w, r12b
movzx r14w, byte ptr [r12 + 4]
movzx r14d, r12b
movzx r14d, r12w
movzx r14d, byte ptr [r12 + 4]
movzx r14d, word ptr [r12 + 4]
movzx r14, r12b
movzx r14, r12w
movzx r14, byte ptr [r12 + 4]
movzx r14, word ptr [r12 + 4]
; Source: r12, target: r15
mov r15b, 1
mov r15w, 1
mov r15d, 1
mov r15, 1
mov r15b, r12b
mov r15w, r12w
mov r15d, r12d
mov r15, r12
mov r15b, byte ptr [r12 - 4]
mov r15b, byte ptr [r12 + 4]
mov r15w, word ptr [r12 + 4]
mov r15d, dword ptr [r12 + 4]
mov r15, qword ptr [r12 + 4]
mov byte ptr [r15 - 4], r12b
mov byte ptr [r15 + 4], r12b
mov word ptr [r15 + 4], r12w
mov dword ptr [r15 + 4], r12d
mov qword ptr [r15 + 4], r12
movzx r15w, r12b
movzx r15w, byte ptr [r12 + 4]
movzx r15d, r12b
movzx r15d, r12w
movzx r15d, byte ptr [r12 + 4]
movzx r15d, word ptr [r12 + 4]
movzx r15, r12b
movzx r15, r12w
movzx r15, byte ptr [r12 + 4]
movzx r15, word ptr [r12 + 4]
; Source: r13, target: rax
mov al, 1
mov ax, 1
mov eax, 1
mov rax, 1
mov al, r13b
mov ax, r13w
mov eax, r13d
mov rax, r13
mov al, byte ptr [r13 - 4]
mov al, byte ptr [r13 + 4]
mov ax, word ptr [r13 + 4]
mov eax, dword ptr [r13 + 4]
mov rax, qword ptr [r13 + 4]
mov byte ptr [rax - 4], r13b
mov byte ptr [rax + 4], r13b
mov word ptr [rax + 4], r13w
mov dword ptr [rax + 4], r13d
mov qword ptr [rax + 4], r13
movzx ax, r13b
movzx ax, byte ptr [r13 + 4]
movzx eax, r13b
movzx eax, r13w
movzx eax, byte ptr [r13 + 4]
movzx eax, word ptr [r13 + 4]
movzx rax, r13b
movzx rax, r13w
movzx rax, byte ptr [r13 + 4]
movzx rax, word ptr [r13 + 4]
; Source: r13, target: rcx
mov cl, 1
mov cx, 1
mov ecx, 1
mov rcx, 1
mov cl, r13b
mov cx, r13w
mov ecx, r13d
mov rcx, r13
mov cl, byte ptr [r13 - 4]
mov cl, byte ptr [r13 + 4]
mov cx, word ptr [r13 + 4]
mov ecx, dword ptr [r13 + 4]
mov rcx, qword ptr [r13 + 4]
mov byte ptr [rcx - 4], r13b
mov byte ptr [rcx + 4], r13b
mov word ptr [rcx + 4], r13w
mov dword ptr [rcx + 4], r13d
mov qword ptr [rcx + 4], r13
movzx cx, r13b
movzx cx, byte ptr [r13 + 4]
movzx ecx, r13b
movzx ecx, r13w
movzx ecx, byte ptr [r13 + 4]
movzx ecx, word ptr [r13 + 4]
movzx rcx, r13b
movzx rcx, r13w
movzx rcx, byte ptr [r13 + 4]
movzx rcx, word ptr [r13 + 4]
; Source: r13, target: rdx
mov dl, 1
mov dx, 1
mov edx, 1
mov rdx, 1
mov dl, r13b
mov dx, r13w
mov edx, r13d
mov rdx, r13
mov dl, byte ptr [r13 - 4]
mov dl, byte ptr [r13 + 4]
mov dx, word ptr [r13 + 4]
mov edx, dword ptr [r13 + 4]
mov rdx, qword ptr [r13 + 4]
mov byte ptr [rdx - 4], r13b
mov byte ptr [rdx + 4], r13b
mov word ptr [rdx + 4], r13w
mov dword ptr [rdx + 4], r13d
mov qword ptr [rdx + 4], r13
movzx dx, r13b
movzx dx, byte ptr [r13 + 4]
movzx edx, r13b
movzx edx, r13w
movzx edx, byte ptr [r13 + 4]
movzx edx, word ptr [r13 + 4]
movzx rdx, r13b
movzx rdx, r13w
movzx rdx, byte ptr [r13 + 4]
movzx rdx, word ptr [r13 + 4]
; Source: r13, target: rbx
mov bl, 1
mov bx, 1
mov ebx, 1
mov rbx, 1
mov bl, r13b
mov bx, r13w
mov ebx, r13d
mov rbx, r13
mov bl, byte ptr [r13 - 4]
mov bl, byte ptr [r13 + 4]
mov bx, word ptr [r13 + 4]
mov ebx, dword ptr [r13 + 4]
mov rbx, qword ptr [r13 + 4]
mov byte ptr [rbx - 4], r13b
mov byte ptr [rbx + 4], r13b
mov word ptr [rbx + 4], r13w
mov dword ptr [rbx + 4], r13d
mov qword ptr [rbx + 4], r13
movzx bx, r13b
movzx bx, byte ptr [r13 + 4]
movzx ebx, r13b
movzx ebx, r13w
movzx ebx, byte ptr [r13 + 4]
movzx ebx, word ptr [r13 + 4]
movzx rbx, r13b
movzx rbx, r13w
movzx rbx, byte ptr [r13 + 4]
movzx rbx, word ptr [r13 + 4]
; Source: r13, target: rsp
mov spl, 1
mov sp, 1
mov esp, 1
mov rsp, 1
mov spl, r13b
mov sp, r13w
mov esp, r13d
mov rsp, r13
mov spl, byte ptr [r13 - 4]
mov spl, byte ptr [r13 + 4]
mov sp, word ptr [r13 + 4]
mov esp, dword ptr [r13 + 4]
mov rsp, qword ptr [r13 + 4]
mov byte ptr [rsp - 4], r13b
mov byte ptr [rsp + 4], r13b
mov word ptr [rsp + 4], r13w
mov dword ptr [rsp + 4], r13d
mov qword ptr [rsp + 4], r13
movzx sp, r13b
movzx sp, byte ptr [r13 + 4]
movzx esp, r13b
movzx esp, r13w
movzx esp, byte ptr [r13 + 4]
movzx esp, word ptr [r13 + 4]
movzx rsp, r13b
movzx rsp, r13w
movzx rsp, byte ptr [r13 + 4]
movzx rsp, word ptr [r13 + 4]
; Source: r13, target: rbp
mov bpl, 1
mov bp, 1
mov ebp, 1
mov rbp, 1
mov bpl, r13b
mov bp, r13w
mov ebp, r13d
mov rbp, r13
mov bpl, byte ptr [r13 - 4]
mov bpl, byte ptr [r13 + 4]
mov bp, word ptr [r13 + 4]
mov ebp, dword ptr [r13 + 4]
mov rbp, qword ptr [r13 + 4]
mov byte ptr [rbp - 4], r13b
mov byte ptr [rbp + 4], r13b
mov word ptr [rbp + 4], r13w
mov dword ptr [rbp + 4], r13d
mov qword ptr [rbp + 4], r13
movzx bp, r13b
movzx bp, byte ptr [r13 + 4]
movzx ebp, r13b
movzx ebp, r13w
movzx ebp, byte ptr [r13 + 4]
movzx ebp, word ptr [r13 + 4]
movzx rbp, r13b
movzx rbp, r13w
movzx rbp, byte ptr [r13 + 4]
movzx rbp, word ptr [r13 + 4]
; Source: r13, target: rsi
mov dil, 1
mov si, 1
mov esi, 1
mov rsi, 1
mov dil, r13b
mov si, r13w
mov esi, r13d
mov rsi, r13
mov dil, byte ptr [r13 - 4]
mov dil, byte ptr [r13 + 4]
mov si, word ptr [r13 + 4]
mov esi, dword ptr [r13 + 4]
mov rsi, qword ptr [r13 + 4]
mov byte ptr [rsi - 4], r13b
mov byte ptr [rsi + 4], r13b
mov word ptr [rsi + 4], r13w
mov dword ptr [rsi + 4], r13d
mov qword ptr [rsi + 4], r13
movzx si, r13b
movzx si, byte ptr [r13 + 4]
movzx esi, r13b
movzx esi, r13w
movzx esi, byte ptr [r13 + 4]
movzx esi, word ptr [r13 + 4]
movzx rsi, r13b
movzx rsi, r13w
movzx rsi, byte ptr [r13 + 4]
movzx rsi, word ptr [r13 + 4]
; Source: r13, target: rdi
mov sil, 1
mov di, 1
mov edi, 1
mov rdi, 1
mov sil, r13b
mov di, r13w
mov edi, r13d
mov rdi, r13
mov sil, byte ptr [r13 - 4]
mov sil, byte ptr [r13 + 4]
mov di, word ptr [r13 + 4]
mov edi, dword ptr [r13 + 4]
mov rdi, qword ptr [r13 + 4]
mov byte ptr [rdi - 4], r13b
mov byte ptr [rdi + 4], r13b
mov word ptr [rdi + 4], r13w
mov dword ptr [rdi + 4], r13d
mov qword ptr [rdi + 4], r13
movzx di, r13b
movzx di, byte ptr [r13 + 4]
movzx edi, r13b
movzx edi, r13w
movzx edi, byte ptr [r13 + 4]
movzx edi, word ptr [r13 + 4]
movzx rdi, r13b
movzx rdi, r13w
movzx rdi, byte ptr [r13 + 4]
movzx rdi, word ptr [r13 + 4]
; Source: r13, target: r8
mov r8b, 1
mov r8w, 1
mov r8d, 1
mov r8, 1
mov r8b, r13b
mov r8w, r13w
mov r8d, r13d
mov r8, r13
mov r8b, byte ptr [r13 - 4]
mov r8b, byte ptr [r13 + 4]
mov r8w, word ptr [r13 + 4]
mov r8d, dword ptr [r13 + 4]
mov r8, qword ptr [r13 + 4]
mov byte ptr [r8 - 4], r13b
mov byte ptr [r8 + 4], r13b
mov word ptr [r8 + 4], r13w
mov dword ptr [r8 + 4], r13d
mov qword ptr [r8 + 4], r13
movzx r8w, r13b
movzx r8w, byte ptr [r13 + 4]
movzx r8d, r13b
movzx r8d, r13w
movzx r8d, byte ptr [r13 + 4]
movzx r8d, word ptr [r13 + 4]
movzx r8, r13b
movzx r8, r13w
movzx r8, byte ptr [r13 + 4]
movzx r8, word ptr [r13 + 4]
; Source: r13, target: r9
mov r9b, 1
mov r9w, 1
mov r9d, 1
mov r9, 1
mov r9b, r13b
mov r9w, r13w
mov r9d, r13d
mov r9, r13
mov r9b, byte ptr [r13 - 4]
mov r9b, byte ptr [r13 + 4]
mov r9w, word ptr [r13 + 4]
mov r9d, dword ptr [r13 + 4]
mov r9, qword ptr [r13 + 4]
mov byte ptr [r9 - 4], r13b
mov byte ptr [r9 + 4], r13b
mov word ptr [r9 + 4], r13w
mov dword ptr [r9 + 4], r13d
mov qword ptr [r9 + 4], r13
movzx r9w, r13b
movzx r9w, byte ptr [r13 + 4]
movzx r9d, r13b
movzx r9d, r13w
movzx r9d, byte ptr [r13 + 4]
movzx r9d, word ptr [r13 + 4]
movzx r9, r13b
movzx r9, r13w
movzx r9, byte ptr [r13 + 4]
movzx r9, word ptr [r13 + 4]
; Source: r13, target: r10
mov r10b, 1
mov r10w, 1
mov r10d, 1
mov r10, 1
mov r10b, r13b
mov r10w, r13w
mov r10d, r13d
mov r10, r13
mov r10b, byte ptr [r13 - 4]
mov r10b, byte ptr [r13 + 4]
mov r10w, word ptr [r13 + 4]
mov r10d, dword ptr [r13 + 4]
mov r10, qword ptr [r13 + 4]
mov byte ptr [r10 - 4], r13b
mov byte ptr [r10 + 4], r13b
mov word ptr [r10 + 4], r13w
mov dword ptr [r10 + 4], r13d
mov qword ptr [r10 + 4], r13
movzx r10w, r13b
movzx r10w, byte ptr [r13 + 4]
movzx r10d, r13b
movzx r10d, r13w
movzx r10d, byte ptr [r13 + 4]
movzx r10d, word ptr [r13 + 4]
movzx r10, r13b
movzx r10, r13w
movzx r10, byte ptr [r13 + 4]
movzx r10, word ptr [r13 + 4]
; Source: r13, target: r11
mov r11b, 1
mov r11w, 1
mov r11d, 1
mov r11, 1
mov r11b, r13b
mov r11w, r13w
mov r11d, r13d
mov r11, r13
mov r11b, byte ptr [r13 - 4]
mov r11b, byte ptr [r13 + 4]
mov r11w, word ptr [r13 + 4]
mov r11d, dword ptr [r13 + 4]
mov r11, qword ptr [r13 + 4]
mov byte ptr [r11 - 4], r13b
mov byte ptr [r11 + 4], r13b
mov word ptr [r11 + 4], r13w
mov dword ptr [r11 + 4], r13d
mov qword ptr [r11 + 4], r13
movzx r11w, r13b
movzx r11w, byte ptr [r13 + 4]
movzx r11d, r13b
movzx r11d, r13w
movzx r11d, byte ptr [r13 + 4]
movzx r11d, word ptr [r13 + 4]
movzx r11, r13b
movzx r11, r13w
movzx r11, byte ptr [r13 + 4]
movzx r11, word ptr [r13 + 4]
; Source: r13, target: r12
mov r12b, 1
mov r12w, 1
mov r12d, 1
mov r12, 1
mov r12b, r13b
mov r12w, r13w
mov r12d, r13d
mov r12, r13
mov r12b, byte ptr [r13 - 4]
mov r12b, byte ptr [r13 + 4]
mov r12w, word ptr [r13 + 4]
mov r12d, dword ptr [r13 + 4]
mov r12, qword ptr [r13 + 4]
mov byte ptr [r12 - 4], r13b
mov byte ptr [r12 + 4], r13b
mov word ptr [r12 + 4], r13w
mov dword ptr [r12 + 4], r13d
mov qword ptr [r12 + 4], r13
movzx r12w, r13b
movzx r12w, byte ptr [r13 + 4]
movzx r12d, r13b
movzx r12d, r13w
movzx r12d, byte ptr [r13 + 4]
movzx r12d, word ptr [r13 + 4]
movzx r12, r13b
movzx r12, r13w
movzx r12, byte ptr [r13 + 4]
movzx r12, word ptr [r13 + 4]
; Source: r13, target: r13
mov r13b, 1
mov r13w, 1
mov r13d, 1
mov r13, 1
mov r13b, r13b
mov r13w, r13w
mov r13d, r13d
mov r13, r13
mov r13b, byte ptr [r13 - 4]
mov r13b, byte ptr [r13 + 4]
mov r13w, word ptr [r13 + 4]
mov r13d, dword ptr [r13 + 4]
mov r13, qword ptr [r13 + 4]
mov byte ptr [r13 - 4], r13b
mov byte ptr [r13 + 4], r13b
mov word ptr [r13 + 4], r13w
mov dword ptr [r13 + 4], r13d
mov qword ptr [r13 + 4], r13
movzx r13w, r13b
movzx r13w, byte ptr [r13 + 4]
movzx r13d, r13b
movzx r13d, r13w
movzx r13d, byte ptr [r13 + 4]
movzx r13d, word ptr [r13 + 4]
movzx r13, r13b
movzx r13, r13w
movzx r13, byte ptr [r13 + 4]
movzx r13, word ptr [r13 + 4]
; Source: r13, target: r14
mov r14b, 1
mov r14w, 1
mov r14d, 1
mov r14, 1
mov r14b, r13b
mov r14w, r13w
mov r14d, r13d
mov r14, r13
mov r14b, byte ptr [r13 - 4]
mov r14b, byte ptr [r13 + 4]
mov r14w, word ptr [r13 + 4]
mov r14d, dword ptr [r13 + 4]
mov r14, qword ptr [r13 + 4]
mov byte ptr [r14 - 4], r13b
mov byte ptr [r14 + 4], r13b
mov word ptr [r14 + 4], r13w
mov dword ptr [r14 + 4], r13d
mov qword ptr [r14 + 4], r13
movzx r14w, r13b
movzx r14w, byte ptr [r13 + 4]
movzx r14d, r13b
movzx r14d, r13w
movzx r14d, byte ptr [r13 + 4]
movzx r14d, word ptr [r13 + 4]
movzx r14, r13b
movzx r14, r13w
movzx r14, byte ptr [r13 + 4]
movzx r14, word ptr [r13 + 4]
; Source: r13, target: r15
mov r15b, 1
mov r15w, 1
mov r15d, 1
mov r15, 1
mov r15b, r13b
mov r15w, r13w
mov r15d, r13d
mov r15, r13
mov r15b, byte ptr [r13 - 4]
mov r15b, byte ptr [r13 + 4]
mov r15w, word ptr [r13 + 4]
mov r15d, dword ptr [r13 + 4]
mov r15, qword ptr [r13 + 4]
mov byte ptr [r15 - 4], r13b
mov byte ptr [r15 + 4], r13b
mov word ptr [r15 + 4], r13w
mov dword ptr [r15 + 4], r13d
mov qword ptr [r15 + 4], r13
movzx r15w, r13b
movzx r15w, byte ptr [r13 + 4]
movzx r15d, r13b
movzx r15d, r13w
movzx r15d, byte ptr [r13 + 4]
movzx r15d, word ptr [r13 + 4]
movzx r15, r13b
movzx r15, r13w
movzx r15, byte ptr [r13 + 4]
movzx r15, word ptr [r13 + 4]
; Source: r14, target: rax
mov al, 1
mov ax, 1
mov eax, 1
mov rax, 1
mov al, r14b
mov ax, r14w
mov eax, r14d
mov rax, r14
mov al, byte ptr [r14 - 4]
mov al, byte ptr [r14 + 4]
mov ax, word ptr [r14 + 4]
mov eax, dword ptr [r14 + 4]
mov rax, qword ptr [r14 + 4]
mov byte ptr [rax - 4], r14b
mov byte ptr [rax + 4], r14b
mov word ptr [rax + 4], r14w
mov dword ptr [rax + 4], r14d
mov qword ptr [rax + 4], r14
movzx ax, r14b
movzx ax, byte ptr [r14 + 4]
movzx eax, r14b
movzx eax, r14w
movzx eax, byte ptr [r14 + 4]
movzx eax, word ptr [r14 + 4]
movzx rax, r14b
movzx rax, r14w
movzx rax, byte ptr [r14 + 4]
movzx rax, word ptr [r14 + 4]
; Source: r14, target: rcx
mov cl, 1
mov cx, 1
mov ecx, 1
mov rcx, 1
mov cl, r14b
mov cx, r14w
mov ecx, r14d
mov rcx, r14
mov cl, byte ptr [r14 - 4]
mov cl, byte ptr [r14 + 4]
mov cx, word ptr [r14 + 4]
mov ecx, dword ptr [r14 + 4]
mov rcx, qword ptr [r14 + 4]
mov byte ptr [rcx - 4], r14b
mov byte ptr [rcx + 4], r14b
mov word ptr [rcx + 4], r14w
mov dword ptr [rcx + 4], r14d
mov qword ptr [rcx + 4], r14
movzx cx, r14b
movzx cx, byte ptr [r14 + 4]
movzx ecx, r14b
movzx ecx, r14w
movzx ecx, byte ptr [r14 + 4]
movzx ecx, word ptr [r14 + 4]
movzx rcx, r14b
movzx rcx, r14w
movzx rcx, byte ptr [r14 + 4]
movzx rcx, word ptr [r14 + 4]
; Source: r14, target: rdx
mov dl, 1
mov dx, 1
mov edx, 1
mov rdx, 1
mov dl, r14b
mov dx, r14w
mov edx, r14d
mov rdx, r14
mov dl, byte ptr [r14 - 4]
mov dl, byte ptr [r14 + 4]
mov dx, word ptr [r14 + 4]
mov edx, dword ptr [r14 + 4]
mov rdx, qword ptr [r14 + 4]
mov byte ptr [rdx - 4], r14b
mov byte ptr [rdx + 4], r14b
mov word ptr [rdx + 4], r14w
mov dword ptr [rdx + 4], r14d
mov qword ptr [rdx + 4], r14
movzx dx, r14b
movzx dx, byte ptr [r14 + 4]
movzx edx, r14b
movzx edx, r14w
movzx edx, byte ptr [r14 + 4]
movzx edx, word ptr [r14 + 4]
movzx rdx, r14b
movzx rdx, r14w
movzx rdx, byte ptr [r14 + 4]
movzx rdx, word ptr [r14 + 4]
; Source: r14, target: rbx
mov bl, 1
mov bx, 1
mov ebx, 1
mov rbx, 1
mov bl, r14b
mov bx, r14w
mov ebx, r14d
mov rbx, r14
mov bl, byte ptr [r14 - 4]
mov bl, byte ptr [r14 + 4]
mov bx, word ptr [r14 + 4]
mov ebx, dword ptr [r14 + 4]
mov rbx, qword ptr [r14 + 4]
mov byte ptr [rbx - 4], r14b
mov byte ptr [rbx + 4], r14b
mov word ptr [rbx + 4], r14w
mov dword ptr [rbx + 4], r14d
mov qword ptr [rbx + 4], r14
movzx bx, r14b
movzx bx, byte ptr [r14 + 4]
movzx ebx, r14b
movzx ebx, r14w
movzx ebx, byte ptr [r14 + 4]
movzx ebx, word ptr [r14 + 4]
movzx rbx, r14b
movzx rbx, r14w
movzx rbx, byte ptr [r14 + 4]
movzx rbx, word ptr [r14 + 4]
; Source: r14, target: rsp
mov spl, 1
mov sp, 1
mov esp, 1
mov rsp, 1
mov spl, r14b
mov sp, r14w
mov esp, r14d
mov rsp, r14
mov spl, byte ptr [r14 - 4]
mov spl, byte ptr [r14 + 4]
mov sp, word ptr [r14 + 4]
mov esp, dword ptr [r14 + 4]
mov rsp, qword ptr [r14 + 4]
mov byte ptr [rsp - 4], r14b
mov byte ptr [rsp + 4], r14b
mov word ptr [rsp + 4], r14w
mov dword ptr [rsp + 4], r14d
mov qword ptr [rsp + 4], r14
movzx sp, r14b
movzx sp, byte ptr [r14 + 4]
movzx esp, r14b
movzx esp, r14w
movzx esp, byte ptr [r14 + 4]
movzx esp, word ptr [r14 + 4]
movzx rsp, r14b
movzx rsp, r14w
movzx rsp, byte ptr [r14 + 4]
movzx rsp, word ptr [r14 + 4]
; Source: r14, target: rbp
mov bpl, 1
mov bp, 1
mov ebp, 1
mov rbp, 1
mov bpl, r14b
mov bp, r14w
mov ebp, r14d
mov rbp, r14
mov bpl, byte ptr [r14 - 4]
mov bpl, byte ptr [r14 + 4]
mov bp, word ptr [r14 + 4]
mov ebp, dword ptr [r14 + 4]
mov rbp, qword ptr [r14 + 4]
mov byte ptr [rbp - 4], r14b
mov byte ptr [rbp + 4], r14b
mov word ptr [rbp + 4], r14w
mov dword ptr [rbp + 4], r14d
mov qword ptr [rbp + 4], r14
movzx bp, r14b
movzx bp, byte ptr [r14 + 4]
movzx ebp, r14b
movzx ebp, r14w
movzx ebp, byte ptr [r14 + 4]
movzx ebp, word ptr [r14 + 4]
movzx rbp, r14b
movzx rbp, r14w
movzx rbp, byte ptr [r14 + 4]
movzx rbp, word ptr [r14 + 4]
; Source: r14, target: rsi
mov dil, 1
mov si, 1
mov esi, 1
mov rsi, 1
mov dil, r14b
mov si, r14w
mov esi, r14d
mov rsi, r14
mov dil, byte ptr [r14 - 4]
mov dil, byte ptr [r14 + 4]
mov si, word ptr [r14 + 4]
mov esi, dword ptr [r14 + 4]
mov rsi, qword ptr [r14 + 4]
mov byte ptr [rsi - 4], r14b
mov byte ptr [rsi + 4], r14b
mov word ptr [rsi + 4], r14w
mov dword ptr [rsi + 4], r14d
mov qword ptr [rsi + 4], r14
movzx si, r14b
movzx si, byte ptr [r14 + 4]
movzx esi, r14b
movzx esi, r14w
movzx esi, byte ptr [r14 + 4]
movzx esi, word ptr [r14 + 4]
movzx rsi, r14b
movzx rsi, r14w
movzx rsi, byte ptr [r14 + 4]
movzx rsi, word ptr [r14 + 4]
; Source: r14, target: rdi
mov sil, 1
mov di, 1
mov edi, 1
mov rdi, 1
mov sil, r14b
mov di, r14w
mov edi, r14d
mov rdi, r14
mov sil, byte ptr [r14 - 4]
mov sil, byte ptr [r14 + 4]
mov di, word ptr [r14 + 4]
mov edi, dword ptr [r14 + 4]
mov rdi, qword ptr [r14 + 4]
mov byte ptr [rdi - 4], r14b
mov byte ptr [rdi + 4], r14b
mov word ptr [rdi + 4], r14w
mov dword ptr [rdi + 4], r14d
mov qword ptr [rdi + 4], r14
movzx di, r14b
movzx di, byte ptr [r14 + 4]
movzx edi, r14b
movzx edi, r14w
movzx edi, byte ptr [r14 + 4]
movzx edi, word ptr [r14 + 4]
movzx rdi, r14b
movzx rdi, r14w
movzx rdi, byte ptr [r14 + 4]
movzx rdi, word ptr [r14 + 4]
; Source: r14, target: r8
mov r8b, 1
mov r8w, 1
mov r8d, 1
mov r8, 1
mov r8b, r14b
mov r8w, r14w
mov r8d, r14d
mov r8, r14
mov r8b, byte ptr [r14 - 4]
mov r8b, byte ptr [r14 + 4]
mov r8w, word ptr [r14 + 4]
mov r8d, dword ptr [r14 + 4]
mov r8, qword ptr [r14 + 4]
mov byte ptr [r8 - 4], r14b
mov byte ptr [r8 + 4], r14b
mov word ptr [r8 + 4], r14w
mov dword ptr [r8 + 4], r14d
mov qword ptr [r8 + 4], r14
movzx r8w, r14b
movzx r8w, byte ptr [r14 + 4]
movzx r8d, r14b
movzx r8d, r14w
movzx r8d, byte ptr [r14 + 4]
movzx r8d, word ptr [r14 + 4]
movzx r8, r14b
movzx r8, r14w
movzx r8, byte ptr [r14 + 4]
movzx r8, word ptr [r14 + 4]
; Source: r14, target: r9
mov r9b, 1
mov r9w, 1
mov r9d, 1
mov r9, 1
mov r9b, r14b
mov r9w, r14w
mov r9d, r14d
mov r9, r14
mov r9b, byte ptr [r14 - 4]
mov r9b, byte ptr [r14 + 4]
mov r9w, word ptr [r14 + 4]
mov r9d, dword ptr [r14 + 4]
mov r9, qword ptr [r14 + 4]
mov byte ptr [r9 - 4], r14b
mov byte ptr [r9 + 4], r14b
mov word ptr [r9 + 4], r14w
mov dword ptr [r9 + 4], r14d
mov qword ptr [r9 + 4], r14
movzx r9w, r14b
movzx r9w, byte ptr [r14 + 4]
movzx r9d, r14b
movzx r9d, r14w
movzx r9d, byte ptr [r14 + 4]
movzx r9d, word ptr [r14 + 4]
movzx r9, r14b
movzx r9, r14w
movzx r9, byte ptr [r14 + 4]
movzx r9, word ptr [r14 + 4]
; Source: r14, target: r10
mov r10b, 1
mov r10w, 1
mov r10d, 1
mov r10, 1
mov r10b, r14b
mov r10w, r14w
mov r10d, r14d
mov r10, r14
mov r10b, byte ptr [r14 - 4]
mov r10b, byte ptr [r14 + 4]
mov r10w, word ptr [r14 + 4]
mov r10d, dword ptr [r14 + 4]
mov r10, qword ptr [r14 + 4]
mov byte ptr [r10 - 4], r14b
mov byte ptr [r10 + 4], r14b
mov word ptr [r10 + 4], r14w
mov dword ptr [r10 + 4], r14d
mov qword ptr [r10 + 4], r14
movzx r10w, r14b
movzx r10w, byte ptr [r14 + 4]
movzx r10d, r14b
movzx r10d, r14w
movzx r10d, byte ptr [r14 + 4]
movzx r10d, word ptr [r14 + 4]
movzx r10, r14b
movzx r10, r14w
movzx r10, byte ptr [r14 + 4]
movzx r10, word ptr [r14 + 4]
; Source: r14, target: r11
mov r11b, 1
mov r11w, 1
mov r11d, 1
mov r11, 1
mov r11b, r14b
mov r11w, r14w
mov r11d, r14d
mov r11, r14
mov r11b, byte ptr [r14 - 4]
mov r11b, byte ptr [r14 + 4]
mov r11w, word ptr [r14 + 4]
mov r11d, dword ptr [r14 + 4]
mov r11, qword ptr [r14 + 4]
mov byte ptr [r11 - 4], r14b
mov byte ptr [r11 + 4], r14b
mov word ptr [r11 + 4], r14w
mov dword ptr [r11 + 4], r14d
mov qword ptr [r11 + 4], r14
movzx r11w, r14b
movzx r11w, byte ptr [r14 + 4]
movzx r11d, r14b
movzx r11d, r14w
movzx r11d, byte ptr [r14 + 4]
movzx r11d, word ptr [r14 + 4]
movzx r11, r14b
movzx r11, r14w
movzx r11, byte ptr [r14 + 4]
movzx r11, word ptr [r14 + 4]
; Source: r14, target: r12
mov r12b, 1
mov r12w, 1
mov r12d, 1
mov r12, 1
mov r12b, r14b
mov r12w, r14w
mov r12d, r14d
mov r12, r14
mov r12b, byte ptr [r14 - 4]
mov r12b, byte ptr [r14 + 4]
mov r12w, word ptr [r14 + 4]
mov r12d, dword ptr [r14 + 4]
mov r12, qword ptr [r14 + 4]
mov byte ptr [r12 - 4], r14b
mov byte ptr [r12 + 4], r14b
mov word ptr [r12 + 4], r14w
mov dword ptr [r12 + 4], r14d
mov qword ptr [r12 + 4], r14
movzx r12w, r14b
movzx r12w, byte ptr [r14 + 4]
movzx r12d, r14b
movzx r12d, r14w
movzx r12d, byte ptr [r14 + 4]
movzx r12d, word ptr [r14 + 4]
movzx r12, r14b
movzx r12, r14w
movzx r12, byte ptr [r14 + 4]
movzx r12, word ptr [r14 + 4]
; Source: r14, target: r13
mov r13b, 1
mov r13w, 1
mov r13d, 1
mov r13, 1
mov r13b, r14b
mov r13w, r14w
mov r13d, r14d
mov r13, r14
mov r13b, byte ptr [r14 - 4]
mov r13b, byte ptr [r14 + 4]
mov r13w, word ptr [r14 + 4]
mov r13d, dword ptr [r14 + 4]
mov r13, qword ptr [r14 + 4]
mov byte ptr [r13 - 4], r14b
mov byte ptr [r13 + 4], r14b
mov word ptr [r13 + 4], r14w
mov dword ptr [r13 + 4], r14d
mov qword ptr [r13 + 4], r14
movzx r13w, r14b
movzx r13w, byte ptr [r14 + 4]
movzx r13d, r14b
movzx r13d, r14w
movzx r13d, byte ptr [r14 + 4]
movzx r13d, word ptr [r14 + 4]
movzx r13, r14b
movzx r13, r14w
movzx r13, byte ptr [r14 + 4]
movzx r13, word ptr [r14 + 4]
; Source: r14, target: r14
mov r14b, 1
mov r14w, 1
mov r14d, 1
mov r14, 1
mov r14b, r14b
mov r14w, r14w
mov r14d, r14d
mov r14, r14
mov r14b, byte ptr [r14 - 4]
mov r14b, byte ptr [r14 + 4]
mov r14w, word ptr [r14 + 4]
mov r14d, dword ptr [r14 + 4]
mov r14, qword ptr [r14 + 4]
mov byte ptr [r14 - 4], r14b
mov byte ptr [r14 + 4], r14b
mov word ptr [r14 + 4], r14w
mov dword ptr [r14 + 4], r14d
mov qword ptr [r14 + 4], r14
movzx r14w, r14b
movzx r14w, byte ptr [r14 + 4]
movzx r14d, r14b
movzx r14d, r14w
movzx r14d, byte ptr [r14 + 4]
movzx r14d, word ptr [r14 + 4]
movzx r14, r14b
movzx r14, r14w
movzx r14, byte ptr [r14 + 4]
movzx r14, word ptr [r14 + 4]
; Source: r14, target: r15
mov r15b, 1
mov r15w, 1
mov r15d, 1
mov r15, 1
mov r15b, r14b
mov r15w, r14w
mov r15d, r14d
mov r15, r14
mov r15b, byte ptr [r14 - 4]
mov r15b, byte ptr [r14 + 4]
mov r15w, word ptr [r14 + 4]
mov r15d, dword ptr [r14 + 4]
mov r15, qword ptr [r14 + 4]
mov byte ptr [r15 - 4], r14b
mov byte ptr [r15 + 4], r14b
mov word ptr [r15 + 4], r14w
mov dword ptr [r15 + 4], r14d
mov qword ptr [r15 + 4], r14
movzx r15w, r14b
movzx r15w, byte ptr [r14 + 4]
movzx r15d, r14b
movzx r15d, r14w
movzx r15d, byte ptr [r14 + 4]
movzx r15d, word ptr [r14 + 4]
movzx r15, r14b
movzx r15, r14w
movzx r15, byte ptr [r14 + 4]
movzx r15, word ptr [r14 + 4]
; Source: r15, target: rax
mov al, 1
mov ax, 1
mov eax, 1
mov rax, 1
mov al, r15b
mov ax, r15w
mov eax, r15d
mov rax, r15
mov al, byte ptr [r15 - 4]
mov al, byte ptr [r15 + 4]
mov ax, word ptr [r15 + 4]
mov eax, dword ptr [r15 + 4]
mov rax, qword ptr [r15 + 4]
mov byte ptr [rax - 4], r15b
mov byte ptr [rax + 4], r15b
mov word ptr [rax + 4], r15w
mov dword ptr [rax + 4], r15d
mov qword ptr [rax + 4], r15
movzx ax, r15b
movzx ax, byte ptr [r15 + 4]
movzx eax, r15b
movzx eax, r15w
movzx eax, byte ptr [r15 + 4]
movzx eax, word ptr [r15 + 4]
movzx rax, r15b
movzx rax, r15w
movzx rax, byte ptr [r15 + 4]
movzx rax, word ptr [r15 + 4]
; Source: r15, target: rcx
mov cl, 1
mov cx, 1
mov ecx, 1
mov rcx, 1
mov cl, r15b
mov cx, r15w
mov ecx, r15d
mov rcx, r15
mov cl, byte ptr [r15 - 4]
mov cl, byte ptr [r15 + 4]
mov cx, word ptr [r15 + 4]
mov ecx, dword ptr [r15 + 4]
mov rcx, qword ptr [r15 + 4]
mov byte ptr [rcx - 4], r15b
mov byte ptr [rcx + 4], r15b
mov word ptr [rcx + 4], r15w
mov dword ptr [rcx + 4], r15d
mov qword ptr [rcx + 4], r15
movzx cx, r15b
movzx cx, byte ptr [r15 + 4]
movzx ecx, r15b
movzx ecx, r15w
movzx ecx, byte ptr [r15 + 4]
movzx ecx, word ptr [r15 + 4]
movzx rcx, r15b
movzx rcx, r15w
movzx rcx, byte ptr [r15 + 4]
movzx rcx, word ptr [r15 + 4]
; Source: r15, target: rdx
mov dl, 1
mov dx, 1
mov edx, 1
mov rdx, 1
mov dl, r15b
mov dx, r15w
mov edx, r15d
mov rdx, r15
mov dl, byte ptr [r15 - 4]
mov dl, byte ptr [r15 + 4]
mov dx, word ptr [r15 + 4]
mov edx, dword ptr [r15 + 4]
mov rdx, qword ptr [r15 + 4]
mov byte ptr [rdx - 4], r15b
mov byte ptr [rdx + 4], r15b
mov word ptr [rdx + 4], r15w
mov dword ptr [rdx + 4], r15d
mov qword ptr [rdx + 4], r15
movzx dx, r15b
movzx dx, byte ptr [r15 + 4]
movzx edx, r15b
movzx edx, r15w
movzx edx, byte ptr [r15 + 4]
movzx edx, word ptr [r15 + 4]
movzx rdx, r15b
movzx rdx, r15w
movzx rdx, byte ptr [r15 + 4]
movzx rdx, word ptr [r15 + 4]
; Source: r15, target: rbx
mov bl, 1
mov bx, 1
mov ebx, 1
mov rbx, 1
mov bl, r15b
mov bx, r15w
mov ebx, r15d
mov rbx, r15
mov bl, byte ptr [r15 - 4]
mov bl, byte ptr [r15 + 4]
mov bx, word ptr [r15 + 4]
mov ebx, dword ptr [r15 + 4]
mov rbx, qword ptr [r15 + 4]
mov byte ptr [rbx - 4], r15b
mov byte ptr [rbx + 4], r15b
mov word ptr [rbx + 4], r15w
mov dword ptr [rbx + 4], r15d
mov qword ptr [rbx + 4], r15
movzx bx, r15b
movzx bx, byte ptr [r15 + 4]
movzx ebx, r15b
movzx ebx, r15w
movzx ebx, byte ptr [r15 + 4]
movzx ebx, word ptr [r15 + 4]
movzx rbx, r15b
movzx rbx, r15w
movzx rbx, byte ptr [r15 + 4]
movzx rbx, word ptr [r15 + 4]
; Source: r15, target: rsp
mov spl, 1
mov sp, 1
mov esp, 1
mov rsp, 1
mov spl, r15b
mov sp, r15w
mov esp, r15d
mov rsp, r15
mov spl, byte ptr [r15 - 4]
mov spl, byte ptr [r15 + 4]
mov sp, word ptr [r15 + 4]
mov esp, dword ptr [r15 + 4]
mov rsp, qword ptr [r15 + 4]
mov byte ptr [rsp - 4], r15b
mov byte ptr [rsp + 4], r15b
mov word ptr [rsp + 4], r15w
mov dword ptr [rsp + 4], r15d
mov qword ptr [rsp + 4], r15
movzx sp, r15b
movzx sp, byte ptr [r15 + 4]
movzx esp, r15b
movzx esp, r15w
movzx esp, byte ptr [r15 + 4]
movzx esp, word ptr [r15 + 4]
movzx rsp, r15b
movzx rsp, r15w
movzx rsp, byte ptr [r15 + 4]
movzx rsp, word ptr [r15 + 4]
; Source: r15, target: rbp
mov bpl, 1
mov bp, 1
mov ebp, 1
mov rbp, 1
mov bpl, r15b
mov bp, r15w
mov ebp, r15d
mov rbp, r15
mov bpl, byte ptr [r15 - 4]
mov bpl, byte ptr [r15 + 4]
mov bp, word ptr [r15 + 4]
mov ebp, dword ptr [r15 + 4]
mov rbp, qword ptr [r15 + 4]
mov byte ptr [rbp - 4], r15b
mov byte ptr [rbp + 4], r15b
mov word ptr [rbp + 4], r15w
mov dword ptr [rbp + 4], r15d
mov qword ptr [rbp + 4], r15
movzx bp, r15b
movzx bp, byte ptr [r15 + 4]
movzx ebp, r15b
movzx ebp, r15w
movzx ebp, byte ptr [r15 + 4]
movzx ebp, word ptr [r15 + 4]
movzx rbp, r15b
movzx rbp, r15w
movzx rbp, byte ptr [r15 + 4]
movzx rbp, word ptr [r15 + 4]
; Source: r15, target: rsi
mov dil, 1
mov si, 1
mov esi, 1
mov rsi, 1
mov dil, r15b
mov si, r15w
mov esi, r15d
mov rsi, r15
mov dil, byte ptr [r15 - 4]
mov dil, byte ptr [r15 + 4]
mov si, word ptr [r15 + 4]
mov esi, dword ptr [r15 + 4]
mov rsi, qword ptr [r15 + 4]
mov byte ptr [rsi - 4], r15b
mov byte ptr [rsi + 4], r15b
mov word ptr [rsi + 4], r15w
mov dword ptr [rsi + 4], r15d
mov qword ptr [rsi + 4], r15
movzx si, r15b
movzx si, byte ptr [r15 + 4]
movzx esi, r15b
movzx esi, r15w
movzx esi, byte ptr [r15 + 4]
movzx esi, word ptr [r15 + 4]
movzx rsi, r15b
movzx rsi, r15w
movzx rsi, byte ptr [r15 + 4]
movzx rsi, word ptr [r15 + 4]
; Source: r15, target: rdi
mov sil, 1
mov di, 1
mov edi, 1
mov rdi, 1
mov sil, r15b
mov di, r15w
mov edi, r15d
mov rdi, r15
mov sil, byte ptr [r15 - 4]
mov sil, byte ptr [r15 + 4]
mov di, word ptr [r15 + 4]
mov edi, dword ptr [r15 + 4]
mov rdi, qword ptr [r15 + 4]
mov byte ptr [rdi - 4], r15b
mov byte ptr [rdi + 4], r15b
mov word ptr [rdi + 4], r15w
mov dword ptr [rdi + 4], r15d
mov qword ptr [rdi + 4], r15
movzx di, r15b
movzx di, byte ptr [r15 + 4]
movzx edi, r15b
movzx edi, r15w
movzx edi, byte ptr [r15 + 4]
movzx edi, word ptr [r15 + 4]
movzx rdi, r15b
movzx rdi, r15w
movzx rdi, byte ptr [r15 + 4]
movzx rdi, word ptr [r15 + 4]
; Source: r15, target: r8
mov r8b, 1
mov r8w, 1
mov r8d, 1
mov r8, 1
mov r8b, r15b
mov r8w, r15w
mov r8d, r15d
mov r8, r15
mov r8b, byte ptr [r15 - 4]
mov r8b, byte ptr [r15 + 4]
mov r8w, word ptr [r15 + 4]
mov r8d, dword ptr [r15 + 4]
mov r8, qword ptr [r15 + 4]
mov byte ptr [r8 - 4], r15b
mov byte ptr [r8 + 4], r15b
mov word ptr [r8 + 4], r15w
mov dword ptr [r8 + 4], r15d
mov qword ptr [r8 + 4], r15
movzx r8w, r15b
movzx r8w, byte ptr [r15 + 4]
movzx r8d, r15b
movzx r8d, r15w
movzx r8d, byte ptr [r15 + 4]
movzx r8d, word ptr [r15 + 4]
movzx r8, r15b
movzx r8, r15w
movzx r8, byte ptr [r15 + 4]
movzx r8, word ptr [r15 + 4]
; Source: r15, target: r9
mov r9b, 1
mov r9w, 1
mov r9d, 1
mov r9, 1
mov r9b, r15b
mov r9w, r15w
mov r9d, r15d
mov r9, r15
mov r9b, byte ptr [r15 - 4]
mov r9b, byte ptr [r15 + 4]
mov r9w, word ptr [r15 + 4]
mov r9d, dword ptr [r15 + 4]
mov r9, qword ptr [r15 + 4]
mov byte ptr [r9 - 4], r15b
mov byte ptr [r9 + 4], r15b
mov word ptr [r9 + 4], r15w
mov dword ptr [r9 + 4], r15d
mov qword ptr [r9 + 4], r15
movzx r9w, r15b
movzx r9w, byte ptr [r15 + 4]
movzx r9d, r15b
movzx r9d, r15w
movzx r9d, byte ptr [r15 + 4]
movzx r9d, word ptr [r15 + 4]
movzx r9, r15b
movzx r9, r15w
movzx r9, byte ptr [r15 + 4]
movzx r9, word ptr [r15 + 4]
; Source: r15, target: r10
mov r10b, 1
mov r10w, 1
mov r10d, 1
mov r10, 1
mov r10b, r15b
mov r10w, r15w
mov r10d, r15d
mov r10, r15
mov r10b, byte ptr [r15 - 4]
mov r10b, byte ptr [r15 + 4]
mov r10w, word ptr [r15 + 4]
mov r10d, dword ptr [r15 + 4]
mov r10, qword ptr [r15 + 4]
mov byte ptr [r10 - 4], r15b
mov byte ptr [r10 + 4], r15b
mov word ptr [r10 + 4], r15w
mov dword ptr [r10 + 4], r15d
mov qword ptr [r10 + 4], r15
movzx r10w, r15b
movzx r10w, byte ptr [r15 + 4]
movzx r10d, r15b
movzx r10d, r15w
movzx r10d, byte ptr [r15 + 4]
movzx r10d, word ptr [r15 + 4]
movzx r10, r15b
movzx r10, r15w
movzx r10, byte ptr [r15 + 4]
movzx r10, word ptr [r15 + 4]
; Source: r15, target: r11
mov r11b, 1
mov r11w, 1
mov r11d, 1
mov r11, 1
mov r11b, r15b
mov r11w, r15w
mov r11d, r15d
mov r11, r15
mov r11b, byte ptr [r15 - 4]
mov r11b, byte ptr [r15 + 4]
mov r11w, word ptr [r15 + 4]
mov r11d, dword ptr [r15 + 4]
mov r11, qword ptr [r15 + 4]
mov byte ptr [r11 - 4], r15b
mov byte ptr [r11 + 4], r15b
mov word ptr [r11 + 4], r15w
mov dword ptr [r11 + 4], r15d
mov qword ptr [r11 + 4], r15
movzx r11w, r15b
movzx r11w, byte ptr [r15 + 4]
movzx r11d, r15b
movzx r11d, r15w
movzx r11d, byte ptr [r15 + 4]
movzx r11d, word ptr [r15 + 4]
movzx r11, r15b
movzx r11, r15w
movzx r11, byte ptr [r15 + 4]
movzx r11, word ptr [r15 + 4]
; Source: r15, target: r12
mov r12b, 1
mov r12w, 1
mov r12d, 1
mov r12, 1
mov r12b, r15b
mov r12w, r15w
mov r12d, r15d
mov r12, r15
mov r12b, byte ptr [r15 - 4]
mov r12b, byte ptr [r15 + 4]
mov r12w, word ptr [r15 + 4]
mov r12d, dword ptr [r15 + 4]
mov r12, qword ptr [r15 + 4]
mov byte ptr [r12 - 4], r15b
mov byte ptr [r12 + 4], r15b
mov word ptr [r12 + 4], r15w
mov dword ptr [r12 + 4], r15d
mov qword ptr [r12 + 4], r15
movzx r12w, r15b
movzx r12w, byte ptr [r15 + 4]
movzx r12d, r15b
movzx r12d, r15w
movzx r12d, byte ptr [r15 + 4]
movzx r12d, word ptr [r15 + 4]
movzx r12, r15b
movzx r12, r15w
movzx r12, byte ptr [r15 + 4]
movzx r12, word ptr [r15 + 4]
; Source: r15, target: r13
mov r13b, 1
mov r13w, 1
mov r13d, 1
mov r13, 1
mov r13b, r15b
mov r13w, r15w
mov r13d, r15d
mov r13, r15
mov r13b, byte ptr [r15 - 4]
mov r13b, byte ptr [r15 + 4]
mov r13w, word ptr [r15 + 4]
mov r13d, dword ptr [r15 + 4]
mov r13, qword ptr [r15 + 4]
mov byte ptr [r13 - 4], r15b
mov byte ptr [r13 + 4], r15b
mov word ptr [r13 + 4], r15w
mov dword ptr [r13 + 4], r15d
mov qword ptr [r13 + 4], r15
movzx r13w, r15b
movzx r13w, byte ptr [r15 + 4]
movzx r13d, r15b
movzx r13d, r15w
movzx r13d, byte ptr [r15 + 4]
movzx r13d, word ptr [r15 + 4]
movzx r13, r15b
movzx r13, r15w
movzx r13, byte ptr [r15 + 4]
movzx r13, word ptr [r15 + 4]
; Source: r15, target: r14
mov r14b, 1
mov r14w, 1
mov r14d, 1
mov r14, 1
mov r14b, r15b
mov r14w, r15w
mov r14d, r15d
mov r14, r15
mov r14b, byte ptr [r15 - 4]
mov r14b, byte ptr [r15 + 4]
mov r14w, word ptr [r15 + 4]
mov r14d, dword ptr [r15 + 4]
mov r14, qword ptr [r15 + 4]
mov byte ptr [r14 - 4], r15b
mov byte ptr [r14 + 4], r15b
mov word ptr [r14 + 4], r15w
mov dword ptr [r14 + 4], r15d
mov qword ptr [r14 + 4], r15
movzx r14w, r15b
movzx r14w, byte ptr [r15 + 4]
movzx r14d, r15b
movzx r14d, r15w
movzx r14d, byte ptr [r15 + 4]
movzx r14d, word ptr [r15 + 4]
movzx r14, r15b
movzx r14, r15w
movzx r14, byte ptr [r15 + 4]
movzx r14, word ptr [r15 + 4]
; Source: r15, target: r15
mov r15b, 1
mov r15w, 1
mov r15d, 1
mov r15, 1
mov r15b, r15b
mov r15w, r15w
mov r15d, r15d
mov r15, r15
mov r15b, byte ptr [r15 - 4]
mov r15b, byte ptr [r15 + 4]
mov r15w, word ptr [r15 + 4]
mov r15d, dword ptr [r15 + 4]
mov r15, qword ptr [r15 + 4]
mov byte ptr [r15 - 4], r15b
mov byte ptr [r15 + 4], r15b
mov word ptr [r15 + 4], r15w
mov dword ptr [r15 + 4], r15d
mov qword ptr [r15 + 4], r15
movzx r15w, r15b
movzx r15w, byte ptr [r15 + 4]
movzx r15d, r15b
movzx r15d, r15w
movzx r15d, byte ptr [r15 + 4]
movzx r15d, word ptr [r15 + 4]
movzx r15, r15b
movzx r15, r15w
movzx r15, byte ptr [r15 + 4]
movzx r15, word ptr [r15 + 4]
; Float <-> float
; Source: xmm0, target: xmm0
movss xmm0, xmm0
movsd xmm0, xmm0
cvtss2sd xmm0, xmm0
cvtsd2ss xmm0, xmm0
; Source: xmm0, target: xmm1
movss xmm1, xmm0
movsd xmm1, xmm0
cvtss2sd xmm1, xmm0
cvtsd2ss xmm1, xmm0
; Source: xmm0, target: xmm2
movss xmm2, xmm0
movsd xmm2, xmm0
cvtss2sd xmm2, xmm0
cvtsd2ss xmm2, xmm0
; Source: xmm0, target: xmm3
movss xmm3, xmm0
movsd xmm3, xmm0
cvtss2sd xmm3, xmm0
cvtsd2ss xmm3, xmm0
; Source: xmm0, target: xmm4
movss xmm4, xmm0
movsd xmm4, xmm0
cvtss2sd xmm4, xmm0
cvtsd2ss xmm4, xmm0
; Source: xmm0, target: xmm5
movss xmm5, xmm0
movsd xmm5, xmm0
cvtss2sd xmm5, xmm0
cvtsd2ss xmm5, xmm0
; Source: xmm0, target: xmm6
movss xmm6, xmm0
movsd xmm6, xmm0
cvtss2sd xmm6, xmm0
cvtsd2ss xmm6, xmm0
; Source: xmm0, target: xmm7
movss xmm7, xmm0
movsd xmm7, xmm0
cvtss2sd xmm7, xmm0
cvtsd2ss xmm7, xmm0
; Source: xmm0, target: xmm8
movss xmm8, xmm0
movsd xmm8, xmm0
cvtss2sd xmm8, xmm0
cvtsd2ss xmm8, xmm0
; Source: xmm0, target: xmm9
movss xmm9, xmm0
movsd xmm9, xmm0
cvtss2sd xmm9, xmm0
cvtsd2ss xmm9, xmm0
; Source: xmm0, target: xmm10
movss xmm10, xmm0
movsd xmm10, xmm0
cvtss2sd xmm10, xmm0
cvtsd2ss xmm10, xmm0
; Source: xmm0, target: xmm11
movss xmm11, xmm0
movsd xmm11, xmm0
cvtss2sd xmm11, xmm0
cvtsd2ss xmm11, xmm0
; Source: xmm0, target: xmm12
movss xmm12, xmm0
movsd xmm12, xmm0
cvtss2sd xmm12, xmm0
cvtsd2ss xmm12, xmm0
; Source: xmm0, target: xmm13
movss xmm13, xmm0
movsd xmm13, xmm0
cvtss2sd xmm13, xmm0
cvtsd2ss xmm13, xmm0
; Source: xmm0, target: xmm14
movss xmm14, xmm0
movsd xmm14, xmm0
cvtss2sd xmm14, xmm0
cvtsd2ss xmm14, xmm0
; Source: xmm0, target: xmm15
movss xmm15, xmm0
movsd xmm15, xmm0
cvtss2sd xmm15, xmm0
cvtsd2ss xmm15, xmm0
; Source: xmm1, target: xmm0
movss xmm0, xmm1
movsd xmm0, xmm1
cvtss2sd xmm0, xmm1
cvtsd2ss xmm0, xmm1
; Source: xmm1, target: xmm1
movss xmm1, xmm1
movsd xmm1, xmm1
cvtss2sd xmm1, xmm1
cvtsd2ss xmm1, xmm1
; Source: xmm1, target: xmm2
movss xmm2, xmm1
movsd xmm2, xmm1
cvtss2sd xmm2, xmm1
cvtsd2ss xmm2, xmm1
; Source: xmm1, target: xmm3
movss xmm3, xmm1
movsd xmm3, xmm1
cvtss2sd xmm3, xmm1
cvtsd2ss xmm3, xmm1
; Source: xmm1, target: xmm4
movss xmm4, xmm1
movsd xmm4, xmm1
cvtss2sd xmm4, xmm1
cvtsd2ss xmm4, xmm1
; Source: xmm1, target: xmm5
movss xmm5, xmm1
movsd xmm5, xmm1
cvtss2sd xmm5, xmm1
cvtsd2ss xmm5, xmm1
; Source: xmm1, target: xmm6
movss xmm6, xmm1
movsd xmm6, xmm1
cvtss2sd xmm6, xmm1
cvtsd2ss xmm6, xmm1
; Source: xmm1, target: xmm7
movss xmm7, xmm1
movsd xmm7, xmm1
cvtss2sd xmm7, xmm1
cvtsd2ss xmm7, xmm1
; Source: xmm1, target: xmm8
movss xmm8, xmm1
movsd xmm8, xmm1
cvtss2sd xmm8, xmm1
cvtsd2ss xmm8, xmm1
; Source: xmm1, target: xmm9
movss xmm9, xmm1
movsd xmm9, xmm1
cvtss2sd xmm9, xmm1
cvtsd2ss xmm9, xmm1
; Source: xmm1, target: xmm10
movss xmm10, xmm1
movsd xmm10, xmm1
cvtss2sd xmm10, xmm1
cvtsd2ss xmm10, xmm1
; Source: xmm1, target: xmm11
movss xmm11, xmm1
movsd xmm11, xmm1
cvtss2sd xmm11, xmm1
cvtsd2ss xmm11, xmm1
; Source: xmm1, target: xmm12
movss xmm12, xmm1
movsd xmm12, xmm1
cvtss2sd xmm12, xmm1
cvtsd2ss xmm12, xmm1
; Source: xmm1, target: xmm13
movss xmm13, xmm1
movsd xmm13, xmm1
cvtss2sd xmm13, xmm1
cvtsd2ss xmm13, xmm1
; Source: xmm1, target: xmm14
movss xmm14, xmm1
movsd xmm14, xmm1
cvtss2sd xmm14, xmm1
cvtsd2ss xmm14, xmm1
; Source: xmm1, target: xmm15
movss xmm15, xmm1
movsd xmm15, xmm1
cvtss2sd xmm15, xmm1
cvtsd2ss xmm15, xmm1
; Source: xmm2, target: xmm0
movss xmm0, xmm2
movsd xmm0, xmm2
cvtss2sd xmm0, xmm2
cvtsd2ss xmm0, xmm2
; Source: xmm2, target: xmm1
movss xmm1, xmm2
movsd xmm1, xmm2
cvtss2sd xmm1, xmm2
cvtsd2ss xmm1, xmm2
; Source: xmm2, target: xmm2
movss xmm2, xmm2
movsd xmm2, xmm2
cvtss2sd xmm2, xmm2
cvtsd2ss xmm2, xmm2
; Source: xmm2, target: xmm3
movss xmm3, xmm2
movsd xmm3, xmm2
cvtss2sd xmm3, xmm2
cvtsd2ss xmm3, xmm2
; Source: xmm2, target: xmm4
movss xmm4, xmm2
movsd xmm4, xmm2
cvtss2sd xmm4, xmm2
cvtsd2ss xmm4, xmm2
; Source: xmm2, target: xmm5
movss xmm5, xmm2
movsd xmm5, xmm2
cvtss2sd xmm5, xmm2
cvtsd2ss xmm5, xmm2
; Source: xmm2, target: xmm6
movss xmm6, xmm2
movsd xmm6, xmm2
cvtss2sd xmm6, xmm2
cvtsd2ss xmm6, xmm2
; Source: xmm2, target: xmm7
movss xmm7, xmm2
movsd xmm7, xmm2
cvtss2sd xmm7, xmm2
cvtsd2ss xmm7, xmm2
; Source: xmm2, target: xmm8
movss xmm8, xmm2
movsd xmm8, xmm2
cvtss2sd xmm8, xmm2
cvtsd2ss xmm8, xmm2
; Source: xmm2, target: xmm9
movss xmm9, xmm2
movsd xmm9, xmm2
cvtss2sd xmm9, xmm2
cvtsd2ss xmm9, xmm2
; Source: xmm2, target: xmm10
movss xmm10, xmm2
movsd xmm10, xmm2
cvtss2sd xmm10, xmm2
cvtsd2ss xmm10, xmm2
; Source: xmm2, target: xmm11
movss xmm11, xmm2
movsd xmm11, xmm2
cvtss2sd xmm11, xmm2
cvtsd2ss xmm11, xmm2
; Source: xmm2, target: xmm12
movss xmm12, xmm2
movsd xmm12, xmm2
cvtss2sd xmm12, xmm2
cvtsd2ss xmm12, xmm2
; Source: xmm2, target: xmm13
movss xmm13, xmm2
movsd xmm13, xmm2
cvtss2sd xmm13, xmm2
cvtsd2ss xmm13, xmm2
; Source: xmm2, target: xmm14
movss xmm14, xmm2
movsd xmm14, xmm2
cvtss2sd xmm14, xmm2
cvtsd2ss xmm14, xmm2
; Source: xmm2, target: xmm15
movss xmm15, xmm2
movsd xmm15, xmm2
cvtss2sd xmm15, xmm2
cvtsd2ss xmm15, xmm2
; Source: xmm3, target: xmm0
movss xmm0, xmm3
movsd xmm0, xmm3
cvtss2sd xmm0, xmm3
cvtsd2ss xmm0, xmm3
; Source: xmm3, target: xmm1
movss xmm1, xmm3
movsd xmm1, xmm3
cvtss2sd xmm1, xmm3
cvtsd2ss xmm1, xmm3
; Source: xmm3, target: xmm2
movss xmm2, xmm3
movsd xmm2, xmm3
cvtss2sd xmm2, xmm3
cvtsd2ss xmm2, xmm3
; Source: xmm3, target: xmm3
movss xmm3, xmm3
movsd xmm3, xmm3
cvtss2sd xmm3, xmm3
cvtsd2ss xmm3, xmm3
; Source: xmm3, target: xmm4
movss xmm4, xmm3
movsd xmm4, xmm3
cvtss2sd xmm4, xmm3
cvtsd2ss xmm4, xmm3
; Source: xmm3, target: xmm5
movss xmm5, xmm3
movsd xmm5, xmm3
cvtss2sd xmm5, xmm3
cvtsd2ss xmm5, xmm3
; Source: xmm3, target: xmm6
movss xmm6, xmm3
movsd xmm6, xmm3
cvtss2sd xmm6, xmm3
cvtsd2ss xmm6, xmm3
; Source: xmm3, target: xmm7
movss xmm7, xmm3
movsd xmm7, xmm3
cvtss2sd xmm7, xmm3
cvtsd2ss xmm7, xmm3
; Source: xmm3, target: xmm8
movss xmm8, xmm3
movsd xmm8, xmm3
cvtss2sd xmm8, xmm3
cvtsd2ss xmm8, xmm3
; Source: xmm3, target: xmm9
movss xmm9, xmm3
movsd xmm9, xmm3
cvtss2sd xmm9, xmm3
cvtsd2ss xmm9, xmm3
; Source: xmm3, target: xmm10
movss xmm10, xmm3
movsd xmm10, xmm3
cvtss2sd xmm10, xmm3
cvtsd2ss xmm10, xmm3
; Source: xmm3, target: xmm11
movss xmm11, xmm3
movsd xmm11, xmm3
cvtss2sd xmm11, xmm3
cvtsd2ss xmm11, xmm3
; Source: xmm3, target: xmm12
movss xmm12, xmm3
movsd xmm12, xmm3
cvtss2sd xmm12, xmm3
cvtsd2ss xmm12, xmm3
; Source: xmm3, target: xmm13
movss xmm13, xmm3
movsd xmm13, xmm3
cvtss2sd xmm13, xmm3
cvtsd2ss xmm13, xmm3
; Source: xmm3, target: xmm14
movss xmm14, xmm3
movsd xmm14, xmm3
cvtss2sd xmm14, xmm3
cvtsd2ss xmm14, xmm3
; Source: xmm3, target: xmm15
movss xmm15, xmm3
movsd xmm15, xmm3
cvtss2sd xmm15, xmm3
cvtsd2ss xmm15, xmm3
; Source: xmm4, target: xmm0
movss xmm0, xmm4
movsd xmm0, xmm4
cvtss2sd xmm0, xmm4
cvtsd2ss xmm0, xmm4
; Source: xmm4, target: xmm1
movss xmm1, xmm4
movsd xmm1, xmm4
cvtss2sd xmm1, xmm4
cvtsd2ss xmm1, xmm4
; Source: xmm4, target: xmm2
movss xmm2, xmm4
movsd xmm2, xmm4
cvtss2sd xmm2, xmm4
cvtsd2ss xmm2, xmm4
; Source: xmm4, target: xmm3
movss xmm3, xmm4
movsd xmm3, xmm4
cvtss2sd xmm3, xmm4
cvtsd2ss xmm3, xmm4
; Source: xmm4, target: xmm4
movss xmm4, xmm4
movsd xmm4, xmm4
cvtss2sd xmm4, xmm4
cvtsd2ss xmm4, xmm4
; Source: xmm4, target: xmm5
movss xmm5, xmm4
movsd xmm5, xmm4
cvtss2sd xmm5, xmm4
cvtsd2ss xmm5, xmm4
; Source: xmm4, target: xmm6
movss xmm6, xmm4
movsd xmm6, xmm4
cvtss2sd xmm6, xmm4
cvtsd2ss xmm6, xmm4
; Source: xmm4, target: xmm7
movss xmm7, xmm4
movsd xmm7, xmm4
cvtss2sd xmm7, xmm4
cvtsd2ss xmm7, xmm4
; Source: xmm4, target: xmm8
movss xmm8, xmm4
movsd xmm8, xmm4
cvtss2sd xmm8, xmm4
cvtsd2ss xmm8, xmm4
; Source: xmm4, target: xmm9
movss xmm9, xmm4
movsd xmm9, xmm4
cvtss2sd xmm9, xmm4
cvtsd2ss xmm9, xmm4
; Source: xmm4, target: xmm10
movss xmm10, xmm4
movsd xmm10, xmm4
cvtss2sd xmm10, xmm4
cvtsd2ss xmm10, xmm4
; Source: xmm4, target: xmm11
movss xmm11, xmm4
movsd xmm11, xmm4
cvtss2sd xmm11, xmm4
cvtsd2ss xmm11, xmm4
; Source: xmm4, target: xmm12
movss xmm12, xmm4
movsd xmm12, xmm4
cvtss2sd xmm12, xmm4
cvtsd2ss xmm12, xmm4
; Source: xmm4, target: xmm13
movss xmm13, xmm4
movsd xmm13, xmm4
cvtss2sd xmm13, xmm4
cvtsd2ss xmm13, xmm4
; Source: xmm4, target: xmm14
movss xmm14, xmm4
movsd xmm14, xmm4
cvtss2sd xmm14, xmm4
cvtsd2ss xmm14, xmm4
; Source: xmm4, target: xmm15
movss xmm15, xmm4
movsd xmm15, xmm4
cvtss2sd xmm15, xmm4
cvtsd2ss xmm15, xmm4
; Source: xmm5, target: xmm0
movss xmm0, xmm5
movsd xmm0, xmm5
cvtss2sd xmm0, xmm5
cvtsd2ss xmm0, xmm5
; Source: xmm5, target: xmm1
movss xmm1, xmm5
movsd xmm1, xmm5
cvtss2sd xmm1, xmm5
cvtsd2ss xmm1, xmm5
; Source: xmm5, target: xmm2
movss xmm2, xmm5
movsd xmm2, xmm5
cvtss2sd xmm2, xmm5
cvtsd2ss xmm2, xmm5
; Source: xmm5, target: xmm3
movss xmm3, xmm5
movsd xmm3, xmm5
cvtss2sd xmm3, xmm5
cvtsd2ss xmm3, xmm5
; Source: xmm5, target: xmm4
movss xmm4, xmm5
movsd xmm4, xmm5
cvtss2sd xmm4, xmm5
cvtsd2ss xmm4, xmm5
; Source: xmm5, target: xmm5
movss xmm5, xmm5
movsd xmm5, xmm5
cvtss2sd xmm5, xmm5
cvtsd2ss xmm5, xmm5
; Source: xmm5, target: xmm6
movss xmm6, xmm5
movsd xmm6, xmm5
cvtss2sd xmm6, xmm5
cvtsd2ss xmm6, xmm5
; Source: xmm5, target: xmm7
movss xmm7, xmm5
movsd xmm7, xmm5
cvtss2sd xmm7, xmm5
cvtsd2ss xmm7, xmm5
; Source: xmm5, target: xmm8
movss xmm8, xmm5
movsd xmm8, xmm5
cvtss2sd xmm8, xmm5
cvtsd2ss xmm8, xmm5
; Source: xmm5, target: xmm9
movss xmm9, xmm5
movsd xmm9, xmm5
cvtss2sd xmm9, xmm5
cvtsd2ss xmm9, xmm5
; Source: xmm5, target: xmm10
movss xmm10, xmm5
movsd xmm10, xmm5
cvtss2sd xmm10, xmm5
cvtsd2ss xmm10, xmm5
; Source: xmm5, target: xmm11
movss xmm11, xmm5
movsd xmm11, xmm5
cvtss2sd xmm11, xmm5
cvtsd2ss xmm11, xmm5
; Source: xmm5, target: xmm12
movss xmm12, xmm5
movsd xmm12, xmm5
cvtss2sd xmm12, xmm5
cvtsd2ss xmm12, xmm5
; Source: xmm5, target: xmm13
movss xmm13, xmm5
movsd xmm13, xmm5
cvtss2sd xmm13, xmm5
cvtsd2ss xmm13, xmm5
; Source: xmm5, target: xmm14
movss xmm14, xmm5
movsd xmm14, xmm5
cvtss2sd xmm14, xmm5
cvtsd2ss xmm14, xmm5
; Source: xmm5, target: xmm15
movss xmm15, xmm5
movsd xmm15, xmm5
cvtss2sd xmm15, xmm5
cvtsd2ss xmm15, xmm5
; Source: xmm6, target: xmm0
movss xmm0, xmm6
movsd xmm0, xmm6
cvtss2sd xmm0, xmm6
cvtsd2ss xmm0, xmm6
; Source: xmm6, target: xmm1
movss xmm1, xmm6
movsd xmm1, xmm6
cvtss2sd xmm1, xmm6
cvtsd2ss xmm1, xmm6
; Source: xmm6, target: xmm2
movss xmm2, xmm6
movsd xmm2, xmm6
cvtss2sd xmm2, xmm6
cvtsd2ss xmm2, xmm6
; Source: xmm6, target: xmm3
movss xmm3, xmm6
movsd xmm3, xmm6
cvtss2sd xmm3, xmm6
cvtsd2ss xmm3, xmm6
; Source: xmm6, target: xmm4
movss xmm4, xmm6
movsd xmm4, xmm6
cvtss2sd xmm4, xmm6
cvtsd2ss xmm4, xmm6
; Source: xmm6, target: xmm5
movss xmm5, xmm6
movsd xmm5, xmm6
cvtss2sd xmm5, xmm6
cvtsd2ss xmm5, xmm6
; Source: xmm6, target: xmm6
movss xmm6, xmm6
movsd xmm6, xmm6
cvtss2sd xmm6, xmm6
cvtsd2ss xmm6, xmm6
; Source: xmm6, target: xmm7
movss xmm7, xmm6
movsd xmm7, xmm6
cvtss2sd xmm7, xmm6
cvtsd2ss xmm7, xmm6
; Source: xmm6, target: xmm8
movss xmm8, xmm6
movsd xmm8, xmm6
cvtss2sd xmm8, xmm6
cvtsd2ss xmm8, xmm6
; Source: xmm6, target: xmm9
movss xmm9, xmm6
movsd xmm9, xmm6
cvtss2sd xmm9, xmm6
cvtsd2ss xmm9, xmm6
; Source: xmm6, target: xmm10
movss xmm10, xmm6
movsd xmm10, xmm6
cvtss2sd xmm10, xmm6
cvtsd2ss xmm10, xmm6
; Source: xmm6, target: xmm11
movss xmm11, xmm6
movsd xmm11, xmm6
cvtss2sd xmm11, xmm6
cvtsd2ss xmm11, xmm6
; Source: xmm6, target: xmm12
movss xmm12, xmm6
movsd xmm12, xmm6
cvtss2sd xmm12, xmm6
cvtsd2ss xmm12, xmm6
; Source: xmm6, target: xmm13
movss xmm13, xmm6
movsd xmm13, xmm6
cvtss2sd xmm13, xmm6
cvtsd2ss xmm13, xmm6
; Source: xmm6, target: xmm14
movss xmm14, xmm6
movsd xmm14, xmm6
cvtss2sd xmm14, xmm6
cvtsd2ss xmm14, xmm6
; Source: xmm6, target: xmm15
movss xmm15, xmm6
movsd xmm15, xmm6
cvtss2sd xmm15, xmm6
cvtsd2ss xmm15, xmm6
; Source: xmm7, target: xmm0
movss xmm0, xmm7
movsd xmm0, xmm7
cvtss2sd xmm0, xmm7
cvtsd2ss xmm0, xmm7
; Source: xmm7, target: xmm1
movss xmm1, xmm7
movsd xmm1, xmm7
cvtss2sd xmm1, xmm7
cvtsd2ss xmm1, xmm7
; Source: xmm7, target: xmm2
movss xmm2, xmm7
movsd xmm2, xmm7
cvtss2sd xmm2, xmm7
cvtsd2ss xmm2, xmm7
; Source: xmm7, target: xmm3
movss xmm3, xmm7
movsd xmm3, xmm7
cvtss2sd xmm3, xmm7
cvtsd2ss xmm3, xmm7
; Source: xmm7, target: xmm4
movss xmm4, xmm7
movsd xmm4, xmm7
cvtss2sd xmm4, xmm7
cvtsd2ss xmm4, xmm7
; Source: xmm7, target: xmm5
movss xmm5, xmm7
movsd xmm5, xmm7
cvtss2sd xmm5, xmm7
cvtsd2ss xmm5, xmm7
; Source: xmm7, target: xmm6
movss xmm6, xmm7
movsd xmm6, xmm7
cvtss2sd xmm6, xmm7
cvtsd2ss xmm6, xmm7
; Source: xmm7, target: xmm7
movss xmm7, xmm7
movsd xmm7, xmm7
cvtss2sd xmm7, xmm7
cvtsd2ss xmm7, xmm7
; Source: xmm7, target: xmm8
movss xmm8, xmm7
movsd xmm8, xmm7
cvtss2sd xmm8, xmm7
cvtsd2ss xmm8, xmm7
; Source: xmm7, target: xmm9
movss xmm9, xmm7
movsd xmm9, xmm7
cvtss2sd xmm9, xmm7
cvtsd2ss xmm9, xmm7
; Source: xmm7, target: xmm10
movss xmm10, xmm7
movsd xmm10, xmm7
cvtss2sd xmm10, xmm7
cvtsd2ss xmm10, xmm7
; Source: xmm7, target: xmm11
movss xmm11, xmm7
movsd xmm11, xmm7
cvtss2sd xmm11, xmm7
cvtsd2ss xmm11, xmm7
; Source: xmm7, target: xmm12
movss xmm12, xmm7
movsd xmm12, xmm7
cvtss2sd xmm12, xmm7
cvtsd2ss xmm12, xmm7
; Source: xmm7, target: xmm13
movss xmm13, xmm7
movsd xmm13, xmm7
cvtss2sd xmm13, xmm7
cvtsd2ss xmm13, xmm7
; Source: xmm7, target: xmm14
movss xmm14, xmm7
movsd xmm14, xmm7
cvtss2sd xmm14, xmm7
cvtsd2ss xmm14, xmm7
; Source: xmm7, target: xmm15
movss xmm15, xmm7
movsd xmm15, xmm7
cvtss2sd xmm15, xmm7
cvtsd2ss xmm15, xmm7
; Source: xmm8, target: xmm0
movss xmm0, xmm8
movsd xmm0, xmm8
cvtss2sd xmm0, xmm8
cvtsd2ss xmm0, xmm8
; Source: xmm8, target: xmm1
movss xmm1, xmm8
movsd xmm1, xmm8
cvtss2sd xmm1, xmm8
cvtsd2ss xmm1, xmm8
; Source: xmm8, target: xmm2
movss xmm2, xmm8
movsd xmm2, xmm8
cvtss2sd xmm2, xmm8
cvtsd2ss xmm2, xmm8
; Source: xmm8, target: xmm3
movss xmm3, xmm8
movsd xmm3, xmm8
cvtss2sd xmm3, xmm8
cvtsd2ss xmm3, xmm8
; Source: xmm8, target: xmm4
movss xmm4, xmm8
movsd xmm4, xmm8
cvtss2sd xmm4, xmm8
cvtsd2ss xmm4, xmm8
; Source: xmm8, target: xmm5
movss xmm5, xmm8
movsd xmm5, xmm8
cvtss2sd xmm5, xmm8
cvtsd2ss xmm5, xmm8
; Source: xmm8, target: xmm6
movss xmm6, xmm8
movsd xmm6, xmm8
cvtss2sd xmm6, xmm8
cvtsd2ss xmm6, xmm8
; Source: xmm8, target: xmm7
movss xmm7, xmm8
movsd xmm7, xmm8
cvtss2sd xmm7, xmm8
cvtsd2ss xmm7, xmm8
; Source: xmm8, target: xmm8
movss xmm8, xmm8
movsd xmm8, xmm8
cvtss2sd xmm8, xmm8
cvtsd2ss xmm8, xmm8
; Source: xmm8, target: xmm9
movss xmm9, xmm8
movsd xmm9, xmm8
cvtss2sd xmm9, xmm8
cvtsd2ss xmm9, xmm8
; Source: xmm8, target: xmm10
movss xmm10, xmm8
movsd xmm10, xmm8
cvtss2sd xmm10, xmm8
cvtsd2ss xmm10, xmm8
; Source: xmm8, target: xmm11
movss xmm11, xmm8
movsd xmm11, xmm8
cvtss2sd xmm11, xmm8
cvtsd2ss xmm11, xmm8
; Source: xmm8, target: xmm12
movss xmm12, xmm8
movsd xmm12, xmm8
cvtss2sd xmm12, xmm8
cvtsd2ss xmm12, xmm8
; Source: xmm8, target: xmm13
movss xmm13, xmm8
movsd xmm13, xmm8
cvtss2sd xmm13, xmm8
cvtsd2ss xmm13, xmm8
; Source: xmm8, target: xmm14
movss xmm14, xmm8
movsd xmm14, xmm8
cvtss2sd xmm14, xmm8
cvtsd2ss xmm14, xmm8
; Source: xmm8, target: xmm15
movss xmm15, xmm8
movsd xmm15, xmm8
cvtss2sd xmm15, xmm8
cvtsd2ss xmm15, xmm8
; Source: xmm9, target: xmm0
movss xmm0, xmm9
movsd xmm0, xmm9
cvtss2sd xmm0, xmm9
cvtsd2ss xmm0, xmm9
; Source: xmm9, target: xmm1
movss xmm1, xmm9
movsd xmm1, xmm9
cvtss2sd xmm1, xmm9
cvtsd2ss xmm1, xmm9
; Source: xmm9, target: xmm2
movss xmm2, xmm9
movsd xmm2, xmm9
cvtss2sd xmm2, xmm9
cvtsd2ss xmm2, xmm9
; Source: xmm9, target: xmm3
movss xmm3, xmm9
movsd xmm3, xmm9
cvtss2sd xmm3, xmm9
cvtsd2ss xmm3, xmm9
; Source: xmm9, target: xmm4
movss xmm4, xmm9
movsd xmm4, xmm9
cvtss2sd xmm4, xmm9
cvtsd2ss xmm4, xmm9
; Source: xmm9, target: xmm5
movss xmm5, xmm9
movsd xmm5, xmm9
cvtss2sd xmm5, xmm9
cvtsd2ss xmm5, xmm9
; Source: xmm9, target: xmm6
movss xmm6, xmm9
movsd xmm6, xmm9
cvtss2sd xmm6, xmm9
cvtsd2ss xmm6, xmm9
; Source: xmm9, target: xmm7
movss xmm7, xmm9
movsd xmm7, xmm9
cvtss2sd xmm7, xmm9
cvtsd2ss xmm7, xmm9
; Source: xmm9, target: xmm8
movss xmm8, xmm9
movsd xmm8, xmm9
cvtss2sd xmm8, xmm9
cvtsd2ss xmm8, xmm9
; Source: xmm9, target: xmm9
movss xmm9, xmm9
movsd xmm9, xmm9
cvtss2sd xmm9, xmm9
cvtsd2ss xmm9, xmm9
; Source: xmm9, target: xmm10
movss xmm10, xmm9
movsd xmm10, xmm9
cvtss2sd xmm10, xmm9
cvtsd2ss xmm10, xmm9
; Source: xmm9, target: xmm11
movss xmm11, xmm9
movsd xmm11, xmm9
cvtss2sd xmm11, xmm9
cvtsd2ss xmm11, xmm9
; Source: xmm9, target: xmm12
movss xmm12, xmm9
movsd xmm12, xmm9
cvtss2sd xmm12, xmm9
cvtsd2ss xmm12, xmm9
; Source: xmm9, target: xmm13
movss xmm13, xmm9
movsd xmm13, xmm9
cvtss2sd xmm13, xmm9
cvtsd2ss xmm13, xmm9
; Source: xmm9, target: xmm14
movss xmm14, xmm9
movsd xmm14, xmm9
cvtss2sd xmm14, xmm9
cvtsd2ss xmm14, xmm9
; Source: xmm9, target: xmm15
movss xmm15, xmm9
movsd xmm15, xmm9
cvtss2sd xmm15, xmm9
cvtsd2ss xmm15, xmm9
; Source: xmm10, target: xmm0
movss xmm0, xmm10
movsd xmm0, xmm10
cvtss2sd xmm0, xmm10
cvtsd2ss xmm0, xmm10
; Source: xmm10, target: xmm1
movss xmm1, xmm10
movsd xmm1, xmm10
cvtss2sd xmm1, xmm10
cvtsd2ss xmm1, xmm10
; Source: xmm10, target: xmm2
movss xmm2, xmm10
movsd xmm2, xmm10
cvtss2sd xmm2, xmm10
cvtsd2ss xmm2, xmm10
; Source: xmm10, target: xmm3
movss xmm3, xmm10
movsd xmm3, xmm10
cvtss2sd xmm3, xmm10
cvtsd2ss xmm3, xmm10
; Source: xmm10, target: xmm4
movss xmm4, xmm10
movsd xmm4, xmm10
cvtss2sd xmm4, xmm10
cvtsd2ss xmm4, xmm10
; Source: xmm10, target: xmm5
movss xmm5, xmm10
movsd xmm5, xmm10
cvtss2sd xmm5, xmm10
cvtsd2ss xmm5, xmm10
; Source: xmm10, target: xmm6
movss xmm6, xmm10
movsd xmm6, xmm10
cvtss2sd xmm6, xmm10
cvtsd2ss xmm6, xmm10
; Source: xmm10, target: xmm7
movss xmm7, xmm10
movsd xmm7, xmm10
cvtss2sd xmm7, xmm10
cvtsd2ss xmm7, xmm10
; Source: xmm10, target: xmm8
movss xmm8, xmm10
movsd xmm8, xmm10
cvtss2sd xmm8, xmm10
cvtsd2ss xmm8, xmm10
; Source: xmm10, target: xmm9
movss xmm9, xmm10
movsd xmm9, xmm10
cvtss2sd xmm9, xmm10
cvtsd2ss xmm9, xmm10
; Source: xmm10, target: xmm10
movss xmm10, xmm10
movsd xmm10, xmm10
cvtss2sd xmm10, xmm10
cvtsd2ss xmm10, xmm10
; Source: xmm10, target: xmm11
movss xmm11, xmm10
movsd xmm11, xmm10
cvtss2sd xmm11, xmm10
cvtsd2ss xmm11, xmm10
; Source: xmm10, target: xmm12
movss xmm12, xmm10
movsd xmm12, xmm10
cvtss2sd xmm12, xmm10
cvtsd2ss xmm12, xmm10
; Source: xmm10, target: xmm13
movss xmm13, xmm10
movsd xmm13, xmm10
cvtss2sd xmm13, xmm10
cvtsd2ss xmm13, xmm10
; Source: xmm10, target: xmm14
movss xmm14, xmm10
movsd xmm14, xmm10
cvtss2sd xmm14, xmm10
cvtsd2ss xmm14, xmm10
; Source: xmm10, target: xmm15
movss xmm15, xmm10
movsd xmm15, xmm10
cvtss2sd xmm15, xmm10
cvtsd2ss xmm15, xmm10
; Source: xmm11, target: xmm0
movss xmm0, xmm11
movsd xmm0, xmm11
cvtss2sd xmm0, xmm11
cvtsd2ss xmm0, xmm11
; Source: xmm11, target: xmm1
movss xmm1, xmm11
movsd xmm1, xmm11
cvtss2sd xmm1, xmm11
cvtsd2ss xmm1, xmm11
; Source: xmm11, target: xmm2
movss xmm2, xmm11
movsd xmm2, xmm11
cvtss2sd xmm2, xmm11
cvtsd2ss xmm2, xmm11
; Source: xmm11, target: xmm3
movss xmm3, xmm11
movsd xmm3, xmm11
cvtss2sd xmm3, xmm11
cvtsd2ss xmm3, xmm11
; Source: xmm11, target: xmm4
movss xmm4, xmm11
movsd xmm4, xmm11
cvtss2sd xmm4, xmm11
cvtsd2ss xmm4, xmm11
; Source: xmm11, target: xmm5
movss xmm5, xmm11
movsd xmm5, xmm11
cvtss2sd xmm5, xmm11
cvtsd2ss xmm5, xmm11
; Source: xmm11, target: xmm6
movss xmm6, xmm11
movsd xmm6, xmm11
cvtss2sd xmm6, xmm11
cvtsd2ss xmm6, xmm11
; Source: xmm11, target: xmm7
movss xmm7, xmm11
movsd xmm7, xmm11
cvtss2sd xmm7, xmm11
cvtsd2ss xmm7, xmm11
; Source: xmm11, target: xmm8
movss xmm8, xmm11
movsd xmm8, xmm11
cvtss2sd xmm8, xmm11
cvtsd2ss xmm8, xmm11
; Source: xmm11, target: xmm9
movss xmm9, xmm11
movsd xmm9, xmm11
cvtss2sd xmm9, xmm11
cvtsd2ss xmm9, xmm11
; Source: xmm11, target: xmm10
movss xmm10, xmm11
movsd xmm10, xmm11
cvtss2sd xmm10, xmm11
cvtsd2ss xmm10, xmm11
; Source: xmm11, target: xmm11
movss xmm11, xmm11
movsd xmm11, xmm11
cvtss2sd xmm11, xmm11
cvtsd2ss xmm11, xmm11
; Source: xmm11, target: xmm12
movss xmm12, xmm11
movsd xmm12, xmm11
cvtss2sd xmm12, xmm11
cvtsd2ss xmm12, xmm11
; Source: xmm11, target: xmm13
movss xmm13, xmm11
movsd xmm13, xmm11
cvtss2sd xmm13, xmm11
cvtsd2ss xmm13, xmm11
; Source: xmm11, target: xmm14
movss xmm14, xmm11
movsd xmm14, xmm11
cvtss2sd xmm14, xmm11
cvtsd2ss xmm14, xmm11
; Source: xmm11, target: xmm15
movss xmm15, xmm11
movsd xmm15, xmm11
cvtss2sd xmm15, xmm11
cvtsd2ss xmm15, xmm11
; Source: xmm12, target: xmm0
movss xmm0, xmm12
movsd xmm0, xmm12
cvtss2sd xmm0, xmm12
cvtsd2ss xmm0, xmm12
; Source: xmm12, target: xmm1
movss xmm1, xmm12
movsd xmm1, xmm12
cvtss2sd xmm1, xmm12
cvtsd2ss xmm1, xmm12
; Source: xmm12, target: xmm2
movss xmm2, xmm12
movsd xmm2, xmm12
cvtss2sd xmm2, xmm12
cvtsd2ss xmm2, xmm12
; Source: xmm12, target: xmm3
movss xmm3, xmm12
movsd xmm3, xmm12
cvtss2sd xmm3, xmm12
cvtsd2ss xmm3, xmm12
; Source: xmm12, target: xmm4
movss xmm4, xmm12
movsd xmm4, xmm12
cvtss2sd xmm4, xmm12
cvtsd2ss xmm4, xmm12
; Source: xmm12, target: xmm5
movss xmm5, xmm12
movsd xmm5, xmm12
cvtss2sd xmm5, xmm12
cvtsd2ss xmm5, xmm12
; Source: xmm12, target: xmm6
movss xmm6, xmm12
movsd xmm6, xmm12
cvtss2sd xmm6, xmm12
cvtsd2ss xmm6, xmm12
; Source: xmm12, target: xmm7
movss xmm7, xmm12
movsd xmm7, xmm12
cvtss2sd xmm7, xmm12
cvtsd2ss xmm7, xmm12
; Source: xmm12, target: xmm8
movss xmm8, xmm12
movsd xmm8, xmm12
cvtss2sd xmm8, xmm12
cvtsd2ss xmm8, xmm12
; Source: xmm12, target: xmm9
movss xmm9, xmm12
movsd xmm9, xmm12
cvtss2sd xmm9, xmm12
cvtsd2ss xmm9, xmm12
; Source: xmm12, target: xmm10
movss xmm10, xmm12
movsd xmm10, xmm12
cvtss2sd xmm10, xmm12
cvtsd2ss xmm10, xmm12
; Source: xmm12, target: xmm11
movss xmm11, xmm12
movsd xmm11, xmm12
cvtss2sd xmm11, xmm12
cvtsd2ss xmm11, xmm12
; Source: xmm12, target: xmm12
movss xmm12, xmm12
movsd xmm12, xmm12
cvtss2sd xmm12, xmm12
cvtsd2ss xmm12, xmm12
; Source: xmm12, target: xmm13
movss xmm13, xmm12
movsd xmm13, xmm12
cvtss2sd xmm13, xmm12
cvtsd2ss xmm13, xmm12
; Source: xmm12, target: xmm14
movss xmm14, xmm12
movsd xmm14, xmm12
cvtss2sd xmm14, xmm12
cvtsd2ss xmm14, xmm12
; Source: xmm12, target: xmm15
movss xmm15, xmm12
movsd xmm15, xmm12
cvtss2sd xmm15, xmm12
cvtsd2ss xmm15, xmm12
; Source: xmm13, target: xmm0
movss xmm0, xmm13
movsd xmm0, xmm13
cvtss2sd xmm0, xmm13
cvtsd2ss xmm0, xmm13
; Source: xmm13, target: xmm1
movss xmm1, xmm13
movsd xmm1, xmm13
cvtss2sd xmm1, xmm13
cvtsd2ss xmm1, xmm13
; Source: xmm13, target: xmm2
movss xmm2, xmm13
movsd xmm2, xmm13
cvtss2sd xmm2, xmm13
cvtsd2ss xmm2, xmm13
; Source: xmm13, target: xmm3
movss xmm3, xmm13
movsd xmm3, xmm13
cvtss2sd xmm3, xmm13
cvtsd2ss xmm3, xmm13
; Source: xmm13, target: xmm4
movss xmm4, xmm13
movsd xmm4, xmm13
cvtss2sd xmm4, xmm13
cvtsd2ss xmm4, xmm13
; Source: xmm13, target: xmm5
movss xmm5, xmm13
movsd xmm5, xmm13
cvtss2sd xmm5, xmm13
cvtsd2ss xmm5, xmm13
; Source: xmm13, target: xmm6
movss xmm6, xmm13
movsd xmm6, xmm13
cvtss2sd xmm6, xmm13
cvtsd2ss xmm6, xmm13
; Source: xmm13, target: xmm7
movss xmm7, xmm13
movsd xmm7, xmm13
cvtss2sd xmm7, xmm13
cvtsd2ss xmm7, xmm13
; Source: xmm13, target: xmm8
movss xmm8, xmm13
movsd xmm8, xmm13
cvtss2sd xmm8, xmm13
cvtsd2ss xmm8, xmm13
; Source: xmm13, target: xmm9
movss xmm9, xmm13
movsd xmm9, xmm13
cvtss2sd xmm9, xmm13
cvtsd2ss xmm9, xmm13
; Source: xmm13, target: xmm10
movss xmm10, xmm13
movsd xmm10, xmm13
cvtss2sd xmm10, xmm13
cvtsd2ss xmm10, xmm13
; Source: xmm13, target: xmm11
movss xmm11, xmm13
movsd xmm11, xmm13
cvtss2sd xmm11, xmm13
cvtsd2ss xmm11, xmm13
; Source: xmm13, target: xmm12
movss xmm12, xmm13
movsd xmm12, xmm13
cvtss2sd xmm12, xmm13
cvtsd2ss xmm12, xmm13
; Source: xmm13, target: xmm13
movss xmm13, xmm13
movsd xmm13, xmm13
cvtss2sd xmm13, xmm13
cvtsd2ss xmm13, xmm13
; Source: xmm13, target: xmm14
movss xmm14, xmm13
movsd xmm14, xmm13
cvtss2sd xmm14, xmm13
cvtsd2ss xmm14, xmm13
; Source: xmm13, target: xmm15
movss xmm15, xmm13
movsd xmm15, xmm13
cvtss2sd xmm15, xmm13
cvtsd2ss xmm15, xmm13
; Source: xmm14, target: xmm0
movss xmm0, xmm14
movsd xmm0, xmm14
cvtss2sd xmm0, xmm14
cvtsd2ss xmm0, xmm14
; Source: xmm14, target: xmm1
movss xmm1, xmm14
movsd xmm1, xmm14
cvtss2sd xmm1, xmm14
cvtsd2ss xmm1, xmm14
; Source: xmm14, target: xmm2
movss xmm2, xmm14
movsd xmm2, xmm14
cvtss2sd xmm2, xmm14
cvtsd2ss xmm2, xmm14
; Source: xmm14, target: xmm3
movss xmm3, xmm14
movsd xmm3, xmm14
cvtss2sd xmm3, xmm14
cvtsd2ss xmm3, xmm14
; Source: xmm14, target: xmm4
movss xmm4, xmm14
movsd xmm4, xmm14
cvtss2sd xmm4, xmm14
cvtsd2ss xmm4, xmm14
; Source: xmm14, target: xmm5
movss xmm5, xmm14
movsd xmm5, xmm14
cvtss2sd xmm5, xmm14
cvtsd2ss xmm5, xmm14
; Source: xmm14, target: xmm6
movss xmm6, xmm14
movsd xmm6, xmm14
cvtss2sd xmm6, xmm14
cvtsd2ss xmm6, xmm14
; Source: xmm14, target: xmm7
movss xmm7, xmm14
movsd xmm7, xmm14
cvtss2sd xmm7, xmm14
cvtsd2ss xmm7, xmm14
; Source: xmm14, target: xmm8
movss xmm8, xmm14
movsd xmm8, xmm14
cvtss2sd xmm8, xmm14
cvtsd2ss xmm8, xmm14
; Source: xmm14, target: xmm9
movss xmm9, xmm14
movsd xmm9, xmm14
cvtss2sd xmm9, xmm14
cvtsd2ss xmm9, xmm14
; Source: xmm14, target: xmm10
movss xmm10, xmm14
movsd xmm10, xmm14
cvtss2sd xmm10, xmm14
cvtsd2ss xmm10, xmm14
; Source: xmm14, target: xmm11
movss xmm11, xmm14
movsd xmm11, xmm14
cvtss2sd xmm11, xmm14
cvtsd2ss xmm11, xmm14
; Source: xmm14, target: xmm12
movss xmm12, xmm14
movsd xmm12, xmm14
cvtss2sd xmm12, xmm14
cvtsd2ss xmm12, xmm14
; Source: xmm14, target: xmm13
movss xmm13, xmm14
movsd xmm13, xmm14
cvtss2sd xmm13, xmm14
cvtsd2ss xmm13, xmm14
; Source: xmm14, target: xmm14
movss xmm14, xmm14
movsd xmm14, xmm14
cvtss2sd xmm14, xmm14
cvtsd2ss xmm14, xmm14
; Source: xmm14, target: xmm15
movss xmm15, xmm14
movsd xmm15, xmm14
cvtss2sd xmm15, xmm14
cvtsd2ss xmm15, xmm14
; Source: xmm15, target: xmm0
movss xmm0, xmm15
movsd xmm0, xmm15
cvtss2sd xmm0, xmm15
cvtsd2ss xmm0, xmm15
; Source: xmm15, target: xmm1
movss xmm1, xmm15
movsd xmm1, xmm15
cvtss2sd xmm1, xmm15
cvtsd2ss xmm1, xmm15
; Source: xmm15, target: xmm2
movss xmm2, xmm15
movsd xmm2, xmm15
cvtss2sd xmm2, xmm15
cvtsd2ss xmm2, xmm15
; Source: xmm15, target: xmm3
movss xmm3, xmm15
movsd xmm3, xmm15
cvtss2sd xmm3, xmm15
cvtsd2ss xmm3, xmm15
; Source: xmm15, target: xmm4
movss xmm4, xmm15
movsd xmm4, xmm15
cvtss2sd xmm4, xmm15
cvtsd2ss xmm4, xmm15
; Source: xmm15, target: xmm5
movss xmm5, xmm15
movsd xmm5, xmm15
cvtss2sd xmm5, xmm15
cvtsd2ss xmm5, xmm15
; Source: xmm15, target: xmm6
movss xmm6, xmm15
movsd xmm6, xmm15
cvtss2sd xmm6, xmm15
cvtsd2ss xmm6, xmm15
; Source: xmm15, target: xmm7
movss xmm7, xmm15
movsd xmm7, xmm15
cvtss2sd xmm7, xmm15
cvtsd2ss xmm7, xmm15
; Source: xmm15, target: xmm8
movss xmm8, xmm15
movsd xmm8, xmm15
cvtss2sd xmm8, xmm15
cvtsd2ss xmm8, xmm15
; Source: xmm15, target: xmm9
movss xmm9, xmm15
movsd xmm9, xmm15
cvtss2sd xmm9, xmm15
cvtsd2ss xmm9, xmm15
; Source: xmm15, target: xmm10
movss xmm10, xmm15
movsd xmm10, xmm15
cvtss2sd xmm10, xmm15
cvtsd2ss xmm10, xmm15
; Source: xmm15, target: xmm11
movss xmm11, xmm15
movsd xmm11, xmm15
cvtss2sd xmm11, xmm15
cvtsd2ss xmm11, xmm15
; Source: xmm15, target: xmm12
movss xmm12, xmm15
movsd xmm12, xmm15
cvtss2sd xmm12, xmm15
cvtsd2ss xmm12, xmm15
; Source: xmm15, target: xmm13
movss xmm13, xmm15
movsd xmm13, xmm15
cvtss2sd xmm13, xmm15
cvtsd2ss xmm13, xmm15
; Source: xmm15, target: xmm14
movss xmm14, xmm15
movsd xmm14, xmm15
cvtss2sd xmm14, xmm15
cvtsd2ss xmm14, xmm15
; Source: xmm15, target: xmm15
movss xmm15, xmm15
movsd xmm15, xmm15
cvtss2sd xmm15, xmm15
cvtsd2ss xmm15, xmm15
; Float <-> Int
; Between: xmm0 and rax
movss dword ptr [rax - 4], xmm0
movsd qword ptr [rax + 4], xmm0
movss xmm0, dword ptr [rax - 4]
movsd xmm0, qword ptr [rax + 4]
cvtsi2ss xmm0, qword ptr [rax - 4]
cvtsi2sd xmm0, dword ptr [rax + 4]
cvttss2si eax, xmm0
cvttsd2si eax, xmm0
cvtsi2ss xmm0, eax
cvtsi2sd xmm0, eax
cvttss2si rax, xmm0
cvttsd2si rax, xmm0
cvtsi2ss xmm0, rax
cvtsi2sd xmm0, rax
; Between: xmm0 and rcx
movss dword ptr [rcx - 4], xmm0
movsd qword ptr [rcx + 4], xmm0
movss xmm0, dword ptr [rcx - 4]
movsd xmm0, qword ptr [rcx + 4]
cvtsi2ss xmm0, qword ptr [rcx - 4]
cvtsi2sd xmm0, dword ptr [rcx + 4]
cvttss2si ecx, xmm0
cvttsd2si ecx, xmm0
cvtsi2ss xmm0, ecx
cvtsi2sd xmm0, ecx
cvttss2si rcx, xmm0
cvttsd2si rcx, xmm0
cvtsi2ss xmm0, rcx
cvtsi2sd xmm0, rcx
; Between: xmm0 and rdx
movss dword ptr [rdx - 4], xmm0
movsd qword ptr [rdx + 4], xmm0
movss xmm0, dword ptr [rdx - 4]
movsd xmm0, qword ptr [rdx + 4]
cvtsi2ss xmm0, qword ptr [rdx - 4]
cvtsi2sd xmm0, dword ptr [rdx + 4]
cvttss2si edx, xmm0
cvttsd2si edx, xmm0
cvtsi2ss xmm0, edx
cvtsi2sd xmm0, edx
cvttss2si rdx, xmm0
cvttsd2si rdx, xmm0
cvtsi2ss xmm0, rdx
cvtsi2sd xmm0, rdx
; Between: xmm0 and rbx
movss dword ptr [rbx - 4], xmm0
movsd qword ptr [rbx + 4], xmm0
movss xmm0, dword ptr [rbx - 4]
movsd xmm0, qword ptr [rbx + 4]
cvtsi2ss xmm0, qword ptr [rbx - 4]
cvtsi2sd xmm0, dword ptr [rbx + 4]
cvttss2si ebx, xmm0
cvttsd2si ebx, xmm0
cvtsi2ss xmm0, ebx
cvtsi2sd xmm0, ebx
cvttss2si rbx, xmm0
cvttsd2si rbx, xmm0
cvtsi2ss xmm0, rbx
cvtsi2sd xmm0, rbx
; Between: xmm0 and rsp
movss dword ptr [rsp - 4], xmm0
movsd qword ptr [rsp + 4], xmm0
movss xmm0, dword ptr [rsp - 4]
movsd xmm0, qword ptr [rsp + 4]
cvtsi2ss xmm0, qword ptr [rsp - 4]
cvtsi2sd xmm0, dword ptr [rsp + 4]
cvttss2si esp, xmm0
cvttsd2si esp, xmm0
cvtsi2ss xmm0, esp
cvtsi2sd xmm0, esp
cvttss2si rsp, xmm0
cvttsd2si rsp, xmm0
cvtsi2ss xmm0, rsp
cvtsi2sd xmm0, rsp
; Between: xmm0 and rbp
movss dword ptr [rbp - 4], xmm0
movsd qword ptr [rbp + 4], xmm0
movss xmm0, dword ptr [rbp - 4]
movsd xmm0, qword ptr [rbp + 4]
cvtsi2ss xmm0, qword ptr [rbp - 4]
cvtsi2sd xmm0, dword ptr [rbp + 4]
cvttss2si ebp, xmm0
cvttsd2si ebp, xmm0
cvtsi2ss xmm0, ebp
cvtsi2sd xmm0, ebp
cvttss2si rbp, xmm0
cvttsd2si rbp, xmm0
cvtsi2ss xmm0, rbp
cvtsi2sd xmm0, rbp
; Between: xmm0 and rsi
movss dword ptr [rsi - 4], xmm0
movsd qword ptr [rsi + 4], xmm0
movss xmm0, dword ptr [rsi - 4]
movsd xmm0, qword ptr [rsi + 4]
cvtsi2ss xmm0, qword ptr [rsi - 4]
cvtsi2sd xmm0, dword ptr [rsi + 4]
cvttss2si esi, xmm0
cvttsd2si esi, xmm0
cvtsi2ss xmm0, esi
cvtsi2sd xmm0, esi
cvttss2si rsi, xmm0
cvttsd2si rsi, xmm0
cvtsi2ss xmm0, rsi
cvtsi2sd xmm0, rsi
; Between: xmm0 and rdi
movss dword ptr [rdi - 4], xmm0
movsd qword ptr [rdi + 4], xmm0
movss xmm0, dword ptr [rdi - 4]
movsd xmm0, qword ptr [rdi + 4]
cvtsi2ss xmm0, qword ptr [rdi - 4]
cvtsi2sd xmm0, dword ptr [rdi + 4]
cvttss2si edi, xmm0
cvttsd2si edi, xmm0
cvtsi2ss xmm0, edi
cvtsi2sd xmm0, edi
cvttss2si rdi, xmm0
cvttsd2si rdi, xmm0
cvtsi2ss xmm0, rdi
cvtsi2sd xmm0, rdi
; Between: xmm0 and r8
movss dword ptr [r8 - 4], xmm0
movsd qword ptr [r8 + 4], xmm0
movss xmm0, dword ptr [r8 - 4]
movsd xmm0, qword ptr [r8 + 4]
cvtsi2ss xmm0, qword ptr [r8 - 4]
cvtsi2sd xmm0, dword ptr [r8 + 4]
cvttss2si r8d, xmm0
cvttsd2si r8d, xmm0
cvtsi2ss xmm0, r8d
cvtsi2sd xmm0, r8d
cvttss2si r8, xmm0
cvttsd2si r8, xmm0
cvtsi2ss xmm0, r8
cvtsi2sd xmm0, r8
; Between: xmm0 and r9
movss dword ptr [r9 - 4], xmm0
movsd qword ptr [r9 + 4], xmm0
movss xmm0, dword ptr [r9 - 4]
movsd xmm0, qword ptr [r9 + 4]
cvtsi2ss xmm0, qword ptr [r9 - 4]
cvtsi2sd xmm0, dword ptr [r9 + 4]
cvttss2si r9d, xmm0
cvttsd2si r9d, xmm0
cvtsi2ss xmm0, r9d
cvtsi2sd xmm0, r9d
cvttss2si r9, xmm0
cvttsd2si r9, xmm0
cvtsi2ss xmm0, r9
cvtsi2sd xmm0, r9
; Between: xmm0 and r10
movss dword ptr [r10 - 4], xmm0
movsd qword ptr [r10 + 4], xmm0
movss xmm0, dword ptr [r10 - 4]
movsd xmm0, qword ptr [r10 + 4]
cvtsi2ss xmm0, qword ptr [r10 - 4]
cvtsi2sd xmm0, dword ptr [r10 + 4]
cvttss2si r10d, xmm0
cvttsd2si r10d, xmm0
cvtsi2ss xmm0, r10d
cvtsi2sd xmm0, r10d
cvttss2si r10, xmm0
cvttsd2si r10, xmm0
cvtsi2ss xmm0, r10
cvtsi2sd xmm0, r10
; Between: xmm0 and r11
movss dword ptr [r11 - 4], xmm0
movsd qword ptr [r11 + 4], xmm0
movss xmm0, dword ptr [r11 - 4]
movsd xmm0, qword ptr [r11 + 4]
cvtsi2ss xmm0, qword ptr [r11 - 4]
cvtsi2sd xmm0, dword ptr [r11 + 4]
cvttss2si r11d, xmm0
cvttsd2si r11d, xmm0
cvtsi2ss xmm0, r11d
cvtsi2sd xmm0, r11d
cvttss2si r11, xmm0
cvttsd2si r11, xmm0
cvtsi2ss xmm0, r11
cvtsi2sd xmm0, r11
; Between: xmm0 and r12
movss dword ptr [r12 - 4], xmm0
movsd qword ptr [r12 + 4], xmm0
movss xmm0, dword ptr [r12 - 4]
movsd xmm0, qword ptr [r12 + 4]
cvtsi2ss xmm0, qword ptr [r12 - 4]
cvtsi2sd xmm0, dword ptr [r12 + 4]
cvttss2si r12d, xmm0
cvttsd2si r12d, xmm0
cvtsi2ss xmm0, r12d
cvtsi2sd xmm0, r12d
cvttss2si r12, xmm0
cvttsd2si r12, xmm0
cvtsi2ss xmm0, r12
cvtsi2sd xmm0, r12
; Between: xmm0 and r13
movss dword ptr [r13 - 4], xmm0
movsd qword ptr [r13 + 4], xmm0
movss xmm0, dword ptr [r13 - 4]
movsd xmm0, qword ptr [r13 + 4]
cvtsi2ss xmm0, qword ptr [r13 - 4]
cvtsi2sd xmm0, dword ptr [r13 + 4]
cvttss2si r13d, xmm0
cvttsd2si r13d, xmm0
cvtsi2ss xmm0, r13d
cvtsi2sd xmm0, r13d
cvttss2si r13, xmm0
cvttsd2si r13, xmm0
cvtsi2ss xmm0, r13
cvtsi2sd xmm0, r13
; Between: xmm0 and r14
movss dword ptr [r14 - 4], xmm0
movsd qword ptr [r14 + 4], xmm0
movss xmm0, dword ptr [r14 - 4]
movsd xmm0, qword ptr [r14 + 4]
cvtsi2ss xmm0, qword ptr [r14 - 4]
cvtsi2sd xmm0, dword ptr [r14 + 4]
cvttss2si r14d, xmm0
cvttsd2si r14d, xmm0
cvtsi2ss xmm0, r14d
cvtsi2sd xmm0, r14d
cvttss2si r14, xmm0
cvttsd2si r14, xmm0
cvtsi2ss xmm0, r14
cvtsi2sd xmm0, r14
; Between: xmm0 and r15
movss dword ptr [r15 - 4], xmm0
movsd qword ptr [r15 + 4], xmm0
movss xmm0, dword ptr [r15 - 4]
movsd xmm0, qword ptr [r15 + 4]
cvtsi2ss xmm0, qword ptr [r15 - 4]
cvtsi2sd xmm0, dword ptr [r15 + 4]
cvttss2si r15d, xmm0
cvttsd2si r15d, xmm0
cvtsi2ss xmm0, r15d
cvtsi2sd xmm0, r15d
cvttss2si r15, xmm0
cvttsd2si r15, xmm0
cvtsi2ss xmm0, r15
cvtsi2sd xmm0, r15
; Between: xmm1 and rax
movss dword ptr [rax - 4], xmm1
movsd qword ptr [rax + 4], xmm1
movss xmm1, dword ptr [rax - 4]
movsd xmm1, qword ptr [rax + 4]
cvtsi2ss xmm1, qword ptr [rax - 4]
cvtsi2sd xmm1, dword ptr [rax + 4]
cvttss2si eax, xmm1
cvttsd2si eax, xmm1
cvtsi2ss xmm1, eax
cvtsi2sd xmm1, eax
cvttss2si rax, xmm1
cvttsd2si rax, xmm1
cvtsi2ss xmm1, rax
cvtsi2sd xmm1, rax
; Between: xmm1 and rcx
movss dword ptr [rcx - 4], xmm1
movsd qword ptr [rcx + 4], xmm1
movss xmm1, dword ptr [rcx - 4]
movsd xmm1, qword ptr [rcx + 4]
cvtsi2ss xmm1, qword ptr [rcx - 4]
cvtsi2sd xmm1, dword ptr [rcx + 4]
cvttss2si ecx, xmm1
cvttsd2si ecx, xmm1
cvtsi2ss xmm1, ecx
cvtsi2sd xmm1, ecx
cvttss2si rcx, xmm1
cvttsd2si rcx, xmm1
cvtsi2ss xmm1, rcx
cvtsi2sd xmm1, rcx
; Between: xmm1 and rdx
movss dword ptr [rdx - 4], xmm1
movsd qword ptr [rdx + 4], xmm1
movss xmm1, dword ptr [rdx - 4]
movsd xmm1, qword ptr [rdx + 4]
cvtsi2ss xmm1, qword ptr [rdx - 4]
cvtsi2sd xmm1, dword ptr [rdx + 4]
cvttss2si edx, xmm1
cvttsd2si edx, xmm1
cvtsi2ss xmm1, edx
cvtsi2sd xmm1, edx
cvttss2si rdx, xmm1
cvttsd2si rdx, xmm1
cvtsi2ss xmm1, rdx
cvtsi2sd xmm1, rdx
; Between: xmm1 and rbx
movss dword ptr [rbx - 4], xmm1
movsd qword ptr [rbx + 4], xmm1
movss xmm1, dword ptr [rbx - 4]
movsd xmm1, qword ptr [rbx + 4]
cvtsi2ss xmm1, qword ptr [rbx - 4]
cvtsi2sd xmm1, dword ptr [rbx + 4]
cvttss2si ebx, xmm1
cvttsd2si ebx, xmm1
cvtsi2ss xmm1, ebx
cvtsi2sd xmm1, ebx
cvttss2si rbx, xmm1
cvttsd2si rbx, xmm1
cvtsi2ss xmm1, rbx
cvtsi2sd xmm1, rbx
; Between: xmm1 and rsp
movss dword ptr [rsp - 4], xmm1
movsd qword ptr [rsp + 4], xmm1
movss xmm1, dword ptr [rsp - 4]
movsd xmm1, qword ptr [rsp + 4]
cvtsi2ss xmm1, qword ptr [rsp - 4]
cvtsi2sd xmm1, dword ptr [rsp + 4]
cvttss2si esp, xmm1
cvttsd2si esp, xmm1
cvtsi2ss xmm1, esp
cvtsi2sd xmm1, esp
cvttss2si rsp, xmm1
cvttsd2si rsp, xmm1
cvtsi2ss xmm1, rsp
cvtsi2sd xmm1, rsp
; Between: xmm1 and rbp
movss dword ptr [rbp - 4], xmm1
movsd qword ptr [rbp + 4], xmm1
movss xmm1, dword ptr [rbp - 4]
movsd xmm1, qword ptr [rbp + 4]
cvtsi2ss xmm1, qword ptr [rbp - 4]
cvtsi2sd xmm1, dword ptr [rbp + 4]
cvttss2si ebp, xmm1
cvttsd2si ebp, xmm1
cvtsi2ss xmm1, ebp
cvtsi2sd xmm1, ebp
cvttss2si rbp, xmm1
cvttsd2si rbp, xmm1
cvtsi2ss xmm1, rbp
cvtsi2sd xmm1, rbp
; Between: xmm1 and rsi
movss dword ptr [rsi - 4], xmm1
movsd qword ptr [rsi + 4], xmm1
movss xmm1, dword ptr [rsi - 4]
movsd xmm1, qword ptr [rsi + 4]
cvtsi2ss xmm1, qword ptr [rsi - 4]
cvtsi2sd xmm1, dword ptr [rsi + 4]
cvttss2si esi, xmm1
cvttsd2si esi, xmm1
cvtsi2ss xmm1, esi
cvtsi2sd xmm1, esi
cvttss2si rsi, xmm1
cvttsd2si rsi, xmm1
cvtsi2ss xmm1, rsi
cvtsi2sd xmm1, rsi
; Between: xmm1 and rdi
movss dword ptr [rdi - 4], xmm1
movsd qword ptr [rdi + 4], xmm1
movss xmm1, dword ptr [rdi - 4]
movsd xmm1, qword ptr [rdi + 4]
cvtsi2ss xmm1, qword ptr [rdi - 4]
cvtsi2sd xmm1, dword ptr [rdi + 4]
cvttss2si edi, xmm1
cvttsd2si edi, xmm1
cvtsi2ss xmm1, edi
cvtsi2sd xmm1, edi
cvttss2si rdi, xmm1
cvttsd2si rdi, xmm1
cvtsi2ss xmm1, rdi
cvtsi2sd xmm1, rdi
; Between: xmm1 and r8
movss dword ptr [r8 - 4], xmm1
movsd qword ptr [r8 + 4], xmm1
movss xmm1, dword ptr [r8 - 4]
movsd xmm1, qword ptr [r8 + 4]
cvtsi2ss xmm1, qword ptr [r8 - 4]
cvtsi2sd xmm1, dword ptr [r8 + 4]
cvttss2si r8d, xmm1
cvttsd2si r8d, xmm1
cvtsi2ss xmm1, r8d
cvtsi2sd xmm1, r8d
cvttss2si r8, xmm1
cvttsd2si r8, xmm1
cvtsi2ss xmm1, r8
cvtsi2sd xmm1, r8
; Between: xmm1 and r9
movss dword ptr [r9 - 4], xmm1
movsd qword ptr [r9 + 4], xmm1
movss xmm1, dword ptr [r9 - 4]
movsd xmm1, qword ptr [r9 + 4]
cvtsi2ss xmm1, qword ptr [r9 - 4]
cvtsi2sd xmm1, dword ptr [r9 + 4]
cvttss2si r9d, xmm1
cvttsd2si r9d, xmm1
cvtsi2ss xmm1, r9d
cvtsi2sd xmm1, r9d
cvttss2si r9, xmm1
cvttsd2si r9, xmm1
cvtsi2ss xmm1, r9
cvtsi2sd xmm1, r9
; Between: xmm1 and r10
movss dword ptr [r10 - 4], xmm1
movsd qword ptr [r10 + 4], xmm1
movss xmm1, dword ptr [r10 - 4]
movsd xmm1, qword ptr [r10 + 4]
cvtsi2ss xmm1, qword ptr [r10 - 4]
cvtsi2sd xmm1, dword ptr [r10 + 4]
cvttss2si r10d, xmm1
cvttsd2si r10d, xmm1
cvtsi2ss xmm1, r10d
cvtsi2sd xmm1, r10d
cvttss2si r10, xmm1
cvttsd2si r10, xmm1
cvtsi2ss xmm1, r10
cvtsi2sd xmm1, r10
; Between: xmm1 and r11
movss dword ptr [r11 - 4], xmm1
movsd qword ptr [r11 + 4], xmm1
movss xmm1, dword ptr [r11 - 4]
movsd xmm1, qword ptr [r11 + 4]
cvtsi2ss xmm1, qword ptr [r11 - 4]
cvtsi2sd xmm1, dword ptr [r11 + 4]
cvttss2si r11d, xmm1
cvttsd2si r11d, xmm1
cvtsi2ss xmm1, r11d
cvtsi2sd xmm1, r11d
cvttss2si r11, xmm1
cvttsd2si r11, xmm1
cvtsi2ss xmm1, r11
cvtsi2sd xmm1, r11
; Between: xmm1 and r12
movss dword ptr [r12 - 4], xmm1
movsd qword ptr [r12 + 4], xmm1
movss xmm1, dword ptr [r12 - 4]
movsd xmm1, qword ptr [r12 + 4]
cvtsi2ss xmm1, qword ptr [r12 - 4]
cvtsi2sd xmm1, dword ptr [r12 + 4]
cvttss2si r12d, xmm1
cvttsd2si r12d, xmm1
cvtsi2ss xmm1, r12d
cvtsi2sd xmm1, r12d
cvttss2si r12, xmm1
cvttsd2si r12, xmm1
cvtsi2ss xmm1, r12
cvtsi2sd xmm1, r12
; Between: xmm1 and r13
movss dword ptr [r13 - 4], xmm1
movsd qword ptr [r13 + 4], xmm1
movss xmm1, dword ptr [r13 - 4]
movsd xmm1, qword ptr [r13 + 4]
cvtsi2ss xmm1, qword ptr [r13 - 4]
cvtsi2sd xmm1, dword ptr [r13 + 4]
cvttss2si r13d, xmm1
cvttsd2si r13d, xmm1
cvtsi2ss xmm1, r13d
cvtsi2sd xmm1, r13d
cvttss2si r13, xmm1
cvttsd2si r13, xmm1
cvtsi2ss xmm1, r13
cvtsi2sd xmm1, r13
; Between: xmm1 and r14
movss dword ptr [r14 - 4], xmm1
movsd qword ptr [r14 + 4], xmm1
movss xmm1, dword ptr [r14 - 4]
movsd xmm1, qword ptr [r14 + 4]
cvtsi2ss xmm1, qword ptr [r14 - 4]
cvtsi2sd xmm1, dword ptr [r14 + 4]
cvttss2si r14d, xmm1
cvttsd2si r14d, xmm1
cvtsi2ss xmm1, r14d
cvtsi2sd xmm1, r14d
cvttss2si r14, xmm1
cvttsd2si r14, xmm1
cvtsi2ss xmm1, r14
cvtsi2sd xmm1, r14
; Between: xmm1 and r15
movss dword ptr [r15 - 4], xmm1
movsd qword ptr [r15 + 4], xmm1
movss xmm1, dword ptr [r15 - 4]
movsd xmm1, qword ptr [r15 + 4]
cvtsi2ss xmm1, qword ptr [r15 - 4]
cvtsi2sd xmm1, dword ptr [r15 + 4]
cvttss2si r15d, xmm1
cvttsd2si r15d, xmm1
cvtsi2ss xmm1, r15d
cvtsi2sd xmm1, r15d
cvttss2si r15, xmm1
cvttsd2si r15, xmm1
cvtsi2ss xmm1, r15
cvtsi2sd xmm1, r15
; Between: xmm2 and rax
movss dword ptr [rax - 4], xmm2
movsd qword ptr [rax + 4], xmm2
movss xmm2, dword ptr [rax - 4]
movsd xmm2, qword ptr [rax + 4]
cvtsi2ss xmm2, qword ptr [rax - 4]
cvtsi2sd xmm2, dword ptr [rax + 4]
cvttss2si eax, xmm2
cvttsd2si eax, xmm2
cvtsi2ss xmm2, eax
cvtsi2sd xmm2, eax
cvttss2si rax, xmm2
cvttsd2si rax, xmm2
cvtsi2ss xmm2, rax
cvtsi2sd xmm2, rax
; Between: xmm2 and rcx
movss dword ptr [rcx - 4], xmm2
movsd qword ptr [rcx + 4], xmm2
movss xmm2, dword ptr [rcx - 4]
movsd xmm2, qword ptr [rcx + 4]
cvtsi2ss xmm2, qword ptr [rcx - 4]
cvtsi2sd xmm2, dword ptr [rcx + 4]
cvttss2si ecx, xmm2
cvttsd2si ecx, xmm2
cvtsi2ss xmm2, ecx
cvtsi2sd xmm2, ecx
cvttss2si rcx, xmm2
cvttsd2si rcx, xmm2
cvtsi2ss xmm2, rcx
cvtsi2sd xmm2, rcx
; Between: xmm2 and rdx
movss dword ptr [rdx - 4], xmm2
movsd qword ptr [rdx + 4], xmm2
movss xmm2, dword ptr [rdx - 4]
movsd xmm2, qword ptr [rdx + 4]
cvtsi2ss xmm2, qword ptr [rdx - 4]
cvtsi2sd xmm2, dword ptr [rdx + 4]
cvttss2si edx, xmm2
cvttsd2si edx, xmm2
cvtsi2ss xmm2, edx
cvtsi2sd xmm2, edx
cvttss2si rdx, xmm2
cvttsd2si rdx, xmm2
cvtsi2ss xmm2, rdx
cvtsi2sd xmm2, rdx
; Between: xmm2 and rbx
movss dword ptr [rbx - 4], xmm2
movsd qword ptr [rbx + 4], xmm2
movss xmm2, dword ptr [rbx - 4]
movsd xmm2, qword ptr [rbx + 4]
cvtsi2ss xmm2, qword ptr [rbx - 4]
cvtsi2sd xmm2, dword ptr [rbx + 4]
cvttss2si ebx, xmm2
cvttsd2si ebx, xmm2
cvtsi2ss xmm2, ebx
cvtsi2sd xmm2, ebx
cvttss2si rbx, xmm2
cvttsd2si rbx, xmm2
cvtsi2ss xmm2, rbx
cvtsi2sd xmm2, rbx
; Between: xmm2 and rsp
movss dword ptr [rsp - 4], xmm2
movsd qword ptr [rsp + 4], xmm2
movss xmm2, dword ptr [rsp - 4]
movsd xmm2, qword ptr [rsp + 4]
cvtsi2ss xmm2, qword ptr [rsp - 4]
cvtsi2sd xmm2, dword ptr [rsp + 4]
cvttss2si esp, xmm2
cvttsd2si esp, xmm2
cvtsi2ss xmm2, esp
cvtsi2sd xmm2, esp
cvttss2si rsp, xmm2
cvttsd2si rsp, xmm2
cvtsi2ss xmm2, rsp
cvtsi2sd xmm2, rsp
; Between: xmm2 and rbp
movss dword ptr [rbp - 4], xmm2
movsd qword ptr [rbp + 4], xmm2
movss xmm2, dword ptr [rbp - 4]
movsd xmm2, qword ptr [rbp + 4]
cvtsi2ss xmm2, qword ptr [rbp - 4]
cvtsi2sd xmm2, dword ptr [rbp + 4]
cvttss2si ebp, xmm2
cvttsd2si ebp, xmm2
cvtsi2ss xmm2, ebp
cvtsi2sd xmm2, ebp
cvttss2si rbp, xmm2
cvttsd2si rbp, xmm2
cvtsi2ss xmm2, rbp
cvtsi2sd xmm2, rbp
; Between: xmm2 and rsi
movss dword ptr [rsi - 4], xmm2
movsd qword ptr [rsi + 4], xmm2
movss xmm2, dword ptr [rsi - 4]
movsd xmm2, qword ptr [rsi + 4]
cvtsi2ss xmm2, qword ptr [rsi - 4]
cvtsi2sd xmm2, dword ptr [rsi + 4]
cvttss2si esi, xmm2
cvttsd2si esi, xmm2
cvtsi2ss xmm2, esi
cvtsi2sd xmm2, esi
cvttss2si rsi, xmm2
cvttsd2si rsi, xmm2
cvtsi2ss xmm2, rsi
cvtsi2sd xmm2, rsi
; Between: xmm2 and rdi
movss dword ptr [rdi - 4], xmm2
movsd qword ptr [rdi + 4], xmm2
movss xmm2, dword ptr [rdi - 4]
movsd xmm2, qword ptr [rdi + 4]
cvtsi2ss xmm2, qword ptr [rdi - 4]
cvtsi2sd xmm2, dword ptr [rdi + 4]
cvttss2si edi, xmm2
cvttsd2si edi, xmm2
cvtsi2ss xmm2, edi
cvtsi2sd xmm2, edi
cvttss2si rdi, xmm2
cvttsd2si rdi, xmm2
cvtsi2ss xmm2, rdi
cvtsi2sd xmm2, rdi
; Between: xmm2 and r8
movss dword ptr [r8 - 4], xmm2
movsd qword ptr [r8 + 4], xmm2
movss xmm2, dword ptr [r8 - 4]
movsd xmm2, qword ptr [r8 + 4]
cvtsi2ss xmm2, qword ptr [r8 - 4]
cvtsi2sd xmm2, dword ptr [r8 + 4]
cvttss2si r8d, xmm2
cvttsd2si r8d, xmm2
cvtsi2ss xmm2, r8d
cvtsi2sd xmm2, r8d
cvttss2si r8, xmm2
cvttsd2si r8, xmm2
cvtsi2ss xmm2, r8
cvtsi2sd xmm2, r8
; Between: xmm2 and r9
movss dword ptr [r9 - 4], xmm2
movsd qword ptr [r9 + 4], xmm2
movss xmm2, dword ptr [r9 - 4]
movsd xmm2, qword ptr [r9 + 4]
cvtsi2ss xmm2, qword ptr [r9 - 4]
cvtsi2sd xmm2, dword ptr [r9 + 4]
cvttss2si r9d, xmm2
cvttsd2si r9d, xmm2
cvtsi2ss xmm2, r9d
cvtsi2sd xmm2, r9d
cvttss2si r9, xmm2
cvttsd2si r9, xmm2
cvtsi2ss xmm2, r9
cvtsi2sd xmm2, r9
; Between: xmm2 and r10
movss dword ptr [r10 - 4], xmm2
movsd qword ptr [r10 + 4], xmm2
movss xmm2, dword ptr [r10 - 4]
movsd xmm2, qword ptr [r10 + 4]
cvtsi2ss xmm2, qword ptr [r10 - 4]
cvtsi2sd xmm2, dword ptr [r10 + 4]
cvttss2si r10d, xmm2
cvttsd2si r10d, xmm2
cvtsi2ss xmm2, r10d
cvtsi2sd xmm2, r10d
cvttss2si r10, xmm2
cvttsd2si r10, xmm2
cvtsi2ss xmm2, r10
cvtsi2sd xmm2, r10
; Between: xmm2 and r11
movss dword ptr [r11 - 4], xmm2
movsd qword ptr [r11 + 4], xmm2
movss xmm2, dword ptr [r11 - 4]
movsd xmm2, qword ptr [r11 + 4]
cvtsi2ss xmm2, qword ptr [r11 - 4]
cvtsi2sd xmm2, dword ptr [r11 + 4]
cvttss2si r11d, xmm2
cvttsd2si r11d, xmm2
cvtsi2ss xmm2, r11d
cvtsi2sd xmm2, r11d
cvttss2si r11, xmm2
cvttsd2si r11, xmm2
cvtsi2ss xmm2, r11
cvtsi2sd xmm2, r11
; Between: xmm2 and r12
movss dword ptr [r12 - 4], xmm2
movsd qword ptr [r12 + 4], xmm2
movss xmm2, dword ptr [r12 - 4]
movsd xmm2, qword ptr [r12 + 4]
cvtsi2ss xmm2, qword ptr [r12 - 4]
cvtsi2sd xmm2, dword ptr [r12 + 4]
cvttss2si r12d, xmm2
cvttsd2si r12d, xmm2
cvtsi2ss xmm2, r12d
cvtsi2sd xmm2, r12d
cvttss2si r12, xmm2
cvttsd2si r12, xmm2
cvtsi2ss xmm2, r12
cvtsi2sd xmm2, r12
; Between: xmm2 and r13
movss dword ptr [r13 - 4], xmm2
movsd qword ptr [r13 + 4], xmm2
movss xmm2, dword ptr [r13 - 4]
movsd xmm2, qword ptr [r13 + 4]
cvtsi2ss xmm2, qword ptr [r13 - 4]
cvtsi2sd xmm2, dword ptr [r13 + 4]
cvttss2si r13d, xmm2
cvttsd2si r13d, xmm2
cvtsi2ss xmm2, r13d
cvtsi2sd xmm2, r13d
cvttss2si r13, xmm2
cvttsd2si r13, xmm2
cvtsi2ss xmm2, r13
cvtsi2sd xmm2, r13
; Between: xmm2 and r14
movss dword ptr [r14 - 4], xmm2
movsd qword ptr [r14 + 4], xmm2
movss xmm2, dword ptr [r14 - 4]
movsd xmm2, qword ptr [r14 + 4]
cvtsi2ss xmm2, qword ptr [r14 - 4]
cvtsi2sd xmm2, dword ptr [r14 + 4]
cvttss2si r14d, xmm2
cvttsd2si r14d, xmm2
cvtsi2ss xmm2, r14d
cvtsi2sd xmm2, r14d
cvttss2si r14, xmm2
cvttsd2si r14, xmm2
cvtsi2ss xmm2, r14
cvtsi2sd xmm2, r14
; Between: xmm2 and r15
movss dword ptr [r15 - 4], xmm2
movsd qword ptr [r15 + 4], xmm2
movss xmm2, dword ptr [r15 - 4]
movsd xmm2, qword ptr [r15 + 4]
cvtsi2ss xmm2, qword ptr [r15 - 4]
cvtsi2sd xmm2, dword ptr [r15 + 4]
cvttss2si r15d, xmm2
cvttsd2si r15d, xmm2
cvtsi2ss xmm2, r15d
cvtsi2sd xmm2, r15d
cvttss2si r15, xmm2
cvttsd2si r15, xmm2
cvtsi2ss xmm2, r15
cvtsi2sd xmm2, r15
; Between: xmm3 and rax
movss dword ptr [rax - 4], xmm3
movsd qword ptr [rax + 4], xmm3
movss xmm3, dword ptr [rax - 4]
movsd xmm3, qword ptr [rax + 4]
cvtsi2ss xmm3, qword ptr [rax - 4]
cvtsi2sd xmm3, dword ptr [rax + 4]
cvttss2si eax, xmm3
cvttsd2si eax, xmm3
cvtsi2ss xmm3, eax
cvtsi2sd xmm3, eax
cvttss2si rax, xmm3
cvttsd2si rax, xmm3
cvtsi2ss xmm3, rax
cvtsi2sd xmm3, rax
; Between: xmm3 and rcx
movss dword ptr [rcx - 4], xmm3
movsd qword ptr [rcx + 4], xmm3
movss xmm3, dword ptr [rcx - 4]
movsd xmm3, qword ptr [rcx + 4]
cvtsi2ss xmm3, qword ptr [rcx - 4]
cvtsi2sd xmm3, dword ptr [rcx + 4]
cvttss2si ecx, xmm3
cvttsd2si ecx, xmm3
cvtsi2ss xmm3, ecx
cvtsi2sd xmm3, ecx
cvttss2si rcx, xmm3
cvttsd2si rcx, xmm3
cvtsi2ss xmm3, rcx
cvtsi2sd xmm3, rcx
; Between: xmm3 and rdx
movss dword ptr [rdx - 4], xmm3
movsd qword ptr [rdx + 4], xmm3
movss xmm3, dword ptr [rdx - 4]
movsd xmm3, qword ptr [rdx + 4]
cvtsi2ss xmm3, qword ptr [rdx - 4]
cvtsi2sd xmm3, dword ptr [rdx + 4]
cvttss2si edx, xmm3
cvttsd2si edx, xmm3
cvtsi2ss xmm3, edx
cvtsi2sd xmm3, edx
cvttss2si rdx, xmm3
cvttsd2si rdx, xmm3
cvtsi2ss xmm3, rdx
cvtsi2sd xmm3, rdx
; Between: xmm3 and rbx
movss dword ptr [rbx - 4], xmm3
movsd qword ptr [rbx + 4], xmm3
movss xmm3, dword ptr [rbx - 4]
movsd xmm3, qword ptr [rbx + 4]
cvtsi2ss xmm3, qword ptr [rbx - 4]
cvtsi2sd xmm3, dword ptr [rbx + 4]
cvttss2si ebx, xmm3
cvttsd2si ebx, xmm3
cvtsi2ss xmm3, ebx
cvtsi2sd xmm3, ebx
cvttss2si rbx, xmm3
cvttsd2si rbx, xmm3
cvtsi2ss xmm3, rbx
cvtsi2sd xmm3, rbx
; Between: xmm3 and rsp
movss dword ptr [rsp - 4], xmm3
movsd qword ptr [rsp + 4], xmm3
movss xmm3, dword ptr [rsp - 4]
movsd xmm3, qword ptr [rsp + 4]
cvtsi2ss xmm3, qword ptr [rsp - 4]
cvtsi2sd xmm3, dword ptr [rsp + 4]
cvttss2si esp, xmm3
cvttsd2si esp, xmm3
cvtsi2ss xmm3, esp
cvtsi2sd xmm3, esp
cvttss2si rsp, xmm3
cvttsd2si rsp, xmm3
cvtsi2ss xmm3, rsp
cvtsi2sd xmm3, rsp
; Between: xmm3 and rbp
movss dword ptr [rbp - 4], xmm3
movsd qword ptr [rbp + 4], xmm3
movss xmm3, dword ptr [rbp - 4]
movsd xmm3, qword ptr [rbp + 4]
cvtsi2ss xmm3, qword ptr [rbp - 4]
cvtsi2sd xmm3, dword ptr [rbp + 4]
cvttss2si ebp, xmm3
cvttsd2si ebp, xmm3
cvtsi2ss xmm3, ebp
cvtsi2sd xmm3, ebp
cvttss2si rbp, xmm3
cvttsd2si rbp, xmm3
cvtsi2ss xmm3, rbp
cvtsi2sd xmm3, rbp
; Between: xmm3 and rsi
movss dword ptr [rsi - 4], xmm3
movsd qword ptr [rsi + 4], xmm3
movss xmm3, dword ptr [rsi - 4]
movsd xmm3, qword ptr [rsi + 4]
cvtsi2ss xmm3, qword ptr [rsi - 4]
cvtsi2sd xmm3, dword ptr [rsi + 4]
cvttss2si esi, xmm3
cvttsd2si esi, xmm3
cvtsi2ss xmm3, esi
cvtsi2sd xmm3, esi
cvttss2si rsi, xmm3
cvttsd2si rsi, xmm3
cvtsi2ss xmm3, rsi
cvtsi2sd xmm3, rsi
; Between: xmm3 and rdi
movss dword ptr [rdi - 4], xmm3
movsd qword ptr [rdi + 4], xmm3
movss xmm3, dword ptr [rdi - 4]
movsd xmm3, qword ptr [rdi + 4]
cvtsi2ss xmm3, qword ptr [rdi - 4]
cvtsi2sd xmm3, dword ptr [rdi + 4]
cvttss2si edi, xmm3
cvttsd2si edi, xmm3
cvtsi2ss xmm3, edi
cvtsi2sd xmm3, edi
cvttss2si rdi, xmm3
cvttsd2si rdi, xmm3
cvtsi2ss xmm3, rdi
cvtsi2sd xmm3, rdi
; Between: xmm3 and r8
movss dword ptr [r8 - 4], xmm3
movsd qword ptr [r8 + 4], xmm3
movss xmm3, dword ptr [r8 - 4]
movsd xmm3, qword ptr [r8 + 4]
cvtsi2ss xmm3, qword ptr [r8 - 4]
cvtsi2sd xmm3, dword ptr [r8 + 4]
cvttss2si r8d, xmm3
cvttsd2si r8d, xmm3
cvtsi2ss xmm3, r8d
cvtsi2sd xmm3, r8d
cvttss2si r8, xmm3
cvttsd2si r8, xmm3
cvtsi2ss xmm3, r8
cvtsi2sd xmm3, r8
; Between: xmm3 and r9
movss dword ptr [r9 - 4], xmm3
movsd qword ptr [r9 + 4], xmm3
movss xmm3, dword ptr [r9 - 4]
movsd xmm3, qword ptr [r9 + 4]
cvtsi2ss xmm3, qword ptr [r9 - 4]
cvtsi2sd xmm3, dword ptr [r9 + 4]
cvttss2si r9d, xmm3
cvttsd2si r9d, xmm3
cvtsi2ss xmm3, r9d
cvtsi2sd xmm3, r9d
cvttss2si r9, xmm3
cvttsd2si r9, xmm3
cvtsi2ss xmm3, r9
cvtsi2sd xmm3, r9
; Between: xmm3 and r10
movss dword ptr [r10 - 4], xmm3
movsd qword ptr [r10 + 4], xmm3
movss xmm3, dword ptr [r10 - 4]
movsd xmm3, qword ptr [r10 + 4]
cvtsi2ss xmm3, qword ptr [r10 - 4]
cvtsi2sd xmm3, dword ptr [r10 + 4]
cvttss2si r10d, xmm3
cvttsd2si r10d, xmm3
cvtsi2ss xmm3, r10d
cvtsi2sd xmm3, r10d
cvttss2si r10, xmm3
cvttsd2si r10, xmm3
cvtsi2ss xmm3, r10
cvtsi2sd xmm3, r10
; Between: xmm3 and r11
movss dword ptr [r11 - 4], xmm3
movsd qword ptr [r11 + 4], xmm3
movss xmm3, dword ptr [r11 - 4]
movsd xmm3, qword ptr [r11 + 4]
cvtsi2ss xmm3, qword ptr [r11 - 4]
cvtsi2sd xmm3, dword ptr [r11 + 4]
cvttss2si r11d, xmm3
cvttsd2si r11d, xmm3
cvtsi2ss xmm3, r11d
cvtsi2sd xmm3, r11d
cvttss2si r11, xmm3
cvttsd2si r11, xmm3
cvtsi2ss xmm3, r11
cvtsi2sd xmm3, r11
; Between: xmm3 and r12
movss dword ptr [r12 - 4], xmm3
movsd qword ptr [r12 + 4], xmm3
movss xmm3, dword ptr [r12 - 4]
movsd xmm3, qword ptr [r12 + 4]
cvtsi2ss xmm3, qword ptr [r12 - 4]
cvtsi2sd xmm3, dword ptr [r12 + 4]
cvttss2si r12d, xmm3
cvttsd2si r12d, xmm3
cvtsi2ss xmm3, r12d
cvtsi2sd xmm3, r12d
cvttss2si r12, xmm3
cvttsd2si r12, xmm3
cvtsi2ss xmm3, r12
cvtsi2sd xmm3, r12
; Between: xmm3 and r13
movss dword ptr [r13 - 4], xmm3
movsd qword ptr [r13 + 4], xmm3
movss xmm3, dword ptr [r13 - 4]
movsd xmm3, qword ptr [r13 + 4]
cvtsi2ss xmm3, qword ptr [r13 - 4]
cvtsi2sd xmm3, dword ptr [r13 + 4]
cvttss2si r13d, xmm3
cvttsd2si r13d, xmm3
cvtsi2ss xmm3, r13d
cvtsi2sd xmm3, r13d
cvttss2si r13, xmm3
cvttsd2si r13, xmm3
cvtsi2ss xmm3, r13
cvtsi2sd xmm3, r13
; Between: xmm3 and r14
movss dword ptr [r14 - 4], xmm3
movsd qword ptr [r14 + 4], xmm3
movss xmm3, dword ptr [r14 - 4]
movsd xmm3, qword ptr [r14 + 4]
cvtsi2ss xmm3, qword ptr [r14 - 4]
cvtsi2sd xmm3, dword ptr [r14 + 4]
cvttss2si r14d, xmm3
cvttsd2si r14d, xmm3
cvtsi2ss xmm3, r14d
cvtsi2sd xmm3, r14d
cvttss2si r14, xmm3
cvttsd2si r14, xmm3
cvtsi2ss xmm3, r14
cvtsi2sd xmm3, r14
; Between: xmm3 and r15
movss dword ptr [r15 - 4], xmm3
movsd qword ptr [r15 + 4], xmm3
movss xmm3, dword ptr [r15 - 4]
movsd xmm3, qword ptr [r15 + 4]
cvtsi2ss xmm3, qword ptr [r15 - 4]
cvtsi2sd xmm3, dword ptr [r15 + 4]
cvttss2si r15d, xmm3
cvttsd2si r15d, xmm3
cvtsi2ss xmm3, r15d
cvtsi2sd xmm3, r15d
cvttss2si r15, xmm3
cvttsd2si r15, xmm3
cvtsi2ss xmm3, r15
cvtsi2sd xmm3, r15
; Between: xmm4 and rax
movss dword ptr [rax - 4], xmm4
movsd qword ptr [rax + 4], xmm4
movss xmm4, dword ptr [rax - 4]
movsd xmm4, qword ptr [rax + 4]
cvtsi2ss xmm4, qword ptr [rax - 4]
cvtsi2sd xmm4, dword ptr [rax + 4]
cvttss2si eax, xmm4
cvttsd2si eax, xmm4
cvtsi2ss xmm4, eax
cvtsi2sd xmm4, eax
cvttss2si rax, xmm4
cvttsd2si rax, xmm4
cvtsi2ss xmm4, rax
cvtsi2sd xmm4, rax
; Between: xmm4 and rcx
movss dword ptr [rcx - 4], xmm4
movsd qword ptr [rcx + 4], xmm4
movss xmm4, dword ptr [rcx - 4]
movsd xmm4, qword ptr [rcx + 4]
cvtsi2ss xmm4, qword ptr [rcx - 4]
cvtsi2sd xmm4, dword ptr [rcx + 4]
cvttss2si ecx, xmm4
cvttsd2si ecx, xmm4
cvtsi2ss xmm4, ecx
cvtsi2sd xmm4, ecx
cvttss2si rcx, xmm4
cvttsd2si rcx, xmm4
cvtsi2ss xmm4, rcx
cvtsi2sd xmm4, rcx
; Between: xmm4 and rdx
movss dword ptr [rdx - 4], xmm4
movsd qword ptr [rdx + 4], xmm4
movss xmm4, dword ptr [rdx - 4]
movsd xmm4, qword ptr [rdx + 4]
cvtsi2ss xmm4, qword ptr [rdx - 4]
cvtsi2sd xmm4, dword ptr [rdx + 4]
cvttss2si edx, xmm4
cvttsd2si edx, xmm4
cvtsi2ss xmm4, edx
cvtsi2sd xmm4, edx
cvttss2si rdx, xmm4
cvttsd2si rdx, xmm4
cvtsi2ss xmm4, rdx
cvtsi2sd xmm4, rdx
; Between: xmm4 and rbx
movss dword ptr [rbx - 4], xmm4
movsd qword ptr [rbx + 4], xmm4
movss xmm4, dword ptr [rbx - 4]
movsd xmm4, qword ptr [rbx + 4]
cvtsi2ss xmm4, qword ptr [rbx - 4]
cvtsi2sd xmm4, dword ptr [rbx + 4]
cvttss2si ebx, xmm4
cvttsd2si ebx, xmm4
cvtsi2ss xmm4, ebx
cvtsi2sd xmm4, ebx
cvttss2si rbx, xmm4
cvttsd2si rbx, xmm4
cvtsi2ss xmm4, rbx
cvtsi2sd xmm4, rbx
; Between: xmm4 and rsp
movss dword ptr [rsp - 4], xmm4
movsd qword ptr [rsp + 4], xmm4
movss xmm4, dword ptr [rsp - 4]
movsd xmm4, qword ptr [rsp + 4]
cvtsi2ss xmm4, qword ptr [rsp - 4]
cvtsi2sd xmm4, dword ptr [rsp + 4]
cvttss2si esp, xmm4
cvttsd2si esp, xmm4
cvtsi2ss xmm4, esp
cvtsi2sd xmm4, esp
cvttss2si rsp, xmm4
cvttsd2si rsp, xmm4
cvtsi2ss xmm4, rsp
cvtsi2sd xmm4, rsp
; Between: xmm4 and rbp
movss dword ptr [rbp - 4], xmm4
movsd qword ptr [rbp + 4], xmm4
movss xmm4, dword ptr [rbp - 4]
movsd xmm4, qword ptr [rbp + 4]
cvtsi2ss xmm4, qword ptr [rbp - 4]
cvtsi2sd xmm4, dword ptr [rbp + 4]
cvttss2si ebp, xmm4
cvttsd2si ebp, xmm4
cvtsi2ss xmm4, ebp
cvtsi2sd xmm4, ebp
cvttss2si rbp, xmm4
cvttsd2si rbp, xmm4
cvtsi2ss xmm4, rbp
cvtsi2sd xmm4, rbp
; Between: xmm4 and rsi
movss dword ptr [rsi - 4], xmm4
movsd qword ptr [rsi + 4], xmm4
movss xmm4, dword ptr [rsi - 4]
movsd xmm4, qword ptr [rsi + 4]
cvtsi2ss xmm4, qword ptr [rsi - 4]
cvtsi2sd xmm4, dword ptr [rsi + 4]
cvttss2si esi, xmm4
cvttsd2si esi, xmm4
cvtsi2ss xmm4, esi
cvtsi2sd xmm4, esi
cvttss2si rsi, xmm4
cvttsd2si rsi, xmm4
cvtsi2ss xmm4, rsi
cvtsi2sd xmm4, rsi
; Between: xmm4 and rdi
movss dword ptr [rdi - 4], xmm4
movsd qword ptr [rdi + 4], xmm4
movss xmm4, dword ptr [rdi - 4]
movsd xmm4, qword ptr [rdi + 4]
cvtsi2ss xmm4, qword ptr [rdi - 4]
cvtsi2sd xmm4, dword ptr [rdi + 4]
cvttss2si edi, xmm4
cvttsd2si edi, xmm4
cvtsi2ss xmm4, edi
cvtsi2sd xmm4, edi
cvttss2si rdi, xmm4
cvttsd2si rdi, xmm4
cvtsi2ss xmm4, rdi
cvtsi2sd xmm4, rdi
; Between: xmm4 and r8
movss dword ptr [r8 - 4], xmm4
movsd qword ptr [r8 + 4], xmm4
movss xmm4, dword ptr [r8 - 4]
movsd xmm4, qword ptr [r8 + 4]
cvtsi2ss xmm4, qword ptr [r8 - 4]
cvtsi2sd xmm4, dword ptr [r8 + 4]
cvttss2si r8d, xmm4
cvttsd2si r8d, xmm4
cvtsi2ss xmm4, r8d
cvtsi2sd xmm4, r8d
cvttss2si r8, xmm4
cvttsd2si r8, xmm4
cvtsi2ss xmm4, r8
cvtsi2sd xmm4, r8
; Between: xmm4 and r9
movss dword ptr [r9 - 4], xmm4
movsd qword ptr [r9 + 4], xmm4
movss xmm4, dword ptr [r9 - 4]
movsd xmm4, qword ptr [r9 + 4]
cvtsi2ss xmm4, qword ptr [r9 - 4]
cvtsi2sd xmm4, dword ptr [r9 + 4]
cvttss2si r9d, xmm4
cvttsd2si r9d, xmm4
cvtsi2ss xmm4, r9d
cvtsi2sd xmm4, r9d
cvttss2si r9, xmm4
cvttsd2si r9, xmm4
cvtsi2ss xmm4, r9
cvtsi2sd xmm4, r9
; Between: xmm4 and r10
movss dword ptr [r10 - 4], xmm4
movsd qword ptr [r10 + 4], xmm4
movss xmm4, dword ptr [r10 - 4]
movsd xmm4, qword ptr [r10 + 4]
cvtsi2ss xmm4, qword ptr [r10 - 4]
cvtsi2sd xmm4, dword ptr [r10 + 4]
cvttss2si r10d, xmm4
cvttsd2si r10d, xmm4
cvtsi2ss xmm4, r10d
cvtsi2sd xmm4, r10d
cvttss2si r10, xmm4
cvttsd2si r10, xmm4
cvtsi2ss xmm4, r10
cvtsi2sd xmm4, r10
; Between: xmm4 and r11
movss dword ptr [r11 - 4], xmm4
movsd qword ptr [r11 + 4], xmm4
movss xmm4, dword ptr [r11 - 4]
movsd xmm4, qword ptr [r11 + 4]
cvtsi2ss xmm4, qword ptr [r11 - 4]
cvtsi2sd xmm4, dword ptr [r11 + 4]
cvttss2si r11d, xmm4
cvttsd2si r11d, xmm4
cvtsi2ss xmm4, r11d
cvtsi2sd xmm4, r11d
cvttss2si r11, xmm4
cvttsd2si r11, xmm4
cvtsi2ss xmm4, r11
cvtsi2sd xmm4, r11
; Between: xmm4 and r12
movss dword ptr [r12 - 4], xmm4
movsd qword ptr [r12 + 4], xmm4
movss xmm4, dword ptr [r12 - 4]
movsd xmm4, qword ptr [r12 + 4]
cvtsi2ss xmm4, qword ptr [r12 - 4]
cvtsi2sd xmm4, dword ptr [r12 + 4]
cvttss2si r12d, xmm4
cvttsd2si r12d, xmm4
cvtsi2ss xmm4, r12d
cvtsi2sd xmm4, r12d
cvttss2si r12, xmm4
cvttsd2si r12, xmm4
cvtsi2ss xmm4, r12
cvtsi2sd xmm4, r12
; Between: xmm4 and r13
movss dword ptr [r13 - 4], xmm4
movsd qword ptr [r13 + 4], xmm4
movss xmm4, dword ptr [r13 - 4]
movsd xmm4, qword ptr [r13 + 4]
cvtsi2ss xmm4, qword ptr [r13 - 4]
cvtsi2sd xmm4, dword ptr [r13 + 4]
cvttss2si r13d, xmm4
cvttsd2si r13d, xmm4
cvtsi2ss xmm4, r13d
cvtsi2sd xmm4, r13d
cvttss2si r13, xmm4
cvttsd2si r13, xmm4
cvtsi2ss xmm4, r13
cvtsi2sd xmm4, r13
; Between: xmm4 and r14
movss dword ptr [r14 - 4], xmm4
movsd qword ptr [r14 + 4], xmm4
movss xmm4, dword ptr [r14 - 4]
movsd xmm4, qword ptr [r14 + 4]
cvtsi2ss xmm4, qword ptr [r14 - 4]
cvtsi2sd xmm4, dword ptr [r14 + 4]
cvttss2si r14d, xmm4
cvttsd2si r14d, xmm4
cvtsi2ss xmm4, r14d
cvtsi2sd xmm4, r14d
cvttss2si r14, xmm4
cvttsd2si r14, xmm4
cvtsi2ss xmm4, r14
cvtsi2sd xmm4, r14
; Between: xmm4 and r15
movss dword ptr [r15 - 4], xmm4
movsd qword ptr [r15 + 4], xmm4
movss xmm4, dword ptr [r15 - 4]
movsd xmm4, qword ptr [r15 + 4]
cvtsi2ss xmm4, qword ptr [r15 - 4]
cvtsi2sd xmm4, dword ptr [r15 + 4]
cvttss2si r15d, xmm4
cvttsd2si r15d, xmm4
cvtsi2ss xmm4, r15d
cvtsi2sd xmm4, r15d
cvttss2si r15, xmm4
cvttsd2si r15, xmm4
cvtsi2ss xmm4, r15
cvtsi2sd xmm4, r15
; Between: xmm5 and rax
movss dword ptr [rax - 4], xmm5
movsd qword ptr [rax + 4], xmm5
movss xmm5, dword ptr [rax - 4]
movsd xmm5, qword ptr [rax + 4]
cvtsi2ss xmm5, qword ptr [rax - 4]
cvtsi2sd xmm5, dword ptr [rax + 4]
cvttss2si eax, xmm5
cvttsd2si eax, xmm5
cvtsi2ss xmm5, eax
cvtsi2sd xmm5, eax
cvttss2si rax, xmm5
cvttsd2si rax, xmm5
cvtsi2ss xmm5, rax
cvtsi2sd xmm5, rax
; Between: xmm5 and rcx
movss dword ptr [rcx - 4], xmm5
movsd qword ptr [rcx + 4], xmm5
movss xmm5, dword ptr [rcx - 4]
movsd xmm5, qword ptr [rcx + 4]
cvtsi2ss xmm5, qword ptr [rcx - 4]
cvtsi2sd xmm5, dword ptr [rcx + 4]
cvttss2si ecx, xmm5
cvttsd2si ecx, xmm5
cvtsi2ss xmm5, ecx
cvtsi2sd xmm5, ecx
cvttss2si rcx, xmm5
cvttsd2si rcx, xmm5
cvtsi2ss xmm5, rcx
cvtsi2sd xmm5, rcx
; Between: xmm5 and rdx
movss dword ptr [rdx - 4], xmm5
movsd qword ptr [rdx + 4], xmm5
movss xmm5, dword ptr [rdx - 4]
movsd xmm5, qword ptr [rdx + 4]
cvtsi2ss xmm5, qword ptr [rdx - 4]
cvtsi2sd xmm5, dword ptr [rdx + 4]
cvttss2si edx, xmm5
cvttsd2si edx, xmm5
cvtsi2ss xmm5, edx
cvtsi2sd xmm5, edx
cvttss2si rdx, xmm5
cvttsd2si rdx, xmm5
cvtsi2ss xmm5, rdx
cvtsi2sd xmm5, rdx
; Between: xmm5 and rbx
movss dword ptr [rbx - 4], xmm5
movsd qword ptr [rbx + 4], xmm5
movss xmm5, dword ptr [rbx - 4]
movsd xmm5, qword ptr [rbx + 4]
cvtsi2ss xmm5, qword ptr [rbx - 4]
cvtsi2sd xmm5, dword ptr [rbx + 4]
cvttss2si ebx, xmm5
cvttsd2si ebx, xmm5
cvtsi2ss xmm5, ebx
cvtsi2sd xmm5, ebx
cvttss2si rbx, xmm5
cvttsd2si rbx, xmm5
cvtsi2ss xmm5, rbx
cvtsi2sd xmm5, rbx
; Between: xmm5 and rsp
movss dword ptr [rsp - 4], xmm5
movsd qword ptr [rsp + 4], xmm5
movss xmm5, dword ptr [rsp - 4]
movsd xmm5, qword ptr [rsp + 4]
cvtsi2ss xmm5, qword ptr [rsp - 4]
cvtsi2sd xmm5, dword ptr [rsp + 4]
cvttss2si esp, xmm5
cvttsd2si esp, xmm5
cvtsi2ss xmm5, esp
cvtsi2sd xmm5, esp
cvttss2si rsp, xmm5
cvttsd2si rsp, xmm5
cvtsi2ss xmm5, rsp
cvtsi2sd xmm5, rsp
; Between: xmm5 and rbp
movss dword ptr [rbp - 4], xmm5
movsd qword ptr [rbp + 4], xmm5
movss xmm5, dword ptr [rbp - 4]
movsd xmm5, qword ptr [rbp + 4]
cvtsi2ss xmm5, qword ptr [rbp - 4]
cvtsi2sd xmm5, dword ptr [rbp + 4]
cvttss2si ebp, xmm5
cvttsd2si ebp, xmm5
cvtsi2ss xmm5, ebp
cvtsi2sd xmm5, ebp
cvttss2si rbp, xmm5
cvttsd2si rbp, xmm5
cvtsi2ss xmm5, rbp
cvtsi2sd xmm5, rbp
; Between: xmm5 and rsi
movss dword ptr [rsi - 4], xmm5
movsd qword ptr [rsi + 4], xmm5
movss xmm5, dword ptr [rsi - 4]
movsd xmm5, qword ptr [rsi + 4]
cvtsi2ss xmm5, qword ptr [rsi - 4]
cvtsi2sd xmm5, dword ptr [rsi + 4]
cvttss2si esi, xmm5
cvttsd2si esi, xmm5
cvtsi2ss xmm5, esi
cvtsi2sd xmm5, esi
cvttss2si rsi, xmm5
cvttsd2si rsi, xmm5
cvtsi2ss xmm5, rsi
cvtsi2sd xmm5, rsi
; Between: xmm5 and rdi
movss dword ptr [rdi - 4], xmm5
movsd qword ptr [rdi + 4], xmm5
movss xmm5, dword ptr [rdi - 4]
movsd xmm5, qword ptr [rdi + 4]
cvtsi2ss xmm5, qword ptr [rdi - 4]
cvtsi2sd xmm5, dword ptr [rdi + 4]
cvttss2si edi, xmm5
cvttsd2si edi, xmm5
cvtsi2ss xmm5, edi
cvtsi2sd xmm5, edi
cvttss2si rdi, xmm5
cvttsd2si rdi, xmm5
cvtsi2ss xmm5, rdi
cvtsi2sd xmm5, rdi
; Between: xmm5 and r8
movss dword ptr [r8 - 4], xmm5
movsd qword ptr [r8 + 4], xmm5
movss xmm5, dword ptr [r8 - 4]
movsd xmm5, qword ptr [r8 + 4]
cvtsi2ss xmm5, qword ptr [r8 - 4]
cvtsi2sd xmm5, dword ptr [r8 + 4]
cvttss2si r8d, xmm5
cvttsd2si r8d, xmm5
cvtsi2ss xmm5, r8d
cvtsi2sd xmm5, r8d
cvttss2si r8, xmm5
cvttsd2si r8, xmm5
cvtsi2ss xmm5, r8
cvtsi2sd xmm5, r8
; Between: xmm5 and r9
movss dword ptr [r9 - 4], xmm5
movsd qword ptr [r9 + 4], xmm5
movss xmm5, dword ptr [r9 - 4]
movsd xmm5, qword ptr [r9 + 4]
cvtsi2ss xmm5, qword ptr [r9 - 4]
cvtsi2sd xmm5, dword ptr [r9 + 4]
cvttss2si r9d, xmm5
cvttsd2si r9d, xmm5
cvtsi2ss xmm5, r9d
cvtsi2sd xmm5, r9d
cvttss2si r9, xmm5
cvttsd2si r9, xmm5
cvtsi2ss xmm5, r9
cvtsi2sd xmm5, r9
; Between: xmm5 and r10
movss dword ptr [r10 - 4], xmm5
movsd qword ptr [r10 + 4], xmm5
movss xmm5, dword ptr [r10 - 4]
movsd xmm5, qword ptr [r10 + 4]
cvtsi2ss xmm5, qword ptr [r10 - 4]
cvtsi2sd xmm5, dword ptr [r10 + 4]
cvttss2si r10d, xmm5
cvttsd2si r10d, xmm5
cvtsi2ss xmm5, r10d
cvtsi2sd xmm5, r10d
cvttss2si r10, xmm5
cvttsd2si r10, xmm5
cvtsi2ss xmm5, r10
cvtsi2sd xmm5, r10
; Between: xmm5 and r11
movss dword ptr [r11 - 4], xmm5
movsd qword ptr [r11 + 4], xmm5
movss xmm5, dword ptr [r11 - 4]
movsd xmm5, qword ptr [r11 + 4]
cvtsi2ss xmm5, qword ptr [r11 - 4]
cvtsi2sd xmm5, dword ptr [r11 + 4]
cvttss2si r11d, xmm5
cvttsd2si r11d, xmm5
cvtsi2ss xmm5, r11d
cvtsi2sd xmm5, r11d
cvttss2si r11, xmm5
cvttsd2si r11, xmm5
cvtsi2ss xmm5, r11
cvtsi2sd xmm5, r11
; Between: xmm5 and r12
movss dword ptr [r12 - 4], xmm5
movsd qword ptr [r12 + 4], xmm5
movss xmm5, dword ptr [r12 - 4]
movsd xmm5, qword ptr [r12 + 4]
cvtsi2ss xmm5, qword ptr [r12 - 4]
cvtsi2sd xmm5, dword ptr [r12 + 4]
cvttss2si r12d, xmm5
cvttsd2si r12d, xmm5
cvtsi2ss xmm5, r12d
cvtsi2sd xmm5, r12d
cvttss2si r12, xmm5
cvttsd2si r12, xmm5
cvtsi2ss xmm5, r12
cvtsi2sd xmm5, r12
; Between: xmm5 and r13
movss dword ptr [r13 - 4], xmm5
movsd qword ptr [r13 + 4], xmm5
movss xmm5, dword ptr [r13 - 4]
movsd xmm5, qword ptr [r13 + 4]
cvtsi2ss xmm5, qword ptr [r13 - 4]
cvtsi2sd xmm5, dword ptr [r13 + 4]
cvttss2si r13d, xmm5
cvttsd2si r13d, xmm5
cvtsi2ss xmm5, r13d
cvtsi2sd xmm5, r13d
cvttss2si r13, xmm5
cvttsd2si r13, xmm5
cvtsi2ss xmm5, r13
cvtsi2sd xmm5, r13
; Between: xmm5 and r14
movss dword ptr [r14 - 4], xmm5
movsd qword ptr [r14 + 4], xmm5
movss xmm5, dword ptr [r14 - 4]
movsd xmm5, qword ptr [r14 + 4]
cvtsi2ss xmm5, qword ptr [r14 - 4]
cvtsi2sd xmm5, dword ptr [r14 + 4]
cvttss2si r14d, xmm5
cvttsd2si r14d, xmm5
cvtsi2ss xmm5, r14d
cvtsi2sd xmm5, r14d
cvttss2si r14, xmm5
cvttsd2si r14, xmm5
cvtsi2ss xmm5, r14
cvtsi2sd xmm5, r14
; Between: xmm5 and r15
movss dword ptr [r15 - 4], xmm5
movsd qword ptr [r15 + 4], xmm5
movss xmm5, dword ptr [r15 - 4]
movsd xmm5, qword ptr [r15 + 4]
cvtsi2ss xmm5, qword ptr [r15 - 4]
cvtsi2sd xmm5, dword ptr [r15 + 4]
cvttss2si r15d, xmm5
cvttsd2si r15d, xmm5
cvtsi2ss xmm5, r15d
cvtsi2sd xmm5, r15d
cvttss2si r15, xmm5
cvttsd2si r15, xmm5
cvtsi2ss xmm5, r15
cvtsi2sd xmm5, r15
; Between: xmm6 and rax
movss dword ptr [rax - 4], xmm6
movsd qword ptr [rax + 4], xmm6
movss xmm6, dword ptr [rax - 4]
movsd xmm6, qword ptr [rax + 4]
cvtsi2ss xmm6, qword ptr [rax - 4]
cvtsi2sd xmm6, dword ptr [rax + 4]
cvttss2si eax, xmm6
cvttsd2si eax, xmm6
cvtsi2ss xmm6, eax
cvtsi2sd xmm6, eax
cvttss2si rax, xmm6
cvttsd2si rax, xmm6
cvtsi2ss xmm6, rax
cvtsi2sd xmm6, rax
; Between: xmm6 and rcx
movss dword ptr [rcx - 4], xmm6
movsd qword ptr [rcx + 4], xmm6
movss xmm6, dword ptr [rcx - 4]
movsd xmm6, qword ptr [rcx + 4]
cvtsi2ss xmm6, qword ptr [rcx - 4]
cvtsi2sd xmm6, dword ptr [rcx + 4]
cvttss2si ecx, xmm6
cvttsd2si ecx, xmm6
cvtsi2ss xmm6, ecx
cvtsi2sd xmm6, ecx
cvttss2si rcx, xmm6
cvttsd2si rcx, xmm6
cvtsi2ss xmm6, rcx
cvtsi2sd xmm6, rcx
; Between: xmm6 and rdx
movss dword ptr [rdx - 4], xmm6
movsd qword ptr [rdx + 4], xmm6
movss xmm6, dword ptr [rdx - 4]
movsd xmm6, qword ptr [rdx + 4]
cvtsi2ss xmm6, qword ptr [rdx - 4]
cvtsi2sd xmm6, dword ptr [rdx + 4]
cvttss2si edx, xmm6
cvttsd2si edx, xmm6
cvtsi2ss xmm6, edx
cvtsi2sd xmm6, edx
cvttss2si rdx, xmm6
cvttsd2si rdx, xmm6
cvtsi2ss xmm6, rdx
cvtsi2sd xmm6, rdx
; Between: xmm6 and rbx
movss dword ptr [rbx - 4], xmm6
movsd qword ptr [rbx + 4], xmm6
movss xmm6, dword ptr [rbx - 4]
movsd xmm6, qword ptr [rbx + 4]
cvtsi2ss xmm6, qword ptr [rbx - 4]
cvtsi2sd xmm6, dword ptr [rbx + 4]
cvttss2si ebx, xmm6
cvttsd2si ebx, xmm6
cvtsi2ss xmm6, ebx
cvtsi2sd xmm6, ebx
cvttss2si rbx, xmm6
cvttsd2si rbx, xmm6
cvtsi2ss xmm6, rbx
cvtsi2sd xmm6, rbx
; Between: xmm6 and rsp
movss dword ptr [rsp - 4], xmm6
movsd qword ptr [rsp + 4], xmm6
movss xmm6, dword ptr [rsp - 4]
movsd xmm6, qword ptr [rsp + 4]
cvtsi2ss xmm6, qword ptr [rsp - 4]
cvtsi2sd xmm6, dword ptr [rsp + 4]
cvttss2si esp, xmm6
cvttsd2si esp, xmm6
cvtsi2ss xmm6, esp
cvtsi2sd xmm6, esp
cvttss2si rsp, xmm6
cvttsd2si rsp, xmm6
cvtsi2ss xmm6, rsp
cvtsi2sd xmm6, rsp
; Between: xmm6 and rbp
movss dword ptr [rbp - 4], xmm6
movsd qword ptr [rbp + 4], xmm6
movss xmm6, dword ptr [rbp - 4]
movsd xmm6, qword ptr [rbp + 4]
cvtsi2ss xmm6, qword ptr [rbp - 4]
cvtsi2sd xmm6, dword ptr [rbp + 4]
cvttss2si ebp, xmm6
cvttsd2si ebp, xmm6
cvtsi2ss xmm6, ebp
cvtsi2sd xmm6, ebp
cvttss2si rbp, xmm6
cvttsd2si rbp, xmm6
cvtsi2ss xmm6, rbp
cvtsi2sd xmm6, rbp
; Between: xmm6 and rsi
movss dword ptr [rsi - 4], xmm6
movsd qword ptr [rsi + 4], xmm6
movss xmm6, dword ptr [rsi - 4]
movsd xmm6, qword ptr [rsi + 4]
cvtsi2ss xmm6, qword ptr [rsi - 4]
cvtsi2sd xmm6, dword ptr [rsi + 4]
cvttss2si esi, xmm6
cvttsd2si esi, xmm6
cvtsi2ss xmm6, esi
cvtsi2sd xmm6, esi
cvttss2si rsi, xmm6
cvttsd2si rsi, xmm6
cvtsi2ss xmm6, rsi
cvtsi2sd xmm6, rsi
; Between: xmm6 and rdi
movss dword ptr [rdi - 4], xmm6
movsd qword ptr [rdi + 4], xmm6
movss xmm6, dword ptr [rdi - 4]
movsd xmm6, qword ptr [rdi + 4]
cvtsi2ss xmm6, qword ptr [rdi - 4]
cvtsi2sd xmm6, dword ptr [rdi + 4]
cvttss2si edi, xmm6
cvttsd2si edi, xmm6
cvtsi2ss xmm6, edi
cvtsi2sd xmm6, edi
cvttss2si rdi, xmm6
cvttsd2si rdi, xmm6
cvtsi2ss xmm6, rdi
cvtsi2sd xmm6, rdi
; Between: xmm6 and r8
movss dword ptr [r8 - 4], xmm6
movsd qword ptr [r8 + 4], xmm6
movss xmm6, dword ptr [r8 - 4]
movsd xmm6, qword ptr [r8 + 4]
cvtsi2ss xmm6, qword ptr [r8 - 4]
cvtsi2sd xmm6, dword ptr [r8 + 4]
cvttss2si r8d, xmm6
cvttsd2si r8d, xmm6
cvtsi2ss xmm6, r8d
cvtsi2sd xmm6, r8d
cvttss2si r8, xmm6
cvttsd2si r8, xmm6
cvtsi2ss xmm6, r8
cvtsi2sd xmm6, r8
; Between: xmm6 and r9
movss dword ptr [r9 - 4], xmm6
movsd qword ptr [r9 + 4], xmm6
movss xmm6, dword ptr [r9 - 4]
movsd xmm6, qword ptr [r9 + 4]
cvtsi2ss xmm6, qword ptr [r9 - 4]
cvtsi2sd xmm6, dword ptr [r9 + 4]
cvttss2si r9d, xmm6
cvttsd2si r9d, xmm6
cvtsi2ss xmm6, r9d
cvtsi2sd xmm6, r9d
cvttss2si r9, xmm6
cvttsd2si r9, xmm6
cvtsi2ss xmm6, r9
cvtsi2sd xmm6, r9
; Between: xmm6 and r10
movss dword ptr [r10 - 4], xmm6
movsd qword ptr [r10 + 4], xmm6
movss xmm6, dword ptr [r10 - 4]
movsd xmm6, qword ptr [r10 + 4]
cvtsi2ss xmm6, qword ptr [r10 - 4]
cvtsi2sd xmm6, dword ptr [r10 + 4]
cvttss2si r10d, xmm6
cvttsd2si r10d, xmm6
cvtsi2ss xmm6, r10d
cvtsi2sd xmm6, r10d
cvttss2si r10, xmm6
cvttsd2si r10, xmm6
cvtsi2ss xmm6, r10
cvtsi2sd xmm6, r10
; Between: xmm6 and r11
movss dword ptr [r11 - 4], xmm6
movsd qword ptr [r11 + 4], xmm6
movss xmm6, dword ptr [r11 - 4]
movsd xmm6, qword ptr [r11 + 4]
cvtsi2ss xmm6, qword ptr [r11 - 4]
cvtsi2sd xmm6, dword ptr [r11 + 4]
cvttss2si r11d, xmm6
cvttsd2si r11d, xmm6
cvtsi2ss xmm6, r11d
cvtsi2sd xmm6, r11d
cvttss2si r11, xmm6
cvttsd2si r11, xmm6
cvtsi2ss xmm6, r11
cvtsi2sd xmm6, r11
; Between: xmm6 and r12
movss dword ptr [r12 - 4], xmm6
movsd qword ptr [r12 + 4], xmm6
movss xmm6, dword ptr [r12 - 4]
movsd xmm6, qword ptr [r12 + 4]
cvtsi2ss xmm6, qword ptr [r12 - 4]
cvtsi2sd xmm6, dword ptr [r12 + 4]
cvttss2si r12d, xmm6
cvttsd2si r12d, xmm6
cvtsi2ss xmm6, r12d
cvtsi2sd xmm6, r12d
cvttss2si r12, xmm6
cvttsd2si r12, xmm6
cvtsi2ss xmm6, r12
cvtsi2sd xmm6, r12
; Between: xmm6 and r13
movss dword ptr [r13 - 4], xmm6
movsd qword ptr [r13 + 4], xmm6
movss xmm6, dword ptr [r13 - 4]
movsd xmm6, qword ptr [r13 + 4]
cvtsi2ss xmm6, qword ptr [r13 - 4]
cvtsi2sd xmm6, dword ptr [r13 + 4]
cvttss2si r13d, xmm6
cvttsd2si r13d, xmm6
cvtsi2ss xmm6, r13d
cvtsi2sd xmm6, r13d
cvttss2si r13, xmm6
cvttsd2si r13, xmm6
cvtsi2ss xmm6, r13
cvtsi2sd xmm6, r13
; Between: xmm6 and r14
movss dword ptr [r14 - 4], xmm6
movsd qword ptr [r14 + 4], xmm6
movss xmm6, dword ptr [r14 - 4]
movsd xmm6, qword ptr [r14 + 4]
cvtsi2ss xmm6, qword ptr [r14 - 4]
cvtsi2sd xmm6, dword ptr [r14 + 4]
cvttss2si r14d, xmm6
cvttsd2si r14d, xmm6
cvtsi2ss xmm6, r14d
cvtsi2sd xmm6, r14d
cvttss2si r14, xmm6
cvttsd2si r14, xmm6
cvtsi2ss xmm6, r14
cvtsi2sd xmm6, r14
; Between: xmm6 and r15
movss dword ptr [r15 - 4], xmm6
movsd qword ptr [r15 + 4], xmm6
movss xmm6, dword ptr [r15 - 4]
movsd xmm6, qword ptr [r15 + 4]
cvtsi2ss xmm6, qword ptr [r15 - 4]
cvtsi2sd xmm6, dword ptr [r15 + 4]
cvttss2si r15d, xmm6
cvttsd2si r15d, xmm6
cvtsi2ss xmm6, r15d
cvtsi2sd xmm6, r15d
cvttss2si r15, xmm6
cvttsd2si r15, xmm6
cvtsi2ss xmm6, r15
cvtsi2sd xmm6, r15
; Between: xmm7 and rax
movss dword ptr [rax - 4], xmm7
movsd qword ptr [rax + 4], xmm7
movss xmm7, dword ptr [rax - 4]
movsd xmm7, qword ptr [rax + 4]
cvtsi2ss xmm7, qword ptr [rax - 4]
cvtsi2sd xmm7, dword ptr [rax + 4]
cvttss2si eax, xmm7
cvttsd2si eax, xmm7
cvtsi2ss xmm7, eax
cvtsi2sd xmm7, eax
cvttss2si rax, xmm7
cvttsd2si rax, xmm7
cvtsi2ss xmm7, rax
cvtsi2sd xmm7, rax
; Between: xmm7 and rcx
movss dword ptr [rcx - 4], xmm7
movsd qword ptr [rcx + 4], xmm7
movss xmm7, dword ptr [rcx - 4]
movsd xmm7, qword ptr [rcx + 4]
cvtsi2ss xmm7, qword ptr [rcx - 4]
cvtsi2sd xmm7, dword ptr [rcx + 4]
cvttss2si ecx, xmm7
cvttsd2si ecx, xmm7
cvtsi2ss xmm7, ecx
cvtsi2sd xmm7, ecx
cvttss2si rcx, xmm7
cvttsd2si rcx, xmm7
cvtsi2ss xmm7, rcx
cvtsi2sd xmm7, rcx
; Between: xmm7 and rdx
movss dword ptr [rdx - 4], xmm7
movsd qword ptr [rdx + 4], xmm7
movss xmm7, dword ptr [rdx - 4]
movsd xmm7, qword ptr [rdx + 4]
cvtsi2ss xmm7, qword ptr [rdx - 4]
cvtsi2sd xmm7, dword ptr [rdx + 4]
cvttss2si edx, xmm7
cvttsd2si edx, xmm7
cvtsi2ss xmm7, edx
cvtsi2sd xmm7, edx
cvttss2si rdx, xmm7
cvttsd2si rdx, xmm7
cvtsi2ss xmm7, rdx
cvtsi2sd xmm7, rdx
; Between: xmm7 and rbx
movss dword ptr [rbx - 4], xmm7
movsd qword ptr [rbx + 4], xmm7
movss xmm7, dword ptr [rbx - 4]
movsd xmm7, qword ptr [rbx + 4]
cvtsi2ss xmm7, qword ptr [rbx - 4]
cvtsi2sd xmm7, dword ptr [rbx + 4]
cvttss2si ebx, xmm7
cvttsd2si ebx, xmm7
cvtsi2ss xmm7, ebx
cvtsi2sd xmm7, ebx
cvttss2si rbx, xmm7
cvttsd2si rbx, xmm7
cvtsi2ss xmm7, rbx
cvtsi2sd xmm7, rbx
; Between: xmm7 and rsp
movss dword ptr [rsp - 4], xmm7
movsd qword ptr [rsp + 4], xmm7
movss xmm7, dword ptr [rsp - 4]
movsd xmm7, qword ptr [rsp + 4]
cvtsi2ss xmm7, qword ptr [rsp - 4]
cvtsi2sd xmm7, dword ptr [rsp + 4]
cvttss2si esp, xmm7
cvttsd2si esp, xmm7
cvtsi2ss xmm7, esp
cvtsi2sd xmm7, esp
cvttss2si rsp, xmm7
cvttsd2si rsp, xmm7
cvtsi2ss xmm7, rsp
cvtsi2sd xmm7, rsp
; Between: xmm7 and rbp
movss dword ptr [rbp - 4], xmm7
movsd qword ptr [rbp + 4], xmm7
movss xmm7, dword ptr [rbp - 4]
movsd xmm7, qword ptr [rbp + 4]
cvtsi2ss xmm7, qword ptr [rbp - 4]
cvtsi2sd xmm7, dword ptr [rbp + 4]
cvttss2si ebp, xmm7
cvttsd2si ebp, xmm7
cvtsi2ss xmm7, ebp
cvtsi2sd xmm7, ebp
cvttss2si rbp, xmm7
cvttsd2si rbp, xmm7
cvtsi2ss xmm7, rbp
cvtsi2sd xmm7, rbp
; Between: xmm7 and rsi
movss dword ptr [rsi - 4], xmm7
movsd qword ptr [rsi + 4], xmm7
movss xmm7, dword ptr [rsi - 4]
movsd xmm7, qword ptr [rsi + 4]
cvtsi2ss xmm7, qword ptr [rsi - 4]
cvtsi2sd xmm7, dword ptr [rsi + 4]
cvttss2si esi, xmm7
cvttsd2si esi, xmm7
cvtsi2ss xmm7, esi
cvtsi2sd xmm7, esi
cvttss2si rsi, xmm7
cvttsd2si rsi, xmm7
cvtsi2ss xmm7, rsi
cvtsi2sd xmm7, rsi
; Between: xmm7 and rdi
movss dword ptr [rdi - 4], xmm7
movsd qword ptr [rdi + 4], xmm7
movss xmm7, dword ptr [rdi - 4]
movsd xmm7, qword ptr [rdi + 4]
cvtsi2ss xmm7, qword ptr [rdi - 4]
cvtsi2sd xmm7, dword ptr [rdi + 4]
cvttss2si edi, xmm7
cvttsd2si edi, xmm7
cvtsi2ss xmm7, edi
cvtsi2sd xmm7, edi
cvttss2si rdi, xmm7
cvttsd2si rdi, xmm7
cvtsi2ss xmm7, rdi
cvtsi2sd xmm7, rdi
; Between: xmm7 and r8
movss dword ptr [r8 - 4], xmm7
movsd qword ptr [r8 + 4], xmm7
movss xmm7, dword ptr [r8 - 4]
movsd xmm7, qword ptr [r8 + 4]
cvtsi2ss xmm7, qword ptr [r8 - 4]
cvtsi2sd xmm7, dword ptr [r8 + 4]
cvttss2si r8d, xmm7
cvttsd2si r8d, xmm7
cvtsi2ss xmm7, r8d
cvtsi2sd xmm7, r8d
cvttss2si r8, xmm7
cvttsd2si r8, xmm7
cvtsi2ss xmm7, r8
cvtsi2sd xmm7, r8
; Between: xmm7 and r9
movss dword ptr [r9 - 4], xmm7
movsd qword ptr [r9 + 4], xmm7
movss xmm7, dword ptr [r9 - 4]
movsd xmm7, qword ptr [r9 + 4]
cvtsi2ss xmm7, qword ptr [r9 - 4]
cvtsi2sd xmm7, dword ptr [r9 + 4]
cvttss2si r9d, xmm7
cvttsd2si r9d, xmm7
cvtsi2ss xmm7, r9d
cvtsi2sd xmm7, r9d
cvttss2si r9, xmm7
cvttsd2si r9, xmm7
cvtsi2ss xmm7, r9
cvtsi2sd xmm7, r9
; Between: xmm7 and r10
movss dword ptr [r10 - 4], xmm7
movsd qword ptr [r10 + 4], xmm7
movss xmm7, dword ptr [r10 - 4]
movsd xmm7, qword ptr [r10 + 4]
cvtsi2ss xmm7, qword ptr [r10 - 4]
cvtsi2sd xmm7, dword ptr [r10 + 4]
cvttss2si r10d, xmm7
cvttsd2si r10d, xmm7
cvtsi2ss xmm7, r10d
cvtsi2sd xmm7, r10d
cvttss2si r10, xmm7
cvttsd2si r10, xmm7
cvtsi2ss xmm7, r10
cvtsi2sd xmm7, r10
; Between: xmm7 and r11
movss dword ptr [r11 - 4], xmm7
movsd qword ptr [r11 + 4], xmm7
movss xmm7, dword ptr [r11 - 4]
movsd xmm7, qword ptr [r11 + 4]
cvtsi2ss xmm7, qword ptr [r11 - 4]
cvtsi2sd xmm7, dword ptr [r11 + 4]
cvttss2si r11d, xmm7
cvttsd2si r11d, xmm7
cvtsi2ss xmm7, r11d
cvtsi2sd xmm7, r11d
cvttss2si r11, xmm7
cvttsd2si r11, xmm7
cvtsi2ss xmm7, r11
cvtsi2sd xmm7, r11
; Between: xmm7 and r12
movss dword ptr [r12 - 4], xmm7
movsd qword ptr [r12 + 4], xmm7
movss xmm7, dword ptr [r12 - 4]
movsd xmm7, qword ptr [r12 + 4]
cvtsi2ss xmm7, qword ptr [r12 - 4]
cvtsi2sd xmm7, dword ptr [r12 + 4]
cvttss2si r12d, xmm7
cvttsd2si r12d, xmm7
cvtsi2ss xmm7, r12d
cvtsi2sd xmm7, r12d
cvttss2si r12, xmm7
cvttsd2si r12, xmm7
cvtsi2ss xmm7, r12
cvtsi2sd xmm7, r12
; Between: xmm7 and r13
movss dword ptr [r13 - 4], xmm7
movsd qword ptr [r13 + 4], xmm7
movss xmm7, dword ptr [r13 - 4]
movsd xmm7, qword ptr [r13 + 4]
cvtsi2ss xmm7, qword ptr [r13 - 4]
cvtsi2sd xmm7, dword ptr [r13 + 4]
cvttss2si r13d, xmm7
cvttsd2si r13d, xmm7
cvtsi2ss xmm7, r13d
cvtsi2sd xmm7, r13d
cvttss2si r13, xmm7
cvttsd2si r13, xmm7
cvtsi2ss xmm7, r13
cvtsi2sd xmm7, r13
; Between: xmm7 and r14
movss dword ptr [r14 - 4], xmm7
movsd qword ptr [r14 + 4], xmm7
movss xmm7, dword ptr [r14 - 4]
movsd xmm7, qword ptr [r14 + 4]
cvtsi2ss xmm7, qword ptr [r14 - 4]
cvtsi2sd xmm7, dword ptr [r14 + 4]
cvttss2si r14d, xmm7
cvttsd2si r14d, xmm7
cvtsi2ss xmm7, r14d
cvtsi2sd xmm7, r14d
cvttss2si r14, xmm7
cvttsd2si r14, xmm7
cvtsi2ss xmm7, r14
cvtsi2sd xmm7, r14
; Between: xmm7 and r15
movss dword ptr [r15 - 4], xmm7
movsd qword ptr [r15 + 4], xmm7
movss xmm7, dword ptr [r15 - 4]
movsd xmm7, qword ptr [r15 + 4]
cvtsi2ss xmm7, qword ptr [r15 - 4]
cvtsi2sd xmm7, dword ptr [r15 + 4]
cvttss2si r15d, xmm7
cvttsd2si r15d, xmm7
cvtsi2ss xmm7, r15d
cvtsi2sd xmm7, r15d
cvttss2si r15, xmm7
cvttsd2si r15, xmm7
cvtsi2ss xmm7, r15
cvtsi2sd xmm7, r15
; Between: xmm8 and rax
movss dword ptr [rax - 4], xmm8
movsd qword ptr [rax + 4], xmm8
movss xmm8, dword ptr [rax - 4]
movsd xmm8, qword ptr [rax + 4]
cvtsi2ss xmm8, qword ptr [rax - 4]
cvtsi2sd xmm8, dword ptr [rax + 4]
cvttss2si eax, xmm8
cvttsd2si eax, xmm8
cvtsi2ss xmm8, eax
cvtsi2sd xmm8, eax
cvttss2si rax, xmm8
cvttsd2si rax, xmm8
cvtsi2ss xmm8, rax
cvtsi2sd xmm8, rax
; Between: xmm8 and rcx
movss dword ptr [rcx - 4], xmm8
movsd qword ptr [rcx + 4], xmm8
movss xmm8, dword ptr [rcx - 4]
movsd xmm8, qword ptr [rcx + 4]
cvtsi2ss xmm8, qword ptr [rcx - 4]
cvtsi2sd xmm8, dword ptr [rcx + 4]
cvttss2si ecx, xmm8
cvttsd2si ecx, xmm8
cvtsi2ss xmm8, ecx
cvtsi2sd xmm8, ecx
cvttss2si rcx, xmm8
cvttsd2si rcx, xmm8
cvtsi2ss xmm8, rcx
cvtsi2sd xmm8, rcx
; Between: xmm8 and rdx
movss dword ptr [rdx - 4], xmm8
movsd qword ptr [rdx + 4], xmm8
movss xmm8, dword ptr [rdx - 4]
movsd xmm8, qword ptr [rdx + 4]
cvtsi2ss xmm8, qword ptr [rdx - 4]
cvtsi2sd xmm8, dword ptr [rdx + 4]
cvttss2si edx, xmm8
cvttsd2si edx, xmm8
cvtsi2ss xmm8, edx
cvtsi2sd xmm8, edx
cvttss2si rdx, xmm8
cvttsd2si rdx, xmm8
cvtsi2ss xmm8, rdx
cvtsi2sd xmm8, rdx
; Between: xmm8 and rbx
movss dword ptr [rbx - 4], xmm8
movsd qword ptr [rbx + 4], xmm8
movss xmm8, dword ptr [rbx - 4]
movsd xmm8, qword ptr [rbx + 4]
cvtsi2ss xmm8, qword ptr [rbx - 4]
cvtsi2sd xmm8, dword ptr [rbx + 4]
cvttss2si ebx, xmm8
cvttsd2si ebx, xmm8
cvtsi2ss xmm8, ebx
cvtsi2sd xmm8, ebx
cvttss2si rbx, xmm8
cvttsd2si rbx, xmm8
cvtsi2ss xmm8, rbx
cvtsi2sd xmm8, rbx
; Between: xmm8 and rsp
movss dword ptr [rsp - 4], xmm8
movsd qword ptr [rsp + 4], xmm8
movss xmm8, dword ptr [rsp - 4]
movsd xmm8, qword ptr [rsp + 4]
cvtsi2ss xmm8, qword ptr [rsp - 4]
cvtsi2sd xmm8, dword ptr [rsp + 4]
cvttss2si esp, xmm8
cvttsd2si esp, xmm8
cvtsi2ss xmm8, esp
cvtsi2sd xmm8, esp
cvttss2si rsp, xmm8
cvttsd2si rsp, xmm8
cvtsi2ss xmm8, rsp
cvtsi2sd xmm8, rsp
; Between: xmm8 and rbp
movss dword ptr [rbp - 4], xmm8
movsd qword ptr [rbp + 4], xmm8
movss xmm8, dword ptr [rbp - 4]
movsd xmm8, qword ptr [rbp + 4]
cvtsi2ss xmm8, qword ptr [rbp - 4]
cvtsi2sd xmm8, dword ptr [rbp + 4]
cvttss2si ebp, xmm8
cvttsd2si ebp, xmm8
cvtsi2ss xmm8, ebp
cvtsi2sd xmm8, ebp
cvttss2si rbp, xmm8
cvttsd2si rbp, xmm8
cvtsi2ss xmm8, rbp
cvtsi2sd xmm8, rbp
; Between: xmm8 and rsi
movss dword ptr [rsi - 4], xmm8
movsd qword ptr [rsi + 4], xmm8
movss xmm8, dword ptr [rsi - 4]
movsd xmm8, qword ptr [rsi + 4]
cvtsi2ss xmm8, qword ptr [rsi - 4]
cvtsi2sd xmm8, dword ptr [rsi + 4]
cvttss2si esi, xmm8
cvttsd2si esi, xmm8
cvtsi2ss xmm8, esi
cvtsi2sd xmm8, esi
cvttss2si rsi, xmm8
cvttsd2si rsi, xmm8
cvtsi2ss xmm8, rsi
cvtsi2sd xmm8, rsi
; Between: xmm8 and rdi
movss dword ptr [rdi - 4], xmm8
movsd qword ptr [rdi + 4], xmm8
movss xmm8, dword ptr [rdi - 4]
movsd xmm8, qword ptr [rdi + 4]
cvtsi2ss xmm8, qword ptr [rdi - 4]
cvtsi2sd xmm8, dword ptr [rdi + 4]
cvttss2si edi, xmm8
cvttsd2si edi, xmm8
cvtsi2ss xmm8, edi
cvtsi2sd xmm8, edi
cvttss2si rdi, xmm8
cvttsd2si rdi, xmm8
cvtsi2ss xmm8, rdi
cvtsi2sd xmm8, rdi
; Between: xmm8 and r8
movss dword ptr [r8 - 4], xmm8
movsd qword ptr [r8 + 4], xmm8
movss xmm8, dword ptr [r8 - 4]
movsd xmm8, qword ptr [r8 + 4]
cvtsi2ss xmm8, qword ptr [r8 - 4]
cvtsi2sd xmm8, dword ptr [r8 + 4]
cvttss2si r8d, xmm8
cvttsd2si r8d, xmm8
cvtsi2ss xmm8, r8d
cvtsi2sd xmm8, r8d
cvttss2si r8, xmm8
cvttsd2si r8, xmm8
cvtsi2ss xmm8, r8
cvtsi2sd xmm8, r8
; Between: xmm8 and r9
movss dword ptr [r9 - 4], xmm8
movsd qword ptr [r9 + 4], xmm8
movss xmm8, dword ptr [r9 - 4]
movsd xmm8, qword ptr [r9 + 4]
cvtsi2ss xmm8, qword ptr [r9 - 4]
cvtsi2sd xmm8, dword ptr [r9 + 4]
cvttss2si r9d, xmm8
cvttsd2si r9d, xmm8
cvtsi2ss xmm8, r9d
cvtsi2sd xmm8, r9d
cvttss2si r9, xmm8
cvttsd2si r9, xmm8
cvtsi2ss xmm8, r9
cvtsi2sd xmm8, r9
; Between: xmm8 and r10
movss dword ptr [r10 - 4], xmm8
movsd qword ptr [r10 + 4], xmm8
movss xmm8, dword ptr [r10 - 4]
movsd xmm8, qword ptr [r10 + 4]
cvtsi2ss xmm8, qword ptr [r10 - 4]
cvtsi2sd xmm8, dword ptr [r10 + 4]
cvttss2si r10d, xmm8
cvttsd2si r10d, xmm8
cvtsi2ss xmm8, r10d
cvtsi2sd xmm8, r10d
cvttss2si r10, xmm8
cvttsd2si r10, xmm8
cvtsi2ss xmm8, r10
cvtsi2sd xmm8, r10
; Between: xmm8 and r11
movss dword ptr [r11 - 4], xmm8
movsd qword ptr [r11 + 4], xmm8
movss xmm8, dword ptr [r11 - 4]
movsd xmm8, qword ptr [r11 + 4]
cvtsi2ss xmm8, qword ptr [r11 - 4]
cvtsi2sd xmm8, dword ptr [r11 + 4]
cvttss2si r11d, xmm8
cvttsd2si r11d, xmm8
cvtsi2ss xmm8, r11d
cvtsi2sd xmm8, r11d
cvttss2si r11, xmm8
cvttsd2si r11, xmm8
cvtsi2ss xmm8, r11
cvtsi2sd xmm8, r11
; Between: xmm8 and r12
movss dword ptr [r12 - 4], xmm8
movsd qword ptr [r12 + 4], xmm8
movss xmm8, dword ptr [r12 - 4]
movsd xmm8, qword ptr [r12 + 4]
cvtsi2ss xmm8, qword ptr [r12 - 4]
cvtsi2sd xmm8, dword ptr [r12 + 4]
cvttss2si r12d, xmm8
cvttsd2si r12d, xmm8
cvtsi2ss xmm8, r12d
cvtsi2sd xmm8, r12d
cvttss2si r12, xmm8
cvttsd2si r12, xmm8
cvtsi2ss xmm8, r12
cvtsi2sd xmm8, r12
; Between: xmm8 and r13
movss dword ptr [r13 - 4], xmm8
movsd qword ptr [r13 + 4], xmm8
movss xmm8, dword ptr [r13 - 4]
movsd xmm8, qword ptr [r13 + 4]
cvtsi2ss xmm8, qword ptr [r13 - 4]
cvtsi2sd xmm8, dword ptr [r13 + 4]
cvttss2si r13d, xmm8
cvttsd2si r13d, xmm8
cvtsi2ss xmm8, r13d
cvtsi2sd xmm8, r13d
cvttss2si r13, xmm8
cvttsd2si r13, xmm8
cvtsi2ss xmm8, r13
cvtsi2sd xmm8, r13
; Between: xmm8 and r14
movss dword ptr [r14 - 4], xmm8
movsd qword ptr [r14 + 4], xmm8
movss xmm8, dword ptr [r14 - 4]
movsd xmm8, qword ptr [r14 + 4]
cvtsi2ss xmm8, qword ptr [r14 - 4]
cvtsi2sd xmm8, dword ptr [r14 + 4]
cvttss2si r14d, xmm8
cvttsd2si r14d, xmm8
cvtsi2ss xmm8, r14d
cvtsi2sd xmm8, r14d
cvttss2si r14, xmm8
cvttsd2si r14, xmm8
cvtsi2ss xmm8, r14
cvtsi2sd xmm8, r14
; Between: xmm8 and r15
movss dword ptr [r15 - 4], xmm8
movsd qword ptr [r15 + 4], xmm8
movss xmm8, dword ptr [r15 - 4]
movsd xmm8, qword ptr [r15 + 4]
cvtsi2ss xmm8, qword ptr [r15 - 4]
cvtsi2sd xmm8, dword ptr [r15 + 4]
cvttss2si r15d, xmm8
cvttsd2si r15d, xmm8
cvtsi2ss xmm8, r15d
cvtsi2sd xmm8, r15d
cvttss2si r15, xmm8
cvttsd2si r15, xmm8
cvtsi2ss xmm8, r15
cvtsi2sd xmm8, r15
; Between: xmm9 and rax
movss dword ptr [rax - 4], xmm9
movsd qword ptr [rax + 4], xmm9
movss xmm9, dword ptr [rax - 4]
movsd xmm9, qword ptr [rax + 4]
cvtsi2ss xmm9, qword ptr [rax - 4]
cvtsi2sd xmm9, dword ptr [rax + 4]
cvttss2si eax, xmm9
cvttsd2si eax, xmm9
cvtsi2ss xmm9, eax
cvtsi2sd xmm9, eax
cvttss2si rax, xmm9
cvttsd2si rax, xmm9
cvtsi2ss xmm9, rax
cvtsi2sd xmm9, rax
; Between: xmm9 and rcx
movss dword ptr [rcx - 4], xmm9
movsd qword ptr [rcx + 4], xmm9
movss xmm9, dword ptr [rcx - 4]
movsd xmm9, qword ptr [rcx + 4]
cvtsi2ss xmm9, qword ptr [rcx - 4]
cvtsi2sd xmm9, dword ptr [rcx + 4]
cvttss2si ecx, xmm9
cvttsd2si ecx, xmm9
cvtsi2ss xmm9, ecx
cvtsi2sd xmm9, ecx
cvttss2si rcx, xmm9
cvttsd2si rcx, xmm9
cvtsi2ss xmm9, rcx
cvtsi2sd xmm9, rcx
; Between: xmm9 and rdx
movss dword ptr [rdx - 4], xmm9
movsd qword ptr [rdx + 4], xmm9
movss xmm9, dword ptr [rdx - 4]
movsd xmm9, qword ptr [rdx + 4]
cvtsi2ss xmm9, qword ptr [rdx - 4]
cvtsi2sd xmm9, dword ptr [rdx + 4]
cvttss2si edx, xmm9
cvttsd2si edx, xmm9
cvtsi2ss xmm9, edx
cvtsi2sd xmm9, edx
cvttss2si rdx, xmm9
cvttsd2si rdx, xmm9
cvtsi2ss xmm9, rdx
cvtsi2sd xmm9, rdx
; Between: xmm9 and rbx
movss dword ptr [rbx - 4], xmm9
movsd qword ptr [rbx + 4], xmm9
movss xmm9, dword ptr [rbx - 4]
movsd xmm9, qword ptr [rbx + 4]
cvtsi2ss xmm9, qword ptr [rbx - 4]
cvtsi2sd xmm9, dword ptr [rbx + 4]
cvttss2si ebx, xmm9
cvttsd2si ebx, xmm9
cvtsi2ss xmm9, ebx
cvtsi2sd xmm9, ebx
cvttss2si rbx, xmm9
cvttsd2si rbx, xmm9
cvtsi2ss xmm9, rbx
cvtsi2sd xmm9, rbx
; Between: xmm9 and rsp
movss dword ptr [rsp - 4], xmm9
movsd qword ptr [rsp + 4], xmm9
movss xmm9, dword ptr [rsp - 4]
movsd xmm9, qword ptr [rsp + 4]
cvtsi2ss xmm9, qword ptr [rsp - 4]
cvtsi2sd xmm9, dword ptr [rsp + 4]
cvttss2si esp, xmm9
cvttsd2si esp, xmm9
cvtsi2ss xmm9, esp
cvtsi2sd xmm9, esp
cvttss2si rsp, xmm9
cvttsd2si rsp, xmm9
cvtsi2ss xmm9, rsp
cvtsi2sd xmm9, rsp
; Between: xmm9 and rbp
movss dword ptr [rbp - 4], xmm9
movsd qword ptr [rbp + 4], xmm9
movss xmm9, dword ptr [rbp - 4]
movsd xmm9, qword ptr [rbp + 4]
cvtsi2ss xmm9, qword ptr [rbp - 4]
cvtsi2sd xmm9, dword ptr [rbp + 4]
cvttss2si ebp, xmm9
cvttsd2si ebp, xmm9
cvtsi2ss xmm9, ebp
cvtsi2sd xmm9, ebp
cvttss2si rbp, xmm9
cvttsd2si rbp, xmm9
cvtsi2ss xmm9, rbp
cvtsi2sd xmm9, rbp
; Between: xmm9 and rsi
movss dword ptr [rsi - 4], xmm9
movsd qword ptr [rsi + 4], xmm9
movss xmm9, dword ptr [rsi - 4]
movsd xmm9, qword ptr [rsi + 4]
cvtsi2ss xmm9, qword ptr [rsi - 4]
cvtsi2sd xmm9, dword ptr [rsi + 4]
cvttss2si esi, xmm9
cvttsd2si esi, xmm9
cvtsi2ss xmm9, esi
cvtsi2sd xmm9, esi
cvttss2si rsi, xmm9
cvttsd2si rsi, xmm9
cvtsi2ss xmm9, rsi
cvtsi2sd xmm9, rsi
; Between: xmm9 and rdi
movss dword ptr [rdi - 4], xmm9
movsd qword ptr [rdi + 4], xmm9
movss xmm9, dword ptr [rdi - 4]
movsd xmm9, qword ptr [rdi + 4]
cvtsi2ss xmm9, qword ptr [rdi - 4]
cvtsi2sd xmm9, dword ptr [rdi + 4]
cvttss2si edi, xmm9
cvttsd2si edi, xmm9
cvtsi2ss xmm9, edi
cvtsi2sd xmm9, edi
cvttss2si rdi, xmm9
cvttsd2si rdi, xmm9
cvtsi2ss xmm9, rdi
cvtsi2sd xmm9, rdi
; Between: xmm9 and r8
movss dword ptr [r8 - 4], xmm9
movsd qword ptr [r8 + 4], xmm9
movss xmm9, dword ptr [r8 - 4]
movsd xmm9, qword ptr [r8 + 4]
cvtsi2ss xmm9, qword ptr [r8 - 4]
cvtsi2sd xmm9, dword ptr [r8 + 4]
cvttss2si r8d, xmm9
cvttsd2si r8d, xmm9
cvtsi2ss xmm9, r8d
cvtsi2sd xmm9, r8d
cvttss2si r8, xmm9
cvttsd2si r8, xmm9
cvtsi2ss xmm9, r8
cvtsi2sd xmm9, r8
; Between: xmm9 and r9
movss dword ptr [r9 - 4], xmm9
movsd qword ptr [r9 + 4], xmm9
movss xmm9, dword ptr [r9 - 4]
movsd xmm9, qword ptr [r9 + 4]
cvtsi2ss xmm9, qword ptr [r9 - 4]
cvtsi2sd xmm9, dword ptr [r9 + 4]
cvttss2si r9d, xmm9
cvttsd2si r9d, xmm9
cvtsi2ss xmm9, r9d
cvtsi2sd xmm9, r9d
cvttss2si r9, xmm9
cvttsd2si r9, xmm9
cvtsi2ss xmm9, r9
cvtsi2sd xmm9, r9
; Between: xmm9 and r10
movss dword ptr [r10 - 4], xmm9
movsd qword ptr [r10 + 4], xmm9
movss xmm9, dword ptr [r10 - 4]
movsd xmm9, qword ptr [r10 + 4]
cvtsi2ss xmm9, qword ptr [r10 - 4]
cvtsi2sd xmm9, dword ptr [r10 + 4]
cvttss2si r10d, xmm9
cvttsd2si r10d, xmm9
cvtsi2ss xmm9, r10d
cvtsi2sd xmm9, r10d
cvttss2si r10, xmm9
cvttsd2si r10, xmm9
cvtsi2ss xmm9, r10
cvtsi2sd xmm9, r10
; Between: xmm9 and r11
movss dword ptr [r11 - 4], xmm9
movsd qword ptr [r11 + 4], xmm9
movss xmm9, dword ptr [r11 - 4]
movsd xmm9, qword ptr [r11 + 4]
cvtsi2ss xmm9, qword ptr [r11 - 4]
cvtsi2sd xmm9, dword ptr [r11 + 4]
cvttss2si r11d, xmm9
cvttsd2si r11d, xmm9
cvtsi2ss xmm9, r11d
cvtsi2sd xmm9, r11d
cvttss2si r11, xmm9
cvttsd2si r11, xmm9
cvtsi2ss xmm9, r11
cvtsi2sd xmm9, r11
; Between: xmm9 and r12
movss dword ptr [r12 - 4], xmm9
movsd qword ptr [r12 + 4], xmm9
movss xmm9, dword ptr [r12 - 4]
movsd xmm9, qword ptr [r12 + 4]
cvtsi2ss xmm9, qword ptr [r12 - 4]
cvtsi2sd xmm9, dword ptr [r12 + 4]
cvttss2si r12d, xmm9
cvttsd2si r12d, xmm9
cvtsi2ss xmm9, r12d
cvtsi2sd xmm9, r12d
cvttss2si r12, xmm9
cvttsd2si r12, xmm9
cvtsi2ss xmm9, r12
cvtsi2sd xmm9, r12
; Between: xmm9 and r13
movss dword ptr [r13 - 4], xmm9
movsd qword ptr [r13 + 4], xmm9
movss xmm9, dword ptr [r13 - 4]
movsd xmm9, qword ptr [r13 + 4]
cvtsi2ss xmm9, qword ptr [r13 - 4]
cvtsi2sd xmm9, dword ptr [r13 + 4]
cvttss2si r13d, xmm9
cvttsd2si r13d, xmm9
cvtsi2ss xmm9, r13d
cvtsi2sd xmm9, r13d
cvttss2si r13, xmm9
cvttsd2si r13, xmm9
cvtsi2ss xmm9, r13
cvtsi2sd xmm9, r13
; Between: xmm9 and r14
movss dword ptr [r14 - 4], xmm9
movsd qword ptr [r14 + 4], xmm9
movss xmm9, dword ptr [r14 - 4]
movsd xmm9, qword ptr [r14 + 4]
cvtsi2ss xmm9, qword ptr [r14 - 4]
cvtsi2sd xmm9, dword ptr [r14 + 4]
cvttss2si r14d, xmm9
cvttsd2si r14d, xmm9
cvtsi2ss xmm9, r14d
cvtsi2sd xmm9, r14d
cvttss2si r14, xmm9
cvttsd2si r14, xmm9
cvtsi2ss xmm9, r14
cvtsi2sd xmm9, r14
; Between: xmm9 and r15
movss dword ptr [r15 - 4], xmm9
movsd qword ptr [r15 + 4], xmm9
movss xmm9, dword ptr [r15 - 4]
movsd xmm9, qword ptr [r15 + 4]
cvtsi2ss xmm9, qword ptr [r15 - 4]
cvtsi2sd xmm9, dword ptr [r15 + 4]
cvttss2si r15d, xmm9
cvttsd2si r15d, xmm9
cvtsi2ss xmm9, r15d
cvtsi2sd xmm9, r15d
cvttss2si r15, xmm9
cvttsd2si r15, xmm9
cvtsi2ss xmm9, r15
cvtsi2sd xmm9, r15
; Between: xmm10 and rax
movss dword ptr [rax - 4], xmm10
movsd qword ptr [rax + 4], xmm10
movss xmm10, dword ptr [rax - 4]
movsd xmm10, qword ptr [rax + 4]
cvtsi2ss xmm10, qword ptr [rax - 4]
cvtsi2sd xmm10, dword ptr [rax + 4]
cvttss2si eax, xmm10
cvttsd2si eax, xmm10
cvtsi2ss xmm10, eax
cvtsi2sd xmm10, eax
cvttss2si rax, xmm10
cvttsd2si rax, xmm10
cvtsi2ss xmm10, rax
cvtsi2sd xmm10, rax
; Between: xmm10 and rcx
movss dword ptr [rcx - 4], xmm10
movsd qword ptr [rcx + 4], xmm10
movss xmm10, dword ptr [rcx - 4]
movsd xmm10, qword ptr [rcx + 4]
cvtsi2ss xmm10, qword ptr [rcx - 4]
cvtsi2sd xmm10, dword ptr [rcx + 4]
cvttss2si ecx, xmm10
cvttsd2si ecx, xmm10
cvtsi2ss xmm10, ecx
cvtsi2sd xmm10, ecx
cvttss2si rcx, xmm10
cvttsd2si rcx, xmm10
cvtsi2ss xmm10, rcx
cvtsi2sd xmm10, rcx
; Between: xmm10 and rdx
movss dword ptr [rdx - 4], xmm10
movsd qword ptr [rdx + 4], xmm10
movss xmm10, dword ptr [rdx - 4]
movsd xmm10, qword ptr [rdx + 4]
cvtsi2ss xmm10, qword ptr [rdx - 4]
cvtsi2sd xmm10, dword ptr [rdx + 4]
cvttss2si edx, xmm10
cvttsd2si edx, xmm10
cvtsi2ss xmm10, edx
cvtsi2sd xmm10, edx
cvttss2si rdx, xmm10
cvttsd2si rdx, xmm10
cvtsi2ss xmm10, rdx
cvtsi2sd xmm10, rdx
; Between: xmm10 and rbx
movss dword ptr [rbx - 4], xmm10
movsd qword ptr [rbx + 4], xmm10
movss xmm10, dword ptr [rbx - 4]
movsd xmm10, qword ptr [rbx + 4]
cvtsi2ss xmm10, qword ptr [rbx - 4]
cvtsi2sd xmm10, dword ptr [rbx + 4]
cvttss2si ebx, xmm10
cvttsd2si ebx, xmm10
cvtsi2ss xmm10, ebx
cvtsi2sd xmm10, ebx
cvttss2si rbx, xmm10
cvttsd2si rbx, xmm10
cvtsi2ss xmm10, rbx
cvtsi2sd xmm10, rbx
; Between: xmm10 and rsp
movss dword ptr [rsp - 4], xmm10
movsd qword ptr [rsp + 4], xmm10
movss xmm10, dword ptr [rsp - 4]
movsd xmm10, qword ptr [rsp + 4]
cvtsi2ss xmm10, qword ptr [rsp - 4]
cvtsi2sd xmm10, dword ptr [rsp + 4]
cvttss2si esp, xmm10
cvttsd2si esp, xmm10
cvtsi2ss xmm10, esp
cvtsi2sd xmm10, esp
cvttss2si rsp, xmm10
cvttsd2si rsp, xmm10
cvtsi2ss xmm10, rsp
cvtsi2sd xmm10, rsp
; Between: xmm10 and rbp
movss dword ptr [rbp - 4], xmm10
movsd qword ptr [rbp + 4], xmm10
movss xmm10, dword ptr [rbp - 4]
movsd xmm10, qword ptr [rbp + 4]
cvtsi2ss xmm10, qword ptr [rbp - 4]
cvtsi2sd xmm10, dword ptr [rbp + 4]
cvttss2si ebp, xmm10
cvttsd2si ebp, xmm10
cvtsi2ss xmm10, ebp
cvtsi2sd xmm10, ebp
cvttss2si rbp, xmm10
cvttsd2si rbp, xmm10
cvtsi2ss xmm10, rbp
cvtsi2sd xmm10, rbp
; Between: xmm10 and rsi
movss dword ptr [rsi - 4], xmm10
movsd qword ptr [rsi + 4], xmm10
movss xmm10, dword ptr [rsi - 4]
movsd xmm10, qword ptr [rsi + 4]
cvtsi2ss xmm10, qword ptr [rsi - 4]
cvtsi2sd xmm10, dword ptr [rsi + 4]
cvttss2si esi, xmm10
cvttsd2si esi, xmm10
cvtsi2ss xmm10, esi
cvtsi2sd xmm10, esi
cvttss2si rsi, xmm10
cvttsd2si rsi, xmm10
cvtsi2ss xmm10, rsi
cvtsi2sd xmm10, rsi
; Between: xmm10 and rdi
movss dword ptr [rdi - 4], xmm10
movsd qword ptr [rdi + 4], xmm10
movss xmm10, dword ptr [rdi - 4]
movsd xmm10, qword ptr [rdi + 4]
cvtsi2ss xmm10, qword ptr [rdi - 4]
cvtsi2sd xmm10, dword ptr [rdi + 4]
cvttss2si edi, xmm10
cvttsd2si edi, xmm10
cvtsi2ss xmm10, edi
cvtsi2sd xmm10, edi
cvttss2si rdi, xmm10
cvttsd2si rdi, xmm10
cvtsi2ss xmm10, rdi
cvtsi2sd xmm10, rdi
; Between: xmm10 and r8
movss dword ptr [r8 - 4], xmm10
movsd qword ptr [r8 + 4], xmm10
movss xmm10, dword ptr [r8 - 4]
movsd xmm10, qword ptr [r8 + 4]
cvtsi2ss xmm10, qword ptr [r8 - 4]
cvtsi2sd xmm10, dword ptr [r8 + 4]
cvttss2si r8d, xmm10
cvttsd2si r8d, xmm10
cvtsi2ss xmm10, r8d
cvtsi2sd xmm10, r8d
cvttss2si r8, xmm10
cvttsd2si r8, xmm10
cvtsi2ss xmm10, r8
cvtsi2sd xmm10, r8
; Between: xmm10 and r9
movss dword ptr [r9 - 4], xmm10
movsd qword ptr [r9 + 4], xmm10
movss xmm10, dword ptr [r9 - 4]
movsd xmm10, qword ptr [r9 + 4]
cvtsi2ss xmm10, qword ptr [r9 - 4]
cvtsi2sd xmm10, dword ptr [r9 + 4]
cvttss2si r9d, xmm10
cvttsd2si r9d, xmm10
cvtsi2ss xmm10, r9d
cvtsi2sd xmm10, r9d
cvttss2si r9, xmm10
cvttsd2si r9, xmm10
cvtsi2ss xmm10, r9
cvtsi2sd xmm10, r9
; Between: xmm10 and r10
movss dword ptr [r10 - 4], xmm10
movsd qword ptr [r10 + 4], xmm10
movss xmm10, dword ptr [r10 - 4]
movsd xmm10, qword ptr [r10 + 4]
cvtsi2ss xmm10, qword ptr [r10 - 4]
cvtsi2sd xmm10, dword ptr [r10 + 4]
cvttss2si r10d, xmm10
cvttsd2si r10d, xmm10
cvtsi2ss xmm10, r10d
cvtsi2sd xmm10, r10d
cvttss2si r10, xmm10
cvttsd2si r10, xmm10
cvtsi2ss xmm10, r10
cvtsi2sd xmm10, r10
; Between: xmm10 and r11
movss dword ptr [r11 - 4], xmm10
movsd qword ptr [r11 + 4], xmm10
movss xmm10, dword ptr [r11 - 4]
movsd xmm10, qword ptr [r11 + 4]
cvtsi2ss xmm10, qword ptr [r11 - 4]
cvtsi2sd xmm10, dword ptr [r11 + 4]
cvttss2si r11d, xmm10
cvttsd2si r11d, xmm10
cvtsi2ss xmm10, r11d
cvtsi2sd xmm10, r11d
cvttss2si r11, xmm10
cvttsd2si r11, xmm10
cvtsi2ss xmm10, r11
cvtsi2sd xmm10, r11
; Between: xmm10 and r12
movss dword ptr [r12 - 4], xmm10
movsd qword ptr [r12 + 4], xmm10
movss xmm10, dword ptr [r12 - 4]
movsd xmm10, qword ptr [r12 + 4]
cvtsi2ss xmm10, qword ptr [r12 - 4]
cvtsi2sd xmm10, dword ptr [r12 + 4]
cvttss2si r12d, xmm10
cvttsd2si r12d, xmm10
cvtsi2ss xmm10, r12d
cvtsi2sd xmm10, r12d
cvttss2si r12, xmm10
cvttsd2si r12, xmm10
cvtsi2ss xmm10, r12
cvtsi2sd xmm10, r12
; Between: xmm10 and r13
movss dword ptr [r13 - 4], xmm10
movsd qword ptr [r13 + 4], xmm10
movss xmm10, dword ptr [r13 - 4]
movsd xmm10, qword ptr [r13 + 4]
cvtsi2ss xmm10, qword ptr [r13 - 4]
cvtsi2sd xmm10, dword ptr [r13 + 4]
cvttss2si r13d, xmm10
cvttsd2si r13d, xmm10
cvtsi2ss xmm10, r13d
cvtsi2sd xmm10, r13d
cvttss2si r13, xmm10
cvttsd2si r13, xmm10
cvtsi2ss xmm10, r13
cvtsi2sd xmm10, r13
; Between: xmm10 and r14
movss dword ptr [r14 - 4], xmm10
movsd qword ptr [r14 + 4], xmm10
movss xmm10, dword ptr [r14 - 4]
movsd xmm10, qword ptr [r14 + 4]
cvtsi2ss xmm10, qword ptr [r14 - 4]
cvtsi2sd xmm10, dword ptr [r14 + 4]
cvttss2si r14d, xmm10
cvttsd2si r14d, xmm10
cvtsi2ss xmm10, r14d
cvtsi2sd xmm10, r14d
cvttss2si r14, xmm10
cvttsd2si r14, xmm10
cvtsi2ss xmm10, r14
cvtsi2sd xmm10, r14
; Between: xmm10 and r15
movss dword ptr [r15 - 4], xmm10
movsd qword ptr [r15 + 4], xmm10
movss xmm10, dword ptr [r15 - 4]
movsd xmm10, qword ptr [r15 + 4]
cvtsi2ss xmm10, qword ptr [r15 - 4]
cvtsi2sd xmm10, dword ptr [r15 + 4]
cvttss2si r15d, xmm10
cvttsd2si r15d, xmm10
cvtsi2ss xmm10, r15d
cvtsi2sd xmm10, r15d
cvttss2si r15, xmm10
cvttsd2si r15, xmm10
cvtsi2ss xmm10, r15
cvtsi2sd xmm10, r15
; Between: xmm11 and rax
movss dword ptr [rax - 4], xmm11
movsd qword ptr [rax + 4], xmm11
movss xmm11, dword ptr [rax - 4]
movsd xmm11, qword ptr [rax + 4]
cvtsi2ss xmm11, qword ptr [rax - 4]
cvtsi2sd xmm11, dword ptr [rax + 4]
cvttss2si eax, xmm11
cvttsd2si eax, xmm11
cvtsi2ss xmm11, eax
cvtsi2sd xmm11, eax
cvttss2si rax, xmm11
cvttsd2si rax, xmm11
cvtsi2ss xmm11, rax
cvtsi2sd xmm11, rax
; Between: xmm11 and rcx
movss dword ptr [rcx - 4], xmm11
movsd qword ptr [rcx + 4], xmm11
movss xmm11, dword ptr [rcx - 4]
movsd xmm11, qword ptr [rcx + 4]
cvtsi2ss xmm11, qword ptr [rcx - 4]
cvtsi2sd xmm11, dword ptr [rcx + 4]
cvttss2si ecx, xmm11
cvttsd2si ecx, xmm11
cvtsi2ss xmm11, ecx
cvtsi2sd xmm11, ecx
cvttss2si rcx, xmm11
cvttsd2si rcx, xmm11
cvtsi2ss xmm11, rcx
cvtsi2sd xmm11, rcx
; Between: xmm11 and rdx
movss dword ptr [rdx - 4], xmm11
movsd qword ptr [rdx + 4], xmm11
movss xmm11, dword ptr [rdx - 4]
movsd xmm11, qword ptr [rdx + 4]
cvtsi2ss xmm11, qword ptr [rdx - 4]
cvtsi2sd xmm11, dword ptr [rdx + 4]
cvttss2si edx, xmm11
cvttsd2si edx, xmm11
cvtsi2ss xmm11, edx
cvtsi2sd xmm11, edx
cvttss2si rdx, xmm11
cvttsd2si rdx, xmm11
cvtsi2ss xmm11, rdx
cvtsi2sd xmm11, rdx
; Between: xmm11 and rbx
movss dword ptr [rbx - 4], xmm11
movsd qword ptr [rbx + 4], xmm11
movss xmm11, dword ptr [rbx - 4]
movsd xmm11, qword ptr [rbx + 4]
cvtsi2ss xmm11, qword ptr [rbx - 4]
cvtsi2sd xmm11, dword ptr [rbx + 4]
cvttss2si ebx, xmm11
cvttsd2si ebx, xmm11
cvtsi2ss xmm11, ebx
cvtsi2sd xmm11, ebx
cvttss2si rbx, xmm11
cvttsd2si rbx, xmm11
cvtsi2ss xmm11, rbx
cvtsi2sd xmm11, rbx
; Between: xmm11 and rsp
movss dword ptr [rsp - 4], xmm11
movsd qword ptr [rsp + 4], xmm11
movss xmm11, dword ptr [rsp - 4]
movsd xmm11, qword ptr [rsp + 4]
cvtsi2ss xmm11, qword ptr [rsp - 4]
cvtsi2sd xmm11, dword ptr [rsp + 4]
cvttss2si esp, xmm11
cvttsd2si esp, xmm11
cvtsi2ss xmm11, esp
cvtsi2sd xmm11, esp
cvttss2si rsp, xmm11
cvttsd2si rsp, xmm11
cvtsi2ss xmm11, rsp
cvtsi2sd xmm11, rsp
; Between: xmm11 and rbp
movss dword ptr [rbp - 4], xmm11
movsd qword ptr [rbp + 4], xmm11
movss xmm11, dword ptr [rbp - 4]
movsd xmm11, qword ptr [rbp + 4]
cvtsi2ss xmm11, qword ptr [rbp - 4]
cvtsi2sd xmm11, dword ptr [rbp + 4]
cvttss2si ebp, xmm11
cvttsd2si ebp, xmm11
cvtsi2ss xmm11, ebp
cvtsi2sd xmm11, ebp
cvttss2si rbp, xmm11
cvttsd2si rbp, xmm11
cvtsi2ss xmm11, rbp
cvtsi2sd xmm11, rbp
; Between: xmm11 and rsi
movss dword ptr [rsi - 4], xmm11
movsd qword ptr [rsi + 4], xmm11
movss xmm11, dword ptr [rsi - 4]
movsd xmm11, qword ptr [rsi + 4]
cvtsi2ss xmm11, qword ptr [rsi - 4]
cvtsi2sd xmm11, dword ptr [rsi + 4]
cvttss2si esi, xmm11
cvttsd2si esi, xmm11
cvtsi2ss xmm11, esi
cvtsi2sd xmm11, esi
cvttss2si rsi, xmm11
cvttsd2si rsi, xmm11
cvtsi2ss xmm11, rsi
cvtsi2sd xmm11, rsi
; Between: xmm11 and rdi
movss dword ptr [rdi - 4], xmm11
movsd qword ptr [rdi + 4], xmm11
movss xmm11, dword ptr [rdi - 4]
movsd xmm11, qword ptr [rdi + 4]
cvtsi2ss xmm11, qword ptr [rdi - 4]
cvtsi2sd xmm11, dword ptr [rdi + 4]
cvttss2si edi, xmm11
cvttsd2si edi, xmm11
cvtsi2ss xmm11, edi
cvtsi2sd xmm11, edi
cvttss2si rdi, xmm11
cvttsd2si rdi, xmm11
cvtsi2ss xmm11, rdi
cvtsi2sd xmm11, rdi
; Between: xmm11 and r8
movss dword ptr [r8 - 4], xmm11
movsd qword ptr [r8 + 4], xmm11
movss xmm11, dword ptr [r8 - 4]
movsd xmm11, qword ptr [r8 + 4]
cvtsi2ss xmm11, qword ptr [r8 - 4]
cvtsi2sd xmm11, dword ptr [r8 + 4]
cvttss2si r8d, xmm11
cvttsd2si r8d, xmm11
cvtsi2ss xmm11, r8d
cvtsi2sd xmm11, r8d
cvttss2si r8, xmm11
cvttsd2si r8, xmm11
cvtsi2ss xmm11, r8
cvtsi2sd xmm11, r8
; Between: xmm11 and r9
movss dword ptr [r9 - 4], xmm11
movsd qword ptr [r9 + 4], xmm11
movss xmm11, dword ptr [r9 - 4]
movsd xmm11, qword ptr [r9 + 4]
cvtsi2ss xmm11, qword ptr [r9 - 4]
cvtsi2sd xmm11, dword ptr [r9 + 4]
cvttss2si r9d, xmm11
cvttsd2si r9d, xmm11
cvtsi2ss xmm11, r9d
cvtsi2sd xmm11, r9d
cvttss2si r9, xmm11
cvttsd2si r9, xmm11
cvtsi2ss xmm11, r9
cvtsi2sd xmm11, r9
; Between: xmm11 and r10
movss dword ptr [r10 - 4], xmm11
movsd qword ptr [r10 + 4], xmm11
movss xmm11, dword ptr [r10 - 4]
movsd xmm11, qword ptr [r10 + 4]
cvtsi2ss xmm11, qword ptr [r10 - 4]
cvtsi2sd xmm11, dword ptr [r10 + 4]
cvttss2si r10d, xmm11
cvttsd2si r10d, xmm11
cvtsi2ss xmm11, r10d
cvtsi2sd xmm11, r10d
cvttss2si r10, xmm11
cvttsd2si r10, xmm11
cvtsi2ss xmm11, r10
cvtsi2sd xmm11, r10
; Between: xmm11 and r11
movss dword ptr [r11 - 4], xmm11
movsd qword ptr [r11 + 4], xmm11
movss xmm11, dword ptr [r11 - 4]
movsd xmm11, qword ptr [r11 + 4]
cvtsi2ss xmm11, qword ptr [r11 - 4]
cvtsi2sd xmm11, dword ptr [r11 + 4]
cvttss2si r11d, xmm11
cvttsd2si r11d, xmm11
cvtsi2ss xmm11, r11d
cvtsi2sd xmm11, r11d
cvttss2si r11, xmm11
cvttsd2si r11, xmm11
cvtsi2ss xmm11, r11
cvtsi2sd xmm11, r11
; Between: xmm11 and r12
movss dword ptr [r12 - 4], xmm11
movsd qword ptr [r12 + 4], xmm11
movss xmm11, dword ptr [r12 - 4]
movsd xmm11, qword ptr [r12 + 4]
cvtsi2ss xmm11, qword ptr [r12 - 4]
cvtsi2sd xmm11, dword ptr [r12 + 4]
cvttss2si r12d, xmm11
cvttsd2si r12d, xmm11
cvtsi2ss xmm11, r12d
cvtsi2sd xmm11, r12d
cvttss2si r12, xmm11
cvttsd2si r12, xmm11
cvtsi2ss xmm11, r12
cvtsi2sd xmm11, r12
; Between: xmm11 and r13
movss dword ptr [r13 - 4], xmm11
movsd qword ptr [r13 + 4], xmm11
movss xmm11, dword ptr [r13 - 4]
movsd xmm11, qword ptr [r13 + 4]
cvtsi2ss xmm11, qword ptr [r13 - 4]
cvtsi2sd xmm11, dword ptr [r13 + 4]
cvttss2si r13d, xmm11
cvttsd2si r13d, xmm11
cvtsi2ss xmm11, r13d
cvtsi2sd xmm11, r13d
cvttss2si r13, xmm11
cvttsd2si r13, xmm11
cvtsi2ss xmm11, r13
cvtsi2sd xmm11, r13
; Between: xmm11 and r14
movss dword ptr [r14 - 4], xmm11
movsd qword ptr [r14 + 4], xmm11
movss xmm11, dword ptr [r14 - 4]
movsd xmm11, qword ptr [r14 + 4]
cvtsi2ss xmm11, qword ptr [r14 - 4]
cvtsi2sd xmm11, dword ptr [r14 + 4]
cvttss2si r14d, xmm11
cvttsd2si r14d, xmm11
cvtsi2ss xmm11, r14d
cvtsi2sd xmm11, r14d
cvttss2si r14, xmm11
cvttsd2si r14, xmm11
cvtsi2ss xmm11, r14
cvtsi2sd xmm11, r14
; Between: xmm11 and r15
movss dword ptr [r15 - 4], xmm11
movsd qword ptr [r15 + 4], xmm11
movss xmm11, dword ptr [r15 - 4]
movsd xmm11, qword ptr [r15 + 4]
cvtsi2ss xmm11, qword ptr [r15 - 4]
cvtsi2sd xmm11, dword ptr [r15 + 4]
cvttss2si r15d, xmm11
cvttsd2si r15d, xmm11
cvtsi2ss xmm11, r15d
cvtsi2sd xmm11, r15d
cvttss2si r15, xmm11
cvttsd2si r15, xmm11
cvtsi2ss xmm11, r15
cvtsi2sd xmm11, r15
; Between: xmm12 and rax
movss dword ptr [rax - 4], xmm12
movsd qword ptr [rax + 4], xmm12
movss xmm12, dword ptr [rax - 4]
movsd xmm12, qword ptr [rax + 4]
cvtsi2ss xmm12, qword ptr [rax - 4]
cvtsi2sd xmm12, dword ptr [rax + 4]
cvttss2si eax, xmm12
cvttsd2si eax, xmm12
cvtsi2ss xmm12, eax
cvtsi2sd xmm12, eax
cvttss2si rax, xmm12
cvttsd2si rax, xmm12
cvtsi2ss xmm12, rax
cvtsi2sd xmm12, rax
; Between: xmm12 and rcx
movss dword ptr [rcx - 4], xmm12
movsd qword ptr [rcx + 4], xmm12
movss xmm12, dword ptr [rcx - 4]
movsd xmm12, qword ptr [rcx + 4]
cvtsi2ss xmm12, qword ptr [rcx - 4]
cvtsi2sd xmm12, dword ptr [rcx + 4]
cvttss2si ecx, xmm12
cvttsd2si ecx, xmm12
cvtsi2ss xmm12, ecx
cvtsi2sd xmm12, ecx
cvttss2si rcx, xmm12
cvttsd2si rcx, xmm12
cvtsi2ss xmm12, rcx
cvtsi2sd xmm12, rcx
; Between: xmm12 and rdx
movss dword ptr [rdx - 4], xmm12
movsd qword ptr [rdx + 4], xmm12
movss xmm12, dword ptr [rdx - 4]
movsd xmm12, qword ptr [rdx + 4]
cvtsi2ss xmm12, qword ptr [rdx - 4]
cvtsi2sd xmm12, dword ptr [rdx + 4]
cvttss2si edx, xmm12
cvttsd2si edx, xmm12
cvtsi2ss xmm12, edx
cvtsi2sd xmm12, edx
cvttss2si rdx, xmm12
cvttsd2si rdx, xmm12
cvtsi2ss xmm12, rdx
cvtsi2sd xmm12, rdx
; Between: xmm12 and rbx
movss dword ptr [rbx - 4], xmm12
movsd qword ptr [rbx + 4], xmm12
movss xmm12, dword ptr [rbx - 4]
movsd xmm12, qword ptr [rbx + 4]
cvtsi2ss xmm12, qword ptr [rbx - 4]
cvtsi2sd xmm12, dword ptr [rbx + 4]
cvttss2si ebx, xmm12
cvttsd2si ebx, xmm12
cvtsi2ss xmm12, ebx
cvtsi2sd xmm12, ebx
cvttss2si rbx, xmm12
cvttsd2si rbx, xmm12
cvtsi2ss xmm12, rbx
cvtsi2sd xmm12, rbx
; Between: xmm12 and rsp
movss dword ptr [rsp - 4], xmm12
movsd qword ptr [rsp + 4], xmm12
movss xmm12, dword ptr [rsp - 4]
movsd xmm12, qword ptr [rsp + 4]
cvtsi2ss xmm12, qword ptr [rsp - 4]
cvtsi2sd xmm12, dword ptr [rsp + 4]
cvttss2si esp, xmm12
cvttsd2si esp, xmm12
cvtsi2ss xmm12, esp
cvtsi2sd xmm12, esp
cvttss2si rsp, xmm12
cvttsd2si rsp, xmm12
cvtsi2ss xmm12, rsp
cvtsi2sd xmm12, rsp
; Between: xmm12 and rbp
movss dword ptr [rbp - 4], xmm12
movsd qword ptr [rbp + 4], xmm12
movss xmm12, dword ptr [rbp - 4]
movsd xmm12, qword ptr [rbp + 4]
cvtsi2ss xmm12, qword ptr [rbp - 4]
cvtsi2sd xmm12, dword ptr [rbp + 4]
cvttss2si ebp, xmm12
cvttsd2si ebp, xmm12
cvtsi2ss xmm12, ebp
cvtsi2sd xmm12, ebp
cvttss2si rbp, xmm12
cvttsd2si rbp, xmm12
cvtsi2ss xmm12, rbp
cvtsi2sd xmm12, rbp
; Between: xmm12 and rsi
movss dword ptr [rsi - 4], xmm12
movsd qword ptr [rsi + 4], xmm12
movss xmm12, dword ptr [rsi - 4]
movsd xmm12, qword ptr [rsi + 4]
cvtsi2ss xmm12, qword ptr [rsi - 4]
cvtsi2sd xmm12, dword ptr [rsi + 4]
cvttss2si esi, xmm12
cvttsd2si esi, xmm12
cvtsi2ss xmm12, esi
cvtsi2sd xmm12, esi
cvttss2si rsi, xmm12
cvttsd2si rsi, xmm12
cvtsi2ss xmm12, rsi
cvtsi2sd xmm12, rsi
; Between: xmm12 and rdi
movss dword ptr [rdi - 4], xmm12
movsd qword ptr [rdi + 4], xmm12
movss xmm12, dword ptr [rdi - 4]
movsd xmm12, qword ptr [rdi + 4]
cvtsi2ss xmm12, qword ptr [rdi - 4]
cvtsi2sd xmm12, dword ptr [rdi + 4]
cvttss2si edi, xmm12
cvttsd2si edi, xmm12
cvtsi2ss xmm12, edi
cvtsi2sd xmm12, edi
cvttss2si rdi, xmm12
cvttsd2si rdi, xmm12
cvtsi2ss xmm12, rdi
cvtsi2sd xmm12, rdi
; Between: xmm12 and r8
movss dword ptr [r8 - 4], xmm12
movsd qword ptr [r8 + 4], xmm12
movss xmm12, dword ptr [r8 - 4]
movsd xmm12, qword ptr [r8 + 4]
cvtsi2ss xmm12, qword ptr [r8 - 4]
cvtsi2sd xmm12, dword ptr [r8 + 4]
cvttss2si r8d, xmm12
cvttsd2si r8d, xmm12
cvtsi2ss xmm12, r8d
cvtsi2sd xmm12, r8d
cvttss2si r8, xmm12
cvttsd2si r8, xmm12
cvtsi2ss xmm12, r8
cvtsi2sd xmm12, r8
; Between: xmm12 and r9
movss dword ptr [r9 - 4], xmm12
movsd qword ptr [r9 + 4], xmm12
movss xmm12, dword ptr [r9 - 4]
movsd xmm12, qword ptr [r9 + 4]
cvtsi2ss xmm12, qword ptr [r9 - 4]
cvtsi2sd xmm12, dword ptr [r9 + 4]
cvttss2si r9d, xmm12
cvttsd2si r9d, xmm12
cvtsi2ss xmm12, r9d
cvtsi2sd xmm12, r9d
cvttss2si r9, xmm12
cvttsd2si r9, xmm12
cvtsi2ss xmm12, r9
cvtsi2sd xmm12, r9
; Between: xmm12 and r10
movss dword ptr [r10 - 4], xmm12
movsd qword ptr [r10 + 4], xmm12
movss xmm12, dword ptr [r10 - 4]
movsd xmm12, qword ptr [r10 + 4]
cvtsi2ss xmm12, qword ptr [r10 - 4]
cvtsi2sd xmm12, dword ptr [r10 + 4]
cvttss2si r10d, xmm12
cvttsd2si r10d, xmm12
cvtsi2ss xmm12, r10d
cvtsi2sd xmm12, r10d
cvttss2si r10, xmm12
cvttsd2si r10, xmm12
cvtsi2ss xmm12, r10
cvtsi2sd xmm12, r10
; Between: xmm12 and r11
movss dword ptr [r11 - 4], xmm12
movsd qword ptr [r11 + 4], xmm12
movss xmm12, dword ptr [r11 - 4]
movsd xmm12, qword ptr [r11 + 4]
cvtsi2ss xmm12, qword ptr [r11 - 4]
cvtsi2sd xmm12, dword ptr [r11 + 4]
cvttss2si r11d, xmm12
cvttsd2si r11d, xmm12
cvtsi2ss xmm12, r11d
cvtsi2sd xmm12, r11d
cvttss2si r11, xmm12
cvttsd2si r11, xmm12
cvtsi2ss xmm12, r11
cvtsi2sd xmm12, r11
; Between: xmm12 and r12
movss dword ptr [r12 - 4], xmm12
movsd qword ptr [r12 + 4], xmm12
movss xmm12, dword ptr [r12 - 4]
movsd xmm12, qword ptr [r12 + 4]
cvtsi2ss xmm12, qword ptr [r12 - 4]
cvtsi2sd xmm12, dword ptr [r12 + 4]
cvttss2si r12d, xmm12
cvttsd2si r12d, xmm12
cvtsi2ss xmm12, r12d
cvtsi2sd xmm12, r12d
cvttss2si r12, xmm12
cvttsd2si r12, xmm12
cvtsi2ss xmm12, r12
cvtsi2sd xmm12, r12
; Between: xmm12 and r13
movss dword ptr [r13 - 4], xmm12
movsd qword ptr [r13 + 4], xmm12
movss xmm12, dword ptr [r13 - 4]
movsd xmm12, qword ptr [r13 + 4]
cvtsi2ss xmm12, qword ptr [r13 - 4]
cvtsi2sd xmm12, dword ptr [r13 + 4]
cvttss2si r13d, xmm12
cvttsd2si r13d, xmm12
cvtsi2ss xmm12, r13d
cvtsi2sd xmm12, r13d
cvttss2si r13, xmm12
cvttsd2si r13, xmm12
cvtsi2ss xmm12, r13
cvtsi2sd xmm12, r13
; Between: xmm12 and r14
movss dword ptr [r14 - 4], xmm12
movsd qword ptr [r14 + 4], xmm12
movss xmm12, dword ptr [r14 - 4]
movsd xmm12, qword ptr [r14 + 4]
cvtsi2ss xmm12, qword ptr [r14 - 4]
cvtsi2sd xmm12, dword ptr [r14 + 4]
cvttss2si r14d, xmm12
cvttsd2si r14d, xmm12
cvtsi2ss xmm12, r14d
cvtsi2sd xmm12, r14d
cvttss2si r14, xmm12
cvttsd2si r14, xmm12
cvtsi2ss xmm12, r14
cvtsi2sd xmm12, r14
; Between: xmm12 and r15
movss dword ptr [r15 - 4], xmm12
movsd qword ptr [r15 + 4], xmm12
movss xmm12, dword ptr [r15 - 4]
movsd xmm12, qword ptr [r15 + 4]
cvtsi2ss xmm12, qword ptr [r15 - 4]
cvtsi2sd xmm12, dword ptr [r15 + 4]
cvttss2si r15d, xmm12
cvttsd2si r15d, xmm12
cvtsi2ss xmm12, r15d
cvtsi2sd xmm12, r15d
cvttss2si r15, xmm12
cvttsd2si r15, xmm12
cvtsi2ss xmm12, r15
cvtsi2sd xmm12, r15
; Between: xmm13 and rax
movss dword ptr [rax - 4], xmm13
movsd qword ptr [rax + 4], xmm13
movss xmm13, dword ptr [rax - 4]
movsd xmm13, qword ptr [rax + 4]
cvtsi2ss xmm13, qword ptr [rax - 4]
cvtsi2sd xmm13, dword ptr [rax + 4]
cvttss2si eax, xmm13
cvttsd2si eax, xmm13
cvtsi2ss xmm13, eax
cvtsi2sd xmm13, eax
cvttss2si rax, xmm13
cvttsd2si rax, xmm13
cvtsi2ss xmm13, rax
cvtsi2sd xmm13, rax
; Between: xmm13 and rcx
movss dword ptr [rcx - 4], xmm13
movsd qword ptr [rcx + 4], xmm13
movss xmm13, dword ptr [rcx - 4]
movsd xmm13, qword ptr [rcx + 4]
cvtsi2ss xmm13, qword ptr [rcx - 4]
cvtsi2sd xmm13, dword ptr [rcx + 4]
cvttss2si ecx, xmm13
cvttsd2si ecx, xmm13
cvtsi2ss xmm13, ecx
cvtsi2sd xmm13, ecx
cvttss2si rcx, xmm13
cvttsd2si rcx, xmm13
cvtsi2ss xmm13, rcx
cvtsi2sd xmm13, rcx
; Between: xmm13 and rdx
movss dword ptr [rdx - 4], xmm13
movsd qword ptr [rdx + 4], xmm13
movss xmm13, dword ptr [rdx - 4]
movsd xmm13, qword ptr [rdx + 4]
cvtsi2ss xmm13, qword ptr [rdx - 4]
cvtsi2sd xmm13, dword ptr [rdx + 4]
cvttss2si edx, xmm13
cvttsd2si edx, xmm13
cvtsi2ss xmm13, edx
cvtsi2sd xmm13, edx
cvttss2si rdx, xmm13
cvttsd2si rdx, xmm13
cvtsi2ss xmm13, rdx
cvtsi2sd xmm13, rdx
; Between: xmm13 and rbx
movss dword ptr [rbx - 4], xmm13
movsd qword ptr [rbx + 4], xmm13
movss xmm13, dword ptr [rbx - 4]
movsd xmm13, qword ptr [rbx + 4]
cvtsi2ss xmm13, qword ptr [rbx - 4]
cvtsi2sd xmm13, dword ptr [rbx + 4]
cvttss2si ebx, xmm13
cvttsd2si ebx, xmm13
cvtsi2ss xmm13, ebx
cvtsi2sd xmm13, ebx
cvttss2si rbx, xmm13
cvttsd2si rbx, xmm13
cvtsi2ss xmm13, rbx
cvtsi2sd xmm13, rbx
; Between: xmm13 and rsp
movss dword ptr [rsp - 4], xmm13
movsd qword ptr [rsp + 4], xmm13
movss xmm13, dword ptr [rsp - 4]
movsd xmm13, qword ptr [rsp + 4]
cvtsi2ss xmm13, qword ptr [rsp - 4]
cvtsi2sd xmm13, dword ptr [rsp + 4]
cvttss2si esp, xmm13
cvttsd2si esp, xmm13
cvtsi2ss xmm13, esp
cvtsi2sd xmm13, esp
cvttss2si rsp, xmm13
cvttsd2si rsp, xmm13
cvtsi2ss xmm13, rsp
cvtsi2sd xmm13, rsp
; Between: xmm13 and rbp
movss dword ptr [rbp - 4], xmm13
movsd qword ptr [rbp + 4], xmm13
movss xmm13, dword ptr [rbp - 4]
movsd xmm13, qword ptr [rbp + 4]
cvtsi2ss xmm13, qword ptr [rbp - 4]
cvtsi2sd xmm13, dword ptr [rbp + 4]
cvttss2si ebp, xmm13
cvttsd2si ebp, xmm13
cvtsi2ss xmm13, ebp
cvtsi2sd xmm13, ebp
cvttss2si rbp, xmm13
cvttsd2si rbp, xmm13
cvtsi2ss xmm13, rbp
cvtsi2sd xmm13, rbp
; Between: xmm13 and rsi
movss dword ptr [rsi - 4], xmm13
movsd qword ptr [rsi + 4], xmm13
movss xmm13, dword ptr [rsi - 4]
movsd xmm13, qword ptr [rsi + 4]
cvtsi2ss xmm13, qword ptr [rsi - 4]
cvtsi2sd xmm13, dword ptr [rsi + 4]
cvttss2si esi, xmm13
cvttsd2si esi, xmm13
cvtsi2ss xmm13, esi
cvtsi2sd xmm13, esi
cvttss2si rsi, xmm13
cvttsd2si rsi, xmm13
cvtsi2ss xmm13, rsi
cvtsi2sd xmm13, rsi
; Between: xmm13 and rdi
movss dword ptr [rdi - 4], xmm13
movsd qword ptr [rdi + 4], xmm13
movss xmm13, dword ptr [rdi - 4]
movsd xmm13, qword ptr [rdi + 4]
cvtsi2ss xmm13, qword ptr [rdi - 4]
cvtsi2sd xmm13, dword ptr [rdi + 4]
cvttss2si edi, xmm13
cvttsd2si edi, xmm13
cvtsi2ss xmm13, edi
cvtsi2sd xmm13, edi
cvttss2si rdi, xmm13
cvttsd2si rdi, xmm13
cvtsi2ss xmm13, rdi
cvtsi2sd xmm13, rdi
; Between: xmm13 and r8
movss dword ptr [r8 - 4], xmm13
movsd qword ptr [r8 + 4], xmm13
movss xmm13, dword ptr [r8 - 4]
movsd xmm13, qword ptr [r8 + 4]
cvtsi2ss xmm13, qword ptr [r8 - 4]
cvtsi2sd xmm13, dword ptr [r8 + 4]
cvttss2si r8d, xmm13
cvttsd2si r8d, xmm13
cvtsi2ss xmm13, r8d
cvtsi2sd xmm13, r8d
cvttss2si r8, xmm13
cvttsd2si r8, xmm13
cvtsi2ss xmm13, r8
cvtsi2sd xmm13, r8
; Between: xmm13 and r9
movss dword ptr [r9 - 4], xmm13
movsd qword ptr [r9 + 4], xmm13
movss xmm13, dword ptr [r9 - 4]
movsd xmm13, qword ptr [r9 + 4]
cvtsi2ss xmm13, qword ptr [r9 - 4]
cvtsi2sd xmm13, dword ptr [r9 + 4]
cvttss2si r9d, xmm13
cvttsd2si r9d, xmm13
cvtsi2ss xmm13, r9d
cvtsi2sd xmm13, r9d
cvttss2si r9, xmm13
cvttsd2si r9, xmm13
cvtsi2ss xmm13, r9
cvtsi2sd xmm13, r9
; Between: xmm13 and r10
movss dword ptr [r10 - 4], xmm13
movsd qword ptr [r10 + 4], xmm13
movss xmm13, dword ptr [r10 - 4]
movsd xmm13, qword ptr [r10 + 4]
cvtsi2ss xmm13, qword ptr [r10 - 4]
cvtsi2sd xmm13, dword ptr [r10 + 4]
cvttss2si r10d, xmm13
cvttsd2si r10d, xmm13
cvtsi2ss xmm13, r10d
cvtsi2sd xmm13, r10d
cvttss2si r10, xmm13
cvttsd2si r10, xmm13
cvtsi2ss xmm13, r10
cvtsi2sd xmm13, r10
; Between: xmm13 and r11
movss dword ptr [r11 - 4], xmm13
movsd qword ptr [r11 + 4], xmm13
movss xmm13, dword ptr [r11 - 4]
movsd xmm13, qword ptr [r11 + 4]
cvtsi2ss xmm13, qword ptr [r11 - 4]
cvtsi2sd xmm13, dword ptr [r11 + 4]
cvttss2si r11d, xmm13
cvttsd2si r11d, xmm13
cvtsi2ss xmm13, r11d
cvtsi2sd xmm13, r11d
cvttss2si r11, xmm13
cvttsd2si r11, xmm13
cvtsi2ss xmm13, r11
cvtsi2sd xmm13, r11
; Between: xmm13 and r12
movss dword ptr [r12 - 4], xmm13
movsd qword ptr [r12 + 4], xmm13
movss xmm13, dword ptr [r12 - 4]
movsd xmm13, qword ptr [r12 + 4]
cvtsi2ss xmm13, qword ptr [r12 - 4]
cvtsi2sd xmm13, dword ptr [r12 + 4]
cvttss2si r12d, xmm13
cvttsd2si r12d, xmm13
cvtsi2ss xmm13, r12d
cvtsi2sd xmm13, r12d
cvttss2si r12, xmm13
cvttsd2si r12, xmm13
cvtsi2ss xmm13, r12
cvtsi2sd xmm13, r12
; Between: xmm13 and r13
movss dword ptr [r13 - 4], xmm13
movsd qword ptr [r13 + 4], xmm13
movss xmm13, dword ptr [r13 - 4]
movsd xmm13, qword ptr [r13 + 4]
cvtsi2ss xmm13, qword ptr [r13 - 4]
cvtsi2sd xmm13, dword ptr [r13 + 4]
cvttss2si r13d, xmm13
cvttsd2si r13d, xmm13
cvtsi2ss xmm13, r13d
cvtsi2sd xmm13, r13d
cvttss2si r13, xmm13
cvttsd2si r13, xmm13
cvtsi2ss xmm13, r13
cvtsi2sd xmm13, r13
; Between: xmm13 and r14
movss dword ptr [r14 - 4], xmm13
movsd qword ptr [r14 + 4], xmm13
movss xmm13, dword ptr [r14 - 4]
movsd xmm13, qword ptr [r14 + 4]
cvtsi2ss xmm13, qword ptr [r14 - 4]
cvtsi2sd xmm13, dword ptr [r14 + 4]
cvttss2si r14d, xmm13
cvttsd2si r14d, xmm13
cvtsi2ss xmm13, r14d
cvtsi2sd xmm13, r14d
cvttss2si r14, xmm13
cvttsd2si r14, xmm13
cvtsi2ss xmm13, r14
cvtsi2sd xmm13, r14
; Between: xmm13 and r15
movss dword ptr [r15 - 4], xmm13
movsd qword ptr [r15 + 4], xmm13
movss xmm13, dword ptr [r15 - 4]
movsd xmm13, qword ptr [r15 + 4]
cvtsi2ss xmm13, qword ptr [r15 - 4]
cvtsi2sd xmm13, dword ptr [r15 + 4]
cvttss2si r15d, xmm13
cvttsd2si r15d, xmm13
cvtsi2ss xmm13, r15d
cvtsi2sd xmm13, r15d
cvttss2si r15, xmm13
cvttsd2si r15, xmm13
cvtsi2ss xmm13, r15
cvtsi2sd xmm13, r15
; Between: xmm14 and rax
movss dword ptr [rax - 4], xmm14
movsd qword ptr [rax + 4], xmm14
movss xmm14, dword ptr [rax - 4]
movsd xmm14, qword ptr [rax + 4]
cvtsi2ss xmm14, qword ptr [rax - 4]
cvtsi2sd xmm14, dword ptr [rax + 4]
cvttss2si eax, xmm14
cvttsd2si eax, xmm14
cvtsi2ss xmm14, eax
cvtsi2sd xmm14, eax
cvttss2si rax, xmm14
cvttsd2si rax, xmm14
cvtsi2ss xmm14, rax
cvtsi2sd xmm14, rax
; Between: xmm14 and rcx
movss dword ptr [rcx - 4], xmm14
movsd qword ptr [rcx + 4], xmm14
movss xmm14, dword ptr [rcx - 4]
movsd xmm14, qword ptr [rcx + 4]
cvtsi2ss xmm14, qword ptr [rcx - 4]
cvtsi2sd xmm14, dword ptr [rcx + 4]
cvttss2si ecx, xmm14
cvttsd2si ecx, xmm14
cvtsi2ss xmm14, ecx
cvtsi2sd xmm14, ecx
cvttss2si rcx, xmm14
cvttsd2si rcx, xmm14
cvtsi2ss xmm14, rcx
cvtsi2sd xmm14, rcx
; Between: xmm14 and rdx
movss dword ptr [rdx - 4], xmm14
movsd qword ptr [rdx + 4], xmm14
movss xmm14, dword ptr [rdx - 4]
movsd xmm14, qword ptr [rdx + 4]
cvtsi2ss xmm14, qword ptr [rdx - 4]
cvtsi2sd xmm14, dword ptr [rdx + 4]
cvttss2si edx, xmm14
cvttsd2si edx, xmm14
cvtsi2ss xmm14, edx
cvtsi2sd xmm14, edx
cvttss2si rdx, xmm14
cvttsd2si rdx, xmm14
cvtsi2ss xmm14, rdx
cvtsi2sd xmm14, rdx
; Between: xmm14 and rbx
movss dword ptr [rbx - 4], xmm14
movsd qword ptr [rbx + 4], xmm14
movss xmm14, dword ptr [rbx - 4]
movsd xmm14, qword ptr [rbx + 4]
cvtsi2ss xmm14, qword ptr [rbx - 4]
cvtsi2sd xmm14, dword ptr [rbx + 4]
cvttss2si ebx, xmm14
cvttsd2si ebx, xmm14
cvtsi2ss xmm14, ebx
cvtsi2sd xmm14, ebx
cvttss2si rbx, xmm14
cvttsd2si rbx, xmm14
cvtsi2ss xmm14, rbx
cvtsi2sd xmm14, rbx
; Between: xmm14 and rsp
movss dword ptr [rsp - 4], xmm14
movsd qword ptr [rsp + 4], xmm14
movss xmm14, dword ptr [rsp - 4]
movsd xmm14, qword ptr [rsp + 4]
cvtsi2ss xmm14, qword ptr [rsp - 4]
cvtsi2sd xmm14, dword ptr [rsp + 4]
cvttss2si esp, xmm14
cvttsd2si esp, xmm14
cvtsi2ss xmm14, esp
cvtsi2sd xmm14, esp
cvttss2si rsp, xmm14
cvttsd2si rsp, xmm14
cvtsi2ss xmm14, rsp
cvtsi2sd xmm14, rsp
; Between: xmm14 and rbp
movss dword ptr [rbp - 4], xmm14
movsd qword ptr [rbp + 4], xmm14
movss xmm14, dword ptr [rbp - 4]
movsd xmm14, qword ptr [rbp + 4]
cvtsi2ss xmm14, qword ptr [rbp - 4]
cvtsi2sd xmm14, dword ptr [rbp + 4]
cvttss2si ebp, xmm14
cvttsd2si ebp, xmm14
cvtsi2ss xmm14, ebp
cvtsi2sd xmm14, ebp
cvttss2si rbp, xmm14
cvttsd2si rbp, xmm14
cvtsi2ss xmm14, rbp
cvtsi2sd xmm14, rbp
; Between: xmm14 and rsi
movss dword ptr [rsi - 4], xmm14
movsd qword ptr [rsi + 4], xmm14
movss xmm14, dword ptr [rsi - 4]
movsd xmm14, qword ptr [rsi + 4]
cvtsi2ss xmm14, qword ptr [rsi - 4]
cvtsi2sd xmm14, dword ptr [rsi + 4]
cvttss2si esi, xmm14
cvttsd2si esi, xmm14
cvtsi2ss xmm14, esi
cvtsi2sd xmm14, esi
cvttss2si rsi, xmm14
cvttsd2si rsi, xmm14
cvtsi2ss xmm14, rsi
cvtsi2sd xmm14, rsi
; Between: xmm14 and rdi
movss dword ptr [rdi - 4], xmm14
movsd qword ptr [rdi + 4], xmm14
movss xmm14, dword ptr [rdi - 4]
movsd xmm14, qword ptr [rdi + 4]
cvtsi2ss xmm14, qword ptr [rdi - 4]
cvtsi2sd xmm14, dword ptr [rdi + 4]
cvttss2si edi, xmm14
cvttsd2si edi, xmm14
cvtsi2ss xmm14, edi
cvtsi2sd xmm14, edi
cvttss2si rdi, xmm14
cvttsd2si rdi, xmm14
cvtsi2ss xmm14, rdi
cvtsi2sd xmm14, rdi
; Between: xmm14 and r8
movss dword ptr [r8 - 4], xmm14
movsd qword ptr [r8 + 4], xmm14
movss xmm14, dword ptr [r8 - 4]
movsd xmm14, qword ptr [r8 + 4]
cvtsi2ss xmm14, qword ptr [r8 - 4]
cvtsi2sd xmm14, dword ptr [r8 + 4]
cvttss2si r8d, xmm14
cvttsd2si r8d, xmm14
cvtsi2ss xmm14, r8d
cvtsi2sd xmm14, r8d
cvttss2si r8, xmm14
cvttsd2si r8, xmm14
cvtsi2ss xmm14, r8
cvtsi2sd xmm14, r8
; Between: xmm14 and r9
movss dword ptr [r9 - 4], xmm14
movsd qword ptr [r9 + 4], xmm14
movss xmm14, dword ptr [r9 - 4]
movsd xmm14, qword ptr [r9 + 4]
cvtsi2ss xmm14, qword ptr [r9 - 4]
cvtsi2sd xmm14, dword ptr [r9 + 4]
cvttss2si r9d, xmm14
cvttsd2si r9d, xmm14
cvtsi2ss xmm14, r9d
cvtsi2sd xmm14, r9d
cvttss2si r9, xmm14
cvttsd2si r9, xmm14
cvtsi2ss xmm14, r9
cvtsi2sd xmm14, r9
; Between: xmm14 and r10
movss dword ptr [r10 - 4], xmm14
movsd qword ptr [r10 + 4], xmm14
movss xmm14, dword ptr [r10 - 4]
movsd xmm14, qword ptr [r10 + 4]
cvtsi2ss xmm14, qword ptr [r10 - 4]
cvtsi2sd xmm14, dword ptr [r10 + 4]
cvttss2si r10d, xmm14
cvttsd2si r10d, xmm14
cvtsi2ss xmm14, r10d
cvtsi2sd xmm14, r10d
cvttss2si r10, xmm14
cvttsd2si r10, xmm14
cvtsi2ss xmm14, r10
cvtsi2sd xmm14, r10
; Between: xmm14 and r11
movss dword ptr [r11 - 4], xmm14
movsd qword ptr [r11 + 4], xmm14
movss xmm14, dword ptr [r11 - 4]
movsd xmm14, qword ptr [r11 + 4]
cvtsi2ss xmm14, qword ptr [r11 - 4]
cvtsi2sd xmm14, dword ptr [r11 + 4]
cvttss2si r11d, xmm14
cvttsd2si r11d, xmm14
cvtsi2ss xmm14, r11d
cvtsi2sd xmm14, r11d
cvttss2si r11, xmm14
cvttsd2si r11, xmm14
cvtsi2ss xmm14, r11
cvtsi2sd xmm14, r11
; Between: xmm14 and r12
movss dword ptr [r12 - 4], xmm14
movsd qword ptr [r12 + 4], xmm14
movss xmm14, dword ptr [r12 - 4]
movsd xmm14, qword ptr [r12 + 4]
cvtsi2ss xmm14, qword ptr [r12 - 4]
cvtsi2sd xmm14, dword ptr [r12 + 4]
cvttss2si r12d, xmm14
cvttsd2si r12d, xmm14
cvtsi2ss xmm14, r12d
cvtsi2sd xmm14, r12d
cvttss2si r12, xmm14
cvttsd2si r12, xmm14
cvtsi2ss xmm14, r12
cvtsi2sd xmm14, r12
; Between: xmm14 and r13
movss dword ptr [r13 - 4], xmm14
movsd qword ptr [r13 + 4], xmm14
movss xmm14, dword ptr [r13 - 4]
movsd xmm14, qword ptr [r13 + 4]
cvtsi2ss xmm14, qword ptr [r13 - 4]
cvtsi2sd xmm14, dword ptr [r13 + 4]
cvttss2si r13d, xmm14
cvttsd2si r13d, xmm14
cvtsi2ss xmm14, r13d
cvtsi2sd xmm14, r13d
cvttss2si r13, xmm14
cvttsd2si r13, xmm14
cvtsi2ss xmm14, r13
cvtsi2sd xmm14, r13
; Between: xmm14 and r14
movss dword ptr [r14 - 4], xmm14
movsd qword ptr [r14 + 4], xmm14
movss xmm14, dword ptr [r14 - 4]
movsd xmm14, qword ptr [r14 + 4]
cvtsi2ss xmm14, qword ptr [r14 - 4]
cvtsi2sd xmm14, dword ptr [r14 + 4]
cvttss2si r14d, xmm14
cvttsd2si r14d, xmm14
cvtsi2ss xmm14, r14d
cvtsi2sd xmm14, r14d
cvttss2si r14, xmm14
cvttsd2si r14, xmm14
cvtsi2ss xmm14, r14
cvtsi2sd xmm14, r14
; Between: xmm14 and r15
movss dword ptr [r15 - 4], xmm14
movsd qword ptr [r15 + 4], xmm14
movss xmm14, dword ptr [r15 - 4]
movsd xmm14, qword ptr [r15 + 4]
cvtsi2ss xmm14, qword ptr [r15 - 4]
cvtsi2sd xmm14, dword ptr [r15 + 4]
cvttss2si r15d, xmm14
cvttsd2si r15d, xmm14
cvtsi2ss xmm14, r15d
cvtsi2sd xmm14, r15d
cvttss2si r15, xmm14
cvttsd2si r15, xmm14
cvtsi2ss xmm14, r15
cvtsi2sd xmm14, r15
; Between: xmm15 and rax
movss dword ptr [rax - 4], xmm15
movsd qword ptr [rax + 4], xmm15
movss xmm15, dword ptr [rax - 4]
movsd xmm15, qword ptr [rax + 4]
cvtsi2ss xmm15, qword ptr [rax - 4]
cvtsi2sd xmm15, dword ptr [rax + 4]
cvttss2si eax, xmm15
cvttsd2si eax, xmm15
cvtsi2ss xmm15, eax
cvtsi2sd xmm15, eax
cvttss2si rax, xmm15
cvttsd2si rax, xmm15
cvtsi2ss xmm15, rax
cvtsi2sd xmm15, rax
; Between: xmm15 and rcx
movss dword ptr [rcx - 4], xmm15
movsd qword ptr [rcx + 4], xmm15
movss xmm15, dword ptr [rcx - 4]
movsd xmm15, qword ptr [rcx + 4]
cvtsi2ss xmm15, qword ptr [rcx - 4]
cvtsi2sd xmm15, dword ptr [rcx + 4]
cvttss2si ecx, xmm15
cvttsd2si ecx, xmm15
cvtsi2ss xmm15, ecx
cvtsi2sd xmm15, ecx
cvttss2si rcx, xmm15
cvttsd2si rcx, xmm15
cvtsi2ss xmm15, rcx
cvtsi2sd xmm15, rcx
; Between: xmm15 and rdx
movss dword ptr [rdx - 4], xmm15
movsd qword ptr [rdx + 4], xmm15
movss xmm15, dword ptr [rdx - 4]
movsd xmm15, qword ptr [rdx + 4]
cvtsi2ss xmm15, qword ptr [rdx - 4]
cvtsi2sd xmm15, dword ptr [rdx + 4]
cvttss2si edx, xmm15
cvttsd2si edx, xmm15
cvtsi2ss xmm15, edx
cvtsi2sd xmm15, edx
cvttss2si rdx, xmm15
cvttsd2si rdx, xmm15
cvtsi2ss xmm15, rdx
cvtsi2sd xmm15, rdx
; Between: xmm15 and rbx
movss dword ptr [rbx - 4], xmm15
movsd qword ptr [rbx + 4], xmm15
movss xmm15, dword ptr [rbx - 4]
movsd xmm15, qword ptr [rbx + 4]
cvtsi2ss xmm15, qword ptr [rbx - 4]
cvtsi2sd xmm15, dword ptr [rbx + 4]
cvttss2si ebx, xmm15
cvttsd2si ebx, xmm15
cvtsi2ss xmm15, ebx
cvtsi2sd xmm15, ebx
cvttss2si rbx, xmm15
cvttsd2si rbx, xmm15
cvtsi2ss xmm15, rbx
cvtsi2sd xmm15, rbx
; Between: xmm15 and rsp
movss dword ptr [rsp - 4], xmm15
movsd qword ptr [rsp + 4], xmm15
movss xmm15, dword ptr [rsp - 4]
movsd xmm15, qword ptr [rsp + 4]
cvtsi2ss xmm15, qword ptr [rsp - 4]
cvtsi2sd xmm15, dword ptr [rsp + 4]
cvttss2si esp, xmm15
cvttsd2si esp, xmm15
cvtsi2ss xmm15, esp
cvtsi2sd xmm15, esp
cvttss2si rsp, xmm15
cvttsd2si rsp, xmm15
cvtsi2ss xmm15, rsp
cvtsi2sd xmm15, rsp
; Between: xmm15 and rbp
movss dword ptr [rbp - 4], xmm15
movsd qword ptr [rbp + 4], xmm15
movss xmm15, dword ptr [rbp - 4]
movsd xmm15, qword ptr [rbp + 4]
cvtsi2ss xmm15, qword ptr [rbp - 4]
cvtsi2sd xmm15, dword ptr [rbp + 4]
cvttss2si ebp, xmm15
cvttsd2si ebp, xmm15
cvtsi2ss xmm15, ebp
cvtsi2sd xmm15, ebp
cvttss2si rbp, xmm15
cvttsd2si rbp, xmm15
cvtsi2ss xmm15, rbp
cvtsi2sd xmm15, rbp
; Between: xmm15 and rsi
movss dword ptr [rsi - 4], xmm15
movsd qword ptr [rsi + 4], xmm15
movss xmm15, dword ptr [rsi - 4]
movsd xmm15, qword ptr [rsi + 4]
cvtsi2ss xmm15, qword ptr [rsi - 4]
cvtsi2sd xmm15, dword ptr [rsi + 4]
cvttss2si esi, xmm15
cvttsd2si esi, xmm15
cvtsi2ss xmm15, esi
cvtsi2sd xmm15, esi
cvttss2si rsi, xmm15
cvttsd2si rsi, xmm15
cvtsi2ss xmm15, rsi
cvtsi2sd xmm15, rsi
; Between: xmm15 and rdi
movss dword ptr [rdi - 4], xmm15
movsd qword ptr [rdi + 4], xmm15
movss xmm15, dword ptr [rdi - 4]
movsd xmm15, qword ptr [rdi + 4]
cvtsi2ss xmm15, qword ptr [rdi - 4]
cvtsi2sd xmm15, dword ptr [rdi + 4]
cvttss2si edi, xmm15
cvttsd2si edi, xmm15
cvtsi2ss xmm15, edi
cvtsi2sd xmm15, edi
cvttss2si rdi, xmm15
cvttsd2si rdi, xmm15
cvtsi2ss xmm15, rdi
cvtsi2sd xmm15, rdi
; Between: xmm15 and r8
movss dword ptr [r8 - 4], xmm15
movsd qword ptr [r8 + 4], xmm15
movss xmm15, dword ptr [r8 - 4]
movsd xmm15, qword ptr [r8 + 4]
cvtsi2ss xmm15, qword ptr [r8 - 4]
cvtsi2sd xmm15, dword ptr [r8 + 4]
cvttss2si r8d, xmm15
cvttsd2si r8d, xmm15
cvtsi2ss xmm15, r8d
cvtsi2sd xmm15, r8d
cvttss2si r8, xmm15
cvttsd2si r8, xmm15
cvtsi2ss xmm15, r8
cvtsi2sd xmm15, r8
; Between: xmm15 and r9
movss dword ptr [r9 - 4], xmm15
movsd qword ptr [r9 + 4], xmm15
movss xmm15, dword ptr [r9 - 4]
movsd xmm15, qword ptr [r9 + 4]
cvtsi2ss xmm15, qword ptr [r9 - 4]
cvtsi2sd xmm15, dword ptr [r9 + 4]
cvttss2si r9d, xmm15
cvttsd2si r9d, xmm15
cvtsi2ss xmm15, r9d
cvtsi2sd xmm15, r9d
cvttss2si r9, xmm15
cvttsd2si r9, xmm15
cvtsi2ss xmm15, r9
cvtsi2sd xmm15, r9
; Between: xmm15 and r10
movss dword ptr [r10 - 4], xmm15
movsd qword ptr [r10 + 4], xmm15
movss xmm15, dword ptr [r10 - 4]
movsd xmm15, qword ptr [r10 + 4]
cvtsi2ss xmm15, qword ptr [r10 - 4]
cvtsi2sd xmm15, dword ptr [r10 + 4]
cvttss2si r10d, xmm15
cvttsd2si r10d, xmm15
cvtsi2ss xmm15, r10d
cvtsi2sd xmm15, r10d
cvttss2si r10, xmm15
cvttsd2si r10, xmm15
cvtsi2ss xmm15, r10
cvtsi2sd xmm15, r10
; Between: xmm15 and r11
movss dword ptr [r11 - 4], xmm15
movsd qword ptr [r11 + 4], xmm15
movss xmm15, dword ptr [r11 - 4]
movsd xmm15, qword ptr [r11 + 4]
cvtsi2ss xmm15, qword ptr [r11 - 4]
cvtsi2sd xmm15, dword ptr [r11 + 4]
cvttss2si r11d, xmm15
cvttsd2si r11d, xmm15
cvtsi2ss xmm15, r11d
cvtsi2sd xmm15, r11d
cvttss2si r11, xmm15
cvttsd2si r11, xmm15
cvtsi2ss xmm15, r11
cvtsi2sd xmm15, r11
; Between: xmm15 and r12
movss dword ptr [r12 - 4], xmm15
movsd qword ptr [r12 + 4], xmm15
movss xmm15, dword ptr [r12 - 4]
movsd xmm15, qword ptr [r12 + 4]
cvtsi2ss xmm15, qword ptr [r12 - 4]
cvtsi2sd xmm15, dword ptr [r12 + 4]
cvttss2si r12d, xmm15
cvttsd2si r12d, xmm15
cvtsi2ss xmm15, r12d
cvtsi2sd xmm15, r12d
cvttss2si r12, xmm15
cvttsd2si r12, xmm15
cvtsi2ss xmm15, r12
cvtsi2sd xmm15, r12
; Between: xmm15 and r13
movss dword ptr [r13 - 4], xmm15
movsd qword ptr [r13 + 4], xmm15
movss xmm15, dword ptr [r13 - 4]
movsd xmm15, qword ptr [r13 + 4]
cvtsi2ss xmm15, qword ptr [r13 - 4]
cvtsi2sd xmm15, dword ptr [r13 + 4]
cvttss2si r13d, xmm15
cvttsd2si r13d, xmm15
cvtsi2ss xmm15, r13d
cvtsi2sd xmm15, r13d
cvttss2si r13, xmm15
cvttsd2si r13, xmm15
cvtsi2ss xmm15, r13
cvtsi2sd xmm15, r13
; Between: xmm15 and r14
movss dword ptr [r14 - 4], xmm15
movsd qword ptr [r14 + 4], xmm15
movss xmm15, dword ptr [r14 - 4]
movsd xmm15, qword ptr [r14 + 4]
cvtsi2ss xmm15, qword ptr [r14 - 4]
cvtsi2sd xmm15, dword ptr [r14 + 4]
cvttss2si r14d, xmm15
cvttsd2si r14d, xmm15
cvtsi2ss xmm15, r14d
cvtsi2sd xmm15, r14d
cvttss2si r14, xmm15
cvttsd2si r14, xmm15
cvtsi2ss xmm15, r14
cvtsi2sd xmm15, r14
; Between: xmm15 and r15
movss dword ptr [r15 - 4], xmm15
movsd qword ptr [r15 + 4], xmm15
movss xmm15, dword ptr [r15 - 4]
movsd xmm15, qword ptr [r15 + 4]
cvtsi2ss xmm15, qword ptr [r15 - 4]
cvtsi2sd xmm15, dword ptr [r15 + 4]
cvttss2si r15d, xmm15
cvttsd2si r15d, xmm15
cvtsi2ss xmm15, r15d
cvtsi2sd xmm15, r15d
cvttss2si r15, xmm15
cvttsd2si r15, xmm15
cvtsi2ss xmm15, r15
cvtsi2sd xmm15, r15
instructions ENDP
END
``` | /content/code_sandbox/src/Assembler/InstructionEncoding.asm | assembly | 2016-04-09T23:53:19 | 2024-06-29T07:05:56 | NativeJIT | BitFunnel/NativeJIT | 1,133 | 140,277 |
```powershell
$registersRxx = ("al", "cl", "dl", "bl", "spl", "bpl", "dil", "sil", "r8b", "r9b", "r10b", "r11b", "r12b", "r13b", "r14b", "r15b"),
("ax", "cx", "dx", "bx", "sp", "bp", "si", "di", "r8w", "r9w", "r10w", "r11w", "r12w", "r13w", "r14w", "r15w"),
("eax", "ecx", "edx", "ebx", "esp", "ebp", "esi", "edi", "r8d", "r9d", "r10d", "r11d", "r12d", "r13d", "r14d", "r15d"),
("rax", "rcx", "rdx", "rbx", "rsp", "rbp", "rsi", "rdi", "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15")
$registersXmm = ("xmm0", "xmm1", "xmm2", "xmm3", "xmm4", "xmm5", "xmm6", "xmm7", "xmm8", "xmm9", "xmm10", "xmm11", "xmm12", "xmm13", "xmm14", "xmm15")
@"
.code
instructions PROC
; Int <-> Int
"@
for ($srcRegId = 0; $srcRegId -lt $registersRxx[0].Count; $srcRegId++)
{
for ($destRegId = 0; $destRegId -lt $registersRxx[0].Count; $destRegId++)
{
$src8 = $registersRxx[0][$srcRegId]
$src16 = $registersRxx[1][$srcRegId]
$src32 = $registersRxx[2][$srcRegId]
$src64 = $registersRxx[3][$srcRegId]
$dest8 = $registersRxx[0][$destRegId]
$dest16 = $registersRxx[1][$destRegId]
$dest32 = $registersRxx[2][$destRegId]
$dest64 = $registersRxx[3][$destRegId]
@"
; Source: $src64, target: $dest64
mov $dest8, 1
mov $dest16, 1
mov $dest32, 1
mov $dest64, 1
mov $dest8, $src8
mov $dest16, $src16
mov $dest32, $src32
mov $dest64, $src64
mov $dest8, byte ptr [$src64 - 4]
mov $dest8, byte ptr [$src64 + 4]
mov $dest16, word ptr [$src64 + 4]
mov $dest32, dword ptr [$src64 + 4]
mov $dest64, qword ptr [$src64 + 4]
mov byte ptr [$dest64 - 4], $src8
mov byte ptr [$dest64 + 4], $src8
mov word ptr [$dest64 + 4], $src16
mov dword ptr [$dest64 + 4], $src32
mov qword ptr [$dest64 + 4], $src64
movzx $dest16, $src8
movzx $dest16, byte ptr [$src64 + 4]
movzx $dest32, $src8
movzx $dest32, $src16
movzx $dest32, byte ptr [$src64 + 4]
movzx $dest32, word ptr [$src64 + 4]
movzx $dest64, $src8
movzx $dest64, $src16
movzx $dest64, byte ptr [$src64 + 4]
movzx $dest64, word ptr [$src64 + 4]
"@
}
}
@"
; Float <-> float
"@
foreach ($src in $registersXmm)
{
foreach ($dest in $registersXmm)
{
@"
; Source: $src, target: $dest
movss $dest, $src
movsd $dest, $src
cvtss2sd $dest, $src
cvtsd2ss $dest, $src
"@
}
}
@"
; Float <-> Int
"@
foreach ($xmm in $registersXmm)
{
for ($rxxRegId = 0; $rxxRegId -lt $registersRxx[0].Count; $rxxRegId++)
{
$rxx32 = $registersRxx[2][$rxxRegId]
$rxx64 = $registersRxx[3][$rxxRegId]
@"
; Between: $xmm and $rxx64
movss dword ptr [$rxx64 - 4], $xmm
movsd qword ptr [$rxx64 + 4], $xmm
movss $xmm, dword ptr [$rxx64 - 4]
movsd $xmm, qword ptr [$rxx64 + 4]
cvtsi2ss $xmm, qword ptr [$rxx64 - 4]
cvtsi2sd $xmm, dword ptr [$rxx64 + 4]
cvttss2si $rxx32, $xmm
cvttsd2si $rxx32, $xmm
cvtsi2ss $xmm, $rxx32
cvtsi2sd $xmm, $rxx32
cvttss2si $rxx64, $xmm
cvttsd2si $rxx64, $xmm
cvtsi2ss $xmm, $rxx64
cvtsi2sd $xmm, $rxx64
"@
}
}
@"
instructions ENDP
END
"@
@"
//
// Int <-> int
//
"@
for ($srcRegId = 0; $srcRegId -lt $registersRxx[0].Count; $srcRegId++)
{
for ($destRegId = 0; $destRegId -lt $registersRxx[0].Count; $destRegId++)
{
$src8 = $registersRxx[0][$srcRegId]
$src16 = $registersRxx[1][$srcRegId]
$src32 = $registersRxx[2][$srcRegId]
$src64 = $registersRxx[3][$srcRegId]
$dest8 = $registersRxx[0][$destRegId]
$dest16 = $registersRxx[1][$destRegId]
$dest32 = $registersRxx[2][$destRegId]
$dest64 = $registersRxx[3][$destRegId]
@"
// Source: $src64, target: $dest64
buffer.EmitImmediate<OpCode::Mov>($dest8, static_cast<uint8_t>(1));
buffer.EmitImmediate<OpCode::Mov>($dest16, static_cast<uint16_t>(1));
buffer.EmitImmediate<OpCode::Mov>($dest32, 1);
buffer.EmitImmediate<OpCode::Mov>($dest64, 1);
buffer.Emit<OpCode::Mov>($dest8, $src8);
buffer.Emit<OpCode::Mov>($dest16, $src16);
buffer.Emit<OpCode::Mov>($dest32, $src32);
buffer.Emit<OpCode::Mov>($dest64, $src64);
buffer.Emit<OpCode::Mov>($dest8, $src64, -4);
buffer.Emit<OpCode::Mov>($dest8, $src64, 4);
buffer.Emit<OpCode::Mov>($dest16, $src64, 4);
buffer.Emit<OpCode::Mov>($dest32, $src64, 4);
buffer.Emit<OpCode::Mov>($dest64, $src64, 4);
buffer.Emit<OpCode::Mov>($dest64, -4, $src8);
buffer.Emit<OpCode::Mov>($dest64, 4, $src8);
buffer.Emit<OpCode::Mov>($dest64, 4, $src16);
buffer.Emit<OpCode::Mov>($dest64, 4, $src32);
buffer.Emit<OpCode::Mov>($dest64, 4, $src64);
buffer.Emit<OpCode::MovZX>($dest16, $src8);
buffer.Emit<OpCode::MovZX, 2, false, 1, false>($dest16, $src64, 4);
buffer.Emit<OpCode::MovZX>($dest32, $src8);
buffer.Emit<OpCode::MovZX>($dest32, $src16);
buffer.Emit<OpCode::MovZX, 4, false, 1, false>($dest32, $src64, 4);
buffer.Emit<OpCode::MovZX, 4, false, 2, false>($dest32, $src64, 4);
buffer.Emit<OpCode::MovZX>($dest64, $src8);
buffer.Emit<OpCode::MovZX>($dest64, $src16);
buffer.Emit<OpCode::MovZX, 8, false, 1, false>($dest64, $src64, 4);
buffer.Emit<OpCode::MovZX, 8, false, 2, false>($dest64, $src64, 4);
"@
}
}
@"
//
// Float <-> float
//
"@
foreach ($src in $registersXmm)
{
foreach ($dest in $registersXmm)
{
$src32 = "${src}s"
$src64 = $src
$dest32 = "${dest}s"
$dest64 = $dest
@"
// Source: $src, target: $dest
buffer.Emit<OpCode::Mov>($dest32, $src32);
buffer.Emit<OpCode::Mov>($dest64, $src64);
buffer.Emit<OpCode::CvtFP2FP>($dest64, $src32);
buffer.Emit<OpCode::CvtFP2FP>($dest32, $src64);
"@
}
}
@"
//
// Float <-> int
//
"@
foreach ($xmm in $registersXmm)
{
for ($rxxRegId = 0; $rxxRegId -lt $registersRxx[0].Count; $rxxRegId++)
{
$xmm32 = "${xmm}s"
$xmm64 = $xmm
$rxx32 = $registersRxx[2][$rxxRegId]
$rxx64 = $registersRxx[3][$rxxRegId]
@"
// Between: $xmm and $rxx64
buffer.Emit<OpCode::Mov>($rxx64, -4, $xmm32);
buffer.Emit<OpCode::Mov>($rxx64, 4, $xmm64);
buffer.Emit<OpCode::Mov>($xmm32, $rxx64, -4);
buffer.Emit<OpCode::Mov>($xmm64, $rxx64, 4);
buffer.Emit<OpCode::CvtSI2FP, 4, true, 8, false>($xmm32, $rxx64, -4);
buffer.Emit<OpCode::CvtSI2FP, 8, true, 4, false>($xmm64, $rxx64, 4);
buffer.Emit<OpCode::CvtFP2SI>($rxx32, $xmm32);
buffer.Emit<OpCode::CvtFP2SI>($rxx32, $xmm64);
buffer.Emit<OpCode::CvtSI2FP>($xmm32, $rxx32);
buffer.Emit<OpCode::CvtSI2FP>($xmm64, $rxx32);
buffer.Emit<OpCode::CvtFP2SI>($rxx64, $xmm32);
buffer.Emit<OpCode::CvtFP2SI>($rxx64, $xmm64);
buffer.Emit<OpCode::CvtSI2FP>($xmm32, $rxx64);
buffer.Emit<OpCode::CvtSI2FP>($xmm64, $rxx64);
"@
}
}
``` | /content/code_sandbox/src/Assembler/GenerateModRMTest.ps1 | powershell | 2016-04-09T23:53:19 | 2024-06-29T07:05:56 | NativeJIT | BitFunnel/NativeJIT | 1,133 | 2,732 |
```batchfile
rem Permission is hereby granted, free of charge, to any person obtaining a copy
rem of this software and associated documentation files (the "Software"), to deal
rem in the Software without restriction, including without limitation the rights
rem to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
rem copies of the Software, and to permit persons to whom the Software is
rem furnished to do so, subject to the following conditions:
rem The above copyright notice and this permission notice shall be included in
rem all copies or substantial portions of the Software.
rem THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
rem IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
rem FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
rem AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
rem LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
rem OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
rem THE SOFTWARE.
"c:\Program Files (x86)\Microsoft Visual Studio 14.0\VC\bin\x86_amd64\ml64.exe" /c /nologo /Sn /FlTestAsm.lst TestAsm.asm
REM "c:\Program Files (x86)\Microsoft Visual Studio 14.0\VC\bin\x86_amd64\ml64.exe" /c /nologo /FlTestAsm.lst /Sn TestAsm.asm
REM type TestAsm.lst
``` | /content/code_sandbox/src/Assembler/asm.bat | batchfile | 2016-04-09T23:53:19 | 2024-06-29T07:05:56 | NativeJIT | BitFunnel/NativeJIT | 1,133 | 324 |
```powershell
# Assembles the input file and formats the output in the format used by ml64Output in CodeGenUnitTest.cpp.
Param([string]$InputFile = "TestAsm.asm",
[string]$OutputFile = "TestAsm.lst",
[string]$MlPath = "c:\Program Files (x86)\Microsoft Visual Studio 12.0\VC\bin\x86_amd64\ml64.exe",
[int]$IndentLength = 16,
[int]$QuotedLineLength = 99)
function Expand-Tabs
{
[CmdletBinding()]
Param([Parameter(Position = 0,
ValueFromPipeline = $true)]
[string]$Text,
[UInt16]$TabSize = 8)
process
{
$expandedLine = ""
$numExpansions = 0
foreach ($portion in ($Text -split "`t"))
{
if ($numExpansions -gt 0)
{
$expandedLine += " " * ($TabSize - $expandedLine.Length % $TabSize)
}
$expandedLine += $portion
$numExpansions++
}
$expandedLine
}
}
& cmd /c "$MlPath" /nologo /c /Sn /Fl"$OutputFile" "$InputFile" | Out-Null
# Expand tabs and format as [indent]"line \n".
#
# Note: Masm has what seems to be a bug where it sometimes concatenates the cvtsi2ss
# instruction with its byte code, which confuses ML64Verifier. The replace mitigates that.
$lines = Get-Content "$OutputFile" `
| Expand-Tabs -TabSize 8 `
| %{ "{0,-$IndentLength}`"{1,-$QuotedLineLength}\n`"" -f " ", $_ } `
| %{ $_ -creplace "([^ ])cvtsi2ss", '$1 cvtsi2ss' }
# Add [indent]""; to end the string.
$lines += "{0,-$IndentLength}`"`";" -f " "
# Print the header.
@"
std::string ml64Output;
ml64Output +=
"@
$currentLength = 0
foreach ($line in $lines)
{
$currentLength += $line.Length
# If next line is likely to overflow, split into a new string. MSVC can't handle strings larger than 64 kB.
# This is overestimating the length of the line as it also includes the spaces before/after the string.
if ($currentLength + $line.Length -ge 65535)
{
@"
$line;
ml64Output +=
"@
$currentLength = 0
}
else
{
$line
}
}
if ($currentLength -eq 0)
{
' "";'
}
@"
ML64Verifier v(ml64Output.c_str(), start);
"@
``` | /content/code_sandbox/src/Assembler/asmAndFormat.ps1 | powershell | 2016-04-09T23:53:19 | 2024-06-29T07:05:56 | NativeJIT | BitFunnel/NativeJIT | 1,133 | 629 |
```assembly
; Permission is hereby granted, free of charge, to any person obtaining a copy
; of this software and associated documentation files (the "Software"), to deal
; in the Software without restriction, including without limitation the rights
; to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
; copies of the Software, and to permit persons to whom the Software is
; furnished to do so, subject to the following conditions:
; The above copyright notice and this permission notice shall be included in
; all copies or substantial portions of the Software.
; THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
; IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
; FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
; AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
; LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
; OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
; THE SOFTWARE.
; Description:
;
; Revision date:
.data
myMessage BYTE "MASM program example",0dh,0ah,0
.code
main PROC
mov rcx, 16;
mov rax, 1234567812345678h
mov rbx, 2108765432108765h
; expect 2238767832348778
l0:
cmp rax, rbx
jae l1
; rbx is greater - shift its high bits into the low bits of rax
shld rax,rbx, 4
jmp l2
l1:
; rax is greater - rotate its high bits into the low bits of rax
rol rax, 4
l2:
; both cases, shift the high order bits of rbx out of the way
shl rbx, 4
;; decrement the loop counter and go back to the top if there are more fields
dec rcx
jnz l0
ret
shld rax, rbx, 4
;movd xmm1, rax
;vprotq xmm0, xmm1, 4
add [rcx + 5], rax
add rax, [rcx + 5]
movd xmm0, rax
movsd xmm0, xmm1
; vmovq xmm0, rax // Illegal instruction
ret
; Bit operations
bsf rax, r14
bsr r15, r13
bt eax, ecx
btc bx, dx
btr esi, edi
bts r8d, r12d
; Stosq
rep stosq
; Dec
dec al
dec ax
dec eax
dec rax
dec r12
dec byte ptr [r12 + 1234h]
dec word ptr [r13 + 1234h]
dec dword ptr [r14 + 1234h]
dec qword ptr [r15 + 1234h]
; Inc
inc r9b
inc r10w
inc r11d
inc r12
inc byte ptr [rax + 1234h]
inc word ptr [rbp + 1234h]
inc dword ptr [rsi + 1234h]
inc qword ptr [rdi + 1234h]
; Neg
neg rbx
neg qword ptr [rbp + 56h]
; Not
not bl
not word ptr [rbp + 56h]
; SIB reads
mov rax, [rsi + rcx * 8 + 1234h]
mov r15, [r14 + r13 * 8 + 1234h]
mov al, [rcx + r13 * 8 + 12h]
mov bx, [r15 + rax * 8 + 34h]
and rax, [rsi + rcx * 8 + 1234h]
and r15, [r14 + r13 * 8 + 1234h]
and al, [rcx + r13 * 8 + 12h]
and bx, [r15 + rax * 8 + 34h]
and rax, [rdi + rdx * 1 + 5678h]
and rax, [rdi + rdx * 2 + 5678h]
and rax, [rdi + rdx * 4 + 5678h]
and rax, [rdi + rdx * 8 + 5678h]
; SIB writes
mov [rsi + rcx * 8 + 1234h], rax
mov [r14 + r13 * 8 + 1234h], r15
mov [rcx + r13 * 8 + 12h], al
mov [r15 + rax * 8 + 34h], bx
and [rsi + rcx * 8 + 1234h], rax
and [r14 + r13 * 8 + 1234h], r15
and [rcx + r13 * 8 + 12h], al
and [r15 + rax * 8 + 34h], bx
and [rdi + rdx * 1 + 5678h], rax
and [rdi + rdx * 2 + 5678h], rax
and [rdi + rdx * 4 + 5678h], rax
and [rdi + rdx * 8 + 5678h], rax
; Another special case
add r13, [r13]
mov r13, [r13]
mov rax, [rbp]
mov rax, [rbp + 12h]
mov rbx, [r13 + 34h]
mov rcx, [rbp + 1234h]
;
; Mod/RM special cases for RSP and R12 and [RBP] ==> [RBP + disp8]
;
sub rbx, [r12]
sub rdi, [r12 + 12h]
sub rbp, [r12 + 1234h]
sub r10, [r12 + 12345678h]
;
; Mod/RM case for R8..R15
;
;
; REX W bit. X bit.
;
;
; Group1 addressing mode permutations for a single opcode.
;
; direct-direct
add al, cl
add bx, dx
add esi, eax
add rax, rbx
add r8, r9
add rsp, r12
; direct-indirect with zero, byte, word, and double word offsets
add cl, byte ptr [rax]
add bl, byte ptr [rcx + 12h]
add r9b, byte ptr [rsi + 100h]
add r15b, byte ptr [rdi + 12345678h]
add dx, word ptr [rdx]
add cx, word ptr [rcx + 12h]
add r9w, word ptr [rsi + 1234h]
add r11w, word ptr [rdi + 12345678h]
add edx, dword ptr [rdx]
add ecx, dword ptr [rcx + 12h]
add r9d, dword ptr [rsi + 1234h]
add r11d, dword ptr [rdi + 12345678h]
add rdx, qword ptr [rdx]
add rcx, qword ptr [rcx + 12h]
add r9, qword ptr [rsi + 1234h]
add r11, qword ptr [rdi + 12345678h]
; indirect-direct with zero, byte, word, and double word offsets
add byte ptr [rax], cl
add byte ptr [rcx + 12h], bl
add byte ptr [rsi + 100h], r9b
add byte ptr [rdi + 12345678h], r15b
add word ptr [rdx], dx
add word ptr [rcx + 12h], cx
add word ptr [rsi + 1234h], r9w
add word ptr [rdi + 12345678h], r11w
add dword ptr [rdx], edx
add dword ptr [rcx + 12h], ecx
add dword ptr [rsi + 1234h], r9d
add dword ptr [rdi + 12345678h], r11d
add qword ptr [rdx], rdx
add qword ptr [rcx + 12h], rcx
add qword ptr [rsi + 1234h], r9
add qword ptr [rdi + 12345678h], r11
; direct-immediate register 0 case
add al, 34h
add ax, 56h
add ax, 5678h
add eax, 12h
add eax, 1234h
add eax, 12345678h
add rax, 12h
add rax, 1234h
add rax, 12345678h
; direct-immediate general purpose register case
add bl, 34h
add r13b, 34h
add cx, 56h
add dx, 5678h
add ebp, 12h
add ebp, 1234h
add ebp, 12345678h
add r12, 12h
add r12, 1234h
add r12, 12345678h
; Direct-immediate, different opcodes depending on
; whether sign extension is acceptable.
;
; The immediates that will be sign extended or will use the
; sign-extend opcode in cases when it makes no difference
; (when both source and target are 1-byte).
;
; The first two lines would correctly fail to compile in NativeJIT
; and are thus commented out. They would produce the value of
; FFFFFFFF80000000h unexpectedly since sign extension is unconditionally
; used for 32-bit immediates targeting 64-bit registers.
;
; add rax, 80000000h
; add rcx, 80000000h
add rax, -7fffffffh
add rcx, -7fffffffh
add cl, -7fh
add cl, 80h
add cx, -7fh
add ecx, -7fh
add rcx, -7fh
; The immediates that will not be sign extended.
add cx, 80h
add ecx, 80h
add rcx, 80h
;
; Verify various flavors of each Group1 opcode.
; These instructions excercise all different flavors
; which use different base opcode and extension. The
; generic Group1 encoding was already verified with
; the add instruction above.
;
and al, 11h
and eax, 11223344h
and dl, 11h
and edx, 11223344h
and edx, 11h
and byte ptr [rbx + 1], dl
and dword ptr [rcx + 4], edx
and dl, byte ptr [rbx + 1]
and edx, dword ptr [rcx + 4]
cmp al, 11h
cmp eax, 11223344h
cmp dl, 11h
cmp edx, 11223344h
cmp edx, 11h
cmp byte ptr [rbx + 1], dl
cmp dword ptr [rcx + 4], edx
cmp dl, byte ptr [rbx + 1]
cmp edx, dword ptr [rcx + 4]
or al, 11h
or eax, 11223344h
or dl, 11h
or edx, 11223344h
or edx, 11h
or byte ptr [rbx + 1], dl
or dword ptr [rcx + 4], edx
or dl, byte ptr [rbx + 1]
or edx, dword ptr [rcx + 4]
sub al, 11h
sub eax, 11223344h
sub dl, 11h
sub edx, 11223344h
sub edx, 11h
sub byte ptr [rbx + 1], dl
sub dword ptr [rcx + 4], edx
sub dl, byte ptr [rbx + 1]
sub edx, dword ptr [rcx + 4]
xor al, 11h
xor eax, 11223344h
xor dl, 11h
xor edx, 11223344h
xor edx, 11h
xor byte ptr [rbx + 1], dl
xor dword ptr [rcx + 4], edx
xor dl, byte ptr [rbx + 1]
xor edx, dword ptr [rcx + 4]
;
; Lea
;
lea rax, [rsi]
lea rax, [rsi + 12h]
lea rax, [rsi - 12h]
lea rax, [rsi + 1234h]
lea rax, [rsi - 1234h]
lea rax, [rsi + 12345678h]
lea rax, [rsi - 12345678h]
lea rbp, [r12]
lea rbp, [r12 + 87h]
lea rbp, [r12 - 789ABCDEh]
lea rbp, [rsp + 20h]
lea rsp, [rbp - 20h]
;
; Mov
;
mov al, cl
mov bx, dx
mov esi, eax
mov rax, rbx
mov r8, r9
mov rsp, r12
mov cl, [rax]
mov bl, [rcx + 12h]
mov r9b, [rsi + 100h]
mov r15b, [rdi + 12345678h]
mov dl, [rdx]
mov cx, [rcx + 12h]
mov r9w, [rsi + 1234h]
mov r11w, [rdi + 12345678h]
mov esp, [r9]
mov edx, [rcx + 12h]
mov esi, [rsi + 1234h]
mov r11d, [rdi + 12345678h]
mov rbx, [r12]
mov rdi, [rcx + 12h]
mov rbp, [rsi + 1234h]
mov r10, [rdi + 12345678h]
; mov r, imm - register 0 case
mov al, 0
mov al, 34h
mov ax, 56h
mov ax, 5678h
mov eax, 12h
mov eax, 1234h
mov eax, 12345678h
mov rax, 12h
mov rax, 1234h
mov rax, 12345678h
mov rax, 80000000h
mov rax, -1
; mov r, imm - general purpose register case
mov bl, 0
mov bl, 34h
mov r13b, 34h
mov cx, 56h
mov dx, 5678h
mov ebp, 12h
mov ebp, 1234h
mov ebp, 12345678h
mov r12, 12h
mov r12, 1234h
mov r12, 12345678h
mov r12, 80000000h
mov rbx, 1234567812345678h
mov rsp, 1234567812345678h
mov r12, 1234567812345678h
; Test for immediate T*
mov rax, 2234567812345678h
; mov [r + offset], r with zero, byte, word, and dword offsets
mov [rax], cl
mov [rcx + 12h], bl
mov [rsi + 100h], r9b
mov [rdi + 12345678h], r15b
mov [rdx], dl
mov [rcx + 12h], cx
mov [rsi + 1234h], r9w
mov [rdi + 12345678h], r11w
mov [r9], esp
mov [rcx + 12h], edx
mov [rsi + 1234h], esi
mov [rdi + 12345678h], r11d
mov [r12], rbx
mov [rcx + 12h], rdi
mov [rsi + 1234h], rbp
mov [rdi + 12345678h], r10
;
; Push/Pop
;
pop rax
pop rbp
pop r12
push rbx
push rbp
push r12
;
; Ret
;
ret
LL1:
jz LL1
jz near ptr LL1
jz LL1
jz near ptr LL1
; jz far ptr LL1
;
; Imul
;
imul bx, cx
imul ebx, ecx
imul rbx, rcx
imul rax, rbx;
imul r8, r9;
imul ax, bx;
imul cx, [rcx + 12h]
imul r9w, [rsi + 1234h]
imul r11w, [rdi + 12345678h]
imul esp, [r9]
imul edx, [rcx + 12h]
imul esi, [rsi + 1234h]
imul r11d, [rdi + 12345678h]
imul rbx, [r12]
imul rdi, [rcx + 12h]
imul rbp, [rsi + 1234h]
imul r10, [rdi + 12345678h]
imul cx, 56h
imul cx, 80h
imul dx, 5678h
imul ebp, 12h
imul ebp, 1234h
imul ebp, 12345678h
imul r12, 12h
imul r12, 1234h
imul r12, 12345678h
imul r12, -1
call rax
call rsp
call rbp
call r12
call r13
mov rax, 07fffffffffffffffh
movd xmm1, rax
movd xmm1, rcx
movd xmm1, r8
movd xmm1, rbp
movd xmm1, r12
movd xmm0, rcx
movd xmm1, rcx
movd xmm2, rcx
movd xmm5, rcx
movd xmm12, rcx
movd xmm1, eax
movd xmm1, ecx
movd xmm1, r8d
movd xmm1, ebp
movd xmm1, r12d
movd xmm0, ecx
movd xmm1, ecx
movd xmm2, ecx
movd xmm5, ecx
movd xmm12, ecx
; movss
movss xmm1, xmm2
movss xmm0, xmm12
movss xmm5, xmm12
movss xmm5, xmm3
movss xmm13, xmm5
movss xmm0, xmm15
movss xmm0, dword ptr [r12]
movss xmm4, dword ptr [rcx + 12h]
movss xmm5, dword ptr [rsi + 1234h]
movss xmm12, dword ptr [rdi + 12345678h]
movss dword ptr [r12], xmm0
movss dword ptr [rcx + 12h], xmm4
movss dword ptr [rsi + 1234h], xmm5
movss dword ptr [rdi + 12345678h], xmm12
; movsd
movsd xmm1, xmm2
movsd xmm0, xmm12
movsd xmm5, xmm12
movsd xmm5, xmm3
movsd xmm13, xmm5
movsd xmm0, xmm15
movsd xmm0, qword ptr [r12]
movsd xmm4, qword ptr [rcx + 12h]
movsd xmm5, qword ptr [rsi + 1234h]
movsd xmm12, qword ptr [rdi + 12345678h]
movsd qword ptr [r12], xmm0
movsd qword ptr [rcx + 12h], xmm4
movsd qword ptr [rsi + 1234h], xmm5
movsd qword ptr [rdi + 12345678h], xmm12
addsd xmm1, xmm2
addsd xmm0, xmm12
mulsd xmm5, xmm12
mulsd xmm5, xmm3
subsd xmm13, xmm5
subsd xmm0, xmm15
addsd xmm0, qword ptr [r12]
addsd xmm4, qword ptr [rcx + 12h]
mulsd xmm5, qword ptr [rsi + 1234h]
subsd xmm12, qword ptr [rdi + 12345678h]
addss xmm1, xmm2
addss xmm0, xmm12
mulss xmm5, xmm12
mulss xmm5, xmm3
subss xmm13, xmm5
subss xmm0, xmm15
addss xmm0, dword ptr [r12]
addss xmm4, dword ptr [rcx + 12h]
mulss xmm5, dword ptr [rsi + 1234h]
subss xmm12, dword ptr [rdi + 12345678h]
;
; MovZX
;
; 1 byte to 2, 4 and 8.
movzx bx, bl
movzx bx, r12b
movzx r9w, dl
movzx bx, byte ptr [rcx + 12h]
movzx bx, byte ptr [r9 + 34h]
movzx ebx, bl
movzx ebx, r12b
movzx r9d, dl
movzx ebx, byte ptr [rcx + 12h]
movzx ebx, byte ptr [r9 + 34h]
movzx rbx, bl
movzx rbx, r12b
movzx r9, dl
movzx rbx, byte ptr [rcx + 12h]
movzx rbx, byte ptr [r9 + 34h]
; 2 bytes to 4 and 8
movzx ebx, bx
movzx ebx, r12w
movzx r9d, dx
movzx ebx, word ptr [rcx + 12h]
movzx ebx, word ptr [r9 + 34h]
movzx rbx, bx
movzx rbx, r12w
movzx r9, dx
movzx rbx, word ptr [rcx + 12h]
movzx rbx, word ptr [r9 + 34h]
; 4 bytes to 8, implemented in terms of mov
mov ebx, ebx
mov ebx, r12d
mov r9d, edx
mov ebx, dword ptr [rcx + 12h]
mov ebx, dword ptr [r9 + 34h]
;
; MovSX
;
; 1 byte to 2, 4 and 8.
movsx bx, bl
movsx bx, r12b
movsx r9w, dl
movsx bx, byte ptr [rcx + 12h]
movsx bx, byte ptr [r9 + 34h]
movsx ebx, bl
movsx ebx, r12b
movsx r9d, dl
movsx ebx, byte ptr [rcx + 12h]
movsx ebx, byte ptr [r9 + 34h]
movsx rbx, bl
movsx rbx, r12b
movsx r9, dl
movsx rbx, byte ptr [rcx + 12h]
movsx rbx, byte ptr [r9 + 34h]
; 2 bytes to 4 and 8
movsx ebx, bx
movsx ebx, r12w
movsx r9d, dx
movsx ebx, word ptr [rcx + 12h]
movsx ebx, word ptr [r9 + 34h]
movsx rbx, bx
movsx rbx, r12w
movsx r9, dx
movsx rbx, word ptr [rcx + 12h]
movsx rbx, word ptr [r9 + 34h]
; 4 bytes to 8
movsxd rbx, ebx
movsxd rbx, r12d
movsxd r9, edx
movsxd rbx, dword ptr [rcx + 12h]
movsxd rbx, dword ptr [r9 + 34h]
;
; Aligned 128-bit floating point move: movaps and movapd
;
movaps xmm1, xmm1
movaps xmm2, xmm9
movaps xmm2, dword ptr [rcx + 20h]
movaps xmm2, dword ptr [r9 + 200h]
movaps dword ptr [rcx + 20h], xmm2
movaps dword ptr [r9 + 20h], xmm2
movaps dword ptr [r9 + 200h], xmm11
movapd xmm1, xmm1
movapd xmm2, xmm9
movapd xmm2, qword ptr [rcx + 20h]
movapd xmm2, qword ptr [r9 + 200h]
movapd qword ptr [rcx + 20h], xmm2
movapd qword ptr [r9 + 20h], xmm2
movapd qword ptr [r9 + 200h], xmm11
;
; CvtSI2SD/CvtSI2SS
;
cvtsi2ss xmm1, eax
cvtsi2ss xmm1, rax
cvtsi2ss xmm9, rbx
cvtsi2ss xmm1, r8
cvtsi2ss xmm1, dword ptr [rcx + 12h]
cvtsi2ss xmm1, dword ptr [r9 + 34h]
cvtsi2ss xmm1, qword ptr [rcx + 56h]
cvtsi2sd xmm1, eax
cvtsi2sd xmm1, rax
cvtsi2sd xmm9, rbx
cvtsi2sd xmm1, r8
cvtsi2sd xmm1, dword ptr [rcx + 12h]
cvtsi2sd xmm1, dword ptr [r9 + 34h]
cvtsi2sd xmm1, qword ptr [rcx + 56h]
;
; CvtTSD2SI/CvtTSS2SI
;
cvttss2si eax, xmm1
cvttss2si rax, xmm1
cvttss2si rbx, xmm9
cvttss2si r8, xmm1
cvttss2si ebx, dword ptr [rcx + 12h]
cvttss2si ebx, dword ptr [r9 + 34h]
cvttss2si rbx, dword ptr [rcx + 56h]
cvttsd2si eax, xmm1
cvttsd2si rax, xmm1
cvttsd2si rbx, xmm9
cvttsd2si r8, xmm1
cvttsd2si ebx, qword ptr [rcx + 12h]
cvttsd2si ebx, qword ptr [r9 + 34h]
cvttsd2si rbx, qword ptr [rcx + 56h]
;
; Conversion, float - cvtss2sd and cvtsd2ss
;
cvtss2sd xmm1, xmm1
cvtss2sd xmm2, xmm9
cvtss2sd xmm2, dword ptr [rcx + 20h]
cvtss2sd xmm2, dword ptr [r9 + 200h]
cvtsd2ss xmm1, xmm1
cvtsd2ss xmm2, xmm9
cvtsd2ss xmm2, qword ptr [rcx + 20h]
cvtsd2ss xmm2, qword ptr [r9 + 200h]
;
; Floating point comparison, comiss and comisd.
;
comiss xmm1, xmm1
comiss xmm2, xmm9
comiss xmm2, dword ptr [rcx + 20h]
comiss xmm2, dword ptr [r9 + 200h]
comisd xmm1, xmm1
comisd xmm2, xmm9
comisd xmm2, qword ptr [rcx + 20h]
comisd xmm2, qword ptr [r9 + 200h]
;
; Shift/rotate
;
rol al, cl
shl ebx, cl
shr r12, cl
rol rax, 3
shl bl, 4
shr r12d, 5
shld ax, bx, 11
shld edx, esi, 24
shld r12, rbp, 43
shld rbp, r12, 43
shld ax, bx, cl
shld edx, esi, cl
shld r12, rbp, cl
shld rbp, r12, cl
main ENDP
END
``` | /content/code_sandbox/src/Assembler/TestAsm.asm | assembly | 2016-04-09T23:53:19 | 2024-06-29T07:05:56 | NativeJIT | BitFunnel/NativeJIT | 1,133 | 6,451 |
```c++
// Permission is hereby granted, free of charge, to any person obtaining a copy
// of this software and associated documentation files (the "Software"), to deal
// in the Software without restriction, including without limitation the rights
// to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
// copies of the Software, and to permit persons to whom the Software is
// furnished to do so, subject to the following conditions:
// The above copyright notice and this permission notice shall be included in
// all copies or substantial portions of the Software.
// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
// AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
// LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
// OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
// THE SOFTWARE.
#include "NativeJIT/BitOperations.h"
#include "NativeJIT/CodeGen/CallingConvention.h"
#include "NativeJIT/CodeGen/FunctionBuffer.h"
#include "NativeJIT/Nodes/CallNode.h"
namespace NativeJIT
{
//*************************************************************************
//
// SaveRestoreVolatilesHelper
//
//*************************************************************************
SaveRestoreVolatilesHelper::SaveRestoreVolatilesHelper(Allocators::IAllocator& allocator)
: m_rxxCallExclusiveRegisterMask(0),
m_xmmCallExclusiveRegisterMask(0),
m_preservationStorage(Allocators::StlAllocator<void*>(allocator))
{
m_preservationStorage.reserve(RegisterBase::c_maxIntegerRegisterID + 1
+ RegisterBase::c_maxIntegerRegisterID + 1);
}
template<>
unsigned SaveRestoreVolatilesHelper::GetRegistersToPreserve<false>(ExpressionTree& tree) const
{
// Save all used volatiles, except those used in and *fully* owned by
// the call itself.
return CallingConvention::c_rxxVolatileRegistersMask
& CallingConvention::c_rxxWritableRegistersMask
& tree.GetRXXUsedMask()
& ~m_rxxCallExclusiveRegisterMask;
}
template<>
unsigned SaveRestoreVolatilesHelper::GetRegistersToPreserve<true>(ExpressionTree& tree) const
{
// Save all used volatiles, except those used in and *fully* owned by
// the call itself.
return CallingConvention::c_xmmVolatileRegistersMask
& CallingConvention::c_xmmWritableRegistersMask
& tree.GetXMMUsedMask()
& ~m_xmmCallExclusiveRegisterMask;
}
void SaveRestoreVolatilesHelper::SaveVolatiles(ExpressionTree& tree)
{
auto & code = tree.GetCodeGenerator();
unsigned rxxVolatiles = GetRegistersToPreserve<false>(tree);
unsigned r = 0;
while (BitOp::GetLowestBitSet(rxxVolatiles, &r))
{
m_preservationStorage.push_back(tree.Temporary<void*>());
auto const & s = m_preservationStorage.back();
code.Emit<OpCode::Mov>(s.GetBaseRegister(),
s.GetOffset(),
Register<8, false>(r));
BitOp::ClearBit(&rxxVolatiles, r);
}
unsigned xmmVolatiles = GetRegistersToPreserve<true>(tree);
while (BitOp::GetLowestBitSet(xmmVolatiles, &r))
{
// DESIGN NOTE: This preserves only the lower 64 bits of the XMM register.
// That is currently fine as NativeJIT only uses floats and doubles
// which don't overlap with the upper 64-bits. Also, the full 128
// bits of XMM nonvolatiles are preserved in the function prolog
// by FunctionBuffer. To be fully correct, this should preserve
// all 128 bits (f. ex. allow Temporary() to return 16-byte
// aligned 16-byte space and use movaps to save the whole register).
// RestoreVolatiles() needs to be modified accordingly as well.
m_preservationStorage.push_back(tree.Temporary<void*>());
auto const & s = m_preservationStorage.back();
code.Emit<OpCode::Mov>(s.GetBaseRegister(),
s.GetOffset(),
Register<8, true>(r));
BitOp::ClearBit(&xmmVolatiles, r);
}
}
void SaveRestoreVolatilesHelper::RestoreVolatiles(ExpressionTree& tree)
{
auto & code = tree.GetCodeGenerator();
// Do everything in the reverse order, including popping XMM registers first.
unsigned xmmVolatiles = GetRegistersToPreserve<true>(tree);
unsigned r = 0;
while (BitOp::GetHighestBitSet(xmmVolatiles, &r))
{
LogThrowAssert(!m_preservationStorage.empty(), "Logic error");
auto const & s = m_preservationStorage.back();
code.Emit<OpCode::Mov>(Register<8, true>(r),
s.GetBaseRegister(),
s.GetOffset());
m_preservationStorage.pop_back();
BitOp::ClearBit(&xmmVolatiles, r);
}
unsigned rxxVolatiles = GetRegistersToPreserve<false>(tree);
while (BitOp::GetHighestBitSet(rxxVolatiles, &r))
{
LogThrowAssert(!m_preservationStorage.empty(), "Logic error");
auto const & s = m_preservationStorage.back();
code.Emit<OpCode::Mov>(Register<8, false>(r),
s.GetBaseRegister(),
s.GetOffset());
m_preservationStorage.pop_back();
BitOp::ClearBit(&rxxVolatiles, r);
}
}
}
``` | /content/code_sandbox/src/NativeJIT/CallNode.cpp | c++ | 2016-04-09T23:53:19 | 2024-06-29T07:05:56 | NativeJIT | BitFunnel/NativeJIT | 1,133 | 1,280 |
```c++
// Permission is hereby granted, free of charge, to any person obtaining a copy
// of this software and associated documentation files (the "Software"), to deal
// in the Software without restriction, including without limitation the rights
// to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
// copies of the Software, and to permit persons to whom the Software is
// furnished to do so, subject to the following conditions:
// The above copyright notice and this permission notice shall be included in
// all copies or substantial portions of the Software.
// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
// AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
// LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
// OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
// THE SOFTWARE.
#include "NativeJIT/CodeGen/CallingConvention.h"
#include "NativeJIT/CodeGen/FunctionBuffer.h"
#include "NativeJIT/CodeGen/FunctionSpecification.h"
#include "NativeJIT/ExecutionPreconditionTest.h"
#include "NativeJIT/Nodes/ParameterNode.h"
namespace NativeJIT
{
//*************************************************************************
//
// ExpressionTree
//
//*************************************************************************
ExpressionTree::ExpressionTree(Allocators::IAllocator& allocator, FunctionBuffer& code)
: m_allocator(allocator),
m_stlAllocator(allocator),
m_code(code),
m_diagnosticsStream(nullptr),
// Note: there is a member initialization order dependency on
// m_stlAllocator for multiple members below.
m_topologicalSort(m_stlAllocator),
m_parameters(m_stlAllocator),
m_ripRelatives(m_stlAllocator),
m_preconditionTests(m_stlAllocator),
m_rxxFreeList(allocator),
m_xmmFreeList(allocator),
m_reservedRxxRegisterStorages(m_stlAllocator),
m_reservedXmmRegisterStorages(m_stlAllocator),
m_reservedRegistersPins(m_stlAllocator),
m_temporaryCount(0),
m_temporaries(m_stlAllocator),
m_maxFunctionCallParameters(-1),
m_basePointer(rbp)
// m_startOfEpilogue intentionally left uninitialized, see Compile().
{
m_reservedRxxRegisterStorages.reserve(RegisterBase::c_maxIntegerRegisterID + 1);
m_reservedXmmRegisterStorages.reserve(RegisterBase::c_maxFloatRegisterID + 1);
m_reservedRegistersPins.reserve(RegisterBase::c_maxIntegerRegisterID
+ RegisterBase::c_maxFloatRegisterID
+ 2);
for (unsigned i = 0 ; i <= RegisterBase::c_maxIntegerRegisterID; ++i)
{
const PointerRegister reg(i);
if (IsAnySharedBaseRegister(reg)
|| !BitOp::TestBit(CallingConvention::c_rxxWritableRegistersMask, i))
{
auto s = Direct<void*>(reg);
m_reservedRxxRegisterStorages.push_back(s);
m_reservedRegistersPins.push_back(s.GetPin());
}
}
for (unsigned i = 0 ; i <= RegisterBase::c_maxFloatRegisterID; ++i)
{
Register<8, true> reg(i);
if (IsAnySharedBaseRegister(reg)
|| !BitOp::TestBit(CallingConvention::c_xmmWritableRegistersMask, i))
{
auto s = Direct<double>(reg);
m_reservedXmmRegisterStorages.push_back(s);
m_reservedRegistersPins.push_back(s.GetPin());
}
}
}
Allocators::IAllocator& ExpressionTree::GetAllocator() const
{
return m_allocator;
}
FunctionBuffer& ExpressionTree::GetCodeGenerator() const
{
return m_code;
}
void ExpressionTree::EnableDiagnostics(std::ostream& out)
{
m_diagnosticsStream = &out;
}
void ExpressionTree::DisableDiagnostics()
{
m_diagnosticsStream = nullptr;
}
bool ExpressionTree::IsDiagnosticsStreamAvailable() const
{
return m_diagnosticsStream != nullptr;
}
std::ostream& ExpressionTree::GetDiagnosticsStream() const
{
LogThrowAssert(m_diagnosticsStream != nullptr, "Diagnostics are disabled");
return *m_diagnosticsStream;
}
void ExpressionTree::ReleaseIfTemporary(int32_t offset)
{
unsigned slot;
if (TemporaryOffsetToSlot(offset, slot))
{
m_temporaries.push_back(slot);
}
}
unsigned ExpressionTree::GetRXXUsedMask() const
{
return m_rxxFreeList.GetUsedMask();
}
unsigned ExpressionTree::GetXMMUsedMask() const
{
return m_xmmFreeList.GetUsedMask();
}
bool ExpressionTree::IsBasePointer(PointerRegister r) const
{
return r.GetId() == m_basePointer.GetId();
}
PointerRegister ExpressionTree::GetBasePointer() const
{
return m_basePointer;
}
Label ExpressionTree::GetStartOfEpilogue() const
{
return m_startOfEpilogue;
}
unsigned ExpressionTree::AddNode(NodeBase& node)
{
m_topologicalSort.push_back(&node);
return static_cast<unsigned>(m_topologicalSort.size() - 1);
}
void ExpressionTree::AddParameter(NodeBase& parameter, unsigned position)
{
LogThrowAssert(position == m_parameters.size(),
"Parameters must be added in order. Previously added %u parameters, "
"adding parameter with index %u",
static_cast<unsigned>(m_parameters.size()),
position);
m_parameters.push_back(¶meter);
}
void ExpressionTree::AddRIPRelative(RIPRelativeImmediate& node)
{
m_ripRelatives.push_back(&node);
}
void ExpressionTree::AddExecutionPreconditionTest(ExecutionPreconditionTest& test)
{
m_preconditionTests.push_back(&test);
}
void ExpressionTree::ReportFunctionCallNode(unsigned parameterCount)
{
if (static_cast<int>(parameterCount) > m_maxFunctionCallParameters)
{
m_maxFunctionCallParameters = parameterCount;
}
}
void ExpressionTree::Compile()
{
// Note: the call to Reset() clears all allocated labels, so start of
// epilogue label must be allocated after that point.
m_code.Reset();
m_startOfEpilogue = m_code.AllocateLabel();
// Generate constants.
Pass0();
// Generate code.
m_code.BeginFunctionBodyGeneration();
Pass1();
Pass2();
Print();
Pass3();
const FunctionSpecification spec(m_allocator,
m_maxFunctionCallParameters,
m_temporaryCount,
m_rxxFreeList.GetLifetimeUsedMask()
& CallingConvention::c_rxxNonVolatileRegistersMask
& CallingConvention::c_rxxWritableRegistersMask,
m_xmmFreeList.GetLifetimeUsedMask()
& CallingConvention::c_xmmNonVolatileRegistersMask
& CallingConvention::c_xmmWritableRegistersMask,
FunctionSpecification::BaseRegisterType::SetRbpToOriginalRsp,
m_code.IsDiagnosticsStreamAvailable()
? &m_code.GetDiagnosticsStream()
: nullptr);
m_code.PlaceLabel(m_startOfEpilogue);
m_code.EndFunctionBodyGeneration(spec);
// Release the reserved registers.
m_reservedRegistersPins.clear();
m_reservedXmmRegisterStorages.clear();
m_reservedRxxRegisterStorages.clear();
Print();
LogThrowAssert(GetRXXUsedMask() == 0,
"Some integer registers have not been released: 0x%x",
GetRXXUsedMask());
LogThrowAssert(GetXMMUsedMask() == 0,
"Some floating point registers have not been released: 0x%x",
GetXMMUsedMask());
}
void const * ExpressionTree::GetUntypedEntryPoint() const
{
return m_code.GetEntryPoint();
}
int32_t ExpressionTree::TemporarySlotToOffset(unsigned temporarySlot)
{
LogThrowAssert(temporarySlot < m_temporaryCount,
"Invalid temporary slot %u (total slots %u)",
temporarySlot,
m_temporaryCount);
// Expression tree asks for BaseRegisterType::SetRbpToOriginalRsp. That
// means that [rbp] holds return address, [rbp + 8] home for function's
// first argument etc, whereas [rbp - 8] holds the first temporary etc.
return -static_cast<int32_t>(temporarySlot + 1)
* sizeof(void*);
}
bool ExpressionTree::TemporaryOffsetToSlot(int32_t temporaryOffset, unsigned& temporarySlot)
{
bool isTemporary = false;
if (temporaryOffset < 0
&& -temporaryOffset % sizeof(void*) == 0)
{
const unsigned slot = -temporaryOffset / sizeof(void*) - 1;
if (slot < m_temporaryCount)
{
temporarySlot = slot;
isTemporary = true;
}
}
return isTemporary;
}
void ExpressionTree::Pass0()
{
if (IsDiagnosticsStreamAvailable())
{
GetDiagnosticsStream() << "=== Pass0 ===" << std::endl;
}
// Emit RIP-relative constants.
for (unsigned i = 0 ; i < m_ripRelatives.size(); ++i)
{
m_ripRelatives[i]->EmitStaticData(*this);
}
// Walk the nodes in reverse order of creation (i.e. in potential order
// of execution) to see whether they can be optimized away.
//
// Note: currently it is not important whether the optimize-away pass
// traverses the nodes in order or in reverse order. This is because the
// only existing optimization technique (base pointer collapsing) is
// performed when node is constructed and removing references from
// children in such case will not create an opportunity for additional
// optimizations.
for (auto nodeIt = m_topologicalSort.rbegin();
nodeIt != m_topologicalSort.rend();
++nodeIt)
{
auto node = *nodeIt;
if (!node->IsReferenced())
{
Print();
LogThrowAssert(node->IsReferenced(),
"Node with ID %u has been created but not referenced by nodes in the tree",
node->GetId());
}
// If there's a way for node's children to be evaluated without
// evaluating this node first (f. ex. collapsing of pointers to the
// same base object), release the references that will be unused.
// Otherwise, the lifetime of the Storage returned by this node's
// CodeGenValue() will be too long.
if (node->CanBeOptimizedAway())
{
node->ReleaseReferencesToChildren();
}
}
}
void ExpressionTree::Pass1()
{
if (IsDiagnosticsStreamAvailable())
{
GetDiagnosticsStream() << "=== Pass1 ===" << std::endl;
}
// Reserve registers used to pass in parameters.
for (auto param : m_parameters)
{
if (param->GetParentCount() > 0)
{
param->CodeGenCache(*this);
}
}
// Execute any return-early tests before compiling the expression further.
for (auto test : m_preconditionTests)
{
test->Evaluate(*this);
}
}
void ExpressionTree::Pass2()
{
if (IsDiagnosticsStreamAvailable())
{
GetDiagnosticsStream() << "=== Pass2 ===" << std::endl;
}
for (unsigned i = 0 ; i < m_topologicalSort.size(); ++i)
{
NodeBase& node = *m_topologicalSort[i];
if (node.GetParentCount() > 1 && !node.HasBeenEvaluated())
{
node.CodeGenCache(*this);
}
}
}
void ExpressionTree::Pass3()
{
if (IsDiagnosticsStreamAvailable())
{
GetDiagnosticsStream() << "=== Pass3 ===" << std::endl;
}
NodeBase& root = *m_topologicalSort.back();
// LogThrowAssert(Root node is return, "Root must be a return node.");
root.CompileAsRoot(*this);
}
void ExpressionTree::Print() const
{
if (!IsDiagnosticsStreamAvailable())
{
return;
}
std::ostream& out = GetDiagnosticsStream();
out << "Parameters:" << std::endl;
for (unsigned i = 0 ; i < m_parameters.size(); ++i)
{
m_parameters[i]->Print(out);
out << std::endl;
}
out << std::endl;
out << "Topological sort:" << std::endl;
for (unsigned i = 0 ; i < m_topologicalSort.size(); ++i)
{
m_topologicalSort[i]->Print(out);
out << std::endl;
}
out << std::endl;
out << "RXX Registers:" << std::endl;
for (unsigned i = 0 ; i <= RegisterBase::c_maxIntegerRegisterID; ++i)
{
out << Register<8, false>(i).GetName()
<< (m_rxxFreeList.IsAvailable(i) ? " free" : " in use")
<< std::endl;
}
out << std::endl;
out << "XMM Registers:" << std::endl;
for (unsigned i = 0 ; i <= RegisterBase::c_maxFloatRegisterID; ++i)
{
out << Register<8, true>(i).GetName()
<< (m_xmmFreeList.IsAvailable(i) ? " free" : " in use")
<< std::endl;
}
out << "Temporaries used: " << m_temporaryCount << std::endl;
out << "Temporaries still in use: " << m_temporaryCount - m_temporaries.size() << std::endl;
out << std::endl;
}
//*************************************************************************
//
// ExpressionTree::Data
//
//*************************************************************************
ExpressionTree::Data::Data(ExpressionTree& tree,
PointerRegister base,
int32_t offset)
: m_tree(tree),
m_storageClass(StorageClass::Indirect),
m_isFloat(base.c_isFloat),
m_registerId(base.GetId()),
m_offset(offset),
m_refCount(0)
{
NotifyDataRegisterChange(RegisterChangeType::Initialize);
}
ExpressionTree& ExpressionTree::Data::GetTree() const
{
return m_tree;
}
StorageClass ExpressionTree::Data::GetStorageClass() const
{
return m_storageClass;
}
unsigned ExpressionTree::Data::GetRegisterId() const
{
return m_registerId;
}
int32_t ExpressionTree::Data::GetOffset() const
{
LogThrowAssert(m_storageClass == StorageClass::Indirect, "StorageClass must be Indirect, found %u", m_storageClass);
return m_offset;
}
void ExpressionTree::Data::ConvertDirectToIndirect(int32_t offset)
{
LogThrowAssert(m_storageClass == StorageClass::Direct,
"StorageClass must be Direct, found %u",
m_storageClass);
LogThrowAssert(!IsSharedBaseRegister(),
"Cannot change type of shared register %u from direct to indirect",
m_registerId);
m_storageClass = StorageClass::Indirect;
m_offset = offset;
}
void ExpressionTree::Data::ConvertIndirectToDirect()
{
LogThrowAssert(m_storageClass == StorageClass::Indirect,
"StorageClass must be Indirect, found %u",
m_storageClass);
LogThrowAssert(!IsSharedBaseRegister(),
"Cannot change type of shared register %u from indirect to direct",
m_registerId);
m_storageClass = StorageClass::Direct;
m_offset = 0;
}
unsigned ExpressionTree::Data::GetRefCount() const
{
return m_refCount;
}
unsigned ExpressionTree::Data::Decrement()
{
LogThrowAssert(m_refCount > 0, "Attempting to decrement zero ref count.");
--m_refCount;
return m_refCount;
}
void ExpressionTree::Data::Increment()
{
++m_refCount;
}
void ExpressionTree::Data::SwapContents(Data* other)
{
std::swap(m_storageClass, other->m_storageClass);
std::swap(m_isFloat, other->m_isFloat);
std::swap(m_registerId, other->m_registerId);
std::swap(m_offset, other->m_offset);
std::swap(m_immediate, other->m_immediate);
// Both Data objects keep their m_refCount.
NotifyDataRegisterChange(RegisterChangeType::Update);
other->NotifyDataRegisterChange(RegisterChangeType::Update);
}
void ExpressionTree::Data::NotifyDataRegisterChange(RegisterChangeType type)
{
if (m_storageClass != StorageClass::Immediate)
{
if (m_isFloat)
{
NotifyDataRegisterChange<true>(type);
}
else
{
NotifyDataRegisterChange<false>(type);
}
}
}
bool ExpressionTree::Data::IsSharedBaseRegister() const
{
return m_storageClass != StorageClass::Immediate
&& !m_isFloat
&& m_tree.IsAnySharedBaseRegister(PointerRegister(m_registerId));
}
ReferenceCounter::ReferenceCounter()
: m_counter(nullptr)
{
// No-op, for symmetry only.
AddReference();
}
ReferenceCounter::ReferenceCounter(unsigned& counter)
: m_counter(&counter)
{
AddReference();
}
ReferenceCounter::ReferenceCounter(ReferenceCounter const & other)
: ReferenceCounter(*other.m_counter)
{
}
ReferenceCounter::~ReferenceCounter()
{
RemoveReference();
}
ReferenceCounter& ReferenceCounter::operator=(ReferenceCounter const & other)
{
if (m_counter != other.m_counter)
{
RemoveReference();
m_counter = other.m_counter;
AddReference();
}
return *this;
}
void ReferenceCounter::Reset()
{
RemoveReference();
m_counter = nullptr;
}
void ReferenceCounter::AddReference()
{
if (m_counter != nullptr)
{
++(*m_counter);
}
}
void ReferenceCounter::RemoveReference()
{
if (m_counter != nullptr)
{
if (*m_counter == 0)
{
throw std::logic_error("Tried to remove a reference with zero reference count");
}
--(*m_counter);
}
}
}
``` | /content/code_sandbox/src/NativeJIT/ExpressionTree.cpp | c++ | 2016-04-09T23:53:19 | 2024-06-29T07:05:56 | NativeJIT | BitFunnel/NativeJIT | 1,133 | 4,104 |
```c++
// Permission is hereby granted, free of charge, to any person obtaining a copy
// of this software and associated documentation files (the "Software"), to deal
// in the Software without restriction, including without limitation the rights
// to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
// copies of the Software, and to permit persons to whom the Software is
// furnished to do so, subject to the following conditions:
// The above copyright notice and this permission notice shall be included in
// all copies or substantial portions of the Software.
// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
// AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
// LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
// OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
// THE SOFTWARE.
#include <algorithm> // For std::max
#include "NativeJIT/ExpressionTree.h"
#include "NativeJIT/Nodes/Node.h"
namespace NativeJIT
{
//*************************************************************************
//
// NodeBase
//
//*************************************************************************
NodeBase::NodeBase(ExpressionTree& tree)
: m_id(tree.AddNode(*this)),
m_parentCount(0),
m_isReferenced(false),
m_hasBeenEvaluated(false)
{
}
unsigned NodeBase::GetId() const
{
return m_id;
}
void NodeBase::IncrementParentCount()
{
LogThrowAssert(!HasBeenEvaluated(), "Cannot change the parent count after the node was evaluated");
++m_parentCount;
MarkReferenced();
}
void NodeBase::DecrementParentCount()
{
LogThrowAssert(!HasBeenEvaluated(), "Cannot change the parent count after the node was evaluated");
LogThrowAssert(m_parentCount > 0,
"Cannot decrement parent count of node %u with zero parents",
GetId());
--m_parentCount;
// Note: m_isReferenced is not affected by this, decrementing the parent
// count is optimization-related call which doesn't change the
// fact that a node is referenced at least conceptually. This is because
// currently having a non-referenced node is considered to be an error,
// and not a chance for removing such nodes.
}
bool NodeBase::HasBeenEvaluated() const
{
return m_hasBeenEvaluated;
}
void NodeBase::MarkEvaluated()
{
m_hasBeenEvaluated = true;
}
bool NodeBase::IsReferenced() const
{
return m_isReferenced;
}
void NodeBase::MarkReferenced()
{
m_isReferenced = true;
}
unsigned NodeBase::GetParentCount() const
{
return m_parentCount;
}
void NodeBase::CompileAsRoot(ExpressionTree& /*tree*/)
{
LogThrowAbort("Root of ExpressionTree must be a ReturnNode node.");
}
bool NodeBase::CanBeOptimizedAway() const
{
return GetParentCount() == 0;
}
void NodeBase::ReleaseReferencesToChildren()
{
LogThrowAbort("Don't know how to remove optimized away references for node with ID %u (orphan node?)",
GetId());
}
bool NodeBase::GetBaseAndOffset(NodeBase*& /* base */, int32_t& /* offset */) const
{
return false;
}
}
``` | /content/code_sandbox/src/NativeJIT/Node.cpp | c++ | 2016-04-09T23:53:19 | 2024-06-29T07:05:56 | NativeJIT | BitFunnel/NativeJIT | 1,133 | 778 |
```c++
// Permission is hereby granted, free of charge, to any person obtaining a copy
// of this software and associated documentation files (the "Software"), to deal
// in the Software without restriction, including without limitation the rights
// to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
// copies of the Software, and to permit persons to whom the Software is
// furnished to do so, subject to the following conditions:
// The above copyright notice and this permission notice shall be included in
// all copies or substantial portions of the Software.
// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
// AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
// LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
// OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
// THE SOFTWARE.
#include "NativeJIT/ExpressionNodeFactory.h"
namespace NativeJIT
{
ExpressionNodeFactory::ExpressionNodeFactory(Allocators::IAllocator& allocator,
FunctionBuffer& code)
: ExpressionTree(allocator, code)
{
}
}
``` | /content/code_sandbox/src/NativeJIT/ExpressionNodeFactory.cpp | c++ | 2016-04-09T23:53:19 | 2024-06-29T07:05:56 | NativeJIT | BitFunnel/NativeJIT | 1,133 | 273 |
```c++
#include "NativeJIT/CodeGen/ExecutionBuffer.h"
#include "NativeJIT/CodeGen/FunctionBuffer.h"
#include "NativeJIT/Function.h"
using NativeJIT::Allocator;
using NativeJIT::ExecutionBuffer;
using NativeJIT::Function;
using NativeJIT::FunctionBuffer;
///////////////////////////////////////////////////////////////////////////////
//
// This example JITs a function that computes the area of a circle, given
// its radius.
//
// Here is a disassembly of the generated code.
//
//
// PI_CONSTANT:
// db 0f 49 40 ; PI constant is stored in memory.
// ENTRY_POINT:
// sub rsp, 28h ; Standard function prolog
// mov qword ptr[rsp], rbp
// movaps xmmword ptr[rsp + 10h], xmm15
// lea rbp, [rsp + 28h]
//
// movss xmm15, xmm0 ; Load radius from first parameter register.
// mulss xmm15, xmm0 ; Multiply by radius.
// mulss xmm15, dword ptr[PI_CONSTANT] ; Multiply by PI.
// movss xmm0, xmm15 ; Return value goes in xmm0.
//
// movaps xmm15, xmmword ptr[rsp + 10h] ; Standard function epilog.
// mov rbp, qword ptr[rsp]
// add rsp, 28h
// ret
//
// TODO: There seems to be a bug in the regster allocator. The generated
// code never should have used xmm15. It should have been
// mulss xmm0, xmm0
// mulss xmm0, dword ptr[PI_CONSTANT]
//
///////////////////////////////////////////////////////////////////////////////
int main()
{
// Create allocator and buffers for pre-compiled and post-compiled code.
ExecutionBuffer codeAllocator(8192);
Allocator allocator(8192);
FunctionBuffer code(codeAllocator, 8192);
// Create the factory for expression nodes.
// Our area expression will take a single float parameter and return a float.
Function<float, float> expression(allocator, code);
// Multiply input parameter by itself to get radius squared.
auto & rsquared = expression.Mul(expression.GetP1(), expression.GetP1());
// Multiply by PI.
const float PI = 3.14159265358979f;
auto & area = expression.Mul(rsquared, expression.Immediate(PI));
// Compile expression into a function.
auto function = expression.Compile(area);
// Now run our expression!
float radius = 2.0;
std::cout << "The area of a circle with radius " << radius
<< " is " << function(radius) << "." << std::endl;
return 0;
}
``` | /content/code_sandbox/Examples/AreaOfCircle/AreaOfCircle.cpp | c++ | 2016-04-09T23:53:19 | 2024-06-29T07:05:56 | NativeJIT | BitFunnel/NativeJIT | 1,133 | 599 |
```c++
#include <iostream>
#include <math.h> // For value of e.
#include <sstream>
#include "NativeJIT/CodeGen/ExecutionBuffer.h"
#include "NativeJIT/CodeGen/FunctionBuffer.h"
#include "NativeJIT/Function.h"
using NativeJIT::Allocator;
using NativeJIT::ExecutionBuffer;
using NativeJIT::Function;
using NativeJIT::FunctionBuffer;
namespace Examples
{
class Parser
{
public:
//
// Constructs a parser for the expression text in src.
// Allocator and FunctionBuffer are constructor parameters
// for NativeJIT::Function.
//
Parser(std::string const & src,
Allocator& allocator,
FunctionBuffer& code);
//
// Compiles the expression, then invokes the resulting
// function.
//
float Evaluate();
//
// ParseError records the character position and cause of an error
// during parsing.
//
class ParseError : public std::runtime_error
{
public:
ParseError(char const * message, size_t position);
friend std::ostream& operator<< (std::ostream &out, const ParseError &e);
private:
// Character position where error occurred.
size_t m_position;
};
private:
// Parses an expression of the form
// EXPRESSION:
// SUM
NativeJIT::Node<float>& Parse();
// Parses expressions of form
// SUM:
// PRODUCT ('+' PRODUCT)*
// PRODUCT ('-' PRODUCT)*
NativeJIT::Node<float>& ParseSum();
// Parses expressions of the form
// PRODUCT:
// TERM ('*' TERM)*
NativeJIT::Node<float>& ParseProduct();
// Parses expressions of the form
// TERM:
// (SUM)
// FLOAT
// SYMBOL
NativeJIT::Node<float>& ParseTerm();
// Parses expressions of the form
// FLOAT:
// [ '+' | '-' ] (DIGIT)* [ '.' DIGIT*] [ ('e' | 'E') [ '+' | '-' ] DIGIT* ]
float ParseFloat();
// Parses expressions of the form
// SYMBOL: ALPHA (ALPHA | DIGIT)*
std::string ParseSymbol();
// Returns true if current position is the first character of a floating
// point number.
bool IsFirstCharOfFloat(char c);
// Advances the current position past whitespace (space, tab, carriage
// return, newline).
void SkipWhite();
// Attempts to advance past next character.
// Throws a ParseError if the next character is not equal to
// the expected character.
void Consume(char expected);
// Advances past the next character.
// Returns the character or '\0' if at the end of the stream.
char GetChar();
// Returns the next character without advancing.
// Returns '\0' if at the end of the stream.
char PeekChar();
// Source string to be parsed.
std::string const m_src;
// Current position of parser in the m_src.
size_t m_currentPosition;
// NativeJIT Function used to build and compile parsed expression.
Function<float> m_expression;
};
Parser::Parser(std::string const & src,
Allocator& allocator,
FunctionBuffer& code)
: m_src(src),
m_currentPosition(0),
m_expression(allocator, code)
{
}
float Parser::Evaluate()
{
auto& root = Parse();
m_expression.Compile(root);
auto function = m_expression.GetEntryPoint();
return function();
}
NativeJIT::Node<float>& Parser::Parse()
{
auto& expression = ParseSum();
SkipWhite();
if (PeekChar() != '\0')
{
throw ParseError("Syntax error.", m_currentPosition);
}
return expression;
}
NativeJIT::Node<float>& Parser::ParseSum()
{
auto* left = &ParseProduct();
while (true)
{
SkipWhite();
char c = PeekChar();
if (c == '+')
{
GetChar();
auto& right = ParseProduct();
left = &m_expression.Add(*left, right);
}
else if (c == '-')
{
GetChar();
auto& right = ParseProduct();
left = &m_expression.Sub(*left, right);
}
else
{
break;
}
}
return *left;
}
NativeJIT::Node<float>& Parser::ParseProduct()
{
auto* left = &ParseTerm();
while (true)
{
SkipWhite();
if (PeekChar() == '*')
{
GetChar();
auto& right = ParseProduct();
return m_expression.Mul(*left, right);
}
else
{
return *left;
}
}
}
NativeJIT::Node<float>& Parser::ParseTerm()
{
SkipWhite();
char next = PeekChar();
if (next == '(')
{
GetChar();
auto& result = ParseSum();
SkipWhite();
Consume(')');
return result;
}
else if (IsFirstCharOfFloat(next))
{
float f = ParseFloat();
return m_expression.Immediate(f);
}
else if (isalpha(next))
{
std::string symbol = ParseSymbol();
if (symbol.compare("e") == 0)
{
// 'e' denotes Euler's number.
const float e = static_cast<float>(exp(1));
return m_expression.Immediate(e);
}
else if (symbol.compare("pi") == 0)
{
// 'pi' denotes the mathematical constant pi.
const float pi = static_cast<float>(atan(1) * 4);
return m_expression.Immediate(pi);
}
else if (symbol.compare("sqrt") == 0)
{
SkipWhite();
Consume('(');
auto& parameter = ParseSum();
SkipWhite();
Consume(')');
auto & sqrtFunction = m_expression.Immediate(sqrtf);
return m_expression.Call(sqrtFunction, parameter);
}
else
{
// TODO: REVIEW: Check lifetime of c_str() passed to exception constructor.
std::stringstream message;
message << "Unknown identifier \"" << symbol << "\".";
throw ParseError(message.str().c_str(), m_currentPosition);
}
}
else
{
throw ParseError("Expected a number, symbol or parenthesized expression.",
m_currentPosition);
}
}
float Parser::ParseFloat()
{
// s will hold a string of floating point number characters that will
// eventually be passed to stof().
std::string s;
SkipWhite();
//
// Gather in s the longest possible sequence of characters that will
// parse as a floating point number.
//
// Optional leading '+' or '-'.
if (PeekChar() == '+' || PeekChar() == '-')
{
s.push_back(GetChar());
}
// Optional mantissa left of '.'
while (isdigit(PeekChar()))
{
s.push_back(GetChar());
}
// Optional portion of mantissa right of '.'.
if (PeekChar() == '.')
{
s.push_back(GetChar());
while (isdigit(PeekChar()))
{
s.push_back(GetChar());
}
}
// Optional exponent.
if (PeekChar() == 'e' || PeekChar() == 'E')
{
s.push_back(GetChar());
// Optional '+' or '-' before exponent.
if (PeekChar() == '+' || PeekChar() == '-')
{
s.push_back(GetChar());
}
if (!isdigit(PeekChar()))
{
throw ParseError("Expected exponent in floating point constant.",
m_currentPosition);
}
while (isdigit(PeekChar()))
{
s.push_back(GetChar());
}
}
// Parse s into a floating point value.
// TODO: could check for really obvious errors before the try.
try
{
return stof(s);
}
catch (...)
{
throw ParseError("Invalid float.",
m_currentPosition);
}
}
std::string Parser::ParseSymbol()
{
std::string symbol;
SkipWhite();
if (!isalpha(PeekChar()))
{
throw ParseError("Expected alpha character at beginning of symbol.",
m_currentPosition);
}
while (isalnum(PeekChar()))
{
symbol.push_back(GetChar());
}
return symbol;
}
bool Parser::IsFirstCharOfFloat(char c)
{
return isdigit(c) || (c == '-') || (c == '+') || (c == '.');
}
void Parser::SkipWhite()
{
while (isspace(PeekChar()))
{
GetChar();
}
}
void Parser::Consume(char c)
{
if (PeekChar() != c)
{
// TODO: REVIEW: Check lifetime of c_str() passed to exception constructor.
std::stringstream message;
message << "Expected '" << c << "'.";
throw ParseError(message.str().c_str(), m_currentPosition);
}
else
{
GetChar();
}
}
char Parser::GetChar()
{
char result = PeekChar();
if (result != '\0')
{
++m_currentPosition;
}
return result;
}
char Parser::PeekChar()
{
if (m_currentPosition >= m_src.length())
{
return '\0';
}
else
{
return m_src[m_currentPosition];
}
}
Parser::ParseError::ParseError(char const * message, size_t position)
: std::runtime_error(message),
m_position(position)
{
}
std::ostream& operator<< (std::ostream &out, const Parser::ParseError &e)
{
out << std::string(e.m_position, ' ') << '^' << std::endl;
out << "Parser error (position = " << e.m_position << "): ";
out << e.what();
out << std::endl;
return out;
}
}
/******************************************************************************
*
* Test() runs a number of test cases for the parser.
* It prints a summary of each case's input and output and either "OK"
* or "FAILED" depending on whether the test succeeded or failed.
*
* Returns true if all tests pass. Otherwise returns false.
*
******************************************************************************/
bool Test()
{
class TestCase
{
public:
// TODO: REVIEW: Passing double here instead of float so that I don't
// have to type the 'f' character at the end of every floating point
// constant. Consider just changing entire example to use doubles.
TestCase(char const * input, double output)
: m_input(input),
m_output(static_cast<float>(output))
{
}
bool Run(std::ostream& output, Allocator& allocator, FunctionBuffer& code)
{
bool succeeded = false;
output << "\"" << m_input << "\" ==> ";
try {
Examples::Parser parser(m_input, allocator, code);
float result = parser.Evaluate();
output << result;
if (result == m_output)
{
succeeded = true;
output << " OK";
}
else
{
output << " FAILED: expected " << m_output;
}
} catch (...) {
output << "FAILED: exception.";
}
output << std::endl;
return succeeded;
}
private:
char const * m_input;
float m_output;
};
TestCase cases[] =
{
// Constants
TestCase("1", 1.0),
TestCase("1.234", 1.234),
TestCase(".1", 0.1),
TestCase("-2", -2.0),
TestCase("-.1", -0.1),
TestCase("1e9", 1e9),
TestCase("2e-8", 2e-8),
TestCase("3e+7", 3e+7),
TestCase("456.789e+5", 456.789e+5),
// Symbols
TestCase("e", static_cast<float>(exp(1))),
TestCase("pi", static_cast<float>(atan(1) * 4)),
// Addition
TestCase("1+2", 3.0),
TestCase("3+e", 3.0 + static_cast<float>(exp(1))),
// Subtraction
TestCase("4-5", -1.0),
// Multiplication
TestCase("2*3", 6.0),
// Parenthesized expressions
TestCase("(3+4)", 7.0),
TestCase("(3+4)*(2+3)", 35.0),
// Combinations
TestCase("1+-2", -1.0), // Addition combined with unary negation.
// White space
TestCase("\t 1 + ( 2 * 10 ) ", 21.0),
// sqrt
TestCase("sqrt(4)", 2.0),
TestCase("sqrt((3+4)*(2+3))", sqrtf(35)),
// More complex expressions
TestCase("2*2+1", 5.0f),
TestCase("1+1+1", 3.0f),
TestCase("1 * 2 * 3", 6.0f),
// Left associativity
TestCase("1-1-1", -1.0f),
TestCase("1-2-3-4", -8.0f),
};
ExecutionBuffer codeAllocator(8192);
Allocator allocator(8192);
FunctionBuffer code(codeAllocator, 8192);
bool success = true;
for (size_t i = 0; i < sizeof(cases) / sizeof(TestCase); ++i)
{
allocator.Reset();
codeAllocator.Reset();
success &= cases[i].Run(std::cout, allocator, code);
}
return success;
}
int main()
{
std::cout << "Running test cases ..." << std::endl;
bool success = Test();
if (success)
{
std::cout << "All tests succeeded." << std::endl;
}
else
{
std::cout << "One or more tests failed." << std::endl;
}
std::cout << std::endl;
std::cout << "Type an expression and press return to evaluate." << std::endl;
std::cout << "Enter an empty line to exit." << std::endl;
ExecutionBuffer codeAllocator(8192);
Allocator allocator(8192);
FunctionBuffer code(codeAllocator, 8192);
std::string prompt(">> ");
for (;;)
{
allocator.Reset();
codeAllocator.Reset();
std::string line;
std::cout << prompt << std::flush;
std::getline(std::cin, line);
// TODO: Should really see if line is completely blank.
// Blank lines cause the parser to crash.
if (line.length() == 0)
{
break;
}
try
{
Examples::Parser parser(line, allocator, code);
float result = parser.Evaluate();
std::cout << result << std::endl;
}
catch (Examples::Parser::ParseError& e)
{
std::cout << std::string(prompt.length(), ' ');
std::cout << e;
}
}
return 0;
}
``` | /content/code_sandbox/Examples/Parser/Parser.cpp | c++ | 2016-04-09T23:53:19 | 2024-06-29T07:05:56 | NativeJIT | BitFunnel/NativeJIT | 1,133 | 3,378 |
```objective-c
// Permission is hereby granted, free of charge, to any person obtaining a copy
// of this software and associated documentation files (the "Software"), to deal
// in the Software without restriction, including without limitation the rights
// to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
// copies of the Software, and to permit persons to whom the Software is
// furnished to do so, subject to the following conditions:
// The above copyright notice and this permission notice shall be included in
// all copies or substantial portions of the Software.
// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
// AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
// LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
// OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
// THE SOFTWARE.
#pragma once
#include <memory>
#include "IAllocator.h"
#include "Temporary/NonCopyable.h"
namespace NativeJIT
{
// TODO: This should be a private header.
class Allocator : public Allocators::IAllocator
{
public:
Allocator(size_t bufferSize);
virtual ~Allocator() override;
// Allocates a block of a specified byte size.
virtual void* Allocate(size_t size) override;
// Frees a block.
virtual void Deallocate(void* block) override;
// Returns the maximum legal allocation size in bytes.
virtual size_t MaxSize() const override;
// Frees all blocks that have been allocated since construction or the
// last call to Reset().
virtual void Reset() override;
private:
void DebugInitialize();
size_t m_bufferSize;
size_t m_bytesAllocated;
std::unique_ptr<char[]> m_buffer;
};
}
``` | /content/code_sandbox/inc/Temporary/Allocator.h | objective-c | 2016-04-09T23:53:19 | 2024-06-29T07:05:56 | NativeJIT | BitFunnel/NativeJIT | 1,133 | 414 |
```objective-c
// Permission is hereby granted, free of charge, to any person obtaining a copy
// of this software and associated documentation files (the "Software"), to deal
// in the Software without restriction, including without limitation the rights
// to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
// copies of the Software, and to permit persons to whom the Software is
// furnished to do so, subject to the following conditions:
// The above copyright notice and this permission notice shall be included in
// all copies or substantial portions of the Software.
// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
// AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
// LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
// OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
// THE SOFTWARE.
#pragma once
#include "IAllocator.h"
namespace Allocators
{
// Allocates memory from the allocator to store an object of type T and
// performs in-place construction of T.
template <typename T, typename... ConstructorArgs>
T&
PlacementConstruct(IAllocator& allocator, ConstructorArgs&&... constructorArgs)
{
// Obtain the memory needed to store the object itself.
// Note: Assumes that IAllocator's Allocate() method returns memory
// aligned to satisfy all object types.
void* memory = allocator.Allocate(sizeof(T));
try
{
// In-place construct the object, perfectly forwarding the
// constructor arguments.
new (memory) T(std::forward<ConstructorArgs>(constructorArgs)...);
}
catch(...)
{
allocator.Deallocate(memory);
throw;
}
return *reinterpret_cast<T*>(memory);
}
}
``` | /content/code_sandbox/inc/Temporary/AllocatorOperations.h | objective-c | 2016-04-09T23:53:19 | 2024-06-29T07:05:56 | NativeJIT | BitFunnel/NativeJIT | 1,133 | 406 |
```objective-c
// Permission is hereby granted, free of charge, to any person obtaining a copy
// of this software and associated documentation files (the "Software"), to deal
// in the Software without restriction, including without limitation the rights
// to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
// copies of the Software, and to permit persons to whom the Software is
// furnished to do so, subject to the following conditions:
// The above copyright notice and this permission notice shall be included in
// all copies or substantial portions of the Software.
// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
// AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
// LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
// OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
// THE SOFTWARE.
#pragma once
#include <cstddef> // For ptrdiff_t and size_t.
#include "IAllocator.h"
namespace Allocators
{
//*************************************************************************
//
// StlAllocator is a is a wrapper class for IAllocator. It is used to
// create an allocator that is compatible with the STL container classes
// like map and vector.
//
// This template declaration is a subset of the declaration in the C++98
// spec (ISO/IEC 14882:1998), section 20.4.1.
// See specification draft: path_to_url
// Also see path_to_url
//
//*************************************************************************
template <typename T> class StlAllocator {
public:
typedef size_t size_type;
typedef ptrdiff_t difference_type;
typedef T* pointer;
typedef const T* const_pointer;
typedef T& reference;
typedef const T& const_reference;
typedef T value_type;
template <typename U> struct rebind
{
typedef StlAllocator<U> other;
};
StlAllocator(IAllocator& allocator);
// The following two methods are in the C++98 specification but were
// not implemented. Keeping the declarations here to document
// differences from the specification and to help with debugging.
//StlAllocator() throw();
//StlAllocator(const StlAllocator&) throw();
template <typename U> StlAllocator(const StlAllocator<U>&) throw();
// The following method is in the C++98 specification but was
// not implemented. Keeping the declarations here to document
// differences from the specification and to help with debugging.
//~StlAllocator() throw();
pointer address(reference x) const;
const_pointer address(const_reference x) const;
pointer allocate(size_type count, const void* hint = 0);
void deallocate(pointer p, size_type n);
size_type max_size() const throw();
void construct(pointer p, const_reference val);
void destroy(pointer p);
bool operator==(const StlAllocator&);
bool operator!=(const StlAllocator&);
private:
template <typename S>
friend class StlAllocator;
// StlAllocator does not implement an assignment operator because
// it stores a reference to its IAllocator.
StlAllocator& operator=(const StlAllocator&);
IAllocator& m_allocator;
};
template <typename T>
StlAllocator<T>::StlAllocator(IAllocator& allocator)
: m_allocator(allocator)
{
}
template <typename T>
template <typename U>
StlAllocator<T>::StlAllocator(const StlAllocator<U>& rhs) throw()
: m_allocator(rhs.m_allocator)
{
}
template <typename T>
typename StlAllocator<T>::pointer StlAllocator<T>::address(typename StlAllocator<T>::reference x) const
{
return &x;
}
template <typename T>
typename StlAllocator<T>::const_pointer StlAllocator<T>::address(typename StlAllocator<T>::const_reference x) const
{
return &x;
}
template <typename T>
typename StlAllocator<T>::pointer StlAllocator<T>::allocate(typename StlAllocator<T>::size_type count, const void* /*hint*/)
{
return static_cast<StlAllocator<T>::pointer>(m_allocator.Allocate(sizeof(T) * count));
}
template <typename T>
void StlAllocator<T>::deallocate(typename StlAllocator<T>::pointer p, typename StlAllocator<T>::size_type /*count*/)
{
m_allocator.Deallocate(p);
}
template <typename T>
typename StlAllocator<T>::size_type StlAllocator<T>::max_size() const throw()
{
return m_allocator.MaxSize();
}
template <typename T>
void StlAllocator<T>::construct(typename StlAllocator<T>::pointer ptr, typename StlAllocator<T>::const_reference val)
{
new (ptr) T(val);
}
#ifdef _MSC_VER
#pragma warning(push)
#pragma warning(disable:4100)
#endif
// Warning C4100 says that 'ptr' is unreferenced as a formal parameter.
// This happens when T is a simple type like int. In this case it seems that
// the compiler optimizes away the call to ptr->~T(), causing the ptr to
// seem unreferenced. This seems like a compiler bug.
template <typename T>
void StlAllocator<T>::destroy(typename StlAllocator<T>::pointer ptr)
{
ptr->~T();
}
#ifdef _MSC_VER
#pragma warning(pop)
#endif
template <typename T>
bool StlAllocator<T>::operator==(const StlAllocator&)
{
return true;
}
template <typename T>
bool StlAllocator<T>::operator!=(const StlAllocator&)
{
return false;
}
}
``` | /content/code_sandbox/inc/Temporary/StlAllocator.h | objective-c | 2016-04-09T23:53:19 | 2024-06-29T07:05:56 | NativeJIT | BitFunnel/NativeJIT | 1,133 | 1,281 |
```objective-c
// Permission is hereby granted, free of charge, to any person obtaining a copy
// of this software and associated documentation files (the "Software"), to deal
// in the Software without restriction, including without limitation the rights
// to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
// copies of the Software, and to permit persons to whom the Software is
// furnished to do so, subject to the following conditions:
// The above copyright notice and this permission notice shall be included in
// all copies or substantial portions of the Software.
// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
// AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
// LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
// OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
// THE SOFTWARE.
#pragma once
namespace Allocators
{
//*************************************************************************
//
// IAllocator is an abstract base class or interface for classes that are
// memory allocators. Classes that implement IAllocator may use any
// allocation strategy and may choose whether or not to be threadsafe.
//
//*************************************************************************
class IAllocator
{
public:
virtual ~IAllocator() {}
// Allocates a block of a specified byte size.
virtual void* Allocate(size_t size) = 0;
// Frees a block.
virtual void Deallocate(void* block) = 0;
// Returns the maximum legal allocation size in bytes.
virtual size_t MaxSize() const = 0;
// Frees all blocks that have been allocated since construction or the
// last call to Reset().
virtual void Reset() = 0;
};
}
``` | /content/code_sandbox/inc/Temporary/IAllocator.h | objective-c | 2016-04-09T23:53:19 | 2024-06-29T07:05:56 | NativeJIT | BitFunnel/NativeJIT | 1,133 | 404 |
```objective-c
// Permission is hereby granted, free of charge, to any person obtaining a copy
// of this software and associated documentation files (the "Software"), to deal
// in the Software without restriction, including without limitation the rights
// to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
// copies of the Software, and to permit persons to whom the Software is
// furnished to do so, subject to the following conditions:
// The above copyright notice and this permission notice shall be included in
// all copies or substantial portions of the Software.
// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
// AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
// LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
// OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
// THE SOFTWARE.
#pragma once
namespace NativeJIT
{
// A temporary local implementation of boost::NonCopyable
class NonCopyable
{
protected:
NonCopyable() {}
~NonCopyable() {}
private: // emphasize the following members are private
NonCopyable(const NonCopyable&);
const NonCopyable& operator=(const NonCopyable&);
};
}
``` | /content/code_sandbox/inc/Temporary/NonCopyable.h | objective-c | 2016-04-09T23:53:19 | 2024-06-29T07:05:56 | NativeJIT | BitFunnel/NativeJIT | 1,133 | 302 |
```objective-c
// Permission is hereby granted, free of charge, to any person obtaining a copy
// of this software and associated documentation files (the "Software"), to deal
// in the Software without restriction, including without limitation the rights
// to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
// copies of the Software, and to permit persons to whom the Software is
// furnished to do so, subject to the following conditions:
// The above copyright notice and this permission notice shall be included in
// all copies or substantial portions of the Software.
// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
// AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
// LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
// OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
// THE SOFTWARE.
#pragma once
// MSVC has __pragma directive for use in macros since #pragma would apply to the macro itself.
#ifdef _MSC_VER
#define PREPROCESSOR_PRAGMA_WARNING(x) __pragma(warning(x))
#else
#define PREPROCESSOR_PRAGMA_WARNING(x)
#endif
#define LogThrowAssert(condition, ...) \
do \
{ \
if (!(condition)) \
{ \
NativeJIT::LogThrowImpl(__FILE__, \
__FUNCTION__, \
__LINE__, \
#condition, \
__VA_ARGS__); \
} \
PREPROCESSOR_PRAGMA_WARNING(push) \
PREPROCESSOR_PRAGMA_WARNING(disable:4127) \
} while (false) \
PREPROCESSOR_PRAGMA_WARNING(pop)
#define LogThrowAbort(...) \
NativeJIT::LogThrowImpl(__FILE__, \
__FUNCTION__, \
__LINE__, \
"Forced failure", \
__VA_ARGS__)
namespace NativeJIT
{
void LogThrowImpl(char const * filename,
char const * function,
unsigned lineNumber,
char const * title,
char const * format,
...);
}
``` | /content/code_sandbox/inc/Temporary/Assert.h | objective-c | 2016-04-09T23:53:19 | 2024-06-29T07:05:56 | NativeJIT | BitFunnel/NativeJIT | 1,133 | 467 |
```objective-c
// Permission is hereby granted, free of charge, to any person obtaining a copy
// of this software and associated documentation files (the "Software"), to deal
// in the Software without restriction, including without limitation the rights
// to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
// copies of the Software, and to permit persons to whom the Software is
// furnished to do so, subject to the following conditions:
// The above copyright notice and this permission notice shall be included in
// all copies or substantial portions of the Software.
// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
// AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
// LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
// OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
// THE SOFTWARE.
#pragma once
//
// Declaration includes - these includes must come before implementation includes.
//
#include "NativeJIT/ExpressionNodeFactoryDecls.h"
//
// Implementation includes
//
#include <cstdint>
#include "NativeJIT/BitOperations.h"
#include "NativeJIT/Nodes/BinaryImmediateNode.h"
#include "NativeJIT/Nodes/BinaryNode.h"
#include "NativeJIT/Nodes/CallNode.h"
#include "NativeJIT/Nodes/CastNode.h"
#include "NativeJIT/Nodes/ConditionalNode.h"
#include "NativeJIT/Nodes/DependentNode.h"
#include "NativeJIT/Nodes/FieldPointerNode.h"
#include "NativeJIT/Nodes/ImmediateNode.h"
#include "NativeJIT/Nodes/IndirectNode.h"
#include "NativeJIT/Nodes/Node.h"
#include "NativeJIT/Nodes/PackedMinMaxNode.h"
#include "NativeJIT/Nodes/ParameterNode.h"
#include "NativeJIT/Nodes/ReturnNode.h"
#include "NativeJIT/Nodes/ShldNode.h"
#include "NativeJIT/Nodes/StackVariableNode.h"
#include "Temporary/Allocator.h"
namespace NativeJIT
{
//*************************************************************************
//
// Template definitions for ExpressionNodeFactory.
//
//*************************************************************************
//
// Leaf nodes
//
template <typename T>
ImmediateNode<T>& ExpressionNodeFactory::Immediate(T value)
{
return PlacementConstruct<ImmediateNode<T>>(*this, value);
}
template <typename T>
ParameterNode<T>& ExpressionNodeFactory::Parameter(ParameterSlotAllocator& slotAllocator)
{
return PlacementConstruct<ParameterNode<T>>(*this, slotAllocator);
}
template <typename T>
Node<T&>& ExpressionNodeFactory::StackVariable()
{
return PlacementConstruct<StackVariableNode<T>>(*this);
}
//
// Unary operators
//
template <typename T>
Node<T*>& ExpressionNodeFactory::AsPointer(Node<T&>& reference)
{
return Cast<T*>(reference);
}
template <typename T>
Node<T&>& ExpressionNodeFactory::AsReference(Node<T*>& pointer)
{
return Cast<T&>(pointer);
}
template <typename TO, typename FROM>
Node<TO>& ExpressionNodeFactory::Cast(Node<FROM>& source)
{
return PlacementConstruct<CastNode<TO, FROM>>(*this, source);
}
template <typename FROM>
Node<FROM const>&
ExpressionNodeFactory::AddConstCast(Node<FROM>& value)
{
return Cast<FROM const>(value);
}
template <typename FROM>
Node<FROM>&
ExpressionNodeFactory::RemoveConstCast(Node<FROM const>& value,
typename std::enable_if<!std::is_const<FROM>::value>::type*)
{
return Cast<FROM>(value);
}
template <typename FROM>
Node<FROM&>&
ExpressionNodeFactory::RemoveConstCast(Node<FROM const &>& value,
typename std::enable_if<std::is_const<FROM>::value>::type*)
{
return Cast<FROM&>(value);
}
template <typename FROM>
Node<FROM const *>&
ExpressionNodeFactory::AddTargetConstCast(Node<FROM*>& value)
{
return Cast<FROM const *>(value);
}
template <typename FROM>
Node<FROM*>& ExpressionNodeFactory::RemoveTargetConstCast(Node<FROM const *>& value)
{
return Cast<FROM*>(value);
}
template <typename T>
Node<T>& ExpressionNodeFactory::Deref(Node<T*>& pointer)
{
return Deref(pointer, 0);
}
template <typename T>
Node<T>& ExpressionNodeFactory::Deref(Node<T*>& pointer, int32_t index)
{
return PlacementConstruct<IndirectNode<T>>(*this, pointer, index);
}
template <typename T>
Node<T>& ExpressionNodeFactory::Deref(Node<T&>& reference)
{
return Deref(AsPointer(reference));
}
template <typename OBJECT, typename FIELD, typename OBJECT1>
Node<FIELD*>&
ExpressionNodeFactory::FieldPointer(Node<OBJECT*>& object, FIELD OBJECT1::*field)
{
static_assert(std::is_same<typename std::remove_const<OBJECT>::type,
typename std::remove_const<OBJECT1>::type>::value,
"Mismatch between the provided object type and field's parent object type");
return PlacementConstruct<FieldPointerNode<OBJECT, FIELD>>(*this, object, field);
}
template <typename T>
Node<T>& ExpressionNodeFactory::Dependent(Node<T>& dependentNode,
NodeBase& prerequisiteNode)
{
return PlacementConstruct<DependentNode<T>>(*this, dependentNode, prerequisiteNode);
}
template <typename T>
NodeBase& ExpressionNodeFactory::Return(Node<T>& value)
{
return PlacementConstruct<ReturnNode<T>>(*this, value);
}
//
// Binary arithmetic operators
//
template <typename L, typename R>
Node<L>& ExpressionNodeFactory::Add(Node<L>& left, Node<R>& right)
{
return Binary<OpCode::Add>(left, right);
}
template <typename L, typename R>
Node<L>& ExpressionNodeFactory::And(Node<L>& left, Node<R>& right)
{
return Binary<OpCode::And>(left, right);
}
template <typename L, typename R>
Node<L>& ExpressionNodeFactory::Sub(Node<L>& left, Node<R>& right)
{
return Binary<OpCode::Sub>(left, right);
}
template <typename L, typename R>
Node<L>& ExpressionNodeFactory::Mul(Node<L>& left, Node<R>& right)
{
return Binary<OpCode::IMul>(left, right);
}
template <typename L, typename R>
Node<L>& ExpressionNodeFactory::MulImmediate(Node<L>& left, R right)
{
Node<L>* result;
if (right == 0)
{
result = &Immediate<L>(0);
}
else if (right == 1)
{
result = &left;
}
else if (BitOp::GetNonZeroBitCount(right) == 1)
{
// Note: not checking return value of GetLowestBitSet() as it's
// guaranteed to return an index when a bit is set.
unsigned bitIndex;
BitOp::GetLowestBitSet(right, &bitIndex);
result = &Shl(left, static_cast<uint8_t>(bitIndex));
}
else
{
result = &BinaryImmediate<OpCode::IMul>(left, right);
}
return *result;
}
template <typename L, typename R>
Node<L>& ExpressionNodeFactory::Or(Node<L>& left, Node<R>& right)
{
return Binary<OpCode::Or>(left, right);
}
template <typename L, typename R>
Node<L>& ExpressionNodeFactory::Rol(Node<L>& left, R right)
{
return BinaryImmediate<OpCode::Rol>(left, right);
}
template <typename L, typename R>
Node<L>& ExpressionNodeFactory::Shl(Node<L>& left, R right)
{
return BinaryImmediate<OpCode::Shl>(left, right);
}
template <typename L, typename R>
Node<L>& ExpressionNodeFactory::Shr(Node<L>& left, R right)
{
return BinaryImmediate<OpCode::Shr>(left, right);
}
template <typename T>
Node<T>& ExpressionNodeFactory::Shld(Node<T>& shiftee, Node<T>& filler, uint8_t bitCount)
{
return PlacementConstruct<ShldNode<T>>(*this, shiftee, filler, bitCount);
}
template <typename T, typename INDEX>
Node<T*>& ExpressionNodeFactory::Add(Node<T*>& array, Node<INDEX>& index)
{
// Cast the index to UInt64 to make sure that the calculated offset
// will not overflow. This will also make it possible to use OpCode::Add
// on the result regardless of sizeof(INDEX) since both T* and UInt64
// use the same register size.
auto & index64 = Cast<uint64_t>(index);
// The IMul instruction doesn't suport 64-bit immediates, but there's
// also no need to support types whose size is larger than UINT32_MAX.
static_assert(sizeof(T) <= UINT32_MAX, "Unsupported type");
auto & offset = MulImmediate(index64, static_cast<uint32_t>(sizeof(T)));
return Binary<OpCode::Add>(array, offset);
}
template <typename T, size_t SIZE, typename INDEX>
Node<T*>& ExpressionNodeFactory::Add(Node<T(*)[SIZE]>& array, Node<INDEX>& index)
{
return Add(Cast<T*>(array), index);
}
//
// Model related
//
template <typename PACKED>
Node<float>& ExpressionNodeFactory::ApplyModel(Node<Model<PACKED>*>& model, Node<PACKED>& packed)
{
auto & array = FieldPointer(model, &Model<PACKED>::m_data);
return Deref(Add(array, packed));
}
//
// Relational operators
//
template <JccType JCC, typename T>
FlagExpressionNode<JCC>&
ExpressionNodeFactory::Compare(Node<T>& left, Node<T>& right)
{
return PlacementConstruct<RelationalOperatorNode<T, JCC>>(*this, left, right);
}
//
// Conditional operators
//
template <typename T, JccType JCC>
Node<T>& ExpressionNodeFactory::Conditional(FlagExpressionNode<JCC>& condition,
Node<T>& trueValue,
Node<T>& falseValue)
{
return PlacementConstruct<ConditionalNode<T, JCC>>(*this, condition, trueValue, falseValue);
}
template <typename CONDT, typename T>
Node<T>& ExpressionNodeFactory::IfNotZero(Node<CONDT>& conditionValue, Node<T>& trueValue, Node<T>& falseValue)
{
auto & conditionNode = Compare<JccType::JNE>(conditionValue, Immediate<CONDT>(0));
return Conditional(conditionNode, trueValue, falseValue);
}
template <typename T>
Node<T>& ExpressionNodeFactory::If(Node<bool>& conditionValue, Node<T>& thenValue, Node<T>& elseValue)
{
return IfNotZero(conditionValue, thenValue, elseValue);
}
//
// Call external function
//
template <typename R>
Node<R>& ExpressionNodeFactory::Call(Node<R (*)()>& function)
{
return PlacementConstruct<CallNode<R>>(*this, function);
}
template <typename R, typename P1>
Node<R>& ExpressionNodeFactory::Call(Node<R (*)(P1)>& function,
Node<P1>& param1)
{
return PlacementConstruct<CallNode<R, P1>>(*this, function, param1);
}
template <typename R, typename P1, typename P2>
Node<R>& ExpressionNodeFactory::Call(Node<R (*)(P1, P2)>& function,
Node<P1>& param1,
Node<P2>& param2)
{
return PlacementConstruct<CallNode<R, P1, P2>>(*this, function, param1, param2);
}
template <typename R, typename P1, typename P2, typename P3>
Node<R>& ExpressionNodeFactory::Call(Node<R (*)(P1, P2, P3)>& function,
Node<P1>& param1,
Node<P2>& param2,
Node<P3>& param3)
{
return PlacementConstruct<CallNode<R, P1, P2, P3>>(*this, function, param1, param2, param3);
}
template <typename R, typename P1, typename P2, typename P3, typename P4>
Node<R>& ExpressionNodeFactory::Call(Node<R (*)(P1, P2, P3, P4)>& function,
Node<P1>& param1,
Node<P2>& param2,
Node<P3>& param3,
Node<P4>& param4)
{
return PlacementConstruct<CallNode<R, P1, P2, P3, P4>>(
*this, function, param1, param2, param3, param4);
}
//
// PackedMinMax
//
template <typename PACKED>
Node<PACKED>& ExpressionNodeFactory::PackedMax(Node<PACKED>& left, Node<PACKED>& right)
{
return PlacementConstruct<PackedMinMaxNode<PACKED, true>>(*this, left, right);
}
template <typename PACKED>
Node<PACKED>& ExpressionNodeFactory::PackedMin(Node<PACKED>& left, Node<PACKED>& right)
{
return PlacementConstruct<PackedMinMaxNode<PACKED, false>>(*this, left, right);
}
//
// Private methods.
//
template <OpCode OP, typename L, typename R>
Node<L>& ExpressionNodeFactory::Binary(Node<L>& left, Node<R>& right)
{
return PlacementConstruct<BinaryNode<OP, L, R>>(*this, left, right);
}
template <OpCode OP, typename L, typename R>
Node<L>& ExpressionNodeFactory::BinaryImmediate(Node<L>& left, R right)
{
return PlacementConstruct<BinaryImmediateNode<OP, L, R>>(*this, left, right);
}
}
``` | /content/code_sandbox/inc/NativeJIT/ExpressionNodeFactory.h | objective-c | 2016-04-09T23:53:19 | 2024-06-29T07:05:56 | NativeJIT | BitFunnel/NativeJIT | 1,133 | 3,181 |
```objective-c
// Permission is hereby granted, free of charge, to any person obtaining a copy
// of this software and associated documentation files (the "Software"), to deal
// in the Software without restriction, including without limitation the rights
// to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
// copies of the Software, and to permit persons to whom the Software is
// furnished to do so, subject to the following conditions:
// The above copyright notice and this permission notice shall be included in
// all copies or substantial portions of the Software.
// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
// AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
// LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
// OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
// THE SOFTWARE.
#pragma once
#include <array> // For arrays in FreeList.
#include <cstdint>
#include <iosfwd> // For debugging output.
#include "NativeJIT/AllocatorVector.h" // Embedded member.
#include "NativeJIT/CodeGen/JumpTable.h" // ExpressionTree embeds Label.
#include "NativeJIT/CodeGen/Register.h"
#include "NativeJIT/TypePredicates.h" // RegisterStorage used in typedef.
#include "Temporary/NonCopyable.h"
namespace Allocators
{
class IAllocator;
}
namespace NativeJIT
{
class ExecutionPreconditionTest;
class FunctionBuffer;
class NodeBase;
class RIPRelativeImmediate;
// A class which increases reference counter on construction and decreases
// it on destruction.
// This class is not thread safe.
class ReferenceCounter final
{
public:
// Default constructor performs no observable reference counting. Used
// in cases where an object of this class needs to be constructed before
// the counter object is known (f. ex. in constructors of classes which
// contain the ReferenceCounter as a member).
ReferenceCounter();
// Increases the reference count in the specified counter.
ReferenceCounter(unsigned& counter);
// Uses the counter in the other object as its counter and increases it.
ReferenceCounter(ReferenceCounter const & other);
// Decreases the current counter.
~ReferenceCounter();
// Decreases the current counter, replaces it with the one in the other
// object and increases that counter.
ReferenceCounter& operator=(ReferenceCounter const & other);
// Decreases the current counter and disassociates itself from it.
void Reset();
private:
// Pointer to the current counter.
unsigned* m_counter;
// Methods to add and remove a reference to the counter.
void AddReference();
void RemoveReference();
};
enum class StorageClass {Direct, Indirect, Immediate};
class ExpressionTree : public NonCopyable
{
private:
class Data;
public:
template <typename T> class Storage;
// Returns the function return register for the specified type.
template <typename T>
static typename Storage<T>::DirectRegister GetResultRegister();
ExpressionTree(Allocators::IAllocator& allocator, FunctionBuffer& code);
Allocators::IAllocator& GetAllocator() const;
FunctionBuffer& GetCodeGenerator() const;
void EnableDiagnostics(std::ostream& out);
void DisableDiagnostics();
// In-place constructs an object using the class allocator. The object's
// lifetime cannot be longer than that of the ExpressionTree.
template <typename T, typename... ConstructorArgs>
T&
PlacementConstruct(ConstructorArgs&&... constructorArgs);
//
// Tree construction
//
unsigned AddNode(NodeBase& node);
// DESIGN NOTE: This might be better if ParameterNode<T> (and get position from it)
// to ensure that other nodes can't be passed to AddParameter. To make
// that possible, a circular include dependency between ExpressionTree.h
// and Node.h (through ParameterNode.h) needs to be broken. Then forward
// declaring ParameterNode<T> and using #include further below would work.
void AddParameter(NodeBase& parameter, unsigned position);
void AddRIPRelative(RIPRelativeImmediate& node);
void ReportFunctionCallNode(unsigned parameterCount);
void Compile();
//
// Storage allocation.
//
template <typename T>
Storage<T> Direct();
template <typename T>
Storage<T> Direct(typename Storage<T>::DirectRegister r);
template <typename T>
Storage<T> RIPRelative(int32_t offset);
// Returns indirect storage relative to the base pointer for a variable
// of type T. It is guaranteed that it's legal to access the whole quadword
// at the target address.
template <typename T>
Storage<T> Temporary();
template <typename T>
Storage<T> Immediate(T value);
template <unsigned SIZE>
void ReleaseRegister(Register<SIZE, false> r);
template <unsigned SIZE>
void ReleaseRegister(Register<SIZE, true> r);
// Given an offset off BaseRegister, checks whether the register
// belongs to a valid offset describing an already allocated slot and,
// if so, releases the corresponding temporary slot. Some valid offsets
// off the base register that don't refer to temporaries include offsets
// referring to compiled function's parameters.
void ReleaseIfTemporary(int32_t offset);
// Returns whether a register is pinned.
template <unsigned SIZE, bool ISFLOAT>
bool IsPinned(Register<SIZE, ISFLOAT> reg);
unsigned GetRXXUsedMask() const;
unsigned GetXMMUsedMask() const;
Label GetStartOfEpilogue() const;
protected:
bool IsDiagnosticsStreamAvailable() const;
// Returns the diagnostic stream. Throws if it is not available.
std::ostream& GetDiagnosticsStream() const;
// Adds a precondition for executing the expression. See the
// m_preconditionTests variable for more information.
void AddExecutionPreconditionTest(ExecutionPreconditionTest& test);
void const * GetUntypedEntryPoint() const;
private:
// Keeps track of used and free registers and the Data* associated with
// each register.
//
// The Data* is kept so that it's easily possible to create another
// Storage around an allocated register when necessary (f. ex. for
// spilling. Thus, there's a required 1-1 mapping between a general
// purpose register and the Data* that refers to it (either as Direct
// or Indirect).
//
// Note that it's neither necessary nor possible to hold information
// about a singular Data* for *Indirect* references to shared base
// registers such as RSP and RIP since multiple Data* refer to them by
// definition and since they don't need to be spilled. The Data* for
// Direct reference to shared base registers is kept, though.
template <unsigned REGISTER_COUNT, bool ISFLOAT>
class FreeList
{
public:
// The bit-mask signifying that all valid registers have been allocated.
static const unsigned c_fullUsedMask = (1ul << REGISTER_COUNT) - 1;
FreeList(Allocators::IAllocator& allocator);
// Returns the number of unallocated registers.
unsigned GetFreeCount() const;
bool IsAvailable(unsigned id) const;
unsigned Allocate();
void Allocate(unsigned id);
// Returns a pin for a register. Pinned register cannot be spilled.
// IMPORTANT: Register pinning should be done in a very limited
// scope. Otherwise, in a larger scope (f. ex. before a CodeGen()
// call) there is a risk of pinning some of the registers used for
// parameter passing, which would cause the compilation of a function
// call to fail.
ReferenceCounter GetPin(unsigned id);
// Returns whether a register is pinned.
bool IsPinned(unsigned id) const;
void Release(unsigned id);
// The methods to set and retrieve the Data* owned by the respective
// register. The InitializeData() and UpdateData() methods differ
// only in sanity checks: the former requires that no Data* was
// previously set for the register whereas the latter requires that
// a Data* already existed.
void InitializeData(unsigned id, Data* data);
void UpdateData(unsigned id, Data* data);
Data* GetData(unsigned id) const;
// Returns the bit-mask for used and allocated registers.
unsigned GetUsedMask() const;
unsigned GetFreeMask() const;
// Returns a register mask specifying which registers were touched
// at any point of time, regardless of whether they were later
// released or not.
unsigned GetLifetimeUsedMask() const;
// Returns the ID of an allocated register that is not pinned and
// can be spilled. Throws if there are no such registers available.
unsigned GetAllocatedSpillable() const;
private:
// Helper methods to perform sanity check on arguments and data contents.
void AssertValidID(unsigned id) const;
void AssertValidData(unsigned id) const;
void AssertValidData(unsigned id, Data* data) const;
// The mask tracking registers which are currently allocated.
unsigned m_usedMask;
// The mask tracking registers which were touched at any point of
// time, regardless of whether they were later released or not.
unsigned m_lifetimeUsedMask;
const unsigned m_volatileRegisterMask;
const unsigned m_nonVolatileRegisterMask;
// See the class description for more details.
std::array<Data*, REGISTER_COUNT> m_data;
// An array of currently allocated IDs, oldest at the beginning.
// DESIGN NOTE: Deque and list better satisfy this variable's usage
// pattern in general (elements always added at the back, mostly pulled
// out from the front). However, given the small number of elements
// and the simplicitly of the vector, it is likely to perform better.
AllocatorVector<uint8_t> m_allocatedRegisters;
// Number of active references to a pinned register. The register
// cannot be spilled while it's pinned.
std::array<unsigned, REGISTER_COUNT> m_pinCount;
};
bool IsBasePointer(PointerRegister r) const;
PointerRegister GetBasePointer() const;
// Returns whether the register is one of the reserved/shared base
// registers (instruction, stack or base pointer).
template <unsigned SIZE>
bool IsAnySharedBaseRegister(Register<SIZE, false> r) const;
template <unsigned SIZE>
bool IsAnySharedBaseRegister(Register<SIZE, true> r) const;
// Converts a valid temporary slot index into an offset off base register.
int32_t TemporarySlotToOffset(unsigned temporarySlot);
// If the temporary offset off base register describes a valid allocated
// temporary slot, returns true and fills in the temporary slot out
// parameter. Returns false otherwise.
bool TemporaryOffsetToSlot(int32_t temporaryOffset, unsigned& temporarySlot);
void Pass0();
void Pass1();
void Pass2();
void Pass3();
void Print() const;
// The following template and the alias template provide a way to access
// the free list for a register and a C++ type respectively.
template <bool ISFLOAT>
class FreeListForRegister;
template <typename T>
using FreeListForType = class FreeListForRegister<RegisterStorage<T>::c_isFloat>;
// The allocator and STL-compatible wrapper around it.
Allocators::IAllocator& m_allocator;
Allocators::StlAllocator<void*> m_stlAllocator;
FunctionBuffer & m_code;
// Stream used to print diagnostics or nullptr if disabled.
std::ostream* m_diagnosticsStream;
AllocatorVector<NodeBase*> m_topologicalSort;
AllocatorVector<NodeBase*> m_parameters;
AllocatorVector<RIPRelativeImmediate*> m_ripRelatives;
// Preconditions for evaluating the whole expression. The preconditions
// are evaluated right after the parameters and will cause the function
// to return early if any of them is not met.
AllocatorVector<ExecutionPreconditionTest*> m_preconditionTests;
FreeList<RegisterBase::c_maxIntegerRegisterID + 1, false> m_rxxFreeList;
FreeList<RegisterBase::c_maxFloatRegisterID + 1, true> m_xmmFreeList;
AllocatorVector<Storage<void*>> m_reservedRxxRegisterStorages;
AllocatorVector<Storage<double>> m_reservedXmmRegisterStorages;
AllocatorVector<ReferenceCounter> m_reservedRegistersPins;
unsigned m_temporaryCount;
AllocatorVector<int32_t> m_temporaries;
// Maximum number of parameters used in function calls done by the tree.
// Negative value signifies no function calls made.
int m_maxFunctionCallParameters;
PointerRegister m_basePointer;
Label m_startOfEpilogue;
};
class ExpressionTree::Data : public NonCopyable
{
public:
template <unsigned SIZE, bool ISFLOAT>
Data(ExpressionTree& tree, Register<SIZE, ISFLOAT> r);
// DESIGN NOTE: It would be better if indrect memory knew the size of the memory it
// points to, otherwise access violation can happen if larger, non-owned
// memory area is dereferenced.
// Also applies to ConvertDirectToIndirect and Storage::Direct(Register).
Data(ExpressionTree& tree, PointerRegister r, int32_t offset);
// Note: attempt to create an immediate storage will static_assert for
// invalid immediates.
template <typename T>
Data(ExpressionTree& tree, T value);
ExpressionTree& GetTree() const;
StorageClass GetStorageClass() const;
unsigned GetRegisterId() const;
int32_t GetOffset() const;
// Note: attempt to GetImmediate() will static_assert for invalid immediates.
template <typename T>
T GetImmediate() const;
void ConvertDirectToIndirect(int32_t offset);
void ConvertIndirectToDirect();
unsigned GetRefCount() const;
unsigned Decrement();
void Increment();
// Swaps the targets between two Data objects keeping the reference
// count unchanged and notifies the free list of the register change.
// Used when all clients of both data objects need to have the contents
// exchanged.
void SwapContents(Data* other);
private:
// WARNING: This class is designed to be allocated by an arena allocator,
// so its destructor will never be called. Therefore, it should hold no
// resources other than memory from the arena allocator.
~Data();
// The type of the register change that the free list gets notified about.
enum class RegisterChangeType { Initialize, Update };
// Returns true if data's storage class is direct/immediate and if the
// register it refers to is one of the shared registers.
bool IsSharedBaseRegister() const;
// Notifies the free list that register ID of this data object has
// been modified. Calls the templated version of the same method to
// peform the actual work.
void NotifyDataRegisterChange(RegisterChangeType type);
// See above.
template <bool ISFLOAT>
void NotifyDataRegisterChange(RegisterChangeType type);
ExpressionTree& m_tree;
// How the data is stored.
StorageClass m_storageClass;
// Which register.
bool m_isFloat;
unsigned m_registerId;
int32_t m_offset;
// Holds the immediate value for Data whose storage class is Immediate.
size_t m_immediate;
// Who is using it.
unsigned m_refCount;
};
// Storage should be public because it is a return type for Node.
// Storage should be private so that its constructor can take an m_data.
template <typename T>
class ExpressionTree::Storage
{
public:
// All Storages need to be treated as the same class, regardless of
// the template parameter.
template <typename U> friend class Storage;
typedef typename RegisterStorage<T>::RegisterType DirectRegister;
typedef PointerRegister BaseRegister;
typedef typename DirectRegister::FullRegister FullRegister;
// Types of swaps. The Single swap affects only the two storages directly
// involved by swapping their Data*. The AllReferences swap modifies the
// underlying Data objects thus swapping the data for the first storage
// as well as the storages that share the same Data* with the second
// storage as well as the storages that share its Data*.
enum class SwapType { Single, AllReferences };
Storage();
template <typename U>
explicit Storage(const Storage<U>& other);
Storage(Storage const & other);
// Takes ownership of a base storage, adds the offset to it and
// dereferences it to produce a Storage<T>. Equivalent to
// *static_cast<T*>(base + byteOffset).
Storage(Storage<void*>&& base, int32_t byteOffset);
// Creates another storage referencing a register. The register must
// already be allocated. For shared base registers, the Storage will
// reference the direct Data version which cannot be converted to
// indirect nor spilled since it's pinned.
static Storage<T> ForAdditionalReferenceToRegister(
ExpressionTree& tree,
DirectRegister reg);
// Allocates an empty register and creates a direct storage referencing it.
// Can only be called when there are available registers.
static Storage<T> ForAnyFreeRegister(ExpressionTree& tree);
// Allocates a specific empty register and creates a direct storage
// referencing it. Can only be called when the specified register is free.
static Storage<T> ForFreeRegister(ExpressionTree& tree,
DirectRegister reg);
// Creates an indirect storage against a shared base register.
static Storage<T> ForSharedBaseRegister(ExpressionTree& tree,
BaseRegister base,
int32_t offset);
// Creates an immediate storage with the specified value.
static Storage<T> ForImmediate(ExpressionTree& tree, T value);
// Loads the address of an immediate storage into a newly created direct
// storage and resets the original storage. If possible, reuses the
// register from the source storage.
// Note: do not call this method with a last reference to a Temporary as
// the Temporary may be released after the source storage is reset and
// the created storage would point to invalid the memory.
template <typename U>
static Storage<T> AddressOfIndirect(Storage<U>&& indirect);
Storage& operator=(Storage const & other);
~Storage();
void Reset();
bool IsNull() const;
// Returns whether this Storage shares ownership over its Data*.
// Note that for direct storages, IsSoleDataOwner() result of true
// implies that the storage also exclusively owns the register. For
// indirect storages, this implication stands only for non-shared base
// registers.
bool IsSoleDataOwner() const;
StorageClass GetStorageClass() const;
DirectRegister GetDirectRegister() const;
BaseRegister GetBaseRegister() const;
int32_t GetOffset() const;
// Note: The method must be removed for invalid immediates rather than
// static_assert triggered because for some of them (arrays) the method
// has invalid declaration otherwise.
template <typename U = T,
typename ENABLED = typename std::enable_if<ImmediateCategoryOf<U>::value
== ImmediateCategory::InlineImmediate>::type>
U GetImmediate() const;
DirectRegister ConvertToDirect(bool forModification);
// Swaps the contents of the two storages. See SwapType definition for
// more details.
template <typename U>
void Swap(Storage<U>& other, SwapType type);
// If the storage is not the sole data owner, copies the data to stack
// and switches the ownership of other owners to it.
// Does nothing if the storage was already the sole data owner.
// Requires that the storage is direct and that it does not refer to
// one of the shared base registers.
void TakeSoleOwnershipOfDirect();
// Returns a pin for the storage's register. While the pin is held,
// the register cannot be spilled. Can only be called if Storage is
// either direct or if it's indirect and refers to non-shared base
// registers.
ReferenceCounter GetPin();
// Prints the information about the storage's type, value, base register
// and offset to the output stream.
void Print(std::ostream& out) const;
// Returns whether or not two storages point to the same Data object.
// (as opposed to having the same contents).
template <typename U>
bool operator==(Storage<U> const & other) const;
private:
// Types used to select the correct flavor of immediate methods. This is
// necessary because GetStorageClass() is a runtime rather than a compile
// time property. Even though it is not possible to create a
// StorageClass::Immediate storage for an invalid immediate, the code
// that branches depending on various types of storage needs to always
// compile.
struct ValidImmediateStorage {};
struct InvalidImmediateStorage {};
typedef typename std::conditional<CanBeInImmediateStorage<T>::value,
ValidImmediateStorage,
InvalidImmediateStorage>::type
ImmediateFlavor;
Storage(ExpressionTree::Data* data);
void SetData(ExpressionTree::Data* data);
void SetData(Storage& other);
void ConvertImmediateToDirect(bool forModification, ValidImmediateStorage);
void ConvertImmediateToDirect(bool forModification, InvalidImmediateStorage);
void PrintImmediate(std::ostream& out, ValidImmediateStorage) const;
void PrintImmediate(std::ostream& out, InvalidImmediateStorage) const;
ExpressionTree::Data* m_data;
};
template <typename T>
using Storage = typename ExpressionTree::Storage<T>;
}
``` | /content/code_sandbox/inc/NativeJIT/ExpressionTreeDecls.h | objective-c | 2016-04-09T23:53:19 | 2024-06-29T07:05:56 | NativeJIT | BitFunnel/NativeJIT | 1,133 | 4,754 |
```objective-c
// Permission is hereby granted, free of charge, to any person obtaining a copy
// of this software and associated documentation files (the "Software"), to deal
// in the Software without restriction, including without limitation the rights
// to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
// copies of the Software, and to permit persons to whom the Software is
// furnished to do so, subject to the following conditions:
// The above copyright notice and this permission notice shall be included in
// all copies or substantial portions of the Software.
// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
// AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
// LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
// OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
// THE SOFTWARE.
#pragma once
#include "NativeJIT/CodeGen/X64CodeGenerator.h"
#include "NativeJIT/ExpressionTree.h"
#include "NativeJIT/Nodes/ConditionalNode.h"
#include "NativeJIT/Nodes/ImmediateNode.h"
namespace NativeJIT
{
// A base class for statements that check whether a precondition for executing
// the full expression has been met and cause a fixed value to be returned
// if not.
class ExecutionPreconditionTest : private NonCopyable
{
public:
// Executes its test and allows the regular flow to continue if test's
// condition is satisfied. Otherwise, places an alternative fixed value
// into the return register and jumps to function's epilog.
virtual void Evaluate(ExpressionTree& tree) = 0;
};
// A class implementing a statement that causes the function either to start
// executing if a precondition has been met or to return an immediate value
// otherwise.
//
// DESIGN NOTE: something similar can be achieved with the If() node-based
// expression at the root of the expression tree, but that may be very
// inefficient: the expression tree will pre-evaluate nodes with multiple
// parents first and then start evaluating the expression. Almost all of the
// pre-evaluated nodes are irrelevant to the early return test, so their X64
// code may be executed needlessly at runtime. This is an issue in cases
// when the function is executed a large number of times for different
// inputs where the vast majority of them is expected to return early.
template <typename T, JccType JCC>
class ExecuteOnlyIfStatement : public ExecutionPreconditionTest
{
public:
ExecuteOnlyIfStatement(FlagExpressionNode<JCC>& condition,
ImmediateNode<T>& otherwiseValue);
//
// Overrides of ExecutionPreconditionTest.
//
virtual void Evaluate(ExpressionTree& tree) override;
private:
FlagExpressionNode<JCC>& m_condition;
ImmediateNode<T>& m_otherwiseValue;
};
//
// Template definitions for ExecuteOnlyIfStatement.
//
template <typename T, JccType JCC>
ExecuteOnlyIfStatement<T, JCC>::ExecuteOnlyIfStatement(
FlagExpressionNode<JCC>& condition,
ImmediateNode<T>& otherwiseValue)
: m_condition(condition),
m_otherwiseValue(otherwiseValue)
{
m_otherwiseValue.IncrementParentCount();
// Use the CodeGenFlags()-related call.
m_condition.IncrementFlagsParentCount();
}
template <typename T, JccType JCC>
void ExecuteOnlyIfStatement<T, JCC>::Evaluate(ExpressionTree& tree)
{
X64CodeGenerator& code = tree.GetCodeGenerator();
Label continueWithRegularFlow = code.AllocateLabel();
// Evaluate the condition to update the CPU flags. If condition is
// satisfied, continue with the regular flow.
m_condition.CodeGenFlags(tree);
code.EmitConditionalJump<JCC>(continueWithRegularFlow);
// Otherwise, return early with the constant value: move the constant
// into the return register and jump to epilog.
auto resultRegister = tree.GetResultRegister<T>();
// IMPORTANT: CodeGen() for ImmediateNode will not cause any registers
// to be spilled or modified. Otherwise, NativeJIT's view of the register
// allocation would get out of sync with the actual state due to the
// conditional jump above. See the comment in
// ConditionalNode::CodeGenValue for more details.
auto otherwiseValue = m_otherwiseValue.CodeGen(tree);
// Move the value into the result register unless already there.
if (!(otherwiseValue.GetStorageClass() == StorageClass::Direct
&& otherwiseValue.GetDirectRegister() == resultRegister))
{
CodeGenHelpers::Emit<OpCode::Mov>(tree.GetCodeGenerator(),
resultRegister,
otherwiseValue);
}
// There are no issues to jumping directly to the start of epilog with
// no regard for the instructions generated before Evaluate() as there
// is nothing in them that would need to be undone. Most notably, the
// stack pointer is supposed to be kept constant during evaluation
// of the function (except temporarily for function calls).
code.Jmp(tree.GetStartOfEpilogue());
code.PlaceLabel(continueWithRegularFlow);
}
}
``` | /content/code_sandbox/inc/NativeJIT/ExecutionPreconditionTest.h | objective-c | 2016-04-09T23:53:19 | 2024-06-29T07:05:56 | NativeJIT | BitFunnel/NativeJIT | 1,133 | 1,160 |
```objective-c
// Permission is hereby granted, free of charge, to any person obtaining a copy
// of this software and associated documentation files (the "Software"), to deal
// in the Software without restriction, including without limitation the rights
// to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
// copies of the Software, and to permit persons to whom the Software is
// furnished to do so, subject to the following conditions:
// The above copyright notice and this permission notice shall be included in
// all copies or substantial portions of the Software.
// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
// AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
// LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
// OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
// THE SOFTWARE.
#pragma once
namespace NativeJIT
{
// DESIGN NOTE: see path_to_url Data
// is polymorphic, and stores a binary blob representing the value of the
// data. TypeCoverter reads and writes the value while without violating
// strict-aliasing via type punning. For example, replaces code that did:
// *(reinterpret_cast<T const *>(&m_immediate));
// and
// *reinterpret_cast<T*>(&m_immediate) = value;
template <typename FROM, typename TO>
union TypeConverter
{
TypeConverter() {}
FROM m_fromValue;
TO m_toValue;
};
template <typename FROM, typename TO>
TO convertType(FROM value)
{
TypeConverter<FROM, TO> temp;
temp.m_fromValue = value;
return temp.m_toValue;
}
}
``` | /content/code_sandbox/inc/NativeJIT/TypeConverter.h | objective-c | 2016-04-09T23:53:19 | 2024-06-29T07:05:56 | NativeJIT | BitFunnel/NativeJIT | 1,133 | 406 |
```objective-c
// Permission is hereby granted, free of charge, to any person obtaining a copy
// of this software and associated documentation files (the "Software"), to deal
// in the Software without restriction, including without limitation the rights
// to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
// copies of the Software, and to permit persons to whom the Software is
// furnished to do so, subject to the following conditions:
// The above copyright notice and this permission notice shall be included in
// all copies or substantial portions of the Software.
// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
// AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
// LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
// OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
// THE SOFTWARE.
#pragma once
#include <vector>
#include "Temporary/StlAllocator.h"
namespace NativeJIT
{
// An alias for a vector which is using StlAllocator to allocate memory.
template <typename T>
using AllocatorVector = std::vector<T, Allocators::StlAllocator<T>>;
}
``` | /content/code_sandbox/inc/NativeJIT/AllocatorVector.h | objective-c | 2016-04-09T23:53:19 | 2024-06-29T07:05:56 | NativeJIT | BitFunnel/NativeJIT | 1,133 | 282 |
```objective-c
// Permission is hereby granted, free of charge, to any person obtaining a copy
// of this software and associated documentation files (the "Software"), to deal
// in the Software without restriction, including without limitation the rights
// to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
// copies of the Software, and to permit persons to whom the Software is
// furnished to do so, subject to the following conditions:
// The above copyright notice and this permission notice shall be included in
// all copies or substantial portions of the Software.
// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
// AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
// LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
// OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
// THE SOFTWARE.
#pragma once
#include "NativeJIT/ExecutionPreconditionTest.h"
#include "NativeJIT/ExpressionNodeFactory.h"
#include "NativeJIT/TypePredicates.h"
namespace NativeJIT
{
template <typename R>
class FunctionBase : public ExpressionNodeFactory
{
public:
FunctionBase(Allocators::IAllocator& allocator, FunctionBuffer& code);
template <JccType JCC>
void AddExecuteOnlyIfStatement(FlagExpressionNode<JCC>& condition,
ImmediateNode<R>& otherwiseValue);
private:
Allocators::IAllocator& m_allocator;
};
template <typename R, typename P1 = void, typename P2 = void, typename P3 = void, typename P4 = void>
class Function : public FunctionBase<R>
{
public:
Function(Allocators::IAllocator& allocator, FunctionBuffer& code);
ParameterNode<P1>& GetP1() const;
ParameterNode<P2>& GetP2() const;
ParameterNode<P3>& GetP3() const;
ParameterNode<P4>& GetP4() const;
typedef R (*FunctionType)(P1, P2, P3, P4);
FunctionType Compile(Node<R>& expression);
FunctionType GetEntryPoint() const;
private:
ParameterNode<P1>* m_p1;
ParameterNode<P2>* m_p2;
ParameterNode<P3>* m_p3;
ParameterNode<P4>* m_p4;
};
template <typename R, typename P1, typename P2, typename P3>
class Function<R, P1, P2, P3> : public FunctionBase<R>
{
public:
Function(Allocators::IAllocator& allocator, FunctionBuffer& code);
ParameterNode<P1>& GetP1() const;
ParameterNode<P2>& GetP2() const;
ParameterNode<P3>& GetP3() const;
typedef R (*FunctionType)(P1, P2, P3);
FunctionType Compile(Node<R>& expression);
FunctionType GetEntryPoint() const;
private:
ParameterNode<P1>* m_p1;
ParameterNode<P2>* m_p2;
ParameterNode<P3>* m_p3;
};
template <typename R, typename P1, typename P2>
class Function<R, P1, P2> : public FunctionBase<R>
{
public:
Function(Allocators::IAllocator& allocator, FunctionBuffer& code);
ParameterNode<P1>& GetP1() const;
ParameterNode<P2>& GetP2() const;
typedef R (*FunctionType)(P1, P2);
FunctionType Compile(Node<R>& expression);
FunctionType GetEntryPoint() const;
private:
ParameterNode<P1>* m_p1;
ParameterNode<P2>* m_p2;
};
template <typename R, typename P1>
class Function<R, P1> : public FunctionBase<R>
{
public:
Function(Allocators::IAllocator& allocator, FunctionBuffer& code);
ParameterNode<P1>& GetP1() const;
typedef R (*FunctionType)(P1);
FunctionType Compile(Node<R>& expression);
FunctionType GetEntryPoint() const;
private:
ParameterNode<P1>* m_p1;
};
template <typename R>
class Function<R> : public FunctionBase<R>
{
public:
Function(Allocators::IAllocator& allocator, FunctionBuffer& code);
typedef R (*FunctionType)();
FunctionType Compile(Node<R>& expression);
FunctionType GetEntryPoint() const;
};
//*************************************************************************
//
// FunctionBase<R> template definitions.
//
//*************************************************************************
template <typename R>
FunctionBase<R>::FunctionBase(Allocators::IAllocator& allocator,
FunctionBuffer& code)
: ExpressionNodeFactory(allocator, code),
m_allocator(allocator)
{
static_assert(IsValidParameter<R>::c_value, "R is an invalid type.");
}
template <typename R>
template <JccType JCC>
void FunctionBase<R>::AddExecuteOnlyIfStatement(FlagExpressionNode<JCC>& condition,
ImmediateNode<R>& otherwiseValue)
{
auto & test = PlacementConstruct<ExecuteOnlyIfStatement<R, JCC>>(condition, otherwiseValue);
AddExecutionPreconditionTest(test);
}
//*************************************************************************
//
// Function<R, P1, P2, P3, P4> template definitions.
//
//*************************************************************************
template <typename R, typename P1, typename P2, typename P3, typename P4>
Function<R, P1, P2, P3, P4>::Function(Allocators::IAllocator& allocator,
FunctionBuffer& code)
: FunctionBase<R>(allocator, code)
{
static_assert(IsValidParameter<P1>::c_value, "P1 is an invalid type.");
static_assert(IsValidParameter<P2>::c_value, "P2 is an invalid type.");
static_assert(IsValidParameter<P3>::c_value, "P3 is an invalid type.");
static_assert(IsValidParameter<P4>::c_value, "P4 is an invalid type.");
ParameterSlotAllocator slotAllocator;
m_p1 = &this->template Parameter<P1>(slotAllocator);
m_p2 = &this->template Parameter<P2>(slotAllocator);
m_p3 = &this->template Parameter<P3>(slotAllocator);
m_p4 = &this->template Parameter<P4>(slotAllocator);
}
template <typename R, typename P1, typename P2, typename P3, typename P4>
ParameterNode<P1>& Function<R, P1, P2, P3, P4>::GetP1() const
{
return *m_p1;
}
template <typename R, typename P1, typename P2, typename P3, typename P4>
ParameterNode<P2>& Function<R, P1, P2, P3, P4>::GetP2() const
{
return *m_p2;
}
template <typename R, typename P1, typename P2, typename P3, typename P4>
ParameterNode<P3>& Function<R, P1, P2, P3, P4>::GetP3() const
{
return *m_p3;
}
template <typename R, typename P1, typename P2, typename P3, typename P4>
ParameterNode<P4>& Function<R, P1, P2, P3, P4>::GetP4() const
{
return *m_p4;
}
template <typename R, typename P1, typename P2, typename P3, typename P4>
typename Function<R, P1, P2, P3, P4>::FunctionType
Function<R, P1, P2, P3, P4>::Compile(Node<R>& value)
{
this->template Return<R>(value);
ExpressionTree::Compile();
return GetEntryPoint();
}
template <typename R, typename P1, typename P2, typename P3, typename P4>
typename Function<R, P1, P2, P3, P4>::FunctionType
Function<R, P1, P2, P3, P4>::GetEntryPoint() const
{
return reinterpret_cast<FunctionType>(const_cast<void*>(this->GetUntypedEntryPoint()));
}
//*************************************************************************
//
// Function<R, P1, P2, P3> template definitions.
//
//*************************************************************************
template <typename R, typename P1, typename P2, typename P3>
Function<R, P1, P2, P3>::Function(Allocators::IAllocator& allocator,
FunctionBuffer& code)
: FunctionBase<R>(allocator, code)
{
static_assert(IsValidParameter<P1>::c_value, "P1 is an invalid type.");
static_assert(IsValidParameter<P2>::c_value, "P2 is an invalid type.");
static_assert(IsValidParameter<P3>::c_value, "P3 is an invalid type.");
ParameterSlotAllocator slotAllocator;
m_p1 = &this->template Parameter<P1>(slotAllocator);
m_p2 = &this->template Parameter<P2>(slotAllocator);
m_p3 = &this->template Parameter<P3>(slotAllocator);
}
template <typename R, typename P1, typename P2, typename P3>
ParameterNode<P1>& Function<R, P1, P2, P3>::GetP1() const
{
return *m_p1;
}
template <typename R, typename P1, typename P2, typename P3>
ParameterNode<P2>& Function<R, P1, P2, P3>::GetP2() const
{
return *m_p2;
}
template <typename R, typename P1, typename P2, typename P3>
ParameterNode<P3>& Function<R, P1, P2, P3>::GetP3() const
{
return *m_p3;
}
template <typename R, typename P1, typename P2, typename P3>
typename Function<R, P1, P2, P3>::FunctionType
Function<R, P1, P2, P3>::Compile(Node<R>& value)
{
this->template Return<R>(value);
ExpressionTree::Compile();
return GetEntryPoint();
}
template <typename R, typename P1, typename P2, typename P3>
typename Function<R, P1, P2, P3>::FunctionType
Function<R, P1, P2, P3>::GetEntryPoint() const
{
return reinterpret_cast<FunctionType>(const_cast<void*>(this->GetUntypedEntryPoint()));
}
//*************************************************************************
//
// Function<R, P1, P2> template definitions.
//
//*************************************************************************
template <typename R, typename P1, typename P2>
Function<R, P1, P2>::Function(Allocators::IAllocator& allocator,
FunctionBuffer& code)
: FunctionBase<R>(allocator, code)
{
static_assert(IsValidParameter<P1>::c_value, "P1 is an invalid type.");
static_assert(IsValidParameter<P2>::c_value, "P2 is an invalid type.");
ParameterSlotAllocator slotAllocator;
m_p1 = &this->template Parameter<P1>(slotAllocator);
m_p2 = &this->template Parameter<P2>(slotAllocator);
}
template <typename R, typename P1, typename P2>
ParameterNode<P1>& Function<R, P1, P2>::GetP1() const
{
return *m_p1;
}
template <typename R, typename P1, typename P2>
ParameterNode<P2>& Function<R, P1, P2>::GetP2() const
{
return *m_p2;
}
template <typename R, typename P1, typename P2>
typename Function<R, P1, P2>::FunctionType
Function<R, P1, P2>::Compile(Node<R>& value)
{
this->template Return<R>(value);
ExpressionTree::Compile();
return GetEntryPoint();
}
template <typename R, typename P1, typename P2>
typename Function<R, P1, P2>::FunctionType
Function<R, P1, P2>::GetEntryPoint() const
{
return reinterpret_cast<FunctionType>(const_cast<void*>(this->GetUntypedEntryPoint()));
}
//*************************************************************************
//
// Function<R, P1> template definitions.
//
//*************************************************************************
template <typename R, typename P1>
Function<R, P1>::Function(Allocators::IAllocator& allocator,
FunctionBuffer& code)
: FunctionBase<R>(allocator, code)
{
static_assert(IsValidParameter<P1>::c_value, "P1 is an invalid type.");
ParameterSlotAllocator slotAllocator;
m_p1 = &this->template Parameter<P1>(slotAllocator);
}
template <typename R, typename P1>
ParameterNode<P1>& Function<R, P1>::GetP1() const
{
return *m_p1;
}
template <typename R, typename P1>
typename Function<R, P1>::FunctionType
Function<R, P1>::Compile(Node<R>& value)
{
this->template Return<R>(value);
ExpressionTree::Compile();
return GetEntryPoint();
}
template <typename R, typename P1>
typename Function<R, P1>::FunctionType
Function<R, P1>::GetEntryPoint() const
{
return reinterpret_cast<FunctionType>(const_cast<void*>(this->GetUntypedEntryPoint()));
}
//*************************************************************************
//
// Function<R> template definitions.
//
//*************************************************************************
template <typename R>
Function<R>::Function(Allocators::IAllocator& allocator,
FunctionBuffer& code)
: FunctionBase<R>(allocator, code)
{
}
template <typename R>
typename Function<R>::FunctionType Function<R>::Compile(Node<R>& value)
{
this->template Return<R>(value);
ExpressionTree::Compile();
return GetEntryPoint();
}
template <typename R>
typename Function<R>::FunctionType Function<R>::GetEntryPoint() const
{
return reinterpret_cast<FunctionType>(const_cast<void*>(this->GetUntypedEntryPoint()));
}
}
``` | /content/code_sandbox/inc/NativeJIT/Function.h | objective-c | 2016-04-09T23:53:19 | 2024-06-29T07:05:56 | NativeJIT | BitFunnel/NativeJIT | 1,133 | 3,145 |
```objective-c
// Permission is hereby granted, free of charge, to any person obtaining a copy
// of this software and associated documentation files (the "Software"), to deal
// in the Software without restriction, including without limitation the rights
// to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
// copies of the Software, and to permit persons to whom the Software is
// furnished to do so, subject to the following conditions:
// The above copyright notice and this permission notice shall be included in
// all copies or substantial portions of the Software.
// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
// AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
// LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
// OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
// THE SOFTWARE.
#pragma once
#include <cstdint>
#include <type_traits>
#ifdef _MSC_VER
#include <intrin.h>
#else
#include <nmmintrin.h>
#include <smmintrin.h>
#include <string.h> // For ffsll()
#include <x86intrin.h> // For __lzcnt64.
#endif
// path_to_url
// path_to_url
// path_to_url
namespace NativeJIT
{
#ifdef _MSC_VER
typedef long BitTestType32;
typedef long long BitTestType64;
typedef unsigned long BitScanType32;
static_assert(sizeof(BitTestType32) == 4, "Invalid BitTestType32 size");
static_assert(sizeof(BitTestType64) == 8, "Invalid BitTestType64 size");
static_assert(sizeof(BitScanType32) == 4, "Invalid BitTestType size");
#else
//#include <x86intrin.h> // Intrinsic instructions.
#endif
// WARNING: the methods in this file are thin wrappers around compiler
// intrinsic methods. As such, they are meant to have no or minimal added
// overhead which is why only compile-time checks are done, but no runtime
// checks for valid input range or similar are performed.
namespace BitOp
{
extern const bool c_isPopCntSupported;
extern char const * const c_bitsSetInByte;
// Reinterprets the cast from FROM* to TO*, ensuring that FROM and
// TO are indeed of the same size.
// This is necessary since bit intrinsics take e.g. pointer to long
// and won't accept pointer to int32_t (i.e. int) even though long and
// int have the same size. The cast doesn't verify that signedness is
// the same since bit intrinsics work the same way regardless of sign.
template <typename TO, typename FROM>
inline
TO* SameTargetSizeCast(FROM* pointer)
{
static_assert(sizeof(FROM) == sizeof(TO),
"The pointers must point to types of the same size");
return reinterpret_cast<TO*>(pointer);
}
// Returns the count of 1 bits in the value.
// Requires SSE4 support.
// See path_to_url#POPCNT_and_LZCNT
// Note that processors from around 2008 and onwards support POPCNT,
inline
uint8_t GetNonZeroBitCount(uint32_t value)
{
return static_cast<uint8_t>(_mm_popcnt_u32(value));
}
// Returns the count of 1 bits in the value.
// Requires SSE4 support.
// See path_to_url#POPCNT_and_LZCNT
inline
uint8_t GetNonZeroBitCount(uint64_t value)
{
return static_cast<uint8_t>(_mm_popcnt_u64(value));
}
// Stores the index of the lowest 1 bit and returns true. Returns
// false and leaves lowestBitSetIndex in an underterminate state
// if the value has no bits set.
// Uses BSF instruction. See path_to_url
inline
bool GetLowestBitSet(uint64_t value, unsigned* lowestBitSetIndex)
{
#ifdef _MSC_VER
return _BitScanForward64(SameTargetSizeCast<BitScanType32>(lowestBitSetIndex),
value)
? true
: false;
#else
*lowestBitSetIndex =
static_cast<unsigned>(ffsll(static_cast<int64_t>(value)));
bool retval = *lowestBitSetIndex != 0;
--*lowestBitSetIndex;
return retval;
#endif
}
// Stores the index of the highest 1 bit and returns true. Returns
// false and leaves highestBitSetIndex in an underterminate state
// if the value has no bits set.
// Uses BSR instruction. See path_to_url
inline
bool GetHighestBitSet(uint64_t value, unsigned* highestBitSetIndex)
{
#ifdef _MSC_VER
// VC++ provides _BitScanReverse64()
return _BitScanReverse64(SameTargetSizeCast<BitScanType32>(highestBitSetIndex),
value)
? true
: false;
#else
#ifdef __LZCNT__
*highestBitSetIndex = __lzcnt64(value);
bool retval = *highestBitSetIndex != 64;
*highestBitSetIndex = 63 - *highestBitSetIndex;
return retval;
#else
*highestBitSetIndex = 63 - static_cast<unsigned>(__builtin_clzll(value));
return value != 0;
#endif
#endif
}
// Returns a boolean indicating whether the specified bit is set or not.
// WARNING: Does not verify that bitIndex is in valid range.
inline
bool TestBit(uint64_t value, unsigned bitIndex)
{
#ifdef _MSC_VER
return _bittest64(SameTargetSizeCast<const BitTestType64>(&value),
bitIndex)
? true
: false;
#else
return (value & (static_cast<uint64_t>(1) << bitIndex)) ? true : false;
#endif
}
// Returns a boolean indicating whether the specified bit is set or not.
// WARNING: Does not verify that bitIndex is in valid range.
template <typename T>
inline
bool TestBit(T value, unsigned bitIndex)
{
static_assert(std::is_integral<T>::value, "Value must be integral");
#ifdef _MSC_VER
static_assert(sizeof(T) <= sizeof(BitTestType32), "Value must not be larger than 32 bits");
const uint32_t value32 = value;
return _bittest(SameTargetSizeCast<const BitTestType32>(&value32),
bitIndex)
? true
: false;
#else
return (value & (static_cast<T>(1) << bitIndex)) ? true : false;
#endif
}
// Sets a specific bit in the target value.
// WARNING: Does not verify that bitIndex is in valid range.
template <typename T>
inline
void SetBit(T* value, unsigned bitIndex)
{
*value |= static_cast<T>(1) << bitIndex;
}
// Clears a bit in the target value.
// WARNING: Does not verify that bitIndex is in valid range.
template <typename T>
inline
void ClearBit(T* value, unsigned bitIndex)
{
*value &= ~(static_cast<T>(1) << bitIndex);
}
}
}
``` | /content/code_sandbox/inc/NativeJIT/BitOperations.h | objective-c | 2016-04-09T23:53:19 | 2024-06-29T07:05:56 | NativeJIT | BitFunnel/NativeJIT | 1,133 | 1,646 |
```objective-c
// Permission is hereby granted, free of charge, to any person obtaining a copy
// of this software and associated documentation files (the "Software"), to deal
// in the Software without restriction, including without limitation the rights
// to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
// copies of the Software, and to permit persons to whom the Software is
// furnished to do so, subject to the following conditions:
// The above copyright notice and this permission notice shall be included in
// all copies or substantial portions of the Software.
// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
// AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
// LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
// OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
// THE SOFTWARE.
#pragma once
#include <type_traits>
namespace NativeJIT
{
template <typename PACKED>
class Model
{
public:
typedef PACKED PackedType;
Model();
float Apply(PACKED packed) const;
float& operator[](unsigned index);
float const & operator[](unsigned index) const;
float& operator[](PACKED packed);
float const & operator[](PACKED packed) const;
// m_data must be public or friend of NativeJIT::ExpressionNodeFactory.
// Otherwise the JIT compiler cannot access m_data.
static const unsigned c_size = 1 << PACKED::c_totalBitCount;
float m_data[c_size];
};
//*************************************************************************
//
// Template definitions for Model<PACKED>
//
//*************************************************************************
template <typename PACKED>
Model<PACKED>::Model()
: m_data()
{
}
template <typename PACKED>
float Model<PACKED>::Apply(PACKED packed) const
{
return m_data[packed.m_bits];
}
template <typename PACKED>
float& Model<PACKED>::operator[](unsigned index)
{
return m_data[index];
}
template <typename PACKED>
float const & Model<PACKED>::operator[](unsigned index) const
{
return m_data[index];
}
template <typename PACKED>
float& Model<PACKED>::operator[](PACKED packed)
{
return m_data[packed.m_bits];
}
template <typename PACKED>
float const & Model<PACKED>::operator[](PACKED packed) const
{
return m_data[packed.m_bits];
}
}
``` | /content/code_sandbox/inc/NativeJIT/Model.h | objective-c | 2016-04-09T23:53:19 | 2024-06-29T07:05:56 | NativeJIT | BitFunnel/NativeJIT | 1,133 | 582 |
```objective-c
// Permission is hereby granted, free of charge, to any person obtaining a copy
// of this software and associated documentation files (the "Software"), to deal
// in the Software without restriction, including without limitation the rights
// to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
// copies of the Software, and to permit persons to whom the Software is
// furnished to do so, subject to the following conditions:
// The above copyright notice and this permission notice shall be included in
// all copies or substantial portions of the Software.
// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
// AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
// LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
// OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
// THE SOFTWARE.
#pragma once
#include <cstdint>
#include "NativeJIT/CodeGen/FunctionBuffer.h" // Emit<OP> referenced by template definition.
#include "NativeJIT/ExpressionTreeDecls.h" // ExpressionTree::Storage<T> parameter.
#include "Temporary/Assert.h" // LogThrowAssert() referenced by template definition.
namespace NativeJIT
{
namespace CodeGenHelpers
{
// Enums specifying whether the Emitter's helper method is operating
// on register and storage whose register types are of the same size
// and type or not and whether the immediate storage is allowed for input.
enum class RegTypes { ExactlySame, Different };
enum class ImmediateType { Allowed, NotAllowed };
// A helper class for the Emit() method to be specialized for different
// types of inputs.
template <RegTypes REGTYPES, ImmediateType IMMEDIATETYPE>
struct Emitter
{
// Emit from storage to register.
template <OpCode OP, typename DESTREGTYPE, typename SRC>
static void Emit(X64CodeGenerator& code,
DESTREGTYPE dest,
const ExpressionTree::Storage<SRC>& src);
// Emit from register to non-immediate storage.
template <OpCode OP, typename DEST, typename SRCREGTYPE>
static void Emit(X64CodeGenerator& code,
const ExpressionTree::Storage<DEST>& dest,
SRCREGTYPE src);
};
//
// Classes and methods that take Storage as the source.
//
// The Emit() method is used to Emit an opcode with the specified target
// register and source storage. Depending on the type of the storage,
// the correct flavor of X64CodeGenerator's Emit() method will be called
// (i.e. registers of same or mixed type/size, immediate flavor allowed
// or not). If the immediate flavor of the storage is not allowed and
// the client passes a storage of an immediate type, an assert is triggered.
template <OpCode OP, typename DESTREGTYPE, typename SRC>
void Emit(X64CodeGenerator& code, DESTREGTYPE dest, const ExpressionTree::Storage<SRC>& src)
{
typedef typename ExpressionTree::Storage<SRC>::DirectRegister SrcRegType;
// Pick the right flavor of the helper class specialization and call it.
const RegTypes regTypes = std::is_same<SrcRegType, DESTREGTYPE>::value
? RegTypes::ExactlySame
: RegTypes::Different;
const ImmediateType immediateType = CanBeInImmediateStorage<SRC>::value
? ImmediateType::Allowed
: ImmediateType::NotAllowed;
Emitter<regTypes, immediateType>::template Emit<OP>(code, dest, src);
}
// Storage and destination with registers with the same type and size,
// with support for immediates.
template <>
template <OpCode OP, typename DESTREGTYPE, typename SRC>
void Emitter<RegTypes::ExactlySame, ImmediateType::Allowed>::Emit(
X64CodeGenerator& code, DESTREGTYPE dest,
const ExpressionTree::Storage<SRC>& src)
{
switch (src.GetStorageClass())
{
case StorageClass::Immediate:
code.EmitImmediate<OP>(dest, src.GetImmediate());
break;
case StorageClass::Direct:
code.Emit<OP>(dest, src.GetDirectRegister());
break;
case StorageClass::Indirect:
code.Emit<OP>(dest, src.GetBaseRegister(), src.GetOffset());
break;
default:
LogThrowAbort("Invalid storage class.");
}
}
// Storage and destination with registers with the same type and size,
// with no support for immediates.
template <>
template <OpCode OP, typename DESTREGTYPE, typename SRC>
void Emitter<RegTypes::ExactlySame, ImmediateType::NotAllowed>::Emit(
X64CodeGenerator& code, DESTREGTYPE dest,
const ExpressionTree::Storage<SRC>& src)
{
switch (src.GetStorageClass())
{
case StorageClass::Direct:
code.Emit<OP>(dest, src.GetDirectRegister());
break;
case StorageClass::Indirect:
code.Emit<OP>(dest, src.GetBaseRegister(), src.GetOffset());
break;
default:
LogThrowAbort("Invalid storage class.");
}
}
// Storage and destination with registers with the mixed type and size,
// with support for immediates.
template <>
template <OpCode OP, typename DESTREGTYPE, typename SRC>
void Emitter<RegTypes::Different, ImmediateType::Allowed>::Emit(
X64CodeGenerator& code, DESTREGTYPE dest,
const ExpressionTree::Storage<SRC>& src)
{
typedef typename ExpressionTree::Storage<SRC>::DirectRegister SrcRegType;
switch (src.GetStorageClass())
{
case StorageClass::Immediate:
code.EmitImmediate<OP>(dest, src.GetImmediate());
break;
case StorageClass::Direct:
code.Emit<OP>(dest, src.GetDirectRegister());
break;
case StorageClass::Indirect:
code.Emit<OP,
DESTREGTYPE::c_size, DESTREGTYPE::c_isFloat,
SrcRegType::c_size, SrcRegType::c_isFloat>(
dest, src.GetBaseRegister(), src.GetOffset());
break;
default:
LogThrowAbort("Invalid storage class.");
}
}
// Storage and destination with registers with the mixed type and size,
// with no support for immediates.
template <>
template <OpCode OP, typename DESTREGTYPE, typename SRC>
void Emitter<RegTypes::Different, ImmediateType::NotAllowed>::Emit(
X64CodeGenerator& code, DESTREGTYPE dest,
const ExpressionTree::Storage<SRC>& src)
{
typedef typename ExpressionTree::Storage<SRC>::DirectRegister SrcRegType;
switch (src.GetStorageClass())
{
case StorageClass::Direct:
code.Emit<OP>(dest, src.GetDirectRegister());
break;
case StorageClass::Indirect:
code.Emit<OP,
DESTREGTYPE::c_size, DESTREGTYPE::c_isFloat,
SrcRegType::c_size, SrcRegType::c_isFloat>(
dest, src.GetBaseRegister(), src.GetOffset());
break;
default:
LogThrowAbort("Invalid storage class.");
}
}
// Places the constant float value into the target floating point
// register. Allocates and releases a temporary integer register in
// the process. This should be used only by the code which cannot
// use the ImmediateNode because it doesn't know the floating point
// value until the code generation time.
template <unsigned SIZE, typename T>
void MovThroughTemporary(ExpressionTree& tree, Register<SIZE, true> dest, T value)
{
static_assert(std::is_floating_point<T>::value, "The immediate must be a float.");
static_assert(sizeof(T) == SIZE, "The size of the immediate must match the register size.");
typedef typename std::conditional<SIZE == 4, uint32_t, uint64_t>::type TemporaryType;
auto & code = tree.GetCodeGenerator();
auto temp = tree.Direct<TemporaryType>();
auto r = temp.GetDirectRegister();
code.EmitImmediate<OpCode::Mov>(r, convertType<T, TemporaryType>(value));
code.Emit<OpCode::Mov>(dest, r);
}
//
// Classes and methods that take Storage as the destination.
//
// The Emit() method is used to Emit an opcode with the specified target
// storage and the source register. Depending on the type of the storage,
// the correct flavor of X64CodeGenerator's Emit() method will be called
// (i.e. registers of same or mixed type/size). Immediate storage is
// never allowed and triggers an assert.
template <OpCode OP, typename DEST, typename SRCREGTYPE>
void Emit(X64CodeGenerator& code,
const ExpressionTree::Storage<DEST>& dest,
SRCREGTYPE src)
{
typedef typename ExpressionTree::Storage<DEST>::DirectRegister DESTREGTYPE;
// Pick the right flavor of the helper class specialization and call it.
const RegTypes regTypes = std::is_same<SRCREGTYPE, DESTREGTYPE>::value
? RegTypes::ExactlySame
: RegTypes::Different;
Emitter<regTypes, ImmediateType::NotAllowed>::template Emit<OP>(code, dest, src);
}
// Storage and destination with registers with the same type and size.
template <>
template <OpCode OP, typename DEST, typename SRCREGTYPE>
void Emitter<RegTypes::ExactlySame, ImmediateType::NotAllowed>::Emit(
X64CodeGenerator& code,
const ExpressionTree::Storage<DEST>& dest,
SRCREGTYPE src)
{
switch (dest.GetStorageClass())
{
case StorageClass::Direct:
code.Emit<OP>(dest.GetDirectRegister(), src);
break;
case StorageClass::Indirect:
code.Emit<OP>(dest.GetBaseRegister(), dest.GetOffset(), src);
break;
default:
LogThrowAbort("Invalid storage class.");
}
}
// Storage and destination with registers with the mixed type and size.
template <>
template <OpCode OP, typename DEST, typename SRCREGTYPE>
void Emitter<RegTypes::Different, ImmediateType::NotAllowed>::Emit(
X64CodeGenerator& code,
const ExpressionTree::Storage<DEST>& dest,
SRCREGTYPE src)
{
typedef typename ExpressionTree::Storage<DEST>::DirectRegister DESTREGTYPE;
switch (dest.GetStorageClass())
{
case StorageClass::Direct:
code.Emit<OP>(dest.GetDirectRegister(), src);
break;
case StorageClass::Indirect:
code.Emit<OP,
DESTREGTYPE::c_size, DESTREGTYPE::c_isFloat,
SRCREGTYPE::c_size, SRCREGTYPE::c_isFloat>(
dest.GetBaseRegister(), dest.GetOffset(), src);
break;
default:
LogThrowAbort("Invalid storage class.");
}
}
}
}
``` | /content/code_sandbox/inc/NativeJIT/CodeGenHelpers.h | objective-c | 2016-04-09T23:53:19 | 2024-06-29T07:05:56 | NativeJIT | BitFunnel/NativeJIT | 1,133 | 2,419 |
```objective-c
// Permission is hereby granted, free of charge, to any person obtaining a copy
// of this software and associated documentation files (the "Software"), to deal
// in the Software without restriction, including without limitation the rights
// to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
// copies of the Software, and to permit persons to whom the Software is
// furnished to do so, subject to the following conditions:
// The above copyright notice and this permission notice shall be included in
// all copies or substantial portions of the Software.
// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
// AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
// LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
// OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
// THE SOFTWARE.
#pragma once
#include <cstdint>
#include <type_traits>
#include "NativeJIT/CodeGen/Register.h"
namespace NativeJIT
{
// A trait used to determine whether a type has any decay other than
// const/volatile.
template <typename T>
struct HasMeaningfulDecay
: std::integral_constant<
bool,
!std::is_same<typename std::remove_cv<T>::type,
typename std::decay<T>::type>
::value>
{
};
// Declares the properties of the type used for register storage.
template <typename T>
struct RegisterStorage
{
// The underlying type stored inside the register when passing the
// storage as an argument to a function. F. ex. references and large
// structures are passed as pointers. Any const/volatile qualifiers are
// removed.
// WARNING: Representation of a reference is implementation-specific.
// However, (almost?) all compilers implement it as a pointer.
typedef typename std::conditional<
std::is_reference<T>::value
|| (sizeof(T) > RegisterBase::c_maxSize),
typename std::add_pointer<typename std::remove_cv<T>::type>::type,
typename std::conditional<
HasMeaningfulDecay<T>::value,
typename std::decay<T>::type,
typename std::remove_cv<T>::type
>::type
>::type UnderlyingType;
static const unsigned c_size = sizeof(UnderlyingType);
static const bool c_isFloat = std::is_floating_point<UnderlyingType>::value;
typedef Register<c_size, c_isFloat> RegisterType;
};
// In the context of immediates that are emitted as parts of x64 instructions,
// there are three categories of types:
//
// 1. NonImmediate types cannot be immediates at all (void).
// 2. RIPRelativeImmediate types must be represented as RIP-relative indirects
// because there are no x64 instructions that support them as immediates
// (floating point values) or most x64 instructions don't support them as
// immediates (quadwords, including function pointers, things that decay
// to pointers such as arrays etc).
// 3. InlineImmediate types can be used directly as immediates in x64 instructions.
enum class ImmediateCategory { NonImmediate, RIPRelativeImmediate, InlineImmediate };
// Classifies types that belong to the RIPRelativeImmediate category.
template <typename T>
struct MustBeEncodedAsRIPRelative
: std::integral_constant<bool,
RegisterStorage<T>::c_isFloat
|| RegisterStorage<T>::c_size == 8
>
{
};
template <>
struct MustBeEncodedAsRIPRelative<void> : std::false_type {};
// Classifies types that belong to the InlineImmediate category in the list above.
template <typename T>
struct CanBeInImmediateStorage
: std::integral_constant<
bool,
std::is_same<typename RegisterStorage<T>::UnderlyingType,
typename std::remove_cv<T>::type>::value
&& !MustBeEncodedAsRIPRelative<T>::value
>
{
};
template <>
struct CanBeInImmediateStorage<void> : std::false_type {};
// Classifies types by ImmediateCategory.
template <typename T>
struct ImmediateCategoryOf
: std::integral_constant<ImmediateCategory,
CanBeInImmediateStorage<T>::value
? ImmediateCategory::InlineImmediate
: (MustBeEncodedAsRIPRelative<T>::value
? ImmediateCategory::RIPRelativeImmediate
: ImmediateCategory::NonImmediate)
>
{
};
// Determines the canonical C++ type that maps to a register type.
template <typename T>
struct CanonicalRegisterType;
template <> struct CanonicalRegisterType<Register<1, false>> { typedef uint8_t Type; };
template <> struct CanonicalRegisterType<Register<2, false>> { typedef uint16_t Type; };
template <> struct CanonicalRegisterType<Register<4, false>> { typedef uint32_t Type; };
template <> struct CanonicalRegisterType<Register<8, false>> { typedef uint64_t Type; };
template <> struct CanonicalRegisterType<Register<4, true>> { typedef float Type; };
template <> struct CanonicalRegisterType<Register<8, true>> { typedef double Type; };
// Determines the canonical C++ type that maps to a register storage needed
// for a type. F. ex. void*, a function pointer etc. map to uint64_t.
template <typename T>
struct CanonicalRegisterStorageType
{
typedef typename CanonicalRegisterType<
typename RegisterStorage<T>::RegisterType
>::Type Type;
};
// Specifies whether a type is a valid parameter/return type for a NativeJIT function.
template <typename T>
struct IsValidParameter
{
static const bool c_value
= std::is_arithmetic<T>::value
|| std::is_pointer<T>::value
|| std::is_reference<T>::value
|| (std::is_pod<T>::value
&& sizeof(T) <= RegisterBase::c_maxSize);
};
}
``` | /content/code_sandbox/inc/NativeJIT/TypePredicates.h | objective-c | 2016-04-09T23:53:19 | 2024-06-29T07:05:56 | NativeJIT | BitFunnel/NativeJIT | 1,133 | 1,345 |
```objective-c
// Permission is hereby granted, free of charge, to any person obtaining a copy
// of this software and associated documentation files (the "Software"), to deal
// in the Software without restriction, including without limitation the rights
// to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
// copies of the Software, and to permit persons to whom the Software is
// furnished to do so, subject to the following conditions:
// The above copyright notice and this permission notice shall be included in
// all copies or substantial portions of the Software.
// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
// AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
// LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
// OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
// THE SOFTWARE.
#pragma once
#include <cstdint>
#include "NativeJIT/CodeGen/X64CodeGenerator.h" // JccType.
#include "NativeJIT/ExpressionTreeDecls.h" // Base class.
#include "NativeJIT/Model.h" // Parameter.
#include "NativeJIT/Nodes/ImmediateNodeDecls.h" // Parameter too cumbersome to forward declare.
namespace NativeJIT
{
template <JccType JCC>
class FlagExpressionNode;
template <typename T>
class Node;
class NodeBase;
class ParameterSlotAllocator;
template <typename T>
class ParameterNode;
class ExpressionNodeFactory : public ExpressionTree
{
public:
ExpressionNodeFactory(Allocators::IAllocator& allocator, FunctionBuffer& code);
//
// Leaf nodes
//
template <typename T> ImmediateNode<T>& Immediate(T value);
template <typename T> ParameterNode<T>& Parameter(ParameterSlotAllocator& slotAllocator);
// See StackVariableNode for important information about stack variable
// lifetime.
template <typename T> Node<T&>& StackVariable();
//
// Unary operators
//
template <typename T> Node<T*>& AsPointer(Node<T&>& reference);
template <typename T> Node<T&>& AsReference(Node<T*>& pointer);
template <typename TO, typename FROM> Node<TO>& Cast(Node<FROM>& value);
// Casts that add or remove const from the node type.
// Note: enable_if is a workaround for the MSVC bug (falsely reported
// ambiguity between the two templates).
template <typename FROM> Node<FROM const>& AddConstCast(Node<FROM>& value);
template <typename FROM> Node<FROM>& RemoveConstCast(Node<FROM const>& value,
typename std::enable_if<!std::is_const<FROM>::value>::type* = nullptr);
template <typename FROM> Node<FROM&>& RemoveConstCast(Node<FROM const &>& value,
typename std::enable_if<std::is_const<FROM>::value>::type* = nullptr);
// Casts that add or remove const from the pointed-to target type.
template <typename FROM> Node<FROM const *>& AddTargetConstCast(Node<FROM*>& value);
template <typename FROM> Node<FROM*>& RemoveTargetConstCast(Node<FROM const *>& value);
template <typename T> Node<T>& Deref(Node<T*>& pointer);
template <typename T> Node<T>& Deref(Node<T*>& pointer, int32_t index);
template <typename T> Node<T>& Deref(Node<T&>& reference);
// Note: OBJECT1 is there to allow for template deduction in all cases
// since OBJECT may or may not be const, but OBJECT1 is never const
// in FieldPointer(someObjectNode, &SomeObject::m_field) expression.
// Otherwise, the following code would fail to compile:
//
// Node<SomeObject const *>& obj = ...;
// FieldPointer(obj, &SomeObject::m_field)
template <typename OBJECT, typename FIELD, typename OBJECT1 = OBJECT>
Node<FIELD*>& FieldPointer(Node<OBJECT*>& object, FIELD OBJECT1::*field);
// Note: even though it has two arguments, Dependent node is conceptually
// unary.
template <typename T> Node<T>& Dependent(Node<T>& dependentNode,
NodeBase& prerequisiteNode);
template <typename T> NodeBase& Return(Node<T>& value);
//
// Binary arithmetic operators
//
template <typename L, typename R> Node<L>& Add(Node<L>& left, Node<R>& right);
template <typename L, typename R> Node<L>& And(Node<L>& left, Node<R>& right);
template <typename L, typename R> Node<L>& Mul(Node<L>& left, Node<R>& right);
template <typename L, typename R> Node<L>& MulImmediate(Node<L>& left, R right);
template <typename L, typename R> Node<L>& Or(Node<L>& left, Node<R>& right);
template <typename L, typename R> Node<L>& Rol(Node<L>& left, R right);
template <typename L, typename R> Node<L>& Shl(Node<L>& left, R right);
template <typename L, typename R> Node<L>& Shr(Node<L>& left, R right);
template <typename L, typename R> Node<L>& Sub(Node<L>& left, Node<R>& right);
template <typename T, size_t SIZE, typename INDEX>
Node<T*>& Add(Node<T(*)[SIZE]>& array, Node<INDEX>& index);
template <typename T, typename INDEX> Node<T*>& Add(Node<T*>& array, Node<INDEX>& index);
//
// Ternary arithmetic operators
template <typename T>
Node<T>& Shld(Node<T>& shiftee, Node<T>& filler, uint8_t bitCount);
//
// Model related.
//
template <typename PACKED> Node<float>& ApplyModel(Node<Model<PACKED>*>& model, Node<PACKED>& packed);
//
// Relational operators
//
template <JccType JCC, typename T>
FlagExpressionNode<JCC>& Compare(Node<T>& left, Node<T>& right);
//
// Conditional operators
//
// WARNING: Both trueValue and falseValue are evaluated before testing the
// condition so both must be legal to evaluate regardless of the result
// of the condition. See the TODO note in ConditionalNode::CodeGenValue.
template <typename T, JccType JCC>
Node<T>& Conditional(FlagExpressionNode<JCC>& condition, Node<T>& trueValue, Node<T>& falseValue);
// WARNING: Both trueValue and falseValue are evaluated before testing the
// condition so both must be legal to evaluate regardless of the result
// of the condition. See the TODO note in ConditionalNode::CodeGenValue.
template <typename CONDT, typename T>
Node<T>& IfNotZero(Node<CONDT>& conditionValue, Node<T>& trueValue, Node<T>& falseValue);
// WARNING: Both thenValue and elseValue are evaluated before testing the
// condition so both must be legal to evaluate regardless of the result
// of the condition. See the TODO note in ConditionalNode::CodeGenValue.
template <typename T>
Node<T>& If(Node<bool>& conditionValue, Node<T>& thenValue, Node<T>& elseValue);
//
// Call node
//
template <typename R>
Node<R>& Call(Node<R (*)()>& function);
template <typename R, typename P1>
Node<R>& Call(Node<R (*)(P1)>& function, Node<P1>& param1);
template <typename R, typename P1, typename P2>
Node<R>& Call(Node<R (*)(P1, P2)>& function, Node<P1>& param1, Node<P2>& param2);
template <typename R, typename P1, typename P2, typename P3>
Node<R>& Call(Node<R (*)(P1, P2, P3)>& function,
Node<P1>& param1,
Node<P2>& param2,
Node<P3>& param3);
template <typename R, typename P1, typename P2, typename P3, typename P4>
Node<R>& Call(Node<R (*)(P1, P2, P3, P4)>& function,
Node<P1>& param1,
Node<P2>& param2,
Node<P3>& param3,
Node<P4>& param4);
//
// Packed operators
//
// TODO: use traits to ensure PACKED is a Packed type.
template <typename PACKED>
Node<PACKED>& PackedMax(Node<PACKED>& left, Node<PACKED>& right);
template <typename PACKED>
Node<PACKED>& PackedMin(Node<PACKED>& left, Node<PACKED>& right);
private:
template <OpCode OP, typename L, typename R> Node<L>& Binary(Node<L>& left, Node<R>& right);
template <OpCode OP, typename L, typename R> Node<L>& BinaryImmediate(Node<L>& left, R right);
};
}
``` | /content/code_sandbox/inc/NativeJIT/ExpressionNodeFactoryDecls.h | objective-c | 2016-04-09T23:53:19 | 2024-06-29T07:05:56 | NativeJIT | BitFunnel/NativeJIT | 1,133 | 1,993 |
```objective-c
// Permission is hereby granted, free of charge, to any person obtaining a copy
// of this software and associated documentation files (the "Software"), to deal
// in the Software without restriction, including without limitation the rights
// to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
// copies of the Software, and to permit persons to whom the Software is
// furnished to do so, subject to the following conditions:
// The above copyright notice and this permission notice shall be included in
// all copies or substantial portions of the Software.
// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
// AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
// LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
// OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
// THE SOFTWARE.
#pragma once
#include <cstdint>
#include <type_traits>
namespace NativeJIT
{
typedef uint32_t PackedUnderlyingType;
//*************************************************************************
// DESIGN NOTE
//
// The Packed class design makes some accomodations in order to simplify
// the NativeJIT code. In VS 2012 and VS 2013, the compiler uses a more
// complex calling convention when invoking a function whose return value
// is not a POD type as determined by Microsoft's implementation of
// std::is_pod.
//
// When the return type is not a POD, the first parameter of the function
// will be a pointer to caller-allocated storage for the return value, and
// the caller will assume that the function will return this pointer in RAX.
//
// When the return type is POD, its value is returned directly in RAX.
//
// The Microsoft implementation of std::is_pod is more restrictive than
// the C++11 definition. The Packed class design is impacted in, particular,
// by Microsoft's restriction on the use of private data members, base
// classes, and user defined constructors in POD type definitions.
//
// A cleaner design of Packed would make m_bits private, and probably
// move it to a base class common to all of the template specializations.
// The FromBits()/FromComponents() methods would be replaced by constructors
// with the same parameter list.
//
// Down the road, we may consider implementing support for non-POD
// return values in NativeJIT, but even if we do this, we may still want
// to keep Packed as POD for performance reasons.
//
//*************************************************************************
// This class and PackedMinMaxNode should probably move from NativeJIT to BitFunnel.Library.
// See bug#30.
// Retrieves the number of bits in the rightmost (last) component of the
// Packed<> type.
template <unsigned LEFT, unsigned... RIGHT>
struct PackedRightmost
{
// Defer the answer to the right portion of the parameter pack.
static const unsigned c_value = PackedRightmost<RIGHT...>::c_value;
};
// Base case.
template <unsigned LEFT>
struct PackedRightmost<LEFT>
{
static const unsigned c_value = LEFT;
};
// Packed<> with two or more components.
template <unsigned LEFT, unsigned... RIGHT>
struct Packed
{
typedef Packed<RIGHT...> Right;
static const unsigned c_componentCount = 1 + sizeof...(RIGHT);
static const unsigned c_totalBitCount = LEFT + Right::c_totalBitCount;
static const unsigned c_leftmostBitCount = LEFT;
static const unsigned c_rightmostBitCount = PackedRightmost<LEFT, RIGHT...>::c_value;
static_assert(c_totalBitCount <= sizeof(PackedUnderlyingType) * 8, "Too many bits in the packed.");
static Packed FromBits(PackedUnderlyingType value)
{
return Packed{value};
}
// Constructs a packed from its components.
template <typename T1, typename... ARGS>
static Packed FromComponents(T1 left, ARGS... args)
{
static_assert(1 + sizeof...(args) == c_componentCount,
"Invalid number of arguments in the constructor");
const auto right = Right::FromComponents(args...);
return right.template InsertLeftmost<LEFT>(left);
}
// Creates a new packed by adding an extra component at the left side.
template <unsigned LEFTMOST>
Packed<LEFTMOST, LEFT, RIGHT...> InsertLeftmost(PackedUnderlyingType value) const
{
const PackedUnderlyingType bits = (value << c_totalBitCount) | m_bits;
return Packed<LEFTMOST, LEFT, RIGHT...>::FromBits(bits);
}
// Creates a new packed by adding an extra component at the right side.
template <unsigned RIGHTMOST>
Packed<LEFT, RIGHT..., RIGHTMOST> InsertRightmost(PackedUnderlyingType value) const
{
const PackedUnderlyingType bits = (m_bits << RIGHTMOST) | value;
return Packed<LEFT, RIGHT..., RIGHTMOST>::FromBits(bits);
}
// Creates a new packed by removing the leftmost component.
Right WithoutLeftmost() const
{
return Right::FromBits(m_bits & ((1 << Right::c_totalBitCount) - 1));
}
// Returns the bits of the leftmost component shifted to the zero bit.
PackedUnderlyingType Leftmost() const
{
return m_bits >> Right::c_totalBitCount;
}
// Returns the bits of the rightmost component.
PackedUnderlyingType Rightmost() const
{
return m_bits & ((1 << c_rightmostBitCount) - 1);
}
operator PackedUnderlyingType() const
{
return m_bits;
}
PackedUnderlyingType m_bits;
};
// Packed<> with one component.
template <unsigned LEFT>
struct Packed<LEFT>
{
// Useful for clients to have different overrides if the Right type is void.
typedef void Right;
static const unsigned c_componentCount = 1;
static const unsigned c_totalBitCount = LEFT;
static const unsigned c_leftmostBitCount = LEFT;
static const unsigned c_rightmostBitCount = LEFT;
static_assert(c_totalBitCount <= sizeof(PackedUnderlyingType) * 8, "Too many bits in the packed.");
static Packed FromBits(PackedUnderlyingType value)
{
return Packed{value};
}
static Packed FromComponents(PackedUnderlyingType value)
{
return Packed{value};
}
template <unsigned LEFTMOST>
Packed<LEFTMOST, LEFT> InsertLeftmost(PackedUnderlyingType value) const
{
const PackedUnderlyingType bits = (value << c_totalBitCount) | m_bits;
return Packed<LEFTMOST, LEFT>::FromBits(bits);
}
template <unsigned RIGHTMOST>
Packed<LEFT, RIGHTMOST> InsertRightmost(PackedUnderlyingType value) const
{
const PackedUnderlyingType bits = (m_bits << RIGHTMOST) | value;
return Packed<LEFT, RIGHTMOST>::FromBits(bits);
}
PackedUnderlyingType Leftmost() const
{
return m_bits;
}
PackedUnderlyingType Rightmost() const
{
return m_bits;
}
operator PackedUnderlyingType() const
{
return m_bits;
}
PackedUnderlyingType m_bits;
};
}
``` | /content/code_sandbox/inc/NativeJIT/Packed.h | objective-c | 2016-04-09T23:53:19 | 2024-06-29T07:05:56 | NativeJIT | BitFunnel/NativeJIT | 1,133 | 1,689 |
```objective-c
// Permission is hereby granted, free of charge, to any person obtaining a copy
// of this software and associated documentation files (the "Software"), to deal
// in the Software without restriction, including without limitation the rights
// to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
// copies of the Software, and to permit persons to whom the Software is
// furnished to do so, subject to the following conditions:
// The above copyright notice and this permission notice shall be included in
// all copies or substantial portions of the Software.
// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
// AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
// LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
// OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
// THE SOFTWARE.
#pragma once
//
// Declaration includes - these includes must come before implementation includes.
//
#include "NativeJIT/ExpressionTreeDecls.h"
//
// Implementation includes
//
#include <algorithm> // For std::find.
#include <iostream> // Debugging output.
#include "NativeJIT/BitOperations.h"
#include "NativeJIT/CodeGen/CallingConvention.h"
#include "NativeJIT/CodeGenHelpers.h"
#include "NativeJIT/TypeConverter.h"
#include "NativeJIT/TypePredicates.h"
#include "Temporary/AllocatorOperations.h"
#include "Temporary/Assert.h"
#include "Temporary/NonCopyable.h"
namespace Allocators
{
class IAllocator;
}
namespace NativeJIT
{
//*************************************************************************
//
// Template definitions for ExpressionTree
//
//*************************************************************************
template <>
class ExpressionTree::FreeListForRegister<false>
{
public:
static auto Get(ExpressionTree& tree) -> decltype(tree.m_rxxFreeList) &
{
return tree.m_rxxFreeList;
}
};
template <>
class ExpressionTree::FreeListForRegister<true>
{
public:
static auto Get(ExpressionTree& tree) -> decltype(tree.m_xmmFreeList) &
{
return tree.m_xmmFreeList;
}
};
template <typename T>
typename Storage<T>::DirectRegister ExpressionTree::GetResultRegister()
{
return typename Storage<T>::DirectRegister(0);
}
template <typename T, typename... ConstructorArgs>
T& ExpressionTree::PlacementConstruct(ConstructorArgs&&... constructorArgs)
{
return Allocators::PlacementConstruct<T>(m_allocator,
std::forward<ConstructorArgs>(constructorArgs)...);
}
template <typename T>
ExpressionTree::Storage<T> ExpressionTree::Direct()
{
auto & freeList = FreeListForType<T>::Get(*this);
Storage<T> direct;
if (freeList.GetFreeCount() > 0)
{
direct = Storage<T>::ForAnyFreeRegister(*this);
}
else
{
const unsigned id = freeList.GetAllocatedSpillable();
direct = Direct<T>(typename Storage<T>::DirectRegister(id));
}
return direct;
}
template <typename T>
ExpressionTree::Storage<T>
ExpressionTree::Direct(typename Storage<T>::DirectRegister r)
{
typedef typename Storage<T>::FullRegister FullRegister;
auto & code = GetCodeGenerator();
auto & freeList = FreeListForType<T>::Get(*this);
LogThrowAssert(!IsPinned(r), "Attempted to obtain the pinned register %s", r.GetName());
unsigned src = r.GetId();
if (!freeList.IsAvailable(src))
{
typedef typename CanonicalRegisterType<FullRegister>::Type FullType;
// DESIGN NOTE: If the storage is indirect, FullType may not be the correct
// size. It will still get the right data due to the little endian
// architecture, but if the process doesn't have access to the
// additional bytes (f. ex. at the end of the allocated memory
// block) it will trigger access violation. See also the comment
// for the indirect Data constructor.
auto registerStorage = Storage<FullType>
::ForAdditionalReferenceToRegister(*this, FullRegister(src));
// Use another register if available or a temporary otherwise to
// bump the current contents of the register.
if (freeList.GetFreeCount() > 0)
{
auto destStorage = Storage<FullType>::ForAnyFreeRegister(*this);
CodeGenHelpers::Emit<OpCode::Mov>(code,
destStorage.GetDirectRegister(),
registerStorage);
// Swap storages for the target storage and for the register
// (including all the references to it). Once the destStorage
// variable goes out of scope, the register will be free.
registerStorage.Swap(destStorage, Storage<FullType>::SwapType::AllReferences);
}
else
{
// IMPORTANT: the spilling code must not affect and CPU flags
// since many nodes (e.g. ConditionalNode) assume that they
// can modify flags, allocate a register and then act on flags.
// The MOV instruction does not affect any flags.
//
// It is not possible to spill an indirect to stack in one
// step, so ensure that the source storage is direct.
// If it was previously indirect, its register will be reused
// because the conversion is not for modification and because
// the register is not one of the base registers.
registerStorage.ConvertToDirect(false);
auto fullReg = registerStorage.GetDirectRegister();
LogThrowAssert(fullReg.IsSameHardwareRegister(r),
"Converting %s to direct without modification should "
"not have moved into a different register (%s)",
r.GetName(),
fullReg.GetName());
// Make registerStorage the only owner. After it goes out of
// scope, the register will be free.
registerStorage.TakeSoleOwnershipOfDirect();
}
}
return Storage<T>::ForFreeRegister(*this, r);
}
template <typename T>
ExpressionTree::Storage<T> ExpressionTree::RIPRelative(int32_t offset)
{
return Storage<T>::ForSharedBaseRegister(*this, rip, offset);
}
template <typename T>
ExpressionTree::Storage<T> ExpressionTree::Temporary()
{
static_assert(sizeof(T) <= sizeof(void*),
"The size of the variable is too large.");
uint32_t slot;
if (m_temporaries.size() > 0)
{
// TODO: assert that m_temporaries is > 0?
slot = static_cast<uint32_t>(m_temporaries.back());
m_temporaries.pop_back();
}
else
{
// Note: FunctionSpecification will throw if too much stack gets allocated.
slot = m_temporaryCount++;
}
const int32_t offset = TemporarySlotToOffset(slot);
return Storage<T>::ForSharedBaseRegister(*this, GetBasePointer(), offset);
}
template <typename T>
ExpressionTree::Storage<T> ExpressionTree::Immediate(T value)
{
return Storage<T>::ForImmediate(*this, value);
}
template <unsigned SIZE>
void ExpressionTree::ReleaseRegister(Register<SIZE, false> r)
{
m_rxxFreeList.Release(r.GetId());
}
template <unsigned SIZE>
void ExpressionTree::ReleaseRegister(Register<SIZE, true> r)
{
m_xmmFreeList.Release(r.GetId());
}
template <unsigned SIZE, bool ISFLOAT>
bool ExpressionTree::IsPinned(Register<SIZE, ISFLOAT> reg)
{
auto & freeList = FreeListForRegister<ISFLOAT>::Get(*this);
return freeList.IsPinned(reg.GetId());
}
template <unsigned SIZE>
bool ExpressionTree::IsAnySharedBaseRegister(Register<SIZE, false> r) const
{
return IsBasePointer(PointerRegister(r))
|| r.IsRIP()
|| r.IsStackPointer();
}
template <unsigned SIZE>
bool ExpressionTree::IsAnySharedBaseRegister(Register<SIZE, true> /* r */) const
{
return false;
}
//*************************************************************************
//
// Template definitions for ExpressionTree::Data
//
//*************************************************************************
template <unsigned SIZE, bool ISFLOAT>
ExpressionTree::Data::Data(ExpressionTree& tree,
Register<SIZE, ISFLOAT> r)
: m_tree(tree),
m_storageClass(StorageClass::Direct),
m_isFloat(ISFLOAT),
m_registerId(r.GetId()),
m_offset(0),
m_refCount(0)
{
NotifyDataRegisterChange(RegisterChangeType::Initialize);
}
template <typename T>
ExpressionTree::Data::Data(ExpressionTree& tree,
T value)
: m_tree(tree),
m_storageClass(StorageClass::Immediate),
m_isFloat(false),
m_registerId(0),
m_offset(0),
m_refCount(0)
{
static_assert(CanBeInImmediateStorage<T>::value, "Invalid immediate type");
static_assert(sizeof(T) <= sizeof(m_immediate), "Unsupported type.");
m_immediate = convertType<T, size_t>(value);
// Note: no need to call NotifyDataRegisterChange() as this constructor
// doesn't apply to registers.
}
template <typename T>
T ExpressionTree::Data::GetImmediate() const
{
static_assert(CanBeInImmediateStorage<T>::value, "Invalid immediate type");
static_assert(sizeof(T) <= sizeof(m_immediate), "Unsupported type.");
LogThrowAssert(m_storageClass == StorageClass::Immediate, "GetImmediate() called for non-immediate storage!");
return convertType<size_t, T>(m_immediate);
}
template <bool ISFLOAT>
void ExpressionTree::Data::NotifyDataRegisterChange(RegisterChangeType type)
{
LogThrowAssert(m_storageClass != StorageClass::Immediate, "Invalid storage class");
auto & freeList = FreeListForRegister<ISFLOAT>::Get(m_tree);
switch (type)
{
case RegisterChangeType::Initialize:
// The free list doesn't need to keep data for indirects relative
// to shared base registers since there can be many of them for
// the same register.
if (!(m_storageClass == StorageClass::Indirect
&& IsSharedBaseRegister()))
{
freeList.InitializeData(m_registerId, this);
}
break;
case RegisterChangeType::Update:
// Only initialization is allowed for the direct shared registers.
LogThrowAssert(!(m_storageClass == StorageClass::Direct
&& IsSharedBaseRegister()),
"Cannot update data for shared register %u",
m_registerId);
// At this point, any reference to shared register is indirect
// and the free list doesn't need to know about such updates.
if (!IsSharedBaseRegister())
{
freeList.UpdateData(m_registerId, this);
}
break;
// clang warns on a default when all enum cases are covered.
// default:
// LogThrowAbort("Unknown register change type %u", type);
// break;
}
}
//*************************************************************************
//
// Template definitions for Storage<T>
//
//*************************************************************************
template <typename T>
ExpressionTree::Storage<T>::Storage()
: m_data(nullptr)
{
}
template <typename T>
template <typename U>
ExpressionTree::Storage<T>::Storage(const Storage<U>& other)
: m_data(nullptr)
{
SetData(other.m_data);
}
template <typename T>
ExpressionTree::Storage<T>::Storage(Storage<void*>&& base,
int32_t byteOffset)
: m_data(nullptr)
{
// Load the base pointer into a register.
base.ConvertToDirect(true);
// Dereference it.
base.m_data->ConvertDirectToIndirect(byteOffset);
// Transfer ownership of datablock to this Storage.
SetData(base.m_data);
base.Reset();
}
template <typename T>
Storage<T> ExpressionTree::Storage<T>::ForAdditionalReferenceToRegister(
ExpressionTree& tree,
DirectRegister reg)
{
auto & freeList = FreeListForType<T>::Get(tree);
LogThrowAssert(!freeList.IsAvailable(reg.GetId()),
"Register %s must already be allocated",
reg.GetName());
return Storage<T>(freeList.GetData(reg.GetId()));
}
template <typename T>
Storage<T> ExpressionTree::Storage<T>::ForAnyFreeRegister(ExpressionTree& tree)
{
auto & freeList = FreeListForType<T>::Get(tree);
Storage<T>::DirectRegister r(freeList.Allocate());
Data* data = &tree.PlacementConstruct<Data>(tree, r);
return Storage<T>(data);
}
template <typename T>
Storage<T> ExpressionTree::Storage<T>::ForFreeRegister(ExpressionTree& tree,
DirectRegister reg)
{
auto & freeList = FreeListForType<T>::Get(tree);
freeList.Allocate(reg.GetId());
Data* data = &tree.PlacementConstruct<Data>(tree, reg);
return Storage<T>(data);
}
template <typename T>
Storage<T> ExpressionTree::Storage<T>::ForSharedBaseRegister(
ExpressionTree& tree,
BaseRegister base,
int32_t offset)
{
LogThrowAssert(tree.IsAnySharedBaseRegister(base), "Register %s is not a shared base register", base.GetName());
return Storage<T>(&tree.PlacementConstruct<Data>(tree, base, offset));
}
template <typename T>
Storage<T> ExpressionTree::Storage<T>::ForImmediate(ExpressionTree& tree, T value)
{
return Storage<T>(&tree.PlacementConstruct<Data>(tree, value));
}
template <typename T>
template <typename U>
Storage<T> ExpressionTree::Storage<T>::AddressOfIndirect(Storage<U>&& indirect)
{
static_assert(std::is_pointer<T>::value, "T must be a pointer type");
static_assert(std::is_same<U, typename std::remove_pointer<T>::type>::value,
"U must be the type T points to");
// The storage being created.
Storage<T> target;
// Source information.
auto const base = indirect.GetBaseRegister();
auto const offset = indirect.GetOffset();
auto & tree = indirect.m_data->GetTree();
auto & code = tree.GetCodeGenerator();
// Reuse the base register if possible. Since the indirect argument
// is giving away the ownership, the register can be reused if that's
// the only reference to it and if it's not one of the special
// reserved/shared registers. Since T is a pointer type, the register
// it needs is compatible to indirect's base PointerRegister.
if (indirect.IsSoleDataOwner()
&& !tree.IsAnySharedBaseRegister(base))
{
// Get the address and convert the storage to indirect.
code.template Emit<OpCode::Lea>(base, base, offset);
indirect.m_data->ConvertIndirectToDirect();
target.SetData(indirect.m_data);
}
else
{
// Get a pin for the base register to make sure it doesn't get spilled
// by the target register allocation.
ReferenceCounter basePin = indirect.GetPin();
target = tree.template Direct<T>();
code.template Emit<OpCode::Lea>(target.GetDirectRegister(), base, offset);
}
// Take away ownership from the indirect storage.
indirect.Reset();
return target;
}
template <typename T>
ExpressionTree::Storage<T>::Storage(Storage const & other)
: m_data(nullptr)
{
SetData(other.m_data);
}
template <typename T>
ExpressionTree::Storage<T>& ExpressionTree::Storage<T>::operator=(Storage const & other)
{
SetData(other.m_data);
return *this;
}
template <typename T>
ExpressionTree::Storage<T>::Storage(ExpressionTree::Data* data)
: m_data(data)
{
m_data->Increment();
}
template <typename T>
ExpressionTree::Storage<T>::~Storage()
{
SetData(nullptr);
}
template <typename T>
void ExpressionTree::Storage<T>::Reset()
{
SetData(nullptr);
}
template <typename T>
bool ExpressionTree::Storage<T>::IsNull() const
{
return m_data == nullptr;
}
template <typename T>
bool ExpressionTree::Storage<T>::IsSoleDataOwner() const
{
return IsNull() || m_data->GetRefCount() == 1;
}
template <typename T>
StorageClass ExpressionTree::Storage<T>::GetStorageClass() const
{
return m_data->GetStorageClass();
}
template <typename T>
typename ExpressionTree::Storage<T>::DirectRegister ExpressionTree::Storage<T>::GetDirectRegister() const
{
LogThrowAssert(m_data->GetStorageClass() == StorageClass::Direct, "GetDirectRegister(): storage class must be direct.");
return DirectRegister(m_data->GetRegisterId());
}
template <typename T>
typename ExpressionTree::Storage<T>::BaseRegister ExpressionTree::Storage<T>::GetBaseRegister() const
{
LogThrowAssert(m_data->GetStorageClass() == StorageClass::Indirect, "GetBaseRegister(): storage class must be indirect.");
return BaseRegister(m_data->GetRegisterId());
}
template <typename T>
int32_t ExpressionTree::Storage<T>::GetOffset() const
{
LogThrowAssert(m_data->GetStorageClass() == StorageClass::Indirect, "GetOffset(): storage class must be indirect.");
return m_data->GetOffset();
}
template <typename T>
template <typename U, typename ENABLED>
U ExpressionTree::Storage<T>::GetImmediate() const
{
static_assert(std::is_same<T, U>::value, "U must not be specified explicitly");
LogThrowAssert(m_data->GetStorageClass() == StorageClass::Immediate, "GetImmediate(): storage class must be immediate.");
return m_data->GetImmediate<T>();
}
template <typename T>
typename ExpressionTree::Storage<T>::DirectRegister
ExpressionTree::Storage<T>::ConvertToDirect(bool forModification)
{
// DESIGN NOTE: Target the whole target register with MovZX to prevent the partial register stall.
// IMPORTANT: This method must not affect any CPU flags. See the comment
// in Direct(reg) method for more information.
auto & tree = m_data->GetTree();
auto & code = tree.GetCodeGenerator();
switch (m_data->GetStorageClass())
{
case StorageClass::Immediate:
ConvertImmediateToDirect(forModification, ImmediateFlavor());
break;
case StorageClass::Direct:
// If the storage is already direct, action is only necessary if it
// needs to be modified but we're not the sole owner.
if (!IsSoleDataOwner() && forModification)
{
auto dest = tree.Direct<T>();
// There's a possibility that the current register may get spilled
// by the allocation, so move from Storage instead of from register.
CodeGenHelpers::Emit<OpCode::Mov>(code,
dest.GetDirectRegister(),
*this);
SetData(dest);
}
break;
case StorageClass::Indirect:
{
BaseRegister base = GetBaseRegister();
// If we either fully own the storage or don't plan to make
// modifications, the type of the base register is compatible
// and it's not one of the reserved (shared) registers, then
// the base register can be reused.
if ((IsSoleDataOwner() || !forModification)
&& BaseRegister::c_isFloat == DirectRegister::c_isFloat
&& !tree.IsAnySharedBaseRegister(base))
{
code.Emit<OpCode::Mov>(DirectRegister(base), base, GetOffset());
m_data->ConvertIndirectToDirect();
}
else
{
// Otherwise, move the data to a newly allocated register,
// making sure that the base register doesn't get spilled.
Storage<T> dest;
{
ReferenceCounter basePin = GetPin();
dest = tree.Direct<T>();
}
code.Emit<OpCode::Mov>(dest.GetDirectRegister(), base, GetOffset());
// Let every owner benefit from moving to direct storage if
// possible. This is also necessary for the register to be
// fully released during spilling.
Swap(dest, forModification
? Storage<T>::SwapType::Single
: Storage<T>::SwapType::AllReferences);
}
}
break;
default:
LogThrowAbort("ConvertToDirect: invalid storage class.");
break;
}
return GetDirectRegister();
}
template <typename T>
void ExpressionTree::Storage<T>::ConvertImmediateToDirect(bool forModification, ValidImmediateStorage)
{
LogThrowAssert(m_data->GetStorageClass() == StorageClass::Immediate, "Unexpected storage class");
auto & tree = m_data->GetTree();
auto & code = tree.GetCodeGenerator();
// Allocate a register and load the immediate into it.
auto dest = tree.Direct<T>();
code.EmitImmediate<OpCode::Mov>(dest.GetDirectRegister(), m_data->GetImmediate<T>());
// Let every owner benefit from moving to direct storage if possible.
Swap(dest, forModification
? Storage<T>::SwapType::Single
: Storage<T>::SwapType::AllReferences);
}
template <typename T>
void ExpressionTree::Storage<T>::ConvertImmediateToDirect(bool /* forModification */, InvalidImmediateStorage)
{
// This should never be hit, it's impossible to compile an invalid immediate
// with StorageClass::Immediate.
LogThrowAssert(m_data->GetStorageClass() == StorageClass::Immediate, "Unexpected storage class");
LogThrowAbort("Unexpected occurrence of an invalid immediate storage");
}
template <typename T>
template <typename U>
void ExpressionTree::Storage<T>::Swap(Storage<U>& other, SwapType type)
{
switch (type)
{
case SwapType::Single:
std::swap(m_data, other.m_data);
break;
case SwapType::AllReferences:
m_data->SwapContents(other.m_data);
break;
default:
LogThrowAbort("Unknown swap type %u", type);
break;
}
}
template <typename T>
void ExpressionTree::Storage<T>::TakeSoleOwnershipOfDirect()
{
// IMPORTANT: This method must not affect any CPU flags. See the comment
// in Direct(reg) method for more information.
auto & tree = m_data->GetTree();
LogThrowAssert(GetStorageClass() == StorageClass::Direct,
"Unexpected storage class %u",
GetStorageClass());
LogThrowAssert(!tree.IsAnySharedBaseRegister(GetDirectRegister()),
"Cannot take sole ownership of %s",
GetDirectRegister().GetName());
if (!IsSoleDataOwner())
{
auto & freeList = FreeListForType<T>::Get(tree);
auto & code = tree.GetCodeGenerator();
typedef typename CanonicalRegisterType<FullRegister>::Type FullType;
// Use another register if available or a temporary otherwise to
// bump the full contents of the register.
Storage<FullType> destStorage
= freeList.GetFreeCount() > 0
? Storage<FullType>::ForAnyFreeRegister(tree)
: tree.Temporary<FullType>();
CodeGenHelpers::Emit<OpCode::Mov>(code,
destStorage,
FullRegister(GetDirectRegister().GetId()));
// After the swap, the destStorage variable will be the only one
// still referring to the original register.
Swap(destStorage, SwapType::AllReferences);
// Make this instance another owner of the register. The other one
// in stackStorage will go away after the closing brace.
*this = Storage<T>(destStorage);
}
}
template <typename T>
ReferenceCounter ExpressionTree::Storage<T>::GetPin()
{
LogThrowAssert(GetStorageClass() != StorageClass::Immediate,
"Cannot pin a register for immediate storage");
if (GetStorageClass() == StorageClass::Direct)
{
auto & freeList = FreeListForType<T>::Get(m_data->GetTree());
return freeList.GetPin(m_data->GetRegisterId());
}
else
{
auto & freeList = FreeListForRegister<false>::Get(m_data->GetTree());
return freeList.GetPin(m_data->GetRegisterId());
}
}
template <typename T>
void ExpressionTree::Storage<T>::SetData(ExpressionTree::Data* data)
{
// If the new data is different from the existing data ...
if (m_data != data)
{
// If there is existing data, decrement the ref count and release resources if zero.
if (!IsNull())
{
if (m_data->Decrement() == 0)
{
if (m_data->GetStorageClass() == StorageClass::Direct)
{
m_data->GetTree().ReleaseRegister(DirectRegister(m_data->GetRegisterId()));
}
else if (m_data->GetStorageClass() == StorageClass::Indirect)
{
BaseRegister base(m_data->GetRegisterId());
if (base.IsRIP())
{
// No need to release RIP-relative constant.
}
else if (m_data->GetTree().IsBasePointer(base))
{
m_data->GetTree().ReleaseIfTemporary(m_data->GetOffset());
}
else if (base.IsStackPointer())
{
// Nothing to release in this case.
// Note: this branch must be after the IsBasePointer()
// branch to also cover the cases when stack pointer
// is chosen to be the base pointer. For such cases,
// it's important that temporaries (which are based
// off base pointer) are released and the IsBasePointer()
// branch handles that.
}
else
{
// Release the base register.
m_data->GetTree().ReleaseRegister(base);
}
}
// Note: m_data intentionally not released as it's meant to
// be allocated and in-place constructed using arena allocator.
}
}
// Set the new data ptr and increment its ref count if applicable.
m_data = data;
if (m_data != nullptr)
{
m_data->Increment();
}
}
}
template <typename T>
void ExpressionTree::Storage<T>::SetData(Storage& other)
{
SetData(other.m_data);
}
template <typename T>
void ExpressionTree::Storage<T>::Print(std::ostream& out) const
{
switch (GetStorageClass())
{
case StorageClass::Direct:
out << "register " << GetDirectRegister().GetName();
break;
case StorageClass::Immediate:
PrintImmediate(out, ImmediateFlavor());
break;
case StorageClass::Indirect:
{
IosMiniStateRestorer state(out);
out << "indirect [" << GetBaseRegister().GetName() << std::uppercase << std::hex;
if (GetOffset() < 0)
{
out << " - " << -GetOffset() << "h";
}
else
{
out << " + " << GetOffset() << "h";
}
out << "]";
break;
}
default:
out << "[unknown storage type]";
break;
}
}
template <typename T>
void ExpressionTree::Storage<T>::PrintImmediate(std::ostream& out, ValidImmediateStorage) const
{
// Unary + causes integral promotion and char ([u]int8_t) would be
// printed as integer, as expected.
out << "immediate value " << +GetImmediate() << "h";
}
template <typename T>
void ExpressionTree::Storage<T>::PrintImmediate(std::ostream& /* out */, InvalidImmediateStorage) const
{
// This should never be hit, it's impossible to compile an invalid immediate
// with StorageClass::Immediate.
LogThrowAssert(m_data->GetStorageClass() == StorageClass::Immediate, "Unexpected storage class");
LogThrowAbort("Unexpected occurrence of an invalid immediate storage");
}
template <typename T>
template <typename U>
bool ExpressionTree::Storage<T>::operator==(Storage<U> const & other) const
{
return this->m_data == other.m_data;
}
//*************************************************************************
//
// template definitions for FreeList
//
//*************************************************************************
template <unsigned REGISTER_COUNT, bool ISFLOAT>
ExpressionTree::FreeList<REGISTER_COUNT, ISFLOAT>::FreeList(Allocators::IAllocator& allocator)
: m_usedMask(0),
m_lifetimeUsedMask(0),
m_volatileRegisterMask(ISFLOAT ?
CallingConvention::c_xmmVolatileRegistersMask :
CallingConvention::c_rxxVolatileRegistersMask),
m_nonVolatileRegisterMask(ISFLOAT ?
CallingConvention::c_xmmNonVolatileRegistersMask :
CallingConvention::c_rxxNonVolatileRegistersMask),
m_data(),
m_allocatedRegisters(Allocators::StlAllocator<uint8_t>(allocator)),
m_pinCount()
{
m_allocatedRegisters.reserve(REGISTER_COUNT);
}
template <unsigned REGISTER_COUNT, bool ISFLOAT>
void ExpressionTree::FreeList<REGISTER_COUNT, ISFLOAT>::AssertValidID(unsigned id) const
{
LogThrowAssert(id < REGISTER_COUNT, "Register %u is out of range.", id);
}
template <unsigned REGISTER_COUNT, bool ISFLOAT>
void ExpressionTree::FreeList<REGISTER_COUNT, ISFLOAT>::AssertValidData(unsigned id) const
{
AssertValidID(id);
AssertValidData(id, m_data[id]);
}
template <unsigned REGISTER_COUNT, bool ISFLOAT>
void ExpressionTree::FreeList<REGISTER_COUNT, ISFLOAT>::AssertValidData(unsigned id, Data* data) const
{
LogThrowAssert(data != nullptr, "Unexpected null data at/intended for register %u", id);
LogThrowAssert(data->GetStorageClass() != StorageClass::Immediate,
"Invalid storage class %u for data at/intended for register %u",
data->GetStorageClass(),
id);
LogThrowAssert(data->GetRegisterId() == id,
"Mismatched register ID %u for data at/intended for register %u",
data->GetRegisterId(),
id);
}
template <unsigned REGISTER_COUNT, bool ISFLOAT>
unsigned ExpressionTree::FreeList<REGISTER_COUNT, ISFLOAT>::GetFreeCount() const
{
return BitOp::GetNonZeroBitCount(GetFreeMask());
}
template <unsigned REGISTER_COUNT, bool ISFLOAT>
bool ExpressionTree::FreeList<REGISTER_COUNT, ISFLOAT>::IsAvailable(unsigned id) const
{
AssertValidID(id);
return BitOp::TestBit(GetFreeMask(), id);
}
template <unsigned REGISTER_COUNT, bool ISFLOAT>
unsigned ExpressionTree::FreeList<REGISTER_COUNT, ISFLOAT>::Allocate()
{
unsigned id;
const bool volatileRegisterFound =
BitOp::GetHighestBitSet(~m_usedMask & m_volatileRegisterMask, &id);
if (volatileRegisterFound)
{
Allocate(id);
return id;
}
else
{
const bool nonVolatileRegisterFound =
BitOp::GetHighestBitSet(~m_usedMask & m_nonVolatileRegisterMask, &id);
LogThrowAssert(nonVolatileRegisterFound, "No free registers available");
Allocate(id);
return id;
}
}
template <unsigned REGISTER_COUNT, bool ISFLOAT>
void ExpressionTree::FreeList<REGISTER_COUNT, ISFLOAT>::Allocate(unsigned id)
{
AssertValidID(id);
LogThrowAssert(BitOp::TestBit(GetFreeMask(), id), "Register %u must be free", id);
LogThrowAssert(!IsPinned(id), "Register %u must be unpined when free", id);
LogThrowAssert(m_data[id] == nullptr, "Data for register %u must be null", id);
m_allocatedRegisters.push_back(static_cast<uint8_t>(id));
BitOp::SetBit(&m_usedMask, id);
BitOp::SetBit(&m_lifetimeUsedMask, id);
}
template <unsigned REGISTER_COUNT, bool ISFLOAT>
void ExpressionTree::FreeList<REGISTER_COUNT, ISFLOAT>::Release(unsigned id)
{
AssertValidData(id);
LogThrowAssert(BitOp::TestBit(GetUsedMask(), id), "Register %u must be allocated", id);
LogThrowAssert(!IsPinned(id), "Register %u must be unpinned before release", id);
LogThrowAssert(m_data[id]->GetRefCount() == 0, "Reference count for register %u must be zero", id);
auto it = std::find(m_allocatedRegisters.begin(),
m_allocatedRegisters.end(),
static_cast<uint8_t>(id));
LogThrowAssert(it != m_allocatedRegisters.end(), "Couldn't find allocation record for %u", id);
m_allocatedRegisters.erase(it);
m_data[id] = nullptr;
BitOp::ClearBit(&m_usedMask, id);
}
template <unsigned REGISTER_COUNT, bool ISFLOAT>
void ExpressionTree::FreeList<REGISTER_COUNT, ISFLOAT>::InitializeData(unsigned id, Data* data)
{
AssertValidID(id);
LogThrowAssert(m_data[id] == nullptr, "Data for register %u must be clear", id);
AssertValidData(id, data);
m_data[id] = data;
}
template <unsigned REGISTER_COUNT, bool ISFLOAT>
void ExpressionTree::FreeList<REGISTER_COUNT, ISFLOAT>::UpdateData(unsigned id, Data* data)
{
AssertValidID(id);
LogThrowAssert(m_data[id] != nullptr, "Data for register %u must not be clear", id);
AssertValidData(id, data);
m_data[id] = data;
}
template <unsigned REGISTER_COUNT, bool ISFLOAT>
ExpressionTree::Data* ExpressionTree::FreeList<REGISTER_COUNT, ISFLOAT>::GetData(unsigned id) const
{
AssertValidData(id);
return m_data[id];
}
template <unsigned REGISTER_COUNT, bool ISFLOAT>
unsigned ExpressionTree::FreeList<REGISTER_COUNT, ISFLOAT>::GetUsedMask() const
{
return m_usedMask;
}
template <unsigned REGISTER_COUNT, bool ISFLOAT>
unsigned ExpressionTree::FreeList<REGISTER_COUNT, ISFLOAT>::GetLifetimeUsedMask() const
{
return m_lifetimeUsedMask;
}
template <unsigned REGISTER_COUNT, bool ISFLOAT>
unsigned ExpressionTree::FreeList<REGISTER_COUNT, ISFLOAT>::GetFreeMask() const
{
return ~m_usedMask & c_fullUsedMask;
}
template <unsigned REGISTER_COUNT, bool ISFLOAT>
unsigned ExpressionTree::FreeList<REGISTER_COUNT, ISFLOAT>::GetAllocatedSpillable() const
{
unsigned pinnedCount = 0;
bool found = false;
unsigned foundId = 0;
// Start looking from the oldest allocated register. This is expected
// to give best results as recently allocated registers are more likely
// to be needed in the code that's currently being compiled.
for (unsigned id : m_allocatedRegisters)
{
if (IsPinned(id))
{
pinnedCount++;
}
else
{
found = true;
foundId = id;
break;
}
}
LogThrowAssert(found,
"Couldn't find any registers for spilling: %u registers "
"allocated, %u of those are pinned",
static_cast<unsigned>(m_allocatedRegisters.size()),
pinnedCount);
return foundId;
}
template <unsigned REGISTER_COUNT, bool ISFLOAT>
ReferenceCounter
ExpressionTree::FreeList<REGISTER_COUNT, ISFLOAT>::GetPin(unsigned id)
{
AssertValidID(id);
LogThrowAssert(BitOp::TestBit(GetUsedMask(), id), "Register %u must be allocated to be pinned", id);
AssertValidData(id);
return ReferenceCounter(m_pinCount[id]);
}
template <unsigned REGISTER_COUNT, bool ISFLOAT>
bool ExpressionTree::FreeList<REGISTER_COUNT, ISFLOAT>::IsPinned(unsigned id) const
{
AssertValidID(id);
return m_pinCount[id] != 0;
}
}
``` | /content/code_sandbox/inc/NativeJIT/ExpressionTree.h | objective-c | 2016-04-09T23:53:19 | 2024-06-29T07:05:56 | NativeJIT | BitFunnel/NativeJIT | 1,133 | 7,951 |
```objective-c
// Permission is hereby granted, free of charge, to any person obtaining a copy
// of this software and associated documentation files (the "Software"), to deal
// in the Software without restriction, including without limitation the rights
// to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
// copies of the Software, and to permit persons to whom the Software is
// furnished to do so, subject to the following conditions:
// The above copyright notice and this permission notice shall be included in
// all copies or substantial portions of the Software.
// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
// AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
// LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
// OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
// THE SOFTWARE.
#pragma once
#include <cstdint>
#include <iosfwd> // Diagnostic stream parameter.
#include "NativeJIT/AllocatorVector.h" // Embedded member.
namespace NativeJIT
{
struct UnwindInfo;
class X64CodeGenerator;
// A class that builds function specification in the form of unwind info,
// prolog and epilog code. These are built from description of function's
// behavior (see constructor parameters for more information).
class FunctionSpecification
{
public:
// Specifies whether/how to set-up the base register. Unused means
// that no base register will be set up. SetRbpToOriginalRsp will make
// RBP reserved and set its value to the value that RSP had before the
// first instruction of the prolog started executing.
enum class BaseRegisterType { Unused, SetRbpToOriginalRsp };
// The maximum size for the unwind buffer that needs to be reserved
// if the number of unwind codes is not known in advance.
// DESIGN NOTE: not defined inline to avoid inclusion of UnwindCode.h.
static const unsigned c_maxUnwindInfoBufferSize;
// The maximum size needed to reserve for prolog or epilog code buffer.
// Larger values allow for more extreme prolog sizes, but lead to more
// wasted space in common case (in the scenario when prolog space is
// reserved and then filled in). Close to 144 bytes is needed when all
// 8 RXX (plus RSP separately) and 10 XMM non-volatiles need to be saved.
static const size_t c_maxPrologOrEpilogSize = 144;
static_assert(c_maxPrologOrEpilogSize <= 256,
"Prolog/epilog cannot be larger than 256 bytes");
// A value larger than 4096 would require the generated code to call _chkstk.
static const unsigned c_maxStackSize = 4096;
static_assert(c_maxStackSize <= 4096, "Cannot have stack larger than 4096 bytes");
// Builds unwind info, prolog and epilog code from the information about
// function's behavior: maximum number of parameters for the functions
// that it calls (negative for none), the number of stack slots to
// reserve for function variables, the set of RXX and XMM registers to
// save/resetore in prolog/epilog and whether to set-up the base register
// and how.
//
// If BaseRegisterType is SetRbpToOriginalRsp, [rbp] holds the return
// address, [rbp + 8] home for function's first argument etc, whereas
// [rbp - 8] holds the first stacj variable etc. This setup allows well
// defined access to parameters and stack variables during function
// body generation time, even if the number of required stack slots is
// not known yet.
//
// If diagnosticStream is non-null, it will be used to print x64
// instructions used for prolog and epilog.
FunctionSpecification(Allocators::IAllocator& allocator,
int maxFunctionCallParameters,
unsigned localStackSlotCount,
unsigned savedRxxNonVolatilesMask,
unsigned savedXmmNonVolatilesMask,
BaseRegisterType baseRegisterType,
std::ostream* diagnosticStream);
// Returns the offset that can be added to the current RSP to get the
// value of RSP that was effective before the prolog started executing.
// This offset can then be used to access the return address as
// [rsp + offset], function parameters as [rsp + offset + 8] etc. or
// stack variables as [rsp + offset - 8] etc.
int32_t GetOffsetToOriginalRsp() const;
// Returns a pointer to the unwind info data and its length.
uint8_t const * GetUnwindInfoBuffer() const;
unsigned GetUnwindInfoByteLength() const;
// Returns a pointer to the prolog code and its length.
uint8_t const * GetProlog() const;
unsigned GetPrologLength() const;
// Returns a pointer to the epilog code and its length.
uint8_t const * GetEpilog() const;
unsigned GetEpilogLength() const;
private:
// Builds unwind info and prolog code from the information about
// function's behavior. The prolog code and unwind info are built into
// the two provided buffers.
// DESIGN NOTE: Conceptually, it makes most sense to first build UnwindInfo
// and then build prolog from it. However, unwind info and prolog code
// are tightly coupled since offsets to prolog instructions need to be
// specified in unwind codes. Also, some instructions not directly
// corresponding to unwind codes may be included in prolog (e.g. setting
// up of RBP).
static void BuildUnwindInfoAndProlog(int maxFunctionCallParameters,
unsigned localStackSlotCount,
unsigned savedRxxNonVolatilesMask,
unsigned savedXmmNonVolatilesMask,
BaseRegisterType baseRegisterType,
// Out parameters:
X64CodeGenerator& prologCode,
AllocatorVector<uint8_t>& unwindInfoBuffer,
int32_t& m_offsetToOriginalRsp);
// Uses the unwind information to generate epilog code into the current
// position of the provided code generator.
static void BuildEpilog(UnwindInfo const & unwindInfo,
X64CodeGenerator& epilogCode);
// Need to save at most 8 RXX and 10 XMM non-volatiles. Each save takes
// 2 codes for a total of 36 codes. Additionally, at most 2 codes to
// allocate stack space.
static const unsigned c_maxUnwindCodes = 38;
static_assert((c_maxUnwindCodes % 2) == 0, "Must have an even number of max unwind codes for alignment");
static_assert(c_maxUnwindCodes <= 256, "Cannot have more than 256 unwind codes");
// Offset to add to RSP after it's modified in prolog to get the value
// of RSP before prolog started executing.
int32_t m_offsetToOriginalRsp;
Allocators::StlAllocator<uint8_t> m_stlAllocator;
AllocatorVector<uint8_t> m_unwindInfoBuffer;
AllocatorVector<uint8_t> m_prologCode;
AllocatorVector<uint8_t> m_epilogCode;
};
}
``` | /content/code_sandbox/inc/NativeJIT/CodeGen/FunctionSpecification.h | objective-c | 2016-04-09T23:53:19 | 2024-06-29T07:05:56 | NativeJIT | BitFunnel/NativeJIT | 1,133 | 1,649 |
```objective-c
// Permission is hereby granted, free of charge, to any person obtaining a copy
// of this software and associated documentation files (the "Software"), to deal
// in the Software without restriction, including without limitation the rights
// to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
// copies of the Software, and to permit persons to whom the Software is
// furnished to do so, subject to the following conditions:
// The above copyright notice and this permission notice shall be included in
// all copies or substantial portions of the Software.
// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
// AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
// LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
// OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
// THE SOFTWARE.
#pragma once
#include <cstdint>
#include <type_traits>
#include "NativeJIT/TypeConverter.h"
namespace NativeJIT
{
// Function overloads returns the byte sizes of various types.
// Used by X64CodeGenerator::Group1() template definition.
unsigned Size(uint8_t);
unsigned Size(uint16_t value);
unsigned Size(uint32_t value);
unsigned Size(uint64_t value);
unsigned Size(int8_t);
unsigned Size(int16_t value);
unsigned Size(int32_t value);
unsigned Size(int64_t value);
// Cast using a static_cast for convertible immediates.
template <typename TO, typename FROM>
TO ForcedCast(FROM from,
typename std::enable_if<std::is_convertible<FROM, TO>::value>::type* = nullptr)
{
return static_cast<TO>(from);
}
// Cast using a reinterpret_cast for non-convertible immediates of the
// same size.
template <typename TO, typename FROM>
TO ForcedCast(FROM from,
typename std::enable_if<!std::is_convertible<FROM, TO>::value>::type* = nullptr)
{
static_assert(sizeof(FROM) == sizeof(TO),
"Cannot do a forced cast between incompatible types of different sizes");
return convertType<FROM, TO>(from);
}
}
``` | /content/code_sandbox/inc/NativeJIT/CodeGen/ValuePredicates.h | objective-c | 2016-04-09T23:53:19 | 2024-06-29T07:05:56 | NativeJIT | BitFunnel/NativeJIT | 1,133 | 507 |
```objective-c
// Permission is hereby granted, free of charge, to any person obtaining a copy
// of this software and associated documentation files (the "Software"), to deal
// in the Software without restriction, including without limitation the rights
// to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
// copies of the Software, and to permit persons to whom the Software is
// furnished to do so, subject to the following conditions:
// The above copyright notice and this permission notice shall be included in
// all copies or substantial portions of the Software.
// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
// AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
// LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
// OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
// THE SOFTWARE.
#pragma once
#include "NativeJIT/CodeGen/CodeBuffer.h" // Embedded class.
#include "Temporary/IAllocator.h"
namespace NativeJIT
{
class CodeBuffer;
struct UnwindInfo;
struct UnwindCode;
class ExecutionBuffer : public Allocators::IAllocator
{
public:
ExecutionBuffer(size_t bufferSize);
virtual ~ExecutionBuffer() override;
//
// IAllocator methods
//
// Allocates a block of a specified byte size.
virtual void* Allocate(size_t size) override;
// Frees a block.
virtual void Deallocate(void* block) override;
// Returns the maximum legal allocation size in bytes.
virtual size_t MaxSize() const override;
// Frees all blocks that have been allocated since construction or the
// last call to Reset().
virtual void Reset() override;
private:
void DebugInitialize();
size_t m_bufferSize;
size_t m_bytesAllocated;
unsigned char* m_buffer;
};
}
``` | /content/code_sandbox/inc/NativeJIT/CodeGen/ExecutionBuffer.h | objective-c | 2016-04-09T23:53:19 | 2024-06-29T07:05:56 | NativeJIT | BitFunnel/NativeJIT | 1,133 | 435 |
```objective-c
// Permission is hereby granted, free of charge, to any person obtaining a copy
// of this software and associated documentation files (the "Software"), to deal
// in the Software without restriction, including without limitation the rights
// to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
// copies of the Software, and to permit persons to whom the Software is
// furnished to do so, subject to the following conditions:
// The above copyright notice and this permission notice shall be included in
// all copies or substantial portions of the Software.
// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
// AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
// LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
// OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
// THE SOFTWARE.
#pragma once
#include <cstdint>
#include <type_traits>
#include "Temporary/Assert.h"
namespace NativeJIT
{
class RegisterBase
{
public:
static const unsigned c_maxSize = 8;
static const unsigned c_maxIntegerRegisterID = 16;
static const unsigned c_maxFloatRegisterID = 15;
protected:
static const unsigned c_maxRegisterID = 16;
static const unsigned c_validSizesCount = 4;
static const unsigned c_typesCount = 2;
// Add 1 to adjust for the fact that array is zero based, unlike size.
static unsigned c_sizes[c_maxSize + 1];
static char const * c_names[c_typesCount][c_validSizesCount][c_maxRegisterID + 1];
};
template <unsigned SIZE, bool ISFLOAT>
class Register : public RegisterBase
{
public:
static_assert((ISFLOAT == 0 && (SIZE == 1 || SIZE == 2 || SIZE == 4 || SIZE == 8))
|| (ISFLOAT == 1 && (SIZE == 4 || SIZE == 8)),
"Invalid register definition.");
typedef Register<c_maxSize, ISFLOAT> FullRegister;
// Templates that don't explicitly receive SIZE and ISFLOAT but rather
// have access to a Register need to have a way to access the size and
// type, so provide them here.
static const unsigned c_size = SIZE;
static const bool c_isFloat = ISFLOAT;
Register()
: m_id(0)
{
}
explicit Register(unsigned id)
: m_id(id)
{
LogThrowAssert((!ISFLOAT && id <= c_maxIntegerRegisterID)
|| (ISFLOAT && id <= c_maxFloatRegisterID),
"Invalid register id.");
}
template <unsigned SIZE2>
explicit Register(Register<SIZE2, false> r)
: m_id(r.GetId())
{
}
unsigned GetId() const
{
return m_id;
}
// Returns the lower three bits of the ID. Equivalent to GetId() for
// non-extended registers.
uint8_t GetId8() const
{
return m_id & 7;
}
unsigned GetMask() const
{
return 1 << m_id;
}
// Returns whether the register belongs to the set of extended registers
// in the long mode (i.e. r8, xmm8 etc).
bool IsExtended() const
{
return m_id > 7;
}
char const * GetName() const
{
char const * name = c_names[ISFLOAT ? 1 : 0][c_sizes[SIZE]][m_id];
LogThrowAssert(name != nullptr, "Attempting to get name for invalid register.");
return name;
}
// Returns whether the registers are exactly the same (size, type and ID).
// Thus, this will return false for comparison between f. ex. rax and eax.
template <unsigned SIZE2,
bool ISFLOAT2,
typename std::enable_if<SIZE != SIZE2 || ISFLOAT != ISFLOAT2>::type * = nullptr>
bool operator==(Register<SIZE2, ISFLOAT2> /* other */) const
{
return false;
}
template <unsigned SIZE2,
bool ISFLOAT2,
typename std::enable_if<SIZE == SIZE2 && ISFLOAT == ISFLOAT2>::type * = nullptr>
bool operator==(Register<SIZE2, ISFLOAT2> other) const
{
return GetId() == other.GetId();
}
// Returns whether the two registers have the same type and ID.
// This will return true for comparison between f. ex. rax and eax but
// false for comparison between rax and xmm0 (even though they have the
// same register ID).
template <unsigned SIZE2, bool ISFLOAT2>
bool IsSameHardwareRegister(Register<SIZE2, ISFLOAT2> other) const
{
return other.GetId() == GetId()
&& ISFLOAT2 == ISFLOAT;
}
bool IsRIP() const;
bool IsStackPointer() const;
protected:
unsigned m_id;
};
typedef Register<sizeof(void*), false> PointerRegister;
// Need to avoid "static initialization order fiasco" for register definitions.
// See path_to_url
// Plan is to use constexpr when VS2013 becomes available to Bing build.
// See bug#24.
extern Register<1, false> al;
extern Register<1, false> cl;
extern Register<1, false> dl;
extern Register<1, false> bl;
extern Register<1, false> spl;
extern Register<1, false> bpl;
extern Register<1, false> sil;
extern Register<1, false> dil;
extern Register<1, false> r8b;
extern Register<1, false> r9b;
extern Register<1, false> r10b;
extern Register<1, false> r11b;
extern Register<1, false> r12b;
extern Register<1, false> r13b;
extern Register<1, false> r14b;
extern Register<1, false> r15b;
extern Register<2, false> ax;
extern Register<2, false> cx;
extern Register<2, false> dx;
extern Register<2, false> bx;
extern Register<2, false> sp;
extern Register<2, false> bp;
extern Register<2, false> si;
extern Register<2, false> di;
extern Register<2, false> r8w;
extern Register<2, false> r9w;
extern Register<2, false> r10w;
extern Register<2, false> r11w;
extern Register<2, false> r12w;
extern Register<2, false> r13w;
extern Register<2, false> r14w;
extern Register<2, false> r15w;
extern Register<4, false> eax;
extern Register<4, false> ecx;
extern Register<4, false> edx;
extern Register<4, false> ebx;
extern Register<4, false> esp;
extern Register<4, false> ebp;
extern Register<4, false> esi;
extern Register<4, false> edi;
extern Register<4, false> r8d;
extern Register<4, false> r9d;
extern Register<4, false> r10d;
extern Register<4, false> r11d;
extern Register<4, false> r12d;
extern Register<4, false> r13d;
extern Register<4, false> r14d;
extern Register<4, false> r15d;
extern Register<8, false> rax;
extern Register<8, false> rcx;
extern Register<8, false> rdx;
extern Register<8, false> rbx;
extern Register<8, false> rsp;
extern Register<8, false> rbp;
extern Register<8, false> rsi;
extern Register<8, false> rdi;
extern Register<8, false> r8;
extern Register<8, false> r9;
extern Register<8, false> r10;
extern Register<8, false> r11;
extern Register<8, false> r12;
extern Register<8, false> r13;
extern Register<8, false> r14;
extern Register<8, false> r15;
extern Register<8, false> rip;
extern Register<4, true> xmm0s;
extern Register<4, true> xmm1s;
extern Register<4, true> xmm2s;
extern Register<4, true> xmm3s;
extern Register<4, true> xmm4s;
extern Register<4, true> xmm5s;
extern Register<4, true> xmm6s;
extern Register<4, true> xmm7s;
extern Register<4, true> xmm8s;
extern Register<4, true> xmm9s;
extern Register<4, true> xmm10s;
extern Register<4, true> xmm11s;
extern Register<4, true> xmm12s;
extern Register<4, true> xmm13s;
extern Register<4, true> xmm14s;
extern Register<4, true> xmm15s;
extern Register<8, true> xmm0;
extern Register<8, true> xmm1;
extern Register<8, true> xmm2;
extern Register<8, true> xmm3;
extern Register<8, true> xmm4;
extern Register<8, true> xmm5;
extern Register<8, true> xmm6;
extern Register<8, true> xmm7;
extern Register<8, true> xmm8;
extern Register<8, true> xmm9;
extern Register<8, true> xmm10;
extern Register<8, true> xmm11;
extern Register<8, true> xmm12;
extern Register<8, true> xmm13;
extern Register<8, true> xmm14;
extern Register<8, true> xmm15;
// IsRIP() and IsStackPointer() were moved after definitions of rip and rsp
// to prevent a compile error in clang.
template <unsigned SIZE, bool ISFLOAT>
bool Register<SIZE, ISFLOAT>::IsRIP() const
{
return IsSameHardwareRegister(rip);
}
template <unsigned SIZE, bool ISFLOAT>
bool Register<SIZE, ISFLOAT>::IsStackPointer() const
{
return IsSameHardwareRegister(rsp);
}
}
``` | /content/code_sandbox/inc/NativeJIT/CodeGen/Register.h | objective-c | 2016-04-09T23:53:19 | 2024-06-29T07:05:56 | NativeJIT | BitFunnel/NativeJIT | 1,133 | 2,384 |
```objective-c
// Permission is hereby granted, free of charge, to any person obtaining a copy
// of this software and associated documentation files (the "Software"), to deal
// in the Software without restriction, including without limitation the rights
// to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
// copies of the Software, and to permit persons to whom the Software is
// furnished to do so, subject to the following conditions:
// The above copyright notice and this permission notice shall be included in
// all copies or substantial portions of the Software.
// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
// AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
// LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
// OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
// THE SOFTWARE.
#pragma once
// path_to_url
// path_to_url
// path_to_url
#include <ostream> // Debugging output.
#include "NativeJIT/BitOperations.h"
#include "NativeJIT/CodeGen/CodeBuffer.h" // Inherits from CodeBuffer.
#include "NativeJIT/CodeGen/ValuePredicates.h" // Called by template code.
#include "NativeJIT/CodeGen/Register.h" // Register parameter.
#include "Temporary/NonCopyable.h" // Inherits from NonCopyable.
#ifdef _MSC_VER
// Supress warning about constant expression involving template parameters.
#pragma warning(push)
#pragma warning(disable:4127)
#endif
namespace Allocators
{
class IAllocator;
}
namespace NativeJIT
{
// WARNING: When modifying JccType, be sure to also modify the function JccName().
enum class JccType : unsigned
{
JO = 0,
JNO = 1,
JB = 2,
JAE = 3, JNB = 3, JNC = 3,
JE = 4, JZ = 4,
JNE = 5, JNZ = 5,
JBE = 6, JNA = 6,
JA = 7, JNBE = 7,
JS = 8,
JNS = 9,
JP = 0xa, JPE = 0xa,
JNP = 0xb, JPO = 0xb,
JL = 0xc, JNGE = 0xc,
JNL = 0xd, JGE = 0xd,
JLE = 0xe, JNG = 0xe,
JNLE = 0xf, JG = 0xf,
// The following value must be the last one.
JccCount
};
// WARNING: When modifying OpCode, be sure to also modify the function OpCodeName().
enum class OpCode : unsigned
{
Add,
And,
Bsf,
Bsr,
Bt,
Btc,
Btr,
Bts,
Call,
Cmp,
CvtFP2FP,
CvtFP2SI,
CvtSI2FP,
Dec,
IMul,
Inc,
Lea,
Mov,
MovSX,
MovZX,
MovAP, // Aligned 128-bit SSE move.
Neg,
Nop,
Not,
Or,
Pop,
Push,
Rep,
Ret,
Rol,
Shl, // Note: Shl and Sal are aliases, unlike Shr and Sar.
Shld,
Shr,
Stosq,
Sub,
Xor,
// The following value must be the last one.
OpCodeCount
};
enum class SIB : uint8_t
{
Scale1 = 0,
Scale2 = 1,
Scale4 = 2,
Scale8 = 3
};
class X64CodeGenerator : public CodeBuffer
{
public:
// Sets up a code buffer with specified capacity. See the CodeBuffer
// constructor for more details on the allocator.
X64CodeGenerator(Allocators::IAllocator& codeAllocator, unsigned capacity);
void EnableDiagnostics(std::ostream& out);
void DisableDiagnostics();
// Returns the diagnostic stream. GetDiagnosticsStream() throws if it is not available.
bool IsDiagnosticsStreamAvailable() const;
std::ostream& GetDiagnosticsStream() const;
// This override allows for printing of debugging information.
virtual void PlaceLabel(Label l) override;
void Call(Label l);
void Jmp(Label l);
void Jmp(void* functionPtr);
// These two methods are public in order to allow access for BinaryNode debugging text.
static char const * OpCodeName(OpCode op);
static char const * JccName(JccType jcc);
//
// X64 opcode emit methods.
//
// Note: the name of this method was changed from Emit() to work around
// an internal compiler error in VisualStudio 2013 (VC12). The ICE was
// fixed in VisualStudio 2015.
template <JccType JCC>
void EmitConditionalJump(Label l);
// No operand (e.g nop, ret)
template <OpCode OP>
void Emit();
// One register operand (e.g. call, neg, not, push, pop)
template <OpCode OP, unsigned SIZE, bool ISFLOAT>
void Emit(Register<SIZE, ISFLOAT> dest);
// Two register operands with the same type and size (e.g. and, mov, or, sub).
template <OpCode OP, unsigned SIZE, bool ISFLOAT>
void Emit(Register<SIZE, ISFLOAT> dest, Register<SIZE, ISFLOAT> src);
// Base register and offset.
template <OpCode OP, unsigned SIZE>
void Emit(Register<8u, false> dest, int32_t offset);
// Two register operands with different type and/or size (f. ex. movzx).
template <OpCode OP, unsigned SIZE1, bool ISFLOAT1, unsigned SIZE2, bool ISFLOAT2>
void Emit(Register<SIZE1, ISFLOAT1> dest, Register<SIZE2, ISFLOAT2> src);
// Two operands - register destination and indirect source with the same
// type and size.
template <OpCode OP, unsigned SIZE, bool ISFLOAT>
void Emit(Register<SIZE, ISFLOAT> dest, Register<8, false> src, int32_t srcOffset);
// Two operands - register destination and indirect source. This flavor
// of the method is used for instructions which can read values of a
// varying size from the source address. F. ex. movzx with 32-bit
// target destination can read either a byte or a word from the indirect
// source.
template <OpCode OP, unsigned SIZE1, bool ISFLOAT1, unsigned SIZE2, bool ISFLOAT2>
void Emit(Register<SIZE1, ISFLOAT1> dest, Register<8, false> src, int32_t srcOffset);
// Scale-index-base (SIB) + offset.
template <OpCode OP, unsigned SIZE, bool ISFLOAT>
void Emit(Register<SIZE, ISFLOAT> dest,
Register<8, false> base,
Register<8, false> index,
SIB scale,
int32_t offset);
// Two operands - indirect destination and register source with the same type and size.
template <OpCode OP, unsigned SIZE, bool ISFLOAT>
void Emit(Register<8, false> dest, int32_t destOffset, Register<SIZE, ISFLOAT> src);
// Scale-index-base (SIB) + offset.
template <OpCode OP, unsigned SIZE, bool ISFLOAT>
void Emit(Register<8, false> base,
Register<8, false> index,
SIB scale,
int32_t offset,
Register<SIZE, ISFLOAT> src);
// Two operands - indirect destination and register source. This flavor
// of the method is used for instructions which can write values of a
// varying size to the destination address.
template <OpCode OP, unsigned SIZE1, bool ISFLOAT1, unsigned SIZE2, bool ISFLOAT2>
void Emit(Register<8, false> dest, int32_t destOffset, Register<SIZE2, ISFLOAT2> src);
// Two operands - register destination and immediate source.
// Note: Method is named EmitImmediate() to avoid clashes with other
// Emit() methods in case when T gets resolved to f. ex. Register.
template <OpCode OP, unsigned SIZE, bool ISFLOAT, typename T>
void EmitImmediate(Register<SIZE, ISFLOAT> dest, T value);
// Three operands: two register operands of the same size and type and
// an immediate (f. ex. shld eax, ebx, 4).
template <OpCode OP, unsigned SIZE, bool ISFLOAT, typename T>
void EmitImmediate(Register<SIZE, ISFLOAT> dest, Register<SIZE, ISFLOAT> src, T value);
private:
void Call(Register<8, false> r);
template <unsigned SIZE>
void IMul(Register<SIZE, false> dest,
Register<SIZE, false> src);
template <unsigned SIZE>
void IMul(Register<SIZE, false> dest,
Register<8, false> src,
int32_t srcOffset);
template <unsigned SIZE, typename T>
void IMulImmediate(Register<SIZE, false> dest,
T value);
template <unsigned SIZE>
void Lea(Register<SIZE, false> dest,
Register<8, false> src,
int32_t srcOffset);
template <unsigned SIZE, typename T>
void MovImmediate(Register<SIZE, false> dest,
T value);
template <typename T>
void MovImmediate(Register<8, false> dest,
T* value);
void Pop(Register<8, false> r);
void Push(Register<8, false> r);
void Ret();
template <unsigned SIZE>
void MovD(Register<SIZE, true> dest, Register<SIZE, false> src);
template <unsigned SIZE1, unsigned SIZE2>
void MovSX(Register<SIZE1, false> dest, Register<SIZE2, false> src);
template <unsigned SIZE1, unsigned SIZE2>
void MovSX(Register<SIZE1, false> dest, Register<8, false> src, int32_t srcOffset);
template <unsigned SIZE1, unsigned SIZE2>
void MovZX(Register<SIZE1, false> dest, Register<SIZE2, false> src);
template <unsigned SIZE1, unsigned SIZE2>
void MovZX(Register<SIZE1, false> dest, Register<8, false> src, int32_t srcOffset);
template <unsigned SIZE>
void Shld(Register<SIZE, false> dest, Register<SIZE, false> src, uint8_t bitCount);
template <unsigned SIZE>
void Shld(Register<SIZE, false> dest, Register<SIZE, false> src);
// Scalar SSE instructions are encoded as XX 0F OPCODE, where XX is
// either 0xF2 or 0xF3 depending on the register size. Used for
// instructions operating on scalars (f. ex. MovSS/SD, AddSS/SD) rather
// than packed (f. ex. MOVUPS/MOVUPD).
// Generic method for emitting 0xF2 or 0xF3 prefix depending on the
// register type and size.
template <unsigned RMSIZE, bool RMISFLOAT,
unsigned REGSIZE, bool REGISFLOAT,
unsigned RMREGSIZE, bool RMREGISFLOAT>
void EmitScalarSSEPrefix(Register<REGSIZE, REGISFLOAT> reg, Register<RMREGSIZE, RMREGISFLOAT> rm);
// Two direct registers.
template <unsigned SIZE1, bool ISFLOAT1, unsigned SIZE2, bool ISFLOAT2>
void EmitScalarSSEPrefixDirect(Register<SIZE1, ISFLOAT1> dest, Register<SIZE2, ISFLOAT2> src);
// Two registers, the one corresponding to R/M is indirect.
template <unsigned RMSIZE, bool RMISFLOAT, unsigned REGSIZE, bool REGISFLOAT>
void EmitScalarSSEPrefixIndirect(Register<REGSIZE, REGISFLOAT> reg, Register<8, false> rm);
// Variants for emitting scalar SSE instructions.
template <uint8_t OPCODE, unsigned SIZE1, bool ISFLOAT1, unsigned SIZE2, bool ISFLOAT2>
void ScalarSSE(Register<SIZE1, ISFLOAT1> dest, Register<SIZE2, ISFLOAT2> src);
template <uint8_t OPCODE, unsigned SIZE1, bool ISFLOAT1, unsigned SIZE2, bool ISFLOAT2>
void ScalarSSE(Register<SIZE1, ISFLOAT1> dest, Register<8, false> src, int32_t srcOffset);
template <uint8_t OPCODE, unsigned SIZE1, bool ISFLOAT1, unsigned SIZE2, bool ISFLOAT2>
void ScalarSSE(Register<8, false> dest, int32_t destOffset, Register<SIZE2, ISFLOAT2> src);
// SSEx66 methods emit SSE instructions that are encoded as
// [0x66] 0F OPCODE, where 0x66 prefix is present only if the source is
// a double. Used mostly but not exclusively for instructions operating
// on packed (f. ex. MovAPS/PD, XorPS/PD). Note that this is not the
// exclusive use of this prefix as there are instructions which use the
// 0x66 prefix to specify whether the arguments are MMX or XMM registers.
// Generic method for emitting the 0x66 prefix depending on the register
// type and size.
template <unsigned RMSIZE, bool RMISFLOAT,
unsigned REGSIZE, bool REGISFLOAT,
unsigned RMREGSIZE, bool RMREGISFLOAT>
void EmitSSEx66Prefix(Register<REGSIZE, REGISFLOAT> reg, Register<RMREGSIZE, RMREGISFLOAT> rm);
// Two direct registers.
template <unsigned SIZE1, bool ISFLOAT1, unsigned SIZE2, bool ISFLOAT2>
void EmitSSEx66PrefixDirect(Register<SIZE1, ISFLOAT1> dest, Register<SIZE2, ISFLOAT2> src);
// Two registers, the one corresponding to R/M is indirect.
template <unsigned RMSIZE, bool RMISFLOAT, unsigned REGSIZE, bool REGISFLOAT>
void EmitSSEx66PrefixIndirect(Register<REGSIZE, REGISFLOAT> reg, Register<8, false> rm);
// Variants for emitting the SSEx66 instructions.
template <uint8_t OPCODE, unsigned SIZE1, bool ISFLOAT1, unsigned SIZE2, bool ISFLOAT2>
void SSEx66(Register<SIZE1, ISFLOAT1> dest, Register<SIZE2, ISFLOAT2> src);
template <uint8_t OPCODE, unsigned SIZE1, bool ISFLOAT1, unsigned SIZE2, bool ISFLOAT2>
void SSEx66(Register<SIZE1, ISFLOAT1> dest, Register<8, false> src, int32_t srcOffset);
template <uint8_t OPCODE, unsigned SIZE1, bool ISFLOAT1, unsigned SIZE2, bool ISFLOAT2>
void SSEx66(Register<8, false> dest, int32_t destOffset, Register<SIZE2, ISFLOAT2> src);
// Group 1/2 instructions.
template <unsigned SIZE>
void Group1(uint8_t baseOpCode,
Register<SIZE, false> dest,
Register<SIZE, false> src);
template <unsigned SIZE>
void Group1(uint8_t baseOpCode,
Register<SIZE, false> dest,
Register<8, false> src,
int32_t srcOffset);
template <unsigned SIZE>
void Group1(uint8_t baseOpCode,
Register<SIZE, false> dest,
Register<8, false> base,
Register<8, false> index,
SIB scale,
int32_t srcOffset);
template <unsigned SIZE>
void Group1(uint8_t baseOpCode,
Register<8, false> dest,
int32_t destOffset,
Register<SIZE, false> src);
template <unsigned SIZE>
void Group1(uint8_t baseOpCode,
Register<8, false> base,
Register<8, false> index,
SIB scale,
int32_t offset,
Register<SIZE, false> src);
template <unsigned SIZE, typename T>
void Group1(uint8_t baseOpCode,
uint8_t extensionOpCode,
Register<SIZE, false> dest,
T value);
template <unsigned SIZE>
void Group2(uint8_t extensionOpCode,
Register<SIZE, false> dest);
template <unsigned SIZE>
void Group2(uint8_t extensionOpCode,
uint8_t shift,
Register<SIZE, false> dest);
template <unsigned SIZE>
void Group3And5(uint8_t opcode,
uint8_t extensionOpCode,
Register<SIZE, false> dest);
template <unsigned SIZE>
void Group3And5(uint8_t opcode,
uint8_t extensionOpCode,
Register<8u, false> base,
int32_t offset);
template <unsigned SIZE>
void GroupBitOps(uint8_t opcode,
Register<SIZE, false> dest,
Register<SIZE, false> bit);
// Methods for emitting the 0x66 operand size override prefix if
// size of either operand is 16-bit. Note: for indirect addressing, the
// size of the operand is the size of the memory being accessed, not the
// size of the indirect base register.
// Reference: path_to_url#Operand-size_and_address-size_override_prefix
// Generic version. When used with indirect addressing, the first two
// template parameters describe the target memory size and type whereas
// the last two describe the base register. For regular addressing,
// these two pairs of template parameters have to be the same.
template <unsigned RMSIZE, bool RMISFLOAT,
unsigned REGSIZE, bool REGISFLOAT,
unsigned RMREGSIZE, bool RMREGISFLOAT>
void EmitOpSizeOverride(Register<REGSIZE, REGISFLOAT> reg,
Register<RMREGSIZE, RMREGISFLOAT> rm);
// Single direct register.
template <unsigned SIZE, bool ISFLOAT>
void EmitOpSizeOverride(Register<SIZE, ISFLOAT> reg);
// Two direct registers.
template <unsigned SIZE1, bool ISFLOAT1, unsigned SIZE2, bool ISFLOAT2>
void EmitOpSizeOverrideDirect(Register<SIZE1, ISFLOAT1> dest,
Register<SIZE2, ISFLOAT2> src);
// Single indirect register.
template <unsigned RMSIZE, bool RMISFLOAT>
void EmitOpSizeOverrideIndirect(Register<8, false> rm);
// Two registers, the one corresponding to R/M is indirect.
template <unsigned RMSIZE, bool RMISFLOAT, unsigned REGSIZE, bool REGISFLOAT>
void EmitOpSizeOverrideIndirect(Register<REGSIZE, REGISFLOAT> reg, Register<8, false> rm);
// Methods for emitting the REX byte. For indirect addressing, the
// size of the operand is the size of the memory being accessed, not the
// size of the indirect base register.
// Reference: path_to_url#REX_prefix
// Generic version. See the comment for EmitOpSizeOverride() for more information.
template <unsigned RMSIZE, bool RMISFLOAT,
unsigned REGSIZE, bool REGISFLOAT,
unsigned RMREGSIZE, bool RMREGISFLOAT>
void EmitRex(Register<REGSIZE, REGISFLOAT> reg, Register<RMREGSIZE, RMREGISFLOAT> rm);
// Single direct register.
template <unsigned SIZE, bool ISFLOAT>
void EmitRex(Register<SIZE, ISFLOAT> reg);
// Two direct registers.
template <unsigned SIZE1, bool ISFLOAT1, unsigned SIZE2, bool ISFLOAT2>
void EmitRexDirect(Register<SIZE1, ISFLOAT1> dest, Register<SIZE2, ISFLOAT2> src);
// Single indirect register.
template <unsigned RMSIZE, bool RMISFLOAT>
void EmitRexIndirect(Register<8, false> rm);
// Two registers, the one corresponding to R/M is indirect.
template <unsigned RMSIZE, bool RMISFLOAT, unsigned REGSIZE, bool REGISFLOAT>
void EmitRexIndirect(Register<REGSIZE, REGISFLOAT> reg, Register<8, false> rm);
// Methods for emitting the ModR/M byte.
// Reference: path_to_url#ModR.2FM
template <unsigned SIZE1, bool ISFLOAT1, unsigned SIZE2, bool ISFLOAT2>
void EmitModRM(Register<SIZE1, ISFLOAT1> dest, Register<SIZE2, ISFLOAT2> src);
template <unsigned SIZE>
void EmitModRM(uint8_t extensionOpCode, Register<SIZE, false> dest);
template <unsigned SIZE, bool ISFLOAT>
void EmitModRMOffset(Register<SIZE, ISFLOAT> dest, Register<8, false> src, int32_t srcOffset);
// Helper class used to provide partial specializations by OpCode,
// ISFLOAT and SIZE for the Emit() methods.
template <OpCode OP>
struct Helper
{
static void Emit(X64CodeGenerator& code);
struct ArgTypes0
{
template <unsigned SIZE>
static void Emit(X64CodeGenerator& code,
Register<SIZE, false> dest);
template <unsigned SIZE>
static void Emit(X64CodeGenerator& code,
Register<8u, false> dest,
int32_t offset);
template <unsigned SIZE>
static void Emit(X64CodeGenerator& code,
Register<SIZE, false> dest,
Register<SIZE, false> bit);
};
// Emit methods where operands have the same type and size. This is
// another layer used to provide partial specialization for the
// Emit() methods.
template <bool ISFLOAT>
struct ArgTypes1
{
template <unsigned SIZE>
static void Emit(X64CodeGenerator& code, Register<SIZE, ISFLOAT> dest);
template <unsigned SIZE>
static void Emit(X64CodeGenerator& code, Register<SIZE, ISFLOAT> dest, Register<SIZE, ISFLOAT> src);
template <unsigned SIZE>
static void Emit(X64CodeGenerator& code, Register<SIZE, ISFLOAT> dest, Register<8, false> src, int32_t srcOffset);
template <unsigned SIZE>
static void Emit(X64CodeGenerator& code,
Register<SIZE, ISFLOAT> dest,
Register<8, false> base,
Register<8, false> index,
SIB scale,
int32_t srcOffset);
template <unsigned SIZE>
static void Emit(X64CodeGenerator& code, Register<8, false> dest, int32_t destOffset, Register<SIZE, ISFLOAT> src);
template <unsigned SIZE>
static void Emit(X64CodeGenerator& code,
Register<8, false> base,
Register<8, false> index,
SIB scale,
int32_t srcOffset,
Register<SIZE, ISFLOAT> src);
template <unsigned SIZE, typename T>
static void EmitImmediate(X64CodeGenerator& code, Register<SIZE, ISFLOAT> dest, T value);
template <unsigned SIZE, typename T>
static void EmitImmediate(X64CodeGenerator& code, Register<SIZE, ISFLOAT> dest, Register<SIZE, ISFLOAT> src, T value);
};
// Emit methods where operands don't have the same type and size.
template <bool ISFLOAT1, bool ISFLOAT2>
struct ArgTypes2
{
template <unsigned SIZE1, unsigned SIZE2>
static void Emit(X64CodeGenerator& code, Register<SIZE1, ISFLOAT1> dest, Register<SIZE2, ISFLOAT2> src);
template <unsigned SIZE1, unsigned SIZE2>
static void Emit(X64CodeGenerator& code, Register<SIZE1, ISFLOAT1> dest, Register<8, false> src, int32_t srcOffset);
template <unsigned SIZE1, unsigned SIZE2>
static void Emit(X64CodeGenerator& code, Register<8, false> dest, int32_t destOffset, Register<SIZE2, ISFLOAT2> src);
};
};
// CodePrinter is a helper class for formatting X64CodeGenerator opcodes
// and operands along with the resulting assembly encoding of the
// instruction into a diagnostics stream, if diagnostics output is enabled.
//
// The client is expected to 1. call NoteStartPosition() before emitting
// the instructions into the X64CodeGenerator and 2. call the relevant
// Print() method after emitting them.
//
class CodePrinter : public NonCopyable
{
public:
// Calls NoteStartPosition() and stores the output diagnostics stream.
CodePrinter(X64CodeGenerator& code);
void NoteStartPosition();
void PlaceLabel(Label label);
// The Print() methods will display the last remembered starting
// point of the code buffer, all the encoded bytes from
// the starting point to the end of the buffer followed by the
// X64CodeGenerator opcodes and operands.
void PrintJump(void *function);
void PrintJump(Label label);
template <JccType JCC>
void Print(Label l);
void Print(OpCode op);
template <unsigned SIZE>
void Print(OpCode op, Register<8u, false> base, int32_t offset);
template <unsigned SIZE, bool ISFLOAT>
void Print(OpCode op, Register<SIZE, ISFLOAT> dest);
template <unsigned SIZE1, bool ISFLOAT1, unsigned SIZE2, bool ISFLOAT2>
void Print(OpCode op, Register<SIZE1, ISFLOAT1> dest, Register<SIZE2, ISFLOAT2> src);
template <unsigned SIZE1, bool ISFLOAT1, unsigned SIZE2, bool ISFLOAT2>
void Print(OpCode op, Register<SIZE1, ISFLOAT1> dest, Register<8, false> src, int32_t srcOffset);
template <unsigned SIZE1, bool ISFLOAT1>
void Print(OpCode op,
Register<SIZE1, ISFLOAT1> dest,
Register<8u, false> base,
Register<8u, false> index,
SIB scale,
int32_t offset);
template <unsigned SIZE1, bool ISFLOAT1, unsigned SIZE2, bool ISFLOAT2>
void Print(OpCode op, Register<8, false> dest, int32_t destOffset, Register<SIZE2, ISFLOAT2> src);
template <unsigned SIZE1, bool ISFLOAT1>
void Print(OpCode op,
Register<8u, false> base,
Register<8u, false> index,
SIB scale,
int32_t offset,
Register<SIZE1, ISFLOAT1> src);
template <unsigned SIZE, bool ISFLOAT, typename T>
void PrintImmediate(OpCode op, Register<SIZE, ISFLOAT> dest, T value);
template <unsigned SIZE, bool ISFLOAT, typename T>
void PrintImmediate(OpCode op, Register<SIZE, ISFLOAT> dest, Register<SIZE, ISFLOAT> src, T value);
private:
X64CodeGenerator& m_code;
unsigned m_startPosition;
std::ostream* m_out;
// Returns "byte" for 1, "word" for 2 etc.
static char const * GetPointerName(unsigned pointerSize);
template <typename T>
static void PrintImmediate(std::ostream& out, T value);
void PrintBytes(unsigned startPosition, unsigned endPosition);
// A functor which implements the abs() operation for integral types.
// CodePrinter prints immediates in hex so the negative values need
// to have the sign printed explicitly in front of the absolute value.
template <typename T, bool ISSIGNED = std::is_signed<T>::value>
struct IntegralAbs
{
T operator()(T value);
};
// Specialization for non-signed types.
template <typename T>
struct IntegralAbs<T, false>
{
T operator()(T value);
};
};
std::ostream* m_diagnosticsStream;
};
// TODO: Move this class to a separate header
//
// Stores the current value of stream's flags, width and fill character in
// the constructor and restores them back in the destructor. The saving/restoring
// of these properties is a close subset of what std::ios::copyfmt does, but
// is more lightweight (no locale, invocation of callbacks etc).
class IosMiniStateRestorer final : private NonCopyable
{
public:
IosMiniStateRestorer(std::ios& stream);
~IosMiniStateRestorer();
private:
std::ios& m_stream;
std::ios::fmtflags m_flags;
std::streamsize m_width;
char m_fillChar;
};
//*************************************************************************
//
// Helper code printing methods.
//
//*************************************************************************
template <JccType JCC>
void X64CodeGenerator::CodePrinter::Print(Label label)
{
if (m_out != nullptr)
{
PrintBytes(m_startPosition, m_code.CurrentPosition());
*m_out << JccName(JCC) << " L" << label.GetId() << std::endl;
}
}
template <unsigned SIZE, bool ISFLOAT>
void X64CodeGenerator::CodePrinter::Print(OpCode op, Register<SIZE, ISFLOAT> dest)
{
if (m_out != nullptr)
{
PrintBytes(m_startPosition, m_code.CurrentPosition());
*m_out << OpCodeName(op) << ' ' << dest.GetName() << std::endl;
}
}
template <unsigned SIZE>
void X64CodeGenerator::CodePrinter::Print(OpCode op,
Register<8u, false> base,
int32_t offset)
{
if (m_out != nullptr)
{
PrintBytes(m_startPosition, m_code.CurrentPosition());
*m_out
<< OpCodeName(op)
<< ' '
<< GetPointerName(SIZE)
<< " ptr ["
<< base.GetName()
<< std::uppercase
<< std::hex;
if (offset > 0)
{
*m_out << " + " << offset << "h";
}
else if (offset < 0)
{
*m_out << " - " << -static_cast<int64_t>(offset) << "h";
}
*m_out << "]" << std::endl;
}
}
template <unsigned SIZE1, bool ISFLOAT1, unsigned SIZE2, bool ISFLOAT2>
void X64CodeGenerator::CodePrinter::Print(OpCode op,
Register<SIZE1, ISFLOAT1> dest,
Register<SIZE2, ISFLOAT2> src)
{
if (m_out != nullptr)
{
PrintBytes(m_startPosition, m_code.CurrentPosition());
*m_out
<< OpCodeName(op)
<< ' ' << dest.GetName()
<< ", " << src.GetName()
<< std::endl;
}
}
template <unsigned SIZE1, bool ISFLOAT1, unsigned SIZE2, bool ISFLOAT2>
void X64CodeGenerator::CodePrinter::Print(OpCode op,
Register<SIZE1, ISFLOAT1> dest,
Register<8, false> src,
int32_t srcOffset)
{
if (m_out != nullptr)
{
IosMiniStateRestorer state(*m_out);
PrintBytes(m_startPosition, m_code.CurrentPosition());
*m_out << OpCodeName(op)
<< ' ' << dest.GetName()
<< ", "
<< GetPointerName(SIZE2)
<< " ptr ["
<< src.GetName()
<< std::uppercase
<< std::hex;
if (srcOffset > 0)
{
*m_out << " + " << srcOffset << "h";
}
else if (srcOffset < 0)
{
*m_out << " - " << -static_cast<int64_t>(srcOffset) << "h";
}
*m_out << "]" << std::endl;
}
}
template <unsigned SIZE, bool ISFLOAT>
void X64CodeGenerator::CodePrinter::Print(OpCode op,
Register<SIZE, ISFLOAT> dest,
Register<8u, false> base,
Register<8u, false> index,
SIB scale,
int32_t offset)
{
if (m_out != nullptr)
{
IosMiniStateRestorer state(*m_out);
PrintBytes(m_startPosition, m_code.CurrentPosition());
*m_out << OpCodeName(op)
<< ' ' << dest.GetName()
<< ", "
<< GetPointerName(SIZE)
<< " ptr ["
<< base.GetName()
<< " + "
<< index.GetName()
<< " * "
<< static_cast<unsigned>(scale)
<< std::uppercase
<< std::hex;
if (offset > 0)
{
*m_out << " + " << offset << "h";
}
else if (offset < 0)
{
*m_out << " - " << -static_cast<int64_t>(offset) << "h";
}
*m_out << "]" << std::endl;
}
}
template <unsigned SIZE1, bool ISFLOAT1, unsigned SIZE2, bool ISFLOAT2>
void X64CodeGenerator::CodePrinter::Print(OpCode op,
Register<8, false> dest,
int32_t destOffset,
Register<SIZE2, ISFLOAT2> src)
{
if (m_out != nullptr)
{
IosMiniStateRestorer state(*m_out);
PrintBytes(m_startPosition, m_code.CurrentPosition());
*m_out << OpCodeName(op)
<< ' '
<< GetPointerName(SIZE1)
<< " ptr ["
<< dest.GetName()
<< std::uppercase
<< std::hex;
if (destOffset > 0)
{
*m_out << " + " << destOffset << "h";
}
else if (destOffset < 0)
{
*m_out << " - " << -static_cast<int64_t>(destOffset) << "h";
}
*m_out << "], " << src.GetName() << std::endl;
}
}
template <unsigned SIZE, bool ISFLOAT>
void X64CodeGenerator::CodePrinter::Print(OpCode op,
Register<8u, false> base,
Register<8u, false> index,
SIB scale,
int32_t offset,
Register<SIZE, ISFLOAT> src)
{
if (m_out != nullptr)
{
IosMiniStateRestorer state(*m_out);
PrintBytes(m_startPosition, m_code.CurrentPosition());
*m_out << OpCodeName(op)
<< GetPointerName(SIZE)
<< " ptr ["
<< base.GetName()
<< " + "
<< index.GetName()
<< " * "
<< static_cast<unsigned>(scale)
<< std::uppercase
<< std::hex;
if (offset > 0)
{
*m_out << " + " << offset << "h";
}
else if (offset < 0)
{
*m_out << " - " << -static_cast<int64_t>(offset) << "h";
}
*m_out
<< "], "
<< ' ' << src.GetName()
<< std::endl;
}
}
template <typename T, bool ISSIGNED>
T X64CodeGenerator::CodePrinter::IntegralAbs<T, ISSIGNED>::operator()(T value)
{
return value < 0 ? -value : value;
}
// Specialization for non-signed types.
template <typename T>
T X64CodeGenerator::CodePrinter::IntegralAbs<T, false>::operator()(T value)
{
return value;
}
template <typename T>
void X64CodeGenerator::CodePrinter::PrintImmediate(std::ostream& out, T value)
{
static_assert(!std::is_floating_point<T>::value,
"Floating point values cannot be used as immediates.");
const T nonNegativeValue = IntegralAbs<T>()(value);
const auto prefix = (value != nonNegativeValue) ? "-" : "";
IosMiniStateRestorer state(out);
// Unary + causes integral promotion so char would be printed as integer,
// as expected.
out
<< std::uppercase
<< std::hex
<< prefix
<< +nonNegativeValue
<< 'h';
}
template <unsigned SIZE, bool ISFLOAT, typename T>
void X64CodeGenerator::CodePrinter::PrintImmediate(OpCode op,
Register<SIZE, ISFLOAT> dest,
T value)
{
if (m_out != nullptr)
{
PrintBytes(m_startPosition, m_code.CurrentPosition());
*m_out << OpCodeName(op) << ' ' << dest.GetName() << ", ";
PrintImmediate(*m_out, value);
*m_out << std::endl;
}
}
template <unsigned SIZE, bool ISFLOAT, typename T>
void X64CodeGenerator::CodePrinter::PrintImmediate(OpCode op,
Register<SIZE, ISFLOAT> dest,
Register<SIZE, ISFLOAT> src,
T value)
{
if (m_out != nullptr)
{
PrintBytes(m_startPosition, m_code.CurrentPosition());
*m_out << OpCodeName(op)
<< ' ' << dest.GetName()
<< ", " << src.GetName()
<< ", ";
PrintImmediate(*m_out, value);
*m_out << std::endl;
}
}
//*************************************************************************
//
// Template definitions for X64CodeGenerator - public methods.
//
//*************************************************************************
template <JccType JCC>
void X64CodeGenerator::EmitConditionalJump(Label label)
{
CodePrinter printer(*this);
Emit8(0xf);
Emit8(0x80 + static_cast<uint8_t>(JCC));
EmitCallSite(label, 4);
printer.Print<JCC>(label);
}
template <OpCode OP>
void X64CodeGenerator::Emit()
{
CodePrinter printer(*this);
Helper<OP>::Emit(*this);
printer.Print(OP);
}
template <OpCode OP, unsigned SIZE, bool ISFLOAT>
void X64CodeGenerator::Emit(Register<SIZE, ISFLOAT> dest)
{
CodePrinter printer(*this);
Helper<OP>::template ArgTypes1<ISFLOAT>::template Emit<SIZE>(*this, dest);
printer.Print(OP, dest);
}
template <OpCode OP, unsigned SIZE, bool ISFLOAT>
void X64CodeGenerator::Emit(Register<SIZE, ISFLOAT> dest, Register<SIZE, ISFLOAT> src)
{
CodePrinter printer(*this);
Helper<OP>::template ArgTypes1<ISFLOAT>::template Emit<SIZE>(*this, dest, src);
printer.Print(OP, dest, src);
}
template <OpCode OP, unsigned SIZE1, bool ISFLOAT1, unsigned SIZE2, bool ISFLOAT2>
void X64CodeGenerator::Emit(Register<SIZE1, ISFLOAT1> dest, Register<SIZE2, ISFLOAT2> src)
{
CodePrinter printer(*this);
Helper<OP>::template ArgTypes2<ISFLOAT1, ISFLOAT2>::template Emit<SIZE1, SIZE2>(*this, dest, src);
printer.Print(OP, dest, src);
}
// Base register and offset.
template <OpCode OP, unsigned SIZE>
void X64CodeGenerator::Emit(Register<8u, false> dest, int32_t offset)
{
CodePrinter printer(*this);
Helper<OP>::ArgTypes0::template Emit<SIZE>(*this, dest, offset);
printer.Print<SIZE>(OP, dest, offset);
}
template <OpCode OP, unsigned SIZE, bool ISFLOAT>
void X64CodeGenerator::Emit(Register<SIZE, ISFLOAT> dest, Register<8, false> src, int32_t srcOffset)
{
CodePrinter printer(*this);
Helper<OP>::template ArgTypes1<ISFLOAT>::template Emit<SIZE>(*this, dest, src, srcOffset);
printer.Print<SIZE, ISFLOAT, SIZE, ISFLOAT>(OP, dest, src, srcOffset);
}
template <OpCode OP, unsigned SIZE1, bool ISFLOAT1, unsigned SIZE2, bool ISFLOAT2>
void X64CodeGenerator::Emit(Register<SIZE1, ISFLOAT1> dest, Register<8, false> src, int32_t srcOffset)
{
CodePrinter printer(*this);
Helper<OP>::template ArgTypes2<ISFLOAT1, ISFLOAT2>::template Emit<SIZE1, SIZE2>(*this, dest, src, srcOffset);
printer.Print<SIZE1, ISFLOAT1, SIZE2, ISFLOAT2>(OP, dest, src, srcOffset);
}
// Scale-index-base (SIB) + offset.
template <OpCode OP, unsigned SIZE, bool ISFLOAT>
void X64CodeGenerator::Emit(Register<SIZE, ISFLOAT> dest,
Register<8, false> base,
Register<8, false> index,
SIB scale,
int32_t offset)
{
CodePrinter printer(*this);
Helper<OP>::template ArgTypes1<ISFLOAT>::template Emit<SIZE>(*this, dest, base, index, scale, offset);
printer.Print<SIZE, ISFLOAT>(OP, dest, base, index, scale, offset);
}
template <OpCode OP, unsigned SIZE, bool ISFLOAT>
void X64CodeGenerator::Emit(Register<8, false> dest, int32_t destOffset, Register<SIZE, ISFLOAT> src)
{
CodePrinter printer(*this);
Helper<OP>::template ArgTypes1<ISFLOAT>::template Emit<SIZE>(*this, dest, destOffset, src);
printer.Print<SIZE, ISFLOAT, SIZE, ISFLOAT>(OP, dest, destOffset, src);
}
template <OpCode OP, unsigned SIZE, bool ISFLOAT>
void X64CodeGenerator::Emit(Register<8, false> base,
Register<8, false> index,
SIB scale,
int32_t offset,
Register<SIZE, ISFLOAT> src)
{
CodePrinter printer(*this);
Helper<OP>::template ArgTypes1<ISFLOAT>::template Emit<SIZE>(*this, base, index, scale, offset, src);
printer.Print<SIZE, ISFLOAT>(OP, base, index, scale, offset, src);
}
template <OpCode OP, unsigned SIZE1, bool ISFLOAT1, unsigned SIZE2, bool ISFLOAT2>
void X64CodeGenerator::Emit(Register<8, false> dest, int32_t destOffset, Register<SIZE2, ISFLOAT2> src)
{
CodePrinter printer(*this);
Helper<OP>::template ArgTypes2<ISFLOAT1, ISFLOAT2>::template Emit<SIZE1, SIZE2>(*this, dest, destOffset, src);
printer.Print<SIZE1, ISFLOAT1, SIZE2, ISFLOAT2>(OP, dest, destOffset, src);
}
template <OpCode OP, unsigned SIZE, bool ISFLOAT, typename T>
void X64CodeGenerator::EmitImmediate(Register<SIZE, ISFLOAT> dest, T value)
{
static_assert(!std::is_floating_point<T>::value, "Floating point values cannot be used as immediates.");
CodePrinter printer(*this);
Helper<OP>::template ArgTypes1<ISFLOAT>::template EmitImmediate<SIZE, T>(*this, dest, value);
printer.PrintImmediate(OP, dest, value);
}
template <OpCode OP, unsigned SIZE, bool ISFLOAT, typename T>
void X64CodeGenerator::EmitImmediate(Register<SIZE, ISFLOAT> dest, Register<SIZE, ISFLOAT> src, T value)
{
static_assert(!std::is_floating_point<T>::value, "Floating point values cannot be used as immediates.");
CodePrinter printer(*this);
Helper<OP>::template ArgTypes1<ISFLOAT>::template EmitImmediate<SIZE, T>(*this, dest, src, value);
printer.PrintImmediate(OP, dest, src, value);
}
//*************************************************************************
//
// Template definitions for X64CodeGenerator - private methods.
//
//*************************************************************************
//
// X64 opcodes
//
template <unsigned SIZE>
void X64CodeGenerator::IMul(Register<SIZE, false> dest,
Register<SIZE, false> src)
{
EmitOpSizeOverrideDirect(dest, src);
EmitRexDirect(dest, src);
Emit8(0x0f);
Emit8(0xAF);
EmitModRM(dest, src);
}
template <unsigned SIZE>
void X64CodeGenerator::IMul(Register<SIZE, false> dest,
Register<8, false> src,
int32_t srcOffset)
{
EmitOpSizeOverrideIndirect<SIZE, false>(dest, src);
EmitRexIndirect<SIZE, false>(dest, src);
Emit8(0x0f);
Emit8(0xAF);
EmitModRMOffset(dest, src, srcOffset);
}
template <unsigned SIZE, typename T>
void X64CodeGenerator::IMulImmediate(Register<SIZE, false> dest,
T value)
{
static_assert(SIZE != 1, "8-bit target not supported.");
static_assert(sizeof(T) <= SIZE, "Invalid size of the immediate.");
static_assert(sizeof(T) < 8, "64-bit immediates are not supported by IMul.");
static_assert(std::is_integral<T>::value, "IMul works only with integral values.");
const unsigned valueSize = Size(value);
EmitOpSizeOverrideDirect(dest, dest);
EmitRexDirect(dest, dest);
if (valueSize <= 1
&& (static_cast<int64_t>(value) < 0
|| !BitOp::TestBit(static_cast<uint64_t>(value), 7)))
{
// Use the sign-extend flavor of the opcode only if the value is
// signed and negative or if the bit #7 is not set otherwise.
Emit8(0x6b);
EmitModRM(dest, dest);
Emit8(static_cast<uint8_t>(value));
}
else
{
Emit8(0x69);
EmitModRM(dest, dest);
if (SIZE == 2)
{
Emit16(static_cast<uint16_t>(value));
}
else // if (valueSize <= 4)
{
Emit32(static_cast<uint32_t>(value));
}
}
}
template <unsigned SIZE>
void X64CodeGenerator::Lea(Register<SIZE, false> dest,
Register<8, false> src,
int32_t srcOffset)
{
EmitRexIndirect<SIZE, false>(dest, src);
Emit8(0x8d);
EmitModRMOffset(dest, src, srcOffset);
}
template <unsigned SIZE, typename T>
void X64CodeGenerator::MovImmediate(Register<SIZE, false> dest,
T value)
{
static_assert(!std::is_floating_point<T>::value, "Invalid type of the immediate.");
static_assert(sizeof(T) <= SIZE, "Invalid size of the immediate.");
EmitOpSizeOverride(dest);
EmitRex(dest);
if (SIZE == 1)
{
Emit8(0xb0 | dest.GetId8());
Emit8(static_cast<uint8_t>(value));
}
else if (SIZE == 8
&& Size(value) <= 4
&& ((std::is_signed<T>::value && static_cast<int64_t>(value) < 0)
|| !BitOp::TestBit(static_cast<uint64_t>(value), 31)))
{
// Use the sign-extend flavor of the opcode only if the value is
// signed and negative or if the bit #31 is not set otherwise.
Emit8(0xc7);
EmitModRM(0, dest);
Emit32(static_cast<uint32_t>(value));
}
else
{
Emit8(0xb8 + dest.GetId8());
if (SIZE == 2)
{
Emit16(static_cast<uint16_t>(value));
}
else if (SIZE == 4)
{
Emit32(static_cast<uint32_t>(value));
}
else
{
Emit64(static_cast<uint64_t>(value));
}
}
}
template <typename T>
void X64CodeGenerator::MovImmediate(Register<8, false> dest,
T* value)
{
MovImmediate(dest, reinterpret_cast<uint64_t>(value));
}
template <unsigned SIZE>
void X64CodeGenerator::MovD(Register<SIZE, true> dest, Register<SIZE, false> src)
{
Emit8(0x66);
EmitRexDirect(dest, src);
Emit8(0x0f);
Emit8(0x6e);
EmitModRM(dest, src);
}
template <unsigned SIZE1, unsigned SIZE2>
void X64CodeGenerator::MovZX(Register<SIZE1, false> dest, Register<SIZE2, false> src)
{
static_assert(SIZE2 == 1 || SIZE2 == 2, "Invalid source size.");
static_assert(SIZE1 > SIZE2, "Target size must be larger than the source size.");
const bool twoByteSource = SIZE2 == 2;
// Size override is not necessary for 16-bit source since an opcode that
// defaults to 16 bits is used in that scenario.
//
if (!twoByteSource)
{
EmitOpSizeOverrideDirect(dest, src);
}
EmitRexDirect(dest, src);
Emit8(0x0f);
Emit8(twoByteSource ? 0xb7 : 0xb6);
EmitModRM(dest, src);
}
template <unsigned SIZE1, unsigned SIZE2>
void X64CodeGenerator::MovZX(Register<SIZE1, false> dest, Register<8, false> src, int32_t srcOffset)
{
static_assert(SIZE2 == 1 || SIZE2 == 2, "Invalid source size.");
static_assert(SIZE1 > SIZE2, "Target size must be larger than the source size.");
const bool twoByteSource = SIZE2 == 2;
if (!twoByteSource)
{
EmitOpSizeOverrideIndirect<SIZE2, false>(dest, src);
}
EmitRexIndirect<SIZE2, false>(dest, src);
Emit8(0x0f);
Emit8(twoByteSource ? 0xb7 : 0xb6);
EmitModRMOffset(dest, src, srcOffset);
}
template <unsigned SIZE1, unsigned SIZE2>
void X64CodeGenerator::MovSX(Register<SIZE1, false> dest, Register<SIZE2, false> src)
{
static_assert(SIZE2 < 8, "Invalid source size.");
static_assert(SIZE1 > SIZE2, "Target size must be larger than the source size.");
if (SIZE2 == 1)
{
EmitOpSizeOverrideDirect(dest, src);
EmitRexDirect(dest, src);
Emit8(0x0f);
Emit8(0xbe);
}
else if (SIZE2 == 2)
{
// No size override since 16-bit is default operand size; different opcode.
EmitRexDirect(dest, src);
Emit8(0x0f);
Emit8(0xbf);
}
else // if (SIZE2 == 4)
{
// No size override since neither operand can be 16-bit.
// No prefix, different opcode.
EmitRexDirect(dest, src);
Emit8(0x63);
}
EmitModRM(dest, src);
}
template <unsigned SIZE1, unsigned SIZE2>
void X64CodeGenerator::MovSX(Register<SIZE1, false> dest, Register<8, false> src, int32_t srcOffset)
{
static_assert(SIZE2 < 8, "Invalid source size.");
static_assert(SIZE1 > SIZE2, "Target size must be larger than the source size.");
if (SIZE2 == 1)
{
EmitOpSizeOverrideIndirect<SIZE2, false>(dest, src);
EmitRexIndirect<SIZE2, false>(dest, src);
Emit8(0x0f);
Emit8(0xbe);
}
else if (SIZE2 == 2)
{
// No size override since 16-bit is default operand size; different opcode.
EmitRexIndirect<SIZE2, false>(dest, src);
Emit8(0x0f);
Emit8(0xbf);
}
else // if (SIZE2 == 4)
{
// No size override since neither operand can be 16-bit.
// No prefix, different opcode.
EmitRexIndirect<SIZE2, false>(dest, src);
Emit8(0x63);
}
EmitModRMOffset(dest, src, srcOffset);
}
template <unsigned SIZE>
void X64CodeGenerator::Shld(Register<SIZE, false> dest, Register<SIZE, false> src, uint8_t bitCount)
{
// Note: operand encoding is MRC, so the order of arguments for the
// Emit*() methods is reversed.
EmitOpSizeOverrideDirect(src, dest);
EmitRexDirect(src, dest);
Emit8(0x0f);
Emit8(0xa4);
EmitModRM(src, dest);
Emit8(bitCount);
}
template <unsigned SIZE>
void X64CodeGenerator::Shld(Register<SIZE, false> dest, Register<SIZE, false> src)
{
// Note: operand encoding is MRC, so the order of arguments for the
// Emit*() methods is reversed.
EmitOpSizeOverrideDirect(src, dest);
EmitRexDirect(src, dest);
Emit8(0x0f);
Emit8(0xa5);
EmitModRM(src, dest);
}
//
// Scalar SSE instructions
//
template <unsigned RMSIZE, bool RMISFLOAT,
unsigned REGSIZE, bool REGISFLOAT,
unsigned RMREGSIZE, bool RMREGISFLOAT>
void X64CodeGenerator::EmitScalarSSEPrefix(Register<REGSIZE, REGISFLOAT> /* reg */,
Register<RMREGSIZE, RMREGISFLOAT> /* rm */)
{
static_assert(RMISFLOAT || REGISFLOAT, "Invalid ScalarSSE usage.");
static_assert(RMSIZE >= 4 && REGSIZE >= 4, "Invalid ScalarSSE integer register."); // Floats would error out before this point.
// Use the source register to decide on the prefix, but only if it's a float.
if (RMISFLOAT)
{
Emit8(RMSIZE == 8 ? 0xf2 : 0xf3);
}
else
{
Emit8(REGSIZE == 8 ? 0xf2 : 0xf3);
}
}
template <unsigned SIZE1, bool ISFLOAT1, unsigned SIZE2, bool ISFLOAT2>
void X64CodeGenerator::EmitScalarSSEPrefixDirect(Register<SIZE1, ISFLOAT1> dest,
Register<SIZE2, ISFLOAT2> src)
{
EmitScalarSSEPrefix<SIZE2, ISFLOAT2>(dest, src);
}
template <unsigned RMSIZE, bool RMISFLOAT, unsigned REGSIZE, bool REGISFLOAT>
void X64CodeGenerator::EmitScalarSSEPrefixIndirect(Register<REGSIZE, REGISFLOAT> reg, Register<8, false> rm)
{
EmitScalarSSEPrefix<RMSIZE, RMISFLOAT>(reg, rm);
}
template <uint8_t OPCODE, unsigned SIZE1, bool ISFLOAT1, unsigned SIZE2, bool ISFLOAT2>
void X64CodeGenerator::ScalarSSE(Register<SIZE1, ISFLOAT1> dest, Register<SIZE2, ISFLOAT2> src)
{
EmitScalarSSEPrefixDirect(dest, src);
EmitRexDirect(dest, src);
Emit8(0x0f);
Emit8(OPCODE);
EmitModRM(dest, src);
}
template <uint8_t OPCODE, unsigned SIZE1, bool ISFLOAT1, unsigned SIZE2, bool ISFLOAT2>
void X64CodeGenerator::ScalarSSE(Register<SIZE1, ISFLOAT1> dest,
Register<8, false> src,
int32_t srcOffset)
{
EmitScalarSSEPrefixIndirect<SIZE2, ISFLOAT2>(dest, src);
EmitRexIndirect<SIZE2, ISFLOAT2>(dest, src);
Emit8(0x0f);
Emit8(OPCODE);
EmitModRMOffset(dest, src, srcOffset);
}
template <uint8_t OPCODE, unsigned SIZE1, bool ISFLOAT1, unsigned SIZE2, bool ISFLOAT2>
void X64CodeGenerator::ScalarSSE(Register<8, false> dest,
int32_t destOffset,
Register<SIZE2, ISFLOAT2> src)
{
// Note: operand encoding is MR, so the order of arguments for the
// Emit*() methods is reversed.
EmitScalarSSEPrefixIndirect<SIZE1, ISFLOAT1>(src, dest);
EmitRexIndirect<SIZE1, ISFLOAT1>(src, dest);
Emit8(0x0f);
Emit8(OPCODE);
EmitModRMOffset(src, dest, destOffset);
}
//
// SSEx66 instructions
//
template <unsigned RMSIZE, bool RMISFLOAT,
unsigned REGSIZE, bool REGISFLOAT,
unsigned RMREGSIZE, bool RMREGISFLOAT>
void X64CodeGenerator::EmitSSEx66Prefix(Register<REGSIZE, REGISFLOAT> /* reg */,
Register<RMREGSIZE, RMREGISFLOAT> /* rm */)
{
static_assert(RMISFLOAT || REGISFLOAT, "Invalid SSEx66 usage.");
static_assert(RMSIZE >= 4 && REGSIZE >= 4, "Invalid ScalarSSE integer register."); // Floats would error out before this point.
// Use the source size to decide on the prefix if it's a float.
// Otherwise, the target is a float so check its size.
if ((RMISFLOAT && RMSIZE == 8)
|| (!RMISFLOAT && REGSIZE == 8))
{
Emit8(0x66);
}
}
template <unsigned SIZE1, bool ISFLOAT1, unsigned SIZE2, bool ISFLOAT2>
void X64CodeGenerator::EmitSSEx66PrefixDirect(Register<SIZE1, ISFLOAT1> dest,
Register<SIZE2, ISFLOAT2> src)
{
EmitSSEx66Prefix<SIZE2, ISFLOAT2>(dest, src);
}
template <unsigned RMSIZE, bool RMISFLOAT, unsigned REGSIZE, bool REGISFLOAT>
void X64CodeGenerator::EmitSSEx66PrefixIndirect(Register<REGSIZE, REGISFLOAT> reg, Register<8, false> rm)
{
EmitSSEx66Prefix<RMSIZE, RMISFLOAT>(reg, rm);
}
template <uint8_t OPCODE, unsigned SIZE1, bool ISFLOAT1, unsigned SIZE2, bool ISFLOAT2>
void X64CodeGenerator::SSEx66(Register<SIZE1, ISFLOAT1> dest, Register<SIZE2, ISFLOAT2> src)
{
EmitSSEx66PrefixDirect(dest, src);
EmitRexDirect(dest, src);
Emit8(0x0f);
Emit8(OPCODE);
EmitModRM(dest, src);
}
template <uint8_t OPCODE, unsigned SIZE1, bool ISFLOAT1, unsigned SIZE2, bool ISFLOAT2>
void X64CodeGenerator::SSEx66(Register<SIZE1, ISFLOAT1> dest,
Register<8, false> src,
int32_t srcOffset)
{
EmitSSEx66PrefixIndirect<SIZE2, ISFLOAT2>(dest, src);
EmitRexIndirect<SIZE2, ISFLOAT2>(dest, src);
Emit8(0x0f);
Emit8(OPCODE);
EmitModRMOffset(dest, src, srcOffset);
}
template <uint8_t OPCODE, unsigned SIZE1, bool ISFLOAT1, unsigned SIZE2, bool ISFLOAT2>
void X64CodeGenerator::SSEx66(Register<8, false> dest,
int32_t destOffset,
Register<SIZE2, ISFLOAT2> src)
{
// Note: operand encoding is MR, so the order of arguments for the
// Emit*() methods is reversed.
EmitSSEx66PrefixIndirect<SIZE1, ISFLOAT1>(src, dest);
EmitRexIndirect<SIZE1, ISFLOAT1>(src, dest);
Emit8(0x0f);
Emit8(OPCODE);
EmitModRMOffset(src, dest, destOffset);
}
//
// X64 group1 opcodes
//
template <unsigned SIZE>
void X64CodeGenerator::Group1(uint8_t baseOpCode,
Register<SIZE, false> dest,
Register<SIZE, false> src)
{
EmitOpSizeOverrideDirect(dest, src);
EmitRexDirect(dest, src);
if (SIZE == 1)
{
Emit8(baseOpCode + 0x2);
}
else
{
Emit8(baseOpCode + 0x3);
}
EmitModRM(dest, src);
}
template <unsigned SIZE>
void X64CodeGenerator::Group1(uint8_t baseOpCode,
Register<SIZE, false> dest,
Register<8, false> src,
int32_t srcOffset)
{
EmitOpSizeOverrideIndirect<SIZE, false>(dest, src);
EmitRexIndirect<SIZE, false>(dest, src);
if (SIZE == 1)
{
Emit8(baseOpCode + 0x2);
}
else
{
Emit8(baseOpCode + 0x3);
}
EmitModRMOffset(dest, src, srcOffset);
}
inline uint8_t Mod(int32_t offset)
{
if (offset == 0)
{
return 0;
}
else if (offset >= -0x80 && offset <= 0x7f)
{
return 1;
}
else
{
return 2;
}
}
template <unsigned SIZE>
void X64CodeGenerator::Group1(uint8_t baseOpCode,
Register<SIZE, false> dest,
Register<8, false> base,
Register<8, false> index,
SIB scale,
int32_t offset)
{
EmitOpSizeOverrideIndirect<SIZE, false>(dest, base);
//
// Emit rex
//
const bool w = (SIZE == 8);
Emit8(0x40
| (w ? 8 : 0)
| (dest.IsExtended() ? 4 : 0)
| (index.IsExtended() ? 2 : 0)
| (base.IsExtended() ? 1 : 0));
//
// Emit opcode
//
if (SIZE == 1)
{
Emit8(baseOpCode + 0x2);
}
else
{
Emit8(baseOpCode + 0x3);
}
//
// Emit mod/rm
//
uint8_t mod = Mod(offset);
const uint8_t baseField = base.GetId8();
const uint8_t destField = dest.GetId8();
const uint8_t indexField = index.GetId8();
Emit8((mod << 6) | (destField << 3) | 4);
//
// Emit SIB
//
const uint8_t s = static_cast<uint8_t>(scale);
Emit8((s << 6) | (indexField << 3) | baseField);
//
// Emit offset
//
if (mod == 1)
{
Emit8(static_cast<uint8_t>(offset));
}
else if (mod == 2)
{
Emit32(offset);
}
}
template <unsigned SIZE>
void X64CodeGenerator::Group1(uint8_t baseOpCode,
Register<8, false> dest,
int32_t destOffset,
Register<SIZE, false> src)
{
// Note: operand encoding is MR, so the order of arguments for the
// Emit*() methods is reversed.
EmitOpSizeOverrideIndirect<SIZE, false>(src, dest);
EmitRexIndirect<SIZE, false>(src, dest);
if (SIZE == 1)
{
Emit8(baseOpCode);
}
else
{
Emit8(baseOpCode + 0x1);
}
EmitModRMOffset(src, dest, destOffset);
}
template <unsigned SIZE>
void X64CodeGenerator::Group1(uint8_t baseOpCode,
Register<8, false> base,
Register<8, false> index,
SIB scale,
int32_t offset,
Register<SIZE, false> src)
{
EmitOpSizeOverrideIndirect<SIZE, false>(src, base);
//
// Emit rex
//
const bool w = (SIZE == 8);
Emit8(0x40
| (w ? 8 : 0)
| (src.IsExtended() ? 4 : 0)
| (index.IsExtended() ? 2 : 0)
| (base.IsExtended() ? 1 : 0));
//
// Emit opcode
//
if (SIZE == 1)
{
Emit8(baseOpCode);
}
else
{
Emit8(baseOpCode + 0x1);
}
//
// Emit mod/rm
//
uint8_t mod = Mod(offset);
const uint8_t baseField = base.GetId8();
const uint8_t destField = src.GetId8();
const uint8_t indexField = index.GetId8();
Emit8((mod << 6) | (destField << 3) | 4);
//
// Emit SIB
//
const uint8_t s = static_cast<uint8_t>(scale);
Emit8((s << 6) | (indexField << 3) | baseField);
//
// Emit offset
//
if (mod == 1)
{
Emit8(static_cast<uint8_t>(offset));
}
else if (mod == 2)
{
Emit32(offset);
}
}
template <unsigned SIZE, typename T>
void X64CodeGenerator::Group1(uint8_t baseOpCode,
uint8_t extensionOpCode,
Register<SIZE, false> dest,
T value)
{
static_assert(std::is_integral<T>::value, "Group1 opcodes work only with integral values.");
static_assert(sizeof(T) <= SIZE, "Invalid size of the immediate.");
static_assert(sizeof(T) < 8, "Group1 instructions don't support 64-bit immediates.");
static_assert(!(SIZE == 8 && sizeof(T) == 4 && std::is_unsigned<T>::value),
"Cannot safely use 32-bit unsigned immediate with 64-bit register, "
"sign extension would have been used.");
unsigned valueSize = Size(value);
EmitOpSizeOverride(dest);
if (dest.GetId() == 0 && SIZE == 1)
{
// Special case for AL.
Emit8(baseOpCode + 0x04);
Emit8(static_cast<uint8_t>(value));
}
else if (dest.GetId() == 0 && valueSize != 1)
{
EmitRex(dest);
Emit8(baseOpCode + 0x05);
if (SIZE == 2)
{
Emit16(static_cast<uint16_t>(value));
}
else
{
// Note: in case of 64-bit register (RAX) and 32-bit immediate,
// the opcode used above will sign-extend the immediate. This is
// OK since the earlier static assert verifies that if a 32-bit
// immediate is used in such case, its type must be signed.
// Any sign-extension will thus be intended in this case.
Emit32(static_cast<uint32_t>(value));
}
}
else
{
EmitRex(dest);
// For an immediate fitting in 1-byte, use the sign-extend flavor of
// the opcode only if it's irrelevant (target is also 1 byte) or if
// it is OK to do so (the value is signed and negative or the bit
// #7 is clear).
if (valueSize <= 1
&& (SIZE == 1
|| (static_cast<int64_t>(value) < 0
|| !BitOp::TestBit(static_cast<uint64_t>(value), 7))))
{
if (SIZE == 1)
{
Emit8(0x80);
}
else
{
Emit8(0x83);
}
EmitModRM(extensionOpCode, dest);
Emit8(static_cast<uint8_t>(value));
}
else // if (valueSize <= 4)
{
Emit8(0x81);
EmitModRM(extensionOpCode, dest);
if (SIZE == 2)
{
Emit16(static_cast<uint16_t>(value));
}
else
{
// This will sign-extend the immediate if 64-bit register
// is used. See the comment inside the topmost else branch
// for RAX for details on why is that OK.
Emit32(static_cast<uint32_t>(value));
}
}
}
}
//
// X64 group2 opcodes
//
template <unsigned SIZE>
void X64CodeGenerator::Group2(uint8_t extensionOpCode,
Register<SIZE, false> dest)
{
EmitOpSizeOverride(dest);
EmitRex(dest);
if (SIZE == 1)
{
Emit8(0xd2);
}
else
{
Emit8(0xd3);
}
EmitModRM(extensionOpCode, dest);
}
// Coalesce with previous by calling previous before emitting shift.
template <unsigned SIZE>
void X64CodeGenerator::Group2(uint8_t extensionOpCode,
uint8_t shift,
Register<SIZE, false> dest)
{
EmitOpSizeOverride(dest);
EmitRex(dest);
if (SIZE == 1)
{
Emit8(0xc0);
}
else
{
Emit8(0xc1);
}
EmitModRM(extensionOpCode, dest);
Emit8(shift);
}
//
// X64 group 5 opcodes.
//
template <unsigned SIZE>
void X64CodeGenerator::Group3And5(uint8_t opcode,
uint8_t extensionOpCode,
Register<SIZE, false> dest)
{
EmitOpSizeOverride(dest);
EmitRex(dest);
if (SIZE == 1)
{
Emit8(opcode);
}
else
{
Emit8(opcode + 1u);
}
EmitModRM(extensionOpCode, dest);
}
template <unsigned SIZE>
void X64CodeGenerator::Group3And5(uint8_t opcode,
uint8_t extensionOpCode,
Register<8u, false> dest,
int32_t offset)
{
EmitOpSizeOverride(Register<SIZE, false>(0));
EmitRex<SIZE, false>(Register<SIZE, false>(0), dest);
if (SIZE == 1)
{
Emit8(opcode);
}
else
{
Emit8(opcode + 1u);
}
EmitModRMOffset(Register<8u, false>(extensionOpCode), dest, offset);
}
//
// Bit operation opcodes.
//
template <unsigned SIZE>
void X64CodeGenerator::GroupBitOps(uint8_t opcode,
Register<SIZE, false> dest,
Register<SIZE, false> bit)
{
EmitOpSizeOverride(Register<SIZE, false>(0));
if (opcode == 0xbc || opcode == 0xbd)
{
EmitRex<SIZE, false>(dest, bit);
Emit8(0x0f);
Emit8(opcode);
EmitModRM(dest, bit);
}
else
{
EmitRex<SIZE, false>(bit, dest);
Emit8(0x0f);
Emit8(opcode);
EmitModRM(bit, dest);
}
}
//
// X64 opcode encoding - operand size override.
//
template <unsigned RMSIZE, bool RMISFLOAT,
unsigned REGSIZE, bool REGISFLOAT,
unsigned RMREGSIZE, bool RMREGISFLOAT>
void X64CodeGenerator::EmitOpSizeOverride(Register<REGSIZE, REGISFLOAT> /* reg */,
Register<RMREGSIZE, RMREGISFLOAT> /* rm */)
{
static_assert((RMSIZE == RMREGSIZE && RMISFLOAT == RMREGISFLOAT)
|| (RMREGSIZE == 8 && !RMREGISFLOAT),
"Only direct addressing or indirect addresing with 64-bit "
"general purpose base register can be used.");
// Emit operand size override prefix if necessary.
// Note: address size override prefix (0x67) is not considered since
// we don't support 32-bit indirects.
if (RMSIZE == 2 || REGSIZE == 2)
{
Emit8(0x66);
}
}
template <unsigned SIZE, bool ISFLOAT>
void X64CodeGenerator::EmitOpSizeOverride(Register<SIZE, ISFLOAT> reg)
{
EmitOpSizeOverride<SIZE, ISFLOAT>(reg, reg);
}
template <unsigned SIZE1, bool ISFLOAT1, unsigned SIZE2, bool ISFLOAT2>
void X64CodeGenerator::EmitOpSizeOverrideDirect(Register<SIZE1, ISFLOAT1> dest,
Register<SIZE2, ISFLOAT2> src)
{
EmitOpSizeOverride<SIZE2, ISFLOAT2>(dest, src);
}
template <unsigned RMSIZE, bool RMISFLOAT>
void X64CodeGenerator::EmitOpSizeOverrideIndirect(Register<8, false> rm)
{
EmitOpSizeOverride<RMSIZE, RMISFLOAT>(Register<RMSIZE, RMISFLOAT>(), rm);
}
template <unsigned RMSIZE, bool RMISFLOAT, unsigned REGSIZE, bool REGISFLOAT>
void X64CodeGenerator::EmitOpSizeOverrideIndirect(Register<REGSIZE, REGISFLOAT> reg,
Register<8, false> rm)
{
EmitOpSizeOverride<RMSIZE, RMISFLOAT>(reg, rm);
}
//
// X64 opcode encoding - REX.
//
template <unsigned RMSIZE, bool RMISFLOAT,
unsigned REGSIZE, bool REGISFLOAT,
unsigned RMREGSIZE, bool RMREGISFLOAT>
void X64CodeGenerator::EmitRex(Register<REGSIZE, REGISFLOAT> reg,
Register<RMREGSIZE, RMREGISFLOAT> rm)
{
static_assert((RMSIZE == RMREGSIZE && RMISFLOAT == RMREGISFLOAT)
|| (RMREGSIZE == 8 && !RMREGISFLOAT),
"Only direct addressing or indirect addresing with 64-bit "
"general purpose base register can be used.");
// This code currently doesn't support the REX.X bit.
// REX.X is an extra bit for the SIB index field. SIB is scale index
// base (think `lea`). We don't currently support this addressing
// mode. The old assembler might support SIB?
//
// Note that the REX.W bit is never set when two floating point operands
// are used.
//
// In the indirect mode, the size and type of the R/M operand are
// determined by the size and type of the target memory area (given
// that the base register is always a general purpose register and size
// in our case always 8).
const bool w = (REGSIZE == 8 && !REGISFLOAT) || (RMSIZE == 8 && !RMISFLOAT);
// When spl, bpl, sil or dil are used, at least an empty REX byte must
// be emitted. Otherwise, these registers would be treated as ah, ch, dh
// and bh respectively.
const bool forceRex = (reg == spl || reg == bpl || reg == sil || reg == dil)
|| (rm == spl || rm == bpl || rm == sil || rm == dil);
if (forceRex || w || reg.IsExtended() || rm.IsExtended())
{
// WRXB
Emit8(0x40
| (w ? 8 : 0)
| (reg.IsExtended() ? 4 : 0)
| (rm.IsExtended() ? 1 : 0));
}
}
template <unsigned SIZE, bool ISFLOAT>
void X64CodeGenerator::EmitRex(Register<SIZE, ISFLOAT> reg)
{
// Use eax for the other register since it will not affect any of the REX flags.
EmitRex<SIZE, ISFLOAT>(eax, reg);
}
template <unsigned SIZE1, bool ISFLOAT1, unsigned SIZE2, bool ISFLOAT2>
void X64CodeGenerator::EmitRexDirect(Register<SIZE1, ISFLOAT1> dest, Register<SIZE2, ISFLOAT2> src)
{
EmitRex<SIZE2, ISFLOAT2>(dest, src);
}
template <unsigned RMSIZE, bool RMISFLOAT>
void X64CodeGenerator::EmitRexIndirect(Register<8, false> rm)
{
// Use eax for the other register since it will not affect any of the REX flags.
EmitRex<RMSIZE, RMISFLOAT>(eax, rm);
}
template <unsigned RMSIZE, bool RMISFLOAT, unsigned REGSIZE, bool REGISFLOAT>
void X64CodeGenerator::EmitRexIndirect(Register<REGSIZE, REGISFLOAT> reg, Register<8, false> rm)
{
EmitRex<RMSIZE, RMISFLOAT>(reg, rm);
}
//
// X64 opcode encoding - ModR/M.
//
template <unsigned SIZE1, bool ISFLOAT1, unsigned SIZE2, bool ISFLOAT2>
void X64CodeGenerator::EmitModRM(Register<SIZE1, ISFLOAT1> dest, Register<SIZE2, ISFLOAT2> src)
{
Emit8(0xc0 | (dest.GetId8() << 3) | src.GetId8());
// BUGBUG: check special cases for RSP, R12. Shouldn't be necessary here if
// this function is only used for Register-Register encoding. Problem will
// crop up if caller passes the base register from an X64Indirect.
}
template <unsigned SIZE>
void X64CodeGenerator::EmitModRM(uint8_t extensionOpCode, Register<SIZE, false> dest)
{
Emit8(0xc0 | (extensionOpCode << 3) | dest.GetId8());
// BUGBUG: check special cases for RSP, R12. Shouldn't be necessary here if
// this function is only used for Register-Register encoding. Problem will
// crop up if caller passes the base register from an X64Indirect.
}
template <unsigned SIZE, bool ISFLOAT>
void X64CodeGenerator::EmitModRMOffset(Register<SIZE, ISFLOAT> reg,
Register<8, false> rm,
int32_t offset)
{
if (rm.IsRIP())
{
// RIP-relative addressing. Hard-code mod = 0 and rmField = 5.
const uint8_t mod = 0;
const uint8_t rmField = 5;
const uint8_t regField = reg.GetId8();
Emit8((mod << 6) | (regField << 3) | rmField);
Emit32(offset - CurrentPosition() - 4);
}
else
{
// Normal, GPR-indirect addressing.
uint8_t mod = Mod(offset);
const uint8_t rmField = rm.GetId8();
const uint8_t regField = reg.GetId8();
if (rmField == 5 && mod == 0)
{
// The combination of rmField == 5 && mod == 0 is a special case
// which is used for RIP-relative addressing. Convert to mod 01
// and emit an 8-bit displacement of 0.
mod = 1;
}
Emit8((mod << 6) | (regField << 3) | rmField);
if (rmField == 4)
{
// When rm is RSP or R12 or XMM4 or XMM12, rmField == 4, which
// is a special case used for SIB addressing. Emit an SIB byte
// which encodes the same register with no scaled index.
// Want SS = 00, Index = 100 (none), and Base = 100 (4).
Emit8(0x24);
}
if (mod == 1)
{
Emit8(static_cast<uint8_t>(offset));
}
else if (mod == 2)
{
Emit32(offset);
}
}
}
//*************************************************************************
//
// X64CodeGenerator::Helper definitions for each opcode and addressing mode.
//
//*************************************************************************
//
// Bit operations
//
template <>
template <>
template <unsigned SIZE>
void X64CodeGenerator::Helper<OpCode::Bsf>::ArgTypes1<false>::Emit(
X64CodeGenerator& code,
Register<SIZE, false> dest,
Register<SIZE, false> bit)
{
code.GroupBitOps(0xbc, dest, bit);
}
template <>
template <>
template <unsigned SIZE>
void X64CodeGenerator::Helper<OpCode::Bsr>::ArgTypes1<false>::Emit(
X64CodeGenerator& code,
Register<SIZE, false> dest,
Register<SIZE, false> bit)
{
code.GroupBitOps(0xbd, dest, bit);
}
template <>
template <>
template <unsigned SIZE>
void X64CodeGenerator::Helper<OpCode::Bt>::ArgTypes1<false>::Emit(
X64CodeGenerator& code,
Register<SIZE, false> dest,
Register<SIZE, false> bit)
{
code.GroupBitOps(0xa3, dest, bit);
}
template <>
template <>
template <unsigned SIZE>
void X64CodeGenerator::Helper<OpCode::Btc>::ArgTypes1<false>::Emit(
X64CodeGenerator& code,
Register<SIZE, false> dest,
Register<SIZE, false> bit)
{
code.GroupBitOps(0xbb, dest, bit);
}
template <>
template <>
template <unsigned SIZE>
void X64CodeGenerator::Helper<OpCode::Btr>::ArgTypes1<false>::Emit(
X64CodeGenerator& code,
Register<SIZE, false> dest,
Register<SIZE, false> bit)
{
code.GroupBitOps(0xb3, dest, bit);
}
template <>
template <>
template <unsigned SIZE>
void X64CodeGenerator::Helper<OpCode::Bts>::ArgTypes1<false>::Emit(
X64CodeGenerator& code,
Register<SIZE, false> dest,
Register<SIZE, false> bit)
{
code.GroupBitOps(0xab, dest, bit);
}
//
// Dec
//
template <>
template <>
template <unsigned SIZE>
void X64CodeGenerator::Helper<OpCode::Dec>::ArgTypes1<false>::Emit(
X64CodeGenerator& code,
Register<SIZE, false> dest)
{
code.Group3And5(0xfe, 1, dest);
}
template <>
template <unsigned SIZE>
void X64CodeGenerator::Helper<OpCode::Dec>::ArgTypes0::Emit(
X64CodeGenerator& code,
Register<8u, false> base,
int32_t offset)
{
code.Group3And5<SIZE>(0xfe, 1, base, offset);
}
//
// Inc
//
template <>
template <>
template <unsigned SIZE>
void X64CodeGenerator::Helper<OpCode::Inc>::ArgTypes1<false>::Emit(
X64CodeGenerator& code,
Register<SIZE, false> dest)
{
code.Group3And5(0xfe, 0, dest);
}
template <>
template <unsigned SIZE>
void X64CodeGenerator::Helper<OpCode::Inc>::ArgTypes0::Emit(
X64CodeGenerator& code,
Register<8u, false> base,
int32_t offset)
{
code.Group3And5<SIZE>(0xfe, 0, base, offset);
}
//
// Neg
//
template <>
template <>
template <unsigned SIZE>
void X64CodeGenerator::Helper<OpCode::Neg>::ArgTypes1<false>::Emit(
X64CodeGenerator& code,
Register<SIZE, false> dest)
{
code.Group3And5(0xf6, 3, dest);
}
template <>
template <unsigned SIZE>
void X64CodeGenerator::Helper<OpCode::Neg>::ArgTypes0::Emit(
X64CodeGenerator& code,
Register<8u, false> base,
int32_t offset)
{
code.Group3And5<SIZE>(0xf6, 3, base, offset);
}
//
// Not
//
template <>
template <>
template <unsigned SIZE>
void X64CodeGenerator::Helper<OpCode::Not>::ArgTypes1<false>::Emit(
X64CodeGenerator& code,
Register<SIZE, false> dest)
{
code.Group3And5(0xf6, 2, dest);
}
template <>
template <unsigned SIZE>
void X64CodeGenerator::Helper<OpCode::Not>::ArgTypes0::Emit(
X64CodeGenerator& code,
Register<8u, false> base,
int32_t offset)
{
code.Group3And5<SIZE>(0xf6, 2, base, offset);
}
//
// Lea
//
template <>
template <>
template <unsigned SIZE>
void X64CodeGenerator::Helper<OpCode::Lea>::ArgTypes1<false>::Emit(
X64CodeGenerator& code,
Register<SIZE, false> dest,
Register<8, false> src,
int32_t srcOffset)
{
code.Lea(dest, src, srcOffset);
}
//
// Mov
//
template <>
template <>
template <unsigned SIZE>
void X64CodeGenerator::Helper<OpCode::Mov>::ArgTypes1<false>::Emit(
X64CodeGenerator& code,
Register<SIZE, false> dest,
Register<SIZE, false> src)
{
code.Group1(0x88, dest, src);
}
template <>
template <>
template <unsigned SIZE>
void X64CodeGenerator::Helper<OpCode::Mov>::ArgTypes1<false>::Emit(
X64CodeGenerator& code,
Register<SIZE, false> dest,
Register<8, false> src,
int32_t srcOffset)
{
code.Group1(0x88, dest, src, srcOffset);
}
template <>
template <>
template <unsigned SIZE>
void X64CodeGenerator::Helper<OpCode::Mov>::ArgTypes1<false>::Emit(
X64CodeGenerator& code,
Register<SIZE, false> dest,
Register<8, false> base,
Register<8, false> index,
SIB scale,
int32_t srcOffset)
{
code.Group1(0x88, dest, base, index, scale, srcOffset);
}
template <>
template <>
template <unsigned SIZE>
void X64CodeGenerator::Helper<OpCode::Mov>::ArgTypes1<false>::Emit(
X64CodeGenerator& code,
Register<8, false> dest,
int32_t destOffset,
Register<SIZE, false> src)
{
code.Group1(0x88, dest, destOffset, src);
}
template <>
template <>
template <unsigned SIZE>
void X64CodeGenerator::Helper<OpCode::Mov>::ArgTypes1<false>::Emit(
X64CodeGenerator& code,
Register<8, false> base,
Register<8, false> index,
SIB scale,
int32_t offset,
Register<SIZE, false> src)
{
code.Group1(0x88, base, index, scale, offset, src);
}
template <>
template <>
template <unsigned SIZE, typename T>
void X64CodeGenerator::Helper<OpCode::Mov>::ArgTypes1<false>::EmitImmediate(
X64CodeGenerator& code,
Register<SIZE, false> dest,
T value)
{
code.MovImmediate(dest, value);
}
template <>
template <>
template <unsigned SIZE1, unsigned SIZE2>
void X64CodeGenerator::Helper<OpCode::Mov>::ArgTypes2<true, false>::Emit(
X64CodeGenerator& code,
Register<SIZE1, true> dest,
Register<SIZE2, false> src)
{
code.MovD(dest, src);
}
template <>
template <>
template <unsigned SIZE>
void X64CodeGenerator::Helper<OpCode::Mov>::ArgTypes1<true>::Emit(
X64CodeGenerator& code,
Register<8, false> dest,
int32_t destOffset,
Register<SIZE, true> src)
{
// MovSS/SD.
code.ScalarSSE<0x11, SIZE, true, SIZE, true>(dest, destOffset, src);
}
//
// Mul
//
template <>
template <>
template <unsigned SIZE>
void X64CodeGenerator::Helper<OpCode::IMul>::ArgTypes1<false>::Emit(
X64CodeGenerator& code,
Register<SIZE, false> dest,
Register<SIZE, false> src)
{
code.IMul(dest, src);
}
template <>
template <>
template <unsigned SIZE>
void X64CodeGenerator::Helper<OpCode::IMul>::ArgTypes1<false>::Emit(
X64CodeGenerator& code,
Register<SIZE, false> dest,
Register<8, false> src,
int32_t srcOffset)
{
code.IMul(dest, src, srcOffset);
}
template <>
template <>
template <unsigned SIZE, typename T>
void X64CodeGenerator::Helper<OpCode::IMul>::ArgTypes1<false>::EmitImmediate(
X64CodeGenerator& code,
Register<SIZE, false> dest,
T value)
{
code.IMulImmediate(dest, value);
}
//
// MovSX
//
template <>
template <>
template <unsigned SIZE1, unsigned SIZE2>
void X64CodeGenerator::Helper<OpCode::MovSX>::ArgTypes2<false, false>::Emit(
X64CodeGenerator& code,
Register<SIZE1, false> dest,
Register<SIZE2, false> src)
{
code.MovSX(dest, src);
}
template <>
template <>
template <unsigned SIZE1, unsigned SIZE2>
void X64CodeGenerator::Helper<OpCode::MovSX>::ArgTypes2<false, false>::Emit(
X64CodeGenerator& code,
Register<SIZE1, false> dest,
Register<8, false> src,
int32_t srcOffset)
{
code.MovSX<SIZE1, SIZE2>(dest, src, srcOffset);
}
//
// MovZX
//
template <>
template <>
template <unsigned SIZE1, unsigned SIZE2>
void X64CodeGenerator::Helper<OpCode::MovZX>::ArgTypes2<false, false>::Emit(
X64CodeGenerator& code,
Register<SIZE1, false> dest,
Register<SIZE2, false> src)
{
code.MovZX(dest, src);
}
// There is no "movzx dest64, src32" instruction, MovZX opcode for this
// combination is implemented in terms of "mov dest32, src32" using full
// template specialization.
template <>
template <>
template <>
void X64CodeGenerator::Helper<OpCode::MovZX>::ArgTypes2<false, false>::Emit<8, 4>(
X64CodeGenerator& code,
Register<8, false> dest,
Register<4, false> src);
template <>
template <>
template <unsigned SIZE1, unsigned SIZE2>
void X64CodeGenerator::Helper<OpCode::MovZX>::ArgTypes2<false, false>::Emit(
X64CodeGenerator& code,
Register<SIZE1, false> dest,
Register<8, false> src,
int32_t srcOffset)
{
code.MovZX<SIZE1, SIZE2>(dest, src, srcOffset);
}
template <>
template <>
template <>
void X64CodeGenerator::Helper<OpCode::MovZX>::ArgTypes2<false, false>::Emit<8, 4>(
X64CodeGenerator& code,
Register<8, false> dest,
Register<8, false> src,
int32_t srcOffset);
//
// Shld
//
template <>
template <>
template <unsigned SIZE, typename T>
void X64CodeGenerator::Helper<OpCode::Shld>::ArgTypes1<false>::EmitImmediate(
X64CodeGenerator& code,
Register<SIZE, false> dest,
Register<SIZE, false> src,
T bitCount)
{
code.Shld(dest, src, bitCount);
}
template <>
template <>
template <unsigned SIZE>
void X64CodeGenerator::Helper<OpCode::Shld>::ArgTypes1<false>::Emit(
X64CodeGenerator& code,
Register<SIZE, false> dest,
Register<SIZE, false> src)
{
code.Shld(dest, src);
}
#define DEFINE_GROUP1(name, baseOpCode, extensionOpCode) \
template <> \
template <> \
template <unsigned SIZE> \
void X64CodeGenerator::Helper<OpCode::name>::ArgTypes1<false>::Emit( \
X64CodeGenerator& code, \
Register<SIZE, false> dest, \
Register<SIZE, false> src) \
{ \
code.Group1(baseOpCode, dest, src); \
} \
\
\
template <> \
template <> \
template <unsigned SIZE> \
void X64CodeGenerator::Helper<OpCode::name>::ArgTypes1<false>::Emit( \
X64CodeGenerator& code, \
Register<SIZE, false> dest, \
Register<8, false> src, \
int32_t srcOffset) \
{ \
code.Group1(baseOpCode, dest, src, srcOffset); \
} \
\
\
template <> \
template <> \
template <unsigned SIZE> \
void X64CodeGenerator::Helper<OpCode::name>::ArgTypes1<false>::Emit( \
X64CodeGenerator& code, \
Register<SIZE, false> dest, \
Register<8, false> base, \
Register<8, false> index, \
SIB scale, \
int32_t srcOffset) \
{ \
code.Group1(baseOpCode, dest, base, index, scale, srcOffset); \
} \
\
\
template <> \
template <> \
template <unsigned SIZE> \
void X64CodeGenerator::Helper<OpCode::name>::ArgTypes1<false>::Emit( \
X64CodeGenerator& code, \
Register<8, false> dest, \
int32_t destOffset, \
Register<SIZE, false> src) \
{ \
code.Group1(baseOpCode, dest, destOffset, src); \
} \
\
\
template <> \
template <> \
template <unsigned SIZE> \
void X64CodeGenerator::Helper<OpCode::name>::ArgTypes1<false>::Emit( \
X64CodeGenerator& code, \
Register<8, false> base, \
Register<8, false> index, \
SIB scale, \
int32_t offset, \
Register<SIZE, false> src) \
{ \
code.Group1(baseOpCode, base, index, scale, offset, src); \
} \
\
\
template <> \
template <> \
template <unsigned SIZE, typename T> \
void X64CodeGenerator::Helper<OpCode::name>::ArgTypes1<false>::EmitImmediate( \
X64CodeGenerator& code, \
Register<SIZE, false> dest, \
T value) \
{ \
code.Group1(baseOpCode, extensionOpCode, dest, value); \
}
DEFINE_GROUP1(Add, 0, 0);
DEFINE_GROUP1(And, 0x20, 4);
DEFINE_GROUP1(Cmp, 0x38, 7);
DEFINE_GROUP1(Or, 8, 1);
DEFINE_GROUP1(Sub, 0x28, 5);
DEFINE_GROUP1(Xor, 0x30, 6);
#undef DEFINE_GROUP1
#define DEFINE_GROUP2(name, extensionOpCode) \
template <> \
template <> \
template <unsigned SIZE> \
void X64CodeGenerator::Helper<OpCode::name>::ArgTypes1<false>::Emit( \
X64CodeGenerator& code, \
Register<SIZE, false> dest) \
{ \
code.Group2(extensionOpCode, dest); \
} \
\
\
template <> \
template <> \
template <unsigned SIZE, typename T> \
void X64CodeGenerator::Helper<OpCode::name>::ArgTypes1<false>::EmitImmediate( \
X64CodeGenerator& code, \
Register<SIZE, false> dest, \
T value) \
{ \
code.Group2(extensionOpCode, value, dest); \
}
DEFINE_GROUP2(Rol, 0);
DEFINE_GROUP2(Shl, 4);
DEFINE_GROUP2(Shr, 5);
#undef DEFINE_GROUP2
// SSE instruction, both arguments of the same type and size.
#define DEFINE_SSE_ARGS1(name, emitMethod, opcode) \
template <> \
template <> \
template <unsigned SIZE> \
void X64CodeGenerator::Helper<OpCode::name>::ArgTypes1<true>::Emit( \
X64CodeGenerator& code, \
Register<SIZE, true> dest, \
Register<SIZE, true> src) \
{ \
code.emitMethod<opcode>(dest, src); \
} \
\
\
template <> \
template <> \
template <unsigned SIZE> \
void X64CodeGenerator::Helper<OpCode::name>::ArgTypes1<true>::Emit( \
X64CodeGenerator& code, \
Register<SIZE, true> dest, \
Register<8, false> src, \
int32_t srcOffset) \
{ \
code.emitMethod<opcode, SIZE, true, SIZE, true>(dest, src, srcOffset); \
} \
DEFINE_SSE_ARGS1(Add, ScalarSSE, 0x58); // AddSS/AddSD.
DEFINE_SSE_ARGS1(Cmp, SSEx66, 0x2f); // ComISS/ComISD.
DEFINE_SSE_ARGS1(IMul, ScalarSSE, 0x59); // MulSS/MulSD.
DEFINE_SSE_ARGS1(Mov, ScalarSSE, 0x10); // MovSS/MovSD.
DEFINE_SSE_ARGS1(MovAP, SSEx66, 0x28); // MovAPS/MovAPD.
DEFINE_SSE_ARGS1(Sub, ScalarSSE, 0x5c); // SubSS/SubSD.
#undef DEFINE_SSE_ARGS1
// Unlike others, MovAPS/MovAPD also have the "mov [rxx + 16], xmm" form
// of the instruction with a different opcode.
template <>
template <>
template <unsigned SIZE>
void X64CodeGenerator::Helper<OpCode::MovAP>::ArgTypes1<true>::Emit(
X64CodeGenerator& code,
Register<8, false> dest,
int32_t destOffset,
Register<SIZE, true> src)
{
code.SSEx66<0x29, SIZE, true, SIZE, true>(dest, destOffset, src);
}
// SSE instruction, arguments of different type or size.
#define DEFINE_SSE_ARGS2(name, emitMethod, opcode, type1, type2, validityCondition) \
template <> \
template <> \
template <unsigned SIZE1, unsigned SIZE2> \
void X64CodeGenerator::Helper<OpCode::name>::ArgTypes2<type1, type2>::Emit( \
X64CodeGenerator& code, \
Register<SIZE1, type1> dest, \
Register<SIZE2, type2> src) \
{ \
static_assert(validityCondition, \
"Invalid " #name " instruction, must be " #validityCondition); \
code.emitMethod<opcode, SIZE1, type1, SIZE2, type2>(dest, src); \
} \
\
\
template <> \
template <> \
template <unsigned SIZE1, unsigned SIZE2> \
void X64CodeGenerator::Helper<OpCode::name>::ArgTypes2<type1, type2>::Emit( \
X64CodeGenerator& code, \
Register<SIZE1, type1> dest, \
Register<8, false> src, \
int32_t srcOffset) \
{ \
static_assert(validityCondition, \
"Invalid " #name " instruction, must be " #validityCondition); \
code.emitMethod<opcode, SIZE1, type1, SIZE2, type2>(dest, src, srcOffset); \
} \
DEFINE_SSE_ARGS2(CvtSI2FP, ScalarSSE, 0x2A, true, false, SIZE2 >= 4); // CvtSI2SD/CvtSI2SS (convert signed int to floating point).
DEFINE_SSE_ARGS2(CvtFP2SI, ScalarSSE, 0x2C, false, true, SIZE1 >= 4); // CvtTSD2SI/CvtTSS2SI (convert floating point to signed int with truncation).
DEFINE_SSE_ARGS2(CvtFP2FP, ScalarSSE, 0x5A, true, true, SIZE1 != SIZE2); // CvtSS2SD/CvtSD2SS (convert float to double and vice versa).
#undef DEFINE_SCALAR_SSE2
}
#ifdef _MSC_VER
#pragma warning(pop)
#endif
``` | /content/code_sandbox/inc/NativeJIT/CodeGen/X64CodeGenerator.h | objective-c | 2016-04-09T23:53:19 | 2024-06-29T07:05:56 | NativeJIT | BitFunnel/NativeJIT | 1,133 | 23,205 |
```objective-c
// Permission is hereby granted, free of charge, to any person obtaining a copy
// of this software and associated documentation files (the "Software"), to deal
// in the Software without restriction, including without limitation the rights
// to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
// copies of the Software, and to permit persons to whom the Software is
// furnished to do so, subject to the following conditions:
// The above copyright notice and this permission notice shall be included in
// all copies or substantial portions of the Software.
// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
// AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
// LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
// OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
// THE SOFTWARE.
#pragma once
namespace NativeJIT
{
namespace CallingConvention
{
#ifdef NATIVEJIT_PLATFORM_WINDOWS
// Register masks of volatile integer and floating point registers.
// TODO: This could be replaced with constexpr: add operator| to Register and use it to define the masks.
// Note: RIP is included in volatiles.
static const unsigned c_rxxVolatileRegistersMask = 0xf07; // 1 0000 1111 0000 0111 (RAX | RCX | RDX | R8 | R9 | R10 | R11 | RIP)
static const unsigned c_xmmVolatileRegistersMask = 0x3f; // 0000 0000 0011 1111 (XMM0-XMM5)
// Register masks of non-volatile integer and floating point registers.
// Note: RIP not included.
static const unsigned c_rxxNonVolatileRegistersMask = 0xf0f8; // 0 1111 0000 1111 1000 (RBX | RSP | RBP | RSI | RDI | R12-R15)
static const unsigned c_xmmNonVolatileRegistersMask = 0xffc0; // 1111 1111 1100 0000 (XMM6-XMM15)
// Register masks of registers that can be written to.
static const unsigned c_rxxWritableRegistersMask = 0xFFFF; // Everything except RIP.
static const unsigned c_xmmWritableRegistersMask = 0xFFFF; // All XMM registers.
#else
// Register masks of volatile integer and floating point registers.
// TODO: This could be replaced with constexpr: add operator| to Register and use it to define the masks.
// Note: RIP is included in volatiles.
static const unsigned c_rxxVolatileRegistersMask = 0xfc7; // 1 0000 1111 1100 0111 (RAX | RCX | RDX | RSI | RDI | R8 | R9 | R10 | R11 | RIP)
static const unsigned c_xmmVolatileRegistersMask = 0xffff; // 1111 1111 1111 1111 (XMM0-XMM15)
// Register masks of non-volatile integer and floating point registers.
// Note: RIP not included.
static const unsigned c_rxxNonVolatileRegistersMask = 0xf038; // 0 1111 0000 0011 1000 (RBX | RSP | RBP | R12-R15)
static const unsigned c_xmmNonVolatileRegistersMask = 0x0000; // 0000 0000 0000 0000 (none)
// Register masks of registers that can be written to.
static const unsigned c_rxxWritableRegistersMask = 0xFFFF; // Everything except RIP.
static const unsigned c_xmmWritableRegistersMask = 0xFFFF; // All XMM registers.
#endif
static_assert((c_rxxNonVolatileRegistersMask ^ c_rxxVolatileRegistersMask) == 0xffff,
"Each register should appear exactly once in calling convention mask");
static_assert((c_xmmNonVolatileRegistersMask ^ c_xmmVolatileRegistersMask) == 0xffff,
"Each register should appear exactly once in calling convention mask");
}
}
``` | /content/code_sandbox/inc/NativeJIT/CodeGen/CallingConvention.h | objective-c | 2016-04-09T23:53:19 | 2024-06-29T07:05:56 | NativeJIT | BitFunnel/NativeJIT | 1,133 | 958 |
```objective-c
// Permission is hereby granted, free of charge, to any person obtaining a copy
// of this software and associated documentation files (the "Software"), to deal
// in the Software without restriction, including without limitation the rights
// to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
// copies of the Software, and to permit persons to whom the Software is
// furnished to do so, subject to the following conditions:
// The above copyright notice and this permission notice shall be included in
// all copies or substantial portions of the Software.
// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
// AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
// LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
// OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
// THE SOFTWARE.
#pragma once
#include <cstdint>
#include <vector> // Embedded member.
namespace NativeJIT
{
class CallSite;
class Label
{
public:
Label();
explicit Label(size_t id);
size_t GetId() const;
private:
size_t m_id;
};
// A JumpTable maintains collections of Labels and CallSites used in jump resolution.
class JumpTable
{
public:
JumpTable();
void Clear();
// Allocates a label that can be used as an argument to an X64 JCC/JMP/CALL instruction.
Label AllocateLabel();
// Binds a label to a memory address.
void PlaceLabel(Label label, const uint8_t* address);
// Records a position in memory containing call site (offset set portion of a JCC/JMP/CALL instruction)
// that will need to be patch once all labels have been placed.
void AddCallSite(Label label, uint8_t* site, unsigned size);
// Patches each call site with the correct offset derived from its resolved label.
void PatchCallSites();
bool LabelIsDefined(Label label) const;
const uint8_t* AddressOfLabel(Label label) const;
private:
// DESIGN NOTE: JumpTable is a part of CodeBuffer which is designed to
// be allocated once and reused multiple times during the program lifetime.
// Labels and call sites can thus use heap since the allocation (due to
// reserve()) will happen only at startup and perhaps very rarely be
// extended during the program lifetime.
std::vector<uint8_t const *> m_labels; // Storage for jump labels.
std::vector<CallSite> m_callSites; // Call sites to be patched.
};
// Call sites represent positions in memory which will contain jump offsets.
// These locations need to be patched after all label offsets are resolved.
class CallSite
{
public:
CallSite();
CallSite(Label label, unsigned size, uint8_t* site);
Label GetLabel() const;
size_t Size() const;
uint8_t* Site() const;
private:
Label m_label; // The jump label used to find the jump target address for this site.
size_t m_size; // The number of bytes to be patched at this site.
uint8_t* m_site; // The address to be patched.
};
}
``` | /content/code_sandbox/inc/NativeJIT/CodeGen/JumpTable.h | objective-c | 2016-04-09T23:53:19 | 2024-06-29T07:05:56 | NativeJIT | BitFunnel/NativeJIT | 1,133 | 735 |
```objective-c
// Permission is hereby granted, free of charge, to any person obtaining a copy
// of this software and associated documentation files (the "Software"), to deal
// in the Software without restriction, including without limitation the rights
// to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
// copies of the Software, and to permit persons to whom the Software is
// furnished to do so, subject to the following conditions:
// The above copyright notice and this permission notice shall be included in
// all copies or substantial portions of the Software.
// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
// AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
// LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
// OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
// THE SOFTWARE.
#pragma once
#ifdef NATIVEJIT_PLATFORM_WINDOWS
#include <windows.h> // RUNTIME_FUNCTION embedded.
#else
#include <cstdint>
typedef uint32_t DWORD;
typedef struct
{
DWORD BeginAddress;
DWORD EndAddress;
DWORD UnwindData;
} RUNTIME_FUNCTION;
#endif
#include "NativeJIT/CodeGen/X64CodeGenerator.h" // Inherits from X64CodeGenerator.
namespace NativeJIT
{
class FunctionSpecification;
class FunctionBuffer : public X64CodeGenerator
{
public:
// Sets up a code buffer with specified capacity and registers a
// callback to facilitate stack unwinding on exception. See the
// CodeBuffer constructor for more details on the allocator.
FunctionBuffer(Allocators::IAllocator& codeAllocator, unsigned capacity);
// Deregisters the stack unwinding callback.
~FunctionBuffer();
// Returns the entry point to the function, i.e. untyped function
// pointer.
void const * GetEntryPoint() const;
// The following functions return the information about the contents
// of the buffer. The offsets are relative to the beginning of the
// buffer. The start and end offset describe the [start, end) range
// containing the function's code (including prolog and epilog). The
// unwind info offset specifies where UnwinInfo is located.
// These calls are valid only after the function body has been generated.
unsigned GetFunctionCodeStartOffset() const;
unsigned GetFunctionCodeEndOffset() const;
unsigned GetUnwindInfoStartOffset() const;
// Called by clients to mark that generation of function's body has
// begun. If function specification is known even before the function
// body is generated, the exact space needed for unwind information and
// function prolog is reserved in front of the function body. Otherwise,
// the maximum allowed space is reserved. In both cases, no data is
// written for unwind info and prolog at this point.
void BeginFunctionBodyGeneration(FunctionSpecification const & spec);
void BeginFunctionBodyGeneration();
// Called by clients to mark that generation of function's body has
// completed. At this point, unwind info and prolog are filled in
// the space previously reserved by BeginFunctionBodyGeneration().
// Then, epilog is written after the function body and all call sites
// patched with the actual values.
void EndFunctionBodyGeneration(FunctionSpecification const & spec);
// Resets the buffer to the same state it had after its construction.
virtual void Reset() override;
private:
// Structure used to register stack unwind information with Windows.
RUNTIME_FUNCTION m_runtimeFunction;
// Temporary values used during compilation of the function. Offsets
// are relative to buffer start. When using BeginFunctionBodyGeneration()
// without parameters, the length values represent the reserved (maximum
// available) length for the respective section.
unsigned m_unwindInfoStartOffset;
unsigned m_unwindInfoByteLength;
unsigned m_prologStartOffset;
unsigned m_prologLength;
bool m_isCodeGenerationCompleted;
// The callback function for RtlInstallFunctionTableCallback. Context
// is a poiner to a FunctionBuffer.
#ifdef NATIVEJIT_PLATFORM_WINDOWS
static RUNTIME_FUNCTION*
WindowsGetRuntimeFunctionCallback(DWORD64 controlPc, void* context);
#endif
// A helper method used to implement the two public flavors of the method.
void BeginFunctionBodyGeneration(unsigned reservedUnwindInfoLength,
unsigned reservedPrologLength);
};
}
``` | /content/code_sandbox/inc/NativeJIT/CodeGen/FunctionBuffer.h | objective-c | 2016-04-09T23:53:19 | 2024-06-29T07:05:56 | NativeJIT | BitFunnel/NativeJIT | 1,133 | 981 |
```objective-c
// Permission is hereby granted, free of charge, to any person obtaining a copy
// of this software and associated documentation files (the "Software"), to deal
// in the Software without restriction, including without limitation the rights
// to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
// copies of the Software, and to permit persons to whom the Software is
// furnished to do so, subject to the following conditions:
// The above copyright notice and this permission notice shall be included in
// all copies or substantial portions of the Software.
// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
// AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
// LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
// OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
// THE SOFTWARE.
#pragma once
#include <cstdint>
#include <stddef.h> // For ::size_t
#include "NativeJIT/CodeGen/JumpTable.h" // Label parameter and return value.
#include "Temporary/Assert.h"
#include "Temporary/NonCopyable.h" // Base class.
namespace Allocators
{
class IAllocator;
}
namespace NativeJIT
{
class CodeBuffer : public NonCopyable
{
public:
// Allocates a buffer from the code allocator. If the code inside
// the buffer is to be executed (and not just f. ex. transferred over the
// network), the allocator must return memory that is executable (see
// ExecutionBuffer class for an example).
CodeBuffer(Allocators::IAllocator& codeAllocator, unsigned capacity);
// Frees the buffer.
virtual ~CodeBuffer();
// Allocating and resolving jump labels.
// Use AllocateLabel() at any time to allocated a label representing a jump target.
// Use PlaceLabel() to associate the current buffer position with a label.
// Once all code generation is done, invoke Finalize() to patch all of the call
// sites with jump targets. Note that all allocated labels must be placed before
// calling Finalize().
Label AllocateLabel();
virtual void PlaceLabel(Label label);
// Writes a byte to the current position in the buffer.
void Emit8(uint8_t x);
// WARNING: Non portable. Assumes little endian machine architecture.
void Emit16(uint16_t x);
// WARNING: Non portable. Assumes little endian machine architecture.
void Emit32(uint32_t x);
// WARNING: Non portable. Assumes little endian machine architecture.
void Emit64(uint64_t x);
// Copies the provided data to the current position in the buffer.
void EmitBytes(uint8_t const *data, unsigned length);
// Writes the bits of the argument to the current position in the buffer.
// WARNING: Non portable. Assumes little endian machine architecture.
template <typename T>
void EmitBytes(T x);
// Replaces the contents of the buffer starting at startPosition and
// length bytes long with specified data. The portion of the buffer that
// will be changed with this call must already have been filled in
// (i.e. CurrentPosition() <= startPosition + length). Besides the buffer
// contents, no other CodeBuffer properties get modified.
void ReplaceBytes(unsigned startPosition, uint8_t const *data, unsigned length);
// Return the size of the buffer, in bytes.
unsigned GetCapacity() const;
// Returns the address of the start of the buffer.
// WARNING: Depending on how this class is used, this may not be the
// entry point to a function that's being built inside the buffer.
// F. ex. FunctionBuffer provides the GetEntryPoint() method to retrieve
// the function pointer.
uint8_t* BufferStart() const;
// Return the offset of the current write position in the buffer.
unsigned CurrentPosition() const;
virtual void Reset();
// Advances the current write position by byteCount and returns a pointer to the write position
// before advancing.
uint8_t* Advance(int byteCount);
template <typename T>
void AdvanceToAlignment();
void Fill(unsigned start, unsigned length, uint8_t value);
// Patches each call site with the correct offset derived from its resolved label.
void PatchCallSites();
protected:
void EmitCallSite(Label label, unsigned size);
private:
Allocators::IAllocator& m_codeAllocator;
unsigned m_capacity;
uint8_t* m_bufferStart;
uint8_t* m_bufferEnd;
uint8_t* m_current;
JumpTable m_localJumpTable; // Jumps within a single CodeBuffer.
// Verifies that the specified length can be written to the buffer.
// Throws if buffer overflow would occur.
void VerifyNoBufferOverflow(unsigned length);
};
//*************************************************************************
//
// Template and inline definitions for CodeBuffer.
//
//*************************************************************************
inline void CodeBuffer::VerifyNoBufferOverflow(unsigned length)
{
LogThrowAssert(m_current + length - 1 < m_bufferEnd,
"CodeBuffer overflow, wanted %u bytes, only %u out of %u bytes available",
length,
static_cast<unsigned>(m_bufferEnd - m_current),
m_capacity);
}
template <typename T>
void CodeBuffer::EmitBytes(T x)
{
static_assert(std::is_trivial<T>::value, "Invalid variable type.");
const size_t varSize = sizeof(T);
VerifyNoBufferOverflow(varSize);
*reinterpret_cast<T*>(m_current) = x;
m_current += varSize;
}
template <typename T>
void CodeBuffer::AdvanceToAlignment()
{
while ( (CurrentPosition() % sizeof(T)) != 0)
{
Emit8(0xaa);
}
}
}
``` | /content/code_sandbox/inc/NativeJIT/CodeGen/CodeBuffer.h | objective-c | 2016-04-09T23:53:19 | 2024-06-29T07:05:56 | NativeJIT | BitFunnel/NativeJIT | 1,133 | 1,288 |
```objective-c
// Permission is hereby granted, free of charge, to any person obtaining a copy
// of this software and associated documentation files (the "Software"), to deal
// in the Software without restriction, including without limitation the rights
// to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
// copies of the Software, and to permit persons to whom the Software is
// furnished to do so, subject to the following conditions:
// The above copyright notice and this permission notice shall be included in
// all copies or substantial portions of the Software.
// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
// AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
// LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
// OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
// THE SOFTWARE.
#pragma once
#include "NativeJIT/Nodes/Node.h"
namespace NativeJIT
{
// Represents a variable on the stack of the function being compiled.
// The variable is valid as long as the function it is being compiled for
// is running. Once the function returns and its stack gets freed, the
// variable is invalid. This means that StackVariableNode cannot be used as
// return value from the function.
template <typename T>
class StackVariableNode : public Node<T&>
{
public:
StackVariableNode(ExpressionTree& tree);
//
// Overrides of Node methods
//
virtual void Print(std::ostream& out) const override;
virtual Storage<T&> CodeGenValue(ExpressionTree& tree) override;
private:
// WARNING: This class is designed to be allocated by an arena allocator,
// so its destructor will never be called. Therefore, it should hold no
// resources other than memory from the arena allocator.
~StackVariableNode();
Storage<T> m_stackStorage;
};
template <typename T>
StackVariableNode<T>::StackVariableNode(ExpressionTree& tree)
: Node<T&>(tree)
{
}
template <typename T>
void StackVariableNode<T>::Print(std::ostream& out) const
{
this->PrintCoreProperties(out, "StackVariableNode");
if (!m_stackStorage.IsNull())
{
out << ", offset " << m_stackStorage.GetOffset()
<< " off " << m_stackStorage.GetBaseRegister().GetName();
}
else
{
out << ", storage not yet assigned";
}
}
template <typename T>
ExpressionTree::Storage<T&> StackVariableNode<T>::CodeGenValue(ExpressionTree& tree)
{
// Allocate temporary storage and store it as a class variable to keep
// it alive. Make a copy which we can give up ownership on.
//
// DESIGN NOTE: The storage returned by CodeGenValue() is a pointer to the
// stack space allocated by m_stackStorage. Thus, m_stackStorage has to
// be kept alive for the address to remain valid. Currently the space
// is kept for the whole lifetime of the expression, which may be an issue
// if something uses many short-lived stack variables. Consider making it
// possible for one storage to extend the lifetime of another storage
// (for example, a concept of parent storage or similar).
m_stackStorage = tree.Temporary<T>();
auto storageCopy = m_stackStorage;
// Transfer ownership of the copy to a direct storage of variable's address.
auto addressOfStorage = Storage<T*>::AddressOfIndirect(std::move(storageCopy));
// Convert the pointer to a reference and return it.
return Storage<T&>(addressOfStorage);
}
}
``` | /content/code_sandbox/inc/NativeJIT/Nodes/StackVariableNode.h | objective-c | 2016-04-09T23:53:19 | 2024-06-29T07:05:56 | NativeJIT | BitFunnel/NativeJIT | 1,133 | 827 |
```objective-c
// Permission is hereby granted, free of charge, to any person obtaining a copy
// of this software and associated documentation files (the "Software"), to deal
// in the Software without restriction, including without limitation the rights
// to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
// copies of the Software, and to permit persons to whom the Software is
// furnished to do so, subject to the following conditions:
// The above copyright notice and this permission notice shall be included in
// all copies or substantial portions of the Software.
// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
// AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
// LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
// OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
// THE SOFTWARE.
#pragma once
#ifdef _MSC_VER
// Disable warning: 'function' : unreferenced local function has been removed
#pragma warning(disable:4505)
#endif
#include <cstdint>
#include <iosfwd> // Debugging output.
#include "NativeJIT/ExpressionTree.h" // ExpressionTree::Storage<T> return type.
#include "NativeJIT/TypePredicates.h"
#include "Temporary/Assert.h"
#include "Temporary/NonCopyable.h"
namespace NativeJIT
{
class ExpressionTree;
// Used in NodeBase as an argument.
template <typename T>
class Node;
class NodeBase : public NonCopyable
{
public:
NodeBase(ExpressionTree& tree);
unsigned GetId() const;
// Increments the number of node's parents that will evaluate the node
// through the Node<T>::CodeGen() method. The node will be evaluated
// only once, but the result will also be stored in cache with a
// matching number of references. The cache will be released once all
// parents evaluate the node.
// IMPORTANT: Currently, there's an assumption that if a node is created,
// it must be placed inside the tree. Remove this assumption and
// allow for optimizing away unused nodes. See bug#29.
void IncrementParentCount();
// Decrements the number of node's parents as set through
// IncrementParentCount(). Used only when nodes are optimized away.
void DecrementParentCount();
unsigned GetParentCount() const;
// Returns whether the node has been evaluated through the Node<T>::CodeGen
// method.
bool HasBeenEvaluated() const;
void MarkEvaluated();
// Returns whether the node is referenced. Node is considered to be
// referenced if it has parents which will call its CodeGen() method
// or through some alternate method. The IncrementParentCount() call
// which implies the CodeGen() call will implicitly mark the node as
// referenced. Parents that use the node through some other means
// need to call MarkReferenced() explicitly.
bool IsReferenced() const;
void MarkReferenced();
//
// Non-pure virtual methods.
//
virtual void CompileAsRoot(ExpressionTree& tree);
// Returns whether the node can be optimized away. Only nodes that have
// no parents and are not used through some node-specific means can
// be optimized away.
virtual bool CanBeOptimizedAway() const;
// When the node is optimized away, instructs it to undo the
// IncreaseParentCount() calls it made in its constructor. Default
// implementation throws.
virtual void ReleaseReferencesToChildren();
// For nodes that represent objects generated off of another base object
// with an added offset, populates the base and offset out parameters
// and returns true. Otherwise leaves the out parameters unchanged and
// returns false (default implementation).
// This allows to optimize a chain of references to the same object
// by collapsing them to the topmost base object and adding the offsets
// in the chain together.
// Callers that override this method also need to override
// ReleaseReferencesToChildren().
virtual bool GetBaseAndOffset(NodeBase*& base, int32_t& offset) const;
//
// Pure virtual methods.
//
virtual void CodeGenCache(ExpressionTree& tree) = 0;
virtual bool IsCached() const = 0;
// Evaluates the node and regardless of its type returns a void* Storage.
// This method is equivalent to Node<T>::CodeGen() with type erasure.
virtual Storage<void*> CodeGenAsBase(ExpressionTree& tree) = 0;
virtual void Print(std::ostream& out) const = 0;
protected:
// WARNING: This class is designed to be allocated by an arena allocator,
// so its destructor will never be called. Therefore, it should hold no
// resources other than memory from the arena allocator.
// Would like to make this private and without method body, but it's
// called implicitly by child class constructors if they throw.
// Making it non-virtual because nothing should be deleting at all,
// let alone through base pointer.
/* virtual */ ~NodeBase() {}
protected:
// Invokes CodeGen() method on both methods and assigns the result to the
// matching storage. The order of CodeGen() calls is determined by the
// estimated number of registers used: the node with higher requirements
// will be evaluated first to minimize spilling when the second node
// is evaluated.
template <typename T1, typename T2>
static void CodeGenInOrder(ExpressionTree& tree,
Node<T1>& n1, Storage<T1>& s1,
Node<T2>& n2, Storage<T2>& s2);
private:
unsigned m_id;
// See the comments for the related accessor methods above for more information.
unsigned m_parentCount;
bool m_isReferenced;
bool m_hasBeenEvaluated;
};
template <typename T>
class Node : public NodeBase
{
public:
typedef typename ExpressionTree::Storage<T>::DirectRegister RegisterType;
Node(ExpressionTree& tree);
ExpressionTree::Storage<T> CodeGen(ExpressionTree& tree);
//
// Overrides of NodeBase methods.
//
virtual void CodeGenCache(ExpressionTree& tree) override;
virtual bool IsCached() const override;
protected:
// WARNING: This class is designed to be allocated by an arena allocator,
// so its destructor will never be called. Therefore, it should hold no
// resources other than memory from the arena allocator.
// Would like to make this private and without method body, but it's
// called implicitly by child class constructors if they throw.
~Node() {}
protected:
void SetRegisterCount(unsigned count);
void PrintCoreProperties(std::ostream& out, char const *nodeName) const;
private:
unsigned m_cacheReferenceCount;
ExpressionTree::Storage<T> m_cache;
virtual Storage<T> CodeGenValue(ExpressionTree& tree) = 0;
virtual Storage<void*> CodeGenAsBase(ExpressionTree& tree) override;
void SetCache(ExpressionTree::Storage<T> s);
Storage<T> GetAndReleaseCache();
};
//*************************************************************************
//
// Template definitions for NodeBase
//
//*************************************************************************
template <typename T1, typename T2>
void NodeBase::CodeGenInOrder(ExpressionTree& tree,
Node<T1>& n1, Storage<T1>& s1,
Node<T2>& n2, Storage<T2>& s2)
{
s1 = n1.CodeGen(tree);
s2 = n2.CodeGen(tree);
}
//*************************************************************************
//
// Template definitions for Node
//
//*************************************************************************
template <typename T>
Node<T>::Node(ExpressionTree& tree)
: NodeBase(tree),
m_cacheReferenceCount(0)
{
}
template <typename T>
void Node<T>::SetCache(ExpressionTree::Storage<T> s)
{
LogThrowAssert(!IsCached(), "Cache is already set for node with ID %u", GetId());
LogThrowAssert(GetParentCount() > 0, "Cannot set cache for node %u with zero parents", GetId());
m_cacheReferenceCount = GetParentCount();
m_cache = s;
}
template <typename T>
Storage<T> Node<T>::GetAndReleaseCache()
{
LogThrowAssert(IsCached(), "Cache has not been set for node ID %u", GetId());
auto result = m_cache;
--m_cacheReferenceCount;
if (m_cacheReferenceCount == 0)
{
m_cache.Reset();
}
return result;
}
template <typename T>
bool Node<T>::IsCached() const
{
// If cache is present, reference count cannot be zero. Similarly, when
// the cache is empty, reference count must be zero.
LogThrowAssert(m_cache.IsNull() == (m_cacheReferenceCount == 0),
"Mismatch in cached storage and cache reference count: "
"have cache %u, reference count: %u",
m_cache.IsNull(),
m_cacheReferenceCount);
return !m_cache.IsNull();
}
template <typename T>
void Node<T>::PrintCoreProperties(std::ostream& out, char const* nodeName) const
{
out << nodeName
<< " [id = " << GetId()
<< ", parents = " << GetParentCount()
<< ", ";
if (IsCached())
{
out << "cached in ";
m_cache.Print(out);
}
else
{
out << "not cached";
}
out << "]";
}
template <typename T>
void Node<T>::CodeGenCache(ExpressionTree& tree)
{
LogThrowAssert(GetParentCount() > 0,
"Cannot evaluate node %u with no parents",
GetId());
LogThrowAssert(!HasBeenEvaluated(),
"Tried to CodeGenValue() node with ID %u more than once",
GetId());
MarkEvaluated();
SetCache(CodeGenValue(tree));
}
template <typename T>
typename ExpressionTree::Storage<T> Node<T>::CodeGen(ExpressionTree& tree)
{
if (!IsCached())
{
CodeGenCache(tree);
}
return GetAndReleaseCache();
}
// Calls LogThrowAbort() if a constant condition is false.
template <bool CONDITION>
void AssertAtRuntime(char const * message);
template <>
inline void AssertAtRuntime<false>(char const * message)
{
LogThrowAbort(message);
}
template <>
inline void AssertAtRuntime<true>(char const * /* message */)
{
}
template <typename T>
ExpressionTree::Storage<void*> Node<T>::CodeGenAsBase(ExpressionTree& tree)
{
// Use this rather than tag dispatch since CodeGenAsBase is a virtual method
// so the method signature at base class would have to be changed as well.
AssertAtRuntime<!RegisterStorage<T>::c_isFloat
&& RegisterStorage<T>::c_size == sizeof(void*)>(
"Invalid call to CodeGenAsBase");
return ExpressionTree::Storage<void*>(CodeGen(tree));
}
}
``` | /content/code_sandbox/inc/NativeJIT/Nodes/Node.h | objective-c | 2016-04-09T23:53:19 | 2024-06-29T07:05:56 | NativeJIT | BitFunnel/NativeJIT | 1,133 | 2,455 |
```objective-c
// Permission is hereby granted, free of charge, to any person obtaining a copy
// of this software and associated documentation files (the "Software"), to deal
// in the Software without restriction, including without limitation the rights
// to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
// copies of the Software, and to permit persons to whom the Software is
// furnished to do so, subject to the following conditions:
// The above copyright notice and this permission notice shall be included in
// all copies or substantial portions of the Software.
// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
// AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
// LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
// OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
// THE SOFTWARE.
#pragma once
#include "NativeJIT/Nodes/Node.h"
namespace NativeJIT
{
// The DependentNode declares that a prerequisite node must be evaluated
// before a dependent node can be evaluated. It is useful in scenarios with
// side effects, f. ex. if a CallNode places an output value into a
// StackVariableNode, dereferencing of the stack variable must be wrapped
// into a DependentNode.
template <typename T>
class DependentNode : public Node<T>
{
public:
DependentNode(ExpressionTree& tree,
Node<T>& dependentNode,
NodeBase& prerequisiteNode);
//
// Overrides of Node methods.
//
virtual Storage<T> CodeGenValue(ExpressionTree& tree) override;
virtual void Print(std::ostream& out) const override;
private:
// WARNING: This class is designed to be allocated by an arena allocator,
// so its destructor will never be called. Therefore, it should hold no
// resources other than memory from the arena allocator.
~DependentNode();
Node<T>& m_dependentNode;
NodeBase& m_prerequisiteNode;
};
//*************************************************************************
//
// Template definitions for the DependentNode.
//
//*************************************************************************
template <typename T>
DependentNode<T>::DependentNode(ExpressionTree& tree,
Node<T>& dependentNode,
NodeBase& prerequisiteNode)
: Node<T>(tree),
m_dependentNode(dependentNode),
m_prerequisiteNode(prerequisiteNode)
{
m_dependentNode.IncrementParentCount();
// Note: not increasing parent count on prerequisite node as DependentNode
// is not using its value but only ensuring that it has been evaluated.
}
template <typename T>
Storage<T>
DependentNode<T>::CodeGenValue(ExpressionTree& tree)
{
if (!m_prerequisiteNode.HasBeenEvaluated())
{
m_prerequisiteNode.CodeGenCache(tree);
}
return m_dependentNode.CodeGen(tree);
}
template <typename T>
void DependentNode<T>::Print(std::ostream& out) const
{
this->PrintCoreProperties(out, "DependentNode");
out << ", dependent = " << m_dependentNode.GetId();
out << ", prerequisite = " << m_prerequisiteNode.GetId();
}
}
``` | /content/code_sandbox/inc/NativeJIT/Nodes/DependentNode.h | objective-c | 2016-04-09T23:53:19 | 2024-06-29T07:05:56 | NativeJIT | BitFunnel/NativeJIT | 1,133 | 732 |
```objective-c
// Permission is hereby granted, free of charge, to any person obtaining a copy
// of this software and associated documentation files (the "Software"), to deal
// in the Software without restriction, including without limitation the rights
// to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
// copies of the Software, and to permit persons to whom the Software is
// furnished to do so, subject to the following conditions:
// The above copyright notice and this permission notice shall be included in
// all copies or substantial portions of the Software.
// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
// AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
// LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
// OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
// THE SOFTWARE.
#pragma once
#include "NativeJIT/CodeGenHelpers.h"
#include "NativeJIT/Nodes/Node.h"
namespace NativeJIT
{
template <typename T>
class ReturnNode : public Node<T>
{
public:
ReturnNode(ExpressionTree& tree, Node<T>& child);
//
// Overrides of Node methods.
//
virtual ExpressionTree::Storage<T> CodeGenValue(ExpressionTree& tree) override;
virtual void CompileAsRoot(ExpressionTree& tree) override;
virtual void Print(std::ostream& out) const override;
private:
// WARNING: This class is designed to be allocated by an arena allocator,
// so its destructor will never be called. Therefore, it should hold no
// resources other than memory from the arena allocator.
~ReturnNode();
Node<T>& m_child;
};
//*************************************************************************
//
// Template definitions for ReturnNode
//
//*************************************************************************
template <typename T>
ReturnNode<T>::ReturnNode(ExpressionTree& tree,
Node<T>& child)
: Node<T>(tree),
m_child(child)
{
// There's an implicit parent to the return node: the function it's used by.
this->IncrementParentCount();
child.IncrementParentCount();
}
template <typename T>
typename ExpressionTree::Storage<T> ReturnNode<T>::CodeGenValue(ExpressionTree& tree)
{
LogThrowAssert(this->GetParentCount() == 1,
"Unexpected parent count for the root node: %u",
this->GetParentCount());
return m_child.CodeGen(tree);
}
template <typename T>
void ReturnNode<T>::CompileAsRoot(ExpressionTree& tree)
{
ExpressionTree::Storage<T> s = this->CodeGen(tree);
auto resultRegister = tree.GetResultRegister<T>();
// Move result into the result register unless already there.
if (!(s.GetStorageClass() == StorageClass::Direct
&& s.GetDirectRegister().IsSameHardwareRegister(resultRegister)))
{
CodeGenHelpers::Emit<OpCode::Mov>(tree.GetCodeGenerator(), resultRegister, s);
}
}
template <typename T>
void ReturnNode<T>::Print(std::ostream& out) const
{
this->PrintCoreProperties(out, "ReturnNode");
}
}
``` | /content/code_sandbox/inc/NativeJIT/Nodes/ReturnNode.h | objective-c | 2016-04-09T23:53:19 | 2024-06-29T07:05:56 | NativeJIT | BitFunnel/NativeJIT | 1,133 | 716 |
```objective-c
// Permission is hereby granted, free of charge, to any person obtaining a copy
// of this software and associated documentation files (the "Software"), to deal
// in the Software without restriction, including without limitation the rights
// to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
// copies of the Software, and to permit persons to whom the Software is
// furnished to do so, subject to the following conditions:
// The above copyright notice and this permission notice shall be included in
// all copies or substantial portions of the Software.
// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
// AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
// LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
// OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
// THE SOFTWARE.
#pragma once
#include "NativeJIT/Nodes/Node.h"
namespace NativeJIT
{
// IndirectNode implements the *(base + index) operation when index is known
// at compile time.
template <typename T>
class IndirectNode : public Node<T>
{
public:
IndirectNode(ExpressionTree& tree, Node<T*>& base, int32_t index);
//
// Overrides of Node methods.
//
virtual ExpressionTree::Storage<T> CodeGenValue(ExpressionTree& tree) override;
virtual void Print(std::ostream& out) const override;
// Note: IndirectNode doesn't implement GetBaseAndOffset() method which
// allows for base object/offset collapsing optimization because it
// dereferences the target object, preventing continuation of the chain.
private:
// WARNING: This class is designed to be allocated by an arena allocator,
// so its destructor will never be called. Therefore, it should hold no
// resources other than memory from the arena allocator.
~IndirectNode();
NodeBase& m_base;
const int32_t m_index;
// Multiple accesses to the same base object can sometimes be collapsed
// as an optimization. In such cases, m_collapsedBase/Offset will point
// to such base object. Otherwise, they will match the base object/offset
// from the constructor.
// IMPORTANT: the constructor depends on collapsed base/offset being
// listed after the original base/offset.
NodeBase* m_collapsedBase;
int32_t m_collapsedOffset;
};
//*************************************************************************
//
// Template definitions for IndirectBase
//
//*************************************************************************
template <typename T>
IndirectNode<T>::IndirectNode(ExpressionTree& tree, Node<T*>& base, int32_t index)
: Node<T>(tree),
m_base(base),
m_index(index),
// Note: there is constructor order dependency for these two.
m_collapsedBase(&m_base),
m_collapsedOffset(sizeof(T) * m_index)
{
NodeBase* grandparent;
int32_t parentOffset;
// If base can be represented off of another object with an added offset,
// make the reference off of that object and adjust the offset.
if (base.GetBaseAndOffset(grandparent, parentOffset))
{
m_collapsedBase = grandparent;
m_collapsedOffset += parentOffset;
base.MarkReferenced();
}
m_collapsedBase->IncrementParentCount();
}
template <typename T>
typename ExpressionTree::Storage<T> IndirectNode<T>::CodeGenValue(ExpressionTree& tree)
{
// The base node's type ensures that the storage represent a T* rather
// than the void* returned by CodeGenAsBase(). The local offset calculated
// from the index skips the required number of T's, so it still represents
// a T*. Dereference the calculated T* to get to T.
return ExpressionTree::Storage<T>(m_collapsedBase->CodeGenAsBase(tree),
m_collapsedOffset);
}
template <typename T>
void IndirectNode<T>::Print(std::ostream& out) const
{
this->PrintCoreProperties(out, "IndirectNode");
out << ", base ID = " << m_base.GetId()
<< ", index = " << m_index;
if (m_base.GetId() != m_collapsedBase->GetId())
{
out
<< ", collapsed base ID = " << m_collapsedBase->GetId()
<< ", collapsed offset = " << m_collapsedOffset;
}
}
}
``` | /content/code_sandbox/inc/NativeJIT/Nodes/IndirectNode.h | objective-c | 2016-04-09T23:53:19 | 2024-06-29T07:05:56 | NativeJIT | BitFunnel/NativeJIT | 1,133 | 1,003 |
```objective-c
// Permission is hereby granted, free of charge, to any person obtaining a copy
// of this software and associated documentation files (the "Software"), to deal
// in the Software without restriction, including without limitation the rights
// to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
// copies of the Software, and to permit persons to whom the Software is
// furnished to do so, subject to the following conditions:
// The above copyright notice and this permission notice shall be included in
// all copies or substantial portions of the Software.
// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
// AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
// LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
// OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
// THE SOFTWARE.
#pragma once
#include "NativeJIT/ExpressionTree.h"
#include "NativeJIT/Nodes/Node.h"
#include "Temporary/Assert.h"
namespace NativeJIT
{
class ParameterSlotAllocator;
template <typename T>
class ParameterNode : public Node<T>
{
public:
ParameterNode(ExpressionTree& tree, ParameterSlotAllocator& slotAllocator);
unsigned GetPosition() const;
//
// Overrides of NodeBase methods.
//
virtual void ReleaseReferencesToChildren() override;
//
// Overrides of Node methods.
//
virtual ExpressionTree::Storage<T> CodeGenValue(ExpressionTree& tree) override;
virtual void Print(std::ostream& out) const override;
private:
// WARNING: This class is designed to be allocated by an arena allocator,
// so its destructor will never be called. Therefore, it should hold no
// resources other than memory from the arena allocator.
~ParameterNode();
unsigned m_position;
unsigned m_logicalRegister;
};
// ParameterSlotAllocator allocates parameter index numbers which are used to
// map parameters to registers. In the Windows ABI, a parameter's index
// numbers is equal to its position in the parameter list, regardless of
// parameter type. For example, in the function,
// void f(int a, float b, int c, float d)
// the parameter indexes would be
// a:0, b:1, c:2, d:3
// In the System V ABI, parameters indexes are allocated from two sequences,
// one for integer types and one for floating point types. Given the
// function definition above, on System V, the parameter indexes would be
// a:0, b:0, c:1, d:1
class ParameterSlotAllocator
{
public:
ParameterSlotAllocator()
: m_ints(0),
m_floats(0),
m_position(0),
m_register(0)
{
}
unsigned GetPosition() const
{
return m_position;
}
unsigned GetLogicalRegister() const
{
return m_register;
}
template <class T, typename std::enable_if<std::is_floating_point<T>::value>::type * = nullptr>
void Allocate()
{
m_position = m_ints + m_floats;
#ifdef NATIVEJIT_PLATFORM_WINDOWS
m_register = m_position;
#else
m_register = m_floats;
#endif
m_floats++;
}
template <class T, typename std::enable_if<!std::is_floating_point<T>::value>::type * = nullptr>
void Allocate()
{
m_position = m_ints + m_floats;
#ifdef NATIVEJIT_PLATFORM_WINDOWS
m_register = m_position;
#else
m_register = m_ints;
#endif
m_ints++;
}
private:
unsigned m_ints;
unsigned m_floats;
unsigned m_position;
unsigned m_register;
};
//*************************************************************************
//
// Template definitions for ParameterNode
//
//*************************************************************************
template <unsigned SIZE>
void GetParameterRegister(unsigned id, Register<SIZE, false>& r)
{
// For now we only support the four parameters that are passed in registers.
// No support for memory parameters.
LogThrowAssert(id < 4, "Exceeded maximum number of register parameters.");
// Integer parameters are passed in RCX, RDX, R8, and R9.
// Use constants to encode registers. See #31.
#ifdef NATIVEJIT_PLATFORM_WINDOWS
const uint8_t idMap[] = {1, 2, 8, 9};
#else
const uint8_t idMap[] = {7, 6, 2, 1, 8, 9};
#endif
r = Register<SIZE, false>(idMap[id]);
}
template <unsigned SIZE>
void GetParameterRegister(unsigned id, Register<SIZE, true>& r)
{
// For now we only support the four parameters that are passed in registers.
// No support for memory parameters.
LogThrowAssert(id < 4, "Exceeded maximum number of register parameters.");
// Floating point parameters are passed in XMM0-XMM3.
r = Register<SIZE, true>(id);
}
template <typename T>
ParameterNode<T>::ParameterNode(ExpressionTree& tree, ParameterSlotAllocator& slotAllocator)
: Node<T>(tree)
{
slotAllocator.Allocate<T>();
m_position = slotAllocator.GetPosition();
m_logicalRegister = slotAllocator.GetLogicalRegister();
// Parameter nodes are always considered to be referenced (as a part of
// the function being compiled) even when they are not referenced
// explicitly.
this->MarkReferenced();
tree.AddParameter(*this, m_position);
}
template <typename T>
unsigned ParameterNode<T>::GetPosition() const
{
return m_position;
}
template <typename T>
void ParameterNode<T>::ReleaseReferencesToChildren()
{
// No children to release.
}
template <typename T>
typename ExpressionTree::Storage<T> ParameterNode<T>::CodeGenValue(ExpressionTree& tree)
{
typename Storage<T>::DirectRegister reg;
GetParameterRegister(m_logicalRegister, reg);
return tree.Direct<T>(reg);
}
template <typename T>
void ParameterNode<T>::Print(std::ostream& out) const
{
this->PrintCoreProperties(out, "ParameterNode");
out << ", position = " << m_position;
}
}
``` | /content/code_sandbox/inc/NativeJIT/Nodes/ParameterNode.h | objective-c | 2016-04-09T23:53:19 | 2024-06-29T07:05:56 | NativeJIT | BitFunnel/NativeJIT | 1,133 | 1,426 |
```objective-c
// Permission is hereby granted, free of charge, to any person obtaining a copy
// of this software and associated documentation files (the "Software"), to deal
// in the Software without restriction, including without limitation the rights
// to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
// copies of the Software, and to permit persons to whom the Software is
// furnished to do so, subject to the following conditions:
// The above copyright notice and this permission notice shall be included in
// all copies or substantial portions of the Software.
// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
// AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
// LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
// OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
// THE SOFTWARE.
#pragma once
#include <type_traits>
#include "NativeJIT/CodeGen/ValuePredicates.h"
#include "NativeJIT/Nodes/ImmediateNodeDecls.h"
namespace NativeJIT
{
//*************************************************************************
//
// Template specializations for ImmediateNode for InlineImmediate types.
//
//*************************************************************************
template <typename T>
ImmediateNode<T, ImmediateCategory::InlineImmediate>::ImmediateNode(ExpressionTree& tree, T value)
: Node<T>(tree),
m_value(value)
{
}
template <typename T>
void ImmediateNode<T, ImmediateCategory::InlineImmediate>::Print(std::ostream& out) const
{
this->PrintCoreProperties(out, "ImmediateNode");
out << ", value = " << m_value;
}
template <typename T>
Storage<T>
ImmediateNode<T, ImmediateCategory::InlineImmediate>::CodeGenValue(ExpressionTree& tree)
{
return tree.Immediate(m_value);
}
//*************************************************************************
//
// Template specializations for ImmediateNode for RIPRelativeImmediate types.
//
//*************************************************************************
template <typename T>
ImmediateNode<T, ImmediateCategory::RIPRelativeImmediate>::ImmediateNode(ExpressionTree& tree, T value)
: Node<T>(tree),
m_value(value)
{
tree.AddRIPRelative(*this);
// m_offset will be initialized with the correct value during pass0
// of compilation in the call to EmitStaticData().
m_offset = 0;
}
template <typename T>
void ImmediateNode<T, ImmediateCategory::RIPRelativeImmediate>::Print(std::ostream& out) const
{
this->PrintCoreProperties(out, "ImmediateNode (RIP-indirect)");
out << ", value = " << m_value;
}
template <typename T>
Storage<T>
ImmediateNode<T, ImmediateCategory::RIPRelativeImmediate>::CodeGenValue(ExpressionTree& tree)
{
return tree.RIPRelative<T>(m_offset);
}
template <typename T>
void ImmediateNode<T, ImmediateCategory::RIPRelativeImmediate>::EmitStaticData(ExpressionTree& tree)
{
auto & code = tree.GetCodeGenerator();
code.AdvanceToAlignment<T>();
m_offset = code.CurrentPosition();
// Emit the value using a canonical type since the EmitValueBytes
// method intentionally has a limited number of input types. Basic
// types will be unchanged, but f. ex. function pointers will be
// emitted as uint64_t.
code.EmitBytes(ForcedCast<typename CanonicalRegisterStorageType<T>::Type>(m_value));
}
}
``` | /content/code_sandbox/inc/NativeJIT/Nodes/ImmediateNode.h | objective-c | 2016-04-09T23:53:19 | 2024-06-29T07:05:56 | NativeJIT | BitFunnel/NativeJIT | 1,133 | 777 |
```objective-c
// Permission is hereby granted, free of charge, to any person obtaining a copy
// of this software and associated documentation files (the "Software"), to deal
// in the Software without restriction, including without limitation the rights
// to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
// copies of the Software, and to permit persons to whom the Software is
// furnished to do so, subject to the following conditions:
// The above copyright notice and this permission notice shall be included in
// all copies or substantial portions of the Software.
// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
// AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
// LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
// OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
// THE SOFTWARE.
#pragma once
#include "NativeJIT/CodeGen/X64CodeGenerator.h" // OpCode type.
#include "NativeJIT/CodeGenHelpers.h"
#include "NativeJIT/Nodes/Node.h"
namespace NativeJIT
{
template <OpCode OP, typename L, typename R>
class BinaryNode : public Node<L>
{
public:
BinaryNode(ExpressionTree& tree, Node<L>& left, Node<R>& right);
virtual ExpressionTree::Storage<L> CodeGenValue(ExpressionTree& tree) override;
virtual void Print(std::ostream& out) const override;
private:
// WARNING: This class is designed to be allocated by an arena allocator,
// so its destructor will never be called. Therefore, it should hold no
// resources other than memory from the arena allocator.
~BinaryNode();
Node<L>& m_left;
Node<R>& m_right;
};
//*************************************************************************
//
// Template definitions for BinaryNode
//
//*************************************************************************
template <OpCode OP, typename L, typename R>
BinaryNode<OP, L, R>::BinaryNode(ExpressionTree& tree,
Node<L>& left,
Node<R>& right)
: Node<L>(tree),
m_left(left),
m_right(right)
{
left.IncrementParentCount();
right.IncrementParentCount();
}
template <OpCode OP, typename L, typename R>
typename ExpressionTree::Storage<L> BinaryNode<OP, L, R>::CodeGenValue(ExpressionTree& tree)
{
Storage<L> sLeft;
Storage<R> sRight;
this->CodeGenInOrder(tree,
m_left, sLeft,
m_right, sRight);
// DESIGN NOTE: sLeft can == sRight when their types don't match. This can happen,
// although we (mhop & danluu) couldn't think of any useful cases where that
// currently happens.
if (sLeft == sRight)
{
sRight.Reset();
CodeGenHelpers::Emit<OP>(tree.GetCodeGenerator(),
sLeft.ConvertToDirect(true), sLeft);
}
else
{
CodeGenHelpers::Emit<OP>(tree.GetCodeGenerator(),
sLeft.ConvertToDirect(true), sRight);
}
return sLeft;
}
template <OpCode OP, typename L, typename R>
void BinaryNode<OP, L, R>::Print(std::ostream& out) const
{
const std::string name = std::string("Operation (")
+ X64CodeGenerator::OpCodeName(OP)
+ ") ";
this->PrintCoreProperties(out, name.c_str());
out << ", left = " << m_left.GetId();
out << ", right = " << m_right.GetId();
}
}
``` | /content/code_sandbox/inc/NativeJIT/Nodes/BinaryNode.h | objective-c | 2016-04-09T23:53:19 | 2024-06-29T07:05:56 | NativeJIT | BitFunnel/NativeJIT | 1,133 | 822 |
```objective-c
// Permission is hereby granted, free of charge, to any person obtaining a copy
// of this software and associated documentation files (the "Software"), to deal
// in the Software without restriction, including without limitation the rights
// to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
// copies of the Software, and to permit persons to whom the Software is
// furnished to do so, subject to the following conditions:
// The above copyright notice and this permission notice shall be included in
// all copies or substantial portions of the Software.
// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
// AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
// LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
// OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
// THE SOFTWARE.
#pragma once
#include "NativeJIT/CodeGen/X64CodeGenerator.h" // OpCode type.
#include "NativeJIT/Nodes/Node.h"
namespace NativeJIT
{
// Implements a node for the SHLD instruction.
template <typename T>
class ShldNode : public Node<T>
{
public:
ShldNode(ExpressionTree& tree, Node<T>& shiftee, Node<T>& filler, uint8_t bitCount);
virtual Storage<T> CodeGenValue(ExpressionTree& tree) override;
virtual void Print(std::ostream& out) const override;
private:
// WARNING: This class is designed to be allocated by an arena allocator,
// so its destructor will never be called. Therefore, it should hold no
// resources other than memory from the arena allocator.
~ShldNode();
Node<T>& m_shiftee;
Node<T>& m_filler;
const uint8_t m_bitCount;
};
//*************************************************************************
//
// Template definitions for BinaryNode
//
//*************************************************************************
template <typename T>
ShldNode<T>::ShldNode(ExpressionTree& tree,
Node<T>& shiftee,
Node<T>& filler,
uint8_t bitCount)
: Node<T>(tree),
m_shiftee(shiftee),
m_filler(filler),
m_bitCount(bitCount)
{
m_shiftee.IncrementParentCount();
m_filler.IncrementParentCount();
}
template <typename T>
Storage<T> ShldNode<T>::CodeGenValue(ExpressionTree& tree)
{
auto & code = tree.GetCodeGenerator();
Storage<T> shiftee;
Storage<T> filler;
this->CodeGenInOrder(tree,
m_shiftee, shiftee,
m_filler, filler);
// Convert both arguments to direct registers. The filler value will
// not be touched.
{
auto shifteeReg = shiftee.ConvertToDirect(true);
ReferenceCounter shifteePin = shiftee.GetPin();
auto fillerReg = filler.ConvertToDirect(false);
code.EmitImmediate<OpCode::Shld>(shifteeReg, fillerReg, m_bitCount);
}
return shiftee;
}
template <typename T>
void ShldNode<T>::Print(std::ostream& out) const
{
this->PrintCoreProperties(out, "Shld");
out << ", shiftee = " << m_shiftee.GetId()
<< ", filler = " << m_filler.GetId()
<< ", bitCount = " << m_bitCount;
}
}
``` | /content/code_sandbox/inc/NativeJIT/Nodes/ShldNode.h | objective-c | 2016-04-09T23:53:19 | 2024-06-29T07:05:56 | NativeJIT | BitFunnel/NativeJIT | 1,133 | 788 |
```objective-c
// Permission is hereby granted, free of charge, to any person obtaining a copy
// of this software and associated documentation files (the "Software"), to deal
// in the Software without restriction, including without limitation the rights
// to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
// copies of the Software, and to permit persons to whom the Software is
// furnished to do so, subject to the following conditions:
// The above copyright notice and this permission notice shall be included in
// all copies or substantial portions of the Software.
// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
// AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
// LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
// OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
// THE SOFTWARE.
#pragma once
#include <algorithm> // For std::max
#include <type_traits>
#include "NativeJIT/ExpressionNodeFactory.h"
#include "NativeJIT/Nodes/Node.h"
namespace NativeJIT
{
class ExpressionNodeFactory;
// The CastNode implements a cast node from FROM to TO, most closely
// resembling the C++ static_cast/reinterpret_cast. Requires that FROM
// is convertible to TO using static_cast or that the sizes of FROM and TO
// are the same so that reinterpret_cast can semi-safely be used.
// If register size and type of FROM/TO are the same, the cast is a no-op.
// Otherwise, the appropriate instructions are emitted to perform the
// conversion.
namespace Casting
{
// All the possible types of casts. Note that integer applies to register
// type, i.e. everything that is not a floating point.
enum class Cast { NoOp, IntToInt, FloatToFloat, IntToFloat, FloatToInt };
// A class used to specialize code generation for casts that can be
// implemented directly using the X64 conversion instructions.
template <Cast TYPE>
struct OneStepCastGenerator
{
template <typename TO, typename FROM>
static Storage<TO>
Generate(ExpressionTree& tree, Storage<FROM>& source);
};
// A class used to build a composite node needed to perform a cast
// for casts that cannot be implemented directly using the X64 conversion
// instructions.
template <Cast TYPE>
struct CompositeCastNodeBuilder
{
template <typename TO, typename FROM>
static Node<TO>& Build(ExpressionNodeFactory& tree, Node<FROM>& from);
};
// Properties for a cast.
template <typename TO, typename FROM>
class Traits
{
public:
// Either neither side is a reference, or if one of them is, the
// other one must be a pointer.
static_assert((!std::is_reference<FROM>::value
&& !std::is_reference<TO>::value)
// Const cast is also acceptable.
|| (std::is_same<typename std::remove_const<FROM>::type,
typename std::remove_const<TO>::type>::value)
|| (std::is_pointer<FROM>::value
|| std::is_pointer<TO>::value),
"If one side is a reference, the other one must be a pointer");
// Source and target register types and properties.
typedef typename Storage<FROM>::DirectRegister FromRegister;
typedef typename Storage<TO>::DirectRegister ToRegister;
private:
static const bool c_isSameRegisterType = std::is_same<FromRegister, ToRegister>::value;
static const bool c_isSameFloatValue = FromRegister::c_isFloat == ToRegister::c_isFloat;
// Cast is a no-op if it's from and to the same register size and
// type (see further for signed/unsigned consideration). Additionally,
// integer cast from larger to smaller size is a no-op and is achieved
// by observing the larger size as the smaller size.
//
// For integer casts, if the signedness of both sides is same, the
// expected outcome is clearly achieved by observing just the smaller
// portion of the register. The same applies for larger signed FROM
// and smaller unsigned TO since that's how the C++ standard defines
// such cast when two's complement system is used. Finally, for larger
// unsigned FROM and smaller signed TO, the behavior is implementation
// defined and here it's chosen to be bit-preserving, the same as in
// VC.
//
// WARNING: assumption that the int cast from larger to smaller size
// is a no-op is non-portable for indirect storage since it assumes
// little endian architecture. If portability is required, the
// assumption could be removed by converting the indirect storage to
// direct.
static const bool c_isNoOp
= c_isSameRegisterType
|| (c_isSameFloatValue
&& !FromRegister::c_isFloat
&& FromRegister::c_size > ToRegister::c_size);
public:
// Determine which type of cast should be performed.
static const Cast c_castType
= c_isNoOp
? Cast::NoOp
: (c_isSameFloatValue
? (FromRegister::c_isFloat ? Cast::FloatToFloat : Cast::IntToInt)
: (FromRegister::c_isFloat ? Cast::FloatToInt : Cast::IntToFloat));
private:
// Check whether an int to float cast can be done using a single x64
// conversion instruction.
static const bool c_isOneStepIntToFloatCast
= c_castType == Cast::IntToFloat
&& (std::is_same<typename std::remove_cv<FROM>::type, int32_t>::value
|| std::is_same<typename std::remove_cv<FROM>::type, int64_t>::value);
// Check whether a float to int cast can be done using a single x64
// conversion instruction.
static const bool c_isOneStepFloatToIntCast
= c_castType == Cast::FloatToInt
&& (std::is_same<typename std::remove_cv<TO>::type, int32_t>::value
|| std::is_same<typename std::remove_cv<TO>::type, int64_t>::value);
public:
static const bool c_isOneStepCast
= c_castType == Cast::NoOp
|| c_castType == Cast::IntToInt
|| c_castType == Cast::FloatToFloat
|| c_isOneStepIntToFloatCast
|| c_isOneStepFloatToIntCast;
};
// A class used to specialize code generation for casts that need to
// convert between two immediate storages. The class is needed instead
// of a simple if/else branch because e.g. if TO type belongs to a
// RIPRelativeImmediate category, the if/else branch that contained
// a tree.Immediate() call would fail to compile.
// Two levels of structs are used to allow different template specializations.
template <ImmediateCategory FROMCATEGORY>
struct FromImmediate
{
template <Cast CASTTYPE, ImmediateCategory TOCATEGORY>
struct CastGenerator
{
template <typename TO, typename FROM>
static Storage<TO>
Generate(ExpressionTree& tree, Storage<FROM>& source);
};
};
}
// The CastNode is partially specialized depending on whether or not a one-step
// cast can be used.
template <typename TO,
typename FROM,
bool ISONESTEP = Casting::Traits<TO, FROM>::c_isOneStepCast>
class CastNode;
// One-step cast version of the CastNode.
template <typename TO, typename FROM>
class CastNode<TO, FROM, true> : public Node<TO>
{
public:
CastNode(ExpressionTree& tree, Node<FROM>& from);
//
// Overrides of Node methods.
//
virtual Storage<TO> CodeGenValue(ExpressionTree& tree) override;
virtual void Print(std::ostream& out) const override;
private:
// WARNING: This class is designed to be allocated by an arena allocator,
// so its destructor will never be called. Therefore, it should hold no
// resources other than memory from the arena allocator.
~CastNode();
typedef Casting::Traits<TO, FROM> Traits;
Node<FROM>& m_from;
};
// Composite cast version of the CastNode.
template <typename TO, typename FROM>
class CastNode<TO, FROM, false> : public Node<TO>
{
public:
CastNode(ExpressionNodeFactory& tree, Node<FROM>& from);
//
// Overrides of Node methods.
//
virtual Storage<TO> CodeGenValue(ExpressionTree& tree) override;
virtual void Print(std::ostream& out) const override;
private:
// WARNING: This class is designed to be allocated by an arena allocator,
// so its destructor will never be called. Therefore, it should hold no
// resources other than memory from the arena allocator.
~CastNode();
typedef Casting::Traits<TO, FROM> Traits;
// The composite node used to perform the cast.
Node<TO>& m_conversionNode;
};
//*************************************************************************
//
// Template definitions for the one-step CastNode.
//
//*************************************************************************
template <typename TO, typename FROM>
CastNode<TO, FROM, true>::CastNode(ExpressionTree& tree, Node<FROM>& from)
: Node<TO>(tree),
m_from(from)
{
m_from.IncrementParentCount();
}
template <typename TO, typename FROM>
Storage<TO>
CastNode<TO, FROM, true>::CodeGenValue(ExpressionTree& tree)
{
auto source = m_from.CodeGen(tree);
return Casting
::template OneStepCastGenerator<Traits::c_castType>
::template Generate<TO, FROM>(tree, source);
}
template <typename TO, typename FROM>
void CastNode<TO, FROM, true>::Print(std::ostream& out) const
{
this->PrintCoreProperties(out, "CastNode (one-step)");
out << ", from = " << m_from.GetId();
}
//*************************************************************************
//
// Template definitions for composite CastNode.
//
//*************************************************************************
template <typename TO, typename FROM>
CastNode<TO, FROM, false>::CastNode(ExpressionNodeFactory& tree, Node<FROM>& from)
: Node<TO>(tree),
m_conversionNode(Casting
::CompositeCastNodeBuilder<Casting::Traits<TO, FROM>::c_castType>
::template Build<TO, FROM>(tree, from))
{
m_conversionNode.IncrementParentCount();
}
template <typename TO, typename FROM>
Storage<TO>
CastNode<TO, FROM, false>::CodeGenValue(ExpressionTree& tree)
{
return m_conversionNode.CodeGen(tree);
}
template <typename TO, typename FROM>
void CastNode<TO, FROM, false>::Print(std::ostream& out) const
{
this->PrintCoreProperties(out, "CastNode (composite)");
out << ", conversionNode = " << m_conversionNode.GetId();
}
namespace Casting
{
//
// Template definitions for OneStepCastGenerator.
//
// No-op cast.
template <>
template <typename TO, typename FROM>
Storage<TO>
OneStepCastGenerator<Cast::NoOp>::Generate(ExpressionTree& /* tree */, Storage<FROM>& source)
{
return Storage<TO>(source);
}
// Cast between two float registers.
template <>
template <typename TO, typename FROM>
Storage<TO>
OneStepCastGenerator<Cast::FloatToFloat>::Generate(ExpressionTree& tree, Storage<FROM>& source)
{
static_assert(Traits<TO, FROM>::c_isOneStepCast, "Invalid one-step cast.");
auto target = tree.Direct<TO>();
CodeGenHelpers::Emit<OpCode::CvtFP2FP>(tree.GetCodeGenerator(),
target.GetDirectRegister(),
source);
return target;
}
// Cast between two integer registers.
template <>
template <typename TO, typename FROM>
Storage<TO>
OneStepCastGenerator<Cast::IntToInt>::Generate(ExpressionTree& tree, Storage<FROM>& source)
{
typedef Traits<TO, FROM> Traits;
static_assert(Traits::c_isOneStepCast, "Invalid one-step cast.");
static_assert(Traits::FromRegister::c_size < Traits::ToRegister::c_size,
"Invalid one-step cast.");
typedef Storage<TO> ToStorage;
// The cast needs to extend the source storage to a larger target.
// Depending on the signedness of the source type, use sign extension
// or zero extension.
const OpCode opCode = std::is_signed<FROM>::value
? OpCode::MovSX
: OpCode::MovZX;
auto & code = tree.GetCodeGenerator();
ToStorage result;
switch (source.GetStorageClass())
{
case StorageClass::Immediate:
result = Casting
::FromImmediate<ImmediateCategoryOf<FROM>::value>
::template CastGenerator<Cast::IntToInt, ImmediateCategoryOf<TO>::value>
::template Generate<TO, FROM>(tree, source);
break;
case StorageClass::Indirect:
{
using namespace CodeGenHelpers;
// Cannot reuse source, allocate a new register and move with
// extension into it.
result = tree.Direct<TO>();
// Target the full register to prevent a partial register stall.
typename ToStorage::FullRegister targetRegister(result.GetDirectRegister());
Emitter<RegTypes::Different, ImmediateType::NotAllowed>
::Emit<opCode>(tree.GetCodeGenerator(),
targetRegister,
source);
break;
}
case StorageClass::Direct:
{
// May be able to reuse the register if it's fully owned by the storage.
source.ConvertToDirect(true);
result = ToStorage(source);
// Always target the full register to prevent a partial register stall.
auto sourceRegister = source.GetDirectRegister();
typename ToStorage::FullRegister fullSourceRegister(sourceRegister);
code.Emit<opCode>(fullSourceRegister, sourceRegister);
break;
}
default:
LogThrowAbort("Invalid storage class.");
break;
}
return result;
}
// Cast from integer to float register.
template <>
template <typename TO, typename FROM>
Storage<TO>
OneStepCastGenerator<Cast::IntToFloat>::Generate(ExpressionTree& tree, Storage<FROM>& source)
{
static_assert(Traits<TO, FROM>::c_isOneStepCast, "Invalid one-step cast.");
Storage<TO> result;
if (source.GetStorageClass() == StorageClass::Immediate)
{
result = Casting
::FromImmediate<ImmediateCategoryOf<FROM>::value>
::template CastGenerator<Cast::IntToFloat, ImmediateCategoryOf<TO>::value>
::template Generate<TO, FROM>(tree, source);
}
else
{
result = tree.Direct<TO>();
// DESIGN NOTE: Implement xorps/xorpd and add a "xor target, target" call to
// clear the target FP register before changing its lower 32/64 bits.
// Doing that might prevent a partial register stall.
using namespace CodeGenHelpers;
Emitter<RegTypes::Different, ImmediateType::NotAllowed>
::Emit<OpCode::CvtSI2FP>(tree.GetCodeGenerator(),
result.GetDirectRegister(),
source);
}
return result;
}
// Cast from float to integer register.
template <>
template <typename TO, typename FROM>
Storage<TO>
OneStepCastGenerator<Cast::FloatToInt>::Generate(ExpressionTree& tree, Storage<FROM>& source)
{
static_assert(Traits<TO, FROM>::c_isOneStepCast, "Invalid one-step cast.");
auto target = tree.Direct<TO>();
CodeGenHelpers::Emit<OpCode::CvtFP2SI>(tree.GetCodeGenerator(),
target.GetDirectRegister(),
source);
return target;
}
// A helper method to build two cast nodes which would convert from FROM
// to TO by using one-step casts through an INTERMEDIATE.
template <typename TO, typename INTERMEDIATE, typename FROM>
Node<TO>& TwoStepCast(ExpressionNodeFactory& tree, Node<FROM>& from)
{
static_assert(Traits<FROM, INTERMEDIATE>::c_isOneStepCast, "Must be a one-step cast.");
static_assert(Traits<INTERMEDIATE, TO>::c_isOneStepCast, "Must be a one-step cast.");
return tree.Cast<TO, INTERMEDIATE>(tree.Cast<INTERMEDIATE, FROM>(from));
}
//
// Template definitions for FromImmediate::CastGenerator.
//
// Target can be represented as a inline immediate so an immediate Storage
// can be used.
template <>
template <>
template <typename TO, typename FROM>
Storage<TO>
FromImmediate<ImmediateCategory::InlineImmediate>
::CastGenerator<Cast::IntToInt, ImmediateCategory::InlineImmediate>
::Generate(ExpressionTree& tree, Storage<FROM>& source)
{
return tree.Immediate(ForcedCast<TO, FROM>(source.GetImmediate()));
}
// Target requires a RIP relative immediate, so a direct register has
// to be used instead of an immediate Storage.
template <>
template <>
template <typename TO, typename FROM>
Storage<TO>
FromImmediate<ImmediateCategory::InlineImmediate>
::CastGenerator<Cast::IntToInt, ImmediateCategory::RIPRelativeImmediate>
::Generate(ExpressionTree& tree, Storage<FROM>& source)
{
Storage<TO> result = tree.Direct<TO>();
// After the compiler performs the cast, move the value to a direct register.
auto targetImmediate = ForcedCast<TO, FROM>(source.GetImmediate());
tree.GetCodeGenerator().EmitImmediate<OpCode::Mov>(result.GetDirectRegister(),
targetImmediate);
return result;
}
// The integer to floating point conversion instruction doesn't have the
// flavor which converts from an immediate directly. Use the compiler
// to get the target floating point value and place it directly into
// the target register through a temporary.
template <>
template <>
template <typename TO, typename FROM>
Storage<TO>
FromImmediate<ImmediateCategory::InlineImmediate>
::CastGenerator<Cast::IntToFloat, ImmediateCategory::RIPRelativeImmediate>
::Generate(ExpressionTree& tree, Storage<FROM>& source)
{
Storage<TO> result = tree.Direct<TO>();
// NOTE: MovThroughTemporary allocates a temporary *integer*
// register to perform the move. There is no danger that the
// register allocated for the "target" Storage above will be
// spilled since it is a *floating point* register.
CodeGenHelpers::MovThroughTemporary(tree,
result.GetDirectRegister(),
static_cast<TO>(source.GetImmediate()));
return result;
}
// Fallback case which should never be reachable.
template <ImmediateCategory FROMCATEGORY>
template <Cast CASTTYPE, ImmediateCategory TOCATEGORY>
template <typename TO, typename FROM>
Storage<TO>
FromImmediate<FROMCATEGORY>
::CastGenerator<CASTTYPE, TOCATEGORY>
::Generate(ExpressionTree& /* tree */, Storage<FROM>& /* source */)
{
static_assert(Traits<TO, FROM>::c_isOneStepCast, "Invalid one-step cast.");
// The compile time checks should prevent writing code that will
// reach this point. Since GetStorageClass() is a runtime method, it's
// necessary to provide a body for the remaining cases even though
// they should not be reachable.
LogThrowAbort("Unexpected immediate type");
return Storage<TO>();
}
//
// Template definitions for CompositeCastNodeBuilder.
//
#ifdef _MSC_VER
// Supress warning about constant expression involving template parameters.
#pragma warning(push)
#pragma warning(disable:4127)
#endif
// Composite node for casting from integer to float.
template <>
template <typename TO, typename FROM>
Node<TO>&
CompositeCastNodeBuilder<Cast::IntToFloat>::Build(ExpressionNodeFactory& tree, Node<FROM>& from)
{
Node<TO>* result;
if (sizeof(FROM) <= 2)
{
// Two one-step casts: [unsigned] int8_t/16 -> int32_t -> float.
// Note that both uint8_t/16 can fully fit into a signed
// int32_t.
result = &TwoStepCast<TO, int32_t, FROM>(tree, from);
}
else if (sizeof(FROM) == 4)
{
// This path can only be reached for uint32_t (cast from
// a int32_t is a one-step cast). Cast using two one-step
// casts: uint32_t -> int64_t -> float.
result = &TwoStepCast<TO, int64_t, FROM>(tree, from);
}
else
{
// This path can only be reached for uint64_t (cast from
// a int64_t is a one-step cast). Cast it to float as if it
// was a int64_t. If the number observed as int64_t
// was negative, such a conversion would have produced a number
// that's 2^64 smaller than expected. Add 2^64 back case to adjust
// in that case. This is how VC++ does the conversion as well.
// This test could be done with the group 3 "test" instruction
// in case it was available.
auto & isNegative = tree.Compare<JccType::JS>(from, tree.Immediate<FROM>(0));
auto & floatNode = TwoStepCast<TO, int64_t, FROM>(tree, from);
auto & twoToThePowerOf64 = tree.Immediate<TO>(1.8446744073709551616e19f);
result = &tree.Conditional(isNegative,
tree.Add(floatNode, twoToThePowerOf64),
floatNode);
}
return *result;
}
// Cast from float to integer register.
template <>
template <typename TO, typename FROM>
Node<TO>&
CompositeCastNodeBuilder<Cast::FloatToInt>::Build(ExpressionNodeFactory& tree, Node<FROM>& from)
{
Node<TO>* result;
// Note: In C++, conversion from a floating point value that is
// outside of the range of the target integer is undefined behavior
// (the result can be anything and it doesn't even have to be
// consistent). Any occurence of undefined behavior makes any further
// operations also undefined. Thus, the caller is expected to make
// sure that the input floating point values are inside the target
// integer range. Because of this, the implementation doesn't take
// any special steps if negative float is converted to unsigned
// integer or if the float is too large.
if (sizeof(TO) <= 2)
{
// Two one-step casts: float -> int32_t -> [unsigned] int8_t/16.
result = &TwoStepCast<TO, int32_t, FROM>(tree, from);
}
else if (sizeof(TO) == 4)
{
// Two one-step casts: float -> int64_t -> uint32_t.
result = &TwoStepCast<TO, int64_t, FROM>(tree, from);
}
else
{
// When converting uint64_t to float, there are two
// branches: if the float is smaller than 2^63 and it will fit
// into a int64_t, use essentially a one-step cast.
// Otherwise, subtract 2^63 from the floating point, convert
// to int64_t and add (integer) 2^63 to the result.
uint64_t twoToThePowerOf63 = 1ull << 63;
auto & twoToThePowerOf63Float
= tree.Immediate(static_cast<FROM>(twoToThePowerOf63));
// Check whether source is smaller than 2^63.
auto & isSourceWithoutOverflow
= tree.Compare<JccType::JB>(from, twoToThePowerOf63Float);
// The node with a reduced float and the int which gets increased
// by the same value after the conversion.
auto & reducedFloat = tree.Sub(from, twoToThePowerOf63Float);
auto & adjustedConvertedInt
= tree.Add(TwoStepCast<TO, int64_t, FROM>(tree, reducedFloat),
tree.Immediate(static_cast<TO>(twoToThePowerOf63)));
result = &tree.Conditional(isSourceWithoutOverflow,
TwoStepCast<TO, int64_t, FROM>(tree, from),
adjustedConvertedInt);
}
return *result;
}
#ifdef _MSC_VER
#pragma warning(pop)
#endif
}
}
``` | /content/code_sandbox/inc/NativeJIT/Nodes/CastNode.h | objective-c | 2016-04-09T23:53:19 | 2024-06-29T07:05:56 | NativeJIT | BitFunnel/NativeJIT | 1,133 | 5,517 |
```objective-c
// Permission is hereby granted, free of charge, to any person obtaining a copy
// of this software and associated documentation files (the "Software"), to deal
// in the Software without restriction, including without limitation the rights
// to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
// copies of the Software, and to permit persons to whom the Software is
// furnished to do so, subject to the following conditions:
// The above copyright notice and this permission notice shall be included in
// all copies or substantial portions of the Software.
// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
// AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
// LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
// OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
// THE SOFTWARE.
#pragma once
#include "NativeJIT/CodeGen/X64CodeGenerator.h" // OpCode type.
#include "NativeJIT/Nodes/Node.h"
#include "NativeJIT/Packed.h"
namespace NativeJIT
{
template <typename PACKED, bool ISMAX>
class PackedMinMaxNode : public Node<PACKED>
{
public:
PackedMinMaxNode(ExpressionTree& tree,
Node<PACKED>& left,
Node<PACKED>& right);
virtual ExpressionTree::Storage<PACKED> CodeGenValue(ExpressionTree& tree) override;
virtual void Print(std::ostream& out) const override;
private:
// WARNING: This class is designed to be allocated by an arena allocator,
// so its destructor will never be called. Therefore, it should hold no
// resources other than memory from the arena allocator.
~PackedMinMaxNode();
Node<PACKED>& m_left;
Node<PACKED>& m_right;
};
namespace PackedMinMaxHelper
{
// A helper class to emit the code to implement min/max operation
// for the specified PACKED. It does its work by processing the outer
// portion of the PACKED and recursively passing the rest of it to
// the matching MinMaxEmitter.
template <bool ISMAX, typename REGTYPE, typename PACKED>
struct MinMaxEmitter
{
static void Emit(FunctionBuffer& code, REGTYPE left, REGTYPE right);
};
// Specialization for the void PACKED, i.e. the exit from recursion.
template <bool ISMAX, typename REGTYPE>
struct MinMaxEmitter<ISMAX, REGTYPE, void>
{
static void Emit(FunctionBuffer& code, REGTYPE left, REGTYPE right);
};
}
//*************************************************************************
//
// Template definitions for PackedMinMaxNode
//
//*************************************************************************
template <typename PACKED, bool ISMAX>
PackedMinMaxNode<PACKED, ISMAX>::PackedMinMaxNode(ExpressionTree& tree,
Node<PACKED>& left,
Node<PACKED>& right)
: Node<PACKED>(tree),
m_left(left),
m_right(right)
{
static_assert(std::is_pod<PACKED>::value, "PACKED must be a POD type.");
left.IncrementParentCount();
right.IncrementParentCount();
}
template <typename PACKED, bool ISMAX>
ExpressionTree::Storage<PACKED>
PackedMinMaxNode<PACKED, ISMAX>::CodeGenValue(ExpressionTree& tree)
{
auto & code = tree.GetCodeGenerator();
ExpressionTree::Storage<PACKED> sLeft;
ExpressionTree::Storage<PACKED> sRight;
this->CodeGenInOrder(tree,
m_left, sLeft,
m_right, sRight);
// Convert the left and right parameters into direct registers making
// sure that they don't get spilled.
// We will be building the result in the left register and destroy the
// right register in the process.
{
auto l = sLeft.ConvertToDirect(true);
ReferenceCounter lPin = sLeft.GetPin();
auto r = sRight.ConvertToDirect(true);
ReferenceCounter rPin = sRight.GetPin();
// The algorithm works by comparing the left and right register field
// by field. In each step, the left register will contain the result
// for the already processed fields. Bits in both registers are rotated
// after each step so that the fields that are currently being compared
// are in the leftmost portion of the registers. Once the whole process
// is completed, the registers will have been rotated the full circle
// and the left register will contain the final result of the operation.
// Process the unused portion of the PACKED by clearing the unused bits.
// This is done by left-shifting towards the most significant bit.
const auto bitsToShiftToMSB = static_cast<uint8_t>(sizeof(PackedUnderlyingType) * 8
- PACKED::c_totalBitCount);
code.EmitImmediate<OpCode::Shl>(l, bitsToShiftToMSB);
code.EmitImmediate<OpCode::Shl>(r, bitsToShiftToMSB);
// Start the recursion. The helper does not use any additional registers.
typedef decltype(l) RegisterType;
PackedMinMaxHelper::MinMaxEmitter<ISMAX, RegisterType, PACKED>::Emit(code, l, r);
}
return sLeft;
}
template <bool ISMAX, typename REGTYPE, typename PACKED>
void PackedMinMaxHelper::MinMaxEmitter<ISMAX, REGTYPE, PACKED>::Emit(
FunctionBuffer& code,
REGTYPE left,
REGTYPE right)
{
Label keepLeftDigit = code.AllocateLabel();
Label bottomOfLoop = code.AllocateLabel();
// Comparing left to right effectively compares the leftmost fields of
// the two values.
code.Emit<OpCode::Cmp>(left, right);
const JccType jccType = ISMAX ? JccType::JAE : JccType::JB;
code.EmitConditionalJump<jccType>(keepLeftDigit);
// Case: Want the keep the digit from the right parameter.
// Shift the high order bits from the right parameter into the low
// order bits of the left parameter.
code.EmitImmediate<OpCode::Shld>(left, right, static_cast<uint8_t>(PACKED::c_leftmostBitCount));
code.Jmp(bottomOfLoop);
// Case: Want to keep the digit from left parameter.
// Just rotate it around to the low order bits.
code.PlaceLabel(keepLeftDigit);
code.EmitImmediate<OpCode::Rol>(left, static_cast<uint8_t>(PACKED::c_leftmostBitCount));
// In either case, shift off the high order bits or the right parameter.
code.PlaceLabel(bottomOfLoop);
code.EmitImmediate<OpCode::Shl>(right, static_cast<uint8_t>(PACKED::c_leftmostBitCount));
// Process the remainder of the PACKED.
MinMaxEmitter<ISMAX, REGTYPE, typename PACKED::Right>::Emit(code, left, right);
}
template <bool ISMAX, typename REGTYPE>
void PackedMinMaxHelper::MinMaxEmitter<ISMAX, REGTYPE, void>::Emit(
FunctionBuffer& /* code */,
REGTYPE /* left */,
REGTYPE /* right */)
{
// End of recursion, do nothing.
}
template <typename PACKED, bool ISMAX>
void PackedMinMaxNode<PACKED, ISMAX>::Print(std::ostream& out) const
{
this->PrintCoreProperties(out, "PackedMinMaxNode");
out << ", isMax = " << (ISMAX ? "true" : "false")
<< ", left = " << m_left.GetId()
<< ", right = " << m_right.GetId();
}
}
``` | /content/code_sandbox/inc/NativeJIT/Nodes/PackedMinMaxNode.h | objective-c | 2016-04-09T23:53:19 | 2024-06-29T07:05:56 | NativeJIT | BitFunnel/NativeJIT | 1,133 | 1,735 |
```objective-c
// Permission is hereby granted, free of charge, to any person obtaining a copy
// of this software and associated documentation files (the "Software"), to deal
// in the Software without restriction, including without limitation the rights
// to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
// copies of the Software, and to permit persons to whom the Software is
// furnished to do so, subject to the following conditions:
// The above copyright notice and this permission notice shall be included in
// all copies or substantial portions of the Software.
// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
// AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
// LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
// OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
// THE SOFTWARE.
#pragma once
#include <algorithm> // For std::max
#include "NativeJIT/CodeGen/X64CodeGenerator.h"
#include "NativeJIT/CodeGenHelpers.h"
#include "NativeJIT/ExpressionTree.h"
#include "NativeJIT/Nodes/Node.h"
namespace NativeJIT
{
class ExpressionTree;
template <JccType JCC>
class FlagExpressionNode : public Node<bool>
{
public:
FlagExpressionNode(ExpressionTree& tree);
//
// Overrides of NodeBase methods.
//
virtual bool CanBeOptimizedAway() const override;
//
// Overrides of Node<T> methods.
//
virtual void CodeGenFlags(ExpressionTree& tree) = 0;
// Increments the number of parents that use the node's CodeGenFlags()
// method rather than the usual CodeGen() method.
void IncrementFlagsParentCount();
protected:
// WARNING: This class is designed to be allocated by an arena allocator,
// so its destructor will never be called. Therefore, it should hold no
// resources other than memory from the arena allocator.
// Would like to make this private and without method body, but it's
// called implicitly by child class constructors if they throw.
~FlagExpressionNode() {}
private:
unsigned m_flagsParentCount;
};
template <typename T, JccType JCC>
class ConditionalNode : public Node<T>
{
public:
ConditionalNode(ExpressionTree& tree,
FlagExpressionNode<JCC>& condition,
Node<T>& trueExpression,
Node<T>& falseExpression);
//
// Overrides of Node methods.
//
virtual void Print(std::ostream& out) const override;
//
// Overrides of Node<T> methods.
//
virtual ExpressionTree::Storage<T> CodeGenValue(ExpressionTree& tree) override;
private:
// WARNING: This class is designed to be allocated by an arena allocator,
// so its destructor will never be called. Therefore, it should hold no
// resources other than memory from the arena allocator.
~ConditionalNode();
FlagExpressionNode<JCC>& m_condition;
Node<T>& m_trueExpression;
Node<T>& m_falseExpression;
};
template <typename T, JccType JCC>
class RelationalOperatorNode : public FlagExpressionNode<JCC>
{
public:
RelationalOperatorNode(ExpressionTree& tree,
Node<T>& left,
Node<T>& right);
//
// Overrides of Node methods.
//
virtual void Print(std::ostream& out) const override;
//
// Overrides of Node<T> methods.
//
virtual ExpressionTree::Storage<bool> CodeGenValue(ExpressionTree& tree) override;
//
// Overrides of FlagExpression methods.
//
virtual void CodeGenFlags(ExpressionTree& tree) override;
private:
// WARNING: This class is designed to be allocated by an arena allocator,
// so its destructor will never be called. Therefore, it should hold no
// resources other than memory from the arena allocator.
~RelationalOperatorNode();
Node<T>& m_left;
Node<T>& m_right;
};
//*************************************************************************
//
// Template definitions for FlagExpressionNode
//
//*************************************************************************
template <JccType JCC>
FlagExpressionNode<JCC>::FlagExpressionNode(ExpressionTree& tree)
: Node<bool>(tree),
m_flagsParentCount(0)
{
}
template <JccType JCC>
bool FlagExpressionNode<JCC>::CanBeOptimizedAway() const
{
// The node can be optimized away only if it's unused in both contexts
// it can be referrenced from (through CodeGenValue() and CodeGenFlags()).
return Node<bool>::CanBeOptimizedAway() && m_flagsParentCount == 0;
}
template <JccType JCC>
void FlagExpressionNode<JCC>::IncrementFlagsParentCount()
{
++m_flagsParentCount;
MarkReferenced();
}
//*************************************************************************
//
// Template definitions for ConditionalNode
//
//*************************************************************************
template <typename T, JccType JCC>
ConditionalNode<T, JCC>::ConditionalNode(ExpressionTree& tree,
FlagExpressionNode<JCC>& condition,
Node<T>& trueExpression,
Node<T>& falseExpression)
: Node<T>(tree),
m_condition(condition),
m_trueExpression(trueExpression),
m_falseExpression(falseExpression)
{
m_trueExpression.IncrementParentCount();
m_falseExpression.IncrementParentCount();
// Use the CodeGenFlags()-related call.
m_condition.IncrementFlagsParentCount();
}
template <typename T, JccType JCC>
void ConditionalNode<T, JCC>::Print(std::ostream& out) const
{
const std::string name = std::string("Conditional(")
+ X64CodeGenerator::JccName(JCC)
+ ") ";
this->PrintCoreProperties(out, name.c_str());
out << ", condition = " << m_condition.GetId();
out << ", trueExpression = " << m_trueExpression.GetId();
out << ", falseExpression = " << m_falseExpression.GetId();
}
template <typename T, JccType JCC>
typename ExpressionTree::Storage<T> ConditionalNode<T, JCC>::CodeGenValue(ExpressionTree& tree)
{
X64CodeGenerator& code = tree.GetCodeGenerator();
Label conditionIsTrue = code.AllocateLabel();
Label testCompleted = code.AllocateLabel();
// TODO: Evaluating both expressions in advance of the test is
// sub-optimal, but it is currently required to guarantee consistent
// state: the execution in NativeJIT has a continuous flow regardless
// of the outcome of the (runtime) condition whereas the generated x64
// code has two branches and each of them can have independent impact on
// allocated and spilled registers. To have each expression evaluated
// only if its branch is hit, the NativeJIT code would have to ensure
// that the state of the allocated/spilled registers (i.e. all Storages)
// is consistent once those two x64 branches converge back.
//
// A related note: if this is addressed, then it may be possible to
// also address the fact that common subexpression (CSE) code is
// inefficient in some cases because some CSEs may not need to be
// evaluated. For example:
// (v == 1)? a : ((v == 2) ? a + b : b + c)
//
// Depending on the value of v, either a or c may not need to be
// evaluated. One possibility is to lazily evaluate CSEs *at runtime*
// as they are needed.
// See bug#27
Storage<T> trueValue;
Storage<T> falseValue;
this->CodeGenInOrder(tree,
m_trueExpression, trueValue,
m_falseExpression, falseValue);
// Enum that specifies whether the result storage currently holds the
// true value, false value or neither of them.
enum class ResultContents { NeitherValue, TrueValue, FalseValue };
ResultContents resultContents;
Storage<T> result;
{
// Evaluate the condition to update the CPU flags. No code in this
// block is allowed to modify the flags up until the
// EmitConditionalJump() call at the end. Spilling (i.e. the MOV
// instructions used used to copy the spilled value from register
// to stack) does not affect any flags.
m_condition.CodeGenFlags(tree);
// Try to re-use a direct register from true/false expressions if
// possible, otherwise allocate a register. The allocation must be
// done before the conditional jump so that any register spills
// apply to both branches.
if (trueValue.GetStorageClass() == StorageClass::Direct
&& trueValue.IsSoleDataOwner())
{
result = trueValue;
resultContents = ResultContents::TrueValue;
}
else if (falseValue.GetStorageClass() == StorageClass::Direct
&& falseValue.IsSoleDataOwner())
{
result = falseValue;
resultContents = ResultContents::FalseValue;
}
else
{
result = tree.Direct<T>();
resultContents = ResultContents::NeitherValue;
}
code.EmitConditionalJump<JCC>(conditionIsTrue);
}
// Emit the code for the "condition is false" branch.
// Move the false value to the result register unless it's already there.
if (resultContents != ResultContents::FalseValue)
{
CodeGenHelpers::Emit<OpCode::Mov>(code, result.GetDirectRegister(), falseValue);
}
// Jump behind the true branch, unless the true branch is empty. The true
// branch is empty only if the true value is already in the result storage.
if (!(resultContents == ResultContents::TrueValue))
{
code.Jmp(testCompleted);
}
// Emit the code for the "condition is true" branch.
code.PlaceLabel(conditionIsTrue);
// Move the true value in the result register unless it's already there.
if (resultContents != ResultContents::TrueValue)
{
CodeGenHelpers::Emit<OpCode::Mov>(code, result.GetDirectRegister(), trueValue);
}
code.PlaceLabel(testCompleted);
return result;
}
//*************************************************************************
//
// Template definitions for RelationalOperator
//
//*************************************************************************
template <typename T, JccType JCC>
RelationalOperatorNode<T, JCC>::RelationalOperatorNode(ExpressionTree& tree,
Node<T>& left,
Node<T>& right)
: FlagExpressionNode<JCC>(tree),
m_left(left),
m_right(right)
{
m_left.IncrementParentCount();
m_right.IncrementParentCount();
}
template <typename T, JccType JCC>
void RelationalOperatorNode<T, JCC>::Print(std::ostream& out) const
{
const std::string name = std::string("RelationalOperatorNode(")
+ X64CodeGenerator::JccName(JCC)
+ ") ";
this->PrintCoreProperties(out, name.c_str());
out << ", left = " << m_left.GetId();
out << ", right = " << m_right.GetId();
}
template <typename T, JccType JCC>
typename ExpressionTree::Storage<bool> RelationalOperatorNode<T, JCC>::CodeGenValue(ExpressionTree& tree)
{
X64CodeGenerator& code = tree.GetCodeGenerator();
Label conditionIsTrue = code.AllocateLabel();
Label testCompleted = code.AllocateLabel();
// Evaluate the condition and react based on it.
CodeGenFlags(tree);
// Allocate the result register before the conditional jump so that
// if any register gets spilled, the spill applies to both branches.
// The spilling (i.e. the MOV instruction that is used to copy the
// spilled value from the register onto stack) does not affect any flags.
auto result = tree.Direct<bool>();
code.EmitConditionalJump<JCC>(conditionIsTrue);
code.EmitImmediate<OpCode::Mov>(result.GetDirectRegister(), false);
code.Jmp(testCompleted);
code.PlaceLabel(conditionIsTrue);
code.EmitImmediate<OpCode::Mov>(result.GetDirectRegister(), true);
code.PlaceLabel(testCompleted);
return result;
}
template <typename T, JccType JCC>
void RelationalOperatorNode<T, JCC>::CodeGenFlags(ExpressionTree& tree)
{
Storage<T> sLeft;
Storage<T> sRight;
this->CodeGenInOrder(tree,
m_left, sLeft,
m_right, sRight);
CodeGenHelpers::Emit<OpCode::Cmp>(tree.GetCodeGenerator(), sLeft.ConvertToDirect(false), sRight);
}
}
``` | /content/code_sandbox/inc/NativeJIT/Nodes/ConditionalNode.h | objective-c | 2016-04-09T23:53:19 | 2024-06-29T07:05:56 | NativeJIT | BitFunnel/NativeJIT | 1,133 | 2,812 |
```objective-c
// Permission is hereby granted, free of charge, to any person obtaining a copy
// of this software and associated documentation files (the "Software"), to deal
// in the Software without restriction, including without limitation the rights
// to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
// copies of the Software, and to permit persons to whom the Software is
// furnished to do so, subject to the following conditions:
// The above copyright notice and this permission notice shall be included in
// all copies or substantial portions of the Software.
// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
// AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
// LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
// OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
// THE SOFTWARE.
#pragma once
#include "NativeJIT/Nodes/Node.h"
#include "NativeJIT/TypePredicates.h"
namespace NativeJIT
{
template <typename T, ImmediateCategory IMMCATEGORY = ImmediateCategoryOf<T>::value>
class ImmediateNode;
//*************************************************************************
//
// Template specializations for ImmediateNode for InlineImmediate types.
//
//*************************************************************************
template <typename T>
class ImmediateNode<T, ImmediateCategory::InlineImmediate> : public Node<T>
{
public:
ImmediateNode(ExpressionTree& tree, T value);
//
// Overrides of Node methods
//
virtual void Print(std::ostream& out) const override;
virtual ExpressionTree::Storage<T> CodeGenValue(ExpressionTree& tree) override;
private:
// WARNING: This class is designed to be allocated by an arena allocator,
// so its destructor will never be called. Therefore, it should hold no
// resources other than memory from the arena allocator.
~ImmediateNode();
T m_value;
};
//*************************************************************************
//
// Template specializations for ImmediateNode for RIPRelativeImmediate types.
//
//*************************************************************************
class RIPRelativeImmediate
{
public:
virtual void EmitStaticData(ExpressionTree& tree) = 0;
};
template <typename T>
class ImmediateNode<T, ImmediateCategory::RIPRelativeImmediate>
: public Node<T>,
public RIPRelativeImmediate
{
public:
ImmediateNode(ExpressionTree& tree, T value);
//
// Overrides of Node methods
//
virtual void Print(std::ostream& out) const override;
virtual ExpressionTree::Storage<T> CodeGenValue(ExpressionTree& tree) override;
//
// Overrides of RIPRelativeImmediate methods
//
virtual void EmitStaticData(ExpressionTree& tree) override;
private:
// WARNING: This class is designed to be allocated by an arena allocator,
// so its destructor will never be called. Therefore, it should hold no
// resources other than memory from the arena allocator.
~ImmediateNode();
T m_value;
int32_t m_offset;
};
}
``` | /content/code_sandbox/inc/NativeJIT/Nodes/ImmediateNodeDecls.h | objective-c | 2016-04-09T23:53:19 | 2024-06-29T07:05:56 | NativeJIT | BitFunnel/NativeJIT | 1,133 | 676 |
```objective-c
// Permission is hereby granted, free of charge, to any person obtaining a copy
// of this software and associated documentation files (the "Software"), to deal
// in the Software without restriction, including without limitation the rights
// to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
// copies of the Software, and to permit persons to whom the Software is
// furnished to do so, subject to the following conditions:
// The above copyright notice and this permission notice shall be included in
// all copies or substantial portions of the Software.
// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
// AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
// LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
// OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
// THE SOFTWARE.
#pragma once
#include <type_traits>
#include "NativeJIT/CodeGen/X64CodeGenerator.h" // OpCode type.
#include "NativeJIT/Nodes/Node.h"
namespace NativeJIT
{
// Implements a binary node that requires a constant as a right hand
// argument. Unlike the regular binary node, the constant cannot end up
// in a register, be spilled to a temporary etc, it's always a constant.
template <OpCode OP, typename L, typename R>
class BinaryImmediateNode : public Node<L>
{
public:
static_assert(std::is_integral<R>::value,
"The right side must have an integral immediate type");
BinaryImmediateNode(ExpressionTree& tree, Node<L>& left, R right);
virtual Storage<L> CodeGenValue(ExpressionTree& tree) override;
virtual void Print(std::ostream& out) const override;
private:
// WARNING: This class is designed to be allocated by an arena allocator,
// so its destructor will never be called. Therefore, it should hold no
// resources other than memory from the arena allocator.
~BinaryImmediateNode();
Node<L>& m_left;
const R m_right;
};
//*************************************************************************
//
// Template definitions for BinaryImmediateNode
//
//*************************************************************************
template <OpCode OP, typename L, typename R>
BinaryImmediateNode<OP, L, R>::BinaryImmediateNode(
ExpressionTree& tree, Node<L>& left, R right)
: Node<L>(tree),
m_left(left),
m_right(right)
{
m_left.IncrementParentCount();
// m_right is not a Node, so no IncrementParentCount() call.
}
template <OpCode OP, typename L, typename R>
Storage<L> BinaryImmediateNode<OP, L, R>::CodeGenValue(ExpressionTree& tree)
{
auto & code = tree.GetCodeGenerator();
auto left = m_left.CodeGen(tree);
code.EmitImmediate<OP>(left.ConvertToDirect(true), m_right);
return left;
}
template <OpCode OP, typename L, typename R>
void BinaryImmediateNode<OP, L, R>::Print(std::ostream& out) const
{
const std::string name = std::string("Operation (")
+ X64CodeGenerator::OpCodeName(OP)
+ ") ";
this->PrintCoreProperties(out, name.c_str());
out << ", left = " << m_left.GetId()
<< ", right = " << m_right;
}
}
``` | /content/code_sandbox/inc/NativeJIT/Nodes/BinaryImmediateNode.h | objective-c | 2016-04-09T23:53:19 | 2024-06-29T07:05:56 | NativeJIT | BitFunnel/NativeJIT | 1,133 | 767 |
```objective-c
// Permission is hereby granted, free of charge, to any person obtaining a copy
// of this software and associated documentation files (the "Software"), to deal
// in the Software without restriction, including without limitation the rights
// to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
// copies of the Software, and to permit persons to whom the Software is
// furnished to do so, subject to the following conditions:
// The above copyright notice and this permission notice shall be included in
// all copies or substantial portions of the Software.
// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
// AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
// LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
// OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
// THE SOFTWARE.
#pragma once
#include "NativeJIT/Nodes/Node.h"
namespace NativeJIT
{
template <typename OBJECT, typename FIELD>
class FieldPointerNode : public Node<FIELD*>
{
public:
FieldPointerNode(ExpressionTree& tree, Node<OBJECT*>& base, FIELD OBJECT::*field);
//
// Overrides of Node methods
//
virtual ExpressionTree::Storage<FIELD*> CodeGenValue(ExpressionTree& tree) override;
virtual void Print(std::ostream& out) const override;
virtual void ReleaseReferencesToChildren() override;
protected:
virtual bool GetBaseAndOffset(NodeBase*& base, int32_t& offset) const override;
private:
// WARNING: This class is designed to be allocated by an arena allocator,
// so its destructor will never be called. Therefore, it should hold no
// resources other than memory from the arena allocator.
~FieldPointerNode();
static int32_t Offset(FIELD OBJECT::*field)
{
return static_cast<int32_t>(reinterpret_cast<uint64_t>(&((static_cast<OBJECT*>(nullptr))->*field)));
}
NodeBase& m_base;
const int32_t m_originalOffset;
// Multiple accesses to the same base object can sometimes be collapsed
// as an optimization. In such cases, m_collapsedBase/Offset will point
// to such base object. Otherwise, they will match the base object/offset
// from the constructor.
// IMPORTANT: the constructor depends on collapsed base/offset being
// listed after the original base/offset.
NodeBase* m_collapsedBase;
int32_t m_collapsedOffset;
};
//*************************************************************************
//
// Template definitions for FieldPointerNode
//
//*************************************************************************
template <typename OBJECT, typename FIELD>
FieldPointerNode<OBJECT, FIELD>::FieldPointerNode(ExpressionTree& tree,
Node<OBJECT*>& base,
FIELD OBJECT::*field)
: Node<FIELD*>(tree),
m_base(base),
m_originalOffset(Offset(field)),
// Note: there is constructor order dependency for these two.
m_collapsedBase(&m_base),
m_collapsedOffset(m_originalOffset)
{
NodeBase* grandparent;
int32_t parentOffset;
// If base can be represented off of another object with an added offset,
// make the reference off of that object and adjust the offset.
if (base.GetBaseAndOffset(grandparent, parentOffset))
{
m_collapsedBase = grandparent;
m_collapsedOffset += parentOffset;
base.MarkReferenced();
}
m_collapsedBase->IncrementParentCount();
}
template <typename OBJECT, typename FIELD>
typename ExpressionTree::Storage<FIELD*> FieldPointerNode<OBJECT, FIELD>::CodeGenValue(ExpressionTree& tree)
{
auto base = m_collapsedBase->CodeGenAsBase(tree);
if (m_collapsedOffset == 0)
{
base.ConvertToDirect(false);
}
else
{
base.ConvertToDirect(true);
tree.GetCodeGenerator()
.EmitImmediate<OpCode::Add>(base.GetDirectRegister(), m_collapsedOffset);
}
// With the added offset, the type changes from void* to FIELD*.
return ExpressionTree::Storage<FIELD*>(base);
}
template <typename OBJECT, typename FIELD>
bool FieldPointerNode<OBJECT, FIELD>::GetBaseAndOffset(NodeBase*& base, int32_t& offset) const
{
base = m_collapsedBase;
offset = m_collapsedOffset;
return true;
}
template <typename OBJECT, typename FIELD>
void FieldPointerNode<OBJECT, FIELD>::ReleaseReferencesToChildren()
{
m_collapsedBase->DecrementParentCount();
}
template <typename OBJECT, typename FIELD>
void FieldPointerNode<OBJECT, FIELD>::Print(std::ostream& out) const
{
this->PrintCoreProperties(out, "FieldPointerNode");
out << ", base ID = " << m_base.GetId()
<< ", offset = " << m_originalOffset;
if (m_base.GetId() != m_collapsedBase->GetId())
{
out
<< ", collapsed base ID = " << m_collapsedBase->GetId()
<< ", collapsed offset = " << m_collapsedOffset;
}
}
}
``` | /content/code_sandbox/inc/NativeJIT/Nodes/FieldPointerNode.h | objective-c | 2016-04-09T23:53:19 | 2024-06-29T07:05:56 | NativeJIT | BitFunnel/NativeJIT | 1,133 | 1,152 |
```objective-c
// Permission is hereby granted, free of charge, to any person obtaining a copy
// of this software and associated documentation files (the "Software"), to deal
// in the Software without restriction, including without limitation the rights
// to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
// copies of the Software, and to permit persons to whom the Software is
// furnished to do so, subject to the following conditions:
// The above copyright notice and this permission notice shall be included in
// all copies or substantial portions of the Software.
// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
// AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
// LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
// OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
// THE SOFTWARE.
#pragma once
#include <iostream> // Accessed by template definition for Print().
#include "NativeJIT/AllocatorVector.h" // Embedded member.
#include "NativeJIT/CodeGenHelpers.h"
#include "NativeJIT/Nodes/Node.h" // Base class.
#include "NativeJIT/TypePredicates.h"
// path_to_url
namespace NativeJIT
{
class ExpressionTree;
class SaveRestoreVolatilesHelper
{
protected:
SaveRestoreVolatilesHelper(Allocators::IAllocator& allocator);
public:
// These methods need to be public for access by
// CallNodeBase::FunctionChild
// CallNodeBase::ParameterChild
void SaveVolatiles(ExpressionTree& tree);
void RestoreVolatiles(ExpressionTree& tree);
template <unsigned SIZE, bool ISFLOAT>
void RecordCallRegister(Register<SIZE, ISFLOAT> r, bool isSoleOwner);
protected:
// WARNING: This class is designed to be allocated by an arena allocator,
// so its destructor will never be called. Therefore, it should hold no
// resources other than memory from the arena allocator.
// Would like to make this private and without method body, but it's
// called implicitly by child class constructors if they throw.
~SaveRestoreVolatilesHelper() {}
private:
// Returns the mask for the registers it's necessary to preserve accross
// the function call that's being made.
template <bool ISFLOAT>
unsigned GetRegistersToPreserve(ExpressionTree& tree) const;
// A bit-mask of registers that are exclusively owned for the function
// call and thus don't need to be preserved.
unsigned m_rxxCallExclusiveRegisterMask;
unsigned m_xmmCallExclusiveRegisterMask;
// Temporary storage used to preserve volatile registers.
AllocatorVector<Storage<void*>> m_preservationStorage;
};
template <typename R, unsigned PARAMETERCOUNT>
class CallNodeBase : public Node<R>, public SaveRestoreVolatilesHelper
{
public:
CallNodeBase(ExpressionTree& tree);
//
// Overrides of Node methods.
//
virtual ExpressionTree::Storage<R> CodeGenValue(ExpressionTree& tree) override;
virtual void Print(std::ostream& out) const override;
protected:
// WARNING: This class is designed to be allocated by an arena allocator,
// so its destructor will never be called. Therefore, it should hold no
// resources other than memory from the arena allocator.
// Would like to make this private and without method body, but it's
// called implicitly by child class constructors if they throw.
~CallNodeBase() {}
protected:
class Child : private NonCopyable
{
public:
// Generates the code to evaluate the expression inside the child.
virtual void Evaluate(ExpressionTree& tree) = 0;
// Emits the code to place the child's value into the appropriate
// register or stack location depending on the type and position
// of the child.
// The staging must not modify any other registers reserved for the
// function call by the calling convention, so the child must already
// be evaluated before it can be staged.
virtual void EmitStaging(ExpressionTree& tree, SaveRestoreVolatilesHelper& volatiles) = 0;
// Releases any registers used during the evaluation of the child
// expression in Evaluate().
virtual void Release() = 0;
// Prints the contents of the child to standard output for debugging.
virtual void Print(std::ostream& out) const = 0;
};
template <typename T>
class TypedChild : public Child
{
public:
TypedChild(Node<T>& expression);
//
// Overrides of Child methods.
//
virtual void Release();
protected:
// Pins the storage register so that it cannot be spilled until
// the Release() call.
void PinStorageRegister();
Node<T>& m_expression;
ExpressionTree::Storage<T> m_storage;
ReferenceCounter m_registerPin;
};
template <typename T>
class ParameterChild : public TypedChild<T>
{
public:
ParameterChild(Node<T>& expression, unsigned position);
typename ExpressionTree::Storage<T>::DirectRegister GetRegister() const;
//
// Overrides of Child methods.
//
virtual void Evaluate(ExpressionTree& tree) override;
virtual void EmitStaging(ExpressionTree& tree,
SaveRestoreVolatilesHelper& volatiles) override;
virtual void Print(std::ostream& out) const override;
private:
typename ExpressionTree::Storage<T>::DirectRegister m_destination;
};
class FunctionChildBase
{
public:
virtual void EmitCall(ExpressionTree& tree) = 0;
};
template <typename T>
class FunctionChild : public FunctionChildBase, public TypedChild<T>
{
public:
FunctionChild(Node<T>& expression,
typename Storage<R>::DirectRegister resultRegister);
//
// Overrides of Child methods.
//
virtual void Evaluate(ExpressionTree& tree) override;
virtual void EmitStaging(ExpressionTree& tree,
SaveRestoreVolatilesHelper& volatiles) override;
//
// Overrides of FunctionChildBase methods.
//
virtual void EmitCall(ExpressionTree& tree) override;
virtual void Print(std::ostream& out) const override;
private:
typename Storage<R>::DirectRegister m_resultRegister;
};
// One child for each parameter plus one for the function pointer.
static const unsigned c_childCount = PARAMETERCOUNT + 1;
Child* m_children[c_childCount];
// Pointer to function's two base classes.
FunctionChildBase* m_functionBase;
Child* m_functionChild;
};
template <typename R, typename P1 = void, typename P2 = void, typename P3 = void, typename P4 = void>
class CallNode;
template <typename R>
class CallNode<R> : public CallNodeBase<R, 0>
{
public:
typedef R (*FunctionPointer)();
CallNode(ExpressionTree& tree,
Node<FunctionPointer>& function);
private:
// WARNING: This class is designed to be allocated by an arena allocator,
// so its destructor will never be called. Therefore, it should hold no
// resources other than memory from the arena allocator.
~CallNode();
typename CallNodeBase<R, 0>::template FunctionChild<FunctionPointer> m_f;
};
template <typename R, typename P1>
class CallNode<R, P1> : public CallNodeBase<R, 1>
{
public:
typedef R (*FunctionPointer)(P1);
CallNode(ExpressionTree& tree,
Node<FunctionPointer>& function,
Node<P1>& p1);
private:
// WARNING: This class is designed to be allocated by an arena allocator,
// so its destructor will never be called. Therefore, it should hold no
// resources other than memory from the arena allocator.
~CallNode();
typename CallNodeBase<R, 1>::template FunctionChild<FunctionPointer> m_f;
typename CallNodeBase<R, 1>::template ParameterChild<P1> m_p1;
};
template <typename R, typename P1, typename P2>
class CallNode<R, P1, P2> : public CallNodeBase<R, 2>
{
public:
typedef R (*FunctionPointer)(P1, P2);
CallNode(ExpressionTree& tree,
Node<FunctionPointer>& function,
Node<P1>& p1,
Node<P2>& p2);
private:
// WARNING: This class is designed to be allocated by an arena allocator,
// so its destructor will never be called. Therefore, it should hold no
// resources other than memory from the arena allocator.
~CallNode();
typename CallNodeBase<R, 2>::template FunctionChild<FunctionPointer> m_f;
typename CallNodeBase<R, 2>::template ParameterChild<P1> m_p1;
typename CallNodeBase<R, 2>::template ParameterChild<P2> m_p2;
};
template <typename R, typename P1, typename P2, typename P3>
class CallNode<R, P1, P2, P3> : public CallNodeBase<R, 3>
{
public:
typedef R (*FunctionPointer)(P1, P2, P3);
CallNode(ExpressionTree& tree,
Node<FunctionPointer>& function,
Node<P1>& p1,
Node<P2>& p2,
Node<P3>& p3);
private:
// WARNING: This class is designed to be allocated by an arena allocator,
// so its destructor will never be called. Therefore, it should hold no
// resources other than memory from the arena allocator.
~CallNode();
typename CallNodeBase<R, 3>::template FunctionChild<FunctionPointer> m_f;
typename CallNodeBase<R, 3>::template ParameterChild<P1> m_p1;
typename CallNodeBase<R, 3>::template ParameterChild<P2> m_p2;
typename CallNodeBase<R, 3>::template ParameterChild<P3> m_p3;
};
template <typename R, typename P1, typename P2, typename P3, typename P4>
class CallNode : public CallNodeBase<R, 4>
{
public:
typedef R (*FunctionPointer)(P1, P2, P3, P4);
CallNode(ExpressionTree& tree,
Node<FunctionPointer>& function,
Node<P1>& p1,
Node<P2>& p2,
Node<P3>& p3,
Node<P4>& p4);
private:
// WARNING: This class is designed to be allocated by an arena allocator,
// so its destructor will never be called. Therefore, it should hold no
// resources other than memory from the arena allocator.
~CallNode();
typename CallNodeBase<R, 4>::template FunctionChild<FunctionPointer> m_f;
typename CallNodeBase<R, 4>::template ParameterChild<P1> m_p1;
typename CallNodeBase<R, 4>::template ParameterChild<P2> m_p2;
typename CallNodeBase<R, 4>::template ParameterChild<P3> m_p3;
typename CallNodeBase<R, 4>::template ParameterChild<P4> m_p4;
};
//*************************************************************************
//
// Template definitions for SaveRestoreVolatilesHelper.
//
//*************************************************************************
template <unsigned SIZE, bool ISFLOAT>
void SaveRestoreVolatilesHelper::RecordCallRegister(Register<SIZE, ISFLOAT> r, bool isSoleOwner)
{
if (isSoleOwner)
{
BitOp::SetBit(ISFLOAT ? &m_xmmCallExclusiveRegisterMask : &m_rxxCallExclusiveRegisterMask,
r.GetId());
}
}
//*************************************************************************
//
// Template definitions for CallNodeBase<R, PARAMETERCOUNT>
//
//*************************************************************************
template <typename R, unsigned PARAMETERCOUNT>
CallNodeBase<R, PARAMETERCOUNT>::CallNodeBase(ExpressionTree& tree)
: Node<R>(tree),
SaveRestoreVolatilesHelper(tree.GetAllocator())
{
static_assert(IsValidParameter<R>::c_value, "R is an invalid type.");
tree.ReportFunctionCallNode(PARAMETERCOUNT);
}
template <typename R, unsigned PARAMETERCOUNT>
ExpressionTree::Storage<R> CallNodeBase<R, PARAMETERCOUNT>::CodeGenValue(ExpressionTree& tree)
{
// Make sure that the result register is not pinned at this point.
auto const resultRegister = tree.GetResultRegister<R>();
LogThrowAssert(!tree.IsPinned(resultRegister), "The result register must not be pinned before the call");
// Evaluate the function pointer and each parameter.
for (Child* child : m_children)
{
child->Evaluate(tree);
}
for (Child* child : m_children)
{
// Stage the parameters first since they need to be placed into
// fixed registers.
if (child != m_functionChild)
{
child->EmitStaging(tree, *this);
}
}
// Stage the function pointer into a register last since it can be staged
// staged into any register.
m_functionChild->EmitStaging(tree, *this);
// If the result register is still not pinned (and thus unused by the
// call), enforce ownership over it.
if (!tree.IsPinned(resultRegister))
{
// Release the register right away by not keeping the Storage.
tree.Direct<R>(resultRegister);
RecordCallRegister(resultRegister, true);
}
SaveVolatiles(tree);
m_functionBase->EmitCall(tree);
RestoreVolatiles(tree);
// Free up registers used for function pointer and parameters.
for (Child* child : m_children)
{
child->Release();
}
// At this point, the result register was either used by a parameter or
// the function pointer and then released, or it was empty after the
// explicit bump further above so the following call will bump nothing.
return tree.Direct<R>(resultRegister);
}
template <typename R, unsigned PARAMETERCOUNT>
void CallNodeBase<R, PARAMETERCOUNT>::Print(std::ostream& out) const
{
this->PrintCoreProperties(out, "CallNode");
for (unsigned i = 0 ; i < c_childCount; ++i)
{
out << ", ";
m_children[i]->Print(out);
}
}
//*************************************************************************
//
// Template definitions for
// CallNodeBase<R, PARAMETERCOUNT>::TypedChild<T>
//
//*************************************************************************
template <typename R, unsigned PARAMETERCOUNT>
template <typename T>
CallNodeBase<R, PARAMETERCOUNT>::TypedChild<T>::TypedChild(Node<T>& expression)
: m_expression(expression)
{
m_expression.IncrementParentCount();
}
template <typename R, unsigned PARAMETERCOUNT>
template <typename T>
void CallNodeBase<R, PARAMETERCOUNT>::TypedChild<T>::Release()
{
// Release the register pin and reset the storage to release the register.
m_registerPin.Reset();
m_storage.Reset();
}
template <typename R, unsigned PARAMETERCOUNT>
template <typename T>
void CallNodeBase<R, PARAMETERCOUNT>::TypedChild<T>::PinStorageRegister()
{
LogThrowAssert(!m_storage.IsNull(), "Storage must be initialized");
if (m_storage.GetStorageClass() == StorageClass::Direct)
{
m_registerPin = m_storage.GetPin();
}
}
//*************************************************************************
//
// Template definitions for
// CallNodeBase<R, PARAMETERCOUNT>::FunctionChild<F>
//
//*************************************************************************
template <typename R, unsigned PARAMETERCOUNT>
template <typename F>
CallNodeBase<R, PARAMETERCOUNT>::FunctionChild<F>::FunctionChild(
Node<F>& expression,
typename Storage<R>::DirectRegister resultRegister)
: TypedChild<F>(expression),
m_resultRegister(resultRegister)
{
}
template <typename R, unsigned PARAMETERCOUNT>
template <typename F>
void CallNodeBase<R, PARAMETERCOUNT>::FunctionChild<F>::Evaluate(ExpressionTree& tree)
{
this->m_storage = this->m_expression.CodeGen(tree);
}
template <typename R, unsigned PARAMETERCOUNT>
template <typename F>
void CallNodeBase<R, PARAMETERCOUNT>::FunctionChild<F>::EmitStaging(ExpressionTree& /* tree */,
SaveRestoreVolatilesHelper& volatiles)
{
auto & storage = this->m_storage;
// The CALL instruction requires a direct register, ensure that's the case.
// Convert for modification to ensure that the register doesn't need
// to be preserved accross the call.
if (storage.GetStorageClass() != StorageClass::Direct)
{
storage.ConvertToDirect(true);
}
// If function pointer happens to be in the result register and there
// are other owners, they must be spilled out of the register. Otherwise,
// the attempt to restore the contents into the result register after
// the call would overwrite the returned result.
if (!storage.IsSoleDataOwner()
&& storage.GetDirectRegister().IsSameHardwareRegister(m_resultRegister))
{
storage.TakeSoleOwnershipOfDirect();
}
volatiles.RecordCallRegister(storage.GetDirectRegister(),
storage.IsSoleDataOwner());
// Make sure that nothing takes away this register.
// NOTE: This depends on the fact that the function pointer is staged
// last to ensure that a fixked parameter register is not picked.
this->PinStorageRegister();
}
template <typename R, unsigned PARAMETERCOUNT>
template <typename F>
void CallNodeBase<R, PARAMETERCOUNT>::FunctionChild<F>::EmitCall(ExpressionTree& tree)
{
tree.GetCodeGenerator().Emit<OpCode::Call>(this->m_storage.GetDirectRegister());
}
template <typename R, unsigned PARAMETERCOUNT>
template <typename F>
void CallNodeBase<R, PARAMETERCOUNT>::FunctionChild<F>::Print(std::ostream& out) const
{
out << "function(" << this->m_expression.GetId() << ")";
}
//*************************************************************************
//
// Template definitions for
// CallNodeBase<R, PARAMETERCOUNT>::ParameterChild<F>
//
//*************************************************************************
template <typename R, unsigned PARAMETERCOUNT>
template <typename T>
CallNodeBase<R, PARAMETERCOUNT>::ParameterChild<T>::ParameterChild(Node<T>& expression, unsigned position)
: TypedChild<T>(expression)
{
GetParameterRegister(position, m_destination);
}
template <typename R, unsigned PARAMETERCOUNT>
template <typename T>
void CallNodeBase<R, PARAMETERCOUNT>::ParameterChild<T>::Evaluate(ExpressionTree& tree)
{
this->m_storage = this->m_expression.CodeGen(tree);
}
template <typename R, unsigned PARAMETERCOUNT>
template <typename T>
void CallNodeBase<R, PARAMETERCOUNT>::ParameterChild<T>::EmitStaging(ExpressionTree& tree,
SaveRestoreVolatilesHelper& volatiles)
{
if (this->m_storage.GetStorageClass() != StorageClass::Direct
|| !this->m_storage.GetDirectRegister().IsSameHardwareRegister(m_destination))
{
ExpressionTree::Storage<T> regStorage = tree.Direct<T>(m_destination);
CodeGenHelpers::Emit<OpCode::Mov>(tree.GetCodeGenerator(), m_destination, this->m_storage);
this->m_storage = regStorage;
}
// DESIGN NOTE: There's room for optimization if the data was already in the
// correct register and shared. If there are some free non-volatile
// registers, it would be better to enforce sole ownership of m_storage
// by spilling to such register (the callee may not be using it and may
// not need to push it to/pop it from the stack). Currently, in such
// case the register will always get pushed/popped by SaveRestoreVolatilesHelper.
volatiles.RecordCallRegister(this->m_storage.GetDirectRegister(),
this->m_storage.IsSoleDataOwner());
// The parameter needs to remain in the specified register.
this->PinStorageRegister();
}
template <typename R, unsigned PARAMETERCOUNT>
template <typename T>
void CallNodeBase<R, PARAMETERCOUNT>::ParameterChild<T>::Print(std::ostream& out) const
{
out << "parameter(" << this->m_expression.GetId() << ")";
}
//*************************************************************************
//
// Template definitions for CallNode<R, P1, P2>
//
//*************************************************************************
template <typename R>
CallNode<R>::CallNode(ExpressionTree& tree,
Node<FunctionPointer>& function)
: CallNodeBase<R, 0>(tree),
m_f(function, tree.GetResultRegister<R>())
{
static_assert(IsValidParameter<R>::c_value, "R is an invalid type.");
this->m_functionBase = &m_f;
this->m_functionChild = &m_f;
this->m_children[0] = this->m_functionChild;
}
template <typename R, typename P1>
CallNode<R, P1>::CallNode(ExpressionTree& tree,
Node<FunctionPointer>& function,
Node<P1>& p1)
: CallNodeBase<R, 1>(tree),
m_f(function, tree.GetResultRegister<R>()),
m_p1(p1, 0)
{
static_assert(IsValidParameter<R>::c_value, "R is an invalid type.");
static_assert(IsValidParameter<P1>::c_value, "P1 is an invalid type.");
this->m_functionBase = &m_f;
this->m_functionChild = &m_f;
this->m_children[0] = this->m_functionChild;
this->m_children[1] = &m_p1;
}
template <typename R, typename P1, typename P2>
CallNode<R, P1, P2>::CallNode(ExpressionTree& tree,
Node<FunctionPointer>& function,
Node<P1>& p1,
Node<P2>& p2)
: CallNodeBase<R, 2>(tree),
m_f(function, tree.GetResultRegister<R>()),
m_p1(p1, 0),
m_p2(p2, 1)
{
static_assert(IsValidParameter<R>::c_value, "R is an invalid type.");
static_assert(IsValidParameter<P1>::c_value, "P1 is an invalid type.");
static_assert(IsValidParameter<P2>::c_value, "P2 is an invalid type.");
this->m_functionBase = &m_f;
this->m_functionChild = &m_f;
this->m_children[0] = this->m_functionChild;
this->m_children[1] = &m_p1;
this->m_children[2] = &m_p2;
}
template <typename R, typename P1, typename P2, typename P3>
CallNode<R, P1, P2, P3>::CallNode(ExpressionTree& tree,
Node<FunctionPointer>& function,
Node<P1>& p1,
Node<P2>& p2,
Node<P3>& p3)
: CallNodeBase<R, 3>(tree),
m_f(function, tree.GetResultRegister<R>()),
m_p1(p1, 0),
m_p2(p2, 1),
m_p3(p3, 2)
{
static_assert(IsValidParameter<R>::c_value, "R is an invalid type.");
static_assert(IsValidParameter<P1>::c_value, "P1 is an invalid type.");
static_assert(IsValidParameter<P2>::c_value, "P2 is an invalid type.");
static_assert(IsValidParameter<P3>::c_value, "P3 is an invalid type.");
this->m_functionBase = &m_f;
this->m_functionChild = &m_f;
this->m_children[0] = this->m_functionChild;
this->m_children[1] = &m_p1;
this->m_children[2] = &m_p2;
this->m_children[3] = &m_p3;
}
template <typename R, typename P1, typename P2, typename P3, typename P4>
CallNode<R, P1, P2, P3, P4>::CallNode(ExpressionTree& tree,
Node<FunctionPointer>& function,
Node<P1>& p1,
Node<P2>& p2,
Node<P3>& p3,
Node<P4>& p4)
: CallNodeBase<R, 4>(tree),
m_f(function, tree.GetResultRegister<R>()),
m_p1(p1, 0),
m_p2(p2, 1),
m_p3(p3, 2),
m_p4(p4, 3)
{
static_assert(IsValidParameter<R>::c_value, "R is an invalid type.");
static_assert(IsValidParameter<P1>::c_value, "P1 is an invalid type.");
static_assert(IsValidParameter<P2>::c_value, "P2 is an invalid type.");
static_assert(IsValidParameter<P3>::c_value, "P3 is an invalid type.");
static_assert(IsValidParameter<P4>::c_value, "P4 is an invalid type.");
this->m_functionBase = &m_f;
this->m_functionChild = &m_f;
this->m_children[0] = this->m_functionChild;
this->m_children[1] = &m_p1;
this->m_children[2] = &m_p2;
this->m_children[3] = &m_p3;
this->m_children[4] = &m_p4;
}
}
``` | /content/code_sandbox/inc/NativeJIT/Nodes/CallNode.h | objective-c | 2016-04-09T23:53:19 | 2024-06-29T07:05:56 | NativeJIT | BitFunnel/NativeJIT | 1,133 | 5,668 |
```c++
// Permission is hereby granted, free of charge, to any person obtaining a copy
// of this software and associated documentation files (the "Software"), to deal
// in the Software without restriction, including without limitation the rights
// to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
// copies of the Software, and to permit persons to whom the Software is
// furnished to do so, subject to the following conditions:
// The above copyright notice and this permission notice shall be included in
// all copies or substantial portions of the Software.
// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
// AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
// LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
// OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
// THE SOFTWARE.
#include <cctype> // isxdigit().
#include <iostream>
#include <sstream>
#include <vector>
#include "ML64Verifier.h"
#include "NativeJIT/CodeGen/ExecutionBuffer.h"
#include "NativeJIT/CodeGen/X64CodeGenerator.h"
#include "Temporary/Allocator.h"
#include "TestSetup.h"
namespace NativeJIT
{
namespace CodeGenUnitTest
{
TEST_FIXTURE_START(InstructionEnconding)
public:
InstructionEnconding() : TestFixture(64 * 1024, TestFixture::c_defaultGeneralAllocatorCapacity, TestFixture::c_defaultDiagnosticsStream)
{
}
TEST_FIXTURE_END_TEST_CASES_BEGIN
// Test REX and ModRM bytes by verifying all permutations of src/dest
// registers.
TEST_F(InstructionEnconding, RexAndModRM)
{
auto setup = GetSetup();
auto& buffer = setup->GetCode();
uint8_t const * start = buffer.BufferStart() + buffer.CurrentPosition();
//
// Int <-> int
//
// Source: rax, target: rax
buffer.EmitImmediate<OpCode::Mov>(al, static_cast<uint8_t>(1));
buffer.EmitImmediate<OpCode::Mov>(ax, static_cast<uint16_t>(1));
buffer.EmitImmediate<OpCode::Mov>(eax, 1);
buffer.EmitImmediate<OpCode::Mov>(rax, 1);
buffer.Emit<OpCode::Mov>(al, al);
buffer.Emit<OpCode::Mov>(ax, ax);
buffer.Emit<OpCode::Mov>(eax, eax);
buffer.Emit<OpCode::Mov>(rax, rax);
buffer.Emit<OpCode::Mov>(al, rax, -4);
buffer.Emit<OpCode::Mov>(al, rax, 4);
buffer.Emit<OpCode::Mov>(ax, rax, 4);
buffer.Emit<OpCode::Mov>(eax, rax, 4);
buffer.Emit<OpCode::Mov>(rax, rax, 4);
buffer.Emit<OpCode::Mov>(rax, -4, al);
buffer.Emit<OpCode::Mov>(rax, 4, al);
buffer.Emit<OpCode::Mov>(rax, 4, ax);
buffer.Emit<OpCode::Mov>(rax, 4, eax);
buffer.Emit<OpCode::Mov>(rax, 4, rax);
buffer.Emit<OpCode::MovZX>(ax, al);
buffer.Emit<OpCode::MovZX, 2, false, 1, false>(ax, rax, 4);
buffer.Emit<OpCode::MovZX>(eax, al);
buffer.Emit<OpCode::MovZX>(eax, ax);
buffer.Emit<OpCode::MovZX, 4, false, 1, false>(eax, rax, 4);
buffer.Emit<OpCode::MovZX, 4, false, 2, false>(eax, rax, 4);
buffer.Emit<OpCode::MovZX>(rax, al);
buffer.Emit<OpCode::MovZX>(rax, ax);
buffer.Emit<OpCode::MovZX, 8, false, 1, false>(rax, rax, 4);
buffer.Emit<OpCode::MovZX, 8, false, 2, false>(rax, rax, 4);
// Source: rax, target: rcx
buffer.EmitImmediate<OpCode::Mov>(cl, static_cast<uint8_t>(1));
buffer.EmitImmediate<OpCode::Mov>(cx, static_cast<uint16_t>(1));
buffer.EmitImmediate<OpCode::Mov>(ecx, 1);
buffer.EmitImmediate<OpCode::Mov>(rcx, 1);
buffer.Emit<OpCode::Mov>(cl, al);
buffer.Emit<OpCode::Mov>(cx, ax);
buffer.Emit<OpCode::Mov>(ecx, eax);
buffer.Emit<OpCode::Mov>(rcx, rax);
buffer.Emit<OpCode::Mov>(cl, rax, -4);
buffer.Emit<OpCode::Mov>(cl, rax, 4);
buffer.Emit<OpCode::Mov>(cx, rax, 4);
buffer.Emit<OpCode::Mov>(ecx, rax, 4);
buffer.Emit<OpCode::Mov>(rcx, rax, 4);
buffer.Emit<OpCode::Mov>(rcx, -4, al);
buffer.Emit<OpCode::Mov>(rcx, 4, al);
buffer.Emit<OpCode::Mov>(rcx, 4, ax);
buffer.Emit<OpCode::Mov>(rcx, 4, eax);
buffer.Emit<OpCode::Mov>(rcx, 4, rax);
buffer.Emit<OpCode::MovZX>(cx, al);
buffer.Emit<OpCode::MovZX, 2, false, 1, false>(cx, rax, 4);
buffer.Emit<OpCode::MovZX>(ecx, al);
buffer.Emit<OpCode::MovZX>(ecx, ax);
buffer.Emit<OpCode::MovZX, 4, false, 1, false>(ecx, rax, 4);
buffer.Emit<OpCode::MovZX, 4, false, 2, false>(ecx, rax, 4);
buffer.Emit<OpCode::MovZX>(rcx, al);
buffer.Emit<OpCode::MovZX>(rcx, ax);
buffer.Emit<OpCode::MovZX, 8, false, 1, false>(rcx, rax, 4);
buffer.Emit<OpCode::MovZX, 8, false, 2, false>(rcx, rax, 4);
// Source: rax, target: rdx
buffer.EmitImmediate<OpCode::Mov>(dl, static_cast<uint8_t>(1));
buffer.EmitImmediate<OpCode::Mov>(dx, static_cast<uint16_t>(1));
buffer.EmitImmediate<OpCode::Mov>(edx, 1);
buffer.EmitImmediate<OpCode::Mov>(rdx, 1);
buffer.Emit<OpCode::Mov>(dl, al);
buffer.Emit<OpCode::Mov>(dx, ax);
buffer.Emit<OpCode::Mov>(edx, eax);
buffer.Emit<OpCode::Mov>(rdx, rax);
buffer.Emit<OpCode::Mov>(dl, rax, -4);
buffer.Emit<OpCode::Mov>(dl, rax, 4);
buffer.Emit<OpCode::Mov>(dx, rax, 4);
buffer.Emit<OpCode::Mov>(edx, rax, 4);
buffer.Emit<OpCode::Mov>(rdx, rax, 4);
buffer.Emit<OpCode::Mov>(rdx, -4, al);
buffer.Emit<OpCode::Mov>(rdx, 4, al);
buffer.Emit<OpCode::Mov>(rdx, 4, ax);
buffer.Emit<OpCode::Mov>(rdx, 4, eax);
buffer.Emit<OpCode::Mov>(rdx, 4, rax);
buffer.Emit<OpCode::MovZX>(dx, al);
buffer.Emit<OpCode::MovZX, 2, false, 1, false>(dx, rax, 4);
buffer.Emit<OpCode::MovZX>(edx, al);
buffer.Emit<OpCode::MovZX>(edx, ax);
buffer.Emit<OpCode::MovZX, 4, false, 1, false>(edx, rax, 4);
buffer.Emit<OpCode::MovZX, 4, false, 2, false>(edx, rax, 4);
buffer.Emit<OpCode::MovZX>(rdx, al);
buffer.Emit<OpCode::MovZX>(rdx, ax);
buffer.Emit<OpCode::MovZX, 8, false, 1, false>(rdx, rax, 4);
buffer.Emit<OpCode::MovZX, 8, false, 2, false>(rdx, rax, 4);
// Source: rax, target: rbx
buffer.EmitImmediate<OpCode::Mov>(bl, static_cast<uint8_t>(1));
buffer.EmitImmediate<OpCode::Mov>(bx, static_cast<uint16_t>(1));
buffer.EmitImmediate<OpCode::Mov>(ebx, 1);
buffer.EmitImmediate<OpCode::Mov>(rbx, 1);
buffer.Emit<OpCode::Mov>(bl, al);
buffer.Emit<OpCode::Mov>(bx, ax);
buffer.Emit<OpCode::Mov>(ebx, eax);
buffer.Emit<OpCode::Mov>(rbx, rax);
buffer.Emit<OpCode::Mov>(bl, rax, -4);
buffer.Emit<OpCode::Mov>(bl, rax, 4);
buffer.Emit<OpCode::Mov>(bx, rax, 4);
buffer.Emit<OpCode::Mov>(ebx, rax, 4);
buffer.Emit<OpCode::Mov>(rbx, rax, 4);
buffer.Emit<OpCode::Mov>(rbx, -4, al);
buffer.Emit<OpCode::Mov>(rbx, 4, al);
buffer.Emit<OpCode::Mov>(rbx, 4, ax);
buffer.Emit<OpCode::Mov>(rbx, 4, eax);
buffer.Emit<OpCode::Mov>(rbx, 4, rax);
buffer.Emit<OpCode::MovZX>(bx, al);
buffer.Emit<OpCode::MovZX, 2, false, 1, false>(bx, rax, 4);
buffer.Emit<OpCode::MovZX>(ebx, al);
buffer.Emit<OpCode::MovZX>(ebx, ax);
buffer.Emit<OpCode::MovZX, 4, false, 1, false>(ebx, rax, 4);
buffer.Emit<OpCode::MovZX, 4, false, 2, false>(ebx, rax, 4);
buffer.Emit<OpCode::MovZX>(rbx, al);
buffer.Emit<OpCode::MovZX>(rbx, ax);
buffer.Emit<OpCode::MovZX, 8, false, 1, false>(rbx, rax, 4);
buffer.Emit<OpCode::MovZX, 8, false, 2, false>(rbx, rax, 4);
// Source: rax, target: rsp
buffer.EmitImmediate<OpCode::Mov>(spl, static_cast<uint8_t>(1));
buffer.EmitImmediate<OpCode::Mov>(sp, static_cast<uint16_t>(1));
buffer.EmitImmediate<OpCode::Mov>(esp, 1);
buffer.EmitImmediate<OpCode::Mov>(rsp, 1);
buffer.Emit<OpCode::Mov>(spl, al);
buffer.Emit<OpCode::Mov>(sp, ax);
buffer.Emit<OpCode::Mov>(esp, eax);
buffer.Emit<OpCode::Mov>(rsp, rax);
buffer.Emit<OpCode::Mov>(spl, rax, -4);
buffer.Emit<OpCode::Mov>(spl, rax, 4);
buffer.Emit<OpCode::Mov>(sp, rax, 4);
buffer.Emit<OpCode::Mov>(esp, rax, 4);
buffer.Emit<OpCode::Mov>(rsp, rax, 4);
buffer.Emit<OpCode::Mov>(rsp, -4, al);
buffer.Emit<OpCode::Mov>(rsp, 4, al);
buffer.Emit<OpCode::Mov>(rsp, 4, ax);
buffer.Emit<OpCode::Mov>(rsp, 4, eax);
buffer.Emit<OpCode::Mov>(rsp, 4, rax);
buffer.Emit<OpCode::MovZX>(sp, al);
buffer.Emit<OpCode::MovZX, 2, false, 1, false>(sp, rax, 4);
buffer.Emit<OpCode::MovZX>(esp, al);
buffer.Emit<OpCode::MovZX>(esp, ax);
buffer.Emit<OpCode::MovZX, 4, false, 1, false>(esp, rax, 4);
buffer.Emit<OpCode::MovZX, 4, false, 2, false>(esp, rax, 4);
buffer.Emit<OpCode::MovZX>(rsp, al);
buffer.Emit<OpCode::MovZX>(rsp, ax);
buffer.Emit<OpCode::MovZX, 8, false, 1, false>(rsp, rax, 4);
buffer.Emit<OpCode::MovZX, 8, false, 2, false>(rsp, rax, 4);
// Source: rax, target: rbp
buffer.EmitImmediate<OpCode::Mov>(bpl, static_cast<uint8_t>(1));
buffer.EmitImmediate<OpCode::Mov>(bp, static_cast<uint16_t>(1));
buffer.EmitImmediate<OpCode::Mov>(ebp, 1);
buffer.EmitImmediate<OpCode::Mov>(rbp, 1);
buffer.Emit<OpCode::Mov>(bpl, al);
buffer.Emit<OpCode::Mov>(bp, ax);
buffer.Emit<OpCode::Mov>(ebp, eax);
buffer.Emit<OpCode::Mov>(rbp, rax);
buffer.Emit<OpCode::Mov>(bpl, rax, -4);
buffer.Emit<OpCode::Mov>(bpl, rax, 4);
buffer.Emit<OpCode::Mov>(bp, rax, 4);
buffer.Emit<OpCode::Mov>(ebp, rax, 4);
buffer.Emit<OpCode::Mov>(rbp, rax, 4);
buffer.Emit<OpCode::Mov>(rbp, -4, al);
buffer.Emit<OpCode::Mov>(rbp, 4, al);
buffer.Emit<OpCode::Mov>(rbp, 4, ax);
buffer.Emit<OpCode::Mov>(rbp, 4, eax);
buffer.Emit<OpCode::Mov>(rbp, 4, rax);
buffer.Emit<OpCode::MovZX>(bp, al);
buffer.Emit<OpCode::MovZX, 2, false, 1, false>(bp, rax, 4);
buffer.Emit<OpCode::MovZX>(ebp, al);
buffer.Emit<OpCode::MovZX>(ebp, ax);
buffer.Emit<OpCode::MovZX, 4, false, 1, false>(ebp, rax, 4);
buffer.Emit<OpCode::MovZX, 4, false, 2, false>(ebp, rax, 4);
buffer.Emit<OpCode::MovZX>(rbp, al);
buffer.Emit<OpCode::MovZX>(rbp, ax);
buffer.Emit<OpCode::MovZX, 8, false, 1, false>(rbp, rax, 4);
buffer.Emit<OpCode::MovZX, 8, false, 2, false>(rbp, rax, 4);
// Source: rax, target: rsi
buffer.EmitImmediate<OpCode::Mov>(dil, static_cast<uint8_t>(1));
buffer.EmitImmediate<OpCode::Mov>(si, static_cast<uint16_t>(1));
buffer.EmitImmediate<OpCode::Mov>(esi, 1);
buffer.EmitImmediate<OpCode::Mov>(rsi, 1);
buffer.Emit<OpCode::Mov>(dil, al);
buffer.Emit<OpCode::Mov>(si, ax);
buffer.Emit<OpCode::Mov>(esi, eax);
buffer.Emit<OpCode::Mov>(rsi, rax);
buffer.Emit<OpCode::Mov>(dil, rax, -4);
buffer.Emit<OpCode::Mov>(dil, rax, 4);
buffer.Emit<OpCode::Mov>(si, rax, 4);
buffer.Emit<OpCode::Mov>(esi, rax, 4);
buffer.Emit<OpCode::Mov>(rsi, rax, 4);
buffer.Emit<OpCode::Mov>(rsi, -4, al);
buffer.Emit<OpCode::Mov>(rsi, 4, al);
buffer.Emit<OpCode::Mov>(rsi, 4, ax);
buffer.Emit<OpCode::Mov>(rsi, 4, eax);
buffer.Emit<OpCode::Mov>(rsi, 4, rax);
buffer.Emit<OpCode::MovZX>(si, al);
buffer.Emit<OpCode::MovZX, 2, false, 1, false>(si, rax, 4);
buffer.Emit<OpCode::MovZX>(esi, al);
buffer.Emit<OpCode::MovZX>(esi, ax);
buffer.Emit<OpCode::MovZX, 4, false, 1, false>(esi, rax, 4);
buffer.Emit<OpCode::MovZX, 4, false, 2, false>(esi, rax, 4);
buffer.Emit<OpCode::MovZX>(rsi, al);
buffer.Emit<OpCode::MovZX>(rsi, ax);
buffer.Emit<OpCode::MovZX, 8, false, 1, false>(rsi, rax, 4);
buffer.Emit<OpCode::MovZX, 8, false, 2, false>(rsi, rax, 4);
// Source: rax, target: rdi
buffer.EmitImmediate<OpCode::Mov>(sil, static_cast<uint8_t>(1));
buffer.EmitImmediate<OpCode::Mov>(di, static_cast<uint16_t>(1));
buffer.EmitImmediate<OpCode::Mov>(edi, 1);
buffer.EmitImmediate<OpCode::Mov>(rdi, 1);
buffer.Emit<OpCode::Mov>(sil, al);
buffer.Emit<OpCode::Mov>(di, ax);
buffer.Emit<OpCode::Mov>(edi, eax);
buffer.Emit<OpCode::Mov>(rdi, rax);
buffer.Emit<OpCode::Mov>(sil, rax, -4);
buffer.Emit<OpCode::Mov>(sil, rax, 4);
buffer.Emit<OpCode::Mov>(di, rax, 4);
buffer.Emit<OpCode::Mov>(edi, rax, 4);
buffer.Emit<OpCode::Mov>(rdi, rax, 4);
buffer.Emit<OpCode::Mov>(rdi, -4, al);
buffer.Emit<OpCode::Mov>(rdi, 4, al);
buffer.Emit<OpCode::Mov>(rdi, 4, ax);
buffer.Emit<OpCode::Mov>(rdi, 4, eax);
buffer.Emit<OpCode::Mov>(rdi, 4, rax);
buffer.Emit<OpCode::MovZX>(di, al);
buffer.Emit<OpCode::MovZX, 2, false, 1, false>(di, rax, 4);
buffer.Emit<OpCode::MovZX>(edi, al);
buffer.Emit<OpCode::MovZX>(edi, ax);
buffer.Emit<OpCode::MovZX, 4, false, 1, false>(edi, rax, 4);
buffer.Emit<OpCode::MovZX, 4, false, 2, false>(edi, rax, 4);
buffer.Emit<OpCode::MovZX>(rdi, al);
buffer.Emit<OpCode::MovZX>(rdi, ax);
buffer.Emit<OpCode::MovZX, 8, false, 1, false>(rdi, rax, 4);
buffer.Emit<OpCode::MovZX, 8, false, 2, false>(rdi, rax, 4);
// Source: rax, target: r8
buffer.EmitImmediate<OpCode::Mov>(r8b, static_cast<uint8_t>(1));
buffer.EmitImmediate<OpCode::Mov>(r8w, static_cast<uint16_t>(1));
buffer.EmitImmediate<OpCode::Mov>(r8d, 1);
buffer.EmitImmediate<OpCode::Mov>(r8, 1);
buffer.Emit<OpCode::Mov>(r8b, al);
buffer.Emit<OpCode::Mov>(r8w, ax);
buffer.Emit<OpCode::Mov>(r8d, eax);
buffer.Emit<OpCode::Mov>(r8, rax);
buffer.Emit<OpCode::Mov>(r8b, rax, -4);
buffer.Emit<OpCode::Mov>(r8b, rax, 4);
buffer.Emit<OpCode::Mov>(r8w, rax, 4);
buffer.Emit<OpCode::Mov>(r8d, rax, 4);
buffer.Emit<OpCode::Mov>(r8, rax, 4);
buffer.Emit<OpCode::Mov>(r8, -4, al);
buffer.Emit<OpCode::Mov>(r8, 4, al);
buffer.Emit<OpCode::Mov>(r8, 4, ax);
buffer.Emit<OpCode::Mov>(r8, 4, eax);
buffer.Emit<OpCode::Mov>(r8, 4, rax);
buffer.Emit<OpCode::MovZX>(r8w, al);
buffer.Emit<OpCode::MovZX, 2, false, 1, false>(r8w, rax, 4);
buffer.Emit<OpCode::MovZX>(r8d, al);
buffer.Emit<OpCode::MovZX>(r8d, ax);
buffer.Emit<OpCode::MovZX, 4, false, 1, false>(r8d, rax, 4);
buffer.Emit<OpCode::MovZX, 4, false, 2, false>(r8d, rax, 4);
buffer.Emit<OpCode::MovZX>(r8, al);
buffer.Emit<OpCode::MovZX>(r8, ax);
buffer.Emit<OpCode::MovZX, 8, false, 1, false>(r8, rax, 4);
buffer.Emit<OpCode::MovZX, 8, false, 2, false>(r8, rax, 4);
// Source: rax, target: r9
buffer.EmitImmediate<OpCode::Mov>(r9b, static_cast<uint8_t>(1));
buffer.EmitImmediate<OpCode::Mov>(r9w, static_cast<uint16_t>(1));
buffer.EmitImmediate<OpCode::Mov>(r9d, 1);
buffer.EmitImmediate<OpCode::Mov>(r9, 1);
buffer.Emit<OpCode::Mov>(r9b, al);
buffer.Emit<OpCode::Mov>(r9w, ax);
buffer.Emit<OpCode::Mov>(r9d, eax);
buffer.Emit<OpCode::Mov>(r9, rax);
buffer.Emit<OpCode::Mov>(r9b, rax, -4);
buffer.Emit<OpCode::Mov>(r9b, rax, 4);
buffer.Emit<OpCode::Mov>(r9w, rax, 4);
buffer.Emit<OpCode::Mov>(r9d, rax, 4);
buffer.Emit<OpCode::Mov>(r9, rax, 4);
buffer.Emit<OpCode::Mov>(r9, -4, al);
buffer.Emit<OpCode::Mov>(r9, 4, al);
buffer.Emit<OpCode::Mov>(r9, 4, ax);
buffer.Emit<OpCode::Mov>(r9, 4, eax);
buffer.Emit<OpCode::Mov>(r9, 4, rax);
buffer.Emit<OpCode::MovZX>(r9w, al);
buffer.Emit<OpCode::MovZX, 2, false, 1, false>(r9w, rax, 4);
buffer.Emit<OpCode::MovZX>(r9d, al);
buffer.Emit<OpCode::MovZX>(r9d, ax);
buffer.Emit<OpCode::MovZX, 4, false, 1, false>(r9d, rax, 4);
buffer.Emit<OpCode::MovZX, 4, false, 2, false>(r9d, rax, 4);
buffer.Emit<OpCode::MovZX>(r9, al);
buffer.Emit<OpCode::MovZX>(r9, ax);
buffer.Emit<OpCode::MovZX, 8, false, 1, false>(r9, rax, 4);
buffer.Emit<OpCode::MovZX, 8, false, 2, false>(r9, rax, 4);
// Source: rax, target: r10
buffer.EmitImmediate<OpCode::Mov>(r10b, static_cast<uint8_t>(1));
buffer.EmitImmediate<OpCode::Mov>(r10w, static_cast<uint16_t>(1));
buffer.EmitImmediate<OpCode::Mov>(r10d, 1);
buffer.EmitImmediate<OpCode::Mov>(r10, 1);
buffer.Emit<OpCode::Mov>(r10b, al);
buffer.Emit<OpCode::Mov>(r10w, ax);
buffer.Emit<OpCode::Mov>(r10d, eax);
buffer.Emit<OpCode::Mov>(r10, rax);
buffer.Emit<OpCode::Mov>(r10b, rax, -4);
buffer.Emit<OpCode::Mov>(r10b, rax, 4);
buffer.Emit<OpCode::Mov>(r10w, rax, 4);
buffer.Emit<OpCode::Mov>(r10d, rax, 4);
buffer.Emit<OpCode::Mov>(r10, rax, 4);
buffer.Emit<OpCode::Mov>(r10, -4, al);
buffer.Emit<OpCode::Mov>(r10, 4, al);
buffer.Emit<OpCode::Mov>(r10, 4, ax);
buffer.Emit<OpCode::Mov>(r10, 4, eax);
buffer.Emit<OpCode::Mov>(r10, 4, rax);
buffer.Emit<OpCode::MovZX>(r10w, al);
buffer.Emit<OpCode::MovZX, 2, false, 1, false>(r10w, rax, 4);
buffer.Emit<OpCode::MovZX>(r10d, al);
buffer.Emit<OpCode::MovZX>(r10d, ax);
buffer.Emit<OpCode::MovZX, 4, false, 1, false>(r10d, rax, 4);
buffer.Emit<OpCode::MovZX, 4, false, 2, false>(r10d, rax, 4);
buffer.Emit<OpCode::MovZX>(r10, al);
buffer.Emit<OpCode::MovZX>(r10, ax);
buffer.Emit<OpCode::MovZX, 8, false, 1, false>(r10, rax, 4);
buffer.Emit<OpCode::MovZX, 8, false, 2, false>(r10, rax, 4);
// Source: rax, target: r11
buffer.EmitImmediate<OpCode::Mov>(r11b, static_cast<uint8_t>(1));
buffer.EmitImmediate<OpCode::Mov>(r11w, static_cast<uint16_t>(1));
buffer.EmitImmediate<OpCode::Mov>(r11d, 1);
buffer.EmitImmediate<OpCode::Mov>(r11, 1);
buffer.Emit<OpCode::Mov>(r11b, al);
buffer.Emit<OpCode::Mov>(r11w, ax);
buffer.Emit<OpCode::Mov>(r11d, eax);
buffer.Emit<OpCode::Mov>(r11, rax);
buffer.Emit<OpCode::Mov>(r11b, rax, -4);
buffer.Emit<OpCode::Mov>(r11b, rax, 4);
buffer.Emit<OpCode::Mov>(r11w, rax, 4);
buffer.Emit<OpCode::Mov>(r11d, rax, 4);
buffer.Emit<OpCode::Mov>(r11, rax, 4);
buffer.Emit<OpCode::Mov>(r11, -4, al);
buffer.Emit<OpCode::Mov>(r11, 4, al);
buffer.Emit<OpCode::Mov>(r11, 4, ax);
buffer.Emit<OpCode::Mov>(r11, 4, eax);
buffer.Emit<OpCode::Mov>(r11, 4, rax);
buffer.Emit<OpCode::MovZX>(r11w, al);
buffer.Emit<OpCode::MovZX, 2, false, 1, false>(r11w, rax, 4);
buffer.Emit<OpCode::MovZX>(r11d, al);
buffer.Emit<OpCode::MovZX>(r11d, ax);
buffer.Emit<OpCode::MovZX, 4, false, 1, false>(r11d, rax, 4);
buffer.Emit<OpCode::MovZX, 4, false, 2, false>(r11d, rax, 4);
buffer.Emit<OpCode::MovZX>(r11, al);
buffer.Emit<OpCode::MovZX>(r11, ax);
buffer.Emit<OpCode::MovZX, 8, false, 1, false>(r11, rax, 4);
buffer.Emit<OpCode::MovZX, 8, false, 2, false>(r11, rax, 4);
// Source: rax, target: r12
buffer.EmitImmediate<OpCode::Mov>(r12b, static_cast<uint8_t>(1));
buffer.EmitImmediate<OpCode::Mov>(r12w, static_cast<uint16_t>(1));
buffer.EmitImmediate<OpCode::Mov>(r12d, 1);
buffer.EmitImmediate<OpCode::Mov>(r12, 1);
buffer.Emit<OpCode::Mov>(r12b, al);
buffer.Emit<OpCode::Mov>(r12w, ax);
buffer.Emit<OpCode::Mov>(r12d, eax);
buffer.Emit<OpCode::Mov>(r12, rax);
buffer.Emit<OpCode::Mov>(r12b, rax, -4);
buffer.Emit<OpCode::Mov>(r12b, rax, 4);
buffer.Emit<OpCode::Mov>(r12w, rax, 4);
buffer.Emit<OpCode::Mov>(r12d, rax, 4);
buffer.Emit<OpCode::Mov>(r12, rax, 4);
buffer.Emit<OpCode::Mov>(r12, -4, al);
buffer.Emit<OpCode::Mov>(r12, 4, al);
buffer.Emit<OpCode::Mov>(r12, 4, ax);
buffer.Emit<OpCode::Mov>(r12, 4, eax);
buffer.Emit<OpCode::Mov>(r12, 4, rax);
buffer.Emit<OpCode::MovZX>(r12w, al);
buffer.Emit<OpCode::MovZX, 2, false, 1, false>(r12w, rax, 4);
buffer.Emit<OpCode::MovZX>(r12d, al);
buffer.Emit<OpCode::MovZX>(r12d, ax);
buffer.Emit<OpCode::MovZX, 4, false, 1, false>(r12d, rax, 4);
buffer.Emit<OpCode::MovZX, 4, false, 2, false>(r12d, rax, 4);
buffer.Emit<OpCode::MovZX>(r12, al);
buffer.Emit<OpCode::MovZX>(r12, ax);
buffer.Emit<OpCode::MovZX, 8, false, 1, false>(r12, rax, 4);
buffer.Emit<OpCode::MovZX, 8, false, 2, false>(r12, rax, 4);
// Source: rax, target: r13
buffer.EmitImmediate<OpCode::Mov>(r13b, static_cast<uint8_t>(1));
buffer.EmitImmediate<OpCode::Mov>(r13w, static_cast<uint16_t>(1));
buffer.EmitImmediate<OpCode::Mov>(r13d, 1);
buffer.EmitImmediate<OpCode::Mov>(r13, 1);
buffer.Emit<OpCode::Mov>(r13b, al);
buffer.Emit<OpCode::Mov>(r13w, ax);
buffer.Emit<OpCode::Mov>(r13d, eax);
buffer.Emit<OpCode::Mov>(r13, rax);
buffer.Emit<OpCode::Mov>(r13b, rax, -4);
buffer.Emit<OpCode::Mov>(r13b, rax, 4);
buffer.Emit<OpCode::Mov>(r13w, rax, 4);
buffer.Emit<OpCode::Mov>(r13d, rax, 4);
buffer.Emit<OpCode::Mov>(r13, rax, 4);
buffer.Emit<OpCode::Mov>(r13, -4, al);
buffer.Emit<OpCode::Mov>(r13, 4, al);
buffer.Emit<OpCode::Mov>(r13, 4, ax);
buffer.Emit<OpCode::Mov>(r13, 4, eax);
buffer.Emit<OpCode::Mov>(r13, 4, rax);
buffer.Emit<OpCode::MovZX>(r13w, al);
buffer.Emit<OpCode::MovZX, 2, false, 1, false>(r13w, rax, 4);
buffer.Emit<OpCode::MovZX>(r13d, al);
buffer.Emit<OpCode::MovZX>(r13d, ax);
buffer.Emit<OpCode::MovZX, 4, false, 1, false>(r13d, rax, 4);
buffer.Emit<OpCode::MovZX, 4, false, 2, false>(r13d, rax, 4);
buffer.Emit<OpCode::MovZX>(r13, al);
buffer.Emit<OpCode::MovZX>(r13, ax);
buffer.Emit<OpCode::MovZX, 8, false, 1, false>(r13, rax, 4);
buffer.Emit<OpCode::MovZX, 8, false, 2, false>(r13, rax, 4);
// Source: rax, target: r14
buffer.EmitImmediate<OpCode::Mov>(r14b, static_cast<uint8_t>(1));
buffer.EmitImmediate<OpCode::Mov>(r14w, static_cast<uint16_t>(1));
buffer.EmitImmediate<OpCode::Mov>(r14d, 1);
buffer.EmitImmediate<OpCode::Mov>(r14, 1);
buffer.Emit<OpCode::Mov>(r14b, al);
buffer.Emit<OpCode::Mov>(r14w, ax);
buffer.Emit<OpCode::Mov>(r14d, eax);
buffer.Emit<OpCode::Mov>(r14, rax);
buffer.Emit<OpCode::Mov>(r14b, rax, -4);
buffer.Emit<OpCode::Mov>(r14b, rax, 4);
buffer.Emit<OpCode::Mov>(r14w, rax, 4);
buffer.Emit<OpCode::Mov>(r14d, rax, 4);
buffer.Emit<OpCode::Mov>(r14, rax, 4);
buffer.Emit<OpCode::Mov>(r14, -4, al);
buffer.Emit<OpCode::Mov>(r14, 4, al);
buffer.Emit<OpCode::Mov>(r14, 4, ax);
buffer.Emit<OpCode::Mov>(r14, 4, eax);
buffer.Emit<OpCode::Mov>(r14, 4, rax);
buffer.Emit<OpCode::MovZX>(r14w, al);
buffer.Emit<OpCode::MovZX, 2, false, 1, false>(r14w, rax, 4);
buffer.Emit<OpCode::MovZX>(r14d, al);
buffer.Emit<OpCode::MovZX>(r14d, ax);
buffer.Emit<OpCode::MovZX, 4, false, 1, false>(r14d, rax, 4);
buffer.Emit<OpCode::MovZX, 4, false, 2, false>(r14d, rax, 4);
buffer.Emit<OpCode::MovZX>(r14, al);
buffer.Emit<OpCode::MovZX>(r14, ax);
buffer.Emit<OpCode::MovZX, 8, false, 1, false>(r14, rax, 4);
buffer.Emit<OpCode::MovZX, 8, false, 2, false>(r14, rax, 4);
// Source: rax, target: r15
buffer.EmitImmediate<OpCode::Mov>(r15b, static_cast<uint8_t>(1));
buffer.EmitImmediate<OpCode::Mov>(r15w, static_cast<uint16_t>(1));
buffer.EmitImmediate<OpCode::Mov>(r15d, 1);
buffer.EmitImmediate<OpCode::Mov>(r15, 1);
buffer.Emit<OpCode::Mov>(r15b, al);
buffer.Emit<OpCode::Mov>(r15w, ax);
buffer.Emit<OpCode::Mov>(r15d, eax);
buffer.Emit<OpCode::Mov>(r15, rax);
buffer.Emit<OpCode::Mov>(r15b, rax, -4);
buffer.Emit<OpCode::Mov>(r15b, rax, 4);
buffer.Emit<OpCode::Mov>(r15w, rax, 4);
buffer.Emit<OpCode::Mov>(r15d, rax, 4);
buffer.Emit<OpCode::Mov>(r15, rax, 4);
buffer.Emit<OpCode::Mov>(r15, -4, al);
buffer.Emit<OpCode::Mov>(r15, 4, al);
buffer.Emit<OpCode::Mov>(r15, 4, ax);
buffer.Emit<OpCode::Mov>(r15, 4, eax);
buffer.Emit<OpCode::Mov>(r15, 4, rax);
buffer.Emit<OpCode::MovZX>(r15w, al);
buffer.Emit<OpCode::MovZX, 2, false, 1, false>(r15w, rax, 4);
buffer.Emit<OpCode::MovZX>(r15d, al);
buffer.Emit<OpCode::MovZX>(r15d, ax);
buffer.Emit<OpCode::MovZX, 4, false, 1, false>(r15d, rax, 4);
buffer.Emit<OpCode::MovZX, 4, false, 2, false>(r15d, rax, 4);
buffer.Emit<OpCode::MovZX>(r15, al);
buffer.Emit<OpCode::MovZX>(r15, ax);
buffer.Emit<OpCode::MovZX, 8, false, 1, false>(r15, rax, 4);
buffer.Emit<OpCode::MovZX, 8, false, 2, false>(r15, rax, 4);
// Source: rcx, target: rax
buffer.EmitImmediate<OpCode::Mov>(al, static_cast<uint8_t>(1));
buffer.EmitImmediate<OpCode::Mov>(ax, static_cast<uint16_t>(1));
buffer.EmitImmediate<OpCode::Mov>(eax, 1);
buffer.EmitImmediate<OpCode::Mov>(rax, 1);
buffer.Emit<OpCode::Mov>(al, cl);
buffer.Emit<OpCode::Mov>(ax, cx);
buffer.Emit<OpCode::Mov>(eax, ecx);
buffer.Emit<OpCode::Mov>(rax, rcx);
buffer.Emit<OpCode::Mov>(al, rcx, -4);
buffer.Emit<OpCode::Mov>(al, rcx, 4);
buffer.Emit<OpCode::Mov>(ax, rcx, 4);
buffer.Emit<OpCode::Mov>(eax, rcx, 4);
buffer.Emit<OpCode::Mov>(rax, rcx, 4);
buffer.Emit<OpCode::Mov>(rax, -4, cl);
buffer.Emit<OpCode::Mov>(rax, 4, cl);
buffer.Emit<OpCode::Mov>(rax, 4, cx);
buffer.Emit<OpCode::Mov>(rax, 4, ecx);
buffer.Emit<OpCode::Mov>(rax, 4, rcx);
buffer.Emit<OpCode::MovZX>(ax, cl);
buffer.Emit<OpCode::MovZX, 2, false, 1, false>(ax, rcx, 4);
buffer.Emit<OpCode::MovZX>(eax, cl);
buffer.Emit<OpCode::MovZX>(eax, cx);
buffer.Emit<OpCode::MovZX, 4, false, 1, false>(eax, rcx, 4);
buffer.Emit<OpCode::MovZX, 4, false, 2, false>(eax, rcx, 4);
buffer.Emit<OpCode::MovZX>(rax, cl);
buffer.Emit<OpCode::MovZX>(rax, cx);
buffer.Emit<OpCode::MovZX, 8, false, 1, false>(rax, rcx, 4);
buffer.Emit<OpCode::MovZX, 8, false, 2, false>(rax, rcx, 4);
// Source: rcx, target: rcx
buffer.EmitImmediate<OpCode::Mov>(cl, static_cast<uint8_t>(1));
buffer.EmitImmediate<OpCode::Mov>(cx, static_cast<uint16_t>(1));
buffer.EmitImmediate<OpCode::Mov>(ecx, 1);
buffer.EmitImmediate<OpCode::Mov>(rcx, 1);
buffer.Emit<OpCode::Mov>(cl, cl);
buffer.Emit<OpCode::Mov>(cx, cx);
buffer.Emit<OpCode::Mov>(ecx, ecx);
buffer.Emit<OpCode::Mov>(rcx, rcx);
buffer.Emit<OpCode::Mov>(cl, rcx, -4);
buffer.Emit<OpCode::Mov>(cl, rcx, 4);
buffer.Emit<OpCode::Mov>(cx, rcx, 4);
buffer.Emit<OpCode::Mov>(ecx, rcx, 4);
buffer.Emit<OpCode::Mov>(rcx, rcx, 4);
buffer.Emit<OpCode::Mov>(rcx, -4, cl);
buffer.Emit<OpCode::Mov>(rcx, 4, cl);
buffer.Emit<OpCode::Mov>(rcx, 4, cx);
buffer.Emit<OpCode::Mov>(rcx, 4, ecx);
buffer.Emit<OpCode::Mov>(rcx, 4, rcx);
buffer.Emit<OpCode::MovZX>(cx, cl);
buffer.Emit<OpCode::MovZX, 2, false, 1, false>(cx, rcx, 4);
buffer.Emit<OpCode::MovZX>(ecx, cl);
buffer.Emit<OpCode::MovZX>(ecx, cx);
buffer.Emit<OpCode::MovZX, 4, false, 1, false>(ecx, rcx, 4);
buffer.Emit<OpCode::MovZX, 4, false, 2, false>(ecx, rcx, 4);
buffer.Emit<OpCode::MovZX>(rcx, cl);
buffer.Emit<OpCode::MovZX>(rcx, cx);
buffer.Emit<OpCode::MovZX, 8, false, 1, false>(rcx, rcx, 4);
buffer.Emit<OpCode::MovZX, 8, false, 2, false>(rcx, rcx, 4);
// Source: rcx, target: rdx
buffer.EmitImmediate<OpCode::Mov>(dl, static_cast<uint8_t>(1));
buffer.EmitImmediate<OpCode::Mov>(dx, static_cast<uint16_t>(1));
buffer.EmitImmediate<OpCode::Mov>(edx, 1);
buffer.EmitImmediate<OpCode::Mov>(rdx, 1);
buffer.Emit<OpCode::Mov>(dl, cl);
buffer.Emit<OpCode::Mov>(dx, cx);
buffer.Emit<OpCode::Mov>(edx, ecx);
buffer.Emit<OpCode::Mov>(rdx, rcx);
buffer.Emit<OpCode::Mov>(dl, rcx, -4);
buffer.Emit<OpCode::Mov>(dl, rcx, 4);
buffer.Emit<OpCode::Mov>(dx, rcx, 4);
buffer.Emit<OpCode::Mov>(edx, rcx, 4);
buffer.Emit<OpCode::Mov>(rdx, rcx, 4);
buffer.Emit<OpCode::Mov>(rdx, -4, cl);
buffer.Emit<OpCode::Mov>(rdx, 4, cl);
buffer.Emit<OpCode::Mov>(rdx, 4, cx);
buffer.Emit<OpCode::Mov>(rdx, 4, ecx);
buffer.Emit<OpCode::Mov>(rdx, 4, rcx);
buffer.Emit<OpCode::MovZX>(dx, cl);
buffer.Emit<OpCode::MovZX, 2, false, 1, false>(dx, rcx, 4);
buffer.Emit<OpCode::MovZX>(edx, cl);
buffer.Emit<OpCode::MovZX>(edx, cx);
buffer.Emit<OpCode::MovZX, 4, false, 1, false>(edx, rcx, 4);
buffer.Emit<OpCode::MovZX, 4, false, 2, false>(edx, rcx, 4);
buffer.Emit<OpCode::MovZX>(rdx, cl);
buffer.Emit<OpCode::MovZX>(rdx, cx);
buffer.Emit<OpCode::MovZX, 8, false, 1, false>(rdx, rcx, 4);
buffer.Emit<OpCode::MovZX, 8, false, 2, false>(rdx, rcx, 4);
// Source: rcx, target: rbx
buffer.EmitImmediate<OpCode::Mov>(bl, static_cast<uint8_t>(1));
buffer.EmitImmediate<OpCode::Mov>(bx, static_cast<uint16_t>(1));
buffer.EmitImmediate<OpCode::Mov>(ebx, 1);
buffer.EmitImmediate<OpCode::Mov>(rbx, 1);
buffer.Emit<OpCode::Mov>(bl, cl);
buffer.Emit<OpCode::Mov>(bx, cx);
buffer.Emit<OpCode::Mov>(ebx, ecx);
buffer.Emit<OpCode::Mov>(rbx, rcx);
buffer.Emit<OpCode::Mov>(bl, rcx, -4);
buffer.Emit<OpCode::Mov>(bl, rcx, 4);
buffer.Emit<OpCode::Mov>(bx, rcx, 4);
buffer.Emit<OpCode::Mov>(ebx, rcx, 4);
buffer.Emit<OpCode::Mov>(rbx, rcx, 4);
buffer.Emit<OpCode::Mov>(rbx, -4, cl);
buffer.Emit<OpCode::Mov>(rbx, 4, cl);
buffer.Emit<OpCode::Mov>(rbx, 4, cx);
buffer.Emit<OpCode::Mov>(rbx, 4, ecx);
buffer.Emit<OpCode::Mov>(rbx, 4, rcx);
buffer.Emit<OpCode::MovZX>(bx, cl);
buffer.Emit<OpCode::MovZX, 2, false, 1, false>(bx, rcx, 4);
buffer.Emit<OpCode::MovZX>(ebx, cl);
buffer.Emit<OpCode::MovZX>(ebx, cx);
buffer.Emit<OpCode::MovZX, 4, false, 1, false>(ebx, rcx, 4);
buffer.Emit<OpCode::MovZX, 4, false, 2, false>(ebx, rcx, 4);
buffer.Emit<OpCode::MovZX>(rbx, cl);
buffer.Emit<OpCode::MovZX>(rbx, cx);
buffer.Emit<OpCode::MovZX, 8, false, 1, false>(rbx, rcx, 4);
buffer.Emit<OpCode::MovZX, 8, false, 2, false>(rbx, rcx, 4);
// Source: rcx, target: rsp
buffer.EmitImmediate<OpCode::Mov>(spl, static_cast<uint8_t>(1));
buffer.EmitImmediate<OpCode::Mov>(sp, static_cast<uint16_t>(1));
buffer.EmitImmediate<OpCode::Mov>(esp, 1);
buffer.EmitImmediate<OpCode::Mov>(rsp, 1);
buffer.Emit<OpCode::Mov>(spl, cl);
buffer.Emit<OpCode::Mov>(sp, cx);
buffer.Emit<OpCode::Mov>(esp, ecx);
buffer.Emit<OpCode::Mov>(rsp, rcx);
buffer.Emit<OpCode::Mov>(spl, rcx, -4);
buffer.Emit<OpCode::Mov>(spl, rcx, 4);
buffer.Emit<OpCode::Mov>(sp, rcx, 4);
buffer.Emit<OpCode::Mov>(esp, rcx, 4);
buffer.Emit<OpCode::Mov>(rsp, rcx, 4);
buffer.Emit<OpCode::Mov>(rsp, -4, cl);
buffer.Emit<OpCode::Mov>(rsp, 4, cl);
buffer.Emit<OpCode::Mov>(rsp, 4, cx);
buffer.Emit<OpCode::Mov>(rsp, 4, ecx);
buffer.Emit<OpCode::Mov>(rsp, 4, rcx);
buffer.Emit<OpCode::MovZX>(sp, cl);
buffer.Emit<OpCode::MovZX, 2, false, 1, false>(sp, rcx, 4);
buffer.Emit<OpCode::MovZX>(esp, cl);
buffer.Emit<OpCode::MovZX>(esp, cx);
buffer.Emit<OpCode::MovZX, 4, false, 1, false>(esp, rcx, 4);
buffer.Emit<OpCode::MovZX, 4, false, 2, false>(esp, rcx, 4);
buffer.Emit<OpCode::MovZX>(rsp, cl);
buffer.Emit<OpCode::MovZX>(rsp, cx);
buffer.Emit<OpCode::MovZX, 8, false, 1, false>(rsp, rcx, 4);
buffer.Emit<OpCode::MovZX, 8, false, 2, false>(rsp, rcx, 4);
// Source: rcx, target: rbp
buffer.EmitImmediate<OpCode::Mov>(bpl, static_cast<uint8_t>(1));
buffer.EmitImmediate<OpCode::Mov>(bp, static_cast<uint16_t>(1));
buffer.EmitImmediate<OpCode::Mov>(ebp, 1);
buffer.EmitImmediate<OpCode::Mov>(rbp, 1);
buffer.Emit<OpCode::Mov>(bpl, cl);
buffer.Emit<OpCode::Mov>(bp, cx);
buffer.Emit<OpCode::Mov>(ebp, ecx);
buffer.Emit<OpCode::Mov>(rbp, rcx);
buffer.Emit<OpCode::Mov>(bpl, rcx, -4);
buffer.Emit<OpCode::Mov>(bpl, rcx, 4);
buffer.Emit<OpCode::Mov>(bp, rcx, 4);
buffer.Emit<OpCode::Mov>(ebp, rcx, 4);
buffer.Emit<OpCode::Mov>(rbp, rcx, 4);
buffer.Emit<OpCode::Mov>(rbp, -4, cl);
buffer.Emit<OpCode::Mov>(rbp, 4, cl);
buffer.Emit<OpCode::Mov>(rbp, 4, cx);
buffer.Emit<OpCode::Mov>(rbp, 4, ecx);
buffer.Emit<OpCode::Mov>(rbp, 4, rcx);
buffer.Emit<OpCode::MovZX>(bp, cl);
buffer.Emit<OpCode::MovZX, 2, false, 1, false>(bp, rcx, 4);
buffer.Emit<OpCode::MovZX>(ebp, cl);
buffer.Emit<OpCode::MovZX>(ebp, cx);
buffer.Emit<OpCode::MovZX, 4, false, 1, false>(ebp, rcx, 4);
buffer.Emit<OpCode::MovZX, 4, false, 2, false>(ebp, rcx, 4);
buffer.Emit<OpCode::MovZX>(rbp, cl);
buffer.Emit<OpCode::MovZX>(rbp, cx);
buffer.Emit<OpCode::MovZX, 8, false, 1, false>(rbp, rcx, 4);
buffer.Emit<OpCode::MovZX, 8, false, 2, false>(rbp, rcx, 4);
// Source: rcx, target: rsi
buffer.EmitImmediate<OpCode::Mov>(dil, static_cast<uint8_t>(1));
buffer.EmitImmediate<OpCode::Mov>(si, static_cast<uint16_t>(1));
buffer.EmitImmediate<OpCode::Mov>(esi, 1);
buffer.EmitImmediate<OpCode::Mov>(rsi, 1);
buffer.Emit<OpCode::Mov>(dil, cl);
buffer.Emit<OpCode::Mov>(si, cx);
buffer.Emit<OpCode::Mov>(esi, ecx);
buffer.Emit<OpCode::Mov>(rsi, rcx);
buffer.Emit<OpCode::Mov>(dil, rcx, -4);
buffer.Emit<OpCode::Mov>(dil, rcx, 4);
buffer.Emit<OpCode::Mov>(si, rcx, 4);
buffer.Emit<OpCode::Mov>(esi, rcx, 4);
buffer.Emit<OpCode::Mov>(rsi, rcx, 4);
buffer.Emit<OpCode::Mov>(rsi, -4, cl);
buffer.Emit<OpCode::Mov>(rsi, 4, cl);
buffer.Emit<OpCode::Mov>(rsi, 4, cx);
buffer.Emit<OpCode::Mov>(rsi, 4, ecx);
buffer.Emit<OpCode::Mov>(rsi, 4, rcx);
buffer.Emit<OpCode::MovZX>(si, cl);
buffer.Emit<OpCode::MovZX, 2, false, 1, false>(si, rcx, 4);
buffer.Emit<OpCode::MovZX>(esi, cl);
buffer.Emit<OpCode::MovZX>(esi, cx);
buffer.Emit<OpCode::MovZX, 4, false, 1, false>(esi, rcx, 4);
buffer.Emit<OpCode::MovZX, 4, false, 2, false>(esi, rcx, 4);
buffer.Emit<OpCode::MovZX>(rsi, cl);
buffer.Emit<OpCode::MovZX>(rsi, cx);
buffer.Emit<OpCode::MovZX, 8, false, 1, false>(rsi, rcx, 4);
buffer.Emit<OpCode::MovZX, 8, false, 2, false>(rsi, rcx, 4);
// Source: rcx, target: rdi
buffer.EmitImmediate<OpCode::Mov>(sil, static_cast<uint8_t>(1));
buffer.EmitImmediate<OpCode::Mov>(di, static_cast<uint16_t>(1));
buffer.EmitImmediate<OpCode::Mov>(edi, 1);
buffer.EmitImmediate<OpCode::Mov>(rdi, 1);
buffer.Emit<OpCode::Mov>(sil, cl);
buffer.Emit<OpCode::Mov>(di, cx);
buffer.Emit<OpCode::Mov>(edi, ecx);
buffer.Emit<OpCode::Mov>(rdi, rcx);
buffer.Emit<OpCode::Mov>(sil, rcx, -4);
buffer.Emit<OpCode::Mov>(sil, rcx, 4);
buffer.Emit<OpCode::Mov>(di, rcx, 4);
buffer.Emit<OpCode::Mov>(edi, rcx, 4);
buffer.Emit<OpCode::Mov>(rdi, rcx, 4);
buffer.Emit<OpCode::Mov>(rdi, -4, cl);
buffer.Emit<OpCode::Mov>(rdi, 4, cl);
buffer.Emit<OpCode::Mov>(rdi, 4, cx);
buffer.Emit<OpCode::Mov>(rdi, 4, ecx);
buffer.Emit<OpCode::Mov>(rdi, 4, rcx);
buffer.Emit<OpCode::MovZX>(di, cl);
buffer.Emit<OpCode::MovZX, 2, false, 1, false>(di, rcx, 4);
buffer.Emit<OpCode::MovZX>(edi, cl);
buffer.Emit<OpCode::MovZX>(edi, cx);
buffer.Emit<OpCode::MovZX, 4, false, 1, false>(edi, rcx, 4);
buffer.Emit<OpCode::MovZX, 4, false, 2, false>(edi, rcx, 4);
buffer.Emit<OpCode::MovZX>(rdi, cl);
buffer.Emit<OpCode::MovZX>(rdi, cx);
buffer.Emit<OpCode::MovZX, 8, false, 1, false>(rdi, rcx, 4);
buffer.Emit<OpCode::MovZX, 8, false, 2, false>(rdi, rcx, 4);
// Source: rcx, target: r8
buffer.EmitImmediate<OpCode::Mov>(r8b, static_cast<uint8_t>(1));
buffer.EmitImmediate<OpCode::Mov>(r8w, static_cast<uint16_t>(1));
buffer.EmitImmediate<OpCode::Mov>(r8d, 1);
buffer.EmitImmediate<OpCode::Mov>(r8, 1);
buffer.Emit<OpCode::Mov>(r8b, cl);
buffer.Emit<OpCode::Mov>(r8w, cx);
buffer.Emit<OpCode::Mov>(r8d, ecx);
buffer.Emit<OpCode::Mov>(r8, rcx);
buffer.Emit<OpCode::Mov>(r8b, rcx, -4);
buffer.Emit<OpCode::Mov>(r8b, rcx, 4);
buffer.Emit<OpCode::Mov>(r8w, rcx, 4);
buffer.Emit<OpCode::Mov>(r8d, rcx, 4);
buffer.Emit<OpCode::Mov>(r8, rcx, 4);
buffer.Emit<OpCode::Mov>(r8, -4, cl);
buffer.Emit<OpCode::Mov>(r8, 4, cl);
buffer.Emit<OpCode::Mov>(r8, 4, cx);
buffer.Emit<OpCode::Mov>(r8, 4, ecx);
buffer.Emit<OpCode::Mov>(r8, 4, rcx);
buffer.Emit<OpCode::MovZX>(r8w, cl);
buffer.Emit<OpCode::MovZX, 2, false, 1, false>(r8w, rcx, 4);
buffer.Emit<OpCode::MovZX>(r8d, cl);
buffer.Emit<OpCode::MovZX>(r8d, cx);
buffer.Emit<OpCode::MovZX, 4, false, 1, false>(r8d, rcx, 4);
buffer.Emit<OpCode::MovZX, 4, false, 2, false>(r8d, rcx, 4);
buffer.Emit<OpCode::MovZX>(r8, cl);
buffer.Emit<OpCode::MovZX>(r8, cx);
buffer.Emit<OpCode::MovZX, 8, false, 1, false>(r8, rcx, 4);
buffer.Emit<OpCode::MovZX, 8, false, 2, false>(r8, rcx, 4);
// Source: rcx, target: r9
buffer.EmitImmediate<OpCode::Mov>(r9b, static_cast<uint8_t>(1));
buffer.EmitImmediate<OpCode::Mov>(r9w, static_cast<uint16_t>(1));
buffer.EmitImmediate<OpCode::Mov>(r9d, 1);
buffer.EmitImmediate<OpCode::Mov>(r9, 1);
buffer.Emit<OpCode::Mov>(r9b, cl);
buffer.Emit<OpCode::Mov>(r9w, cx);
buffer.Emit<OpCode::Mov>(r9d, ecx);
buffer.Emit<OpCode::Mov>(r9, rcx);
buffer.Emit<OpCode::Mov>(r9b, rcx, -4);
buffer.Emit<OpCode::Mov>(r9b, rcx, 4);
buffer.Emit<OpCode::Mov>(r9w, rcx, 4);
buffer.Emit<OpCode::Mov>(r9d, rcx, 4);
buffer.Emit<OpCode::Mov>(r9, rcx, 4);
buffer.Emit<OpCode::Mov>(r9, -4, cl);
buffer.Emit<OpCode::Mov>(r9, 4, cl);
buffer.Emit<OpCode::Mov>(r9, 4, cx);
buffer.Emit<OpCode::Mov>(r9, 4, ecx);
buffer.Emit<OpCode::Mov>(r9, 4, rcx);
buffer.Emit<OpCode::MovZX>(r9w, cl);
buffer.Emit<OpCode::MovZX, 2, false, 1, false>(r9w, rcx, 4);
buffer.Emit<OpCode::MovZX>(r9d, cl);
buffer.Emit<OpCode::MovZX>(r9d, cx);
buffer.Emit<OpCode::MovZX, 4, false, 1, false>(r9d, rcx, 4);
buffer.Emit<OpCode::MovZX, 4, false, 2, false>(r9d, rcx, 4);
buffer.Emit<OpCode::MovZX>(r9, cl);
buffer.Emit<OpCode::MovZX>(r9, cx);
buffer.Emit<OpCode::MovZX, 8, false, 1, false>(r9, rcx, 4);
buffer.Emit<OpCode::MovZX, 8, false, 2, false>(r9, rcx, 4);
// Source: rcx, target: r10
buffer.EmitImmediate<OpCode::Mov>(r10b, static_cast<uint8_t>(1));
buffer.EmitImmediate<OpCode::Mov>(r10w, static_cast<uint16_t>(1));
buffer.EmitImmediate<OpCode::Mov>(r10d, 1);
buffer.EmitImmediate<OpCode::Mov>(r10, 1);
buffer.Emit<OpCode::Mov>(r10b, cl);
buffer.Emit<OpCode::Mov>(r10w, cx);
buffer.Emit<OpCode::Mov>(r10d, ecx);
buffer.Emit<OpCode::Mov>(r10, rcx);
buffer.Emit<OpCode::Mov>(r10b, rcx, -4);
buffer.Emit<OpCode::Mov>(r10b, rcx, 4);
buffer.Emit<OpCode::Mov>(r10w, rcx, 4);
buffer.Emit<OpCode::Mov>(r10d, rcx, 4);
buffer.Emit<OpCode::Mov>(r10, rcx, 4);
buffer.Emit<OpCode::Mov>(r10, -4, cl);
buffer.Emit<OpCode::Mov>(r10, 4, cl);
buffer.Emit<OpCode::Mov>(r10, 4, cx);
buffer.Emit<OpCode::Mov>(r10, 4, ecx);
buffer.Emit<OpCode::Mov>(r10, 4, rcx);
buffer.Emit<OpCode::MovZX>(r10w, cl);
buffer.Emit<OpCode::MovZX, 2, false, 1, false>(r10w, rcx, 4);
buffer.Emit<OpCode::MovZX>(r10d, cl);
buffer.Emit<OpCode::MovZX>(r10d, cx);
buffer.Emit<OpCode::MovZX, 4, false, 1, false>(r10d, rcx, 4);
buffer.Emit<OpCode::MovZX, 4, false, 2, false>(r10d, rcx, 4);
buffer.Emit<OpCode::MovZX>(r10, cl);
buffer.Emit<OpCode::MovZX>(r10, cx);
buffer.Emit<OpCode::MovZX, 8, false, 1, false>(r10, rcx, 4);
buffer.Emit<OpCode::MovZX, 8, false, 2, false>(r10, rcx, 4);
// Source: rcx, target: r11
buffer.EmitImmediate<OpCode::Mov>(r11b, static_cast<uint8_t>(1));
buffer.EmitImmediate<OpCode::Mov>(r11w, static_cast<uint16_t>(1));
buffer.EmitImmediate<OpCode::Mov>(r11d, 1);
buffer.EmitImmediate<OpCode::Mov>(r11, 1);
buffer.Emit<OpCode::Mov>(r11b, cl);
buffer.Emit<OpCode::Mov>(r11w, cx);
buffer.Emit<OpCode::Mov>(r11d, ecx);
buffer.Emit<OpCode::Mov>(r11, rcx);
buffer.Emit<OpCode::Mov>(r11b, rcx, -4);
buffer.Emit<OpCode::Mov>(r11b, rcx, 4);
buffer.Emit<OpCode::Mov>(r11w, rcx, 4);
buffer.Emit<OpCode::Mov>(r11d, rcx, 4);
buffer.Emit<OpCode::Mov>(r11, rcx, 4);
buffer.Emit<OpCode::Mov>(r11, -4, cl);
buffer.Emit<OpCode::Mov>(r11, 4, cl);
buffer.Emit<OpCode::Mov>(r11, 4, cx);
buffer.Emit<OpCode::Mov>(r11, 4, ecx);
buffer.Emit<OpCode::Mov>(r11, 4, rcx);
buffer.Emit<OpCode::MovZX>(r11w, cl);
buffer.Emit<OpCode::MovZX, 2, false, 1, false>(r11w, rcx, 4);
buffer.Emit<OpCode::MovZX>(r11d, cl);
buffer.Emit<OpCode::MovZX>(r11d, cx);
buffer.Emit<OpCode::MovZX, 4, false, 1, false>(r11d, rcx, 4);
buffer.Emit<OpCode::MovZX, 4, false, 2, false>(r11d, rcx, 4);
buffer.Emit<OpCode::MovZX>(r11, cl);
buffer.Emit<OpCode::MovZX>(r11, cx);
buffer.Emit<OpCode::MovZX, 8, false, 1, false>(r11, rcx, 4);
buffer.Emit<OpCode::MovZX, 8, false, 2, false>(r11, rcx, 4);
// Source: rcx, target: r12
buffer.EmitImmediate<OpCode::Mov>(r12b, static_cast<uint8_t>(1));
buffer.EmitImmediate<OpCode::Mov>(r12w, static_cast<uint16_t>(1));
buffer.EmitImmediate<OpCode::Mov>(r12d, 1);
buffer.EmitImmediate<OpCode::Mov>(r12, 1);
buffer.Emit<OpCode::Mov>(r12b, cl);
buffer.Emit<OpCode::Mov>(r12w, cx);
buffer.Emit<OpCode::Mov>(r12d, ecx);
buffer.Emit<OpCode::Mov>(r12, rcx);
buffer.Emit<OpCode::Mov>(r12b, rcx, -4);
buffer.Emit<OpCode::Mov>(r12b, rcx, 4);
buffer.Emit<OpCode::Mov>(r12w, rcx, 4);
buffer.Emit<OpCode::Mov>(r12d, rcx, 4);
buffer.Emit<OpCode::Mov>(r12, rcx, 4);
buffer.Emit<OpCode::Mov>(r12, -4, cl);
buffer.Emit<OpCode::Mov>(r12, 4, cl);
buffer.Emit<OpCode::Mov>(r12, 4, cx);
buffer.Emit<OpCode::Mov>(r12, 4, ecx);
buffer.Emit<OpCode::Mov>(r12, 4, rcx);
buffer.Emit<OpCode::MovZX>(r12w, cl);
buffer.Emit<OpCode::MovZX, 2, false, 1, false>(r12w, rcx, 4);
buffer.Emit<OpCode::MovZX>(r12d, cl);
buffer.Emit<OpCode::MovZX>(r12d, cx);
buffer.Emit<OpCode::MovZX, 4, false, 1, false>(r12d, rcx, 4);
buffer.Emit<OpCode::MovZX, 4, false, 2, false>(r12d, rcx, 4);
buffer.Emit<OpCode::MovZX>(r12, cl);
buffer.Emit<OpCode::MovZX>(r12, cx);
buffer.Emit<OpCode::MovZX, 8, false, 1, false>(r12, rcx, 4);
buffer.Emit<OpCode::MovZX, 8, false, 2, false>(r12, rcx, 4);
// Source: rcx, target: r13
buffer.EmitImmediate<OpCode::Mov>(r13b, static_cast<uint8_t>(1));
buffer.EmitImmediate<OpCode::Mov>(r13w, static_cast<uint16_t>(1));
buffer.EmitImmediate<OpCode::Mov>(r13d, 1);
buffer.EmitImmediate<OpCode::Mov>(r13, 1);
buffer.Emit<OpCode::Mov>(r13b, cl);
buffer.Emit<OpCode::Mov>(r13w, cx);
buffer.Emit<OpCode::Mov>(r13d, ecx);
buffer.Emit<OpCode::Mov>(r13, rcx);
buffer.Emit<OpCode::Mov>(r13b, rcx, -4);
buffer.Emit<OpCode::Mov>(r13b, rcx, 4);
buffer.Emit<OpCode::Mov>(r13w, rcx, 4);
buffer.Emit<OpCode::Mov>(r13d, rcx, 4);
buffer.Emit<OpCode::Mov>(r13, rcx, 4);
buffer.Emit<OpCode::Mov>(r13, -4, cl);
buffer.Emit<OpCode::Mov>(r13, 4, cl);
buffer.Emit<OpCode::Mov>(r13, 4, cx);
buffer.Emit<OpCode::Mov>(r13, 4, ecx);
buffer.Emit<OpCode::Mov>(r13, 4, rcx);
buffer.Emit<OpCode::MovZX>(r13w, cl);
buffer.Emit<OpCode::MovZX, 2, false, 1, false>(r13w, rcx, 4);
buffer.Emit<OpCode::MovZX>(r13d, cl);
buffer.Emit<OpCode::MovZX>(r13d, cx);
buffer.Emit<OpCode::MovZX, 4, false, 1, false>(r13d, rcx, 4);
buffer.Emit<OpCode::MovZX, 4, false, 2, false>(r13d, rcx, 4);
buffer.Emit<OpCode::MovZX>(r13, cl);
buffer.Emit<OpCode::MovZX>(r13, cx);
buffer.Emit<OpCode::MovZX, 8, false, 1, false>(r13, rcx, 4);
buffer.Emit<OpCode::MovZX, 8, false, 2, false>(r13, rcx, 4);
// Source: rcx, target: r14
buffer.EmitImmediate<OpCode::Mov>(r14b, static_cast<uint8_t>(1));
buffer.EmitImmediate<OpCode::Mov>(r14w, static_cast<uint16_t>(1));
buffer.EmitImmediate<OpCode::Mov>(r14d, 1);
buffer.EmitImmediate<OpCode::Mov>(r14, 1);
buffer.Emit<OpCode::Mov>(r14b, cl);
buffer.Emit<OpCode::Mov>(r14w, cx);
buffer.Emit<OpCode::Mov>(r14d, ecx);
buffer.Emit<OpCode::Mov>(r14, rcx);
buffer.Emit<OpCode::Mov>(r14b, rcx, -4);
buffer.Emit<OpCode::Mov>(r14b, rcx, 4);
buffer.Emit<OpCode::Mov>(r14w, rcx, 4);
buffer.Emit<OpCode::Mov>(r14d, rcx, 4);
buffer.Emit<OpCode::Mov>(r14, rcx, 4);
buffer.Emit<OpCode::Mov>(r14, -4, cl);
buffer.Emit<OpCode::Mov>(r14, 4, cl);
buffer.Emit<OpCode::Mov>(r14, 4, cx);
buffer.Emit<OpCode::Mov>(r14, 4, ecx);
buffer.Emit<OpCode::Mov>(r14, 4, rcx);
buffer.Emit<OpCode::MovZX>(r14w, cl);
buffer.Emit<OpCode::MovZX, 2, false, 1, false>(r14w, rcx, 4);
buffer.Emit<OpCode::MovZX>(r14d, cl);
buffer.Emit<OpCode::MovZX>(r14d, cx);
buffer.Emit<OpCode::MovZX, 4, false, 1, false>(r14d, rcx, 4);
buffer.Emit<OpCode::MovZX, 4, false, 2, false>(r14d, rcx, 4);
buffer.Emit<OpCode::MovZX>(r14, cl);
buffer.Emit<OpCode::MovZX>(r14, cx);
buffer.Emit<OpCode::MovZX, 8, false, 1, false>(r14, rcx, 4);
buffer.Emit<OpCode::MovZX, 8, false, 2, false>(r14, rcx, 4);
// Source: rcx, target: r15
buffer.EmitImmediate<OpCode::Mov>(r15b, static_cast<uint8_t>(1));
buffer.EmitImmediate<OpCode::Mov>(r15w, static_cast<uint16_t>(1));
buffer.EmitImmediate<OpCode::Mov>(r15d, 1);
buffer.EmitImmediate<OpCode::Mov>(r15, 1);
buffer.Emit<OpCode::Mov>(r15b, cl);
buffer.Emit<OpCode::Mov>(r15w, cx);
buffer.Emit<OpCode::Mov>(r15d, ecx);
buffer.Emit<OpCode::Mov>(r15, rcx);
buffer.Emit<OpCode::Mov>(r15b, rcx, -4);
buffer.Emit<OpCode::Mov>(r15b, rcx, 4);
buffer.Emit<OpCode::Mov>(r15w, rcx, 4);
buffer.Emit<OpCode::Mov>(r15d, rcx, 4);
buffer.Emit<OpCode::Mov>(r15, rcx, 4);
buffer.Emit<OpCode::Mov>(r15, -4, cl);
buffer.Emit<OpCode::Mov>(r15, 4, cl);
buffer.Emit<OpCode::Mov>(r15, 4, cx);
buffer.Emit<OpCode::Mov>(r15, 4, ecx);
buffer.Emit<OpCode::Mov>(r15, 4, rcx);
buffer.Emit<OpCode::MovZX>(r15w, cl);
buffer.Emit<OpCode::MovZX, 2, false, 1, false>(r15w, rcx, 4);
buffer.Emit<OpCode::MovZX>(r15d, cl);
buffer.Emit<OpCode::MovZX>(r15d, cx);
buffer.Emit<OpCode::MovZX, 4, false, 1, false>(r15d, rcx, 4);
buffer.Emit<OpCode::MovZX, 4, false, 2, false>(r15d, rcx, 4);
buffer.Emit<OpCode::MovZX>(r15, cl);
buffer.Emit<OpCode::MovZX>(r15, cx);
buffer.Emit<OpCode::MovZX, 8, false, 1, false>(r15, rcx, 4);
buffer.Emit<OpCode::MovZX, 8, false, 2, false>(r15, rcx, 4);
// Source: rdx, target: rax
buffer.EmitImmediate<OpCode::Mov>(al, static_cast<uint8_t>(1));
buffer.EmitImmediate<OpCode::Mov>(ax, static_cast<uint16_t>(1));
buffer.EmitImmediate<OpCode::Mov>(eax, 1);
buffer.EmitImmediate<OpCode::Mov>(rax, 1);
buffer.Emit<OpCode::Mov>(al, dl);
buffer.Emit<OpCode::Mov>(ax, dx);
buffer.Emit<OpCode::Mov>(eax, edx);
buffer.Emit<OpCode::Mov>(rax, rdx);
buffer.Emit<OpCode::Mov>(al, rdx, -4);
buffer.Emit<OpCode::Mov>(al, rdx, 4);
buffer.Emit<OpCode::Mov>(ax, rdx, 4);
buffer.Emit<OpCode::Mov>(eax, rdx, 4);
buffer.Emit<OpCode::Mov>(rax, rdx, 4);
buffer.Emit<OpCode::Mov>(rax, -4, dl);
buffer.Emit<OpCode::Mov>(rax, 4, dl);
buffer.Emit<OpCode::Mov>(rax, 4, dx);
buffer.Emit<OpCode::Mov>(rax, 4, edx);
buffer.Emit<OpCode::Mov>(rax, 4, rdx);
buffer.Emit<OpCode::MovZX>(ax, dl);
buffer.Emit<OpCode::MovZX, 2, false, 1, false>(ax, rdx, 4);
buffer.Emit<OpCode::MovZX>(eax, dl);
buffer.Emit<OpCode::MovZX>(eax, dx);
buffer.Emit<OpCode::MovZX, 4, false, 1, false>(eax, rdx, 4);
buffer.Emit<OpCode::MovZX, 4, false, 2, false>(eax, rdx, 4);
buffer.Emit<OpCode::MovZX>(rax, dl);
buffer.Emit<OpCode::MovZX>(rax, dx);
buffer.Emit<OpCode::MovZX, 8, false, 1, false>(rax, rdx, 4);
buffer.Emit<OpCode::MovZX, 8, false, 2, false>(rax, rdx, 4);
// Source: rdx, target: rcx
buffer.EmitImmediate<OpCode::Mov>(cl, static_cast<uint8_t>(1));
buffer.EmitImmediate<OpCode::Mov>(cx, static_cast<uint16_t>(1));
buffer.EmitImmediate<OpCode::Mov>(ecx, 1);
buffer.EmitImmediate<OpCode::Mov>(rcx, 1);
buffer.Emit<OpCode::Mov>(cl, dl);
buffer.Emit<OpCode::Mov>(cx, dx);
buffer.Emit<OpCode::Mov>(ecx, edx);
buffer.Emit<OpCode::Mov>(rcx, rdx);
buffer.Emit<OpCode::Mov>(cl, rdx, -4);
buffer.Emit<OpCode::Mov>(cl, rdx, 4);
buffer.Emit<OpCode::Mov>(cx, rdx, 4);
buffer.Emit<OpCode::Mov>(ecx, rdx, 4);
buffer.Emit<OpCode::Mov>(rcx, rdx, 4);
buffer.Emit<OpCode::Mov>(rcx, -4, dl);
buffer.Emit<OpCode::Mov>(rcx, 4, dl);
buffer.Emit<OpCode::Mov>(rcx, 4, dx);
buffer.Emit<OpCode::Mov>(rcx, 4, edx);
buffer.Emit<OpCode::Mov>(rcx, 4, rdx);
buffer.Emit<OpCode::MovZX>(cx, dl);
buffer.Emit<OpCode::MovZX, 2, false, 1, false>(cx, rdx, 4);
buffer.Emit<OpCode::MovZX>(ecx, dl);
buffer.Emit<OpCode::MovZX>(ecx, dx);
buffer.Emit<OpCode::MovZX, 4, false, 1, false>(ecx, rdx, 4);
buffer.Emit<OpCode::MovZX, 4, false, 2, false>(ecx, rdx, 4);
buffer.Emit<OpCode::MovZX>(rcx, dl);
buffer.Emit<OpCode::MovZX>(rcx, dx);
buffer.Emit<OpCode::MovZX, 8, false, 1, false>(rcx, rdx, 4);
buffer.Emit<OpCode::MovZX, 8, false, 2, false>(rcx, rdx, 4);
// Source: rdx, target: rdx
buffer.EmitImmediate<OpCode::Mov>(dl, static_cast<uint8_t>(1));
buffer.EmitImmediate<OpCode::Mov>(dx, static_cast<uint16_t>(1));
buffer.EmitImmediate<OpCode::Mov>(edx, 1);
buffer.EmitImmediate<OpCode::Mov>(rdx, 1);
buffer.Emit<OpCode::Mov>(dl, dl);
buffer.Emit<OpCode::Mov>(dx, dx);
buffer.Emit<OpCode::Mov>(edx, edx);
buffer.Emit<OpCode::Mov>(rdx, rdx);
buffer.Emit<OpCode::Mov>(dl, rdx, -4);
buffer.Emit<OpCode::Mov>(dl, rdx, 4);
buffer.Emit<OpCode::Mov>(dx, rdx, 4);
buffer.Emit<OpCode::Mov>(edx, rdx, 4);
buffer.Emit<OpCode::Mov>(rdx, rdx, 4);
buffer.Emit<OpCode::Mov>(rdx, -4, dl);
buffer.Emit<OpCode::Mov>(rdx, 4, dl);
buffer.Emit<OpCode::Mov>(rdx, 4, dx);
buffer.Emit<OpCode::Mov>(rdx, 4, edx);
buffer.Emit<OpCode::Mov>(rdx, 4, rdx);
buffer.Emit<OpCode::MovZX>(dx, dl);
buffer.Emit<OpCode::MovZX, 2, false, 1, false>(dx, rdx, 4);
buffer.Emit<OpCode::MovZX>(edx, dl);
buffer.Emit<OpCode::MovZX>(edx, dx);
buffer.Emit<OpCode::MovZX, 4, false, 1, false>(edx, rdx, 4);
buffer.Emit<OpCode::MovZX, 4, false, 2, false>(edx, rdx, 4);
buffer.Emit<OpCode::MovZX>(rdx, dl);
buffer.Emit<OpCode::MovZX>(rdx, dx);
buffer.Emit<OpCode::MovZX, 8, false, 1, false>(rdx, rdx, 4);
buffer.Emit<OpCode::MovZX, 8, false, 2, false>(rdx, rdx, 4);
// Source: rdx, target: rbx
buffer.EmitImmediate<OpCode::Mov>(bl, static_cast<uint8_t>(1));
buffer.EmitImmediate<OpCode::Mov>(bx, static_cast<uint16_t>(1));
buffer.EmitImmediate<OpCode::Mov>(ebx, 1);
buffer.EmitImmediate<OpCode::Mov>(rbx, 1);
buffer.Emit<OpCode::Mov>(bl, dl);
buffer.Emit<OpCode::Mov>(bx, dx);
buffer.Emit<OpCode::Mov>(ebx, edx);
buffer.Emit<OpCode::Mov>(rbx, rdx);
buffer.Emit<OpCode::Mov>(bl, rdx, -4);
buffer.Emit<OpCode::Mov>(bl, rdx, 4);
buffer.Emit<OpCode::Mov>(bx, rdx, 4);
buffer.Emit<OpCode::Mov>(ebx, rdx, 4);
buffer.Emit<OpCode::Mov>(rbx, rdx, 4);
buffer.Emit<OpCode::Mov>(rbx, -4, dl);
buffer.Emit<OpCode::Mov>(rbx, 4, dl);
buffer.Emit<OpCode::Mov>(rbx, 4, dx);
buffer.Emit<OpCode::Mov>(rbx, 4, edx);
buffer.Emit<OpCode::Mov>(rbx, 4, rdx);
buffer.Emit<OpCode::MovZX>(bx, dl);
buffer.Emit<OpCode::MovZX, 2, false, 1, false>(bx, rdx, 4);
buffer.Emit<OpCode::MovZX>(ebx, dl);
buffer.Emit<OpCode::MovZX>(ebx, dx);
buffer.Emit<OpCode::MovZX, 4, false, 1, false>(ebx, rdx, 4);
buffer.Emit<OpCode::MovZX, 4, false, 2, false>(ebx, rdx, 4);
buffer.Emit<OpCode::MovZX>(rbx, dl);
buffer.Emit<OpCode::MovZX>(rbx, dx);
buffer.Emit<OpCode::MovZX, 8, false, 1, false>(rbx, rdx, 4);
buffer.Emit<OpCode::MovZX, 8, false, 2, false>(rbx, rdx, 4);
// Source: rdx, target: rsp
buffer.EmitImmediate<OpCode::Mov>(spl, static_cast<uint8_t>(1));
buffer.EmitImmediate<OpCode::Mov>(sp, static_cast<uint16_t>(1));
buffer.EmitImmediate<OpCode::Mov>(esp, 1);
buffer.EmitImmediate<OpCode::Mov>(rsp, 1);
buffer.Emit<OpCode::Mov>(spl, dl);
buffer.Emit<OpCode::Mov>(sp, dx);
buffer.Emit<OpCode::Mov>(esp, edx);
buffer.Emit<OpCode::Mov>(rsp, rdx);
buffer.Emit<OpCode::Mov>(spl, rdx, -4);
buffer.Emit<OpCode::Mov>(spl, rdx, 4);
buffer.Emit<OpCode::Mov>(sp, rdx, 4);
buffer.Emit<OpCode::Mov>(esp, rdx, 4);
buffer.Emit<OpCode::Mov>(rsp, rdx, 4);
buffer.Emit<OpCode::Mov>(rsp, -4, dl);
buffer.Emit<OpCode::Mov>(rsp, 4, dl);
buffer.Emit<OpCode::Mov>(rsp, 4, dx);
buffer.Emit<OpCode::Mov>(rsp, 4, edx);
buffer.Emit<OpCode::Mov>(rsp, 4, rdx);
buffer.Emit<OpCode::MovZX>(sp, dl);
buffer.Emit<OpCode::MovZX, 2, false, 1, false>(sp, rdx, 4);
buffer.Emit<OpCode::MovZX>(esp, dl);
buffer.Emit<OpCode::MovZX>(esp, dx);
buffer.Emit<OpCode::MovZX, 4, false, 1, false>(esp, rdx, 4);
buffer.Emit<OpCode::MovZX, 4, false, 2, false>(esp, rdx, 4);
buffer.Emit<OpCode::MovZX>(rsp, dl);
buffer.Emit<OpCode::MovZX>(rsp, dx);
buffer.Emit<OpCode::MovZX, 8, false, 1, false>(rsp, rdx, 4);
buffer.Emit<OpCode::MovZX, 8, false, 2, false>(rsp, rdx, 4);
// Source: rdx, target: rbp
buffer.EmitImmediate<OpCode::Mov>(bpl, static_cast<uint8_t>(1));
buffer.EmitImmediate<OpCode::Mov>(bp, static_cast<uint16_t>(1));
buffer.EmitImmediate<OpCode::Mov>(ebp, 1);
buffer.EmitImmediate<OpCode::Mov>(rbp, 1);
buffer.Emit<OpCode::Mov>(bpl, dl);
buffer.Emit<OpCode::Mov>(bp, dx);
buffer.Emit<OpCode::Mov>(ebp, edx);
buffer.Emit<OpCode::Mov>(rbp, rdx);
buffer.Emit<OpCode::Mov>(bpl, rdx, -4);
buffer.Emit<OpCode::Mov>(bpl, rdx, 4);
buffer.Emit<OpCode::Mov>(bp, rdx, 4);
buffer.Emit<OpCode::Mov>(ebp, rdx, 4);
buffer.Emit<OpCode::Mov>(rbp, rdx, 4);
buffer.Emit<OpCode::Mov>(rbp, -4, dl);
buffer.Emit<OpCode::Mov>(rbp, 4, dl);
buffer.Emit<OpCode::Mov>(rbp, 4, dx);
buffer.Emit<OpCode::Mov>(rbp, 4, edx);
buffer.Emit<OpCode::Mov>(rbp, 4, rdx);
buffer.Emit<OpCode::MovZX>(bp, dl);
buffer.Emit<OpCode::MovZX, 2, false, 1, false>(bp, rdx, 4);
buffer.Emit<OpCode::MovZX>(ebp, dl);
buffer.Emit<OpCode::MovZX>(ebp, dx);
buffer.Emit<OpCode::MovZX, 4, false, 1, false>(ebp, rdx, 4);
buffer.Emit<OpCode::MovZX, 4, false, 2, false>(ebp, rdx, 4);
buffer.Emit<OpCode::MovZX>(rbp, dl);
buffer.Emit<OpCode::MovZX>(rbp, dx);
buffer.Emit<OpCode::MovZX, 8, false, 1, false>(rbp, rdx, 4);
buffer.Emit<OpCode::MovZX, 8, false, 2, false>(rbp, rdx, 4);
// Source: rdx, target: rsi
buffer.EmitImmediate<OpCode::Mov>(dil, static_cast<uint8_t>(1));
buffer.EmitImmediate<OpCode::Mov>(si, static_cast<uint16_t>(1));
buffer.EmitImmediate<OpCode::Mov>(esi, 1);
buffer.EmitImmediate<OpCode::Mov>(rsi, 1);
buffer.Emit<OpCode::Mov>(dil, dl);
buffer.Emit<OpCode::Mov>(si, dx);
buffer.Emit<OpCode::Mov>(esi, edx);
buffer.Emit<OpCode::Mov>(rsi, rdx);
buffer.Emit<OpCode::Mov>(dil, rdx, -4);
buffer.Emit<OpCode::Mov>(dil, rdx, 4);
buffer.Emit<OpCode::Mov>(si, rdx, 4);
buffer.Emit<OpCode::Mov>(esi, rdx, 4);
buffer.Emit<OpCode::Mov>(rsi, rdx, 4);
buffer.Emit<OpCode::Mov>(rsi, -4, dl);
buffer.Emit<OpCode::Mov>(rsi, 4, dl);
buffer.Emit<OpCode::Mov>(rsi, 4, dx);
buffer.Emit<OpCode::Mov>(rsi, 4, edx);
buffer.Emit<OpCode::Mov>(rsi, 4, rdx);
buffer.Emit<OpCode::MovZX>(si, dl);
buffer.Emit<OpCode::MovZX, 2, false, 1, false>(si, rdx, 4);
buffer.Emit<OpCode::MovZX>(esi, dl);
buffer.Emit<OpCode::MovZX>(esi, dx);
buffer.Emit<OpCode::MovZX, 4, false, 1, false>(esi, rdx, 4);
buffer.Emit<OpCode::MovZX, 4, false, 2, false>(esi, rdx, 4);
buffer.Emit<OpCode::MovZX>(rsi, dl);
buffer.Emit<OpCode::MovZX>(rsi, dx);
buffer.Emit<OpCode::MovZX, 8, false, 1, false>(rsi, rdx, 4);
buffer.Emit<OpCode::MovZX, 8, false, 2, false>(rsi, rdx, 4);
// Source: rdx, target: rdi
buffer.EmitImmediate<OpCode::Mov>(sil, static_cast<uint8_t>(1));
buffer.EmitImmediate<OpCode::Mov>(di, static_cast<uint16_t>(1));
buffer.EmitImmediate<OpCode::Mov>(edi, 1);
buffer.EmitImmediate<OpCode::Mov>(rdi, 1);
buffer.Emit<OpCode::Mov>(sil, dl);
buffer.Emit<OpCode::Mov>(di, dx);
buffer.Emit<OpCode::Mov>(edi, edx);
buffer.Emit<OpCode::Mov>(rdi, rdx);
buffer.Emit<OpCode::Mov>(sil, rdx, -4);
buffer.Emit<OpCode::Mov>(sil, rdx, 4);
buffer.Emit<OpCode::Mov>(di, rdx, 4);
buffer.Emit<OpCode::Mov>(edi, rdx, 4);
buffer.Emit<OpCode::Mov>(rdi, rdx, 4);
buffer.Emit<OpCode::Mov>(rdi, -4, dl);
buffer.Emit<OpCode::Mov>(rdi, 4, dl);
buffer.Emit<OpCode::Mov>(rdi, 4, dx);
buffer.Emit<OpCode::Mov>(rdi, 4, edx);
buffer.Emit<OpCode::Mov>(rdi, 4, rdx);
buffer.Emit<OpCode::MovZX>(di, dl);
buffer.Emit<OpCode::MovZX, 2, false, 1, false>(di, rdx, 4);
buffer.Emit<OpCode::MovZX>(edi, dl);
buffer.Emit<OpCode::MovZX>(edi, dx);
buffer.Emit<OpCode::MovZX, 4, false, 1, false>(edi, rdx, 4);
buffer.Emit<OpCode::MovZX, 4, false, 2, false>(edi, rdx, 4);
buffer.Emit<OpCode::MovZX>(rdi, dl);
buffer.Emit<OpCode::MovZX>(rdi, dx);
buffer.Emit<OpCode::MovZX, 8, false, 1, false>(rdi, rdx, 4);
buffer.Emit<OpCode::MovZX, 8, false, 2, false>(rdi, rdx, 4);
// Source: rdx, target: r8
buffer.EmitImmediate<OpCode::Mov>(r8b, static_cast<uint8_t>(1));
buffer.EmitImmediate<OpCode::Mov>(r8w, static_cast<uint16_t>(1));
buffer.EmitImmediate<OpCode::Mov>(r8d, 1);
buffer.EmitImmediate<OpCode::Mov>(r8, 1);
buffer.Emit<OpCode::Mov>(r8b, dl);
buffer.Emit<OpCode::Mov>(r8w, dx);
buffer.Emit<OpCode::Mov>(r8d, edx);
buffer.Emit<OpCode::Mov>(r8, rdx);
buffer.Emit<OpCode::Mov>(r8b, rdx, -4);
buffer.Emit<OpCode::Mov>(r8b, rdx, 4);
buffer.Emit<OpCode::Mov>(r8w, rdx, 4);
buffer.Emit<OpCode::Mov>(r8d, rdx, 4);
buffer.Emit<OpCode::Mov>(r8, rdx, 4);
buffer.Emit<OpCode::Mov>(r8, -4, dl);
buffer.Emit<OpCode::Mov>(r8, 4, dl);
buffer.Emit<OpCode::Mov>(r8, 4, dx);
buffer.Emit<OpCode::Mov>(r8, 4, edx);
buffer.Emit<OpCode::Mov>(r8, 4, rdx);
buffer.Emit<OpCode::MovZX>(r8w, dl);
buffer.Emit<OpCode::MovZX, 2, false, 1, false>(r8w, rdx, 4);
buffer.Emit<OpCode::MovZX>(r8d, dl);
buffer.Emit<OpCode::MovZX>(r8d, dx);
buffer.Emit<OpCode::MovZX, 4, false, 1, false>(r8d, rdx, 4);
buffer.Emit<OpCode::MovZX, 4, false, 2, false>(r8d, rdx, 4);
buffer.Emit<OpCode::MovZX>(r8, dl);
buffer.Emit<OpCode::MovZX>(r8, dx);
buffer.Emit<OpCode::MovZX, 8, false, 1, false>(r8, rdx, 4);
buffer.Emit<OpCode::MovZX, 8, false, 2, false>(r8, rdx, 4);
// Source: rdx, target: r9
buffer.EmitImmediate<OpCode::Mov>(r9b, static_cast<uint8_t>(1));
buffer.EmitImmediate<OpCode::Mov>(r9w, static_cast<uint16_t>(1));
buffer.EmitImmediate<OpCode::Mov>(r9d, 1);
buffer.EmitImmediate<OpCode::Mov>(r9, 1);
buffer.Emit<OpCode::Mov>(r9b, dl);
buffer.Emit<OpCode::Mov>(r9w, dx);
buffer.Emit<OpCode::Mov>(r9d, edx);
buffer.Emit<OpCode::Mov>(r9, rdx);
buffer.Emit<OpCode::Mov>(r9b, rdx, -4);
buffer.Emit<OpCode::Mov>(r9b, rdx, 4);
buffer.Emit<OpCode::Mov>(r9w, rdx, 4);
buffer.Emit<OpCode::Mov>(r9d, rdx, 4);
buffer.Emit<OpCode::Mov>(r9, rdx, 4);
buffer.Emit<OpCode::Mov>(r9, -4, dl);
buffer.Emit<OpCode::Mov>(r9, 4, dl);
buffer.Emit<OpCode::Mov>(r9, 4, dx);
buffer.Emit<OpCode::Mov>(r9, 4, edx);
buffer.Emit<OpCode::Mov>(r9, 4, rdx);
buffer.Emit<OpCode::MovZX>(r9w, dl);
buffer.Emit<OpCode::MovZX, 2, false, 1, false>(r9w, rdx, 4);
buffer.Emit<OpCode::MovZX>(r9d, dl);
buffer.Emit<OpCode::MovZX>(r9d, dx);
buffer.Emit<OpCode::MovZX, 4, false, 1, false>(r9d, rdx, 4);
buffer.Emit<OpCode::MovZX, 4, false, 2, false>(r9d, rdx, 4);
buffer.Emit<OpCode::MovZX>(r9, dl);
buffer.Emit<OpCode::MovZX>(r9, dx);
buffer.Emit<OpCode::MovZX, 8, false, 1, false>(r9, rdx, 4);
buffer.Emit<OpCode::MovZX, 8, false, 2, false>(r9, rdx, 4);
// Source: rdx, target: r10
buffer.EmitImmediate<OpCode::Mov>(r10b, static_cast<uint8_t>(1));
buffer.EmitImmediate<OpCode::Mov>(r10w, static_cast<uint16_t>(1));
buffer.EmitImmediate<OpCode::Mov>(r10d, 1);
buffer.EmitImmediate<OpCode::Mov>(r10, 1);
buffer.Emit<OpCode::Mov>(r10b, dl);
buffer.Emit<OpCode::Mov>(r10w, dx);
buffer.Emit<OpCode::Mov>(r10d, edx);
buffer.Emit<OpCode::Mov>(r10, rdx);
buffer.Emit<OpCode::Mov>(r10b, rdx, -4);
buffer.Emit<OpCode::Mov>(r10b, rdx, 4);
buffer.Emit<OpCode::Mov>(r10w, rdx, 4);
buffer.Emit<OpCode::Mov>(r10d, rdx, 4);
buffer.Emit<OpCode::Mov>(r10, rdx, 4);
buffer.Emit<OpCode::Mov>(r10, -4, dl);
buffer.Emit<OpCode::Mov>(r10, 4, dl);
buffer.Emit<OpCode::Mov>(r10, 4, dx);
buffer.Emit<OpCode::Mov>(r10, 4, edx);
buffer.Emit<OpCode::Mov>(r10, 4, rdx);
buffer.Emit<OpCode::MovZX>(r10w, dl);
buffer.Emit<OpCode::MovZX, 2, false, 1, false>(r10w, rdx, 4);
buffer.Emit<OpCode::MovZX>(r10d, dl);
buffer.Emit<OpCode::MovZX>(r10d, dx);
buffer.Emit<OpCode::MovZX, 4, false, 1, false>(r10d, rdx, 4);
buffer.Emit<OpCode::MovZX, 4, false, 2, false>(r10d, rdx, 4);
buffer.Emit<OpCode::MovZX>(r10, dl);
buffer.Emit<OpCode::MovZX>(r10, dx);
buffer.Emit<OpCode::MovZX, 8, false, 1, false>(r10, rdx, 4);
buffer.Emit<OpCode::MovZX, 8, false, 2, false>(r10, rdx, 4);
// Source: rdx, target: r11
buffer.EmitImmediate<OpCode::Mov>(r11b, static_cast<uint8_t>(1));
buffer.EmitImmediate<OpCode::Mov>(r11w, static_cast<uint16_t>(1));
buffer.EmitImmediate<OpCode::Mov>(r11d, 1);
buffer.EmitImmediate<OpCode::Mov>(r11, 1);
buffer.Emit<OpCode::Mov>(r11b, dl);
buffer.Emit<OpCode::Mov>(r11w, dx);
buffer.Emit<OpCode::Mov>(r11d, edx);
buffer.Emit<OpCode::Mov>(r11, rdx);
buffer.Emit<OpCode::Mov>(r11b, rdx, -4);
buffer.Emit<OpCode::Mov>(r11b, rdx, 4);
buffer.Emit<OpCode::Mov>(r11w, rdx, 4);
buffer.Emit<OpCode::Mov>(r11d, rdx, 4);
buffer.Emit<OpCode::Mov>(r11, rdx, 4);
buffer.Emit<OpCode::Mov>(r11, -4, dl);
buffer.Emit<OpCode::Mov>(r11, 4, dl);
buffer.Emit<OpCode::Mov>(r11, 4, dx);
buffer.Emit<OpCode::Mov>(r11, 4, edx);
buffer.Emit<OpCode::Mov>(r11, 4, rdx);
buffer.Emit<OpCode::MovZX>(r11w, dl);
buffer.Emit<OpCode::MovZX, 2, false, 1, false>(r11w, rdx, 4);
buffer.Emit<OpCode::MovZX>(r11d, dl);
buffer.Emit<OpCode::MovZX>(r11d, dx);
buffer.Emit<OpCode::MovZX, 4, false, 1, false>(r11d, rdx, 4);
buffer.Emit<OpCode::MovZX, 4, false, 2, false>(r11d, rdx, 4);
buffer.Emit<OpCode::MovZX>(r11, dl);
buffer.Emit<OpCode::MovZX>(r11, dx);
buffer.Emit<OpCode::MovZX, 8, false, 1, false>(r11, rdx, 4);
buffer.Emit<OpCode::MovZX, 8, false, 2, false>(r11, rdx, 4);
// Source: rdx, target: r12
buffer.EmitImmediate<OpCode::Mov>(r12b, static_cast<uint8_t>(1));
buffer.EmitImmediate<OpCode::Mov>(r12w, static_cast<uint16_t>(1));
buffer.EmitImmediate<OpCode::Mov>(r12d, 1);
buffer.EmitImmediate<OpCode::Mov>(r12, 1);
buffer.Emit<OpCode::Mov>(r12b, dl);
buffer.Emit<OpCode::Mov>(r12w, dx);
buffer.Emit<OpCode::Mov>(r12d, edx);
buffer.Emit<OpCode::Mov>(r12, rdx);
buffer.Emit<OpCode::Mov>(r12b, rdx, -4);
buffer.Emit<OpCode::Mov>(r12b, rdx, 4);
buffer.Emit<OpCode::Mov>(r12w, rdx, 4);
buffer.Emit<OpCode::Mov>(r12d, rdx, 4);
buffer.Emit<OpCode::Mov>(r12, rdx, 4);
buffer.Emit<OpCode::Mov>(r12, -4, dl);
buffer.Emit<OpCode::Mov>(r12, 4, dl);
buffer.Emit<OpCode::Mov>(r12, 4, dx);
buffer.Emit<OpCode::Mov>(r12, 4, edx);
buffer.Emit<OpCode::Mov>(r12, 4, rdx);
buffer.Emit<OpCode::MovZX>(r12w, dl);
buffer.Emit<OpCode::MovZX, 2, false, 1, false>(r12w, rdx, 4);
buffer.Emit<OpCode::MovZX>(r12d, dl);
buffer.Emit<OpCode::MovZX>(r12d, dx);
buffer.Emit<OpCode::MovZX, 4, false, 1, false>(r12d, rdx, 4);
buffer.Emit<OpCode::MovZX, 4, false, 2, false>(r12d, rdx, 4);
buffer.Emit<OpCode::MovZX>(r12, dl);
buffer.Emit<OpCode::MovZX>(r12, dx);
buffer.Emit<OpCode::MovZX, 8, false, 1, false>(r12, rdx, 4);
buffer.Emit<OpCode::MovZX, 8, false, 2, false>(r12, rdx, 4);
// Source: rdx, target: r13
buffer.EmitImmediate<OpCode::Mov>(r13b, static_cast<uint8_t>(1));
buffer.EmitImmediate<OpCode::Mov>(r13w, static_cast<uint16_t>(1));
buffer.EmitImmediate<OpCode::Mov>(r13d, 1);
buffer.EmitImmediate<OpCode::Mov>(r13, 1);
buffer.Emit<OpCode::Mov>(r13b, dl);
buffer.Emit<OpCode::Mov>(r13w, dx);
buffer.Emit<OpCode::Mov>(r13d, edx);
buffer.Emit<OpCode::Mov>(r13, rdx);
buffer.Emit<OpCode::Mov>(r13b, rdx, -4);
buffer.Emit<OpCode::Mov>(r13b, rdx, 4);
buffer.Emit<OpCode::Mov>(r13w, rdx, 4);
buffer.Emit<OpCode::Mov>(r13d, rdx, 4);
buffer.Emit<OpCode::Mov>(r13, rdx, 4);
buffer.Emit<OpCode::Mov>(r13, -4, dl);
buffer.Emit<OpCode::Mov>(r13, 4, dl);
buffer.Emit<OpCode::Mov>(r13, 4, dx);
buffer.Emit<OpCode::Mov>(r13, 4, edx);
buffer.Emit<OpCode::Mov>(r13, 4, rdx);
buffer.Emit<OpCode::MovZX>(r13w, dl);
buffer.Emit<OpCode::MovZX, 2, false, 1, false>(r13w, rdx, 4);
buffer.Emit<OpCode::MovZX>(r13d, dl);
buffer.Emit<OpCode::MovZX>(r13d, dx);
buffer.Emit<OpCode::MovZX, 4, false, 1, false>(r13d, rdx, 4);
buffer.Emit<OpCode::MovZX, 4, false, 2, false>(r13d, rdx, 4);
buffer.Emit<OpCode::MovZX>(r13, dl);
buffer.Emit<OpCode::MovZX>(r13, dx);
buffer.Emit<OpCode::MovZX, 8, false, 1, false>(r13, rdx, 4);
buffer.Emit<OpCode::MovZX, 8, false, 2, false>(r13, rdx, 4);
// Source: rdx, target: r14
buffer.EmitImmediate<OpCode::Mov>(r14b, static_cast<uint8_t>(1));
buffer.EmitImmediate<OpCode::Mov>(r14w, static_cast<uint16_t>(1));
buffer.EmitImmediate<OpCode::Mov>(r14d, 1);
buffer.EmitImmediate<OpCode::Mov>(r14, 1);
buffer.Emit<OpCode::Mov>(r14b, dl);
buffer.Emit<OpCode::Mov>(r14w, dx);
buffer.Emit<OpCode::Mov>(r14d, edx);
buffer.Emit<OpCode::Mov>(r14, rdx);
buffer.Emit<OpCode::Mov>(r14b, rdx, -4);
buffer.Emit<OpCode::Mov>(r14b, rdx, 4);
buffer.Emit<OpCode::Mov>(r14w, rdx, 4);
buffer.Emit<OpCode::Mov>(r14d, rdx, 4);
buffer.Emit<OpCode::Mov>(r14, rdx, 4);
buffer.Emit<OpCode::Mov>(r14, -4, dl);
buffer.Emit<OpCode::Mov>(r14, 4, dl);
buffer.Emit<OpCode::Mov>(r14, 4, dx);
buffer.Emit<OpCode::Mov>(r14, 4, edx);
buffer.Emit<OpCode::Mov>(r14, 4, rdx);
buffer.Emit<OpCode::MovZX>(r14w, dl);
buffer.Emit<OpCode::MovZX, 2, false, 1, false>(r14w, rdx, 4);
buffer.Emit<OpCode::MovZX>(r14d, dl);
buffer.Emit<OpCode::MovZX>(r14d, dx);
buffer.Emit<OpCode::MovZX, 4, false, 1, false>(r14d, rdx, 4);
buffer.Emit<OpCode::MovZX, 4, false, 2, false>(r14d, rdx, 4);
buffer.Emit<OpCode::MovZX>(r14, dl);
buffer.Emit<OpCode::MovZX>(r14, dx);
buffer.Emit<OpCode::MovZX, 8, false, 1, false>(r14, rdx, 4);
buffer.Emit<OpCode::MovZX, 8, false, 2, false>(r14, rdx, 4);
// Source: rdx, target: r15
buffer.EmitImmediate<OpCode::Mov>(r15b, static_cast<uint8_t>(1));
buffer.EmitImmediate<OpCode::Mov>(r15w, static_cast<uint16_t>(1));
buffer.EmitImmediate<OpCode::Mov>(r15d, 1);
buffer.EmitImmediate<OpCode::Mov>(r15, 1);
buffer.Emit<OpCode::Mov>(r15b, dl);
buffer.Emit<OpCode::Mov>(r15w, dx);
buffer.Emit<OpCode::Mov>(r15d, edx);
buffer.Emit<OpCode::Mov>(r15, rdx);
buffer.Emit<OpCode::Mov>(r15b, rdx, -4);
buffer.Emit<OpCode::Mov>(r15b, rdx, 4);
buffer.Emit<OpCode::Mov>(r15w, rdx, 4);
buffer.Emit<OpCode::Mov>(r15d, rdx, 4);
buffer.Emit<OpCode::Mov>(r15, rdx, 4);
buffer.Emit<OpCode::Mov>(r15, -4, dl);
buffer.Emit<OpCode::Mov>(r15, 4, dl);
buffer.Emit<OpCode::Mov>(r15, 4, dx);
buffer.Emit<OpCode::Mov>(r15, 4, edx);
buffer.Emit<OpCode::Mov>(r15, 4, rdx);
buffer.Emit<OpCode::MovZX>(r15w, dl);
buffer.Emit<OpCode::MovZX, 2, false, 1, false>(r15w, rdx, 4);
buffer.Emit<OpCode::MovZX>(r15d, dl);
buffer.Emit<OpCode::MovZX>(r15d, dx);
buffer.Emit<OpCode::MovZX, 4, false, 1, false>(r15d, rdx, 4);
buffer.Emit<OpCode::MovZX, 4, false, 2, false>(r15d, rdx, 4);
buffer.Emit<OpCode::MovZX>(r15, dl);
buffer.Emit<OpCode::MovZX>(r15, dx);
buffer.Emit<OpCode::MovZX, 8, false, 1, false>(r15, rdx, 4);
buffer.Emit<OpCode::MovZX, 8, false, 2, false>(r15, rdx, 4);
// Source: rbx, target: rax
buffer.EmitImmediate<OpCode::Mov>(al, static_cast<uint8_t>(1));
buffer.EmitImmediate<OpCode::Mov>(ax, static_cast<uint16_t>(1));
buffer.EmitImmediate<OpCode::Mov>(eax, 1);
buffer.EmitImmediate<OpCode::Mov>(rax, 1);
buffer.Emit<OpCode::Mov>(al, bl);
buffer.Emit<OpCode::Mov>(ax, bx);
buffer.Emit<OpCode::Mov>(eax, ebx);
buffer.Emit<OpCode::Mov>(rax, rbx);
buffer.Emit<OpCode::Mov>(al, rbx, -4);
buffer.Emit<OpCode::Mov>(al, rbx, 4);
buffer.Emit<OpCode::Mov>(ax, rbx, 4);
buffer.Emit<OpCode::Mov>(eax, rbx, 4);
buffer.Emit<OpCode::Mov>(rax, rbx, 4);
buffer.Emit<OpCode::Mov>(rax, -4, bl);
buffer.Emit<OpCode::Mov>(rax, 4, bl);
buffer.Emit<OpCode::Mov>(rax, 4, bx);
buffer.Emit<OpCode::Mov>(rax, 4, ebx);
buffer.Emit<OpCode::Mov>(rax, 4, rbx);
buffer.Emit<OpCode::MovZX>(ax, bl);
buffer.Emit<OpCode::MovZX, 2, false, 1, false>(ax, rbx, 4);
buffer.Emit<OpCode::MovZX>(eax, bl);
buffer.Emit<OpCode::MovZX>(eax, bx);
buffer.Emit<OpCode::MovZX, 4, false, 1, false>(eax, rbx, 4);
buffer.Emit<OpCode::MovZX, 4, false, 2, false>(eax, rbx, 4);
buffer.Emit<OpCode::MovZX>(rax, bl);
buffer.Emit<OpCode::MovZX>(rax, bx);
buffer.Emit<OpCode::MovZX, 8, false, 1, false>(rax, rbx, 4);
buffer.Emit<OpCode::MovZX, 8, false, 2, false>(rax, rbx, 4);
// Source: rbx, target: rcx
buffer.EmitImmediate<OpCode::Mov>(cl, static_cast<uint8_t>(1));
buffer.EmitImmediate<OpCode::Mov>(cx, static_cast<uint16_t>(1));
buffer.EmitImmediate<OpCode::Mov>(ecx, 1);
buffer.EmitImmediate<OpCode::Mov>(rcx, 1);
buffer.Emit<OpCode::Mov>(cl, bl);
buffer.Emit<OpCode::Mov>(cx, bx);
buffer.Emit<OpCode::Mov>(ecx, ebx);
buffer.Emit<OpCode::Mov>(rcx, rbx);
buffer.Emit<OpCode::Mov>(cl, rbx, -4);
buffer.Emit<OpCode::Mov>(cl, rbx, 4);
buffer.Emit<OpCode::Mov>(cx, rbx, 4);
buffer.Emit<OpCode::Mov>(ecx, rbx, 4);
buffer.Emit<OpCode::Mov>(rcx, rbx, 4);
buffer.Emit<OpCode::Mov>(rcx, -4, bl);
buffer.Emit<OpCode::Mov>(rcx, 4, bl);
buffer.Emit<OpCode::Mov>(rcx, 4, bx);
buffer.Emit<OpCode::Mov>(rcx, 4, ebx);
buffer.Emit<OpCode::Mov>(rcx, 4, rbx);
buffer.Emit<OpCode::MovZX>(cx, bl);
buffer.Emit<OpCode::MovZX, 2, false, 1, false>(cx, rbx, 4);
buffer.Emit<OpCode::MovZX>(ecx, bl);
buffer.Emit<OpCode::MovZX>(ecx, bx);
buffer.Emit<OpCode::MovZX, 4, false, 1, false>(ecx, rbx, 4);
buffer.Emit<OpCode::MovZX, 4, false, 2, false>(ecx, rbx, 4);
buffer.Emit<OpCode::MovZX>(rcx, bl);
buffer.Emit<OpCode::MovZX>(rcx, bx);
buffer.Emit<OpCode::MovZX, 8, false, 1, false>(rcx, rbx, 4);
buffer.Emit<OpCode::MovZX, 8, false, 2, false>(rcx, rbx, 4);
// Source: rbx, target: rdx
buffer.EmitImmediate<OpCode::Mov>(dl, static_cast<uint8_t>(1));
buffer.EmitImmediate<OpCode::Mov>(dx, static_cast<uint16_t>(1));
buffer.EmitImmediate<OpCode::Mov>(edx, 1);
buffer.EmitImmediate<OpCode::Mov>(rdx, 1);
buffer.Emit<OpCode::Mov>(dl, bl);
buffer.Emit<OpCode::Mov>(dx, bx);
buffer.Emit<OpCode::Mov>(edx, ebx);
buffer.Emit<OpCode::Mov>(rdx, rbx);
buffer.Emit<OpCode::Mov>(dl, rbx, -4);
buffer.Emit<OpCode::Mov>(dl, rbx, 4);
buffer.Emit<OpCode::Mov>(dx, rbx, 4);
buffer.Emit<OpCode::Mov>(edx, rbx, 4);
buffer.Emit<OpCode::Mov>(rdx, rbx, 4);
buffer.Emit<OpCode::Mov>(rdx, -4, bl);
buffer.Emit<OpCode::Mov>(rdx, 4, bl);
buffer.Emit<OpCode::Mov>(rdx, 4, bx);
buffer.Emit<OpCode::Mov>(rdx, 4, ebx);
buffer.Emit<OpCode::Mov>(rdx, 4, rbx);
buffer.Emit<OpCode::MovZX>(dx, bl);
buffer.Emit<OpCode::MovZX, 2, false, 1, false>(dx, rbx, 4);
buffer.Emit<OpCode::MovZX>(edx, bl);
buffer.Emit<OpCode::MovZX>(edx, bx);
buffer.Emit<OpCode::MovZX, 4, false, 1, false>(edx, rbx, 4);
buffer.Emit<OpCode::MovZX, 4, false, 2, false>(edx, rbx, 4);
buffer.Emit<OpCode::MovZX>(rdx, bl);
buffer.Emit<OpCode::MovZX>(rdx, bx);
buffer.Emit<OpCode::MovZX, 8, false, 1, false>(rdx, rbx, 4);
buffer.Emit<OpCode::MovZX, 8, false, 2, false>(rdx, rbx, 4);
// Source: rbx, target: rbx
buffer.EmitImmediate<OpCode::Mov>(bl, static_cast<uint8_t>(1));
buffer.EmitImmediate<OpCode::Mov>(bx, static_cast<uint16_t>(1));
buffer.EmitImmediate<OpCode::Mov>(ebx, 1);
buffer.EmitImmediate<OpCode::Mov>(rbx, 1);
buffer.Emit<OpCode::Mov>(bl, bl);
buffer.Emit<OpCode::Mov>(bx, bx);
buffer.Emit<OpCode::Mov>(ebx, ebx);
buffer.Emit<OpCode::Mov>(rbx, rbx);
buffer.Emit<OpCode::Mov>(bl, rbx, -4);
buffer.Emit<OpCode::Mov>(bl, rbx, 4);
buffer.Emit<OpCode::Mov>(bx, rbx, 4);
buffer.Emit<OpCode::Mov>(ebx, rbx, 4);
buffer.Emit<OpCode::Mov>(rbx, rbx, 4);
buffer.Emit<OpCode::Mov>(rbx, -4, bl);
buffer.Emit<OpCode::Mov>(rbx, 4, bl);
buffer.Emit<OpCode::Mov>(rbx, 4, bx);
buffer.Emit<OpCode::Mov>(rbx, 4, ebx);
buffer.Emit<OpCode::Mov>(rbx, 4, rbx);
buffer.Emit<OpCode::MovZX>(bx, bl);
buffer.Emit<OpCode::MovZX, 2, false, 1, false>(bx, rbx, 4);
buffer.Emit<OpCode::MovZX>(ebx, bl);
buffer.Emit<OpCode::MovZX>(ebx, bx);
buffer.Emit<OpCode::MovZX, 4, false, 1, false>(ebx, rbx, 4);
buffer.Emit<OpCode::MovZX, 4, false, 2, false>(ebx, rbx, 4);
buffer.Emit<OpCode::MovZX>(rbx, bl);
buffer.Emit<OpCode::MovZX>(rbx, bx);
buffer.Emit<OpCode::MovZX, 8, false, 1, false>(rbx, rbx, 4);
buffer.Emit<OpCode::MovZX, 8, false, 2, false>(rbx, rbx, 4);
// Source: rbx, target: rsp
buffer.EmitImmediate<OpCode::Mov>(spl, static_cast<uint8_t>(1));
buffer.EmitImmediate<OpCode::Mov>(sp, static_cast<uint16_t>(1));
buffer.EmitImmediate<OpCode::Mov>(esp, 1);
buffer.EmitImmediate<OpCode::Mov>(rsp, 1);
buffer.Emit<OpCode::Mov>(spl, bl);
buffer.Emit<OpCode::Mov>(sp, bx);
buffer.Emit<OpCode::Mov>(esp, ebx);
buffer.Emit<OpCode::Mov>(rsp, rbx);
buffer.Emit<OpCode::Mov>(spl, rbx, -4);
buffer.Emit<OpCode::Mov>(spl, rbx, 4);
buffer.Emit<OpCode::Mov>(sp, rbx, 4);
buffer.Emit<OpCode::Mov>(esp, rbx, 4);
buffer.Emit<OpCode::Mov>(rsp, rbx, 4);
buffer.Emit<OpCode::Mov>(rsp, -4, bl);
buffer.Emit<OpCode::Mov>(rsp, 4, bl);
buffer.Emit<OpCode::Mov>(rsp, 4, bx);
buffer.Emit<OpCode::Mov>(rsp, 4, ebx);
buffer.Emit<OpCode::Mov>(rsp, 4, rbx);
buffer.Emit<OpCode::MovZX>(sp, bl);
buffer.Emit<OpCode::MovZX, 2, false, 1, false>(sp, rbx, 4);
buffer.Emit<OpCode::MovZX>(esp, bl);
buffer.Emit<OpCode::MovZX>(esp, bx);
buffer.Emit<OpCode::MovZX, 4, false, 1, false>(esp, rbx, 4);
buffer.Emit<OpCode::MovZX, 4, false, 2, false>(esp, rbx, 4);
buffer.Emit<OpCode::MovZX>(rsp, bl);
buffer.Emit<OpCode::MovZX>(rsp, bx);
buffer.Emit<OpCode::MovZX, 8, false, 1, false>(rsp, rbx, 4);
buffer.Emit<OpCode::MovZX, 8, false, 2, false>(rsp, rbx, 4);
// Source: rbx, target: rbp
buffer.EmitImmediate<OpCode::Mov>(bpl, static_cast<uint8_t>(1));
buffer.EmitImmediate<OpCode::Mov>(bp, static_cast<uint16_t>(1));
buffer.EmitImmediate<OpCode::Mov>(ebp, 1);
buffer.EmitImmediate<OpCode::Mov>(rbp, 1);
buffer.Emit<OpCode::Mov>(bpl, bl);
buffer.Emit<OpCode::Mov>(bp, bx);
buffer.Emit<OpCode::Mov>(ebp, ebx);
buffer.Emit<OpCode::Mov>(rbp, rbx);
buffer.Emit<OpCode::Mov>(bpl, rbx, -4);
buffer.Emit<OpCode::Mov>(bpl, rbx, 4);
buffer.Emit<OpCode::Mov>(bp, rbx, 4);
buffer.Emit<OpCode::Mov>(ebp, rbx, 4);
buffer.Emit<OpCode::Mov>(rbp, rbx, 4);
buffer.Emit<OpCode::Mov>(rbp, -4, bl);
buffer.Emit<OpCode::Mov>(rbp, 4, bl);
buffer.Emit<OpCode::Mov>(rbp, 4, bx);
buffer.Emit<OpCode::Mov>(rbp, 4, ebx);
buffer.Emit<OpCode::Mov>(rbp, 4, rbx);
buffer.Emit<OpCode::MovZX>(bp, bl);
buffer.Emit<OpCode::MovZX, 2, false, 1, false>(bp, rbx, 4);
buffer.Emit<OpCode::MovZX>(ebp, bl);
buffer.Emit<OpCode::MovZX>(ebp, bx);
buffer.Emit<OpCode::MovZX, 4, false, 1, false>(ebp, rbx, 4);
buffer.Emit<OpCode::MovZX, 4, false, 2, false>(ebp, rbx, 4);
buffer.Emit<OpCode::MovZX>(rbp, bl);
buffer.Emit<OpCode::MovZX>(rbp, bx);
buffer.Emit<OpCode::MovZX, 8, false, 1, false>(rbp, rbx, 4);
buffer.Emit<OpCode::MovZX, 8, false, 2, false>(rbp, rbx, 4);
// Source: rbx, target: rsi
buffer.EmitImmediate<OpCode::Mov>(dil, static_cast<uint8_t>(1));
buffer.EmitImmediate<OpCode::Mov>(si, static_cast<uint16_t>(1));
buffer.EmitImmediate<OpCode::Mov>(esi, 1);
buffer.EmitImmediate<OpCode::Mov>(rsi, 1);
buffer.Emit<OpCode::Mov>(dil, bl);
buffer.Emit<OpCode::Mov>(si, bx);
buffer.Emit<OpCode::Mov>(esi, ebx);
buffer.Emit<OpCode::Mov>(rsi, rbx);
buffer.Emit<OpCode::Mov>(dil, rbx, -4);
buffer.Emit<OpCode::Mov>(dil, rbx, 4);
buffer.Emit<OpCode::Mov>(si, rbx, 4);
buffer.Emit<OpCode::Mov>(esi, rbx, 4);
buffer.Emit<OpCode::Mov>(rsi, rbx, 4);
buffer.Emit<OpCode::Mov>(rsi, -4, bl);
buffer.Emit<OpCode::Mov>(rsi, 4, bl);
buffer.Emit<OpCode::Mov>(rsi, 4, bx);
buffer.Emit<OpCode::Mov>(rsi, 4, ebx);
buffer.Emit<OpCode::Mov>(rsi, 4, rbx);
buffer.Emit<OpCode::MovZX>(si, bl);
buffer.Emit<OpCode::MovZX, 2, false, 1, false>(si, rbx, 4);
buffer.Emit<OpCode::MovZX>(esi, bl);
buffer.Emit<OpCode::MovZX>(esi, bx);
buffer.Emit<OpCode::MovZX, 4, false, 1, false>(esi, rbx, 4);
buffer.Emit<OpCode::MovZX, 4, false, 2, false>(esi, rbx, 4);
buffer.Emit<OpCode::MovZX>(rsi, bl);
buffer.Emit<OpCode::MovZX>(rsi, bx);
buffer.Emit<OpCode::MovZX, 8, false, 1, false>(rsi, rbx, 4);
buffer.Emit<OpCode::MovZX, 8, false, 2, false>(rsi, rbx, 4);
// Source: rbx, target: rdi
buffer.EmitImmediate<OpCode::Mov>(sil, static_cast<uint8_t>(1));
buffer.EmitImmediate<OpCode::Mov>(di, static_cast<uint16_t>(1));
buffer.EmitImmediate<OpCode::Mov>(edi, 1);
buffer.EmitImmediate<OpCode::Mov>(rdi, 1);
buffer.Emit<OpCode::Mov>(sil, bl);
buffer.Emit<OpCode::Mov>(di, bx);
buffer.Emit<OpCode::Mov>(edi, ebx);
buffer.Emit<OpCode::Mov>(rdi, rbx);
buffer.Emit<OpCode::Mov>(sil, rbx, -4);
buffer.Emit<OpCode::Mov>(sil, rbx, 4);
buffer.Emit<OpCode::Mov>(di, rbx, 4);
buffer.Emit<OpCode::Mov>(edi, rbx, 4);
buffer.Emit<OpCode::Mov>(rdi, rbx, 4);
buffer.Emit<OpCode::Mov>(rdi, -4, bl);
buffer.Emit<OpCode::Mov>(rdi, 4, bl);
buffer.Emit<OpCode::Mov>(rdi, 4, bx);
buffer.Emit<OpCode::Mov>(rdi, 4, ebx);
buffer.Emit<OpCode::Mov>(rdi, 4, rbx);
buffer.Emit<OpCode::MovZX>(di, bl);
buffer.Emit<OpCode::MovZX, 2, false, 1, false>(di, rbx, 4);
buffer.Emit<OpCode::MovZX>(edi, bl);
buffer.Emit<OpCode::MovZX>(edi, bx);
buffer.Emit<OpCode::MovZX, 4, false, 1, false>(edi, rbx, 4);
buffer.Emit<OpCode::MovZX, 4, false, 2, false>(edi, rbx, 4);
buffer.Emit<OpCode::MovZX>(rdi, bl);
buffer.Emit<OpCode::MovZX>(rdi, bx);
buffer.Emit<OpCode::MovZX, 8, false, 1, false>(rdi, rbx, 4);
buffer.Emit<OpCode::MovZX, 8, false, 2, false>(rdi, rbx, 4);
// Source: rbx, target: r8
buffer.EmitImmediate<OpCode::Mov>(r8b, static_cast<uint8_t>(1));
buffer.EmitImmediate<OpCode::Mov>(r8w, static_cast<uint16_t>(1));
buffer.EmitImmediate<OpCode::Mov>(r8d, 1);
buffer.EmitImmediate<OpCode::Mov>(r8, 1);
buffer.Emit<OpCode::Mov>(r8b, bl);
buffer.Emit<OpCode::Mov>(r8w, bx);
buffer.Emit<OpCode::Mov>(r8d, ebx);
buffer.Emit<OpCode::Mov>(r8, rbx);
buffer.Emit<OpCode::Mov>(r8b, rbx, -4);
buffer.Emit<OpCode::Mov>(r8b, rbx, 4);
buffer.Emit<OpCode::Mov>(r8w, rbx, 4);
buffer.Emit<OpCode::Mov>(r8d, rbx, 4);
buffer.Emit<OpCode::Mov>(r8, rbx, 4);
buffer.Emit<OpCode::Mov>(r8, -4, bl);
buffer.Emit<OpCode::Mov>(r8, 4, bl);
buffer.Emit<OpCode::Mov>(r8, 4, bx);
buffer.Emit<OpCode::Mov>(r8, 4, ebx);
buffer.Emit<OpCode::Mov>(r8, 4, rbx);
buffer.Emit<OpCode::MovZX>(r8w, bl);
buffer.Emit<OpCode::MovZX, 2, false, 1, false>(r8w, rbx, 4);
buffer.Emit<OpCode::MovZX>(r8d, bl);
buffer.Emit<OpCode::MovZX>(r8d, bx);
buffer.Emit<OpCode::MovZX, 4, false, 1, false>(r8d, rbx, 4);
buffer.Emit<OpCode::MovZX, 4, false, 2, false>(r8d, rbx, 4);
buffer.Emit<OpCode::MovZX>(r8, bl);
buffer.Emit<OpCode::MovZX>(r8, bx);
buffer.Emit<OpCode::MovZX, 8, false, 1, false>(r8, rbx, 4);
buffer.Emit<OpCode::MovZX, 8, false, 2, false>(r8, rbx, 4);
// Source: rbx, target: r9
buffer.EmitImmediate<OpCode::Mov>(r9b, static_cast<uint8_t>(1));
buffer.EmitImmediate<OpCode::Mov>(r9w, static_cast<uint16_t>(1));
buffer.EmitImmediate<OpCode::Mov>(r9d, 1);
buffer.EmitImmediate<OpCode::Mov>(r9, 1);
buffer.Emit<OpCode::Mov>(r9b, bl);
buffer.Emit<OpCode::Mov>(r9w, bx);
buffer.Emit<OpCode::Mov>(r9d, ebx);
buffer.Emit<OpCode::Mov>(r9, rbx);
buffer.Emit<OpCode::Mov>(r9b, rbx, -4);
buffer.Emit<OpCode::Mov>(r9b, rbx, 4);
buffer.Emit<OpCode::Mov>(r9w, rbx, 4);
buffer.Emit<OpCode::Mov>(r9d, rbx, 4);
buffer.Emit<OpCode::Mov>(r9, rbx, 4);
buffer.Emit<OpCode::Mov>(r9, -4, bl);
buffer.Emit<OpCode::Mov>(r9, 4, bl);
buffer.Emit<OpCode::Mov>(r9, 4, bx);
buffer.Emit<OpCode::Mov>(r9, 4, ebx);
buffer.Emit<OpCode::Mov>(r9, 4, rbx);
buffer.Emit<OpCode::MovZX>(r9w, bl);
buffer.Emit<OpCode::MovZX, 2, false, 1, false>(r9w, rbx, 4);
buffer.Emit<OpCode::MovZX>(r9d, bl);
buffer.Emit<OpCode::MovZX>(r9d, bx);
buffer.Emit<OpCode::MovZX, 4, false, 1, false>(r9d, rbx, 4);
buffer.Emit<OpCode::MovZX, 4, false, 2, false>(r9d, rbx, 4);
buffer.Emit<OpCode::MovZX>(r9, bl);
buffer.Emit<OpCode::MovZX>(r9, bx);
buffer.Emit<OpCode::MovZX, 8, false, 1, false>(r9, rbx, 4);
buffer.Emit<OpCode::MovZX, 8, false, 2, false>(r9, rbx, 4);
// Source: rbx, target: r10
buffer.EmitImmediate<OpCode::Mov>(r10b, static_cast<uint8_t>(1));
buffer.EmitImmediate<OpCode::Mov>(r10w, static_cast<uint16_t>(1));
buffer.EmitImmediate<OpCode::Mov>(r10d, 1);
buffer.EmitImmediate<OpCode::Mov>(r10, 1);
buffer.Emit<OpCode::Mov>(r10b, bl);
buffer.Emit<OpCode::Mov>(r10w, bx);
buffer.Emit<OpCode::Mov>(r10d, ebx);
buffer.Emit<OpCode::Mov>(r10, rbx);
buffer.Emit<OpCode::Mov>(r10b, rbx, -4);
buffer.Emit<OpCode::Mov>(r10b, rbx, 4);
buffer.Emit<OpCode::Mov>(r10w, rbx, 4);
buffer.Emit<OpCode::Mov>(r10d, rbx, 4);
buffer.Emit<OpCode::Mov>(r10, rbx, 4);
buffer.Emit<OpCode::Mov>(r10, -4, bl);
buffer.Emit<OpCode::Mov>(r10, 4, bl);
buffer.Emit<OpCode::Mov>(r10, 4, bx);
buffer.Emit<OpCode::Mov>(r10, 4, ebx);
buffer.Emit<OpCode::Mov>(r10, 4, rbx);
buffer.Emit<OpCode::MovZX>(r10w, bl);
buffer.Emit<OpCode::MovZX, 2, false, 1, false>(r10w, rbx, 4);
buffer.Emit<OpCode::MovZX>(r10d, bl);
buffer.Emit<OpCode::MovZX>(r10d, bx);
buffer.Emit<OpCode::MovZX, 4, false, 1, false>(r10d, rbx, 4);
buffer.Emit<OpCode::MovZX, 4, false, 2, false>(r10d, rbx, 4);
buffer.Emit<OpCode::MovZX>(r10, bl);
buffer.Emit<OpCode::MovZX>(r10, bx);
buffer.Emit<OpCode::MovZX, 8, false, 1, false>(r10, rbx, 4);
buffer.Emit<OpCode::MovZX, 8, false, 2, false>(r10, rbx, 4);
// Source: rbx, target: r11
buffer.EmitImmediate<OpCode::Mov>(r11b, static_cast<uint8_t>(1));
buffer.EmitImmediate<OpCode::Mov>(r11w, static_cast<uint16_t>(1));
buffer.EmitImmediate<OpCode::Mov>(r11d, 1);
buffer.EmitImmediate<OpCode::Mov>(r11, 1);
buffer.Emit<OpCode::Mov>(r11b, bl);
buffer.Emit<OpCode::Mov>(r11w, bx);
buffer.Emit<OpCode::Mov>(r11d, ebx);
buffer.Emit<OpCode::Mov>(r11, rbx);
buffer.Emit<OpCode::Mov>(r11b, rbx, -4);
buffer.Emit<OpCode::Mov>(r11b, rbx, 4);
buffer.Emit<OpCode::Mov>(r11w, rbx, 4);
buffer.Emit<OpCode::Mov>(r11d, rbx, 4);
buffer.Emit<OpCode::Mov>(r11, rbx, 4);
buffer.Emit<OpCode::Mov>(r11, -4, bl);
buffer.Emit<OpCode::Mov>(r11, 4, bl);
buffer.Emit<OpCode::Mov>(r11, 4, bx);
buffer.Emit<OpCode::Mov>(r11, 4, ebx);
buffer.Emit<OpCode::Mov>(r11, 4, rbx);
buffer.Emit<OpCode::MovZX>(r11w, bl);
buffer.Emit<OpCode::MovZX, 2, false, 1, false>(r11w, rbx, 4);
buffer.Emit<OpCode::MovZX>(r11d, bl);
buffer.Emit<OpCode::MovZX>(r11d, bx);
buffer.Emit<OpCode::MovZX, 4, false, 1, false>(r11d, rbx, 4);
buffer.Emit<OpCode::MovZX, 4, false, 2, false>(r11d, rbx, 4);
buffer.Emit<OpCode::MovZX>(r11, bl);
buffer.Emit<OpCode::MovZX>(r11, bx);
buffer.Emit<OpCode::MovZX, 8, false, 1, false>(r11, rbx, 4);
buffer.Emit<OpCode::MovZX, 8, false, 2, false>(r11, rbx, 4);
// Source: rbx, target: r12
buffer.EmitImmediate<OpCode::Mov>(r12b, static_cast<uint8_t>(1));
buffer.EmitImmediate<OpCode::Mov>(r12w, static_cast<uint16_t>(1));
buffer.EmitImmediate<OpCode::Mov>(r12d, 1);
buffer.EmitImmediate<OpCode::Mov>(r12, 1);
buffer.Emit<OpCode::Mov>(r12b, bl);
buffer.Emit<OpCode::Mov>(r12w, bx);
buffer.Emit<OpCode::Mov>(r12d, ebx);
buffer.Emit<OpCode::Mov>(r12, rbx);
buffer.Emit<OpCode::Mov>(r12b, rbx, -4);
buffer.Emit<OpCode::Mov>(r12b, rbx, 4);
buffer.Emit<OpCode::Mov>(r12w, rbx, 4);
buffer.Emit<OpCode::Mov>(r12d, rbx, 4);
buffer.Emit<OpCode::Mov>(r12, rbx, 4);
buffer.Emit<OpCode::Mov>(r12, -4, bl);
buffer.Emit<OpCode::Mov>(r12, 4, bl);
buffer.Emit<OpCode::Mov>(r12, 4, bx);
buffer.Emit<OpCode::Mov>(r12, 4, ebx);
buffer.Emit<OpCode::Mov>(r12, 4, rbx);
buffer.Emit<OpCode::MovZX>(r12w, bl);
buffer.Emit<OpCode::MovZX, 2, false, 1, false>(r12w, rbx, 4);
buffer.Emit<OpCode::MovZX>(r12d, bl);
buffer.Emit<OpCode::MovZX>(r12d, bx);
buffer.Emit<OpCode::MovZX, 4, false, 1, false>(r12d, rbx, 4);
buffer.Emit<OpCode::MovZX, 4, false, 2, false>(r12d, rbx, 4);
buffer.Emit<OpCode::MovZX>(r12, bl);
buffer.Emit<OpCode::MovZX>(r12, bx);
buffer.Emit<OpCode::MovZX, 8, false, 1, false>(r12, rbx, 4);
buffer.Emit<OpCode::MovZX, 8, false, 2, false>(r12, rbx, 4);
// Source: rbx, target: r13
buffer.EmitImmediate<OpCode::Mov>(r13b, static_cast<uint8_t>(1));
buffer.EmitImmediate<OpCode::Mov>(r13w, static_cast<uint16_t>(1));
buffer.EmitImmediate<OpCode::Mov>(r13d, 1);
buffer.EmitImmediate<OpCode::Mov>(r13, 1);
buffer.Emit<OpCode::Mov>(r13b, bl);
buffer.Emit<OpCode::Mov>(r13w, bx);
buffer.Emit<OpCode::Mov>(r13d, ebx);
buffer.Emit<OpCode::Mov>(r13, rbx);
buffer.Emit<OpCode::Mov>(r13b, rbx, -4);
buffer.Emit<OpCode::Mov>(r13b, rbx, 4);
buffer.Emit<OpCode::Mov>(r13w, rbx, 4);
buffer.Emit<OpCode::Mov>(r13d, rbx, 4);
buffer.Emit<OpCode::Mov>(r13, rbx, 4);
buffer.Emit<OpCode::Mov>(r13, -4, bl);
buffer.Emit<OpCode::Mov>(r13, 4, bl);
buffer.Emit<OpCode::Mov>(r13, 4, bx);
buffer.Emit<OpCode::Mov>(r13, 4, ebx);
buffer.Emit<OpCode::Mov>(r13, 4, rbx);
buffer.Emit<OpCode::MovZX>(r13w, bl);
buffer.Emit<OpCode::MovZX, 2, false, 1, false>(r13w, rbx, 4);
buffer.Emit<OpCode::MovZX>(r13d, bl);
buffer.Emit<OpCode::MovZX>(r13d, bx);
buffer.Emit<OpCode::MovZX, 4, false, 1, false>(r13d, rbx, 4);
buffer.Emit<OpCode::MovZX, 4, false, 2, false>(r13d, rbx, 4);
buffer.Emit<OpCode::MovZX>(r13, bl);
buffer.Emit<OpCode::MovZX>(r13, bx);
buffer.Emit<OpCode::MovZX, 8, false, 1, false>(r13, rbx, 4);
buffer.Emit<OpCode::MovZX, 8, false, 2, false>(r13, rbx, 4);
// Source: rbx, target: r14
buffer.EmitImmediate<OpCode::Mov>(r14b, static_cast<uint8_t>(1));
buffer.EmitImmediate<OpCode::Mov>(r14w, static_cast<uint16_t>(1));
buffer.EmitImmediate<OpCode::Mov>(r14d, 1);
buffer.EmitImmediate<OpCode::Mov>(r14, 1);
buffer.Emit<OpCode::Mov>(r14b, bl);
buffer.Emit<OpCode::Mov>(r14w, bx);
buffer.Emit<OpCode::Mov>(r14d, ebx);
buffer.Emit<OpCode::Mov>(r14, rbx);
buffer.Emit<OpCode::Mov>(r14b, rbx, -4);
buffer.Emit<OpCode::Mov>(r14b, rbx, 4);
buffer.Emit<OpCode::Mov>(r14w, rbx, 4);
buffer.Emit<OpCode::Mov>(r14d, rbx, 4);
buffer.Emit<OpCode::Mov>(r14, rbx, 4);
buffer.Emit<OpCode::Mov>(r14, -4, bl);
buffer.Emit<OpCode::Mov>(r14, 4, bl);
buffer.Emit<OpCode::Mov>(r14, 4, bx);
buffer.Emit<OpCode::Mov>(r14, 4, ebx);
buffer.Emit<OpCode::Mov>(r14, 4, rbx);
buffer.Emit<OpCode::MovZX>(r14w, bl);
buffer.Emit<OpCode::MovZX, 2, false, 1, false>(r14w, rbx, 4);
buffer.Emit<OpCode::MovZX>(r14d, bl);
buffer.Emit<OpCode::MovZX>(r14d, bx);
buffer.Emit<OpCode::MovZX, 4, false, 1, false>(r14d, rbx, 4);
buffer.Emit<OpCode::MovZX, 4, false, 2, false>(r14d, rbx, 4);
buffer.Emit<OpCode::MovZX>(r14, bl);
buffer.Emit<OpCode::MovZX>(r14, bx);
buffer.Emit<OpCode::MovZX, 8, false, 1, false>(r14, rbx, 4);
buffer.Emit<OpCode::MovZX, 8, false, 2, false>(r14, rbx, 4);
// Source: rbx, target: r15
buffer.EmitImmediate<OpCode::Mov>(r15b, static_cast<uint8_t>(1));
buffer.EmitImmediate<OpCode::Mov>(r15w, static_cast<uint16_t>(1));
buffer.EmitImmediate<OpCode::Mov>(r15d, 1);
buffer.EmitImmediate<OpCode::Mov>(r15, 1);
buffer.Emit<OpCode::Mov>(r15b, bl);
buffer.Emit<OpCode::Mov>(r15w, bx);
buffer.Emit<OpCode::Mov>(r15d, ebx);
buffer.Emit<OpCode::Mov>(r15, rbx);
buffer.Emit<OpCode::Mov>(r15b, rbx, -4);
buffer.Emit<OpCode::Mov>(r15b, rbx, 4);
buffer.Emit<OpCode::Mov>(r15w, rbx, 4);
buffer.Emit<OpCode::Mov>(r15d, rbx, 4);
buffer.Emit<OpCode::Mov>(r15, rbx, 4);
buffer.Emit<OpCode::Mov>(r15, -4, bl);
buffer.Emit<OpCode::Mov>(r15, 4, bl);
buffer.Emit<OpCode::Mov>(r15, 4, bx);
buffer.Emit<OpCode::Mov>(r15, 4, ebx);
buffer.Emit<OpCode::Mov>(r15, 4, rbx);
buffer.Emit<OpCode::MovZX>(r15w, bl);
buffer.Emit<OpCode::MovZX, 2, false, 1, false>(r15w, rbx, 4);
buffer.Emit<OpCode::MovZX>(r15d, bl);
buffer.Emit<OpCode::MovZX>(r15d, bx);
buffer.Emit<OpCode::MovZX, 4, false, 1, false>(r15d, rbx, 4);
buffer.Emit<OpCode::MovZX, 4, false, 2, false>(r15d, rbx, 4);
buffer.Emit<OpCode::MovZX>(r15, bl);
buffer.Emit<OpCode::MovZX>(r15, bx);
buffer.Emit<OpCode::MovZX, 8, false, 1, false>(r15, rbx, 4);
buffer.Emit<OpCode::MovZX, 8, false, 2, false>(r15, rbx, 4);
// Source: rsp, target: rax
buffer.EmitImmediate<OpCode::Mov>(al, static_cast<uint8_t>(1));
buffer.EmitImmediate<OpCode::Mov>(ax, static_cast<uint16_t>(1));
buffer.EmitImmediate<OpCode::Mov>(eax, 1);
buffer.EmitImmediate<OpCode::Mov>(rax, 1);
buffer.Emit<OpCode::Mov>(al, spl);
buffer.Emit<OpCode::Mov>(ax, sp);
buffer.Emit<OpCode::Mov>(eax, esp);
buffer.Emit<OpCode::Mov>(rax, rsp);
buffer.Emit<OpCode::Mov>(al, rsp, -4);
buffer.Emit<OpCode::Mov>(al, rsp, 4);
buffer.Emit<OpCode::Mov>(ax, rsp, 4);
buffer.Emit<OpCode::Mov>(eax, rsp, 4);
buffer.Emit<OpCode::Mov>(rax, rsp, 4);
buffer.Emit<OpCode::Mov>(rax, -4, spl);
buffer.Emit<OpCode::Mov>(rax, 4, spl);
buffer.Emit<OpCode::Mov>(rax, 4, sp);
buffer.Emit<OpCode::Mov>(rax, 4, esp);
buffer.Emit<OpCode::Mov>(rax, 4, rsp);
buffer.Emit<OpCode::MovZX>(ax, spl);
buffer.Emit<OpCode::MovZX, 2, false, 1, false>(ax, rsp, 4);
buffer.Emit<OpCode::MovZX>(eax, spl);
buffer.Emit<OpCode::MovZX>(eax, sp);
buffer.Emit<OpCode::MovZX, 4, false, 1, false>(eax, rsp, 4);
buffer.Emit<OpCode::MovZX, 4, false, 2, false>(eax, rsp, 4);
buffer.Emit<OpCode::MovZX>(rax, spl);
buffer.Emit<OpCode::MovZX>(rax, sp);
buffer.Emit<OpCode::MovZX, 8, false, 1, false>(rax, rsp, 4);
buffer.Emit<OpCode::MovZX, 8, false, 2, false>(rax, rsp, 4);
// Source: rsp, target: rcx
buffer.EmitImmediate<OpCode::Mov>(cl, static_cast<uint8_t>(1));
buffer.EmitImmediate<OpCode::Mov>(cx, static_cast<uint16_t>(1));
buffer.EmitImmediate<OpCode::Mov>(ecx, 1);
buffer.EmitImmediate<OpCode::Mov>(rcx, 1);
buffer.Emit<OpCode::Mov>(cl, spl);
buffer.Emit<OpCode::Mov>(cx, sp);
buffer.Emit<OpCode::Mov>(ecx, esp);
buffer.Emit<OpCode::Mov>(rcx, rsp);
buffer.Emit<OpCode::Mov>(cl, rsp, -4);
buffer.Emit<OpCode::Mov>(cl, rsp, 4);
buffer.Emit<OpCode::Mov>(cx, rsp, 4);
buffer.Emit<OpCode::Mov>(ecx, rsp, 4);
buffer.Emit<OpCode::Mov>(rcx, rsp, 4);
buffer.Emit<OpCode::Mov>(rcx, -4, spl);
buffer.Emit<OpCode::Mov>(rcx, 4, spl);
buffer.Emit<OpCode::Mov>(rcx, 4, sp);
buffer.Emit<OpCode::Mov>(rcx, 4, esp);
buffer.Emit<OpCode::Mov>(rcx, 4, rsp);
buffer.Emit<OpCode::MovZX>(cx, spl);
buffer.Emit<OpCode::MovZX, 2, false, 1, false>(cx, rsp, 4);
buffer.Emit<OpCode::MovZX>(ecx, spl);
buffer.Emit<OpCode::MovZX>(ecx, sp);
buffer.Emit<OpCode::MovZX, 4, false, 1, false>(ecx, rsp, 4);
buffer.Emit<OpCode::MovZX, 4, false, 2, false>(ecx, rsp, 4);
buffer.Emit<OpCode::MovZX>(rcx, spl);
buffer.Emit<OpCode::MovZX>(rcx, sp);
buffer.Emit<OpCode::MovZX, 8, false, 1, false>(rcx, rsp, 4);
buffer.Emit<OpCode::MovZX, 8, false, 2, false>(rcx, rsp, 4);
// Source: rsp, target: rdx
buffer.EmitImmediate<OpCode::Mov>(dl, static_cast<uint8_t>(1));
buffer.EmitImmediate<OpCode::Mov>(dx, static_cast<uint16_t>(1));
buffer.EmitImmediate<OpCode::Mov>(edx, 1);
buffer.EmitImmediate<OpCode::Mov>(rdx, 1);
buffer.Emit<OpCode::Mov>(dl, spl);
buffer.Emit<OpCode::Mov>(dx, sp);
buffer.Emit<OpCode::Mov>(edx, esp);
buffer.Emit<OpCode::Mov>(rdx, rsp);
buffer.Emit<OpCode::Mov>(dl, rsp, -4);
buffer.Emit<OpCode::Mov>(dl, rsp, 4);
buffer.Emit<OpCode::Mov>(dx, rsp, 4);
buffer.Emit<OpCode::Mov>(edx, rsp, 4);
buffer.Emit<OpCode::Mov>(rdx, rsp, 4);
buffer.Emit<OpCode::Mov>(rdx, -4, spl);
buffer.Emit<OpCode::Mov>(rdx, 4, spl);
buffer.Emit<OpCode::Mov>(rdx, 4, sp);
buffer.Emit<OpCode::Mov>(rdx, 4, esp);
buffer.Emit<OpCode::Mov>(rdx, 4, rsp);
buffer.Emit<OpCode::MovZX>(dx, spl);
buffer.Emit<OpCode::MovZX, 2, false, 1, false>(dx, rsp, 4);
buffer.Emit<OpCode::MovZX>(edx, spl);
buffer.Emit<OpCode::MovZX>(edx, sp);
buffer.Emit<OpCode::MovZX, 4, false, 1, false>(edx, rsp, 4);
buffer.Emit<OpCode::MovZX, 4, false, 2, false>(edx, rsp, 4);
buffer.Emit<OpCode::MovZX>(rdx, spl);
buffer.Emit<OpCode::MovZX>(rdx, sp);
buffer.Emit<OpCode::MovZX, 8, false, 1, false>(rdx, rsp, 4);
buffer.Emit<OpCode::MovZX, 8, false, 2, false>(rdx, rsp, 4);
// Source: rsp, target: rbx
buffer.EmitImmediate<OpCode::Mov>(bl, static_cast<uint8_t>(1));
buffer.EmitImmediate<OpCode::Mov>(bx, static_cast<uint16_t>(1));
buffer.EmitImmediate<OpCode::Mov>(ebx, 1);
buffer.EmitImmediate<OpCode::Mov>(rbx, 1);
buffer.Emit<OpCode::Mov>(bl, spl);
buffer.Emit<OpCode::Mov>(bx, sp);
buffer.Emit<OpCode::Mov>(ebx, esp);
buffer.Emit<OpCode::Mov>(rbx, rsp);
buffer.Emit<OpCode::Mov>(bl, rsp, -4);
buffer.Emit<OpCode::Mov>(bl, rsp, 4);
buffer.Emit<OpCode::Mov>(bx, rsp, 4);
buffer.Emit<OpCode::Mov>(ebx, rsp, 4);
buffer.Emit<OpCode::Mov>(rbx, rsp, 4);
buffer.Emit<OpCode::Mov>(rbx, -4, spl);
buffer.Emit<OpCode::Mov>(rbx, 4, spl);
buffer.Emit<OpCode::Mov>(rbx, 4, sp);
buffer.Emit<OpCode::Mov>(rbx, 4, esp);
buffer.Emit<OpCode::Mov>(rbx, 4, rsp);
buffer.Emit<OpCode::MovZX>(bx, spl);
buffer.Emit<OpCode::MovZX, 2, false, 1, false>(bx, rsp, 4);
buffer.Emit<OpCode::MovZX>(ebx, spl);
buffer.Emit<OpCode::MovZX>(ebx, sp);
buffer.Emit<OpCode::MovZX, 4, false, 1, false>(ebx, rsp, 4);
buffer.Emit<OpCode::MovZX, 4, false, 2, false>(ebx, rsp, 4);
buffer.Emit<OpCode::MovZX>(rbx, spl);
buffer.Emit<OpCode::MovZX>(rbx, sp);
buffer.Emit<OpCode::MovZX, 8, false, 1, false>(rbx, rsp, 4);
buffer.Emit<OpCode::MovZX, 8, false, 2, false>(rbx, rsp, 4);
// Source: rsp, target: rsp
buffer.EmitImmediate<OpCode::Mov>(spl, static_cast<uint8_t>(1));
buffer.EmitImmediate<OpCode::Mov>(sp, static_cast<uint16_t>(1));
buffer.EmitImmediate<OpCode::Mov>(esp, 1);
buffer.EmitImmediate<OpCode::Mov>(rsp, 1);
buffer.Emit<OpCode::Mov>(spl, spl);
buffer.Emit<OpCode::Mov>(sp, sp);
buffer.Emit<OpCode::Mov>(esp, esp);
buffer.Emit<OpCode::Mov>(rsp, rsp);
buffer.Emit<OpCode::Mov>(spl, rsp, -4);
buffer.Emit<OpCode::Mov>(spl, rsp, 4);
buffer.Emit<OpCode::Mov>(sp, rsp, 4);
buffer.Emit<OpCode::Mov>(esp, rsp, 4);
buffer.Emit<OpCode::Mov>(rsp, rsp, 4);
buffer.Emit<OpCode::Mov>(rsp, -4, spl);
buffer.Emit<OpCode::Mov>(rsp, 4, spl);
buffer.Emit<OpCode::Mov>(rsp, 4, sp);
buffer.Emit<OpCode::Mov>(rsp, 4, esp);
buffer.Emit<OpCode::Mov>(rsp, 4, rsp);
buffer.Emit<OpCode::MovZX>(sp, spl);
buffer.Emit<OpCode::MovZX, 2, false, 1, false>(sp, rsp, 4);
buffer.Emit<OpCode::MovZX>(esp, spl);
buffer.Emit<OpCode::MovZX>(esp, sp);
buffer.Emit<OpCode::MovZX, 4, false, 1, false>(esp, rsp, 4);
buffer.Emit<OpCode::MovZX, 4, false, 2, false>(esp, rsp, 4);
buffer.Emit<OpCode::MovZX>(rsp, spl);
buffer.Emit<OpCode::MovZX>(rsp, sp);
buffer.Emit<OpCode::MovZX, 8, false, 1, false>(rsp, rsp, 4);
buffer.Emit<OpCode::MovZX, 8, false, 2, false>(rsp, rsp, 4);
// Source: rsp, target: rbp
buffer.EmitImmediate<OpCode::Mov>(bpl, static_cast<uint8_t>(1));
buffer.EmitImmediate<OpCode::Mov>(bp, static_cast<uint16_t>(1));
buffer.EmitImmediate<OpCode::Mov>(ebp, 1);
buffer.EmitImmediate<OpCode::Mov>(rbp, 1);
buffer.Emit<OpCode::Mov>(bpl, spl);
buffer.Emit<OpCode::Mov>(bp, sp);
buffer.Emit<OpCode::Mov>(ebp, esp);
buffer.Emit<OpCode::Mov>(rbp, rsp);
buffer.Emit<OpCode::Mov>(bpl, rsp, -4);
buffer.Emit<OpCode::Mov>(bpl, rsp, 4);
buffer.Emit<OpCode::Mov>(bp, rsp, 4);
buffer.Emit<OpCode::Mov>(ebp, rsp, 4);
buffer.Emit<OpCode::Mov>(rbp, rsp, 4);
buffer.Emit<OpCode::Mov>(rbp, -4, spl);
buffer.Emit<OpCode::Mov>(rbp, 4, spl);
buffer.Emit<OpCode::Mov>(rbp, 4, sp);
buffer.Emit<OpCode::Mov>(rbp, 4, esp);
buffer.Emit<OpCode::Mov>(rbp, 4, rsp);
buffer.Emit<OpCode::MovZX>(bp, spl);
buffer.Emit<OpCode::MovZX, 2, false, 1, false>(bp, rsp, 4);
buffer.Emit<OpCode::MovZX>(ebp, spl);
buffer.Emit<OpCode::MovZX>(ebp, sp);
buffer.Emit<OpCode::MovZX, 4, false, 1, false>(ebp, rsp, 4);
buffer.Emit<OpCode::MovZX, 4, false, 2, false>(ebp, rsp, 4);
buffer.Emit<OpCode::MovZX>(rbp, spl);
buffer.Emit<OpCode::MovZX>(rbp, sp);
buffer.Emit<OpCode::MovZX, 8, false, 1, false>(rbp, rsp, 4);
buffer.Emit<OpCode::MovZX, 8, false, 2, false>(rbp, rsp, 4);
// Source: rsp, target: rsi
buffer.EmitImmediate<OpCode::Mov>(dil, static_cast<uint8_t>(1));
buffer.EmitImmediate<OpCode::Mov>(si, static_cast<uint16_t>(1));
buffer.EmitImmediate<OpCode::Mov>(esi, 1);
buffer.EmitImmediate<OpCode::Mov>(rsi, 1);
buffer.Emit<OpCode::Mov>(dil, spl);
buffer.Emit<OpCode::Mov>(si, sp);
buffer.Emit<OpCode::Mov>(esi, esp);
buffer.Emit<OpCode::Mov>(rsi, rsp);
buffer.Emit<OpCode::Mov>(dil, rsp, -4);
buffer.Emit<OpCode::Mov>(dil, rsp, 4);
buffer.Emit<OpCode::Mov>(si, rsp, 4);
buffer.Emit<OpCode::Mov>(esi, rsp, 4);
buffer.Emit<OpCode::Mov>(rsi, rsp, 4);
buffer.Emit<OpCode::Mov>(rsi, -4, spl);
buffer.Emit<OpCode::Mov>(rsi, 4, spl);
buffer.Emit<OpCode::Mov>(rsi, 4, sp);
buffer.Emit<OpCode::Mov>(rsi, 4, esp);
buffer.Emit<OpCode::Mov>(rsi, 4, rsp);
buffer.Emit<OpCode::MovZX>(si, spl);
buffer.Emit<OpCode::MovZX, 2, false, 1, false>(si, rsp, 4);
buffer.Emit<OpCode::MovZX>(esi, spl);
buffer.Emit<OpCode::MovZX>(esi, sp);
buffer.Emit<OpCode::MovZX, 4, false, 1, false>(esi, rsp, 4);
buffer.Emit<OpCode::MovZX, 4, false, 2, false>(esi, rsp, 4);
buffer.Emit<OpCode::MovZX>(rsi, spl);
buffer.Emit<OpCode::MovZX>(rsi, sp);
buffer.Emit<OpCode::MovZX, 8, false, 1, false>(rsi, rsp, 4);
buffer.Emit<OpCode::MovZX, 8, false, 2, false>(rsi, rsp, 4);
// Source: rsp, target: rdi
buffer.EmitImmediate<OpCode::Mov>(sil, static_cast<uint8_t>(1));
buffer.EmitImmediate<OpCode::Mov>(di, static_cast<uint16_t>(1));
buffer.EmitImmediate<OpCode::Mov>(edi, 1);
buffer.EmitImmediate<OpCode::Mov>(rdi, 1);
buffer.Emit<OpCode::Mov>(sil, spl);
buffer.Emit<OpCode::Mov>(di, sp);
buffer.Emit<OpCode::Mov>(edi, esp);
buffer.Emit<OpCode::Mov>(rdi, rsp);
buffer.Emit<OpCode::Mov>(sil, rsp, -4);
buffer.Emit<OpCode::Mov>(sil, rsp, 4);
buffer.Emit<OpCode::Mov>(di, rsp, 4);
buffer.Emit<OpCode::Mov>(edi, rsp, 4);
buffer.Emit<OpCode::Mov>(rdi, rsp, 4);
buffer.Emit<OpCode::Mov>(rdi, -4, spl);
buffer.Emit<OpCode::Mov>(rdi, 4, spl);
buffer.Emit<OpCode::Mov>(rdi, 4, sp);
buffer.Emit<OpCode::Mov>(rdi, 4, esp);
buffer.Emit<OpCode::Mov>(rdi, 4, rsp);
buffer.Emit<OpCode::MovZX>(di, spl);
buffer.Emit<OpCode::MovZX, 2, false, 1, false>(di, rsp, 4);
buffer.Emit<OpCode::MovZX>(edi, spl);
buffer.Emit<OpCode::MovZX>(edi, sp);
buffer.Emit<OpCode::MovZX, 4, false, 1, false>(edi, rsp, 4);
buffer.Emit<OpCode::MovZX, 4, false, 2, false>(edi, rsp, 4);
buffer.Emit<OpCode::MovZX>(rdi, spl);
buffer.Emit<OpCode::MovZX>(rdi, sp);
buffer.Emit<OpCode::MovZX, 8, false, 1, false>(rdi, rsp, 4);
buffer.Emit<OpCode::MovZX, 8, false, 2, false>(rdi, rsp, 4);
// Source: rsp, target: r8
buffer.EmitImmediate<OpCode::Mov>(r8b, static_cast<uint8_t>(1));
buffer.EmitImmediate<OpCode::Mov>(r8w, static_cast<uint16_t>(1));
buffer.EmitImmediate<OpCode::Mov>(r8d, 1);
buffer.EmitImmediate<OpCode::Mov>(r8, 1);
buffer.Emit<OpCode::Mov>(r8b, spl);
buffer.Emit<OpCode::Mov>(r8w, sp);
buffer.Emit<OpCode::Mov>(r8d, esp);
buffer.Emit<OpCode::Mov>(r8, rsp);
buffer.Emit<OpCode::Mov>(r8b, rsp, -4);
buffer.Emit<OpCode::Mov>(r8b, rsp, 4);
buffer.Emit<OpCode::Mov>(r8w, rsp, 4);
buffer.Emit<OpCode::Mov>(r8d, rsp, 4);
buffer.Emit<OpCode::Mov>(r8, rsp, 4);
buffer.Emit<OpCode::Mov>(r8, -4, spl);
buffer.Emit<OpCode::Mov>(r8, 4, spl);
buffer.Emit<OpCode::Mov>(r8, 4, sp);
buffer.Emit<OpCode::Mov>(r8, 4, esp);
buffer.Emit<OpCode::Mov>(r8, 4, rsp);
buffer.Emit<OpCode::MovZX>(r8w, spl);
buffer.Emit<OpCode::MovZX, 2, false, 1, false>(r8w, rsp, 4);
buffer.Emit<OpCode::MovZX>(r8d, spl);
buffer.Emit<OpCode::MovZX>(r8d, sp);
buffer.Emit<OpCode::MovZX, 4, false, 1, false>(r8d, rsp, 4);
buffer.Emit<OpCode::MovZX, 4, false, 2, false>(r8d, rsp, 4);
buffer.Emit<OpCode::MovZX>(r8, spl);
buffer.Emit<OpCode::MovZX>(r8, sp);
buffer.Emit<OpCode::MovZX, 8, false, 1, false>(r8, rsp, 4);
buffer.Emit<OpCode::MovZX, 8, false, 2, false>(r8, rsp, 4);
// Source: rsp, target: r9
buffer.EmitImmediate<OpCode::Mov>(r9b, static_cast<uint8_t>(1));
buffer.EmitImmediate<OpCode::Mov>(r9w, static_cast<uint16_t>(1));
buffer.EmitImmediate<OpCode::Mov>(r9d, 1);
buffer.EmitImmediate<OpCode::Mov>(r9, 1);
buffer.Emit<OpCode::Mov>(r9b, spl);
buffer.Emit<OpCode::Mov>(r9w, sp);
buffer.Emit<OpCode::Mov>(r9d, esp);
buffer.Emit<OpCode::Mov>(r9, rsp);
buffer.Emit<OpCode::Mov>(r9b, rsp, -4);
buffer.Emit<OpCode::Mov>(r9b, rsp, 4);
buffer.Emit<OpCode::Mov>(r9w, rsp, 4);
buffer.Emit<OpCode::Mov>(r9d, rsp, 4);
buffer.Emit<OpCode::Mov>(r9, rsp, 4);
buffer.Emit<OpCode::Mov>(r9, -4, spl);
buffer.Emit<OpCode::Mov>(r9, 4, spl);
buffer.Emit<OpCode::Mov>(r9, 4, sp);
buffer.Emit<OpCode::Mov>(r9, 4, esp);
buffer.Emit<OpCode::Mov>(r9, 4, rsp);
buffer.Emit<OpCode::MovZX>(r9w, spl);
buffer.Emit<OpCode::MovZX, 2, false, 1, false>(r9w, rsp, 4);
buffer.Emit<OpCode::MovZX>(r9d, spl);
buffer.Emit<OpCode::MovZX>(r9d, sp);
buffer.Emit<OpCode::MovZX, 4, false, 1, false>(r9d, rsp, 4);
buffer.Emit<OpCode::MovZX, 4, false, 2, false>(r9d, rsp, 4);
buffer.Emit<OpCode::MovZX>(r9, spl);
buffer.Emit<OpCode::MovZX>(r9, sp);
buffer.Emit<OpCode::MovZX, 8, false, 1, false>(r9, rsp, 4);
buffer.Emit<OpCode::MovZX, 8, false, 2, false>(r9, rsp, 4);
// Source: rsp, target: r10
buffer.EmitImmediate<OpCode::Mov>(r10b, static_cast<uint8_t>(1));
buffer.EmitImmediate<OpCode::Mov>(r10w, static_cast<uint16_t>(1));
buffer.EmitImmediate<OpCode::Mov>(r10d, 1);
buffer.EmitImmediate<OpCode::Mov>(r10, 1);
buffer.Emit<OpCode::Mov>(r10b, spl);
buffer.Emit<OpCode::Mov>(r10w, sp);
buffer.Emit<OpCode::Mov>(r10d, esp);
buffer.Emit<OpCode::Mov>(r10, rsp);
buffer.Emit<OpCode::Mov>(r10b, rsp, -4);
buffer.Emit<OpCode::Mov>(r10b, rsp, 4);
buffer.Emit<OpCode::Mov>(r10w, rsp, 4);
buffer.Emit<OpCode::Mov>(r10d, rsp, 4);
buffer.Emit<OpCode::Mov>(r10, rsp, 4);
buffer.Emit<OpCode::Mov>(r10, -4, spl);
buffer.Emit<OpCode::Mov>(r10, 4, spl);
buffer.Emit<OpCode::Mov>(r10, 4, sp);
buffer.Emit<OpCode::Mov>(r10, 4, esp);
buffer.Emit<OpCode::Mov>(r10, 4, rsp);
buffer.Emit<OpCode::MovZX>(r10w, spl);
buffer.Emit<OpCode::MovZX, 2, false, 1, false>(r10w, rsp, 4);
buffer.Emit<OpCode::MovZX>(r10d, spl);
buffer.Emit<OpCode::MovZX>(r10d, sp);
buffer.Emit<OpCode::MovZX, 4, false, 1, false>(r10d, rsp, 4);
buffer.Emit<OpCode::MovZX, 4, false, 2, false>(r10d, rsp, 4);
buffer.Emit<OpCode::MovZX>(r10, spl);
buffer.Emit<OpCode::MovZX>(r10, sp);
buffer.Emit<OpCode::MovZX, 8, false, 1, false>(r10, rsp, 4);
buffer.Emit<OpCode::MovZX, 8, false, 2, false>(r10, rsp, 4);
// Source: rsp, target: r11
buffer.EmitImmediate<OpCode::Mov>(r11b, static_cast<uint8_t>(1));
buffer.EmitImmediate<OpCode::Mov>(r11w, static_cast<uint16_t>(1));
buffer.EmitImmediate<OpCode::Mov>(r11d, 1);
buffer.EmitImmediate<OpCode::Mov>(r11, 1);
buffer.Emit<OpCode::Mov>(r11b, spl);
buffer.Emit<OpCode::Mov>(r11w, sp);
buffer.Emit<OpCode::Mov>(r11d, esp);
buffer.Emit<OpCode::Mov>(r11, rsp);
buffer.Emit<OpCode::Mov>(r11b, rsp, -4);
buffer.Emit<OpCode::Mov>(r11b, rsp, 4);
buffer.Emit<OpCode::Mov>(r11w, rsp, 4);
buffer.Emit<OpCode::Mov>(r11d, rsp, 4);
buffer.Emit<OpCode::Mov>(r11, rsp, 4);
buffer.Emit<OpCode::Mov>(r11, -4, spl);
buffer.Emit<OpCode::Mov>(r11, 4, spl);
buffer.Emit<OpCode::Mov>(r11, 4, sp);
buffer.Emit<OpCode::Mov>(r11, 4, esp);
buffer.Emit<OpCode::Mov>(r11, 4, rsp);
buffer.Emit<OpCode::MovZX>(r11w, spl);
buffer.Emit<OpCode::MovZX, 2, false, 1, false>(r11w, rsp, 4);
buffer.Emit<OpCode::MovZX>(r11d, spl);
buffer.Emit<OpCode::MovZX>(r11d, sp);
buffer.Emit<OpCode::MovZX, 4, false, 1, false>(r11d, rsp, 4);
buffer.Emit<OpCode::MovZX, 4, false, 2, false>(r11d, rsp, 4);
buffer.Emit<OpCode::MovZX>(r11, spl);
buffer.Emit<OpCode::MovZX>(r11, sp);
buffer.Emit<OpCode::MovZX, 8, false, 1, false>(r11, rsp, 4);
buffer.Emit<OpCode::MovZX, 8, false, 2, false>(r11, rsp, 4);
// Source: rsp, target: r12
buffer.EmitImmediate<OpCode::Mov>(r12b, static_cast<uint8_t>(1));
buffer.EmitImmediate<OpCode::Mov>(r12w, static_cast<uint16_t>(1));
buffer.EmitImmediate<OpCode::Mov>(r12d, 1);
buffer.EmitImmediate<OpCode::Mov>(r12, 1);
buffer.Emit<OpCode::Mov>(r12b, spl);
buffer.Emit<OpCode::Mov>(r12w, sp);
buffer.Emit<OpCode::Mov>(r12d, esp);
buffer.Emit<OpCode::Mov>(r12, rsp);
buffer.Emit<OpCode::Mov>(r12b, rsp, -4);
buffer.Emit<OpCode::Mov>(r12b, rsp, 4);
buffer.Emit<OpCode::Mov>(r12w, rsp, 4);
buffer.Emit<OpCode::Mov>(r12d, rsp, 4);
buffer.Emit<OpCode::Mov>(r12, rsp, 4);
buffer.Emit<OpCode::Mov>(r12, -4, spl);
buffer.Emit<OpCode::Mov>(r12, 4, spl);
buffer.Emit<OpCode::Mov>(r12, 4, sp);
buffer.Emit<OpCode::Mov>(r12, 4, esp);
buffer.Emit<OpCode::Mov>(r12, 4, rsp);
buffer.Emit<OpCode::MovZX>(r12w, spl);
buffer.Emit<OpCode::MovZX, 2, false, 1, false>(r12w, rsp, 4);
buffer.Emit<OpCode::MovZX>(r12d, spl);
buffer.Emit<OpCode::MovZX>(r12d, sp);
buffer.Emit<OpCode::MovZX, 4, false, 1, false>(r12d, rsp, 4);
buffer.Emit<OpCode::MovZX, 4, false, 2, false>(r12d, rsp, 4);
buffer.Emit<OpCode::MovZX>(r12, spl);
buffer.Emit<OpCode::MovZX>(r12, sp);
buffer.Emit<OpCode::MovZX, 8, false, 1, false>(r12, rsp, 4);
buffer.Emit<OpCode::MovZX, 8, false, 2, false>(r12, rsp, 4);
// Source: rsp, target: r13
buffer.EmitImmediate<OpCode::Mov>(r13b, static_cast<uint8_t>(1));
buffer.EmitImmediate<OpCode::Mov>(r13w, static_cast<uint16_t>(1));
buffer.EmitImmediate<OpCode::Mov>(r13d, 1);
buffer.EmitImmediate<OpCode::Mov>(r13, 1);
buffer.Emit<OpCode::Mov>(r13b, spl);
buffer.Emit<OpCode::Mov>(r13w, sp);
buffer.Emit<OpCode::Mov>(r13d, esp);
buffer.Emit<OpCode::Mov>(r13, rsp);
buffer.Emit<OpCode::Mov>(r13b, rsp, -4);
buffer.Emit<OpCode::Mov>(r13b, rsp, 4);
buffer.Emit<OpCode::Mov>(r13w, rsp, 4);
buffer.Emit<OpCode::Mov>(r13d, rsp, 4);
buffer.Emit<OpCode::Mov>(r13, rsp, 4);
buffer.Emit<OpCode::Mov>(r13, -4, spl);
buffer.Emit<OpCode::Mov>(r13, 4, spl);
buffer.Emit<OpCode::Mov>(r13, 4, sp);
buffer.Emit<OpCode::Mov>(r13, 4, esp);
buffer.Emit<OpCode::Mov>(r13, 4, rsp);
buffer.Emit<OpCode::MovZX>(r13w, spl);
buffer.Emit<OpCode::MovZX, 2, false, 1, false>(r13w, rsp, 4);
buffer.Emit<OpCode::MovZX>(r13d, spl);
buffer.Emit<OpCode::MovZX>(r13d, sp);
buffer.Emit<OpCode::MovZX, 4, false, 1, false>(r13d, rsp, 4);
buffer.Emit<OpCode::MovZX, 4, false, 2, false>(r13d, rsp, 4);
buffer.Emit<OpCode::MovZX>(r13, spl);
buffer.Emit<OpCode::MovZX>(r13, sp);
buffer.Emit<OpCode::MovZX, 8, false, 1, false>(r13, rsp, 4);
buffer.Emit<OpCode::MovZX, 8, false, 2, false>(r13, rsp, 4);
// Source: rsp, target: r14
buffer.EmitImmediate<OpCode::Mov>(r14b, static_cast<uint8_t>(1));
buffer.EmitImmediate<OpCode::Mov>(r14w, static_cast<uint16_t>(1));
buffer.EmitImmediate<OpCode::Mov>(r14d, 1);
buffer.EmitImmediate<OpCode::Mov>(r14, 1);
buffer.Emit<OpCode::Mov>(r14b, spl);
buffer.Emit<OpCode::Mov>(r14w, sp);
buffer.Emit<OpCode::Mov>(r14d, esp);
buffer.Emit<OpCode::Mov>(r14, rsp);
buffer.Emit<OpCode::Mov>(r14b, rsp, -4);
buffer.Emit<OpCode::Mov>(r14b, rsp, 4);
buffer.Emit<OpCode::Mov>(r14w, rsp, 4);
buffer.Emit<OpCode::Mov>(r14d, rsp, 4);
buffer.Emit<OpCode::Mov>(r14, rsp, 4);
buffer.Emit<OpCode::Mov>(r14, -4, spl);
buffer.Emit<OpCode::Mov>(r14, 4, spl);
buffer.Emit<OpCode::Mov>(r14, 4, sp);
buffer.Emit<OpCode::Mov>(r14, 4, esp);
buffer.Emit<OpCode::Mov>(r14, 4, rsp);
buffer.Emit<OpCode::MovZX>(r14w, spl);
buffer.Emit<OpCode::MovZX, 2, false, 1, false>(r14w, rsp, 4);
buffer.Emit<OpCode::MovZX>(r14d, spl);
buffer.Emit<OpCode::MovZX>(r14d, sp);
buffer.Emit<OpCode::MovZX, 4, false, 1, false>(r14d, rsp, 4);
buffer.Emit<OpCode::MovZX, 4, false, 2, false>(r14d, rsp, 4);
buffer.Emit<OpCode::MovZX>(r14, spl);
buffer.Emit<OpCode::MovZX>(r14, sp);
buffer.Emit<OpCode::MovZX, 8, false, 1, false>(r14, rsp, 4);
buffer.Emit<OpCode::MovZX, 8, false, 2, false>(r14, rsp, 4);
// Source: rsp, target: r15
buffer.EmitImmediate<OpCode::Mov>(r15b, static_cast<uint8_t>(1));
buffer.EmitImmediate<OpCode::Mov>(r15w, static_cast<uint16_t>(1));
buffer.EmitImmediate<OpCode::Mov>(r15d, 1);
buffer.EmitImmediate<OpCode::Mov>(r15, 1);
buffer.Emit<OpCode::Mov>(r15b, spl);
buffer.Emit<OpCode::Mov>(r15w, sp);
buffer.Emit<OpCode::Mov>(r15d, esp);
buffer.Emit<OpCode::Mov>(r15, rsp);
buffer.Emit<OpCode::Mov>(r15b, rsp, -4);
buffer.Emit<OpCode::Mov>(r15b, rsp, 4);
buffer.Emit<OpCode::Mov>(r15w, rsp, 4);
buffer.Emit<OpCode::Mov>(r15d, rsp, 4);
buffer.Emit<OpCode::Mov>(r15, rsp, 4);
buffer.Emit<OpCode::Mov>(r15, -4, spl);
buffer.Emit<OpCode::Mov>(r15, 4, spl);
buffer.Emit<OpCode::Mov>(r15, 4, sp);
buffer.Emit<OpCode::Mov>(r15, 4, esp);
buffer.Emit<OpCode::Mov>(r15, 4, rsp);
buffer.Emit<OpCode::MovZX>(r15w, spl);
buffer.Emit<OpCode::MovZX, 2, false, 1, false>(r15w, rsp, 4);
buffer.Emit<OpCode::MovZX>(r15d, spl);
buffer.Emit<OpCode::MovZX>(r15d, sp);
buffer.Emit<OpCode::MovZX, 4, false, 1, false>(r15d, rsp, 4);
buffer.Emit<OpCode::MovZX, 4, false, 2, false>(r15d, rsp, 4);
buffer.Emit<OpCode::MovZX>(r15, spl);
buffer.Emit<OpCode::MovZX>(r15, sp);
buffer.Emit<OpCode::MovZX, 8, false, 1, false>(r15, rsp, 4);
buffer.Emit<OpCode::MovZX, 8, false, 2, false>(r15, rsp, 4);
// Source: rbp, target: rax
buffer.EmitImmediate<OpCode::Mov>(al, static_cast<uint8_t>(1));
buffer.EmitImmediate<OpCode::Mov>(ax, static_cast<uint16_t>(1));
buffer.EmitImmediate<OpCode::Mov>(eax, 1);
buffer.EmitImmediate<OpCode::Mov>(rax, 1);
buffer.Emit<OpCode::Mov>(al, bpl);
buffer.Emit<OpCode::Mov>(ax, bp);
buffer.Emit<OpCode::Mov>(eax, ebp);
buffer.Emit<OpCode::Mov>(rax, rbp);
buffer.Emit<OpCode::Mov>(al, rbp, -4);
buffer.Emit<OpCode::Mov>(al, rbp, 4);
buffer.Emit<OpCode::Mov>(ax, rbp, 4);
buffer.Emit<OpCode::Mov>(eax, rbp, 4);
buffer.Emit<OpCode::Mov>(rax, rbp, 4);
buffer.Emit<OpCode::Mov>(rax, -4, bpl);
buffer.Emit<OpCode::Mov>(rax, 4, bpl);
buffer.Emit<OpCode::Mov>(rax, 4, bp);
buffer.Emit<OpCode::Mov>(rax, 4, ebp);
buffer.Emit<OpCode::Mov>(rax, 4, rbp);
buffer.Emit<OpCode::MovZX>(ax, bpl);
buffer.Emit<OpCode::MovZX, 2, false, 1, false>(ax, rbp, 4);
buffer.Emit<OpCode::MovZX>(eax, bpl);
buffer.Emit<OpCode::MovZX>(eax, bp);
buffer.Emit<OpCode::MovZX, 4, false, 1, false>(eax, rbp, 4);
buffer.Emit<OpCode::MovZX, 4, false, 2, false>(eax, rbp, 4);
buffer.Emit<OpCode::MovZX>(rax, bpl);
buffer.Emit<OpCode::MovZX>(rax, bp);
buffer.Emit<OpCode::MovZX, 8, false, 1, false>(rax, rbp, 4);
buffer.Emit<OpCode::MovZX, 8, false, 2, false>(rax, rbp, 4);
// Source: rbp, target: rcx
buffer.EmitImmediate<OpCode::Mov>(cl, static_cast<uint8_t>(1));
buffer.EmitImmediate<OpCode::Mov>(cx, static_cast<uint16_t>(1));
buffer.EmitImmediate<OpCode::Mov>(ecx, 1);
buffer.EmitImmediate<OpCode::Mov>(rcx, 1);
buffer.Emit<OpCode::Mov>(cl, bpl);
buffer.Emit<OpCode::Mov>(cx, bp);
buffer.Emit<OpCode::Mov>(ecx, ebp);
buffer.Emit<OpCode::Mov>(rcx, rbp);
buffer.Emit<OpCode::Mov>(cl, rbp, -4);
buffer.Emit<OpCode::Mov>(cl, rbp, 4);
buffer.Emit<OpCode::Mov>(cx, rbp, 4);
buffer.Emit<OpCode::Mov>(ecx, rbp, 4);
buffer.Emit<OpCode::Mov>(rcx, rbp, 4);
buffer.Emit<OpCode::Mov>(rcx, -4, bpl);
buffer.Emit<OpCode::Mov>(rcx, 4, bpl);
buffer.Emit<OpCode::Mov>(rcx, 4, bp);
buffer.Emit<OpCode::Mov>(rcx, 4, ebp);
buffer.Emit<OpCode::Mov>(rcx, 4, rbp);
buffer.Emit<OpCode::MovZX>(cx, bpl);
buffer.Emit<OpCode::MovZX, 2, false, 1, false>(cx, rbp, 4);
buffer.Emit<OpCode::MovZX>(ecx, bpl);
buffer.Emit<OpCode::MovZX>(ecx, bp);
buffer.Emit<OpCode::MovZX, 4, false, 1, false>(ecx, rbp, 4);
buffer.Emit<OpCode::MovZX, 4, false, 2, false>(ecx, rbp, 4);
buffer.Emit<OpCode::MovZX>(rcx, bpl);
buffer.Emit<OpCode::MovZX>(rcx, bp);
buffer.Emit<OpCode::MovZX, 8, false, 1, false>(rcx, rbp, 4);
buffer.Emit<OpCode::MovZX, 8, false, 2, false>(rcx, rbp, 4);
// Source: rbp, target: rdx
buffer.EmitImmediate<OpCode::Mov>(dl, static_cast<uint8_t>(1));
buffer.EmitImmediate<OpCode::Mov>(dx, static_cast<uint16_t>(1));
buffer.EmitImmediate<OpCode::Mov>(edx, 1);
buffer.EmitImmediate<OpCode::Mov>(rdx, 1);
buffer.Emit<OpCode::Mov>(dl, bpl);
buffer.Emit<OpCode::Mov>(dx, bp);
buffer.Emit<OpCode::Mov>(edx, ebp);
buffer.Emit<OpCode::Mov>(rdx, rbp);
buffer.Emit<OpCode::Mov>(dl, rbp, -4);
buffer.Emit<OpCode::Mov>(dl, rbp, 4);
buffer.Emit<OpCode::Mov>(dx, rbp, 4);
buffer.Emit<OpCode::Mov>(edx, rbp, 4);
buffer.Emit<OpCode::Mov>(rdx, rbp, 4);
buffer.Emit<OpCode::Mov>(rdx, -4, bpl);
buffer.Emit<OpCode::Mov>(rdx, 4, bpl);
buffer.Emit<OpCode::Mov>(rdx, 4, bp);
buffer.Emit<OpCode::Mov>(rdx, 4, ebp);
buffer.Emit<OpCode::Mov>(rdx, 4, rbp);
buffer.Emit<OpCode::MovZX>(dx, bpl);
buffer.Emit<OpCode::MovZX, 2, false, 1, false>(dx, rbp, 4);
buffer.Emit<OpCode::MovZX>(edx, bpl);
buffer.Emit<OpCode::MovZX>(edx, bp);
buffer.Emit<OpCode::MovZX, 4, false, 1, false>(edx, rbp, 4);
buffer.Emit<OpCode::MovZX, 4, false, 2, false>(edx, rbp, 4);
buffer.Emit<OpCode::MovZX>(rdx, bpl);
buffer.Emit<OpCode::MovZX>(rdx, bp);
buffer.Emit<OpCode::MovZX, 8, false, 1, false>(rdx, rbp, 4);
buffer.Emit<OpCode::MovZX, 8, false, 2, false>(rdx, rbp, 4);
// Source: rbp, target: rbx
buffer.EmitImmediate<OpCode::Mov>(bl, static_cast<uint8_t>(1));
buffer.EmitImmediate<OpCode::Mov>(bx, static_cast<uint16_t>(1));
buffer.EmitImmediate<OpCode::Mov>(ebx, 1);
buffer.EmitImmediate<OpCode::Mov>(rbx, 1);
buffer.Emit<OpCode::Mov>(bl, bpl);
buffer.Emit<OpCode::Mov>(bx, bp);
buffer.Emit<OpCode::Mov>(ebx, ebp);
buffer.Emit<OpCode::Mov>(rbx, rbp);
buffer.Emit<OpCode::Mov>(bl, rbp, -4);
buffer.Emit<OpCode::Mov>(bl, rbp, 4);
buffer.Emit<OpCode::Mov>(bx, rbp, 4);
buffer.Emit<OpCode::Mov>(ebx, rbp, 4);
buffer.Emit<OpCode::Mov>(rbx, rbp, 4);
buffer.Emit<OpCode::Mov>(rbx, -4, bpl);
buffer.Emit<OpCode::Mov>(rbx, 4, bpl);
buffer.Emit<OpCode::Mov>(rbx, 4, bp);
buffer.Emit<OpCode::Mov>(rbx, 4, ebp);
buffer.Emit<OpCode::Mov>(rbx, 4, rbp);
buffer.Emit<OpCode::MovZX>(bx, bpl);
buffer.Emit<OpCode::MovZX, 2, false, 1, false>(bx, rbp, 4);
buffer.Emit<OpCode::MovZX>(ebx, bpl);
buffer.Emit<OpCode::MovZX>(ebx, bp);
buffer.Emit<OpCode::MovZX, 4, false, 1, false>(ebx, rbp, 4);
buffer.Emit<OpCode::MovZX, 4, false, 2, false>(ebx, rbp, 4);
buffer.Emit<OpCode::MovZX>(rbx, bpl);
buffer.Emit<OpCode::MovZX>(rbx, bp);
buffer.Emit<OpCode::MovZX, 8, false, 1, false>(rbx, rbp, 4);
buffer.Emit<OpCode::MovZX, 8, false, 2, false>(rbx, rbp, 4);
// Source: rbp, target: rsp
buffer.EmitImmediate<OpCode::Mov>(spl, static_cast<uint8_t>(1));
buffer.EmitImmediate<OpCode::Mov>(sp, static_cast<uint16_t>(1));
buffer.EmitImmediate<OpCode::Mov>(esp, 1);
buffer.EmitImmediate<OpCode::Mov>(rsp, 1);
buffer.Emit<OpCode::Mov>(spl, bpl);
buffer.Emit<OpCode::Mov>(sp, bp);
buffer.Emit<OpCode::Mov>(esp, ebp);
buffer.Emit<OpCode::Mov>(rsp, rbp);
buffer.Emit<OpCode::Mov>(spl, rbp, -4);
buffer.Emit<OpCode::Mov>(spl, rbp, 4);
buffer.Emit<OpCode::Mov>(sp, rbp, 4);
buffer.Emit<OpCode::Mov>(esp, rbp, 4);
buffer.Emit<OpCode::Mov>(rsp, rbp, 4);
buffer.Emit<OpCode::Mov>(rsp, -4, bpl);
buffer.Emit<OpCode::Mov>(rsp, 4, bpl);
buffer.Emit<OpCode::Mov>(rsp, 4, bp);
buffer.Emit<OpCode::Mov>(rsp, 4, ebp);
buffer.Emit<OpCode::Mov>(rsp, 4, rbp);
buffer.Emit<OpCode::MovZX>(sp, bpl);
buffer.Emit<OpCode::MovZX, 2, false, 1, false>(sp, rbp, 4);
buffer.Emit<OpCode::MovZX>(esp, bpl);
buffer.Emit<OpCode::MovZX>(esp, bp);
buffer.Emit<OpCode::MovZX, 4, false, 1, false>(esp, rbp, 4);
buffer.Emit<OpCode::MovZX, 4, false, 2, false>(esp, rbp, 4);
buffer.Emit<OpCode::MovZX>(rsp, bpl);
buffer.Emit<OpCode::MovZX>(rsp, bp);
buffer.Emit<OpCode::MovZX, 8, false, 1, false>(rsp, rbp, 4);
buffer.Emit<OpCode::MovZX, 8, false, 2, false>(rsp, rbp, 4);
// Source: rbp, target: rbp
buffer.EmitImmediate<OpCode::Mov>(bpl, static_cast<uint8_t>(1));
buffer.EmitImmediate<OpCode::Mov>(bp, static_cast<uint16_t>(1));
buffer.EmitImmediate<OpCode::Mov>(ebp, 1);
buffer.EmitImmediate<OpCode::Mov>(rbp, 1);
buffer.Emit<OpCode::Mov>(bpl, bpl);
buffer.Emit<OpCode::Mov>(bp, bp);
buffer.Emit<OpCode::Mov>(ebp, ebp);
buffer.Emit<OpCode::Mov>(rbp, rbp);
buffer.Emit<OpCode::Mov>(bpl, rbp, -4);
buffer.Emit<OpCode::Mov>(bpl, rbp, 4);
buffer.Emit<OpCode::Mov>(bp, rbp, 4);
buffer.Emit<OpCode::Mov>(ebp, rbp, 4);
buffer.Emit<OpCode::Mov>(rbp, rbp, 4);
buffer.Emit<OpCode::Mov>(rbp, -4, bpl);
buffer.Emit<OpCode::Mov>(rbp, 4, bpl);
buffer.Emit<OpCode::Mov>(rbp, 4, bp);
buffer.Emit<OpCode::Mov>(rbp, 4, ebp);
buffer.Emit<OpCode::Mov>(rbp, 4, rbp);
buffer.Emit<OpCode::MovZX>(bp, bpl);
buffer.Emit<OpCode::MovZX, 2, false, 1, false>(bp, rbp, 4);
buffer.Emit<OpCode::MovZX>(ebp, bpl);
buffer.Emit<OpCode::MovZX>(ebp, bp);
buffer.Emit<OpCode::MovZX, 4, false, 1, false>(ebp, rbp, 4);
buffer.Emit<OpCode::MovZX, 4, false, 2, false>(ebp, rbp, 4);
buffer.Emit<OpCode::MovZX>(rbp, bpl);
buffer.Emit<OpCode::MovZX>(rbp, bp);
buffer.Emit<OpCode::MovZX, 8, false, 1, false>(rbp, rbp, 4);
buffer.Emit<OpCode::MovZX, 8, false, 2, false>(rbp, rbp, 4);
// Source: rbp, target: rsi
buffer.EmitImmediate<OpCode::Mov>(dil, static_cast<uint8_t>(1));
buffer.EmitImmediate<OpCode::Mov>(si, static_cast<uint16_t>(1));
buffer.EmitImmediate<OpCode::Mov>(esi, 1);
buffer.EmitImmediate<OpCode::Mov>(rsi, 1);
buffer.Emit<OpCode::Mov>(dil, bpl);
buffer.Emit<OpCode::Mov>(si, bp);
buffer.Emit<OpCode::Mov>(esi, ebp);
buffer.Emit<OpCode::Mov>(rsi, rbp);
buffer.Emit<OpCode::Mov>(dil, rbp, -4);
buffer.Emit<OpCode::Mov>(dil, rbp, 4);
buffer.Emit<OpCode::Mov>(si, rbp, 4);
buffer.Emit<OpCode::Mov>(esi, rbp, 4);
buffer.Emit<OpCode::Mov>(rsi, rbp, 4);
buffer.Emit<OpCode::Mov>(rsi, -4, bpl);
buffer.Emit<OpCode::Mov>(rsi, 4, bpl);
buffer.Emit<OpCode::Mov>(rsi, 4, bp);
buffer.Emit<OpCode::Mov>(rsi, 4, ebp);
buffer.Emit<OpCode::Mov>(rsi, 4, rbp);
buffer.Emit<OpCode::MovZX>(si, bpl);
buffer.Emit<OpCode::MovZX, 2, false, 1, false>(si, rbp, 4);
buffer.Emit<OpCode::MovZX>(esi, bpl);
buffer.Emit<OpCode::MovZX>(esi, bp);
buffer.Emit<OpCode::MovZX, 4, false, 1, false>(esi, rbp, 4);
buffer.Emit<OpCode::MovZX, 4, false, 2, false>(esi, rbp, 4);
buffer.Emit<OpCode::MovZX>(rsi, bpl);
buffer.Emit<OpCode::MovZX>(rsi, bp);
buffer.Emit<OpCode::MovZX, 8, false, 1, false>(rsi, rbp, 4);
buffer.Emit<OpCode::MovZX, 8, false, 2, false>(rsi, rbp, 4);
// Source: rbp, target: rdi
buffer.EmitImmediate<OpCode::Mov>(sil, static_cast<uint8_t>(1));
buffer.EmitImmediate<OpCode::Mov>(di, static_cast<uint16_t>(1));
buffer.EmitImmediate<OpCode::Mov>(edi, 1);
buffer.EmitImmediate<OpCode::Mov>(rdi, 1);
buffer.Emit<OpCode::Mov>(sil, bpl);
buffer.Emit<OpCode::Mov>(di, bp);
buffer.Emit<OpCode::Mov>(edi, ebp);
buffer.Emit<OpCode::Mov>(rdi, rbp);
buffer.Emit<OpCode::Mov>(sil, rbp, -4);
buffer.Emit<OpCode::Mov>(sil, rbp, 4);
buffer.Emit<OpCode::Mov>(di, rbp, 4);
buffer.Emit<OpCode::Mov>(edi, rbp, 4);
buffer.Emit<OpCode::Mov>(rdi, rbp, 4);
buffer.Emit<OpCode::Mov>(rdi, -4, bpl);
buffer.Emit<OpCode::Mov>(rdi, 4, bpl);
buffer.Emit<OpCode::Mov>(rdi, 4, bp);
buffer.Emit<OpCode::Mov>(rdi, 4, ebp);
buffer.Emit<OpCode::Mov>(rdi, 4, rbp);
buffer.Emit<OpCode::MovZX>(di, bpl);
buffer.Emit<OpCode::MovZX, 2, false, 1, false>(di, rbp, 4);
buffer.Emit<OpCode::MovZX>(edi, bpl);
buffer.Emit<OpCode::MovZX>(edi, bp);
buffer.Emit<OpCode::MovZX, 4, false, 1, false>(edi, rbp, 4);
buffer.Emit<OpCode::MovZX, 4, false, 2, false>(edi, rbp, 4);
buffer.Emit<OpCode::MovZX>(rdi, bpl);
buffer.Emit<OpCode::MovZX>(rdi, bp);
buffer.Emit<OpCode::MovZX, 8, false, 1, false>(rdi, rbp, 4);
buffer.Emit<OpCode::MovZX, 8, false, 2, false>(rdi, rbp, 4);
// Source: rbp, target: r8
buffer.EmitImmediate<OpCode::Mov>(r8b, static_cast<uint8_t>(1));
buffer.EmitImmediate<OpCode::Mov>(r8w, static_cast<uint16_t>(1));
buffer.EmitImmediate<OpCode::Mov>(r8d, 1);
buffer.EmitImmediate<OpCode::Mov>(r8, 1);
buffer.Emit<OpCode::Mov>(r8b, bpl);
buffer.Emit<OpCode::Mov>(r8w, bp);
buffer.Emit<OpCode::Mov>(r8d, ebp);
buffer.Emit<OpCode::Mov>(r8, rbp);
buffer.Emit<OpCode::Mov>(r8b, rbp, -4);
buffer.Emit<OpCode::Mov>(r8b, rbp, 4);
buffer.Emit<OpCode::Mov>(r8w, rbp, 4);
buffer.Emit<OpCode::Mov>(r8d, rbp, 4);
buffer.Emit<OpCode::Mov>(r8, rbp, 4);
buffer.Emit<OpCode::Mov>(r8, -4, bpl);
buffer.Emit<OpCode::Mov>(r8, 4, bpl);
buffer.Emit<OpCode::Mov>(r8, 4, bp);
buffer.Emit<OpCode::Mov>(r8, 4, ebp);
buffer.Emit<OpCode::Mov>(r8, 4, rbp);
buffer.Emit<OpCode::MovZX>(r8w, bpl);
buffer.Emit<OpCode::MovZX, 2, false, 1, false>(r8w, rbp, 4);
buffer.Emit<OpCode::MovZX>(r8d, bpl);
buffer.Emit<OpCode::MovZX>(r8d, bp);
buffer.Emit<OpCode::MovZX, 4, false, 1, false>(r8d, rbp, 4);
buffer.Emit<OpCode::MovZX, 4, false, 2, false>(r8d, rbp, 4);
buffer.Emit<OpCode::MovZX>(r8, bpl);
buffer.Emit<OpCode::MovZX>(r8, bp);
buffer.Emit<OpCode::MovZX, 8, false, 1, false>(r8, rbp, 4);
buffer.Emit<OpCode::MovZX, 8, false, 2, false>(r8, rbp, 4);
// Source: rbp, target: r9
buffer.EmitImmediate<OpCode::Mov>(r9b, static_cast<uint8_t>(1));
buffer.EmitImmediate<OpCode::Mov>(r9w, static_cast<uint16_t>(1));
buffer.EmitImmediate<OpCode::Mov>(r9d, 1);
buffer.EmitImmediate<OpCode::Mov>(r9, 1);
buffer.Emit<OpCode::Mov>(r9b, bpl);
buffer.Emit<OpCode::Mov>(r9w, bp);
buffer.Emit<OpCode::Mov>(r9d, ebp);
buffer.Emit<OpCode::Mov>(r9, rbp);
buffer.Emit<OpCode::Mov>(r9b, rbp, -4);
buffer.Emit<OpCode::Mov>(r9b, rbp, 4);
buffer.Emit<OpCode::Mov>(r9w, rbp, 4);
buffer.Emit<OpCode::Mov>(r9d, rbp, 4);
buffer.Emit<OpCode::Mov>(r9, rbp, 4);
buffer.Emit<OpCode::Mov>(r9, -4, bpl);
buffer.Emit<OpCode::Mov>(r9, 4, bpl);
buffer.Emit<OpCode::Mov>(r9, 4, bp);
buffer.Emit<OpCode::Mov>(r9, 4, ebp);
buffer.Emit<OpCode::Mov>(r9, 4, rbp);
buffer.Emit<OpCode::MovZX>(r9w, bpl);
buffer.Emit<OpCode::MovZX, 2, false, 1, false>(r9w, rbp, 4);
buffer.Emit<OpCode::MovZX>(r9d, bpl);
buffer.Emit<OpCode::MovZX>(r9d, bp);
buffer.Emit<OpCode::MovZX, 4, false, 1, false>(r9d, rbp, 4);
buffer.Emit<OpCode::MovZX, 4, false, 2, false>(r9d, rbp, 4);
buffer.Emit<OpCode::MovZX>(r9, bpl);
buffer.Emit<OpCode::MovZX>(r9, bp);
buffer.Emit<OpCode::MovZX, 8, false, 1, false>(r9, rbp, 4);
buffer.Emit<OpCode::MovZX, 8, false, 2, false>(r9, rbp, 4);
// Source: rbp, target: r10
buffer.EmitImmediate<OpCode::Mov>(r10b, static_cast<uint8_t>(1));
buffer.EmitImmediate<OpCode::Mov>(r10w, static_cast<uint16_t>(1));
buffer.EmitImmediate<OpCode::Mov>(r10d, 1);
buffer.EmitImmediate<OpCode::Mov>(r10, 1);
buffer.Emit<OpCode::Mov>(r10b, bpl);
buffer.Emit<OpCode::Mov>(r10w, bp);
buffer.Emit<OpCode::Mov>(r10d, ebp);
buffer.Emit<OpCode::Mov>(r10, rbp);
buffer.Emit<OpCode::Mov>(r10b, rbp, -4);
buffer.Emit<OpCode::Mov>(r10b, rbp, 4);
buffer.Emit<OpCode::Mov>(r10w, rbp, 4);
buffer.Emit<OpCode::Mov>(r10d, rbp, 4);
buffer.Emit<OpCode::Mov>(r10, rbp, 4);
buffer.Emit<OpCode::Mov>(r10, -4, bpl);
buffer.Emit<OpCode::Mov>(r10, 4, bpl);
buffer.Emit<OpCode::Mov>(r10, 4, bp);
buffer.Emit<OpCode::Mov>(r10, 4, ebp);
buffer.Emit<OpCode::Mov>(r10, 4, rbp);
buffer.Emit<OpCode::MovZX>(r10w, bpl);
buffer.Emit<OpCode::MovZX, 2, false, 1, false>(r10w, rbp, 4);
buffer.Emit<OpCode::MovZX>(r10d, bpl);
buffer.Emit<OpCode::MovZX>(r10d, bp);
buffer.Emit<OpCode::MovZX, 4, false, 1, false>(r10d, rbp, 4);
buffer.Emit<OpCode::MovZX, 4, false, 2, false>(r10d, rbp, 4);
buffer.Emit<OpCode::MovZX>(r10, bpl);
buffer.Emit<OpCode::MovZX>(r10, bp);
buffer.Emit<OpCode::MovZX, 8, false, 1, false>(r10, rbp, 4);
buffer.Emit<OpCode::MovZX, 8, false, 2, false>(r10, rbp, 4);
// Source: rbp, target: r11
buffer.EmitImmediate<OpCode::Mov>(r11b, static_cast<uint8_t>(1));
buffer.EmitImmediate<OpCode::Mov>(r11w, static_cast<uint16_t>(1));
buffer.EmitImmediate<OpCode::Mov>(r11d, 1);
buffer.EmitImmediate<OpCode::Mov>(r11, 1);
buffer.Emit<OpCode::Mov>(r11b, bpl);
buffer.Emit<OpCode::Mov>(r11w, bp);
buffer.Emit<OpCode::Mov>(r11d, ebp);
buffer.Emit<OpCode::Mov>(r11, rbp);
buffer.Emit<OpCode::Mov>(r11b, rbp, -4);
buffer.Emit<OpCode::Mov>(r11b, rbp, 4);
buffer.Emit<OpCode::Mov>(r11w, rbp, 4);
buffer.Emit<OpCode::Mov>(r11d, rbp, 4);
buffer.Emit<OpCode::Mov>(r11, rbp, 4);
buffer.Emit<OpCode::Mov>(r11, -4, bpl);
buffer.Emit<OpCode::Mov>(r11, 4, bpl);
buffer.Emit<OpCode::Mov>(r11, 4, bp);
buffer.Emit<OpCode::Mov>(r11, 4, ebp);
buffer.Emit<OpCode::Mov>(r11, 4, rbp);
buffer.Emit<OpCode::MovZX>(r11w, bpl);
buffer.Emit<OpCode::MovZX, 2, false, 1, false>(r11w, rbp, 4);
buffer.Emit<OpCode::MovZX>(r11d, bpl);
buffer.Emit<OpCode::MovZX>(r11d, bp);
buffer.Emit<OpCode::MovZX, 4, false, 1, false>(r11d, rbp, 4);
buffer.Emit<OpCode::MovZX, 4, false, 2, false>(r11d, rbp, 4);
buffer.Emit<OpCode::MovZX>(r11, bpl);
buffer.Emit<OpCode::MovZX>(r11, bp);
buffer.Emit<OpCode::MovZX, 8, false, 1, false>(r11, rbp, 4);
buffer.Emit<OpCode::MovZX, 8, false, 2, false>(r11, rbp, 4);
// Source: rbp, target: r12
buffer.EmitImmediate<OpCode::Mov>(r12b, static_cast<uint8_t>(1));
buffer.EmitImmediate<OpCode::Mov>(r12w, static_cast<uint16_t>(1));
buffer.EmitImmediate<OpCode::Mov>(r12d, 1);
buffer.EmitImmediate<OpCode::Mov>(r12, 1);
buffer.Emit<OpCode::Mov>(r12b, bpl);
buffer.Emit<OpCode::Mov>(r12w, bp);
buffer.Emit<OpCode::Mov>(r12d, ebp);
buffer.Emit<OpCode::Mov>(r12, rbp);
buffer.Emit<OpCode::Mov>(r12b, rbp, -4);
buffer.Emit<OpCode::Mov>(r12b, rbp, 4);
buffer.Emit<OpCode::Mov>(r12w, rbp, 4);
buffer.Emit<OpCode::Mov>(r12d, rbp, 4);
buffer.Emit<OpCode::Mov>(r12, rbp, 4);
buffer.Emit<OpCode::Mov>(r12, -4, bpl);
buffer.Emit<OpCode::Mov>(r12, 4, bpl);
buffer.Emit<OpCode::Mov>(r12, 4, bp);
buffer.Emit<OpCode::Mov>(r12, 4, ebp);
buffer.Emit<OpCode::Mov>(r12, 4, rbp);
buffer.Emit<OpCode::MovZX>(r12w, bpl);
buffer.Emit<OpCode::MovZX, 2, false, 1, false>(r12w, rbp, 4);
buffer.Emit<OpCode::MovZX>(r12d, bpl);
buffer.Emit<OpCode::MovZX>(r12d, bp);
buffer.Emit<OpCode::MovZX, 4, false, 1, false>(r12d, rbp, 4);
buffer.Emit<OpCode::MovZX, 4, false, 2, false>(r12d, rbp, 4);
buffer.Emit<OpCode::MovZX>(r12, bpl);
buffer.Emit<OpCode::MovZX>(r12, bp);
buffer.Emit<OpCode::MovZX, 8, false, 1, false>(r12, rbp, 4);
buffer.Emit<OpCode::MovZX, 8, false, 2, false>(r12, rbp, 4);
// Source: rbp, target: r13
buffer.EmitImmediate<OpCode::Mov>(r13b, static_cast<uint8_t>(1));
buffer.EmitImmediate<OpCode::Mov>(r13w, static_cast<uint16_t>(1));
buffer.EmitImmediate<OpCode::Mov>(r13d, 1);
buffer.EmitImmediate<OpCode::Mov>(r13, 1);
buffer.Emit<OpCode::Mov>(r13b, bpl);
buffer.Emit<OpCode::Mov>(r13w, bp);
buffer.Emit<OpCode::Mov>(r13d, ebp);
buffer.Emit<OpCode::Mov>(r13, rbp);
buffer.Emit<OpCode::Mov>(r13b, rbp, -4);
buffer.Emit<OpCode::Mov>(r13b, rbp, 4);
buffer.Emit<OpCode::Mov>(r13w, rbp, 4);
buffer.Emit<OpCode::Mov>(r13d, rbp, 4);
buffer.Emit<OpCode::Mov>(r13, rbp, 4);
buffer.Emit<OpCode::Mov>(r13, -4, bpl);
buffer.Emit<OpCode::Mov>(r13, 4, bpl);
buffer.Emit<OpCode::Mov>(r13, 4, bp);
buffer.Emit<OpCode::Mov>(r13, 4, ebp);
buffer.Emit<OpCode::Mov>(r13, 4, rbp);
buffer.Emit<OpCode::MovZX>(r13w, bpl);
buffer.Emit<OpCode::MovZX, 2, false, 1, false>(r13w, rbp, 4);
buffer.Emit<OpCode::MovZX>(r13d, bpl);
buffer.Emit<OpCode::MovZX>(r13d, bp);
buffer.Emit<OpCode::MovZX, 4, false, 1, false>(r13d, rbp, 4);
buffer.Emit<OpCode::MovZX, 4, false, 2, false>(r13d, rbp, 4);
buffer.Emit<OpCode::MovZX>(r13, bpl);
buffer.Emit<OpCode::MovZX>(r13, bp);
buffer.Emit<OpCode::MovZX, 8, false, 1, false>(r13, rbp, 4);
buffer.Emit<OpCode::MovZX, 8, false, 2, false>(r13, rbp, 4);
// Source: rbp, target: r14
buffer.EmitImmediate<OpCode::Mov>(r14b, static_cast<uint8_t>(1));
buffer.EmitImmediate<OpCode::Mov>(r14w, static_cast<uint16_t>(1));
buffer.EmitImmediate<OpCode::Mov>(r14d, 1);
buffer.EmitImmediate<OpCode::Mov>(r14, 1);
buffer.Emit<OpCode::Mov>(r14b, bpl);
buffer.Emit<OpCode::Mov>(r14w, bp);
buffer.Emit<OpCode::Mov>(r14d, ebp);
buffer.Emit<OpCode::Mov>(r14, rbp);
buffer.Emit<OpCode::Mov>(r14b, rbp, -4);
buffer.Emit<OpCode::Mov>(r14b, rbp, 4);
buffer.Emit<OpCode::Mov>(r14w, rbp, 4);
buffer.Emit<OpCode::Mov>(r14d, rbp, 4);
buffer.Emit<OpCode::Mov>(r14, rbp, 4);
buffer.Emit<OpCode::Mov>(r14, -4, bpl);
buffer.Emit<OpCode::Mov>(r14, 4, bpl);
buffer.Emit<OpCode::Mov>(r14, 4, bp);
buffer.Emit<OpCode::Mov>(r14, 4, ebp);
buffer.Emit<OpCode::Mov>(r14, 4, rbp);
buffer.Emit<OpCode::MovZX>(r14w, bpl);
buffer.Emit<OpCode::MovZX, 2, false, 1, false>(r14w, rbp, 4);
buffer.Emit<OpCode::MovZX>(r14d, bpl);
buffer.Emit<OpCode::MovZX>(r14d, bp);
buffer.Emit<OpCode::MovZX, 4, false, 1, false>(r14d, rbp, 4);
buffer.Emit<OpCode::MovZX, 4, false, 2, false>(r14d, rbp, 4);
buffer.Emit<OpCode::MovZX>(r14, bpl);
buffer.Emit<OpCode::MovZX>(r14, bp);
buffer.Emit<OpCode::MovZX, 8, false, 1, false>(r14, rbp, 4);
buffer.Emit<OpCode::MovZX, 8, false, 2, false>(r14, rbp, 4);
// Source: rbp, target: r15
buffer.EmitImmediate<OpCode::Mov>(r15b, static_cast<uint8_t>(1));
buffer.EmitImmediate<OpCode::Mov>(r15w, static_cast<uint16_t>(1));
buffer.EmitImmediate<OpCode::Mov>(r15d, 1);
buffer.EmitImmediate<OpCode::Mov>(r15, 1);
buffer.Emit<OpCode::Mov>(r15b, bpl);
buffer.Emit<OpCode::Mov>(r15w, bp);
buffer.Emit<OpCode::Mov>(r15d, ebp);
buffer.Emit<OpCode::Mov>(r15, rbp);
buffer.Emit<OpCode::Mov>(r15b, rbp, -4);
buffer.Emit<OpCode::Mov>(r15b, rbp, 4);
buffer.Emit<OpCode::Mov>(r15w, rbp, 4);
buffer.Emit<OpCode::Mov>(r15d, rbp, 4);
buffer.Emit<OpCode::Mov>(r15, rbp, 4);
buffer.Emit<OpCode::Mov>(r15, -4, bpl);
buffer.Emit<OpCode::Mov>(r15, 4, bpl);
buffer.Emit<OpCode::Mov>(r15, 4, bp);
buffer.Emit<OpCode::Mov>(r15, 4, ebp);
buffer.Emit<OpCode::Mov>(r15, 4, rbp);
buffer.Emit<OpCode::MovZX>(r15w, bpl);
buffer.Emit<OpCode::MovZX, 2, false, 1, false>(r15w, rbp, 4);
buffer.Emit<OpCode::MovZX>(r15d, bpl);
buffer.Emit<OpCode::MovZX>(r15d, bp);
buffer.Emit<OpCode::MovZX, 4, false, 1, false>(r15d, rbp, 4);
buffer.Emit<OpCode::MovZX, 4, false, 2, false>(r15d, rbp, 4);
buffer.Emit<OpCode::MovZX>(r15, bpl);
buffer.Emit<OpCode::MovZX>(r15, bp);
buffer.Emit<OpCode::MovZX, 8, false, 1, false>(r15, rbp, 4);
buffer.Emit<OpCode::MovZX, 8, false, 2, false>(r15, rbp, 4);
// Source: rsi, target: rax
buffer.EmitImmediate<OpCode::Mov>(al, static_cast<uint8_t>(1));
buffer.EmitImmediate<OpCode::Mov>(ax, static_cast<uint16_t>(1));
buffer.EmitImmediate<OpCode::Mov>(eax, 1);
buffer.EmitImmediate<OpCode::Mov>(rax, 1);
buffer.Emit<OpCode::Mov>(al, dil);
buffer.Emit<OpCode::Mov>(ax, si);
buffer.Emit<OpCode::Mov>(eax, esi);
buffer.Emit<OpCode::Mov>(rax, rsi);
buffer.Emit<OpCode::Mov>(al, rsi, -4);
buffer.Emit<OpCode::Mov>(al, rsi, 4);
buffer.Emit<OpCode::Mov>(ax, rsi, 4);
buffer.Emit<OpCode::Mov>(eax, rsi, 4);
buffer.Emit<OpCode::Mov>(rax, rsi, 4);
buffer.Emit<OpCode::Mov>(rax, -4, dil);
buffer.Emit<OpCode::Mov>(rax, 4, dil);
buffer.Emit<OpCode::Mov>(rax, 4, si);
buffer.Emit<OpCode::Mov>(rax, 4, esi);
buffer.Emit<OpCode::Mov>(rax, 4, rsi);
buffer.Emit<OpCode::MovZX>(ax, dil);
buffer.Emit<OpCode::MovZX, 2, false, 1, false>(ax, rsi, 4);
buffer.Emit<OpCode::MovZX>(eax, dil);
buffer.Emit<OpCode::MovZX>(eax, si);
buffer.Emit<OpCode::MovZX, 4, false, 1, false>(eax, rsi, 4);
buffer.Emit<OpCode::MovZX, 4, false, 2, false>(eax, rsi, 4);
buffer.Emit<OpCode::MovZX>(rax, dil);
buffer.Emit<OpCode::MovZX>(rax, si);
buffer.Emit<OpCode::MovZX, 8, false, 1, false>(rax, rsi, 4);
buffer.Emit<OpCode::MovZX, 8, false, 2, false>(rax, rsi, 4);
// Source: rsi, target: rcx
buffer.EmitImmediate<OpCode::Mov>(cl, static_cast<uint8_t>(1));
buffer.EmitImmediate<OpCode::Mov>(cx, static_cast<uint16_t>(1));
buffer.EmitImmediate<OpCode::Mov>(ecx, 1);
buffer.EmitImmediate<OpCode::Mov>(rcx, 1);
buffer.Emit<OpCode::Mov>(cl, dil);
buffer.Emit<OpCode::Mov>(cx, si);
buffer.Emit<OpCode::Mov>(ecx, esi);
buffer.Emit<OpCode::Mov>(rcx, rsi);
buffer.Emit<OpCode::Mov>(cl, rsi, -4);
buffer.Emit<OpCode::Mov>(cl, rsi, 4);
buffer.Emit<OpCode::Mov>(cx, rsi, 4);
buffer.Emit<OpCode::Mov>(ecx, rsi, 4);
buffer.Emit<OpCode::Mov>(rcx, rsi, 4);
buffer.Emit<OpCode::Mov>(rcx, -4, dil);
buffer.Emit<OpCode::Mov>(rcx, 4, dil);
buffer.Emit<OpCode::Mov>(rcx, 4, si);
buffer.Emit<OpCode::Mov>(rcx, 4, esi);
buffer.Emit<OpCode::Mov>(rcx, 4, rsi);
buffer.Emit<OpCode::MovZX>(cx, dil);
buffer.Emit<OpCode::MovZX, 2, false, 1, false>(cx, rsi, 4);
buffer.Emit<OpCode::MovZX>(ecx, dil);
buffer.Emit<OpCode::MovZX>(ecx, si);
buffer.Emit<OpCode::MovZX, 4, false, 1, false>(ecx, rsi, 4);
buffer.Emit<OpCode::MovZX, 4, false, 2, false>(ecx, rsi, 4);
buffer.Emit<OpCode::MovZX>(rcx, dil);
buffer.Emit<OpCode::MovZX>(rcx, si);
buffer.Emit<OpCode::MovZX, 8, false, 1, false>(rcx, rsi, 4);
buffer.Emit<OpCode::MovZX, 8, false, 2, false>(rcx, rsi, 4);
// Source: rsi, target: rdx
buffer.EmitImmediate<OpCode::Mov>(dl, static_cast<uint8_t>(1));
buffer.EmitImmediate<OpCode::Mov>(dx, static_cast<uint16_t>(1));
buffer.EmitImmediate<OpCode::Mov>(edx, 1);
buffer.EmitImmediate<OpCode::Mov>(rdx, 1);
buffer.Emit<OpCode::Mov>(dl, dil);
buffer.Emit<OpCode::Mov>(dx, si);
buffer.Emit<OpCode::Mov>(edx, esi);
buffer.Emit<OpCode::Mov>(rdx, rsi);
buffer.Emit<OpCode::Mov>(dl, rsi, -4);
buffer.Emit<OpCode::Mov>(dl, rsi, 4);
buffer.Emit<OpCode::Mov>(dx, rsi, 4);
buffer.Emit<OpCode::Mov>(edx, rsi, 4);
buffer.Emit<OpCode::Mov>(rdx, rsi, 4);
buffer.Emit<OpCode::Mov>(rdx, -4, dil);
buffer.Emit<OpCode::Mov>(rdx, 4, dil);
buffer.Emit<OpCode::Mov>(rdx, 4, si);
buffer.Emit<OpCode::Mov>(rdx, 4, esi);
buffer.Emit<OpCode::Mov>(rdx, 4, rsi);
buffer.Emit<OpCode::MovZX>(dx, dil);
buffer.Emit<OpCode::MovZX, 2, false, 1, false>(dx, rsi, 4);
buffer.Emit<OpCode::MovZX>(edx, dil);
buffer.Emit<OpCode::MovZX>(edx, si);
buffer.Emit<OpCode::MovZX, 4, false, 1, false>(edx, rsi, 4);
buffer.Emit<OpCode::MovZX, 4, false, 2, false>(edx, rsi, 4);
buffer.Emit<OpCode::MovZX>(rdx, dil);
buffer.Emit<OpCode::MovZX>(rdx, si);
buffer.Emit<OpCode::MovZX, 8, false, 1, false>(rdx, rsi, 4);
buffer.Emit<OpCode::MovZX, 8, false, 2, false>(rdx, rsi, 4);
// Source: rsi, target: rbx
buffer.EmitImmediate<OpCode::Mov>(bl, static_cast<uint8_t>(1));
buffer.EmitImmediate<OpCode::Mov>(bx, static_cast<uint16_t>(1));
buffer.EmitImmediate<OpCode::Mov>(ebx, 1);
buffer.EmitImmediate<OpCode::Mov>(rbx, 1);
buffer.Emit<OpCode::Mov>(bl, dil);
buffer.Emit<OpCode::Mov>(bx, si);
buffer.Emit<OpCode::Mov>(ebx, esi);
buffer.Emit<OpCode::Mov>(rbx, rsi);
buffer.Emit<OpCode::Mov>(bl, rsi, -4);
buffer.Emit<OpCode::Mov>(bl, rsi, 4);
buffer.Emit<OpCode::Mov>(bx, rsi, 4);
buffer.Emit<OpCode::Mov>(ebx, rsi, 4);
buffer.Emit<OpCode::Mov>(rbx, rsi, 4);
buffer.Emit<OpCode::Mov>(rbx, -4, dil);
buffer.Emit<OpCode::Mov>(rbx, 4, dil);
buffer.Emit<OpCode::Mov>(rbx, 4, si);
buffer.Emit<OpCode::Mov>(rbx, 4, esi);
buffer.Emit<OpCode::Mov>(rbx, 4, rsi);
buffer.Emit<OpCode::MovZX>(bx, dil);
buffer.Emit<OpCode::MovZX, 2, false, 1, false>(bx, rsi, 4);
buffer.Emit<OpCode::MovZX>(ebx, dil);
buffer.Emit<OpCode::MovZX>(ebx, si);
buffer.Emit<OpCode::MovZX, 4, false, 1, false>(ebx, rsi, 4);
buffer.Emit<OpCode::MovZX, 4, false, 2, false>(ebx, rsi, 4);
buffer.Emit<OpCode::MovZX>(rbx, dil);
buffer.Emit<OpCode::MovZX>(rbx, si);
buffer.Emit<OpCode::MovZX, 8, false, 1, false>(rbx, rsi, 4);
buffer.Emit<OpCode::MovZX, 8, false, 2, false>(rbx, rsi, 4);
// Source: rsi, target: rsp
buffer.EmitImmediate<OpCode::Mov>(spl, static_cast<uint8_t>(1));
buffer.EmitImmediate<OpCode::Mov>(sp, static_cast<uint16_t>(1));
buffer.EmitImmediate<OpCode::Mov>(esp, 1);
buffer.EmitImmediate<OpCode::Mov>(rsp, 1);
buffer.Emit<OpCode::Mov>(spl, dil);
buffer.Emit<OpCode::Mov>(sp, si);
buffer.Emit<OpCode::Mov>(esp, esi);
buffer.Emit<OpCode::Mov>(rsp, rsi);
buffer.Emit<OpCode::Mov>(spl, rsi, -4);
buffer.Emit<OpCode::Mov>(spl, rsi, 4);
buffer.Emit<OpCode::Mov>(sp, rsi, 4);
buffer.Emit<OpCode::Mov>(esp, rsi, 4);
buffer.Emit<OpCode::Mov>(rsp, rsi, 4);
buffer.Emit<OpCode::Mov>(rsp, -4, dil);
buffer.Emit<OpCode::Mov>(rsp, 4, dil);
buffer.Emit<OpCode::Mov>(rsp, 4, si);
buffer.Emit<OpCode::Mov>(rsp, 4, esi);
buffer.Emit<OpCode::Mov>(rsp, 4, rsi);
buffer.Emit<OpCode::MovZX>(sp, dil);
buffer.Emit<OpCode::MovZX, 2, false, 1, false>(sp, rsi, 4);
buffer.Emit<OpCode::MovZX>(esp, dil);
buffer.Emit<OpCode::MovZX>(esp, si);
buffer.Emit<OpCode::MovZX, 4, false, 1, false>(esp, rsi, 4);
buffer.Emit<OpCode::MovZX, 4, false, 2, false>(esp, rsi, 4);
buffer.Emit<OpCode::MovZX>(rsp, dil);
buffer.Emit<OpCode::MovZX>(rsp, si);
buffer.Emit<OpCode::MovZX, 8, false, 1, false>(rsp, rsi, 4);
buffer.Emit<OpCode::MovZX, 8, false, 2, false>(rsp, rsi, 4);
// Source: rsi, target: rbp
buffer.EmitImmediate<OpCode::Mov>(bpl, static_cast<uint8_t>(1));
buffer.EmitImmediate<OpCode::Mov>(bp, static_cast<uint16_t>(1));
buffer.EmitImmediate<OpCode::Mov>(ebp, 1);
buffer.EmitImmediate<OpCode::Mov>(rbp, 1);
buffer.Emit<OpCode::Mov>(bpl, dil);
buffer.Emit<OpCode::Mov>(bp, si);
buffer.Emit<OpCode::Mov>(ebp, esi);
buffer.Emit<OpCode::Mov>(rbp, rsi);
buffer.Emit<OpCode::Mov>(bpl, rsi, -4);
buffer.Emit<OpCode::Mov>(bpl, rsi, 4);
buffer.Emit<OpCode::Mov>(bp, rsi, 4);
buffer.Emit<OpCode::Mov>(ebp, rsi, 4);
buffer.Emit<OpCode::Mov>(rbp, rsi, 4);
buffer.Emit<OpCode::Mov>(rbp, -4, dil);
buffer.Emit<OpCode::Mov>(rbp, 4, dil);
buffer.Emit<OpCode::Mov>(rbp, 4, si);
buffer.Emit<OpCode::Mov>(rbp, 4, esi);
buffer.Emit<OpCode::Mov>(rbp, 4, rsi);
buffer.Emit<OpCode::MovZX>(bp, dil);
buffer.Emit<OpCode::MovZX, 2, false, 1, false>(bp, rsi, 4);
buffer.Emit<OpCode::MovZX>(ebp, dil);
buffer.Emit<OpCode::MovZX>(ebp, si);
buffer.Emit<OpCode::MovZX, 4, false, 1, false>(ebp, rsi, 4);
buffer.Emit<OpCode::MovZX, 4, false, 2, false>(ebp, rsi, 4);
buffer.Emit<OpCode::MovZX>(rbp, dil);
buffer.Emit<OpCode::MovZX>(rbp, si);
buffer.Emit<OpCode::MovZX, 8, false, 1, false>(rbp, rsi, 4);
buffer.Emit<OpCode::MovZX, 8, false, 2, false>(rbp, rsi, 4);
// Source: rsi, target: rsi
buffer.EmitImmediate<OpCode::Mov>(dil, static_cast<uint8_t>(1));
buffer.EmitImmediate<OpCode::Mov>(si, static_cast<uint16_t>(1));
buffer.EmitImmediate<OpCode::Mov>(esi, 1);
buffer.EmitImmediate<OpCode::Mov>(rsi, 1);
buffer.Emit<OpCode::Mov>(dil, dil);
buffer.Emit<OpCode::Mov>(si, si);
buffer.Emit<OpCode::Mov>(esi, esi);
buffer.Emit<OpCode::Mov>(rsi, rsi);
buffer.Emit<OpCode::Mov>(dil, rsi, -4);
buffer.Emit<OpCode::Mov>(dil, rsi, 4);
buffer.Emit<OpCode::Mov>(si, rsi, 4);
buffer.Emit<OpCode::Mov>(esi, rsi, 4);
buffer.Emit<OpCode::Mov>(rsi, rsi, 4);
buffer.Emit<OpCode::Mov>(rsi, -4, dil);
buffer.Emit<OpCode::Mov>(rsi, 4, dil);
buffer.Emit<OpCode::Mov>(rsi, 4, si);
buffer.Emit<OpCode::Mov>(rsi, 4, esi);
buffer.Emit<OpCode::Mov>(rsi, 4, rsi);
buffer.Emit<OpCode::MovZX>(si, dil);
buffer.Emit<OpCode::MovZX, 2, false, 1, false>(si, rsi, 4);
buffer.Emit<OpCode::MovZX>(esi, dil);
buffer.Emit<OpCode::MovZX>(esi, si);
buffer.Emit<OpCode::MovZX, 4, false, 1, false>(esi, rsi, 4);
buffer.Emit<OpCode::MovZX, 4, false, 2, false>(esi, rsi, 4);
buffer.Emit<OpCode::MovZX>(rsi, dil);
buffer.Emit<OpCode::MovZX>(rsi, si);
buffer.Emit<OpCode::MovZX, 8, false, 1, false>(rsi, rsi, 4);
buffer.Emit<OpCode::MovZX, 8, false, 2, false>(rsi, rsi, 4);
// Source: rsi, target: rdi
buffer.EmitImmediate<OpCode::Mov>(sil, static_cast<uint8_t>(1));
buffer.EmitImmediate<OpCode::Mov>(di, static_cast<uint16_t>(1));
buffer.EmitImmediate<OpCode::Mov>(edi, 1);
buffer.EmitImmediate<OpCode::Mov>(rdi, 1);
buffer.Emit<OpCode::Mov>(sil, dil);
buffer.Emit<OpCode::Mov>(di, si);
buffer.Emit<OpCode::Mov>(edi, esi);
buffer.Emit<OpCode::Mov>(rdi, rsi);
buffer.Emit<OpCode::Mov>(sil, rsi, -4);
buffer.Emit<OpCode::Mov>(sil, rsi, 4);
buffer.Emit<OpCode::Mov>(di, rsi, 4);
buffer.Emit<OpCode::Mov>(edi, rsi, 4);
buffer.Emit<OpCode::Mov>(rdi, rsi, 4);
buffer.Emit<OpCode::Mov>(rdi, -4, dil);
buffer.Emit<OpCode::Mov>(rdi, 4, dil);
buffer.Emit<OpCode::Mov>(rdi, 4, si);
buffer.Emit<OpCode::Mov>(rdi, 4, esi);
buffer.Emit<OpCode::Mov>(rdi, 4, rsi);
buffer.Emit<OpCode::MovZX>(di, dil);
buffer.Emit<OpCode::MovZX, 2, false, 1, false>(di, rsi, 4);
buffer.Emit<OpCode::MovZX>(edi, dil);
buffer.Emit<OpCode::MovZX>(edi, si);
buffer.Emit<OpCode::MovZX, 4, false, 1, false>(edi, rsi, 4);
buffer.Emit<OpCode::MovZX, 4, false, 2, false>(edi, rsi, 4);
buffer.Emit<OpCode::MovZX>(rdi, dil);
buffer.Emit<OpCode::MovZX>(rdi, si);
buffer.Emit<OpCode::MovZX, 8, false, 1, false>(rdi, rsi, 4);
buffer.Emit<OpCode::MovZX, 8, false, 2, false>(rdi, rsi, 4);
// Source: rsi, target: r8
buffer.EmitImmediate<OpCode::Mov>(r8b, static_cast<uint8_t>(1));
buffer.EmitImmediate<OpCode::Mov>(r8w, static_cast<uint16_t>(1));
buffer.EmitImmediate<OpCode::Mov>(r8d, 1);
buffer.EmitImmediate<OpCode::Mov>(r8, 1);
buffer.Emit<OpCode::Mov>(r8b, dil);
buffer.Emit<OpCode::Mov>(r8w, si);
buffer.Emit<OpCode::Mov>(r8d, esi);
buffer.Emit<OpCode::Mov>(r8, rsi);
buffer.Emit<OpCode::Mov>(r8b, rsi, -4);
buffer.Emit<OpCode::Mov>(r8b, rsi, 4);
buffer.Emit<OpCode::Mov>(r8w, rsi, 4);
buffer.Emit<OpCode::Mov>(r8d, rsi, 4);
buffer.Emit<OpCode::Mov>(r8, rsi, 4);
buffer.Emit<OpCode::Mov>(r8, -4, dil);
buffer.Emit<OpCode::Mov>(r8, 4, dil);
buffer.Emit<OpCode::Mov>(r8, 4, si);
buffer.Emit<OpCode::Mov>(r8, 4, esi);
buffer.Emit<OpCode::Mov>(r8, 4, rsi);
buffer.Emit<OpCode::MovZX>(r8w, dil);
buffer.Emit<OpCode::MovZX, 2, false, 1, false>(r8w, rsi, 4);
buffer.Emit<OpCode::MovZX>(r8d, dil);
buffer.Emit<OpCode::MovZX>(r8d, si);
buffer.Emit<OpCode::MovZX, 4, false, 1, false>(r8d, rsi, 4);
buffer.Emit<OpCode::MovZX, 4, false, 2, false>(r8d, rsi, 4);
buffer.Emit<OpCode::MovZX>(r8, dil);
buffer.Emit<OpCode::MovZX>(r8, si);
buffer.Emit<OpCode::MovZX, 8, false, 1, false>(r8, rsi, 4);
buffer.Emit<OpCode::MovZX, 8, false, 2, false>(r8, rsi, 4);
// Source: rsi, target: r9
buffer.EmitImmediate<OpCode::Mov>(r9b, static_cast<uint8_t>(1));
buffer.EmitImmediate<OpCode::Mov>(r9w, static_cast<uint16_t>(1));
buffer.EmitImmediate<OpCode::Mov>(r9d, 1);
buffer.EmitImmediate<OpCode::Mov>(r9, 1);
buffer.Emit<OpCode::Mov>(r9b, dil);
buffer.Emit<OpCode::Mov>(r9w, si);
buffer.Emit<OpCode::Mov>(r9d, esi);
buffer.Emit<OpCode::Mov>(r9, rsi);
buffer.Emit<OpCode::Mov>(r9b, rsi, -4);
buffer.Emit<OpCode::Mov>(r9b, rsi, 4);
buffer.Emit<OpCode::Mov>(r9w, rsi, 4);
buffer.Emit<OpCode::Mov>(r9d, rsi, 4);
buffer.Emit<OpCode::Mov>(r9, rsi, 4);
buffer.Emit<OpCode::Mov>(r9, -4, dil);
buffer.Emit<OpCode::Mov>(r9, 4, dil);
buffer.Emit<OpCode::Mov>(r9, 4, si);
buffer.Emit<OpCode::Mov>(r9, 4, esi);
buffer.Emit<OpCode::Mov>(r9, 4, rsi);
buffer.Emit<OpCode::MovZX>(r9w, dil);
buffer.Emit<OpCode::MovZX, 2, false, 1, false>(r9w, rsi, 4);
buffer.Emit<OpCode::MovZX>(r9d, dil);
buffer.Emit<OpCode::MovZX>(r9d, si);
buffer.Emit<OpCode::MovZX, 4, false, 1, false>(r9d, rsi, 4);
buffer.Emit<OpCode::MovZX, 4, false, 2, false>(r9d, rsi, 4);
buffer.Emit<OpCode::MovZX>(r9, dil);
buffer.Emit<OpCode::MovZX>(r9, si);
buffer.Emit<OpCode::MovZX, 8, false, 1, false>(r9, rsi, 4);
buffer.Emit<OpCode::MovZX, 8, false, 2, false>(r9, rsi, 4);
// Source: rsi, target: r10
buffer.EmitImmediate<OpCode::Mov>(r10b, static_cast<uint8_t>(1));
buffer.EmitImmediate<OpCode::Mov>(r10w, static_cast<uint16_t>(1));
buffer.EmitImmediate<OpCode::Mov>(r10d, 1);
buffer.EmitImmediate<OpCode::Mov>(r10, 1);
buffer.Emit<OpCode::Mov>(r10b, dil);
buffer.Emit<OpCode::Mov>(r10w, si);
buffer.Emit<OpCode::Mov>(r10d, esi);
buffer.Emit<OpCode::Mov>(r10, rsi);
buffer.Emit<OpCode::Mov>(r10b, rsi, -4);
buffer.Emit<OpCode::Mov>(r10b, rsi, 4);
buffer.Emit<OpCode::Mov>(r10w, rsi, 4);
buffer.Emit<OpCode::Mov>(r10d, rsi, 4);
buffer.Emit<OpCode::Mov>(r10, rsi, 4);
buffer.Emit<OpCode::Mov>(r10, -4, dil);
buffer.Emit<OpCode::Mov>(r10, 4, dil);
buffer.Emit<OpCode::Mov>(r10, 4, si);
buffer.Emit<OpCode::Mov>(r10, 4, esi);
buffer.Emit<OpCode::Mov>(r10, 4, rsi);
buffer.Emit<OpCode::MovZX>(r10w, dil);
buffer.Emit<OpCode::MovZX, 2, false, 1, false>(r10w, rsi, 4);
buffer.Emit<OpCode::MovZX>(r10d, dil);
buffer.Emit<OpCode::MovZX>(r10d, si);
buffer.Emit<OpCode::MovZX, 4, false, 1, false>(r10d, rsi, 4);
buffer.Emit<OpCode::MovZX, 4, false, 2, false>(r10d, rsi, 4);
buffer.Emit<OpCode::MovZX>(r10, dil);
buffer.Emit<OpCode::MovZX>(r10, si);
buffer.Emit<OpCode::MovZX, 8, false, 1, false>(r10, rsi, 4);
buffer.Emit<OpCode::MovZX, 8, false, 2, false>(r10, rsi, 4);
// Source: rsi, target: r11
buffer.EmitImmediate<OpCode::Mov>(r11b, static_cast<uint8_t>(1));
buffer.EmitImmediate<OpCode::Mov>(r11w, static_cast<uint16_t>(1));
buffer.EmitImmediate<OpCode::Mov>(r11d, 1);
buffer.EmitImmediate<OpCode::Mov>(r11, 1);
buffer.Emit<OpCode::Mov>(r11b, dil);
buffer.Emit<OpCode::Mov>(r11w, si);
buffer.Emit<OpCode::Mov>(r11d, esi);
buffer.Emit<OpCode::Mov>(r11, rsi);
buffer.Emit<OpCode::Mov>(r11b, rsi, -4);
buffer.Emit<OpCode::Mov>(r11b, rsi, 4);
buffer.Emit<OpCode::Mov>(r11w, rsi, 4);
buffer.Emit<OpCode::Mov>(r11d, rsi, 4);
buffer.Emit<OpCode::Mov>(r11, rsi, 4);
buffer.Emit<OpCode::Mov>(r11, -4, dil);
buffer.Emit<OpCode::Mov>(r11, 4, dil);
buffer.Emit<OpCode::Mov>(r11, 4, si);
buffer.Emit<OpCode::Mov>(r11, 4, esi);
buffer.Emit<OpCode::Mov>(r11, 4, rsi);
buffer.Emit<OpCode::MovZX>(r11w, dil);
buffer.Emit<OpCode::MovZX, 2, false, 1, false>(r11w, rsi, 4);
buffer.Emit<OpCode::MovZX>(r11d, dil);
buffer.Emit<OpCode::MovZX>(r11d, si);
buffer.Emit<OpCode::MovZX, 4, false, 1, false>(r11d, rsi, 4);
buffer.Emit<OpCode::MovZX, 4, false, 2, false>(r11d, rsi, 4);
buffer.Emit<OpCode::MovZX>(r11, dil);
buffer.Emit<OpCode::MovZX>(r11, si);
buffer.Emit<OpCode::MovZX, 8, false, 1, false>(r11, rsi, 4);
buffer.Emit<OpCode::MovZX, 8, false, 2, false>(r11, rsi, 4);
// Source: rsi, target: r12
buffer.EmitImmediate<OpCode::Mov>(r12b, static_cast<uint8_t>(1));
buffer.EmitImmediate<OpCode::Mov>(r12w, static_cast<uint16_t>(1));
buffer.EmitImmediate<OpCode::Mov>(r12d, 1);
buffer.EmitImmediate<OpCode::Mov>(r12, 1);
buffer.Emit<OpCode::Mov>(r12b, dil);
buffer.Emit<OpCode::Mov>(r12w, si);
buffer.Emit<OpCode::Mov>(r12d, esi);
buffer.Emit<OpCode::Mov>(r12, rsi);
buffer.Emit<OpCode::Mov>(r12b, rsi, -4);
buffer.Emit<OpCode::Mov>(r12b, rsi, 4);
buffer.Emit<OpCode::Mov>(r12w, rsi, 4);
buffer.Emit<OpCode::Mov>(r12d, rsi, 4);
buffer.Emit<OpCode::Mov>(r12, rsi, 4);
buffer.Emit<OpCode::Mov>(r12, -4, dil);
buffer.Emit<OpCode::Mov>(r12, 4, dil);
buffer.Emit<OpCode::Mov>(r12, 4, si);
buffer.Emit<OpCode::Mov>(r12, 4, esi);
buffer.Emit<OpCode::Mov>(r12, 4, rsi);
buffer.Emit<OpCode::MovZX>(r12w, dil);
buffer.Emit<OpCode::MovZX, 2, false, 1, false>(r12w, rsi, 4);
buffer.Emit<OpCode::MovZX>(r12d, dil);
buffer.Emit<OpCode::MovZX>(r12d, si);
buffer.Emit<OpCode::MovZX, 4, false, 1, false>(r12d, rsi, 4);
buffer.Emit<OpCode::MovZX, 4, false, 2, false>(r12d, rsi, 4);
buffer.Emit<OpCode::MovZX>(r12, dil);
buffer.Emit<OpCode::MovZX>(r12, si);
buffer.Emit<OpCode::MovZX, 8, false, 1, false>(r12, rsi, 4);
buffer.Emit<OpCode::MovZX, 8, false, 2, false>(r12, rsi, 4);
// Source: rsi, target: r13
buffer.EmitImmediate<OpCode::Mov>(r13b, static_cast<uint8_t>(1));
buffer.EmitImmediate<OpCode::Mov>(r13w, static_cast<uint16_t>(1));
buffer.EmitImmediate<OpCode::Mov>(r13d, 1);
buffer.EmitImmediate<OpCode::Mov>(r13, 1);
buffer.Emit<OpCode::Mov>(r13b, dil);
buffer.Emit<OpCode::Mov>(r13w, si);
buffer.Emit<OpCode::Mov>(r13d, esi);
buffer.Emit<OpCode::Mov>(r13, rsi);
buffer.Emit<OpCode::Mov>(r13b, rsi, -4);
buffer.Emit<OpCode::Mov>(r13b, rsi, 4);
buffer.Emit<OpCode::Mov>(r13w, rsi, 4);
buffer.Emit<OpCode::Mov>(r13d, rsi, 4);
buffer.Emit<OpCode::Mov>(r13, rsi, 4);
buffer.Emit<OpCode::Mov>(r13, -4, dil);
buffer.Emit<OpCode::Mov>(r13, 4, dil);
buffer.Emit<OpCode::Mov>(r13, 4, si);
buffer.Emit<OpCode::Mov>(r13, 4, esi);
buffer.Emit<OpCode::Mov>(r13, 4, rsi);
buffer.Emit<OpCode::MovZX>(r13w, dil);
buffer.Emit<OpCode::MovZX, 2, false, 1, false>(r13w, rsi, 4);
buffer.Emit<OpCode::MovZX>(r13d, dil);
buffer.Emit<OpCode::MovZX>(r13d, si);
buffer.Emit<OpCode::MovZX, 4, false, 1, false>(r13d, rsi, 4);
buffer.Emit<OpCode::MovZX, 4, false, 2, false>(r13d, rsi, 4);
buffer.Emit<OpCode::MovZX>(r13, dil);
buffer.Emit<OpCode::MovZX>(r13, si);
buffer.Emit<OpCode::MovZX, 8, false, 1, false>(r13, rsi, 4);
buffer.Emit<OpCode::MovZX, 8, false, 2, false>(r13, rsi, 4);
// Source: rsi, target: r14
buffer.EmitImmediate<OpCode::Mov>(r14b, static_cast<uint8_t>(1));
buffer.EmitImmediate<OpCode::Mov>(r14w, static_cast<uint16_t>(1));
buffer.EmitImmediate<OpCode::Mov>(r14d, 1);
buffer.EmitImmediate<OpCode::Mov>(r14, 1);
buffer.Emit<OpCode::Mov>(r14b, dil);
buffer.Emit<OpCode::Mov>(r14w, si);
buffer.Emit<OpCode::Mov>(r14d, esi);
buffer.Emit<OpCode::Mov>(r14, rsi);
buffer.Emit<OpCode::Mov>(r14b, rsi, -4);
buffer.Emit<OpCode::Mov>(r14b, rsi, 4);
buffer.Emit<OpCode::Mov>(r14w, rsi, 4);
buffer.Emit<OpCode::Mov>(r14d, rsi, 4);
buffer.Emit<OpCode::Mov>(r14, rsi, 4);
buffer.Emit<OpCode::Mov>(r14, -4, dil);
buffer.Emit<OpCode::Mov>(r14, 4, dil);
buffer.Emit<OpCode::Mov>(r14, 4, si);
buffer.Emit<OpCode::Mov>(r14, 4, esi);
buffer.Emit<OpCode::Mov>(r14, 4, rsi);
buffer.Emit<OpCode::MovZX>(r14w, dil);
buffer.Emit<OpCode::MovZX, 2, false, 1, false>(r14w, rsi, 4);
buffer.Emit<OpCode::MovZX>(r14d, dil);
buffer.Emit<OpCode::MovZX>(r14d, si);
buffer.Emit<OpCode::MovZX, 4, false, 1, false>(r14d, rsi, 4);
buffer.Emit<OpCode::MovZX, 4, false, 2, false>(r14d, rsi, 4);
buffer.Emit<OpCode::MovZX>(r14, dil);
buffer.Emit<OpCode::MovZX>(r14, si);
buffer.Emit<OpCode::MovZX, 8, false, 1, false>(r14, rsi, 4);
buffer.Emit<OpCode::MovZX, 8, false, 2, false>(r14, rsi, 4);
// Source: rsi, target: r15
buffer.EmitImmediate<OpCode::Mov>(r15b, static_cast<uint8_t>(1));
buffer.EmitImmediate<OpCode::Mov>(r15w, static_cast<uint16_t>(1));
buffer.EmitImmediate<OpCode::Mov>(r15d, 1);
buffer.EmitImmediate<OpCode::Mov>(r15, 1);
buffer.Emit<OpCode::Mov>(r15b, dil);
buffer.Emit<OpCode::Mov>(r15w, si);
buffer.Emit<OpCode::Mov>(r15d, esi);
buffer.Emit<OpCode::Mov>(r15, rsi);
buffer.Emit<OpCode::Mov>(r15b, rsi, -4);
buffer.Emit<OpCode::Mov>(r15b, rsi, 4);
buffer.Emit<OpCode::Mov>(r15w, rsi, 4);
buffer.Emit<OpCode::Mov>(r15d, rsi, 4);
buffer.Emit<OpCode::Mov>(r15, rsi, 4);
buffer.Emit<OpCode::Mov>(r15, -4, dil);
buffer.Emit<OpCode::Mov>(r15, 4, dil);
buffer.Emit<OpCode::Mov>(r15, 4, si);
buffer.Emit<OpCode::Mov>(r15, 4, esi);
buffer.Emit<OpCode::Mov>(r15, 4, rsi);
buffer.Emit<OpCode::MovZX>(r15w, dil);
buffer.Emit<OpCode::MovZX, 2, false, 1, false>(r15w, rsi, 4);
buffer.Emit<OpCode::MovZX>(r15d, dil);
buffer.Emit<OpCode::MovZX>(r15d, si);
buffer.Emit<OpCode::MovZX, 4, false, 1, false>(r15d, rsi, 4);
buffer.Emit<OpCode::MovZX, 4, false, 2, false>(r15d, rsi, 4);
buffer.Emit<OpCode::MovZX>(r15, dil);
buffer.Emit<OpCode::MovZX>(r15, si);
buffer.Emit<OpCode::MovZX, 8, false, 1, false>(r15, rsi, 4);
buffer.Emit<OpCode::MovZX, 8, false, 2, false>(r15, rsi, 4);
// Source: rdi, target: rax
buffer.EmitImmediate<OpCode::Mov>(al, static_cast<uint8_t>(1));
buffer.EmitImmediate<OpCode::Mov>(ax, static_cast<uint16_t>(1));
buffer.EmitImmediate<OpCode::Mov>(eax, 1);
buffer.EmitImmediate<OpCode::Mov>(rax, 1);
buffer.Emit<OpCode::Mov>(al, sil);
buffer.Emit<OpCode::Mov>(ax, di);
buffer.Emit<OpCode::Mov>(eax, edi);
buffer.Emit<OpCode::Mov>(rax, rdi);
buffer.Emit<OpCode::Mov>(al, rdi, -4);
buffer.Emit<OpCode::Mov>(al, rdi, 4);
buffer.Emit<OpCode::Mov>(ax, rdi, 4);
buffer.Emit<OpCode::Mov>(eax, rdi, 4);
buffer.Emit<OpCode::Mov>(rax, rdi, 4);
buffer.Emit<OpCode::Mov>(rax, -4, sil);
buffer.Emit<OpCode::Mov>(rax, 4, sil);
buffer.Emit<OpCode::Mov>(rax, 4, di);
buffer.Emit<OpCode::Mov>(rax, 4, edi);
buffer.Emit<OpCode::Mov>(rax, 4, rdi);
buffer.Emit<OpCode::MovZX>(ax, sil);
buffer.Emit<OpCode::MovZX, 2, false, 1, false>(ax, rdi, 4);
buffer.Emit<OpCode::MovZX>(eax, sil);
buffer.Emit<OpCode::MovZX>(eax, di);
buffer.Emit<OpCode::MovZX, 4, false, 1, false>(eax, rdi, 4);
buffer.Emit<OpCode::MovZX, 4, false, 2, false>(eax, rdi, 4);
buffer.Emit<OpCode::MovZX>(rax, sil);
buffer.Emit<OpCode::MovZX>(rax, di);
buffer.Emit<OpCode::MovZX, 8, false, 1, false>(rax, rdi, 4);
buffer.Emit<OpCode::MovZX, 8, false, 2, false>(rax, rdi, 4);
// Source: rdi, target: rcx
buffer.EmitImmediate<OpCode::Mov>(cl, static_cast<uint8_t>(1));
buffer.EmitImmediate<OpCode::Mov>(cx, static_cast<uint16_t>(1));
buffer.EmitImmediate<OpCode::Mov>(ecx, 1);
buffer.EmitImmediate<OpCode::Mov>(rcx, 1);
buffer.Emit<OpCode::Mov>(cl, sil);
buffer.Emit<OpCode::Mov>(cx, di);
buffer.Emit<OpCode::Mov>(ecx, edi);
buffer.Emit<OpCode::Mov>(rcx, rdi);
buffer.Emit<OpCode::Mov>(cl, rdi, -4);
buffer.Emit<OpCode::Mov>(cl, rdi, 4);
buffer.Emit<OpCode::Mov>(cx, rdi, 4);
buffer.Emit<OpCode::Mov>(ecx, rdi, 4);
buffer.Emit<OpCode::Mov>(rcx, rdi, 4);
buffer.Emit<OpCode::Mov>(rcx, -4, sil);
buffer.Emit<OpCode::Mov>(rcx, 4, sil);
buffer.Emit<OpCode::Mov>(rcx, 4, di);
buffer.Emit<OpCode::Mov>(rcx, 4, edi);
buffer.Emit<OpCode::Mov>(rcx, 4, rdi);
buffer.Emit<OpCode::MovZX>(cx, sil);
buffer.Emit<OpCode::MovZX, 2, false, 1, false>(cx, rdi, 4);
buffer.Emit<OpCode::MovZX>(ecx, sil);
buffer.Emit<OpCode::MovZX>(ecx, di);
buffer.Emit<OpCode::MovZX, 4, false, 1, false>(ecx, rdi, 4);
buffer.Emit<OpCode::MovZX, 4, false, 2, false>(ecx, rdi, 4);
buffer.Emit<OpCode::MovZX>(rcx, sil);
buffer.Emit<OpCode::MovZX>(rcx, di);
buffer.Emit<OpCode::MovZX, 8, false, 1, false>(rcx, rdi, 4);
buffer.Emit<OpCode::MovZX, 8, false, 2, false>(rcx, rdi, 4);
// Source: rdi, target: rdx
buffer.EmitImmediate<OpCode::Mov>(dl, static_cast<uint8_t>(1));
buffer.EmitImmediate<OpCode::Mov>(dx, static_cast<uint16_t>(1));
buffer.EmitImmediate<OpCode::Mov>(edx, 1);
buffer.EmitImmediate<OpCode::Mov>(rdx, 1);
buffer.Emit<OpCode::Mov>(dl, sil);
buffer.Emit<OpCode::Mov>(dx, di);
buffer.Emit<OpCode::Mov>(edx, edi);
buffer.Emit<OpCode::Mov>(rdx, rdi);
buffer.Emit<OpCode::Mov>(dl, rdi, -4);
buffer.Emit<OpCode::Mov>(dl, rdi, 4);
buffer.Emit<OpCode::Mov>(dx, rdi, 4);
buffer.Emit<OpCode::Mov>(edx, rdi, 4);
buffer.Emit<OpCode::Mov>(rdx, rdi, 4);
buffer.Emit<OpCode::Mov>(rdx, -4, sil);
buffer.Emit<OpCode::Mov>(rdx, 4, sil);
buffer.Emit<OpCode::Mov>(rdx, 4, di);
buffer.Emit<OpCode::Mov>(rdx, 4, edi);
buffer.Emit<OpCode::Mov>(rdx, 4, rdi);
buffer.Emit<OpCode::MovZX>(dx, sil);
buffer.Emit<OpCode::MovZX, 2, false, 1, false>(dx, rdi, 4);
buffer.Emit<OpCode::MovZX>(edx, sil);
buffer.Emit<OpCode::MovZX>(edx, di);
buffer.Emit<OpCode::MovZX, 4, false, 1, false>(edx, rdi, 4);
buffer.Emit<OpCode::MovZX, 4, false, 2, false>(edx, rdi, 4);
buffer.Emit<OpCode::MovZX>(rdx, sil);
buffer.Emit<OpCode::MovZX>(rdx, di);
buffer.Emit<OpCode::MovZX, 8, false, 1, false>(rdx, rdi, 4);
buffer.Emit<OpCode::MovZX, 8, false, 2, false>(rdx, rdi, 4);
// Source: rdi, target: rbx
buffer.EmitImmediate<OpCode::Mov>(bl, static_cast<uint8_t>(1));
buffer.EmitImmediate<OpCode::Mov>(bx, static_cast<uint16_t>(1));
buffer.EmitImmediate<OpCode::Mov>(ebx, 1);
buffer.EmitImmediate<OpCode::Mov>(rbx, 1);
buffer.Emit<OpCode::Mov>(bl, sil);
buffer.Emit<OpCode::Mov>(bx, di);
buffer.Emit<OpCode::Mov>(ebx, edi);
buffer.Emit<OpCode::Mov>(rbx, rdi);
buffer.Emit<OpCode::Mov>(bl, rdi, -4);
buffer.Emit<OpCode::Mov>(bl, rdi, 4);
buffer.Emit<OpCode::Mov>(bx, rdi, 4);
buffer.Emit<OpCode::Mov>(ebx, rdi, 4);
buffer.Emit<OpCode::Mov>(rbx, rdi, 4);
buffer.Emit<OpCode::Mov>(rbx, -4, sil);
buffer.Emit<OpCode::Mov>(rbx, 4, sil);
buffer.Emit<OpCode::Mov>(rbx, 4, di);
buffer.Emit<OpCode::Mov>(rbx, 4, edi);
buffer.Emit<OpCode::Mov>(rbx, 4, rdi);
buffer.Emit<OpCode::MovZX>(bx, sil);
buffer.Emit<OpCode::MovZX, 2, false, 1, false>(bx, rdi, 4);
buffer.Emit<OpCode::MovZX>(ebx, sil);
buffer.Emit<OpCode::MovZX>(ebx, di);
buffer.Emit<OpCode::MovZX, 4, false, 1, false>(ebx, rdi, 4);
buffer.Emit<OpCode::MovZX, 4, false, 2, false>(ebx, rdi, 4);
buffer.Emit<OpCode::MovZX>(rbx, sil);
buffer.Emit<OpCode::MovZX>(rbx, di);
buffer.Emit<OpCode::MovZX, 8, false, 1, false>(rbx, rdi, 4);
buffer.Emit<OpCode::MovZX, 8, false, 2, false>(rbx, rdi, 4);
// Source: rdi, target: rsp
buffer.EmitImmediate<OpCode::Mov>(spl, static_cast<uint8_t>(1));
buffer.EmitImmediate<OpCode::Mov>(sp, static_cast<uint16_t>(1));
buffer.EmitImmediate<OpCode::Mov>(esp, 1);
buffer.EmitImmediate<OpCode::Mov>(rsp, 1);
buffer.Emit<OpCode::Mov>(spl, sil);
buffer.Emit<OpCode::Mov>(sp, di);
buffer.Emit<OpCode::Mov>(esp, edi);
buffer.Emit<OpCode::Mov>(rsp, rdi);
buffer.Emit<OpCode::Mov>(spl, rdi, -4);
buffer.Emit<OpCode::Mov>(spl, rdi, 4);
buffer.Emit<OpCode::Mov>(sp, rdi, 4);
buffer.Emit<OpCode::Mov>(esp, rdi, 4);
buffer.Emit<OpCode::Mov>(rsp, rdi, 4);
buffer.Emit<OpCode::Mov>(rsp, -4, sil);
buffer.Emit<OpCode::Mov>(rsp, 4, sil);
buffer.Emit<OpCode::Mov>(rsp, 4, di);
buffer.Emit<OpCode::Mov>(rsp, 4, edi);
buffer.Emit<OpCode::Mov>(rsp, 4, rdi);
buffer.Emit<OpCode::MovZX>(sp, sil);
buffer.Emit<OpCode::MovZX, 2, false, 1, false>(sp, rdi, 4);
buffer.Emit<OpCode::MovZX>(esp, sil);
buffer.Emit<OpCode::MovZX>(esp, di);
buffer.Emit<OpCode::MovZX, 4, false, 1, false>(esp, rdi, 4);
buffer.Emit<OpCode::MovZX, 4, false, 2, false>(esp, rdi, 4);
buffer.Emit<OpCode::MovZX>(rsp, sil);
buffer.Emit<OpCode::MovZX>(rsp, di);
buffer.Emit<OpCode::MovZX, 8, false, 1, false>(rsp, rdi, 4);
buffer.Emit<OpCode::MovZX, 8, false, 2, false>(rsp, rdi, 4);
// Source: rdi, target: rbp
buffer.EmitImmediate<OpCode::Mov>(bpl, static_cast<uint8_t>(1));
buffer.EmitImmediate<OpCode::Mov>(bp, static_cast<uint16_t>(1));
buffer.EmitImmediate<OpCode::Mov>(ebp, 1);
buffer.EmitImmediate<OpCode::Mov>(rbp, 1);
buffer.Emit<OpCode::Mov>(bpl, sil);
buffer.Emit<OpCode::Mov>(bp, di);
buffer.Emit<OpCode::Mov>(ebp, edi);
buffer.Emit<OpCode::Mov>(rbp, rdi);
buffer.Emit<OpCode::Mov>(bpl, rdi, -4);
buffer.Emit<OpCode::Mov>(bpl, rdi, 4);
buffer.Emit<OpCode::Mov>(bp, rdi, 4);
buffer.Emit<OpCode::Mov>(ebp, rdi, 4);
buffer.Emit<OpCode::Mov>(rbp, rdi, 4);
buffer.Emit<OpCode::Mov>(rbp, -4, sil);
buffer.Emit<OpCode::Mov>(rbp, 4, sil);
buffer.Emit<OpCode::Mov>(rbp, 4, di);
buffer.Emit<OpCode::Mov>(rbp, 4, edi);
buffer.Emit<OpCode::Mov>(rbp, 4, rdi);
buffer.Emit<OpCode::MovZX>(bp, sil);
buffer.Emit<OpCode::MovZX, 2, false, 1, false>(bp, rdi, 4);
buffer.Emit<OpCode::MovZX>(ebp, sil);
buffer.Emit<OpCode::MovZX>(ebp, di);
buffer.Emit<OpCode::MovZX, 4, false, 1, false>(ebp, rdi, 4);
buffer.Emit<OpCode::MovZX, 4, false, 2, false>(ebp, rdi, 4);
buffer.Emit<OpCode::MovZX>(rbp, sil);
buffer.Emit<OpCode::MovZX>(rbp, di);
buffer.Emit<OpCode::MovZX, 8, false, 1, false>(rbp, rdi, 4);
buffer.Emit<OpCode::MovZX, 8, false, 2, false>(rbp, rdi, 4);
// Source: rdi, target: rsi
buffer.EmitImmediate<OpCode::Mov>(dil, static_cast<uint8_t>(1));
buffer.EmitImmediate<OpCode::Mov>(si, static_cast<uint16_t>(1));
buffer.EmitImmediate<OpCode::Mov>(esi, 1);
buffer.EmitImmediate<OpCode::Mov>(rsi, 1);
buffer.Emit<OpCode::Mov>(dil, sil);
buffer.Emit<OpCode::Mov>(si, di);
buffer.Emit<OpCode::Mov>(esi, edi);
buffer.Emit<OpCode::Mov>(rsi, rdi);
buffer.Emit<OpCode::Mov>(dil, rdi, -4);
buffer.Emit<OpCode::Mov>(dil, rdi, 4);
buffer.Emit<OpCode::Mov>(si, rdi, 4);
buffer.Emit<OpCode::Mov>(esi, rdi, 4);
buffer.Emit<OpCode::Mov>(rsi, rdi, 4);
buffer.Emit<OpCode::Mov>(rsi, -4, sil);
buffer.Emit<OpCode::Mov>(rsi, 4, sil);
buffer.Emit<OpCode::Mov>(rsi, 4, di);
buffer.Emit<OpCode::Mov>(rsi, 4, edi);
buffer.Emit<OpCode::Mov>(rsi, 4, rdi);
buffer.Emit<OpCode::MovZX>(si, sil);
buffer.Emit<OpCode::MovZX, 2, false, 1, false>(si, rdi, 4);
buffer.Emit<OpCode::MovZX>(esi, sil);
buffer.Emit<OpCode::MovZX>(esi, di);
buffer.Emit<OpCode::MovZX, 4, false, 1, false>(esi, rdi, 4);
buffer.Emit<OpCode::MovZX, 4, false, 2, false>(esi, rdi, 4);
buffer.Emit<OpCode::MovZX>(rsi, sil);
buffer.Emit<OpCode::MovZX>(rsi, di);
buffer.Emit<OpCode::MovZX, 8, false, 1, false>(rsi, rdi, 4);
buffer.Emit<OpCode::MovZX, 8, false, 2, false>(rsi, rdi, 4);
// Source: rdi, target: rdi
buffer.EmitImmediate<OpCode::Mov>(sil, static_cast<uint8_t>(1));
buffer.EmitImmediate<OpCode::Mov>(di, static_cast<uint16_t>(1));
buffer.EmitImmediate<OpCode::Mov>(edi, 1);
buffer.EmitImmediate<OpCode::Mov>(rdi, 1);
buffer.Emit<OpCode::Mov>(sil, sil);
buffer.Emit<OpCode::Mov>(di, di);
buffer.Emit<OpCode::Mov>(edi, edi);
buffer.Emit<OpCode::Mov>(rdi, rdi);
buffer.Emit<OpCode::Mov>(sil, rdi, -4);
buffer.Emit<OpCode::Mov>(sil, rdi, 4);
buffer.Emit<OpCode::Mov>(di, rdi, 4);
buffer.Emit<OpCode::Mov>(edi, rdi, 4);
buffer.Emit<OpCode::Mov>(rdi, rdi, 4);
buffer.Emit<OpCode::Mov>(rdi, -4, sil);
buffer.Emit<OpCode::Mov>(rdi, 4, sil);
buffer.Emit<OpCode::Mov>(rdi, 4, di);
buffer.Emit<OpCode::Mov>(rdi, 4, edi);
buffer.Emit<OpCode::Mov>(rdi, 4, rdi);
buffer.Emit<OpCode::MovZX>(di, sil);
buffer.Emit<OpCode::MovZX, 2, false, 1, false>(di, rdi, 4);
buffer.Emit<OpCode::MovZX>(edi, sil);
buffer.Emit<OpCode::MovZX>(edi, di);
buffer.Emit<OpCode::MovZX, 4, false, 1, false>(edi, rdi, 4);
buffer.Emit<OpCode::MovZX, 4, false, 2, false>(edi, rdi, 4);
buffer.Emit<OpCode::MovZX>(rdi, sil);
buffer.Emit<OpCode::MovZX>(rdi, di);
buffer.Emit<OpCode::MovZX, 8, false, 1, false>(rdi, rdi, 4);
buffer.Emit<OpCode::MovZX, 8, false, 2, false>(rdi, rdi, 4);
// Source: rdi, target: r8
buffer.EmitImmediate<OpCode::Mov>(r8b, static_cast<uint8_t>(1));
buffer.EmitImmediate<OpCode::Mov>(r8w, static_cast<uint16_t>(1));
buffer.EmitImmediate<OpCode::Mov>(r8d, 1);
buffer.EmitImmediate<OpCode::Mov>(r8, 1);
buffer.Emit<OpCode::Mov>(r8b, sil);
buffer.Emit<OpCode::Mov>(r8w, di);
buffer.Emit<OpCode::Mov>(r8d, edi);
buffer.Emit<OpCode::Mov>(r8, rdi);
buffer.Emit<OpCode::Mov>(r8b, rdi, -4);
buffer.Emit<OpCode::Mov>(r8b, rdi, 4);
buffer.Emit<OpCode::Mov>(r8w, rdi, 4);
buffer.Emit<OpCode::Mov>(r8d, rdi, 4);
buffer.Emit<OpCode::Mov>(r8, rdi, 4);
buffer.Emit<OpCode::Mov>(r8, -4, sil);
buffer.Emit<OpCode::Mov>(r8, 4, sil);
buffer.Emit<OpCode::Mov>(r8, 4, di);
buffer.Emit<OpCode::Mov>(r8, 4, edi);
buffer.Emit<OpCode::Mov>(r8, 4, rdi);
buffer.Emit<OpCode::MovZX>(r8w, sil);
buffer.Emit<OpCode::MovZX, 2, false, 1, false>(r8w, rdi, 4);
buffer.Emit<OpCode::MovZX>(r8d, sil);
buffer.Emit<OpCode::MovZX>(r8d, di);
buffer.Emit<OpCode::MovZX, 4, false, 1, false>(r8d, rdi, 4);
buffer.Emit<OpCode::MovZX, 4, false, 2, false>(r8d, rdi, 4);
buffer.Emit<OpCode::MovZX>(r8, sil);
buffer.Emit<OpCode::MovZX>(r8, di);
buffer.Emit<OpCode::MovZX, 8, false, 1, false>(r8, rdi, 4);
buffer.Emit<OpCode::MovZX, 8, false, 2, false>(r8, rdi, 4);
// Source: rdi, target: r9
buffer.EmitImmediate<OpCode::Mov>(r9b, static_cast<uint8_t>(1));
buffer.EmitImmediate<OpCode::Mov>(r9w, static_cast<uint16_t>(1));
buffer.EmitImmediate<OpCode::Mov>(r9d, 1);
buffer.EmitImmediate<OpCode::Mov>(r9, 1);
buffer.Emit<OpCode::Mov>(r9b, sil);
buffer.Emit<OpCode::Mov>(r9w, di);
buffer.Emit<OpCode::Mov>(r9d, edi);
buffer.Emit<OpCode::Mov>(r9, rdi);
buffer.Emit<OpCode::Mov>(r9b, rdi, -4);
buffer.Emit<OpCode::Mov>(r9b, rdi, 4);
buffer.Emit<OpCode::Mov>(r9w, rdi, 4);
buffer.Emit<OpCode::Mov>(r9d, rdi, 4);
buffer.Emit<OpCode::Mov>(r9, rdi, 4);
buffer.Emit<OpCode::Mov>(r9, -4, sil);
buffer.Emit<OpCode::Mov>(r9, 4, sil);
buffer.Emit<OpCode::Mov>(r9, 4, di);
buffer.Emit<OpCode::Mov>(r9, 4, edi);
buffer.Emit<OpCode::Mov>(r9, 4, rdi);
buffer.Emit<OpCode::MovZX>(r9w, sil);
buffer.Emit<OpCode::MovZX, 2, false, 1, false>(r9w, rdi, 4);
buffer.Emit<OpCode::MovZX>(r9d, sil);
buffer.Emit<OpCode::MovZX>(r9d, di);
buffer.Emit<OpCode::MovZX, 4, false, 1, false>(r9d, rdi, 4);
buffer.Emit<OpCode::MovZX, 4, false, 2, false>(r9d, rdi, 4);
buffer.Emit<OpCode::MovZX>(r9, sil);
buffer.Emit<OpCode::MovZX>(r9, di);
buffer.Emit<OpCode::MovZX, 8, false, 1, false>(r9, rdi, 4);
buffer.Emit<OpCode::MovZX, 8, false, 2, false>(r9, rdi, 4);
// Source: rdi, target: r10
buffer.EmitImmediate<OpCode::Mov>(r10b, static_cast<uint8_t>(1));
buffer.EmitImmediate<OpCode::Mov>(r10w, static_cast<uint16_t>(1));
buffer.EmitImmediate<OpCode::Mov>(r10d, 1);
buffer.EmitImmediate<OpCode::Mov>(r10, 1);
buffer.Emit<OpCode::Mov>(r10b, sil);
buffer.Emit<OpCode::Mov>(r10w, di);
buffer.Emit<OpCode::Mov>(r10d, edi);
buffer.Emit<OpCode::Mov>(r10, rdi);
buffer.Emit<OpCode::Mov>(r10b, rdi, -4);
buffer.Emit<OpCode::Mov>(r10b, rdi, 4);
buffer.Emit<OpCode::Mov>(r10w, rdi, 4);
buffer.Emit<OpCode::Mov>(r10d, rdi, 4);
buffer.Emit<OpCode::Mov>(r10, rdi, 4);
buffer.Emit<OpCode::Mov>(r10, -4, sil);
buffer.Emit<OpCode::Mov>(r10, 4, sil);
buffer.Emit<OpCode::Mov>(r10, 4, di);
buffer.Emit<OpCode::Mov>(r10, 4, edi);
buffer.Emit<OpCode::Mov>(r10, 4, rdi);
buffer.Emit<OpCode::MovZX>(r10w, sil);
buffer.Emit<OpCode::MovZX, 2, false, 1, false>(r10w, rdi, 4);
buffer.Emit<OpCode::MovZX>(r10d, sil);
buffer.Emit<OpCode::MovZX>(r10d, di);
buffer.Emit<OpCode::MovZX, 4, false, 1, false>(r10d, rdi, 4);
buffer.Emit<OpCode::MovZX, 4, false, 2, false>(r10d, rdi, 4);
buffer.Emit<OpCode::MovZX>(r10, sil);
buffer.Emit<OpCode::MovZX>(r10, di);
buffer.Emit<OpCode::MovZX, 8, false, 1, false>(r10, rdi, 4);
buffer.Emit<OpCode::MovZX, 8, false, 2, false>(r10, rdi, 4);
// Source: rdi, target: r11
buffer.EmitImmediate<OpCode::Mov>(r11b, static_cast<uint8_t>(1));
buffer.EmitImmediate<OpCode::Mov>(r11w, static_cast<uint16_t>(1));
buffer.EmitImmediate<OpCode::Mov>(r11d, 1);
buffer.EmitImmediate<OpCode::Mov>(r11, 1);
buffer.Emit<OpCode::Mov>(r11b, sil);
buffer.Emit<OpCode::Mov>(r11w, di);
buffer.Emit<OpCode::Mov>(r11d, edi);
buffer.Emit<OpCode::Mov>(r11, rdi);
buffer.Emit<OpCode::Mov>(r11b, rdi, -4);
buffer.Emit<OpCode::Mov>(r11b, rdi, 4);
buffer.Emit<OpCode::Mov>(r11w, rdi, 4);
buffer.Emit<OpCode::Mov>(r11d, rdi, 4);
buffer.Emit<OpCode::Mov>(r11, rdi, 4);
buffer.Emit<OpCode::Mov>(r11, -4, sil);
buffer.Emit<OpCode::Mov>(r11, 4, sil);
buffer.Emit<OpCode::Mov>(r11, 4, di);
buffer.Emit<OpCode::Mov>(r11, 4, edi);
buffer.Emit<OpCode::Mov>(r11, 4, rdi);
buffer.Emit<OpCode::MovZX>(r11w, sil);
buffer.Emit<OpCode::MovZX, 2, false, 1, false>(r11w, rdi, 4);
buffer.Emit<OpCode::MovZX>(r11d, sil);
buffer.Emit<OpCode::MovZX>(r11d, di);
buffer.Emit<OpCode::MovZX, 4, false, 1, false>(r11d, rdi, 4);
buffer.Emit<OpCode::MovZX, 4, false, 2, false>(r11d, rdi, 4);
buffer.Emit<OpCode::MovZX>(r11, sil);
buffer.Emit<OpCode::MovZX>(r11, di);
buffer.Emit<OpCode::MovZX, 8, false, 1, false>(r11, rdi, 4);
buffer.Emit<OpCode::MovZX, 8, false, 2, false>(r11, rdi, 4);
// Source: rdi, target: r12
buffer.EmitImmediate<OpCode::Mov>(r12b, static_cast<uint8_t>(1));
buffer.EmitImmediate<OpCode::Mov>(r12w, static_cast<uint16_t>(1));
buffer.EmitImmediate<OpCode::Mov>(r12d, 1);
buffer.EmitImmediate<OpCode::Mov>(r12, 1);
buffer.Emit<OpCode::Mov>(r12b, sil);
buffer.Emit<OpCode::Mov>(r12w, di);
buffer.Emit<OpCode::Mov>(r12d, edi);
buffer.Emit<OpCode::Mov>(r12, rdi);
buffer.Emit<OpCode::Mov>(r12b, rdi, -4);
buffer.Emit<OpCode::Mov>(r12b, rdi, 4);
buffer.Emit<OpCode::Mov>(r12w, rdi, 4);
buffer.Emit<OpCode::Mov>(r12d, rdi, 4);
buffer.Emit<OpCode::Mov>(r12, rdi, 4);
buffer.Emit<OpCode::Mov>(r12, -4, sil);
buffer.Emit<OpCode::Mov>(r12, 4, sil);
buffer.Emit<OpCode::Mov>(r12, 4, di);
buffer.Emit<OpCode::Mov>(r12, 4, edi);
buffer.Emit<OpCode::Mov>(r12, 4, rdi);
buffer.Emit<OpCode::MovZX>(r12w, sil);
buffer.Emit<OpCode::MovZX, 2, false, 1, false>(r12w, rdi, 4);
buffer.Emit<OpCode::MovZX>(r12d, sil);
buffer.Emit<OpCode::MovZX>(r12d, di);
buffer.Emit<OpCode::MovZX, 4, false, 1, false>(r12d, rdi, 4);
buffer.Emit<OpCode::MovZX, 4, false, 2, false>(r12d, rdi, 4);
buffer.Emit<OpCode::MovZX>(r12, sil);
buffer.Emit<OpCode::MovZX>(r12, di);
buffer.Emit<OpCode::MovZX, 8, false, 1, false>(r12, rdi, 4);
buffer.Emit<OpCode::MovZX, 8, false, 2, false>(r12, rdi, 4);
// Source: rdi, target: r13
buffer.EmitImmediate<OpCode::Mov>(r13b, static_cast<uint8_t>(1));
buffer.EmitImmediate<OpCode::Mov>(r13w, static_cast<uint16_t>(1));
buffer.EmitImmediate<OpCode::Mov>(r13d, 1);
buffer.EmitImmediate<OpCode::Mov>(r13, 1);
buffer.Emit<OpCode::Mov>(r13b, sil);
buffer.Emit<OpCode::Mov>(r13w, di);
buffer.Emit<OpCode::Mov>(r13d, edi);
buffer.Emit<OpCode::Mov>(r13, rdi);
buffer.Emit<OpCode::Mov>(r13b, rdi, -4);
buffer.Emit<OpCode::Mov>(r13b, rdi, 4);
buffer.Emit<OpCode::Mov>(r13w, rdi, 4);
buffer.Emit<OpCode::Mov>(r13d, rdi, 4);
buffer.Emit<OpCode::Mov>(r13, rdi, 4);
buffer.Emit<OpCode::Mov>(r13, -4, sil);
buffer.Emit<OpCode::Mov>(r13, 4, sil);
buffer.Emit<OpCode::Mov>(r13, 4, di);
buffer.Emit<OpCode::Mov>(r13, 4, edi);
buffer.Emit<OpCode::Mov>(r13, 4, rdi);
buffer.Emit<OpCode::MovZX>(r13w, sil);
buffer.Emit<OpCode::MovZX, 2, false, 1, false>(r13w, rdi, 4);
buffer.Emit<OpCode::MovZX>(r13d, sil);
buffer.Emit<OpCode::MovZX>(r13d, di);
buffer.Emit<OpCode::MovZX, 4, false, 1, false>(r13d, rdi, 4);
buffer.Emit<OpCode::MovZX, 4, false, 2, false>(r13d, rdi, 4);
buffer.Emit<OpCode::MovZX>(r13, sil);
buffer.Emit<OpCode::MovZX>(r13, di);
buffer.Emit<OpCode::MovZX, 8, false, 1, false>(r13, rdi, 4);
buffer.Emit<OpCode::MovZX, 8, false, 2, false>(r13, rdi, 4);
// Source: rdi, target: r14
buffer.EmitImmediate<OpCode::Mov>(r14b, static_cast<uint8_t>(1));
buffer.EmitImmediate<OpCode::Mov>(r14w, static_cast<uint16_t>(1));
buffer.EmitImmediate<OpCode::Mov>(r14d, 1);
buffer.EmitImmediate<OpCode::Mov>(r14, 1);
buffer.Emit<OpCode::Mov>(r14b, sil);
buffer.Emit<OpCode::Mov>(r14w, di);
buffer.Emit<OpCode::Mov>(r14d, edi);
buffer.Emit<OpCode::Mov>(r14, rdi);
buffer.Emit<OpCode::Mov>(r14b, rdi, -4);
buffer.Emit<OpCode::Mov>(r14b, rdi, 4);
buffer.Emit<OpCode::Mov>(r14w, rdi, 4);
buffer.Emit<OpCode::Mov>(r14d, rdi, 4);
buffer.Emit<OpCode::Mov>(r14, rdi, 4);
buffer.Emit<OpCode::Mov>(r14, -4, sil);
buffer.Emit<OpCode::Mov>(r14, 4, sil);
buffer.Emit<OpCode::Mov>(r14, 4, di);
buffer.Emit<OpCode::Mov>(r14, 4, edi);
buffer.Emit<OpCode::Mov>(r14, 4, rdi);
buffer.Emit<OpCode::MovZX>(r14w, sil);
buffer.Emit<OpCode::MovZX, 2, false, 1, false>(r14w, rdi, 4);
buffer.Emit<OpCode::MovZX>(r14d, sil);
buffer.Emit<OpCode::MovZX>(r14d, di);
buffer.Emit<OpCode::MovZX, 4, false, 1, false>(r14d, rdi, 4);
buffer.Emit<OpCode::MovZX, 4, false, 2, false>(r14d, rdi, 4);
buffer.Emit<OpCode::MovZX>(r14, sil);
buffer.Emit<OpCode::MovZX>(r14, di);
buffer.Emit<OpCode::MovZX, 8, false, 1, false>(r14, rdi, 4);
buffer.Emit<OpCode::MovZX, 8, false, 2, false>(r14, rdi, 4);
// Source: rdi, target: r15
buffer.EmitImmediate<OpCode::Mov>(r15b, static_cast<uint8_t>(1));
buffer.EmitImmediate<OpCode::Mov>(r15w, static_cast<uint16_t>(1));
buffer.EmitImmediate<OpCode::Mov>(r15d, 1);
buffer.EmitImmediate<OpCode::Mov>(r15, 1);
buffer.Emit<OpCode::Mov>(r15b, sil);
buffer.Emit<OpCode::Mov>(r15w, di);
buffer.Emit<OpCode::Mov>(r15d, edi);
buffer.Emit<OpCode::Mov>(r15, rdi);
buffer.Emit<OpCode::Mov>(r15b, rdi, -4);
buffer.Emit<OpCode::Mov>(r15b, rdi, 4);
buffer.Emit<OpCode::Mov>(r15w, rdi, 4);
buffer.Emit<OpCode::Mov>(r15d, rdi, 4);
buffer.Emit<OpCode::Mov>(r15, rdi, 4);
buffer.Emit<OpCode::Mov>(r15, -4, sil);
buffer.Emit<OpCode::Mov>(r15, 4, sil);
buffer.Emit<OpCode::Mov>(r15, 4, di);
buffer.Emit<OpCode::Mov>(r15, 4, edi);
buffer.Emit<OpCode::Mov>(r15, 4, rdi);
buffer.Emit<OpCode::MovZX>(r15w, sil);
buffer.Emit<OpCode::MovZX, 2, false, 1, false>(r15w, rdi, 4);
buffer.Emit<OpCode::MovZX>(r15d, sil);
buffer.Emit<OpCode::MovZX>(r15d, di);
buffer.Emit<OpCode::MovZX, 4, false, 1, false>(r15d, rdi, 4);
buffer.Emit<OpCode::MovZX, 4, false, 2, false>(r15d, rdi, 4);
buffer.Emit<OpCode::MovZX>(r15, sil);
buffer.Emit<OpCode::MovZX>(r15, di);
buffer.Emit<OpCode::MovZX, 8, false, 1, false>(r15, rdi, 4);
buffer.Emit<OpCode::MovZX, 8, false, 2, false>(r15, rdi, 4);
// Source: r8, target: rax
buffer.EmitImmediate<OpCode::Mov>(al, static_cast<uint8_t>(1));
buffer.EmitImmediate<OpCode::Mov>(ax, static_cast<uint16_t>(1));
buffer.EmitImmediate<OpCode::Mov>(eax, 1);
buffer.EmitImmediate<OpCode::Mov>(rax, 1);
buffer.Emit<OpCode::Mov>(al, r8b);
buffer.Emit<OpCode::Mov>(ax, r8w);
buffer.Emit<OpCode::Mov>(eax, r8d);
buffer.Emit<OpCode::Mov>(rax, r8);
buffer.Emit<OpCode::Mov>(al, r8, -4);
buffer.Emit<OpCode::Mov>(al, r8, 4);
buffer.Emit<OpCode::Mov>(ax, r8, 4);
buffer.Emit<OpCode::Mov>(eax, r8, 4);
buffer.Emit<OpCode::Mov>(rax, r8, 4);
buffer.Emit<OpCode::Mov>(rax, -4, r8b);
buffer.Emit<OpCode::Mov>(rax, 4, r8b);
buffer.Emit<OpCode::Mov>(rax, 4, r8w);
buffer.Emit<OpCode::Mov>(rax, 4, r8d);
buffer.Emit<OpCode::Mov>(rax, 4, r8);
buffer.Emit<OpCode::MovZX>(ax, r8b);
buffer.Emit<OpCode::MovZX, 2, false, 1, false>(ax, r8, 4);
buffer.Emit<OpCode::MovZX>(eax, r8b);
buffer.Emit<OpCode::MovZX>(eax, r8w);
buffer.Emit<OpCode::MovZX, 4, false, 1, false>(eax, r8, 4);
buffer.Emit<OpCode::MovZX, 4, false, 2, false>(eax, r8, 4);
buffer.Emit<OpCode::MovZX>(rax, r8b);
buffer.Emit<OpCode::MovZX>(rax, r8w);
buffer.Emit<OpCode::MovZX, 8, false, 1, false>(rax, r8, 4);
buffer.Emit<OpCode::MovZX, 8, false, 2, false>(rax, r8, 4);
// Source: r8, target: rcx
buffer.EmitImmediate<OpCode::Mov>(cl, static_cast<uint8_t>(1));
buffer.EmitImmediate<OpCode::Mov>(cx, static_cast<uint16_t>(1));
buffer.EmitImmediate<OpCode::Mov>(ecx, 1);
buffer.EmitImmediate<OpCode::Mov>(rcx, 1);
buffer.Emit<OpCode::Mov>(cl, r8b);
buffer.Emit<OpCode::Mov>(cx, r8w);
buffer.Emit<OpCode::Mov>(ecx, r8d);
buffer.Emit<OpCode::Mov>(rcx, r8);
buffer.Emit<OpCode::Mov>(cl, r8, -4);
buffer.Emit<OpCode::Mov>(cl, r8, 4);
buffer.Emit<OpCode::Mov>(cx, r8, 4);
buffer.Emit<OpCode::Mov>(ecx, r8, 4);
buffer.Emit<OpCode::Mov>(rcx, r8, 4);
buffer.Emit<OpCode::Mov>(rcx, -4, r8b);
buffer.Emit<OpCode::Mov>(rcx, 4, r8b);
buffer.Emit<OpCode::Mov>(rcx, 4, r8w);
buffer.Emit<OpCode::Mov>(rcx, 4, r8d);
buffer.Emit<OpCode::Mov>(rcx, 4, r8);
buffer.Emit<OpCode::MovZX>(cx, r8b);
buffer.Emit<OpCode::MovZX, 2, false, 1, false>(cx, r8, 4);
buffer.Emit<OpCode::MovZX>(ecx, r8b);
buffer.Emit<OpCode::MovZX>(ecx, r8w);
buffer.Emit<OpCode::MovZX, 4, false, 1, false>(ecx, r8, 4);
buffer.Emit<OpCode::MovZX, 4, false, 2, false>(ecx, r8, 4);
buffer.Emit<OpCode::MovZX>(rcx, r8b);
buffer.Emit<OpCode::MovZX>(rcx, r8w);
buffer.Emit<OpCode::MovZX, 8, false, 1, false>(rcx, r8, 4);
buffer.Emit<OpCode::MovZX, 8, false, 2, false>(rcx, r8, 4);
// Source: r8, target: rdx
buffer.EmitImmediate<OpCode::Mov>(dl, static_cast<uint8_t>(1));
buffer.EmitImmediate<OpCode::Mov>(dx, static_cast<uint16_t>(1));
buffer.EmitImmediate<OpCode::Mov>(edx, 1);
buffer.EmitImmediate<OpCode::Mov>(rdx, 1);
buffer.Emit<OpCode::Mov>(dl, r8b);
buffer.Emit<OpCode::Mov>(dx, r8w);
buffer.Emit<OpCode::Mov>(edx, r8d);
buffer.Emit<OpCode::Mov>(rdx, r8);
buffer.Emit<OpCode::Mov>(dl, r8, -4);
buffer.Emit<OpCode::Mov>(dl, r8, 4);
buffer.Emit<OpCode::Mov>(dx, r8, 4);
buffer.Emit<OpCode::Mov>(edx, r8, 4);
buffer.Emit<OpCode::Mov>(rdx, r8, 4);
buffer.Emit<OpCode::Mov>(rdx, -4, r8b);
buffer.Emit<OpCode::Mov>(rdx, 4, r8b);
buffer.Emit<OpCode::Mov>(rdx, 4, r8w);
buffer.Emit<OpCode::Mov>(rdx, 4, r8d);
buffer.Emit<OpCode::Mov>(rdx, 4, r8);
buffer.Emit<OpCode::MovZX>(dx, r8b);
buffer.Emit<OpCode::MovZX, 2, false, 1, false>(dx, r8, 4);
buffer.Emit<OpCode::MovZX>(edx, r8b);
buffer.Emit<OpCode::MovZX>(edx, r8w);
buffer.Emit<OpCode::MovZX, 4, false, 1, false>(edx, r8, 4);
buffer.Emit<OpCode::MovZX, 4, false, 2, false>(edx, r8, 4);
buffer.Emit<OpCode::MovZX>(rdx, r8b);
buffer.Emit<OpCode::MovZX>(rdx, r8w);
buffer.Emit<OpCode::MovZX, 8, false, 1, false>(rdx, r8, 4);
buffer.Emit<OpCode::MovZX, 8, false, 2, false>(rdx, r8, 4);
// Source: r8, target: rbx
buffer.EmitImmediate<OpCode::Mov>(bl, static_cast<uint8_t>(1));
buffer.EmitImmediate<OpCode::Mov>(bx, static_cast<uint16_t>(1));
buffer.EmitImmediate<OpCode::Mov>(ebx, 1);
buffer.EmitImmediate<OpCode::Mov>(rbx, 1);
buffer.Emit<OpCode::Mov>(bl, r8b);
buffer.Emit<OpCode::Mov>(bx, r8w);
buffer.Emit<OpCode::Mov>(ebx, r8d);
buffer.Emit<OpCode::Mov>(rbx, r8);
buffer.Emit<OpCode::Mov>(bl, r8, -4);
buffer.Emit<OpCode::Mov>(bl, r8, 4);
buffer.Emit<OpCode::Mov>(bx, r8, 4);
buffer.Emit<OpCode::Mov>(ebx, r8, 4);
buffer.Emit<OpCode::Mov>(rbx, r8, 4);
buffer.Emit<OpCode::Mov>(rbx, -4, r8b);
buffer.Emit<OpCode::Mov>(rbx, 4, r8b);
buffer.Emit<OpCode::Mov>(rbx, 4, r8w);
buffer.Emit<OpCode::Mov>(rbx, 4, r8d);
buffer.Emit<OpCode::Mov>(rbx, 4, r8);
buffer.Emit<OpCode::MovZX>(bx, r8b);
buffer.Emit<OpCode::MovZX, 2, false, 1, false>(bx, r8, 4);
buffer.Emit<OpCode::MovZX>(ebx, r8b);
buffer.Emit<OpCode::MovZX>(ebx, r8w);
buffer.Emit<OpCode::MovZX, 4, false, 1, false>(ebx, r8, 4);
buffer.Emit<OpCode::MovZX, 4, false, 2, false>(ebx, r8, 4);
buffer.Emit<OpCode::MovZX>(rbx, r8b);
buffer.Emit<OpCode::MovZX>(rbx, r8w);
buffer.Emit<OpCode::MovZX, 8, false, 1, false>(rbx, r8, 4);
buffer.Emit<OpCode::MovZX, 8, false, 2, false>(rbx, r8, 4);
// Source: r8, target: rsp
buffer.EmitImmediate<OpCode::Mov>(spl, static_cast<uint8_t>(1));
buffer.EmitImmediate<OpCode::Mov>(sp, static_cast<uint16_t>(1));
buffer.EmitImmediate<OpCode::Mov>(esp, 1);
buffer.EmitImmediate<OpCode::Mov>(rsp, 1);
buffer.Emit<OpCode::Mov>(spl, r8b);
buffer.Emit<OpCode::Mov>(sp, r8w);
buffer.Emit<OpCode::Mov>(esp, r8d);
buffer.Emit<OpCode::Mov>(rsp, r8);
buffer.Emit<OpCode::Mov>(spl, r8, -4);
buffer.Emit<OpCode::Mov>(spl, r8, 4);
buffer.Emit<OpCode::Mov>(sp, r8, 4);
buffer.Emit<OpCode::Mov>(esp, r8, 4);
buffer.Emit<OpCode::Mov>(rsp, r8, 4);
buffer.Emit<OpCode::Mov>(rsp, -4, r8b);
buffer.Emit<OpCode::Mov>(rsp, 4, r8b);
buffer.Emit<OpCode::Mov>(rsp, 4, r8w);
buffer.Emit<OpCode::Mov>(rsp, 4, r8d);
buffer.Emit<OpCode::Mov>(rsp, 4, r8);
buffer.Emit<OpCode::MovZX>(sp, r8b);
buffer.Emit<OpCode::MovZX, 2, false, 1, false>(sp, r8, 4);
buffer.Emit<OpCode::MovZX>(esp, r8b);
buffer.Emit<OpCode::MovZX>(esp, r8w);
buffer.Emit<OpCode::MovZX, 4, false, 1, false>(esp, r8, 4);
buffer.Emit<OpCode::MovZX, 4, false, 2, false>(esp, r8, 4);
buffer.Emit<OpCode::MovZX>(rsp, r8b);
buffer.Emit<OpCode::MovZX>(rsp, r8w);
buffer.Emit<OpCode::MovZX, 8, false, 1, false>(rsp, r8, 4);
buffer.Emit<OpCode::MovZX, 8, false, 2, false>(rsp, r8, 4);
// Source: r8, target: rbp
buffer.EmitImmediate<OpCode::Mov>(bpl, static_cast<uint8_t>(1));
buffer.EmitImmediate<OpCode::Mov>(bp, static_cast<uint16_t>(1));
buffer.EmitImmediate<OpCode::Mov>(ebp, 1);
buffer.EmitImmediate<OpCode::Mov>(rbp, 1);
buffer.Emit<OpCode::Mov>(bpl, r8b);
buffer.Emit<OpCode::Mov>(bp, r8w);
buffer.Emit<OpCode::Mov>(ebp, r8d);
buffer.Emit<OpCode::Mov>(rbp, r8);
buffer.Emit<OpCode::Mov>(bpl, r8, -4);
buffer.Emit<OpCode::Mov>(bpl, r8, 4);
buffer.Emit<OpCode::Mov>(bp, r8, 4);
buffer.Emit<OpCode::Mov>(ebp, r8, 4);
buffer.Emit<OpCode::Mov>(rbp, r8, 4);
buffer.Emit<OpCode::Mov>(rbp, -4, r8b);
buffer.Emit<OpCode::Mov>(rbp, 4, r8b);
buffer.Emit<OpCode::Mov>(rbp, 4, r8w);
buffer.Emit<OpCode::Mov>(rbp, 4, r8d);
buffer.Emit<OpCode::Mov>(rbp, 4, r8);
buffer.Emit<OpCode::MovZX>(bp, r8b);
buffer.Emit<OpCode::MovZX, 2, false, 1, false>(bp, r8, 4);
buffer.Emit<OpCode::MovZX>(ebp, r8b);
buffer.Emit<OpCode::MovZX>(ebp, r8w);
buffer.Emit<OpCode::MovZX, 4, false, 1, false>(ebp, r8, 4);
buffer.Emit<OpCode::MovZX, 4, false, 2, false>(ebp, r8, 4);
buffer.Emit<OpCode::MovZX>(rbp, r8b);
buffer.Emit<OpCode::MovZX>(rbp, r8w);
buffer.Emit<OpCode::MovZX, 8, false, 1, false>(rbp, r8, 4);
buffer.Emit<OpCode::MovZX, 8, false, 2, false>(rbp, r8, 4);
// Source: r8, target: rsi
buffer.EmitImmediate<OpCode::Mov>(dil, static_cast<uint8_t>(1));
buffer.EmitImmediate<OpCode::Mov>(si, static_cast<uint16_t>(1));
buffer.EmitImmediate<OpCode::Mov>(esi, 1);
buffer.EmitImmediate<OpCode::Mov>(rsi, 1);
buffer.Emit<OpCode::Mov>(dil, r8b);
buffer.Emit<OpCode::Mov>(si, r8w);
buffer.Emit<OpCode::Mov>(esi, r8d);
buffer.Emit<OpCode::Mov>(rsi, r8);
buffer.Emit<OpCode::Mov>(dil, r8, -4);
buffer.Emit<OpCode::Mov>(dil, r8, 4);
buffer.Emit<OpCode::Mov>(si, r8, 4);
buffer.Emit<OpCode::Mov>(esi, r8, 4);
buffer.Emit<OpCode::Mov>(rsi, r8, 4);
buffer.Emit<OpCode::Mov>(rsi, -4, r8b);
buffer.Emit<OpCode::Mov>(rsi, 4, r8b);
buffer.Emit<OpCode::Mov>(rsi, 4, r8w);
buffer.Emit<OpCode::Mov>(rsi, 4, r8d);
buffer.Emit<OpCode::Mov>(rsi, 4, r8);
buffer.Emit<OpCode::MovZX>(si, r8b);
buffer.Emit<OpCode::MovZX, 2, false, 1, false>(si, r8, 4);
buffer.Emit<OpCode::MovZX>(esi, r8b);
buffer.Emit<OpCode::MovZX>(esi, r8w);
buffer.Emit<OpCode::MovZX, 4, false, 1, false>(esi, r8, 4);
buffer.Emit<OpCode::MovZX, 4, false, 2, false>(esi, r8, 4);
buffer.Emit<OpCode::MovZX>(rsi, r8b);
buffer.Emit<OpCode::MovZX>(rsi, r8w);
buffer.Emit<OpCode::MovZX, 8, false, 1, false>(rsi, r8, 4);
buffer.Emit<OpCode::MovZX, 8, false, 2, false>(rsi, r8, 4);
// Source: r8, target: rdi
buffer.EmitImmediate<OpCode::Mov>(sil, static_cast<uint8_t>(1));
buffer.EmitImmediate<OpCode::Mov>(di, static_cast<uint16_t>(1));
buffer.EmitImmediate<OpCode::Mov>(edi, 1);
buffer.EmitImmediate<OpCode::Mov>(rdi, 1);
buffer.Emit<OpCode::Mov>(sil, r8b);
buffer.Emit<OpCode::Mov>(di, r8w);
buffer.Emit<OpCode::Mov>(edi, r8d);
buffer.Emit<OpCode::Mov>(rdi, r8);
buffer.Emit<OpCode::Mov>(sil, r8, -4);
buffer.Emit<OpCode::Mov>(sil, r8, 4);
buffer.Emit<OpCode::Mov>(di, r8, 4);
buffer.Emit<OpCode::Mov>(edi, r8, 4);
buffer.Emit<OpCode::Mov>(rdi, r8, 4);
buffer.Emit<OpCode::Mov>(rdi, -4, r8b);
buffer.Emit<OpCode::Mov>(rdi, 4, r8b);
buffer.Emit<OpCode::Mov>(rdi, 4, r8w);
buffer.Emit<OpCode::Mov>(rdi, 4, r8d);
buffer.Emit<OpCode::Mov>(rdi, 4, r8);
buffer.Emit<OpCode::MovZX>(di, r8b);
buffer.Emit<OpCode::MovZX, 2, false, 1, false>(di, r8, 4);
buffer.Emit<OpCode::MovZX>(edi, r8b);
buffer.Emit<OpCode::MovZX>(edi, r8w);
buffer.Emit<OpCode::MovZX, 4, false, 1, false>(edi, r8, 4);
buffer.Emit<OpCode::MovZX, 4, false, 2, false>(edi, r8, 4);
buffer.Emit<OpCode::MovZX>(rdi, r8b);
buffer.Emit<OpCode::MovZX>(rdi, r8w);
buffer.Emit<OpCode::MovZX, 8, false, 1, false>(rdi, r8, 4);
buffer.Emit<OpCode::MovZX, 8, false, 2, false>(rdi, r8, 4);
// Source: r8, target: r8
buffer.EmitImmediate<OpCode::Mov>(r8b, static_cast<uint8_t>(1));
buffer.EmitImmediate<OpCode::Mov>(r8w, static_cast<uint16_t>(1));
buffer.EmitImmediate<OpCode::Mov>(r8d, 1);
buffer.EmitImmediate<OpCode::Mov>(r8, 1);
buffer.Emit<OpCode::Mov>(r8b, r8b);
buffer.Emit<OpCode::Mov>(r8w, r8w);
buffer.Emit<OpCode::Mov>(r8d, r8d);
buffer.Emit<OpCode::Mov>(r8, r8);
buffer.Emit<OpCode::Mov>(r8b, r8, -4);
buffer.Emit<OpCode::Mov>(r8b, r8, 4);
buffer.Emit<OpCode::Mov>(r8w, r8, 4);
buffer.Emit<OpCode::Mov>(r8d, r8, 4);
buffer.Emit<OpCode::Mov>(r8, r8, 4);
buffer.Emit<OpCode::Mov>(r8, -4, r8b);
buffer.Emit<OpCode::Mov>(r8, 4, r8b);
buffer.Emit<OpCode::Mov>(r8, 4, r8w);
buffer.Emit<OpCode::Mov>(r8, 4, r8d);
buffer.Emit<OpCode::Mov>(r8, 4, r8);
buffer.Emit<OpCode::MovZX>(r8w, r8b);
buffer.Emit<OpCode::MovZX, 2, false, 1, false>(r8w, r8, 4);
buffer.Emit<OpCode::MovZX>(r8d, r8b);
buffer.Emit<OpCode::MovZX>(r8d, r8w);
buffer.Emit<OpCode::MovZX, 4, false, 1, false>(r8d, r8, 4);
buffer.Emit<OpCode::MovZX, 4, false, 2, false>(r8d, r8, 4);
buffer.Emit<OpCode::MovZX>(r8, r8b);
buffer.Emit<OpCode::MovZX>(r8, r8w);
buffer.Emit<OpCode::MovZX, 8, false, 1, false>(r8, r8, 4);
buffer.Emit<OpCode::MovZX, 8, false, 2, false>(r8, r8, 4);
// Source: r8, target: r9
buffer.EmitImmediate<OpCode::Mov>(r9b, static_cast<uint8_t>(1));
buffer.EmitImmediate<OpCode::Mov>(r9w, static_cast<uint16_t>(1));
buffer.EmitImmediate<OpCode::Mov>(r9d, 1);
buffer.EmitImmediate<OpCode::Mov>(r9, 1);
buffer.Emit<OpCode::Mov>(r9b, r8b);
buffer.Emit<OpCode::Mov>(r9w, r8w);
buffer.Emit<OpCode::Mov>(r9d, r8d);
buffer.Emit<OpCode::Mov>(r9, r8);
buffer.Emit<OpCode::Mov>(r9b, r8, -4);
buffer.Emit<OpCode::Mov>(r9b, r8, 4);
buffer.Emit<OpCode::Mov>(r9w, r8, 4);
buffer.Emit<OpCode::Mov>(r9d, r8, 4);
buffer.Emit<OpCode::Mov>(r9, r8, 4);
buffer.Emit<OpCode::Mov>(r9, -4, r8b);
buffer.Emit<OpCode::Mov>(r9, 4, r8b);
buffer.Emit<OpCode::Mov>(r9, 4, r8w);
buffer.Emit<OpCode::Mov>(r9, 4, r8d);
buffer.Emit<OpCode::Mov>(r9, 4, r8);
buffer.Emit<OpCode::MovZX>(r9w, r8b);
buffer.Emit<OpCode::MovZX, 2, false, 1, false>(r9w, r8, 4);
buffer.Emit<OpCode::MovZX>(r9d, r8b);
buffer.Emit<OpCode::MovZX>(r9d, r8w);
buffer.Emit<OpCode::MovZX, 4, false, 1, false>(r9d, r8, 4);
buffer.Emit<OpCode::MovZX, 4, false, 2, false>(r9d, r8, 4);
buffer.Emit<OpCode::MovZX>(r9, r8b);
buffer.Emit<OpCode::MovZX>(r9, r8w);
buffer.Emit<OpCode::MovZX, 8, false, 1, false>(r9, r8, 4);
buffer.Emit<OpCode::MovZX, 8, false, 2, false>(r9, r8, 4);
// Source: r8, target: r10
buffer.EmitImmediate<OpCode::Mov>(r10b, static_cast<uint8_t>(1));
buffer.EmitImmediate<OpCode::Mov>(r10w, static_cast<uint16_t>(1));
buffer.EmitImmediate<OpCode::Mov>(r10d, 1);
buffer.EmitImmediate<OpCode::Mov>(r10, 1);
buffer.Emit<OpCode::Mov>(r10b, r8b);
buffer.Emit<OpCode::Mov>(r10w, r8w);
buffer.Emit<OpCode::Mov>(r10d, r8d);
buffer.Emit<OpCode::Mov>(r10, r8);
buffer.Emit<OpCode::Mov>(r10b, r8, -4);
buffer.Emit<OpCode::Mov>(r10b, r8, 4);
buffer.Emit<OpCode::Mov>(r10w, r8, 4);
buffer.Emit<OpCode::Mov>(r10d, r8, 4);
buffer.Emit<OpCode::Mov>(r10, r8, 4);
buffer.Emit<OpCode::Mov>(r10, -4, r8b);
buffer.Emit<OpCode::Mov>(r10, 4, r8b);
buffer.Emit<OpCode::Mov>(r10, 4, r8w);
buffer.Emit<OpCode::Mov>(r10, 4, r8d);
buffer.Emit<OpCode::Mov>(r10, 4, r8);
buffer.Emit<OpCode::MovZX>(r10w, r8b);
buffer.Emit<OpCode::MovZX, 2, false, 1, false>(r10w, r8, 4);
buffer.Emit<OpCode::MovZX>(r10d, r8b);
buffer.Emit<OpCode::MovZX>(r10d, r8w);
buffer.Emit<OpCode::MovZX, 4, false, 1, false>(r10d, r8, 4);
buffer.Emit<OpCode::MovZX, 4, false, 2, false>(r10d, r8, 4);
buffer.Emit<OpCode::MovZX>(r10, r8b);
buffer.Emit<OpCode::MovZX>(r10, r8w);
buffer.Emit<OpCode::MovZX, 8, false, 1, false>(r10, r8, 4);
buffer.Emit<OpCode::MovZX, 8, false, 2, false>(r10, r8, 4);
// Source: r8, target: r11
buffer.EmitImmediate<OpCode::Mov>(r11b, static_cast<uint8_t>(1));
buffer.EmitImmediate<OpCode::Mov>(r11w, static_cast<uint16_t>(1));
buffer.EmitImmediate<OpCode::Mov>(r11d, 1);
buffer.EmitImmediate<OpCode::Mov>(r11, 1);
buffer.Emit<OpCode::Mov>(r11b, r8b);
buffer.Emit<OpCode::Mov>(r11w, r8w);
buffer.Emit<OpCode::Mov>(r11d, r8d);
buffer.Emit<OpCode::Mov>(r11, r8);
buffer.Emit<OpCode::Mov>(r11b, r8, -4);
buffer.Emit<OpCode::Mov>(r11b, r8, 4);
buffer.Emit<OpCode::Mov>(r11w, r8, 4);
buffer.Emit<OpCode::Mov>(r11d, r8, 4);
buffer.Emit<OpCode::Mov>(r11, r8, 4);
buffer.Emit<OpCode::Mov>(r11, -4, r8b);
buffer.Emit<OpCode::Mov>(r11, 4, r8b);
buffer.Emit<OpCode::Mov>(r11, 4, r8w);
buffer.Emit<OpCode::Mov>(r11, 4, r8d);
buffer.Emit<OpCode::Mov>(r11, 4, r8);
buffer.Emit<OpCode::MovZX>(r11w, r8b);
buffer.Emit<OpCode::MovZX, 2, false, 1, false>(r11w, r8, 4);
buffer.Emit<OpCode::MovZX>(r11d, r8b);
buffer.Emit<OpCode::MovZX>(r11d, r8w);
buffer.Emit<OpCode::MovZX, 4, false, 1, false>(r11d, r8, 4);
buffer.Emit<OpCode::MovZX, 4, false, 2, false>(r11d, r8, 4);
buffer.Emit<OpCode::MovZX>(r11, r8b);
buffer.Emit<OpCode::MovZX>(r11, r8w);
buffer.Emit<OpCode::MovZX, 8, false, 1, false>(r11, r8, 4);
buffer.Emit<OpCode::MovZX, 8, false, 2, false>(r11, r8, 4);
// Source: r8, target: r12
buffer.EmitImmediate<OpCode::Mov>(r12b, static_cast<uint8_t>(1));
buffer.EmitImmediate<OpCode::Mov>(r12w, static_cast<uint16_t>(1));
buffer.EmitImmediate<OpCode::Mov>(r12d, 1);
buffer.EmitImmediate<OpCode::Mov>(r12, 1);
buffer.Emit<OpCode::Mov>(r12b, r8b);
buffer.Emit<OpCode::Mov>(r12w, r8w);
buffer.Emit<OpCode::Mov>(r12d, r8d);
buffer.Emit<OpCode::Mov>(r12, r8);
buffer.Emit<OpCode::Mov>(r12b, r8, -4);
buffer.Emit<OpCode::Mov>(r12b, r8, 4);
buffer.Emit<OpCode::Mov>(r12w, r8, 4);
buffer.Emit<OpCode::Mov>(r12d, r8, 4);
buffer.Emit<OpCode::Mov>(r12, r8, 4);
buffer.Emit<OpCode::Mov>(r12, -4, r8b);
buffer.Emit<OpCode::Mov>(r12, 4, r8b);
buffer.Emit<OpCode::Mov>(r12, 4, r8w);
buffer.Emit<OpCode::Mov>(r12, 4, r8d);
buffer.Emit<OpCode::Mov>(r12, 4, r8);
buffer.Emit<OpCode::MovZX>(r12w, r8b);
buffer.Emit<OpCode::MovZX, 2, false, 1, false>(r12w, r8, 4);
buffer.Emit<OpCode::MovZX>(r12d, r8b);
buffer.Emit<OpCode::MovZX>(r12d, r8w);
buffer.Emit<OpCode::MovZX, 4, false, 1, false>(r12d, r8, 4);
buffer.Emit<OpCode::MovZX, 4, false, 2, false>(r12d, r8, 4);
buffer.Emit<OpCode::MovZX>(r12, r8b);
buffer.Emit<OpCode::MovZX>(r12, r8w);
buffer.Emit<OpCode::MovZX, 8, false, 1, false>(r12, r8, 4);
buffer.Emit<OpCode::MovZX, 8, false, 2, false>(r12, r8, 4);
// Source: r8, target: r13
buffer.EmitImmediate<OpCode::Mov>(r13b, static_cast<uint8_t>(1));
buffer.EmitImmediate<OpCode::Mov>(r13w, static_cast<uint16_t>(1));
buffer.EmitImmediate<OpCode::Mov>(r13d, 1);
buffer.EmitImmediate<OpCode::Mov>(r13, 1);
buffer.Emit<OpCode::Mov>(r13b, r8b);
buffer.Emit<OpCode::Mov>(r13w, r8w);
buffer.Emit<OpCode::Mov>(r13d, r8d);
buffer.Emit<OpCode::Mov>(r13, r8);
buffer.Emit<OpCode::Mov>(r13b, r8, -4);
buffer.Emit<OpCode::Mov>(r13b, r8, 4);
buffer.Emit<OpCode::Mov>(r13w, r8, 4);
buffer.Emit<OpCode::Mov>(r13d, r8, 4);
buffer.Emit<OpCode::Mov>(r13, r8, 4);
buffer.Emit<OpCode::Mov>(r13, -4, r8b);
buffer.Emit<OpCode::Mov>(r13, 4, r8b);
buffer.Emit<OpCode::Mov>(r13, 4, r8w);
buffer.Emit<OpCode::Mov>(r13, 4, r8d);
buffer.Emit<OpCode::Mov>(r13, 4, r8);
buffer.Emit<OpCode::MovZX>(r13w, r8b);
buffer.Emit<OpCode::MovZX, 2, false, 1, false>(r13w, r8, 4);
buffer.Emit<OpCode::MovZX>(r13d, r8b);
buffer.Emit<OpCode::MovZX>(r13d, r8w);
buffer.Emit<OpCode::MovZX, 4, false, 1, false>(r13d, r8, 4);
buffer.Emit<OpCode::MovZX, 4, false, 2, false>(r13d, r8, 4);
buffer.Emit<OpCode::MovZX>(r13, r8b);
buffer.Emit<OpCode::MovZX>(r13, r8w);
buffer.Emit<OpCode::MovZX, 8, false, 1, false>(r13, r8, 4);
buffer.Emit<OpCode::MovZX, 8, false, 2, false>(r13, r8, 4);
// Source: r8, target: r14
buffer.EmitImmediate<OpCode::Mov>(r14b, static_cast<uint8_t>(1));
buffer.EmitImmediate<OpCode::Mov>(r14w, static_cast<uint16_t>(1));
buffer.EmitImmediate<OpCode::Mov>(r14d, 1);
buffer.EmitImmediate<OpCode::Mov>(r14, 1);
buffer.Emit<OpCode::Mov>(r14b, r8b);
buffer.Emit<OpCode::Mov>(r14w, r8w);
buffer.Emit<OpCode::Mov>(r14d, r8d);
buffer.Emit<OpCode::Mov>(r14, r8);
buffer.Emit<OpCode::Mov>(r14b, r8, -4);
buffer.Emit<OpCode::Mov>(r14b, r8, 4);
buffer.Emit<OpCode::Mov>(r14w, r8, 4);
buffer.Emit<OpCode::Mov>(r14d, r8, 4);
buffer.Emit<OpCode::Mov>(r14, r8, 4);
buffer.Emit<OpCode::Mov>(r14, -4, r8b);
buffer.Emit<OpCode::Mov>(r14, 4, r8b);
buffer.Emit<OpCode::Mov>(r14, 4, r8w);
buffer.Emit<OpCode::Mov>(r14, 4, r8d);
buffer.Emit<OpCode::Mov>(r14, 4, r8);
buffer.Emit<OpCode::MovZX>(r14w, r8b);
buffer.Emit<OpCode::MovZX, 2, false, 1, false>(r14w, r8, 4);
buffer.Emit<OpCode::MovZX>(r14d, r8b);
buffer.Emit<OpCode::MovZX>(r14d, r8w);
buffer.Emit<OpCode::MovZX, 4, false, 1, false>(r14d, r8, 4);
buffer.Emit<OpCode::MovZX, 4, false, 2, false>(r14d, r8, 4);
buffer.Emit<OpCode::MovZX>(r14, r8b);
buffer.Emit<OpCode::MovZX>(r14, r8w);
buffer.Emit<OpCode::MovZX, 8, false, 1, false>(r14, r8, 4);
buffer.Emit<OpCode::MovZX, 8, false, 2, false>(r14, r8, 4);
// Source: r8, target: r15
buffer.EmitImmediate<OpCode::Mov>(r15b, static_cast<uint8_t>(1));
buffer.EmitImmediate<OpCode::Mov>(r15w, static_cast<uint16_t>(1));
buffer.EmitImmediate<OpCode::Mov>(r15d, 1);
buffer.EmitImmediate<OpCode::Mov>(r15, 1);
buffer.Emit<OpCode::Mov>(r15b, r8b);
buffer.Emit<OpCode::Mov>(r15w, r8w);
buffer.Emit<OpCode::Mov>(r15d, r8d);
buffer.Emit<OpCode::Mov>(r15, r8);
buffer.Emit<OpCode::Mov>(r15b, r8, -4);
buffer.Emit<OpCode::Mov>(r15b, r8, 4);
buffer.Emit<OpCode::Mov>(r15w, r8, 4);
buffer.Emit<OpCode::Mov>(r15d, r8, 4);
buffer.Emit<OpCode::Mov>(r15, r8, 4);
buffer.Emit<OpCode::Mov>(r15, -4, r8b);
buffer.Emit<OpCode::Mov>(r15, 4, r8b);
buffer.Emit<OpCode::Mov>(r15, 4, r8w);
buffer.Emit<OpCode::Mov>(r15, 4, r8d);
buffer.Emit<OpCode::Mov>(r15, 4, r8);
buffer.Emit<OpCode::MovZX>(r15w, r8b);
buffer.Emit<OpCode::MovZX, 2, false, 1, false>(r15w, r8, 4);
buffer.Emit<OpCode::MovZX>(r15d, r8b);
buffer.Emit<OpCode::MovZX>(r15d, r8w);
buffer.Emit<OpCode::MovZX, 4, false, 1, false>(r15d, r8, 4);
buffer.Emit<OpCode::MovZX, 4, false, 2, false>(r15d, r8, 4);
buffer.Emit<OpCode::MovZX>(r15, r8b);
buffer.Emit<OpCode::MovZX>(r15, r8w);
buffer.Emit<OpCode::MovZX, 8, false, 1, false>(r15, r8, 4);
buffer.Emit<OpCode::MovZX, 8, false, 2, false>(r15, r8, 4);
// Source: r9, target: rax
buffer.EmitImmediate<OpCode::Mov>(al, static_cast<uint8_t>(1));
buffer.EmitImmediate<OpCode::Mov>(ax, static_cast<uint16_t>(1));
buffer.EmitImmediate<OpCode::Mov>(eax, 1);
buffer.EmitImmediate<OpCode::Mov>(rax, 1);
buffer.Emit<OpCode::Mov>(al, r9b);
buffer.Emit<OpCode::Mov>(ax, r9w);
buffer.Emit<OpCode::Mov>(eax, r9d);
buffer.Emit<OpCode::Mov>(rax, r9);
buffer.Emit<OpCode::Mov>(al, r9, -4);
buffer.Emit<OpCode::Mov>(al, r9, 4);
buffer.Emit<OpCode::Mov>(ax, r9, 4);
buffer.Emit<OpCode::Mov>(eax, r9, 4);
buffer.Emit<OpCode::Mov>(rax, r9, 4);
buffer.Emit<OpCode::Mov>(rax, -4, r9b);
buffer.Emit<OpCode::Mov>(rax, 4, r9b);
buffer.Emit<OpCode::Mov>(rax, 4, r9w);
buffer.Emit<OpCode::Mov>(rax, 4, r9d);
buffer.Emit<OpCode::Mov>(rax, 4, r9);
buffer.Emit<OpCode::MovZX>(ax, r9b);
buffer.Emit<OpCode::MovZX, 2, false, 1, false>(ax, r9, 4);
buffer.Emit<OpCode::MovZX>(eax, r9b);
buffer.Emit<OpCode::MovZX>(eax, r9w);
buffer.Emit<OpCode::MovZX, 4, false, 1, false>(eax, r9, 4);
buffer.Emit<OpCode::MovZX, 4, false, 2, false>(eax, r9, 4);
buffer.Emit<OpCode::MovZX>(rax, r9b);
buffer.Emit<OpCode::MovZX>(rax, r9w);
buffer.Emit<OpCode::MovZX, 8, false, 1, false>(rax, r9, 4);
buffer.Emit<OpCode::MovZX, 8, false, 2, false>(rax, r9, 4);
// Source: r9, target: rcx
buffer.EmitImmediate<OpCode::Mov>(cl, static_cast<uint8_t>(1));
buffer.EmitImmediate<OpCode::Mov>(cx, static_cast<uint16_t>(1));
buffer.EmitImmediate<OpCode::Mov>(ecx, 1);
buffer.EmitImmediate<OpCode::Mov>(rcx, 1);
buffer.Emit<OpCode::Mov>(cl, r9b);
buffer.Emit<OpCode::Mov>(cx, r9w);
buffer.Emit<OpCode::Mov>(ecx, r9d);
buffer.Emit<OpCode::Mov>(rcx, r9);
buffer.Emit<OpCode::Mov>(cl, r9, -4);
buffer.Emit<OpCode::Mov>(cl, r9, 4);
buffer.Emit<OpCode::Mov>(cx, r9, 4);
buffer.Emit<OpCode::Mov>(ecx, r9, 4);
buffer.Emit<OpCode::Mov>(rcx, r9, 4);
buffer.Emit<OpCode::Mov>(rcx, -4, r9b);
buffer.Emit<OpCode::Mov>(rcx, 4, r9b);
buffer.Emit<OpCode::Mov>(rcx, 4, r9w);
buffer.Emit<OpCode::Mov>(rcx, 4, r9d);
buffer.Emit<OpCode::Mov>(rcx, 4, r9);
buffer.Emit<OpCode::MovZX>(cx, r9b);
buffer.Emit<OpCode::MovZX, 2, false, 1, false>(cx, r9, 4);
buffer.Emit<OpCode::MovZX>(ecx, r9b);
buffer.Emit<OpCode::MovZX>(ecx, r9w);
buffer.Emit<OpCode::MovZX, 4, false, 1, false>(ecx, r9, 4);
buffer.Emit<OpCode::MovZX, 4, false, 2, false>(ecx, r9, 4);
buffer.Emit<OpCode::MovZX>(rcx, r9b);
buffer.Emit<OpCode::MovZX>(rcx, r9w);
buffer.Emit<OpCode::MovZX, 8, false, 1, false>(rcx, r9, 4);
buffer.Emit<OpCode::MovZX, 8, false, 2, false>(rcx, r9, 4);
// Source: r9, target: rdx
buffer.EmitImmediate<OpCode::Mov>(dl, static_cast<uint8_t>(1));
buffer.EmitImmediate<OpCode::Mov>(dx, static_cast<uint16_t>(1));
buffer.EmitImmediate<OpCode::Mov>(edx, 1);
buffer.EmitImmediate<OpCode::Mov>(rdx, 1);
buffer.Emit<OpCode::Mov>(dl, r9b);
buffer.Emit<OpCode::Mov>(dx, r9w);
buffer.Emit<OpCode::Mov>(edx, r9d);
buffer.Emit<OpCode::Mov>(rdx, r9);
buffer.Emit<OpCode::Mov>(dl, r9, -4);
buffer.Emit<OpCode::Mov>(dl, r9, 4);
buffer.Emit<OpCode::Mov>(dx, r9, 4);
buffer.Emit<OpCode::Mov>(edx, r9, 4);
buffer.Emit<OpCode::Mov>(rdx, r9, 4);
buffer.Emit<OpCode::Mov>(rdx, -4, r9b);
buffer.Emit<OpCode::Mov>(rdx, 4, r9b);
buffer.Emit<OpCode::Mov>(rdx, 4, r9w);
buffer.Emit<OpCode::Mov>(rdx, 4, r9d);
buffer.Emit<OpCode::Mov>(rdx, 4, r9);
buffer.Emit<OpCode::MovZX>(dx, r9b);
buffer.Emit<OpCode::MovZX, 2, false, 1, false>(dx, r9, 4);
buffer.Emit<OpCode::MovZX>(edx, r9b);
buffer.Emit<OpCode::MovZX>(edx, r9w);
buffer.Emit<OpCode::MovZX, 4, false, 1, false>(edx, r9, 4);
buffer.Emit<OpCode::MovZX, 4, false, 2, false>(edx, r9, 4);
buffer.Emit<OpCode::MovZX>(rdx, r9b);
buffer.Emit<OpCode::MovZX>(rdx, r9w);
buffer.Emit<OpCode::MovZX, 8, false, 1, false>(rdx, r9, 4);
buffer.Emit<OpCode::MovZX, 8, false, 2, false>(rdx, r9, 4);
// Source: r9, target: rbx
buffer.EmitImmediate<OpCode::Mov>(bl, static_cast<uint8_t>(1));
buffer.EmitImmediate<OpCode::Mov>(bx, static_cast<uint16_t>(1));
buffer.EmitImmediate<OpCode::Mov>(ebx, 1);
buffer.EmitImmediate<OpCode::Mov>(rbx, 1);
buffer.Emit<OpCode::Mov>(bl, r9b);
buffer.Emit<OpCode::Mov>(bx, r9w);
buffer.Emit<OpCode::Mov>(ebx, r9d);
buffer.Emit<OpCode::Mov>(rbx, r9);
buffer.Emit<OpCode::Mov>(bl, r9, -4);
buffer.Emit<OpCode::Mov>(bl, r9, 4);
buffer.Emit<OpCode::Mov>(bx, r9, 4);
buffer.Emit<OpCode::Mov>(ebx, r9, 4);
buffer.Emit<OpCode::Mov>(rbx, r9, 4);
buffer.Emit<OpCode::Mov>(rbx, -4, r9b);
buffer.Emit<OpCode::Mov>(rbx, 4, r9b);
buffer.Emit<OpCode::Mov>(rbx, 4, r9w);
buffer.Emit<OpCode::Mov>(rbx, 4, r9d);
buffer.Emit<OpCode::Mov>(rbx, 4, r9);
buffer.Emit<OpCode::MovZX>(bx, r9b);
buffer.Emit<OpCode::MovZX, 2, false, 1, false>(bx, r9, 4);
buffer.Emit<OpCode::MovZX>(ebx, r9b);
buffer.Emit<OpCode::MovZX>(ebx, r9w);
buffer.Emit<OpCode::MovZX, 4, false, 1, false>(ebx, r9, 4);
buffer.Emit<OpCode::MovZX, 4, false, 2, false>(ebx, r9, 4);
buffer.Emit<OpCode::MovZX>(rbx, r9b);
buffer.Emit<OpCode::MovZX>(rbx, r9w);
buffer.Emit<OpCode::MovZX, 8, false, 1, false>(rbx, r9, 4);
buffer.Emit<OpCode::MovZX, 8, false, 2, false>(rbx, r9, 4);
// Source: r9, target: rsp
buffer.EmitImmediate<OpCode::Mov>(spl, static_cast<uint8_t>(1));
buffer.EmitImmediate<OpCode::Mov>(sp, static_cast<uint16_t>(1));
buffer.EmitImmediate<OpCode::Mov>(esp, 1);
buffer.EmitImmediate<OpCode::Mov>(rsp, 1);
buffer.Emit<OpCode::Mov>(spl, r9b);
buffer.Emit<OpCode::Mov>(sp, r9w);
buffer.Emit<OpCode::Mov>(esp, r9d);
buffer.Emit<OpCode::Mov>(rsp, r9);
buffer.Emit<OpCode::Mov>(spl, r9, -4);
buffer.Emit<OpCode::Mov>(spl, r9, 4);
buffer.Emit<OpCode::Mov>(sp, r9, 4);
buffer.Emit<OpCode::Mov>(esp, r9, 4);
buffer.Emit<OpCode::Mov>(rsp, r9, 4);
buffer.Emit<OpCode::Mov>(rsp, -4, r9b);
buffer.Emit<OpCode::Mov>(rsp, 4, r9b);
buffer.Emit<OpCode::Mov>(rsp, 4, r9w);
buffer.Emit<OpCode::Mov>(rsp, 4, r9d);
buffer.Emit<OpCode::Mov>(rsp, 4, r9);
buffer.Emit<OpCode::MovZX>(sp, r9b);
buffer.Emit<OpCode::MovZX, 2, false, 1, false>(sp, r9, 4);
buffer.Emit<OpCode::MovZX>(esp, r9b);
buffer.Emit<OpCode::MovZX>(esp, r9w);
buffer.Emit<OpCode::MovZX, 4, false, 1, false>(esp, r9, 4);
buffer.Emit<OpCode::MovZX, 4, false, 2, false>(esp, r9, 4);
buffer.Emit<OpCode::MovZX>(rsp, r9b);
buffer.Emit<OpCode::MovZX>(rsp, r9w);
buffer.Emit<OpCode::MovZX, 8, false, 1, false>(rsp, r9, 4);
buffer.Emit<OpCode::MovZX, 8, false, 2, false>(rsp, r9, 4);
// Source: r9, target: rbp
buffer.EmitImmediate<OpCode::Mov>(bpl, static_cast<uint8_t>(1));
buffer.EmitImmediate<OpCode::Mov>(bp, static_cast<uint16_t>(1));
buffer.EmitImmediate<OpCode::Mov>(ebp, 1);
buffer.EmitImmediate<OpCode::Mov>(rbp, 1);
buffer.Emit<OpCode::Mov>(bpl, r9b);
buffer.Emit<OpCode::Mov>(bp, r9w);
buffer.Emit<OpCode::Mov>(ebp, r9d);
buffer.Emit<OpCode::Mov>(rbp, r9);
buffer.Emit<OpCode::Mov>(bpl, r9, -4);
buffer.Emit<OpCode::Mov>(bpl, r9, 4);
buffer.Emit<OpCode::Mov>(bp, r9, 4);
buffer.Emit<OpCode::Mov>(ebp, r9, 4);
buffer.Emit<OpCode::Mov>(rbp, r9, 4);
buffer.Emit<OpCode::Mov>(rbp, -4, r9b);
buffer.Emit<OpCode::Mov>(rbp, 4, r9b);
buffer.Emit<OpCode::Mov>(rbp, 4, r9w);
buffer.Emit<OpCode::Mov>(rbp, 4, r9d);
buffer.Emit<OpCode::Mov>(rbp, 4, r9);
buffer.Emit<OpCode::MovZX>(bp, r9b);
buffer.Emit<OpCode::MovZX, 2, false, 1, false>(bp, r9, 4);
buffer.Emit<OpCode::MovZX>(ebp, r9b);
buffer.Emit<OpCode::MovZX>(ebp, r9w);
buffer.Emit<OpCode::MovZX, 4, false, 1, false>(ebp, r9, 4);
buffer.Emit<OpCode::MovZX, 4, false, 2, false>(ebp, r9, 4);
buffer.Emit<OpCode::MovZX>(rbp, r9b);
buffer.Emit<OpCode::MovZX>(rbp, r9w);
buffer.Emit<OpCode::MovZX, 8, false, 1, false>(rbp, r9, 4);
buffer.Emit<OpCode::MovZX, 8, false, 2, false>(rbp, r9, 4);
// Source: r9, target: rsi
buffer.EmitImmediate<OpCode::Mov>(dil, static_cast<uint8_t>(1));
buffer.EmitImmediate<OpCode::Mov>(si, static_cast<uint16_t>(1));
buffer.EmitImmediate<OpCode::Mov>(esi, 1);
buffer.EmitImmediate<OpCode::Mov>(rsi, 1);
buffer.Emit<OpCode::Mov>(dil, r9b);
buffer.Emit<OpCode::Mov>(si, r9w);
buffer.Emit<OpCode::Mov>(esi, r9d);
buffer.Emit<OpCode::Mov>(rsi, r9);
buffer.Emit<OpCode::Mov>(dil, r9, -4);
buffer.Emit<OpCode::Mov>(dil, r9, 4);
buffer.Emit<OpCode::Mov>(si, r9, 4);
buffer.Emit<OpCode::Mov>(esi, r9, 4);
buffer.Emit<OpCode::Mov>(rsi, r9, 4);
buffer.Emit<OpCode::Mov>(rsi, -4, r9b);
buffer.Emit<OpCode::Mov>(rsi, 4, r9b);
buffer.Emit<OpCode::Mov>(rsi, 4, r9w);
buffer.Emit<OpCode::Mov>(rsi, 4, r9d);
buffer.Emit<OpCode::Mov>(rsi, 4, r9);
buffer.Emit<OpCode::MovZX>(si, r9b);
buffer.Emit<OpCode::MovZX, 2, false, 1, false>(si, r9, 4);
buffer.Emit<OpCode::MovZX>(esi, r9b);
buffer.Emit<OpCode::MovZX>(esi, r9w);
buffer.Emit<OpCode::MovZX, 4, false, 1, false>(esi, r9, 4);
buffer.Emit<OpCode::MovZX, 4, false, 2, false>(esi, r9, 4);
buffer.Emit<OpCode::MovZX>(rsi, r9b);
buffer.Emit<OpCode::MovZX>(rsi, r9w);
buffer.Emit<OpCode::MovZX, 8, false, 1, false>(rsi, r9, 4);
buffer.Emit<OpCode::MovZX, 8, false, 2, false>(rsi, r9, 4);
// Source: r9, target: rdi
buffer.EmitImmediate<OpCode::Mov>(sil, static_cast<uint8_t>(1));
buffer.EmitImmediate<OpCode::Mov>(di, static_cast<uint16_t>(1));
buffer.EmitImmediate<OpCode::Mov>(edi, 1);
buffer.EmitImmediate<OpCode::Mov>(rdi, 1);
buffer.Emit<OpCode::Mov>(sil, r9b);
buffer.Emit<OpCode::Mov>(di, r9w);
buffer.Emit<OpCode::Mov>(edi, r9d);
buffer.Emit<OpCode::Mov>(rdi, r9);
buffer.Emit<OpCode::Mov>(sil, r9, -4);
buffer.Emit<OpCode::Mov>(sil, r9, 4);
buffer.Emit<OpCode::Mov>(di, r9, 4);
buffer.Emit<OpCode::Mov>(edi, r9, 4);
buffer.Emit<OpCode::Mov>(rdi, r9, 4);
buffer.Emit<OpCode::Mov>(rdi, -4, r9b);
buffer.Emit<OpCode::Mov>(rdi, 4, r9b);
buffer.Emit<OpCode::Mov>(rdi, 4, r9w);
buffer.Emit<OpCode::Mov>(rdi, 4, r9d);
buffer.Emit<OpCode::Mov>(rdi, 4, r9);
buffer.Emit<OpCode::MovZX>(di, r9b);
buffer.Emit<OpCode::MovZX, 2, false, 1, false>(di, r9, 4);
buffer.Emit<OpCode::MovZX>(edi, r9b);
buffer.Emit<OpCode::MovZX>(edi, r9w);
buffer.Emit<OpCode::MovZX, 4, false, 1, false>(edi, r9, 4);
buffer.Emit<OpCode::MovZX, 4, false, 2, false>(edi, r9, 4);
buffer.Emit<OpCode::MovZX>(rdi, r9b);
buffer.Emit<OpCode::MovZX>(rdi, r9w);
buffer.Emit<OpCode::MovZX, 8, false, 1, false>(rdi, r9, 4);
buffer.Emit<OpCode::MovZX, 8, false, 2, false>(rdi, r9, 4);
// Source: r9, target: r8
buffer.EmitImmediate<OpCode::Mov>(r8b, static_cast<uint8_t>(1));
buffer.EmitImmediate<OpCode::Mov>(r8w, static_cast<uint16_t>(1));
buffer.EmitImmediate<OpCode::Mov>(r8d, 1);
buffer.EmitImmediate<OpCode::Mov>(r8, 1);
buffer.Emit<OpCode::Mov>(r8b, r9b);
buffer.Emit<OpCode::Mov>(r8w, r9w);
buffer.Emit<OpCode::Mov>(r8d, r9d);
buffer.Emit<OpCode::Mov>(r8, r9);
buffer.Emit<OpCode::Mov>(r8b, r9, -4);
buffer.Emit<OpCode::Mov>(r8b, r9, 4);
buffer.Emit<OpCode::Mov>(r8w, r9, 4);
buffer.Emit<OpCode::Mov>(r8d, r9, 4);
buffer.Emit<OpCode::Mov>(r8, r9, 4);
buffer.Emit<OpCode::Mov>(r8, -4, r9b);
buffer.Emit<OpCode::Mov>(r8, 4, r9b);
buffer.Emit<OpCode::Mov>(r8, 4, r9w);
buffer.Emit<OpCode::Mov>(r8, 4, r9d);
buffer.Emit<OpCode::Mov>(r8, 4, r9);
buffer.Emit<OpCode::MovZX>(r8w, r9b);
buffer.Emit<OpCode::MovZX, 2, false, 1, false>(r8w, r9, 4);
buffer.Emit<OpCode::MovZX>(r8d, r9b);
buffer.Emit<OpCode::MovZX>(r8d, r9w);
buffer.Emit<OpCode::MovZX, 4, false, 1, false>(r8d, r9, 4);
buffer.Emit<OpCode::MovZX, 4, false, 2, false>(r8d, r9, 4);
buffer.Emit<OpCode::MovZX>(r8, r9b);
buffer.Emit<OpCode::MovZX>(r8, r9w);
buffer.Emit<OpCode::MovZX, 8, false, 1, false>(r8, r9, 4);
buffer.Emit<OpCode::MovZX, 8, false, 2, false>(r8, r9, 4);
// Source: r9, target: r9
buffer.EmitImmediate<OpCode::Mov>(r9b, static_cast<uint8_t>(1));
buffer.EmitImmediate<OpCode::Mov>(r9w, static_cast<uint16_t>(1));
buffer.EmitImmediate<OpCode::Mov>(r9d, 1);
buffer.EmitImmediate<OpCode::Mov>(r9, 1);
buffer.Emit<OpCode::Mov>(r9b, r9b);
buffer.Emit<OpCode::Mov>(r9w, r9w);
buffer.Emit<OpCode::Mov>(r9d, r9d);
buffer.Emit<OpCode::Mov>(r9, r9);
buffer.Emit<OpCode::Mov>(r9b, r9, -4);
buffer.Emit<OpCode::Mov>(r9b, r9, 4);
buffer.Emit<OpCode::Mov>(r9w, r9, 4);
buffer.Emit<OpCode::Mov>(r9d, r9, 4);
buffer.Emit<OpCode::Mov>(r9, r9, 4);
buffer.Emit<OpCode::Mov>(r9, -4, r9b);
buffer.Emit<OpCode::Mov>(r9, 4, r9b);
buffer.Emit<OpCode::Mov>(r9, 4, r9w);
buffer.Emit<OpCode::Mov>(r9, 4, r9d);
buffer.Emit<OpCode::Mov>(r9, 4, r9);
buffer.Emit<OpCode::MovZX>(r9w, r9b);
buffer.Emit<OpCode::MovZX, 2, false, 1, false>(r9w, r9, 4);
buffer.Emit<OpCode::MovZX>(r9d, r9b);
buffer.Emit<OpCode::MovZX>(r9d, r9w);
buffer.Emit<OpCode::MovZX, 4, false, 1, false>(r9d, r9, 4);
buffer.Emit<OpCode::MovZX, 4, false, 2, false>(r9d, r9, 4);
buffer.Emit<OpCode::MovZX>(r9, r9b);
buffer.Emit<OpCode::MovZX>(r9, r9w);
buffer.Emit<OpCode::MovZX, 8, false, 1, false>(r9, r9, 4);
buffer.Emit<OpCode::MovZX, 8, false, 2, false>(r9, r9, 4);
// Source: r9, target: r10
buffer.EmitImmediate<OpCode::Mov>(r10b, static_cast<uint8_t>(1));
buffer.EmitImmediate<OpCode::Mov>(r10w, static_cast<uint16_t>(1));
buffer.EmitImmediate<OpCode::Mov>(r10d, 1);
buffer.EmitImmediate<OpCode::Mov>(r10, 1);
buffer.Emit<OpCode::Mov>(r10b, r9b);
buffer.Emit<OpCode::Mov>(r10w, r9w);
buffer.Emit<OpCode::Mov>(r10d, r9d);
buffer.Emit<OpCode::Mov>(r10, r9);
buffer.Emit<OpCode::Mov>(r10b, r9, -4);
buffer.Emit<OpCode::Mov>(r10b, r9, 4);
buffer.Emit<OpCode::Mov>(r10w, r9, 4);
buffer.Emit<OpCode::Mov>(r10d, r9, 4);
buffer.Emit<OpCode::Mov>(r10, r9, 4);
buffer.Emit<OpCode::Mov>(r10, -4, r9b);
buffer.Emit<OpCode::Mov>(r10, 4, r9b);
buffer.Emit<OpCode::Mov>(r10, 4, r9w);
buffer.Emit<OpCode::Mov>(r10, 4, r9d);
buffer.Emit<OpCode::Mov>(r10, 4, r9);
buffer.Emit<OpCode::MovZX>(r10w, r9b);
buffer.Emit<OpCode::MovZX, 2, false, 1, false>(r10w, r9, 4);
buffer.Emit<OpCode::MovZX>(r10d, r9b);
buffer.Emit<OpCode::MovZX>(r10d, r9w);
buffer.Emit<OpCode::MovZX, 4, false, 1, false>(r10d, r9, 4);
buffer.Emit<OpCode::MovZX, 4, false, 2, false>(r10d, r9, 4);
buffer.Emit<OpCode::MovZX>(r10, r9b);
buffer.Emit<OpCode::MovZX>(r10, r9w);
buffer.Emit<OpCode::MovZX, 8, false, 1, false>(r10, r9, 4);
buffer.Emit<OpCode::MovZX, 8, false, 2, false>(r10, r9, 4);
// Source: r9, target: r11
buffer.EmitImmediate<OpCode::Mov>(r11b, static_cast<uint8_t>(1));
buffer.EmitImmediate<OpCode::Mov>(r11w, static_cast<uint16_t>(1));
buffer.EmitImmediate<OpCode::Mov>(r11d, 1);
buffer.EmitImmediate<OpCode::Mov>(r11, 1);
buffer.Emit<OpCode::Mov>(r11b, r9b);
buffer.Emit<OpCode::Mov>(r11w, r9w);
buffer.Emit<OpCode::Mov>(r11d, r9d);
buffer.Emit<OpCode::Mov>(r11, r9);
buffer.Emit<OpCode::Mov>(r11b, r9, -4);
buffer.Emit<OpCode::Mov>(r11b, r9, 4);
buffer.Emit<OpCode::Mov>(r11w, r9, 4);
buffer.Emit<OpCode::Mov>(r11d, r9, 4);
buffer.Emit<OpCode::Mov>(r11, r9, 4);
buffer.Emit<OpCode::Mov>(r11, -4, r9b);
buffer.Emit<OpCode::Mov>(r11, 4, r9b);
buffer.Emit<OpCode::Mov>(r11, 4, r9w);
buffer.Emit<OpCode::Mov>(r11, 4, r9d);
buffer.Emit<OpCode::Mov>(r11, 4, r9);
buffer.Emit<OpCode::MovZX>(r11w, r9b);
buffer.Emit<OpCode::MovZX, 2, false, 1, false>(r11w, r9, 4);
buffer.Emit<OpCode::MovZX>(r11d, r9b);
buffer.Emit<OpCode::MovZX>(r11d, r9w);
buffer.Emit<OpCode::MovZX, 4, false, 1, false>(r11d, r9, 4);
buffer.Emit<OpCode::MovZX, 4, false, 2, false>(r11d, r9, 4);
buffer.Emit<OpCode::MovZX>(r11, r9b);
buffer.Emit<OpCode::MovZX>(r11, r9w);
buffer.Emit<OpCode::MovZX, 8, false, 1, false>(r11, r9, 4);
buffer.Emit<OpCode::MovZX, 8, false, 2, false>(r11, r9, 4);
// Source: r9, target: r12
buffer.EmitImmediate<OpCode::Mov>(r12b, static_cast<uint8_t>(1));
buffer.EmitImmediate<OpCode::Mov>(r12w, static_cast<uint16_t>(1));
buffer.EmitImmediate<OpCode::Mov>(r12d, 1);
buffer.EmitImmediate<OpCode::Mov>(r12, 1);
buffer.Emit<OpCode::Mov>(r12b, r9b);
buffer.Emit<OpCode::Mov>(r12w, r9w);
buffer.Emit<OpCode::Mov>(r12d, r9d);
buffer.Emit<OpCode::Mov>(r12, r9);
buffer.Emit<OpCode::Mov>(r12b, r9, -4);
buffer.Emit<OpCode::Mov>(r12b, r9, 4);
buffer.Emit<OpCode::Mov>(r12w, r9, 4);
buffer.Emit<OpCode::Mov>(r12d, r9, 4);
buffer.Emit<OpCode::Mov>(r12, r9, 4);
buffer.Emit<OpCode::Mov>(r12, -4, r9b);
buffer.Emit<OpCode::Mov>(r12, 4, r9b);
buffer.Emit<OpCode::Mov>(r12, 4, r9w);
buffer.Emit<OpCode::Mov>(r12, 4, r9d);
buffer.Emit<OpCode::Mov>(r12, 4, r9);
buffer.Emit<OpCode::MovZX>(r12w, r9b);
buffer.Emit<OpCode::MovZX, 2, false, 1, false>(r12w, r9, 4);
buffer.Emit<OpCode::MovZX>(r12d, r9b);
buffer.Emit<OpCode::MovZX>(r12d, r9w);
buffer.Emit<OpCode::MovZX, 4, false, 1, false>(r12d, r9, 4);
buffer.Emit<OpCode::MovZX, 4, false, 2, false>(r12d, r9, 4);
buffer.Emit<OpCode::MovZX>(r12, r9b);
buffer.Emit<OpCode::MovZX>(r12, r9w);
buffer.Emit<OpCode::MovZX, 8, false, 1, false>(r12, r9, 4);
buffer.Emit<OpCode::MovZX, 8, false, 2, false>(r12, r9, 4);
// Source: r9, target: r13
buffer.EmitImmediate<OpCode::Mov>(r13b, static_cast<uint8_t>(1));
buffer.EmitImmediate<OpCode::Mov>(r13w, static_cast<uint16_t>(1));
buffer.EmitImmediate<OpCode::Mov>(r13d, 1);
buffer.EmitImmediate<OpCode::Mov>(r13, 1);
buffer.Emit<OpCode::Mov>(r13b, r9b);
buffer.Emit<OpCode::Mov>(r13w, r9w);
buffer.Emit<OpCode::Mov>(r13d, r9d);
buffer.Emit<OpCode::Mov>(r13, r9);
buffer.Emit<OpCode::Mov>(r13b, r9, -4);
buffer.Emit<OpCode::Mov>(r13b, r9, 4);
buffer.Emit<OpCode::Mov>(r13w, r9, 4);
buffer.Emit<OpCode::Mov>(r13d, r9, 4);
buffer.Emit<OpCode::Mov>(r13, r9, 4);
buffer.Emit<OpCode::Mov>(r13, -4, r9b);
buffer.Emit<OpCode::Mov>(r13, 4, r9b);
buffer.Emit<OpCode::Mov>(r13, 4, r9w);
buffer.Emit<OpCode::Mov>(r13, 4, r9d);
buffer.Emit<OpCode::Mov>(r13, 4, r9);
buffer.Emit<OpCode::MovZX>(r13w, r9b);
buffer.Emit<OpCode::MovZX, 2, false, 1, false>(r13w, r9, 4);
buffer.Emit<OpCode::MovZX>(r13d, r9b);
buffer.Emit<OpCode::MovZX>(r13d, r9w);
buffer.Emit<OpCode::MovZX, 4, false, 1, false>(r13d, r9, 4);
buffer.Emit<OpCode::MovZX, 4, false, 2, false>(r13d, r9, 4);
buffer.Emit<OpCode::MovZX>(r13, r9b);
buffer.Emit<OpCode::MovZX>(r13, r9w);
buffer.Emit<OpCode::MovZX, 8, false, 1, false>(r13, r9, 4);
buffer.Emit<OpCode::MovZX, 8, false, 2, false>(r13, r9, 4);
// Source: r9, target: r14
buffer.EmitImmediate<OpCode::Mov>(r14b, static_cast<uint8_t>(1));
buffer.EmitImmediate<OpCode::Mov>(r14w, static_cast<uint16_t>(1));
buffer.EmitImmediate<OpCode::Mov>(r14d, 1);
buffer.EmitImmediate<OpCode::Mov>(r14, 1);
buffer.Emit<OpCode::Mov>(r14b, r9b);
buffer.Emit<OpCode::Mov>(r14w, r9w);
buffer.Emit<OpCode::Mov>(r14d, r9d);
buffer.Emit<OpCode::Mov>(r14, r9);
buffer.Emit<OpCode::Mov>(r14b, r9, -4);
buffer.Emit<OpCode::Mov>(r14b, r9, 4);
buffer.Emit<OpCode::Mov>(r14w, r9, 4);
buffer.Emit<OpCode::Mov>(r14d, r9, 4);
buffer.Emit<OpCode::Mov>(r14, r9, 4);
buffer.Emit<OpCode::Mov>(r14, -4, r9b);
buffer.Emit<OpCode::Mov>(r14, 4, r9b);
buffer.Emit<OpCode::Mov>(r14, 4, r9w);
buffer.Emit<OpCode::Mov>(r14, 4, r9d);
buffer.Emit<OpCode::Mov>(r14, 4, r9);
buffer.Emit<OpCode::MovZX>(r14w, r9b);
buffer.Emit<OpCode::MovZX, 2, false, 1, false>(r14w, r9, 4);
buffer.Emit<OpCode::MovZX>(r14d, r9b);
buffer.Emit<OpCode::MovZX>(r14d, r9w);
buffer.Emit<OpCode::MovZX, 4, false, 1, false>(r14d, r9, 4);
buffer.Emit<OpCode::MovZX, 4, false, 2, false>(r14d, r9, 4);
buffer.Emit<OpCode::MovZX>(r14, r9b);
buffer.Emit<OpCode::MovZX>(r14, r9w);
buffer.Emit<OpCode::MovZX, 8, false, 1, false>(r14, r9, 4);
buffer.Emit<OpCode::MovZX, 8, false, 2, false>(r14, r9, 4);
// Source: r9, target: r15
buffer.EmitImmediate<OpCode::Mov>(r15b, static_cast<uint8_t>(1));
buffer.EmitImmediate<OpCode::Mov>(r15w, static_cast<uint16_t>(1));
buffer.EmitImmediate<OpCode::Mov>(r15d, 1);
buffer.EmitImmediate<OpCode::Mov>(r15, 1);
buffer.Emit<OpCode::Mov>(r15b, r9b);
buffer.Emit<OpCode::Mov>(r15w, r9w);
buffer.Emit<OpCode::Mov>(r15d, r9d);
buffer.Emit<OpCode::Mov>(r15, r9);
buffer.Emit<OpCode::Mov>(r15b, r9, -4);
buffer.Emit<OpCode::Mov>(r15b, r9, 4);
buffer.Emit<OpCode::Mov>(r15w, r9, 4);
buffer.Emit<OpCode::Mov>(r15d, r9, 4);
buffer.Emit<OpCode::Mov>(r15, r9, 4);
buffer.Emit<OpCode::Mov>(r15, -4, r9b);
buffer.Emit<OpCode::Mov>(r15, 4, r9b);
buffer.Emit<OpCode::Mov>(r15, 4, r9w);
buffer.Emit<OpCode::Mov>(r15, 4, r9d);
buffer.Emit<OpCode::Mov>(r15, 4, r9);
buffer.Emit<OpCode::MovZX>(r15w, r9b);
buffer.Emit<OpCode::MovZX, 2, false, 1, false>(r15w, r9, 4);
buffer.Emit<OpCode::MovZX>(r15d, r9b);
buffer.Emit<OpCode::MovZX>(r15d, r9w);
buffer.Emit<OpCode::MovZX, 4, false, 1, false>(r15d, r9, 4);
buffer.Emit<OpCode::MovZX, 4, false, 2, false>(r15d, r9, 4);
buffer.Emit<OpCode::MovZX>(r15, r9b);
buffer.Emit<OpCode::MovZX>(r15, r9w);
buffer.Emit<OpCode::MovZX, 8, false, 1, false>(r15, r9, 4);
buffer.Emit<OpCode::MovZX, 8, false, 2, false>(r15, r9, 4);
// Source: r10, target: rax
buffer.EmitImmediate<OpCode::Mov>(al, static_cast<uint8_t>(1));
buffer.EmitImmediate<OpCode::Mov>(ax, static_cast<uint16_t>(1));
buffer.EmitImmediate<OpCode::Mov>(eax, 1);
buffer.EmitImmediate<OpCode::Mov>(rax, 1);
buffer.Emit<OpCode::Mov>(al, r10b);
buffer.Emit<OpCode::Mov>(ax, r10w);
buffer.Emit<OpCode::Mov>(eax, r10d);
buffer.Emit<OpCode::Mov>(rax, r10);
buffer.Emit<OpCode::Mov>(al, r10, -4);
buffer.Emit<OpCode::Mov>(al, r10, 4);
buffer.Emit<OpCode::Mov>(ax, r10, 4);
buffer.Emit<OpCode::Mov>(eax, r10, 4);
buffer.Emit<OpCode::Mov>(rax, r10, 4);
buffer.Emit<OpCode::Mov>(rax, -4, r10b);
buffer.Emit<OpCode::Mov>(rax, 4, r10b);
buffer.Emit<OpCode::Mov>(rax, 4, r10w);
buffer.Emit<OpCode::Mov>(rax, 4, r10d);
buffer.Emit<OpCode::Mov>(rax, 4, r10);
buffer.Emit<OpCode::MovZX>(ax, r10b);
buffer.Emit<OpCode::MovZX, 2, false, 1, false>(ax, r10, 4);
buffer.Emit<OpCode::MovZX>(eax, r10b);
buffer.Emit<OpCode::MovZX>(eax, r10w);
buffer.Emit<OpCode::MovZX, 4, false, 1, false>(eax, r10, 4);
buffer.Emit<OpCode::MovZX, 4, false, 2, false>(eax, r10, 4);
buffer.Emit<OpCode::MovZX>(rax, r10b);
buffer.Emit<OpCode::MovZX>(rax, r10w);
buffer.Emit<OpCode::MovZX, 8, false, 1, false>(rax, r10, 4);
buffer.Emit<OpCode::MovZX, 8, false, 2, false>(rax, r10, 4);
// Source: r10, target: rcx
buffer.EmitImmediate<OpCode::Mov>(cl, static_cast<uint8_t>(1));
buffer.EmitImmediate<OpCode::Mov>(cx, static_cast<uint16_t>(1));
buffer.EmitImmediate<OpCode::Mov>(ecx, 1);
buffer.EmitImmediate<OpCode::Mov>(rcx, 1);
buffer.Emit<OpCode::Mov>(cl, r10b);
buffer.Emit<OpCode::Mov>(cx, r10w);
buffer.Emit<OpCode::Mov>(ecx, r10d);
buffer.Emit<OpCode::Mov>(rcx, r10);
buffer.Emit<OpCode::Mov>(cl, r10, -4);
buffer.Emit<OpCode::Mov>(cl, r10, 4);
buffer.Emit<OpCode::Mov>(cx, r10, 4);
buffer.Emit<OpCode::Mov>(ecx, r10, 4);
buffer.Emit<OpCode::Mov>(rcx, r10, 4);
buffer.Emit<OpCode::Mov>(rcx, -4, r10b);
buffer.Emit<OpCode::Mov>(rcx, 4, r10b);
buffer.Emit<OpCode::Mov>(rcx, 4, r10w);
buffer.Emit<OpCode::Mov>(rcx, 4, r10d);
buffer.Emit<OpCode::Mov>(rcx, 4, r10);
buffer.Emit<OpCode::MovZX>(cx, r10b);
buffer.Emit<OpCode::MovZX, 2, false, 1, false>(cx, r10, 4);
buffer.Emit<OpCode::MovZX>(ecx, r10b);
buffer.Emit<OpCode::MovZX>(ecx, r10w);
buffer.Emit<OpCode::MovZX, 4, false, 1, false>(ecx, r10, 4);
buffer.Emit<OpCode::MovZX, 4, false, 2, false>(ecx, r10, 4);
buffer.Emit<OpCode::MovZX>(rcx, r10b);
buffer.Emit<OpCode::MovZX>(rcx, r10w);
buffer.Emit<OpCode::MovZX, 8, false, 1, false>(rcx, r10, 4);
buffer.Emit<OpCode::MovZX, 8, false, 2, false>(rcx, r10, 4);
// Source: r10, target: rdx
buffer.EmitImmediate<OpCode::Mov>(dl, static_cast<uint8_t>(1));
buffer.EmitImmediate<OpCode::Mov>(dx, static_cast<uint16_t>(1));
buffer.EmitImmediate<OpCode::Mov>(edx, 1);
buffer.EmitImmediate<OpCode::Mov>(rdx, 1);
buffer.Emit<OpCode::Mov>(dl, r10b);
buffer.Emit<OpCode::Mov>(dx, r10w);
buffer.Emit<OpCode::Mov>(edx, r10d);
buffer.Emit<OpCode::Mov>(rdx, r10);
buffer.Emit<OpCode::Mov>(dl, r10, -4);
buffer.Emit<OpCode::Mov>(dl, r10, 4);
buffer.Emit<OpCode::Mov>(dx, r10, 4);
buffer.Emit<OpCode::Mov>(edx, r10, 4);
buffer.Emit<OpCode::Mov>(rdx, r10, 4);
buffer.Emit<OpCode::Mov>(rdx, -4, r10b);
buffer.Emit<OpCode::Mov>(rdx, 4, r10b);
buffer.Emit<OpCode::Mov>(rdx, 4, r10w);
buffer.Emit<OpCode::Mov>(rdx, 4, r10d);
buffer.Emit<OpCode::Mov>(rdx, 4, r10);
buffer.Emit<OpCode::MovZX>(dx, r10b);
buffer.Emit<OpCode::MovZX, 2, false, 1, false>(dx, r10, 4);
buffer.Emit<OpCode::MovZX>(edx, r10b);
buffer.Emit<OpCode::MovZX>(edx, r10w);
buffer.Emit<OpCode::MovZX, 4, false, 1, false>(edx, r10, 4);
buffer.Emit<OpCode::MovZX, 4, false, 2, false>(edx, r10, 4);
buffer.Emit<OpCode::MovZX>(rdx, r10b);
buffer.Emit<OpCode::MovZX>(rdx, r10w);
buffer.Emit<OpCode::MovZX, 8, false, 1, false>(rdx, r10, 4);
buffer.Emit<OpCode::MovZX, 8, false, 2, false>(rdx, r10, 4);
// Source: r10, target: rbx
buffer.EmitImmediate<OpCode::Mov>(bl, static_cast<uint8_t>(1));
buffer.EmitImmediate<OpCode::Mov>(bx, static_cast<uint16_t>(1));
buffer.EmitImmediate<OpCode::Mov>(ebx, 1);
buffer.EmitImmediate<OpCode::Mov>(rbx, 1);
buffer.Emit<OpCode::Mov>(bl, r10b);
buffer.Emit<OpCode::Mov>(bx, r10w);
buffer.Emit<OpCode::Mov>(ebx, r10d);
buffer.Emit<OpCode::Mov>(rbx, r10);
buffer.Emit<OpCode::Mov>(bl, r10, -4);
buffer.Emit<OpCode::Mov>(bl, r10, 4);
buffer.Emit<OpCode::Mov>(bx, r10, 4);
buffer.Emit<OpCode::Mov>(ebx, r10, 4);
buffer.Emit<OpCode::Mov>(rbx, r10, 4);
buffer.Emit<OpCode::Mov>(rbx, -4, r10b);
buffer.Emit<OpCode::Mov>(rbx, 4, r10b);
buffer.Emit<OpCode::Mov>(rbx, 4, r10w);
buffer.Emit<OpCode::Mov>(rbx, 4, r10d);
buffer.Emit<OpCode::Mov>(rbx, 4, r10);
buffer.Emit<OpCode::MovZX>(bx, r10b);
buffer.Emit<OpCode::MovZX, 2, false, 1, false>(bx, r10, 4);
buffer.Emit<OpCode::MovZX>(ebx, r10b);
buffer.Emit<OpCode::MovZX>(ebx, r10w);
buffer.Emit<OpCode::MovZX, 4, false, 1, false>(ebx, r10, 4);
buffer.Emit<OpCode::MovZX, 4, false, 2, false>(ebx, r10, 4);
buffer.Emit<OpCode::MovZX>(rbx, r10b);
buffer.Emit<OpCode::MovZX>(rbx, r10w);
buffer.Emit<OpCode::MovZX, 8, false, 1, false>(rbx, r10, 4);
buffer.Emit<OpCode::MovZX, 8, false, 2, false>(rbx, r10, 4);
// Source: r10, target: rsp
buffer.EmitImmediate<OpCode::Mov>(spl, static_cast<uint8_t>(1));
buffer.EmitImmediate<OpCode::Mov>(sp, static_cast<uint16_t>(1));
buffer.EmitImmediate<OpCode::Mov>(esp, 1);
buffer.EmitImmediate<OpCode::Mov>(rsp, 1);
buffer.Emit<OpCode::Mov>(spl, r10b);
buffer.Emit<OpCode::Mov>(sp, r10w);
buffer.Emit<OpCode::Mov>(esp, r10d);
buffer.Emit<OpCode::Mov>(rsp, r10);
buffer.Emit<OpCode::Mov>(spl, r10, -4);
buffer.Emit<OpCode::Mov>(spl, r10, 4);
buffer.Emit<OpCode::Mov>(sp, r10, 4);
buffer.Emit<OpCode::Mov>(esp, r10, 4);
buffer.Emit<OpCode::Mov>(rsp, r10, 4);
buffer.Emit<OpCode::Mov>(rsp, -4, r10b);
buffer.Emit<OpCode::Mov>(rsp, 4, r10b);
buffer.Emit<OpCode::Mov>(rsp, 4, r10w);
buffer.Emit<OpCode::Mov>(rsp, 4, r10d);
buffer.Emit<OpCode::Mov>(rsp, 4, r10);
buffer.Emit<OpCode::MovZX>(sp, r10b);
buffer.Emit<OpCode::MovZX, 2, false, 1, false>(sp, r10, 4);
buffer.Emit<OpCode::MovZX>(esp, r10b);
buffer.Emit<OpCode::MovZX>(esp, r10w);
buffer.Emit<OpCode::MovZX, 4, false, 1, false>(esp, r10, 4);
buffer.Emit<OpCode::MovZX, 4, false, 2, false>(esp, r10, 4);
buffer.Emit<OpCode::MovZX>(rsp, r10b);
buffer.Emit<OpCode::MovZX>(rsp, r10w);
buffer.Emit<OpCode::MovZX, 8, false, 1, false>(rsp, r10, 4);
buffer.Emit<OpCode::MovZX, 8, false, 2, false>(rsp, r10, 4);
// Source: r10, target: rbp
buffer.EmitImmediate<OpCode::Mov>(bpl, static_cast<uint8_t>(1));
buffer.EmitImmediate<OpCode::Mov>(bp, static_cast<uint16_t>(1));
buffer.EmitImmediate<OpCode::Mov>(ebp, 1);
buffer.EmitImmediate<OpCode::Mov>(rbp, 1);
buffer.Emit<OpCode::Mov>(bpl, r10b);
buffer.Emit<OpCode::Mov>(bp, r10w);
buffer.Emit<OpCode::Mov>(ebp, r10d);
buffer.Emit<OpCode::Mov>(rbp, r10);
buffer.Emit<OpCode::Mov>(bpl, r10, -4);
buffer.Emit<OpCode::Mov>(bpl, r10, 4);
buffer.Emit<OpCode::Mov>(bp, r10, 4);
buffer.Emit<OpCode::Mov>(ebp, r10, 4);
buffer.Emit<OpCode::Mov>(rbp, r10, 4);
buffer.Emit<OpCode::Mov>(rbp, -4, r10b);
buffer.Emit<OpCode::Mov>(rbp, 4, r10b);
buffer.Emit<OpCode::Mov>(rbp, 4, r10w);
buffer.Emit<OpCode::Mov>(rbp, 4, r10d);
buffer.Emit<OpCode::Mov>(rbp, 4, r10);
buffer.Emit<OpCode::MovZX>(bp, r10b);
buffer.Emit<OpCode::MovZX, 2, false, 1, false>(bp, r10, 4);
buffer.Emit<OpCode::MovZX>(ebp, r10b);
buffer.Emit<OpCode::MovZX>(ebp, r10w);
buffer.Emit<OpCode::MovZX, 4, false, 1, false>(ebp, r10, 4);
buffer.Emit<OpCode::MovZX, 4, false, 2, false>(ebp, r10, 4);
buffer.Emit<OpCode::MovZX>(rbp, r10b);
buffer.Emit<OpCode::MovZX>(rbp, r10w);
buffer.Emit<OpCode::MovZX, 8, false, 1, false>(rbp, r10, 4);
buffer.Emit<OpCode::MovZX, 8, false, 2, false>(rbp, r10, 4);
// Source: r10, target: rsi
buffer.EmitImmediate<OpCode::Mov>(dil, static_cast<uint8_t>(1));
buffer.EmitImmediate<OpCode::Mov>(si, static_cast<uint16_t>(1));
buffer.EmitImmediate<OpCode::Mov>(esi, 1);
buffer.EmitImmediate<OpCode::Mov>(rsi, 1);
buffer.Emit<OpCode::Mov>(dil, r10b);
buffer.Emit<OpCode::Mov>(si, r10w);
buffer.Emit<OpCode::Mov>(esi, r10d);
buffer.Emit<OpCode::Mov>(rsi, r10);
buffer.Emit<OpCode::Mov>(dil, r10, -4);
buffer.Emit<OpCode::Mov>(dil, r10, 4);
buffer.Emit<OpCode::Mov>(si, r10, 4);
buffer.Emit<OpCode::Mov>(esi, r10, 4);
buffer.Emit<OpCode::Mov>(rsi, r10, 4);
buffer.Emit<OpCode::Mov>(rsi, -4, r10b);
buffer.Emit<OpCode::Mov>(rsi, 4, r10b);
buffer.Emit<OpCode::Mov>(rsi, 4, r10w);
buffer.Emit<OpCode::Mov>(rsi, 4, r10d);
buffer.Emit<OpCode::Mov>(rsi, 4, r10);
buffer.Emit<OpCode::MovZX>(si, r10b);
buffer.Emit<OpCode::MovZX, 2, false, 1, false>(si, r10, 4);
buffer.Emit<OpCode::MovZX>(esi, r10b);
buffer.Emit<OpCode::MovZX>(esi, r10w);
buffer.Emit<OpCode::MovZX, 4, false, 1, false>(esi, r10, 4);
buffer.Emit<OpCode::MovZX, 4, false, 2, false>(esi, r10, 4);
buffer.Emit<OpCode::MovZX>(rsi, r10b);
buffer.Emit<OpCode::MovZX>(rsi, r10w);
buffer.Emit<OpCode::MovZX, 8, false, 1, false>(rsi, r10, 4);
buffer.Emit<OpCode::MovZX, 8, false, 2, false>(rsi, r10, 4);
// Source: r10, target: rdi
buffer.EmitImmediate<OpCode::Mov>(sil, static_cast<uint8_t>(1));
buffer.EmitImmediate<OpCode::Mov>(di, static_cast<uint16_t>(1));
buffer.EmitImmediate<OpCode::Mov>(edi, 1);
buffer.EmitImmediate<OpCode::Mov>(rdi, 1);
buffer.Emit<OpCode::Mov>(sil, r10b);
buffer.Emit<OpCode::Mov>(di, r10w);
buffer.Emit<OpCode::Mov>(edi, r10d);
buffer.Emit<OpCode::Mov>(rdi, r10);
buffer.Emit<OpCode::Mov>(sil, r10, -4);
buffer.Emit<OpCode::Mov>(sil, r10, 4);
buffer.Emit<OpCode::Mov>(di, r10, 4);
buffer.Emit<OpCode::Mov>(edi, r10, 4);
buffer.Emit<OpCode::Mov>(rdi, r10, 4);
buffer.Emit<OpCode::Mov>(rdi, -4, r10b);
buffer.Emit<OpCode::Mov>(rdi, 4, r10b);
buffer.Emit<OpCode::Mov>(rdi, 4, r10w);
buffer.Emit<OpCode::Mov>(rdi, 4, r10d);
buffer.Emit<OpCode::Mov>(rdi, 4, r10);
buffer.Emit<OpCode::MovZX>(di, r10b);
buffer.Emit<OpCode::MovZX, 2, false, 1, false>(di, r10, 4);
buffer.Emit<OpCode::MovZX>(edi, r10b);
buffer.Emit<OpCode::MovZX>(edi, r10w);
buffer.Emit<OpCode::MovZX, 4, false, 1, false>(edi, r10, 4);
buffer.Emit<OpCode::MovZX, 4, false, 2, false>(edi, r10, 4);
buffer.Emit<OpCode::MovZX>(rdi, r10b);
buffer.Emit<OpCode::MovZX>(rdi, r10w);
buffer.Emit<OpCode::MovZX, 8, false, 1, false>(rdi, r10, 4);
buffer.Emit<OpCode::MovZX, 8, false, 2, false>(rdi, r10, 4);
// Source: r10, target: r8
buffer.EmitImmediate<OpCode::Mov>(r8b, static_cast<uint8_t>(1));
buffer.EmitImmediate<OpCode::Mov>(r8w, static_cast<uint16_t>(1));
buffer.EmitImmediate<OpCode::Mov>(r8d, 1);
buffer.EmitImmediate<OpCode::Mov>(r8, 1);
buffer.Emit<OpCode::Mov>(r8b, r10b);
buffer.Emit<OpCode::Mov>(r8w, r10w);
buffer.Emit<OpCode::Mov>(r8d, r10d);
buffer.Emit<OpCode::Mov>(r8, r10);
buffer.Emit<OpCode::Mov>(r8b, r10, -4);
buffer.Emit<OpCode::Mov>(r8b, r10, 4);
buffer.Emit<OpCode::Mov>(r8w, r10, 4);
buffer.Emit<OpCode::Mov>(r8d, r10, 4);
buffer.Emit<OpCode::Mov>(r8, r10, 4);
buffer.Emit<OpCode::Mov>(r8, -4, r10b);
buffer.Emit<OpCode::Mov>(r8, 4, r10b);
buffer.Emit<OpCode::Mov>(r8, 4, r10w);
buffer.Emit<OpCode::Mov>(r8, 4, r10d);
buffer.Emit<OpCode::Mov>(r8, 4, r10);
buffer.Emit<OpCode::MovZX>(r8w, r10b);
buffer.Emit<OpCode::MovZX, 2, false, 1, false>(r8w, r10, 4);
buffer.Emit<OpCode::MovZX>(r8d, r10b);
buffer.Emit<OpCode::MovZX>(r8d, r10w);
buffer.Emit<OpCode::MovZX, 4, false, 1, false>(r8d, r10, 4);
buffer.Emit<OpCode::MovZX, 4, false, 2, false>(r8d, r10, 4);
buffer.Emit<OpCode::MovZX>(r8, r10b);
buffer.Emit<OpCode::MovZX>(r8, r10w);
buffer.Emit<OpCode::MovZX, 8, false, 1, false>(r8, r10, 4);
buffer.Emit<OpCode::MovZX, 8, false, 2, false>(r8, r10, 4);
// Source: r10, target: r9
buffer.EmitImmediate<OpCode::Mov>(r9b, static_cast<uint8_t>(1));
buffer.EmitImmediate<OpCode::Mov>(r9w, static_cast<uint16_t>(1));
buffer.EmitImmediate<OpCode::Mov>(r9d, 1);
buffer.EmitImmediate<OpCode::Mov>(r9, 1);
buffer.Emit<OpCode::Mov>(r9b, r10b);
buffer.Emit<OpCode::Mov>(r9w, r10w);
buffer.Emit<OpCode::Mov>(r9d, r10d);
buffer.Emit<OpCode::Mov>(r9, r10);
buffer.Emit<OpCode::Mov>(r9b, r10, -4);
buffer.Emit<OpCode::Mov>(r9b, r10, 4);
buffer.Emit<OpCode::Mov>(r9w, r10, 4);
buffer.Emit<OpCode::Mov>(r9d, r10, 4);
buffer.Emit<OpCode::Mov>(r9, r10, 4);
buffer.Emit<OpCode::Mov>(r9, -4, r10b);
buffer.Emit<OpCode::Mov>(r9, 4, r10b);
buffer.Emit<OpCode::Mov>(r9, 4, r10w);
buffer.Emit<OpCode::Mov>(r9, 4, r10d);
buffer.Emit<OpCode::Mov>(r9, 4, r10);
buffer.Emit<OpCode::MovZX>(r9w, r10b);
buffer.Emit<OpCode::MovZX, 2, false, 1, false>(r9w, r10, 4);
buffer.Emit<OpCode::MovZX>(r9d, r10b);
buffer.Emit<OpCode::MovZX>(r9d, r10w);
buffer.Emit<OpCode::MovZX, 4, false, 1, false>(r9d, r10, 4);
buffer.Emit<OpCode::MovZX, 4, false, 2, false>(r9d, r10, 4);
buffer.Emit<OpCode::MovZX>(r9, r10b);
buffer.Emit<OpCode::MovZX>(r9, r10w);
buffer.Emit<OpCode::MovZX, 8, false, 1, false>(r9, r10, 4);
buffer.Emit<OpCode::MovZX, 8, false, 2, false>(r9, r10, 4);
// Source: r10, target: r10
buffer.EmitImmediate<OpCode::Mov>(r10b, static_cast<uint8_t>(1));
buffer.EmitImmediate<OpCode::Mov>(r10w, static_cast<uint16_t>(1));
buffer.EmitImmediate<OpCode::Mov>(r10d, 1);
buffer.EmitImmediate<OpCode::Mov>(r10, 1);
buffer.Emit<OpCode::Mov>(r10b, r10b);
buffer.Emit<OpCode::Mov>(r10w, r10w);
buffer.Emit<OpCode::Mov>(r10d, r10d);
buffer.Emit<OpCode::Mov>(r10, r10);
buffer.Emit<OpCode::Mov>(r10b, r10, -4);
buffer.Emit<OpCode::Mov>(r10b, r10, 4);
buffer.Emit<OpCode::Mov>(r10w, r10, 4);
buffer.Emit<OpCode::Mov>(r10d, r10, 4);
buffer.Emit<OpCode::Mov>(r10, r10, 4);
buffer.Emit<OpCode::Mov>(r10, -4, r10b);
buffer.Emit<OpCode::Mov>(r10, 4, r10b);
buffer.Emit<OpCode::Mov>(r10, 4, r10w);
buffer.Emit<OpCode::Mov>(r10, 4, r10d);
buffer.Emit<OpCode::Mov>(r10, 4, r10);
buffer.Emit<OpCode::MovZX>(r10w, r10b);
buffer.Emit<OpCode::MovZX, 2, false, 1, false>(r10w, r10, 4);
buffer.Emit<OpCode::MovZX>(r10d, r10b);
buffer.Emit<OpCode::MovZX>(r10d, r10w);
buffer.Emit<OpCode::MovZX, 4, false, 1, false>(r10d, r10, 4);
buffer.Emit<OpCode::MovZX, 4, false, 2, false>(r10d, r10, 4);
buffer.Emit<OpCode::MovZX>(r10, r10b);
buffer.Emit<OpCode::MovZX>(r10, r10w);
buffer.Emit<OpCode::MovZX, 8, false, 1, false>(r10, r10, 4);
buffer.Emit<OpCode::MovZX, 8, false, 2, false>(r10, r10, 4);
// Source: r10, target: r11
buffer.EmitImmediate<OpCode::Mov>(r11b, static_cast<uint8_t>(1));
buffer.EmitImmediate<OpCode::Mov>(r11w, static_cast<uint16_t>(1));
buffer.EmitImmediate<OpCode::Mov>(r11d, 1);
buffer.EmitImmediate<OpCode::Mov>(r11, 1);
buffer.Emit<OpCode::Mov>(r11b, r10b);
buffer.Emit<OpCode::Mov>(r11w, r10w);
buffer.Emit<OpCode::Mov>(r11d, r10d);
buffer.Emit<OpCode::Mov>(r11, r10);
buffer.Emit<OpCode::Mov>(r11b, r10, -4);
buffer.Emit<OpCode::Mov>(r11b, r10, 4);
buffer.Emit<OpCode::Mov>(r11w, r10, 4);
buffer.Emit<OpCode::Mov>(r11d, r10, 4);
buffer.Emit<OpCode::Mov>(r11, r10, 4);
buffer.Emit<OpCode::Mov>(r11, -4, r10b);
buffer.Emit<OpCode::Mov>(r11, 4, r10b);
buffer.Emit<OpCode::Mov>(r11, 4, r10w);
buffer.Emit<OpCode::Mov>(r11, 4, r10d);
buffer.Emit<OpCode::Mov>(r11, 4, r10);
buffer.Emit<OpCode::MovZX>(r11w, r10b);
buffer.Emit<OpCode::MovZX, 2, false, 1, false>(r11w, r10, 4);
buffer.Emit<OpCode::MovZX>(r11d, r10b);
buffer.Emit<OpCode::MovZX>(r11d, r10w);
buffer.Emit<OpCode::MovZX, 4, false, 1, false>(r11d, r10, 4);
buffer.Emit<OpCode::MovZX, 4, false, 2, false>(r11d, r10, 4);
buffer.Emit<OpCode::MovZX>(r11, r10b);
buffer.Emit<OpCode::MovZX>(r11, r10w);
buffer.Emit<OpCode::MovZX, 8, false, 1, false>(r11, r10, 4);
buffer.Emit<OpCode::MovZX, 8, false, 2, false>(r11, r10, 4);
// Source: r10, target: r12
buffer.EmitImmediate<OpCode::Mov>(r12b, static_cast<uint8_t>(1));
buffer.EmitImmediate<OpCode::Mov>(r12w, static_cast<uint16_t>(1));
buffer.EmitImmediate<OpCode::Mov>(r12d, 1);
buffer.EmitImmediate<OpCode::Mov>(r12, 1);
buffer.Emit<OpCode::Mov>(r12b, r10b);
buffer.Emit<OpCode::Mov>(r12w, r10w);
buffer.Emit<OpCode::Mov>(r12d, r10d);
buffer.Emit<OpCode::Mov>(r12, r10);
buffer.Emit<OpCode::Mov>(r12b, r10, -4);
buffer.Emit<OpCode::Mov>(r12b, r10, 4);
buffer.Emit<OpCode::Mov>(r12w, r10, 4);
buffer.Emit<OpCode::Mov>(r12d, r10, 4);
buffer.Emit<OpCode::Mov>(r12, r10, 4);
buffer.Emit<OpCode::Mov>(r12, -4, r10b);
buffer.Emit<OpCode::Mov>(r12, 4, r10b);
buffer.Emit<OpCode::Mov>(r12, 4, r10w);
buffer.Emit<OpCode::Mov>(r12, 4, r10d);
buffer.Emit<OpCode::Mov>(r12, 4, r10);
buffer.Emit<OpCode::MovZX>(r12w, r10b);
buffer.Emit<OpCode::MovZX, 2, false, 1, false>(r12w, r10, 4);
buffer.Emit<OpCode::MovZX>(r12d, r10b);
buffer.Emit<OpCode::MovZX>(r12d, r10w);
buffer.Emit<OpCode::MovZX, 4, false, 1, false>(r12d, r10, 4);
buffer.Emit<OpCode::MovZX, 4, false, 2, false>(r12d, r10, 4);
buffer.Emit<OpCode::MovZX>(r12, r10b);
buffer.Emit<OpCode::MovZX>(r12, r10w);
buffer.Emit<OpCode::MovZX, 8, false, 1, false>(r12, r10, 4);
buffer.Emit<OpCode::MovZX, 8, false, 2, false>(r12, r10, 4);
// Source: r10, target: r13
buffer.EmitImmediate<OpCode::Mov>(r13b, static_cast<uint8_t>(1));
buffer.EmitImmediate<OpCode::Mov>(r13w, static_cast<uint16_t>(1));
buffer.EmitImmediate<OpCode::Mov>(r13d, 1);
buffer.EmitImmediate<OpCode::Mov>(r13, 1);
buffer.Emit<OpCode::Mov>(r13b, r10b);
buffer.Emit<OpCode::Mov>(r13w, r10w);
buffer.Emit<OpCode::Mov>(r13d, r10d);
buffer.Emit<OpCode::Mov>(r13, r10);
buffer.Emit<OpCode::Mov>(r13b, r10, -4);
buffer.Emit<OpCode::Mov>(r13b, r10, 4);
buffer.Emit<OpCode::Mov>(r13w, r10, 4);
buffer.Emit<OpCode::Mov>(r13d, r10, 4);
buffer.Emit<OpCode::Mov>(r13, r10, 4);
buffer.Emit<OpCode::Mov>(r13, -4, r10b);
buffer.Emit<OpCode::Mov>(r13, 4, r10b);
buffer.Emit<OpCode::Mov>(r13, 4, r10w);
buffer.Emit<OpCode::Mov>(r13, 4, r10d);
buffer.Emit<OpCode::Mov>(r13, 4, r10);
buffer.Emit<OpCode::MovZX>(r13w, r10b);
buffer.Emit<OpCode::MovZX, 2, false, 1, false>(r13w, r10, 4);
buffer.Emit<OpCode::MovZX>(r13d, r10b);
buffer.Emit<OpCode::MovZX>(r13d, r10w);
buffer.Emit<OpCode::MovZX, 4, false, 1, false>(r13d, r10, 4);
buffer.Emit<OpCode::MovZX, 4, false, 2, false>(r13d, r10, 4);
buffer.Emit<OpCode::MovZX>(r13, r10b);
buffer.Emit<OpCode::MovZX>(r13, r10w);
buffer.Emit<OpCode::MovZX, 8, false, 1, false>(r13, r10, 4);
buffer.Emit<OpCode::MovZX, 8, false, 2, false>(r13, r10, 4);
// Source: r10, target: r14
buffer.EmitImmediate<OpCode::Mov>(r14b, static_cast<uint8_t>(1));
buffer.EmitImmediate<OpCode::Mov>(r14w, static_cast<uint16_t>(1));
buffer.EmitImmediate<OpCode::Mov>(r14d, 1);
buffer.EmitImmediate<OpCode::Mov>(r14, 1);
buffer.Emit<OpCode::Mov>(r14b, r10b);
buffer.Emit<OpCode::Mov>(r14w, r10w);
buffer.Emit<OpCode::Mov>(r14d, r10d);
buffer.Emit<OpCode::Mov>(r14, r10);
buffer.Emit<OpCode::Mov>(r14b, r10, -4);
buffer.Emit<OpCode::Mov>(r14b, r10, 4);
buffer.Emit<OpCode::Mov>(r14w, r10, 4);
buffer.Emit<OpCode::Mov>(r14d, r10, 4);
buffer.Emit<OpCode::Mov>(r14, r10, 4);
buffer.Emit<OpCode::Mov>(r14, -4, r10b);
buffer.Emit<OpCode::Mov>(r14, 4, r10b);
buffer.Emit<OpCode::Mov>(r14, 4, r10w);
buffer.Emit<OpCode::Mov>(r14, 4, r10d);
buffer.Emit<OpCode::Mov>(r14, 4, r10);
buffer.Emit<OpCode::MovZX>(r14w, r10b);
buffer.Emit<OpCode::MovZX, 2, false, 1, false>(r14w, r10, 4);
buffer.Emit<OpCode::MovZX>(r14d, r10b);
buffer.Emit<OpCode::MovZX>(r14d, r10w);
buffer.Emit<OpCode::MovZX, 4, false, 1, false>(r14d, r10, 4);
buffer.Emit<OpCode::MovZX, 4, false, 2, false>(r14d, r10, 4);
buffer.Emit<OpCode::MovZX>(r14, r10b);
buffer.Emit<OpCode::MovZX>(r14, r10w);
buffer.Emit<OpCode::MovZX, 8, false, 1, false>(r14, r10, 4);
buffer.Emit<OpCode::MovZX, 8, false, 2, false>(r14, r10, 4);
// Source: r10, target: r15
buffer.EmitImmediate<OpCode::Mov>(r15b, static_cast<uint8_t>(1));
buffer.EmitImmediate<OpCode::Mov>(r15w, static_cast<uint16_t>(1));
buffer.EmitImmediate<OpCode::Mov>(r15d, 1);
buffer.EmitImmediate<OpCode::Mov>(r15, 1);
buffer.Emit<OpCode::Mov>(r15b, r10b);
buffer.Emit<OpCode::Mov>(r15w, r10w);
buffer.Emit<OpCode::Mov>(r15d, r10d);
buffer.Emit<OpCode::Mov>(r15, r10);
buffer.Emit<OpCode::Mov>(r15b, r10, -4);
buffer.Emit<OpCode::Mov>(r15b, r10, 4);
buffer.Emit<OpCode::Mov>(r15w, r10, 4);
buffer.Emit<OpCode::Mov>(r15d, r10, 4);
buffer.Emit<OpCode::Mov>(r15, r10, 4);
buffer.Emit<OpCode::Mov>(r15, -4, r10b);
buffer.Emit<OpCode::Mov>(r15, 4, r10b);
buffer.Emit<OpCode::Mov>(r15, 4, r10w);
buffer.Emit<OpCode::Mov>(r15, 4, r10d);
buffer.Emit<OpCode::Mov>(r15, 4, r10);
buffer.Emit<OpCode::MovZX>(r15w, r10b);
buffer.Emit<OpCode::MovZX, 2, false, 1, false>(r15w, r10, 4);
buffer.Emit<OpCode::MovZX>(r15d, r10b);
buffer.Emit<OpCode::MovZX>(r15d, r10w);
buffer.Emit<OpCode::MovZX, 4, false, 1, false>(r15d, r10, 4);
buffer.Emit<OpCode::MovZX, 4, false, 2, false>(r15d, r10, 4);
buffer.Emit<OpCode::MovZX>(r15, r10b);
buffer.Emit<OpCode::MovZX>(r15, r10w);
buffer.Emit<OpCode::MovZX, 8, false, 1, false>(r15, r10, 4);
buffer.Emit<OpCode::MovZX, 8, false, 2, false>(r15, r10, 4);
// Source: r11, target: rax
buffer.EmitImmediate<OpCode::Mov>(al, static_cast<uint8_t>(1));
buffer.EmitImmediate<OpCode::Mov>(ax, static_cast<uint16_t>(1));
buffer.EmitImmediate<OpCode::Mov>(eax, 1);
buffer.EmitImmediate<OpCode::Mov>(rax, 1);
buffer.Emit<OpCode::Mov>(al, r11b);
buffer.Emit<OpCode::Mov>(ax, r11w);
buffer.Emit<OpCode::Mov>(eax, r11d);
buffer.Emit<OpCode::Mov>(rax, r11);
buffer.Emit<OpCode::Mov>(al, r11, -4);
buffer.Emit<OpCode::Mov>(al, r11, 4);
buffer.Emit<OpCode::Mov>(ax, r11, 4);
buffer.Emit<OpCode::Mov>(eax, r11, 4);
buffer.Emit<OpCode::Mov>(rax, r11, 4);
buffer.Emit<OpCode::Mov>(rax, -4, r11b);
buffer.Emit<OpCode::Mov>(rax, 4, r11b);
buffer.Emit<OpCode::Mov>(rax, 4, r11w);
buffer.Emit<OpCode::Mov>(rax, 4, r11d);
buffer.Emit<OpCode::Mov>(rax, 4, r11);
buffer.Emit<OpCode::MovZX>(ax, r11b);
buffer.Emit<OpCode::MovZX, 2, false, 1, false>(ax, r11, 4);
buffer.Emit<OpCode::MovZX>(eax, r11b);
buffer.Emit<OpCode::MovZX>(eax, r11w);
buffer.Emit<OpCode::MovZX, 4, false, 1, false>(eax, r11, 4);
buffer.Emit<OpCode::MovZX, 4, false, 2, false>(eax, r11, 4);
buffer.Emit<OpCode::MovZX>(rax, r11b);
buffer.Emit<OpCode::MovZX>(rax, r11w);
buffer.Emit<OpCode::MovZX, 8, false, 1, false>(rax, r11, 4);
buffer.Emit<OpCode::MovZX, 8, false, 2, false>(rax, r11, 4);
// Source: r11, target: rcx
buffer.EmitImmediate<OpCode::Mov>(cl, static_cast<uint8_t>(1));
buffer.EmitImmediate<OpCode::Mov>(cx, static_cast<uint16_t>(1));
buffer.EmitImmediate<OpCode::Mov>(ecx, 1);
buffer.EmitImmediate<OpCode::Mov>(rcx, 1);
buffer.Emit<OpCode::Mov>(cl, r11b);
buffer.Emit<OpCode::Mov>(cx, r11w);
buffer.Emit<OpCode::Mov>(ecx, r11d);
buffer.Emit<OpCode::Mov>(rcx, r11);
buffer.Emit<OpCode::Mov>(cl, r11, -4);
buffer.Emit<OpCode::Mov>(cl, r11, 4);
buffer.Emit<OpCode::Mov>(cx, r11, 4);
buffer.Emit<OpCode::Mov>(ecx, r11, 4);
buffer.Emit<OpCode::Mov>(rcx, r11, 4);
buffer.Emit<OpCode::Mov>(rcx, -4, r11b);
buffer.Emit<OpCode::Mov>(rcx, 4, r11b);
buffer.Emit<OpCode::Mov>(rcx, 4, r11w);
buffer.Emit<OpCode::Mov>(rcx, 4, r11d);
buffer.Emit<OpCode::Mov>(rcx, 4, r11);
buffer.Emit<OpCode::MovZX>(cx, r11b);
buffer.Emit<OpCode::MovZX, 2, false, 1, false>(cx, r11, 4);
buffer.Emit<OpCode::MovZX>(ecx, r11b);
buffer.Emit<OpCode::MovZX>(ecx, r11w);
buffer.Emit<OpCode::MovZX, 4, false, 1, false>(ecx, r11, 4);
buffer.Emit<OpCode::MovZX, 4, false, 2, false>(ecx, r11, 4);
buffer.Emit<OpCode::MovZX>(rcx, r11b);
buffer.Emit<OpCode::MovZX>(rcx, r11w);
buffer.Emit<OpCode::MovZX, 8, false, 1, false>(rcx, r11, 4);
buffer.Emit<OpCode::MovZX, 8, false, 2, false>(rcx, r11, 4);
// Source: r11, target: rdx
buffer.EmitImmediate<OpCode::Mov>(dl, static_cast<uint8_t>(1));
buffer.EmitImmediate<OpCode::Mov>(dx, static_cast<uint16_t>(1));
buffer.EmitImmediate<OpCode::Mov>(edx, 1);
buffer.EmitImmediate<OpCode::Mov>(rdx, 1);
buffer.Emit<OpCode::Mov>(dl, r11b);
buffer.Emit<OpCode::Mov>(dx, r11w);
buffer.Emit<OpCode::Mov>(edx, r11d);
buffer.Emit<OpCode::Mov>(rdx, r11);
buffer.Emit<OpCode::Mov>(dl, r11, -4);
buffer.Emit<OpCode::Mov>(dl, r11, 4);
buffer.Emit<OpCode::Mov>(dx, r11, 4);
buffer.Emit<OpCode::Mov>(edx, r11, 4);
buffer.Emit<OpCode::Mov>(rdx, r11, 4);
buffer.Emit<OpCode::Mov>(rdx, -4, r11b);
buffer.Emit<OpCode::Mov>(rdx, 4, r11b);
buffer.Emit<OpCode::Mov>(rdx, 4, r11w);
buffer.Emit<OpCode::Mov>(rdx, 4, r11d);
buffer.Emit<OpCode::Mov>(rdx, 4, r11);
buffer.Emit<OpCode::MovZX>(dx, r11b);
buffer.Emit<OpCode::MovZX, 2, false, 1, false>(dx, r11, 4);
buffer.Emit<OpCode::MovZX>(edx, r11b);
buffer.Emit<OpCode::MovZX>(edx, r11w);
buffer.Emit<OpCode::MovZX, 4, false, 1, false>(edx, r11, 4);
buffer.Emit<OpCode::MovZX, 4, false, 2, false>(edx, r11, 4);
buffer.Emit<OpCode::MovZX>(rdx, r11b);
buffer.Emit<OpCode::MovZX>(rdx, r11w);
buffer.Emit<OpCode::MovZX, 8, false, 1, false>(rdx, r11, 4);
buffer.Emit<OpCode::MovZX, 8, false, 2, false>(rdx, r11, 4);
// Source: r11, target: rbx
buffer.EmitImmediate<OpCode::Mov>(bl, static_cast<uint8_t>(1));
buffer.EmitImmediate<OpCode::Mov>(bx, static_cast<uint16_t>(1));
buffer.EmitImmediate<OpCode::Mov>(ebx, 1);
buffer.EmitImmediate<OpCode::Mov>(rbx, 1);
buffer.Emit<OpCode::Mov>(bl, r11b);
buffer.Emit<OpCode::Mov>(bx, r11w);
buffer.Emit<OpCode::Mov>(ebx, r11d);
buffer.Emit<OpCode::Mov>(rbx, r11);
buffer.Emit<OpCode::Mov>(bl, r11, -4);
buffer.Emit<OpCode::Mov>(bl, r11, 4);
buffer.Emit<OpCode::Mov>(bx, r11, 4);
buffer.Emit<OpCode::Mov>(ebx, r11, 4);
buffer.Emit<OpCode::Mov>(rbx, r11, 4);
buffer.Emit<OpCode::Mov>(rbx, -4, r11b);
buffer.Emit<OpCode::Mov>(rbx, 4, r11b);
buffer.Emit<OpCode::Mov>(rbx, 4, r11w);
buffer.Emit<OpCode::Mov>(rbx, 4, r11d);
buffer.Emit<OpCode::Mov>(rbx, 4, r11);
buffer.Emit<OpCode::MovZX>(bx, r11b);
buffer.Emit<OpCode::MovZX, 2, false, 1, false>(bx, r11, 4);
buffer.Emit<OpCode::MovZX>(ebx, r11b);
buffer.Emit<OpCode::MovZX>(ebx, r11w);
buffer.Emit<OpCode::MovZX, 4, false, 1, false>(ebx, r11, 4);
buffer.Emit<OpCode::MovZX, 4, false, 2, false>(ebx, r11, 4);
buffer.Emit<OpCode::MovZX>(rbx, r11b);
buffer.Emit<OpCode::MovZX>(rbx, r11w);
buffer.Emit<OpCode::MovZX, 8, false, 1, false>(rbx, r11, 4);
buffer.Emit<OpCode::MovZX, 8, false, 2, false>(rbx, r11, 4);
// Source: r11, target: rsp
buffer.EmitImmediate<OpCode::Mov>(spl, static_cast<uint8_t>(1));
buffer.EmitImmediate<OpCode::Mov>(sp, static_cast<uint16_t>(1));
buffer.EmitImmediate<OpCode::Mov>(esp, 1);
buffer.EmitImmediate<OpCode::Mov>(rsp, 1);
buffer.Emit<OpCode::Mov>(spl, r11b);
buffer.Emit<OpCode::Mov>(sp, r11w);
buffer.Emit<OpCode::Mov>(esp, r11d);
buffer.Emit<OpCode::Mov>(rsp, r11);
buffer.Emit<OpCode::Mov>(spl, r11, -4);
buffer.Emit<OpCode::Mov>(spl, r11, 4);
buffer.Emit<OpCode::Mov>(sp, r11, 4);
buffer.Emit<OpCode::Mov>(esp, r11, 4);
buffer.Emit<OpCode::Mov>(rsp, r11, 4);
buffer.Emit<OpCode::Mov>(rsp, -4, r11b);
buffer.Emit<OpCode::Mov>(rsp, 4, r11b);
buffer.Emit<OpCode::Mov>(rsp, 4, r11w);
buffer.Emit<OpCode::Mov>(rsp, 4, r11d);
buffer.Emit<OpCode::Mov>(rsp, 4, r11);
buffer.Emit<OpCode::MovZX>(sp, r11b);
buffer.Emit<OpCode::MovZX, 2, false, 1, false>(sp, r11, 4);
buffer.Emit<OpCode::MovZX>(esp, r11b);
buffer.Emit<OpCode::MovZX>(esp, r11w);
buffer.Emit<OpCode::MovZX, 4, false, 1, false>(esp, r11, 4);
buffer.Emit<OpCode::MovZX, 4, false, 2, false>(esp, r11, 4);
buffer.Emit<OpCode::MovZX>(rsp, r11b);
buffer.Emit<OpCode::MovZX>(rsp, r11w);
buffer.Emit<OpCode::MovZX, 8, false, 1, false>(rsp, r11, 4);
buffer.Emit<OpCode::MovZX, 8, false, 2, false>(rsp, r11, 4);
// Source: r11, target: rbp
buffer.EmitImmediate<OpCode::Mov>(bpl, static_cast<uint8_t>(1));
buffer.EmitImmediate<OpCode::Mov>(bp, static_cast<uint16_t>(1));
buffer.EmitImmediate<OpCode::Mov>(ebp, 1);
buffer.EmitImmediate<OpCode::Mov>(rbp, 1);
buffer.Emit<OpCode::Mov>(bpl, r11b);
buffer.Emit<OpCode::Mov>(bp, r11w);
buffer.Emit<OpCode::Mov>(ebp, r11d);
buffer.Emit<OpCode::Mov>(rbp, r11);
buffer.Emit<OpCode::Mov>(bpl, r11, -4);
buffer.Emit<OpCode::Mov>(bpl, r11, 4);
buffer.Emit<OpCode::Mov>(bp, r11, 4);
buffer.Emit<OpCode::Mov>(ebp, r11, 4);
buffer.Emit<OpCode::Mov>(rbp, r11, 4);
buffer.Emit<OpCode::Mov>(rbp, -4, r11b);
buffer.Emit<OpCode::Mov>(rbp, 4, r11b);
buffer.Emit<OpCode::Mov>(rbp, 4, r11w);
buffer.Emit<OpCode::Mov>(rbp, 4, r11d);
buffer.Emit<OpCode::Mov>(rbp, 4, r11);
buffer.Emit<OpCode::MovZX>(bp, r11b);
buffer.Emit<OpCode::MovZX, 2, false, 1, false>(bp, r11, 4);
buffer.Emit<OpCode::MovZX>(ebp, r11b);
buffer.Emit<OpCode::MovZX>(ebp, r11w);
buffer.Emit<OpCode::MovZX, 4, false, 1, false>(ebp, r11, 4);
buffer.Emit<OpCode::MovZX, 4, false, 2, false>(ebp, r11, 4);
buffer.Emit<OpCode::MovZX>(rbp, r11b);
buffer.Emit<OpCode::MovZX>(rbp, r11w);
buffer.Emit<OpCode::MovZX, 8, false, 1, false>(rbp, r11, 4);
buffer.Emit<OpCode::MovZX, 8, false, 2, false>(rbp, r11, 4);
// Source: r11, target: rsi
buffer.EmitImmediate<OpCode::Mov>(dil, static_cast<uint8_t>(1));
buffer.EmitImmediate<OpCode::Mov>(si, static_cast<uint16_t>(1));
buffer.EmitImmediate<OpCode::Mov>(esi, 1);
buffer.EmitImmediate<OpCode::Mov>(rsi, 1);
buffer.Emit<OpCode::Mov>(dil, r11b);
buffer.Emit<OpCode::Mov>(si, r11w);
buffer.Emit<OpCode::Mov>(esi, r11d);
buffer.Emit<OpCode::Mov>(rsi, r11);
buffer.Emit<OpCode::Mov>(dil, r11, -4);
buffer.Emit<OpCode::Mov>(dil, r11, 4);
buffer.Emit<OpCode::Mov>(si, r11, 4);
buffer.Emit<OpCode::Mov>(esi, r11, 4);
buffer.Emit<OpCode::Mov>(rsi, r11, 4);
buffer.Emit<OpCode::Mov>(rsi, -4, r11b);
buffer.Emit<OpCode::Mov>(rsi, 4, r11b);
buffer.Emit<OpCode::Mov>(rsi, 4, r11w);
buffer.Emit<OpCode::Mov>(rsi, 4, r11d);
buffer.Emit<OpCode::Mov>(rsi, 4, r11);
buffer.Emit<OpCode::MovZX>(si, r11b);
buffer.Emit<OpCode::MovZX, 2, false, 1, false>(si, r11, 4);
buffer.Emit<OpCode::MovZX>(esi, r11b);
buffer.Emit<OpCode::MovZX>(esi, r11w);
buffer.Emit<OpCode::MovZX, 4, false, 1, false>(esi, r11, 4);
buffer.Emit<OpCode::MovZX, 4, false, 2, false>(esi, r11, 4);
buffer.Emit<OpCode::MovZX>(rsi, r11b);
buffer.Emit<OpCode::MovZX>(rsi, r11w);
buffer.Emit<OpCode::MovZX, 8, false, 1, false>(rsi, r11, 4);
buffer.Emit<OpCode::MovZX, 8, false, 2, false>(rsi, r11, 4);
// Source: r11, target: rdi
buffer.EmitImmediate<OpCode::Mov>(sil, static_cast<uint8_t>(1));
buffer.EmitImmediate<OpCode::Mov>(di, static_cast<uint16_t>(1));
buffer.EmitImmediate<OpCode::Mov>(edi, 1);
buffer.EmitImmediate<OpCode::Mov>(rdi, 1);
buffer.Emit<OpCode::Mov>(sil, r11b);
buffer.Emit<OpCode::Mov>(di, r11w);
buffer.Emit<OpCode::Mov>(edi, r11d);
buffer.Emit<OpCode::Mov>(rdi, r11);
buffer.Emit<OpCode::Mov>(sil, r11, -4);
buffer.Emit<OpCode::Mov>(sil, r11, 4);
buffer.Emit<OpCode::Mov>(di, r11, 4);
buffer.Emit<OpCode::Mov>(edi, r11, 4);
buffer.Emit<OpCode::Mov>(rdi, r11, 4);
buffer.Emit<OpCode::Mov>(rdi, -4, r11b);
buffer.Emit<OpCode::Mov>(rdi, 4, r11b);
buffer.Emit<OpCode::Mov>(rdi, 4, r11w);
buffer.Emit<OpCode::Mov>(rdi, 4, r11d);
buffer.Emit<OpCode::Mov>(rdi, 4, r11);
buffer.Emit<OpCode::MovZX>(di, r11b);
buffer.Emit<OpCode::MovZX, 2, false, 1, false>(di, r11, 4);
buffer.Emit<OpCode::MovZX>(edi, r11b);
buffer.Emit<OpCode::MovZX>(edi, r11w);
buffer.Emit<OpCode::MovZX, 4, false, 1, false>(edi, r11, 4);
buffer.Emit<OpCode::MovZX, 4, false, 2, false>(edi, r11, 4);
buffer.Emit<OpCode::MovZX>(rdi, r11b);
buffer.Emit<OpCode::MovZX>(rdi, r11w);
buffer.Emit<OpCode::MovZX, 8, false, 1, false>(rdi, r11, 4);
buffer.Emit<OpCode::MovZX, 8, false, 2, false>(rdi, r11, 4);
// Source: r11, target: r8
buffer.EmitImmediate<OpCode::Mov>(r8b, static_cast<uint8_t>(1));
buffer.EmitImmediate<OpCode::Mov>(r8w, static_cast<uint16_t>(1));
buffer.EmitImmediate<OpCode::Mov>(r8d, 1);
buffer.EmitImmediate<OpCode::Mov>(r8, 1);
buffer.Emit<OpCode::Mov>(r8b, r11b);
buffer.Emit<OpCode::Mov>(r8w, r11w);
buffer.Emit<OpCode::Mov>(r8d, r11d);
buffer.Emit<OpCode::Mov>(r8, r11);
buffer.Emit<OpCode::Mov>(r8b, r11, -4);
buffer.Emit<OpCode::Mov>(r8b, r11, 4);
buffer.Emit<OpCode::Mov>(r8w, r11, 4);
buffer.Emit<OpCode::Mov>(r8d, r11, 4);
buffer.Emit<OpCode::Mov>(r8, r11, 4);
buffer.Emit<OpCode::Mov>(r8, -4, r11b);
buffer.Emit<OpCode::Mov>(r8, 4, r11b);
buffer.Emit<OpCode::Mov>(r8, 4, r11w);
buffer.Emit<OpCode::Mov>(r8, 4, r11d);
buffer.Emit<OpCode::Mov>(r8, 4, r11);
buffer.Emit<OpCode::MovZX>(r8w, r11b);
buffer.Emit<OpCode::MovZX, 2, false, 1, false>(r8w, r11, 4);
buffer.Emit<OpCode::MovZX>(r8d, r11b);
buffer.Emit<OpCode::MovZX>(r8d, r11w);
buffer.Emit<OpCode::MovZX, 4, false, 1, false>(r8d, r11, 4);
buffer.Emit<OpCode::MovZX, 4, false, 2, false>(r8d, r11, 4);
buffer.Emit<OpCode::MovZX>(r8, r11b);
buffer.Emit<OpCode::MovZX>(r8, r11w);
buffer.Emit<OpCode::MovZX, 8, false, 1, false>(r8, r11, 4);
buffer.Emit<OpCode::MovZX, 8, false, 2, false>(r8, r11, 4);
// Source: r11, target: r9
buffer.EmitImmediate<OpCode::Mov>(r9b, static_cast<uint8_t>(1));
buffer.EmitImmediate<OpCode::Mov>(r9w, static_cast<uint16_t>(1));
buffer.EmitImmediate<OpCode::Mov>(r9d, 1);
buffer.EmitImmediate<OpCode::Mov>(r9, 1);
buffer.Emit<OpCode::Mov>(r9b, r11b);
buffer.Emit<OpCode::Mov>(r9w, r11w);
buffer.Emit<OpCode::Mov>(r9d, r11d);
buffer.Emit<OpCode::Mov>(r9, r11);
buffer.Emit<OpCode::Mov>(r9b, r11, -4);
buffer.Emit<OpCode::Mov>(r9b, r11, 4);
buffer.Emit<OpCode::Mov>(r9w, r11, 4);
buffer.Emit<OpCode::Mov>(r9d, r11, 4);
buffer.Emit<OpCode::Mov>(r9, r11, 4);
buffer.Emit<OpCode::Mov>(r9, -4, r11b);
buffer.Emit<OpCode::Mov>(r9, 4, r11b);
buffer.Emit<OpCode::Mov>(r9, 4, r11w);
buffer.Emit<OpCode::Mov>(r9, 4, r11d);
buffer.Emit<OpCode::Mov>(r9, 4, r11);
buffer.Emit<OpCode::MovZX>(r9w, r11b);
buffer.Emit<OpCode::MovZX, 2, false, 1, false>(r9w, r11, 4);
buffer.Emit<OpCode::MovZX>(r9d, r11b);
buffer.Emit<OpCode::MovZX>(r9d, r11w);
buffer.Emit<OpCode::MovZX, 4, false, 1, false>(r9d, r11, 4);
buffer.Emit<OpCode::MovZX, 4, false, 2, false>(r9d, r11, 4);
buffer.Emit<OpCode::MovZX>(r9, r11b);
buffer.Emit<OpCode::MovZX>(r9, r11w);
buffer.Emit<OpCode::MovZX, 8, false, 1, false>(r9, r11, 4);
buffer.Emit<OpCode::MovZX, 8, false, 2, false>(r9, r11, 4);
// Source: r11, target: r10
buffer.EmitImmediate<OpCode::Mov>(r10b, static_cast<uint8_t>(1));
buffer.EmitImmediate<OpCode::Mov>(r10w, static_cast<uint16_t>(1));
buffer.EmitImmediate<OpCode::Mov>(r10d, 1);
buffer.EmitImmediate<OpCode::Mov>(r10, 1);
buffer.Emit<OpCode::Mov>(r10b, r11b);
buffer.Emit<OpCode::Mov>(r10w, r11w);
buffer.Emit<OpCode::Mov>(r10d, r11d);
buffer.Emit<OpCode::Mov>(r10, r11);
buffer.Emit<OpCode::Mov>(r10b, r11, -4);
buffer.Emit<OpCode::Mov>(r10b, r11, 4);
buffer.Emit<OpCode::Mov>(r10w, r11, 4);
buffer.Emit<OpCode::Mov>(r10d, r11, 4);
buffer.Emit<OpCode::Mov>(r10, r11, 4);
buffer.Emit<OpCode::Mov>(r10, -4, r11b);
buffer.Emit<OpCode::Mov>(r10, 4, r11b);
buffer.Emit<OpCode::Mov>(r10, 4, r11w);
buffer.Emit<OpCode::Mov>(r10, 4, r11d);
buffer.Emit<OpCode::Mov>(r10, 4, r11);
buffer.Emit<OpCode::MovZX>(r10w, r11b);
buffer.Emit<OpCode::MovZX, 2, false, 1, false>(r10w, r11, 4);
buffer.Emit<OpCode::MovZX>(r10d, r11b);
buffer.Emit<OpCode::MovZX>(r10d, r11w);
buffer.Emit<OpCode::MovZX, 4, false, 1, false>(r10d, r11, 4);
buffer.Emit<OpCode::MovZX, 4, false, 2, false>(r10d, r11, 4);
buffer.Emit<OpCode::MovZX>(r10, r11b);
buffer.Emit<OpCode::MovZX>(r10, r11w);
buffer.Emit<OpCode::MovZX, 8, false, 1, false>(r10, r11, 4);
buffer.Emit<OpCode::MovZX, 8, false, 2, false>(r10, r11, 4);
// Source: r11, target: r11
buffer.EmitImmediate<OpCode::Mov>(r11b, static_cast<uint8_t>(1));
buffer.EmitImmediate<OpCode::Mov>(r11w, static_cast<uint16_t>(1));
buffer.EmitImmediate<OpCode::Mov>(r11d, 1);
buffer.EmitImmediate<OpCode::Mov>(r11, 1);
buffer.Emit<OpCode::Mov>(r11b, r11b);
buffer.Emit<OpCode::Mov>(r11w, r11w);
buffer.Emit<OpCode::Mov>(r11d, r11d);
buffer.Emit<OpCode::Mov>(r11, r11);
buffer.Emit<OpCode::Mov>(r11b, r11, -4);
buffer.Emit<OpCode::Mov>(r11b, r11, 4);
buffer.Emit<OpCode::Mov>(r11w, r11, 4);
buffer.Emit<OpCode::Mov>(r11d, r11, 4);
buffer.Emit<OpCode::Mov>(r11, r11, 4);
buffer.Emit<OpCode::Mov>(r11, -4, r11b);
buffer.Emit<OpCode::Mov>(r11, 4, r11b);
buffer.Emit<OpCode::Mov>(r11, 4, r11w);
buffer.Emit<OpCode::Mov>(r11, 4, r11d);
buffer.Emit<OpCode::Mov>(r11, 4, r11);
buffer.Emit<OpCode::MovZX>(r11w, r11b);
buffer.Emit<OpCode::MovZX, 2, false, 1, false>(r11w, r11, 4);
buffer.Emit<OpCode::MovZX>(r11d, r11b);
buffer.Emit<OpCode::MovZX>(r11d, r11w);
buffer.Emit<OpCode::MovZX, 4, false, 1, false>(r11d, r11, 4);
buffer.Emit<OpCode::MovZX, 4, false, 2, false>(r11d, r11, 4);
buffer.Emit<OpCode::MovZX>(r11, r11b);
buffer.Emit<OpCode::MovZX>(r11, r11w);
buffer.Emit<OpCode::MovZX, 8, false, 1, false>(r11, r11, 4);
buffer.Emit<OpCode::MovZX, 8, false, 2, false>(r11, r11, 4);
// Source: r11, target: r12
buffer.EmitImmediate<OpCode::Mov>(r12b, static_cast<uint8_t>(1));
buffer.EmitImmediate<OpCode::Mov>(r12w, static_cast<uint16_t>(1));
buffer.EmitImmediate<OpCode::Mov>(r12d, 1);
buffer.EmitImmediate<OpCode::Mov>(r12, 1);
buffer.Emit<OpCode::Mov>(r12b, r11b);
buffer.Emit<OpCode::Mov>(r12w, r11w);
buffer.Emit<OpCode::Mov>(r12d, r11d);
buffer.Emit<OpCode::Mov>(r12, r11);
buffer.Emit<OpCode::Mov>(r12b, r11, -4);
buffer.Emit<OpCode::Mov>(r12b, r11, 4);
buffer.Emit<OpCode::Mov>(r12w, r11, 4);
buffer.Emit<OpCode::Mov>(r12d, r11, 4);
buffer.Emit<OpCode::Mov>(r12, r11, 4);
buffer.Emit<OpCode::Mov>(r12, -4, r11b);
buffer.Emit<OpCode::Mov>(r12, 4, r11b);
buffer.Emit<OpCode::Mov>(r12, 4, r11w);
buffer.Emit<OpCode::Mov>(r12, 4, r11d);
buffer.Emit<OpCode::Mov>(r12, 4, r11);
buffer.Emit<OpCode::MovZX>(r12w, r11b);
buffer.Emit<OpCode::MovZX, 2, false, 1, false>(r12w, r11, 4);
buffer.Emit<OpCode::MovZX>(r12d, r11b);
buffer.Emit<OpCode::MovZX>(r12d, r11w);
buffer.Emit<OpCode::MovZX, 4, false, 1, false>(r12d, r11, 4);
buffer.Emit<OpCode::MovZX, 4, false, 2, false>(r12d, r11, 4);
buffer.Emit<OpCode::MovZX>(r12, r11b);
buffer.Emit<OpCode::MovZX>(r12, r11w);
buffer.Emit<OpCode::MovZX, 8, false, 1, false>(r12, r11, 4);
buffer.Emit<OpCode::MovZX, 8, false, 2, false>(r12, r11, 4);
// Source: r11, target: r13
buffer.EmitImmediate<OpCode::Mov>(r13b, static_cast<uint8_t>(1));
buffer.EmitImmediate<OpCode::Mov>(r13w, static_cast<uint16_t>(1));
buffer.EmitImmediate<OpCode::Mov>(r13d, 1);
buffer.EmitImmediate<OpCode::Mov>(r13, 1);
buffer.Emit<OpCode::Mov>(r13b, r11b);
buffer.Emit<OpCode::Mov>(r13w, r11w);
buffer.Emit<OpCode::Mov>(r13d, r11d);
buffer.Emit<OpCode::Mov>(r13, r11);
buffer.Emit<OpCode::Mov>(r13b, r11, -4);
buffer.Emit<OpCode::Mov>(r13b, r11, 4);
buffer.Emit<OpCode::Mov>(r13w, r11, 4);
buffer.Emit<OpCode::Mov>(r13d, r11, 4);
buffer.Emit<OpCode::Mov>(r13, r11, 4);
buffer.Emit<OpCode::Mov>(r13, -4, r11b);
buffer.Emit<OpCode::Mov>(r13, 4, r11b);
buffer.Emit<OpCode::Mov>(r13, 4, r11w);
buffer.Emit<OpCode::Mov>(r13, 4, r11d);
buffer.Emit<OpCode::Mov>(r13, 4, r11);
buffer.Emit<OpCode::MovZX>(r13w, r11b);
buffer.Emit<OpCode::MovZX, 2, false, 1, false>(r13w, r11, 4);
buffer.Emit<OpCode::MovZX>(r13d, r11b);
buffer.Emit<OpCode::MovZX>(r13d, r11w);
buffer.Emit<OpCode::MovZX, 4, false, 1, false>(r13d, r11, 4);
buffer.Emit<OpCode::MovZX, 4, false, 2, false>(r13d, r11, 4);
buffer.Emit<OpCode::MovZX>(r13, r11b);
buffer.Emit<OpCode::MovZX>(r13, r11w);
buffer.Emit<OpCode::MovZX, 8, false, 1, false>(r13, r11, 4);
buffer.Emit<OpCode::MovZX, 8, false, 2, false>(r13, r11, 4);
// Source: r11, target: r14
buffer.EmitImmediate<OpCode::Mov>(r14b, static_cast<uint8_t>(1));
buffer.EmitImmediate<OpCode::Mov>(r14w, static_cast<uint16_t>(1));
buffer.EmitImmediate<OpCode::Mov>(r14d, 1);
buffer.EmitImmediate<OpCode::Mov>(r14, 1);
buffer.Emit<OpCode::Mov>(r14b, r11b);
buffer.Emit<OpCode::Mov>(r14w, r11w);
buffer.Emit<OpCode::Mov>(r14d, r11d);
buffer.Emit<OpCode::Mov>(r14, r11);
buffer.Emit<OpCode::Mov>(r14b, r11, -4);
buffer.Emit<OpCode::Mov>(r14b, r11, 4);
buffer.Emit<OpCode::Mov>(r14w, r11, 4);
buffer.Emit<OpCode::Mov>(r14d, r11, 4);
buffer.Emit<OpCode::Mov>(r14, r11, 4);
buffer.Emit<OpCode::Mov>(r14, -4, r11b);
buffer.Emit<OpCode::Mov>(r14, 4, r11b);
buffer.Emit<OpCode::Mov>(r14, 4, r11w);
buffer.Emit<OpCode::Mov>(r14, 4, r11d);
buffer.Emit<OpCode::Mov>(r14, 4, r11);
buffer.Emit<OpCode::MovZX>(r14w, r11b);
buffer.Emit<OpCode::MovZX, 2, false, 1, false>(r14w, r11, 4);
buffer.Emit<OpCode::MovZX>(r14d, r11b);
buffer.Emit<OpCode::MovZX>(r14d, r11w);
buffer.Emit<OpCode::MovZX, 4, false, 1, false>(r14d, r11, 4);
buffer.Emit<OpCode::MovZX, 4, false, 2, false>(r14d, r11, 4);
buffer.Emit<OpCode::MovZX>(r14, r11b);
buffer.Emit<OpCode::MovZX>(r14, r11w);
buffer.Emit<OpCode::MovZX, 8, false, 1, false>(r14, r11, 4);
buffer.Emit<OpCode::MovZX, 8, false, 2, false>(r14, r11, 4);
// Source: r11, target: r15
buffer.EmitImmediate<OpCode::Mov>(r15b, static_cast<uint8_t>(1));
buffer.EmitImmediate<OpCode::Mov>(r15w, static_cast<uint16_t>(1));
buffer.EmitImmediate<OpCode::Mov>(r15d, 1);
buffer.EmitImmediate<OpCode::Mov>(r15, 1);
buffer.Emit<OpCode::Mov>(r15b, r11b);
buffer.Emit<OpCode::Mov>(r15w, r11w);
buffer.Emit<OpCode::Mov>(r15d, r11d);
buffer.Emit<OpCode::Mov>(r15, r11);
buffer.Emit<OpCode::Mov>(r15b, r11, -4);
buffer.Emit<OpCode::Mov>(r15b, r11, 4);
buffer.Emit<OpCode::Mov>(r15w, r11, 4);
buffer.Emit<OpCode::Mov>(r15d, r11, 4);
buffer.Emit<OpCode::Mov>(r15, r11, 4);
buffer.Emit<OpCode::Mov>(r15, -4, r11b);
buffer.Emit<OpCode::Mov>(r15, 4, r11b);
buffer.Emit<OpCode::Mov>(r15, 4, r11w);
buffer.Emit<OpCode::Mov>(r15, 4, r11d);
buffer.Emit<OpCode::Mov>(r15, 4, r11);
buffer.Emit<OpCode::MovZX>(r15w, r11b);
buffer.Emit<OpCode::MovZX, 2, false, 1, false>(r15w, r11, 4);
buffer.Emit<OpCode::MovZX>(r15d, r11b);
buffer.Emit<OpCode::MovZX>(r15d, r11w);
buffer.Emit<OpCode::MovZX, 4, false, 1, false>(r15d, r11, 4);
buffer.Emit<OpCode::MovZX, 4, false, 2, false>(r15d, r11, 4);
buffer.Emit<OpCode::MovZX>(r15, r11b);
buffer.Emit<OpCode::MovZX>(r15, r11w);
buffer.Emit<OpCode::MovZX, 8, false, 1, false>(r15, r11, 4);
buffer.Emit<OpCode::MovZX, 8, false, 2, false>(r15, r11, 4);
// Source: r12, target: rax
buffer.EmitImmediate<OpCode::Mov>(al, static_cast<uint8_t>(1));
buffer.EmitImmediate<OpCode::Mov>(ax, static_cast<uint16_t>(1));
buffer.EmitImmediate<OpCode::Mov>(eax, 1);
buffer.EmitImmediate<OpCode::Mov>(rax, 1);
buffer.Emit<OpCode::Mov>(al, r12b);
buffer.Emit<OpCode::Mov>(ax, r12w);
buffer.Emit<OpCode::Mov>(eax, r12d);
buffer.Emit<OpCode::Mov>(rax, r12);
buffer.Emit<OpCode::Mov>(al, r12, -4);
buffer.Emit<OpCode::Mov>(al, r12, 4);
buffer.Emit<OpCode::Mov>(ax, r12, 4);
buffer.Emit<OpCode::Mov>(eax, r12, 4);
buffer.Emit<OpCode::Mov>(rax, r12, 4);
buffer.Emit<OpCode::Mov>(rax, -4, r12b);
buffer.Emit<OpCode::Mov>(rax, 4, r12b);
buffer.Emit<OpCode::Mov>(rax, 4, r12w);
buffer.Emit<OpCode::Mov>(rax, 4, r12d);
buffer.Emit<OpCode::Mov>(rax, 4, r12);
buffer.Emit<OpCode::MovZX>(ax, r12b);
buffer.Emit<OpCode::MovZX, 2, false, 1, false>(ax, r12, 4);
buffer.Emit<OpCode::MovZX>(eax, r12b);
buffer.Emit<OpCode::MovZX>(eax, r12w);
buffer.Emit<OpCode::MovZX, 4, false, 1, false>(eax, r12, 4);
buffer.Emit<OpCode::MovZX, 4, false, 2, false>(eax, r12, 4);
buffer.Emit<OpCode::MovZX>(rax, r12b);
buffer.Emit<OpCode::MovZX>(rax, r12w);
buffer.Emit<OpCode::MovZX, 8, false, 1, false>(rax, r12, 4);
buffer.Emit<OpCode::MovZX, 8, false, 2, false>(rax, r12, 4);
// Source: r12, target: rcx
buffer.EmitImmediate<OpCode::Mov>(cl, static_cast<uint8_t>(1));
buffer.EmitImmediate<OpCode::Mov>(cx, static_cast<uint16_t>(1));
buffer.EmitImmediate<OpCode::Mov>(ecx, 1);
buffer.EmitImmediate<OpCode::Mov>(rcx, 1);
buffer.Emit<OpCode::Mov>(cl, r12b);
buffer.Emit<OpCode::Mov>(cx, r12w);
buffer.Emit<OpCode::Mov>(ecx, r12d);
buffer.Emit<OpCode::Mov>(rcx, r12);
buffer.Emit<OpCode::Mov>(cl, r12, -4);
buffer.Emit<OpCode::Mov>(cl, r12, 4);
buffer.Emit<OpCode::Mov>(cx, r12, 4);
buffer.Emit<OpCode::Mov>(ecx, r12, 4);
buffer.Emit<OpCode::Mov>(rcx, r12, 4);
buffer.Emit<OpCode::Mov>(rcx, -4, r12b);
buffer.Emit<OpCode::Mov>(rcx, 4, r12b);
buffer.Emit<OpCode::Mov>(rcx, 4, r12w);
buffer.Emit<OpCode::Mov>(rcx, 4, r12d);
buffer.Emit<OpCode::Mov>(rcx, 4, r12);
buffer.Emit<OpCode::MovZX>(cx, r12b);
buffer.Emit<OpCode::MovZX, 2, false, 1, false>(cx, r12, 4);
buffer.Emit<OpCode::MovZX>(ecx, r12b);
buffer.Emit<OpCode::MovZX>(ecx, r12w);
buffer.Emit<OpCode::MovZX, 4, false, 1, false>(ecx, r12, 4);
buffer.Emit<OpCode::MovZX, 4, false, 2, false>(ecx, r12, 4);
buffer.Emit<OpCode::MovZX>(rcx, r12b);
buffer.Emit<OpCode::MovZX>(rcx, r12w);
buffer.Emit<OpCode::MovZX, 8, false, 1, false>(rcx, r12, 4);
buffer.Emit<OpCode::MovZX, 8, false, 2, false>(rcx, r12, 4);
// Source: r12, target: rdx
buffer.EmitImmediate<OpCode::Mov>(dl, static_cast<uint8_t>(1));
buffer.EmitImmediate<OpCode::Mov>(dx, static_cast<uint16_t>(1));
buffer.EmitImmediate<OpCode::Mov>(edx, 1);
buffer.EmitImmediate<OpCode::Mov>(rdx, 1);
buffer.Emit<OpCode::Mov>(dl, r12b);
buffer.Emit<OpCode::Mov>(dx, r12w);
buffer.Emit<OpCode::Mov>(edx, r12d);
buffer.Emit<OpCode::Mov>(rdx, r12);
buffer.Emit<OpCode::Mov>(dl, r12, -4);
buffer.Emit<OpCode::Mov>(dl, r12, 4);
buffer.Emit<OpCode::Mov>(dx, r12, 4);
buffer.Emit<OpCode::Mov>(edx, r12, 4);
buffer.Emit<OpCode::Mov>(rdx, r12, 4);
buffer.Emit<OpCode::Mov>(rdx, -4, r12b);
buffer.Emit<OpCode::Mov>(rdx, 4, r12b);
buffer.Emit<OpCode::Mov>(rdx, 4, r12w);
buffer.Emit<OpCode::Mov>(rdx, 4, r12d);
buffer.Emit<OpCode::Mov>(rdx, 4, r12);
buffer.Emit<OpCode::MovZX>(dx, r12b);
buffer.Emit<OpCode::MovZX, 2, false, 1, false>(dx, r12, 4);
buffer.Emit<OpCode::MovZX>(edx, r12b);
buffer.Emit<OpCode::MovZX>(edx, r12w);
buffer.Emit<OpCode::MovZX, 4, false, 1, false>(edx, r12, 4);
buffer.Emit<OpCode::MovZX, 4, false, 2, false>(edx, r12, 4);
buffer.Emit<OpCode::MovZX>(rdx, r12b);
buffer.Emit<OpCode::MovZX>(rdx, r12w);
buffer.Emit<OpCode::MovZX, 8, false, 1, false>(rdx, r12, 4);
buffer.Emit<OpCode::MovZX, 8, false, 2, false>(rdx, r12, 4);
// Source: r12, target: rbx
buffer.EmitImmediate<OpCode::Mov>(bl, static_cast<uint8_t>(1));
buffer.EmitImmediate<OpCode::Mov>(bx, static_cast<uint16_t>(1));
buffer.EmitImmediate<OpCode::Mov>(ebx, 1);
buffer.EmitImmediate<OpCode::Mov>(rbx, 1);
buffer.Emit<OpCode::Mov>(bl, r12b);
buffer.Emit<OpCode::Mov>(bx, r12w);
buffer.Emit<OpCode::Mov>(ebx, r12d);
buffer.Emit<OpCode::Mov>(rbx, r12);
buffer.Emit<OpCode::Mov>(bl, r12, -4);
buffer.Emit<OpCode::Mov>(bl, r12, 4);
buffer.Emit<OpCode::Mov>(bx, r12, 4);
buffer.Emit<OpCode::Mov>(ebx, r12, 4);
buffer.Emit<OpCode::Mov>(rbx, r12, 4);
buffer.Emit<OpCode::Mov>(rbx, -4, r12b);
buffer.Emit<OpCode::Mov>(rbx, 4, r12b);
buffer.Emit<OpCode::Mov>(rbx, 4, r12w);
buffer.Emit<OpCode::Mov>(rbx, 4, r12d);
buffer.Emit<OpCode::Mov>(rbx, 4, r12);
buffer.Emit<OpCode::MovZX>(bx, r12b);
buffer.Emit<OpCode::MovZX, 2, false, 1, false>(bx, r12, 4);
buffer.Emit<OpCode::MovZX>(ebx, r12b);
buffer.Emit<OpCode::MovZX>(ebx, r12w);
buffer.Emit<OpCode::MovZX, 4, false, 1, false>(ebx, r12, 4);
buffer.Emit<OpCode::MovZX, 4, false, 2, false>(ebx, r12, 4);
buffer.Emit<OpCode::MovZX>(rbx, r12b);
buffer.Emit<OpCode::MovZX>(rbx, r12w);
buffer.Emit<OpCode::MovZX, 8, false, 1, false>(rbx, r12, 4);
buffer.Emit<OpCode::MovZX, 8, false, 2, false>(rbx, r12, 4);
// Source: r12, target: rsp
buffer.EmitImmediate<OpCode::Mov>(spl, static_cast<uint8_t>(1));
buffer.EmitImmediate<OpCode::Mov>(sp, static_cast<uint16_t>(1));
buffer.EmitImmediate<OpCode::Mov>(esp, 1);
buffer.EmitImmediate<OpCode::Mov>(rsp, 1);
buffer.Emit<OpCode::Mov>(spl, r12b);
buffer.Emit<OpCode::Mov>(sp, r12w);
buffer.Emit<OpCode::Mov>(esp, r12d);
buffer.Emit<OpCode::Mov>(rsp, r12);
buffer.Emit<OpCode::Mov>(spl, r12, -4);
buffer.Emit<OpCode::Mov>(spl, r12, 4);
buffer.Emit<OpCode::Mov>(sp, r12, 4);
buffer.Emit<OpCode::Mov>(esp, r12, 4);
buffer.Emit<OpCode::Mov>(rsp, r12, 4);
buffer.Emit<OpCode::Mov>(rsp, -4, r12b);
buffer.Emit<OpCode::Mov>(rsp, 4, r12b);
buffer.Emit<OpCode::Mov>(rsp, 4, r12w);
buffer.Emit<OpCode::Mov>(rsp, 4, r12d);
buffer.Emit<OpCode::Mov>(rsp, 4, r12);
buffer.Emit<OpCode::MovZX>(sp, r12b);
buffer.Emit<OpCode::MovZX, 2, false, 1, false>(sp, r12, 4);
buffer.Emit<OpCode::MovZX>(esp, r12b);
buffer.Emit<OpCode::MovZX>(esp, r12w);
buffer.Emit<OpCode::MovZX, 4, false, 1, false>(esp, r12, 4);
buffer.Emit<OpCode::MovZX, 4, false, 2, false>(esp, r12, 4);
buffer.Emit<OpCode::MovZX>(rsp, r12b);
buffer.Emit<OpCode::MovZX>(rsp, r12w);
buffer.Emit<OpCode::MovZX, 8, false, 1, false>(rsp, r12, 4);
buffer.Emit<OpCode::MovZX, 8, false, 2, false>(rsp, r12, 4);
// Source: r12, target: rbp
buffer.EmitImmediate<OpCode::Mov>(bpl, static_cast<uint8_t>(1));
buffer.EmitImmediate<OpCode::Mov>(bp, static_cast<uint16_t>(1));
buffer.EmitImmediate<OpCode::Mov>(ebp, 1);
buffer.EmitImmediate<OpCode::Mov>(rbp, 1);
buffer.Emit<OpCode::Mov>(bpl, r12b);
buffer.Emit<OpCode::Mov>(bp, r12w);
buffer.Emit<OpCode::Mov>(ebp, r12d);
buffer.Emit<OpCode::Mov>(rbp, r12);
buffer.Emit<OpCode::Mov>(bpl, r12, -4);
buffer.Emit<OpCode::Mov>(bpl, r12, 4);
buffer.Emit<OpCode::Mov>(bp, r12, 4);
buffer.Emit<OpCode::Mov>(ebp, r12, 4);
buffer.Emit<OpCode::Mov>(rbp, r12, 4);
buffer.Emit<OpCode::Mov>(rbp, -4, r12b);
buffer.Emit<OpCode::Mov>(rbp, 4, r12b);
buffer.Emit<OpCode::Mov>(rbp, 4, r12w);
buffer.Emit<OpCode::Mov>(rbp, 4, r12d);
buffer.Emit<OpCode::Mov>(rbp, 4, r12);
buffer.Emit<OpCode::MovZX>(bp, r12b);
buffer.Emit<OpCode::MovZX, 2, false, 1, false>(bp, r12, 4);
buffer.Emit<OpCode::MovZX>(ebp, r12b);
buffer.Emit<OpCode::MovZX>(ebp, r12w);
buffer.Emit<OpCode::MovZX, 4, false, 1, false>(ebp, r12, 4);
buffer.Emit<OpCode::MovZX, 4, false, 2, false>(ebp, r12, 4);
buffer.Emit<OpCode::MovZX>(rbp, r12b);
buffer.Emit<OpCode::MovZX>(rbp, r12w);
buffer.Emit<OpCode::MovZX, 8, false, 1, false>(rbp, r12, 4);
buffer.Emit<OpCode::MovZX, 8, false, 2, false>(rbp, r12, 4);
// Source: r12, target: rsi
buffer.EmitImmediate<OpCode::Mov>(dil, static_cast<uint8_t>(1));
buffer.EmitImmediate<OpCode::Mov>(si, static_cast<uint16_t>(1));
buffer.EmitImmediate<OpCode::Mov>(esi, 1);
buffer.EmitImmediate<OpCode::Mov>(rsi, 1);
buffer.Emit<OpCode::Mov>(dil, r12b);
buffer.Emit<OpCode::Mov>(si, r12w);
buffer.Emit<OpCode::Mov>(esi, r12d);
buffer.Emit<OpCode::Mov>(rsi, r12);
buffer.Emit<OpCode::Mov>(dil, r12, -4);
buffer.Emit<OpCode::Mov>(dil, r12, 4);
buffer.Emit<OpCode::Mov>(si, r12, 4);
buffer.Emit<OpCode::Mov>(esi, r12, 4);
buffer.Emit<OpCode::Mov>(rsi, r12, 4);
buffer.Emit<OpCode::Mov>(rsi, -4, r12b);
buffer.Emit<OpCode::Mov>(rsi, 4, r12b);
buffer.Emit<OpCode::Mov>(rsi, 4, r12w);
buffer.Emit<OpCode::Mov>(rsi, 4, r12d);
buffer.Emit<OpCode::Mov>(rsi, 4, r12);
buffer.Emit<OpCode::MovZX>(si, r12b);
buffer.Emit<OpCode::MovZX, 2, false, 1, false>(si, r12, 4);
buffer.Emit<OpCode::MovZX>(esi, r12b);
buffer.Emit<OpCode::MovZX>(esi, r12w);
buffer.Emit<OpCode::MovZX, 4, false, 1, false>(esi, r12, 4);
buffer.Emit<OpCode::MovZX, 4, false, 2, false>(esi, r12, 4);
buffer.Emit<OpCode::MovZX>(rsi, r12b);
buffer.Emit<OpCode::MovZX>(rsi, r12w);
buffer.Emit<OpCode::MovZX, 8, false, 1, false>(rsi, r12, 4);
buffer.Emit<OpCode::MovZX, 8, false, 2, false>(rsi, r12, 4);
// Source: r12, target: rdi
buffer.EmitImmediate<OpCode::Mov>(sil, static_cast<uint8_t>(1));
buffer.EmitImmediate<OpCode::Mov>(di, static_cast<uint16_t>(1));
buffer.EmitImmediate<OpCode::Mov>(edi, 1);
buffer.EmitImmediate<OpCode::Mov>(rdi, 1);
buffer.Emit<OpCode::Mov>(sil, r12b);
buffer.Emit<OpCode::Mov>(di, r12w);
buffer.Emit<OpCode::Mov>(edi, r12d);
buffer.Emit<OpCode::Mov>(rdi, r12);
buffer.Emit<OpCode::Mov>(sil, r12, -4);
buffer.Emit<OpCode::Mov>(sil, r12, 4);
buffer.Emit<OpCode::Mov>(di, r12, 4);
buffer.Emit<OpCode::Mov>(edi, r12, 4);
buffer.Emit<OpCode::Mov>(rdi, r12, 4);
buffer.Emit<OpCode::Mov>(rdi, -4, r12b);
buffer.Emit<OpCode::Mov>(rdi, 4, r12b);
buffer.Emit<OpCode::Mov>(rdi, 4, r12w);
buffer.Emit<OpCode::Mov>(rdi, 4, r12d);
buffer.Emit<OpCode::Mov>(rdi, 4, r12);
buffer.Emit<OpCode::MovZX>(di, r12b);
buffer.Emit<OpCode::MovZX, 2, false, 1, false>(di, r12, 4);
buffer.Emit<OpCode::MovZX>(edi, r12b);
buffer.Emit<OpCode::MovZX>(edi, r12w);
buffer.Emit<OpCode::MovZX, 4, false, 1, false>(edi, r12, 4);
buffer.Emit<OpCode::MovZX, 4, false, 2, false>(edi, r12, 4);
buffer.Emit<OpCode::MovZX>(rdi, r12b);
buffer.Emit<OpCode::MovZX>(rdi, r12w);
buffer.Emit<OpCode::MovZX, 8, false, 1, false>(rdi, r12, 4);
buffer.Emit<OpCode::MovZX, 8, false, 2, false>(rdi, r12, 4);
// Source: r12, target: r8
buffer.EmitImmediate<OpCode::Mov>(r8b, static_cast<uint8_t>(1));
buffer.EmitImmediate<OpCode::Mov>(r8w, static_cast<uint16_t>(1));
buffer.EmitImmediate<OpCode::Mov>(r8d, 1);
buffer.EmitImmediate<OpCode::Mov>(r8, 1);
buffer.Emit<OpCode::Mov>(r8b, r12b);
buffer.Emit<OpCode::Mov>(r8w, r12w);
buffer.Emit<OpCode::Mov>(r8d, r12d);
buffer.Emit<OpCode::Mov>(r8, r12);
buffer.Emit<OpCode::Mov>(r8b, r12, -4);
buffer.Emit<OpCode::Mov>(r8b, r12, 4);
buffer.Emit<OpCode::Mov>(r8w, r12, 4);
buffer.Emit<OpCode::Mov>(r8d, r12, 4);
buffer.Emit<OpCode::Mov>(r8, r12, 4);
buffer.Emit<OpCode::Mov>(r8, -4, r12b);
buffer.Emit<OpCode::Mov>(r8, 4, r12b);
buffer.Emit<OpCode::Mov>(r8, 4, r12w);
buffer.Emit<OpCode::Mov>(r8, 4, r12d);
buffer.Emit<OpCode::Mov>(r8, 4, r12);
buffer.Emit<OpCode::MovZX>(r8w, r12b);
buffer.Emit<OpCode::MovZX, 2, false, 1, false>(r8w, r12, 4);
buffer.Emit<OpCode::MovZX>(r8d, r12b);
buffer.Emit<OpCode::MovZX>(r8d, r12w);
buffer.Emit<OpCode::MovZX, 4, false, 1, false>(r8d, r12, 4);
buffer.Emit<OpCode::MovZX, 4, false, 2, false>(r8d, r12, 4);
buffer.Emit<OpCode::MovZX>(r8, r12b);
buffer.Emit<OpCode::MovZX>(r8, r12w);
buffer.Emit<OpCode::MovZX, 8, false, 1, false>(r8, r12, 4);
buffer.Emit<OpCode::MovZX, 8, false, 2, false>(r8, r12, 4);
// Source: r12, target: r9
buffer.EmitImmediate<OpCode::Mov>(r9b, static_cast<uint8_t>(1));
buffer.EmitImmediate<OpCode::Mov>(r9w, static_cast<uint16_t>(1));
buffer.EmitImmediate<OpCode::Mov>(r9d, 1);
buffer.EmitImmediate<OpCode::Mov>(r9, 1);
buffer.Emit<OpCode::Mov>(r9b, r12b);
buffer.Emit<OpCode::Mov>(r9w, r12w);
buffer.Emit<OpCode::Mov>(r9d, r12d);
buffer.Emit<OpCode::Mov>(r9, r12);
buffer.Emit<OpCode::Mov>(r9b, r12, -4);
buffer.Emit<OpCode::Mov>(r9b, r12, 4);
buffer.Emit<OpCode::Mov>(r9w, r12, 4);
buffer.Emit<OpCode::Mov>(r9d, r12, 4);
buffer.Emit<OpCode::Mov>(r9, r12, 4);
buffer.Emit<OpCode::Mov>(r9, -4, r12b);
buffer.Emit<OpCode::Mov>(r9, 4, r12b);
buffer.Emit<OpCode::Mov>(r9, 4, r12w);
buffer.Emit<OpCode::Mov>(r9, 4, r12d);
buffer.Emit<OpCode::Mov>(r9, 4, r12);
buffer.Emit<OpCode::MovZX>(r9w, r12b);
buffer.Emit<OpCode::MovZX, 2, false, 1, false>(r9w, r12, 4);
buffer.Emit<OpCode::MovZX>(r9d, r12b);
buffer.Emit<OpCode::MovZX>(r9d, r12w);
buffer.Emit<OpCode::MovZX, 4, false, 1, false>(r9d, r12, 4);
buffer.Emit<OpCode::MovZX, 4, false, 2, false>(r9d, r12, 4);
buffer.Emit<OpCode::MovZX>(r9, r12b);
buffer.Emit<OpCode::MovZX>(r9, r12w);
buffer.Emit<OpCode::MovZX, 8, false, 1, false>(r9, r12, 4);
buffer.Emit<OpCode::MovZX, 8, false, 2, false>(r9, r12, 4);
// Source: r12, target: r10
buffer.EmitImmediate<OpCode::Mov>(r10b, static_cast<uint8_t>(1));
buffer.EmitImmediate<OpCode::Mov>(r10w, static_cast<uint16_t>(1));
buffer.EmitImmediate<OpCode::Mov>(r10d, 1);
buffer.EmitImmediate<OpCode::Mov>(r10, 1);
buffer.Emit<OpCode::Mov>(r10b, r12b);
buffer.Emit<OpCode::Mov>(r10w, r12w);
buffer.Emit<OpCode::Mov>(r10d, r12d);
buffer.Emit<OpCode::Mov>(r10, r12);
buffer.Emit<OpCode::Mov>(r10b, r12, -4);
buffer.Emit<OpCode::Mov>(r10b, r12, 4);
buffer.Emit<OpCode::Mov>(r10w, r12, 4);
buffer.Emit<OpCode::Mov>(r10d, r12, 4);
buffer.Emit<OpCode::Mov>(r10, r12, 4);
buffer.Emit<OpCode::Mov>(r10, -4, r12b);
buffer.Emit<OpCode::Mov>(r10, 4, r12b);
buffer.Emit<OpCode::Mov>(r10, 4, r12w);
buffer.Emit<OpCode::Mov>(r10, 4, r12d);
buffer.Emit<OpCode::Mov>(r10, 4, r12);
buffer.Emit<OpCode::MovZX>(r10w, r12b);
buffer.Emit<OpCode::MovZX, 2, false, 1, false>(r10w, r12, 4);
buffer.Emit<OpCode::MovZX>(r10d, r12b);
buffer.Emit<OpCode::MovZX>(r10d, r12w);
buffer.Emit<OpCode::MovZX, 4, false, 1, false>(r10d, r12, 4);
buffer.Emit<OpCode::MovZX, 4, false, 2, false>(r10d, r12, 4);
buffer.Emit<OpCode::MovZX>(r10, r12b);
buffer.Emit<OpCode::MovZX>(r10, r12w);
buffer.Emit<OpCode::MovZX, 8, false, 1, false>(r10, r12, 4);
buffer.Emit<OpCode::MovZX, 8, false, 2, false>(r10, r12, 4);
// Source: r12, target: r11
buffer.EmitImmediate<OpCode::Mov>(r11b, static_cast<uint8_t>(1));
buffer.EmitImmediate<OpCode::Mov>(r11w, static_cast<uint16_t>(1));
buffer.EmitImmediate<OpCode::Mov>(r11d, 1);
buffer.EmitImmediate<OpCode::Mov>(r11, 1);
buffer.Emit<OpCode::Mov>(r11b, r12b);
buffer.Emit<OpCode::Mov>(r11w, r12w);
buffer.Emit<OpCode::Mov>(r11d, r12d);
buffer.Emit<OpCode::Mov>(r11, r12);
buffer.Emit<OpCode::Mov>(r11b, r12, -4);
buffer.Emit<OpCode::Mov>(r11b, r12, 4);
buffer.Emit<OpCode::Mov>(r11w, r12, 4);
buffer.Emit<OpCode::Mov>(r11d, r12, 4);
buffer.Emit<OpCode::Mov>(r11, r12, 4);
buffer.Emit<OpCode::Mov>(r11, -4, r12b);
buffer.Emit<OpCode::Mov>(r11, 4, r12b);
buffer.Emit<OpCode::Mov>(r11, 4, r12w);
buffer.Emit<OpCode::Mov>(r11, 4, r12d);
buffer.Emit<OpCode::Mov>(r11, 4, r12);
buffer.Emit<OpCode::MovZX>(r11w, r12b);
buffer.Emit<OpCode::MovZX, 2, false, 1, false>(r11w, r12, 4);
buffer.Emit<OpCode::MovZX>(r11d, r12b);
buffer.Emit<OpCode::MovZX>(r11d, r12w);
buffer.Emit<OpCode::MovZX, 4, false, 1, false>(r11d, r12, 4);
buffer.Emit<OpCode::MovZX, 4, false, 2, false>(r11d, r12, 4);
buffer.Emit<OpCode::MovZX>(r11, r12b);
buffer.Emit<OpCode::MovZX>(r11, r12w);
buffer.Emit<OpCode::MovZX, 8, false, 1, false>(r11, r12, 4);
buffer.Emit<OpCode::MovZX, 8, false, 2, false>(r11, r12, 4);
// Source: r12, target: r12
buffer.EmitImmediate<OpCode::Mov>(r12b, static_cast<uint8_t>(1));
buffer.EmitImmediate<OpCode::Mov>(r12w, static_cast<uint16_t>(1));
buffer.EmitImmediate<OpCode::Mov>(r12d, 1);
buffer.EmitImmediate<OpCode::Mov>(r12, 1);
buffer.Emit<OpCode::Mov>(r12b, r12b);
buffer.Emit<OpCode::Mov>(r12w, r12w);
buffer.Emit<OpCode::Mov>(r12d, r12d);
buffer.Emit<OpCode::Mov>(r12, r12);
buffer.Emit<OpCode::Mov>(r12b, r12, -4);
buffer.Emit<OpCode::Mov>(r12b, r12, 4);
buffer.Emit<OpCode::Mov>(r12w, r12, 4);
buffer.Emit<OpCode::Mov>(r12d, r12, 4);
buffer.Emit<OpCode::Mov>(r12, r12, 4);
buffer.Emit<OpCode::Mov>(r12, -4, r12b);
buffer.Emit<OpCode::Mov>(r12, 4, r12b);
buffer.Emit<OpCode::Mov>(r12, 4, r12w);
buffer.Emit<OpCode::Mov>(r12, 4, r12d);
buffer.Emit<OpCode::Mov>(r12, 4, r12);
buffer.Emit<OpCode::MovZX>(r12w, r12b);
buffer.Emit<OpCode::MovZX, 2, false, 1, false>(r12w, r12, 4);
buffer.Emit<OpCode::MovZX>(r12d, r12b);
buffer.Emit<OpCode::MovZX>(r12d, r12w);
buffer.Emit<OpCode::MovZX, 4, false, 1, false>(r12d, r12, 4);
buffer.Emit<OpCode::MovZX, 4, false, 2, false>(r12d, r12, 4);
buffer.Emit<OpCode::MovZX>(r12, r12b);
buffer.Emit<OpCode::MovZX>(r12, r12w);
buffer.Emit<OpCode::MovZX, 8, false, 1, false>(r12, r12, 4);
buffer.Emit<OpCode::MovZX, 8, false, 2, false>(r12, r12, 4);
// Source: r12, target: r13
buffer.EmitImmediate<OpCode::Mov>(r13b, static_cast<uint8_t>(1));
buffer.EmitImmediate<OpCode::Mov>(r13w, static_cast<uint16_t>(1));
buffer.EmitImmediate<OpCode::Mov>(r13d, 1);
buffer.EmitImmediate<OpCode::Mov>(r13, 1);
buffer.Emit<OpCode::Mov>(r13b, r12b);
buffer.Emit<OpCode::Mov>(r13w, r12w);
buffer.Emit<OpCode::Mov>(r13d, r12d);
buffer.Emit<OpCode::Mov>(r13, r12);
buffer.Emit<OpCode::Mov>(r13b, r12, -4);
buffer.Emit<OpCode::Mov>(r13b, r12, 4);
buffer.Emit<OpCode::Mov>(r13w, r12, 4);
buffer.Emit<OpCode::Mov>(r13d, r12, 4);
buffer.Emit<OpCode::Mov>(r13, r12, 4);
buffer.Emit<OpCode::Mov>(r13, -4, r12b);
buffer.Emit<OpCode::Mov>(r13, 4, r12b);
buffer.Emit<OpCode::Mov>(r13, 4, r12w);
buffer.Emit<OpCode::Mov>(r13, 4, r12d);
buffer.Emit<OpCode::Mov>(r13, 4, r12);
buffer.Emit<OpCode::MovZX>(r13w, r12b);
buffer.Emit<OpCode::MovZX, 2, false, 1, false>(r13w, r12, 4);
buffer.Emit<OpCode::MovZX>(r13d, r12b);
buffer.Emit<OpCode::MovZX>(r13d, r12w);
buffer.Emit<OpCode::MovZX, 4, false, 1, false>(r13d, r12, 4);
buffer.Emit<OpCode::MovZX, 4, false, 2, false>(r13d, r12, 4);
buffer.Emit<OpCode::MovZX>(r13, r12b);
buffer.Emit<OpCode::MovZX>(r13, r12w);
buffer.Emit<OpCode::MovZX, 8, false, 1, false>(r13, r12, 4);
buffer.Emit<OpCode::MovZX, 8, false, 2, false>(r13, r12, 4);
// Source: r12, target: r14
buffer.EmitImmediate<OpCode::Mov>(r14b, static_cast<uint8_t>(1));
buffer.EmitImmediate<OpCode::Mov>(r14w, static_cast<uint16_t>(1));
buffer.EmitImmediate<OpCode::Mov>(r14d, 1);
buffer.EmitImmediate<OpCode::Mov>(r14, 1);
buffer.Emit<OpCode::Mov>(r14b, r12b);
buffer.Emit<OpCode::Mov>(r14w, r12w);
buffer.Emit<OpCode::Mov>(r14d, r12d);
buffer.Emit<OpCode::Mov>(r14, r12);
buffer.Emit<OpCode::Mov>(r14b, r12, -4);
buffer.Emit<OpCode::Mov>(r14b, r12, 4);
buffer.Emit<OpCode::Mov>(r14w, r12, 4);
buffer.Emit<OpCode::Mov>(r14d, r12, 4);
buffer.Emit<OpCode::Mov>(r14, r12, 4);
buffer.Emit<OpCode::Mov>(r14, -4, r12b);
buffer.Emit<OpCode::Mov>(r14, 4, r12b);
buffer.Emit<OpCode::Mov>(r14, 4, r12w);
buffer.Emit<OpCode::Mov>(r14, 4, r12d);
buffer.Emit<OpCode::Mov>(r14, 4, r12);
buffer.Emit<OpCode::MovZX>(r14w, r12b);
buffer.Emit<OpCode::MovZX, 2, false, 1, false>(r14w, r12, 4);
buffer.Emit<OpCode::MovZX>(r14d, r12b);
buffer.Emit<OpCode::MovZX>(r14d, r12w);
buffer.Emit<OpCode::MovZX, 4, false, 1, false>(r14d, r12, 4);
buffer.Emit<OpCode::MovZX, 4, false, 2, false>(r14d, r12, 4);
buffer.Emit<OpCode::MovZX>(r14, r12b);
buffer.Emit<OpCode::MovZX>(r14, r12w);
buffer.Emit<OpCode::MovZX, 8, false, 1, false>(r14, r12, 4);
buffer.Emit<OpCode::MovZX, 8, false, 2, false>(r14, r12, 4);
// Source: r12, target: r15
buffer.EmitImmediate<OpCode::Mov>(r15b, static_cast<uint8_t>(1));
buffer.EmitImmediate<OpCode::Mov>(r15w, static_cast<uint16_t>(1));
buffer.EmitImmediate<OpCode::Mov>(r15d, 1);
buffer.EmitImmediate<OpCode::Mov>(r15, 1);
buffer.Emit<OpCode::Mov>(r15b, r12b);
buffer.Emit<OpCode::Mov>(r15w, r12w);
buffer.Emit<OpCode::Mov>(r15d, r12d);
buffer.Emit<OpCode::Mov>(r15, r12);
buffer.Emit<OpCode::Mov>(r15b, r12, -4);
buffer.Emit<OpCode::Mov>(r15b, r12, 4);
buffer.Emit<OpCode::Mov>(r15w, r12, 4);
buffer.Emit<OpCode::Mov>(r15d, r12, 4);
buffer.Emit<OpCode::Mov>(r15, r12, 4);
buffer.Emit<OpCode::Mov>(r15, -4, r12b);
buffer.Emit<OpCode::Mov>(r15, 4, r12b);
buffer.Emit<OpCode::Mov>(r15, 4, r12w);
buffer.Emit<OpCode::Mov>(r15, 4, r12d);
buffer.Emit<OpCode::Mov>(r15, 4, r12);
buffer.Emit<OpCode::MovZX>(r15w, r12b);
buffer.Emit<OpCode::MovZX, 2, false, 1, false>(r15w, r12, 4);
buffer.Emit<OpCode::MovZX>(r15d, r12b);
buffer.Emit<OpCode::MovZX>(r15d, r12w);
buffer.Emit<OpCode::MovZX, 4, false, 1, false>(r15d, r12, 4);
buffer.Emit<OpCode::MovZX, 4, false, 2, false>(r15d, r12, 4);
buffer.Emit<OpCode::MovZX>(r15, r12b);
buffer.Emit<OpCode::MovZX>(r15, r12w);
buffer.Emit<OpCode::MovZX, 8, false, 1, false>(r15, r12, 4);
buffer.Emit<OpCode::MovZX, 8, false, 2, false>(r15, r12, 4);
// Source: r13, target: rax
buffer.EmitImmediate<OpCode::Mov>(al, static_cast<uint8_t>(1));
buffer.EmitImmediate<OpCode::Mov>(ax, static_cast<uint16_t>(1));
buffer.EmitImmediate<OpCode::Mov>(eax, 1);
buffer.EmitImmediate<OpCode::Mov>(rax, 1);
buffer.Emit<OpCode::Mov>(al, r13b);
buffer.Emit<OpCode::Mov>(ax, r13w);
buffer.Emit<OpCode::Mov>(eax, r13d);
buffer.Emit<OpCode::Mov>(rax, r13);
buffer.Emit<OpCode::Mov>(al, r13, -4);
buffer.Emit<OpCode::Mov>(al, r13, 4);
buffer.Emit<OpCode::Mov>(ax, r13, 4);
buffer.Emit<OpCode::Mov>(eax, r13, 4);
buffer.Emit<OpCode::Mov>(rax, r13, 4);
buffer.Emit<OpCode::Mov>(rax, -4, r13b);
buffer.Emit<OpCode::Mov>(rax, 4, r13b);
buffer.Emit<OpCode::Mov>(rax, 4, r13w);
buffer.Emit<OpCode::Mov>(rax, 4, r13d);
buffer.Emit<OpCode::Mov>(rax, 4, r13);
buffer.Emit<OpCode::MovZX>(ax, r13b);
buffer.Emit<OpCode::MovZX, 2, false, 1, false>(ax, r13, 4);
buffer.Emit<OpCode::MovZX>(eax, r13b);
buffer.Emit<OpCode::MovZX>(eax, r13w);
buffer.Emit<OpCode::MovZX, 4, false, 1, false>(eax, r13, 4);
buffer.Emit<OpCode::MovZX, 4, false, 2, false>(eax, r13, 4);
buffer.Emit<OpCode::MovZX>(rax, r13b);
buffer.Emit<OpCode::MovZX>(rax, r13w);
buffer.Emit<OpCode::MovZX, 8, false, 1, false>(rax, r13, 4);
buffer.Emit<OpCode::MovZX, 8, false, 2, false>(rax, r13, 4);
// Source: r13, target: rcx
buffer.EmitImmediate<OpCode::Mov>(cl, static_cast<uint8_t>(1));
buffer.EmitImmediate<OpCode::Mov>(cx, static_cast<uint16_t>(1));
buffer.EmitImmediate<OpCode::Mov>(ecx, 1);
buffer.EmitImmediate<OpCode::Mov>(rcx, 1);
buffer.Emit<OpCode::Mov>(cl, r13b);
buffer.Emit<OpCode::Mov>(cx, r13w);
buffer.Emit<OpCode::Mov>(ecx, r13d);
buffer.Emit<OpCode::Mov>(rcx, r13);
buffer.Emit<OpCode::Mov>(cl, r13, -4);
buffer.Emit<OpCode::Mov>(cl, r13, 4);
buffer.Emit<OpCode::Mov>(cx, r13, 4);
buffer.Emit<OpCode::Mov>(ecx, r13, 4);
buffer.Emit<OpCode::Mov>(rcx, r13, 4);
buffer.Emit<OpCode::Mov>(rcx, -4, r13b);
buffer.Emit<OpCode::Mov>(rcx, 4, r13b);
buffer.Emit<OpCode::Mov>(rcx, 4, r13w);
buffer.Emit<OpCode::Mov>(rcx, 4, r13d);
buffer.Emit<OpCode::Mov>(rcx, 4, r13);
buffer.Emit<OpCode::MovZX>(cx, r13b);
buffer.Emit<OpCode::MovZX, 2, false, 1, false>(cx, r13, 4);
buffer.Emit<OpCode::MovZX>(ecx, r13b);
buffer.Emit<OpCode::MovZX>(ecx, r13w);
buffer.Emit<OpCode::MovZX, 4, false, 1, false>(ecx, r13, 4);
buffer.Emit<OpCode::MovZX, 4, false, 2, false>(ecx, r13, 4);
buffer.Emit<OpCode::MovZX>(rcx, r13b);
buffer.Emit<OpCode::MovZX>(rcx, r13w);
buffer.Emit<OpCode::MovZX, 8, false, 1, false>(rcx, r13, 4);
buffer.Emit<OpCode::MovZX, 8, false, 2, false>(rcx, r13, 4);
// Source: r13, target: rdx
buffer.EmitImmediate<OpCode::Mov>(dl, static_cast<uint8_t>(1));
buffer.EmitImmediate<OpCode::Mov>(dx, static_cast<uint16_t>(1));
buffer.EmitImmediate<OpCode::Mov>(edx, 1);
buffer.EmitImmediate<OpCode::Mov>(rdx, 1);
buffer.Emit<OpCode::Mov>(dl, r13b);
buffer.Emit<OpCode::Mov>(dx, r13w);
buffer.Emit<OpCode::Mov>(edx, r13d);
buffer.Emit<OpCode::Mov>(rdx, r13);
buffer.Emit<OpCode::Mov>(dl, r13, -4);
buffer.Emit<OpCode::Mov>(dl, r13, 4);
buffer.Emit<OpCode::Mov>(dx, r13, 4);
buffer.Emit<OpCode::Mov>(edx, r13, 4);
buffer.Emit<OpCode::Mov>(rdx, r13, 4);
buffer.Emit<OpCode::Mov>(rdx, -4, r13b);
buffer.Emit<OpCode::Mov>(rdx, 4, r13b);
buffer.Emit<OpCode::Mov>(rdx, 4, r13w);
buffer.Emit<OpCode::Mov>(rdx, 4, r13d);
buffer.Emit<OpCode::Mov>(rdx, 4, r13);
buffer.Emit<OpCode::MovZX>(dx, r13b);
buffer.Emit<OpCode::MovZX, 2, false, 1, false>(dx, r13, 4);
buffer.Emit<OpCode::MovZX>(edx, r13b);
buffer.Emit<OpCode::MovZX>(edx, r13w);
buffer.Emit<OpCode::MovZX, 4, false, 1, false>(edx, r13, 4);
buffer.Emit<OpCode::MovZX, 4, false, 2, false>(edx, r13, 4);
buffer.Emit<OpCode::MovZX>(rdx, r13b);
buffer.Emit<OpCode::MovZX>(rdx, r13w);
buffer.Emit<OpCode::MovZX, 8, false, 1, false>(rdx, r13, 4);
buffer.Emit<OpCode::MovZX, 8, false, 2, false>(rdx, r13, 4);
// Source: r13, target: rbx
buffer.EmitImmediate<OpCode::Mov>(bl, static_cast<uint8_t>(1));
buffer.EmitImmediate<OpCode::Mov>(bx, static_cast<uint16_t>(1));
buffer.EmitImmediate<OpCode::Mov>(ebx, 1);
buffer.EmitImmediate<OpCode::Mov>(rbx, 1);
buffer.Emit<OpCode::Mov>(bl, r13b);
buffer.Emit<OpCode::Mov>(bx, r13w);
buffer.Emit<OpCode::Mov>(ebx, r13d);
buffer.Emit<OpCode::Mov>(rbx, r13);
buffer.Emit<OpCode::Mov>(bl, r13, -4);
buffer.Emit<OpCode::Mov>(bl, r13, 4);
buffer.Emit<OpCode::Mov>(bx, r13, 4);
buffer.Emit<OpCode::Mov>(ebx, r13, 4);
buffer.Emit<OpCode::Mov>(rbx, r13, 4);
buffer.Emit<OpCode::Mov>(rbx, -4, r13b);
buffer.Emit<OpCode::Mov>(rbx, 4, r13b);
buffer.Emit<OpCode::Mov>(rbx, 4, r13w);
buffer.Emit<OpCode::Mov>(rbx, 4, r13d);
buffer.Emit<OpCode::Mov>(rbx, 4, r13);
buffer.Emit<OpCode::MovZX>(bx, r13b);
buffer.Emit<OpCode::MovZX, 2, false, 1, false>(bx, r13, 4);
buffer.Emit<OpCode::MovZX>(ebx, r13b);
buffer.Emit<OpCode::MovZX>(ebx, r13w);
buffer.Emit<OpCode::MovZX, 4, false, 1, false>(ebx, r13, 4);
buffer.Emit<OpCode::MovZX, 4, false, 2, false>(ebx, r13, 4);
buffer.Emit<OpCode::MovZX>(rbx, r13b);
buffer.Emit<OpCode::MovZX>(rbx, r13w);
buffer.Emit<OpCode::MovZX, 8, false, 1, false>(rbx, r13, 4);
buffer.Emit<OpCode::MovZX, 8, false, 2, false>(rbx, r13, 4);
// Source: r13, target: rsp
buffer.EmitImmediate<OpCode::Mov>(spl, static_cast<uint8_t>(1));
buffer.EmitImmediate<OpCode::Mov>(sp, static_cast<uint16_t>(1));
buffer.EmitImmediate<OpCode::Mov>(esp, 1);
buffer.EmitImmediate<OpCode::Mov>(rsp, 1);
buffer.Emit<OpCode::Mov>(spl, r13b);
buffer.Emit<OpCode::Mov>(sp, r13w);
buffer.Emit<OpCode::Mov>(esp, r13d);
buffer.Emit<OpCode::Mov>(rsp, r13);
buffer.Emit<OpCode::Mov>(spl, r13, -4);
buffer.Emit<OpCode::Mov>(spl, r13, 4);
buffer.Emit<OpCode::Mov>(sp, r13, 4);
buffer.Emit<OpCode::Mov>(esp, r13, 4);
buffer.Emit<OpCode::Mov>(rsp, r13, 4);
buffer.Emit<OpCode::Mov>(rsp, -4, r13b);
buffer.Emit<OpCode::Mov>(rsp, 4, r13b);
buffer.Emit<OpCode::Mov>(rsp, 4, r13w);
buffer.Emit<OpCode::Mov>(rsp, 4, r13d);
buffer.Emit<OpCode::Mov>(rsp, 4, r13);
buffer.Emit<OpCode::MovZX>(sp, r13b);
buffer.Emit<OpCode::MovZX, 2, false, 1, false>(sp, r13, 4);
buffer.Emit<OpCode::MovZX>(esp, r13b);
buffer.Emit<OpCode::MovZX>(esp, r13w);
buffer.Emit<OpCode::MovZX, 4, false, 1, false>(esp, r13, 4);
buffer.Emit<OpCode::MovZX, 4, false, 2, false>(esp, r13, 4);
buffer.Emit<OpCode::MovZX>(rsp, r13b);
buffer.Emit<OpCode::MovZX>(rsp, r13w);
buffer.Emit<OpCode::MovZX, 8, false, 1, false>(rsp, r13, 4);
buffer.Emit<OpCode::MovZX, 8, false, 2, false>(rsp, r13, 4);
// Source: r13, target: rbp
buffer.EmitImmediate<OpCode::Mov>(bpl, static_cast<uint8_t>(1));
buffer.EmitImmediate<OpCode::Mov>(bp, static_cast<uint16_t>(1));
buffer.EmitImmediate<OpCode::Mov>(ebp, 1);
buffer.EmitImmediate<OpCode::Mov>(rbp, 1);
buffer.Emit<OpCode::Mov>(bpl, r13b);
buffer.Emit<OpCode::Mov>(bp, r13w);
buffer.Emit<OpCode::Mov>(ebp, r13d);
buffer.Emit<OpCode::Mov>(rbp, r13);
buffer.Emit<OpCode::Mov>(bpl, r13, -4);
buffer.Emit<OpCode::Mov>(bpl, r13, 4);
buffer.Emit<OpCode::Mov>(bp, r13, 4);
buffer.Emit<OpCode::Mov>(ebp, r13, 4);
buffer.Emit<OpCode::Mov>(rbp, r13, 4);
buffer.Emit<OpCode::Mov>(rbp, -4, r13b);
buffer.Emit<OpCode::Mov>(rbp, 4, r13b);
buffer.Emit<OpCode::Mov>(rbp, 4, r13w);
buffer.Emit<OpCode::Mov>(rbp, 4, r13d);
buffer.Emit<OpCode::Mov>(rbp, 4, r13);
buffer.Emit<OpCode::MovZX>(bp, r13b);
buffer.Emit<OpCode::MovZX, 2, false, 1, false>(bp, r13, 4);
buffer.Emit<OpCode::MovZX>(ebp, r13b);
buffer.Emit<OpCode::MovZX>(ebp, r13w);
buffer.Emit<OpCode::MovZX, 4, false, 1, false>(ebp, r13, 4);
buffer.Emit<OpCode::MovZX, 4, false, 2, false>(ebp, r13, 4);
buffer.Emit<OpCode::MovZX>(rbp, r13b);
buffer.Emit<OpCode::MovZX>(rbp, r13w);
buffer.Emit<OpCode::MovZX, 8, false, 1, false>(rbp, r13, 4);
buffer.Emit<OpCode::MovZX, 8, false, 2, false>(rbp, r13, 4);
// Source: r13, target: rsi
buffer.EmitImmediate<OpCode::Mov>(dil, static_cast<uint8_t>(1));
buffer.EmitImmediate<OpCode::Mov>(si, static_cast<uint16_t>(1));
buffer.EmitImmediate<OpCode::Mov>(esi, 1);
buffer.EmitImmediate<OpCode::Mov>(rsi, 1);
buffer.Emit<OpCode::Mov>(dil, r13b);
buffer.Emit<OpCode::Mov>(si, r13w);
buffer.Emit<OpCode::Mov>(esi, r13d);
buffer.Emit<OpCode::Mov>(rsi, r13);
buffer.Emit<OpCode::Mov>(dil, r13, -4);
buffer.Emit<OpCode::Mov>(dil, r13, 4);
buffer.Emit<OpCode::Mov>(si, r13, 4);
buffer.Emit<OpCode::Mov>(esi, r13, 4);
buffer.Emit<OpCode::Mov>(rsi, r13, 4);
buffer.Emit<OpCode::Mov>(rsi, -4, r13b);
buffer.Emit<OpCode::Mov>(rsi, 4, r13b);
buffer.Emit<OpCode::Mov>(rsi, 4, r13w);
buffer.Emit<OpCode::Mov>(rsi, 4, r13d);
buffer.Emit<OpCode::Mov>(rsi, 4, r13);
buffer.Emit<OpCode::MovZX>(si, r13b);
buffer.Emit<OpCode::MovZX, 2, false, 1, false>(si, r13, 4);
buffer.Emit<OpCode::MovZX>(esi, r13b);
buffer.Emit<OpCode::MovZX>(esi, r13w);
buffer.Emit<OpCode::MovZX, 4, false, 1, false>(esi, r13, 4);
buffer.Emit<OpCode::MovZX, 4, false, 2, false>(esi, r13, 4);
buffer.Emit<OpCode::MovZX>(rsi, r13b);
buffer.Emit<OpCode::MovZX>(rsi, r13w);
buffer.Emit<OpCode::MovZX, 8, false, 1, false>(rsi, r13, 4);
buffer.Emit<OpCode::MovZX, 8, false, 2, false>(rsi, r13, 4);
// Source: r13, target: rdi
buffer.EmitImmediate<OpCode::Mov>(sil, static_cast<uint8_t>(1));
buffer.EmitImmediate<OpCode::Mov>(di, static_cast<uint16_t>(1));
buffer.EmitImmediate<OpCode::Mov>(edi, 1);
buffer.EmitImmediate<OpCode::Mov>(rdi, 1);
buffer.Emit<OpCode::Mov>(sil, r13b);
buffer.Emit<OpCode::Mov>(di, r13w);
buffer.Emit<OpCode::Mov>(edi, r13d);
buffer.Emit<OpCode::Mov>(rdi, r13);
buffer.Emit<OpCode::Mov>(sil, r13, -4);
buffer.Emit<OpCode::Mov>(sil, r13, 4);
buffer.Emit<OpCode::Mov>(di, r13, 4);
buffer.Emit<OpCode::Mov>(edi, r13, 4);
buffer.Emit<OpCode::Mov>(rdi, r13, 4);
buffer.Emit<OpCode::Mov>(rdi, -4, r13b);
buffer.Emit<OpCode::Mov>(rdi, 4, r13b);
buffer.Emit<OpCode::Mov>(rdi, 4, r13w);
buffer.Emit<OpCode::Mov>(rdi, 4, r13d);
buffer.Emit<OpCode::Mov>(rdi, 4, r13);
buffer.Emit<OpCode::MovZX>(di, r13b);
buffer.Emit<OpCode::MovZX, 2, false, 1, false>(di, r13, 4);
buffer.Emit<OpCode::MovZX>(edi, r13b);
buffer.Emit<OpCode::MovZX>(edi, r13w);
buffer.Emit<OpCode::MovZX, 4, false, 1, false>(edi, r13, 4);
buffer.Emit<OpCode::MovZX, 4, false, 2, false>(edi, r13, 4);
buffer.Emit<OpCode::MovZX>(rdi, r13b);
buffer.Emit<OpCode::MovZX>(rdi, r13w);
buffer.Emit<OpCode::MovZX, 8, false, 1, false>(rdi, r13, 4);
buffer.Emit<OpCode::MovZX, 8, false, 2, false>(rdi, r13, 4);
// Source: r13, target: r8
buffer.EmitImmediate<OpCode::Mov>(r8b, static_cast<uint8_t>(1));
buffer.EmitImmediate<OpCode::Mov>(r8w, static_cast<uint16_t>(1));
buffer.EmitImmediate<OpCode::Mov>(r8d, 1);
buffer.EmitImmediate<OpCode::Mov>(r8, 1);
buffer.Emit<OpCode::Mov>(r8b, r13b);
buffer.Emit<OpCode::Mov>(r8w, r13w);
buffer.Emit<OpCode::Mov>(r8d, r13d);
buffer.Emit<OpCode::Mov>(r8, r13);
buffer.Emit<OpCode::Mov>(r8b, r13, -4);
buffer.Emit<OpCode::Mov>(r8b, r13, 4);
buffer.Emit<OpCode::Mov>(r8w, r13, 4);
buffer.Emit<OpCode::Mov>(r8d, r13, 4);
buffer.Emit<OpCode::Mov>(r8, r13, 4);
buffer.Emit<OpCode::Mov>(r8, -4, r13b);
buffer.Emit<OpCode::Mov>(r8, 4, r13b);
buffer.Emit<OpCode::Mov>(r8, 4, r13w);
buffer.Emit<OpCode::Mov>(r8, 4, r13d);
buffer.Emit<OpCode::Mov>(r8, 4, r13);
buffer.Emit<OpCode::MovZX>(r8w, r13b);
buffer.Emit<OpCode::MovZX, 2, false, 1, false>(r8w, r13, 4);
buffer.Emit<OpCode::MovZX>(r8d, r13b);
buffer.Emit<OpCode::MovZX>(r8d, r13w);
buffer.Emit<OpCode::MovZX, 4, false, 1, false>(r8d, r13, 4);
buffer.Emit<OpCode::MovZX, 4, false, 2, false>(r8d, r13, 4);
buffer.Emit<OpCode::MovZX>(r8, r13b);
buffer.Emit<OpCode::MovZX>(r8, r13w);
buffer.Emit<OpCode::MovZX, 8, false, 1, false>(r8, r13, 4);
buffer.Emit<OpCode::MovZX, 8, false, 2, false>(r8, r13, 4);
// Source: r13, target: r9
buffer.EmitImmediate<OpCode::Mov>(r9b, static_cast<uint8_t>(1));
buffer.EmitImmediate<OpCode::Mov>(r9w, static_cast<uint16_t>(1));
buffer.EmitImmediate<OpCode::Mov>(r9d, 1);
buffer.EmitImmediate<OpCode::Mov>(r9, 1);
buffer.Emit<OpCode::Mov>(r9b, r13b);
buffer.Emit<OpCode::Mov>(r9w, r13w);
buffer.Emit<OpCode::Mov>(r9d, r13d);
buffer.Emit<OpCode::Mov>(r9, r13);
buffer.Emit<OpCode::Mov>(r9b, r13, -4);
buffer.Emit<OpCode::Mov>(r9b, r13, 4);
buffer.Emit<OpCode::Mov>(r9w, r13, 4);
buffer.Emit<OpCode::Mov>(r9d, r13, 4);
buffer.Emit<OpCode::Mov>(r9, r13, 4);
buffer.Emit<OpCode::Mov>(r9, -4, r13b);
buffer.Emit<OpCode::Mov>(r9, 4, r13b);
buffer.Emit<OpCode::Mov>(r9, 4, r13w);
buffer.Emit<OpCode::Mov>(r9, 4, r13d);
buffer.Emit<OpCode::Mov>(r9, 4, r13);
buffer.Emit<OpCode::MovZX>(r9w, r13b);
buffer.Emit<OpCode::MovZX, 2, false, 1, false>(r9w, r13, 4);
buffer.Emit<OpCode::MovZX>(r9d, r13b);
buffer.Emit<OpCode::MovZX>(r9d, r13w);
buffer.Emit<OpCode::MovZX, 4, false, 1, false>(r9d, r13, 4);
buffer.Emit<OpCode::MovZX, 4, false, 2, false>(r9d, r13, 4);
buffer.Emit<OpCode::MovZX>(r9, r13b);
buffer.Emit<OpCode::MovZX>(r9, r13w);
buffer.Emit<OpCode::MovZX, 8, false, 1, false>(r9, r13, 4);
buffer.Emit<OpCode::MovZX, 8, false, 2, false>(r9, r13, 4);
// Source: r13, target: r10
buffer.EmitImmediate<OpCode::Mov>(r10b, static_cast<uint8_t>(1));
buffer.EmitImmediate<OpCode::Mov>(r10w, static_cast<uint16_t>(1));
buffer.EmitImmediate<OpCode::Mov>(r10d, 1);
buffer.EmitImmediate<OpCode::Mov>(r10, 1);
buffer.Emit<OpCode::Mov>(r10b, r13b);
buffer.Emit<OpCode::Mov>(r10w, r13w);
buffer.Emit<OpCode::Mov>(r10d, r13d);
buffer.Emit<OpCode::Mov>(r10, r13);
buffer.Emit<OpCode::Mov>(r10b, r13, -4);
buffer.Emit<OpCode::Mov>(r10b, r13, 4);
buffer.Emit<OpCode::Mov>(r10w, r13, 4);
buffer.Emit<OpCode::Mov>(r10d, r13, 4);
buffer.Emit<OpCode::Mov>(r10, r13, 4);
buffer.Emit<OpCode::Mov>(r10, -4, r13b);
buffer.Emit<OpCode::Mov>(r10, 4, r13b);
buffer.Emit<OpCode::Mov>(r10, 4, r13w);
buffer.Emit<OpCode::Mov>(r10, 4, r13d);
buffer.Emit<OpCode::Mov>(r10, 4, r13);
buffer.Emit<OpCode::MovZX>(r10w, r13b);
buffer.Emit<OpCode::MovZX, 2, false, 1, false>(r10w, r13, 4);
buffer.Emit<OpCode::MovZX>(r10d, r13b);
buffer.Emit<OpCode::MovZX>(r10d, r13w);
buffer.Emit<OpCode::MovZX, 4, false, 1, false>(r10d, r13, 4);
buffer.Emit<OpCode::MovZX, 4, false, 2, false>(r10d, r13, 4);
buffer.Emit<OpCode::MovZX>(r10, r13b);
buffer.Emit<OpCode::MovZX>(r10, r13w);
buffer.Emit<OpCode::MovZX, 8, false, 1, false>(r10, r13, 4);
buffer.Emit<OpCode::MovZX, 8, false, 2, false>(r10, r13, 4);
// Source: r13, target: r11
buffer.EmitImmediate<OpCode::Mov>(r11b, static_cast<uint8_t>(1));
buffer.EmitImmediate<OpCode::Mov>(r11w, static_cast<uint16_t>(1));
buffer.EmitImmediate<OpCode::Mov>(r11d, 1);
buffer.EmitImmediate<OpCode::Mov>(r11, 1);
buffer.Emit<OpCode::Mov>(r11b, r13b);
buffer.Emit<OpCode::Mov>(r11w, r13w);
buffer.Emit<OpCode::Mov>(r11d, r13d);
buffer.Emit<OpCode::Mov>(r11, r13);
buffer.Emit<OpCode::Mov>(r11b, r13, -4);
buffer.Emit<OpCode::Mov>(r11b, r13, 4);
buffer.Emit<OpCode::Mov>(r11w, r13, 4);
buffer.Emit<OpCode::Mov>(r11d, r13, 4);
buffer.Emit<OpCode::Mov>(r11, r13, 4);
buffer.Emit<OpCode::Mov>(r11, -4, r13b);
buffer.Emit<OpCode::Mov>(r11, 4, r13b);
buffer.Emit<OpCode::Mov>(r11, 4, r13w);
buffer.Emit<OpCode::Mov>(r11, 4, r13d);
buffer.Emit<OpCode::Mov>(r11, 4, r13);
buffer.Emit<OpCode::MovZX>(r11w, r13b);
buffer.Emit<OpCode::MovZX, 2, false, 1, false>(r11w, r13, 4);
buffer.Emit<OpCode::MovZX>(r11d, r13b);
buffer.Emit<OpCode::MovZX>(r11d, r13w);
buffer.Emit<OpCode::MovZX, 4, false, 1, false>(r11d, r13, 4);
buffer.Emit<OpCode::MovZX, 4, false, 2, false>(r11d, r13, 4);
buffer.Emit<OpCode::MovZX>(r11, r13b);
buffer.Emit<OpCode::MovZX>(r11, r13w);
buffer.Emit<OpCode::MovZX, 8, false, 1, false>(r11, r13, 4);
buffer.Emit<OpCode::MovZX, 8, false, 2, false>(r11, r13, 4);
// Source: r13, target: r12
buffer.EmitImmediate<OpCode::Mov>(r12b, static_cast<uint8_t>(1));
buffer.EmitImmediate<OpCode::Mov>(r12w, static_cast<uint16_t>(1));
buffer.EmitImmediate<OpCode::Mov>(r12d, 1);
buffer.EmitImmediate<OpCode::Mov>(r12, 1);
buffer.Emit<OpCode::Mov>(r12b, r13b);
buffer.Emit<OpCode::Mov>(r12w, r13w);
buffer.Emit<OpCode::Mov>(r12d, r13d);
buffer.Emit<OpCode::Mov>(r12, r13);
buffer.Emit<OpCode::Mov>(r12b, r13, -4);
buffer.Emit<OpCode::Mov>(r12b, r13, 4);
buffer.Emit<OpCode::Mov>(r12w, r13, 4);
buffer.Emit<OpCode::Mov>(r12d, r13, 4);
buffer.Emit<OpCode::Mov>(r12, r13, 4);
buffer.Emit<OpCode::Mov>(r12, -4, r13b);
buffer.Emit<OpCode::Mov>(r12, 4, r13b);
buffer.Emit<OpCode::Mov>(r12, 4, r13w);
buffer.Emit<OpCode::Mov>(r12, 4, r13d);
buffer.Emit<OpCode::Mov>(r12, 4, r13);
buffer.Emit<OpCode::MovZX>(r12w, r13b);
buffer.Emit<OpCode::MovZX, 2, false, 1, false>(r12w, r13, 4);
buffer.Emit<OpCode::MovZX>(r12d, r13b);
buffer.Emit<OpCode::MovZX>(r12d, r13w);
buffer.Emit<OpCode::MovZX, 4, false, 1, false>(r12d, r13, 4);
buffer.Emit<OpCode::MovZX, 4, false, 2, false>(r12d, r13, 4);
buffer.Emit<OpCode::MovZX>(r12, r13b);
buffer.Emit<OpCode::MovZX>(r12, r13w);
buffer.Emit<OpCode::MovZX, 8, false, 1, false>(r12, r13, 4);
buffer.Emit<OpCode::MovZX, 8, false, 2, false>(r12, r13, 4);
// Source: r13, target: r13
buffer.EmitImmediate<OpCode::Mov>(r13b, static_cast<uint8_t>(1));
buffer.EmitImmediate<OpCode::Mov>(r13w, static_cast<uint16_t>(1));
buffer.EmitImmediate<OpCode::Mov>(r13d, 1);
buffer.EmitImmediate<OpCode::Mov>(r13, 1);
buffer.Emit<OpCode::Mov>(r13b, r13b);
buffer.Emit<OpCode::Mov>(r13w, r13w);
buffer.Emit<OpCode::Mov>(r13d, r13d);
buffer.Emit<OpCode::Mov>(r13, r13);
buffer.Emit<OpCode::Mov>(r13b, r13, -4);
buffer.Emit<OpCode::Mov>(r13b, r13, 4);
buffer.Emit<OpCode::Mov>(r13w, r13, 4);
buffer.Emit<OpCode::Mov>(r13d, r13, 4);
buffer.Emit<OpCode::Mov>(r13, r13, 4);
buffer.Emit<OpCode::Mov>(r13, -4, r13b);
buffer.Emit<OpCode::Mov>(r13, 4, r13b);
buffer.Emit<OpCode::Mov>(r13, 4, r13w);
buffer.Emit<OpCode::Mov>(r13, 4, r13d);
buffer.Emit<OpCode::Mov>(r13, 4, r13);
buffer.Emit<OpCode::MovZX>(r13w, r13b);
buffer.Emit<OpCode::MovZX, 2, false, 1, false>(r13w, r13, 4);
buffer.Emit<OpCode::MovZX>(r13d, r13b);
buffer.Emit<OpCode::MovZX>(r13d, r13w);
buffer.Emit<OpCode::MovZX, 4, false, 1, false>(r13d, r13, 4);
buffer.Emit<OpCode::MovZX, 4, false, 2, false>(r13d, r13, 4);
buffer.Emit<OpCode::MovZX>(r13, r13b);
buffer.Emit<OpCode::MovZX>(r13, r13w);
buffer.Emit<OpCode::MovZX, 8, false, 1, false>(r13, r13, 4);
buffer.Emit<OpCode::MovZX, 8, false, 2, false>(r13, r13, 4);
// Source: r13, target: r14
buffer.EmitImmediate<OpCode::Mov>(r14b, static_cast<uint8_t>(1));
buffer.EmitImmediate<OpCode::Mov>(r14w, static_cast<uint16_t>(1));
buffer.EmitImmediate<OpCode::Mov>(r14d, 1);
buffer.EmitImmediate<OpCode::Mov>(r14, 1);
buffer.Emit<OpCode::Mov>(r14b, r13b);
buffer.Emit<OpCode::Mov>(r14w, r13w);
buffer.Emit<OpCode::Mov>(r14d, r13d);
buffer.Emit<OpCode::Mov>(r14, r13);
buffer.Emit<OpCode::Mov>(r14b, r13, -4);
buffer.Emit<OpCode::Mov>(r14b, r13, 4);
buffer.Emit<OpCode::Mov>(r14w, r13, 4);
buffer.Emit<OpCode::Mov>(r14d, r13, 4);
buffer.Emit<OpCode::Mov>(r14, r13, 4);
buffer.Emit<OpCode::Mov>(r14, -4, r13b);
buffer.Emit<OpCode::Mov>(r14, 4, r13b);
buffer.Emit<OpCode::Mov>(r14, 4, r13w);
buffer.Emit<OpCode::Mov>(r14, 4, r13d);
buffer.Emit<OpCode::Mov>(r14, 4, r13);
buffer.Emit<OpCode::MovZX>(r14w, r13b);
buffer.Emit<OpCode::MovZX, 2, false, 1, false>(r14w, r13, 4);
buffer.Emit<OpCode::MovZX>(r14d, r13b);
buffer.Emit<OpCode::MovZX>(r14d, r13w);
buffer.Emit<OpCode::MovZX, 4, false, 1, false>(r14d, r13, 4);
buffer.Emit<OpCode::MovZX, 4, false, 2, false>(r14d, r13, 4);
buffer.Emit<OpCode::MovZX>(r14, r13b);
buffer.Emit<OpCode::MovZX>(r14, r13w);
buffer.Emit<OpCode::MovZX, 8, false, 1, false>(r14, r13, 4);
buffer.Emit<OpCode::MovZX, 8, false, 2, false>(r14, r13, 4);
// Source: r13, target: r15
buffer.EmitImmediate<OpCode::Mov>(r15b, static_cast<uint8_t>(1));
buffer.EmitImmediate<OpCode::Mov>(r15w, static_cast<uint16_t>(1));
buffer.EmitImmediate<OpCode::Mov>(r15d, 1);
buffer.EmitImmediate<OpCode::Mov>(r15, 1);
buffer.Emit<OpCode::Mov>(r15b, r13b);
buffer.Emit<OpCode::Mov>(r15w, r13w);
buffer.Emit<OpCode::Mov>(r15d, r13d);
buffer.Emit<OpCode::Mov>(r15, r13);
buffer.Emit<OpCode::Mov>(r15b, r13, -4);
buffer.Emit<OpCode::Mov>(r15b, r13, 4);
buffer.Emit<OpCode::Mov>(r15w, r13, 4);
buffer.Emit<OpCode::Mov>(r15d, r13, 4);
buffer.Emit<OpCode::Mov>(r15, r13, 4);
buffer.Emit<OpCode::Mov>(r15, -4, r13b);
buffer.Emit<OpCode::Mov>(r15, 4, r13b);
buffer.Emit<OpCode::Mov>(r15, 4, r13w);
buffer.Emit<OpCode::Mov>(r15, 4, r13d);
buffer.Emit<OpCode::Mov>(r15, 4, r13);
buffer.Emit<OpCode::MovZX>(r15w, r13b);
buffer.Emit<OpCode::MovZX, 2, false, 1, false>(r15w, r13, 4);
buffer.Emit<OpCode::MovZX>(r15d, r13b);
buffer.Emit<OpCode::MovZX>(r15d, r13w);
buffer.Emit<OpCode::MovZX, 4, false, 1, false>(r15d, r13, 4);
buffer.Emit<OpCode::MovZX, 4, false, 2, false>(r15d, r13, 4);
buffer.Emit<OpCode::MovZX>(r15, r13b);
buffer.Emit<OpCode::MovZX>(r15, r13w);
buffer.Emit<OpCode::MovZX, 8, false, 1, false>(r15, r13, 4);
buffer.Emit<OpCode::MovZX, 8, false, 2, false>(r15, r13, 4);
// Source: r14, target: rax
buffer.EmitImmediate<OpCode::Mov>(al, static_cast<uint8_t>(1));
buffer.EmitImmediate<OpCode::Mov>(ax, static_cast<uint16_t>(1));
buffer.EmitImmediate<OpCode::Mov>(eax, 1);
buffer.EmitImmediate<OpCode::Mov>(rax, 1);
buffer.Emit<OpCode::Mov>(al, r14b);
buffer.Emit<OpCode::Mov>(ax, r14w);
buffer.Emit<OpCode::Mov>(eax, r14d);
buffer.Emit<OpCode::Mov>(rax, r14);
buffer.Emit<OpCode::Mov>(al, r14, -4);
buffer.Emit<OpCode::Mov>(al, r14, 4);
buffer.Emit<OpCode::Mov>(ax, r14, 4);
buffer.Emit<OpCode::Mov>(eax, r14, 4);
buffer.Emit<OpCode::Mov>(rax, r14, 4);
buffer.Emit<OpCode::Mov>(rax, -4, r14b);
buffer.Emit<OpCode::Mov>(rax, 4, r14b);
buffer.Emit<OpCode::Mov>(rax, 4, r14w);
buffer.Emit<OpCode::Mov>(rax, 4, r14d);
buffer.Emit<OpCode::Mov>(rax, 4, r14);
buffer.Emit<OpCode::MovZX>(ax, r14b);
buffer.Emit<OpCode::MovZX, 2, false, 1, false>(ax, r14, 4);
buffer.Emit<OpCode::MovZX>(eax, r14b);
buffer.Emit<OpCode::MovZX>(eax, r14w);
buffer.Emit<OpCode::MovZX, 4, false, 1, false>(eax, r14, 4);
buffer.Emit<OpCode::MovZX, 4, false, 2, false>(eax, r14, 4);
buffer.Emit<OpCode::MovZX>(rax, r14b);
buffer.Emit<OpCode::MovZX>(rax, r14w);
buffer.Emit<OpCode::MovZX, 8, false, 1, false>(rax, r14, 4);
buffer.Emit<OpCode::MovZX, 8, false, 2, false>(rax, r14, 4);
// Source: r14, target: rcx
buffer.EmitImmediate<OpCode::Mov>(cl, static_cast<uint8_t>(1));
buffer.EmitImmediate<OpCode::Mov>(cx, static_cast<uint16_t>(1));
buffer.EmitImmediate<OpCode::Mov>(ecx, 1);
buffer.EmitImmediate<OpCode::Mov>(rcx, 1);
buffer.Emit<OpCode::Mov>(cl, r14b);
buffer.Emit<OpCode::Mov>(cx, r14w);
buffer.Emit<OpCode::Mov>(ecx, r14d);
buffer.Emit<OpCode::Mov>(rcx, r14);
buffer.Emit<OpCode::Mov>(cl, r14, -4);
buffer.Emit<OpCode::Mov>(cl, r14, 4);
buffer.Emit<OpCode::Mov>(cx, r14, 4);
buffer.Emit<OpCode::Mov>(ecx, r14, 4);
buffer.Emit<OpCode::Mov>(rcx, r14, 4);
buffer.Emit<OpCode::Mov>(rcx, -4, r14b);
buffer.Emit<OpCode::Mov>(rcx, 4, r14b);
buffer.Emit<OpCode::Mov>(rcx, 4, r14w);
buffer.Emit<OpCode::Mov>(rcx, 4, r14d);
buffer.Emit<OpCode::Mov>(rcx, 4, r14);
buffer.Emit<OpCode::MovZX>(cx, r14b);
buffer.Emit<OpCode::MovZX, 2, false, 1, false>(cx, r14, 4);
buffer.Emit<OpCode::MovZX>(ecx, r14b);
buffer.Emit<OpCode::MovZX>(ecx, r14w);
buffer.Emit<OpCode::MovZX, 4, false, 1, false>(ecx, r14, 4);
buffer.Emit<OpCode::MovZX, 4, false, 2, false>(ecx, r14, 4);
buffer.Emit<OpCode::MovZX>(rcx, r14b);
buffer.Emit<OpCode::MovZX>(rcx, r14w);
buffer.Emit<OpCode::MovZX, 8, false, 1, false>(rcx, r14, 4);
buffer.Emit<OpCode::MovZX, 8, false, 2, false>(rcx, r14, 4);
// Source: r14, target: rdx
buffer.EmitImmediate<OpCode::Mov>(dl, static_cast<uint8_t>(1));
buffer.EmitImmediate<OpCode::Mov>(dx, static_cast<uint16_t>(1));
buffer.EmitImmediate<OpCode::Mov>(edx, 1);
buffer.EmitImmediate<OpCode::Mov>(rdx, 1);
buffer.Emit<OpCode::Mov>(dl, r14b);
buffer.Emit<OpCode::Mov>(dx, r14w);
buffer.Emit<OpCode::Mov>(edx, r14d);
buffer.Emit<OpCode::Mov>(rdx, r14);
buffer.Emit<OpCode::Mov>(dl, r14, -4);
buffer.Emit<OpCode::Mov>(dl, r14, 4);
buffer.Emit<OpCode::Mov>(dx, r14, 4);
buffer.Emit<OpCode::Mov>(edx, r14, 4);
buffer.Emit<OpCode::Mov>(rdx, r14, 4);
buffer.Emit<OpCode::Mov>(rdx, -4, r14b);
buffer.Emit<OpCode::Mov>(rdx, 4, r14b);
buffer.Emit<OpCode::Mov>(rdx, 4, r14w);
buffer.Emit<OpCode::Mov>(rdx, 4, r14d);
buffer.Emit<OpCode::Mov>(rdx, 4, r14);
buffer.Emit<OpCode::MovZX>(dx, r14b);
buffer.Emit<OpCode::MovZX, 2, false, 1, false>(dx, r14, 4);
buffer.Emit<OpCode::MovZX>(edx, r14b);
buffer.Emit<OpCode::MovZX>(edx, r14w);
buffer.Emit<OpCode::MovZX, 4, false, 1, false>(edx, r14, 4);
buffer.Emit<OpCode::MovZX, 4, false, 2, false>(edx, r14, 4);
buffer.Emit<OpCode::MovZX>(rdx, r14b);
buffer.Emit<OpCode::MovZX>(rdx, r14w);
buffer.Emit<OpCode::MovZX, 8, false, 1, false>(rdx, r14, 4);
buffer.Emit<OpCode::MovZX, 8, false, 2, false>(rdx, r14, 4);
// Source: r14, target: rbx
buffer.EmitImmediate<OpCode::Mov>(bl, static_cast<uint8_t>(1));
buffer.EmitImmediate<OpCode::Mov>(bx, static_cast<uint16_t>(1));
buffer.EmitImmediate<OpCode::Mov>(ebx, 1);
buffer.EmitImmediate<OpCode::Mov>(rbx, 1);
buffer.Emit<OpCode::Mov>(bl, r14b);
buffer.Emit<OpCode::Mov>(bx, r14w);
buffer.Emit<OpCode::Mov>(ebx, r14d);
buffer.Emit<OpCode::Mov>(rbx, r14);
buffer.Emit<OpCode::Mov>(bl, r14, -4);
buffer.Emit<OpCode::Mov>(bl, r14, 4);
buffer.Emit<OpCode::Mov>(bx, r14, 4);
buffer.Emit<OpCode::Mov>(ebx, r14, 4);
buffer.Emit<OpCode::Mov>(rbx, r14, 4);
buffer.Emit<OpCode::Mov>(rbx, -4, r14b);
buffer.Emit<OpCode::Mov>(rbx, 4, r14b);
buffer.Emit<OpCode::Mov>(rbx, 4, r14w);
buffer.Emit<OpCode::Mov>(rbx, 4, r14d);
buffer.Emit<OpCode::Mov>(rbx, 4, r14);
buffer.Emit<OpCode::MovZX>(bx, r14b);
buffer.Emit<OpCode::MovZX, 2, false, 1, false>(bx, r14, 4);
buffer.Emit<OpCode::MovZX>(ebx, r14b);
buffer.Emit<OpCode::MovZX>(ebx, r14w);
buffer.Emit<OpCode::MovZX, 4, false, 1, false>(ebx, r14, 4);
buffer.Emit<OpCode::MovZX, 4, false, 2, false>(ebx, r14, 4);
buffer.Emit<OpCode::MovZX>(rbx, r14b);
buffer.Emit<OpCode::MovZX>(rbx, r14w);
buffer.Emit<OpCode::MovZX, 8, false, 1, false>(rbx, r14, 4);
buffer.Emit<OpCode::MovZX, 8, false, 2, false>(rbx, r14, 4);
// Source: r14, target: rsp
buffer.EmitImmediate<OpCode::Mov>(spl, static_cast<uint8_t>(1));
buffer.EmitImmediate<OpCode::Mov>(sp, static_cast<uint16_t>(1));
buffer.EmitImmediate<OpCode::Mov>(esp, 1);
buffer.EmitImmediate<OpCode::Mov>(rsp, 1);
buffer.Emit<OpCode::Mov>(spl, r14b);
buffer.Emit<OpCode::Mov>(sp, r14w);
buffer.Emit<OpCode::Mov>(esp, r14d);
buffer.Emit<OpCode::Mov>(rsp, r14);
buffer.Emit<OpCode::Mov>(spl, r14, -4);
buffer.Emit<OpCode::Mov>(spl, r14, 4);
buffer.Emit<OpCode::Mov>(sp, r14, 4);
buffer.Emit<OpCode::Mov>(esp, r14, 4);
buffer.Emit<OpCode::Mov>(rsp, r14, 4);
buffer.Emit<OpCode::Mov>(rsp, -4, r14b);
buffer.Emit<OpCode::Mov>(rsp, 4, r14b);
buffer.Emit<OpCode::Mov>(rsp, 4, r14w);
buffer.Emit<OpCode::Mov>(rsp, 4, r14d);
buffer.Emit<OpCode::Mov>(rsp, 4, r14);
buffer.Emit<OpCode::MovZX>(sp, r14b);
buffer.Emit<OpCode::MovZX, 2, false, 1, false>(sp, r14, 4);
buffer.Emit<OpCode::MovZX>(esp, r14b);
buffer.Emit<OpCode::MovZX>(esp, r14w);
buffer.Emit<OpCode::MovZX, 4, false, 1, false>(esp, r14, 4);
buffer.Emit<OpCode::MovZX, 4, false, 2, false>(esp, r14, 4);
buffer.Emit<OpCode::MovZX>(rsp, r14b);
buffer.Emit<OpCode::MovZX>(rsp, r14w);
buffer.Emit<OpCode::MovZX, 8, false, 1, false>(rsp, r14, 4);
buffer.Emit<OpCode::MovZX, 8, false, 2, false>(rsp, r14, 4);
// Source: r14, target: rbp
buffer.EmitImmediate<OpCode::Mov>(bpl, static_cast<uint8_t>(1));
buffer.EmitImmediate<OpCode::Mov>(bp, static_cast<uint16_t>(1));
buffer.EmitImmediate<OpCode::Mov>(ebp, 1);
buffer.EmitImmediate<OpCode::Mov>(rbp, 1);
buffer.Emit<OpCode::Mov>(bpl, r14b);
buffer.Emit<OpCode::Mov>(bp, r14w);
buffer.Emit<OpCode::Mov>(ebp, r14d);
buffer.Emit<OpCode::Mov>(rbp, r14);
buffer.Emit<OpCode::Mov>(bpl, r14, -4);
buffer.Emit<OpCode::Mov>(bpl, r14, 4);
buffer.Emit<OpCode::Mov>(bp, r14, 4);
buffer.Emit<OpCode::Mov>(ebp, r14, 4);
buffer.Emit<OpCode::Mov>(rbp, r14, 4);
buffer.Emit<OpCode::Mov>(rbp, -4, r14b);
buffer.Emit<OpCode::Mov>(rbp, 4, r14b);
buffer.Emit<OpCode::Mov>(rbp, 4, r14w);
buffer.Emit<OpCode::Mov>(rbp, 4, r14d);
buffer.Emit<OpCode::Mov>(rbp, 4, r14);
buffer.Emit<OpCode::MovZX>(bp, r14b);
buffer.Emit<OpCode::MovZX, 2, false, 1, false>(bp, r14, 4);
buffer.Emit<OpCode::MovZX>(ebp, r14b);
buffer.Emit<OpCode::MovZX>(ebp, r14w);
buffer.Emit<OpCode::MovZX, 4, false, 1, false>(ebp, r14, 4);
buffer.Emit<OpCode::MovZX, 4, false, 2, false>(ebp, r14, 4);
buffer.Emit<OpCode::MovZX>(rbp, r14b);
buffer.Emit<OpCode::MovZX>(rbp, r14w);
buffer.Emit<OpCode::MovZX, 8, false, 1, false>(rbp, r14, 4);
buffer.Emit<OpCode::MovZX, 8, false, 2, false>(rbp, r14, 4);
// Source: r14, target: rsi
buffer.EmitImmediate<OpCode::Mov>(dil, static_cast<uint8_t>(1));
buffer.EmitImmediate<OpCode::Mov>(si, static_cast<uint16_t>(1));
buffer.EmitImmediate<OpCode::Mov>(esi, 1);
buffer.EmitImmediate<OpCode::Mov>(rsi, 1);
buffer.Emit<OpCode::Mov>(dil, r14b);
buffer.Emit<OpCode::Mov>(si, r14w);
buffer.Emit<OpCode::Mov>(esi, r14d);
buffer.Emit<OpCode::Mov>(rsi, r14);
buffer.Emit<OpCode::Mov>(dil, r14, -4);
buffer.Emit<OpCode::Mov>(dil, r14, 4);
buffer.Emit<OpCode::Mov>(si, r14, 4);
buffer.Emit<OpCode::Mov>(esi, r14, 4);
buffer.Emit<OpCode::Mov>(rsi, r14, 4);
buffer.Emit<OpCode::Mov>(rsi, -4, r14b);
buffer.Emit<OpCode::Mov>(rsi, 4, r14b);
buffer.Emit<OpCode::Mov>(rsi, 4, r14w);
buffer.Emit<OpCode::Mov>(rsi, 4, r14d);
buffer.Emit<OpCode::Mov>(rsi, 4, r14);
buffer.Emit<OpCode::MovZX>(si, r14b);
buffer.Emit<OpCode::MovZX, 2, false, 1, false>(si, r14, 4);
buffer.Emit<OpCode::MovZX>(esi, r14b);
buffer.Emit<OpCode::MovZX>(esi, r14w);
buffer.Emit<OpCode::MovZX, 4, false, 1, false>(esi, r14, 4);
buffer.Emit<OpCode::MovZX, 4, false, 2, false>(esi, r14, 4);
buffer.Emit<OpCode::MovZX>(rsi, r14b);
buffer.Emit<OpCode::MovZX>(rsi, r14w);
buffer.Emit<OpCode::MovZX, 8, false, 1, false>(rsi, r14, 4);
buffer.Emit<OpCode::MovZX, 8, false, 2, false>(rsi, r14, 4);
// Source: r14, target: rdi
buffer.EmitImmediate<OpCode::Mov>(sil, static_cast<uint8_t>(1));
buffer.EmitImmediate<OpCode::Mov>(di, static_cast<uint16_t>(1));
buffer.EmitImmediate<OpCode::Mov>(edi, 1);
buffer.EmitImmediate<OpCode::Mov>(rdi, 1);
buffer.Emit<OpCode::Mov>(sil, r14b);
buffer.Emit<OpCode::Mov>(di, r14w);
buffer.Emit<OpCode::Mov>(edi, r14d);
buffer.Emit<OpCode::Mov>(rdi, r14);
buffer.Emit<OpCode::Mov>(sil, r14, -4);
buffer.Emit<OpCode::Mov>(sil, r14, 4);
buffer.Emit<OpCode::Mov>(di, r14, 4);
buffer.Emit<OpCode::Mov>(edi, r14, 4);
buffer.Emit<OpCode::Mov>(rdi, r14, 4);
buffer.Emit<OpCode::Mov>(rdi, -4, r14b);
buffer.Emit<OpCode::Mov>(rdi, 4, r14b);
buffer.Emit<OpCode::Mov>(rdi, 4, r14w);
buffer.Emit<OpCode::Mov>(rdi, 4, r14d);
buffer.Emit<OpCode::Mov>(rdi, 4, r14);
buffer.Emit<OpCode::MovZX>(di, r14b);
buffer.Emit<OpCode::MovZX, 2, false, 1, false>(di, r14, 4);
buffer.Emit<OpCode::MovZX>(edi, r14b);
buffer.Emit<OpCode::MovZX>(edi, r14w);
buffer.Emit<OpCode::MovZX, 4, false, 1, false>(edi, r14, 4);
buffer.Emit<OpCode::MovZX, 4, false, 2, false>(edi, r14, 4);
buffer.Emit<OpCode::MovZX>(rdi, r14b);
buffer.Emit<OpCode::MovZX>(rdi, r14w);
buffer.Emit<OpCode::MovZX, 8, false, 1, false>(rdi, r14, 4);
buffer.Emit<OpCode::MovZX, 8, false, 2, false>(rdi, r14, 4);
// Source: r14, target: r8
buffer.EmitImmediate<OpCode::Mov>(r8b, static_cast<uint8_t>(1));
buffer.EmitImmediate<OpCode::Mov>(r8w, static_cast<uint16_t>(1));
buffer.EmitImmediate<OpCode::Mov>(r8d, 1);
buffer.EmitImmediate<OpCode::Mov>(r8, 1);
buffer.Emit<OpCode::Mov>(r8b, r14b);
buffer.Emit<OpCode::Mov>(r8w, r14w);
buffer.Emit<OpCode::Mov>(r8d, r14d);
buffer.Emit<OpCode::Mov>(r8, r14);
buffer.Emit<OpCode::Mov>(r8b, r14, -4);
buffer.Emit<OpCode::Mov>(r8b, r14, 4);
buffer.Emit<OpCode::Mov>(r8w, r14, 4);
buffer.Emit<OpCode::Mov>(r8d, r14, 4);
buffer.Emit<OpCode::Mov>(r8, r14, 4);
buffer.Emit<OpCode::Mov>(r8, -4, r14b);
buffer.Emit<OpCode::Mov>(r8, 4, r14b);
buffer.Emit<OpCode::Mov>(r8, 4, r14w);
buffer.Emit<OpCode::Mov>(r8, 4, r14d);
buffer.Emit<OpCode::Mov>(r8, 4, r14);
buffer.Emit<OpCode::MovZX>(r8w, r14b);
buffer.Emit<OpCode::MovZX, 2, false, 1, false>(r8w, r14, 4);
buffer.Emit<OpCode::MovZX>(r8d, r14b);
buffer.Emit<OpCode::MovZX>(r8d, r14w);
buffer.Emit<OpCode::MovZX, 4, false, 1, false>(r8d, r14, 4);
buffer.Emit<OpCode::MovZX, 4, false, 2, false>(r8d, r14, 4);
buffer.Emit<OpCode::MovZX>(r8, r14b);
buffer.Emit<OpCode::MovZX>(r8, r14w);
buffer.Emit<OpCode::MovZX, 8, false, 1, false>(r8, r14, 4);
buffer.Emit<OpCode::MovZX, 8, false, 2, false>(r8, r14, 4);
// Source: r14, target: r9
buffer.EmitImmediate<OpCode::Mov>(r9b, static_cast<uint8_t>(1));
buffer.EmitImmediate<OpCode::Mov>(r9w, static_cast<uint16_t>(1));
buffer.EmitImmediate<OpCode::Mov>(r9d, 1);
buffer.EmitImmediate<OpCode::Mov>(r9, 1);
buffer.Emit<OpCode::Mov>(r9b, r14b);
buffer.Emit<OpCode::Mov>(r9w, r14w);
buffer.Emit<OpCode::Mov>(r9d, r14d);
buffer.Emit<OpCode::Mov>(r9, r14);
buffer.Emit<OpCode::Mov>(r9b, r14, -4);
buffer.Emit<OpCode::Mov>(r9b, r14, 4);
buffer.Emit<OpCode::Mov>(r9w, r14, 4);
buffer.Emit<OpCode::Mov>(r9d, r14, 4);
buffer.Emit<OpCode::Mov>(r9, r14, 4);
buffer.Emit<OpCode::Mov>(r9, -4, r14b);
buffer.Emit<OpCode::Mov>(r9, 4, r14b);
buffer.Emit<OpCode::Mov>(r9, 4, r14w);
buffer.Emit<OpCode::Mov>(r9, 4, r14d);
buffer.Emit<OpCode::Mov>(r9, 4, r14);
buffer.Emit<OpCode::MovZX>(r9w, r14b);
buffer.Emit<OpCode::MovZX, 2, false, 1, false>(r9w, r14, 4);
buffer.Emit<OpCode::MovZX>(r9d, r14b);
buffer.Emit<OpCode::MovZX>(r9d, r14w);
buffer.Emit<OpCode::MovZX, 4, false, 1, false>(r9d, r14, 4);
buffer.Emit<OpCode::MovZX, 4, false, 2, false>(r9d, r14, 4);
buffer.Emit<OpCode::MovZX>(r9, r14b);
buffer.Emit<OpCode::MovZX>(r9, r14w);
buffer.Emit<OpCode::MovZX, 8, false, 1, false>(r9, r14, 4);
buffer.Emit<OpCode::MovZX, 8, false, 2, false>(r9, r14, 4);
// Source: r14, target: r10
buffer.EmitImmediate<OpCode::Mov>(r10b, static_cast<uint8_t>(1));
buffer.EmitImmediate<OpCode::Mov>(r10w, static_cast<uint16_t>(1));
buffer.EmitImmediate<OpCode::Mov>(r10d, 1);
buffer.EmitImmediate<OpCode::Mov>(r10, 1);
buffer.Emit<OpCode::Mov>(r10b, r14b);
buffer.Emit<OpCode::Mov>(r10w, r14w);
buffer.Emit<OpCode::Mov>(r10d, r14d);
buffer.Emit<OpCode::Mov>(r10, r14);
buffer.Emit<OpCode::Mov>(r10b, r14, -4);
buffer.Emit<OpCode::Mov>(r10b, r14, 4);
buffer.Emit<OpCode::Mov>(r10w, r14, 4);
buffer.Emit<OpCode::Mov>(r10d, r14, 4);
buffer.Emit<OpCode::Mov>(r10, r14, 4);
buffer.Emit<OpCode::Mov>(r10, -4, r14b);
buffer.Emit<OpCode::Mov>(r10, 4, r14b);
buffer.Emit<OpCode::Mov>(r10, 4, r14w);
buffer.Emit<OpCode::Mov>(r10, 4, r14d);
buffer.Emit<OpCode::Mov>(r10, 4, r14);
buffer.Emit<OpCode::MovZX>(r10w, r14b);
buffer.Emit<OpCode::MovZX, 2, false, 1, false>(r10w, r14, 4);
buffer.Emit<OpCode::MovZX>(r10d, r14b);
buffer.Emit<OpCode::MovZX>(r10d, r14w);
buffer.Emit<OpCode::MovZX, 4, false, 1, false>(r10d, r14, 4);
buffer.Emit<OpCode::MovZX, 4, false, 2, false>(r10d, r14, 4);
buffer.Emit<OpCode::MovZX>(r10, r14b);
buffer.Emit<OpCode::MovZX>(r10, r14w);
buffer.Emit<OpCode::MovZX, 8, false, 1, false>(r10, r14, 4);
buffer.Emit<OpCode::MovZX, 8, false, 2, false>(r10, r14, 4);
// Source: r14, target: r11
buffer.EmitImmediate<OpCode::Mov>(r11b, static_cast<uint8_t>(1));
buffer.EmitImmediate<OpCode::Mov>(r11w, static_cast<uint16_t>(1));
buffer.EmitImmediate<OpCode::Mov>(r11d, 1);
buffer.EmitImmediate<OpCode::Mov>(r11, 1);
buffer.Emit<OpCode::Mov>(r11b, r14b);
buffer.Emit<OpCode::Mov>(r11w, r14w);
buffer.Emit<OpCode::Mov>(r11d, r14d);
buffer.Emit<OpCode::Mov>(r11, r14);
buffer.Emit<OpCode::Mov>(r11b, r14, -4);
buffer.Emit<OpCode::Mov>(r11b, r14, 4);
buffer.Emit<OpCode::Mov>(r11w, r14, 4);
buffer.Emit<OpCode::Mov>(r11d, r14, 4);
buffer.Emit<OpCode::Mov>(r11, r14, 4);
buffer.Emit<OpCode::Mov>(r11, -4, r14b);
buffer.Emit<OpCode::Mov>(r11, 4, r14b);
buffer.Emit<OpCode::Mov>(r11, 4, r14w);
buffer.Emit<OpCode::Mov>(r11, 4, r14d);
buffer.Emit<OpCode::Mov>(r11, 4, r14);
buffer.Emit<OpCode::MovZX>(r11w, r14b);
buffer.Emit<OpCode::MovZX, 2, false, 1, false>(r11w, r14, 4);
buffer.Emit<OpCode::MovZX>(r11d, r14b);
buffer.Emit<OpCode::MovZX>(r11d, r14w);
buffer.Emit<OpCode::MovZX, 4, false, 1, false>(r11d, r14, 4);
buffer.Emit<OpCode::MovZX, 4, false, 2, false>(r11d, r14, 4);
buffer.Emit<OpCode::MovZX>(r11, r14b);
buffer.Emit<OpCode::MovZX>(r11, r14w);
buffer.Emit<OpCode::MovZX, 8, false, 1, false>(r11, r14, 4);
buffer.Emit<OpCode::MovZX, 8, false, 2, false>(r11, r14, 4);
// Source: r14, target: r12
buffer.EmitImmediate<OpCode::Mov>(r12b, static_cast<uint8_t>(1));
buffer.EmitImmediate<OpCode::Mov>(r12w, static_cast<uint16_t>(1));
buffer.EmitImmediate<OpCode::Mov>(r12d, 1);
buffer.EmitImmediate<OpCode::Mov>(r12, 1);
buffer.Emit<OpCode::Mov>(r12b, r14b);
buffer.Emit<OpCode::Mov>(r12w, r14w);
buffer.Emit<OpCode::Mov>(r12d, r14d);
buffer.Emit<OpCode::Mov>(r12, r14);
buffer.Emit<OpCode::Mov>(r12b, r14, -4);
buffer.Emit<OpCode::Mov>(r12b, r14, 4);
buffer.Emit<OpCode::Mov>(r12w, r14, 4);
buffer.Emit<OpCode::Mov>(r12d, r14, 4);
buffer.Emit<OpCode::Mov>(r12, r14, 4);
buffer.Emit<OpCode::Mov>(r12, -4, r14b);
buffer.Emit<OpCode::Mov>(r12, 4, r14b);
buffer.Emit<OpCode::Mov>(r12, 4, r14w);
buffer.Emit<OpCode::Mov>(r12, 4, r14d);
buffer.Emit<OpCode::Mov>(r12, 4, r14);
buffer.Emit<OpCode::MovZX>(r12w, r14b);
buffer.Emit<OpCode::MovZX, 2, false, 1, false>(r12w, r14, 4);
buffer.Emit<OpCode::MovZX>(r12d, r14b);
buffer.Emit<OpCode::MovZX>(r12d, r14w);
buffer.Emit<OpCode::MovZX, 4, false, 1, false>(r12d, r14, 4);
buffer.Emit<OpCode::MovZX, 4, false, 2, false>(r12d, r14, 4);
buffer.Emit<OpCode::MovZX>(r12, r14b);
buffer.Emit<OpCode::MovZX>(r12, r14w);
buffer.Emit<OpCode::MovZX, 8, false, 1, false>(r12, r14, 4);
buffer.Emit<OpCode::MovZX, 8, false, 2, false>(r12, r14, 4);
// Source: r14, target: r13
buffer.EmitImmediate<OpCode::Mov>(r13b, static_cast<uint8_t>(1));
buffer.EmitImmediate<OpCode::Mov>(r13w, static_cast<uint16_t>(1));
buffer.EmitImmediate<OpCode::Mov>(r13d, 1);
buffer.EmitImmediate<OpCode::Mov>(r13, 1);
buffer.Emit<OpCode::Mov>(r13b, r14b);
buffer.Emit<OpCode::Mov>(r13w, r14w);
buffer.Emit<OpCode::Mov>(r13d, r14d);
buffer.Emit<OpCode::Mov>(r13, r14);
buffer.Emit<OpCode::Mov>(r13b, r14, -4);
buffer.Emit<OpCode::Mov>(r13b, r14, 4);
buffer.Emit<OpCode::Mov>(r13w, r14, 4);
buffer.Emit<OpCode::Mov>(r13d, r14, 4);
buffer.Emit<OpCode::Mov>(r13, r14, 4);
buffer.Emit<OpCode::Mov>(r13, -4, r14b);
buffer.Emit<OpCode::Mov>(r13, 4, r14b);
buffer.Emit<OpCode::Mov>(r13, 4, r14w);
buffer.Emit<OpCode::Mov>(r13, 4, r14d);
buffer.Emit<OpCode::Mov>(r13, 4, r14);
buffer.Emit<OpCode::MovZX>(r13w, r14b);
buffer.Emit<OpCode::MovZX, 2, false, 1, false>(r13w, r14, 4);
buffer.Emit<OpCode::MovZX>(r13d, r14b);
buffer.Emit<OpCode::MovZX>(r13d, r14w);
buffer.Emit<OpCode::MovZX, 4, false, 1, false>(r13d, r14, 4);
buffer.Emit<OpCode::MovZX, 4, false, 2, false>(r13d, r14, 4);
buffer.Emit<OpCode::MovZX>(r13, r14b);
buffer.Emit<OpCode::MovZX>(r13, r14w);
buffer.Emit<OpCode::MovZX, 8, false, 1, false>(r13, r14, 4);
buffer.Emit<OpCode::MovZX, 8, false, 2, false>(r13, r14, 4);
// Source: r14, target: r14
buffer.EmitImmediate<OpCode::Mov>(r14b, static_cast<uint8_t>(1));
buffer.EmitImmediate<OpCode::Mov>(r14w, static_cast<uint16_t>(1));
buffer.EmitImmediate<OpCode::Mov>(r14d, 1);
buffer.EmitImmediate<OpCode::Mov>(r14, 1);
buffer.Emit<OpCode::Mov>(r14b, r14b);
buffer.Emit<OpCode::Mov>(r14w, r14w);
buffer.Emit<OpCode::Mov>(r14d, r14d);
buffer.Emit<OpCode::Mov>(r14, r14);
buffer.Emit<OpCode::Mov>(r14b, r14, -4);
buffer.Emit<OpCode::Mov>(r14b, r14, 4);
buffer.Emit<OpCode::Mov>(r14w, r14, 4);
buffer.Emit<OpCode::Mov>(r14d, r14, 4);
buffer.Emit<OpCode::Mov>(r14, r14, 4);
buffer.Emit<OpCode::Mov>(r14, -4, r14b);
buffer.Emit<OpCode::Mov>(r14, 4, r14b);
buffer.Emit<OpCode::Mov>(r14, 4, r14w);
buffer.Emit<OpCode::Mov>(r14, 4, r14d);
buffer.Emit<OpCode::Mov>(r14, 4, r14);
buffer.Emit<OpCode::MovZX>(r14w, r14b);
buffer.Emit<OpCode::MovZX, 2, false, 1, false>(r14w, r14, 4);
buffer.Emit<OpCode::MovZX>(r14d, r14b);
buffer.Emit<OpCode::MovZX>(r14d, r14w);
buffer.Emit<OpCode::MovZX, 4, false, 1, false>(r14d, r14, 4);
buffer.Emit<OpCode::MovZX, 4, false, 2, false>(r14d, r14, 4);
buffer.Emit<OpCode::MovZX>(r14, r14b);
buffer.Emit<OpCode::MovZX>(r14, r14w);
buffer.Emit<OpCode::MovZX, 8, false, 1, false>(r14, r14, 4);
buffer.Emit<OpCode::MovZX, 8, false, 2, false>(r14, r14, 4);
// Source: r14, target: r15
buffer.EmitImmediate<OpCode::Mov>(r15b, static_cast<uint8_t>(1));
buffer.EmitImmediate<OpCode::Mov>(r15w, static_cast<uint16_t>(1));
buffer.EmitImmediate<OpCode::Mov>(r15d, 1);
buffer.EmitImmediate<OpCode::Mov>(r15, 1);
buffer.Emit<OpCode::Mov>(r15b, r14b);
buffer.Emit<OpCode::Mov>(r15w, r14w);
buffer.Emit<OpCode::Mov>(r15d, r14d);
buffer.Emit<OpCode::Mov>(r15, r14);
buffer.Emit<OpCode::Mov>(r15b, r14, -4);
buffer.Emit<OpCode::Mov>(r15b, r14, 4);
buffer.Emit<OpCode::Mov>(r15w, r14, 4);
buffer.Emit<OpCode::Mov>(r15d, r14, 4);
buffer.Emit<OpCode::Mov>(r15, r14, 4);
buffer.Emit<OpCode::Mov>(r15, -4, r14b);
buffer.Emit<OpCode::Mov>(r15, 4, r14b);
buffer.Emit<OpCode::Mov>(r15, 4, r14w);
buffer.Emit<OpCode::Mov>(r15, 4, r14d);
buffer.Emit<OpCode::Mov>(r15, 4, r14);
buffer.Emit<OpCode::MovZX>(r15w, r14b);
buffer.Emit<OpCode::MovZX, 2, false, 1, false>(r15w, r14, 4);
buffer.Emit<OpCode::MovZX>(r15d, r14b);
buffer.Emit<OpCode::MovZX>(r15d, r14w);
buffer.Emit<OpCode::MovZX, 4, false, 1, false>(r15d, r14, 4);
buffer.Emit<OpCode::MovZX, 4, false, 2, false>(r15d, r14, 4);
buffer.Emit<OpCode::MovZX>(r15, r14b);
buffer.Emit<OpCode::MovZX>(r15, r14w);
buffer.Emit<OpCode::MovZX, 8, false, 1, false>(r15, r14, 4);
buffer.Emit<OpCode::MovZX, 8, false, 2, false>(r15, r14, 4);
// Source: r15, target: rax
buffer.EmitImmediate<OpCode::Mov>(al, static_cast<uint8_t>(1));
buffer.EmitImmediate<OpCode::Mov>(ax, static_cast<uint16_t>(1));
buffer.EmitImmediate<OpCode::Mov>(eax, 1);
buffer.EmitImmediate<OpCode::Mov>(rax, 1);
buffer.Emit<OpCode::Mov>(al, r15b);
buffer.Emit<OpCode::Mov>(ax, r15w);
buffer.Emit<OpCode::Mov>(eax, r15d);
buffer.Emit<OpCode::Mov>(rax, r15);
buffer.Emit<OpCode::Mov>(al, r15, -4);
buffer.Emit<OpCode::Mov>(al, r15, 4);
buffer.Emit<OpCode::Mov>(ax, r15, 4);
buffer.Emit<OpCode::Mov>(eax, r15, 4);
buffer.Emit<OpCode::Mov>(rax, r15, 4);
buffer.Emit<OpCode::Mov>(rax, -4, r15b);
buffer.Emit<OpCode::Mov>(rax, 4, r15b);
buffer.Emit<OpCode::Mov>(rax, 4, r15w);
buffer.Emit<OpCode::Mov>(rax, 4, r15d);
buffer.Emit<OpCode::Mov>(rax, 4, r15);
buffer.Emit<OpCode::MovZX>(ax, r15b);
buffer.Emit<OpCode::MovZX, 2, false, 1, false>(ax, r15, 4);
buffer.Emit<OpCode::MovZX>(eax, r15b);
buffer.Emit<OpCode::MovZX>(eax, r15w);
buffer.Emit<OpCode::MovZX, 4, false, 1, false>(eax, r15, 4);
buffer.Emit<OpCode::MovZX, 4, false, 2, false>(eax, r15, 4);
buffer.Emit<OpCode::MovZX>(rax, r15b);
buffer.Emit<OpCode::MovZX>(rax, r15w);
buffer.Emit<OpCode::MovZX, 8, false, 1, false>(rax, r15, 4);
buffer.Emit<OpCode::MovZX, 8, false, 2, false>(rax, r15, 4);
// Source: r15, target: rcx
buffer.EmitImmediate<OpCode::Mov>(cl, static_cast<uint8_t>(1));
buffer.EmitImmediate<OpCode::Mov>(cx, static_cast<uint16_t>(1));
buffer.EmitImmediate<OpCode::Mov>(ecx, 1);
buffer.EmitImmediate<OpCode::Mov>(rcx, 1);
buffer.Emit<OpCode::Mov>(cl, r15b);
buffer.Emit<OpCode::Mov>(cx, r15w);
buffer.Emit<OpCode::Mov>(ecx, r15d);
buffer.Emit<OpCode::Mov>(rcx, r15);
buffer.Emit<OpCode::Mov>(cl, r15, -4);
buffer.Emit<OpCode::Mov>(cl, r15, 4);
buffer.Emit<OpCode::Mov>(cx, r15, 4);
buffer.Emit<OpCode::Mov>(ecx, r15, 4);
buffer.Emit<OpCode::Mov>(rcx, r15, 4);
buffer.Emit<OpCode::Mov>(rcx, -4, r15b);
buffer.Emit<OpCode::Mov>(rcx, 4, r15b);
buffer.Emit<OpCode::Mov>(rcx, 4, r15w);
buffer.Emit<OpCode::Mov>(rcx, 4, r15d);
buffer.Emit<OpCode::Mov>(rcx, 4, r15);
buffer.Emit<OpCode::MovZX>(cx, r15b);
buffer.Emit<OpCode::MovZX, 2, false, 1, false>(cx, r15, 4);
buffer.Emit<OpCode::MovZX>(ecx, r15b);
buffer.Emit<OpCode::MovZX>(ecx, r15w);
buffer.Emit<OpCode::MovZX, 4, false, 1, false>(ecx, r15, 4);
buffer.Emit<OpCode::MovZX, 4, false, 2, false>(ecx, r15, 4);
buffer.Emit<OpCode::MovZX>(rcx, r15b);
buffer.Emit<OpCode::MovZX>(rcx, r15w);
buffer.Emit<OpCode::MovZX, 8, false, 1, false>(rcx, r15, 4);
buffer.Emit<OpCode::MovZX, 8, false, 2, false>(rcx, r15, 4);
// Source: r15, target: rdx
buffer.EmitImmediate<OpCode::Mov>(dl, static_cast<uint8_t>(1));
buffer.EmitImmediate<OpCode::Mov>(dx, static_cast<uint16_t>(1));
buffer.EmitImmediate<OpCode::Mov>(edx, 1);
buffer.EmitImmediate<OpCode::Mov>(rdx, 1);
buffer.Emit<OpCode::Mov>(dl, r15b);
buffer.Emit<OpCode::Mov>(dx, r15w);
buffer.Emit<OpCode::Mov>(edx, r15d);
buffer.Emit<OpCode::Mov>(rdx, r15);
buffer.Emit<OpCode::Mov>(dl, r15, -4);
buffer.Emit<OpCode::Mov>(dl, r15, 4);
buffer.Emit<OpCode::Mov>(dx, r15, 4);
buffer.Emit<OpCode::Mov>(edx, r15, 4);
buffer.Emit<OpCode::Mov>(rdx, r15, 4);
buffer.Emit<OpCode::Mov>(rdx, -4, r15b);
buffer.Emit<OpCode::Mov>(rdx, 4, r15b);
buffer.Emit<OpCode::Mov>(rdx, 4, r15w);
buffer.Emit<OpCode::Mov>(rdx, 4, r15d);
buffer.Emit<OpCode::Mov>(rdx, 4, r15);
buffer.Emit<OpCode::MovZX>(dx, r15b);
buffer.Emit<OpCode::MovZX, 2, false, 1, false>(dx, r15, 4);
buffer.Emit<OpCode::MovZX>(edx, r15b);
buffer.Emit<OpCode::MovZX>(edx, r15w);
buffer.Emit<OpCode::MovZX, 4, false, 1, false>(edx, r15, 4);
buffer.Emit<OpCode::MovZX, 4, false, 2, false>(edx, r15, 4);
buffer.Emit<OpCode::MovZX>(rdx, r15b);
buffer.Emit<OpCode::MovZX>(rdx, r15w);
buffer.Emit<OpCode::MovZX, 8, false, 1, false>(rdx, r15, 4);
buffer.Emit<OpCode::MovZX, 8, false, 2, false>(rdx, r15, 4);
// Source: r15, target: rbx
buffer.EmitImmediate<OpCode::Mov>(bl, static_cast<uint8_t>(1));
buffer.EmitImmediate<OpCode::Mov>(bx, static_cast<uint16_t>(1));
buffer.EmitImmediate<OpCode::Mov>(ebx, 1);
buffer.EmitImmediate<OpCode::Mov>(rbx, 1);
buffer.Emit<OpCode::Mov>(bl, r15b);
buffer.Emit<OpCode::Mov>(bx, r15w);
buffer.Emit<OpCode::Mov>(ebx, r15d);
buffer.Emit<OpCode::Mov>(rbx, r15);
buffer.Emit<OpCode::Mov>(bl, r15, -4);
buffer.Emit<OpCode::Mov>(bl, r15, 4);
buffer.Emit<OpCode::Mov>(bx, r15, 4);
buffer.Emit<OpCode::Mov>(ebx, r15, 4);
buffer.Emit<OpCode::Mov>(rbx, r15, 4);
buffer.Emit<OpCode::Mov>(rbx, -4, r15b);
buffer.Emit<OpCode::Mov>(rbx, 4, r15b);
buffer.Emit<OpCode::Mov>(rbx, 4, r15w);
buffer.Emit<OpCode::Mov>(rbx, 4, r15d);
buffer.Emit<OpCode::Mov>(rbx, 4, r15);
buffer.Emit<OpCode::MovZX>(bx, r15b);
buffer.Emit<OpCode::MovZX, 2, false, 1, false>(bx, r15, 4);
buffer.Emit<OpCode::MovZX>(ebx, r15b);
buffer.Emit<OpCode::MovZX>(ebx, r15w);
buffer.Emit<OpCode::MovZX, 4, false, 1, false>(ebx, r15, 4);
buffer.Emit<OpCode::MovZX, 4, false, 2, false>(ebx, r15, 4);
buffer.Emit<OpCode::MovZX>(rbx, r15b);
buffer.Emit<OpCode::MovZX>(rbx, r15w);
buffer.Emit<OpCode::MovZX, 8, false, 1, false>(rbx, r15, 4);
buffer.Emit<OpCode::MovZX, 8, false, 2, false>(rbx, r15, 4);
// Source: r15, target: rsp
buffer.EmitImmediate<OpCode::Mov>(spl, static_cast<uint8_t>(1));
buffer.EmitImmediate<OpCode::Mov>(sp, static_cast<uint16_t>(1));
buffer.EmitImmediate<OpCode::Mov>(esp, 1);
buffer.EmitImmediate<OpCode::Mov>(rsp, 1);
buffer.Emit<OpCode::Mov>(spl, r15b);
buffer.Emit<OpCode::Mov>(sp, r15w);
buffer.Emit<OpCode::Mov>(esp, r15d);
buffer.Emit<OpCode::Mov>(rsp, r15);
buffer.Emit<OpCode::Mov>(spl, r15, -4);
buffer.Emit<OpCode::Mov>(spl, r15, 4);
buffer.Emit<OpCode::Mov>(sp, r15, 4);
buffer.Emit<OpCode::Mov>(esp, r15, 4);
buffer.Emit<OpCode::Mov>(rsp, r15, 4);
buffer.Emit<OpCode::Mov>(rsp, -4, r15b);
buffer.Emit<OpCode::Mov>(rsp, 4, r15b);
buffer.Emit<OpCode::Mov>(rsp, 4, r15w);
buffer.Emit<OpCode::Mov>(rsp, 4, r15d);
buffer.Emit<OpCode::Mov>(rsp, 4, r15);
buffer.Emit<OpCode::MovZX>(sp, r15b);
buffer.Emit<OpCode::MovZX, 2, false, 1, false>(sp, r15, 4);
buffer.Emit<OpCode::MovZX>(esp, r15b);
buffer.Emit<OpCode::MovZX>(esp, r15w);
buffer.Emit<OpCode::MovZX, 4, false, 1, false>(esp, r15, 4);
buffer.Emit<OpCode::MovZX, 4, false, 2, false>(esp, r15, 4);
buffer.Emit<OpCode::MovZX>(rsp, r15b);
buffer.Emit<OpCode::MovZX>(rsp, r15w);
buffer.Emit<OpCode::MovZX, 8, false, 1, false>(rsp, r15, 4);
buffer.Emit<OpCode::MovZX, 8, false, 2, false>(rsp, r15, 4);
// Source: r15, target: rbp
buffer.EmitImmediate<OpCode::Mov>(bpl, static_cast<uint8_t>(1));
buffer.EmitImmediate<OpCode::Mov>(bp, static_cast<uint16_t>(1));
buffer.EmitImmediate<OpCode::Mov>(ebp, 1);
buffer.EmitImmediate<OpCode::Mov>(rbp, 1);
buffer.Emit<OpCode::Mov>(bpl, r15b);
buffer.Emit<OpCode::Mov>(bp, r15w);
buffer.Emit<OpCode::Mov>(ebp, r15d);
buffer.Emit<OpCode::Mov>(rbp, r15);
buffer.Emit<OpCode::Mov>(bpl, r15, -4);
buffer.Emit<OpCode::Mov>(bpl, r15, 4);
buffer.Emit<OpCode::Mov>(bp, r15, 4);
buffer.Emit<OpCode::Mov>(ebp, r15, 4);
buffer.Emit<OpCode::Mov>(rbp, r15, 4);
buffer.Emit<OpCode::Mov>(rbp, -4, r15b);
buffer.Emit<OpCode::Mov>(rbp, 4, r15b);
buffer.Emit<OpCode::Mov>(rbp, 4, r15w);
buffer.Emit<OpCode::Mov>(rbp, 4, r15d);
buffer.Emit<OpCode::Mov>(rbp, 4, r15);
buffer.Emit<OpCode::MovZX>(bp, r15b);
buffer.Emit<OpCode::MovZX, 2, false, 1, false>(bp, r15, 4);
buffer.Emit<OpCode::MovZX>(ebp, r15b);
buffer.Emit<OpCode::MovZX>(ebp, r15w);
buffer.Emit<OpCode::MovZX, 4, false, 1, false>(ebp, r15, 4);
buffer.Emit<OpCode::MovZX, 4, false, 2, false>(ebp, r15, 4);
buffer.Emit<OpCode::MovZX>(rbp, r15b);
buffer.Emit<OpCode::MovZX>(rbp, r15w);
buffer.Emit<OpCode::MovZX, 8, false, 1, false>(rbp, r15, 4);
buffer.Emit<OpCode::MovZX, 8, false, 2, false>(rbp, r15, 4);
// Source: r15, target: rsi
buffer.EmitImmediate<OpCode::Mov>(dil, static_cast<uint8_t>(1));
buffer.EmitImmediate<OpCode::Mov>(si, static_cast<uint16_t>(1));
buffer.EmitImmediate<OpCode::Mov>(esi, 1);
buffer.EmitImmediate<OpCode::Mov>(rsi, 1);
buffer.Emit<OpCode::Mov>(dil, r15b);
buffer.Emit<OpCode::Mov>(si, r15w);
buffer.Emit<OpCode::Mov>(esi, r15d);
buffer.Emit<OpCode::Mov>(rsi, r15);
buffer.Emit<OpCode::Mov>(dil, r15, -4);
buffer.Emit<OpCode::Mov>(dil, r15, 4);
buffer.Emit<OpCode::Mov>(si, r15, 4);
buffer.Emit<OpCode::Mov>(esi, r15, 4);
buffer.Emit<OpCode::Mov>(rsi, r15, 4);
buffer.Emit<OpCode::Mov>(rsi, -4, r15b);
buffer.Emit<OpCode::Mov>(rsi, 4, r15b);
buffer.Emit<OpCode::Mov>(rsi, 4, r15w);
buffer.Emit<OpCode::Mov>(rsi, 4, r15d);
buffer.Emit<OpCode::Mov>(rsi, 4, r15);
buffer.Emit<OpCode::MovZX>(si, r15b);
buffer.Emit<OpCode::MovZX, 2, false, 1, false>(si, r15, 4);
buffer.Emit<OpCode::MovZX>(esi, r15b);
buffer.Emit<OpCode::MovZX>(esi, r15w);
buffer.Emit<OpCode::MovZX, 4, false, 1, false>(esi, r15, 4);
buffer.Emit<OpCode::MovZX, 4, false, 2, false>(esi, r15, 4);
buffer.Emit<OpCode::MovZX>(rsi, r15b);
buffer.Emit<OpCode::MovZX>(rsi, r15w);
buffer.Emit<OpCode::MovZX, 8, false, 1, false>(rsi, r15, 4);
buffer.Emit<OpCode::MovZX, 8, false, 2, false>(rsi, r15, 4);
// Source: r15, target: rdi
buffer.EmitImmediate<OpCode::Mov>(sil, static_cast<uint8_t>(1));
buffer.EmitImmediate<OpCode::Mov>(di, static_cast<uint16_t>(1));
buffer.EmitImmediate<OpCode::Mov>(edi, 1);
buffer.EmitImmediate<OpCode::Mov>(rdi, 1);
buffer.Emit<OpCode::Mov>(sil, r15b);
buffer.Emit<OpCode::Mov>(di, r15w);
buffer.Emit<OpCode::Mov>(edi, r15d);
buffer.Emit<OpCode::Mov>(rdi, r15);
buffer.Emit<OpCode::Mov>(sil, r15, -4);
buffer.Emit<OpCode::Mov>(sil, r15, 4);
buffer.Emit<OpCode::Mov>(di, r15, 4);
buffer.Emit<OpCode::Mov>(edi, r15, 4);
buffer.Emit<OpCode::Mov>(rdi, r15, 4);
buffer.Emit<OpCode::Mov>(rdi, -4, r15b);
buffer.Emit<OpCode::Mov>(rdi, 4, r15b);
buffer.Emit<OpCode::Mov>(rdi, 4, r15w);
buffer.Emit<OpCode::Mov>(rdi, 4, r15d);
buffer.Emit<OpCode::Mov>(rdi, 4, r15);
buffer.Emit<OpCode::MovZX>(di, r15b);
buffer.Emit<OpCode::MovZX, 2, false, 1, false>(di, r15, 4);
buffer.Emit<OpCode::MovZX>(edi, r15b);
buffer.Emit<OpCode::MovZX>(edi, r15w);
buffer.Emit<OpCode::MovZX, 4, false, 1, false>(edi, r15, 4);
buffer.Emit<OpCode::MovZX, 4, false, 2, false>(edi, r15, 4);
buffer.Emit<OpCode::MovZX>(rdi, r15b);
buffer.Emit<OpCode::MovZX>(rdi, r15w);
buffer.Emit<OpCode::MovZX, 8, false, 1, false>(rdi, r15, 4);
buffer.Emit<OpCode::MovZX, 8, false, 2, false>(rdi, r15, 4);
// Source: r15, target: r8
buffer.EmitImmediate<OpCode::Mov>(r8b, static_cast<uint8_t>(1));
buffer.EmitImmediate<OpCode::Mov>(r8w, static_cast<uint16_t>(1));
buffer.EmitImmediate<OpCode::Mov>(r8d, 1);
buffer.EmitImmediate<OpCode::Mov>(r8, 1);
buffer.Emit<OpCode::Mov>(r8b, r15b);
buffer.Emit<OpCode::Mov>(r8w, r15w);
buffer.Emit<OpCode::Mov>(r8d, r15d);
buffer.Emit<OpCode::Mov>(r8, r15);
buffer.Emit<OpCode::Mov>(r8b, r15, -4);
buffer.Emit<OpCode::Mov>(r8b, r15, 4);
buffer.Emit<OpCode::Mov>(r8w, r15, 4);
buffer.Emit<OpCode::Mov>(r8d, r15, 4);
buffer.Emit<OpCode::Mov>(r8, r15, 4);
buffer.Emit<OpCode::Mov>(r8, -4, r15b);
buffer.Emit<OpCode::Mov>(r8, 4, r15b);
buffer.Emit<OpCode::Mov>(r8, 4, r15w);
buffer.Emit<OpCode::Mov>(r8, 4, r15d);
buffer.Emit<OpCode::Mov>(r8, 4, r15);
buffer.Emit<OpCode::MovZX>(r8w, r15b);
buffer.Emit<OpCode::MovZX, 2, false, 1, false>(r8w, r15, 4);
buffer.Emit<OpCode::MovZX>(r8d, r15b);
buffer.Emit<OpCode::MovZX>(r8d, r15w);
buffer.Emit<OpCode::MovZX, 4, false, 1, false>(r8d, r15, 4);
buffer.Emit<OpCode::MovZX, 4, false, 2, false>(r8d, r15, 4);
buffer.Emit<OpCode::MovZX>(r8, r15b);
buffer.Emit<OpCode::MovZX>(r8, r15w);
buffer.Emit<OpCode::MovZX, 8, false, 1, false>(r8, r15, 4);
buffer.Emit<OpCode::MovZX, 8, false, 2, false>(r8, r15, 4);
// Source: r15, target: r9
buffer.EmitImmediate<OpCode::Mov>(r9b, static_cast<uint8_t>(1));
buffer.EmitImmediate<OpCode::Mov>(r9w, static_cast<uint16_t>(1));
buffer.EmitImmediate<OpCode::Mov>(r9d, 1);
buffer.EmitImmediate<OpCode::Mov>(r9, 1);
buffer.Emit<OpCode::Mov>(r9b, r15b);
buffer.Emit<OpCode::Mov>(r9w, r15w);
buffer.Emit<OpCode::Mov>(r9d, r15d);
buffer.Emit<OpCode::Mov>(r9, r15);
buffer.Emit<OpCode::Mov>(r9b, r15, -4);
buffer.Emit<OpCode::Mov>(r9b, r15, 4);
buffer.Emit<OpCode::Mov>(r9w, r15, 4);
buffer.Emit<OpCode::Mov>(r9d, r15, 4);
buffer.Emit<OpCode::Mov>(r9, r15, 4);
buffer.Emit<OpCode::Mov>(r9, -4, r15b);
buffer.Emit<OpCode::Mov>(r9, 4, r15b);
buffer.Emit<OpCode::Mov>(r9, 4, r15w);
buffer.Emit<OpCode::Mov>(r9, 4, r15d);
buffer.Emit<OpCode::Mov>(r9, 4, r15);
buffer.Emit<OpCode::MovZX>(r9w, r15b);
buffer.Emit<OpCode::MovZX, 2, false, 1, false>(r9w, r15, 4);
buffer.Emit<OpCode::MovZX>(r9d, r15b);
buffer.Emit<OpCode::MovZX>(r9d, r15w);
buffer.Emit<OpCode::MovZX, 4, false, 1, false>(r9d, r15, 4);
buffer.Emit<OpCode::MovZX, 4, false, 2, false>(r9d, r15, 4);
buffer.Emit<OpCode::MovZX>(r9, r15b);
buffer.Emit<OpCode::MovZX>(r9, r15w);
buffer.Emit<OpCode::MovZX, 8, false, 1, false>(r9, r15, 4);
buffer.Emit<OpCode::MovZX, 8, false, 2, false>(r9, r15, 4);
// Source: r15, target: r10
buffer.EmitImmediate<OpCode::Mov>(r10b, static_cast<uint8_t>(1));
buffer.EmitImmediate<OpCode::Mov>(r10w, static_cast<uint16_t>(1));
buffer.EmitImmediate<OpCode::Mov>(r10d, 1);
buffer.EmitImmediate<OpCode::Mov>(r10, 1);
buffer.Emit<OpCode::Mov>(r10b, r15b);
buffer.Emit<OpCode::Mov>(r10w, r15w);
buffer.Emit<OpCode::Mov>(r10d, r15d);
buffer.Emit<OpCode::Mov>(r10, r15);
buffer.Emit<OpCode::Mov>(r10b, r15, -4);
buffer.Emit<OpCode::Mov>(r10b, r15, 4);
buffer.Emit<OpCode::Mov>(r10w, r15, 4);
buffer.Emit<OpCode::Mov>(r10d, r15, 4);
buffer.Emit<OpCode::Mov>(r10, r15, 4);
buffer.Emit<OpCode::Mov>(r10, -4, r15b);
buffer.Emit<OpCode::Mov>(r10, 4, r15b);
buffer.Emit<OpCode::Mov>(r10, 4, r15w);
buffer.Emit<OpCode::Mov>(r10, 4, r15d);
buffer.Emit<OpCode::Mov>(r10, 4, r15);
buffer.Emit<OpCode::MovZX>(r10w, r15b);
buffer.Emit<OpCode::MovZX, 2, false, 1, false>(r10w, r15, 4);
buffer.Emit<OpCode::MovZX>(r10d, r15b);
buffer.Emit<OpCode::MovZX>(r10d, r15w);
buffer.Emit<OpCode::MovZX, 4, false, 1, false>(r10d, r15, 4);
buffer.Emit<OpCode::MovZX, 4, false, 2, false>(r10d, r15, 4);
buffer.Emit<OpCode::MovZX>(r10, r15b);
buffer.Emit<OpCode::MovZX>(r10, r15w);
buffer.Emit<OpCode::MovZX, 8, false, 1, false>(r10, r15, 4);
buffer.Emit<OpCode::MovZX, 8, false, 2, false>(r10, r15, 4);
// Source: r15, target: r11
buffer.EmitImmediate<OpCode::Mov>(r11b, static_cast<uint8_t>(1));
buffer.EmitImmediate<OpCode::Mov>(r11w, static_cast<uint16_t>(1));
buffer.EmitImmediate<OpCode::Mov>(r11d, 1);
buffer.EmitImmediate<OpCode::Mov>(r11, 1);
buffer.Emit<OpCode::Mov>(r11b, r15b);
buffer.Emit<OpCode::Mov>(r11w, r15w);
buffer.Emit<OpCode::Mov>(r11d, r15d);
buffer.Emit<OpCode::Mov>(r11, r15);
buffer.Emit<OpCode::Mov>(r11b, r15, -4);
buffer.Emit<OpCode::Mov>(r11b, r15, 4);
buffer.Emit<OpCode::Mov>(r11w, r15, 4);
buffer.Emit<OpCode::Mov>(r11d, r15, 4);
buffer.Emit<OpCode::Mov>(r11, r15, 4);
buffer.Emit<OpCode::Mov>(r11, -4, r15b);
buffer.Emit<OpCode::Mov>(r11, 4, r15b);
buffer.Emit<OpCode::Mov>(r11, 4, r15w);
buffer.Emit<OpCode::Mov>(r11, 4, r15d);
buffer.Emit<OpCode::Mov>(r11, 4, r15);
buffer.Emit<OpCode::MovZX>(r11w, r15b);
buffer.Emit<OpCode::MovZX, 2, false, 1, false>(r11w, r15, 4);
buffer.Emit<OpCode::MovZX>(r11d, r15b);
buffer.Emit<OpCode::MovZX>(r11d, r15w);
buffer.Emit<OpCode::MovZX, 4, false, 1, false>(r11d, r15, 4);
buffer.Emit<OpCode::MovZX, 4, false, 2, false>(r11d, r15, 4);
buffer.Emit<OpCode::MovZX>(r11, r15b);
buffer.Emit<OpCode::MovZX>(r11, r15w);
buffer.Emit<OpCode::MovZX, 8, false, 1, false>(r11, r15, 4);
buffer.Emit<OpCode::MovZX, 8, false, 2, false>(r11, r15, 4);
// Source: r15, target: r12
buffer.EmitImmediate<OpCode::Mov>(r12b, static_cast<uint8_t>(1));
buffer.EmitImmediate<OpCode::Mov>(r12w, static_cast<uint16_t>(1));
buffer.EmitImmediate<OpCode::Mov>(r12d, 1);
buffer.EmitImmediate<OpCode::Mov>(r12, 1);
buffer.Emit<OpCode::Mov>(r12b, r15b);
buffer.Emit<OpCode::Mov>(r12w, r15w);
buffer.Emit<OpCode::Mov>(r12d, r15d);
buffer.Emit<OpCode::Mov>(r12, r15);
buffer.Emit<OpCode::Mov>(r12b, r15, -4);
buffer.Emit<OpCode::Mov>(r12b, r15, 4);
buffer.Emit<OpCode::Mov>(r12w, r15, 4);
buffer.Emit<OpCode::Mov>(r12d, r15, 4);
buffer.Emit<OpCode::Mov>(r12, r15, 4);
buffer.Emit<OpCode::Mov>(r12, -4, r15b);
buffer.Emit<OpCode::Mov>(r12, 4, r15b);
buffer.Emit<OpCode::Mov>(r12, 4, r15w);
buffer.Emit<OpCode::Mov>(r12, 4, r15d);
buffer.Emit<OpCode::Mov>(r12, 4, r15);
buffer.Emit<OpCode::MovZX>(r12w, r15b);
buffer.Emit<OpCode::MovZX, 2, false, 1, false>(r12w, r15, 4);
buffer.Emit<OpCode::MovZX>(r12d, r15b);
buffer.Emit<OpCode::MovZX>(r12d, r15w);
buffer.Emit<OpCode::MovZX, 4, false, 1, false>(r12d, r15, 4);
buffer.Emit<OpCode::MovZX, 4, false, 2, false>(r12d, r15, 4);
buffer.Emit<OpCode::MovZX>(r12, r15b);
buffer.Emit<OpCode::MovZX>(r12, r15w);
buffer.Emit<OpCode::MovZX, 8, false, 1, false>(r12, r15, 4);
buffer.Emit<OpCode::MovZX, 8, false, 2, false>(r12, r15, 4);
// Source: r15, target: r13
buffer.EmitImmediate<OpCode::Mov>(r13b, static_cast<uint8_t>(1));
buffer.EmitImmediate<OpCode::Mov>(r13w, static_cast<uint16_t>(1));
buffer.EmitImmediate<OpCode::Mov>(r13d, 1);
buffer.EmitImmediate<OpCode::Mov>(r13, 1);
buffer.Emit<OpCode::Mov>(r13b, r15b);
buffer.Emit<OpCode::Mov>(r13w, r15w);
buffer.Emit<OpCode::Mov>(r13d, r15d);
buffer.Emit<OpCode::Mov>(r13, r15);
buffer.Emit<OpCode::Mov>(r13b, r15, -4);
buffer.Emit<OpCode::Mov>(r13b, r15, 4);
buffer.Emit<OpCode::Mov>(r13w, r15, 4);
buffer.Emit<OpCode::Mov>(r13d, r15, 4);
buffer.Emit<OpCode::Mov>(r13, r15, 4);
buffer.Emit<OpCode::Mov>(r13, -4, r15b);
buffer.Emit<OpCode::Mov>(r13, 4, r15b);
buffer.Emit<OpCode::Mov>(r13, 4, r15w);
buffer.Emit<OpCode::Mov>(r13, 4, r15d);
buffer.Emit<OpCode::Mov>(r13, 4, r15);
buffer.Emit<OpCode::MovZX>(r13w, r15b);
buffer.Emit<OpCode::MovZX, 2, false, 1, false>(r13w, r15, 4);
buffer.Emit<OpCode::MovZX>(r13d, r15b);
buffer.Emit<OpCode::MovZX>(r13d, r15w);
buffer.Emit<OpCode::MovZX, 4, false, 1, false>(r13d, r15, 4);
buffer.Emit<OpCode::MovZX, 4, false, 2, false>(r13d, r15, 4);
buffer.Emit<OpCode::MovZX>(r13, r15b);
buffer.Emit<OpCode::MovZX>(r13, r15w);
buffer.Emit<OpCode::MovZX, 8, false, 1, false>(r13, r15, 4);
buffer.Emit<OpCode::MovZX, 8, false, 2, false>(r13, r15, 4);
// Source: r15, target: r14
buffer.EmitImmediate<OpCode::Mov>(r14b, static_cast<uint8_t>(1));
buffer.EmitImmediate<OpCode::Mov>(r14w, static_cast<uint16_t>(1));
buffer.EmitImmediate<OpCode::Mov>(r14d, 1);
buffer.EmitImmediate<OpCode::Mov>(r14, 1);
buffer.Emit<OpCode::Mov>(r14b, r15b);
buffer.Emit<OpCode::Mov>(r14w, r15w);
buffer.Emit<OpCode::Mov>(r14d, r15d);
buffer.Emit<OpCode::Mov>(r14, r15);
buffer.Emit<OpCode::Mov>(r14b, r15, -4);
buffer.Emit<OpCode::Mov>(r14b, r15, 4);
buffer.Emit<OpCode::Mov>(r14w, r15, 4);
buffer.Emit<OpCode::Mov>(r14d, r15, 4);
buffer.Emit<OpCode::Mov>(r14, r15, 4);
buffer.Emit<OpCode::Mov>(r14, -4, r15b);
buffer.Emit<OpCode::Mov>(r14, 4, r15b);
buffer.Emit<OpCode::Mov>(r14, 4, r15w);
buffer.Emit<OpCode::Mov>(r14, 4, r15d);
buffer.Emit<OpCode::Mov>(r14, 4, r15);
buffer.Emit<OpCode::MovZX>(r14w, r15b);
buffer.Emit<OpCode::MovZX, 2, false, 1, false>(r14w, r15, 4);
buffer.Emit<OpCode::MovZX>(r14d, r15b);
buffer.Emit<OpCode::MovZX>(r14d, r15w);
buffer.Emit<OpCode::MovZX, 4, false, 1, false>(r14d, r15, 4);
buffer.Emit<OpCode::MovZX, 4, false, 2, false>(r14d, r15, 4);
buffer.Emit<OpCode::MovZX>(r14, r15b);
buffer.Emit<OpCode::MovZX>(r14, r15w);
buffer.Emit<OpCode::MovZX, 8, false, 1, false>(r14, r15, 4);
buffer.Emit<OpCode::MovZX, 8, false, 2, false>(r14, r15, 4);
// Source: r15, target: r15
buffer.EmitImmediate<OpCode::Mov>(r15b, static_cast<uint8_t>(1));
buffer.EmitImmediate<OpCode::Mov>(r15w, static_cast<uint16_t>(1));
buffer.EmitImmediate<OpCode::Mov>(r15d, 1);
buffer.EmitImmediate<OpCode::Mov>(r15, 1);
buffer.Emit<OpCode::Mov>(r15b, r15b);
buffer.Emit<OpCode::Mov>(r15w, r15w);
buffer.Emit<OpCode::Mov>(r15d, r15d);
buffer.Emit<OpCode::Mov>(r15, r15);
buffer.Emit<OpCode::Mov>(r15b, r15, -4);
buffer.Emit<OpCode::Mov>(r15b, r15, 4);
buffer.Emit<OpCode::Mov>(r15w, r15, 4);
buffer.Emit<OpCode::Mov>(r15d, r15, 4);
buffer.Emit<OpCode::Mov>(r15, r15, 4);
buffer.Emit<OpCode::Mov>(r15, -4, r15b);
buffer.Emit<OpCode::Mov>(r15, 4, r15b);
buffer.Emit<OpCode::Mov>(r15, 4, r15w);
buffer.Emit<OpCode::Mov>(r15, 4, r15d);
buffer.Emit<OpCode::Mov>(r15, 4, r15);
buffer.Emit<OpCode::MovZX>(r15w, r15b);
buffer.Emit<OpCode::MovZX, 2, false, 1, false>(r15w, r15, 4);
buffer.Emit<OpCode::MovZX>(r15d, r15b);
buffer.Emit<OpCode::MovZX>(r15d, r15w);
buffer.Emit<OpCode::MovZX, 4, false, 1, false>(r15d, r15, 4);
buffer.Emit<OpCode::MovZX, 4, false, 2, false>(r15d, r15, 4);
buffer.Emit<OpCode::MovZX>(r15, r15b);
buffer.Emit<OpCode::MovZX>(r15, r15w);
buffer.Emit<OpCode::MovZX, 8, false, 1, false>(r15, r15, 4);
buffer.Emit<OpCode::MovZX, 8, false, 2, false>(r15, r15, 4);
//
// Float <-> float
//
// Source: xmm0, target: xmm0
buffer.Emit<OpCode::Mov>(xmm0s, xmm0s);
buffer.Emit<OpCode::Mov>(xmm0, xmm0);
buffer.Emit<OpCode::CvtFP2FP>(xmm0, xmm0s);
buffer.Emit<OpCode::CvtFP2FP>(xmm0s, xmm0);
// Source: xmm0, target: xmm1
buffer.Emit<OpCode::Mov>(xmm1s, xmm0s);
buffer.Emit<OpCode::Mov>(xmm1, xmm0);
buffer.Emit<OpCode::CvtFP2FP>(xmm1, xmm0s);
buffer.Emit<OpCode::CvtFP2FP>(xmm1s, xmm0);
// Source: xmm0, target: xmm2
buffer.Emit<OpCode::Mov>(xmm2s, xmm0s);
buffer.Emit<OpCode::Mov>(xmm2, xmm0);
buffer.Emit<OpCode::CvtFP2FP>(xmm2, xmm0s);
buffer.Emit<OpCode::CvtFP2FP>(xmm2s, xmm0);
// Source: xmm0, target: xmm3
buffer.Emit<OpCode::Mov>(xmm3s, xmm0s);
buffer.Emit<OpCode::Mov>(xmm3, xmm0);
buffer.Emit<OpCode::CvtFP2FP>(xmm3, xmm0s);
buffer.Emit<OpCode::CvtFP2FP>(xmm3s, xmm0);
// Source: xmm0, target: xmm4
buffer.Emit<OpCode::Mov>(xmm4s, xmm0s);
buffer.Emit<OpCode::Mov>(xmm4, xmm0);
buffer.Emit<OpCode::CvtFP2FP>(xmm4, xmm0s);
buffer.Emit<OpCode::CvtFP2FP>(xmm4s, xmm0);
// Source: xmm0, target: xmm5
buffer.Emit<OpCode::Mov>(xmm5s, xmm0s);
buffer.Emit<OpCode::Mov>(xmm5, xmm0);
buffer.Emit<OpCode::CvtFP2FP>(xmm5, xmm0s);
buffer.Emit<OpCode::CvtFP2FP>(xmm5s, xmm0);
// Source: xmm0, target: xmm6
buffer.Emit<OpCode::Mov>(xmm6s, xmm0s);
buffer.Emit<OpCode::Mov>(xmm6, xmm0);
buffer.Emit<OpCode::CvtFP2FP>(xmm6, xmm0s);
buffer.Emit<OpCode::CvtFP2FP>(xmm6s, xmm0);
// Source: xmm0, target: xmm7
buffer.Emit<OpCode::Mov>(xmm7s, xmm0s);
buffer.Emit<OpCode::Mov>(xmm7, xmm0);
buffer.Emit<OpCode::CvtFP2FP>(xmm7, xmm0s);
buffer.Emit<OpCode::CvtFP2FP>(xmm7s, xmm0);
// Source: xmm0, target: xmm8
buffer.Emit<OpCode::Mov>(xmm8s, xmm0s);
buffer.Emit<OpCode::Mov>(xmm8, xmm0);
buffer.Emit<OpCode::CvtFP2FP>(xmm8, xmm0s);
buffer.Emit<OpCode::CvtFP2FP>(xmm8s, xmm0);
// Source: xmm0, target: xmm9
buffer.Emit<OpCode::Mov>(xmm9s, xmm0s);
buffer.Emit<OpCode::Mov>(xmm9, xmm0);
buffer.Emit<OpCode::CvtFP2FP>(xmm9, xmm0s);
buffer.Emit<OpCode::CvtFP2FP>(xmm9s, xmm0);
// Source: xmm0, target: xmm10
buffer.Emit<OpCode::Mov>(xmm10s, xmm0s);
buffer.Emit<OpCode::Mov>(xmm10, xmm0);
buffer.Emit<OpCode::CvtFP2FP>(xmm10, xmm0s);
buffer.Emit<OpCode::CvtFP2FP>(xmm10s, xmm0);
// Source: xmm0, target: xmm11
buffer.Emit<OpCode::Mov>(xmm11s, xmm0s);
buffer.Emit<OpCode::Mov>(xmm11, xmm0);
buffer.Emit<OpCode::CvtFP2FP>(xmm11, xmm0s);
buffer.Emit<OpCode::CvtFP2FP>(xmm11s, xmm0);
// Source: xmm0, target: xmm12
buffer.Emit<OpCode::Mov>(xmm12s, xmm0s);
buffer.Emit<OpCode::Mov>(xmm12, xmm0);
buffer.Emit<OpCode::CvtFP2FP>(xmm12, xmm0s);
buffer.Emit<OpCode::CvtFP2FP>(xmm12s, xmm0);
// Source: xmm0, target: xmm13
buffer.Emit<OpCode::Mov>(xmm13s, xmm0s);
buffer.Emit<OpCode::Mov>(xmm13, xmm0);
buffer.Emit<OpCode::CvtFP2FP>(xmm13, xmm0s);
buffer.Emit<OpCode::CvtFP2FP>(xmm13s, xmm0);
// Source: xmm0, target: xmm14
buffer.Emit<OpCode::Mov>(xmm14s, xmm0s);
buffer.Emit<OpCode::Mov>(xmm14, xmm0);
buffer.Emit<OpCode::CvtFP2FP>(xmm14, xmm0s);
buffer.Emit<OpCode::CvtFP2FP>(xmm14s, xmm0);
// Source: xmm0, target: xmm15
buffer.Emit<OpCode::Mov>(xmm15s, xmm0s);
buffer.Emit<OpCode::Mov>(xmm15, xmm0);
buffer.Emit<OpCode::CvtFP2FP>(xmm15, xmm0s);
buffer.Emit<OpCode::CvtFP2FP>(xmm15s, xmm0);
// Source: xmm1, target: xmm0
buffer.Emit<OpCode::Mov>(xmm0s, xmm1s);
buffer.Emit<OpCode::Mov>(xmm0, xmm1);
buffer.Emit<OpCode::CvtFP2FP>(xmm0, xmm1s);
buffer.Emit<OpCode::CvtFP2FP>(xmm0s, xmm1);
// Source: xmm1, target: xmm1
buffer.Emit<OpCode::Mov>(xmm1s, xmm1s);
buffer.Emit<OpCode::Mov>(xmm1, xmm1);
buffer.Emit<OpCode::CvtFP2FP>(xmm1, xmm1s);
buffer.Emit<OpCode::CvtFP2FP>(xmm1s, xmm1);
// Source: xmm1, target: xmm2
buffer.Emit<OpCode::Mov>(xmm2s, xmm1s);
buffer.Emit<OpCode::Mov>(xmm2, xmm1);
buffer.Emit<OpCode::CvtFP2FP>(xmm2, xmm1s);
buffer.Emit<OpCode::CvtFP2FP>(xmm2s, xmm1);
// Source: xmm1, target: xmm3
buffer.Emit<OpCode::Mov>(xmm3s, xmm1s);
buffer.Emit<OpCode::Mov>(xmm3, xmm1);
buffer.Emit<OpCode::CvtFP2FP>(xmm3, xmm1s);
buffer.Emit<OpCode::CvtFP2FP>(xmm3s, xmm1);
// Source: xmm1, target: xmm4
buffer.Emit<OpCode::Mov>(xmm4s, xmm1s);
buffer.Emit<OpCode::Mov>(xmm4, xmm1);
buffer.Emit<OpCode::CvtFP2FP>(xmm4, xmm1s);
buffer.Emit<OpCode::CvtFP2FP>(xmm4s, xmm1);
// Source: xmm1, target: xmm5
buffer.Emit<OpCode::Mov>(xmm5s, xmm1s);
buffer.Emit<OpCode::Mov>(xmm5, xmm1);
buffer.Emit<OpCode::CvtFP2FP>(xmm5, xmm1s);
buffer.Emit<OpCode::CvtFP2FP>(xmm5s, xmm1);
// Source: xmm1, target: xmm6
buffer.Emit<OpCode::Mov>(xmm6s, xmm1s);
buffer.Emit<OpCode::Mov>(xmm6, xmm1);
buffer.Emit<OpCode::CvtFP2FP>(xmm6, xmm1s);
buffer.Emit<OpCode::CvtFP2FP>(xmm6s, xmm1);
// Source: xmm1, target: xmm7
buffer.Emit<OpCode::Mov>(xmm7s, xmm1s);
buffer.Emit<OpCode::Mov>(xmm7, xmm1);
buffer.Emit<OpCode::CvtFP2FP>(xmm7, xmm1s);
buffer.Emit<OpCode::CvtFP2FP>(xmm7s, xmm1);
// Source: xmm1, target: xmm8
buffer.Emit<OpCode::Mov>(xmm8s, xmm1s);
buffer.Emit<OpCode::Mov>(xmm8, xmm1);
buffer.Emit<OpCode::CvtFP2FP>(xmm8, xmm1s);
buffer.Emit<OpCode::CvtFP2FP>(xmm8s, xmm1);
// Source: xmm1, target: xmm9
buffer.Emit<OpCode::Mov>(xmm9s, xmm1s);
buffer.Emit<OpCode::Mov>(xmm9, xmm1);
buffer.Emit<OpCode::CvtFP2FP>(xmm9, xmm1s);
buffer.Emit<OpCode::CvtFP2FP>(xmm9s, xmm1);
// Source: xmm1, target: xmm10
buffer.Emit<OpCode::Mov>(xmm10s, xmm1s);
buffer.Emit<OpCode::Mov>(xmm10, xmm1);
buffer.Emit<OpCode::CvtFP2FP>(xmm10, xmm1s);
buffer.Emit<OpCode::CvtFP2FP>(xmm10s, xmm1);
// Source: xmm1, target: xmm11
buffer.Emit<OpCode::Mov>(xmm11s, xmm1s);
buffer.Emit<OpCode::Mov>(xmm11, xmm1);
buffer.Emit<OpCode::CvtFP2FP>(xmm11, xmm1s);
buffer.Emit<OpCode::CvtFP2FP>(xmm11s, xmm1);
// Source: xmm1, target: xmm12
buffer.Emit<OpCode::Mov>(xmm12s, xmm1s);
buffer.Emit<OpCode::Mov>(xmm12, xmm1);
buffer.Emit<OpCode::CvtFP2FP>(xmm12, xmm1s);
buffer.Emit<OpCode::CvtFP2FP>(xmm12s, xmm1);
// Source: xmm1, target: xmm13
buffer.Emit<OpCode::Mov>(xmm13s, xmm1s);
buffer.Emit<OpCode::Mov>(xmm13, xmm1);
buffer.Emit<OpCode::CvtFP2FP>(xmm13, xmm1s);
buffer.Emit<OpCode::CvtFP2FP>(xmm13s, xmm1);
// Source: xmm1, target: xmm14
buffer.Emit<OpCode::Mov>(xmm14s, xmm1s);
buffer.Emit<OpCode::Mov>(xmm14, xmm1);
buffer.Emit<OpCode::CvtFP2FP>(xmm14, xmm1s);
buffer.Emit<OpCode::CvtFP2FP>(xmm14s, xmm1);
// Source: xmm1, target: xmm15
buffer.Emit<OpCode::Mov>(xmm15s, xmm1s);
buffer.Emit<OpCode::Mov>(xmm15, xmm1);
buffer.Emit<OpCode::CvtFP2FP>(xmm15, xmm1s);
buffer.Emit<OpCode::CvtFP2FP>(xmm15s, xmm1);
// Source: xmm2, target: xmm0
buffer.Emit<OpCode::Mov>(xmm0s, xmm2s);
buffer.Emit<OpCode::Mov>(xmm0, xmm2);
buffer.Emit<OpCode::CvtFP2FP>(xmm0, xmm2s);
buffer.Emit<OpCode::CvtFP2FP>(xmm0s, xmm2);
// Source: xmm2, target: xmm1
buffer.Emit<OpCode::Mov>(xmm1s, xmm2s);
buffer.Emit<OpCode::Mov>(xmm1, xmm2);
buffer.Emit<OpCode::CvtFP2FP>(xmm1, xmm2s);
buffer.Emit<OpCode::CvtFP2FP>(xmm1s, xmm2);
// Source: xmm2, target: xmm2
buffer.Emit<OpCode::Mov>(xmm2s, xmm2s);
buffer.Emit<OpCode::Mov>(xmm2, xmm2);
buffer.Emit<OpCode::CvtFP2FP>(xmm2, xmm2s);
buffer.Emit<OpCode::CvtFP2FP>(xmm2s, xmm2);
// Source: xmm2, target: xmm3
buffer.Emit<OpCode::Mov>(xmm3s, xmm2s);
buffer.Emit<OpCode::Mov>(xmm3, xmm2);
buffer.Emit<OpCode::CvtFP2FP>(xmm3, xmm2s);
buffer.Emit<OpCode::CvtFP2FP>(xmm3s, xmm2);
// Source: xmm2, target: xmm4
buffer.Emit<OpCode::Mov>(xmm4s, xmm2s);
buffer.Emit<OpCode::Mov>(xmm4, xmm2);
buffer.Emit<OpCode::CvtFP2FP>(xmm4, xmm2s);
buffer.Emit<OpCode::CvtFP2FP>(xmm4s, xmm2);
// Source: xmm2, target: xmm5
buffer.Emit<OpCode::Mov>(xmm5s, xmm2s);
buffer.Emit<OpCode::Mov>(xmm5, xmm2);
buffer.Emit<OpCode::CvtFP2FP>(xmm5, xmm2s);
buffer.Emit<OpCode::CvtFP2FP>(xmm5s, xmm2);
// Source: xmm2, target: xmm6
buffer.Emit<OpCode::Mov>(xmm6s, xmm2s);
buffer.Emit<OpCode::Mov>(xmm6, xmm2);
buffer.Emit<OpCode::CvtFP2FP>(xmm6, xmm2s);
buffer.Emit<OpCode::CvtFP2FP>(xmm6s, xmm2);
// Source: xmm2, target: xmm7
buffer.Emit<OpCode::Mov>(xmm7s, xmm2s);
buffer.Emit<OpCode::Mov>(xmm7, xmm2);
buffer.Emit<OpCode::CvtFP2FP>(xmm7, xmm2s);
buffer.Emit<OpCode::CvtFP2FP>(xmm7s, xmm2);
// Source: xmm2, target: xmm8
buffer.Emit<OpCode::Mov>(xmm8s, xmm2s);
buffer.Emit<OpCode::Mov>(xmm8, xmm2);
buffer.Emit<OpCode::CvtFP2FP>(xmm8, xmm2s);
buffer.Emit<OpCode::CvtFP2FP>(xmm8s, xmm2);
// Source: xmm2, target: xmm9
buffer.Emit<OpCode::Mov>(xmm9s, xmm2s);
buffer.Emit<OpCode::Mov>(xmm9, xmm2);
buffer.Emit<OpCode::CvtFP2FP>(xmm9, xmm2s);
buffer.Emit<OpCode::CvtFP2FP>(xmm9s, xmm2);
// Source: xmm2, target: xmm10
buffer.Emit<OpCode::Mov>(xmm10s, xmm2s);
buffer.Emit<OpCode::Mov>(xmm10, xmm2);
buffer.Emit<OpCode::CvtFP2FP>(xmm10, xmm2s);
buffer.Emit<OpCode::CvtFP2FP>(xmm10s, xmm2);
// Source: xmm2, target: xmm11
buffer.Emit<OpCode::Mov>(xmm11s, xmm2s);
buffer.Emit<OpCode::Mov>(xmm11, xmm2);
buffer.Emit<OpCode::CvtFP2FP>(xmm11, xmm2s);
buffer.Emit<OpCode::CvtFP2FP>(xmm11s, xmm2);
// Source: xmm2, target: xmm12
buffer.Emit<OpCode::Mov>(xmm12s, xmm2s);
buffer.Emit<OpCode::Mov>(xmm12, xmm2);
buffer.Emit<OpCode::CvtFP2FP>(xmm12, xmm2s);
buffer.Emit<OpCode::CvtFP2FP>(xmm12s, xmm2);
// Source: xmm2, target: xmm13
buffer.Emit<OpCode::Mov>(xmm13s, xmm2s);
buffer.Emit<OpCode::Mov>(xmm13, xmm2);
buffer.Emit<OpCode::CvtFP2FP>(xmm13, xmm2s);
buffer.Emit<OpCode::CvtFP2FP>(xmm13s, xmm2);
// Source: xmm2, target: xmm14
buffer.Emit<OpCode::Mov>(xmm14s, xmm2s);
buffer.Emit<OpCode::Mov>(xmm14, xmm2);
buffer.Emit<OpCode::CvtFP2FP>(xmm14, xmm2s);
buffer.Emit<OpCode::CvtFP2FP>(xmm14s, xmm2);
// Source: xmm2, target: xmm15
buffer.Emit<OpCode::Mov>(xmm15s, xmm2s);
buffer.Emit<OpCode::Mov>(xmm15, xmm2);
buffer.Emit<OpCode::CvtFP2FP>(xmm15, xmm2s);
buffer.Emit<OpCode::CvtFP2FP>(xmm15s, xmm2);
// Source: xmm3, target: xmm0
buffer.Emit<OpCode::Mov>(xmm0s, xmm3s);
buffer.Emit<OpCode::Mov>(xmm0, xmm3);
buffer.Emit<OpCode::CvtFP2FP>(xmm0, xmm3s);
buffer.Emit<OpCode::CvtFP2FP>(xmm0s, xmm3);
// Source: xmm3, target: xmm1
buffer.Emit<OpCode::Mov>(xmm1s, xmm3s);
buffer.Emit<OpCode::Mov>(xmm1, xmm3);
buffer.Emit<OpCode::CvtFP2FP>(xmm1, xmm3s);
buffer.Emit<OpCode::CvtFP2FP>(xmm1s, xmm3);
// Source: xmm3, target: xmm2
buffer.Emit<OpCode::Mov>(xmm2s, xmm3s);
buffer.Emit<OpCode::Mov>(xmm2, xmm3);
buffer.Emit<OpCode::CvtFP2FP>(xmm2, xmm3s);
buffer.Emit<OpCode::CvtFP2FP>(xmm2s, xmm3);
// Source: xmm3, target: xmm3
buffer.Emit<OpCode::Mov>(xmm3s, xmm3s);
buffer.Emit<OpCode::Mov>(xmm3, xmm3);
buffer.Emit<OpCode::CvtFP2FP>(xmm3, xmm3s);
buffer.Emit<OpCode::CvtFP2FP>(xmm3s, xmm3);
// Source: xmm3, target: xmm4
buffer.Emit<OpCode::Mov>(xmm4s, xmm3s);
buffer.Emit<OpCode::Mov>(xmm4, xmm3);
buffer.Emit<OpCode::CvtFP2FP>(xmm4, xmm3s);
buffer.Emit<OpCode::CvtFP2FP>(xmm4s, xmm3);
// Source: xmm3, target: xmm5
buffer.Emit<OpCode::Mov>(xmm5s, xmm3s);
buffer.Emit<OpCode::Mov>(xmm5, xmm3);
buffer.Emit<OpCode::CvtFP2FP>(xmm5, xmm3s);
buffer.Emit<OpCode::CvtFP2FP>(xmm5s, xmm3);
// Source: xmm3, target: xmm6
buffer.Emit<OpCode::Mov>(xmm6s, xmm3s);
buffer.Emit<OpCode::Mov>(xmm6, xmm3);
buffer.Emit<OpCode::CvtFP2FP>(xmm6, xmm3s);
buffer.Emit<OpCode::CvtFP2FP>(xmm6s, xmm3);
// Source: xmm3, target: xmm7
buffer.Emit<OpCode::Mov>(xmm7s, xmm3s);
buffer.Emit<OpCode::Mov>(xmm7, xmm3);
buffer.Emit<OpCode::CvtFP2FP>(xmm7, xmm3s);
buffer.Emit<OpCode::CvtFP2FP>(xmm7s, xmm3);
// Source: xmm3, target: xmm8
buffer.Emit<OpCode::Mov>(xmm8s, xmm3s);
buffer.Emit<OpCode::Mov>(xmm8, xmm3);
buffer.Emit<OpCode::CvtFP2FP>(xmm8, xmm3s);
buffer.Emit<OpCode::CvtFP2FP>(xmm8s, xmm3);
// Source: xmm3, target: xmm9
buffer.Emit<OpCode::Mov>(xmm9s, xmm3s);
buffer.Emit<OpCode::Mov>(xmm9, xmm3);
buffer.Emit<OpCode::CvtFP2FP>(xmm9, xmm3s);
buffer.Emit<OpCode::CvtFP2FP>(xmm9s, xmm3);
// Source: xmm3, target: xmm10
buffer.Emit<OpCode::Mov>(xmm10s, xmm3s);
buffer.Emit<OpCode::Mov>(xmm10, xmm3);
buffer.Emit<OpCode::CvtFP2FP>(xmm10, xmm3s);
buffer.Emit<OpCode::CvtFP2FP>(xmm10s, xmm3);
// Source: xmm3, target: xmm11
buffer.Emit<OpCode::Mov>(xmm11s, xmm3s);
buffer.Emit<OpCode::Mov>(xmm11, xmm3);
buffer.Emit<OpCode::CvtFP2FP>(xmm11, xmm3s);
buffer.Emit<OpCode::CvtFP2FP>(xmm11s, xmm3);
// Source: xmm3, target: xmm12
buffer.Emit<OpCode::Mov>(xmm12s, xmm3s);
buffer.Emit<OpCode::Mov>(xmm12, xmm3);
buffer.Emit<OpCode::CvtFP2FP>(xmm12, xmm3s);
buffer.Emit<OpCode::CvtFP2FP>(xmm12s, xmm3);
// Source: xmm3, target: xmm13
buffer.Emit<OpCode::Mov>(xmm13s, xmm3s);
buffer.Emit<OpCode::Mov>(xmm13, xmm3);
buffer.Emit<OpCode::CvtFP2FP>(xmm13, xmm3s);
buffer.Emit<OpCode::CvtFP2FP>(xmm13s, xmm3);
// Source: xmm3, target: xmm14
buffer.Emit<OpCode::Mov>(xmm14s, xmm3s);
buffer.Emit<OpCode::Mov>(xmm14, xmm3);
buffer.Emit<OpCode::CvtFP2FP>(xmm14, xmm3s);
buffer.Emit<OpCode::CvtFP2FP>(xmm14s, xmm3);
// Source: xmm3, target: xmm15
buffer.Emit<OpCode::Mov>(xmm15s, xmm3s);
buffer.Emit<OpCode::Mov>(xmm15, xmm3);
buffer.Emit<OpCode::CvtFP2FP>(xmm15, xmm3s);
buffer.Emit<OpCode::CvtFP2FP>(xmm15s, xmm3);
// Source: xmm4, target: xmm0
buffer.Emit<OpCode::Mov>(xmm0s, xmm4s);
buffer.Emit<OpCode::Mov>(xmm0, xmm4);
buffer.Emit<OpCode::CvtFP2FP>(xmm0, xmm4s);
buffer.Emit<OpCode::CvtFP2FP>(xmm0s, xmm4);
// Source: xmm4, target: xmm1
buffer.Emit<OpCode::Mov>(xmm1s, xmm4s);
buffer.Emit<OpCode::Mov>(xmm1, xmm4);
buffer.Emit<OpCode::CvtFP2FP>(xmm1, xmm4s);
buffer.Emit<OpCode::CvtFP2FP>(xmm1s, xmm4);
// Source: xmm4, target: xmm2
buffer.Emit<OpCode::Mov>(xmm2s, xmm4s);
buffer.Emit<OpCode::Mov>(xmm2, xmm4);
buffer.Emit<OpCode::CvtFP2FP>(xmm2, xmm4s);
buffer.Emit<OpCode::CvtFP2FP>(xmm2s, xmm4);
// Source: xmm4, target: xmm3
buffer.Emit<OpCode::Mov>(xmm3s, xmm4s);
buffer.Emit<OpCode::Mov>(xmm3, xmm4);
buffer.Emit<OpCode::CvtFP2FP>(xmm3, xmm4s);
buffer.Emit<OpCode::CvtFP2FP>(xmm3s, xmm4);
// Source: xmm4, target: xmm4
buffer.Emit<OpCode::Mov>(xmm4s, xmm4s);
buffer.Emit<OpCode::Mov>(xmm4, xmm4);
buffer.Emit<OpCode::CvtFP2FP>(xmm4, xmm4s);
buffer.Emit<OpCode::CvtFP2FP>(xmm4s, xmm4);
// Source: xmm4, target: xmm5
buffer.Emit<OpCode::Mov>(xmm5s, xmm4s);
buffer.Emit<OpCode::Mov>(xmm5, xmm4);
buffer.Emit<OpCode::CvtFP2FP>(xmm5, xmm4s);
buffer.Emit<OpCode::CvtFP2FP>(xmm5s, xmm4);
// Source: xmm4, target: xmm6
buffer.Emit<OpCode::Mov>(xmm6s, xmm4s);
buffer.Emit<OpCode::Mov>(xmm6, xmm4);
buffer.Emit<OpCode::CvtFP2FP>(xmm6, xmm4s);
buffer.Emit<OpCode::CvtFP2FP>(xmm6s, xmm4);
// Source: xmm4, target: xmm7
buffer.Emit<OpCode::Mov>(xmm7s, xmm4s);
buffer.Emit<OpCode::Mov>(xmm7, xmm4);
buffer.Emit<OpCode::CvtFP2FP>(xmm7, xmm4s);
buffer.Emit<OpCode::CvtFP2FP>(xmm7s, xmm4);
// Source: xmm4, target: xmm8
buffer.Emit<OpCode::Mov>(xmm8s, xmm4s);
buffer.Emit<OpCode::Mov>(xmm8, xmm4);
buffer.Emit<OpCode::CvtFP2FP>(xmm8, xmm4s);
buffer.Emit<OpCode::CvtFP2FP>(xmm8s, xmm4);
// Source: xmm4, target: xmm9
buffer.Emit<OpCode::Mov>(xmm9s, xmm4s);
buffer.Emit<OpCode::Mov>(xmm9, xmm4);
buffer.Emit<OpCode::CvtFP2FP>(xmm9, xmm4s);
buffer.Emit<OpCode::CvtFP2FP>(xmm9s, xmm4);
// Source: xmm4, target: xmm10
buffer.Emit<OpCode::Mov>(xmm10s, xmm4s);
buffer.Emit<OpCode::Mov>(xmm10, xmm4);
buffer.Emit<OpCode::CvtFP2FP>(xmm10, xmm4s);
buffer.Emit<OpCode::CvtFP2FP>(xmm10s, xmm4);
// Source: xmm4, target: xmm11
buffer.Emit<OpCode::Mov>(xmm11s, xmm4s);
buffer.Emit<OpCode::Mov>(xmm11, xmm4);
buffer.Emit<OpCode::CvtFP2FP>(xmm11, xmm4s);
buffer.Emit<OpCode::CvtFP2FP>(xmm11s, xmm4);
// Source: xmm4, target: xmm12
buffer.Emit<OpCode::Mov>(xmm12s, xmm4s);
buffer.Emit<OpCode::Mov>(xmm12, xmm4);
buffer.Emit<OpCode::CvtFP2FP>(xmm12, xmm4s);
buffer.Emit<OpCode::CvtFP2FP>(xmm12s, xmm4);
// Source: xmm4, target: xmm13
buffer.Emit<OpCode::Mov>(xmm13s, xmm4s);
buffer.Emit<OpCode::Mov>(xmm13, xmm4);
buffer.Emit<OpCode::CvtFP2FP>(xmm13, xmm4s);
buffer.Emit<OpCode::CvtFP2FP>(xmm13s, xmm4);
// Source: xmm4, target: xmm14
buffer.Emit<OpCode::Mov>(xmm14s, xmm4s);
buffer.Emit<OpCode::Mov>(xmm14, xmm4);
buffer.Emit<OpCode::CvtFP2FP>(xmm14, xmm4s);
buffer.Emit<OpCode::CvtFP2FP>(xmm14s, xmm4);
// Source: xmm4, target: xmm15
buffer.Emit<OpCode::Mov>(xmm15s, xmm4s);
buffer.Emit<OpCode::Mov>(xmm15, xmm4);
buffer.Emit<OpCode::CvtFP2FP>(xmm15, xmm4s);
buffer.Emit<OpCode::CvtFP2FP>(xmm15s, xmm4);
// Source: xmm5, target: xmm0
buffer.Emit<OpCode::Mov>(xmm0s, xmm5s);
buffer.Emit<OpCode::Mov>(xmm0, xmm5);
buffer.Emit<OpCode::CvtFP2FP>(xmm0, xmm5s);
buffer.Emit<OpCode::CvtFP2FP>(xmm0s, xmm5);
// Source: xmm5, target: xmm1
buffer.Emit<OpCode::Mov>(xmm1s, xmm5s);
buffer.Emit<OpCode::Mov>(xmm1, xmm5);
buffer.Emit<OpCode::CvtFP2FP>(xmm1, xmm5s);
buffer.Emit<OpCode::CvtFP2FP>(xmm1s, xmm5);
// Source: xmm5, target: xmm2
buffer.Emit<OpCode::Mov>(xmm2s, xmm5s);
buffer.Emit<OpCode::Mov>(xmm2, xmm5);
buffer.Emit<OpCode::CvtFP2FP>(xmm2, xmm5s);
buffer.Emit<OpCode::CvtFP2FP>(xmm2s, xmm5);
// Source: xmm5, target: xmm3
buffer.Emit<OpCode::Mov>(xmm3s, xmm5s);
buffer.Emit<OpCode::Mov>(xmm3, xmm5);
buffer.Emit<OpCode::CvtFP2FP>(xmm3, xmm5s);
buffer.Emit<OpCode::CvtFP2FP>(xmm3s, xmm5);
// Source: xmm5, target: xmm4
buffer.Emit<OpCode::Mov>(xmm4s, xmm5s);
buffer.Emit<OpCode::Mov>(xmm4, xmm5);
buffer.Emit<OpCode::CvtFP2FP>(xmm4, xmm5s);
buffer.Emit<OpCode::CvtFP2FP>(xmm4s, xmm5);
// Source: xmm5, target: xmm5
buffer.Emit<OpCode::Mov>(xmm5s, xmm5s);
buffer.Emit<OpCode::Mov>(xmm5, xmm5);
buffer.Emit<OpCode::CvtFP2FP>(xmm5, xmm5s);
buffer.Emit<OpCode::CvtFP2FP>(xmm5s, xmm5);
// Source: xmm5, target: xmm6
buffer.Emit<OpCode::Mov>(xmm6s, xmm5s);
buffer.Emit<OpCode::Mov>(xmm6, xmm5);
buffer.Emit<OpCode::CvtFP2FP>(xmm6, xmm5s);
buffer.Emit<OpCode::CvtFP2FP>(xmm6s, xmm5);
// Source: xmm5, target: xmm7
buffer.Emit<OpCode::Mov>(xmm7s, xmm5s);
buffer.Emit<OpCode::Mov>(xmm7, xmm5);
buffer.Emit<OpCode::CvtFP2FP>(xmm7, xmm5s);
buffer.Emit<OpCode::CvtFP2FP>(xmm7s, xmm5);
// Source: xmm5, target: xmm8
buffer.Emit<OpCode::Mov>(xmm8s, xmm5s);
buffer.Emit<OpCode::Mov>(xmm8, xmm5);
buffer.Emit<OpCode::CvtFP2FP>(xmm8, xmm5s);
buffer.Emit<OpCode::CvtFP2FP>(xmm8s, xmm5);
// Source: xmm5, target: xmm9
buffer.Emit<OpCode::Mov>(xmm9s, xmm5s);
buffer.Emit<OpCode::Mov>(xmm9, xmm5);
buffer.Emit<OpCode::CvtFP2FP>(xmm9, xmm5s);
buffer.Emit<OpCode::CvtFP2FP>(xmm9s, xmm5);
// Source: xmm5, target: xmm10
buffer.Emit<OpCode::Mov>(xmm10s, xmm5s);
buffer.Emit<OpCode::Mov>(xmm10, xmm5);
buffer.Emit<OpCode::CvtFP2FP>(xmm10, xmm5s);
buffer.Emit<OpCode::CvtFP2FP>(xmm10s, xmm5);
// Source: xmm5, target: xmm11
buffer.Emit<OpCode::Mov>(xmm11s, xmm5s);
buffer.Emit<OpCode::Mov>(xmm11, xmm5);
buffer.Emit<OpCode::CvtFP2FP>(xmm11, xmm5s);
buffer.Emit<OpCode::CvtFP2FP>(xmm11s, xmm5);
// Source: xmm5, target: xmm12
buffer.Emit<OpCode::Mov>(xmm12s, xmm5s);
buffer.Emit<OpCode::Mov>(xmm12, xmm5);
buffer.Emit<OpCode::CvtFP2FP>(xmm12, xmm5s);
buffer.Emit<OpCode::CvtFP2FP>(xmm12s, xmm5);
// Source: xmm5, target: xmm13
buffer.Emit<OpCode::Mov>(xmm13s, xmm5s);
buffer.Emit<OpCode::Mov>(xmm13, xmm5);
buffer.Emit<OpCode::CvtFP2FP>(xmm13, xmm5s);
buffer.Emit<OpCode::CvtFP2FP>(xmm13s, xmm5);
// Source: xmm5, target: xmm14
buffer.Emit<OpCode::Mov>(xmm14s, xmm5s);
buffer.Emit<OpCode::Mov>(xmm14, xmm5);
buffer.Emit<OpCode::CvtFP2FP>(xmm14, xmm5s);
buffer.Emit<OpCode::CvtFP2FP>(xmm14s, xmm5);
// Source: xmm5, target: xmm15
buffer.Emit<OpCode::Mov>(xmm15s, xmm5s);
buffer.Emit<OpCode::Mov>(xmm15, xmm5);
buffer.Emit<OpCode::CvtFP2FP>(xmm15, xmm5s);
buffer.Emit<OpCode::CvtFP2FP>(xmm15s, xmm5);
// Source: xmm6, target: xmm0
buffer.Emit<OpCode::Mov>(xmm0s, xmm6s);
buffer.Emit<OpCode::Mov>(xmm0, xmm6);
buffer.Emit<OpCode::CvtFP2FP>(xmm0, xmm6s);
buffer.Emit<OpCode::CvtFP2FP>(xmm0s, xmm6);
// Source: xmm6, target: xmm1
buffer.Emit<OpCode::Mov>(xmm1s, xmm6s);
buffer.Emit<OpCode::Mov>(xmm1, xmm6);
buffer.Emit<OpCode::CvtFP2FP>(xmm1, xmm6s);
buffer.Emit<OpCode::CvtFP2FP>(xmm1s, xmm6);
// Source: xmm6, target: xmm2
buffer.Emit<OpCode::Mov>(xmm2s, xmm6s);
buffer.Emit<OpCode::Mov>(xmm2, xmm6);
buffer.Emit<OpCode::CvtFP2FP>(xmm2, xmm6s);
buffer.Emit<OpCode::CvtFP2FP>(xmm2s, xmm6);
// Source: xmm6, target: xmm3
buffer.Emit<OpCode::Mov>(xmm3s, xmm6s);
buffer.Emit<OpCode::Mov>(xmm3, xmm6);
buffer.Emit<OpCode::CvtFP2FP>(xmm3, xmm6s);
buffer.Emit<OpCode::CvtFP2FP>(xmm3s, xmm6);
// Source: xmm6, target: xmm4
buffer.Emit<OpCode::Mov>(xmm4s, xmm6s);
buffer.Emit<OpCode::Mov>(xmm4, xmm6);
buffer.Emit<OpCode::CvtFP2FP>(xmm4, xmm6s);
buffer.Emit<OpCode::CvtFP2FP>(xmm4s, xmm6);
// Source: xmm6, target: xmm5
buffer.Emit<OpCode::Mov>(xmm5s, xmm6s);
buffer.Emit<OpCode::Mov>(xmm5, xmm6);
buffer.Emit<OpCode::CvtFP2FP>(xmm5, xmm6s);
buffer.Emit<OpCode::CvtFP2FP>(xmm5s, xmm6);
// Source: xmm6, target: xmm6
buffer.Emit<OpCode::Mov>(xmm6s, xmm6s);
buffer.Emit<OpCode::Mov>(xmm6, xmm6);
buffer.Emit<OpCode::CvtFP2FP>(xmm6, xmm6s);
buffer.Emit<OpCode::CvtFP2FP>(xmm6s, xmm6);
// Source: xmm6, target: xmm7
buffer.Emit<OpCode::Mov>(xmm7s, xmm6s);
buffer.Emit<OpCode::Mov>(xmm7, xmm6);
buffer.Emit<OpCode::CvtFP2FP>(xmm7, xmm6s);
buffer.Emit<OpCode::CvtFP2FP>(xmm7s, xmm6);
// Source: xmm6, target: xmm8
buffer.Emit<OpCode::Mov>(xmm8s, xmm6s);
buffer.Emit<OpCode::Mov>(xmm8, xmm6);
buffer.Emit<OpCode::CvtFP2FP>(xmm8, xmm6s);
buffer.Emit<OpCode::CvtFP2FP>(xmm8s, xmm6);
// Source: xmm6, target: xmm9
buffer.Emit<OpCode::Mov>(xmm9s, xmm6s);
buffer.Emit<OpCode::Mov>(xmm9, xmm6);
buffer.Emit<OpCode::CvtFP2FP>(xmm9, xmm6s);
buffer.Emit<OpCode::CvtFP2FP>(xmm9s, xmm6);
// Source: xmm6, target: xmm10
buffer.Emit<OpCode::Mov>(xmm10s, xmm6s);
buffer.Emit<OpCode::Mov>(xmm10, xmm6);
buffer.Emit<OpCode::CvtFP2FP>(xmm10, xmm6s);
buffer.Emit<OpCode::CvtFP2FP>(xmm10s, xmm6);
// Source: xmm6, target: xmm11
buffer.Emit<OpCode::Mov>(xmm11s, xmm6s);
buffer.Emit<OpCode::Mov>(xmm11, xmm6);
buffer.Emit<OpCode::CvtFP2FP>(xmm11, xmm6s);
buffer.Emit<OpCode::CvtFP2FP>(xmm11s, xmm6);
// Source: xmm6, target: xmm12
buffer.Emit<OpCode::Mov>(xmm12s, xmm6s);
buffer.Emit<OpCode::Mov>(xmm12, xmm6);
buffer.Emit<OpCode::CvtFP2FP>(xmm12, xmm6s);
buffer.Emit<OpCode::CvtFP2FP>(xmm12s, xmm6);
// Source: xmm6, target: xmm13
buffer.Emit<OpCode::Mov>(xmm13s, xmm6s);
buffer.Emit<OpCode::Mov>(xmm13, xmm6);
buffer.Emit<OpCode::CvtFP2FP>(xmm13, xmm6s);
buffer.Emit<OpCode::CvtFP2FP>(xmm13s, xmm6);
// Source: xmm6, target: xmm14
buffer.Emit<OpCode::Mov>(xmm14s, xmm6s);
buffer.Emit<OpCode::Mov>(xmm14, xmm6);
buffer.Emit<OpCode::CvtFP2FP>(xmm14, xmm6s);
buffer.Emit<OpCode::CvtFP2FP>(xmm14s, xmm6);
// Source: xmm6, target: xmm15
buffer.Emit<OpCode::Mov>(xmm15s, xmm6s);
buffer.Emit<OpCode::Mov>(xmm15, xmm6);
buffer.Emit<OpCode::CvtFP2FP>(xmm15, xmm6s);
buffer.Emit<OpCode::CvtFP2FP>(xmm15s, xmm6);
// Source: xmm7, target: xmm0
buffer.Emit<OpCode::Mov>(xmm0s, xmm7s);
buffer.Emit<OpCode::Mov>(xmm0, xmm7);
buffer.Emit<OpCode::CvtFP2FP>(xmm0, xmm7s);
buffer.Emit<OpCode::CvtFP2FP>(xmm0s, xmm7);
// Source: xmm7, target: xmm1
buffer.Emit<OpCode::Mov>(xmm1s, xmm7s);
buffer.Emit<OpCode::Mov>(xmm1, xmm7);
buffer.Emit<OpCode::CvtFP2FP>(xmm1, xmm7s);
buffer.Emit<OpCode::CvtFP2FP>(xmm1s, xmm7);
// Source: xmm7, target: xmm2
buffer.Emit<OpCode::Mov>(xmm2s, xmm7s);
buffer.Emit<OpCode::Mov>(xmm2, xmm7);
buffer.Emit<OpCode::CvtFP2FP>(xmm2, xmm7s);
buffer.Emit<OpCode::CvtFP2FP>(xmm2s, xmm7);
// Source: xmm7, target: xmm3
buffer.Emit<OpCode::Mov>(xmm3s, xmm7s);
buffer.Emit<OpCode::Mov>(xmm3, xmm7);
buffer.Emit<OpCode::CvtFP2FP>(xmm3, xmm7s);
buffer.Emit<OpCode::CvtFP2FP>(xmm3s, xmm7);
// Source: xmm7, target: xmm4
buffer.Emit<OpCode::Mov>(xmm4s, xmm7s);
buffer.Emit<OpCode::Mov>(xmm4, xmm7);
buffer.Emit<OpCode::CvtFP2FP>(xmm4, xmm7s);
buffer.Emit<OpCode::CvtFP2FP>(xmm4s, xmm7);
// Source: xmm7, target: xmm5
buffer.Emit<OpCode::Mov>(xmm5s, xmm7s);
buffer.Emit<OpCode::Mov>(xmm5, xmm7);
buffer.Emit<OpCode::CvtFP2FP>(xmm5, xmm7s);
buffer.Emit<OpCode::CvtFP2FP>(xmm5s, xmm7);
// Source: xmm7, target: xmm6
buffer.Emit<OpCode::Mov>(xmm6s, xmm7s);
buffer.Emit<OpCode::Mov>(xmm6, xmm7);
buffer.Emit<OpCode::CvtFP2FP>(xmm6, xmm7s);
buffer.Emit<OpCode::CvtFP2FP>(xmm6s, xmm7);
// Source: xmm7, target: xmm7
buffer.Emit<OpCode::Mov>(xmm7s, xmm7s);
buffer.Emit<OpCode::Mov>(xmm7, xmm7);
buffer.Emit<OpCode::CvtFP2FP>(xmm7, xmm7s);
buffer.Emit<OpCode::CvtFP2FP>(xmm7s, xmm7);
// Source: xmm7, target: xmm8
buffer.Emit<OpCode::Mov>(xmm8s, xmm7s);
buffer.Emit<OpCode::Mov>(xmm8, xmm7);
buffer.Emit<OpCode::CvtFP2FP>(xmm8, xmm7s);
buffer.Emit<OpCode::CvtFP2FP>(xmm8s, xmm7);
// Source: xmm7, target: xmm9
buffer.Emit<OpCode::Mov>(xmm9s, xmm7s);
buffer.Emit<OpCode::Mov>(xmm9, xmm7);
buffer.Emit<OpCode::CvtFP2FP>(xmm9, xmm7s);
buffer.Emit<OpCode::CvtFP2FP>(xmm9s, xmm7);
// Source: xmm7, target: xmm10
buffer.Emit<OpCode::Mov>(xmm10s, xmm7s);
buffer.Emit<OpCode::Mov>(xmm10, xmm7);
buffer.Emit<OpCode::CvtFP2FP>(xmm10, xmm7s);
buffer.Emit<OpCode::CvtFP2FP>(xmm10s, xmm7);
// Source: xmm7, target: xmm11
buffer.Emit<OpCode::Mov>(xmm11s, xmm7s);
buffer.Emit<OpCode::Mov>(xmm11, xmm7);
buffer.Emit<OpCode::CvtFP2FP>(xmm11, xmm7s);
buffer.Emit<OpCode::CvtFP2FP>(xmm11s, xmm7);
// Source: xmm7, target: xmm12
buffer.Emit<OpCode::Mov>(xmm12s, xmm7s);
buffer.Emit<OpCode::Mov>(xmm12, xmm7);
buffer.Emit<OpCode::CvtFP2FP>(xmm12, xmm7s);
buffer.Emit<OpCode::CvtFP2FP>(xmm12s, xmm7);
// Source: xmm7, target: xmm13
buffer.Emit<OpCode::Mov>(xmm13s, xmm7s);
buffer.Emit<OpCode::Mov>(xmm13, xmm7);
buffer.Emit<OpCode::CvtFP2FP>(xmm13, xmm7s);
buffer.Emit<OpCode::CvtFP2FP>(xmm13s, xmm7);
// Source: xmm7, target: xmm14
buffer.Emit<OpCode::Mov>(xmm14s, xmm7s);
buffer.Emit<OpCode::Mov>(xmm14, xmm7);
buffer.Emit<OpCode::CvtFP2FP>(xmm14, xmm7s);
buffer.Emit<OpCode::CvtFP2FP>(xmm14s, xmm7);
// Source: xmm7, target: xmm15
buffer.Emit<OpCode::Mov>(xmm15s, xmm7s);
buffer.Emit<OpCode::Mov>(xmm15, xmm7);
buffer.Emit<OpCode::CvtFP2FP>(xmm15, xmm7s);
buffer.Emit<OpCode::CvtFP2FP>(xmm15s, xmm7);
// Source: xmm8, target: xmm0
buffer.Emit<OpCode::Mov>(xmm0s, xmm8s);
buffer.Emit<OpCode::Mov>(xmm0, xmm8);
buffer.Emit<OpCode::CvtFP2FP>(xmm0, xmm8s);
buffer.Emit<OpCode::CvtFP2FP>(xmm0s, xmm8);
// Source: xmm8, target: xmm1
buffer.Emit<OpCode::Mov>(xmm1s, xmm8s);
buffer.Emit<OpCode::Mov>(xmm1, xmm8);
buffer.Emit<OpCode::CvtFP2FP>(xmm1, xmm8s);
buffer.Emit<OpCode::CvtFP2FP>(xmm1s, xmm8);
// Source: xmm8, target: xmm2
buffer.Emit<OpCode::Mov>(xmm2s, xmm8s);
buffer.Emit<OpCode::Mov>(xmm2, xmm8);
buffer.Emit<OpCode::CvtFP2FP>(xmm2, xmm8s);
buffer.Emit<OpCode::CvtFP2FP>(xmm2s, xmm8);
// Source: xmm8, target: xmm3
buffer.Emit<OpCode::Mov>(xmm3s, xmm8s);
buffer.Emit<OpCode::Mov>(xmm3, xmm8);
buffer.Emit<OpCode::CvtFP2FP>(xmm3, xmm8s);
buffer.Emit<OpCode::CvtFP2FP>(xmm3s, xmm8);
// Source: xmm8, target: xmm4
buffer.Emit<OpCode::Mov>(xmm4s, xmm8s);
buffer.Emit<OpCode::Mov>(xmm4, xmm8);
buffer.Emit<OpCode::CvtFP2FP>(xmm4, xmm8s);
buffer.Emit<OpCode::CvtFP2FP>(xmm4s, xmm8);
// Source: xmm8, target: xmm5
buffer.Emit<OpCode::Mov>(xmm5s, xmm8s);
buffer.Emit<OpCode::Mov>(xmm5, xmm8);
buffer.Emit<OpCode::CvtFP2FP>(xmm5, xmm8s);
buffer.Emit<OpCode::CvtFP2FP>(xmm5s, xmm8);
// Source: xmm8, target: xmm6
buffer.Emit<OpCode::Mov>(xmm6s, xmm8s);
buffer.Emit<OpCode::Mov>(xmm6, xmm8);
buffer.Emit<OpCode::CvtFP2FP>(xmm6, xmm8s);
buffer.Emit<OpCode::CvtFP2FP>(xmm6s, xmm8);
// Source: xmm8, target: xmm7
buffer.Emit<OpCode::Mov>(xmm7s, xmm8s);
buffer.Emit<OpCode::Mov>(xmm7, xmm8);
buffer.Emit<OpCode::CvtFP2FP>(xmm7, xmm8s);
buffer.Emit<OpCode::CvtFP2FP>(xmm7s, xmm8);
// Source: xmm8, target: xmm8
buffer.Emit<OpCode::Mov>(xmm8s, xmm8s);
buffer.Emit<OpCode::Mov>(xmm8, xmm8);
buffer.Emit<OpCode::CvtFP2FP>(xmm8, xmm8s);
buffer.Emit<OpCode::CvtFP2FP>(xmm8s, xmm8);
// Source: xmm8, target: xmm9
buffer.Emit<OpCode::Mov>(xmm9s, xmm8s);
buffer.Emit<OpCode::Mov>(xmm9, xmm8);
buffer.Emit<OpCode::CvtFP2FP>(xmm9, xmm8s);
buffer.Emit<OpCode::CvtFP2FP>(xmm9s, xmm8);
// Source: xmm8, target: xmm10
buffer.Emit<OpCode::Mov>(xmm10s, xmm8s);
buffer.Emit<OpCode::Mov>(xmm10, xmm8);
buffer.Emit<OpCode::CvtFP2FP>(xmm10, xmm8s);
buffer.Emit<OpCode::CvtFP2FP>(xmm10s, xmm8);
// Source: xmm8, target: xmm11
buffer.Emit<OpCode::Mov>(xmm11s, xmm8s);
buffer.Emit<OpCode::Mov>(xmm11, xmm8);
buffer.Emit<OpCode::CvtFP2FP>(xmm11, xmm8s);
buffer.Emit<OpCode::CvtFP2FP>(xmm11s, xmm8);
// Source: xmm8, target: xmm12
buffer.Emit<OpCode::Mov>(xmm12s, xmm8s);
buffer.Emit<OpCode::Mov>(xmm12, xmm8);
buffer.Emit<OpCode::CvtFP2FP>(xmm12, xmm8s);
buffer.Emit<OpCode::CvtFP2FP>(xmm12s, xmm8);
// Source: xmm8, target: xmm13
buffer.Emit<OpCode::Mov>(xmm13s, xmm8s);
buffer.Emit<OpCode::Mov>(xmm13, xmm8);
buffer.Emit<OpCode::CvtFP2FP>(xmm13, xmm8s);
buffer.Emit<OpCode::CvtFP2FP>(xmm13s, xmm8);
// Source: xmm8, target: xmm14
buffer.Emit<OpCode::Mov>(xmm14s, xmm8s);
buffer.Emit<OpCode::Mov>(xmm14, xmm8);
buffer.Emit<OpCode::CvtFP2FP>(xmm14, xmm8s);
buffer.Emit<OpCode::CvtFP2FP>(xmm14s, xmm8);
// Source: xmm8, target: xmm15
buffer.Emit<OpCode::Mov>(xmm15s, xmm8s);
buffer.Emit<OpCode::Mov>(xmm15, xmm8);
buffer.Emit<OpCode::CvtFP2FP>(xmm15, xmm8s);
buffer.Emit<OpCode::CvtFP2FP>(xmm15s, xmm8);
// Source: xmm9, target: xmm0
buffer.Emit<OpCode::Mov>(xmm0s, xmm9s);
buffer.Emit<OpCode::Mov>(xmm0, xmm9);
buffer.Emit<OpCode::CvtFP2FP>(xmm0, xmm9s);
buffer.Emit<OpCode::CvtFP2FP>(xmm0s, xmm9);
// Source: xmm9, target: xmm1
buffer.Emit<OpCode::Mov>(xmm1s, xmm9s);
buffer.Emit<OpCode::Mov>(xmm1, xmm9);
buffer.Emit<OpCode::CvtFP2FP>(xmm1, xmm9s);
buffer.Emit<OpCode::CvtFP2FP>(xmm1s, xmm9);
// Source: xmm9, target: xmm2
buffer.Emit<OpCode::Mov>(xmm2s, xmm9s);
buffer.Emit<OpCode::Mov>(xmm2, xmm9);
buffer.Emit<OpCode::CvtFP2FP>(xmm2, xmm9s);
buffer.Emit<OpCode::CvtFP2FP>(xmm2s, xmm9);
// Source: xmm9, target: xmm3
buffer.Emit<OpCode::Mov>(xmm3s, xmm9s);
buffer.Emit<OpCode::Mov>(xmm3, xmm9);
buffer.Emit<OpCode::CvtFP2FP>(xmm3, xmm9s);
buffer.Emit<OpCode::CvtFP2FP>(xmm3s, xmm9);
// Source: xmm9, target: xmm4
buffer.Emit<OpCode::Mov>(xmm4s, xmm9s);
buffer.Emit<OpCode::Mov>(xmm4, xmm9);
buffer.Emit<OpCode::CvtFP2FP>(xmm4, xmm9s);
buffer.Emit<OpCode::CvtFP2FP>(xmm4s, xmm9);
// Source: xmm9, target: xmm5
buffer.Emit<OpCode::Mov>(xmm5s, xmm9s);
buffer.Emit<OpCode::Mov>(xmm5, xmm9);
buffer.Emit<OpCode::CvtFP2FP>(xmm5, xmm9s);
buffer.Emit<OpCode::CvtFP2FP>(xmm5s, xmm9);
// Source: xmm9, target: xmm6
buffer.Emit<OpCode::Mov>(xmm6s, xmm9s);
buffer.Emit<OpCode::Mov>(xmm6, xmm9);
buffer.Emit<OpCode::CvtFP2FP>(xmm6, xmm9s);
buffer.Emit<OpCode::CvtFP2FP>(xmm6s, xmm9);
// Source: xmm9, target: xmm7
buffer.Emit<OpCode::Mov>(xmm7s, xmm9s);
buffer.Emit<OpCode::Mov>(xmm7, xmm9);
buffer.Emit<OpCode::CvtFP2FP>(xmm7, xmm9s);
buffer.Emit<OpCode::CvtFP2FP>(xmm7s, xmm9);
// Source: xmm9, target: xmm8
buffer.Emit<OpCode::Mov>(xmm8s, xmm9s);
buffer.Emit<OpCode::Mov>(xmm8, xmm9);
buffer.Emit<OpCode::CvtFP2FP>(xmm8, xmm9s);
buffer.Emit<OpCode::CvtFP2FP>(xmm8s, xmm9);
// Source: xmm9, target: xmm9
buffer.Emit<OpCode::Mov>(xmm9s, xmm9s);
buffer.Emit<OpCode::Mov>(xmm9, xmm9);
buffer.Emit<OpCode::CvtFP2FP>(xmm9, xmm9s);
buffer.Emit<OpCode::CvtFP2FP>(xmm9s, xmm9);
// Source: xmm9, target: xmm10
buffer.Emit<OpCode::Mov>(xmm10s, xmm9s);
buffer.Emit<OpCode::Mov>(xmm10, xmm9);
buffer.Emit<OpCode::CvtFP2FP>(xmm10, xmm9s);
buffer.Emit<OpCode::CvtFP2FP>(xmm10s, xmm9);
// Source: xmm9, target: xmm11
buffer.Emit<OpCode::Mov>(xmm11s, xmm9s);
buffer.Emit<OpCode::Mov>(xmm11, xmm9);
buffer.Emit<OpCode::CvtFP2FP>(xmm11, xmm9s);
buffer.Emit<OpCode::CvtFP2FP>(xmm11s, xmm9);
// Source: xmm9, target: xmm12
buffer.Emit<OpCode::Mov>(xmm12s, xmm9s);
buffer.Emit<OpCode::Mov>(xmm12, xmm9);
buffer.Emit<OpCode::CvtFP2FP>(xmm12, xmm9s);
buffer.Emit<OpCode::CvtFP2FP>(xmm12s, xmm9);
// Source: xmm9, target: xmm13
buffer.Emit<OpCode::Mov>(xmm13s, xmm9s);
buffer.Emit<OpCode::Mov>(xmm13, xmm9);
buffer.Emit<OpCode::CvtFP2FP>(xmm13, xmm9s);
buffer.Emit<OpCode::CvtFP2FP>(xmm13s, xmm9);
// Source: xmm9, target: xmm14
buffer.Emit<OpCode::Mov>(xmm14s, xmm9s);
buffer.Emit<OpCode::Mov>(xmm14, xmm9);
buffer.Emit<OpCode::CvtFP2FP>(xmm14, xmm9s);
buffer.Emit<OpCode::CvtFP2FP>(xmm14s, xmm9);
// Source: xmm9, target: xmm15
buffer.Emit<OpCode::Mov>(xmm15s, xmm9s);
buffer.Emit<OpCode::Mov>(xmm15, xmm9);
buffer.Emit<OpCode::CvtFP2FP>(xmm15, xmm9s);
buffer.Emit<OpCode::CvtFP2FP>(xmm15s, xmm9);
// Source: xmm10, target: xmm0
buffer.Emit<OpCode::Mov>(xmm0s, xmm10s);
buffer.Emit<OpCode::Mov>(xmm0, xmm10);
buffer.Emit<OpCode::CvtFP2FP>(xmm0, xmm10s);
buffer.Emit<OpCode::CvtFP2FP>(xmm0s, xmm10);
// Source: xmm10, target: xmm1
buffer.Emit<OpCode::Mov>(xmm1s, xmm10s);
buffer.Emit<OpCode::Mov>(xmm1, xmm10);
buffer.Emit<OpCode::CvtFP2FP>(xmm1, xmm10s);
buffer.Emit<OpCode::CvtFP2FP>(xmm1s, xmm10);
// Source: xmm10, target: xmm2
buffer.Emit<OpCode::Mov>(xmm2s, xmm10s);
buffer.Emit<OpCode::Mov>(xmm2, xmm10);
buffer.Emit<OpCode::CvtFP2FP>(xmm2, xmm10s);
buffer.Emit<OpCode::CvtFP2FP>(xmm2s, xmm10);
// Source: xmm10, target: xmm3
buffer.Emit<OpCode::Mov>(xmm3s, xmm10s);
buffer.Emit<OpCode::Mov>(xmm3, xmm10);
buffer.Emit<OpCode::CvtFP2FP>(xmm3, xmm10s);
buffer.Emit<OpCode::CvtFP2FP>(xmm3s, xmm10);
// Source: xmm10, target: xmm4
buffer.Emit<OpCode::Mov>(xmm4s, xmm10s);
buffer.Emit<OpCode::Mov>(xmm4, xmm10);
buffer.Emit<OpCode::CvtFP2FP>(xmm4, xmm10s);
buffer.Emit<OpCode::CvtFP2FP>(xmm4s, xmm10);
// Source: xmm10, target: xmm5
buffer.Emit<OpCode::Mov>(xmm5s, xmm10s);
buffer.Emit<OpCode::Mov>(xmm5, xmm10);
buffer.Emit<OpCode::CvtFP2FP>(xmm5, xmm10s);
buffer.Emit<OpCode::CvtFP2FP>(xmm5s, xmm10);
// Source: xmm10, target: xmm6
buffer.Emit<OpCode::Mov>(xmm6s, xmm10s);
buffer.Emit<OpCode::Mov>(xmm6, xmm10);
buffer.Emit<OpCode::CvtFP2FP>(xmm6, xmm10s);
buffer.Emit<OpCode::CvtFP2FP>(xmm6s, xmm10);
// Source: xmm10, target: xmm7
buffer.Emit<OpCode::Mov>(xmm7s, xmm10s);
buffer.Emit<OpCode::Mov>(xmm7, xmm10);
buffer.Emit<OpCode::CvtFP2FP>(xmm7, xmm10s);
buffer.Emit<OpCode::CvtFP2FP>(xmm7s, xmm10);
// Source: xmm10, target: xmm8
buffer.Emit<OpCode::Mov>(xmm8s, xmm10s);
buffer.Emit<OpCode::Mov>(xmm8, xmm10);
buffer.Emit<OpCode::CvtFP2FP>(xmm8, xmm10s);
buffer.Emit<OpCode::CvtFP2FP>(xmm8s, xmm10);
// Source: xmm10, target: xmm9
buffer.Emit<OpCode::Mov>(xmm9s, xmm10s);
buffer.Emit<OpCode::Mov>(xmm9, xmm10);
buffer.Emit<OpCode::CvtFP2FP>(xmm9, xmm10s);
buffer.Emit<OpCode::CvtFP2FP>(xmm9s, xmm10);
// Source: xmm10, target: xmm10
buffer.Emit<OpCode::Mov>(xmm10s, xmm10s);
buffer.Emit<OpCode::Mov>(xmm10, xmm10);
buffer.Emit<OpCode::CvtFP2FP>(xmm10, xmm10s);
buffer.Emit<OpCode::CvtFP2FP>(xmm10s, xmm10);
// Source: xmm10, target: xmm11
buffer.Emit<OpCode::Mov>(xmm11s, xmm10s);
buffer.Emit<OpCode::Mov>(xmm11, xmm10);
buffer.Emit<OpCode::CvtFP2FP>(xmm11, xmm10s);
buffer.Emit<OpCode::CvtFP2FP>(xmm11s, xmm10);
// Source: xmm10, target: xmm12
buffer.Emit<OpCode::Mov>(xmm12s, xmm10s);
buffer.Emit<OpCode::Mov>(xmm12, xmm10);
buffer.Emit<OpCode::CvtFP2FP>(xmm12, xmm10s);
buffer.Emit<OpCode::CvtFP2FP>(xmm12s, xmm10);
// Source: xmm10, target: xmm13
buffer.Emit<OpCode::Mov>(xmm13s, xmm10s);
buffer.Emit<OpCode::Mov>(xmm13, xmm10);
buffer.Emit<OpCode::CvtFP2FP>(xmm13, xmm10s);
buffer.Emit<OpCode::CvtFP2FP>(xmm13s, xmm10);
// Source: xmm10, target: xmm14
buffer.Emit<OpCode::Mov>(xmm14s, xmm10s);
buffer.Emit<OpCode::Mov>(xmm14, xmm10);
buffer.Emit<OpCode::CvtFP2FP>(xmm14, xmm10s);
buffer.Emit<OpCode::CvtFP2FP>(xmm14s, xmm10);
// Source: xmm10, target: xmm15
buffer.Emit<OpCode::Mov>(xmm15s, xmm10s);
buffer.Emit<OpCode::Mov>(xmm15, xmm10);
buffer.Emit<OpCode::CvtFP2FP>(xmm15, xmm10s);
buffer.Emit<OpCode::CvtFP2FP>(xmm15s, xmm10);
// Source: xmm11, target: xmm0
buffer.Emit<OpCode::Mov>(xmm0s, xmm11s);
buffer.Emit<OpCode::Mov>(xmm0, xmm11);
buffer.Emit<OpCode::CvtFP2FP>(xmm0, xmm11s);
buffer.Emit<OpCode::CvtFP2FP>(xmm0s, xmm11);
// Source: xmm11, target: xmm1
buffer.Emit<OpCode::Mov>(xmm1s, xmm11s);
buffer.Emit<OpCode::Mov>(xmm1, xmm11);
buffer.Emit<OpCode::CvtFP2FP>(xmm1, xmm11s);
buffer.Emit<OpCode::CvtFP2FP>(xmm1s, xmm11);
// Source: xmm11, target: xmm2
buffer.Emit<OpCode::Mov>(xmm2s, xmm11s);
buffer.Emit<OpCode::Mov>(xmm2, xmm11);
buffer.Emit<OpCode::CvtFP2FP>(xmm2, xmm11s);
buffer.Emit<OpCode::CvtFP2FP>(xmm2s, xmm11);
// Source: xmm11, target: xmm3
buffer.Emit<OpCode::Mov>(xmm3s, xmm11s);
buffer.Emit<OpCode::Mov>(xmm3, xmm11);
buffer.Emit<OpCode::CvtFP2FP>(xmm3, xmm11s);
buffer.Emit<OpCode::CvtFP2FP>(xmm3s, xmm11);
// Source: xmm11, target: xmm4
buffer.Emit<OpCode::Mov>(xmm4s, xmm11s);
buffer.Emit<OpCode::Mov>(xmm4, xmm11);
buffer.Emit<OpCode::CvtFP2FP>(xmm4, xmm11s);
buffer.Emit<OpCode::CvtFP2FP>(xmm4s, xmm11);
// Source: xmm11, target: xmm5
buffer.Emit<OpCode::Mov>(xmm5s, xmm11s);
buffer.Emit<OpCode::Mov>(xmm5, xmm11);
buffer.Emit<OpCode::CvtFP2FP>(xmm5, xmm11s);
buffer.Emit<OpCode::CvtFP2FP>(xmm5s, xmm11);
// Source: xmm11, target: xmm6
buffer.Emit<OpCode::Mov>(xmm6s, xmm11s);
buffer.Emit<OpCode::Mov>(xmm6, xmm11);
buffer.Emit<OpCode::CvtFP2FP>(xmm6, xmm11s);
buffer.Emit<OpCode::CvtFP2FP>(xmm6s, xmm11);
// Source: xmm11, target: xmm7
buffer.Emit<OpCode::Mov>(xmm7s, xmm11s);
buffer.Emit<OpCode::Mov>(xmm7, xmm11);
buffer.Emit<OpCode::CvtFP2FP>(xmm7, xmm11s);
buffer.Emit<OpCode::CvtFP2FP>(xmm7s, xmm11);
// Source: xmm11, target: xmm8
buffer.Emit<OpCode::Mov>(xmm8s, xmm11s);
buffer.Emit<OpCode::Mov>(xmm8, xmm11);
buffer.Emit<OpCode::CvtFP2FP>(xmm8, xmm11s);
buffer.Emit<OpCode::CvtFP2FP>(xmm8s, xmm11);
// Source: xmm11, target: xmm9
buffer.Emit<OpCode::Mov>(xmm9s, xmm11s);
buffer.Emit<OpCode::Mov>(xmm9, xmm11);
buffer.Emit<OpCode::CvtFP2FP>(xmm9, xmm11s);
buffer.Emit<OpCode::CvtFP2FP>(xmm9s, xmm11);
// Source: xmm11, target: xmm10
buffer.Emit<OpCode::Mov>(xmm10s, xmm11s);
buffer.Emit<OpCode::Mov>(xmm10, xmm11);
buffer.Emit<OpCode::CvtFP2FP>(xmm10, xmm11s);
buffer.Emit<OpCode::CvtFP2FP>(xmm10s, xmm11);
// Source: xmm11, target: xmm11
buffer.Emit<OpCode::Mov>(xmm11s, xmm11s);
buffer.Emit<OpCode::Mov>(xmm11, xmm11);
buffer.Emit<OpCode::CvtFP2FP>(xmm11, xmm11s);
buffer.Emit<OpCode::CvtFP2FP>(xmm11s, xmm11);
// Source: xmm11, target: xmm12
buffer.Emit<OpCode::Mov>(xmm12s, xmm11s);
buffer.Emit<OpCode::Mov>(xmm12, xmm11);
buffer.Emit<OpCode::CvtFP2FP>(xmm12, xmm11s);
buffer.Emit<OpCode::CvtFP2FP>(xmm12s, xmm11);
// Source: xmm11, target: xmm13
buffer.Emit<OpCode::Mov>(xmm13s, xmm11s);
buffer.Emit<OpCode::Mov>(xmm13, xmm11);
buffer.Emit<OpCode::CvtFP2FP>(xmm13, xmm11s);
buffer.Emit<OpCode::CvtFP2FP>(xmm13s, xmm11);
// Source: xmm11, target: xmm14
buffer.Emit<OpCode::Mov>(xmm14s, xmm11s);
buffer.Emit<OpCode::Mov>(xmm14, xmm11);
buffer.Emit<OpCode::CvtFP2FP>(xmm14, xmm11s);
buffer.Emit<OpCode::CvtFP2FP>(xmm14s, xmm11);
// Source: xmm11, target: xmm15
buffer.Emit<OpCode::Mov>(xmm15s, xmm11s);
buffer.Emit<OpCode::Mov>(xmm15, xmm11);
buffer.Emit<OpCode::CvtFP2FP>(xmm15, xmm11s);
buffer.Emit<OpCode::CvtFP2FP>(xmm15s, xmm11);
// Source: xmm12, target: xmm0
buffer.Emit<OpCode::Mov>(xmm0s, xmm12s);
buffer.Emit<OpCode::Mov>(xmm0, xmm12);
buffer.Emit<OpCode::CvtFP2FP>(xmm0, xmm12s);
buffer.Emit<OpCode::CvtFP2FP>(xmm0s, xmm12);
// Source: xmm12, target: xmm1
buffer.Emit<OpCode::Mov>(xmm1s, xmm12s);
buffer.Emit<OpCode::Mov>(xmm1, xmm12);
buffer.Emit<OpCode::CvtFP2FP>(xmm1, xmm12s);
buffer.Emit<OpCode::CvtFP2FP>(xmm1s, xmm12);
// Source: xmm12, target: xmm2
buffer.Emit<OpCode::Mov>(xmm2s, xmm12s);
buffer.Emit<OpCode::Mov>(xmm2, xmm12);
buffer.Emit<OpCode::CvtFP2FP>(xmm2, xmm12s);
buffer.Emit<OpCode::CvtFP2FP>(xmm2s, xmm12);
// Source: xmm12, target: xmm3
buffer.Emit<OpCode::Mov>(xmm3s, xmm12s);
buffer.Emit<OpCode::Mov>(xmm3, xmm12);
buffer.Emit<OpCode::CvtFP2FP>(xmm3, xmm12s);
buffer.Emit<OpCode::CvtFP2FP>(xmm3s, xmm12);
// Source: xmm12, target: xmm4
buffer.Emit<OpCode::Mov>(xmm4s, xmm12s);
buffer.Emit<OpCode::Mov>(xmm4, xmm12);
buffer.Emit<OpCode::CvtFP2FP>(xmm4, xmm12s);
buffer.Emit<OpCode::CvtFP2FP>(xmm4s, xmm12);
// Source: xmm12, target: xmm5
buffer.Emit<OpCode::Mov>(xmm5s, xmm12s);
buffer.Emit<OpCode::Mov>(xmm5, xmm12);
buffer.Emit<OpCode::CvtFP2FP>(xmm5, xmm12s);
buffer.Emit<OpCode::CvtFP2FP>(xmm5s, xmm12);
// Source: xmm12, target: xmm6
buffer.Emit<OpCode::Mov>(xmm6s, xmm12s);
buffer.Emit<OpCode::Mov>(xmm6, xmm12);
buffer.Emit<OpCode::CvtFP2FP>(xmm6, xmm12s);
buffer.Emit<OpCode::CvtFP2FP>(xmm6s, xmm12);
// Source: xmm12, target: xmm7
buffer.Emit<OpCode::Mov>(xmm7s, xmm12s);
buffer.Emit<OpCode::Mov>(xmm7, xmm12);
buffer.Emit<OpCode::CvtFP2FP>(xmm7, xmm12s);
buffer.Emit<OpCode::CvtFP2FP>(xmm7s, xmm12);
// Source: xmm12, target: xmm8
buffer.Emit<OpCode::Mov>(xmm8s, xmm12s);
buffer.Emit<OpCode::Mov>(xmm8, xmm12);
buffer.Emit<OpCode::CvtFP2FP>(xmm8, xmm12s);
buffer.Emit<OpCode::CvtFP2FP>(xmm8s, xmm12);
// Source: xmm12, target: xmm9
buffer.Emit<OpCode::Mov>(xmm9s, xmm12s);
buffer.Emit<OpCode::Mov>(xmm9, xmm12);
buffer.Emit<OpCode::CvtFP2FP>(xmm9, xmm12s);
buffer.Emit<OpCode::CvtFP2FP>(xmm9s, xmm12);
// Source: xmm12, target: xmm10
buffer.Emit<OpCode::Mov>(xmm10s, xmm12s);
buffer.Emit<OpCode::Mov>(xmm10, xmm12);
buffer.Emit<OpCode::CvtFP2FP>(xmm10, xmm12s);
buffer.Emit<OpCode::CvtFP2FP>(xmm10s, xmm12);
// Source: xmm12, target: xmm11
buffer.Emit<OpCode::Mov>(xmm11s, xmm12s);
buffer.Emit<OpCode::Mov>(xmm11, xmm12);
buffer.Emit<OpCode::CvtFP2FP>(xmm11, xmm12s);
buffer.Emit<OpCode::CvtFP2FP>(xmm11s, xmm12);
// Source: xmm12, target: xmm12
buffer.Emit<OpCode::Mov>(xmm12s, xmm12s);
buffer.Emit<OpCode::Mov>(xmm12, xmm12);
buffer.Emit<OpCode::CvtFP2FP>(xmm12, xmm12s);
buffer.Emit<OpCode::CvtFP2FP>(xmm12s, xmm12);
// Source: xmm12, target: xmm13
buffer.Emit<OpCode::Mov>(xmm13s, xmm12s);
buffer.Emit<OpCode::Mov>(xmm13, xmm12);
buffer.Emit<OpCode::CvtFP2FP>(xmm13, xmm12s);
buffer.Emit<OpCode::CvtFP2FP>(xmm13s, xmm12);
// Source: xmm12, target: xmm14
buffer.Emit<OpCode::Mov>(xmm14s, xmm12s);
buffer.Emit<OpCode::Mov>(xmm14, xmm12);
buffer.Emit<OpCode::CvtFP2FP>(xmm14, xmm12s);
buffer.Emit<OpCode::CvtFP2FP>(xmm14s, xmm12);
// Source: xmm12, target: xmm15
buffer.Emit<OpCode::Mov>(xmm15s, xmm12s);
buffer.Emit<OpCode::Mov>(xmm15, xmm12);
buffer.Emit<OpCode::CvtFP2FP>(xmm15, xmm12s);
buffer.Emit<OpCode::CvtFP2FP>(xmm15s, xmm12);
// Source: xmm13, target: xmm0
buffer.Emit<OpCode::Mov>(xmm0s, xmm13s);
buffer.Emit<OpCode::Mov>(xmm0, xmm13);
buffer.Emit<OpCode::CvtFP2FP>(xmm0, xmm13s);
buffer.Emit<OpCode::CvtFP2FP>(xmm0s, xmm13);
// Source: xmm13, target: xmm1
buffer.Emit<OpCode::Mov>(xmm1s, xmm13s);
buffer.Emit<OpCode::Mov>(xmm1, xmm13);
buffer.Emit<OpCode::CvtFP2FP>(xmm1, xmm13s);
buffer.Emit<OpCode::CvtFP2FP>(xmm1s, xmm13);
// Source: xmm13, target: xmm2
buffer.Emit<OpCode::Mov>(xmm2s, xmm13s);
buffer.Emit<OpCode::Mov>(xmm2, xmm13);
buffer.Emit<OpCode::CvtFP2FP>(xmm2, xmm13s);
buffer.Emit<OpCode::CvtFP2FP>(xmm2s, xmm13);
// Source: xmm13, target: xmm3
buffer.Emit<OpCode::Mov>(xmm3s, xmm13s);
buffer.Emit<OpCode::Mov>(xmm3, xmm13);
buffer.Emit<OpCode::CvtFP2FP>(xmm3, xmm13s);
buffer.Emit<OpCode::CvtFP2FP>(xmm3s, xmm13);
// Source: xmm13, target: xmm4
buffer.Emit<OpCode::Mov>(xmm4s, xmm13s);
buffer.Emit<OpCode::Mov>(xmm4, xmm13);
buffer.Emit<OpCode::CvtFP2FP>(xmm4, xmm13s);
buffer.Emit<OpCode::CvtFP2FP>(xmm4s, xmm13);
// Source: xmm13, target: xmm5
buffer.Emit<OpCode::Mov>(xmm5s, xmm13s);
buffer.Emit<OpCode::Mov>(xmm5, xmm13);
buffer.Emit<OpCode::CvtFP2FP>(xmm5, xmm13s);
buffer.Emit<OpCode::CvtFP2FP>(xmm5s, xmm13);
// Source: xmm13, target: xmm6
buffer.Emit<OpCode::Mov>(xmm6s, xmm13s);
buffer.Emit<OpCode::Mov>(xmm6, xmm13);
buffer.Emit<OpCode::CvtFP2FP>(xmm6, xmm13s);
buffer.Emit<OpCode::CvtFP2FP>(xmm6s, xmm13);
// Source: xmm13, target: xmm7
buffer.Emit<OpCode::Mov>(xmm7s, xmm13s);
buffer.Emit<OpCode::Mov>(xmm7, xmm13);
buffer.Emit<OpCode::CvtFP2FP>(xmm7, xmm13s);
buffer.Emit<OpCode::CvtFP2FP>(xmm7s, xmm13);
// Source: xmm13, target: xmm8
buffer.Emit<OpCode::Mov>(xmm8s, xmm13s);
buffer.Emit<OpCode::Mov>(xmm8, xmm13);
buffer.Emit<OpCode::CvtFP2FP>(xmm8, xmm13s);
buffer.Emit<OpCode::CvtFP2FP>(xmm8s, xmm13);
// Source: xmm13, target: xmm9
buffer.Emit<OpCode::Mov>(xmm9s, xmm13s);
buffer.Emit<OpCode::Mov>(xmm9, xmm13);
buffer.Emit<OpCode::CvtFP2FP>(xmm9, xmm13s);
buffer.Emit<OpCode::CvtFP2FP>(xmm9s, xmm13);
// Source: xmm13, target: xmm10
buffer.Emit<OpCode::Mov>(xmm10s, xmm13s);
buffer.Emit<OpCode::Mov>(xmm10, xmm13);
buffer.Emit<OpCode::CvtFP2FP>(xmm10, xmm13s);
buffer.Emit<OpCode::CvtFP2FP>(xmm10s, xmm13);
// Source: xmm13, target: xmm11
buffer.Emit<OpCode::Mov>(xmm11s, xmm13s);
buffer.Emit<OpCode::Mov>(xmm11, xmm13);
buffer.Emit<OpCode::CvtFP2FP>(xmm11, xmm13s);
buffer.Emit<OpCode::CvtFP2FP>(xmm11s, xmm13);
// Source: xmm13, target: xmm12
buffer.Emit<OpCode::Mov>(xmm12s, xmm13s);
buffer.Emit<OpCode::Mov>(xmm12, xmm13);
buffer.Emit<OpCode::CvtFP2FP>(xmm12, xmm13s);
buffer.Emit<OpCode::CvtFP2FP>(xmm12s, xmm13);
// Source: xmm13, target: xmm13
buffer.Emit<OpCode::Mov>(xmm13s, xmm13s);
buffer.Emit<OpCode::Mov>(xmm13, xmm13);
buffer.Emit<OpCode::CvtFP2FP>(xmm13, xmm13s);
buffer.Emit<OpCode::CvtFP2FP>(xmm13s, xmm13);
// Source: xmm13, target: xmm14
buffer.Emit<OpCode::Mov>(xmm14s, xmm13s);
buffer.Emit<OpCode::Mov>(xmm14, xmm13);
buffer.Emit<OpCode::CvtFP2FP>(xmm14, xmm13s);
buffer.Emit<OpCode::CvtFP2FP>(xmm14s, xmm13);
// Source: xmm13, target: xmm15
buffer.Emit<OpCode::Mov>(xmm15s, xmm13s);
buffer.Emit<OpCode::Mov>(xmm15, xmm13);
buffer.Emit<OpCode::CvtFP2FP>(xmm15, xmm13s);
buffer.Emit<OpCode::CvtFP2FP>(xmm15s, xmm13);
// Source: xmm14, target: xmm0
buffer.Emit<OpCode::Mov>(xmm0s, xmm14s);
buffer.Emit<OpCode::Mov>(xmm0, xmm14);
buffer.Emit<OpCode::CvtFP2FP>(xmm0, xmm14s);
buffer.Emit<OpCode::CvtFP2FP>(xmm0s, xmm14);
// Source: xmm14, target: xmm1
buffer.Emit<OpCode::Mov>(xmm1s, xmm14s);
buffer.Emit<OpCode::Mov>(xmm1, xmm14);
buffer.Emit<OpCode::CvtFP2FP>(xmm1, xmm14s);
buffer.Emit<OpCode::CvtFP2FP>(xmm1s, xmm14);
// Source: xmm14, target: xmm2
buffer.Emit<OpCode::Mov>(xmm2s, xmm14s);
buffer.Emit<OpCode::Mov>(xmm2, xmm14);
buffer.Emit<OpCode::CvtFP2FP>(xmm2, xmm14s);
buffer.Emit<OpCode::CvtFP2FP>(xmm2s, xmm14);
// Source: xmm14, target: xmm3
buffer.Emit<OpCode::Mov>(xmm3s, xmm14s);
buffer.Emit<OpCode::Mov>(xmm3, xmm14);
buffer.Emit<OpCode::CvtFP2FP>(xmm3, xmm14s);
buffer.Emit<OpCode::CvtFP2FP>(xmm3s, xmm14);
// Source: xmm14, target: xmm4
buffer.Emit<OpCode::Mov>(xmm4s, xmm14s);
buffer.Emit<OpCode::Mov>(xmm4, xmm14);
buffer.Emit<OpCode::CvtFP2FP>(xmm4, xmm14s);
buffer.Emit<OpCode::CvtFP2FP>(xmm4s, xmm14);
// Source: xmm14, target: xmm5
buffer.Emit<OpCode::Mov>(xmm5s, xmm14s);
buffer.Emit<OpCode::Mov>(xmm5, xmm14);
buffer.Emit<OpCode::CvtFP2FP>(xmm5, xmm14s);
buffer.Emit<OpCode::CvtFP2FP>(xmm5s, xmm14);
// Source: xmm14, target: xmm6
buffer.Emit<OpCode::Mov>(xmm6s, xmm14s);
buffer.Emit<OpCode::Mov>(xmm6, xmm14);
buffer.Emit<OpCode::CvtFP2FP>(xmm6, xmm14s);
buffer.Emit<OpCode::CvtFP2FP>(xmm6s, xmm14);
// Source: xmm14, target: xmm7
buffer.Emit<OpCode::Mov>(xmm7s, xmm14s);
buffer.Emit<OpCode::Mov>(xmm7, xmm14);
buffer.Emit<OpCode::CvtFP2FP>(xmm7, xmm14s);
buffer.Emit<OpCode::CvtFP2FP>(xmm7s, xmm14);
// Source: xmm14, target: xmm8
buffer.Emit<OpCode::Mov>(xmm8s, xmm14s);
buffer.Emit<OpCode::Mov>(xmm8, xmm14);
buffer.Emit<OpCode::CvtFP2FP>(xmm8, xmm14s);
buffer.Emit<OpCode::CvtFP2FP>(xmm8s, xmm14);
// Source: xmm14, target: xmm9
buffer.Emit<OpCode::Mov>(xmm9s, xmm14s);
buffer.Emit<OpCode::Mov>(xmm9, xmm14);
buffer.Emit<OpCode::CvtFP2FP>(xmm9, xmm14s);
buffer.Emit<OpCode::CvtFP2FP>(xmm9s, xmm14);
// Source: xmm14, target: xmm10
buffer.Emit<OpCode::Mov>(xmm10s, xmm14s);
buffer.Emit<OpCode::Mov>(xmm10, xmm14);
buffer.Emit<OpCode::CvtFP2FP>(xmm10, xmm14s);
buffer.Emit<OpCode::CvtFP2FP>(xmm10s, xmm14);
// Source: xmm14, target: xmm11
buffer.Emit<OpCode::Mov>(xmm11s, xmm14s);
buffer.Emit<OpCode::Mov>(xmm11, xmm14);
buffer.Emit<OpCode::CvtFP2FP>(xmm11, xmm14s);
buffer.Emit<OpCode::CvtFP2FP>(xmm11s, xmm14);
// Source: xmm14, target: xmm12
buffer.Emit<OpCode::Mov>(xmm12s, xmm14s);
buffer.Emit<OpCode::Mov>(xmm12, xmm14);
buffer.Emit<OpCode::CvtFP2FP>(xmm12, xmm14s);
buffer.Emit<OpCode::CvtFP2FP>(xmm12s, xmm14);
// Source: xmm14, target: xmm13
buffer.Emit<OpCode::Mov>(xmm13s, xmm14s);
buffer.Emit<OpCode::Mov>(xmm13, xmm14);
buffer.Emit<OpCode::CvtFP2FP>(xmm13, xmm14s);
buffer.Emit<OpCode::CvtFP2FP>(xmm13s, xmm14);
// Source: xmm14, target: xmm14
buffer.Emit<OpCode::Mov>(xmm14s, xmm14s);
buffer.Emit<OpCode::Mov>(xmm14, xmm14);
buffer.Emit<OpCode::CvtFP2FP>(xmm14, xmm14s);
buffer.Emit<OpCode::CvtFP2FP>(xmm14s, xmm14);
// Source: xmm14, target: xmm15
buffer.Emit<OpCode::Mov>(xmm15s, xmm14s);
buffer.Emit<OpCode::Mov>(xmm15, xmm14);
buffer.Emit<OpCode::CvtFP2FP>(xmm15, xmm14s);
buffer.Emit<OpCode::CvtFP2FP>(xmm15s, xmm14);
// Source: xmm15, target: xmm0
buffer.Emit<OpCode::Mov>(xmm0s, xmm15s);
buffer.Emit<OpCode::Mov>(xmm0, xmm15);
buffer.Emit<OpCode::CvtFP2FP>(xmm0, xmm15s);
buffer.Emit<OpCode::CvtFP2FP>(xmm0s, xmm15);
// Source: xmm15, target: xmm1
buffer.Emit<OpCode::Mov>(xmm1s, xmm15s);
buffer.Emit<OpCode::Mov>(xmm1, xmm15);
buffer.Emit<OpCode::CvtFP2FP>(xmm1, xmm15s);
buffer.Emit<OpCode::CvtFP2FP>(xmm1s, xmm15);
// Source: xmm15, target: xmm2
buffer.Emit<OpCode::Mov>(xmm2s, xmm15s);
buffer.Emit<OpCode::Mov>(xmm2, xmm15);
buffer.Emit<OpCode::CvtFP2FP>(xmm2, xmm15s);
buffer.Emit<OpCode::CvtFP2FP>(xmm2s, xmm15);
// Source: xmm15, target: xmm3
buffer.Emit<OpCode::Mov>(xmm3s, xmm15s);
buffer.Emit<OpCode::Mov>(xmm3, xmm15);
buffer.Emit<OpCode::CvtFP2FP>(xmm3, xmm15s);
buffer.Emit<OpCode::CvtFP2FP>(xmm3s, xmm15);
// Source: xmm15, target: xmm4
buffer.Emit<OpCode::Mov>(xmm4s, xmm15s);
buffer.Emit<OpCode::Mov>(xmm4, xmm15);
buffer.Emit<OpCode::CvtFP2FP>(xmm4, xmm15s);
buffer.Emit<OpCode::CvtFP2FP>(xmm4s, xmm15);
// Source: xmm15, target: xmm5
buffer.Emit<OpCode::Mov>(xmm5s, xmm15s);
buffer.Emit<OpCode::Mov>(xmm5, xmm15);
buffer.Emit<OpCode::CvtFP2FP>(xmm5, xmm15s);
buffer.Emit<OpCode::CvtFP2FP>(xmm5s, xmm15);
// Source: xmm15, target: xmm6
buffer.Emit<OpCode::Mov>(xmm6s, xmm15s);
buffer.Emit<OpCode::Mov>(xmm6, xmm15);
buffer.Emit<OpCode::CvtFP2FP>(xmm6, xmm15s);
buffer.Emit<OpCode::CvtFP2FP>(xmm6s, xmm15);
// Source: xmm15, target: xmm7
buffer.Emit<OpCode::Mov>(xmm7s, xmm15s);
buffer.Emit<OpCode::Mov>(xmm7, xmm15);
buffer.Emit<OpCode::CvtFP2FP>(xmm7, xmm15s);
buffer.Emit<OpCode::CvtFP2FP>(xmm7s, xmm15);
// Source: xmm15, target: xmm8
buffer.Emit<OpCode::Mov>(xmm8s, xmm15s);
buffer.Emit<OpCode::Mov>(xmm8, xmm15);
buffer.Emit<OpCode::CvtFP2FP>(xmm8, xmm15s);
buffer.Emit<OpCode::CvtFP2FP>(xmm8s, xmm15);
// Source: xmm15, target: xmm9
buffer.Emit<OpCode::Mov>(xmm9s, xmm15s);
buffer.Emit<OpCode::Mov>(xmm9, xmm15);
buffer.Emit<OpCode::CvtFP2FP>(xmm9, xmm15s);
buffer.Emit<OpCode::CvtFP2FP>(xmm9s, xmm15);
// Source: xmm15, target: xmm10
buffer.Emit<OpCode::Mov>(xmm10s, xmm15s);
buffer.Emit<OpCode::Mov>(xmm10, xmm15);
buffer.Emit<OpCode::CvtFP2FP>(xmm10, xmm15s);
buffer.Emit<OpCode::CvtFP2FP>(xmm10s, xmm15);
// Source: xmm15, target: xmm11
buffer.Emit<OpCode::Mov>(xmm11s, xmm15s);
buffer.Emit<OpCode::Mov>(xmm11, xmm15);
buffer.Emit<OpCode::CvtFP2FP>(xmm11, xmm15s);
buffer.Emit<OpCode::CvtFP2FP>(xmm11s, xmm15);
// Source: xmm15, target: xmm12
buffer.Emit<OpCode::Mov>(xmm12s, xmm15s);
buffer.Emit<OpCode::Mov>(xmm12, xmm15);
buffer.Emit<OpCode::CvtFP2FP>(xmm12, xmm15s);
buffer.Emit<OpCode::CvtFP2FP>(xmm12s, xmm15);
// Source: xmm15, target: xmm13
buffer.Emit<OpCode::Mov>(xmm13s, xmm15s);
buffer.Emit<OpCode::Mov>(xmm13, xmm15);
buffer.Emit<OpCode::CvtFP2FP>(xmm13, xmm15s);
buffer.Emit<OpCode::CvtFP2FP>(xmm13s, xmm15);
// Source: xmm15, target: xmm14
buffer.Emit<OpCode::Mov>(xmm14s, xmm15s);
buffer.Emit<OpCode::Mov>(xmm14, xmm15);
buffer.Emit<OpCode::CvtFP2FP>(xmm14, xmm15s);
buffer.Emit<OpCode::CvtFP2FP>(xmm14s, xmm15);
// Source: xmm15, target: xmm15
buffer.Emit<OpCode::Mov>(xmm15s, xmm15s);
buffer.Emit<OpCode::Mov>(xmm15, xmm15);
buffer.Emit<OpCode::CvtFP2FP>(xmm15, xmm15s);
buffer.Emit<OpCode::CvtFP2FP>(xmm15s, xmm15);
//
// Float <-> int
//
// Between: xmm0 and rax
buffer.Emit<OpCode::Mov>(rax, -4, xmm0s);
buffer.Emit<OpCode::Mov>(rax, 4, xmm0);
buffer.Emit<OpCode::Mov>(xmm0s, rax, -4);
buffer.Emit<OpCode::Mov>(xmm0, rax, 4);
buffer.Emit<OpCode::CvtSI2FP, 4, true, 8, false>(xmm0s, rax, -4);
buffer.Emit<OpCode::CvtSI2FP, 8, true, 4, false>(xmm0, rax, 4);
buffer.Emit<OpCode::CvtFP2SI>(eax, xmm0s);
buffer.Emit<OpCode::CvtFP2SI>(eax, xmm0);
buffer.Emit<OpCode::CvtSI2FP>(xmm0s, eax);
buffer.Emit<OpCode::CvtSI2FP>(xmm0, eax);
buffer.Emit<OpCode::CvtFP2SI>(rax, xmm0s);
buffer.Emit<OpCode::CvtFP2SI>(rax, xmm0);
buffer.Emit<OpCode::CvtSI2FP>(xmm0s, rax);
buffer.Emit<OpCode::CvtSI2FP>(xmm0, rax);
// Between: xmm0 and rcx
buffer.Emit<OpCode::Mov>(rcx, -4, xmm0s);
buffer.Emit<OpCode::Mov>(rcx, 4, xmm0);
buffer.Emit<OpCode::Mov>(xmm0s, rcx, -4);
buffer.Emit<OpCode::Mov>(xmm0, rcx, 4);
buffer.Emit<OpCode::CvtSI2FP, 4, true, 8, false>(xmm0s, rcx, -4);
buffer.Emit<OpCode::CvtSI2FP, 8, true, 4, false>(xmm0, rcx, 4);
buffer.Emit<OpCode::CvtFP2SI>(ecx, xmm0s);
buffer.Emit<OpCode::CvtFP2SI>(ecx, xmm0);
buffer.Emit<OpCode::CvtSI2FP>(xmm0s, ecx);
buffer.Emit<OpCode::CvtSI2FP>(xmm0, ecx);
buffer.Emit<OpCode::CvtFP2SI>(rcx, xmm0s);
buffer.Emit<OpCode::CvtFP2SI>(rcx, xmm0);
buffer.Emit<OpCode::CvtSI2FP>(xmm0s, rcx);
buffer.Emit<OpCode::CvtSI2FP>(xmm0, rcx);
// Between: xmm0 and rdx
buffer.Emit<OpCode::Mov>(rdx, -4, xmm0s);
buffer.Emit<OpCode::Mov>(rdx, 4, xmm0);
buffer.Emit<OpCode::Mov>(xmm0s, rdx, -4);
buffer.Emit<OpCode::Mov>(xmm0, rdx, 4);
buffer.Emit<OpCode::CvtSI2FP, 4, true, 8, false>(xmm0s, rdx, -4);
buffer.Emit<OpCode::CvtSI2FP, 8, true, 4, false>(xmm0, rdx, 4);
buffer.Emit<OpCode::CvtFP2SI>(edx, xmm0s);
buffer.Emit<OpCode::CvtFP2SI>(edx, xmm0);
buffer.Emit<OpCode::CvtSI2FP>(xmm0s, edx);
buffer.Emit<OpCode::CvtSI2FP>(xmm0, edx);
buffer.Emit<OpCode::CvtFP2SI>(rdx, xmm0s);
buffer.Emit<OpCode::CvtFP2SI>(rdx, xmm0);
buffer.Emit<OpCode::CvtSI2FP>(xmm0s, rdx);
buffer.Emit<OpCode::CvtSI2FP>(xmm0, rdx);
// Between: xmm0 and rbx
buffer.Emit<OpCode::Mov>(rbx, -4, xmm0s);
buffer.Emit<OpCode::Mov>(rbx, 4, xmm0);
buffer.Emit<OpCode::Mov>(xmm0s, rbx, -4);
buffer.Emit<OpCode::Mov>(xmm0, rbx, 4);
buffer.Emit<OpCode::CvtSI2FP, 4, true, 8, false>(xmm0s, rbx, -4);
buffer.Emit<OpCode::CvtSI2FP, 8, true, 4, false>(xmm0, rbx, 4);
buffer.Emit<OpCode::CvtFP2SI>(ebx, xmm0s);
buffer.Emit<OpCode::CvtFP2SI>(ebx, xmm0);
buffer.Emit<OpCode::CvtSI2FP>(xmm0s, ebx);
buffer.Emit<OpCode::CvtSI2FP>(xmm0, ebx);
buffer.Emit<OpCode::CvtFP2SI>(rbx, xmm0s);
buffer.Emit<OpCode::CvtFP2SI>(rbx, xmm0);
buffer.Emit<OpCode::CvtSI2FP>(xmm0s, rbx);
buffer.Emit<OpCode::CvtSI2FP>(xmm0, rbx);
// Between: xmm0 and rsp
buffer.Emit<OpCode::Mov>(rsp, -4, xmm0s);
buffer.Emit<OpCode::Mov>(rsp, 4, xmm0);
buffer.Emit<OpCode::Mov>(xmm0s, rsp, -4);
buffer.Emit<OpCode::Mov>(xmm0, rsp, 4);
buffer.Emit<OpCode::CvtSI2FP, 4, true, 8, false>(xmm0s, rsp, -4);
buffer.Emit<OpCode::CvtSI2FP, 8, true, 4, false>(xmm0, rsp, 4);
buffer.Emit<OpCode::CvtFP2SI>(esp, xmm0s);
buffer.Emit<OpCode::CvtFP2SI>(esp, xmm0);
buffer.Emit<OpCode::CvtSI2FP>(xmm0s, esp);
buffer.Emit<OpCode::CvtSI2FP>(xmm0, esp);
buffer.Emit<OpCode::CvtFP2SI>(rsp, xmm0s);
buffer.Emit<OpCode::CvtFP2SI>(rsp, xmm0);
buffer.Emit<OpCode::CvtSI2FP>(xmm0s, rsp);
buffer.Emit<OpCode::CvtSI2FP>(xmm0, rsp);
// Between: xmm0 and rbp
buffer.Emit<OpCode::Mov>(rbp, -4, xmm0s);
buffer.Emit<OpCode::Mov>(rbp, 4, xmm0);
buffer.Emit<OpCode::Mov>(xmm0s, rbp, -4);
buffer.Emit<OpCode::Mov>(xmm0, rbp, 4);
buffer.Emit<OpCode::CvtSI2FP, 4, true, 8, false>(xmm0s, rbp, -4);
buffer.Emit<OpCode::CvtSI2FP, 8, true, 4, false>(xmm0, rbp, 4);
buffer.Emit<OpCode::CvtFP2SI>(ebp, xmm0s);
buffer.Emit<OpCode::CvtFP2SI>(ebp, xmm0);
buffer.Emit<OpCode::CvtSI2FP>(xmm0s, ebp);
buffer.Emit<OpCode::CvtSI2FP>(xmm0, ebp);
buffer.Emit<OpCode::CvtFP2SI>(rbp, xmm0s);
buffer.Emit<OpCode::CvtFP2SI>(rbp, xmm0);
buffer.Emit<OpCode::CvtSI2FP>(xmm0s, rbp);
buffer.Emit<OpCode::CvtSI2FP>(xmm0, rbp);
// Between: xmm0 and rsi
buffer.Emit<OpCode::Mov>(rsi, -4, xmm0s);
buffer.Emit<OpCode::Mov>(rsi, 4, xmm0);
buffer.Emit<OpCode::Mov>(xmm0s, rsi, -4);
buffer.Emit<OpCode::Mov>(xmm0, rsi, 4);
buffer.Emit<OpCode::CvtSI2FP, 4, true, 8, false>(xmm0s, rsi, -4);
buffer.Emit<OpCode::CvtSI2FP, 8, true, 4, false>(xmm0, rsi, 4);
buffer.Emit<OpCode::CvtFP2SI>(esi, xmm0s);
buffer.Emit<OpCode::CvtFP2SI>(esi, xmm0);
buffer.Emit<OpCode::CvtSI2FP>(xmm0s, esi);
buffer.Emit<OpCode::CvtSI2FP>(xmm0, esi);
buffer.Emit<OpCode::CvtFP2SI>(rsi, xmm0s);
buffer.Emit<OpCode::CvtFP2SI>(rsi, xmm0);
buffer.Emit<OpCode::CvtSI2FP>(xmm0s, rsi);
buffer.Emit<OpCode::CvtSI2FP>(xmm0, rsi);
// Between: xmm0 and rdi
buffer.Emit<OpCode::Mov>(rdi, -4, xmm0s);
buffer.Emit<OpCode::Mov>(rdi, 4, xmm0);
buffer.Emit<OpCode::Mov>(xmm0s, rdi, -4);
buffer.Emit<OpCode::Mov>(xmm0, rdi, 4);
buffer.Emit<OpCode::CvtSI2FP, 4, true, 8, false>(xmm0s, rdi, -4);
buffer.Emit<OpCode::CvtSI2FP, 8, true, 4, false>(xmm0, rdi, 4);
buffer.Emit<OpCode::CvtFP2SI>(edi, xmm0s);
buffer.Emit<OpCode::CvtFP2SI>(edi, xmm0);
buffer.Emit<OpCode::CvtSI2FP>(xmm0s, edi);
buffer.Emit<OpCode::CvtSI2FP>(xmm0, edi);
buffer.Emit<OpCode::CvtFP2SI>(rdi, xmm0s);
buffer.Emit<OpCode::CvtFP2SI>(rdi, xmm0);
buffer.Emit<OpCode::CvtSI2FP>(xmm0s, rdi);
buffer.Emit<OpCode::CvtSI2FP>(xmm0, rdi);
// Between: xmm0 and r8
buffer.Emit<OpCode::Mov>(r8, -4, xmm0s);
buffer.Emit<OpCode::Mov>(r8, 4, xmm0);
buffer.Emit<OpCode::Mov>(xmm0s, r8, -4);
buffer.Emit<OpCode::Mov>(xmm0, r8, 4);
buffer.Emit<OpCode::CvtSI2FP, 4, true, 8, false>(xmm0s, r8, -4);
buffer.Emit<OpCode::CvtSI2FP, 8, true, 4, false>(xmm0, r8, 4);
buffer.Emit<OpCode::CvtFP2SI>(r8d, xmm0s);
buffer.Emit<OpCode::CvtFP2SI>(r8d, xmm0);
buffer.Emit<OpCode::CvtSI2FP>(xmm0s, r8d);
buffer.Emit<OpCode::CvtSI2FP>(xmm0, r8d);
buffer.Emit<OpCode::CvtFP2SI>(r8, xmm0s);
buffer.Emit<OpCode::CvtFP2SI>(r8, xmm0);
buffer.Emit<OpCode::CvtSI2FP>(xmm0s, r8);
buffer.Emit<OpCode::CvtSI2FP>(xmm0, r8);
// Between: xmm0 and r9
buffer.Emit<OpCode::Mov>(r9, -4, xmm0s);
buffer.Emit<OpCode::Mov>(r9, 4, xmm0);
buffer.Emit<OpCode::Mov>(xmm0s, r9, -4);
buffer.Emit<OpCode::Mov>(xmm0, r9, 4);
buffer.Emit<OpCode::CvtSI2FP, 4, true, 8, false>(xmm0s, r9, -4);
buffer.Emit<OpCode::CvtSI2FP, 8, true, 4, false>(xmm0, r9, 4);
buffer.Emit<OpCode::CvtFP2SI>(r9d, xmm0s);
buffer.Emit<OpCode::CvtFP2SI>(r9d, xmm0);
buffer.Emit<OpCode::CvtSI2FP>(xmm0s, r9d);
buffer.Emit<OpCode::CvtSI2FP>(xmm0, r9d);
buffer.Emit<OpCode::CvtFP2SI>(r9, xmm0s);
buffer.Emit<OpCode::CvtFP2SI>(r9, xmm0);
buffer.Emit<OpCode::CvtSI2FP>(xmm0s, r9);
buffer.Emit<OpCode::CvtSI2FP>(xmm0, r9);
// Between: xmm0 and r10
buffer.Emit<OpCode::Mov>(r10, -4, xmm0s);
buffer.Emit<OpCode::Mov>(r10, 4, xmm0);
buffer.Emit<OpCode::Mov>(xmm0s, r10, -4);
buffer.Emit<OpCode::Mov>(xmm0, r10, 4);
buffer.Emit<OpCode::CvtSI2FP, 4, true, 8, false>(xmm0s, r10, -4);
buffer.Emit<OpCode::CvtSI2FP, 8, true, 4, false>(xmm0, r10, 4);
buffer.Emit<OpCode::CvtFP2SI>(r10d, xmm0s);
buffer.Emit<OpCode::CvtFP2SI>(r10d, xmm0);
buffer.Emit<OpCode::CvtSI2FP>(xmm0s, r10d);
buffer.Emit<OpCode::CvtSI2FP>(xmm0, r10d);
buffer.Emit<OpCode::CvtFP2SI>(r10, xmm0s);
buffer.Emit<OpCode::CvtFP2SI>(r10, xmm0);
buffer.Emit<OpCode::CvtSI2FP>(xmm0s, r10);
buffer.Emit<OpCode::CvtSI2FP>(xmm0, r10);
// Between: xmm0 and r11
buffer.Emit<OpCode::Mov>(r11, -4, xmm0s);
buffer.Emit<OpCode::Mov>(r11, 4, xmm0);
buffer.Emit<OpCode::Mov>(xmm0s, r11, -4);
buffer.Emit<OpCode::Mov>(xmm0, r11, 4);
buffer.Emit<OpCode::CvtSI2FP, 4, true, 8, false>(xmm0s, r11, -4);
buffer.Emit<OpCode::CvtSI2FP, 8, true, 4, false>(xmm0, r11, 4);
buffer.Emit<OpCode::CvtFP2SI>(r11d, xmm0s);
buffer.Emit<OpCode::CvtFP2SI>(r11d, xmm0);
buffer.Emit<OpCode::CvtSI2FP>(xmm0s, r11d);
buffer.Emit<OpCode::CvtSI2FP>(xmm0, r11d);
buffer.Emit<OpCode::CvtFP2SI>(r11, xmm0s);
buffer.Emit<OpCode::CvtFP2SI>(r11, xmm0);
buffer.Emit<OpCode::CvtSI2FP>(xmm0s, r11);
buffer.Emit<OpCode::CvtSI2FP>(xmm0, r11);
// Between: xmm0 and r12
buffer.Emit<OpCode::Mov>(r12, -4, xmm0s);
buffer.Emit<OpCode::Mov>(r12, 4, xmm0);
buffer.Emit<OpCode::Mov>(xmm0s, r12, -4);
buffer.Emit<OpCode::Mov>(xmm0, r12, 4);
buffer.Emit<OpCode::CvtSI2FP, 4, true, 8, false>(xmm0s, r12, -4);
buffer.Emit<OpCode::CvtSI2FP, 8, true, 4, false>(xmm0, r12, 4);
buffer.Emit<OpCode::CvtFP2SI>(r12d, xmm0s);
buffer.Emit<OpCode::CvtFP2SI>(r12d, xmm0);
buffer.Emit<OpCode::CvtSI2FP>(xmm0s, r12d);
buffer.Emit<OpCode::CvtSI2FP>(xmm0, r12d);
buffer.Emit<OpCode::CvtFP2SI>(r12, xmm0s);
buffer.Emit<OpCode::CvtFP2SI>(r12, xmm0);
buffer.Emit<OpCode::CvtSI2FP>(xmm0s, r12);
buffer.Emit<OpCode::CvtSI2FP>(xmm0, r12);
// Between: xmm0 and r13
buffer.Emit<OpCode::Mov>(r13, -4, xmm0s);
buffer.Emit<OpCode::Mov>(r13, 4, xmm0);
buffer.Emit<OpCode::Mov>(xmm0s, r13, -4);
buffer.Emit<OpCode::Mov>(xmm0, r13, 4);
buffer.Emit<OpCode::CvtSI2FP, 4, true, 8, false>(xmm0s, r13, -4);
buffer.Emit<OpCode::CvtSI2FP, 8, true, 4, false>(xmm0, r13, 4);
buffer.Emit<OpCode::CvtFP2SI>(r13d, xmm0s);
buffer.Emit<OpCode::CvtFP2SI>(r13d, xmm0);
buffer.Emit<OpCode::CvtSI2FP>(xmm0s, r13d);
buffer.Emit<OpCode::CvtSI2FP>(xmm0, r13d);
buffer.Emit<OpCode::CvtFP2SI>(r13, xmm0s);
buffer.Emit<OpCode::CvtFP2SI>(r13, xmm0);
buffer.Emit<OpCode::CvtSI2FP>(xmm0s, r13);
buffer.Emit<OpCode::CvtSI2FP>(xmm0, r13);
// Between: xmm0 and r14
buffer.Emit<OpCode::Mov>(r14, -4, xmm0s);
buffer.Emit<OpCode::Mov>(r14, 4, xmm0);
buffer.Emit<OpCode::Mov>(xmm0s, r14, -4);
buffer.Emit<OpCode::Mov>(xmm0, r14, 4);
buffer.Emit<OpCode::CvtSI2FP, 4, true, 8, false>(xmm0s, r14, -4);
buffer.Emit<OpCode::CvtSI2FP, 8, true, 4, false>(xmm0, r14, 4);
buffer.Emit<OpCode::CvtFP2SI>(r14d, xmm0s);
buffer.Emit<OpCode::CvtFP2SI>(r14d, xmm0);
buffer.Emit<OpCode::CvtSI2FP>(xmm0s, r14d);
buffer.Emit<OpCode::CvtSI2FP>(xmm0, r14d);
buffer.Emit<OpCode::CvtFP2SI>(r14, xmm0s);
buffer.Emit<OpCode::CvtFP2SI>(r14, xmm0);
buffer.Emit<OpCode::CvtSI2FP>(xmm0s, r14);
buffer.Emit<OpCode::CvtSI2FP>(xmm0, r14);
// Between: xmm0 and r15
buffer.Emit<OpCode::Mov>(r15, -4, xmm0s);
buffer.Emit<OpCode::Mov>(r15, 4, xmm0);
buffer.Emit<OpCode::Mov>(xmm0s, r15, -4);
buffer.Emit<OpCode::Mov>(xmm0, r15, 4);
buffer.Emit<OpCode::CvtSI2FP, 4, true, 8, false>(xmm0s, r15, -4);
buffer.Emit<OpCode::CvtSI2FP, 8, true, 4, false>(xmm0, r15, 4);
buffer.Emit<OpCode::CvtFP2SI>(r15d, xmm0s);
buffer.Emit<OpCode::CvtFP2SI>(r15d, xmm0);
buffer.Emit<OpCode::CvtSI2FP>(xmm0s, r15d);
buffer.Emit<OpCode::CvtSI2FP>(xmm0, r15d);
buffer.Emit<OpCode::CvtFP2SI>(r15, xmm0s);
buffer.Emit<OpCode::CvtFP2SI>(r15, xmm0);
buffer.Emit<OpCode::CvtSI2FP>(xmm0s, r15);
buffer.Emit<OpCode::CvtSI2FP>(xmm0, r15);
// Between: xmm1 and rax
buffer.Emit<OpCode::Mov>(rax, -4, xmm1s);
buffer.Emit<OpCode::Mov>(rax, 4, xmm1);
buffer.Emit<OpCode::Mov>(xmm1s, rax, -4);
buffer.Emit<OpCode::Mov>(xmm1, rax, 4);
buffer.Emit<OpCode::CvtSI2FP, 4, true, 8, false>(xmm1s, rax, -4);
buffer.Emit<OpCode::CvtSI2FP, 8, true, 4, false>(xmm1, rax, 4);
buffer.Emit<OpCode::CvtFP2SI>(eax, xmm1s);
buffer.Emit<OpCode::CvtFP2SI>(eax, xmm1);
buffer.Emit<OpCode::CvtSI2FP>(xmm1s, eax);
buffer.Emit<OpCode::CvtSI2FP>(xmm1, eax);
buffer.Emit<OpCode::CvtFP2SI>(rax, xmm1s);
buffer.Emit<OpCode::CvtFP2SI>(rax, xmm1);
buffer.Emit<OpCode::CvtSI2FP>(xmm1s, rax);
buffer.Emit<OpCode::CvtSI2FP>(xmm1, rax);
// Between: xmm1 and rcx
buffer.Emit<OpCode::Mov>(rcx, -4, xmm1s);
buffer.Emit<OpCode::Mov>(rcx, 4, xmm1);
buffer.Emit<OpCode::Mov>(xmm1s, rcx, -4);
buffer.Emit<OpCode::Mov>(xmm1, rcx, 4);
buffer.Emit<OpCode::CvtSI2FP, 4, true, 8, false>(xmm1s, rcx, -4);
buffer.Emit<OpCode::CvtSI2FP, 8, true, 4, false>(xmm1, rcx, 4);
buffer.Emit<OpCode::CvtFP2SI>(ecx, xmm1s);
buffer.Emit<OpCode::CvtFP2SI>(ecx, xmm1);
buffer.Emit<OpCode::CvtSI2FP>(xmm1s, ecx);
buffer.Emit<OpCode::CvtSI2FP>(xmm1, ecx);
buffer.Emit<OpCode::CvtFP2SI>(rcx, xmm1s);
buffer.Emit<OpCode::CvtFP2SI>(rcx, xmm1);
buffer.Emit<OpCode::CvtSI2FP>(xmm1s, rcx);
buffer.Emit<OpCode::CvtSI2FP>(xmm1, rcx);
// Between: xmm1 and rdx
buffer.Emit<OpCode::Mov>(rdx, -4, xmm1s);
buffer.Emit<OpCode::Mov>(rdx, 4, xmm1);
buffer.Emit<OpCode::Mov>(xmm1s, rdx, -4);
buffer.Emit<OpCode::Mov>(xmm1, rdx, 4);
buffer.Emit<OpCode::CvtSI2FP, 4, true, 8, false>(xmm1s, rdx, -4);
buffer.Emit<OpCode::CvtSI2FP, 8, true, 4, false>(xmm1, rdx, 4);
buffer.Emit<OpCode::CvtFP2SI>(edx, xmm1s);
buffer.Emit<OpCode::CvtFP2SI>(edx, xmm1);
buffer.Emit<OpCode::CvtSI2FP>(xmm1s, edx);
buffer.Emit<OpCode::CvtSI2FP>(xmm1, edx);
buffer.Emit<OpCode::CvtFP2SI>(rdx, xmm1s);
buffer.Emit<OpCode::CvtFP2SI>(rdx, xmm1);
buffer.Emit<OpCode::CvtSI2FP>(xmm1s, rdx);
buffer.Emit<OpCode::CvtSI2FP>(xmm1, rdx);
// Between: xmm1 and rbx
buffer.Emit<OpCode::Mov>(rbx, -4, xmm1s);
buffer.Emit<OpCode::Mov>(rbx, 4, xmm1);
buffer.Emit<OpCode::Mov>(xmm1s, rbx, -4);
buffer.Emit<OpCode::Mov>(xmm1, rbx, 4);
buffer.Emit<OpCode::CvtSI2FP, 4, true, 8, false>(xmm1s, rbx, -4);
buffer.Emit<OpCode::CvtSI2FP, 8, true, 4, false>(xmm1, rbx, 4);
buffer.Emit<OpCode::CvtFP2SI>(ebx, xmm1s);
buffer.Emit<OpCode::CvtFP2SI>(ebx, xmm1);
buffer.Emit<OpCode::CvtSI2FP>(xmm1s, ebx);
buffer.Emit<OpCode::CvtSI2FP>(xmm1, ebx);
buffer.Emit<OpCode::CvtFP2SI>(rbx, xmm1s);
buffer.Emit<OpCode::CvtFP2SI>(rbx, xmm1);
buffer.Emit<OpCode::CvtSI2FP>(xmm1s, rbx);
buffer.Emit<OpCode::CvtSI2FP>(xmm1, rbx);
// Between: xmm1 and rsp
buffer.Emit<OpCode::Mov>(rsp, -4, xmm1s);
buffer.Emit<OpCode::Mov>(rsp, 4, xmm1);
buffer.Emit<OpCode::Mov>(xmm1s, rsp, -4);
buffer.Emit<OpCode::Mov>(xmm1, rsp, 4);
buffer.Emit<OpCode::CvtSI2FP, 4, true, 8, false>(xmm1s, rsp, -4);
buffer.Emit<OpCode::CvtSI2FP, 8, true, 4, false>(xmm1, rsp, 4);
buffer.Emit<OpCode::CvtFP2SI>(esp, xmm1s);
buffer.Emit<OpCode::CvtFP2SI>(esp, xmm1);
buffer.Emit<OpCode::CvtSI2FP>(xmm1s, esp);
buffer.Emit<OpCode::CvtSI2FP>(xmm1, esp);
buffer.Emit<OpCode::CvtFP2SI>(rsp, xmm1s);
buffer.Emit<OpCode::CvtFP2SI>(rsp, xmm1);
buffer.Emit<OpCode::CvtSI2FP>(xmm1s, rsp);
buffer.Emit<OpCode::CvtSI2FP>(xmm1, rsp);
// Between: xmm1 and rbp
buffer.Emit<OpCode::Mov>(rbp, -4, xmm1s);
buffer.Emit<OpCode::Mov>(rbp, 4, xmm1);
buffer.Emit<OpCode::Mov>(xmm1s, rbp, -4);
buffer.Emit<OpCode::Mov>(xmm1, rbp, 4);
buffer.Emit<OpCode::CvtSI2FP, 4, true, 8, false>(xmm1s, rbp, -4);
buffer.Emit<OpCode::CvtSI2FP, 8, true, 4, false>(xmm1, rbp, 4);
buffer.Emit<OpCode::CvtFP2SI>(ebp, xmm1s);
buffer.Emit<OpCode::CvtFP2SI>(ebp, xmm1);
buffer.Emit<OpCode::CvtSI2FP>(xmm1s, ebp);
buffer.Emit<OpCode::CvtSI2FP>(xmm1, ebp);
buffer.Emit<OpCode::CvtFP2SI>(rbp, xmm1s);
buffer.Emit<OpCode::CvtFP2SI>(rbp, xmm1);
buffer.Emit<OpCode::CvtSI2FP>(xmm1s, rbp);
buffer.Emit<OpCode::CvtSI2FP>(xmm1, rbp);
// Between: xmm1 and rsi
buffer.Emit<OpCode::Mov>(rsi, -4, xmm1s);
buffer.Emit<OpCode::Mov>(rsi, 4, xmm1);
buffer.Emit<OpCode::Mov>(xmm1s, rsi, -4);
buffer.Emit<OpCode::Mov>(xmm1, rsi, 4);
buffer.Emit<OpCode::CvtSI2FP, 4, true, 8, false>(xmm1s, rsi, -4);
buffer.Emit<OpCode::CvtSI2FP, 8, true, 4, false>(xmm1, rsi, 4);
buffer.Emit<OpCode::CvtFP2SI>(esi, xmm1s);
buffer.Emit<OpCode::CvtFP2SI>(esi, xmm1);
buffer.Emit<OpCode::CvtSI2FP>(xmm1s, esi);
buffer.Emit<OpCode::CvtSI2FP>(xmm1, esi);
buffer.Emit<OpCode::CvtFP2SI>(rsi, xmm1s);
buffer.Emit<OpCode::CvtFP2SI>(rsi, xmm1);
buffer.Emit<OpCode::CvtSI2FP>(xmm1s, rsi);
buffer.Emit<OpCode::CvtSI2FP>(xmm1, rsi);
// Between: xmm1 and rdi
buffer.Emit<OpCode::Mov>(rdi, -4, xmm1s);
buffer.Emit<OpCode::Mov>(rdi, 4, xmm1);
buffer.Emit<OpCode::Mov>(xmm1s, rdi, -4);
buffer.Emit<OpCode::Mov>(xmm1, rdi, 4);
buffer.Emit<OpCode::CvtSI2FP, 4, true, 8, false>(xmm1s, rdi, -4);
buffer.Emit<OpCode::CvtSI2FP, 8, true, 4, false>(xmm1, rdi, 4);
buffer.Emit<OpCode::CvtFP2SI>(edi, xmm1s);
buffer.Emit<OpCode::CvtFP2SI>(edi, xmm1);
buffer.Emit<OpCode::CvtSI2FP>(xmm1s, edi);
buffer.Emit<OpCode::CvtSI2FP>(xmm1, edi);
buffer.Emit<OpCode::CvtFP2SI>(rdi, xmm1s);
buffer.Emit<OpCode::CvtFP2SI>(rdi, xmm1);
buffer.Emit<OpCode::CvtSI2FP>(xmm1s, rdi);
buffer.Emit<OpCode::CvtSI2FP>(xmm1, rdi);
// Between: xmm1 and r8
buffer.Emit<OpCode::Mov>(r8, -4, xmm1s);
buffer.Emit<OpCode::Mov>(r8, 4, xmm1);
buffer.Emit<OpCode::Mov>(xmm1s, r8, -4);
buffer.Emit<OpCode::Mov>(xmm1, r8, 4);
buffer.Emit<OpCode::CvtSI2FP, 4, true, 8, false>(xmm1s, r8, -4);
buffer.Emit<OpCode::CvtSI2FP, 8, true, 4, false>(xmm1, r8, 4);
buffer.Emit<OpCode::CvtFP2SI>(r8d, xmm1s);
buffer.Emit<OpCode::CvtFP2SI>(r8d, xmm1);
buffer.Emit<OpCode::CvtSI2FP>(xmm1s, r8d);
buffer.Emit<OpCode::CvtSI2FP>(xmm1, r8d);
buffer.Emit<OpCode::CvtFP2SI>(r8, xmm1s);
buffer.Emit<OpCode::CvtFP2SI>(r8, xmm1);
buffer.Emit<OpCode::CvtSI2FP>(xmm1s, r8);
buffer.Emit<OpCode::CvtSI2FP>(xmm1, r8);
// Between: xmm1 and r9
buffer.Emit<OpCode::Mov>(r9, -4, xmm1s);
buffer.Emit<OpCode::Mov>(r9, 4, xmm1);
buffer.Emit<OpCode::Mov>(xmm1s, r9, -4);
buffer.Emit<OpCode::Mov>(xmm1, r9, 4);
buffer.Emit<OpCode::CvtSI2FP, 4, true, 8, false>(xmm1s, r9, -4);
buffer.Emit<OpCode::CvtSI2FP, 8, true, 4, false>(xmm1, r9, 4);
buffer.Emit<OpCode::CvtFP2SI>(r9d, xmm1s);
buffer.Emit<OpCode::CvtFP2SI>(r9d, xmm1);
buffer.Emit<OpCode::CvtSI2FP>(xmm1s, r9d);
buffer.Emit<OpCode::CvtSI2FP>(xmm1, r9d);
buffer.Emit<OpCode::CvtFP2SI>(r9, xmm1s);
buffer.Emit<OpCode::CvtFP2SI>(r9, xmm1);
buffer.Emit<OpCode::CvtSI2FP>(xmm1s, r9);
buffer.Emit<OpCode::CvtSI2FP>(xmm1, r9);
// Between: xmm1 and r10
buffer.Emit<OpCode::Mov>(r10, -4, xmm1s);
buffer.Emit<OpCode::Mov>(r10, 4, xmm1);
buffer.Emit<OpCode::Mov>(xmm1s, r10, -4);
buffer.Emit<OpCode::Mov>(xmm1, r10, 4);
buffer.Emit<OpCode::CvtSI2FP, 4, true, 8, false>(xmm1s, r10, -4);
buffer.Emit<OpCode::CvtSI2FP, 8, true, 4, false>(xmm1, r10, 4);
buffer.Emit<OpCode::CvtFP2SI>(r10d, xmm1s);
buffer.Emit<OpCode::CvtFP2SI>(r10d, xmm1);
buffer.Emit<OpCode::CvtSI2FP>(xmm1s, r10d);
buffer.Emit<OpCode::CvtSI2FP>(xmm1, r10d);
buffer.Emit<OpCode::CvtFP2SI>(r10, xmm1s);
buffer.Emit<OpCode::CvtFP2SI>(r10, xmm1);
buffer.Emit<OpCode::CvtSI2FP>(xmm1s, r10);
buffer.Emit<OpCode::CvtSI2FP>(xmm1, r10);
// Between: xmm1 and r11
buffer.Emit<OpCode::Mov>(r11, -4, xmm1s);
buffer.Emit<OpCode::Mov>(r11, 4, xmm1);
buffer.Emit<OpCode::Mov>(xmm1s, r11, -4);
buffer.Emit<OpCode::Mov>(xmm1, r11, 4);
buffer.Emit<OpCode::CvtSI2FP, 4, true, 8, false>(xmm1s, r11, -4);
buffer.Emit<OpCode::CvtSI2FP, 8, true, 4, false>(xmm1, r11, 4);
buffer.Emit<OpCode::CvtFP2SI>(r11d, xmm1s);
buffer.Emit<OpCode::CvtFP2SI>(r11d, xmm1);
buffer.Emit<OpCode::CvtSI2FP>(xmm1s, r11d);
buffer.Emit<OpCode::CvtSI2FP>(xmm1, r11d);
buffer.Emit<OpCode::CvtFP2SI>(r11, xmm1s);
buffer.Emit<OpCode::CvtFP2SI>(r11, xmm1);
buffer.Emit<OpCode::CvtSI2FP>(xmm1s, r11);
buffer.Emit<OpCode::CvtSI2FP>(xmm1, r11);
// Between: xmm1 and r12
buffer.Emit<OpCode::Mov>(r12, -4, xmm1s);
buffer.Emit<OpCode::Mov>(r12, 4, xmm1);
buffer.Emit<OpCode::Mov>(xmm1s, r12, -4);
buffer.Emit<OpCode::Mov>(xmm1, r12, 4);
buffer.Emit<OpCode::CvtSI2FP, 4, true, 8, false>(xmm1s, r12, -4);
buffer.Emit<OpCode::CvtSI2FP, 8, true, 4, false>(xmm1, r12, 4);
buffer.Emit<OpCode::CvtFP2SI>(r12d, xmm1s);
buffer.Emit<OpCode::CvtFP2SI>(r12d, xmm1);
buffer.Emit<OpCode::CvtSI2FP>(xmm1s, r12d);
buffer.Emit<OpCode::CvtSI2FP>(xmm1, r12d);
buffer.Emit<OpCode::CvtFP2SI>(r12, xmm1s);
buffer.Emit<OpCode::CvtFP2SI>(r12, xmm1);
buffer.Emit<OpCode::CvtSI2FP>(xmm1s, r12);
buffer.Emit<OpCode::CvtSI2FP>(xmm1, r12);
// Between: xmm1 and r13
buffer.Emit<OpCode::Mov>(r13, -4, xmm1s);
buffer.Emit<OpCode::Mov>(r13, 4, xmm1);
buffer.Emit<OpCode::Mov>(xmm1s, r13, -4);
buffer.Emit<OpCode::Mov>(xmm1, r13, 4);
buffer.Emit<OpCode::CvtSI2FP, 4, true, 8, false>(xmm1s, r13, -4);
buffer.Emit<OpCode::CvtSI2FP, 8, true, 4, false>(xmm1, r13, 4);
buffer.Emit<OpCode::CvtFP2SI>(r13d, xmm1s);
buffer.Emit<OpCode::CvtFP2SI>(r13d, xmm1);
buffer.Emit<OpCode::CvtSI2FP>(xmm1s, r13d);
buffer.Emit<OpCode::CvtSI2FP>(xmm1, r13d);
buffer.Emit<OpCode::CvtFP2SI>(r13, xmm1s);
buffer.Emit<OpCode::CvtFP2SI>(r13, xmm1);
buffer.Emit<OpCode::CvtSI2FP>(xmm1s, r13);
buffer.Emit<OpCode::CvtSI2FP>(xmm1, r13);
// Between: xmm1 and r14
buffer.Emit<OpCode::Mov>(r14, -4, xmm1s);
buffer.Emit<OpCode::Mov>(r14, 4, xmm1);
buffer.Emit<OpCode::Mov>(xmm1s, r14, -4);
buffer.Emit<OpCode::Mov>(xmm1, r14, 4);
buffer.Emit<OpCode::CvtSI2FP, 4, true, 8, false>(xmm1s, r14, -4);
buffer.Emit<OpCode::CvtSI2FP, 8, true, 4, false>(xmm1, r14, 4);
buffer.Emit<OpCode::CvtFP2SI>(r14d, xmm1s);
buffer.Emit<OpCode::CvtFP2SI>(r14d, xmm1);
buffer.Emit<OpCode::CvtSI2FP>(xmm1s, r14d);
buffer.Emit<OpCode::CvtSI2FP>(xmm1, r14d);
buffer.Emit<OpCode::CvtFP2SI>(r14, xmm1s);
buffer.Emit<OpCode::CvtFP2SI>(r14, xmm1);
buffer.Emit<OpCode::CvtSI2FP>(xmm1s, r14);
buffer.Emit<OpCode::CvtSI2FP>(xmm1, r14);
// Between: xmm1 and r15
buffer.Emit<OpCode::Mov>(r15, -4, xmm1s);
buffer.Emit<OpCode::Mov>(r15, 4, xmm1);
buffer.Emit<OpCode::Mov>(xmm1s, r15, -4);
buffer.Emit<OpCode::Mov>(xmm1, r15, 4);
buffer.Emit<OpCode::CvtSI2FP, 4, true, 8, false>(xmm1s, r15, -4);
buffer.Emit<OpCode::CvtSI2FP, 8, true, 4, false>(xmm1, r15, 4);
buffer.Emit<OpCode::CvtFP2SI>(r15d, xmm1s);
buffer.Emit<OpCode::CvtFP2SI>(r15d, xmm1);
buffer.Emit<OpCode::CvtSI2FP>(xmm1s, r15d);
buffer.Emit<OpCode::CvtSI2FP>(xmm1, r15d);
buffer.Emit<OpCode::CvtFP2SI>(r15, xmm1s);
buffer.Emit<OpCode::CvtFP2SI>(r15, xmm1);
buffer.Emit<OpCode::CvtSI2FP>(xmm1s, r15);
buffer.Emit<OpCode::CvtSI2FP>(xmm1, r15);
// Between: xmm2 and rax
buffer.Emit<OpCode::Mov>(rax, -4, xmm2s);
buffer.Emit<OpCode::Mov>(rax, 4, xmm2);
buffer.Emit<OpCode::Mov>(xmm2s, rax, -4);
buffer.Emit<OpCode::Mov>(xmm2, rax, 4);
buffer.Emit<OpCode::CvtSI2FP, 4, true, 8, false>(xmm2s, rax, -4);
buffer.Emit<OpCode::CvtSI2FP, 8, true, 4, false>(xmm2, rax, 4);
buffer.Emit<OpCode::CvtFP2SI>(eax, xmm2s);
buffer.Emit<OpCode::CvtFP2SI>(eax, xmm2);
buffer.Emit<OpCode::CvtSI2FP>(xmm2s, eax);
buffer.Emit<OpCode::CvtSI2FP>(xmm2, eax);
buffer.Emit<OpCode::CvtFP2SI>(rax, xmm2s);
buffer.Emit<OpCode::CvtFP2SI>(rax, xmm2);
buffer.Emit<OpCode::CvtSI2FP>(xmm2s, rax);
buffer.Emit<OpCode::CvtSI2FP>(xmm2, rax);
// Between: xmm2 and rcx
buffer.Emit<OpCode::Mov>(rcx, -4, xmm2s);
buffer.Emit<OpCode::Mov>(rcx, 4, xmm2);
buffer.Emit<OpCode::Mov>(xmm2s, rcx, -4);
buffer.Emit<OpCode::Mov>(xmm2, rcx, 4);
buffer.Emit<OpCode::CvtSI2FP, 4, true, 8, false>(xmm2s, rcx, -4);
buffer.Emit<OpCode::CvtSI2FP, 8, true, 4, false>(xmm2, rcx, 4);
buffer.Emit<OpCode::CvtFP2SI>(ecx, xmm2s);
buffer.Emit<OpCode::CvtFP2SI>(ecx, xmm2);
buffer.Emit<OpCode::CvtSI2FP>(xmm2s, ecx);
buffer.Emit<OpCode::CvtSI2FP>(xmm2, ecx);
buffer.Emit<OpCode::CvtFP2SI>(rcx, xmm2s);
buffer.Emit<OpCode::CvtFP2SI>(rcx, xmm2);
buffer.Emit<OpCode::CvtSI2FP>(xmm2s, rcx);
buffer.Emit<OpCode::CvtSI2FP>(xmm2, rcx);
// Between: xmm2 and rdx
buffer.Emit<OpCode::Mov>(rdx, -4, xmm2s);
buffer.Emit<OpCode::Mov>(rdx, 4, xmm2);
buffer.Emit<OpCode::Mov>(xmm2s, rdx, -4);
buffer.Emit<OpCode::Mov>(xmm2, rdx, 4);
buffer.Emit<OpCode::CvtSI2FP, 4, true, 8, false>(xmm2s, rdx, -4);
buffer.Emit<OpCode::CvtSI2FP, 8, true, 4, false>(xmm2, rdx, 4);
buffer.Emit<OpCode::CvtFP2SI>(edx, xmm2s);
buffer.Emit<OpCode::CvtFP2SI>(edx, xmm2);
buffer.Emit<OpCode::CvtSI2FP>(xmm2s, edx);
buffer.Emit<OpCode::CvtSI2FP>(xmm2, edx);
buffer.Emit<OpCode::CvtFP2SI>(rdx, xmm2s);
buffer.Emit<OpCode::CvtFP2SI>(rdx, xmm2);
buffer.Emit<OpCode::CvtSI2FP>(xmm2s, rdx);
buffer.Emit<OpCode::CvtSI2FP>(xmm2, rdx);
// Between: xmm2 and rbx
buffer.Emit<OpCode::Mov>(rbx, -4, xmm2s);
buffer.Emit<OpCode::Mov>(rbx, 4, xmm2);
buffer.Emit<OpCode::Mov>(xmm2s, rbx, -4);
buffer.Emit<OpCode::Mov>(xmm2, rbx, 4);
buffer.Emit<OpCode::CvtSI2FP, 4, true, 8, false>(xmm2s, rbx, -4);
buffer.Emit<OpCode::CvtSI2FP, 8, true, 4, false>(xmm2, rbx, 4);
buffer.Emit<OpCode::CvtFP2SI>(ebx, xmm2s);
buffer.Emit<OpCode::CvtFP2SI>(ebx, xmm2);
buffer.Emit<OpCode::CvtSI2FP>(xmm2s, ebx);
buffer.Emit<OpCode::CvtSI2FP>(xmm2, ebx);
buffer.Emit<OpCode::CvtFP2SI>(rbx, xmm2s);
buffer.Emit<OpCode::CvtFP2SI>(rbx, xmm2);
buffer.Emit<OpCode::CvtSI2FP>(xmm2s, rbx);
buffer.Emit<OpCode::CvtSI2FP>(xmm2, rbx);
// Between: xmm2 and rsp
buffer.Emit<OpCode::Mov>(rsp, -4, xmm2s);
buffer.Emit<OpCode::Mov>(rsp, 4, xmm2);
buffer.Emit<OpCode::Mov>(xmm2s, rsp, -4);
buffer.Emit<OpCode::Mov>(xmm2, rsp, 4);
buffer.Emit<OpCode::CvtSI2FP, 4, true, 8, false>(xmm2s, rsp, -4);
buffer.Emit<OpCode::CvtSI2FP, 8, true, 4, false>(xmm2, rsp, 4);
buffer.Emit<OpCode::CvtFP2SI>(esp, xmm2s);
buffer.Emit<OpCode::CvtFP2SI>(esp, xmm2);
buffer.Emit<OpCode::CvtSI2FP>(xmm2s, esp);
buffer.Emit<OpCode::CvtSI2FP>(xmm2, esp);
buffer.Emit<OpCode::CvtFP2SI>(rsp, xmm2s);
buffer.Emit<OpCode::CvtFP2SI>(rsp, xmm2);
buffer.Emit<OpCode::CvtSI2FP>(xmm2s, rsp);
buffer.Emit<OpCode::CvtSI2FP>(xmm2, rsp);
// Between: xmm2 and rbp
buffer.Emit<OpCode::Mov>(rbp, -4, xmm2s);
buffer.Emit<OpCode::Mov>(rbp, 4, xmm2);
buffer.Emit<OpCode::Mov>(xmm2s, rbp, -4);
buffer.Emit<OpCode::Mov>(xmm2, rbp, 4);
buffer.Emit<OpCode::CvtSI2FP, 4, true, 8, false>(xmm2s, rbp, -4);
buffer.Emit<OpCode::CvtSI2FP, 8, true, 4, false>(xmm2, rbp, 4);
buffer.Emit<OpCode::CvtFP2SI>(ebp, xmm2s);
buffer.Emit<OpCode::CvtFP2SI>(ebp, xmm2);
buffer.Emit<OpCode::CvtSI2FP>(xmm2s, ebp);
buffer.Emit<OpCode::CvtSI2FP>(xmm2, ebp);
buffer.Emit<OpCode::CvtFP2SI>(rbp, xmm2s);
buffer.Emit<OpCode::CvtFP2SI>(rbp, xmm2);
buffer.Emit<OpCode::CvtSI2FP>(xmm2s, rbp);
buffer.Emit<OpCode::CvtSI2FP>(xmm2, rbp);
// Between: xmm2 and rsi
buffer.Emit<OpCode::Mov>(rsi, -4, xmm2s);
buffer.Emit<OpCode::Mov>(rsi, 4, xmm2);
buffer.Emit<OpCode::Mov>(xmm2s, rsi, -4);
buffer.Emit<OpCode::Mov>(xmm2, rsi, 4);
buffer.Emit<OpCode::CvtSI2FP, 4, true, 8, false>(xmm2s, rsi, -4);
buffer.Emit<OpCode::CvtSI2FP, 8, true, 4, false>(xmm2, rsi, 4);
buffer.Emit<OpCode::CvtFP2SI>(esi, xmm2s);
buffer.Emit<OpCode::CvtFP2SI>(esi, xmm2);
buffer.Emit<OpCode::CvtSI2FP>(xmm2s, esi);
buffer.Emit<OpCode::CvtSI2FP>(xmm2, esi);
buffer.Emit<OpCode::CvtFP2SI>(rsi, xmm2s);
buffer.Emit<OpCode::CvtFP2SI>(rsi, xmm2);
buffer.Emit<OpCode::CvtSI2FP>(xmm2s, rsi);
buffer.Emit<OpCode::CvtSI2FP>(xmm2, rsi);
// Between: xmm2 and rdi
buffer.Emit<OpCode::Mov>(rdi, -4, xmm2s);
buffer.Emit<OpCode::Mov>(rdi, 4, xmm2);
buffer.Emit<OpCode::Mov>(xmm2s, rdi, -4);
buffer.Emit<OpCode::Mov>(xmm2, rdi, 4);
buffer.Emit<OpCode::CvtSI2FP, 4, true, 8, false>(xmm2s, rdi, -4);
buffer.Emit<OpCode::CvtSI2FP, 8, true, 4, false>(xmm2, rdi, 4);
buffer.Emit<OpCode::CvtFP2SI>(edi, xmm2s);
buffer.Emit<OpCode::CvtFP2SI>(edi, xmm2);
buffer.Emit<OpCode::CvtSI2FP>(xmm2s, edi);
buffer.Emit<OpCode::CvtSI2FP>(xmm2, edi);
buffer.Emit<OpCode::CvtFP2SI>(rdi, xmm2s);
buffer.Emit<OpCode::CvtFP2SI>(rdi, xmm2);
buffer.Emit<OpCode::CvtSI2FP>(xmm2s, rdi);
buffer.Emit<OpCode::CvtSI2FP>(xmm2, rdi);
// Between: xmm2 and r8
buffer.Emit<OpCode::Mov>(r8, -4, xmm2s);
buffer.Emit<OpCode::Mov>(r8, 4, xmm2);
buffer.Emit<OpCode::Mov>(xmm2s, r8, -4);
buffer.Emit<OpCode::Mov>(xmm2, r8, 4);
buffer.Emit<OpCode::CvtSI2FP, 4, true, 8, false>(xmm2s, r8, -4);
buffer.Emit<OpCode::CvtSI2FP, 8, true, 4, false>(xmm2, r8, 4);
buffer.Emit<OpCode::CvtFP2SI>(r8d, xmm2s);
buffer.Emit<OpCode::CvtFP2SI>(r8d, xmm2);
buffer.Emit<OpCode::CvtSI2FP>(xmm2s, r8d);
buffer.Emit<OpCode::CvtSI2FP>(xmm2, r8d);
buffer.Emit<OpCode::CvtFP2SI>(r8, xmm2s);
buffer.Emit<OpCode::CvtFP2SI>(r8, xmm2);
buffer.Emit<OpCode::CvtSI2FP>(xmm2s, r8);
buffer.Emit<OpCode::CvtSI2FP>(xmm2, r8);
// Between: xmm2 and r9
buffer.Emit<OpCode::Mov>(r9, -4, xmm2s);
buffer.Emit<OpCode::Mov>(r9, 4, xmm2);
buffer.Emit<OpCode::Mov>(xmm2s, r9, -4);
buffer.Emit<OpCode::Mov>(xmm2, r9, 4);
buffer.Emit<OpCode::CvtSI2FP, 4, true, 8, false>(xmm2s, r9, -4);
buffer.Emit<OpCode::CvtSI2FP, 8, true, 4, false>(xmm2, r9, 4);
buffer.Emit<OpCode::CvtFP2SI>(r9d, xmm2s);
buffer.Emit<OpCode::CvtFP2SI>(r9d, xmm2);
buffer.Emit<OpCode::CvtSI2FP>(xmm2s, r9d);
buffer.Emit<OpCode::CvtSI2FP>(xmm2, r9d);
buffer.Emit<OpCode::CvtFP2SI>(r9, xmm2s);
buffer.Emit<OpCode::CvtFP2SI>(r9, xmm2);
buffer.Emit<OpCode::CvtSI2FP>(xmm2s, r9);
buffer.Emit<OpCode::CvtSI2FP>(xmm2, r9);
// Between: xmm2 and r10
buffer.Emit<OpCode::Mov>(r10, -4, xmm2s);
buffer.Emit<OpCode::Mov>(r10, 4, xmm2);
buffer.Emit<OpCode::Mov>(xmm2s, r10, -4);
buffer.Emit<OpCode::Mov>(xmm2, r10, 4);
buffer.Emit<OpCode::CvtSI2FP, 4, true, 8, false>(xmm2s, r10, -4);
buffer.Emit<OpCode::CvtSI2FP, 8, true, 4, false>(xmm2, r10, 4);
buffer.Emit<OpCode::CvtFP2SI>(r10d, xmm2s);
buffer.Emit<OpCode::CvtFP2SI>(r10d, xmm2);
buffer.Emit<OpCode::CvtSI2FP>(xmm2s, r10d);
buffer.Emit<OpCode::CvtSI2FP>(xmm2, r10d);
buffer.Emit<OpCode::CvtFP2SI>(r10, xmm2s);
buffer.Emit<OpCode::CvtFP2SI>(r10, xmm2);
buffer.Emit<OpCode::CvtSI2FP>(xmm2s, r10);
buffer.Emit<OpCode::CvtSI2FP>(xmm2, r10);
// Between: xmm2 and r11
buffer.Emit<OpCode::Mov>(r11, -4, xmm2s);
buffer.Emit<OpCode::Mov>(r11, 4, xmm2);
buffer.Emit<OpCode::Mov>(xmm2s, r11, -4);
buffer.Emit<OpCode::Mov>(xmm2, r11, 4);
buffer.Emit<OpCode::CvtSI2FP, 4, true, 8, false>(xmm2s, r11, -4);
buffer.Emit<OpCode::CvtSI2FP, 8, true, 4, false>(xmm2, r11, 4);
buffer.Emit<OpCode::CvtFP2SI>(r11d, xmm2s);
buffer.Emit<OpCode::CvtFP2SI>(r11d, xmm2);
buffer.Emit<OpCode::CvtSI2FP>(xmm2s, r11d);
buffer.Emit<OpCode::CvtSI2FP>(xmm2, r11d);
buffer.Emit<OpCode::CvtFP2SI>(r11, xmm2s);
buffer.Emit<OpCode::CvtFP2SI>(r11, xmm2);
buffer.Emit<OpCode::CvtSI2FP>(xmm2s, r11);
buffer.Emit<OpCode::CvtSI2FP>(xmm2, r11);
// Between: xmm2 and r12
buffer.Emit<OpCode::Mov>(r12, -4, xmm2s);
buffer.Emit<OpCode::Mov>(r12, 4, xmm2);
buffer.Emit<OpCode::Mov>(xmm2s, r12, -4);
buffer.Emit<OpCode::Mov>(xmm2, r12, 4);
buffer.Emit<OpCode::CvtSI2FP, 4, true, 8, false>(xmm2s, r12, -4);
buffer.Emit<OpCode::CvtSI2FP, 8, true, 4, false>(xmm2, r12, 4);
buffer.Emit<OpCode::CvtFP2SI>(r12d, xmm2s);
buffer.Emit<OpCode::CvtFP2SI>(r12d, xmm2);
buffer.Emit<OpCode::CvtSI2FP>(xmm2s, r12d);
buffer.Emit<OpCode::CvtSI2FP>(xmm2, r12d);
buffer.Emit<OpCode::CvtFP2SI>(r12, xmm2s);
buffer.Emit<OpCode::CvtFP2SI>(r12, xmm2);
buffer.Emit<OpCode::CvtSI2FP>(xmm2s, r12);
buffer.Emit<OpCode::CvtSI2FP>(xmm2, r12);
// Between: xmm2 and r13
buffer.Emit<OpCode::Mov>(r13, -4, xmm2s);
buffer.Emit<OpCode::Mov>(r13, 4, xmm2);
buffer.Emit<OpCode::Mov>(xmm2s, r13, -4);
buffer.Emit<OpCode::Mov>(xmm2, r13, 4);
buffer.Emit<OpCode::CvtSI2FP, 4, true, 8, false>(xmm2s, r13, -4);
buffer.Emit<OpCode::CvtSI2FP, 8, true, 4, false>(xmm2, r13, 4);
buffer.Emit<OpCode::CvtFP2SI>(r13d, xmm2s);
buffer.Emit<OpCode::CvtFP2SI>(r13d, xmm2);
buffer.Emit<OpCode::CvtSI2FP>(xmm2s, r13d);
buffer.Emit<OpCode::CvtSI2FP>(xmm2, r13d);
buffer.Emit<OpCode::CvtFP2SI>(r13, xmm2s);
buffer.Emit<OpCode::CvtFP2SI>(r13, xmm2);
buffer.Emit<OpCode::CvtSI2FP>(xmm2s, r13);
buffer.Emit<OpCode::CvtSI2FP>(xmm2, r13);
// Between: xmm2 and r14
buffer.Emit<OpCode::Mov>(r14, -4, xmm2s);
buffer.Emit<OpCode::Mov>(r14, 4, xmm2);
buffer.Emit<OpCode::Mov>(xmm2s, r14, -4);
buffer.Emit<OpCode::Mov>(xmm2, r14, 4);
buffer.Emit<OpCode::CvtSI2FP, 4, true, 8, false>(xmm2s, r14, -4);
buffer.Emit<OpCode::CvtSI2FP, 8, true, 4, false>(xmm2, r14, 4);
buffer.Emit<OpCode::CvtFP2SI>(r14d, xmm2s);
buffer.Emit<OpCode::CvtFP2SI>(r14d, xmm2);
buffer.Emit<OpCode::CvtSI2FP>(xmm2s, r14d);
buffer.Emit<OpCode::CvtSI2FP>(xmm2, r14d);
buffer.Emit<OpCode::CvtFP2SI>(r14, xmm2s);
buffer.Emit<OpCode::CvtFP2SI>(r14, xmm2);
buffer.Emit<OpCode::CvtSI2FP>(xmm2s, r14);
buffer.Emit<OpCode::CvtSI2FP>(xmm2, r14);
// Between: xmm2 and r15
buffer.Emit<OpCode::Mov>(r15, -4, xmm2s);
buffer.Emit<OpCode::Mov>(r15, 4, xmm2);
buffer.Emit<OpCode::Mov>(xmm2s, r15, -4);
buffer.Emit<OpCode::Mov>(xmm2, r15, 4);
buffer.Emit<OpCode::CvtSI2FP, 4, true, 8, false>(xmm2s, r15, -4);
buffer.Emit<OpCode::CvtSI2FP, 8, true, 4, false>(xmm2, r15, 4);
buffer.Emit<OpCode::CvtFP2SI>(r15d, xmm2s);
buffer.Emit<OpCode::CvtFP2SI>(r15d, xmm2);
buffer.Emit<OpCode::CvtSI2FP>(xmm2s, r15d);
buffer.Emit<OpCode::CvtSI2FP>(xmm2, r15d);
buffer.Emit<OpCode::CvtFP2SI>(r15, xmm2s);
buffer.Emit<OpCode::CvtFP2SI>(r15, xmm2);
buffer.Emit<OpCode::CvtSI2FP>(xmm2s, r15);
buffer.Emit<OpCode::CvtSI2FP>(xmm2, r15);
// Between: xmm3 and rax
buffer.Emit<OpCode::Mov>(rax, -4, xmm3s);
buffer.Emit<OpCode::Mov>(rax, 4, xmm3);
buffer.Emit<OpCode::Mov>(xmm3s, rax, -4);
buffer.Emit<OpCode::Mov>(xmm3, rax, 4);
buffer.Emit<OpCode::CvtSI2FP, 4, true, 8, false>(xmm3s, rax, -4);
buffer.Emit<OpCode::CvtSI2FP, 8, true, 4, false>(xmm3, rax, 4);
buffer.Emit<OpCode::CvtFP2SI>(eax, xmm3s);
buffer.Emit<OpCode::CvtFP2SI>(eax, xmm3);
buffer.Emit<OpCode::CvtSI2FP>(xmm3s, eax);
buffer.Emit<OpCode::CvtSI2FP>(xmm3, eax);
buffer.Emit<OpCode::CvtFP2SI>(rax, xmm3s);
buffer.Emit<OpCode::CvtFP2SI>(rax, xmm3);
buffer.Emit<OpCode::CvtSI2FP>(xmm3s, rax);
buffer.Emit<OpCode::CvtSI2FP>(xmm3, rax);
// Between: xmm3 and rcx
buffer.Emit<OpCode::Mov>(rcx, -4, xmm3s);
buffer.Emit<OpCode::Mov>(rcx, 4, xmm3);
buffer.Emit<OpCode::Mov>(xmm3s, rcx, -4);
buffer.Emit<OpCode::Mov>(xmm3, rcx, 4);
buffer.Emit<OpCode::CvtSI2FP, 4, true, 8, false>(xmm3s, rcx, -4);
buffer.Emit<OpCode::CvtSI2FP, 8, true, 4, false>(xmm3, rcx, 4);
buffer.Emit<OpCode::CvtFP2SI>(ecx, xmm3s);
buffer.Emit<OpCode::CvtFP2SI>(ecx, xmm3);
buffer.Emit<OpCode::CvtSI2FP>(xmm3s, ecx);
buffer.Emit<OpCode::CvtSI2FP>(xmm3, ecx);
buffer.Emit<OpCode::CvtFP2SI>(rcx, xmm3s);
buffer.Emit<OpCode::CvtFP2SI>(rcx, xmm3);
buffer.Emit<OpCode::CvtSI2FP>(xmm3s, rcx);
buffer.Emit<OpCode::CvtSI2FP>(xmm3, rcx);
// Between: xmm3 and rdx
buffer.Emit<OpCode::Mov>(rdx, -4, xmm3s);
buffer.Emit<OpCode::Mov>(rdx, 4, xmm3);
buffer.Emit<OpCode::Mov>(xmm3s, rdx, -4);
buffer.Emit<OpCode::Mov>(xmm3, rdx, 4);
buffer.Emit<OpCode::CvtSI2FP, 4, true, 8, false>(xmm3s, rdx, -4);
buffer.Emit<OpCode::CvtSI2FP, 8, true, 4, false>(xmm3, rdx, 4);
buffer.Emit<OpCode::CvtFP2SI>(edx, xmm3s);
buffer.Emit<OpCode::CvtFP2SI>(edx, xmm3);
buffer.Emit<OpCode::CvtSI2FP>(xmm3s, edx);
buffer.Emit<OpCode::CvtSI2FP>(xmm3, edx);
buffer.Emit<OpCode::CvtFP2SI>(rdx, xmm3s);
buffer.Emit<OpCode::CvtFP2SI>(rdx, xmm3);
buffer.Emit<OpCode::CvtSI2FP>(xmm3s, rdx);
buffer.Emit<OpCode::CvtSI2FP>(xmm3, rdx);
// Between: xmm3 and rbx
buffer.Emit<OpCode::Mov>(rbx, -4, xmm3s);
buffer.Emit<OpCode::Mov>(rbx, 4, xmm3);
buffer.Emit<OpCode::Mov>(xmm3s, rbx, -4);
buffer.Emit<OpCode::Mov>(xmm3, rbx, 4);
buffer.Emit<OpCode::CvtSI2FP, 4, true, 8, false>(xmm3s, rbx, -4);
buffer.Emit<OpCode::CvtSI2FP, 8, true, 4, false>(xmm3, rbx, 4);
buffer.Emit<OpCode::CvtFP2SI>(ebx, xmm3s);
buffer.Emit<OpCode::CvtFP2SI>(ebx, xmm3);
buffer.Emit<OpCode::CvtSI2FP>(xmm3s, ebx);
buffer.Emit<OpCode::CvtSI2FP>(xmm3, ebx);
buffer.Emit<OpCode::CvtFP2SI>(rbx, xmm3s);
buffer.Emit<OpCode::CvtFP2SI>(rbx, xmm3);
buffer.Emit<OpCode::CvtSI2FP>(xmm3s, rbx);
buffer.Emit<OpCode::CvtSI2FP>(xmm3, rbx);
// Between: xmm3 and rsp
buffer.Emit<OpCode::Mov>(rsp, -4, xmm3s);
buffer.Emit<OpCode::Mov>(rsp, 4, xmm3);
buffer.Emit<OpCode::Mov>(xmm3s, rsp, -4);
buffer.Emit<OpCode::Mov>(xmm3, rsp, 4);
buffer.Emit<OpCode::CvtSI2FP, 4, true, 8, false>(xmm3s, rsp, -4);
buffer.Emit<OpCode::CvtSI2FP, 8, true, 4, false>(xmm3, rsp, 4);
buffer.Emit<OpCode::CvtFP2SI>(esp, xmm3s);
buffer.Emit<OpCode::CvtFP2SI>(esp, xmm3);
buffer.Emit<OpCode::CvtSI2FP>(xmm3s, esp);
buffer.Emit<OpCode::CvtSI2FP>(xmm3, esp);
buffer.Emit<OpCode::CvtFP2SI>(rsp, xmm3s);
buffer.Emit<OpCode::CvtFP2SI>(rsp, xmm3);
buffer.Emit<OpCode::CvtSI2FP>(xmm3s, rsp);
buffer.Emit<OpCode::CvtSI2FP>(xmm3, rsp);
// Between: xmm3 and rbp
buffer.Emit<OpCode::Mov>(rbp, -4, xmm3s);
buffer.Emit<OpCode::Mov>(rbp, 4, xmm3);
buffer.Emit<OpCode::Mov>(xmm3s, rbp, -4);
buffer.Emit<OpCode::Mov>(xmm3, rbp, 4);
buffer.Emit<OpCode::CvtSI2FP, 4, true, 8, false>(xmm3s, rbp, -4);
buffer.Emit<OpCode::CvtSI2FP, 8, true, 4, false>(xmm3, rbp, 4);
buffer.Emit<OpCode::CvtFP2SI>(ebp, xmm3s);
buffer.Emit<OpCode::CvtFP2SI>(ebp, xmm3);
buffer.Emit<OpCode::CvtSI2FP>(xmm3s, ebp);
buffer.Emit<OpCode::CvtSI2FP>(xmm3, ebp);
buffer.Emit<OpCode::CvtFP2SI>(rbp, xmm3s);
buffer.Emit<OpCode::CvtFP2SI>(rbp, xmm3);
buffer.Emit<OpCode::CvtSI2FP>(xmm3s, rbp);
buffer.Emit<OpCode::CvtSI2FP>(xmm3, rbp);
// Between: xmm3 and rsi
buffer.Emit<OpCode::Mov>(rsi, -4, xmm3s);
buffer.Emit<OpCode::Mov>(rsi, 4, xmm3);
buffer.Emit<OpCode::Mov>(xmm3s, rsi, -4);
buffer.Emit<OpCode::Mov>(xmm3, rsi, 4);
buffer.Emit<OpCode::CvtSI2FP, 4, true, 8, false>(xmm3s, rsi, -4);
buffer.Emit<OpCode::CvtSI2FP, 8, true, 4, false>(xmm3, rsi, 4);
buffer.Emit<OpCode::CvtFP2SI>(esi, xmm3s);
buffer.Emit<OpCode::CvtFP2SI>(esi, xmm3);
buffer.Emit<OpCode::CvtSI2FP>(xmm3s, esi);
buffer.Emit<OpCode::CvtSI2FP>(xmm3, esi);
buffer.Emit<OpCode::CvtFP2SI>(rsi, xmm3s);
buffer.Emit<OpCode::CvtFP2SI>(rsi, xmm3);
buffer.Emit<OpCode::CvtSI2FP>(xmm3s, rsi);
buffer.Emit<OpCode::CvtSI2FP>(xmm3, rsi);
// Between: xmm3 and rdi
buffer.Emit<OpCode::Mov>(rdi, -4, xmm3s);
buffer.Emit<OpCode::Mov>(rdi, 4, xmm3);
buffer.Emit<OpCode::Mov>(xmm3s, rdi, -4);
buffer.Emit<OpCode::Mov>(xmm3, rdi, 4);
buffer.Emit<OpCode::CvtSI2FP, 4, true, 8, false>(xmm3s, rdi, -4);
buffer.Emit<OpCode::CvtSI2FP, 8, true, 4, false>(xmm3, rdi, 4);
buffer.Emit<OpCode::CvtFP2SI>(edi, xmm3s);
buffer.Emit<OpCode::CvtFP2SI>(edi, xmm3);
buffer.Emit<OpCode::CvtSI2FP>(xmm3s, edi);
buffer.Emit<OpCode::CvtSI2FP>(xmm3, edi);
buffer.Emit<OpCode::CvtFP2SI>(rdi, xmm3s);
buffer.Emit<OpCode::CvtFP2SI>(rdi, xmm3);
buffer.Emit<OpCode::CvtSI2FP>(xmm3s, rdi);
buffer.Emit<OpCode::CvtSI2FP>(xmm3, rdi);
// Between: xmm3 and r8
buffer.Emit<OpCode::Mov>(r8, -4, xmm3s);
buffer.Emit<OpCode::Mov>(r8, 4, xmm3);
buffer.Emit<OpCode::Mov>(xmm3s, r8, -4);
buffer.Emit<OpCode::Mov>(xmm3, r8, 4);
buffer.Emit<OpCode::CvtSI2FP, 4, true, 8, false>(xmm3s, r8, -4);
buffer.Emit<OpCode::CvtSI2FP, 8, true, 4, false>(xmm3, r8, 4);
buffer.Emit<OpCode::CvtFP2SI>(r8d, xmm3s);
buffer.Emit<OpCode::CvtFP2SI>(r8d, xmm3);
buffer.Emit<OpCode::CvtSI2FP>(xmm3s, r8d);
buffer.Emit<OpCode::CvtSI2FP>(xmm3, r8d);
buffer.Emit<OpCode::CvtFP2SI>(r8, xmm3s);
buffer.Emit<OpCode::CvtFP2SI>(r8, xmm3);
buffer.Emit<OpCode::CvtSI2FP>(xmm3s, r8);
buffer.Emit<OpCode::CvtSI2FP>(xmm3, r8);
// Between: xmm3 and r9
buffer.Emit<OpCode::Mov>(r9, -4, xmm3s);
buffer.Emit<OpCode::Mov>(r9, 4, xmm3);
buffer.Emit<OpCode::Mov>(xmm3s, r9, -4);
buffer.Emit<OpCode::Mov>(xmm3, r9, 4);
buffer.Emit<OpCode::CvtSI2FP, 4, true, 8, false>(xmm3s, r9, -4);
buffer.Emit<OpCode::CvtSI2FP, 8, true, 4, false>(xmm3, r9, 4);
buffer.Emit<OpCode::CvtFP2SI>(r9d, xmm3s);
buffer.Emit<OpCode::CvtFP2SI>(r9d, xmm3);
buffer.Emit<OpCode::CvtSI2FP>(xmm3s, r9d);
buffer.Emit<OpCode::CvtSI2FP>(xmm3, r9d);
buffer.Emit<OpCode::CvtFP2SI>(r9, xmm3s);
buffer.Emit<OpCode::CvtFP2SI>(r9, xmm3);
buffer.Emit<OpCode::CvtSI2FP>(xmm3s, r9);
buffer.Emit<OpCode::CvtSI2FP>(xmm3, r9);
// Between: xmm3 and r10
buffer.Emit<OpCode::Mov>(r10, -4, xmm3s);
buffer.Emit<OpCode::Mov>(r10, 4, xmm3);
buffer.Emit<OpCode::Mov>(xmm3s, r10, -4);
buffer.Emit<OpCode::Mov>(xmm3, r10, 4);
buffer.Emit<OpCode::CvtSI2FP, 4, true, 8, false>(xmm3s, r10, -4);
buffer.Emit<OpCode::CvtSI2FP, 8, true, 4, false>(xmm3, r10, 4);
buffer.Emit<OpCode::CvtFP2SI>(r10d, xmm3s);
buffer.Emit<OpCode::CvtFP2SI>(r10d, xmm3);
buffer.Emit<OpCode::CvtSI2FP>(xmm3s, r10d);
buffer.Emit<OpCode::CvtSI2FP>(xmm3, r10d);
buffer.Emit<OpCode::CvtFP2SI>(r10, xmm3s);
buffer.Emit<OpCode::CvtFP2SI>(r10, xmm3);
buffer.Emit<OpCode::CvtSI2FP>(xmm3s, r10);
buffer.Emit<OpCode::CvtSI2FP>(xmm3, r10);
// Between: xmm3 and r11
buffer.Emit<OpCode::Mov>(r11, -4, xmm3s);
buffer.Emit<OpCode::Mov>(r11, 4, xmm3);
buffer.Emit<OpCode::Mov>(xmm3s, r11, -4);
buffer.Emit<OpCode::Mov>(xmm3, r11, 4);
buffer.Emit<OpCode::CvtSI2FP, 4, true, 8, false>(xmm3s, r11, -4);
buffer.Emit<OpCode::CvtSI2FP, 8, true, 4, false>(xmm3, r11, 4);
buffer.Emit<OpCode::CvtFP2SI>(r11d, xmm3s);
buffer.Emit<OpCode::CvtFP2SI>(r11d, xmm3);
buffer.Emit<OpCode::CvtSI2FP>(xmm3s, r11d);
buffer.Emit<OpCode::CvtSI2FP>(xmm3, r11d);
buffer.Emit<OpCode::CvtFP2SI>(r11, xmm3s);
buffer.Emit<OpCode::CvtFP2SI>(r11, xmm3);
buffer.Emit<OpCode::CvtSI2FP>(xmm3s, r11);
buffer.Emit<OpCode::CvtSI2FP>(xmm3, r11);
// Between: xmm3 and r12
buffer.Emit<OpCode::Mov>(r12, -4, xmm3s);
buffer.Emit<OpCode::Mov>(r12, 4, xmm3);
buffer.Emit<OpCode::Mov>(xmm3s, r12, -4);
buffer.Emit<OpCode::Mov>(xmm3, r12, 4);
buffer.Emit<OpCode::CvtSI2FP, 4, true, 8, false>(xmm3s, r12, -4);
buffer.Emit<OpCode::CvtSI2FP, 8, true, 4, false>(xmm3, r12, 4);
buffer.Emit<OpCode::CvtFP2SI>(r12d, xmm3s);
buffer.Emit<OpCode::CvtFP2SI>(r12d, xmm3);
buffer.Emit<OpCode::CvtSI2FP>(xmm3s, r12d);
buffer.Emit<OpCode::CvtSI2FP>(xmm3, r12d);
buffer.Emit<OpCode::CvtFP2SI>(r12, xmm3s);
buffer.Emit<OpCode::CvtFP2SI>(r12, xmm3);
buffer.Emit<OpCode::CvtSI2FP>(xmm3s, r12);
buffer.Emit<OpCode::CvtSI2FP>(xmm3, r12);
// Between: xmm3 and r13
buffer.Emit<OpCode::Mov>(r13, -4, xmm3s);
buffer.Emit<OpCode::Mov>(r13, 4, xmm3);
buffer.Emit<OpCode::Mov>(xmm3s, r13, -4);
buffer.Emit<OpCode::Mov>(xmm3, r13, 4);
buffer.Emit<OpCode::CvtSI2FP, 4, true, 8, false>(xmm3s, r13, -4);
buffer.Emit<OpCode::CvtSI2FP, 8, true, 4, false>(xmm3, r13, 4);
buffer.Emit<OpCode::CvtFP2SI>(r13d, xmm3s);
buffer.Emit<OpCode::CvtFP2SI>(r13d, xmm3);
buffer.Emit<OpCode::CvtSI2FP>(xmm3s, r13d);
buffer.Emit<OpCode::CvtSI2FP>(xmm3, r13d);
buffer.Emit<OpCode::CvtFP2SI>(r13, xmm3s);
buffer.Emit<OpCode::CvtFP2SI>(r13, xmm3);
buffer.Emit<OpCode::CvtSI2FP>(xmm3s, r13);
buffer.Emit<OpCode::CvtSI2FP>(xmm3, r13);
// Between: xmm3 and r14
buffer.Emit<OpCode::Mov>(r14, -4, xmm3s);
buffer.Emit<OpCode::Mov>(r14, 4, xmm3);
buffer.Emit<OpCode::Mov>(xmm3s, r14, -4);
buffer.Emit<OpCode::Mov>(xmm3, r14, 4);
buffer.Emit<OpCode::CvtSI2FP, 4, true, 8, false>(xmm3s, r14, -4);
buffer.Emit<OpCode::CvtSI2FP, 8, true, 4, false>(xmm3, r14, 4);
buffer.Emit<OpCode::CvtFP2SI>(r14d, xmm3s);
buffer.Emit<OpCode::CvtFP2SI>(r14d, xmm3);
buffer.Emit<OpCode::CvtSI2FP>(xmm3s, r14d);
buffer.Emit<OpCode::CvtSI2FP>(xmm3, r14d);
buffer.Emit<OpCode::CvtFP2SI>(r14, xmm3s);
buffer.Emit<OpCode::CvtFP2SI>(r14, xmm3);
buffer.Emit<OpCode::CvtSI2FP>(xmm3s, r14);
buffer.Emit<OpCode::CvtSI2FP>(xmm3, r14);
// Between: xmm3 and r15
buffer.Emit<OpCode::Mov>(r15, -4, xmm3s);
buffer.Emit<OpCode::Mov>(r15, 4, xmm3);
buffer.Emit<OpCode::Mov>(xmm3s, r15, -4);
buffer.Emit<OpCode::Mov>(xmm3, r15, 4);
buffer.Emit<OpCode::CvtSI2FP, 4, true, 8, false>(xmm3s, r15, -4);
buffer.Emit<OpCode::CvtSI2FP, 8, true, 4, false>(xmm3, r15, 4);
buffer.Emit<OpCode::CvtFP2SI>(r15d, xmm3s);
buffer.Emit<OpCode::CvtFP2SI>(r15d, xmm3);
buffer.Emit<OpCode::CvtSI2FP>(xmm3s, r15d);
buffer.Emit<OpCode::CvtSI2FP>(xmm3, r15d);
buffer.Emit<OpCode::CvtFP2SI>(r15, xmm3s);
buffer.Emit<OpCode::CvtFP2SI>(r15, xmm3);
buffer.Emit<OpCode::CvtSI2FP>(xmm3s, r15);
buffer.Emit<OpCode::CvtSI2FP>(xmm3, r15);
// Between: xmm4 and rax
buffer.Emit<OpCode::Mov>(rax, -4, xmm4s);
buffer.Emit<OpCode::Mov>(rax, 4, xmm4);
buffer.Emit<OpCode::Mov>(xmm4s, rax, -4);
buffer.Emit<OpCode::Mov>(xmm4, rax, 4);
buffer.Emit<OpCode::CvtSI2FP, 4, true, 8, false>(xmm4s, rax, -4);
buffer.Emit<OpCode::CvtSI2FP, 8, true, 4, false>(xmm4, rax, 4);
buffer.Emit<OpCode::CvtFP2SI>(eax, xmm4s);
buffer.Emit<OpCode::CvtFP2SI>(eax, xmm4);
buffer.Emit<OpCode::CvtSI2FP>(xmm4s, eax);
buffer.Emit<OpCode::CvtSI2FP>(xmm4, eax);
buffer.Emit<OpCode::CvtFP2SI>(rax, xmm4s);
buffer.Emit<OpCode::CvtFP2SI>(rax, xmm4);
buffer.Emit<OpCode::CvtSI2FP>(xmm4s, rax);
buffer.Emit<OpCode::CvtSI2FP>(xmm4, rax);
// Between: xmm4 and rcx
buffer.Emit<OpCode::Mov>(rcx, -4, xmm4s);
buffer.Emit<OpCode::Mov>(rcx, 4, xmm4);
buffer.Emit<OpCode::Mov>(xmm4s, rcx, -4);
buffer.Emit<OpCode::Mov>(xmm4, rcx, 4);
buffer.Emit<OpCode::CvtSI2FP, 4, true, 8, false>(xmm4s, rcx, -4);
buffer.Emit<OpCode::CvtSI2FP, 8, true, 4, false>(xmm4, rcx, 4);
buffer.Emit<OpCode::CvtFP2SI>(ecx, xmm4s);
buffer.Emit<OpCode::CvtFP2SI>(ecx, xmm4);
buffer.Emit<OpCode::CvtSI2FP>(xmm4s, ecx);
buffer.Emit<OpCode::CvtSI2FP>(xmm4, ecx);
buffer.Emit<OpCode::CvtFP2SI>(rcx, xmm4s);
buffer.Emit<OpCode::CvtFP2SI>(rcx, xmm4);
buffer.Emit<OpCode::CvtSI2FP>(xmm4s, rcx);
buffer.Emit<OpCode::CvtSI2FP>(xmm4, rcx);
// Between: xmm4 and rdx
buffer.Emit<OpCode::Mov>(rdx, -4, xmm4s);
buffer.Emit<OpCode::Mov>(rdx, 4, xmm4);
buffer.Emit<OpCode::Mov>(xmm4s, rdx, -4);
buffer.Emit<OpCode::Mov>(xmm4, rdx, 4);
buffer.Emit<OpCode::CvtSI2FP, 4, true, 8, false>(xmm4s, rdx, -4);
buffer.Emit<OpCode::CvtSI2FP, 8, true, 4, false>(xmm4, rdx, 4);
buffer.Emit<OpCode::CvtFP2SI>(edx, xmm4s);
buffer.Emit<OpCode::CvtFP2SI>(edx, xmm4);
buffer.Emit<OpCode::CvtSI2FP>(xmm4s, edx);
buffer.Emit<OpCode::CvtSI2FP>(xmm4, edx);
buffer.Emit<OpCode::CvtFP2SI>(rdx, xmm4s);
buffer.Emit<OpCode::CvtFP2SI>(rdx, xmm4);
buffer.Emit<OpCode::CvtSI2FP>(xmm4s, rdx);
buffer.Emit<OpCode::CvtSI2FP>(xmm4, rdx);
// Between: xmm4 and rbx
buffer.Emit<OpCode::Mov>(rbx, -4, xmm4s);
buffer.Emit<OpCode::Mov>(rbx, 4, xmm4);
buffer.Emit<OpCode::Mov>(xmm4s, rbx, -4);
buffer.Emit<OpCode::Mov>(xmm4, rbx, 4);
buffer.Emit<OpCode::CvtSI2FP, 4, true, 8, false>(xmm4s, rbx, -4);
buffer.Emit<OpCode::CvtSI2FP, 8, true, 4, false>(xmm4, rbx, 4);
buffer.Emit<OpCode::CvtFP2SI>(ebx, xmm4s);
buffer.Emit<OpCode::CvtFP2SI>(ebx, xmm4);
buffer.Emit<OpCode::CvtSI2FP>(xmm4s, ebx);
buffer.Emit<OpCode::CvtSI2FP>(xmm4, ebx);
buffer.Emit<OpCode::CvtFP2SI>(rbx, xmm4s);
buffer.Emit<OpCode::CvtFP2SI>(rbx, xmm4);
buffer.Emit<OpCode::CvtSI2FP>(xmm4s, rbx);
buffer.Emit<OpCode::CvtSI2FP>(xmm4, rbx);
// Between: xmm4 and rsp
buffer.Emit<OpCode::Mov>(rsp, -4, xmm4s);
buffer.Emit<OpCode::Mov>(rsp, 4, xmm4);
buffer.Emit<OpCode::Mov>(xmm4s, rsp, -4);
buffer.Emit<OpCode::Mov>(xmm4, rsp, 4);
buffer.Emit<OpCode::CvtSI2FP, 4, true, 8, false>(xmm4s, rsp, -4);
buffer.Emit<OpCode::CvtSI2FP, 8, true, 4, false>(xmm4, rsp, 4);
buffer.Emit<OpCode::CvtFP2SI>(esp, xmm4s);
buffer.Emit<OpCode::CvtFP2SI>(esp, xmm4);
buffer.Emit<OpCode::CvtSI2FP>(xmm4s, esp);
buffer.Emit<OpCode::CvtSI2FP>(xmm4, esp);
buffer.Emit<OpCode::CvtFP2SI>(rsp, xmm4s);
buffer.Emit<OpCode::CvtFP2SI>(rsp, xmm4);
buffer.Emit<OpCode::CvtSI2FP>(xmm4s, rsp);
buffer.Emit<OpCode::CvtSI2FP>(xmm4, rsp);
// Between: xmm4 and rbp
buffer.Emit<OpCode::Mov>(rbp, -4, xmm4s);
buffer.Emit<OpCode::Mov>(rbp, 4, xmm4);
buffer.Emit<OpCode::Mov>(xmm4s, rbp, -4);
buffer.Emit<OpCode::Mov>(xmm4, rbp, 4);
buffer.Emit<OpCode::CvtSI2FP, 4, true, 8, false>(xmm4s, rbp, -4);
buffer.Emit<OpCode::CvtSI2FP, 8, true, 4, false>(xmm4, rbp, 4);
buffer.Emit<OpCode::CvtFP2SI>(ebp, xmm4s);
buffer.Emit<OpCode::CvtFP2SI>(ebp, xmm4);
buffer.Emit<OpCode::CvtSI2FP>(xmm4s, ebp);
buffer.Emit<OpCode::CvtSI2FP>(xmm4, ebp);
buffer.Emit<OpCode::CvtFP2SI>(rbp, xmm4s);
buffer.Emit<OpCode::CvtFP2SI>(rbp, xmm4);
buffer.Emit<OpCode::CvtSI2FP>(xmm4s, rbp);
buffer.Emit<OpCode::CvtSI2FP>(xmm4, rbp);
// Between: xmm4 and rsi
buffer.Emit<OpCode::Mov>(rsi, -4, xmm4s);
buffer.Emit<OpCode::Mov>(rsi, 4, xmm4);
buffer.Emit<OpCode::Mov>(xmm4s, rsi, -4);
buffer.Emit<OpCode::Mov>(xmm4, rsi, 4);
buffer.Emit<OpCode::CvtSI2FP, 4, true, 8, false>(xmm4s, rsi, -4);
buffer.Emit<OpCode::CvtSI2FP, 8, true, 4, false>(xmm4, rsi, 4);
buffer.Emit<OpCode::CvtFP2SI>(esi, xmm4s);
buffer.Emit<OpCode::CvtFP2SI>(esi, xmm4);
buffer.Emit<OpCode::CvtSI2FP>(xmm4s, esi);
buffer.Emit<OpCode::CvtSI2FP>(xmm4, esi);
buffer.Emit<OpCode::CvtFP2SI>(rsi, xmm4s);
buffer.Emit<OpCode::CvtFP2SI>(rsi, xmm4);
buffer.Emit<OpCode::CvtSI2FP>(xmm4s, rsi);
buffer.Emit<OpCode::CvtSI2FP>(xmm4, rsi);
// Between: xmm4 and rdi
buffer.Emit<OpCode::Mov>(rdi, -4, xmm4s);
buffer.Emit<OpCode::Mov>(rdi, 4, xmm4);
buffer.Emit<OpCode::Mov>(xmm4s, rdi, -4);
buffer.Emit<OpCode::Mov>(xmm4, rdi, 4);
buffer.Emit<OpCode::CvtSI2FP, 4, true, 8, false>(xmm4s, rdi, -4);
buffer.Emit<OpCode::CvtSI2FP, 8, true, 4, false>(xmm4, rdi, 4);
buffer.Emit<OpCode::CvtFP2SI>(edi, xmm4s);
buffer.Emit<OpCode::CvtFP2SI>(edi, xmm4);
buffer.Emit<OpCode::CvtSI2FP>(xmm4s, edi);
buffer.Emit<OpCode::CvtSI2FP>(xmm4, edi);
buffer.Emit<OpCode::CvtFP2SI>(rdi, xmm4s);
buffer.Emit<OpCode::CvtFP2SI>(rdi, xmm4);
buffer.Emit<OpCode::CvtSI2FP>(xmm4s, rdi);
buffer.Emit<OpCode::CvtSI2FP>(xmm4, rdi);
// Between: xmm4 and r8
buffer.Emit<OpCode::Mov>(r8, -4, xmm4s);
buffer.Emit<OpCode::Mov>(r8, 4, xmm4);
buffer.Emit<OpCode::Mov>(xmm4s, r8, -4);
buffer.Emit<OpCode::Mov>(xmm4, r8, 4);
buffer.Emit<OpCode::CvtSI2FP, 4, true, 8, false>(xmm4s, r8, -4);
buffer.Emit<OpCode::CvtSI2FP, 8, true, 4, false>(xmm4, r8, 4);
buffer.Emit<OpCode::CvtFP2SI>(r8d, xmm4s);
buffer.Emit<OpCode::CvtFP2SI>(r8d, xmm4);
buffer.Emit<OpCode::CvtSI2FP>(xmm4s, r8d);
buffer.Emit<OpCode::CvtSI2FP>(xmm4, r8d);
buffer.Emit<OpCode::CvtFP2SI>(r8, xmm4s);
buffer.Emit<OpCode::CvtFP2SI>(r8, xmm4);
buffer.Emit<OpCode::CvtSI2FP>(xmm4s, r8);
buffer.Emit<OpCode::CvtSI2FP>(xmm4, r8);
// Between: xmm4 and r9
buffer.Emit<OpCode::Mov>(r9, -4, xmm4s);
buffer.Emit<OpCode::Mov>(r9, 4, xmm4);
buffer.Emit<OpCode::Mov>(xmm4s, r9, -4);
buffer.Emit<OpCode::Mov>(xmm4, r9, 4);
buffer.Emit<OpCode::CvtSI2FP, 4, true, 8, false>(xmm4s, r9, -4);
buffer.Emit<OpCode::CvtSI2FP, 8, true, 4, false>(xmm4, r9, 4);
buffer.Emit<OpCode::CvtFP2SI>(r9d, xmm4s);
buffer.Emit<OpCode::CvtFP2SI>(r9d, xmm4);
buffer.Emit<OpCode::CvtSI2FP>(xmm4s, r9d);
buffer.Emit<OpCode::CvtSI2FP>(xmm4, r9d);
buffer.Emit<OpCode::CvtFP2SI>(r9, xmm4s);
buffer.Emit<OpCode::CvtFP2SI>(r9, xmm4);
buffer.Emit<OpCode::CvtSI2FP>(xmm4s, r9);
buffer.Emit<OpCode::CvtSI2FP>(xmm4, r9);
// Between: xmm4 and r10
buffer.Emit<OpCode::Mov>(r10, -4, xmm4s);
buffer.Emit<OpCode::Mov>(r10, 4, xmm4);
buffer.Emit<OpCode::Mov>(xmm4s, r10, -4);
buffer.Emit<OpCode::Mov>(xmm4, r10, 4);
buffer.Emit<OpCode::CvtSI2FP, 4, true, 8, false>(xmm4s, r10, -4);
buffer.Emit<OpCode::CvtSI2FP, 8, true, 4, false>(xmm4, r10, 4);
buffer.Emit<OpCode::CvtFP2SI>(r10d, xmm4s);
buffer.Emit<OpCode::CvtFP2SI>(r10d, xmm4);
buffer.Emit<OpCode::CvtSI2FP>(xmm4s, r10d);
buffer.Emit<OpCode::CvtSI2FP>(xmm4, r10d);
buffer.Emit<OpCode::CvtFP2SI>(r10, xmm4s);
buffer.Emit<OpCode::CvtFP2SI>(r10, xmm4);
buffer.Emit<OpCode::CvtSI2FP>(xmm4s, r10);
buffer.Emit<OpCode::CvtSI2FP>(xmm4, r10);
// Between: xmm4 and r11
buffer.Emit<OpCode::Mov>(r11, -4, xmm4s);
buffer.Emit<OpCode::Mov>(r11, 4, xmm4);
buffer.Emit<OpCode::Mov>(xmm4s, r11, -4);
buffer.Emit<OpCode::Mov>(xmm4, r11, 4);
buffer.Emit<OpCode::CvtSI2FP, 4, true, 8, false>(xmm4s, r11, -4);
buffer.Emit<OpCode::CvtSI2FP, 8, true, 4, false>(xmm4, r11, 4);
buffer.Emit<OpCode::CvtFP2SI>(r11d, xmm4s);
buffer.Emit<OpCode::CvtFP2SI>(r11d, xmm4);
buffer.Emit<OpCode::CvtSI2FP>(xmm4s, r11d);
buffer.Emit<OpCode::CvtSI2FP>(xmm4, r11d);
buffer.Emit<OpCode::CvtFP2SI>(r11, xmm4s);
buffer.Emit<OpCode::CvtFP2SI>(r11, xmm4);
buffer.Emit<OpCode::CvtSI2FP>(xmm4s, r11);
buffer.Emit<OpCode::CvtSI2FP>(xmm4, r11);
// Between: xmm4 and r12
buffer.Emit<OpCode::Mov>(r12, -4, xmm4s);
buffer.Emit<OpCode::Mov>(r12, 4, xmm4);
buffer.Emit<OpCode::Mov>(xmm4s, r12, -4);
buffer.Emit<OpCode::Mov>(xmm4, r12, 4);
buffer.Emit<OpCode::CvtSI2FP, 4, true, 8, false>(xmm4s, r12, -4);
buffer.Emit<OpCode::CvtSI2FP, 8, true, 4, false>(xmm4, r12, 4);
buffer.Emit<OpCode::CvtFP2SI>(r12d, xmm4s);
buffer.Emit<OpCode::CvtFP2SI>(r12d, xmm4);
buffer.Emit<OpCode::CvtSI2FP>(xmm4s, r12d);
buffer.Emit<OpCode::CvtSI2FP>(xmm4, r12d);
buffer.Emit<OpCode::CvtFP2SI>(r12, xmm4s);
buffer.Emit<OpCode::CvtFP2SI>(r12, xmm4);
buffer.Emit<OpCode::CvtSI2FP>(xmm4s, r12);
buffer.Emit<OpCode::CvtSI2FP>(xmm4, r12);
// Between: xmm4 and r13
buffer.Emit<OpCode::Mov>(r13, -4, xmm4s);
buffer.Emit<OpCode::Mov>(r13, 4, xmm4);
buffer.Emit<OpCode::Mov>(xmm4s, r13, -4);
buffer.Emit<OpCode::Mov>(xmm4, r13, 4);
buffer.Emit<OpCode::CvtSI2FP, 4, true, 8, false>(xmm4s, r13, -4);
buffer.Emit<OpCode::CvtSI2FP, 8, true, 4, false>(xmm4, r13, 4);
buffer.Emit<OpCode::CvtFP2SI>(r13d, xmm4s);
buffer.Emit<OpCode::CvtFP2SI>(r13d, xmm4);
buffer.Emit<OpCode::CvtSI2FP>(xmm4s, r13d);
buffer.Emit<OpCode::CvtSI2FP>(xmm4, r13d);
buffer.Emit<OpCode::CvtFP2SI>(r13, xmm4s);
buffer.Emit<OpCode::CvtFP2SI>(r13, xmm4);
buffer.Emit<OpCode::CvtSI2FP>(xmm4s, r13);
buffer.Emit<OpCode::CvtSI2FP>(xmm4, r13);
// Between: xmm4 and r14
buffer.Emit<OpCode::Mov>(r14, -4, xmm4s);
buffer.Emit<OpCode::Mov>(r14, 4, xmm4);
buffer.Emit<OpCode::Mov>(xmm4s, r14, -4);
buffer.Emit<OpCode::Mov>(xmm4, r14, 4);
buffer.Emit<OpCode::CvtSI2FP, 4, true, 8, false>(xmm4s, r14, -4);
buffer.Emit<OpCode::CvtSI2FP, 8, true, 4, false>(xmm4, r14, 4);
buffer.Emit<OpCode::CvtFP2SI>(r14d, xmm4s);
buffer.Emit<OpCode::CvtFP2SI>(r14d, xmm4);
buffer.Emit<OpCode::CvtSI2FP>(xmm4s, r14d);
buffer.Emit<OpCode::CvtSI2FP>(xmm4, r14d);
buffer.Emit<OpCode::CvtFP2SI>(r14, xmm4s);
buffer.Emit<OpCode::CvtFP2SI>(r14, xmm4);
buffer.Emit<OpCode::CvtSI2FP>(xmm4s, r14);
buffer.Emit<OpCode::CvtSI2FP>(xmm4, r14);
// Between: xmm4 and r15
buffer.Emit<OpCode::Mov>(r15, -4, xmm4s);
buffer.Emit<OpCode::Mov>(r15, 4, xmm4);
buffer.Emit<OpCode::Mov>(xmm4s, r15, -4);
buffer.Emit<OpCode::Mov>(xmm4, r15, 4);
buffer.Emit<OpCode::CvtSI2FP, 4, true, 8, false>(xmm4s, r15, -4);
buffer.Emit<OpCode::CvtSI2FP, 8, true, 4, false>(xmm4, r15, 4);
buffer.Emit<OpCode::CvtFP2SI>(r15d, xmm4s);
buffer.Emit<OpCode::CvtFP2SI>(r15d, xmm4);
buffer.Emit<OpCode::CvtSI2FP>(xmm4s, r15d);
buffer.Emit<OpCode::CvtSI2FP>(xmm4, r15d);
buffer.Emit<OpCode::CvtFP2SI>(r15, xmm4s);
buffer.Emit<OpCode::CvtFP2SI>(r15, xmm4);
buffer.Emit<OpCode::CvtSI2FP>(xmm4s, r15);
buffer.Emit<OpCode::CvtSI2FP>(xmm4, r15);
// Between: xmm5 and rax
buffer.Emit<OpCode::Mov>(rax, -4, xmm5s);
buffer.Emit<OpCode::Mov>(rax, 4, xmm5);
buffer.Emit<OpCode::Mov>(xmm5s, rax, -4);
buffer.Emit<OpCode::Mov>(xmm5, rax, 4);
buffer.Emit<OpCode::CvtSI2FP, 4, true, 8, false>(xmm5s, rax, -4);
buffer.Emit<OpCode::CvtSI2FP, 8, true, 4, false>(xmm5, rax, 4);
buffer.Emit<OpCode::CvtFP2SI>(eax, xmm5s);
buffer.Emit<OpCode::CvtFP2SI>(eax, xmm5);
buffer.Emit<OpCode::CvtSI2FP>(xmm5s, eax);
buffer.Emit<OpCode::CvtSI2FP>(xmm5, eax);
buffer.Emit<OpCode::CvtFP2SI>(rax, xmm5s);
buffer.Emit<OpCode::CvtFP2SI>(rax, xmm5);
buffer.Emit<OpCode::CvtSI2FP>(xmm5s, rax);
buffer.Emit<OpCode::CvtSI2FP>(xmm5, rax);
// Between: xmm5 and rcx
buffer.Emit<OpCode::Mov>(rcx, -4, xmm5s);
buffer.Emit<OpCode::Mov>(rcx, 4, xmm5);
buffer.Emit<OpCode::Mov>(xmm5s, rcx, -4);
buffer.Emit<OpCode::Mov>(xmm5, rcx, 4);
buffer.Emit<OpCode::CvtSI2FP, 4, true, 8, false>(xmm5s, rcx, -4);
buffer.Emit<OpCode::CvtSI2FP, 8, true, 4, false>(xmm5, rcx, 4);
buffer.Emit<OpCode::CvtFP2SI>(ecx, xmm5s);
buffer.Emit<OpCode::CvtFP2SI>(ecx, xmm5);
buffer.Emit<OpCode::CvtSI2FP>(xmm5s, ecx);
buffer.Emit<OpCode::CvtSI2FP>(xmm5, ecx);
buffer.Emit<OpCode::CvtFP2SI>(rcx, xmm5s);
buffer.Emit<OpCode::CvtFP2SI>(rcx, xmm5);
buffer.Emit<OpCode::CvtSI2FP>(xmm5s, rcx);
buffer.Emit<OpCode::CvtSI2FP>(xmm5, rcx);
// Between: xmm5 and rdx
buffer.Emit<OpCode::Mov>(rdx, -4, xmm5s);
buffer.Emit<OpCode::Mov>(rdx, 4, xmm5);
buffer.Emit<OpCode::Mov>(xmm5s, rdx, -4);
buffer.Emit<OpCode::Mov>(xmm5, rdx, 4);
buffer.Emit<OpCode::CvtSI2FP, 4, true, 8, false>(xmm5s, rdx, -4);
buffer.Emit<OpCode::CvtSI2FP, 8, true, 4, false>(xmm5, rdx, 4);
buffer.Emit<OpCode::CvtFP2SI>(edx, xmm5s);
buffer.Emit<OpCode::CvtFP2SI>(edx, xmm5);
buffer.Emit<OpCode::CvtSI2FP>(xmm5s, edx);
buffer.Emit<OpCode::CvtSI2FP>(xmm5, edx);
buffer.Emit<OpCode::CvtFP2SI>(rdx, xmm5s);
buffer.Emit<OpCode::CvtFP2SI>(rdx, xmm5);
buffer.Emit<OpCode::CvtSI2FP>(xmm5s, rdx);
buffer.Emit<OpCode::CvtSI2FP>(xmm5, rdx);
// Between: xmm5 and rbx
buffer.Emit<OpCode::Mov>(rbx, -4, xmm5s);
buffer.Emit<OpCode::Mov>(rbx, 4, xmm5);
buffer.Emit<OpCode::Mov>(xmm5s, rbx, -4);
buffer.Emit<OpCode::Mov>(xmm5, rbx, 4);
buffer.Emit<OpCode::CvtSI2FP, 4, true, 8, false>(xmm5s, rbx, -4);
buffer.Emit<OpCode::CvtSI2FP, 8, true, 4, false>(xmm5, rbx, 4);
buffer.Emit<OpCode::CvtFP2SI>(ebx, xmm5s);
buffer.Emit<OpCode::CvtFP2SI>(ebx, xmm5);
buffer.Emit<OpCode::CvtSI2FP>(xmm5s, ebx);
buffer.Emit<OpCode::CvtSI2FP>(xmm5, ebx);
buffer.Emit<OpCode::CvtFP2SI>(rbx, xmm5s);
buffer.Emit<OpCode::CvtFP2SI>(rbx, xmm5);
buffer.Emit<OpCode::CvtSI2FP>(xmm5s, rbx);
buffer.Emit<OpCode::CvtSI2FP>(xmm5, rbx);
// Between: xmm5 and rsp
buffer.Emit<OpCode::Mov>(rsp, -4, xmm5s);
buffer.Emit<OpCode::Mov>(rsp, 4, xmm5);
buffer.Emit<OpCode::Mov>(xmm5s, rsp, -4);
buffer.Emit<OpCode::Mov>(xmm5, rsp, 4);
buffer.Emit<OpCode::CvtSI2FP, 4, true, 8, false>(xmm5s, rsp, -4);
buffer.Emit<OpCode::CvtSI2FP, 8, true, 4, false>(xmm5, rsp, 4);
buffer.Emit<OpCode::CvtFP2SI>(esp, xmm5s);
buffer.Emit<OpCode::CvtFP2SI>(esp, xmm5);
buffer.Emit<OpCode::CvtSI2FP>(xmm5s, esp);
buffer.Emit<OpCode::CvtSI2FP>(xmm5, esp);
buffer.Emit<OpCode::CvtFP2SI>(rsp, xmm5s);
buffer.Emit<OpCode::CvtFP2SI>(rsp, xmm5);
buffer.Emit<OpCode::CvtSI2FP>(xmm5s, rsp);
buffer.Emit<OpCode::CvtSI2FP>(xmm5, rsp);
// Between: xmm5 and rbp
buffer.Emit<OpCode::Mov>(rbp, -4, xmm5s);
buffer.Emit<OpCode::Mov>(rbp, 4, xmm5);
buffer.Emit<OpCode::Mov>(xmm5s, rbp, -4);
buffer.Emit<OpCode::Mov>(xmm5, rbp, 4);
buffer.Emit<OpCode::CvtSI2FP, 4, true, 8, false>(xmm5s, rbp, -4);
buffer.Emit<OpCode::CvtSI2FP, 8, true, 4, false>(xmm5, rbp, 4);
buffer.Emit<OpCode::CvtFP2SI>(ebp, xmm5s);
buffer.Emit<OpCode::CvtFP2SI>(ebp, xmm5);
buffer.Emit<OpCode::CvtSI2FP>(xmm5s, ebp);
buffer.Emit<OpCode::CvtSI2FP>(xmm5, ebp);
buffer.Emit<OpCode::CvtFP2SI>(rbp, xmm5s);
buffer.Emit<OpCode::CvtFP2SI>(rbp, xmm5);
buffer.Emit<OpCode::CvtSI2FP>(xmm5s, rbp);
buffer.Emit<OpCode::CvtSI2FP>(xmm5, rbp);
// Between: xmm5 and rsi
buffer.Emit<OpCode::Mov>(rsi, -4, xmm5s);
buffer.Emit<OpCode::Mov>(rsi, 4, xmm5);
buffer.Emit<OpCode::Mov>(xmm5s, rsi, -4);
buffer.Emit<OpCode::Mov>(xmm5, rsi, 4);
buffer.Emit<OpCode::CvtSI2FP, 4, true, 8, false>(xmm5s, rsi, -4);
buffer.Emit<OpCode::CvtSI2FP, 8, true, 4, false>(xmm5, rsi, 4);
buffer.Emit<OpCode::CvtFP2SI>(esi, xmm5s);
buffer.Emit<OpCode::CvtFP2SI>(esi, xmm5);
buffer.Emit<OpCode::CvtSI2FP>(xmm5s, esi);
buffer.Emit<OpCode::CvtSI2FP>(xmm5, esi);
buffer.Emit<OpCode::CvtFP2SI>(rsi, xmm5s);
buffer.Emit<OpCode::CvtFP2SI>(rsi, xmm5);
buffer.Emit<OpCode::CvtSI2FP>(xmm5s, rsi);
buffer.Emit<OpCode::CvtSI2FP>(xmm5, rsi);
// Between: xmm5 and rdi
buffer.Emit<OpCode::Mov>(rdi, -4, xmm5s);
buffer.Emit<OpCode::Mov>(rdi, 4, xmm5);
buffer.Emit<OpCode::Mov>(xmm5s, rdi, -4);
buffer.Emit<OpCode::Mov>(xmm5, rdi, 4);
buffer.Emit<OpCode::CvtSI2FP, 4, true, 8, false>(xmm5s, rdi, -4);
buffer.Emit<OpCode::CvtSI2FP, 8, true, 4, false>(xmm5, rdi, 4);
buffer.Emit<OpCode::CvtFP2SI>(edi, xmm5s);
buffer.Emit<OpCode::CvtFP2SI>(edi, xmm5);
buffer.Emit<OpCode::CvtSI2FP>(xmm5s, edi);
buffer.Emit<OpCode::CvtSI2FP>(xmm5, edi);
buffer.Emit<OpCode::CvtFP2SI>(rdi, xmm5s);
buffer.Emit<OpCode::CvtFP2SI>(rdi, xmm5);
buffer.Emit<OpCode::CvtSI2FP>(xmm5s, rdi);
buffer.Emit<OpCode::CvtSI2FP>(xmm5, rdi);
// Between: xmm5 and r8
buffer.Emit<OpCode::Mov>(r8, -4, xmm5s);
buffer.Emit<OpCode::Mov>(r8, 4, xmm5);
buffer.Emit<OpCode::Mov>(xmm5s, r8, -4);
buffer.Emit<OpCode::Mov>(xmm5, r8, 4);
buffer.Emit<OpCode::CvtSI2FP, 4, true, 8, false>(xmm5s, r8, -4);
buffer.Emit<OpCode::CvtSI2FP, 8, true, 4, false>(xmm5, r8, 4);
buffer.Emit<OpCode::CvtFP2SI>(r8d, xmm5s);
buffer.Emit<OpCode::CvtFP2SI>(r8d, xmm5);
buffer.Emit<OpCode::CvtSI2FP>(xmm5s, r8d);
buffer.Emit<OpCode::CvtSI2FP>(xmm5, r8d);
buffer.Emit<OpCode::CvtFP2SI>(r8, xmm5s);
buffer.Emit<OpCode::CvtFP2SI>(r8, xmm5);
buffer.Emit<OpCode::CvtSI2FP>(xmm5s, r8);
buffer.Emit<OpCode::CvtSI2FP>(xmm5, r8);
// Between: xmm5 and r9
buffer.Emit<OpCode::Mov>(r9, -4, xmm5s);
buffer.Emit<OpCode::Mov>(r9, 4, xmm5);
buffer.Emit<OpCode::Mov>(xmm5s, r9, -4);
buffer.Emit<OpCode::Mov>(xmm5, r9, 4);
buffer.Emit<OpCode::CvtSI2FP, 4, true, 8, false>(xmm5s, r9, -4);
buffer.Emit<OpCode::CvtSI2FP, 8, true, 4, false>(xmm5, r9, 4);
buffer.Emit<OpCode::CvtFP2SI>(r9d, xmm5s);
buffer.Emit<OpCode::CvtFP2SI>(r9d, xmm5);
buffer.Emit<OpCode::CvtSI2FP>(xmm5s, r9d);
buffer.Emit<OpCode::CvtSI2FP>(xmm5, r9d);
buffer.Emit<OpCode::CvtFP2SI>(r9, xmm5s);
buffer.Emit<OpCode::CvtFP2SI>(r9, xmm5);
buffer.Emit<OpCode::CvtSI2FP>(xmm5s, r9);
buffer.Emit<OpCode::CvtSI2FP>(xmm5, r9);
// Between: xmm5 and r10
buffer.Emit<OpCode::Mov>(r10, -4, xmm5s);
buffer.Emit<OpCode::Mov>(r10, 4, xmm5);
buffer.Emit<OpCode::Mov>(xmm5s, r10, -4);
buffer.Emit<OpCode::Mov>(xmm5, r10, 4);
buffer.Emit<OpCode::CvtSI2FP, 4, true, 8, false>(xmm5s, r10, -4);
buffer.Emit<OpCode::CvtSI2FP, 8, true, 4, false>(xmm5, r10, 4);
buffer.Emit<OpCode::CvtFP2SI>(r10d, xmm5s);
buffer.Emit<OpCode::CvtFP2SI>(r10d, xmm5);
buffer.Emit<OpCode::CvtSI2FP>(xmm5s, r10d);
buffer.Emit<OpCode::CvtSI2FP>(xmm5, r10d);
buffer.Emit<OpCode::CvtFP2SI>(r10, xmm5s);
buffer.Emit<OpCode::CvtFP2SI>(r10, xmm5);
buffer.Emit<OpCode::CvtSI2FP>(xmm5s, r10);
buffer.Emit<OpCode::CvtSI2FP>(xmm5, r10);
// Between: xmm5 and r11
buffer.Emit<OpCode::Mov>(r11, -4, xmm5s);
buffer.Emit<OpCode::Mov>(r11, 4, xmm5);
buffer.Emit<OpCode::Mov>(xmm5s, r11, -4);
buffer.Emit<OpCode::Mov>(xmm5, r11, 4);
buffer.Emit<OpCode::CvtSI2FP, 4, true, 8, false>(xmm5s, r11, -4);
buffer.Emit<OpCode::CvtSI2FP, 8, true, 4, false>(xmm5, r11, 4);
buffer.Emit<OpCode::CvtFP2SI>(r11d, xmm5s);
buffer.Emit<OpCode::CvtFP2SI>(r11d, xmm5);
buffer.Emit<OpCode::CvtSI2FP>(xmm5s, r11d);
buffer.Emit<OpCode::CvtSI2FP>(xmm5, r11d);
buffer.Emit<OpCode::CvtFP2SI>(r11, xmm5s);
buffer.Emit<OpCode::CvtFP2SI>(r11, xmm5);
buffer.Emit<OpCode::CvtSI2FP>(xmm5s, r11);
buffer.Emit<OpCode::CvtSI2FP>(xmm5, r11);
// Between: xmm5 and r12
buffer.Emit<OpCode::Mov>(r12, -4, xmm5s);
buffer.Emit<OpCode::Mov>(r12, 4, xmm5);
buffer.Emit<OpCode::Mov>(xmm5s, r12, -4);
buffer.Emit<OpCode::Mov>(xmm5, r12, 4);
buffer.Emit<OpCode::CvtSI2FP, 4, true, 8, false>(xmm5s, r12, -4);
buffer.Emit<OpCode::CvtSI2FP, 8, true, 4, false>(xmm5, r12, 4);
buffer.Emit<OpCode::CvtFP2SI>(r12d, xmm5s);
buffer.Emit<OpCode::CvtFP2SI>(r12d, xmm5);
buffer.Emit<OpCode::CvtSI2FP>(xmm5s, r12d);
buffer.Emit<OpCode::CvtSI2FP>(xmm5, r12d);
buffer.Emit<OpCode::CvtFP2SI>(r12, xmm5s);
buffer.Emit<OpCode::CvtFP2SI>(r12, xmm5);
buffer.Emit<OpCode::CvtSI2FP>(xmm5s, r12);
buffer.Emit<OpCode::CvtSI2FP>(xmm5, r12);
// Between: xmm5 and r13
buffer.Emit<OpCode::Mov>(r13, -4, xmm5s);
buffer.Emit<OpCode::Mov>(r13, 4, xmm5);
buffer.Emit<OpCode::Mov>(xmm5s, r13, -4);
buffer.Emit<OpCode::Mov>(xmm5, r13, 4);
buffer.Emit<OpCode::CvtSI2FP, 4, true, 8, false>(xmm5s, r13, -4);
buffer.Emit<OpCode::CvtSI2FP, 8, true, 4, false>(xmm5, r13, 4);
buffer.Emit<OpCode::CvtFP2SI>(r13d, xmm5s);
buffer.Emit<OpCode::CvtFP2SI>(r13d, xmm5);
buffer.Emit<OpCode::CvtSI2FP>(xmm5s, r13d);
buffer.Emit<OpCode::CvtSI2FP>(xmm5, r13d);
buffer.Emit<OpCode::CvtFP2SI>(r13, xmm5s);
buffer.Emit<OpCode::CvtFP2SI>(r13, xmm5);
buffer.Emit<OpCode::CvtSI2FP>(xmm5s, r13);
buffer.Emit<OpCode::CvtSI2FP>(xmm5, r13);
// Between: xmm5 and r14
buffer.Emit<OpCode::Mov>(r14, -4, xmm5s);
buffer.Emit<OpCode::Mov>(r14, 4, xmm5);
buffer.Emit<OpCode::Mov>(xmm5s, r14, -4);
buffer.Emit<OpCode::Mov>(xmm5, r14, 4);
buffer.Emit<OpCode::CvtSI2FP, 4, true, 8, false>(xmm5s, r14, -4);
buffer.Emit<OpCode::CvtSI2FP, 8, true, 4, false>(xmm5, r14, 4);
buffer.Emit<OpCode::CvtFP2SI>(r14d, xmm5s);
buffer.Emit<OpCode::CvtFP2SI>(r14d, xmm5);
buffer.Emit<OpCode::CvtSI2FP>(xmm5s, r14d);
buffer.Emit<OpCode::CvtSI2FP>(xmm5, r14d);
buffer.Emit<OpCode::CvtFP2SI>(r14, xmm5s);
buffer.Emit<OpCode::CvtFP2SI>(r14, xmm5);
buffer.Emit<OpCode::CvtSI2FP>(xmm5s, r14);
buffer.Emit<OpCode::CvtSI2FP>(xmm5, r14);
// Between: xmm5 and r15
buffer.Emit<OpCode::Mov>(r15, -4, xmm5s);
buffer.Emit<OpCode::Mov>(r15, 4, xmm5);
buffer.Emit<OpCode::Mov>(xmm5s, r15, -4);
buffer.Emit<OpCode::Mov>(xmm5, r15, 4);
buffer.Emit<OpCode::CvtSI2FP, 4, true, 8, false>(xmm5s, r15, -4);
buffer.Emit<OpCode::CvtSI2FP, 8, true, 4, false>(xmm5, r15, 4);
buffer.Emit<OpCode::CvtFP2SI>(r15d, xmm5s);
buffer.Emit<OpCode::CvtFP2SI>(r15d, xmm5);
buffer.Emit<OpCode::CvtSI2FP>(xmm5s, r15d);
buffer.Emit<OpCode::CvtSI2FP>(xmm5, r15d);
buffer.Emit<OpCode::CvtFP2SI>(r15, xmm5s);
buffer.Emit<OpCode::CvtFP2SI>(r15, xmm5);
buffer.Emit<OpCode::CvtSI2FP>(xmm5s, r15);
buffer.Emit<OpCode::CvtSI2FP>(xmm5, r15);
// Between: xmm6 and rax
buffer.Emit<OpCode::Mov>(rax, -4, xmm6s);
buffer.Emit<OpCode::Mov>(rax, 4, xmm6);
buffer.Emit<OpCode::Mov>(xmm6s, rax, -4);
buffer.Emit<OpCode::Mov>(xmm6, rax, 4);
buffer.Emit<OpCode::CvtSI2FP, 4, true, 8, false>(xmm6s, rax, -4);
buffer.Emit<OpCode::CvtSI2FP, 8, true, 4, false>(xmm6, rax, 4);
buffer.Emit<OpCode::CvtFP2SI>(eax, xmm6s);
buffer.Emit<OpCode::CvtFP2SI>(eax, xmm6);
buffer.Emit<OpCode::CvtSI2FP>(xmm6s, eax);
buffer.Emit<OpCode::CvtSI2FP>(xmm6, eax);
buffer.Emit<OpCode::CvtFP2SI>(rax, xmm6s);
buffer.Emit<OpCode::CvtFP2SI>(rax, xmm6);
buffer.Emit<OpCode::CvtSI2FP>(xmm6s, rax);
buffer.Emit<OpCode::CvtSI2FP>(xmm6, rax);
// Between: xmm6 and rcx
buffer.Emit<OpCode::Mov>(rcx, -4, xmm6s);
buffer.Emit<OpCode::Mov>(rcx, 4, xmm6);
buffer.Emit<OpCode::Mov>(xmm6s, rcx, -4);
buffer.Emit<OpCode::Mov>(xmm6, rcx, 4);
buffer.Emit<OpCode::CvtSI2FP, 4, true, 8, false>(xmm6s, rcx, -4);
buffer.Emit<OpCode::CvtSI2FP, 8, true, 4, false>(xmm6, rcx, 4);
buffer.Emit<OpCode::CvtFP2SI>(ecx, xmm6s);
buffer.Emit<OpCode::CvtFP2SI>(ecx, xmm6);
buffer.Emit<OpCode::CvtSI2FP>(xmm6s, ecx);
buffer.Emit<OpCode::CvtSI2FP>(xmm6, ecx);
buffer.Emit<OpCode::CvtFP2SI>(rcx, xmm6s);
buffer.Emit<OpCode::CvtFP2SI>(rcx, xmm6);
buffer.Emit<OpCode::CvtSI2FP>(xmm6s, rcx);
buffer.Emit<OpCode::CvtSI2FP>(xmm6, rcx);
// Between: xmm6 and rdx
buffer.Emit<OpCode::Mov>(rdx, -4, xmm6s);
buffer.Emit<OpCode::Mov>(rdx, 4, xmm6);
buffer.Emit<OpCode::Mov>(xmm6s, rdx, -4);
buffer.Emit<OpCode::Mov>(xmm6, rdx, 4);
buffer.Emit<OpCode::CvtSI2FP, 4, true, 8, false>(xmm6s, rdx, -4);
buffer.Emit<OpCode::CvtSI2FP, 8, true, 4, false>(xmm6, rdx, 4);
buffer.Emit<OpCode::CvtFP2SI>(edx, xmm6s);
buffer.Emit<OpCode::CvtFP2SI>(edx, xmm6);
buffer.Emit<OpCode::CvtSI2FP>(xmm6s, edx);
buffer.Emit<OpCode::CvtSI2FP>(xmm6, edx);
buffer.Emit<OpCode::CvtFP2SI>(rdx, xmm6s);
buffer.Emit<OpCode::CvtFP2SI>(rdx, xmm6);
buffer.Emit<OpCode::CvtSI2FP>(xmm6s, rdx);
buffer.Emit<OpCode::CvtSI2FP>(xmm6, rdx);
// Between: xmm6 and rbx
buffer.Emit<OpCode::Mov>(rbx, -4, xmm6s);
buffer.Emit<OpCode::Mov>(rbx, 4, xmm6);
buffer.Emit<OpCode::Mov>(xmm6s, rbx, -4);
buffer.Emit<OpCode::Mov>(xmm6, rbx, 4);
buffer.Emit<OpCode::CvtSI2FP, 4, true, 8, false>(xmm6s, rbx, -4);
buffer.Emit<OpCode::CvtSI2FP, 8, true, 4, false>(xmm6, rbx, 4);
buffer.Emit<OpCode::CvtFP2SI>(ebx, xmm6s);
buffer.Emit<OpCode::CvtFP2SI>(ebx, xmm6);
buffer.Emit<OpCode::CvtSI2FP>(xmm6s, ebx);
buffer.Emit<OpCode::CvtSI2FP>(xmm6, ebx);
buffer.Emit<OpCode::CvtFP2SI>(rbx, xmm6s);
buffer.Emit<OpCode::CvtFP2SI>(rbx, xmm6);
buffer.Emit<OpCode::CvtSI2FP>(xmm6s, rbx);
buffer.Emit<OpCode::CvtSI2FP>(xmm6, rbx);
// Between: xmm6 and rsp
buffer.Emit<OpCode::Mov>(rsp, -4, xmm6s);
buffer.Emit<OpCode::Mov>(rsp, 4, xmm6);
buffer.Emit<OpCode::Mov>(xmm6s, rsp, -4);
buffer.Emit<OpCode::Mov>(xmm6, rsp, 4);
buffer.Emit<OpCode::CvtSI2FP, 4, true, 8, false>(xmm6s, rsp, -4);
buffer.Emit<OpCode::CvtSI2FP, 8, true, 4, false>(xmm6, rsp, 4);
buffer.Emit<OpCode::CvtFP2SI>(esp, xmm6s);
buffer.Emit<OpCode::CvtFP2SI>(esp, xmm6);
buffer.Emit<OpCode::CvtSI2FP>(xmm6s, esp);
buffer.Emit<OpCode::CvtSI2FP>(xmm6, esp);
buffer.Emit<OpCode::CvtFP2SI>(rsp, xmm6s);
buffer.Emit<OpCode::CvtFP2SI>(rsp, xmm6);
buffer.Emit<OpCode::CvtSI2FP>(xmm6s, rsp);
buffer.Emit<OpCode::CvtSI2FP>(xmm6, rsp);
// Between: xmm6 and rbp
buffer.Emit<OpCode::Mov>(rbp, -4, xmm6s);
buffer.Emit<OpCode::Mov>(rbp, 4, xmm6);
buffer.Emit<OpCode::Mov>(xmm6s, rbp, -4);
buffer.Emit<OpCode::Mov>(xmm6, rbp, 4);
buffer.Emit<OpCode::CvtSI2FP, 4, true, 8, false>(xmm6s, rbp, -4);
buffer.Emit<OpCode::CvtSI2FP, 8, true, 4, false>(xmm6, rbp, 4);
buffer.Emit<OpCode::CvtFP2SI>(ebp, xmm6s);
buffer.Emit<OpCode::CvtFP2SI>(ebp, xmm6);
buffer.Emit<OpCode::CvtSI2FP>(xmm6s, ebp);
buffer.Emit<OpCode::CvtSI2FP>(xmm6, ebp);
buffer.Emit<OpCode::CvtFP2SI>(rbp, xmm6s);
buffer.Emit<OpCode::CvtFP2SI>(rbp, xmm6);
buffer.Emit<OpCode::CvtSI2FP>(xmm6s, rbp);
buffer.Emit<OpCode::CvtSI2FP>(xmm6, rbp);
// Between: xmm6 and rsi
buffer.Emit<OpCode::Mov>(rsi, -4, xmm6s);
buffer.Emit<OpCode::Mov>(rsi, 4, xmm6);
buffer.Emit<OpCode::Mov>(xmm6s, rsi, -4);
buffer.Emit<OpCode::Mov>(xmm6, rsi, 4);
buffer.Emit<OpCode::CvtSI2FP, 4, true, 8, false>(xmm6s, rsi, -4);
buffer.Emit<OpCode::CvtSI2FP, 8, true, 4, false>(xmm6, rsi, 4);
buffer.Emit<OpCode::CvtFP2SI>(esi, xmm6s);
buffer.Emit<OpCode::CvtFP2SI>(esi, xmm6);
buffer.Emit<OpCode::CvtSI2FP>(xmm6s, esi);
buffer.Emit<OpCode::CvtSI2FP>(xmm6, esi);
buffer.Emit<OpCode::CvtFP2SI>(rsi, xmm6s);
buffer.Emit<OpCode::CvtFP2SI>(rsi, xmm6);
buffer.Emit<OpCode::CvtSI2FP>(xmm6s, rsi);
buffer.Emit<OpCode::CvtSI2FP>(xmm6, rsi);
// Between: xmm6 and rdi
buffer.Emit<OpCode::Mov>(rdi, -4, xmm6s);
buffer.Emit<OpCode::Mov>(rdi, 4, xmm6);
buffer.Emit<OpCode::Mov>(xmm6s, rdi, -4);
buffer.Emit<OpCode::Mov>(xmm6, rdi, 4);
buffer.Emit<OpCode::CvtSI2FP, 4, true, 8, false>(xmm6s, rdi, -4);
buffer.Emit<OpCode::CvtSI2FP, 8, true, 4, false>(xmm6, rdi, 4);
buffer.Emit<OpCode::CvtFP2SI>(edi, xmm6s);
buffer.Emit<OpCode::CvtFP2SI>(edi, xmm6);
buffer.Emit<OpCode::CvtSI2FP>(xmm6s, edi);
buffer.Emit<OpCode::CvtSI2FP>(xmm6, edi);
buffer.Emit<OpCode::CvtFP2SI>(rdi, xmm6s);
buffer.Emit<OpCode::CvtFP2SI>(rdi, xmm6);
buffer.Emit<OpCode::CvtSI2FP>(xmm6s, rdi);
buffer.Emit<OpCode::CvtSI2FP>(xmm6, rdi);
// Between: xmm6 and r8
buffer.Emit<OpCode::Mov>(r8, -4, xmm6s);
buffer.Emit<OpCode::Mov>(r8, 4, xmm6);
buffer.Emit<OpCode::Mov>(xmm6s, r8, -4);
buffer.Emit<OpCode::Mov>(xmm6, r8, 4);
buffer.Emit<OpCode::CvtSI2FP, 4, true, 8, false>(xmm6s, r8, -4);
buffer.Emit<OpCode::CvtSI2FP, 8, true, 4, false>(xmm6, r8, 4);
buffer.Emit<OpCode::CvtFP2SI>(r8d, xmm6s);
buffer.Emit<OpCode::CvtFP2SI>(r8d, xmm6);
buffer.Emit<OpCode::CvtSI2FP>(xmm6s, r8d);
buffer.Emit<OpCode::CvtSI2FP>(xmm6, r8d);
buffer.Emit<OpCode::CvtFP2SI>(r8, xmm6s);
buffer.Emit<OpCode::CvtFP2SI>(r8, xmm6);
buffer.Emit<OpCode::CvtSI2FP>(xmm6s, r8);
buffer.Emit<OpCode::CvtSI2FP>(xmm6, r8);
// Between: xmm6 and r9
buffer.Emit<OpCode::Mov>(r9, -4, xmm6s);
buffer.Emit<OpCode::Mov>(r9, 4, xmm6);
buffer.Emit<OpCode::Mov>(xmm6s, r9, -4);
buffer.Emit<OpCode::Mov>(xmm6, r9, 4);
buffer.Emit<OpCode::CvtSI2FP, 4, true, 8, false>(xmm6s, r9, -4);
buffer.Emit<OpCode::CvtSI2FP, 8, true, 4, false>(xmm6, r9, 4);
buffer.Emit<OpCode::CvtFP2SI>(r9d, xmm6s);
buffer.Emit<OpCode::CvtFP2SI>(r9d, xmm6);
buffer.Emit<OpCode::CvtSI2FP>(xmm6s, r9d);
buffer.Emit<OpCode::CvtSI2FP>(xmm6, r9d);
buffer.Emit<OpCode::CvtFP2SI>(r9, xmm6s);
buffer.Emit<OpCode::CvtFP2SI>(r9, xmm6);
buffer.Emit<OpCode::CvtSI2FP>(xmm6s, r9);
buffer.Emit<OpCode::CvtSI2FP>(xmm6, r9);
// Between: xmm6 and r10
buffer.Emit<OpCode::Mov>(r10, -4, xmm6s);
buffer.Emit<OpCode::Mov>(r10, 4, xmm6);
buffer.Emit<OpCode::Mov>(xmm6s, r10, -4);
buffer.Emit<OpCode::Mov>(xmm6, r10, 4);
buffer.Emit<OpCode::CvtSI2FP, 4, true, 8, false>(xmm6s, r10, -4);
buffer.Emit<OpCode::CvtSI2FP, 8, true, 4, false>(xmm6, r10, 4);
buffer.Emit<OpCode::CvtFP2SI>(r10d, xmm6s);
buffer.Emit<OpCode::CvtFP2SI>(r10d, xmm6);
buffer.Emit<OpCode::CvtSI2FP>(xmm6s, r10d);
buffer.Emit<OpCode::CvtSI2FP>(xmm6, r10d);
buffer.Emit<OpCode::CvtFP2SI>(r10, xmm6s);
buffer.Emit<OpCode::CvtFP2SI>(r10, xmm6);
buffer.Emit<OpCode::CvtSI2FP>(xmm6s, r10);
buffer.Emit<OpCode::CvtSI2FP>(xmm6, r10);
// Between: xmm6 and r11
buffer.Emit<OpCode::Mov>(r11, -4, xmm6s);
buffer.Emit<OpCode::Mov>(r11, 4, xmm6);
buffer.Emit<OpCode::Mov>(xmm6s, r11, -4);
buffer.Emit<OpCode::Mov>(xmm6, r11, 4);
buffer.Emit<OpCode::CvtSI2FP, 4, true, 8, false>(xmm6s, r11, -4);
buffer.Emit<OpCode::CvtSI2FP, 8, true, 4, false>(xmm6, r11, 4);
buffer.Emit<OpCode::CvtFP2SI>(r11d, xmm6s);
buffer.Emit<OpCode::CvtFP2SI>(r11d, xmm6);
buffer.Emit<OpCode::CvtSI2FP>(xmm6s, r11d);
buffer.Emit<OpCode::CvtSI2FP>(xmm6, r11d);
buffer.Emit<OpCode::CvtFP2SI>(r11, xmm6s);
buffer.Emit<OpCode::CvtFP2SI>(r11, xmm6);
buffer.Emit<OpCode::CvtSI2FP>(xmm6s, r11);
buffer.Emit<OpCode::CvtSI2FP>(xmm6, r11);
// Between: xmm6 and r12
buffer.Emit<OpCode::Mov>(r12, -4, xmm6s);
buffer.Emit<OpCode::Mov>(r12, 4, xmm6);
buffer.Emit<OpCode::Mov>(xmm6s, r12, -4);
buffer.Emit<OpCode::Mov>(xmm6, r12, 4);
buffer.Emit<OpCode::CvtSI2FP, 4, true, 8, false>(xmm6s, r12, -4);
buffer.Emit<OpCode::CvtSI2FP, 8, true, 4, false>(xmm6, r12, 4);
buffer.Emit<OpCode::CvtFP2SI>(r12d, xmm6s);
buffer.Emit<OpCode::CvtFP2SI>(r12d, xmm6);
buffer.Emit<OpCode::CvtSI2FP>(xmm6s, r12d);
buffer.Emit<OpCode::CvtSI2FP>(xmm6, r12d);
buffer.Emit<OpCode::CvtFP2SI>(r12, xmm6s);
buffer.Emit<OpCode::CvtFP2SI>(r12, xmm6);
buffer.Emit<OpCode::CvtSI2FP>(xmm6s, r12);
buffer.Emit<OpCode::CvtSI2FP>(xmm6, r12);
// Between: xmm6 and r13
buffer.Emit<OpCode::Mov>(r13, -4, xmm6s);
buffer.Emit<OpCode::Mov>(r13, 4, xmm6);
buffer.Emit<OpCode::Mov>(xmm6s, r13, -4);
buffer.Emit<OpCode::Mov>(xmm6, r13, 4);
buffer.Emit<OpCode::CvtSI2FP, 4, true, 8, false>(xmm6s, r13, -4);
buffer.Emit<OpCode::CvtSI2FP, 8, true, 4, false>(xmm6, r13, 4);
buffer.Emit<OpCode::CvtFP2SI>(r13d, xmm6s);
buffer.Emit<OpCode::CvtFP2SI>(r13d, xmm6);
buffer.Emit<OpCode::CvtSI2FP>(xmm6s, r13d);
buffer.Emit<OpCode::CvtSI2FP>(xmm6, r13d);
buffer.Emit<OpCode::CvtFP2SI>(r13, xmm6s);
buffer.Emit<OpCode::CvtFP2SI>(r13, xmm6);
buffer.Emit<OpCode::CvtSI2FP>(xmm6s, r13);
buffer.Emit<OpCode::CvtSI2FP>(xmm6, r13);
// Between: xmm6 and r14
buffer.Emit<OpCode::Mov>(r14, -4, xmm6s);
buffer.Emit<OpCode::Mov>(r14, 4, xmm6);
buffer.Emit<OpCode::Mov>(xmm6s, r14, -4);
buffer.Emit<OpCode::Mov>(xmm6, r14, 4);
buffer.Emit<OpCode::CvtSI2FP, 4, true, 8, false>(xmm6s, r14, -4);
buffer.Emit<OpCode::CvtSI2FP, 8, true, 4, false>(xmm6, r14, 4);
buffer.Emit<OpCode::CvtFP2SI>(r14d, xmm6s);
buffer.Emit<OpCode::CvtFP2SI>(r14d, xmm6);
buffer.Emit<OpCode::CvtSI2FP>(xmm6s, r14d);
buffer.Emit<OpCode::CvtSI2FP>(xmm6, r14d);
buffer.Emit<OpCode::CvtFP2SI>(r14, xmm6s);
buffer.Emit<OpCode::CvtFP2SI>(r14, xmm6);
buffer.Emit<OpCode::CvtSI2FP>(xmm6s, r14);
buffer.Emit<OpCode::CvtSI2FP>(xmm6, r14);
// Between: xmm6 and r15
buffer.Emit<OpCode::Mov>(r15, -4, xmm6s);
buffer.Emit<OpCode::Mov>(r15, 4, xmm6);
buffer.Emit<OpCode::Mov>(xmm6s, r15, -4);
buffer.Emit<OpCode::Mov>(xmm6, r15, 4);
buffer.Emit<OpCode::CvtSI2FP, 4, true, 8, false>(xmm6s, r15, -4);
buffer.Emit<OpCode::CvtSI2FP, 8, true, 4, false>(xmm6, r15, 4);
buffer.Emit<OpCode::CvtFP2SI>(r15d, xmm6s);
buffer.Emit<OpCode::CvtFP2SI>(r15d, xmm6);
buffer.Emit<OpCode::CvtSI2FP>(xmm6s, r15d);
buffer.Emit<OpCode::CvtSI2FP>(xmm6, r15d);
buffer.Emit<OpCode::CvtFP2SI>(r15, xmm6s);
buffer.Emit<OpCode::CvtFP2SI>(r15, xmm6);
buffer.Emit<OpCode::CvtSI2FP>(xmm6s, r15);
buffer.Emit<OpCode::CvtSI2FP>(xmm6, r15);
// Between: xmm7 and rax
buffer.Emit<OpCode::Mov>(rax, -4, xmm7s);
buffer.Emit<OpCode::Mov>(rax, 4, xmm7);
buffer.Emit<OpCode::Mov>(xmm7s, rax, -4);
buffer.Emit<OpCode::Mov>(xmm7, rax, 4);
buffer.Emit<OpCode::CvtSI2FP, 4, true, 8, false>(xmm7s, rax, -4);
buffer.Emit<OpCode::CvtSI2FP, 8, true, 4, false>(xmm7, rax, 4);
buffer.Emit<OpCode::CvtFP2SI>(eax, xmm7s);
buffer.Emit<OpCode::CvtFP2SI>(eax, xmm7);
buffer.Emit<OpCode::CvtSI2FP>(xmm7s, eax);
buffer.Emit<OpCode::CvtSI2FP>(xmm7, eax);
buffer.Emit<OpCode::CvtFP2SI>(rax, xmm7s);
buffer.Emit<OpCode::CvtFP2SI>(rax, xmm7);
buffer.Emit<OpCode::CvtSI2FP>(xmm7s, rax);
buffer.Emit<OpCode::CvtSI2FP>(xmm7, rax);
// Between: xmm7 and rcx
buffer.Emit<OpCode::Mov>(rcx, -4, xmm7s);
buffer.Emit<OpCode::Mov>(rcx, 4, xmm7);
buffer.Emit<OpCode::Mov>(xmm7s, rcx, -4);
buffer.Emit<OpCode::Mov>(xmm7, rcx, 4);
buffer.Emit<OpCode::CvtSI2FP, 4, true, 8, false>(xmm7s, rcx, -4);
buffer.Emit<OpCode::CvtSI2FP, 8, true, 4, false>(xmm7, rcx, 4);
buffer.Emit<OpCode::CvtFP2SI>(ecx, xmm7s);
buffer.Emit<OpCode::CvtFP2SI>(ecx, xmm7);
buffer.Emit<OpCode::CvtSI2FP>(xmm7s, ecx);
buffer.Emit<OpCode::CvtSI2FP>(xmm7, ecx);
buffer.Emit<OpCode::CvtFP2SI>(rcx, xmm7s);
buffer.Emit<OpCode::CvtFP2SI>(rcx, xmm7);
buffer.Emit<OpCode::CvtSI2FP>(xmm7s, rcx);
buffer.Emit<OpCode::CvtSI2FP>(xmm7, rcx);
// Between: xmm7 and rdx
buffer.Emit<OpCode::Mov>(rdx, -4, xmm7s);
buffer.Emit<OpCode::Mov>(rdx, 4, xmm7);
buffer.Emit<OpCode::Mov>(xmm7s, rdx, -4);
buffer.Emit<OpCode::Mov>(xmm7, rdx, 4);
buffer.Emit<OpCode::CvtSI2FP, 4, true, 8, false>(xmm7s, rdx, -4);
buffer.Emit<OpCode::CvtSI2FP, 8, true, 4, false>(xmm7, rdx, 4);
buffer.Emit<OpCode::CvtFP2SI>(edx, xmm7s);
buffer.Emit<OpCode::CvtFP2SI>(edx, xmm7);
buffer.Emit<OpCode::CvtSI2FP>(xmm7s, edx);
buffer.Emit<OpCode::CvtSI2FP>(xmm7, edx);
buffer.Emit<OpCode::CvtFP2SI>(rdx, xmm7s);
buffer.Emit<OpCode::CvtFP2SI>(rdx, xmm7);
buffer.Emit<OpCode::CvtSI2FP>(xmm7s, rdx);
buffer.Emit<OpCode::CvtSI2FP>(xmm7, rdx);
// Between: xmm7 and rbx
buffer.Emit<OpCode::Mov>(rbx, -4, xmm7s);
buffer.Emit<OpCode::Mov>(rbx, 4, xmm7);
buffer.Emit<OpCode::Mov>(xmm7s, rbx, -4);
buffer.Emit<OpCode::Mov>(xmm7, rbx, 4);
buffer.Emit<OpCode::CvtSI2FP, 4, true, 8, false>(xmm7s, rbx, -4);
buffer.Emit<OpCode::CvtSI2FP, 8, true, 4, false>(xmm7, rbx, 4);
buffer.Emit<OpCode::CvtFP2SI>(ebx, xmm7s);
buffer.Emit<OpCode::CvtFP2SI>(ebx, xmm7);
buffer.Emit<OpCode::CvtSI2FP>(xmm7s, ebx);
buffer.Emit<OpCode::CvtSI2FP>(xmm7, ebx);
buffer.Emit<OpCode::CvtFP2SI>(rbx, xmm7s);
buffer.Emit<OpCode::CvtFP2SI>(rbx, xmm7);
buffer.Emit<OpCode::CvtSI2FP>(xmm7s, rbx);
buffer.Emit<OpCode::CvtSI2FP>(xmm7, rbx);
// Between: xmm7 and rsp
buffer.Emit<OpCode::Mov>(rsp, -4, xmm7s);
buffer.Emit<OpCode::Mov>(rsp, 4, xmm7);
buffer.Emit<OpCode::Mov>(xmm7s, rsp, -4);
buffer.Emit<OpCode::Mov>(xmm7, rsp, 4);
buffer.Emit<OpCode::CvtSI2FP, 4, true, 8, false>(xmm7s, rsp, -4);
buffer.Emit<OpCode::CvtSI2FP, 8, true, 4, false>(xmm7, rsp, 4);
buffer.Emit<OpCode::CvtFP2SI>(esp, xmm7s);
buffer.Emit<OpCode::CvtFP2SI>(esp, xmm7);
buffer.Emit<OpCode::CvtSI2FP>(xmm7s, esp);
buffer.Emit<OpCode::CvtSI2FP>(xmm7, esp);
buffer.Emit<OpCode::CvtFP2SI>(rsp, xmm7s);
buffer.Emit<OpCode::CvtFP2SI>(rsp, xmm7);
buffer.Emit<OpCode::CvtSI2FP>(xmm7s, rsp);
buffer.Emit<OpCode::CvtSI2FP>(xmm7, rsp);
// Between: xmm7 and rbp
buffer.Emit<OpCode::Mov>(rbp, -4, xmm7s);
buffer.Emit<OpCode::Mov>(rbp, 4, xmm7);
buffer.Emit<OpCode::Mov>(xmm7s, rbp, -4);
buffer.Emit<OpCode::Mov>(xmm7, rbp, 4);
buffer.Emit<OpCode::CvtSI2FP, 4, true, 8, false>(xmm7s, rbp, -4);
buffer.Emit<OpCode::CvtSI2FP, 8, true, 4, false>(xmm7, rbp, 4);
buffer.Emit<OpCode::CvtFP2SI>(ebp, xmm7s);
buffer.Emit<OpCode::CvtFP2SI>(ebp, xmm7);
buffer.Emit<OpCode::CvtSI2FP>(xmm7s, ebp);
buffer.Emit<OpCode::CvtSI2FP>(xmm7, ebp);
buffer.Emit<OpCode::CvtFP2SI>(rbp, xmm7s);
buffer.Emit<OpCode::CvtFP2SI>(rbp, xmm7);
buffer.Emit<OpCode::CvtSI2FP>(xmm7s, rbp);
buffer.Emit<OpCode::CvtSI2FP>(xmm7, rbp);
// Between: xmm7 and rsi
buffer.Emit<OpCode::Mov>(rsi, -4, xmm7s);
buffer.Emit<OpCode::Mov>(rsi, 4, xmm7);
buffer.Emit<OpCode::Mov>(xmm7s, rsi, -4);
buffer.Emit<OpCode::Mov>(xmm7, rsi, 4);
buffer.Emit<OpCode::CvtSI2FP, 4, true, 8, false>(xmm7s, rsi, -4);
buffer.Emit<OpCode::CvtSI2FP, 8, true, 4, false>(xmm7, rsi, 4);
buffer.Emit<OpCode::CvtFP2SI>(esi, xmm7s);
buffer.Emit<OpCode::CvtFP2SI>(esi, xmm7);
buffer.Emit<OpCode::CvtSI2FP>(xmm7s, esi);
buffer.Emit<OpCode::CvtSI2FP>(xmm7, esi);
buffer.Emit<OpCode::CvtFP2SI>(rsi, xmm7s);
buffer.Emit<OpCode::CvtFP2SI>(rsi, xmm7);
buffer.Emit<OpCode::CvtSI2FP>(xmm7s, rsi);
buffer.Emit<OpCode::CvtSI2FP>(xmm7, rsi);
// Between: xmm7 and rdi
buffer.Emit<OpCode::Mov>(rdi, -4, xmm7s);
buffer.Emit<OpCode::Mov>(rdi, 4, xmm7);
buffer.Emit<OpCode::Mov>(xmm7s, rdi, -4);
buffer.Emit<OpCode::Mov>(xmm7, rdi, 4);
buffer.Emit<OpCode::CvtSI2FP, 4, true, 8, false>(xmm7s, rdi, -4);
buffer.Emit<OpCode::CvtSI2FP, 8, true, 4, false>(xmm7, rdi, 4);
buffer.Emit<OpCode::CvtFP2SI>(edi, xmm7s);
buffer.Emit<OpCode::CvtFP2SI>(edi, xmm7);
buffer.Emit<OpCode::CvtSI2FP>(xmm7s, edi);
buffer.Emit<OpCode::CvtSI2FP>(xmm7, edi);
buffer.Emit<OpCode::CvtFP2SI>(rdi, xmm7s);
buffer.Emit<OpCode::CvtFP2SI>(rdi, xmm7);
buffer.Emit<OpCode::CvtSI2FP>(xmm7s, rdi);
buffer.Emit<OpCode::CvtSI2FP>(xmm7, rdi);
// Between: xmm7 and r8
buffer.Emit<OpCode::Mov>(r8, -4, xmm7s);
buffer.Emit<OpCode::Mov>(r8, 4, xmm7);
buffer.Emit<OpCode::Mov>(xmm7s, r8, -4);
buffer.Emit<OpCode::Mov>(xmm7, r8, 4);
buffer.Emit<OpCode::CvtSI2FP, 4, true, 8, false>(xmm7s, r8, -4);
buffer.Emit<OpCode::CvtSI2FP, 8, true, 4, false>(xmm7, r8, 4);
buffer.Emit<OpCode::CvtFP2SI>(r8d, xmm7s);
buffer.Emit<OpCode::CvtFP2SI>(r8d, xmm7);
buffer.Emit<OpCode::CvtSI2FP>(xmm7s, r8d);
buffer.Emit<OpCode::CvtSI2FP>(xmm7, r8d);
buffer.Emit<OpCode::CvtFP2SI>(r8, xmm7s);
buffer.Emit<OpCode::CvtFP2SI>(r8, xmm7);
buffer.Emit<OpCode::CvtSI2FP>(xmm7s, r8);
buffer.Emit<OpCode::CvtSI2FP>(xmm7, r8);
// Between: xmm7 and r9
buffer.Emit<OpCode::Mov>(r9, -4, xmm7s);
buffer.Emit<OpCode::Mov>(r9, 4, xmm7);
buffer.Emit<OpCode::Mov>(xmm7s, r9, -4);
buffer.Emit<OpCode::Mov>(xmm7, r9, 4);
buffer.Emit<OpCode::CvtSI2FP, 4, true, 8, false>(xmm7s, r9, -4);
buffer.Emit<OpCode::CvtSI2FP, 8, true, 4, false>(xmm7, r9, 4);
buffer.Emit<OpCode::CvtFP2SI>(r9d, xmm7s);
buffer.Emit<OpCode::CvtFP2SI>(r9d, xmm7);
buffer.Emit<OpCode::CvtSI2FP>(xmm7s, r9d);
buffer.Emit<OpCode::CvtSI2FP>(xmm7, r9d);
buffer.Emit<OpCode::CvtFP2SI>(r9, xmm7s);
buffer.Emit<OpCode::CvtFP2SI>(r9, xmm7);
buffer.Emit<OpCode::CvtSI2FP>(xmm7s, r9);
buffer.Emit<OpCode::CvtSI2FP>(xmm7, r9);
// Between: xmm7 and r10
buffer.Emit<OpCode::Mov>(r10, -4, xmm7s);
buffer.Emit<OpCode::Mov>(r10, 4, xmm7);
buffer.Emit<OpCode::Mov>(xmm7s, r10, -4);
buffer.Emit<OpCode::Mov>(xmm7, r10, 4);
buffer.Emit<OpCode::CvtSI2FP, 4, true, 8, false>(xmm7s, r10, -4);
buffer.Emit<OpCode::CvtSI2FP, 8, true, 4, false>(xmm7, r10, 4);
buffer.Emit<OpCode::CvtFP2SI>(r10d, xmm7s);
buffer.Emit<OpCode::CvtFP2SI>(r10d, xmm7);
buffer.Emit<OpCode::CvtSI2FP>(xmm7s, r10d);
buffer.Emit<OpCode::CvtSI2FP>(xmm7, r10d);
buffer.Emit<OpCode::CvtFP2SI>(r10, xmm7s);
buffer.Emit<OpCode::CvtFP2SI>(r10, xmm7);
buffer.Emit<OpCode::CvtSI2FP>(xmm7s, r10);
buffer.Emit<OpCode::CvtSI2FP>(xmm7, r10);
// Between: xmm7 and r11
buffer.Emit<OpCode::Mov>(r11, -4, xmm7s);
buffer.Emit<OpCode::Mov>(r11, 4, xmm7);
buffer.Emit<OpCode::Mov>(xmm7s, r11, -4);
buffer.Emit<OpCode::Mov>(xmm7, r11, 4);
buffer.Emit<OpCode::CvtSI2FP, 4, true, 8, false>(xmm7s, r11, -4);
buffer.Emit<OpCode::CvtSI2FP, 8, true, 4, false>(xmm7, r11, 4);
buffer.Emit<OpCode::CvtFP2SI>(r11d, xmm7s);
buffer.Emit<OpCode::CvtFP2SI>(r11d, xmm7);
buffer.Emit<OpCode::CvtSI2FP>(xmm7s, r11d);
buffer.Emit<OpCode::CvtSI2FP>(xmm7, r11d);
buffer.Emit<OpCode::CvtFP2SI>(r11, xmm7s);
buffer.Emit<OpCode::CvtFP2SI>(r11, xmm7);
buffer.Emit<OpCode::CvtSI2FP>(xmm7s, r11);
buffer.Emit<OpCode::CvtSI2FP>(xmm7, r11);
// Between: xmm7 and r12
buffer.Emit<OpCode::Mov>(r12, -4, xmm7s);
buffer.Emit<OpCode::Mov>(r12, 4, xmm7);
buffer.Emit<OpCode::Mov>(xmm7s, r12, -4);
buffer.Emit<OpCode::Mov>(xmm7, r12, 4);
buffer.Emit<OpCode::CvtSI2FP, 4, true, 8, false>(xmm7s, r12, -4);
buffer.Emit<OpCode::CvtSI2FP, 8, true, 4, false>(xmm7, r12, 4);
buffer.Emit<OpCode::CvtFP2SI>(r12d, xmm7s);
buffer.Emit<OpCode::CvtFP2SI>(r12d, xmm7);
buffer.Emit<OpCode::CvtSI2FP>(xmm7s, r12d);
buffer.Emit<OpCode::CvtSI2FP>(xmm7, r12d);
buffer.Emit<OpCode::CvtFP2SI>(r12, xmm7s);
buffer.Emit<OpCode::CvtFP2SI>(r12, xmm7);
buffer.Emit<OpCode::CvtSI2FP>(xmm7s, r12);
buffer.Emit<OpCode::CvtSI2FP>(xmm7, r12);
// Between: xmm7 and r13
buffer.Emit<OpCode::Mov>(r13, -4, xmm7s);
buffer.Emit<OpCode::Mov>(r13, 4, xmm7);
buffer.Emit<OpCode::Mov>(xmm7s, r13, -4);
buffer.Emit<OpCode::Mov>(xmm7, r13, 4);
buffer.Emit<OpCode::CvtSI2FP, 4, true, 8, false>(xmm7s, r13, -4);
buffer.Emit<OpCode::CvtSI2FP, 8, true, 4, false>(xmm7, r13, 4);
buffer.Emit<OpCode::CvtFP2SI>(r13d, xmm7s);
buffer.Emit<OpCode::CvtFP2SI>(r13d, xmm7);
buffer.Emit<OpCode::CvtSI2FP>(xmm7s, r13d);
buffer.Emit<OpCode::CvtSI2FP>(xmm7, r13d);
buffer.Emit<OpCode::CvtFP2SI>(r13, xmm7s);
buffer.Emit<OpCode::CvtFP2SI>(r13, xmm7);
buffer.Emit<OpCode::CvtSI2FP>(xmm7s, r13);
buffer.Emit<OpCode::CvtSI2FP>(xmm7, r13);
// Between: xmm7 and r14
buffer.Emit<OpCode::Mov>(r14, -4, xmm7s);
buffer.Emit<OpCode::Mov>(r14, 4, xmm7);
buffer.Emit<OpCode::Mov>(xmm7s, r14, -4);
buffer.Emit<OpCode::Mov>(xmm7, r14, 4);
buffer.Emit<OpCode::CvtSI2FP, 4, true, 8, false>(xmm7s, r14, -4);
buffer.Emit<OpCode::CvtSI2FP, 8, true, 4, false>(xmm7, r14, 4);
buffer.Emit<OpCode::CvtFP2SI>(r14d, xmm7s);
buffer.Emit<OpCode::CvtFP2SI>(r14d, xmm7);
buffer.Emit<OpCode::CvtSI2FP>(xmm7s, r14d);
buffer.Emit<OpCode::CvtSI2FP>(xmm7, r14d);
buffer.Emit<OpCode::CvtFP2SI>(r14, xmm7s);
buffer.Emit<OpCode::CvtFP2SI>(r14, xmm7);
buffer.Emit<OpCode::CvtSI2FP>(xmm7s, r14);
buffer.Emit<OpCode::CvtSI2FP>(xmm7, r14);
// Between: xmm7 and r15
buffer.Emit<OpCode::Mov>(r15, -4, xmm7s);
buffer.Emit<OpCode::Mov>(r15, 4, xmm7);
buffer.Emit<OpCode::Mov>(xmm7s, r15, -4);
buffer.Emit<OpCode::Mov>(xmm7, r15, 4);
buffer.Emit<OpCode::CvtSI2FP, 4, true, 8, false>(xmm7s, r15, -4);
buffer.Emit<OpCode::CvtSI2FP, 8, true, 4, false>(xmm7, r15, 4);
buffer.Emit<OpCode::CvtFP2SI>(r15d, xmm7s);
buffer.Emit<OpCode::CvtFP2SI>(r15d, xmm7);
buffer.Emit<OpCode::CvtSI2FP>(xmm7s, r15d);
buffer.Emit<OpCode::CvtSI2FP>(xmm7, r15d);
buffer.Emit<OpCode::CvtFP2SI>(r15, xmm7s);
buffer.Emit<OpCode::CvtFP2SI>(r15, xmm7);
buffer.Emit<OpCode::CvtSI2FP>(xmm7s, r15);
buffer.Emit<OpCode::CvtSI2FP>(xmm7, r15);
// Between: xmm8 and rax
buffer.Emit<OpCode::Mov>(rax, -4, xmm8s);
buffer.Emit<OpCode::Mov>(rax, 4, xmm8);
buffer.Emit<OpCode::Mov>(xmm8s, rax, -4);
buffer.Emit<OpCode::Mov>(xmm8, rax, 4);
buffer.Emit<OpCode::CvtSI2FP, 4, true, 8, false>(xmm8s, rax, -4);
buffer.Emit<OpCode::CvtSI2FP, 8, true, 4, false>(xmm8, rax, 4);
buffer.Emit<OpCode::CvtFP2SI>(eax, xmm8s);
buffer.Emit<OpCode::CvtFP2SI>(eax, xmm8);
buffer.Emit<OpCode::CvtSI2FP>(xmm8s, eax);
buffer.Emit<OpCode::CvtSI2FP>(xmm8, eax);
buffer.Emit<OpCode::CvtFP2SI>(rax, xmm8s);
buffer.Emit<OpCode::CvtFP2SI>(rax, xmm8);
buffer.Emit<OpCode::CvtSI2FP>(xmm8s, rax);
buffer.Emit<OpCode::CvtSI2FP>(xmm8, rax);
// Between: xmm8 and rcx
buffer.Emit<OpCode::Mov>(rcx, -4, xmm8s);
buffer.Emit<OpCode::Mov>(rcx, 4, xmm8);
buffer.Emit<OpCode::Mov>(xmm8s, rcx, -4);
buffer.Emit<OpCode::Mov>(xmm8, rcx, 4);
buffer.Emit<OpCode::CvtSI2FP, 4, true, 8, false>(xmm8s, rcx, -4);
buffer.Emit<OpCode::CvtSI2FP, 8, true, 4, false>(xmm8, rcx, 4);
buffer.Emit<OpCode::CvtFP2SI>(ecx, xmm8s);
buffer.Emit<OpCode::CvtFP2SI>(ecx, xmm8);
buffer.Emit<OpCode::CvtSI2FP>(xmm8s, ecx);
buffer.Emit<OpCode::CvtSI2FP>(xmm8, ecx);
buffer.Emit<OpCode::CvtFP2SI>(rcx, xmm8s);
buffer.Emit<OpCode::CvtFP2SI>(rcx, xmm8);
buffer.Emit<OpCode::CvtSI2FP>(xmm8s, rcx);
buffer.Emit<OpCode::CvtSI2FP>(xmm8, rcx);
// Between: xmm8 and rdx
buffer.Emit<OpCode::Mov>(rdx, -4, xmm8s);
buffer.Emit<OpCode::Mov>(rdx, 4, xmm8);
buffer.Emit<OpCode::Mov>(xmm8s, rdx, -4);
buffer.Emit<OpCode::Mov>(xmm8, rdx, 4);
buffer.Emit<OpCode::CvtSI2FP, 4, true, 8, false>(xmm8s, rdx, -4);
buffer.Emit<OpCode::CvtSI2FP, 8, true, 4, false>(xmm8, rdx, 4);
buffer.Emit<OpCode::CvtFP2SI>(edx, xmm8s);
buffer.Emit<OpCode::CvtFP2SI>(edx, xmm8);
buffer.Emit<OpCode::CvtSI2FP>(xmm8s, edx);
buffer.Emit<OpCode::CvtSI2FP>(xmm8, edx);
buffer.Emit<OpCode::CvtFP2SI>(rdx, xmm8s);
buffer.Emit<OpCode::CvtFP2SI>(rdx, xmm8);
buffer.Emit<OpCode::CvtSI2FP>(xmm8s, rdx);
buffer.Emit<OpCode::CvtSI2FP>(xmm8, rdx);
// Between: xmm8 and rbx
buffer.Emit<OpCode::Mov>(rbx, -4, xmm8s);
buffer.Emit<OpCode::Mov>(rbx, 4, xmm8);
buffer.Emit<OpCode::Mov>(xmm8s, rbx, -4);
buffer.Emit<OpCode::Mov>(xmm8, rbx, 4);
buffer.Emit<OpCode::CvtSI2FP, 4, true, 8, false>(xmm8s, rbx, -4);
buffer.Emit<OpCode::CvtSI2FP, 8, true, 4, false>(xmm8, rbx, 4);
buffer.Emit<OpCode::CvtFP2SI>(ebx, xmm8s);
buffer.Emit<OpCode::CvtFP2SI>(ebx, xmm8);
buffer.Emit<OpCode::CvtSI2FP>(xmm8s, ebx);
buffer.Emit<OpCode::CvtSI2FP>(xmm8, ebx);
buffer.Emit<OpCode::CvtFP2SI>(rbx, xmm8s);
buffer.Emit<OpCode::CvtFP2SI>(rbx, xmm8);
buffer.Emit<OpCode::CvtSI2FP>(xmm8s, rbx);
buffer.Emit<OpCode::CvtSI2FP>(xmm8, rbx);
// Between: xmm8 and rsp
buffer.Emit<OpCode::Mov>(rsp, -4, xmm8s);
buffer.Emit<OpCode::Mov>(rsp, 4, xmm8);
buffer.Emit<OpCode::Mov>(xmm8s, rsp, -4);
buffer.Emit<OpCode::Mov>(xmm8, rsp, 4);
buffer.Emit<OpCode::CvtSI2FP, 4, true, 8, false>(xmm8s, rsp, -4);
buffer.Emit<OpCode::CvtSI2FP, 8, true, 4, false>(xmm8, rsp, 4);
buffer.Emit<OpCode::CvtFP2SI>(esp, xmm8s);
buffer.Emit<OpCode::CvtFP2SI>(esp, xmm8);
buffer.Emit<OpCode::CvtSI2FP>(xmm8s, esp);
buffer.Emit<OpCode::CvtSI2FP>(xmm8, esp);
buffer.Emit<OpCode::CvtFP2SI>(rsp, xmm8s);
buffer.Emit<OpCode::CvtFP2SI>(rsp, xmm8);
buffer.Emit<OpCode::CvtSI2FP>(xmm8s, rsp);
buffer.Emit<OpCode::CvtSI2FP>(xmm8, rsp);
// Between: xmm8 and rbp
buffer.Emit<OpCode::Mov>(rbp, -4, xmm8s);
buffer.Emit<OpCode::Mov>(rbp, 4, xmm8);
buffer.Emit<OpCode::Mov>(xmm8s, rbp, -4);
buffer.Emit<OpCode::Mov>(xmm8, rbp, 4);
buffer.Emit<OpCode::CvtSI2FP, 4, true, 8, false>(xmm8s, rbp, -4);
buffer.Emit<OpCode::CvtSI2FP, 8, true, 4, false>(xmm8, rbp, 4);
buffer.Emit<OpCode::CvtFP2SI>(ebp, xmm8s);
buffer.Emit<OpCode::CvtFP2SI>(ebp, xmm8);
buffer.Emit<OpCode::CvtSI2FP>(xmm8s, ebp);
buffer.Emit<OpCode::CvtSI2FP>(xmm8, ebp);
buffer.Emit<OpCode::CvtFP2SI>(rbp, xmm8s);
buffer.Emit<OpCode::CvtFP2SI>(rbp, xmm8);
buffer.Emit<OpCode::CvtSI2FP>(xmm8s, rbp);
buffer.Emit<OpCode::CvtSI2FP>(xmm8, rbp);
// Between: xmm8 and rsi
buffer.Emit<OpCode::Mov>(rsi, -4, xmm8s);
buffer.Emit<OpCode::Mov>(rsi, 4, xmm8);
buffer.Emit<OpCode::Mov>(xmm8s, rsi, -4);
buffer.Emit<OpCode::Mov>(xmm8, rsi, 4);
buffer.Emit<OpCode::CvtSI2FP, 4, true, 8, false>(xmm8s, rsi, -4);
buffer.Emit<OpCode::CvtSI2FP, 8, true, 4, false>(xmm8, rsi, 4);
buffer.Emit<OpCode::CvtFP2SI>(esi, xmm8s);
buffer.Emit<OpCode::CvtFP2SI>(esi, xmm8);
buffer.Emit<OpCode::CvtSI2FP>(xmm8s, esi);
buffer.Emit<OpCode::CvtSI2FP>(xmm8, esi);
buffer.Emit<OpCode::CvtFP2SI>(rsi, xmm8s);
buffer.Emit<OpCode::CvtFP2SI>(rsi, xmm8);
buffer.Emit<OpCode::CvtSI2FP>(xmm8s, rsi);
buffer.Emit<OpCode::CvtSI2FP>(xmm8, rsi);
// Between: xmm8 and rdi
buffer.Emit<OpCode::Mov>(rdi, -4, xmm8s);
buffer.Emit<OpCode::Mov>(rdi, 4, xmm8);
buffer.Emit<OpCode::Mov>(xmm8s, rdi, -4);
buffer.Emit<OpCode::Mov>(xmm8, rdi, 4);
buffer.Emit<OpCode::CvtSI2FP, 4, true, 8, false>(xmm8s, rdi, -4);
buffer.Emit<OpCode::CvtSI2FP, 8, true, 4, false>(xmm8, rdi, 4);
buffer.Emit<OpCode::CvtFP2SI>(edi, xmm8s);
buffer.Emit<OpCode::CvtFP2SI>(edi, xmm8);
buffer.Emit<OpCode::CvtSI2FP>(xmm8s, edi);
buffer.Emit<OpCode::CvtSI2FP>(xmm8, edi);
buffer.Emit<OpCode::CvtFP2SI>(rdi, xmm8s);
buffer.Emit<OpCode::CvtFP2SI>(rdi, xmm8);
buffer.Emit<OpCode::CvtSI2FP>(xmm8s, rdi);
buffer.Emit<OpCode::CvtSI2FP>(xmm8, rdi);
// Between: xmm8 and r8
buffer.Emit<OpCode::Mov>(r8, -4, xmm8s);
buffer.Emit<OpCode::Mov>(r8, 4, xmm8);
buffer.Emit<OpCode::Mov>(xmm8s, r8, -4);
buffer.Emit<OpCode::Mov>(xmm8, r8, 4);
buffer.Emit<OpCode::CvtSI2FP, 4, true, 8, false>(xmm8s, r8, -4);
buffer.Emit<OpCode::CvtSI2FP, 8, true, 4, false>(xmm8, r8, 4);
buffer.Emit<OpCode::CvtFP2SI>(r8d, xmm8s);
buffer.Emit<OpCode::CvtFP2SI>(r8d, xmm8);
buffer.Emit<OpCode::CvtSI2FP>(xmm8s, r8d);
buffer.Emit<OpCode::CvtSI2FP>(xmm8, r8d);
buffer.Emit<OpCode::CvtFP2SI>(r8, xmm8s);
buffer.Emit<OpCode::CvtFP2SI>(r8, xmm8);
buffer.Emit<OpCode::CvtSI2FP>(xmm8s, r8);
buffer.Emit<OpCode::CvtSI2FP>(xmm8, r8);
// Between: xmm8 and r9
buffer.Emit<OpCode::Mov>(r9, -4, xmm8s);
buffer.Emit<OpCode::Mov>(r9, 4, xmm8);
buffer.Emit<OpCode::Mov>(xmm8s, r9, -4);
buffer.Emit<OpCode::Mov>(xmm8, r9, 4);
buffer.Emit<OpCode::CvtSI2FP, 4, true, 8, false>(xmm8s, r9, -4);
buffer.Emit<OpCode::CvtSI2FP, 8, true, 4, false>(xmm8, r9, 4);
buffer.Emit<OpCode::CvtFP2SI>(r9d, xmm8s);
buffer.Emit<OpCode::CvtFP2SI>(r9d, xmm8);
buffer.Emit<OpCode::CvtSI2FP>(xmm8s, r9d);
buffer.Emit<OpCode::CvtSI2FP>(xmm8, r9d);
buffer.Emit<OpCode::CvtFP2SI>(r9, xmm8s);
buffer.Emit<OpCode::CvtFP2SI>(r9, xmm8);
buffer.Emit<OpCode::CvtSI2FP>(xmm8s, r9);
buffer.Emit<OpCode::CvtSI2FP>(xmm8, r9);
// Between: xmm8 and r10
buffer.Emit<OpCode::Mov>(r10, -4, xmm8s);
buffer.Emit<OpCode::Mov>(r10, 4, xmm8);
buffer.Emit<OpCode::Mov>(xmm8s, r10, -4);
buffer.Emit<OpCode::Mov>(xmm8, r10, 4);
buffer.Emit<OpCode::CvtSI2FP, 4, true, 8, false>(xmm8s, r10, -4);
buffer.Emit<OpCode::CvtSI2FP, 8, true, 4, false>(xmm8, r10, 4);
buffer.Emit<OpCode::CvtFP2SI>(r10d, xmm8s);
buffer.Emit<OpCode::CvtFP2SI>(r10d, xmm8);
buffer.Emit<OpCode::CvtSI2FP>(xmm8s, r10d);
buffer.Emit<OpCode::CvtSI2FP>(xmm8, r10d);
buffer.Emit<OpCode::CvtFP2SI>(r10, xmm8s);
buffer.Emit<OpCode::CvtFP2SI>(r10, xmm8);
buffer.Emit<OpCode::CvtSI2FP>(xmm8s, r10);
buffer.Emit<OpCode::CvtSI2FP>(xmm8, r10);
// Between: xmm8 and r11
buffer.Emit<OpCode::Mov>(r11, -4, xmm8s);
buffer.Emit<OpCode::Mov>(r11, 4, xmm8);
buffer.Emit<OpCode::Mov>(xmm8s, r11, -4);
buffer.Emit<OpCode::Mov>(xmm8, r11, 4);
buffer.Emit<OpCode::CvtSI2FP, 4, true, 8, false>(xmm8s, r11, -4);
buffer.Emit<OpCode::CvtSI2FP, 8, true, 4, false>(xmm8, r11, 4);
buffer.Emit<OpCode::CvtFP2SI>(r11d, xmm8s);
buffer.Emit<OpCode::CvtFP2SI>(r11d, xmm8);
buffer.Emit<OpCode::CvtSI2FP>(xmm8s, r11d);
buffer.Emit<OpCode::CvtSI2FP>(xmm8, r11d);
buffer.Emit<OpCode::CvtFP2SI>(r11, xmm8s);
buffer.Emit<OpCode::CvtFP2SI>(r11, xmm8);
buffer.Emit<OpCode::CvtSI2FP>(xmm8s, r11);
buffer.Emit<OpCode::CvtSI2FP>(xmm8, r11);
// Between: xmm8 and r12
buffer.Emit<OpCode::Mov>(r12, -4, xmm8s);
buffer.Emit<OpCode::Mov>(r12, 4, xmm8);
buffer.Emit<OpCode::Mov>(xmm8s, r12, -4);
buffer.Emit<OpCode::Mov>(xmm8, r12, 4);
buffer.Emit<OpCode::CvtSI2FP, 4, true, 8, false>(xmm8s, r12, -4);
buffer.Emit<OpCode::CvtSI2FP, 8, true, 4, false>(xmm8, r12, 4);
buffer.Emit<OpCode::CvtFP2SI>(r12d, xmm8s);
buffer.Emit<OpCode::CvtFP2SI>(r12d, xmm8);
buffer.Emit<OpCode::CvtSI2FP>(xmm8s, r12d);
buffer.Emit<OpCode::CvtSI2FP>(xmm8, r12d);
buffer.Emit<OpCode::CvtFP2SI>(r12, xmm8s);
buffer.Emit<OpCode::CvtFP2SI>(r12, xmm8);
buffer.Emit<OpCode::CvtSI2FP>(xmm8s, r12);
buffer.Emit<OpCode::CvtSI2FP>(xmm8, r12);
// Between: xmm8 and r13
buffer.Emit<OpCode::Mov>(r13, -4, xmm8s);
buffer.Emit<OpCode::Mov>(r13, 4, xmm8);
buffer.Emit<OpCode::Mov>(xmm8s, r13, -4);
buffer.Emit<OpCode::Mov>(xmm8, r13, 4);
buffer.Emit<OpCode::CvtSI2FP, 4, true, 8, false>(xmm8s, r13, -4);
buffer.Emit<OpCode::CvtSI2FP, 8, true, 4, false>(xmm8, r13, 4);
buffer.Emit<OpCode::CvtFP2SI>(r13d, xmm8s);
buffer.Emit<OpCode::CvtFP2SI>(r13d, xmm8);
buffer.Emit<OpCode::CvtSI2FP>(xmm8s, r13d);
buffer.Emit<OpCode::CvtSI2FP>(xmm8, r13d);
buffer.Emit<OpCode::CvtFP2SI>(r13, xmm8s);
buffer.Emit<OpCode::CvtFP2SI>(r13, xmm8);
buffer.Emit<OpCode::CvtSI2FP>(xmm8s, r13);
buffer.Emit<OpCode::CvtSI2FP>(xmm8, r13);
// Between: xmm8 and r14
buffer.Emit<OpCode::Mov>(r14, -4, xmm8s);
buffer.Emit<OpCode::Mov>(r14, 4, xmm8);
buffer.Emit<OpCode::Mov>(xmm8s, r14, -4);
buffer.Emit<OpCode::Mov>(xmm8, r14, 4);
buffer.Emit<OpCode::CvtSI2FP, 4, true, 8, false>(xmm8s, r14, -4);
buffer.Emit<OpCode::CvtSI2FP, 8, true, 4, false>(xmm8, r14, 4);
buffer.Emit<OpCode::CvtFP2SI>(r14d, xmm8s);
buffer.Emit<OpCode::CvtFP2SI>(r14d, xmm8);
buffer.Emit<OpCode::CvtSI2FP>(xmm8s, r14d);
buffer.Emit<OpCode::CvtSI2FP>(xmm8, r14d);
buffer.Emit<OpCode::CvtFP2SI>(r14, xmm8s);
buffer.Emit<OpCode::CvtFP2SI>(r14, xmm8);
buffer.Emit<OpCode::CvtSI2FP>(xmm8s, r14);
buffer.Emit<OpCode::CvtSI2FP>(xmm8, r14);
// Between: xmm8 and r15
buffer.Emit<OpCode::Mov>(r15, -4, xmm8s);
buffer.Emit<OpCode::Mov>(r15, 4, xmm8);
buffer.Emit<OpCode::Mov>(xmm8s, r15, -4);
buffer.Emit<OpCode::Mov>(xmm8, r15, 4);
buffer.Emit<OpCode::CvtSI2FP, 4, true, 8, false>(xmm8s, r15, -4);
buffer.Emit<OpCode::CvtSI2FP, 8, true, 4, false>(xmm8, r15, 4);
buffer.Emit<OpCode::CvtFP2SI>(r15d, xmm8s);
buffer.Emit<OpCode::CvtFP2SI>(r15d, xmm8);
buffer.Emit<OpCode::CvtSI2FP>(xmm8s, r15d);
buffer.Emit<OpCode::CvtSI2FP>(xmm8, r15d);
buffer.Emit<OpCode::CvtFP2SI>(r15, xmm8s);
buffer.Emit<OpCode::CvtFP2SI>(r15, xmm8);
buffer.Emit<OpCode::CvtSI2FP>(xmm8s, r15);
buffer.Emit<OpCode::CvtSI2FP>(xmm8, r15);
// Between: xmm9 and rax
buffer.Emit<OpCode::Mov>(rax, -4, xmm9s);
buffer.Emit<OpCode::Mov>(rax, 4, xmm9);
buffer.Emit<OpCode::Mov>(xmm9s, rax, -4);
buffer.Emit<OpCode::Mov>(xmm9, rax, 4);
buffer.Emit<OpCode::CvtSI2FP, 4, true, 8, false>(xmm9s, rax, -4);
buffer.Emit<OpCode::CvtSI2FP, 8, true, 4, false>(xmm9, rax, 4);
buffer.Emit<OpCode::CvtFP2SI>(eax, xmm9s);
buffer.Emit<OpCode::CvtFP2SI>(eax, xmm9);
buffer.Emit<OpCode::CvtSI2FP>(xmm9s, eax);
buffer.Emit<OpCode::CvtSI2FP>(xmm9, eax);
buffer.Emit<OpCode::CvtFP2SI>(rax, xmm9s);
buffer.Emit<OpCode::CvtFP2SI>(rax, xmm9);
buffer.Emit<OpCode::CvtSI2FP>(xmm9s, rax);
buffer.Emit<OpCode::CvtSI2FP>(xmm9, rax);
// Between: xmm9 and rcx
buffer.Emit<OpCode::Mov>(rcx, -4, xmm9s);
buffer.Emit<OpCode::Mov>(rcx, 4, xmm9);
buffer.Emit<OpCode::Mov>(xmm9s, rcx, -4);
buffer.Emit<OpCode::Mov>(xmm9, rcx, 4);
buffer.Emit<OpCode::CvtSI2FP, 4, true, 8, false>(xmm9s, rcx, -4);
buffer.Emit<OpCode::CvtSI2FP, 8, true, 4, false>(xmm9, rcx, 4);
buffer.Emit<OpCode::CvtFP2SI>(ecx, xmm9s);
buffer.Emit<OpCode::CvtFP2SI>(ecx, xmm9);
buffer.Emit<OpCode::CvtSI2FP>(xmm9s, ecx);
buffer.Emit<OpCode::CvtSI2FP>(xmm9, ecx);
buffer.Emit<OpCode::CvtFP2SI>(rcx, xmm9s);
buffer.Emit<OpCode::CvtFP2SI>(rcx, xmm9);
buffer.Emit<OpCode::CvtSI2FP>(xmm9s, rcx);
buffer.Emit<OpCode::CvtSI2FP>(xmm9, rcx);
// Between: xmm9 and rdx
buffer.Emit<OpCode::Mov>(rdx, -4, xmm9s);
buffer.Emit<OpCode::Mov>(rdx, 4, xmm9);
buffer.Emit<OpCode::Mov>(xmm9s, rdx, -4);
buffer.Emit<OpCode::Mov>(xmm9, rdx, 4);
buffer.Emit<OpCode::CvtSI2FP, 4, true, 8, false>(xmm9s, rdx, -4);
buffer.Emit<OpCode::CvtSI2FP, 8, true, 4, false>(xmm9, rdx, 4);
buffer.Emit<OpCode::CvtFP2SI>(edx, xmm9s);
buffer.Emit<OpCode::CvtFP2SI>(edx, xmm9);
buffer.Emit<OpCode::CvtSI2FP>(xmm9s, edx);
buffer.Emit<OpCode::CvtSI2FP>(xmm9, edx);
buffer.Emit<OpCode::CvtFP2SI>(rdx, xmm9s);
buffer.Emit<OpCode::CvtFP2SI>(rdx, xmm9);
buffer.Emit<OpCode::CvtSI2FP>(xmm9s, rdx);
buffer.Emit<OpCode::CvtSI2FP>(xmm9, rdx);
// Between: xmm9 and rbx
buffer.Emit<OpCode::Mov>(rbx, -4, xmm9s);
buffer.Emit<OpCode::Mov>(rbx, 4, xmm9);
buffer.Emit<OpCode::Mov>(xmm9s, rbx, -4);
buffer.Emit<OpCode::Mov>(xmm9, rbx, 4);
buffer.Emit<OpCode::CvtSI2FP, 4, true, 8, false>(xmm9s, rbx, -4);
buffer.Emit<OpCode::CvtSI2FP, 8, true, 4, false>(xmm9, rbx, 4);
buffer.Emit<OpCode::CvtFP2SI>(ebx, xmm9s);
buffer.Emit<OpCode::CvtFP2SI>(ebx, xmm9);
buffer.Emit<OpCode::CvtSI2FP>(xmm9s, ebx);
buffer.Emit<OpCode::CvtSI2FP>(xmm9, ebx);
buffer.Emit<OpCode::CvtFP2SI>(rbx, xmm9s);
buffer.Emit<OpCode::CvtFP2SI>(rbx, xmm9);
buffer.Emit<OpCode::CvtSI2FP>(xmm9s, rbx);
buffer.Emit<OpCode::CvtSI2FP>(xmm9, rbx);
// Between: xmm9 and rsp
buffer.Emit<OpCode::Mov>(rsp, -4, xmm9s);
buffer.Emit<OpCode::Mov>(rsp, 4, xmm9);
buffer.Emit<OpCode::Mov>(xmm9s, rsp, -4);
buffer.Emit<OpCode::Mov>(xmm9, rsp, 4);
buffer.Emit<OpCode::CvtSI2FP, 4, true, 8, false>(xmm9s, rsp, -4);
buffer.Emit<OpCode::CvtSI2FP, 8, true, 4, false>(xmm9, rsp, 4);
buffer.Emit<OpCode::CvtFP2SI>(esp, xmm9s);
buffer.Emit<OpCode::CvtFP2SI>(esp, xmm9);
buffer.Emit<OpCode::CvtSI2FP>(xmm9s, esp);
buffer.Emit<OpCode::CvtSI2FP>(xmm9, esp);
buffer.Emit<OpCode::CvtFP2SI>(rsp, xmm9s);
buffer.Emit<OpCode::CvtFP2SI>(rsp, xmm9);
buffer.Emit<OpCode::CvtSI2FP>(xmm9s, rsp);
buffer.Emit<OpCode::CvtSI2FP>(xmm9, rsp);
// Between: xmm9 and rbp
buffer.Emit<OpCode::Mov>(rbp, -4, xmm9s);
buffer.Emit<OpCode::Mov>(rbp, 4, xmm9);
buffer.Emit<OpCode::Mov>(xmm9s, rbp, -4);
buffer.Emit<OpCode::Mov>(xmm9, rbp, 4);
buffer.Emit<OpCode::CvtSI2FP, 4, true, 8, false>(xmm9s, rbp, -4);
buffer.Emit<OpCode::CvtSI2FP, 8, true, 4, false>(xmm9, rbp, 4);
buffer.Emit<OpCode::CvtFP2SI>(ebp, xmm9s);
buffer.Emit<OpCode::CvtFP2SI>(ebp, xmm9);
buffer.Emit<OpCode::CvtSI2FP>(xmm9s, ebp);
buffer.Emit<OpCode::CvtSI2FP>(xmm9, ebp);
buffer.Emit<OpCode::CvtFP2SI>(rbp, xmm9s);
buffer.Emit<OpCode::CvtFP2SI>(rbp, xmm9);
buffer.Emit<OpCode::CvtSI2FP>(xmm9s, rbp);
buffer.Emit<OpCode::CvtSI2FP>(xmm9, rbp);
// Between: xmm9 and rsi
buffer.Emit<OpCode::Mov>(rsi, -4, xmm9s);
buffer.Emit<OpCode::Mov>(rsi, 4, xmm9);
buffer.Emit<OpCode::Mov>(xmm9s, rsi, -4);
buffer.Emit<OpCode::Mov>(xmm9, rsi, 4);
buffer.Emit<OpCode::CvtSI2FP, 4, true, 8, false>(xmm9s, rsi, -4);
buffer.Emit<OpCode::CvtSI2FP, 8, true, 4, false>(xmm9, rsi, 4);
buffer.Emit<OpCode::CvtFP2SI>(esi, xmm9s);
buffer.Emit<OpCode::CvtFP2SI>(esi, xmm9);
buffer.Emit<OpCode::CvtSI2FP>(xmm9s, esi);
buffer.Emit<OpCode::CvtSI2FP>(xmm9, esi);
buffer.Emit<OpCode::CvtFP2SI>(rsi, xmm9s);
buffer.Emit<OpCode::CvtFP2SI>(rsi, xmm9);
buffer.Emit<OpCode::CvtSI2FP>(xmm9s, rsi);
buffer.Emit<OpCode::CvtSI2FP>(xmm9, rsi);
// Between: xmm9 and rdi
buffer.Emit<OpCode::Mov>(rdi, -4, xmm9s);
buffer.Emit<OpCode::Mov>(rdi, 4, xmm9);
buffer.Emit<OpCode::Mov>(xmm9s, rdi, -4);
buffer.Emit<OpCode::Mov>(xmm9, rdi, 4);
buffer.Emit<OpCode::CvtSI2FP, 4, true, 8, false>(xmm9s, rdi, -4);
buffer.Emit<OpCode::CvtSI2FP, 8, true, 4, false>(xmm9, rdi, 4);
buffer.Emit<OpCode::CvtFP2SI>(edi, xmm9s);
buffer.Emit<OpCode::CvtFP2SI>(edi, xmm9);
buffer.Emit<OpCode::CvtSI2FP>(xmm9s, edi);
buffer.Emit<OpCode::CvtSI2FP>(xmm9, edi);
buffer.Emit<OpCode::CvtFP2SI>(rdi, xmm9s);
buffer.Emit<OpCode::CvtFP2SI>(rdi, xmm9);
buffer.Emit<OpCode::CvtSI2FP>(xmm9s, rdi);
buffer.Emit<OpCode::CvtSI2FP>(xmm9, rdi);
// Between: xmm9 and r8
buffer.Emit<OpCode::Mov>(r8, -4, xmm9s);
buffer.Emit<OpCode::Mov>(r8, 4, xmm9);
buffer.Emit<OpCode::Mov>(xmm9s, r8, -4);
buffer.Emit<OpCode::Mov>(xmm9, r8, 4);
buffer.Emit<OpCode::CvtSI2FP, 4, true, 8, false>(xmm9s, r8, -4);
buffer.Emit<OpCode::CvtSI2FP, 8, true, 4, false>(xmm9, r8, 4);
buffer.Emit<OpCode::CvtFP2SI>(r8d, xmm9s);
buffer.Emit<OpCode::CvtFP2SI>(r8d, xmm9);
buffer.Emit<OpCode::CvtSI2FP>(xmm9s, r8d);
buffer.Emit<OpCode::CvtSI2FP>(xmm9, r8d);
buffer.Emit<OpCode::CvtFP2SI>(r8, xmm9s);
buffer.Emit<OpCode::CvtFP2SI>(r8, xmm9);
buffer.Emit<OpCode::CvtSI2FP>(xmm9s, r8);
buffer.Emit<OpCode::CvtSI2FP>(xmm9, r8);
// Between: xmm9 and r9
buffer.Emit<OpCode::Mov>(r9, -4, xmm9s);
buffer.Emit<OpCode::Mov>(r9, 4, xmm9);
buffer.Emit<OpCode::Mov>(xmm9s, r9, -4);
buffer.Emit<OpCode::Mov>(xmm9, r9, 4);
buffer.Emit<OpCode::CvtSI2FP, 4, true, 8, false>(xmm9s, r9, -4);
buffer.Emit<OpCode::CvtSI2FP, 8, true, 4, false>(xmm9, r9, 4);
buffer.Emit<OpCode::CvtFP2SI>(r9d, xmm9s);
buffer.Emit<OpCode::CvtFP2SI>(r9d, xmm9);
buffer.Emit<OpCode::CvtSI2FP>(xmm9s, r9d);
buffer.Emit<OpCode::CvtSI2FP>(xmm9, r9d);
buffer.Emit<OpCode::CvtFP2SI>(r9, xmm9s);
buffer.Emit<OpCode::CvtFP2SI>(r9, xmm9);
buffer.Emit<OpCode::CvtSI2FP>(xmm9s, r9);
buffer.Emit<OpCode::CvtSI2FP>(xmm9, r9);
// Between: xmm9 and r10
buffer.Emit<OpCode::Mov>(r10, -4, xmm9s);
buffer.Emit<OpCode::Mov>(r10, 4, xmm9);
buffer.Emit<OpCode::Mov>(xmm9s, r10, -4);
buffer.Emit<OpCode::Mov>(xmm9, r10, 4);
buffer.Emit<OpCode::CvtSI2FP, 4, true, 8, false>(xmm9s, r10, -4);
buffer.Emit<OpCode::CvtSI2FP, 8, true, 4, false>(xmm9, r10, 4);
buffer.Emit<OpCode::CvtFP2SI>(r10d, xmm9s);
buffer.Emit<OpCode::CvtFP2SI>(r10d, xmm9);
buffer.Emit<OpCode::CvtSI2FP>(xmm9s, r10d);
buffer.Emit<OpCode::CvtSI2FP>(xmm9, r10d);
buffer.Emit<OpCode::CvtFP2SI>(r10, xmm9s);
buffer.Emit<OpCode::CvtFP2SI>(r10, xmm9);
buffer.Emit<OpCode::CvtSI2FP>(xmm9s, r10);
buffer.Emit<OpCode::CvtSI2FP>(xmm9, r10);
// Between: xmm9 and r11
buffer.Emit<OpCode::Mov>(r11, -4, xmm9s);
buffer.Emit<OpCode::Mov>(r11, 4, xmm9);
buffer.Emit<OpCode::Mov>(xmm9s, r11, -4);
buffer.Emit<OpCode::Mov>(xmm9, r11, 4);
buffer.Emit<OpCode::CvtSI2FP, 4, true, 8, false>(xmm9s, r11, -4);
buffer.Emit<OpCode::CvtSI2FP, 8, true, 4, false>(xmm9, r11, 4);
buffer.Emit<OpCode::CvtFP2SI>(r11d, xmm9s);
buffer.Emit<OpCode::CvtFP2SI>(r11d, xmm9);
buffer.Emit<OpCode::CvtSI2FP>(xmm9s, r11d);
buffer.Emit<OpCode::CvtSI2FP>(xmm9, r11d);
buffer.Emit<OpCode::CvtFP2SI>(r11, xmm9s);
buffer.Emit<OpCode::CvtFP2SI>(r11, xmm9);
buffer.Emit<OpCode::CvtSI2FP>(xmm9s, r11);
buffer.Emit<OpCode::CvtSI2FP>(xmm9, r11);
// Between: xmm9 and r12
buffer.Emit<OpCode::Mov>(r12, -4, xmm9s);
buffer.Emit<OpCode::Mov>(r12, 4, xmm9);
buffer.Emit<OpCode::Mov>(xmm9s, r12, -4);
buffer.Emit<OpCode::Mov>(xmm9, r12, 4);
buffer.Emit<OpCode::CvtSI2FP, 4, true, 8, false>(xmm9s, r12, -4);
buffer.Emit<OpCode::CvtSI2FP, 8, true, 4, false>(xmm9, r12, 4);
buffer.Emit<OpCode::CvtFP2SI>(r12d, xmm9s);
buffer.Emit<OpCode::CvtFP2SI>(r12d, xmm9);
buffer.Emit<OpCode::CvtSI2FP>(xmm9s, r12d);
buffer.Emit<OpCode::CvtSI2FP>(xmm9, r12d);
buffer.Emit<OpCode::CvtFP2SI>(r12, xmm9s);
buffer.Emit<OpCode::CvtFP2SI>(r12, xmm9);
buffer.Emit<OpCode::CvtSI2FP>(xmm9s, r12);
buffer.Emit<OpCode::CvtSI2FP>(xmm9, r12);
// Between: xmm9 and r13
buffer.Emit<OpCode::Mov>(r13, -4, xmm9s);
buffer.Emit<OpCode::Mov>(r13, 4, xmm9);
buffer.Emit<OpCode::Mov>(xmm9s, r13, -4);
buffer.Emit<OpCode::Mov>(xmm9, r13, 4);
buffer.Emit<OpCode::CvtSI2FP, 4, true, 8, false>(xmm9s, r13, -4);
buffer.Emit<OpCode::CvtSI2FP, 8, true, 4, false>(xmm9, r13, 4);
buffer.Emit<OpCode::CvtFP2SI>(r13d, xmm9s);
buffer.Emit<OpCode::CvtFP2SI>(r13d, xmm9);
buffer.Emit<OpCode::CvtSI2FP>(xmm9s, r13d);
buffer.Emit<OpCode::CvtSI2FP>(xmm9, r13d);
buffer.Emit<OpCode::CvtFP2SI>(r13, xmm9s);
buffer.Emit<OpCode::CvtFP2SI>(r13, xmm9);
buffer.Emit<OpCode::CvtSI2FP>(xmm9s, r13);
buffer.Emit<OpCode::CvtSI2FP>(xmm9, r13);
// Between: xmm9 and r14
buffer.Emit<OpCode::Mov>(r14, -4, xmm9s);
buffer.Emit<OpCode::Mov>(r14, 4, xmm9);
buffer.Emit<OpCode::Mov>(xmm9s, r14, -4);
buffer.Emit<OpCode::Mov>(xmm9, r14, 4);
buffer.Emit<OpCode::CvtSI2FP, 4, true, 8, false>(xmm9s, r14, -4);
buffer.Emit<OpCode::CvtSI2FP, 8, true, 4, false>(xmm9, r14, 4);
buffer.Emit<OpCode::CvtFP2SI>(r14d, xmm9s);
buffer.Emit<OpCode::CvtFP2SI>(r14d, xmm9);
buffer.Emit<OpCode::CvtSI2FP>(xmm9s, r14d);
buffer.Emit<OpCode::CvtSI2FP>(xmm9, r14d);
buffer.Emit<OpCode::CvtFP2SI>(r14, xmm9s);
buffer.Emit<OpCode::CvtFP2SI>(r14, xmm9);
buffer.Emit<OpCode::CvtSI2FP>(xmm9s, r14);
buffer.Emit<OpCode::CvtSI2FP>(xmm9, r14);
// Between: xmm9 and r15
buffer.Emit<OpCode::Mov>(r15, -4, xmm9s);
buffer.Emit<OpCode::Mov>(r15, 4, xmm9);
buffer.Emit<OpCode::Mov>(xmm9s, r15, -4);
buffer.Emit<OpCode::Mov>(xmm9, r15, 4);
buffer.Emit<OpCode::CvtSI2FP, 4, true, 8, false>(xmm9s, r15, -4);
buffer.Emit<OpCode::CvtSI2FP, 8, true, 4, false>(xmm9, r15, 4);
buffer.Emit<OpCode::CvtFP2SI>(r15d, xmm9s);
buffer.Emit<OpCode::CvtFP2SI>(r15d, xmm9);
buffer.Emit<OpCode::CvtSI2FP>(xmm9s, r15d);
buffer.Emit<OpCode::CvtSI2FP>(xmm9, r15d);
buffer.Emit<OpCode::CvtFP2SI>(r15, xmm9s);
buffer.Emit<OpCode::CvtFP2SI>(r15, xmm9);
buffer.Emit<OpCode::CvtSI2FP>(xmm9s, r15);
buffer.Emit<OpCode::CvtSI2FP>(xmm9, r15);
// Between: xmm10 and rax
buffer.Emit<OpCode::Mov>(rax, -4, xmm10s);
buffer.Emit<OpCode::Mov>(rax, 4, xmm10);
buffer.Emit<OpCode::Mov>(xmm10s, rax, -4);
buffer.Emit<OpCode::Mov>(xmm10, rax, 4);
buffer.Emit<OpCode::CvtSI2FP, 4, true, 8, false>(xmm10s, rax, -4);
buffer.Emit<OpCode::CvtSI2FP, 8, true, 4, false>(xmm10, rax, 4);
buffer.Emit<OpCode::CvtFP2SI>(eax, xmm10s);
buffer.Emit<OpCode::CvtFP2SI>(eax, xmm10);
buffer.Emit<OpCode::CvtSI2FP>(xmm10s, eax);
buffer.Emit<OpCode::CvtSI2FP>(xmm10, eax);
buffer.Emit<OpCode::CvtFP2SI>(rax, xmm10s);
buffer.Emit<OpCode::CvtFP2SI>(rax, xmm10);
buffer.Emit<OpCode::CvtSI2FP>(xmm10s, rax);
buffer.Emit<OpCode::CvtSI2FP>(xmm10, rax);
// Between: xmm10 and rcx
buffer.Emit<OpCode::Mov>(rcx, -4, xmm10s);
buffer.Emit<OpCode::Mov>(rcx, 4, xmm10);
buffer.Emit<OpCode::Mov>(xmm10s, rcx, -4);
buffer.Emit<OpCode::Mov>(xmm10, rcx, 4);
buffer.Emit<OpCode::CvtSI2FP, 4, true, 8, false>(xmm10s, rcx, -4);
buffer.Emit<OpCode::CvtSI2FP, 8, true, 4, false>(xmm10, rcx, 4);
buffer.Emit<OpCode::CvtFP2SI>(ecx, xmm10s);
buffer.Emit<OpCode::CvtFP2SI>(ecx, xmm10);
buffer.Emit<OpCode::CvtSI2FP>(xmm10s, ecx);
buffer.Emit<OpCode::CvtSI2FP>(xmm10, ecx);
buffer.Emit<OpCode::CvtFP2SI>(rcx, xmm10s);
buffer.Emit<OpCode::CvtFP2SI>(rcx, xmm10);
buffer.Emit<OpCode::CvtSI2FP>(xmm10s, rcx);
buffer.Emit<OpCode::CvtSI2FP>(xmm10, rcx);
// Between: xmm10 and rdx
buffer.Emit<OpCode::Mov>(rdx, -4, xmm10s);
buffer.Emit<OpCode::Mov>(rdx, 4, xmm10);
buffer.Emit<OpCode::Mov>(xmm10s, rdx, -4);
buffer.Emit<OpCode::Mov>(xmm10, rdx, 4);
buffer.Emit<OpCode::CvtSI2FP, 4, true, 8, false>(xmm10s, rdx, -4);
buffer.Emit<OpCode::CvtSI2FP, 8, true, 4, false>(xmm10, rdx, 4);
buffer.Emit<OpCode::CvtFP2SI>(edx, xmm10s);
buffer.Emit<OpCode::CvtFP2SI>(edx, xmm10);
buffer.Emit<OpCode::CvtSI2FP>(xmm10s, edx);
buffer.Emit<OpCode::CvtSI2FP>(xmm10, edx);
buffer.Emit<OpCode::CvtFP2SI>(rdx, xmm10s);
buffer.Emit<OpCode::CvtFP2SI>(rdx, xmm10);
buffer.Emit<OpCode::CvtSI2FP>(xmm10s, rdx);
buffer.Emit<OpCode::CvtSI2FP>(xmm10, rdx);
// Between: xmm10 and rbx
buffer.Emit<OpCode::Mov>(rbx, -4, xmm10s);
buffer.Emit<OpCode::Mov>(rbx, 4, xmm10);
buffer.Emit<OpCode::Mov>(xmm10s, rbx, -4);
buffer.Emit<OpCode::Mov>(xmm10, rbx, 4);
buffer.Emit<OpCode::CvtSI2FP, 4, true, 8, false>(xmm10s, rbx, -4);
buffer.Emit<OpCode::CvtSI2FP, 8, true, 4, false>(xmm10, rbx, 4);
buffer.Emit<OpCode::CvtFP2SI>(ebx, xmm10s);
buffer.Emit<OpCode::CvtFP2SI>(ebx, xmm10);
buffer.Emit<OpCode::CvtSI2FP>(xmm10s, ebx);
buffer.Emit<OpCode::CvtSI2FP>(xmm10, ebx);
buffer.Emit<OpCode::CvtFP2SI>(rbx, xmm10s);
buffer.Emit<OpCode::CvtFP2SI>(rbx, xmm10);
buffer.Emit<OpCode::CvtSI2FP>(xmm10s, rbx);
buffer.Emit<OpCode::CvtSI2FP>(xmm10, rbx);
// Between: xmm10 and rsp
buffer.Emit<OpCode::Mov>(rsp, -4, xmm10s);
buffer.Emit<OpCode::Mov>(rsp, 4, xmm10);
buffer.Emit<OpCode::Mov>(xmm10s, rsp, -4);
buffer.Emit<OpCode::Mov>(xmm10, rsp, 4);
buffer.Emit<OpCode::CvtSI2FP, 4, true, 8, false>(xmm10s, rsp, -4);
buffer.Emit<OpCode::CvtSI2FP, 8, true, 4, false>(xmm10, rsp, 4);
buffer.Emit<OpCode::CvtFP2SI>(esp, xmm10s);
buffer.Emit<OpCode::CvtFP2SI>(esp, xmm10);
buffer.Emit<OpCode::CvtSI2FP>(xmm10s, esp);
buffer.Emit<OpCode::CvtSI2FP>(xmm10, esp);
buffer.Emit<OpCode::CvtFP2SI>(rsp, xmm10s);
buffer.Emit<OpCode::CvtFP2SI>(rsp, xmm10);
buffer.Emit<OpCode::CvtSI2FP>(xmm10s, rsp);
buffer.Emit<OpCode::CvtSI2FP>(xmm10, rsp);
// Between: xmm10 and rbp
buffer.Emit<OpCode::Mov>(rbp, -4, xmm10s);
buffer.Emit<OpCode::Mov>(rbp, 4, xmm10);
buffer.Emit<OpCode::Mov>(xmm10s, rbp, -4);
buffer.Emit<OpCode::Mov>(xmm10, rbp, 4);
buffer.Emit<OpCode::CvtSI2FP, 4, true, 8, false>(xmm10s, rbp, -4);
buffer.Emit<OpCode::CvtSI2FP, 8, true, 4, false>(xmm10, rbp, 4);
buffer.Emit<OpCode::CvtFP2SI>(ebp, xmm10s);
buffer.Emit<OpCode::CvtFP2SI>(ebp, xmm10);
buffer.Emit<OpCode::CvtSI2FP>(xmm10s, ebp);
buffer.Emit<OpCode::CvtSI2FP>(xmm10, ebp);
buffer.Emit<OpCode::CvtFP2SI>(rbp, xmm10s);
buffer.Emit<OpCode::CvtFP2SI>(rbp, xmm10);
buffer.Emit<OpCode::CvtSI2FP>(xmm10s, rbp);
buffer.Emit<OpCode::CvtSI2FP>(xmm10, rbp);
// Between: xmm10 and rsi
buffer.Emit<OpCode::Mov>(rsi, -4, xmm10s);
buffer.Emit<OpCode::Mov>(rsi, 4, xmm10);
buffer.Emit<OpCode::Mov>(xmm10s, rsi, -4);
buffer.Emit<OpCode::Mov>(xmm10, rsi, 4);
buffer.Emit<OpCode::CvtSI2FP, 4, true, 8, false>(xmm10s, rsi, -4);
buffer.Emit<OpCode::CvtSI2FP, 8, true, 4, false>(xmm10, rsi, 4);
buffer.Emit<OpCode::CvtFP2SI>(esi, xmm10s);
buffer.Emit<OpCode::CvtFP2SI>(esi, xmm10);
buffer.Emit<OpCode::CvtSI2FP>(xmm10s, esi);
buffer.Emit<OpCode::CvtSI2FP>(xmm10, esi);
buffer.Emit<OpCode::CvtFP2SI>(rsi, xmm10s);
buffer.Emit<OpCode::CvtFP2SI>(rsi, xmm10);
buffer.Emit<OpCode::CvtSI2FP>(xmm10s, rsi);
buffer.Emit<OpCode::CvtSI2FP>(xmm10, rsi);
// Between: xmm10 and rdi
buffer.Emit<OpCode::Mov>(rdi, -4, xmm10s);
buffer.Emit<OpCode::Mov>(rdi, 4, xmm10);
buffer.Emit<OpCode::Mov>(xmm10s, rdi, -4);
buffer.Emit<OpCode::Mov>(xmm10, rdi, 4);
buffer.Emit<OpCode::CvtSI2FP, 4, true, 8, false>(xmm10s, rdi, -4);
buffer.Emit<OpCode::CvtSI2FP, 8, true, 4, false>(xmm10, rdi, 4);
buffer.Emit<OpCode::CvtFP2SI>(edi, xmm10s);
buffer.Emit<OpCode::CvtFP2SI>(edi, xmm10);
buffer.Emit<OpCode::CvtSI2FP>(xmm10s, edi);
buffer.Emit<OpCode::CvtSI2FP>(xmm10, edi);
buffer.Emit<OpCode::CvtFP2SI>(rdi, xmm10s);
buffer.Emit<OpCode::CvtFP2SI>(rdi, xmm10);
buffer.Emit<OpCode::CvtSI2FP>(xmm10s, rdi);
buffer.Emit<OpCode::CvtSI2FP>(xmm10, rdi);
// Between: xmm10 and r8
buffer.Emit<OpCode::Mov>(r8, -4, xmm10s);
buffer.Emit<OpCode::Mov>(r8, 4, xmm10);
buffer.Emit<OpCode::Mov>(xmm10s, r8, -4);
buffer.Emit<OpCode::Mov>(xmm10, r8, 4);
buffer.Emit<OpCode::CvtSI2FP, 4, true, 8, false>(xmm10s, r8, -4);
buffer.Emit<OpCode::CvtSI2FP, 8, true, 4, false>(xmm10, r8, 4);
buffer.Emit<OpCode::CvtFP2SI>(r8d, xmm10s);
buffer.Emit<OpCode::CvtFP2SI>(r8d, xmm10);
buffer.Emit<OpCode::CvtSI2FP>(xmm10s, r8d);
buffer.Emit<OpCode::CvtSI2FP>(xmm10, r8d);
buffer.Emit<OpCode::CvtFP2SI>(r8, xmm10s);
buffer.Emit<OpCode::CvtFP2SI>(r8, xmm10);
buffer.Emit<OpCode::CvtSI2FP>(xmm10s, r8);
buffer.Emit<OpCode::CvtSI2FP>(xmm10, r8);
// Between: xmm10 and r9
buffer.Emit<OpCode::Mov>(r9, -4, xmm10s);
buffer.Emit<OpCode::Mov>(r9, 4, xmm10);
buffer.Emit<OpCode::Mov>(xmm10s, r9, -4);
buffer.Emit<OpCode::Mov>(xmm10, r9, 4);
buffer.Emit<OpCode::CvtSI2FP, 4, true, 8, false>(xmm10s, r9, -4);
buffer.Emit<OpCode::CvtSI2FP, 8, true, 4, false>(xmm10, r9, 4);
buffer.Emit<OpCode::CvtFP2SI>(r9d, xmm10s);
buffer.Emit<OpCode::CvtFP2SI>(r9d, xmm10);
buffer.Emit<OpCode::CvtSI2FP>(xmm10s, r9d);
buffer.Emit<OpCode::CvtSI2FP>(xmm10, r9d);
buffer.Emit<OpCode::CvtFP2SI>(r9, xmm10s);
buffer.Emit<OpCode::CvtFP2SI>(r9, xmm10);
buffer.Emit<OpCode::CvtSI2FP>(xmm10s, r9);
buffer.Emit<OpCode::CvtSI2FP>(xmm10, r9);
// Between: xmm10 and r10
buffer.Emit<OpCode::Mov>(r10, -4, xmm10s);
buffer.Emit<OpCode::Mov>(r10, 4, xmm10);
buffer.Emit<OpCode::Mov>(xmm10s, r10, -4);
buffer.Emit<OpCode::Mov>(xmm10, r10, 4);
buffer.Emit<OpCode::CvtSI2FP, 4, true, 8, false>(xmm10s, r10, -4);
buffer.Emit<OpCode::CvtSI2FP, 8, true, 4, false>(xmm10, r10, 4);
buffer.Emit<OpCode::CvtFP2SI>(r10d, xmm10s);
buffer.Emit<OpCode::CvtFP2SI>(r10d, xmm10);
buffer.Emit<OpCode::CvtSI2FP>(xmm10s, r10d);
buffer.Emit<OpCode::CvtSI2FP>(xmm10, r10d);
buffer.Emit<OpCode::CvtFP2SI>(r10, xmm10s);
buffer.Emit<OpCode::CvtFP2SI>(r10, xmm10);
buffer.Emit<OpCode::CvtSI2FP>(xmm10s, r10);
buffer.Emit<OpCode::CvtSI2FP>(xmm10, r10);
// Between: xmm10 and r11
buffer.Emit<OpCode::Mov>(r11, -4, xmm10s);
buffer.Emit<OpCode::Mov>(r11, 4, xmm10);
buffer.Emit<OpCode::Mov>(xmm10s, r11, -4);
buffer.Emit<OpCode::Mov>(xmm10, r11, 4);
buffer.Emit<OpCode::CvtSI2FP, 4, true, 8, false>(xmm10s, r11, -4);
buffer.Emit<OpCode::CvtSI2FP, 8, true, 4, false>(xmm10, r11, 4);
buffer.Emit<OpCode::CvtFP2SI>(r11d, xmm10s);
buffer.Emit<OpCode::CvtFP2SI>(r11d, xmm10);
buffer.Emit<OpCode::CvtSI2FP>(xmm10s, r11d);
buffer.Emit<OpCode::CvtSI2FP>(xmm10, r11d);
buffer.Emit<OpCode::CvtFP2SI>(r11, xmm10s);
buffer.Emit<OpCode::CvtFP2SI>(r11, xmm10);
buffer.Emit<OpCode::CvtSI2FP>(xmm10s, r11);
buffer.Emit<OpCode::CvtSI2FP>(xmm10, r11);
// Between: xmm10 and r12
buffer.Emit<OpCode::Mov>(r12, -4, xmm10s);
buffer.Emit<OpCode::Mov>(r12, 4, xmm10);
buffer.Emit<OpCode::Mov>(xmm10s, r12, -4);
buffer.Emit<OpCode::Mov>(xmm10, r12, 4);
buffer.Emit<OpCode::CvtSI2FP, 4, true, 8, false>(xmm10s, r12, -4);
buffer.Emit<OpCode::CvtSI2FP, 8, true, 4, false>(xmm10, r12, 4);
buffer.Emit<OpCode::CvtFP2SI>(r12d, xmm10s);
buffer.Emit<OpCode::CvtFP2SI>(r12d, xmm10);
buffer.Emit<OpCode::CvtSI2FP>(xmm10s, r12d);
buffer.Emit<OpCode::CvtSI2FP>(xmm10, r12d);
buffer.Emit<OpCode::CvtFP2SI>(r12, xmm10s);
buffer.Emit<OpCode::CvtFP2SI>(r12, xmm10);
buffer.Emit<OpCode::CvtSI2FP>(xmm10s, r12);
buffer.Emit<OpCode::CvtSI2FP>(xmm10, r12);
// Between: xmm10 and r13
buffer.Emit<OpCode::Mov>(r13, -4, xmm10s);
buffer.Emit<OpCode::Mov>(r13, 4, xmm10);
buffer.Emit<OpCode::Mov>(xmm10s, r13, -4);
buffer.Emit<OpCode::Mov>(xmm10, r13, 4);
buffer.Emit<OpCode::CvtSI2FP, 4, true, 8, false>(xmm10s, r13, -4);
buffer.Emit<OpCode::CvtSI2FP, 8, true, 4, false>(xmm10, r13, 4);
buffer.Emit<OpCode::CvtFP2SI>(r13d, xmm10s);
buffer.Emit<OpCode::CvtFP2SI>(r13d, xmm10);
buffer.Emit<OpCode::CvtSI2FP>(xmm10s, r13d);
buffer.Emit<OpCode::CvtSI2FP>(xmm10, r13d);
buffer.Emit<OpCode::CvtFP2SI>(r13, xmm10s);
buffer.Emit<OpCode::CvtFP2SI>(r13, xmm10);
buffer.Emit<OpCode::CvtSI2FP>(xmm10s, r13);
buffer.Emit<OpCode::CvtSI2FP>(xmm10, r13);
// Between: xmm10 and r14
buffer.Emit<OpCode::Mov>(r14, -4, xmm10s);
buffer.Emit<OpCode::Mov>(r14, 4, xmm10);
buffer.Emit<OpCode::Mov>(xmm10s, r14, -4);
buffer.Emit<OpCode::Mov>(xmm10, r14, 4);
buffer.Emit<OpCode::CvtSI2FP, 4, true, 8, false>(xmm10s, r14, -4);
buffer.Emit<OpCode::CvtSI2FP, 8, true, 4, false>(xmm10, r14, 4);
buffer.Emit<OpCode::CvtFP2SI>(r14d, xmm10s);
buffer.Emit<OpCode::CvtFP2SI>(r14d, xmm10);
buffer.Emit<OpCode::CvtSI2FP>(xmm10s, r14d);
buffer.Emit<OpCode::CvtSI2FP>(xmm10, r14d);
buffer.Emit<OpCode::CvtFP2SI>(r14, xmm10s);
buffer.Emit<OpCode::CvtFP2SI>(r14, xmm10);
buffer.Emit<OpCode::CvtSI2FP>(xmm10s, r14);
buffer.Emit<OpCode::CvtSI2FP>(xmm10, r14);
// Between: xmm10 and r15
buffer.Emit<OpCode::Mov>(r15, -4, xmm10s);
buffer.Emit<OpCode::Mov>(r15, 4, xmm10);
buffer.Emit<OpCode::Mov>(xmm10s, r15, -4);
buffer.Emit<OpCode::Mov>(xmm10, r15, 4);
buffer.Emit<OpCode::CvtSI2FP, 4, true, 8, false>(xmm10s, r15, -4);
buffer.Emit<OpCode::CvtSI2FP, 8, true, 4, false>(xmm10, r15, 4);
buffer.Emit<OpCode::CvtFP2SI>(r15d, xmm10s);
buffer.Emit<OpCode::CvtFP2SI>(r15d, xmm10);
buffer.Emit<OpCode::CvtSI2FP>(xmm10s, r15d);
buffer.Emit<OpCode::CvtSI2FP>(xmm10, r15d);
buffer.Emit<OpCode::CvtFP2SI>(r15, xmm10s);
buffer.Emit<OpCode::CvtFP2SI>(r15, xmm10);
buffer.Emit<OpCode::CvtSI2FP>(xmm10s, r15);
buffer.Emit<OpCode::CvtSI2FP>(xmm10, r15);
// Between: xmm11 and rax
buffer.Emit<OpCode::Mov>(rax, -4, xmm11s);
buffer.Emit<OpCode::Mov>(rax, 4, xmm11);
buffer.Emit<OpCode::Mov>(xmm11s, rax, -4);
buffer.Emit<OpCode::Mov>(xmm11, rax, 4);
buffer.Emit<OpCode::CvtSI2FP, 4, true, 8, false>(xmm11s, rax, -4);
buffer.Emit<OpCode::CvtSI2FP, 8, true, 4, false>(xmm11, rax, 4);
buffer.Emit<OpCode::CvtFP2SI>(eax, xmm11s);
buffer.Emit<OpCode::CvtFP2SI>(eax, xmm11);
buffer.Emit<OpCode::CvtSI2FP>(xmm11s, eax);
buffer.Emit<OpCode::CvtSI2FP>(xmm11, eax);
buffer.Emit<OpCode::CvtFP2SI>(rax, xmm11s);
buffer.Emit<OpCode::CvtFP2SI>(rax, xmm11);
buffer.Emit<OpCode::CvtSI2FP>(xmm11s, rax);
buffer.Emit<OpCode::CvtSI2FP>(xmm11, rax);
// Between: xmm11 and rcx
buffer.Emit<OpCode::Mov>(rcx, -4, xmm11s);
buffer.Emit<OpCode::Mov>(rcx, 4, xmm11);
buffer.Emit<OpCode::Mov>(xmm11s, rcx, -4);
buffer.Emit<OpCode::Mov>(xmm11, rcx, 4);
buffer.Emit<OpCode::CvtSI2FP, 4, true, 8, false>(xmm11s, rcx, -4);
buffer.Emit<OpCode::CvtSI2FP, 8, true, 4, false>(xmm11, rcx, 4);
buffer.Emit<OpCode::CvtFP2SI>(ecx, xmm11s);
buffer.Emit<OpCode::CvtFP2SI>(ecx, xmm11);
buffer.Emit<OpCode::CvtSI2FP>(xmm11s, ecx);
buffer.Emit<OpCode::CvtSI2FP>(xmm11, ecx);
buffer.Emit<OpCode::CvtFP2SI>(rcx, xmm11s);
buffer.Emit<OpCode::CvtFP2SI>(rcx, xmm11);
buffer.Emit<OpCode::CvtSI2FP>(xmm11s, rcx);
buffer.Emit<OpCode::CvtSI2FP>(xmm11, rcx);
// Between: xmm11 and rdx
buffer.Emit<OpCode::Mov>(rdx, -4, xmm11s);
buffer.Emit<OpCode::Mov>(rdx, 4, xmm11);
buffer.Emit<OpCode::Mov>(xmm11s, rdx, -4);
buffer.Emit<OpCode::Mov>(xmm11, rdx, 4);
buffer.Emit<OpCode::CvtSI2FP, 4, true, 8, false>(xmm11s, rdx, -4);
buffer.Emit<OpCode::CvtSI2FP, 8, true, 4, false>(xmm11, rdx, 4);
buffer.Emit<OpCode::CvtFP2SI>(edx, xmm11s);
buffer.Emit<OpCode::CvtFP2SI>(edx, xmm11);
buffer.Emit<OpCode::CvtSI2FP>(xmm11s, edx);
buffer.Emit<OpCode::CvtSI2FP>(xmm11, edx);
buffer.Emit<OpCode::CvtFP2SI>(rdx, xmm11s);
buffer.Emit<OpCode::CvtFP2SI>(rdx, xmm11);
buffer.Emit<OpCode::CvtSI2FP>(xmm11s, rdx);
buffer.Emit<OpCode::CvtSI2FP>(xmm11, rdx);
// Between: xmm11 and rbx
buffer.Emit<OpCode::Mov>(rbx, -4, xmm11s);
buffer.Emit<OpCode::Mov>(rbx, 4, xmm11);
buffer.Emit<OpCode::Mov>(xmm11s, rbx, -4);
buffer.Emit<OpCode::Mov>(xmm11, rbx, 4);
buffer.Emit<OpCode::CvtSI2FP, 4, true, 8, false>(xmm11s, rbx, -4);
buffer.Emit<OpCode::CvtSI2FP, 8, true, 4, false>(xmm11, rbx, 4);
buffer.Emit<OpCode::CvtFP2SI>(ebx, xmm11s);
buffer.Emit<OpCode::CvtFP2SI>(ebx, xmm11);
buffer.Emit<OpCode::CvtSI2FP>(xmm11s, ebx);
buffer.Emit<OpCode::CvtSI2FP>(xmm11, ebx);
buffer.Emit<OpCode::CvtFP2SI>(rbx, xmm11s);
buffer.Emit<OpCode::CvtFP2SI>(rbx, xmm11);
buffer.Emit<OpCode::CvtSI2FP>(xmm11s, rbx);
buffer.Emit<OpCode::CvtSI2FP>(xmm11, rbx);
// Between: xmm11 and rsp
buffer.Emit<OpCode::Mov>(rsp, -4, xmm11s);
buffer.Emit<OpCode::Mov>(rsp, 4, xmm11);
buffer.Emit<OpCode::Mov>(xmm11s, rsp, -4);
buffer.Emit<OpCode::Mov>(xmm11, rsp, 4);
buffer.Emit<OpCode::CvtSI2FP, 4, true, 8, false>(xmm11s, rsp, -4);
buffer.Emit<OpCode::CvtSI2FP, 8, true, 4, false>(xmm11, rsp, 4);
buffer.Emit<OpCode::CvtFP2SI>(esp, xmm11s);
buffer.Emit<OpCode::CvtFP2SI>(esp, xmm11);
buffer.Emit<OpCode::CvtSI2FP>(xmm11s, esp);
buffer.Emit<OpCode::CvtSI2FP>(xmm11, esp);
buffer.Emit<OpCode::CvtFP2SI>(rsp, xmm11s);
buffer.Emit<OpCode::CvtFP2SI>(rsp, xmm11);
buffer.Emit<OpCode::CvtSI2FP>(xmm11s, rsp);
buffer.Emit<OpCode::CvtSI2FP>(xmm11, rsp);
// Between: xmm11 and rbp
buffer.Emit<OpCode::Mov>(rbp, -4, xmm11s);
buffer.Emit<OpCode::Mov>(rbp, 4, xmm11);
buffer.Emit<OpCode::Mov>(xmm11s, rbp, -4);
buffer.Emit<OpCode::Mov>(xmm11, rbp, 4);
buffer.Emit<OpCode::CvtSI2FP, 4, true, 8, false>(xmm11s, rbp, -4);
buffer.Emit<OpCode::CvtSI2FP, 8, true, 4, false>(xmm11, rbp, 4);
buffer.Emit<OpCode::CvtFP2SI>(ebp, xmm11s);
buffer.Emit<OpCode::CvtFP2SI>(ebp, xmm11);
buffer.Emit<OpCode::CvtSI2FP>(xmm11s, ebp);
buffer.Emit<OpCode::CvtSI2FP>(xmm11, ebp);
buffer.Emit<OpCode::CvtFP2SI>(rbp, xmm11s);
buffer.Emit<OpCode::CvtFP2SI>(rbp, xmm11);
buffer.Emit<OpCode::CvtSI2FP>(xmm11s, rbp);
buffer.Emit<OpCode::CvtSI2FP>(xmm11, rbp);
// Between: xmm11 and rsi
buffer.Emit<OpCode::Mov>(rsi, -4, xmm11s);
buffer.Emit<OpCode::Mov>(rsi, 4, xmm11);
buffer.Emit<OpCode::Mov>(xmm11s, rsi, -4);
buffer.Emit<OpCode::Mov>(xmm11, rsi, 4);
buffer.Emit<OpCode::CvtSI2FP, 4, true, 8, false>(xmm11s, rsi, -4);
buffer.Emit<OpCode::CvtSI2FP, 8, true, 4, false>(xmm11, rsi, 4);
buffer.Emit<OpCode::CvtFP2SI>(esi, xmm11s);
buffer.Emit<OpCode::CvtFP2SI>(esi, xmm11);
buffer.Emit<OpCode::CvtSI2FP>(xmm11s, esi);
buffer.Emit<OpCode::CvtSI2FP>(xmm11, esi);
buffer.Emit<OpCode::CvtFP2SI>(rsi, xmm11s);
buffer.Emit<OpCode::CvtFP2SI>(rsi, xmm11);
buffer.Emit<OpCode::CvtSI2FP>(xmm11s, rsi);
buffer.Emit<OpCode::CvtSI2FP>(xmm11, rsi);
// Between: xmm11 and rdi
buffer.Emit<OpCode::Mov>(rdi, -4, xmm11s);
buffer.Emit<OpCode::Mov>(rdi, 4, xmm11);
buffer.Emit<OpCode::Mov>(xmm11s, rdi, -4);
buffer.Emit<OpCode::Mov>(xmm11, rdi, 4);
buffer.Emit<OpCode::CvtSI2FP, 4, true, 8, false>(xmm11s, rdi, -4);
buffer.Emit<OpCode::CvtSI2FP, 8, true, 4, false>(xmm11, rdi, 4);
buffer.Emit<OpCode::CvtFP2SI>(edi, xmm11s);
buffer.Emit<OpCode::CvtFP2SI>(edi, xmm11);
buffer.Emit<OpCode::CvtSI2FP>(xmm11s, edi);
buffer.Emit<OpCode::CvtSI2FP>(xmm11, edi);
buffer.Emit<OpCode::CvtFP2SI>(rdi, xmm11s);
buffer.Emit<OpCode::CvtFP2SI>(rdi, xmm11);
buffer.Emit<OpCode::CvtSI2FP>(xmm11s, rdi);
buffer.Emit<OpCode::CvtSI2FP>(xmm11, rdi);
// Between: xmm11 and r8
buffer.Emit<OpCode::Mov>(r8, -4, xmm11s);
buffer.Emit<OpCode::Mov>(r8, 4, xmm11);
buffer.Emit<OpCode::Mov>(xmm11s, r8, -4);
buffer.Emit<OpCode::Mov>(xmm11, r8, 4);
buffer.Emit<OpCode::CvtSI2FP, 4, true, 8, false>(xmm11s, r8, -4);
buffer.Emit<OpCode::CvtSI2FP, 8, true, 4, false>(xmm11, r8, 4);
buffer.Emit<OpCode::CvtFP2SI>(r8d, xmm11s);
buffer.Emit<OpCode::CvtFP2SI>(r8d, xmm11);
buffer.Emit<OpCode::CvtSI2FP>(xmm11s, r8d);
buffer.Emit<OpCode::CvtSI2FP>(xmm11, r8d);
buffer.Emit<OpCode::CvtFP2SI>(r8, xmm11s);
buffer.Emit<OpCode::CvtFP2SI>(r8, xmm11);
buffer.Emit<OpCode::CvtSI2FP>(xmm11s, r8);
buffer.Emit<OpCode::CvtSI2FP>(xmm11, r8);
// Between: xmm11 and r9
buffer.Emit<OpCode::Mov>(r9, -4, xmm11s);
buffer.Emit<OpCode::Mov>(r9, 4, xmm11);
buffer.Emit<OpCode::Mov>(xmm11s, r9, -4);
buffer.Emit<OpCode::Mov>(xmm11, r9, 4);
buffer.Emit<OpCode::CvtSI2FP, 4, true, 8, false>(xmm11s, r9, -4);
buffer.Emit<OpCode::CvtSI2FP, 8, true, 4, false>(xmm11, r9, 4);
buffer.Emit<OpCode::CvtFP2SI>(r9d, xmm11s);
buffer.Emit<OpCode::CvtFP2SI>(r9d, xmm11);
buffer.Emit<OpCode::CvtSI2FP>(xmm11s, r9d);
buffer.Emit<OpCode::CvtSI2FP>(xmm11, r9d);
buffer.Emit<OpCode::CvtFP2SI>(r9, xmm11s);
buffer.Emit<OpCode::CvtFP2SI>(r9, xmm11);
buffer.Emit<OpCode::CvtSI2FP>(xmm11s, r9);
buffer.Emit<OpCode::CvtSI2FP>(xmm11, r9);
// Between: xmm11 and r10
buffer.Emit<OpCode::Mov>(r10, -4, xmm11s);
buffer.Emit<OpCode::Mov>(r10, 4, xmm11);
buffer.Emit<OpCode::Mov>(xmm11s, r10, -4);
buffer.Emit<OpCode::Mov>(xmm11, r10, 4);
buffer.Emit<OpCode::CvtSI2FP, 4, true, 8, false>(xmm11s, r10, -4);
buffer.Emit<OpCode::CvtSI2FP, 8, true, 4, false>(xmm11, r10, 4);
buffer.Emit<OpCode::CvtFP2SI>(r10d, xmm11s);
buffer.Emit<OpCode::CvtFP2SI>(r10d, xmm11);
buffer.Emit<OpCode::CvtSI2FP>(xmm11s, r10d);
buffer.Emit<OpCode::CvtSI2FP>(xmm11, r10d);
buffer.Emit<OpCode::CvtFP2SI>(r10, xmm11s);
buffer.Emit<OpCode::CvtFP2SI>(r10, xmm11);
buffer.Emit<OpCode::CvtSI2FP>(xmm11s, r10);
buffer.Emit<OpCode::CvtSI2FP>(xmm11, r10);
// Between: xmm11 and r11
buffer.Emit<OpCode::Mov>(r11, -4, xmm11s);
buffer.Emit<OpCode::Mov>(r11, 4, xmm11);
buffer.Emit<OpCode::Mov>(xmm11s, r11, -4);
buffer.Emit<OpCode::Mov>(xmm11, r11, 4);
buffer.Emit<OpCode::CvtSI2FP, 4, true, 8, false>(xmm11s, r11, -4);
buffer.Emit<OpCode::CvtSI2FP, 8, true, 4, false>(xmm11, r11, 4);
buffer.Emit<OpCode::CvtFP2SI>(r11d, xmm11s);
buffer.Emit<OpCode::CvtFP2SI>(r11d, xmm11);
buffer.Emit<OpCode::CvtSI2FP>(xmm11s, r11d);
buffer.Emit<OpCode::CvtSI2FP>(xmm11, r11d);
buffer.Emit<OpCode::CvtFP2SI>(r11, xmm11s);
buffer.Emit<OpCode::CvtFP2SI>(r11, xmm11);
buffer.Emit<OpCode::CvtSI2FP>(xmm11s, r11);
buffer.Emit<OpCode::CvtSI2FP>(xmm11, r11);
// Between: xmm11 and r12
buffer.Emit<OpCode::Mov>(r12, -4, xmm11s);
buffer.Emit<OpCode::Mov>(r12, 4, xmm11);
buffer.Emit<OpCode::Mov>(xmm11s, r12, -4);
buffer.Emit<OpCode::Mov>(xmm11, r12, 4);
buffer.Emit<OpCode::CvtSI2FP, 4, true, 8, false>(xmm11s, r12, -4);
buffer.Emit<OpCode::CvtSI2FP, 8, true, 4, false>(xmm11, r12, 4);
buffer.Emit<OpCode::CvtFP2SI>(r12d, xmm11s);
buffer.Emit<OpCode::CvtFP2SI>(r12d, xmm11);
buffer.Emit<OpCode::CvtSI2FP>(xmm11s, r12d);
buffer.Emit<OpCode::CvtSI2FP>(xmm11, r12d);
buffer.Emit<OpCode::CvtFP2SI>(r12, xmm11s);
buffer.Emit<OpCode::CvtFP2SI>(r12, xmm11);
buffer.Emit<OpCode::CvtSI2FP>(xmm11s, r12);
buffer.Emit<OpCode::CvtSI2FP>(xmm11, r12);
// Between: xmm11 and r13
buffer.Emit<OpCode::Mov>(r13, -4, xmm11s);
buffer.Emit<OpCode::Mov>(r13, 4, xmm11);
buffer.Emit<OpCode::Mov>(xmm11s, r13, -4);
buffer.Emit<OpCode::Mov>(xmm11, r13, 4);
buffer.Emit<OpCode::CvtSI2FP, 4, true, 8, false>(xmm11s, r13, -4);
buffer.Emit<OpCode::CvtSI2FP, 8, true, 4, false>(xmm11, r13, 4);
buffer.Emit<OpCode::CvtFP2SI>(r13d, xmm11s);
buffer.Emit<OpCode::CvtFP2SI>(r13d, xmm11);
buffer.Emit<OpCode::CvtSI2FP>(xmm11s, r13d);
buffer.Emit<OpCode::CvtSI2FP>(xmm11, r13d);
buffer.Emit<OpCode::CvtFP2SI>(r13, xmm11s);
buffer.Emit<OpCode::CvtFP2SI>(r13, xmm11);
buffer.Emit<OpCode::CvtSI2FP>(xmm11s, r13);
buffer.Emit<OpCode::CvtSI2FP>(xmm11, r13);
// Between: xmm11 and r14
buffer.Emit<OpCode::Mov>(r14, -4, xmm11s);
buffer.Emit<OpCode::Mov>(r14, 4, xmm11);
buffer.Emit<OpCode::Mov>(xmm11s, r14, -4);
buffer.Emit<OpCode::Mov>(xmm11, r14, 4);
buffer.Emit<OpCode::CvtSI2FP, 4, true, 8, false>(xmm11s, r14, -4);
buffer.Emit<OpCode::CvtSI2FP, 8, true, 4, false>(xmm11, r14, 4);
buffer.Emit<OpCode::CvtFP2SI>(r14d, xmm11s);
buffer.Emit<OpCode::CvtFP2SI>(r14d, xmm11);
buffer.Emit<OpCode::CvtSI2FP>(xmm11s, r14d);
buffer.Emit<OpCode::CvtSI2FP>(xmm11, r14d);
buffer.Emit<OpCode::CvtFP2SI>(r14, xmm11s);
buffer.Emit<OpCode::CvtFP2SI>(r14, xmm11);
buffer.Emit<OpCode::CvtSI2FP>(xmm11s, r14);
buffer.Emit<OpCode::CvtSI2FP>(xmm11, r14);
// Between: xmm11 and r15
buffer.Emit<OpCode::Mov>(r15, -4, xmm11s);
buffer.Emit<OpCode::Mov>(r15, 4, xmm11);
buffer.Emit<OpCode::Mov>(xmm11s, r15, -4);
buffer.Emit<OpCode::Mov>(xmm11, r15, 4);
buffer.Emit<OpCode::CvtSI2FP, 4, true, 8, false>(xmm11s, r15, -4);
buffer.Emit<OpCode::CvtSI2FP, 8, true, 4, false>(xmm11, r15, 4);
buffer.Emit<OpCode::CvtFP2SI>(r15d, xmm11s);
buffer.Emit<OpCode::CvtFP2SI>(r15d, xmm11);
buffer.Emit<OpCode::CvtSI2FP>(xmm11s, r15d);
buffer.Emit<OpCode::CvtSI2FP>(xmm11, r15d);
buffer.Emit<OpCode::CvtFP2SI>(r15, xmm11s);
buffer.Emit<OpCode::CvtFP2SI>(r15, xmm11);
buffer.Emit<OpCode::CvtSI2FP>(xmm11s, r15);
buffer.Emit<OpCode::CvtSI2FP>(xmm11, r15);
// Between: xmm12 and rax
buffer.Emit<OpCode::Mov>(rax, -4, xmm12s);
buffer.Emit<OpCode::Mov>(rax, 4, xmm12);
buffer.Emit<OpCode::Mov>(xmm12s, rax, -4);
buffer.Emit<OpCode::Mov>(xmm12, rax, 4);
buffer.Emit<OpCode::CvtSI2FP, 4, true, 8, false>(xmm12s, rax, -4);
buffer.Emit<OpCode::CvtSI2FP, 8, true, 4, false>(xmm12, rax, 4);
buffer.Emit<OpCode::CvtFP2SI>(eax, xmm12s);
buffer.Emit<OpCode::CvtFP2SI>(eax, xmm12);
buffer.Emit<OpCode::CvtSI2FP>(xmm12s, eax);
buffer.Emit<OpCode::CvtSI2FP>(xmm12, eax);
buffer.Emit<OpCode::CvtFP2SI>(rax, xmm12s);
buffer.Emit<OpCode::CvtFP2SI>(rax, xmm12);
buffer.Emit<OpCode::CvtSI2FP>(xmm12s, rax);
buffer.Emit<OpCode::CvtSI2FP>(xmm12, rax);
// Between: xmm12 and rcx
buffer.Emit<OpCode::Mov>(rcx, -4, xmm12s);
buffer.Emit<OpCode::Mov>(rcx, 4, xmm12);
buffer.Emit<OpCode::Mov>(xmm12s, rcx, -4);
buffer.Emit<OpCode::Mov>(xmm12, rcx, 4);
buffer.Emit<OpCode::CvtSI2FP, 4, true, 8, false>(xmm12s, rcx, -4);
buffer.Emit<OpCode::CvtSI2FP, 8, true, 4, false>(xmm12, rcx, 4);
buffer.Emit<OpCode::CvtFP2SI>(ecx, xmm12s);
buffer.Emit<OpCode::CvtFP2SI>(ecx, xmm12);
buffer.Emit<OpCode::CvtSI2FP>(xmm12s, ecx);
buffer.Emit<OpCode::CvtSI2FP>(xmm12, ecx);
buffer.Emit<OpCode::CvtFP2SI>(rcx, xmm12s);
buffer.Emit<OpCode::CvtFP2SI>(rcx, xmm12);
buffer.Emit<OpCode::CvtSI2FP>(xmm12s, rcx);
buffer.Emit<OpCode::CvtSI2FP>(xmm12, rcx);
// Between: xmm12 and rdx
buffer.Emit<OpCode::Mov>(rdx, -4, xmm12s);
buffer.Emit<OpCode::Mov>(rdx, 4, xmm12);
buffer.Emit<OpCode::Mov>(xmm12s, rdx, -4);
buffer.Emit<OpCode::Mov>(xmm12, rdx, 4);
buffer.Emit<OpCode::CvtSI2FP, 4, true, 8, false>(xmm12s, rdx, -4);
buffer.Emit<OpCode::CvtSI2FP, 8, true, 4, false>(xmm12, rdx, 4);
buffer.Emit<OpCode::CvtFP2SI>(edx, xmm12s);
buffer.Emit<OpCode::CvtFP2SI>(edx, xmm12);
buffer.Emit<OpCode::CvtSI2FP>(xmm12s, edx);
buffer.Emit<OpCode::CvtSI2FP>(xmm12, edx);
buffer.Emit<OpCode::CvtFP2SI>(rdx, xmm12s);
buffer.Emit<OpCode::CvtFP2SI>(rdx, xmm12);
buffer.Emit<OpCode::CvtSI2FP>(xmm12s, rdx);
buffer.Emit<OpCode::CvtSI2FP>(xmm12, rdx);
// Between: xmm12 and rbx
buffer.Emit<OpCode::Mov>(rbx, -4, xmm12s);
buffer.Emit<OpCode::Mov>(rbx, 4, xmm12);
buffer.Emit<OpCode::Mov>(xmm12s, rbx, -4);
buffer.Emit<OpCode::Mov>(xmm12, rbx, 4);
buffer.Emit<OpCode::CvtSI2FP, 4, true, 8, false>(xmm12s, rbx, -4);
buffer.Emit<OpCode::CvtSI2FP, 8, true, 4, false>(xmm12, rbx, 4);
buffer.Emit<OpCode::CvtFP2SI>(ebx, xmm12s);
buffer.Emit<OpCode::CvtFP2SI>(ebx, xmm12);
buffer.Emit<OpCode::CvtSI2FP>(xmm12s, ebx);
buffer.Emit<OpCode::CvtSI2FP>(xmm12, ebx);
buffer.Emit<OpCode::CvtFP2SI>(rbx, xmm12s);
buffer.Emit<OpCode::CvtFP2SI>(rbx, xmm12);
buffer.Emit<OpCode::CvtSI2FP>(xmm12s, rbx);
buffer.Emit<OpCode::CvtSI2FP>(xmm12, rbx);
// Between: xmm12 and rsp
buffer.Emit<OpCode::Mov>(rsp, -4, xmm12s);
buffer.Emit<OpCode::Mov>(rsp, 4, xmm12);
buffer.Emit<OpCode::Mov>(xmm12s, rsp, -4);
buffer.Emit<OpCode::Mov>(xmm12, rsp, 4);
buffer.Emit<OpCode::CvtSI2FP, 4, true, 8, false>(xmm12s, rsp, -4);
buffer.Emit<OpCode::CvtSI2FP, 8, true, 4, false>(xmm12, rsp, 4);
buffer.Emit<OpCode::CvtFP2SI>(esp, xmm12s);
buffer.Emit<OpCode::CvtFP2SI>(esp, xmm12);
buffer.Emit<OpCode::CvtSI2FP>(xmm12s, esp);
buffer.Emit<OpCode::CvtSI2FP>(xmm12, esp);
buffer.Emit<OpCode::CvtFP2SI>(rsp, xmm12s);
buffer.Emit<OpCode::CvtFP2SI>(rsp, xmm12);
buffer.Emit<OpCode::CvtSI2FP>(xmm12s, rsp);
buffer.Emit<OpCode::CvtSI2FP>(xmm12, rsp);
// Between: xmm12 and rbp
buffer.Emit<OpCode::Mov>(rbp, -4, xmm12s);
buffer.Emit<OpCode::Mov>(rbp, 4, xmm12);
buffer.Emit<OpCode::Mov>(xmm12s, rbp, -4);
buffer.Emit<OpCode::Mov>(xmm12, rbp, 4);
buffer.Emit<OpCode::CvtSI2FP, 4, true, 8, false>(xmm12s, rbp, -4);
buffer.Emit<OpCode::CvtSI2FP, 8, true, 4, false>(xmm12, rbp, 4);
buffer.Emit<OpCode::CvtFP2SI>(ebp, xmm12s);
buffer.Emit<OpCode::CvtFP2SI>(ebp, xmm12);
buffer.Emit<OpCode::CvtSI2FP>(xmm12s, ebp);
buffer.Emit<OpCode::CvtSI2FP>(xmm12, ebp);
buffer.Emit<OpCode::CvtFP2SI>(rbp, xmm12s);
buffer.Emit<OpCode::CvtFP2SI>(rbp, xmm12);
buffer.Emit<OpCode::CvtSI2FP>(xmm12s, rbp);
buffer.Emit<OpCode::CvtSI2FP>(xmm12, rbp);
// Between: xmm12 and rsi
buffer.Emit<OpCode::Mov>(rsi, -4, xmm12s);
buffer.Emit<OpCode::Mov>(rsi, 4, xmm12);
buffer.Emit<OpCode::Mov>(xmm12s, rsi, -4);
buffer.Emit<OpCode::Mov>(xmm12, rsi, 4);
buffer.Emit<OpCode::CvtSI2FP, 4, true, 8, false>(xmm12s, rsi, -4);
buffer.Emit<OpCode::CvtSI2FP, 8, true, 4, false>(xmm12, rsi, 4);
buffer.Emit<OpCode::CvtFP2SI>(esi, xmm12s);
buffer.Emit<OpCode::CvtFP2SI>(esi, xmm12);
buffer.Emit<OpCode::CvtSI2FP>(xmm12s, esi);
buffer.Emit<OpCode::CvtSI2FP>(xmm12, esi);
buffer.Emit<OpCode::CvtFP2SI>(rsi, xmm12s);
buffer.Emit<OpCode::CvtFP2SI>(rsi, xmm12);
buffer.Emit<OpCode::CvtSI2FP>(xmm12s, rsi);
buffer.Emit<OpCode::CvtSI2FP>(xmm12, rsi);
// Between: xmm12 and rdi
buffer.Emit<OpCode::Mov>(rdi, -4, xmm12s);
buffer.Emit<OpCode::Mov>(rdi, 4, xmm12);
buffer.Emit<OpCode::Mov>(xmm12s, rdi, -4);
buffer.Emit<OpCode::Mov>(xmm12, rdi, 4);
buffer.Emit<OpCode::CvtSI2FP, 4, true, 8, false>(xmm12s, rdi, -4);
buffer.Emit<OpCode::CvtSI2FP, 8, true, 4, false>(xmm12, rdi, 4);
buffer.Emit<OpCode::CvtFP2SI>(edi, xmm12s);
buffer.Emit<OpCode::CvtFP2SI>(edi, xmm12);
buffer.Emit<OpCode::CvtSI2FP>(xmm12s, edi);
buffer.Emit<OpCode::CvtSI2FP>(xmm12, edi);
buffer.Emit<OpCode::CvtFP2SI>(rdi, xmm12s);
buffer.Emit<OpCode::CvtFP2SI>(rdi, xmm12);
buffer.Emit<OpCode::CvtSI2FP>(xmm12s, rdi);
buffer.Emit<OpCode::CvtSI2FP>(xmm12, rdi);
// Between: xmm12 and r8
buffer.Emit<OpCode::Mov>(r8, -4, xmm12s);
buffer.Emit<OpCode::Mov>(r8, 4, xmm12);
buffer.Emit<OpCode::Mov>(xmm12s, r8, -4);
buffer.Emit<OpCode::Mov>(xmm12, r8, 4);
buffer.Emit<OpCode::CvtSI2FP, 4, true, 8, false>(xmm12s, r8, -4);
buffer.Emit<OpCode::CvtSI2FP, 8, true, 4, false>(xmm12, r8, 4);
buffer.Emit<OpCode::CvtFP2SI>(r8d, xmm12s);
buffer.Emit<OpCode::CvtFP2SI>(r8d, xmm12);
buffer.Emit<OpCode::CvtSI2FP>(xmm12s, r8d);
buffer.Emit<OpCode::CvtSI2FP>(xmm12, r8d);
buffer.Emit<OpCode::CvtFP2SI>(r8, xmm12s);
buffer.Emit<OpCode::CvtFP2SI>(r8, xmm12);
buffer.Emit<OpCode::CvtSI2FP>(xmm12s, r8);
buffer.Emit<OpCode::CvtSI2FP>(xmm12, r8);
// Between: xmm12 and r9
buffer.Emit<OpCode::Mov>(r9, -4, xmm12s);
buffer.Emit<OpCode::Mov>(r9, 4, xmm12);
buffer.Emit<OpCode::Mov>(xmm12s, r9, -4);
buffer.Emit<OpCode::Mov>(xmm12, r9, 4);
buffer.Emit<OpCode::CvtSI2FP, 4, true, 8, false>(xmm12s, r9, -4);
buffer.Emit<OpCode::CvtSI2FP, 8, true, 4, false>(xmm12, r9, 4);
buffer.Emit<OpCode::CvtFP2SI>(r9d, xmm12s);
buffer.Emit<OpCode::CvtFP2SI>(r9d, xmm12);
buffer.Emit<OpCode::CvtSI2FP>(xmm12s, r9d);
buffer.Emit<OpCode::CvtSI2FP>(xmm12, r9d);
buffer.Emit<OpCode::CvtFP2SI>(r9, xmm12s);
buffer.Emit<OpCode::CvtFP2SI>(r9, xmm12);
buffer.Emit<OpCode::CvtSI2FP>(xmm12s, r9);
buffer.Emit<OpCode::CvtSI2FP>(xmm12, r9);
// Between: xmm12 and r10
buffer.Emit<OpCode::Mov>(r10, -4, xmm12s);
buffer.Emit<OpCode::Mov>(r10, 4, xmm12);
buffer.Emit<OpCode::Mov>(xmm12s, r10, -4);
buffer.Emit<OpCode::Mov>(xmm12, r10, 4);
buffer.Emit<OpCode::CvtSI2FP, 4, true, 8, false>(xmm12s, r10, -4);
buffer.Emit<OpCode::CvtSI2FP, 8, true, 4, false>(xmm12, r10, 4);
buffer.Emit<OpCode::CvtFP2SI>(r10d, xmm12s);
buffer.Emit<OpCode::CvtFP2SI>(r10d, xmm12);
buffer.Emit<OpCode::CvtSI2FP>(xmm12s, r10d);
buffer.Emit<OpCode::CvtSI2FP>(xmm12, r10d);
buffer.Emit<OpCode::CvtFP2SI>(r10, xmm12s);
buffer.Emit<OpCode::CvtFP2SI>(r10, xmm12);
buffer.Emit<OpCode::CvtSI2FP>(xmm12s, r10);
buffer.Emit<OpCode::CvtSI2FP>(xmm12, r10);
// Between: xmm12 and r11
buffer.Emit<OpCode::Mov>(r11, -4, xmm12s);
buffer.Emit<OpCode::Mov>(r11, 4, xmm12);
buffer.Emit<OpCode::Mov>(xmm12s, r11, -4);
buffer.Emit<OpCode::Mov>(xmm12, r11, 4);
buffer.Emit<OpCode::CvtSI2FP, 4, true, 8, false>(xmm12s, r11, -4);
buffer.Emit<OpCode::CvtSI2FP, 8, true, 4, false>(xmm12, r11, 4);
buffer.Emit<OpCode::CvtFP2SI>(r11d, xmm12s);
buffer.Emit<OpCode::CvtFP2SI>(r11d, xmm12);
buffer.Emit<OpCode::CvtSI2FP>(xmm12s, r11d);
buffer.Emit<OpCode::CvtSI2FP>(xmm12, r11d);
buffer.Emit<OpCode::CvtFP2SI>(r11, xmm12s);
buffer.Emit<OpCode::CvtFP2SI>(r11, xmm12);
buffer.Emit<OpCode::CvtSI2FP>(xmm12s, r11);
buffer.Emit<OpCode::CvtSI2FP>(xmm12, r11);
// Between: xmm12 and r12
buffer.Emit<OpCode::Mov>(r12, -4, xmm12s);
buffer.Emit<OpCode::Mov>(r12, 4, xmm12);
buffer.Emit<OpCode::Mov>(xmm12s, r12, -4);
buffer.Emit<OpCode::Mov>(xmm12, r12, 4);
buffer.Emit<OpCode::CvtSI2FP, 4, true, 8, false>(xmm12s, r12, -4);
buffer.Emit<OpCode::CvtSI2FP, 8, true, 4, false>(xmm12, r12, 4);
buffer.Emit<OpCode::CvtFP2SI>(r12d, xmm12s);
buffer.Emit<OpCode::CvtFP2SI>(r12d, xmm12);
buffer.Emit<OpCode::CvtSI2FP>(xmm12s, r12d);
buffer.Emit<OpCode::CvtSI2FP>(xmm12, r12d);
buffer.Emit<OpCode::CvtFP2SI>(r12, xmm12s);
buffer.Emit<OpCode::CvtFP2SI>(r12, xmm12);
buffer.Emit<OpCode::CvtSI2FP>(xmm12s, r12);
buffer.Emit<OpCode::CvtSI2FP>(xmm12, r12);
// Between: xmm12 and r13
buffer.Emit<OpCode::Mov>(r13, -4, xmm12s);
buffer.Emit<OpCode::Mov>(r13, 4, xmm12);
buffer.Emit<OpCode::Mov>(xmm12s, r13, -4);
buffer.Emit<OpCode::Mov>(xmm12, r13, 4);
buffer.Emit<OpCode::CvtSI2FP, 4, true, 8, false>(xmm12s, r13, -4);
buffer.Emit<OpCode::CvtSI2FP, 8, true, 4, false>(xmm12, r13, 4);
buffer.Emit<OpCode::CvtFP2SI>(r13d, xmm12s);
buffer.Emit<OpCode::CvtFP2SI>(r13d, xmm12);
buffer.Emit<OpCode::CvtSI2FP>(xmm12s, r13d);
buffer.Emit<OpCode::CvtSI2FP>(xmm12, r13d);
buffer.Emit<OpCode::CvtFP2SI>(r13, xmm12s);
buffer.Emit<OpCode::CvtFP2SI>(r13, xmm12);
buffer.Emit<OpCode::CvtSI2FP>(xmm12s, r13);
buffer.Emit<OpCode::CvtSI2FP>(xmm12, r13);
// Between: xmm12 and r14
buffer.Emit<OpCode::Mov>(r14, -4, xmm12s);
buffer.Emit<OpCode::Mov>(r14, 4, xmm12);
buffer.Emit<OpCode::Mov>(xmm12s, r14, -4);
buffer.Emit<OpCode::Mov>(xmm12, r14, 4);
buffer.Emit<OpCode::CvtSI2FP, 4, true, 8, false>(xmm12s, r14, -4);
buffer.Emit<OpCode::CvtSI2FP, 8, true, 4, false>(xmm12, r14, 4);
buffer.Emit<OpCode::CvtFP2SI>(r14d, xmm12s);
buffer.Emit<OpCode::CvtFP2SI>(r14d, xmm12);
buffer.Emit<OpCode::CvtSI2FP>(xmm12s, r14d);
buffer.Emit<OpCode::CvtSI2FP>(xmm12, r14d);
buffer.Emit<OpCode::CvtFP2SI>(r14, xmm12s);
buffer.Emit<OpCode::CvtFP2SI>(r14, xmm12);
buffer.Emit<OpCode::CvtSI2FP>(xmm12s, r14);
buffer.Emit<OpCode::CvtSI2FP>(xmm12, r14);
// Between: xmm12 and r15
buffer.Emit<OpCode::Mov>(r15, -4, xmm12s);
buffer.Emit<OpCode::Mov>(r15, 4, xmm12);
buffer.Emit<OpCode::Mov>(xmm12s, r15, -4);
buffer.Emit<OpCode::Mov>(xmm12, r15, 4);
buffer.Emit<OpCode::CvtSI2FP, 4, true, 8, false>(xmm12s, r15, -4);
buffer.Emit<OpCode::CvtSI2FP, 8, true, 4, false>(xmm12, r15, 4);
buffer.Emit<OpCode::CvtFP2SI>(r15d, xmm12s);
buffer.Emit<OpCode::CvtFP2SI>(r15d, xmm12);
buffer.Emit<OpCode::CvtSI2FP>(xmm12s, r15d);
buffer.Emit<OpCode::CvtSI2FP>(xmm12, r15d);
buffer.Emit<OpCode::CvtFP2SI>(r15, xmm12s);
buffer.Emit<OpCode::CvtFP2SI>(r15, xmm12);
buffer.Emit<OpCode::CvtSI2FP>(xmm12s, r15);
buffer.Emit<OpCode::CvtSI2FP>(xmm12, r15);
// Between: xmm13 and rax
buffer.Emit<OpCode::Mov>(rax, -4, xmm13s);
buffer.Emit<OpCode::Mov>(rax, 4, xmm13);
buffer.Emit<OpCode::Mov>(xmm13s, rax, -4);
buffer.Emit<OpCode::Mov>(xmm13, rax, 4);
buffer.Emit<OpCode::CvtSI2FP, 4, true, 8, false>(xmm13s, rax, -4);
buffer.Emit<OpCode::CvtSI2FP, 8, true, 4, false>(xmm13, rax, 4);
buffer.Emit<OpCode::CvtFP2SI>(eax, xmm13s);
buffer.Emit<OpCode::CvtFP2SI>(eax, xmm13);
buffer.Emit<OpCode::CvtSI2FP>(xmm13s, eax);
buffer.Emit<OpCode::CvtSI2FP>(xmm13, eax);
buffer.Emit<OpCode::CvtFP2SI>(rax, xmm13s);
buffer.Emit<OpCode::CvtFP2SI>(rax, xmm13);
buffer.Emit<OpCode::CvtSI2FP>(xmm13s, rax);
buffer.Emit<OpCode::CvtSI2FP>(xmm13, rax);
// Between: xmm13 and rcx
buffer.Emit<OpCode::Mov>(rcx, -4, xmm13s);
buffer.Emit<OpCode::Mov>(rcx, 4, xmm13);
buffer.Emit<OpCode::Mov>(xmm13s, rcx, -4);
buffer.Emit<OpCode::Mov>(xmm13, rcx, 4);
buffer.Emit<OpCode::CvtSI2FP, 4, true, 8, false>(xmm13s, rcx, -4);
buffer.Emit<OpCode::CvtSI2FP, 8, true, 4, false>(xmm13, rcx, 4);
buffer.Emit<OpCode::CvtFP2SI>(ecx, xmm13s);
buffer.Emit<OpCode::CvtFP2SI>(ecx, xmm13);
buffer.Emit<OpCode::CvtSI2FP>(xmm13s, ecx);
buffer.Emit<OpCode::CvtSI2FP>(xmm13, ecx);
buffer.Emit<OpCode::CvtFP2SI>(rcx, xmm13s);
buffer.Emit<OpCode::CvtFP2SI>(rcx, xmm13);
buffer.Emit<OpCode::CvtSI2FP>(xmm13s, rcx);
buffer.Emit<OpCode::CvtSI2FP>(xmm13, rcx);
// Between: xmm13 and rdx
buffer.Emit<OpCode::Mov>(rdx, -4, xmm13s);
buffer.Emit<OpCode::Mov>(rdx, 4, xmm13);
buffer.Emit<OpCode::Mov>(xmm13s, rdx, -4);
buffer.Emit<OpCode::Mov>(xmm13, rdx, 4);
buffer.Emit<OpCode::CvtSI2FP, 4, true, 8, false>(xmm13s, rdx, -4);
buffer.Emit<OpCode::CvtSI2FP, 8, true, 4, false>(xmm13, rdx, 4);
buffer.Emit<OpCode::CvtFP2SI>(edx, xmm13s);
buffer.Emit<OpCode::CvtFP2SI>(edx, xmm13);
buffer.Emit<OpCode::CvtSI2FP>(xmm13s, edx);
buffer.Emit<OpCode::CvtSI2FP>(xmm13, edx);
buffer.Emit<OpCode::CvtFP2SI>(rdx, xmm13s);
buffer.Emit<OpCode::CvtFP2SI>(rdx, xmm13);
buffer.Emit<OpCode::CvtSI2FP>(xmm13s, rdx);
buffer.Emit<OpCode::CvtSI2FP>(xmm13, rdx);
// Between: xmm13 and rbx
buffer.Emit<OpCode::Mov>(rbx, -4, xmm13s);
buffer.Emit<OpCode::Mov>(rbx, 4, xmm13);
buffer.Emit<OpCode::Mov>(xmm13s, rbx, -4);
buffer.Emit<OpCode::Mov>(xmm13, rbx, 4);
buffer.Emit<OpCode::CvtSI2FP, 4, true, 8, false>(xmm13s, rbx, -4);
buffer.Emit<OpCode::CvtSI2FP, 8, true, 4, false>(xmm13, rbx, 4);
buffer.Emit<OpCode::CvtFP2SI>(ebx, xmm13s);
buffer.Emit<OpCode::CvtFP2SI>(ebx, xmm13);
buffer.Emit<OpCode::CvtSI2FP>(xmm13s, ebx);
buffer.Emit<OpCode::CvtSI2FP>(xmm13, ebx);
buffer.Emit<OpCode::CvtFP2SI>(rbx, xmm13s);
buffer.Emit<OpCode::CvtFP2SI>(rbx, xmm13);
buffer.Emit<OpCode::CvtSI2FP>(xmm13s, rbx);
buffer.Emit<OpCode::CvtSI2FP>(xmm13, rbx);
// Between: xmm13 and rsp
buffer.Emit<OpCode::Mov>(rsp, -4, xmm13s);
buffer.Emit<OpCode::Mov>(rsp, 4, xmm13);
buffer.Emit<OpCode::Mov>(xmm13s, rsp, -4);
buffer.Emit<OpCode::Mov>(xmm13, rsp, 4);
buffer.Emit<OpCode::CvtSI2FP, 4, true, 8, false>(xmm13s, rsp, -4);
buffer.Emit<OpCode::CvtSI2FP, 8, true, 4, false>(xmm13, rsp, 4);
buffer.Emit<OpCode::CvtFP2SI>(esp, xmm13s);
buffer.Emit<OpCode::CvtFP2SI>(esp, xmm13);
buffer.Emit<OpCode::CvtSI2FP>(xmm13s, esp);
buffer.Emit<OpCode::CvtSI2FP>(xmm13, esp);
buffer.Emit<OpCode::CvtFP2SI>(rsp, xmm13s);
buffer.Emit<OpCode::CvtFP2SI>(rsp, xmm13);
buffer.Emit<OpCode::CvtSI2FP>(xmm13s, rsp);
buffer.Emit<OpCode::CvtSI2FP>(xmm13, rsp);
// Between: xmm13 and rbp
buffer.Emit<OpCode::Mov>(rbp, -4, xmm13s);
buffer.Emit<OpCode::Mov>(rbp, 4, xmm13);
buffer.Emit<OpCode::Mov>(xmm13s, rbp, -4);
buffer.Emit<OpCode::Mov>(xmm13, rbp, 4);
buffer.Emit<OpCode::CvtSI2FP, 4, true, 8, false>(xmm13s, rbp, -4);
buffer.Emit<OpCode::CvtSI2FP, 8, true, 4, false>(xmm13, rbp, 4);
buffer.Emit<OpCode::CvtFP2SI>(ebp, xmm13s);
buffer.Emit<OpCode::CvtFP2SI>(ebp, xmm13);
buffer.Emit<OpCode::CvtSI2FP>(xmm13s, ebp);
buffer.Emit<OpCode::CvtSI2FP>(xmm13, ebp);
buffer.Emit<OpCode::CvtFP2SI>(rbp, xmm13s);
buffer.Emit<OpCode::CvtFP2SI>(rbp, xmm13);
buffer.Emit<OpCode::CvtSI2FP>(xmm13s, rbp);
buffer.Emit<OpCode::CvtSI2FP>(xmm13, rbp);
// Between: xmm13 and rsi
buffer.Emit<OpCode::Mov>(rsi, -4, xmm13s);
buffer.Emit<OpCode::Mov>(rsi, 4, xmm13);
buffer.Emit<OpCode::Mov>(xmm13s, rsi, -4);
buffer.Emit<OpCode::Mov>(xmm13, rsi, 4);
buffer.Emit<OpCode::CvtSI2FP, 4, true, 8, false>(xmm13s, rsi, -4);
buffer.Emit<OpCode::CvtSI2FP, 8, true, 4, false>(xmm13, rsi, 4);
buffer.Emit<OpCode::CvtFP2SI>(esi, xmm13s);
buffer.Emit<OpCode::CvtFP2SI>(esi, xmm13);
buffer.Emit<OpCode::CvtSI2FP>(xmm13s, esi);
buffer.Emit<OpCode::CvtSI2FP>(xmm13, esi);
buffer.Emit<OpCode::CvtFP2SI>(rsi, xmm13s);
buffer.Emit<OpCode::CvtFP2SI>(rsi, xmm13);
buffer.Emit<OpCode::CvtSI2FP>(xmm13s, rsi);
buffer.Emit<OpCode::CvtSI2FP>(xmm13, rsi);
// Between: xmm13 and rdi
buffer.Emit<OpCode::Mov>(rdi, -4, xmm13s);
buffer.Emit<OpCode::Mov>(rdi, 4, xmm13);
buffer.Emit<OpCode::Mov>(xmm13s, rdi, -4);
buffer.Emit<OpCode::Mov>(xmm13, rdi, 4);
buffer.Emit<OpCode::CvtSI2FP, 4, true, 8, false>(xmm13s, rdi, -4);
buffer.Emit<OpCode::CvtSI2FP, 8, true, 4, false>(xmm13, rdi, 4);
buffer.Emit<OpCode::CvtFP2SI>(edi, xmm13s);
buffer.Emit<OpCode::CvtFP2SI>(edi, xmm13);
buffer.Emit<OpCode::CvtSI2FP>(xmm13s, edi);
buffer.Emit<OpCode::CvtSI2FP>(xmm13, edi);
buffer.Emit<OpCode::CvtFP2SI>(rdi, xmm13s);
buffer.Emit<OpCode::CvtFP2SI>(rdi, xmm13);
buffer.Emit<OpCode::CvtSI2FP>(xmm13s, rdi);
buffer.Emit<OpCode::CvtSI2FP>(xmm13, rdi);
// Between: xmm13 and r8
buffer.Emit<OpCode::Mov>(r8, -4, xmm13s);
buffer.Emit<OpCode::Mov>(r8, 4, xmm13);
buffer.Emit<OpCode::Mov>(xmm13s, r8, -4);
buffer.Emit<OpCode::Mov>(xmm13, r8, 4);
buffer.Emit<OpCode::CvtSI2FP, 4, true, 8, false>(xmm13s, r8, -4);
buffer.Emit<OpCode::CvtSI2FP, 8, true, 4, false>(xmm13, r8, 4);
buffer.Emit<OpCode::CvtFP2SI>(r8d, xmm13s);
buffer.Emit<OpCode::CvtFP2SI>(r8d, xmm13);
buffer.Emit<OpCode::CvtSI2FP>(xmm13s, r8d);
buffer.Emit<OpCode::CvtSI2FP>(xmm13, r8d);
buffer.Emit<OpCode::CvtFP2SI>(r8, xmm13s);
buffer.Emit<OpCode::CvtFP2SI>(r8, xmm13);
buffer.Emit<OpCode::CvtSI2FP>(xmm13s, r8);
buffer.Emit<OpCode::CvtSI2FP>(xmm13, r8);
// Between: xmm13 and r9
buffer.Emit<OpCode::Mov>(r9, -4, xmm13s);
buffer.Emit<OpCode::Mov>(r9, 4, xmm13);
buffer.Emit<OpCode::Mov>(xmm13s, r9, -4);
buffer.Emit<OpCode::Mov>(xmm13, r9, 4);
buffer.Emit<OpCode::CvtSI2FP, 4, true, 8, false>(xmm13s, r9, -4);
buffer.Emit<OpCode::CvtSI2FP, 8, true, 4, false>(xmm13, r9, 4);
buffer.Emit<OpCode::CvtFP2SI>(r9d, xmm13s);
buffer.Emit<OpCode::CvtFP2SI>(r9d, xmm13);
buffer.Emit<OpCode::CvtSI2FP>(xmm13s, r9d);
buffer.Emit<OpCode::CvtSI2FP>(xmm13, r9d);
buffer.Emit<OpCode::CvtFP2SI>(r9, xmm13s);
buffer.Emit<OpCode::CvtFP2SI>(r9, xmm13);
buffer.Emit<OpCode::CvtSI2FP>(xmm13s, r9);
buffer.Emit<OpCode::CvtSI2FP>(xmm13, r9);
// Between: xmm13 and r10
buffer.Emit<OpCode::Mov>(r10, -4, xmm13s);
buffer.Emit<OpCode::Mov>(r10, 4, xmm13);
buffer.Emit<OpCode::Mov>(xmm13s, r10, -4);
buffer.Emit<OpCode::Mov>(xmm13, r10, 4);
buffer.Emit<OpCode::CvtSI2FP, 4, true, 8, false>(xmm13s, r10, -4);
buffer.Emit<OpCode::CvtSI2FP, 8, true, 4, false>(xmm13, r10, 4);
buffer.Emit<OpCode::CvtFP2SI>(r10d, xmm13s);
buffer.Emit<OpCode::CvtFP2SI>(r10d, xmm13);
buffer.Emit<OpCode::CvtSI2FP>(xmm13s, r10d);
buffer.Emit<OpCode::CvtSI2FP>(xmm13, r10d);
buffer.Emit<OpCode::CvtFP2SI>(r10, xmm13s);
buffer.Emit<OpCode::CvtFP2SI>(r10, xmm13);
buffer.Emit<OpCode::CvtSI2FP>(xmm13s, r10);
buffer.Emit<OpCode::CvtSI2FP>(xmm13, r10);
// Between: xmm13 and r11
buffer.Emit<OpCode::Mov>(r11, -4, xmm13s);
buffer.Emit<OpCode::Mov>(r11, 4, xmm13);
buffer.Emit<OpCode::Mov>(xmm13s, r11, -4);
buffer.Emit<OpCode::Mov>(xmm13, r11, 4);
buffer.Emit<OpCode::CvtSI2FP, 4, true, 8, false>(xmm13s, r11, -4);
buffer.Emit<OpCode::CvtSI2FP, 8, true, 4, false>(xmm13, r11, 4);
buffer.Emit<OpCode::CvtFP2SI>(r11d, xmm13s);
buffer.Emit<OpCode::CvtFP2SI>(r11d, xmm13);
buffer.Emit<OpCode::CvtSI2FP>(xmm13s, r11d);
buffer.Emit<OpCode::CvtSI2FP>(xmm13, r11d);
buffer.Emit<OpCode::CvtFP2SI>(r11, xmm13s);
buffer.Emit<OpCode::CvtFP2SI>(r11, xmm13);
buffer.Emit<OpCode::CvtSI2FP>(xmm13s, r11);
buffer.Emit<OpCode::CvtSI2FP>(xmm13, r11);
// Between: xmm13 and r12
buffer.Emit<OpCode::Mov>(r12, -4, xmm13s);
buffer.Emit<OpCode::Mov>(r12, 4, xmm13);
buffer.Emit<OpCode::Mov>(xmm13s, r12, -4);
buffer.Emit<OpCode::Mov>(xmm13, r12, 4);
buffer.Emit<OpCode::CvtSI2FP, 4, true, 8, false>(xmm13s, r12, -4);
buffer.Emit<OpCode::CvtSI2FP, 8, true, 4, false>(xmm13, r12, 4);
buffer.Emit<OpCode::CvtFP2SI>(r12d, xmm13s);
buffer.Emit<OpCode::CvtFP2SI>(r12d, xmm13);
buffer.Emit<OpCode::CvtSI2FP>(xmm13s, r12d);
buffer.Emit<OpCode::CvtSI2FP>(xmm13, r12d);
buffer.Emit<OpCode::CvtFP2SI>(r12, xmm13s);
buffer.Emit<OpCode::CvtFP2SI>(r12, xmm13);
buffer.Emit<OpCode::CvtSI2FP>(xmm13s, r12);
buffer.Emit<OpCode::CvtSI2FP>(xmm13, r12);
// Between: xmm13 and r13
buffer.Emit<OpCode::Mov>(r13, -4, xmm13s);
buffer.Emit<OpCode::Mov>(r13, 4, xmm13);
buffer.Emit<OpCode::Mov>(xmm13s, r13, -4);
buffer.Emit<OpCode::Mov>(xmm13, r13, 4);
buffer.Emit<OpCode::CvtSI2FP, 4, true, 8, false>(xmm13s, r13, -4);
buffer.Emit<OpCode::CvtSI2FP, 8, true, 4, false>(xmm13, r13, 4);
buffer.Emit<OpCode::CvtFP2SI>(r13d, xmm13s);
buffer.Emit<OpCode::CvtFP2SI>(r13d, xmm13);
buffer.Emit<OpCode::CvtSI2FP>(xmm13s, r13d);
buffer.Emit<OpCode::CvtSI2FP>(xmm13, r13d);
buffer.Emit<OpCode::CvtFP2SI>(r13, xmm13s);
buffer.Emit<OpCode::CvtFP2SI>(r13, xmm13);
buffer.Emit<OpCode::CvtSI2FP>(xmm13s, r13);
buffer.Emit<OpCode::CvtSI2FP>(xmm13, r13);
// Between: xmm13 and r14
buffer.Emit<OpCode::Mov>(r14, -4, xmm13s);
buffer.Emit<OpCode::Mov>(r14, 4, xmm13);
buffer.Emit<OpCode::Mov>(xmm13s, r14, -4);
buffer.Emit<OpCode::Mov>(xmm13, r14, 4);
buffer.Emit<OpCode::CvtSI2FP, 4, true, 8, false>(xmm13s, r14, -4);
buffer.Emit<OpCode::CvtSI2FP, 8, true, 4, false>(xmm13, r14, 4);
buffer.Emit<OpCode::CvtFP2SI>(r14d, xmm13s);
buffer.Emit<OpCode::CvtFP2SI>(r14d, xmm13);
buffer.Emit<OpCode::CvtSI2FP>(xmm13s, r14d);
buffer.Emit<OpCode::CvtSI2FP>(xmm13, r14d);
buffer.Emit<OpCode::CvtFP2SI>(r14, xmm13s);
buffer.Emit<OpCode::CvtFP2SI>(r14, xmm13);
buffer.Emit<OpCode::CvtSI2FP>(xmm13s, r14);
buffer.Emit<OpCode::CvtSI2FP>(xmm13, r14);
// Between: xmm13 and r15
buffer.Emit<OpCode::Mov>(r15, -4, xmm13s);
buffer.Emit<OpCode::Mov>(r15, 4, xmm13);
buffer.Emit<OpCode::Mov>(xmm13s, r15, -4);
buffer.Emit<OpCode::Mov>(xmm13, r15, 4);
buffer.Emit<OpCode::CvtSI2FP, 4, true, 8, false>(xmm13s, r15, -4);
buffer.Emit<OpCode::CvtSI2FP, 8, true, 4, false>(xmm13, r15, 4);
buffer.Emit<OpCode::CvtFP2SI>(r15d, xmm13s);
buffer.Emit<OpCode::CvtFP2SI>(r15d, xmm13);
buffer.Emit<OpCode::CvtSI2FP>(xmm13s, r15d);
buffer.Emit<OpCode::CvtSI2FP>(xmm13, r15d);
buffer.Emit<OpCode::CvtFP2SI>(r15, xmm13s);
buffer.Emit<OpCode::CvtFP2SI>(r15, xmm13);
buffer.Emit<OpCode::CvtSI2FP>(xmm13s, r15);
buffer.Emit<OpCode::CvtSI2FP>(xmm13, r15);
// Between: xmm14 and rax
buffer.Emit<OpCode::Mov>(rax, -4, xmm14s);
buffer.Emit<OpCode::Mov>(rax, 4, xmm14);
buffer.Emit<OpCode::Mov>(xmm14s, rax, -4);
buffer.Emit<OpCode::Mov>(xmm14, rax, 4);
buffer.Emit<OpCode::CvtSI2FP, 4, true, 8, false>(xmm14s, rax, -4);
buffer.Emit<OpCode::CvtSI2FP, 8, true, 4, false>(xmm14, rax, 4);
buffer.Emit<OpCode::CvtFP2SI>(eax, xmm14s);
buffer.Emit<OpCode::CvtFP2SI>(eax, xmm14);
buffer.Emit<OpCode::CvtSI2FP>(xmm14s, eax);
buffer.Emit<OpCode::CvtSI2FP>(xmm14, eax);
buffer.Emit<OpCode::CvtFP2SI>(rax, xmm14s);
buffer.Emit<OpCode::CvtFP2SI>(rax, xmm14);
buffer.Emit<OpCode::CvtSI2FP>(xmm14s, rax);
buffer.Emit<OpCode::CvtSI2FP>(xmm14, rax);
// Between: xmm14 and rcx
buffer.Emit<OpCode::Mov>(rcx, -4, xmm14s);
buffer.Emit<OpCode::Mov>(rcx, 4, xmm14);
buffer.Emit<OpCode::Mov>(xmm14s, rcx, -4);
buffer.Emit<OpCode::Mov>(xmm14, rcx, 4);
buffer.Emit<OpCode::CvtSI2FP, 4, true, 8, false>(xmm14s, rcx, -4);
buffer.Emit<OpCode::CvtSI2FP, 8, true, 4, false>(xmm14, rcx, 4);
buffer.Emit<OpCode::CvtFP2SI>(ecx, xmm14s);
buffer.Emit<OpCode::CvtFP2SI>(ecx, xmm14);
buffer.Emit<OpCode::CvtSI2FP>(xmm14s, ecx);
buffer.Emit<OpCode::CvtSI2FP>(xmm14, ecx);
buffer.Emit<OpCode::CvtFP2SI>(rcx, xmm14s);
buffer.Emit<OpCode::CvtFP2SI>(rcx, xmm14);
buffer.Emit<OpCode::CvtSI2FP>(xmm14s, rcx);
buffer.Emit<OpCode::CvtSI2FP>(xmm14, rcx);
// Between: xmm14 and rdx
buffer.Emit<OpCode::Mov>(rdx, -4, xmm14s);
buffer.Emit<OpCode::Mov>(rdx, 4, xmm14);
buffer.Emit<OpCode::Mov>(xmm14s, rdx, -4);
buffer.Emit<OpCode::Mov>(xmm14, rdx, 4);
buffer.Emit<OpCode::CvtSI2FP, 4, true, 8, false>(xmm14s, rdx, -4);
buffer.Emit<OpCode::CvtSI2FP, 8, true, 4, false>(xmm14, rdx, 4);
buffer.Emit<OpCode::CvtFP2SI>(edx, xmm14s);
buffer.Emit<OpCode::CvtFP2SI>(edx, xmm14);
buffer.Emit<OpCode::CvtSI2FP>(xmm14s, edx);
buffer.Emit<OpCode::CvtSI2FP>(xmm14, edx);
buffer.Emit<OpCode::CvtFP2SI>(rdx, xmm14s);
buffer.Emit<OpCode::CvtFP2SI>(rdx, xmm14);
buffer.Emit<OpCode::CvtSI2FP>(xmm14s, rdx);
buffer.Emit<OpCode::CvtSI2FP>(xmm14, rdx);
// Between: xmm14 and rbx
buffer.Emit<OpCode::Mov>(rbx, -4, xmm14s);
buffer.Emit<OpCode::Mov>(rbx, 4, xmm14);
buffer.Emit<OpCode::Mov>(xmm14s, rbx, -4);
buffer.Emit<OpCode::Mov>(xmm14, rbx, 4);
buffer.Emit<OpCode::CvtSI2FP, 4, true, 8, false>(xmm14s, rbx, -4);
buffer.Emit<OpCode::CvtSI2FP, 8, true, 4, false>(xmm14, rbx, 4);
buffer.Emit<OpCode::CvtFP2SI>(ebx, xmm14s);
buffer.Emit<OpCode::CvtFP2SI>(ebx, xmm14);
buffer.Emit<OpCode::CvtSI2FP>(xmm14s, ebx);
buffer.Emit<OpCode::CvtSI2FP>(xmm14, ebx);
buffer.Emit<OpCode::CvtFP2SI>(rbx, xmm14s);
buffer.Emit<OpCode::CvtFP2SI>(rbx, xmm14);
buffer.Emit<OpCode::CvtSI2FP>(xmm14s, rbx);
buffer.Emit<OpCode::CvtSI2FP>(xmm14, rbx);
// Between: xmm14 and rsp
buffer.Emit<OpCode::Mov>(rsp, -4, xmm14s);
buffer.Emit<OpCode::Mov>(rsp, 4, xmm14);
buffer.Emit<OpCode::Mov>(xmm14s, rsp, -4);
buffer.Emit<OpCode::Mov>(xmm14, rsp, 4);
buffer.Emit<OpCode::CvtSI2FP, 4, true, 8, false>(xmm14s, rsp, -4);
buffer.Emit<OpCode::CvtSI2FP, 8, true, 4, false>(xmm14, rsp, 4);
buffer.Emit<OpCode::CvtFP2SI>(esp, xmm14s);
buffer.Emit<OpCode::CvtFP2SI>(esp, xmm14);
buffer.Emit<OpCode::CvtSI2FP>(xmm14s, esp);
buffer.Emit<OpCode::CvtSI2FP>(xmm14, esp);
buffer.Emit<OpCode::CvtFP2SI>(rsp, xmm14s);
buffer.Emit<OpCode::CvtFP2SI>(rsp, xmm14);
buffer.Emit<OpCode::CvtSI2FP>(xmm14s, rsp);
buffer.Emit<OpCode::CvtSI2FP>(xmm14, rsp);
// Between: xmm14 and rbp
buffer.Emit<OpCode::Mov>(rbp, -4, xmm14s);
buffer.Emit<OpCode::Mov>(rbp, 4, xmm14);
buffer.Emit<OpCode::Mov>(xmm14s, rbp, -4);
buffer.Emit<OpCode::Mov>(xmm14, rbp, 4);
buffer.Emit<OpCode::CvtSI2FP, 4, true, 8, false>(xmm14s, rbp, -4);
buffer.Emit<OpCode::CvtSI2FP, 8, true, 4, false>(xmm14, rbp, 4);
buffer.Emit<OpCode::CvtFP2SI>(ebp, xmm14s);
buffer.Emit<OpCode::CvtFP2SI>(ebp, xmm14);
buffer.Emit<OpCode::CvtSI2FP>(xmm14s, ebp);
buffer.Emit<OpCode::CvtSI2FP>(xmm14, ebp);
buffer.Emit<OpCode::CvtFP2SI>(rbp, xmm14s);
buffer.Emit<OpCode::CvtFP2SI>(rbp, xmm14);
buffer.Emit<OpCode::CvtSI2FP>(xmm14s, rbp);
buffer.Emit<OpCode::CvtSI2FP>(xmm14, rbp);
// Between: xmm14 and rsi
buffer.Emit<OpCode::Mov>(rsi, -4, xmm14s);
buffer.Emit<OpCode::Mov>(rsi, 4, xmm14);
buffer.Emit<OpCode::Mov>(xmm14s, rsi, -4);
buffer.Emit<OpCode::Mov>(xmm14, rsi, 4);
buffer.Emit<OpCode::CvtSI2FP, 4, true, 8, false>(xmm14s, rsi, -4);
buffer.Emit<OpCode::CvtSI2FP, 8, true, 4, false>(xmm14, rsi, 4);
buffer.Emit<OpCode::CvtFP2SI>(esi, xmm14s);
buffer.Emit<OpCode::CvtFP2SI>(esi, xmm14);
buffer.Emit<OpCode::CvtSI2FP>(xmm14s, esi);
buffer.Emit<OpCode::CvtSI2FP>(xmm14, esi);
buffer.Emit<OpCode::CvtFP2SI>(rsi, xmm14s);
buffer.Emit<OpCode::CvtFP2SI>(rsi, xmm14);
buffer.Emit<OpCode::CvtSI2FP>(xmm14s, rsi);
buffer.Emit<OpCode::CvtSI2FP>(xmm14, rsi);
// Between: xmm14 and rdi
buffer.Emit<OpCode::Mov>(rdi, -4, xmm14s);
buffer.Emit<OpCode::Mov>(rdi, 4, xmm14);
buffer.Emit<OpCode::Mov>(xmm14s, rdi, -4);
buffer.Emit<OpCode::Mov>(xmm14, rdi, 4);
buffer.Emit<OpCode::CvtSI2FP, 4, true, 8, false>(xmm14s, rdi, -4);
buffer.Emit<OpCode::CvtSI2FP, 8, true, 4, false>(xmm14, rdi, 4);
buffer.Emit<OpCode::CvtFP2SI>(edi, xmm14s);
buffer.Emit<OpCode::CvtFP2SI>(edi, xmm14);
buffer.Emit<OpCode::CvtSI2FP>(xmm14s, edi);
buffer.Emit<OpCode::CvtSI2FP>(xmm14, edi);
buffer.Emit<OpCode::CvtFP2SI>(rdi, xmm14s);
buffer.Emit<OpCode::CvtFP2SI>(rdi, xmm14);
buffer.Emit<OpCode::CvtSI2FP>(xmm14s, rdi);
buffer.Emit<OpCode::CvtSI2FP>(xmm14, rdi);
// Between: xmm14 and r8
buffer.Emit<OpCode::Mov>(r8, -4, xmm14s);
buffer.Emit<OpCode::Mov>(r8, 4, xmm14);
buffer.Emit<OpCode::Mov>(xmm14s, r8, -4);
buffer.Emit<OpCode::Mov>(xmm14, r8, 4);
buffer.Emit<OpCode::CvtSI2FP, 4, true, 8, false>(xmm14s, r8, -4);
buffer.Emit<OpCode::CvtSI2FP, 8, true, 4, false>(xmm14, r8, 4);
buffer.Emit<OpCode::CvtFP2SI>(r8d, xmm14s);
buffer.Emit<OpCode::CvtFP2SI>(r8d, xmm14);
buffer.Emit<OpCode::CvtSI2FP>(xmm14s, r8d);
buffer.Emit<OpCode::CvtSI2FP>(xmm14, r8d);
buffer.Emit<OpCode::CvtFP2SI>(r8, xmm14s);
buffer.Emit<OpCode::CvtFP2SI>(r8, xmm14);
buffer.Emit<OpCode::CvtSI2FP>(xmm14s, r8);
buffer.Emit<OpCode::CvtSI2FP>(xmm14, r8);
// Between: xmm14 and r9
buffer.Emit<OpCode::Mov>(r9, -4, xmm14s);
buffer.Emit<OpCode::Mov>(r9, 4, xmm14);
buffer.Emit<OpCode::Mov>(xmm14s, r9, -4);
buffer.Emit<OpCode::Mov>(xmm14, r9, 4);
buffer.Emit<OpCode::CvtSI2FP, 4, true, 8, false>(xmm14s, r9, -4);
buffer.Emit<OpCode::CvtSI2FP, 8, true, 4, false>(xmm14, r9, 4);
buffer.Emit<OpCode::CvtFP2SI>(r9d, xmm14s);
buffer.Emit<OpCode::CvtFP2SI>(r9d, xmm14);
buffer.Emit<OpCode::CvtSI2FP>(xmm14s, r9d);
buffer.Emit<OpCode::CvtSI2FP>(xmm14, r9d);
buffer.Emit<OpCode::CvtFP2SI>(r9, xmm14s);
buffer.Emit<OpCode::CvtFP2SI>(r9, xmm14);
buffer.Emit<OpCode::CvtSI2FP>(xmm14s, r9);
buffer.Emit<OpCode::CvtSI2FP>(xmm14, r9);
// Between: xmm14 and r10
buffer.Emit<OpCode::Mov>(r10, -4, xmm14s);
buffer.Emit<OpCode::Mov>(r10, 4, xmm14);
buffer.Emit<OpCode::Mov>(xmm14s, r10, -4);
buffer.Emit<OpCode::Mov>(xmm14, r10, 4);
buffer.Emit<OpCode::CvtSI2FP, 4, true, 8, false>(xmm14s, r10, -4);
buffer.Emit<OpCode::CvtSI2FP, 8, true, 4, false>(xmm14, r10, 4);
buffer.Emit<OpCode::CvtFP2SI>(r10d, xmm14s);
buffer.Emit<OpCode::CvtFP2SI>(r10d, xmm14);
buffer.Emit<OpCode::CvtSI2FP>(xmm14s, r10d);
buffer.Emit<OpCode::CvtSI2FP>(xmm14, r10d);
buffer.Emit<OpCode::CvtFP2SI>(r10, xmm14s);
buffer.Emit<OpCode::CvtFP2SI>(r10, xmm14);
buffer.Emit<OpCode::CvtSI2FP>(xmm14s, r10);
buffer.Emit<OpCode::CvtSI2FP>(xmm14, r10);
// Between: xmm14 and r11
buffer.Emit<OpCode::Mov>(r11, -4, xmm14s);
buffer.Emit<OpCode::Mov>(r11, 4, xmm14);
buffer.Emit<OpCode::Mov>(xmm14s, r11, -4);
buffer.Emit<OpCode::Mov>(xmm14, r11, 4);
buffer.Emit<OpCode::CvtSI2FP, 4, true, 8, false>(xmm14s, r11, -4);
buffer.Emit<OpCode::CvtSI2FP, 8, true, 4, false>(xmm14, r11, 4);
buffer.Emit<OpCode::CvtFP2SI>(r11d, xmm14s);
buffer.Emit<OpCode::CvtFP2SI>(r11d, xmm14);
buffer.Emit<OpCode::CvtSI2FP>(xmm14s, r11d);
buffer.Emit<OpCode::CvtSI2FP>(xmm14, r11d);
buffer.Emit<OpCode::CvtFP2SI>(r11, xmm14s);
buffer.Emit<OpCode::CvtFP2SI>(r11, xmm14);
buffer.Emit<OpCode::CvtSI2FP>(xmm14s, r11);
buffer.Emit<OpCode::CvtSI2FP>(xmm14, r11);
// Between: xmm14 and r12
buffer.Emit<OpCode::Mov>(r12, -4, xmm14s);
buffer.Emit<OpCode::Mov>(r12, 4, xmm14);
buffer.Emit<OpCode::Mov>(xmm14s, r12, -4);
buffer.Emit<OpCode::Mov>(xmm14, r12, 4);
buffer.Emit<OpCode::CvtSI2FP, 4, true, 8, false>(xmm14s, r12, -4);
buffer.Emit<OpCode::CvtSI2FP, 8, true, 4, false>(xmm14, r12, 4);
buffer.Emit<OpCode::CvtFP2SI>(r12d, xmm14s);
buffer.Emit<OpCode::CvtFP2SI>(r12d, xmm14);
buffer.Emit<OpCode::CvtSI2FP>(xmm14s, r12d);
buffer.Emit<OpCode::CvtSI2FP>(xmm14, r12d);
buffer.Emit<OpCode::CvtFP2SI>(r12, xmm14s);
buffer.Emit<OpCode::CvtFP2SI>(r12, xmm14);
buffer.Emit<OpCode::CvtSI2FP>(xmm14s, r12);
buffer.Emit<OpCode::CvtSI2FP>(xmm14, r12);
// Between: xmm14 and r13
buffer.Emit<OpCode::Mov>(r13, -4, xmm14s);
buffer.Emit<OpCode::Mov>(r13, 4, xmm14);
buffer.Emit<OpCode::Mov>(xmm14s, r13, -4);
buffer.Emit<OpCode::Mov>(xmm14, r13, 4);
buffer.Emit<OpCode::CvtSI2FP, 4, true, 8, false>(xmm14s, r13, -4);
buffer.Emit<OpCode::CvtSI2FP, 8, true, 4, false>(xmm14, r13, 4);
buffer.Emit<OpCode::CvtFP2SI>(r13d, xmm14s);
buffer.Emit<OpCode::CvtFP2SI>(r13d, xmm14);
buffer.Emit<OpCode::CvtSI2FP>(xmm14s, r13d);
buffer.Emit<OpCode::CvtSI2FP>(xmm14, r13d);
buffer.Emit<OpCode::CvtFP2SI>(r13, xmm14s);
buffer.Emit<OpCode::CvtFP2SI>(r13, xmm14);
buffer.Emit<OpCode::CvtSI2FP>(xmm14s, r13);
buffer.Emit<OpCode::CvtSI2FP>(xmm14, r13);
// Between: xmm14 and r14
buffer.Emit<OpCode::Mov>(r14, -4, xmm14s);
buffer.Emit<OpCode::Mov>(r14, 4, xmm14);
buffer.Emit<OpCode::Mov>(xmm14s, r14, -4);
buffer.Emit<OpCode::Mov>(xmm14, r14, 4);
buffer.Emit<OpCode::CvtSI2FP, 4, true, 8, false>(xmm14s, r14, -4);
buffer.Emit<OpCode::CvtSI2FP, 8, true, 4, false>(xmm14, r14, 4);
buffer.Emit<OpCode::CvtFP2SI>(r14d, xmm14s);
buffer.Emit<OpCode::CvtFP2SI>(r14d, xmm14);
buffer.Emit<OpCode::CvtSI2FP>(xmm14s, r14d);
buffer.Emit<OpCode::CvtSI2FP>(xmm14, r14d);
buffer.Emit<OpCode::CvtFP2SI>(r14, xmm14s);
buffer.Emit<OpCode::CvtFP2SI>(r14, xmm14);
buffer.Emit<OpCode::CvtSI2FP>(xmm14s, r14);
buffer.Emit<OpCode::CvtSI2FP>(xmm14, r14);
// Between: xmm14 and r15
buffer.Emit<OpCode::Mov>(r15, -4, xmm14s);
buffer.Emit<OpCode::Mov>(r15, 4, xmm14);
buffer.Emit<OpCode::Mov>(xmm14s, r15, -4);
buffer.Emit<OpCode::Mov>(xmm14, r15, 4);
buffer.Emit<OpCode::CvtSI2FP, 4, true, 8, false>(xmm14s, r15, -4);
buffer.Emit<OpCode::CvtSI2FP, 8, true, 4, false>(xmm14, r15, 4);
buffer.Emit<OpCode::CvtFP2SI>(r15d, xmm14s);
buffer.Emit<OpCode::CvtFP2SI>(r15d, xmm14);
buffer.Emit<OpCode::CvtSI2FP>(xmm14s, r15d);
buffer.Emit<OpCode::CvtSI2FP>(xmm14, r15d);
buffer.Emit<OpCode::CvtFP2SI>(r15, xmm14s);
buffer.Emit<OpCode::CvtFP2SI>(r15, xmm14);
buffer.Emit<OpCode::CvtSI2FP>(xmm14s, r15);
buffer.Emit<OpCode::CvtSI2FP>(xmm14, r15);
// Between: xmm15 and rax
buffer.Emit<OpCode::Mov>(rax, -4, xmm15s);
buffer.Emit<OpCode::Mov>(rax, 4, xmm15);
buffer.Emit<OpCode::Mov>(xmm15s, rax, -4);
buffer.Emit<OpCode::Mov>(xmm15, rax, 4);
buffer.Emit<OpCode::CvtSI2FP, 4, true, 8, false>(xmm15s, rax, -4);
buffer.Emit<OpCode::CvtSI2FP, 8, true, 4, false>(xmm15, rax, 4);
buffer.Emit<OpCode::CvtFP2SI>(eax, xmm15s);
buffer.Emit<OpCode::CvtFP2SI>(eax, xmm15);
buffer.Emit<OpCode::CvtSI2FP>(xmm15s, eax);
buffer.Emit<OpCode::CvtSI2FP>(xmm15, eax);
buffer.Emit<OpCode::CvtFP2SI>(rax, xmm15s);
buffer.Emit<OpCode::CvtFP2SI>(rax, xmm15);
buffer.Emit<OpCode::CvtSI2FP>(xmm15s, rax);
buffer.Emit<OpCode::CvtSI2FP>(xmm15, rax);
// Between: xmm15 and rcx
buffer.Emit<OpCode::Mov>(rcx, -4, xmm15s);
buffer.Emit<OpCode::Mov>(rcx, 4, xmm15);
buffer.Emit<OpCode::Mov>(xmm15s, rcx, -4);
buffer.Emit<OpCode::Mov>(xmm15, rcx, 4);
buffer.Emit<OpCode::CvtSI2FP, 4, true, 8, false>(xmm15s, rcx, -4);
buffer.Emit<OpCode::CvtSI2FP, 8, true, 4, false>(xmm15, rcx, 4);
buffer.Emit<OpCode::CvtFP2SI>(ecx, xmm15s);
buffer.Emit<OpCode::CvtFP2SI>(ecx, xmm15);
buffer.Emit<OpCode::CvtSI2FP>(xmm15s, ecx);
buffer.Emit<OpCode::CvtSI2FP>(xmm15, ecx);
buffer.Emit<OpCode::CvtFP2SI>(rcx, xmm15s);
buffer.Emit<OpCode::CvtFP2SI>(rcx, xmm15);
buffer.Emit<OpCode::CvtSI2FP>(xmm15s, rcx);
buffer.Emit<OpCode::CvtSI2FP>(xmm15, rcx);
// Between: xmm15 and rdx
buffer.Emit<OpCode::Mov>(rdx, -4, xmm15s);
buffer.Emit<OpCode::Mov>(rdx, 4, xmm15);
buffer.Emit<OpCode::Mov>(xmm15s, rdx, -4);
buffer.Emit<OpCode::Mov>(xmm15, rdx, 4);
buffer.Emit<OpCode::CvtSI2FP, 4, true, 8, false>(xmm15s, rdx, -4);
buffer.Emit<OpCode::CvtSI2FP, 8, true, 4, false>(xmm15, rdx, 4);
buffer.Emit<OpCode::CvtFP2SI>(edx, xmm15s);
buffer.Emit<OpCode::CvtFP2SI>(edx, xmm15);
buffer.Emit<OpCode::CvtSI2FP>(xmm15s, edx);
buffer.Emit<OpCode::CvtSI2FP>(xmm15, edx);
buffer.Emit<OpCode::CvtFP2SI>(rdx, xmm15s);
buffer.Emit<OpCode::CvtFP2SI>(rdx, xmm15);
buffer.Emit<OpCode::CvtSI2FP>(xmm15s, rdx);
buffer.Emit<OpCode::CvtSI2FP>(xmm15, rdx);
// Between: xmm15 and rbx
buffer.Emit<OpCode::Mov>(rbx, -4, xmm15s);
buffer.Emit<OpCode::Mov>(rbx, 4, xmm15);
buffer.Emit<OpCode::Mov>(xmm15s, rbx, -4);
buffer.Emit<OpCode::Mov>(xmm15, rbx, 4);
buffer.Emit<OpCode::CvtSI2FP, 4, true, 8, false>(xmm15s, rbx, -4);
buffer.Emit<OpCode::CvtSI2FP, 8, true, 4, false>(xmm15, rbx, 4);
buffer.Emit<OpCode::CvtFP2SI>(ebx, xmm15s);
buffer.Emit<OpCode::CvtFP2SI>(ebx, xmm15);
buffer.Emit<OpCode::CvtSI2FP>(xmm15s, ebx);
buffer.Emit<OpCode::CvtSI2FP>(xmm15, ebx);
buffer.Emit<OpCode::CvtFP2SI>(rbx, xmm15s);
buffer.Emit<OpCode::CvtFP2SI>(rbx, xmm15);
buffer.Emit<OpCode::CvtSI2FP>(xmm15s, rbx);
buffer.Emit<OpCode::CvtSI2FP>(xmm15, rbx);
// Between: xmm15 and rsp
buffer.Emit<OpCode::Mov>(rsp, -4, xmm15s);
buffer.Emit<OpCode::Mov>(rsp, 4, xmm15);
buffer.Emit<OpCode::Mov>(xmm15s, rsp, -4);
buffer.Emit<OpCode::Mov>(xmm15, rsp, 4);
buffer.Emit<OpCode::CvtSI2FP, 4, true, 8, false>(xmm15s, rsp, -4);
buffer.Emit<OpCode::CvtSI2FP, 8, true, 4, false>(xmm15, rsp, 4);
buffer.Emit<OpCode::CvtFP2SI>(esp, xmm15s);
buffer.Emit<OpCode::CvtFP2SI>(esp, xmm15);
buffer.Emit<OpCode::CvtSI2FP>(xmm15s, esp);
buffer.Emit<OpCode::CvtSI2FP>(xmm15, esp);
buffer.Emit<OpCode::CvtFP2SI>(rsp, xmm15s);
buffer.Emit<OpCode::CvtFP2SI>(rsp, xmm15);
buffer.Emit<OpCode::CvtSI2FP>(xmm15s, rsp);
buffer.Emit<OpCode::CvtSI2FP>(xmm15, rsp);
// Between: xmm15 and rbp
buffer.Emit<OpCode::Mov>(rbp, -4, xmm15s);
buffer.Emit<OpCode::Mov>(rbp, 4, xmm15);
buffer.Emit<OpCode::Mov>(xmm15s, rbp, -4);
buffer.Emit<OpCode::Mov>(xmm15, rbp, 4);
buffer.Emit<OpCode::CvtSI2FP, 4, true, 8, false>(xmm15s, rbp, -4);
buffer.Emit<OpCode::CvtSI2FP, 8, true, 4, false>(xmm15, rbp, 4);
buffer.Emit<OpCode::CvtFP2SI>(ebp, xmm15s);
buffer.Emit<OpCode::CvtFP2SI>(ebp, xmm15);
buffer.Emit<OpCode::CvtSI2FP>(xmm15s, ebp);
buffer.Emit<OpCode::CvtSI2FP>(xmm15, ebp);
buffer.Emit<OpCode::CvtFP2SI>(rbp, xmm15s);
buffer.Emit<OpCode::CvtFP2SI>(rbp, xmm15);
buffer.Emit<OpCode::CvtSI2FP>(xmm15s, rbp);
buffer.Emit<OpCode::CvtSI2FP>(xmm15, rbp);
// Between: xmm15 and rsi
buffer.Emit<OpCode::Mov>(rsi, -4, xmm15s);
buffer.Emit<OpCode::Mov>(rsi, 4, xmm15);
buffer.Emit<OpCode::Mov>(xmm15s, rsi, -4);
buffer.Emit<OpCode::Mov>(xmm15, rsi, 4);
buffer.Emit<OpCode::CvtSI2FP, 4, true, 8, false>(xmm15s, rsi, -4);
buffer.Emit<OpCode::CvtSI2FP, 8, true, 4, false>(xmm15, rsi, 4);
buffer.Emit<OpCode::CvtFP2SI>(esi, xmm15s);
buffer.Emit<OpCode::CvtFP2SI>(esi, xmm15);
buffer.Emit<OpCode::CvtSI2FP>(xmm15s, esi);
buffer.Emit<OpCode::CvtSI2FP>(xmm15, esi);
buffer.Emit<OpCode::CvtFP2SI>(rsi, xmm15s);
buffer.Emit<OpCode::CvtFP2SI>(rsi, xmm15);
buffer.Emit<OpCode::CvtSI2FP>(xmm15s, rsi);
buffer.Emit<OpCode::CvtSI2FP>(xmm15, rsi);
// Between: xmm15 and rdi
buffer.Emit<OpCode::Mov>(rdi, -4, xmm15s);
buffer.Emit<OpCode::Mov>(rdi, 4, xmm15);
buffer.Emit<OpCode::Mov>(xmm15s, rdi, -4);
buffer.Emit<OpCode::Mov>(xmm15, rdi, 4);
buffer.Emit<OpCode::CvtSI2FP, 4, true, 8, false>(xmm15s, rdi, -4);
buffer.Emit<OpCode::CvtSI2FP, 8, true, 4, false>(xmm15, rdi, 4);
buffer.Emit<OpCode::CvtFP2SI>(edi, xmm15s);
buffer.Emit<OpCode::CvtFP2SI>(edi, xmm15);
buffer.Emit<OpCode::CvtSI2FP>(xmm15s, edi);
buffer.Emit<OpCode::CvtSI2FP>(xmm15, edi);
buffer.Emit<OpCode::CvtFP2SI>(rdi, xmm15s);
buffer.Emit<OpCode::CvtFP2SI>(rdi, xmm15);
buffer.Emit<OpCode::CvtSI2FP>(xmm15s, rdi);
buffer.Emit<OpCode::CvtSI2FP>(xmm15, rdi);
// Between: xmm15 and r8
buffer.Emit<OpCode::Mov>(r8, -4, xmm15s);
buffer.Emit<OpCode::Mov>(r8, 4, xmm15);
buffer.Emit<OpCode::Mov>(xmm15s, r8, -4);
buffer.Emit<OpCode::Mov>(xmm15, r8, 4);
buffer.Emit<OpCode::CvtSI2FP, 4, true, 8, false>(xmm15s, r8, -4);
buffer.Emit<OpCode::CvtSI2FP, 8, true, 4, false>(xmm15, r8, 4);
buffer.Emit<OpCode::CvtFP2SI>(r8d, xmm15s);
buffer.Emit<OpCode::CvtFP2SI>(r8d, xmm15);
buffer.Emit<OpCode::CvtSI2FP>(xmm15s, r8d);
buffer.Emit<OpCode::CvtSI2FP>(xmm15, r8d);
buffer.Emit<OpCode::CvtFP2SI>(r8, xmm15s);
buffer.Emit<OpCode::CvtFP2SI>(r8, xmm15);
buffer.Emit<OpCode::CvtSI2FP>(xmm15s, r8);
buffer.Emit<OpCode::CvtSI2FP>(xmm15, r8);
// Between: xmm15 and r9
buffer.Emit<OpCode::Mov>(r9, -4, xmm15s);
buffer.Emit<OpCode::Mov>(r9, 4, xmm15);
buffer.Emit<OpCode::Mov>(xmm15s, r9, -4);
buffer.Emit<OpCode::Mov>(xmm15, r9, 4);
buffer.Emit<OpCode::CvtSI2FP, 4, true, 8, false>(xmm15s, r9, -4);
buffer.Emit<OpCode::CvtSI2FP, 8, true, 4, false>(xmm15, r9, 4);
buffer.Emit<OpCode::CvtFP2SI>(r9d, xmm15s);
buffer.Emit<OpCode::CvtFP2SI>(r9d, xmm15);
buffer.Emit<OpCode::CvtSI2FP>(xmm15s, r9d);
buffer.Emit<OpCode::CvtSI2FP>(xmm15, r9d);
buffer.Emit<OpCode::CvtFP2SI>(r9, xmm15s);
buffer.Emit<OpCode::CvtFP2SI>(r9, xmm15);
buffer.Emit<OpCode::CvtSI2FP>(xmm15s, r9);
buffer.Emit<OpCode::CvtSI2FP>(xmm15, r9);
// Between: xmm15 and r10
buffer.Emit<OpCode::Mov>(r10, -4, xmm15s);
buffer.Emit<OpCode::Mov>(r10, 4, xmm15);
buffer.Emit<OpCode::Mov>(xmm15s, r10, -4);
buffer.Emit<OpCode::Mov>(xmm15, r10, 4);
buffer.Emit<OpCode::CvtSI2FP, 4, true, 8, false>(xmm15s, r10, -4);
buffer.Emit<OpCode::CvtSI2FP, 8, true, 4, false>(xmm15, r10, 4);
buffer.Emit<OpCode::CvtFP2SI>(r10d, xmm15s);
buffer.Emit<OpCode::CvtFP2SI>(r10d, xmm15);
buffer.Emit<OpCode::CvtSI2FP>(xmm15s, r10d);
buffer.Emit<OpCode::CvtSI2FP>(xmm15, r10d);
buffer.Emit<OpCode::CvtFP2SI>(r10, xmm15s);
buffer.Emit<OpCode::CvtFP2SI>(r10, xmm15);
buffer.Emit<OpCode::CvtSI2FP>(xmm15s, r10);
buffer.Emit<OpCode::CvtSI2FP>(xmm15, r10);
// Between: xmm15 and r11
buffer.Emit<OpCode::Mov>(r11, -4, xmm15s);
buffer.Emit<OpCode::Mov>(r11, 4, xmm15);
buffer.Emit<OpCode::Mov>(xmm15s, r11, -4);
buffer.Emit<OpCode::Mov>(xmm15, r11, 4);
buffer.Emit<OpCode::CvtSI2FP, 4, true, 8, false>(xmm15s, r11, -4);
buffer.Emit<OpCode::CvtSI2FP, 8, true, 4, false>(xmm15, r11, 4);
buffer.Emit<OpCode::CvtFP2SI>(r11d, xmm15s);
buffer.Emit<OpCode::CvtFP2SI>(r11d, xmm15);
buffer.Emit<OpCode::CvtSI2FP>(xmm15s, r11d);
buffer.Emit<OpCode::CvtSI2FP>(xmm15, r11d);
buffer.Emit<OpCode::CvtFP2SI>(r11, xmm15s);
buffer.Emit<OpCode::CvtFP2SI>(r11, xmm15);
buffer.Emit<OpCode::CvtSI2FP>(xmm15s, r11);
buffer.Emit<OpCode::CvtSI2FP>(xmm15, r11);
// Between: xmm15 and r12
buffer.Emit<OpCode::Mov>(r12, -4, xmm15s);
buffer.Emit<OpCode::Mov>(r12, 4, xmm15);
buffer.Emit<OpCode::Mov>(xmm15s, r12, -4);
buffer.Emit<OpCode::Mov>(xmm15, r12, 4);
buffer.Emit<OpCode::CvtSI2FP, 4, true, 8, false>(xmm15s, r12, -4);
buffer.Emit<OpCode::CvtSI2FP, 8, true, 4, false>(xmm15, r12, 4);
buffer.Emit<OpCode::CvtFP2SI>(r12d, xmm15s);
buffer.Emit<OpCode::CvtFP2SI>(r12d, xmm15);
buffer.Emit<OpCode::CvtSI2FP>(xmm15s, r12d);
buffer.Emit<OpCode::CvtSI2FP>(xmm15, r12d);
buffer.Emit<OpCode::CvtFP2SI>(r12, xmm15s);
buffer.Emit<OpCode::CvtFP2SI>(r12, xmm15);
buffer.Emit<OpCode::CvtSI2FP>(xmm15s, r12);
buffer.Emit<OpCode::CvtSI2FP>(xmm15, r12);
// Between: xmm15 and r13
buffer.Emit<OpCode::Mov>(r13, -4, xmm15s);
buffer.Emit<OpCode::Mov>(r13, 4, xmm15);
buffer.Emit<OpCode::Mov>(xmm15s, r13, -4);
buffer.Emit<OpCode::Mov>(xmm15, r13, 4);
buffer.Emit<OpCode::CvtSI2FP, 4, true, 8, false>(xmm15s, r13, -4);
buffer.Emit<OpCode::CvtSI2FP, 8, true, 4, false>(xmm15, r13, 4);
buffer.Emit<OpCode::CvtFP2SI>(r13d, xmm15s);
buffer.Emit<OpCode::CvtFP2SI>(r13d, xmm15);
buffer.Emit<OpCode::CvtSI2FP>(xmm15s, r13d);
buffer.Emit<OpCode::CvtSI2FP>(xmm15, r13d);
buffer.Emit<OpCode::CvtFP2SI>(r13, xmm15s);
buffer.Emit<OpCode::CvtFP2SI>(r13, xmm15);
buffer.Emit<OpCode::CvtSI2FP>(xmm15s, r13);
buffer.Emit<OpCode::CvtSI2FP>(xmm15, r13);
// Between: xmm15 and r14
buffer.Emit<OpCode::Mov>(r14, -4, xmm15s);
buffer.Emit<OpCode::Mov>(r14, 4, xmm15);
buffer.Emit<OpCode::Mov>(xmm15s, r14, -4);
buffer.Emit<OpCode::Mov>(xmm15, r14, 4);
buffer.Emit<OpCode::CvtSI2FP, 4, true, 8, false>(xmm15s, r14, -4);
buffer.Emit<OpCode::CvtSI2FP, 8, true, 4, false>(xmm15, r14, 4);
buffer.Emit<OpCode::CvtFP2SI>(r14d, xmm15s);
buffer.Emit<OpCode::CvtFP2SI>(r14d, xmm15);
buffer.Emit<OpCode::CvtSI2FP>(xmm15s, r14d);
buffer.Emit<OpCode::CvtSI2FP>(xmm15, r14d);
buffer.Emit<OpCode::CvtFP2SI>(r14, xmm15s);
buffer.Emit<OpCode::CvtFP2SI>(r14, xmm15);
buffer.Emit<OpCode::CvtSI2FP>(xmm15s, r14);
buffer.Emit<OpCode::CvtSI2FP>(xmm15, r14);
// Between: xmm15 and r15
buffer.Emit<OpCode::Mov>(r15, -4, xmm15s);
buffer.Emit<OpCode::Mov>(r15, 4, xmm15);
buffer.Emit<OpCode::Mov>(xmm15s, r15, -4);
buffer.Emit<OpCode::Mov>(xmm15, r15, 4);
buffer.Emit<OpCode::CvtSI2FP, 4, true, 8, false>(xmm15s, r15, -4);
buffer.Emit<OpCode::CvtSI2FP, 8, true, 4, false>(xmm15, r15, 4);
buffer.Emit<OpCode::CvtFP2SI>(r15d, xmm15s);
buffer.Emit<OpCode::CvtFP2SI>(r15d, xmm15);
buffer.Emit<OpCode::CvtSI2FP>(xmm15s, r15d);
buffer.Emit<OpCode::CvtSI2FP>(xmm15, r15d);
buffer.Emit<OpCode::CvtFP2SI>(r15, xmm15s);
buffer.Emit<OpCode::CvtFP2SI>(r15, xmm15);
buffer.Emit<OpCode::CvtSI2FP>(xmm15s, r15);
buffer.Emit<OpCode::CvtSI2FP>(xmm15, r15);
// The full string is longer than 64 kB and needs to be split in smaller pieces at least for MSVC.
std::string ml64Output;
ml64Output +=
" 00000000 .code \n"
" 00000000 instructions PROC \n"
" \n"
" \n"
" ; Int <-> Int \n"
" \n"
" ; Source: rax, target: rax \n"
" 00000000 B0 01 mov al, 1 \n"
" 00000002 66| B8 0001 mov ax, 1 \n"
" 00000006 B8 00000001 mov eax, 1 \n"
" 0000000B 48/ C7 C0 mov rax, 1 \n"
" 00000001 \n"
" \n"
" 00000012 8A C0 mov al, al \n"
" 00000014 66| 8B C0 mov ax, ax \n"
" 00000017 8B C0 mov eax, eax \n"
" 00000019 48/ 8B C0 mov rax, rax \n"
" \n"
" 0000001C 8A 40 FC mov al, byte ptr [rax - 4] \n"
" 0000001F 8A 40 04 mov al, byte ptr [rax + 4] \n"
" 00000022 66| 8B 40 04 mov ax, word ptr [rax + 4] \n"
" 00000026 8B 40 04 mov eax, dword ptr [rax + 4] \n"
" 00000029 48/ 8B 40 04 mov rax, qword ptr [rax + 4] \n"
" \n"
" 0000002D 88 40 FC mov byte ptr [rax - 4], al \n"
" 00000030 88 40 04 mov byte ptr [rax + 4], al \n"
" 00000033 66| 89 40 04 mov word ptr [rax + 4], ax \n"
" 00000037 89 40 04 mov dword ptr [rax + 4], eax \n"
" 0000003A 48/ 89 40 04 mov qword ptr [rax + 4], rax \n"
" \n"
" 0000003E 66| 0F B6 C0 movzx ax, al \n"
" 00000042 66| 0F B6 40 movzx ax, byte ptr [rax + 4] \n"
" 04 \n"
" \n"
" 00000047 0F B6 C0 movzx eax, al \n"
" 0000004A 0F B7 C0 movzx eax, ax \n"
" 0000004D 0F B6 40 04 movzx eax, byte ptr [rax + 4] \n"
" 00000051 0F B7 40 04 movzx eax, word ptr [rax + 4] \n"
" \n"
" 00000055 48/ 0F B6 C0 movzx rax, al \n"
" 00000059 48/ 0F B7 C0 movzx rax, ax \n"
" 0000005D 48/ 0F B6 40 movzx rax, byte ptr [rax + 4] \n"
" 04 \n"
" 00000062 48/ 0F B7 40 movzx rax, word ptr [rax + 4] \n"
" 04 \n"
" \n"
" \n"
" ; Source: rax, target: rcx \n"
" 00000067 B1 01 mov cl, 1 \n"
" 00000069 66| B9 0001 mov cx, 1 \n"
" 0000006D B9 00000001 mov ecx, 1 \n"
" 00000072 48/ C7 C1 mov rcx, 1 \n"
" 00000001 \n"
" \n"
" 00000079 8A C8 mov cl, al \n"
" 0000007B 66| 8B C8 mov cx, ax \n"
" 0000007E 8B C8 mov ecx, eax \n"
" 00000080 48/ 8B C8 mov rcx, rax \n"
" \n"
" 00000083 8A 48 FC mov cl, byte ptr [rax - 4] \n"
" 00000086 8A 48 04 mov cl, byte ptr [rax + 4] \n"
" 00000089 66| 8B 48 04 mov cx, word ptr [rax + 4] \n"
" 0000008D 8B 48 04 mov ecx, dword ptr [rax + 4] \n"
" 00000090 48/ 8B 48 04 mov rcx, qword ptr [rax + 4] \n"
" \n"
" 00000094 88 41 FC mov byte ptr [rcx - 4], al \n"
" 00000097 88 41 04 mov byte ptr [rcx + 4], al \n"
" 0000009A 66| 89 41 04 mov word ptr [rcx + 4], ax \n"
" 0000009E 89 41 04 mov dword ptr [rcx + 4], eax \n"
" 000000A1 48/ 89 41 04 mov qword ptr [rcx + 4], rax \n"
" \n"
" 000000A5 66| 0F B6 C8 movzx cx, al \n"
" 000000A9 66| 0F B6 48 movzx cx, byte ptr [rax + 4] \n"
" 04 \n"
" \n"
" 000000AE 0F B6 C8 movzx ecx, al \n"
" 000000B1 0F B7 C8 movzx ecx, ax \n"
" 000000B4 0F B6 48 04 movzx ecx, byte ptr [rax + 4] \n"
" 000000B8 0F B7 48 04 movzx ecx, word ptr [rax + 4] \n"
" \n"
" 000000BC 48/ 0F B6 C8 movzx rcx, al \n"
" 000000C0 48/ 0F B7 C8 movzx rcx, ax \n"
" 000000C4 48/ 0F B6 48 movzx rcx, byte ptr [rax + 4] \n"
" 04 \n"
" 000000C9 48/ 0F B7 48 movzx rcx, word ptr [rax + 4] \n"
" 04 \n"
" \n"
" \n"
" ; Source: rax, target: rdx \n"
" 000000CE B2 01 mov dl, 1 \n"
" 000000D0 66| BA 0001 mov dx, 1 \n"
" 000000D4 BA 00000001 mov edx, 1 \n"
" 000000D9 48/ C7 C2 mov rdx, 1 \n"
" 00000001 \n"
" \n"
" 000000E0 8A D0 mov dl, al \n"
" 000000E2 66| 8B D0 mov dx, ax \n"
" 000000E5 8B D0 mov edx, eax \n"
" 000000E7 48/ 8B D0 mov rdx, rax \n"
" \n"
" 000000EA 8A 50 FC mov dl, byte ptr [rax - 4] \n"
" 000000ED 8A 50 04 mov dl, byte ptr [rax + 4] \n"
" 000000F0 66| 8B 50 04 mov dx, word ptr [rax + 4] \n"
" 000000F4 8B 50 04 mov edx, dword ptr [rax + 4] \n"
" 000000F7 48/ 8B 50 04 mov rdx, qword ptr [rax + 4] \n"
" \n"
" 000000FB 88 42 FC mov byte ptr [rdx - 4], al \n"
" 000000FE 88 42 04 mov byte ptr [rdx + 4], al \n"
" 00000101 66| 89 42 04 mov word ptr [rdx + 4], ax \n"
" 00000105 89 42 04 mov dword ptr [rdx + 4], eax \n"
" 00000108 48/ 89 42 04 mov qword ptr [rdx + 4], rax \n"
" \n"
" 0000010C 66| 0F B6 D0 movzx dx, al \n"
" 00000110 66| 0F B6 50 movzx dx, byte ptr [rax + 4] \n"
" 04 \n"
" \n"
" 00000115 0F B6 D0 movzx edx, al \n"
" 00000118 0F B7 D0 movzx edx, ax \n"
" 0000011B 0F B6 50 04 movzx edx, byte ptr [rax + 4] \n"
" 0000011F 0F B7 50 04 movzx edx, word ptr [rax + 4] \n"
" \n"
" 00000123 48/ 0F B6 D0 movzx rdx, al \n"
" 00000127 48/ 0F B7 D0 movzx rdx, ax \n"
" 0000012B 48/ 0F B6 50 movzx rdx, byte ptr [rax + 4] \n"
" 04 \n"
" 00000130 48/ 0F B7 50 movzx rdx, word ptr [rax + 4] \n"
" 04 \n"
" \n"
" \n"
" ; Source: rax, target: rbx \n"
" 00000135 B3 01 mov bl, 1 \n"
" 00000137 66| BB 0001 mov bx, 1 \n"
" 0000013B BB 00000001 mov ebx, 1 \n"
" 00000140 48/ C7 C3 mov rbx, 1 \n"
" 00000001 \n"
" \n"
" 00000147 8A D8 mov bl, al \n"
" 00000149 66| 8B D8 mov bx, ax \n"
" 0000014C 8B D8 mov ebx, eax \n"
" 0000014E 48/ 8B D8 mov rbx, rax \n"
" \n"
" 00000151 8A 58 FC mov bl, byte ptr [rax - 4] \n"
" 00000154 8A 58 04 mov bl, byte ptr [rax + 4] \n"
" 00000157 66| 8B 58 04 mov bx, word ptr [rax + 4] \n"
" 0000015B 8B 58 04 mov ebx, dword ptr [rax + 4] \n"
" 0000015E 48/ 8B 58 04 mov rbx, qword ptr [rax + 4] \n"
" \n"
" 00000162 88 43 FC mov byte ptr [rbx - 4], al \n"
" 00000165 88 43 04 mov byte ptr [rbx + 4], al \n"
" 00000168 66| 89 43 04 mov word ptr [rbx + 4], ax \n"
" 0000016C 89 43 04 mov dword ptr [rbx + 4], eax \n"
" 0000016F 48/ 89 43 04 mov qword ptr [rbx + 4], rax \n"
" \n"
" 00000173 66| 0F B6 D8 movzx bx, al \n"
" 00000177 66| 0F B6 58 movzx bx, byte ptr [rax + 4] \n"
" 04 \n"
" \n"
" 0000017C 0F B6 D8 movzx ebx, al \n"
" 0000017F 0F B7 D8 movzx ebx, ax \n"
" 00000182 0F B6 58 04 movzx ebx, byte ptr [rax + 4] \n"
" 00000186 0F B7 58 04 movzx ebx, word ptr [rax + 4] \n"
" \n"
" 0000018A 48/ 0F B6 D8 movzx rbx, al \n"
" 0000018E 48/ 0F B7 D8 movzx rbx, ax \n"
" 00000192 48/ 0F B6 58 movzx rbx, byte ptr [rax + 4] \n"
" 04 \n"
" 00000197 48/ 0F B7 58 movzx rbx, word ptr [rax + 4] \n"
" 04 \n"
" \n"
" \n"
" ; Source: rax, target: rsp \n"
" 0000019C 40/ B4 01 mov spl, 1 \n"
" 0000019F 66| BC 0001 mov sp, 1 \n"
" 000001A3 BC 00000001 mov esp, 1 \n"
" 000001A8 48/ C7 C4 mov rsp, 1 \n"
" 00000001 \n"
" \n"
" 000001AF 40/ 8A E0 mov spl, al \n"
" 000001B2 66| 8B E0 mov sp, ax \n"
" 000001B5 8B E0 mov esp, eax \n"
" 000001B7 48/ 8B E0 mov rsp, rax \n"
" \n"
" 000001BA 40/ 8A 60 FC mov spl, byte ptr [rax - 4] \n"
" 000001BE 40/ 8A 60 04 mov spl, byte ptr [rax + 4] \n"
" 000001C2 66| 8B 60 04 mov sp, word ptr [rax + 4] \n"
" 000001C6 8B 60 04 mov esp, dword ptr [rax + 4] \n"
" 000001C9 48/ 8B 60 04 mov rsp, qword ptr [rax + 4] \n"
" \n"
" 000001CD 88 44 24 FC mov byte ptr [rsp - 4], al \n"
" 000001D1 88 44 24 04 mov byte ptr [rsp + 4], al \n"
" 000001D5 66| 89 44 24 mov word ptr [rsp + 4], ax \n"
" 04 \n"
" 000001DA 89 44 24 04 mov dword ptr [rsp + 4], eax \n"
" 000001DE 48/ 89 44 24 mov qword ptr [rsp + 4], rax \n"
" 04 \n"
" \n"
" 000001E3 66| 0F B6 E0 movzx sp, al \n"
" 000001E7 66| 0F B6 60 movzx sp, byte ptr [rax + 4] \n"
" 04 \n"
" \n"
" 000001EC 0F B6 E0 movzx esp, al \n"
" 000001EF 0F B7 E0 movzx esp, ax \n"
" 000001F2 0F B6 60 04 movzx esp, byte ptr [rax + 4] \n"
" 000001F6 0F B7 60 04 movzx esp, word ptr [rax + 4] \n"
" \n"
" 000001FA 48/ 0F B6 E0 movzx rsp, al \n"
" 000001FE 48/ 0F B7 E0 movzx rsp, ax \n"
" 00000202 48/ 0F B6 60 movzx rsp, byte ptr [rax + 4] \n"
" 04 \n"
" 00000207 48/ 0F B7 60 movzx rsp, word ptr [rax + 4] \n"
" 04 \n"
" \n"
" \n"
" ; Source: rax, target: rbp \n"
" 0000020C 40/ B5 01 mov bpl, 1 \n"
" 0000020F 66| BD 0001 mov bp, 1 \n"
" 00000213 BD 00000001 mov ebp, 1 \n"
" 00000218 48/ C7 C5 mov rbp, 1 \n"
" 00000001 \n"
" \n"
" 0000021F 40/ 8A E8 mov bpl, al \n"
" 00000222 66| 8B E8 mov bp, ax \n"
" 00000225 8B E8 mov ebp, eax \n"
" 00000227 48/ 8B E8 mov rbp, rax \n"
" \n"
" 0000022A 40/ 8A 68 FC mov bpl, byte ptr [rax - 4] \n"
" 0000022E 40/ 8A 68 04 mov bpl, byte ptr [rax + 4] \n"
" 00000232 66| 8B 68 04 mov bp, word ptr [rax + 4] \n"
" 00000236 8B 68 04 mov ebp, dword ptr [rax + 4] \n"
" 00000239 48/ 8B 68 04 mov rbp, qword ptr [rax + 4] \n"
" \n"
" 0000023D 88 45 FC mov byte ptr [rbp - 4], al \n"
" 00000240 88 45 04 mov byte ptr [rbp + 4], al \n"
" 00000243 66| 89 45 04 mov word ptr [rbp + 4], ax \n"
" 00000247 89 45 04 mov dword ptr [rbp + 4], eax \n"
" 0000024A 48/ 89 45 04 mov qword ptr [rbp + 4], rax \n"
" \n"
" 0000024E 66| 0F B6 E8 movzx bp, al \n"
" 00000252 66| 0F B6 68 movzx bp, byte ptr [rax + 4] \n"
" 04 \n"
" \n"
" 00000257 0F B6 E8 movzx ebp, al \n"
" 0000025A 0F B7 E8 movzx ebp, ax \n"
" 0000025D 0F B6 68 04 movzx ebp, byte ptr [rax + 4] \n"
" 00000261 0F B7 68 04 movzx ebp, word ptr [rax + 4] \n"
" \n"
" 00000265 48/ 0F B6 E8 movzx rbp, al \n"
" 00000269 48/ 0F B7 E8 movzx rbp, ax \n"
" 0000026D 48/ 0F B6 68 movzx rbp, byte ptr [rax + 4] \n"
" 04 \n"
" 00000272 48/ 0F B7 68 movzx rbp, word ptr [rax + 4] \n"
" 04 \n"
" \n"
" \n"
" ; Source: rax, target: rsi \n"
" 00000277 40/ B7 01 mov dil, 1 \n"
" 0000027A 66| BE 0001 mov si, 1 \n"
" 0000027E BE 00000001 mov esi, 1 \n"
" 00000283 48/ C7 C6 mov rsi, 1 \n"
" 00000001 \n"
" \n"
" 0000028A 40/ 8A F8 mov dil, al \n"
" 0000028D 66| 8B F0 mov si, ax \n"
" 00000290 8B F0 mov esi, eax \n"
" 00000292 48/ 8B F0 mov rsi, rax \n"
" \n"
" 00000295 40/ 8A 78 FC mov dil, byte ptr [rax - 4] \n"
" 00000299 40/ 8A 78 04 mov dil, byte ptr [rax + 4] \n"
" 0000029D 66| 8B 70 04 mov si, word ptr [rax + 4] \n"
" 000002A1 8B 70 04 mov esi, dword ptr [rax + 4] \n"
" 000002A4 48/ 8B 70 04 mov rsi, qword ptr [rax + 4] \n"
" \n"
" 000002A8 88 46 FC mov byte ptr [rsi - 4], al \n"
" 000002AB 88 46 04 mov byte ptr [rsi + 4], al \n"
" 000002AE 66| 89 46 04 mov word ptr [rsi + 4], ax \n"
" 000002B2 89 46 04 mov dword ptr [rsi + 4], eax \n"
" 000002B5 48/ 89 46 04 mov qword ptr [rsi + 4], rax \n"
" \n"
" 000002B9 66| 0F B6 F0 movzx si, al \n"
" 000002BD 66| 0F B6 70 movzx si, byte ptr [rax + 4] \n"
" 04 \n"
" \n"
" 000002C2 0F B6 F0 movzx esi, al \n"
" 000002C5 0F B7 F0 movzx esi, ax \n"
" 000002C8 0F B6 70 04 movzx esi, byte ptr [rax + 4] \n"
" 000002CC 0F B7 70 04 movzx esi, word ptr [rax + 4] \n"
" \n"
" 000002D0 48/ 0F B6 F0 movzx rsi, al \n"
" 000002D4 48/ 0F B7 F0 movzx rsi, ax \n"
" 000002D8 48/ 0F B6 70 movzx rsi, byte ptr [rax + 4] \n"
" 04 \n"
" 000002DD 48/ 0F B7 70 movzx rsi, word ptr [rax + 4] \n"
" 04 \n"
" \n"
" \n"
" ; Source: rax, target: rdi \n"
" 000002E2 40/ B6 01 mov sil, 1 \n"
" 000002E5 66| BF 0001 mov di, 1 \n"
" 000002E9 BF 00000001 mov edi, 1 \n"
" 000002EE 48/ C7 C7 mov rdi, 1 \n"
" 00000001 \n"
" \n"
" 000002F5 40/ 8A F0 mov sil, al \n"
" 000002F8 66| 8B F8 mov di, ax \n"
" 000002FB 8B F8 mov edi, eax \n"
" 000002FD 48/ 8B F8 mov rdi, rax \n"
" \n"
" 00000300 40/ 8A 70 FC mov sil, byte ptr [rax - 4] \n"
" 00000304 40/ 8A 70 04 mov sil, byte ptr [rax + 4] \n"
" 00000308 66| 8B 78 04 mov di, word ptr [rax + 4] \n"
" 0000030C 8B 78 04 mov edi, dword ptr [rax + 4] \n"
" 0000030F 48/ 8B 78 04 mov rdi, qword ptr [rax + 4] \n"
" \n"
" 00000313 88 47 FC mov byte ptr [rdi - 4], al \n"
" 00000316 88 47 04 mov byte ptr [rdi + 4], al \n"
" 00000319 66| 89 47 04 mov word ptr [rdi + 4], ax \n"
" 0000031D 89 47 04 mov dword ptr [rdi + 4], eax \n"
" 00000320 48/ 89 47 04 mov qword ptr [rdi + 4], rax \n"
" \n"
" 00000324 66| 0F B6 F8 movzx di, al \n"
" 00000328 66| 0F B6 78 movzx di, byte ptr [rax + 4] \n"
" 04 \n"
" \n"
" 0000032D 0F B6 F8 movzx edi, al \n"
" 00000330 0F B7 F8 movzx edi, ax \n"
" 00000333 0F B6 78 04 movzx edi, byte ptr [rax + 4] \n"
" 00000337 0F B7 78 04 movzx edi, word ptr [rax + 4] \n"
" \n"
" 0000033B 48/ 0F B6 F8 movzx rdi, al \n"
" 0000033F 48/ 0F B7 F8 movzx rdi, ax \n"
" 00000343 48/ 0F B6 78 movzx rdi, byte ptr [rax + 4] \n"
" 04 \n"
" 00000348 48/ 0F B7 78 movzx rdi, word ptr [rax + 4] \n"
" 04 \n"
" \n"
" \n"
" ; Source: rax, target: r8 \n"
" 0000034D 41/ B0 01 mov r8b, 1 \n"
" 00000350 66| 41/ B8 mov r8w, 1 \n"
" 0001 \n"
" 00000355 41/ B8 mov r8d, 1 \n"
" 00000001 \n"
" 0000035B 49/ C7 C0 mov r8, 1 \n"
" 00000001 \n"
" \n"
" 00000362 44/ 8A C0 mov r8b, al \n"
" 00000365 66| 44/ 8B C0 mov r8w, ax \n"
" 00000369 44/ 8B C0 mov r8d, eax \n"
" 0000036C 4C/ 8B C0 mov r8, rax \n"
" \n"
" 0000036F 44/ 8A 40 FC mov r8b, byte ptr [rax - 4] \n"
" 00000373 44/ 8A 40 04 mov r8b, byte ptr [rax + 4] \n"
" 00000377 66| 44/ 8B 40 mov r8w, word ptr [rax + 4] \n"
" 04 \n"
" 0000037C 44/ 8B 40 04 mov r8d, dword ptr [rax + 4] \n"
" 00000380 4C/ 8B 40 04 mov r8, qword ptr [rax + 4] \n"
" \n"
" 00000384 41/ 88 40 FC mov byte ptr [r8 - 4], al \n"
" 00000388 41/ 88 40 04 mov byte ptr [r8 + 4], al \n"
" 0000038C 66| 41/ 89 40 mov word ptr [r8 + 4], ax \n"
" 04 \n"
" 00000391 41/ 89 40 04 mov dword ptr [r8 + 4], eax \n"
" 00000395 49/ 89 40 04 mov qword ptr [r8 + 4], rax \n"
" \n"
" 00000399 66| 44/ 0F B6 C0 movzx r8w, al \n"
" 0000039E 66| 44/ 0F B6 40 movzx r8w, byte ptr [rax + 4] \n"
" 04 \n"
" \n"
" 000003A4 44/ 0F B6 C0 movzx r8d, al \n"
" 000003A8 44/ 0F B7 C0 movzx r8d, ax \n"
" 000003AC 44/ 0F B6 40 movzx r8d, byte ptr [rax + 4] \n"
" 04 \n"
" 000003B1 44/ 0F B7 40 movzx r8d, word ptr [rax + 4] \n"
" 04 \n"
" \n"
" 000003B6 4C/ 0F B6 C0 movzx r8, al \n"
" 000003BA 4C/ 0F B7 C0 movzx r8, ax \n"
" 000003BE 4C/ 0F B6 40 movzx r8, byte ptr [rax + 4] \n"
" 04 \n"
" 000003C3 4C/ 0F B7 40 movzx r8, word ptr [rax + 4] \n"
" 04 \n"
" \n"
" \n"
" ; Source: rax, target: r9 \n"
" 000003C8 41/ B1 01 mov r9b, 1 \n"
" 000003CB 66| 41/ B9 mov r9w, 1 \n"
" 0001 \n"
" 000003D0 41/ B9 mov r9d, 1 \n"
" 00000001 \n"
" 000003D6 49/ C7 C1 mov r9, 1 \n"
" 00000001 \n"
" \n"
" 000003DD 44/ 8A C8 mov r9b, al \n"
" 000003E0 66| 44/ 8B C8 mov r9w, ax \n"
" 000003E4 44/ 8B C8 mov r9d, eax \n"
" 000003E7 4C/ 8B C8 mov r9, rax \n"
" \n"
" 000003EA 44/ 8A 48 FC mov r9b, byte ptr [rax - 4] \n"
" 000003EE 44/ 8A 48 04 mov r9b, byte ptr [rax + 4] \n"
" 000003F2 66| 44/ 8B 48 mov r9w, word ptr [rax + 4] \n"
" 04 \n"
" 000003F7 44/ 8B 48 04 mov r9d, dword ptr [rax + 4] \n"
" 000003FB 4C/ 8B 48 04 mov r9, qword ptr [rax + 4] \n"
" \n"
" 000003FF 41/ 88 41 FC mov byte ptr [r9 - 4], al \n"
" 00000403 41/ 88 41 04 mov byte ptr [r9 + 4], al \n"
" 00000407 66| 41/ 89 41 mov word ptr [r9 + 4], ax \n"
" 04 \n"
" 0000040C 41/ 89 41 04 mov dword ptr [r9 + 4], eax \n"
" 00000410 49/ 89 41 04 mov qword ptr [r9 + 4], rax \n"
" \n"
" 00000414 66| 44/ 0F B6 C8 movzx r9w, al \n"
" 00000419 66| 44/ 0F B6 48 movzx r9w, byte ptr [rax + 4] \n"
" 04 \n"
" \n"
" 0000041F 44/ 0F B6 C8 movzx r9d, al \n"
" 00000423 44/ 0F B7 C8 movzx r9d, ax \n"
" 00000427 44/ 0F B6 48 movzx r9d, byte ptr [rax + 4] \n"
" 04 \n"
" 0000042C 44/ 0F B7 48 movzx r9d, word ptr [rax + 4] \n"
" 04 \n"
" \n"
" 00000431 4C/ 0F B6 C8 movzx r9, al \n"
" 00000435 4C/ 0F B7 C8 movzx r9, ax \n"
" 00000439 4C/ 0F B6 48 movzx r9, byte ptr [rax + 4] \n"
" 04 \n"
" 0000043E 4C/ 0F B7 48 movzx r9, word ptr [rax + 4] \n"
" 04 \n"
" \n"
" \n"
" ; Source: rax, target: r10 \n"
" 00000443 41/ B2 01 mov r10b, 1 \n"
" 00000446 66| 41/ BA mov r10w, 1 \n"
" 0001 \n"
" 0000044B 41/ BA mov r10d, 1 \n"
" 00000001 \n"
" 00000451 49/ C7 C2 mov r10, 1 \n"
" 00000001 \n"
" \n"
" 00000458 44/ 8A D0 mov r10b, al \n"
" 0000045B 66| 44/ 8B D0 mov r10w, ax \n"
" 0000045F 44/ 8B D0 mov r10d, eax \n"
" 00000462 4C/ 8B D0 mov r10, rax \n"
" \n"
" 00000465 44/ 8A 50 FC mov r10b, byte ptr [rax - 4] \n"
" 00000469 44/ 8A 50 04 mov r10b, byte ptr [rax + 4] \n"
" 0000046D 66| 44/ 8B 50 mov r10w, word ptr [rax + 4] \n"
" 04 \n"
" 00000472 44/ 8B 50 04 mov r10d, dword ptr [rax + 4] \n"
" 00000476 4C/ 8B 50 04 mov r10, qword ptr [rax + 4] \n"
" \n"
" 0000047A 41/ 88 42 FC mov byte ptr [r10 - 4], al \n"
" 0000047E 41/ 88 42 04 mov byte ptr [r10 + 4], al \n"
" 00000482 66| 41/ 89 42 mov word ptr [r10 + 4], ax \n"
" 04 \n"
" 00000487 41/ 89 42 04 mov dword ptr [r10 + 4], eax \n"
" 0000048B 49/ 89 42 04 mov qword ptr [r10 + 4], rax \n"
" \n"
" 0000048F 66| 44/ 0F B6 D0 movzx r10w, al \n"
" 00000494 66| 44/ 0F B6 50 movzx r10w, byte ptr [rax + 4] \n"
" 04 \n"
" \n"
" 0000049A 44/ 0F B6 D0 movzx r10d, al \n"
" 0000049E 44/ 0F B7 D0 movzx r10d, ax \n"
" 000004A2 44/ 0F B6 50 movzx r10d, byte ptr [rax + 4] \n"
" 04 \n"
" 000004A7 44/ 0F B7 50 movzx r10d, word ptr [rax + 4] \n"
" 04 \n"
" \n"
" 000004AC 4C/ 0F B6 D0 movzx r10, al \n"
" 000004B0 4C/ 0F B7 D0 movzx r10, ax \n"
" 000004B4 4C/ 0F B6 50 movzx r10, byte ptr [rax + 4] \n"
" 04 \n"
" 000004B9 4C/ 0F B7 50 movzx r10, word ptr [rax + 4] \n"
" 04 \n"
" \n"
" \n"
" ; Source: rax, target: r11 \n"
" 000004BE 41/ B3 01 mov r11b, 1 \n"
" 000004C1 66| 41/ BB mov r11w, 1 \n"
" 0001 \n"
" 000004C6 41/ BB mov r11d, 1 \n"
" 00000001 \n"
" 000004CC 49/ C7 C3 mov r11, 1 \n"
" 00000001 \n"
" \n"
" 000004D3 44/ 8A D8 mov r11b, al \n"
" 000004D6 66| 44/ 8B D8 mov r11w, ax \n"
" 000004DA 44/ 8B D8 mov r11d, eax \n"
" 000004DD 4C/ 8B D8 mov r11, rax \n"
" \n"
" 000004E0 44/ 8A 58 FC mov r11b, byte ptr [rax - 4] \n"
" 000004E4 44/ 8A 58 04 mov r11b, byte ptr [rax + 4] \n"
" 000004E8 66| 44/ 8B 58 mov r11w, word ptr [rax + 4] \n"
" 04 \n"
" 000004ED 44/ 8B 58 04 mov r11d, dword ptr [rax + 4] \n"
" 000004F1 4C/ 8B 58 04 mov r11, qword ptr [rax + 4] \n"
" \n"
" 000004F5 41/ 88 43 FC mov byte ptr [r11 - 4], al \n"
" 000004F9 41/ 88 43 04 mov byte ptr [r11 + 4], al \n"
" 000004FD 66| 41/ 89 43 mov word ptr [r11 + 4], ax \n"
" 04 \n"
" 00000502 41/ 89 43 04 mov dword ptr [r11 + 4], eax \n"
" 00000506 49/ 89 43 04 mov qword ptr [r11 + 4], rax \n"
" \n"
" 0000050A 66| 44/ 0F B6 D8 movzx r11w, al \n"
" 0000050F 66| 44/ 0F B6 58 movzx r11w, byte ptr [rax + 4] \n"
" 04 \n"
" \n"
" 00000515 44/ 0F B6 D8 movzx r11d, al \n"
" 00000519 44/ 0F B7 D8 movzx r11d, ax \n"
" 0000051D 44/ 0F B6 58 movzx r11d, byte ptr [rax + 4] \n"
" 04 \n"
" 00000522 44/ 0F B7 58 movzx r11d, word ptr [rax + 4] \n"
" 04 \n"
" \n"
" 00000527 4C/ 0F B6 D8 movzx r11, al \n"
" 0000052B 4C/ 0F B7 D8 movzx r11, ax \n"
" 0000052F 4C/ 0F B6 58 movzx r11, byte ptr [rax + 4] \n"
" 04 \n"
" 00000534 4C/ 0F B7 58 movzx r11, word ptr [rax + 4] \n"
" 04 \n"
" \n"
" \n"
" ; Source: rax, target: r12 \n"
" 00000539 41/ B4 01 mov r12b, 1 \n"
" 0000053C 66| 41/ BC mov r12w, 1 \n"
" 0001 \n"
" 00000541 41/ BC mov r12d, 1 \n"
" 00000001 \n"
" 00000547 49/ C7 C4 mov r12, 1 \n"
" 00000001 \n"
" \n"
" 0000054E 44/ 8A E0 mov r12b, al \n"
" 00000551 66| 44/ 8B E0 mov r12w, ax \n"
" 00000555 44/ 8B E0 mov r12d, eax \n"
" 00000558 4C/ 8B E0 mov r12, rax \n"
" \n"
" 0000055B 44/ 8A 60 FC mov r12b, byte ptr [rax - 4] \n"
" 0000055F 44/ 8A 60 04 mov r12b, byte ptr [rax + 4] \n"
" 00000563 66| 44/ 8B 60 mov r12w, word ptr [rax + 4] \n"
" 04 \n"
" 00000568 44/ 8B 60 04 mov r12d, dword ptr [rax + 4] \n"
" 0000056C 4C/ 8B 60 04 mov r12, qword ptr [rax + 4] \n"
" \n"
" 00000570 41/ 88 44 24 mov byte ptr [r12 - 4], al \n";
ml64Output +=
" FC \n"
" 00000575 41/ 88 44 24 mov byte ptr [r12 + 4], al \n"
" 04 \n"
" 0000057A 66| 41/ 89 44 24 mov word ptr [r12 + 4], ax \n"
" 04 \n"
" 00000580 41/ 89 44 24 mov dword ptr [r12 + 4], eax \n"
" 04 \n"
" 00000585 49/ 89 44 24 mov qword ptr [r12 + 4], rax \n"
" 04 \n"
" \n"
" 0000058A 66| 44/ 0F B6 E0 movzx r12w, al \n"
" 0000058F 66| 44/ 0F B6 60 movzx r12w, byte ptr [rax + 4] \n"
" 04 \n"
" \n"
" 00000595 44/ 0F B6 E0 movzx r12d, al \n"
" 00000599 44/ 0F B7 E0 movzx r12d, ax \n"
" 0000059D 44/ 0F B6 60 movzx r12d, byte ptr [rax + 4] \n"
" 04 \n"
" 000005A2 44/ 0F B7 60 movzx r12d, word ptr [rax + 4] \n"
" 04 \n"
" \n"
" 000005A7 4C/ 0F B6 E0 movzx r12, al \n"
" 000005AB 4C/ 0F B7 E0 movzx r12, ax \n"
" 000005AF 4C/ 0F B6 60 movzx r12, byte ptr [rax + 4] \n"
" 04 \n"
" 000005B4 4C/ 0F B7 60 movzx r12, word ptr [rax + 4] \n"
" 04 \n"
" \n"
" \n"
" ; Source: rax, target: r13 \n"
" 000005B9 41/ B5 01 mov r13b, 1 \n"
" 000005BC 66| 41/ BD mov r13w, 1 \n"
" 0001 \n"
" 000005C1 41/ BD mov r13d, 1 \n"
" 00000001 \n"
" 000005C7 49/ C7 C5 mov r13, 1 \n"
" 00000001 \n"
" \n"
" 000005CE 44/ 8A E8 mov r13b, al \n"
" 000005D1 66| 44/ 8B E8 mov r13w, ax \n"
" 000005D5 44/ 8B E8 mov r13d, eax \n"
" 000005D8 4C/ 8B E8 mov r13, rax \n"
" \n"
" 000005DB 44/ 8A 68 FC mov r13b, byte ptr [rax - 4] \n"
" 000005DF 44/ 8A 68 04 mov r13b, byte ptr [rax + 4] \n"
" 000005E3 66| 44/ 8B 68 mov r13w, word ptr [rax + 4] \n"
" 04 \n"
" 000005E8 44/ 8B 68 04 mov r13d, dword ptr [rax + 4] \n"
" 000005EC 4C/ 8B 68 04 mov r13, qword ptr [rax + 4] \n"
" \n"
" 000005F0 41/ 88 45 FC mov byte ptr [r13 - 4], al \n"
" 000005F4 41/ 88 45 04 mov byte ptr [r13 + 4], al \n"
" 000005F8 66| 41/ 89 45 mov word ptr [r13 + 4], ax \n"
" 04 \n"
" 000005FD 41/ 89 45 04 mov dword ptr [r13 + 4], eax \n"
" 00000601 49/ 89 45 04 mov qword ptr [r13 + 4], rax \n"
" \n"
" 00000605 66| 44/ 0F B6 E8 movzx r13w, al \n"
" 0000060A 66| 44/ 0F B6 68 movzx r13w, byte ptr [rax + 4] \n"
" 04 \n"
" \n"
" 00000610 44/ 0F B6 E8 movzx r13d, al \n"
" 00000614 44/ 0F B7 E8 movzx r13d, ax \n"
" 00000618 44/ 0F B6 68 movzx r13d, byte ptr [rax + 4] \n"
" 04 \n"
" 0000061D 44/ 0F B7 68 movzx r13d, word ptr [rax + 4] \n"
" 04 \n"
" \n"
" 00000622 4C/ 0F B6 E8 movzx r13, al \n"
" 00000626 4C/ 0F B7 E8 movzx r13, ax \n"
" 0000062A 4C/ 0F B6 68 movzx r13, byte ptr [rax + 4] \n"
" 04 \n"
" 0000062F 4C/ 0F B7 68 movzx r13, word ptr [rax + 4] \n"
" 04 \n"
" \n"
" \n"
" ; Source: rax, target: r14 \n"
" 00000634 41/ B6 01 mov r14b, 1 \n"
" 00000637 66| 41/ BE mov r14w, 1 \n"
" 0001 \n"
" 0000063C 41/ BE mov r14d, 1 \n"
" 00000001 \n"
" 00000642 49/ C7 C6 mov r14, 1 \n"
" 00000001 \n"
" \n"
" 00000649 44/ 8A F0 mov r14b, al \n"
" 0000064C 66| 44/ 8B F0 mov r14w, ax \n"
" 00000650 44/ 8B F0 mov r14d, eax \n"
" 00000653 4C/ 8B F0 mov r14, rax \n"
" \n"
" 00000656 44/ 8A 70 FC mov r14b, byte ptr [rax - 4] \n"
" 0000065A 44/ 8A 70 04 mov r14b, byte ptr [rax + 4] \n"
" 0000065E 66| 44/ 8B 70 mov r14w, word ptr [rax + 4] \n"
" 04 \n"
" 00000663 44/ 8B 70 04 mov r14d, dword ptr [rax + 4] \n"
" 00000667 4C/ 8B 70 04 mov r14, qword ptr [rax + 4] \n"
" \n"
" 0000066B 41/ 88 46 FC mov byte ptr [r14 - 4], al \n"
" 0000066F 41/ 88 46 04 mov byte ptr [r14 + 4], al \n"
" 00000673 66| 41/ 89 46 mov word ptr [r14 + 4], ax \n"
" 04 \n"
" 00000678 41/ 89 46 04 mov dword ptr [r14 + 4], eax \n"
" 0000067C 49/ 89 46 04 mov qword ptr [r14 + 4], rax \n"
" \n"
" 00000680 66| 44/ 0F B6 F0 movzx r14w, al \n"
" 00000685 66| 44/ 0F B6 70 movzx r14w, byte ptr [rax + 4] \n"
" 04 \n"
" \n"
" 0000068B 44/ 0F B6 F0 movzx r14d, al \n"
" 0000068F 44/ 0F B7 F0 movzx r14d, ax \n"
" 00000693 44/ 0F B6 70 movzx r14d, byte ptr [rax + 4] \n"
" 04 \n"
" 00000698 44/ 0F B7 70 movzx r14d, word ptr [rax + 4] \n"
" 04 \n"
" \n"
" 0000069D 4C/ 0F B6 F0 movzx r14, al \n"
" 000006A1 4C/ 0F B7 F0 movzx r14, ax \n"
" 000006A5 4C/ 0F B6 70 movzx r14, byte ptr [rax + 4] \n"
" 04 \n"
" 000006AA 4C/ 0F B7 70 movzx r14, word ptr [rax + 4] \n"
" 04 \n"
" \n"
" \n"
" ; Source: rax, target: r15 \n"
" 000006AF 41/ B7 01 mov r15b, 1 \n"
" 000006B2 66| 41/ BF mov r15w, 1 \n"
" 0001 \n"
" 000006B7 41/ BF mov r15d, 1 \n"
" 00000001 \n"
" 000006BD 49/ C7 C7 mov r15, 1 \n"
" 00000001 \n"
" \n"
" 000006C4 44/ 8A F8 mov r15b, al \n"
" 000006C7 66| 44/ 8B F8 mov r15w, ax \n"
" 000006CB 44/ 8B F8 mov r15d, eax \n"
" 000006CE 4C/ 8B F8 mov r15, rax \n"
" \n"
" 000006D1 44/ 8A 78 FC mov r15b, byte ptr [rax - 4] \n"
" 000006D5 44/ 8A 78 04 mov r15b, byte ptr [rax + 4] \n"
" 000006D9 66| 44/ 8B 78 mov r15w, word ptr [rax + 4] \n"
" 04 \n"
" 000006DE 44/ 8B 78 04 mov r15d, dword ptr [rax + 4] \n"
" 000006E2 4C/ 8B 78 04 mov r15, qword ptr [rax + 4] \n"
" \n"
" 000006E6 41/ 88 47 FC mov byte ptr [r15 - 4], al \n"
" 000006EA 41/ 88 47 04 mov byte ptr [r15 + 4], al \n"
" 000006EE 66| 41/ 89 47 mov word ptr [r15 + 4], ax \n"
" 04 \n"
" 000006F3 41/ 89 47 04 mov dword ptr [r15 + 4], eax \n"
" 000006F7 49/ 89 47 04 mov qword ptr [r15 + 4], rax \n"
" \n"
" 000006FB 66| 44/ 0F B6 F8 movzx r15w, al \n"
" 00000700 66| 44/ 0F B6 78 movzx r15w, byte ptr [rax + 4] \n"
" 04 \n"
" \n"
" 00000706 44/ 0F B6 F8 movzx r15d, al \n"
" 0000070A 44/ 0F B7 F8 movzx r15d, ax \n"
" 0000070E 44/ 0F B6 78 movzx r15d, byte ptr [rax + 4] \n"
" 04 \n"
" 00000713 44/ 0F B7 78 movzx r15d, word ptr [rax + 4] \n"
" 04 \n"
" \n"
" 00000718 4C/ 0F B6 F8 movzx r15, al \n"
" 0000071C 4C/ 0F B7 F8 movzx r15, ax \n"
" 00000720 4C/ 0F B6 78 movzx r15, byte ptr [rax + 4] \n"
" 04 \n"
" 00000725 4C/ 0F B7 78 movzx r15, word ptr [rax + 4] \n"
" 04 \n"
" \n"
" \n"
" ; Source: rcx, target: rax \n"
" 0000072A B0 01 mov al, 1 \n"
" 0000072C 66| B8 0001 mov ax, 1 \n"
" 00000730 B8 00000001 mov eax, 1 \n"
" 00000735 48/ C7 C0 mov rax, 1 \n"
" 00000001 \n"
" \n"
" 0000073C 8A C1 mov al, cl \n"
" 0000073E 66| 8B C1 mov ax, cx \n"
" 00000741 8B C1 mov eax, ecx \n"
" 00000743 48/ 8B C1 mov rax, rcx \n"
" \n"
" 00000746 8A 41 FC mov al, byte ptr [rcx - 4] \n"
" 00000749 8A 41 04 mov al, byte ptr [rcx + 4] \n"
" 0000074C 66| 8B 41 04 mov ax, word ptr [rcx + 4] \n"
" 00000750 8B 41 04 mov eax, dword ptr [rcx + 4] \n"
" 00000753 48/ 8B 41 04 mov rax, qword ptr [rcx + 4] \n"
" \n"
" 00000757 88 48 FC mov byte ptr [rax - 4], cl \n"
" 0000075A 88 48 04 mov byte ptr [rax + 4], cl \n"
" 0000075D 66| 89 48 04 mov word ptr [rax + 4], cx \n"
" 00000761 89 48 04 mov dword ptr [rax + 4], ecx \n"
" 00000764 48/ 89 48 04 mov qword ptr [rax + 4], rcx \n"
" \n"
" 00000768 66| 0F B6 C1 movzx ax, cl \n"
" 0000076C 66| 0F B6 41 movzx ax, byte ptr [rcx + 4] \n"
" 04 \n"
" \n"
" 00000771 0F B6 C1 movzx eax, cl \n"
" 00000774 0F B7 C1 movzx eax, cx \n"
" 00000777 0F B6 41 04 movzx eax, byte ptr [rcx + 4] \n"
" 0000077B 0F B7 41 04 movzx eax, word ptr [rcx + 4] \n"
" \n"
" 0000077F 48/ 0F B6 C1 movzx rax, cl \n"
" 00000783 48/ 0F B7 C1 movzx rax, cx \n"
" 00000787 48/ 0F B6 41 movzx rax, byte ptr [rcx + 4] \n"
" 04 \n"
" 0000078C 48/ 0F B7 41 movzx rax, word ptr [rcx + 4] \n"
" 04 \n"
" \n"
" \n"
" ; Source: rcx, target: rcx \n"
" 00000791 B1 01 mov cl, 1 \n"
" 00000793 66| B9 0001 mov cx, 1 \n"
" 00000797 B9 00000001 mov ecx, 1 \n"
" 0000079C 48/ C7 C1 mov rcx, 1 \n"
" 00000001 \n"
" \n"
" 000007A3 8A C9 mov cl, cl \n"
" 000007A5 66| 8B C9 mov cx, cx \n"
" 000007A8 8B C9 mov ecx, ecx \n"
" 000007AA 48/ 8B C9 mov rcx, rcx \n"
" \n"
" 000007AD 8A 49 FC mov cl, byte ptr [rcx - 4] \n"
" 000007B0 8A 49 04 mov cl, byte ptr [rcx + 4] \n"
" 000007B3 66| 8B 49 04 mov cx, word ptr [rcx + 4] \n"
" 000007B7 8B 49 04 mov ecx, dword ptr [rcx + 4] \n"
" 000007BA 48/ 8B 49 04 mov rcx, qword ptr [rcx + 4] \n"
" \n"
" 000007BE 88 49 FC mov byte ptr [rcx - 4], cl \n"
" 000007C1 88 49 04 mov byte ptr [rcx + 4], cl \n"
" 000007C4 66| 89 49 04 mov word ptr [rcx + 4], cx \n"
" 000007C8 89 49 04 mov dword ptr [rcx + 4], ecx \n"
" 000007CB 48/ 89 49 04 mov qword ptr [rcx + 4], rcx \n"
" \n"
" 000007CF 66| 0F B6 C9 movzx cx, cl \n"
" 000007D3 66| 0F B6 49 movzx cx, byte ptr [rcx + 4] \n"
" 04 \n"
" \n"
" 000007D8 0F B6 C9 movzx ecx, cl \n"
" 000007DB 0F B7 C9 movzx ecx, cx \n"
" 000007DE 0F B6 49 04 movzx ecx, byte ptr [rcx + 4] \n"
" 000007E2 0F B7 49 04 movzx ecx, word ptr [rcx + 4] \n"
" \n"
" 000007E6 48/ 0F B6 C9 movzx rcx, cl \n"
" 000007EA 48/ 0F B7 C9 movzx rcx, cx \n"
" 000007EE 48/ 0F B6 49 movzx rcx, byte ptr [rcx + 4] \n"
" 04 \n"
" 000007F3 48/ 0F B7 49 movzx rcx, word ptr [rcx + 4] \n"
" 04 \n"
" \n"
" \n"
" ; Source: rcx, target: rdx \n"
" 000007F8 B2 01 mov dl, 1 \n"
" 000007FA 66| BA 0001 mov dx, 1 \n"
" 000007FE BA 00000001 mov edx, 1 \n"
" 00000803 48/ C7 C2 mov rdx, 1 \n"
" 00000001 \n"
" \n"
" 0000080A 8A D1 mov dl, cl \n"
" 0000080C 66| 8B D1 mov dx, cx \n"
" 0000080F 8B D1 mov edx, ecx \n"
" 00000811 48/ 8B D1 mov rdx, rcx \n"
" \n"
" 00000814 8A 51 FC mov dl, byte ptr [rcx - 4] \n"
" 00000817 8A 51 04 mov dl, byte ptr [rcx + 4] \n"
" 0000081A 66| 8B 51 04 mov dx, word ptr [rcx + 4] \n"
" 0000081E 8B 51 04 mov edx, dword ptr [rcx + 4] \n"
" 00000821 48/ 8B 51 04 mov rdx, qword ptr [rcx + 4] \n"
" \n"
" 00000825 88 4A FC mov byte ptr [rdx - 4], cl \n"
" 00000828 88 4A 04 mov byte ptr [rdx + 4], cl \n"
" 0000082B 66| 89 4A 04 mov word ptr [rdx + 4], cx \n"
" 0000082F 89 4A 04 mov dword ptr [rdx + 4], ecx \n"
" 00000832 48/ 89 4A 04 mov qword ptr [rdx + 4], rcx \n"
" \n"
" 00000836 66| 0F B6 D1 movzx dx, cl \n"
" 0000083A 66| 0F B6 51 movzx dx, byte ptr [rcx + 4] \n"
" 04 \n"
" \n"
" 0000083F 0F B6 D1 movzx edx, cl \n"
" 00000842 0F B7 D1 movzx edx, cx \n"
" 00000845 0F B6 51 04 movzx edx, byte ptr [rcx + 4] \n"
" 00000849 0F B7 51 04 movzx edx, word ptr [rcx + 4] \n"
" \n"
" 0000084D 48/ 0F B6 D1 movzx rdx, cl \n"
" 00000851 48/ 0F B7 D1 movzx rdx, cx \n"
" 00000855 48/ 0F B6 51 movzx rdx, byte ptr [rcx + 4] \n"
" 04 \n"
" 0000085A 48/ 0F B7 51 movzx rdx, word ptr [rcx + 4] \n"
" 04 \n"
" \n"
" \n"
" ; Source: rcx, target: rbx \n"
" 0000085F B3 01 mov bl, 1 \n"
" 00000861 66| BB 0001 mov bx, 1 \n"
" 00000865 BB 00000001 mov ebx, 1 \n"
" 0000086A 48/ C7 C3 mov rbx, 1 \n"
" 00000001 \n"
" \n"
" 00000871 8A D9 mov bl, cl \n"
" 00000873 66| 8B D9 mov bx, cx \n"
" 00000876 8B D9 mov ebx, ecx \n"
" 00000878 48/ 8B D9 mov rbx, rcx \n"
" \n"
" 0000087B 8A 59 FC mov bl, byte ptr [rcx - 4] \n"
" 0000087E 8A 59 04 mov bl, byte ptr [rcx + 4] \n"
" 00000881 66| 8B 59 04 mov bx, word ptr [rcx + 4] \n"
" 00000885 8B 59 04 mov ebx, dword ptr [rcx + 4] \n"
" 00000888 48/ 8B 59 04 mov rbx, qword ptr [rcx + 4] \n"
" \n"
" 0000088C 88 4B FC mov byte ptr [rbx - 4], cl \n"
" 0000088F 88 4B 04 mov byte ptr [rbx + 4], cl \n"
" 00000892 66| 89 4B 04 mov word ptr [rbx + 4], cx \n"
" 00000896 89 4B 04 mov dword ptr [rbx + 4], ecx \n"
" 00000899 48/ 89 4B 04 mov qword ptr [rbx + 4], rcx \n"
" \n"
" 0000089D 66| 0F B6 D9 movzx bx, cl \n"
" 000008A1 66| 0F B6 59 movzx bx, byte ptr [rcx + 4] \n"
" 04 \n"
" \n"
" 000008A6 0F B6 D9 movzx ebx, cl \n"
" 000008A9 0F B7 D9 movzx ebx, cx \n"
" 000008AC 0F B6 59 04 movzx ebx, byte ptr [rcx + 4] \n"
" 000008B0 0F B7 59 04 movzx ebx, word ptr [rcx + 4] \n"
" \n"
" 000008B4 48/ 0F B6 D9 movzx rbx, cl \n"
" 000008B8 48/ 0F B7 D9 movzx rbx, cx \n"
" 000008BC 48/ 0F B6 59 movzx rbx, byte ptr [rcx + 4] \n"
" 04 \n"
" 000008C1 48/ 0F B7 59 movzx rbx, word ptr [rcx + 4] \n"
" 04 \n"
" \n"
" \n"
" ; Source: rcx, target: rsp \n"
" 000008C6 40/ B4 01 mov spl, 1 \n"
" 000008C9 66| BC 0001 mov sp, 1 \n"
" 000008CD BC 00000001 mov esp, 1 \n"
" 000008D2 48/ C7 C4 mov rsp, 1 \n"
" 00000001 \n"
" \n"
" 000008D9 40/ 8A E1 mov spl, cl \n"
" 000008DC 66| 8B E1 mov sp, cx \n"
" 000008DF 8B E1 mov esp, ecx \n"
" 000008E1 48/ 8B E1 mov rsp, rcx \n"
" \n"
" 000008E4 40/ 8A 61 FC mov spl, byte ptr [rcx - 4] \n"
" 000008E8 40/ 8A 61 04 mov spl, byte ptr [rcx + 4] \n"
" 000008EC 66| 8B 61 04 mov sp, word ptr [rcx + 4] \n"
" 000008F0 8B 61 04 mov esp, dword ptr [rcx + 4] \n"
" 000008F3 48/ 8B 61 04 mov rsp, qword ptr [rcx + 4] \n"
" \n"
" 000008F7 88 4C 24 FC mov byte ptr [rsp - 4], cl \n"
" 000008FB 88 4C 24 04 mov byte ptr [rsp + 4], cl \n"
" 000008FF 66| 89 4C 24 mov word ptr [rsp + 4], cx \n"
" 04 \n"
" 00000904 89 4C 24 04 mov dword ptr [rsp + 4], ecx \n"
" 00000908 48/ 89 4C 24 mov qword ptr [rsp + 4], rcx \n"
" 04 \n"
" \n"
" 0000090D 66| 0F B6 E1 movzx sp, cl \n"
" 00000911 66| 0F B6 61 movzx sp, byte ptr [rcx + 4] \n"
" 04 \n"
" \n"
" 00000916 0F B6 E1 movzx esp, cl \n"
" 00000919 0F B7 E1 movzx esp, cx \n"
" 0000091C 0F B6 61 04 movzx esp, byte ptr [rcx + 4] \n"
" 00000920 0F B7 61 04 movzx esp, word ptr [rcx + 4] \n"
" \n"
" 00000924 48/ 0F B6 E1 movzx rsp, cl \n"
" 00000928 48/ 0F B7 E1 movzx rsp, cx \n"
" 0000092C 48/ 0F B6 61 movzx rsp, byte ptr [rcx + 4] \n"
" 04 \n"
" 00000931 48/ 0F B7 61 movzx rsp, word ptr [rcx + 4] \n"
" 04 \n"
" \n"
" \n"
" ; Source: rcx, target: rbp \n"
" 00000936 40/ B5 01 mov bpl, 1 \n"
" 00000939 66| BD 0001 mov bp, 1 \n"
" 0000093D BD 00000001 mov ebp, 1 \n"
" 00000942 48/ C7 C5 mov rbp, 1 \n"
" 00000001 \n"
" \n"
" 00000949 40/ 8A E9 mov bpl, cl \n"
" 0000094C 66| 8B E9 mov bp, cx \n"
" 0000094F 8B E9 mov ebp, ecx \n"
" 00000951 48/ 8B E9 mov rbp, rcx \n"
" \n"
" 00000954 40/ 8A 69 FC mov bpl, byte ptr [rcx - 4] \n"
" 00000958 40/ 8A 69 04 mov bpl, byte ptr [rcx + 4] \n"
" 0000095C 66| 8B 69 04 mov bp, word ptr [rcx + 4] \n"
" 00000960 8B 69 04 mov ebp, dword ptr [rcx + 4] \n"
" 00000963 48/ 8B 69 04 mov rbp, qword ptr [rcx + 4] \n"
" \n"
" 00000967 88 4D FC mov byte ptr [rbp - 4], cl \n"
" 0000096A 88 4D 04 mov byte ptr [rbp + 4], cl \n"
" 0000096D 66| 89 4D 04 mov word ptr [rbp + 4], cx \n"
" 00000971 89 4D 04 mov dword ptr [rbp + 4], ecx \n"
" 00000974 48/ 89 4D 04 mov qword ptr [rbp + 4], rcx \n"
" \n"
" 00000978 66| 0F B6 E9 movzx bp, cl \n"
" 0000097C 66| 0F B6 69 movzx bp, byte ptr [rcx + 4] \n"
" 04 \n"
" \n"
" 00000981 0F B6 E9 movzx ebp, cl \n"
" 00000984 0F B7 E9 movzx ebp, cx \n"
" 00000987 0F B6 69 04 movzx ebp, byte ptr [rcx + 4] \n"
" 0000098B 0F B7 69 04 movzx ebp, word ptr [rcx + 4] \n"
" \n"
" 0000098F 48/ 0F B6 E9 movzx rbp, cl \n"
" 00000993 48/ 0F B7 E9 movzx rbp, cx \n"
" 00000997 48/ 0F B6 69 movzx rbp, byte ptr [rcx + 4] \n"
" 04 \n"
" 0000099C 48/ 0F B7 69 movzx rbp, word ptr [rcx + 4] \n"
" 04 \n"
" \n"
" \n"
" ; Source: rcx, target: rsi \n"
" 000009A1 40/ B7 01 mov dil, 1 \n"
" 000009A4 66| BE 0001 mov si, 1 \n"
" 000009A8 BE 00000001 mov esi, 1 \n"
" 000009AD 48/ C7 C6 mov rsi, 1 \n"
" 00000001 \n"
" \n"
" 000009B4 40/ 8A F9 mov dil, cl \n"
" 000009B7 66| 8B F1 mov si, cx \n"
" 000009BA 8B F1 mov esi, ecx \n"
" 000009BC 48/ 8B F1 mov rsi, rcx \n"
" \n"
" 000009BF 40/ 8A 79 FC mov dil, byte ptr [rcx - 4] \n"
" 000009C3 40/ 8A 79 04 mov dil, byte ptr [rcx + 4] \n"
" 000009C7 66| 8B 71 04 mov si, word ptr [rcx + 4] \n"
" 000009CB 8B 71 04 mov esi, dword ptr [rcx + 4] \n"
" 000009CE 48/ 8B 71 04 mov rsi, qword ptr [rcx + 4] \n"
" \n"
" 000009D2 88 4E FC mov byte ptr [rsi - 4], cl \n"
" 000009D5 88 4E 04 mov byte ptr [rsi + 4], cl \n"
" 000009D8 66| 89 4E 04 mov word ptr [rsi + 4], cx \n"
" 000009DC 89 4E 04 mov dword ptr [rsi + 4], ecx \n"
" 000009DF 48/ 89 4E 04 mov qword ptr [rsi + 4], rcx \n"
" \n"
" 000009E3 66| 0F B6 F1 movzx si, cl \n"
" 000009E7 66| 0F B6 71 movzx si, byte ptr [rcx + 4] \n"
" 04 \n"
" \n"
" 000009EC 0F B6 F1 movzx esi, cl \n"
" 000009EF 0F B7 F1 movzx esi, cx \n"
" 000009F2 0F B6 71 04 movzx esi, byte ptr [rcx + 4] \n"
" 000009F6 0F B7 71 04 movzx esi, word ptr [rcx + 4] \n"
" \n"
" 000009FA 48/ 0F B6 F1 movzx rsi, cl \n"
" 000009FE 48/ 0F B7 F1 movzx rsi, cx \n"
" 00000A02 48/ 0F B6 71 movzx rsi, byte ptr [rcx + 4] \n"
" 04 \n"
" 00000A07 48/ 0F B7 71 movzx rsi, word ptr [rcx + 4] \n"
" 04 \n"
" \n"
" \n"
" ; Source: rcx, target: rdi \n"
" 00000A0C 40/ B6 01 mov sil, 1 \n"
" 00000A0F 66| BF 0001 mov di, 1 \n"
" 00000A13 BF 00000001 mov edi, 1 \n"
" 00000A18 48/ C7 C7 mov rdi, 1 \n"
" 00000001 \n"
" \n"
" 00000A1F 40/ 8A F1 mov sil, cl \n"
" 00000A22 66| 8B F9 mov di, cx \n"
" 00000A25 8B F9 mov edi, ecx \n"
" 00000A27 48/ 8B F9 mov rdi, rcx \n"
" \n"
" 00000A2A 40/ 8A 71 FC mov sil, byte ptr [rcx - 4] \n"
" 00000A2E 40/ 8A 71 04 mov sil, byte ptr [rcx + 4] \n"
" 00000A32 66| 8B 79 04 mov di, word ptr [rcx + 4] \n"
" 00000A36 8B 79 04 mov edi, dword ptr [rcx + 4] \n"
" 00000A39 48/ 8B 79 04 mov rdi, qword ptr [rcx + 4] \n"
" \n"
" 00000A3D 88 4F FC mov byte ptr [rdi - 4], cl \n"
" 00000A40 88 4F 04 mov byte ptr [rdi + 4], cl \n"
" 00000A43 66| 89 4F 04 mov word ptr [rdi + 4], cx \n"
" 00000A47 89 4F 04 mov dword ptr [rdi + 4], ecx \n"
" 00000A4A 48/ 89 4F 04 mov qword ptr [rdi + 4], rcx \n"
" \n"
" 00000A4E 66| 0F B6 F9 movzx di, cl \n"
" 00000A52 66| 0F B6 79 movzx di, byte ptr [rcx + 4] \n"
" 04 \n"
" \n"
" 00000A57 0F B6 F9 movzx edi, cl \n"
" 00000A5A 0F B7 F9 movzx edi, cx \n"
" 00000A5D 0F B6 79 04 movzx edi, byte ptr [rcx + 4] \n"
" 00000A61 0F B7 79 04 movzx edi, word ptr [rcx + 4] \n"
" \n"
" 00000A65 48/ 0F B6 F9 movzx rdi, cl \n"
" 00000A69 48/ 0F B7 F9 movzx rdi, cx \n"
" 00000A6D 48/ 0F B6 79 movzx rdi, byte ptr [rcx + 4] \n"
" 04 \n"
" 00000A72 48/ 0F B7 79 movzx rdi, word ptr [rcx + 4] \n"
" 04 \n"
" \n"
" \n"
" ; Source: rcx, target: r8 \n"
" 00000A77 41/ B0 01 mov r8b, 1 \n"
" 00000A7A 66| 41/ B8 mov r8w, 1 \n"
" 0001 \n"
" 00000A7F 41/ B8 mov r8d, 1 \n"
" 00000001 \n"
" 00000A85 49/ C7 C0 mov r8, 1 \n"
" 00000001 \n"
" \n"
" 00000A8C 44/ 8A C1 mov r8b, cl \n"
" 00000A8F 66| 44/ 8B C1 mov r8w, cx \n"
" 00000A93 44/ 8B C1 mov r8d, ecx \n"
" 00000A96 4C/ 8B C1 mov r8, rcx \n"
" \n"
" 00000A99 44/ 8A 41 FC mov r8b, byte ptr [rcx - 4] \n"
" 00000A9D 44/ 8A 41 04 mov r8b, byte ptr [rcx + 4] \n"
" 00000AA1 66| 44/ 8B 41 mov r8w, word ptr [rcx + 4] \n"
" 04 \n"
" 00000AA6 44/ 8B 41 04 mov r8d, dword ptr [rcx + 4] \n"
" 00000AAA 4C/ 8B 41 04 mov r8, qword ptr [rcx + 4] \n"
" \n"
" 00000AAE 41/ 88 48 FC mov byte ptr [r8 - 4], cl \n"
" 00000AB2 41/ 88 48 04 mov byte ptr [r8 + 4], cl \n"
" 00000AB6 66| 41/ 89 48 mov word ptr [r8 + 4], cx \n"
" 04 \n"
" 00000ABB 41/ 89 48 04 mov dword ptr [r8 + 4], ecx \n"
" 00000ABF 49/ 89 48 04 mov qword ptr [r8 + 4], rcx \n"
" \n"
" 00000AC3 66| 44/ 0F B6 C1 movzx r8w, cl \n"
" 00000AC8 66| 44/ 0F B6 41 movzx r8w, byte ptr [rcx + 4] \n"
" 04 \n"
" \n"
" 00000ACE 44/ 0F B6 C1 movzx r8d, cl \n"
" 00000AD2 44/ 0F B7 C1 movzx r8d, cx \n"
" 00000AD6 44/ 0F B6 41 movzx r8d, byte ptr [rcx + 4] \n"
" 04 \n"
" 00000ADB 44/ 0F B7 41 movzx r8d, word ptr [rcx + 4] \n"
" 04 \n"
" \n"
" 00000AE0 4C/ 0F B6 C1 movzx r8, cl \n"
" 00000AE4 4C/ 0F B7 C1 movzx r8, cx \n"
" 00000AE8 4C/ 0F B6 41 movzx r8, byte ptr [rcx + 4] \n"
" 04 \n"
" 00000AED 4C/ 0F B7 41 movzx r8, word ptr [rcx + 4] \n"
" 04 \n"
" \n"
" \n"
" ; Source: rcx, target: r9 \n"
" 00000AF2 41/ B1 01 mov r9b, 1 \n"
" 00000AF5 66| 41/ B9 mov r9w, 1 \n";
ml64Output +=
" 0001 \n"
" 00000AFA 41/ B9 mov r9d, 1 \n"
" 00000001 \n"
" 00000B00 49/ C7 C1 mov r9, 1 \n"
" 00000001 \n"
" \n"
" 00000B07 44/ 8A C9 mov r9b, cl \n"
" 00000B0A 66| 44/ 8B C9 mov r9w, cx \n"
" 00000B0E 44/ 8B C9 mov r9d, ecx \n"
" 00000B11 4C/ 8B C9 mov r9, rcx \n"
" \n"
" 00000B14 44/ 8A 49 FC mov r9b, byte ptr [rcx - 4] \n"
" 00000B18 44/ 8A 49 04 mov r9b, byte ptr [rcx + 4] \n"
" 00000B1C 66| 44/ 8B 49 mov r9w, word ptr [rcx + 4] \n"
" 04 \n"
" 00000B21 44/ 8B 49 04 mov r9d, dword ptr [rcx + 4] \n"
" 00000B25 4C/ 8B 49 04 mov r9, qword ptr [rcx + 4] \n"
" \n"
" 00000B29 41/ 88 49 FC mov byte ptr [r9 - 4], cl \n"
" 00000B2D 41/ 88 49 04 mov byte ptr [r9 + 4], cl \n"
" 00000B31 66| 41/ 89 49 mov word ptr [r9 + 4], cx \n"
" 04 \n"
" 00000B36 41/ 89 49 04 mov dword ptr [r9 + 4], ecx \n"
" 00000B3A 49/ 89 49 04 mov qword ptr [r9 + 4], rcx \n"
" \n"
" 00000B3E 66| 44/ 0F B6 C9 movzx r9w, cl \n"
" 00000B43 66| 44/ 0F B6 49 movzx r9w, byte ptr [rcx + 4] \n"
" 04 \n"
" \n"
" 00000B49 44/ 0F B6 C9 movzx r9d, cl \n"
" 00000B4D 44/ 0F B7 C9 movzx r9d, cx \n"
" 00000B51 44/ 0F B6 49 movzx r9d, byte ptr [rcx + 4] \n"
" 04 \n"
" 00000B56 44/ 0F B7 49 movzx r9d, word ptr [rcx + 4] \n"
" 04 \n"
" \n"
" 00000B5B 4C/ 0F B6 C9 movzx r9, cl \n"
" 00000B5F 4C/ 0F B7 C9 movzx r9, cx \n"
" 00000B63 4C/ 0F B6 49 movzx r9, byte ptr [rcx + 4] \n"
" 04 \n"
" 00000B68 4C/ 0F B7 49 movzx r9, word ptr [rcx + 4] \n"
" 04 \n"
" \n"
" \n"
" ; Source: rcx, target: r10 \n"
" 00000B6D 41/ B2 01 mov r10b, 1 \n"
" 00000B70 66| 41/ BA mov r10w, 1 \n"
" 0001 \n"
" 00000B75 41/ BA mov r10d, 1 \n"
" 00000001 \n"
" 00000B7B 49/ C7 C2 mov r10, 1 \n"
" 00000001 \n"
" \n"
" 00000B82 44/ 8A D1 mov r10b, cl \n"
" 00000B85 66| 44/ 8B D1 mov r10w, cx \n"
" 00000B89 44/ 8B D1 mov r10d, ecx \n"
" 00000B8C 4C/ 8B D1 mov r10, rcx \n"
" \n"
" 00000B8F 44/ 8A 51 FC mov r10b, byte ptr [rcx - 4] \n"
" 00000B93 44/ 8A 51 04 mov r10b, byte ptr [rcx + 4] \n"
" 00000B97 66| 44/ 8B 51 mov r10w, word ptr [rcx + 4] \n"
" 04 \n"
" 00000B9C 44/ 8B 51 04 mov r10d, dword ptr [rcx + 4] \n"
" 00000BA0 4C/ 8B 51 04 mov r10, qword ptr [rcx + 4] \n"
" \n"
" 00000BA4 41/ 88 4A FC mov byte ptr [r10 - 4], cl \n"
" 00000BA8 41/ 88 4A 04 mov byte ptr [r10 + 4], cl \n"
" 00000BAC 66| 41/ 89 4A mov word ptr [r10 + 4], cx \n"
" 04 \n"
" 00000BB1 41/ 89 4A 04 mov dword ptr [r10 + 4], ecx \n"
" 00000BB5 49/ 89 4A 04 mov qword ptr [r10 + 4], rcx \n"
" \n"
" 00000BB9 66| 44/ 0F B6 D1 movzx r10w, cl \n"
" 00000BBE 66| 44/ 0F B6 51 movzx r10w, byte ptr [rcx + 4] \n"
" 04 \n"
" \n"
" 00000BC4 44/ 0F B6 D1 movzx r10d, cl \n"
" 00000BC8 44/ 0F B7 D1 movzx r10d, cx \n"
" 00000BCC 44/ 0F B6 51 movzx r10d, byte ptr [rcx + 4] \n"
" 04 \n"
" 00000BD1 44/ 0F B7 51 movzx r10d, word ptr [rcx + 4] \n"
" 04 \n"
" \n"
" 00000BD6 4C/ 0F B6 D1 movzx r10, cl \n"
" 00000BDA 4C/ 0F B7 D1 movzx r10, cx \n"
" 00000BDE 4C/ 0F B6 51 movzx r10, byte ptr [rcx + 4] \n"
" 04 \n"
" 00000BE3 4C/ 0F B7 51 movzx r10, word ptr [rcx + 4] \n"
" 04 \n"
" \n"
" \n"
" ; Source: rcx, target: r11 \n"
" 00000BE8 41/ B3 01 mov r11b, 1 \n"
" 00000BEB 66| 41/ BB mov r11w, 1 \n"
" 0001 \n"
" 00000BF0 41/ BB mov r11d, 1 \n"
" 00000001 \n"
" 00000BF6 49/ C7 C3 mov r11, 1 \n"
" 00000001 \n"
" \n"
" 00000BFD 44/ 8A D9 mov r11b, cl \n"
" 00000C00 66| 44/ 8B D9 mov r11w, cx \n"
" 00000C04 44/ 8B D9 mov r11d, ecx \n"
" 00000C07 4C/ 8B D9 mov r11, rcx \n"
" \n"
" 00000C0A 44/ 8A 59 FC mov r11b, byte ptr [rcx - 4] \n"
" 00000C0E 44/ 8A 59 04 mov r11b, byte ptr [rcx + 4] \n"
" 00000C12 66| 44/ 8B 59 mov r11w, word ptr [rcx + 4] \n"
" 04 \n"
" 00000C17 44/ 8B 59 04 mov r11d, dword ptr [rcx + 4] \n"
" 00000C1B 4C/ 8B 59 04 mov r11, qword ptr [rcx + 4] \n"
" \n"
" 00000C1F 41/ 88 4B FC mov byte ptr [r11 - 4], cl \n"
" 00000C23 41/ 88 4B 04 mov byte ptr [r11 + 4], cl \n"
" 00000C27 66| 41/ 89 4B mov word ptr [r11 + 4], cx \n"
" 04 \n"
" 00000C2C 41/ 89 4B 04 mov dword ptr [r11 + 4], ecx \n"
" 00000C30 49/ 89 4B 04 mov qword ptr [r11 + 4], rcx \n"
" \n"
" 00000C34 66| 44/ 0F B6 D9 movzx r11w, cl \n"
" 00000C39 66| 44/ 0F B6 59 movzx r11w, byte ptr [rcx + 4] \n"
" 04 \n"
" \n"
" 00000C3F 44/ 0F B6 D9 movzx r11d, cl \n"
" 00000C43 44/ 0F B7 D9 movzx r11d, cx \n"
" 00000C47 44/ 0F B6 59 movzx r11d, byte ptr [rcx + 4] \n"
" 04 \n"
" 00000C4C 44/ 0F B7 59 movzx r11d, word ptr [rcx + 4] \n"
" 04 \n"
" \n"
" 00000C51 4C/ 0F B6 D9 movzx r11, cl \n"
" 00000C55 4C/ 0F B7 D9 movzx r11, cx \n"
" 00000C59 4C/ 0F B6 59 movzx r11, byte ptr [rcx + 4] \n"
" 04 \n"
" 00000C5E 4C/ 0F B7 59 movzx r11, word ptr [rcx + 4] \n"
" 04 \n"
" \n"
" \n"
" ; Source: rcx, target: r12 \n"
" 00000C63 41/ B4 01 mov r12b, 1 \n"
" 00000C66 66| 41/ BC mov r12w, 1 \n"
" 0001 \n"
" 00000C6B 41/ BC mov r12d, 1 \n"
" 00000001 \n"
" 00000C71 49/ C7 C4 mov r12, 1 \n"
" 00000001 \n"
" \n"
" 00000C78 44/ 8A E1 mov r12b, cl \n"
" 00000C7B 66| 44/ 8B E1 mov r12w, cx \n"
" 00000C7F 44/ 8B E1 mov r12d, ecx \n"
" 00000C82 4C/ 8B E1 mov r12, rcx \n"
" \n"
" 00000C85 44/ 8A 61 FC mov r12b, byte ptr [rcx - 4] \n"
" 00000C89 44/ 8A 61 04 mov r12b, byte ptr [rcx + 4] \n"
" 00000C8D 66| 44/ 8B 61 mov r12w, word ptr [rcx + 4] \n"
" 04 \n"
" 00000C92 44/ 8B 61 04 mov r12d, dword ptr [rcx + 4] \n"
" 00000C96 4C/ 8B 61 04 mov r12, qword ptr [rcx + 4] \n"
" \n"
" 00000C9A 41/ 88 4C 24 mov byte ptr [r12 - 4], cl \n"
" FC \n"
" 00000C9F 41/ 88 4C 24 mov byte ptr [r12 + 4], cl \n"
" 04 \n"
" 00000CA4 66| 41/ 89 4C 24 mov word ptr [r12 + 4], cx \n"
" 04 \n"
" 00000CAA 41/ 89 4C 24 mov dword ptr [r12 + 4], ecx \n"
" 04 \n"
" 00000CAF 49/ 89 4C 24 mov qword ptr [r12 + 4], rcx \n"
" 04 \n"
" \n"
" 00000CB4 66| 44/ 0F B6 E1 movzx r12w, cl \n"
" 00000CB9 66| 44/ 0F B6 61 movzx r12w, byte ptr [rcx + 4] \n"
" 04 \n"
" \n"
" 00000CBF 44/ 0F B6 E1 movzx r12d, cl \n"
" 00000CC3 44/ 0F B7 E1 movzx r12d, cx \n"
" 00000CC7 44/ 0F B6 61 movzx r12d, byte ptr [rcx + 4] \n"
" 04 \n"
" 00000CCC 44/ 0F B7 61 movzx r12d, word ptr [rcx + 4] \n"
" 04 \n"
" \n"
" 00000CD1 4C/ 0F B6 E1 movzx r12, cl \n"
" 00000CD5 4C/ 0F B7 E1 movzx r12, cx \n"
" 00000CD9 4C/ 0F B6 61 movzx r12, byte ptr [rcx + 4] \n"
" 04 \n"
" 00000CDE 4C/ 0F B7 61 movzx r12, word ptr [rcx + 4] \n"
" 04 \n"
" \n"
" \n"
" ; Source: rcx, target: r13 \n"
" 00000CE3 41/ B5 01 mov r13b, 1 \n"
" 00000CE6 66| 41/ BD mov r13w, 1 \n"
" 0001 \n"
" 00000CEB 41/ BD mov r13d, 1 \n"
" 00000001 \n"
" 00000CF1 49/ C7 C5 mov r13, 1 \n"
" 00000001 \n"
" \n"
" 00000CF8 44/ 8A E9 mov r13b, cl \n"
" 00000CFB 66| 44/ 8B E9 mov r13w, cx \n"
" 00000CFF 44/ 8B E9 mov r13d, ecx \n"
" 00000D02 4C/ 8B E9 mov r13, rcx \n"
" \n"
" 00000D05 44/ 8A 69 FC mov r13b, byte ptr [rcx - 4] \n"
" 00000D09 44/ 8A 69 04 mov r13b, byte ptr [rcx + 4] \n"
" 00000D0D 66| 44/ 8B 69 mov r13w, word ptr [rcx + 4] \n"
" 04 \n"
" 00000D12 44/ 8B 69 04 mov r13d, dword ptr [rcx + 4] \n"
" 00000D16 4C/ 8B 69 04 mov r13, qword ptr [rcx + 4] \n"
" \n"
" 00000D1A 41/ 88 4D FC mov byte ptr [r13 - 4], cl \n"
" 00000D1E 41/ 88 4D 04 mov byte ptr [r13 + 4], cl \n"
" 00000D22 66| 41/ 89 4D mov word ptr [r13 + 4], cx \n"
" 04 \n"
" 00000D27 41/ 89 4D 04 mov dword ptr [r13 + 4], ecx \n"
" 00000D2B 49/ 89 4D 04 mov qword ptr [r13 + 4], rcx \n"
" \n"
" 00000D2F 66| 44/ 0F B6 E9 movzx r13w, cl \n"
" 00000D34 66| 44/ 0F B6 69 movzx r13w, byte ptr [rcx + 4] \n"
" 04 \n"
" \n"
" 00000D3A 44/ 0F B6 E9 movzx r13d, cl \n"
" 00000D3E 44/ 0F B7 E9 movzx r13d, cx \n"
" 00000D42 44/ 0F B6 69 movzx r13d, byte ptr [rcx + 4] \n"
" 04 \n"
" 00000D47 44/ 0F B7 69 movzx r13d, word ptr [rcx + 4] \n"
" 04 \n"
" \n"
" 00000D4C 4C/ 0F B6 E9 movzx r13, cl \n"
" 00000D50 4C/ 0F B7 E9 movzx r13, cx \n"
" 00000D54 4C/ 0F B6 69 movzx r13, byte ptr [rcx + 4] \n"
" 04 \n"
" 00000D59 4C/ 0F B7 69 movzx r13, word ptr [rcx + 4] \n"
" 04 \n"
" \n"
" \n"
" ; Source: rcx, target: r14 \n"
" 00000D5E 41/ B6 01 mov r14b, 1 \n"
" 00000D61 66| 41/ BE mov r14w, 1 \n"
" 0001 \n"
" 00000D66 41/ BE mov r14d, 1 \n"
" 00000001 \n"
" 00000D6C 49/ C7 C6 mov r14, 1 \n"
" 00000001 \n"
" \n"
" 00000D73 44/ 8A F1 mov r14b, cl \n"
" 00000D76 66| 44/ 8B F1 mov r14w, cx \n"
" 00000D7A 44/ 8B F1 mov r14d, ecx \n"
" 00000D7D 4C/ 8B F1 mov r14, rcx \n"
" \n"
" 00000D80 44/ 8A 71 FC mov r14b, byte ptr [rcx - 4] \n"
" 00000D84 44/ 8A 71 04 mov r14b, byte ptr [rcx + 4] \n"
" 00000D88 66| 44/ 8B 71 mov r14w, word ptr [rcx + 4] \n"
" 04 \n"
" 00000D8D 44/ 8B 71 04 mov r14d, dword ptr [rcx + 4] \n"
" 00000D91 4C/ 8B 71 04 mov r14, qword ptr [rcx + 4] \n"
" \n"
" 00000D95 41/ 88 4E FC mov byte ptr [r14 - 4], cl \n"
" 00000D99 41/ 88 4E 04 mov byte ptr [r14 + 4], cl \n"
" 00000D9D 66| 41/ 89 4E mov word ptr [r14 + 4], cx \n"
" 04 \n"
" 00000DA2 41/ 89 4E 04 mov dword ptr [r14 + 4], ecx \n"
" 00000DA6 49/ 89 4E 04 mov qword ptr [r14 + 4], rcx \n"
" \n"
" 00000DAA 66| 44/ 0F B6 F1 movzx r14w, cl \n"
" 00000DAF 66| 44/ 0F B6 71 movzx r14w, byte ptr [rcx + 4] \n"
" 04 \n"
" \n"
" 00000DB5 44/ 0F B6 F1 movzx r14d, cl \n"
" 00000DB9 44/ 0F B7 F1 movzx r14d, cx \n"
" 00000DBD 44/ 0F B6 71 movzx r14d, byte ptr [rcx + 4] \n"
" 04 \n"
" 00000DC2 44/ 0F B7 71 movzx r14d, word ptr [rcx + 4] \n"
" 04 \n"
" \n"
" 00000DC7 4C/ 0F B6 F1 movzx r14, cl \n"
" 00000DCB 4C/ 0F B7 F1 movzx r14, cx \n"
" 00000DCF 4C/ 0F B6 71 movzx r14, byte ptr [rcx + 4] \n"
" 04 \n"
" 00000DD4 4C/ 0F B7 71 movzx r14, word ptr [rcx + 4] \n"
" 04 \n"
" \n"
" \n"
" ; Source: rcx, target: r15 \n"
" 00000DD9 41/ B7 01 mov r15b, 1 \n"
" 00000DDC 66| 41/ BF mov r15w, 1 \n"
" 0001 \n"
" 00000DE1 41/ BF mov r15d, 1 \n"
" 00000001 \n"
" 00000DE7 49/ C7 C7 mov r15, 1 \n"
" 00000001 \n"
" \n"
" 00000DEE 44/ 8A F9 mov r15b, cl \n"
" 00000DF1 66| 44/ 8B F9 mov r15w, cx \n"
" 00000DF5 44/ 8B F9 mov r15d, ecx \n"
" 00000DF8 4C/ 8B F9 mov r15, rcx \n"
" \n"
" 00000DFB 44/ 8A 79 FC mov r15b, byte ptr [rcx - 4] \n"
" 00000DFF 44/ 8A 79 04 mov r15b, byte ptr [rcx + 4] \n"
" 00000E03 66| 44/ 8B 79 mov r15w, word ptr [rcx + 4] \n"
" 04 \n"
" 00000E08 44/ 8B 79 04 mov r15d, dword ptr [rcx + 4] \n"
" 00000E0C 4C/ 8B 79 04 mov r15, qword ptr [rcx + 4] \n"
" \n"
" 00000E10 41/ 88 4F FC mov byte ptr [r15 - 4], cl \n"
" 00000E14 41/ 88 4F 04 mov byte ptr [r15 + 4], cl \n"
" 00000E18 66| 41/ 89 4F mov word ptr [r15 + 4], cx \n"
" 04 \n"
" 00000E1D 41/ 89 4F 04 mov dword ptr [r15 + 4], ecx \n"
" 00000E21 49/ 89 4F 04 mov qword ptr [r15 + 4], rcx \n"
" \n"
" 00000E25 66| 44/ 0F B6 F9 movzx r15w, cl \n"
" 00000E2A 66| 44/ 0F B6 79 movzx r15w, byte ptr [rcx + 4] \n"
" 04 \n"
" \n"
" 00000E30 44/ 0F B6 F9 movzx r15d, cl \n"
" 00000E34 44/ 0F B7 F9 movzx r15d, cx \n"
" 00000E38 44/ 0F B6 79 movzx r15d, byte ptr [rcx + 4] \n"
" 04 \n"
" 00000E3D 44/ 0F B7 79 movzx r15d, word ptr [rcx + 4] \n"
" 04 \n"
" \n"
" 00000E42 4C/ 0F B6 F9 movzx r15, cl \n"
" 00000E46 4C/ 0F B7 F9 movzx r15, cx \n"
" 00000E4A 4C/ 0F B6 79 movzx r15, byte ptr [rcx + 4] \n"
" 04 \n"
" 00000E4F 4C/ 0F B7 79 movzx r15, word ptr [rcx + 4] \n"
" 04 \n"
" \n"
" \n"
" ; Source: rdx, target: rax \n"
" 00000E54 B0 01 mov al, 1 \n"
" 00000E56 66| B8 0001 mov ax, 1 \n"
" 00000E5A B8 00000001 mov eax, 1 \n"
" 00000E5F 48/ C7 C0 mov rax, 1 \n"
" 00000001 \n"
" \n"
" 00000E66 8A C2 mov al, dl \n"
" 00000E68 66| 8B C2 mov ax, dx \n"
" 00000E6B 8B C2 mov eax, edx \n"
" 00000E6D 48/ 8B C2 mov rax, rdx \n"
" \n"
" 00000E70 8A 42 FC mov al, byte ptr [rdx - 4] \n"
" 00000E73 8A 42 04 mov al, byte ptr [rdx + 4] \n"
" 00000E76 66| 8B 42 04 mov ax, word ptr [rdx + 4] \n"
" 00000E7A 8B 42 04 mov eax, dword ptr [rdx + 4] \n"
" 00000E7D 48/ 8B 42 04 mov rax, qword ptr [rdx + 4] \n"
" \n"
" 00000E81 88 50 FC mov byte ptr [rax - 4], dl \n"
" 00000E84 88 50 04 mov byte ptr [rax + 4], dl \n"
" 00000E87 66| 89 50 04 mov word ptr [rax + 4], dx \n"
" 00000E8B 89 50 04 mov dword ptr [rax + 4], edx \n"
" 00000E8E 48/ 89 50 04 mov qword ptr [rax + 4], rdx \n"
" \n"
" 00000E92 66| 0F B6 C2 movzx ax, dl \n"
" 00000E96 66| 0F B6 42 movzx ax, byte ptr [rdx + 4] \n"
" 04 \n"
" \n"
" 00000E9B 0F B6 C2 movzx eax, dl \n"
" 00000E9E 0F B7 C2 movzx eax, dx \n"
" 00000EA1 0F B6 42 04 movzx eax, byte ptr [rdx + 4] \n"
" 00000EA5 0F B7 42 04 movzx eax, word ptr [rdx + 4] \n"
" \n"
" 00000EA9 48/ 0F B6 C2 movzx rax, dl \n"
" 00000EAD 48/ 0F B7 C2 movzx rax, dx \n"
" 00000EB1 48/ 0F B6 42 movzx rax, byte ptr [rdx + 4] \n"
" 04 \n"
" 00000EB6 48/ 0F B7 42 movzx rax, word ptr [rdx + 4] \n"
" 04 \n"
" \n"
" \n"
" ; Source: rdx, target: rcx \n"
" 00000EBB B1 01 mov cl, 1 \n"
" 00000EBD 66| B9 0001 mov cx, 1 \n"
" 00000EC1 B9 00000001 mov ecx, 1 \n"
" 00000EC6 48/ C7 C1 mov rcx, 1 \n"
" 00000001 \n"
" \n"
" 00000ECD 8A CA mov cl, dl \n"
" 00000ECF 66| 8B CA mov cx, dx \n"
" 00000ED2 8B CA mov ecx, edx \n"
" 00000ED4 48/ 8B CA mov rcx, rdx \n"
" \n"
" 00000ED7 8A 4A FC mov cl, byte ptr [rdx - 4] \n"
" 00000EDA 8A 4A 04 mov cl, byte ptr [rdx + 4] \n"
" 00000EDD 66| 8B 4A 04 mov cx, word ptr [rdx + 4] \n"
" 00000EE1 8B 4A 04 mov ecx, dword ptr [rdx + 4] \n"
" 00000EE4 48/ 8B 4A 04 mov rcx, qword ptr [rdx + 4] \n"
" \n"
" 00000EE8 88 51 FC mov byte ptr [rcx - 4], dl \n"
" 00000EEB 88 51 04 mov byte ptr [rcx + 4], dl \n"
" 00000EEE 66| 89 51 04 mov word ptr [rcx + 4], dx \n"
" 00000EF2 89 51 04 mov dword ptr [rcx + 4], edx \n"
" 00000EF5 48/ 89 51 04 mov qword ptr [rcx + 4], rdx \n"
" \n"
" 00000EF9 66| 0F B6 CA movzx cx, dl \n"
" 00000EFD 66| 0F B6 4A movzx cx, byte ptr [rdx + 4] \n"
" 04 \n"
" \n"
" 00000F02 0F B6 CA movzx ecx, dl \n"
" 00000F05 0F B7 CA movzx ecx, dx \n"
" 00000F08 0F B6 4A 04 movzx ecx, byte ptr [rdx + 4] \n"
" 00000F0C 0F B7 4A 04 movzx ecx, word ptr [rdx + 4] \n"
" \n"
" 00000F10 48/ 0F B6 CA movzx rcx, dl \n"
" 00000F14 48/ 0F B7 CA movzx rcx, dx \n"
" 00000F18 48/ 0F B6 4A movzx rcx, byte ptr [rdx + 4] \n"
" 04 \n"
" 00000F1D 48/ 0F B7 4A movzx rcx, word ptr [rdx + 4] \n"
" 04 \n"
" \n"
" \n"
" ; Source: rdx, target: rdx \n"
" 00000F22 B2 01 mov dl, 1 \n"
" 00000F24 66| BA 0001 mov dx, 1 \n"
" 00000F28 BA 00000001 mov edx, 1 \n"
" 00000F2D 48/ C7 C2 mov rdx, 1 \n"
" 00000001 \n"
" \n"
" 00000F34 8A D2 mov dl, dl \n"
" 00000F36 66| 8B D2 mov dx, dx \n"
" 00000F39 8B D2 mov edx, edx \n"
" 00000F3B 48/ 8B D2 mov rdx, rdx \n"
" \n"
" 00000F3E 8A 52 FC mov dl, byte ptr [rdx - 4] \n"
" 00000F41 8A 52 04 mov dl, byte ptr [rdx + 4] \n"
" 00000F44 66| 8B 52 04 mov dx, word ptr [rdx + 4] \n"
" 00000F48 8B 52 04 mov edx, dword ptr [rdx + 4] \n"
" 00000F4B 48/ 8B 52 04 mov rdx, qword ptr [rdx + 4] \n"
" \n"
" 00000F4F 88 52 FC mov byte ptr [rdx - 4], dl \n"
" 00000F52 88 52 04 mov byte ptr [rdx + 4], dl \n"
" 00000F55 66| 89 52 04 mov word ptr [rdx + 4], dx \n"
" 00000F59 89 52 04 mov dword ptr [rdx + 4], edx \n"
" 00000F5C 48/ 89 52 04 mov qword ptr [rdx + 4], rdx \n"
" \n"
" 00000F60 66| 0F B6 D2 movzx dx, dl \n"
" 00000F64 66| 0F B6 52 movzx dx, byte ptr [rdx + 4] \n"
" 04 \n"
" \n"
" 00000F69 0F B6 D2 movzx edx, dl \n"
" 00000F6C 0F B7 D2 movzx edx, dx \n"
" 00000F6F 0F B6 52 04 movzx edx, byte ptr [rdx + 4] \n"
" 00000F73 0F B7 52 04 movzx edx, word ptr [rdx + 4] \n"
" \n"
" 00000F77 48/ 0F B6 D2 movzx rdx, dl \n"
" 00000F7B 48/ 0F B7 D2 movzx rdx, dx \n"
" 00000F7F 48/ 0F B6 52 movzx rdx, byte ptr [rdx + 4] \n"
" 04 \n"
" 00000F84 48/ 0F B7 52 movzx rdx, word ptr [rdx + 4] \n"
" 04 \n"
" \n"
" \n"
" ; Source: rdx, target: rbx \n"
" 00000F89 B3 01 mov bl, 1 \n"
" 00000F8B 66| BB 0001 mov bx, 1 \n"
" 00000F8F BB 00000001 mov ebx, 1 \n"
" 00000F94 48/ C7 C3 mov rbx, 1 \n"
" 00000001 \n"
" \n"
" 00000F9B 8A DA mov bl, dl \n"
" 00000F9D 66| 8B DA mov bx, dx \n"
" 00000FA0 8B DA mov ebx, edx \n"
" 00000FA2 48/ 8B DA mov rbx, rdx \n"
" \n"
" 00000FA5 8A 5A FC mov bl, byte ptr [rdx - 4] \n"
" 00000FA8 8A 5A 04 mov bl, byte ptr [rdx + 4] \n"
" 00000FAB 66| 8B 5A 04 mov bx, word ptr [rdx + 4] \n"
" 00000FAF 8B 5A 04 mov ebx, dword ptr [rdx + 4] \n"
" 00000FB2 48/ 8B 5A 04 mov rbx, qword ptr [rdx + 4] \n"
" \n"
" 00000FB6 88 53 FC mov byte ptr [rbx - 4], dl \n"
" 00000FB9 88 53 04 mov byte ptr [rbx + 4], dl \n"
" 00000FBC 66| 89 53 04 mov word ptr [rbx + 4], dx \n"
" 00000FC0 89 53 04 mov dword ptr [rbx + 4], edx \n"
" 00000FC3 48/ 89 53 04 mov qword ptr [rbx + 4], rdx \n"
" \n"
" 00000FC7 66| 0F B6 DA movzx bx, dl \n"
" 00000FCB 66| 0F B6 5A movzx bx, byte ptr [rdx + 4] \n"
" 04 \n"
" \n"
" 00000FD0 0F B6 DA movzx ebx, dl \n"
" 00000FD3 0F B7 DA movzx ebx, dx \n"
" 00000FD6 0F B6 5A 04 movzx ebx, byte ptr [rdx + 4] \n"
" 00000FDA 0F B7 5A 04 movzx ebx, word ptr [rdx + 4] \n"
" \n"
" 00000FDE 48/ 0F B6 DA movzx rbx, dl \n"
" 00000FE2 48/ 0F B7 DA movzx rbx, dx \n"
" 00000FE6 48/ 0F B6 5A movzx rbx, byte ptr [rdx + 4] \n"
" 04 \n"
" 00000FEB 48/ 0F B7 5A movzx rbx, word ptr [rdx + 4] \n"
" 04 \n"
" \n"
" \n"
" ; Source: rdx, target: rsp \n"
" 00000FF0 40/ B4 01 mov spl, 1 \n"
" 00000FF3 66| BC 0001 mov sp, 1 \n"
" 00000FF7 BC 00000001 mov esp, 1 \n"
" 00000FFC 48/ C7 C4 mov rsp, 1 \n"
" 00000001 \n"
" \n"
" 00001003 40/ 8A E2 mov spl, dl \n"
" 00001006 66| 8B E2 mov sp, dx \n"
" 00001009 8B E2 mov esp, edx \n"
" 0000100B 48/ 8B E2 mov rsp, rdx \n"
" \n"
" 0000100E 40/ 8A 62 FC mov spl, byte ptr [rdx - 4] \n"
" 00001012 40/ 8A 62 04 mov spl, byte ptr [rdx + 4] \n"
" 00001016 66| 8B 62 04 mov sp, word ptr [rdx + 4] \n"
" 0000101A 8B 62 04 mov esp, dword ptr [rdx + 4] \n"
" 0000101D 48/ 8B 62 04 mov rsp, qword ptr [rdx + 4] \n"
" \n"
" 00001021 88 54 24 FC mov byte ptr [rsp - 4], dl \n"
" 00001025 88 54 24 04 mov byte ptr [rsp + 4], dl \n"
" 00001029 66| 89 54 24 mov word ptr [rsp + 4], dx \n"
" 04 \n"
" 0000102E 89 54 24 04 mov dword ptr [rsp + 4], edx \n"
" 00001032 48/ 89 54 24 mov qword ptr [rsp + 4], rdx \n"
" 04 \n"
" \n"
" 00001037 66| 0F B6 E2 movzx sp, dl \n"
" 0000103B 66| 0F B6 62 movzx sp, byte ptr [rdx + 4] \n"
" 04 \n"
" \n"
" 00001040 0F B6 E2 movzx esp, dl \n"
" 00001043 0F B7 E2 movzx esp, dx \n"
" 00001046 0F B6 62 04 movzx esp, byte ptr [rdx + 4] \n"
" 0000104A 0F B7 62 04 movzx esp, word ptr [rdx + 4] \n"
" \n"
" 0000104E 48/ 0F B6 E2 movzx rsp, dl \n"
" 00001052 48/ 0F B7 E2 movzx rsp, dx \n"
" 00001056 48/ 0F B6 62 movzx rsp, byte ptr [rdx + 4] \n"
" 04 \n"
" 0000105B 48/ 0F B7 62 movzx rsp, word ptr [rdx + 4] \n"
" 04 \n"
" \n"
" \n"
" ; Source: rdx, target: rbp \n"
" 00001060 40/ B5 01 mov bpl, 1 \n"
" 00001063 66| BD 0001 mov bp, 1 \n"
" 00001067 BD 00000001 mov ebp, 1 \n"
" 0000106C 48/ C7 C5 mov rbp, 1 \n"
" 00000001 \n"
" \n"
" 00001073 40/ 8A EA mov bpl, dl \n"
" 00001076 66| 8B EA mov bp, dx \n"
" 00001079 8B EA mov ebp, edx \n"
" 0000107B 48/ 8B EA mov rbp, rdx \n"
" \n"
" 0000107E 40/ 8A 6A FC mov bpl, byte ptr [rdx - 4] \n";
ml64Output +=
" 00001082 40/ 8A 6A 04 mov bpl, byte ptr [rdx + 4] \n"
" 00001086 66| 8B 6A 04 mov bp, word ptr [rdx + 4] \n"
" 0000108A 8B 6A 04 mov ebp, dword ptr [rdx + 4] \n"
" 0000108D 48/ 8B 6A 04 mov rbp, qword ptr [rdx + 4] \n"
" \n"
" 00001091 88 55 FC mov byte ptr [rbp - 4], dl \n"
" 00001094 88 55 04 mov byte ptr [rbp + 4], dl \n"
" 00001097 66| 89 55 04 mov word ptr [rbp + 4], dx \n"
" 0000109B 89 55 04 mov dword ptr [rbp + 4], edx \n"
" 0000109E 48/ 89 55 04 mov qword ptr [rbp + 4], rdx \n"
" \n"
" 000010A2 66| 0F B6 EA movzx bp, dl \n"
" 000010A6 66| 0F B6 6A movzx bp, byte ptr [rdx + 4] \n"
" 04 \n"
" \n"
" 000010AB 0F B6 EA movzx ebp, dl \n"
" 000010AE 0F B7 EA movzx ebp, dx \n"
" 000010B1 0F B6 6A 04 movzx ebp, byte ptr [rdx + 4] \n"
" 000010B5 0F B7 6A 04 movzx ebp, word ptr [rdx + 4] \n"
" \n"
" 000010B9 48/ 0F B6 EA movzx rbp, dl \n"
" 000010BD 48/ 0F B7 EA movzx rbp, dx \n"
" 000010C1 48/ 0F B6 6A movzx rbp, byte ptr [rdx + 4] \n"
" 04 \n"
" 000010C6 48/ 0F B7 6A movzx rbp, word ptr [rdx + 4] \n"
" 04 \n"
" \n"
" \n"
" ; Source: rdx, target: rsi \n"
" 000010CB 40/ B7 01 mov dil, 1 \n"
" 000010CE 66| BE 0001 mov si, 1 \n"
" 000010D2 BE 00000001 mov esi, 1 \n"
" 000010D7 48/ C7 C6 mov rsi, 1 \n"
" 00000001 \n"
" \n"
" 000010DE 40/ 8A FA mov dil, dl \n"
" 000010E1 66| 8B F2 mov si, dx \n"
" 000010E4 8B F2 mov esi, edx \n"
" 000010E6 48/ 8B F2 mov rsi, rdx \n"
" \n"
" 000010E9 40/ 8A 7A FC mov dil, byte ptr [rdx - 4] \n"
" 000010ED 40/ 8A 7A 04 mov dil, byte ptr [rdx + 4] \n"
" 000010F1 66| 8B 72 04 mov si, word ptr [rdx + 4] \n"
" 000010F5 8B 72 04 mov esi, dword ptr [rdx + 4] \n"
" 000010F8 48/ 8B 72 04 mov rsi, qword ptr [rdx + 4] \n"
" \n"
" 000010FC 88 56 FC mov byte ptr [rsi - 4], dl \n"
" 000010FF 88 56 04 mov byte ptr [rsi + 4], dl \n"
" 00001102 66| 89 56 04 mov word ptr [rsi + 4], dx \n"
" 00001106 89 56 04 mov dword ptr [rsi + 4], edx \n"
" 00001109 48/ 89 56 04 mov qword ptr [rsi + 4], rdx \n"
" \n"
" 0000110D 66| 0F B6 F2 movzx si, dl \n"
" 00001111 66| 0F B6 72 movzx si, byte ptr [rdx + 4] \n"
" 04 \n"
" \n"
" 00001116 0F B6 F2 movzx esi, dl \n"
" 00001119 0F B7 F2 movzx esi, dx \n"
" 0000111C 0F B6 72 04 movzx esi, byte ptr [rdx + 4] \n"
" 00001120 0F B7 72 04 movzx esi, word ptr [rdx + 4] \n"
" \n"
" 00001124 48/ 0F B6 F2 movzx rsi, dl \n"
" 00001128 48/ 0F B7 F2 movzx rsi, dx \n"
" 0000112C 48/ 0F B6 72 movzx rsi, byte ptr [rdx + 4] \n"
" 04 \n"
" 00001131 48/ 0F B7 72 movzx rsi, word ptr [rdx + 4] \n"
" 04 \n"
" \n"
" \n"
" ; Source: rdx, target: rdi \n"
" 00001136 40/ B6 01 mov sil, 1 \n"
" 00001139 66| BF 0001 mov di, 1 \n"
" 0000113D BF 00000001 mov edi, 1 \n"
" 00001142 48/ C7 C7 mov rdi, 1 \n"
" 00000001 \n"
" \n"
" 00001149 40/ 8A F2 mov sil, dl \n"
" 0000114C 66| 8B FA mov di, dx \n"
" 0000114F 8B FA mov edi, edx \n"
" 00001151 48/ 8B FA mov rdi, rdx \n"
" \n"
" 00001154 40/ 8A 72 FC mov sil, byte ptr [rdx - 4] \n"
" 00001158 40/ 8A 72 04 mov sil, byte ptr [rdx + 4] \n"
" 0000115C 66| 8B 7A 04 mov di, word ptr [rdx + 4] \n"
" 00001160 8B 7A 04 mov edi, dword ptr [rdx + 4] \n"
" 00001163 48/ 8B 7A 04 mov rdi, qword ptr [rdx + 4] \n"
" \n"
" 00001167 88 57 FC mov byte ptr [rdi - 4], dl \n"
" 0000116A 88 57 04 mov byte ptr [rdi + 4], dl \n"
" 0000116D 66| 89 57 04 mov word ptr [rdi + 4], dx \n"
" 00001171 89 57 04 mov dword ptr [rdi + 4], edx \n"
" 00001174 48/ 89 57 04 mov qword ptr [rdi + 4], rdx \n"
" \n"
" 00001178 66| 0F B6 FA movzx di, dl \n"
" 0000117C 66| 0F B6 7A movzx di, byte ptr [rdx + 4] \n"
" 04 \n"
" \n"
" 00001181 0F B6 FA movzx edi, dl \n"
" 00001184 0F B7 FA movzx edi, dx \n"
" 00001187 0F B6 7A 04 movzx edi, byte ptr [rdx + 4] \n"
" 0000118B 0F B7 7A 04 movzx edi, word ptr [rdx + 4] \n"
" \n"
" 0000118F 48/ 0F B6 FA movzx rdi, dl \n"
" 00001193 48/ 0F B7 FA movzx rdi, dx \n"
" 00001197 48/ 0F B6 7A movzx rdi, byte ptr [rdx + 4] \n"
" 04 \n"
" 0000119C 48/ 0F B7 7A movzx rdi, word ptr [rdx + 4] \n"
" 04 \n"
" \n"
" \n"
" ; Source: rdx, target: r8 \n"
" 000011A1 41/ B0 01 mov r8b, 1 \n"
" 000011A4 66| 41/ B8 mov r8w, 1 \n"
" 0001 \n"
" 000011A9 41/ B8 mov r8d, 1 \n"
" 00000001 \n"
" 000011AF 49/ C7 C0 mov r8, 1 \n"
" 00000001 \n"
" \n"
" 000011B6 44/ 8A C2 mov r8b, dl \n"
" 000011B9 66| 44/ 8B C2 mov r8w, dx \n"
" 000011BD 44/ 8B C2 mov r8d, edx \n"
" 000011C0 4C/ 8B C2 mov r8, rdx \n"
" \n"
" 000011C3 44/ 8A 42 FC mov r8b, byte ptr [rdx - 4] \n"
" 000011C7 44/ 8A 42 04 mov r8b, byte ptr [rdx + 4] \n"
" 000011CB 66| 44/ 8B 42 mov r8w, word ptr [rdx + 4] \n"
" 04 \n"
" 000011D0 44/ 8B 42 04 mov r8d, dword ptr [rdx + 4] \n"
" 000011D4 4C/ 8B 42 04 mov r8, qword ptr [rdx + 4] \n"
" \n"
" 000011D8 41/ 88 50 FC mov byte ptr [r8 - 4], dl \n"
" 000011DC 41/ 88 50 04 mov byte ptr [r8 + 4], dl \n"
" 000011E0 66| 41/ 89 50 mov word ptr [r8 + 4], dx \n"
" 04 \n"
" 000011E5 41/ 89 50 04 mov dword ptr [r8 + 4], edx \n"
" 000011E9 49/ 89 50 04 mov qword ptr [r8 + 4], rdx \n"
" \n"
" 000011ED 66| 44/ 0F B6 C2 movzx r8w, dl \n"
" 000011F2 66| 44/ 0F B6 42 movzx r8w, byte ptr [rdx + 4] \n"
" 04 \n"
" \n"
" 000011F8 44/ 0F B6 C2 movzx r8d, dl \n"
" 000011FC 44/ 0F B7 C2 movzx r8d, dx \n"
" 00001200 44/ 0F B6 42 movzx r8d, byte ptr [rdx + 4] \n"
" 04 \n"
" 00001205 44/ 0F B7 42 movzx r8d, word ptr [rdx + 4] \n"
" 04 \n"
" \n"
" 0000120A 4C/ 0F B6 C2 movzx r8, dl \n"
" 0000120E 4C/ 0F B7 C2 movzx r8, dx \n"
" 00001212 4C/ 0F B6 42 movzx r8, byte ptr [rdx + 4] \n"
" 04 \n"
" 00001217 4C/ 0F B7 42 movzx r8, word ptr [rdx + 4] \n"
" 04 \n"
" \n"
" \n"
" ; Source: rdx, target: r9 \n"
" 0000121C 41/ B1 01 mov r9b, 1 \n"
" 0000121F 66| 41/ B9 mov r9w, 1 \n"
" 0001 \n"
" 00001224 41/ B9 mov r9d, 1 \n"
" 00000001 \n"
" 0000122A 49/ C7 C1 mov r9, 1 \n"
" 00000001 \n"
" \n"
" 00001231 44/ 8A CA mov r9b, dl \n"
" 00001234 66| 44/ 8B CA mov r9w, dx \n"
" 00001238 44/ 8B CA mov r9d, edx \n"
" 0000123B 4C/ 8B CA mov r9, rdx \n"
" \n"
" 0000123E 44/ 8A 4A FC mov r9b, byte ptr [rdx - 4] \n"
" 00001242 44/ 8A 4A 04 mov r9b, byte ptr [rdx + 4] \n"
" 00001246 66| 44/ 8B 4A mov r9w, word ptr [rdx + 4] \n"
" 04 \n"
" 0000124B 44/ 8B 4A 04 mov r9d, dword ptr [rdx + 4] \n"
" 0000124F 4C/ 8B 4A 04 mov r9, qword ptr [rdx + 4] \n"
" \n"
" 00001253 41/ 88 51 FC mov byte ptr [r9 - 4], dl \n"
" 00001257 41/ 88 51 04 mov byte ptr [r9 + 4], dl \n"
" 0000125B 66| 41/ 89 51 mov word ptr [r9 + 4], dx \n"
" 04 \n"
" 00001260 41/ 89 51 04 mov dword ptr [r9 + 4], edx \n"
" 00001264 49/ 89 51 04 mov qword ptr [r9 + 4], rdx \n"
" \n"
" 00001268 66| 44/ 0F B6 CA movzx r9w, dl \n"
" 0000126D 66| 44/ 0F B6 4A movzx r9w, byte ptr [rdx + 4] \n"
" 04 \n"
" \n"
" 00001273 44/ 0F B6 CA movzx r9d, dl \n"
" 00001277 44/ 0F B7 CA movzx r9d, dx \n"
" 0000127B 44/ 0F B6 4A movzx r9d, byte ptr [rdx + 4] \n"
" 04 \n"
" 00001280 44/ 0F B7 4A movzx r9d, word ptr [rdx + 4] \n"
" 04 \n"
" \n"
" 00001285 4C/ 0F B6 CA movzx r9, dl \n"
" 00001289 4C/ 0F B7 CA movzx r9, dx \n"
" 0000128D 4C/ 0F B6 4A movzx r9, byte ptr [rdx + 4] \n"
" 04 \n"
" 00001292 4C/ 0F B7 4A movzx r9, word ptr [rdx + 4] \n"
" 04 \n"
" \n"
" \n"
" ; Source: rdx, target: r10 \n"
" 00001297 41/ B2 01 mov r10b, 1 \n"
" 0000129A 66| 41/ BA mov r10w, 1 \n"
" 0001 \n"
" 0000129F 41/ BA mov r10d, 1 \n"
" 00000001 \n"
" 000012A5 49/ C7 C2 mov r10, 1 \n"
" 00000001 \n"
" \n"
" 000012AC 44/ 8A D2 mov r10b, dl \n"
" 000012AF 66| 44/ 8B D2 mov r10w, dx \n"
" 000012B3 44/ 8B D2 mov r10d, edx \n"
" 000012B6 4C/ 8B D2 mov r10, rdx \n"
" \n"
" 000012B9 44/ 8A 52 FC mov r10b, byte ptr [rdx - 4] \n"
" 000012BD 44/ 8A 52 04 mov r10b, byte ptr [rdx + 4] \n"
" 000012C1 66| 44/ 8B 52 mov r10w, word ptr [rdx + 4] \n"
" 04 \n"
" 000012C6 44/ 8B 52 04 mov r10d, dword ptr [rdx + 4] \n"
" 000012CA 4C/ 8B 52 04 mov r10, qword ptr [rdx + 4] \n"
" \n"
" 000012CE 41/ 88 52 FC mov byte ptr [r10 - 4], dl \n"
" 000012D2 41/ 88 52 04 mov byte ptr [r10 + 4], dl \n"
" 000012D6 66| 41/ 89 52 mov word ptr [r10 + 4], dx \n"
" 04 \n"
" 000012DB 41/ 89 52 04 mov dword ptr [r10 + 4], edx \n"
" 000012DF 49/ 89 52 04 mov qword ptr [r10 + 4], rdx \n"
" \n"
" 000012E3 66| 44/ 0F B6 D2 movzx r10w, dl \n"
" 000012E8 66| 44/ 0F B6 52 movzx r10w, byte ptr [rdx + 4] \n"
" 04 \n"
" \n"
" 000012EE 44/ 0F B6 D2 movzx r10d, dl \n"
" 000012F2 44/ 0F B7 D2 movzx r10d, dx \n"
" 000012F6 44/ 0F B6 52 movzx r10d, byte ptr [rdx + 4] \n"
" 04 \n"
" 000012FB 44/ 0F B7 52 movzx r10d, word ptr [rdx + 4] \n"
" 04 \n"
" \n"
" 00001300 4C/ 0F B6 D2 movzx r10, dl \n"
" 00001304 4C/ 0F B7 D2 movzx r10, dx \n"
" 00001308 4C/ 0F B6 52 movzx r10, byte ptr [rdx + 4] \n"
" 04 \n"
" 0000130D 4C/ 0F B7 52 movzx r10, word ptr [rdx + 4] \n"
" 04 \n"
" \n"
" \n"
" ; Source: rdx, target: r11 \n"
" 00001312 41/ B3 01 mov r11b, 1 \n"
" 00001315 66| 41/ BB mov r11w, 1 \n"
" 0001 \n"
" 0000131A 41/ BB mov r11d, 1 \n"
" 00000001 \n"
" 00001320 49/ C7 C3 mov r11, 1 \n"
" 00000001 \n"
" \n"
" 00001327 44/ 8A DA mov r11b, dl \n"
" 0000132A 66| 44/ 8B DA mov r11w, dx \n"
" 0000132E 44/ 8B DA mov r11d, edx \n"
" 00001331 4C/ 8B DA mov r11, rdx \n"
" \n"
" 00001334 44/ 8A 5A FC mov r11b, byte ptr [rdx - 4] \n"
" 00001338 44/ 8A 5A 04 mov r11b, byte ptr [rdx + 4] \n"
" 0000133C 66| 44/ 8B 5A mov r11w, word ptr [rdx + 4] \n"
" 04 \n"
" 00001341 44/ 8B 5A 04 mov r11d, dword ptr [rdx + 4] \n"
" 00001345 4C/ 8B 5A 04 mov r11, qword ptr [rdx + 4] \n"
" \n"
" 00001349 41/ 88 53 FC mov byte ptr [r11 - 4], dl \n"
" 0000134D 41/ 88 53 04 mov byte ptr [r11 + 4], dl \n"
" 00001351 66| 41/ 89 53 mov word ptr [r11 + 4], dx \n"
" 04 \n"
" 00001356 41/ 89 53 04 mov dword ptr [r11 + 4], edx \n"
" 0000135A 49/ 89 53 04 mov qword ptr [r11 + 4], rdx \n"
" \n"
" 0000135E 66| 44/ 0F B6 DA movzx r11w, dl \n"
" 00001363 66| 44/ 0F B6 5A movzx r11w, byte ptr [rdx + 4] \n"
" 04 \n"
" \n"
" 00001369 44/ 0F B6 DA movzx r11d, dl \n"
" 0000136D 44/ 0F B7 DA movzx r11d, dx \n"
" 00001371 44/ 0F B6 5A movzx r11d, byte ptr [rdx + 4] \n"
" 04 \n"
" 00001376 44/ 0F B7 5A movzx r11d, word ptr [rdx + 4] \n"
" 04 \n"
" \n"
" 0000137B 4C/ 0F B6 DA movzx r11, dl \n"
" 0000137F 4C/ 0F B7 DA movzx r11, dx \n"
" 00001383 4C/ 0F B6 5A movzx r11, byte ptr [rdx + 4] \n"
" 04 \n"
" 00001388 4C/ 0F B7 5A movzx r11, word ptr [rdx + 4] \n"
" 04 \n"
" \n"
" \n"
" ; Source: rdx, target: r12 \n"
" 0000138D 41/ B4 01 mov r12b, 1 \n"
" 00001390 66| 41/ BC mov r12w, 1 \n"
" 0001 \n"
" 00001395 41/ BC mov r12d, 1 \n"
" 00000001 \n"
" 0000139B 49/ C7 C4 mov r12, 1 \n"
" 00000001 \n"
" \n"
" 000013A2 44/ 8A E2 mov r12b, dl \n"
" 000013A5 66| 44/ 8B E2 mov r12w, dx \n"
" 000013A9 44/ 8B E2 mov r12d, edx \n"
" 000013AC 4C/ 8B E2 mov r12, rdx \n"
" \n"
" 000013AF 44/ 8A 62 FC mov r12b, byte ptr [rdx - 4] \n"
" 000013B3 44/ 8A 62 04 mov r12b, byte ptr [rdx + 4] \n"
" 000013B7 66| 44/ 8B 62 mov r12w, word ptr [rdx + 4] \n"
" 04 \n"
" 000013BC 44/ 8B 62 04 mov r12d, dword ptr [rdx + 4] \n"
" 000013C0 4C/ 8B 62 04 mov r12, qword ptr [rdx + 4] \n"
" \n"
" 000013C4 41/ 88 54 24 mov byte ptr [r12 - 4], dl \n"
" FC \n"
" 000013C9 41/ 88 54 24 mov byte ptr [r12 + 4], dl \n"
" 04 \n"
" 000013CE 66| 41/ 89 54 24 mov word ptr [r12 + 4], dx \n"
" 04 \n"
" 000013D4 41/ 89 54 24 mov dword ptr [r12 + 4], edx \n"
" 04 \n"
" 000013D9 49/ 89 54 24 mov qword ptr [r12 + 4], rdx \n"
" 04 \n"
" \n"
" 000013DE 66| 44/ 0F B6 E2 movzx r12w, dl \n"
" 000013E3 66| 44/ 0F B6 62 movzx r12w, byte ptr [rdx + 4] \n"
" 04 \n"
" \n"
" 000013E9 44/ 0F B6 E2 movzx r12d, dl \n"
" 000013ED 44/ 0F B7 E2 movzx r12d, dx \n"
" 000013F1 44/ 0F B6 62 movzx r12d, byte ptr [rdx + 4] \n"
" 04 \n"
" 000013F6 44/ 0F B7 62 movzx r12d, word ptr [rdx + 4] \n"
" 04 \n"
" \n"
" 000013FB 4C/ 0F B6 E2 movzx r12, dl \n"
" 000013FF 4C/ 0F B7 E2 movzx r12, dx \n"
" 00001403 4C/ 0F B6 62 movzx r12, byte ptr [rdx + 4] \n"
" 04 \n"
" 00001408 4C/ 0F B7 62 movzx r12, word ptr [rdx + 4] \n"
" 04 \n"
" \n"
" \n"
" ; Source: rdx, target: r13 \n"
" 0000140D 41/ B5 01 mov r13b, 1 \n"
" 00001410 66| 41/ BD mov r13w, 1 \n"
" 0001 \n"
" 00001415 41/ BD mov r13d, 1 \n"
" 00000001 \n"
" 0000141B 49/ C7 C5 mov r13, 1 \n"
" 00000001 \n"
" \n"
" 00001422 44/ 8A EA mov r13b, dl \n"
" 00001425 66| 44/ 8B EA mov r13w, dx \n"
" 00001429 44/ 8B EA mov r13d, edx \n"
" 0000142C 4C/ 8B EA mov r13, rdx \n"
" \n"
" 0000142F 44/ 8A 6A FC mov r13b, byte ptr [rdx - 4] \n"
" 00001433 44/ 8A 6A 04 mov r13b, byte ptr [rdx + 4] \n"
" 00001437 66| 44/ 8B 6A mov r13w, word ptr [rdx + 4] \n"
" 04 \n"
" 0000143C 44/ 8B 6A 04 mov r13d, dword ptr [rdx + 4] \n"
" 00001440 4C/ 8B 6A 04 mov r13, qword ptr [rdx + 4] \n"
" \n"
" 00001444 41/ 88 55 FC mov byte ptr [r13 - 4], dl \n"
" 00001448 41/ 88 55 04 mov byte ptr [r13 + 4], dl \n"
" 0000144C 66| 41/ 89 55 mov word ptr [r13 + 4], dx \n"
" 04 \n"
" 00001451 41/ 89 55 04 mov dword ptr [r13 + 4], edx \n"
" 00001455 49/ 89 55 04 mov qword ptr [r13 + 4], rdx \n"
" \n"
" 00001459 66| 44/ 0F B6 EA movzx r13w, dl \n"
" 0000145E 66| 44/ 0F B6 6A movzx r13w, byte ptr [rdx + 4] \n"
" 04 \n"
" \n"
" 00001464 44/ 0F B6 EA movzx r13d, dl \n"
" 00001468 44/ 0F B7 EA movzx r13d, dx \n"
" 0000146C 44/ 0F B6 6A movzx r13d, byte ptr [rdx + 4] \n"
" 04 \n"
" 00001471 44/ 0F B7 6A movzx r13d, word ptr [rdx + 4] \n"
" 04 \n"
" \n"
" 00001476 4C/ 0F B6 EA movzx r13, dl \n"
" 0000147A 4C/ 0F B7 EA movzx r13, dx \n"
" 0000147E 4C/ 0F B6 6A movzx r13, byte ptr [rdx + 4] \n"
" 04 \n"
" 00001483 4C/ 0F B7 6A movzx r13, word ptr [rdx + 4] \n"
" 04 \n"
" \n"
" \n"
" ; Source: rdx, target: r14 \n"
" 00001488 41/ B6 01 mov r14b, 1 \n"
" 0000148B 66| 41/ BE mov r14w, 1 \n"
" 0001 \n"
" 00001490 41/ BE mov r14d, 1 \n"
" 00000001 \n"
" 00001496 49/ C7 C6 mov r14, 1 \n"
" 00000001 \n"
" \n"
" 0000149D 44/ 8A F2 mov r14b, dl \n"
" 000014A0 66| 44/ 8B F2 mov r14w, dx \n"
" 000014A4 44/ 8B F2 mov r14d, edx \n"
" 000014A7 4C/ 8B F2 mov r14, rdx \n"
" \n"
" 000014AA 44/ 8A 72 FC mov r14b, byte ptr [rdx - 4] \n"
" 000014AE 44/ 8A 72 04 mov r14b, byte ptr [rdx + 4] \n"
" 000014B2 66| 44/ 8B 72 mov r14w, word ptr [rdx + 4] \n"
" 04 \n"
" 000014B7 44/ 8B 72 04 mov r14d, dword ptr [rdx + 4] \n"
" 000014BB 4C/ 8B 72 04 mov r14, qword ptr [rdx + 4] \n"
" \n"
" 000014BF 41/ 88 56 FC mov byte ptr [r14 - 4], dl \n"
" 000014C3 41/ 88 56 04 mov byte ptr [r14 + 4], dl \n"
" 000014C7 66| 41/ 89 56 mov word ptr [r14 + 4], dx \n"
" 04 \n"
" 000014CC 41/ 89 56 04 mov dword ptr [r14 + 4], edx \n"
" 000014D0 49/ 89 56 04 mov qword ptr [r14 + 4], rdx \n"
" \n"
" 000014D4 66| 44/ 0F B6 F2 movzx r14w, dl \n"
" 000014D9 66| 44/ 0F B6 72 movzx r14w, byte ptr [rdx + 4] \n"
" 04 \n"
" \n"
" 000014DF 44/ 0F B6 F2 movzx r14d, dl \n"
" 000014E3 44/ 0F B7 F2 movzx r14d, dx \n"
" 000014E7 44/ 0F B6 72 movzx r14d, byte ptr [rdx + 4] \n"
" 04 \n"
" 000014EC 44/ 0F B7 72 movzx r14d, word ptr [rdx + 4] \n"
" 04 \n"
" \n"
" 000014F1 4C/ 0F B6 F2 movzx r14, dl \n"
" 000014F5 4C/ 0F B7 F2 movzx r14, dx \n"
" 000014F9 4C/ 0F B6 72 movzx r14, byte ptr [rdx + 4] \n"
" 04 \n"
" 000014FE 4C/ 0F B7 72 movzx r14, word ptr [rdx + 4] \n"
" 04 \n"
" \n"
" \n"
" ; Source: rdx, target: r15 \n"
" 00001503 41/ B7 01 mov r15b, 1 \n"
" 00001506 66| 41/ BF mov r15w, 1 \n"
" 0001 \n"
" 0000150B 41/ BF mov r15d, 1 \n"
" 00000001 \n"
" 00001511 49/ C7 C7 mov r15, 1 \n"
" 00000001 \n"
" \n"
" 00001518 44/ 8A FA mov r15b, dl \n"
" 0000151B 66| 44/ 8B FA mov r15w, dx \n"
" 0000151F 44/ 8B FA mov r15d, edx \n"
" 00001522 4C/ 8B FA mov r15, rdx \n"
" \n"
" 00001525 44/ 8A 7A FC mov r15b, byte ptr [rdx - 4] \n"
" 00001529 44/ 8A 7A 04 mov r15b, byte ptr [rdx + 4] \n"
" 0000152D 66| 44/ 8B 7A mov r15w, word ptr [rdx + 4] \n"
" 04 \n"
" 00001532 44/ 8B 7A 04 mov r15d, dword ptr [rdx + 4] \n"
" 00001536 4C/ 8B 7A 04 mov r15, qword ptr [rdx + 4] \n"
" \n"
" 0000153A 41/ 88 57 FC mov byte ptr [r15 - 4], dl \n"
" 0000153E 41/ 88 57 04 mov byte ptr [r15 + 4], dl \n"
" 00001542 66| 41/ 89 57 mov word ptr [r15 + 4], dx \n"
" 04 \n"
" 00001547 41/ 89 57 04 mov dword ptr [r15 + 4], edx \n"
" 0000154B 49/ 89 57 04 mov qword ptr [r15 + 4], rdx \n"
" \n"
" 0000154F 66| 44/ 0F B6 FA movzx r15w, dl \n"
" 00001554 66| 44/ 0F B6 7A movzx r15w, byte ptr [rdx + 4] \n"
" 04 \n"
" \n"
" 0000155A 44/ 0F B6 FA movzx r15d, dl \n"
" 0000155E 44/ 0F B7 FA movzx r15d, dx \n"
" 00001562 44/ 0F B6 7A movzx r15d, byte ptr [rdx + 4] \n"
" 04 \n"
" 00001567 44/ 0F B7 7A movzx r15d, word ptr [rdx + 4] \n"
" 04 \n"
" \n"
" 0000156C 4C/ 0F B6 FA movzx r15, dl \n"
" 00001570 4C/ 0F B7 FA movzx r15, dx \n"
" 00001574 4C/ 0F B6 7A movzx r15, byte ptr [rdx + 4] \n"
" 04 \n"
" 00001579 4C/ 0F B7 7A movzx r15, word ptr [rdx + 4] \n"
" 04 \n"
" \n"
" \n"
" ; Source: rbx, target: rax \n"
" 0000157E B0 01 mov al, 1 \n"
" 00001580 66| B8 0001 mov ax, 1 \n"
" 00001584 B8 00000001 mov eax, 1 \n"
" 00001589 48/ C7 C0 mov rax, 1 \n"
" 00000001 \n"
" \n"
" 00001590 8A C3 mov al, bl \n"
" 00001592 66| 8B C3 mov ax, bx \n"
" 00001595 8B C3 mov eax, ebx \n"
" 00001597 48/ 8B C3 mov rax, rbx \n"
" \n"
" 0000159A 8A 43 FC mov al, byte ptr [rbx - 4] \n"
" 0000159D 8A 43 04 mov al, byte ptr [rbx + 4] \n"
" 000015A0 66| 8B 43 04 mov ax, word ptr [rbx + 4] \n"
" 000015A4 8B 43 04 mov eax, dword ptr [rbx + 4] \n"
" 000015A7 48/ 8B 43 04 mov rax, qword ptr [rbx + 4] \n"
" \n"
" 000015AB 88 58 FC mov byte ptr [rax - 4], bl \n"
" 000015AE 88 58 04 mov byte ptr [rax + 4], bl \n"
" 000015B1 66| 89 58 04 mov word ptr [rax + 4], bx \n"
" 000015B5 89 58 04 mov dword ptr [rax + 4], ebx \n"
" 000015B8 48/ 89 58 04 mov qword ptr [rax + 4], rbx \n"
" \n"
" 000015BC 66| 0F B6 C3 movzx ax, bl \n"
" 000015C0 66| 0F B6 43 movzx ax, byte ptr [rbx + 4] \n"
" 04 \n"
" \n"
" 000015C5 0F B6 C3 movzx eax, bl \n"
" 000015C8 0F B7 C3 movzx eax, bx \n"
" 000015CB 0F B6 43 04 movzx eax, byte ptr [rbx + 4] \n"
" 000015CF 0F B7 43 04 movzx eax, word ptr [rbx + 4] \n"
" \n"
" 000015D3 48/ 0F B6 C3 movzx rax, bl \n"
" 000015D7 48/ 0F B7 C3 movzx rax, bx \n"
" 000015DB 48/ 0F B6 43 movzx rax, byte ptr [rbx + 4] \n"
" 04 \n"
" 000015E0 48/ 0F B7 43 movzx rax, word ptr [rbx + 4] \n"
" 04 \n"
" \n"
" \n"
" ; Source: rbx, target: rcx \n"
" 000015E5 B1 01 mov cl, 1 \n"
" 000015E7 66| B9 0001 mov cx, 1 \n"
" 000015EB B9 00000001 mov ecx, 1 \n"
" 000015F0 48/ C7 C1 mov rcx, 1 \n"
" 00000001 \n"
" \n"
" 000015F7 8A CB mov cl, bl \n"
" 000015F9 66| 8B CB mov cx, bx \n"
" 000015FC 8B CB mov ecx, ebx \n"
" 000015FE 48/ 8B CB mov rcx, rbx \n"
" \n"
" 00001601 8A 4B FC mov cl, byte ptr [rbx - 4] \n"
" 00001604 8A 4B 04 mov cl, byte ptr [rbx + 4] \n"
" 00001607 66| 8B 4B 04 mov cx, word ptr [rbx + 4] \n"
" 0000160B 8B 4B 04 mov ecx, dword ptr [rbx + 4] \n"
" 0000160E 48/ 8B 4B 04 mov rcx, qword ptr [rbx + 4] \n"
" \n"
" 00001612 88 59 FC mov byte ptr [rcx - 4], bl \n";
ml64Output +=
" 00001615 88 59 04 mov byte ptr [rcx + 4], bl \n"
" 00001618 66| 89 59 04 mov word ptr [rcx + 4], bx \n"
" 0000161C 89 59 04 mov dword ptr [rcx + 4], ebx \n"
" 0000161F 48/ 89 59 04 mov qword ptr [rcx + 4], rbx \n"
" \n"
" 00001623 66| 0F B6 CB movzx cx, bl \n"
" 00001627 66| 0F B6 4B movzx cx, byte ptr [rbx + 4] \n"
" 04 \n"
" \n"
" 0000162C 0F B6 CB movzx ecx, bl \n"
" 0000162F 0F B7 CB movzx ecx, bx \n"
" 00001632 0F B6 4B 04 movzx ecx, byte ptr [rbx + 4] \n"
" 00001636 0F B7 4B 04 movzx ecx, word ptr [rbx + 4] \n"
" \n"
" 0000163A 48/ 0F B6 CB movzx rcx, bl \n"
" 0000163E 48/ 0F B7 CB movzx rcx, bx \n"
" 00001642 48/ 0F B6 4B movzx rcx, byte ptr [rbx + 4] \n"
" 04 \n"
" 00001647 48/ 0F B7 4B movzx rcx, word ptr [rbx + 4] \n"
" 04 \n"
" \n"
" \n"
" ; Source: rbx, target: rdx \n"
" 0000164C B2 01 mov dl, 1 \n"
" 0000164E 66| BA 0001 mov dx, 1 \n"
" 00001652 BA 00000001 mov edx, 1 \n"
" 00001657 48/ C7 C2 mov rdx, 1 \n"
" 00000001 \n"
" \n"
" 0000165E 8A D3 mov dl, bl \n"
" 00001660 66| 8B D3 mov dx, bx \n"
" 00001663 8B D3 mov edx, ebx \n"
" 00001665 48/ 8B D3 mov rdx, rbx \n"
" \n"
" 00001668 8A 53 FC mov dl, byte ptr [rbx - 4] \n"
" 0000166B 8A 53 04 mov dl, byte ptr [rbx + 4] \n"
" 0000166E 66| 8B 53 04 mov dx, word ptr [rbx + 4] \n"
" 00001672 8B 53 04 mov edx, dword ptr [rbx + 4] \n"
" 00001675 48/ 8B 53 04 mov rdx, qword ptr [rbx + 4] \n"
" \n"
" 00001679 88 5A FC mov byte ptr [rdx - 4], bl \n"
" 0000167C 88 5A 04 mov byte ptr [rdx + 4], bl \n"
" 0000167F 66| 89 5A 04 mov word ptr [rdx + 4], bx \n"
" 00001683 89 5A 04 mov dword ptr [rdx + 4], ebx \n"
" 00001686 48/ 89 5A 04 mov qword ptr [rdx + 4], rbx \n"
" \n"
" 0000168A 66| 0F B6 D3 movzx dx, bl \n"
" 0000168E 66| 0F B6 53 movzx dx, byte ptr [rbx + 4] \n"
" 04 \n"
" \n"
" 00001693 0F B6 D3 movzx edx, bl \n"
" 00001696 0F B7 D3 movzx edx, bx \n"
" 00001699 0F B6 53 04 movzx edx, byte ptr [rbx + 4] \n"
" 0000169D 0F B7 53 04 movzx edx, word ptr [rbx + 4] \n"
" \n"
" 000016A1 48/ 0F B6 D3 movzx rdx, bl \n"
" 000016A5 48/ 0F B7 D3 movzx rdx, bx \n"
" 000016A9 48/ 0F B6 53 movzx rdx, byte ptr [rbx + 4] \n"
" 04 \n"
" 000016AE 48/ 0F B7 53 movzx rdx, word ptr [rbx + 4] \n"
" 04 \n"
" \n"
" \n"
" ; Source: rbx, target: rbx \n"
" 000016B3 B3 01 mov bl, 1 \n"
" 000016B5 66| BB 0001 mov bx, 1 \n"
" 000016B9 BB 00000001 mov ebx, 1 \n"
" 000016BE 48/ C7 C3 mov rbx, 1 \n"
" 00000001 \n"
" \n"
" 000016C5 8A DB mov bl, bl \n"
" 000016C7 66| 8B DB mov bx, bx \n"
" 000016CA 8B DB mov ebx, ebx \n"
" 000016CC 48/ 8B DB mov rbx, rbx \n"
" \n"
" 000016CF 8A 5B FC mov bl, byte ptr [rbx - 4] \n"
" 000016D2 8A 5B 04 mov bl, byte ptr [rbx + 4] \n"
" 000016D5 66| 8B 5B 04 mov bx, word ptr [rbx + 4] \n"
" 000016D9 8B 5B 04 mov ebx, dword ptr [rbx + 4] \n"
" 000016DC 48/ 8B 5B 04 mov rbx, qword ptr [rbx + 4] \n"
" \n"
" 000016E0 88 5B FC mov byte ptr [rbx - 4], bl \n"
" 000016E3 88 5B 04 mov byte ptr [rbx + 4], bl \n"
" 000016E6 66| 89 5B 04 mov word ptr [rbx + 4], bx \n"
" 000016EA 89 5B 04 mov dword ptr [rbx + 4], ebx \n"
" 000016ED 48/ 89 5B 04 mov qword ptr [rbx + 4], rbx \n"
" \n"
" 000016F1 66| 0F B6 DB movzx bx, bl \n"
" 000016F5 66| 0F B6 5B movzx bx, byte ptr [rbx + 4] \n"
" 04 \n"
" \n"
" 000016FA 0F B6 DB movzx ebx, bl \n"
" 000016FD 0F B7 DB movzx ebx, bx \n"
" 00001700 0F B6 5B 04 movzx ebx, byte ptr [rbx + 4] \n"
" 00001704 0F B7 5B 04 movzx ebx, word ptr [rbx + 4] \n"
" \n"
" 00001708 48/ 0F B6 DB movzx rbx, bl \n"
" 0000170C 48/ 0F B7 DB movzx rbx, bx \n"
" 00001710 48/ 0F B6 5B movzx rbx, byte ptr [rbx + 4] \n"
" 04 \n"
" 00001715 48/ 0F B7 5B movzx rbx, word ptr [rbx + 4] \n"
" 04 \n"
" \n"
" \n"
" ; Source: rbx, target: rsp \n"
" 0000171A 40/ B4 01 mov spl, 1 \n"
" 0000171D 66| BC 0001 mov sp, 1 \n"
" 00001721 BC 00000001 mov esp, 1 \n"
" 00001726 48/ C7 C4 mov rsp, 1 \n"
" 00000001 \n"
" \n"
" 0000172D 40/ 8A E3 mov spl, bl \n"
" 00001730 66| 8B E3 mov sp, bx \n"
" 00001733 8B E3 mov esp, ebx \n"
" 00001735 48/ 8B E3 mov rsp, rbx \n"
" \n"
" 00001738 40/ 8A 63 FC mov spl, byte ptr [rbx - 4] \n"
" 0000173C 40/ 8A 63 04 mov spl, byte ptr [rbx + 4] \n"
" 00001740 66| 8B 63 04 mov sp, word ptr [rbx + 4] \n"
" 00001744 8B 63 04 mov esp, dword ptr [rbx + 4] \n"
" 00001747 48/ 8B 63 04 mov rsp, qword ptr [rbx + 4] \n"
" \n"
" 0000174B 88 5C 24 FC mov byte ptr [rsp - 4], bl \n"
" 0000174F 88 5C 24 04 mov byte ptr [rsp + 4], bl \n"
" 00001753 66| 89 5C 24 mov word ptr [rsp + 4], bx \n"
" 04 \n"
" 00001758 89 5C 24 04 mov dword ptr [rsp + 4], ebx \n"
" 0000175C 48/ 89 5C 24 mov qword ptr [rsp + 4], rbx \n"
" 04 \n"
" \n"
" 00001761 66| 0F B6 E3 movzx sp, bl \n"
" 00001765 66| 0F B6 63 movzx sp, byte ptr [rbx + 4] \n"
" 04 \n"
" \n"
" 0000176A 0F B6 E3 movzx esp, bl \n"
" 0000176D 0F B7 E3 movzx esp, bx \n"
" 00001770 0F B6 63 04 movzx esp, byte ptr [rbx + 4] \n"
" 00001774 0F B7 63 04 movzx esp, word ptr [rbx + 4] \n"
" \n"
" 00001778 48/ 0F B6 E3 movzx rsp, bl \n"
" 0000177C 48/ 0F B7 E3 movzx rsp, bx \n"
" 00001780 48/ 0F B6 63 movzx rsp, byte ptr [rbx + 4] \n"
" 04 \n"
" 00001785 48/ 0F B7 63 movzx rsp, word ptr [rbx + 4] \n"
" 04 \n"
" \n"
" \n"
" ; Source: rbx, target: rbp \n"
" 0000178A 40/ B5 01 mov bpl, 1 \n"
" 0000178D 66| BD 0001 mov bp, 1 \n"
" 00001791 BD 00000001 mov ebp, 1 \n"
" 00001796 48/ C7 C5 mov rbp, 1 \n"
" 00000001 \n"
" \n"
" 0000179D 40/ 8A EB mov bpl, bl \n"
" 000017A0 66| 8B EB mov bp, bx \n"
" 000017A3 8B EB mov ebp, ebx \n"
" 000017A5 48/ 8B EB mov rbp, rbx \n"
" \n"
" 000017A8 40/ 8A 6B FC mov bpl, byte ptr [rbx - 4] \n"
" 000017AC 40/ 8A 6B 04 mov bpl, byte ptr [rbx + 4] \n"
" 000017B0 66| 8B 6B 04 mov bp, word ptr [rbx + 4] \n"
" 000017B4 8B 6B 04 mov ebp, dword ptr [rbx + 4] \n"
" 000017B7 48/ 8B 6B 04 mov rbp, qword ptr [rbx + 4] \n"
" \n"
" 000017BB 88 5D FC mov byte ptr [rbp - 4], bl \n"
" 000017BE 88 5D 04 mov byte ptr [rbp + 4], bl \n"
" 000017C1 66| 89 5D 04 mov word ptr [rbp + 4], bx \n"
" 000017C5 89 5D 04 mov dword ptr [rbp + 4], ebx \n"
" 000017C8 48/ 89 5D 04 mov qword ptr [rbp + 4], rbx \n"
" \n"
" 000017CC 66| 0F B6 EB movzx bp, bl \n"
" 000017D0 66| 0F B6 6B movzx bp, byte ptr [rbx + 4] \n"
" 04 \n"
" \n"
" 000017D5 0F B6 EB movzx ebp, bl \n"
" 000017D8 0F B7 EB movzx ebp, bx \n"
" 000017DB 0F B6 6B 04 movzx ebp, byte ptr [rbx + 4] \n"
" 000017DF 0F B7 6B 04 movzx ebp, word ptr [rbx + 4] \n"
" \n"
" 000017E3 48/ 0F B6 EB movzx rbp, bl \n"
" 000017E7 48/ 0F B7 EB movzx rbp, bx \n"
" 000017EB 48/ 0F B6 6B movzx rbp, byte ptr [rbx + 4] \n"
" 04 \n"
" 000017F0 48/ 0F B7 6B movzx rbp, word ptr [rbx + 4] \n"
" 04 \n"
" \n"
" \n"
" ; Source: rbx, target: rsi \n"
" 000017F5 40/ B7 01 mov dil, 1 \n"
" 000017F8 66| BE 0001 mov si, 1 \n"
" 000017FC BE 00000001 mov esi, 1 \n"
" 00001801 48/ C7 C6 mov rsi, 1 \n"
" 00000001 \n"
" \n"
" 00001808 40/ 8A FB mov dil, bl \n"
" 0000180B 66| 8B F3 mov si, bx \n"
" 0000180E 8B F3 mov esi, ebx \n"
" 00001810 48/ 8B F3 mov rsi, rbx \n"
" \n"
" 00001813 40/ 8A 7B FC mov dil, byte ptr [rbx - 4] \n"
" 00001817 40/ 8A 7B 04 mov dil, byte ptr [rbx + 4] \n"
" 0000181B 66| 8B 73 04 mov si, word ptr [rbx + 4] \n"
" 0000181F 8B 73 04 mov esi, dword ptr [rbx + 4] \n"
" 00001822 48/ 8B 73 04 mov rsi, qword ptr [rbx + 4] \n"
" \n"
" 00001826 88 5E FC mov byte ptr [rsi - 4], bl \n"
" 00001829 88 5E 04 mov byte ptr [rsi + 4], bl \n"
" 0000182C 66| 89 5E 04 mov word ptr [rsi + 4], bx \n"
" 00001830 89 5E 04 mov dword ptr [rsi + 4], ebx \n"
" 00001833 48/ 89 5E 04 mov qword ptr [rsi + 4], rbx \n"
" \n"
" 00001837 66| 0F B6 F3 movzx si, bl \n"
" 0000183B 66| 0F B6 73 movzx si, byte ptr [rbx + 4] \n"
" 04 \n"
" \n"
" 00001840 0F B6 F3 movzx esi, bl \n"
" 00001843 0F B7 F3 movzx esi, bx \n"
" 00001846 0F B6 73 04 movzx esi, byte ptr [rbx + 4] \n"
" 0000184A 0F B7 73 04 movzx esi, word ptr [rbx + 4] \n"
" \n"
" 0000184E 48/ 0F B6 F3 movzx rsi, bl \n"
" 00001852 48/ 0F B7 F3 movzx rsi, bx \n"
" 00001856 48/ 0F B6 73 movzx rsi, byte ptr [rbx + 4] \n"
" 04 \n"
" 0000185B 48/ 0F B7 73 movzx rsi, word ptr [rbx + 4] \n"
" 04 \n"
" \n"
" \n"
" ; Source: rbx, target: rdi \n"
" 00001860 40/ B6 01 mov sil, 1 \n"
" 00001863 66| BF 0001 mov di, 1 \n"
" 00001867 BF 00000001 mov edi, 1 \n"
" 0000186C 48/ C7 C7 mov rdi, 1 \n"
" 00000001 \n"
" \n"
" 00001873 40/ 8A F3 mov sil, bl \n"
" 00001876 66| 8B FB mov di, bx \n"
" 00001879 8B FB mov edi, ebx \n"
" 0000187B 48/ 8B FB mov rdi, rbx \n"
" \n"
" 0000187E 40/ 8A 73 FC mov sil, byte ptr [rbx - 4] \n"
" 00001882 40/ 8A 73 04 mov sil, byte ptr [rbx + 4] \n"
" 00001886 66| 8B 7B 04 mov di, word ptr [rbx + 4] \n"
" 0000188A 8B 7B 04 mov edi, dword ptr [rbx + 4] \n"
" 0000188D 48/ 8B 7B 04 mov rdi, qword ptr [rbx + 4] \n"
" \n"
" 00001891 88 5F FC mov byte ptr [rdi - 4], bl \n"
" 00001894 88 5F 04 mov byte ptr [rdi + 4], bl \n"
" 00001897 66| 89 5F 04 mov word ptr [rdi + 4], bx \n"
" 0000189B 89 5F 04 mov dword ptr [rdi + 4], ebx \n"
" 0000189E 48/ 89 5F 04 mov qword ptr [rdi + 4], rbx \n"
" \n"
" 000018A2 66| 0F B6 FB movzx di, bl \n"
" 000018A6 66| 0F B6 7B movzx di, byte ptr [rbx + 4] \n"
" 04 \n"
" \n"
" 000018AB 0F B6 FB movzx edi, bl \n"
" 000018AE 0F B7 FB movzx edi, bx \n"
" 000018B1 0F B6 7B 04 movzx edi, byte ptr [rbx + 4] \n"
" 000018B5 0F B7 7B 04 movzx edi, word ptr [rbx + 4] \n"
" \n"
" 000018B9 48/ 0F B6 FB movzx rdi, bl \n"
" 000018BD 48/ 0F B7 FB movzx rdi, bx \n"
" 000018C1 48/ 0F B6 7B movzx rdi, byte ptr [rbx + 4] \n"
" 04 \n"
" 000018C6 48/ 0F B7 7B movzx rdi, word ptr [rbx + 4] \n"
" 04 \n"
" \n"
" \n"
" ; Source: rbx, target: r8 \n"
" 000018CB 41/ B0 01 mov r8b, 1 \n"
" 000018CE 66| 41/ B8 mov r8w, 1 \n"
" 0001 \n"
" 000018D3 41/ B8 mov r8d, 1 \n"
" 00000001 \n"
" 000018D9 49/ C7 C0 mov r8, 1 \n"
" 00000001 \n"
" \n"
" 000018E0 44/ 8A C3 mov r8b, bl \n"
" 000018E3 66| 44/ 8B C3 mov r8w, bx \n"
" 000018E7 44/ 8B C3 mov r8d, ebx \n"
" 000018EA 4C/ 8B C3 mov r8, rbx \n"
" \n"
" 000018ED 44/ 8A 43 FC mov r8b, byte ptr [rbx - 4] \n"
" 000018F1 44/ 8A 43 04 mov r8b, byte ptr [rbx + 4] \n"
" 000018F5 66| 44/ 8B 43 mov r8w, word ptr [rbx + 4] \n"
" 04 \n"
" 000018FA 44/ 8B 43 04 mov r8d, dword ptr [rbx + 4] \n"
" 000018FE 4C/ 8B 43 04 mov r8, qword ptr [rbx + 4] \n"
" \n"
" 00001902 41/ 88 58 FC mov byte ptr [r8 - 4], bl \n"
" 00001906 41/ 88 58 04 mov byte ptr [r8 + 4], bl \n"
" 0000190A 66| 41/ 89 58 mov word ptr [r8 + 4], bx \n"
" 04 \n"
" 0000190F 41/ 89 58 04 mov dword ptr [r8 + 4], ebx \n"
" 00001913 49/ 89 58 04 mov qword ptr [r8 + 4], rbx \n"
" \n"
" 00001917 66| 44/ 0F B6 C3 movzx r8w, bl \n"
" 0000191C 66| 44/ 0F B6 43 movzx r8w, byte ptr [rbx + 4] \n"
" 04 \n"
" \n"
" 00001922 44/ 0F B6 C3 movzx r8d, bl \n"
" 00001926 44/ 0F B7 C3 movzx r8d, bx \n"
" 0000192A 44/ 0F B6 43 movzx r8d, byte ptr [rbx + 4] \n"
" 04 \n"
" 0000192F 44/ 0F B7 43 movzx r8d, word ptr [rbx + 4] \n"
" 04 \n"
" \n"
" 00001934 4C/ 0F B6 C3 movzx r8, bl \n"
" 00001938 4C/ 0F B7 C3 movzx r8, bx \n"
" 0000193C 4C/ 0F B6 43 movzx r8, byte ptr [rbx + 4] \n"
" 04 \n"
" 00001941 4C/ 0F B7 43 movzx r8, word ptr [rbx + 4] \n"
" 04 \n"
" \n"
" \n"
" ; Source: rbx, target: r9 \n"
" 00001946 41/ B1 01 mov r9b, 1 \n"
" 00001949 66| 41/ B9 mov r9w, 1 \n"
" 0001 \n"
" 0000194E 41/ B9 mov r9d, 1 \n"
" 00000001 \n"
" 00001954 49/ C7 C1 mov r9, 1 \n"
" 00000001 \n"
" \n"
" 0000195B 44/ 8A CB mov r9b, bl \n"
" 0000195E 66| 44/ 8B CB mov r9w, bx \n"
" 00001962 44/ 8B CB mov r9d, ebx \n"
" 00001965 4C/ 8B CB mov r9, rbx \n"
" \n"
" 00001968 44/ 8A 4B FC mov r9b, byte ptr [rbx - 4] \n"
" 0000196C 44/ 8A 4B 04 mov r9b, byte ptr [rbx + 4] \n"
" 00001970 66| 44/ 8B 4B mov r9w, word ptr [rbx + 4] \n"
" 04 \n"
" 00001975 44/ 8B 4B 04 mov r9d, dword ptr [rbx + 4] \n"
" 00001979 4C/ 8B 4B 04 mov r9, qword ptr [rbx + 4] \n"
" \n"
" 0000197D 41/ 88 59 FC mov byte ptr [r9 - 4], bl \n"
" 00001981 41/ 88 59 04 mov byte ptr [r9 + 4], bl \n"
" 00001985 66| 41/ 89 59 mov word ptr [r9 + 4], bx \n"
" 04 \n"
" 0000198A 41/ 89 59 04 mov dword ptr [r9 + 4], ebx \n"
" 0000198E 49/ 89 59 04 mov qword ptr [r9 + 4], rbx \n"
" \n"
" 00001992 66| 44/ 0F B6 CB movzx r9w, bl \n"
" 00001997 66| 44/ 0F B6 4B movzx r9w, byte ptr [rbx + 4] \n"
" 04 \n"
" \n"
" 0000199D 44/ 0F B6 CB movzx r9d, bl \n"
" 000019A1 44/ 0F B7 CB movzx r9d, bx \n"
" 000019A5 44/ 0F B6 4B movzx r9d, byte ptr [rbx + 4] \n"
" 04 \n"
" 000019AA 44/ 0F B7 4B movzx r9d, word ptr [rbx + 4] \n"
" 04 \n"
" \n"
" 000019AF 4C/ 0F B6 CB movzx r9, bl \n"
" 000019B3 4C/ 0F B7 CB movzx r9, bx \n"
" 000019B7 4C/ 0F B6 4B movzx r9, byte ptr [rbx + 4] \n"
" 04 \n"
" 000019BC 4C/ 0F B7 4B movzx r9, word ptr [rbx + 4] \n"
" 04 \n"
" \n"
" \n"
" ; Source: rbx, target: r10 \n"
" 000019C1 41/ B2 01 mov r10b, 1 \n"
" 000019C4 66| 41/ BA mov r10w, 1 \n"
" 0001 \n"
" 000019C9 41/ BA mov r10d, 1 \n"
" 00000001 \n"
" 000019CF 49/ C7 C2 mov r10, 1 \n"
" 00000001 \n"
" \n"
" 000019D6 44/ 8A D3 mov r10b, bl \n"
" 000019D9 66| 44/ 8B D3 mov r10w, bx \n"
" 000019DD 44/ 8B D3 mov r10d, ebx \n"
" 000019E0 4C/ 8B D3 mov r10, rbx \n"
" \n"
" 000019E3 44/ 8A 53 FC mov r10b, byte ptr [rbx - 4] \n"
" 000019E7 44/ 8A 53 04 mov r10b, byte ptr [rbx + 4] \n"
" 000019EB 66| 44/ 8B 53 mov r10w, word ptr [rbx + 4] \n"
" 04 \n"
" 000019F0 44/ 8B 53 04 mov r10d, dword ptr [rbx + 4] \n"
" 000019F4 4C/ 8B 53 04 mov r10, qword ptr [rbx + 4] \n"
" \n"
" 000019F8 41/ 88 5A FC mov byte ptr [r10 - 4], bl \n"
" 000019FC 41/ 88 5A 04 mov byte ptr [r10 + 4], bl \n"
" 00001A00 66| 41/ 89 5A mov word ptr [r10 + 4], bx \n"
" 04 \n"
" 00001A05 41/ 89 5A 04 mov dword ptr [r10 + 4], ebx \n"
" 00001A09 49/ 89 5A 04 mov qword ptr [r10 + 4], rbx \n"
" \n"
" 00001A0D 66| 44/ 0F B6 D3 movzx r10w, bl \n"
" 00001A12 66| 44/ 0F B6 53 movzx r10w, byte ptr [rbx + 4] \n"
" 04 \n"
" \n"
" 00001A18 44/ 0F B6 D3 movzx r10d, bl \n"
" 00001A1C 44/ 0F B7 D3 movzx r10d, bx \n"
" 00001A20 44/ 0F B6 53 movzx r10d, byte ptr [rbx + 4] \n"
" 04 \n"
" 00001A25 44/ 0F B7 53 movzx r10d, word ptr [rbx + 4] \n"
" 04 \n"
" \n"
" 00001A2A 4C/ 0F B6 D3 movzx r10, bl \n"
" 00001A2E 4C/ 0F B7 D3 movzx r10, bx \n"
" 00001A32 4C/ 0F B6 53 movzx r10, byte ptr [rbx + 4] \n"
" 04 \n"
" 00001A37 4C/ 0F B7 53 movzx r10, word ptr [rbx + 4] \n"
" 04 \n"
" \n"
" \n"
" ; Source: rbx, target: r11 \n"
" 00001A3C 41/ B3 01 mov r11b, 1 \n"
" 00001A3F 66| 41/ BB mov r11w, 1 \n"
" 0001 \n"
" 00001A44 41/ BB mov r11d, 1 \n"
" 00000001 \n"
" 00001A4A 49/ C7 C3 mov r11, 1 \n"
" 00000001 \n"
" \n"
" 00001A51 44/ 8A DB mov r11b, bl \n"
" 00001A54 66| 44/ 8B DB mov r11w, bx \n"
" 00001A58 44/ 8B DB mov r11d, ebx \n"
" 00001A5B 4C/ 8B DB mov r11, rbx \n"
" \n"
" 00001A5E 44/ 8A 5B FC mov r11b, byte ptr [rbx - 4] \n"
" 00001A62 44/ 8A 5B 04 mov r11b, byte ptr [rbx + 4] \n"
" 00001A66 66| 44/ 8B 5B mov r11w, word ptr [rbx + 4] \n"
" 04 \n"
" 00001A6B 44/ 8B 5B 04 mov r11d, dword ptr [rbx + 4] \n"
" 00001A6F 4C/ 8B 5B 04 mov r11, qword ptr [rbx + 4] \n"
" \n"
" 00001A73 41/ 88 5B FC mov byte ptr [r11 - 4], bl \n"
" 00001A77 41/ 88 5B 04 mov byte ptr [r11 + 4], bl \n"
" 00001A7B 66| 41/ 89 5B mov word ptr [r11 + 4], bx \n"
" 04 \n"
" 00001A80 41/ 89 5B 04 mov dword ptr [r11 + 4], ebx \n"
" 00001A84 49/ 89 5B 04 mov qword ptr [r11 + 4], rbx \n"
" \n"
" 00001A88 66| 44/ 0F B6 DB movzx r11w, bl \n"
" 00001A8D 66| 44/ 0F B6 5B movzx r11w, byte ptr [rbx + 4] \n"
" 04 \n"
" \n"
" 00001A93 44/ 0F B6 DB movzx r11d, bl \n"
" 00001A97 44/ 0F B7 DB movzx r11d, bx \n"
" 00001A9B 44/ 0F B6 5B movzx r11d, byte ptr [rbx + 4] \n"
" 04 \n"
" 00001AA0 44/ 0F B7 5B movzx r11d, word ptr [rbx + 4] \n"
" 04 \n"
" \n"
" 00001AA5 4C/ 0F B6 DB movzx r11, bl \n"
" 00001AA9 4C/ 0F B7 DB movzx r11, bx \n"
" 00001AAD 4C/ 0F B6 5B movzx r11, byte ptr [rbx + 4] \n"
" 04 \n"
" 00001AB2 4C/ 0F B7 5B movzx r11, word ptr [rbx + 4] \n"
" 04 \n"
" \n"
" \n"
" ; Source: rbx, target: r12 \n"
" 00001AB7 41/ B4 01 mov r12b, 1 \n"
" 00001ABA 66| 41/ BC mov r12w, 1 \n"
" 0001 \n"
" 00001ABF 41/ BC mov r12d, 1 \n"
" 00000001 \n"
" 00001AC5 49/ C7 C4 mov r12, 1 \n"
" 00000001 \n"
" \n"
" 00001ACC 44/ 8A E3 mov r12b, bl \n"
" 00001ACF 66| 44/ 8B E3 mov r12w, bx \n"
" 00001AD3 44/ 8B E3 mov r12d, ebx \n"
" 00001AD6 4C/ 8B E3 mov r12, rbx \n"
" \n"
" 00001AD9 44/ 8A 63 FC mov r12b, byte ptr [rbx - 4] \n"
" 00001ADD 44/ 8A 63 04 mov r12b, byte ptr [rbx + 4] \n"
" 00001AE1 66| 44/ 8B 63 mov r12w, word ptr [rbx + 4] \n"
" 04 \n"
" 00001AE6 44/ 8B 63 04 mov r12d, dword ptr [rbx + 4] \n"
" 00001AEA 4C/ 8B 63 04 mov r12, qword ptr [rbx + 4] \n"
" \n"
" 00001AEE 41/ 88 5C 24 mov byte ptr [r12 - 4], bl \n"
" FC \n"
" 00001AF3 41/ 88 5C 24 mov byte ptr [r12 + 4], bl \n"
" 04 \n"
" 00001AF8 66| 41/ 89 5C 24 mov word ptr [r12 + 4], bx \n"
" 04 \n"
" 00001AFE 41/ 89 5C 24 mov dword ptr [r12 + 4], ebx \n"
" 04 \n"
" 00001B03 49/ 89 5C 24 mov qword ptr [r12 + 4], rbx \n"
" 04 \n"
" \n"
" 00001B08 66| 44/ 0F B6 E3 movzx r12w, bl \n"
" 00001B0D 66| 44/ 0F B6 63 movzx r12w, byte ptr [rbx + 4] \n"
" 04 \n"
" \n"
" 00001B13 44/ 0F B6 E3 movzx r12d, bl \n"
" 00001B17 44/ 0F B7 E3 movzx r12d, bx \n"
" 00001B1B 44/ 0F B6 63 movzx r12d, byte ptr [rbx + 4] \n"
" 04 \n"
" 00001B20 44/ 0F B7 63 movzx r12d, word ptr [rbx + 4] \n"
" 04 \n"
" \n"
" 00001B25 4C/ 0F B6 E3 movzx r12, bl \n"
" 00001B29 4C/ 0F B7 E3 movzx r12, bx \n"
" 00001B2D 4C/ 0F B6 63 movzx r12, byte ptr [rbx + 4] \n"
" 04 \n"
" 00001B32 4C/ 0F B7 63 movzx r12, word ptr [rbx + 4] \n"
" 04 \n"
" \n"
" \n"
" ; Source: rbx, target: r13 \n"
" 00001B37 41/ B5 01 mov r13b, 1 \n"
" 00001B3A 66| 41/ BD mov r13w, 1 \n"
" 0001 \n"
" 00001B3F 41/ BD mov r13d, 1 \n"
" 00000001 \n"
" 00001B45 49/ C7 C5 mov r13, 1 \n"
" 00000001 \n"
" \n"
" 00001B4C 44/ 8A EB mov r13b, bl \n"
" 00001B4F 66| 44/ 8B EB mov r13w, bx \n"
" 00001B53 44/ 8B EB mov r13d, ebx \n"
" 00001B56 4C/ 8B EB mov r13, rbx \n"
" \n"
" 00001B59 44/ 8A 6B FC mov r13b, byte ptr [rbx - 4] \n"
" 00001B5D 44/ 8A 6B 04 mov r13b, byte ptr [rbx + 4] \n"
" 00001B61 66| 44/ 8B 6B mov r13w, word ptr [rbx + 4] \n"
" 04 \n"
" 00001B66 44/ 8B 6B 04 mov r13d, dword ptr [rbx + 4] \n"
" 00001B6A 4C/ 8B 6B 04 mov r13, qword ptr [rbx + 4] \n"
" \n"
" 00001B6E 41/ 88 5D FC mov byte ptr [r13 - 4], bl \n"
" 00001B72 41/ 88 5D 04 mov byte ptr [r13 + 4], bl \n"
" 00001B76 66| 41/ 89 5D mov word ptr [r13 + 4], bx \n"
" 04 \n"
" 00001B7B 41/ 89 5D 04 mov dword ptr [r13 + 4], ebx \n"
" 00001B7F 49/ 89 5D 04 mov qword ptr [r13 + 4], rbx \n"
" \n"
" 00001B83 66| 44/ 0F B6 EB movzx r13w, bl \n"
" 00001B88 66| 44/ 0F B6 6B movzx r13w, byte ptr [rbx + 4] \n"
" 04 \n"
" \n"
" 00001B8E 44/ 0F B6 EB movzx r13d, bl \n"
" 00001B92 44/ 0F B7 EB movzx r13d, bx \n"
" 00001B96 44/ 0F B6 6B movzx r13d, byte ptr [rbx + 4] \n"
" 04 \n"
" 00001B9B 44/ 0F B7 6B movzx r13d, word ptr [rbx + 4] \n"
" 04 \n"
" \n"
" 00001BA0 4C/ 0F B6 EB movzx r13, bl \n"
" 00001BA4 4C/ 0F B7 EB movzx r13, bx \n";
ml64Output +=
" 00001BA8 4C/ 0F B6 6B movzx r13, byte ptr [rbx + 4] \n"
" 04 \n"
" 00001BAD 4C/ 0F B7 6B movzx r13, word ptr [rbx + 4] \n"
" 04 \n"
" \n"
" \n"
" ; Source: rbx, target: r14 \n"
" 00001BB2 41/ B6 01 mov r14b, 1 \n"
" 00001BB5 66| 41/ BE mov r14w, 1 \n"
" 0001 \n"
" 00001BBA 41/ BE mov r14d, 1 \n"
" 00000001 \n"
" 00001BC0 49/ C7 C6 mov r14, 1 \n"
" 00000001 \n"
" \n"
" 00001BC7 44/ 8A F3 mov r14b, bl \n"
" 00001BCA 66| 44/ 8B F3 mov r14w, bx \n"
" 00001BCE 44/ 8B F3 mov r14d, ebx \n"
" 00001BD1 4C/ 8B F3 mov r14, rbx \n"
" \n"
" 00001BD4 44/ 8A 73 FC mov r14b, byte ptr [rbx - 4] \n"
" 00001BD8 44/ 8A 73 04 mov r14b, byte ptr [rbx + 4] \n"
" 00001BDC 66| 44/ 8B 73 mov r14w, word ptr [rbx + 4] \n"
" 04 \n"
" 00001BE1 44/ 8B 73 04 mov r14d, dword ptr [rbx + 4] \n"
" 00001BE5 4C/ 8B 73 04 mov r14, qword ptr [rbx + 4] \n"
" \n"
" 00001BE9 41/ 88 5E FC mov byte ptr [r14 - 4], bl \n"
" 00001BED 41/ 88 5E 04 mov byte ptr [r14 + 4], bl \n"
" 00001BF1 66| 41/ 89 5E mov word ptr [r14 + 4], bx \n"
" 04 \n"
" 00001BF6 41/ 89 5E 04 mov dword ptr [r14 + 4], ebx \n"
" 00001BFA 49/ 89 5E 04 mov qword ptr [r14 + 4], rbx \n"
" \n"
" 00001BFE 66| 44/ 0F B6 F3 movzx r14w, bl \n"
" 00001C03 66| 44/ 0F B6 73 movzx r14w, byte ptr [rbx + 4] \n"
" 04 \n"
" \n"
" 00001C09 44/ 0F B6 F3 movzx r14d, bl \n"
" 00001C0D 44/ 0F B7 F3 movzx r14d, bx \n"
" 00001C11 44/ 0F B6 73 movzx r14d, byte ptr [rbx + 4] \n"
" 04 \n"
" 00001C16 44/ 0F B7 73 movzx r14d, word ptr [rbx + 4] \n"
" 04 \n"
" \n"
" 00001C1B 4C/ 0F B6 F3 movzx r14, bl \n"
" 00001C1F 4C/ 0F B7 F3 movzx r14, bx \n"
" 00001C23 4C/ 0F B6 73 movzx r14, byte ptr [rbx + 4] \n"
" 04 \n"
" 00001C28 4C/ 0F B7 73 movzx r14, word ptr [rbx + 4] \n"
" 04 \n"
" \n"
" \n"
" ; Source: rbx, target: r15 \n"
" 00001C2D 41/ B7 01 mov r15b, 1 \n"
" 00001C30 66| 41/ BF mov r15w, 1 \n"
" 0001 \n"
" 00001C35 41/ BF mov r15d, 1 \n"
" 00000001 \n"
" 00001C3B 49/ C7 C7 mov r15, 1 \n"
" 00000001 \n"
" \n"
" 00001C42 44/ 8A FB mov r15b, bl \n"
" 00001C45 66| 44/ 8B FB mov r15w, bx \n"
" 00001C49 44/ 8B FB mov r15d, ebx \n"
" 00001C4C 4C/ 8B FB mov r15, rbx \n"
" \n"
" 00001C4F 44/ 8A 7B FC mov r15b, byte ptr [rbx - 4] \n"
" 00001C53 44/ 8A 7B 04 mov r15b, byte ptr [rbx + 4] \n"
" 00001C57 66| 44/ 8B 7B mov r15w, word ptr [rbx + 4] \n"
" 04 \n"
" 00001C5C 44/ 8B 7B 04 mov r15d, dword ptr [rbx + 4] \n"
" 00001C60 4C/ 8B 7B 04 mov r15, qword ptr [rbx + 4] \n"
" \n"
" 00001C64 41/ 88 5F FC mov byte ptr [r15 - 4], bl \n"
" 00001C68 41/ 88 5F 04 mov byte ptr [r15 + 4], bl \n"
" 00001C6C 66| 41/ 89 5F mov word ptr [r15 + 4], bx \n"
" 04 \n"
" 00001C71 41/ 89 5F 04 mov dword ptr [r15 + 4], ebx \n"
" 00001C75 49/ 89 5F 04 mov qword ptr [r15 + 4], rbx \n"
" \n"
" 00001C79 66| 44/ 0F B6 FB movzx r15w, bl \n"
" 00001C7E 66| 44/ 0F B6 7B movzx r15w, byte ptr [rbx + 4] \n"
" 04 \n"
" \n"
" 00001C84 44/ 0F B6 FB movzx r15d, bl \n"
" 00001C88 44/ 0F B7 FB movzx r15d, bx \n"
" 00001C8C 44/ 0F B6 7B movzx r15d, byte ptr [rbx + 4] \n"
" 04 \n"
" 00001C91 44/ 0F B7 7B movzx r15d, word ptr [rbx + 4] \n"
" 04 \n"
" \n"
" 00001C96 4C/ 0F B6 FB movzx r15, bl \n"
" 00001C9A 4C/ 0F B7 FB movzx r15, bx \n"
" 00001C9E 4C/ 0F B6 7B movzx r15, byte ptr [rbx + 4] \n"
" 04 \n"
" 00001CA3 4C/ 0F B7 7B movzx r15, word ptr [rbx + 4] \n"
" 04 \n"
" \n"
" \n"
" ; Source: rsp, target: rax \n"
" 00001CA8 B0 01 mov al, 1 \n"
" 00001CAA 66| B8 0001 mov ax, 1 \n"
" 00001CAE B8 00000001 mov eax, 1 \n"
" 00001CB3 48/ C7 C0 mov rax, 1 \n"
" 00000001 \n"
" \n"
" 00001CBA 40/ 8A C4 mov al, spl \n"
" 00001CBD 66| 8B C4 mov ax, sp \n"
" 00001CC0 8B C4 mov eax, esp \n"
" 00001CC2 48/ 8B C4 mov rax, rsp \n"
" \n"
" 00001CC5 8A 44 24 FC mov al, byte ptr [rsp - 4] \n"
" 00001CC9 8A 44 24 04 mov al, byte ptr [rsp + 4] \n"
" 00001CCD 66| 8B 44 24 mov ax, word ptr [rsp + 4] \n"
" 04 \n"
" 00001CD2 8B 44 24 04 mov eax, dword ptr [rsp + 4] \n"
" 00001CD6 48/ 8B 44 24 mov rax, qword ptr [rsp + 4] \n"
" 04 \n"
" \n"
" 00001CDB 40/ 88 60 FC mov byte ptr [rax - 4], spl \n"
" 00001CDF 40/ 88 60 04 mov byte ptr [rax + 4], spl \n"
" 00001CE3 66| 89 60 04 mov word ptr [rax + 4], sp \n"
" 00001CE7 89 60 04 mov dword ptr [rax + 4], esp \n"
" 00001CEA 48/ 89 60 04 mov qword ptr [rax + 4], rsp \n"
" \n"
" 00001CEE 66| 40/ 0F B6 C4 movzx ax, spl \n"
" 00001CF3 66| 0F B6 44 24 movzx ax, byte ptr [rsp + 4] \n"
" 04 \n"
" \n"
" 00001CF9 40/ 0F B6 C4 movzx eax, spl \n"
" 00001CFD 0F B7 C4 movzx eax, sp \n"
" 00001D00 0F B6 44 24 04 movzx eax, byte ptr [rsp + 4] \n"
" 00001D05 0F B7 44 24 04 movzx eax, word ptr [rsp + 4] \n"
" \n"
" 00001D0A 48/ 0F B6 C4 movzx rax, spl \n"
" 00001D0E 48/ 0F B7 C4 movzx rax, sp \n"
" 00001D12 48/ 0F B6 44 24 movzx rax, byte ptr [rsp + 4] \n"
" 04 \n"
" 00001D18 48/ 0F B7 44 24 movzx rax, word ptr [rsp + 4] \n"
" 04 \n"
" \n"
" \n"
" ; Source: rsp, target: rcx \n"
" 00001D1E B1 01 mov cl, 1 \n"
" 00001D20 66| B9 0001 mov cx, 1 \n"
" 00001D24 B9 00000001 mov ecx, 1 \n"
" 00001D29 48/ C7 C1 mov rcx, 1 \n"
" 00000001 \n"
" \n"
" 00001D30 40/ 8A CC mov cl, spl \n"
" 00001D33 66| 8B CC mov cx, sp \n"
" 00001D36 8B CC mov ecx, esp \n"
" 00001D38 48/ 8B CC mov rcx, rsp \n"
" \n"
" 00001D3B 8A 4C 24 FC mov cl, byte ptr [rsp - 4] \n"
" 00001D3F 8A 4C 24 04 mov cl, byte ptr [rsp + 4] \n"
" 00001D43 66| 8B 4C 24 mov cx, word ptr [rsp + 4] \n"
" 04 \n"
" 00001D48 8B 4C 24 04 mov ecx, dword ptr [rsp + 4] \n"
" 00001D4C 48/ 8B 4C 24 mov rcx, qword ptr [rsp + 4] \n"
" 04 \n"
" \n"
" 00001D51 40/ 88 61 FC mov byte ptr [rcx - 4], spl \n"
" 00001D55 40/ 88 61 04 mov byte ptr [rcx + 4], spl \n"
" 00001D59 66| 89 61 04 mov word ptr [rcx + 4], sp \n"
" 00001D5D 89 61 04 mov dword ptr [rcx + 4], esp \n"
" 00001D60 48/ 89 61 04 mov qword ptr [rcx + 4], rsp \n"
" \n"
" 00001D64 66| 40/ 0F B6 CC movzx cx, spl \n"
" 00001D69 66| 0F B6 4C 24 movzx cx, byte ptr [rsp + 4] \n"
" 04 \n"
" \n"
" 00001D6F 40/ 0F B6 CC movzx ecx, spl \n"
" 00001D73 0F B7 CC movzx ecx, sp \n"
" 00001D76 0F B6 4C 24 04 movzx ecx, byte ptr [rsp + 4] \n"
" 00001D7B 0F B7 4C 24 04 movzx ecx, word ptr [rsp + 4] \n"
" \n"
" 00001D80 48/ 0F B6 CC movzx rcx, spl \n"
" 00001D84 48/ 0F B7 CC movzx rcx, sp \n"
" 00001D88 48/ 0F B6 4C 24 movzx rcx, byte ptr [rsp + 4] \n"
" 04 \n"
" 00001D8E 48/ 0F B7 4C 24 movzx rcx, word ptr [rsp + 4] \n"
" 04 \n"
" \n"
" \n"
" ; Source: rsp, target: rdx \n"
" 00001D94 B2 01 mov dl, 1 \n"
" 00001D96 66| BA 0001 mov dx, 1 \n"
" 00001D9A BA 00000001 mov edx, 1 \n"
" 00001D9F 48/ C7 C2 mov rdx, 1 \n"
" 00000001 \n"
" \n"
" 00001DA6 40/ 8A D4 mov dl, spl \n"
" 00001DA9 66| 8B D4 mov dx, sp \n"
" 00001DAC 8B D4 mov edx, esp \n"
" 00001DAE 48/ 8B D4 mov rdx, rsp \n"
" \n"
" 00001DB1 8A 54 24 FC mov dl, byte ptr [rsp - 4] \n"
" 00001DB5 8A 54 24 04 mov dl, byte ptr [rsp + 4] \n"
" 00001DB9 66| 8B 54 24 mov dx, word ptr [rsp + 4] \n"
" 04 \n"
" 00001DBE 8B 54 24 04 mov edx, dword ptr [rsp + 4] \n"
" 00001DC2 48/ 8B 54 24 mov rdx, qword ptr [rsp + 4] \n"
" 04 \n"
" \n"
" 00001DC7 40/ 88 62 FC mov byte ptr [rdx - 4], spl \n"
" 00001DCB 40/ 88 62 04 mov byte ptr [rdx + 4], spl \n"
" 00001DCF 66| 89 62 04 mov word ptr [rdx + 4], sp \n"
" 00001DD3 89 62 04 mov dword ptr [rdx + 4], esp \n"
" 00001DD6 48/ 89 62 04 mov qword ptr [rdx + 4], rsp \n"
" \n"
" 00001DDA 66| 40/ 0F B6 D4 movzx dx, spl \n"
" 00001DDF 66| 0F B6 54 24 movzx dx, byte ptr [rsp + 4] \n"
" 04 \n"
" \n"
" 00001DE5 40/ 0F B6 D4 movzx edx, spl \n"
" 00001DE9 0F B7 D4 movzx edx, sp \n"
" 00001DEC 0F B6 54 24 04 movzx edx, byte ptr [rsp + 4] \n"
" 00001DF1 0F B7 54 24 04 movzx edx, word ptr [rsp + 4] \n"
" \n"
" 00001DF6 48/ 0F B6 D4 movzx rdx, spl \n"
" 00001DFA 48/ 0F B7 D4 movzx rdx, sp \n"
" 00001DFE 48/ 0F B6 54 24 movzx rdx, byte ptr [rsp + 4] \n"
" 04 \n"
" 00001E04 48/ 0F B7 54 24 movzx rdx, word ptr [rsp + 4] \n"
" 04 \n"
" \n"
" \n"
" ; Source: rsp, target: rbx \n"
" 00001E0A B3 01 mov bl, 1 \n"
" 00001E0C 66| BB 0001 mov bx, 1 \n"
" 00001E10 BB 00000001 mov ebx, 1 \n"
" 00001E15 48/ C7 C3 mov rbx, 1 \n"
" 00000001 \n"
" \n"
" 00001E1C 40/ 8A DC mov bl, spl \n"
" 00001E1F 66| 8B DC mov bx, sp \n"
" 00001E22 8B DC mov ebx, esp \n"
" 00001E24 48/ 8B DC mov rbx, rsp \n"
" \n"
" 00001E27 8A 5C 24 FC mov bl, byte ptr [rsp - 4] \n"
" 00001E2B 8A 5C 24 04 mov bl, byte ptr [rsp + 4] \n"
" 00001E2F 66| 8B 5C 24 mov bx, word ptr [rsp + 4] \n"
" 04 \n"
" 00001E34 8B 5C 24 04 mov ebx, dword ptr [rsp + 4] \n"
" 00001E38 48/ 8B 5C 24 mov rbx, qword ptr [rsp + 4] \n"
" 04 \n"
" \n"
" 00001E3D 40/ 88 63 FC mov byte ptr [rbx - 4], spl \n"
" 00001E41 40/ 88 63 04 mov byte ptr [rbx + 4], spl \n"
" 00001E45 66| 89 63 04 mov word ptr [rbx + 4], sp \n"
" 00001E49 89 63 04 mov dword ptr [rbx + 4], esp \n"
" 00001E4C 48/ 89 63 04 mov qword ptr [rbx + 4], rsp \n"
" \n"
" 00001E50 66| 40/ 0F B6 DC movzx bx, spl \n"
" 00001E55 66| 0F B6 5C 24 movzx bx, byte ptr [rsp + 4] \n"
" 04 \n"
" \n"
" 00001E5B 40/ 0F B6 DC movzx ebx, spl \n"
" 00001E5F 0F B7 DC movzx ebx, sp \n"
" 00001E62 0F B6 5C 24 04 movzx ebx, byte ptr [rsp + 4] \n"
" 00001E67 0F B7 5C 24 04 movzx ebx, word ptr [rsp + 4] \n"
" \n"
" 00001E6C 48/ 0F B6 DC movzx rbx, spl \n"
" 00001E70 48/ 0F B7 DC movzx rbx, sp \n"
" 00001E74 48/ 0F B6 5C 24 movzx rbx, byte ptr [rsp + 4] \n"
" 04 \n"
" 00001E7A 48/ 0F B7 5C 24 movzx rbx, word ptr [rsp + 4] \n"
" 04 \n"
" \n"
" \n"
" ; Source: rsp, target: rsp \n"
" 00001E80 40/ B4 01 mov spl, 1 \n"
" 00001E83 66| BC 0001 mov sp, 1 \n"
" 00001E87 BC 00000001 mov esp, 1 \n"
" 00001E8C 48/ C7 C4 mov rsp, 1 \n"
" 00000001 \n"
" \n"
" 00001E93 40/ 8A E4 mov spl, spl \n"
" 00001E96 66| 8B E4 mov sp, sp \n"
" 00001E99 8B E4 mov esp, esp \n"
" 00001E9B 48/ 8B E4 mov rsp, rsp \n"
" \n"
" 00001E9E 40/ 8A 64 24 mov spl, byte ptr [rsp - 4] \n"
" FC \n"
" 00001EA3 40/ 8A 64 24 mov spl, byte ptr [rsp + 4] \n"
" 04 \n"
" 00001EA8 66| 8B 64 24 mov sp, word ptr [rsp + 4] \n"
" 04 \n"
" 00001EAD 8B 64 24 04 mov esp, dword ptr [rsp + 4] \n"
" 00001EB1 48/ 8B 64 24 mov rsp, qword ptr [rsp + 4] \n"
" 04 \n"
" \n"
" 00001EB6 40/ 88 64 24 mov byte ptr [rsp - 4], spl \n"
" FC \n"
" 00001EBB 40/ 88 64 24 mov byte ptr [rsp + 4], spl \n"
" 04 \n"
" 00001EC0 66| 89 64 24 mov word ptr [rsp + 4], sp \n"
" 04 \n"
" 00001EC5 89 64 24 04 mov dword ptr [rsp + 4], esp \n"
" 00001EC9 48/ 89 64 24 mov qword ptr [rsp + 4], rsp \n"
" 04 \n"
" \n"
" 00001ECE 66| 40/ 0F B6 E4 movzx sp, spl \n"
" 00001ED3 66| 0F B6 64 24 movzx sp, byte ptr [rsp + 4] \n"
" 04 \n"
" \n"
" 00001ED9 40/ 0F B6 E4 movzx esp, spl \n"
" 00001EDD 0F B7 E4 movzx esp, sp \n"
" 00001EE0 0F B6 64 24 04 movzx esp, byte ptr [rsp + 4] \n"
" 00001EE5 0F B7 64 24 04 movzx esp, word ptr [rsp + 4] \n"
" \n"
" 00001EEA 48/ 0F B6 E4 movzx rsp, spl \n"
" 00001EEE 48/ 0F B7 E4 movzx rsp, sp \n"
" 00001EF2 48/ 0F B6 64 24 movzx rsp, byte ptr [rsp + 4] \n"
" 04 \n"
" 00001EF8 48/ 0F B7 64 24 movzx rsp, word ptr [rsp + 4] \n"
" 04 \n"
" \n"
" \n"
" ; Source: rsp, target: rbp \n"
" 00001EFE 40/ B5 01 mov bpl, 1 \n"
" 00001F01 66| BD 0001 mov bp, 1 \n"
" 00001F05 BD 00000001 mov ebp, 1 \n"
" 00001F0A 48/ C7 C5 mov rbp, 1 \n"
" 00000001 \n"
" \n"
" 00001F11 40/ 8A EC mov bpl, spl \n"
" 00001F14 66| 8B EC mov bp, sp \n"
" 00001F17 8B EC mov ebp, esp \n"
" 00001F19 48/ 8B EC mov rbp, rsp \n"
" \n"
" 00001F1C 40/ 8A 6C 24 mov bpl, byte ptr [rsp - 4] \n"
" FC \n"
" 00001F21 40/ 8A 6C 24 mov bpl, byte ptr [rsp + 4] \n"
" 04 \n"
" 00001F26 66| 8B 6C 24 mov bp, word ptr [rsp + 4] \n"
" 04 \n"
" 00001F2B 8B 6C 24 04 mov ebp, dword ptr [rsp + 4] \n"
" 00001F2F 48/ 8B 6C 24 mov rbp, qword ptr [rsp + 4] \n"
" 04 \n"
" \n"
" 00001F34 40/ 88 65 FC mov byte ptr [rbp - 4], spl \n"
" 00001F38 40/ 88 65 04 mov byte ptr [rbp + 4], spl \n"
" 00001F3C 66| 89 65 04 mov word ptr [rbp + 4], sp \n"
" 00001F40 89 65 04 mov dword ptr [rbp + 4], esp \n"
" 00001F43 48/ 89 65 04 mov qword ptr [rbp + 4], rsp \n"
" \n"
" 00001F47 66| 40/ 0F B6 EC movzx bp, spl \n"
" 00001F4C 66| 0F B6 6C 24 movzx bp, byte ptr [rsp + 4] \n"
" 04 \n"
" \n"
" 00001F52 40/ 0F B6 EC movzx ebp, spl \n"
" 00001F56 0F B7 EC movzx ebp, sp \n"
" 00001F59 0F B6 6C 24 04 movzx ebp, byte ptr [rsp + 4] \n"
" 00001F5E 0F B7 6C 24 04 movzx ebp, word ptr [rsp + 4] \n"
" \n"
" 00001F63 48/ 0F B6 EC movzx rbp, spl \n"
" 00001F67 48/ 0F B7 EC movzx rbp, sp \n"
" 00001F6B 48/ 0F B6 6C 24 movzx rbp, byte ptr [rsp + 4] \n"
" 04 \n"
" 00001F71 48/ 0F B7 6C 24 movzx rbp, word ptr [rsp + 4] \n"
" 04 \n"
" \n"
" \n"
" ; Source: rsp, target: rsi \n"
" 00001F77 40/ B7 01 mov dil, 1 \n"
" 00001F7A 66| BE 0001 mov si, 1 \n"
" 00001F7E BE 00000001 mov esi, 1 \n"
" 00001F83 48/ C7 C6 mov rsi, 1 \n"
" 00000001 \n"
" \n"
" 00001F8A 40/ 8A FC mov dil, spl \n"
" 00001F8D 66| 8B F4 mov si, sp \n"
" 00001F90 8B F4 mov esi, esp \n"
" 00001F92 48/ 8B F4 mov rsi, rsp \n"
" \n"
" 00001F95 40/ 8A 7C 24 mov dil, byte ptr [rsp - 4] \n"
" FC \n"
" 00001F9A 40/ 8A 7C 24 mov dil, byte ptr [rsp + 4] \n"
" 04 \n"
" 00001F9F 66| 8B 74 24 mov si, word ptr [rsp + 4] \n"
" 04 \n"
" 00001FA4 8B 74 24 04 mov esi, dword ptr [rsp + 4] \n"
" 00001FA8 48/ 8B 74 24 mov rsi, qword ptr [rsp + 4] \n"
" 04 \n"
" \n"
" 00001FAD 40/ 88 66 FC mov byte ptr [rsi - 4], spl \n"
" 00001FB1 40/ 88 66 04 mov byte ptr [rsi + 4], spl \n"
" 00001FB5 66| 89 66 04 mov word ptr [rsi + 4], sp \n"
" 00001FB9 89 66 04 mov dword ptr [rsi + 4], esp \n"
" 00001FBC 48/ 89 66 04 mov qword ptr [rsi + 4], rsp \n"
" \n"
" 00001FC0 66| 40/ 0F B6 F4 movzx si, spl \n"
" 00001FC5 66| 0F B6 74 24 movzx si, byte ptr [rsp + 4] \n"
" 04 \n"
" \n"
" 00001FCB 40/ 0F B6 F4 movzx esi, spl \n"
" 00001FCF 0F B7 F4 movzx esi, sp \n"
" 00001FD2 0F B6 74 24 04 movzx esi, byte ptr [rsp + 4] \n"
" 00001FD7 0F B7 74 24 04 movzx esi, word ptr [rsp + 4] \n"
" \n"
" 00001FDC 48/ 0F B6 F4 movzx rsi, spl \n"
" 00001FE0 48/ 0F B7 F4 movzx rsi, sp \n"
" 00001FE4 48/ 0F B6 74 24 movzx rsi, byte ptr [rsp + 4] \n"
" 04 \n"
" 00001FEA 48/ 0F B7 74 24 movzx rsi, word ptr [rsp + 4] \n"
" 04 \n"
" \n"
" \n"
" ; Source: rsp, target: rdi \n"
" 00001FF0 40/ B6 01 mov sil, 1 \n"
" 00001FF3 66| BF 0001 mov di, 1 \n"
" 00001FF7 BF 00000001 mov edi, 1 \n"
" 00001FFC 48/ C7 C7 mov rdi, 1 \n"
" 00000001 \n"
" \n"
" 00002003 40/ 8A F4 mov sil, spl \n"
" 00002006 66| 8B FC mov di, sp \n"
" 00002009 8B FC mov edi, esp \n"
" 0000200B 48/ 8B FC mov rdi, rsp \n"
" \n"
" 0000200E 40/ 8A 74 24 mov sil, byte ptr [rsp - 4] \n"
" FC \n"
" 00002013 40/ 8A 74 24 mov sil, byte ptr [rsp + 4] \n"
" 04 \n"
" 00002018 66| 8B 7C 24 mov di, word ptr [rsp + 4] \n"
" 04 \n"
" 0000201D 8B 7C 24 04 mov edi, dword ptr [rsp + 4] \n"
" 00002021 48/ 8B 7C 24 mov rdi, qword ptr [rsp + 4] \n"
" 04 \n"
" \n"
" 00002026 40/ 88 67 FC mov byte ptr [rdi - 4], spl \n"
" 0000202A 40/ 88 67 04 mov byte ptr [rdi + 4], spl \n"
" 0000202E 66| 89 67 04 mov word ptr [rdi + 4], sp \n"
" 00002032 89 67 04 mov dword ptr [rdi + 4], esp \n"
" 00002035 48/ 89 67 04 mov qword ptr [rdi + 4], rsp \n"
" \n"
" 00002039 66| 40/ 0F B6 FC movzx di, spl \n"
" 0000203E 66| 0F B6 7C 24 movzx di, byte ptr [rsp + 4] \n"
" 04 \n"
" \n"
" 00002044 40/ 0F B6 FC movzx edi, spl \n"
" 00002048 0F B7 FC movzx edi, sp \n"
" 0000204B 0F B6 7C 24 04 movzx edi, byte ptr [rsp + 4] \n"
" 00002050 0F B7 7C 24 04 movzx edi, word ptr [rsp + 4] \n"
" \n"
" 00002055 48/ 0F B6 FC movzx rdi, spl \n"
" 00002059 48/ 0F B7 FC movzx rdi, sp \n"
" 0000205D 48/ 0F B6 7C 24 movzx rdi, byte ptr [rsp + 4] \n"
" 04 \n"
" 00002063 48/ 0F B7 7C 24 movzx rdi, word ptr [rsp + 4] \n"
" 04 \n"
" \n"
" \n"
" ; Source: rsp, target: r8 \n"
" 00002069 41/ B0 01 mov r8b, 1 \n"
" 0000206C 66| 41/ B8 mov r8w, 1 \n"
" 0001 \n"
" 00002071 41/ B8 mov r8d, 1 \n"
" 00000001 \n"
" 00002077 49/ C7 C0 mov r8, 1 \n"
" 00000001 \n"
" \n"
" 0000207E 44/ 8A C4 mov r8b, spl \n"
" 00002081 66| 44/ 8B C4 mov r8w, sp \n"
" 00002085 44/ 8B C4 mov r8d, esp \n"
" 00002088 4C/ 8B C4 mov r8, rsp \n"
" \n"
" 0000208B 44/ 8A 44 24 mov r8b, byte ptr [rsp - 4] \n"
" FC \n"
" 00002090 44/ 8A 44 24 mov r8b, byte ptr [rsp + 4] \n"
" 04 \n"
" 00002095 66| 44/ 8B 44 24 mov r8w, word ptr [rsp + 4] \n"
" 04 \n"
" 0000209B 44/ 8B 44 24 mov r8d, dword ptr [rsp + 4] \n"
" 04 \n"
" 000020A0 4C/ 8B 44 24 mov r8, qword ptr [rsp + 4] \n"
" 04 \n"
" \n"
" 000020A5 41/ 88 60 FC mov byte ptr [r8 - 4], spl \n"
" 000020A9 41/ 88 60 04 mov byte ptr [r8 + 4], spl \n"
" 000020AD 66| 41/ 89 60 mov word ptr [r8 + 4], sp \n"
" 04 \n"
" 000020B2 41/ 89 60 04 mov dword ptr [r8 + 4], esp \n"
" 000020B6 49/ 89 60 04 mov qword ptr [r8 + 4], rsp \n"
" \n"
" 000020BA 66| 44/ 0F B6 C4 movzx r8w, spl \n"
" 000020BF 66| 44/ 0F B6 44 movzx r8w, byte ptr [rsp + 4] \n"
" 24 04 \n"
" \n"
" 000020C6 44/ 0F B6 C4 movzx r8d, spl \n"
" 000020CA 44/ 0F B7 C4 movzx r8d, sp \n"
" 000020CE 44/ 0F B6 44 24 movzx r8d, byte ptr [rsp + 4] \n"
" 04 \n"
" 000020D4 44/ 0F B7 44 24 movzx r8d, word ptr [rsp + 4] \n"
" 04 \n"
" \n"
" 000020DA 4C/ 0F B6 C4 movzx r8, spl \n"
" 000020DE 4C/ 0F B7 C4 movzx r8, sp \n"
" 000020E2 4C/ 0F B6 44 24 movzx r8, byte ptr [rsp + 4] \n"
" 04 \n"
" 000020E8 4C/ 0F B7 44 24 movzx r8, word ptr [rsp + 4] \n"
" 04 \n"
" \n"
" \n"
" ; Source: rsp, target: r9 \n"
" 000020EE 41/ B1 01 mov r9b, 1 \n"
" 000020F1 66| 41/ B9 mov r9w, 1 \n"
" 0001 \n"
" 000020F6 41/ B9 mov r9d, 1 \n"
" 00000001 \n"
" 000020FC 49/ C7 C1 mov r9, 1 \n"
" 00000001 \n"
" \n"
" 00002103 44/ 8A CC mov r9b, spl \n"
" 00002106 66| 44/ 8B CC mov r9w, sp \n"
" 0000210A 44/ 8B CC mov r9d, esp \n"
" 0000210D 4C/ 8B CC mov r9, rsp \n"
" \n"
" 00002110 44/ 8A 4C 24 mov r9b, byte ptr [rsp - 4] \n"
" FC \n"
" 00002115 44/ 8A 4C 24 mov r9b, byte ptr [rsp + 4] \n"
" 04 \n"
" 0000211A 66| 44/ 8B 4C 24 mov r9w, word ptr [rsp + 4] \n"
" 04 \n"
" 00002120 44/ 8B 4C 24 mov r9d, dword ptr [rsp + 4] \n"
" 04 \n"
" 00002125 4C/ 8B 4C 24 mov r9, qword ptr [rsp + 4] \n"
" 04 \n"
" \n"
" 0000212A 41/ 88 61 FC mov byte ptr [r9 - 4], spl \n"
" 0000212E 41/ 88 61 04 mov byte ptr [r9 + 4], spl \n"
" 00002132 66| 41/ 89 61 mov word ptr [r9 + 4], sp \n"
" 04 \n"
" 00002137 41/ 89 61 04 mov dword ptr [r9 + 4], esp \n"
" 0000213B 49/ 89 61 04 mov qword ptr [r9 + 4], rsp \n"
" \n"
" 0000213F 66| 44/ 0F B6 CC movzx r9w, spl \n"
" 00002144 66| 44/ 0F B6 4C movzx r9w, byte ptr [rsp + 4] \n"
" 24 04 \n"
" \n"
" 0000214B 44/ 0F B6 CC movzx r9d, spl \n"
" 0000214F 44/ 0F B7 CC movzx r9d, sp \n"
" 00002153 44/ 0F B6 4C 24 movzx r9d, byte ptr [rsp + 4] \n"
" 04 \n"
" 00002159 44/ 0F B7 4C 24 movzx r9d, word ptr [rsp + 4] \n"
" 04 \n"
" \n";
ml64Output +=
" 0000215F 4C/ 0F B6 CC movzx r9, spl \n"
" 00002163 4C/ 0F B7 CC movzx r9, sp \n"
" 00002167 4C/ 0F B6 4C 24 movzx r9, byte ptr [rsp + 4] \n"
" 04 \n"
" 0000216D 4C/ 0F B7 4C 24 movzx r9, word ptr [rsp + 4] \n"
" 04 \n"
" \n"
" \n"
" ; Source: rsp, target: r10 \n"
" 00002173 41/ B2 01 mov r10b, 1 \n"
" 00002176 66| 41/ BA mov r10w, 1 \n"
" 0001 \n"
" 0000217B 41/ BA mov r10d, 1 \n"
" 00000001 \n"
" 00002181 49/ C7 C2 mov r10, 1 \n"
" 00000001 \n"
" \n"
" 00002188 44/ 8A D4 mov r10b, spl \n"
" 0000218B 66| 44/ 8B D4 mov r10w, sp \n"
" 0000218F 44/ 8B D4 mov r10d, esp \n"
" 00002192 4C/ 8B D4 mov r10, rsp \n"
" \n"
" 00002195 44/ 8A 54 24 mov r10b, byte ptr [rsp - 4] \n"
" FC \n"
" 0000219A 44/ 8A 54 24 mov r10b, byte ptr [rsp + 4] \n"
" 04 \n"
" 0000219F 66| 44/ 8B 54 24 mov r10w, word ptr [rsp + 4] \n"
" 04 \n"
" 000021A5 44/ 8B 54 24 mov r10d, dword ptr [rsp + 4] \n"
" 04 \n"
" 000021AA 4C/ 8B 54 24 mov r10, qword ptr [rsp + 4] \n"
" 04 \n"
" \n"
" 000021AF 41/ 88 62 FC mov byte ptr [r10 - 4], spl \n"
" 000021B3 41/ 88 62 04 mov byte ptr [r10 + 4], spl \n"
" 000021B7 66| 41/ 89 62 mov word ptr [r10 + 4], sp \n"
" 04 \n"
" 000021BC 41/ 89 62 04 mov dword ptr [r10 + 4], esp \n"
" 000021C0 49/ 89 62 04 mov qword ptr [r10 + 4], rsp \n"
" \n"
" 000021C4 66| 44/ 0F B6 D4 movzx r10w, spl \n"
" 000021C9 66| 44/ 0F B6 54 movzx r10w, byte ptr [rsp + 4] \n"
" 24 04 \n"
" \n"
" 000021D0 44/ 0F B6 D4 movzx r10d, spl \n"
" 000021D4 44/ 0F B7 D4 movzx r10d, sp \n"
" 000021D8 44/ 0F B6 54 24 movzx r10d, byte ptr [rsp + 4] \n"
" 04 \n"
" 000021DE 44/ 0F B7 54 24 movzx r10d, word ptr [rsp + 4] \n"
" 04 \n"
" \n"
" 000021E4 4C/ 0F B6 D4 movzx r10, spl \n"
" 000021E8 4C/ 0F B7 D4 movzx r10, sp \n"
" 000021EC 4C/ 0F B6 54 24 movzx r10, byte ptr [rsp + 4] \n"
" 04 \n"
" 000021F2 4C/ 0F B7 54 24 movzx r10, word ptr [rsp + 4] \n"
" 04 \n"
" \n"
" \n"
" ; Source: rsp, target: r11 \n"
" 000021F8 41/ B3 01 mov r11b, 1 \n"
" 000021FB 66| 41/ BB mov r11w, 1 \n"
" 0001 \n"
" 00002200 41/ BB mov r11d, 1 \n"
" 00000001 \n"
" 00002206 49/ C7 C3 mov r11, 1 \n"
" 00000001 \n"
" \n"
" 0000220D 44/ 8A DC mov r11b, spl \n"
" 00002210 66| 44/ 8B DC mov r11w, sp \n"
" 00002214 44/ 8B DC mov r11d, esp \n"
" 00002217 4C/ 8B DC mov r11, rsp \n"
" \n"
" 0000221A 44/ 8A 5C 24 mov r11b, byte ptr [rsp - 4] \n"
" FC \n"
" 0000221F 44/ 8A 5C 24 mov r11b, byte ptr [rsp + 4] \n"
" 04 \n"
" 00002224 66| 44/ 8B 5C 24 mov r11w, word ptr [rsp + 4] \n"
" 04 \n"
" 0000222A 44/ 8B 5C 24 mov r11d, dword ptr [rsp + 4] \n"
" 04 \n"
" 0000222F 4C/ 8B 5C 24 mov r11, qword ptr [rsp + 4] \n"
" 04 \n"
" \n"
" 00002234 41/ 88 63 FC mov byte ptr [r11 - 4], spl \n"
" 00002238 41/ 88 63 04 mov byte ptr [r11 + 4], spl \n"
" 0000223C 66| 41/ 89 63 mov word ptr [r11 + 4], sp \n"
" 04 \n"
" 00002241 41/ 89 63 04 mov dword ptr [r11 + 4], esp \n"
" 00002245 49/ 89 63 04 mov qword ptr [r11 + 4], rsp \n"
" \n"
" 00002249 66| 44/ 0F B6 DC movzx r11w, spl \n"
" 0000224E 66| 44/ 0F B6 5C movzx r11w, byte ptr [rsp + 4] \n"
" 24 04 \n"
" \n"
" 00002255 44/ 0F B6 DC movzx r11d, spl \n"
" 00002259 44/ 0F B7 DC movzx r11d, sp \n"
" 0000225D 44/ 0F B6 5C 24 movzx r11d, byte ptr [rsp + 4] \n"
" 04 \n"
" 00002263 44/ 0F B7 5C 24 movzx r11d, word ptr [rsp + 4] \n"
" 04 \n"
" \n"
" 00002269 4C/ 0F B6 DC movzx r11, spl \n"
" 0000226D 4C/ 0F B7 DC movzx r11, sp \n"
" 00002271 4C/ 0F B6 5C 24 movzx r11, byte ptr [rsp + 4] \n"
" 04 \n"
" 00002277 4C/ 0F B7 5C 24 movzx r11, word ptr [rsp + 4] \n"
" 04 \n"
" \n"
" \n"
" ; Source: rsp, target: r12 \n"
" 0000227D 41/ B4 01 mov r12b, 1 \n"
" 00002280 66| 41/ BC mov r12w, 1 \n"
" 0001 \n"
" 00002285 41/ BC mov r12d, 1 \n"
" 00000001 \n"
" 0000228B 49/ C7 C4 mov r12, 1 \n"
" 00000001 \n"
" \n"
" 00002292 44/ 8A E4 mov r12b, spl \n"
" 00002295 66| 44/ 8B E4 mov r12w, sp \n"
" 00002299 44/ 8B E4 mov r12d, esp \n"
" 0000229C 4C/ 8B E4 mov r12, rsp \n"
" \n"
" 0000229F 44/ 8A 64 24 mov r12b, byte ptr [rsp - 4] \n"
" FC \n"
" 000022A4 44/ 8A 64 24 mov r12b, byte ptr [rsp + 4] \n"
" 04 \n"
" 000022A9 66| 44/ 8B 64 24 mov r12w, word ptr [rsp + 4] \n"
" 04 \n"
" 000022AF 44/ 8B 64 24 mov r12d, dword ptr [rsp + 4] \n"
" 04 \n"
" 000022B4 4C/ 8B 64 24 mov r12, qword ptr [rsp + 4] \n"
" 04 \n"
" \n"
" 000022B9 41/ 88 64 24 mov byte ptr [r12 - 4], spl \n"
" FC \n"
" 000022BE 41/ 88 64 24 mov byte ptr [r12 + 4], spl \n"
" 04 \n"
" 000022C3 66| 41/ 89 64 24 mov word ptr [r12 + 4], sp \n"
" 04 \n"
" 000022C9 41/ 89 64 24 mov dword ptr [r12 + 4], esp \n"
" 04 \n"
" 000022CE 49/ 89 64 24 mov qword ptr [r12 + 4], rsp \n"
" 04 \n"
" \n"
" 000022D3 66| 44/ 0F B6 E4 movzx r12w, spl \n"
" 000022D8 66| 44/ 0F B6 64 movzx r12w, byte ptr [rsp + 4] \n"
" 24 04 \n"
" \n"
" 000022DF 44/ 0F B6 E4 movzx r12d, spl \n"
" 000022E3 44/ 0F B7 E4 movzx r12d, sp \n"
" 000022E7 44/ 0F B6 64 24 movzx r12d, byte ptr [rsp + 4] \n"
" 04 \n"
" 000022ED 44/ 0F B7 64 24 movzx r12d, word ptr [rsp + 4] \n"
" 04 \n"
" \n"
" 000022F3 4C/ 0F B6 E4 movzx r12, spl \n"
" 000022F7 4C/ 0F B7 E4 movzx r12, sp \n"
" 000022FB 4C/ 0F B6 64 24 movzx r12, byte ptr [rsp + 4] \n"
" 04 \n"
" 00002301 4C/ 0F B7 64 24 movzx r12, word ptr [rsp + 4] \n"
" 04 \n"
" \n"
" \n"
" ; Source: rsp, target: r13 \n"
" 00002307 41/ B5 01 mov r13b, 1 \n"
" 0000230A 66| 41/ BD mov r13w, 1 \n"
" 0001 \n"
" 0000230F 41/ BD mov r13d, 1 \n"
" 00000001 \n"
" 00002315 49/ C7 C5 mov r13, 1 \n"
" 00000001 \n"
" \n"
" 0000231C 44/ 8A EC mov r13b, spl \n"
" 0000231F 66| 44/ 8B EC mov r13w, sp \n"
" 00002323 44/ 8B EC mov r13d, esp \n"
" 00002326 4C/ 8B EC mov r13, rsp \n"
" \n"
" 00002329 44/ 8A 6C 24 mov r13b, byte ptr [rsp - 4] \n"
" FC \n"
" 0000232E 44/ 8A 6C 24 mov r13b, byte ptr [rsp + 4] \n"
" 04 \n"
" 00002333 66| 44/ 8B 6C 24 mov r13w, word ptr [rsp + 4] \n"
" 04 \n"
" 00002339 44/ 8B 6C 24 mov r13d, dword ptr [rsp + 4] \n"
" 04 \n"
" 0000233E 4C/ 8B 6C 24 mov r13, qword ptr [rsp + 4] \n"
" 04 \n"
" \n"
" 00002343 41/ 88 65 FC mov byte ptr [r13 - 4], spl \n"
" 00002347 41/ 88 65 04 mov byte ptr [r13 + 4], spl \n"
" 0000234B 66| 41/ 89 65 mov word ptr [r13 + 4], sp \n"
" 04 \n"
" 00002350 41/ 89 65 04 mov dword ptr [r13 + 4], esp \n"
" 00002354 49/ 89 65 04 mov qword ptr [r13 + 4], rsp \n"
" \n"
" 00002358 66| 44/ 0F B6 EC movzx r13w, spl \n"
" 0000235D 66| 44/ 0F B6 6C movzx r13w, byte ptr [rsp + 4] \n"
" 24 04 \n"
" \n"
" 00002364 44/ 0F B6 EC movzx r13d, spl \n"
" 00002368 44/ 0F B7 EC movzx r13d, sp \n"
" 0000236C 44/ 0F B6 6C 24 movzx r13d, byte ptr [rsp + 4] \n"
" 04 \n"
" 00002372 44/ 0F B7 6C 24 movzx r13d, word ptr [rsp + 4] \n"
" 04 \n"
" \n"
" 00002378 4C/ 0F B6 EC movzx r13, spl \n"
" 0000237C 4C/ 0F B7 EC movzx r13, sp \n"
" 00002380 4C/ 0F B6 6C 24 movzx r13, byte ptr [rsp + 4] \n"
" 04 \n"
" 00002386 4C/ 0F B7 6C 24 movzx r13, word ptr [rsp + 4] \n"
" 04 \n"
" \n"
" \n"
" ; Source: rsp, target: r14 \n"
" 0000238C 41/ B6 01 mov r14b, 1 \n"
" 0000238F 66| 41/ BE mov r14w, 1 \n"
" 0001 \n"
" 00002394 41/ BE mov r14d, 1 \n"
" 00000001 \n"
" 0000239A 49/ C7 C6 mov r14, 1 \n"
" 00000001 \n"
" \n"
" 000023A1 44/ 8A F4 mov r14b, spl \n"
" 000023A4 66| 44/ 8B F4 mov r14w, sp \n"
" 000023A8 44/ 8B F4 mov r14d, esp \n"
" 000023AB 4C/ 8B F4 mov r14, rsp \n"
" \n"
" 000023AE 44/ 8A 74 24 mov r14b, byte ptr [rsp - 4] \n"
" FC \n"
" 000023B3 44/ 8A 74 24 mov r14b, byte ptr [rsp + 4] \n"
" 04 \n"
" 000023B8 66| 44/ 8B 74 24 mov r14w, word ptr [rsp + 4] \n"
" 04 \n"
" 000023BE 44/ 8B 74 24 mov r14d, dword ptr [rsp + 4] \n"
" 04 \n"
" 000023C3 4C/ 8B 74 24 mov r14, qword ptr [rsp + 4] \n"
" 04 \n"
" \n"
" 000023C8 41/ 88 66 FC mov byte ptr [r14 - 4], spl \n"
" 000023CC 41/ 88 66 04 mov byte ptr [r14 + 4], spl \n"
" 000023D0 66| 41/ 89 66 mov word ptr [r14 + 4], sp \n"
" 04 \n"
" 000023D5 41/ 89 66 04 mov dword ptr [r14 + 4], esp \n"
" 000023D9 49/ 89 66 04 mov qword ptr [r14 + 4], rsp \n"
" \n"
" 000023DD 66| 44/ 0F B6 F4 movzx r14w, spl \n"
" 000023E2 66| 44/ 0F B6 74 movzx r14w, byte ptr [rsp + 4] \n"
" 24 04 \n"
" \n"
" 000023E9 44/ 0F B6 F4 movzx r14d, spl \n"
" 000023ED 44/ 0F B7 F4 movzx r14d, sp \n"
" 000023F1 44/ 0F B6 74 24 movzx r14d, byte ptr [rsp + 4] \n"
" 04 \n"
" 000023F7 44/ 0F B7 74 24 movzx r14d, word ptr [rsp + 4] \n"
" 04 \n"
" \n"
" 000023FD 4C/ 0F B6 F4 movzx r14, spl \n"
" 00002401 4C/ 0F B7 F4 movzx r14, sp \n"
" 00002405 4C/ 0F B6 74 24 movzx r14, byte ptr [rsp + 4] \n"
" 04 \n"
" 0000240B 4C/ 0F B7 74 24 movzx r14, word ptr [rsp + 4] \n"
" 04 \n"
" \n"
" \n"
" ; Source: rsp, target: r15 \n"
" 00002411 41/ B7 01 mov r15b, 1 \n"
" 00002414 66| 41/ BF mov r15w, 1 \n"
" 0001 \n"
" 00002419 41/ BF mov r15d, 1 \n"
" 00000001 \n"
" 0000241F 49/ C7 C7 mov r15, 1 \n"
" 00000001 \n"
" \n"
" 00002426 44/ 8A FC mov r15b, spl \n"
" 00002429 66| 44/ 8B FC mov r15w, sp \n"
" 0000242D 44/ 8B FC mov r15d, esp \n"
" 00002430 4C/ 8B FC mov r15, rsp \n"
" \n"
" 00002433 44/ 8A 7C 24 mov r15b, byte ptr [rsp - 4] \n"
" FC \n"
" 00002438 44/ 8A 7C 24 mov r15b, byte ptr [rsp + 4] \n"
" 04 \n"
" 0000243D 66| 44/ 8B 7C 24 mov r15w, word ptr [rsp + 4] \n"
" 04 \n"
" 00002443 44/ 8B 7C 24 mov r15d, dword ptr [rsp + 4] \n"
" 04 \n"
" 00002448 4C/ 8B 7C 24 mov r15, qword ptr [rsp + 4] \n"
" 04 \n"
" \n"
" 0000244D 41/ 88 67 FC mov byte ptr [r15 - 4], spl \n"
" 00002451 41/ 88 67 04 mov byte ptr [r15 + 4], spl \n"
" 00002455 66| 41/ 89 67 mov word ptr [r15 + 4], sp \n"
" 04 \n"
" 0000245A 41/ 89 67 04 mov dword ptr [r15 + 4], esp \n"
" 0000245E 49/ 89 67 04 mov qword ptr [r15 + 4], rsp \n"
" \n"
" 00002462 66| 44/ 0F B6 FC movzx r15w, spl \n"
" 00002467 66| 44/ 0F B6 7C movzx r15w, byte ptr [rsp + 4] \n"
" 24 04 \n"
" \n"
" 0000246E 44/ 0F B6 FC movzx r15d, spl \n"
" 00002472 44/ 0F B7 FC movzx r15d, sp \n"
" 00002476 44/ 0F B6 7C 24 movzx r15d, byte ptr [rsp + 4] \n"
" 04 \n"
" 0000247C 44/ 0F B7 7C 24 movzx r15d, word ptr [rsp + 4] \n"
" 04 \n"
" \n"
" 00002482 4C/ 0F B6 FC movzx r15, spl \n"
" 00002486 4C/ 0F B7 FC movzx r15, sp \n"
" 0000248A 4C/ 0F B6 7C 24 movzx r15, byte ptr [rsp + 4] \n"
" 04 \n"
" 00002490 4C/ 0F B7 7C 24 movzx r15, word ptr [rsp + 4] \n"
" 04 \n"
" \n"
" \n"
" ; Source: rbp, target: rax \n"
" 00002496 B0 01 mov al, 1 \n"
" 00002498 66| B8 0001 mov ax, 1 \n"
" 0000249C B8 00000001 mov eax, 1 \n"
" 000024A1 48/ C7 C0 mov rax, 1 \n"
" 00000001 \n"
" \n"
" 000024A8 40/ 8A C5 mov al, bpl \n"
" 000024AB 66| 8B C5 mov ax, bp \n"
" 000024AE 8B C5 mov eax, ebp \n"
" 000024B0 48/ 8B C5 mov rax, rbp \n"
" \n"
" 000024B3 8A 45 FC mov al, byte ptr [rbp - 4] \n"
" 000024B6 8A 45 04 mov al, byte ptr [rbp + 4] \n"
" 000024B9 66| 8B 45 04 mov ax, word ptr [rbp + 4] \n"
" 000024BD 8B 45 04 mov eax, dword ptr [rbp + 4] \n"
" 000024C0 48/ 8B 45 04 mov rax, qword ptr [rbp + 4] \n"
" \n"
" 000024C4 40/ 88 68 FC mov byte ptr [rax - 4], bpl \n"
" 000024C8 40/ 88 68 04 mov byte ptr [rax + 4], bpl \n"
" 000024CC 66| 89 68 04 mov word ptr [rax + 4], bp \n"
" 000024D0 89 68 04 mov dword ptr [rax + 4], ebp \n"
" 000024D3 48/ 89 68 04 mov qword ptr [rax + 4], rbp \n"
" \n"
" 000024D7 66| 40/ 0F B6 C5 movzx ax, bpl \n"
" 000024DC 66| 0F B6 45 movzx ax, byte ptr [rbp + 4] \n"
" 04 \n"
" \n"
" 000024E1 40/ 0F B6 C5 movzx eax, bpl \n"
" 000024E5 0F B7 C5 movzx eax, bp \n"
" 000024E8 0F B6 45 04 movzx eax, byte ptr [rbp + 4] \n"
" 000024EC 0F B7 45 04 movzx eax, word ptr [rbp + 4] \n"
" \n"
" 000024F0 48/ 0F B6 C5 movzx rax, bpl \n"
" 000024F4 48/ 0F B7 C5 movzx rax, bp \n"
" 000024F8 48/ 0F B6 45 movzx rax, byte ptr [rbp + 4] \n"
" 04 \n"
" 000024FD 48/ 0F B7 45 movzx rax, word ptr [rbp + 4] \n"
" 04 \n"
" \n"
" \n"
" ; Source: rbp, target: rcx \n"
" 00002502 B1 01 mov cl, 1 \n"
" 00002504 66| B9 0001 mov cx, 1 \n"
" 00002508 B9 00000001 mov ecx, 1 \n"
" 0000250D 48/ C7 C1 mov rcx, 1 \n"
" 00000001 \n"
" \n"
" 00002514 40/ 8A CD mov cl, bpl \n"
" 00002517 66| 8B CD mov cx, bp \n"
" 0000251A 8B CD mov ecx, ebp \n"
" 0000251C 48/ 8B CD mov rcx, rbp \n"
" \n"
" 0000251F 8A 4D FC mov cl, byte ptr [rbp - 4] \n"
" 00002522 8A 4D 04 mov cl, byte ptr [rbp + 4] \n"
" 00002525 66| 8B 4D 04 mov cx, word ptr [rbp + 4] \n"
" 00002529 8B 4D 04 mov ecx, dword ptr [rbp + 4] \n"
" 0000252C 48/ 8B 4D 04 mov rcx, qword ptr [rbp + 4] \n"
" \n"
" 00002530 40/ 88 69 FC mov byte ptr [rcx - 4], bpl \n"
" 00002534 40/ 88 69 04 mov byte ptr [rcx + 4], bpl \n"
" 00002538 66| 89 69 04 mov word ptr [rcx + 4], bp \n"
" 0000253C 89 69 04 mov dword ptr [rcx + 4], ebp \n"
" 0000253F 48/ 89 69 04 mov qword ptr [rcx + 4], rbp \n"
" \n"
" 00002543 66| 40/ 0F B6 CD movzx cx, bpl \n"
" 00002548 66| 0F B6 4D movzx cx, byte ptr [rbp + 4] \n"
" 04 \n"
" \n"
" 0000254D 40/ 0F B6 CD movzx ecx, bpl \n"
" 00002551 0F B7 CD movzx ecx, bp \n"
" 00002554 0F B6 4D 04 movzx ecx, byte ptr [rbp + 4] \n"
" 00002558 0F B7 4D 04 movzx ecx, word ptr [rbp + 4] \n"
" \n"
" 0000255C 48/ 0F B6 CD movzx rcx, bpl \n"
" 00002560 48/ 0F B7 CD movzx rcx, bp \n"
" 00002564 48/ 0F B6 4D movzx rcx, byte ptr [rbp + 4] \n"
" 04 \n"
" 00002569 48/ 0F B7 4D movzx rcx, word ptr [rbp + 4] \n"
" 04 \n"
" \n"
" \n"
" ; Source: rbp, target: rdx \n"
" 0000256E B2 01 mov dl, 1 \n"
" 00002570 66| BA 0001 mov dx, 1 \n"
" 00002574 BA 00000001 mov edx, 1 \n"
" 00002579 48/ C7 C2 mov rdx, 1 \n"
" 00000001 \n"
" \n"
" 00002580 40/ 8A D5 mov dl, bpl \n"
" 00002583 66| 8B D5 mov dx, bp \n"
" 00002586 8B D5 mov edx, ebp \n"
" 00002588 48/ 8B D5 mov rdx, rbp \n"
" \n"
" 0000258B 8A 55 FC mov dl, byte ptr [rbp - 4] \n"
" 0000258E 8A 55 04 mov dl, byte ptr [rbp + 4] \n"
" 00002591 66| 8B 55 04 mov dx, word ptr [rbp + 4] \n"
" 00002595 8B 55 04 mov edx, dword ptr [rbp + 4] \n"
" 00002598 48/ 8B 55 04 mov rdx, qword ptr [rbp + 4] \n"
" \n"
" 0000259C 40/ 88 6A FC mov byte ptr [rdx - 4], bpl \n"
" 000025A0 40/ 88 6A 04 mov byte ptr [rdx + 4], bpl \n"
" 000025A4 66| 89 6A 04 mov word ptr [rdx + 4], bp \n"
" 000025A8 89 6A 04 mov dword ptr [rdx + 4], ebp \n"
" 000025AB 48/ 89 6A 04 mov qword ptr [rdx + 4], rbp \n"
" \n"
" 000025AF 66| 40/ 0F B6 D5 movzx dx, bpl \n"
" 000025B4 66| 0F B6 55 movzx dx, byte ptr [rbp + 4] \n"
" 04 \n"
" \n"
" 000025B9 40/ 0F B6 D5 movzx edx, bpl \n"
" 000025BD 0F B7 D5 movzx edx, bp \n"
" 000025C0 0F B6 55 04 movzx edx, byte ptr [rbp + 4] \n"
" 000025C4 0F B7 55 04 movzx edx, word ptr [rbp + 4] \n"
" \n"
" 000025C8 48/ 0F B6 D5 movzx rdx, bpl \n"
" 000025CC 48/ 0F B7 D5 movzx rdx, bp \n"
" 000025D0 48/ 0F B6 55 movzx rdx, byte ptr [rbp + 4] \n"
" 04 \n"
" 000025D5 48/ 0F B7 55 movzx rdx, word ptr [rbp + 4] \n"
" 04 \n"
" \n"
" \n"
" ; Source: rbp, target: rbx \n"
" 000025DA B3 01 mov bl, 1 \n"
" 000025DC 66| BB 0001 mov bx, 1 \n"
" 000025E0 BB 00000001 mov ebx, 1 \n"
" 000025E5 48/ C7 C3 mov rbx, 1 \n"
" 00000001 \n"
" \n"
" 000025EC 40/ 8A DD mov bl, bpl \n"
" 000025EF 66| 8B DD mov bx, bp \n"
" 000025F2 8B DD mov ebx, ebp \n"
" 000025F4 48/ 8B DD mov rbx, rbp \n"
" \n"
" 000025F7 8A 5D FC mov bl, byte ptr [rbp - 4] \n"
" 000025FA 8A 5D 04 mov bl, byte ptr [rbp + 4] \n"
" 000025FD 66| 8B 5D 04 mov bx, word ptr [rbp + 4] \n"
" 00002601 8B 5D 04 mov ebx, dword ptr [rbp + 4] \n"
" 00002604 48/ 8B 5D 04 mov rbx, qword ptr [rbp + 4] \n"
" \n"
" 00002608 40/ 88 6B FC mov byte ptr [rbx - 4], bpl \n"
" 0000260C 40/ 88 6B 04 mov byte ptr [rbx + 4], bpl \n"
" 00002610 66| 89 6B 04 mov word ptr [rbx + 4], bp \n"
" 00002614 89 6B 04 mov dword ptr [rbx + 4], ebp \n"
" 00002617 48/ 89 6B 04 mov qword ptr [rbx + 4], rbp \n"
" \n"
" 0000261B 66| 40/ 0F B6 DD movzx bx, bpl \n"
" 00002620 66| 0F B6 5D movzx bx, byte ptr [rbp + 4] \n"
" 04 \n"
" \n"
" 00002625 40/ 0F B6 DD movzx ebx, bpl \n"
" 00002629 0F B7 DD movzx ebx, bp \n"
" 0000262C 0F B6 5D 04 movzx ebx, byte ptr [rbp + 4] \n"
" 00002630 0F B7 5D 04 movzx ebx, word ptr [rbp + 4] \n"
" \n"
" 00002634 48/ 0F B6 DD movzx rbx, bpl \n"
" 00002638 48/ 0F B7 DD movzx rbx, bp \n"
" 0000263C 48/ 0F B6 5D movzx rbx, byte ptr [rbp + 4] \n"
" 04 \n"
" 00002641 48/ 0F B7 5D movzx rbx, word ptr [rbp + 4] \n"
" 04 \n"
" \n"
" \n"
" ; Source: rbp, target: rsp \n"
" 00002646 40/ B4 01 mov spl, 1 \n"
" 00002649 66| BC 0001 mov sp, 1 \n"
" 0000264D BC 00000001 mov esp, 1 \n"
" 00002652 48/ C7 C4 mov rsp, 1 \n"
" 00000001 \n"
" \n"
" 00002659 40/ 8A E5 mov spl, bpl \n"
" 0000265C 66| 8B E5 mov sp, bp \n"
" 0000265F 8B E5 mov esp, ebp \n"
" 00002661 48/ 8B E5 mov rsp, rbp \n"
" \n"
" 00002664 40/ 8A 65 FC mov spl, byte ptr [rbp - 4] \n"
" 00002668 40/ 8A 65 04 mov spl, byte ptr [rbp + 4] \n"
" 0000266C 66| 8B 65 04 mov sp, word ptr [rbp + 4] \n"
" 00002670 8B 65 04 mov esp, dword ptr [rbp + 4] \n"
" 00002673 48/ 8B 65 04 mov rsp, qword ptr [rbp + 4] \n"
" \n"
" 00002677 40/ 88 6C 24 mov byte ptr [rsp - 4], bpl \n"
" FC \n"
" 0000267C 40/ 88 6C 24 mov byte ptr [rsp + 4], bpl \n"
" 04 \n"
" 00002681 66| 89 6C 24 mov word ptr [rsp + 4], bp \n"
" 04 \n"
" 00002686 89 6C 24 04 mov dword ptr [rsp + 4], ebp \n"
" 0000268A 48/ 89 6C 24 mov qword ptr [rsp + 4], rbp \n"
" 04 \n"
" \n"
" 0000268F 66| 40/ 0F B6 E5 movzx sp, bpl \n"
" 00002694 66| 0F B6 65 movzx sp, byte ptr [rbp + 4] \n"
" 04 \n"
" \n"
" 00002699 40/ 0F B6 E5 movzx esp, bpl \n"
" 0000269D 0F B7 E5 movzx esp, bp \n"
" 000026A0 0F B6 65 04 movzx esp, byte ptr [rbp + 4] \n"
" 000026A4 0F B7 65 04 movzx esp, word ptr [rbp + 4] \n"
" \n"
" 000026A8 48/ 0F B6 E5 movzx rsp, bpl \n"
" 000026AC 48/ 0F B7 E5 movzx rsp, bp \n"
" 000026B0 48/ 0F B6 65 movzx rsp, byte ptr [rbp + 4] \n"
" 04 \n"
" 000026B5 48/ 0F B7 65 movzx rsp, word ptr [rbp + 4] \n"
" 04 \n"
" \n"
" \n"
" ; Source: rbp, target: rbp \n"
" 000026BA 40/ B5 01 mov bpl, 1 \n"
" 000026BD 66| BD 0001 mov bp, 1 \n"
" 000026C1 BD 00000001 mov ebp, 1 \n"
" 000026C6 48/ C7 C5 mov rbp, 1 \n"
" 00000001 \n"
" \n"
" 000026CD 40/ 8A ED mov bpl, bpl \n"
" 000026D0 66| 8B ED mov bp, bp \n"
" 000026D3 8B ED mov ebp, ebp \n"
" 000026D5 48/ 8B ED mov rbp, rbp \n"
" \n"
" 000026D8 40/ 8A 6D FC mov bpl, byte ptr [rbp - 4] \n"
" 000026DC 40/ 8A 6D 04 mov bpl, byte ptr [rbp + 4] \n"
" 000026E0 66| 8B 6D 04 mov bp, word ptr [rbp + 4] \n"
" 000026E4 8B 6D 04 mov ebp, dword ptr [rbp + 4] \n"
" 000026E7 48/ 8B 6D 04 mov rbp, qword ptr [rbp + 4] \n"
" \n"
" 000026EB 40/ 88 6D FC mov byte ptr [rbp - 4], bpl \n"
" 000026EF 40/ 88 6D 04 mov byte ptr [rbp + 4], bpl \n"
" 000026F3 66| 89 6D 04 mov word ptr [rbp + 4], bp \n"
" 000026F7 89 6D 04 mov dword ptr [rbp + 4], ebp \n"
" 000026FA 48/ 89 6D 04 mov qword ptr [rbp + 4], rbp \n";
ml64Output +=
" \n"
" 000026FE 66| 40/ 0F B6 ED movzx bp, bpl \n"
" 00002703 66| 0F B6 6D movzx bp, byte ptr [rbp + 4] \n"
" 04 \n"
" \n"
" 00002708 40/ 0F B6 ED movzx ebp, bpl \n"
" 0000270C 0F B7 ED movzx ebp, bp \n"
" 0000270F 0F B6 6D 04 movzx ebp, byte ptr [rbp + 4] \n"
" 00002713 0F B7 6D 04 movzx ebp, word ptr [rbp + 4] \n"
" \n"
" 00002717 48/ 0F B6 ED movzx rbp, bpl \n"
" 0000271B 48/ 0F B7 ED movzx rbp, bp \n"
" 0000271F 48/ 0F B6 6D movzx rbp, byte ptr [rbp + 4] \n"
" 04 \n"
" 00002724 48/ 0F B7 6D movzx rbp, word ptr [rbp + 4] \n"
" 04 \n"
" \n"
" \n"
" ; Source: rbp, target: rsi \n"
" 00002729 40/ B7 01 mov dil, 1 \n"
" 0000272C 66| BE 0001 mov si, 1 \n"
" 00002730 BE 00000001 mov esi, 1 \n"
" 00002735 48/ C7 C6 mov rsi, 1 \n"
" 00000001 \n"
" \n"
" 0000273C 40/ 8A FD mov dil, bpl \n"
" 0000273F 66| 8B F5 mov si, bp \n"
" 00002742 8B F5 mov esi, ebp \n"
" 00002744 48/ 8B F5 mov rsi, rbp \n"
" \n"
" 00002747 40/ 8A 7D FC mov dil, byte ptr [rbp - 4] \n"
" 0000274B 40/ 8A 7D 04 mov dil, byte ptr [rbp + 4] \n"
" 0000274F 66| 8B 75 04 mov si, word ptr [rbp + 4] \n"
" 00002753 8B 75 04 mov esi, dword ptr [rbp + 4] \n"
" 00002756 48/ 8B 75 04 mov rsi, qword ptr [rbp + 4] \n"
" \n"
" 0000275A 40/ 88 6E FC mov byte ptr [rsi - 4], bpl \n"
" 0000275E 40/ 88 6E 04 mov byte ptr [rsi + 4], bpl \n"
" 00002762 66| 89 6E 04 mov word ptr [rsi + 4], bp \n"
" 00002766 89 6E 04 mov dword ptr [rsi + 4], ebp \n"
" 00002769 48/ 89 6E 04 mov qword ptr [rsi + 4], rbp \n"
" \n"
" 0000276D 66| 40/ 0F B6 F5 movzx si, bpl \n"
" 00002772 66| 0F B6 75 movzx si, byte ptr [rbp + 4] \n"
" 04 \n"
" \n"
" 00002777 40/ 0F B6 F5 movzx esi, bpl \n"
" 0000277B 0F B7 F5 movzx esi, bp \n"
" 0000277E 0F B6 75 04 movzx esi, byte ptr [rbp + 4] \n"
" 00002782 0F B7 75 04 movzx esi, word ptr [rbp + 4] \n"
" \n"
" 00002786 48/ 0F B6 F5 movzx rsi, bpl \n"
" 0000278A 48/ 0F B7 F5 movzx rsi, bp \n"
" 0000278E 48/ 0F B6 75 movzx rsi, byte ptr [rbp + 4] \n"
" 04 \n"
" 00002793 48/ 0F B7 75 movzx rsi, word ptr [rbp + 4] \n"
" 04 \n"
" \n"
" \n"
" ; Source: rbp, target: rdi \n"
" 00002798 40/ B6 01 mov sil, 1 \n"
" 0000279B 66| BF 0001 mov di, 1 \n"
" 0000279F BF 00000001 mov edi, 1 \n"
" 000027A4 48/ C7 C7 mov rdi, 1 \n"
" 00000001 \n"
" \n"
" 000027AB 40/ 8A F5 mov sil, bpl \n"
" 000027AE 66| 8B FD mov di, bp \n"
" 000027B1 8B FD mov edi, ebp \n"
" 000027B3 48/ 8B FD mov rdi, rbp \n"
" \n"
" 000027B6 40/ 8A 75 FC mov sil, byte ptr [rbp - 4] \n"
" 000027BA 40/ 8A 75 04 mov sil, byte ptr [rbp + 4] \n"
" 000027BE 66| 8B 7D 04 mov di, word ptr [rbp + 4] \n"
" 000027C2 8B 7D 04 mov edi, dword ptr [rbp + 4] \n"
" 000027C5 48/ 8B 7D 04 mov rdi, qword ptr [rbp + 4] \n"
" \n"
" 000027C9 40/ 88 6F FC mov byte ptr [rdi - 4], bpl \n"
" 000027CD 40/ 88 6F 04 mov byte ptr [rdi + 4], bpl \n"
" 000027D1 66| 89 6F 04 mov word ptr [rdi + 4], bp \n"
" 000027D5 89 6F 04 mov dword ptr [rdi + 4], ebp \n"
" 000027D8 48/ 89 6F 04 mov qword ptr [rdi + 4], rbp \n"
" \n"
" 000027DC 66| 40/ 0F B6 FD movzx di, bpl \n"
" 000027E1 66| 0F B6 7D movzx di, byte ptr [rbp + 4] \n"
" 04 \n"
" \n"
" 000027E6 40/ 0F B6 FD movzx edi, bpl \n"
" 000027EA 0F B7 FD movzx edi, bp \n"
" 000027ED 0F B6 7D 04 movzx edi, byte ptr [rbp + 4] \n"
" 000027F1 0F B7 7D 04 movzx edi, word ptr [rbp + 4] \n"
" \n"
" 000027F5 48/ 0F B6 FD movzx rdi, bpl \n"
" 000027F9 48/ 0F B7 FD movzx rdi, bp \n"
" 000027FD 48/ 0F B6 7D movzx rdi, byte ptr [rbp + 4] \n"
" 04 \n"
" 00002802 48/ 0F B7 7D movzx rdi, word ptr [rbp + 4] \n"
" 04 \n"
" \n"
" \n"
" ; Source: rbp, target: r8 \n"
" 00002807 41/ B0 01 mov r8b, 1 \n"
" 0000280A 66| 41/ B8 mov r8w, 1 \n"
" 0001 \n"
" 0000280F 41/ B8 mov r8d, 1 \n"
" 00000001 \n"
" 00002815 49/ C7 C0 mov r8, 1 \n"
" 00000001 \n"
" \n"
" 0000281C 44/ 8A C5 mov r8b, bpl \n"
" 0000281F 66| 44/ 8B C5 mov r8w, bp \n"
" 00002823 44/ 8B C5 mov r8d, ebp \n"
" 00002826 4C/ 8B C5 mov r8, rbp \n"
" \n"
" 00002829 44/ 8A 45 FC mov r8b, byte ptr [rbp - 4] \n"
" 0000282D 44/ 8A 45 04 mov r8b, byte ptr [rbp + 4] \n"
" 00002831 66| 44/ 8B 45 mov r8w, word ptr [rbp + 4] \n"
" 04 \n"
" 00002836 44/ 8B 45 04 mov r8d, dword ptr [rbp + 4] \n"
" 0000283A 4C/ 8B 45 04 mov r8, qword ptr [rbp + 4] \n"
" \n"
" 0000283E 41/ 88 68 FC mov byte ptr [r8 - 4], bpl \n"
" 00002842 41/ 88 68 04 mov byte ptr [r8 + 4], bpl \n"
" 00002846 66| 41/ 89 68 mov word ptr [r8 + 4], bp \n"
" 04 \n"
" 0000284B 41/ 89 68 04 mov dword ptr [r8 + 4], ebp \n"
" 0000284F 49/ 89 68 04 mov qword ptr [r8 + 4], rbp \n"
" \n"
" 00002853 66| 44/ 0F B6 C5 movzx r8w, bpl \n"
" 00002858 66| 44/ 0F B6 45 movzx r8w, byte ptr [rbp + 4] \n"
" 04 \n"
" \n"
" 0000285E 44/ 0F B6 C5 movzx r8d, bpl \n"
" 00002862 44/ 0F B7 C5 movzx r8d, bp \n"
" 00002866 44/ 0F B6 45 movzx r8d, byte ptr [rbp + 4] \n"
" 04 \n"
" 0000286B 44/ 0F B7 45 movzx r8d, word ptr [rbp + 4] \n"
" 04 \n"
" \n"
" 00002870 4C/ 0F B6 C5 movzx r8, bpl \n"
" 00002874 4C/ 0F B7 C5 movzx r8, bp \n"
" 00002878 4C/ 0F B6 45 movzx r8, byte ptr [rbp + 4] \n"
" 04 \n"
" 0000287D 4C/ 0F B7 45 movzx r8, word ptr [rbp + 4] \n"
" 04 \n"
" \n"
" \n"
" ; Source: rbp, target: r9 \n"
" 00002882 41/ B1 01 mov r9b, 1 \n"
" 00002885 66| 41/ B9 mov r9w, 1 \n"
" 0001 \n"
" 0000288A 41/ B9 mov r9d, 1 \n"
" 00000001 \n"
" 00002890 49/ C7 C1 mov r9, 1 \n"
" 00000001 \n"
" \n"
" 00002897 44/ 8A CD mov r9b, bpl \n"
" 0000289A 66| 44/ 8B CD mov r9w, bp \n"
" 0000289E 44/ 8B CD mov r9d, ebp \n"
" 000028A1 4C/ 8B CD mov r9, rbp \n"
" \n"
" 000028A4 44/ 8A 4D FC mov r9b, byte ptr [rbp - 4] \n"
" 000028A8 44/ 8A 4D 04 mov r9b, byte ptr [rbp + 4] \n"
" 000028AC 66| 44/ 8B 4D mov r9w, word ptr [rbp + 4] \n"
" 04 \n"
" 000028B1 44/ 8B 4D 04 mov r9d, dword ptr [rbp + 4] \n"
" 000028B5 4C/ 8B 4D 04 mov r9, qword ptr [rbp + 4] \n"
" \n"
" 000028B9 41/ 88 69 FC mov byte ptr [r9 - 4], bpl \n"
" 000028BD 41/ 88 69 04 mov byte ptr [r9 + 4], bpl \n"
" 000028C1 66| 41/ 89 69 mov word ptr [r9 + 4], bp \n"
" 04 \n"
" 000028C6 41/ 89 69 04 mov dword ptr [r9 + 4], ebp \n"
" 000028CA 49/ 89 69 04 mov qword ptr [r9 + 4], rbp \n"
" \n"
" 000028CE 66| 44/ 0F B6 CD movzx r9w, bpl \n"
" 000028D3 66| 44/ 0F B6 4D movzx r9w, byte ptr [rbp + 4] \n"
" 04 \n"
" \n"
" 000028D9 44/ 0F B6 CD movzx r9d, bpl \n"
" 000028DD 44/ 0F B7 CD movzx r9d, bp \n"
" 000028E1 44/ 0F B6 4D movzx r9d, byte ptr [rbp + 4] \n"
" 04 \n"
" 000028E6 44/ 0F B7 4D movzx r9d, word ptr [rbp + 4] \n"
" 04 \n"
" \n"
" 000028EB 4C/ 0F B6 CD movzx r9, bpl \n"
" 000028EF 4C/ 0F B7 CD movzx r9, bp \n"
" 000028F3 4C/ 0F B6 4D movzx r9, byte ptr [rbp + 4] \n"
" 04 \n"
" 000028F8 4C/ 0F B7 4D movzx r9, word ptr [rbp + 4] \n"
" 04 \n"
" \n"
" \n"
" ; Source: rbp, target: r10 \n"
" 000028FD 41/ B2 01 mov r10b, 1 \n"
" 00002900 66| 41/ BA mov r10w, 1 \n"
" 0001 \n"
" 00002905 41/ BA mov r10d, 1 \n"
" 00000001 \n"
" 0000290B 49/ C7 C2 mov r10, 1 \n"
" 00000001 \n"
" \n"
" 00002912 44/ 8A D5 mov r10b, bpl \n"
" 00002915 66| 44/ 8B D5 mov r10w, bp \n"
" 00002919 44/ 8B D5 mov r10d, ebp \n"
" 0000291C 4C/ 8B D5 mov r10, rbp \n"
" \n"
" 0000291F 44/ 8A 55 FC mov r10b, byte ptr [rbp - 4] \n"
" 00002923 44/ 8A 55 04 mov r10b, byte ptr [rbp + 4] \n"
" 00002927 66| 44/ 8B 55 mov r10w, word ptr [rbp + 4] \n"
" 04 \n"
" 0000292C 44/ 8B 55 04 mov r10d, dword ptr [rbp + 4] \n"
" 00002930 4C/ 8B 55 04 mov r10, qword ptr [rbp + 4] \n"
" \n"
" 00002934 41/ 88 6A FC mov byte ptr [r10 - 4], bpl \n"
" 00002938 41/ 88 6A 04 mov byte ptr [r10 + 4], bpl \n"
" 0000293C 66| 41/ 89 6A mov word ptr [r10 + 4], bp \n"
" 04 \n"
" 00002941 41/ 89 6A 04 mov dword ptr [r10 + 4], ebp \n"
" 00002945 49/ 89 6A 04 mov qword ptr [r10 + 4], rbp \n"
" \n"
" 00002949 66| 44/ 0F B6 D5 movzx r10w, bpl \n"
" 0000294E 66| 44/ 0F B6 55 movzx r10w, byte ptr [rbp + 4] \n"
" 04 \n"
" \n"
" 00002954 44/ 0F B6 D5 movzx r10d, bpl \n"
" 00002958 44/ 0F B7 D5 movzx r10d, bp \n"
" 0000295C 44/ 0F B6 55 movzx r10d, byte ptr [rbp + 4] \n"
" 04 \n"
" 00002961 44/ 0F B7 55 movzx r10d, word ptr [rbp + 4] \n"
" 04 \n"
" \n"
" 00002966 4C/ 0F B6 D5 movzx r10, bpl \n"
" 0000296A 4C/ 0F B7 D5 movzx r10, bp \n"
" 0000296E 4C/ 0F B6 55 movzx r10, byte ptr [rbp + 4] \n"
" 04 \n"
" 00002973 4C/ 0F B7 55 movzx r10, word ptr [rbp + 4] \n"
" 04 \n"
" \n"
" \n"
" ; Source: rbp, target: r11 \n"
" 00002978 41/ B3 01 mov r11b, 1 \n"
" 0000297B 66| 41/ BB mov r11w, 1 \n"
" 0001 \n"
" 00002980 41/ BB mov r11d, 1 \n"
" 00000001 \n"
" 00002986 49/ C7 C3 mov r11, 1 \n"
" 00000001 \n"
" \n"
" 0000298D 44/ 8A DD mov r11b, bpl \n"
" 00002990 66| 44/ 8B DD mov r11w, bp \n"
" 00002994 44/ 8B DD mov r11d, ebp \n"
" 00002997 4C/ 8B DD mov r11, rbp \n"
" \n"
" 0000299A 44/ 8A 5D FC mov r11b, byte ptr [rbp - 4] \n"
" 0000299E 44/ 8A 5D 04 mov r11b, byte ptr [rbp + 4] \n"
" 000029A2 66| 44/ 8B 5D mov r11w, word ptr [rbp + 4] \n"
" 04 \n"
" 000029A7 44/ 8B 5D 04 mov r11d, dword ptr [rbp + 4] \n"
" 000029AB 4C/ 8B 5D 04 mov r11, qword ptr [rbp + 4] \n"
" \n"
" 000029AF 41/ 88 6B FC mov byte ptr [r11 - 4], bpl \n"
" 000029B3 41/ 88 6B 04 mov byte ptr [r11 + 4], bpl \n"
" 000029B7 66| 41/ 89 6B mov word ptr [r11 + 4], bp \n"
" 04 \n"
" 000029BC 41/ 89 6B 04 mov dword ptr [r11 + 4], ebp \n"
" 000029C0 49/ 89 6B 04 mov qword ptr [r11 + 4], rbp \n"
" \n"
" 000029C4 66| 44/ 0F B6 DD movzx r11w, bpl \n"
" 000029C9 66| 44/ 0F B6 5D movzx r11w, byte ptr [rbp + 4] \n"
" 04 \n"
" \n"
" 000029CF 44/ 0F B6 DD movzx r11d, bpl \n"
" 000029D3 44/ 0F B7 DD movzx r11d, bp \n"
" 000029D7 44/ 0F B6 5D movzx r11d, byte ptr [rbp + 4] \n"
" 04 \n"
" 000029DC 44/ 0F B7 5D movzx r11d, word ptr [rbp + 4] \n"
" 04 \n"
" \n"
" 000029E1 4C/ 0F B6 DD movzx r11, bpl \n"
" 000029E5 4C/ 0F B7 DD movzx r11, bp \n"
" 000029E9 4C/ 0F B6 5D movzx r11, byte ptr [rbp + 4] \n"
" 04 \n"
" 000029EE 4C/ 0F B7 5D movzx r11, word ptr [rbp + 4] \n"
" 04 \n"
" \n"
" \n"
" ; Source: rbp, target: r12 \n"
" 000029F3 41/ B4 01 mov r12b, 1 \n"
" 000029F6 66| 41/ BC mov r12w, 1 \n"
" 0001 \n"
" 000029FB 41/ BC mov r12d, 1 \n"
" 00000001 \n"
" 00002A01 49/ C7 C4 mov r12, 1 \n"
" 00000001 \n"
" \n"
" 00002A08 44/ 8A E5 mov r12b, bpl \n"
" 00002A0B 66| 44/ 8B E5 mov r12w, bp \n"
" 00002A0F 44/ 8B E5 mov r12d, ebp \n"
" 00002A12 4C/ 8B E5 mov r12, rbp \n"
" \n"
" 00002A15 44/ 8A 65 FC mov r12b, byte ptr [rbp - 4] \n"
" 00002A19 44/ 8A 65 04 mov r12b, byte ptr [rbp + 4] \n"
" 00002A1D 66| 44/ 8B 65 mov r12w, word ptr [rbp + 4] \n"
" 04 \n"
" 00002A22 44/ 8B 65 04 mov r12d, dword ptr [rbp + 4] \n"
" 00002A26 4C/ 8B 65 04 mov r12, qword ptr [rbp + 4] \n"
" \n"
" 00002A2A 41/ 88 6C 24 mov byte ptr [r12 - 4], bpl \n"
" FC \n"
" 00002A2F 41/ 88 6C 24 mov byte ptr [r12 + 4], bpl \n"
" 04 \n"
" 00002A34 66| 41/ 89 6C 24 mov word ptr [r12 + 4], bp \n"
" 04 \n"
" 00002A3A 41/ 89 6C 24 mov dword ptr [r12 + 4], ebp \n"
" 04 \n"
" 00002A3F 49/ 89 6C 24 mov qword ptr [r12 + 4], rbp \n"
" 04 \n"
" \n"
" 00002A44 66| 44/ 0F B6 E5 movzx r12w, bpl \n"
" 00002A49 66| 44/ 0F B6 65 movzx r12w, byte ptr [rbp + 4] \n"
" 04 \n"
" \n"
" 00002A4F 44/ 0F B6 E5 movzx r12d, bpl \n"
" 00002A53 44/ 0F B7 E5 movzx r12d, bp \n"
" 00002A57 44/ 0F B6 65 movzx r12d, byte ptr [rbp + 4] \n"
" 04 \n"
" 00002A5C 44/ 0F B7 65 movzx r12d, word ptr [rbp + 4] \n"
" 04 \n"
" \n"
" 00002A61 4C/ 0F B6 E5 movzx r12, bpl \n"
" 00002A65 4C/ 0F B7 E5 movzx r12, bp \n"
" 00002A69 4C/ 0F B6 65 movzx r12, byte ptr [rbp + 4] \n"
" 04 \n"
" 00002A6E 4C/ 0F B7 65 movzx r12, word ptr [rbp + 4] \n"
" 04 \n"
" \n"
" \n"
" ; Source: rbp, target: r13 \n"
" 00002A73 41/ B5 01 mov r13b, 1 \n"
" 00002A76 66| 41/ BD mov r13w, 1 \n"
" 0001 \n"
" 00002A7B 41/ BD mov r13d, 1 \n"
" 00000001 \n"
" 00002A81 49/ C7 C5 mov r13, 1 \n"
" 00000001 \n"
" \n"
" 00002A88 44/ 8A ED mov r13b, bpl \n"
" 00002A8B 66| 44/ 8B ED mov r13w, bp \n"
" 00002A8F 44/ 8B ED mov r13d, ebp \n"
" 00002A92 4C/ 8B ED mov r13, rbp \n"
" \n"
" 00002A95 44/ 8A 6D FC mov r13b, byte ptr [rbp - 4] \n"
" 00002A99 44/ 8A 6D 04 mov r13b, byte ptr [rbp + 4] \n"
" 00002A9D 66| 44/ 8B 6D mov r13w, word ptr [rbp + 4] \n"
" 04 \n"
" 00002AA2 44/ 8B 6D 04 mov r13d, dword ptr [rbp + 4] \n"
" 00002AA6 4C/ 8B 6D 04 mov r13, qword ptr [rbp + 4] \n"
" \n"
" 00002AAA 41/ 88 6D FC mov byte ptr [r13 - 4], bpl \n"
" 00002AAE 41/ 88 6D 04 mov byte ptr [r13 + 4], bpl \n"
" 00002AB2 66| 41/ 89 6D mov word ptr [r13 + 4], bp \n"
" 04 \n"
" 00002AB7 41/ 89 6D 04 mov dword ptr [r13 + 4], ebp \n"
" 00002ABB 49/ 89 6D 04 mov qword ptr [r13 + 4], rbp \n"
" \n"
" 00002ABF 66| 44/ 0F B6 ED movzx r13w, bpl \n"
" 00002AC4 66| 44/ 0F B6 6D movzx r13w, byte ptr [rbp + 4] \n"
" 04 \n"
" \n"
" 00002ACA 44/ 0F B6 ED movzx r13d, bpl \n"
" 00002ACE 44/ 0F B7 ED movzx r13d, bp \n"
" 00002AD2 44/ 0F B6 6D movzx r13d, byte ptr [rbp + 4] \n"
" 04 \n"
" 00002AD7 44/ 0F B7 6D movzx r13d, word ptr [rbp + 4] \n"
" 04 \n"
" \n"
" 00002ADC 4C/ 0F B6 ED movzx r13, bpl \n"
" 00002AE0 4C/ 0F B7 ED movzx r13, bp \n"
" 00002AE4 4C/ 0F B6 6D movzx r13, byte ptr [rbp + 4] \n"
" 04 \n"
" 00002AE9 4C/ 0F B7 6D movzx r13, word ptr [rbp + 4] \n"
" 04 \n"
" \n"
" \n"
" ; Source: rbp, target: r14 \n"
" 00002AEE 41/ B6 01 mov r14b, 1 \n"
" 00002AF1 66| 41/ BE mov r14w, 1 \n"
" 0001 \n"
" 00002AF6 41/ BE mov r14d, 1 \n"
" 00000001 \n"
" 00002AFC 49/ C7 C6 mov r14, 1 \n"
" 00000001 \n"
" \n"
" 00002B03 44/ 8A F5 mov r14b, bpl \n"
" 00002B06 66| 44/ 8B F5 mov r14w, bp \n"
" 00002B0A 44/ 8B F5 mov r14d, ebp \n"
" 00002B0D 4C/ 8B F5 mov r14, rbp \n"
" \n"
" 00002B10 44/ 8A 75 FC mov r14b, byte ptr [rbp - 4] \n"
" 00002B14 44/ 8A 75 04 mov r14b, byte ptr [rbp + 4] \n"
" 00002B18 66| 44/ 8B 75 mov r14w, word ptr [rbp + 4] \n"
" 04 \n"
" 00002B1D 44/ 8B 75 04 mov r14d, dword ptr [rbp + 4] \n"
" 00002B21 4C/ 8B 75 04 mov r14, qword ptr [rbp + 4] \n"
" \n"
" 00002B25 41/ 88 6E FC mov byte ptr [r14 - 4], bpl \n"
" 00002B29 41/ 88 6E 04 mov byte ptr [r14 + 4], bpl \n"
" 00002B2D 66| 41/ 89 6E mov word ptr [r14 + 4], bp \n"
" 04 \n"
" 00002B32 41/ 89 6E 04 mov dword ptr [r14 + 4], ebp \n"
" 00002B36 49/ 89 6E 04 mov qword ptr [r14 + 4], rbp \n"
" \n"
" 00002B3A 66| 44/ 0F B6 F5 movzx r14w, bpl \n"
" 00002B3F 66| 44/ 0F B6 75 movzx r14w, byte ptr [rbp + 4] \n"
" 04 \n"
" \n"
" 00002B45 44/ 0F B6 F5 movzx r14d, bpl \n"
" 00002B49 44/ 0F B7 F5 movzx r14d, bp \n"
" 00002B4D 44/ 0F B6 75 movzx r14d, byte ptr [rbp + 4] \n"
" 04 \n"
" 00002B52 44/ 0F B7 75 movzx r14d, word ptr [rbp + 4] \n"
" 04 \n"
" \n"
" 00002B57 4C/ 0F B6 F5 movzx r14, bpl \n"
" 00002B5B 4C/ 0F B7 F5 movzx r14, bp \n"
" 00002B5F 4C/ 0F B6 75 movzx r14, byte ptr [rbp + 4] \n"
" 04 \n"
" 00002B64 4C/ 0F B7 75 movzx r14, word ptr [rbp + 4] \n"
" 04 \n"
" \n"
" \n"
" ; Source: rbp, target: r15 \n"
" 00002B69 41/ B7 01 mov r15b, 1 \n"
" 00002B6C 66| 41/ BF mov r15w, 1 \n"
" 0001 \n"
" 00002B71 41/ BF mov r15d, 1 \n"
" 00000001 \n"
" 00002B77 49/ C7 C7 mov r15, 1 \n"
" 00000001 \n"
" \n"
" 00002B7E 44/ 8A FD mov r15b, bpl \n"
" 00002B81 66| 44/ 8B FD mov r15w, bp \n"
" 00002B85 44/ 8B FD mov r15d, ebp \n"
" 00002B88 4C/ 8B FD mov r15, rbp \n"
" \n"
" 00002B8B 44/ 8A 7D FC mov r15b, byte ptr [rbp - 4] \n"
" 00002B8F 44/ 8A 7D 04 mov r15b, byte ptr [rbp + 4] \n"
" 00002B93 66| 44/ 8B 7D mov r15w, word ptr [rbp + 4] \n"
" 04 \n"
" 00002B98 44/ 8B 7D 04 mov r15d, dword ptr [rbp + 4] \n"
" 00002B9C 4C/ 8B 7D 04 mov r15, qword ptr [rbp + 4] \n"
" \n"
" 00002BA0 41/ 88 6F FC mov byte ptr [r15 - 4], bpl \n"
" 00002BA4 41/ 88 6F 04 mov byte ptr [r15 + 4], bpl \n"
" 00002BA8 66| 41/ 89 6F mov word ptr [r15 + 4], bp \n"
" 04 \n"
" 00002BAD 41/ 89 6F 04 mov dword ptr [r15 + 4], ebp \n"
" 00002BB1 49/ 89 6F 04 mov qword ptr [r15 + 4], rbp \n"
" \n"
" 00002BB5 66| 44/ 0F B6 FD movzx r15w, bpl \n"
" 00002BBA 66| 44/ 0F B6 7D movzx r15w, byte ptr [rbp + 4] \n"
" 04 \n"
" \n"
" 00002BC0 44/ 0F B6 FD movzx r15d, bpl \n"
" 00002BC4 44/ 0F B7 FD movzx r15d, bp \n"
" 00002BC8 44/ 0F B6 7D movzx r15d, byte ptr [rbp + 4] \n"
" 04 \n"
" 00002BCD 44/ 0F B7 7D movzx r15d, word ptr [rbp + 4] \n"
" 04 \n"
" \n"
" 00002BD2 4C/ 0F B6 FD movzx r15, bpl \n"
" 00002BD6 4C/ 0F B7 FD movzx r15, bp \n"
" 00002BDA 4C/ 0F B6 7D movzx r15, byte ptr [rbp + 4] \n"
" 04 \n"
" 00002BDF 4C/ 0F B7 7D movzx r15, word ptr [rbp + 4] \n"
" 04 \n"
" \n"
" \n"
" ; Source: rsi, target: rax \n"
" 00002BE4 B0 01 mov al, 1 \n"
" 00002BE6 66| B8 0001 mov ax, 1 \n"
" 00002BEA B8 00000001 mov eax, 1 \n"
" 00002BEF 48/ C7 C0 mov rax, 1 \n"
" 00000001 \n"
" \n"
" 00002BF6 40/ 8A C7 mov al, dil \n"
" 00002BF9 66| 8B C6 mov ax, si \n"
" 00002BFC 8B C6 mov eax, esi \n"
" 00002BFE 48/ 8B C6 mov rax, rsi \n"
" \n"
" 00002C01 8A 46 FC mov al, byte ptr [rsi - 4] \n"
" 00002C04 8A 46 04 mov al, byte ptr [rsi + 4] \n"
" 00002C07 66| 8B 46 04 mov ax, word ptr [rsi + 4] \n"
" 00002C0B 8B 46 04 mov eax, dword ptr [rsi + 4] \n"
" 00002C0E 48/ 8B 46 04 mov rax, qword ptr [rsi + 4] \n"
" \n"
" 00002C12 40/ 88 78 FC mov byte ptr [rax - 4], dil \n"
" 00002C16 40/ 88 78 04 mov byte ptr [rax + 4], dil \n"
" 00002C1A 66| 89 70 04 mov word ptr [rax + 4], si \n"
" 00002C1E 89 70 04 mov dword ptr [rax + 4], esi \n"
" 00002C21 48/ 89 70 04 mov qword ptr [rax + 4], rsi \n"
" \n"
" 00002C25 66| 40/ 0F B6 C7 movzx ax, dil \n"
" 00002C2A 66| 0F B6 46 movzx ax, byte ptr [rsi + 4] \n"
" 04 \n"
" \n"
" 00002C2F 40/ 0F B6 C7 movzx eax, dil \n"
" 00002C33 0F B7 C6 movzx eax, si \n"
" 00002C36 0F B6 46 04 movzx eax, byte ptr [rsi + 4] \n"
" 00002C3A 0F B7 46 04 movzx eax, word ptr [rsi + 4] \n"
" \n"
" 00002C3E 48/ 0F B6 C7 movzx rax, dil \n"
" 00002C42 48/ 0F B7 C6 movzx rax, si \n"
" 00002C46 48/ 0F B6 46 movzx rax, byte ptr [rsi + 4] \n"
" 04 \n"
" 00002C4B 48/ 0F B7 46 movzx rax, word ptr [rsi + 4] \n"
" 04 \n"
" \n"
" \n"
" ; Source: rsi, target: rcx \n"
" 00002C50 B1 01 mov cl, 1 \n"
" 00002C52 66| B9 0001 mov cx, 1 \n"
" 00002C56 B9 00000001 mov ecx, 1 \n"
" 00002C5B 48/ C7 C1 mov rcx, 1 \n"
" 00000001 \n"
" \n"
" 00002C62 40/ 8A CF mov cl, dil \n"
" 00002C65 66| 8B CE mov cx, si \n"
" 00002C68 8B CE mov ecx, esi \n"
" 00002C6A 48/ 8B CE mov rcx, rsi \n"
" \n"
" 00002C6D 8A 4E FC mov cl, byte ptr [rsi - 4] \n"
" 00002C70 8A 4E 04 mov cl, byte ptr [rsi + 4] \n"
" 00002C73 66| 8B 4E 04 mov cx, word ptr [rsi + 4] \n"
" 00002C77 8B 4E 04 mov ecx, dword ptr [rsi + 4] \n"
" 00002C7A 48/ 8B 4E 04 mov rcx, qword ptr [rsi + 4] \n"
" \n"
" 00002C7E 40/ 88 79 FC mov byte ptr [rcx - 4], dil \n"
" 00002C82 40/ 88 79 04 mov byte ptr [rcx + 4], dil \n"
" 00002C86 66| 89 71 04 mov word ptr [rcx + 4], si \n"
" 00002C8A 89 71 04 mov dword ptr [rcx + 4], esi \n"
" 00002C8D 48/ 89 71 04 mov qword ptr [rcx + 4], rsi \n"
" \n"
" 00002C91 66| 40/ 0F B6 CF movzx cx, dil \n"
" 00002C96 66| 0F B6 4E movzx cx, byte ptr [rsi + 4] \n"
" 04 \n"
" \n"
" 00002C9B 40/ 0F B6 CF movzx ecx, dil \n";
ml64Output +=
" 00002C9F 0F B7 CE movzx ecx, si \n"
" 00002CA2 0F B6 4E 04 movzx ecx, byte ptr [rsi + 4] \n"
" 00002CA6 0F B7 4E 04 movzx ecx, word ptr [rsi + 4] \n"
" \n"
" 00002CAA 48/ 0F B6 CF movzx rcx, dil \n"
" 00002CAE 48/ 0F B7 CE movzx rcx, si \n"
" 00002CB2 48/ 0F B6 4E movzx rcx, byte ptr [rsi + 4] \n"
" 04 \n"
" 00002CB7 48/ 0F B7 4E movzx rcx, word ptr [rsi + 4] \n"
" 04 \n"
" \n"
" \n"
" ; Source: rsi, target: rdx \n"
" 00002CBC B2 01 mov dl, 1 \n"
" 00002CBE 66| BA 0001 mov dx, 1 \n"
" 00002CC2 BA 00000001 mov edx, 1 \n"
" 00002CC7 48/ C7 C2 mov rdx, 1 \n"
" 00000001 \n"
" \n"
" 00002CCE 40/ 8A D7 mov dl, dil \n"
" 00002CD1 66| 8B D6 mov dx, si \n"
" 00002CD4 8B D6 mov edx, esi \n"
" 00002CD6 48/ 8B D6 mov rdx, rsi \n"
" \n"
" 00002CD9 8A 56 FC mov dl, byte ptr [rsi - 4] \n"
" 00002CDC 8A 56 04 mov dl, byte ptr [rsi + 4] \n"
" 00002CDF 66| 8B 56 04 mov dx, word ptr [rsi + 4] \n"
" 00002CE3 8B 56 04 mov edx, dword ptr [rsi + 4] \n"
" 00002CE6 48/ 8B 56 04 mov rdx, qword ptr [rsi + 4] \n"
" \n"
" 00002CEA 40/ 88 7A FC mov byte ptr [rdx - 4], dil \n"
" 00002CEE 40/ 88 7A 04 mov byte ptr [rdx + 4], dil \n"
" 00002CF2 66| 89 72 04 mov word ptr [rdx + 4], si \n"
" 00002CF6 89 72 04 mov dword ptr [rdx + 4], esi \n"
" 00002CF9 48/ 89 72 04 mov qword ptr [rdx + 4], rsi \n"
" \n"
" 00002CFD 66| 40/ 0F B6 D7 movzx dx, dil \n"
" 00002D02 66| 0F B6 56 movzx dx, byte ptr [rsi + 4] \n"
" 04 \n"
" \n"
" 00002D07 40/ 0F B6 D7 movzx edx, dil \n"
" 00002D0B 0F B7 D6 movzx edx, si \n"
" 00002D0E 0F B6 56 04 movzx edx, byte ptr [rsi + 4] \n"
" 00002D12 0F B7 56 04 movzx edx, word ptr [rsi + 4] \n"
" \n"
" 00002D16 48/ 0F B6 D7 movzx rdx, dil \n"
" 00002D1A 48/ 0F B7 D6 movzx rdx, si \n"
" 00002D1E 48/ 0F B6 56 movzx rdx, byte ptr [rsi + 4] \n"
" 04 \n"
" 00002D23 48/ 0F B7 56 movzx rdx, word ptr [rsi + 4] \n"
" 04 \n"
" \n"
" \n"
" ; Source: rsi, target: rbx \n"
" 00002D28 B3 01 mov bl, 1 \n"
" 00002D2A 66| BB 0001 mov bx, 1 \n"
" 00002D2E BB 00000001 mov ebx, 1 \n"
" 00002D33 48/ C7 C3 mov rbx, 1 \n"
" 00000001 \n"
" \n"
" 00002D3A 40/ 8A DF mov bl, dil \n"
" 00002D3D 66| 8B DE mov bx, si \n"
" 00002D40 8B DE mov ebx, esi \n"
" 00002D42 48/ 8B DE mov rbx, rsi \n"
" \n"
" 00002D45 8A 5E FC mov bl, byte ptr [rsi - 4] \n"
" 00002D48 8A 5E 04 mov bl, byte ptr [rsi + 4] \n"
" 00002D4B 66| 8B 5E 04 mov bx, word ptr [rsi + 4] \n"
" 00002D4F 8B 5E 04 mov ebx, dword ptr [rsi + 4] \n"
" 00002D52 48/ 8B 5E 04 mov rbx, qword ptr [rsi + 4] \n"
" \n"
" 00002D56 40/ 88 7B FC mov byte ptr [rbx - 4], dil \n"
" 00002D5A 40/ 88 7B 04 mov byte ptr [rbx + 4], dil \n"
" 00002D5E 66| 89 73 04 mov word ptr [rbx + 4], si \n"
" 00002D62 89 73 04 mov dword ptr [rbx + 4], esi \n"
" 00002D65 48/ 89 73 04 mov qword ptr [rbx + 4], rsi \n"
" \n"
" 00002D69 66| 40/ 0F B6 DF movzx bx, dil \n"
" 00002D6E 66| 0F B6 5E movzx bx, byte ptr [rsi + 4] \n"
" 04 \n"
" \n"
" 00002D73 40/ 0F B6 DF movzx ebx, dil \n"
" 00002D77 0F B7 DE movzx ebx, si \n"
" 00002D7A 0F B6 5E 04 movzx ebx, byte ptr [rsi + 4] \n"
" 00002D7E 0F B7 5E 04 movzx ebx, word ptr [rsi + 4] \n"
" \n"
" 00002D82 48/ 0F B6 DF movzx rbx, dil \n"
" 00002D86 48/ 0F B7 DE movzx rbx, si \n"
" 00002D8A 48/ 0F B6 5E movzx rbx, byte ptr [rsi + 4] \n"
" 04 \n"
" 00002D8F 48/ 0F B7 5E movzx rbx, word ptr [rsi + 4] \n"
" 04 \n"
" \n"
" \n"
" ; Source: rsi, target: rsp \n"
" 00002D94 40/ B4 01 mov spl, 1 \n"
" 00002D97 66| BC 0001 mov sp, 1 \n"
" 00002D9B BC 00000001 mov esp, 1 \n"
" 00002DA0 48/ C7 C4 mov rsp, 1 \n"
" 00000001 \n"
" \n"
" 00002DA7 40/ 8A E7 mov spl, dil \n"
" 00002DAA 66| 8B E6 mov sp, si \n"
" 00002DAD 8B E6 mov esp, esi \n"
" 00002DAF 48/ 8B E6 mov rsp, rsi \n"
" \n"
" 00002DB2 40/ 8A 66 FC mov spl, byte ptr [rsi - 4] \n"
" 00002DB6 40/ 8A 66 04 mov spl, byte ptr [rsi + 4] \n"
" 00002DBA 66| 8B 66 04 mov sp, word ptr [rsi + 4] \n"
" 00002DBE 8B 66 04 mov esp, dword ptr [rsi + 4] \n"
" 00002DC1 48/ 8B 66 04 mov rsp, qword ptr [rsi + 4] \n"
" \n"
" 00002DC5 40/ 88 7C 24 mov byte ptr [rsp - 4], dil \n"
" FC \n"
" 00002DCA 40/ 88 7C 24 mov byte ptr [rsp + 4], dil \n"
" 04 \n"
" 00002DCF 66| 89 74 24 mov word ptr [rsp + 4], si \n"
" 04 \n"
" 00002DD4 89 74 24 04 mov dword ptr [rsp + 4], esi \n"
" 00002DD8 48/ 89 74 24 mov qword ptr [rsp + 4], rsi \n"
" 04 \n"
" \n"
" 00002DDD 66| 40/ 0F B6 E7 movzx sp, dil \n"
" 00002DE2 66| 0F B6 66 movzx sp, byte ptr [rsi + 4] \n"
" 04 \n"
" \n"
" 00002DE7 40/ 0F B6 E7 movzx esp, dil \n"
" 00002DEB 0F B7 E6 movzx esp, si \n"
" 00002DEE 0F B6 66 04 movzx esp, byte ptr [rsi + 4] \n"
" 00002DF2 0F B7 66 04 movzx esp, word ptr [rsi + 4] \n"
" \n"
" 00002DF6 48/ 0F B6 E7 movzx rsp, dil \n"
" 00002DFA 48/ 0F B7 E6 movzx rsp, si \n"
" 00002DFE 48/ 0F B6 66 movzx rsp, byte ptr [rsi + 4] \n"
" 04 \n"
" 00002E03 48/ 0F B7 66 movzx rsp, word ptr [rsi + 4] \n"
" 04 \n"
" \n"
" \n"
" ; Source: rsi, target: rbp \n"
" 00002E08 40/ B5 01 mov bpl, 1 \n"
" 00002E0B 66| BD 0001 mov bp, 1 \n"
" 00002E0F BD 00000001 mov ebp, 1 \n"
" 00002E14 48/ C7 C5 mov rbp, 1 \n"
" 00000001 \n"
" \n"
" 00002E1B 40/ 8A EF mov bpl, dil \n"
" 00002E1E 66| 8B EE mov bp, si \n"
" 00002E21 8B EE mov ebp, esi \n"
" 00002E23 48/ 8B EE mov rbp, rsi \n"
" \n"
" 00002E26 40/ 8A 6E FC mov bpl, byte ptr [rsi - 4] \n"
" 00002E2A 40/ 8A 6E 04 mov bpl, byte ptr [rsi + 4] \n"
" 00002E2E 66| 8B 6E 04 mov bp, word ptr [rsi + 4] \n"
" 00002E32 8B 6E 04 mov ebp, dword ptr [rsi + 4] \n"
" 00002E35 48/ 8B 6E 04 mov rbp, qword ptr [rsi + 4] \n"
" \n"
" 00002E39 40/ 88 7D FC mov byte ptr [rbp - 4], dil \n"
" 00002E3D 40/ 88 7D 04 mov byte ptr [rbp + 4], dil \n"
" 00002E41 66| 89 75 04 mov word ptr [rbp + 4], si \n"
" 00002E45 89 75 04 mov dword ptr [rbp + 4], esi \n"
" 00002E48 48/ 89 75 04 mov qword ptr [rbp + 4], rsi \n"
" \n"
" 00002E4C 66| 40/ 0F B6 EF movzx bp, dil \n"
" 00002E51 66| 0F B6 6E movzx bp, byte ptr [rsi + 4] \n"
" 04 \n"
" \n"
" 00002E56 40/ 0F B6 EF movzx ebp, dil \n"
" 00002E5A 0F B7 EE movzx ebp, si \n"
" 00002E5D 0F B6 6E 04 movzx ebp, byte ptr [rsi + 4] \n"
" 00002E61 0F B7 6E 04 movzx ebp, word ptr [rsi + 4] \n"
" \n"
" 00002E65 48/ 0F B6 EF movzx rbp, dil \n"
" 00002E69 48/ 0F B7 EE movzx rbp, si \n"
" 00002E6D 48/ 0F B6 6E movzx rbp, byte ptr [rsi + 4] \n"
" 04 \n"
" 00002E72 48/ 0F B7 6E movzx rbp, word ptr [rsi + 4] \n"
" 04 \n"
" \n"
" \n"
" ; Source: rsi, target: rsi \n"
" 00002E77 40/ B7 01 mov dil, 1 \n"
" 00002E7A 66| BE 0001 mov si, 1 \n"
" 00002E7E BE 00000001 mov esi, 1 \n"
" 00002E83 48/ C7 C6 mov rsi, 1 \n"
" 00000001 \n"
" \n"
" 00002E8A 40/ 8A FF mov dil, dil \n"
" 00002E8D 66| 8B F6 mov si, si \n"
" 00002E90 8B F6 mov esi, esi \n"
" 00002E92 48/ 8B F6 mov rsi, rsi \n"
" \n"
" 00002E95 40/ 8A 7E FC mov dil, byte ptr [rsi - 4] \n"
" 00002E99 40/ 8A 7E 04 mov dil, byte ptr [rsi + 4] \n"
" 00002E9D 66| 8B 76 04 mov si, word ptr [rsi + 4] \n"
" 00002EA1 8B 76 04 mov esi, dword ptr [rsi + 4] \n"
" 00002EA4 48/ 8B 76 04 mov rsi, qword ptr [rsi + 4] \n"
" \n"
" 00002EA8 40/ 88 7E FC mov byte ptr [rsi - 4], dil \n"
" 00002EAC 40/ 88 7E 04 mov byte ptr [rsi + 4], dil \n"
" 00002EB0 66| 89 76 04 mov word ptr [rsi + 4], si \n"
" 00002EB4 89 76 04 mov dword ptr [rsi + 4], esi \n"
" 00002EB7 48/ 89 76 04 mov qword ptr [rsi + 4], rsi \n"
" \n"
" 00002EBB 66| 40/ 0F B6 F7 movzx si, dil \n"
" 00002EC0 66| 0F B6 76 movzx si, byte ptr [rsi + 4] \n"
" 04 \n"
" \n"
" 00002EC5 40/ 0F B6 F7 movzx esi, dil \n"
" 00002EC9 0F B7 F6 movzx esi, si \n"
" 00002ECC 0F B6 76 04 movzx esi, byte ptr [rsi + 4] \n"
" 00002ED0 0F B7 76 04 movzx esi, word ptr [rsi + 4] \n"
" \n"
" 00002ED4 48/ 0F B6 F7 movzx rsi, dil \n"
" 00002ED8 48/ 0F B7 F6 movzx rsi, si \n"
" 00002EDC 48/ 0F B6 76 movzx rsi, byte ptr [rsi + 4] \n"
" 04 \n"
" 00002EE1 48/ 0F B7 76 movzx rsi, word ptr [rsi + 4] \n"
" 04 \n"
" \n"
" \n"
" ; Source: rsi, target: rdi \n"
" 00002EE6 40/ B6 01 mov sil, 1 \n"
" 00002EE9 66| BF 0001 mov di, 1 \n"
" 00002EED BF 00000001 mov edi, 1 \n"
" 00002EF2 48/ C7 C7 mov rdi, 1 \n"
" 00000001 \n"
" \n"
" 00002EF9 40/ 8A F7 mov sil, dil \n"
" 00002EFC 66| 8B FE mov di, si \n"
" 00002EFF 8B FE mov edi, esi \n"
" 00002F01 48/ 8B FE mov rdi, rsi \n"
" \n"
" 00002F04 40/ 8A 76 FC mov sil, byte ptr [rsi - 4] \n"
" 00002F08 40/ 8A 76 04 mov sil, byte ptr [rsi + 4] \n"
" 00002F0C 66| 8B 7E 04 mov di, word ptr [rsi + 4] \n"
" 00002F10 8B 7E 04 mov edi, dword ptr [rsi + 4] \n"
" 00002F13 48/ 8B 7E 04 mov rdi, qword ptr [rsi + 4] \n"
" \n"
" 00002F17 40/ 88 7F FC mov byte ptr [rdi - 4], dil \n"
" 00002F1B 40/ 88 7F 04 mov byte ptr [rdi + 4], dil \n"
" 00002F1F 66| 89 77 04 mov word ptr [rdi + 4], si \n"
" 00002F23 89 77 04 mov dword ptr [rdi + 4], esi \n"
" 00002F26 48/ 89 77 04 mov qword ptr [rdi + 4], rsi \n"
" \n"
" 00002F2A 66| 40/ 0F B6 FF movzx di, dil \n"
" 00002F2F 66| 0F B6 7E movzx di, byte ptr [rsi + 4] \n"
" 04 \n"
" \n"
" 00002F34 40/ 0F B6 FF movzx edi, dil \n"
" 00002F38 0F B7 FE movzx edi, si \n"
" 00002F3B 0F B6 7E 04 movzx edi, byte ptr [rsi + 4] \n"
" 00002F3F 0F B7 7E 04 movzx edi, word ptr [rsi + 4] \n"
" \n"
" 00002F43 48/ 0F B6 FF movzx rdi, dil \n"
" 00002F47 48/ 0F B7 FE movzx rdi, si \n"
" 00002F4B 48/ 0F B6 7E movzx rdi, byte ptr [rsi + 4] \n"
" 04 \n"
" 00002F50 48/ 0F B7 7E movzx rdi, word ptr [rsi + 4] \n"
" 04 \n"
" \n"
" \n"
" ; Source: rsi, target: r8 \n"
" 00002F55 41/ B0 01 mov r8b, 1 \n"
" 00002F58 66| 41/ B8 mov r8w, 1 \n"
" 0001 \n"
" 00002F5D 41/ B8 mov r8d, 1 \n"
" 00000001 \n"
" 00002F63 49/ C7 C0 mov r8, 1 \n"
" 00000001 \n"
" \n"
" 00002F6A 44/ 8A C7 mov r8b, dil \n"
" 00002F6D 66| 44/ 8B C6 mov r8w, si \n"
" 00002F71 44/ 8B C6 mov r8d, esi \n"
" 00002F74 4C/ 8B C6 mov r8, rsi \n"
" \n"
" 00002F77 44/ 8A 46 FC mov r8b, byte ptr [rsi - 4] \n"
" 00002F7B 44/ 8A 46 04 mov r8b, byte ptr [rsi + 4] \n"
" 00002F7F 66| 44/ 8B 46 mov r8w, word ptr [rsi + 4] \n"
" 04 \n"
" 00002F84 44/ 8B 46 04 mov r8d, dword ptr [rsi + 4] \n"
" 00002F88 4C/ 8B 46 04 mov r8, qword ptr [rsi + 4] \n"
" \n"
" 00002F8C 41/ 88 78 FC mov byte ptr [r8 - 4], dil \n"
" 00002F90 41/ 88 78 04 mov byte ptr [r8 + 4], dil \n"
" 00002F94 66| 41/ 89 70 mov word ptr [r8 + 4], si \n"
" 04 \n"
" 00002F99 41/ 89 70 04 mov dword ptr [r8 + 4], esi \n"
" 00002F9D 49/ 89 70 04 mov qword ptr [r8 + 4], rsi \n"
" \n"
" 00002FA1 66| 44/ 0F B6 C7 movzx r8w, dil \n"
" 00002FA6 66| 44/ 0F B6 46 movzx r8w, byte ptr [rsi + 4] \n"
" 04 \n"
" \n"
" 00002FAC 44/ 0F B6 C7 movzx r8d, dil \n"
" 00002FB0 44/ 0F B7 C6 movzx r8d, si \n"
" 00002FB4 44/ 0F B6 46 movzx r8d, byte ptr [rsi + 4] \n"
" 04 \n"
" 00002FB9 44/ 0F B7 46 movzx r8d, word ptr [rsi + 4] \n"
" 04 \n"
" \n"
" 00002FBE 4C/ 0F B6 C7 movzx r8, dil \n"
" 00002FC2 4C/ 0F B7 C6 movzx r8, si \n"
" 00002FC6 4C/ 0F B6 46 movzx r8, byte ptr [rsi + 4] \n"
" 04 \n"
" 00002FCB 4C/ 0F B7 46 movzx r8, word ptr [rsi + 4] \n"
" 04 \n"
" \n"
" \n"
" ; Source: rsi, target: r9 \n"
" 00002FD0 41/ B1 01 mov r9b, 1 \n"
" 00002FD3 66| 41/ B9 mov r9w, 1 \n"
" 0001 \n"
" 00002FD8 41/ B9 mov r9d, 1 \n"
" 00000001 \n"
" 00002FDE 49/ C7 C1 mov r9, 1 \n"
" 00000001 \n"
" \n"
" 00002FE5 44/ 8A CF mov r9b, dil \n"
" 00002FE8 66| 44/ 8B CE mov r9w, si \n"
" 00002FEC 44/ 8B CE mov r9d, esi \n"
" 00002FEF 4C/ 8B CE mov r9, rsi \n"
" \n"
" 00002FF2 44/ 8A 4E FC mov r9b, byte ptr [rsi - 4] \n"
" 00002FF6 44/ 8A 4E 04 mov r9b, byte ptr [rsi + 4] \n"
" 00002FFA 66| 44/ 8B 4E mov r9w, word ptr [rsi + 4] \n"
" 04 \n"
" 00002FFF 44/ 8B 4E 04 mov r9d, dword ptr [rsi + 4] \n"
" 00003003 4C/ 8B 4E 04 mov r9, qword ptr [rsi + 4] \n"
" \n"
" 00003007 41/ 88 79 FC mov byte ptr [r9 - 4], dil \n"
" 0000300B 41/ 88 79 04 mov byte ptr [r9 + 4], dil \n"
" 0000300F 66| 41/ 89 71 mov word ptr [r9 + 4], si \n"
" 04 \n"
" 00003014 41/ 89 71 04 mov dword ptr [r9 + 4], esi \n"
" 00003018 49/ 89 71 04 mov qword ptr [r9 + 4], rsi \n"
" \n"
" 0000301C 66| 44/ 0F B6 CF movzx r9w, dil \n"
" 00003021 66| 44/ 0F B6 4E movzx r9w, byte ptr [rsi + 4] \n"
" 04 \n"
" \n"
" 00003027 44/ 0F B6 CF movzx r9d, dil \n"
" 0000302B 44/ 0F B7 CE movzx r9d, si \n"
" 0000302F 44/ 0F B6 4E movzx r9d, byte ptr [rsi + 4] \n"
" 04 \n"
" 00003034 44/ 0F B7 4E movzx r9d, word ptr [rsi + 4] \n"
" 04 \n"
" \n"
" 00003039 4C/ 0F B6 CF movzx r9, dil \n"
" 0000303D 4C/ 0F B7 CE movzx r9, si \n"
" 00003041 4C/ 0F B6 4E movzx r9, byte ptr [rsi + 4] \n"
" 04 \n"
" 00003046 4C/ 0F B7 4E movzx r9, word ptr [rsi + 4] \n"
" 04 \n"
" \n"
" \n"
" ; Source: rsi, target: r10 \n"
" 0000304B 41/ B2 01 mov r10b, 1 \n"
" 0000304E 66| 41/ BA mov r10w, 1 \n"
" 0001 \n"
" 00003053 41/ BA mov r10d, 1 \n"
" 00000001 \n"
" 00003059 49/ C7 C2 mov r10, 1 \n"
" 00000001 \n"
" \n"
" 00003060 44/ 8A D7 mov r10b, dil \n"
" 00003063 66| 44/ 8B D6 mov r10w, si \n"
" 00003067 44/ 8B D6 mov r10d, esi \n"
" 0000306A 4C/ 8B D6 mov r10, rsi \n"
" \n"
" 0000306D 44/ 8A 56 FC mov r10b, byte ptr [rsi - 4] \n"
" 00003071 44/ 8A 56 04 mov r10b, byte ptr [rsi + 4] \n"
" 00003075 66| 44/ 8B 56 mov r10w, word ptr [rsi + 4] \n"
" 04 \n"
" 0000307A 44/ 8B 56 04 mov r10d, dword ptr [rsi + 4] \n"
" 0000307E 4C/ 8B 56 04 mov r10, qword ptr [rsi + 4] \n"
" \n"
" 00003082 41/ 88 7A FC mov byte ptr [r10 - 4], dil \n"
" 00003086 41/ 88 7A 04 mov byte ptr [r10 + 4], dil \n"
" 0000308A 66| 41/ 89 72 mov word ptr [r10 + 4], si \n"
" 04 \n"
" 0000308F 41/ 89 72 04 mov dword ptr [r10 + 4], esi \n"
" 00003093 49/ 89 72 04 mov qword ptr [r10 + 4], rsi \n"
" \n"
" 00003097 66| 44/ 0F B6 D7 movzx r10w, dil \n"
" 0000309C 66| 44/ 0F B6 56 movzx r10w, byte ptr [rsi + 4] \n"
" 04 \n"
" \n"
" 000030A2 44/ 0F B6 D7 movzx r10d, dil \n"
" 000030A6 44/ 0F B7 D6 movzx r10d, si \n"
" 000030AA 44/ 0F B6 56 movzx r10d, byte ptr [rsi + 4] \n"
" 04 \n"
" 000030AF 44/ 0F B7 56 movzx r10d, word ptr [rsi + 4] \n"
" 04 \n"
" \n"
" 000030B4 4C/ 0F B6 D7 movzx r10, dil \n"
" 000030B8 4C/ 0F B7 D6 movzx r10, si \n"
" 000030BC 4C/ 0F B6 56 movzx r10, byte ptr [rsi + 4] \n"
" 04 \n"
" 000030C1 4C/ 0F B7 56 movzx r10, word ptr [rsi + 4] \n"
" 04 \n"
" \n"
" \n"
" ; Source: rsi, target: r11 \n"
" 000030C6 41/ B3 01 mov r11b, 1 \n"
" 000030C9 66| 41/ BB mov r11w, 1 \n"
" 0001 \n"
" 000030CE 41/ BB mov r11d, 1 \n"
" 00000001 \n"
" 000030D4 49/ C7 C3 mov r11, 1 \n"
" 00000001 \n"
" \n"
" 000030DB 44/ 8A DF mov r11b, dil \n"
" 000030DE 66| 44/ 8B DE mov r11w, si \n"
" 000030E2 44/ 8B DE mov r11d, esi \n"
" 000030E5 4C/ 8B DE mov r11, rsi \n"
" \n"
" 000030E8 44/ 8A 5E FC mov r11b, byte ptr [rsi - 4] \n"
" 000030EC 44/ 8A 5E 04 mov r11b, byte ptr [rsi + 4] \n"
" 000030F0 66| 44/ 8B 5E mov r11w, word ptr [rsi + 4] \n"
" 04 \n"
" 000030F5 44/ 8B 5E 04 mov r11d, dword ptr [rsi + 4] \n"
" 000030F9 4C/ 8B 5E 04 mov r11, qword ptr [rsi + 4] \n"
" \n"
" 000030FD 41/ 88 7B FC mov byte ptr [r11 - 4], dil \n"
" 00003101 41/ 88 7B 04 mov byte ptr [r11 + 4], dil \n"
" 00003105 66| 41/ 89 73 mov word ptr [r11 + 4], si \n"
" 04 \n"
" 0000310A 41/ 89 73 04 mov dword ptr [r11 + 4], esi \n"
" 0000310E 49/ 89 73 04 mov qword ptr [r11 + 4], rsi \n"
" \n"
" 00003112 66| 44/ 0F B6 DF movzx r11w, dil \n"
" 00003117 66| 44/ 0F B6 5E movzx r11w, byte ptr [rsi + 4] \n"
" 04 \n"
" \n"
" 0000311D 44/ 0F B6 DF movzx r11d, dil \n"
" 00003121 44/ 0F B7 DE movzx r11d, si \n"
" 00003125 44/ 0F B6 5E movzx r11d, byte ptr [rsi + 4] \n"
" 04 \n"
" 0000312A 44/ 0F B7 5E movzx r11d, word ptr [rsi + 4] \n"
" 04 \n"
" \n"
" 0000312F 4C/ 0F B6 DF movzx r11, dil \n"
" 00003133 4C/ 0F B7 DE movzx r11, si \n"
" 00003137 4C/ 0F B6 5E movzx r11, byte ptr [rsi + 4] \n"
" 04 \n"
" 0000313C 4C/ 0F B7 5E movzx r11, word ptr [rsi + 4] \n"
" 04 \n"
" \n"
" \n"
" ; Source: rsi, target: r12 \n"
" 00003141 41/ B4 01 mov r12b, 1 \n"
" 00003144 66| 41/ BC mov r12w, 1 \n"
" 0001 \n"
" 00003149 41/ BC mov r12d, 1 \n"
" 00000001 \n"
" 0000314F 49/ C7 C4 mov r12, 1 \n"
" 00000001 \n"
" \n"
" 00003156 44/ 8A E7 mov r12b, dil \n"
" 00003159 66| 44/ 8B E6 mov r12w, si \n"
" 0000315D 44/ 8B E6 mov r12d, esi \n"
" 00003160 4C/ 8B E6 mov r12, rsi \n"
" \n"
" 00003163 44/ 8A 66 FC mov r12b, byte ptr [rsi - 4] \n"
" 00003167 44/ 8A 66 04 mov r12b, byte ptr [rsi + 4] \n"
" 0000316B 66| 44/ 8B 66 mov r12w, word ptr [rsi + 4] \n"
" 04 \n"
" 00003170 44/ 8B 66 04 mov r12d, dword ptr [rsi + 4] \n"
" 00003174 4C/ 8B 66 04 mov r12, qword ptr [rsi + 4] \n"
" \n"
" 00003178 41/ 88 7C 24 mov byte ptr [r12 - 4], dil \n"
" FC \n"
" 0000317D 41/ 88 7C 24 mov byte ptr [r12 + 4], dil \n"
" 04 \n"
" 00003182 66| 41/ 89 74 24 mov word ptr [r12 + 4], si \n"
" 04 \n"
" 00003188 41/ 89 74 24 mov dword ptr [r12 + 4], esi \n"
" 04 \n"
" 0000318D 49/ 89 74 24 mov qword ptr [r12 + 4], rsi \n"
" 04 \n"
" \n"
" 00003192 66| 44/ 0F B6 E7 movzx r12w, dil \n"
" 00003197 66| 44/ 0F B6 66 movzx r12w, byte ptr [rsi + 4] \n"
" 04 \n"
" \n"
" 0000319D 44/ 0F B6 E7 movzx r12d, dil \n"
" 000031A1 44/ 0F B7 E6 movzx r12d, si \n"
" 000031A5 44/ 0F B6 66 movzx r12d, byte ptr [rsi + 4] \n"
" 04 \n"
" 000031AA 44/ 0F B7 66 movzx r12d, word ptr [rsi + 4] \n"
" 04 \n"
" \n"
" 000031AF 4C/ 0F B6 E7 movzx r12, dil \n"
" 000031B3 4C/ 0F B7 E6 movzx r12, si \n"
" 000031B7 4C/ 0F B6 66 movzx r12, byte ptr [rsi + 4] \n"
" 04 \n"
" 000031BC 4C/ 0F B7 66 movzx r12, word ptr [rsi + 4] \n"
" 04 \n"
" \n"
" \n"
" ; Source: rsi, target: r13 \n"
" 000031C1 41/ B5 01 mov r13b, 1 \n"
" 000031C4 66| 41/ BD mov r13w, 1 \n"
" 0001 \n"
" 000031C9 41/ BD mov r13d, 1 \n"
" 00000001 \n"
" 000031CF 49/ C7 C5 mov r13, 1 \n"
" 00000001 \n"
" \n"
" 000031D6 44/ 8A EF mov r13b, dil \n"
" 000031D9 66| 44/ 8B EE mov r13w, si \n"
" 000031DD 44/ 8B EE mov r13d, esi \n"
" 000031E0 4C/ 8B EE mov r13, rsi \n"
" \n"
" 000031E3 44/ 8A 6E FC mov r13b, byte ptr [rsi - 4] \n"
" 000031E7 44/ 8A 6E 04 mov r13b, byte ptr [rsi + 4] \n"
" 000031EB 66| 44/ 8B 6E mov r13w, word ptr [rsi + 4] \n"
" 04 \n"
" 000031F0 44/ 8B 6E 04 mov r13d, dword ptr [rsi + 4] \n"
" 000031F4 4C/ 8B 6E 04 mov r13, qword ptr [rsi + 4] \n"
" \n"
" 000031F8 41/ 88 7D FC mov byte ptr [r13 - 4], dil \n"
" 000031FC 41/ 88 7D 04 mov byte ptr [r13 + 4], dil \n"
" 00003200 66| 41/ 89 75 mov word ptr [r13 + 4], si \n"
" 04 \n"
" 00003205 41/ 89 75 04 mov dword ptr [r13 + 4], esi \n"
" 00003209 49/ 89 75 04 mov qword ptr [r13 + 4], rsi \n"
" \n"
" 0000320D 66| 44/ 0F B6 EF movzx r13w, dil \n"
" 00003212 66| 44/ 0F B6 6E movzx r13w, byte ptr [rsi + 4] \n"
" 04 \n"
" \n"
" 00003218 44/ 0F B6 EF movzx r13d, dil \n"
" 0000321C 44/ 0F B7 EE movzx r13d, si \n"
" 00003220 44/ 0F B6 6E movzx r13d, byte ptr [rsi + 4] \n"
" 04 \n"
" 00003225 44/ 0F B7 6E movzx r13d, word ptr [rsi + 4] \n"
" 04 \n"
" \n"
" 0000322A 4C/ 0F B6 EF movzx r13, dil \n"
" 0000322E 4C/ 0F B7 EE movzx r13, si \n"
" 00003232 4C/ 0F B6 6E movzx r13, byte ptr [rsi + 4] \n"
" 04 \n"
" 00003237 4C/ 0F B7 6E movzx r13, word ptr [rsi + 4] \n"
" 04 \n"
" \n"
" \n"
" ; Source: rsi, target: r14 \n"
" 0000323C 41/ B6 01 mov r14b, 1 \n";
ml64Output +=
" 0000323F 66| 41/ BE mov r14w, 1 \n"
" 0001 \n"
" 00003244 41/ BE mov r14d, 1 \n"
" 00000001 \n"
" 0000324A 49/ C7 C6 mov r14, 1 \n"
" 00000001 \n"
" \n"
" 00003251 44/ 8A F7 mov r14b, dil \n"
" 00003254 66| 44/ 8B F6 mov r14w, si \n"
" 00003258 44/ 8B F6 mov r14d, esi \n"
" 0000325B 4C/ 8B F6 mov r14, rsi \n"
" \n"
" 0000325E 44/ 8A 76 FC mov r14b, byte ptr [rsi - 4] \n"
" 00003262 44/ 8A 76 04 mov r14b, byte ptr [rsi + 4] \n"
" 00003266 66| 44/ 8B 76 mov r14w, word ptr [rsi + 4] \n"
" 04 \n"
" 0000326B 44/ 8B 76 04 mov r14d, dword ptr [rsi + 4] \n"
" 0000326F 4C/ 8B 76 04 mov r14, qword ptr [rsi + 4] \n"
" \n"
" 00003273 41/ 88 7E FC mov byte ptr [r14 - 4], dil \n"
" 00003277 41/ 88 7E 04 mov byte ptr [r14 + 4], dil \n"
" 0000327B 66| 41/ 89 76 mov word ptr [r14 + 4], si \n"
" 04 \n"
" 00003280 41/ 89 76 04 mov dword ptr [r14 + 4], esi \n"
" 00003284 49/ 89 76 04 mov qword ptr [r14 + 4], rsi \n"
" \n"
" 00003288 66| 44/ 0F B6 F7 movzx r14w, dil \n"
" 0000328D 66| 44/ 0F B6 76 movzx r14w, byte ptr [rsi + 4] \n"
" 04 \n"
" \n"
" 00003293 44/ 0F B6 F7 movzx r14d, dil \n"
" 00003297 44/ 0F B7 F6 movzx r14d, si \n"
" 0000329B 44/ 0F B6 76 movzx r14d, byte ptr [rsi + 4] \n"
" 04 \n"
" 000032A0 44/ 0F B7 76 movzx r14d, word ptr [rsi + 4] \n"
" 04 \n"
" \n"
" 000032A5 4C/ 0F B6 F7 movzx r14, dil \n"
" 000032A9 4C/ 0F B7 F6 movzx r14, si \n"
" 000032AD 4C/ 0F B6 76 movzx r14, byte ptr [rsi + 4] \n"
" 04 \n"
" 000032B2 4C/ 0F B7 76 movzx r14, word ptr [rsi + 4] \n"
" 04 \n"
" \n"
" \n"
" ; Source: rsi, target: r15 \n"
" 000032B7 41/ B7 01 mov r15b, 1 \n"
" 000032BA 66| 41/ BF mov r15w, 1 \n"
" 0001 \n"
" 000032BF 41/ BF mov r15d, 1 \n"
" 00000001 \n"
" 000032C5 49/ C7 C7 mov r15, 1 \n"
" 00000001 \n"
" \n"
" 000032CC 44/ 8A FF mov r15b, dil \n"
" 000032CF 66| 44/ 8B FE mov r15w, si \n"
" 000032D3 44/ 8B FE mov r15d, esi \n"
" 000032D6 4C/ 8B FE mov r15, rsi \n"
" \n"
" 000032D9 44/ 8A 7E FC mov r15b, byte ptr [rsi - 4] \n"
" 000032DD 44/ 8A 7E 04 mov r15b, byte ptr [rsi + 4] \n"
" 000032E1 66| 44/ 8B 7E mov r15w, word ptr [rsi + 4] \n"
" 04 \n"
" 000032E6 44/ 8B 7E 04 mov r15d, dword ptr [rsi + 4] \n"
" 000032EA 4C/ 8B 7E 04 mov r15, qword ptr [rsi + 4] \n"
" \n"
" 000032EE 41/ 88 7F FC mov byte ptr [r15 - 4], dil \n"
" 000032F2 41/ 88 7F 04 mov byte ptr [r15 + 4], dil \n"
" 000032F6 66| 41/ 89 77 mov word ptr [r15 + 4], si \n"
" 04 \n"
" 000032FB 41/ 89 77 04 mov dword ptr [r15 + 4], esi \n"
" 000032FF 49/ 89 77 04 mov qword ptr [r15 + 4], rsi \n"
" \n"
" 00003303 66| 44/ 0F B6 FF movzx r15w, dil \n"
" 00003308 66| 44/ 0F B6 7E movzx r15w, byte ptr [rsi + 4] \n"
" 04 \n"
" \n"
" 0000330E 44/ 0F B6 FF movzx r15d, dil \n"
" 00003312 44/ 0F B7 FE movzx r15d, si \n"
" 00003316 44/ 0F B6 7E movzx r15d, byte ptr [rsi + 4] \n"
" 04 \n"
" 0000331B 44/ 0F B7 7E movzx r15d, word ptr [rsi + 4] \n"
" 04 \n"
" \n"
" 00003320 4C/ 0F B6 FF movzx r15, dil \n"
" 00003324 4C/ 0F B7 FE movzx r15, si \n"
" 00003328 4C/ 0F B6 7E movzx r15, byte ptr [rsi + 4] \n"
" 04 \n"
" 0000332D 4C/ 0F B7 7E movzx r15, word ptr [rsi + 4] \n"
" 04 \n"
" \n"
" \n"
" ; Source: rdi, target: rax \n"
" 00003332 B0 01 mov al, 1 \n"
" 00003334 66| B8 0001 mov ax, 1 \n"
" 00003338 B8 00000001 mov eax, 1 \n"
" 0000333D 48/ C7 C0 mov rax, 1 \n"
" 00000001 \n"
" \n"
" 00003344 40/ 8A C6 mov al, sil \n"
" 00003347 66| 8B C7 mov ax, di \n"
" 0000334A 8B C7 mov eax, edi \n"
" 0000334C 48/ 8B C7 mov rax, rdi \n"
" \n"
" 0000334F 8A 47 FC mov al, byte ptr [rdi - 4] \n"
" 00003352 8A 47 04 mov al, byte ptr [rdi + 4] \n"
" 00003355 66| 8B 47 04 mov ax, word ptr [rdi + 4] \n"
" 00003359 8B 47 04 mov eax, dword ptr [rdi + 4] \n"
" 0000335C 48/ 8B 47 04 mov rax, qword ptr [rdi + 4] \n"
" \n"
" 00003360 40/ 88 70 FC mov byte ptr [rax - 4], sil \n"
" 00003364 40/ 88 70 04 mov byte ptr [rax + 4], sil \n"
" 00003368 66| 89 78 04 mov word ptr [rax + 4], di \n"
" 0000336C 89 78 04 mov dword ptr [rax + 4], edi \n"
" 0000336F 48/ 89 78 04 mov qword ptr [rax + 4], rdi \n"
" \n"
" 00003373 66| 40/ 0F B6 C6 movzx ax, sil \n"
" 00003378 66| 0F B6 47 movzx ax, byte ptr [rdi + 4] \n"
" 04 \n"
" \n"
" 0000337D 40/ 0F B6 C6 movzx eax, sil \n"
" 00003381 0F B7 C7 movzx eax, di \n"
" 00003384 0F B6 47 04 movzx eax, byte ptr [rdi + 4] \n"
" 00003388 0F B7 47 04 movzx eax, word ptr [rdi + 4] \n"
" \n"
" 0000338C 48/ 0F B6 C6 movzx rax, sil \n"
" 00003390 48/ 0F B7 C7 movzx rax, di \n"
" 00003394 48/ 0F B6 47 movzx rax, byte ptr [rdi + 4] \n"
" 04 \n"
" 00003399 48/ 0F B7 47 movzx rax, word ptr [rdi + 4] \n"
" 04 \n"
" \n"
" \n"
" ; Source: rdi, target: rcx \n"
" 0000339E B1 01 mov cl, 1 \n"
" 000033A0 66| B9 0001 mov cx, 1 \n"
" 000033A4 B9 00000001 mov ecx, 1 \n"
" 000033A9 48/ C7 C1 mov rcx, 1 \n"
" 00000001 \n"
" \n"
" 000033B0 40/ 8A CE mov cl, sil \n"
" 000033B3 66| 8B CF mov cx, di \n"
" 000033B6 8B CF mov ecx, edi \n"
" 000033B8 48/ 8B CF mov rcx, rdi \n"
" \n"
" 000033BB 8A 4F FC mov cl, byte ptr [rdi - 4] \n"
" 000033BE 8A 4F 04 mov cl, byte ptr [rdi + 4] \n"
" 000033C1 66| 8B 4F 04 mov cx, word ptr [rdi + 4] \n"
" 000033C5 8B 4F 04 mov ecx, dword ptr [rdi + 4] \n"
" 000033C8 48/ 8B 4F 04 mov rcx, qword ptr [rdi + 4] \n"
" \n"
" 000033CC 40/ 88 71 FC mov byte ptr [rcx - 4], sil \n"
" 000033D0 40/ 88 71 04 mov byte ptr [rcx + 4], sil \n"
" 000033D4 66| 89 79 04 mov word ptr [rcx + 4], di \n"
" 000033D8 89 79 04 mov dword ptr [rcx + 4], edi \n"
" 000033DB 48/ 89 79 04 mov qword ptr [rcx + 4], rdi \n"
" \n"
" 000033DF 66| 40/ 0F B6 CE movzx cx, sil \n"
" 000033E4 66| 0F B6 4F movzx cx, byte ptr [rdi + 4] \n"
" 04 \n"
" \n"
" 000033E9 40/ 0F B6 CE movzx ecx, sil \n"
" 000033ED 0F B7 CF movzx ecx, di \n"
" 000033F0 0F B6 4F 04 movzx ecx, byte ptr [rdi + 4] \n"
" 000033F4 0F B7 4F 04 movzx ecx, word ptr [rdi + 4] \n"
" \n"
" 000033F8 48/ 0F B6 CE movzx rcx, sil \n"
" 000033FC 48/ 0F B7 CF movzx rcx, di \n"
" 00003400 48/ 0F B6 4F movzx rcx, byte ptr [rdi + 4] \n"
" 04 \n"
" 00003405 48/ 0F B7 4F movzx rcx, word ptr [rdi + 4] \n"
" 04 \n"
" \n"
" \n"
" ; Source: rdi, target: rdx \n"
" 0000340A B2 01 mov dl, 1 \n"
" 0000340C 66| BA 0001 mov dx, 1 \n"
" 00003410 BA 00000001 mov edx, 1 \n"
" 00003415 48/ C7 C2 mov rdx, 1 \n"
" 00000001 \n"
" \n"
" 0000341C 40/ 8A D6 mov dl, sil \n"
" 0000341F 66| 8B D7 mov dx, di \n"
" 00003422 8B D7 mov edx, edi \n"
" 00003424 48/ 8B D7 mov rdx, rdi \n"
" \n"
" 00003427 8A 57 FC mov dl, byte ptr [rdi - 4] \n"
" 0000342A 8A 57 04 mov dl, byte ptr [rdi + 4] \n"
" 0000342D 66| 8B 57 04 mov dx, word ptr [rdi + 4] \n"
" 00003431 8B 57 04 mov edx, dword ptr [rdi + 4] \n"
" 00003434 48/ 8B 57 04 mov rdx, qword ptr [rdi + 4] \n"
" \n"
" 00003438 40/ 88 72 FC mov byte ptr [rdx - 4], sil \n"
" 0000343C 40/ 88 72 04 mov byte ptr [rdx + 4], sil \n"
" 00003440 66| 89 7A 04 mov word ptr [rdx + 4], di \n"
" 00003444 89 7A 04 mov dword ptr [rdx + 4], edi \n"
" 00003447 48/ 89 7A 04 mov qword ptr [rdx + 4], rdi \n"
" \n"
" 0000344B 66| 40/ 0F B6 D6 movzx dx, sil \n"
" 00003450 66| 0F B6 57 movzx dx, byte ptr [rdi + 4] \n"
" 04 \n"
" \n"
" 00003455 40/ 0F B6 D6 movzx edx, sil \n"
" 00003459 0F B7 D7 movzx edx, di \n"
" 0000345C 0F B6 57 04 movzx edx, byte ptr [rdi + 4] \n"
" 00003460 0F B7 57 04 movzx edx, word ptr [rdi + 4] \n"
" \n"
" 00003464 48/ 0F B6 D6 movzx rdx, sil \n"
" 00003468 48/ 0F B7 D7 movzx rdx, di \n"
" 0000346C 48/ 0F B6 57 movzx rdx, byte ptr [rdi + 4] \n"
" 04 \n"
" 00003471 48/ 0F B7 57 movzx rdx, word ptr [rdi + 4] \n"
" 04 \n"
" \n"
" \n"
" ; Source: rdi, target: rbx \n"
" 00003476 B3 01 mov bl, 1 \n"
" 00003478 66| BB 0001 mov bx, 1 \n"
" 0000347C BB 00000001 mov ebx, 1 \n"
" 00003481 48/ C7 C3 mov rbx, 1 \n"
" 00000001 \n"
" \n"
" 00003488 40/ 8A DE mov bl, sil \n"
" 0000348B 66| 8B DF mov bx, di \n"
" 0000348E 8B DF mov ebx, edi \n"
" 00003490 48/ 8B DF mov rbx, rdi \n"
" \n"
" 00003493 8A 5F FC mov bl, byte ptr [rdi - 4] \n"
" 00003496 8A 5F 04 mov bl, byte ptr [rdi + 4] \n"
" 00003499 66| 8B 5F 04 mov bx, word ptr [rdi + 4] \n"
" 0000349D 8B 5F 04 mov ebx, dword ptr [rdi + 4] \n"
" 000034A0 48/ 8B 5F 04 mov rbx, qword ptr [rdi + 4] \n"
" \n"
" 000034A4 40/ 88 73 FC mov byte ptr [rbx - 4], sil \n"
" 000034A8 40/ 88 73 04 mov byte ptr [rbx + 4], sil \n"
" 000034AC 66| 89 7B 04 mov word ptr [rbx + 4], di \n"
" 000034B0 89 7B 04 mov dword ptr [rbx + 4], edi \n"
" 000034B3 48/ 89 7B 04 mov qword ptr [rbx + 4], rdi \n"
" \n"
" 000034B7 66| 40/ 0F B6 DE movzx bx, sil \n"
" 000034BC 66| 0F B6 5F movzx bx, byte ptr [rdi + 4] \n"
" 04 \n"
" \n"
" 000034C1 40/ 0F B6 DE movzx ebx, sil \n"
" 000034C5 0F B7 DF movzx ebx, di \n"
" 000034C8 0F B6 5F 04 movzx ebx, byte ptr [rdi + 4] \n"
" 000034CC 0F B7 5F 04 movzx ebx, word ptr [rdi + 4] \n"
" \n"
" 000034D0 48/ 0F B6 DE movzx rbx, sil \n"
" 000034D4 48/ 0F B7 DF movzx rbx, di \n"
" 000034D8 48/ 0F B6 5F movzx rbx, byte ptr [rdi + 4] \n"
" 04 \n"
" 000034DD 48/ 0F B7 5F movzx rbx, word ptr [rdi + 4] \n"
" 04 \n"
" \n"
" \n"
" ; Source: rdi, target: rsp \n"
" 000034E2 40/ B4 01 mov spl, 1 \n"
" 000034E5 66| BC 0001 mov sp, 1 \n"
" 000034E9 BC 00000001 mov esp, 1 \n"
" 000034EE 48/ C7 C4 mov rsp, 1 \n"
" 00000001 \n"
" \n"
" 000034F5 40/ 8A E6 mov spl, sil \n"
" 000034F8 66| 8B E7 mov sp, di \n"
" 000034FB 8B E7 mov esp, edi \n"
" 000034FD 48/ 8B E7 mov rsp, rdi \n"
" \n"
" 00003500 40/ 8A 67 FC mov spl, byte ptr [rdi - 4] \n"
" 00003504 40/ 8A 67 04 mov spl, byte ptr [rdi + 4] \n"
" 00003508 66| 8B 67 04 mov sp, word ptr [rdi + 4] \n"
" 0000350C 8B 67 04 mov esp, dword ptr [rdi + 4] \n"
" 0000350F 48/ 8B 67 04 mov rsp, qword ptr [rdi + 4] \n"
" \n"
" 00003513 40/ 88 74 24 mov byte ptr [rsp - 4], sil \n"
" FC \n"
" 00003518 40/ 88 74 24 mov byte ptr [rsp + 4], sil \n"
" 04 \n"
" 0000351D 66| 89 7C 24 mov word ptr [rsp + 4], di \n"
" 04 \n"
" 00003522 89 7C 24 04 mov dword ptr [rsp + 4], edi \n"
" 00003526 48/ 89 7C 24 mov qword ptr [rsp + 4], rdi \n"
" 04 \n"
" \n"
" 0000352B 66| 40/ 0F B6 E6 movzx sp, sil \n"
" 00003530 66| 0F B6 67 movzx sp, byte ptr [rdi + 4] \n"
" 04 \n"
" \n"
" 00003535 40/ 0F B6 E6 movzx esp, sil \n"
" 00003539 0F B7 E7 movzx esp, di \n"
" 0000353C 0F B6 67 04 movzx esp, byte ptr [rdi + 4] \n"
" 00003540 0F B7 67 04 movzx esp, word ptr [rdi + 4] \n"
" \n"
" 00003544 48/ 0F B6 E6 movzx rsp, sil \n"
" 00003548 48/ 0F B7 E7 movzx rsp, di \n"
" 0000354C 48/ 0F B6 67 movzx rsp, byte ptr [rdi + 4] \n"
" 04 \n"
" 00003551 48/ 0F B7 67 movzx rsp, word ptr [rdi + 4] \n"
" 04 \n"
" \n"
" \n"
" ; Source: rdi, target: rbp \n"
" 00003556 40/ B5 01 mov bpl, 1 \n"
" 00003559 66| BD 0001 mov bp, 1 \n"
" 0000355D BD 00000001 mov ebp, 1 \n"
" 00003562 48/ C7 C5 mov rbp, 1 \n"
" 00000001 \n"
" \n"
" 00003569 40/ 8A EE mov bpl, sil \n"
" 0000356C 66| 8B EF mov bp, di \n"
" 0000356F 8B EF mov ebp, edi \n"
" 00003571 48/ 8B EF mov rbp, rdi \n"
" \n"
" 00003574 40/ 8A 6F FC mov bpl, byte ptr [rdi - 4] \n"
" 00003578 40/ 8A 6F 04 mov bpl, byte ptr [rdi + 4] \n"
" 0000357C 66| 8B 6F 04 mov bp, word ptr [rdi + 4] \n"
" 00003580 8B 6F 04 mov ebp, dword ptr [rdi + 4] \n"
" 00003583 48/ 8B 6F 04 mov rbp, qword ptr [rdi + 4] \n"
" \n"
" 00003587 40/ 88 75 FC mov byte ptr [rbp - 4], sil \n"
" 0000358B 40/ 88 75 04 mov byte ptr [rbp + 4], sil \n"
" 0000358F 66| 89 7D 04 mov word ptr [rbp + 4], di \n"
" 00003593 89 7D 04 mov dword ptr [rbp + 4], edi \n"
" 00003596 48/ 89 7D 04 mov qword ptr [rbp + 4], rdi \n"
" \n"
" 0000359A 66| 40/ 0F B6 EE movzx bp, sil \n"
" 0000359F 66| 0F B6 6F movzx bp, byte ptr [rdi + 4] \n"
" 04 \n"
" \n"
" 000035A4 40/ 0F B6 EE movzx ebp, sil \n"
" 000035A8 0F B7 EF movzx ebp, di \n"
" 000035AB 0F B6 6F 04 movzx ebp, byte ptr [rdi + 4] \n"
" 000035AF 0F B7 6F 04 movzx ebp, word ptr [rdi + 4] \n"
" \n"
" 000035B3 48/ 0F B6 EE movzx rbp, sil \n"
" 000035B7 48/ 0F B7 EF movzx rbp, di \n"
" 000035BB 48/ 0F B6 6F movzx rbp, byte ptr [rdi + 4] \n"
" 04 \n"
" 000035C0 48/ 0F B7 6F movzx rbp, word ptr [rdi + 4] \n"
" 04 \n"
" \n"
" \n"
" ; Source: rdi, target: rsi \n"
" 000035C5 40/ B7 01 mov dil, 1 \n"
" 000035C8 66| BE 0001 mov si, 1 \n"
" 000035CC BE 00000001 mov esi, 1 \n"
" 000035D1 48/ C7 C6 mov rsi, 1 \n"
" 00000001 \n"
" \n"
" 000035D8 40/ 8A FE mov dil, sil \n"
" 000035DB 66| 8B F7 mov si, di \n"
" 000035DE 8B F7 mov esi, edi \n"
" 000035E0 48/ 8B F7 mov rsi, rdi \n"
" \n"
" 000035E3 40/ 8A 7F FC mov dil, byte ptr [rdi - 4] \n"
" 000035E7 40/ 8A 7F 04 mov dil, byte ptr [rdi + 4] \n"
" 000035EB 66| 8B 77 04 mov si, word ptr [rdi + 4] \n"
" 000035EF 8B 77 04 mov esi, dword ptr [rdi + 4] \n"
" 000035F2 48/ 8B 77 04 mov rsi, qword ptr [rdi + 4] \n"
" \n"
" 000035F6 40/ 88 76 FC mov byte ptr [rsi - 4], sil \n"
" 000035FA 40/ 88 76 04 mov byte ptr [rsi + 4], sil \n"
" 000035FE 66| 89 7E 04 mov word ptr [rsi + 4], di \n"
" 00003602 89 7E 04 mov dword ptr [rsi + 4], edi \n"
" 00003605 48/ 89 7E 04 mov qword ptr [rsi + 4], rdi \n"
" \n"
" 00003609 66| 40/ 0F B6 F6 movzx si, sil \n"
" 0000360E 66| 0F B6 77 movzx si, byte ptr [rdi + 4] \n"
" 04 \n"
" \n"
" 00003613 40/ 0F B6 F6 movzx esi, sil \n"
" 00003617 0F B7 F7 movzx esi, di \n"
" 0000361A 0F B6 77 04 movzx esi, byte ptr [rdi + 4] \n"
" 0000361E 0F B7 77 04 movzx esi, word ptr [rdi + 4] \n"
" \n"
" 00003622 48/ 0F B6 F6 movzx rsi, sil \n"
" 00003626 48/ 0F B7 F7 movzx rsi, di \n"
" 0000362A 48/ 0F B6 77 movzx rsi, byte ptr [rdi + 4] \n"
" 04 \n"
" 0000362F 48/ 0F B7 77 movzx rsi, word ptr [rdi + 4] \n"
" 04 \n"
" \n"
" \n"
" ; Source: rdi, target: rdi \n"
" 00003634 40/ B6 01 mov sil, 1 \n"
" 00003637 66| BF 0001 mov di, 1 \n"
" 0000363B BF 00000001 mov edi, 1 \n"
" 00003640 48/ C7 C7 mov rdi, 1 \n"
" 00000001 \n"
" \n"
" 00003647 40/ 8A F6 mov sil, sil \n"
" 0000364A 66| 8B FF mov di, di \n"
" 0000364D 8B FF mov edi, edi \n"
" 0000364F 48/ 8B FF mov rdi, rdi \n"
" \n"
" 00003652 40/ 8A 77 FC mov sil, byte ptr [rdi - 4] \n"
" 00003656 40/ 8A 77 04 mov sil, byte ptr [rdi + 4] \n"
" 0000365A 66| 8B 7F 04 mov di, word ptr [rdi + 4] \n"
" 0000365E 8B 7F 04 mov edi, dword ptr [rdi + 4] \n"
" 00003661 48/ 8B 7F 04 mov rdi, qword ptr [rdi + 4] \n"
" \n"
" 00003665 40/ 88 77 FC mov byte ptr [rdi - 4], sil \n"
" 00003669 40/ 88 77 04 mov byte ptr [rdi + 4], sil \n"
" 0000366D 66| 89 7F 04 mov word ptr [rdi + 4], di \n"
" 00003671 89 7F 04 mov dword ptr [rdi + 4], edi \n"
" 00003674 48/ 89 7F 04 mov qword ptr [rdi + 4], rdi \n"
" \n"
" 00003678 66| 40/ 0F B6 FE movzx di, sil \n"
" 0000367D 66| 0F B6 7F movzx di, byte ptr [rdi + 4] \n"
" 04 \n"
" \n"
" 00003682 40/ 0F B6 FE movzx edi, sil \n"
" 00003686 0F B7 FF movzx edi, di \n"
" 00003689 0F B6 7F 04 movzx edi, byte ptr [rdi + 4] \n"
" 0000368D 0F B7 7F 04 movzx edi, word ptr [rdi + 4] \n"
" \n"
" 00003691 48/ 0F B6 FE movzx rdi, sil \n"
" 00003695 48/ 0F B7 FF movzx rdi, di \n"
" 00003699 48/ 0F B6 7F movzx rdi, byte ptr [rdi + 4] \n"
" 04 \n"
" 0000369E 48/ 0F B7 7F movzx rdi, word ptr [rdi + 4] \n"
" 04 \n"
" \n"
" \n"
" ; Source: rdi, target: r8 \n"
" 000036A3 41/ B0 01 mov r8b, 1 \n"
" 000036A6 66| 41/ B8 mov r8w, 1 \n"
" 0001 \n"
" 000036AB 41/ B8 mov r8d, 1 \n"
" 00000001 \n"
" 000036B1 49/ C7 C0 mov r8, 1 \n"
" 00000001 \n"
" \n"
" 000036B8 44/ 8A C6 mov r8b, sil \n"
" 000036BB 66| 44/ 8B C7 mov r8w, di \n"
" 000036BF 44/ 8B C7 mov r8d, edi \n"
" 000036C2 4C/ 8B C7 mov r8, rdi \n"
" \n"
" 000036C5 44/ 8A 47 FC mov r8b, byte ptr [rdi - 4] \n"
" 000036C9 44/ 8A 47 04 mov r8b, byte ptr [rdi + 4] \n"
" 000036CD 66| 44/ 8B 47 mov r8w, word ptr [rdi + 4] \n"
" 04 \n"
" 000036D2 44/ 8B 47 04 mov r8d, dword ptr [rdi + 4] \n"
" 000036D6 4C/ 8B 47 04 mov r8, qword ptr [rdi + 4] \n"
" \n"
" 000036DA 41/ 88 70 FC mov byte ptr [r8 - 4], sil \n"
" 000036DE 41/ 88 70 04 mov byte ptr [r8 + 4], sil \n"
" 000036E2 66| 41/ 89 78 mov word ptr [r8 + 4], di \n"
" 04 \n"
" 000036E7 41/ 89 78 04 mov dword ptr [r8 + 4], edi \n"
" 000036EB 49/ 89 78 04 mov qword ptr [r8 + 4], rdi \n"
" \n"
" 000036EF 66| 44/ 0F B6 C6 movzx r8w, sil \n"
" 000036F4 66| 44/ 0F B6 47 movzx r8w, byte ptr [rdi + 4] \n"
" 04 \n"
" \n"
" 000036FA 44/ 0F B6 C6 movzx r8d, sil \n"
" 000036FE 44/ 0F B7 C7 movzx r8d, di \n"
" 00003702 44/ 0F B6 47 movzx r8d, byte ptr [rdi + 4] \n"
" 04 \n"
" 00003707 44/ 0F B7 47 movzx r8d, word ptr [rdi + 4] \n"
" 04 \n"
" \n"
" 0000370C 4C/ 0F B6 C6 movzx r8, sil \n"
" 00003710 4C/ 0F B7 C7 movzx r8, di \n"
" 00003714 4C/ 0F B6 47 movzx r8, byte ptr [rdi + 4] \n"
" 04 \n"
" 00003719 4C/ 0F B7 47 movzx r8, word ptr [rdi + 4] \n"
" 04 \n"
" \n"
" \n"
" ; Source: rdi, target: r9 \n"
" 0000371E 41/ B1 01 mov r9b, 1 \n"
" 00003721 66| 41/ B9 mov r9w, 1 \n"
" 0001 \n"
" 00003726 41/ B9 mov r9d, 1 \n"
" 00000001 \n"
" 0000372C 49/ C7 C1 mov r9, 1 \n"
" 00000001 \n"
" \n"
" 00003733 44/ 8A CE mov r9b, sil \n"
" 00003736 66| 44/ 8B CF mov r9w, di \n"
" 0000373A 44/ 8B CF mov r9d, edi \n"
" 0000373D 4C/ 8B CF mov r9, rdi \n"
" \n"
" 00003740 44/ 8A 4F FC mov r9b, byte ptr [rdi - 4] \n"
" 00003744 44/ 8A 4F 04 mov r9b, byte ptr [rdi + 4] \n"
" 00003748 66| 44/ 8B 4F mov r9w, word ptr [rdi + 4] \n"
" 04 \n"
" 0000374D 44/ 8B 4F 04 mov r9d, dword ptr [rdi + 4] \n"
" 00003751 4C/ 8B 4F 04 mov r9, qword ptr [rdi + 4] \n"
" \n"
" 00003755 41/ 88 71 FC mov byte ptr [r9 - 4], sil \n"
" 00003759 41/ 88 71 04 mov byte ptr [r9 + 4], sil \n"
" 0000375D 66| 41/ 89 79 mov word ptr [r9 + 4], di \n"
" 04 \n"
" 00003762 41/ 89 79 04 mov dword ptr [r9 + 4], edi \n"
" 00003766 49/ 89 79 04 mov qword ptr [r9 + 4], rdi \n"
" \n"
" 0000376A 66| 44/ 0F B6 CE movzx r9w, sil \n"
" 0000376F 66| 44/ 0F B6 4F movzx r9w, byte ptr [rdi + 4] \n"
" 04 \n"
" \n"
" 00003775 44/ 0F B6 CE movzx r9d, sil \n"
" 00003779 44/ 0F B7 CF movzx r9d, di \n"
" 0000377D 44/ 0F B6 4F movzx r9d, byte ptr [rdi + 4] \n"
" 04 \n"
" 00003782 44/ 0F B7 4F movzx r9d, word ptr [rdi + 4] \n"
" 04 \n"
" \n"
" 00003787 4C/ 0F B6 CE movzx r9, sil \n"
" 0000378B 4C/ 0F B7 CF movzx r9, di \n"
" 0000378F 4C/ 0F B6 4F movzx r9, byte ptr [rdi + 4] \n"
" 04 \n"
" 00003794 4C/ 0F B7 4F movzx r9, word ptr [rdi + 4] \n"
" 04 \n"
" \n"
" \n"
" ; Source: rdi, target: r10 \n"
" 00003799 41/ B2 01 mov r10b, 1 \n"
" 0000379C 66| 41/ BA mov r10w, 1 \n"
" 0001 \n"
" 000037A1 41/ BA mov r10d, 1 \n"
" 00000001 \n"
" 000037A7 49/ C7 C2 mov r10, 1 \n"
" 00000001 \n"
" \n"
" 000037AE 44/ 8A D6 mov r10b, sil \n"
" 000037B1 66| 44/ 8B D7 mov r10w, di \n"
" 000037B5 44/ 8B D7 mov r10d, edi \n"
" 000037B8 4C/ 8B D7 mov r10, rdi \n"
" \n"
" 000037BB 44/ 8A 57 FC mov r10b, byte ptr [rdi - 4] \n"
" 000037BF 44/ 8A 57 04 mov r10b, byte ptr [rdi + 4] \n"
" 000037C3 66| 44/ 8B 57 mov r10w, word ptr [rdi + 4] \n"
" 04 \n"
" 000037C8 44/ 8B 57 04 mov r10d, dword ptr [rdi + 4] \n"
" 000037CC 4C/ 8B 57 04 mov r10, qword ptr [rdi + 4] \n"
" \n"
" 000037D0 41/ 88 72 FC mov byte ptr [r10 - 4], sil \n"
" 000037D4 41/ 88 72 04 mov byte ptr [r10 + 4], sil \n"
" 000037D8 66| 41/ 89 7A mov word ptr [r10 + 4], di \n"
" 04 \n"
" 000037DD 41/ 89 7A 04 mov dword ptr [r10 + 4], edi \n"
" 000037E1 49/ 89 7A 04 mov qword ptr [r10 + 4], rdi \n"
" \n"
" 000037E5 66| 44/ 0F B6 D6 movzx r10w, sil \n"
" 000037EA 66| 44/ 0F B6 57 movzx r10w, byte ptr [rdi + 4] \n"
" 04 \n"
" \n";
ml64Output +=
" 000037F0 44/ 0F B6 D6 movzx r10d, sil \n"
" 000037F4 44/ 0F B7 D7 movzx r10d, di \n"
" 000037F8 44/ 0F B6 57 movzx r10d, byte ptr [rdi + 4] \n"
" 04 \n"
" 000037FD 44/ 0F B7 57 movzx r10d, word ptr [rdi + 4] \n"
" 04 \n"
" \n"
" 00003802 4C/ 0F B6 D6 movzx r10, sil \n"
" 00003806 4C/ 0F B7 D7 movzx r10, di \n"
" 0000380A 4C/ 0F B6 57 movzx r10, byte ptr [rdi + 4] \n"
" 04 \n"
" 0000380F 4C/ 0F B7 57 movzx r10, word ptr [rdi + 4] \n"
" 04 \n"
" \n"
" \n"
" ; Source: rdi, target: r11 \n"
" 00003814 41/ B3 01 mov r11b, 1 \n"
" 00003817 66| 41/ BB mov r11w, 1 \n"
" 0001 \n"
" 0000381C 41/ BB mov r11d, 1 \n"
" 00000001 \n"
" 00003822 49/ C7 C3 mov r11, 1 \n"
" 00000001 \n"
" \n"
" 00003829 44/ 8A DE mov r11b, sil \n"
" 0000382C 66| 44/ 8B DF mov r11w, di \n"
" 00003830 44/ 8B DF mov r11d, edi \n"
" 00003833 4C/ 8B DF mov r11, rdi \n"
" \n"
" 00003836 44/ 8A 5F FC mov r11b, byte ptr [rdi - 4] \n"
" 0000383A 44/ 8A 5F 04 mov r11b, byte ptr [rdi + 4] \n"
" 0000383E 66| 44/ 8B 5F mov r11w, word ptr [rdi + 4] \n"
" 04 \n"
" 00003843 44/ 8B 5F 04 mov r11d, dword ptr [rdi + 4] \n"
" 00003847 4C/ 8B 5F 04 mov r11, qword ptr [rdi + 4] \n"
" \n"
" 0000384B 41/ 88 73 FC mov byte ptr [r11 - 4], sil \n"
" 0000384F 41/ 88 73 04 mov byte ptr [r11 + 4], sil \n"
" 00003853 66| 41/ 89 7B mov word ptr [r11 + 4], di \n"
" 04 \n"
" 00003858 41/ 89 7B 04 mov dword ptr [r11 + 4], edi \n"
" 0000385C 49/ 89 7B 04 mov qword ptr [r11 + 4], rdi \n"
" \n"
" 00003860 66| 44/ 0F B6 DE movzx r11w, sil \n"
" 00003865 66| 44/ 0F B6 5F movzx r11w, byte ptr [rdi + 4] \n"
" 04 \n"
" \n"
" 0000386B 44/ 0F B6 DE movzx r11d, sil \n"
" 0000386F 44/ 0F B7 DF movzx r11d, di \n"
" 00003873 44/ 0F B6 5F movzx r11d, byte ptr [rdi + 4] \n"
" 04 \n"
" 00003878 44/ 0F B7 5F movzx r11d, word ptr [rdi + 4] \n"
" 04 \n"
" \n"
" 0000387D 4C/ 0F B6 DE movzx r11, sil \n"
" 00003881 4C/ 0F B7 DF movzx r11, di \n"
" 00003885 4C/ 0F B6 5F movzx r11, byte ptr [rdi + 4] \n"
" 04 \n"
" 0000388A 4C/ 0F B7 5F movzx r11, word ptr [rdi + 4] \n"
" 04 \n"
" \n"
" \n"
" ; Source: rdi, target: r12 \n"
" 0000388F 41/ B4 01 mov r12b, 1 \n"
" 00003892 66| 41/ BC mov r12w, 1 \n"
" 0001 \n"
" 00003897 41/ BC mov r12d, 1 \n"
" 00000001 \n"
" 0000389D 49/ C7 C4 mov r12, 1 \n"
" 00000001 \n"
" \n"
" 000038A4 44/ 8A E6 mov r12b, sil \n"
" 000038A7 66| 44/ 8B E7 mov r12w, di \n"
" 000038AB 44/ 8B E7 mov r12d, edi \n"
" 000038AE 4C/ 8B E7 mov r12, rdi \n"
" \n"
" 000038B1 44/ 8A 67 FC mov r12b, byte ptr [rdi - 4] \n"
" 000038B5 44/ 8A 67 04 mov r12b, byte ptr [rdi + 4] \n"
" 000038B9 66| 44/ 8B 67 mov r12w, word ptr [rdi + 4] \n"
" 04 \n"
" 000038BE 44/ 8B 67 04 mov r12d, dword ptr [rdi + 4] \n"
" 000038C2 4C/ 8B 67 04 mov r12, qword ptr [rdi + 4] \n"
" \n"
" 000038C6 41/ 88 74 24 mov byte ptr [r12 - 4], sil \n"
" FC \n"
" 000038CB 41/ 88 74 24 mov byte ptr [r12 + 4], sil \n"
" 04 \n"
" 000038D0 66| 41/ 89 7C 24 mov word ptr [r12 + 4], di \n"
" 04 \n"
" 000038D6 41/ 89 7C 24 mov dword ptr [r12 + 4], edi \n"
" 04 \n"
" 000038DB 49/ 89 7C 24 mov qword ptr [r12 + 4], rdi \n"
" 04 \n"
" \n"
" 000038E0 66| 44/ 0F B6 E6 movzx r12w, sil \n"
" 000038E5 66| 44/ 0F B6 67 movzx r12w, byte ptr [rdi + 4] \n"
" 04 \n"
" \n"
" 000038EB 44/ 0F B6 E6 movzx r12d, sil \n"
" 000038EF 44/ 0F B7 E7 movzx r12d, di \n"
" 000038F3 44/ 0F B6 67 movzx r12d, byte ptr [rdi + 4] \n"
" 04 \n"
" 000038F8 44/ 0F B7 67 movzx r12d, word ptr [rdi + 4] \n"
" 04 \n"
" \n"
" 000038FD 4C/ 0F B6 E6 movzx r12, sil \n"
" 00003901 4C/ 0F B7 E7 movzx r12, di \n"
" 00003905 4C/ 0F B6 67 movzx r12, byte ptr [rdi + 4] \n"
" 04 \n"
" 0000390A 4C/ 0F B7 67 movzx r12, word ptr [rdi + 4] \n"
" 04 \n"
" \n"
" \n"
" ; Source: rdi, target: r13 \n"
" 0000390F 41/ B5 01 mov r13b, 1 \n"
" 00003912 66| 41/ BD mov r13w, 1 \n"
" 0001 \n"
" 00003917 41/ BD mov r13d, 1 \n"
" 00000001 \n"
" 0000391D 49/ C7 C5 mov r13, 1 \n"
" 00000001 \n"
" \n"
" 00003924 44/ 8A EE mov r13b, sil \n"
" 00003927 66| 44/ 8B EF mov r13w, di \n"
" 0000392B 44/ 8B EF mov r13d, edi \n"
" 0000392E 4C/ 8B EF mov r13, rdi \n"
" \n"
" 00003931 44/ 8A 6F FC mov r13b, byte ptr [rdi - 4] \n"
" 00003935 44/ 8A 6F 04 mov r13b, byte ptr [rdi + 4] \n"
" 00003939 66| 44/ 8B 6F mov r13w, word ptr [rdi + 4] \n"
" 04 \n"
" 0000393E 44/ 8B 6F 04 mov r13d, dword ptr [rdi + 4] \n"
" 00003942 4C/ 8B 6F 04 mov r13, qword ptr [rdi + 4] \n"
" \n"
" 00003946 41/ 88 75 FC mov byte ptr [r13 - 4], sil \n"
" 0000394A 41/ 88 75 04 mov byte ptr [r13 + 4], sil \n"
" 0000394E 66| 41/ 89 7D mov word ptr [r13 + 4], di \n"
" 04 \n"
" 00003953 41/ 89 7D 04 mov dword ptr [r13 + 4], edi \n"
" 00003957 49/ 89 7D 04 mov qword ptr [r13 + 4], rdi \n"
" \n"
" 0000395B 66| 44/ 0F B6 EE movzx r13w, sil \n"
" 00003960 66| 44/ 0F B6 6F movzx r13w, byte ptr [rdi + 4] \n"
" 04 \n"
" \n"
" 00003966 44/ 0F B6 EE movzx r13d, sil \n"
" 0000396A 44/ 0F B7 EF movzx r13d, di \n"
" 0000396E 44/ 0F B6 6F movzx r13d, byte ptr [rdi + 4] \n"
" 04 \n"
" 00003973 44/ 0F B7 6F movzx r13d, word ptr [rdi + 4] \n"
" 04 \n"
" \n"
" 00003978 4C/ 0F B6 EE movzx r13, sil \n"
" 0000397C 4C/ 0F B7 EF movzx r13, di \n"
" 00003980 4C/ 0F B6 6F movzx r13, byte ptr [rdi + 4] \n"
" 04 \n"
" 00003985 4C/ 0F B7 6F movzx r13, word ptr [rdi + 4] \n"
" 04 \n"
" \n"
" \n"
" ; Source: rdi, target: r14 \n"
" 0000398A 41/ B6 01 mov r14b, 1 \n"
" 0000398D 66| 41/ BE mov r14w, 1 \n"
" 0001 \n"
" 00003992 41/ BE mov r14d, 1 \n"
" 00000001 \n"
" 00003998 49/ C7 C6 mov r14, 1 \n"
" 00000001 \n"
" \n"
" 0000399F 44/ 8A F6 mov r14b, sil \n"
" 000039A2 66| 44/ 8B F7 mov r14w, di \n"
" 000039A6 44/ 8B F7 mov r14d, edi \n"
" 000039A9 4C/ 8B F7 mov r14, rdi \n"
" \n"
" 000039AC 44/ 8A 77 FC mov r14b, byte ptr [rdi - 4] \n"
" 000039B0 44/ 8A 77 04 mov r14b, byte ptr [rdi + 4] \n"
" 000039B4 66| 44/ 8B 77 mov r14w, word ptr [rdi + 4] \n"
" 04 \n"
" 000039B9 44/ 8B 77 04 mov r14d, dword ptr [rdi + 4] \n"
" 000039BD 4C/ 8B 77 04 mov r14, qword ptr [rdi + 4] \n"
" \n"
" 000039C1 41/ 88 76 FC mov byte ptr [r14 - 4], sil \n"
" 000039C5 41/ 88 76 04 mov byte ptr [r14 + 4], sil \n"
" 000039C9 66| 41/ 89 7E mov word ptr [r14 + 4], di \n"
" 04 \n"
" 000039CE 41/ 89 7E 04 mov dword ptr [r14 + 4], edi \n"
" 000039D2 49/ 89 7E 04 mov qword ptr [r14 + 4], rdi \n"
" \n"
" 000039D6 66| 44/ 0F B6 F6 movzx r14w, sil \n"
" 000039DB 66| 44/ 0F B6 77 movzx r14w, byte ptr [rdi + 4] \n"
" 04 \n"
" \n"
" 000039E1 44/ 0F B6 F6 movzx r14d, sil \n"
" 000039E5 44/ 0F B7 F7 movzx r14d, di \n"
" 000039E9 44/ 0F B6 77 movzx r14d, byte ptr [rdi + 4] \n"
" 04 \n"
" 000039EE 44/ 0F B7 77 movzx r14d, word ptr [rdi + 4] \n"
" 04 \n"
" \n"
" 000039F3 4C/ 0F B6 F6 movzx r14, sil \n"
" 000039F7 4C/ 0F B7 F7 movzx r14, di \n"
" 000039FB 4C/ 0F B6 77 movzx r14, byte ptr [rdi + 4] \n"
" 04 \n"
" 00003A00 4C/ 0F B7 77 movzx r14, word ptr [rdi + 4] \n"
" 04 \n"
" \n"
" \n"
" ; Source: rdi, target: r15 \n"
" 00003A05 41/ B7 01 mov r15b, 1 \n"
" 00003A08 66| 41/ BF mov r15w, 1 \n"
" 0001 \n"
" 00003A0D 41/ BF mov r15d, 1 \n"
" 00000001 \n"
" 00003A13 49/ C7 C7 mov r15, 1 \n"
" 00000001 \n"
" \n"
" 00003A1A 44/ 8A FE mov r15b, sil \n"
" 00003A1D 66| 44/ 8B FF mov r15w, di \n"
" 00003A21 44/ 8B FF mov r15d, edi \n"
" 00003A24 4C/ 8B FF mov r15, rdi \n"
" \n"
" 00003A27 44/ 8A 7F FC mov r15b, byte ptr [rdi - 4] \n"
" 00003A2B 44/ 8A 7F 04 mov r15b, byte ptr [rdi + 4] \n"
" 00003A2F 66| 44/ 8B 7F mov r15w, word ptr [rdi + 4] \n"
" 04 \n"
" 00003A34 44/ 8B 7F 04 mov r15d, dword ptr [rdi + 4] \n"
" 00003A38 4C/ 8B 7F 04 mov r15, qword ptr [rdi + 4] \n"
" \n"
" 00003A3C 41/ 88 77 FC mov byte ptr [r15 - 4], sil \n"
" 00003A40 41/ 88 77 04 mov byte ptr [r15 + 4], sil \n"
" 00003A44 66| 41/ 89 7F mov word ptr [r15 + 4], di \n"
" 04 \n"
" 00003A49 41/ 89 7F 04 mov dword ptr [r15 + 4], edi \n"
" 00003A4D 49/ 89 7F 04 mov qword ptr [r15 + 4], rdi \n"
" \n"
" 00003A51 66| 44/ 0F B6 FE movzx r15w, sil \n"
" 00003A56 66| 44/ 0F B6 7F movzx r15w, byte ptr [rdi + 4] \n"
" 04 \n"
" \n"
" 00003A5C 44/ 0F B6 FE movzx r15d, sil \n"
" 00003A60 44/ 0F B7 FF movzx r15d, di \n"
" 00003A64 44/ 0F B6 7F movzx r15d, byte ptr [rdi + 4] \n"
" 04 \n"
" 00003A69 44/ 0F B7 7F movzx r15d, word ptr [rdi + 4] \n"
" 04 \n"
" \n"
" 00003A6E 4C/ 0F B6 FE movzx r15, sil \n"
" 00003A72 4C/ 0F B7 FF movzx r15, di \n"
" 00003A76 4C/ 0F B6 7F movzx r15, byte ptr [rdi + 4] \n"
" 04 \n"
" 00003A7B 4C/ 0F B7 7F movzx r15, word ptr [rdi + 4] \n"
" 04 \n"
" \n"
" \n"
" ; Source: r8, target: rax \n"
" 00003A80 B0 01 mov al, 1 \n"
" 00003A82 66| B8 0001 mov ax, 1 \n"
" 00003A86 B8 00000001 mov eax, 1 \n"
" 00003A8B 48/ C7 C0 mov rax, 1 \n"
" 00000001 \n"
" \n"
" 00003A92 41/ 8A C0 mov al, r8b \n"
" 00003A95 66| 41/ 8B C0 mov ax, r8w \n"
" 00003A99 41/ 8B C0 mov eax, r8d \n"
" 00003A9C 49/ 8B C0 mov rax, r8 \n"
" \n"
" 00003A9F 41/ 8A 40 FC mov al, byte ptr [r8 - 4] \n"
" 00003AA3 41/ 8A 40 04 mov al, byte ptr [r8 + 4] \n"
" 00003AA7 66| 41/ 8B 40 mov ax, word ptr [r8 + 4] \n"
" 04 \n"
" 00003AAC 41/ 8B 40 04 mov eax, dword ptr [r8 + 4] \n"
" 00003AB0 49/ 8B 40 04 mov rax, qword ptr [r8 + 4] \n"
" \n"
" 00003AB4 44/ 88 40 FC mov byte ptr [rax - 4], r8b \n"
" 00003AB8 44/ 88 40 04 mov byte ptr [rax + 4], r8b \n"
" 00003ABC 66| 44/ 89 40 mov word ptr [rax + 4], r8w \n"
" 04 \n"
" 00003AC1 44/ 89 40 04 mov dword ptr [rax + 4], r8d \n"
" 00003AC5 4C/ 89 40 04 mov qword ptr [rax + 4], r8 \n"
" \n"
" 00003AC9 66| 41/ 0F B6 C0 movzx ax, r8b \n"
" 00003ACE 66| 41/ 0F B6 40 movzx ax, byte ptr [r8 + 4] \n"
" 04 \n"
" \n"
" 00003AD4 41/ 0F B6 C0 movzx eax, r8b \n"
" 00003AD8 41/ 0F B7 C0 movzx eax, r8w \n"
" 00003ADC 41/ 0F B6 40 movzx eax, byte ptr [r8 + 4] \n"
" 04 \n"
" 00003AE1 41/ 0F B7 40 movzx eax, word ptr [r8 + 4] \n"
" 04 \n"
" \n"
" 00003AE6 49/ 0F B6 C0 movzx rax, r8b \n"
" 00003AEA 49/ 0F B7 C0 movzx rax, r8w \n"
" 00003AEE 49/ 0F B6 40 movzx rax, byte ptr [r8 + 4] \n"
" 04 \n"
" 00003AF3 49/ 0F B7 40 movzx rax, word ptr [r8 + 4] \n"
" 04 \n"
" \n"
" \n"
" ; Source: r8, target: rcx \n"
" 00003AF8 B1 01 mov cl, 1 \n"
" 00003AFA 66| B9 0001 mov cx, 1 \n"
" 00003AFE B9 00000001 mov ecx, 1 \n"
" 00003B03 48/ C7 C1 mov rcx, 1 \n"
" 00000001 \n"
" \n"
" 00003B0A 41/ 8A C8 mov cl, r8b \n"
" 00003B0D 66| 41/ 8B C8 mov cx, r8w \n"
" 00003B11 41/ 8B C8 mov ecx, r8d \n"
" 00003B14 49/ 8B C8 mov rcx, r8 \n"
" \n"
" 00003B17 41/ 8A 48 FC mov cl, byte ptr [r8 - 4] \n"
" 00003B1B 41/ 8A 48 04 mov cl, byte ptr [r8 + 4] \n"
" 00003B1F 66| 41/ 8B 48 mov cx, word ptr [r8 + 4] \n"
" 04 \n"
" 00003B24 41/ 8B 48 04 mov ecx, dword ptr [r8 + 4] \n"
" 00003B28 49/ 8B 48 04 mov rcx, qword ptr [r8 + 4] \n"
" \n"
" 00003B2C 44/ 88 41 FC mov byte ptr [rcx - 4], r8b \n"
" 00003B30 44/ 88 41 04 mov byte ptr [rcx + 4], r8b \n"
" 00003B34 66| 44/ 89 41 mov word ptr [rcx + 4], r8w \n"
" 04 \n"
" 00003B39 44/ 89 41 04 mov dword ptr [rcx + 4], r8d \n"
" 00003B3D 4C/ 89 41 04 mov qword ptr [rcx + 4], r8 \n"
" \n"
" 00003B41 66| 41/ 0F B6 C8 movzx cx, r8b \n"
" 00003B46 66| 41/ 0F B6 48 movzx cx, byte ptr [r8 + 4] \n"
" 04 \n"
" \n"
" 00003B4C 41/ 0F B6 C8 movzx ecx, r8b \n"
" 00003B50 41/ 0F B7 C8 movzx ecx, r8w \n"
" 00003B54 41/ 0F B6 48 movzx ecx, byte ptr [r8 + 4] \n"
" 04 \n"
" 00003B59 41/ 0F B7 48 movzx ecx, word ptr [r8 + 4] \n"
" 04 \n"
" \n"
" 00003B5E 49/ 0F B6 C8 movzx rcx, r8b \n"
" 00003B62 49/ 0F B7 C8 movzx rcx, r8w \n"
" 00003B66 49/ 0F B6 48 movzx rcx, byte ptr [r8 + 4] \n"
" 04 \n"
" 00003B6B 49/ 0F B7 48 movzx rcx, word ptr [r8 + 4] \n"
" 04 \n"
" \n"
" \n"
" ; Source: r8, target: rdx \n"
" 00003B70 B2 01 mov dl, 1 \n"
" 00003B72 66| BA 0001 mov dx, 1 \n"
" 00003B76 BA 00000001 mov edx, 1 \n"
" 00003B7B 48/ C7 C2 mov rdx, 1 \n"
" 00000001 \n"
" \n"
" 00003B82 41/ 8A D0 mov dl, r8b \n"
" 00003B85 66| 41/ 8B D0 mov dx, r8w \n"
" 00003B89 41/ 8B D0 mov edx, r8d \n"
" 00003B8C 49/ 8B D0 mov rdx, r8 \n"
" \n"
" 00003B8F 41/ 8A 50 FC mov dl, byte ptr [r8 - 4] \n"
" 00003B93 41/ 8A 50 04 mov dl, byte ptr [r8 + 4] \n"
" 00003B97 66| 41/ 8B 50 mov dx, word ptr [r8 + 4] \n"
" 04 \n"
" 00003B9C 41/ 8B 50 04 mov edx, dword ptr [r8 + 4] \n"
" 00003BA0 49/ 8B 50 04 mov rdx, qword ptr [r8 + 4] \n"
" \n"
" 00003BA4 44/ 88 42 FC mov byte ptr [rdx - 4], r8b \n"
" 00003BA8 44/ 88 42 04 mov byte ptr [rdx + 4], r8b \n"
" 00003BAC 66| 44/ 89 42 mov word ptr [rdx + 4], r8w \n"
" 04 \n"
" 00003BB1 44/ 89 42 04 mov dword ptr [rdx + 4], r8d \n"
" 00003BB5 4C/ 89 42 04 mov qword ptr [rdx + 4], r8 \n"
" \n"
" 00003BB9 66| 41/ 0F B6 D0 movzx dx, r8b \n"
" 00003BBE 66| 41/ 0F B6 50 movzx dx, byte ptr [r8 + 4] \n"
" 04 \n"
" \n"
" 00003BC4 41/ 0F B6 D0 movzx edx, r8b \n"
" 00003BC8 41/ 0F B7 D0 movzx edx, r8w \n"
" 00003BCC 41/ 0F B6 50 movzx edx, byte ptr [r8 + 4] \n"
" 04 \n"
" 00003BD1 41/ 0F B7 50 movzx edx, word ptr [r8 + 4] \n"
" 04 \n"
" \n"
" 00003BD6 49/ 0F B6 D0 movzx rdx, r8b \n"
" 00003BDA 49/ 0F B7 D0 movzx rdx, r8w \n"
" 00003BDE 49/ 0F B6 50 movzx rdx, byte ptr [r8 + 4] \n"
" 04 \n"
" 00003BE3 49/ 0F B7 50 movzx rdx, word ptr [r8 + 4] \n"
" 04 \n"
" \n"
" \n"
" ; Source: r8, target: rbx \n"
" 00003BE8 B3 01 mov bl, 1 \n"
" 00003BEA 66| BB 0001 mov bx, 1 \n"
" 00003BEE BB 00000001 mov ebx, 1 \n"
" 00003BF3 48/ C7 C3 mov rbx, 1 \n"
" 00000001 \n"
" \n"
" 00003BFA 41/ 8A D8 mov bl, r8b \n"
" 00003BFD 66| 41/ 8B D8 mov bx, r8w \n"
" 00003C01 41/ 8B D8 mov ebx, r8d \n"
" 00003C04 49/ 8B D8 mov rbx, r8 \n"
" \n"
" 00003C07 41/ 8A 58 FC mov bl, byte ptr [r8 - 4] \n"
" 00003C0B 41/ 8A 58 04 mov bl, byte ptr [r8 + 4] \n"
" 00003C0F 66| 41/ 8B 58 mov bx, word ptr [r8 + 4] \n"
" 04 \n"
" 00003C14 41/ 8B 58 04 mov ebx, dword ptr [r8 + 4] \n"
" 00003C18 49/ 8B 58 04 mov rbx, qword ptr [r8 + 4] \n"
" \n"
" 00003C1C 44/ 88 43 FC mov byte ptr [rbx - 4], r8b \n"
" 00003C20 44/ 88 43 04 mov byte ptr [rbx + 4], r8b \n"
" 00003C24 66| 44/ 89 43 mov word ptr [rbx + 4], r8w \n"
" 04 \n"
" 00003C29 44/ 89 43 04 mov dword ptr [rbx + 4], r8d \n"
" 00003C2D 4C/ 89 43 04 mov qword ptr [rbx + 4], r8 \n"
" \n"
" 00003C31 66| 41/ 0F B6 D8 movzx bx, r8b \n"
" 00003C36 66| 41/ 0F B6 58 movzx bx, byte ptr [r8 + 4] \n"
" 04 \n"
" \n"
" 00003C3C 41/ 0F B6 D8 movzx ebx, r8b \n"
" 00003C40 41/ 0F B7 D8 movzx ebx, r8w \n"
" 00003C44 41/ 0F B6 58 movzx ebx, byte ptr [r8 + 4] \n"
" 04 \n"
" 00003C49 41/ 0F B7 58 movzx ebx, word ptr [r8 + 4] \n"
" 04 \n"
" \n"
" 00003C4E 49/ 0F B6 D8 movzx rbx, r8b \n"
" 00003C52 49/ 0F B7 D8 movzx rbx, r8w \n"
" 00003C56 49/ 0F B6 58 movzx rbx, byte ptr [r8 + 4] \n"
" 04 \n"
" 00003C5B 49/ 0F B7 58 movzx rbx, word ptr [r8 + 4] \n"
" 04 \n"
" \n"
" \n"
" ; Source: r8, target: rsp \n"
" 00003C60 40/ B4 01 mov spl, 1 \n"
" 00003C63 66| BC 0001 mov sp, 1 \n"
" 00003C67 BC 00000001 mov esp, 1 \n"
" 00003C6C 48/ C7 C4 mov rsp, 1 \n"
" 00000001 \n"
" \n"
" 00003C73 41/ 8A E0 mov spl, r8b \n"
" 00003C76 66| 41/ 8B E0 mov sp, r8w \n"
" 00003C7A 41/ 8B E0 mov esp, r8d \n"
" 00003C7D 49/ 8B E0 mov rsp, r8 \n"
" \n"
" 00003C80 41/ 8A 60 FC mov spl, byte ptr [r8 - 4] \n"
" 00003C84 41/ 8A 60 04 mov spl, byte ptr [r8 + 4] \n"
" 00003C88 66| 41/ 8B 60 mov sp, word ptr [r8 + 4] \n"
" 04 \n"
" 00003C8D 41/ 8B 60 04 mov esp, dword ptr [r8 + 4] \n"
" 00003C91 49/ 8B 60 04 mov rsp, qword ptr [r8 + 4] \n"
" \n"
" 00003C95 44/ 88 44 24 mov byte ptr [rsp - 4], r8b \n"
" FC \n"
" 00003C9A 44/ 88 44 24 mov byte ptr [rsp + 4], r8b \n"
" 04 \n"
" 00003C9F 66| 44/ 89 44 24 mov word ptr [rsp + 4], r8w \n"
" 04 \n"
" 00003CA5 44/ 89 44 24 mov dword ptr [rsp + 4], r8d \n"
" 04 \n"
" 00003CAA 4C/ 89 44 24 mov qword ptr [rsp + 4], r8 \n"
" 04 \n"
" \n"
" 00003CAF 66| 41/ 0F B6 E0 movzx sp, r8b \n"
" 00003CB4 66| 41/ 0F B6 60 movzx sp, byte ptr [r8 + 4] \n"
" 04 \n"
" \n"
" 00003CBA 41/ 0F B6 E0 movzx esp, r8b \n"
" 00003CBE 41/ 0F B7 E0 movzx esp, r8w \n"
" 00003CC2 41/ 0F B6 60 movzx esp, byte ptr [r8 + 4] \n"
" 04 \n"
" 00003CC7 41/ 0F B7 60 movzx esp, word ptr [r8 + 4] \n"
" 04 \n"
" \n"
" 00003CCC 49/ 0F B6 E0 movzx rsp, r8b \n"
" 00003CD0 49/ 0F B7 E0 movzx rsp, r8w \n"
" 00003CD4 49/ 0F B6 60 movzx rsp, byte ptr [r8 + 4] \n"
" 04 \n"
" 00003CD9 49/ 0F B7 60 movzx rsp, word ptr [r8 + 4] \n"
" 04 \n"
" \n"
" \n"
" ; Source: r8, target: rbp \n"
" 00003CDE 40/ B5 01 mov bpl, 1 \n"
" 00003CE1 66| BD 0001 mov bp, 1 \n"
" 00003CE5 BD 00000001 mov ebp, 1 \n"
" 00003CEA 48/ C7 C5 mov rbp, 1 \n"
" 00000001 \n"
" \n"
" 00003CF1 41/ 8A E8 mov bpl, r8b \n"
" 00003CF4 66| 41/ 8B E8 mov bp, r8w \n"
" 00003CF8 41/ 8B E8 mov ebp, r8d \n"
" 00003CFB 49/ 8B E8 mov rbp, r8 \n"
" \n"
" 00003CFE 41/ 8A 68 FC mov bpl, byte ptr [r8 - 4] \n"
" 00003D02 41/ 8A 68 04 mov bpl, byte ptr [r8 + 4] \n"
" 00003D06 66| 41/ 8B 68 mov bp, word ptr [r8 + 4] \n"
" 04 \n"
" 00003D0B 41/ 8B 68 04 mov ebp, dword ptr [r8 + 4] \n"
" 00003D0F 49/ 8B 68 04 mov rbp, qword ptr [r8 + 4] \n"
" \n"
" 00003D13 44/ 88 45 FC mov byte ptr [rbp - 4], r8b \n"
" 00003D17 44/ 88 45 04 mov byte ptr [rbp + 4], r8b \n"
" 00003D1B 66| 44/ 89 45 mov word ptr [rbp + 4], r8w \n"
" 04 \n"
" 00003D20 44/ 89 45 04 mov dword ptr [rbp + 4], r8d \n"
" 00003D24 4C/ 89 45 04 mov qword ptr [rbp + 4], r8 \n"
" \n"
" 00003D28 66| 41/ 0F B6 E8 movzx bp, r8b \n"
" 00003D2D 66| 41/ 0F B6 68 movzx bp, byte ptr [r8 + 4] \n"
" 04 \n"
" \n"
" 00003D33 41/ 0F B6 E8 movzx ebp, r8b \n"
" 00003D37 41/ 0F B7 E8 movzx ebp, r8w \n"
" 00003D3B 41/ 0F B6 68 movzx ebp, byte ptr [r8 + 4] \n"
" 04 \n"
" 00003D40 41/ 0F B7 68 movzx ebp, word ptr [r8 + 4] \n"
" 04 \n"
" \n"
" 00003D45 49/ 0F B6 E8 movzx rbp, r8b \n"
" 00003D49 49/ 0F B7 E8 movzx rbp, r8w \n"
" 00003D4D 49/ 0F B6 68 movzx rbp, byte ptr [r8 + 4] \n"
" 04 \n"
" 00003D52 49/ 0F B7 68 movzx rbp, word ptr [r8 + 4] \n"
" 04 \n"
" \n"
" \n"
" ; Source: r8, target: rsi \n"
" 00003D57 40/ B7 01 mov dil, 1 \n"
" 00003D5A 66| BE 0001 mov si, 1 \n"
" 00003D5E BE 00000001 mov esi, 1 \n"
" 00003D63 48/ C7 C6 mov rsi, 1 \n"
" 00000001 \n"
" \n"
" 00003D6A 41/ 8A F8 mov dil, r8b \n"
" 00003D6D 66| 41/ 8B F0 mov si, r8w \n"
" 00003D71 41/ 8B F0 mov esi, r8d \n"
" 00003D74 49/ 8B F0 mov rsi, r8 \n"
" \n"
" 00003D77 41/ 8A 78 FC mov dil, byte ptr [r8 - 4] \n"
" 00003D7B 41/ 8A 78 04 mov dil, byte ptr [r8 + 4] \n"
" 00003D7F 66| 41/ 8B 70 mov si, word ptr [r8 + 4] \n"
" 04 \n"
" 00003D84 41/ 8B 70 04 mov esi, dword ptr [r8 + 4] \n"
" 00003D88 49/ 8B 70 04 mov rsi, qword ptr [r8 + 4] \n"
" \n"
" 00003D8C 44/ 88 46 FC mov byte ptr [rsi - 4], r8b \n"
" 00003D90 44/ 88 46 04 mov byte ptr [rsi + 4], r8b \n"
" 00003D94 66| 44/ 89 46 mov word ptr [rsi + 4], r8w \n";
ml64Output +=
" 04 \n"
" 00003D99 44/ 89 46 04 mov dword ptr [rsi + 4], r8d \n"
" 00003D9D 4C/ 89 46 04 mov qword ptr [rsi + 4], r8 \n"
" \n"
" 00003DA1 66| 41/ 0F B6 F0 movzx si, r8b \n"
" 00003DA6 66| 41/ 0F B6 70 movzx si, byte ptr [r8 + 4] \n"
" 04 \n"
" \n"
" 00003DAC 41/ 0F B6 F0 movzx esi, r8b \n"
" 00003DB0 41/ 0F B7 F0 movzx esi, r8w \n"
" 00003DB4 41/ 0F B6 70 movzx esi, byte ptr [r8 + 4] \n"
" 04 \n"
" 00003DB9 41/ 0F B7 70 movzx esi, word ptr [r8 + 4] \n"
" 04 \n"
" \n"
" 00003DBE 49/ 0F B6 F0 movzx rsi, r8b \n"
" 00003DC2 49/ 0F B7 F0 movzx rsi, r8w \n"
" 00003DC6 49/ 0F B6 70 movzx rsi, byte ptr [r8 + 4] \n"
" 04 \n"
" 00003DCB 49/ 0F B7 70 movzx rsi, word ptr [r8 + 4] \n"
" 04 \n"
" \n"
" \n"
" ; Source: r8, target: rdi \n"
" 00003DD0 40/ B6 01 mov sil, 1 \n"
" 00003DD3 66| BF 0001 mov di, 1 \n"
" 00003DD7 BF 00000001 mov edi, 1 \n"
" 00003DDC 48/ C7 C7 mov rdi, 1 \n"
" 00000001 \n"
" \n"
" 00003DE3 41/ 8A F0 mov sil, r8b \n"
" 00003DE6 66| 41/ 8B F8 mov di, r8w \n"
" 00003DEA 41/ 8B F8 mov edi, r8d \n"
" 00003DED 49/ 8B F8 mov rdi, r8 \n"
" \n"
" 00003DF0 41/ 8A 70 FC mov sil, byte ptr [r8 - 4] \n"
" 00003DF4 41/ 8A 70 04 mov sil, byte ptr [r8 + 4] \n"
" 00003DF8 66| 41/ 8B 78 mov di, word ptr [r8 + 4] \n"
" 04 \n"
" 00003DFD 41/ 8B 78 04 mov edi, dword ptr [r8 + 4] \n"
" 00003E01 49/ 8B 78 04 mov rdi, qword ptr [r8 + 4] \n"
" \n"
" 00003E05 44/ 88 47 FC mov byte ptr [rdi - 4], r8b \n"
" 00003E09 44/ 88 47 04 mov byte ptr [rdi + 4], r8b \n"
" 00003E0D 66| 44/ 89 47 mov word ptr [rdi + 4], r8w \n"
" 04 \n"
" 00003E12 44/ 89 47 04 mov dword ptr [rdi + 4], r8d \n"
" 00003E16 4C/ 89 47 04 mov qword ptr [rdi + 4], r8 \n"
" \n"
" 00003E1A 66| 41/ 0F B6 F8 movzx di, r8b \n"
" 00003E1F 66| 41/ 0F B6 78 movzx di, byte ptr [r8 + 4] \n"
" 04 \n"
" \n"
" 00003E25 41/ 0F B6 F8 movzx edi, r8b \n"
" 00003E29 41/ 0F B7 F8 movzx edi, r8w \n"
" 00003E2D 41/ 0F B6 78 movzx edi, byte ptr [r8 + 4] \n"
" 04 \n"
" 00003E32 41/ 0F B7 78 movzx edi, word ptr [r8 + 4] \n"
" 04 \n"
" \n"
" 00003E37 49/ 0F B6 F8 movzx rdi, r8b \n"
" 00003E3B 49/ 0F B7 F8 movzx rdi, r8w \n"
" 00003E3F 49/ 0F B6 78 movzx rdi, byte ptr [r8 + 4] \n"
" 04 \n"
" 00003E44 49/ 0F B7 78 movzx rdi, word ptr [r8 + 4] \n"
" 04 \n"
" \n"
" \n"
" ; Source: r8, target: r8 \n"
" 00003E49 41/ B0 01 mov r8b, 1 \n"
" 00003E4C 66| 41/ B8 mov r8w, 1 \n"
" 0001 \n"
" 00003E51 41/ B8 mov r8d, 1 \n"
" 00000001 \n"
" 00003E57 49/ C7 C0 mov r8, 1 \n"
" 00000001 \n"
" \n"
" 00003E5E 45/ 8A C0 mov r8b, r8b \n"
" 00003E61 66| 45/ 8B C0 mov r8w, r8w \n"
" 00003E65 45/ 8B C0 mov r8d, r8d \n"
" 00003E68 4D/ 8B C0 mov r8, r8 \n"
" \n"
" 00003E6B 45/ 8A 40 FC mov r8b, byte ptr [r8 - 4] \n"
" 00003E6F 45/ 8A 40 04 mov r8b, byte ptr [r8 + 4] \n"
" 00003E73 66| 45/ 8B 40 mov r8w, word ptr [r8 + 4] \n"
" 04 \n"
" 00003E78 45/ 8B 40 04 mov r8d, dword ptr [r8 + 4] \n"
" 00003E7C 4D/ 8B 40 04 mov r8, qword ptr [r8 + 4] \n"
" \n"
" 00003E80 45/ 88 40 FC mov byte ptr [r8 - 4], r8b \n"
" 00003E84 45/ 88 40 04 mov byte ptr [r8 + 4], r8b \n"
" 00003E88 66| 45/ 89 40 mov word ptr [r8 + 4], r8w \n"
" 04 \n"
" 00003E8D 45/ 89 40 04 mov dword ptr [r8 + 4], r8d \n"
" 00003E91 4D/ 89 40 04 mov qword ptr [r8 + 4], r8 \n"
" \n"
" 00003E95 66| 45/ 0F B6 C0 movzx r8w, r8b \n"
" 00003E9A 66| 45/ 0F B6 40 movzx r8w, byte ptr [r8 + 4] \n"
" 04 \n"
" \n"
" 00003EA0 45/ 0F B6 C0 movzx r8d, r8b \n"
" 00003EA4 45/ 0F B7 C0 movzx r8d, r8w \n"
" 00003EA8 45/ 0F B6 40 movzx r8d, byte ptr [r8 + 4] \n"
" 04 \n"
" 00003EAD 45/ 0F B7 40 movzx r8d, word ptr [r8 + 4] \n"
" 04 \n"
" \n"
" 00003EB2 4D/ 0F B6 C0 movzx r8, r8b \n"
" 00003EB6 4D/ 0F B7 C0 movzx r8, r8w \n"
" 00003EBA 4D/ 0F B6 40 movzx r8, byte ptr [r8 + 4] \n"
" 04 \n"
" 00003EBF 4D/ 0F B7 40 movzx r8, word ptr [r8 + 4] \n"
" 04 \n"
" \n"
" \n"
" ; Source: r8, target: r9 \n"
" 00003EC4 41/ B1 01 mov r9b, 1 \n"
" 00003EC7 66| 41/ B9 mov r9w, 1 \n"
" 0001 \n"
" 00003ECC 41/ B9 mov r9d, 1 \n"
" 00000001 \n"
" 00003ED2 49/ C7 C1 mov r9, 1 \n"
" 00000001 \n"
" \n"
" 00003ED9 45/ 8A C8 mov r9b, r8b \n"
" 00003EDC 66| 45/ 8B C8 mov r9w, r8w \n"
" 00003EE0 45/ 8B C8 mov r9d, r8d \n"
" 00003EE3 4D/ 8B C8 mov r9, r8 \n"
" \n"
" 00003EE6 45/ 8A 48 FC mov r9b, byte ptr [r8 - 4] \n"
" 00003EEA 45/ 8A 48 04 mov r9b, byte ptr [r8 + 4] \n"
" 00003EEE 66| 45/ 8B 48 mov r9w, word ptr [r8 + 4] \n"
" 04 \n"
" 00003EF3 45/ 8B 48 04 mov r9d, dword ptr [r8 + 4] \n"
" 00003EF7 4D/ 8B 48 04 mov r9, qword ptr [r8 + 4] \n"
" \n"
" 00003EFB 45/ 88 41 FC mov byte ptr [r9 - 4], r8b \n"
" 00003EFF 45/ 88 41 04 mov byte ptr [r9 + 4], r8b \n"
" 00003F03 66| 45/ 89 41 mov word ptr [r9 + 4], r8w \n"
" 04 \n"
" 00003F08 45/ 89 41 04 mov dword ptr [r9 + 4], r8d \n"
" 00003F0C 4D/ 89 41 04 mov qword ptr [r9 + 4], r8 \n"
" \n"
" 00003F10 66| 45/ 0F B6 C8 movzx r9w, r8b \n"
" 00003F15 66| 45/ 0F B6 48 movzx r9w, byte ptr [r8 + 4] \n"
" 04 \n"
" \n"
" 00003F1B 45/ 0F B6 C8 movzx r9d, r8b \n"
" 00003F1F 45/ 0F B7 C8 movzx r9d, r8w \n"
" 00003F23 45/ 0F B6 48 movzx r9d, byte ptr [r8 + 4] \n"
" 04 \n"
" 00003F28 45/ 0F B7 48 movzx r9d, word ptr [r8 + 4] \n"
" 04 \n"
" \n"
" 00003F2D 4D/ 0F B6 C8 movzx r9, r8b \n"
" 00003F31 4D/ 0F B7 C8 movzx r9, r8w \n"
" 00003F35 4D/ 0F B6 48 movzx r9, byte ptr [r8 + 4] \n"
" 04 \n"
" 00003F3A 4D/ 0F B7 48 movzx r9, word ptr [r8 + 4] \n"
" 04 \n"
" \n"
" \n"
" ; Source: r8, target: r10 \n"
" 00003F3F 41/ B2 01 mov r10b, 1 \n"
" 00003F42 66| 41/ BA mov r10w, 1 \n"
" 0001 \n"
" 00003F47 41/ BA mov r10d, 1 \n"
" 00000001 \n"
" 00003F4D 49/ C7 C2 mov r10, 1 \n"
" 00000001 \n"
" \n"
" 00003F54 45/ 8A D0 mov r10b, r8b \n"
" 00003F57 66| 45/ 8B D0 mov r10w, r8w \n"
" 00003F5B 45/ 8B D0 mov r10d, r8d \n"
" 00003F5E 4D/ 8B D0 mov r10, r8 \n"
" \n"
" 00003F61 45/ 8A 50 FC mov r10b, byte ptr [r8 - 4] \n"
" 00003F65 45/ 8A 50 04 mov r10b, byte ptr [r8 + 4] \n"
" 00003F69 66| 45/ 8B 50 mov r10w, word ptr [r8 + 4] \n"
" 04 \n"
" 00003F6E 45/ 8B 50 04 mov r10d, dword ptr [r8 + 4] \n"
" 00003F72 4D/ 8B 50 04 mov r10, qword ptr [r8 + 4] \n"
" \n"
" 00003F76 45/ 88 42 FC mov byte ptr [r10 - 4], r8b \n"
" 00003F7A 45/ 88 42 04 mov byte ptr [r10 + 4], r8b \n"
" 00003F7E 66| 45/ 89 42 mov word ptr [r10 + 4], r8w \n"
" 04 \n"
" 00003F83 45/ 89 42 04 mov dword ptr [r10 + 4], r8d \n"
" 00003F87 4D/ 89 42 04 mov qword ptr [r10 + 4], r8 \n"
" \n"
" 00003F8B 66| 45/ 0F B6 D0 movzx r10w, r8b \n"
" 00003F90 66| 45/ 0F B6 50 movzx r10w, byte ptr [r8 + 4] \n"
" 04 \n"
" \n"
" 00003F96 45/ 0F B6 D0 movzx r10d, r8b \n"
" 00003F9A 45/ 0F B7 D0 movzx r10d, r8w \n"
" 00003F9E 45/ 0F B6 50 movzx r10d, byte ptr [r8 + 4] \n"
" 04 \n"
" 00003FA3 45/ 0F B7 50 movzx r10d, word ptr [r8 + 4] \n"
" 04 \n"
" \n"
" 00003FA8 4D/ 0F B6 D0 movzx r10, r8b \n"
" 00003FAC 4D/ 0F B7 D0 movzx r10, r8w \n"
" 00003FB0 4D/ 0F B6 50 movzx r10, byte ptr [r8 + 4] \n"
" 04 \n"
" 00003FB5 4D/ 0F B7 50 movzx r10, word ptr [r8 + 4] \n"
" 04 \n"
" \n"
" \n"
" ; Source: r8, target: r11 \n"
" 00003FBA 41/ B3 01 mov r11b, 1 \n"
" 00003FBD 66| 41/ BB mov r11w, 1 \n"
" 0001 \n"
" 00003FC2 41/ BB mov r11d, 1 \n"
" 00000001 \n"
" 00003FC8 49/ C7 C3 mov r11, 1 \n"
" 00000001 \n"
" \n"
" 00003FCF 45/ 8A D8 mov r11b, r8b \n"
" 00003FD2 66| 45/ 8B D8 mov r11w, r8w \n"
" 00003FD6 45/ 8B D8 mov r11d, r8d \n"
" 00003FD9 4D/ 8B D8 mov r11, r8 \n"
" \n"
" 00003FDC 45/ 8A 58 FC mov r11b, byte ptr [r8 - 4] \n"
" 00003FE0 45/ 8A 58 04 mov r11b, byte ptr [r8 + 4] \n"
" 00003FE4 66| 45/ 8B 58 mov r11w, word ptr [r8 + 4] \n"
" 04 \n"
" 00003FE9 45/ 8B 58 04 mov r11d, dword ptr [r8 + 4] \n"
" 00003FED 4D/ 8B 58 04 mov r11, qword ptr [r8 + 4] \n"
" \n"
" 00003FF1 45/ 88 43 FC mov byte ptr [r11 - 4], r8b \n"
" 00003FF5 45/ 88 43 04 mov byte ptr [r11 + 4], r8b \n"
" 00003FF9 66| 45/ 89 43 mov word ptr [r11 + 4], r8w \n"
" 04 \n"
" 00003FFE 45/ 89 43 04 mov dword ptr [r11 + 4], r8d \n"
" 00004002 4D/ 89 43 04 mov qword ptr [r11 + 4], r8 \n"
" \n"
" 00004006 66| 45/ 0F B6 D8 movzx r11w, r8b \n"
" 0000400B 66| 45/ 0F B6 58 movzx r11w, byte ptr [r8 + 4] \n"
" 04 \n"
" \n"
" 00004011 45/ 0F B6 D8 movzx r11d, r8b \n"
" 00004015 45/ 0F B7 D8 movzx r11d, r8w \n"
" 00004019 45/ 0F B6 58 movzx r11d, byte ptr [r8 + 4] \n"
" 04 \n"
" 0000401E 45/ 0F B7 58 movzx r11d, word ptr [r8 + 4] \n"
" 04 \n"
" \n"
" 00004023 4D/ 0F B6 D8 movzx r11, r8b \n"
" 00004027 4D/ 0F B7 D8 movzx r11, r8w \n"
" 0000402B 4D/ 0F B6 58 movzx r11, byte ptr [r8 + 4] \n"
" 04 \n"
" 00004030 4D/ 0F B7 58 movzx r11, word ptr [r8 + 4] \n"
" 04 \n"
" \n"
" \n"
" ; Source: r8, target: r12 \n"
" 00004035 41/ B4 01 mov r12b, 1 \n"
" 00004038 66| 41/ BC mov r12w, 1 \n"
" 0001 \n"
" 0000403D 41/ BC mov r12d, 1 \n"
" 00000001 \n"
" 00004043 49/ C7 C4 mov r12, 1 \n"
" 00000001 \n"
" \n"
" 0000404A 45/ 8A E0 mov r12b, r8b \n"
" 0000404D 66| 45/ 8B E0 mov r12w, r8w \n"
" 00004051 45/ 8B E0 mov r12d, r8d \n"
" 00004054 4D/ 8B E0 mov r12, r8 \n"
" \n"
" 00004057 45/ 8A 60 FC mov r12b, byte ptr [r8 - 4] \n"
" 0000405B 45/ 8A 60 04 mov r12b, byte ptr [r8 + 4] \n"
" 0000405F 66| 45/ 8B 60 mov r12w, word ptr [r8 + 4] \n"
" 04 \n"
" 00004064 45/ 8B 60 04 mov r12d, dword ptr [r8 + 4] \n"
" 00004068 4D/ 8B 60 04 mov r12, qword ptr [r8 + 4] \n"
" \n"
" 0000406C 45/ 88 44 24 mov byte ptr [r12 - 4], r8b \n"
" FC \n"
" 00004071 45/ 88 44 24 mov byte ptr [r12 + 4], r8b \n"
" 04 \n"
" 00004076 66| 45/ 89 44 24 mov word ptr [r12 + 4], r8w \n"
" 04 \n"
" 0000407C 45/ 89 44 24 mov dword ptr [r12 + 4], r8d \n"
" 04 \n"
" 00004081 4D/ 89 44 24 mov qword ptr [r12 + 4], r8 \n"
" 04 \n"
" \n"
" 00004086 66| 45/ 0F B6 E0 movzx r12w, r8b \n"
" 0000408B 66| 45/ 0F B6 60 movzx r12w, byte ptr [r8 + 4] \n"
" 04 \n"
" \n"
" 00004091 45/ 0F B6 E0 movzx r12d, r8b \n"
" 00004095 45/ 0F B7 E0 movzx r12d, r8w \n"
" 00004099 45/ 0F B6 60 movzx r12d, byte ptr [r8 + 4] \n"
" 04 \n"
" 0000409E 45/ 0F B7 60 movzx r12d, word ptr [r8 + 4] \n"
" 04 \n"
" \n"
" 000040A3 4D/ 0F B6 E0 movzx r12, r8b \n"
" 000040A7 4D/ 0F B7 E0 movzx r12, r8w \n"
" 000040AB 4D/ 0F B6 60 movzx r12, byte ptr [r8 + 4] \n"
" 04 \n"
" 000040B0 4D/ 0F B7 60 movzx r12, word ptr [r8 + 4] \n"
" 04 \n"
" \n"
" \n"
" ; Source: r8, target: r13 \n"
" 000040B5 41/ B5 01 mov r13b, 1 \n"
" 000040B8 66| 41/ BD mov r13w, 1 \n"
" 0001 \n"
" 000040BD 41/ BD mov r13d, 1 \n"
" 00000001 \n"
" 000040C3 49/ C7 C5 mov r13, 1 \n"
" 00000001 \n"
" \n"
" 000040CA 45/ 8A E8 mov r13b, r8b \n"
" 000040CD 66| 45/ 8B E8 mov r13w, r8w \n"
" 000040D1 45/ 8B E8 mov r13d, r8d \n"
" 000040D4 4D/ 8B E8 mov r13, r8 \n"
" \n"
" 000040D7 45/ 8A 68 FC mov r13b, byte ptr [r8 - 4] \n"
" 000040DB 45/ 8A 68 04 mov r13b, byte ptr [r8 + 4] \n"
" 000040DF 66| 45/ 8B 68 mov r13w, word ptr [r8 + 4] \n"
" 04 \n"
" 000040E4 45/ 8B 68 04 mov r13d, dword ptr [r8 + 4] \n"
" 000040E8 4D/ 8B 68 04 mov r13, qword ptr [r8 + 4] \n"
" \n"
" 000040EC 45/ 88 45 FC mov byte ptr [r13 - 4], r8b \n"
" 000040F0 45/ 88 45 04 mov byte ptr [r13 + 4], r8b \n"
" 000040F4 66| 45/ 89 45 mov word ptr [r13 + 4], r8w \n"
" 04 \n"
" 000040F9 45/ 89 45 04 mov dword ptr [r13 + 4], r8d \n"
" 000040FD 4D/ 89 45 04 mov qword ptr [r13 + 4], r8 \n"
" \n"
" 00004101 66| 45/ 0F B6 E8 movzx r13w, r8b \n"
" 00004106 66| 45/ 0F B6 68 movzx r13w, byte ptr [r8 + 4] \n"
" 04 \n"
" \n"
" 0000410C 45/ 0F B6 E8 movzx r13d, r8b \n"
" 00004110 45/ 0F B7 E8 movzx r13d, r8w \n"
" 00004114 45/ 0F B6 68 movzx r13d, byte ptr [r8 + 4] \n"
" 04 \n"
" 00004119 45/ 0F B7 68 movzx r13d, word ptr [r8 + 4] \n"
" 04 \n"
" \n"
" 0000411E 4D/ 0F B6 E8 movzx r13, r8b \n"
" 00004122 4D/ 0F B7 E8 movzx r13, r8w \n"
" 00004126 4D/ 0F B6 68 movzx r13, byte ptr [r8 + 4] \n"
" 04 \n"
" 0000412B 4D/ 0F B7 68 movzx r13, word ptr [r8 + 4] \n"
" 04 \n"
" \n"
" \n"
" ; Source: r8, target: r14 \n"
" 00004130 41/ B6 01 mov r14b, 1 \n"
" 00004133 66| 41/ BE mov r14w, 1 \n"
" 0001 \n"
" 00004138 41/ BE mov r14d, 1 \n"
" 00000001 \n"
" 0000413E 49/ C7 C6 mov r14, 1 \n"
" 00000001 \n"
" \n"
" 00004145 45/ 8A F0 mov r14b, r8b \n"
" 00004148 66| 45/ 8B F0 mov r14w, r8w \n"
" 0000414C 45/ 8B F0 mov r14d, r8d \n"
" 0000414F 4D/ 8B F0 mov r14, r8 \n"
" \n"
" 00004152 45/ 8A 70 FC mov r14b, byte ptr [r8 - 4] \n"
" 00004156 45/ 8A 70 04 mov r14b, byte ptr [r8 + 4] \n"
" 0000415A 66| 45/ 8B 70 mov r14w, word ptr [r8 + 4] \n"
" 04 \n"
" 0000415F 45/ 8B 70 04 mov r14d, dword ptr [r8 + 4] \n"
" 00004163 4D/ 8B 70 04 mov r14, qword ptr [r8 + 4] \n"
" \n"
" 00004167 45/ 88 46 FC mov byte ptr [r14 - 4], r8b \n"
" 0000416B 45/ 88 46 04 mov byte ptr [r14 + 4], r8b \n"
" 0000416F 66| 45/ 89 46 mov word ptr [r14 + 4], r8w \n"
" 04 \n"
" 00004174 45/ 89 46 04 mov dword ptr [r14 + 4], r8d \n"
" 00004178 4D/ 89 46 04 mov qword ptr [r14 + 4], r8 \n"
" \n"
" 0000417C 66| 45/ 0F B6 F0 movzx r14w, r8b \n"
" 00004181 66| 45/ 0F B6 70 movzx r14w, byte ptr [r8 + 4] \n"
" 04 \n"
" \n"
" 00004187 45/ 0F B6 F0 movzx r14d, r8b \n"
" 0000418B 45/ 0F B7 F0 movzx r14d, r8w \n"
" 0000418F 45/ 0F B6 70 movzx r14d, byte ptr [r8 + 4] \n"
" 04 \n"
" 00004194 45/ 0F B7 70 movzx r14d, word ptr [r8 + 4] \n"
" 04 \n"
" \n"
" 00004199 4D/ 0F B6 F0 movzx r14, r8b \n"
" 0000419D 4D/ 0F B7 F0 movzx r14, r8w \n"
" 000041A1 4D/ 0F B6 70 movzx r14, byte ptr [r8 + 4] \n"
" 04 \n"
" 000041A6 4D/ 0F B7 70 movzx r14, word ptr [r8 + 4] \n"
" 04 \n"
" \n"
" \n"
" ; Source: r8, target: r15 \n"
" 000041AB 41/ B7 01 mov r15b, 1 \n"
" 000041AE 66| 41/ BF mov r15w, 1 \n"
" 0001 \n"
" 000041B3 41/ BF mov r15d, 1 \n"
" 00000001 \n"
" 000041B9 49/ C7 C7 mov r15, 1 \n"
" 00000001 \n"
" \n"
" 000041C0 45/ 8A F8 mov r15b, r8b \n"
" 000041C3 66| 45/ 8B F8 mov r15w, r8w \n"
" 000041C7 45/ 8B F8 mov r15d, r8d \n"
" 000041CA 4D/ 8B F8 mov r15, r8 \n"
" \n"
" 000041CD 45/ 8A 78 FC mov r15b, byte ptr [r8 - 4] \n"
" 000041D1 45/ 8A 78 04 mov r15b, byte ptr [r8 + 4] \n"
" 000041D5 66| 45/ 8B 78 mov r15w, word ptr [r8 + 4] \n"
" 04 \n"
" 000041DA 45/ 8B 78 04 mov r15d, dword ptr [r8 + 4] \n"
" 000041DE 4D/ 8B 78 04 mov r15, qword ptr [r8 + 4] \n"
" \n"
" 000041E2 45/ 88 47 FC mov byte ptr [r15 - 4], r8b \n"
" 000041E6 45/ 88 47 04 mov byte ptr [r15 + 4], r8b \n"
" 000041EA 66| 45/ 89 47 mov word ptr [r15 + 4], r8w \n"
" 04 \n"
" 000041EF 45/ 89 47 04 mov dword ptr [r15 + 4], r8d \n"
" 000041F3 4D/ 89 47 04 mov qword ptr [r15 + 4], r8 \n"
" \n"
" 000041F7 66| 45/ 0F B6 F8 movzx r15w, r8b \n"
" 000041FC 66| 45/ 0F B6 78 movzx r15w, byte ptr [r8 + 4] \n"
" 04 \n"
" \n"
" 00004202 45/ 0F B6 F8 movzx r15d, r8b \n"
" 00004206 45/ 0F B7 F8 movzx r15d, r8w \n"
" 0000420A 45/ 0F B6 78 movzx r15d, byte ptr [r8 + 4] \n"
" 04 \n"
" 0000420F 45/ 0F B7 78 movzx r15d, word ptr [r8 + 4] \n"
" 04 \n"
" \n"
" 00004214 4D/ 0F B6 F8 movzx r15, r8b \n"
" 00004218 4D/ 0F B7 F8 movzx r15, r8w \n"
" 0000421C 4D/ 0F B6 78 movzx r15, byte ptr [r8 + 4] \n"
" 04 \n"
" 00004221 4D/ 0F B7 78 movzx r15, word ptr [r8 + 4] \n"
" 04 \n"
" \n"
" \n"
" ; Source: r9, target: rax \n"
" 00004226 B0 01 mov al, 1 \n"
" 00004228 66| B8 0001 mov ax, 1 \n"
" 0000422C B8 00000001 mov eax, 1 \n"
" 00004231 48/ C7 C0 mov rax, 1 \n"
" 00000001 \n"
" \n"
" 00004238 41/ 8A C1 mov al, r9b \n"
" 0000423B 66| 41/ 8B C1 mov ax, r9w \n"
" 0000423F 41/ 8B C1 mov eax, r9d \n"
" 00004242 49/ 8B C1 mov rax, r9 \n"
" \n"
" 00004245 41/ 8A 41 FC mov al, byte ptr [r9 - 4] \n"
" 00004249 41/ 8A 41 04 mov al, byte ptr [r9 + 4] \n"
" 0000424D 66| 41/ 8B 41 mov ax, word ptr [r9 + 4] \n"
" 04 \n"
" 00004252 41/ 8B 41 04 mov eax, dword ptr [r9 + 4] \n"
" 00004256 49/ 8B 41 04 mov rax, qword ptr [r9 + 4] \n"
" \n"
" 0000425A 44/ 88 48 FC mov byte ptr [rax - 4], r9b \n"
" 0000425E 44/ 88 48 04 mov byte ptr [rax + 4], r9b \n"
" 00004262 66| 44/ 89 48 mov word ptr [rax + 4], r9w \n"
" 04 \n"
" 00004267 44/ 89 48 04 mov dword ptr [rax + 4], r9d \n"
" 0000426B 4C/ 89 48 04 mov qword ptr [rax + 4], r9 \n"
" \n"
" 0000426F 66| 41/ 0F B6 C1 movzx ax, r9b \n"
" 00004274 66| 41/ 0F B6 41 movzx ax, byte ptr [r9 + 4] \n"
" 04 \n"
" \n"
" 0000427A 41/ 0F B6 C1 movzx eax, r9b \n"
" 0000427E 41/ 0F B7 C1 movzx eax, r9w \n"
" 00004282 41/ 0F B6 41 movzx eax, byte ptr [r9 + 4] \n"
" 04 \n"
" 00004287 41/ 0F B7 41 movzx eax, word ptr [r9 + 4] \n"
" 04 \n"
" \n"
" 0000428C 49/ 0F B6 C1 movzx rax, r9b \n"
" 00004290 49/ 0F B7 C1 movzx rax, r9w \n"
" 00004294 49/ 0F B6 41 movzx rax, byte ptr [r9 + 4] \n"
" 04 \n"
" 00004299 49/ 0F B7 41 movzx rax, word ptr [r9 + 4] \n"
" 04 \n"
" \n"
" \n"
" ; Source: r9, target: rcx \n"
" 0000429E B1 01 mov cl, 1 \n"
" 000042A0 66| B9 0001 mov cx, 1 \n"
" 000042A4 B9 00000001 mov ecx, 1 \n"
" 000042A9 48/ C7 C1 mov rcx, 1 \n"
" 00000001 \n"
" \n"
" 000042B0 41/ 8A C9 mov cl, r9b \n"
" 000042B3 66| 41/ 8B C9 mov cx, r9w \n"
" 000042B7 41/ 8B C9 mov ecx, r9d \n"
" 000042BA 49/ 8B C9 mov rcx, r9 \n"
" \n"
" 000042BD 41/ 8A 49 FC mov cl, byte ptr [r9 - 4] \n"
" 000042C1 41/ 8A 49 04 mov cl, byte ptr [r9 + 4] \n"
" 000042C5 66| 41/ 8B 49 mov cx, word ptr [r9 + 4] \n"
" 04 \n"
" 000042CA 41/ 8B 49 04 mov ecx, dword ptr [r9 + 4] \n"
" 000042CE 49/ 8B 49 04 mov rcx, qword ptr [r9 + 4] \n"
" \n"
" 000042D2 44/ 88 49 FC mov byte ptr [rcx - 4], r9b \n"
" 000042D6 44/ 88 49 04 mov byte ptr [rcx + 4], r9b \n"
" 000042DA 66| 44/ 89 49 mov word ptr [rcx + 4], r9w \n"
" 04 \n"
" 000042DF 44/ 89 49 04 mov dword ptr [rcx + 4], r9d \n"
" 000042E3 4C/ 89 49 04 mov qword ptr [rcx + 4], r9 \n"
" \n"
" 000042E7 66| 41/ 0F B6 C9 movzx cx, r9b \n"
" 000042EC 66| 41/ 0F B6 49 movzx cx, byte ptr [r9 + 4] \n"
" 04 \n"
" \n"
" 000042F2 41/ 0F B6 C9 movzx ecx, r9b \n"
" 000042F6 41/ 0F B7 C9 movzx ecx, r9w \n"
" 000042FA 41/ 0F B6 49 movzx ecx, byte ptr [r9 + 4] \n"
" 04 \n"
" 000042FF 41/ 0F B7 49 movzx ecx, word ptr [r9 + 4] \n"
" 04 \n"
" \n"
" 00004304 49/ 0F B6 C9 movzx rcx, r9b \n"
" 00004308 49/ 0F B7 C9 movzx rcx, r9w \n"
" 0000430C 49/ 0F B6 49 movzx rcx, byte ptr [r9 + 4] \n"
" 04 \n"
" 00004311 49/ 0F B7 49 movzx rcx, word ptr [r9 + 4] \n"
" 04 \n"
" \n"
" \n"
" ; Source: r9, target: rdx \n"
" 00004316 B2 01 mov dl, 1 \n"
" 00004318 66| BA 0001 mov dx, 1 \n"
" 0000431C BA 00000001 mov edx, 1 \n"
" 00004321 48/ C7 C2 mov rdx, 1 \n"
" 00000001 \n"
" \n"
" 00004328 41/ 8A D1 mov dl, r9b \n"
" 0000432B 66| 41/ 8B D1 mov dx, r9w \n"
" 0000432F 41/ 8B D1 mov edx, r9d \n"
" 00004332 49/ 8B D1 mov rdx, r9 \n"
" \n";
ml64Output +=
" 00004335 41/ 8A 51 FC mov dl, byte ptr [r9 - 4] \n"
" 00004339 41/ 8A 51 04 mov dl, byte ptr [r9 + 4] \n"
" 0000433D 66| 41/ 8B 51 mov dx, word ptr [r9 + 4] \n"
" 04 \n"
" 00004342 41/ 8B 51 04 mov edx, dword ptr [r9 + 4] \n"
" 00004346 49/ 8B 51 04 mov rdx, qword ptr [r9 + 4] \n"
" \n"
" 0000434A 44/ 88 4A FC mov byte ptr [rdx - 4], r9b \n"
" 0000434E 44/ 88 4A 04 mov byte ptr [rdx + 4], r9b \n"
" 00004352 66| 44/ 89 4A mov word ptr [rdx + 4], r9w \n"
" 04 \n"
" 00004357 44/ 89 4A 04 mov dword ptr [rdx + 4], r9d \n"
" 0000435B 4C/ 89 4A 04 mov qword ptr [rdx + 4], r9 \n"
" \n"
" 0000435F 66| 41/ 0F B6 D1 movzx dx, r9b \n"
" 00004364 66| 41/ 0F B6 51 movzx dx, byte ptr [r9 + 4] \n"
" 04 \n"
" \n"
" 0000436A 41/ 0F B6 D1 movzx edx, r9b \n"
" 0000436E 41/ 0F B7 D1 movzx edx, r9w \n"
" 00004372 41/ 0F B6 51 movzx edx, byte ptr [r9 + 4] \n"
" 04 \n"
" 00004377 41/ 0F B7 51 movzx edx, word ptr [r9 + 4] \n"
" 04 \n"
" \n"
" 0000437C 49/ 0F B6 D1 movzx rdx, r9b \n"
" 00004380 49/ 0F B7 D1 movzx rdx, r9w \n"
" 00004384 49/ 0F B6 51 movzx rdx, byte ptr [r9 + 4] \n"
" 04 \n"
" 00004389 49/ 0F B7 51 movzx rdx, word ptr [r9 + 4] \n"
" 04 \n"
" \n"
" \n"
" ; Source: r9, target: rbx \n"
" 0000438E B3 01 mov bl, 1 \n"
" 00004390 66| BB 0001 mov bx, 1 \n"
" 00004394 BB 00000001 mov ebx, 1 \n"
" 00004399 48/ C7 C3 mov rbx, 1 \n"
" 00000001 \n"
" \n"
" 000043A0 41/ 8A D9 mov bl, r9b \n"
" 000043A3 66| 41/ 8B D9 mov bx, r9w \n"
" 000043A7 41/ 8B D9 mov ebx, r9d \n"
" 000043AA 49/ 8B D9 mov rbx, r9 \n"
" \n"
" 000043AD 41/ 8A 59 FC mov bl, byte ptr [r9 - 4] \n"
" 000043B1 41/ 8A 59 04 mov bl, byte ptr [r9 + 4] \n"
" 000043B5 66| 41/ 8B 59 mov bx, word ptr [r9 + 4] \n"
" 04 \n"
" 000043BA 41/ 8B 59 04 mov ebx, dword ptr [r9 + 4] \n"
" 000043BE 49/ 8B 59 04 mov rbx, qword ptr [r9 + 4] \n"
" \n"
" 000043C2 44/ 88 4B FC mov byte ptr [rbx - 4], r9b \n"
" 000043C6 44/ 88 4B 04 mov byte ptr [rbx + 4], r9b \n"
" 000043CA 66| 44/ 89 4B mov word ptr [rbx + 4], r9w \n"
" 04 \n"
" 000043CF 44/ 89 4B 04 mov dword ptr [rbx + 4], r9d \n"
" 000043D3 4C/ 89 4B 04 mov qword ptr [rbx + 4], r9 \n"
" \n"
" 000043D7 66| 41/ 0F B6 D9 movzx bx, r9b \n"
" 000043DC 66| 41/ 0F B6 59 movzx bx, byte ptr [r9 + 4] \n"
" 04 \n"
" \n"
" 000043E2 41/ 0F B6 D9 movzx ebx, r9b \n"
" 000043E6 41/ 0F B7 D9 movzx ebx, r9w \n"
" 000043EA 41/ 0F B6 59 movzx ebx, byte ptr [r9 + 4] \n"
" 04 \n"
" 000043EF 41/ 0F B7 59 movzx ebx, word ptr [r9 + 4] \n"
" 04 \n"
" \n"
" 000043F4 49/ 0F B6 D9 movzx rbx, r9b \n"
" 000043F8 49/ 0F B7 D9 movzx rbx, r9w \n"
" 000043FC 49/ 0F B6 59 movzx rbx, byte ptr [r9 + 4] \n"
" 04 \n"
" 00004401 49/ 0F B7 59 movzx rbx, word ptr [r9 + 4] \n"
" 04 \n"
" \n"
" \n"
" ; Source: r9, target: rsp \n"
" 00004406 40/ B4 01 mov spl, 1 \n"
" 00004409 66| BC 0001 mov sp, 1 \n"
" 0000440D BC 00000001 mov esp, 1 \n"
" 00004412 48/ C7 C4 mov rsp, 1 \n"
" 00000001 \n"
" \n"
" 00004419 41/ 8A E1 mov spl, r9b \n"
" 0000441C 66| 41/ 8B E1 mov sp, r9w \n"
" 00004420 41/ 8B E1 mov esp, r9d \n"
" 00004423 49/ 8B E1 mov rsp, r9 \n"
" \n"
" 00004426 41/ 8A 61 FC mov spl, byte ptr [r9 - 4] \n"
" 0000442A 41/ 8A 61 04 mov spl, byte ptr [r9 + 4] \n"
" 0000442E 66| 41/ 8B 61 mov sp, word ptr [r9 + 4] \n"
" 04 \n"
" 00004433 41/ 8B 61 04 mov esp, dword ptr [r9 + 4] \n"
" 00004437 49/ 8B 61 04 mov rsp, qword ptr [r9 + 4] \n"
" \n"
" 0000443B 44/ 88 4C 24 mov byte ptr [rsp - 4], r9b \n"
" FC \n"
" 00004440 44/ 88 4C 24 mov byte ptr [rsp + 4], r9b \n"
" 04 \n"
" 00004445 66| 44/ 89 4C 24 mov word ptr [rsp + 4], r9w \n"
" 04 \n"
" 0000444B 44/ 89 4C 24 mov dword ptr [rsp + 4], r9d \n"
" 04 \n"
" 00004450 4C/ 89 4C 24 mov qword ptr [rsp + 4], r9 \n"
" 04 \n"
" \n"
" 00004455 66| 41/ 0F B6 E1 movzx sp, r9b \n"
" 0000445A 66| 41/ 0F B6 61 movzx sp, byte ptr [r9 + 4] \n"
" 04 \n"
" \n"
" 00004460 41/ 0F B6 E1 movzx esp, r9b \n"
" 00004464 41/ 0F B7 E1 movzx esp, r9w \n"
" 00004468 41/ 0F B6 61 movzx esp, byte ptr [r9 + 4] \n"
" 04 \n"
" 0000446D 41/ 0F B7 61 movzx esp, word ptr [r9 + 4] \n"
" 04 \n"
" \n"
" 00004472 49/ 0F B6 E1 movzx rsp, r9b \n"
" 00004476 49/ 0F B7 E1 movzx rsp, r9w \n"
" 0000447A 49/ 0F B6 61 movzx rsp, byte ptr [r9 + 4] \n"
" 04 \n"
" 0000447F 49/ 0F B7 61 movzx rsp, word ptr [r9 + 4] \n"
" 04 \n"
" \n"
" \n"
" ; Source: r9, target: rbp \n"
" 00004484 40/ B5 01 mov bpl, 1 \n"
" 00004487 66| BD 0001 mov bp, 1 \n"
" 0000448B BD 00000001 mov ebp, 1 \n"
" 00004490 48/ C7 C5 mov rbp, 1 \n"
" 00000001 \n"
" \n"
" 00004497 41/ 8A E9 mov bpl, r9b \n"
" 0000449A 66| 41/ 8B E9 mov bp, r9w \n"
" 0000449E 41/ 8B E9 mov ebp, r9d \n"
" 000044A1 49/ 8B E9 mov rbp, r9 \n"
" \n"
" 000044A4 41/ 8A 69 FC mov bpl, byte ptr [r9 - 4] \n"
" 000044A8 41/ 8A 69 04 mov bpl, byte ptr [r9 + 4] \n"
" 000044AC 66| 41/ 8B 69 mov bp, word ptr [r9 + 4] \n"
" 04 \n"
" 000044B1 41/ 8B 69 04 mov ebp, dword ptr [r9 + 4] \n"
" 000044B5 49/ 8B 69 04 mov rbp, qword ptr [r9 + 4] \n"
" \n"
" 000044B9 44/ 88 4D FC mov byte ptr [rbp - 4], r9b \n"
" 000044BD 44/ 88 4D 04 mov byte ptr [rbp + 4], r9b \n"
" 000044C1 66| 44/ 89 4D mov word ptr [rbp + 4], r9w \n"
" 04 \n"
" 000044C6 44/ 89 4D 04 mov dword ptr [rbp + 4], r9d \n"
" 000044CA 4C/ 89 4D 04 mov qword ptr [rbp + 4], r9 \n"
" \n"
" 000044CE 66| 41/ 0F B6 E9 movzx bp, r9b \n"
" 000044D3 66| 41/ 0F B6 69 movzx bp, byte ptr [r9 + 4] \n"
" 04 \n"
" \n"
" 000044D9 41/ 0F B6 E9 movzx ebp, r9b \n"
" 000044DD 41/ 0F B7 E9 movzx ebp, r9w \n"
" 000044E1 41/ 0F B6 69 movzx ebp, byte ptr [r9 + 4] \n"
" 04 \n"
" 000044E6 41/ 0F B7 69 movzx ebp, word ptr [r9 + 4] \n"
" 04 \n"
" \n"
" 000044EB 49/ 0F B6 E9 movzx rbp, r9b \n"
" 000044EF 49/ 0F B7 E9 movzx rbp, r9w \n"
" 000044F3 49/ 0F B6 69 movzx rbp, byte ptr [r9 + 4] \n"
" 04 \n"
" 000044F8 49/ 0F B7 69 movzx rbp, word ptr [r9 + 4] \n"
" 04 \n"
" \n"
" \n"
" ; Source: r9, target: rsi \n"
" 000044FD 40/ B7 01 mov dil, 1 \n"
" 00004500 66| BE 0001 mov si, 1 \n"
" 00004504 BE 00000001 mov esi, 1 \n"
" 00004509 48/ C7 C6 mov rsi, 1 \n"
" 00000001 \n"
" \n"
" 00004510 41/ 8A F9 mov dil, r9b \n"
" 00004513 66| 41/ 8B F1 mov si, r9w \n"
" 00004517 41/ 8B F1 mov esi, r9d \n"
" 0000451A 49/ 8B F1 mov rsi, r9 \n"
" \n"
" 0000451D 41/ 8A 79 FC mov dil, byte ptr [r9 - 4] \n"
" 00004521 41/ 8A 79 04 mov dil, byte ptr [r9 + 4] \n"
" 00004525 66| 41/ 8B 71 mov si, word ptr [r9 + 4] \n"
" 04 \n"
" 0000452A 41/ 8B 71 04 mov esi, dword ptr [r9 + 4] \n"
" 0000452E 49/ 8B 71 04 mov rsi, qword ptr [r9 + 4] \n"
" \n"
" 00004532 44/ 88 4E FC mov byte ptr [rsi - 4], r9b \n"
" 00004536 44/ 88 4E 04 mov byte ptr [rsi + 4], r9b \n"
" 0000453A 66| 44/ 89 4E mov word ptr [rsi + 4], r9w \n"
" 04 \n"
" 0000453F 44/ 89 4E 04 mov dword ptr [rsi + 4], r9d \n"
" 00004543 4C/ 89 4E 04 mov qword ptr [rsi + 4], r9 \n"
" \n"
" 00004547 66| 41/ 0F B6 F1 movzx si, r9b \n"
" 0000454C 66| 41/ 0F B6 71 movzx si, byte ptr [r9 + 4] \n"
" 04 \n"
" \n"
" 00004552 41/ 0F B6 F1 movzx esi, r9b \n"
" 00004556 41/ 0F B7 F1 movzx esi, r9w \n"
" 0000455A 41/ 0F B6 71 movzx esi, byte ptr [r9 + 4] \n"
" 04 \n"
" 0000455F 41/ 0F B7 71 movzx esi, word ptr [r9 + 4] \n"
" 04 \n"
" \n"
" 00004564 49/ 0F B6 F1 movzx rsi, r9b \n"
" 00004568 49/ 0F B7 F1 movzx rsi, r9w \n"
" 0000456C 49/ 0F B6 71 movzx rsi, byte ptr [r9 + 4] \n"
" 04 \n"
" 00004571 49/ 0F B7 71 movzx rsi, word ptr [r9 + 4] \n"
" 04 \n"
" \n"
" \n"
" ; Source: r9, target: rdi \n"
" 00004576 40/ B6 01 mov sil, 1 \n"
" 00004579 66| BF 0001 mov di, 1 \n"
" 0000457D BF 00000001 mov edi, 1 \n"
" 00004582 48/ C7 C7 mov rdi, 1 \n"
" 00000001 \n"
" \n"
" 00004589 41/ 8A F1 mov sil, r9b \n"
" 0000458C 66| 41/ 8B F9 mov di, r9w \n"
" 00004590 41/ 8B F9 mov edi, r9d \n"
" 00004593 49/ 8B F9 mov rdi, r9 \n"
" \n"
" 00004596 41/ 8A 71 FC mov sil, byte ptr [r9 - 4] \n"
" 0000459A 41/ 8A 71 04 mov sil, byte ptr [r9 + 4] \n"
" 0000459E 66| 41/ 8B 79 mov di, word ptr [r9 + 4] \n"
" 04 \n"
" 000045A3 41/ 8B 79 04 mov edi, dword ptr [r9 + 4] \n"
" 000045A7 49/ 8B 79 04 mov rdi, qword ptr [r9 + 4] \n"
" \n"
" 000045AB 44/ 88 4F FC mov byte ptr [rdi - 4], r9b \n"
" 000045AF 44/ 88 4F 04 mov byte ptr [rdi + 4], r9b \n"
" 000045B3 66| 44/ 89 4F mov word ptr [rdi + 4], r9w \n"
" 04 \n"
" 000045B8 44/ 89 4F 04 mov dword ptr [rdi + 4], r9d \n"
" 000045BC 4C/ 89 4F 04 mov qword ptr [rdi + 4], r9 \n"
" \n"
" 000045C0 66| 41/ 0F B6 F9 movzx di, r9b \n"
" 000045C5 66| 41/ 0F B6 79 movzx di, byte ptr [r9 + 4] \n"
" 04 \n"
" \n"
" 000045CB 41/ 0F B6 F9 movzx edi, r9b \n"
" 000045CF 41/ 0F B7 F9 movzx edi, r9w \n"
" 000045D3 41/ 0F B6 79 movzx edi, byte ptr [r9 + 4] \n"
" 04 \n"
" 000045D8 41/ 0F B7 79 movzx edi, word ptr [r9 + 4] \n"
" 04 \n"
" \n"
" 000045DD 49/ 0F B6 F9 movzx rdi, r9b \n"
" 000045E1 49/ 0F B7 F9 movzx rdi, r9w \n"
" 000045E5 49/ 0F B6 79 movzx rdi, byte ptr [r9 + 4] \n"
" 04 \n"
" 000045EA 49/ 0F B7 79 movzx rdi, word ptr [r9 + 4] \n"
" 04 \n"
" \n"
" \n"
" ; Source: r9, target: r8 \n"
" 000045EF 41/ B0 01 mov r8b, 1 \n"
" 000045F2 66| 41/ B8 mov r8w, 1 \n"
" 0001 \n"
" 000045F7 41/ B8 mov r8d, 1 \n"
" 00000001 \n"
" 000045FD 49/ C7 C0 mov r8, 1 \n"
" 00000001 \n"
" \n"
" 00004604 45/ 8A C1 mov r8b, r9b \n"
" 00004607 66| 45/ 8B C1 mov r8w, r9w \n"
" 0000460B 45/ 8B C1 mov r8d, r9d \n"
" 0000460E 4D/ 8B C1 mov r8, r9 \n"
" \n"
" 00004611 45/ 8A 41 FC mov r8b, byte ptr [r9 - 4] \n"
" 00004615 45/ 8A 41 04 mov r8b, byte ptr [r9 + 4] \n"
" 00004619 66| 45/ 8B 41 mov r8w, word ptr [r9 + 4] \n"
" 04 \n"
" 0000461E 45/ 8B 41 04 mov r8d, dword ptr [r9 + 4] \n"
" 00004622 4D/ 8B 41 04 mov r8, qword ptr [r9 + 4] \n"
" \n"
" 00004626 45/ 88 48 FC mov byte ptr [r8 - 4], r9b \n"
" 0000462A 45/ 88 48 04 mov byte ptr [r8 + 4], r9b \n"
" 0000462E 66| 45/ 89 48 mov word ptr [r8 + 4], r9w \n"
" 04 \n"
" 00004633 45/ 89 48 04 mov dword ptr [r8 + 4], r9d \n"
" 00004637 4D/ 89 48 04 mov qword ptr [r8 + 4], r9 \n"
" \n"
" 0000463B 66| 45/ 0F B6 C1 movzx r8w, r9b \n"
" 00004640 66| 45/ 0F B6 41 movzx r8w, byte ptr [r9 + 4] \n"
" 04 \n"
" \n"
" 00004646 45/ 0F B6 C1 movzx r8d, r9b \n"
" 0000464A 45/ 0F B7 C1 movzx r8d, r9w \n"
" 0000464E 45/ 0F B6 41 movzx r8d, byte ptr [r9 + 4] \n"
" 04 \n"
" 00004653 45/ 0F B7 41 movzx r8d, word ptr [r9 + 4] \n"
" 04 \n"
" \n"
" 00004658 4D/ 0F B6 C1 movzx r8, r9b \n"
" 0000465C 4D/ 0F B7 C1 movzx r8, r9w \n"
" 00004660 4D/ 0F B6 41 movzx r8, byte ptr [r9 + 4] \n"
" 04 \n"
" 00004665 4D/ 0F B7 41 movzx r8, word ptr [r9 + 4] \n"
" 04 \n"
" \n"
" \n"
" ; Source: r9, target: r9 \n"
" 0000466A 41/ B1 01 mov r9b, 1 \n"
" 0000466D 66| 41/ B9 mov r9w, 1 \n"
" 0001 \n"
" 00004672 41/ B9 mov r9d, 1 \n"
" 00000001 \n"
" 00004678 49/ C7 C1 mov r9, 1 \n"
" 00000001 \n"
" \n"
" 0000467F 45/ 8A C9 mov r9b, r9b \n"
" 00004682 66| 45/ 8B C9 mov r9w, r9w \n"
" 00004686 45/ 8B C9 mov r9d, r9d \n"
" 00004689 4D/ 8B C9 mov r9, r9 \n"
" \n"
" 0000468C 45/ 8A 49 FC mov r9b, byte ptr [r9 - 4] \n"
" 00004690 45/ 8A 49 04 mov r9b, byte ptr [r9 + 4] \n"
" 00004694 66| 45/ 8B 49 mov r9w, word ptr [r9 + 4] \n"
" 04 \n"
" 00004699 45/ 8B 49 04 mov r9d, dword ptr [r9 + 4] \n"
" 0000469D 4D/ 8B 49 04 mov r9, qword ptr [r9 + 4] \n"
" \n"
" 000046A1 45/ 88 49 FC mov byte ptr [r9 - 4], r9b \n"
" 000046A5 45/ 88 49 04 mov byte ptr [r9 + 4], r9b \n"
" 000046A9 66| 45/ 89 49 mov word ptr [r9 + 4], r9w \n"
" 04 \n"
" 000046AE 45/ 89 49 04 mov dword ptr [r9 + 4], r9d \n"
" 000046B2 4D/ 89 49 04 mov qword ptr [r9 + 4], r9 \n"
" \n"
" 000046B6 66| 45/ 0F B6 C9 movzx r9w, r9b \n"
" 000046BB 66| 45/ 0F B6 49 movzx r9w, byte ptr [r9 + 4] \n"
" 04 \n"
" \n"
" 000046C1 45/ 0F B6 C9 movzx r9d, r9b \n"
" 000046C5 45/ 0F B7 C9 movzx r9d, r9w \n"
" 000046C9 45/ 0F B6 49 movzx r9d, byte ptr [r9 + 4] \n"
" 04 \n"
" 000046CE 45/ 0F B7 49 movzx r9d, word ptr [r9 + 4] \n"
" 04 \n"
" \n"
" 000046D3 4D/ 0F B6 C9 movzx r9, r9b \n"
" 000046D7 4D/ 0F B7 C9 movzx r9, r9w \n"
" 000046DB 4D/ 0F B6 49 movzx r9, byte ptr [r9 + 4] \n"
" 04 \n"
" 000046E0 4D/ 0F B7 49 movzx r9, word ptr [r9 + 4] \n"
" 04 \n"
" \n"
" \n"
" ; Source: r9, target: r10 \n"
" 000046E5 41/ B2 01 mov r10b, 1 \n"
" 000046E8 66| 41/ BA mov r10w, 1 \n"
" 0001 \n"
" 000046ED 41/ BA mov r10d, 1 \n"
" 00000001 \n"
" 000046F3 49/ C7 C2 mov r10, 1 \n"
" 00000001 \n"
" \n"
" 000046FA 45/ 8A D1 mov r10b, r9b \n"
" 000046FD 66| 45/ 8B D1 mov r10w, r9w \n"
" 00004701 45/ 8B D1 mov r10d, r9d \n"
" 00004704 4D/ 8B D1 mov r10, r9 \n"
" \n"
" 00004707 45/ 8A 51 FC mov r10b, byte ptr [r9 - 4] \n"
" 0000470B 45/ 8A 51 04 mov r10b, byte ptr [r9 + 4] \n"
" 0000470F 66| 45/ 8B 51 mov r10w, word ptr [r9 + 4] \n"
" 04 \n"
" 00004714 45/ 8B 51 04 mov r10d, dword ptr [r9 + 4] \n"
" 00004718 4D/ 8B 51 04 mov r10, qword ptr [r9 + 4] \n"
" \n"
" 0000471C 45/ 88 4A FC mov byte ptr [r10 - 4], r9b \n"
" 00004720 45/ 88 4A 04 mov byte ptr [r10 + 4], r9b \n"
" 00004724 66| 45/ 89 4A mov word ptr [r10 + 4], r9w \n"
" 04 \n"
" 00004729 45/ 89 4A 04 mov dword ptr [r10 + 4], r9d \n"
" 0000472D 4D/ 89 4A 04 mov qword ptr [r10 + 4], r9 \n"
" \n"
" 00004731 66| 45/ 0F B6 D1 movzx r10w, r9b \n"
" 00004736 66| 45/ 0F B6 51 movzx r10w, byte ptr [r9 + 4] \n"
" 04 \n"
" \n"
" 0000473C 45/ 0F B6 D1 movzx r10d, r9b \n"
" 00004740 45/ 0F B7 D1 movzx r10d, r9w \n"
" 00004744 45/ 0F B6 51 movzx r10d, byte ptr [r9 + 4] \n"
" 04 \n"
" 00004749 45/ 0F B7 51 movzx r10d, word ptr [r9 + 4] \n"
" 04 \n"
" \n"
" 0000474E 4D/ 0F B6 D1 movzx r10, r9b \n"
" 00004752 4D/ 0F B7 D1 movzx r10, r9w \n"
" 00004756 4D/ 0F B6 51 movzx r10, byte ptr [r9 + 4] \n"
" 04 \n"
" 0000475B 4D/ 0F B7 51 movzx r10, word ptr [r9 + 4] \n"
" 04 \n"
" \n"
" \n"
" ; Source: r9, target: r11 \n"
" 00004760 41/ B3 01 mov r11b, 1 \n"
" 00004763 66| 41/ BB mov r11w, 1 \n"
" 0001 \n"
" 00004768 41/ BB mov r11d, 1 \n"
" 00000001 \n"
" 0000476E 49/ C7 C3 mov r11, 1 \n"
" 00000001 \n"
" \n"
" 00004775 45/ 8A D9 mov r11b, r9b \n"
" 00004778 66| 45/ 8B D9 mov r11w, r9w \n"
" 0000477C 45/ 8B D9 mov r11d, r9d \n"
" 0000477F 4D/ 8B D9 mov r11, r9 \n"
" \n"
" 00004782 45/ 8A 59 FC mov r11b, byte ptr [r9 - 4] \n"
" 00004786 45/ 8A 59 04 mov r11b, byte ptr [r9 + 4] \n"
" 0000478A 66| 45/ 8B 59 mov r11w, word ptr [r9 + 4] \n"
" 04 \n"
" 0000478F 45/ 8B 59 04 mov r11d, dword ptr [r9 + 4] \n"
" 00004793 4D/ 8B 59 04 mov r11, qword ptr [r9 + 4] \n"
" \n"
" 00004797 45/ 88 4B FC mov byte ptr [r11 - 4], r9b \n"
" 0000479B 45/ 88 4B 04 mov byte ptr [r11 + 4], r9b \n"
" 0000479F 66| 45/ 89 4B mov word ptr [r11 + 4], r9w \n"
" 04 \n"
" 000047A4 45/ 89 4B 04 mov dword ptr [r11 + 4], r9d \n"
" 000047A8 4D/ 89 4B 04 mov qword ptr [r11 + 4], r9 \n"
" \n"
" 000047AC 66| 45/ 0F B6 D9 movzx r11w, r9b \n"
" 000047B1 66| 45/ 0F B6 59 movzx r11w, byte ptr [r9 + 4] \n"
" 04 \n"
" \n"
" 000047B7 45/ 0F B6 D9 movzx r11d, r9b \n"
" 000047BB 45/ 0F B7 D9 movzx r11d, r9w \n"
" 000047BF 45/ 0F B6 59 movzx r11d, byte ptr [r9 + 4] \n"
" 04 \n"
" 000047C4 45/ 0F B7 59 movzx r11d, word ptr [r9 + 4] \n"
" 04 \n"
" \n"
" 000047C9 4D/ 0F B6 D9 movzx r11, r9b \n"
" 000047CD 4D/ 0F B7 D9 movzx r11, r9w \n"
" 000047D1 4D/ 0F B6 59 movzx r11, byte ptr [r9 + 4] \n"
" 04 \n"
" 000047D6 4D/ 0F B7 59 movzx r11, word ptr [r9 + 4] \n"
" 04 \n"
" \n"
" \n"
" ; Source: r9, target: r12 \n"
" 000047DB 41/ B4 01 mov r12b, 1 \n"
" 000047DE 66| 41/ BC mov r12w, 1 \n"
" 0001 \n"
" 000047E3 41/ BC mov r12d, 1 \n"
" 00000001 \n"
" 000047E9 49/ C7 C4 mov r12, 1 \n"
" 00000001 \n"
" \n"
" 000047F0 45/ 8A E1 mov r12b, r9b \n"
" 000047F3 66| 45/ 8B E1 mov r12w, r9w \n"
" 000047F7 45/ 8B E1 mov r12d, r9d \n"
" 000047FA 4D/ 8B E1 mov r12, r9 \n"
" \n"
" 000047FD 45/ 8A 61 FC mov r12b, byte ptr [r9 - 4] \n"
" 00004801 45/ 8A 61 04 mov r12b, byte ptr [r9 + 4] \n"
" 00004805 66| 45/ 8B 61 mov r12w, word ptr [r9 + 4] \n"
" 04 \n"
" 0000480A 45/ 8B 61 04 mov r12d, dword ptr [r9 + 4] \n"
" 0000480E 4D/ 8B 61 04 mov r12, qword ptr [r9 + 4] \n"
" \n"
" 00004812 45/ 88 4C 24 mov byte ptr [r12 - 4], r9b \n"
" FC \n"
" 00004817 45/ 88 4C 24 mov byte ptr [r12 + 4], r9b \n"
" 04 \n"
" 0000481C 66| 45/ 89 4C 24 mov word ptr [r12 + 4], r9w \n"
" 04 \n"
" 00004822 45/ 89 4C 24 mov dword ptr [r12 + 4], r9d \n"
" 04 \n"
" 00004827 4D/ 89 4C 24 mov qword ptr [r12 + 4], r9 \n"
" 04 \n"
" \n"
" 0000482C 66| 45/ 0F B6 E1 movzx r12w, r9b \n"
" 00004831 66| 45/ 0F B6 61 movzx r12w, byte ptr [r9 + 4] \n"
" 04 \n"
" \n"
" 00004837 45/ 0F B6 E1 movzx r12d, r9b \n"
" 0000483B 45/ 0F B7 E1 movzx r12d, r9w \n"
" 0000483F 45/ 0F B6 61 movzx r12d, byte ptr [r9 + 4] \n"
" 04 \n"
" 00004844 45/ 0F B7 61 movzx r12d, word ptr [r9 + 4] \n"
" 04 \n"
" \n"
" 00004849 4D/ 0F B6 E1 movzx r12, r9b \n"
" 0000484D 4D/ 0F B7 E1 movzx r12, r9w \n"
" 00004851 4D/ 0F B6 61 movzx r12, byte ptr [r9 + 4] \n"
" 04 \n"
" 00004856 4D/ 0F B7 61 movzx r12, word ptr [r9 + 4] \n"
" 04 \n"
" \n"
" \n"
" ; Source: r9, target: r13 \n"
" 0000485B 41/ B5 01 mov r13b, 1 \n"
" 0000485E 66| 41/ BD mov r13w, 1 \n"
" 0001 \n"
" 00004863 41/ BD mov r13d, 1 \n"
" 00000001 \n"
" 00004869 49/ C7 C5 mov r13, 1 \n"
" 00000001 \n"
" \n"
" 00004870 45/ 8A E9 mov r13b, r9b \n"
" 00004873 66| 45/ 8B E9 mov r13w, r9w \n"
" 00004877 45/ 8B E9 mov r13d, r9d \n"
" 0000487A 4D/ 8B E9 mov r13, r9 \n"
" \n"
" 0000487D 45/ 8A 69 FC mov r13b, byte ptr [r9 - 4] \n"
" 00004881 45/ 8A 69 04 mov r13b, byte ptr [r9 + 4] \n"
" 00004885 66| 45/ 8B 69 mov r13w, word ptr [r9 + 4] \n"
" 04 \n"
" 0000488A 45/ 8B 69 04 mov r13d, dword ptr [r9 + 4] \n"
" 0000488E 4D/ 8B 69 04 mov r13, qword ptr [r9 + 4] \n"
" \n"
" 00004892 45/ 88 4D FC mov byte ptr [r13 - 4], r9b \n"
" 00004896 45/ 88 4D 04 mov byte ptr [r13 + 4], r9b \n"
" 0000489A 66| 45/ 89 4D mov word ptr [r13 + 4], r9w \n"
" 04 \n"
" 0000489F 45/ 89 4D 04 mov dword ptr [r13 + 4], r9d \n"
" 000048A3 4D/ 89 4D 04 mov qword ptr [r13 + 4], r9 \n"
" \n"
" 000048A7 66| 45/ 0F B6 E9 movzx r13w, r9b \n"
" 000048AC 66| 45/ 0F B6 69 movzx r13w, byte ptr [r9 + 4] \n"
" 04 \n"
" \n"
" 000048B2 45/ 0F B6 E9 movzx r13d, r9b \n"
" 000048B6 45/ 0F B7 E9 movzx r13d, r9w \n"
" 000048BA 45/ 0F B6 69 movzx r13d, byte ptr [r9 + 4] \n"
" 04 \n"
" 000048BF 45/ 0F B7 69 movzx r13d, word ptr [r9 + 4] \n"
" 04 \n"
" \n"
" 000048C4 4D/ 0F B6 E9 movzx r13, r9b \n"
" 000048C8 4D/ 0F B7 E9 movzx r13, r9w \n"
" 000048CC 4D/ 0F B6 69 movzx r13, byte ptr [r9 + 4] \n"
" 04 \n"
" 000048D1 4D/ 0F B7 69 movzx r13, word ptr [r9 + 4] \n"
" 04 \n"
" \n"
" \n"
" ; Source: r9, target: r14 \n"
" 000048D6 41/ B6 01 mov r14b, 1 \n";
ml64Output +=
" 000048D9 66| 41/ BE mov r14w, 1 \n"
" 0001 \n"
" 000048DE 41/ BE mov r14d, 1 \n"
" 00000001 \n"
" 000048E4 49/ C7 C6 mov r14, 1 \n"
" 00000001 \n"
" \n"
" 000048EB 45/ 8A F1 mov r14b, r9b \n"
" 000048EE 66| 45/ 8B F1 mov r14w, r9w \n"
" 000048F2 45/ 8B F1 mov r14d, r9d \n"
" 000048F5 4D/ 8B F1 mov r14, r9 \n"
" \n"
" 000048F8 45/ 8A 71 FC mov r14b, byte ptr [r9 - 4] \n"
" 000048FC 45/ 8A 71 04 mov r14b, byte ptr [r9 + 4] \n"
" 00004900 66| 45/ 8B 71 mov r14w, word ptr [r9 + 4] \n"
" 04 \n"
" 00004905 45/ 8B 71 04 mov r14d, dword ptr [r9 + 4] \n"
" 00004909 4D/ 8B 71 04 mov r14, qword ptr [r9 + 4] \n"
" \n"
" 0000490D 45/ 88 4E FC mov byte ptr [r14 - 4], r9b \n"
" 00004911 45/ 88 4E 04 mov byte ptr [r14 + 4], r9b \n"
" 00004915 66| 45/ 89 4E mov word ptr [r14 + 4], r9w \n"
" 04 \n"
" 0000491A 45/ 89 4E 04 mov dword ptr [r14 + 4], r9d \n"
" 0000491E 4D/ 89 4E 04 mov qword ptr [r14 + 4], r9 \n"
" \n"
" 00004922 66| 45/ 0F B6 F1 movzx r14w, r9b \n"
" 00004927 66| 45/ 0F B6 71 movzx r14w, byte ptr [r9 + 4] \n"
" 04 \n"
" \n"
" 0000492D 45/ 0F B6 F1 movzx r14d, r9b \n"
" 00004931 45/ 0F B7 F1 movzx r14d, r9w \n"
" 00004935 45/ 0F B6 71 movzx r14d, byte ptr [r9 + 4] \n"
" 04 \n"
" 0000493A 45/ 0F B7 71 movzx r14d, word ptr [r9 + 4] \n"
" 04 \n"
" \n"
" 0000493F 4D/ 0F B6 F1 movzx r14, r9b \n"
" 00004943 4D/ 0F B7 F1 movzx r14, r9w \n"
" 00004947 4D/ 0F B6 71 movzx r14, byte ptr [r9 + 4] \n"
" 04 \n"
" 0000494C 4D/ 0F B7 71 movzx r14, word ptr [r9 + 4] \n"
" 04 \n"
" \n"
" \n"
" ; Source: r9, target: r15 \n"
" 00004951 41/ B7 01 mov r15b, 1 \n"
" 00004954 66| 41/ BF mov r15w, 1 \n"
" 0001 \n"
" 00004959 41/ BF mov r15d, 1 \n"
" 00000001 \n"
" 0000495F 49/ C7 C7 mov r15, 1 \n"
" 00000001 \n"
" \n"
" 00004966 45/ 8A F9 mov r15b, r9b \n"
" 00004969 66| 45/ 8B F9 mov r15w, r9w \n"
" 0000496D 45/ 8B F9 mov r15d, r9d \n"
" 00004970 4D/ 8B F9 mov r15, r9 \n"
" \n"
" 00004973 45/ 8A 79 FC mov r15b, byte ptr [r9 - 4] \n"
" 00004977 45/ 8A 79 04 mov r15b, byte ptr [r9 + 4] \n"
" 0000497B 66| 45/ 8B 79 mov r15w, word ptr [r9 + 4] \n"
" 04 \n"
" 00004980 45/ 8B 79 04 mov r15d, dword ptr [r9 + 4] \n"
" 00004984 4D/ 8B 79 04 mov r15, qword ptr [r9 + 4] \n"
" \n"
" 00004988 45/ 88 4F FC mov byte ptr [r15 - 4], r9b \n"
" 0000498C 45/ 88 4F 04 mov byte ptr [r15 + 4], r9b \n"
" 00004990 66| 45/ 89 4F mov word ptr [r15 + 4], r9w \n"
" 04 \n"
" 00004995 45/ 89 4F 04 mov dword ptr [r15 + 4], r9d \n"
" 00004999 4D/ 89 4F 04 mov qword ptr [r15 + 4], r9 \n"
" \n"
" 0000499D 66| 45/ 0F B6 F9 movzx r15w, r9b \n"
" 000049A2 66| 45/ 0F B6 79 movzx r15w, byte ptr [r9 + 4] \n"
" 04 \n"
" \n"
" 000049A8 45/ 0F B6 F9 movzx r15d, r9b \n"
" 000049AC 45/ 0F B7 F9 movzx r15d, r9w \n"
" 000049B0 45/ 0F B6 79 movzx r15d, byte ptr [r9 + 4] \n"
" 04 \n"
" 000049B5 45/ 0F B7 79 movzx r15d, word ptr [r9 + 4] \n"
" 04 \n"
" \n"
" 000049BA 4D/ 0F B6 F9 movzx r15, r9b \n"
" 000049BE 4D/ 0F B7 F9 movzx r15, r9w \n"
" 000049C2 4D/ 0F B6 79 movzx r15, byte ptr [r9 + 4] \n"
" 04 \n"
" 000049C7 4D/ 0F B7 79 movzx r15, word ptr [r9 + 4] \n"
" 04 \n"
" \n"
" \n"
" ; Source: r10, target: rax \n"
" 000049CC B0 01 mov al, 1 \n"
" 000049CE 66| B8 0001 mov ax, 1 \n"
" 000049D2 B8 00000001 mov eax, 1 \n"
" 000049D7 48/ C7 C0 mov rax, 1 \n"
" 00000001 \n"
" \n"
" 000049DE 41/ 8A C2 mov al, r10b \n"
" 000049E1 66| 41/ 8B C2 mov ax, r10w \n"
" 000049E5 41/ 8B C2 mov eax, r10d \n"
" 000049E8 49/ 8B C2 mov rax, r10 \n"
" \n"
" 000049EB 41/ 8A 42 FC mov al, byte ptr [r10 - 4] \n"
" 000049EF 41/ 8A 42 04 mov al, byte ptr [r10 + 4] \n"
" 000049F3 66| 41/ 8B 42 mov ax, word ptr [r10 + 4] \n"
" 04 \n"
" 000049F8 41/ 8B 42 04 mov eax, dword ptr [r10 + 4] \n"
" 000049FC 49/ 8B 42 04 mov rax, qword ptr [r10 + 4] \n"
" \n"
" 00004A00 44/ 88 50 FC mov byte ptr [rax - 4], r10b \n"
" 00004A04 44/ 88 50 04 mov byte ptr [rax + 4], r10b \n"
" 00004A08 66| 44/ 89 50 mov word ptr [rax + 4], r10w \n"
" 04 \n"
" 00004A0D 44/ 89 50 04 mov dword ptr [rax + 4], r10d \n"
" 00004A11 4C/ 89 50 04 mov qword ptr [rax + 4], r10 \n"
" \n"
" 00004A15 66| 41/ 0F B6 C2 movzx ax, r10b \n"
" 00004A1A 66| 41/ 0F B6 42 movzx ax, byte ptr [r10 + 4] \n"
" 04 \n"
" \n"
" 00004A20 41/ 0F B6 C2 movzx eax, r10b \n"
" 00004A24 41/ 0F B7 C2 movzx eax, r10w \n"
" 00004A28 41/ 0F B6 42 movzx eax, byte ptr [r10 + 4] \n"
" 04 \n"
" 00004A2D 41/ 0F B7 42 movzx eax, word ptr [r10 + 4] \n"
" 04 \n"
" \n"
" 00004A32 49/ 0F B6 C2 movzx rax, r10b \n"
" 00004A36 49/ 0F B7 C2 movzx rax, r10w \n"
" 00004A3A 49/ 0F B6 42 movzx rax, byte ptr [r10 + 4] \n"
" 04 \n"
" 00004A3F 49/ 0F B7 42 movzx rax, word ptr [r10 + 4] \n"
" 04 \n"
" \n"
" \n"
" ; Source: r10, target: rcx \n"
" 00004A44 B1 01 mov cl, 1 \n"
" 00004A46 66| B9 0001 mov cx, 1 \n"
" 00004A4A B9 00000001 mov ecx, 1 \n"
" 00004A4F 48/ C7 C1 mov rcx, 1 \n"
" 00000001 \n"
" \n"
" 00004A56 41/ 8A CA mov cl, r10b \n"
" 00004A59 66| 41/ 8B CA mov cx, r10w \n"
" 00004A5D 41/ 8B CA mov ecx, r10d \n"
" 00004A60 49/ 8B CA mov rcx, r10 \n"
" \n"
" 00004A63 41/ 8A 4A FC mov cl, byte ptr [r10 - 4] \n"
" 00004A67 41/ 8A 4A 04 mov cl, byte ptr [r10 + 4] \n"
" 00004A6B 66| 41/ 8B 4A mov cx, word ptr [r10 + 4] \n"
" 04 \n"
" 00004A70 41/ 8B 4A 04 mov ecx, dword ptr [r10 + 4] \n"
" 00004A74 49/ 8B 4A 04 mov rcx, qword ptr [r10 + 4] \n"
" \n"
" 00004A78 44/ 88 51 FC mov byte ptr [rcx - 4], r10b \n"
" 00004A7C 44/ 88 51 04 mov byte ptr [rcx + 4], r10b \n"
" 00004A80 66| 44/ 89 51 mov word ptr [rcx + 4], r10w \n"
" 04 \n"
" 00004A85 44/ 89 51 04 mov dword ptr [rcx + 4], r10d \n"
" 00004A89 4C/ 89 51 04 mov qword ptr [rcx + 4], r10 \n"
" \n"
" 00004A8D 66| 41/ 0F B6 CA movzx cx, r10b \n"
" 00004A92 66| 41/ 0F B6 4A movzx cx, byte ptr [r10 + 4] \n"
" 04 \n"
" \n"
" 00004A98 41/ 0F B6 CA movzx ecx, r10b \n"
" 00004A9C 41/ 0F B7 CA movzx ecx, r10w \n"
" 00004AA0 41/ 0F B6 4A movzx ecx, byte ptr [r10 + 4] \n"
" 04 \n"
" 00004AA5 41/ 0F B7 4A movzx ecx, word ptr [r10 + 4] \n"
" 04 \n"
" \n"
" 00004AAA 49/ 0F B6 CA movzx rcx, r10b \n"
" 00004AAE 49/ 0F B7 CA movzx rcx, r10w \n"
" 00004AB2 49/ 0F B6 4A movzx rcx, byte ptr [r10 + 4] \n"
" 04 \n"
" 00004AB7 49/ 0F B7 4A movzx rcx, word ptr [r10 + 4] \n"
" 04 \n"
" \n"
" \n"
" ; Source: r10, target: rdx \n"
" 00004ABC B2 01 mov dl, 1 \n"
" 00004ABE 66| BA 0001 mov dx, 1 \n"
" 00004AC2 BA 00000001 mov edx, 1 \n"
" 00004AC7 48/ C7 C2 mov rdx, 1 \n"
" 00000001 \n"
" \n"
" 00004ACE 41/ 8A D2 mov dl, r10b \n"
" 00004AD1 66| 41/ 8B D2 mov dx, r10w \n"
" 00004AD5 41/ 8B D2 mov edx, r10d \n"
" 00004AD8 49/ 8B D2 mov rdx, r10 \n"
" \n"
" 00004ADB 41/ 8A 52 FC mov dl, byte ptr [r10 - 4] \n"
" 00004ADF 41/ 8A 52 04 mov dl, byte ptr [r10 + 4] \n"
" 00004AE3 66| 41/ 8B 52 mov dx, word ptr [r10 + 4] \n"
" 04 \n"
" 00004AE8 41/ 8B 52 04 mov edx, dword ptr [r10 + 4] \n"
" 00004AEC 49/ 8B 52 04 mov rdx, qword ptr [r10 + 4] \n"
" \n"
" 00004AF0 44/ 88 52 FC mov byte ptr [rdx - 4], r10b \n"
" 00004AF4 44/ 88 52 04 mov byte ptr [rdx + 4], r10b \n"
" 00004AF8 66| 44/ 89 52 mov word ptr [rdx + 4], r10w \n"
" 04 \n"
" 00004AFD 44/ 89 52 04 mov dword ptr [rdx + 4], r10d \n"
" 00004B01 4C/ 89 52 04 mov qword ptr [rdx + 4], r10 \n"
" \n"
" 00004B05 66| 41/ 0F B6 D2 movzx dx, r10b \n"
" 00004B0A 66| 41/ 0F B6 52 movzx dx, byte ptr [r10 + 4] \n"
" 04 \n"
" \n"
" 00004B10 41/ 0F B6 D2 movzx edx, r10b \n"
" 00004B14 41/ 0F B7 D2 movzx edx, r10w \n"
" 00004B18 41/ 0F B6 52 movzx edx, byte ptr [r10 + 4] \n"
" 04 \n"
" 00004B1D 41/ 0F B7 52 movzx edx, word ptr [r10 + 4] \n"
" 04 \n"
" \n"
" 00004B22 49/ 0F B6 D2 movzx rdx, r10b \n"
" 00004B26 49/ 0F B7 D2 movzx rdx, r10w \n"
" 00004B2A 49/ 0F B6 52 movzx rdx, byte ptr [r10 + 4] \n"
" 04 \n"
" 00004B2F 49/ 0F B7 52 movzx rdx, word ptr [r10 + 4] \n"
" 04 \n"
" \n"
" \n"
" ; Source: r10, target: rbx \n"
" 00004B34 B3 01 mov bl, 1 \n"
" 00004B36 66| BB 0001 mov bx, 1 \n"
" 00004B3A BB 00000001 mov ebx, 1 \n"
" 00004B3F 48/ C7 C3 mov rbx, 1 \n"
" 00000001 \n"
" \n"
" 00004B46 41/ 8A DA mov bl, r10b \n"
" 00004B49 66| 41/ 8B DA mov bx, r10w \n"
" 00004B4D 41/ 8B DA mov ebx, r10d \n"
" 00004B50 49/ 8B DA mov rbx, r10 \n"
" \n"
" 00004B53 41/ 8A 5A FC mov bl, byte ptr [r10 - 4] \n"
" 00004B57 41/ 8A 5A 04 mov bl, byte ptr [r10 + 4] \n"
" 00004B5B 66| 41/ 8B 5A mov bx, word ptr [r10 + 4] \n"
" 04 \n"
" 00004B60 41/ 8B 5A 04 mov ebx, dword ptr [r10 + 4] \n"
" 00004B64 49/ 8B 5A 04 mov rbx, qword ptr [r10 + 4] \n"
" \n"
" 00004B68 44/ 88 53 FC mov byte ptr [rbx - 4], r10b \n"
" 00004B6C 44/ 88 53 04 mov byte ptr [rbx + 4], r10b \n"
" 00004B70 66| 44/ 89 53 mov word ptr [rbx + 4], r10w \n"
" 04 \n"
" 00004B75 44/ 89 53 04 mov dword ptr [rbx + 4], r10d \n"
" 00004B79 4C/ 89 53 04 mov qword ptr [rbx + 4], r10 \n"
" \n"
" 00004B7D 66| 41/ 0F B6 DA movzx bx, r10b \n"
" 00004B82 66| 41/ 0F B6 5A movzx bx, byte ptr [r10 + 4] \n"
" 04 \n"
" \n"
" 00004B88 41/ 0F B6 DA movzx ebx, r10b \n"
" 00004B8C 41/ 0F B7 DA movzx ebx, r10w \n"
" 00004B90 41/ 0F B6 5A movzx ebx, byte ptr [r10 + 4] \n"
" 04 \n"
" 00004B95 41/ 0F B7 5A movzx ebx, word ptr [r10 + 4] \n"
" 04 \n"
" \n"
" 00004B9A 49/ 0F B6 DA movzx rbx, r10b \n"
" 00004B9E 49/ 0F B7 DA movzx rbx, r10w \n"
" 00004BA2 49/ 0F B6 5A movzx rbx, byte ptr [r10 + 4] \n"
" 04 \n"
" 00004BA7 49/ 0F B7 5A movzx rbx, word ptr [r10 + 4] \n"
" 04 \n"
" \n"
" \n"
" ; Source: r10, target: rsp \n"
" 00004BAC 40/ B4 01 mov spl, 1 \n"
" 00004BAF 66| BC 0001 mov sp, 1 \n"
" 00004BB3 BC 00000001 mov esp, 1 \n"
" 00004BB8 48/ C7 C4 mov rsp, 1 \n"
" 00000001 \n"
" \n"
" 00004BBF 41/ 8A E2 mov spl, r10b \n"
" 00004BC2 66| 41/ 8B E2 mov sp, r10w \n"
" 00004BC6 41/ 8B E2 mov esp, r10d \n"
" 00004BC9 49/ 8B E2 mov rsp, r10 \n"
" \n"
" 00004BCC 41/ 8A 62 FC mov spl, byte ptr [r10 - 4] \n"
" 00004BD0 41/ 8A 62 04 mov spl, byte ptr [r10 + 4] \n"
" 00004BD4 66| 41/ 8B 62 mov sp, word ptr [r10 + 4] \n"
" 04 \n"
" 00004BD9 41/ 8B 62 04 mov esp, dword ptr [r10 + 4] \n"
" 00004BDD 49/ 8B 62 04 mov rsp, qword ptr [r10 + 4] \n"
" \n"
" 00004BE1 44/ 88 54 24 mov byte ptr [rsp - 4], r10b \n"
" FC \n"
" 00004BE6 44/ 88 54 24 mov byte ptr [rsp + 4], r10b \n"
" 04 \n"
" 00004BEB 66| 44/ 89 54 24 mov word ptr [rsp + 4], r10w \n"
" 04 \n"
" 00004BF1 44/ 89 54 24 mov dword ptr [rsp + 4], r10d \n"
" 04 \n"
" 00004BF6 4C/ 89 54 24 mov qword ptr [rsp + 4], r10 \n"
" 04 \n"
" \n"
" 00004BFB 66| 41/ 0F B6 E2 movzx sp, r10b \n"
" 00004C00 66| 41/ 0F B6 62 movzx sp, byte ptr [r10 + 4] \n"
" 04 \n"
" \n"
" 00004C06 41/ 0F B6 E2 movzx esp, r10b \n"
" 00004C0A 41/ 0F B7 E2 movzx esp, r10w \n"
" 00004C0E 41/ 0F B6 62 movzx esp, byte ptr [r10 + 4] \n"
" 04 \n"
" 00004C13 41/ 0F B7 62 movzx esp, word ptr [r10 + 4] \n"
" 04 \n"
" \n"
" 00004C18 49/ 0F B6 E2 movzx rsp, r10b \n"
" 00004C1C 49/ 0F B7 E2 movzx rsp, r10w \n"
" 00004C20 49/ 0F B6 62 movzx rsp, byte ptr [r10 + 4] \n"
" 04 \n"
" 00004C25 49/ 0F B7 62 movzx rsp, word ptr [r10 + 4] \n"
" 04 \n"
" \n"
" \n"
" ; Source: r10, target: rbp \n"
" 00004C2A 40/ B5 01 mov bpl, 1 \n"
" 00004C2D 66| BD 0001 mov bp, 1 \n"
" 00004C31 BD 00000001 mov ebp, 1 \n"
" 00004C36 48/ C7 C5 mov rbp, 1 \n"
" 00000001 \n"
" \n"
" 00004C3D 41/ 8A EA mov bpl, r10b \n"
" 00004C40 66| 41/ 8B EA mov bp, r10w \n"
" 00004C44 41/ 8B EA mov ebp, r10d \n"
" 00004C47 49/ 8B EA mov rbp, r10 \n"
" \n"
" 00004C4A 41/ 8A 6A FC mov bpl, byte ptr [r10 - 4] \n"
" 00004C4E 41/ 8A 6A 04 mov bpl, byte ptr [r10 + 4] \n"
" 00004C52 66| 41/ 8B 6A mov bp, word ptr [r10 + 4] \n"
" 04 \n"
" 00004C57 41/ 8B 6A 04 mov ebp, dword ptr [r10 + 4] \n"
" 00004C5B 49/ 8B 6A 04 mov rbp, qword ptr [r10 + 4] \n"
" \n"
" 00004C5F 44/ 88 55 FC mov byte ptr [rbp - 4], r10b \n"
" 00004C63 44/ 88 55 04 mov byte ptr [rbp + 4], r10b \n"
" 00004C67 66| 44/ 89 55 mov word ptr [rbp + 4], r10w \n"
" 04 \n"
" 00004C6C 44/ 89 55 04 mov dword ptr [rbp + 4], r10d \n"
" 00004C70 4C/ 89 55 04 mov qword ptr [rbp + 4], r10 \n"
" \n"
" 00004C74 66| 41/ 0F B6 EA movzx bp, r10b \n"
" 00004C79 66| 41/ 0F B6 6A movzx bp, byte ptr [r10 + 4] \n"
" 04 \n"
" \n"
" 00004C7F 41/ 0F B6 EA movzx ebp, r10b \n"
" 00004C83 41/ 0F B7 EA movzx ebp, r10w \n"
" 00004C87 41/ 0F B6 6A movzx ebp, byte ptr [r10 + 4] \n"
" 04 \n"
" 00004C8C 41/ 0F B7 6A movzx ebp, word ptr [r10 + 4] \n"
" 04 \n"
" \n"
" 00004C91 49/ 0F B6 EA movzx rbp, r10b \n"
" 00004C95 49/ 0F B7 EA movzx rbp, r10w \n"
" 00004C99 49/ 0F B6 6A movzx rbp, byte ptr [r10 + 4] \n"
" 04 \n"
" 00004C9E 49/ 0F B7 6A movzx rbp, word ptr [r10 + 4] \n"
" 04 \n"
" \n"
" \n"
" ; Source: r10, target: rsi \n"
" 00004CA3 40/ B7 01 mov dil, 1 \n"
" 00004CA6 66| BE 0001 mov si, 1 \n"
" 00004CAA BE 00000001 mov esi, 1 \n"
" 00004CAF 48/ C7 C6 mov rsi, 1 \n"
" 00000001 \n"
" \n"
" 00004CB6 41/ 8A FA mov dil, r10b \n"
" 00004CB9 66| 41/ 8B F2 mov si, r10w \n"
" 00004CBD 41/ 8B F2 mov esi, r10d \n"
" 00004CC0 49/ 8B F2 mov rsi, r10 \n"
" \n"
" 00004CC3 41/ 8A 7A FC mov dil, byte ptr [r10 - 4] \n"
" 00004CC7 41/ 8A 7A 04 mov dil, byte ptr [r10 + 4] \n"
" 00004CCB 66| 41/ 8B 72 mov si, word ptr [r10 + 4] \n"
" 04 \n"
" 00004CD0 41/ 8B 72 04 mov esi, dword ptr [r10 + 4] \n"
" 00004CD4 49/ 8B 72 04 mov rsi, qword ptr [r10 + 4] \n"
" \n"
" 00004CD8 44/ 88 56 FC mov byte ptr [rsi - 4], r10b \n"
" 00004CDC 44/ 88 56 04 mov byte ptr [rsi + 4], r10b \n"
" 00004CE0 66| 44/ 89 56 mov word ptr [rsi + 4], r10w \n"
" 04 \n"
" 00004CE5 44/ 89 56 04 mov dword ptr [rsi + 4], r10d \n"
" 00004CE9 4C/ 89 56 04 mov qword ptr [rsi + 4], r10 \n"
" \n"
" 00004CED 66| 41/ 0F B6 F2 movzx si, r10b \n"
" 00004CF2 66| 41/ 0F B6 72 movzx si, byte ptr [r10 + 4] \n"
" 04 \n"
" \n"
" 00004CF8 41/ 0F B6 F2 movzx esi, r10b \n"
" 00004CFC 41/ 0F B7 F2 movzx esi, r10w \n"
" 00004D00 41/ 0F B6 72 movzx esi, byte ptr [r10 + 4] \n"
" 04 \n"
" 00004D05 41/ 0F B7 72 movzx esi, word ptr [r10 + 4] \n"
" 04 \n"
" \n"
" 00004D0A 49/ 0F B6 F2 movzx rsi, r10b \n"
" 00004D0E 49/ 0F B7 F2 movzx rsi, r10w \n"
" 00004D12 49/ 0F B6 72 movzx rsi, byte ptr [r10 + 4] \n"
" 04 \n"
" 00004D17 49/ 0F B7 72 movzx rsi, word ptr [r10 + 4] \n"
" 04 \n"
" \n"
" \n"
" ; Source: r10, target: rdi \n"
" 00004D1C 40/ B6 01 mov sil, 1 \n"
" 00004D1F 66| BF 0001 mov di, 1 \n"
" 00004D23 BF 00000001 mov edi, 1 \n"
" 00004D28 48/ C7 C7 mov rdi, 1 \n"
" 00000001 \n"
" \n"
" 00004D2F 41/ 8A F2 mov sil, r10b \n"
" 00004D32 66| 41/ 8B FA mov di, r10w \n"
" 00004D36 41/ 8B FA mov edi, r10d \n"
" 00004D39 49/ 8B FA mov rdi, r10 \n"
" \n"
" 00004D3C 41/ 8A 72 FC mov sil, byte ptr [r10 - 4] \n"
" 00004D40 41/ 8A 72 04 mov sil, byte ptr [r10 + 4] \n"
" 00004D44 66| 41/ 8B 7A mov di, word ptr [r10 + 4] \n"
" 04 \n"
" 00004D49 41/ 8B 7A 04 mov edi, dword ptr [r10 + 4] \n"
" 00004D4D 49/ 8B 7A 04 mov rdi, qword ptr [r10 + 4] \n"
" \n"
" 00004D51 44/ 88 57 FC mov byte ptr [rdi - 4], r10b \n"
" 00004D55 44/ 88 57 04 mov byte ptr [rdi + 4], r10b \n"
" 00004D59 66| 44/ 89 57 mov word ptr [rdi + 4], r10w \n"
" 04 \n"
" 00004D5E 44/ 89 57 04 mov dword ptr [rdi + 4], r10d \n"
" 00004D62 4C/ 89 57 04 mov qword ptr [rdi + 4], r10 \n"
" \n"
" 00004D66 66| 41/ 0F B6 FA movzx di, r10b \n"
" 00004D6B 66| 41/ 0F B6 7A movzx di, byte ptr [r10 + 4] \n"
" 04 \n"
" \n"
" 00004D71 41/ 0F B6 FA movzx edi, r10b \n"
" 00004D75 41/ 0F B7 FA movzx edi, r10w \n"
" 00004D79 41/ 0F B6 7A movzx edi, byte ptr [r10 + 4] \n"
" 04 \n"
" 00004D7E 41/ 0F B7 7A movzx edi, word ptr [r10 + 4] \n"
" 04 \n"
" \n"
" 00004D83 49/ 0F B6 FA movzx rdi, r10b \n"
" 00004D87 49/ 0F B7 FA movzx rdi, r10w \n"
" 00004D8B 49/ 0F B6 7A movzx rdi, byte ptr [r10 + 4] \n"
" 04 \n"
" 00004D90 49/ 0F B7 7A movzx rdi, word ptr [r10 + 4] \n"
" 04 \n"
" \n"
" \n"
" ; Source: r10, target: r8 \n"
" 00004D95 41/ B0 01 mov r8b, 1 \n"
" 00004D98 66| 41/ B8 mov r8w, 1 \n"
" 0001 \n"
" 00004D9D 41/ B8 mov r8d, 1 \n"
" 00000001 \n"
" 00004DA3 49/ C7 C0 mov r8, 1 \n"
" 00000001 \n"
" \n"
" 00004DAA 45/ 8A C2 mov r8b, r10b \n"
" 00004DAD 66| 45/ 8B C2 mov r8w, r10w \n"
" 00004DB1 45/ 8B C2 mov r8d, r10d \n"
" 00004DB4 4D/ 8B C2 mov r8, r10 \n"
" \n"
" 00004DB7 45/ 8A 42 FC mov r8b, byte ptr [r10 - 4] \n"
" 00004DBB 45/ 8A 42 04 mov r8b, byte ptr [r10 + 4] \n"
" 00004DBF 66| 45/ 8B 42 mov r8w, word ptr [r10 + 4] \n"
" 04 \n"
" 00004DC4 45/ 8B 42 04 mov r8d, dword ptr [r10 + 4] \n"
" 00004DC8 4D/ 8B 42 04 mov r8, qword ptr [r10 + 4] \n"
" \n"
" 00004DCC 45/ 88 50 FC mov byte ptr [r8 - 4], r10b \n"
" 00004DD0 45/ 88 50 04 mov byte ptr [r8 + 4], r10b \n"
" 00004DD4 66| 45/ 89 50 mov word ptr [r8 + 4], r10w \n"
" 04 \n"
" 00004DD9 45/ 89 50 04 mov dword ptr [r8 + 4], r10d \n"
" 00004DDD 4D/ 89 50 04 mov qword ptr [r8 + 4], r10 \n"
" \n"
" 00004DE1 66| 45/ 0F B6 C2 movzx r8w, r10b \n"
" 00004DE6 66| 45/ 0F B6 42 movzx r8w, byte ptr [r10 + 4] \n"
" 04 \n"
" \n"
" 00004DEC 45/ 0F B6 C2 movzx r8d, r10b \n"
" 00004DF0 45/ 0F B7 C2 movzx r8d, r10w \n"
" 00004DF4 45/ 0F B6 42 movzx r8d, byte ptr [r10 + 4] \n"
" 04 \n"
" 00004DF9 45/ 0F B7 42 movzx r8d, word ptr [r10 + 4] \n"
" 04 \n"
" \n"
" 00004DFE 4D/ 0F B6 C2 movzx r8, r10b \n"
" 00004E02 4D/ 0F B7 C2 movzx r8, r10w \n"
" 00004E06 4D/ 0F B6 42 movzx r8, byte ptr [r10 + 4] \n"
" 04 \n"
" 00004E0B 4D/ 0F B7 42 movzx r8, word ptr [r10 + 4] \n"
" 04 \n"
" \n"
" \n"
" ; Source: r10, target: r9 \n"
" 00004E10 41/ B1 01 mov r9b, 1 \n"
" 00004E13 66| 41/ B9 mov r9w, 1 \n"
" 0001 \n"
" 00004E18 41/ B9 mov r9d, 1 \n"
" 00000001 \n"
" 00004E1E 49/ C7 C1 mov r9, 1 \n"
" 00000001 \n"
" \n"
" 00004E25 45/ 8A CA mov r9b, r10b \n"
" 00004E28 66| 45/ 8B CA mov r9w, r10w \n"
" 00004E2C 45/ 8B CA mov r9d, r10d \n"
" 00004E2F 4D/ 8B CA mov r9, r10 \n"
" \n"
" 00004E32 45/ 8A 4A FC mov r9b, byte ptr [r10 - 4] \n"
" 00004E36 45/ 8A 4A 04 mov r9b, byte ptr [r10 + 4] \n"
" 00004E3A 66| 45/ 8B 4A mov r9w, word ptr [r10 + 4] \n"
" 04 \n"
" 00004E3F 45/ 8B 4A 04 mov r9d, dword ptr [r10 + 4] \n"
" 00004E43 4D/ 8B 4A 04 mov r9, qword ptr [r10 + 4] \n"
" \n"
" 00004E47 45/ 88 51 FC mov byte ptr [r9 - 4], r10b \n"
" 00004E4B 45/ 88 51 04 mov byte ptr [r9 + 4], r10b \n"
" 00004E4F 66| 45/ 89 51 mov word ptr [r9 + 4], r10w \n"
" 04 \n"
" 00004E54 45/ 89 51 04 mov dword ptr [r9 + 4], r10d \n"
" 00004E58 4D/ 89 51 04 mov qword ptr [r9 + 4], r10 \n"
" \n"
" 00004E5C 66| 45/ 0F B6 CA movzx r9w, r10b \n"
" 00004E61 66| 45/ 0F B6 4A movzx r9w, byte ptr [r10 + 4] \n"
" 04 \n"
" \n"
" 00004E67 45/ 0F B6 CA movzx r9d, r10b \n"
" 00004E6B 45/ 0F B7 CA movzx r9d, r10w \n"
" 00004E6F 45/ 0F B6 4A movzx r9d, byte ptr [r10 + 4] \n"
" 04 \n"
" 00004E74 45/ 0F B7 4A movzx r9d, word ptr [r10 + 4] \n"
" 04 \n"
" \n"
" 00004E79 4D/ 0F B6 CA movzx r9, r10b \n"
" 00004E7D 4D/ 0F B7 CA movzx r9, r10w \n"
" 00004E81 4D/ 0F B6 4A movzx r9, byte ptr [r10 + 4] \n"
" 04 \n"
" 00004E86 4D/ 0F B7 4A movzx r9, word ptr [r10 + 4] \n"
" 04 \n"
" \n"
" \n";
ml64Output +=
" ; Source: r10, target: r10 \n"
" 00004E8B 41/ B2 01 mov r10b, 1 \n"
" 00004E8E 66| 41/ BA mov r10w, 1 \n"
" 0001 \n"
" 00004E93 41/ BA mov r10d, 1 \n"
" 00000001 \n"
" 00004E99 49/ C7 C2 mov r10, 1 \n"
" 00000001 \n"
" \n"
" 00004EA0 45/ 8A D2 mov r10b, r10b \n"
" 00004EA3 66| 45/ 8B D2 mov r10w, r10w \n"
" 00004EA7 45/ 8B D2 mov r10d, r10d \n"
" 00004EAA 4D/ 8B D2 mov r10, r10 \n"
" \n"
" 00004EAD 45/ 8A 52 FC mov r10b, byte ptr [r10 - 4] \n"
" 00004EB1 45/ 8A 52 04 mov r10b, byte ptr [r10 + 4] \n"
" 00004EB5 66| 45/ 8B 52 mov r10w, word ptr [r10 + 4] \n"
" 04 \n"
" 00004EBA 45/ 8B 52 04 mov r10d, dword ptr [r10 + 4] \n"
" 00004EBE 4D/ 8B 52 04 mov r10, qword ptr [r10 + 4] \n"
" \n"
" 00004EC2 45/ 88 52 FC mov byte ptr [r10 - 4], r10b \n"
" 00004EC6 45/ 88 52 04 mov byte ptr [r10 + 4], r10b \n"
" 00004ECA 66| 45/ 89 52 mov word ptr [r10 + 4], r10w \n"
" 04 \n"
" 00004ECF 45/ 89 52 04 mov dword ptr [r10 + 4], r10d \n"
" 00004ED3 4D/ 89 52 04 mov qword ptr [r10 + 4], r10 \n"
" \n"
" 00004ED7 66| 45/ 0F B6 D2 movzx r10w, r10b \n"
" 00004EDC 66| 45/ 0F B6 52 movzx r10w, byte ptr [r10 + 4] \n"
" 04 \n"
" \n"
" 00004EE2 45/ 0F B6 D2 movzx r10d, r10b \n"
" 00004EE6 45/ 0F B7 D2 movzx r10d, r10w \n"
" 00004EEA 45/ 0F B6 52 movzx r10d, byte ptr [r10 + 4] \n"
" 04 \n"
" 00004EEF 45/ 0F B7 52 movzx r10d, word ptr [r10 + 4] \n"
" 04 \n"
" \n"
" 00004EF4 4D/ 0F B6 D2 movzx r10, r10b \n"
" 00004EF8 4D/ 0F B7 D2 movzx r10, r10w \n"
" 00004EFC 4D/ 0F B6 52 movzx r10, byte ptr [r10 + 4] \n"
" 04 \n"
" 00004F01 4D/ 0F B7 52 movzx r10, word ptr [r10 + 4] \n"
" 04 \n"
" \n"
" \n"
" ; Source: r10, target: r11 \n"
" 00004F06 41/ B3 01 mov r11b, 1 \n"
" 00004F09 66| 41/ BB mov r11w, 1 \n"
" 0001 \n"
" 00004F0E 41/ BB mov r11d, 1 \n"
" 00000001 \n"
" 00004F14 49/ C7 C3 mov r11, 1 \n"
" 00000001 \n"
" \n"
" 00004F1B 45/ 8A DA mov r11b, r10b \n"
" 00004F1E 66| 45/ 8B DA mov r11w, r10w \n"
" 00004F22 45/ 8B DA mov r11d, r10d \n"
" 00004F25 4D/ 8B DA mov r11, r10 \n"
" \n"
" 00004F28 45/ 8A 5A FC mov r11b, byte ptr [r10 - 4] \n"
" 00004F2C 45/ 8A 5A 04 mov r11b, byte ptr [r10 + 4] \n"
" 00004F30 66| 45/ 8B 5A mov r11w, word ptr [r10 + 4] \n"
" 04 \n"
" 00004F35 45/ 8B 5A 04 mov r11d, dword ptr [r10 + 4] \n"
" 00004F39 4D/ 8B 5A 04 mov r11, qword ptr [r10 + 4] \n"
" \n"
" 00004F3D 45/ 88 53 FC mov byte ptr [r11 - 4], r10b \n"
" 00004F41 45/ 88 53 04 mov byte ptr [r11 + 4], r10b \n"
" 00004F45 66| 45/ 89 53 mov word ptr [r11 + 4], r10w \n"
" 04 \n"
" 00004F4A 45/ 89 53 04 mov dword ptr [r11 + 4], r10d \n"
" 00004F4E 4D/ 89 53 04 mov qword ptr [r11 + 4], r10 \n"
" \n"
" 00004F52 66| 45/ 0F B6 DA movzx r11w, r10b \n"
" 00004F57 66| 45/ 0F B6 5A movzx r11w, byte ptr [r10 + 4] \n"
" 04 \n"
" \n"
" 00004F5D 45/ 0F B6 DA movzx r11d, r10b \n"
" 00004F61 45/ 0F B7 DA movzx r11d, r10w \n"
" 00004F65 45/ 0F B6 5A movzx r11d, byte ptr [r10 + 4] \n"
" 04 \n"
" 00004F6A 45/ 0F B7 5A movzx r11d, word ptr [r10 + 4] \n"
" 04 \n"
" \n"
" 00004F6F 4D/ 0F B6 DA movzx r11, r10b \n"
" 00004F73 4D/ 0F B7 DA movzx r11, r10w \n"
" 00004F77 4D/ 0F B6 5A movzx r11, byte ptr [r10 + 4] \n"
" 04 \n"
" 00004F7C 4D/ 0F B7 5A movzx r11, word ptr [r10 + 4] \n"
" 04 \n"
" \n"
" \n"
" ; Source: r10, target: r12 \n"
" 00004F81 41/ B4 01 mov r12b, 1 \n"
" 00004F84 66| 41/ BC mov r12w, 1 \n"
" 0001 \n"
" 00004F89 41/ BC mov r12d, 1 \n"
" 00000001 \n"
" 00004F8F 49/ C7 C4 mov r12, 1 \n"
" 00000001 \n"
" \n"
" 00004F96 45/ 8A E2 mov r12b, r10b \n"
" 00004F99 66| 45/ 8B E2 mov r12w, r10w \n"
" 00004F9D 45/ 8B E2 mov r12d, r10d \n"
" 00004FA0 4D/ 8B E2 mov r12, r10 \n"
" \n"
" 00004FA3 45/ 8A 62 FC mov r12b, byte ptr [r10 - 4] \n"
" 00004FA7 45/ 8A 62 04 mov r12b, byte ptr [r10 + 4] \n"
" 00004FAB 66| 45/ 8B 62 mov r12w, word ptr [r10 + 4] \n"
" 04 \n"
" 00004FB0 45/ 8B 62 04 mov r12d, dword ptr [r10 + 4] \n"
" 00004FB4 4D/ 8B 62 04 mov r12, qword ptr [r10 + 4] \n"
" \n"
" 00004FB8 45/ 88 54 24 mov byte ptr [r12 - 4], r10b \n"
" FC \n"
" 00004FBD 45/ 88 54 24 mov byte ptr [r12 + 4], r10b \n"
" 04 \n"
" 00004FC2 66| 45/ 89 54 24 mov word ptr [r12 + 4], r10w \n"
" 04 \n"
" 00004FC8 45/ 89 54 24 mov dword ptr [r12 + 4], r10d \n"
" 04 \n"
" 00004FCD 4D/ 89 54 24 mov qword ptr [r12 + 4], r10 \n"
" 04 \n"
" \n"
" 00004FD2 66| 45/ 0F B6 E2 movzx r12w, r10b \n"
" 00004FD7 66| 45/ 0F B6 62 movzx r12w, byte ptr [r10 + 4] \n"
" 04 \n"
" \n"
" 00004FDD 45/ 0F B6 E2 movzx r12d, r10b \n"
" 00004FE1 45/ 0F B7 E2 movzx r12d, r10w \n"
" 00004FE5 45/ 0F B6 62 movzx r12d, byte ptr [r10 + 4] \n"
" 04 \n"
" 00004FEA 45/ 0F B7 62 movzx r12d, word ptr [r10 + 4] \n"
" 04 \n"
" \n"
" 00004FEF 4D/ 0F B6 E2 movzx r12, r10b \n"
" 00004FF3 4D/ 0F B7 E2 movzx r12, r10w \n"
" 00004FF7 4D/ 0F B6 62 movzx r12, byte ptr [r10 + 4] \n"
" 04 \n"
" 00004FFC 4D/ 0F B7 62 movzx r12, word ptr [r10 + 4] \n"
" 04 \n"
" \n"
" \n"
" ; Source: r10, target: r13 \n"
" 00005001 41/ B5 01 mov r13b, 1 \n"
" 00005004 66| 41/ BD mov r13w, 1 \n"
" 0001 \n"
" 00005009 41/ BD mov r13d, 1 \n"
" 00000001 \n"
" 0000500F 49/ C7 C5 mov r13, 1 \n"
" 00000001 \n"
" \n"
" 00005016 45/ 8A EA mov r13b, r10b \n"
" 00005019 66| 45/ 8B EA mov r13w, r10w \n"
" 0000501D 45/ 8B EA mov r13d, r10d \n"
" 00005020 4D/ 8B EA mov r13, r10 \n"
" \n"
" 00005023 45/ 8A 6A FC mov r13b, byte ptr [r10 - 4] \n"
" 00005027 45/ 8A 6A 04 mov r13b, byte ptr [r10 + 4] \n"
" 0000502B 66| 45/ 8B 6A mov r13w, word ptr [r10 + 4] \n"
" 04 \n"
" 00005030 45/ 8B 6A 04 mov r13d, dword ptr [r10 + 4] \n"
" 00005034 4D/ 8B 6A 04 mov r13, qword ptr [r10 + 4] \n"
" \n"
" 00005038 45/ 88 55 FC mov byte ptr [r13 - 4], r10b \n"
" 0000503C 45/ 88 55 04 mov byte ptr [r13 + 4], r10b \n"
" 00005040 66| 45/ 89 55 mov word ptr [r13 + 4], r10w \n"
" 04 \n"
" 00005045 45/ 89 55 04 mov dword ptr [r13 + 4], r10d \n"
" 00005049 4D/ 89 55 04 mov qword ptr [r13 + 4], r10 \n"
" \n"
" 0000504D 66| 45/ 0F B6 EA movzx r13w, r10b \n"
" 00005052 66| 45/ 0F B6 6A movzx r13w, byte ptr [r10 + 4] \n"
" 04 \n"
" \n"
" 00005058 45/ 0F B6 EA movzx r13d, r10b \n"
" 0000505C 45/ 0F B7 EA movzx r13d, r10w \n"
" 00005060 45/ 0F B6 6A movzx r13d, byte ptr [r10 + 4] \n"
" 04 \n"
" 00005065 45/ 0F B7 6A movzx r13d, word ptr [r10 + 4] \n"
" 04 \n"
" \n"
" 0000506A 4D/ 0F B6 EA movzx r13, r10b \n"
" 0000506E 4D/ 0F B7 EA movzx r13, r10w \n"
" 00005072 4D/ 0F B6 6A movzx r13, byte ptr [r10 + 4] \n"
" 04 \n"
" 00005077 4D/ 0F B7 6A movzx r13, word ptr [r10 + 4] \n"
" 04 \n"
" \n"
" \n"
" ; Source: r10, target: r14 \n"
" 0000507C 41/ B6 01 mov r14b, 1 \n"
" 0000507F 66| 41/ BE mov r14w, 1 \n"
" 0001 \n"
" 00005084 41/ BE mov r14d, 1 \n"
" 00000001 \n"
" 0000508A 49/ C7 C6 mov r14, 1 \n"
" 00000001 \n"
" \n"
" 00005091 45/ 8A F2 mov r14b, r10b \n"
" 00005094 66| 45/ 8B F2 mov r14w, r10w \n"
" 00005098 45/ 8B F2 mov r14d, r10d \n"
" 0000509B 4D/ 8B F2 mov r14, r10 \n"
" \n"
" 0000509E 45/ 8A 72 FC mov r14b, byte ptr [r10 - 4] \n"
" 000050A2 45/ 8A 72 04 mov r14b, byte ptr [r10 + 4] \n"
" 000050A6 66| 45/ 8B 72 mov r14w, word ptr [r10 + 4] \n"
" 04 \n"
" 000050AB 45/ 8B 72 04 mov r14d, dword ptr [r10 + 4] \n"
" 000050AF 4D/ 8B 72 04 mov r14, qword ptr [r10 + 4] \n"
" \n"
" 000050B3 45/ 88 56 FC mov byte ptr [r14 - 4], r10b \n"
" 000050B7 45/ 88 56 04 mov byte ptr [r14 + 4], r10b \n"
" 000050BB 66| 45/ 89 56 mov word ptr [r14 + 4], r10w \n"
" 04 \n"
" 000050C0 45/ 89 56 04 mov dword ptr [r14 + 4], r10d \n"
" 000050C4 4D/ 89 56 04 mov qword ptr [r14 + 4], r10 \n"
" \n"
" 000050C8 66| 45/ 0F B6 F2 movzx r14w, r10b \n"
" 000050CD 66| 45/ 0F B6 72 movzx r14w, byte ptr [r10 + 4] \n"
" 04 \n"
" \n"
" 000050D3 45/ 0F B6 F2 movzx r14d, r10b \n"
" 000050D7 45/ 0F B7 F2 movzx r14d, r10w \n"
" 000050DB 45/ 0F B6 72 movzx r14d, byte ptr [r10 + 4] \n"
" 04 \n"
" 000050E0 45/ 0F B7 72 movzx r14d, word ptr [r10 + 4] \n"
" 04 \n"
" \n"
" 000050E5 4D/ 0F B6 F2 movzx r14, r10b \n"
" 000050E9 4D/ 0F B7 F2 movzx r14, r10w \n"
" 000050ED 4D/ 0F B6 72 movzx r14, byte ptr [r10 + 4] \n"
" 04 \n"
" 000050F2 4D/ 0F B7 72 movzx r14, word ptr [r10 + 4] \n"
" 04 \n"
" \n"
" \n"
" ; Source: r10, target: r15 \n"
" 000050F7 41/ B7 01 mov r15b, 1 \n"
" 000050FA 66| 41/ BF mov r15w, 1 \n"
" 0001 \n"
" 000050FF 41/ BF mov r15d, 1 \n"
" 00000001 \n"
" 00005105 49/ C7 C7 mov r15, 1 \n"
" 00000001 \n"
" \n"
" 0000510C 45/ 8A FA mov r15b, r10b \n"
" 0000510F 66| 45/ 8B FA mov r15w, r10w \n"
" 00005113 45/ 8B FA mov r15d, r10d \n"
" 00005116 4D/ 8B FA mov r15, r10 \n"
" \n"
" 00005119 45/ 8A 7A FC mov r15b, byte ptr [r10 - 4] \n"
" 0000511D 45/ 8A 7A 04 mov r15b, byte ptr [r10 + 4] \n"
" 00005121 66| 45/ 8B 7A mov r15w, word ptr [r10 + 4] \n"
" 04 \n"
" 00005126 45/ 8B 7A 04 mov r15d, dword ptr [r10 + 4] \n"
" 0000512A 4D/ 8B 7A 04 mov r15, qword ptr [r10 + 4] \n"
" \n"
" 0000512E 45/ 88 57 FC mov byte ptr [r15 - 4], r10b \n"
" 00005132 45/ 88 57 04 mov byte ptr [r15 + 4], r10b \n"
" 00005136 66| 45/ 89 57 mov word ptr [r15 + 4], r10w \n"
" 04 \n"
" 0000513B 45/ 89 57 04 mov dword ptr [r15 + 4], r10d \n"
" 0000513F 4D/ 89 57 04 mov qword ptr [r15 + 4], r10 \n"
" \n"
" 00005143 66| 45/ 0F B6 FA movzx r15w, r10b \n"
" 00005148 66| 45/ 0F B6 7A movzx r15w, byte ptr [r10 + 4] \n"
" 04 \n"
" \n"
" 0000514E 45/ 0F B6 FA movzx r15d, r10b \n"
" 00005152 45/ 0F B7 FA movzx r15d, r10w \n"
" 00005156 45/ 0F B6 7A movzx r15d, byte ptr [r10 + 4] \n"
" 04 \n"
" 0000515B 45/ 0F B7 7A movzx r15d, word ptr [r10 + 4] \n"
" 04 \n"
" \n"
" 00005160 4D/ 0F B6 FA movzx r15, r10b \n"
" 00005164 4D/ 0F B7 FA movzx r15, r10w \n"
" 00005168 4D/ 0F B6 7A movzx r15, byte ptr [r10 + 4] \n"
" 04 \n"
" 0000516D 4D/ 0F B7 7A movzx r15, word ptr [r10 + 4] \n"
" 04 \n"
" \n"
" \n"
" ; Source: r11, target: rax \n"
" 00005172 B0 01 mov al, 1 \n"
" 00005174 66| B8 0001 mov ax, 1 \n"
" 00005178 B8 00000001 mov eax, 1 \n"
" 0000517D 48/ C7 C0 mov rax, 1 \n"
" 00000001 \n"
" \n"
" 00005184 41/ 8A C3 mov al, r11b \n"
" 00005187 66| 41/ 8B C3 mov ax, r11w \n"
" 0000518B 41/ 8B C3 mov eax, r11d \n"
" 0000518E 49/ 8B C3 mov rax, r11 \n"
" \n"
" 00005191 41/ 8A 43 FC mov al, byte ptr [r11 - 4] \n"
" 00005195 41/ 8A 43 04 mov al, byte ptr [r11 + 4] \n"
" 00005199 66| 41/ 8B 43 mov ax, word ptr [r11 + 4] \n"
" 04 \n"
" 0000519E 41/ 8B 43 04 mov eax, dword ptr [r11 + 4] \n"
" 000051A2 49/ 8B 43 04 mov rax, qword ptr [r11 + 4] \n"
" \n"
" 000051A6 44/ 88 58 FC mov byte ptr [rax - 4], r11b \n"
" 000051AA 44/ 88 58 04 mov byte ptr [rax + 4], r11b \n"
" 000051AE 66| 44/ 89 58 mov word ptr [rax + 4], r11w \n"
" 04 \n"
" 000051B3 44/ 89 58 04 mov dword ptr [rax + 4], r11d \n"
" 000051B7 4C/ 89 58 04 mov qword ptr [rax + 4], r11 \n"
" \n"
" 000051BB 66| 41/ 0F B6 C3 movzx ax, r11b \n"
" 000051C0 66| 41/ 0F B6 43 movzx ax, byte ptr [r11 + 4] \n"
" 04 \n"
" \n"
" 000051C6 41/ 0F B6 C3 movzx eax, r11b \n"
" 000051CA 41/ 0F B7 C3 movzx eax, r11w \n"
" 000051CE 41/ 0F B6 43 movzx eax, byte ptr [r11 + 4] \n"
" 04 \n"
" 000051D3 41/ 0F B7 43 movzx eax, word ptr [r11 + 4] \n"
" 04 \n"
" \n"
" 000051D8 49/ 0F B6 C3 movzx rax, r11b \n"
" 000051DC 49/ 0F B7 C3 movzx rax, r11w \n"
" 000051E0 49/ 0F B6 43 movzx rax, byte ptr [r11 + 4] \n"
" 04 \n"
" 000051E5 49/ 0F B7 43 movzx rax, word ptr [r11 + 4] \n"
" 04 \n"
" \n"
" \n"
" ; Source: r11, target: rcx \n"
" 000051EA B1 01 mov cl, 1 \n"
" 000051EC 66| B9 0001 mov cx, 1 \n"
" 000051F0 B9 00000001 mov ecx, 1 \n"
" 000051F5 48/ C7 C1 mov rcx, 1 \n"
" 00000001 \n"
" \n"
" 000051FC 41/ 8A CB mov cl, r11b \n"
" 000051FF 66| 41/ 8B CB mov cx, r11w \n"
" 00005203 41/ 8B CB mov ecx, r11d \n"
" 00005206 49/ 8B CB mov rcx, r11 \n"
" \n"
" 00005209 41/ 8A 4B FC mov cl, byte ptr [r11 - 4] \n"
" 0000520D 41/ 8A 4B 04 mov cl, byte ptr [r11 + 4] \n"
" 00005211 66| 41/ 8B 4B mov cx, word ptr [r11 + 4] \n"
" 04 \n"
" 00005216 41/ 8B 4B 04 mov ecx, dword ptr [r11 + 4] \n"
" 0000521A 49/ 8B 4B 04 mov rcx, qword ptr [r11 + 4] \n"
" \n"
" 0000521E 44/ 88 59 FC mov byte ptr [rcx - 4], r11b \n"
" 00005222 44/ 88 59 04 mov byte ptr [rcx + 4], r11b \n"
" 00005226 66| 44/ 89 59 mov word ptr [rcx + 4], r11w \n"
" 04 \n"
" 0000522B 44/ 89 59 04 mov dword ptr [rcx + 4], r11d \n"
" 0000522F 4C/ 89 59 04 mov qword ptr [rcx + 4], r11 \n"
" \n"
" 00005233 66| 41/ 0F B6 CB movzx cx, r11b \n"
" 00005238 66| 41/ 0F B6 4B movzx cx, byte ptr [r11 + 4] \n"
" 04 \n"
" \n"
" 0000523E 41/ 0F B6 CB movzx ecx, r11b \n"
" 00005242 41/ 0F B7 CB movzx ecx, r11w \n"
" 00005246 41/ 0F B6 4B movzx ecx, byte ptr [r11 + 4] \n"
" 04 \n"
" 0000524B 41/ 0F B7 4B movzx ecx, word ptr [r11 + 4] \n"
" 04 \n"
" \n"
" 00005250 49/ 0F B6 CB movzx rcx, r11b \n"
" 00005254 49/ 0F B7 CB movzx rcx, r11w \n"
" 00005258 49/ 0F B6 4B movzx rcx, byte ptr [r11 + 4] \n"
" 04 \n"
" 0000525D 49/ 0F B7 4B movzx rcx, word ptr [r11 + 4] \n"
" 04 \n"
" \n"
" \n"
" ; Source: r11, target: rdx \n"
" 00005262 B2 01 mov dl, 1 \n"
" 00005264 66| BA 0001 mov dx, 1 \n"
" 00005268 BA 00000001 mov edx, 1 \n"
" 0000526D 48/ C7 C2 mov rdx, 1 \n"
" 00000001 \n"
" \n"
" 00005274 41/ 8A D3 mov dl, r11b \n"
" 00005277 66| 41/ 8B D3 mov dx, r11w \n"
" 0000527B 41/ 8B D3 mov edx, r11d \n"
" 0000527E 49/ 8B D3 mov rdx, r11 \n"
" \n"
" 00005281 41/ 8A 53 FC mov dl, byte ptr [r11 - 4] \n"
" 00005285 41/ 8A 53 04 mov dl, byte ptr [r11 + 4] \n"
" 00005289 66| 41/ 8B 53 mov dx, word ptr [r11 + 4] \n"
" 04 \n"
" 0000528E 41/ 8B 53 04 mov edx, dword ptr [r11 + 4] \n"
" 00005292 49/ 8B 53 04 mov rdx, qword ptr [r11 + 4] \n"
" \n"
" 00005296 44/ 88 5A FC mov byte ptr [rdx - 4], r11b \n"
" 0000529A 44/ 88 5A 04 mov byte ptr [rdx + 4], r11b \n"
" 0000529E 66| 44/ 89 5A mov word ptr [rdx + 4], r11w \n"
" 04 \n"
" 000052A3 44/ 89 5A 04 mov dword ptr [rdx + 4], r11d \n"
" 000052A7 4C/ 89 5A 04 mov qword ptr [rdx + 4], r11 \n"
" \n"
" 000052AB 66| 41/ 0F B6 D3 movzx dx, r11b \n"
" 000052B0 66| 41/ 0F B6 53 movzx dx, byte ptr [r11 + 4] \n"
" 04 \n"
" \n"
" 000052B6 41/ 0F B6 D3 movzx edx, r11b \n"
" 000052BA 41/ 0F B7 D3 movzx edx, r11w \n"
" 000052BE 41/ 0F B6 53 movzx edx, byte ptr [r11 + 4] \n"
" 04 \n"
" 000052C3 41/ 0F B7 53 movzx edx, word ptr [r11 + 4] \n"
" 04 \n"
" \n"
" 000052C8 49/ 0F B6 D3 movzx rdx, r11b \n"
" 000052CC 49/ 0F B7 D3 movzx rdx, r11w \n"
" 000052D0 49/ 0F B6 53 movzx rdx, byte ptr [r11 + 4] \n"
" 04 \n"
" 000052D5 49/ 0F B7 53 movzx rdx, word ptr [r11 + 4] \n"
" 04 \n"
" \n"
" \n"
" ; Source: r11, target: rbx \n"
" 000052DA B3 01 mov bl, 1 \n"
" 000052DC 66| BB 0001 mov bx, 1 \n"
" 000052E0 BB 00000001 mov ebx, 1 \n"
" 000052E5 48/ C7 C3 mov rbx, 1 \n"
" 00000001 \n"
" \n"
" 000052EC 41/ 8A DB mov bl, r11b \n"
" 000052EF 66| 41/ 8B DB mov bx, r11w \n"
" 000052F3 41/ 8B DB mov ebx, r11d \n"
" 000052F6 49/ 8B DB mov rbx, r11 \n"
" \n"
" 000052F9 41/ 8A 5B FC mov bl, byte ptr [r11 - 4] \n"
" 000052FD 41/ 8A 5B 04 mov bl, byte ptr [r11 + 4] \n"
" 00005301 66| 41/ 8B 5B mov bx, word ptr [r11 + 4] \n"
" 04 \n"
" 00005306 41/ 8B 5B 04 mov ebx, dword ptr [r11 + 4] \n"
" 0000530A 49/ 8B 5B 04 mov rbx, qword ptr [r11 + 4] \n"
" \n"
" 0000530E 44/ 88 5B FC mov byte ptr [rbx - 4], r11b \n"
" 00005312 44/ 88 5B 04 mov byte ptr [rbx + 4], r11b \n"
" 00005316 66| 44/ 89 5B mov word ptr [rbx + 4], r11w \n"
" 04 \n"
" 0000531B 44/ 89 5B 04 mov dword ptr [rbx + 4], r11d \n"
" 0000531F 4C/ 89 5B 04 mov qword ptr [rbx + 4], r11 \n"
" \n"
" 00005323 66| 41/ 0F B6 DB movzx bx, r11b \n"
" 00005328 66| 41/ 0F B6 5B movzx bx, byte ptr [r11 + 4] \n"
" 04 \n"
" \n"
" 0000532E 41/ 0F B6 DB movzx ebx, r11b \n"
" 00005332 41/ 0F B7 DB movzx ebx, r11w \n"
" 00005336 41/ 0F B6 5B movzx ebx, byte ptr [r11 + 4] \n"
" 04 \n"
" 0000533B 41/ 0F B7 5B movzx ebx, word ptr [r11 + 4] \n"
" 04 \n"
" \n"
" 00005340 49/ 0F B6 DB movzx rbx, r11b \n"
" 00005344 49/ 0F B7 DB movzx rbx, r11w \n"
" 00005348 49/ 0F B6 5B movzx rbx, byte ptr [r11 + 4] \n"
" 04 \n"
" 0000534D 49/ 0F B7 5B movzx rbx, word ptr [r11 + 4] \n"
" 04 \n"
" \n"
" \n"
" ; Source: r11, target: rsp \n"
" 00005352 40/ B4 01 mov spl, 1 \n"
" 00005355 66| BC 0001 mov sp, 1 \n"
" 00005359 BC 00000001 mov esp, 1 \n"
" 0000535E 48/ C7 C4 mov rsp, 1 \n"
" 00000001 \n"
" \n"
" 00005365 41/ 8A E3 mov spl, r11b \n"
" 00005368 66| 41/ 8B E3 mov sp, r11w \n"
" 0000536C 41/ 8B E3 mov esp, r11d \n"
" 0000536F 49/ 8B E3 mov rsp, r11 \n"
" \n"
" 00005372 41/ 8A 63 FC mov spl, byte ptr [r11 - 4] \n"
" 00005376 41/ 8A 63 04 mov spl, byte ptr [r11 + 4] \n"
" 0000537A 66| 41/ 8B 63 mov sp, word ptr [r11 + 4] \n"
" 04 \n"
" 0000537F 41/ 8B 63 04 mov esp, dword ptr [r11 + 4] \n"
" 00005383 49/ 8B 63 04 mov rsp, qword ptr [r11 + 4] \n"
" \n"
" 00005387 44/ 88 5C 24 mov byte ptr [rsp - 4], r11b \n"
" FC \n"
" 0000538C 44/ 88 5C 24 mov byte ptr [rsp + 4], r11b \n"
" 04 \n"
" 00005391 66| 44/ 89 5C 24 mov word ptr [rsp + 4], r11w \n"
" 04 \n"
" 00005397 44/ 89 5C 24 mov dword ptr [rsp + 4], r11d \n"
" 04 \n"
" 0000539C 4C/ 89 5C 24 mov qword ptr [rsp + 4], r11 \n"
" 04 \n"
" \n"
" 000053A1 66| 41/ 0F B6 E3 movzx sp, r11b \n"
" 000053A6 66| 41/ 0F B6 63 movzx sp, byte ptr [r11 + 4] \n"
" 04 \n"
" \n"
" 000053AC 41/ 0F B6 E3 movzx esp, r11b \n"
" 000053B0 41/ 0F B7 E3 movzx esp, r11w \n"
" 000053B4 41/ 0F B6 63 movzx esp, byte ptr [r11 + 4] \n"
" 04 \n"
" 000053B9 41/ 0F B7 63 movzx esp, word ptr [r11 + 4] \n"
" 04 \n"
" \n"
" 000053BE 49/ 0F B6 E3 movzx rsp, r11b \n"
" 000053C2 49/ 0F B7 E3 movzx rsp, r11w \n"
" 000053C6 49/ 0F B6 63 movzx rsp, byte ptr [r11 + 4] \n"
" 04 \n"
" 000053CB 49/ 0F B7 63 movzx rsp, word ptr [r11 + 4] \n"
" 04 \n"
" \n"
" \n"
" ; Source: r11, target: rbp \n"
" 000053D0 40/ B5 01 mov bpl, 1 \n"
" 000053D3 66| BD 0001 mov bp, 1 \n"
" 000053D7 BD 00000001 mov ebp, 1 \n"
" 000053DC 48/ C7 C5 mov rbp, 1 \n"
" 00000001 \n"
" \n"
" 000053E3 41/ 8A EB mov bpl, r11b \n"
" 000053E6 66| 41/ 8B EB mov bp, r11w \n"
" 000053EA 41/ 8B EB mov ebp, r11d \n"
" 000053ED 49/ 8B EB mov rbp, r11 \n"
" \n"
" 000053F0 41/ 8A 6B FC mov bpl, byte ptr [r11 - 4] \n"
" 000053F4 41/ 8A 6B 04 mov bpl, byte ptr [r11 + 4] \n"
" 000053F8 66| 41/ 8B 6B mov bp, word ptr [r11 + 4] \n"
" 04 \n"
" 000053FD 41/ 8B 6B 04 mov ebp, dword ptr [r11 + 4] \n"
" 00005401 49/ 8B 6B 04 mov rbp, qword ptr [r11 + 4] \n"
" \n"
" 00005405 44/ 88 5D FC mov byte ptr [rbp - 4], r11b \n"
" 00005409 44/ 88 5D 04 mov byte ptr [rbp + 4], r11b \n"
" 0000540D 66| 44/ 89 5D mov word ptr [rbp + 4], r11w \n"
" 04 \n"
" 00005412 44/ 89 5D 04 mov dword ptr [rbp + 4], r11d \n"
" 00005416 4C/ 89 5D 04 mov qword ptr [rbp + 4], r11 \n"
" \n"
" 0000541A 66| 41/ 0F B6 EB movzx bp, r11b \n"
" 0000541F 66| 41/ 0F B6 6B movzx bp, byte ptr [r11 + 4] \n"
" 04 \n"
" \n"
" 00005425 41/ 0F B6 EB movzx ebp, r11b \n"
" 00005429 41/ 0F B7 EB movzx ebp, r11w \n"
" 0000542D 41/ 0F B6 6B movzx ebp, byte ptr [r11 + 4] \n"
" 04 \n"
" 00005432 41/ 0F B7 6B movzx ebp, word ptr [r11 + 4] \n";
ml64Output +=
" 04 \n"
" \n"
" 00005437 49/ 0F B6 EB movzx rbp, r11b \n"
" 0000543B 49/ 0F B7 EB movzx rbp, r11w \n"
" 0000543F 49/ 0F B6 6B movzx rbp, byte ptr [r11 + 4] \n"
" 04 \n"
" 00005444 49/ 0F B7 6B movzx rbp, word ptr [r11 + 4] \n"
" 04 \n"
" \n"
" \n"
" ; Source: r11, target: rsi \n"
" 00005449 40/ B7 01 mov dil, 1 \n"
" 0000544C 66| BE 0001 mov si, 1 \n"
" 00005450 BE 00000001 mov esi, 1 \n"
" 00005455 48/ C7 C6 mov rsi, 1 \n"
" 00000001 \n"
" \n"
" 0000545C 41/ 8A FB mov dil, r11b \n"
" 0000545F 66| 41/ 8B F3 mov si, r11w \n"
" 00005463 41/ 8B F3 mov esi, r11d \n"
" 00005466 49/ 8B F3 mov rsi, r11 \n"
" \n"
" 00005469 41/ 8A 7B FC mov dil, byte ptr [r11 - 4] \n"
" 0000546D 41/ 8A 7B 04 mov dil, byte ptr [r11 + 4] \n"
" 00005471 66| 41/ 8B 73 mov si, word ptr [r11 + 4] \n"
" 04 \n"
" 00005476 41/ 8B 73 04 mov esi, dword ptr [r11 + 4] \n"
" 0000547A 49/ 8B 73 04 mov rsi, qword ptr [r11 + 4] \n"
" \n"
" 0000547E 44/ 88 5E FC mov byte ptr [rsi - 4], r11b \n"
" 00005482 44/ 88 5E 04 mov byte ptr [rsi + 4], r11b \n"
" 00005486 66| 44/ 89 5E mov word ptr [rsi + 4], r11w \n"
" 04 \n"
" 0000548B 44/ 89 5E 04 mov dword ptr [rsi + 4], r11d \n"
" 0000548F 4C/ 89 5E 04 mov qword ptr [rsi + 4], r11 \n"
" \n"
" 00005493 66| 41/ 0F B6 F3 movzx si, r11b \n"
" 00005498 66| 41/ 0F B6 73 movzx si, byte ptr [r11 + 4] \n"
" 04 \n"
" \n"
" 0000549E 41/ 0F B6 F3 movzx esi, r11b \n"
" 000054A2 41/ 0F B7 F3 movzx esi, r11w \n"
" 000054A6 41/ 0F B6 73 movzx esi, byte ptr [r11 + 4] \n"
" 04 \n"
" 000054AB 41/ 0F B7 73 movzx esi, word ptr [r11 + 4] \n"
" 04 \n"
" \n"
" 000054B0 49/ 0F B6 F3 movzx rsi, r11b \n"
" 000054B4 49/ 0F B7 F3 movzx rsi, r11w \n"
" 000054B8 49/ 0F B6 73 movzx rsi, byte ptr [r11 + 4] \n"
" 04 \n"
" 000054BD 49/ 0F B7 73 movzx rsi, word ptr [r11 + 4] \n"
" 04 \n"
" \n"
" \n"
" ; Source: r11, target: rdi \n"
" 000054C2 40/ B6 01 mov sil, 1 \n"
" 000054C5 66| BF 0001 mov di, 1 \n"
" 000054C9 BF 00000001 mov edi, 1 \n"
" 000054CE 48/ C7 C7 mov rdi, 1 \n"
" 00000001 \n"
" \n"
" 000054D5 41/ 8A F3 mov sil, r11b \n"
" 000054D8 66| 41/ 8B FB mov di, r11w \n"
" 000054DC 41/ 8B FB mov edi, r11d \n"
" 000054DF 49/ 8B FB mov rdi, r11 \n"
" \n"
" 000054E2 41/ 8A 73 FC mov sil, byte ptr [r11 - 4] \n"
" 000054E6 41/ 8A 73 04 mov sil, byte ptr [r11 + 4] \n"
" 000054EA 66| 41/ 8B 7B mov di, word ptr [r11 + 4] \n"
" 04 \n"
" 000054EF 41/ 8B 7B 04 mov edi, dword ptr [r11 + 4] \n"
" 000054F3 49/ 8B 7B 04 mov rdi, qword ptr [r11 + 4] \n"
" \n"
" 000054F7 44/ 88 5F FC mov byte ptr [rdi - 4], r11b \n"
" 000054FB 44/ 88 5F 04 mov byte ptr [rdi + 4], r11b \n"
" 000054FF 66| 44/ 89 5F mov word ptr [rdi + 4], r11w \n"
" 04 \n"
" 00005504 44/ 89 5F 04 mov dword ptr [rdi + 4], r11d \n"
" 00005508 4C/ 89 5F 04 mov qword ptr [rdi + 4], r11 \n"
" \n"
" 0000550C 66| 41/ 0F B6 FB movzx di, r11b \n"
" 00005511 66| 41/ 0F B6 7B movzx di, byte ptr [r11 + 4] \n"
" 04 \n"
" \n"
" 00005517 41/ 0F B6 FB movzx edi, r11b \n"
" 0000551B 41/ 0F B7 FB movzx edi, r11w \n"
" 0000551F 41/ 0F B6 7B movzx edi, byte ptr [r11 + 4] \n"
" 04 \n"
" 00005524 41/ 0F B7 7B movzx edi, word ptr [r11 + 4] \n"
" 04 \n"
" \n"
" 00005529 49/ 0F B6 FB movzx rdi, r11b \n"
" 0000552D 49/ 0F B7 FB movzx rdi, r11w \n"
" 00005531 49/ 0F B6 7B movzx rdi, byte ptr [r11 + 4] \n"
" 04 \n"
" 00005536 49/ 0F B7 7B movzx rdi, word ptr [r11 + 4] \n"
" 04 \n"
" \n"
" \n"
" ; Source: r11, target: r8 \n"
" 0000553B 41/ B0 01 mov r8b, 1 \n"
" 0000553E 66| 41/ B8 mov r8w, 1 \n"
" 0001 \n"
" 00005543 41/ B8 mov r8d, 1 \n"
" 00000001 \n"
" 00005549 49/ C7 C0 mov r8, 1 \n"
" 00000001 \n"
" \n"
" 00005550 45/ 8A C3 mov r8b, r11b \n"
" 00005553 66| 45/ 8B C3 mov r8w, r11w \n"
" 00005557 45/ 8B C3 mov r8d, r11d \n"
" 0000555A 4D/ 8B C3 mov r8, r11 \n"
" \n"
" 0000555D 45/ 8A 43 FC mov r8b, byte ptr [r11 - 4] \n"
" 00005561 45/ 8A 43 04 mov r8b, byte ptr [r11 + 4] \n"
" 00005565 66| 45/ 8B 43 mov r8w, word ptr [r11 + 4] \n"
" 04 \n"
" 0000556A 45/ 8B 43 04 mov r8d, dword ptr [r11 + 4] \n"
" 0000556E 4D/ 8B 43 04 mov r8, qword ptr [r11 + 4] \n"
" \n"
" 00005572 45/ 88 58 FC mov byte ptr [r8 - 4], r11b \n"
" 00005576 45/ 88 58 04 mov byte ptr [r8 + 4], r11b \n"
" 0000557A 66| 45/ 89 58 mov word ptr [r8 + 4], r11w \n"
" 04 \n"
" 0000557F 45/ 89 58 04 mov dword ptr [r8 + 4], r11d \n"
" 00005583 4D/ 89 58 04 mov qword ptr [r8 + 4], r11 \n"
" \n"
" 00005587 66| 45/ 0F B6 C3 movzx r8w, r11b \n"
" 0000558C 66| 45/ 0F B6 43 movzx r8w, byte ptr [r11 + 4] \n"
" 04 \n"
" \n"
" 00005592 45/ 0F B6 C3 movzx r8d, r11b \n"
" 00005596 45/ 0F B7 C3 movzx r8d, r11w \n"
" 0000559A 45/ 0F B6 43 movzx r8d, byte ptr [r11 + 4] \n"
" 04 \n"
" 0000559F 45/ 0F B7 43 movzx r8d, word ptr [r11 + 4] \n"
" 04 \n"
" \n"
" 000055A4 4D/ 0F B6 C3 movzx r8, r11b \n"
" 000055A8 4D/ 0F B7 C3 movzx r8, r11w \n"
" 000055AC 4D/ 0F B6 43 movzx r8, byte ptr [r11 + 4] \n"
" 04 \n"
" 000055B1 4D/ 0F B7 43 movzx r8, word ptr [r11 + 4] \n"
" 04 \n"
" \n"
" \n"
" ; Source: r11, target: r9 \n"
" 000055B6 41/ B1 01 mov r9b, 1 \n"
" 000055B9 66| 41/ B9 mov r9w, 1 \n"
" 0001 \n"
" 000055BE 41/ B9 mov r9d, 1 \n"
" 00000001 \n"
" 000055C4 49/ C7 C1 mov r9, 1 \n"
" 00000001 \n"
" \n"
" 000055CB 45/ 8A CB mov r9b, r11b \n"
" 000055CE 66| 45/ 8B CB mov r9w, r11w \n"
" 000055D2 45/ 8B CB mov r9d, r11d \n"
" 000055D5 4D/ 8B CB mov r9, r11 \n"
" \n"
" 000055D8 45/ 8A 4B FC mov r9b, byte ptr [r11 - 4] \n"
" 000055DC 45/ 8A 4B 04 mov r9b, byte ptr [r11 + 4] \n"
" 000055E0 66| 45/ 8B 4B mov r9w, word ptr [r11 + 4] \n"
" 04 \n"
" 000055E5 45/ 8B 4B 04 mov r9d, dword ptr [r11 + 4] \n"
" 000055E9 4D/ 8B 4B 04 mov r9, qword ptr [r11 + 4] \n"
" \n"
" 000055ED 45/ 88 59 FC mov byte ptr [r9 - 4], r11b \n"
" 000055F1 45/ 88 59 04 mov byte ptr [r9 + 4], r11b \n"
" 000055F5 66| 45/ 89 59 mov word ptr [r9 + 4], r11w \n"
" 04 \n"
" 000055FA 45/ 89 59 04 mov dword ptr [r9 + 4], r11d \n"
" 000055FE 4D/ 89 59 04 mov qword ptr [r9 + 4], r11 \n"
" \n"
" 00005602 66| 45/ 0F B6 CB movzx r9w, r11b \n"
" 00005607 66| 45/ 0F B6 4B movzx r9w, byte ptr [r11 + 4] \n"
" 04 \n"
" \n"
" 0000560D 45/ 0F B6 CB movzx r9d, r11b \n"
" 00005611 45/ 0F B7 CB movzx r9d, r11w \n"
" 00005615 45/ 0F B6 4B movzx r9d, byte ptr [r11 + 4] \n"
" 04 \n"
" 0000561A 45/ 0F B7 4B movzx r9d, word ptr [r11 + 4] \n"
" 04 \n"
" \n"
" 0000561F 4D/ 0F B6 CB movzx r9, r11b \n"
" 00005623 4D/ 0F B7 CB movzx r9, r11w \n"
" 00005627 4D/ 0F B6 4B movzx r9, byte ptr [r11 + 4] \n"
" 04 \n"
" 0000562C 4D/ 0F B7 4B movzx r9, word ptr [r11 + 4] \n"
" 04 \n"
" \n"
" \n"
" ; Source: r11, target: r10 \n"
" 00005631 41/ B2 01 mov r10b, 1 \n"
" 00005634 66| 41/ BA mov r10w, 1 \n"
" 0001 \n"
" 00005639 41/ BA mov r10d, 1 \n"
" 00000001 \n"
" 0000563F 49/ C7 C2 mov r10, 1 \n"
" 00000001 \n"
" \n"
" 00005646 45/ 8A D3 mov r10b, r11b \n"
" 00005649 66| 45/ 8B D3 mov r10w, r11w \n"
" 0000564D 45/ 8B D3 mov r10d, r11d \n"
" 00005650 4D/ 8B D3 mov r10, r11 \n"
" \n"
" 00005653 45/ 8A 53 FC mov r10b, byte ptr [r11 - 4] \n"
" 00005657 45/ 8A 53 04 mov r10b, byte ptr [r11 + 4] \n"
" 0000565B 66| 45/ 8B 53 mov r10w, word ptr [r11 + 4] \n"
" 04 \n"
" 00005660 45/ 8B 53 04 mov r10d, dword ptr [r11 + 4] \n"
" 00005664 4D/ 8B 53 04 mov r10, qword ptr [r11 + 4] \n"
" \n"
" 00005668 45/ 88 5A FC mov byte ptr [r10 - 4], r11b \n"
" 0000566C 45/ 88 5A 04 mov byte ptr [r10 + 4], r11b \n"
" 00005670 66| 45/ 89 5A mov word ptr [r10 + 4], r11w \n"
" 04 \n"
" 00005675 45/ 89 5A 04 mov dword ptr [r10 + 4], r11d \n"
" 00005679 4D/ 89 5A 04 mov qword ptr [r10 + 4], r11 \n"
" \n"
" 0000567D 66| 45/ 0F B6 D3 movzx r10w, r11b \n"
" 00005682 66| 45/ 0F B6 53 movzx r10w, byte ptr [r11 + 4] \n"
" 04 \n"
" \n"
" 00005688 45/ 0F B6 D3 movzx r10d, r11b \n"
" 0000568C 45/ 0F B7 D3 movzx r10d, r11w \n"
" 00005690 45/ 0F B6 53 movzx r10d, byte ptr [r11 + 4] \n"
" 04 \n"
" 00005695 45/ 0F B7 53 movzx r10d, word ptr [r11 + 4] \n"
" 04 \n"
" \n"
" 0000569A 4D/ 0F B6 D3 movzx r10, r11b \n"
" 0000569E 4D/ 0F B7 D3 movzx r10, r11w \n"
" 000056A2 4D/ 0F B6 53 movzx r10, byte ptr [r11 + 4] \n"
" 04 \n"
" 000056A7 4D/ 0F B7 53 movzx r10, word ptr [r11 + 4] \n"
" 04 \n"
" \n"
" \n"
" ; Source: r11, target: r11 \n"
" 000056AC 41/ B3 01 mov r11b, 1 \n"
" 000056AF 66| 41/ BB mov r11w, 1 \n"
" 0001 \n"
" 000056B4 41/ BB mov r11d, 1 \n"
" 00000001 \n"
" 000056BA 49/ C7 C3 mov r11, 1 \n"
" 00000001 \n"
" \n"
" 000056C1 45/ 8A DB mov r11b, r11b \n"
" 000056C4 66| 45/ 8B DB mov r11w, r11w \n"
" 000056C8 45/ 8B DB mov r11d, r11d \n"
" 000056CB 4D/ 8B DB mov r11, r11 \n"
" \n"
" 000056CE 45/ 8A 5B FC mov r11b, byte ptr [r11 - 4] \n"
" 000056D2 45/ 8A 5B 04 mov r11b, byte ptr [r11 + 4] \n"
" 000056D6 66| 45/ 8B 5B mov r11w, word ptr [r11 + 4] \n"
" 04 \n"
" 000056DB 45/ 8B 5B 04 mov r11d, dword ptr [r11 + 4] \n"
" 000056DF 4D/ 8B 5B 04 mov r11, qword ptr [r11 + 4] \n"
" \n"
" 000056E3 45/ 88 5B FC mov byte ptr [r11 - 4], r11b \n"
" 000056E7 45/ 88 5B 04 mov byte ptr [r11 + 4], r11b \n"
" 000056EB 66| 45/ 89 5B mov word ptr [r11 + 4], r11w \n"
" 04 \n"
" 000056F0 45/ 89 5B 04 mov dword ptr [r11 + 4], r11d \n"
" 000056F4 4D/ 89 5B 04 mov qword ptr [r11 + 4], r11 \n"
" \n"
" 000056F8 66| 45/ 0F B6 DB movzx r11w, r11b \n"
" 000056FD 66| 45/ 0F B6 5B movzx r11w, byte ptr [r11 + 4] \n"
" 04 \n"
" \n"
" 00005703 45/ 0F B6 DB movzx r11d, r11b \n"
" 00005707 45/ 0F B7 DB movzx r11d, r11w \n"
" 0000570B 45/ 0F B6 5B movzx r11d, byte ptr [r11 + 4] \n"
" 04 \n"
" 00005710 45/ 0F B7 5B movzx r11d, word ptr [r11 + 4] \n"
" 04 \n"
" \n"
" 00005715 4D/ 0F B6 DB movzx r11, r11b \n"
" 00005719 4D/ 0F B7 DB movzx r11, r11w \n"
" 0000571D 4D/ 0F B6 5B movzx r11, byte ptr [r11 + 4] \n"
" 04 \n"
" 00005722 4D/ 0F B7 5B movzx r11, word ptr [r11 + 4] \n"
" 04 \n"
" \n"
" \n"
" ; Source: r11, target: r12 \n"
" 00005727 41/ B4 01 mov r12b, 1 \n"
" 0000572A 66| 41/ BC mov r12w, 1 \n"
" 0001 \n"
" 0000572F 41/ BC mov r12d, 1 \n"
" 00000001 \n"
" 00005735 49/ C7 C4 mov r12, 1 \n"
" 00000001 \n"
" \n"
" 0000573C 45/ 8A E3 mov r12b, r11b \n"
" 0000573F 66| 45/ 8B E3 mov r12w, r11w \n"
" 00005743 45/ 8B E3 mov r12d, r11d \n"
" 00005746 4D/ 8B E3 mov r12, r11 \n"
" \n"
" 00005749 45/ 8A 63 FC mov r12b, byte ptr [r11 - 4] \n"
" 0000574D 45/ 8A 63 04 mov r12b, byte ptr [r11 + 4] \n"
" 00005751 66| 45/ 8B 63 mov r12w, word ptr [r11 + 4] \n"
" 04 \n"
" 00005756 45/ 8B 63 04 mov r12d, dword ptr [r11 + 4] \n"
" 0000575A 4D/ 8B 63 04 mov r12, qword ptr [r11 + 4] \n"
" \n"
" 0000575E 45/ 88 5C 24 mov byte ptr [r12 - 4], r11b \n"
" FC \n"
" 00005763 45/ 88 5C 24 mov byte ptr [r12 + 4], r11b \n"
" 04 \n"
" 00005768 66| 45/ 89 5C 24 mov word ptr [r12 + 4], r11w \n"
" 04 \n"
" 0000576E 45/ 89 5C 24 mov dword ptr [r12 + 4], r11d \n"
" 04 \n"
" 00005773 4D/ 89 5C 24 mov qword ptr [r12 + 4], r11 \n"
" 04 \n"
" \n"
" 00005778 66| 45/ 0F B6 E3 movzx r12w, r11b \n"
" 0000577D 66| 45/ 0F B6 63 movzx r12w, byte ptr [r11 + 4] \n"
" 04 \n"
" \n"
" 00005783 45/ 0F B6 E3 movzx r12d, r11b \n"
" 00005787 45/ 0F B7 E3 movzx r12d, r11w \n"
" 0000578B 45/ 0F B6 63 movzx r12d, byte ptr [r11 + 4] \n"
" 04 \n"
" 00005790 45/ 0F B7 63 movzx r12d, word ptr [r11 + 4] \n"
" 04 \n"
" \n"
" 00005795 4D/ 0F B6 E3 movzx r12, r11b \n"
" 00005799 4D/ 0F B7 E3 movzx r12, r11w \n"
" 0000579D 4D/ 0F B6 63 movzx r12, byte ptr [r11 + 4] \n"
" 04 \n"
" 000057A2 4D/ 0F B7 63 movzx r12, word ptr [r11 + 4] \n"
" 04 \n"
" \n"
" \n"
" ; Source: r11, target: r13 \n"
" 000057A7 41/ B5 01 mov r13b, 1 \n"
" 000057AA 66| 41/ BD mov r13w, 1 \n"
" 0001 \n"
" 000057AF 41/ BD mov r13d, 1 \n"
" 00000001 \n"
" 000057B5 49/ C7 C5 mov r13, 1 \n"
" 00000001 \n"
" \n"
" 000057BC 45/ 8A EB mov r13b, r11b \n"
" 000057BF 66| 45/ 8B EB mov r13w, r11w \n"
" 000057C3 45/ 8B EB mov r13d, r11d \n"
" 000057C6 4D/ 8B EB mov r13, r11 \n"
" \n"
" 000057C9 45/ 8A 6B FC mov r13b, byte ptr [r11 - 4] \n"
" 000057CD 45/ 8A 6B 04 mov r13b, byte ptr [r11 + 4] \n"
" 000057D1 66| 45/ 8B 6B mov r13w, word ptr [r11 + 4] \n"
" 04 \n"
" 000057D6 45/ 8B 6B 04 mov r13d, dword ptr [r11 + 4] \n"
" 000057DA 4D/ 8B 6B 04 mov r13, qword ptr [r11 + 4] \n"
" \n"
" 000057DE 45/ 88 5D FC mov byte ptr [r13 - 4], r11b \n"
" 000057E2 45/ 88 5D 04 mov byte ptr [r13 + 4], r11b \n"
" 000057E6 66| 45/ 89 5D mov word ptr [r13 + 4], r11w \n"
" 04 \n"
" 000057EB 45/ 89 5D 04 mov dword ptr [r13 + 4], r11d \n"
" 000057EF 4D/ 89 5D 04 mov qword ptr [r13 + 4], r11 \n"
" \n"
" 000057F3 66| 45/ 0F B6 EB movzx r13w, r11b \n"
" 000057F8 66| 45/ 0F B6 6B movzx r13w, byte ptr [r11 + 4] \n"
" 04 \n"
" \n"
" 000057FE 45/ 0F B6 EB movzx r13d, r11b \n"
" 00005802 45/ 0F B7 EB movzx r13d, r11w \n"
" 00005806 45/ 0F B6 6B movzx r13d, byte ptr [r11 + 4] \n"
" 04 \n"
" 0000580B 45/ 0F B7 6B movzx r13d, word ptr [r11 + 4] \n"
" 04 \n"
" \n"
" 00005810 4D/ 0F B6 EB movzx r13, r11b \n"
" 00005814 4D/ 0F B7 EB movzx r13, r11w \n"
" 00005818 4D/ 0F B6 6B movzx r13, byte ptr [r11 + 4] \n"
" 04 \n"
" 0000581D 4D/ 0F B7 6B movzx r13, word ptr [r11 + 4] \n"
" 04 \n"
" \n"
" \n"
" ; Source: r11, target: r14 \n"
" 00005822 41/ B6 01 mov r14b, 1 \n"
" 00005825 66| 41/ BE mov r14w, 1 \n"
" 0001 \n"
" 0000582A 41/ BE mov r14d, 1 \n"
" 00000001 \n"
" 00005830 49/ C7 C6 mov r14, 1 \n"
" 00000001 \n"
" \n"
" 00005837 45/ 8A F3 mov r14b, r11b \n"
" 0000583A 66| 45/ 8B F3 mov r14w, r11w \n"
" 0000583E 45/ 8B F3 mov r14d, r11d \n"
" 00005841 4D/ 8B F3 mov r14, r11 \n"
" \n"
" 00005844 45/ 8A 73 FC mov r14b, byte ptr [r11 - 4] \n"
" 00005848 45/ 8A 73 04 mov r14b, byte ptr [r11 + 4] \n"
" 0000584C 66| 45/ 8B 73 mov r14w, word ptr [r11 + 4] \n"
" 04 \n"
" 00005851 45/ 8B 73 04 mov r14d, dword ptr [r11 + 4] \n"
" 00005855 4D/ 8B 73 04 mov r14, qword ptr [r11 + 4] \n"
" \n"
" 00005859 45/ 88 5E FC mov byte ptr [r14 - 4], r11b \n"
" 0000585D 45/ 88 5E 04 mov byte ptr [r14 + 4], r11b \n"
" 00005861 66| 45/ 89 5E mov word ptr [r14 + 4], r11w \n"
" 04 \n"
" 00005866 45/ 89 5E 04 mov dword ptr [r14 + 4], r11d \n"
" 0000586A 4D/ 89 5E 04 mov qword ptr [r14 + 4], r11 \n"
" \n"
" 0000586E 66| 45/ 0F B6 F3 movzx r14w, r11b \n"
" 00005873 66| 45/ 0F B6 73 movzx r14w, byte ptr [r11 + 4] \n"
" 04 \n"
" \n"
" 00005879 45/ 0F B6 F3 movzx r14d, r11b \n"
" 0000587D 45/ 0F B7 F3 movzx r14d, r11w \n"
" 00005881 45/ 0F B6 73 movzx r14d, byte ptr [r11 + 4] \n"
" 04 \n"
" 00005886 45/ 0F B7 73 movzx r14d, word ptr [r11 + 4] \n"
" 04 \n"
" \n"
" 0000588B 4D/ 0F B6 F3 movzx r14, r11b \n"
" 0000588F 4D/ 0F B7 F3 movzx r14, r11w \n"
" 00005893 4D/ 0F B6 73 movzx r14, byte ptr [r11 + 4] \n"
" 04 \n"
" 00005898 4D/ 0F B7 73 movzx r14, word ptr [r11 + 4] \n"
" 04 \n"
" \n"
" \n"
" ; Source: r11, target: r15 \n"
" 0000589D 41/ B7 01 mov r15b, 1 \n"
" 000058A0 66| 41/ BF mov r15w, 1 \n"
" 0001 \n"
" 000058A5 41/ BF mov r15d, 1 \n"
" 00000001 \n"
" 000058AB 49/ C7 C7 mov r15, 1 \n"
" 00000001 \n"
" \n"
" 000058B2 45/ 8A FB mov r15b, r11b \n"
" 000058B5 66| 45/ 8B FB mov r15w, r11w \n"
" 000058B9 45/ 8B FB mov r15d, r11d \n"
" 000058BC 4D/ 8B FB mov r15, r11 \n"
" \n"
" 000058BF 45/ 8A 7B FC mov r15b, byte ptr [r11 - 4] \n"
" 000058C3 45/ 8A 7B 04 mov r15b, byte ptr [r11 + 4] \n"
" 000058C7 66| 45/ 8B 7B mov r15w, word ptr [r11 + 4] \n"
" 04 \n"
" 000058CC 45/ 8B 7B 04 mov r15d, dword ptr [r11 + 4] \n"
" 000058D0 4D/ 8B 7B 04 mov r15, qword ptr [r11 + 4] \n"
" \n"
" 000058D4 45/ 88 5F FC mov byte ptr [r15 - 4], r11b \n"
" 000058D8 45/ 88 5F 04 mov byte ptr [r15 + 4], r11b \n"
" 000058DC 66| 45/ 89 5F mov word ptr [r15 + 4], r11w \n"
" 04 \n"
" 000058E1 45/ 89 5F 04 mov dword ptr [r15 + 4], r11d \n"
" 000058E5 4D/ 89 5F 04 mov qword ptr [r15 + 4], r11 \n"
" \n"
" 000058E9 66| 45/ 0F B6 FB movzx r15w, r11b \n"
" 000058EE 66| 45/ 0F B6 7B movzx r15w, byte ptr [r11 + 4] \n"
" 04 \n"
" \n"
" 000058F4 45/ 0F B6 FB movzx r15d, r11b \n"
" 000058F8 45/ 0F B7 FB movzx r15d, r11w \n"
" 000058FC 45/ 0F B6 7B movzx r15d, byte ptr [r11 + 4] \n"
" 04 \n"
" 00005901 45/ 0F B7 7B movzx r15d, word ptr [r11 + 4] \n"
" 04 \n"
" \n"
" 00005906 4D/ 0F B6 FB movzx r15, r11b \n"
" 0000590A 4D/ 0F B7 FB movzx r15, r11w \n"
" 0000590E 4D/ 0F B6 7B movzx r15, byte ptr [r11 + 4] \n"
" 04 \n"
" 00005913 4D/ 0F B7 7B movzx r15, word ptr [r11 + 4] \n"
" 04 \n"
" \n"
" \n"
" ; Source: r12, target: rax \n"
" 00005918 B0 01 mov al, 1 \n"
" 0000591A 66| B8 0001 mov ax, 1 \n"
" 0000591E B8 00000001 mov eax, 1 \n"
" 00005923 48/ C7 C0 mov rax, 1 \n"
" 00000001 \n"
" \n"
" 0000592A 41/ 8A C4 mov al, r12b \n"
" 0000592D 66| 41/ 8B C4 mov ax, r12w \n"
" 00005931 41/ 8B C4 mov eax, r12d \n"
" 00005934 49/ 8B C4 mov rax, r12 \n"
" \n"
" 00005937 41/ 8A 44 24 mov al, byte ptr [r12 - 4] \n"
" FC \n"
" 0000593C 41/ 8A 44 24 mov al, byte ptr [r12 + 4] \n"
" 04 \n"
" 00005941 66| 41/ 8B 44 24 mov ax, word ptr [r12 + 4] \n"
" 04 \n"
" 00005947 41/ 8B 44 24 mov eax, dword ptr [r12 + 4] \n"
" 04 \n"
" 0000594C 49/ 8B 44 24 mov rax, qword ptr [r12 + 4] \n"
" 04 \n"
" \n"
" 00005951 44/ 88 60 FC mov byte ptr [rax - 4], r12b \n"
" 00005955 44/ 88 60 04 mov byte ptr [rax + 4], r12b \n"
" 00005959 66| 44/ 89 60 mov word ptr [rax + 4], r12w \n"
" 04 \n"
" 0000595E 44/ 89 60 04 mov dword ptr [rax + 4], r12d \n"
" 00005962 4C/ 89 60 04 mov qword ptr [rax + 4], r12 \n"
" \n"
" 00005966 66| 41/ 0F B6 C4 movzx ax, r12b \n"
" 0000596B 66| 41/ 0F B6 44 movzx ax, byte ptr [r12 + 4] \n"
" 24 04 \n"
" \n"
" 00005972 41/ 0F B6 C4 movzx eax, r12b \n"
" 00005976 41/ 0F B7 C4 movzx eax, r12w \n"
" 0000597A 41/ 0F B6 44 24 movzx eax, byte ptr [r12 + 4] \n"
" 04 \n"
" 00005980 41/ 0F B7 44 24 movzx eax, word ptr [r12 + 4] \n"
" 04 \n"
" \n"
" 00005986 49/ 0F B6 C4 movzx rax, r12b \n"
" 0000598A 49/ 0F B7 C4 movzx rax, r12w \n"
" 0000598E 49/ 0F B6 44 24 movzx rax, byte ptr [r12 + 4] \n"
" 04 \n"
" 00005994 49/ 0F B7 44 24 movzx rax, word ptr [r12 + 4] \n"
" 04 \n"
" \n"
" \n"
" ; Source: r12, target: rcx \n"
" 0000599A B1 01 mov cl, 1 \n"
" 0000599C 66| B9 0001 mov cx, 1 \n"
" 000059A0 B9 00000001 mov ecx, 1 \n"
" 000059A5 48/ C7 C1 mov rcx, 1 \n"
" 00000001 \n"
" \n"
" 000059AC 41/ 8A CC mov cl, r12b \n"
" 000059AF 66| 41/ 8B CC mov cx, r12w \n"
" 000059B3 41/ 8B CC mov ecx, r12d \n"
" 000059B6 49/ 8B CC mov rcx, r12 \n"
" \n"
" 000059B9 41/ 8A 4C 24 mov cl, byte ptr [r12 - 4] \n"
" FC \n"
" 000059BE 41/ 8A 4C 24 mov cl, byte ptr [r12 + 4] \n"
" 04 \n"
" 000059C3 66| 41/ 8B 4C 24 mov cx, word ptr [r12 + 4] \n"
" 04 \n"
" 000059C9 41/ 8B 4C 24 mov ecx, dword ptr [r12 + 4] \n"
" 04 \n"
" 000059CE 49/ 8B 4C 24 mov rcx, qword ptr [r12 + 4] \n";
ml64Output +=
" 04 \n"
" \n"
" 000059D3 44/ 88 61 FC mov byte ptr [rcx - 4], r12b \n"
" 000059D7 44/ 88 61 04 mov byte ptr [rcx + 4], r12b \n"
" 000059DB 66| 44/ 89 61 mov word ptr [rcx + 4], r12w \n"
" 04 \n"
" 000059E0 44/ 89 61 04 mov dword ptr [rcx + 4], r12d \n"
" 000059E4 4C/ 89 61 04 mov qword ptr [rcx + 4], r12 \n"
" \n"
" 000059E8 66| 41/ 0F B6 CC movzx cx, r12b \n"
" 000059ED 66| 41/ 0F B6 4C movzx cx, byte ptr [r12 + 4] \n"
" 24 04 \n"
" \n"
" 000059F4 41/ 0F B6 CC movzx ecx, r12b \n"
" 000059F8 41/ 0F B7 CC movzx ecx, r12w \n"
" 000059FC 41/ 0F B6 4C 24 movzx ecx, byte ptr [r12 + 4] \n"
" 04 \n"
" 00005A02 41/ 0F B7 4C 24 movzx ecx, word ptr [r12 + 4] \n"
" 04 \n"
" \n"
" 00005A08 49/ 0F B6 CC movzx rcx, r12b \n"
" 00005A0C 49/ 0F B7 CC movzx rcx, r12w \n"
" 00005A10 49/ 0F B6 4C 24 movzx rcx, byte ptr [r12 + 4] \n"
" 04 \n"
" 00005A16 49/ 0F B7 4C 24 movzx rcx, word ptr [r12 + 4] \n"
" 04 \n"
" \n"
" \n"
" ; Source: r12, target: rdx \n"
" 00005A1C B2 01 mov dl, 1 \n"
" 00005A1E 66| BA 0001 mov dx, 1 \n"
" 00005A22 BA 00000001 mov edx, 1 \n"
" 00005A27 48/ C7 C2 mov rdx, 1 \n"
" 00000001 \n"
" \n"
" 00005A2E 41/ 8A D4 mov dl, r12b \n"
" 00005A31 66| 41/ 8B D4 mov dx, r12w \n"
" 00005A35 41/ 8B D4 mov edx, r12d \n"
" 00005A38 49/ 8B D4 mov rdx, r12 \n"
" \n"
" 00005A3B 41/ 8A 54 24 mov dl, byte ptr [r12 - 4] \n"
" FC \n"
" 00005A40 41/ 8A 54 24 mov dl, byte ptr [r12 + 4] \n"
" 04 \n"
" 00005A45 66| 41/ 8B 54 24 mov dx, word ptr [r12 + 4] \n"
" 04 \n"
" 00005A4B 41/ 8B 54 24 mov edx, dword ptr [r12 + 4] \n"
" 04 \n"
" 00005A50 49/ 8B 54 24 mov rdx, qword ptr [r12 + 4] \n"
" 04 \n"
" \n"
" 00005A55 44/ 88 62 FC mov byte ptr [rdx - 4], r12b \n"
" 00005A59 44/ 88 62 04 mov byte ptr [rdx + 4], r12b \n"
" 00005A5D 66| 44/ 89 62 mov word ptr [rdx + 4], r12w \n"
" 04 \n"
" 00005A62 44/ 89 62 04 mov dword ptr [rdx + 4], r12d \n"
" 00005A66 4C/ 89 62 04 mov qword ptr [rdx + 4], r12 \n"
" \n"
" 00005A6A 66| 41/ 0F B6 D4 movzx dx, r12b \n"
" 00005A6F 66| 41/ 0F B6 54 movzx dx, byte ptr [r12 + 4] \n"
" 24 04 \n"
" \n"
" 00005A76 41/ 0F B6 D4 movzx edx, r12b \n"
" 00005A7A 41/ 0F B7 D4 movzx edx, r12w \n"
" 00005A7E 41/ 0F B6 54 24 movzx edx, byte ptr [r12 + 4] \n"
" 04 \n"
" 00005A84 41/ 0F B7 54 24 movzx edx, word ptr [r12 + 4] \n"
" 04 \n"
" \n"
" 00005A8A 49/ 0F B6 D4 movzx rdx, r12b \n"
" 00005A8E 49/ 0F B7 D4 movzx rdx, r12w \n"
" 00005A92 49/ 0F B6 54 24 movzx rdx, byte ptr [r12 + 4] \n"
" 04 \n"
" 00005A98 49/ 0F B7 54 24 movzx rdx, word ptr [r12 + 4] \n"
" 04 \n"
" \n"
" \n"
" ; Source: r12, target: rbx \n"
" 00005A9E B3 01 mov bl, 1 \n"
" 00005AA0 66| BB 0001 mov bx, 1 \n"
" 00005AA4 BB 00000001 mov ebx, 1 \n"
" 00005AA9 48/ C7 C3 mov rbx, 1 \n"
" 00000001 \n"
" \n"
" 00005AB0 41/ 8A DC mov bl, r12b \n"
" 00005AB3 66| 41/ 8B DC mov bx, r12w \n"
" 00005AB7 41/ 8B DC mov ebx, r12d \n"
" 00005ABA 49/ 8B DC mov rbx, r12 \n"
" \n"
" 00005ABD 41/ 8A 5C 24 mov bl, byte ptr [r12 - 4] \n"
" FC \n"
" 00005AC2 41/ 8A 5C 24 mov bl, byte ptr [r12 + 4] \n"
" 04 \n"
" 00005AC7 66| 41/ 8B 5C 24 mov bx, word ptr [r12 + 4] \n"
" 04 \n"
" 00005ACD 41/ 8B 5C 24 mov ebx, dword ptr [r12 + 4] \n"
" 04 \n"
" 00005AD2 49/ 8B 5C 24 mov rbx, qword ptr [r12 + 4] \n"
" 04 \n"
" \n"
" 00005AD7 44/ 88 63 FC mov byte ptr [rbx - 4], r12b \n"
" 00005ADB 44/ 88 63 04 mov byte ptr [rbx + 4], r12b \n"
" 00005ADF 66| 44/ 89 63 mov word ptr [rbx + 4], r12w \n"
" 04 \n"
" 00005AE4 44/ 89 63 04 mov dword ptr [rbx + 4], r12d \n"
" 00005AE8 4C/ 89 63 04 mov qword ptr [rbx + 4], r12 \n"
" \n"
" 00005AEC 66| 41/ 0F B6 DC movzx bx, r12b \n"
" 00005AF1 66| 41/ 0F B6 5C movzx bx, byte ptr [r12 + 4] \n"
" 24 04 \n"
" \n"
" 00005AF8 41/ 0F B6 DC movzx ebx, r12b \n"
" 00005AFC 41/ 0F B7 DC movzx ebx, r12w \n"
" 00005B00 41/ 0F B6 5C 24 movzx ebx, byte ptr [r12 + 4] \n"
" 04 \n"
" 00005B06 41/ 0F B7 5C 24 movzx ebx, word ptr [r12 + 4] \n"
" 04 \n"
" \n"
" 00005B0C 49/ 0F B6 DC movzx rbx, r12b \n"
" 00005B10 49/ 0F B7 DC movzx rbx, r12w \n"
" 00005B14 49/ 0F B6 5C 24 movzx rbx, byte ptr [r12 + 4] \n"
" 04 \n"
" 00005B1A 49/ 0F B7 5C 24 movzx rbx, word ptr [r12 + 4] \n"
" 04 \n"
" \n"
" \n"
" ; Source: r12, target: rsp \n"
" 00005B20 40/ B4 01 mov spl, 1 \n"
" 00005B23 66| BC 0001 mov sp, 1 \n"
" 00005B27 BC 00000001 mov esp, 1 \n"
" 00005B2C 48/ C7 C4 mov rsp, 1 \n"
" 00000001 \n"
" \n"
" 00005B33 41/ 8A E4 mov spl, r12b \n"
" 00005B36 66| 41/ 8B E4 mov sp, r12w \n"
" 00005B3A 41/ 8B E4 mov esp, r12d \n"
" 00005B3D 49/ 8B E4 mov rsp, r12 \n"
" \n"
" 00005B40 41/ 8A 64 24 mov spl, byte ptr [r12 - 4] \n"
" FC \n"
" 00005B45 41/ 8A 64 24 mov spl, byte ptr [r12 + 4] \n"
" 04 \n"
" 00005B4A 66| 41/ 8B 64 24 mov sp, word ptr [r12 + 4] \n"
" 04 \n"
" 00005B50 41/ 8B 64 24 mov esp, dword ptr [r12 + 4] \n"
" 04 \n"
" 00005B55 49/ 8B 64 24 mov rsp, qword ptr [r12 + 4] \n"
" 04 \n"
" \n"
" 00005B5A 44/ 88 64 24 mov byte ptr [rsp - 4], r12b \n"
" FC \n"
" 00005B5F 44/ 88 64 24 mov byte ptr [rsp + 4], r12b \n"
" 04 \n"
" 00005B64 66| 44/ 89 64 24 mov word ptr [rsp + 4], r12w \n"
" 04 \n"
" 00005B6A 44/ 89 64 24 mov dword ptr [rsp + 4], r12d \n"
" 04 \n"
" 00005B6F 4C/ 89 64 24 mov qword ptr [rsp + 4], r12 \n"
" 04 \n"
" \n"
" 00005B74 66| 41/ 0F B6 E4 movzx sp, r12b \n"
" 00005B79 66| 41/ 0F B6 64 movzx sp, byte ptr [r12 + 4] \n"
" 24 04 \n"
" \n"
" 00005B80 41/ 0F B6 E4 movzx esp, r12b \n"
" 00005B84 41/ 0F B7 E4 movzx esp, r12w \n"
" 00005B88 41/ 0F B6 64 24 movzx esp, byte ptr [r12 + 4] \n"
" 04 \n"
" 00005B8E 41/ 0F B7 64 24 movzx esp, word ptr [r12 + 4] \n"
" 04 \n"
" \n"
" 00005B94 49/ 0F B6 E4 movzx rsp, r12b \n"
" 00005B98 49/ 0F B7 E4 movzx rsp, r12w \n"
" 00005B9C 49/ 0F B6 64 24 movzx rsp, byte ptr [r12 + 4] \n"
" 04 \n"
" 00005BA2 49/ 0F B7 64 24 movzx rsp, word ptr [r12 + 4] \n"
" 04 \n"
" \n"
" \n"
" ; Source: r12, target: rbp \n"
" 00005BA8 40/ B5 01 mov bpl, 1 \n"
" 00005BAB 66| BD 0001 mov bp, 1 \n"
" 00005BAF BD 00000001 mov ebp, 1 \n"
" 00005BB4 48/ C7 C5 mov rbp, 1 \n"
" 00000001 \n"
" \n"
" 00005BBB 41/ 8A EC mov bpl, r12b \n"
" 00005BBE 66| 41/ 8B EC mov bp, r12w \n"
" 00005BC2 41/ 8B EC mov ebp, r12d \n"
" 00005BC5 49/ 8B EC mov rbp, r12 \n"
" \n"
" 00005BC8 41/ 8A 6C 24 mov bpl, byte ptr [r12 - 4] \n"
" FC \n"
" 00005BCD 41/ 8A 6C 24 mov bpl, byte ptr [r12 + 4] \n"
" 04 \n"
" 00005BD2 66| 41/ 8B 6C 24 mov bp, word ptr [r12 + 4] \n"
" 04 \n"
" 00005BD8 41/ 8B 6C 24 mov ebp, dword ptr [r12 + 4] \n"
" 04 \n"
" 00005BDD 49/ 8B 6C 24 mov rbp, qword ptr [r12 + 4] \n"
" 04 \n"
" \n"
" 00005BE2 44/ 88 65 FC mov byte ptr [rbp - 4], r12b \n"
" 00005BE6 44/ 88 65 04 mov byte ptr [rbp + 4], r12b \n"
" 00005BEA 66| 44/ 89 65 mov word ptr [rbp + 4], r12w \n"
" 04 \n"
" 00005BEF 44/ 89 65 04 mov dword ptr [rbp + 4], r12d \n"
" 00005BF3 4C/ 89 65 04 mov qword ptr [rbp + 4], r12 \n"
" \n"
" 00005BF7 66| 41/ 0F B6 EC movzx bp, r12b \n"
" 00005BFC 66| 41/ 0F B6 6C movzx bp, byte ptr [r12 + 4] \n"
" 24 04 \n"
" \n"
" 00005C03 41/ 0F B6 EC movzx ebp, r12b \n"
" 00005C07 41/ 0F B7 EC movzx ebp, r12w \n"
" 00005C0B 41/ 0F B6 6C 24 movzx ebp, byte ptr [r12 + 4] \n"
" 04 \n"
" 00005C11 41/ 0F B7 6C 24 movzx ebp, word ptr [r12 + 4] \n"
" 04 \n"
" \n"
" 00005C17 49/ 0F B6 EC movzx rbp, r12b \n"
" 00005C1B 49/ 0F B7 EC movzx rbp, r12w \n"
" 00005C1F 49/ 0F B6 6C 24 movzx rbp, byte ptr [r12 + 4] \n"
" 04 \n"
" 00005C25 49/ 0F B7 6C 24 movzx rbp, word ptr [r12 + 4] \n"
" 04 \n"
" \n"
" \n"
" ; Source: r12, target: rsi \n"
" 00005C2B 40/ B7 01 mov dil, 1 \n"
" 00005C2E 66| BE 0001 mov si, 1 \n"
" 00005C32 BE 00000001 mov esi, 1 \n"
" 00005C37 48/ C7 C6 mov rsi, 1 \n"
" 00000001 \n"
" \n"
" 00005C3E 41/ 8A FC mov dil, r12b \n"
" 00005C41 66| 41/ 8B F4 mov si, r12w \n"
" 00005C45 41/ 8B F4 mov esi, r12d \n"
" 00005C48 49/ 8B F4 mov rsi, r12 \n"
" \n"
" 00005C4B 41/ 8A 7C 24 mov dil, byte ptr [r12 - 4] \n"
" FC \n"
" 00005C50 41/ 8A 7C 24 mov dil, byte ptr [r12 + 4] \n"
" 04 \n"
" 00005C55 66| 41/ 8B 74 24 mov si, word ptr [r12 + 4] \n"
" 04 \n"
" 00005C5B 41/ 8B 74 24 mov esi, dword ptr [r12 + 4] \n"
" 04 \n"
" 00005C60 49/ 8B 74 24 mov rsi, qword ptr [r12 + 4] \n"
" 04 \n"
" \n"
" 00005C65 44/ 88 66 FC mov byte ptr [rsi - 4], r12b \n"
" 00005C69 44/ 88 66 04 mov byte ptr [rsi + 4], r12b \n"
" 00005C6D 66| 44/ 89 66 mov word ptr [rsi + 4], r12w \n"
" 04 \n"
" 00005C72 44/ 89 66 04 mov dword ptr [rsi + 4], r12d \n"
" 00005C76 4C/ 89 66 04 mov qword ptr [rsi + 4], r12 \n"
" \n"
" 00005C7A 66| 41/ 0F B6 F4 movzx si, r12b \n"
" 00005C7F 66| 41/ 0F B6 74 movzx si, byte ptr [r12 + 4] \n"
" 24 04 \n"
" \n"
" 00005C86 41/ 0F B6 F4 movzx esi, r12b \n"
" 00005C8A 41/ 0F B7 F4 movzx esi, r12w \n"
" 00005C8E 41/ 0F B6 74 24 movzx esi, byte ptr [r12 + 4] \n"
" 04 \n"
" 00005C94 41/ 0F B7 74 24 movzx esi, word ptr [r12 + 4] \n"
" 04 \n"
" \n"
" 00005C9A 49/ 0F B6 F4 movzx rsi, r12b \n"
" 00005C9E 49/ 0F B7 F4 movzx rsi, r12w \n"
" 00005CA2 49/ 0F B6 74 24 movzx rsi, byte ptr [r12 + 4] \n"
" 04 \n"
" 00005CA8 49/ 0F B7 74 24 movzx rsi, word ptr [r12 + 4] \n"
" 04 \n"
" \n"
" \n"
" ; Source: r12, target: rdi \n"
" 00005CAE 40/ B6 01 mov sil, 1 \n"
" 00005CB1 66| BF 0001 mov di, 1 \n"
" 00005CB5 BF 00000001 mov edi, 1 \n"
" 00005CBA 48/ C7 C7 mov rdi, 1 \n"
" 00000001 \n"
" \n"
" 00005CC1 41/ 8A F4 mov sil, r12b \n"
" 00005CC4 66| 41/ 8B FC mov di, r12w \n"
" 00005CC8 41/ 8B FC mov edi, r12d \n"
" 00005CCB 49/ 8B FC mov rdi, r12 \n"
" \n"
" 00005CCE 41/ 8A 74 24 mov sil, byte ptr [r12 - 4] \n"
" FC \n"
" 00005CD3 41/ 8A 74 24 mov sil, byte ptr [r12 + 4] \n"
" 04 \n"
" 00005CD8 66| 41/ 8B 7C 24 mov di, word ptr [r12 + 4] \n"
" 04 \n"
" 00005CDE 41/ 8B 7C 24 mov edi, dword ptr [r12 + 4] \n"
" 04 \n"
" 00005CE3 49/ 8B 7C 24 mov rdi, qword ptr [r12 + 4] \n"
" 04 \n"
" \n"
" 00005CE8 44/ 88 67 FC mov byte ptr [rdi - 4], r12b \n"
" 00005CEC 44/ 88 67 04 mov byte ptr [rdi + 4], r12b \n"
" 00005CF0 66| 44/ 89 67 mov word ptr [rdi + 4], r12w \n"
" 04 \n"
" 00005CF5 44/ 89 67 04 mov dword ptr [rdi + 4], r12d \n"
" 00005CF9 4C/ 89 67 04 mov qword ptr [rdi + 4], r12 \n"
" \n"
" 00005CFD 66| 41/ 0F B6 FC movzx di, r12b \n"
" 00005D02 66| 41/ 0F B6 7C movzx di, byte ptr [r12 + 4] \n"
" 24 04 \n"
" \n"
" 00005D09 41/ 0F B6 FC movzx edi, r12b \n"
" 00005D0D 41/ 0F B7 FC movzx edi, r12w \n"
" 00005D11 41/ 0F B6 7C 24 movzx edi, byte ptr [r12 + 4] \n"
" 04 \n"
" 00005D17 41/ 0F B7 7C 24 movzx edi, word ptr [r12 + 4] \n"
" 04 \n"
" \n"
" 00005D1D 49/ 0F B6 FC movzx rdi, r12b \n"
" 00005D21 49/ 0F B7 FC movzx rdi, r12w \n"
" 00005D25 49/ 0F B6 7C 24 movzx rdi, byte ptr [r12 + 4] \n"
" 04 \n"
" 00005D2B 49/ 0F B7 7C 24 movzx rdi, word ptr [r12 + 4] \n"
" 04 \n"
" \n"
" \n"
" ; Source: r12, target: r8 \n"
" 00005D31 41/ B0 01 mov r8b, 1 \n"
" 00005D34 66| 41/ B8 mov r8w, 1 \n"
" 0001 \n"
" 00005D39 41/ B8 mov r8d, 1 \n"
" 00000001 \n"
" 00005D3F 49/ C7 C0 mov r8, 1 \n"
" 00000001 \n"
" \n"
" 00005D46 45/ 8A C4 mov r8b, r12b \n"
" 00005D49 66| 45/ 8B C4 mov r8w, r12w \n"
" 00005D4D 45/ 8B C4 mov r8d, r12d \n"
" 00005D50 4D/ 8B C4 mov r8, r12 \n"
" \n"
" 00005D53 45/ 8A 44 24 mov r8b, byte ptr [r12 - 4] \n"
" FC \n"
" 00005D58 45/ 8A 44 24 mov r8b, byte ptr [r12 + 4] \n"
" 04 \n"
" 00005D5D 66| 45/ 8B 44 24 mov r8w, word ptr [r12 + 4] \n"
" 04 \n"
" 00005D63 45/ 8B 44 24 mov r8d, dword ptr [r12 + 4] \n"
" 04 \n"
" 00005D68 4D/ 8B 44 24 mov r8, qword ptr [r12 + 4] \n"
" 04 \n"
" \n"
" 00005D6D 45/ 88 60 FC mov byte ptr [r8 - 4], r12b \n"
" 00005D71 45/ 88 60 04 mov byte ptr [r8 + 4], r12b \n"
" 00005D75 66| 45/ 89 60 mov word ptr [r8 + 4], r12w \n"
" 04 \n"
" 00005D7A 45/ 89 60 04 mov dword ptr [r8 + 4], r12d \n"
" 00005D7E 4D/ 89 60 04 mov qword ptr [r8 + 4], r12 \n"
" \n"
" 00005D82 66| 45/ 0F B6 C4 movzx r8w, r12b \n"
" 00005D87 66| 45/ 0F B6 44 movzx r8w, byte ptr [r12 + 4] \n"
" 24 04 \n"
" \n"
" 00005D8E 45/ 0F B6 C4 movzx r8d, r12b \n"
" 00005D92 45/ 0F B7 C4 movzx r8d, r12w \n"
" 00005D96 45/ 0F B6 44 24 movzx r8d, byte ptr [r12 + 4] \n"
" 04 \n"
" 00005D9C 45/ 0F B7 44 24 movzx r8d, word ptr [r12 + 4] \n"
" 04 \n"
" \n"
" 00005DA2 4D/ 0F B6 C4 movzx r8, r12b \n"
" 00005DA6 4D/ 0F B7 C4 movzx r8, r12w \n"
" 00005DAA 4D/ 0F B6 44 24 movzx r8, byte ptr [r12 + 4] \n"
" 04 \n"
" 00005DB0 4D/ 0F B7 44 24 movzx r8, word ptr [r12 + 4] \n"
" 04 \n"
" \n"
" \n"
" ; Source: r12, target: r9 \n"
" 00005DB6 41/ B1 01 mov r9b, 1 \n"
" 00005DB9 66| 41/ B9 mov r9w, 1 \n"
" 0001 \n"
" 00005DBE 41/ B9 mov r9d, 1 \n"
" 00000001 \n"
" 00005DC4 49/ C7 C1 mov r9, 1 \n"
" 00000001 \n"
" \n"
" 00005DCB 45/ 8A CC mov r9b, r12b \n"
" 00005DCE 66| 45/ 8B CC mov r9w, r12w \n"
" 00005DD2 45/ 8B CC mov r9d, r12d \n"
" 00005DD5 4D/ 8B CC mov r9, r12 \n"
" \n"
" 00005DD8 45/ 8A 4C 24 mov r9b, byte ptr [r12 - 4] \n"
" FC \n"
" 00005DDD 45/ 8A 4C 24 mov r9b, byte ptr [r12 + 4] \n"
" 04 \n"
" 00005DE2 66| 45/ 8B 4C 24 mov r9w, word ptr [r12 + 4] \n"
" 04 \n"
" 00005DE8 45/ 8B 4C 24 mov r9d, dword ptr [r12 + 4] \n"
" 04 \n"
" 00005DED 4D/ 8B 4C 24 mov r9, qword ptr [r12 + 4] \n"
" 04 \n"
" \n"
" 00005DF2 45/ 88 61 FC mov byte ptr [r9 - 4], r12b \n"
" 00005DF6 45/ 88 61 04 mov byte ptr [r9 + 4], r12b \n"
" 00005DFA 66| 45/ 89 61 mov word ptr [r9 + 4], r12w \n"
" 04 \n"
" 00005DFF 45/ 89 61 04 mov dword ptr [r9 + 4], r12d \n"
" 00005E03 4D/ 89 61 04 mov qword ptr [r9 + 4], r12 \n"
" \n"
" 00005E07 66| 45/ 0F B6 CC movzx r9w, r12b \n"
" 00005E0C 66| 45/ 0F B6 4C movzx r9w, byte ptr [r12 + 4] \n"
" 24 04 \n"
" \n"
" 00005E13 45/ 0F B6 CC movzx r9d, r12b \n"
" 00005E17 45/ 0F B7 CC movzx r9d, r12w \n"
" 00005E1B 45/ 0F B6 4C 24 movzx r9d, byte ptr [r12 + 4] \n"
" 04 \n"
" 00005E21 45/ 0F B7 4C 24 movzx r9d, word ptr [r12 + 4] \n"
" 04 \n"
" \n"
" 00005E27 4D/ 0F B6 CC movzx r9, r12b \n"
" 00005E2B 4D/ 0F B7 CC movzx r9, r12w \n"
" 00005E2F 4D/ 0F B6 4C 24 movzx r9, byte ptr [r12 + 4] \n"
" 04 \n"
" 00005E35 4D/ 0F B7 4C 24 movzx r9, word ptr [r12 + 4] \n"
" 04 \n"
" \n"
" \n"
" ; Source: r12, target: r10 \n"
" 00005E3B 41/ B2 01 mov r10b, 1 \n"
" 00005E3E 66| 41/ BA mov r10w, 1 \n"
" 0001 \n"
" 00005E43 41/ BA mov r10d, 1 \n"
" 00000001 \n"
" 00005E49 49/ C7 C2 mov r10, 1 \n"
" 00000001 \n"
" \n"
" 00005E50 45/ 8A D4 mov r10b, r12b \n"
" 00005E53 66| 45/ 8B D4 mov r10w, r12w \n"
" 00005E57 45/ 8B D4 mov r10d, r12d \n"
" 00005E5A 4D/ 8B D4 mov r10, r12 \n"
" \n"
" 00005E5D 45/ 8A 54 24 mov r10b, byte ptr [r12 - 4] \n"
" FC \n"
" 00005E62 45/ 8A 54 24 mov r10b, byte ptr [r12 + 4] \n"
" 04 \n"
" 00005E67 66| 45/ 8B 54 24 mov r10w, word ptr [r12 + 4] \n"
" 04 \n"
" 00005E6D 45/ 8B 54 24 mov r10d, dword ptr [r12 + 4] \n"
" 04 \n"
" 00005E72 4D/ 8B 54 24 mov r10, qword ptr [r12 + 4] \n"
" 04 \n"
" \n"
" 00005E77 45/ 88 62 FC mov byte ptr [r10 - 4], r12b \n"
" 00005E7B 45/ 88 62 04 mov byte ptr [r10 + 4], r12b \n"
" 00005E7F 66| 45/ 89 62 mov word ptr [r10 + 4], r12w \n"
" 04 \n"
" 00005E84 45/ 89 62 04 mov dword ptr [r10 + 4], r12d \n"
" 00005E88 4D/ 89 62 04 mov qword ptr [r10 + 4], r12 \n"
" \n"
" 00005E8C 66| 45/ 0F B6 D4 movzx r10w, r12b \n"
" 00005E91 66| 45/ 0F B6 54 movzx r10w, byte ptr [r12 + 4] \n"
" 24 04 \n"
" \n"
" 00005E98 45/ 0F B6 D4 movzx r10d, r12b \n"
" 00005E9C 45/ 0F B7 D4 movzx r10d, r12w \n"
" 00005EA0 45/ 0F B6 54 24 movzx r10d, byte ptr [r12 + 4] \n"
" 04 \n"
" 00005EA6 45/ 0F B7 54 24 movzx r10d, word ptr [r12 + 4] \n"
" 04 \n"
" \n"
" 00005EAC 4D/ 0F B6 D4 movzx r10, r12b \n"
" 00005EB0 4D/ 0F B7 D4 movzx r10, r12w \n"
" 00005EB4 4D/ 0F B6 54 24 movzx r10, byte ptr [r12 + 4] \n"
" 04 \n"
" 00005EBA 4D/ 0F B7 54 24 movzx r10, word ptr [r12 + 4] \n"
" 04 \n"
" \n"
" \n"
" ; Source: r12, target: r11 \n"
" 00005EC0 41/ B3 01 mov r11b, 1 \n"
" 00005EC3 66| 41/ BB mov r11w, 1 \n"
" 0001 \n"
" 00005EC8 41/ BB mov r11d, 1 \n"
" 00000001 \n"
" 00005ECE 49/ C7 C3 mov r11, 1 \n"
" 00000001 \n"
" \n"
" 00005ED5 45/ 8A DC mov r11b, r12b \n"
" 00005ED8 66| 45/ 8B DC mov r11w, r12w \n"
" 00005EDC 45/ 8B DC mov r11d, r12d \n"
" 00005EDF 4D/ 8B DC mov r11, r12 \n"
" \n"
" 00005EE2 45/ 8A 5C 24 mov r11b, byte ptr [r12 - 4] \n"
" FC \n"
" 00005EE7 45/ 8A 5C 24 mov r11b, byte ptr [r12 + 4] \n"
" 04 \n"
" 00005EEC 66| 45/ 8B 5C 24 mov r11w, word ptr [r12 + 4] \n"
" 04 \n"
" 00005EF2 45/ 8B 5C 24 mov r11d, dword ptr [r12 + 4] \n"
" 04 \n"
" 00005EF7 4D/ 8B 5C 24 mov r11, qword ptr [r12 + 4] \n"
" 04 \n"
" \n"
" 00005EFC 45/ 88 63 FC mov byte ptr [r11 - 4], r12b \n"
" 00005F00 45/ 88 63 04 mov byte ptr [r11 + 4], r12b \n"
" 00005F04 66| 45/ 89 63 mov word ptr [r11 + 4], r12w \n"
" 04 \n"
" 00005F09 45/ 89 63 04 mov dword ptr [r11 + 4], r12d \n"
" 00005F0D 4D/ 89 63 04 mov qword ptr [r11 + 4], r12 \n"
" \n"
" 00005F11 66| 45/ 0F B6 DC movzx r11w, r12b \n"
" 00005F16 66| 45/ 0F B6 5C movzx r11w, byte ptr [r12 + 4] \n"
" 24 04 \n"
" \n"
" 00005F1D 45/ 0F B6 DC movzx r11d, r12b \n"
" 00005F21 45/ 0F B7 DC movzx r11d, r12w \n"
" 00005F25 45/ 0F B6 5C 24 movzx r11d, byte ptr [r12 + 4] \n"
" 04 \n"
" 00005F2B 45/ 0F B7 5C 24 movzx r11d, word ptr [r12 + 4] \n"
" 04 \n"
" \n"
" 00005F31 4D/ 0F B6 DC movzx r11, r12b \n"
" 00005F35 4D/ 0F B7 DC movzx r11, r12w \n"
" 00005F39 4D/ 0F B6 5C 24 movzx r11, byte ptr [r12 + 4] \n"
" 04 \n"
" 00005F3F 4D/ 0F B7 5C 24 movzx r11, word ptr [r12 + 4] \n"
" 04 \n"
" \n"
" \n"
" ; Source: r12, target: r12 \n"
" 00005F45 41/ B4 01 mov r12b, 1 \n"
" 00005F48 66| 41/ BC mov r12w, 1 \n"
" 0001 \n"
" 00005F4D 41/ BC mov r12d, 1 \n"
" 00000001 \n"
" 00005F53 49/ C7 C4 mov r12, 1 \n"
" 00000001 \n"
" \n"
" 00005F5A 45/ 8A E4 mov r12b, r12b \n"
" 00005F5D 66| 45/ 8B E4 mov r12w, r12w \n"
" 00005F61 45/ 8B E4 mov r12d, r12d \n"
" 00005F64 4D/ 8B E4 mov r12, r12 \n"
" \n"
" 00005F67 45/ 8A 64 24 mov r12b, byte ptr [r12 - 4] \n"
" FC \n"
" 00005F6C 45/ 8A 64 24 mov r12b, byte ptr [r12 + 4] \n"
" 04 \n"
" 00005F71 66| 45/ 8B 64 24 mov r12w, word ptr [r12 + 4] \n"
" 04 \n";
ml64Output +=
" 00005F77 45/ 8B 64 24 mov r12d, dword ptr [r12 + 4] \n"
" 04 \n"
" 00005F7C 4D/ 8B 64 24 mov r12, qword ptr [r12 + 4] \n"
" 04 \n"
" \n"
" 00005F81 45/ 88 64 24 mov byte ptr [r12 - 4], r12b \n"
" FC \n"
" 00005F86 45/ 88 64 24 mov byte ptr [r12 + 4], r12b \n"
" 04 \n"
" 00005F8B 66| 45/ 89 64 24 mov word ptr [r12 + 4], r12w \n"
" 04 \n"
" 00005F91 45/ 89 64 24 mov dword ptr [r12 + 4], r12d \n"
" 04 \n"
" 00005F96 4D/ 89 64 24 mov qword ptr [r12 + 4], r12 \n"
" 04 \n"
" \n"
" 00005F9B 66| 45/ 0F B6 E4 movzx r12w, r12b \n"
" 00005FA0 66| 45/ 0F B6 64 movzx r12w, byte ptr [r12 + 4] \n"
" 24 04 \n"
" \n"
" 00005FA7 45/ 0F B6 E4 movzx r12d, r12b \n"
" 00005FAB 45/ 0F B7 E4 movzx r12d, r12w \n"
" 00005FAF 45/ 0F B6 64 24 movzx r12d, byte ptr [r12 + 4] \n"
" 04 \n"
" 00005FB5 45/ 0F B7 64 24 movzx r12d, word ptr [r12 + 4] \n"
" 04 \n"
" \n"
" 00005FBB 4D/ 0F B6 E4 movzx r12, r12b \n"
" 00005FBF 4D/ 0F B7 E4 movzx r12, r12w \n"
" 00005FC3 4D/ 0F B6 64 24 movzx r12, byte ptr [r12 + 4] \n"
" 04 \n"
" 00005FC9 4D/ 0F B7 64 24 movzx r12, word ptr [r12 + 4] \n"
" 04 \n"
" \n"
" \n"
" ; Source: r12, target: r13 \n"
" 00005FCF 41/ B5 01 mov r13b, 1 \n"
" 00005FD2 66| 41/ BD mov r13w, 1 \n"
" 0001 \n"
" 00005FD7 41/ BD mov r13d, 1 \n"
" 00000001 \n"
" 00005FDD 49/ C7 C5 mov r13, 1 \n"
" 00000001 \n"
" \n"
" 00005FE4 45/ 8A EC mov r13b, r12b \n"
" 00005FE7 66| 45/ 8B EC mov r13w, r12w \n"
" 00005FEB 45/ 8B EC mov r13d, r12d \n"
" 00005FEE 4D/ 8B EC mov r13, r12 \n"
" \n"
" 00005FF1 45/ 8A 6C 24 mov r13b, byte ptr [r12 - 4] \n"
" FC \n"
" 00005FF6 45/ 8A 6C 24 mov r13b, byte ptr [r12 + 4] \n"
" 04 \n"
" 00005FFB 66| 45/ 8B 6C 24 mov r13w, word ptr [r12 + 4] \n"
" 04 \n"
" 00006001 45/ 8B 6C 24 mov r13d, dword ptr [r12 + 4] \n"
" 04 \n"
" 00006006 4D/ 8B 6C 24 mov r13, qword ptr [r12 + 4] \n"
" 04 \n"
" \n"
" 0000600B 45/ 88 65 FC mov byte ptr [r13 - 4], r12b \n"
" 0000600F 45/ 88 65 04 mov byte ptr [r13 + 4], r12b \n"
" 00006013 66| 45/ 89 65 mov word ptr [r13 + 4], r12w \n"
" 04 \n"
" 00006018 45/ 89 65 04 mov dword ptr [r13 + 4], r12d \n"
" 0000601C 4D/ 89 65 04 mov qword ptr [r13 + 4], r12 \n"
" \n"
" 00006020 66| 45/ 0F B6 EC movzx r13w, r12b \n"
" 00006025 66| 45/ 0F B6 6C movzx r13w, byte ptr [r12 + 4] \n"
" 24 04 \n"
" \n"
" 0000602C 45/ 0F B6 EC movzx r13d, r12b \n"
" 00006030 45/ 0F B7 EC movzx r13d, r12w \n"
" 00006034 45/ 0F B6 6C 24 movzx r13d, byte ptr [r12 + 4] \n"
" 04 \n"
" 0000603A 45/ 0F B7 6C 24 movzx r13d, word ptr [r12 + 4] \n"
" 04 \n"
" \n"
" 00006040 4D/ 0F B6 EC movzx r13, r12b \n"
" 00006044 4D/ 0F B7 EC movzx r13, r12w \n"
" 00006048 4D/ 0F B6 6C 24 movzx r13, byte ptr [r12 + 4] \n"
" 04 \n"
" 0000604E 4D/ 0F B7 6C 24 movzx r13, word ptr [r12 + 4] \n"
" 04 \n"
" \n"
" \n"
" ; Source: r12, target: r14 \n"
" 00006054 41/ B6 01 mov r14b, 1 \n"
" 00006057 66| 41/ BE mov r14w, 1 \n"
" 0001 \n"
" 0000605C 41/ BE mov r14d, 1 \n"
" 00000001 \n"
" 00006062 49/ C7 C6 mov r14, 1 \n"
" 00000001 \n"
" \n"
" 00006069 45/ 8A F4 mov r14b, r12b \n"
" 0000606C 66| 45/ 8B F4 mov r14w, r12w \n"
" 00006070 45/ 8B F4 mov r14d, r12d \n"
" 00006073 4D/ 8B F4 mov r14, r12 \n"
" \n"
" 00006076 45/ 8A 74 24 mov r14b, byte ptr [r12 - 4] \n"
" FC \n"
" 0000607B 45/ 8A 74 24 mov r14b, byte ptr [r12 + 4] \n"
" 04 \n"
" 00006080 66| 45/ 8B 74 24 mov r14w, word ptr [r12 + 4] \n"
" 04 \n"
" 00006086 45/ 8B 74 24 mov r14d, dword ptr [r12 + 4] \n"
" 04 \n"
" 0000608B 4D/ 8B 74 24 mov r14, qword ptr [r12 + 4] \n"
" 04 \n"
" \n"
" 00006090 45/ 88 66 FC mov byte ptr [r14 - 4], r12b \n"
" 00006094 45/ 88 66 04 mov byte ptr [r14 + 4], r12b \n"
" 00006098 66| 45/ 89 66 mov word ptr [r14 + 4], r12w \n"
" 04 \n"
" 0000609D 45/ 89 66 04 mov dword ptr [r14 + 4], r12d \n"
" 000060A1 4D/ 89 66 04 mov qword ptr [r14 + 4], r12 \n"
" \n"
" 000060A5 66| 45/ 0F B6 F4 movzx r14w, r12b \n"
" 000060AA 66| 45/ 0F B6 74 movzx r14w, byte ptr [r12 + 4] \n"
" 24 04 \n"
" \n"
" 000060B1 45/ 0F B6 F4 movzx r14d, r12b \n"
" 000060B5 45/ 0F B7 F4 movzx r14d, r12w \n"
" 000060B9 45/ 0F B6 74 24 movzx r14d, byte ptr [r12 + 4] \n"
" 04 \n"
" 000060BF 45/ 0F B7 74 24 movzx r14d, word ptr [r12 + 4] \n"
" 04 \n"
" \n"
" 000060C5 4D/ 0F B6 F4 movzx r14, r12b \n"
" 000060C9 4D/ 0F B7 F4 movzx r14, r12w \n"
" 000060CD 4D/ 0F B6 74 24 movzx r14, byte ptr [r12 + 4] \n"
" 04 \n"
" 000060D3 4D/ 0F B7 74 24 movzx r14, word ptr [r12 + 4] \n"
" 04 \n"
" \n"
" \n"
" ; Source: r12, target: r15 \n"
" 000060D9 41/ B7 01 mov r15b, 1 \n"
" 000060DC 66| 41/ BF mov r15w, 1 \n"
" 0001 \n"
" 000060E1 41/ BF mov r15d, 1 \n"
" 00000001 \n"
" 000060E7 49/ C7 C7 mov r15, 1 \n"
" 00000001 \n"
" \n"
" 000060EE 45/ 8A FC mov r15b, r12b \n"
" 000060F1 66| 45/ 8B FC mov r15w, r12w \n"
" 000060F5 45/ 8B FC mov r15d, r12d \n"
" 000060F8 4D/ 8B FC mov r15, r12 \n"
" \n"
" 000060FB 45/ 8A 7C 24 mov r15b, byte ptr [r12 - 4] \n"
" FC \n"
" 00006100 45/ 8A 7C 24 mov r15b, byte ptr [r12 + 4] \n"
" 04 \n"
" 00006105 66| 45/ 8B 7C 24 mov r15w, word ptr [r12 + 4] \n"
" 04 \n"
" 0000610B 45/ 8B 7C 24 mov r15d, dword ptr [r12 + 4] \n"
" 04 \n"
" 00006110 4D/ 8B 7C 24 mov r15, qword ptr [r12 + 4] \n"
" 04 \n"
" \n"
" 00006115 45/ 88 67 FC mov byte ptr [r15 - 4], r12b \n"
" 00006119 45/ 88 67 04 mov byte ptr [r15 + 4], r12b \n"
" 0000611D 66| 45/ 89 67 mov word ptr [r15 + 4], r12w \n"
" 04 \n"
" 00006122 45/ 89 67 04 mov dword ptr [r15 + 4], r12d \n"
" 00006126 4D/ 89 67 04 mov qword ptr [r15 + 4], r12 \n"
" \n"
" 0000612A 66| 45/ 0F B6 FC movzx r15w, r12b \n"
" 0000612F 66| 45/ 0F B6 7C movzx r15w, byte ptr [r12 + 4] \n"
" 24 04 \n"
" \n"
" 00006136 45/ 0F B6 FC movzx r15d, r12b \n"
" 0000613A 45/ 0F B7 FC movzx r15d, r12w \n"
" 0000613E 45/ 0F B6 7C 24 movzx r15d, byte ptr [r12 + 4] \n"
" 04 \n"
" 00006144 45/ 0F B7 7C 24 movzx r15d, word ptr [r12 + 4] \n"
" 04 \n"
" \n"
" 0000614A 4D/ 0F B6 FC movzx r15, r12b \n"
" 0000614E 4D/ 0F B7 FC movzx r15, r12w \n"
" 00006152 4D/ 0F B6 7C 24 movzx r15, byte ptr [r12 + 4] \n"
" 04 \n"
" 00006158 4D/ 0F B7 7C 24 movzx r15, word ptr [r12 + 4] \n"
" 04 \n"
" \n"
" \n"
" ; Source: r13, target: rax \n"
" 0000615E B0 01 mov al, 1 \n"
" 00006160 66| B8 0001 mov ax, 1 \n"
" 00006164 B8 00000001 mov eax, 1 \n"
" 00006169 48/ C7 C0 mov rax, 1 \n"
" 00000001 \n"
" \n"
" 00006170 41/ 8A C5 mov al, r13b \n"
" 00006173 66| 41/ 8B C5 mov ax, r13w \n"
" 00006177 41/ 8B C5 mov eax, r13d \n"
" 0000617A 49/ 8B C5 mov rax, r13 \n"
" \n"
" 0000617D 41/ 8A 45 FC mov al, byte ptr [r13 - 4] \n"
" 00006181 41/ 8A 45 04 mov al, byte ptr [r13 + 4] \n"
" 00006185 66| 41/ 8B 45 mov ax, word ptr [r13 + 4] \n"
" 04 \n"
" 0000618A 41/ 8B 45 04 mov eax, dword ptr [r13 + 4] \n"
" 0000618E 49/ 8B 45 04 mov rax, qword ptr [r13 + 4] \n"
" \n"
" 00006192 44/ 88 68 FC mov byte ptr [rax - 4], r13b \n"
" 00006196 44/ 88 68 04 mov byte ptr [rax + 4], r13b \n"
" 0000619A 66| 44/ 89 68 mov word ptr [rax + 4], r13w \n"
" 04 \n"
" 0000619F 44/ 89 68 04 mov dword ptr [rax + 4], r13d \n"
" 000061A3 4C/ 89 68 04 mov qword ptr [rax + 4], r13 \n"
" \n"
" 000061A7 66| 41/ 0F B6 C5 movzx ax, r13b \n"
" 000061AC 66| 41/ 0F B6 45 movzx ax, byte ptr [r13 + 4] \n"
" 04 \n"
" \n"
" 000061B2 41/ 0F B6 C5 movzx eax, r13b \n"
" 000061B6 41/ 0F B7 C5 movzx eax, r13w \n"
" 000061BA 41/ 0F B6 45 movzx eax, byte ptr [r13 + 4] \n"
" 04 \n"
" 000061BF 41/ 0F B7 45 movzx eax, word ptr [r13 + 4] \n"
" 04 \n"
" \n"
" 000061C4 49/ 0F B6 C5 movzx rax, r13b \n"
" 000061C8 49/ 0F B7 C5 movzx rax, r13w \n"
" 000061CC 49/ 0F B6 45 movzx rax, byte ptr [r13 + 4] \n"
" 04 \n"
" 000061D1 49/ 0F B7 45 movzx rax, word ptr [r13 + 4] \n"
" 04 \n"
" \n"
" \n"
" ; Source: r13, target: rcx \n"
" 000061D6 B1 01 mov cl, 1 \n"
" 000061D8 66| B9 0001 mov cx, 1 \n"
" 000061DC B9 00000001 mov ecx, 1 \n"
" 000061E1 48/ C7 C1 mov rcx, 1 \n"
" 00000001 \n"
" \n"
" 000061E8 41/ 8A CD mov cl, r13b \n"
" 000061EB 66| 41/ 8B CD mov cx, r13w \n"
" 000061EF 41/ 8B CD mov ecx, r13d \n"
" 000061F2 49/ 8B CD mov rcx, r13 \n"
" \n"
" 000061F5 41/ 8A 4D FC mov cl, byte ptr [r13 - 4] \n"
" 000061F9 41/ 8A 4D 04 mov cl, byte ptr [r13 + 4] \n"
" 000061FD 66| 41/ 8B 4D mov cx, word ptr [r13 + 4] \n"
" 04 \n"
" 00006202 41/ 8B 4D 04 mov ecx, dword ptr [r13 + 4] \n"
" 00006206 49/ 8B 4D 04 mov rcx, qword ptr [r13 + 4] \n"
" \n"
" 0000620A 44/ 88 69 FC mov byte ptr [rcx - 4], r13b \n"
" 0000620E 44/ 88 69 04 mov byte ptr [rcx + 4], r13b \n"
" 00006212 66| 44/ 89 69 mov word ptr [rcx + 4], r13w \n"
" 04 \n"
" 00006217 44/ 89 69 04 mov dword ptr [rcx + 4], r13d \n"
" 0000621B 4C/ 89 69 04 mov qword ptr [rcx + 4], r13 \n"
" \n"
" 0000621F 66| 41/ 0F B6 CD movzx cx, r13b \n"
" 00006224 66| 41/ 0F B6 4D movzx cx, byte ptr [r13 + 4] \n"
" 04 \n"
" \n"
" 0000622A 41/ 0F B6 CD movzx ecx, r13b \n"
" 0000622E 41/ 0F B7 CD movzx ecx, r13w \n"
" 00006232 41/ 0F B6 4D movzx ecx, byte ptr [r13 + 4] \n"
" 04 \n"
" 00006237 41/ 0F B7 4D movzx ecx, word ptr [r13 + 4] \n"
" 04 \n"
" \n"
" 0000623C 49/ 0F B6 CD movzx rcx, r13b \n"
" 00006240 49/ 0F B7 CD movzx rcx, r13w \n"
" 00006244 49/ 0F B6 4D movzx rcx, byte ptr [r13 + 4] \n"
" 04 \n"
" 00006249 49/ 0F B7 4D movzx rcx, word ptr [r13 + 4] \n"
" 04 \n"
" \n"
" \n"
" ; Source: r13, target: rdx \n"
" 0000624E B2 01 mov dl, 1 \n"
" 00006250 66| BA 0001 mov dx, 1 \n"
" 00006254 BA 00000001 mov edx, 1 \n"
" 00006259 48/ C7 C2 mov rdx, 1 \n"
" 00000001 \n"
" \n"
" 00006260 41/ 8A D5 mov dl, r13b \n"
" 00006263 66| 41/ 8B D5 mov dx, r13w \n"
" 00006267 41/ 8B D5 mov edx, r13d \n"
" 0000626A 49/ 8B D5 mov rdx, r13 \n"
" \n"
" 0000626D 41/ 8A 55 FC mov dl, byte ptr [r13 - 4] \n"
" 00006271 41/ 8A 55 04 mov dl, byte ptr [r13 + 4] \n"
" 00006275 66| 41/ 8B 55 mov dx, word ptr [r13 + 4] \n"
" 04 \n"
" 0000627A 41/ 8B 55 04 mov edx, dword ptr [r13 + 4] \n"
" 0000627E 49/ 8B 55 04 mov rdx, qword ptr [r13 + 4] \n"
" \n"
" 00006282 44/ 88 6A FC mov byte ptr [rdx - 4], r13b \n"
" 00006286 44/ 88 6A 04 mov byte ptr [rdx + 4], r13b \n"
" 0000628A 66| 44/ 89 6A mov word ptr [rdx + 4], r13w \n"
" 04 \n"
" 0000628F 44/ 89 6A 04 mov dword ptr [rdx + 4], r13d \n"
" 00006293 4C/ 89 6A 04 mov qword ptr [rdx + 4], r13 \n"
" \n"
" 00006297 66| 41/ 0F B6 D5 movzx dx, r13b \n"
" 0000629C 66| 41/ 0F B6 55 movzx dx, byte ptr [r13 + 4] \n"
" 04 \n"
" \n"
" 000062A2 41/ 0F B6 D5 movzx edx, r13b \n"
" 000062A6 41/ 0F B7 D5 movzx edx, r13w \n"
" 000062AA 41/ 0F B6 55 movzx edx, byte ptr [r13 + 4] \n"
" 04 \n"
" 000062AF 41/ 0F B7 55 movzx edx, word ptr [r13 + 4] \n"
" 04 \n"
" \n"
" 000062B4 49/ 0F B6 D5 movzx rdx, r13b \n"
" 000062B8 49/ 0F B7 D5 movzx rdx, r13w \n"
" 000062BC 49/ 0F B6 55 movzx rdx, byte ptr [r13 + 4] \n"
" 04 \n"
" 000062C1 49/ 0F B7 55 movzx rdx, word ptr [r13 + 4] \n"
" 04 \n"
" \n"
" \n"
" ; Source: r13, target: rbx \n"
" 000062C6 B3 01 mov bl, 1 \n"
" 000062C8 66| BB 0001 mov bx, 1 \n"
" 000062CC BB 00000001 mov ebx, 1 \n"
" 000062D1 48/ C7 C3 mov rbx, 1 \n"
" 00000001 \n"
" \n"
" 000062D8 41/ 8A DD mov bl, r13b \n"
" 000062DB 66| 41/ 8B DD mov bx, r13w \n"
" 000062DF 41/ 8B DD mov ebx, r13d \n"
" 000062E2 49/ 8B DD mov rbx, r13 \n"
" \n"
" 000062E5 41/ 8A 5D FC mov bl, byte ptr [r13 - 4] \n"
" 000062E9 41/ 8A 5D 04 mov bl, byte ptr [r13 + 4] \n"
" 000062ED 66| 41/ 8B 5D mov bx, word ptr [r13 + 4] \n"
" 04 \n"
" 000062F2 41/ 8B 5D 04 mov ebx, dword ptr [r13 + 4] \n"
" 000062F6 49/ 8B 5D 04 mov rbx, qword ptr [r13 + 4] \n"
" \n"
" 000062FA 44/ 88 6B FC mov byte ptr [rbx - 4], r13b \n"
" 000062FE 44/ 88 6B 04 mov byte ptr [rbx + 4], r13b \n"
" 00006302 66| 44/ 89 6B mov word ptr [rbx + 4], r13w \n"
" 04 \n"
" 00006307 44/ 89 6B 04 mov dword ptr [rbx + 4], r13d \n"
" 0000630B 4C/ 89 6B 04 mov qword ptr [rbx + 4], r13 \n"
" \n"
" 0000630F 66| 41/ 0F B6 DD movzx bx, r13b \n"
" 00006314 66| 41/ 0F B6 5D movzx bx, byte ptr [r13 + 4] \n"
" 04 \n"
" \n"
" 0000631A 41/ 0F B6 DD movzx ebx, r13b \n"
" 0000631E 41/ 0F B7 DD movzx ebx, r13w \n"
" 00006322 41/ 0F B6 5D movzx ebx, byte ptr [r13 + 4] \n"
" 04 \n"
" 00006327 41/ 0F B7 5D movzx ebx, word ptr [r13 + 4] \n"
" 04 \n"
" \n"
" 0000632C 49/ 0F B6 DD movzx rbx, r13b \n"
" 00006330 49/ 0F B7 DD movzx rbx, r13w \n"
" 00006334 49/ 0F B6 5D movzx rbx, byte ptr [r13 + 4] \n"
" 04 \n"
" 00006339 49/ 0F B7 5D movzx rbx, word ptr [r13 + 4] \n"
" 04 \n"
" \n"
" \n"
" ; Source: r13, target: rsp \n"
" 0000633E 40/ B4 01 mov spl, 1 \n"
" 00006341 66| BC 0001 mov sp, 1 \n"
" 00006345 BC 00000001 mov esp, 1 \n"
" 0000634A 48/ C7 C4 mov rsp, 1 \n"
" 00000001 \n"
" \n"
" 00006351 41/ 8A E5 mov spl, r13b \n"
" 00006354 66| 41/ 8B E5 mov sp, r13w \n"
" 00006358 41/ 8B E5 mov esp, r13d \n"
" 0000635B 49/ 8B E5 mov rsp, r13 \n"
" \n"
" 0000635E 41/ 8A 65 FC mov spl, byte ptr [r13 - 4] \n"
" 00006362 41/ 8A 65 04 mov spl, byte ptr [r13 + 4] \n"
" 00006366 66| 41/ 8B 65 mov sp, word ptr [r13 + 4] \n"
" 04 \n"
" 0000636B 41/ 8B 65 04 mov esp, dword ptr [r13 + 4] \n"
" 0000636F 49/ 8B 65 04 mov rsp, qword ptr [r13 + 4] \n"
" \n"
" 00006373 44/ 88 6C 24 mov byte ptr [rsp - 4], r13b \n"
" FC \n"
" 00006378 44/ 88 6C 24 mov byte ptr [rsp + 4], r13b \n"
" 04 \n"
" 0000637D 66| 44/ 89 6C 24 mov word ptr [rsp + 4], r13w \n"
" 04 \n"
" 00006383 44/ 89 6C 24 mov dword ptr [rsp + 4], r13d \n"
" 04 \n"
" 00006388 4C/ 89 6C 24 mov qword ptr [rsp + 4], r13 \n"
" 04 \n"
" \n"
" 0000638D 66| 41/ 0F B6 E5 movzx sp, r13b \n"
" 00006392 66| 41/ 0F B6 65 movzx sp, byte ptr [r13 + 4] \n"
" 04 \n"
" \n"
" 00006398 41/ 0F B6 E5 movzx esp, r13b \n"
" 0000639C 41/ 0F B7 E5 movzx esp, r13w \n"
" 000063A0 41/ 0F B6 65 movzx esp, byte ptr [r13 + 4] \n"
" 04 \n"
" 000063A5 41/ 0F B7 65 movzx esp, word ptr [r13 + 4] \n"
" 04 \n"
" \n"
" 000063AA 49/ 0F B6 E5 movzx rsp, r13b \n"
" 000063AE 49/ 0F B7 E5 movzx rsp, r13w \n"
" 000063B2 49/ 0F B6 65 movzx rsp, byte ptr [r13 + 4] \n"
" 04 \n"
" 000063B7 49/ 0F B7 65 movzx rsp, word ptr [r13 + 4] \n"
" 04 \n"
" \n"
" \n"
" ; Source: r13, target: rbp \n"
" 000063BC 40/ B5 01 mov bpl, 1 \n"
" 000063BF 66| BD 0001 mov bp, 1 \n"
" 000063C3 BD 00000001 mov ebp, 1 \n"
" 000063C8 48/ C7 C5 mov rbp, 1 \n"
" 00000001 \n"
" \n"
" 000063CF 41/ 8A ED mov bpl, r13b \n"
" 000063D2 66| 41/ 8B ED mov bp, r13w \n"
" 000063D6 41/ 8B ED mov ebp, r13d \n"
" 000063D9 49/ 8B ED mov rbp, r13 \n"
" \n"
" 000063DC 41/ 8A 6D FC mov bpl, byte ptr [r13 - 4] \n"
" 000063E0 41/ 8A 6D 04 mov bpl, byte ptr [r13 + 4] \n"
" 000063E4 66| 41/ 8B 6D mov bp, word ptr [r13 + 4] \n"
" 04 \n"
" 000063E9 41/ 8B 6D 04 mov ebp, dword ptr [r13 + 4] \n"
" 000063ED 49/ 8B 6D 04 mov rbp, qword ptr [r13 + 4] \n"
" \n"
" 000063F1 44/ 88 6D FC mov byte ptr [rbp - 4], r13b \n"
" 000063F5 44/ 88 6D 04 mov byte ptr [rbp + 4], r13b \n"
" 000063F9 66| 44/ 89 6D mov word ptr [rbp + 4], r13w \n"
" 04 \n"
" 000063FE 44/ 89 6D 04 mov dword ptr [rbp + 4], r13d \n"
" 00006402 4C/ 89 6D 04 mov qword ptr [rbp + 4], r13 \n"
" \n"
" 00006406 66| 41/ 0F B6 ED movzx bp, r13b \n"
" 0000640B 66| 41/ 0F B6 6D movzx bp, byte ptr [r13 + 4] \n"
" 04 \n"
" \n"
" 00006411 41/ 0F B6 ED movzx ebp, r13b \n"
" 00006415 41/ 0F B7 ED movzx ebp, r13w \n"
" 00006419 41/ 0F B6 6D movzx ebp, byte ptr [r13 + 4] \n"
" 04 \n"
" 0000641E 41/ 0F B7 6D movzx ebp, word ptr [r13 + 4] \n"
" 04 \n"
" \n"
" 00006423 49/ 0F B6 ED movzx rbp, r13b \n"
" 00006427 49/ 0F B7 ED movzx rbp, r13w \n"
" 0000642B 49/ 0F B6 6D movzx rbp, byte ptr [r13 + 4] \n"
" 04 \n"
" 00006430 49/ 0F B7 6D movzx rbp, word ptr [r13 + 4] \n"
" 04 \n"
" \n"
" \n"
" ; Source: r13, target: rsi \n"
" 00006435 40/ B7 01 mov dil, 1 \n"
" 00006438 66| BE 0001 mov si, 1 \n"
" 0000643C BE 00000001 mov esi, 1 \n"
" 00006441 48/ C7 C6 mov rsi, 1 \n"
" 00000001 \n"
" \n"
" 00006448 41/ 8A FD mov dil, r13b \n"
" 0000644B 66| 41/ 8B F5 mov si, r13w \n"
" 0000644F 41/ 8B F5 mov esi, r13d \n"
" 00006452 49/ 8B F5 mov rsi, r13 \n"
" \n"
" 00006455 41/ 8A 7D FC mov dil, byte ptr [r13 - 4] \n"
" 00006459 41/ 8A 7D 04 mov dil, byte ptr [r13 + 4] \n"
" 0000645D 66| 41/ 8B 75 mov si, word ptr [r13 + 4] \n"
" 04 \n"
" 00006462 41/ 8B 75 04 mov esi, dword ptr [r13 + 4] \n"
" 00006466 49/ 8B 75 04 mov rsi, qword ptr [r13 + 4] \n"
" \n"
" 0000646A 44/ 88 6E FC mov byte ptr [rsi - 4], r13b \n"
" 0000646E 44/ 88 6E 04 mov byte ptr [rsi + 4], r13b \n"
" 00006472 66| 44/ 89 6E mov word ptr [rsi + 4], r13w \n"
" 04 \n"
" 00006477 44/ 89 6E 04 mov dword ptr [rsi + 4], r13d \n"
" 0000647B 4C/ 89 6E 04 mov qword ptr [rsi + 4], r13 \n"
" \n"
" 0000647F 66| 41/ 0F B6 F5 movzx si, r13b \n"
" 00006484 66| 41/ 0F B6 75 movzx si, byte ptr [r13 + 4] \n"
" 04 \n"
" \n"
" 0000648A 41/ 0F B6 F5 movzx esi, r13b \n"
" 0000648E 41/ 0F B7 F5 movzx esi, r13w \n"
" 00006492 41/ 0F B6 75 movzx esi, byte ptr [r13 + 4] \n"
" 04 \n"
" 00006497 41/ 0F B7 75 movzx esi, word ptr [r13 + 4] \n"
" 04 \n"
" \n"
" 0000649C 49/ 0F B6 F5 movzx rsi, r13b \n"
" 000064A0 49/ 0F B7 F5 movzx rsi, r13w \n"
" 000064A4 49/ 0F B6 75 movzx rsi, byte ptr [r13 + 4] \n"
" 04 \n"
" 000064A9 49/ 0F B7 75 movzx rsi, word ptr [r13 + 4] \n"
" 04 \n"
" \n"
" \n"
" ; Source: r13, target: rdi \n"
" 000064AE 40/ B6 01 mov sil, 1 \n"
" 000064B1 66| BF 0001 mov di, 1 \n"
" 000064B5 BF 00000001 mov edi, 1 \n"
" 000064BA 48/ C7 C7 mov rdi, 1 \n"
" 00000001 \n"
" \n"
" 000064C1 41/ 8A F5 mov sil, r13b \n"
" 000064C4 66| 41/ 8B FD mov di, r13w \n"
" 000064C8 41/ 8B FD mov edi, r13d \n"
" 000064CB 49/ 8B FD mov rdi, r13 \n"
" \n"
" 000064CE 41/ 8A 75 FC mov sil, byte ptr [r13 - 4] \n"
" 000064D2 41/ 8A 75 04 mov sil, byte ptr [r13 + 4] \n"
" 000064D6 66| 41/ 8B 7D mov di, word ptr [r13 + 4] \n"
" 04 \n"
" 000064DB 41/ 8B 7D 04 mov edi, dword ptr [r13 + 4] \n"
" 000064DF 49/ 8B 7D 04 mov rdi, qword ptr [r13 + 4] \n"
" \n"
" 000064E3 44/ 88 6F FC mov byte ptr [rdi - 4], r13b \n"
" 000064E7 44/ 88 6F 04 mov byte ptr [rdi + 4], r13b \n"
" 000064EB 66| 44/ 89 6F mov word ptr [rdi + 4], r13w \n"
" 04 \n"
" 000064F0 44/ 89 6F 04 mov dword ptr [rdi + 4], r13d \n"
" 000064F4 4C/ 89 6F 04 mov qword ptr [rdi + 4], r13 \n"
" \n"
" 000064F8 66| 41/ 0F B6 FD movzx di, r13b \n"
" 000064FD 66| 41/ 0F B6 7D movzx di, byte ptr [r13 + 4] \n"
" 04 \n"
" \n"
" 00006503 41/ 0F B6 FD movzx edi, r13b \n"
" 00006507 41/ 0F B7 FD movzx edi, r13w \n"
" 0000650B 41/ 0F B6 7D movzx edi, byte ptr [r13 + 4] \n"
" 04 \n"
" 00006510 41/ 0F B7 7D movzx edi, word ptr [r13 + 4] \n"
" 04 \n"
" \n"
" 00006515 49/ 0F B6 FD movzx rdi, r13b \n"
" 00006519 49/ 0F B7 FD movzx rdi, r13w \n"
" 0000651D 49/ 0F B6 7D movzx rdi, byte ptr [r13 + 4] \n"
" 04 \n"
" 00006522 49/ 0F B7 7D movzx rdi, word ptr [r13 + 4] \n"
" 04 \n";
ml64Output +=
" \n"
" \n"
" ; Source: r13, target: r8 \n"
" 00006527 41/ B0 01 mov r8b, 1 \n"
" 0000652A 66| 41/ B8 mov r8w, 1 \n"
" 0001 \n"
" 0000652F 41/ B8 mov r8d, 1 \n"
" 00000001 \n"
" 00006535 49/ C7 C0 mov r8, 1 \n"
" 00000001 \n"
" \n"
" 0000653C 45/ 8A C5 mov r8b, r13b \n"
" 0000653F 66| 45/ 8B C5 mov r8w, r13w \n"
" 00006543 45/ 8B C5 mov r8d, r13d \n"
" 00006546 4D/ 8B C5 mov r8, r13 \n"
" \n"
" 00006549 45/ 8A 45 FC mov r8b, byte ptr [r13 - 4] \n"
" 0000654D 45/ 8A 45 04 mov r8b, byte ptr [r13 + 4] \n"
" 00006551 66| 45/ 8B 45 mov r8w, word ptr [r13 + 4] \n"
" 04 \n"
" 00006556 45/ 8B 45 04 mov r8d, dword ptr [r13 + 4] \n"
" 0000655A 4D/ 8B 45 04 mov r8, qword ptr [r13 + 4] \n"
" \n"
" 0000655E 45/ 88 68 FC mov byte ptr [r8 - 4], r13b \n"
" 00006562 45/ 88 68 04 mov byte ptr [r8 + 4], r13b \n"
" 00006566 66| 45/ 89 68 mov word ptr [r8 + 4], r13w \n"
" 04 \n"
" 0000656B 45/ 89 68 04 mov dword ptr [r8 + 4], r13d \n"
" 0000656F 4D/ 89 68 04 mov qword ptr [r8 + 4], r13 \n"
" \n"
" 00006573 66| 45/ 0F B6 C5 movzx r8w, r13b \n"
" 00006578 66| 45/ 0F B6 45 movzx r8w, byte ptr [r13 + 4] \n"
" 04 \n"
" \n"
" 0000657E 45/ 0F B6 C5 movzx r8d, r13b \n"
" 00006582 45/ 0F B7 C5 movzx r8d, r13w \n"
" 00006586 45/ 0F B6 45 movzx r8d, byte ptr [r13 + 4] \n"
" 04 \n"
" 0000658B 45/ 0F B7 45 movzx r8d, word ptr [r13 + 4] \n"
" 04 \n"
" \n"
" 00006590 4D/ 0F B6 C5 movzx r8, r13b \n"
" 00006594 4D/ 0F B7 C5 movzx r8, r13w \n"
" 00006598 4D/ 0F B6 45 movzx r8, byte ptr [r13 + 4] \n"
" 04 \n"
" 0000659D 4D/ 0F B7 45 movzx r8, word ptr [r13 + 4] \n"
" 04 \n"
" \n"
" \n"
" ; Source: r13, target: r9 \n"
" 000065A2 41/ B1 01 mov r9b, 1 \n"
" 000065A5 66| 41/ B9 mov r9w, 1 \n"
" 0001 \n"
" 000065AA 41/ B9 mov r9d, 1 \n"
" 00000001 \n"
" 000065B0 49/ C7 C1 mov r9, 1 \n"
" 00000001 \n"
" \n"
" 000065B7 45/ 8A CD mov r9b, r13b \n"
" 000065BA 66| 45/ 8B CD mov r9w, r13w \n"
" 000065BE 45/ 8B CD mov r9d, r13d \n"
" 000065C1 4D/ 8B CD mov r9, r13 \n"
" \n"
" 000065C4 45/ 8A 4D FC mov r9b, byte ptr [r13 - 4] \n"
" 000065C8 45/ 8A 4D 04 mov r9b, byte ptr [r13 + 4] \n"
" 000065CC 66| 45/ 8B 4D mov r9w, word ptr [r13 + 4] \n"
" 04 \n"
" 000065D1 45/ 8B 4D 04 mov r9d, dword ptr [r13 + 4] \n"
" 000065D5 4D/ 8B 4D 04 mov r9, qword ptr [r13 + 4] \n"
" \n"
" 000065D9 45/ 88 69 FC mov byte ptr [r9 - 4], r13b \n"
" 000065DD 45/ 88 69 04 mov byte ptr [r9 + 4], r13b \n"
" 000065E1 66| 45/ 89 69 mov word ptr [r9 + 4], r13w \n"
" 04 \n"
" 000065E6 45/ 89 69 04 mov dword ptr [r9 + 4], r13d \n"
" 000065EA 4D/ 89 69 04 mov qword ptr [r9 + 4], r13 \n"
" \n"
" 000065EE 66| 45/ 0F B6 CD movzx r9w, r13b \n"
" 000065F3 66| 45/ 0F B6 4D movzx r9w, byte ptr [r13 + 4] \n"
" 04 \n"
" \n"
" 000065F9 45/ 0F B6 CD movzx r9d, r13b \n"
" 000065FD 45/ 0F B7 CD movzx r9d, r13w \n"
" 00006601 45/ 0F B6 4D movzx r9d, byte ptr [r13 + 4] \n"
" 04 \n"
" 00006606 45/ 0F B7 4D movzx r9d, word ptr [r13 + 4] \n"
" 04 \n"
" \n"
" 0000660B 4D/ 0F B6 CD movzx r9, r13b \n"
" 0000660F 4D/ 0F B7 CD movzx r9, r13w \n"
" 00006613 4D/ 0F B6 4D movzx r9, byte ptr [r13 + 4] \n"
" 04 \n"
" 00006618 4D/ 0F B7 4D movzx r9, word ptr [r13 + 4] \n"
" 04 \n"
" \n"
" \n"
" ; Source: r13, target: r10 \n"
" 0000661D 41/ B2 01 mov r10b, 1 \n"
" 00006620 66| 41/ BA mov r10w, 1 \n"
" 0001 \n"
" 00006625 41/ BA mov r10d, 1 \n"
" 00000001 \n"
" 0000662B 49/ C7 C2 mov r10, 1 \n"
" 00000001 \n"
" \n"
" 00006632 45/ 8A D5 mov r10b, r13b \n"
" 00006635 66| 45/ 8B D5 mov r10w, r13w \n"
" 00006639 45/ 8B D5 mov r10d, r13d \n"
" 0000663C 4D/ 8B D5 mov r10, r13 \n"
" \n"
" 0000663F 45/ 8A 55 FC mov r10b, byte ptr [r13 - 4] \n"
" 00006643 45/ 8A 55 04 mov r10b, byte ptr [r13 + 4] \n"
" 00006647 66| 45/ 8B 55 mov r10w, word ptr [r13 + 4] \n"
" 04 \n"
" 0000664C 45/ 8B 55 04 mov r10d, dword ptr [r13 + 4] \n"
" 00006650 4D/ 8B 55 04 mov r10, qword ptr [r13 + 4] \n"
" \n"
" 00006654 45/ 88 6A FC mov byte ptr [r10 - 4], r13b \n"
" 00006658 45/ 88 6A 04 mov byte ptr [r10 + 4], r13b \n"
" 0000665C 66| 45/ 89 6A mov word ptr [r10 + 4], r13w \n"
" 04 \n"
" 00006661 45/ 89 6A 04 mov dword ptr [r10 + 4], r13d \n"
" 00006665 4D/ 89 6A 04 mov qword ptr [r10 + 4], r13 \n"
" \n"
" 00006669 66| 45/ 0F B6 D5 movzx r10w, r13b \n"
" 0000666E 66| 45/ 0F B6 55 movzx r10w, byte ptr [r13 + 4] \n"
" 04 \n"
" \n"
" 00006674 45/ 0F B6 D5 movzx r10d, r13b \n"
" 00006678 45/ 0F B7 D5 movzx r10d, r13w \n"
" 0000667C 45/ 0F B6 55 movzx r10d, byte ptr [r13 + 4] \n"
" 04 \n"
" 00006681 45/ 0F B7 55 movzx r10d, word ptr [r13 + 4] \n"
" 04 \n"
" \n"
" 00006686 4D/ 0F B6 D5 movzx r10, r13b \n"
" 0000668A 4D/ 0F B7 D5 movzx r10, r13w \n"
" 0000668E 4D/ 0F B6 55 movzx r10, byte ptr [r13 + 4] \n"
" 04 \n"
" 00006693 4D/ 0F B7 55 movzx r10, word ptr [r13 + 4] \n"
" 04 \n"
" \n"
" \n"
" ; Source: r13, target: r11 \n"
" 00006698 41/ B3 01 mov r11b, 1 \n"
" 0000669B 66| 41/ BB mov r11w, 1 \n"
" 0001 \n"
" 000066A0 41/ BB mov r11d, 1 \n"
" 00000001 \n"
" 000066A6 49/ C7 C3 mov r11, 1 \n"
" 00000001 \n"
" \n"
" 000066AD 45/ 8A DD mov r11b, r13b \n"
" 000066B0 66| 45/ 8B DD mov r11w, r13w \n"
" 000066B4 45/ 8B DD mov r11d, r13d \n"
" 000066B7 4D/ 8B DD mov r11, r13 \n"
" \n"
" 000066BA 45/ 8A 5D FC mov r11b, byte ptr [r13 - 4] \n"
" 000066BE 45/ 8A 5D 04 mov r11b, byte ptr [r13 + 4] \n"
" 000066C2 66| 45/ 8B 5D mov r11w, word ptr [r13 + 4] \n"
" 04 \n"
" 000066C7 45/ 8B 5D 04 mov r11d, dword ptr [r13 + 4] \n"
" 000066CB 4D/ 8B 5D 04 mov r11, qword ptr [r13 + 4] \n"
" \n"
" 000066CF 45/ 88 6B FC mov byte ptr [r11 - 4], r13b \n"
" 000066D3 45/ 88 6B 04 mov byte ptr [r11 + 4], r13b \n"
" 000066D7 66| 45/ 89 6B mov word ptr [r11 + 4], r13w \n"
" 04 \n"
" 000066DC 45/ 89 6B 04 mov dword ptr [r11 + 4], r13d \n"
" 000066E0 4D/ 89 6B 04 mov qword ptr [r11 + 4], r13 \n"
" \n"
" 000066E4 66| 45/ 0F B6 DD movzx r11w, r13b \n"
" 000066E9 66| 45/ 0F B6 5D movzx r11w, byte ptr [r13 + 4] \n"
" 04 \n"
" \n"
" 000066EF 45/ 0F B6 DD movzx r11d, r13b \n"
" 000066F3 45/ 0F B7 DD movzx r11d, r13w \n"
" 000066F7 45/ 0F B6 5D movzx r11d, byte ptr [r13 + 4] \n"
" 04 \n"
" 000066FC 45/ 0F B7 5D movzx r11d, word ptr [r13 + 4] \n"
" 04 \n"
" \n"
" 00006701 4D/ 0F B6 DD movzx r11, r13b \n"
" 00006705 4D/ 0F B7 DD movzx r11, r13w \n"
" 00006709 4D/ 0F B6 5D movzx r11, byte ptr [r13 + 4] \n"
" 04 \n"
" 0000670E 4D/ 0F B7 5D movzx r11, word ptr [r13 + 4] \n"
" 04 \n"
" \n"
" \n"
" ; Source: r13, target: r12 \n"
" 00006713 41/ B4 01 mov r12b, 1 \n"
" 00006716 66| 41/ BC mov r12w, 1 \n"
" 0001 \n"
" 0000671B 41/ BC mov r12d, 1 \n"
" 00000001 \n"
" 00006721 49/ C7 C4 mov r12, 1 \n"
" 00000001 \n"
" \n"
" 00006728 45/ 8A E5 mov r12b, r13b \n"
" 0000672B 66| 45/ 8B E5 mov r12w, r13w \n"
" 0000672F 45/ 8B E5 mov r12d, r13d \n"
" 00006732 4D/ 8B E5 mov r12, r13 \n"
" \n"
" 00006735 45/ 8A 65 FC mov r12b, byte ptr [r13 - 4] \n"
" 00006739 45/ 8A 65 04 mov r12b, byte ptr [r13 + 4] \n"
" 0000673D 66| 45/ 8B 65 mov r12w, word ptr [r13 + 4] \n"
" 04 \n"
" 00006742 45/ 8B 65 04 mov r12d, dword ptr [r13 + 4] \n"
" 00006746 4D/ 8B 65 04 mov r12, qword ptr [r13 + 4] \n"
" \n"
" 0000674A 45/ 88 6C 24 mov byte ptr [r12 - 4], r13b \n"
" FC \n"
" 0000674F 45/ 88 6C 24 mov byte ptr [r12 + 4], r13b \n"
" 04 \n"
" 00006754 66| 45/ 89 6C 24 mov word ptr [r12 + 4], r13w \n"
" 04 \n"
" 0000675A 45/ 89 6C 24 mov dword ptr [r12 + 4], r13d \n"
" 04 \n"
" 0000675F 4D/ 89 6C 24 mov qword ptr [r12 + 4], r13 \n"
" 04 \n"
" \n"
" 00006764 66| 45/ 0F B6 E5 movzx r12w, r13b \n"
" 00006769 66| 45/ 0F B6 65 movzx r12w, byte ptr [r13 + 4] \n"
" 04 \n"
" \n"
" 0000676F 45/ 0F B6 E5 movzx r12d, r13b \n"
" 00006773 45/ 0F B7 E5 movzx r12d, r13w \n"
" 00006777 45/ 0F B6 65 movzx r12d, byte ptr [r13 + 4] \n"
" 04 \n"
" 0000677C 45/ 0F B7 65 movzx r12d, word ptr [r13 + 4] \n"
" 04 \n"
" \n"
" 00006781 4D/ 0F B6 E5 movzx r12, r13b \n"
" 00006785 4D/ 0F B7 E5 movzx r12, r13w \n"
" 00006789 4D/ 0F B6 65 movzx r12, byte ptr [r13 + 4] \n"
" 04 \n"
" 0000678E 4D/ 0F B7 65 movzx r12, word ptr [r13 + 4] \n"
" 04 \n"
" \n"
" \n"
" ; Source: r13, target: r13 \n"
" 00006793 41/ B5 01 mov r13b, 1 \n"
" 00006796 66| 41/ BD mov r13w, 1 \n"
" 0001 \n"
" 0000679B 41/ BD mov r13d, 1 \n"
" 00000001 \n"
" 000067A1 49/ C7 C5 mov r13, 1 \n"
" 00000001 \n"
" \n"
" 000067A8 45/ 8A ED mov r13b, r13b \n"
" 000067AB 66| 45/ 8B ED mov r13w, r13w \n"
" 000067AF 45/ 8B ED mov r13d, r13d \n"
" 000067B2 4D/ 8B ED mov r13, r13 \n"
" \n"
" 000067B5 45/ 8A 6D FC mov r13b, byte ptr [r13 - 4] \n"
" 000067B9 45/ 8A 6D 04 mov r13b, byte ptr [r13 + 4] \n"
" 000067BD 66| 45/ 8B 6D mov r13w, word ptr [r13 + 4] \n"
" 04 \n"
" 000067C2 45/ 8B 6D 04 mov r13d, dword ptr [r13 + 4] \n"
" 000067C6 4D/ 8B 6D 04 mov r13, qword ptr [r13 + 4] \n"
" \n"
" 000067CA 45/ 88 6D FC mov byte ptr [r13 - 4], r13b \n"
" 000067CE 45/ 88 6D 04 mov byte ptr [r13 + 4], r13b \n"
" 000067D2 66| 45/ 89 6D mov word ptr [r13 + 4], r13w \n"
" 04 \n"
" 000067D7 45/ 89 6D 04 mov dword ptr [r13 + 4], r13d \n"
" 000067DB 4D/ 89 6D 04 mov qword ptr [r13 + 4], r13 \n"
" \n"
" 000067DF 66| 45/ 0F B6 ED movzx r13w, r13b \n"
" 000067E4 66| 45/ 0F B6 6D movzx r13w, byte ptr [r13 + 4] \n"
" 04 \n"
" \n"
" 000067EA 45/ 0F B6 ED movzx r13d, r13b \n"
" 000067EE 45/ 0F B7 ED movzx r13d, r13w \n"
" 000067F2 45/ 0F B6 6D movzx r13d, byte ptr [r13 + 4] \n"
" 04 \n"
" 000067F7 45/ 0F B7 6D movzx r13d, word ptr [r13 + 4] \n"
" 04 \n"
" \n"
" 000067FC 4D/ 0F B6 ED movzx r13, r13b \n"
" 00006800 4D/ 0F B7 ED movzx r13, r13w \n"
" 00006804 4D/ 0F B6 6D movzx r13, byte ptr [r13 + 4] \n"
" 04 \n"
" 00006809 4D/ 0F B7 6D movzx r13, word ptr [r13 + 4] \n"
" 04 \n"
" \n"
" \n"
" ; Source: r13, target: r14 \n"
" 0000680E 41/ B6 01 mov r14b, 1 \n"
" 00006811 66| 41/ BE mov r14w, 1 \n"
" 0001 \n"
" 00006816 41/ BE mov r14d, 1 \n"
" 00000001 \n"
" 0000681C 49/ C7 C6 mov r14, 1 \n"
" 00000001 \n"
" \n"
" 00006823 45/ 8A F5 mov r14b, r13b \n"
" 00006826 66| 45/ 8B F5 mov r14w, r13w \n"
" 0000682A 45/ 8B F5 mov r14d, r13d \n"
" 0000682D 4D/ 8B F5 mov r14, r13 \n"
" \n"
" 00006830 45/ 8A 75 FC mov r14b, byte ptr [r13 - 4] \n"
" 00006834 45/ 8A 75 04 mov r14b, byte ptr [r13 + 4] \n"
" 00006838 66| 45/ 8B 75 mov r14w, word ptr [r13 + 4] \n"
" 04 \n"
" 0000683D 45/ 8B 75 04 mov r14d, dword ptr [r13 + 4] \n"
" 00006841 4D/ 8B 75 04 mov r14, qword ptr [r13 + 4] \n"
" \n"
" 00006845 45/ 88 6E FC mov byte ptr [r14 - 4], r13b \n"
" 00006849 45/ 88 6E 04 mov byte ptr [r14 + 4], r13b \n"
" 0000684D 66| 45/ 89 6E mov word ptr [r14 + 4], r13w \n"
" 04 \n"
" 00006852 45/ 89 6E 04 mov dword ptr [r14 + 4], r13d \n"
" 00006856 4D/ 89 6E 04 mov qword ptr [r14 + 4], r13 \n"
" \n"
" 0000685A 66| 45/ 0F B6 F5 movzx r14w, r13b \n"
" 0000685F 66| 45/ 0F B6 75 movzx r14w, byte ptr [r13 + 4] \n"
" 04 \n"
" \n"
" 00006865 45/ 0F B6 F5 movzx r14d, r13b \n"
" 00006869 45/ 0F B7 F5 movzx r14d, r13w \n"
" 0000686D 45/ 0F B6 75 movzx r14d, byte ptr [r13 + 4] \n"
" 04 \n"
" 00006872 45/ 0F B7 75 movzx r14d, word ptr [r13 + 4] \n"
" 04 \n"
" \n"
" 00006877 4D/ 0F B6 F5 movzx r14, r13b \n"
" 0000687B 4D/ 0F B7 F5 movzx r14, r13w \n"
" 0000687F 4D/ 0F B6 75 movzx r14, byte ptr [r13 + 4] \n"
" 04 \n"
" 00006884 4D/ 0F B7 75 movzx r14, word ptr [r13 + 4] \n"
" 04 \n"
" \n"
" \n"
" ; Source: r13, target: r15 \n"
" 00006889 41/ B7 01 mov r15b, 1 \n"
" 0000688C 66| 41/ BF mov r15w, 1 \n"
" 0001 \n"
" 00006891 41/ BF mov r15d, 1 \n"
" 00000001 \n"
" 00006897 49/ C7 C7 mov r15, 1 \n"
" 00000001 \n"
" \n"
" 0000689E 45/ 8A FD mov r15b, r13b \n"
" 000068A1 66| 45/ 8B FD mov r15w, r13w \n"
" 000068A5 45/ 8B FD mov r15d, r13d \n"
" 000068A8 4D/ 8B FD mov r15, r13 \n"
" \n"
" 000068AB 45/ 8A 7D FC mov r15b, byte ptr [r13 - 4] \n"
" 000068AF 45/ 8A 7D 04 mov r15b, byte ptr [r13 + 4] \n"
" 000068B3 66| 45/ 8B 7D mov r15w, word ptr [r13 + 4] \n"
" 04 \n"
" 000068B8 45/ 8B 7D 04 mov r15d, dword ptr [r13 + 4] \n"
" 000068BC 4D/ 8B 7D 04 mov r15, qword ptr [r13 + 4] \n"
" \n"
" 000068C0 45/ 88 6F FC mov byte ptr [r15 - 4], r13b \n"
" 000068C4 45/ 88 6F 04 mov byte ptr [r15 + 4], r13b \n"
" 000068C8 66| 45/ 89 6F mov word ptr [r15 + 4], r13w \n"
" 04 \n"
" 000068CD 45/ 89 6F 04 mov dword ptr [r15 + 4], r13d \n"
" 000068D1 4D/ 89 6F 04 mov qword ptr [r15 + 4], r13 \n"
" \n"
" 000068D5 66| 45/ 0F B6 FD movzx r15w, r13b \n"
" 000068DA 66| 45/ 0F B6 7D movzx r15w, byte ptr [r13 + 4] \n"
" 04 \n"
" \n"
" 000068E0 45/ 0F B6 FD movzx r15d, r13b \n"
" 000068E4 45/ 0F B7 FD movzx r15d, r13w \n"
" 000068E8 45/ 0F B6 7D movzx r15d, byte ptr [r13 + 4] \n"
" 04 \n"
" 000068ED 45/ 0F B7 7D movzx r15d, word ptr [r13 + 4] \n"
" 04 \n"
" \n"
" 000068F2 4D/ 0F B6 FD movzx r15, r13b \n"
" 000068F6 4D/ 0F B7 FD movzx r15, r13w \n"
" 000068FA 4D/ 0F B6 7D movzx r15, byte ptr [r13 + 4] \n"
" 04 \n"
" 000068FF 4D/ 0F B7 7D movzx r15, word ptr [r13 + 4] \n"
" 04 \n"
" \n"
" \n"
" ; Source: r14, target: rax \n"
" 00006904 B0 01 mov al, 1 \n"
" 00006906 66| B8 0001 mov ax, 1 \n"
" 0000690A B8 00000001 mov eax, 1 \n"
" 0000690F 48/ C7 C0 mov rax, 1 \n"
" 00000001 \n"
" \n"
" 00006916 41/ 8A C6 mov al, r14b \n"
" 00006919 66| 41/ 8B C6 mov ax, r14w \n"
" 0000691D 41/ 8B C6 mov eax, r14d \n"
" 00006920 49/ 8B C6 mov rax, r14 \n"
" \n"
" 00006923 41/ 8A 46 FC mov al, byte ptr [r14 - 4] \n"
" 00006927 41/ 8A 46 04 mov al, byte ptr [r14 + 4] \n"
" 0000692B 66| 41/ 8B 46 mov ax, word ptr [r14 + 4] \n"
" 04 \n"
" 00006930 41/ 8B 46 04 mov eax, dword ptr [r14 + 4] \n"
" 00006934 49/ 8B 46 04 mov rax, qword ptr [r14 + 4] \n"
" \n"
" 00006938 44/ 88 70 FC mov byte ptr [rax - 4], r14b \n"
" 0000693C 44/ 88 70 04 mov byte ptr [rax + 4], r14b \n"
" 00006940 66| 44/ 89 70 mov word ptr [rax + 4], r14w \n"
" 04 \n"
" 00006945 44/ 89 70 04 mov dword ptr [rax + 4], r14d \n"
" 00006949 4C/ 89 70 04 mov qword ptr [rax + 4], r14 \n"
" \n"
" 0000694D 66| 41/ 0F B6 C6 movzx ax, r14b \n"
" 00006952 66| 41/ 0F B6 46 movzx ax, byte ptr [r14 + 4] \n"
" 04 \n"
" \n"
" 00006958 41/ 0F B6 C6 movzx eax, r14b \n"
" 0000695C 41/ 0F B7 C6 movzx eax, r14w \n"
" 00006960 41/ 0F B6 46 movzx eax, byte ptr [r14 + 4] \n"
" 04 \n"
" 00006965 41/ 0F B7 46 movzx eax, word ptr [r14 + 4] \n"
" 04 \n"
" \n"
" 0000696A 49/ 0F B6 C6 movzx rax, r14b \n"
" 0000696E 49/ 0F B7 C6 movzx rax, r14w \n"
" 00006972 49/ 0F B6 46 movzx rax, byte ptr [r14 + 4] \n"
" 04 \n"
" 00006977 49/ 0F B7 46 movzx rax, word ptr [r14 + 4] \n"
" 04 \n"
" \n"
" \n"
" ; Source: r14, target: rcx \n"
" 0000697C B1 01 mov cl, 1 \n"
" 0000697E 66| B9 0001 mov cx, 1 \n"
" 00006982 B9 00000001 mov ecx, 1 \n"
" 00006987 48/ C7 C1 mov rcx, 1 \n"
" 00000001 \n"
" \n"
" 0000698E 41/ 8A CE mov cl, r14b \n"
" 00006991 66| 41/ 8B CE mov cx, r14w \n"
" 00006995 41/ 8B CE mov ecx, r14d \n"
" 00006998 49/ 8B CE mov rcx, r14 \n"
" \n"
" 0000699B 41/ 8A 4E FC mov cl, byte ptr [r14 - 4] \n"
" 0000699F 41/ 8A 4E 04 mov cl, byte ptr [r14 + 4] \n"
" 000069A3 66| 41/ 8B 4E mov cx, word ptr [r14 + 4] \n"
" 04 \n"
" 000069A8 41/ 8B 4E 04 mov ecx, dword ptr [r14 + 4] \n"
" 000069AC 49/ 8B 4E 04 mov rcx, qword ptr [r14 + 4] \n"
" \n"
" 000069B0 44/ 88 71 FC mov byte ptr [rcx - 4], r14b \n"
" 000069B4 44/ 88 71 04 mov byte ptr [rcx + 4], r14b \n"
" 000069B8 66| 44/ 89 71 mov word ptr [rcx + 4], r14w \n"
" 04 \n"
" 000069BD 44/ 89 71 04 mov dword ptr [rcx + 4], r14d \n"
" 000069C1 4C/ 89 71 04 mov qword ptr [rcx + 4], r14 \n"
" \n"
" 000069C5 66| 41/ 0F B6 CE movzx cx, r14b \n"
" 000069CA 66| 41/ 0F B6 4E movzx cx, byte ptr [r14 + 4] \n"
" 04 \n"
" \n"
" 000069D0 41/ 0F B6 CE movzx ecx, r14b \n"
" 000069D4 41/ 0F B7 CE movzx ecx, r14w \n"
" 000069D8 41/ 0F B6 4E movzx ecx, byte ptr [r14 + 4] \n"
" 04 \n"
" 000069DD 41/ 0F B7 4E movzx ecx, word ptr [r14 + 4] \n"
" 04 \n"
" \n"
" 000069E2 49/ 0F B6 CE movzx rcx, r14b \n"
" 000069E6 49/ 0F B7 CE movzx rcx, r14w \n"
" 000069EA 49/ 0F B6 4E movzx rcx, byte ptr [r14 + 4] \n"
" 04 \n"
" 000069EF 49/ 0F B7 4E movzx rcx, word ptr [r14 + 4] \n"
" 04 \n"
" \n"
" \n"
" ; Source: r14, target: rdx \n"
" 000069F4 B2 01 mov dl, 1 \n"
" 000069F6 66| BA 0001 mov dx, 1 \n"
" 000069FA BA 00000001 mov edx, 1 \n"
" 000069FF 48/ C7 C2 mov rdx, 1 \n"
" 00000001 \n"
" \n"
" 00006A06 41/ 8A D6 mov dl, r14b \n"
" 00006A09 66| 41/ 8B D6 mov dx, r14w \n"
" 00006A0D 41/ 8B D6 mov edx, r14d \n"
" 00006A10 49/ 8B D6 mov rdx, r14 \n"
" \n"
" 00006A13 41/ 8A 56 FC mov dl, byte ptr [r14 - 4] \n"
" 00006A17 41/ 8A 56 04 mov dl, byte ptr [r14 + 4] \n"
" 00006A1B 66| 41/ 8B 56 mov dx, word ptr [r14 + 4] \n"
" 04 \n"
" 00006A20 41/ 8B 56 04 mov edx, dword ptr [r14 + 4] \n"
" 00006A24 49/ 8B 56 04 mov rdx, qword ptr [r14 + 4] \n"
" \n"
" 00006A28 44/ 88 72 FC mov byte ptr [rdx - 4], r14b \n"
" 00006A2C 44/ 88 72 04 mov byte ptr [rdx + 4], r14b \n"
" 00006A30 66| 44/ 89 72 mov word ptr [rdx + 4], r14w \n"
" 04 \n"
" 00006A35 44/ 89 72 04 mov dword ptr [rdx + 4], r14d \n"
" 00006A39 4C/ 89 72 04 mov qword ptr [rdx + 4], r14 \n"
" \n"
" 00006A3D 66| 41/ 0F B6 D6 movzx dx, r14b \n"
" 00006A42 66| 41/ 0F B6 56 movzx dx, byte ptr [r14 + 4] \n"
" 04 \n"
" \n"
" 00006A48 41/ 0F B6 D6 movzx edx, r14b \n"
" 00006A4C 41/ 0F B7 D6 movzx edx, r14w \n"
" 00006A50 41/ 0F B6 56 movzx edx, byte ptr [r14 + 4] \n"
" 04 \n"
" 00006A55 41/ 0F B7 56 movzx edx, word ptr [r14 + 4] \n"
" 04 \n"
" \n"
" 00006A5A 49/ 0F B6 D6 movzx rdx, r14b \n"
" 00006A5E 49/ 0F B7 D6 movzx rdx, r14w \n"
" 00006A62 49/ 0F B6 56 movzx rdx, byte ptr [r14 + 4] \n"
" 04 \n"
" 00006A67 49/ 0F B7 56 movzx rdx, word ptr [r14 + 4] \n"
" 04 \n"
" \n"
" \n"
" ; Source: r14, target: rbx \n"
" 00006A6C B3 01 mov bl, 1 \n"
" 00006A6E 66| BB 0001 mov bx, 1 \n"
" 00006A72 BB 00000001 mov ebx, 1 \n"
" 00006A77 48/ C7 C3 mov rbx, 1 \n"
" 00000001 \n"
" \n"
" 00006A7E 41/ 8A DE mov bl, r14b \n"
" 00006A81 66| 41/ 8B DE mov bx, r14w \n"
" 00006A85 41/ 8B DE mov ebx, r14d \n"
" 00006A88 49/ 8B DE mov rbx, r14 \n"
" \n"
" 00006A8B 41/ 8A 5E FC mov bl, byte ptr [r14 - 4] \n"
" 00006A8F 41/ 8A 5E 04 mov bl, byte ptr [r14 + 4] \n"
" 00006A93 66| 41/ 8B 5E mov bx, word ptr [r14 + 4] \n"
" 04 \n"
" 00006A98 41/ 8B 5E 04 mov ebx, dword ptr [r14 + 4] \n"
" 00006A9C 49/ 8B 5E 04 mov rbx, qword ptr [r14 + 4] \n"
" \n"
" 00006AA0 44/ 88 73 FC mov byte ptr [rbx - 4], r14b \n"
" 00006AA4 44/ 88 73 04 mov byte ptr [rbx + 4], r14b \n"
" 00006AA8 66| 44/ 89 73 mov word ptr [rbx + 4], r14w \n"
" 04 \n"
" 00006AAD 44/ 89 73 04 mov dword ptr [rbx + 4], r14d \n"
" 00006AB1 4C/ 89 73 04 mov qword ptr [rbx + 4], r14 \n"
" \n"
" 00006AB5 66| 41/ 0F B6 DE movzx bx, r14b \n"
" 00006ABA 66| 41/ 0F B6 5E movzx bx, byte ptr [r14 + 4] \n"
" 04 \n"
" \n"
" 00006AC0 41/ 0F B6 DE movzx ebx, r14b \n"
" 00006AC4 41/ 0F B7 DE movzx ebx, r14w \n"
" 00006AC8 41/ 0F B6 5E movzx ebx, byte ptr [r14 + 4] \n";
ml64Output +=
" 04 \n"
" 00006ACD 41/ 0F B7 5E movzx ebx, word ptr [r14 + 4] \n"
" 04 \n"
" \n"
" 00006AD2 49/ 0F B6 DE movzx rbx, r14b \n"
" 00006AD6 49/ 0F B7 DE movzx rbx, r14w \n"
" 00006ADA 49/ 0F B6 5E movzx rbx, byte ptr [r14 + 4] \n"
" 04 \n"
" 00006ADF 49/ 0F B7 5E movzx rbx, word ptr [r14 + 4] \n"
" 04 \n"
" \n"
" \n"
" ; Source: r14, target: rsp \n"
" 00006AE4 40/ B4 01 mov spl, 1 \n"
" 00006AE7 66| BC 0001 mov sp, 1 \n"
" 00006AEB BC 00000001 mov esp, 1 \n"
" 00006AF0 48/ C7 C4 mov rsp, 1 \n"
" 00000001 \n"
" \n"
" 00006AF7 41/ 8A E6 mov spl, r14b \n"
" 00006AFA 66| 41/ 8B E6 mov sp, r14w \n"
" 00006AFE 41/ 8B E6 mov esp, r14d \n"
" 00006B01 49/ 8B E6 mov rsp, r14 \n"
" \n"
" 00006B04 41/ 8A 66 FC mov spl, byte ptr [r14 - 4] \n"
" 00006B08 41/ 8A 66 04 mov spl, byte ptr [r14 + 4] \n"
" 00006B0C 66| 41/ 8B 66 mov sp, word ptr [r14 + 4] \n"
" 04 \n"
" 00006B11 41/ 8B 66 04 mov esp, dword ptr [r14 + 4] \n"
" 00006B15 49/ 8B 66 04 mov rsp, qword ptr [r14 + 4] \n"
" \n"
" 00006B19 44/ 88 74 24 mov byte ptr [rsp - 4], r14b \n"
" FC \n"
" 00006B1E 44/ 88 74 24 mov byte ptr [rsp + 4], r14b \n"
" 04 \n"
" 00006B23 66| 44/ 89 74 24 mov word ptr [rsp + 4], r14w \n"
" 04 \n"
" 00006B29 44/ 89 74 24 mov dword ptr [rsp + 4], r14d \n"
" 04 \n"
" 00006B2E 4C/ 89 74 24 mov qword ptr [rsp + 4], r14 \n"
" 04 \n"
" \n"
" 00006B33 66| 41/ 0F B6 E6 movzx sp, r14b \n"
" 00006B38 66| 41/ 0F B6 66 movzx sp, byte ptr [r14 + 4] \n"
" 04 \n"
" \n"
" 00006B3E 41/ 0F B6 E6 movzx esp, r14b \n"
" 00006B42 41/ 0F B7 E6 movzx esp, r14w \n"
" 00006B46 41/ 0F B6 66 movzx esp, byte ptr [r14 + 4] \n"
" 04 \n"
" 00006B4B 41/ 0F B7 66 movzx esp, word ptr [r14 + 4] \n"
" 04 \n"
" \n"
" 00006B50 49/ 0F B6 E6 movzx rsp, r14b \n"
" 00006B54 49/ 0F B7 E6 movzx rsp, r14w \n"
" 00006B58 49/ 0F B6 66 movzx rsp, byte ptr [r14 + 4] \n"
" 04 \n"
" 00006B5D 49/ 0F B7 66 movzx rsp, word ptr [r14 + 4] \n"
" 04 \n"
" \n"
" \n"
" ; Source: r14, target: rbp \n"
" 00006B62 40/ B5 01 mov bpl, 1 \n"
" 00006B65 66| BD 0001 mov bp, 1 \n"
" 00006B69 BD 00000001 mov ebp, 1 \n"
" 00006B6E 48/ C7 C5 mov rbp, 1 \n"
" 00000001 \n"
" \n"
" 00006B75 41/ 8A EE mov bpl, r14b \n"
" 00006B78 66| 41/ 8B EE mov bp, r14w \n"
" 00006B7C 41/ 8B EE mov ebp, r14d \n"
" 00006B7F 49/ 8B EE mov rbp, r14 \n"
" \n"
" 00006B82 41/ 8A 6E FC mov bpl, byte ptr [r14 - 4] \n"
" 00006B86 41/ 8A 6E 04 mov bpl, byte ptr [r14 + 4] \n"
" 00006B8A 66| 41/ 8B 6E mov bp, word ptr [r14 + 4] \n"
" 04 \n"
" 00006B8F 41/ 8B 6E 04 mov ebp, dword ptr [r14 + 4] \n"
" 00006B93 49/ 8B 6E 04 mov rbp, qword ptr [r14 + 4] \n"
" \n"
" 00006B97 44/ 88 75 FC mov byte ptr [rbp - 4], r14b \n"
" 00006B9B 44/ 88 75 04 mov byte ptr [rbp + 4], r14b \n"
" 00006B9F 66| 44/ 89 75 mov word ptr [rbp + 4], r14w \n"
" 04 \n"
" 00006BA4 44/ 89 75 04 mov dword ptr [rbp + 4], r14d \n"
" 00006BA8 4C/ 89 75 04 mov qword ptr [rbp + 4], r14 \n"
" \n"
" 00006BAC 66| 41/ 0F B6 EE movzx bp, r14b \n"
" 00006BB1 66| 41/ 0F B6 6E movzx bp, byte ptr [r14 + 4] \n"
" 04 \n"
" \n"
" 00006BB7 41/ 0F B6 EE movzx ebp, r14b \n"
" 00006BBB 41/ 0F B7 EE movzx ebp, r14w \n"
" 00006BBF 41/ 0F B6 6E movzx ebp, byte ptr [r14 + 4] \n"
" 04 \n"
" 00006BC4 41/ 0F B7 6E movzx ebp, word ptr [r14 + 4] \n"
" 04 \n"
" \n"
" 00006BC9 49/ 0F B6 EE movzx rbp, r14b \n"
" 00006BCD 49/ 0F B7 EE movzx rbp, r14w \n"
" 00006BD1 49/ 0F B6 6E movzx rbp, byte ptr [r14 + 4] \n"
" 04 \n"
" 00006BD6 49/ 0F B7 6E movzx rbp, word ptr [r14 + 4] \n"
" 04 \n"
" \n"
" \n"
" ; Source: r14, target: rsi \n"
" 00006BDB 40/ B7 01 mov dil, 1 \n"
" 00006BDE 66| BE 0001 mov si, 1 \n"
" 00006BE2 BE 00000001 mov esi, 1 \n"
" 00006BE7 48/ C7 C6 mov rsi, 1 \n"
" 00000001 \n"
" \n"
" 00006BEE 41/ 8A FE mov dil, r14b \n"
" 00006BF1 66| 41/ 8B F6 mov si, r14w \n"
" 00006BF5 41/ 8B F6 mov esi, r14d \n"
" 00006BF8 49/ 8B F6 mov rsi, r14 \n"
" \n"
" 00006BFB 41/ 8A 7E FC mov dil, byte ptr [r14 - 4] \n"
" 00006BFF 41/ 8A 7E 04 mov dil, byte ptr [r14 + 4] \n"
" 00006C03 66| 41/ 8B 76 mov si, word ptr [r14 + 4] \n"
" 04 \n"
" 00006C08 41/ 8B 76 04 mov esi, dword ptr [r14 + 4] \n"
" 00006C0C 49/ 8B 76 04 mov rsi, qword ptr [r14 + 4] \n"
" \n"
" 00006C10 44/ 88 76 FC mov byte ptr [rsi - 4], r14b \n"
" 00006C14 44/ 88 76 04 mov byte ptr [rsi + 4], r14b \n"
" 00006C18 66| 44/ 89 76 mov word ptr [rsi + 4], r14w \n"
" 04 \n"
" 00006C1D 44/ 89 76 04 mov dword ptr [rsi + 4], r14d \n"
" 00006C21 4C/ 89 76 04 mov qword ptr [rsi + 4], r14 \n"
" \n"
" 00006C25 66| 41/ 0F B6 F6 movzx si, r14b \n"
" 00006C2A 66| 41/ 0F B6 76 movzx si, byte ptr [r14 + 4] \n"
" 04 \n"
" \n"
" 00006C30 41/ 0F B6 F6 movzx esi, r14b \n"
" 00006C34 41/ 0F B7 F6 movzx esi, r14w \n"
" 00006C38 41/ 0F B6 76 movzx esi, byte ptr [r14 + 4] \n"
" 04 \n"
" 00006C3D 41/ 0F B7 76 movzx esi, word ptr [r14 + 4] \n"
" 04 \n"
" \n"
" 00006C42 49/ 0F B6 F6 movzx rsi, r14b \n"
" 00006C46 49/ 0F B7 F6 movzx rsi, r14w \n"
" 00006C4A 49/ 0F B6 76 movzx rsi, byte ptr [r14 + 4] \n"
" 04 \n"
" 00006C4F 49/ 0F B7 76 movzx rsi, word ptr [r14 + 4] \n"
" 04 \n"
" \n"
" \n"
" ; Source: r14, target: rdi \n"
" 00006C54 40/ B6 01 mov sil, 1 \n"
" 00006C57 66| BF 0001 mov di, 1 \n"
" 00006C5B BF 00000001 mov edi, 1 \n"
" 00006C60 48/ C7 C7 mov rdi, 1 \n"
" 00000001 \n"
" \n"
" 00006C67 41/ 8A F6 mov sil, r14b \n"
" 00006C6A 66| 41/ 8B FE mov di, r14w \n"
" 00006C6E 41/ 8B FE mov edi, r14d \n"
" 00006C71 49/ 8B FE mov rdi, r14 \n"
" \n"
" 00006C74 41/ 8A 76 FC mov sil, byte ptr [r14 - 4] \n"
" 00006C78 41/ 8A 76 04 mov sil, byte ptr [r14 + 4] \n"
" 00006C7C 66| 41/ 8B 7E mov di, word ptr [r14 + 4] \n"
" 04 \n"
" 00006C81 41/ 8B 7E 04 mov edi, dword ptr [r14 + 4] \n"
" 00006C85 49/ 8B 7E 04 mov rdi, qword ptr [r14 + 4] \n"
" \n"
" 00006C89 44/ 88 77 FC mov byte ptr [rdi - 4], r14b \n"
" 00006C8D 44/ 88 77 04 mov byte ptr [rdi + 4], r14b \n"
" 00006C91 66| 44/ 89 77 mov word ptr [rdi + 4], r14w \n"
" 04 \n"
" 00006C96 44/ 89 77 04 mov dword ptr [rdi + 4], r14d \n"
" 00006C9A 4C/ 89 77 04 mov qword ptr [rdi + 4], r14 \n"
" \n"
" 00006C9E 66| 41/ 0F B6 FE movzx di, r14b \n"
" 00006CA3 66| 41/ 0F B6 7E movzx di, byte ptr [r14 + 4] \n"
" 04 \n"
" \n"
" 00006CA9 41/ 0F B6 FE movzx edi, r14b \n"
" 00006CAD 41/ 0F B7 FE movzx edi, r14w \n"
" 00006CB1 41/ 0F B6 7E movzx edi, byte ptr [r14 + 4] \n"
" 04 \n"
" 00006CB6 41/ 0F B7 7E movzx edi, word ptr [r14 + 4] \n"
" 04 \n"
" \n"
" 00006CBB 49/ 0F B6 FE movzx rdi, r14b \n"
" 00006CBF 49/ 0F B7 FE movzx rdi, r14w \n"
" 00006CC3 49/ 0F B6 7E movzx rdi, byte ptr [r14 + 4] \n"
" 04 \n"
" 00006CC8 49/ 0F B7 7E movzx rdi, word ptr [r14 + 4] \n"
" 04 \n"
" \n"
" \n"
" ; Source: r14, target: r8 \n"
" 00006CCD 41/ B0 01 mov r8b, 1 \n"
" 00006CD0 66| 41/ B8 mov r8w, 1 \n"
" 0001 \n"
" 00006CD5 41/ B8 mov r8d, 1 \n"
" 00000001 \n"
" 00006CDB 49/ C7 C0 mov r8, 1 \n"
" 00000001 \n"
" \n"
" 00006CE2 45/ 8A C6 mov r8b, r14b \n"
" 00006CE5 66| 45/ 8B C6 mov r8w, r14w \n"
" 00006CE9 45/ 8B C6 mov r8d, r14d \n"
" 00006CEC 4D/ 8B C6 mov r8, r14 \n"
" \n"
" 00006CEF 45/ 8A 46 FC mov r8b, byte ptr [r14 - 4] \n"
" 00006CF3 45/ 8A 46 04 mov r8b, byte ptr [r14 + 4] \n"
" 00006CF7 66| 45/ 8B 46 mov r8w, word ptr [r14 + 4] \n"
" 04 \n"
" 00006CFC 45/ 8B 46 04 mov r8d, dword ptr [r14 + 4] \n"
" 00006D00 4D/ 8B 46 04 mov r8, qword ptr [r14 + 4] \n"
" \n"
" 00006D04 45/ 88 70 FC mov byte ptr [r8 - 4], r14b \n"
" 00006D08 45/ 88 70 04 mov byte ptr [r8 + 4], r14b \n"
" 00006D0C 66| 45/ 89 70 mov word ptr [r8 + 4], r14w \n"
" 04 \n"
" 00006D11 45/ 89 70 04 mov dword ptr [r8 + 4], r14d \n"
" 00006D15 4D/ 89 70 04 mov qword ptr [r8 + 4], r14 \n"
" \n"
" 00006D19 66| 45/ 0F B6 C6 movzx r8w, r14b \n"
" 00006D1E 66| 45/ 0F B6 46 movzx r8w, byte ptr [r14 + 4] \n"
" 04 \n"
" \n"
" 00006D24 45/ 0F B6 C6 movzx r8d, r14b \n"
" 00006D28 45/ 0F B7 C6 movzx r8d, r14w \n"
" 00006D2C 45/ 0F B6 46 movzx r8d, byte ptr [r14 + 4] \n"
" 04 \n"
" 00006D31 45/ 0F B7 46 movzx r8d, word ptr [r14 + 4] \n"
" 04 \n"
" \n"
" 00006D36 4D/ 0F B6 C6 movzx r8, r14b \n"
" 00006D3A 4D/ 0F B7 C6 movzx r8, r14w \n"
" 00006D3E 4D/ 0F B6 46 movzx r8, byte ptr [r14 + 4] \n"
" 04 \n"
" 00006D43 4D/ 0F B7 46 movzx r8, word ptr [r14 + 4] \n"
" 04 \n"
" \n"
" \n"
" ; Source: r14, target: r9 \n"
" 00006D48 41/ B1 01 mov r9b, 1 \n"
" 00006D4B 66| 41/ B9 mov r9w, 1 \n"
" 0001 \n"
" 00006D50 41/ B9 mov r9d, 1 \n"
" 00000001 \n"
" 00006D56 49/ C7 C1 mov r9, 1 \n"
" 00000001 \n"
" \n"
" 00006D5D 45/ 8A CE mov r9b, r14b \n"
" 00006D60 66| 45/ 8B CE mov r9w, r14w \n"
" 00006D64 45/ 8B CE mov r9d, r14d \n"
" 00006D67 4D/ 8B CE mov r9, r14 \n"
" \n"
" 00006D6A 45/ 8A 4E FC mov r9b, byte ptr [r14 - 4] \n"
" 00006D6E 45/ 8A 4E 04 mov r9b, byte ptr [r14 + 4] \n"
" 00006D72 66| 45/ 8B 4E mov r9w, word ptr [r14 + 4] \n"
" 04 \n"
" 00006D77 45/ 8B 4E 04 mov r9d, dword ptr [r14 + 4] \n"
" 00006D7B 4D/ 8B 4E 04 mov r9, qword ptr [r14 + 4] \n"
" \n"
" 00006D7F 45/ 88 71 FC mov byte ptr [r9 - 4], r14b \n"
" 00006D83 45/ 88 71 04 mov byte ptr [r9 + 4], r14b \n"
" 00006D87 66| 45/ 89 71 mov word ptr [r9 + 4], r14w \n"
" 04 \n"
" 00006D8C 45/ 89 71 04 mov dword ptr [r9 + 4], r14d \n"
" 00006D90 4D/ 89 71 04 mov qword ptr [r9 + 4], r14 \n"
" \n"
" 00006D94 66| 45/ 0F B6 CE movzx r9w, r14b \n"
" 00006D99 66| 45/ 0F B6 4E movzx r9w, byte ptr [r14 + 4] \n"
" 04 \n"
" \n"
" 00006D9F 45/ 0F B6 CE movzx r9d, r14b \n"
" 00006DA3 45/ 0F B7 CE movzx r9d, r14w \n"
" 00006DA7 45/ 0F B6 4E movzx r9d, byte ptr [r14 + 4] \n"
" 04 \n"
" 00006DAC 45/ 0F B7 4E movzx r9d, word ptr [r14 + 4] \n"
" 04 \n"
" \n"
" 00006DB1 4D/ 0F B6 CE movzx r9, r14b \n"
" 00006DB5 4D/ 0F B7 CE movzx r9, r14w \n"
" 00006DB9 4D/ 0F B6 4E movzx r9, byte ptr [r14 + 4] \n"
" 04 \n"
" 00006DBE 4D/ 0F B7 4E movzx r9, word ptr [r14 + 4] \n"
" 04 \n"
" \n"
" \n"
" ; Source: r14, target: r10 \n"
" 00006DC3 41/ B2 01 mov r10b, 1 \n"
" 00006DC6 66| 41/ BA mov r10w, 1 \n"
" 0001 \n"
" 00006DCB 41/ BA mov r10d, 1 \n"
" 00000001 \n"
" 00006DD1 49/ C7 C2 mov r10, 1 \n"
" 00000001 \n"
" \n"
" 00006DD8 45/ 8A D6 mov r10b, r14b \n"
" 00006DDB 66| 45/ 8B D6 mov r10w, r14w \n"
" 00006DDF 45/ 8B D6 mov r10d, r14d \n"
" 00006DE2 4D/ 8B D6 mov r10, r14 \n"
" \n"
" 00006DE5 45/ 8A 56 FC mov r10b, byte ptr [r14 - 4] \n"
" 00006DE9 45/ 8A 56 04 mov r10b, byte ptr [r14 + 4] \n"
" 00006DED 66| 45/ 8B 56 mov r10w, word ptr [r14 + 4] \n"
" 04 \n"
" 00006DF2 45/ 8B 56 04 mov r10d, dword ptr [r14 + 4] \n"
" 00006DF6 4D/ 8B 56 04 mov r10, qword ptr [r14 + 4] \n"
" \n"
" 00006DFA 45/ 88 72 FC mov byte ptr [r10 - 4], r14b \n"
" 00006DFE 45/ 88 72 04 mov byte ptr [r10 + 4], r14b \n"
" 00006E02 66| 45/ 89 72 mov word ptr [r10 + 4], r14w \n"
" 04 \n"
" 00006E07 45/ 89 72 04 mov dword ptr [r10 + 4], r14d \n"
" 00006E0B 4D/ 89 72 04 mov qword ptr [r10 + 4], r14 \n"
" \n"
" 00006E0F 66| 45/ 0F B6 D6 movzx r10w, r14b \n"
" 00006E14 66| 45/ 0F B6 56 movzx r10w, byte ptr [r14 + 4] \n"
" 04 \n"
" \n"
" 00006E1A 45/ 0F B6 D6 movzx r10d, r14b \n"
" 00006E1E 45/ 0F B7 D6 movzx r10d, r14w \n"
" 00006E22 45/ 0F B6 56 movzx r10d, byte ptr [r14 + 4] \n"
" 04 \n"
" 00006E27 45/ 0F B7 56 movzx r10d, word ptr [r14 + 4] \n"
" 04 \n"
" \n"
" 00006E2C 4D/ 0F B6 D6 movzx r10, r14b \n"
" 00006E30 4D/ 0F B7 D6 movzx r10, r14w \n"
" 00006E34 4D/ 0F B6 56 movzx r10, byte ptr [r14 + 4] \n"
" 04 \n"
" 00006E39 4D/ 0F B7 56 movzx r10, word ptr [r14 + 4] \n"
" 04 \n"
" \n"
" \n"
" ; Source: r14, target: r11 \n"
" 00006E3E 41/ B3 01 mov r11b, 1 \n"
" 00006E41 66| 41/ BB mov r11w, 1 \n"
" 0001 \n"
" 00006E46 41/ BB mov r11d, 1 \n"
" 00000001 \n"
" 00006E4C 49/ C7 C3 mov r11, 1 \n"
" 00000001 \n"
" \n"
" 00006E53 45/ 8A DE mov r11b, r14b \n"
" 00006E56 66| 45/ 8B DE mov r11w, r14w \n"
" 00006E5A 45/ 8B DE mov r11d, r14d \n"
" 00006E5D 4D/ 8B DE mov r11, r14 \n"
" \n"
" 00006E60 45/ 8A 5E FC mov r11b, byte ptr [r14 - 4] \n"
" 00006E64 45/ 8A 5E 04 mov r11b, byte ptr [r14 + 4] \n"
" 00006E68 66| 45/ 8B 5E mov r11w, word ptr [r14 + 4] \n"
" 04 \n"
" 00006E6D 45/ 8B 5E 04 mov r11d, dword ptr [r14 + 4] \n"
" 00006E71 4D/ 8B 5E 04 mov r11, qword ptr [r14 + 4] \n"
" \n"
" 00006E75 45/ 88 73 FC mov byte ptr [r11 - 4], r14b \n"
" 00006E79 45/ 88 73 04 mov byte ptr [r11 + 4], r14b \n"
" 00006E7D 66| 45/ 89 73 mov word ptr [r11 + 4], r14w \n"
" 04 \n"
" 00006E82 45/ 89 73 04 mov dword ptr [r11 + 4], r14d \n"
" 00006E86 4D/ 89 73 04 mov qword ptr [r11 + 4], r14 \n"
" \n"
" 00006E8A 66| 45/ 0F B6 DE movzx r11w, r14b \n"
" 00006E8F 66| 45/ 0F B6 5E movzx r11w, byte ptr [r14 + 4] \n"
" 04 \n"
" \n"
" 00006E95 45/ 0F B6 DE movzx r11d, r14b \n"
" 00006E99 45/ 0F B7 DE movzx r11d, r14w \n"
" 00006E9D 45/ 0F B6 5E movzx r11d, byte ptr [r14 + 4] \n"
" 04 \n"
" 00006EA2 45/ 0F B7 5E movzx r11d, word ptr [r14 + 4] \n"
" 04 \n"
" \n"
" 00006EA7 4D/ 0F B6 DE movzx r11, r14b \n"
" 00006EAB 4D/ 0F B7 DE movzx r11, r14w \n"
" 00006EAF 4D/ 0F B6 5E movzx r11, byte ptr [r14 + 4] \n"
" 04 \n"
" 00006EB4 4D/ 0F B7 5E movzx r11, word ptr [r14 + 4] \n"
" 04 \n"
" \n"
" \n"
" ; Source: r14, target: r12 \n"
" 00006EB9 41/ B4 01 mov r12b, 1 \n"
" 00006EBC 66| 41/ BC mov r12w, 1 \n"
" 0001 \n"
" 00006EC1 41/ BC mov r12d, 1 \n"
" 00000001 \n"
" 00006EC7 49/ C7 C4 mov r12, 1 \n"
" 00000001 \n"
" \n"
" 00006ECE 45/ 8A E6 mov r12b, r14b \n"
" 00006ED1 66| 45/ 8B E6 mov r12w, r14w \n"
" 00006ED5 45/ 8B E6 mov r12d, r14d \n"
" 00006ED8 4D/ 8B E6 mov r12, r14 \n"
" \n"
" 00006EDB 45/ 8A 66 FC mov r12b, byte ptr [r14 - 4] \n"
" 00006EDF 45/ 8A 66 04 mov r12b, byte ptr [r14 + 4] \n"
" 00006EE3 66| 45/ 8B 66 mov r12w, word ptr [r14 + 4] \n"
" 04 \n"
" 00006EE8 45/ 8B 66 04 mov r12d, dword ptr [r14 + 4] \n"
" 00006EEC 4D/ 8B 66 04 mov r12, qword ptr [r14 + 4] \n"
" \n"
" 00006EF0 45/ 88 74 24 mov byte ptr [r12 - 4], r14b \n"
" FC \n"
" 00006EF5 45/ 88 74 24 mov byte ptr [r12 + 4], r14b \n"
" 04 \n"
" 00006EFA 66| 45/ 89 74 24 mov word ptr [r12 + 4], r14w \n"
" 04 \n"
" 00006F00 45/ 89 74 24 mov dword ptr [r12 + 4], r14d \n"
" 04 \n"
" 00006F05 4D/ 89 74 24 mov qword ptr [r12 + 4], r14 \n"
" 04 \n"
" \n"
" 00006F0A 66| 45/ 0F B6 E6 movzx r12w, r14b \n"
" 00006F0F 66| 45/ 0F B6 66 movzx r12w, byte ptr [r14 + 4] \n"
" 04 \n"
" \n"
" 00006F15 45/ 0F B6 E6 movzx r12d, r14b \n"
" 00006F19 45/ 0F B7 E6 movzx r12d, r14w \n"
" 00006F1D 45/ 0F B6 66 movzx r12d, byte ptr [r14 + 4] \n"
" 04 \n"
" 00006F22 45/ 0F B7 66 movzx r12d, word ptr [r14 + 4] \n"
" 04 \n"
" \n"
" 00006F27 4D/ 0F B6 E6 movzx r12, r14b \n"
" 00006F2B 4D/ 0F B7 E6 movzx r12, r14w \n"
" 00006F2F 4D/ 0F B6 66 movzx r12, byte ptr [r14 + 4] \n"
" 04 \n"
" 00006F34 4D/ 0F B7 66 movzx r12, word ptr [r14 + 4] \n"
" 04 \n"
" \n"
" \n"
" ; Source: r14, target: r13 \n"
" 00006F39 41/ B5 01 mov r13b, 1 \n"
" 00006F3C 66| 41/ BD mov r13w, 1 \n"
" 0001 \n"
" 00006F41 41/ BD mov r13d, 1 \n"
" 00000001 \n"
" 00006F47 49/ C7 C5 mov r13, 1 \n"
" 00000001 \n"
" \n"
" 00006F4E 45/ 8A EE mov r13b, r14b \n"
" 00006F51 66| 45/ 8B EE mov r13w, r14w \n"
" 00006F55 45/ 8B EE mov r13d, r14d \n"
" 00006F58 4D/ 8B EE mov r13, r14 \n"
" \n"
" 00006F5B 45/ 8A 6E FC mov r13b, byte ptr [r14 - 4] \n"
" 00006F5F 45/ 8A 6E 04 mov r13b, byte ptr [r14 + 4] \n"
" 00006F63 66| 45/ 8B 6E mov r13w, word ptr [r14 + 4] \n"
" 04 \n"
" 00006F68 45/ 8B 6E 04 mov r13d, dword ptr [r14 + 4] \n"
" 00006F6C 4D/ 8B 6E 04 mov r13, qword ptr [r14 + 4] \n"
" \n"
" 00006F70 45/ 88 75 FC mov byte ptr [r13 - 4], r14b \n"
" 00006F74 45/ 88 75 04 mov byte ptr [r13 + 4], r14b \n"
" 00006F78 66| 45/ 89 75 mov word ptr [r13 + 4], r14w \n"
" 04 \n"
" 00006F7D 45/ 89 75 04 mov dword ptr [r13 + 4], r14d \n"
" 00006F81 4D/ 89 75 04 mov qword ptr [r13 + 4], r14 \n"
" \n"
" 00006F85 66| 45/ 0F B6 EE movzx r13w, r14b \n"
" 00006F8A 66| 45/ 0F B6 6E movzx r13w, byte ptr [r14 + 4] \n"
" 04 \n"
" \n"
" 00006F90 45/ 0F B6 EE movzx r13d, r14b \n"
" 00006F94 45/ 0F B7 EE movzx r13d, r14w \n"
" 00006F98 45/ 0F B6 6E movzx r13d, byte ptr [r14 + 4] \n"
" 04 \n"
" 00006F9D 45/ 0F B7 6E movzx r13d, word ptr [r14 + 4] \n"
" 04 \n"
" \n"
" 00006FA2 4D/ 0F B6 EE movzx r13, r14b \n"
" 00006FA6 4D/ 0F B7 EE movzx r13, r14w \n"
" 00006FAA 4D/ 0F B6 6E movzx r13, byte ptr [r14 + 4] \n"
" 04 \n"
" 00006FAF 4D/ 0F B7 6E movzx r13, word ptr [r14 + 4] \n"
" 04 \n"
" \n"
" \n"
" ; Source: r14, target: r14 \n"
" 00006FB4 41/ B6 01 mov r14b, 1 \n"
" 00006FB7 66| 41/ BE mov r14w, 1 \n"
" 0001 \n"
" 00006FBC 41/ BE mov r14d, 1 \n"
" 00000001 \n"
" 00006FC2 49/ C7 C6 mov r14, 1 \n"
" 00000001 \n"
" \n"
" 00006FC9 45/ 8A F6 mov r14b, r14b \n"
" 00006FCC 66| 45/ 8B F6 mov r14w, r14w \n"
" 00006FD0 45/ 8B F6 mov r14d, r14d \n"
" 00006FD3 4D/ 8B F6 mov r14, r14 \n"
" \n"
" 00006FD6 45/ 8A 76 FC mov r14b, byte ptr [r14 - 4] \n"
" 00006FDA 45/ 8A 76 04 mov r14b, byte ptr [r14 + 4] \n"
" 00006FDE 66| 45/ 8B 76 mov r14w, word ptr [r14 + 4] \n"
" 04 \n"
" 00006FE3 45/ 8B 76 04 mov r14d, dword ptr [r14 + 4] \n"
" 00006FE7 4D/ 8B 76 04 mov r14, qword ptr [r14 + 4] \n"
" \n"
" 00006FEB 45/ 88 76 FC mov byte ptr [r14 - 4], r14b \n"
" 00006FEF 45/ 88 76 04 mov byte ptr [r14 + 4], r14b \n"
" 00006FF3 66| 45/ 89 76 mov word ptr [r14 + 4], r14w \n"
" 04 \n"
" 00006FF8 45/ 89 76 04 mov dword ptr [r14 + 4], r14d \n"
" 00006FFC 4D/ 89 76 04 mov qword ptr [r14 + 4], r14 \n"
" \n"
" 00007000 66| 45/ 0F B6 F6 movzx r14w, r14b \n"
" 00007005 66| 45/ 0F B6 76 movzx r14w, byte ptr [r14 + 4] \n"
" 04 \n"
" \n"
" 0000700B 45/ 0F B6 F6 movzx r14d, r14b \n"
" 0000700F 45/ 0F B7 F6 movzx r14d, r14w \n"
" 00007013 45/ 0F B6 76 movzx r14d, byte ptr [r14 + 4] \n"
" 04 \n"
" 00007018 45/ 0F B7 76 movzx r14d, word ptr [r14 + 4] \n"
" 04 \n"
" \n"
" 0000701D 4D/ 0F B6 F6 movzx r14, r14b \n"
" 00007021 4D/ 0F B7 F6 movzx r14, r14w \n"
" 00007025 4D/ 0F B6 76 movzx r14, byte ptr [r14 + 4] \n"
" 04 \n"
" 0000702A 4D/ 0F B7 76 movzx r14, word ptr [r14 + 4] \n"
" 04 \n"
" \n"
" \n"
" ; Source: r14, target: r15 \n"
" 0000702F 41/ B7 01 mov r15b, 1 \n"
" 00007032 66| 41/ BF mov r15w, 1 \n"
" 0001 \n"
" 00007037 41/ BF mov r15d, 1 \n"
" 00000001 \n"
" 0000703D 49/ C7 C7 mov r15, 1 \n"
" 00000001 \n"
" \n"
" 00007044 45/ 8A FE mov r15b, r14b \n"
" 00007047 66| 45/ 8B FE mov r15w, r14w \n"
" 0000704B 45/ 8B FE mov r15d, r14d \n"
" 0000704E 4D/ 8B FE mov r15, r14 \n"
" \n"
" 00007051 45/ 8A 7E FC mov r15b, byte ptr [r14 - 4] \n"
" 00007055 45/ 8A 7E 04 mov r15b, byte ptr [r14 + 4] \n"
" 00007059 66| 45/ 8B 7E mov r15w, word ptr [r14 + 4] \n"
" 04 \n"
" 0000705E 45/ 8B 7E 04 mov r15d, dword ptr [r14 + 4] \n"
" 00007062 4D/ 8B 7E 04 mov r15, qword ptr [r14 + 4] \n"
" \n";
ml64Output +=
" 00007066 45/ 88 77 FC mov byte ptr [r15 - 4], r14b \n"
" 0000706A 45/ 88 77 04 mov byte ptr [r15 + 4], r14b \n"
" 0000706E 66| 45/ 89 77 mov word ptr [r15 + 4], r14w \n"
" 04 \n"
" 00007073 45/ 89 77 04 mov dword ptr [r15 + 4], r14d \n"
" 00007077 4D/ 89 77 04 mov qword ptr [r15 + 4], r14 \n"
" \n"
" 0000707B 66| 45/ 0F B6 FE movzx r15w, r14b \n"
" 00007080 66| 45/ 0F B6 7E movzx r15w, byte ptr [r14 + 4] \n"
" 04 \n"
" \n"
" 00007086 45/ 0F B6 FE movzx r15d, r14b \n"
" 0000708A 45/ 0F B7 FE movzx r15d, r14w \n"
" 0000708E 45/ 0F B6 7E movzx r15d, byte ptr [r14 + 4] \n"
" 04 \n"
" 00007093 45/ 0F B7 7E movzx r15d, word ptr [r14 + 4] \n"
" 04 \n"
" \n"
" 00007098 4D/ 0F B6 FE movzx r15, r14b \n"
" 0000709C 4D/ 0F B7 FE movzx r15, r14w \n"
" 000070A0 4D/ 0F B6 7E movzx r15, byte ptr [r14 + 4] \n"
" 04 \n"
" 000070A5 4D/ 0F B7 7E movzx r15, word ptr [r14 + 4] \n"
" 04 \n"
" \n"
" \n"
" ; Source: r15, target: rax \n"
" 000070AA B0 01 mov al, 1 \n"
" 000070AC 66| B8 0001 mov ax, 1 \n"
" 000070B0 B8 00000001 mov eax, 1 \n"
" 000070B5 48/ C7 C0 mov rax, 1 \n"
" 00000001 \n"
" \n"
" 000070BC 41/ 8A C7 mov al, r15b \n"
" 000070BF 66| 41/ 8B C7 mov ax, r15w \n"
" 000070C3 41/ 8B C7 mov eax, r15d \n"
" 000070C6 49/ 8B C7 mov rax, r15 \n"
" \n"
" 000070C9 41/ 8A 47 FC mov al, byte ptr [r15 - 4] \n"
" 000070CD 41/ 8A 47 04 mov al, byte ptr [r15 + 4] \n"
" 000070D1 66| 41/ 8B 47 mov ax, word ptr [r15 + 4] \n"
" 04 \n"
" 000070D6 41/ 8B 47 04 mov eax, dword ptr [r15 + 4] \n"
" 000070DA 49/ 8B 47 04 mov rax, qword ptr [r15 + 4] \n"
" \n"
" 000070DE 44/ 88 78 FC mov byte ptr [rax - 4], r15b \n"
" 000070E2 44/ 88 78 04 mov byte ptr [rax + 4], r15b \n"
" 000070E6 66| 44/ 89 78 mov word ptr [rax + 4], r15w \n"
" 04 \n"
" 000070EB 44/ 89 78 04 mov dword ptr [rax + 4], r15d \n"
" 000070EF 4C/ 89 78 04 mov qword ptr [rax + 4], r15 \n"
" \n"
" 000070F3 66| 41/ 0F B6 C7 movzx ax, r15b \n"
" 000070F8 66| 41/ 0F B6 47 movzx ax, byte ptr [r15 + 4] \n"
" 04 \n"
" \n"
" 000070FE 41/ 0F B6 C7 movzx eax, r15b \n"
" 00007102 41/ 0F B7 C7 movzx eax, r15w \n"
" 00007106 41/ 0F B6 47 movzx eax, byte ptr [r15 + 4] \n"
" 04 \n"
" 0000710B 41/ 0F B7 47 movzx eax, word ptr [r15 + 4] \n"
" 04 \n"
" \n"
" 00007110 49/ 0F B6 C7 movzx rax, r15b \n"
" 00007114 49/ 0F B7 C7 movzx rax, r15w \n"
" 00007118 49/ 0F B6 47 movzx rax, byte ptr [r15 + 4] \n"
" 04 \n"
" 0000711D 49/ 0F B7 47 movzx rax, word ptr [r15 + 4] \n"
" 04 \n"
" \n"
" \n"
" ; Source: r15, target: rcx \n"
" 00007122 B1 01 mov cl, 1 \n"
" 00007124 66| B9 0001 mov cx, 1 \n"
" 00007128 B9 00000001 mov ecx, 1 \n"
" 0000712D 48/ C7 C1 mov rcx, 1 \n"
" 00000001 \n"
" \n"
" 00007134 41/ 8A CF mov cl, r15b \n"
" 00007137 66| 41/ 8B CF mov cx, r15w \n"
" 0000713B 41/ 8B CF mov ecx, r15d \n"
" 0000713E 49/ 8B CF mov rcx, r15 \n"
" \n"
" 00007141 41/ 8A 4F FC mov cl, byte ptr [r15 - 4] \n"
" 00007145 41/ 8A 4F 04 mov cl, byte ptr [r15 + 4] \n"
" 00007149 66| 41/ 8B 4F mov cx, word ptr [r15 + 4] \n"
" 04 \n"
" 0000714E 41/ 8B 4F 04 mov ecx, dword ptr [r15 + 4] \n"
" 00007152 49/ 8B 4F 04 mov rcx, qword ptr [r15 + 4] \n"
" \n"
" 00007156 44/ 88 79 FC mov byte ptr [rcx - 4], r15b \n"
" 0000715A 44/ 88 79 04 mov byte ptr [rcx + 4], r15b \n"
" 0000715E 66| 44/ 89 79 mov word ptr [rcx + 4], r15w \n"
" 04 \n"
" 00007163 44/ 89 79 04 mov dword ptr [rcx + 4], r15d \n"
" 00007167 4C/ 89 79 04 mov qword ptr [rcx + 4], r15 \n"
" \n"
" 0000716B 66| 41/ 0F B6 CF movzx cx, r15b \n"
" 00007170 66| 41/ 0F B6 4F movzx cx, byte ptr [r15 + 4] \n"
" 04 \n"
" \n"
" 00007176 41/ 0F B6 CF movzx ecx, r15b \n"
" 0000717A 41/ 0F B7 CF movzx ecx, r15w \n"
" 0000717E 41/ 0F B6 4F movzx ecx, byte ptr [r15 + 4] \n"
" 04 \n"
" 00007183 41/ 0F B7 4F movzx ecx, word ptr [r15 + 4] \n"
" 04 \n"
" \n"
" 00007188 49/ 0F B6 CF movzx rcx, r15b \n"
" 0000718C 49/ 0F B7 CF movzx rcx, r15w \n"
" 00007190 49/ 0F B6 4F movzx rcx, byte ptr [r15 + 4] \n"
" 04 \n"
" 00007195 49/ 0F B7 4F movzx rcx, word ptr [r15 + 4] \n"
" 04 \n"
" \n"
" \n"
" ; Source: r15, target: rdx \n"
" 0000719A B2 01 mov dl, 1 \n"
" 0000719C 66| BA 0001 mov dx, 1 \n"
" 000071A0 BA 00000001 mov edx, 1 \n"
" 000071A5 48/ C7 C2 mov rdx, 1 \n"
" 00000001 \n"
" \n"
" 000071AC 41/ 8A D7 mov dl, r15b \n"
" 000071AF 66| 41/ 8B D7 mov dx, r15w \n"
" 000071B3 41/ 8B D7 mov edx, r15d \n"
" 000071B6 49/ 8B D7 mov rdx, r15 \n"
" \n"
" 000071B9 41/ 8A 57 FC mov dl, byte ptr [r15 - 4] \n"
" 000071BD 41/ 8A 57 04 mov dl, byte ptr [r15 + 4] \n"
" 000071C1 66| 41/ 8B 57 mov dx, word ptr [r15 + 4] \n"
" 04 \n"
" 000071C6 41/ 8B 57 04 mov edx, dword ptr [r15 + 4] \n"
" 000071CA 49/ 8B 57 04 mov rdx, qword ptr [r15 + 4] \n"
" \n"
" 000071CE 44/ 88 7A FC mov byte ptr [rdx - 4], r15b \n"
" 000071D2 44/ 88 7A 04 mov byte ptr [rdx + 4], r15b \n"
" 000071D6 66| 44/ 89 7A mov word ptr [rdx + 4], r15w \n"
" 04 \n"
" 000071DB 44/ 89 7A 04 mov dword ptr [rdx + 4], r15d \n"
" 000071DF 4C/ 89 7A 04 mov qword ptr [rdx + 4], r15 \n"
" \n"
" 000071E3 66| 41/ 0F B6 D7 movzx dx, r15b \n"
" 000071E8 66| 41/ 0F B6 57 movzx dx, byte ptr [r15 + 4] \n"
" 04 \n"
" \n"
" 000071EE 41/ 0F B6 D7 movzx edx, r15b \n"
" 000071F2 41/ 0F B7 D7 movzx edx, r15w \n"
" 000071F6 41/ 0F B6 57 movzx edx, byte ptr [r15 + 4] \n"
" 04 \n"
" 000071FB 41/ 0F B7 57 movzx edx, word ptr [r15 + 4] \n"
" 04 \n"
" \n"
" 00007200 49/ 0F B6 D7 movzx rdx, r15b \n"
" 00007204 49/ 0F B7 D7 movzx rdx, r15w \n"
" 00007208 49/ 0F B6 57 movzx rdx, byte ptr [r15 + 4] \n"
" 04 \n"
" 0000720D 49/ 0F B7 57 movzx rdx, word ptr [r15 + 4] \n"
" 04 \n"
" \n"
" \n"
" ; Source: r15, target: rbx \n"
" 00007212 B3 01 mov bl, 1 \n"
" 00007214 66| BB 0001 mov bx, 1 \n"
" 00007218 BB 00000001 mov ebx, 1 \n"
" 0000721D 48/ C7 C3 mov rbx, 1 \n"
" 00000001 \n"
" \n"
" 00007224 41/ 8A DF mov bl, r15b \n"
" 00007227 66| 41/ 8B DF mov bx, r15w \n"
" 0000722B 41/ 8B DF mov ebx, r15d \n"
" 0000722E 49/ 8B DF mov rbx, r15 \n"
" \n"
" 00007231 41/ 8A 5F FC mov bl, byte ptr [r15 - 4] \n"
" 00007235 41/ 8A 5F 04 mov bl, byte ptr [r15 + 4] \n"
" 00007239 66| 41/ 8B 5F mov bx, word ptr [r15 + 4] \n"
" 04 \n"
" 0000723E 41/ 8B 5F 04 mov ebx, dword ptr [r15 + 4] \n"
" 00007242 49/ 8B 5F 04 mov rbx, qword ptr [r15 + 4] \n"
" \n"
" 00007246 44/ 88 7B FC mov byte ptr [rbx - 4], r15b \n"
" 0000724A 44/ 88 7B 04 mov byte ptr [rbx + 4], r15b \n"
" 0000724E 66| 44/ 89 7B mov word ptr [rbx + 4], r15w \n"
" 04 \n"
" 00007253 44/ 89 7B 04 mov dword ptr [rbx + 4], r15d \n"
" 00007257 4C/ 89 7B 04 mov qword ptr [rbx + 4], r15 \n"
" \n"
" 0000725B 66| 41/ 0F B6 DF movzx bx, r15b \n"
" 00007260 66| 41/ 0F B6 5F movzx bx, byte ptr [r15 + 4] \n"
" 04 \n"
" \n"
" 00007266 41/ 0F B6 DF movzx ebx, r15b \n"
" 0000726A 41/ 0F B7 DF movzx ebx, r15w \n"
" 0000726E 41/ 0F B6 5F movzx ebx, byte ptr [r15 + 4] \n"
" 04 \n"
" 00007273 41/ 0F B7 5F movzx ebx, word ptr [r15 + 4] \n"
" 04 \n"
" \n"
" 00007278 49/ 0F B6 DF movzx rbx, r15b \n"
" 0000727C 49/ 0F B7 DF movzx rbx, r15w \n"
" 00007280 49/ 0F B6 5F movzx rbx, byte ptr [r15 + 4] \n"
" 04 \n"
" 00007285 49/ 0F B7 5F movzx rbx, word ptr [r15 + 4] \n"
" 04 \n"
" \n"
" \n"
" ; Source: r15, target: rsp \n"
" 0000728A 40/ B4 01 mov spl, 1 \n"
" 0000728D 66| BC 0001 mov sp, 1 \n"
" 00007291 BC 00000001 mov esp, 1 \n"
" 00007296 48/ C7 C4 mov rsp, 1 \n"
" 00000001 \n"
" \n"
" 0000729D 41/ 8A E7 mov spl, r15b \n"
" 000072A0 66| 41/ 8B E7 mov sp, r15w \n"
" 000072A4 41/ 8B E7 mov esp, r15d \n"
" 000072A7 49/ 8B E7 mov rsp, r15 \n"
" \n"
" 000072AA 41/ 8A 67 FC mov spl, byte ptr [r15 - 4] \n"
" 000072AE 41/ 8A 67 04 mov spl, byte ptr [r15 + 4] \n"
" 000072B2 66| 41/ 8B 67 mov sp, word ptr [r15 + 4] \n"
" 04 \n"
" 000072B7 41/ 8B 67 04 mov esp, dword ptr [r15 + 4] \n"
" 000072BB 49/ 8B 67 04 mov rsp, qword ptr [r15 + 4] \n"
" \n"
" 000072BF 44/ 88 7C 24 mov byte ptr [rsp - 4], r15b \n"
" FC \n"
" 000072C4 44/ 88 7C 24 mov byte ptr [rsp + 4], r15b \n"
" 04 \n"
" 000072C9 66| 44/ 89 7C 24 mov word ptr [rsp + 4], r15w \n"
" 04 \n"
" 000072CF 44/ 89 7C 24 mov dword ptr [rsp + 4], r15d \n"
" 04 \n"
" 000072D4 4C/ 89 7C 24 mov qword ptr [rsp + 4], r15 \n"
" 04 \n"
" \n"
" 000072D9 66| 41/ 0F B6 E7 movzx sp, r15b \n"
" 000072DE 66| 41/ 0F B6 67 movzx sp, byte ptr [r15 + 4] \n"
" 04 \n"
" \n"
" 000072E4 41/ 0F B6 E7 movzx esp, r15b \n"
" 000072E8 41/ 0F B7 E7 movzx esp, r15w \n"
" 000072EC 41/ 0F B6 67 movzx esp, byte ptr [r15 + 4] \n"
" 04 \n"
" 000072F1 41/ 0F B7 67 movzx esp, word ptr [r15 + 4] \n"
" 04 \n"
" \n"
" 000072F6 49/ 0F B6 E7 movzx rsp, r15b \n"
" 000072FA 49/ 0F B7 E7 movzx rsp, r15w \n"
" 000072FE 49/ 0F B6 67 movzx rsp, byte ptr [r15 + 4] \n"
" 04 \n"
" 00007303 49/ 0F B7 67 movzx rsp, word ptr [r15 + 4] \n"
" 04 \n"
" \n"
" \n"
" ; Source: r15, target: rbp \n"
" 00007308 40/ B5 01 mov bpl, 1 \n"
" 0000730B 66| BD 0001 mov bp, 1 \n"
" 0000730F BD 00000001 mov ebp, 1 \n"
" 00007314 48/ C7 C5 mov rbp, 1 \n"
" 00000001 \n"
" \n"
" 0000731B 41/ 8A EF mov bpl, r15b \n"
" 0000731E 66| 41/ 8B EF mov bp, r15w \n"
" 00007322 41/ 8B EF mov ebp, r15d \n"
" 00007325 49/ 8B EF mov rbp, r15 \n"
" \n"
" 00007328 41/ 8A 6F FC mov bpl, byte ptr [r15 - 4] \n"
" 0000732C 41/ 8A 6F 04 mov bpl, byte ptr [r15 + 4] \n"
" 00007330 66| 41/ 8B 6F mov bp, word ptr [r15 + 4] \n"
" 04 \n"
" 00007335 41/ 8B 6F 04 mov ebp, dword ptr [r15 + 4] \n"
" 00007339 49/ 8B 6F 04 mov rbp, qword ptr [r15 + 4] \n"
" \n"
" 0000733D 44/ 88 7D FC mov byte ptr [rbp - 4], r15b \n"
" 00007341 44/ 88 7D 04 mov byte ptr [rbp + 4], r15b \n"
" 00007345 66| 44/ 89 7D mov word ptr [rbp + 4], r15w \n"
" 04 \n"
" 0000734A 44/ 89 7D 04 mov dword ptr [rbp + 4], r15d \n"
" 0000734E 4C/ 89 7D 04 mov qword ptr [rbp + 4], r15 \n"
" \n"
" 00007352 66| 41/ 0F B6 EF movzx bp, r15b \n"
" 00007357 66| 41/ 0F B6 6F movzx bp, byte ptr [r15 + 4] \n"
" 04 \n"
" \n"
" 0000735D 41/ 0F B6 EF movzx ebp, r15b \n"
" 00007361 41/ 0F B7 EF movzx ebp, r15w \n"
" 00007365 41/ 0F B6 6F movzx ebp, byte ptr [r15 + 4] \n"
" 04 \n"
" 0000736A 41/ 0F B7 6F movzx ebp, word ptr [r15 + 4] \n"
" 04 \n"
" \n"
" 0000736F 49/ 0F B6 EF movzx rbp, r15b \n"
" 00007373 49/ 0F B7 EF movzx rbp, r15w \n"
" 00007377 49/ 0F B6 6F movzx rbp, byte ptr [r15 + 4] \n"
" 04 \n"
" 0000737C 49/ 0F B7 6F movzx rbp, word ptr [r15 + 4] \n"
" 04 \n"
" \n"
" \n"
" ; Source: r15, target: rsi \n"
" 00007381 40/ B7 01 mov dil, 1 \n"
" 00007384 66| BE 0001 mov si, 1 \n"
" 00007388 BE 00000001 mov esi, 1 \n"
" 0000738D 48/ C7 C6 mov rsi, 1 \n"
" 00000001 \n"
" \n"
" 00007394 41/ 8A FF mov dil, r15b \n"
" 00007397 66| 41/ 8B F7 mov si, r15w \n"
" 0000739B 41/ 8B F7 mov esi, r15d \n"
" 0000739E 49/ 8B F7 mov rsi, r15 \n"
" \n"
" 000073A1 41/ 8A 7F FC mov dil, byte ptr [r15 - 4] \n"
" 000073A5 41/ 8A 7F 04 mov dil, byte ptr [r15 + 4] \n"
" 000073A9 66| 41/ 8B 77 mov si, word ptr [r15 + 4] \n"
" 04 \n"
" 000073AE 41/ 8B 77 04 mov esi, dword ptr [r15 + 4] \n"
" 000073B2 49/ 8B 77 04 mov rsi, qword ptr [r15 + 4] \n"
" \n"
" 000073B6 44/ 88 7E FC mov byte ptr [rsi - 4], r15b \n"
" 000073BA 44/ 88 7E 04 mov byte ptr [rsi + 4], r15b \n"
" 000073BE 66| 44/ 89 7E mov word ptr [rsi + 4], r15w \n"
" 04 \n"
" 000073C3 44/ 89 7E 04 mov dword ptr [rsi + 4], r15d \n"
" 000073C7 4C/ 89 7E 04 mov qword ptr [rsi + 4], r15 \n"
" \n"
" 000073CB 66| 41/ 0F B6 F7 movzx si, r15b \n"
" 000073D0 66| 41/ 0F B6 77 movzx si, byte ptr [r15 + 4] \n"
" 04 \n"
" \n"
" 000073D6 41/ 0F B6 F7 movzx esi, r15b \n"
" 000073DA 41/ 0F B7 F7 movzx esi, r15w \n"
" 000073DE 41/ 0F B6 77 movzx esi, byte ptr [r15 + 4] \n"
" 04 \n"
" 000073E3 41/ 0F B7 77 movzx esi, word ptr [r15 + 4] \n"
" 04 \n"
" \n"
" 000073E8 49/ 0F B6 F7 movzx rsi, r15b \n"
" 000073EC 49/ 0F B7 F7 movzx rsi, r15w \n"
" 000073F0 49/ 0F B6 77 movzx rsi, byte ptr [r15 + 4] \n"
" 04 \n"
" 000073F5 49/ 0F B7 77 movzx rsi, word ptr [r15 + 4] \n"
" 04 \n"
" \n"
" \n"
" ; Source: r15, target: rdi \n"
" 000073FA 40/ B6 01 mov sil, 1 \n"
" 000073FD 66| BF 0001 mov di, 1 \n"
" 00007401 BF 00000001 mov edi, 1 \n"
" 00007406 48/ C7 C7 mov rdi, 1 \n"
" 00000001 \n"
" \n"
" 0000740D 41/ 8A F7 mov sil, r15b \n"
" 00007410 66| 41/ 8B FF mov di, r15w \n"
" 00007414 41/ 8B FF mov edi, r15d \n"
" 00007417 49/ 8B FF mov rdi, r15 \n"
" \n"
" 0000741A 41/ 8A 77 FC mov sil, byte ptr [r15 - 4] \n"
" 0000741E 41/ 8A 77 04 mov sil, byte ptr [r15 + 4] \n"
" 00007422 66| 41/ 8B 7F mov di, word ptr [r15 + 4] \n"
" 04 \n"
" 00007427 41/ 8B 7F 04 mov edi, dword ptr [r15 + 4] \n"
" 0000742B 49/ 8B 7F 04 mov rdi, qword ptr [r15 + 4] \n"
" \n"
" 0000742F 44/ 88 7F FC mov byte ptr [rdi - 4], r15b \n"
" 00007433 44/ 88 7F 04 mov byte ptr [rdi + 4], r15b \n"
" 00007437 66| 44/ 89 7F mov word ptr [rdi + 4], r15w \n"
" 04 \n"
" 0000743C 44/ 89 7F 04 mov dword ptr [rdi + 4], r15d \n"
" 00007440 4C/ 89 7F 04 mov qword ptr [rdi + 4], r15 \n"
" \n"
" 00007444 66| 41/ 0F B6 FF movzx di, r15b \n"
" 00007449 66| 41/ 0F B6 7F movzx di, byte ptr [r15 + 4] \n"
" 04 \n"
" \n"
" 0000744F 41/ 0F B6 FF movzx edi, r15b \n"
" 00007453 41/ 0F B7 FF movzx edi, r15w \n"
" 00007457 41/ 0F B6 7F movzx edi, byte ptr [r15 + 4] \n"
" 04 \n"
" 0000745C 41/ 0F B7 7F movzx edi, word ptr [r15 + 4] \n"
" 04 \n"
" \n"
" 00007461 49/ 0F B6 FF movzx rdi, r15b \n"
" 00007465 49/ 0F B7 FF movzx rdi, r15w \n"
" 00007469 49/ 0F B6 7F movzx rdi, byte ptr [r15 + 4] \n"
" 04 \n"
" 0000746E 49/ 0F B7 7F movzx rdi, word ptr [r15 + 4] \n"
" 04 \n"
" \n"
" \n"
" ; Source: r15, target: r8 \n"
" 00007473 41/ B0 01 mov r8b, 1 \n"
" 00007476 66| 41/ B8 mov r8w, 1 \n"
" 0001 \n"
" 0000747B 41/ B8 mov r8d, 1 \n"
" 00000001 \n"
" 00007481 49/ C7 C0 mov r8, 1 \n"
" 00000001 \n"
" \n"
" 00007488 45/ 8A C7 mov r8b, r15b \n"
" 0000748B 66| 45/ 8B C7 mov r8w, r15w \n"
" 0000748F 45/ 8B C7 mov r8d, r15d \n"
" 00007492 4D/ 8B C7 mov r8, r15 \n"
" \n"
" 00007495 45/ 8A 47 FC mov r8b, byte ptr [r15 - 4] \n"
" 00007499 45/ 8A 47 04 mov r8b, byte ptr [r15 + 4] \n"
" 0000749D 66| 45/ 8B 47 mov r8w, word ptr [r15 + 4] \n"
" 04 \n"
" 000074A2 45/ 8B 47 04 mov r8d, dword ptr [r15 + 4] \n"
" 000074A6 4D/ 8B 47 04 mov r8, qword ptr [r15 + 4] \n"
" \n"
" 000074AA 45/ 88 78 FC mov byte ptr [r8 - 4], r15b \n"
" 000074AE 45/ 88 78 04 mov byte ptr [r8 + 4], r15b \n"
" 000074B2 66| 45/ 89 78 mov word ptr [r8 + 4], r15w \n"
" 04 \n"
" 000074B7 45/ 89 78 04 mov dword ptr [r8 + 4], r15d \n"
" 000074BB 4D/ 89 78 04 mov qword ptr [r8 + 4], r15 \n"
" \n"
" 000074BF 66| 45/ 0F B6 C7 movzx r8w, r15b \n"
" 000074C4 66| 45/ 0F B6 47 movzx r8w, byte ptr [r15 + 4] \n"
" 04 \n"
" \n"
" 000074CA 45/ 0F B6 C7 movzx r8d, r15b \n"
" 000074CE 45/ 0F B7 C7 movzx r8d, r15w \n"
" 000074D2 45/ 0F B6 47 movzx r8d, byte ptr [r15 + 4] \n"
" 04 \n"
" 000074D7 45/ 0F B7 47 movzx r8d, word ptr [r15 + 4] \n"
" 04 \n"
" \n"
" 000074DC 4D/ 0F B6 C7 movzx r8, r15b \n"
" 000074E0 4D/ 0F B7 C7 movzx r8, r15w \n"
" 000074E4 4D/ 0F B6 47 movzx r8, byte ptr [r15 + 4] \n"
" 04 \n"
" 000074E9 4D/ 0F B7 47 movzx r8, word ptr [r15 + 4] \n"
" 04 \n"
" \n"
" \n"
" ; Source: r15, target: r9 \n"
" 000074EE 41/ B1 01 mov r9b, 1 \n"
" 000074F1 66| 41/ B9 mov r9w, 1 \n"
" 0001 \n"
" 000074F6 41/ B9 mov r9d, 1 \n"
" 00000001 \n"
" 000074FC 49/ C7 C1 mov r9, 1 \n"
" 00000001 \n"
" \n"
" 00007503 45/ 8A CF mov r9b, r15b \n"
" 00007506 66| 45/ 8B CF mov r9w, r15w \n"
" 0000750A 45/ 8B CF mov r9d, r15d \n"
" 0000750D 4D/ 8B CF mov r9, r15 \n"
" \n"
" 00007510 45/ 8A 4F FC mov r9b, byte ptr [r15 - 4] \n"
" 00007514 45/ 8A 4F 04 mov r9b, byte ptr [r15 + 4] \n"
" 00007518 66| 45/ 8B 4F mov r9w, word ptr [r15 + 4] \n"
" 04 \n"
" 0000751D 45/ 8B 4F 04 mov r9d, dword ptr [r15 + 4] \n"
" 00007521 4D/ 8B 4F 04 mov r9, qword ptr [r15 + 4] \n"
" \n"
" 00007525 45/ 88 79 FC mov byte ptr [r9 - 4], r15b \n"
" 00007529 45/ 88 79 04 mov byte ptr [r9 + 4], r15b \n"
" 0000752D 66| 45/ 89 79 mov word ptr [r9 + 4], r15w \n"
" 04 \n"
" 00007532 45/ 89 79 04 mov dword ptr [r9 + 4], r15d \n"
" 00007536 4D/ 89 79 04 mov qword ptr [r9 + 4], r15 \n"
" \n"
" 0000753A 66| 45/ 0F B6 CF movzx r9w, r15b \n"
" 0000753F 66| 45/ 0F B6 4F movzx r9w, byte ptr [r15 + 4] \n"
" 04 \n"
" \n"
" 00007545 45/ 0F B6 CF movzx r9d, r15b \n"
" 00007549 45/ 0F B7 CF movzx r9d, r15w \n"
" 0000754D 45/ 0F B6 4F movzx r9d, byte ptr [r15 + 4] \n"
" 04 \n"
" 00007552 45/ 0F B7 4F movzx r9d, word ptr [r15 + 4] \n"
" 04 \n"
" \n"
" 00007557 4D/ 0F B6 CF movzx r9, r15b \n"
" 0000755B 4D/ 0F B7 CF movzx r9, r15w \n"
" 0000755F 4D/ 0F B6 4F movzx r9, byte ptr [r15 + 4] \n"
" 04 \n"
" 00007564 4D/ 0F B7 4F movzx r9, word ptr [r15 + 4] \n"
" 04 \n"
" \n"
" \n"
" ; Source: r15, target: r10 \n"
" 00007569 41/ B2 01 mov r10b, 1 \n"
" 0000756C 66| 41/ BA mov r10w, 1 \n"
" 0001 \n"
" 00007571 41/ BA mov r10d, 1 \n"
" 00000001 \n"
" 00007577 49/ C7 C2 mov r10, 1 \n"
" 00000001 \n"
" \n"
" 0000757E 45/ 8A D7 mov r10b, r15b \n"
" 00007581 66| 45/ 8B D7 mov r10w, r15w \n"
" 00007585 45/ 8B D7 mov r10d, r15d \n"
" 00007588 4D/ 8B D7 mov r10, r15 \n"
" \n"
" 0000758B 45/ 8A 57 FC mov r10b, byte ptr [r15 - 4] \n"
" 0000758F 45/ 8A 57 04 mov r10b, byte ptr [r15 + 4] \n"
" 00007593 66| 45/ 8B 57 mov r10w, word ptr [r15 + 4] \n"
" 04 \n"
" 00007598 45/ 8B 57 04 mov r10d, dword ptr [r15 + 4] \n"
" 0000759C 4D/ 8B 57 04 mov r10, qword ptr [r15 + 4] \n"
" \n"
" 000075A0 45/ 88 7A FC mov byte ptr [r10 - 4], r15b \n"
" 000075A4 45/ 88 7A 04 mov byte ptr [r10 + 4], r15b \n"
" 000075A8 66| 45/ 89 7A mov word ptr [r10 + 4], r15w \n"
" 04 \n"
" 000075AD 45/ 89 7A 04 mov dword ptr [r10 + 4], r15d \n"
" 000075B1 4D/ 89 7A 04 mov qword ptr [r10 + 4], r15 \n"
" \n"
" 000075B5 66| 45/ 0F B6 D7 movzx r10w, r15b \n"
" 000075BA 66| 45/ 0F B6 57 movzx r10w, byte ptr [r15 + 4] \n"
" 04 \n"
" \n"
" 000075C0 45/ 0F B6 D7 movzx r10d, r15b \n"
" 000075C4 45/ 0F B7 D7 movzx r10d, r15w \n"
" 000075C8 45/ 0F B6 57 movzx r10d, byte ptr [r15 + 4] \n"
" 04 \n"
" 000075CD 45/ 0F B7 57 movzx r10d, word ptr [r15 + 4] \n"
" 04 \n"
" \n"
" 000075D2 4D/ 0F B6 D7 movzx r10, r15b \n"
" 000075D6 4D/ 0F B7 D7 movzx r10, r15w \n"
" 000075DA 4D/ 0F B6 57 movzx r10, byte ptr [r15 + 4] \n"
" 04 \n"
" 000075DF 4D/ 0F B7 57 movzx r10, word ptr [r15 + 4] \n"
" 04 \n"
" \n"
" \n"
" ; Source: r15, target: r11 \n"
" 000075E4 41/ B3 01 mov r11b, 1 \n"
" 000075E7 66| 41/ BB mov r11w, 1 \n"
" 0001 \n"
" 000075EC 41/ BB mov r11d, 1 \n"
" 00000001 \n"
" 000075F2 49/ C7 C3 mov r11, 1 \n"
" 00000001 \n"
" \n"
" 000075F9 45/ 8A DF mov r11b, r15b \n"
" 000075FC 66| 45/ 8B DF mov r11w, r15w \n"
" 00007600 45/ 8B DF mov r11d, r15d \n"
" 00007603 4D/ 8B DF mov r11, r15 \n"
" \n"
" 00007606 45/ 8A 5F FC mov r11b, byte ptr [r15 - 4] \n"
" 0000760A 45/ 8A 5F 04 mov r11b, byte ptr [r15 + 4] \n"
" 0000760E 66| 45/ 8B 5F mov r11w, word ptr [r15 + 4] \n"
" 04 \n"
" 00007613 45/ 8B 5F 04 mov r11d, dword ptr [r15 + 4] \n";
ml64Output +=
" 00007617 4D/ 8B 5F 04 mov r11, qword ptr [r15 + 4] \n"
" \n"
" 0000761B 45/ 88 7B FC mov byte ptr [r11 - 4], r15b \n"
" 0000761F 45/ 88 7B 04 mov byte ptr [r11 + 4], r15b \n"
" 00007623 66| 45/ 89 7B mov word ptr [r11 + 4], r15w \n"
" 04 \n"
" 00007628 45/ 89 7B 04 mov dword ptr [r11 + 4], r15d \n"
" 0000762C 4D/ 89 7B 04 mov qword ptr [r11 + 4], r15 \n"
" \n"
" 00007630 66| 45/ 0F B6 DF movzx r11w, r15b \n"
" 00007635 66| 45/ 0F B6 5F movzx r11w, byte ptr [r15 + 4] \n"
" 04 \n"
" \n"
" 0000763B 45/ 0F B6 DF movzx r11d, r15b \n"
" 0000763F 45/ 0F B7 DF movzx r11d, r15w \n"
" 00007643 45/ 0F B6 5F movzx r11d, byte ptr [r15 + 4] \n"
" 04 \n"
" 00007648 45/ 0F B7 5F movzx r11d, word ptr [r15 + 4] \n"
" 04 \n"
" \n"
" 0000764D 4D/ 0F B6 DF movzx r11, r15b \n"
" 00007651 4D/ 0F B7 DF movzx r11, r15w \n"
" 00007655 4D/ 0F B6 5F movzx r11, byte ptr [r15 + 4] \n"
" 04 \n"
" 0000765A 4D/ 0F B7 5F movzx r11, word ptr [r15 + 4] \n"
" 04 \n"
" \n"
" \n"
" ; Source: r15, target: r12 \n"
" 0000765F 41/ B4 01 mov r12b, 1 \n"
" 00007662 66| 41/ BC mov r12w, 1 \n"
" 0001 \n"
" 00007667 41/ BC mov r12d, 1 \n"
" 00000001 \n"
" 0000766D 49/ C7 C4 mov r12, 1 \n"
" 00000001 \n"
" \n"
" 00007674 45/ 8A E7 mov r12b, r15b \n"
" 00007677 66| 45/ 8B E7 mov r12w, r15w \n"
" 0000767B 45/ 8B E7 mov r12d, r15d \n"
" 0000767E 4D/ 8B E7 mov r12, r15 \n"
" \n"
" 00007681 45/ 8A 67 FC mov r12b, byte ptr [r15 - 4] \n"
" 00007685 45/ 8A 67 04 mov r12b, byte ptr [r15 + 4] \n"
" 00007689 66| 45/ 8B 67 mov r12w, word ptr [r15 + 4] \n"
" 04 \n"
" 0000768E 45/ 8B 67 04 mov r12d, dword ptr [r15 + 4] \n"
" 00007692 4D/ 8B 67 04 mov r12, qword ptr [r15 + 4] \n"
" \n"
" 00007696 45/ 88 7C 24 mov byte ptr [r12 - 4], r15b \n"
" FC \n"
" 0000769B 45/ 88 7C 24 mov byte ptr [r12 + 4], r15b \n"
" 04 \n"
" 000076A0 66| 45/ 89 7C 24 mov word ptr [r12 + 4], r15w \n"
" 04 \n"
" 000076A6 45/ 89 7C 24 mov dword ptr [r12 + 4], r15d \n"
" 04 \n"
" 000076AB 4D/ 89 7C 24 mov qword ptr [r12 + 4], r15 \n"
" 04 \n"
" \n"
" 000076B0 66| 45/ 0F B6 E7 movzx r12w, r15b \n"
" 000076B5 66| 45/ 0F B6 67 movzx r12w, byte ptr [r15 + 4] \n"
" 04 \n"
" \n"
" 000076BB 45/ 0F B6 E7 movzx r12d, r15b \n"
" 000076BF 45/ 0F B7 E7 movzx r12d, r15w \n"
" 000076C3 45/ 0F B6 67 movzx r12d, byte ptr [r15 + 4] \n"
" 04 \n"
" 000076C8 45/ 0F B7 67 movzx r12d, word ptr [r15 + 4] \n"
" 04 \n"
" \n"
" 000076CD 4D/ 0F B6 E7 movzx r12, r15b \n"
" 000076D1 4D/ 0F B7 E7 movzx r12, r15w \n"
" 000076D5 4D/ 0F B6 67 movzx r12, byte ptr [r15 + 4] \n"
" 04 \n"
" 000076DA 4D/ 0F B7 67 movzx r12, word ptr [r15 + 4] \n"
" 04 \n"
" \n"
" \n"
" ; Source: r15, target: r13 \n"
" 000076DF 41/ B5 01 mov r13b, 1 \n"
" 000076E2 66| 41/ BD mov r13w, 1 \n"
" 0001 \n"
" 000076E7 41/ BD mov r13d, 1 \n"
" 00000001 \n"
" 000076ED 49/ C7 C5 mov r13, 1 \n"
" 00000001 \n"
" \n"
" 000076F4 45/ 8A EF mov r13b, r15b \n"
" 000076F7 66| 45/ 8B EF mov r13w, r15w \n"
" 000076FB 45/ 8B EF mov r13d, r15d \n"
" 000076FE 4D/ 8B EF mov r13, r15 \n"
" \n"
" 00007701 45/ 8A 6F FC mov r13b, byte ptr [r15 - 4] \n"
" 00007705 45/ 8A 6F 04 mov r13b, byte ptr [r15 + 4] \n"
" 00007709 66| 45/ 8B 6F mov r13w, word ptr [r15 + 4] \n"
" 04 \n"
" 0000770E 45/ 8B 6F 04 mov r13d, dword ptr [r15 + 4] \n"
" 00007712 4D/ 8B 6F 04 mov r13, qword ptr [r15 + 4] \n"
" \n"
" 00007716 45/ 88 7D FC mov byte ptr [r13 - 4], r15b \n"
" 0000771A 45/ 88 7D 04 mov byte ptr [r13 + 4], r15b \n"
" 0000771E 66| 45/ 89 7D mov word ptr [r13 + 4], r15w \n"
" 04 \n"
" 00007723 45/ 89 7D 04 mov dword ptr [r13 + 4], r15d \n"
" 00007727 4D/ 89 7D 04 mov qword ptr [r13 + 4], r15 \n"
" \n"
" 0000772B 66| 45/ 0F B6 EF movzx r13w, r15b \n"
" 00007730 66| 45/ 0F B6 6F movzx r13w, byte ptr [r15 + 4] \n"
" 04 \n"
" \n"
" 00007736 45/ 0F B6 EF movzx r13d, r15b \n"
" 0000773A 45/ 0F B7 EF movzx r13d, r15w \n"
" 0000773E 45/ 0F B6 6F movzx r13d, byte ptr [r15 + 4] \n"
" 04 \n"
" 00007743 45/ 0F B7 6F movzx r13d, word ptr [r15 + 4] \n"
" 04 \n"
" \n"
" 00007748 4D/ 0F B6 EF movzx r13, r15b \n"
" 0000774C 4D/ 0F B7 EF movzx r13, r15w \n"
" 00007750 4D/ 0F B6 6F movzx r13, byte ptr [r15 + 4] \n"
" 04 \n"
" 00007755 4D/ 0F B7 6F movzx r13, word ptr [r15 + 4] \n"
" 04 \n"
" \n"
" \n"
" ; Source: r15, target: r14 \n"
" 0000775A 41/ B6 01 mov r14b, 1 \n"
" 0000775D 66| 41/ BE mov r14w, 1 \n"
" 0001 \n"
" 00007762 41/ BE mov r14d, 1 \n"
" 00000001 \n"
" 00007768 49/ C7 C6 mov r14, 1 \n"
" 00000001 \n"
" \n"
" 0000776F 45/ 8A F7 mov r14b, r15b \n"
" 00007772 66| 45/ 8B F7 mov r14w, r15w \n"
" 00007776 45/ 8B F7 mov r14d, r15d \n"
" 00007779 4D/ 8B F7 mov r14, r15 \n"
" \n"
" 0000777C 45/ 8A 77 FC mov r14b, byte ptr [r15 - 4] \n"
" 00007780 45/ 8A 77 04 mov r14b, byte ptr [r15 + 4] \n"
" 00007784 66| 45/ 8B 77 mov r14w, word ptr [r15 + 4] \n"
" 04 \n"
" 00007789 45/ 8B 77 04 mov r14d, dword ptr [r15 + 4] \n"
" 0000778D 4D/ 8B 77 04 mov r14, qword ptr [r15 + 4] \n"
" \n"
" 00007791 45/ 88 7E FC mov byte ptr [r14 - 4], r15b \n"
" 00007795 45/ 88 7E 04 mov byte ptr [r14 + 4], r15b \n"
" 00007799 66| 45/ 89 7E mov word ptr [r14 + 4], r15w \n"
" 04 \n"
" 0000779E 45/ 89 7E 04 mov dword ptr [r14 + 4], r15d \n"
" 000077A2 4D/ 89 7E 04 mov qword ptr [r14 + 4], r15 \n"
" \n"
" 000077A6 66| 45/ 0F B6 F7 movzx r14w, r15b \n"
" 000077AB 66| 45/ 0F B6 77 movzx r14w, byte ptr [r15 + 4] \n"
" 04 \n"
" \n"
" 000077B1 45/ 0F B6 F7 movzx r14d, r15b \n"
" 000077B5 45/ 0F B7 F7 movzx r14d, r15w \n"
" 000077B9 45/ 0F B6 77 movzx r14d, byte ptr [r15 + 4] \n"
" 04 \n"
" 000077BE 45/ 0F B7 77 movzx r14d, word ptr [r15 + 4] \n"
" 04 \n"
" \n"
" 000077C3 4D/ 0F B6 F7 movzx r14, r15b \n"
" 000077C7 4D/ 0F B7 F7 movzx r14, r15w \n"
" 000077CB 4D/ 0F B6 77 movzx r14, byte ptr [r15 + 4] \n"
" 04 \n"
" 000077D0 4D/ 0F B7 77 movzx r14, word ptr [r15 + 4] \n"
" 04 \n"
" \n"
" \n"
" ; Source: r15, target: r15 \n"
" 000077D5 41/ B7 01 mov r15b, 1 \n"
" 000077D8 66| 41/ BF mov r15w, 1 \n"
" 0001 \n"
" 000077DD 41/ BF mov r15d, 1 \n"
" 00000001 \n"
" 000077E3 49/ C7 C7 mov r15, 1 \n"
" 00000001 \n"
" \n"
" 000077EA 45/ 8A FF mov r15b, r15b \n"
" 000077ED 66| 45/ 8B FF mov r15w, r15w \n"
" 000077F1 45/ 8B FF mov r15d, r15d \n"
" 000077F4 4D/ 8B FF mov r15, r15 \n"
" \n"
" 000077F7 45/ 8A 7F FC mov r15b, byte ptr [r15 - 4] \n"
" 000077FB 45/ 8A 7F 04 mov r15b, byte ptr [r15 + 4] \n"
" 000077FF 66| 45/ 8B 7F mov r15w, word ptr [r15 + 4] \n"
" 04 \n"
" 00007804 45/ 8B 7F 04 mov r15d, dword ptr [r15 + 4] \n"
" 00007808 4D/ 8B 7F 04 mov r15, qword ptr [r15 + 4] \n"
" \n"
" 0000780C 45/ 88 7F FC mov byte ptr [r15 - 4], r15b \n"
" 00007810 45/ 88 7F 04 mov byte ptr [r15 + 4], r15b \n"
" 00007814 66| 45/ 89 7F mov word ptr [r15 + 4], r15w \n"
" 04 \n"
" 00007819 45/ 89 7F 04 mov dword ptr [r15 + 4], r15d \n"
" 0000781D 4D/ 89 7F 04 mov qword ptr [r15 + 4], r15 \n"
" \n"
" 00007821 66| 45/ 0F B6 FF movzx r15w, r15b \n"
" 00007826 66| 45/ 0F B6 7F movzx r15w, byte ptr [r15 + 4] \n"
" 04 \n"
" \n"
" 0000782C 45/ 0F B6 FF movzx r15d, r15b \n"
" 00007830 45/ 0F B7 FF movzx r15d, r15w \n"
" 00007834 45/ 0F B6 7F movzx r15d, byte ptr [r15 + 4] \n"
" 04 \n"
" 00007839 45/ 0F B7 7F movzx r15d, word ptr [r15 + 4] \n"
" 04 \n"
" \n"
" 0000783E 4D/ 0F B6 FF movzx r15, r15b \n"
" 00007842 4D/ 0F B7 FF movzx r15, r15w \n"
" 00007846 4D/ 0F B6 7F movzx r15, byte ptr [r15 + 4] \n"
" 04 \n"
" 0000784B 4D/ 0F B7 7F movzx r15, word ptr [r15 + 4] \n"
" 04 \n"
" \n"
" \n"
" ; Float <-> float \n"
" \n"
" ; Source: xmm0, target: xmm0 \n"
" 00007850 F3/ 0F 10 C0 movss xmm0, xmm0 \n"
" 00007854 F2/ 0F 10 C0 movsd xmm0, xmm0 \n"
" \n"
" 00007858 F3/ 0F 5A C0 cvtss2sd xmm0, xmm0 \n"
" 0000785C F2/ 0F 5A C0 cvtsd2ss xmm0, xmm0 \n"
" \n"
" \n"
" ; Source: xmm0, target: xmm1 \n"
" 00007860 F3/ 0F 10 C8 movss xmm1, xmm0 \n"
" 00007864 F2/ 0F 10 C8 movsd xmm1, xmm0 \n"
" \n"
" 00007868 F3/ 0F 5A C8 cvtss2sd xmm1, xmm0 \n"
" 0000786C F2/ 0F 5A C8 cvtsd2ss xmm1, xmm0 \n"
" \n"
" \n"
" ; Source: xmm0, target: xmm2 \n"
" 00007870 F3/ 0F 10 D0 movss xmm2, xmm0 \n"
" 00007874 F2/ 0F 10 D0 movsd xmm2, xmm0 \n"
" \n"
" 00007878 F3/ 0F 5A D0 cvtss2sd xmm2, xmm0 \n"
" 0000787C F2/ 0F 5A D0 cvtsd2ss xmm2, xmm0 \n"
" \n"
" \n"
" ; Source: xmm0, target: xmm3 \n"
" 00007880 F3/ 0F 10 D8 movss xmm3, xmm0 \n"
" 00007884 F2/ 0F 10 D8 movsd xmm3, xmm0 \n"
" \n"
" 00007888 F3/ 0F 5A D8 cvtss2sd xmm3, xmm0 \n"
" 0000788C F2/ 0F 5A D8 cvtsd2ss xmm3, xmm0 \n"
" \n"
" \n"
" ; Source: xmm0, target: xmm4 \n"
" 00007890 F3/ 0F 10 E0 movss xmm4, xmm0 \n"
" 00007894 F2/ 0F 10 E0 movsd xmm4, xmm0 \n"
" \n"
" 00007898 F3/ 0F 5A E0 cvtss2sd xmm4, xmm0 \n"
" 0000789C F2/ 0F 5A E0 cvtsd2ss xmm4, xmm0 \n"
" \n"
" \n"
" ; Source: xmm0, target: xmm5 \n"
" 000078A0 F3/ 0F 10 E8 movss xmm5, xmm0 \n"
" 000078A4 F2/ 0F 10 E8 movsd xmm5, xmm0 \n"
" \n"
" 000078A8 F3/ 0F 5A E8 cvtss2sd xmm5, xmm0 \n"
" 000078AC F2/ 0F 5A E8 cvtsd2ss xmm5, xmm0 \n"
" \n"
" \n"
" ; Source: xmm0, target: xmm6 \n"
" 000078B0 F3/ 0F 10 F0 movss xmm6, xmm0 \n"
" 000078B4 F2/ 0F 10 F0 movsd xmm6, xmm0 \n"
" \n"
" 000078B8 F3/ 0F 5A F0 cvtss2sd xmm6, xmm0 \n"
" 000078BC F2/ 0F 5A F0 cvtsd2ss xmm6, xmm0 \n"
" \n"
" \n"
" ; Source: xmm0, target: xmm7 \n"
" 000078C0 F3/ 0F 10 F8 movss xmm7, xmm0 \n"
" 000078C4 F2/ 0F 10 F8 movsd xmm7, xmm0 \n"
" \n"
" 000078C8 F3/ 0F 5A F8 cvtss2sd xmm7, xmm0 \n"
" 000078CC F2/ 0F 5A F8 cvtsd2ss xmm7, xmm0 \n"
" \n"
" \n"
" ; Source: xmm0, target: xmm8 \n"
" 000078D0 F3/ 44/ 0F 10 C0 movss xmm8, xmm0 \n"
" 000078D5 F2/ 44/ 0F 10 C0 movsd xmm8, xmm0 \n"
" \n"
" 000078DA F3/ 44/ 0F 5A C0 cvtss2sd xmm8, xmm0 \n"
" 000078DF F2/ 44/ 0F 5A C0 cvtsd2ss xmm8, xmm0 \n"
" \n"
" \n"
" ; Source: xmm0, target: xmm9 \n"
" 000078E4 F3/ 44/ 0F 10 C8 movss xmm9, xmm0 \n"
" 000078E9 F2/ 44/ 0F 10 C8 movsd xmm9, xmm0 \n"
" \n"
" 000078EE F3/ 44/ 0F 5A C8 cvtss2sd xmm9, xmm0 \n"
" 000078F3 F2/ 44/ 0F 5A C8 cvtsd2ss xmm9, xmm0 \n"
" \n"
" \n"
" ; Source: xmm0, target: xmm10 \n"
" 000078F8 F3/ 44/ 0F 10 D0 movss xmm10, xmm0 \n"
" 000078FD F2/ 44/ 0F 10 D0 movsd xmm10, xmm0 \n"
" \n"
" 00007902 F3/ 44/ 0F 5A D0 cvtss2sd xmm10, xmm0 \n"
" 00007907 F2/ 44/ 0F 5A D0 cvtsd2ss xmm10, xmm0 \n"
" \n"
" \n"
" ; Source: xmm0, target: xmm11 \n"
" 0000790C F3/ 44/ 0F 10 D8 movss xmm11, xmm0 \n"
" 00007911 F2/ 44/ 0F 10 D8 movsd xmm11, xmm0 \n"
" \n"
" 00007916 F3/ 44/ 0F 5A D8 cvtss2sd xmm11, xmm0 \n"
" 0000791B F2/ 44/ 0F 5A D8 cvtsd2ss xmm11, xmm0 \n"
" \n"
" \n"
" ; Source: xmm0, target: xmm12 \n"
" 00007920 F3/ 44/ 0F 10 E0 movss xmm12, xmm0 \n"
" 00007925 F2/ 44/ 0F 10 E0 movsd xmm12, xmm0 \n"
" \n"
" 0000792A F3/ 44/ 0F 5A E0 cvtss2sd xmm12, xmm0 \n"
" 0000792F F2/ 44/ 0F 5A E0 cvtsd2ss xmm12, xmm0 \n"
" \n"
" \n"
" ; Source: xmm0, target: xmm13 \n"
" 00007934 F3/ 44/ 0F 10 E8 movss xmm13, xmm0 \n"
" 00007939 F2/ 44/ 0F 10 E8 movsd xmm13, xmm0 \n"
" \n"
" 0000793E F3/ 44/ 0F 5A E8 cvtss2sd xmm13, xmm0 \n"
" 00007943 F2/ 44/ 0F 5A E8 cvtsd2ss xmm13, xmm0 \n"
" \n"
" \n"
" ; Source: xmm0, target: xmm14 \n"
" 00007948 F3/ 44/ 0F 10 F0 movss xmm14, xmm0 \n"
" 0000794D F2/ 44/ 0F 10 F0 movsd xmm14, xmm0 \n"
" \n"
" 00007952 F3/ 44/ 0F 5A F0 cvtss2sd xmm14, xmm0 \n"
" 00007957 F2/ 44/ 0F 5A F0 cvtsd2ss xmm14, xmm0 \n"
" \n"
" \n"
" ; Source: xmm0, target: xmm15 \n"
" 0000795C F3/ 44/ 0F 10 F8 movss xmm15, xmm0 \n"
" 00007961 F2/ 44/ 0F 10 F8 movsd xmm15, xmm0 \n"
" \n"
" 00007966 F3/ 44/ 0F 5A F8 cvtss2sd xmm15, xmm0 \n"
" 0000796B F2/ 44/ 0F 5A F8 cvtsd2ss xmm15, xmm0 \n"
" \n"
" \n"
" ; Source: xmm1, target: xmm0 \n"
" 00007970 F3/ 0F 10 C1 movss xmm0, xmm1 \n"
" 00007974 F2/ 0F 10 C1 movsd xmm0, xmm1 \n"
" \n"
" 00007978 F3/ 0F 5A C1 cvtss2sd xmm0, xmm1 \n"
" 0000797C F2/ 0F 5A C1 cvtsd2ss xmm0, xmm1 \n"
" \n"
" \n"
" ; Source: xmm1, target: xmm1 \n"
" 00007980 F3/ 0F 10 C9 movss xmm1, xmm1 \n"
" 00007984 F2/ 0F 10 C9 movsd xmm1, xmm1 \n"
" \n"
" 00007988 F3/ 0F 5A C9 cvtss2sd xmm1, xmm1 \n"
" 0000798C F2/ 0F 5A C9 cvtsd2ss xmm1, xmm1 \n"
" \n"
" \n"
" ; Source: xmm1, target: xmm2 \n"
" 00007990 F3/ 0F 10 D1 movss xmm2, xmm1 \n"
" 00007994 F2/ 0F 10 D1 movsd xmm2, xmm1 \n"
" \n"
" 00007998 F3/ 0F 5A D1 cvtss2sd xmm2, xmm1 \n"
" 0000799C F2/ 0F 5A D1 cvtsd2ss xmm2, xmm1 \n"
" \n"
" \n"
" ; Source: xmm1, target: xmm3 \n"
" 000079A0 F3/ 0F 10 D9 movss xmm3, xmm1 \n"
" 000079A4 F2/ 0F 10 D9 movsd xmm3, xmm1 \n"
" \n"
" 000079A8 F3/ 0F 5A D9 cvtss2sd xmm3, xmm1 \n"
" 000079AC F2/ 0F 5A D9 cvtsd2ss xmm3, xmm1 \n"
" \n"
" \n"
" ; Source: xmm1, target: xmm4 \n"
" 000079B0 F3/ 0F 10 E1 movss xmm4, xmm1 \n"
" 000079B4 F2/ 0F 10 E1 movsd xmm4, xmm1 \n"
" \n"
" 000079B8 F3/ 0F 5A E1 cvtss2sd xmm4, xmm1 \n"
" 000079BC F2/ 0F 5A E1 cvtsd2ss xmm4, xmm1 \n"
" \n"
" \n"
" ; Source: xmm1, target: xmm5 \n"
" 000079C0 F3/ 0F 10 E9 movss xmm5, xmm1 \n"
" 000079C4 F2/ 0F 10 E9 movsd xmm5, xmm1 \n"
" \n"
" 000079C8 F3/ 0F 5A E9 cvtss2sd xmm5, xmm1 \n"
" 000079CC F2/ 0F 5A E9 cvtsd2ss xmm5, xmm1 \n"
" \n"
" \n"
" ; Source: xmm1, target: xmm6 \n"
" 000079D0 F3/ 0F 10 F1 movss xmm6, xmm1 \n"
" 000079D4 F2/ 0F 10 F1 movsd xmm6, xmm1 \n"
" \n"
" 000079D8 F3/ 0F 5A F1 cvtss2sd xmm6, xmm1 \n"
" 000079DC F2/ 0F 5A F1 cvtsd2ss xmm6, xmm1 \n"
" \n"
" \n"
" ; Source: xmm1, target: xmm7 \n"
" 000079E0 F3/ 0F 10 F9 movss xmm7, xmm1 \n"
" 000079E4 F2/ 0F 10 F9 movsd xmm7, xmm1 \n"
" \n"
" 000079E8 F3/ 0F 5A F9 cvtss2sd xmm7, xmm1 \n"
" 000079EC F2/ 0F 5A F9 cvtsd2ss xmm7, xmm1 \n"
" \n"
" \n"
" ; Source: xmm1, target: xmm8 \n"
" 000079F0 F3/ 44/ 0F 10 C1 movss xmm8, xmm1 \n"
" 000079F5 F2/ 44/ 0F 10 C1 movsd xmm8, xmm1 \n"
" \n"
" 000079FA F3/ 44/ 0F 5A C1 cvtss2sd xmm8, xmm1 \n"
" 000079FF F2/ 44/ 0F 5A C1 cvtsd2ss xmm8, xmm1 \n"
" \n"
" \n"
" ; Source: xmm1, target: xmm9 \n"
" 00007A04 F3/ 44/ 0F 10 C9 movss xmm9, xmm1 \n"
" 00007A09 F2/ 44/ 0F 10 C9 movsd xmm9, xmm1 \n"
" \n"
" 00007A0E F3/ 44/ 0F 5A C9 cvtss2sd xmm9, xmm1 \n"
" 00007A13 F2/ 44/ 0F 5A C9 cvtsd2ss xmm9, xmm1 \n"
" \n"
" \n"
" ; Source: xmm1, target: xmm10 \n"
" 00007A18 F3/ 44/ 0F 10 D1 movss xmm10, xmm1 \n"
" 00007A1D F2/ 44/ 0F 10 D1 movsd xmm10, xmm1 \n"
" \n"
" 00007A22 F3/ 44/ 0F 5A D1 cvtss2sd xmm10, xmm1 \n"
" 00007A27 F2/ 44/ 0F 5A D1 cvtsd2ss xmm10, xmm1 \n"
" \n"
" \n"
" ; Source: xmm1, target: xmm11 \n"
" 00007A2C F3/ 44/ 0F 10 D9 movss xmm11, xmm1 \n"
" 00007A31 F2/ 44/ 0F 10 D9 movsd xmm11, xmm1 \n"
" \n"
" 00007A36 F3/ 44/ 0F 5A D9 cvtss2sd xmm11, xmm1 \n"
" 00007A3B F2/ 44/ 0F 5A D9 cvtsd2ss xmm11, xmm1 \n"
" \n"
" \n"
" ; Source: xmm1, target: xmm12 \n"
" 00007A40 F3/ 44/ 0F 10 E1 movss xmm12, xmm1 \n"
" 00007A45 F2/ 44/ 0F 10 E1 movsd xmm12, xmm1 \n"
" \n"
" 00007A4A F3/ 44/ 0F 5A E1 cvtss2sd xmm12, xmm1 \n"
" 00007A4F F2/ 44/ 0F 5A E1 cvtsd2ss xmm12, xmm1 \n"
" \n"
" \n"
" ; Source: xmm1, target: xmm13 \n"
" 00007A54 F3/ 44/ 0F 10 E9 movss xmm13, xmm1 \n"
" 00007A59 F2/ 44/ 0F 10 E9 movsd xmm13, xmm1 \n"
" \n"
" 00007A5E F3/ 44/ 0F 5A E9 cvtss2sd xmm13, xmm1 \n"
" 00007A63 F2/ 44/ 0F 5A E9 cvtsd2ss xmm13, xmm1 \n"
" \n"
" \n"
" ; Source: xmm1, target: xmm14 \n"
" 00007A68 F3/ 44/ 0F 10 F1 movss xmm14, xmm1 \n"
" 00007A6D F2/ 44/ 0F 10 F1 movsd xmm14, xmm1 \n"
" \n"
" 00007A72 F3/ 44/ 0F 5A F1 cvtss2sd xmm14, xmm1 \n"
" 00007A77 F2/ 44/ 0F 5A F1 cvtsd2ss xmm14, xmm1 \n"
" \n"
" \n"
" ; Source: xmm1, target: xmm15 \n"
" 00007A7C F3/ 44/ 0F 10 F9 movss xmm15, xmm1 \n"
" 00007A81 F2/ 44/ 0F 10 F9 movsd xmm15, xmm1 \n"
" \n"
" 00007A86 F3/ 44/ 0F 5A F9 cvtss2sd xmm15, xmm1 \n"
" 00007A8B F2/ 44/ 0F 5A F9 cvtsd2ss xmm15, xmm1 \n"
" \n"
" \n"
" ; Source: xmm2, target: xmm0 \n"
" 00007A90 F3/ 0F 10 C2 movss xmm0, xmm2 \n"
" 00007A94 F2/ 0F 10 C2 movsd xmm0, xmm2 \n"
" \n"
" 00007A98 F3/ 0F 5A C2 cvtss2sd xmm0, xmm2 \n"
" 00007A9C F2/ 0F 5A C2 cvtsd2ss xmm0, xmm2 \n"
" \n"
" \n"
" ; Source: xmm2, target: xmm1 \n"
" 00007AA0 F3/ 0F 10 CA movss xmm1, xmm2 \n"
" 00007AA4 F2/ 0F 10 CA movsd xmm1, xmm2 \n"
" \n"
" 00007AA8 F3/ 0F 5A CA cvtss2sd xmm1, xmm2 \n"
" 00007AAC F2/ 0F 5A CA cvtsd2ss xmm1, xmm2 \n"
" \n"
" \n"
" ; Source: xmm2, target: xmm2 \n"
" 00007AB0 F3/ 0F 10 D2 movss xmm2, xmm2 \n"
" 00007AB4 F2/ 0F 10 D2 movsd xmm2, xmm2 \n"
" \n"
" 00007AB8 F3/ 0F 5A D2 cvtss2sd xmm2, xmm2 \n"
" 00007ABC F2/ 0F 5A D2 cvtsd2ss xmm2, xmm2 \n"
" \n"
" \n"
" ; Source: xmm2, target: xmm3 \n"
" 00007AC0 F3/ 0F 10 DA movss xmm3, xmm2 \n"
" 00007AC4 F2/ 0F 10 DA movsd xmm3, xmm2 \n"
" \n"
" 00007AC8 F3/ 0F 5A DA cvtss2sd xmm3, xmm2 \n"
" 00007ACC F2/ 0F 5A DA cvtsd2ss xmm3, xmm2 \n"
" \n"
" \n"
" ; Source: xmm2, target: xmm4 \n"
" 00007AD0 F3/ 0F 10 E2 movss xmm4, xmm2 \n"
" 00007AD4 F2/ 0F 10 E2 movsd xmm4, xmm2 \n"
" \n"
" 00007AD8 F3/ 0F 5A E2 cvtss2sd xmm4, xmm2 \n"
" 00007ADC F2/ 0F 5A E2 cvtsd2ss xmm4, xmm2 \n"
" \n"
" \n"
" ; Source: xmm2, target: xmm5 \n"
" 00007AE0 F3/ 0F 10 EA movss xmm5, xmm2 \n"
" 00007AE4 F2/ 0F 10 EA movsd xmm5, xmm2 \n"
" \n"
" 00007AE8 F3/ 0F 5A EA cvtss2sd xmm5, xmm2 \n"
" 00007AEC F2/ 0F 5A EA cvtsd2ss xmm5, xmm2 \n"
" \n"
" \n"
" ; Source: xmm2, target: xmm6 \n"
" 00007AF0 F3/ 0F 10 F2 movss xmm6, xmm2 \n"
" 00007AF4 F2/ 0F 10 F2 movsd xmm6, xmm2 \n"
" \n"
" 00007AF8 F3/ 0F 5A F2 cvtss2sd xmm6, xmm2 \n"
" 00007AFC F2/ 0F 5A F2 cvtsd2ss xmm6, xmm2 \n"
" \n"
" \n"
" ; Source: xmm2, target: xmm7 \n"
" 00007B00 F3/ 0F 10 FA movss xmm7, xmm2 \n"
" 00007B04 F2/ 0F 10 FA movsd xmm7, xmm2 \n"
" \n"
" 00007B08 F3/ 0F 5A FA cvtss2sd xmm7, xmm2 \n"
" 00007B0C F2/ 0F 5A FA cvtsd2ss xmm7, xmm2 \n"
" \n"
" \n"
" ; Source: xmm2, target: xmm8 \n"
" 00007B10 F3/ 44/ 0F 10 C2 movss xmm8, xmm2 \n"
" 00007B15 F2/ 44/ 0F 10 C2 movsd xmm8, xmm2 \n"
" \n"
" 00007B1A F3/ 44/ 0F 5A C2 cvtss2sd xmm8, xmm2 \n"
" 00007B1F F2/ 44/ 0F 5A C2 cvtsd2ss xmm8, xmm2 \n"
" \n"
" \n";
ml64Output +=
" ; Source: xmm2, target: xmm9 \n"
" 00007B24 F3/ 44/ 0F 10 CA movss xmm9, xmm2 \n"
" 00007B29 F2/ 44/ 0F 10 CA movsd xmm9, xmm2 \n"
" \n"
" 00007B2E F3/ 44/ 0F 5A CA cvtss2sd xmm9, xmm2 \n"
" 00007B33 F2/ 44/ 0F 5A CA cvtsd2ss xmm9, xmm2 \n"
" \n"
" \n"
" ; Source: xmm2, target: xmm10 \n"
" 00007B38 F3/ 44/ 0F 10 D2 movss xmm10, xmm2 \n"
" 00007B3D F2/ 44/ 0F 10 D2 movsd xmm10, xmm2 \n"
" \n"
" 00007B42 F3/ 44/ 0F 5A D2 cvtss2sd xmm10, xmm2 \n"
" 00007B47 F2/ 44/ 0F 5A D2 cvtsd2ss xmm10, xmm2 \n"
" \n"
" \n"
" ; Source: xmm2, target: xmm11 \n"
" 00007B4C F3/ 44/ 0F 10 DA movss xmm11, xmm2 \n"
" 00007B51 F2/ 44/ 0F 10 DA movsd xmm11, xmm2 \n"
" \n"
" 00007B56 F3/ 44/ 0F 5A DA cvtss2sd xmm11, xmm2 \n"
" 00007B5B F2/ 44/ 0F 5A DA cvtsd2ss xmm11, xmm2 \n"
" \n"
" \n"
" ; Source: xmm2, target: xmm12 \n"
" 00007B60 F3/ 44/ 0F 10 E2 movss xmm12, xmm2 \n"
" 00007B65 F2/ 44/ 0F 10 E2 movsd xmm12, xmm2 \n"
" \n"
" 00007B6A F3/ 44/ 0F 5A E2 cvtss2sd xmm12, xmm2 \n"
" 00007B6F F2/ 44/ 0F 5A E2 cvtsd2ss xmm12, xmm2 \n"
" \n"
" \n"
" ; Source: xmm2, target: xmm13 \n"
" 00007B74 F3/ 44/ 0F 10 EA movss xmm13, xmm2 \n"
" 00007B79 F2/ 44/ 0F 10 EA movsd xmm13, xmm2 \n"
" \n"
" 00007B7E F3/ 44/ 0F 5A EA cvtss2sd xmm13, xmm2 \n"
" 00007B83 F2/ 44/ 0F 5A EA cvtsd2ss xmm13, xmm2 \n"
" \n"
" \n"
" ; Source: xmm2, target: xmm14 \n"
" 00007B88 F3/ 44/ 0F 10 F2 movss xmm14, xmm2 \n"
" 00007B8D F2/ 44/ 0F 10 F2 movsd xmm14, xmm2 \n"
" \n"
" 00007B92 F3/ 44/ 0F 5A F2 cvtss2sd xmm14, xmm2 \n"
" 00007B97 F2/ 44/ 0F 5A F2 cvtsd2ss xmm14, xmm2 \n"
" \n"
" \n"
" ; Source: xmm2, target: xmm15 \n"
" 00007B9C F3/ 44/ 0F 10 FA movss xmm15, xmm2 \n"
" 00007BA1 F2/ 44/ 0F 10 FA movsd xmm15, xmm2 \n"
" \n"
" 00007BA6 F3/ 44/ 0F 5A FA cvtss2sd xmm15, xmm2 \n"
" 00007BAB F2/ 44/ 0F 5A FA cvtsd2ss xmm15, xmm2 \n"
" \n"
" \n"
" ; Source: xmm3, target: xmm0 \n"
" 00007BB0 F3/ 0F 10 C3 movss xmm0, xmm3 \n"
" 00007BB4 F2/ 0F 10 C3 movsd xmm0, xmm3 \n"
" \n"
" 00007BB8 F3/ 0F 5A C3 cvtss2sd xmm0, xmm3 \n"
" 00007BBC F2/ 0F 5A C3 cvtsd2ss xmm0, xmm3 \n"
" \n"
" \n"
" ; Source: xmm3, target: xmm1 \n"
" 00007BC0 F3/ 0F 10 CB movss xmm1, xmm3 \n"
" 00007BC4 F2/ 0F 10 CB movsd xmm1, xmm3 \n"
" \n"
" 00007BC8 F3/ 0F 5A CB cvtss2sd xmm1, xmm3 \n"
" 00007BCC F2/ 0F 5A CB cvtsd2ss xmm1, xmm3 \n"
" \n"
" \n"
" ; Source: xmm3, target: xmm2 \n"
" 00007BD0 F3/ 0F 10 D3 movss xmm2, xmm3 \n"
" 00007BD4 F2/ 0F 10 D3 movsd xmm2, xmm3 \n"
" \n"
" 00007BD8 F3/ 0F 5A D3 cvtss2sd xmm2, xmm3 \n"
" 00007BDC F2/ 0F 5A D3 cvtsd2ss xmm2, xmm3 \n"
" \n"
" \n"
" ; Source: xmm3, target: xmm3 \n"
" 00007BE0 F3/ 0F 10 DB movss xmm3, xmm3 \n"
" 00007BE4 F2/ 0F 10 DB movsd xmm3, xmm3 \n"
" \n"
" 00007BE8 F3/ 0F 5A DB cvtss2sd xmm3, xmm3 \n"
" 00007BEC F2/ 0F 5A DB cvtsd2ss xmm3, xmm3 \n"
" \n"
" \n"
" ; Source: xmm3, target: xmm4 \n"
" 00007BF0 F3/ 0F 10 E3 movss xmm4, xmm3 \n"
" 00007BF4 F2/ 0F 10 E3 movsd xmm4, xmm3 \n"
" \n"
" 00007BF8 F3/ 0F 5A E3 cvtss2sd xmm4, xmm3 \n"
" 00007BFC F2/ 0F 5A E3 cvtsd2ss xmm4, xmm3 \n"
" \n"
" \n"
" ; Source: xmm3, target: xmm5 \n"
" 00007C00 F3/ 0F 10 EB movss xmm5, xmm3 \n"
" 00007C04 F2/ 0F 10 EB movsd xmm5, xmm3 \n"
" \n"
" 00007C08 F3/ 0F 5A EB cvtss2sd xmm5, xmm3 \n"
" 00007C0C F2/ 0F 5A EB cvtsd2ss xmm5, xmm3 \n"
" \n"
" \n"
" ; Source: xmm3, target: xmm6 \n"
" 00007C10 F3/ 0F 10 F3 movss xmm6, xmm3 \n"
" 00007C14 F2/ 0F 10 F3 movsd xmm6, xmm3 \n"
" \n"
" 00007C18 F3/ 0F 5A F3 cvtss2sd xmm6, xmm3 \n"
" 00007C1C F2/ 0F 5A F3 cvtsd2ss xmm6, xmm3 \n"
" \n"
" \n"
" ; Source: xmm3, target: xmm7 \n"
" 00007C20 F3/ 0F 10 FB movss xmm7, xmm3 \n"
" 00007C24 F2/ 0F 10 FB movsd xmm7, xmm3 \n"
" \n"
" 00007C28 F3/ 0F 5A FB cvtss2sd xmm7, xmm3 \n"
" 00007C2C F2/ 0F 5A FB cvtsd2ss xmm7, xmm3 \n"
" \n"
" \n"
" ; Source: xmm3, target: xmm8 \n"
" 00007C30 F3/ 44/ 0F 10 C3 movss xmm8, xmm3 \n"
" 00007C35 F2/ 44/ 0F 10 C3 movsd xmm8, xmm3 \n"
" \n"
" 00007C3A F3/ 44/ 0F 5A C3 cvtss2sd xmm8, xmm3 \n"
" 00007C3F F2/ 44/ 0F 5A C3 cvtsd2ss xmm8, xmm3 \n"
" \n"
" \n"
" ; Source: xmm3, target: xmm9 \n"
" 00007C44 F3/ 44/ 0F 10 CB movss xmm9, xmm3 \n"
" 00007C49 F2/ 44/ 0F 10 CB movsd xmm9, xmm3 \n"
" \n"
" 00007C4E F3/ 44/ 0F 5A CB cvtss2sd xmm9, xmm3 \n"
" 00007C53 F2/ 44/ 0F 5A CB cvtsd2ss xmm9, xmm3 \n"
" \n"
" \n"
" ; Source: xmm3, target: xmm10 \n"
" 00007C58 F3/ 44/ 0F 10 D3 movss xmm10, xmm3 \n"
" 00007C5D F2/ 44/ 0F 10 D3 movsd xmm10, xmm3 \n"
" \n"
" 00007C62 F3/ 44/ 0F 5A D3 cvtss2sd xmm10, xmm3 \n"
" 00007C67 F2/ 44/ 0F 5A D3 cvtsd2ss xmm10, xmm3 \n"
" \n"
" \n"
" ; Source: xmm3, target: xmm11 \n"
" 00007C6C F3/ 44/ 0F 10 DB movss xmm11, xmm3 \n"
" 00007C71 F2/ 44/ 0F 10 DB movsd xmm11, xmm3 \n"
" \n"
" 00007C76 F3/ 44/ 0F 5A DB cvtss2sd xmm11, xmm3 \n"
" 00007C7B F2/ 44/ 0F 5A DB cvtsd2ss xmm11, xmm3 \n"
" \n"
" \n"
" ; Source: xmm3, target: xmm12 \n"
" 00007C80 F3/ 44/ 0F 10 E3 movss xmm12, xmm3 \n"
" 00007C85 F2/ 44/ 0F 10 E3 movsd xmm12, xmm3 \n"
" \n"
" 00007C8A F3/ 44/ 0F 5A E3 cvtss2sd xmm12, xmm3 \n"
" 00007C8F F2/ 44/ 0F 5A E3 cvtsd2ss xmm12, xmm3 \n"
" \n"
" \n"
" ; Source: xmm3, target: xmm13 \n"
" 00007C94 F3/ 44/ 0F 10 EB movss xmm13, xmm3 \n"
" 00007C99 F2/ 44/ 0F 10 EB movsd xmm13, xmm3 \n"
" \n"
" 00007C9E F3/ 44/ 0F 5A EB cvtss2sd xmm13, xmm3 \n"
" 00007CA3 F2/ 44/ 0F 5A EB cvtsd2ss xmm13, xmm3 \n"
" \n"
" \n"
" ; Source: xmm3, target: xmm14 \n"
" 00007CA8 F3/ 44/ 0F 10 F3 movss xmm14, xmm3 \n"
" 00007CAD F2/ 44/ 0F 10 F3 movsd xmm14, xmm3 \n"
" \n"
" 00007CB2 F3/ 44/ 0F 5A F3 cvtss2sd xmm14, xmm3 \n"
" 00007CB7 F2/ 44/ 0F 5A F3 cvtsd2ss xmm14, xmm3 \n"
" \n"
" \n"
" ; Source: xmm3, target: xmm15 \n"
" 00007CBC F3/ 44/ 0F 10 FB movss xmm15, xmm3 \n"
" 00007CC1 F2/ 44/ 0F 10 FB movsd xmm15, xmm3 \n"
" \n"
" 00007CC6 F3/ 44/ 0F 5A FB cvtss2sd xmm15, xmm3 \n"
" 00007CCB F2/ 44/ 0F 5A FB cvtsd2ss xmm15, xmm3 \n"
" \n"
" \n"
" ; Source: xmm4, target: xmm0 \n"
" 00007CD0 F3/ 0F 10 C4 movss xmm0, xmm4 \n"
" 00007CD4 F2/ 0F 10 C4 movsd xmm0, xmm4 \n"
" \n"
" 00007CD8 F3/ 0F 5A C4 cvtss2sd xmm0, xmm4 \n"
" 00007CDC F2/ 0F 5A C4 cvtsd2ss xmm0, xmm4 \n"
" \n"
" \n"
" ; Source: xmm4, target: xmm1 \n"
" 00007CE0 F3/ 0F 10 CC movss xmm1, xmm4 \n"
" 00007CE4 F2/ 0F 10 CC movsd xmm1, xmm4 \n"
" \n"
" 00007CE8 F3/ 0F 5A CC cvtss2sd xmm1, xmm4 \n"
" 00007CEC F2/ 0F 5A CC cvtsd2ss xmm1, xmm4 \n"
" \n"
" \n"
" ; Source: xmm4, target: xmm2 \n"
" 00007CF0 F3/ 0F 10 D4 movss xmm2, xmm4 \n"
" 00007CF4 F2/ 0F 10 D4 movsd xmm2, xmm4 \n"
" \n"
" 00007CF8 F3/ 0F 5A D4 cvtss2sd xmm2, xmm4 \n"
" 00007CFC F2/ 0F 5A D4 cvtsd2ss xmm2, xmm4 \n"
" \n"
" \n"
" ; Source: xmm4, target: xmm3 \n"
" 00007D00 F3/ 0F 10 DC movss xmm3, xmm4 \n"
" 00007D04 F2/ 0F 10 DC movsd xmm3, xmm4 \n"
" \n"
" 00007D08 F3/ 0F 5A DC cvtss2sd xmm3, xmm4 \n"
" 00007D0C F2/ 0F 5A DC cvtsd2ss xmm3, xmm4 \n"
" \n"
" \n"
" ; Source: xmm4, target: xmm4 \n"
" 00007D10 F3/ 0F 10 E4 movss xmm4, xmm4 \n"
" 00007D14 F2/ 0F 10 E4 movsd xmm4, xmm4 \n"
" \n"
" 00007D18 F3/ 0F 5A E4 cvtss2sd xmm4, xmm4 \n"
" 00007D1C F2/ 0F 5A E4 cvtsd2ss xmm4, xmm4 \n"
" \n"
" \n"
" ; Source: xmm4, target: xmm5 \n"
" 00007D20 F3/ 0F 10 EC movss xmm5, xmm4 \n"
" 00007D24 F2/ 0F 10 EC movsd xmm5, xmm4 \n"
" \n"
" 00007D28 F3/ 0F 5A EC cvtss2sd xmm5, xmm4 \n"
" 00007D2C F2/ 0F 5A EC cvtsd2ss xmm5, xmm4 \n"
" \n"
" \n"
" ; Source: xmm4, target: xmm6 \n"
" 00007D30 F3/ 0F 10 F4 movss xmm6, xmm4 \n"
" 00007D34 F2/ 0F 10 F4 movsd xmm6, xmm4 \n"
" \n"
" 00007D38 F3/ 0F 5A F4 cvtss2sd xmm6, xmm4 \n"
" 00007D3C F2/ 0F 5A F4 cvtsd2ss xmm6, xmm4 \n"
" \n"
" \n"
" ; Source: xmm4, target: xmm7 \n"
" 00007D40 F3/ 0F 10 FC movss xmm7, xmm4 \n"
" 00007D44 F2/ 0F 10 FC movsd xmm7, xmm4 \n"
" \n"
" 00007D48 F3/ 0F 5A FC cvtss2sd xmm7, xmm4 \n"
" 00007D4C F2/ 0F 5A FC cvtsd2ss xmm7, xmm4 \n"
" \n"
" \n"
" ; Source: xmm4, target: xmm8 \n"
" 00007D50 F3/ 44/ 0F 10 C4 movss xmm8, xmm4 \n"
" 00007D55 F2/ 44/ 0F 10 C4 movsd xmm8, xmm4 \n"
" \n"
" 00007D5A F3/ 44/ 0F 5A C4 cvtss2sd xmm8, xmm4 \n"
" 00007D5F F2/ 44/ 0F 5A C4 cvtsd2ss xmm8, xmm4 \n"
" \n"
" \n"
" ; Source: xmm4, target: xmm9 \n"
" 00007D64 F3/ 44/ 0F 10 CC movss xmm9, xmm4 \n"
" 00007D69 F2/ 44/ 0F 10 CC movsd xmm9, xmm4 \n"
" \n"
" 00007D6E F3/ 44/ 0F 5A CC cvtss2sd xmm9, xmm4 \n"
" 00007D73 F2/ 44/ 0F 5A CC cvtsd2ss xmm9, xmm4 \n"
" \n"
" \n"
" ; Source: xmm4, target: xmm10 \n"
" 00007D78 F3/ 44/ 0F 10 D4 movss xmm10, xmm4 \n"
" 00007D7D F2/ 44/ 0F 10 D4 movsd xmm10, xmm4 \n"
" \n"
" 00007D82 F3/ 44/ 0F 5A D4 cvtss2sd xmm10, xmm4 \n"
" 00007D87 F2/ 44/ 0F 5A D4 cvtsd2ss xmm10, xmm4 \n"
" \n"
" \n"
" ; Source: xmm4, target: xmm11 \n"
" 00007D8C F3/ 44/ 0F 10 DC movss xmm11, xmm4 \n"
" 00007D91 F2/ 44/ 0F 10 DC movsd xmm11, xmm4 \n"
" \n"
" 00007D96 F3/ 44/ 0F 5A DC cvtss2sd xmm11, xmm4 \n"
" 00007D9B F2/ 44/ 0F 5A DC cvtsd2ss xmm11, xmm4 \n"
" \n"
" \n"
" ; Source: xmm4, target: xmm12 \n"
" 00007DA0 F3/ 44/ 0F 10 E4 movss xmm12, xmm4 \n"
" 00007DA5 F2/ 44/ 0F 10 E4 movsd xmm12, xmm4 \n"
" \n"
" 00007DAA F3/ 44/ 0F 5A E4 cvtss2sd xmm12, xmm4 \n"
" 00007DAF F2/ 44/ 0F 5A E4 cvtsd2ss xmm12, xmm4 \n"
" \n"
" \n"
" ; Source: xmm4, target: xmm13 \n"
" 00007DB4 F3/ 44/ 0F 10 EC movss xmm13, xmm4 \n"
" 00007DB9 F2/ 44/ 0F 10 EC movsd xmm13, xmm4 \n"
" \n"
" 00007DBE F3/ 44/ 0F 5A EC cvtss2sd xmm13, xmm4 \n"
" 00007DC3 F2/ 44/ 0F 5A EC cvtsd2ss xmm13, xmm4 \n"
" \n"
" \n"
" ; Source: xmm4, target: xmm14 \n"
" 00007DC8 F3/ 44/ 0F 10 F4 movss xmm14, xmm4 \n"
" 00007DCD F2/ 44/ 0F 10 F4 movsd xmm14, xmm4 \n"
" \n"
" 00007DD2 F3/ 44/ 0F 5A F4 cvtss2sd xmm14, xmm4 \n"
" 00007DD7 F2/ 44/ 0F 5A F4 cvtsd2ss xmm14, xmm4 \n"
" \n"
" \n"
" ; Source: xmm4, target: xmm15 \n"
" 00007DDC F3/ 44/ 0F 10 FC movss xmm15, xmm4 \n"
" 00007DE1 F2/ 44/ 0F 10 FC movsd xmm15, xmm4 \n"
" \n"
" 00007DE6 F3/ 44/ 0F 5A FC cvtss2sd xmm15, xmm4 \n"
" 00007DEB F2/ 44/ 0F 5A FC cvtsd2ss xmm15, xmm4 \n"
" \n"
" \n"
" ; Source: xmm5, target: xmm0 \n"
" 00007DF0 F3/ 0F 10 C5 movss xmm0, xmm5 \n"
" 00007DF4 F2/ 0F 10 C5 movsd xmm0, xmm5 \n"
" \n"
" 00007DF8 F3/ 0F 5A C5 cvtss2sd xmm0, xmm5 \n"
" 00007DFC F2/ 0F 5A C5 cvtsd2ss xmm0, xmm5 \n"
" \n"
" \n"
" ; Source: xmm5, target: xmm1 \n"
" 00007E00 F3/ 0F 10 CD movss xmm1, xmm5 \n"
" 00007E04 F2/ 0F 10 CD movsd xmm1, xmm5 \n"
" \n"
" 00007E08 F3/ 0F 5A CD cvtss2sd xmm1, xmm5 \n"
" 00007E0C F2/ 0F 5A CD cvtsd2ss xmm1, xmm5 \n"
" \n"
" \n"
" ; Source: xmm5, target: xmm2 \n"
" 00007E10 F3/ 0F 10 D5 movss xmm2, xmm5 \n"
" 00007E14 F2/ 0F 10 D5 movsd xmm2, xmm5 \n"
" \n"
" 00007E18 F3/ 0F 5A D5 cvtss2sd xmm2, xmm5 \n"
" 00007E1C F2/ 0F 5A D5 cvtsd2ss xmm2, xmm5 \n"
" \n"
" \n"
" ; Source: xmm5, target: xmm3 \n"
" 00007E20 F3/ 0F 10 DD movss xmm3, xmm5 \n"
" 00007E24 F2/ 0F 10 DD movsd xmm3, xmm5 \n"
" \n"
" 00007E28 F3/ 0F 5A DD cvtss2sd xmm3, xmm5 \n"
" 00007E2C F2/ 0F 5A DD cvtsd2ss xmm3, xmm5 \n"
" \n"
" \n"
" ; Source: xmm5, target: xmm4 \n"
" 00007E30 F3/ 0F 10 E5 movss xmm4, xmm5 \n"
" 00007E34 F2/ 0F 10 E5 movsd xmm4, xmm5 \n"
" \n"
" 00007E38 F3/ 0F 5A E5 cvtss2sd xmm4, xmm5 \n"
" 00007E3C F2/ 0F 5A E5 cvtsd2ss xmm4, xmm5 \n"
" \n"
" \n"
" ; Source: xmm5, target: xmm5 \n"
" 00007E40 F3/ 0F 10 ED movss xmm5, xmm5 \n"
" 00007E44 F2/ 0F 10 ED movsd xmm5, xmm5 \n"
" \n"
" 00007E48 F3/ 0F 5A ED cvtss2sd xmm5, xmm5 \n"
" 00007E4C F2/ 0F 5A ED cvtsd2ss xmm5, xmm5 \n"
" \n"
" \n"
" ; Source: xmm5, target: xmm6 \n"
" 00007E50 F3/ 0F 10 F5 movss xmm6, xmm5 \n"
" 00007E54 F2/ 0F 10 F5 movsd xmm6, xmm5 \n"
" \n"
" 00007E58 F3/ 0F 5A F5 cvtss2sd xmm6, xmm5 \n"
" 00007E5C F2/ 0F 5A F5 cvtsd2ss xmm6, xmm5 \n"
" \n"
" \n"
" ; Source: xmm5, target: xmm7 \n"
" 00007E60 F3/ 0F 10 FD movss xmm7, xmm5 \n"
" 00007E64 F2/ 0F 10 FD movsd xmm7, xmm5 \n"
" \n"
" 00007E68 F3/ 0F 5A FD cvtss2sd xmm7, xmm5 \n"
" 00007E6C F2/ 0F 5A FD cvtsd2ss xmm7, xmm5 \n"
" \n"
" \n"
" ; Source: xmm5, target: xmm8 \n"
" 00007E70 F3/ 44/ 0F 10 C5 movss xmm8, xmm5 \n"
" 00007E75 F2/ 44/ 0F 10 C5 movsd xmm8, xmm5 \n"
" \n"
" 00007E7A F3/ 44/ 0F 5A C5 cvtss2sd xmm8, xmm5 \n"
" 00007E7F F2/ 44/ 0F 5A C5 cvtsd2ss xmm8, xmm5 \n"
" \n"
" \n"
" ; Source: xmm5, target: xmm9 \n"
" 00007E84 F3/ 44/ 0F 10 CD movss xmm9, xmm5 \n"
" 00007E89 F2/ 44/ 0F 10 CD movsd xmm9, xmm5 \n"
" \n"
" 00007E8E F3/ 44/ 0F 5A CD cvtss2sd xmm9, xmm5 \n"
" 00007E93 F2/ 44/ 0F 5A CD cvtsd2ss xmm9, xmm5 \n"
" \n"
" \n"
" ; Source: xmm5, target: xmm10 \n"
" 00007E98 F3/ 44/ 0F 10 D5 movss xmm10, xmm5 \n"
" 00007E9D F2/ 44/ 0F 10 D5 movsd xmm10, xmm5 \n"
" \n"
" 00007EA2 F3/ 44/ 0F 5A D5 cvtss2sd xmm10, xmm5 \n"
" 00007EA7 F2/ 44/ 0F 5A D5 cvtsd2ss xmm10, xmm5 \n"
" \n"
" \n"
" ; Source: xmm5, target: xmm11 \n"
" 00007EAC F3/ 44/ 0F 10 DD movss xmm11, xmm5 \n"
" 00007EB1 F2/ 44/ 0F 10 DD movsd xmm11, xmm5 \n"
" \n"
" 00007EB6 F3/ 44/ 0F 5A DD cvtss2sd xmm11, xmm5 \n"
" 00007EBB F2/ 44/ 0F 5A DD cvtsd2ss xmm11, xmm5 \n"
" \n"
" \n"
" ; Source: xmm5, target: xmm12 \n"
" 00007EC0 F3/ 44/ 0F 10 E5 movss xmm12, xmm5 \n"
" 00007EC5 F2/ 44/ 0F 10 E5 movsd xmm12, xmm5 \n"
" \n"
" 00007ECA F3/ 44/ 0F 5A E5 cvtss2sd xmm12, xmm5 \n"
" 00007ECF F2/ 44/ 0F 5A E5 cvtsd2ss xmm12, xmm5 \n"
" \n"
" \n"
" ; Source: xmm5, target: xmm13 \n"
" 00007ED4 F3/ 44/ 0F 10 ED movss xmm13, xmm5 \n"
" 00007ED9 F2/ 44/ 0F 10 ED movsd xmm13, xmm5 \n"
" \n"
" 00007EDE F3/ 44/ 0F 5A ED cvtss2sd xmm13, xmm5 \n"
" 00007EE3 F2/ 44/ 0F 5A ED cvtsd2ss xmm13, xmm5 \n"
" \n"
" \n"
" ; Source: xmm5, target: xmm14 \n"
" 00007EE8 F3/ 44/ 0F 10 F5 movss xmm14, xmm5 \n"
" 00007EED F2/ 44/ 0F 10 F5 movsd xmm14, xmm5 \n"
" \n"
" 00007EF2 F3/ 44/ 0F 5A F5 cvtss2sd xmm14, xmm5 \n"
" 00007EF7 F2/ 44/ 0F 5A F5 cvtsd2ss xmm14, xmm5 \n"
" \n"
" \n"
" ; Source: xmm5, target: xmm15 \n"
" 00007EFC F3/ 44/ 0F 10 FD movss xmm15, xmm5 \n"
" 00007F01 F2/ 44/ 0F 10 FD movsd xmm15, xmm5 \n"
" \n"
" 00007F06 F3/ 44/ 0F 5A FD cvtss2sd xmm15, xmm5 \n"
" 00007F0B F2/ 44/ 0F 5A FD cvtsd2ss xmm15, xmm5 \n"
" \n"
" \n"
" ; Source: xmm6, target: xmm0 \n"
" 00007F10 F3/ 0F 10 C6 movss xmm0, xmm6 \n"
" 00007F14 F2/ 0F 10 C6 movsd xmm0, xmm6 \n"
" \n"
" 00007F18 F3/ 0F 5A C6 cvtss2sd xmm0, xmm6 \n"
" 00007F1C F2/ 0F 5A C6 cvtsd2ss xmm0, xmm6 \n"
" \n"
" \n"
" ; Source: xmm6, target: xmm1 \n"
" 00007F20 F3/ 0F 10 CE movss xmm1, xmm6 \n"
" 00007F24 F2/ 0F 10 CE movsd xmm1, xmm6 \n"
" \n"
" 00007F28 F3/ 0F 5A CE cvtss2sd xmm1, xmm6 \n"
" 00007F2C F2/ 0F 5A CE cvtsd2ss xmm1, xmm6 \n"
" \n"
" \n"
" ; Source: xmm6, target: xmm2 \n"
" 00007F30 F3/ 0F 10 D6 movss xmm2, xmm6 \n"
" 00007F34 F2/ 0F 10 D6 movsd xmm2, xmm6 \n"
" \n"
" 00007F38 F3/ 0F 5A D6 cvtss2sd xmm2, xmm6 \n"
" 00007F3C F2/ 0F 5A D6 cvtsd2ss xmm2, xmm6 \n"
" \n"
" \n"
" ; Source: xmm6, target: xmm3 \n"
" 00007F40 F3/ 0F 10 DE movss xmm3, xmm6 \n"
" 00007F44 F2/ 0F 10 DE movsd xmm3, xmm6 \n"
" \n"
" 00007F48 F3/ 0F 5A DE cvtss2sd xmm3, xmm6 \n"
" 00007F4C F2/ 0F 5A DE cvtsd2ss xmm3, xmm6 \n"
" \n"
" \n"
" ; Source: xmm6, target: xmm4 \n"
" 00007F50 F3/ 0F 10 E6 movss xmm4, xmm6 \n"
" 00007F54 F2/ 0F 10 E6 movsd xmm4, xmm6 \n"
" \n"
" 00007F58 F3/ 0F 5A E6 cvtss2sd xmm4, xmm6 \n"
" 00007F5C F2/ 0F 5A E6 cvtsd2ss xmm4, xmm6 \n"
" \n"
" \n"
" ; Source: xmm6, target: xmm5 \n"
" 00007F60 F3/ 0F 10 EE movss xmm5, xmm6 \n"
" 00007F64 F2/ 0F 10 EE movsd xmm5, xmm6 \n"
" \n"
" 00007F68 F3/ 0F 5A EE cvtss2sd xmm5, xmm6 \n"
" 00007F6C F2/ 0F 5A EE cvtsd2ss xmm5, xmm6 \n"
" \n"
" \n"
" ; Source: xmm6, target: xmm6 \n"
" 00007F70 F3/ 0F 10 F6 movss xmm6, xmm6 \n"
" 00007F74 F2/ 0F 10 F6 movsd xmm6, xmm6 \n"
" \n"
" 00007F78 F3/ 0F 5A F6 cvtss2sd xmm6, xmm6 \n"
" 00007F7C F2/ 0F 5A F6 cvtsd2ss xmm6, xmm6 \n"
" \n"
" \n"
" ; Source: xmm6, target: xmm7 \n"
" 00007F80 F3/ 0F 10 FE movss xmm7, xmm6 \n"
" 00007F84 F2/ 0F 10 FE movsd xmm7, xmm6 \n"
" \n"
" 00007F88 F3/ 0F 5A FE cvtss2sd xmm7, xmm6 \n"
" 00007F8C F2/ 0F 5A FE cvtsd2ss xmm7, xmm6 \n"
" \n"
" \n"
" ; Source: xmm6, target: xmm8 \n"
" 00007F90 F3/ 44/ 0F 10 C6 movss xmm8, xmm6 \n"
" 00007F95 F2/ 44/ 0F 10 C6 movsd xmm8, xmm6 \n"
" \n"
" 00007F9A F3/ 44/ 0F 5A C6 cvtss2sd xmm8, xmm6 \n"
" 00007F9F F2/ 44/ 0F 5A C6 cvtsd2ss xmm8, xmm6 \n"
" \n"
" \n"
" ; Source: xmm6, target: xmm9 \n"
" 00007FA4 F3/ 44/ 0F 10 CE movss xmm9, xmm6 \n"
" 00007FA9 F2/ 44/ 0F 10 CE movsd xmm9, xmm6 \n"
" \n"
" 00007FAE F3/ 44/ 0F 5A CE cvtss2sd xmm9, xmm6 \n"
" 00007FB3 F2/ 44/ 0F 5A CE cvtsd2ss xmm9, xmm6 \n"
" \n"
" \n"
" ; Source: xmm6, target: xmm10 \n"
" 00007FB8 F3/ 44/ 0F 10 D6 movss xmm10, xmm6 \n"
" 00007FBD F2/ 44/ 0F 10 D6 movsd xmm10, xmm6 \n"
" \n"
" 00007FC2 F3/ 44/ 0F 5A D6 cvtss2sd xmm10, xmm6 \n"
" 00007FC7 F2/ 44/ 0F 5A D6 cvtsd2ss xmm10, xmm6 \n"
" \n"
" \n"
" ; Source: xmm6, target: xmm11 \n"
" 00007FCC F3/ 44/ 0F 10 DE movss xmm11, xmm6 \n"
" 00007FD1 F2/ 44/ 0F 10 DE movsd xmm11, xmm6 \n"
" \n"
" 00007FD6 F3/ 44/ 0F 5A DE cvtss2sd xmm11, xmm6 \n"
" 00007FDB F2/ 44/ 0F 5A DE cvtsd2ss xmm11, xmm6 \n"
" \n"
" \n"
" ; Source: xmm6, target: xmm12 \n"
" 00007FE0 F3/ 44/ 0F 10 E6 movss xmm12, xmm6 \n"
" 00007FE5 F2/ 44/ 0F 10 E6 movsd xmm12, xmm6 \n"
" \n"
" 00007FEA F3/ 44/ 0F 5A E6 cvtss2sd xmm12, xmm6 \n"
" 00007FEF F2/ 44/ 0F 5A E6 cvtsd2ss xmm12, xmm6 \n"
" \n"
" \n"
" ; Source: xmm6, target: xmm13 \n"
" 00007FF4 F3/ 44/ 0F 10 EE movss xmm13, xmm6 \n"
" 00007FF9 F2/ 44/ 0F 10 EE movsd xmm13, xmm6 \n"
" \n"
" 00007FFE F3/ 44/ 0F 5A EE cvtss2sd xmm13, xmm6 \n"
" 00008003 F2/ 44/ 0F 5A EE cvtsd2ss xmm13, xmm6 \n";
ml64Output +=
" \n"
" \n"
" ; Source: xmm6, target: xmm14 \n"
" 00008008 F3/ 44/ 0F 10 F6 movss xmm14, xmm6 \n"
" 0000800D F2/ 44/ 0F 10 F6 movsd xmm14, xmm6 \n"
" \n"
" 00008012 F3/ 44/ 0F 5A F6 cvtss2sd xmm14, xmm6 \n"
" 00008017 F2/ 44/ 0F 5A F6 cvtsd2ss xmm14, xmm6 \n"
" \n"
" \n"
" ; Source: xmm6, target: xmm15 \n"
" 0000801C F3/ 44/ 0F 10 FE movss xmm15, xmm6 \n"
" 00008021 F2/ 44/ 0F 10 FE movsd xmm15, xmm6 \n"
" \n"
" 00008026 F3/ 44/ 0F 5A FE cvtss2sd xmm15, xmm6 \n"
" 0000802B F2/ 44/ 0F 5A FE cvtsd2ss xmm15, xmm6 \n"
" \n"
" \n"
" ; Source: xmm7, target: xmm0 \n"
" 00008030 F3/ 0F 10 C7 movss xmm0, xmm7 \n"
" 00008034 F2/ 0F 10 C7 movsd xmm0, xmm7 \n"
" \n"
" 00008038 F3/ 0F 5A C7 cvtss2sd xmm0, xmm7 \n"
" 0000803C F2/ 0F 5A C7 cvtsd2ss xmm0, xmm7 \n"
" \n"
" \n"
" ; Source: xmm7, target: xmm1 \n"
" 00008040 F3/ 0F 10 CF movss xmm1, xmm7 \n"
" 00008044 F2/ 0F 10 CF movsd xmm1, xmm7 \n"
" \n"
" 00008048 F3/ 0F 5A CF cvtss2sd xmm1, xmm7 \n"
" 0000804C F2/ 0F 5A CF cvtsd2ss xmm1, xmm7 \n"
" \n"
" \n"
" ; Source: xmm7, target: xmm2 \n"
" 00008050 F3/ 0F 10 D7 movss xmm2, xmm7 \n"
" 00008054 F2/ 0F 10 D7 movsd xmm2, xmm7 \n"
" \n"
" 00008058 F3/ 0F 5A D7 cvtss2sd xmm2, xmm7 \n"
" 0000805C F2/ 0F 5A D7 cvtsd2ss xmm2, xmm7 \n"
" \n"
" \n"
" ; Source: xmm7, target: xmm3 \n"
" 00008060 F3/ 0F 10 DF movss xmm3, xmm7 \n"
" 00008064 F2/ 0F 10 DF movsd xmm3, xmm7 \n"
" \n"
" 00008068 F3/ 0F 5A DF cvtss2sd xmm3, xmm7 \n"
" 0000806C F2/ 0F 5A DF cvtsd2ss xmm3, xmm7 \n"
" \n"
" \n"
" ; Source: xmm7, target: xmm4 \n"
" 00008070 F3/ 0F 10 E7 movss xmm4, xmm7 \n"
" 00008074 F2/ 0F 10 E7 movsd xmm4, xmm7 \n"
" \n"
" 00008078 F3/ 0F 5A E7 cvtss2sd xmm4, xmm7 \n"
" 0000807C F2/ 0F 5A E7 cvtsd2ss xmm4, xmm7 \n"
" \n"
" \n"
" ; Source: xmm7, target: xmm5 \n"
" 00008080 F3/ 0F 10 EF movss xmm5, xmm7 \n"
" 00008084 F2/ 0F 10 EF movsd xmm5, xmm7 \n"
" \n"
" 00008088 F3/ 0F 5A EF cvtss2sd xmm5, xmm7 \n"
" 0000808C F2/ 0F 5A EF cvtsd2ss xmm5, xmm7 \n"
" \n"
" \n"
" ; Source: xmm7, target: xmm6 \n"
" 00008090 F3/ 0F 10 F7 movss xmm6, xmm7 \n"
" 00008094 F2/ 0F 10 F7 movsd xmm6, xmm7 \n"
" \n"
" 00008098 F3/ 0F 5A F7 cvtss2sd xmm6, xmm7 \n"
" 0000809C F2/ 0F 5A F7 cvtsd2ss xmm6, xmm7 \n"
" \n"
" \n"
" ; Source: xmm7, target: xmm7 \n"
" 000080A0 F3/ 0F 10 FF movss xmm7, xmm7 \n"
" 000080A4 F2/ 0F 10 FF movsd xmm7, xmm7 \n"
" \n"
" 000080A8 F3/ 0F 5A FF cvtss2sd xmm7, xmm7 \n"
" 000080AC F2/ 0F 5A FF cvtsd2ss xmm7, xmm7 \n"
" \n"
" \n"
" ; Source: xmm7, target: xmm8 \n"
" 000080B0 F3/ 44/ 0F 10 C7 movss xmm8, xmm7 \n"
" 000080B5 F2/ 44/ 0F 10 C7 movsd xmm8, xmm7 \n"
" \n"
" 000080BA F3/ 44/ 0F 5A C7 cvtss2sd xmm8, xmm7 \n"
" 000080BF F2/ 44/ 0F 5A C7 cvtsd2ss xmm8, xmm7 \n"
" \n"
" \n"
" ; Source: xmm7, target: xmm9 \n"
" 000080C4 F3/ 44/ 0F 10 CF movss xmm9, xmm7 \n"
" 000080C9 F2/ 44/ 0F 10 CF movsd xmm9, xmm7 \n"
" \n"
" 000080CE F3/ 44/ 0F 5A CF cvtss2sd xmm9, xmm7 \n"
" 000080D3 F2/ 44/ 0F 5A CF cvtsd2ss xmm9, xmm7 \n"
" \n"
" \n"
" ; Source: xmm7, target: xmm10 \n"
" 000080D8 F3/ 44/ 0F 10 D7 movss xmm10, xmm7 \n"
" 000080DD F2/ 44/ 0F 10 D7 movsd xmm10, xmm7 \n"
" \n"
" 000080E2 F3/ 44/ 0F 5A D7 cvtss2sd xmm10, xmm7 \n"
" 000080E7 F2/ 44/ 0F 5A D7 cvtsd2ss xmm10, xmm7 \n"
" \n"
" \n"
" ; Source: xmm7, target: xmm11 \n"
" 000080EC F3/ 44/ 0F 10 DF movss xmm11, xmm7 \n"
" 000080F1 F2/ 44/ 0F 10 DF movsd xmm11, xmm7 \n"
" \n"
" 000080F6 F3/ 44/ 0F 5A DF cvtss2sd xmm11, xmm7 \n"
" 000080FB F2/ 44/ 0F 5A DF cvtsd2ss xmm11, xmm7 \n"
" \n"
" \n"
" ; Source: xmm7, target: xmm12 \n"
" 00008100 F3/ 44/ 0F 10 E7 movss xmm12, xmm7 \n"
" 00008105 F2/ 44/ 0F 10 E7 movsd xmm12, xmm7 \n"
" \n"
" 0000810A F3/ 44/ 0F 5A E7 cvtss2sd xmm12, xmm7 \n"
" 0000810F F2/ 44/ 0F 5A E7 cvtsd2ss xmm12, xmm7 \n"
" \n"
" \n"
" ; Source: xmm7, target: xmm13 \n"
" 00008114 F3/ 44/ 0F 10 EF movss xmm13, xmm7 \n"
" 00008119 F2/ 44/ 0F 10 EF movsd xmm13, xmm7 \n"
" \n"
" 0000811E F3/ 44/ 0F 5A EF cvtss2sd xmm13, xmm7 \n"
" 00008123 F2/ 44/ 0F 5A EF cvtsd2ss xmm13, xmm7 \n"
" \n"
" \n"
" ; Source: xmm7, target: xmm14 \n"
" 00008128 F3/ 44/ 0F 10 F7 movss xmm14, xmm7 \n"
" 0000812D F2/ 44/ 0F 10 F7 movsd xmm14, xmm7 \n"
" \n"
" 00008132 F3/ 44/ 0F 5A F7 cvtss2sd xmm14, xmm7 \n"
" 00008137 F2/ 44/ 0F 5A F7 cvtsd2ss xmm14, xmm7 \n"
" \n"
" \n"
" ; Source: xmm7, target: xmm15 \n"
" 0000813C F3/ 44/ 0F 10 FF movss xmm15, xmm7 \n"
" 00008141 F2/ 44/ 0F 10 FF movsd xmm15, xmm7 \n"
" \n"
" 00008146 F3/ 44/ 0F 5A FF cvtss2sd xmm15, xmm7 \n"
" 0000814B F2/ 44/ 0F 5A FF cvtsd2ss xmm15, xmm7 \n"
" \n"
" \n"
" ; Source: xmm8, target: xmm0 \n"
" 00008150 F3/ 41/ 0F 10 C0 movss xmm0, xmm8 \n"
" 00008155 F2/ 41/ 0F 10 C0 movsd xmm0, xmm8 \n"
" \n"
" 0000815A F3/ 41/ 0F 5A C0 cvtss2sd xmm0, xmm8 \n"
" 0000815F F2/ 41/ 0F 5A C0 cvtsd2ss xmm0, xmm8 \n"
" \n"
" \n"
" ; Source: xmm8, target: xmm1 \n"
" 00008164 F3/ 41/ 0F 10 C8 movss xmm1, xmm8 \n"
" 00008169 F2/ 41/ 0F 10 C8 movsd xmm1, xmm8 \n"
" \n"
" 0000816E F3/ 41/ 0F 5A C8 cvtss2sd xmm1, xmm8 \n"
" 00008173 F2/ 41/ 0F 5A C8 cvtsd2ss xmm1, xmm8 \n"
" \n"
" \n"
" ; Source: xmm8, target: xmm2 \n"
" 00008178 F3/ 41/ 0F 10 D0 movss xmm2, xmm8 \n"
" 0000817D F2/ 41/ 0F 10 D0 movsd xmm2, xmm8 \n"
" \n"
" 00008182 F3/ 41/ 0F 5A D0 cvtss2sd xmm2, xmm8 \n"
" 00008187 F2/ 41/ 0F 5A D0 cvtsd2ss xmm2, xmm8 \n"
" \n"
" \n"
" ; Source: xmm8, target: xmm3 \n"
" 0000818C F3/ 41/ 0F 10 D8 movss xmm3, xmm8 \n"
" 00008191 F2/ 41/ 0F 10 D8 movsd xmm3, xmm8 \n"
" \n"
" 00008196 F3/ 41/ 0F 5A D8 cvtss2sd xmm3, xmm8 \n"
" 0000819B F2/ 41/ 0F 5A D8 cvtsd2ss xmm3, xmm8 \n"
" \n"
" \n"
" ; Source: xmm8, target: xmm4 \n"
" 000081A0 F3/ 41/ 0F 10 E0 movss xmm4, xmm8 \n"
" 000081A5 F2/ 41/ 0F 10 E0 movsd xmm4, xmm8 \n"
" \n"
" 000081AA F3/ 41/ 0F 5A E0 cvtss2sd xmm4, xmm8 \n"
" 000081AF F2/ 41/ 0F 5A E0 cvtsd2ss xmm4, xmm8 \n"
" \n"
" \n"
" ; Source: xmm8, target: xmm5 \n"
" 000081B4 F3/ 41/ 0F 10 E8 movss xmm5, xmm8 \n"
" 000081B9 F2/ 41/ 0F 10 E8 movsd xmm5, xmm8 \n"
" \n"
" 000081BE F3/ 41/ 0F 5A E8 cvtss2sd xmm5, xmm8 \n"
" 000081C3 F2/ 41/ 0F 5A E8 cvtsd2ss xmm5, xmm8 \n"
" \n"
" \n"
" ; Source: xmm8, target: xmm6 \n"
" 000081C8 F3/ 41/ 0F 10 F0 movss xmm6, xmm8 \n"
" 000081CD F2/ 41/ 0F 10 F0 movsd xmm6, xmm8 \n"
" \n"
" 000081D2 F3/ 41/ 0F 5A F0 cvtss2sd xmm6, xmm8 \n"
" 000081D7 F2/ 41/ 0F 5A F0 cvtsd2ss xmm6, xmm8 \n"
" \n"
" \n"
" ; Source: xmm8, target: xmm7 \n"
" 000081DC F3/ 41/ 0F 10 F8 movss xmm7, xmm8 \n"
" 000081E1 F2/ 41/ 0F 10 F8 movsd xmm7, xmm8 \n"
" \n"
" 000081E6 F3/ 41/ 0F 5A F8 cvtss2sd xmm7, xmm8 \n"
" 000081EB F2/ 41/ 0F 5A F8 cvtsd2ss xmm7, xmm8 \n"
" \n"
" \n"
" ; Source: xmm8, target: xmm8 \n"
" 000081F0 F3/ 45/ 0F 10 C0 movss xmm8, xmm8 \n"
" 000081F5 F2/ 45/ 0F 10 C0 movsd xmm8, xmm8 \n"
" \n"
" 000081FA F3/ 45/ 0F 5A C0 cvtss2sd xmm8, xmm8 \n"
" 000081FF F2/ 45/ 0F 5A C0 cvtsd2ss xmm8, xmm8 \n"
" \n"
" \n"
" ; Source: xmm8, target: xmm9 \n"
" 00008204 F3/ 45/ 0F 10 C8 movss xmm9, xmm8 \n"
" 00008209 F2/ 45/ 0F 10 C8 movsd xmm9, xmm8 \n"
" \n"
" 0000820E F3/ 45/ 0F 5A C8 cvtss2sd xmm9, xmm8 \n"
" 00008213 F2/ 45/ 0F 5A C8 cvtsd2ss xmm9, xmm8 \n"
" \n"
" \n"
" ; Source: xmm8, target: xmm10 \n"
" 00008218 F3/ 45/ 0F 10 D0 movss xmm10, xmm8 \n"
" 0000821D F2/ 45/ 0F 10 D0 movsd xmm10, xmm8 \n"
" \n"
" 00008222 F3/ 45/ 0F 5A D0 cvtss2sd xmm10, xmm8 \n"
" 00008227 F2/ 45/ 0F 5A D0 cvtsd2ss xmm10, xmm8 \n"
" \n"
" \n"
" ; Source: xmm8, target: xmm11 \n"
" 0000822C F3/ 45/ 0F 10 D8 movss xmm11, xmm8 \n"
" 00008231 F2/ 45/ 0F 10 D8 movsd xmm11, xmm8 \n"
" \n"
" 00008236 F3/ 45/ 0F 5A D8 cvtss2sd xmm11, xmm8 \n"
" 0000823B F2/ 45/ 0F 5A D8 cvtsd2ss xmm11, xmm8 \n"
" \n"
" \n"
" ; Source: xmm8, target: xmm12 \n"
" 00008240 F3/ 45/ 0F 10 E0 movss xmm12, xmm8 \n"
" 00008245 F2/ 45/ 0F 10 E0 movsd xmm12, xmm8 \n"
" \n"
" 0000824A F3/ 45/ 0F 5A E0 cvtss2sd xmm12, xmm8 \n"
" 0000824F F2/ 45/ 0F 5A E0 cvtsd2ss xmm12, xmm8 \n"
" \n"
" \n"
" ; Source: xmm8, target: xmm13 \n"
" 00008254 F3/ 45/ 0F 10 E8 movss xmm13, xmm8 \n"
" 00008259 F2/ 45/ 0F 10 E8 movsd xmm13, xmm8 \n"
" \n"
" 0000825E F3/ 45/ 0F 5A E8 cvtss2sd xmm13, xmm8 \n"
" 00008263 F2/ 45/ 0F 5A E8 cvtsd2ss xmm13, xmm8 \n"
" \n"
" \n"
" ; Source: xmm8, target: xmm14 \n"
" 00008268 F3/ 45/ 0F 10 F0 movss xmm14, xmm8 \n"
" 0000826D F2/ 45/ 0F 10 F0 movsd xmm14, xmm8 \n"
" \n"
" 00008272 F3/ 45/ 0F 5A F0 cvtss2sd xmm14, xmm8 \n"
" 00008277 F2/ 45/ 0F 5A F0 cvtsd2ss xmm14, xmm8 \n"
" \n"
" \n"
" ; Source: xmm8, target: xmm15 \n"
" 0000827C F3/ 45/ 0F 10 F8 movss xmm15, xmm8 \n"
" 00008281 F2/ 45/ 0F 10 F8 movsd xmm15, xmm8 \n"
" \n"
" 00008286 F3/ 45/ 0F 5A F8 cvtss2sd xmm15, xmm8 \n"
" 0000828B F2/ 45/ 0F 5A F8 cvtsd2ss xmm15, xmm8 \n"
" \n"
" \n"
" ; Source: xmm9, target: xmm0 \n"
" 00008290 F3/ 41/ 0F 10 C1 movss xmm0, xmm9 \n"
" 00008295 F2/ 41/ 0F 10 C1 movsd xmm0, xmm9 \n"
" \n"
" 0000829A F3/ 41/ 0F 5A C1 cvtss2sd xmm0, xmm9 \n"
" 0000829F F2/ 41/ 0F 5A C1 cvtsd2ss xmm0, xmm9 \n"
" \n"
" \n"
" ; Source: xmm9, target: xmm1 \n"
" 000082A4 F3/ 41/ 0F 10 C9 movss xmm1, xmm9 \n"
" 000082A9 F2/ 41/ 0F 10 C9 movsd xmm1, xmm9 \n"
" \n"
" 000082AE F3/ 41/ 0F 5A C9 cvtss2sd xmm1, xmm9 \n"
" 000082B3 F2/ 41/ 0F 5A C9 cvtsd2ss xmm1, xmm9 \n"
" \n"
" \n"
" ; Source: xmm9, target: xmm2 \n"
" 000082B8 F3/ 41/ 0F 10 D1 movss xmm2, xmm9 \n"
" 000082BD F2/ 41/ 0F 10 D1 movsd xmm2, xmm9 \n"
" \n"
" 000082C2 F3/ 41/ 0F 5A D1 cvtss2sd xmm2, xmm9 \n"
" 000082C7 F2/ 41/ 0F 5A D1 cvtsd2ss xmm2, xmm9 \n"
" \n"
" \n"
" ; Source: xmm9, target: xmm3 \n"
" 000082CC F3/ 41/ 0F 10 D9 movss xmm3, xmm9 \n"
" 000082D1 F2/ 41/ 0F 10 D9 movsd xmm3, xmm9 \n"
" \n"
" 000082D6 F3/ 41/ 0F 5A D9 cvtss2sd xmm3, xmm9 \n"
" 000082DB F2/ 41/ 0F 5A D9 cvtsd2ss xmm3, xmm9 \n"
" \n"
" \n"
" ; Source: xmm9, target: xmm4 \n"
" 000082E0 F3/ 41/ 0F 10 E1 movss xmm4, xmm9 \n"
" 000082E5 F2/ 41/ 0F 10 E1 movsd xmm4, xmm9 \n"
" \n"
" 000082EA F3/ 41/ 0F 5A E1 cvtss2sd xmm4, xmm9 \n"
" 000082EF F2/ 41/ 0F 5A E1 cvtsd2ss xmm4, xmm9 \n"
" \n"
" \n"
" ; Source: xmm9, target: xmm5 \n"
" 000082F4 F3/ 41/ 0F 10 E9 movss xmm5, xmm9 \n"
" 000082F9 F2/ 41/ 0F 10 E9 movsd xmm5, xmm9 \n"
" \n"
" 000082FE F3/ 41/ 0F 5A E9 cvtss2sd xmm5, xmm9 \n"
" 00008303 F2/ 41/ 0F 5A E9 cvtsd2ss xmm5, xmm9 \n"
" \n"
" \n"
" ; Source: xmm9, target: xmm6 \n"
" 00008308 F3/ 41/ 0F 10 F1 movss xmm6, xmm9 \n"
" 0000830D F2/ 41/ 0F 10 F1 movsd xmm6, xmm9 \n"
" \n"
" 00008312 F3/ 41/ 0F 5A F1 cvtss2sd xmm6, xmm9 \n"
" 00008317 F2/ 41/ 0F 5A F1 cvtsd2ss xmm6, xmm9 \n"
" \n"
" \n"
" ; Source: xmm9, target: xmm7 \n"
" 0000831C F3/ 41/ 0F 10 F9 movss xmm7, xmm9 \n"
" 00008321 F2/ 41/ 0F 10 F9 movsd xmm7, xmm9 \n"
" \n"
" 00008326 F3/ 41/ 0F 5A F9 cvtss2sd xmm7, xmm9 \n"
" 0000832B F2/ 41/ 0F 5A F9 cvtsd2ss xmm7, xmm9 \n"
" \n"
" \n"
" ; Source: xmm9, target: xmm8 \n"
" 00008330 F3/ 45/ 0F 10 C1 movss xmm8, xmm9 \n"
" 00008335 F2/ 45/ 0F 10 C1 movsd xmm8, xmm9 \n"
" \n"
" 0000833A F3/ 45/ 0F 5A C1 cvtss2sd xmm8, xmm9 \n"
" 0000833F F2/ 45/ 0F 5A C1 cvtsd2ss xmm8, xmm9 \n"
" \n"
" \n"
" ; Source: xmm9, target: xmm9 \n"
" 00008344 F3/ 45/ 0F 10 C9 movss xmm9, xmm9 \n"
" 00008349 F2/ 45/ 0F 10 C9 movsd xmm9, xmm9 \n"
" \n"
" 0000834E F3/ 45/ 0F 5A C9 cvtss2sd xmm9, xmm9 \n"
" 00008353 F2/ 45/ 0F 5A C9 cvtsd2ss xmm9, xmm9 \n"
" \n"
" \n"
" ; Source: xmm9, target: xmm10 \n"
" 00008358 F3/ 45/ 0F 10 D1 movss xmm10, xmm9 \n"
" 0000835D F2/ 45/ 0F 10 D1 movsd xmm10, xmm9 \n"
" \n"
" 00008362 F3/ 45/ 0F 5A D1 cvtss2sd xmm10, xmm9 \n"
" 00008367 F2/ 45/ 0F 5A D1 cvtsd2ss xmm10, xmm9 \n"
" \n"
" \n"
" ; Source: xmm9, target: xmm11 \n"
" 0000836C F3/ 45/ 0F 10 D9 movss xmm11, xmm9 \n"
" 00008371 F2/ 45/ 0F 10 D9 movsd xmm11, xmm9 \n"
" \n"
" 00008376 F3/ 45/ 0F 5A D9 cvtss2sd xmm11, xmm9 \n"
" 0000837B F2/ 45/ 0F 5A D9 cvtsd2ss xmm11, xmm9 \n"
" \n"
" \n"
" ; Source: xmm9, target: xmm12 \n"
" 00008380 F3/ 45/ 0F 10 E1 movss xmm12, xmm9 \n"
" 00008385 F2/ 45/ 0F 10 E1 movsd xmm12, xmm9 \n"
" \n"
" 0000838A F3/ 45/ 0F 5A E1 cvtss2sd xmm12, xmm9 \n"
" 0000838F F2/ 45/ 0F 5A E1 cvtsd2ss xmm12, xmm9 \n"
" \n"
" \n"
" ; Source: xmm9, target: xmm13 \n"
" 00008394 F3/ 45/ 0F 10 E9 movss xmm13, xmm9 \n"
" 00008399 F2/ 45/ 0F 10 E9 movsd xmm13, xmm9 \n"
" \n"
" 0000839E F3/ 45/ 0F 5A E9 cvtss2sd xmm13, xmm9 \n"
" 000083A3 F2/ 45/ 0F 5A E9 cvtsd2ss xmm13, xmm9 \n"
" \n"
" \n"
" ; Source: xmm9, target: xmm14 \n"
" 000083A8 F3/ 45/ 0F 10 F1 movss xmm14, xmm9 \n"
" 000083AD F2/ 45/ 0F 10 F1 movsd xmm14, xmm9 \n"
" \n"
" 000083B2 F3/ 45/ 0F 5A F1 cvtss2sd xmm14, xmm9 \n"
" 000083B7 F2/ 45/ 0F 5A F1 cvtsd2ss xmm14, xmm9 \n"
" \n"
" \n"
" ; Source: xmm9, target: xmm15 \n"
" 000083BC F3/ 45/ 0F 10 F9 movss xmm15, xmm9 \n"
" 000083C1 F2/ 45/ 0F 10 F9 movsd xmm15, xmm9 \n"
" \n"
" 000083C6 F3/ 45/ 0F 5A F9 cvtss2sd xmm15, xmm9 \n"
" 000083CB F2/ 45/ 0F 5A F9 cvtsd2ss xmm15, xmm9 \n"
" \n"
" \n"
" ; Source: xmm10, target: xmm0 \n"
" 000083D0 F3/ 41/ 0F 10 C2 movss xmm0, xmm10 \n"
" 000083D5 F2/ 41/ 0F 10 C2 movsd xmm0, xmm10 \n"
" \n"
" 000083DA F3/ 41/ 0F 5A C2 cvtss2sd xmm0, xmm10 \n"
" 000083DF F2/ 41/ 0F 5A C2 cvtsd2ss xmm0, xmm10 \n"
" \n"
" \n"
" ; Source: xmm10, target: xmm1 \n"
" 000083E4 F3/ 41/ 0F 10 CA movss xmm1, xmm10 \n"
" 000083E9 F2/ 41/ 0F 10 CA movsd xmm1, xmm10 \n"
" \n"
" 000083EE F3/ 41/ 0F 5A CA cvtss2sd xmm1, xmm10 \n"
" 000083F3 F2/ 41/ 0F 5A CA cvtsd2ss xmm1, xmm10 \n"
" \n"
" \n"
" ; Source: xmm10, target: xmm2 \n"
" 000083F8 F3/ 41/ 0F 10 D2 movss xmm2, xmm10 \n"
" 000083FD F2/ 41/ 0F 10 D2 movsd xmm2, xmm10 \n"
" \n"
" 00008402 F3/ 41/ 0F 5A D2 cvtss2sd xmm2, xmm10 \n"
" 00008407 F2/ 41/ 0F 5A D2 cvtsd2ss xmm2, xmm10 \n"
" \n"
" \n"
" ; Source: xmm10, target: xmm3 \n"
" 0000840C F3/ 41/ 0F 10 DA movss xmm3, xmm10 \n"
" 00008411 F2/ 41/ 0F 10 DA movsd xmm3, xmm10 \n"
" \n"
" 00008416 F3/ 41/ 0F 5A DA cvtss2sd xmm3, xmm10 \n"
" 0000841B F2/ 41/ 0F 5A DA cvtsd2ss xmm3, xmm10 \n"
" \n"
" \n"
" ; Source: xmm10, target: xmm4 \n"
" 00008420 F3/ 41/ 0F 10 E2 movss xmm4, xmm10 \n"
" 00008425 F2/ 41/ 0F 10 E2 movsd xmm4, xmm10 \n"
" \n"
" 0000842A F3/ 41/ 0F 5A E2 cvtss2sd xmm4, xmm10 \n"
" 0000842F F2/ 41/ 0F 5A E2 cvtsd2ss xmm4, xmm10 \n"
" \n"
" \n"
" ; Source: xmm10, target: xmm5 \n"
" 00008434 F3/ 41/ 0F 10 EA movss xmm5, xmm10 \n"
" 00008439 F2/ 41/ 0F 10 EA movsd xmm5, xmm10 \n"
" \n"
" 0000843E F3/ 41/ 0F 5A EA cvtss2sd xmm5, xmm10 \n"
" 00008443 F2/ 41/ 0F 5A EA cvtsd2ss xmm5, xmm10 \n"
" \n"
" \n"
" ; Source: xmm10, target: xmm6 \n"
" 00008448 F3/ 41/ 0F 10 F2 movss xmm6, xmm10 \n"
" 0000844D F2/ 41/ 0F 10 F2 movsd xmm6, xmm10 \n"
" \n"
" 00008452 F3/ 41/ 0F 5A F2 cvtss2sd xmm6, xmm10 \n"
" 00008457 F2/ 41/ 0F 5A F2 cvtsd2ss xmm6, xmm10 \n"
" \n"
" \n"
" ; Source: xmm10, target: xmm7 \n"
" 0000845C F3/ 41/ 0F 10 FA movss xmm7, xmm10 \n"
" 00008461 F2/ 41/ 0F 10 FA movsd xmm7, xmm10 \n"
" \n"
" 00008466 F3/ 41/ 0F 5A FA cvtss2sd xmm7, xmm10 \n"
" 0000846B F2/ 41/ 0F 5A FA cvtsd2ss xmm7, xmm10 \n"
" \n"
" \n"
" ; Source: xmm10, target: xmm8 \n"
" 00008470 F3/ 45/ 0F 10 C2 movss xmm8, xmm10 \n"
" 00008475 F2/ 45/ 0F 10 C2 movsd xmm8, xmm10 \n"
" \n"
" 0000847A F3/ 45/ 0F 5A C2 cvtss2sd xmm8, xmm10 \n"
" 0000847F F2/ 45/ 0F 5A C2 cvtsd2ss xmm8, xmm10 \n"
" \n"
" \n"
" ; Source: xmm10, target: xmm9 \n"
" 00008484 F3/ 45/ 0F 10 CA movss xmm9, xmm10 \n"
" 00008489 F2/ 45/ 0F 10 CA movsd xmm9, xmm10 \n"
" \n"
" 0000848E F3/ 45/ 0F 5A CA cvtss2sd xmm9, xmm10 \n"
" 00008493 F2/ 45/ 0F 5A CA cvtsd2ss xmm9, xmm10 \n"
" \n"
" \n"
" ; Source: xmm10, target: xmm10 \n"
" 00008498 F3/ 45/ 0F 10 D2 movss xmm10, xmm10 \n"
" 0000849D F2/ 45/ 0F 10 D2 movsd xmm10, xmm10 \n"
" \n"
" 000084A2 F3/ 45/ 0F 5A D2 cvtss2sd xmm10, xmm10 \n"
" 000084A7 F2/ 45/ 0F 5A D2 cvtsd2ss xmm10, xmm10 \n"
" \n"
" \n"
" ; Source: xmm10, target: xmm11 \n"
" 000084AC F3/ 45/ 0F 10 DA movss xmm11, xmm10 \n"
" 000084B1 F2/ 45/ 0F 10 DA movsd xmm11, xmm10 \n"
" \n"
" 000084B6 F3/ 45/ 0F 5A DA cvtss2sd xmm11, xmm10 \n"
" 000084BB F2/ 45/ 0F 5A DA cvtsd2ss xmm11, xmm10 \n"
" \n"
" \n"
" ; Source: xmm10, target: xmm12 \n"
" 000084C0 F3/ 45/ 0F 10 E2 movss xmm12, xmm10 \n"
" 000084C5 F2/ 45/ 0F 10 E2 movsd xmm12, xmm10 \n"
" \n"
" 000084CA F3/ 45/ 0F 5A E2 cvtss2sd xmm12, xmm10 \n"
" 000084CF F2/ 45/ 0F 5A E2 cvtsd2ss xmm12, xmm10 \n"
" \n"
" \n"
" ; Source: xmm10, target: xmm13 \n"
" 000084D4 F3/ 45/ 0F 10 EA movss xmm13, xmm10 \n"
" 000084D9 F2/ 45/ 0F 10 EA movsd xmm13, xmm10 \n"
" \n"
" 000084DE F3/ 45/ 0F 5A EA cvtss2sd xmm13, xmm10 \n"
" 000084E3 F2/ 45/ 0F 5A EA cvtsd2ss xmm13, xmm10 \n"
" \n"
" \n"
" ; Source: xmm10, target: xmm14 \n"
" 000084E8 F3/ 45/ 0F 10 F2 movss xmm14, xmm10 \n"
" 000084ED F2/ 45/ 0F 10 F2 movsd xmm14, xmm10 \n"
" \n"
" 000084F2 F3/ 45/ 0F 5A F2 cvtss2sd xmm14, xmm10 \n"
" 000084F7 F2/ 45/ 0F 5A F2 cvtsd2ss xmm14, xmm10 \n"
" \n"
" \n"
" ; Source: xmm10, target: xmm15 \n"
" 000084FC F3/ 45/ 0F 10 FA movss xmm15, xmm10 \n"
" 00008501 F2/ 45/ 0F 10 FA movsd xmm15, xmm10 \n"
" \n"
" 00008506 F3/ 45/ 0F 5A FA cvtss2sd xmm15, xmm10 \n"
" 0000850B F2/ 45/ 0F 5A FA cvtsd2ss xmm15, xmm10 \n"
" \n"
" \n"
" ; Source: xmm11, target: xmm0 \n"
" 00008510 F3/ 41/ 0F 10 C3 movss xmm0, xmm11 \n"
" 00008515 F2/ 41/ 0F 10 C3 movsd xmm0, xmm11 \n"
" \n"
" 0000851A F3/ 41/ 0F 5A C3 cvtss2sd xmm0, xmm11 \n"
" 0000851F F2/ 41/ 0F 5A C3 cvtsd2ss xmm0, xmm11 \n"
" \n"
" \n"
" ; Source: xmm11, target: xmm1 \n"
" 00008524 F3/ 41/ 0F 10 CB movss xmm1, xmm11 \n"
" 00008529 F2/ 41/ 0F 10 CB movsd xmm1, xmm11 \n"
" \n"
" 0000852E F3/ 41/ 0F 5A CB cvtss2sd xmm1, xmm11 \n"
" 00008533 F2/ 41/ 0F 5A CB cvtsd2ss xmm1, xmm11 \n"
" \n"
" \n"
" ; Source: xmm11, target: xmm2 \n"
" 00008538 F3/ 41/ 0F 10 D3 movss xmm2, xmm11 \n"
" 0000853D F2/ 41/ 0F 10 D3 movsd xmm2, xmm11 \n"
" \n";
ml64Output +=
" 00008542 F3/ 41/ 0F 5A D3 cvtss2sd xmm2, xmm11 \n"
" 00008547 F2/ 41/ 0F 5A D3 cvtsd2ss xmm2, xmm11 \n"
" \n"
" \n"
" ; Source: xmm11, target: xmm3 \n"
" 0000854C F3/ 41/ 0F 10 DB movss xmm3, xmm11 \n"
" 00008551 F2/ 41/ 0F 10 DB movsd xmm3, xmm11 \n"
" \n"
" 00008556 F3/ 41/ 0F 5A DB cvtss2sd xmm3, xmm11 \n"
" 0000855B F2/ 41/ 0F 5A DB cvtsd2ss xmm3, xmm11 \n"
" \n"
" \n"
" ; Source: xmm11, target: xmm4 \n"
" 00008560 F3/ 41/ 0F 10 E3 movss xmm4, xmm11 \n"
" 00008565 F2/ 41/ 0F 10 E3 movsd xmm4, xmm11 \n"
" \n"
" 0000856A F3/ 41/ 0F 5A E3 cvtss2sd xmm4, xmm11 \n"
" 0000856F F2/ 41/ 0F 5A E3 cvtsd2ss xmm4, xmm11 \n"
" \n"
" \n"
" ; Source: xmm11, target: xmm5 \n"
" 00008574 F3/ 41/ 0F 10 EB movss xmm5, xmm11 \n"
" 00008579 F2/ 41/ 0F 10 EB movsd xmm5, xmm11 \n"
" \n"
" 0000857E F3/ 41/ 0F 5A EB cvtss2sd xmm5, xmm11 \n"
" 00008583 F2/ 41/ 0F 5A EB cvtsd2ss xmm5, xmm11 \n"
" \n"
" \n"
" ; Source: xmm11, target: xmm6 \n"
" 00008588 F3/ 41/ 0F 10 F3 movss xmm6, xmm11 \n"
" 0000858D F2/ 41/ 0F 10 F3 movsd xmm6, xmm11 \n"
" \n"
" 00008592 F3/ 41/ 0F 5A F3 cvtss2sd xmm6, xmm11 \n"
" 00008597 F2/ 41/ 0F 5A F3 cvtsd2ss xmm6, xmm11 \n"
" \n"
" \n"
" ; Source: xmm11, target: xmm7 \n"
" 0000859C F3/ 41/ 0F 10 FB movss xmm7, xmm11 \n"
" 000085A1 F2/ 41/ 0F 10 FB movsd xmm7, xmm11 \n"
" \n"
" 000085A6 F3/ 41/ 0F 5A FB cvtss2sd xmm7, xmm11 \n"
" 000085AB F2/ 41/ 0F 5A FB cvtsd2ss xmm7, xmm11 \n"
" \n"
" \n"
" ; Source: xmm11, target: xmm8 \n"
" 000085B0 F3/ 45/ 0F 10 C3 movss xmm8, xmm11 \n"
" 000085B5 F2/ 45/ 0F 10 C3 movsd xmm8, xmm11 \n"
" \n"
" 000085BA F3/ 45/ 0F 5A C3 cvtss2sd xmm8, xmm11 \n"
" 000085BF F2/ 45/ 0F 5A C3 cvtsd2ss xmm8, xmm11 \n"
" \n"
" \n"
" ; Source: xmm11, target: xmm9 \n"
" 000085C4 F3/ 45/ 0F 10 CB movss xmm9, xmm11 \n"
" 000085C9 F2/ 45/ 0F 10 CB movsd xmm9, xmm11 \n"
" \n"
" 000085CE F3/ 45/ 0F 5A CB cvtss2sd xmm9, xmm11 \n"
" 000085D3 F2/ 45/ 0F 5A CB cvtsd2ss xmm9, xmm11 \n"
" \n"
" \n"
" ; Source: xmm11, target: xmm10 \n"
" 000085D8 F3/ 45/ 0F 10 D3 movss xmm10, xmm11 \n"
" 000085DD F2/ 45/ 0F 10 D3 movsd xmm10, xmm11 \n"
" \n"
" 000085E2 F3/ 45/ 0F 5A D3 cvtss2sd xmm10, xmm11 \n"
" 000085E7 F2/ 45/ 0F 5A D3 cvtsd2ss xmm10, xmm11 \n"
" \n"
" \n"
" ; Source: xmm11, target: xmm11 \n"
" 000085EC F3/ 45/ 0F 10 DB movss xmm11, xmm11 \n"
" 000085F1 F2/ 45/ 0F 10 DB movsd xmm11, xmm11 \n"
" \n"
" 000085F6 F3/ 45/ 0F 5A DB cvtss2sd xmm11, xmm11 \n"
" 000085FB F2/ 45/ 0F 5A DB cvtsd2ss xmm11, xmm11 \n"
" \n"
" \n"
" ; Source: xmm11, target: xmm12 \n"
" 00008600 F3/ 45/ 0F 10 E3 movss xmm12, xmm11 \n"
" 00008605 F2/ 45/ 0F 10 E3 movsd xmm12, xmm11 \n"
" \n"
" 0000860A F3/ 45/ 0F 5A E3 cvtss2sd xmm12, xmm11 \n"
" 0000860F F2/ 45/ 0F 5A E3 cvtsd2ss xmm12, xmm11 \n"
" \n"
" \n"
" ; Source: xmm11, target: xmm13 \n"
" 00008614 F3/ 45/ 0F 10 EB movss xmm13, xmm11 \n"
" 00008619 F2/ 45/ 0F 10 EB movsd xmm13, xmm11 \n"
" \n"
" 0000861E F3/ 45/ 0F 5A EB cvtss2sd xmm13, xmm11 \n"
" 00008623 F2/ 45/ 0F 5A EB cvtsd2ss xmm13, xmm11 \n"
" \n"
" \n"
" ; Source: xmm11, target: xmm14 \n"
" 00008628 F3/ 45/ 0F 10 F3 movss xmm14, xmm11 \n"
" 0000862D F2/ 45/ 0F 10 F3 movsd xmm14, xmm11 \n"
" \n"
" 00008632 F3/ 45/ 0F 5A F3 cvtss2sd xmm14, xmm11 \n"
" 00008637 F2/ 45/ 0F 5A F3 cvtsd2ss xmm14, xmm11 \n"
" \n"
" \n"
" ; Source: xmm11, target: xmm15 \n"
" 0000863C F3/ 45/ 0F 10 FB movss xmm15, xmm11 \n"
" 00008641 F2/ 45/ 0F 10 FB movsd xmm15, xmm11 \n"
" \n"
" 00008646 F3/ 45/ 0F 5A FB cvtss2sd xmm15, xmm11 \n"
" 0000864B F2/ 45/ 0F 5A FB cvtsd2ss xmm15, xmm11 \n"
" \n"
" \n"
" ; Source: xmm12, target: xmm0 \n"
" 00008650 F3/ 41/ 0F 10 C4 movss xmm0, xmm12 \n"
" 00008655 F2/ 41/ 0F 10 C4 movsd xmm0, xmm12 \n"
" \n"
" 0000865A F3/ 41/ 0F 5A C4 cvtss2sd xmm0, xmm12 \n"
" 0000865F F2/ 41/ 0F 5A C4 cvtsd2ss xmm0, xmm12 \n"
" \n"
" \n"
" ; Source: xmm12, target: xmm1 \n"
" 00008664 F3/ 41/ 0F 10 CC movss xmm1, xmm12 \n"
" 00008669 F2/ 41/ 0F 10 CC movsd xmm1, xmm12 \n"
" \n"
" 0000866E F3/ 41/ 0F 5A CC cvtss2sd xmm1, xmm12 \n"
" 00008673 F2/ 41/ 0F 5A CC cvtsd2ss xmm1, xmm12 \n"
" \n"
" \n"
" ; Source: xmm12, target: xmm2 \n"
" 00008678 F3/ 41/ 0F 10 D4 movss xmm2, xmm12 \n"
" 0000867D F2/ 41/ 0F 10 D4 movsd xmm2, xmm12 \n"
" \n"
" 00008682 F3/ 41/ 0F 5A D4 cvtss2sd xmm2, xmm12 \n"
" 00008687 F2/ 41/ 0F 5A D4 cvtsd2ss xmm2, xmm12 \n"
" \n"
" \n"
" ; Source: xmm12, target: xmm3 \n"
" 0000868C F3/ 41/ 0F 10 DC movss xmm3, xmm12 \n"
" 00008691 F2/ 41/ 0F 10 DC movsd xmm3, xmm12 \n"
" \n"
" 00008696 F3/ 41/ 0F 5A DC cvtss2sd xmm3, xmm12 \n"
" 0000869B F2/ 41/ 0F 5A DC cvtsd2ss xmm3, xmm12 \n"
" \n"
" \n"
" ; Source: xmm12, target: xmm4 \n"
" 000086A0 F3/ 41/ 0F 10 E4 movss xmm4, xmm12 \n"
" 000086A5 F2/ 41/ 0F 10 E4 movsd xmm4, xmm12 \n"
" \n"
" 000086AA F3/ 41/ 0F 5A E4 cvtss2sd xmm4, xmm12 \n"
" 000086AF F2/ 41/ 0F 5A E4 cvtsd2ss xmm4, xmm12 \n"
" \n"
" \n"
" ; Source: xmm12, target: xmm5 \n"
" 000086B4 F3/ 41/ 0F 10 EC movss xmm5, xmm12 \n"
" 000086B9 F2/ 41/ 0F 10 EC movsd xmm5, xmm12 \n"
" \n"
" 000086BE F3/ 41/ 0F 5A EC cvtss2sd xmm5, xmm12 \n"
" 000086C3 F2/ 41/ 0F 5A EC cvtsd2ss xmm5, xmm12 \n"
" \n"
" \n"
" ; Source: xmm12, target: xmm6 \n"
" 000086C8 F3/ 41/ 0F 10 F4 movss xmm6, xmm12 \n"
" 000086CD F2/ 41/ 0F 10 F4 movsd xmm6, xmm12 \n"
" \n"
" 000086D2 F3/ 41/ 0F 5A F4 cvtss2sd xmm6, xmm12 \n"
" 000086D7 F2/ 41/ 0F 5A F4 cvtsd2ss xmm6, xmm12 \n"
" \n"
" \n"
" ; Source: xmm12, target: xmm7 \n"
" 000086DC F3/ 41/ 0F 10 FC movss xmm7, xmm12 \n"
" 000086E1 F2/ 41/ 0F 10 FC movsd xmm7, xmm12 \n"
" \n"
" 000086E6 F3/ 41/ 0F 5A FC cvtss2sd xmm7, xmm12 \n"
" 000086EB F2/ 41/ 0F 5A FC cvtsd2ss xmm7, xmm12 \n"
" \n"
" \n"
" ; Source: xmm12, target: xmm8 \n"
" 000086F0 F3/ 45/ 0F 10 C4 movss xmm8, xmm12 \n"
" 000086F5 F2/ 45/ 0F 10 C4 movsd xmm8, xmm12 \n"
" \n"
" 000086FA F3/ 45/ 0F 5A C4 cvtss2sd xmm8, xmm12 \n"
" 000086FF F2/ 45/ 0F 5A C4 cvtsd2ss xmm8, xmm12 \n"
" \n"
" \n"
" ; Source: xmm12, target: xmm9 \n"
" 00008704 F3/ 45/ 0F 10 CC movss xmm9, xmm12 \n"
" 00008709 F2/ 45/ 0F 10 CC movsd xmm9, xmm12 \n"
" \n"
" 0000870E F3/ 45/ 0F 5A CC cvtss2sd xmm9, xmm12 \n"
" 00008713 F2/ 45/ 0F 5A CC cvtsd2ss xmm9, xmm12 \n"
" \n"
" \n"
" ; Source: xmm12, target: xmm10 \n"
" 00008718 F3/ 45/ 0F 10 D4 movss xmm10, xmm12 \n"
" 0000871D F2/ 45/ 0F 10 D4 movsd xmm10, xmm12 \n"
" \n"
" 00008722 F3/ 45/ 0F 5A D4 cvtss2sd xmm10, xmm12 \n"
" 00008727 F2/ 45/ 0F 5A D4 cvtsd2ss xmm10, xmm12 \n"
" \n"
" \n"
" ; Source: xmm12, target: xmm11 \n"
" 0000872C F3/ 45/ 0F 10 DC movss xmm11, xmm12 \n"
" 00008731 F2/ 45/ 0F 10 DC movsd xmm11, xmm12 \n"
" \n"
" 00008736 F3/ 45/ 0F 5A DC cvtss2sd xmm11, xmm12 \n"
" 0000873B F2/ 45/ 0F 5A DC cvtsd2ss xmm11, xmm12 \n"
" \n"
" \n"
" ; Source: xmm12, target: xmm12 \n"
" 00008740 F3/ 45/ 0F 10 E4 movss xmm12, xmm12 \n"
" 00008745 F2/ 45/ 0F 10 E4 movsd xmm12, xmm12 \n"
" \n"
" 0000874A F3/ 45/ 0F 5A E4 cvtss2sd xmm12, xmm12 \n"
" 0000874F F2/ 45/ 0F 5A E4 cvtsd2ss xmm12, xmm12 \n"
" \n"
" \n"
" ; Source: xmm12, target: xmm13 \n"
" 00008754 F3/ 45/ 0F 10 EC movss xmm13, xmm12 \n"
" 00008759 F2/ 45/ 0F 10 EC movsd xmm13, xmm12 \n"
" \n"
" 0000875E F3/ 45/ 0F 5A EC cvtss2sd xmm13, xmm12 \n"
" 00008763 F2/ 45/ 0F 5A EC cvtsd2ss xmm13, xmm12 \n"
" \n"
" \n"
" ; Source: xmm12, target: xmm14 \n"
" 00008768 F3/ 45/ 0F 10 F4 movss xmm14, xmm12 \n"
" 0000876D F2/ 45/ 0F 10 F4 movsd xmm14, xmm12 \n"
" \n"
" 00008772 F3/ 45/ 0F 5A F4 cvtss2sd xmm14, xmm12 \n"
" 00008777 F2/ 45/ 0F 5A F4 cvtsd2ss xmm14, xmm12 \n"
" \n"
" \n"
" ; Source: xmm12, target: xmm15 \n"
" 0000877C F3/ 45/ 0F 10 FC movss xmm15, xmm12 \n"
" 00008781 F2/ 45/ 0F 10 FC movsd xmm15, xmm12 \n"
" \n"
" 00008786 F3/ 45/ 0F 5A FC cvtss2sd xmm15, xmm12 \n"
" 0000878B F2/ 45/ 0F 5A FC cvtsd2ss xmm15, xmm12 \n"
" \n"
" \n"
" ; Source: xmm13, target: xmm0 \n"
" 00008790 F3/ 41/ 0F 10 C5 movss xmm0, xmm13 \n"
" 00008795 F2/ 41/ 0F 10 C5 movsd xmm0, xmm13 \n"
" \n"
" 0000879A F3/ 41/ 0F 5A C5 cvtss2sd xmm0, xmm13 \n"
" 0000879F F2/ 41/ 0F 5A C5 cvtsd2ss xmm0, xmm13 \n"
" \n"
" \n"
" ; Source: xmm13, target: xmm1 \n"
" 000087A4 F3/ 41/ 0F 10 CD movss xmm1, xmm13 \n"
" 000087A9 F2/ 41/ 0F 10 CD movsd xmm1, xmm13 \n"
" \n"
" 000087AE F3/ 41/ 0F 5A CD cvtss2sd xmm1, xmm13 \n"
" 000087B3 F2/ 41/ 0F 5A CD cvtsd2ss xmm1, xmm13 \n"
" \n"
" \n"
" ; Source: xmm13, target: xmm2 \n"
" 000087B8 F3/ 41/ 0F 10 D5 movss xmm2, xmm13 \n"
" 000087BD F2/ 41/ 0F 10 D5 movsd xmm2, xmm13 \n"
" \n"
" 000087C2 F3/ 41/ 0F 5A D5 cvtss2sd xmm2, xmm13 \n"
" 000087C7 F2/ 41/ 0F 5A D5 cvtsd2ss xmm2, xmm13 \n"
" \n"
" \n"
" ; Source: xmm13, target: xmm3 \n"
" 000087CC F3/ 41/ 0F 10 DD movss xmm3, xmm13 \n"
" 000087D1 F2/ 41/ 0F 10 DD movsd xmm3, xmm13 \n"
" \n"
" 000087D6 F3/ 41/ 0F 5A DD cvtss2sd xmm3, xmm13 \n"
" 000087DB F2/ 41/ 0F 5A DD cvtsd2ss xmm3, xmm13 \n"
" \n"
" \n"
" ; Source: xmm13, target: xmm4 \n"
" 000087E0 F3/ 41/ 0F 10 E5 movss xmm4, xmm13 \n"
" 000087E5 F2/ 41/ 0F 10 E5 movsd xmm4, xmm13 \n"
" \n"
" 000087EA F3/ 41/ 0F 5A E5 cvtss2sd xmm4, xmm13 \n"
" 000087EF F2/ 41/ 0F 5A E5 cvtsd2ss xmm4, xmm13 \n"
" \n"
" \n"
" ; Source: xmm13, target: xmm5 \n"
" 000087F4 F3/ 41/ 0F 10 ED movss xmm5, xmm13 \n"
" 000087F9 F2/ 41/ 0F 10 ED movsd xmm5, xmm13 \n"
" \n"
" 000087FE F3/ 41/ 0F 5A ED cvtss2sd xmm5, xmm13 \n"
" 00008803 F2/ 41/ 0F 5A ED cvtsd2ss xmm5, xmm13 \n"
" \n"
" \n"
" ; Source: xmm13, target: xmm6 \n"
" 00008808 F3/ 41/ 0F 10 F5 movss xmm6, xmm13 \n"
" 0000880D F2/ 41/ 0F 10 F5 movsd xmm6, xmm13 \n"
" \n"
" 00008812 F3/ 41/ 0F 5A F5 cvtss2sd xmm6, xmm13 \n"
" 00008817 F2/ 41/ 0F 5A F5 cvtsd2ss xmm6, xmm13 \n"
" \n"
" \n"
" ; Source: xmm13, target: xmm7 \n"
" 0000881C F3/ 41/ 0F 10 FD movss xmm7, xmm13 \n"
" 00008821 F2/ 41/ 0F 10 FD movsd xmm7, xmm13 \n"
" \n"
" 00008826 F3/ 41/ 0F 5A FD cvtss2sd xmm7, xmm13 \n"
" 0000882B F2/ 41/ 0F 5A FD cvtsd2ss xmm7, xmm13 \n"
" \n"
" \n"
" ; Source: xmm13, target: xmm8 \n"
" 00008830 F3/ 45/ 0F 10 C5 movss xmm8, xmm13 \n"
" 00008835 F2/ 45/ 0F 10 C5 movsd xmm8, xmm13 \n"
" \n"
" 0000883A F3/ 45/ 0F 5A C5 cvtss2sd xmm8, xmm13 \n"
" 0000883F F2/ 45/ 0F 5A C5 cvtsd2ss xmm8, xmm13 \n"
" \n"
" \n"
" ; Source: xmm13, target: xmm9 \n"
" 00008844 F3/ 45/ 0F 10 CD movss xmm9, xmm13 \n"
" 00008849 F2/ 45/ 0F 10 CD movsd xmm9, xmm13 \n"
" \n"
" 0000884E F3/ 45/ 0F 5A CD cvtss2sd xmm9, xmm13 \n"
" 00008853 F2/ 45/ 0F 5A CD cvtsd2ss xmm9, xmm13 \n"
" \n"
" \n"
" ; Source: xmm13, target: xmm10 \n"
" 00008858 F3/ 45/ 0F 10 D5 movss xmm10, xmm13 \n"
" 0000885D F2/ 45/ 0F 10 D5 movsd xmm10, xmm13 \n"
" \n"
" 00008862 F3/ 45/ 0F 5A D5 cvtss2sd xmm10, xmm13 \n"
" 00008867 F2/ 45/ 0F 5A D5 cvtsd2ss xmm10, xmm13 \n"
" \n"
" \n"
" ; Source: xmm13, target: xmm11 \n"
" 0000886C F3/ 45/ 0F 10 DD movss xmm11, xmm13 \n"
" 00008871 F2/ 45/ 0F 10 DD movsd xmm11, xmm13 \n"
" \n"
" 00008876 F3/ 45/ 0F 5A DD cvtss2sd xmm11, xmm13 \n"
" 0000887B F2/ 45/ 0F 5A DD cvtsd2ss xmm11, xmm13 \n"
" \n"
" \n"
" ; Source: xmm13, target: xmm12 \n"
" 00008880 F3/ 45/ 0F 10 E5 movss xmm12, xmm13 \n"
" 00008885 F2/ 45/ 0F 10 E5 movsd xmm12, xmm13 \n"
" \n"
" 0000888A F3/ 45/ 0F 5A E5 cvtss2sd xmm12, xmm13 \n"
" 0000888F F2/ 45/ 0F 5A E5 cvtsd2ss xmm12, xmm13 \n"
" \n"
" \n"
" ; Source: xmm13, target: xmm13 \n"
" 00008894 F3/ 45/ 0F 10 ED movss xmm13, xmm13 \n"
" 00008899 F2/ 45/ 0F 10 ED movsd xmm13, xmm13 \n"
" \n"
" 0000889E F3/ 45/ 0F 5A ED cvtss2sd xmm13, xmm13 \n"
" 000088A3 F2/ 45/ 0F 5A ED cvtsd2ss xmm13, xmm13 \n"
" \n"
" \n"
" ; Source: xmm13, target: xmm14 \n"
" 000088A8 F3/ 45/ 0F 10 F5 movss xmm14, xmm13 \n"
" 000088AD F2/ 45/ 0F 10 F5 movsd xmm14, xmm13 \n"
" \n"
" 000088B2 F3/ 45/ 0F 5A F5 cvtss2sd xmm14, xmm13 \n"
" 000088B7 F2/ 45/ 0F 5A F5 cvtsd2ss xmm14, xmm13 \n"
" \n"
" \n"
" ; Source: xmm13, target: xmm15 \n"
" 000088BC F3/ 45/ 0F 10 FD movss xmm15, xmm13 \n"
" 000088C1 F2/ 45/ 0F 10 FD movsd xmm15, xmm13 \n"
" \n"
" 000088C6 F3/ 45/ 0F 5A FD cvtss2sd xmm15, xmm13 \n"
" 000088CB F2/ 45/ 0F 5A FD cvtsd2ss xmm15, xmm13 \n"
" \n"
" \n"
" ; Source: xmm14, target: xmm0 \n"
" 000088D0 F3/ 41/ 0F 10 C6 movss xmm0, xmm14 \n"
" 000088D5 F2/ 41/ 0F 10 C6 movsd xmm0, xmm14 \n"
" \n"
" 000088DA F3/ 41/ 0F 5A C6 cvtss2sd xmm0, xmm14 \n"
" 000088DF F2/ 41/ 0F 5A C6 cvtsd2ss xmm0, xmm14 \n"
" \n"
" \n"
" ; Source: xmm14, target: xmm1 \n"
" 000088E4 F3/ 41/ 0F 10 CE movss xmm1, xmm14 \n"
" 000088E9 F2/ 41/ 0F 10 CE movsd xmm1, xmm14 \n"
" \n"
" 000088EE F3/ 41/ 0F 5A CE cvtss2sd xmm1, xmm14 \n"
" 000088F3 F2/ 41/ 0F 5A CE cvtsd2ss xmm1, xmm14 \n"
" \n"
" \n"
" ; Source: xmm14, target: xmm2 \n"
" 000088F8 F3/ 41/ 0F 10 D6 movss xmm2, xmm14 \n"
" 000088FD F2/ 41/ 0F 10 D6 movsd xmm2, xmm14 \n"
" \n"
" 00008902 F3/ 41/ 0F 5A D6 cvtss2sd xmm2, xmm14 \n"
" 00008907 F2/ 41/ 0F 5A D6 cvtsd2ss xmm2, xmm14 \n"
" \n"
" \n"
" ; Source: xmm14, target: xmm3 \n"
" 0000890C F3/ 41/ 0F 10 DE movss xmm3, xmm14 \n"
" 00008911 F2/ 41/ 0F 10 DE movsd xmm3, xmm14 \n"
" \n"
" 00008916 F3/ 41/ 0F 5A DE cvtss2sd xmm3, xmm14 \n"
" 0000891B F2/ 41/ 0F 5A DE cvtsd2ss xmm3, xmm14 \n"
" \n"
" \n"
" ; Source: xmm14, target: xmm4 \n"
" 00008920 F3/ 41/ 0F 10 E6 movss xmm4, xmm14 \n"
" 00008925 F2/ 41/ 0F 10 E6 movsd xmm4, xmm14 \n"
" \n"
" 0000892A F3/ 41/ 0F 5A E6 cvtss2sd xmm4, xmm14 \n"
" 0000892F F2/ 41/ 0F 5A E6 cvtsd2ss xmm4, xmm14 \n"
" \n"
" \n"
" ; Source: xmm14, target: xmm5 \n"
" 00008934 F3/ 41/ 0F 10 EE movss xmm5, xmm14 \n"
" 00008939 F2/ 41/ 0F 10 EE movsd xmm5, xmm14 \n"
" \n"
" 0000893E F3/ 41/ 0F 5A EE cvtss2sd xmm5, xmm14 \n"
" 00008943 F2/ 41/ 0F 5A EE cvtsd2ss xmm5, xmm14 \n"
" \n"
" \n"
" ; Source: xmm14, target: xmm6 \n"
" 00008948 F3/ 41/ 0F 10 F6 movss xmm6, xmm14 \n"
" 0000894D F2/ 41/ 0F 10 F6 movsd xmm6, xmm14 \n"
" \n"
" 00008952 F3/ 41/ 0F 5A F6 cvtss2sd xmm6, xmm14 \n"
" 00008957 F2/ 41/ 0F 5A F6 cvtsd2ss xmm6, xmm14 \n"
" \n"
" \n"
" ; Source: xmm14, target: xmm7 \n"
" 0000895C F3/ 41/ 0F 10 FE movss xmm7, xmm14 \n"
" 00008961 F2/ 41/ 0F 10 FE movsd xmm7, xmm14 \n"
" \n"
" 00008966 F3/ 41/ 0F 5A FE cvtss2sd xmm7, xmm14 \n"
" 0000896B F2/ 41/ 0F 5A FE cvtsd2ss xmm7, xmm14 \n"
" \n"
" \n"
" ; Source: xmm14, target: xmm8 \n"
" 00008970 F3/ 45/ 0F 10 C6movss xmm8, xmm14 \n"
" 00008975 F2/ 45/ 0F 10 C6 movsd xmm8, xmm14 \n"
" \n"
" 0000897A F3/ 45/ 0F 5A C6 cvtss2sd xmm8, xmm14 \n"
" 0000897F F2/ 45/ 0F 5A C6 cvtsd2ss xmm8, xmm14 \n"
" \n"
" \n"
" ; Source: xmm14, target: xmm9 \n"
" 00008984 F3/ 45/ 0F 10 CE movss xmm9, xmm14 \n"
" 00008989 F2/ 45/ 0F 10 CE movsd xmm9, xmm14 \n"
" \n"
" 0000898E F3/ 45/ 0F 5A CE cvtss2sd xmm9, xmm14 \n"
" 00008993 F2/ 45/ 0F 5A CE cvtsd2ss xmm9, xmm14 \n"
" \n"
" \n"
" ; Source: xmm14, target: xmm10 \n"
" 00008998 F3/ 45/ 0F 10 D6 movss xmm10, xmm14 \n"
" 0000899D F2/ 45/ 0F 10 D6 movsd xmm10, xmm14 \n"
" \n"
" 000089A2 F3/ 45/ 0F 5A D6 cvtss2sd xmm10, xmm14 \n"
" 000089A7 F2/ 45/ 0F 5A D6 cvtsd2ss xmm10, xmm14 \n"
" \n"
" \n"
" ; Source: xmm14, target: xmm11 \n"
" 000089AC F3/ 45/ 0F 10 DE movss xmm11, xmm14 \n"
" 000089B1 F2/ 45/ 0F 10 DE movsd xmm11, xmm14 \n"
" \n"
" 000089B6 F3/ 45/ 0F 5A DE cvtss2sd xmm11, xmm14 \n"
" 000089BB F2/ 45/ 0F 5A DE cvtsd2ss xmm11, xmm14 \n"
" \n"
" \n"
" ; Source: xmm14, target: xmm12 \n"
" 000089C0 F3/ 45/ 0F 10 E6 movss xmm12, xmm14 \n"
" 000089C5 F2/ 45/ 0F 10 E6 movsd xmm12, xmm14 \n"
" \n"
" 000089CA F3/ 45/ 0F 5A E6 cvtss2sd xmm12, xmm14 \n"
" 000089CF F2/ 45/ 0F 5A E6 cvtsd2ss xmm12, xmm14 \n"
" \n"
" \n"
" ; Source: xmm14, target: xmm13 \n"
" 000089D4 F3/ 45/ 0F 10 EE movss xmm13, xmm14 \n"
" 000089D9 F2/ 45/ 0F 10 EE movsd xmm13, xmm14 \n"
" \n"
" 000089DE F3/ 45/ 0F 5A EE cvtss2sd xmm13, xmm14 \n"
" 000089E3 F2/ 45/ 0F 5A EE cvtsd2ss xmm13, xmm14 \n"
" \n"
" \n"
" ; Source: xmm14, target: xmm14 \n"
" 000089E8 F3/ 45/ 0F 10 F6 movss xmm14, xmm14 \n"
" 000089ED F2/ 45/ 0F 10 F6 movsd xmm14, xmm14 \n"
" \n"
" 000089F2 F3/ 45/ 0F 5A F6 cvtss2sd xmm14, xmm14 \n"
" 000089F7 F2/ 45/ 0F 5A F6 cvtsd2ss xmm14, xmm14 \n"
" \n"
" \n"
" ; Source: xmm14, target: xmm15 \n"
" 000089FC F3/ 45/ 0F 10 FE movss xmm15, xmm14 \n"
" 00008A01 F2/ 45/ 0F 10 FE movsd xmm15, xmm14 \n"
" \n"
" 00008A06 F3/ 45/ 0F 5A FE cvtss2sd xmm15, xmm14 \n"
" 00008A0B F2/ 45/ 0F 5A FE cvtsd2ss xmm15, xmm14 \n"
" \n"
" \n"
" ; Source: xmm15, target: xmm0 \n"
" 00008A10 F3/ 41/ 0F 10 C7 movss xmm0, xmm15 \n"
" 00008A15 F2/ 41/ 0F 10 C7 movsd xmm0, xmm15 \n"
" \n"
" 00008A1A F3/ 41/ 0F 5A C7 cvtss2sd xmm0, xmm15 \n"
" 00008A1F F2/ 41/ 0F 5A C7 cvtsd2ss xmm0, xmm15 \n"
" \n"
" \n"
" ; Source: xmm15, target: xmm1 \n"
" 00008A24 F3/ 41/ 0F 10 CF movss xmm1, xmm15 \n"
" 00008A29 F2/ 41/ 0F 10 CF movsd xmm1, xmm15 \n"
" \n"
" 00008A2E F3/ 41/ 0F 5A CF cvtss2sd xmm1, xmm15 \n"
" 00008A33 F2/ 41/ 0F 5A CF cvtsd2ss xmm1, xmm15 \n"
" \n"
" \n"
" ; Source: xmm15, target: xmm2 \n"
" 00008A38 F3/ 41/ 0F 10 D7 movss xmm2, xmm15 \n"
" 00008A3D F2/ 41/ 0F 10 D7 movsd xmm2, xmm15 \n"
" \n"
" 00008A42 F3/ 41/ 0F 5A D7 cvtss2sd xmm2, xmm15 \n"
" 00008A47 F2/ 41/ 0F 5A D7 cvtsd2ss xmm2, xmm15 \n"
" \n"
" \n"
" ; Source: xmm15, target: xmm3 \n"
" 00008A4C F3/ 41/ 0F 10 DF movss xmm3, xmm15 \n"
" 00008A51 F2/ 41/ 0F 10 DF movsd xmm3, xmm15 \n"
" \n"
" 00008A56 F3/ 41/ 0F 5A DF cvtss2sd xmm3, xmm15 \n"
" 00008A5B F2/ 41/ 0F 5A DF cvtsd2ss xmm3, xmm15 \n"
" \n"
" \n"
" ; Source: xmm15, target: xmm4 \n"
" 00008A60 F3/ 41/ 0F 10 E7 movss xmm4, xmm15 \n"
" 00008A65 F2/ 41/ 0F 10 E7 movsd xmm4, xmm15 \n"
" \n"
" 00008A6A F3/ 41/ 0F 5A E7 cvtss2sd xmm4, xmm15 \n"
" 00008A6F F2/ 41/ 0F 5A E7 cvtsd2ss xmm4, xmm15 \n"
" \n"
" \n"
" ; Source: xmm15, target: xmm5 \n"
" 00008A74 F3/ 41/ 0F 10 EF movss xmm5, xmm15 \n"
" 00008A79 F2/ 41/ 0F 10 EF movsd xmm5, xmm15 \n"
" \n"
" 00008A7E F3/ 41/ 0F 5A EF cvtss2sd xmm5, xmm15 \n"
" 00008A83 F2/ 41/ 0F 5A EF cvtsd2ss xmm5, xmm15 \n"
" \n"
" \n"
" ; Source: xmm15, target: xmm6 \n"
" 00008A88 F3/ 41/ 0F 10 F7 movss xmm6, xmm15 \n"
" 00008A8D F2/ 41/ 0F 10 F7 movsd xmm6, xmm15 \n"
" \n"
" 00008A92 F3/ 41/ 0F 5A F7 cvtss2sd xmm6, xmm15 \n"
" 00008A97 F2/ 41/ 0F 5A F7 cvtsd2ss xmm6, xmm15 \n"
" \n"
" \n"
" ; Source: xmm15, target: xmm7 \n"
" 00008A9C F3/ 41/ 0F 10 FF movss xmm7, xmm15 \n";
ml64Output +=
" 00008AA1 F2/ 41/ 0F 10 FF movsd xmm7, xmm15 \n"
" \n"
" 00008AA6 F3/ 41/ 0F 5A FF cvtss2sd xmm7, xmm15 \n"
" 00008AAB F2/ 41/ 0F 5A FF cvtsd2ss xmm7, xmm15 \n"
" \n"
" \n"
" ; Source: xmm15, target: xmm8 \n"
" 00008AB0 F3/ 45/ 0F 10 C7 movss xmm8, xmm15 \n"
" 00008AB5 F2/ 45/ 0F 10 C7 movsd xmm8, xmm15 \n"
" \n"
" 00008ABA F3/ 45/ 0F 5A C7 cvtss2sd xmm8, xmm15 \n"
" 00008ABF F2/ 45/ 0F 5A C7 cvtsd2ss xmm8, xmm15 \n"
" \n"
" \n"
" ; Source: xmm15, target: xmm9 \n"
" 00008AC4 F3/ 45/ 0F 10 CF movss xmm9, xmm15 \n"
" 00008AC9 F2/ 45/ 0F 10 CF movsd xmm9, xmm15 \n"
" \n"
" 00008ACE F3/ 45/ 0F 5A CF cvtss2sd xmm9, xmm15 \n"
" 00008AD3 F2/ 45/ 0F 5A CF cvtsd2ss xmm9, xmm15 \n"
" \n"
" \n"
" ; Source: xmm15, target: xmm10 \n"
" 00008AD8 F3/ 45/ 0F 10 D7 movss xmm10, xmm15 \n"
" 00008ADD F2/ 45/ 0F 10 D7 movsd xmm10, xmm15 \n"
" \n"
" 00008AE2 F3/ 45/ 0F 5A D7 cvtss2sd xmm10, xmm15 \n"
" 00008AE7 F2/ 45/ 0F 5A D7 cvtsd2ss xmm10, xmm15 \n"
" \n"
" \n"
" ; Source: xmm15, target: xmm11 \n"
" 00008AEC F3/ 45/ 0F 10 DF movss xmm11, xmm15 \n"
" 00008AF1 F2/ 45/ 0F 10 DF movsd xmm11, xmm15 \n"
" \n"
" 00008AF6 F3/ 45/ 0F 5A DF cvtss2sd xmm11, xmm15 \n"
" 00008AFB F2/ 45/ 0F 5A DF cvtsd2ss xmm11, xmm15 \n"
" \n"
" \n"
" ; Source: xmm15, target: xmm12 \n"
" 00008B00 F3/ 45/ 0F 10 E7 movss xmm12, xmm15 \n"
" 00008B05 F2/ 45/ 0F 10 E7 movsd xmm12, xmm15 \n"
" \n"
" 00008B0A F3/ 45/ 0F 5A E7 cvtss2sd xmm12, xmm15 \n"
" 00008B0F F2/ 45/ 0F 5A E7 cvtsd2ss xmm12, xmm15 \n"
" \n"
" \n"
" ; Source: xmm15, target: xmm13 \n"
" 00008B14 F3/ 45/ 0F 10 EF movss xmm13, xmm15 \n"
" 00008B19 F2/ 45/ 0F 10 EF movsd xmm13, xmm15 \n"
" \n"
" 00008B1E F3/ 45/ 0F 5A EF cvtss2sd xmm13, xmm15 \n"
" 00008B23 F2/ 45/ 0F 5A EF cvtsd2ss xmm13, xmm15 \n"
" \n"
" \n"
" ; Source: xmm15, target: xmm14 \n"
" 00008B28 F3/ 45/ 0F 10 F7 movss xmm14, xmm15 \n"
" 00008B2D F2/ 45/ 0F 10 F7 movsd xmm14, xmm15 \n"
" \n"
" 00008B32 F3/ 45/ 0F 5A F7 cvtss2sd xmm14, xmm15 \n"
" 00008B37 F2/ 45/ 0F 5A F7 cvtsd2ss xmm14, xmm15 \n"
" \n"
" \n"
" ; Source: xmm15, target: xmm15 \n"
" 00008B3C F3/ 45/ 0F 10 FF movss xmm15, xmm15 \n"
" 00008B41 F2/ 45/ 0F 10 FF movsd xmm15, xmm15 \n"
" \n"
" 00008B46 F3/ 45/ 0F 5A FF cvtss2sd xmm15, xmm15 \n"
" 00008B4B F2/ 45/ 0F 5A FF cvtsd2ss xmm15, xmm15 \n"
" \n"
" \n"
" ; Float <-> Int \n"
" \n"
" ; Between: xmm0 and rax \n"
" 00008B50 F3/ 0F 11 40 movss dword ptr [rax - 4], xmm0 \n"
" FC \n"
" 00008B55 F2/ 0F 11 40 movsd qword ptr [rax + 4], xmm0 \n"
" 04 \n"
" \n"
" 00008B5A F3/ 0F 10 40 movss xmm0, dword ptr [rax - 4] \n"
" FC \n"
" 00008B5F F2/ 0F 10 40 movsd xmm0, qword ptr [rax + 4] \n"
" 04 \n"
" 00008B64 F3/ 48/ 0F 2A 40 cvtsi2ss xmm0, qword ptr [rax - 4] \n"
" FC \n"
" 00008B6A F2/ 0F 2A 40 cvtsi2sd xmm0, dword ptr [rax + 4] \n"
" 04 \n"
" \n"
" 00008B6F F3/ 0F 2C C0 cvttss2si eax, xmm0 \n"
" 00008B73 F2/ 0F 2C C0 cvttsd2si eax, xmm0 \n"
" \n"
" 00008B77 F3/ 0F 2A C0 cvtsi2ss xmm0, eax \n"
" 00008B7B F2/ 0F 2A C0 cvtsi2sd xmm0, eax \n"
" \n"
" 00008B7F F3/ 48/ 0F 2C C0 cvttss2si rax, xmm0 \n"
" 00008B84 F2/ 48/ 0F 2C C0 cvttsd2si rax, xmm0 \n"
" \n"
" 00008B89 F3/ 48/ 0F 2A C0 cvtsi2ss xmm0, rax \n"
" 00008B8E F2/ 48/ 0F 2A C0 cvtsi2sd xmm0, rax \n"
" \n"
" \n"
" ; Between: xmm0 and rcx \n"
" 00008B93 F3/ 0F 11 41 movss dword ptr [rcx - 4], xmm0 \n"
" FC \n"
" 00008B98 F2/ 0F 11 41 movsd qword ptr [rcx + 4], xmm0 \n"
" 04 \n"
" \n"
" 00008B9D F3/ 0F 10 41 movss xmm0, dword ptr [rcx - 4] \n"
" FC \n"
" 00008BA2 F2/ 0F 10 41 movsd xmm0, qword ptr [rcx + 4] \n"
" 04 \n"
" 00008BA7 F3/ 48/ 0F 2A 41 cvtsi2ss xmm0, qword ptr [rcx - 4] \n"
" FC \n"
" 00008BAD F2/ 0F 2A 41 cvtsi2sd xmm0, dword ptr [rcx + 4] \n"
" 04 \n"
" \n"
" 00008BB2 F3/ 0F 2C C8 cvttss2si ecx, xmm0 \n"
" 00008BB6 F2/ 0F 2C C8 cvttsd2si ecx, xmm0 \n"
" \n"
" 00008BBA F3/ 0F 2A C1 cvtsi2ss xmm0, ecx \n"
" 00008BBE F2/ 0F 2A C1 cvtsi2sd xmm0, ecx \n"
" \n"
" 00008BC2 F3/ 48/ 0F 2C C8 cvttss2si rcx, xmm0 \n"
" 00008BC7 F2/ 48/ 0F 2C C8 cvttsd2si rcx, xmm0 \n"
" \n"
" 00008BCC F3/ 48/ 0F 2A C1 cvtsi2ss xmm0, rcx \n"
" 00008BD1 F2/ 48/ 0F 2A C1 cvtsi2sd xmm0, rcx \n"
" \n"
" \n"
" ; Between: xmm0 and rdx \n"
" 00008BD6 F3/ 0F 11 42 movss dword ptr [rdx - 4], xmm0 \n"
" FC \n"
" 00008BDB F2/ 0F 11 42 movsd qword ptr [rdx + 4], xmm0 \n"
" 04 \n"
" \n"
" 00008BE0 F3/ 0F 10 42 movss xmm0, dword ptr [rdx - 4] \n"
" FC \n"
" 00008BE5 F2/ 0F 10 42 movsd xmm0, qword ptr [rdx + 4] \n"
" 04 \n"
" 00008BEA F3/ 48/ 0F 2A 42 cvtsi2ss xmm0, qword ptr [rdx - 4] \n"
" FC \n"
" 00008BF0 F2/ 0F 2A 42 cvtsi2sd xmm0, dword ptr [rdx + 4] \n"
" 04 \n"
" \n"
" 00008BF5 F3/ 0F 2C D0 cvttss2si edx, xmm0 \n"
" 00008BF9 F2/ 0F 2C D0 cvttsd2si edx, xmm0 \n"
" \n"
" 00008BFD F3/ 0F 2A C2 cvtsi2ss xmm0, edx \n"
" 00008C01 F2/ 0F 2A C2 cvtsi2sd xmm0, edx \n"
" \n"
" 00008C05 F3/ 48/ 0F 2C D0 cvttss2si rdx, xmm0 \n"
" 00008C0A F2/ 48/ 0F 2C D0 cvttsd2si rdx, xmm0 \n"
" \n"
" 00008C0F F3/ 48/ 0F 2A C2 cvtsi2ss xmm0, rdx \n"
" 00008C14 F2/ 48/ 0F 2A C2 cvtsi2sd xmm0, rdx \n"
" \n"
" \n"
" ; Between: xmm0 and rbx \n"
" 00008C19 F3/ 0F 11 43 movss dword ptr [rbx - 4], xmm0 \n"
" FC \n"
" 00008C1E F2/ 0F 11 43 movsd qword ptr [rbx + 4], xmm0 \n"
" 04 \n"
" \n"
" 00008C23 F3/ 0F 10 43 movss xmm0, dword ptr [rbx - 4] \n"
" FC \n"
" 00008C28 F2/ 0F 10 43 movsd xmm0, qword ptr [rbx + 4] \n"
" 04 \n"
" 00008C2D F3/ 48/ 0F 2A 43 cvtsi2ss xmm0, qword ptr [rbx - 4] \n"
" FC \n"
" 00008C33 F2/ 0F 2A 43 cvtsi2sd xmm0, dword ptr [rbx + 4] \n"
" 04 \n"
" \n"
" 00008C38 F3/ 0F 2C D8 cvttss2si ebx, xmm0 \n"
" 00008C3C F2/ 0F 2C D8 cvttsd2si ebx, xmm0 \n"
" \n"
" 00008C40 F3/ 0F 2A C3 cvtsi2ss xmm0, ebx \n"
" 00008C44 F2/ 0F 2A C3 cvtsi2sd xmm0, ebx \n"
" \n"
" 00008C48 F3/ 48/ 0F 2C D8 cvttss2si rbx, xmm0 \n"
" 00008C4D F2/ 48/ 0F 2C D8 cvttsd2si rbx, xmm0 \n"
" \n"
" 00008C52 F3/ 48/ 0F 2A C3 cvtsi2ss xmm0, rbx \n"
" 00008C57 F2/ 48/ 0F 2A C3 cvtsi2sd xmm0, rbx \n"
" \n"
" \n"
" ; Between: xmm0 and rsp \n"
" 00008C5C F3/ 0F 11 44 24 movss dword ptr [rsp - 4], xmm0 \n"
" FC \n"
" 00008C62 F2/ 0F 11 44 24 movsd qword ptr [rsp + 4], xmm0 \n"
" 04 \n"
" \n"
" 00008C68 F3/ 0F 10 44 24 movss xmm0, dword ptr [rsp - 4] \n"
" FC \n"
" 00008C6E F2/ 0F 10 44 24 movsd xmm0, qword ptr [rsp + 4] \n"
" 04 \n"
" 00008C74 F3/ 48/ 0F 2A 44 cvtsi2ss xmm0, qword ptr [rsp - 4] \n"
" 24 FC \n"
" 00008C7B F2/ 0F 2A 44 24 cvtsi2sd xmm0, dword ptr [rsp + 4] \n"
" 04 \n"
" \n"
" 00008C81 F3/ 0F 2C E0 cvttss2si esp, xmm0 \n"
" 00008C85 F2/ 0F 2C E0 cvttsd2si esp, xmm0 \n"
" \n"
" 00008C89 F3/ 0F 2A C4 cvtsi2ss xmm0, esp \n"
" 00008C8D F2/ 0F 2A C4 cvtsi2sd xmm0, esp \n"
" \n"
" 00008C91 F3/ 48/ 0F 2C E0 cvttss2si rsp, xmm0 \n"
" 00008C96 F2/ 48/ 0F 2C E0 cvttsd2si rsp, xmm0 \n"
" \n"
" 00008C9B F3/ 48/ 0F 2A C4 cvtsi2ss xmm0, rsp \n"
" 00008CA0 F2/ 48/ 0F 2A C4 cvtsi2sd xmm0, rsp \n"
" \n"
" \n"
" ; Between: xmm0 and rbp \n"
" 00008CA5 F3/ 0F 11 45 movss dword ptr [rbp - 4], xmm0 \n"
" FC \n"
" 00008CAA F2/ 0F 11 45 movsd qword ptr [rbp + 4], xmm0 \n"
" 04 \n"
" \n"
" 00008CAF F3/ 0F 10 45 movss xmm0, dword ptr [rbp - 4] \n"
" FC \n"
" 00008CB4 F2/ 0F 10 45 movsd xmm0, qword ptr [rbp + 4] \n"
" 04 \n"
" 00008CB9 F3/ 48/ 0F 2A 45 cvtsi2ss xmm0, qword ptr [rbp - 4] \n"
" FC \n"
" 00008CBF F2/ 0F 2A 45 cvtsi2sd xmm0, dword ptr [rbp + 4] \n"
" 04 \n"
" \n"
" 00008CC4 F3/ 0F 2C E8 cvttss2si ebp, xmm0 \n"
" 00008CC8 F2/ 0F 2C E8 cvttsd2si ebp, xmm0 \n"
" \n"
" 00008CCC F3/ 0F 2A C5 cvtsi2ss xmm0, ebp \n"
" 00008CD0 F2/ 0F 2A C5 cvtsi2sd xmm0, ebp \n"
" \n"
" 00008CD4 F3/ 48/ 0F 2C E8 cvttss2si rbp, xmm0 \n"
" 00008CD9 F2/ 48/ 0F 2C E8 cvttsd2si rbp, xmm0 \n"
" \n"
" 00008CDE F3/ 48/ 0F 2A C5 cvtsi2ss xmm0, rbp \n"
" 00008CE3 F2/ 48/ 0F 2A C5 cvtsi2sd xmm0, rbp \n"
" \n"
" \n"
" ; Between: xmm0 and rsi \n"
" 00008CE8 F3/ 0F 11 46 movss dword ptr [rsi - 4], xmm0 \n"
" FC \n"
" 00008CED F2/ 0F 11 46 movsd qword ptr [rsi + 4], xmm0 \n"
" 04 \n"
" \n"
" 00008CF2 F3/ 0F 10 46 movss xmm0, dword ptr [rsi - 4] \n"
" FC \n"
" 00008CF7 F2/ 0F 10 46 movsd xmm0, qword ptr [rsi + 4] \n"
" 04 \n"
" 00008CFC F3/ 48/ 0F 2A 46 cvtsi2ss xmm0, qword ptr [rsi - 4] \n"
" FC \n"
" 00008D02 F2/ 0F 2A 46 cvtsi2sd xmm0, dword ptr [rsi + 4] \n"
" 04 \n"
" \n"
" 00008D07 F3/ 0F 2C F0 cvttss2si esi, xmm0 \n"
" 00008D0B F2/ 0F 2C F0 cvttsd2si esi, xmm0 \n"
" \n"
" 00008D0F F3/ 0F 2A C6 cvtsi2ss xmm0, esi \n"
" 00008D13 F2/ 0F 2A C6 cvtsi2sd xmm0, esi \n"
" \n"
" 00008D17 F3/ 48/ 0F 2C F0 cvttss2si rsi, xmm0 \n"
" 00008D1C F2/ 48/ 0F 2C F0 cvttsd2si rsi, xmm0 \n"
" \n"
" 00008D21 F3/ 48/ 0F 2A C6 cvtsi2ss xmm0, rsi \n"
" 00008D26 F2/ 48/ 0F 2A C6 cvtsi2sd xmm0, rsi \n"
" \n"
" \n"
" ; Between: xmm0 and rdi \n"
" 00008D2B F3/ 0F 11 47 movss dword ptr [rdi - 4], xmm0 \n"
" FC \n"
" 00008D30 F2/ 0F 11 47 movsd qword ptr [rdi + 4], xmm0 \n"
" 04 \n"
" \n"
" 00008D35 F3/ 0F 10 47 movss xmm0, dword ptr [rdi - 4] \n"
" FC \n"
" 00008D3A F2/ 0F 10 47 movsd xmm0, qword ptr [rdi + 4] \n"
" 04 \n"
" 00008D3F F3/ 48/ 0F 2A 47 cvtsi2ss xmm0, qword ptr [rdi - 4] \n"
" FC \n"
" 00008D45 F2/ 0F 2A 47 cvtsi2sd xmm0, dword ptr [rdi + 4] \n"
" 04 \n"
" \n"
" 00008D4A F3/ 0F 2C F8 cvttss2si edi, xmm0 \n"
" 00008D4E F2/ 0F 2C F8 cvttsd2si edi, xmm0 \n"
" \n"
" 00008D52 F3/ 0F 2A C7 cvtsi2ss xmm0, edi \n"
" 00008D56 F2/ 0F 2A C7 cvtsi2sd xmm0, edi \n"
" \n"
" 00008D5A F3/ 48/ 0F 2C F8 cvttss2si rdi, xmm0 \n"
" 00008D5F F2/ 48/ 0F 2C F8 cvttsd2si rdi, xmm0 \n"
" \n"
" 00008D64 F3/ 48/ 0F 2A C7 cvtsi2ss xmm0, rdi \n"
" 00008D69 F2/ 48/ 0F 2A C7 cvtsi2sd xmm0, rdi \n"
" \n"
" \n"
" ; Between: xmm0 and r8 \n"
" 00008D6E F3/ 41/ 0F 11 40 movss dword ptr [r8 - 4], xmm0 \n"
" FC \n"
" 00008D74 F2/ 41/ 0F 11 40 movsd qword ptr [r8 + 4], xmm0 \n"
" 04 \n"
" \n"
" 00008D7A F3/ 41/ 0F 10 40 movss xmm0, dword ptr [r8 - 4] \n"
" FC \n"
" 00008D80 F2/ 41/ 0F 10 40 movsd xmm0, qword ptr [r8 + 4] \n"
" 04 \n"
" 00008D86 F3/ 49/ 0F 2A 40 cvtsi2ss xmm0, qword ptr [r8 - 4] \n"
" FC \n"
" 00008D8C F2/ 41/ 0F 2A 40 cvtsi2sd xmm0, dword ptr [r8 + 4] \n"
" 04 \n"
" \n"
" 00008D92 F3/ 44/ 0F 2C C0 cvttss2si r8d, xmm0 \n"
" 00008D97 F2/ 44/ 0F 2C C0 cvttsd2si r8d, xmm0 \n"
" \n"
" 00008D9C F3/ 41/ 0F 2A C0 cvtsi2ss xmm0, r8d \n"
" 00008DA1 F2/ 41/ 0F 2A C0 cvtsi2sd xmm0, r8d \n"
" \n"
" 00008DA6 F3/ 4C/ 0F 2C C0 cvttss2si r8, xmm0 \n"
" 00008DAB F2/ 4C/ 0F 2C C0 cvttsd2si r8, xmm0 \n"
" \n"
" 00008DB0 F3/ 49/ 0F 2A C0 cvtsi2ss xmm0, r8 \n"
" 00008DB5 F2/ 49/ 0F 2A C0 cvtsi2sd xmm0, r8 \n"
" \n"
" \n"
" ; Between: xmm0 and r9 \n"
" 00008DBA F3/ 41/ 0F 11 41 movss dword ptr [r9 - 4], xmm0 \n"
" FC \n"
" 00008DC0 F2/ 41/ 0F 11 41 movsd qword ptr [r9 + 4], xmm0 \n"
" 04 \n"
" \n"
" 00008DC6 F3/ 41/ 0F 10 41 movss xmm0, dword ptr [r9 - 4] \n"
" FC \n"
" 00008DCC F2/ 41/ 0F 10 41 movsd xmm0, qword ptr [r9 + 4] \n"
" 04 \n"
" 00008DD2 F3/ 49/ 0F 2A 41 cvtsi2ss xmm0, qword ptr [r9 - 4] \n"
" FC \n"
" 00008DD8 F2/ 41/ 0F 2A 41 cvtsi2sd xmm0, dword ptr [r9 + 4] \n"
" 04 \n"
" \n"
" 00008DDE F3/ 44/ 0F 2C C8 cvttss2si r9d, xmm0 \n"
" 00008DE3 F2/ 44/ 0F 2C C8 cvttsd2si r9d, xmm0 \n"
" \n"
" 00008DE8 F3/ 41/ 0F 2A C1 cvtsi2ss xmm0, r9d \n"
" 00008DED F2/ 41/ 0F 2A C1 cvtsi2sd xmm0, r9d \n"
" \n"
" 00008DF2 F3/ 4C/ 0F 2C C8 cvttss2si r9, xmm0 \n"
" 00008DF7 F2/ 4C/ 0F 2C C8 cvttsd2si r9, xmm0 \n"
" \n"
" 00008DFC F3/ 49/ 0F 2A C1 cvtsi2ss xmm0, r9 \n"
" 00008E01 F2/ 49/ 0F 2A C1 cvtsi2sd xmm0, r9 \n"
" \n"
" \n"
" ; Between: xmm0 and r10 \n"
" 00008E06 F3/ 41/ 0F 11 42 movss dword ptr [r10 - 4], xmm0 \n"
" FC \n"
" 00008E0C F2/ 41/ 0F 11 42 movsd qword ptr [r10 + 4], xmm0 \n"
" 04 \n"
" \n"
" 00008E12 F3/ 41/ 0F 10 42 movss xmm0, dword ptr [r10 - 4] \n"
" FC \n"
" 00008E18 F2/ 41/ 0F 10 42 movsd xmm0, qword ptr [r10 + 4] \n"
" 04 \n"
" 00008E1E F3/ 49/ 0F 2A 42 cvtsi2ss xmm0, qword ptr [r10 - 4] \n"
" FC \n"
" 00008E24 F2/ 41/ 0F 2A 42 cvtsi2sd xmm0, dword ptr [r10 + 4] \n"
" 04 \n"
" \n"
" 00008E2A F3/ 44/ 0F 2C D0 cvttss2si r10d, xmm0 \n"
" 00008E2F F2/ 44/ 0F 2C D0 cvttsd2si r10d, xmm0 \n"
" \n"
" 00008E34 F3/ 41/ 0F 2A C2 cvtsi2ss xmm0, r10d \n"
" 00008E39 F2/ 41/ 0F 2A C2 cvtsi2sd xmm0, r10d \n"
" \n"
" 00008E3E F3/ 4C/ 0F 2C D0 cvttss2si r10, xmm0 \n"
" 00008E43 F2/ 4C/ 0F 2C D0 cvttsd2si r10, xmm0 \n"
" \n"
" 00008E48 F3/ 49/ 0F 2A C2 cvtsi2ss xmm0, r10 \n"
" 00008E4D F2/ 49/ 0F 2A C2 cvtsi2sd xmm0, r10 \n"
" \n"
" \n"
" ; Between: xmm0 and r11 \n"
" 00008E52 F3/ 41/ 0F 11 43 movss dword ptr [r11 - 4], xmm0 \n"
" FC \n"
" 00008E58 F2/ 41/ 0F 11 43 movsd qword ptr [r11 + 4], xmm0 \n"
" 04 \n"
" \n"
" 00008E5E F3/ 41/ 0F 10 43 movss xmm0, dword ptr [r11 - 4] \n"
" FC \n"
" 00008E64 F2/ 41/ 0F 10 43 movsd xmm0, qword ptr [r11 + 4] \n"
" 04 \n"
" 00008E6A F3/ 49/ 0F 2A 43 cvtsi2ss xmm0, qword ptr [r11 - 4] \n"
" FC \n"
" 00008E70 F2/ 41/ 0F 2A 43 cvtsi2sd xmm0, dword ptr [r11 + 4] \n"
" 04 \n"
" \n"
" 00008E76 F3/ 44/ 0F 2C D8 cvttss2si r11d, xmm0 \n"
" 00008E7B F2/ 44/ 0F 2C D8 cvttsd2si r11d, xmm0 \n"
" \n"
" 00008E80 F3/ 41/ 0F 2A C3 cvtsi2ss xmm0, r11d \n"
" 00008E85 F2/ 41/ 0F 2A C3 cvtsi2sd xmm0, r11d \n"
" \n"
" 00008E8A F3/ 4C/ 0F 2C D8 cvttss2si r11, xmm0 \n"
" 00008E8F F2/ 4C/ 0F 2C D8 cvttsd2si r11, xmm0 \n"
" \n"
" 00008E94 F3/ 49/ 0F 2A C3 cvtsi2ss xmm0, r11 \n"
" 00008E99 F2/ 49/ 0F 2A C3 cvtsi2sd xmm0, r11 \n"
" \n"
" \n"
" ; Between: xmm0 and r12 \n"
" 00008E9E F3/ 41/ 0F 11 44 movss dword ptr [r12 - 4], xmm0 \n"
" 24 FC \n"
" 00008EA5 F2/ 41/ 0F 11 44 movsd qword ptr [r12 + 4], xmm0 \n"
" 24 04 \n"
" \n"
" 00008EAC F3/ 41/ 0F 10 44 movss xmm0, dword ptr [r12 - 4] \n"
" 24 FC \n"
" 00008EB3 F2/ 41/ 0F 10 44 movsd xmm0, qword ptr [r12 + 4] \n"
" 24 04 \n"
" 00008EBA F3/ 49/ 0F 2A 44 cvtsi2ss xmm0, qword ptr [r12 - 4] \n"
" 24 FC \n"
" 00008EC1 F2/ 41/ 0F 2A 44 cvtsi2sd xmm0, dword ptr [r12 + 4] \n"
" 24 04 \n"
" \n"
" 00008EC8 F3/ 44/ 0F 2C E0 cvttss2si r12d, xmm0 \n"
" 00008ECD F2/ 44/ 0F 2C E0 cvttsd2si r12d, xmm0 \n"
" \n"
" 00008ED2 F3/ 41/ 0F 2A C4 cvtsi2ss xmm0, r12d \n"
" 00008ED7 F2/ 41/ 0F 2A C4 cvtsi2sd xmm0, r12d \n"
" \n"
" 00008EDC F3/ 4C/ 0F 2C E0 cvttss2si r12, xmm0 \n"
" 00008EE1 F2/ 4C/ 0F 2C E0 cvttsd2si r12, xmm0 \n"
" \n"
" 00008EE6 F3/ 49/ 0F 2A C4 cvtsi2ss xmm0, r12 \n"
" 00008EEB F2/ 49/ 0F 2A C4 cvtsi2sd xmm0, r12 \n"
" \n"
" \n"
" ; Between: xmm0 and r13 \n"
" 00008EF0 F3/ 41/ 0F 11 45 movss dword ptr [r13 - 4], xmm0 \n"
" FC \n"
" 00008EF6 F2/ 41/ 0F 11 45 movsd qword ptr [r13 + 4], xmm0 \n"
" 04 \n"
" \n"
" 00008EFC F3/ 41/ 0F 10 45 movss xmm0, dword ptr [r13 - 4] \n"
" FC \n"
" 00008F02 F2/ 41/ 0F 10 45 movsd xmm0, qword ptr [r13 + 4] \n"
" 04 \n"
" 00008F08 F3/ 49/ 0F 2A 45 cvtsi2ss xmm0, qword ptr [r13 - 4] \n"
" FC \n"
" 00008F0E F2/ 41/ 0F 2A 45 cvtsi2sd xmm0, dword ptr [r13 + 4] \n"
" 04 \n"
" \n"
" 00008F14 F3/ 44/ 0F 2C E8 cvttss2si r13d, xmm0 \n"
" 00008F19 F2/ 44/ 0F 2C E8 cvttsd2si r13d, xmm0 \n"
" \n"
" 00008F1E F3/ 41/ 0F 2A C5 cvtsi2ss xmm0, r13d \n"
" 00008F23 F2/ 41/ 0F 2A C5 cvtsi2sd xmm0, r13d \n"
" \n"
" 00008F28 F3/ 4C/ 0F 2C E8 cvttss2si r13, xmm0 \n"
" 00008F2D F2/ 4C/ 0F 2C E8 cvttsd2si r13, xmm0 \n"
" \n"
" 00008F32 F3/ 49/ 0F 2A C5 cvtsi2ss xmm0, r13 \n"
" 00008F37 F2/ 49/ 0F 2A C5 cvtsi2sd xmm0, r13 \n"
" \n"
" \n"
" ; Between: xmm0 and r14 \n"
" 00008F3C F3/ 41/ 0F 11 46 movss dword ptr [r14 - 4], xmm0 \n"
" FC \n"
" 00008F42 F2/ 41/ 0F 11 46 movsd qword ptr [r14 + 4], xmm0 \n"
" 04 \n"
" \n"
" 00008F48 F3/ 41/ 0F 10 46 movss xmm0, dword ptr [r14 - 4] \n"
" FC \n"
" 00008F4E F2/ 41/ 0F 10 46 movsd xmm0, qword ptr [r14 + 4] \n"
" 04 \n"
" 00008F54 F3/ 49/ 0F 2A 46 cvtsi2ss xmm0, qword ptr [r14 - 4] \n"
" FC \n"
" 00008F5A F2/ 41/ 0F 2A 46 cvtsi2sd xmm0, dword ptr [r14 + 4] \n"
" 04 \n"
" \n"
" 00008F60 F3/ 44/ 0F 2C F0 cvttss2si r14d, xmm0 \n"
" 00008F65 F2/ 44/ 0F 2C F0 cvttsd2si r14d, xmm0 \n"
" \n"
" 00008F6A F3/ 41/ 0F 2A C6 cvtsi2ss xmm0, r14d \n"
" 00008F6F F2/ 41/ 0F 2A C6 cvtsi2sd xmm0, r14d \n"
" \n"
" 00008F74 F3/ 4C/ 0F 2C F0 cvttss2si r14, xmm0 \n"
" 00008F79 F2/ 4C/ 0F 2C F0 cvttsd2si r14, xmm0 \n"
" \n"
" 00008F7E F3/ 49/ 0F 2A C6 cvtsi2ss xmm0, r14 \n"
" 00008F83 F2/ 49/ 0F 2A C6 cvtsi2sd xmm0, r14 \n"
" \n"
" \n"
" ; Between: xmm0 and r15 \n"
" 00008F88 F3/ 41/ 0F 11 47 movss dword ptr [r15 - 4], xmm0 \n"
" FC \n"
" 00008F8E F2/ 41/ 0F 11 47 movsd qword ptr [r15 + 4], xmm0 \n"
" 04 \n"
" \n"
" 00008F94 F3/ 41/ 0F 10 47 movss xmm0, dword ptr [r15 - 4] \n"
" FC \n"
" 00008F9A F2/ 41/ 0F 10 47 movsd xmm0, qword ptr [r15 + 4] \n"
" 04 \n"
" 00008FA0 F3/ 49/ 0F 2A 47 cvtsi2ss xmm0, qword ptr [r15 - 4] \n"
" FC \n"
" 00008FA6 F2/ 41/ 0F 2A 47 cvtsi2sd xmm0, dword ptr [r15 + 4] \n"
" 04 \n"
" \n"
" 00008FAC F3/ 44/ 0F 2C F8 cvttss2si r15d, xmm0 \n"
" 00008FB1 F2/ 44/ 0F 2C F8 cvttsd2si r15d, xmm0 \n"
" \n"
" 00008FB6 F3/ 41/ 0F 2A C7 cvtsi2ss xmm0, r15d \n"
" 00008FBB F2/ 41/ 0F 2A C7 cvtsi2sd xmm0, r15d \n"
" \n"
" 00008FC0 F3/ 4C/ 0F 2C F8 cvttss2si r15, xmm0 \n"
" 00008FC5 F2/ 4C/ 0F 2C F8 cvttsd2si r15, xmm0 \n"
" \n"
" 00008FCA F3/ 49/ 0F 2A C7 cvtsi2ss xmm0, r15 \n"
" 00008FCF F2/ 49/ 0F 2A C7 cvtsi2sd xmm0, r15 \n"
" \n"
" \n"
" ; Between: xmm1 and rax \n"
" 00008FD4 F3/ 0F 11 48 movss dword ptr [rax - 4], xmm1 \n"
" FC \n"
" 00008FD9 F2/ 0F 11 48 movsd qword ptr [rax + 4], xmm1 \n"
" 04 \n"
" \n"
" 00008FDE F3/ 0F 10 48 movss xmm1, dword ptr [rax - 4] \n"
" FC \n"
" 00008FE3 F2/ 0F 10 48 movsd xmm1, qword ptr [rax + 4] \n"
" 04 \n"
" 00008FE8 F3/ 48/ 0F 2A 48 cvtsi2ss xmm1, qword ptr [rax - 4] \n"
" FC \n"
" 00008FEE F2/ 0F 2A 48 cvtsi2sd xmm1, dword ptr [rax + 4] \n"
" 04 \n"
" \n"
" 00008FF3 F3/ 0F 2C C1 cvttss2si eax, xmm1 \n"
" 00008FF7 F2/ 0F 2C C1 cvttsd2si eax, xmm1 \n"
" \n"
" 00008FFB F3/ 0F 2A C8 cvtsi2ss xmm1, eax \n"
" 00008FFF F2/ 0F 2A C8 cvtsi2sd xmm1, eax \n"
" \n"
" 00009003 F3/ 48/ 0F 2C C1 cvttss2si rax, xmm1 \n"
" 00009008 F2/ 48/ 0F 2C C1 cvttsd2si rax, xmm1 \n"
" \n"
" 0000900D F3/ 48/ 0F 2A C8 cvtsi2ss xmm1, rax \n"
" 00009012 F2/ 48/ 0F 2A C8 cvtsi2sd xmm1, rax \n"
" \n"
" \n"
" ; Between: xmm1 and rcx \n"
" 00009017 F3/ 0F 11 49 movss dword ptr [rcx - 4], xmm1 \n";
ml64Output +=
" FC \n"
" 0000901C F2/ 0F 11 49 movsd qword ptr [rcx + 4], xmm1 \n"
" 04 \n"
" \n"
" 00009021 F3/ 0F 10 49 movss xmm1, dword ptr [rcx - 4] \n"
" FC \n"
" 00009026 F2/ 0F 10 49 movsd xmm1, qword ptr [rcx + 4] \n"
" 04 \n"
" 0000902B F3/ 48/ 0F 2A 49 cvtsi2ss xmm1, qword ptr [rcx - 4] \n"
" FC \n"
" 00009031 F2/ 0F 2A 49 cvtsi2sd xmm1, dword ptr [rcx + 4] \n"
" 04 \n"
" \n"
" 00009036 F3/ 0F 2C C9 cvttss2si ecx, xmm1 \n"
" 0000903A F2/ 0F 2C C9 cvttsd2si ecx, xmm1 \n"
" \n"
" 0000903E F3/ 0F 2A C9 cvtsi2ss xmm1, ecx \n"
" 00009042 F2/ 0F 2A C9 cvtsi2sd xmm1, ecx \n"
" \n"
" 00009046 F3/ 48/ 0F 2C C9 cvttss2si rcx, xmm1 \n"
" 0000904B F2/ 48/ 0F 2C C9 cvttsd2si rcx, xmm1 \n"
" \n"
" 00009050 F3/ 48/ 0F 2A C9 cvtsi2ss xmm1, rcx \n"
" 00009055 F2/ 48/ 0F 2A C9 cvtsi2sd xmm1, rcx \n"
" \n"
" \n"
" ; Between: xmm1 and rdx \n"
" 0000905A F3/ 0F 11 4A movss dword ptr [rdx - 4], xmm1 \n"
" FC \n"
" 0000905F F2/ 0F 11 4A movsd qword ptr [rdx + 4], xmm1 \n"
" 04 \n"
" \n"
" 00009064 F3/ 0F 10 4A movss xmm1, dword ptr [rdx - 4] \n"
" FC \n"
" 00009069 F2/ 0F 10 4A movsd xmm1, qword ptr [rdx + 4] \n"
" 04 \n"
" 0000906E F3/ 48/ 0F 2A 4A cvtsi2ss xmm1, qword ptr [rdx - 4] \n"
" FC \n"
" 00009074 F2/ 0F 2A 4A cvtsi2sd xmm1, dword ptr [rdx + 4] \n"
" 04 \n"
" \n"
" 00009079 F3/ 0F 2C D1 cvttss2si edx, xmm1 \n"
" 0000907D F2/ 0F 2C D1 cvttsd2si edx, xmm1 \n"
" \n"
" 00009081 F3/ 0F 2A CA cvtsi2ss xmm1, edx \n"
" 00009085 F2/ 0F 2A CA cvtsi2sd xmm1, edx \n"
" \n"
" 00009089 F3/ 48/ 0F 2C D1 cvttss2si rdx, xmm1 \n"
" 0000908E F2/ 48/ 0F 2C D1 cvttsd2si rdx, xmm1 \n"
" \n"
" 00009093 F3/ 48/ 0F 2A CA cvtsi2ss xmm1, rdx \n"
" 00009098 F2/ 48/ 0F 2A CA cvtsi2sd xmm1, rdx \n"
" \n"
" \n"
" ; Between: xmm1 and rbx \n"
" 0000909D F3/ 0F 11 4B movss dword ptr [rbx - 4], xmm1 \n"
" FC \n"
" 000090A2 F2/ 0F 11 4B movsd qword ptr [rbx + 4], xmm1 \n"
" 04 \n"
" \n"
" 000090A7 F3/ 0F 10 4B movss xmm1, dword ptr [rbx - 4] \n"
" FC \n"
" 000090AC F2/ 0F 10 4B movsd xmm1, qword ptr [rbx + 4] \n"
" 04 \n"
" 000090B1 F3/ 48/ 0F 2A 4B cvtsi2ss xmm1, qword ptr [rbx - 4] \n"
" FC \n"
" 000090B7 F2/ 0F 2A 4B cvtsi2sd xmm1, dword ptr [rbx + 4] \n"
" 04 \n"
" \n"
" 000090BC F3/ 0F 2C D9 cvttss2si ebx, xmm1 \n"
" 000090C0 F2/ 0F 2C D9 cvttsd2si ebx, xmm1 \n"
" \n"
" 000090C4 F3/ 0F 2A CB cvtsi2ss xmm1, ebx \n"
" 000090C8 F2/ 0F 2A CB cvtsi2sd xmm1, ebx \n"
" \n"
" 000090CC F3/ 48/ 0F 2C D9 cvttss2si rbx, xmm1 \n"
" 000090D1 F2/ 48/ 0F 2C D9 cvttsd2si rbx, xmm1 \n"
" \n"
" 000090D6 F3/ 48/ 0F 2A CB cvtsi2ss xmm1, rbx \n"
" 000090DB F2/ 48/ 0F 2A CB cvtsi2sd xmm1, rbx \n"
" \n"
" \n"
" ; Between: xmm1 and rsp \n"
" 000090E0 F3/ 0F 11 4C 24 movss dword ptr [rsp - 4], xmm1 \n"
" FC \n"
" 000090E6 F2/ 0F 11 4C 24 movsd qword ptr [rsp + 4], xmm1 \n"
" 04 \n"
" \n"
" 000090EC F3/ 0F 10 4C 24 movss xmm1, dword ptr [rsp - 4] \n"
" FC \n"
" 000090F2 F2/ 0F 10 4C 24 movsd xmm1, qword ptr [rsp + 4] \n"
" 04 \n"
" 000090F8 F3/ 48/ 0F 2A 4C cvtsi2ss xmm1, qword ptr [rsp - 4] \n"
" 24 FC \n"
" 000090FF F2/ 0F 2A 4C 24 cvtsi2sd xmm1, dword ptr [rsp + 4] \n"
" 04 \n"
" \n"
" 00009105 F3/ 0F 2C E1 cvttss2si esp, xmm1 \n"
" 00009109 F2/ 0F 2C E1 cvttsd2si esp, xmm1 \n"
" \n"
" 0000910D F3/ 0F 2A CC cvtsi2ss xmm1, esp \n"
" 00009111 F2/ 0F 2A CC cvtsi2sd xmm1, esp \n"
" \n"
" 00009115 F3/ 48/ 0F 2C E1 cvttss2si rsp, xmm1 \n"
" 0000911A F2/ 48/ 0F 2C E1 cvttsd2si rsp, xmm1 \n"
" \n"
" 0000911F F3/ 48/ 0F 2A CC cvtsi2ss xmm1, rsp \n"
" 00009124 F2/ 48/ 0F 2A CC cvtsi2sd xmm1, rsp \n"
" \n"
" \n"
" ; Between: xmm1 and rbp \n"
" 00009129 F3/ 0F 11 4D movss dword ptr [rbp - 4], xmm1 \n"
" FC \n"
" 0000912E F2/ 0F 11 4D movsd qword ptr [rbp + 4], xmm1 \n"
" 04 \n"
" \n"
" 00009133 F3/ 0F 10 4D movss xmm1, dword ptr [rbp - 4] \n"
" FC \n"
" 00009138 F2/ 0F 10 4D movsd xmm1, qword ptr [rbp + 4] \n"
" 04 \n"
" 0000913D F3/ 48/ 0F 2A 4D cvtsi2ss xmm1, qword ptr [rbp - 4] \n"
" FC \n"
" 00009143 F2/ 0F 2A 4D cvtsi2sd xmm1, dword ptr [rbp + 4] \n"
" 04 \n"
" \n"
" 00009148 F3/ 0F 2C E9 cvttss2si ebp, xmm1 \n"
" 0000914C F2/ 0F 2C E9 cvttsd2si ebp, xmm1 \n"
" \n"
" 00009150 F3/ 0F 2A CD cvtsi2ss xmm1, ebp \n"
" 00009154 F2/ 0F 2A CD cvtsi2sd xmm1, ebp \n"
" \n"
" 00009158 F3/ 48/ 0F 2C E9 cvttss2si rbp, xmm1 \n"
" 0000915D F2/ 48/ 0F 2C E9 cvttsd2si rbp, xmm1 \n"
" \n"
" 00009162 F3/ 48/ 0F 2A CD cvtsi2ss xmm1, rbp \n"
" 00009167 F2/ 48/ 0F 2A CD cvtsi2sd xmm1, rbp \n"
" \n"
" \n"
" ; Between: xmm1 and rsi \n"
" 0000916C F3/ 0F 11 4E movss dword ptr [rsi - 4], xmm1 \n"
" FC \n"
" 00009171 F2/ 0F 11 4E movsd qword ptr [rsi + 4], xmm1 \n"
" 04 \n"
" \n"
" 00009176 F3/ 0F 10 4E movss xmm1, dword ptr [rsi - 4] \n"
" FC \n"
" 0000917B F2/ 0F 10 4E movsd xmm1, qword ptr [rsi + 4] \n"
" 04 \n"
" 00009180 F3/ 48/ 0F 2A 4E cvtsi2ss xmm1, qword ptr [rsi - 4] \n"
" FC \n"
" 00009186 F2/ 0F 2A 4E cvtsi2sd xmm1, dword ptr [rsi + 4] \n"
" 04 \n"
" \n"
" 0000918B F3/ 0F 2C F1 cvttss2si esi, xmm1 \n"
" 0000918F F2/ 0F 2C F1 cvttsd2si esi, xmm1 \n"
" \n"
" 00009193 F3/ 0F 2A CE cvtsi2ss xmm1, esi \n"
" 00009197 F2/ 0F 2A CE cvtsi2sd xmm1, esi \n"
" \n"
" 0000919B F3/ 48/ 0F 2C F1 cvttss2si rsi, xmm1 \n"
" 000091A0 F2/ 48/ 0F 2C F1 cvttsd2si rsi, xmm1 \n"
" \n"
" 000091A5 F3/ 48/ 0F 2A CE cvtsi2ss xmm1, rsi \n"
" 000091AA F2/ 48/ 0F 2A CE cvtsi2sd xmm1, rsi \n"
" \n"
" \n"
" ; Between: xmm1 and rdi \n"
" 000091AF F3/ 0F 11 4F movss dword ptr [rdi - 4], xmm1 \n"
" FC \n"
" 000091B4 F2/ 0F 11 4F movsd qword ptr [rdi + 4], xmm1 \n"
" 04 \n"
" \n"
" 000091B9 F3/ 0F 10 4F movss xmm1, dword ptr [rdi - 4] \n"
" FC \n"
" 000091BE F2/ 0F 10 4F movsd xmm1, qword ptr [rdi + 4] \n"
" 04 \n"
" 000091C3 F3/ 48/ 0F 2A 4F cvtsi2ss xmm1, qword ptr [rdi - 4] \n"
" FC \n"
" 000091C9 F2/ 0F 2A 4F cvtsi2sd xmm1, dword ptr [rdi + 4] \n"
" 04 \n"
" \n"
" 000091CE F3/ 0F 2C F9 cvttss2si edi, xmm1 \n"
" 000091D2 F2/ 0F 2C F9 cvttsd2si edi, xmm1 \n"
" \n"
" 000091D6 F3/ 0F 2A CF cvtsi2ss xmm1, edi \n"
" 000091DA F2/ 0F 2A CF cvtsi2sd xmm1, edi \n"
" \n"
" 000091DE F3/ 48/ 0F 2C F9 cvttss2si rdi, xmm1 \n"
" 000091E3 F2/ 48/ 0F 2C F9 cvttsd2si rdi, xmm1 \n"
" \n"
" 000091E8 F3/ 48/ 0F 2A CF cvtsi2ss xmm1, rdi \n"
" 000091ED F2/ 48/ 0F 2A CF cvtsi2sd xmm1, rdi \n"
" \n"
" \n"
" ; Between: xmm1 and r8 \n"
" 000091F2 F3/ 41/ 0F 11 48 movss dword ptr [r8 - 4], xmm1 \n"
" FC \n"
" 000091F8 F2/ 41/ 0F 11 48 movsd qword ptr [r8 + 4], xmm1 \n"
" 04 \n"
" \n"
" 000091FE F3/ 41/ 0F 10 48 movss xmm1, dword ptr [r8 - 4] \n"
" FC \n"
" 00009204 F2/ 41/ 0F 10 48 movsd xmm1, qword ptr [r8 + 4] \n"
" 04 \n"
" 0000920A F3/ 49/ 0F 2A 48 cvtsi2ss xmm1, qword ptr [r8 - 4] \n"
" FC \n"
" 00009210 F2/ 41/ 0F 2A 48 cvtsi2sd xmm1, dword ptr [r8 + 4] \n"
" 04 \n"
" \n"
" 00009216 F3/ 44/ 0F 2C C1 cvttss2si r8d, xmm1 \n"
" 0000921B F2/ 44/ 0F 2C C1 cvttsd2si r8d, xmm1 \n"
" \n"
" 00009220 F3/ 41/ 0F 2A C8 cvtsi2ss xmm1, r8d \n"
" 00009225 F2/ 41/ 0F 2A C8 cvtsi2sd xmm1, r8d \n"
" \n"
" 0000922A F3/ 4C/ 0F 2C C1 cvttss2si r8, xmm1 \n"
" 0000922F F2/ 4C/ 0F 2C C1 cvttsd2si r8, xmm1 \n"
" \n"
" 00009234 F3/ 49/ 0F 2A C8 cvtsi2ss xmm1, r8 \n"
" 00009239 F2/ 49/ 0F 2A C8 cvtsi2sd xmm1, r8 \n"
" \n"
" \n"
" ; Between: xmm1 and r9 \n"
" 0000923E F3/ 41/ 0F 11 49 movss dword ptr [r9 - 4], xmm1 \n"
" FC \n"
" 00009244 F2/ 41/ 0F 11 49 movsd qword ptr [r9 + 4], xmm1 \n"
" 04 \n"
" \n"
" 0000924A F3/ 41/ 0F 10 49 movss xmm1, dword ptr [r9 - 4] \n"
" FC \n"
" 00009250 F2/ 41/ 0F 10 49 movsd xmm1, qword ptr [r9 + 4] \n"
" 04 \n"
" 00009256 F3/ 49/ 0F 2A 49 cvtsi2ss xmm1, qword ptr [r9 - 4] \n"
" FC \n"
" 0000925C F2/ 41/ 0F 2A 49 cvtsi2sd xmm1, dword ptr [r9 + 4] \n"
" 04 \n"
" \n"
" 00009262 F3/ 44/ 0F 2C C9 cvttss2si r9d, xmm1 \n"
" 00009267 F2/ 44/ 0F 2C C9 cvttsd2si r9d, xmm1 \n"
" \n"
" 0000926C F3/ 41/ 0F 2A C9 cvtsi2ss xmm1, r9d \n"
" 00009271 F2/ 41/ 0F 2A C9 cvtsi2sd xmm1, r9d \n"
" \n"
" 00009276 F3/ 4C/ 0F 2C C9 cvttss2si r9, xmm1 \n"
" 0000927B F2/ 4C/ 0F 2C C9 cvttsd2si r9, xmm1 \n"
" \n"
" 00009280 F3/ 49/ 0F 2A C9 cvtsi2ss xmm1, r9 \n"
" 00009285 F2/ 49/ 0F 2A C9 cvtsi2sd xmm1, r9 \n"
" \n"
" \n"
" ; Between: xmm1 and r10 \n"
" 0000928A F3/ 41/ 0F 11 4A movss dword ptr [r10 - 4], xmm1 \n"
" FC \n"
" 00009290 F2/ 41/ 0F 11 4A movsd qword ptr [r10 + 4], xmm1 \n"
" 04 \n"
" \n"
" 00009296 F3/ 41/ 0F 10 4A movss xmm1, dword ptr [r10 - 4] \n"
" FC \n"
" 0000929C F2/ 41/ 0F 10 4A movsd xmm1, qword ptr [r10 + 4] \n"
" 04 \n"
" 000092A2 F3/ 49/ 0F 2A 4A cvtsi2ss xmm1, qword ptr [r10 - 4] \n"
" FC \n"
" 000092A8 F2/ 41/ 0F 2A 4A cvtsi2sd xmm1, dword ptr [r10 + 4] \n"
" 04 \n"
" \n"
" 000092AE F3/ 44/ 0F 2C D1 cvttss2si r10d, xmm1 \n"
" 000092B3 F2/ 44/ 0F 2C D1 cvttsd2si r10d, xmm1 \n"
" \n"
" 000092B8 F3/ 41/ 0F 2A CA cvtsi2ss xmm1, r10d \n"
" 000092BD F2/ 41/ 0F 2A CA cvtsi2sd xmm1, r10d \n"
" \n"
" 000092C2 F3/ 4C/ 0F 2C D1 cvttss2si r10, xmm1 \n"
" 000092C7 F2/ 4C/ 0F 2C D1 cvttsd2si r10, xmm1 \n"
" \n"
" 000092CC F3/ 49/ 0F 2A CA cvtsi2ss xmm1, r10 \n"
" 000092D1 F2/ 49/ 0F 2A CA cvtsi2sd xmm1, r10 \n"
" \n"
" \n"
" ; Between: xmm1 and r11 \n"
" 000092D6 F3/ 41/ 0F 11 4B movss dword ptr [r11 - 4], xmm1 \n"
" FC \n"
" 000092DC F2/ 41/ 0F 11 4B movsd qword ptr [r11 + 4], xmm1 \n"
" 04 \n"
" \n"
" 000092E2 F3/ 41/ 0F 10 4B movss xmm1, dword ptr [r11 - 4] \n"
" FC \n"
" 000092E8 F2/ 41/ 0F 10 4B movsd xmm1, qword ptr [r11 + 4] \n"
" 04 \n"
" 000092EE F3/ 49/ 0F 2A 4B cvtsi2ss xmm1, qword ptr [r11 - 4] \n"
" FC \n"
" 000092F4 F2/ 41/ 0F 2A 4B cvtsi2sd xmm1, dword ptr [r11 + 4] \n"
" 04 \n"
" \n"
" 000092FA F3/ 44/ 0F 2C D9 cvttss2si r11d, xmm1 \n"
" 000092FF F2/ 44/ 0F 2C D9 cvttsd2si r11d, xmm1 \n"
" \n"
" 00009304 F3/ 41/ 0F 2A CB cvtsi2ss xmm1, r11d \n"
" 00009309 F2/ 41/ 0F 2A CB cvtsi2sd xmm1, r11d \n"
" \n"
" 0000930E F3/ 4C/ 0F 2C D9 cvttss2si r11, xmm1 \n"
" 00009313 F2/ 4C/ 0F 2C D9 cvttsd2si r11, xmm1 \n"
" \n"
" 00009318 F3/ 49/ 0F 2A CB cvtsi2ss xmm1, r11 \n"
" 0000931D F2/ 49/ 0F 2A CB cvtsi2sd xmm1, r11 \n"
" \n"
" \n"
" ; Between: xmm1 and r12 \n"
" 00009322 F3/ 41/ 0F 11 4C movss dword ptr [r12 - 4], xmm1 \n"
" 24 FC \n"
" 00009329 F2/ 41/ 0F 11 4C movsd qword ptr [r12 + 4], xmm1 \n"
" 24 04 \n"
" \n"
" 00009330 F3/ 41/ 0F 10 4C movss xmm1, dword ptr [r12 - 4] \n"
" 24 FC \n"
" 00009337 F2/ 41/ 0F 10 4C movsd xmm1, qword ptr [r12 + 4] \n"
" 24 04 \n"
" 0000933E F3/ 49/ 0F 2A 4C cvtsi2ss xmm1, qword ptr [r12 - 4] \n"
" 24 FC \n"
" 00009345 F2/ 41/ 0F 2A 4C cvtsi2sd xmm1, dword ptr [r12 + 4] \n"
" 24 04 \n"
" \n"
" 0000934C F3/ 44/ 0F 2C E1 cvttss2si r12d, xmm1 \n"
" 00009351 F2/ 44/ 0F 2C E1 cvttsd2si r12d, xmm1 \n"
" \n"
" 00009356 F3/ 41/ 0F 2A CC cvtsi2ss xmm1, r12d \n"
" 0000935B F2/ 41/ 0F 2A CC cvtsi2sd xmm1, r12d \n"
" \n"
" 00009360 F3/ 4C/ 0F 2C E1 cvttss2si r12, xmm1 \n"
" 00009365 F2/ 4C/ 0F 2C E1 cvttsd2si r12, xmm1 \n"
" \n"
" 0000936A F3/ 49/ 0F 2A CC cvtsi2ss xmm1, r12 \n"
" 0000936F F2/ 49/ 0F 2A CC cvtsi2sd xmm1, r12 \n"
" \n"
" \n"
" ; Between: xmm1 and r13 \n"
" 00009374 F3/ 41/ 0F 11 4D movss dword ptr [r13 - 4], xmm1 \n"
" FC \n"
" 0000937A F2/ 41/ 0F 11 4D movsd qword ptr [r13 + 4], xmm1 \n"
" 04 \n"
" \n"
" 00009380 F3/ 41/ 0F 10 4D movss xmm1, dword ptr [r13 - 4] \n"
" FC \n"
" 00009386 F2/ 41/ 0F 10 4D movsd xmm1, qword ptr [r13 + 4] \n"
" 04 \n"
" 0000938C F3/ 49/ 0F 2A 4D cvtsi2ss xmm1, qword ptr [r13 - 4] \n"
" FC \n"
" 00009392 F2/ 41/ 0F 2A 4D cvtsi2sd xmm1, dword ptr [r13 + 4] \n"
" 04 \n"
" \n"
" 00009398 F3/ 44/ 0F 2C E9 cvttss2si r13d, xmm1 \n"
" 0000939D F2/ 44/ 0F 2C E9 cvttsd2si r13d, xmm1 \n"
" \n"
" 000093A2 F3/ 41/ 0F 2A CD cvtsi2ss xmm1, r13d \n"
" 000093A7 F2/ 41/ 0F 2A CD cvtsi2sd xmm1, r13d \n"
" \n"
" 000093AC F3/ 4C/ 0F 2C E9 cvttss2si r13, xmm1 \n"
" 000093B1 F2/ 4C/ 0F 2C E9 cvttsd2si r13, xmm1 \n"
" \n"
" 000093B6 F3/ 49/ 0F 2A CD cvtsi2ss xmm1, r13 \n"
" 000093BB F2/ 49/ 0F 2A CD cvtsi2sd xmm1, r13 \n"
" \n"
" \n"
" ; Between: xmm1 and r14 \n"
" 000093C0 F3/ 41/ 0F 11 4E movss dword ptr [r14 - 4], xmm1 \n"
" FC \n"
" 000093C6 F2/ 41/ 0F 11 4E movsd qword ptr [r14 + 4], xmm1 \n"
" 04 \n"
" \n"
" 000093CC F3/ 41/ 0F 10 4E movss xmm1, dword ptr [r14 - 4] \n"
" FC \n"
" 000093D2 F2/ 41/ 0F 10 4E movsd xmm1, qword ptr [r14 + 4] \n"
" 04 \n"
" 000093D8 F3/ 49/ 0F 2A 4E cvtsi2ss xmm1, qword ptr [r14 - 4] \n"
" FC \n"
" 000093DE F2/ 41/ 0F 2A 4E cvtsi2sd xmm1, dword ptr [r14 + 4] \n"
" 04 \n"
" \n"
" 000093E4 F3/ 44/ 0F 2C F1 cvttss2si r14d, xmm1 \n"
" 000093E9 F2/ 44/ 0F 2C F1 cvttsd2si r14d, xmm1 \n"
" \n"
" 000093EE F3/ 41/ 0F 2A CE cvtsi2ss xmm1, r14d \n"
" 000093F3 F2/ 41/ 0F 2A CE cvtsi2sd xmm1, r14d \n"
" \n"
" 000093F8 F3/ 4C/ 0F 2C F1 cvttss2si r14, xmm1 \n"
" 000093FD F2/ 4C/ 0F 2C F1 cvttsd2si r14, xmm1 \n"
" \n"
" 00009402 F3/ 49/ 0F 2A CE cvtsi2ss xmm1, r14 \n"
" 00009407 F2/ 49/ 0F 2A CE cvtsi2sd xmm1, r14 \n"
" \n"
" \n"
" ; Between: xmm1 and r15 \n"
" 0000940C F3/ 41/ 0F 11 4F movss dword ptr [r15 - 4], xmm1 \n"
" FC \n"
" 00009412 F2/ 41/ 0F 11 4F movsd qword ptr [r15 + 4], xmm1 \n"
" 04 \n"
" \n"
" 00009418 F3/ 41/ 0F 10 4F movss xmm1, dword ptr [r15 - 4] \n"
" FC \n"
" 0000941E F2/ 41/ 0F 10 4F movsd xmm1, qword ptr [r15 + 4] \n"
" 04 \n"
" 00009424 F3/ 49/ 0F 2A 4F cvtsi2ss xmm1, qword ptr [r15 - 4] \n"
" FC \n"
" 0000942A F2/ 41/ 0F 2A 4F cvtsi2sd xmm1, dword ptr [r15 + 4] \n"
" 04 \n"
" \n"
" 00009430 F3/ 44/ 0F 2C F9 cvttss2si r15d, xmm1 \n"
" 00009435 F2/ 44/ 0F 2C F9 cvttsd2si r15d, xmm1 \n"
" \n"
" 0000943A F3/ 41/ 0F 2A CF cvtsi2ss xmm1, r15d \n"
" 0000943F F2/ 41/ 0F 2A CF cvtsi2sd xmm1, r15d \n"
" \n"
" 00009444 F3/ 4C/ 0F 2C F9 cvttss2si r15, xmm1 \n"
" 00009449 F2/ 4C/ 0F 2C F9 cvttsd2si r15, xmm1 \n"
" \n"
" 0000944E F3/ 49/ 0F 2A CF cvtsi2ss xmm1, r15 \n"
" 00009453 F2/ 49/ 0F 2A CF cvtsi2sd xmm1, r15 \n"
" \n"
" \n"
" ; Between: xmm2 and rax \n"
" 00009458 F3/ 0F 11 50 movss dword ptr [rax - 4], xmm2 \n"
" FC \n"
" 0000945D F2/ 0F 11 50 movsd qword ptr [rax + 4], xmm2 \n"
" 04 \n"
" \n"
" 00009462 F3/ 0F 10 50 movss xmm2, dword ptr [rax - 4] \n"
" FC \n"
" 00009467 F2/ 0F 10 50 movsd xmm2, qword ptr [rax + 4] \n"
" 04 \n"
" 0000946C F3/ 48/ 0F 2A 50 cvtsi2ss xmm2, qword ptr [rax - 4] \n"
" FC \n"
" 00009472 F2/ 0F 2A 50 cvtsi2sd xmm2, dword ptr [rax + 4] \n"
" 04 \n"
" \n"
" 00009477 F3/ 0F 2C C2 cvttss2si eax, xmm2 \n"
" 0000947B F2/ 0F 2C C2 cvttsd2si eax, xmm2 \n"
" \n"
" 0000947F F3/ 0F 2A D0 cvtsi2ss xmm2, eax \n"
" 00009483 F2/ 0F 2A D0 cvtsi2sd xmm2, eax \n"
" \n"
" 00009487 F3/ 48/ 0F 2C C2 cvttss2si rax, xmm2 \n"
" 0000948C F2/ 48/ 0F 2C C2 cvttsd2si rax, xmm2 \n"
" \n"
" 00009491 F3/ 48/ 0F 2A D0 cvtsi2ss xmm2, rax \n"
" 00009496 F2/ 48/ 0F 2A D0 cvtsi2sd xmm2, rax \n"
" \n"
" \n"
" ; Between: xmm2 and rcx \n"
" 0000949B F3/ 0F 11 51 movss dword ptr [rcx - 4], xmm2 \n"
" FC \n"
" 000094A0 F2/ 0F 11 51 movsd qword ptr [rcx + 4], xmm2 \n"
" 04 \n"
" \n"
" 000094A5 F3/ 0F 10 51 movss xmm2, dword ptr [rcx - 4] \n"
" FC \n"
" 000094AA F2/ 0F 10 51 movsd xmm2, qword ptr [rcx + 4] \n"
" 04 \n"
" 000094AF F3/ 48/ 0F 2A 51 cvtsi2ss xmm2, qword ptr [rcx - 4] \n"
" FC \n"
" 000094B5 F2/ 0F 2A 51 cvtsi2sd xmm2, dword ptr [rcx + 4] \n"
" 04 \n"
" \n"
" 000094BA F3/ 0F 2C CA cvttss2si ecx, xmm2 \n"
" 000094BE F2/ 0F 2C CA cvttsd2si ecx, xmm2 \n"
" \n"
" 000094C2 F3/ 0F 2A D1 cvtsi2ss xmm2, ecx \n"
" 000094C6 F2/ 0F 2A D1 cvtsi2sd xmm2, ecx \n"
" \n"
" 000094CA F3/ 48/ 0F 2C CA cvttss2si rcx, xmm2 \n"
" 000094CF F2/ 48/ 0F 2C CA cvttsd2si rcx, xmm2 \n"
" \n"
" 000094D4 F3/ 48/ 0F 2A D1 cvtsi2ss xmm2, rcx \n"
" 000094D9 F2/ 48/ 0F 2A D1 cvtsi2sd xmm2, rcx \n"
" \n"
" \n"
" ; Between: xmm2 and rdx \n"
" 000094DE F3/ 0F 11 52 movss dword ptr [rdx - 4], xmm2 \n"
" FC \n"
" 000094E3 F2/ 0F 11 52 movsd qword ptr [rdx + 4], xmm2 \n"
" 04 \n"
" \n"
" 000094E8 F3/ 0F 10 52 movss xmm2, dword ptr [rdx - 4] \n"
" FC \n"
" 000094ED F2/ 0F 10 52 movsd xmm2, qword ptr [rdx + 4] \n"
" 04 \n"
" 000094F2 F3/ 48/ 0F 2A 52 cvtsi2ss xmm2, qword ptr [rdx - 4] \n"
" FC \n"
" 000094F8 F2/ 0F 2A 52 cvtsi2sd xmm2, dword ptr [rdx + 4] \n"
" 04 \n"
" \n"
" 000094FD F3/ 0F 2C D2 cvttss2si edx, xmm2 \n"
" 00009501 F2/ 0F 2C D2 cvttsd2si edx, xmm2 \n"
" \n"
" 00009505 F3/ 0F 2A D2 cvtsi2ss xmm2, edx \n"
" 00009509 F2/ 0F 2A D2 cvtsi2sd xmm2, edx \n"
" \n"
" 0000950D F3/ 48/ 0F 2C D2 cvttss2si rdx, xmm2 \n"
" 00009512 F2/ 48/ 0F 2C D2 cvttsd2si rdx, xmm2 \n"
" \n"
" 00009517 F3/ 48/ 0F 2A D2 cvtsi2ss xmm2, rdx \n"
" 0000951C F2/ 48/ 0F 2A D2 cvtsi2sd xmm2, rdx \n"
" \n"
" \n"
" ; Between: xmm2 and rbx \n"
" 00009521 F3/ 0F 11 53 movss dword ptr [rbx - 4], xmm2 \n"
" FC \n"
" 00009526 F2/ 0F 11 53 movsd qword ptr [rbx + 4], xmm2 \n"
" 04 \n"
" \n"
" 0000952B F3/ 0F 10 53 movss xmm2, dword ptr [rbx - 4] \n"
" FC \n"
" 00009530 F2/ 0F 10 53 movsd xmm2, qword ptr [rbx + 4] \n"
" 04 \n"
" 00009535 F3/ 48/ 0F 2A 53 cvtsi2ss xmm2, qword ptr [rbx - 4] \n"
" FC \n"
" 0000953B F2/ 0F 2A 53 cvtsi2sd xmm2, dword ptr [rbx + 4] \n"
" 04 \n"
" \n"
" 00009540 F3/ 0F 2C DA cvttss2si ebx, xmm2 \n"
" 00009544 F2/ 0F 2C DA cvttsd2si ebx, xmm2 \n"
" \n"
" 00009548 F3/ 0F 2A D3 cvtsi2ss xmm2, ebx \n"
" 0000954C F2/ 0F 2A D3 cvtsi2sd xmm2, ebx \n"
" \n"
" 00009550 F3/ 48/ 0F 2C DA cvttss2si rbx, xmm2 \n"
" 00009555 F2/ 48/ 0F 2C DA cvttsd2si rbx, xmm2 \n"
" \n"
" 0000955A F3/ 48/ 0F 2A D3 cvtsi2ss xmm2, rbx \n"
" 0000955F F2/ 48/ 0F 2A D3 cvtsi2sd xmm2, rbx \n"
" \n"
" \n"
" ; Between: xmm2 and rsp \n"
" 00009564 F3/ 0F 11 54 24 movss dword ptr [rsp - 4], xmm2 \n"
" FC \n"
" 0000956A F2/ 0F 11 54 24 movsd qword ptr [rsp + 4], xmm2 \n"
" 04 \n"
" \n"
" 00009570 F3/ 0F 10 54 24 movss xmm2, dword ptr [rsp - 4] \n"
" FC \n"
" 00009576 F2/ 0F 10 54 24 movsd xmm2, qword ptr [rsp + 4] \n"
" 04 \n"
" 0000957C F3/ 48/ 0F 2A 54 cvtsi2ss xmm2, qword ptr [rsp - 4] \n"
" 24 FC \n"
" 00009583 F2/ 0F 2A 54 24 cvtsi2sd xmm2, dword ptr [rsp + 4] \n"
" 04 \n"
" \n"
" 00009589 F3/ 0F 2C E2 cvttss2si esp, xmm2 \n"
" 0000958D F2/ 0F 2C E2 cvttsd2si esp, xmm2 \n"
" \n"
" 00009591 F3/ 0F 2A D4 cvtsi2ss xmm2, esp \n"
" 00009595 F2/ 0F 2A D4 cvtsi2sd xmm2, esp \n";
ml64Output +=
" \n"
" 00009599 F3/ 48/ 0F 2C E2 cvttss2si rsp, xmm2 \n"
" 0000959E F2/ 48/ 0F 2C E2 cvttsd2si rsp, xmm2 \n"
" \n"
" 000095A3 F3/ 48/ 0F 2A D4 cvtsi2ss xmm2, rsp \n"
" 000095A8 F2/ 48/ 0F 2A D4 cvtsi2sd xmm2, rsp \n"
" \n"
" \n"
" ; Between: xmm2 and rbp \n"
" 000095AD F3/ 0F 11 55 movss dword ptr [rbp - 4], xmm2 \n"
" FC \n"
" 000095B2 F2/ 0F 11 55 movsd qword ptr [rbp + 4], xmm2 \n"
" 04 \n"
" \n"
" 000095B7 F3/ 0F 10 55 movss xmm2, dword ptr [rbp - 4] \n"
" FC \n"
" 000095BC F2/ 0F 10 55 movsd xmm2, qword ptr [rbp + 4] \n"
" 04 \n"
" 000095C1 F3/ 48/ 0F 2A 55 cvtsi2ss xmm2, qword ptr [rbp - 4] \n"
" FC \n"
" 000095C7 F2/ 0F 2A 55 cvtsi2sd xmm2, dword ptr [rbp + 4] \n"
" 04 \n"
" \n"
" 000095CC F3/ 0F 2C EA cvttss2si ebp, xmm2 \n"
" 000095D0 F2/ 0F 2C EA cvttsd2si ebp, xmm2 \n"
" \n"
" 000095D4 F3/ 0F 2A D5 cvtsi2ss xmm2, ebp \n"
" 000095D8 F2/ 0F 2A D5 cvtsi2sd xmm2, ebp \n"
" \n"
" 000095DC F3/ 48/ 0F 2C EA cvttss2si rbp, xmm2 \n"
" 000095E1 F2/ 48/ 0F 2C EA cvttsd2si rbp, xmm2 \n"
" \n"
" 000095E6 F3/ 48/ 0F 2A D5 cvtsi2ss xmm2, rbp \n"
" 000095EB F2/ 48/ 0F 2A D5 cvtsi2sd xmm2, rbp \n"
" \n"
" \n"
" ; Between: xmm2 and rsi \n"
" 000095F0 F3/ 0F 11 56 movss dword ptr [rsi - 4], xmm2 \n"
" FC \n"
" 000095F5 F2/ 0F 11 56 movsd qword ptr [rsi + 4], xmm2 \n"
" 04 \n"
" \n"
" 000095FA F3/ 0F 10 56 movss xmm2, dword ptr [rsi - 4] \n"
" FC \n"
" 000095FF F2/ 0F 10 56 movsd xmm2, qword ptr [rsi + 4] \n"
" 04 \n"
" 00009604 F3/ 48/ 0F 2A 56 cvtsi2ss xmm2, qword ptr [rsi - 4] \n"
" FC \n"
" 0000960A F2/ 0F 2A 56 cvtsi2sd xmm2, dword ptr [rsi + 4] \n"
" 04 \n"
" \n"
" 0000960F F3/ 0F 2C F2 cvttss2si esi, xmm2 \n"
" 00009613 F2/ 0F 2C F2 cvttsd2si esi, xmm2 \n"
" \n"
" 00009617 F3/ 0F 2A D6 cvtsi2ss xmm2, esi \n"
" 0000961B F2/ 0F 2A D6 cvtsi2sd xmm2, esi \n"
" \n"
" 0000961F F3/ 48/ 0F 2C F2 cvttss2si rsi, xmm2 \n"
" 00009624 F2/ 48/ 0F 2C F2 cvttsd2si rsi, xmm2 \n"
" \n"
" 00009629 F3/ 48/ 0F 2A D6 cvtsi2ss xmm2, rsi \n"
" 0000962E F2/ 48/ 0F 2A D6 cvtsi2sd xmm2, rsi \n"
" \n"
" \n"
" ; Between: xmm2 and rdi \n"
" 00009633 F3/ 0F 11 57 movss dword ptr [rdi - 4], xmm2 \n"
" FC \n"
" 00009638 F2/ 0F 11 57 movsd qword ptr [rdi + 4], xmm2 \n"
" 04 \n"
" \n"
" 0000963D F3/ 0F 10 57 movss xmm2, dword ptr [rdi - 4] \n"
" FC \n"
" 00009642 F2/ 0F 10 57 movsd xmm2, qword ptr [rdi + 4] \n"
" 04 \n"
" 00009647 F3/ 48/ 0F 2A 57 cvtsi2ss xmm2, qword ptr [rdi - 4] \n"
" FC \n"
" 0000964D F2/ 0F 2A 57 cvtsi2sd xmm2, dword ptr [rdi + 4] \n"
" 04 \n"
" \n"
" 00009652 F3/ 0F 2C FA cvttss2si edi, xmm2 \n"
" 00009656 F2/ 0F 2C FA cvttsd2si edi, xmm2 \n"
" \n"
" 0000965A F3/ 0F 2A D7 cvtsi2ss xmm2, edi \n"
" 0000965E F2/ 0F 2A D7 cvtsi2sd xmm2, edi \n"
" \n"
" 00009662 F3/ 48/ 0F 2C FA cvttss2si rdi, xmm2 \n"
" 00009667 F2/ 48/ 0F 2C FA cvttsd2si rdi, xmm2 \n"
" \n"
" 0000966C F3/ 48/ 0F 2A D7 cvtsi2ss xmm2, rdi \n"
" 00009671 F2/ 48/ 0F 2A D7 cvtsi2sd xmm2, rdi \n"
" \n"
" \n"
" ; Between: xmm2 and r8 \n"
" 00009676 F3/ 41/ 0F 11 50 movss dword ptr [r8 - 4], xmm2 \n"
" FC \n"
" 0000967C F2/ 41/ 0F 11 50 movsd qword ptr [r8 + 4], xmm2 \n"
" 04 \n"
" \n"
" 00009682 F3/ 41/ 0F 10 50 movss xmm2, dword ptr [r8 - 4] \n"
" FC \n"
" 00009688 F2/ 41/ 0F 10 50 movsd xmm2, qword ptr [r8 + 4] \n"
" 04 \n"
" 0000968E F3/ 49/ 0F 2A 50 cvtsi2ss xmm2, qword ptr [r8 - 4] \n"
" FC \n"
" 00009694 F2/ 41/ 0F 2A 50 cvtsi2sd xmm2, dword ptr [r8 + 4] \n"
" 04 \n"
" \n"
" 0000969A F3/ 44/ 0F 2C C2 cvttss2si r8d, xmm2 \n"
" 0000969F F2/ 44/ 0F 2C C2 cvttsd2si r8d, xmm2 \n"
" \n"
" 000096A4 F3/ 41/ 0F 2A D0 cvtsi2ss xmm2, r8d \n"
" 000096A9 F2/ 41/ 0F 2A D0 cvtsi2sd xmm2, r8d \n"
" \n"
" 000096AE F3/ 4C/ 0F 2C C2 cvttss2si r8, xmm2 \n"
" 000096B3 F2/ 4C/ 0F 2C C2 cvttsd2si r8, xmm2 \n"
" \n"
" 000096B8 F3/ 49/ 0F 2A D0 cvtsi2ss xmm2, r8 \n"
" 000096BD F2/ 49/ 0F 2A D0 cvtsi2sd xmm2, r8 \n"
" \n"
" \n"
" ; Between: xmm2 and r9 \n"
" 000096C2 F3/ 41/ 0F 11 51 movss dword ptr [r9 - 4], xmm2 \n"
" FC \n"
" 000096C8 F2/ 41/ 0F 11 51 movsd qword ptr [r9 + 4], xmm2 \n"
" 04 \n"
" \n"
" 000096CE F3/ 41/ 0F 10 51 movss xmm2, dword ptr [r9 - 4] \n"
" FC \n"
" 000096D4 F2/ 41/ 0F 10 51 movsd xmm2, qword ptr [r9 + 4] \n"
" 04 \n"
" 000096DA F3/ 49/ 0F 2A 51 cvtsi2ss xmm2, qword ptr [r9 - 4] \n"
" FC \n"
" 000096E0 F2/ 41/ 0F 2A 51 cvtsi2sd xmm2, dword ptr [r9 + 4] \n"
" 04 \n"
" \n"
" 000096E6 F3/ 44/ 0F 2C CA cvttss2si r9d, xmm2 \n"
" 000096EB F2/ 44/ 0F 2C CA cvttsd2si r9d, xmm2 \n"
" \n"
" 000096F0 F3/ 41/ 0F 2A D1 cvtsi2ss xmm2, r9d \n"
" 000096F5 F2/ 41/ 0F 2A D1 cvtsi2sd xmm2, r9d \n"
" \n"
" 000096FA F3/ 4C/ 0F 2C CA cvttss2si r9, xmm2 \n"
" 000096FF F2/ 4C/ 0F 2C CA cvttsd2si r9, xmm2 \n"
" \n"
" 00009704 F3/ 49/ 0F 2A D1 cvtsi2ss xmm2, r9 \n"
" 00009709 F2/ 49/ 0F 2A D1 cvtsi2sd xmm2, r9 \n"
" \n"
" \n"
" ; Between: xmm2 and r10 \n"
" 0000970E F3/ 41/ 0F 11 52 movss dword ptr [r10 - 4], xmm2 \n"
" FC \n"
" 00009714 F2/ 41/ 0F 11 52 movsd qword ptr [r10 + 4], xmm2 \n"
" 04 \n"
" \n"
" 0000971A F3/ 41/ 0F 10 52 movss xmm2, dword ptr [r10 - 4] \n"
" FC \n"
" 00009720 F2/ 41/ 0F 10 52 movsd xmm2, qword ptr [r10 + 4] \n"
" 04 \n"
" 00009726 F3/ 49/ 0F 2A 52 cvtsi2ss xmm2, qword ptr [r10 - 4] \n"
" FC \n"
" 0000972C F2/ 41/ 0F 2A 52 cvtsi2sd xmm2, dword ptr [r10 + 4] \n"
" 04 \n"
" \n"
" 00009732 F3/ 44/ 0F 2C D2 cvttss2si r10d, xmm2 \n"
" 00009737 F2/ 44/ 0F 2C D2 cvttsd2si r10d, xmm2 \n"
" \n"
" 0000973C F3/ 41/ 0F 2A D2 cvtsi2ss xmm2, r10d \n"
" 00009741 F2/ 41/ 0F 2A D2 cvtsi2sd xmm2, r10d \n"
" \n"
" 00009746 F3/ 4C/ 0F 2C D2 cvttss2si r10, xmm2 \n"
" 0000974B F2/ 4C/ 0F 2C D2 cvttsd2si r10, xmm2 \n"
" \n"
" 00009750 F3/ 49/ 0F 2A D2 cvtsi2ss xmm2, r10 \n"
" 00009755 F2/ 49/ 0F 2A D2 cvtsi2sd xmm2, r10 \n"
" \n"
" \n"
" ; Between: xmm2 and r11 \n"
" 0000975A F3/ 41/ 0F 11 53 movss dword ptr [r11 - 4], xmm2 \n"
" FC \n"
" 00009760 F2/ 41/ 0F 11 53 movsd qword ptr [r11 + 4], xmm2 \n"
" 04 \n"
" \n"
" 00009766 F3/ 41/ 0F 10 53 movss xmm2, dword ptr [r11 - 4] \n"
" FC \n"
" 0000976C F2/ 41/ 0F 10 53 movsd xmm2, qword ptr [r11 + 4] \n"
" 04 \n"
" 00009772 F3/ 49/ 0F 2A 53 cvtsi2ss xmm2, qword ptr [r11 - 4] \n"
" FC \n"
" 00009778 F2/ 41/ 0F 2A 53 cvtsi2sd xmm2, dword ptr [r11 + 4] \n"
" 04 \n"
" \n"
" 0000977E F3/ 44/ 0F 2C DA cvttss2si r11d, xmm2 \n"
" 00009783 F2/ 44/ 0F 2C DA cvttsd2si r11d, xmm2 \n"
" \n"
" 00009788 F3/ 41/ 0F 2A D3 cvtsi2ss xmm2, r11d \n"
" 0000978D F2/ 41/ 0F 2A D3 cvtsi2sd xmm2, r11d \n"
" \n"
" 00009792 F3/ 4C/ 0F 2C DA cvttss2si r11, xmm2 \n"
" 00009797 F2/ 4C/ 0F 2C DA cvttsd2si r11, xmm2 \n"
" \n"
" 0000979C F3/ 49/ 0F 2A D3 cvtsi2ss xmm2, r11 \n"
" 000097A1 F2/ 49/ 0F 2A D3 cvtsi2sd xmm2, r11 \n"
" \n"
" \n"
" ; Between: xmm2 and r12 \n"
" 000097A6 F3/ 41/ 0F 11 54 movss dword ptr [r12 - 4], xmm2 \n"
" 24 FC \n"
" 000097AD F2/ 41/ 0F 11 54 movsd qword ptr [r12 + 4], xmm2 \n"
" 24 04 \n"
" \n"
" 000097B4 F3/ 41/ 0F 10 54 movss xmm2, dword ptr [r12 - 4] \n"
" 24 FC \n"
" 000097BB F2/ 41/ 0F 10 54 movsd xmm2, qword ptr [r12 + 4] \n"
" 24 04 \n"
" 000097C2 F3/ 49/ 0F 2A 54 cvtsi2ss xmm2, qword ptr [r12 - 4] \n"
" 24 FC \n"
" 000097C9 F2/ 41/ 0F 2A 54 cvtsi2sd xmm2, dword ptr [r12 + 4] \n"
" 24 04 \n"
" \n"
" 000097D0 F3/ 44/ 0F 2C E2 cvttss2si r12d, xmm2 \n"
" 000097D5 F2/ 44/ 0F 2C E2 cvttsd2si r12d, xmm2 \n"
" \n"
" 000097DA F3/ 41/ 0F 2A D4 cvtsi2ss xmm2, r12d \n"
" 000097DF F2/ 41/ 0F 2A D4 cvtsi2sd xmm2, r12d \n"
" \n"
" 000097E4 F3/ 4C/ 0F 2C E2 cvttss2si r12, xmm2 \n"
" 000097E9 F2/ 4C/ 0F 2C E2 cvttsd2si r12, xmm2 \n"
" \n"
" 000097EE F3/ 49/ 0F 2A D4 cvtsi2ss xmm2, r12 \n"
" 000097F3 F2/ 49/ 0F 2A D4 cvtsi2sd xmm2, r12 \n"
" \n"
" \n"
" ; Between: xmm2 and r13 \n"
" 000097F8 F3/ 41/ 0F 11 55 movss dword ptr [r13 - 4], xmm2 \n"
" FC \n"
" 000097FE F2/ 41/ 0F 11 55 movsd qword ptr [r13 + 4], xmm2 \n"
" 04 \n"
" \n"
" 00009804 F3/ 41/ 0F 10 55 movss xmm2, dword ptr [r13 - 4] \n"
" FC \n"
" 0000980A F2/ 41/ 0F 10 55 movsd xmm2, qword ptr [r13 + 4] \n"
" 04 \n"
" 00009810 F3/ 49/ 0F 2A 55 cvtsi2ss xmm2, qword ptr [r13 - 4] \n"
" FC \n"
" 00009816 F2/ 41/ 0F 2A 55 cvtsi2sd xmm2, dword ptr [r13 + 4] \n"
" 04 \n"
" \n"
" 0000981C F3/ 44/ 0F 2C EA cvttss2si r13d, xmm2 \n"
" 00009821 F2/ 44/ 0F 2C EA cvttsd2si r13d, xmm2 \n"
" \n"
" 00009826 F3/ 41/ 0F 2A D5 cvtsi2ss xmm2, r13d \n"
" 0000982B F2/ 41/ 0F 2A D5 cvtsi2sd xmm2, r13d \n"
" \n"
" 00009830 F3/ 4C/ 0F 2C EA cvttss2si r13, xmm2 \n"
" 00009835 F2/ 4C/ 0F 2C EA cvttsd2si r13, xmm2 \n"
" \n"
" 0000983A F3/ 49/ 0F 2A D5 cvtsi2ss xmm2, r13 \n"
" 0000983F F2/ 49/ 0F 2A D5 cvtsi2sd xmm2, r13 \n"
" \n"
" \n"
" ; Between: xmm2 and r14 \n"
" 00009844 F3/ 41/ 0F 11 56 movss dword ptr [r14 - 4], xmm2 \n"
" FC \n"
" 0000984A F2/ 41/ 0F 11 56 movsd qword ptr [r14 + 4], xmm2 \n"
" 04 \n"
" \n"
" 00009850 F3/ 41/ 0F 10 56 movss xmm2, dword ptr [r14 - 4] \n"
" FC \n"
" 00009856 F2/ 41/ 0F 10 56 movsd xmm2, qword ptr [r14 + 4] \n"
" 04 \n"
" 0000985C F3/ 49/ 0F 2A 56 cvtsi2ss xmm2, qword ptr [r14 - 4] \n"
" FC \n"
" 00009862 F2/ 41/ 0F 2A 56 cvtsi2sd xmm2, dword ptr [r14 + 4] \n"
" 04 \n"
" \n"
" 00009868 F3/ 44/ 0F 2C F2 cvttss2si r14d, xmm2 \n"
" 0000986D F2/ 44/ 0F 2C F2 cvttsd2si r14d, xmm2 \n"
" \n"
" 00009872 F3/ 41/ 0F 2A D6 cvtsi2ss xmm2, r14d \n"
" 00009877 F2/ 41/ 0F 2A D6 cvtsi2sd xmm2, r14d \n"
" \n"
" 0000987C F3/ 4C/ 0F 2C F2 cvttss2si r14, xmm2 \n"
" 00009881 F2/ 4C/ 0F 2C F2 cvttsd2si r14, xmm2 \n"
" \n"
" 00009886 F3/ 49/ 0F 2A D6 cvtsi2ss xmm2, r14 \n"
" 0000988B F2/ 49/ 0F 2A D6 cvtsi2sd xmm2, r14 \n"
" \n"
" \n"
" ; Between: xmm2 and r15 \n"
" 00009890 F3/ 41/ 0F 11 57 movss dword ptr [r15 - 4], xmm2 \n"
" FC \n"
" 00009896 F2/ 41/ 0F 11 57 movsd qword ptr [r15 + 4], xmm2 \n"
" 04 \n"
" \n"
" 0000989C F3/ 41/ 0F 10 57 movss xmm2, dword ptr [r15 - 4] \n"
" FC \n"
" 000098A2 F2/ 41/ 0F 10 57 movsd xmm2, qword ptr [r15 + 4] \n"
" 04 \n"
" 000098A8 F3/ 49/ 0F 2A 57 cvtsi2ss xmm2, qword ptr [r15 - 4] \n"
" FC \n"
" 000098AE F2/ 41/ 0F 2A 57 cvtsi2sd xmm2, dword ptr [r15 + 4] \n"
" 04 \n"
" \n"
" 000098B4 F3/ 44/ 0F 2C FA cvttss2si r15d, xmm2 \n"
" 000098B9 F2/ 44/ 0F 2C FA cvttsd2si r15d, xmm2 \n"
" \n"
" 000098BE F3/ 41/ 0F 2A D7 cvtsi2ss xmm2, r15d \n"
" 000098C3 F2/ 41/ 0F 2A D7 cvtsi2sd xmm2, r15d \n"
" \n"
" 000098C8 F3/ 4C/ 0F 2C FA cvttss2si r15, xmm2 \n"
" 000098CD F2/ 4C/ 0F 2C FA cvttsd2si r15, xmm2 \n"
" \n"
" 000098D2 F3/ 49/ 0F 2A D7 cvtsi2ss xmm2, r15 \n"
" 000098D7 F2/ 49/ 0F 2A D7 cvtsi2sd xmm2, r15 \n"
" \n"
" \n"
" ; Between: xmm3 and rax \n"
" 000098DC F3/ 0F 11 58 movss dword ptr [rax - 4], xmm3 \n"
" FC \n"
" 000098E1 F2/ 0F 11 58 movsd qword ptr [rax + 4], xmm3 \n"
" 04 \n"
" \n"
" 000098E6 F3/ 0F 10 58 movss xmm3, dword ptr [rax - 4] \n"
" FC \n"
" 000098EB F2/ 0F 10 58 movsd xmm3, qword ptr [rax + 4] \n"
" 04 \n"
" 000098F0 F3/ 48/ 0F 2A 58 cvtsi2ss xmm3, qword ptr [rax - 4] \n"
" FC \n"
" 000098F6 F2/ 0F 2A 58 cvtsi2sd xmm3, dword ptr [rax + 4] \n"
" 04 \n"
" \n"
" 000098FB F3/ 0F 2C C3 cvttss2si eax, xmm3 \n"
" 000098FF F2/ 0F 2C C3 cvttsd2si eax, xmm3 \n"
" \n"
" 00009903 F3/ 0F 2A D8 cvtsi2ss xmm3, eax \n"
" 00009907 F2/ 0F 2A D8 cvtsi2sd xmm3, eax \n"
" \n"
" 0000990B F3/ 48/ 0F 2C C3 cvttss2si rax, xmm3 \n"
" 00009910 F2/ 48/ 0F 2C C3 cvttsd2si rax, xmm3 \n"
" \n"
" 00009915 F3/ 48/ 0F 2A D8 cvtsi2ss xmm3, rax \n"
" 0000991A F2/ 48/ 0F 2A D8 cvtsi2sd xmm3, rax \n"
" \n"
" \n"
" ; Between: xmm3 and rcx \n"
" 0000991F F3/ 0F 11 59 movss dword ptr [rcx - 4], xmm3 \n"
" FC \n"
" 00009924 F2/ 0F 11 59 movsd qword ptr [rcx + 4], xmm3 \n"
" 04 \n"
" \n"
" 00009929 F3/ 0F 10 59 movss xmm3, dword ptr [rcx - 4] \n"
" FC \n"
" 0000992E F2/ 0F 10 59 movsd xmm3, qword ptr [rcx + 4] \n"
" 04 \n"
" 00009933 F3/ 48/ 0F 2A 59 cvtsi2ss xmm3, qword ptr [rcx - 4] \n"
" FC \n"
" 00009939 F2/ 0F 2A 59 cvtsi2sd xmm3, dword ptr [rcx + 4] \n"
" 04 \n"
" \n"
" 0000993E F3/ 0F 2C CB cvttss2si ecx, xmm3 \n"
" 00009942 F2/ 0F 2C CB cvttsd2si ecx, xmm3 \n"
" \n"
" 00009946 F3/ 0F 2A D9 cvtsi2ss xmm3, ecx \n"
" 0000994A F2/ 0F 2A D9 cvtsi2sd xmm3, ecx \n"
" \n"
" 0000994E F3/ 48/ 0F 2C CB cvttss2si rcx, xmm3 \n"
" 00009953 F2/ 48/ 0F 2C CB cvttsd2si rcx, xmm3 \n"
" \n"
" 00009958 F3/ 48/ 0F 2A D9 cvtsi2ss xmm3, rcx \n"
" 0000995D F2/ 48/ 0F 2A D9 cvtsi2sd xmm3, rcx \n"
" \n"
" \n"
" ; Between: xmm3 and rdx \n"
" 00009962 F3/ 0F 11 5A movss dword ptr [rdx - 4], xmm3 \n"
" FC \n"
" 00009967 F2/ 0F 11 5A movsd qword ptr [rdx + 4], xmm3 \n"
" 04 \n"
" \n"
" 0000996C F3/ 0F 10 5A movss xmm3, dword ptr [rdx - 4] \n"
" FC \n"
" 00009971 F2/ 0F 10 5A movsd xmm3, qword ptr [rdx + 4] \n"
" 04 \n"
" 00009976 F3/ 48/ 0F 2A 5A cvtsi2ss xmm3, qword ptr [rdx - 4] \n"
" FC \n"
" 0000997C F2/ 0F 2A 5A cvtsi2sd xmm3, dword ptr [rdx + 4] \n"
" 04 \n"
" \n"
" 00009981 F3/ 0F 2C D3 cvttss2si edx, xmm3 \n"
" 00009985 F2/ 0F 2C D3 cvttsd2si edx, xmm3 \n"
" \n"
" 00009989 F3/ 0F 2A DA cvtsi2ss xmm3, edx \n"
" 0000998D F2/ 0F 2A DA cvtsi2sd xmm3, edx \n"
" \n"
" 00009991 F3/ 48/ 0F 2C D3 cvttss2si rdx, xmm3 \n"
" 00009996 F2/ 48/ 0F 2C D3 cvttsd2si rdx, xmm3 \n"
" \n"
" 0000999B F3/ 48/ 0F 2A DA cvtsi2ss xmm3, rdx \n"
" 000099A0 F2/ 48/ 0F 2A DA cvtsi2sd xmm3, rdx \n"
" \n"
" \n"
" ; Between: xmm3 and rbx \n"
" 000099A5 F3/ 0F 11 5B movss dword ptr [rbx - 4], xmm3 \n"
" FC \n"
" 000099AA F2/ 0F 11 5B movsd qword ptr [rbx + 4], xmm3 \n"
" 04 \n"
" \n"
" 000099AF F3/ 0F 10 5B movss xmm3, dword ptr [rbx - 4] \n"
" FC \n"
" 000099B4 F2/ 0F 10 5B movsd xmm3, qword ptr [rbx + 4] \n"
" 04 \n"
" 000099B9 F3/ 48/ 0F 2A 5B cvtsi2ss xmm3, qword ptr [rbx - 4] \n"
" FC \n"
" 000099BF F2/ 0F 2A 5B cvtsi2sd xmm3, dword ptr [rbx + 4] \n"
" 04 \n"
" \n"
" 000099C4 F3/ 0F 2C DB cvttss2si ebx, xmm3 \n"
" 000099C8 F2/ 0F 2C DB cvttsd2si ebx, xmm3 \n"
" \n"
" 000099CC F3/ 0F 2A DB cvtsi2ss xmm3, ebx \n"
" 000099D0 F2/ 0F 2A DB cvtsi2sd xmm3, ebx \n"
" \n"
" 000099D4 F3/ 48/ 0F 2C DB cvttss2si rbx, xmm3 \n"
" 000099D9 F2/ 48/ 0F 2C DB cvttsd2si rbx, xmm3 \n"
" \n"
" 000099DE F3/ 48/ 0F 2A DB cvtsi2ss xmm3, rbx \n"
" 000099E3 F2/ 48/ 0F 2A DB cvtsi2sd xmm3, rbx \n"
" \n"
" \n"
" ; Between: xmm3 and rsp \n"
" 000099E8 F3/ 0F 11 5C 24 movss dword ptr [rsp - 4], xmm3 \n"
" FC \n"
" 000099EE F2/ 0F 11 5C 24 movsd qword ptr [rsp + 4], xmm3 \n"
" 04 \n"
" \n"
" 000099F4 F3/ 0F 10 5C 24 movss xmm3, dword ptr [rsp - 4] \n"
" FC \n"
" 000099FA F2/ 0F 10 5C 24 movsd xmm3, qword ptr [rsp + 4] \n"
" 04 \n"
" 00009A00 F3/ 48/ 0F 2A 5C cvtsi2ss xmm3, qword ptr [rsp - 4] \n"
" 24 FC \n"
" 00009A07 F2/ 0F 2A 5C 24 cvtsi2sd xmm3, dword ptr [rsp + 4] \n"
" 04 \n"
" \n"
" 00009A0D F3/ 0F 2C E3 cvttss2si esp, xmm3 \n"
" 00009A11 F2/ 0F 2C E3 cvttsd2si esp, xmm3 \n"
" \n"
" 00009A15 F3/ 0F 2A DC cvtsi2ss xmm3, esp \n"
" 00009A19 F2/ 0F 2A DC cvtsi2sd xmm3, esp \n"
" \n"
" 00009A1D F3/ 48/ 0F 2C E3 cvttss2si rsp, xmm3 \n"
" 00009A22 F2/ 48/ 0F 2C E3 cvttsd2si rsp, xmm3 \n"
" \n"
" 00009A27 F3/ 48/ 0F 2A DC cvtsi2ss xmm3, rsp \n"
" 00009A2C F2/ 48/ 0F 2A DC cvtsi2sd xmm3, rsp \n"
" \n"
" \n"
" ; Between: xmm3 and rbp \n"
" 00009A31 F3/ 0F 11 5D movss dword ptr [rbp - 4], xmm3 \n"
" FC \n"
" 00009A36 F2/ 0F 11 5D movsd qword ptr [rbp + 4], xmm3 \n"
" 04 \n"
" \n"
" 00009A3B F3/ 0F 10 5D movss xmm3, dword ptr [rbp - 4] \n"
" FC \n"
" 00009A40 F2/ 0F 10 5D movsd xmm3, qword ptr [rbp + 4] \n"
" 04 \n"
" 00009A45 F3/ 48/ 0F 2A 5D cvtsi2ss xmm3, qword ptr [rbp - 4] \n"
" FC \n"
" 00009A4B F2/ 0F 2A 5D cvtsi2sd xmm3, dword ptr [rbp + 4] \n"
" 04 \n"
" \n"
" 00009A50 F3/ 0F 2C EB cvttss2si ebp, xmm3 \n"
" 00009A54 F2/ 0F 2C EB cvttsd2si ebp, xmm3 \n"
" \n"
" 00009A58 F3/ 0F 2A DD cvtsi2ss xmm3, ebp \n"
" 00009A5C F2/ 0F 2A DD cvtsi2sd xmm3, ebp \n"
" \n"
" 00009A60 F3/ 48/ 0F 2C EB cvttss2si rbp, xmm3 \n"
" 00009A65 F2/ 48/ 0F 2C EB cvttsd2si rbp, xmm3 \n"
" \n"
" 00009A6A F3/ 48/ 0F 2A DD cvtsi2ss xmm3, rbp \n"
" 00009A6F F2/ 48/ 0F 2A DD cvtsi2sd xmm3, rbp \n"
" \n"
" \n"
" ; Between: xmm3 and rsi \n"
" 00009A74 F3/ 0F 11 5E movss dword ptr [rsi - 4], xmm3 \n"
" FC \n"
" 00009A79 F2/ 0F 11 5E movsd qword ptr [rsi + 4], xmm3 \n"
" 04 \n"
" \n"
" 00009A7E F3/ 0F 10 5E movss xmm3, dword ptr [rsi - 4] \n"
" FC \n"
" 00009A83 F2/ 0F 10 5E movsd xmm3, qword ptr [rsi + 4] \n"
" 04 \n"
" 00009A88 F3/ 48/ 0F 2A 5E cvtsi2ss xmm3, qword ptr [rsi - 4] \n"
" FC \n"
" 00009A8E F2/ 0F 2A 5E cvtsi2sd xmm3, dword ptr [rsi + 4] \n"
" 04 \n"
" \n"
" 00009A93 F3/ 0F 2C F3 cvttss2si esi, xmm3 \n"
" 00009A97 F2/ 0F 2C F3 cvttsd2si esi, xmm3 \n"
" \n"
" 00009A9B F3/ 0F 2A DE cvtsi2ss xmm3, esi \n"
" 00009A9F F2/ 0F 2A DE cvtsi2sd xmm3, esi \n"
" \n"
" 00009AA3 F3/ 48/ 0F 2C F3 cvttss2si rsi, xmm3 \n"
" 00009AA8 F2/ 48/ 0F 2C F3 cvttsd2si rsi, xmm3 \n"
" \n"
" 00009AAD F3/ 48/ 0F 2A DE cvtsi2ss xmm3, rsi \n"
" 00009AB2 F2/ 48/ 0F 2A DE cvtsi2sd xmm3, rsi \n"
" \n"
" \n"
" ; Between: xmm3 and rdi \n"
" 00009AB7 F3/ 0F 11 5F movss dword ptr [rdi - 4], xmm3 \n"
" FC \n"
" 00009ABC F2/ 0F 11 5F movsd qword ptr [rdi + 4], xmm3 \n"
" 04 \n"
" \n"
" 00009AC1 F3/ 0F 10 5F movss xmm3, dword ptr [rdi - 4] \n"
" FC \n"
" 00009AC6 F2/ 0F 10 5F movsd xmm3, qword ptr [rdi + 4] \n"
" 04 \n"
" 00009ACB F3/ 48/ 0F 2A 5F cvtsi2ss xmm3, qword ptr [rdi - 4] \n"
" FC \n"
" 00009AD1 F2/ 0F 2A 5F cvtsi2sd xmm3, dword ptr [rdi + 4] \n"
" 04 \n"
" \n"
" 00009AD6 F3/ 0F 2C FB cvttss2si edi, xmm3 \n"
" 00009ADA F2/ 0F 2C FB cvttsd2si edi, xmm3 \n"
" \n"
" 00009ADE F3/ 0F 2A DF cvtsi2ss xmm3, edi \n"
" 00009AE2 F2/ 0F 2A DF cvtsi2sd xmm3, edi \n"
" \n"
" 00009AE6 F3/ 48/ 0F 2C FB cvttss2si rdi, xmm3 \n"
" 00009AEB F2/ 48/ 0F 2C FB cvttsd2si rdi, xmm3 \n"
" \n"
" 00009AF0 F3/ 48/ 0F 2A DF cvtsi2ss xmm3, rdi \n"
" 00009AF5 F2/ 48/ 0F 2A DF cvtsi2sd xmm3, rdi \n"
" \n"
" \n"
" ; Between: xmm3 and r8 \n"
" 00009AFA F3/ 41/ 0F 11 58 movss dword ptr [r8 - 4], xmm3 \n"
" FC \n"
" 00009B00 F2/ 41/ 0F 11 58 movsd qword ptr [r8 + 4], xmm3 \n"
" 04 \n"
" \n"
" 00009B06 F3/ 41/ 0F 10 58 movss xmm3, dword ptr [r8 - 4] \n"
" FC \n"
" 00009B0C F2/ 41/ 0F 10 58 movsd xmm3, qword ptr [r8 + 4] \n"
" 04 \n";
ml64Output +=
" 00009B12 F3/ 49/ 0F 2A 58 cvtsi2ss xmm3, qword ptr [r8 - 4] \n"
" FC \n"
" 00009B18 F2/ 41/ 0F 2A 58 cvtsi2sd xmm3, dword ptr [r8 + 4] \n"
" 04 \n"
" \n"
" 00009B1E F3/ 44/ 0F 2C C3 cvttss2si r8d, xmm3 \n"
" 00009B23 F2/ 44/ 0F 2C C3 cvttsd2si r8d, xmm3 \n"
" \n"
" 00009B28 F3/ 41/ 0F 2A D8 cvtsi2ss xmm3, r8d \n"
" 00009B2D F2/ 41/ 0F 2A D8 cvtsi2sd xmm3, r8d \n"
" \n"
" 00009B32 F3/ 4C/ 0F 2C C3 cvttss2si r8, xmm3 \n"
" 00009B37 F2/ 4C/ 0F 2C C3 cvttsd2si r8, xmm3 \n"
" \n"
" 00009B3C F3/ 49/ 0F 2A D8 cvtsi2ss xmm3, r8 \n"
" 00009B41 F2/ 49/ 0F 2A D8 cvtsi2sd xmm3, r8 \n"
" \n"
" \n"
" ; Between: xmm3 and r9 \n"
" 00009B46 F3/ 41/ 0F 11 59 movss dword ptr [r9 - 4], xmm3 \n"
" FC \n"
" 00009B4C F2/ 41/ 0F 11 59 movsd qword ptr [r9 + 4], xmm3 \n"
" 04 \n"
" \n"
" 00009B52 F3/ 41/ 0F 10 59 movss xmm3, dword ptr [r9 - 4] \n"
" FC \n"
" 00009B58 F2/ 41/ 0F 10 59 movsd xmm3, qword ptr [r9 + 4] \n"
" 04 \n"
" 00009B5E F3/ 49/ 0F 2A 59 cvtsi2ss xmm3, qword ptr [r9 - 4] \n"
" FC \n"
" 00009B64 F2/ 41/ 0F 2A 59 cvtsi2sd xmm3, dword ptr [r9 + 4] \n"
" 04 \n"
" \n"
" 00009B6A F3/ 44/ 0F 2C CB cvttss2si r9d, xmm3 \n"
" 00009B6F F2/ 44/ 0F 2C CB cvttsd2si r9d, xmm3 \n"
" \n"
" 00009B74 F3/ 41/ 0F 2A D9 cvtsi2ss xmm3, r9d \n"
" 00009B79 F2/ 41/ 0F 2A D9 cvtsi2sd xmm3, r9d \n"
" \n"
" 00009B7E F3/ 4C/ 0F 2C CB cvttss2si r9, xmm3 \n"
" 00009B83 F2/ 4C/ 0F 2C CB cvttsd2si r9, xmm3 \n"
" \n"
" 00009B88 F3/ 49/ 0F 2A D9 cvtsi2ss xmm3, r9 \n"
" 00009B8D F2/ 49/ 0F 2A D9 cvtsi2sd xmm3, r9 \n"
" \n"
" \n"
" ; Between: xmm3 and r10 \n"
" 00009B92 F3/ 41/ 0F 11 5A movss dword ptr [r10 - 4], xmm3 \n"
" FC \n"
" 00009B98 F2/ 41/ 0F 11 5A movsd qword ptr [r10 + 4], xmm3 \n"
" 04 \n"
" \n"
" 00009B9E F3/ 41/ 0F 10 5A movss xmm3, dword ptr [r10 - 4] \n"
" FC \n"
" 00009BA4 F2/ 41/ 0F 10 5A movsd xmm3, qword ptr [r10 + 4] \n"
" 04 \n"
" 00009BAA F3/ 49/ 0F 2A 5A cvtsi2ss xmm3, qword ptr [r10 - 4] \n"
" FC \n"
" 00009BB0 F2/ 41/ 0F 2A 5A cvtsi2sd xmm3, dword ptr [r10 + 4] \n"
" 04 \n"
" \n"
" 00009BB6 F3/ 44/ 0F 2C D3 cvttss2si r10d, xmm3 \n"
" 00009BBB F2/ 44/ 0F 2C D3 cvttsd2si r10d, xmm3 \n"
" \n"
" 00009BC0 F3/ 41/ 0F 2A DA cvtsi2ss xmm3, r10d \n"
" 00009BC5 F2/ 41/ 0F 2A DA cvtsi2sd xmm3, r10d \n"
" \n"
" 00009BCA F3/ 4C/ 0F 2C D3 cvttss2si r10, xmm3 \n"
" 00009BCF F2/ 4C/ 0F 2C D3 cvttsd2si r10, xmm3 \n"
" \n"
" 00009BD4 F3/ 49/ 0F 2A DA cvtsi2ss xmm3, r10 \n"
" 00009BD9 F2/ 49/ 0F 2A DA cvtsi2sd xmm3, r10 \n"
" \n"
" \n"
" ; Between: xmm3 and r11 \n"
" 00009BDE F3/ 41/ 0F 11 5B movss dword ptr [r11 - 4], xmm3 \n"
" FC \n"
" 00009BE4 F2/ 41/ 0F 11 5B movsd qword ptr [r11 + 4], xmm3 \n"
" 04 \n"
" \n"
" 00009BEA F3/ 41/ 0F 10 5B movss xmm3, dword ptr [r11 - 4] \n"
" FC \n"
" 00009BF0 F2/ 41/ 0F 10 5B movsd xmm3, qword ptr [r11 + 4] \n"
" 04 \n"
" 00009BF6 F3/ 49/ 0F 2A 5B cvtsi2ss xmm3, qword ptr [r11 - 4] \n"
" FC \n"
" 00009BFC F2/ 41/ 0F 2A 5B cvtsi2sd xmm3, dword ptr [r11 + 4] \n"
" 04 \n"
" \n"
" 00009C02 F3/ 44/ 0F 2C DB cvttss2si r11d, xmm3 \n"
" 00009C07 F2/ 44/ 0F 2C DB cvttsd2si r11d, xmm3 \n"
" \n"
" 00009C0C F3/ 41/ 0F 2A DB cvtsi2ss xmm3, r11d \n"
" 00009C11 F2/ 41/ 0F 2A DB cvtsi2sd xmm3, r11d \n"
" \n"
" 00009C16 F3/ 4C/ 0F 2C DB cvttss2si r11, xmm3 \n"
" 00009C1B F2/ 4C/ 0F 2C DB cvttsd2si r11, xmm3 \n"
" \n"
" 00009C20 F3/ 49/ 0F 2A DB cvtsi2ss xmm3, r11 \n"
" 00009C25 F2/ 49/ 0F 2A DB cvtsi2sd xmm3, r11 \n"
" \n"
" \n"
" ; Between: xmm3 and r12 \n"
" 00009C2A F3/ 41/ 0F 11 5C movss dword ptr [r12 - 4], xmm3 \n"
" 24 FC \n"
" 00009C31 F2/ 41/ 0F 11 5C movsd qword ptr [r12 + 4], xmm3 \n"
" 24 04 \n"
" \n"
" 00009C38 F3/ 41/ 0F 10 5C movss xmm3, dword ptr [r12 - 4] \n"
" 24 FC \n"
" 00009C3F F2/ 41/ 0F 10 5C movsd xmm3, qword ptr [r12 + 4] \n"
" 24 04 \n"
" 00009C46 F3/ 49/ 0F 2A 5C cvtsi2ss xmm3, qword ptr [r12 - 4] \n"
" 24 FC \n"
" 00009C4D F2/ 41/ 0F 2A 5C cvtsi2sd xmm3, dword ptr [r12 + 4] \n"
" 24 04 \n"
" \n"
" 00009C54 F3/ 44/ 0F 2C E3 cvttss2si r12d, xmm3 \n"
" 00009C59 F2/ 44/ 0F 2C E3 cvttsd2si r12d, xmm3 \n"
" \n"
" 00009C5E F3/ 41/ 0F 2A DC cvtsi2ss xmm3, r12d \n"
" 00009C63 F2/ 41/ 0F 2A DC cvtsi2sd xmm3, r12d \n"
" \n"
" 00009C68 F3/ 4C/ 0F 2C E3 cvttss2si r12, xmm3 \n"
" 00009C6D F2/ 4C/ 0F 2C E3 cvttsd2si r12, xmm3 \n"
" \n"
" 00009C72 F3/ 49/ 0F 2A DC cvtsi2ss xmm3, r12 \n"
" 00009C77 F2/ 49/ 0F 2A DC cvtsi2sd xmm3, r12 \n"
" \n"
" \n"
" ; Between: xmm3 and r13 \n"
" 00009C7C F3/ 41/ 0F 11 5D movss dword ptr [r13 - 4], xmm3 \n"
" FC \n"
" 00009C82 F2/ 41/ 0F 11 5D movsd qword ptr [r13 + 4], xmm3 \n"
" 04 \n"
" \n"
" 00009C88 F3/ 41/ 0F 10 5D movss xmm3, dword ptr [r13 - 4] \n"
" FC \n"
" 00009C8E F2/ 41/ 0F 10 5D movsd xmm3, qword ptr [r13 + 4] \n"
" 04 \n"
" 00009C94 F3/ 49/ 0F 2A 5D cvtsi2ss xmm3, qword ptr [r13 - 4] \n"
" FC \n"
" 00009C9A F2/ 41/ 0F 2A 5D cvtsi2sd xmm3, dword ptr [r13 + 4] \n"
" 04 \n"
" \n"
" 00009CA0 F3/ 44/ 0F 2C EB cvttss2si r13d, xmm3 \n"
" 00009CA5 F2/ 44/ 0F 2C EB cvttsd2si r13d, xmm3 \n"
" \n"
" 00009CAA F3/ 41/ 0F 2A DD cvtsi2ss xmm3, r13d \n"
" 00009CAF F2/ 41/ 0F 2A DD cvtsi2sd xmm3, r13d \n"
" \n"
" 00009CB4 F3/ 4C/ 0F 2C EB cvttss2si r13, xmm3 \n"
" 00009CB9 F2/ 4C/ 0F 2C EB cvttsd2si r13, xmm3 \n"
" \n"
" 00009CBE F3/ 49/ 0F 2A DD cvtsi2ss xmm3, r13 \n"
" 00009CC3 F2/ 49/ 0F 2A DD cvtsi2sd xmm3, r13 \n"
" \n"
" \n"
" ; Between: xmm3 and r14 \n"
" 00009CC8 F3/ 41/ 0F 11 5E movss dword ptr [r14 - 4], xmm3 \n"
" FC \n"
" 00009CCE F2/ 41/ 0F 11 5E movsd qword ptr [r14 + 4], xmm3 \n"
" 04 \n"
" \n"
" 00009CD4 F3/ 41/ 0F 10 5E movss xmm3, dword ptr [r14 - 4] \n"
" FC \n"
" 00009CDA F2/ 41/ 0F 10 5E movsd xmm3, qword ptr [r14 + 4] \n"
" 04 \n"
" 00009CE0 F3/ 49/ 0F 2A 5E cvtsi2ss xmm3, qword ptr [r14 - 4] \n"
" FC \n"
" 00009CE6 F2/ 41/ 0F 2A 5E cvtsi2sd xmm3, dword ptr [r14 + 4] \n"
" 04 \n"
" \n"
" 00009CEC F3/ 44/ 0F 2C F3 cvttss2si r14d, xmm3 \n"
" 00009CF1 F2/ 44/ 0F 2C F3 cvttsd2si r14d, xmm3 \n"
" \n"
" 00009CF6 F3/ 41/ 0F 2A DE cvtsi2ss xmm3, r14d \n"
" 00009CFB F2/ 41/ 0F 2A DE cvtsi2sd xmm3, r14d \n"
" \n"
" 00009D00 F3/ 4C/ 0F 2C F3 cvttss2si r14, xmm3 \n"
" 00009D05 F2/ 4C/ 0F 2C F3 cvttsd2si r14, xmm3 \n"
" \n"
" 00009D0A F3/ 49/ 0F 2A DE cvtsi2ss xmm3, r14 \n"
" 00009D0F F2/ 49/ 0F 2A DE cvtsi2sd xmm3, r14 \n"
" \n"
" \n"
" ; Between: xmm3 and r15 \n"
" 00009D14 F3/ 41/ 0F 11 5F movss dword ptr [r15 - 4], xmm3 \n"
" FC \n"
" 00009D1A F2/ 41/ 0F 11 5F movsd qword ptr [r15 + 4], xmm3 \n"
" 04 \n"
" \n"
" 00009D20 F3/ 41/ 0F 10 5F movss xmm3, dword ptr [r15 - 4] \n"
" FC \n"
" 00009D26 F2/ 41/ 0F 10 5F movsd xmm3, qword ptr [r15 + 4] \n"
" 04 \n"
" 00009D2C F3/ 49/ 0F 2A 5F cvtsi2ss xmm3, qword ptr [r15 - 4] \n"
" FC \n"
" 00009D32 F2/ 41/ 0F 2A 5F cvtsi2sd xmm3, dword ptr [r15 + 4] \n"
" 04 \n"
" \n"
" 00009D38 F3/ 44/ 0F 2C FB cvttss2si r15d, xmm3 \n"
" 00009D3D F2/ 44/ 0F 2C FB cvttsd2si r15d, xmm3 \n"
" \n"
" 00009D42 F3/ 41/ 0F 2A DF cvtsi2ss xmm3, r15d \n"
" 00009D47 F2/ 41/ 0F 2A DF cvtsi2sd xmm3, r15d \n"
" \n"
" 00009D4C F3/ 4C/ 0F 2C FB cvttss2si r15, xmm3 \n"
" 00009D51 F2/ 4C/ 0F 2C FB cvttsd2si r15, xmm3 \n"
" \n"
" 00009D56 F3/ 49/ 0F 2A DF cvtsi2ss xmm3, r15 \n"
" 00009D5B F2/ 49/ 0F 2A DF cvtsi2sd xmm3, r15 \n"
" \n"
" \n"
" ; Between: xmm4 and rax \n"
" 00009D60 F3/ 0F 11 60 movss dword ptr [rax - 4], xmm4 \n"
" FC \n"
" 00009D65 F2/ 0F 11 60 movsd qword ptr [rax + 4], xmm4 \n"
" 04 \n"
" \n"
" 00009D6A F3/ 0F 10 60 movss xmm4, dword ptr [rax - 4] \n"
" FC \n"
" 00009D6F F2/ 0F 10 60 movsd xmm4, qword ptr [rax + 4] \n"
" 04 \n"
" 00009D74 F3/ 48/ 0F 2A 60 cvtsi2ss xmm4, qword ptr [rax - 4] \n"
" FC \n"
" 00009D7A F2/ 0F 2A 60 cvtsi2sd xmm4, dword ptr [rax + 4] \n"
" 04 \n"
" \n"
" 00009D7F F3/ 0F 2C C4 cvttss2si eax, xmm4 \n"
" 00009D83 F2/ 0F 2C C4 cvttsd2si eax, xmm4 \n"
" \n"
" 00009D87 F3/ 0F 2A E0 cvtsi2ss xmm4, eax \n"
" 00009D8B F2/ 0F 2A E0 cvtsi2sd xmm4, eax \n"
" \n"
" 00009D8F F3/ 48/ 0F 2C C4 cvttss2si rax, xmm4 \n"
" 00009D94 F2/ 48/ 0F 2C C4 cvttsd2si rax, xmm4 \n"
" \n"
" 00009D99 F3/ 48/ 0F 2A E0 cvtsi2ss xmm4, rax \n"
" 00009D9E F2/ 48/ 0F 2A E0 cvtsi2sd xmm4, rax \n"
" \n"
" \n"
" ; Between: xmm4 and rcx \n"
" 00009DA3 F3/ 0F 11 61 movss dword ptr [rcx - 4], xmm4 \n"
" FC \n"
" 00009DA8 F2/ 0F 11 61 movsd qword ptr [rcx + 4], xmm4 \n"
" 04 \n"
" \n"
" 00009DAD F3/ 0F 10 61 movss xmm4, dword ptr [rcx - 4] \n"
" FC \n"
" 00009DB2 F2/ 0F 10 61 movsd xmm4, qword ptr [rcx + 4] \n"
" 04 \n"
" 00009DB7 F3/ 48/ 0F 2A 61 cvtsi2ss xmm4, qword ptr [rcx - 4] \n"
" FC \n"
" 00009DBD F2/ 0F 2A 61 cvtsi2sd xmm4, dword ptr [rcx + 4] \n"
" 04 \n"
" \n"
" 00009DC2 F3/ 0F 2C CC cvttss2si ecx, xmm4 \n"
" 00009DC6 F2/ 0F 2C CC cvttsd2si ecx, xmm4 \n"
" \n"
" 00009DCA F3/ 0F 2A E1 cvtsi2ss xmm4, ecx \n"
" 00009DCE F2/ 0F 2A E1 cvtsi2sd xmm4, ecx \n"
" \n"
" 00009DD2 F3/ 48/ 0F 2C CC cvttss2si rcx, xmm4 \n"
" 00009DD7 F2/ 48/ 0F 2C CC cvttsd2si rcx, xmm4 \n"
" \n"
" 00009DDC F3/ 48/ 0F 2A E1 cvtsi2ss xmm4, rcx \n"
" 00009DE1 F2/ 48/ 0F 2A E1 cvtsi2sd xmm4, rcx \n"
" \n"
" \n"
" ; Between: xmm4 and rdx \n"
" 00009DE6 F3/ 0F 11 62 movss dword ptr [rdx - 4], xmm4 \n"
" FC \n"
" 00009DEB F2/ 0F 11 62 movsd qword ptr [rdx + 4], xmm4 \n"
" 04 \n"
" \n"
" 00009DF0 F3/ 0F 10 62 movss xmm4, dword ptr [rdx - 4] \n"
" FC \n"
" 00009DF5 F2/ 0F 10 62 movsd xmm4, qword ptr [rdx + 4] \n"
" 04 \n"
" 00009DFA F3/ 48/ 0F 2A 62 cvtsi2ss xmm4, qword ptr [rdx - 4] \n"
" FC \n"
" 00009E00 F2/ 0F 2A 62 cvtsi2sd xmm4, dword ptr [rdx + 4] \n"
" 04 \n"
" \n"
" 00009E05 F3/ 0F 2C D4 cvttss2si edx, xmm4 \n"
" 00009E09 F2/ 0F 2C D4 cvttsd2si edx, xmm4 \n"
" \n"
" 00009E0D F3/ 0F 2A E2 cvtsi2ss xmm4, edx \n"
" 00009E11 F2/ 0F 2A E2 cvtsi2sd xmm4, edx \n"
" \n"
" 00009E15 F3/ 48/ 0F 2C D4 cvttss2si rdx, xmm4 \n"
" 00009E1A F2/ 48/ 0F 2C D4 cvttsd2si rdx, xmm4 \n"
" \n"
" 00009E1F F3/ 48/ 0F 2A E2 cvtsi2ss xmm4, rdx \n"
" 00009E24 F2/ 48/ 0F 2A E2 cvtsi2sd xmm4, rdx \n"
" \n"
" \n"
" ; Between: xmm4 and rbx \n"
" 00009E29 F3/ 0F 11 63 movss dword ptr [rbx - 4], xmm4 \n"
" FC \n"
" 00009E2E F2/ 0F 11 63 movsd qword ptr [rbx + 4], xmm4 \n"
" 04 \n"
" \n"
" 00009E33 F3/ 0F 10 63 movss xmm4, dword ptr [rbx - 4] \n"
" FC \n"
" 00009E38 F2/ 0F 10 63 movsd xmm4, qword ptr [rbx + 4] \n"
" 04 \n"
" 00009E3D F3/ 48/ 0F 2A 63 cvtsi2ss xmm4, qword ptr [rbx - 4] \n"
" FC \n"
" 00009E43 F2/ 0F 2A 63 cvtsi2sd xmm4, dword ptr [rbx + 4] \n"
" 04 \n"
" \n"
" 00009E48 F3/ 0F 2C DC cvttss2si ebx, xmm4 \n"
" 00009E4C F2/ 0F 2C DC cvttsd2si ebx, xmm4 \n"
" \n"
" 00009E50 F3/ 0F 2A E3 cvtsi2ss xmm4, ebx \n"
" 00009E54 F2/ 0F 2A E3 cvtsi2sd xmm4, ebx \n"
" \n"
" 00009E58 F3/ 48/ 0F 2C DC cvttss2si rbx, xmm4 \n"
" 00009E5D F2/ 48/ 0F 2C DC cvttsd2si rbx, xmm4 \n"
" \n"
" 00009E62 F3/ 48/ 0F 2A E3 cvtsi2ss xmm4, rbx \n"
" 00009E67 F2/ 48/ 0F 2A E3 cvtsi2sd xmm4, rbx \n"
" \n"
" \n"
" ; Between: xmm4 and rsp \n"
" 00009E6C F3/ 0F 11 64 24 movss dword ptr [rsp - 4], xmm4 \n"
" FC \n"
" 00009E72 F2/ 0F 11 64 24 movsd qword ptr [rsp + 4], xmm4 \n"
" 04 \n"
" \n"
" 00009E78 F3/ 0F 10 64 24 movss xmm4, dword ptr [rsp - 4] \n"
" FC \n"
" 00009E7E F2/ 0F 10 64 24 movsd xmm4, qword ptr [rsp + 4] \n"
" 04 \n"
" 00009E84 F3/ 48/ 0F 2A 64 cvtsi2ss xmm4, qword ptr [rsp - 4] \n"
" 24 FC \n"
" 00009E8B F2/ 0F 2A 64 24 cvtsi2sd xmm4, dword ptr [rsp + 4] \n"
" 04 \n"
" \n"
" 00009E91 F3/ 0F 2C E4 cvttss2si esp, xmm4 \n"
" 00009E95 F2/ 0F 2C E4 cvttsd2si esp, xmm4 \n"
" \n"
" 00009E99 F3/ 0F 2A E4 cvtsi2ss xmm4, esp \n"
" 00009E9D F2/ 0F 2A E4 cvtsi2sd xmm4, esp \n"
" \n"
" 00009EA1 F3/ 48/ 0F 2C E4 cvttss2si rsp, xmm4 \n"
" 00009EA6 F2/ 48/ 0F 2C E4 cvttsd2si rsp, xmm4 \n"
" \n"
" 00009EAB F3/ 48/ 0F 2A E4 cvtsi2ss xmm4, rsp \n"
" 00009EB0 F2/ 48/ 0F 2A E4 cvtsi2sd xmm4, rsp \n"
" \n"
" \n"
" ; Between: xmm4 and rbp \n"
" 00009EB5 F3/ 0F 11 65 movss dword ptr [rbp - 4], xmm4 \n"
" FC \n"
" 00009EBA F2/ 0F 11 65 movsd qword ptr [rbp + 4], xmm4 \n"
" 04 \n"
" \n"
" 00009EBF F3/ 0F 10 65 movss xmm4, dword ptr [rbp - 4] \n"
" FC \n"
" 00009EC4 F2/ 0F 10 65 movsd xmm4, qword ptr [rbp + 4] \n"
" 04 \n"
" 00009EC9 F3/ 48/ 0F 2A 65 cvtsi2ss xmm4, qword ptr [rbp - 4] \n"
" FC \n"
" 00009ECF F2/ 0F 2A 65 cvtsi2sd xmm4, dword ptr [rbp + 4] \n"
" 04 \n"
" \n"
" 00009ED4 F3/ 0F 2C EC cvttss2si ebp, xmm4 \n"
" 00009ED8 F2/ 0F 2C EC cvttsd2si ebp, xmm4 \n"
" \n"
" 00009EDC F3/ 0F 2A E5 cvtsi2ss xmm4, ebp \n"
" 00009EE0 F2/ 0F 2A E5 cvtsi2sd xmm4, ebp \n"
" \n"
" 00009EE4 F3/ 48/ 0F 2C EC cvttss2si rbp, xmm4 \n"
" 00009EE9 F2/ 48/ 0F 2C EC cvttsd2si rbp, xmm4 \n"
" \n"
" 00009EEE F3/ 48/ 0F 2A E5 cvtsi2ss xmm4, rbp \n"
" 00009EF3 F2/ 48/ 0F 2A E5 cvtsi2sd xmm4, rbp \n"
" \n"
" \n"
" ; Between: xmm4 and rsi \n"
" 00009EF8 F3/ 0F 11 66 movss dword ptr [rsi - 4], xmm4 \n"
" FC \n"
" 00009EFD F2/ 0F 11 66 movsd qword ptr [rsi + 4], xmm4 \n"
" 04 \n"
" \n"
" 00009F02 F3/ 0F 10 66 movss xmm4, dword ptr [rsi - 4] \n"
" FC \n"
" 00009F07 F2/ 0F 10 66 movsd xmm4, qword ptr [rsi + 4] \n"
" 04 \n"
" 00009F0C F3/ 48/ 0F 2A 66 cvtsi2ss xmm4, qword ptr [rsi - 4] \n"
" FC \n"
" 00009F12 F2/ 0F 2A 66 cvtsi2sd xmm4, dword ptr [rsi + 4] \n"
" 04 \n"
" \n"
" 00009F17 F3/ 0F 2C F4 cvttss2si esi, xmm4 \n"
" 00009F1B F2/ 0F 2C F4 cvttsd2si esi, xmm4 \n"
" \n"
" 00009F1F F3/ 0F 2A E6 cvtsi2ss xmm4, esi \n"
" 00009F23 F2/ 0F 2A E6 cvtsi2sd xmm4, esi \n"
" \n"
" 00009F27 F3/ 48/ 0F 2C F4 cvttss2si rsi, xmm4 \n"
" 00009F2C F2/ 48/ 0F 2C F4 cvttsd2si rsi, xmm4 \n"
" \n"
" 00009F31 F3/ 48/ 0F 2A E6 cvtsi2ss xmm4, rsi \n"
" 00009F36 F2/ 48/ 0F 2A E6 cvtsi2sd xmm4, rsi \n"
" \n"
" \n"
" ; Between: xmm4 and rdi \n"
" 00009F3B F3/ 0F 11 67 movss dword ptr [rdi - 4], xmm4 \n"
" FC \n"
" 00009F40 F2/ 0F 11 67 movsd qword ptr [rdi + 4], xmm4 \n"
" 04 \n"
" \n"
" 00009F45 F3/ 0F 10 67 movss xmm4, dword ptr [rdi - 4] \n"
" FC \n"
" 00009F4A F2/ 0F 10 67 movsd xmm4, qword ptr [rdi + 4] \n"
" 04 \n"
" 00009F4F F3/ 48/ 0F 2A 67 cvtsi2ss xmm4, qword ptr [rdi - 4] \n"
" FC \n"
" 00009F55 F2/ 0F 2A 67 cvtsi2sd xmm4, dword ptr [rdi + 4] \n"
" 04 \n"
" \n"
" 00009F5A F3/ 0F 2C FC cvttss2si edi, xmm4 \n"
" 00009F5E F2/ 0F 2C FC cvttsd2si edi, xmm4 \n"
" \n"
" 00009F62 F3/ 0F 2A E7 cvtsi2ss xmm4, edi \n"
" 00009F66 F2/ 0F 2A E7 cvtsi2sd xmm4, edi \n"
" \n"
" 00009F6A F3/ 48/ 0F 2C FC cvttss2si rdi, xmm4 \n"
" 00009F6F F2/ 48/ 0F 2C FC cvttsd2si rdi, xmm4 \n"
" \n"
" 00009F74 F3/ 48/ 0F 2A E7 cvtsi2ss xmm4, rdi \n"
" 00009F79 F2/ 48/ 0F 2A E7 cvtsi2sd xmm4, rdi \n"
" \n"
" \n"
" ; Between: xmm4 and r8 \n"
" 00009F7E F3/ 41/ 0F 11 60 movss dword ptr [r8 - 4], xmm4 \n"
" FC \n"
" 00009F84 F2/ 41/ 0F 11 60 movsd qword ptr [r8 + 4], xmm4 \n"
" 04 \n"
" \n"
" 00009F8A F3/ 41/ 0F 10 60 movss xmm4, dword ptr [r8 - 4] \n"
" FC \n"
" 00009F90 F2/ 41/ 0F 10 60 movsd xmm4, qword ptr [r8 + 4] \n"
" 04 \n"
" 00009F96 F3/ 49/ 0F 2A 60 cvtsi2ss xmm4, qword ptr [r8 - 4] \n"
" FC \n"
" 00009F9C F2/ 41/ 0F 2A 60 cvtsi2sd xmm4, dword ptr [r8 + 4] \n"
" 04 \n"
" \n"
" 00009FA2 F3/ 44/ 0F 2C C4 cvttss2si r8d, xmm4 \n"
" 00009FA7 F2/ 44/ 0F 2C C4 cvttsd2si r8d, xmm4 \n"
" \n"
" 00009FAC F3/ 41/ 0F 2A E0 cvtsi2ss xmm4, r8d \n"
" 00009FB1 F2/ 41/ 0F 2A E0 cvtsi2sd xmm4, r8d \n"
" \n"
" 00009FB6 F3/ 4C/ 0F 2C C4 cvttss2si r8, xmm4 \n"
" 00009FBB F2/ 4C/ 0F 2C C4 cvttsd2si r8, xmm4 \n"
" \n"
" 00009FC0 F3/ 49/ 0F 2A E0 cvtsi2ss xmm4, r8 \n"
" 00009FC5 F2/ 49/ 0F 2A E0 cvtsi2sd xmm4, r8 \n"
" \n"
" \n"
" ; Between: xmm4 and r9 \n"
" 00009FCA F3/ 41/ 0F 11 61 movss dword ptr [r9 - 4], xmm4 \n"
" FC \n"
" 00009FD0 F2/ 41/ 0F 11 61 movsd qword ptr [r9 + 4], xmm4 \n"
" 04 \n"
" \n"
" 00009FD6 F3/ 41/ 0F 10 61 movss xmm4, dword ptr [r9 - 4] \n"
" FC \n"
" 00009FDC F2/ 41/ 0F 10 61 movsd xmm4, qword ptr [r9 + 4] \n"
" 04 \n"
" 00009FE2 F3/ 49/ 0F 2A 61 cvtsi2ss xmm4, qword ptr [r9 - 4] \n"
" FC \n"
" 00009FE8 F2/ 41/ 0F 2A 61 cvtsi2sd xmm4, dword ptr [r9 + 4] \n"
" 04 \n"
" \n"
" 00009FEE F3/ 44/ 0F 2C CC cvttss2si r9d, xmm4 \n"
" 00009FF3 F2/ 44/ 0F 2C CC cvttsd2si r9d, xmm4 \n"
" \n"
" 00009FF8 F3/ 41/ 0F 2A E1 cvtsi2ss xmm4, r9d \n"
" 00009FFD F2/ 41/ 0F 2A E1 cvtsi2sd xmm4, r9d \n"
" \n"
" 0000A002 F3/ 4C/ 0F 2C CC cvttss2si r9, xmm4 \n"
" 0000A007 F2/ 4C/ 0F 2C CC cvttsd2si r9, xmm4 \n"
" \n"
" 0000A00C F3/ 49/ 0F 2A E1 cvtsi2ss xmm4, r9 \n"
" 0000A011 F2/ 49/ 0F 2A E1 cvtsi2sd xmm4, r9 \n"
" \n"
" \n"
" ; Between: xmm4 and r10 \n"
" 0000A016 F3/ 41/ 0F 11 62 movss dword ptr [r10 - 4], xmm4 \n"
" FC \n"
" 0000A01C F2/ 41/ 0F 11 62 movsd qword ptr [r10 + 4], xmm4 \n"
" 04 \n"
" \n"
" 0000A022 F3/ 41/ 0F 10 62 movss xmm4, dword ptr [r10 - 4] \n"
" FC \n"
" 0000A028 F2/ 41/ 0F 10 62 movsd xmm4, qword ptr [r10 + 4] \n"
" 04 \n"
" 0000A02E F3/ 49/ 0F 2A 62 cvtsi2ss xmm4, qword ptr [r10 - 4] \n"
" FC \n"
" 0000A034 F2/ 41/ 0F 2A 62 cvtsi2sd xmm4, dword ptr [r10 + 4] \n"
" 04 \n"
" \n"
" 0000A03A F3/ 44/ 0F 2C D4 cvttss2si r10d, xmm4 \n"
" 0000A03F F2/ 44/ 0F 2C D4 cvttsd2si r10d, xmm4 \n"
" \n"
" 0000A044 F3/ 41/ 0F 2A E2 cvtsi2ss xmm4, r10d \n"
" 0000A049 F2/ 41/ 0F 2A E2 cvtsi2sd xmm4, r10d \n"
" \n"
" 0000A04E F3/ 4C/ 0F 2C D4 cvttss2si r10, xmm4 \n"
" 0000A053 F2/ 4C/ 0F 2C D4 cvttsd2si r10, xmm4 \n"
" \n"
" 0000A058 F3/ 49/ 0F 2A E2 cvtsi2ss xmm4, r10 \n"
" 0000A05D F2/ 49/ 0F 2A E2 cvtsi2sd xmm4, r10 \n"
" \n"
" \n"
" ; Between: xmm4 and r11 \n"
" 0000A062 F3/ 41/ 0F 11 63 movss dword ptr [r11 - 4], xmm4 \n"
" FC \n"
" 0000A068 F2/ 41/ 0F 11 63 movsd qword ptr [r11 + 4], xmm4 \n"
" 04 \n"
" \n"
" 0000A06E F3/ 41/ 0F 10 63 movss xmm4, dword ptr [r11 - 4] \n"
" FC \n"
" 0000A074 F2/ 41/ 0F 10 63 movsd xmm4, qword ptr [r11 + 4] \n"
" 04 \n"
" 0000A07A F3/ 49/ 0F 2A 63 cvtsi2ss xmm4, qword ptr [r11 - 4] \n"
" FC \n"
" 0000A080 F2/ 41/ 0F 2A 63 cvtsi2sd xmm4, dword ptr [r11 + 4] \n"
" 04 \n"
" \n"
" 0000A086 F3/ 44/ 0F 2C DC cvttss2si r11d, xmm4 \n"
" 0000A08B F2/ 44/ 0F 2C DC cvttsd2si r11d, xmm4 \n"
" \n"
" 0000A090 F3/ 41/ 0F 2A E3 cvtsi2ss xmm4, r11d \n"
" 0000A095 F2/ 41/ 0F 2A E3 cvtsi2sd xmm4, r11d \n"
" \n"
" 0000A09A F3/ 4C/ 0F 2C DC cvttss2si r11, xmm4 \n"
" 0000A09F F2/ 4C/ 0F 2C DC cvttsd2si r11, xmm4 \n"
" \n"
" 0000A0A4 F3/ 49/ 0F 2A E3 cvtsi2ss xmm4, r11 \n"
" 0000A0A9 F2/ 49/ 0F 2A E3 cvtsi2sd xmm4, r11 \n"
" \n"
" \n";
ml64Output +=
" ; Between: xmm4 and r12 \n"
" 0000A0AE F3/ 41/ 0F 11 64 movss dword ptr [r12 - 4], xmm4 \n"
" 24 FC \n"
" 0000A0B5 F2/ 41/ 0F 11 64 movsd qword ptr [r12 + 4], xmm4 \n"
" 24 04 \n"
" \n"
" 0000A0BC F3/ 41/ 0F 10 64 movss xmm4, dword ptr [r12 - 4] \n"
" 24 FC \n"
" 0000A0C3 F2/ 41/ 0F 10 64 movsd xmm4, qword ptr [r12 + 4] \n"
" 24 04 \n"
" 0000A0CA F3/ 49/ 0F 2A 64 cvtsi2ss xmm4, qword ptr [r12 - 4] \n"
" 24 FC \n"
" 0000A0D1 F2/ 41/ 0F 2A 64 cvtsi2sd xmm4, dword ptr [r12 + 4] \n"
" 24 04 \n"
" \n"
" 0000A0D8 F3/ 44/ 0F 2C E4 cvttss2si r12d, xmm4 \n"
" 0000A0DD F2/ 44/ 0F 2C E4 cvttsd2si r12d, xmm4 \n"
" \n"
" 0000A0E2 F3/ 41/ 0F 2A E4 cvtsi2ss xmm4, r12d \n"
" 0000A0E7 F2/ 41/ 0F 2A E4 cvtsi2sd xmm4, r12d \n"
" \n"
" 0000A0EC F3/ 4C/ 0F 2C E4 cvttss2si r12, xmm4 \n"
" 0000A0F1 F2/ 4C/ 0F 2C E4 cvttsd2si r12, xmm4 \n"
" \n"
" 0000A0F6 F3/ 49/ 0F 2A E4 cvtsi2ss xmm4, r12 \n"
" 0000A0FB F2/ 49/ 0F 2A E4 cvtsi2sd xmm4, r12 \n"
" \n"
" \n"
" ; Between: xmm4 and r13 \n"
" 0000A100 F3/ 41/ 0F 11 65 movss dword ptr [r13 - 4], xmm4 \n"
" FC \n"
" 0000A106 F2/ 41/ 0F 11 65 movsd qword ptr [r13 + 4], xmm4 \n"
" 04 \n"
" \n"
" 0000A10C F3/ 41/ 0F 10 65 movss xmm4, dword ptr [r13 - 4] \n"
" FC \n"
" 0000A112 F2/ 41/ 0F 10 65 movsd xmm4, qword ptr [r13 + 4] \n"
" 04 \n"
" 0000A118 F3/ 49/ 0F 2A 65 cvtsi2ss xmm4, qword ptr [r13 - 4] \n"
" FC \n"
" 0000A11E F2/ 41/ 0F 2A 65 cvtsi2sd xmm4, dword ptr [r13 + 4] \n"
" 04 \n"
" \n"
" 0000A124 F3/ 44/ 0F 2C EC cvttss2si r13d, xmm4 \n"
" 0000A129 F2/ 44/ 0F 2C EC cvttsd2si r13d, xmm4 \n"
" \n"
" 0000A12E F3/ 41/ 0F 2A E5 cvtsi2ss xmm4, r13d \n"
" 0000A133 F2/ 41/ 0F 2A E5 cvtsi2sd xmm4, r13d \n"
" \n"
" 0000A138 F3/ 4C/ 0F 2C EC cvttss2si r13, xmm4 \n"
" 0000A13D F2/ 4C/ 0F 2C EC cvttsd2si r13, xmm4 \n"
" \n"
" 0000A142 F3/ 49/ 0F 2A E5 cvtsi2ss xmm4, r13 \n"
" 0000A147 F2/ 49/ 0F 2A E5 cvtsi2sd xmm4, r13 \n"
" \n"
" \n"
" ; Between: xmm4 and r14 \n"
" 0000A14C F3/ 41/ 0F 11 66 movss dword ptr [r14 - 4], xmm4 \n"
" FC \n"
" 0000A152 F2/ 41/ 0F 11 66 movsd qword ptr [r14 + 4], xmm4 \n"
" 04 \n"
" \n"
" 0000A158 F3/ 41/ 0F 10 66 movss xmm4, dword ptr [r14 - 4] \n"
" FC \n"
" 0000A15E F2/ 41/ 0F 10 66 movsd xmm4, qword ptr [r14 + 4] \n"
" 04 \n"
" 0000A164 F3/ 49/ 0F 2A 66 cvtsi2ss xmm4, qword ptr [r14 - 4] \n"
" FC \n"
" 0000A16A F2/ 41/ 0F 2A 66 cvtsi2sd xmm4, dword ptr [r14 + 4] \n"
" 04 \n"
" \n"
" 0000A170 F3/ 44/ 0F 2C F4 cvttss2si r14d, xmm4 \n"
" 0000A175 F2/ 44/ 0F 2C F4 cvttsd2si r14d, xmm4 \n"
" \n"
" 0000A17A F3/ 41/ 0F 2A E6 cvtsi2ss xmm4, r14d \n"
" 0000A17F F2/ 41/ 0F 2A E6 cvtsi2sd xmm4, r14d \n"
" \n"
" 0000A184 F3/ 4C/ 0F 2C F4 cvttss2si r14, xmm4 \n"
" 0000A189 F2/ 4C/ 0F 2C F4 cvttsd2si r14, xmm4 \n"
" \n"
" 0000A18E F3/ 49/ 0F 2A E6 cvtsi2ss xmm4, r14 \n"
" 0000A193 F2/ 49/ 0F 2A E6 cvtsi2sd xmm4, r14 \n"
" \n"
" \n"
" ; Between: xmm4 and r15 \n"
" 0000A198 F3/ 41/ 0F 11 67 movss dword ptr [r15 - 4], xmm4 \n"
" FC \n"
" 0000A19E F2/ 41/ 0F 11 67 movsd qword ptr [r15 + 4], xmm4 \n"
" 04 \n"
" \n"
" 0000A1A4 F3/ 41/ 0F 10 67 movss xmm4, dword ptr [r15 - 4] \n"
" FC \n"
" 0000A1AA F2/ 41/ 0F 10 67 movsd xmm4, qword ptr [r15 + 4] \n"
" 04 \n"
" 0000A1B0 F3/ 49/ 0F 2A 67 cvtsi2ss xmm4, qword ptr [r15 - 4] \n"
" FC \n"
" 0000A1B6 F2/ 41/ 0F 2A 67 cvtsi2sd xmm4, dword ptr [r15 + 4] \n"
" 04 \n"
" \n"
" 0000A1BC F3/ 44/ 0F 2C FC cvttss2si r15d, xmm4 \n"
" 0000A1C1 F2/ 44/ 0F 2C FC cvttsd2si r15d, xmm4 \n"
" \n"
" 0000A1C6 F3/ 41/ 0F 2A E7 cvtsi2ss xmm4, r15d \n"
" 0000A1CB F2/ 41/ 0F 2A E7 cvtsi2sd xmm4, r15d \n"
" \n"
" 0000A1D0 F3/ 4C/ 0F 2C FC cvttss2si r15, xmm4 \n"
" 0000A1D5 F2/ 4C/ 0F 2C FC cvttsd2si r15, xmm4 \n"
" \n"
" 0000A1DA F3/ 49/ 0F 2A E7 cvtsi2ss xmm4, r15 \n"
" 0000A1DF F2/ 49/ 0F 2A E7 cvtsi2sd xmm4, r15 \n"
" \n"
" \n"
" ; Between: xmm5 and rax \n"
" 0000A1E4 F3/ 0F 11 68 movss dword ptr [rax - 4], xmm5 \n"
" FC \n"
" 0000A1E9 F2/ 0F 11 68 movsd qword ptr [rax + 4], xmm5 \n"
" 04 \n"
" \n"
" 0000A1EE F3/ 0F 10 68 movss xmm5, dword ptr [rax - 4] \n"
" FC \n"
" 0000A1F3 F2/ 0F 10 68 movsd xmm5, qword ptr [rax + 4] \n"
" 04 \n"
" 0000A1F8 F3/ 48/ 0F 2A 68 cvtsi2ss xmm5, qword ptr [rax - 4] \n"
" FC \n"
" 0000A1FE F2/ 0F 2A 68 cvtsi2sd xmm5, dword ptr [rax + 4] \n"
" 04 \n"
" \n"
" 0000A203 F3/ 0F 2C C5 cvttss2si eax, xmm5 \n"
" 0000A207 F2/ 0F 2C C5 cvttsd2si eax, xmm5 \n"
" \n"
" 0000A20B F3/ 0F 2A E8 cvtsi2ss xmm5, eax \n"
" 0000A20F F2/ 0F 2A E8 cvtsi2sd xmm5, eax \n"
" \n"
" 0000A213 F3/ 48/ 0F 2C C5 cvttss2si rax, xmm5 \n"
" 0000A218 F2/ 48/ 0F 2C C5 cvttsd2si rax, xmm5 \n"
" \n"
" 0000A21D F3/ 48/ 0F 2A E8 cvtsi2ss xmm5, rax \n"
" 0000A222 F2/ 48/ 0F 2A E8 cvtsi2sd xmm5, rax \n"
" \n"
" \n"
" ; Between: xmm5 and rcx \n"
" 0000A227 F3/ 0F 11 69 movss dword ptr [rcx - 4], xmm5 \n"
" FC \n"
" 0000A22C F2/ 0F 11 69 movsd qword ptr [rcx + 4], xmm5 \n"
" 04 \n"
" \n"
" 0000A231 F3/ 0F 10 69 movss xmm5, dword ptr [rcx - 4] \n"
" FC \n"
" 0000A236 F2/ 0F 10 69 movsd xmm5, qword ptr [rcx + 4] \n"
" 04 \n"
" 0000A23B F3/ 48/ 0F 2A 69 cvtsi2ss xmm5, qword ptr [rcx - 4] \n"
" FC \n"
" 0000A241 F2/ 0F 2A 69 cvtsi2sd xmm5, dword ptr [rcx + 4] \n"
" 04 \n"
" \n"
" 0000A246 F3/ 0F 2C CD cvttss2si ecx, xmm5 \n"
" 0000A24A F2/ 0F 2C CD cvttsd2si ecx, xmm5 \n"
" \n"
" 0000A24E F3/ 0F 2A E9 cvtsi2ss xmm5, ecx \n"
" 0000A252 F2/ 0F 2A E9 cvtsi2sd xmm5, ecx \n"
" \n"
" 0000A256 F3/ 48/ 0F 2C CD cvttss2si rcx, xmm5 \n"
" 0000A25B F2/ 48/ 0F 2C CD cvttsd2si rcx, xmm5 \n"
" \n"
" 0000A260 F3/ 48/ 0F 2A E9 cvtsi2ss xmm5, rcx \n"
" 0000A265 F2/ 48/ 0F 2A E9 cvtsi2sd xmm5, rcx \n"
" \n"
" \n"
" ; Between: xmm5 and rdx \n"
" 0000A26A F3/ 0F 11 6A movss dword ptr [rdx - 4], xmm5 \n"
" FC \n"
" 0000A26F F2/ 0F 11 6A movsd qword ptr [rdx + 4], xmm5 \n"
" 04 \n"
" \n"
" 0000A274 F3/ 0F 10 6A movss xmm5, dword ptr [rdx - 4] \n"
" FC \n"
" 0000A279 F2/ 0F 10 6A movsd xmm5, qword ptr [rdx + 4] \n"
" 04 \n"
" 0000A27E F3/ 48/ 0F 2A 6A cvtsi2ss xmm5, qword ptr [rdx - 4] \n"
" FC \n"
" 0000A284 F2/ 0F 2A 6A cvtsi2sd xmm5, dword ptr [rdx + 4] \n"
" 04 \n"
" \n"
" 0000A289 F3/ 0F 2C D5 cvttss2si edx, xmm5 \n"
" 0000A28D F2/ 0F 2C D5 cvttsd2si edx, xmm5 \n"
" \n"
" 0000A291 F3/ 0F 2A EA cvtsi2ss xmm5, edx \n"
" 0000A295 F2/ 0F 2A EA cvtsi2sd xmm5, edx \n"
" \n"
" 0000A299 F3/ 48/ 0F 2C D5 cvttss2si rdx, xmm5 \n"
" 0000A29E F2/ 48/ 0F 2C D5 cvttsd2si rdx, xmm5 \n"
" \n"
" 0000A2A3 F3/ 48/ 0F 2A EA cvtsi2ss xmm5, rdx \n"
" 0000A2A8 F2/ 48/ 0F 2A EA cvtsi2sd xmm5, rdx \n"
" \n"
" \n"
" ; Between: xmm5 and rbx \n"
" 0000A2AD F3/ 0F 11 6B movss dword ptr [rbx - 4], xmm5 \n"
" FC \n"
" 0000A2B2 F2/ 0F 11 6B movsd qword ptr [rbx + 4], xmm5 \n"
" 04 \n"
" \n"
" 0000A2B7 F3/ 0F 10 6B movss xmm5, dword ptr [rbx - 4] \n"
" FC \n"
" 0000A2BC F2/ 0F 10 6B movsd xmm5, qword ptr [rbx + 4] \n"
" 04 \n"
" 0000A2C1 F3/ 48/ 0F 2A 6B cvtsi2ss xmm5, qword ptr [rbx - 4] \n"
" FC \n"
" 0000A2C7 F2/ 0F 2A 6B cvtsi2sd xmm5, dword ptr [rbx + 4] \n"
" 04 \n"
" \n"
" 0000A2CC F3/ 0F 2C DD cvttss2si ebx, xmm5 \n"
" 0000A2D0 F2/ 0F 2C DD cvttsd2si ebx, xmm5 \n"
" \n"
" 0000A2D4 F3/ 0F 2A EB cvtsi2ss xmm5, ebx \n"
" 0000A2D8 F2/ 0F 2A EB cvtsi2sd xmm5, ebx \n"
" \n"
" 0000A2DC F3/ 48/ 0F 2C DD cvttss2si rbx, xmm5 \n"
" 0000A2E1 F2/ 48/ 0F 2C DD cvttsd2si rbx, xmm5 \n"
" \n"
" 0000A2E6 F3/ 48/ 0F 2A EB cvtsi2ss xmm5, rbx \n"
" 0000A2EB F2/ 48/ 0F 2A EB cvtsi2sd xmm5, rbx \n"
" \n"
" \n"
" ; Between: xmm5 and rsp \n"
" 0000A2F0 F3/ 0F 11 6C 24 movss dword ptr [rsp - 4], xmm5 \n"
" FC \n"
" 0000A2F6 F2/ 0F 11 6C 24 movsd qword ptr [rsp + 4], xmm5 \n"
" 04 \n"
" \n"
" 0000A2FC F3/ 0F 10 6C 24 movss xmm5, dword ptr [rsp - 4] \n"
" FC \n"
" 0000A302 F2/ 0F 10 6C 24 movsd xmm5, qword ptr [rsp + 4] \n"
" 04 \n"
" 0000A308 F3/ 48/ 0F 2A 6C cvtsi2ss xmm5, qword ptr [rsp - 4] \n"
" 24 FC \n"
" 0000A30F F2/ 0F 2A 6C 24 cvtsi2sd xmm5, dword ptr [rsp + 4] \n"
" 04 \n"
" \n"
" 0000A315 F3/ 0F 2C E5 cvttss2si esp, xmm5 \n"
" 0000A319 F2/ 0F 2C E5 cvttsd2si esp, xmm5 \n"
" \n"
" 0000A31D F3/ 0F 2A EC cvtsi2ss xmm5, esp \n"
" 0000A321 F2/ 0F 2A EC cvtsi2sd xmm5, esp \n"
" \n"
" 0000A325 F3/ 48/ 0F 2C E5 cvttss2si rsp, xmm5 \n"
" 0000A32A F2/ 48/ 0F 2C E5 cvttsd2si rsp, xmm5 \n"
" \n"
" 0000A32F F3/ 48/ 0F 2A EC cvtsi2ss xmm5, rsp \n"
" 0000A334 F2/ 48/ 0F 2A EC cvtsi2sd xmm5, rsp \n"
" \n"
" \n"
" ; Between: xmm5 and rbp \n"
" 0000A339 F3/ 0F 11 6D movss dword ptr [rbp - 4], xmm5 \n"
" FC \n"
" 0000A33E F2/ 0F 11 6D movsd qword ptr [rbp + 4], xmm5 \n"
" 04 \n"
" \n"
" 0000A343 F3/ 0F 10 6D movss xmm5, dword ptr [rbp - 4] \n"
" FC \n"
" 0000A348 F2/ 0F 10 6D movsd xmm5, qword ptr [rbp + 4] \n"
" 04 \n"
" 0000A34D F3/ 48/ 0F 2A 6D cvtsi2ss xmm5, qword ptr [rbp - 4] \n"
" FC \n"
" 0000A353 F2/ 0F 2A 6D cvtsi2sd xmm5, dword ptr [rbp + 4] \n"
" 04 \n"
" \n"
" 0000A358 F3/ 0F 2C ED cvttss2si ebp, xmm5 \n"
" 0000A35C F2/ 0F 2C ED cvttsd2si ebp, xmm5 \n"
" \n"
" 0000A360 F3/ 0F 2A ED cvtsi2ss xmm5, ebp \n"
" 0000A364 F2/ 0F 2A ED cvtsi2sd xmm5, ebp \n"
" \n"
" 0000A368 F3/ 48/ 0F 2C ED cvttss2si rbp, xmm5 \n"
" 0000A36D F2/ 48/ 0F 2C ED cvttsd2si rbp, xmm5 \n"
" \n"
" 0000A372 F3/ 48/ 0F 2A ED cvtsi2ss xmm5, rbp \n"
" 0000A377 F2/ 48/ 0F 2A ED cvtsi2sd xmm5, rbp \n"
" \n"
" \n"
" ; Between: xmm5 and rsi \n"
" 0000A37C F3/ 0F 11 6E movss dword ptr [rsi - 4], xmm5 \n"
" FC \n"
" 0000A381 F2/ 0F 11 6E movsd qword ptr [rsi + 4], xmm5 \n"
" 04 \n"
" \n"
" 0000A386 F3/ 0F 10 6E movss xmm5, dword ptr [rsi - 4] \n"
" FC \n"
" 0000A38B F2/ 0F 10 6E movsd xmm5, qword ptr [rsi + 4] \n"
" 04 \n"
" 0000A390 F3/ 48/ 0F 2A 6E cvtsi2ss xmm5, qword ptr [rsi - 4] \n"
" FC \n"
" 0000A396 F2/ 0F 2A 6E cvtsi2sd xmm5, dword ptr [rsi + 4] \n"
" 04 \n"
" \n"
" 0000A39B F3/ 0F 2C F5 cvttss2si esi, xmm5 \n"
" 0000A39F F2/ 0F 2C F5 cvttsd2si esi, xmm5 \n"
" \n"
" 0000A3A3 F3/ 0F 2A EE cvtsi2ss xmm5, esi \n"
" 0000A3A7 F2/ 0F 2A EE cvtsi2sd xmm5, esi \n"
" \n"
" 0000A3AB F3/ 48/ 0F 2C F5 cvttss2si rsi, xmm5 \n"
" 0000A3B0 F2/ 48/ 0F 2C F5 cvttsd2si rsi, xmm5 \n"
" \n"
" 0000A3B5 F3/ 48/ 0F 2A EE cvtsi2ss xmm5, rsi \n"
" 0000A3BA F2/ 48/ 0F 2A EE cvtsi2sd xmm5, rsi \n"
" \n"
" \n"
" ; Between: xmm5 and rdi \n"
" 0000A3BF F3/ 0F 11 6F movss dword ptr [rdi - 4], xmm5 \n"
" FC \n"
" 0000A3C4 F2/ 0F 11 6F movsd qword ptr [rdi + 4], xmm5 \n"
" 04 \n"
" \n"
" 0000A3C9 F3/ 0F 10 6F movss xmm5, dword ptr [rdi - 4] \n"
" FC \n"
" 0000A3CE F2/ 0F 10 6F movsd xmm5, qword ptr [rdi + 4] \n"
" 04 \n"
" 0000A3D3 F3/ 48/ 0F 2A 6F cvtsi2ss xmm5, qword ptr [rdi - 4] \n"
" FC \n"
" 0000A3D9 F2/ 0F 2A 6F cvtsi2sd xmm5, dword ptr [rdi + 4] \n"
" 04 \n"
" \n"
" 0000A3DE F3/ 0F 2C FD cvttss2si edi, xmm5 \n"
" 0000A3E2 F2/ 0F 2C FD cvttsd2si edi, xmm5 \n"
" \n"
" 0000A3E6 F3/ 0F 2A EF cvtsi2ss xmm5, edi \n"
" 0000A3EA F2/ 0F 2A EF cvtsi2sd xmm5, edi \n"
" \n"
" 0000A3EE F3/ 48/ 0F 2C FD cvttss2si rdi, xmm5 \n"
" 0000A3F3 F2/ 48/ 0F 2C FD cvttsd2si rdi, xmm5 \n"
" \n"
" 0000A3F8 F3/ 48/ 0F 2A EF cvtsi2ss xmm5, rdi \n"
" 0000A3FD F2/ 48/ 0F 2A EF cvtsi2sd xmm5, rdi \n"
" \n"
" \n"
" ; Between: xmm5 and r8 \n"
" 0000A402 F3/ 41/ 0F 11 68 movss dword ptr [r8 - 4], xmm5 \n"
" FC \n"
" 0000A408 F2/ 41/ 0F 11 68 movsd qword ptr [r8 + 4], xmm5 \n"
" 04 \n"
" \n"
" 0000A40E F3/ 41/ 0F 10 68 movss xmm5, dword ptr [r8 - 4] \n"
" FC \n"
" 0000A414 F2/ 41/ 0F 10 68 movsd xmm5, qword ptr [r8 + 4] \n"
" 04 \n"
" 0000A41A F3/ 49/ 0F 2A 68 cvtsi2ss xmm5, qword ptr [r8 - 4] \n"
" FC \n"
" 0000A420 F2/ 41/ 0F 2A 68 cvtsi2sd xmm5, dword ptr [r8 + 4] \n"
" 04 \n"
" \n"
" 0000A426 F3/ 44/ 0F 2C C5 cvttss2si r8d, xmm5 \n"
" 0000A42B F2/ 44/ 0F 2C C5 cvttsd2si r8d, xmm5 \n"
" \n"
" 0000A430 F3/ 41/ 0F 2A E8 cvtsi2ss xmm5, r8d \n"
" 0000A435 F2/ 41/ 0F 2A E8 cvtsi2sd xmm5, r8d \n"
" \n"
" 0000A43A F3/ 4C/ 0F 2C C5 cvttss2si r8, xmm5 \n"
" 0000A43F F2/ 4C/ 0F 2C C5 cvttsd2si r8, xmm5 \n"
" \n"
" 0000A444 F3/ 49/ 0F 2A E8 cvtsi2ss xmm5, r8 \n"
" 0000A449 F2/ 49/ 0F 2A E8 cvtsi2sd xmm5, r8 \n"
" \n"
" \n"
" ; Between: xmm5 and r9 \n"
" 0000A44E F3/ 41/ 0F 11 69 movss dword ptr [r9 - 4], xmm5 \n"
" FC \n"
" 0000A454 F2/ 41/ 0F 11 69 movsd qword ptr [r9 + 4], xmm5 \n"
" 04 \n"
" \n"
" 0000A45A F3/ 41/ 0F 10 69 movss xmm5, dword ptr [r9 - 4] \n"
" FC \n"
" 0000A460 F2/ 41/ 0F 10 69 movsd xmm5, qword ptr [r9 + 4] \n"
" 04 \n"
" 0000A466 F3/ 49/ 0F 2A 69 cvtsi2ss xmm5, qword ptr [r9 - 4] \n"
" FC \n"
" 0000A46C F2/ 41/ 0F 2A 69 cvtsi2sd xmm5, dword ptr [r9 + 4] \n"
" 04 \n"
" \n"
" 0000A472 F3/ 44/ 0F 2C CD cvttss2si r9d, xmm5 \n"
" 0000A477 F2/ 44/ 0F 2C CD cvttsd2si r9d, xmm5 \n"
" \n"
" 0000A47C F3/ 41/ 0F 2A E9 cvtsi2ss xmm5, r9d \n"
" 0000A481 F2/ 41/ 0F 2A E9 cvtsi2sd xmm5, r9d \n"
" \n"
" 0000A486 F3/ 4C/ 0F 2C CD cvttss2si r9, xmm5 \n"
" 0000A48B F2/ 4C/ 0F 2C CD cvttsd2si r9, xmm5 \n"
" \n"
" 0000A490 F3/ 49/ 0F 2A E9 cvtsi2ss xmm5, r9 \n"
" 0000A495 F2/ 49/ 0F 2A E9 cvtsi2sd xmm5, r9 \n"
" \n"
" \n"
" ; Between: xmm5 and r10 \n"
" 0000A49A F3/ 41/ 0F 11 6A movss dword ptr [r10 - 4], xmm5 \n"
" FC \n"
" 0000A4A0 F2/ 41/ 0F 11 6A movsd qword ptr [r10 + 4], xmm5 \n"
" 04 \n"
" \n"
" 0000A4A6 F3/ 41/ 0F 10 6A movss xmm5, dword ptr [r10 - 4] \n"
" FC \n"
" 0000A4AC F2/ 41/ 0F 10 6A movsd xmm5, qword ptr [r10 + 4] \n"
" 04 \n"
" 0000A4B2 F3/ 49/ 0F 2A 6A cvtsi2ss xmm5, qword ptr [r10 - 4] \n"
" FC \n"
" 0000A4B8 F2/ 41/ 0F 2A 6A cvtsi2sd xmm5, dword ptr [r10 + 4] \n"
" 04 \n"
" \n"
" 0000A4BE F3/ 44/ 0F 2C D5 cvttss2si r10d, xmm5 \n"
" 0000A4C3 F2/ 44/ 0F 2C D5 cvttsd2si r10d, xmm5 \n"
" \n"
" 0000A4C8 F3/ 41/ 0F 2A EA cvtsi2ss xmm5, r10d \n"
" 0000A4CD F2/ 41/ 0F 2A EA cvtsi2sd xmm5, r10d \n"
" \n"
" 0000A4D2 F3/ 4C/ 0F 2C D5 cvttss2si r10, xmm5 \n"
" 0000A4D7 F2/ 4C/ 0F 2C D5 cvttsd2si r10, xmm5 \n"
" \n"
" 0000A4DC F3/ 49/ 0F 2A EA cvtsi2ss xmm5, r10 \n"
" 0000A4E1 F2/ 49/ 0F 2A EA cvtsi2sd xmm5, r10 \n"
" \n"
" \n"
" ; Between: xmm5 and r11 \n"
" 0000A4E6 F3/ 41/ 0F 11 6B movss dword ptr [r11 - 4], xmm5 \n"
" FC \n"
" 0000A4EC F2/ 41/ 0F 11 6B movsd qword ptr [r11 + 4], xmm5 \n"
" 04 \n"
" \n"
" 0000A4F2 F3/ 41/ 0F 10 6B movss xmm5, dword ptr [r11 - 4] \n"
" FC \n"
" 0000A4F8 F2/ 41/ 0F 10 6B movsd xmm5, qword ptr [r11 + 4] \n"
" 04 \n"
" 0000A4FE F3/ 49/ 0F 2A 6B cvtsi2ss xmm5, qword ptr [r11 - 4] \n"
" FC \n"
" 0000A504 F2/ 41/ 0F 2A 6B cvtsi2sd xmm5, dword ptr [r11 + 4] \n"
" 04 \n"
" \n"
" 0000A50A F3/ 44/ 0F 2C DD cvttss2si r11d, xmm5 \n"
" 0000A50F F2/ 44/ 0F 2C DD cvttsd2si r11d, xmm5 \n"
" \n"
" 0000A514 F3/ 41/ 0F 2A EB cvtsi2ss xmm5, r11d \n"
" 0000A519 F2/ 41/ 0F 2A EB cvtsi2sd xmm5, r11d \n"
" \n"
" 0000A51E F3/ 4C/ 0F 2C DD cvttss2si r11, xmm5 \n"
" 0000A523 F2/ 4C/ 0F 2C DD cvttsd2si r11, xmm5 \n"
" \n"
" 0000A528 F3/ 49/ 0F 2A EB cvtsi2ss xmm5, r11 \n"
" 0000A52D F2/ 49/ 0F 2A EB cvtsi2sd xmm5, r11 \n"
" \n"
" \n"
" ; Between: xmm5 and r12 \n"
" 0000A532 F3/ 41/ 0F 11 6C movss dword ptr [r12 - 4], xmm5 \n"
" 24 FC \n"
" 0000A539 F2/ 41/ 0F 11 6C movsd qword ptr [r12 + 4], xmm5 \n"
" 24 04 \n"
" \n"
" 0000A540 F3/ 41/ 0F 10 6C movss xmm5, dword ptr [r12 - 4] \n"
" 24 FC \n"
" 0000A547 F2/ 41/ 0F 10 6C movsd xmm5, qword ptr [r12 + 4] \n"
" 24 04 \n"
" 0000A54E F3/ 49/ 0F 2A 6C cvtsi2ss xmm5, qword ptr [r12 - 4] \n"
" 24 FC \n"
" 0000A555 F2/ 41/ 0F 2A 6C cvtsi2sd xmm5, dword ptr [r12 + 4] \n"
" 24 04 \n"
" \n"
" 0000A55C F3/ 44/ 0F 2C E5 cvttss2si r12d, xmm5 \n"
" 0000A561 F2/ 44/ 0F 2C E5 cvttsd2si r12d, xmm5 \n"
" \n"
" 0000A566 F3/ 41/ 0F 2A EC cvtsi2ss xmm5, r12d \n"
" 0000A56B F2/ 41/ 0F 2A EC cvtsi2sd xmm5, r12d \n"
" \n"
" 0000A570 F3/ 4C/ 0F 2C E5 cvttss2si r12, xmm5 \n"
" 0000A575 F2/ 4C/ 0F 2C E5 cvttsd2si r12, xmm5 \n"
" \n"
" 0000A57A F3/ 49/ 0F 2A EC cvtsi2ss xmm5, r12 \n"
" 0000A57F F2/ 49/ 0F 2A EC cvtsi2sd xmm5, r12 \n"
" \n"
" \n"
" ; Between: xmm5 and r13 \n"
" 0000A584 F3/ 41/ 0F 11 6D movss dword ptr [r13 - 4], xmm5 \n"
" FC \n"
" 0000A58A F2/ 41/ 0F 11 6D movsd qword ptr [r13 + 4], xmm5 \n"
" 04 \n"
" \n"
" 0000A590 F3/ 41/ 0F 10 6D movss xmm5, dword ptr [r13 - 4] \n"
" FC \n"
" 0000A596 F2/ 41/ 0F 10 6D movsd xmm5, qword ptr [r13 + 4] \n"
" 04 \n"
" 0000A59C F3/ 49/ 0F 2A 6D cvtsi2ss xmm5, qword ptr [r13 - 4] \n"
" FC \n"
" 0000A5A2 F2/ 41/ 0F 2A 6D cvtsi2sd xmm5, dword ptr [r13 + 4] \n"
" 04 \n"
" \n"
" 0000A5A8 F3/ 44/ 0F 2C ED cvttss2si r13d, xmm5 \n"
" 0000A5AD F2/ 44/ 0F 2C ED cvttsd2si r13d, xmm5 \n"
" \n"
" 0000A5B2 F3/ 41/ 0F 2A ED cvtsi2ss xmm5, r13d \n"
" 0000A5B7 F2/ 41/ 0F 2A ED cvtsi2sd xmm5, r13d \n"
" \n"
" 0000A5BC F3/ 4C/ 0F 2C ED cvttss2si r13, xmm5 \n"
" 0000A5C1 F2/ 4C/ 0F 2C ED cvttsd2si r13, xmm5 \n"
" \n"
" 0000A5C6 F3/ 49/ 0F 2A ED cvtsi2ss xmm5, r13 \n"
" 0000A5CB F2/ 49/ 0F 2A ED cvtsi2sd xmm5, r13 \n"
" \n"
" \n"
" ; Between: xmm5 and r14 \n"
" 0000A5D0 F3/ 41/ 0F 11 6E movss dword ptr [r14 - 4], xmm5 \n"
" FC \n"
" 0000A5D6 F2/ 41/ 0F 11 6E movsd qword ptr [r14 + 4], xmm5 \n"
" 04 \n"
" \n"
" 0000A5DC F3/ 41/ 0F 10 6E movss xmm5, dword ptr [r14 - 4] \n"
" FC \n"
" 0000A5E2 F2/ 41/ 0F 10 6E movsd xmm5, qword ptr [r14 + 4] \n"
" 04 \n"
" 0000A5E8 F3/ 49/ 0F 2A 6E cvtsi2ss xmm5, qword ptr [r14 - 4] \n"
" FC \n"
" 0000A5EE F2/ 41/ 0F 2A 6E cvtsi2sd xmm5, dword ptr [r14 + 4] \n"
" 04 \n"
" \n"
" 0000A5F4 F3/ 44/ 0F 2C F5 cvttss2si r14d, xmm5 \n"
" 0000A5F9 F2/ 44/ 0F 2C F5 cvttsd2si r14d, xmm5 \n"
" \n"
" 0000A5FE F3/ 41/ 0F 2A EE cvtsi2ss xmm5, r14d \n"
" 0000A603 F2/ 41/ 0F 2A EE cvtsi2sd xmm5, r14d \n"
" \n"
" 0000A608 F3/ 4C/ 0F 2C F5 cvttss2si r14, xmm5 \n"
" 0000A60D F2/ 4C/ 0F 2C F5 cvttsd2si r14, xmm5 \n"
" \n"
" 0000A612 F3/ 49/ 0F 2A EE cvtsi2ss xmm5, r14 \n"
" 0000A617 F2/ 49/ 0F 2A EE cvtsi2sd xmm5, r14 \n"
" \n"
" \n"
" ; Between: xmm5 and r15 \n"
" 0000A61C F3/ 41/ 0F 11 6F movss dword ptr [r15 - 4], xmm5 \n"
" FC \n"
" 0000A622 F2/ 41/ 0F 11 6F movsd qword ptr [r15 + 4], xmm5 \n"
" 04 \n"
" \n"
" 0000A628 F3/ 41/ 0F 10 6F movss xmm5, dword ptr [r15 - 4] \n"
" FC \n"
" 0000A62E F2/ 41/ 0F 10 6F movsd xmm5, qword ptr [r15 + 4] \n"
" 04 \n"
" 0000A634 F3/ 49/ 0F 2A 6F cvtsi2ss xmm5, qword ptr [r15 - 4] \n"
" FC \n"
" 0000A63A F2/ 41/ 0F 2A 6F cvtsi2sd xmm5, dword ptr [r15 + 4] \n"
" 04 \n"
" \n"
" 0000A640 F3/ 44/ 0F 2C FD cvttss2si r15d, xmm5 \n"
" 0000A645 F2/ 44/ 0F 2C FD cvttsd2si r15d, xmm5 \n"
" \n";
ml64Output +=
" 0000A64A F3/ 41/ 0F 2A EF cvtsi2ss xmm5, r15d \n"
" 0000A64F F2/ 41/ 0F 2A EF cvtsi2sd xmm5, r15d \n"
" \n"
" 0000A654 F3/ 4C/ 0F 2C FD cvttss2si r15, xmm5 \n"
" 0000A659 F2/ 4C/ 0F 2C FD cvttsd2si r15, xmm5 \n"
" \n"
" 0000A65E F3/ 49/ 0F 2A EF cvtsi2ss xmm5, r15 \n"
" 0000A663 F2/ 49/ 0F 2A EF cvtsi2sd xmm5, r15 \n"
" \n"
" \n"
" ; Between: xmm6 and rax \n"
" 0000A668 F3/ 0F 11 70 movss dword ptr [rax - 4], xmm6 \n"
" FC \n"
" 0000A66D F2/ 0F 11 70 movsd qword ptr [rax + 4], xmm6 \n"
" 04 \n"
" \n"
" 0000A672 F3/ 0F 10 70 movss xmm6, dword ptr [rax - 4] \n"
" FC \n"
" 0000A677 F2/ 0F 10 70 movsd xmm6, qword ptr [rax + 4] \n"
" 04 \n"
" 0000A67C F3/ 48/ 0F 2A 70 cvtsi2ss xmm6, qword ptr [rax - 4] \n"
" FC \n"
" 0000A682 F2/ 0F 2A 70 cvtsi2sd xmm6, dword ptr [rax + 4] \n"
" 04 \n"
" \n"
" 0000A687 F3/ 0F 2C C6 cvttss2si eax, xmm6 \n"
" 0000A68B F2/ 0F 2C C6 cvttsd2si eax, xmm6 \n"
" \n"
" 0000A68F F3/ 0F 2A F0 cvtsi2ss xmm6, eax \n"
" 0000A693 F2/ 0F 2A F0 cvtsi2sd xmm6, eax \n"
" \n"
" 0000A697 F3/ 48/ 0F 2C C6 cvttss2si rax, xmm6 \n"
" 0000A69C F2/ 48/ 0F 2C C6 cvttsd2si rax, xmm6 \n"
" \n"
" 0000A6A1 F3/ 48/ 0F 2A F0 cvtsi2ss xmm6, rax \n"
" 0000A6A6 F2/ 48/ 0F 2A F0 cvtsi2sd xmm6, rax \n"
" \n"
" \n"
" ; Between: xmm6 and rcx \n"
" 0000A6AB F3/ 0F 11 71 movss dword ptr [rcx - 4], xmm6 \n"
" FC \n"
" 0000A6B0 F2/ 0F 11 71 movsd qword ptr [rcx + 4], xmm6 \n"
" 04 \n"
" \n"
" 0000A6B5 F3/ 0F 10 71 movss xmm6, dword ptr [rcx - 4] \n"
" FC \n"
" 0000A6BA F2/ 0F 10 71 movsd xmm6, qword ptr [rcx + 4] \n"
" 04 \n"
" 0000A6BF F3/ 48/ 0F 2A 71 cvtsi2ss xmm6, qword ptr [rcx - 4] \n"
" FC \n"
" 0000A6C5 F2/ 0F 2A 71 cvtsi2sd xmm6, dword ptr [rcx + 4] \n"
" 04 \n"
" \n"
" 0000A6CA F3/ 0F 2C CE cvttss2si ecx, xmm6 \n"
" 0000A6CE F2/ 0F 2C CE cvttsd2si ecx, xmm6 \n"
" \n"
" 0000A6D2 F3/ 0F 2A F1 cvtsi2ss xmm6, ecx \n"
" 0000A6D6 F2/ 0F 2A F1 cvtsi2sd xmm6, ecx \n"
" \n"
" 0000A6DA F3/ 48/ 0F 2C CE cvttss2si rcx, xmm6 \n"
" 0000A6DF F2/ 48/ 0F 2C CE cvttsd2si rcx, xmm6 \n"
" \n"
" 0000A6E4 F3/ 48/ 0F 2A F1 cvtsi2ss xmm6, rcx \n"
" 0000A6E9 F2/ 48/ 0F 2A F1 cvtsi2sd xmm6, rcx \n"
" \n"
" \n"
" ; Between: xmm6 and rdx \n"
" 0000A6EE F3/ 0F 11 72 movss dword ptr [rdx - 4], xmm6 \n"
" FC \n"
" 0000A6F3 F2/ 0F 11 72 movsd qword ptr [rdx + 4], xmm6 \n"
" 04 \n"
" \n"
" 0000A6F8 F3/ 0F 10 72 movss xmm6, dword ptr [rdx - 4] \n"
" FC \n"
" 0000A6FD F2/ 0F 10 72 movsd xmm6, qword ptr [rdx + 4] \n"
" 04 \n"
" 0000A702 F3/ 48/ 0F 2A 72 cvtsi2ss xmm6, qword ptr [rdx - 4] \n"
" FC \n"
" 0000A708 F2/ 0F 2A 72 cvtsi2sd xmm6, dword ptr [rdx + 4] \n"
" 04 \n"
" \n"
" 0000A70D F3/ 0F 2C D6 cvttss2si edx, xmm6 \n"
" 0000A711 F2/ 0F 2C D6 cvttsd2si edx, xmm6 \n"
" \n"
" 0000A715 F3/ 0F 2A F2 cvtsi2ss xmm6, edx \n"
" 0000A719 F2/ 0F 2A F2 cvtsi2sd xmm6, edx \n"
" \n"
" 0000A71D F3/ 48/ 0F 2C D6 cvttss2si rdx, xmm6 \n"
" 0000A722 F2/ 48/ 0F 2C D6 cvttsd2si rdx, xmm6 \n"
" \n"
" 0000A727 F3/ 48/ 0F 2A F2 cvtsi2ss xmm6, rdx \n"
" 0000A72C F2/ 48/ 0F 2A F2 cvtsi2sd xmm6, rdx \n"
" \n"
" \n"
" ; Between: xmm6 and rbx \n"
" 0000A731 F3/ 0F 11 73 movss dword ptr [rbx - 4], xmm6 \n"
" FC \n"
" 0000A736 F2/ 0F 11 73 movsd qword ptr [rbx + 4], xmm6 \n"
" 04 \n"
" \n"
" 0000A73B F3/ 0F 10 73 movss xmm6, dword ptr [rbx - 4] \n"
" FC \n"
" 0000A740 F2/ 0F 10 73 movsd xmm6, qword ptr [rbx + 4] \n"
" 04 \n"
" 0000A745 F3/ 48/ 0F 2A 73 cvtsi2ss xmm6, qword ptr [rbx - 4] \n"
" FC \n"
" 0000A74B F2/ 0F 2A 73 cvtsi2sd xmm6, dword ptr [rbx + 4] \n"
" 04 \n"
" \n"
" 0000A750 F3/ 0F 2C DE cvttss2si ebx, xmm6 \n"
" 0000A754 F2/ 0F 2C DE cvttsd2si ebx, xmm6 \n"
" \n"
" 0000A758 F3/ 0F 2A F3 cvtsi2ss xmm6, ebx \n"
" 0000A75C F2/ 0F 2A F3 cvtsi2sd xmm6, ebx \n"
" \n"
" 0000A760 F3/ 48/ 0F 2C DE cvttss2si rbx, xmm6 \n"
" 0000A765 F2/ 48/ 0F 2C DE cvttsd2si rbx, xmm6 \n"
" \n"
" 0000A76A F3/ 48/ 0F 2A F3 cvtsi2ss xmm6, rbx \n"
" 0000A76F F2/ 48/ 0F 2A F3 cvtsi2sd xmm6, rbx \n"
" \n"
" \n"
" ; Between: xmm6 and rsp \n"
" 0000A774 F3/ 0F 11 74 24 movss dword ptr [rsp - 4], xmm6 \n"
" FC \n"
" 0000A77A F2/ 0F 11 74 24 movsd qword ptr [rsp + 4], xmm6 \n"
" 04 \n"
" \n"
" 0000A780 F3/ 0F 10 74 24 movss xmm6, dword ptr [rsp - 4] \n"
" FC \n"
" 0000A786 F2/ 0F 10 74 24 movsd xmm6, qword ptr [rsp + 4] \n"
" 04 \n"
" 0000A78C F3/ 48/ 0F 2A 74 cvtsi2ss xmm6, qword ptr [rsp - 4] \n"
" 24 FC \n"
" 0000A793 F2/ 0F 2A 74 24 cvtsi2sd xmm6, dword ptr [rsp + 4] \n"
" 04 \n"
" \n"
" 0000A799 F3/ 0F 2C E6 cvttss2si esp, xmm6 \n"
" 0000A79D F2/ 0F 2C E6 cvttsd2si esp, xmm6 \n"
" \n"
" 0000A7A1 F3/ 0F 2A F4 cvtsi2ss xmm6, esp \n"
" 0000A7A5 F2/ 0F 2A F4 cvtsi2sd xmm6, esp \n"
" \n"
" 0000A7A9 F3/ 48/ 0F 2C E6 cvttss2si rsp, xmm6 \n"
" 0000A7AE F2/ 48/ 0F 2C E6 cvttsd2si rsp, xmm6 \n"
" \n"
" 0000A7B3 F3/ 48/ 0F 2A F4 cvtsi2ss xmm6, rsp \n"
" 0000A7B8 F2/ 48/ 0F 2A F4 cvtsi2sd xmm6, rsp \n"
" \n"
" \n"
" ; Between: xmm6 and rbp \n"
" 0000A7BD F3/ 0F 11 75 movss dword ptr [rbp - 4], xmm6 \n"
" FC \n"
" 0000A7C2 F2/ 0F 11 75 movsd qword ptr [rbp + 4], xmm6 \n"
" 04 \n"
" \n"
" 0000A7C7 F3/ 0F 10 75 movss xmm6, dword ptr [rbp - 4] \n"
" FC \n"
" 0000A7CC F2/ 0F 10 75 movsd xmm6, qword ptr [rbp + 4] \n"
" 04 \n"
" 0000A7D1 F3/ 48/ 0F 2A 75 cvtsi2ss xmm6, qword ptr [rbp - 4] \n"
" FC \n"
" 0000A7D7 F2/ 0F 2A 75 cvtsi2sd xmm6, dword ptr [rbp + 4] \n"
" 04 \n"
" \n"
" 0000A7DC F3/ 0F 2C EE cvttss2si ebp, xmm6 \n"
" 0000A7E0 F2/ 0F 2C EE cvttsd2si ebp, xmm6 \n"
" \n"
" 0000A7E4 F3/ 0F 2A F5 cvtsi2ss xmm6, ebp \n"
" 0000A7E8 F2/ 0F 2A F5 cvtsi2sd xmm6, ebp \n"
" \n"
" 0000A7EC F3/ 48/ 0F 2C EE cvttss2si rbp, xmm6 \n"
" 0000A7F1 F2/ 48/ 0F 2C EE cvttsd2si rbp, xmm6 \n"
" \n"
" 0000A7F6 F3/ 48/ 0F 2A F5 cvtsi2ss xmm6, rbp \n"
" 0000A7FB F2/ 48/ 0F 2A F5 cvtsi2sd xmm6, rbp \n"
" \n"
" \n"
" ; Between: xmm6 and rsi \n"
" 0000A800 F3/ 0F 11 76 movss dword ptr [rsi - 4], xmm6 \n"
" FC \n"
" 0000A805 F2/ 0F 11 76 movsd qword ptr [rsi + 4], xmm6 \n"
" 04 \n"
" \n"
" 0000A80A F3/ 0F 10 76 movss xmm6, dword ptr [rsi - 4] \n"
" FC \n"
" 0000A80F F2/ 0F 10 76 movsd xmm6, qword ptr [rsi + 4] \n"
" 04 \n"
" 0000A814 F3/ 48/ 0F 2A 76 cvtsi2ss xmm6, qword ptr [rsi - 4] \n"
" FC \n"
" 0000A81A F2/ 0F 2A 76 cvtsi2sd xmm6, dword ptr [rsi + 4] \n"
" 04 \n"
" \n"
" 0000A81F F3/ 0F 2C F6 cvttss2si esi, xmm6 \n"
" 0000A823 F2/ 0F 2C F6 cvttsd2si esi, xmm6 \n"
" \n"
" 0000A827 F3/ 0F 2A F6 cvtsi2ss xmm6, esi \n"
" 0000A82B F2/ 0F 2A F6 cvtsi2sd xmm6, esi \n"
" \n"
" 0000A82F F3/ 48/ 0F 2C F6 cvttss2si rsi, xmm6 \n"
" 0000A834 F2/ 48/ 0F 2C F6 cvttsd2si rsi, xmm6 \n"
" \n"
" 0000A839 F3/ 48/ 0F 2A F6 cvtsi2ss xmm6, rsi \n"
" 0000A83E F2/ 48/ 0F 2A F6 cvtsi2sd xmm6, rsi \n"
" \n"
" \n"
" ; Between: xmm6 and rdi \n"
" 0000A843 F3/ 0F 11 77 movss dword ptr [rdi - 4], xmm6 \n"
" FC \n"
" 0000A848 F2/ 0F 11 77 movsd qword ptr [rdi + 4], xmm6 \n"
" 04 \n"
" \n"
" 0000A84D F3/ 0F 10 77 movss xmm6, dword ptr [rdi - 4] \n"
" FC \n"
" 0000A852 F2/ 0F 10 77 movsd xmm6, qword ptr [rdi + 4] \n"
" 04 \n"
" 0000A857 F3/ 48/ 0F 2A 77 cvtsi2ss xmm6, qword ptr [rdi - 4] \n"
" FC \n"
" 0000A85D F2/ 0F 2A 77 cvtsi2sd xmm6, dword ptr [rdi + 4] \n"
" 04 \n"
" \n"
" 0000A862 F3/ 0F 2C FE cvttss2si edi, xmm6 \n"
" 0000A866 F2/ 0F 2C FE cvttsd2si edi, xmm6 \n"
" \n"
" 0000A86A F3/ 0F 2A F7 cvtsi2ss xmm6, edi \n"
" 0000A86E F2/ 0F 2A F7 cvtsi2sd xmm6, edi \n"
" \n"
" 0000A872 F3/ 48/ 0F 2C FE cvttss2si rdi, xmm6 \n"
" 0000A877 F2/ 48/ 0F 2C FE cvttsd2si rdi, xmm6 \n"
" \n"
" 0000A87C F3/ 48/ 0F 2A F7 cvtsi2ss xmm6, rdi \n"
" 0000A881 F2/ 48/ 0F 2A F7 cvtsi2sd xmm6, rdi \n"
" \n"
" \n"
" ; Between: xmm6 and r8 \n"
" 0000A886 F3/ 41/ 0F 11 70 movss dword ptr [r8 - 4], xmm6 \n"
" FC \n"
" 0000A88C F2/ 41/ 0F 11 70 movsd qword ptr [r8 + 4], xmm6 \n"
" 04 \n"
" \n"
" 0000A892 F3/ 41/ 0F 10 70 movss xmm6, dword ptr [r8 - 4] \n"
" FC \n"
" 0000A898 F2/ 41/ 0F 10 70 movsd xmm6, qword ptr [r8 + 4] \n"
" 04 \n"
" 0000A89E F3/ 49/ 0F 2A 70 cvtsi2ss xmm6, qword ptr [r8 - 4] \n"
" FC \n"
" 0000A8A4 F2/ 41/ 0F 2A 70 cvtsi2sd xmm6, dword ptr [r8 + 4] \n"
" 04 \n"
" \n"
" 0000A8AA F3/ 44/ 0F 2C C6 cvttss2si r8d, xmm6 \n"
" 0000A8AF F2/ 44/ 0F 2C C6 cvttsd2si r8d, xmm6 \n"
" \n"
" 0000A8B4 F3/ 41/ 0F 2A F0 cvtsi2ss xmm6, r8d \n"
" 0000A8B9 F2/ 41/ 0F 2A F0 cvtsi2sd xmm6, r8d \n"
" \n"
" 0000A8BE F3/ 4C/ 0F 2C C6 cvttss2si r8, xmm6 \n"
" 0000A8C3 F2/ 4C/ 0F 2C C6 cvttsd2si r8, xmm6 \n"
" \n"
" 0000A8C8 F3/ 49/ 0F 2A F0 cvtsi2ss xmm6, r8 \n"
" 0000A8CD F2/ 49/ 0F 2A F0 cvtsi2sd xmm6, r8 \n"
" \n"
" \n"
" ; Between: xmm6 and r9 \n"
" 0000A8D2 F3/ 41/ 0F 11 71 movss dword ptr [r9 - 4], xmm6 \n"
" FC \n"
" 0000A8D8 F2/ 41/ 0F 11 71 movsd qword ptr [r9 + 4], xmm6 \n"
" 04 \n"
" \n"
" 0000A8DE F3/ 41/ 0F 10 71 movss xmm6, dword ptr [r9 - 4] \n"
" FC \n"
" 0000A8E4 F2/ 41/ 0F 10 71 movsd xmm6, qword ptr [r9 + 4] \n"
" 04 \n"
" 0000A8EA F3/ 49/ 0F 2A 71 cvtsi2ss xmm6, qword ptr [r9 - 4] \n"
" FC \n"
" 0000A8F0 F2/ 41/ 0F 2A 71 cvtsi2sd xmm6, dword ptr [r9 + 4] \n"
" 04 \n"
" \n"
" 0000A8F6 F3/ 44/ 0F 2C CE cvttss2si r9d, xmm6 \n"
" 0000A8FB F2/ 44/ 0F 2C CE cvttsd2si r9d, xmm6 \n"
" \n"
" 0000A900 F3/ 41/ 0F 2A F1 cvtsi2ss xmm6, r9d \n"
" 0000A905 F2/ 41/ 0F 2A F1 cvtsi2sd xmm6, r9d \n"
" \n"
" 0000A90A F3/ 4C/ 0F 2C CE cvttss2si r9, xmm6 \n"
" 0000A90F F2/ 4C/ 0F 2C CE cvttsd2si r9, xmm6 \n"
" \n"
" 0000A914 F3/ 49/ 0F 2A F1 cvtsi2ss xmm6, r9 \n"
" 0000A919 F2/ 49/ 0F 2A F1 cvtsi2sd xmm6, r9 \n"
" \n"
" \n"
" ; Between: xmm6 and r10 \n"
" 0000A91E F3/ 41/ 0F 11 72 movss dword ptr [r10 - 4], xmm6 \n"
" FC \n"
" 0000A924 F2/ 41/ 0F 11 72 movsd qword ptr [r10 + 4], xmm6 \n"
" 04 \n"
" \n"
" 0000A92A F3/ 41/ 0F 10 72 movss xmm6, dword ptr [r10 - 4] \n"
" FC \n"
" 0000A930 F2/ 41/ 0F 10 72 movsd xmm6, qword ptr [r10 + 4] \n"
" 04 \n"
" 0000A936 F3/ 49/ 0F 2A 72 cvtsi2ss xmm6, qword ptr [r10 - 4] \n"
" FC \n"
" 0000A93C F2/ 41/ 0F 2A 72 cvtsi2sd xmm6, dword ptr [r10 + 4] \n"
" 04 \n"
" \n"
" 0000A942 F3/ 44/ 0F 2C D6 cvttss2si r10d, xmm6 \n"
" 0000A947 F2/ 44/ 0F 2C D6 cvttsd2si r10d, xmm6 \n"
" \n"
" 0000A94C F3/ 41/ 0F 2A F2 cvtsi2ss xmm6, r10d \n"
" 0000A951 F2/ 41/ 0F 2A F2 cvtsi2sd xmm6, r10d \n"
" \n"
" 0000A956 F3/ 4C/ 0F 2C D6 cvttss2si r10, xmm6 \n"
" 0000A95B F2/ 4C/ 0F 2C D6 cvttsd2si r10, xmm6 \n"
" \n"
" 0000A960 F3/ 49/ 0F 2A F2 cvtsi2ss xmm6, r10 \n"
" 0000A965 F2/ 49/ 0F 2A F2 cvtsi2sd xmm6, r10 \n"
" \n"
" \n"
" ; Between: xmm6 and r11 \n"
" 0000A96A F3/ 41/ 0F 11 73 movss dword ptr [r11 - 4], xmm6 \n"
" FC \n"
" 0000A970 F2/ 41/ 0F 11 73 movsd qword ptr [r11 + 4], xmm6 \n"
" 04 \n"
" \n"
" 0000A976 F3/ 41/ 0F 10 73 movss xmm6, dword ptr [r11 - 4] \n"
" FC \n"
" 0000A97C F2/ 41/ 0F 10 73 movsd xmm6, qword ptr [r11 + 4] \n"
" 04 \n"
" 0000A982 F3/ 49/ 0F 2A 73 cvtsi2ss xmm6, qword ptr [r11 - 4] \n"
" FC \n"
" 0000A988 F2/ 41/ 0F 2A 73 cvtsi2sd xmm6, dword ptr [r11 + 4] \n"
" 04 \n"
" \n"
" 0000A98E F3/ 44/ 0F 2C DE cvttss2si r11d, xmm6 \n"
" 0000A993 F2/ 44/ 0F 2C DE cvttsd2si r11d, xmm6 \n"
" \n"
" 0000A998 F3/ 41/ 0F 2A F3 cvtsi2ss xmm6, r11d \n"
" 0000A99D F2/ 41/ 0F 2A F3 cvtsi2sd xmm6, r11d \n"
" \n"
" 0000A9A2 F3/ 4C/ 0F 2C DE cvttss2si r11, xmm6 \n"
" 0000A9A7 F2/ 4C/ 0F 2C DE cvttsd2si r11, xmm6 \n"
" \n"
" 0000A9AC F3/ 49/ 0F 2A F3 cvtsi2ss xmm6, r11 \n"
" 0000A9B1 F2/ 49/ 0F 2A F3 cvtsi2sd xmm6, r11 \n"
" \n"
" \n"
" ; Between: xmm6 and r12 \n"
" 0000A9B6 F3/ 41/ 0F 11 74 movss dword ptr [r12 - 4], xmm6 \n"
" 24 FC \n"
" 0000A9BD F2/ 41/ 0F 11 74 movsd qword ptr [r12 + 4], xmm6 \n"
" 24 04 \n"
" \n"
" 0000A9C4 F3/ 41/ 0F 10 74 movss xmm6, dword ptr [r12 - 4] \n"
" 24 FC \n"
" 0000A9CB F2/ 41/ 0F 10 74 movsd xmm6, qword ptr [r12 + 4] \n"
" 24 04 \n"
" 0000A9D2 F3/ 49/ 0F 2A 74 cvtsi2ss xmm6, qword ptr [r12 - 4] \n"
" 24 FC \n"
" 0000A9D9 F2/ 41/ 0F 2A 74 cvtsi2sd xmm6, dword ptr [r12 + 4] \n"
" 24 04 \n"
" \n"
" 0000A9E0 F3/ 44/ 0F 2C E6 cvttss2si r12d, xmm6 \n"
" 0000A9E5 F2/ 44/ 0F 2C E6 cvttsd2si r12d, xmm6 \n"
" \n"
" 0000A9EA F3/ 41/ 0F 2A F4 cvtsi2ss xmm6, r12d \n"
" 0000A9EF F2/ 41/ 0F 2A F4 cvtsi2sd xmm6, r12d \n"
" \n"
" 0000A9F4 F3/ 4C/ 0F 2C E6 cvttss2si r12, xmm6 \n"
" 0000A9F9 F2/ 4C/ 0F 2C E6 cvttsd2si r12, xmm6 \n"
" \n"
" 0000A9FE F3/ 49/ 0F 2A F4 cvtsi2ss xmm6, r12 \n"
" 0000AA03 F2/ 49/ 0F 2A F4 cvtsi2sd xmm6, r12 \n"
" \n"
" \n"
" ; Between: xmm6 and r13 \n"
" 0000AA08 F3/ 41/ 0F 11 75 movss dword ptr [r13 - 4], xmm6 \n"
" FC \n"
" 0000AA0E F2/ 41/ 0F 11 75 movsd qword ptr [r13 + 4], xmm6 \n"
" 04 \n"
" \n"
" 0000AA14 F3/ 41/ 0F 10 75 movss xmm6, dword ptr [r13 - 4] \n"
" FC \n"
" 0000AA1A F2/ 41/ 0F 10 75 movsd xmm6, qword ptr [r13 + 4] \n"
" 04 \n"
" 0000AA20 F3/ 49/ 0F 2A 75 cvtsi2ss xmm6, qword ptr [r13 - 4] \n"
" FC \n"
" 0000AA26 F2/ 41/ 0F 2A 75 cvtsi2sd xmm6, dword ptr [r13 + 4] \n"
" 04 \n"
" \n"
" 0000AA2C F3/ 44/ 0F 2C EE cvttss2si r13d, xmm6 \n"
" 0000AA31 F2/ 44/ 0F 2C EE cvttsd2si r13d, xmm6 \n"
" \n"
" 0000AA36 F3/ 41/ 0F 2A F5 cvtsi2ss xmm6, r13d \n"
" 0000AA3B F2/ 41/ 0F 2A F5 cvtsi2sd xmm6, r13d \n"
" \n"
" 0000AA40 F3/ 4C/ 0F 2C EE cvttss2si r13, xmm6 \n"
" 0000AA45 F2/ 4C/ 0F 2C EE cvttsd2si r13, xmm6 \n"
" \n"
" 0000AA4A F3/ 49/ 0F 2A F5 cvtsi2ss xmm6, r13 \n"
" 0000AA4F F2/ 49/ 0F 2A F5 cvtsi2sd xmm6, r13 \n"
" \n"
" \n"
" ; Between: xmm6 and r14 \n"
" 0000AA54 F3/ 41/ 0F 11 76 movss dword ptr [r14 - 4], xmm6 \n"
" FC \n"
" 0000AA5A F2/ 41/ 0F 11 76 movsd qword ptr [r14 + 4], xmm6 \n"
" 04 \n"
" \n"
" 0000AA60 F3/ 41/ 0F 10 76 movss xmm6, dword ptr [r14 - 4] \n"
" FC \n"
" 0000AA66 F2/ 41/ 0F 10 76 movsd xmm6, qword ptr [r14 + 4] \n"
" 04 \n"
" 0000AA6C F3/ 49/ 0F 2A 76 cvtsi2ss xmm6, qword ptr [r14 - 4] \n"
" FC \n"
" 0000AA72 F2/ 41/ 0F 2A 76 cvtsi2sd xmm6, dword ptr [r14 + 4] \n"
" 04 \n"
" \n"
" 0000AA78 F3/ 44/ 0F 2C F6 cvttss2si r14d, xmm6 \n"
" 0000AA7D F2/ 44/ 0F 2C F6 cvttsd2si r14d, xmm6 \n"
" \n"
" 0000AA82 F3/ 41/ 0F 2A F6 cvtsi2ss xmm6, r14d \n"
" 0000AA87 F2/ 41/ 0F 2A F6 cvtsi2sd xmm6, r14d \n"
" \n"
" 0000AA8C F3/ 4C/ 0F 2C F6 cvttss2si r14, xmm6 \n"
" 0000AA91 F2/ 4C/ 0F 2C F6 cvttsd2si r14, xmm6 \n"
" \n"
" 0000AA96 F3/ 49/ 0F 2A F6 cvtsi2ss xmm6, r14 \n"
" 0000AA9B F2/ 49/ 0F 2A F6 cvtsi2sd xmm6, r14 \n"
" \n"
" \n"
" ; Between: xmm6 and r15 \n"
" 0000AAA0 F3/ 41/ 0F 11 77 movss dword ptr [r15 - 4], xmm6 \n"
" FC \n"
" 0000AAA6 F2/ 41/ 0F 11 77 movsd qword ptr [r15 + 4], xmm6 \n"
" 04 \n"
" \n"
" 0000AAAC F3/ 41/ 0F 10 77 movss xmm6, dword ptr [r15 - 4] \n"
" FC \n"
" 0000AAB2 F2/ 41/ 0F 10 77 movsd xmm6, qword ptr [r15 + 4] \n"
" 04 \n"
" 0000AAB8 F3/ 49/ 0F 2A 77 cvtsi2ss xmm6, qword ptr [r15 - 4] \n"
" FC \n"
" 0000AABE F2/ 41/ 0F 2A 77 cvtsi2sd xmm6, dword ptr [r15 + 4] \n"
" 04 \n"
" \n"
" 0000AAC4 F3/ 44/ 0F 2C FE cvttss2si r15d, xmm6 \n"
" 0000AAC9 F2/ 44/ 0F 2C FE cvttsd2si r15d, xmm6 \n"
" \n"
" 0000AACE F3/ 41/ 0F 2A F7 cvtsi2ss xmm6, r15d \n"
" 0000AAD3 F2/ 41/ 0F 2A F7 cvtsi2sd xmm6, r15d \n"
" \n"
" 0000AAD8 F3/ 4C/ 0F 2C FE cvttss2si r15, xmm6 \n"
" 0000AADD F2/ 4C/ 0F 2C FE cvttsd2si r15, xmm6 \n"
" \n"
" 0000AAE2 F3/ 49/ 0F 2A F7 cvtsi2ss xmm6, r15 \n"
" 0000AAE7 F2/ 49/ 0F 2A F7 cvtsi2sd xmm6, r15 \n"
" \n"
" \n"
" ; Between: xmm7 and rax \n"
" 0000AAEC F3/ 0F 11 78 movss dword ptr [rax - 4], xmm7 \n"
" FC \n"
" 0000AAF1 F2/ 0F 11 78 movsd qword ptr [rax + 4], xmm7 \n"
" 04 \n"
" \n"
" 0000AAF6 F3/ 0F 10 78 movss xmm7, dword ptr [rax - 4] \n"
" FC \n"
" 0000AAFB F2/ 0F 10 78 movsd xmm7, qword ptr [rax + 4] \n"
" 04 \n"
" 0000AB00 F3/ 48/ 0F 2A 78 cvtsi2ss xmm7, qword ptr [rax - 4] \n"
" FC \n"
" 0000AB06 F2/ 0F 2A 78 cvtsi2sd xmm7, dword ptr [rax + 4] \n"
" 04 \n"
" \n"
" 0000AB0B F3/ 0F 2C C7 cvttss2si eax, xmm7 \n"
" 0000AB0F F2/ 0F 2C C7 cvttsd2si eax, xmm7 \n"
" \n"
" 0000AB13 F3/ 0F 2A F8 cvtsi2ss xmm7, eax \n"
" 0000AB17 F2/ 0F 2A F8 cvtsi2sd xmm7, eax \n"
" \n"
" 0000AB1B F3/ 48/ 0F 2C C7 cvttss2si rax, xmm7 \n"
" 0000AB20 F2/ 48/ 0F 2C C7 cvttsd2si rax, xmm7 \n"
" \n"
" 0000AB25 F3/ 48/ 0F 2A F8 cvtsi2ss xmm7, rax \n"
" 0000AB2A F2/ 48/ 0F 2A F8 cvtsi2sd xmm7, rax \n"
" \n"
" \n"
" ; Between: xmm7 and rcx \n"
" 0000AB2F F3/ 0F 11 79 movss dword ptr [rcx - 4], xmm7 \n"
" FC \n"
" 0000AB34 F2/ 0F 11 79 movsd qword ptr [rcx + 4], xmm7 \n"
" 04 \n"
" \n"
" 0000AB39 F3/ 0F 10 79 movss xmm7, dword ptr [rcx - 4] \n"
" FC \n"
" 0000AB3E F2/ 0F 10 79 movsd xmm7, qword ptr [rcx + 4] \n"
" 04 \n"
" 0000AB43 F3/ 48/ 0F 2A 79 cvtsi2ss xmm7, qword ptr [rcx - 4] \n"
" FC \n"
" 0000AB49 F2/ 0F 2A 79 cvtsi2sd xmm7, dword ptr [rcx + 4] \n"
" 04 \n"
" \n"
" 0000AB4E F3/ 0F 2C CF cvttss2si ecx, xmm7 \n"
" 0000AB52 F2/ 0F 2C CF cvttsd2si ecx, xmm7 \n"
" \n"
" 0000AB56 F3/ 0F 2A F9 cvtsi2ss xmm7, ecx \n"
" 0000AB5A F2/ 0F 2A F9 cvtsi2sd xmm7, ecx \n"
" \n"
" 0000AB5E F3/ 48/ 0F 2C CF cvttss2si rcx, xmm7 \n"
" 0000AB63 F2/ 48/ 0F 2C CF cvttsd2si rcx, xmm7 \n"
" \n"
" 0000AB68 F3/ 48/ 0F 2A F9 cvtsi2ss xmm7, rcx \n"
" 0000AB6D F2/ 48/ 0F 2A F9 cvtsi2sd xmm7, rcx \n"
" \n"
" \n"
" ; Between: xmm7 and rdx \n"
" 0000AB72 F3/ 0F 11 7A movss dword ptr [rdx - 4], xmm7 \n"
" FC \n"
" 0000AB77 F2/ 0F 11 7A movsd qword ptr [rdx + 4], xmm7 \n"
" 04 \n"
" \n"
" 0000AB7C F3/ 0F 10 7A movss xmm7, dword ptr [rdx - 4] \n"
" FC \n"
" 0000AB81 F2/ 0F 10 7A movsd xmm7, qword ptr [rdx + 4] \n"
" 04 \n"
" 0000AB86 F3/ 48/ 0F 2A 7A cvtsi2ss xmm7, qword ptr [rdx - 4] \n"
" FC \n"
" 0000AB8C F2/ 0F 2A 7A cvtsi2sd xmm7, dword ptr [rdx + 4] \n"
" 04 \n"
" \n"
" 0000AB91 F3/ 0F 2C D7 cvttss2si edx, xmm7 \n"
" 0000AB95 F2/ 0F 2C D7 cvttsd2si edx, xmm7 \n"
" \n"
" 0000AB99 F3/ 0F 2A FA cvtsi2ss xmm7, edx \n"
" 0000AB9D F2/ 0F 2A FA cvtsi2sd xmm7, edx \n"
" \n"
" 0000ABA1 F3/ 48/ 0F 2C D7 cvttss2si rdx, xmm7 \n"
" 0000ABA6 F2/ 48/ 0F 2C D7 cvttsd2si rdx, xmm7 \n"
" \n"
" 0000ABAB F3/ 48/ 0F 2A FA cvtsi2ss xmm7, rdx \n"
" 0000ABB0 F2/ 48/ 0F 2A FA cvtsi2sd xmm7, rdx \n"
" \n"
" \n"
" ; Between: xmm7 and rbx \n"
" 0000ABB5 F3/ 0F 11 7B movss dword ptr [rbx - 4], xmm7 \n"
" FC \n"
" 0000ABBA F2/ 0F 11 7B movsd qword ptr [rbx + 4], xmm7 \n"
" 04 \n"
" \n"
" 0000ABBF F3/ 0F 10 7B movss xmm7, dword ptr [rbx - 4] \n"
" FC \n";
ml64Output +=
" 0000ABC4 F2/ 0F 10 7B movsd xmm7, qword ptr [rbx + 4] \n"
" 04 \n"
" 0000ABC9 F3/ 48/ 0F 2A 7B cvtsi2ss xmm7, qword ptr [rbx - 4] \n"
" FC \n"
" 0000ABCF F2/ 0F 2A 7B cvtsi2sd xmm7, dword ptr [rbx + 4] \n"
" 04 \n"
" \n"
" 0000ABD4 F3/ 0F 2C DF cvttss2si ebx, xmm7 \n"
" 0000ABD8 F2/ 0F 2C DF cvttsd2si ebx, xmm7 \n"
" \n"
" 0000ABDC F3/ 0F 2A FB cvtsi2ss xmm7, ebx \n"
" 0000ABE0 F2/ 0F 2A FB cvtsi2sd xmm7, ebx \n"
" \n"
" 0000ABE4 F3/ 48/ 0F 2C DF cvttss2si rbx, xmm7 \n"
" 0000ABE9 F2/ 48/ 0F 2C DF cvttsd2si rbx, xmm7 \n"
" \n"
" 0000ABEE F3/ 48/ 0F 2A FB cvtsi2ss xmm7, rbx \n"
" 0000ABF3 F2/ 48/ 0F 2A FB cvtsi2sd xmm7, rbx \n"
" \n"
" \n"
" ; Between: xmm7 and rsp \n"
" 0000ABF8 F3/ 0F 11 7C 24 movss dword ptr [rsp - 4], xmm7 \n"
" FC \n"
" 0000ABFE F2/ 0F 11 7C 24 movsd qword ptr [rsp + 4], xmm7 \n"
" 04 \n"
" \n"
" 0000AC04 F3/ 0F 10 7C 24 movss xmm7, dword ptr [rsp - 4] \n"
" FC \n"
" 0000AC0A F2/ 0F 10 7C 24 movsd xmm7, qword ptr [rsp + 4] \n"
" 04 \n"
" 0000AC10 F3/ 48/ 0F 2A 7C cvtsi2ss xmm7, qword ptr [rsp - 4] \n"
" 24 FC \n"
" 0000AC17 F2/ 0F 2A 7C 24 cvtsi2sd xmm7, dword ptr [rsp + 4] \n"
" 04 \n"
" \n"
" 0000AC1D F3/ 0F 2C E7 cvttss2si esp, xmm7 \n"
" 0000AC21 F2/ 0F 2C E7 cvttsd2si esp, xmm7 \n"
" \n"
" 0000AC25 F3/ 0F 2A FC cvtsi2ss xmm7, esp \n"
" 0000AC29 F2/ 0F 2A FC cvtsi2sd xmm7, esp \n"
" \n"
" 0000AC2D F3/ 48/ 0F 2C E7 cvttss2si rsp, xmm7 \n"
" 0000AC32 F2/ 48/ 0F 2C E7 cvttsd2si rsp, xmm7 \n"
" \n"
" 0000AC37 F3/ 48/ 0F 2A FC cvtsi2ss xmm7, rsp \n"
" 0000AC3C F2/ 48/ 0F 2A FC cvtsi2sd xmm7, rsp \n"
" \n"
" \n"
" ; Between: xmm7 and rbp \n"
" 0000AC41 F3/ 0F 11 7D movss dword ptr [rbp - 4], xmm7 \n"
" FC \n"
" 0000AC46 F2/ 0F 11 7D movsd qword ptr [rbp + 4], xmm7 \n"
" 04 \n"
" \n"
" 0000AC4B F3/ 0F 10 7D movss xmm7, dword ptr [rbp - 4] \n"
" FC \n"
" 0000AC50 F2/ 0F 10 7D movsd xmm7, qword ptr [rbp + 4] \n"
" 04 \n"
" 0000AC55 F3/ 48/ 0F 2A 7D cvtsi2ss xmm7, qword ptr [rbp - 4] \n"
" FC \n"
" 0000AC5B F2/ 0F 2A 7D cvtsi2sd xmm7, dword ptr [rbp + 4] \n"
" 04 \n"
" \n"
" 0000AC60 F3/ 0F 2C EF cvttss2si ebp, xmm7 \n"
" 0000AC64 F2/ 0F 2C EF cvttsd2si ebp, xmm7 \n"
" \n"
" 0000AC68 F3/ 0F 2A FD cvtsi2ss xmm7, ebp \n"
" 0000AC6C F2/ 0F 2A FD cvtsi2sd xmm7, ebp \n"
" \n"
" 0000AC70 F3/ 48/ 0F 2C EF cvttss2si rbp, xmm7 \n"
" 0000AC75 F2/ 48/ 0F 2C EF cvttsd2si rbp, xmm7 \n"
" \n"
" 0000AC7A F3/ 48/ 0F 2A FD cvtsi2ss xmm7, rbp \n"
" 0000AC7F F2/ 48/ 0F 2A FD cvtsi2sd xmm7, rbp \n"
" \n"
" \n"
" ; Between: xmm7 and rsi \n"
" 0000AC84 F3/ 0F 11 7E movss dword ptr [rsi - 4], xmm7 \n"
" FC \n"
" 0000AC89 F2/ 0F 11 7E movsd qword ptr [rsi + 4], xmm7 \n"
" 04 \n"
" \n"
" 0000AC8E F3/ 0F 10 7E movss xmm7, dword ptr [rsi - 4] \n"
" FC \n"
" 0000AC93 F2/ 0F 10 7E movsd xmm7, qword ptr [rsi + 4] \n"
" 04 \n"
" 0000AC98 F3/ 48/ 0F 2A 7E cvtsi2ss xmm7, qword ptr [rsi - 4] \n"
" FC \n"
" 0000AC9E F2/ 0F 2A 7E cvtsi2sd xmm7, dword ptr [rsi + 4] \n"
" 04 \n"
" \n"
" 0000ACA3 F3/ 0F 2C F7 cvttss2si esi, xmm7 \n"
" 0000ACA7 F2/ 0F 2C F7 cvttsd2si esi, xmm7 \n"
" \n"
" 0000ACAB F3/ 0F 2A FE cvtsi2ss xmm7, esi \n"
" 0000ACAF F2/ 0F 2A FE cvtsi2sd xmm7, esi \n"
" \n"
" 0000ACB3 F3/ 48/ 0F 2C F7 cvttss2si rsi, xmm7 \n"
" 0000ACB8 F2/ 48/ 0F 2C F7 cvttsd2si rsi, xmm7 \n"
" \n"
" 0000ACBD F3/ 48/ 0F 2A FE cvtsi2ss xmm7, rsi \n"
" 0000ACC2 F2/ 48/ 0F 2A FE cvtsi2sd xmm7, rsi \n"
" \n"
" \n"
" ; Between: xmm7 and rdi \n"
" 0000ACC7 F3/ 0F 11 7F movss dword ptr [rdi - 4], xmm7 \n"
" FC \n"
" 0000ACCC F2/ 0F 11 7F movsd qword ptr [rdi + 4], xmm7 \n"
" 04 \n"
" \n"
" 0000ACD1 F3/ 0F 10 7F movss xmm7, dword ptr [rdi - 4] \n"
" FC \n"
" 0000ACD6 F2/ 0F 10 7F movsd xmm7, qword ptr [rdi + 4] \n"
" 04 \n"
" 0000ACDB F3/ 48/ 0F 2A 7F cvtsi2ss xmm7, qword ptr [rdi - 4] \n"
" FC \n"
" 0000ACE1 F2/ 0F 2A 7F cvtsi2sd xmm7, dword ptr [rdi + 4] \n"
" 04 \n"
" \n"
" 0000ACE6 F3/ 0F 2C FF cvttss2si edi, xmm7 \n"
" 0000ACEA F2/ 0F 2C FF cvttsd2si edi, xmm7 \n"
" \n"
" 0000ACEE F3/ 0F 2A FF cvtsi2ss xmm7, edi \n"
" 0000ACF2 F2/ 0F 2A FF cvtsi2sd xmm7, edi \n"
" \n"
" 0000ACF6 F3/ 48/ 0F 2C FF cvttss2si rdi, xmm7 \n"
" 0000ACFB F2/ 48/ 0F 2C FF cvttsd2si rdi, xmm7 \n"
" \n"
" 0000AD00 F3/ 48/ 0F 2A FF cvtsi2ss xmm7, rdi \n"
" 0000AD05 F2/ 48/ 0F 2A FF cvtsi2sd xmm7, rdi \n"
" \n"
" \n"
" ; Between: xmm7 and r8 \n"
" 0000AD0A F3/ 41/ 0F 11 78 movss dword ptr [r8 - 4], xmm7 \n"
" FC \n"
" 0000AD10 F2/ 41/ 0F 11 78 movsd qword ptr [r8 + 4], xmm7 \n"
" 04 \n"
" \n"
" 0000AD16 F3/ 41/ 0F 10 78 movss xmm7, dword ptr [r8 - 4] \n"
" FC \n"
" 0000AD1C F2/ 41/ 0F 10 78 movsd xmm7, qword ptr [r8 + 4] \n"
" 04 \n"
" 0000AD22 F3/ 49/ 0F 2A 78 cvtsi2ss xmm7, qword ptr [r8 - 4] \n"
" FC \n"
" 0000AD28 F2/ 41/ 0F 2A 78 cvtsi2sd xmm7, dword ptr [r8 + 4] \n"
" 04 \n"
" \n"
" 0000AD2E F3/ 44/ 0F 2C C7 cvttss2si r8d, xmm7 \n"
" 0000AD33 F2/ 44/ 0F 2C C7 cvttsd2si r8d, xmm7 \n"
" \n"
" 0000AD38 F3/ 41/ 0F 2A F8 cvtsi2ss xmm7, r8d \n"
" 0000AD3D F2/ 41/ 0F 2A F8 cvtsi2sd xmm7, r8d \n"
" \n"
" 0000AD42 F3/ 4C/ 0F 2C C7 cvttss2si r8, xmm7 \n"
" 0000AD47 F2/ 4C/ 0F 2C C7 cvttsd2si r8, xmm7 \n"
" \n"
" 0000AD4C F3/ 49/ 0F 2A F8 cvtsi2ss xmm7, r8 \n"
" 0000AD51 F2/ 49/ 0F 2A F8 cvtsi2sd xmm7, r8 \n"
" \n"
" \n"
" ; Between: xmm7 and r9 \n"
" 0000AD56 F3/ 41/ 0F 11 79 movss dword ptr [r9 - 4], xmm7 \n"
" FC \n"
" 0000AD5C F2/ 41/ 0F 11 79 movsd qword ptr [r9 + 4], xmm7 \n"
" 04 \n"
" \n"
" 0000AD62 F3/ 41/ 0F 10 79 movss xmm7, dword ptr [r9 - 4] \n"
" FC \n"
" 0000AD68 F2/ 41/ 0F 10 79 movsd xmm7, qword ptr [r9 + 4] \n"
" 04 \n"
" 0000AD6E F3/ 49/ 0F 2A 79 cvtsi2ss xmm7, qword ptr [r9 - 4] \n"
" FC \n"
" 0000AD74 F2/ 41/ 0F 2A 79 cvtsi2sd xmm7, dword ptr [r9 + 4] \n"
" 04 \n"
" \n"
" 0000AD7A F3/ 44/ 0F 2C CF cvttss2si r9d, xmm7 \n"
" 0000AD7F F2/ 44/ 0F 2C CF cvttsd2si r9d, xmm7 \n"
" \n"
" 0000AD84 F3/ 41/ 0F 2A F9 cvtsi2ss xmm7, r9d \n"
" 0000AD89 F2/ 41/ 0F 2A F9 cvtsi2sd xmm7, r9d \n"
" \n"
" 0000AD8E F3/ 4C/ 0F 2C CF cvttss2si r9, xmm7 \n"
" 0000AD93 F2/ 4C/ 0F 2C CF cvttsd2si r9, xmm7 \n"
" \n"
" 0000AD98 F3/ 49/ 0F 2A F9 cvtsi2ss xmm7, r9 \n"
" 0000AD9D F2/ 49/ 0F 2A F9 cvtsi2sd xmm7, r9 \n"
" \n"
" \n"
" ; Between: xmm7 and r10 \n"
" 0000ADA2 F3/ 41/ 0F 11 7A movss dword ptr [r10 - 4], xmm7 \n"
" FC \n"
" 0000ADA8 F2/ 41/ 0F 11 7A movsd qword ptr [r10 + 4], xmm7 \n"
" 04 \n"
" \n"
" 0000ADAE F3/ 41/ 0F 10 7A movss xmm7, dword ptr [r10 - 4] \n"
" FC \n"
" 0000ADB4 F2/ 41/ 0F 10 7A movsd xmm7, qword ptr [r10 + 4] \n"
" 04 \n"
" 0000ADBA F3/ 49/ 0F 2A 7A cvtsi2ss xmm7, qword ptr [r10 - 4] \n"
" FC \n"
" 0000ADC0 F2/ 41/ 0F 2A 7A cvtsi2sd xmm7, dword ptr [r10 + 4] \n"
" 04 \n"
" \n"
" 0000ADC6 F3/ 44/ 0F 2C D7 cvttss2si r10d, xmm7 \n"
" 0000ADCB F2/ 44/ 0F 2C D7 cvttsd2si r10d, xmm7 \n"
" \n"
" 0000ADD0 F3/ 41/ 0F 2A FA cvtsi2ss xmm7, r10d \n"
" 0000ADD5 F2/ 41/ 0F 2A FA cvtsi2sd xmm7, r10d \n"
" \n"
" 0000ADDA F3/ 4C/ 0F 2C D7 cvttss2si r10, xmm7 \n"
" 0000ADDF F2/ 4C/ 0F 2C D7 cvttsd2si r10, xmm7 \n"
" \n"
" 0000ADE4 F3/ 49/ 0F 2A FA cvtsi2ss xmm7, r10 \n"
" 0000ADE9 F2/ 49/ 0F 2A FA cvtsi2sd xmm7, r10 \n"
" \n"
" \n"
" ; Between: xmm7 and r11 \n"
" 0000ADEE F3/ 41/ 0F 11 7B movss dword ptr [r11 - 4], xmm7 \n"
" FC \n"
" 0000ADF4 F2/ 41/ 0F 11 7B movsd qword ptr [r11 + 4], xmm7 \n"
" 04 \n"
" \n"
" 0000ADFA F3/ 41/ 0F 10 7B movss xmm7, dword ptr [r11 - 4] \n"
" FC \n"
" 0000AE00 F2/ 41/ 0F 10 7B movsd xmm7, qword ptr [r11 + 4] \n"
" 04 \n"
" 0000AE06 F3/ 49/ 0F 2A 7B cvtsi2ss xmm7, qword ptr [r11 - 4] \n"
" FC \n"
" 0000AE0C F2/ 41/ 0F 2A 7B cvtsi2sd xmm7, dword ptr [r11 + 4] \n"
" 04 \n"
" \n"
" 0000AE12 F3/ 44/ 0F 2C DF cvttss2si r11d, xmm7 \n"
" 0000AE17 F2/ 44/ 0F 2C DF cvttsd2si r11d, xmm7 \n"
" \n"
" 0000AE1C F3/ 41/ 0F 2A FB cvtsi2ss xmm7, r11d \n"
" 0000AE21 F2/ 41/ 0F 2A FB cvtsi2sd xmm7, r11d \n"
" \n"
" 0000AE26 F3/ 4C/ 0F 2C DF cvttss2si r11, xmm7 \n"
" 0000AE2B F2/ 4C/ 0F 2C DF cvttsd2si r11, xmm7 \n"
" \n"
" 0000AE30 F3/ 49/ 0F 2A FB cvtsi2ss xmm7, r11 \n"
" 0000AE35 F2/ 49/ 0F 2A FB cvtsi2sd xmm7, r11 \n"
" \n"
" \n"
" ; Between: xmm7 and r12 \n"
" 0000AE3A F3/ 41/ 0F 11 7C movss dword ptr [r12 - 4], xmm7 \n"
" 24 FC \n"
" 0000AE41 F2/ 41/ 0F 11 7C movsd qword ptr [r12 + 4], xmm7 \n"
" 24 04 \n"
" \n"
" 0000AE48 F3/ 41/ 0F 10 7C movss xmm7, dword ptr [r12 - 4] \n"
" 24 FC \n"
" 0000AE4F F2/ 41/ 0F 10 7C movsd xmm7, qword ptr [r12 + 4] \n"
" 24 04 \n"
" 0000AE56 F3/ 49/ 0F 2A 7C cvtsi2ss xmm7, qword ptr [r12 - 4] \n"
" 24 FC \n"
" 0000AE5D F2/ 41/ 0F 2A 7C cvtsi2sd xmm7, dword ptr [r12 + 4] \n"
" 24 04 \n"
" \n"
" 0000AE64 F3/ 44/ 0F 2C E7 cvttss2si r12d, xmm7 \n"
" 0000AE69 F2/ 44/ 0F 2C E7 cvttsd2si r12d, xmm7 \n"
" \n"
" 0000AE6E F3/ 41/ 0F 2A FC cvtsi2ss xmm7, r12d \n"
" 0000AE73 F2/ 41/ 0F 2A FC cvtsi2sd xmm7, r12d \n"
" \n"
" 0000AE78 F3/ 4C/ 0F 2C E7 cvttss2si r12, xmm7 \n"
" 0000AE7D F2/ 4C/ 0F 2C E7 cvttsd2si r12, xmm7 \n"
" \n"
" 0000AE82 F3/ 49/ 0F 2A FC cvtsi2ss xmm7, r12 \n"
" 0000AE87 F2/ 49/ 0F 2A FC cvtsi2sd xmm7, r12 \n"
" \n"
" \n"
" ; Between: xmm7 and r13 \n"
" 0000AE8C F3/ 41/ 0F 11 7D movss dword ptr [r13 - 4], xmm7 \n"
" FC \n"
" 0000AE92 F2/ 41/ 0F 11 7D movsd qword ptr [r13 + 4], xmm7 \n"
" 04 \n"
" \n"
" 0000AE98 F3/ 41/ 0F 10 7D movss xmm7, dword ptr [r13 - 4] \n"
" FC \n"
" 0000AE9E F2/ 41/ 0F 10 7D movsd xmm7, qword ptr [r13 + 4] \n"
" 04 \n"
" 0000AEA4 F3/ 49/ 0F 2A 7D cvtsi2ss xmm7, qword ptr [r13 - 4] \n"
" FC \n"
" 0000AEAA F2/ 41/ 0F 2A 7D cvtsi2sd xmm7, dword ptr [r13 + 4] \n"
" 04 \n"
" \n"
" 0000AEB0 F3/ 44/ 0F 2C EF cvttss2si r13d, xmm7 \n"
" 0000AEB5 F2/ 44/ 0F 2C EF cvttsd2si r13d, xmm7 \n"
" \n"
" 0000AEBA F3/ 41/ 0F 2A FD cvtsi2ss xmm7, r13d \n"
" 0000AEBF F2/ 41/ 0F 2A FD cvtsi2sd xmm7, r13d \n"
" \n"
" 0000AEC4 F3/ 4C/ 0F 2C EF cvttss2si r13, xmm7 \n"
" 0000AEC9 F2/ 4C/ 0F 2C EF cvttsd2si r13, xmm7 \n"
" \n"
" 0000AECE F3/ 49/ 0F 2A FD cvtsi2ss xmm7, r13 \n"
" 0000AED3 F2/ 49/ 0F 2A FD cvtsi2sd xmm7, r13 \n"
" \n"
" \n"
" ; Between: xmm7 and r14 \n"
" 0000AED8 F3/ 41/ 0F 11 7E movss dword ptr [r14 - 4], xmm7 \n"
" FC \n"
" 0000AEDE F2/ 41/ 0F 11 7E movsd qword ptr [r14 + 4], xmm7 \n"
" 04 \n"
" \n"
" 0000AEE4 F3/ 41/ 0F 10 7E movss xmm7, dword ptr [r14 - 4] \n"
" FC \n"
" 0000AEEA F2/ 41/ 0F 10 7E movsd xmm7, qword ptr [r14 + 4] \n"
" 04 \n"
" 0000AEF0 F3/ 49/ 0F 2A 7E cvtsi2ss xmm7, qword ptr [r14 - 4] \n"
" FC \n"
" 0000AEF6 F2/ 41/ 0F 2A 7E cvtsi2sd xmm7, dword ptr [r14 + 4] \n"
" 04 \n"
" \n"
" 0000AEFC F3/ 44/ 0F 2C F7 cvttss2si r14d, xmm7 \n"
" 0000AF01 F2/ 44/ 0F 2C F7 cvttsd2si r14d, xmm7 \n"
" \n"
" 0000AF06 F3/ 41/ 0F 2A FE cvtsi2ss xmm7, r14d \n"
" 0000AF0B F2/ 41/ 0F 2A FE cvtsi2sd xmm7, r14d \n"
" \n"
" 0000AF10 F3/ 4C/ 0F 2C F7 cvttss2si r14, xmm7 \n"
" 0000AF15 F2/ 4C/ 0F 2C F7 cvttsd2si r14, xmm7 \n"
" \n"
" 0000AF1A F3/ 49/ 0F 2A FE cvtsi2ss xmm7, r14 \n"
" 0000AF1F F2/ 49/ 0F 2A FE cvtsi2sd xmm7, r14 \n"
" \n"
" \n"
" ; Between: xmm7 and r15 \n"
" 0000AF24 F3/ 41/ 0F 11 7F movss dword ptr [r15 - 4], xmm7 \n"
" FC \n"
" 0000AF2A F2/ 41/ 0F 11 7F movsd qword ptr [r15 + 4], xmm7 \n"
" 04 \n"
" \n"
" 0000AF30 F3/ 41/ 0F 10 7F movss xmm7, dword ptr [r15 - 4] \n"
" FC \n"
" 0000AF36 F2/ 41/ 0F 10 7F movsd xmm7, qword ptr [r15 + 4] \n"
" 04 \n"
" 0000AF3C F3/ 49/ 0F 2A 7F cvtsi2ss xmm7, qword ptr [r15 - 4] \n"
" FC \n"
" 0000AF42 F2/ 41/ 0F 2A 7F cvtsi2sd xmm7, dword ptr [r15 + 4] \n"
" 04 \n"
" \n"
" 0000AF48 F3/ 44/ 0F 2C FF cvttss2si r15d, xmm7 \n"
" 0000AF4D F2/ 44/ 0F 2C FF cvttsd2si r15d, xmm7 \n"
" \n"
" 0000AF52 F3/ 41/ 0F 2A FF cvtsi2ss xmm7, r15d \n"
" 0000AF57 F2/ 41/ 0F 2A FF cvtsi2sd xmm7, r15d \n"
" \n"
" 0000AF5C F3/ 4C/ 0F 2C FF cvttss2si r15, xmm7 \n"
" 0000AF61 F2/ 4C/ 0F 2C FF cvttsd2si r15, xmm7 \n"
" \n"
" 0000AF66 F3/ 49/ 0F 2A FF cvtsi2ss xmm7, r15 \n"
" 0000AF6B F2/ 49/ 0F 2A FF cvtsi2sd xmm7, r15 \n"
" \n"
" \n"
" ; Between: xmm8 and rax \n"
" 0000AF70 F3/ 44/ 0F 11 40 movss dword ptr [rax - 4], xmm8 \n"
" FC \n"
" 0000AF76 F2/ 44/ 0F 11 40 movsd qword ptr [rax + 4], xmm8 \n"
" 04 \n"
" \n"
" 0000AF7C F3/ 44/ 0F 10 40 movss xmm8, dword ptr [rax - 4] \n"
" FC \n"
" 0000AF82 F2/ 44/ 0F 10 40 movsd xmm8, qword ptr [rax + 4] \n"
" 04 \n"
" 0000AF88 F3/ 4C/ 0F 2A 40 cvtsi2ss xmm8, qword ptr [rax - 4] \n"
" FC \n"
" 0000AF8E F2/ 44/ 0F 2A 40 cvtsi2sd xmm8, dword ptr [rax + 4] \n"
" 04 \n"
" \n"
" 0000AF94 F3/ 41/ 0F 2C C0 cvttss2si eax, xmm8 \n"
" 0000AF99 F2/ 41/ 0F 2C C0 cvttsd2si eax, xmm8 \n"
" \n"
" 0000AF9E F3/ 44/ 0F 2A C0 cvtsi2ss xmm8, eax \n"
" 0000AFA3 F2/ 44/ 0F 2A C0 cvtsi2sd xmm8, eax \n"
" \n"
" 0000AFA8 F3/ 49/ 0F 2C C0 cvttss2si rax, xmm8 \n"
" 0000AFAD F2/ 49/ 0F 2C C0 cvttsd2si rax, xmm8 \n"
" \n"
" 0000AFB2 F3/ 4C/ 0F 2A C0 cvtsi2ss xmm8, rax \n"
" 0000AFB7 F2/ 4C/ 0F 2A C0 cvtsi2sd xmm8, rax \n"
" \n"
" \n"
" ; Between: xmm8 and rcx \n"
" 0000AFBC F3/ 44/ 0F 11 41 movss dword ptr [rcx - 4], xmm8 \n"
" FC \n"
" 0000AFC2 F2/ 44/ 0F 11 41 movsd qword ptr [rcx + 4], xmm8 \n"
" 04 \n"
" \n"
" 0000AFC8 F3/ 44/ 0F 10 41 movss xmm8, dword ptr [rcx - 4] \n"
" FC \n"
" 0000AFCE F2/ 44/ 0F 10 41 movsd xmm8, qword ptr [rcx + 4] \n"
" 04 \n"
" 0000AFD4 F3/ 4C/ 0F 2A 41 cvtsi2ss xmm8, qword ptr [rcx - 4] \n"
" FC \n"
" 0000AFDA F2/ 44/ 0F 2A 41 cvtsi2sd xmm8, dword ptr [rcx + 4] \n"
" 04 \n"
" \n"
" 0000AFE0 F3/ 41/ 0F 2C C8 cvttss2si ecx, xmm8 \n"
" 0000AFE5 F2/ 41/ 0F 2C C8 cvttsd2si ecx, xmm8 \n"
" \n"
" 0000AFEA F3/ 44/ 0F 2A C1 cvtsi2ss xmm8, ecx \n"
" 0000AFEF F2/ 44/ 0F 2A C1 cvtsi2sd xmm8, ecx \n"
" \n"
" 0000AFF4 F3/ 49/ 0F 2C C8 cvttss2si rcx, xmm8 \n"
" 0000AFF9 F2/ 49/ 0F 2C C8 cvttsd2si rcx, xmm8 \n"
" \n"
" 0000AFFE F3/ 4C/ 0F 2A C1 cvtsi2ss xmm8, rcx \n"
" 0000B003 F2/ 4C/ 0F 2A C1 cvtsi2sd xmm8, rcx \n"
" \n"
" \n"
" ; Between: xmm8 and rdx \n"
" 0000B008 F3/ 44/ 0F 11 42 movss dword ptr [rdx - 4], xmm8 \n"
" FC \n"
" 0000B00E F2/ 44/ 0F 11 42 movsd qword ptr [rdx + 4], xmm8 \n"
" 04 \n"
" \n"
" 0000B014 F3/ 44/ 0F 10 42 movss xmm8, dword ptr [rdx - 4] \n"
" FC \n"
" 0000B01A F2/ 44/ 0F 10 42 movsd xmm8, qword ptr [rdx + 4] \n"
" 04 \n"
" 0000B020 F3/ 4C/ 0F 2A 42 cvtsi2ss xmm8, qword ptr [rdx - 4] \n"
" FC \n"
" 0000B026 F2/ 44/ 0F 2A 42 cvtsi2sd xmm8, dword ptr [rdx + 4] \n"
" 04 \n"
" \n"
" 0000B02C F3/ 41/ 0F 2C D0 cvttss2si edx, xmm8 \n"
" 0000B031 F2/ 41/ 0F 2C D0 cvttsd2si edx, xmm8 \n"
" \n"
" 0000B036 F3/ 44/ 0F 2A C2 cvtsi2ss xmm8, edx \n"
" 0000B03B F2/ 44/ 0F 2A C2 cvtsi2sd xmm8, edx \n"
" \n"
" 0000B040 F3/ 49/ 0F 2C D0 cvttss2si rdx, xmm8 \n"
" 0000B045 F2/ 49/ 0F 2C D0 cvttsd2si rdx, xmm8 \n"
" \n"
" 0000B04A F3/ 4C/ 0F 2A C2 cvtsi2ss xmm8, rdx \n"
" 0000B04F F2/ 4C/ 0F 2A C2 cvtsi2sd xmm8, rdx \n"
" \n"
" \n"
" ; Between: xmm8 and rbx \n"
" 0000B054 F3/ 44/ 0F 11 43 movss dword ptr [rbx - 4], xmm8 \n"
" FC \n"
" 0000B05A F2/ 44/ 0F 11 43 movsd qword ptr [rbx + 4], xmm8 \n"
" 04 \n"
" \n"
" 0000B060 F3/ 44/ 0F 10 43 movss xmm8, dword ptr [rbx - 4] \n"
" FC \n"
" 0000B066 F2/ 44/ 0F 10 43 movsd xmm8, qword ptr [rbx + 4] \n"
" 04 \n"
" 0000B06C F3/ 4C/ 0F 2A 43 cvtsi2ss xmm8, qword ptr [rbx - 4] \n"
" FC \n"
" 0000B072 F2/ 44/ 0F 2A 43 cvtsi2sd xmm8, dword ptr [rbx + 4] \n"
" 04 \n"
" \n"
" 0000B078 F3/ 41/ 0F 2C D8 cvttss2si ebx, xmm8 \n"
" 0000B07D F2/ 41/ 0F 2C D8 cvttsd2si ebx, xmm8 \n"
" \n"
" 0000B082 F3/ 44/ 0F 2A C3 cvtsi2ss xmm8, ebx \n"
" 0000B087 F2/ 44/ 0F 2A C3 cvtsi2sd xmm8, ebx \n"
" \n"
" 0000B08C F3/ 49/ 0F 2C D8 cvttss2si rbx, xmm8 \n"
" 0000B091 F2/ 49/ 0F 2C D8 cvttsd2si rbx, xmm8 \n"
" \n"
" 0000B096 F3/ 4C/ 0F 2A C3 cvtsi2ss xmm8, rbx \n"
" 0000B09B F2/ 4C/ 0F 2A C3 cvtsi2sd xmm8, rbx \n"
" \n"
" \n"
" ; Between: xmm8 and rsp \n"
" 0000B0A0 F3/ 44/ 0F 11 44 movss dword ptr [rsp - 4], xmm8 \n"
" 24 FC \n"
" 0000B0A7 F2/ 44/ 0F 11 44 movsd qword ptr [rsp + 4], xmm8 \n"
" 24 04 \n"
" \n"
" 0000B0AE F3/ 44/ 0F 10 44 movss xmm8, dword ptr [rsp - 4] \n"
" 24 FC \n"
" 0000B0B5 F2/ 44/ 0F 10 44 movsd xmm8, qword ptr [rsp + 4] \n"
" 24 04 \n"
" 0000B0BC F3/ 4C/ 0F 2A 44 cvtsi2ss xmm8, qword ptr [rsp - 4] \n"
" 24 FC \n"
" 0000B0C3 F2/ 44/ 0F 2A 44 cvtsi2sd xmm8, dword ptr [rsp + 4] \n"
" 24 04 \n"
" \n"
" 0000B0CA F3/ 41/ 0F 2C E0 cvttss2si esp, xmm8 \n"
" 0000B0CF F2/ 41/ 0F 2C E0 cvttsd2si esp, xmm8 \n"
" \n"
" 0000B0D4 F3/ 44/ 0F 2A C4 cvtsi2ss xmm8, esp \n"
" 0000B0D9 F2/ 44/ 0F 2A C4 cvtsi2sd xmm8, esp \n"
" \n"
" 0000B0DE F3/ 49/ 0F 2C E0 cvttss2si rsp, xmm8 \n"
" 0000B0E3 F2/ 49/ 0F 2C E0 cvttsd2si rsp, xmm8 \n"
" \n"
" 0000B0E8 F3/ 4C/ 0F 2A C4 cvtsi2ss xmm8, rsp \n"
" 0000B0ED F2/ 4C/ 0F 2A C4 cvtsi2sd xmm8, rsp \n"
" \n"
" \n"
" ; Between: xmm8 and rbp \n"
" 0000B0F2 F3/ 44/ 0F 11 45 movss dword ptr [rbp - 4], xmm8 \n"
" FC \n"
" 0000B0F8 F2/ 44/ 0F 11 45 movsd qword ptr [rbp + 4], xmm8 \n"
" 04 \n"
" \n"
" 0000B0FE F3/ 44/ 0F 10 45 movss xmm8, dword ptr [rbp - 4] \n"
" FC \n"
" 0000B104 F2/ 44/ 0F 10 45 movsd xmm8, qword ptr [rbp + 4] \n"
" 04 \n"
" 0000B10A F3/ 4C/ 0F 2A 45 cvtsi2ss xmm8, qword ptr [rbp - 4] \n"
" FC \n"
" 0000B110 F2/ 44/ 0F 2A 45 cvtsi2sd xmm8, dword ptr [rbp + 4] \n"
" 04 \n"
" \n"
" 0000B116 F3/ 41/ 0F 2C E8 cvttss2si ebp, xmm8 \n"
" 0000B11B F2/ 41/ 0F 2C E8 cvttsd2si ebp, xmm8 \n"
" \n"
" 0000B120 F3/ 44/ 0F 2A C5 cvtsi2ss xmm8, ebp \n"
" 0000B125 F2/ 44/ 0F 2A C5 cvtsi2sd xmm8, ebp \n"
" \n"
" 0000B12A F3/ 49/ 0F 2C E8 cvttss2si rbp, xmm8 \n"
" 0000B12F F2/ 49/ 0F 2C E8 cvttsd2si rbp, xmm8 \n"
" \n"
" 0000B134 F3/ 4C/ 0F 2A C5 cvtsi2ss xmm8, rbp \n"
" 0000B139 F2/ 4C/ 0F 2A C5 cvtsi2sd xmm8, rbp \n"
" \n"
" \n"
" ; Between: xmm8 and rsi \n"
" 0000B13E F3/ 44/ 0F 11 46 movss dword ptr [rsi - 4], xmm8 \n"
" FC \n"
" 0000B144 F2/ 44/ 0F 11 46 movsd qword ptr [rsi + 4], xmm8 \n"
" 04 \n"
" \n"
" 0000B14A F3/ 44/ 0F 10 46 movss xmm8, dword ptr [rsi - 4] \n"
" FC \n"
" 0000B150 F2/ 44/ 0F 10 46 movsd xmm8, qword ptr [rsi + 4] \n"
" 04 \n"
" 0000B156 F3/ 4C/ 0F 2A 46 cvtsi2ss xmm8, qword ptr [rsi - 4] \n"
" FC \n"
" 0000B15C F2/ 44/ 0F 2A 46 cvtsi2sd xmm8, dword ptr [rsi + 4] \n"
" 04 \n"
" \n"
" 0000B162 F3/ 41/ 0F 2C F0 cvttss2si esi, xmm8 \n"
" 0000B167 F2/ 41/ 0F 2C F0 cvttsd2si esi, xmm8 \n"
" \n"
" 0000B16C F3/ 44/ 0F 2A C6 cvtsi2ss xmm8, esi \n"
" 0000B171 F2/ 44/ 0F 2A C6 cvtsi2sd xmm8, esi \n"
" \n"
" 0000B176 F3/ 49/ 0F 2C F0 cvttss2si rsi, xmm8 \n"
" 0000B17B F2/ 49/ 0F 2C F0 cvttsd2si rsi, xmm8 \n"
" \n"
" 0000B180 F3/ 4C/ 0F 2A C6 cvtsi2ss xmm8, rsi \n"
" 0000B185 F2/ 4C/ 0F 2A C6 cvtsi2sd xmm8, rsi \n";
ml64Output +=
" \n"
" \n"
" ; Between: xmm8 and rdi \n"
" 0000B18A F3/ 44/ 0F 11 47 movss dword ptr [rdi - 4], xmm8 \n"
" FC \n"
" 0000B190 F2/ 44/ 0F 11 47 movsd qword ptr [rdi + 4], xmm8 \n"
" 04 \n"
" \n"
" 0000B196 F3/ 44/ 0F 10 47 movss xmm8, dword ptr [rdi - 4] \n"
" FC \n"
" 0000B19C F2/ 44/ 0F 10 47 movsd xmm8, qword ptr [rdi + 4] \n"
" 04 \n"
" 0000B1A2 F3/ 4C/ 0F 2A 47 cvtsi2ss xmm8, qword ptr [rdi - 4] \n"
" FC \n"
" 0000B1A8 F2/ 44/ 0F 2A 47 cvtsi2sd xmm8, dword ptr [rdi + 4] \n"
" 04 \n"
" \n"
" 0000B1AE F3/ 41/ 0F 2C F8 cvttss2si edi, xmm8 \n"
" 0000B1B3 F2/ 41/ 0F 2C F8 cvttsd2si edi, xmm8 \n"
" \n"
" 0000B1B8 F3/ 44/ 0F 2A C7 cvtsi2ss xmm8, edi \n"
" 0000B1BD F2/ 44/ 0F 2A C7 cvtsi2sd xmm8, edi \n"
" \n"
" 0000B1C2 F3/ 49/ 0F 2C F8 cvttss2si rdi, xmm8 \n"
" 0000B1C7 F2/ 49/ 0F 2C F8 cvttsd2si rdi, xmm8 \n"
" \n"
" 0000B1CC F3/ 4C/ 0F 2A C7 cvtsi2ss xmm8, rdi \n"
" 0000B1D1 F2/ 4C/ 0F 2A C7 cvtsi2sd xmm8, rdi \n"
" \n"
" \n"
" ; Between: xmm8 and r8 \n"
" 0000B1D6 F3/ 45/ 0F 11 40 movss dword ptr [r8 - 4], xmm8 \n"
" FC \n"
" 0000B1DC F2/ 45/ 0F 11 40 movsd qword ptr [r8 + 4], xmm8 \n"
" 04 \n"
" \n"
" 0000B1E2 F3/ 45/ 0F 10 40 movss xmm8, dword ptr [r8 - 4] \n"
" FC \n"
" 0000B1E8 F2/ 45/ 0F 10 40 movsd xmm8, qword ptr [r8 + 4] \n"
" 04 \n"
" 0000B1EE F3/ 4D/ 0F 2A 40 cvtsi2ss xmm8, qword ptr [r8 - 4] \n"
" FC \n"
" 0000B1F4 F2/ 45/ 0F 2A 40 cvtsi2sd xmm8, dword ptr [r8 + 4] \n"
" 04 \n"
" \n"
" 0000B1FA F3/ 45/ 0F 2C C0 cvttss2si r8d, xmm8 \n"
" 0000B1FF F2/ 45/ 0F 2C C0 cvttsd2si r8d, xmm8 \n"
" \n"
" 0000B204 F3/ 45/ 0F 2A C0 cvtsi2ss xmm8, r8d \n"
" 0000B209 F2/ 45/ 0F 2A C0 cvtsi2sd xmm8, r8d \n"
" \n"
" 0000B20E F3/ 4D/ 0F 2C C0 cvttss2si r8, xmm8 \n"
" 0000B213 F2/ 4D/ 0F 2C C0 cvttsd2si r8, xmm8 \n"
" \n"
" 0000B218 F3/ 4D/ 0F 2A C0 cvtsi2ss xmm8, r8 \n"
" 0000B21D F2/ 4D/ 0F 2A C0 cvtsi2sd xmm8, r8 \n"
" \n"
" \n"
" ; Between: xmm8 and r9 \n"
" 0000B222 F3/ 45/ 0F 11 41 movss dword ptr [r9 - 4], xmm8 \n"
" FC \n"
" 0000B228 F2/ 45/ 0F 11 41 movsd qword ptr [r9 + 4], xmm8 \n"
" 04 \n"
" \n"
" 0000B22E F3/ 45/ 0F 10 41 movss xmm8, dword ptr [r9 - 4] \n"
" FC \n"
" 0000B234 F2/ 45/ 0F 10 41 movsd xmm8, qword ptr [r9 + 4] \n"
" 04 \n"
" 0000B23A F3/ 4D/ 0F 2A 41 cvtsi2ss xmm8, qword ptr [r9 - 4] \n"
" FC \n"
" 0000B240 F2/ 45/ 0F 2A 41 cvtsi2sd xmm8, dword ptr [r9 + 4] \n"
" 04 \n"
" \n"
" 0000B246 F3/ 45/ 0F 2C C8 cvttss2si r9d, xmm8 \n"
" 0000B24B F2/ 45/ 0F 2C C8 cvttsd2si r9d, xmm8 \n"
" \n"
" 0000B250 F3/ 45/ 0F 2A C1 cvtsi2ss xmm8, r9d \n"
" 0000B255 F2/ 45/ 0F 2A C1 cvtsi2sd xmm8, r9d \n"
" \n"
" 0000B25A F3/ 4D/ 0F 2C C8 cvttss2si r9, xmm8 \n"
" 0000B25F F2/ 4D/ 0F 2C C8 cvttsd2si r9, xmm8 \n"
" \n"
" 0000B264 F3/ 4D/ 0F 2A C1 cvtsi2ss xmm8, r9 \n"
" 0000B269 F2/ 4D/ 0F 2A C1 cvtsi2sd xmm8, r9 \n"
" \n"
" \n"
" ; Between: xmm8 and r10 \n"
" 0000B26E F3/ 45/ 0F 11 42 movss dword ptr [r10 - 4], xmm8 \n"
" FC \n"
" 0000B274 F2/ 45/ 0F 11 42 movsd qword ptr [r10 + 4], xmm8 \n"
" 04 \n"
" \n"
" 0000B27A F3/ 45/ 0F 10 42 movss xmm8, dword ptr [r10 - 4] \n"
" FC \n"
" 0000B280 F2/ 45/ 0F 10 42 movsd xmm8, qword ptr [r10 + 4] \n"
" 04 \n"
" 0000B286 F3/ 4D/ 0F 2A 42 cvtsi2ss xmm8, qword ptr [r10 - 4] \n"
" FC \n"
" 0000B28C F2/ 45/ 0F 2A 42 cvtsi2sd xmm8, dword ptr [r10 + 4] \n"
" 04 \n"
" \n"
" 0000B292 F3/ 45/ 0F 2C D0 cvttss2si r10d, xmm8 \n"
" 0000B297 F2/ 45/ 0F 2C D0 cvttsd2si r10d, xmm8 \n"
" \n"
" 0000B29C F3/ 45/ 0F 2A C2 cvtsi2ss xmm8, r10d \n"
" 0000B2A1 F2/ 45/ 0F 2A C2 cvtsi2sd xmm8, r10d \n"
" \n"
" 0000B2A6 F3/ 4D/ 0F 2C D0 cvttss2si r10, xmm8 \n"
" 0000B2AB F2/ 4D/ 0F 2C D0 cvttsd2si r10, xmm8 \n"
" \n"
" 0000B2B0 F3/ 4D/ 0F 2A C2 cvtsi2ss xmm8, r10 \n"
" 0000B2B5 F2/ 4D/ 0F 2A C2 cvtsi2sd xmm8, r10 \n"
" \n"
" \n"
" ; Between: xmm8 and r11 \n"
" 0000B2BA F3/ 45/ 0F 11 43 movss dword ptr [r11 - 4], xmm8 \n"
" FC \n"
" 0000B2C0 F2/ 45/ 0F 11 43 movsd qword ptr [r11 + 4], xmm8 \n"
" 04 \n"
" \n"
" 0000B2C6 F3/ 45/ 0F 10 43 movss xmm8, dword ptr [r11 - 4] \n"
" FC \n"
" 0000B2CC F2/ 45/ 0F 10 43 movsd xmm8, qword ptr [r11 + 4] \n"
" 04 \n"
" 0000B2D2 F3/ 4D/ 0F 2A 43 cvtsi2ss xmm8, qword ptr [r11 - 4] \n"
" FC \n"
" 0000B2D8 F2/ 45/ 0F 2A 43 cvtsi2sd xmm8, dword ptr [r11 + 4] \n"
" 04 \n"
" \n"
" 0000B2DE F3/ 45/ 0F 2C D8 cvttss2si r11d, xmm8 \n"
" 0000B2E3 F2/ 45/ 0F 2C D8 cvttsd2si r11d, xmm8 \n"
" \n"
" 0000B2E8 F3/ 45/ 0F 2A C3 cvtsi2ss xmm8, r11d \n"
" 0000B2ED F2/ 45/ 0F 2A C3 cvtsi2sd xmm8, r11d \n"
" \n"
" 0000B2F2 F3/ 4D/ 0F 2C D8 cvttss2si r11, xmm8 \n"
" 0000B2F7 F2/ 4D/ 0F 2C D8 cvttsd2si r11, xmm8 \n"
" \n"
" 0000B2FC F3/ 4D/ 0F 2A C3 cvtsi2ss xmm8, r11 \n"
" 0000B301 F2/ 4D/ 0F 2A C3 cvtsi2sd xmm8, r11 \n"
" \n"
" \n"
" ; Between: xmm8 and r12 \n"
" 0000B306 F3/ 45/ 0F 11 44 movss dword ptr [r12 - 4], xmm8 \n"
" 24 FC \n"
" 0000B30D F2/ 45/ 0F 11 44 movsd qword ptr [r12 + 4], xmm8 \n"
" 24 04 \n"
" \n"
" 0000B314 F3/ 45/ 0F 10 44 movss xmm8, dword ptr [r12 - 4] \n"
" 24 FC \n"
" 0000B31B F2/ 45/ 0F 10 44 movsd xmm8, qword ptr [r12 + 4] \n"
" 24 04 \n"
" 0000B322 F3/ 4D/ 0F 2A 44 cvtsi2ss xmm8, qword ptr [r12 - 4] \n"
" 24 FC \n"
" 0000B329 F2/ 45/ 0F 2A 44 cvtsi2sd xmm8, dword ptr [r12 + 4] \n"
" 24 04 \n"
" \n"
" 0000B330 F3/ 45/ 0F 2C E0 cvttss2si r12d, xmm8 \n"
" 0000B335 F2/ 45/ 0F 2C E0 cvttsd2si r12d, xmm8 \n"
" \n"
" 0000B33A F3/ 45/ 0F 2A C4 cvtsi2ss xmm8, r12d \n"
" 0000B33F F2/ 45/ 0F 2A C4 cvtsi2sd xmm8, r12d \n"
" \n"
" 0000B344 F3/ 4D/ 0F 2C E0 cvttss2si r12, xmm8 \n"
" 0000B349 F2/ 4D/ 0F 2C E0 cvttsd2si r12, xmm8 \n"
" \n"
" 0000B34E F3/ 4D/ 0F 2A C4 cvtsi2ss xmm8, r12 \n"
" 0000B353 F2/ 4D/ 0F 2A C4 cvtsi2sd xmm8, r12 \n"
" \n"
" \n"
" ; Between: xmm8 and r13 \n"
" 0000B358 F3/ 45/ 0F 11 45 movss dword ptr [r13 - 4], xmm8 \n"
" FC \n"
" 0000B35E F2/ 45/ 0F 11 45 movsd qword ptr [r13 + 4], xmm8 \n"
" 04 \n"
" \n"
" 0000B364 F3/ 45/ 0F 10 45 movss xmm8, dword ptr [r13 - 4] \n"
" FC \n"
" 0000B36A F2/ 45/ 0F 10 45 movsd xmm8, qword ptr [r13 + 4] \n"
" 04 \n"
" 0000B370 F3/ 4D/ 0F 2A 45 cvtsi2ss xmm8, qword ptr [r13 - 4] \n"
" FC \n"
" 0000B376 F2/ 45/ 0F 2A 45 cvtsi2sd xmm8, dword ptr [r13 + 4] \n"
" 04 \n"
" \n"
" 0000B37C F3/ 45/ 0F 2C E8 cvttss2si r13d, xmm8 \n"
" 0000B381 F2/ 45/ 0F 2C E8 cvttsd2si r13d, xmm8 \n"
" \n"
" 0000B386 F3/ 45/ 0F 2A C5 cvtsi2ss xmm8, r13d \n"
" 0000B38B F2/ 45/ 0F 2A C5 cvtsi2sd xmm8, r13d \n"
" \n"
" 0000B390 F3/ 4D/ 0F 2C E8 cvttss2si r13, xmm8 \n"
" 0000B395 F2/ 4D/ 0F 2C E8 cvttsd2si r13, xmm8 \n"
" \n"
" 0000B39A F3/ 4D/ 0F 2A C5 cvtsi2ss xmm8, r13 \n"
" 0000B39F F2/ 4D/ 0F 2A C5 cvtsi2sd xmm8, r13 \n"
" \n"
" \n"
" ; Between: xmm8 and r14 \n"
" 0000B3A4 F3/ 45/ 0F 11 46 movss dword ptr [r14 - 4], xmm8 \n"
" FC \n"
" 0000B3AA F2/ 45/ 0F 11 46 movsd qword ptr [r14 + 4], xmm8 \n"
" 04 \n"
" \n"
" 0000B3B0 F3/ 45/ 0F 10 46 movss xmm8, dword ptr [r14 - 4] \n"
" FC \n"
" 0000B3B6 F2/ 45/ 0F 10 46 movsd xmm8, qword ptr [r14 + 4] \n"
" 04 \n"
" 0000B3BC F3/ 4D/ 0F 2A 46 cvtsi2ss xmm8, qword ptr [r14 - 4] \n"
" FC \n"
" 0000B3C2 F2/ 45/ 0F 2A 46 cvtsi2sd xmm8, dword ptr [r14 + 4] \n"
" 04 \n"
" \n"
" 0000B3C8 F3/ 45/ 0F 2C F0 cvttss2si r14d, xmm8 \n"
" 0000B3CD F2/ 45/ 0F 2C F0 cvttsd2si r14d, xmm8 \n"
" \n"
" 0000B3D2 F3/ 45/ 0F 2A C6 cvtsi2ss xmm8, r14d \n"
" 0000B3D7 F2/ 45/ 0F 2A C6 cvtsi2sd xmm8, r14d \n"
" \n"
" 0000B3DC F3/ 4D/ 0F 2C F0 cvttss2si r14, xmm8 \n"
" 0000B3E1 F2/ 4D/ 0F 2C F0 cvttsd2si r14, xmm8 \n"
" \n"
" 0000B3E6 F3/ 4D/ 0F 2A C6 cvtsi2ss xmm8, r14 \n"
" 0000B3EB F2/ 4D/ 0F 2A C6 cvtsi2sd xmm8, r14 \n"
" \n"
" \n"
" ; Between: xmm8 and r15 \n"
" 0000B3F0 F3/ 45/ 0F 11 47 movss dword ptr [r15 - 4], xmm8 \n"
" FC \n"
" 0000B3F6 F2/ 45/ 0F 11 47 movsd qword ptr [r15 + 4], xmm8 \n"
" 04 \n"
" \n"
" 0000B3FC F3/ 45/ 0F 10 47 movss xmm8, dword ptr [r15 - 4] \n"
" FC \n"
" 0000B402 F2/ 45/ 0F 10 47 movsd xmm8, qword ptr [r15 + 4] \n"
" 04 \n"
" 0000B408 F3/ 4D/ 0F 2A 47 cvtsi2ss xmm8, qword ptr [r15 - 4] \n"
" FC \n"
" 0000B40E F2/ 45/ 0F 2A 47 cvtsi2sd xmm8, dword ptr [r15 + 4] \n"
" 04 \n"
" \n"
" 0000B414 F3/ 45/ 0F 2C F8 cvttss2si r15d, xmm8 \n"
" 0000B419 F2/ 45/ 0F 2C F8 cvttsd2si r15d, xmm8 \n"
" \n"
" 0000B41E F3/ 45/ 0F 2A C7 cvtsi2ss xmm8, r15d \n"
" 0000B423 F2/ 45/ 0F 2A C7 cvtsi2sd xmm8, r15d \n"
" \n"
" 0000B428 F3/ 4D/ 0F 2C F8 cvttss2si r15, xmm8 \n"
" 0000B42D F2/ 4D/ 0F 2C F8 cvttsd2si r15, xmm8 \n"
" \n"
" 0000B432 F3/ 4D/ 0F 2A C7 cvtsi2ss xmm8, r15 \n"
" 0000B437 F2/ 4D/ 0F 2A C7 cvtsi2sd xmm8, r15 \n"
" \n"
" \n"
" ; Between: xmm9 and rax \n"
" 0000B43C F3/ 44/ 0F 11 48 movss dword ptr [rax - 4], xmm9 \n"
" FC \n"
" 0000B442 F2/ 44/ 0F 11 48 movsd qword ptr [rax + 4], xmm9 \n"
" 04 \n"
" \n"
" 0000B448 F3/ 44/ 0F 10 48 movss xmm9, dword ptr [rax - 4] \n"
" FC \n"
" 0000B44E F2/ 44/ 0F 10 48 movsd xmm9, qword ptr [rax + 4] \n"
" 04 \n"
" 0000B454 F3/ 4C/ 0F 2A 48 cvtsi2ss xmm9, qword ptr [rax - 4] \n"
" FC \n"
" 0000B45A F2/ 44/ 0F 2A 48 cvtsi2sd xmm9, dword ptr [rax + 4] \n"
" 04 \n"
" \n"
" 0000B460 F3/ 41/ 0F 2C C1 cvttss2si eax, xmm9 \n"
" 0000B465 F2/ 41/ 0F 2C C1 cvttsd2si eax, xmm9 \n"
" \n"
" 0000B46A F3/ 44/ 0F 2A C8 cvtsi2ss xmm9, eax \n"
" 0000B46F F2/ 44/ 0F 2A C8 cvtsi2sd xmm9, eax \n"
" \n"
" 0000B474 F3/ 49/ 0F 2C C1 cvttss2si rax, xmm9 \n"
" 0000B479 F2/ 49/ 0F 2C C1 cvttsd2si rax, xmm9 \n"
" \n"
" 0000B47E F3/ 4C/ 0F 2A C8 cvtsi2ss xmm9, rax \n"
" 0000B483 F2/ 4C/ 0F 2A C8 cvtsi2sd xmm9, rax \n"
" \n"
" \n"
" ; Between: xmm9 and rcx \n"
" 0000B488 F3/ 44/ 0F 11 49 movss dword ptr [rcx - 4], xmm9 \n"
" FC \n"
" 0000B48E F2/ 44/ 0F 11 49 movsd qword ptr [rcx + 4], xmm9 \n"
" 04 \n"
" \n"
" 0000B494 F3/ 44/ 0F 10 49 movss xmm9, dword ptr [rcx - 4] \n"
" FC \n"
" 0000B49A F2/ 44/ 0F 10 49 movsd xmm9, qword ptr [rcx + 4] \n"
" 04 \n"
" 0000B4A0 F3/ 4C/ 0F 2A 49 cvtsi2ss xmm9, qword ptr [rcx - 4] \n"
" FC \n"
" 0000B4A6 F2/ 44/ 0F 2A 49 cvtsi2sd xmm9, dword ptr [rcx + 4] \n"
" 04 \n"
" \n"
" 0000B4AC F3/ 41/ 0F 2C C9 cvttss2si ecx, xmm9 \n"
" 0000B4B1 F2/ 41/ 0F 2C C9 cvttsd2si ecx, xmm9 \n"
" \n"
" 0000B4B6 F3/ 44/ 0F 2A C9 cvtsi2ss xmm9, ecx \n"
" 0000B4BB F2/ 44/ 0F 2A C9 cvtsi2sd xmm9, ecx \n"
" \n"
" 0000B4C0 F3/ 49/ 0F 2C C9 cvttss2si rcx, xmm9 \n"
" 0000B4C5 F2/ 49/ 0F 2C C9 cvttsd2si rcx, xmm9 \n"
" \n"
" 0000B4CA F3/ 4C/ 0F 2A C9 cvtsi2ss xmm9, rcx \n"
" 0000B4CF F2/ 4C/ 0F 2A C9 cvtsi2sd xmm9, rcx \n"
" \n"
" \n"
" ; Between: xmm9 and rdx \n"
" 0000B4D4 F3/ 44/ 0F 11 4A movss dword ptr [rdx - 4], xmm9 \n"
" FC \n"
" 0000B4DA F2/ 44/ 0F 11 4A movsd qword ptr [rdx + 4], xmm9 \n"
" 04 \n"
" \n"
" 0000B4E0 F3/ 44/ 0F 10 4A movss xmm9, dword ptr [rdx - 4] \n"
" FC \n"
" 0000B4E6 F2/ 44/ 0F 10 4A movsd xmm9, qword ptr [rdx + 4] \n"
" 04 \n"
" 0000B4EC F3/ 4C/ 0F 2A 4A cvtsi2ss xmm9, qword ptr [rdx - 4] \n"
" FC \n"
" 0000B4F2 F2/ 44/ 0F 2A 4A cvtsi2sd xmm9, dword ptr [rdx + 4] \n"
" 04 \n"
" \n"
" 0000B4F8 F3/ 41/ 0F 2C D1 cvttss2si edx, xmm9 \n"
" 0000B4FD F2/ 41/ 0F 2C D1 cvttsd2si edx, xmm9 \n"
" \n"
" 0000B502 F3/ 44/ 0F 2A CA cvtsi2ss xmm9, edx \n"
" 0000B507 F2/ 44/ 0F 2A CA cvtsi2sd xmm9, edx \n"
" \n"
" 0000B50C F3/ 49/ 0F 2C D1 cvttss2si rdx, xmm9 \n"
" 0000B511 F2/ 49/ 0F 2C D1 cvttsd2si rdx, xmm9 \n"
" \n"
" 0000B516 F3/ 4C/ 0F 2A CA cvtsi2ss xmm9, rdx \n"
" 0000B51B F2/ 4C/ 0F 2A CA cvtsi2sd xmm9, rdx \n"
" \n"
" \n"
" ; Between: xmm9 and rbx \n"
" 0000B520 F3/ 44/ 0F 11 4B movss dword ptr [rbx - 4], xmm9 \n"
" FC \n"
" 0000B526 F2/ 44/ 0F 11 4B movsd qword ptr [rbx + 4], xmm9 \n"
" 04 \n"
" \n"
" 0000B52C F3/ 44/ 0F 10 4B movss xmm9, dword ptr [rbx - 4] \n"
" FC \n"
" 0000B532 F2/ 44/ 0F 10 4B movsd xmm9, qword ptr [rbx + 4] \n"
" 04 \n"
" 0000B538 F3/ 4C/ 0F 2A 4B cvtsi2ss xmm9, qword ptr [rbx - 4] \n"
" FC \n"
" 0000B53E F2/ 44/ 0F 2A 4B cvtsi2sd xmm9, dword ptr [rbx + 4] \n"
" 04 \n"
" \n"
" 0000B544 F3/ 41/ 0F 2C D9 cvttss2si ebx, xmm9 \n"
" 0000B549 F2/ 41/ 0F 2C D9 cvttsd2si ebx, xmm9 \n"
" \n"
" 0000B54E F3/ 44/ 0F 2A CB cvtsi2ss xmm9, ebx \n"
" 0000B553 F2/ 44/ 0F 2A CB cvtsi2sd xmm9, ebx \n"
" \n"
" 0000B558 F3/ 49/ 0F 2C D9 cvttss2si rbx, xmm9 \n"
" 0000B55D F2/ 49/ 0F 2C D9 cvttsd2si rbx, xmm9 \n"
" \n"
" 0000B562 F3/ 4C/ 0F 2A CB cvtsi2ss xmm9, rbx \n"
" 0000B567 F2/ 4C/ 0F 2A CB cvtsi2sd xmm9, rbx \n"
" \n"
" \n"
" ; Between: xmm9 and rsp \n"
" 0000B56C F3/ 44/ 0F 11 4C movss dword ptr [rsp - 4], xmm9 \n"
" 24 FC \n"
" 0000B573 F2/ 44/ 0F 11 4C movsd qword ptr [rsp + 4], xmm9 \n"
" 24 04 \n"
" \n"
" 0000B57A F3/ 44/ 0F 10 4C movss xmm9, dword ptr [rsp - 4] \n"
" 24 FC \n"
" 0000B581 F2/ 44/ 0F 10 4C movsd xmm9, qword ptr [rsp + 4] \n"
" 24 04 \n"
" 0000B588 F3/ 4C/ 0F 2A 4C cvtsi2ss xmm9, qword ptr [rsp - 4] \n"
" 24 FC \n"
" 0000B58F F2/ 44/ 0F 2A 4C cvtsi2sd xmm9, dword ptr [rsp + 4] \n"
" 24 04 \n"
" \n"
" 0000B596 F3/ 41/ 0F 2C E1 cvttss2si esp, xmm9 \n"
" 0000B59B F2/ 41/ 0F 2C E1 cvttsd2si esp, xmm9 \n"
" \n"
" 0000B5A0 F3/ 44/ 0F 2A CC cvtsi2ss xmm9, esp \n"
" 0000B5A5 F2/ 44/ 0F 2A CC cvtsi2sd xmm9, esp \n"
" \n"
" 0000B5AA F3/ 49/ 0F 2C E1 cvttss2si rsp, xmm9 \n"
" 0000B5AF F2/ 49/ 0F 2C E1 cvttsd2si rsp, xmm9 \n"
" \n"
" 0000B5B4 F3/ 4C/ 0F 2A CC cvtsi2ss xmm9, rsp \n"
" 0000B5B9 F2/ 4C/ 0F 2A CC cvtsi2sd xmm9, rsp \n"
" \n"
" \n"
" ; Between: xmm9 and rbp \n"
" 0000B5BE F3/ 44/ 0F 11 4D movss dword ptr [rbp - 4], xmm9 \n"
" FC \n"
" 0000B5C4 F2/ 44/ 0F 11 4D movsd qword ptr [rbp + 4], xmm9 \n"
" 04 \n"
" \n"
" 0000B5CA F3/ 44/ 0F 10 4D movss xmm9, dword ptr [rbp - 4] \n"
" FC \n"
" 0000B5D0 F2/ 44/ 0F 10 4D movsd xmm9, qword ptr [rbp + 4] \n"
" 04 \n"
" 0000B5D6 F3/ 4C/ 0F 2A 4D cvtsi2ss xmm9, qword ptr [rbp - 4] \n"
" FC \n"
" 0000B5DC F2/ 44/ 0F 2A 4D cvtsi2sd xmm9, dword ptr [rbp + 4] \n"
" 04 \n"
" \n"
" 0000B5E2 F3/ 41/ 0F 2C E9 cvttss2si ebp, xmm9 \n"
" 0000B5E7 F2/ 41/ 0F 2C E9 cvttsd2si ebp, xmm9 \n"
" \n"
" 0000B5EC F3/ 44/ 0F 2A CD cvtsi2ss xmm9, ebp \n"
" 0000B5F1 F2/ 44/ 0F 2A CD cvtsi2sd xmm9, ebp \n"
" \n"
" 0000B5F6 F3/ 49/ 0F 2C E9 cvttss2si rbp, xmm9 \n"
" 0000B5FB F2/ 49/ 0F 2C E9 cvttsd2si rbp, xmm9 \n"
" \n"
" 0000B600 F3/ 4C/ 0F 2A CD cvtsi2ss xmm9, rbp \n"
" 0000B605 F2/ 4C/ 0F 2A CD cvtsi2sd xmm9, rbp \n"
" \n"
" \n"
" ; Between: xmm9 and rsi \n"
" 0000B60A F3/ 44/ 0F 11 4E movss dword ptr [rsi - 4], xmm9 \n"
" FC \n"
" 0000B610 F2/ 44/ 0F 11 4E movsd qword ptr [rsi + 4], xmm9 \n"
" 04 \n"
" \n"
" 0000B616 F3/ 44/ 0F 10 4E movss xmm9, dword ptr [rsi - 4] \n"
" FC \n"
" 0000B61C F2/ 44/ 0F 10 4E movsd xmm9, qword ptr [rsi + 4] \n"
" 04 \n"
" 0000B622 F3/ 4C/ 0F 2A 4E cvtsi2ss xmm9, qword ptr [rsi - 4] \n"
" FC \n"
" 0000B628 F2/ 44/ 0F 2A 4E cvtsi2sd xmm9, dword ptr [rsi + 4] \n"
" 04 \n"
" \n"
" 0000B62E F3/ 41/ 0F 2C F1 cvttss2si esi, xmm9 \n"
" 0000B633 F2/ 41/ 0F 2C F1 cvttsd2si esi, xmm9 \n"
" \n"
" 0000B638 F3/ 44/ 0F 2A CE cvtsi2ss xmm9, esi \n"
" 0000B63D F2/ 44/ 0F 2A CE cvtsi2sd xmm9, esi \n"
" \n"
" 0000B642 F3/ 49/ 0F 2C F1 cvttss2si rsi, xmm9 \n"
" 0000B647 F2/ 49/ 0F 2C F1 cvttsd2si rsi, xmm9 \n"
" \n"
" 0000B64C F3/ 4C/ 0F 2A CE cvtsi2ss xmm9, rsi \n"
" 0000B651 F2/ 4C/ 0F 2A CE cvtsi2sd xmm9, rsi \n"
" \n"
" \n"
" ; Between: xmm9 and rdi \n"
" 0000B656 F3/ 44/ 0F 11 4F movss dword ptr [rdi - 4], xmm9 \n"
" FC \n"
" 0000B65C F2/ 44/ 0F 11 4F movsd qword ptr [rdi + 4], xmm9 \n"
" 04 \n"
" \n"
" 0000B662 F3/ 44/ 0F 10 4F movss xmm9, dword ptr [rdi - 4] \n"
" FC \n"
" 0000B668 F2/ 44/ 0F 10 4F movsd xmm9, qword ptr [rdi + 4] \n"
" 04 \n"
" 0000B66E F3/ 4C/ 0F 2A 4F cvtsi2ss xmm9, qword ptr [rdi - 4] \n"
" FC \n"
" 0000B674 F2/ 44/ 0F 2A 4F cvtsi2sd xmm9, dword ptr [rdi + 4] \n"
" 04 \n"
" \n"
" 0000B67A F3/ 41/ 0F 2C F9 cvttss2si edi, xmm9 \n"
" 0000B67F F2/ 41/ 0F 2C F9 cvttsd2si edi, xmm9 \n"
" \n"
" 0000B684 F3/ 44/ 0F 2A CF cvtsi2ss xmm9, edi \n"
" 0000B689 F2/ 44/ 0F 2A CF cvtsi2sd xmm9, edi \n"
" \n"
" 0000B68E F3/ 49/ 0F 2C F9 cvttss2si rdi, xmm9 \n"
" 0000B693 F2/ 49/ 0F 2C F9 cvttsd2si rdi, xmm9 \n"
" \n"
" 0000B698 F3/ 4C/ 0F 2A CF cvtsi2ss xmm9, rdi \n"
" 0000B69D F2/ 4C/ 0F 2A CF cvtsi2sd xmm9, rdi \n"
" \n"
" \n"
" ; Between: xmm9 and r8 \n"
" 0000B6A2 F3/ 45/ 0F 11 48 movss dword ptr [r8 - 4], xmm9 \n"
" FC \n"
" 0000B6A8 F2/ 45/ 0F 11 48 movsd qword ptr [r8 + 4], xmm9 \n"
" 04 \n"
" \n"
" 0000B6AE F3/ 45/ 0F 10 48 movss xmm9, dword ptr [r8 - 4] \n"
" FC \n"
" 0000B6B4 F2/ 45/ 0F 10 48 movsd xmm9, qword ptr [r8 + 4] \n"
" 04 \n"
" 0000B6BA F3/ 4D/ 0F 2A 48 cvtsi2ss xmm9, qword ptr [r8 - 4] \n"
" FC \n"
" 0000B6C0 F2/ 45/ 0F 2A 48 cvtsi2sd xmm9, dword ptr [r8 + 4] \n"
" 04 \n"
" \n"
" 0000B6C6 F3/ 45/ 0F 2C C1 cvttss2si r8d, xmm9 \n"
" 0000B6CB F2/ 45/ 0F 2C C1 cvttsd2si r8d, xmm9 \n"
" \n"
" 0000B6D0 F3/ 45/ 0F 2A C8 cvtsi2ss xmm9, r8d \n"
" 0000B6D5 F2/ 45/ 0F 2A C8 cvtsi2sd xmm9, r8d \n"
" \n"
" 0000B6DA F3/ 4D/ 0F 2C C1 cvttss2si r8, xmm9 \n"
" 0000B6DF F2/ 4D/ 0F 2C C1 cvttsd2si r8, xmm9 \n"
" \n"
" 0000B6E4 F3/ 4D/ 0F 2A C8 cvtsi2ss xmm9, r8 \n"
" 0000B6E9 F2/ 4D/ 0F 2A C8 cvtsi2sd xmm9, r8 \n"
" \n"
" \n"
" ; Between: xmm9 and r9 \n"
" 0000B6EE F3/ 45/ 0F 11 49 movss dword ptr [r9 - 4], xmm9 \n"
" FC \n"
" 0000B6F4 F2/ 45/ 0F 11 49 movsd qword ptr [r9 + 4], xmm9 \n"
" 04 \n"
" \n"
" 0000B6FA F3/ 45/ 0F 10 49 movss xmm9, dword ptr [r9 - 4] \n"
" FC \n"
" 0000B700 F2/ 45/ 0F 10 49 movsd xmm9, qword ptr [r9 + 4] \n"
" 04 \n"
" 0000B706 F3/ 4D/ 0F 2A 49 cvtsi2ss xmm9, qword ptr [r9 - 4] \n"
" FC \n"
" 0000B70C F2/ 45/ 0F 2A 49 cvtsi2sd xmm9, dword ptr [r9 + 4] \n"
" 04 \n"
" \n"
" 0000B712 F3/ 45/ 0F 2C C9 cvttss2si r9d, xmm9 \n"
" 0000B717 F2/ 45/ 0F 2C C9 cvttsd2si r9d, xmm9 \n"
" \n"
" 0000B71C F3/ 45/ 0F 2A C9 cvtsi2ss xmm9, r9d \n"
" 0000B721 F2/ 45/ 0F 2A C9 cvtsi2sd xmm9, r9d \n"
" \n"
" 0000B726 F3/ 4D/ 0F 2C C9 cvttss2si r9, xmm9 \n"
" 0000B72B F2/ 4D/ 0F 2C C9 cvttsd2si r9, xmm9 \n"
" \n"
" 0000B730 F3/ 4D/ 0F 2A C9 cvtsi2ss xmm9, r9 \n"
" 0000B735 F2/ 4D/ 0F 2A C9 cvtsi2sd xmm9, r9 \n"
" \n"
" \n"
" ; Between: xmm9 and r10 \n"
" 0000B73A F3/ 45/ 0F 11 4A movss dword ptr [r10 - 4], xmm9 \n"
" FC \n"
" 0000B740 F2/ 45/ 0F 11 4A movsd qword ptr [r10 + 4], xmm9 \n"
" 04 \n"
" \n"
" 0000B746 F3/ 45/ 0F 10 4A movss xmm9, dword ptr [r10 - 4] \n"
" FC \n"
" 0000B74C F2/ 45/ 0F 10 4A movsd xmm9, qword ptr [r10 + 4] \n"
" 04 \n"
" 0000B752 F3/ 4D/ 0F 2A 4A cvtsi2ss xmm9, qword ptr [r10 - 4] \n"
" FC \n"
" 0000B758 F2/ 45/ 0F 2A 4A cvtsi2sd xmm9, dword ptr [r10 + 4] \n"
" 04 \n"
" \n"
" 0000B75E F3/ 45/ 0F 2C D1 cvttss2si r10d, xmm9 \n";
ml64Output +=
" 0000B763 F2/ 45/ 0F 2C D1 cvttsd2si r10d, xmm9 \n"
" \n"
" 0000B768 F3/ 45/ 0F 2A CA cvtsi2ss xmm9, r10d \n"
" 0000B76D F2/ 45/ 0F 2A CA cvtsi2sd xmm9, r10d \n"
" \n"
" 0000B772 F3/ 4D/ 0F 2C D1 cvttss2si r10, xmm9 \n"
" 0000B777 F2/ 4D/ 0F 2C D1 cvttsd2si r10, xmm9 \n"
" \n"
" 0000B77C F3/ 4D/ 0F 2A CA cvtsi2ss xmm9, r10 \n"
" 0000B781 F2/ 4D/ 0F 2A CA cvtsi2sd xmm9, r10 \n"
" \n"
" \n"
" ; Between: xmm9 and r11 \n"
" 0000B786 F3/ 45/ 0F 11 4B movss dword ptr [r11 - 4], xmm9 \n"
" FC \n"
" 0000B78C F2/ 45/ 0F 11 4B movsd qword ptr [r11 + 4], xmm9 \n"
" 04 \n"
" \n"
" 0000B792 F3/ 45/ 0F 10 4B movss xmm9, dword ptr [r11 - 4] \n"
" FC \n"
" 0000B798 F2/ 45/ 0F 10 4B movsd xmm9, qword ptr [r11 + 4] \n"
" 04 \n"
" 0000B79E F3/ 4D/ 0F 2A 4B cvtsi2ss xmm9, qword ptr [r11 - 4] \n"
" FC \n"
" 0000B7A4 F2/ 45/ 0F 2A 4B cvtsi2sd xmm9, dword ptr [r11 + 4] \n"
" 04 \n"
" \n"
" 0000B7AA F3/ 45/ 0F 2C D9 cvttss2si r11d, xmm9 \n"
" 0000B7AF F2/ 45/ 0F 2C D9 cvttsd2si r11d, xmm9 \n"
" \n"
" 0000B7B4 F3/ 45/ 0F 2A CB cvtsi2ss xmm9, r11d \n"
" 0000B7B9 F2/ 45/ 0F 2A CB cvtsi2sd xmm9, r11d \n"
" \n"
" 0000B7BE F3/ 4D/ 0F 2C D9 cvttss2si r11, xmm9 \n"
" 0000B7C3 F2/ 4D/ 0F 2C D9 cvttsd2si r11, xmm9 \n"
" \n"
" 0000B7C8 F3/ 4D/ 0F 2A CB cvtsi2ss xmm9, r11 \n"
" 0000B7CD F2/ 4D/ 0F 2A CB cvtsi2sd xmm9, r11 \n"
" \n"
" \n"
" ; Between: xmm9 and r12 \n"
" 0000B7D2 F3/ 45/ 0F 11 4C movss dword ptr [r12 - 4], xmm9 \n"
" 24 FC \n"
" 0000B7D9 F2/ 45/ 0F 11 4C movsd qword ptr [r12 + 4], xmm9 \n"
" 24 04 \n"
" \n"
" 0000B7E0 F3/ 45/ 0F 10 4C movss xmm9, dword ptr [r12 - 4] \n"
" 24 FC \n"
" 0000B7E7 F2/ 45/ 0F 10 4C movsd xmm9, qword ptr [r12 + 4] \n"
" 24 04 \n"
" 0000B7EE F3/ 4D/ 0F 2A 4C cvtsi2ss xmm9, qword ptr [r12 - 4] \n"
" 24 FC \n"
" 0000B7F5 F2/ 45/ 0F 2A 4C cvtsi2sd xmm9, dword ptr [r12 + 4] \n"
" 24 04 \n"
" \n"
" 0000B7FC F3/ 45/ 0F 2C E1 cvttss2si r12d, xmm9 \n"
" 0000B801 F2/ 45/ 0F 2C E1 cvttsd2si r12d, xmm9 \n"
" \n"
" 0000B806 F3/ 45/ 0F 2A CC cvtsi2ss xmm9, r12d \n"
" 0000B80B F2/ 45/ 0F 2A CC cvtsi2sd xmm9, r12d \n"
" \n"
" 0000B810 F3/ 4D/ 0F 2C E1 cvttss2si r12, xmm9 \n"
" 0000B815 F2/ 4D/ 0F 2C E1 cvttsd2si r12, xmm9 \n"
" \n"
" 0000B81A F3/ 4D/ 0F 2A CC cvtsi2ss xmm9, r12 \n"
" 0000B81F F2/ 4D/ 0F 2A CC cvtsi2sd xmm9, r12 \n"
" \n"
" \n"
" ; Between: xmm9 and r13 \n"
" 0000B824 F3/ 45/ 0F 11 4D movss dword ptr [r13 - 4], xmm9 \n"
" FC \n"
" 0000B82A F2/ 45/ 0F 11 4D movsd qword ptr [r13 + 4], xmm9 \n"
" 04 \n"
" \n"
" 0000B830 F3/ 45/ 0F 10 4D movss xmm9, dword ptr [r13 - 4] \n"
" FC \n"
" 0000B836 F2/ 45/ 0F 10 4D movsd xmm9, qword ptr [r13 + 4] \n"
" 04 \n"
" 0000B83C F3/ 4D/ 0F 2A 4D cvtsi2ss xmm9, qword ptr [r13 - 4] \n"
" FC \n"
" 0000B842 F2/ 45/ 0F 2A 4D cvtsi2sd xmm9, dword ptr [r13 + 4] \n"
" 04 \n"
" \n"
" 0000B848 F3/ 45/ 0F 2C E9 cvttss2si r13d, xmm9 \n"
" 0000B84D F2/ 45/ 0F 2C E9 cvttsd2si r13d, xmm9 \n"
" \n"
" 0000B852 F3/ 45/ 0F 2A CD cvtsi2ss xmm9, r13d \n"
" 0000B857 F2/ 45/ 0F 2A CD cvtsi2sd xmm9, r13d \n"
" \n"
" 0000B85C F3/ 4D/ 0F 2C E9 cvttss2si r13, xmm9 \n"
" 0000B861 F2/ 4D/ 0F 2C E9 cvttsd2si r13, xmm9 \n"
" \n"
" 0000B866 F3/ 4D/ 0F 2A CD cvtsi2ss xmm9, r13 \n"
" 0000B86B F2/ 4D/ 0F 2A CD cvtsi2sd xmm9, r13 \n"
" \n"
" \n"
" ; Between: xmm9 and r14 \n"
" 0000B870 F3/ 45/ 0F 11 4E movss dword ptr [r14 - 4], xmm9 \n"
" FC \n"
" 0000B876 F2/ 45/ 0F 11 4E movsd qword ptr [r14 + 4], xmm9 \n"
" 04 \n"
" \n"
" 0000B87C F3/ 45/ 0F 10 4E movss xmm9, dword ptr [r14 - 4] \n"
" FC \n"
" 0000B882 F2/ 45/ 0F 10 4E movsd xmm9, qword ptr [r14 + 4] \n"
" 04 \n"
" 0000B888 F3/ 4D/ 0F 2A 4E cvtsi2ss xmm9, qword ptr [r14 - 4] \n"
" FC \n"
" 0000B88E F2/ 45/ 0F 2A 4E cvtsi2sd xmm9, dword ptr [r14 + 4] \n"
" 04 \n"
" \n"
" 0000B894 F3/ 45/ 0F 2C F1 cvttss2si r14d, xmm9 \n"
" 0000B899 F2/ 45/ 0F 2C F1 cvttsd2si r14d, xmm9 \n"
" \n"
" 0000B89E F3/ 45/ 0F 2A CE cvtsi2ss xmm9, r14d \n"
" 0000B8A3 F2/ 45/ 0F 2A CE cvtsi2sd xmm9, r14d \n"
" \n"
" 0000B8A8 F3/ 4D/ 0F 2C F1 cvttss2si r14, xmm9 \n"
" 0000B8AD F2/ 4D/ 0F 2C F1 cvttsd2si r14, xmm9 \n"
" \n"
" 0000B8B2 F3/ 4D/ 0F 2A CE cvtsi2ss xmm9, r14 \n"
" 0000B8B7 F2/ 4D/ 0F 2A CE cvtsi2sd xmm9, r14 \n"
" \n"
" \n"
" ; Between: xmm9 and r15 \n"
" 0000B8BC F3/ 45/ 0F 11 4F movss dword ptr [r15 - 4], xmm9 \n"
" FC \n"
" 0000B8C2 F2/ 45/ 0F 11 4F movsd qword ptr [r15 + 4], xmm9 \n"
" 04 \n"
" \n"
" 0000B8C8 F3/ 45/ 0F 10 4F movss xmm9, dword ptr [r15 - 4] \n"
" FC \n"
" 0000B8CE F2/ 45/ 0F 10 4F movsd xmm9, qword ptr [r15 + 4] \n"
" 04 \n"
" 0000B8D4 F3/ 4D/ 0F 2A 4F cvtsi2ss xmm9, qword ptr [r15 - 4] \n"
" FC \n"
" 0000B8DA F2/ 45/ 0F 2A 4F cvtsi2sd xmm9, dword ptr [r15 + 4] \n"
" 04 \n"
" \n"
" 0000B8E0 F3/ 45/ 0F 2C F9 cvttss2si r15d, xmm9 \n"
" 0000B8E5 F2/ 45/ 0F 2C F9 cvttsd2si r15d, xmm9 \n"
" \n"
" 0000B8EA F3/ 45/ 0F 2A CF cvtsi2ss xmm9, r15d \n"
" 0000B8EF F2/ 45/ 0F 2A CF cvtsi2sd xmm9, r15d \n"
" \n"
" 0000B8F4 F3/ 4D/ 0F 2C F9 cvttss2si r15, xmm9 \n"
" 0000B8F9 F2/ 4D/ 0F 2C F9 cvttsd2si r15, xmm9 \n"
" \n"
" 0000B8FE F3/ 4D/ 0F 2A CF cvtsi2ss xmm9, r15 \n"
" 0000B903 F2/ 4D/ 0F 2A CF cvtsi2sd xmm9, r15 \n"
" \n"
" \n"
" ; Between: xmm10 and rax \n"
" 0000B908 F3/ 44/ 0F 11 50 movss dword ptr [rax - 4], xmm10 \n"
" FC \n"
" 0000B90E F2/ 44/ 0F 11 50 movsd qword ptr [rax + 4], xmm10 \n"
" 04 \n"
" \n"
" 0000B914 F3/ 44/ 0F 10 50 movss xmm10, dword ptr [rax - 4] \n"
" FC \n"
" 0000B91A F2/ 44/ 0F 10 50 movsd xmm10, qword ptr [rax + 4] \n"
" 04 \n"
" 0000B920 F3/ 4C/ 0F 2A 50 cvtsi2ss xmm10, qword ptr [rax - 4] \n"
" FC \n"
" 0000B926 F2/ 44/ 0F 2A 50 cvtsi2sd xmm10, dword ptr [rax + 4] \n"
" 04 \n"
" \n"
" 0000B92C F3/ 41/ 0F 2C C2 cvttss2si eax, xmm10 \n"
" 0000B931 F2/ 41/ 0F 2C C2 cvttsd2si eax, xmm10 \n"
" \n"
" 0000B936 F3/ 44/ 0F 2A D0 cvtsi2ss xmm10, eax \n"
" 0000B93B F2/ 44/ 0F 2A D0 cvtsi2sd xmm10, eax \n"
" \n"
" 0000B940 F3/ 49/ 0F 2C C2 cvttss2si rax, xmm10 \n"
" 0000B945 F2/ 49/ 0F 2C C2 cvttsd2si rax, xmm10 \n"
" \n"
" 0000B94A F3/ 4C/ 0F 2A D0 cvtsi2ss xmm10, rax \n"
" 0000B94F F2/ 4C/ 0F 2A D0 cvtsi2sd xmm10, rax \n"
" \n"
" \n"
" ; Between: xmm10 and rcx \n"
" 0000B954 F3/ 44/ 0F 11 51 movss dword ptr [rcx - 4], xmm10 \n"
" FC \n"
" 0000B95A F2/ 44/ 0F 11 51 movsd qword ptr [rcx + 4], xmm10 \n"
" 04 \n"
" \n"
" 0000B960 F3/ 44/ 0F 10 51 movss xmm10, dword ptr [rcx - 4] \n"
" FC \n"
" 0000B966 F2/ 44/ 0F 10 51 movsd xmm10, qword ptr [rcx + 4] \n"
" 04 \n"
" 0000B96C F3/ 4C/ 0F 2A 51 cvtsi2ss xmm10, qword ptr [rcx - 4] \n"
" FC \n"
" 0000B972 F2/ 44/ 0F 2A 51 cvtsi2sd xmm10, dword ptr [rcx + 4] \n"
" 04 \n"
" \n"
" 0000B978 F3/ 41/ 0F 2C CA cvttss2si ecx, xmm10 \n"
" 0000B97D F2/ 41/ 0F 2C CA cvttsd2si ecx, xmm10 \n"
" \n"
" 0000B982 F3/ 44/ 0F 2A D1 cvtsi2ss xmm10, ecx \n"
" 0000B987 F2/ 44/ 0F 2A D1 cvtsi2sd xmm10, ecx \n"
" \n"
" 0000B98C F3/ 49/ 0F 2C CA cvttss2si rcx, xmm10 \n"
" 0000B991 F2/ 49/ 0F 2C CA cvttsd2si rcx, xmm10 \n"
" \n"
" 0000B996 F3/ 4C/ 0F 2A D1 cvtsi2ss xmm10, rcx \n"
" 0000B99B F2/ 4C/ 0F 2A D1 cvtsi2sd xmm10, rcx \n"
" \n"
" \n"
" ; Between: xmm10 and rdx \n"
" 0000B9A0 F3/ 44/ 0F 11 52 movss dword ptr [rdx - 4], xmm10 \n"
" FC \n"
" 0000B9A6 F2/ 44/ 0F 11 52 movsd qword ptr [rdx + 4], xmm10 \n"
" 04 \n"
" \n"
" 0000B9AC F3/ 44/ 0F 10 52 movss xmm10, dword ptr [rdx - 4] \n"
" FC \n"
" 0000B9B2 F2/ 44/ 0F 10 52 movsd xmm10, qword ptr [rdx + 4] \n"
" 04 \n"
" 0000B9B8 F3/ 4C/ 0F 2A 52 cvtsi2ss xmm10, qword ptr [rdx - 4] \n"
" FC \n"
" 0000B9BE F2/ 44/ 0F 2A 52 cvtsi2sd xmm10, dword ptr [rdx + 4] \n"
" 04 \n"
" \n"
" 0000B9C4 F3/ 41/ 0F 2C D2 cvttss2si edx, xmm10 \n"
" 0000B9C9 F2/ 41/ 0F 2C D2 cvttsd2si edx, xmm10 \n"
" \n"
" 0000B9CE F3/ 44/ 0F 2A D2 cvtsi2ss xmm10, edx \n"
" 0000B9D3 F2/ 44/ 0F 2A D2 cvtsi2sd xmm10, edx \n"
" \n"
" 0000B9D8 F3/ 49/ 0F 2C D2 cvttss2si rdx, xmm10 \n"
" 0000B9DD F2/ 49/ 0F 2C D2 cvttsd2si rdx, xmm10 \n"
" \n"
" 0000B9E2 F3/ 4C/ 0F 2A D2 cvtsi2ss xmm10, rdx \n"
" 0000B9E7 F2/ 4C/ 0F 2A D2 cvtsi2sd xmm10, rdx \n"
" \n"
" \n"
" ; Between: xmm10 and rbx \n"
" 0000B9EC F3/ 44/ 0F 11 53 movss dword ptr [rbx - 4], xmm10 \n"
" FC \n"
" 0000B9F2 F2/ 44/ 0F 11 53 movsd qword ptr [rbx + 4], xmm10 \n"
" 04 \n"
" \n"
" 0000B9F8 F3/ 44/ 0F 10 53 movss xmm10, dword ptr [rbx - 4] \n"
" FC \n"
" 0000B9FE F2/ 44/ 0F 10 53 movsd xmm10, qword ptr [rbx + 4] \n"
" 04 \n"
" 0000BA04 F3/ 4C/ 0F 2A 53 cvtsi2ss xmm10, qword ptr [rbx - 4] \n"
" FC \n"
" 0000BA0A F2/ 44/ 0F 2A 53 cvtsi2sd xmm10, dword ptr [rbx + 4] \n"
" 04 \n"
" \n"
" 0000BA10 F3/ 41/ 0F 2C DA cvttss2si ebx, xmm10 \n"
" 0000BA15 F2/ 41/ 0F 2C DA cvttsd2si ebx, xmm10 \n"
" \n"
" 0000BA1A F3/ 44/ 0F 2A D3 cvtsi2ss xmm10, ebx \n"
" 0000BA1F F2/ 44/ 0F 2A D3 cvtsi2sd xmm10, ebx \n"
" \n"
" 0000BA24 F3/ 49/ 0F 2C DA cvttss2si rbx, xmm10 \n"
" 0000BA29 F2/ 49/ 0F 2C DA cvttsd2si rbx, xmm10 \n"
" \n"
" 0000BA2E F3/ 4C/ 0F 2A D3 cvtsi2ss xmm10, rbx \n"
" 0000BA33 F2/ 4C/ 0F 2A D3 cvtsi2sd xmm10, rbx \n"
" \n"
" \n"
" ; Between: xmm10 and rsp \n"
" 0000BA38 F3/ 44/ 0F 11 54 movss dword ptr [rsp - 4], xmm10 \n"
" 24 FC \n"
" 0000BA3F F2/ 44/ 0F 11 54 movsd qword ptr [rsp + 4], xmm10 \n"
" 24 04 \n"
" \n"
" 0000BA46 F3/ 44/ 0F 10 54 movss xmm10, dword ptr [rsp - 4] \n"
" 24 FC \n"
" 0000BA4D F2/ 44/ 0F 10 54 movsd xmm10, qword ptr [rsp + 4] \n"
" 24 04 \n"
" 0000BA54 F3/ 4C/ 0F 2A 54 cvtsi2ss xmm10, qword ptr [rsp - 4] \n"
" 24 FC \n"
" 0000BA5B F2/ 44/ 0F 2A 54 cvtsi2sd xmm10, dword ptr [rsp + 4] \n"
" 24 04 \n"
" \n"
" 0000BA62 F3/ 41/ 0F 2C E2 cvttss2si esp, xmm10 \n"
" 0000BA67 F2/ 41/ 0F 2C E2 cvttsd2si esp, xmm10 \n"
" \n"
" 0000BA6C F3/ 44/ 0F 2A D4 cvtsi2ss xmm10, esp \n"
" 0000BA71 F2/ 44/ 0F 2A D4 cvtsi2sd xmm10, esp \n"
" \n"
" 0000BA76 F3/ 49/ 0F 2C E2 cvttss2si rsp, xmm10 \n"
" 0000BA7B F2/ 49/ 0F 2C E2 cvttsd2si rsp, xmm10 \n"
" \n"
" 0000BA80 F3/ 4C/ 0F 2A D4 cvtsi2ss xmm10, rsp \n"
" 0000BA85 F2/ 4C/ 0F 2A D4 cvtsi2sd xmm10, rsp \n"
" \n"
" \n"
" ; Between: xmm10 and rbp \n"
" 0000BA8A F3/ 44/ 0F 11 55 movss dword ptr [rbp - 4], xmm10 \n"
" FC \n"
" 0000BA90 F2/ 44/ 0F 11 55 movsd qword ptr [rbp + 4], xmm10 \n"
" 04 \n"
" \n"
" 0000BA96 F3/ 44/ 0F 10 55 movss xmm10, dword ptr [rbp - 4] \n"
" FC \n"
" 0000BA9C F2/ 44/ 0F 10 55 movsd xmm10, qword ptr [rbp + 4] \n"
" 04 \n"
" 0000BAA2 F3/ 4C/ 0F 2A 55 cvtsi2ss xmm10, qword ptr [rbp - 4] \n"
" FC \n"
" 0000BAA8 F2/ 44/ 0F 2A 55 cvtsi2sd xmm10, dword ptr [rbp + 4] \n"
" 04 \n"
" \n"
" 0000BAAE F3/ 41/ 0F 2C EA cvttss2si ebp, xmm10 \n"
" 0000BAB3 F2/ 41/ 0F 2C EA cvttsd2si ebp, xmm10 \n"
" \n"
" 0000BAB8 F3/ 44/ 0F 2A D5 cvtsi2ss xmm10, ebp \n"
" 0000BABD F2/ 44/ 0F 2A D5 cvtsi2sd xmm10, ebp \n"
" \n"
" 0000BAC2 F3/ 49/ 0F 2C EA cvttss2si rbp, xmm10 \n"
" 0000BAC7 F2/ 49/ 0F 2C EA cvttsd2si rbp, xmm10 \n"
" \n"
" 0000BACC F3/ 4C/ 0F 2A D5 cvtsi2ss xmm10, rbp \n"
" 0000BAD1 F2/ 4C/ 0F 2A D5 cvtsi2sd xmm10, rbp \n"
" \n"
" \n"
" ; Between: xmm10 and rsi \n"
" 0000BAD6 F3/ 44/ 0F 11 56 movss dword ptr [rsi - 4], xmm10 \n"
" FC \n"
" 0000BADC F2/ 44/ 0F 11 56 movsd qword ptr [rsi + 4], xmm10 \n"
" 04 \n"
" \n"
" 0000BAE2 F3/ 44/ 0F 10 56 movss xmm10, dword ptr [rsi - 4] \n"
" FC \n"
" 0000BAE8 F2/ 44/ 0F 10 56 movsd xmm10, qword ptr [rsi + 4] \n"
" 04 \n"
" 0000BAEE F3/ 4C/ 0F 2A 56 cvtsi2ss xmm10, qword ptr [rsi - 4] \n"
" FC \n"
" 0000BAF4 F2/ 44/ 0F 2A 56 cvtsi2sd xmm10, dword ptr [rsi + 4] \n"
" 04 \n"
" \n"
" 0000BAFA F3/ 41/ 0F 2C F2 cvttss2si esi, xmm10 \n"
" 0000BAFF F2/ 41/ 0F 2C F2 cvttsd2si esi, xmm10 \n"
" \n"
" 0000BB04 F3/ 44/ 0F 2A D6 cvtsi2ss xmm10, esi \n"
" 0000BB09 F2/ 44/ 0F 2A D6 cvtsi2sd xmm10, esi \n"
" \n"
" 0000BB0E F3/ 49/ 0F 2C F2 cvttss2si rsi, xmm10 \n"
" 0000BB13 F2/ 49/ 0F 2C F2 cvttsd2si rsi, xmm10 \n"
" \n"
" 0000BB18 F3/ 4C/ 0F 2A D6 cvtsi2ss xmm10, rsi \n"
" 0000BB1D F2/ 4C/ 0F 2A D6 cvtsi2sd xmm10, rsi \n"
" \n"
" \n"
" ; Between: xmm10 and rdi \n"
" 0000BB22 F3/ 44/ 0F 11 57 movss dword ptr [rdi - 4], xmm10 \n"
" FC \n"
" 0000BB28 F2/ 44/ 0F 11 57 movsd qword ptr [rdi + 4], xmm10 \n"
" 04 \n"
" \n"
" 0000BB2E F3/ 44/ 0F 10 57 movss xmm10, dword ptr [rdi - 4] \n"
" FC \n"
" 0000BB34 F2/ 44/ 0F 10 57 movsd xmm10, qword ptr [rdi + 4] \n"
" 04 \n"
" 0000BB3A F3/ 4C/ 0F 2A 57 cvtsi2ss xmm10, qword ptr [rdi - 4] \n"
" FC \n"
" 0000BB40 F2/ 44/ 0F 2A 57 cvtsi2sd xmm10, dword ptr [rdi + 4] \n"
" 04 \n"
" \n"
" 0000BB46 F3/ 41/ 0F 2C FA cvttss2si edi, xmm10 \n"
" 0000BB4B F2/ 41/ 0F 2C FA cvttsd2si edi, xmm10 \n"
" \n"
" 0000BB50 F3/ 44/ 0F 2A D7 cvtsi2ss xmm10, edi \n"
" 0000BB55 F2/ 44/ 0F 2A D7 cvtsi2sd xmm10, edi \n"
" \n"
" 0000BB5A F3/ 49/ 0F 2C FA cvttss2si rdi, xmm10 \n"
" 0000BB5F F2/ 49/ 0F 2C FA cvttsd2si rdi, xmm10 \n"
" \n"
" 0000BB64 F3/ 4C/ 0F 2A D7 cvtsi2ss xmm10, rdi \n"
" 0000BB69 F2/ 4C/ 0F 2A D7 cvtsi2sd xmm10, rdi \n"
" \n"
" \n"
" ; Between: xmm10 and r8 \n"
" 0000BB6E F3/ 45/ 0F 11 50 movss dword ptr [r8 - 4], xmm10 \n"
" FC \n"
" 0000BB74 F2/ 45/ 0F 11 50 movsd qword ptr [r8 + 4], xmm10 \n"
" 04 \n"
" \n"
" 0000BB7A F3/ 45/ 0F 10 50 movss xmm10, dword ptr [r8 - 4] \n"
" FC \n"
" 0000BB80 F2/ 45/ 0F 10 50 movsd xmm10, qword ptr [r8 + 4] \n"
" 04 \n"
" 0000BB86 F3/ 4D/ 0F 2A 50 cvtsi2ss xmm10, qword ptr [r8 - 4] \n"
" FC \n"
" 0000BB8C F2/ 45/ 0F 2A 50 cvtsi2sd xmm10, dword ptr [r8 + 4] \n"
" 04 \n"
" \n"
" 0000BB92 F3/ 45/ 0F 2C C2 cvttss2si r8d, xmm10 \n"
" 0000BB97 F2/ 45/ 0F 2C C2 cvttsd2si r8d, xmm10 \n"
" \n"
" 0000BB9C F3/ 45/ 0F 2A D0 cvtsi2ss xmm10, r8d \n"
" 0000BBA1 F2/ 45/ 0F 2A D0 cvtsi2sd xmm10, r8d \n"
" \n"
" 0000BBA6 F3/ 4D/ 0F 2C C2 cvttss2si r8, xmm10 \n"
" 0000BBAB F2/ 4D/ 0F 2C C2 cvttsd2si r8, xmm10 \n"
" \n"
" 0000BBB0 F3/ 4D/ 0F 2A D0 cvtsi2ss xmm10, r8 \n"
" 0000BBB5 F2/ 4D/ 0F 2A D0 cvtsi2sd xmm10, r8 \n"
" \n"
" \n"
" ; Between: xmm10 and r9 \n"
" 0000BBBA F3/ 45/ 0F 11 51 movss dword ptr [r9 - 4], xmm10 \n"
" FC \n"
" 0000BBC0 F2/ 45/ 0F 11 51 movsd qword ptr [r9 + 4], xmm10 \n"
" 04 \n"
" \n"
" 0000BBC6 F3/ 45/ 0F 10 51 movss xmm10, dword ptr [r9 - 4] \n"
" FC \n"
" 0000BBCC F2/ 45/ 0F 10 51 movsd xmm10, qword ptr [r9 + 4] \n"
" 04 \n"
" 0000BBD2 F3/ 4D/ 0F 2A 51 cvtsi2ss xmm10, qword ptr [r9 - 4] \n"
" FC \n"
" 0000BBD8 F2/ 45/ 0F 2A 51 cvtsi2sd xmm10, dword ptr [r9 + 4] \n"
" 04 \n"
" \n"
" 0000BBDE F3/ 45/ 0F 2C CA cvttss2si r9d, xmm10 \n"
" 0000BBE3 F2/ 45/ 0F 2C CA cvttsd2si r9d, xmm10 \n"
" \n"
" 0000BBE8 F3/ 45/ 0F 2A D1 cvtsi2ss xmm10, r9d \n"
" 0000BBED F2/ 45/ 0F 2A D1 cvtsi2sd xmm10, r9d \n"
" \n"
" 0000BBF2 F3/ 4D/ 0F 2C CA cvttss2si r9, xmm10 \n"
" 0000BBF7 F2/ 4D/ 0F 2C CA cvttsd2si r9, xmm10 \n"
" \n"
" 0000BBFC F3/ 4D/ 0F 2A D1 cvtsi2ss xmm10, r9 \n"
" 0000BC01 F2/ 4D/ 0F 2A D1 cvtsi2sd xmm10, r9 \n"
" \n"
" \n"
" ; Between: xmm10 and r10 \n"
" 0000BC06 F3/ 45/ 0F 11 52 movss dword ptr [r10 - 4], xmm10 \n"
" FC \n"
" 0000BC0C F2/ 45/ 0F 11 52 movsd qword ptr [r10 + 4], xmm10 \n"
" 04 \n"
" \n"
" 0000BC12 F3/ 45/ 0F 10 52 movss xmm10, dword ptr [r10 - 4] \n"
" FC \n"
" 0000BC18 F2/ 45/ 0F 10 52 movsd xmm10, qword ptr [r10 + 4] \n"
" 04 \n"
" 0000BC1E F3/ 4D/ 0F 2A 52 cvtsi2ss xmm10, qword ptr [r10 - 4] \n"
" FC \n"
" 0000BC24 F2/ 45/ 0F 2A 52 cvtsi2sd xmm10, dword ptr [r10 + 4] \n"
" 04 \n"
" \n"
" 0000BC2A F3/ 45/ 0F 2C D2 cvttss2si r10d, xmm10 \n"
" 0000BC2F F2/ 45/ 0F 2C D2 cvttsd2si r10d, xmm10 \n"
" \n"
" 0000BC34 F3/ 45/ 0F 2A D2 cvtsi2ss xmm10, r10d \n"
" 0000BC39 F2/ 45/ 0F 2A D2 cvtsi2sd xmm10, r10d \n"
" \n"
" 0000BC3E F3/ 4D/ 0F 2C D2 cvttss2si r10, xmm10 \n"
" 0000BC43 F2/ 4D/ 0F 2C D2 cvttsd2si r10, xmm10 \n"
" \n"
" 0000BC48 F3/ 4D/ 0F 2A D2 cvtsi2ss xmm10, r10 \n"
" 0000BC4D F2/ 4D/ 0F 2A D2 cvtsi2sd xmm10, r10 \n"
" \n"
" \n"
" ; Between: xmm10 and r11 \n"
" 0000BC52 F3/ 45/ 0F 11 53 movss dword ptr [r11 - 4], xmm10 \n"
" FC \n"
" 0000BC58 F2/ 45/ 0F 11 53 movsd qword ptr [r11 + 4], xmm10 \n"
" 04 \n"
" \n"
" 0000BC5E F3/ 45/ 0F 10 53 movss xmm10, dword ptr [r11 - 4] \n"
" FC \n"
" 0000BC64 F2/ 45/ 0F 10 53 movsd xmm10, qword ptr [r11 + 4] \n"
" 04 \n"
" 0000BC6A F3/ 4D/ 0F 2A 53 cvtsi2ss xmm10, qword ptr [r11 - 4] \n"
" FC \n"
" 0000BC70 F2/ 45/ 0F 2A 53 cvtsi2sd xmm10, dword ptr [r11 + 4] \n"
" 04 \n"
" \n"
" 0000BC76 F3/ 45/ 0F 2C DA cvttss2si r11d, xmm10 \n"
" 0000BC7B F2/ 45/ 0F 2C DA cvttsd2si r11d, xmm10 \n"
" \n"
" 0000BC80 F3/ 45/ 0F 2A D3 cvtsi2ss xmm10, r11d \n"
" 0000BC85 F2/ 45/ 0F 2A D3 cvtsi2sd xmm10, r11d \n"
" \n"
" 0000BC8A F3/ 4D/ 0F 2C DA cvttss2si r11, xmm10 \n"
" 0000BC8F F2/ 4D/ 0F 2C DA cvttsd2si r11, xmm10 \n"
" \n"
" 0000BC94 F3/ 4D/ 0F 2A D3 cvtsi2ss xmm10, r11 \n"
" 0000BC99 F2/ 4D/ 0F 2A D3 cvtsi2sd xmm10, r11 \n"
" \n"
" \n"
" ; Between: xmm10 and r12 \n"
" 0000BC9E F3/ 45/ 0F 11 54 movss dword ptr [r12 - 4], xmm10 \n"
" 24 FC \n"
" 0000BCA5 F2/ 45/ 0F 11 54 movsd qword ptr [r12 + 4], xmm10 \n"
" 24 04 \n"
" \n"
" 0000BCAC F3/ 45/ 0F 10 54 movss xmm10, dword ptr [r12 - 4] \n"
" 24 FC \n"
" 0000BCB3 F2/ 45/ 0F 10 54 movsd xmm10, qword ptr [r12 + 4] \n"
" 24 04 \n"
" 0000BCBA F3/ 4D/ 0F 2A 54 cvtsi2ss xmm10, qword ptr [r12 - 4] \n"
" 24 FC \n"
" 0000BCC1 F2/ 45/ 0F 2A 54 cvtsi2sd xmm10, dword ptr [r12 + 4] \n"
" 24 04 \n"
" \n"
" 0000BCC8 F3/ 45/ 0F 2C E2 cvttss2si r12d, xmm10 \n"
" 0000BCCD F2/ 45/ 0F 2C E2 cvttsd2si r12d, xmm10 \n"
" \n"
" 0000BCD2 F3/ 45/ 0F 2A D4 cvtsi2ss xmm10, r12d \n"
" 0000BCD7 F2/ 45/ 0F 2A D4 cvtsi2sd xmm10, r12d \n"
" \n"
" 0000BCDC F3/ 4D/ 0F 2C E2 cvttss2si r12, xmm10 \n"
" 0000BCE1 F2/ 4D/ 0F 2C E2 cvttsd2si r12, xmm10 \n"
" \n"
" 0000BCE6 F3/ 4D/ 0F 2A D4 cvtsi2ss xmm10, r12 \n"
" 0000BCEB F2/ 4D/ 0F 2A D4 cvtsi2sd xmm10, r12 \n"
" \n"
" \n"
" ; Between: xmm10 and r13 \n"
" 0000BCF0 F3/ 45/ 0F 11 55 movss dword ptr [r13 - 4], xmm10 \n"
" FC \n"
" 0000BCF6 F2/ 45/ 0F 11 55 movsd qword ptr [r13 + 4], xmm10 \n"
" 04 \n"
" \n"
" 0000BCFC F3/ 45/ 0F 10 55 movss xmm10, dword ptr [r13 - 4] \n"
" FC \n"
" 0000BD02 F2/ 45/ 0F 10 55 movsd xmm10, qword ptr [r13 + 4] \n"
" 04 \n"
" 0000BD08 F3/ 4D/ 0F 2A 55 cvtsi2ss xmm10, qword ptr [r13 - 4] \n"
" FC \n"
" 0000BD0E F2/ 45/ 0F 2A 55 cvtsi2sd xmm10, dword ptr [r13 + 4] \n"
" 04 \n"
" \n"
" 0000BD14 F3/ 45/ 0F 2C EA cvttss2si r13d, xmm10 \n"
" 0000BD19 F2/ 45/ 0F 2C EA cvttsd2si r13d, xmm10 \n"
" \n"
" 0000BD1E F3/ 45/ 0F 2A D5 cvtsi2ss xmm10, r13d \n"
" 0000BD23 F2/ 45/ 0F 2A D5 cvtsi2sd xmm10, r13d \n"
" \n"
" 0000BD28 F3/ 4D/ 0F 2C EA cvttss2si r13, xmm10 \n"
" 0000BD2D F2/ 4D/ 0F 2C EA cvttsd2si r13, xmm10 \n"
" \n"
" 0000BD32 F3/ 4D/ 0F 2A D5 cvtsi2ss xmm10, r13 \n"
" 0000BD37 F2/ 4D/ 0F 2A D5 cvtsi2sd xmm10, r13 \n"
" \n"
" \n"
" ; Between: xmm10 and r14 \n"
" 0000BD3C F3/ 45/ 0F 11 56 movss dword ptr [r14 - 4], xmm10 \n"
" FC \n"
" 0000BD42 F2/ 45/ 0F 11 56 movsd qword ptr [r14 + 4], xmm10 \n"
" 04 \n"
" \n";
ml64Output +=
" 0000BD48 F3/ 45/ 0F 10 56 movss xmm10, dword ptr [r14 - 4] \n"
" FC \n"
" 0000BD4E F2/ 45/ 0F 10 56 movsd xmm10, qword ptr [r14 + 4] \n"
" 04 \n"
" 0000BD54 F3/ 4D/ 0F 2A 56 cvtsi2ss xmm10, qword ptr [r14 - 4] \n"
" FC \n"
" 0000BD5A F2/ 45/ 0F 2A 56 cvtsi2sd xmm10, dword ptr [r14 + 4] \n"
" 04 \n"
" \n"
" 0000BD60 F3/ 45/ 0F 2C F2 cvttss2si r14d, xmm10 \n"
" 0000BD65 F2/ 45/ 0F 2C F2 cvttsd2si r14d, xmm10 \n"
" \n"
" 0000BD6A F3/ 45/ 0F 2A D6 cvtsi2ss xmm10, r14d \n"
" 0000BD6F F2/ 45/ 0F 2A D6 cvtsi2sd xmm10, r14d \n"
" \n"
" 0000BD74 F3/ 4D/ 0F 2C F2 cvttss2si r14, xmm10 \n"
" 0000BD79 F2/ 4D/ 0F 2C F2 cvttsd2si r14, xmm10 \n"
" \n"
" 0000BD7E F3/ 4D/ 0F 2A D6 cvtsi2ss xmm10, r14 \n"
" 0000BD83 F2/ 4D/ 0F 2A D6 cvtsi2sd xmm10, r14 \n"
" \n"
" \n"
" ; Between: xmm10 and r15 \n"
" 0000BD88 F3/ 45/ 0F 11 57 movss dword ptr [r15 - 4], xmm10 \n"
" FC \n"
" 0000BD8E F2/ 45/ 0F 11 57 movsd qword ptr [r15 + 4], xmm10 \n"
" 04 \n"
" \n"
" 0000BD94 F3/ 45/ 0F 10 57 movss xmm10, dword ptr [r15 - 4] \n"
" FC \n"
" 0000BD9A F2/ 45/ 0F 10 57 movsd xmm10, qword ptr [r15 + 4] \n"
" 04 \n"
" 0000BDA0 F3/ 4D/ 0F 2A 57 cvtsi2ss xmm10, qword ptr [r15 - 4] \n"
" FC \n"
" 0000BDA6 F2/ 45/ 0F 2A 57 cvtsi2sd xmm10, dword ptr [r15 + 4] \n"
" 04 \n"
" \n"
" 0000BDAC F3/ 45/ 0F 2C FA cvttss2si r15d, xmm10 \n"
" 0000BDB1 F2/ 45/ 0F 2C FA cvttsd2si r15d, xmm10 \n"
" \n"
" 0000BDB6 F3/ 45/ 0F 2A D7 cvtsi2ss xmm10, r15d \n"
" 0000BDBB F2/ 45/ 0F 2A D7 cvtsi2sd xmm10, r15d \n"
" \n"
" 0000BDC0 F3/ 4D/ 0F 2C FA cvttss2si r15, xmm10 \n"
" 0000BDC5 F2/ 4D/ 0F 2C FA cvttsd2si r15, xmm10 \n"
" \n"
" 0000BDCA F3/ 4D/ 0F 2A D7 cvtsi2ss xmm10, r15 \n"
" 0000BDCF F2/ 4D/ 0F 2A D7 cvtsi2sd xmm10, r15 \n"
" \n"
" \n"
" ; Between: xmm11 and rax \n"
" 0000BDD4 F3/ 44/ 0F 11 58 movss dword ptr [rax - 4], xmm11 \n"
" FC \n"
" 0000BDDA F2/ 44/ 0F 11 58 movsd qword ptr [rax + 4], xmm11 \n"
" 04 \n"
" \n"
" 0000BDE0 F3/ 44/ 0F 10 58 movss xmm11, dword ptr [rax - 4] \n"
" FC \n"
" 0000BDE6 F2/ 44/ 0F 10 58 movsd xmm11, qword ptr [rax + 4] \n"
" 04 \n"
" 0000BDEC F3/ 4C/ 0F 2A 58 cvtsi2ss xmm11, qword ptr [rax - 4] \n"
" FC \n"
" 0000BDF2 F2/ 44/ 0F 2A 58 cvtsi2sd xmm11, dword ptr [rax + 4] \n"
" 04 \n"
" \n"
" 0000BDF8 F3/ 41/ 0F 2C C3 cvttss2si eax, xmm11 \n"
" 0000BDFD F2/ 41/ 0F 2C C3 cvttsd2si eax, xmm11 \n"
" \n"
" 0000BE02 F3/ 44/ 0F 2A D8 cvtsi2ss xmm11, eax \n"
" 0000BE07 F2/ 44/ 0F 2A D8 cvtsi2sd xmm11, eax \n"
" \n"
" 0000BE0C F3/ 49/ 0F 2C C3 cvttss2si rax, xmm11 \n"
" 0000BE11 F2/ 49/ 0F 2C C3 cvttsd2si rax, xmm11 \n"
" \n"
" 0000BE16 F3/ 4C/ 0F 2A D8 cvtsi2ss xmm11, rax \n"
" 0000BE1B F2/ 4C/ 0F 2A D8 cvtsi2sd xmm11, rax \n"
" \n"
" \n"
" ; Between: xmm11 and rcx \n"
" 0000BE20 F3/ 44/ 0F 11 59 movss dword ptr [rcx - 4], xmm11 \n"
" FC \n"
" 0000BE26 F2/ 44/ 0F 11 59 movsd qword ptr [rcx + 4], xmm11 \n"
" 04 \n"
" \n"
" 0000BE2C F3/ 44/ 0F 10 59 movss xmm11, dword ptr [rcx - 4] \n"
" FC \n"
" 0000BE32 F2/ 44/ 0F 10 59 movsd xmm11, qword ptr [rcx + 4] \n"
" 04 \n"
" 0000BE38 F3/ 4C/ 0F 2A 59 cvtsi2ss xmm11, qword ptr [rcx - 4] \n"
" FC \n"
" 0000BE3E F2/ 44/ 0F 2A 59 cvtsi2sd xmm11, dword ptr [rcx + 4] \n"
" 04 \n"
" \n"
" 0000BE44 F3/ 41/ 0F 2C CB cvttss2si ecx, xmm11 \n"
" 0000BE49 F2/ 41/ 0F 2C CB cvttsd2si ecx, xmm11 \n"
" \n"
" 0000BE4E F3/ 44/ 0F 2A D9 cvtsi2ss xmm11, ecx \n"
" 0000BE53 F2/ 44/ 0F 2A D9 cvtsi2sd xmm11, ecx \n"
" \n"
" 0000BE58 F3/ 49/ 0F 2C CB cvttss2si rcx, xmm11 \n"
" 0000BE5D F2/ 49/ 0F 2C CB cvttsd2si rcx, xmm11 \n"
" \n"
" 0000BE62 F3/ 4C/ 0F 2A D9 cvtsi2ss xmm11, rcx \n"
" 0000BE67 F2/ 4C/ 0F 2A D9 cvtsi2sd xmm11, rcx \n"
" \n"
" \n"
" ; Between: xmm11 and rdx \n"
" 0000BE6C F3/ 44/ 0F 11 5A movss dword ptr [rdx - 4], xmm11 \n"
" FC \n"
" 0000BE72 F2/ 44/ 0F 11 5A movsd qword ptr [rdx + 4], xmm11 \n"
" 04 \n"
" \n"
" 0000BE78 F3/ 44/ 0F 10 5A movss xmm11, dword ptr [rdx - 4] \n"
" FC \n"
" 0000BE7E F2/ 44/ 0F 10 5A movsd xmm11, qword ptr [rdx + 4] \n"
" 04 \n"
" 0000BE84 F3/ 4C/ 0F 2A 5A cvtsi2ss xmm11, qword ptr [rdx - 4] \n"
" FC \n"
" 0000BE8A F2/ 44/ 0F 2A 5A cvtsi2sd xmm11, dword ptr [rdx + 4] \n"
" 04 \n"
" \n"
" 0000BE90 F3/ 41/ 0F 2C D3 cvttss2si edx, xmm11 \n"
" 0000BE95 F2/ 41/ 0F 2C D3 cvttsd2si edx, xmm11 \n"
" \n"
" 0000BE9A F3/ 44/ 0F 2A DA cvtsi2ss xmm11, edx \n"
" 0000BE9F F2/ 44/ 0F 2A DA cvtsi2sd xmm11, edx \n"
" \n"
" 0000BEA4 F3/ 49/ 0F 2C D3 cvttss2si rdx, xmm11 \n"
" 0000BEA9 F2/ 49/ 0F 2C D3 cvttsd2si rdx, xmm11 \n"
" \n"
" 0000BEAE F3/ 4C/ 0F 2A DA cvtsi2ss xmm11, rdx \n"
" 0000BEB3 F2/ 4C/ 0F 2A DA cvtsi2sd xmm11, rdx \n"
" \n"
" \n"
" ; Between: xmm11 and rbx \n"
" 0000BEB8 F3/ 44/ 0F 11 5B movss dword ptr [rbx - 4], xmm11 \n"
" FC \n"
" 0000BEBE F2/ 44/ 0F 11 5B movsd qword ptr [rbx + 4], xmm11 \n"
" 04 \n"
" \n"
" 0000BEC4 F3/ 44/ 0F 10 5B movss xmm11, dword ptr [rbx - 4] \n"
" FC \n"
" 0000BECA F2/ 44/ 0F 10 5B movsd xmm11, qword ptr [rbx + 4] \n"
" 04 \n"
" 0000BED0 F3/ 4C/ 0F 2A 5B cvtsi2ss xmm11, qword ptr [rbx - 4] \n"
" FC \n"
" 0000BED6 F2/ 44/ 0F 2A 5B cvtsi2sd xmm11, dword ptr [rbx + 4] \n"
" 04 \n"
" \n"
" 0000BEDC F3/ 41/ 0F 2C DB cvttss2si ebx, xmm11 \n"
" 0000BEE1 F2/ 41/ 0F 2C DB cvttsd2si ebx, xmm11 \n"
" \n"
" 0000BEE6 F3/ 44/ 0F 2A DB cvtsi2ss xmm11, ebx \n"
" 0000BEEB F2/ 44/ 0F 2A DB cvtsi2sd xmm11, ebx \n"
" \n"
" 0000BEF0 F3/ 49/ 0F 2C DB cvttss2si rbx, xmm11 \n"
" 0000BEF5 F2/ 49/ 0F 2C DB cvttsd2si rbx, xmm11 \n"
" \n"
" 0000BEFA F3/ 4C/ 0F 2A DB cvtsi2ss xmm11, rbx \n"
" 0000BEFF F2/ 4C/ 0F 2A DB cvtsi2sd xmm11, rbx \n"
" \n"
" \n"
" ; Between: xmm11 and rsp \n"
" 0000BF04 F3/ 44/ 0F 11 5C movss dword ptr [rsp - 4], xmm11 \n"
" 24 FC \n"
" 0000BF0B F2/ 44/ 0F 11 5C movsd qword ptr [rsp + 4], xmm11 \n"
" 24 04 \n"
" \n"
" 0000BF12 F3/ 44/ 0F 10 5C movss xmm11, dword ptr [rsp - 4] \n"
" 24 FC \n"
" 0000BF19 F2/ 44/ 0F 10 5C movsd xmm11, qword ptr [rsp + 4] \n"
" 24 04 \n"
" 0000BF20 F3/ 4C/ 0F 2A 5C cvtsi2ss xmm11, qword ptr [rsp - 4] \n"
" 24 FC \n"
" 0000BF27 F2/ 44/ 0F 2A 5C cvtsi2sd xmm11, dword ptr [rsp + 4] \n"
" 24 04 \n"
" \n"
" 0000BF2E F3/ 41/ 0F 2C E3 cvttss2si esp, xmm11 \n"
" 0000BF33 F2/ 41/ 0F 2C E3 cvttsd2si esp, xmm11 \n"
" \n"
" 0000BF38 F3/ 44/ 0F 2A DC cvtsi2ss xmm11, esp \n"
" 0000BF3D F2/ 44/ 0F 2A DC cvtsi2sd xmm11, esp \n"
" \n"
" 0000BF42 F3/ 49/ 0F 2C E3 cvttss2si rsp, xmm11 \n"
" 0000BF47 F2/ 49/ 0F 2C E3 cvttsd2si rsp, xmm11 \n"
" \n"
" 0000BF4C F3/ 4C/ 0F 2A DC cvtsi2ss xmm11, rsp \n"
" 0000BF51 F2/ 4C/ 0F 2A DC cvtsi2sd xmm11, rsp \n"
" \n"
" \n"
" ; Between: xmm11 and rbp \n"
" 0000BF56 F3/ 44/ 0F 11 5D movss dword ptr [rbp - 4], xmm11 \n"
" FC \n"
" 0000BF5C F2/ 44/ 0F 11 5D movsd qword ptr [rbp + 4], xmm11 \n"
" 04 \n"
" \n"
" 0000BF62 F3/ 44/ 0F 10 5D movss xmm11, dword ptr [rbp - 4] \n"
" FC \n"
" 0000BF68 F2/ 44/ 0F 10 5D movsd xmm11, qword ptr [rbp + 4] \n"
" 04 \n"
" 0000BF6E F3/ 4C/ 0F 2A 5D cvtsi2ss xmm11, qword ptr [rbp - 4] \n"
" FC \n"
" 0000BF74 F2/ 44/ 0F 2A 5D cvtsi2sd xmm11, dword ptr [rbp + 4] \n"
" 04 \n"
" \n"
" 0000BF7A F3/ 41/ 0F 2C EB cvttss2si ebp, xmm11 \n"
" 0000BF7F F2/ 41/ 0F 2C EB cvttsd2si ebp, xmm11 \n"
" \n"
" 0000BF84 F3/ 44/ 0F 2A DD cvtsi2ss xmm11, ebp \n"
" 0000BF89 F2/ 44/ 0F 2A DD cvtsi2sd xmm11, ebp \n"
" \n"
" 0000BF8E F3/ 49/ 0F 2C EB cvttss2si rbp, xmm11 \n"
" 0000BF93 F2/ 49/ 0F 2C EB cvttsd2si rbp, xmm11 \n"
" \n"
" 0000BF98 F3/ 4C/ 0F 2A DD cvtsi2ss xmm11, rbp \n"
" 0000BF9D F2/ 4C/ 0F 2A DD cvtsi2sd xmm11, rbp \n"
" \n"
" \n"
" ; Between: xmm11 and rsi \n"
" 0000BFA2 F3/ 44/ 0F 11 5E movss dword ptr [rsi - 4], xmm11 \n"
" FC \n"
" 0000BFA8 F2/ 44/ 0F 11 5E movsd qword ptr [rsi + 4], xmm11 \n"
" 04 \n"
" \n"
" 0000BFAE F3/ 44/ 0F 10 5E movss xmm11, dword ptr [rsi - 4] \n"
" FC \n"
" 0000BFB4 F2/ 44/ 0F 10 5E movsd xmm11, qword ptr [rsi + 4] \n"
" 04 \n"
" 0000BFBA F3/ 4C/ 0F 2A 5E cvtsi2ss xmm11, qword ptr [rsi - 4] \n"
" FC \n"
" 0000BFC0 F2/ 44/ 0F 2A 5E cvtsi2sd xmm11, dword ptr [rsi + 4] \n"
" 04 \n"
" \n"
" 0000BFC6 F3/ 41/ 0F 2C F3 cvttss2si esi, xmm11 \n"
" 0000BFCB F2/ 41/ 0F 2C F3 cvttsd2si esi, xmm11 \n"
" \n"
" 0000BFD0 F3/ 44/ 0F 2A DE cvtsi2ss xmm11, esi \n"
" 0000BFD5 F2/ 44/ 0F 2A DE cvtsi2sd xmm11, esi \n"
" \n"
" 0000BFDA F3/ 49/ 0F 2C F3 cvttss2si rsi, xmm11 \n"
" 0000BFDF F2/ 49/ 0F 2C F3 cvttsd2si rsi, xmm11 \n"
" \n"
" 0000BFE4 F3/ 4C/ 0F 2A DE cvtsi2ss xmm11, rsi \n"
" 0000BFE9 F2/ 4C/ 0F 2A DE cvtsi2sd xmm11, rsi \n"
" \n"
" \n"
" ; Between: xmm11 and rdi \n"
" 0000BFEE F3/ 44/ 0F 11 5F movss dword ptr [rdi - 4], xmm11 \n"
" FC \n"
" 0000BFF4 F2/ 44/ 0F 11 5F movsd qword ptr [rdi + 4], xmm11 \n"
" 04 \n"
" \n"
" 0000BFFA F3/ 44/ 0F 10 5F movss xmm11, dword ptr [rdi - 4] \n"
" FC \n"
" 0000C000 F2/ 44/ 0F 10 5F movsd xmm11, qword ptr [rdi + 4] \n"
" 04 \n"
" 0000C006 F3/ 4C/ 0F 2A 5F cvtsi2ss xmm11, qword ptr [rdi - 4] \n"
" FC \n"
" 0000C00C F2/ 44/ 0F 2A 5F cvtsi2sd xmm11, dword ptr [rdi + 4] \n"
" 04 \n"
" \n"
" 0000C012 F3/ 41/ 0F 2C FB cvttss2si edi, xmm11 \n"
" 0000C017 F2/ 41/ 0F 2C FB cvttsd2si edi, xmm11 \n"
" \n"
" 0000C01C F3/ 44/ 0F 2A DF cvtsi2ss xmm11, edi \n"
" 0000C021 F2/ 44/ 0F 2A DF cvtsi2sd xmm11, edi \n"
" \n"
" 0000C026 F3/ 49/ 0F 2C FB cvttss2si rdi, xmm11 \n"
" 0000C02B F2/ 49/ 0F 2C FB cvttsd2si rdi, xmm11 \n"
" \n"
" 0000C030 F3/ 4C/ 0F 2A DF cvtsi2ss xmm11, rdi \n"
" 0000C035 F2/ 4C/ 0F 2A DF cvtsi2sd xmm11, rdi \n"
" \n"
" \n"
" ; Between: xmm11 and r8 \n"
" 0000C03A F3/ 45/ 0F 11 58 movss dword ptr [r8 - 4], xmm11 \n"
" FC \n"
" 0000C040 F2/ 45/ 0F 11 58 movsd qword ptr [r8 + 4], xmm11 \n"
" 04 \n"
" \n"
" 0000C046 F3/ 45/ 0F 10 58 movss xmm11, dword ptr [r8 - 4] \n"
" FC \n"
" 0000C04C F2/ 45/ 0F 10 58 movsd xmm11, qword ptr [r8 + 4] \n"
" 04 \n"
" 0000C052 F3/ 4D/ 0F 2A 58 cvtsi2ss xmm11, qword ptr [r8 - 4] \n"
" FC \n"
" 0000C058 F2/ 45/ 0F 2A 58 cvtsi2sd xmm11, dword ptr [r8 + 4] \n"
" 04 \n"
" \n"
" 0000C05E F3/ 45/ 0F 2C C3 cvttss2si r8d, xmm11 \n"
" 0000C063 F2/ 45/ 0F 2C C3 cvttsd2si r8d, xmm11 \n"
" \n"
" 0000C068 F3/ 45/ 0F 2A D8 cvtsi2ss xmm11, r8d \n"
" 0000C06D F2/ 45/ 0F 2A D8 cvtsi2sd xmm11, r8d \n"
" \n"
" 0000C072 F3/ 4D/ 0F 2C C3 cvttss2si r8, xmm11 \n"
" 0000C077 F2/ 4D/ 0F 2C C3 cvttsd2si r8, xmm11 \n"
" \n"
" 0000C07C F3/ 4D/ 0F 2A D8 cvtsi2ss xmm11, r8 \n"
" 0000C081 F2/ 4D/ 0F 2A D8 cvtsi2sd xmm11, r8 \n"
" \n"
" \n"
" ; Between: xmm11 and r9 \n"
" 0000C086 F3/ 45/ 0F 11 59 movss dword ptr [r9 - 4], xmm11 \n"
" FC \n"
" 0000C08C F2/ 45/ 0F 11 59 movsd qword ptr [r9 + 4], xmm11 \n"
" 04 \n"
" \n"
" 0000C092 F3/ 45/ 0F 10 59 movss xmm11, dword ptr [r9 - 4] \n"
" FC \n"
" 0000C098 F2/ 45/ 0F 10 59 movsd xmm11, qword ptr [r9 + 4] \n"
" 04 \n"
" 0000C09E F3/ 4D/ 0F 2A 59 cvtsi2ss xmm11, qword ptr [r9 - 4] \n"
" FC \n"
" 0000C0A4 F2/ 45/ 0F 2A 59 cvtsi2sd xmm11, dword ptr [r9 + 4] \n"
" 04 \n"
" \n"
" 0000C0AA F3/ 45/ 0F 2C CB cvttss2si r9d, xmm11 \n"
" 0000C0AF F2/ 45/ 0F 2C CB cvttsd2si r9d, xmm11 \n"
" \n"
" 0000C0B4 F3/ 45/ 0F 2A D9 cvtsi2ss xmm11, r9d \n"
" 0000C0B9 F2/ 45/ 0F 2A D9 cvtsi2sd xmm11, r9d \n"
" \n"
" 0000C0BE F3/ 4D/ 0F 2C CB cvttss2si r9, xmm11 \n"
" 0000C0C3 F2/ 4D/ 0F 2C CB cvttsd2si r9, xmm11 \n"
" \n"
" 0000C0C8 F3/ 4D/ 0F 2A D9 cvtsi2ss xmm11, r9 \n"
" 0000C0CD F2/ 4D/ 0F 2A D9 cvtsi2sd xmm11, r9 \n"
" \n"
" \n"
" ; Between: xmm11 and r10 \n"
" 0000C0D2 F3/ 45/ 0F 11 5A movss dword ptr [r10 - 4], xmm11 \n"
" FC \n"
" 0000C0D8 F2/ 45/ 0F 11 5A movsd qword ptr [r10 + 4], xmm11 \n"
" 04 \n"
" \n"
" 0000C0DE F3/ 45/ 0F 10 5A movss xmm11, dword ptr [r10 - 4] \n"
" FC \n"
" 0000C0E4 F2/ 45/ 0F 10 5A movsd xmm11, qword ptr [r10 + 4] \n"
" 04 \n"
" 0000C0EA F3/ 4D/ 0F 2A 5A cvtsi2ss xmm11, qword ptr [r10 - 4] \n"
" FC \n"
" 0000C0F0 F2/ 45/ 0F 2A 5A cvtsi2sd xmm11, dword ptr [r10 + 4] \n"
" 04 \n"
" \n"
" 0000C0F6 F3/ 45/ 0F 2C D3 cvttss2si r10d, xmm11 \n"
" 0000C0FB F2/ 45/ 0F 2C D3 cvttsd2si r10d, xmm11 \n"
" \n"
" 0000C100 F3/ 45/ 0F 2A DA cvtsi2ss xmm11, r10d \n"
" 0000C105 F2/ 45/ 0F 2A DA cvtsi2sd xmm11, r10d \n"
" \n"
" 0000C10A F3/ 4D/ 0F 2C D3 cvttss2si r10, xmm11 \n"
" 0000C10F F2/ 4D/ 0F 2C D3 cvttsd2si r10, xmm11 \n"
" \n"
" 0000C114 F3/ 4D/ 0F 2A DA cvtsi2ss xmm11, r10 \n"
" 0000C119 F2/ 4D/ 0F 2A DA cvtsi2sd xmm11, r10 \n"
" \n"
" \n"
" ; Between: xmm11 and r11 \n"
" 0000C11E F3/ 45/ 0F 11 5B movss dword ptr [r11 - 4], xmm11 \n"
" FC \n"
" 0000C124 F2/ 45/ 0F 11 5B movsd qword ptr [r11 + 4], xmm11 \n"
" 04 \n"
" \n"
" 0000C12A F3/ 45/ 0F 10 5B movss xmm11, dword ptr [r11 - 4] \n"
" FC \n"
" 0000C130 F2/ 45/ 0F 10 5B movsd xmm11, qword ptr [r11 + 4] \n"
" 04 \n"
" 0000C136 F3/ 4D/ 0F 2A 5B cvtsi2ss xmm11, qword ptr [r11 - 4] \n"
" FC \n"
" 0000C13C F2/ 45/ 0F 2A 5B cvtsi2sd xmm11, dword ptr [r11 + 4] \n"
" 04 \n"
" \n"
" 0000C142 F3/ 45/ 0F 2C DB cvttss2si r11d, xmm11 \n"
" 0000C147 F2/ 45/ 0F 2C DB cvttsd2si r11d, xmm11 \n"
" \n"
" 0000C14C F3/ 45/ 0F 2A DB cvtsi2ss xmm11, r11d \n"
" 0000C151 F2/ 45/ 0F 2A DB cvtsi2sd xmm11, r11d \n"
" \n"
" 0000C156 F3/ 4D/ 0F 2C DB cvttss2si r11, xmm11 \n"
" 0000C15B F2/ 4D/ 0F 2C DB cvttsd2si r11, xmm11 \n"
" \n"
" 0000C160 F3/ 4D/ 0F 2A DB cvtsi2ss xmm11, r11 \n"
" 0000C165 F2/ 4D/ 0F 2A DB cvtsi2sd xmm11, r11 \n"
" \n"
" \n"
" ; Between: xmm11 and r12 \n"
" 0000C16A F3/ 45/ 0F 11 5C movss dword ptr [r12 - 4], xmm11 \n"
" 24 FC \n"
" 0000C171 F2/ 45/ 0F 11 5C movsd qword ptr [r12 + 4], xmm11 \n"
" 24 04 \n"
" \n"
" 0000C178 F3/ 45/ 0F 10 5C movss xmm11, dword ptr [r12 - 4] \n"
" 24 FC \n"
" 0000C17F F2/ 45/ 0F 10 5C movsd xmm11, qword ptr [r12 + 4] \n"
" 24 04 \n"
" 0000C186 F3/ 4D/ 0F 2A 5C cvtsi2ss xmm11, qword ptr [r12 - 4] \n"
" 24 FC \n"
" 0000C18D F2/ 45/ 0F 2A 5C cvtsi2sd xmm11, dword ptr [r12 + 4] \n"
" 24 04 \n"
" \n"
" 0000C194 F3/ 45/ 0F 2C E3 cvttss2si r12d, xmm11 \n"
" 0000C199 F2/ 45/ 0F 2C E3 cvttsd2si r12d, xmm11 \n"
" \n"
" 0000C19E F3/ 45/ 0F 2A DC cvtsi2ss xmm11, r12d \n"
" 0000C1A3 F2/ 45/ 0F 2A DC cvtsi2sd xmm11, r12d \n"
" \n"
" 0000C1A8 F3/ 4D/ 0F 2C E3 cvttss2si r12, xmm11 \n"
" 0000C1AD F2/ 4D/ 0F 2C E3 cvttsd2si r12, xmm11 \n"
" \n"
" 0000C1B2 F3/ 4D/ 0F 2A DC cvtsi2ss xmm11, r12 \n"
" 0000C1B7 F2/ 4D/ 0F 2A DC cvtsi2sd xmm11, r12 \n"
" \n"
" \n"
" ; Between: xmm11 and r13 \n"
" 0000C1BC F3/ 45/ 0F 11 5D movss dword ptr [r13 - 4], xmm11 \n"
" FC \n"
" 0000C1C2 F2/ 45/ 0F 11 5D movsd qword ptr [r13 + 4], xmm11 \n"
" 04 \n"
" \n"
" 0000C1C8 F3/ 45/ 0F 10 5D movss xmm11, dword ptr [r13 - 4] \n"
" FC \n"
" 0000C1CE F2/ 45/ 0F 10 5D movsd xmm11, qword ptr [r13 + 4] \n"
" 04 \n"
" 0000C1D4 F3/ 4D/ 0F 2A 5D cvtsi2ss xmm11, qword ptr [r13 - 4] \n"
" FC \n"
" 0000C1DA F2/ 45/ 0F 2A 5D cvtsi2sd xmm11, dword ptr [r13 + 4] \n"
" 04 \n"
" \n"
" 0000C1E0 F3/ 45/ 0F 2C EB cvttss2si r13d, xmm11 \n"
" 0000C1E5 F2/ 45/ 0F 2C EB cvttsd2si r13d, xmm11 \n"
" \n"
" 0000C1EA F3/ 45/ 0F 2A DD cvtsi2ss xmm11, r13d \n"
" 0000C1EF F2/ 45/ 0F 2A DD cvtsi2sd xmm11, r13d \n"
" \n"
" 0000C1F4 F3/ 4D/ 0F 2C EB cvttss2si r13, xmm11 \n"
" 0000C1F9 F2/ 4D/ 0F 2C EB cvttsd2si r13, xmm11 \n"
" \n"
" 0000C1FE F3/ 4D/ 0F 2A DD cvtsi2ss xmm11, r13 \n"
" 0000C203 F2/ 4D/ 0F 2A DD cvtsi2sd xmm11, r13 \n"
" \n"
" \n"
" ; Between: xmm11 and r14 \n"
" 0000C208 F3/ 45/ 0F 11 5E movss dword ptr [r14 - 4], xmm11 \n"
" FC \n"
" 0000C20E F2/ 45/ 0F 11 5E movsd qword ptr [r14 + 4], xmm11 \n"
" 04 \n"
" \n"
" 0000C214 F3/ 45/ 0F 10 5E movss xmm11, dword ptr [r14 - 4] \n"
" FC \n"
" 0000C21A F2/ 45/ 0F 10 5E movsd xmm11, qword ptr [r14 + 4] \n"
" 04 \n"
" 0000C220 F3/ 4D/ 0F 2A 5E cvtsi2ss xmm11, qword ptr [r14 - 4] \n"
" FC \n"
" 0000C226 F2/ 45/ 0F 2A 5E cvtsi2sd xmm11, dword ptr [r14 + 4] \n"
" 04 \n"
" \n"
" 0000C22C F3/ 45/ 0F 2C F3 cvttss2si r14d, xmm11 \n"
" 0000C231 F2/ 45/ 0F 2C F3 cvttsd2si r14d, xmm11 \n"
" \n"
" 0000C236 F3/ 45/ 0F 2A DE cvtsi2ss xmm11, r14d \n"
" 0000C23B F2/ 45/ 0F 2A DE cvtsi2sd xmm11, r14d \n"
" \n"
" 0000C240 F3/ 4D/ 0F 2C F3 cvttss2si r14, xmm11 \n"
" 0000C245 F2/ 4D/ 0F 2C F3 cvttsd2si r14, xmm11 \n"
" \n"
" 0000C24A F3/ 4D/ 0F 2A DE cvtsi2ss xmm11, r14 \n"
" 0000C24F F2/ 4D/ 0F 2A DE cvtsi2sd xmm11, r14 \n"
" \n"
" \n"
" ; Between: xmm11 and r15 \n"
" 0000C254 F3/ 45/ 0F 11 5F movss dword ptr [r15 - 4], xmm11 \n"
" FC \n"
" 0000C25A F2/ 45/ 0F 11 5F movsd qword ptr [r15 + 4], xmm11 \n"
" 04 \n"
" \n"
" 0000C260 F3/ 45/ 0F 10 5F movss xmm11, dword ptr [r15 - 4] \n"
" FC \n"
" 0000C266 F2/ 45/ 0F 10 5F movsd xmm11, qword ptr [r15 + 4] \n"
" 04 \n"
" 0000C26C F3/ 4D/ 0F 2A 5F cvtsi2ss xmm11, qword ptr [r15 - 4] \n"
" FC \n"
" 0000C272 F2/ 45/ 0F 2A 5F cvtsi2sd xmm11, dword ptr [r15 + 4] \n"
" 04 \n"
" \n"
" 0000C278 F3/ 45/ 0F 2C FB cvttss2si r15d, xmm11 \n"
" 0000C27D F2/ 45/ 0F 2C FB cvttsd2si r15d, xmm11 \n"
" \n"
" 0000C282 F3/ 45/ 0F 2A DF cvtsi2ss xmm11, r15d \n"
" 0000C287 F2/ 45/ 0F 2A DF cvtsi2sd xmm11, r15d \n"
" \n"
" 0000C28C F3/ 4D/ 0F 2C FB cvttss2si r15, xmm11 \n"
" 0000C291 F2/ 4D/ 0F 2C FB cvttsd2si r15, xmm11 \n"
" \n"
" 0000C296 F3/ 4D/ 0F 2A DF cvtsi2ss xmm11, r15 \n"
" 0000C29B F2/ 4D/ 0F 2A DF cvtsi2sd xmm11, r15 \n"
" \n"
" \n"
" ; Between: xmm12 and rax \n"
" 0000C2A0 F3/ 44/ 0F 11 60 movss dword ptr [rax - 4], xmm12 \n"
" FC \n"
" 0000C2A6 F2/ 44/ 0F 11 60 movsd qword ptr [rax + 4], xmm12 \n"
" 04 \n"
" \n"
" 0000C2AC F3/ 44/ 0F 10 60 movss xmm12, dword ptr [rax - 4] \n"
" FC \n"
" 0000C2B2 F2/ 44/ 0F 10 60 movsd xmm12, qword ptr [rax + 4] \n"
" 04 \n"
" 0000C2B8 F3/ 4C/ 0F 2A 60 cvtsi2ss xmm12, qword ptr [rax - 4] \n"
" FC \n"
" 0000C2BE F2/ 44/ 0F 2A 60 cvtsi2sd xmm12, dword ptr [rax + 4] \n"
" 04 \n"
" \n"
" 0000C2C4 F3/ 41/ 0F 2C C4 cvttss2si eax, xmm12 \n"
" 0000C2C9 F2/ 41/ 0F 2C C4 cvttsd2si eax, xmm12 \n"
" \n"
" 0000C2CE F3/ 44/ 0F 2A E0 cvtsi2ss xmm12, eax \n"
" 0000C2D3 F2/ 44/ 0F 2A E0 cvtsi2sd xmm12, eax \n"
" \n"
" 0000C2D8 F3/ 49/ 0F 2C C4 cvttss2si rax, xmm12 \n"
" 0000C2DD F2/ 49/ 0F 2C C4 cvttsd2si rax, xmm12 \n"
" \n"
" 0000C2E2 F3/ 4C/ 0F 2A E0 cvtsi2ss xmm12, rax \n"
" 0000C2E7 F2/ 4C/ 0F 2A E0 cvtsi2sd xmm12, rax \n"
" \n"
" \n"
" ; Between: xmm12 and rcx \n"
" 0000C2EC F3/ 44/ 0F 11 61 movss dword ptr [rcx - 4], xmm12 \n"
" FC \n"
" 0000C2F2 F2/ 44/ 0F 11 61 movsd qword ptr [rcx + 4], xmm12 \n"
" 04 \n"
" \n"
" 0000C2F8 F3/ 44/ 0F 10 61 movss xmm12, dword ptr [rcx - 4] \n"
" FC \n"
" 0000C2FE F2/ 44/ 0F 10 61 movsd xmm12, qword ptr [rcx + 4] \n"
" 04 \n"
" 0000C304 F3/ 4C/ 0F 2A 61 cvtsi2ss xmm12, qword ptr [rcx - 4] \n"
" FC \n"
" 0000C30A F2/ 44/ 0F 2A 61 cvtsi2sd xmm12, dword ptr [rcx + 4] \n"
" 04 \n"
" \n"
" 0000C310 F3/ 41/ 0F 2C CC cvttss2si ecx, xmm12 \n"
" 0000C315 F2/ 41/ 0F 2C CC cvttsd2si ecx, xmm12 \n"
" \n"
" 0000C31A F3/ 44/ 0F 2A E1 cvtsi2ss xmm12, ecx \n"
" 0000C31F F2/ 44/ 0F 2A E1 cvtsi2sd xmm12, ecx \n"
" \n"
" 0000C324 F3/ 49/ 0F 2C CC cvttss2si rcx, xmm12 \n"
" 0000C329 F2/ 49/ 0F 2C CC cvttsd2si rcx, xmm12 \n"
" \n";
ml64Output +=
" 0000C32E F3/ 4C/ 0F 2A E1 cvtsi2ss xmm12, rcx \n"
" 0000C333 F2/ 4C/ 0F 2A E1 cvtsi2sd xmm12, rcx \n"
" \n"
" \n"
" ; Between: xmm12 and rdx \n"
" 0000C338 F3/ 44/ 0F 11 62 movss dword ptr [rdx - 4], xmm12 \n"
" FC \n"
" 0000C33E F2/ 44/ 0F 11 62 movsd qword ptr [rdx + 4], xmm12 \n"
" 04 \n"
" \n"
" 0000C344 F3/ 44/ 0F 10 62 movss xmm12, dword ptr [rdx - 4] \n"
" FC \n"
" 0000C34A F2/ 44/ 0F 10 62 movsd xmm12, qword ptr [rdx + 4] \n"
" 04 \n"
" 0000C350 F3/ 4C/ 0F 2A 62 cvtsi2ss xmm12, qword ptr [rdx - 4] \n"
" FC \n"
" 0000C356 F2/ 44/ 0F 2A 62 cvtsi2sd xmm12, dword ptr [rdx + 4] \n"
" 04 \n"
" \n"
" 0000C35C F3/ 41/ 0F 2C D4 cvttss2si edx, xmm12 \n"
" 0000C361 F2/ 41/ 0F 2C D4 cvttsd2si edx, xmm12 \n"
" \n"
" 0000C366 F3/ 44/ 0F 2A E2 cvtsi2ss xmm12, edx \n"
" 0000C36B F2/ 44/ 0F 2A E2 cvtsi2sd xmm12, edx \n"
" \n"
" 0000C370 F3/ 49/ 0F 2C D4 cvttss2si rdx, xmm12 \n"
" 0000C375 F2/ 49/ 0F 2C D4 cvttsd2si rdx, xmm12 \n"
" \n"
" 0000C37A F3/ 4C/ 0F 2A E2 cvtsi2ss xmm12, rdx \n"
" 0000C37F F2/ 4C/ 0F 2A E2 cvtsi2sd xmm12, rdx \n"
" \n"
" \n"
" ; Between: xmm12 and rbx \n"
" 0000C384 F3/ 44/ 0F 11 63 movss dword ptr [rbx - 4], xmm12 \n"
" FC \n"
" 0000C38A F2/ 44/ 0F 11 63 movsd qword ptr [rbx + 4], xmm12 \n"
" 04 \n"
" \n"
" 0000C390 F3/ 44/ 0F 10 63 movss xmm12, dword ptr [rbx - 4] \n"
" FC \n"
" 0000C396 F2/ 44/ 0F 10 63 movsd xmm12, qword ptr [rbx + 4] \n"
" 04 \n"
" 0000C39C F3/ 4C/ 0F 2A 63 cvtsi2ss xmm12, qword ptr [rbx - 4] \n"
" FC \n"
" 0000C3A2 F2/ 44/ 0F 2A 63 cvtsi2sd xmm12, dword ptr [rbx + 4] \n"
" 04 \n"
" \n"
" 0000C3A8 F3/ 41/ 0F 2C DC cvttss2si ebx, xmm12 \n"
" 0000C3AD F2/ 41/ 0F 2C DC cvttsd2si ebx, xmm12 \n"
" \n"
" 0000C3B2 F3/ 44/ 0F 2A E3 cvtsi2ss xmm12, ebx \n"
" 0000C3B7 F2/ 44/ 0F 2A E3 cvtsi2sd xmm12, ebx \n"
" \n"
" 0000C3BC F3/ 49/ 0F 2C DC cvttss2si rbx, xmm12 \n"
" 0000C3C1 F2/ 49/ 0F 2C DC cvttsd2si rbx, xmm12 \n"
" \n"
" 0000C3C6 F3/ 4C/ 0F 2A E3 cvtsi2ss xmm12, rbx \n"
" 0000C3CB F2/ 4C/ 0F 2A E3 cvtsi2sd xmm12, rbx \n"
" \n"
" \n"
" ; Between: xmm12 and rsp \n"
" 0000C3D0 F3/ 44/ 0F 11 64 movss dword ptr [rsp - 4], xmm12 \n"
" 24 FC \n"
" 0000C3D7 F2/ 44/ 0F 11 64 movsd qword ptr [rsp + 4], xmm12 \n"
" 24 04 \n"
" \n"
" 0000C3DE F3/ 44/ 0F 10 64 movss xmm12, dword ptr [rsp - 4] \n"
" 24 FC \n"
" 0000C3E5 F2/ 44/ 0F 10 64 movsd xmm12, qword ptr [rsp + 4] \n"
" 24 04 \n"
" 0000C3EC F3/ 4C/ 0F 2A 64 cvtsi2ss xmm12, qword ptr [rsp - 4] \n"
" 24 FC \n"
" 0000C3F3 F2/ 44/ 0F 2A 64 cvtsi2sd xmm12, dword ptr [rsp + 4] \n"
" 24 04 \n"
" \n"
" 0000C3FA F3/ 41/ 0F 2C E4 cvttss2si esp, xmm12 \n"
" 0000C3FF F2/ 41/ 0F 2C E4 cvttsd2si esp, xmm12 \n"
" \n"
" 0000C404 F3/ 44/ 0F 2A E4 cvtsi2ss xmm12, esp \n"
" 0000C409 F2/ 44/ 0F 2A E4 cvtsi2sd xmm12, esp \n"
" \n"
" 0000C40E F3/ 49/ 0F 2C E4 cvttss2si rsp, xmm12 \n"
" 0000C413 F2/ 49/ 0F 2C E4 cvttsd2si rsp, xmm12 \n"
" \n"
" 0000C418 F3/ 4C/ 0F 2A E4 cvtsi2ss xmm12, rsp \n"
" 0000C41D F2/ 4C/ 0F 2A E4 cvtsi2sd xmm12, rsp \n"
" \n"
" \n"
" ; Between: xmm12 and rbp \n"
" 0000C422 F3/ 44/ 0F 11 65 movss dword ptr [rbp - 4], xmm12 \n"
" FC \n"
" 0000C428 F2/ 44/ 0F 11 65 movsd qword ptr [rbp + 4], xmm12 \n"
" 04 \n"
" \n"
" 0000C42E F3/ 44/ 0F 10 65 movss xmm12, dword ptr [rbp - 4] \n"
" FC \n"
" 0000C434 F2/ 44/ 0F 10 65 movsd xmm12, qword ptr [rbp + 4] \n"
" 04 \n"
" 0000C43A F3/ 4C/ 0F 2A 65 cvtsi2ss xmm12, qword ptr [rbp - 4] \n"
" FC \n"
" 0000C440 F2/ 44/ 0F 2A 65 cvtsi2sd xmm12, dword ptr [rbp + 4] \n"
" 04 \n"
" \n"
" 0000C446 F3/ 41/ 0F 2C EC cvttss2si ebp, xmm12 \n"
" 0000C44B F2/ 41/ 0F 2C EC cvttsd2si ebp, xmm12 \n"
" \n"
" 0000C450 F3/ 44/ 0F 2A E5 cvtsi2ss xmm12, ebp \n"
" 0000C455 F2/ 44/ 0F 2A E5 cvtsi2sd xmm12, ebp \n"
" \n"
" 0000C45A F3/ 49/ 0F 2C EC cvttss2si rbp, xmm12 \n"
" 0000C45F F2/ 49/ 0F 2C EC cvttsd2si rbp, xmm12 \n"
" \n"
" 0000C464 F3/ 4C/ 0F 2A E5 cvtsi2ss xmm12, rbp \n"
" 0000C469 F2/ 4C/ 0F 2A E5 cvtsi2sd xmm12, rbp \n"
" \n"
" \n"
" ; Between: xmm12 and rsi \n"
" 0000C46E F3/ 44/ 0F 11 66 movss dword ptr [rsi - 4], xmm12 \n"
" FC \n"
" 0000C474 F2/ 44/ 0F 11 66 movsd qword ptr [rsi + 4], xmm12 \n"
" 04 \n"
" \n"
" 0000C47A F3/ 44/ 0F 10 66 movss xmm12, dword ptr [rsi - 4] \n"
" FC \n"
" 0000C480 F2/ 44/ 0F 10 66 movsd xmm12, qword ptr [rsi + 4] \n"
" 04 \n"
" 0000C486 F3/ 4C/ 0F 2A 66 cvtsi2ss xmm12, qword ptr [rsi - 4] \n"
" FC \n"
" 0000C48C F2/ 44/ 0F 2A 66 cvtsi2sd xmm12, dword ptr [rsi + 4] \n"
" 04 \n"
" \n"
" 0000C492 F3/ 41/ 0F 2C F4 cvttss2si esi, xmm12 \n"
" 0000C497 F2/ 41/ 0F 2C F4 cvttsd2si esi, xmm12 \n"
" \n"
" 0000C49C F3/ 44/ 0F 2A E6 cvtsi2ss xmm12, esi \n"
" 0000C4A1 F2/ 44/ 0F 2A E6 cvtsi2sd xmm12, esi \n"
" \n"
" 0000C4A6 F3/ 49/ 0F 2C F4 cvttss2si rsi, xmm12 \n"
" 0000C4AB F2/ 49/ 0F 2C F4 cvttsd2si rsi, xmm12 \n"
" \n"
" 0000C4B0 F3/ 4C/ 0F 2A E6 cvtsi2ss xmm12, rsi \n"
" 0000C4B5 F2/ 4C/ 0F 2A E6 cvtsi2sd xmm12, rsi \n"
" \n"
" \n"
" ; Between: xmm12 and rdi \n"
" 0000C4BA F3/ 44/ 0F 11 67 movss dword ptr [rdi - 4], xmm12 \n"
" FC \n"
" 0000C4C0 F2/ 44/ 0F 11 67 movsd qword ptr [rdi + 4], xmm12 \n"
" 04 \n"
" \n"
" 0000C4C6 F3/ 44/ 0F 10 67 movss xmm12, dword ptr [rdi - 4] \n"
" FC \n"
" 0000C4CC F2/ 44/ 0F 10 67 movsd xmm12, qword ptr [rdi + 4] \n"
" 04 \n"
" 0000C4D2 F3/ 4C/ 0F 2A 67 cvtsi2ss xmm12, qword ptr [rdi - 4] \n"
" FC \n"
" 0000C4D8 F2/ 44/ 0F 2A 67 cvtsi2sd xmm12, dword ptr [rdi + 4] \n"
" 04 \n"
" \n"
" 0000C4DE F3/ 41/ 0F 2C FC cvttss2si edi, xmm12 \n"
" 0000C4E3 F2/ 41/ 0F 2C FC cvttsd2si edi, xmm12 \n"
" \n"
" 0000C4E8 F3/ 44/ 0F 2A E7 cvtsi2ss xmm12, edi \n"
" 0000C4ED F2/ 44/ 0F 2A E7 cvtsi2sd xmm12, edi \n"
" \n"
" 0000C4F2 F3/ 49/ 0F 2C FC cvttss2si rdi, xmm12 \n"
" 0000C4F7 F2/ 49/ 0F 2C FC cvttsd2si rdi, xmm12 \n"
" \n"
" 0000C4FC F3/ 4C/ 0F 2A E7 cvtsi2ss xmm12, rdi \n"
" 0000C501 F2/ 4C/ 0F 2A E7 cvtsi2sd xmm12, rdi \n"
" \n"
" \n"
" ; Between: xmm12 and r8 \n"
" 0000C506 F3/ 45/ 0F 11 60 movss dword ptr [r8 - 4], xmm12 \n"
" FC \n"
" 0000C50C F2/ 45/ 0F 11 60 movsd qword ptr [r8 + 4], xmm12 \n"
" 04 \n"
" \n"
" 0000C512 F3/ 45/ 0F 10 60 movss xmm12, dword ptr [r8 - 4] \n"
" FC \n"
" 0000C518 F2/ 45/ 0F 10 60 movsd xmm12, qword ptr [r8 + 4] \n"
" 04 \n"
" 0000C51E F3/ 4D/ 0F 2A 60 cvtsi2ss xmm12, qword ptr [r8 - 4] \n"
" FC \n"
" 0000C524 F2/ 45/ 0F 2A 60 cvtsi2sd xmm12, dword ptr [r8 + 4] \n"
" 04 \n"
" \n"
" 0000C52A F3/ 45/ 0F 2C C4 cvttss2si r8d, xmm12 \n"
" 0000C52F F2/ 45/ 0F 2C C4 cvttsd2si r8d, xmm12 \n"
" \n"
" 0000C534 F3/ 45/ 0F 2A E0 cvtsi2ss xmm12, r8d \n"
" 0000C539 F2/ 45/ 0F 2A E0 cvtsi2sd xmm12, r8d \n"
" \n"
" 0000C53E F3/ 4D/ 0F 2C C4 cvttss2si r8, xmm12 \n"
" 0000C543 F2/ 4D/ 0F 2C C4 cvttsd2si r8, xmm12 \n"
" \n"
" 0000C548 F3/ 4D/ 0F 2A E0 cvtsi2ss xmm12, r8 \n"
" 0000C54D F2/ 4D/ 0F 2A E0 cvtsi2sd xmm12, r8 \n"
" \n"
" \n"
" ; Between: xmm12 and r9 \n"
" 0000C552 F3/ 45/ 0F 11 61 movss dword ptr [r9 - 4], xmm12 \n"
" FC \n"
" 0000C558 F2/ 45/ 0F 11 61 movsd qword ptr [r9 + 4], xmm12 \n"
" 04 \n"
" \n"
" 0000C55E F3/ 45/ 0F 10 61 movss xmm12, dword ptr [r9 - 4] \n"
" FC \n"
" 0000C564 F2/ 45/ 0F 10 61 movsd xmm12, qword ptr [r9 + 4] \n"
" 04 \n"
" 0000C56A F3/ 4D/ 0F 2A 61 cvtsi2ss xmm12, qword ptr [r9 - 4] \n"
" FC \n"
" 0000C570 F2/ 45/ 0F 2A 61 cvtsi2sd xmm12, dword ptr [r9 + 4] \n"
" 04 \n"
" \n"
" 0000C576 F3/ 45/ 0F 2C CC cvttss2si r9d, xmm12 \n"
" 0000C57B F2/ 45/ 0F 2C CC cvttsd2si r9d, xmm12 \n"
" \n"
" 0000C580 F3/ 45/ 0F 2A E1 cvtsi2ss xmm12, r9d \n"
" 0000C585 F2/ 45/ 0F 2A E1 cvtsi2sd xmm12, r9d \n"
" \n"
" 0000C58A F3/ 4D/ 0F 2C CC cvttss2si r9, xmm12 \n"
" 0000C58F F2/ 4D/ 0F 2C CC cvttsd2si r9, xmm12 \n"
" \n"
" 0000C594 F3/ 4D/ 0F 2A E1 cvtsi2ss xmm12, r9 \n"
" 0000C599 F2/ 4D/ 0F 2A E1 cvtsi2sd xmm12, r9 \n"
" \n"
" \n"
" ; Between: xmm12 and r10 \n"
" 0000C59E F3/ 45/ 0F 11 62 movss dword ptr [r10 - 4], xmm12 \n"
" FC \n"
" 0000C5A4 F2/ 45/ 0F 11 62 movsd qword ptr [r10 + 4], xmm12 \n"
" 04 \n"
" \n"
" 0000C5AA F3/ 45/ 0F 10 62 movss xmm12, dword ptr [r10 - 4] \n"
" FC \n"
" 0000C5B0 F2/ 45/ 0F 10 62 movsd xmm12, qword ptr [r10 + 4] \n"
" 04 \n"
" 0000C5B6 F3/ 4D/ 0F 2A 62 cvtsi2ss xmm12, qword ptr [r10 - 4] \n"
" FC \n"
" 0000C5BC F2/ 45/ 0F 2A 62 cvtsi2sd xmm12, dword ptr [r10 + 4] \n"
" 04 \n"
" \n"
" 0000C5C2 F3/ 45/ 0F 2C D4 cvttss2si r10d, xmm12 \n"
" 0000C5C7 F2/ 45/ 0F 2C D4 cvttsd2si r10d, xmm12 \n"
" \n"
" 0000C5CC F3/ 45/ 0F 2A E2 cvtsi2ss xmm12, r10d \n"
" 0000C5D1 F2/ 45/ 0F 2A E2 cvtsi2sd xmm12, r10d \n"
" \n"
" 0000C5D6 F3/ 4D/ 0F 2C D4 cvttss2si r10, xmm12 \n"
" 0000C5DB F2/ 4D/ 0F 2C D4 cvttsd2si r10, xmm12 \n"
" \n"
" 0000C5E0 F3/ 4D/ 0F 2A E2 cvtsi2ss xmm12, r10 \n"
" 0000C5E5 F2/ 4D/ 0F 2A E2 cvtsi2sd xmm12, r10 \n"
" \n"
" \n"
" ; Between: xmm12 and r11 \n"
" 0000C5EA F3/ 45/ 0F 11 63 movss dword ptr [r11 - 4], xmm12 \n"
" FC \n"
" 0000C5F0 F2/ 45/ 0F 11 63 movsd qword ptr [r11 + 4], xmm12 \n"
" 04 \n"
" \n"
" 0000C5F6 F3/ 45/ 0F 10 63 movss xmm12, dword ptr [r11 - 4] \n"
" FC \n"
" 0000C5FC F2/ 45/ 0F 10 63 movsd xmm12, qword ptr [r11 + 4] \n"
" 04 \n"
" 0000C602 F3/ 4D/ 0F 2A 63 cvtsi2ss xmm12, qword ptr [r11 - 4] \n"
" FC \n"
" 0000C608 F2/ 45/ 0F 2A 63 cvtsi2sd xmm12, dword ptr [r11 + 4] \n"
" 04 \n"
" \n"
" 0000C60E F3/ 45/ 0F 2C DC cvttss2si r11d, xmm12 \n"
" 0000C613 F2/ 45/ 0F 2C DC cvttsd2si r11d, xmm12 \n"
" \n"
" 0000C618 F3/ 45/ 0F 2A E3 cvtsi2ss xmm12, r11d \n"
" 0000C61D F2/ 45/ 0F 2A E3 cvtsi2sd xmm12, r11d \n"
" \n"
" 0000C622 F3/ 4D/ 0F 2C DC cvttss2si r11, xmm12 \n"
" 0000C627 F2/ 4D/ 0F 2C DC cvttsd2si r11, xmm12 \n"
" \n"
" 0000C62C F3/ 4D/ 0F 2A E3 cvtsi2ss xmm12, r11 \n"
" 0000C631 F2/ 4D/ 0F 2A E3 cvtsi2sd xmm12, r11 \n"
" \n"
" \n"
" ; Between: xmm12 and r12 \n"
" 0000C636 F3/ 45/ 0F 11 64 movss dword ptr [r12 - 4], xmm12 \n"
" 24 FC \n"
" 0000C63D F2/ 45/ 0F 11 64 movsd qword ptr [r12 + 4], xmm12 \n"
" 24 04 \n"
" \n"
" 0000C644 F3/ 45/ 0F 10 64 movss xmm12, dword ptr [r12 - 4] \n"
" 24 FC \n"
" 0000C64B F2/ 45/ 0F 10 64 movsd xmm12, qword ptr [r12 + 4] \n"
" 24 04 \n"
" 0000C652 F3/ 4D/ 0F 2A 64 cvtsi2ss xmm12, qword ptr [r12 - 4] \n"
" 24 FC \n"
" 0000C659 F2/ 45/ 0F 2A 64 cvtsi2sd xmm12, dword ptr [r12 + 4] \n"
" 24 04 \n"
" \n"
" 0000C660 F3/ 45/ 0F 2C E4 cvttss2si r12d, xmm12 \n"
" 0000C665 F2/ 45/ 0F 2C E4 cvttsd2si r12d, xmm12 \n"
" \n"
" 0000C66A F3/ 45/ 0F 2A E4 cvtsi2ss xmm12, r12d \n"
" 0000C66F F2/ 45/ 0F 2A E4 cvtsi2sd xmm12, r12d \n"
" \n"
" 0000C674 F3/ 4D/ 0F 2C E4 cvttss2si r12, xmm12 \n"
" 0000C679 F2/ 4D/ 0F 2C E4 cvttsd2si r12, xmm12 \n"
" \n"
" 0000C67E F3/ 4D/ 0F 2A E4 cvtsi2ss xmm12, r12 \n"
" 0000C683 F2/ 4D/ 0F 2A E4 cvtsi2sd xmm12, r12 \n"
" \n"
" \n"
" ; Between: xmm12 and r13 \n"
" 0000C688 F3/ 45/ 0F 11 65 movss dword ptr [r13 - 4], xmm12 \n"
" FC \n"
" 0000C68E F2/ 45/ 0F 11 65 movsd qword ptr [r13 + 4], xmm12 \n"
" 04 \n"
" \n"
" 0000C694 F3/ 45/ 0F 10 65 movss xmm12, dword ptr [r13 - 4] \n"
" FC \n"
" 0000C69A F2/ 45/ 0F 10 65 movsd xmm12, qword ptr [r13 + 4] \n"
" 04 \n"
" 0000C6A0 F3/ 4D/ 0F 2A 65 cvtsi2ss xmm12, qword ptr [r13 - 4] \n"
" FC \n"
" 0000C6A6 F2/ 45/ 0F 2A 65 cvtsi2sd xmm12, dword ptr [r13 + 4] \n"
" 04 \n"
" \n"
" 0000C6AC F3/ 45/ 0F 2C EC cvttss2si r13d, xmm12 \n"
" 0000C6B1 F2/ 45/ 0F 2C EC cvttsd2si r13d, xmm12 \n"
" \n"
" 0000C6B6 F3/ 45/ 0F 2A E5 cvtsi2ss xmm12, r13d \n"
" 0000C6BB F2/ 45/ 0F 2A E5 cvtsi2sd xmm12, r13d \n"
" \n"
" 0000C6C0 F3/ 4D/ 0F 2C EC cvttss2si r13, xmm12 \n"
" 0000C6C5 F2/ 4D/ 0F 2C EC cvttsd2si r13, xmm12 \n"
" \n"
" 0000C6CA F3/ 4D/ 0F 2A E5 cvtsi2ss xmm12, r13 \n"
" 0000C6CF F2/ 4D/ 0F 2A E5 cvtsi2sd xmm12, r13 \n"
" \n"
" \n"
" ; Between: xmm12 and r14 \n"
" 0000C6D4 F3/ 45/ 0F 11 66 movss dword ptr [r14 - 4], xmm12 \n"
" FC \n"
" 0000C6DA F2/ 45/ 0F 11 66 movsd qword ptr [r14 + 4], xmm12 \n"
" 04 \n"
" \n"
" 0000C6E0 F3/ 45/ 0F 10 66 movss xmm12, dword ptr [r14 - 4] \n"
" FC \n"
" 0000C6E6 F2/ 45/ 0F 10 66 movsd xmm12, qword ptr [r14 + 4] \n"
" 04 \n"
" 0000C6EC F3/ 4D/ 0F 2A 66 cvtsi2ss xmm12, qword ptr [r14 - 4] \n"
" FC \n"
" 0000C6F2 F2/ 45/ 0F 2A 66 cvtsi2sd xmm12, dword ptr [r14 + 4] \n"
" 04 \n"
" \n"
" 0000C6F8 F3/ 45/ 0F 2C F4 cvttss2si r14d, xmm12 \n"
" 0000C6FD F2/ 45/ 0F 2C F4 cvttsd2si r14d, xmm12 \n"
" \n"
" 0000C702 F3/ 45/ 0F 2A E6 cvtsi2ss xmm12, r14d \n"
" 0000C707 F2/ 45/ 0F 2A E6 cvtsi2sd xmm12, r14d \n"
" \n"
" 0000C70C F3/ 4D/ 0F 2C F4 cvttss2si r14, xmm12 \n"
" 0000C711 F2/ 4D/ 0F 2C F4 cvttsd2si r14, xmm12 \n"
" \n"
" 0000C716 F3/ 4D/ 0F 2A E6 cvtsi2ss xmm12, r14 \n"
" 0000C71B F2/ 4D/ 0F 2A E6 cvtsi2sd xmm12, r14 \n"
" \n"
" \n"
" ; Between: xmm12 and r15 \n"
" 0000C720 F3/ 45/ 0F 11 67 movss dword ptr [r15 - 4], xmm12 \n"
" FC \n"
" 0000C726 F2/ 45/ 0F 11 67 movsd qword ptr [r15 + 4], xmm12 \n"
" 04 \n"
" \n"
" 0000C72C F3/ 45/ 0F 10 67 movss xmm12, dword ptr [r15 - 4] \n"
" FC \n"
" 0000C732 F2/ 45/ 0F 10 67 movsd xmm12, qword ptr [r15 + 4] \n"
" 04 \n"
" 0000C738 F3/ 4D/ 0F 2A 67 cvtsi2ss xmm12, qword ptr [r15 - 4] \n"
" FC \n"
" 0000C73E F2/ 45/ 0F 2A 67 cvtsi2sd xmm12, dword ptr [r15 + 4] \n"
" 04 \n"
" \n"
" 0000C744 F3/ 45/ 0F 2C FC cvttss2si r15d, xmm12 \n"
" 0000C749 F2/ 45/ 0F 2C FC cvttsd2si r15d, xmm12 \n"
" \n"
" 0000C74E F3/ 45/ 0F 2A E7 cvtsi2ss xmm12, r15d \n"
" 0000C753 F2/ 45/ 0F 2A E7 cvtsi2sd xmm12, r15d \n"
" \n"
" 0000C758 F3/ 4D/ 0F 2C FC cvttss2si r15, xmm12 \n"
" 0000C75D F2/ 4D/ 0F 2C FC cvttsd2si r15, xmm12 \n"
" \n"
" 0000C762 F3/ 4D/ 0F 2A E7 cvtsi2ss xmm12, r15 \n"
" 0000C767 F2/ 4D/ 0F 2A E7 cvtsi2sd xmm12, r15 \n"
" \n"
" \n"
" ; Between: xmm13 and rax \n"
" 0000C76C F3/ 44/ 0F 11 68 movss dword ptr [rax - 4], xmm13 \n"
" FC \n"
" 0000C772 F2/ 44/ 0F 11 68 movsd qword ptr [rax + 4], xmm13 \n"
" 04 \n"
" \n"
" 0000C778 F3/ 44/ 0F 10 68 movss xmm13, dword ptr [rax - 4] \n"
" FC \n"
" 0000C77E F2/ 44/ 0F 10 68 movsd xmm13, qword ptr [rax + 4] \n"
" 04 \n"
" 0000C784 F3/ 4C/ 0F 2A 68 cvtsi2ss xmm13, qword ptr [rax - 4] \n"
" FC \n"
" 0000C78A F2/ 44/ 0F 2A 68 cvtsi2sd xmm13, dword ptr [rax + 4] \n"
" 04 \n"
" \n"
" 0000C790 F3/ 41/ 0F 2C C5 cvttss2si eax, xmm13 \n"
" 0000C795 F2/ 41/ 0F 2C C5 cvttsd2si eax, xmm13 \n"
" \n"
" 0000C79A F3/ 44/ 0F 2A E8 cvtsi2ss xmm13, eax \n"
" 0000C79F F2/ 44/ 0F 2A E8 cvtsi2sd xmm13, eax \n"
" \n"
" 0000C7A4 F3/ 49/ 0F 2C C5 cvttss2si rax, xmm13 \n"
" 0000C7A9 F2/ 49/ 0F 2C C5 cvttsd2si rax, xmm13 \n"
" \n"
" 0000C7AE F3/ 4C/ 0F 2A E8 cvtsi2ss xmm13, rax \n"
" 0000C7B3 F2/ 4C/ 0F 2A E8 cvtsi2sd xmm13, rax \n"
" \n"
" \n"
" ; Between: xmm13 and rcx \n"
" 0000C7B8 F3/ 44/ 0F 11 69 movss dword ptr [rcx - 4], xmm13 \n"
" FC \n"
" 0000C7BE F2/ 44/ 0F 11 69 movsd qword ptr [rcx + 4], xmm13 \n"
" 04 \n"
" \n"
" 0000C7C4 F3/ 44/ 0F 10 69 movss xmm13, dword ptr [rcx - 4] \n"
" FC \n"
" 0000C7CA F2/ 44/ 0F 10 69 movsd xmm13, qword ptr [rcx + 4] \n"
" 04 \n"
" 0000C7D0 F3/ 4C/ 0F 2A 69 cvtsi2ss xmm13, qword ptr [rcx - 4] \n"
" FC \n"
" 0000C7D6 F2/ 44/ 0F 2A 69 cvtsi2sd xmm13, dword ptr [rcx + 4] \n"
" 04 \n"
" \n"
" 0000C7DC F3/ 41/ 0F 2C CD cvttss2si ecx, xmm13 \n"
" 0000C7E1 F2/ 41/ 0F 2C CD cvttsd2si ecx, xmm13 \n"
" \n"
" 0000C7E6 F3/ 44/ 0F 2A E9 cvtsi2ss xmm13, ecx \n"
" 0000C7EB F2/ 44/ 0F 2A E9 cvtsi2sd xmm13, ecx \n"
" \n"
" 0000C7F0 F3/ 49/ 0F 2C CD cvttss2si rcx, xmm13 \n"
" 0000C7F5 F2/ 49/ 0F 2C CD cvttsd2si rcx, xmm13 \n"
" \n"
" 0000C7FA F3/ 4C/ 0F 2A E9 cvtsi2ss xmm13, rcx \n"
" 0000C7FF F2/ 4C/ 0F 2A E9 cvtsi2sd xmm13, rcx \n"
" \n"
" \n"
" ; Between: xmm13 and rdx \n"
" 0000C804 F3/ 44/ 0F 11 6A movss dword ptr [rdx - 4], xmm13 \n"
" FC \n"
" 0000C80A F2/ 44/ 0F 11 6A movsd qword ptr [rdx + 4], xmm13 \n"
" 04 \n"
" \n"
" 0000C810 F3/ 44/ 0F 10 6A movss xmm13, dword ptr [rdx - 4] \n"
" FC \n"
" 0000C816 F2/ 44/ 0F 10 6A movsd xmm13, qword ptr [rdx + 4] \n"
" 04 \n"
" 0000C81C F3/ 4C/ 0F 2A 6A cvtsi2ss xmm13, qword ptr [rdx - 4] \n"
" FC \n"
" 0000C822 F2/ 44/ 0F 2A 6A cvtsi2sd xmm13, dword ptr [rdx + 4] \n"
" 04 \n"
" \n"
" 0000C828 F3/ 41/ 0F 2C D5 cvttss2si edx, xmm13 \n"
" 0000C82D F2/ 41/ 0F 2C D5 cvttsd2si edx, xmm13 \n"
" \n"
" 0000C832 F3/ 44/ 0F 2A EA cvtsi2ss xmm13, edx \n"
" 0000C837 F2/ 44/ 0F 2A EA cvtsi2sd xmm13, edx \n"
" \n"
" 0000C83C F3/ 49/ 0F 2C D5 cvttss2si rdx, xmm13 \n"
" 0000C841 F2/ 49/ 0F 2C D5 cvttsd2si rdx, xmm13 \n"
" \n"
" 0000C846 F3/ 4C/ 0F 2A EA cvtsi2ss xmm13, rdx \n"
" 0000C84B F2/ 4C/ 0F 2A EA cvtsi2sd xmm13, rdx \n"
" \n"
" \n"
" ; Between: xmm13 and rbx \n"
" 0000C850 F3/ 44/ 0F 11 6B movss dword ptr [rbx - 4], xmm13 \n"
" FC \n"
" 0000C856 F2/ 44/ 0F 11 6B movsd qword ptr [rbx + 4], xmm13 \n"
" 04 \n"
" \n"
" 0000C85C F3/ 44/ 0F 10 6B movss xmm13, dword ptr [rbx - 4] \n"
" FC \n"
" 0000C862 F2/ 44/ 0F 10 6B movsd xmm13, qword ptr [rbx + 4] \n"
" 04 \n"
" 0000C868 F3/ 4C/ 0F 2A 6B cvtsi2ss xmm13, qword ptr [rbx - 4] \n"
" FC \n"
" 0000C86E F2/ 44/ 0F 2A 6B cvtsi2sd xmm13, dword ptr [rbx + 4] \n"
" 04 \n"
" \n"
" 0000C874 F3/ 41/ 0F 2C DD cvttss2si ebx, xmm13 \n"
" 0000C879 F2/ 41/ 0F 2C DD cvttsd2si ebx, xmm13 \n"
" \n"
" 0000C87E F3/ 44/ 0F 2A EB cvtsi2ss xmm13, ebx \n"
" 0000C883 F2/ 44/ 0F 2A EB cvtsi2sd xmm13, ebx \n"
" \n"
" 0000C888 F3/ 49/ 0F 2C DD cvttss2si rbx, xmm13 \n"
" 0000C88D F2/ 49/ 0F 2C DD cvttsd2si rbx, xmm13 \n"
" \n"
" 0000C892 F3/ 4C/ 0F 2A EB cvtsi2ss xmm13, rbx \n"
" 0000C897 F2/ 4C/ 0F 2A EB cvtsi2sd xmm13, rbx \n"
" \n"
" \n"
" ; Between: xmm13 and rsp \n"
" 0000C89C F3/ 44/ 0F 11 6C movss dword ptr [rsp - 4], xmm13 \n"
" 24 FC \n"
" 0000C8A3 F2/ 44/ 0F 11 6C movsd qword ptr [rsp + 4], xmm13 \n"
" 24 04 \n"
" \n"
" 0000C8AA F3/ 44/ 0F 10 6C movss xmm13, dword ptr [rsp - 4] \n"
" 24 FC \n"
" 0000C8B1 F2/ 44/ 0F 10 6C movsd xmm13, qword ptr [rsp + 4] \n"
" 24 04 \n"
" 0000C8B8 F3/ 4C/ 0F 2A 6C cvtsi2ss xmm13, qword ptr [rsp - 4] \n"
" 24 FC \n"
" 0000C8BF F2/ 44/ 0F 2A 6C cvtsi2sd xmm13, dword ptr [rsp + 4] \n"
" 24 04 \n"
" \n"
" 0000C8C6 F3/ 41/ 0F 2C E5 cvttss2si esp, xmm13 \n"
" 0000C8CB F2/ 41/ 0F 2C E5 cvttsd2si esp, xmm13 \n"
" \n"
" 0000C8D0 F3/ 44/ 0F 2A EC cvtsi2ss xmm13, esp \n"
" 0000C8D5 F2/ 44/ 0F 2A EC cvtsi2sd xmm13, esp \n"
" \n"
" 0000C8DA F3/ 49/ 0F 2C E5 cvttss2si rsp, xmm13 \n"
" 0000C8DF F2/ 49/ 0F 2C E5 cvttsd2si rsp, xmm13 \n"
" \n"
" 0000C8E4 F3/ 4C/ 0F 2A EC cvtsi2ss xmm13, rsp \n"
" 0000C8E9 F2/ 4C/ 0F 2A EC cvtsi2sd xmm13, rsp \n"
" \n"
" \n"
" ; Between: xmm13 and rbp \n"
" 0000C8EE F3/ 44/ 0F 11 6D movss dword ptr [rbp - 4], xmm13 \n"
" FC \n"
" 0000C8F4 F2/ 44/ 0F 11 6D movsd qword ptr [rbp + 4], xmm13 \n"
" 04 \n"
" \n"
" 0000C8FA F3/ 44/ 0F 10 6D movss xmm13, dword ptr [rbp - 4] \n"
" FC \n"
" 0000C900 F2/ 44/ 0F 10 6D movsd xmm13, qword ptr [rbp + 4] \n"
" 04 \n"
" 0000C906 F3/ 4C/ 0F 2A 6D cvtsi2ss xmm13, qword ptr [rbp - 4] \n"
" FC \n"
" 0000C90C F2/ 44/ 0F 2A 6D cvtsi2sd xmm13, dword ptr [rbp + 4] \n"
" 04 \n";
ml64Output +=
" \n"
" 0000C912 F3/ 41/ 0F 2C ED cvttss2si ebp, xmm13 \n"
" 0000C917 F2/ 41/ 0F 2C ED cvttsd2si ebp, xmm13 \n"
" \n"
" 0000C91C F3/ 44/ 0F 2A ED cvtsi2ss xmm13, ebp \n"
" 0000C921 F2/ 44/ 0F 2A ED cvtsi2sd xmm13, ebp \n"
" \n"
" 0000C926 F3/ 49/ 0F 2C ED cvttss2si rbp, xmm13 \n"
" 0000C92B F2/ 49/ 0F 2C ED cvttsd2si rbp, xmm13 \n"
" \n"
" 0000C930 F3/ 4C/ 0F 2A ED cvtsi2ss xmm13, rbp \n"
" 0000C935 F2/ 4C/ 0F 2A ED cvtsi2sd xmm13, rbp \n"
" \n"
" \n"
" ; Between: xmm13 and rsi \n"
" 0000C93A F3/ 44/ 0F 11 6E movss dword ptr [rsi - 4], xmm13 \n"
" FC \n"
" 0000C940 F2/ 44/ 0F 11 6E movsd qword ptr [rsi + 4], xmm13 \n"
" 04 \n"
" \n"
" 0000C946 F3/ 44/ 0F 10 6E movss xmm13, dword ptr [rsi - 4] \n"
" FC \n"
" 0000C94C F2/ 44/ 0F 10 6E movsd xmm13, qword ptr [rsi + 4] \n"
" 04 \n"
" 0000C952 F3/ 4C/ 0F 2A 6E cvtsi2ss xmm13, qword ptr [rsi - 4] \n"
" FC \n"
" 0000C958 F2/ 44/ 0F 2A 6E cvtsi2sd xmm13, dword ptr [rsi + 4] \n"
" 04 \n"
" \n"
" 0000C95E F3/ 41/ 0F 2C F5 cvttss2si esi, xmm13 \n"
" 0000C963 F2/ 41/ 0F 2C F5 cvttsd2si esi, xmm13 \n"
" \n"
" 0000C968 F3/ 44/ 0F 2A EE cvtsi2ss xmm13, esi \n"
" 0000C96D F2/ 44/ 0F 2A EE cvtsi2sd xmm13, esi \n"
" \n"
" 0000C972 F3/ 49/ 0F 2C F5 cvttss2si rsi, xmm13 \n"
" 0000C977 F2/ 49/ 0F 2C F5 cvttsd2si rsi, xmm13 \n"
" \n"
" 0000C97C F3/ 4C/ 0F 2A EE cvtsi2ss xmm13, rsi \n"
" 0000C981 F2/ 4C/ 0F 2A EE cvtsi2sd xmm13, rsi \n"
" \n"
" \n"
" ; Between: xmm13 and rdi \n"
" 0000C986 F3/ 44/ 0F 11 6F movss dword ptr [rdi - 4], xmm13 \n"
" FC \n"
" 0000C98C F2/ 44/ 0F 11 6F movsd qword ptr [rdi + 4], xmm13 \n"
" 04 \n"
" \n"
" 0000C992 F3/ 44/ 0F 10 6F movss xmm13, dword ptr [rdi - 4] \n"
" FC \n"
" 0000C998 F2/ 44/ 0F 10 6F movsd xmm13, qword ptr [rdi + 4] \n"
" 04 \n"
" 0000C99E F3/ 4C/ 0F 2A 6F cvtsi2ss xmm13, qword ptr [rdi - 4] \n"
" FC \n"
" 0000C9A4 F2/ 44/ 0F 2A 6F cvtsi2sd xmm13, dword ptr [rdi + 4] \n"
" 04 \n"
" \n"
" 0000C9AA F3/ 41/ 0F 2C FD cvttss2si edi, xmm13 \n"
" 0000C9AF F2/ 41/ 0F 2C FD cvttsd2si edi, xmm13 \n"
" \n"
" 0000C9B4 F3/ 44/ 0F 2A EF cvtsi2ss xmm13, edi \n"
" 0000C9B9 F2/ 44/ 0F 2A EF cvtsi2sd xmm13, edi \n"
" \n"
" 0000C9BE F3/ 49/ 0F 2C FD cvttss2si rdi, xmm13 \n"
" 0000C9C3 F2/ 49/ 0F 2C FD cvttsd2si rdi, xmm13 \n"
" \n"
" 0000C9C8 F3/ 4C/ 0F 2A EF cvtsi2ss xmm13, rdi \n"
" 0000C9CD F2/ 4C/ 0F 2A EF cvtsi2sd xmm13, rdi \n"
" \n"
" \n"
" ; Between: xmm13 and r8 \n"
" 0000C9D2 F3/ 45/ 0F 11 68 movss dword ptr [r8 - 4], xmm13 \n"
" FC \n"
" 0000C9D8 F2/ 45/ 0F 11 68 movsd qword ptr [r8 + 4], xmm13 \n"
" 04 \n"
" \n"
" 0000C9DE F3/ 45/ 0F 10 68 movss xmm13, dword ptr [r8 - 4] \n"
" FC \n"
" 0000C9E4 F2/ 45/ 0F 10 68 movsd xmm13, qword ptr [r8 + 4] \n"
" 04 \n"
" 0000C9EA F3/ 4D/ 0F 2A 68 cvtsi2ss xmm13, qword ptr [r8 - 4] \n"
" FC \n"
" 0000C9F0 F2/ 45/ 0F 2A 68 cvtsi2sd xmm13, dword ptr [r8 + 4] \n"
" 04 \n"
" \n"
" 0000C9F6 F3/ 45/ 0F 2C C5 cvttss2si r8d, xmm13 \n"
" 0000C9FB F2/ 45/ 0F 2C C5 cvttsd2si r8d, xmm13 \n"
" \n"
" 0000CA00 F3/ 45/ 0F 2A E8 cvtsi2ss xmm13, r8d \n"
" 0000CA05 F2/ 45/ 0F 2A E8 cvtsi2sd xmm13, r8d \n"
" \n"
" 0000CA0A F3/ 4D/ 0F 2C C5 cvttss2si r8, xmm13 \n"
" 0000CA0F F2/ 4D/ 0F 2C C5 cvttsd2si r8, xmm13 \n"
" \n"
" 0000CA14 F3/ 4D/ 0F 2A E8 cvtsi2ss xmm13, r8 \n"
" 0000CA19 F2/ 4D/ 0F 2A E8 cvtsi2sd xmm13, r8 \n"
" \n"
" \n"
" ; Between: xmm13 and r9 \n"
" 0000CA1E F3/ 45/ 0F 11 69 movss dword ptr [r9 - 4], xmm13 \n"
" FC \n"
" 0000CA24 F2/ 45/ 0F 11 69 movsd qword ptr [r9 + 4], xmm13 \n"
" 04 \n"
" \n"
" 0000CA2A F3/ 45/ 0F 10 69 movss xmm13, dword ptr [r9 - 4] \n"
" FC \n"
" 0000CA30 F2/ 45/ 0F 10 69 movsd xmm13, qword ptr [r9 + 4] \n"
" 04 \n"
" 0000CA36 F3/ 4D/ 0F 2A 69 cvtsi2ss xmm13, qword ptr [r9 - 4] \n"
" FC \n"
" 0000CA3C F2/ 45/ 0F 2A 69 cvtsi2sd xmm13, dword ptr [r9 + 4] \n"
" 04 \n"
" \n"
" 0000CA42 F3/ 45/ 0F 2C CD cvttss2si r9d, xmm13 \n"
" 0000CA47 F2/ 45/ 0F 2C CD cvttsd2si r9d, xmm13 \n"
" \n"
" 0000CA4C F3/ 45/ 0F 2A E9 cvtsi2ss xmm13, r9d \n"
" 0000CA51 F2/ 45/ 0F 2A E9 cvtsi2sd xmm13, r9d \n"
" \n"
" 0000CA56 F3/ 4D/ 0F 2C CD cvttss2si r9, xmm13 \n"
" 0000CA5B F2/ 4D/ 0F 2C CD cvttsd2si r9, xmm13 \n"
" \n"
" 0000CA60 F3/ 4D/ 0F 2A E9 cvtsi2ss xmm13, r9 \n"
" 0000CA65 F2/ 4D/ 0F 2A E9 cvtsi2sd xmm13, r9 \n"
" \n"
" \n"
" ; Between: xmm13 and r10 \n"
" 0000CA6A F3/ 45/ 0F 11 6A movss dword ptr [r10 - 4], xmm13 \n"
" FC \n"
" 0000CA70 F2/ 45/ 0F 11 6A movsd qword ptr [r10 + 4], xmm13 \n"
" 04 \n"
" \n"
" 0000CA76 F3/ 45/ 0F 10 6A movss xmm13, dword ptr [r10 - 4] \n"
" FC \n"
" 0000CA7C F2/ 45/ 0F 10 6A movsd xmm13, qword ptr [r10 + 4] \n"
" 04 \n"
" 0000CA82 F3/ 4D/ 0F 2A 6A cvtsi2ss xmm13, qword ptr [r10 - 4] \n"
" FC \n"
" 0000CA88 F2/ 45/ 0F 2A 6A cvtsi2sd xmm13, dword ptr [r10 + 4] \n"
" 04 \n"
" \n"
" 0000CA8E F3/ 45/ 0F 2C D5 cvttss2si r10d, xmm13 \n"
" 0000CA93 F2/ 45/ 0F 2C D5 cvttsd2si r10d, xmm13 \n"
" \n"
" 0000CA98 F3/ 45/ 0F 2A EA cvtsi2ss xmm13, r10d \n"
" 0000CA9D F2/ 45/ 0F 2A EA cvtsi2sd xmm13, r10d \n"
" \n"
" 0000CAA2 F3/ 4D/ 0F 2C D5 cvttss2si r10, xmm13 \n"
" 0000CAA7 F2/ 4D/ 0F 2C D5 cvttsd2si r10, xmm13 \n"
" \n"
" 0000CAAC F3/ 4D/ 0F 2A EA cvtsi2ss xmm13, r10 \n"
" 0000CAB1 F2/ 4D/ 0F 2A EA cvtsi2sd xmm13, r10 \n"
" \n"
" \n"
" ; Between: xmm13 and r11 \n"
" 0000CAB6 F3/ 45/ 0F 11 6B movss dword ptr [r11 - 4], xmm13 \n"
" FC \n"
" 0000CABC F2/ 45/ 0F 11 6B movsd qword ptr [r11 + 4], xmm13 \n"
" 04 \n"
" \n"
" 0000CAC2 F3/ 45/ 0F 10 6B movss xmm13, dword ptr [r11 - 4] \n"
" FC \n"
" 0000CAC8 F2/ 45/ 0F 10 6B movsd xmm13, qword ptr [r11 + 4] \n"
" 04 \n"
" 0000CACE F3/ 4D/ 0F 2A 6B cvtsi2ss xmm13, qword ptr [r11 - 4] \n"
" FC \n"
" 0000CAD4 F2/ 45/ 0F 2A 6B cvtsi2sd xmm13, dword ptr [r11 + 4] \n"
" 04 \n"
" \n"
" 0000CADA F3/ 45/ 0F 2C DD cvttss2si r11d, xmm13 \n"
" 0000CADF F2/ 45/ 0F 2C DD cvttsd2si r11d, xmm13 \n"
" \n"
" 0000CAE4 F3/ 45/ 0F 2A EB cvtsi2ss xmm13, r11d \n"
" 0000CAE9 F2/ 45/ 0F 2A EB cvtsi2sd xmm13, r11d \n"
" \n"
" 0000CAEE F3/ 4D/ 0F 2C DD cvttss2si r11, xmm13 \n"
" 0000CAF3 F2/ 4D/ 0F 2C DD cvttsd2si r11, xmm13 \n"
" \n"
" 0000CAF8 F3/ 4D/ 0F 2A EB cvtsi2ss xmm13, r11 \n"
" 0000CAFD F2/ 4D/ 0F 2A EB cvtsi2sd xmm13, r11 \n"
" \n"
" \n"
" ; Between: xmm13 and r12 \n"
" 0000CB02 F3/ 45/ 0F 11 6C movss dword ptr [r12 - 4], xmm13 \n"
" 24 FC \n"
" 0000CB09 F2/ 45/ 0F 11 6C movsd qword ptr [r12 + 4], xmm13 \n"
" 24 04 \n"
" \n"
" 0000CB10 F3/ 45/ 0F 10 6C movss xmm13, dword ptr [r12 - 4] \n"
" 24 FC \n"
" 0000CB17 F2/ 45/ 0F 10 6C movsd xmm13, qword ptr [r12 + 4] \n"
" 24 04 \n"
" 0000CB1E F3/ 4D/ 0F 2A 6C cvtsi2ss xmm13, qword ptr [r12 - 4] \n"
" 24 FC \n"
" 0000CB25 F2/ 45/ 0F 2A 6C cvtsi2sd xmm13, dword ptr [r12 + 4] \n"
" 24 04 \n"
" \n"
" 0000CB2C F3/ 45/ 0F 2C E5 cvttss2si r12d, xmm13 \n"
" 0000CB31 F2/ 45/ 0F 2C E5 cvttsd2si r12d, xmm13 \n"
" \n"
" 0000CB36 F3/ 45/ 0F 2A EC cvtsi2ss xmm13, r12d \n"
" 0000CB3B F2/ 45/ 0F 2A EC cvtsi2sd xmm13, r12d \n"
" \n"
" 0000CB40 F3/ 4D/ 0F 2C E5 cvttss2si r12, xmm13 \n"
" 0000CB45 F2/ 4D/ 0F 2C E5 cvttsd2si r12, xmm13 \n"
" \n"
" 0000CB4A F3/ 4D/ 0F 2A EC cvtsi2ss xmm13, r12 \n"
" 0000CB4F F2/ 4D/ 0F 2A EC cvtsi2sd xmm13, r12 \n"
" \n"
" \n"
" ; Between: xmm13 and r13 \n"
" 0000CB54 F3/ 45/ 0F 11 6D movss dword ptr [r13 - 4], xmm13 \n"
" FC \n"
" 0000CB5A F2/ 45/ 0F 11 6D movsd qword ptr [r13 + 4], xmm13 \n"
" 04 \n"
" \n"
" 0000CB60 F3/ 45/ 0F 10 6D movss xmm13, dword ptr [r13 - 4] \n"
" FC \n"
" 0000CB66 F2/ 45/ 0F 10 6D movsd xmm13, qword ptr [r13 + 4] \n"
" 04 \n"
" 0000CB6C F3/ 4D/ 0F 2A 6D cvtsi2ss xmm13, qword ptr [r13 - 4] \n"
" FC \n"
" 0000CB72 F2/ 45/ 0F 2A 6D cvtsi2sd xmm13, dword ptr [r13 + 4] \n"
" 04 \n"
" \n"
" 0000CB78 F3/ 45/ 0F 2C ED cvttss2si r13d, xmm13 \n"
" 0000CB7D F2/ 45/ 0F 2C ED cvttsd2si r13d, xmm13 \n"
" \n"
" 0000CB82 F3/ 45/ 0F 2A ED cvtsi2ss xmm13, r13d \n"
" 0000CB87 F2/ 45/ 0F 2A ED cvtsi2sd xmm13, r13d \n"
" \n"
" 0000CB8C F3/ 4D/ 0F 2C ED cvttss2si r13, xmm13 \n"
" 0000CB91 F2/ 4D/ 0F 2C ED cvttsd2si r13, xmm13 \n"
" \n"
" 0000CB96 F3/ 4D/ 0F 2A ED cvtsi2ss xmm13, r13 \n"
" 0000CB9B F2/ 4D/ 0F 2A ED cvtsi2sd xmm13, r13 \n"
" \n"
" \n"
"; Between: xmm13 and r14 \n"
" 0000CBA0 F3/ 45/ 0F 11 6E movss dword ptr [r14 - 4], xmm13 \n"
" FC \n"
" 0000CBA6 F2/ 45/ 0F 11 6E movsd qword ptr [r14 + 4], xmm13 \n"
" 04 \n"
" \n"
" 0000CBAC F3/ 45/ 0F 10 6E movss xmm13, dword ptr [r14 - 4] \n"
" FC \n"
" 0000CBB2 F2/ 45/ 0F 10 6E movsd xmm13, qword ptr [r14 + 4] \n"
" 04 \n"
" 0000CBB8 F3/ 4D/ 0F 2A 6E cvtsi2ss xmm13, qword ptr [r14 - 4] \n"
" FC \n"
" 0000CBBE F2/ 45/ 0F 2A 6E cvtsi2sd xmm13, dword ptr [r14 + 4] \n"
" 04 \n"
" \n"
" 0000CBC4 F3/ 45/ 0F 2C F5 cvttss2si r14d, xmm13 \n"
" 0000CBC9 F2/ 45/ 0F 2C F5 cvttsd2si r14d, xmm13 \n"
" \n"
" 0000CBCE F3/ 45/ 0F 2A EE cvtsi2ss xmm13, r14d \n"
" 0000CBD3 F2/ 45/ 0F 2A EE cvtsi2sd xmm13, r14d \n"
" \n"
" 0000CBD8 F3/ 4D/ 0F 2C F5 cvttss2si r14, xmm13 \n"
" 0000CBDD F2/ 4D/ 0F 2C F5 cvttsd2si r14, xmm13 \n"
" \n"
" 0000CBE2 F3/ 4D/ 0F 2A EE cvtsi2ss xmm13, r14 \n"
" 0000CBE7 F2/ 4D/ 0F 2A EE cvtsi2sd xmm13, r14 \n"
" \n"
" \n"
" ; Between: xmm13 and r15 \n"
" 0000CBEC F3/ 45/ 0F 11 6F movss dword ptr [r15 - 4], xmm13 \n"
" FC \n"
" 0000CBF2 F2/ 45/ 0F 11 6F movsd qword ptr [r15 + 4], xmm13 \n"
" 04 \n"
" \n"
" 0000CBF8 F3/ 45/ 0F 10 6F movss xmm13, dword ptr [r15 - 4] \n"
" FC \n"
" 0000CBFE F2/ 45/ 0F 10 6F movsd xmm13, qword ptr [r15 + 4] \n"
" 04 \n"
" 0000CC04 F3/ 4D/ 0F 2A 6F cvtsi2ss xmm13, qword ptr [r15 - 4] \n"
" FC \n"
" 0000CC0A F2/ 45/ 0F 2A 6F cvtsi2sd xmm13, dword ptr [r15 + 4] \n"
" 04 \n"
" \n"
" 0000CC10 F3/ 45/ 0F 2C FD cvttss2si r15d, xmm13 \n"
" 0000CC15 F2/ 45/ 0F 2C FD cvttsd2si r15d, xmm13 \n"
" \n"
" 0000CC1A F3/ 45/ 0F 2A EF cvtsi2ss xmm13, r15d \n"
" 0000CC1F F2/ 45/ 0F 2A EF cvtsi2sd xmm13, r15d \n"
" \n"
" 0000CC24 F3/ 4D/ 0F 2C FD cvttss2si r15, xmm13 \n"
" 0000CC29 F2/ 4D/ 0F 2C FD cvttsd2si r15, xmm13 \n"
" \n"
" 0000CC2E F3/ 4D/ 0F 2A EF cvtsi2ss xmm13, r15 \n"
" 0000CC33 F2/ 4D/ 0F 2A EF cvtsi2sd xmm13, r15 \n"
" \n"
" \n"
" ; Between: xmm14 and rax \n"
" 0000CC38 F3/ 44/ 0F 11 70 movss dword ptr [rax - 4], xmm14 \n"
" FC \n"
" 0000CC3E F2/ 44/ 0F 11 70 movsd qword ptr [rax + 4], xmm14 \n"
" 04 \n"
" \n"
" 0000CC44 F3/ 44/ 0F 10 70 movss xmm14, dword ptr [rax - 4] \n"
" FC \n"
" 0000CC4A F2/ 44/ 0F 10 70 movsd xmm14, qword ptr [rax + 4] \n"
" 04 \n"
" 0000CC50 F3/ 4C/ 0F 2A 70 cvtsi2ss xmm14, qword ptr [rax - 4] \n"
" FC \n"
" 0000CC56 F2/ 44/ 0F 2A 70 cvtsi2sd xmm14, dword ptr [rax + 4] \n"
" 04 \n"
" \n"
" 0000CC5C F3/ 41/ 0F 2C C6 cvttss2si eax, xmm14 \n"
" 0000CC61 F2/ 41/ 0F 2C C6 cvttsd2si eax, xmm14 \n"
" \n"
" 0000CC66 F3/ 44/ 0F 2A F0 cvtsi2ss xmm14, eax \n"
" 0000CC6B F2/ 44/ 0F 2A F0 cvtsi2sd xmm14, eax \n"
" \n"
" 0000CC70 F3/ 49/ 0F 2C C6 cvttss2si rax, xmm14 \n"
" 0000CC75 F2/ 49/ 0F 2C C6 cvttsd2si rax, xmm14 \n"
" \n"
" 0000CC7A F3/ 4C/ 0F 2A F0 cvtsi2ss xmm14, rax \n"
" 0000CC7F F2/ 4C/ 0F 2A F0 cvtsi2sd xmm14, rax \n"
" \n"
" \n"
" ; Between: xmm14 and rcx \n"
" 0000CC84 F3/ 44/ 0F 11 71 movss dword ptr [rcx - 4], xmm14 \n"
" FC \n"
" 0000CC8A F2/ 44/ 0F 11 71 movsd qword ptr [rcx + 4], xmm14 \n"
" 04 \n"
" \n"
" 0000CC90 F3/ 44/ 0F 10 71 movss xmm14, dword ptr [rcx - 4] \n"
" FC \n"
" 0000CC96 F2/ 44/ 0F 10 71 movsd xmm14, qword ptr [rcx + 4] \n"
" 04 \n"
" 0000CC9C F3/ 4C/ 0F 2A 71 cvtsi2ss xmm14, qword ptr [rcx - 4] \n"
" FC \n"
" 0000CCA2 F2/ 44/ 0F 2A 71 cvtsi2sd xmm14, dword ptr [rcx + 4] \n"
" 04 \n"
" \n"
" 0000CCA8 F3/ 41/ 0F 2C CE cvttss2si ecx, xmm14 \n"
" 0000CCAD F2/ 41/ 0F 2C CE cvttsd2si ecx, xmm14 \n"
" \n"
" 0000CCB2 F3/ 44/ 0F 2A F1 cvtsi2ss xmm14, ecx \n"
" 0000CCB7 F2/ 44/ 0F 2A F1 cvtsi2sd xmm14, ecx \n"
" \n"
" 0000CCBC F3/ 49/ 0F 2C CE cvttss2si rcx, xmm14 \n"
" 0000CCC1 F2/ 49/ 0F 2C CE cvttsd2si rcx, xmm14 \n"
" \n"
" 0000CCC6 F3/ 4C/ 0F 2A F1 cvtsi2ss xmm14, rcx \n"
" 0000CCCB F2/ 4C/ 0F 2A F1 cvtsi2sd xmm14, rcx \n"
" \n"
" \n"
" ; Between: xmm14 and rdx \n"
" 0000CCD0 F3/ 44/ 0F 11 72 movss dword ptr [rdx - 4], xmm14 \n"
" FC \n"
" 0000CCD6 F2/ 44/ 0F 11 72 movsd qword ptr [rdx + 4], xmm14 \n"
" 04 \n"
" \n"
" 0000CCDC F3/ 44/ 0F 10 72 movss xmm14, dword ptr [rdx - 4] \n"
" FC \n"
" 0000CCE2 F2/ 44/ 0F 10 72 movsd xmm14, qword ptr [rdx + 4] \n"
" 04 \n"
" 0000CCE8 F3/ 4C/ 0F 2A 72 cvtsi2ss xmm14, qword ptr [rdx - 4] \n"
" FC \n"
" 0000CCEE F2/ 44/ 0F 2A 72 cvtsi2sd xmm14, dword ptr [rdx + 4] \n"
" 04 \n"
" \n"
" 0000CCF4 F3/ 41/ 0F 2C D6 cvttss2si edx, xmm14 \n"
" 0000CCF9 F2/ 41/ 0F 2C D6 cvttsd2si edx, xmm14 \n"
" \n"
" 0000CCFE F3/ 44/ 0F 2A F2 cvtsi2ss xmm14, edx \n"
" 0000CD03 F2/ 44/ 0F 2A F2 cvtsi2sd xmm14, edx \n"
" \n"
" 0000CD08 F3/ 49/ 0F 2C D6 cvttss2si rdx, xmm14 \n"
" 0000CD0D F2/ 49/ 0F 2C D6 cvttsd2si rdx, xmm14 \n"
" \n"
" 0000CD12 F3/ 4C/ 0F 2A F2 cvtsi2ss xmm14, rdx \n"
" 0000CD17 F2/ 4C/ 0F 2A F2 cvtsi2sd xmm14, rdx \n"
" \n"
" \n"
" ; Between: xmm14 and rbx \n"
" 0000CD1C F3/ 44/ 0F 11 73 movss dword ptr [rbx - 4], xmm14 \n"
" FC \n"
" 0000CD22 F2/ 44/ 0F 11 73 movsd qword ptr [rbx + 4], xmm14 \n"
" 04 \n"
" \n"
" 0000CD28 F3/ 44/ 0F 10 73 movss xmm14, dword ptr [rbx - 4] \n"
" FC \n"
" 0000CD2E F2/ 44/ 0F 10 73 movsd xmm14, qword ptr [rbx + 4] \n"
" 04 \n"
" 0000CD34 F3/ 4C/ 0F 2A 73 cvtsi2ss xmm14, qword ptr [rbx - 4] \n"
" FC \n"
" 0000CD3A F2/ 44/ 0F 2A 73 cvtsi2sd xmm14, dword ptr [rbx + 4] \n"
" 04 \n"
" \n"
" 0000CD40 F3/ 41/ 0F 2C DE cvttss2si ebx, xmm14 \n"
" 0000CD45 F2/ 41/ 0F 2C DE cvttsd2si ebx, xmm14 \n"
" \n"
" 0000CD4A F3/ 44/ 0F 2A F3 cvtsi2ss xmm14, ebx \n"
" 0000CD4F F2/ 44/ 0F 2A F3 cvtsi2sd xmm14, ebx \n"
" \n"
" 0000CD54 F3/ 49/ 0F 2C DE cvttss2si rbx, xmm14 \n"
" 0000CD59 F2/ 49/ 0F 2C DE cvttsd2si rbx, xmm14 \n"
" \n"
" 0000CD5E F3/ 4C/ 0F 2A F3 cvtsi2ss xmm14, rbx \n"
" 0000CD63 F2/ 4C/ 0F 2A F3 cvtsi2sd xmm14, rbx \n"
" \n"
" \n"
" ; Between: xmm14 and rsp \n"
" 0000CD68 F3/ 44/ 0F 11 74 movss dword ptr [rsp - 4], xmm14 \n"
" 24 FC \n"
" 0000CD6F F2/ 44/ 0F 11 74 movsd qword ptr [rsp + 4], xmm14 \n"
" 24 04 \n"
" \n"
" 0000CD76 F3/ 44/ 0F 10 74 movss xmm14, dword ptr [rsp - 4] \n"
" 24 FC \n"
" 0000CD7D F2/ 44/ 0F 10 74 movsd xmm14, qword ptr [rsp + 4] \n"
" 24 04 \n"
" 0000CD84 F3/ 4C/ 0F 2A 74 cvtsi2ss xmm14, qword ptr [rsp - 4] \n"
" 24 FC \n"
" 0000CD8B F2/ 44/ 0F 2A 74 cvtsi2sd xmm14, dword ptr [rsp + 4] \n"
" 24 04 \n"
" \n"
" 0000CD92 F3/ 41/ 0F 2C E6 cvttss2si esp, xmm14 \n"
" 0000CD97 F2/ 41/ 0F 2C E6 cvttsd2si esp, xmm14 \n"
" \n"
" 0000CD9C F3/ 44/ 0F 2A F4 cvtsi2ss xmm14, esp \n"
" 0000CDA1 F2/ 44/ 0F 2A F4 cvtsi2sd xmm14, esp \n"
" \n"
" 0000CDA6 F3/ 49/ 0F 2C E6 cvttss2si rsp, xmm14 \n"
" 0000CDAB F2/ 49/ 0F 2C E6 cvttsd2si rsp, xmm14 \n"
" \n"
" 0000CDB0 F3/ 4C/ 0F 2A F4 cvtsi2ss xmm14, rsp \n"
" 0000CDB5 F2/ 4C/ 0F 2A F4 cvtsi2sd xmm14, rsp \n"
" \n"
" \n"
" ; Between: xmm14 and rbp \n"
" 0000CDBA F3/ 44/ 0F 11 75 movss dword ptr [rbp - 4], xmm14 \n"
" FC \n"
" 0000CDC0 F2/ 44/ 0F 11 75 movsd qword ptr [rbp + 4], xmm14 \n"
" 04 \n"
" \n"
" 0000CDC6 F3/ 44/ 0F 10 75 movss xmm14, dword ptr [rbp - 4] \n"
" FC \n"
" 0000CDCC F2/ 44/ 0F 10 75 movsd xmm14, qword ptr [rbp + 4] \n"
" 04 \n"
" 0000CDD2 F3/ 4C/ 0F 2A 75 cvtsi2ss xmm14, qword ptr [rbp - 4] \n"
" FC \n"
" 0000CDD8 F2/ 44/ 0F 2A 75 cvtsi2sd xmm14, dword ptr [rbp + 4] \n"
" 04 \n"
" \n"
" 0000CDDE F3/ 41/ 0F 2C EE cvttss2si ebp, xmm14 \n"
" 0000CDE3 F2/ 41/ 0F 2C EE cvttsd2si ebp, xmm14 \n"
" \n"
" 0000CDE8 F3/ 44/ 0F 2A F5 cvtsi2ss xmm14, ebp \n"
" 0000CDED F2/ 44/ 0F 2A F5 cvtsi2sd xmm14, ebp \n"
" \n"
" 0000CDF2 F3/ 49/ 0F 2C EE cvttss2si rbp, xmm14 \n"
" 0000CDF7 F2/ 49/ 0F 2C EE cvttsd2si rbp, xmm14 \n"
" \n"
" 0000CDFC F3/ 4C/ 0F 2A F5 cvtsi2ss xmm14, rbp \n"
" 0000CE01 F2/ 4C/ 0F 2A F5 cvtsi2sd xmm14, rbp \n"
" \n"
" \n"
" ; Between: xmm14 and rsi \n"
" 0000CE06 F3/ 44/ 0F 11 76 movss dword ptr [rsi - 4], xmm14 \n"
" FC \n"
" 0000CE0C F2/ 44/ 0F 11 76 movsd qword ptr [rsi + 4], xmm14 \n"
" 04 \n"
" \n"
" 0000CE12 F3/ 44/ 0F 10 76 movss xmm14, dword ptr [rsi - 4] \n"
" FC \n"
" 0000CE18 F2/ 44/ 0F 10 76 movsd xmm14, qword ptr [rsi + 4] \n"
" 04 \n"
" 0000CE1E F3/ 4C/ 0F 2A 76 cvtsi2ss xmm14, qword ptr [rsi - 4] \n"
" FC \n"
" 0000CE24 F2/ 44/ 0F 2A 76 cvtsi2sd xmm14, dword ptr [rsi + 4] \n"
" 04 \n"
" \n"
" 0000CE2A F3/ 41/ 0F 2C F6 cvttss2si esi, xmm14 \n"
" 0000CE2F F2/ 41/ 0F 2C F6 cvttsd2si esi, xmm14 \n"
" \n"
" 0000CE34 F3/ 44/ 0F 2A F6 cvtsi2ss xmm14, esi \n"
" 0000CE39 F2/ 44/ 0F 2A F6 cvtsi2sd xmm14, esi \n"
" \n"
" 0000CE3E F3/ 49/ 0F 2C F6 cvttss2si rsi, xmm14 \n"
" 0000CE43 F2/ 49/ 0F 2C F6 cvttsd2si rsi, xmm14 \n"
" \n"
" 0000CE48 F3/ 4C/ 0F 2A F6 cvtsi2ss xmm14, rsi \n"
" 0000CE4D F2/ 4C/ 0F 2A F6 cvtsi2sd xmm14, rsi \n"
" \n"
" \n"
" ; Between: xmm14 and rdi \n"
" 0000CE52 F3/ 44/ 0F 11 77 movss dword ptr [rdi - 4], xmm14 \n"
" FC \n"
" 0000CE58 F2/ 44/ 0F 11 77 movsd qword ptr [rdi + 4], xmm14 \n"
" 04 \n"
" \n"
" 0000CE5E F3/ 44/ 0F 10 77 movss xmm14, dword ptr [rdi - 4] \n"
" FC \n"
" 0000CE64 F2/ 44/ 0F 10 77 movsd xmm14, qword ptr [rdi + 4] \n"
" 04 \n"
" 0000CE6A F3/ 4C/ 0F 2A 77 cvtsi2ss xmm14, qword ptr [rdi - 4] \n"
" FC \n"
" 0000CE70 F2/ 44/ 0F 2A 77 cvtsi2sd xmm14, dword ptr [rdi + 4] \n"
" 04 \n"
" \n"
" 0000CE76 F3/ 41/ 0F 2C FE cvttss2si edi, xmm14 \n"
" 0000CE7B F2/ 41/ 0F 2C FE cvttsd2si edi, xmm14 \n"
" \n"
" 0000CE80 F3/ 44/ 0F 2A F7 cvtsi2ss xmm14, edi \n"
" 0000CE85 F2/ 44/ 0F 2A F7 cvtsi2sd xmm14, edi \n"
" \n"
" 0000CE8A F3/ 49/ 0F 2C FE cvttss2si rdi, xmm14 \n"
" 0000CE8F F2/ 49/ 0F 2C FE cvttsd2si rdi, xmm14 \n"
" \n"
" 0000CE94 F3/ 4C/ 0F 2A F7 cvtsi2ss xmm14, rdi \n"
" 0000CE99 F2/ 4C/ 0F 2A F7 cvtsi2sd xmm14, rdi \n"
" \n"
" \n"
" ; Between: xmm14 and r8 \n"
" 0000CE9E F3/ 45/ 0F 11 70 movss dword ptr [r8 - 4], xmm14 \n"
" FC \n"
" 0000CEA4 F2/ 45/ 0F 11 70 movsd qword ptr [r8 + 4], xmm14 \n"
" 04 \n"
" \n"
" 0000CEAA F3/ 45/ 0F 10 70 movss xmm14, dword ptr [r8 - 4] \n"
" FC \n"
" 0000CEB0 F2/ 45/ 0F 10 70 movsd xmm14, qword ptr [r8 + 4] \n"
" 04 \n"
" 0000CEB6 F3/ 4D/ 0F 2A 70 cvtsi2ss xmm14, qword ptr [r8 - 4] \n"
" FC \n"
" 0000CEBC F2/ 45/ 0F 2A 70 cvtsi2sd xmm14, dword ptr [r8 + 4] \n"
" 04 \n"
" \n"
" 0000CEC2 F3/ 45/ 0F 2C C6 cvttss2si r8d, xmm14 \n"
" 0000CEC7 F2/ 45/ 0F 2C C6 cvttsd2si r8d, xmm14 \n"
" \n"
" 0000CECC F3/ 45/ 0F 2A F0 cvtsi2ss xmm14, r8d \n"
" 0000CED1 F2/ 45/ 0F 2A F0 cvtsi2sd xmm14, r8d \n"
" \n"
" 0000CED6 F3/ 4D/ 0F 2C C6 cvttss2si r8, xmm14 \n"
" 0000CEDB F2/ 4D/ 0F 2C C6 cvttsd2si r8, xmm14 \n"
" \n"
" 0000CEE0 F3/ 4D/ 0F 2A F0 cvtsi2ss xmm14, r8 \n"
" 0000CEE5 F2/ 4D/ 0F 2A F0 cvtsi2sd xmm14, r8 \n"
" \n"
" \n"
" ; Between: xmm14 and r9 \n"
" 0000CEEA F3/ 45/ 0F 11 71 movss dword ptr [r9 - 4], xmm14 \n"
" FC \n"
" 0000CEF0 F2/ 45/ 0F 11 71 movsd qword ptr [r9 + 4], xmm14 \n";
ml64Output +=
" 04 \n"
" \n"
" 0000CEF6 F3/ 45/ 0F 10 71 movss xmm14, dword ptr [r9 - 4] \n"
" FC \n"
" 0000CEFC F2/ 45/ 0F 10 71 movsd xmm14, qword ptr [r9 + 4] \n"
" 04 \n"
" 0000CF02 F3/ 4D/ 0F 2A 71 cvtsi2ss xmm14, qword ptr [r9 - 4] \n"
" FC \n"
" 0000CF08 F2/ 45/ 0F 2A 71 cvtsi2sd xmm14, dword ptr [r9 + 4] \n"
" 04 \n"
" \n"
" 0000CF0E F3/ 45/ 0F 2C CE cvttss2si r9d, xmm14 \n"
" 0000CF13 F2/ 45/ 0F 2C CE cvttsd2si r9d, xmm14 \n"
" \n"
" 0000CF18 F3/ 45/ 0F 2A F1 cvtsi2ss xmm14, r9d \n"
" 0000CF1D F2/ 45/ 0F 2A F1 cvtsi2sd xmm14, r9d \n"
" \n"
" 0000CF22 F3/ 4D/ 0F 2C CE cvttss2si r9, xmm14 \n"
" 0000CF27 F2/ 4D/ 0F 2C CE cvttsd2si r9, xmm14 \n"
" \n"
" 0000CF2C F3/ 4D/ 0F 2A F1 cvtsi2ss xmm14, r9 \n"
" 0000CF31 F2/ 4D/ 0F 2A F1 cvtsi2sd xmm14, r9 \n"
" \n"
" \n"
" ; Between: xmm14 and r10 \n"
" 0000CF36 F3/ 45/ 0F 11 72 movss dword ptr [r10 - 4], xmm14 \n"
" FC \n"
" 0000CF3C F2/ 45/ 0F 11 72 movsd qword ptr [r10 + 4], xmm14 \n"
" 04 \n"
" \n"
" 0000CF42 F3/ 45/ 0F 10 72 movss xmm14, dword ptr [r10 - 4] \n"
" FC \n"
" 0000CF48 F2/ 45/ 0F 10 72 movsd xmm14, qword ptr [r10 + 4] \n"
" 04 \n"
" 0000CF4E F3/ 4D/ 0F 2A 72 cvtsi2ss xmm14, qword ptr [r10 - 4] \n"
" FC \n"
" 0000CF54 F2/ 45/ 0F 2A 72 cvtsi2sd xmm14, dword ptr [r10 + 4] \n"
" 04 \n"
" \n"
" 0000CF5A F3/ 45/ 0F 2C D6 cvttss2si r10d, xmm14 \n"
" 0000CF5F F2/ 45/ 0F 2C D6 cvttsd2si r10d, xmm14 \n"
" \n"
" 0000CF64 F3/ 45/ 0F 2A F2 cvtsi2ss xmm14, r10d \n"
" 0000CF69 F2/ 45/ 0F 2A F2 cvtsi2sd xmm14, r10d \n"
" \n"
" 0000CF6E F3/ 4D/ 0F 2C D6 cvttss2si r10, xmm14 \n"
" 0000CF73 F2/ 4D/ 0F 2C D6 cvttsd2si r10, xmm14 \n"
" \n"
" 0000CF78 F3/ 4D/ 0F 2A F2 cvtsi2ss xmm14, r10 \n"
" 0000CF7D F2/ 4D/ 0F 2A F2 cvtsi2sd xmm14, r10 \n"
" \n"
" \n"
" ; Between: xmm14 and r11 \n"
" 0000CF82 F3/ 45/ 0F 11 73 movss dword ptr [r11 - 4], xmm14 \n"
" FC \n"
" 0000CF88 F2/ 45/ 0F 11 73 movsd qword ptr [r11 + 4], xmm14 \n"
" 04 \n"
" \n"
" 0000CF8E F3/ 45/ 0F 10 73 movss xmm14, dword ptr [r11 - 4] \n"
" FC \n"
" 0000CF94 F2/ 45/ 0F 10 73 movsd xmm14, qword ptr [r11 + 4] \n"
" 04 \n"
" 0000CF9A F3/ 4D/ 0F 2A 73 cvtsi2ss xmm14, qword ptr [r11 - 4] \n"
" FC \n"
" 0000CFA0 F2/ 45/ 0F 2A 73 cvtsi2sd xmm14, dword ptr [r11 + 4] \n"
" 04 \n"
" \n"
" 0000CFA6 F3/ 45/ 0F 2C DE cvttss2si r11d, xmm14 \n"
" 0000CFAB F2/ 45/ 0F 2C DE cvttsd2si r11d, xmm14 \n"
" \n"
" 0000CFB0 F3/ 45/ 0F 2A F3 cvtsi2ss xmm14, r11d \n"
" 0000CFB5 F2/ 45/ 0F 2A F3 cvtsi2sd xmm14, r11d \n"
" \n"
" 0000CFBA F3/ 4D/ 0F 2C DE cvttss2si r11, xmm14 \n"
" 0000CFBF F2/ 4D/ 0F 2C DE cvttsd2si r11, xmm14 \n"
" \n"
" 0000CFC4 F3/ 4D/ 0F 2A F3 cvtsi2ss xmm14, r11 \n"
" 0000CFC9 F2/ 4D/ 0F 2A F3 cvtsi2sd xmm14, r11 \n"
" \n"
" \n"
" ; Between: xmm14 and r12 \n"
" 0000CFCE F3/ 45/ 0F 11 74 movss dword ptr [r12 - 4], xmm14 \n"
" 24 FC \n"
" 0000CFD5 F2/ 45/ 0F 11 74 movsd qword ptr [r12 + 4], xmm14 \n"
" 24 04 \n"
" \n"
" 0000CFDC F3/ 45/ 0F 10 74 movss xmm14, dword ptr [r12 - 4] \n"
" 24 FC \n"
" 0000CFE3 F2/ 45/ 0F 10 74 movsd xmm14, qword ptr [r12 + 4] \n"
" 24 04 \n"
" 0000CFEA F3/ 4D/ 0F 2A 74 cvtsi2ss xmm14, qword ptr [r12 - 4] \n"
" 24 FC \n"
" 0000CFF1 F2/ 45/ 0F 2A 74 cvtsi2sd xmm14, dword ptr [r12 + 4] \n"
" 24 04 \n"
" \n"
" 0000CFF8 F3/ 45/ 0F 2C E6 cvttss2si r12d, xmm14 \n"
" 0000CFFD F2/ 45/ 0F 2C E6 cvttsd2si r12d, xmm14 \n"
" \n"
" 0000D002 F3/ 45/ 0F 2A F4 cvtsi2ss xmm14, r12d \n"
" 0000D007 F2/ 45/ 0F 2A F4 cvtsi2sd xmm14, r12d \n"
" \n"
" 0000D00C F3/ 4D/ 0F 2C E6 cvttss2si r12, xmm14 \n"
" 0000D011 F2/ 4D/ 0F 2C E6 cvttsd2si r12, xmm14 \n"
" \n"
" 0000D016 F3/ 4D/ 0F 2A F4 cvtsi2ss xmm14, r12 \n"
" 0000D01B F2/ 4D/ 0F 2A F4 cvtsi2sd xmm14, r12 \n"
" \n"
" \n"
" ; Between: xmm14 and r13 \n"
" 0000D020 F3/ 45/ 0F 11 75 movss dword ptr [r13 - 4], xmm14 \n"
" FC \n"
" 0000D026 F2/ 45/ 0F 11 75 movsd qword ptr [r13 + 4], xmm14 \n"
" 04 \n"
" \n"
" 0000D02C F3/ 45/ 0F 10 75 movss xmm14, dword ptr [r13 - 4] \n"
" FC \n"
" 0000D032 F2/ 45/ 0F 10 75 movsd xmm14, qword ptr [r13 + 4] \n"
" 04 \n"
" 0000D038 F3/ 4D/ 0F 2A 75 cvtsi2ss xmm14, qword ptr [r13 - 4] \n"
" FC \n"
" 0000D03E F2/ 45/ 0F 2A 75 cvtsi2sd xmm14, dword ptr [r13 + 4] \n"
" 04 \n"
" \n"
" 0000D044 F3/ 45/ 0F 2C EE cvttss2si r13d, xmm14 \n"
" 0000D049 F2/ 45/ 0F 2C EE cvttsd2si r13d, xmm14 \n"
" \n"
" 0000D04E F3/ 45/ 0F 2A F5 cvtsi2ss xmm14, r13d \n"
" 0000D053 F2/ 45/ 0F 2A F5 cvtsi2sd xmm14, r13d \n"
" \n"
" 0000D058 F3/ 4D/ 0F 2C EE cvttss2si r13, xmm14 \n"
" 0000D05D F2/ 4D/ 0F 2C EE cvttsd2si r13, xmm14 \n"
" \n"
" 0000D062 F3/ 4D/ 0F 2A F5 cvtsi2ss xmm14, r13 \n"
" 0000D067 F2/ 4D/ 0F 2A F5 cvtsi2sd xmm14, r13 \n"
" \n"
" \n"
" ; Between: xmm14 and r14 \n"
" 0000D06C F3/ 45/ 0F 11 76 movss dword ptr [r14 - 4], xmm14 \n"
" FC \n"
" 0000D072 F2/ 45/ 0F 11 76 movsd qword ptr [r14 + 4], xmm14 \n"
" 04 \n"
" \n"
" 0000D078 F3/ 45/ 0F 10 76 movss xmm14, dword ptr [r14 - 4] \n"
" FC \n"
" 0000D07E F2/ 45/ 0F 10 76 movsd xmm14, qword ptr [r14 + 4] \n"
" 04 \n"
" 0000D084 F3/ 4D/ 0F 2A 76 cvtsi2ss xmm14, qword ptr [r14 - 4] \n"
" FC \n"
" 0000D08A F2/ 45/ 0F 2A 76 cvtsi2sd xmm14, dword ptr [r14 + 4] \n"
" 04 \n"
" \n"
" 0000D090 F3/ 45/ 0F 2C F6 cvttss2si r14d, xmm14 \n"
" 0000D095 F2/ 45/ 0F 2C F6 cvttsd2si r14d, xmm14 \n"
" \n"
" 0000D09A F3/ 45/ 0F 2A F6 cvtsi2ss xmm14, r14d \n"
" 0000D09F F2/ 45/ 0F 2A F6 cvtsi2sd xmm14, r14d \n"
" \n"
" 0000D0A4 F3/ 4D/ 0F 2C F6 cvttss2si r14, xmm14 \n"
" 0000D0A9 F2/ 4D/ 0F 2C F6 cvttsd2si r14, xmm14 \n"
" \n"
" 0000D0AE F3/ 4D/ 0F 2A F6 cvtsi2ss xmm14, r14 \n"
" 0000D0B3 F2/ 4D/ 0F 2A F6 cvtsi2sd xmm14, r14 \n"
" \n"
" \n"
" ; Between: xmm14 and r15 \n"
" 0000D0B8 F3/ 45/ 0F 11 77 movss dword ptr [r15 - 4], xmm14 \n"
" FC \n"
" 0000D0BE F2/ 45/ 0F 11 77 movsd qword ptr [r15 + 4], xmm14 \n"
" 04 \n"
" \n"
" 0000D0C4 F3/ 45/ 0F 10 77 movss xmm14, dword ptr [r15 - 4] \n"
" FC \n"
" 0000D0CA F2/ 45/ 0F 10 77 movsd xmm14, qword ptr [r15 + 4] \n"
" 04 \n"
" 0000D0D0 F3/ 4D/ 0F 2A 77 cvtsi2ss xmm14, qword ptr [r15 - 4] \n"
" FC \n"
" 0000D0D6 F2/ 45/ 0F 2A 77 cvtsi2sd xmm14, dword ptr [r15 + 4] \n"
" 04 \n"
" \n"
" 0000D0DC F3/ 45/ 0F 2C FE cvttss2si r15d, xmm14 \n"
" 0000D0E1 F2/ 45/ 0F 2C FE cvttsd2si r15d, xmm14 \n"
" \n"
" 0000D0E6 F3/ 45/ 0F 2A F7 cvtsi2ss xmm14, r15d \n"
" 0000D0EB F2/ 45/ 0F 2A F7 cvtsi2sd xmm14, r15d \n"
" \n"
" 0000D0F0 F3/ 4D/ 0F 2C FE cvttss2si r15, xmm14 \n"
" 0000D0F5 F2/ 4D/ 0F 2C FE cvttsd2si r15, xmm14 \n"
" \n"
" 0000D0FA F3/ 4D/ 0F 2A F7 cvtsi2ss xmm14, r15 \n"
" 0000D0FF F2/ 4D/ 0F 2A F7 cvtsi2sd xmm14, r15 \n"
" \n"
" \n"
" ; Between: xmm15 and rax \n"
" 0000D104 F3/ 44/ 0F 11 78 movss dword ptr [rax - 4], xmm15 \n"
" FC \n"
" 0000D10A F2/ 44/ 0F 11 78 movsd qword ptr [rax + 4], xmm15 \n"
" 04 \n"
" \n"
" 0000D110 F3/ 44/ 0F 10 78 movss xmm15, dword ptr [rax - 4] \n"
" FC \n"
" 0000D116 F2/ 44/ 0F 10 78 movsd xmm15, qword ptr [rax + 4] \n"
" 04 \n"
" 0000D11C F3/ 4C/ 0F 2A 78 cvtsi2ss xmm15, qword ptr [rax - 4] \n"
" FC \n"
" 0000D122 F2/ 44/ 0F 2A 78 cvtsi2sd xmm15, dword ptr [rax + 4] \n"
" 04 \n"
" \n"
" 0000D128 F3/ 41/ 0F 2C C7 cvttss2si eax, xmm15 \n"
" 0000D12D F2/ 41/ 0F 2C C7 cvttsd2si eax, xmm15 \n"
" \n"
" 0000D132 F3/ 44/ 0F 2A F8 cvtsi2ss xmm15, eax \n"
" 0000D137 F2/ 44/ 0F 2A F8 cvtsi2sd xmm15, eax \n"
" \n"
" 0000D13C F3/ 49/ 0F 2C C7 cvttss2si rax, xmm15 \n"
" 0000D141 F2/ 49/ 0F 2C C7 cvttsd2si rax, xmm15 \n"
" \n"
" 0000D146 F3/ 4C/ 0F 2A F8 cvtsi2ss xmm15, rax \n"
" 0000D14B F2/ 4C/ 0F 2A F8 cvtsi2sd xmm15, rax \n"
" \n"
" \n"
" ; Between: xmm15 and rcx \n"
" 0000D150 F3/ 44/ 0F 11 79 movss dword ptr [rcx - 4], xmm15 \n"
" FC \n"
" 0000D156 F2/ 44/ 0F 11 79 movsd qword ptr [rcx + 4], xmm15 \n"
" 04 \n"
" \n"
" 0000D15C F3/ 44/ 0F 10 79 movss xmm15, dword ptr [rcx - 4] \n"
" FC \n"
" 0000D162 F2/ 44/ 0F 10 79 movsd xmm15, qword ptr [rcx + 4] \n"
" 04 \n"
" 0000D168 F3/ 4C/ 0F 2A 79 cvtsi2ss xmm15, qword ptr [rcx - 4] \n"
" FC \n"
" 0000D16E F2/ 44/ 0F 2A 79 cvtsi2sd xmm15, dword ptr [rcx + 4] \n"
" 04 \n"
" \n"
" 0000D174 F3/ 41/ 0F 2C CF cvttss2si ecx, xmm15 \n"
" 0000D179 F2/ 41/ 0F 2C CF cvttsd2si ecx, xmm15 \n"
" \n"
" 0000D17E F3/ 44/ 0F 2A F9 cvtsi2ss xmm15, ecx \n"
" 0000D183 F2/ 44/ 0F 2A F9 cvtsi2sd xmm15, ecx \n"
" \n"
" 0000D188 F3/ 49/ 0F 2C CF cvttss2si rcx, xmm15 \n"
" 0000D18D F2/ 49/ 0F 2C CF cvttsd2si rcx, xmm15 \n"
" \n"
" 0000D192 F3/ 4C/ 0F 2A F9 cvtsi2ss xmm15, rcx \n"
" 0000D197 F2/ 4C/ 0F 2A F9 cvtsi2sd xmm15, rcx \n"
" \n"
" \n"
" ; Between: xmm15 and rdx \n"
" 0000D19C F3/ 44/ 0F 11 7A movss dword ptr [rdx - 4], xmm15 \n"
" FC \n"
" 0000D1A2 F2/ 44/ 0F 11 7A movsd qword ptr [rdx + 4], xmm15 \n"
" 04 \n"
" \n"
" 0000D1A8 F3/ 44/ 0F 10 7A movss xmm15, dword ptr [rdx - 4] \n"
" FC \n"
" 0000D1AE F2/ 44/ 0F 10 7A movsd xmm15, qword ptr [rdx + 4] \n"
" 04 \n"
" 0000D1B4 F3/ 4C/ 0F 2A 7A cvtsi2ss xmm15, qword ptr [rdx - 4] \n"
" FC \n"
" 0000D1BA F2/ 44/ 0F 2A 7A cvtsi2sd xmm15, dword ptr [rdx + 4] \n"
" 04 \n"
" \n"
" 0000D1C0 F3/ 41/ 0F 2C D7 cvttss2si edx, xmm15 \n"
" 0000D1C5 F2/ 41/ 0F 2C D7 cvttsd2si edx, xmm15 \n"
" \n"
" 0000D1CA F3/ 44/ 0F 2A FA cvtsi2ss xmm15, edx \n"
" 0000D1CF F2/ 44/ 0F 2A FA cvtsi2sd xmm15, edx \n"
" \n"
" 0000D1D4 F3/ 49/ 0F 2C D7 cvttss2si rdx, xmm15 \n"
" 0000D1D9 F2/ 49/ 0F 2C D7 cvttsd2si rdx, xmm15 \n"
" \n"
" 0000D1DE F3/ 4C/ 0F 2A FA cvtsi2ss xmm15, rdx \n"
" 0000D1E3 F2/ 4C/ 0F 2A FA cvtsi2sd xmm15, rdx \n"
" \n"
" \n"
" ; Between: xmm15 and rbx \n"
" 0000D1E8 F3/ 44/ 0F 11 7B movss dword ptr [rbx - 4], xmm15 \n"
" FC \n"
" 0000D1EE F2/ 44/ 0F 11 7B movsd qword ptr [rbx + 4], xmm15 \n"
" 04 \n"
" \n"
" 0000D1F4 F3/ 44/ 0F 10 7B movss xmm15, dword ptr [rbx - 4] \n"
" FC \n"
" 0000D1FA F2/ 44/ 0F 10 7B movsd xmm15, qword ptr [rbx + 4] \n"
" 04 \n"
" 0000D200 F3/ 4C/ 0F 2A 7B cvtsi2ss xmm15, qword ptr [rbx - 4] \n"
" FC \n"
" 0000D206 F2/ 44/ 0F 2A 7B cvtsi2sd xmm15, dword ptr [rbx + 4] \n"
" 04 \n"
" \n"
" 0000D20C F3/ 41/ 0F 2C DF cvttss2si ebx, xmm15 \n"
" 0000D211 F2/ 41/ 0F 2C DF cvttsd2si ebx, xmm15 \n"
" \n"
" 0000D216 F3/ 44/ 0F 2A FB cvtsi2ss xmm15, ebx \n"
" 0000D21B F2/ 44/ 0F 2A FB cvtsi2sd xmm15, ebx \n"
" \n"
" 0000D220 F3/ 49/ 0F 2C DF cvttss2si rbx, xmm15 \n"
" 0000D225 F2/ 49/ 0F 2C DF cvttsd2si rbx, xmm15 \n"
" \n"
" 0000D22A F3/ 4C/ 0F 2A FB cvtsi2ss xmm15, rbx \n"
" 0000D22F F2/ 4C/ 0F 2A FB cvtsi2sd xmm15, rbx \n"
" \n"
" \n"
" ; Between: xmm15 and rsp \n"
" 0000D234 F3/ 44/ 0F 11 7C movss dword ptr [rsp - 4], xmm15 \n"
" 24 FC \n"
" 0000D23B F2/ 44/ 0F 11 7C movsd qword ptr [rsp + 4], xmm15 \n"
" 24 04 \n"
" \n"
" 0000D242 F3/ 44/ 0F 10 7C movss xmm15, dword ptr [rsp - 4] \n"
" 24 FC \n"
" 0000D249 F2/ 44/ 0F 10 7C movsd xmm15, qword ptr [rsp + 4] \n"
" 24 04 \n"
" 0000D250 F3/ 4C/ 0F 2A 7C cvtsi2ss xmm15, qword ptr [rsp - 4] \n"
" 24 FC \n"
" 0000D257 F2/ 44/ 0F 2A 7C cvtsi2sd xmm15, dword ptr [rsp + 4] \n"
" 24 04 \n"
" \n"
" 0000D25E F3/ 41/ 0F 2C E7 cvttss2si esp, xmm15 \n"
" 0000D263 F2/ 41/ 0F 2C E7 cvttsd2si esp, xmm15 \n"
" \n"
" 0000D268 F3/ 44/ 0F 2A FC cvtsi2ss xmm15, esp \n"
" 0000D26D F2/ 44/ 0F 2A FC cvtsi2sd xmm15, esp \n"
" \n"
" 0000D272 F3/ 49/ 0F 2C E7 cvttss2si rsp, xmm15 \n"
" 0000D277 F2/ 49/ 0F 2C E7 cvttsd2si rsp, xmm15 \n"
" \n"
" 0000D27C F3/ 4C/ 0F 2A FC cvtsi2ss xmm15, rsp \n"
" 0000D281 F2/ 4C/ 0F 2A FC cvtsi2sd xmm15, rsp \n"
" \n"
" \n"
" ; Between: xmm15 and rbp \n"
" 0000D286 F3/ 44/ 0F 11 7D movss dword ptr [rbp - 4], xmm15 \n"
" FC \n"
" 0000D28C F2/ 44/ 0F 11 7D movsd qword ptr [rbp + 4], xmm15 \n"
" 04 \n"
" \n"
" 0000D292 F3/ 44/ 0F 10 7D movss xmm15, dword ptr [rbp - 4] \n"
" FC \n"
" 0000D298 F2/ 44/ 0F 10 7D movsd xmm15, qword ptr [rbp + 4] \n"
" 04 \n"
" 0000D29E F3/ 4C/ 0F 2A 7D cvtsi2ss xmm15, qword ptr [rbp - 4] \n"
" FC \n"
" 0000D2A4 F2/ 44/ 0F 2A 7D cvtsi2sd xmm15, dword ptr [rbp + 4] \n"
" 04 \n"
" \n"
" 0000D2AA F3/ 41/ 0F 2C EF cvttss2si ebp, xmm15 \n"
" 0000D2AF F2/ 41/ 0F 2C EF cvttsd2si ebp, xmm15 \n"
" \n"
" 0000D2B4 F3/ 44/ 0F 2A FD cvtsi2ss xmm15, ebp \n"
" 0000D2B9 F2/ 44/ 0F 2A FD cvtsi2sd xmm15, ebp \n"
" \n"
" 0000D2BE F3/ 49/ 0F 2C EF cvttss2si rbp, xmm15 \n"
" 0000D2C3 F2/ 49/ 0F 2C EF cvttsd2si rbp, xmm15 \n"
" \n"
" 0000D2C8 F3/ 4C/ 0F 2A FD cvtsi2ss xmm15, rbp \n"
" 0000D2CD F2/ 4C/ 0F 2A FD cvtsi2sd xmm15, rbp \n"
" \n"
" \n"
" ; Between: xmm15 and rsi \n"
" 0000D2D2 F3/ 44/ 0F 11 7E movss dword ptr [rsi - 4], xmm15 \n"
" FC \n"
" 0000D2D8 F2/ 44/ 0F 11 7E movsd qword ptr [rsi + 4], xmm15 \n"
" 04 \n"
" \n"
" 0000D2DE F3/ 44/ 0F 10 7E movss xmm15, dword ptr [rsi - 4] \n"
" FC \n"
" 0000D2E4 F2/ 44/ 0F 10 7E movsd xmm15, qword ptr [rsi + 4] \n"
" 04 \n"
" 0000D2EA F3/ 4C/ 0F 2A 7E cvtsi2ss xmm15, qword ptr [rsi - 4] \n"
" FC \n"
" 0000D2F0 F2/ 44/ 0F 2A 7E cvtsi2sd xmm15, dword ptr [rsi + 4] \n"
" 04 \n"
" \n"
" 0000D2F6 F3/ 41/ 0F 2C F7 cvttss2si esi, xmm15 \n"
" 0000D2FB F2/ 41/ 0F 2C F7 cvttsd2si esi, xmm15 \n"
" \n"
" 0000D300 F3/ 44/ 0F 2A FE cvtsi2ss xmm15, esi \n"
" 0000D305 F2/ 44/ 0F 2A FE cvtsi2sd xmm15, esi \n"
" \n"
" 0000D30A F3/ 49/ 0F 2C F7 cvttss2si rsi, xmm15 \n"
" 0000D30F F2/ 49/ 0F 2C F7 cvttsd2si rsi, xmm15 \n"
" \n"
" 0000D314 F3/ 4C/ 0F 2A FE cvtsi2ss xmm15, rsi \n"
" 0000D319 F2/ 4C/ 0F 2A FE cvtsi2sd xmm15, rsi \n"
" \n"
" \n"
" ; Between: xmm15 and rdi \n"
" 0000D31E F3/ 44/ 0F 11 7F movss dword ptr [rdi - 4], xmm15 \n"
" FC \n"
" 0000D324 F2/ 44/ 0F 11 7F movsd qword ptr [rdi + 4], xmm15 \n"
" 04 \n"
" \n"
" 0000D32A F3/ 44/ 0F 10 7F movss xmm15, dword ptr [rdi - 4] \n"
" FC \n"
" 0000D330 F2/ 44/ 0F 10 7F movsd xmm15, qword ptr [rdi + 4] \n"
" 04 \n"
" 0000D336 F3/ 4C/ 0F 2A 7F cvtsi2ss xmm15, qword ptr [rdi - 4] \n"
" FC \n"
" 0000D33C F2/ 44/ 0F 2A 7F cvtsi2sd xmm15, dword ptr [rdi + 4] \n"
" 04 \n"
" \n"
" 0000D342 F3/ 41/ 0F 2C FF cvttss2si edi, xmm15 \n"
" 0000D347 F2/ 41/ 0F 2C FF cvttsd2si edi, xmm15 \n"
" \n"
" 0000D34C F3/ 44/ 0F 2A FF cvtsi2ss xmm15, edi \n"
" 0000D351 F2/ 44/ 0F 2A FF cvtsi2sd xmm15, edi \n"
" \n"
" 0000D356 F3/ 49/ 0F 2C FF cvttss2si rdi, xmm15 \n"
" 0000D35B F2/ 49/ 0F 2C FF cvttsd2si rdi, xmm15 \n"
" \n"
" 0000D360 F3/ 4C/ 0F 2A FF cvtsi2ss xmm15, rdi \n"
" 0000D365 F2/ 4C/ 0F 2A FF cvtsi2sd xmm15, rdi \n"
" \n"
" \n"
" ; Between: xmm15 and r8 \n"
" 0000D36A F3/ 45/ 0F 11 78 movss dword ptr [r8 - 4], xmm15 \n"
" FC \n"
" 0000D370 F2/ 45/ 0F 11 78 movsd qword ptr [r8 + 4], xmm15 \n"
" 04 \n"
" \n"
" 0000D376 F3/ 45/ 0F 10 78 movss xmm15, dword ptr [r8 - 4] \n"
" FC \n"
" 0000D37C F2/ 45/ 0F 10 78 movsd xmm15, qword ptr [r8 + 4] \n"
" 04 \n"
" 0000D382 F3/ 4D/ 0F 2A 78 cvtsi2ss xmm15, qword ptr [r8 - 4] \n"
" FC \n"
" 0000D388 F2/ 45/ 0F 2A 78 cvtsi2sd xmm15, dword ptr [r8 + 4] \n"
" 04 \n"
" \n"
" 0000D38E F3/ 45/ 0F 2C C7 cvttss2si r8d, xmm15 \n"
" 0000D393 F2/ 45/ 0F 2C C7 cvttsd2si r8d, xmm15 \n"
" \n"
" 0000D398 F3/ 45/ 0F 2A F8 cvtsi2ss xmm15, r8d \n"
" 0000D39D F2/ 45/ 0F 2A F8 cvtsi2sd xmm15, r8d \n"
" \n"
" 0000D3A2 F3/ 4D/ 0F 2C C7 cvttss2si r8, xmm15 \n"
" 0000D3A7 F2/ 4D/ 0F 2C C7 cvttsd2si r8, xmm15 \n"
" \n"
" 0000D3AC F3/ 4D/ 0F 2A F8 cvtsi2ss xmm15, r8 \n"
" 0000D3B1 F2/ 4D/ 0F 2A F8 cvtsi2sd xmm15, r8 \n"
" \n"
" \n"
" ; Between: xmm15 and r9 \n"
" 0000D3B6 F3/ 45/ 0F 11 79 movss dword ptr [r9 - 4], xmm15 \n"
" FC \n"
" 0000D3BC F2/ 45/ 0F 11 79 movsd qword ptr [r9 + 4], xmm15 \n"
" 04 \n"
" \n"
" 0000D3C2 F3/ 45/ 0F 10 79 movss xmm15, dword ptr [r9 - 4] \n"
" FC \n"
" 0000D3C8 F2/ 45/ 0F 10 79 movsd xmm15, qword ptr [r9 + 4] \n"
" 04 \n"
" 0000D3CE F3/ 4D/ 0F 2A 79 cvtsi2ss xmm15, qword ptr [r9 - 4] \n"
" FC \n"
" 0000D3D4 F2/ 45/ 0F 2A 79 cvtsi2sd xmm15, dword ptr [r9 + 4] \n"
" 04 \n"
" \n"
" 0000D3DA F3/ 45/ 0F 2C CF cvttss2si r9d, xmm15 \n"
" 0000D3DF F2/ 45/ 0F 2C CF cvttsd2si r9d, xmm15 \n"
" \n"
" 0000D3E4 F3/ 45/ 0F 2A F9 cvtsi2ss xmm15, r9d \n"
" 0000D3E9 F2/ 45/ 0F 2A F9 cvtsi2sd xmm15, r9d \n"
" \n"
" 0000D3EE F3/ 4D/ 0F 2C CF cvttss2si r9, xmm15 \n"
" 0000D3F3 F2/ 4D/ 0F 2C CF cvttsd2si r9, xmm15 \n"
" \n"
" 0000D3F8 F3/ 4D/ 0F 2A F9 cvtsi2ss xmm15, r9 \n"
" 0000D3FD F2/ 4D/ 0F 2A F9 cvtsi2sd xmm15, r9 \n"
" \n"
" \n"
" ; Between: xmm15 and r10 \n"
" 0000D402 F3/ 45/ 0F 11 7A movss dword ptr [r10 - 4], xmm15 \n"
" FC \n"
" 0000D408 F2/ 45/ 0F 11 7A movsd qword ptr [r10 + 4], xmm15 \n"
" 04 \n"
" \n"
" 0000D40E F3/ 45/ 0F 10 7A movss xmm15, dword ptr [r10 - 4] \n"
" FC \n"
" 0000D414 F2/ 45/ 0F 10 7A movsd xmm15, qword ptr [r10 + 4] \n"
" 04 \n"
" 0000D41A F3/ 4D/ 0F 2A 7A cvtsi2ss xmm15, qword ptr [r10 - 4] \n"
" FC \n"
" 0000D420 F2/ 45/ 0F 2A 7A cvtsi2sd xmm15, dword ptr [r10 + 4] \n"
" 04 \n"
" \n"
" 0000D426 F3/ 45/ 0F 2C D7 cvttss2si r10d, xmm15 \n"
" 0000D42B F2/ 45/ 0F 2C D7 cvttsd2si r10d, xmm15 \n"
" \n"
" 0000D430 F3/ 45/ 0F 2A FA cvtsi2ss xmm15, r10d \n"
" 0000D435 F2/ 45/ 0F 2A FA cvtsi2sd xmm15, r10d \n"
" \n"
" 0000D43A F3/ 4D/ 0F 2C D7 cvttss2si r10, xmm15 \n"
" 0000D43F F2/ 4D/ 0F 2C D7 cvttsd2si r10, xmm15 \n"
" \n"
" 0000D444 F3/ 4D/ 0F 2A FA cvtsi2ss xmm15, r10 \n"
" 0000D449 F2/ 4D/ 0F 2A FA cvtsi2sd xmm15, r10 \n"
" \n"
" \n"
" ; Between: xmm15 and r11 \n"
" 0000D44E F3/ 45/ 0F 11 7B movss dword ptr [r11 - 4], xmm15 \n"
" FC \n"
" 0000D454 F2/ 45/ 0F 11 7B movsd qword ptr [r11 + 4], xmm15 \n"
" 04 \n"
" \n"
" 0000D45A F3/ 45/ 0F 10 7B movss xmm15, dword ptr [r11 - 4] \n"
" FC \n"
" 0000D460 F2/ 45/ 0F 10 7B movsd xmm15, qword ptr [r11 + 4] \n"
" 04 \n"
" 0000D466 F3/ 4D/ 0F 2A 7B cvtsi2ss xmm15, qword ptr [r11 - 4] \n"
" FC \n"
" 0000D46C F2/ 45/ 0F 2A 7B cvtsi2sd xmm15, dword ptr [r11 + 4] \n"
" 04 \n"
" \n"
" 0000D472 F3/ 45/ 0F 2C DF cvttss2si r11d, xmm15 \n"
" 0000D477 F2/ 45/ 0F 2C DF cvttsd2si r11d, xmm15 \n"
" \n"
" 0000D47C F3/ 45/ 0F 2A FB cvtsi2ss xmm15, r11d \n"
" 0000D481 F2/ 45/ 0F 2A FB cvtsi2sd xmm15, r11d \n"
" \n"
" 0000D486 F3/ 4D/ 0F 2C DF cvttss2si r11, xmm15 \n"
" 0000D48B F2/ 4D/ 0F 2C DF cvttsd2si r11, xmm15 \n"
" \n"
" 0000D490 F3/ 4D/ 0F 2A FB cvtsi2ss xmm15, r11 \n"
" 0000D495 F2/ 4D/ 0F 2A FB cvtsi2sd xmm15, r11 \n"
" \n"
" \n"
" ; Between: xmm15 and r12 \n"
" 0000D49A F3/ 45/ 0F 11 7C movss dword ptr [r12 - 4], xmm15 \n"
" 24 FC \n"
" 0000D4A1 F2/ 45/ 0F 11 7C movsd qword ptr [r12 + 4], xmm15 \n"
" 24 04 \n"
" \n"
" 0000D4A8 F3/ 45/ 0F 10 7C movss xmm15, dword ptr [r12 - 4] \n"
" 24 FC \n"
" 0000D4AF F2/ 45/ 0F 10 7C movsd xmm15, qword ptr [r12 + 4] \n"
" 24 04 \n"
" 0000D4B6 F3/ 4D/ 0F 2A 7C cvtsi2ss xmm15, qword ptr [r12 - 4] \n"
" 24 FC \n"
" 0000D4BD F2/ 45/ 0F 2A 7C cvtsi2sd xmm15, dword ptr [r12 + 4] \n"
" 24 04 \n"
" \n"
" 0000D4C4 F3/ 45/ 0F 2C E7 cvttss2si r12d, xmm15 \n"
" 0000D4C9 F2/ 45/ 0F 2C E7 cvttsd2si r12d, xmm15 \n"
" \n"
" 0000D4CE F3/ 45/ 0F 2A FC cvtsi2ss xmm15, r12d \n"
" 0000D4D3 F2/ 45/ 0F 2A FC cvtsi2sd xmm15, r12d \n"
" \n"
" 0000D4D8 F3/ 4D/ 0F 2C E7 cvttss2si r12, xmm15 \n";
ml64Output +=
" 0000D4DD F2/ 4D/ 0F 2C E7 cvttsd2si r12, xmm15 \n"
" \n"
" 0000D4E2 F3/ 4D/ 0F 2A FC cvtsi2ss xmm15, r12 \n"
" 0000D4E7 F2/ 4D/ 0F 2A FC cvtsi2sd xmm15, r12 \n"
" \n"
" \n"
" ; Between: xmm15 and r13 \n"
" 0000D4EC F3/ 45/ 0F 11 7D movss dword ptr [r13 - 4], xmm15 \n"
" FC \n"
" 0000D4F2 F2/ 45/ 0F 11 7D movsd qword ptr [r13 + 4], xmm15 \n"
" 04 \n"
" \n"
" 0000D4F8 F3/ 45/ 0F 10 7D movss xmm15, dword ptr [r13 - 4] \n"
" FC \n"
" 0000D4FE F2/ 45/ 0F 10 7D movsd xmm15, qword ptr [r13 + 4] \n"
" 04 \n"
" 0000D504 F3/ 4D/ 0F 2A 7D cvtsi2ss xmm15, qword ptr [r13 - 4] \n"
" FC \n"
" 0000D50A F2/ 45/ 0F 2A 7D cvtsi2sd xmm15, dword ptr [r13 + 4] \n"
" 04 \n"
" \n"
" 0000D510 F3/ 45/ 0F 2C EF cvttss2si r13d, xmm15 \n"
" 0000D515 F2/ 45/ 0F 2C EF cvttsd2si r13d, xmm15 \n"
" \n"
" 0000D51A F3/ 45/ 0F 2A FD cvtsi2ss xmm15, r13d \n"
" 0000D51F F2/ 45/ 0F 2A FD cvtsi2sd xmm15, r13d \n"
" \n"
" 0000D524 F3/ 4D/ 0F 2C EF cvttss2si r13, xmm15 \n"
" 0000D529 F2/ 4D/ 0F 2C EF cvttsd2si r13, xmm15 \n"
" \n"
" 0000D52E F3/ 4D/ 0F 2A FD cvtsi2ss xmm15, r13 \n"
" 0000D533 F2/ 4D/ 0F 2A FD cvtsi2sd xmm15, r13 \n"
" \n"
" \n"
" ; Between: xmm15 and r14 \n"
" 0000D538 F3/ 45/ 0F 11 7E movss dword ptr [r14 - 4], xmm15 \n"
" FC \n"
" 0000D53E F2/ 45/ 0F 11 7E movsd qword ptr [r14 + 4], xmm15 \n"
" 04 \n"
" \n"
" 0000D544 F3/ 45/ 0F 10 7E movss xmm15, dword ptr [r14 - 4] \n"
" FC \n"
" 0000D54A F2/ 45/ 0F 10 7E movsd xmm15, qword ptr [r14 + 4] \n"
" 04 \n"
" 0000D550 F3/ 4D/ 0F 2A 7E cvtsi2ss xmm15, qword ptr [r14 - 4] \n"
" FC \n"
" 0000D556 F2/ 45/ 0F 2A 7E cvtsi2sd xmm15, dword ptr [r14 + 4] \n"
" 04 \n"
" \n"
" 0000D55C F3/ 45/ 0F 2C F7 cvttss2si r14d, xmm15 \n"
" 0000D561 F2/ 45/ 0F 2C F7 cvttsd2si r14d, xmm15 \n"
" \n"
" 0000D566 F3/ 45/ 0F 2A FE cvtsi2ss xmm15, r14d \n"
" 0000D56B F2/ 45/ 0F 2A FE cvtsi2sd xmm15, r14d \n"
" \n"
" 0000D570 F3/ 4D/ 0F 2C F7 cvttss2si r14, xmm15 \n"
" 0000D575 F2/ 4D/ 0F 2C F7 cvttsd2si r14, xmm15 \n"
" \n"
" 0000D57A F3/ 4D/ 0F 2A FE cvtsi2ss xmm15, r14 \n"
" 0000D57F F2/ 4D/ 0F 2A FE cvtsi2sd xmm15, r14 \n"
" \n"
" \n"
" ; Between: xmm15 and r15 \n"
" 0000D584 F3/ 45/ 0F 11 7F movss dword ptr [r15 - 4], xmm15 \n"
" FC \n"
" 0000D58A F2/ 45/ 0F 11 7F movsd qword ptr [r15 + 4], xmm15 \n"
" 04 \n"
" \n"
" 0000D590 F3/ 45/ 0F 10 7F movss xmm15, dword ptr [r15 - 4] \n"
" FC \n"
" 0000D596 F2/ 45/ 0F 10 7F movsd xmm15, qword ptr [r15 + 4] \n"
" 04 \n"
" 0000D59C F3/ 4D/ 0F 2A 7F cvtsi2ss xmm15, qword ptr [r15 - 4] \n"
" FC \n"
" 0000D5A2 F2/ 45/ 0F 2A 7F cvtsi2sd xmm15, dword ptr [r15 + 4] \n"
" 04 \n"
" \n"
" 0000D5A8 F3/ 45/ 0F 2C FF cvttss2si r15d, xmm15 \n"
" 0000D5AD F2/ 45/ 0F 2C FF cvttsd2si r15d, xmm15 \n"
" \n"
" 0000D5B2 F3/ 45/ 0F 2A FF cvtsi2ss xmm15, r15d \n"
" 0000D5B7 F2/ 45/ 0F 2A FF cvtsi2sd xmm15, r15d \n"
" \n"
" 0000D5BC F3/ 4D/ 0F 2C FF cvttss2si r15, xmm15 \n"
" 0000D5C1 F2/ 4D/ 0F 2C FF cvttsd2si r15, xmm15 \n"
" \n"
" 0000D5C6 F3/ 4D/ 0F 2A FF cvtsi2ss xmm15, r15 \n"
" 0000D5CB F2/ 4D/ 0F 2A FF cvtsi2sd xmm15, r15 \n"
"";
ML64Verifier v(ml64Output.c_str(), start);
}
TEST_CASES_END
}
}
``` | /content/code_sandbox/test/CodeGen/InstructionEncodingTest.cpp | c++ | 2016-04-09T23:53:19 | 2024-06-29T07:05:56 | NativeJIT | BitFunnel/NativeJIT | 1,133 | 727,556 |
```shell
#!/usr/bin/env bash
set -e
# build dev debug apk
./gradlew --daemon installProductionRelease
# start main activity
adb shell am start -n "com.blankj.androidutilcode/com.blankj.main.pkg.MainActivity" -a android.intent.action.MAIN -c android.intent.category.LAUNCHER
``` | /content/code_sandbox/script/runProductionRelease.sh | shell | 2016-07-30T18:18:32 | 2024-08-16T01:37:59 | AndroidUtilCode | Blankj/AndroidUtilCode | 33,178 | 65 |
```batchfile
@rem
@rem
@rem
@rem path_to_url
@rem
@rem Unless required by applicable law or agreed to in writing, software
@rem WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
@rem
@if "%DEBUG%" == "" @echo off
@rem ##########################################################################
@rem
@rem Gradle startup script for Windows
@rem
@rem ##########################################################################
@rem Set local scope for the variables with windows NT shell
if "%OS%"=="Windows_NT" setlocal
set DIRNAME=%~dp0
if "%DIRNAME%" == "" set DIRNAME=.
set APP_BASE_NAME=%~n0
set APP_HOME=%DIRNAME%
@rem Add default JVM options here. You can also use JAVA_OPTS and GRADLE_OPTS to pass JVM options to this script.
set DEFAULT_JVM_OPTS="-Xmx64m" "-Xms64m"
@rem Find java.exe
if defined JAVA_HOME goto findJavaFromJavaHome
set JAVA_EXE=java.exe
%JAVA_EXE% -version >NUL 2>&1
if "%ERRORLEVEL%" == "0" goto init
echo.
echo ERROR: JAVA_HOME is not set and no 'java' command could be found in your PATH.
echo.
echo Please set the JAVA_HOME variable in your environment to match the
echo location of your Java installation.
goto fail
:findJavaFromJavaHome
set JAVA_HOME=%JAVA_HOME:"=%
set JAVA_EXE=%JAVA_HOME%/bin/java.exe
if exist "%JAVA_EXE%" goto init
echo.
echo ERROR: JAVA_HOME is set to an invalid directory: %JAVA_HOME%
echo.
echo Please set the JAVA_HOME variable in your environment to match the
echo location of your Java installation.
goto fail
:init
@rem Get command-line arguments, handling Windows variants
if not "%OS%" == "Windows_NT" goto win9xME_args
:win9xME_args
@rem Slurp the command line arguments.
set CMD_LINE_ARGS=
set _SKIP=2
:win9xME_args_slurp
if "x%~1" == "x" goto execute
set CMD_LINE_ARGS=%*
:execute
@rem Setup the command line
set CLASSPATH=%APP_HOME%\gradle\wrapper\gradle-wrapper.jar
@rem Execute Gradle
"%JAVA_EXE%" %DEFAULT_JVM_OPTS% %JAVA_OPTS% %GRADLE_OPTS% "-Dorg.gradle.appname=%APP_BASE_NAME%" -classpath "%CLASSPATH%" org.gradle.wrapper.GradleWrapperMain %CMD_LINE_ARGS%
:end
@rem End local scope for the variables with windows NT shell
if "%ERRORLEVEL%"=="0" goto mainEnd
:fail
rem Set variable GRADLE_EXIT_CONSOLE if you need the _script_ return code instead of
rem the _cmd.exe /c_ return code!
if not "" == "%GRADLE_EXIT_CONSOLE%" exit 1
exit /b 1
:mainEnd
if "%OS%"=="Windows_NT" endlocal
:omega
``` | /content/code_sandbox/gradlew.bat | batchfile | 2016-07-30T18:18:32 | 2024-08-16T01:37:59 | AndroidUtilCode | Blankj/AndroidUtilCode | 33,178 | 647 |
```java
package com.blankj.subutil.util;
import android.app.PendingIntent;
import android.content.Context;
import android.content.Intent;
import android.os.Build;
import android.os.PowerManager;
import android.telephony.SmsManager;
import android.telephony.TelephonyManager;
import android.text.TextUtils;
import android.util.Log;
import com.blankj.utilcode.util.IntentUtils;
import com.blankj.utilcode.util.ShellUtils;
import com.blankj.utilcode.util.Utils;
import java.io.File;
import java.lang.reflect.Method;
import java.util.List;
import androidx.annotation.RequiresPermission;
import static android.Manifest.permission.MODIFY_PHONE_STATE;
import static android.Manifest.permission.SEND_SMS;
/**
* <pre>
* author: Blankj
* blog : path_to_url
* time : 2019/06/29
* desc :
* </pre>
*/
public class DangerousUtils {
private DangerousUtils() {
throw new UnsupportedOperationException("u can't instantiate me...");
}
///////////////////////////////////////////////////////////////////////////
// AppUtils
///////////////////////////////////////////////////////////////////////////
/**
* Install the app silently.
* <p>Without root permission must hold
* {@code android:sharedUserId="android.uid.shell"} and
* {@code <uses-permission android:name="android.permission.INSTALL_PACKAGES" />}</p>
*
* @param filePath The path of file.
* @return {@code true}: success<br>{@code false}: fail
*/
public static boolean installAppSilent(final String filePath) {
return installAppSilent(getFileByPath(filePath), null);
}
/**
* Install the app silently.
* <p>Without root permission must hold
* {@code android:sharedUserId="android.uid.shell"} and
* {@code <uses-permission android:name="android.permission.INSTALL_PACKAGES" />}</p>
*
* @param file The file.
* @return {@code true}: success<br>{@code false}: fail
*/
public static boolean installAppSilent(final File file) {
return installAppSilent(file, null);
}
/**
* Install the app silently.
* <p>Without root permission must hold
* {@code android:sharedUserId="android.uid.shell"} and
* {@code <uses-permission android:name="android.permission.INSTALL_PACKAGES" />}</p>
*
* @param filePath The path of file.
* @param params The params of installation(e.g.,<code>-r</code>, <code>-s</code>).
* @return {@code true}: success<br>{@code false}: fail
*/
public static boolean installAppSilent(final String filePath, final String params) {
return installAppSilent(getFileByPath(filePath), params);
}
/**
* Install the app silently.
* <p>Without root permission must hold
* {@code android:sharedUserId="android.uid.shell"} and
* {@code <uses-permission android:name="android.permission.INSTALL_PACKAGES" />}</p>
*
* @param file The file.
* @param params The params of installation(e.g.,<code>-r</code>, <code>-s</code>).
* @return {@code true}: success<br>{@code false}: fail
*/
public static boolean installAppSilent(final File file, final String params) {
return installAppSilent(file, params, isDeviceRooted());
}
/**
* Install the app silently.
* <p>Without root permission must hold
* {@code android:sharedUserId="android.uid.shell"} and
* {@code <uses-permission android:name="android.permission.INSTALL_PACKAGES" />}</p>
*
* @param file The file.
* @param params The params of installation(e.g.,<code>-r</code>, <code>-s</code>).
* @param isRooted True to use root, false otherwise.
* @return {@code true}: success<br>{@code false}: fail
*/
public static boolean installAppSilent(final File file,
final String params,
final boolean isRooted) {
if (!isFileExists(file)) return false;
String filePath = '"' + file.getAbsolutePath() + '"';
String command = "LD_LIBRARY_PATH=/vendor/lib*:/system/lib* pm install " +
(params == null ? "" : params + " ")
+ filePath;
ShellUtils.CommandResult commandResult = ShellUtils.execCmd(command, isRooted);
if (commandResult.successMsg != null
&& commandResult.successMsg.toLowerCase().contains("success")) {
return true;
} else {
Log.e("AppUtils", "installAppSilent successMsg: " + commandResult.successMsg +
", errorMsg: " + commandResult.errorMsg);
return false;
}
}
/**
* Uninstall the app silently.
* <p>Without root permission must hold
* {@code android:sharedUserId="android.uid.shell"} and
* {@code <uses-permission android:name="android.permission.DELETE_PACKAGES" />}</p>
*
* @param packageName The name of the package.
* @return {@code true}: success<br>{@code false}: fail
*/
public static boolean uninstallAppSilent(final String packageName) {
return uninstallAppSilent(packageName, false);
}
/**
* Uninstall the app silently.
* <p>Without root permission must hold
* {@code android:sharedUserId="android.uid.shell"} and
* {@code <uses-permission android:name="android.permission.DELETE_PACKAGES" />}</p>
*
* @param packageName The name of the package.
* @param isKeepData Is keep the data.
* @return {@code true}: success<br>{@code false}: fail
*/
public static boolean uninstallAppSilent(final String packageName, final boolean isKeepData) {
return uninstallAppSilent(packageName, isKeepData, isDeviceRooted());
}
/**
* Uninstall the app silently.
* <p>Without root permission must hold
* {@code android:sharedUserId="android.uid.shell"} and
* {@code <uses-permission android:name="android.permission.DELETE_PACKAGES" />}</p>
*
* @param packageName The name of the package.
* @param isKeepData Is keep the data.
* @param isRooted True to use root, false otherwise.
* @return {@code true}: success<br>{@code false}: fail
*/
public static boolean uninstallAppSilent(final String packageName,
final boolean isKeepData,
final boolean isRooted) {
if (isSpace(packageName)) return false;
String command = "LD_LIBRARY_PATH=/vendor/lib*:/system/lib* pm uninstall "
+ (isKeepData ? "-k " : "")
+ packageName;
ShellUtils.CommandResult commandResult = ShellUtils.execCmd(command, isRooted);
if (commandResult.successMsg != null
&& commandResult.successMsg.toLowerCase().contains("success")) {
return true;
} else {
Log.e("AppUtils", "uninstallAppSilent successMsg: " + commandResult.successMsg +
", errorMsg: " + commandResult.errorMsg);
return false;
}
}
private static boolean isFileExists(final File file) {
return file != null && file.exists();
}
private static File getFileByPath(final String filePath) {
return isSpace(filePath) ? null : new File(filePath);
}
private static boolean isSpace(final String s) {
if (s == null) return true;
for (int i = 0, len = s.length(); i < len; ++i) {
if (!Character.isWhitespace(s.charAt(i))) {
return false;
}
}
return true;
}
private static boolean isDeviceRooted() {
String su = "su";
String[] locations = {"/system/bin/", "/system/xbin/", "/sbin/", "/system/sd/xbin/",
"/system/bin/failsafe/", "/data/local/xbin/", "/data/local/bin/", "/data/local/",
"/system/sbin/", "/usr/bin/", "/vendor/bin/"};
for (String location : locations) {
if (new File(location + su).exists()) {
return true;
}
}
return false;
}
///////////////////////////////////////////////////////////////////////////
// DeviceUtils
///////////////////////////////////////////////////////////////////////////
/**
* Shutdown the device
* <p>Requires root permission
* or hold {@code android:sharedUserId="android.uid.system"},
* {@code <uses-permission android:name="android.permission.SHUTDOWN" />}
* in manifest.</p>
*
* @return {@code true}: success<br>{@code false}: fail
*/
public static boolean shutdown() {
try {
ShellUtils.CommandResult result = ShellUtils.execCmd("reboot -p", true);
if (result.result == 0) return true;
Utils.getApp().startActivity(IntentUtils.getShutdownIntent());
return true;
} catch (Exception e) {
return false;
}
}
/**
* Reboot the device.
* <p>Requires root permission
* or hold {@code android:sharedUserId="android.uid.system"} in manifest.</p>
*
* @return {@code true}: success<br>{@code false}: fail
*/
public static boolean reboot() {
try {
ShellUtils.CommandResult result = ShellUtils.execCmd("reboot", true);
if (result.result == 0) return true;
Intent intent = new Intent(Intent.ACTION_REBOOT);
intent.putExtra("nowait", 1);
intent.putExtra("interval", 1);
intent.putExtra("window", 0);
Utils.getApp().sendBroadcast(intent);
return true;
} catch (Exception e) {
return false;
}
}
/**
* Reboot the device.
* <p>Requires root permission
* or hold {@code android:sharedUserId="android.uid.system"},
* {@code <uses-permission android:name="android.permission.REBOOT" />}</p>
*
* @param reason code to pass to the kernel (e.g., "recovery") to
* request special boot modes, or null.
* @return {@code true}: success<br>{@code false}: fail
*/
public static boolean reboot(final String reason) {
try {
PowerManager pm = (PowerManager) Utils.getApp().getSystemService(Context.POWER_SERVICE);
pm.reboot(reason);
return true;
} catch (Exception e) {
return false;
}
}
/**
* Reboot the device to recovery.
* <p>Requires root permission.</p>
*
* @return {@code true}: success<br>{@code false}: fail
*/
public static boolean reboot2Recovery() {
ShellUtils.CommandResult result = ShellUtils.execCmd("reboot recovery", true);
return result.result == 0;
}
/**
* Reboot the device to bootloader.
* <p>Requires root permission.</p>
*
* @return {@code true}: success<br>{@code false}: fail
*/
public static boolean reboot2Bootloader() {
ShellUtils.CommandResult result = ShellUtils.execCmd("reboot bootloader", true);
return result.result == 0;
}
/**
* Enable or disable mobile data.
* <p>Must hold {@code android:sharedUserId="android.uid.system"},
* {@code <uses-permission android:name="android.permission.MODIFY_PHONE_STATE" />}</p>
*
* @param enabled True to enabled, false otherwise.
* @return {@code true}: success<br>{@code false}: fail
*/
@RequiresPermission(MODIFY_PHONE_STATE)
public static boolean setMobileDataEnabled(final boolean enabled) {
try {
TelephonyManager tm =
(TelephonyManager) Utils.getApp().getSystemService(Context.TELEPHONY_SERVICE);
if (tm == null) return false;
if (Build.VERSION.SDK_INT >= Build.VERSION_CODES.O) {
tm.setDataEnabled(enabled);
return true;
}
Method setDataEnabledMethod =
tm.getClass().getDeclaredMethod("setDataEnabled", boolean.class);
setDataEnabledMethod.invoke(tm, enabled);
return true;
} catch (Exception e) {
e.printStackTrace();
}
return false;
}
/**
* Send sms silently.
* <p>Must hold {@code <uses-permission android:name="android.permission.SEND_SMS" />}</p>
*
* @param phoneNumber The phone number.
* @param content The content.
*/
@RequiresPermission(SEND_SMS)
public static void sendSmsSilent(final String phoneNumber, final String content) {
if (TextUtils.isEmpty(content)) return;
PendingIntent sentIntent = PendingIntent.getBroadcast(Utils.getApp(), 0, new Intent("send"), 0);
SmsManager smsManager = SmsManager.getDefault();
if (content.length() >= 70) {
List<String> ms = smsManager.divideMessage(content);
for (String str : ms) {
smsManager.sendTextMessage(phoneNumber, null, str, sentIntent, null);
}
} else {
smsManager.sendTextMessage(phoneNumber, null, content, sentIntent, null);
}
}
}
``` | /content/code_sandbox/lib/subutil/src/main/java/com/blankj/subutil/util/DangerousUtils.java | java | 2016-07-30T18:18:32 | 2024-08-16T01:37:59 | AndroidUtilCode | Blankj/AndroidUtilCode | 33,178 | 2,873 |
```java
package com.blankj.subutil.util;
import android.annotation.SuppressLint;
import android.app.Application;
import android.content.ContentProvider;
import android.content.ContentValues;
import android.content.Context;
import android.database.Cursor;
import android.net.Uri;
import androidx.annotation.NonNull;
import androidx.annotation.Nullable;
import java.lang.reflect.InvocationTargetException;
/**
* <pre>
* author:
* ___ ___ ___ ___
* _____ / /\ /__/\ /__/| / /\
* / /::\ / /::\ \ \:\ | |:| / /:/
* / /:/\:\ ___ ___ / /:/\:\ \ \:\ | |:| /__/::\
* / /:/~/::\ /__/\ / /\ / /:/~/::\ _____\__\:\ __| |:| \__\/\:\
* /__/:/ /:/\:| \ \:\ / /:/ /__/:/ /:/\:\ /__/::::::::\ /__/\_|:|____ \ \:\
* \ \:\/:/~/:/ \ \:\ /:/ \ \:\/:/__\/ \ \:\~~\~~\/ \ \:\/:::::/ \__\:\
* \ \::/ /:/ \ \:\/:/ \ \::/ \ \:\ ~~~ \ \::/~~~~ / /:/
* \ \:\/:/ \ \::/ \ \:\ \ \:\ \ \:\ /__/:/
* \ \::/ \__\/ \ \:\ \ \:\ \ \:\ \__\/
* \__\/ \__\/ \__\/ \__\/
* blog : path_to_url
* time : 16/12/08
* desc : utils about initialization
* </pre>
*/
public final class Utils {
@SuppressLint("StaticFieldLeak")
private static Application sApplication;
private Utils() {
throw new UnsupportedOperationException("u can't instantiate me...");
}
/**
* Init utils.
* <p>Init it in the class of Application.</p>
*
* @param context context
*/
public static void init(final Context context) {
if (context == null) {
init(getApplicationByReflect());
return;
}
init((Application) context.getApplicationContext());
}
/**
* Init utils.
* <p>Init it in the class of Application.</p>
*
* @param app application
*/
public static void init(final Application app) {
if (sApplication == null) {
if (app == null) {
Utils.sApplication = getApplicationByReflect();
} else {
Utils.sApplication = app;
}
}
}
/**
* Return the context of Application object.
*
* @return the context of Application object
*/
public static Application getApp() {
if (sApplication != null) return sApplication;
return getApplicationByReflect();
}
private static Application getApplicationByReflect() {
try {
@SuppressLint("PrivateApi")
Class<?> activityThread = Class.forName("android.app.ActivityThread");
Object at = activityThread.getMethod("currentActivityThread").invoke(null);
Object app = activityThread.getMethod("getApplication").invoke(at);
if (app == null) {
throw new NullPointerException("u should init first");
}
init((Application) app);
return sApplication;
} catch (NoSuchMethodException e) {
e.printStackTrace();
} catch (IllegalAccessException e) {
e.printStackTrace();
} catch (InvocationTargetException e) {
e.printStackTrace();
} catch (ClassNotFoundException e) {
e.printStackTrace();
}
throw new NullPointerException("u should init first");
}
public static final class ContentProvider4SubUtil extends ContentProvider {
@Override
public boolean onCreate() {
Utils.init(getContext());
return true;
}
@Nullable
@Override
public Cursor query(@NonNull Uri uri, @Nullable String[] projection, @Nullable String selection, @Nullable String[] selectionArgs, @Nullable String sortOrder) {
return null;
}
@Nullable
@Override
public String getType(@NonNull Uri uri) {
return null;
}
@Nullable
@Override
public Uri insert(@NonNull Uri uri, @Nullable ContentValues values) {
return null;
}
@Override
public int delete(@NonNull Uri uri, @Nullable String selection, @Nullable String[] selectionArgs) {
return 0;
}
@Override
public int update(@NonNull Uri uri, @Nullable ContentValues values, @Nullable String selection, @Nullable String[] selectionArgs) {
return 0;
}
}
}
``` | /content/code_sandbox/lib/subutil/src/main/java/com/blankj/subutil/util/Utils.java | java | 2016-07-30T18:18:32 | 2024-08-16T01:37:59 | AndroidUtilCode | Blankj/AndroidUtilCode | 33,178 | 1,074 |
```gradle
import groovy.json.JsonSlurper
/**
* module_config.json appConfig pkgConfig include
* apply
*/
def json = new JsonSlurper().parse(file("./module_config.json"))
for (def module in json.moduleConfig) {
String moduleName = module.name
if (moduleName == "feature_mock") {
if (json.pkgConfig.isEmpty()) {
module.isApply = false
}
} else if (moduleName.endsWith("_app")) {
if (!json.appConfig.contains(moduleName)) {
module.isApply = false
}
} else if (moduleName.endsWith("_pkg")) {
if (!json.pkgConfig.isEmpty()) {
if (!json.pkgConfig.contains(moduleName)) {
module.isApply = false
}
}
}
if (module.useLocal && module.isApply) {
include moduleName
project(":$moduleName").projectDir = file(module.localPath)
}
}
def ls = System.getProperty("line.separator")
List<String> modules = []
for (def module in json.moduleConfig) {
String name = module.name
boolean isApply = module.isApply
boolean useLocal = module.useLocal
String localPath = module.localPath
String remotePath = module.remotePath
if (localPath != null) localPath = "\"$localPath\""
if (remotePath != null) remotePath = "\"$remotePath\""
modules.add(String.format("%-12s%-27s: new ModuleConfig(isApply: %-5s, useLocal: %-5s, localPath: $localPath%s),",
"", name, isApply, useLocal, remotePath == null ? "" : ", remotePath: $remotePath"))
}
def configFile = file('./buildSrc/src/main/groovy/Config.groovy')
def lines = configFile.readLines("utf8")
def configContent = new StringBuilder()
boolean enterNeverFlag = false
for (def line : lines) {
if (enterNeverFlag) {
if (line.contains("/*Don't delete this line*/")) {
configContent.append(ls).append(line)
enterNeverFlag = false
}
continue
}
configContent.append(ls).append(line)
if (line.contains("/*Don't delete this line*/")) {
configContent.append(ls).append(String.format("%-12s/*Generated by \"module_config.json\"*/", ""))
enterNeverFlag = true
for (String m : modules) {
configContent.append(ls).append(m)
}
}
}
configFile.write(configContent.substring(ls.length()).toString())
``` | /content/code_sandbox/module_config.gradle | gradle | 2016-07-30T18:18:32 | 2024-08-16T01:37:59 | AndroidUtilCode | Blankj/AndroidUtilCode | 33,178 | 551 |
```shell
#!/usr/bin/env bash
set -e
# build dev debug apk
./gradlew --daemon installDevDebug
# start main activity
adb shell am start -n "com.blankj.androidutilcode.dev/com.blankj.main.pkg.MainActivity" -a android.intent.action.MAIN -c android.intent.category.LAUNCHER
``` | /content/code_sandbox/script/runDevDebug.sh | shell | 2016-07-30T18:18:32 | 2024-08-16T01:37:59 | AndroidUtilCode | Blankj/AndroidUtilCode | 33,178 | 66 |
```java
package com.blankj.subutil.util;
/**
* <pre>
* author: Blankj
* blog : path_to_url
* time : 2018/08/25
* desc : utils about retrofit
* </pre>
*/
public final class RetrofitUtils {
}
``` | /content/code_sandbox/lib/subutil/src/main/java/com/blankj/subutil/util/RetrofitUtils.java | java | 2016-07-30T18:18:32 | 2024-08-16T01:37:59 | AndroidUtilCode | Blankj/AndroidUtilCode | 33,178 | 64 |
```shell
#!/usr/bin/env bash
while true; do
echo " ############## input command code #################"
echo " # [1] Git Push #"
echo " # [2] Git Push And Merge to Master #"
echo " # [other] exit #"
echo " ###################################################"
read which
case $which in
1)
curBranch=$(git symbolic-ref --short -q HEAD)
gitPush $curBranch
;;
2)
curBranch=$(git symbolic-ref --short -q HEAD)
gitPush $curBranch
echo "git checkout master"
echo $(git checkout master)
echo "git merge $branchName"
echo $(git merge $branchName)
echo "git push origin master"
echo $(git push origin master)
echo "git checkout $branchName"
echo $(git checkout $branchName)
;;
*)
echo "88"
break
;;
esac
done
function gitPush() {
curBranch=$1
echo "curBranch = $curBranch"
echo "git add -A"
echo $(git add -A)
date=$(date "+%m/%d")
echo "git commit -m \"see $date log\""
echo $(git commit -m "see $date log")
echo "git push origin $curBranch"
echo $(git push origin $curBranch)
}
``` | /content/code_sandbox/script/gitHelp.sh | shell | 2016-07-30T18:18:32 | 2024-08-16T01:37:59 | AndroidUtilCode | Blankj/AndroidUtilCode | 33,178 | 316 |
```gradle
apply plugin: "com.android.application"
apply {
from "${rootDir.path}/buildCommon.gradle"
from "${rootDir.path}/config/flavor.gradle"
if (Config.plugins.plugin_api.isApply) {
plugin Config.plugins.plugin_api.id
}
if (Config.plugins.plugin_bus.isApply) {
plugin Config.plugins.plugin_bus.id
}
}
configSigning()
configApkName()
//if (PluginConfig.plugin_bus.isApply) {
// bus {
// onlyScanLibRegex = '^([:]|(com\\.blankj)).+$'
// }
//}
//
//if (PluginConfig.plugin_api.isApply) {
// api {
// onlyScanLibRegex = '^([:]|(com\\.blankj)).+$'
// }
//}
android {
defaultConfig {
applicationId Config.applicationId + suffix
targetSdkVersion Config.targetSdkVersion
multiDexEnabled true
}
buildTypes {
debug {}
release {
minifyEnabled true
proguardFiles getDefaultProguardFile('proguard-android.txt'), 'proguard-rules.pro'
}
}
packagingOptions {
exclude 'META-INF/*'
}
dexOptions {
preDexLibraries true
javaMaxHeapSize "8g"
maxProcessCount 8
dexInProcess = true
}
productFlavors {
dev {
applicationIdSuffix ".dev"
versionNameSuffix "-dev"
resValue "string", "app_name", Config.appName + suffix + "-dev"
}
production {
resValue "string", "app_name", Config.appName + suffix
}
}
}
dependencies {
// LeakCanary
debugImplementation Config.libs.leakcanary.path
debugImplementation Config.modules.lib_utildebug.dep
releaseImplementation Config.modules.lib_utildebug_no_op.dep
// Config.pkgConfig pkg
for (def entrySet : ConfigUtils.getApplyPkgs().entrySet()) {
api entrySet.value.dep
}
if (Config.modules.feature_mock.isApply) {
api ModuleConfig.modules.feature_mock.dep
}
}
def getSuffix() {
if (project.name == "feature_launcher_app") return ""
return "." + project.
name.
substring("feature_".length(), project.name.length() - "_app".length())
}
def configSigning() {
File signPropertiesFile = file("${rootDir.path}/sign/keystore.properties")
if (!signPropertiesFile.exists()) return
GLog.d("${project.toString()} sign start...")
project.android {
Properties properties = new Properties()
properties.load(new FileInputStream(signPropertiesFile))
signingConfigs {
release {
storeFile new File(signPropertiesFile.getParent(), properties['keystore'])
storePassword properties['storePassword']
keyAlias properties['keyAlias']
keyPassword properties['keyPassword']
}
}
buildTypes.release.signingConfig signingConfigs.release
}
GLog.d("${project.toString()} sign end...")
}
def configApkName() {
project.android.applicationVariants.all { variant ->
if (variant.buildType.name != "debug") {
def artifact = variant.getPackageApplicationProvider().get()
artifact.outputDirectory = new File("${rootDir.path}/apk")
variant.outputs.each {
it.outputFileName = "util" + suffix +
(variant.flavorName == "" ? "" : ("_" + variant.flavorName)) +
"_" +
variant.versionName.replace(".", "_") +
"_" +
variant.buildType.name +
".apk"
}
}
}
}
``` | /content/code_sandbox/buildApp.gradle | gradle | 2016-07-30T18:18:32 | 2024-08-16T01:37:59 | AndroidUtilCode | Blankj/AndroidUtilCode | 33,178 | 759 |
```gradle
apply {
plugin "kotlin-android"
plugin "kotlin-android-extensions"
}
android {
compileSdkVersion Config.compileSdkVersion
defaultConfig {
minSdkVersion Config.minSdkVersion
versionCode Config.versionCode
versionName Config.versionName
consumerProguardFiles 'proguard-rules.pro'
}
buildTypes {
release {
minifyEnabled true
proguardFiles getDefaultProguardFile('proguard-android.txt'), 'proguard-rules.pro'
}
}
compileOptions {
sourceCompatibility JavaVersion.VERSION_1_8
targetCompatibility JavaVersion.VERSION_1_8
}
lintOptions {
abortOnError false
}
}
``` | /content/code_sandbox/buildCommon.gradle | gradle | 2016-07-30T18:18:32 | 2024-08-16T01:37:59 | AndroidUtilCode | Blankj/AndroidUtilCode | 33,178 | 150 |
```qmake
# Add project specific ProGuard rules here.
# By default, the flags in this file are appended to flags specified
# in /Users/Blankj/Library/Android/android_sdk/tools/proguard/proguard-android.txt
# You can edit the include path and order by changing the proguardFiles
# directive in build.gradle.
#
# For more details, see
# path_to_url
# Add any project specific keep options here:
# If your project uses WebView with JS, uncomment the following
# and specify the fully qualified class name to the JavaScript interface
# class:
#-keepclassmembers class fqcn.of.javascript.interface.for.webview {
# public *;
#}
# Uncomment this to preserve the line number information for
# debugging stack traces.
#-keepattributes SourceFile,LineNumberTable
# If you keep the line number information, uncomment this to
# hide the original source file name.
#-renamesourcefileattribute SourceFile
#-keep class com.blankj.subutil.** { *; }
#-keepclassmembers class com.blankj.subutil.** { *; }
-dontwarn com.blankj.subutil.**
``` | /content/code_sandbox/lib/subutil/proguard-rules.pro | qmake | 2016-07-30T18:18:32 | 2024-08-16T01:37:59 | AndroidUtilCode | Blankj/AndroidUtilCode | 33,178 | 241 |
```gradle
apply plugin: "com.android.library"
apply from: "${rootDir.path}/buildCommon.gradle"
dependencies {
if (project.name.endsWith("_pkg") || project.name.endsWith("_mock")) {
// if module's name equals 'pkg', api all of export
for (def entrySet : ConfigUtils.getApplyExports().entrySet()) {
api entrySet.value.dep
}
} else if (project.name.endsWith("_export")) {
api Config.modules.lib_common.dep
}
}
``` | /content/code_sandbox/buildLib.gradle | gradle | 2016-07-30T18:18:32 | 2024-08-16T01:37:59 | AndroidUtilCode | Blankj/AndroidUtilCode | 33,178 | 104 |
```java
package com.blankj.subutil.util;
import android.content.Context;
import android.content.Intent;
import android.location.Address;
import android.location.Criteria;
import android.location.Geocoder;
import android.location.Location;
import android.location.LocationListener;
import android.location.LocationManager;
import android.location.LocationProvider;
import android.os.Bundle;
import android.provider.Settings;
import androidx.annotation.RequiresPermission;
import android.util.Log;
import com.blankj.utilcode.util.Utils;
import java.io.IOException;
import java.util.List;
import java.util.Locale;
import static android.Manifest.permission.ACCESS_COARSE_LOCATION;
import static android.Manifest.permission.ACCESS_FINE_LOCATION;
/**
* <pre>
* author: Blankj
* blog : path_to_url
* time : 16/11/13
* desc :
* </pre>
*/
public final class LocationUtils {
private static final int TWO_MINUTES = 1000 * 60 * 2;
private static OnLocationChangeListener mListener;
private static MyLocationListener myLocationListener;
private static LocationManager mLocationManager;
private LocationUtils() {
throw new UnsupportedOperationException("u can't instantiate me...");
}
// /**
// * you have to check for Location Permission before use this method
// * add this code <uses-permission android:name="android.permission.ACCESS_FINE_LOCATION" /> to your Manifest file.
// * you have also implement LocationListener and passed it to the method.
// *
// * @param Context
// * @param LocationListener
// * @return {@code Location}
// */
//
// @SuppressLint("MissingPermission")
// public static Location getLocation(Context context, LocationListener listener) {
// Location location = null;
// try {
// mLocationManager = (LocationManager) context.getSystemService(LOCATION_SERVICE);
// if (!isLocationEnabled()) {
// //no Network and GPS providers is enabled
// Toast.makeText(context
// , " you have to open GPS or INTERNET"
// , Toast.LENGTH_LONG)
// .show();
// } else {
// if (isLocationEnabled()) {
// mLocationManager.requestLocationUpdates(
// LocationManager.NETWORK_PROVIDER,
// MIN_TIME_BETWEEN_UPDATES,
// MIN_DISTANCE_CHANGE_FOR_UPDATES,
// listener);
//
// if (mLocationManager != null) {
// location = mLocationManager.getLastKnownLocation(LocationManager.NETWORK_PROVIDER);
// if (location != null) {
// mLocationManager.removeUpdates(listener);
// return location;
// }
// }
// }
// //when GPS is enabled.
// if (isGpsEnabled()) {
// if (location == null) {
// mLocationManager.requestLocationUpdates(LocationManager.GPS_PROVIDER,
// MIN_TIME_BETWEEN_UPDATES,
// MIN_DISTANCE_CHANGE_FOR_UPDATES,
// listener);
//
// if (mLocationManager != null) {
// location =
// mLocationManager.getLastKnownLocation(LocationManager.GPS_PROVIDER);
// if (location != null) {
// mLocationManager.removeUpdates(listener);
// return location;
// }
// }
// }
// }
//
// }
// } catch (Exception e) {
// e.printStackTrace();
// }
//
// return location;
// }
/**
* Gps
*
* @return {@code true}: <br>{@code false}:
*/
public static boolean isGpsEnabled() {
LocationManager lm = (LocationManager) Utils.getApp().getSystemService(Context.LOCATION_SERVICE);
return lm.isProviderEnabled(LocationManager.GPS_PROVIDER);
}
/**
*
*
* @return {@code true}: <br>{@code false}:
*/
public static boolean isLocationEnabled() {
LocationManager lm = (LocationManager) Utils.getApp().getSystemService(Context.LOCATION_SERVICE);
return lm.isProviderEnabled(LocationManager.NETWORK_PROVIDER)
|| lm.isProviderEnabled(LocationManager.GPS_PROVIDER);
}
/**
* Gps
*/
public static void openGpsSettings() {
Intent intent = new Intent(Settings.ACTION_LOCATION_SOURCE_SETTINGS);
Utils.getApp().startActivity(intent.addFlags(Intent.FLAG_ACTIVITY_NEW_TASK));
}
/**
*
* <p>{@link #unregister()}</p>
* <p> {@code <uses-permission android:name="android.permission.INTERNET" />}</p>
* <p> {@code <uses-permission android:name="android.permission.ACCESS_COARSE_LOCATION" />}</p>
* <p> {@code <uses-permission android:name="android.permission.ACCESS_FINE_LOCATION" />}</p>
* <p>{@code minDistance}0{@code minTime}</p>
* <p>{@code minDistance}0{@code minDistance}</p>
* <p>0</p>
*
* @param minTime
* @param minDistance
* @param listener
* @return {@code true}: <br>{@code false}:
*/
@RequiresPermission(ACCESS_FINE_LOCATION)
public static boolean register(long minTime, long minDistance, OnLocationChangeListener listener) {
if (listener == null) return false;
mLocationManager = (LocationManager) Utils.getApp().getSystemService(Context.LOCATION_SERVICE);
if (!mLocationManager.isProviderEnabled(LocationManager.NETWORK_PROVIDER)
&& !mLocationManager.isProviderEnabled(LocationManager.GPS_PROVIDER)) {
Log.d("LocationUtils", "");
return false;
}
mListener = listener;
String provider = mLocationManager.getBestProvider(getCriteria(), true);
Location location = mLocationManager.getLastKnownLocation(provider);
if (location != null) listener.getLastKnownLocation(location);
if (myLocationListener == null) myLocationListener = new MyLocationListener();
mLocationManager.requestLocationUpdates(provider, minTime, minDistance, myLocationListener);
return true;
}
/**
*
*/
@RequiresPermission(ACCESS_COARSE_LOCATION)
public static void unregister() {
if (mLocationManager != null) {
if (myLocationListener != null) {
mLocationManager.removeUpdates(myLocationListener);
myLocationListener = null;
}
mLocationManager = null;
}
if (mListener != null) {
mListener = null;
}
}
/**
*
*
* @return {@link Criteria}
*/
private static Criteria getCriteria() {
Criteria criteria = new Criteria();
// Criteria.ACCURACY_COARSECriteria.ACCURACY_FINE
criteria.setAccuracy(Criteria.ACCURACY_FINE);
//
criteria.setSpeedRequired(false);
//
criteria.setCostAllowed(false);
//
criteria.setBearingRequired(false);
//
criteria.setAltitudeRequired(false);
//
criteria.setPowerRequirement(Criteria.POWER_LOW);
return criteria;
}
/**
*
*
* @param latitude
* @param longitude
* @return {@link Address}
*/
public static Address getAddress(double latitude, double longitude) {
Geocoder geocoder = new Geocoder(Utils.getApp(), Locale.getDefault());
try {
List<Address> addresses = geocoder.getFromLocation(latitude, longitude, 1);
if (addresses.size() > 0) return addresses.get(0);
} catch (IOException e) {
e.printStackTrace();
}
return null;
}
/**
*
*
* @param latitude
* @param longitude
* @return
*/
public static String getCountryName(double latitude, double longitude) {
Address address = getAddress(latitude, longitude);
return address == null ? "unknown" : address.getCountryName();
}
/**
*
*
* @param latitude
* @param longitude
* @return
*/
public static String getLocality(double latitude, double longitude) {
Address address = getAddress(latitude, longitude);
return address == null ? "unknown" : address.getLocality();
}
/**
*
*
* @param latitude
* @param longitude
* @return
*/
public static String getStreet(double latitude, double longitude) {
Address address = getAddress(latitude, longitude);
return address == null ? "unknown" : address.getAddressLine(0);
}
/**
*
*
* @param newLocation The new Location that you want to evaluate
* @param currentBestLocation The current Location fix, to which you want to compare the new one
* @return {@code true}: <br>{@code false}:
*/
public static boolean isBetterLocation(Location newLocation, Location currentBestLocation) {
if (currentBestLocation == null) {
// A new location is always better than no location
return true;
}
// Check whether the new location fix is newer or older
long timeDelta = newLocation.getTime() - currentBestLocation.getTime();
boolean isSignificantlyNewer = timeDelta > TWO_MINUTES;
boolean isSignificantlyOlder = timeDelta < -TWO_MINUTES;
boolean isNewer = timeDelta > 0;
// If it's been more than two minutes since the current location, use the new location
// because the user has likely moved
if (isSignificantlyNewer) {
return true;
// If the new location is more than two minutes older, it must be worse
} else if (isSignificantlyOlder) {
return false;
}
// Check whether the new location fix is more or less accurate
int accuracyDelta = (int) (newLocation.getAccuracy() - currentBestLocation.getAccuracy());
boolean isLessAccurate = accuracyDelta > 0;
boolean isMoreAccurate = accuracyDelta < 0;
boolean isSignificantlyLessAccurate = accuracyDelta > 200;
// Check if the old and new location are from the same provider
boolean isFromSameProvider = isSameProvider(newLocation.getProvider(), currentBestLocation.getProvider());
// Determine location quality using a combination of timeliness and accuracy
if (isMoreAccurate) {
return true;
} else if (isNewer && !isLessAccurate) {
return true;
} else if (isNewer && !isSignificantlyLessAccurate && isFromSameProvider) {
return true;
}
return false;
}
/**
*
*
* @param provider0 1
* @param provider1 2
* @return {@code true}: <br>{@code false}:
*/
public static boolean isSameProvider(String provider0, String provider1) {
if (provider0 == null) {
return provider1 == null;
}
return provider0.equals(provider1);
}
private static class MyLocationListener
implements LocationListener {
/**
* Provider
*
* @param location
*/
@Override
public void onLocationChanged(Location location) {
if (mListener != null) {
mListener.onLocationChanged(location);
}
}
/**
* provider
*
* @param provider
* @param status
* @param extras provider
*/
@Override
public void onStatusChanged(String provider, int status, Bundle extras) {
if (mListener != null) {
mListener.onStatusChanged(provider, status, extras);
}
switch (status) {
case LocationProvider.AVAILABLE:
Log.d("LocationUtils", "GPS");
break;
case LocationProvider.OUT_OF_SERVICE:
Log.d("LocationUtils", "GPS");
break;
case LocationProvider.TEMPORARILY_UNAVAILABLE:
Log.d("LocationUtils", "GPS");
break;
}
}
/**
* providerenableGPS
*/
@Override
public void onProviderEnabled(String provider) {
}
/**
* providerdisableGPS
*/
@Override
public void onProviderDisabled(String provider) {
}
}
public interface OnLocationChangeListener {
/**
*
*
* @param location
*/
void getLastKnownLocation(Location location);
/**
* Provider
*
* @param location
*/
void onLocationChanged(Location location);
/**
* provider
*
* @param provider
* @param status
* @param extras provider
*/
void onStatusChanged(String provider, int status, Bundle extras);//
}
}
``` | /content/code_sandbox/lib/subutil/src/main/java/com/blankj/subutil/util/LocationUtils.java | java | 2016-07-30T18:18:32 | 2024-08-16T01:37:59 | AndroidUtilCode | Blankj/AndroidUtilCode | 33,178 | 2,687 |
```java
package com.blankj.subutil.util;
import android.content.BroadcastReceiver;
import android.content.Context;
import android.content.Intent;
import android.content.IntentFilter;
import android.os.BatteryManager;
import android.os.Build;
import android.os.PowerManager;
import com.blankj.utilcode.util.ThreadUtils;
import com.blankj.utilcode.util.Utils;
import java.lang.annotation.Retention;
import java.lang.annotation.RetentionPolicy;
import java.util.HashSet;
import java.util.Set;
import androidx.annotation.IntDef;
import androidx.annotation.RequiresApi;
/**
* <pre>
* author: blankj
* blog : path_to_url
* time : 2020/03/31
* desc :
* </pre>
*/
public final class BatteryUtils {
@IntDef({BatteryStatus.UNKNOWN, BatteryStatus.DISCHARGING, BatteryStatus.CHARGING,
BatteryStatus.NOT_CHARGING, BatteryStatus.FULL})
@Retention(RetentionPolicy.SOURCE)
public @interface BatteryStatus {
int UNKNOWN = BatteryManager.BATTERY_STATUS_UNKNOWN;
int DISCHARGING = BatteryManager.BATTERY_STATUS_DISCHARGING;
int CHARGING = BatteryManager.BATTERY_STATUS_CHARGING;
int NOT_CHARGING = BatteryManager.BATTERY_STATUS_NOT_CHARGING;
int FULL = BatteryManager.BATTERY_STATUS_FULL;
}
/**
* Return whether the app is on the device's power whitelist.
*
* @return {@code true}: yes<br>{@code false}: no
*/
@RequiresApi(api = Build.VERSION_CODES.M)
public static boolean isIgnoringBatteryOptimizations() {
return isIgnoringBatteryOptimizations(Utils.getApp().getPackageName());
}
/**
* Return whether the app is on the device's power whitelist.
*
* @return {@code true}: yes<br>{@code false}: no
*/
@RequiresApi(api = Build.VERSION_CODES.M)
public static boolean isIgnoringBatteryOptimizations(String pkgName) {
try {
PowerManager pm = (PowerManager) Utils.getApp().getSystemService(Context.POWER_SERVICE);
//noinspection ConstantConditions
return pm.isIgnoringBatteryOptimizations(pkgName);
} catch (Exception e) {
return true;
}
}
/**
* Register the status of battery changed listener.
*
* @param listener The status of battery changed listener.
*/
public static void registerBatteryStatusChangedListener(final OnBatteryStatusChangedListener listener) {
BatteryChangedReceiver.getInstance().registerListener(listener);
}
/**
* Return whether the status of battery changed listener has been registered.
*
* @param listener The status of battery changed listener.
* @return true to registered, false otherwise.
*/
public static boolean isRegistered(final OnBatteryStatusChangedListener listener) {
return BatteryChangedReceiver.getInstance().isRegistered(listener);
}
/**
* Unregister the status of battery changed listener.
*
* @param listener The status of battery changed listener.
*/
public static void unregisterBatteryStatusChangedListener(final OnBatteryStatusChangedListener listener) {
BatteryChangedReceiver.getInstance().unregisterListener(listener);
}
public static final class BatteryChangedReceiver extends BroadcastReceiver {
private static BatteryChangedReceiver getInstance() {
return BatteryChangedReceiver.LazyHolder.INSTANCE;
}
private Set<OnBatteryStatusChangedListener> mListeners = new HashSet<>();
void registerListener(final OnBatteryStatusChangedListener listener) {
if (listener == null) return;
ThreadUtils.runOnUiThread(new Runnable() {
@Override
public void run() {
int preSize = mListeners.size();
mListeners.add(listener);
if (preSize == 0 && mListeners.size() == 1) {
IntentFilter intentFilter = new IntentFilter();
intentFilter.addAction(Intent.ACTION_BATTERY_CHANGED);
Utils.getApp().registerReceiver(BatteryChangedReceiver.getInstance(), intentFilter);
}
}
});
}
boolean isRegistered(final OnBatteryStatusChangedListener listener) {
if (listener == null) return false;
return mListeners.contains(listener);
}
void unregisterListener(final OnBatteryStatusChangedListener listener) {
if (listener == null) return;
ThreadUtils.runOnUiThread(new Runnable() {
@Override
public void run() {
int preSize = mListeners.size();
mListeners.remove(listener);
if (preSize == 1 && mListeners.size() == 0) {
Utils.getApp().unregisterReceiver(BatteryChangedReceiver.getInstance());
}
}
});
}
@Override
public void onReceive(Context context, final Intent intent) {
if (Intent.ACTION_BATTERY_CHANGED.equals(intent.getAction())) {
ThreadUtils.runOnUiThread(new Runnable() {
@Override
public void run() {
int level = intent.getIntExtra(BatteryManager.EXTRA_LEVEL, -1);
int status = intent.getIntExtra(BatteryManager.EXTRA_STATUS, BatteryStatus.UNKNOWN);
for (OnBatteryStatusChangedListener listener : mListeners) {
listener.onBatteryStatusChanged(new Status(level, status));
}
}
});
}
}
private static class LazyHolder {
private static final BatteryChangedReceiver INSTANCE = new BatteryChangedReceiver();
}
}
public interface OnBatteryStatusChangedListener {
void onBatteryStatusChanged(Status status);
}
public static final class Status {
private int level;
@BatteryStatus
private int status;
Status(int level, int status) {
this.level = level;
this.status = status;
}
public int getLevel() {
return level;
}
public void setLevel(int level) {
this.level = level;
}
@BatteryStatus
public int getStatus() {
return status;
}
public void setStatus(int status) {
this.status = status;
}
@Override
public String toString() {
return batteryStatus2String(status) + ": " + level + "%";
}
public static String batteryStatus2String(@BatteryStatus int status) {
if (status == BatteryStatus.DISCHARGING) {
return "discharging";
}
if (status == BatteryStatus.CHARGING) {
return "charging";
}
if (status == BatteryStatus.NOT_CHARGING) {
return "not_charging";
}
if (status == BatteryStatus.FULL) {
return "full";
}
return "unknown";
}
}
}
``` | /content/code_sandbox/lib/subutil/src/main/java/com/blankj/subutil/util/BatteryUtils.java | java | 2016-07-30T18:18:32 | 2024-08-16T01:37:59 | AndroidUtilCode | Blankj/AndroidUtilCode | 33,178 | 1,360 |
```java
package com.blankj.subutil.util;
/**
* <pre>
* author: Blankj
* blog : path_to_url
* time : 2016/09/19
* desc :
* </pre>
*/
public final class CameraUtils {
// private CameraUtils() {
// throw new UnsupportedOperationException("u can't instantiate me...");
// }
//
// /**
// * Intent
// */
// public static Intent getOpenCameraIntent() {
// return new Intent(MediaStore.ACTION_IMAGE_CAPTURE);
// }
//
// /**
// * Intent
// */
// public static Intent getImagePickerIntent() {
// Intent intent = new Intent(Intent.ACTION_PICK, null);
// return intent.setDataAndType(MediaStore.Images.Media.EXTERNAL_CONTENT_URI, "image/*");
// }
//
// /**
// * [,]Intent
// */
// public static Intent getImagePickerIntent(int outputX, int outputY, Uri fromFileURI,
// Uri saveFileURI) {
// return getImagePickerIntent(1, 1, outputX, outputY, true, fromFileURI, saveFileURI);
// }
//
// /**
// * [,]Intent
// */
// public static Intent getImagePickerIntent(int aspectX, int aspectY, int outputX, int outputY, Uri fromFileURI,
// Uri saveFileURI) {
// return getImagePickerIntent(aspectX, aspectY, outputX, outputY, true, fromFileURI, saveFileURI);
// }
//
// /**
// * [,]Intent
// *
// * @param aspectX X
// * @param aspectY Y
// * @param outputX
// * @param outputY
// * @param canScale
// * @param fromFileURI URI
// * @param saveFileURI URI
// */
// public static Intent getImagePickerIntent(int aspectX, int aspectY, int outputX, int outputY, boolean canScale,
// Uri fromFileURI, Uri saveFileURI) {
// Intent intent = new Intent(Intent.ACTION_PICK);
// intent.setDataAndType(fromFileURI, "image/*");
// intent.putExtra("crop", "true");
// intent.putExtra("aspectX", aspectX <= 0 ? 1 : aspectX);
// intent.putExtra("aspectY", aspectY <= 0 ? 1 : aspectY);
// intent.putExtra("outputX", outputX);
// intent.putExtra("outputY", outputY);
// intent.putExtra("scale", canScale);
// //
// intent.putExtra("scaleUpIfNeeded", true);
// intent.putExtra("return-data", false);
// intent.putExtra(MediaStore.EXTRA_OUTPUT, saveFileURI);
// intent.putExtra("outputFormat", Bitmap.CompressFormat.JPEG.toString());
// //
// return intent.putExtra("noFaceDetection", true);
// }
//
// /**
// * [,]Intent
// */
// public static Intent getCameraIntent(final Uri saveFileURI) {
// Intent mIntent = new Intent(MediaStore.ACTION_IMAGE_CAPTURE);
// return mIntent.putExtra(MediaStore.EXTRA_OUTPUT, saveFileURI);
// }
//
// /**
// * [,]Intent
// */
// public static Intent getCropImageIntent(int outputX, int outputY, Uri fromFileURI,
// Uri saveFileURI) {
// return getCropImageIntent(1, 1, outputX, outputY, true, fromFileURI, saveFileURI);
// }
//
// /**
// * [,]Intent
// */
// public static Intent getCropImageIntent(int aspectX, int aspectY, int outputX, int outputY, Uri fromFileURI,
// Uri saveFileURI) {
// return getCropImageIntent(aspectX, aspectY, outputX, outputY, true, fromFileURI, saveFileURI);
// }
//
//
// /**
// * []Intent
// */
// public static Intent getCropImageIntent(int aspectX, int aspectY, int outputX, int outputY, boolean canScale,
// Uri fromFileURI, Uri saveFileURI) {
// Intent intent = new Intent("com.android.camera.action.CROP");
// intent.setDataAndType(fromFileURI, "image/*");
// intent.putExtra("crop", "true");
// // X
// intent.putExtra("aspectX", aspectX <= 0 ? 1 : aspectX);
// // Y
// intent.putExtra("aspectY", aspectY <= 0 ? 1 : aspectY);
// intent.putExtra("outputX", outputX);
// intent.putExtra("outputY", outputY);
// intent.putExtra("scale", canScale);
// //
// intent.putExtra("scaleUpIfNeeded", true);
// intent.putExtra("return-data", false);
// // 0byte
// intent.putExtra(MediaStore.EXTRA_OUTPUT, saveFileURI);
// // true-->BitmapURIBitmapURI
// intent.putExtra("outputFormat", Bitmap.CompressFormat.JPEG.toString());
// //
// intent.putExtra("noFaceDetection", true);
// return intent;
// }
//
// /**
// *
// *
// * @param context
// * @param data onActivityResultIntent
// * @return bitmap
// */
// public static Bitmap getChoosedImage(final Activity context, final Intent data) {
// if (data == null) return null;
// Bitmap bm = null;
// ContentResolver cr = context.getContentResolver();
// Uri originalUri = data.getData();
// try {
// bm = MediaStore.Images.Media.getBitmap(cr, originalUri);
// } catch (IOException e) {
// e.printStackTrace();
// }
// return bm;
// }
//
// /**
// *
// *
// * @param context
// * @param data onActivityResultIntent
// * @return
// */
// public static String getChoosedImagePath(final Activity context, final Intent data) {
// if (data == null) return null;
// String path = "";
// ContentResolver resolver = context.getContentResolver();
// Uri originalUri = data.getData();
// if (null == originalUri) return null;
// String[] projection = {MediaStore.Images.Media.DATA};
// Cursor cursor = resolver.query(originalUri, projection, null, null, null);
// if (null != cursor) {
// try {
// int column_index = cursor.getColumnIndexOrThrow(MediaStore.Images.Media.DATA);
// cursor.moveToFirst();
// path = cursor.getString(column_index);
// } catch (IllegalArgumentException e) {
// e.printStackTrace();
// } finally {
// try {
// if (!cursor.isClosed()) {
// cursor.close();
// }
// } catch (Exception e) {
// e.printStackTrace();
// }
// }
// }
// return StringUtils.isEmpty(path) ? originalUri.getPath() : null;
// }
//
// /**
// * JPG
// *
// * @param data onActivityResult
// * @param filePath The path of file.
// * @return
// */
// public static File getTakePictureFile(final Intent data, final String filePath) {
// if (data == null) return null;
// Bundle extras = data.getExtras();
// if (extras == null) return null;
// Bitmap photo = extras.getParcelable("data");
// File file = new File(filePath);
// if (ImageUtils.save(photo, file, Bitmap.CompressFormat.JPEG)) return file;
// return null;
// }
}
``` | /content/code_sandbox/lib/subutil/src/main/java/com/blankj/subutil/util/CameraUtils.java | java | 2016-07-30T18:18:32 | 2024-08-16T01:37:59 | AndroidUtilCode | Blankj/AndroidUtilCode | 33,178 | 1,665 |
```java
package com.blankj.subutil.util;
import static java.lang.Math.PI;
/**
* <pre>
* author: Blankj
* blog : path_to_url
* time : 2018/03/21
* desc :
* </pre>
*/
public final class CoordinateUtils {
private final static double X_PI = 3.14159265358979324 * 3000.0 / 180.0;
private final static double A = 6378245.0;
private final static double EE = 0.00669342162296594323;
/**
* BD09 GCJ02
*
* @param lng BD09
* @param lat BD09
* @return GCJ02 []
*/
public static double[] bd09ToGcj02(double lng, double lat) {
double x = lng - 0.0065;
double y = lat - 0.006;
double z = Math.sqrt(x * x + y * y) - 0.00002 * Math.sin(y * X_PI);
double theta = Math.atan2(y, x) - 0.000003 * Math.cos(x * X_PI);
double gg_lng = z * Math.cos(theta);
double gg_lat = z * Math.sin(theta);
return new double[]{gg_lng, gg_lat};
}
/**
* GCJ02 BD09
*
* @param lng GCJ02
* @param lat GCJ02
* @return BD09 []
*/
public static double[] gcj02ToBd09(double lng, double lat) {
double z = Math.sqrt(lng * lng + lat * lat) + 0.00002 * Math.sin(lat * X_PI);
double theta = Math.atan2(lat, lng) + 0.000003 * Math.cos(lng * X_PI);
double bd_lng = z * Math.cos(theta) + 0.0065;
double bd_lat = z * Math.sin(theta) + 0.006;
return new double[]{bd_lng, bd_lat};
}
/**
* GCJ02 WGS84
*
* @param lng GCJ02
* @param lat GCJ02
* @return WGS84 []
*/
public static double[] gcj02ToWGS84(double lng, double lat) {
if (outOfChina(lng, lat)) {
return new double[]{lng, lat};
}
double dlat = transformLat(lng - 105.0, lat - 35.0);
double dlng = transformLng(lng - 105.0, lat - 35.0);
double radlat = lat / 180.0 * PI;
double magic = Math.sin(radlat);
magic = 1 - EE * magic * magic;
double sqrtmagic = Math.sqrt(magic);
dlat = (dlat * 180.0) / ((A * (1 - EE)) / (magic * sqrtmagic) * PI);
dlng = (dlng * 180.0) / (A / sqrtmagic * Math.cos(radlat) * PI);
double mglat = lat + dlat;
double mglng = lng + dlng;
return new double[]{lng * 2 - mglng, lat * 2 - mglat};
}
/**
* WGS84 GCJ02
*
* @param lng WGS84
* @param lat WGS84
* @return GCJ02 []
*/
public static double[] wgs84ToGcj02(double lng, double lat) {
if (outOfChina(lng, lat)) {
return new double[]{lng, lat};
}
double dlat = transformLat(lng - 105.0, lat - 35.0);
double dlng = transformLng(lng - 105.0, lat - 35.0);
double radlat = lat / 180.0 * PI;
double magic = Math.sin(radlat);
magic = 1 - EE * magic * magic;
double sqrtmagic = Math.sqrt(magic);
dlat = (dlat * 180.0) / ((A * (1 - EE)) / (magic * sqrtmagic) * PI);
dlng = (dlng * 180.0) / (A / sqrtmagic * Math.cos(radlat) * PI);
double mglat = lat + dlat;
double mglng = lng + dlng;
return new double[]{mglng, mglat};
}
/**
* BD09 WGS84
*
* @param lng BD09
* @param lat BD09
* @return WGS84 []
*/
public static double[] bd09ToWGS84(double lng, double lat) {
double[] gcj = bd09ToGcj02(lng, lat);
return gcj02ToWGS84(gcj[0], gcj[1]);
}
/**
* WGS84 BD09
*
* @param lng WGS84
* @param lat WGS84
* @return BD09 []
*/
public static double[] wgs84ToBd09(double lng, double lat) {
double[] gcj = wgs84ToGcj02(lng, lat);
return gcj02ToBd09(gcj[0], gcj[1]);
}
/**
* Mercator WGS84
*
* @param lng Mercator
* @param lat Mercator
* @return WGS84 []
*/
public static double[] mercatorToWGS84(double lng, double lat) {
double x = lng / 20037508.34d * 180.;
double y = lat / 20037508.34d * 180.;
y = 180 / PI * (2 * Math.atan(Math.exp(y * PI / 180.0)) - PI / 2);
return new double[]{x, y};
}
/**
* WGS84 Mercator
*
* @param lng WGS84
* @param lat WGS84
* @return Mercator []
*/
public static double[] wgs84ToMercator(double lng, double lat) {
double x = lng * 20037508.34D / 180.0;
double y = Math.log(Math.tan((90.0 + lat) * PI / 360.0)) / (PI / 180.);
y = y * 20037508.34D / 180.0;
return new double[]{x, y};
}
private static double transformLat(double lng, double lat) {
double ret = -100.0 + 2.0 * lng + 3.0 * lat + 0.2 * lat * lat + 0.1 * lng * lat + 0.2 * Math.sqrt(Math.abs(lng));
ret += (20.0 * Math.sin(6.0 * lng * PI) + 20.0 * Math.sin(2.0 * lng * PI)) * 2.0 / 3.0;
ret += (20.0 * Math.sin(lat * PI) + 40.0 * Math.sin(lat / 3.0 * PI)) * 2.0 / 3.0;
ret += (160.0 * Math.sin(lat / 12.0 * PI) + 320 * Math.sin(lat * PI / 30.0)) * 2.0 / 3.0;
return ret;
}
private static double transformLng(double lng, double lat) {
double ret = 300.0 + lng + 2.0 * lat + 0.1 * lng * lng + 0.1 * lng * lat + 0.1 * Math.sqrt(Math.abs(lng));
ret += (20.0 * Math.sin(6.0 * lng * PI) + 20.0 * Math.sin(2.0 * lng * PI)) * 2.0 / 3.0;
ret += (20.0 * Math.sin(lng * PI) + 40.0 * Math.sin(lng / 3.0 * PI)) * 2.0 / 3.0;
ret += (150.0 * Math.sin(lng / 12.0 * PI) + 300.0 * Math.sin(lng / 30.0 * PI)) * 2.0 / 3.0;
return ret;
}
private static boolean outOfChina(double lng, double lat) {
return lng < 72.004 || lng > 137.8347 || lat < 0.8293 || lat > 55.8271;
}
}
``` | /content/code_sandbox/lib/subutil/src/main/java/com/blankj/subutil/util/CoordinateUtils.java | java | 2016-07-30T18:18:32 | 2024-08-16T01:37:59 | AndroidUtilCode | Blankj/AndroidUtilCode | 33,178 | 1,931 |
```java
package com.blankj.subutil.util;
import android.util.Log;
/**
* <pre>
* author: Blankj
* blog : path_to_url
* time : 2018/03/21
* desc :
* </pre>
*/
public final class BitUtils {
private BitUtils() {
throw new UnsupportedOperationException("u can't instantiate me...");
}
/**
* <br>
* 0000 1011 0 1, 2 0<br>
*
* @param source
* @param pos (0...7)
* @return (0 or 1)
*/
public static byte getBitValue(byte source, int pos) {
return (byte) ((source >> pos) & 1);
}
/**
* <br>
* : 0000 1011 0000 1111, 2 1<br>
*
* @param source
* @param pos (0<=pos<=7)
* @param value 0, 1, 01, 00
* @return
*/
public static byte setBitValue(byte source, int pos, byte value) {
byte mask = (byte) (1 << pos);
if (value > 0) {
source |= mask;
} else {
source &= (~mask);
}
return source;
}
/**
* <br>
* 0000 1011 3 , 0000 0011; 2, 0000 1111<br>
*
* @param source
* @param pos (0<=pos<=7)
* @return
*/
public static byte reverseBitValue(byte source, int pos) {
byte mask = (byte) (1 << pos);
return (byte) (source ^ mask);
}
/**
* 1<br>
*
* @param source
* @param pos (0<=pos<=7)
* @return true 1, false 0
*/
public static boolean checkBitValue(byte source, int pos) {
source = (byte) (source >>> pos);
return (source & 1) == 1;
}
/**
* <br>
*
* @param args
*/
public static void main(String[] args) {
// 11 ( 0000 1011)
byte source = 11;
// 2, 0000 1011
for (byte i = 7; i >= 0; i--) {
Log.d("BitUtils", getBitValue(source, i) + "");
}
// 61 , 75 (0100 1011)
Log.d("BitUtils", setBitValue(source, 6, (byte) 1) + "");
// 6, 75(0100 1011)
Log.d("BitUtils", reverseBitValue(source, 6) + "");
// 61false
Log.d("BitUtils", checkBitValue(source, 6) + "");
// 1, 0 1 3
for (byte i = 0; i < 8; i++) {
if (checkBitValue(source, i)) {
Log.d("BitUtils", i + "");
}
}
}
}
``` | /content/code_sandbox/lib/subutil/src/main/java/com/blankj/subutil/util/BitUtils.java | java | 2016-07-30T18:18:32 | 2024-08-16T01:37:59 | AndroidUtilCode | Blankj/AndroidUtilCode | 33,178 | 751 |
```java
package com.blankj.subutil.util;
/**
* <pre>
* author: Faramarz Afzali
* time : 2020/09/05
* desc : This class is intended for converting temperatures into different units.
* C refers to the Celsius unit
* F refers to the Fahrenheit unit
* K refers to the Kelvin unit
* </pre>
*/
public final class TemperatureUtils {
public static float cToF(float temp) {
return (temp * 9) / 5 + 32;
}
public static float cToK(float temp) {
return temp + 273.15f;
}
public static float fToC(float temp) {
return (temp - 32) * 5 / 9;
}
public static float fToK(float temp) {
return temp + 255.3722222222f;
}
public static float kToC(float temp) {
return temp - 273.15f;
}
public static float kToF(float temp) {
return temp - 459.67f;
}
}
``` | /content/code_sandbox/lib/subutil/src/main/java/com/blankj/subutil/util/TemperatureUtils.java | java | 2016-07-30T18:18:32 | 2024-08-16T01:37:59 | AndroidUtilCode | Blankj/AndroidUtilCode | 33,178 | 243 |
```java
package com.blankj.subutil.util;
/**
* <pre>
* author: Blankj
* blog : path_to_url
* time : 2016/12/05
* desc :
* </pre>
*/
public final class LunarUtils {
private LunarUtils() {
throw new UnsupportedOperationException("u can't instantiate me...");
}
/*
* |----4|-------------13130029|
*/
private static final int[] LUNAR_MONTH_DAYS = {1887, 0x1694, 0x16aa, 0x4ad5, 0xab6, 0xc4b7, 0x4ae, 0xa56, 0xb52a, 0x1d2a,
0xd54, 0x75aa, 0x156a, 0x1096d, 0x95c, 0x14ae, 0xaa4d, 0x1a4c, 0x1b2a, 0x8d55, 0xad4, 0x135a, 0x495d, 0x95c,
0xd49b, 0x149a, 0x1a4a, 0xbaa5, 0x16a8, 0x1ad4, 0x52da, 0x12b6, 0xe937, 0x92e, 0x1496, 0xb64b, 0xd4a, 0xda8,
0x95b5, 0x56c, 0x12ae, 0x492f, 0x92e, 0xcc96, 0x1a94, 0x1d4a, 0xada9, 0xb5a, 0x56c, 0x726e, 0x125c, 0xf92d,
0x192a, 0x1a94, 0xdb4a, 0x16aa, 0xad4, 0x955b, 0x4ba, 0x125a, 0x592b, 0x152a, 0xf695, 0xd94, 0x16aa, 0xaab5,
0x9b4, 0x14b6, 0x6a57, 0xa56, 0x1152a, 0x1d2a, 0xd54, 0xd5aa, 0x156a, 0x96c, 0x94ae, 0x14ae, 0xa4c, 0x7d26,
0x1b2a, 0xeb55, 0xad4, 0x12da, 0xa95d, 0x95a, 0x149a, 0x9a4d, 0x1a4a, 0x11aa5, 0x16a8, 0x16d4, 0xd2da,
0x12b6, 0x936, 0x9497, 0x1496, 0x1564b, 0xd4a, 0xda8, 0xd5b4, 0x156c, 0x12ae, 0xa92f, 0x92e, 0xc96, 0x6d4a,
0x1d4a, 0x10d65, 0xb58, 0x156c, 0xb26d, 0x125c, 0x192c, 0x9a95, 0x1a94, 0x1b4a, 0x4b55, 0xad4, 0xf55b,
0x4ba, 0x125a, 0xb92b, 0x152a, 0x1694, 0x96aa, 0x15aa, 0x12ab5, 0x974, 0x14b6, 0xca57, 0xa56, 0x1526,
0x8e95, 0xd54, 0x15aa, 0x49b5, 0x96c, 0xd4ae, 0x149c, 0x1a4c, 0xbd26, 0x1aa6, 0xb54, 0x6d6a, 0x12da,
0x1695d, 0x95a, 0x149a, 0xda4b, 0x1a4a, 0x1aa4, 0xbb54, 0x16b4, 0xada, 0x495b, 0x936, 0xf497, 0x1496,
0x154a, 0xb6a5, 0xda4, 0x15b4, 0x6ab6, 0x126e, 0x1092f, 0x92e, 0xc96, 0xcd4a, 0x1d4a, 0xd64, 0x956c, 0x155c,
0x125c, 0x792e, 0x192c, 0xfa95, 0x1a94, 0x1b4a, 0xab55, 0xad4, 0x14da, 0x8a5d, 0xa5a, 0x1152b, 0x152a,
0x1694, 0xd6aa, 0x15aa, 0xab4, 0x94ba, 0x14b6, 0xa56, 0x7527, 0xd26, 0xee53, 0xd54, 0x15aa, 0xa9b5, 0x96c,
0x14ae, 0x8a4e, 0x1a4c, 0x11d26, 0x1aa4, 0x1b54, 0xcd6a, 0xada, 0x95c, 0x949d, 0x149a, 0x1a2a, 0x5b25,
0x1aa4, 0xfb52, 0x16b4, 0xaba, 0xa95b, 0x936, 0x1496, 0x9a4b, 0x154a, 0x136a5, 0xda4, 0x15ac};
private static final int[] SOLAR_1_1 = {1887, 0xec04c, 0xec23f, 0xec435, 0xec649, 0xec83e, 0xeca51, 0xecc46, 0xece3a,
0xed04d, 0xed242, 0xed436, 0xed64a, 0xed83f, 0xeda53, 0xedc48, 0xede3d, 0xee050, 0xee244, 0xee439, 0xee64d,
0xee842, 0xeea36, 0xeec4a, 0xeee3e, 0xef052, 0xef246, 0xef43a, 0xef64e, 0xef843, 0xefa37, 0xefc4b, 0xefe41,
0xf0054, 0xf0248, 0xf043c, 0xf0650, 0xf0845, 0xf0a38, 0xf0c4d, 0xf0e42, 0xf1037, 0xf124a, 0xf143e, 0xf1651,
0xf1846, 0xf1a3a, 0xf1c4e, 0xf1e44, 0xf2038, 0xf224b, 0xf243f, 0xf2653, 0xf2848, 0xf2a3b, 0xf2c4f, 0xf2e45,
0xf3039, 0xf324d, 0xf3442, 0xf3636, 0xf384a, 0xf3a3d, 0xf3c51, 0xf3e46, 0xf403b, 0xf424e, 0xf4443, 0xf4638,
0xf484c, 0xf4a3f, 0xf4c52, 0xf4e48, 0xf503c, 0xf524f, 0xf5445, 0xf5639, 0xf584d, 0xf5a42, 0xf5c35, 0xf5e49,
0xf603e, 0xf6251, 0xf6446, 0xf663b, 0xf684f, 0xf6a43, 0xf6c37, 0xf6e4b, 0xf703f, 0xf7252, 0xf7447, 0xf763c,
0xf7850, 0xf7a45, 0xf7c39, 0xf7e4d, 0xf8042, 0xf8254, 0xf8449, 0xf863d, 0xf8851, 0xf8a46, 0xf8c3b, 0xf8e4f,
0xf9044, 0xf9237, 0xf944a, 0xf963f, 0xf9853, 0xf9a47, 0xf9c3c, 0xf9e50, 0xfa045, 0xfa238, 0xfa44c, 0xfa641,
0xfa836, 0xfaa49, 0xfac3d, 0xfae52, 0xfb047, 0xfb23a, 0xfb44e, 0xfb643, 0xfb837, 0xfba4a, 0xfbc3f, 0xfbe53,
0xfc048, 0xfc23c, 0xfc450, 0xfc645, 0xfc839, 0xfca4c, 0xfcc41, 0xfce36, 0xfd04a, 0xfd23d, 0xfd451, 0xfd646,
0xfd83a, 0xfda4d, 0xfdc43, 0xfde37, 0xfe04b, 0xfe23f, 0xfe453, 0xfe648, 0xfe83c, 0xfea4f, 0xfec44, 0xfee38,
0xff04c, 0xff241, 0xff436, 0xff64a, 0xff83e, 0xffa51, 0xffc46, 0xffe3a, 0x10004e, 0x100242, 0x100437,
0x10064b, 0x100841, 0x100a53, 0x100c48, 0x100e3c, 0x10104f, 0x101244, 0x101438, 0x10164c, 0x101842,
0x101a35, 0x101c49, 0x101e3d, 0x102051, 0x102245, 0x10243a, 0x10264e, 0x102843, 0x102a37, 0x102c4b,
0x102e3f, 0x103053, 0x103247, 0x10343b, 0x10364f, 0x103845, 0x103a38, 0x103c4c, 0x103e42, 0x104036,
0x104249, 0x10443d, 0x104651, 0x104846, 0x104a3a, 0x104c4e, 0x104e43, 0x105038, 0x10524a, 0x10543e,
0x105652, 0x105847, 0x105a3b, 0x105c4f, 0x105e45, 0x106039, 0x10624c, 0x106441, 0x106635, 0x106849,
0x106a3d, 0x106c51, 0x106e47, 0x10703c, 0x10724f, 0x107444, 0x107638, 0x10784c, 0x107a3f, 0x107c53,
0x107e48};
private static int getBitInt(final int data, final int length, final int shift) {
return (data & (((1 << length) - 1) << shift)) >> shift;
}
/**
*
*
* @param lunarYear
* @return
*/
public static String lunarYear2GanZhi(final int lunarYear) {
final String[] tianGan = {"", "", "", "", "", "", "", "", "", ""};
final String[] diZhi = {"", "", "", "", "", "", "", "", "", "", "", ""};
return tianGan[(lunarYear - 4) % 10] + diZhi[(lunarYear - 4) % 12] + "";
}
/**
*
*
* @param lunar
* @return
*/
public static Solar lunar2Solar(final Lunar lunar) {
int days = LUNAR_MONTH_DAYS[lunar.lunarYear - LUNAR_MONTH_DAYS[0]];
int leap = getBitInt(days, 4, 13);
int offset = 0;
int loopend = leap;
if (!lunar.isLeap) {
if (lunar.lunarMonth <= leap || leap == 0) {
loopend = lunar.lunarMonth - 1;
} else {
loopend = lunar.lunarMonth;
}
}
for (int i = 0; i < loopend; i++) {
offset += getBitInt(days, 1, 12 - i) == 1 ? 30 : 29;
}
offset += lunar.lunarDay;
int solar11 = SOLAR_1_1[lunar.lunarYear - SOLAR_1_1[0]];
int y = getBitInt(solar11, 12, 9);
int m = getBitInt(solar11, 4, 5);
int d = getBitInt(solar11, 5, 0);
return solarFromInt(solarToInt(y, m, d) + offset - 1);
}
/**
*
*
* @param solar
* @return
*/
public static Lunar solar2Lunar(final Solar solar) {
Lunar lunar = new Lunar();
int index = solar.solarYear - SOLAR_1_1[0];
int data = (solar.solarYear << 9) | (solar.solarMonth << 5) | (solar.solarDay);
int solar11 = 0;
if (SOLAR_1_1[index] > data) {
index--;
}
solar11 = SOLAR_1_1[index];
int y = getBitInt(solar11, 12, 9);
int m = getBitInt(solar11, 4, 5);
int d = getBitInt(solar11, 5, 0);
long offset = solarToInt(solar.solarYear, solar.solarMonth, solar.solarDay) - solarToInt(y, m, d);
int days = LUNAR_MONTH_DAYS[index];
int leap = getBitInt(days, 4, 13);
int lunarY = index + SOLAR_1_1[0];
int lunarM = 1;
int lunarD = 1;
offset += 1;
for (int i = 0; i < 13; i++) {
int dm = getBitInt(days, 1, 12 - i) == 1 ? 30 : 29;
if (offset > dm) {
lunarM++;
offset -= dm;
} else {
break;
}
}
lunarD = (int) (offset);
lunar.lunarYear = lunarY;
lunar.lunarMonth = lunarM;
lunar.isLeap = false;
if (leap != 0 && lunarM > leap) {
lunar.lunarMonth = lunarM - 1;
if (lunarM == leap + 1) {
lunar.isLeap = true;
}
}
lunar.lunarDay = lunarD;
return lunar;
}
private static Solar solarFromInt(final long g) {
long y = (10000 * g + 14780) / 3652425;
long ddd = g - (365 * y + y / 4 - y / 100 + y / 400);
if (ddd < 0) {
y--;
ddd = g - (365 * y + y / 4 - y / 100 + y / 400);
}
long mi = (100 * ddd + 52) / 3060;
long mm = (mi + 2) % 12 + 1;
y = y + (mi + 2) / 12;
long dd = ddd - (mi * 306 + 5) / 10 + 1;
Solar solar = new Solar();
solar.solarYear = (int) y;
solar.solarMonth = (int) mm;
solar.solarDay = (int) dd;
return solar;
}
private static long solarToInt(int y, int m, final int d) {
m = (m + 9) % 12;
y = y - m / 10;
return 365 * y + y / 4 - y / 100 + y / 400 + (m * 306 + 5) / 10 + (d - 1);
}
public static class Lunar {
public int lunarYear;
public int lunarMonth;
public int lunarDay;
public boolean isLeap;
Lunar() {
}
public Lunar(int lunarYear, int lunarMonth, int lunarDay, boolean isLeap) {
this.lunarYear = lunarYear;
this.lunarMonth = lunarMonth;
this.lunarDay = lunarDay;
this.isLeap = isLeap;
}
@Override
public String toString() {
return "" + lunarYear + ", " + lunarMonth + ", " + lunarDay + ", " + isLeap;
}
}
public static class Solar {
public int solarYear;
public int solarMonth;
public int solarDay;
Solar() {
}
public Solar(int solarYear, int solarMonth, int solarDay) {
this.solarYear = solarYear;
this.solarMonth = solarMonth;
this.solarDay = solarDay;
}
@Override
public String toString() {
return "" + solarYear + ", " + solarMonth + ", " + solarDay;
}
}
}
``` | /content/code_sandbox/lib/subutil/src/main/java/com/blankj/subutil/util/LunarUtils.java | java | 2016-07-30T18:18:32 | 2024-08-16T01:37:59 | AndroidUtilCode | Blankj/AndroidUtilCode | 33,178 | 4,422 |
```java
package com.blankj.subutil.util;
import android.content.Context;
import android.content.res.Resources;
import android.telephony.TelephonyManager;
import com.blankj.utilcode.util.Utils;
import java.util.HashMap;
/**
* <pre>
* author: Blankj
* blog : path_to_url
* time : 2019/06/11
* desc : utils about country code
* </pre>
*/
public class CountryUtils {
private static HashMap<String, String> countryCodeMap;
/**
* Return the country code by sim card.
*
* @param defaultValue The default value.
* @return the country code
*/
public static String getCountryCodeBySim(String defaultValue) {
String code = getCountryCodeFromMap().get(getCountryBySim());
if (code == null) {
return defaultValue;
}
return code;
}
/**
* Return the country code by system language.
*
* @param defaultValue The default value.
* @return the country code
*/
public static String getCountryCodeByLanguage(String defaultValue) {
String code = getCountryCodeFromMap().get(getCountryByLanguage());
if (code == null) {
return defaultValue;
}
return code;
}
/**
* Return the country by sim card.
*
* @return the country
*/
public static String getCountryBySim() {
TelephonyManager manager = (TelephonyManager) Utils.getApp().getSystemService(Context.TELEPHONY_SERVICE);
if (manager != null) {
return manager.getSimCountryIso().toUpperCase();
}
return "";
}
/**
* Return the country by system language.
*
* @return the country
*/
public static String getCountryByLanguage() {
return Resources.getSystem().getConfiguration().locale.getCountry();
}
private static HashMap<String, String> getCountryCodeFromMap() {
if (countryCodeMap == null) {
countryCodeMap = new HashMap<>(256);
countryCodeMap.put("AL", "+355");
countryCodeMap.put("DZ", "+213");
countryCodeMap.put("AF", "+93");
countryCodeMap.put("AR", "+54");
countryCodeMap.put("AE", "+971");
countryCodeMap.put("AW", "+297");
countryCodeMap.put("OM", "+968");
countryCodeMap.put("AZ", "+994");
countryCodeMap.put("AC", "+247");
countryCodeMap.put("EG", "+20");
countryCodeMap.put("ET", "+251");
countryCodeMap.put("IE", "+353");
countryCodeMap.put("EE", "+372");
countryCodeMap.put("AD", "+376");
countryCodeMap.put("AO", "+244");
countryCodeMap.put("AI", "+1");
countryCodeMap.put("AG", "+1");
countryCodeMap.put("AT", "+43");
countryCodeMap.put("AX", "+358");
countryCodeMap.put("AU", "+61");
countryCodeMap.put("BB", "+1");
countryCodeMap.put("PG", "+675");
countryCodeMap.put("BS", "+1");
countryCodeMap.put("PK", "+92");
countryCodeMap.put("PY", "+595");
countryCodeMap.put("PS", "+970");
countryCodeMap.put("BH", "+973");
countryCodeMap.put("PA", "+507");
countryCodeMap.put("BR", "+55");
countryCodeMap.put("BY", "+375");
countryCodeMap.put("BM", "+1");
countryCodeMap.put("BG", "+359");
countryCodeMap.put("MP", "+1");
countryCodeMap.put("BJ", "+229");
countryCodeMap.put("BE", "+32");
countryCodeMap.put("IS", "+354");
countryCodeMap.put("PR", "+1");
countryCodeMap.put("PL", "+48");
countryCodeMap.put("BA", "+387");
countryCodeMap.put("BO", "+591");
countryCodeMap.put("BZ", "+501");
countryCodeMap.put("BW", "+267");
countryCodeMap.put("BT", "+975");
countryCodeMap.put("BF", "+226");
countryCodeMap.put("BI", "+257");
countryCodeMap.put("KP", "+850");
countryCodeMap.put("GQ", "+240");
countryCodeMap.put("DK", "+45");
countryCodeMap.put("DE", "+49");
countryCodeMap.put("TL", "+670");
countryCodeMap.put("TG", "+228");
countryCodeMap.put("DO", "+1");
countryCodeMap.put("DM", "+1");
countryCodeMap.put("RU", "+7");
countryCodeMap.put("EC", "+593");
countryCodeMap.put("ER", "+291");
countryCodeMap.put("FR", "+33");
countryCodeMap.put("FO", "+298");
countryCodeMap.put("PF", "+689");
countryCodeMap.put("GF", "+594");
countryCodeMap.put("VA", "+39");
countryCodeMap.put("PH", "+63");
countryCodeMap.put("FJ", "+679");
countryCodeMap.put("FI", "+358");
countryCodeMap.put("CV", "+238");
countryCodeMap.put("FK", "+500");
countryCodeMap.put("GM", "+220");
countryCodeMap.put("CG", "+242");
countryCodeMap.put("CD", "+243");
countryCodeMap.put("CO", "+57");
countryCodeMap.put("CR", "+506");
countryCodeMap.put("GG", "+44");
countryCodeMap.put("GD", "+1");
countryCodeMap.put("GL", "+299");
countryCodeMap.put("GE", "+995");
countryCodeMap.put("CU", "+53");
countryCodeMap.put("GP", "+590");
countryCodeMap.put("GU", "+1");
countryCodeMap.put("GY", "+592");
countryCodeMap.put("KZ", "+7");
countryCodeMap.put("HT", "+509");
countryCodeMap.put("KR", "+82");
countryCodeMap.put("NL", "+31");
countryCodeMap.put("BQ", "+599");
countryCodeMap.put("SX", "+1");
countryCodeMap.put("ME", "+382");
countryCodeMap.put("HN", "+504");
countryCodeMap.put("KI", "+686");
countryCodeMap.put("DJ", "+253");
countryCodeMap.put("KG", "+996");
countryCodeMap.put("GN", "+224");
countryCodeMap.put("GW", "+245");
countryCodeMap.put("CA", "+1");
countryCodeMap.put("GH", "+233");
countryCodeMap.put("GA", "+241");
countryCodeMap.put("KH", "+855");
countryCodeMap.put("CZ", "+420");
countryCodeMap.put("ZW", "+263");
countryCodeMap.put("CM", "+237");
countryCodeMap.put("QA", "+974");
countryCodeMap.put("KY", "+1");
countryCodeMap.put("CC", "+61");
countryCodeMap.put("KM", "+269");
countryCodeMap.put("XK", "+383");
countryCodeMap.put("CI", "+225");
countryCodeMap.put("KW", "+965");
countryCodeMap.put("HR", "+385");
countryCodeMap.put("KE", "+254");
countryCodeMap.put("CK", "+682");
countryCodeMap.put("CW", "+599");
countryCodeMap.put("LV", "+371");
countryCodeMap.put("LS", "+266");
countryCodeMap.put("LA", "+856");
countryCodeMap.put("LB", "+961");
countryCodeMap.put("LT", "+370");
countryCodeMap.put("LR", "+231");
countryCodeMap.put("LY", "+218");
countryCodeMap.put("LI", "+423");
countryCodeMap.put("RE", "+262");
countryCodeMap.put("LU", "+352");
countryCodeMap.put("RW", "+250");
countryCodeMap.put("RO", "+40");
countryCodeMap.put("MG", "+261");
countryCodeMap.put("IM", "+44");
countryCodeMap.put("MV", "+960");
countryCodeMap.put("MT", "+356");
countryCodeMap.put("MW", "+265");
countryCodeMap.put("MY", "+60");
countryCodeMap.put("ML", "+223");
countryCodeMap.put("MK", "+389");
countryCodeMap.put("MH", "+692");
countryCodeMap.put("MQ", "+596");
countryCodeMap.put("YT", "+262");
countryCodeMap.put("MU", "+230");
countryCodeMap.put("MR", "+222");
countryCodeMap.put("US", "+1");
countryCodeMap.put("AS", "+1");
countryCodeMap.put("VI", "+1");
countryCodeMap.put("MN", "+976");
countryCodeMap.put("MS", "+1");
countryCodeMap.put("BD", "+880");
countryCodeMap.put("PE", "+51");
countryCodeMap.put("FM", "+691");
countryCodeMap.put("MM", "+95");
countryCodeMap.put("MD", "+373");
countryCodeMap.put("MA", "+212");
countryCodeMap.put("MC", "+377");
countryCodeMap.put("MZ", "+258");
countryCodeMap.put("MX", "+52");
countryCodeMap.put("NA", "+264");
countryCodeMap.put("ZA", "+27");
countryCodeMap.put("SS", "+211");
countryCodeMap.put("NR", "+674");
countryCodeMap.put("NI", "+505");
countryCodeMap.put("NP", "+977");
countryCodeMap.put("NE", "+227");
countryCodeMap.put("NG", "+234");
countryCodeMap.put("NU", "+683");
countryCodeMap.put("NO", "+47");
countryCodeMap.put("NF", "+672");
countryCodeMap.put("PW", "+680");
countryCodeMap.put("PT", "+351");
countryCodeMap.put("JP", "+81");
countryCodeMap.put("SE", "+46");
countryCodeMap.put("CH", "+41");
countryCodeMap.put("SV", "+503");
countryCodeMap.put("WS", "+685");
countryCodeMap.put("RS", "+381");
countryCodeMap.put("SL", "+232");
countryCodeMap.put("SN", "+221");
countryCodeMap.put("CY", "+357");
countryCodeMap.put("SC", "+248");
countryCodeMap.put("SA", "+966");
countryCodeMap.put("BL", "+590");
countryCodeMap.put("CX", "+61");
countryCodeMap.put("ST", "+239");
countryCodeMap.put("SH", "+290");
countryCodeMap.put("PN", "+870");
countryCodeMap.put("KN", "+1");
countryCodeMap.put("LC", "+1");
countryCodeMap.put("MF", "+590");
countryCodeMap.put("SM", "+378");
countryCodeMap.put("PM", "+508");
countryCodeMap.put("VC", "+1");
countryCodeMap.put("LK", "+94");
countryCodeMap.put("SK", "+421");
countryCodeMap.put("SI", "+386");
countryCodeMap.put("SJ", "+47");
countryCodeMap.put("SZ", "+268");
countryCodeMap.put("SD", "+249");
countryCodeMap.put("SR", "+597");
countryCodeMap.put("SB", "+677");
countryCodeMap.put("SO", "+252");
countryCodeMap.put("TJ", "+992");
countryCodeMap.put("TH", "+66");
countryCodeMap.put("TZ", "+255");
countryCodeMap.put("TO", "+676");
countryCodeMap.put("TC", "+1");
countryCodeMap.put("TA", "+290");
countryCodeMap.put("TT", "+1");
countryCodeMap.put("TN", "+216");
countryCodeMap.put("TV", "+688");
countryCodeMap.put("TR", "+90");
countryCodeMap.put("TM", "+993");
countryCodeMap.put("TK", "+690");
countryCodeMap.put("WF", "+681");
countryCodeMap.put("VU", "+678");
countryCodeMap.put("GT", "+502");
countryCodeMap.put("VE", "+58");
countryCodeMap.put("BN", "+673");
countryCodeMap.put("UG", "+256");
countryCodeMap.put("UA", "+380");
countryCodeMap.put("UY", "+598");
countryCodeMap.put("UZ", "+998");
countryCodeMap.put("GR", "+30");
countryCodeMap.put("ES", "+34");
countryCodeMap.put("EH", "+212");
countryCodeMap.put("SG", "+65");
countryCodeMap.put("NC", "+687");
countryCodeMap.put("NZ", "+64");
countryCodeMap.put("HU", "+36");
countryCodeMap.put("SY", "+963");
countryCodeMap.put("JM", "+1");
countryCodeMap.put("AM", "+374");
countryCodeMap.put("YE", "+967");
countryCodeMap.put("IQ", "+964");
countryCodeMap.put("UM", "+1");
countryCodeMap.put("IR", "+98");
countryCodeMap.put("IL", "+972");
countryCodeMap.put("IT", "+39");
countryCodeMap.put("IN", "+91");
countryCodeMap.put("ID", "+62");
countryCodeMap.put("GB", "+44");
countryCodeMap.put("VG", "+1");
countryCodeMap.put("IO", "+246");
countryCodeMap.put("JO", "+962");
countryCodeMap.put("VN", "+84");
countryCodeMap.put("ZM", "+260");
countryCodeMap.put("JE", "+44");
countryCodeMap.put("TD", "+235");
countryCodeMap.put("GI", "+350");
countryCodeMap.put("CL", "+56");
countryCodeMap.put("CF", "+236");
countryCodeMap.put("CN", "+86");
countryCodeMap.put("MO", "+853");
countryCodeMap.put("TW", "+886");
countryCodeMap.put("HK", "+852");
}
return countryCodeMap;
}
}
``` | /content/code_sandbox/lib/subutil/src/main/java/com/blankj/subutil/util/CountryUtils.java | java | 2016-07-30T18:18:32 | 2024-08-16T01:37:59 | AndroidUtilCode | Blankj/AndroidUtilCode | 33,178 | 2,923 |
```java
//package com.blankj.subutil.util;
//
//import android.content.Context;
//import android.graphics.drawable.PictureDrawable;
//import android.widget.ImageView;
//
//import com.blankj.subutil.R;
//import com.blankj.subutil.util.image.GlideApp;
//import com.bumptech.glide.Glide;
//import com.bumptech.glide.load.engine.DiskCacheStrategy;
//import com.bumptech.glide.request.RequestOptions;
//
///**
// * <pre>
// * author: Blankj
// * blog : path_to_url
// * time : 2018/05/16
// * desc :
// * </pre>
// */
//public final class GlideUtils {
//
//
//
// public static void setCircleImage(Context context, String url, ImageView view) {
// RequestOptions requestOptions = new RequestOptions()
// .placeholder(R.drawable.def_img_round_holder)
// .error(R.drawable.def_img_round_error)
// .diskCacheStrategy(DiskCacheStrategy.AUTOMATIC)
// .circleCrop().dontAnimate();
// Glide.with(context).load(url).apply(requestOptions).into(view);
// }
//
// public static void setImage(Context context, String url, ImageView view) {
// if (url.endsWith(".svg") || url.endsWith(".SVG")) {
// setSvgImage(context, url, view);
// return;
// }
//
// RequestOptions requestOptions = new RequestOptions().placeholder(R.drawable.def_img)
// .error(R.drawable.def_img).diskCacheStrategy(DiskCacheStrategy.AUTOMATIC).dontAnimate();
// Glide.with(context).load(url).apply(requestOptions).into(view);
// }
//
// private static void setSvgImage(Context context, String url, ImageView view) {
// GlideApp.with(context)
// .as(PictureDrawable.class)
// .error(R.drawable.def_img).load(url).into(view);
// }
//}
``` | /content/code_sandbox/lib/subutil/src/main/java/com/blankj/subutil/util/GlideUtils.java | java | 2016-07-30T18:18:32 | 2024-08-16T01:37:59 | AndroidUtilCode | Blankj/AndroidUtilCode | 33,178 | 397 |
```java
package com.blankj.subutil.util;
import java.io.DataOutputStream;
import java.io.IOException;
import java.io.InputStream;
import java.net.HttpURLConnection;
import java.net.URL;
import java.util.Scanner;
/**
* <pre>
* author: MilkZS
* time : 2019/01/09
* desc : https
* </pre>
*/
public final class HttpsUtil {
private static final int CONNECT_TIMEOUT_TIME = 15000;
private static final int READ_TIMEOUT_TIME = 19000;
/**
* POST + JSON
*
* @param data send data
* @param url target url
* @return data receive from server
* @author MilkZS
*/
public static String postJson(String data, String url) {
return doHttpAction(data, true, true, url);
}
/**
* POST + FORM
*
* @param data send data
* @param url target url
* @return data receive from serv
* @author MilkZS
*/
public static String postForm(String data, String url) {
return doHttpAction(data, false, true, url);
}
/**
* GET + JSON
*
* @param data send data
* @param url target url
* @return data receive from server
* @author MilkZS
*/
public static String getJson(String data, String url) {
return doHttpAction(data, true, false, url);
}
/**
* GET + FORM
*
* @param data send data
* @param url target url
* @return data receive from server
* @author MilkZS
*/
public static String getForm(String data, String url) {
return doHttpAction(data, false, false, url);
}
private static String doHttpAction(String data, boolean json, boolean post, String url) {
HttpURLConnection connection = null;
DataOutputStream os = null;
InputStream is = null;
try {
URL sUrl = new URL(url);
connection = (HttpURLConnection) sUrl.openConnection();
connection.setConnectTimeout(CONNECT_TIMEOUT_TIME);
connection.setReadTimeout(READ_TIMEOUT_TIME);
if (post) {
connection.setRequestMethod("POST");
} else {
connection.setRequestMethod("GET");
}
//
connection.setDoInput(true);
connection.setDoOutput(true);
//
connection.setUseCaches(false);
// true
// falsehttp replyurl
connection.setInstanceFollowRedirects(true);
//
if (json) {
connection.setRequestProperty("Content-Type", "application/json");
} else {
connection.setRequestProperty("Content-Type", "application/x-www-form-urlencoded");
connection.setRequestProperty("Content-Length", data.length() + "");
}
connection.connect();
os = new DataOutputStream(connection.getOutputStream());
os.write(data.getBytes(), 0, data.getBytes().length);
os.flush();
os.close();
is = connection.getInputStream();
Scanner scan = new Scanner(is);
scan.useDelimiter("\\A");
if (scan.hasNext()) return scan.next();
} catch (Exception e) {
e.printStackTrace();
} finally {
if (connection != null) connection.disconnect();
if (os != null) {
try {
os.close();
} catch (IOException e) {
e.printStackTrace();
}
}
if (is != null) {
try {
is.close();
} catch (IOException e) {
e.printStackTrace();
}
}
}
return null;
}
}
``` | /content/code_sandbox/lib/subutil/src/main/java/com/blankj/subutil/util/HttpsUtil.java | java | 2016-07-30T18:18:32 | 2024-08-16T01:37:59 | AndroidUtilCode | Blankj/AndroidUtilCode | 33,178 | 782 |
```java
package com.blankj.subutil.util;
import android.content.Intent;
import android.content.pm.PackageManager;
import android.content.pm.ResolveInfo;
import android.net.Uri;
import android.util.Log;
import com.blankj.utilcode.util.AppUtils;
import com.blankj.utilcode.util.RomUtils;
import com.blankj.utilcode.util.Utils;
import java.util.List;
/**
* <pre>
* author: Blankj
* blog : path_to_url
* time : 2019/05/20
* desc : utils about app store
* </pre>
*/
public final class AppStoreUtils {
private static final String TAG = "AppStoreUtils";
private static final String GOOGLE_PLAY_APP_STORE_PACKAGE_NAME = "com.android.vending";
/**
* Intent
*
* @return Intent
*/
public static Intent getAppStoreIntent() {
return getAppStoreIntent(Utils.getApp().getPackageName(), false);
}
/**
* Intent
*
* @param isIncludeGooglePlayStore Google Play
* @return Intent
*/
public static Intent getAppStoreIntent(boolean isIncludeGooglePlayStore) {
return getAppStoreIntent(Utils.getApp().getPackageName(), isIncludeGooglePlayStore);
}
/**
* Intent
*
* @param packageName
* @return Intent
*/
public static Intent getAppStoreIntent(final String packageName) {
return getAppStoreIntent(packageName, false);
}
/**
* Intent
* <p></p>
*
* @param packageName
* @param isIncludeGooglePlayStore Google Play
* @return Intent
*/
public static Intent getAppStoreIntent(final String packageName, boolean isIncludeGooglePlayStore) {
if (RomUtils.isSamsung()) {//
Intent samsungAppStoreIntent = getSamsungAppStoreIntent(packageName);
if (samsungAppStoreIntent != null) return samsungAppStoreIntent;
}
if (RomUtils.isLeeco()) {//
Intent leecoAppStoreIntent = getLeecoAppStoreIntent(packageName);
if (leecoAppStoreIntent != null) return leecoAppStoreIntent;
}
Uri uri = Uri.parse("market://details?id=" + packageName);
Intent intent = new Intent();
intent.setData(uri);
intent.addFlags(Intent.FLAG_ACTIVITY_NEW_TASK);
List<ResolveInfo> resolveInfos = Utils.getApp().getPackageManager()
.queryIntentActivities(intent, PackageManager.MATCH_DEFAULT_ONLY);
if (resolveInfos == null || resolveInfos.size() == 0) {
Log.e(TAG, "No app store!");
return null;
}
Intent googleIntent = null;
for (ResolveInfo resolveInfo : resolveInfos) {
String pkgName = resolveInfo.activityInfo.packageName;
if (!GOOGLE_PLAY_APP_STORE_PACKAGE_NAME.equals(pkgName)) {
if (AppUtils.isAppSystem(pkgName)) {
intent.setPackage(pkgName);
return intent;
}
} else {
intent.setPackage(GOOGLE_PLAY_APP_STORE_PACKAGE_NAME);
googleIntent = intent;
}
}
if (isIncludeGooglePlayStore && googleIntent != null) {
return googleIntent;
}
intent.setPackage(resolveInfos.get(0).activityInfo.packageName);
return intent;
}
private static Intent getSamsungAppStoreIntent(final String packageName) {
Intent intent = new Intent();
intent.setClassName("com.sec.android.app.samsungapps", "com.sec.android.app.samsungapps.Main");
intent.setData(Uri.parse("path_to_url" + packageName));
intent.addFlags(Intent.FLAG_ACTIVITY_NEW_TASK);
if (getAvailableIntentSize(intent) > 0) {
return intent;
}
return null;
}
private static Intent getLeecoAppStoreIntent(final String packageName) {
Intent intent = new Intent();
intent.setClassName("com.letv.app.appstore", "com.letv.app.appstore.appmodule.details.DetailsActivity");
intent.setAction("com.letv.app.appstore.appdetailactivity");
intent.putExtra("packageName", packageName);
intent.addFlags(Intent.FLAG_ACTIVITY_NEW_TASK);
if (getAvailableIntentSize(intent) > 0) {
return intent;
}
return null;
}
private static int getAvailableIntentSize(final Intent intent) {
return Utils.getApp().getPackageManager()
.queryIntentActivities(intent, PackageManager.MATCH_DEFAULT_ONLY)
.size();
}
}
``` | /content/code_sandbox/lib/subutil/src/main/java/com/blankj/subutil/util/AppStoreUtils.java | java | 2016-07-30T18:18:32 | 2024-08-16T01:37:59 | AndroidUtilCode | Blankj/AndroidUtilCode | 33,178 | 947 |
```java
package com.blankj.subutil.util.http;
import com.google.gson.Gson;
import java.io.File;
import java.io.InputStream;
import java.lang.reflect.Type;
import java.util.List;
import java.util.Map;
/**
* <pre>
* author: Blankj
* blog : path_to_url
* time : 2019/02/17
* </pre>
*/
public class Response {
private Map<String, List<String>> mHeaders;
private InputStream mBody;
public Response(Map<String, List<String>> headers, InputStream body) {
mHeaders = headers;
mBody = body;
}
public Map<String, List<String>> getHeaders() {
return mHeaders;
}
public InputStream getBody() {
return mBody;
}
public String getString() {
return getString("utf-8");
}
public String getString(final String charset) {
return HttpUtils.is2String(mBody, charset);
}
public <T> T getJson(final Type type) {
return getJson(type, "utf-8");
}
public <T> T getJson(final Type type, final String charset) {
return new Gson().fromJson(getString(charset), type);
}
public boolean downloadFile(final File file) {
return HttpUtils.writeFileFromIS(file, mBody);
}
}
``` | /content/code_sandbox/lib/subutil/src/main/java/com/blankj/subutil/util/http/Response.java | java | 2016-07-30T18:18:32 | 2024-08-16T01:37:59 | AndroidUtilCode | Blankj/AndroidUtilCode | 33,178 | 286 |
```java
package com.blankj.subutil.util.http;
/**
* <pre>
* author: Blankj
* blog : path_to_url
* time : 2019/02/17
* </pre>
*/
public abstract class ResponseCallback {
public abstract void onResponse(Response response);
public abstract void onFailed(Exception e);
}
``` | /content/code_sandbox/lib/subutil/src/main/java/com/blankj/subutil/util/http/ResponseCallback.java | java | 2016-07-30T18:18:32 | 2024-08-16T01:37:59 | AndroidUtilCode | Blankj/AndroidUtilCode | 33,178 | 73 |
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