text stringlengths 9 39.2M | dir stringlengths 26 295 | lang stringclasses 185
values | created_date timestamp[us] | updated_date timestamp[us] | repo_name stringlengths 1 97 | repo_full_name stringlengths 7 106 | star int64 1k 183k | len_tokens int64 1 13.8M |
|---|---|---|---|---|---|---|---|---|
```c
/*
* 86Box A hypervisor and IBM PC system emulator that specializes in
* running old operating systems and software designed for IBM
* PC systems and compatibles from 1981 through fairly recent
* system designs based on the PCI bus.
*
* This file is part of the 86Box distribution.
*
* Implementation of the NEC uPD-765 and compatible floppy disk
* controller.
*
*
*
* Authors: Sarah Walker, <path_to_url
* Miran Grca, <mgrca8@gmail.com>
*
*/
#include <stdio.h>
#include <stdint.h>
#include <stdlib.h>
#include <string.h>
#include <stdarg.h>
#include <wchar.h>
#define HAVE_STDARG_H
#include <86box/86box.h>
#include <86box/device.h>
#include "cpu.h"
#include <86box/machine.h>
#include <86box/io.h>
#include <86box/dma.h>
#include <86box/pic.h>
#include <86box/timer.h>
#include <86box/ui.h>
#include <86box/fdd.h>
#include <86box/fdc.h>
#include <86box/fdc_ext.h>
#include <86box/plat_fallthrough.h>
#include <86box/plat_unused.h>
#include <86box/fifo.h>
extern uint64_t motoron[FDD_NUM];
const uint8_t command_has_drivesel[32] = {
0, 0,
1, /* READ TRACK */
0,
1, /* SENSE DRIVE STATUS */
1, /* WRITE DATA */
1, /* READ DATA */
1, /* RECALIBRATE */
0,
1, /* WRITE DELETED DATA */
1, /* READ ID */
0,
1, /* READ DELETED DATA */
1, /* FORMAT TRACK */
0,
1, /* SEEK, RELATIVE SEEK */
0,
1, /* SCAN EQUAL */
0, 0, 0, 0,
1, /* VERIFY */
0, 0,
1, /* SCAN LOW OR EQUAL */
0, 0, 0,
1, /* SCAN HIGH OR EQUAL */
0, 0
};
static uint8_t current_drive = 0;
static void fdc_callback(void *priv);
int lastbyte = 0;
int floppymodified[4];
int floppyrate[4];
int fdc_current[FDC_MAX] = { 0, 0 };
#ifdef ENABLE_FDC_LOG
int fdc_do_log = ENABLE_FDC_LOG;
static void
fdc_log(const char *fmt, ...)
{
va_list ap;
if (fdc_do_log) {
va_start(ap, fmt);
pclog_ex(fmt, ap);
va_end(ap);
}
}
#else
# define fdc_log(fmt, ...)
#endif
typedef const struct {
const device_t *device;
} fdc_cards_t;
static fdc_cards_t fdc_cards[] = {
// clang-format off
{ &device_none },
{ &device_internal },
{ &fdc_xt_device },
{ &fdc_at_device },
{ &fdc_b215_device },
{ &fdc_pii151b_device },
{ &fdc_pii158b_device },
{ &fdc_monster_device },
{ NULL }
// clang-format on
};
int
fdc_card_available(int card)
{
if (fdc_cards[card].device)
return (device_available(fdc_cards[card].device));
return 1;
}
const device_t *
fdc_card_getdevice(int card)
{
return (fdc_cards[card].device);
}
int
fdc_card_has_config(int card)
{
if (!fdc_cards[card].device)
return 0;
return (device_has_config(fdc_cards[card].device) ? 1 : 0);
}
const char *
fdc_card_get_internal_name(int card)
{
return device_get_internal_name(fdc_cards[card].device);
}
int
fdc_card_get_from_internal_name(char *s)
{
int c = 0;
while (fdc_cards[c].device != NULL) {
if (!strcmp(fdc_cards[c].device->internal_name, s))
return c;
c++;
}
return 0;
}
void
fdc_card_init(void)
{
if ((fdc_current[0] > FDC_INTERNAL) && fdc_cards[fdc_current[0]].device)
device_add_inst(fdc_cards[fdc_current[0]].device, 0);
}
uint8_t
fdc_get_current_drive(void)
{
return current_drive;
}
void
fdc_ctrl_reset(void *priv)
{
fdc_t *fdc = (fdc_t *) priv;
fdc->stat = 0x80;
fdc->pnum = fdc->ptot = 0;
fdc->st0 = 0;
fdc->lock = 0;
fdc->head = 0;
fdc->step = 0;
fdc->power_down = 0;
if (!(fdc->flags & FDC_FLAG_AT))
fdc->rate = 2;
}
sector_id_t
fdc_get_read_track_sector(fdc_t *fdc)
{
return fdc->read_track_sector;
}
int
fdc_get_compare_condition(fdc_t *fdc)
{
switch (fdc->interrupt) {
default:
case 0x11:
return 0;
case 0x19:
return 1;
case 0x1D:
return 2;
}
}
int
fdc_is_deleted(fdc_t *fdc)
{
return fdc->deleted & 1;
}
int
fdc_is_sk(fdc_t *fdc)
{
return (fdc->deleted & 0x20) ? 1 : 0;
}
void
fdc_set_wrong_am(fdc_t *fdc)
{
fdc->wrong_am = 1;
}
int
fdc_get_drive(fdc_t *fdc)
{
return (int) fdc->drive;
}
int fdc_get_bitcell_period(fdc_t *fdc);
int fdc_get_bit_rate(fdc_t *fdc);
static void fdc_rate(fdc_t *fdc, int drive);
int
fdc_get_perp(fdc_t *fdc)
{
if (!(fdc->flags & FDC_FLAG_AT) || (fdc->flags & FDC_FLAG_PCJR))
return 0;
return (int) fdc->perp;
}
int
fdc_get_gap2(fdc_t *fdc, int drive)
{
int auto_gap2 = 22;
if (!(fdc->flags & FDC_FLAG_AT) || (fdc->flags & FDC_FLAG_PCJR))
return 22;
if (fdc->perp & 3)
return ((fdc->perp & 3) == 3) ? 41 : 22;
else {
auto_gap2 = (fdc_get_bit_rate(fdc) >= 3) ? 41 : 22;
return (fdc->perp & (4 << drive)) ? auto_gap2 : 22;
}
}
int
fdc_get_format_n(fdc_t *fdc)
{
return (int) fdc->format_n;
}
int
fdc_is_mfm(fdc_t *fdc)
{
return fdc->mfm ? 1 : 0;
}
void
fdc_request_next_sector_id(fdc_t *fdc)
{
if ((fdc->flags & FDC_FLAG_PCJR) || !fdc->dma)
fdc->stat = 0xf0;
else {
dma_set_drq(fdc->dma_ch, 1);
fdc->stat = 0x50;
}
}
void
fdc_stop_id_request(fdc_t *fdc)
{
fdc->stat &= 0x7f;
}
int
fdc_get_gap(fdc_t *fdc)
{
return (int) fdc->gap;
}
int
fdc_get_dtl(fdc_t *fdc)
{
return fdc->dtl;
}
int
fdc_get_format_sectors(fdc_t *fdc)
{
return (int) fdc->format_sectors;
}
static void
fdc_int(fdc_t *fdc, int set_fintr)
{
int ienable = 0;
if (!(fdc->flags & FDC_FLAG_PCJR))
ienable = !!(fdc->dor & 8);
if (ienable)
picint(1 << fdc->irq);
if (set_fintr)
fdc->fintr = 1;
fdc_log("fdc_int(%i): fdc->fintr = %i\n", set_fintr, fdc->fintr);
}
static void
fdc_watchdog_poll(void *priv)
{
fdc_t *fdc = (fdc_t *) priv;
fdc->watchdog_count--;
if (fdc->watchdog_count)
timer_advance_u64(&fdc->watchdog_timer, 1000 * TIMER_USEC);
else {
if (fdc->dor & 0x20)
picint(1 << fdc->irq);
}
}
/* fdc->rwc per Winbond W83877F datasheet:
0 = normal;
1 = 500 kbps, 360 rpm;
2 = 500 kbps, 300 rpm;
3 = 250 kbps
Drive is only aware of selected rate and densel, so on real hardware, the rate expected by fdc_t and the rate actually being
processed by drive can mismatch, in which case the fdc_t won't receive the correct data.
*/
void
fdc_update_rates(fdc_t *fdc)
{
fdc_rate(fdc, 0);
fdc_rate(fdc, 1);
fdc_rate(fdc, 2);
fdc_rate(fdc, 3);
}
void
fdc_set_power_down(fdc_t *fdc, uint8_t power_down)
{
fdc->power_down = power_down;
}
void
fdc_update_max_track(fdc_t *fdc, int max_track)
{
fdc->max_track = max_track;
}
void
fdc_update_enh_mode(fdc_t *fdc, int enh_mode)
{
fdc->enh_mode = !!enh_mode;
fdc_update_rates(fdc);
}
int
fdc_get_rwc(fdc_t *fdc, int drive)
{
return fdc->rwc[drive];
}
void
fdc_update_rwc(fdc_t *fdc, int drive, int rwc)
{
fdc_log("FDD %c: New RWC is %i\n", 0x41 + drive, rwc);
fdc->rwc[drive] = rwc;
fdc_rate(fdc, drive);
}
int
fdc_get_boot_drive(fdc_t *fdc)
{
return fdc->boot_drive;
}
void
fdc_update_boot_drive(fdc_t *fdc, int boot_drive)
{
fdc->boot_drive = boot_drive;
}
void
fdc_update_densel_polarity(fdc_t *fdc, int densel_polarity)
{
fdc_log("FDC: New DENSEL polarity is %i\n", densel_polarity);
fdc->densel_polarity = densel_polarity;
fdc_update_rates(fdc);
}
uint8_t
fdc_get_densel_polarity(fdc_t *fdc)
{
return fdc->densel_polarity;
}
void
fdc_update_densel_force(fdc_t *fdc, int densel_force)
{
fdc_log("FDC: New DENSEL force is %i\n", densel_force);
fdc->densel_force = densel_force;
fdc_update_rates(fdc);
}
void
fdc_update_drvrate(fdc_t *fdc, int drive, int drvrate)
{
fdc_log("FDD %c: New drive rate is %i\n", 0x41 + drive, drvrate);
fdc->drvrate[drive] = drvrate;
fdc_rate(fdc, drive);
}
void
fdc_update_drv2en(fdc_t *fdc, int drv2en)
{
fdc->drv2en = !!drv2en;
}
void
fdc_update_rate(fdc_t *fdc, int drive)
{
if (((fdc->rwc[drive] == 1) || (fdc->rwc[drive] == 2)) && fdc->enh_mode)
fdc->bit_rate = 500;
else if ((fdc->rwc[drive] == 3) && fdc->enh_mode)
fdc->bit_rate = 250;
else switch (fdc->rate) {
default:
break;
case 0: /*High density*/
fdc->bit_rate = 500;
break;
case 1: /*Double density (360 rpm)*/
switch (fdc->drvrate[drive]) {
default:
break;
case 0:
fdc->bit_rate = 300;
break;
case 1:
fdc->bit_rate = 500;
break;
case 2:
fdc->bit_rate = 2000;
break;
}
break;
case 2: /*Double density*/
fdc->bit_rate = 250;
break;
case 3: /*Extended density*/
fdc->bit_rate = 1000;
break;
}
fdc->bitcell_period = (1000000 / fdc->bit_rate) * 2; /*Bitcell period in ns*/
}
int
fdc_get_bit_rate(fdc_t *fdc)
{
switch (fdc->bit_rate) {
case 500:
return 0;
case 300:
return 1;
case 2000:
return 1 | 4;
case 250:
return 2;
case 1000:
return 3;
default:
break;
}
return 2;
}
int
fdc_get_bitcell_period(fdc_t *fdc)
{
return fdc->bitcell_period;
}
static int
fdc_get_densel(fdc_t *fdc, int drive)
{
if (fdc->enh_mode) {
switch (fdc->rwc[drive]) {
case 1:
case 3:
return 0;
case 2:
return 1;
default:
break;
}
}
if (!(fdc->flags & FDC_FLAG_NSC)) {
switch (fdc->densel_force) {
case 2:
return 1;
case 3:
return 0;
default:
break;
}
} else {
switch (fdc->densel_force) {
case 0:
return 0;
case 1:
return 1;
default:
break;
}
}
switch (fdc->rate) {
case 0:
case 3:
return fdc->densel_polarity ? 1 : 0;
case 1:
case 2:
return fdc->densel_polarity ? 0 : 1;
default:
break;
}
return 0;
}
static void
fdc_rate(fdc_t *fdc, int drive)
{
fdc_update_rate(fdc, drive);
fdc_log("FDD %c: [%i] Setting rate: %i, %i, %i (%i, %i, %i)\n", 0x41 + drive, fdc->enh_mode, fdc->drvrate[drive], fdc->rate, fdc_get_densel(fdc, drive), fdc->rwc[drive], fdc->densel_force, fdc->densel_polarity);
fdd_set_densel(fdc_get_densel(fdc, drive));
fdc_log("FDD %c: [%i] Densel: %i\n", 0x41 + drive, fdc->enh_mode, fdc_get_densel(fdc, drive));
}
int
real_drive(fdc_t *fdc, int drive)
{
if (drive < 2)
return drive ^ fdc->swap;
else
return drive;
}
void
fdc_seek(fdc_t *fdc, int drive, int params)
{
fdd_seek(real_drive(fdc, drive), params);
fdc->stat |= (1 << fdc->drive);
}
static void
fdc_bad_command(fdc_t *fdc)
{
fdc->stat = 0x10;
fdc->interrupt = 0xfc;
timer_set_delay_u64(&fdc->timer, 100 * TIMER_USEC);
}
static void
fdc_io_command_phase1(fdc_t *fdc, int out)
{
fifo_reset(fdc->fifo_p);
fdc_rate(fdc, fdc->drive);
fdc->head = fdc->params[2];
fdd_set_head(real_drive(fdc, fdc->drive), (fdc->params[0] & 4) ? 1 : 0);
fdc->sector = fdc->params[3];
fdc->eot[fdc->drive] = fdc->params[5];
fdc->gap = fdc->params[6];
fdc->dtl = fdc->params[7];
fdc->rw_track = fdc->params[1];
if (fdc->config & 0x40) {
if (fdc->rw_track != fdc->pcn[fdc->params[0] & 3]) {
fdc_seek(fdc, fdc->drive, ((int) fdc->rw_track) - ((int) fdc->pcn[fdc->params[0] & 3]));
fdc->pcn[fdc->params[0] & 3] = fdc->rw_track;
}
}
ui_sb_update_icon(SB_FLOPPY | real_drive(fdc, fdc->drive), 1);
fdc->stat = out ? 0x10 : 0x50;
if ((fdc->flags & FDC_FLAG_PCJR) || !fdc->dma)
fdc->stat |= 0x20;
else
dma_set_drq(fdc->dma_ch, 1);
}
static void
fdc_sis(fdc_t *fdc)
{
int drive_num;
fdc->stat = (fdc->stat & 0xf) | 0xd0;
if (fdc->reset_stat) {
drive_num = real_drive(fdc, 4 - fdc->reset_stat);
if ((drive_num < FDD_NUM) && fdd_get_flags(drive_num)) {
fdd_stop(drive_num);
fdd_set_head(drive_num, 0);
fdc->res[9] = 0xc0 | (4 - fdc->reset_stat) | (fdd_get_head(drive_num) ? 4 : 0);
} else
fdc->res[9] = 0xc0 | (4 - fdc->reset_stat);
fdc->reset_stat--;
} else {
if (fdc->fintr) {
fdc->res[9] = (fdc->st0 & ~0x04) | (fdd_get_head(real_drive(fdc, fdc->drive)) ? 4 : 0);
fdc->fintr = 0;
} else {
fdc->res[10] = 0x80;
fdc->paramstogo = 1;
return;
}
}
fdc->res[10] = fdc->pcn[fdc->res[9] & 3];
fdc_log("Sense interrupt status: 2 parameters to go\n");
fdc->paramstogo = 2;
}
static void
fdc_write(uint16_t addr, uint8_t val, void *priv)
{
fdc_t *fdc = (fdc_t *) priv;
int drive;
int i;
int drive_num;
fdc_log("Write FDC %04X %02X\n", addr, val);
cycles -= ISA_CYCLES(8);
if (!fdc->power_down || ((addr & 7) == 2) || ((addr & 7) == 4)) switch (addr & 7) {
case 0:
return;
case 1:
return;
case 2: /*DOR*/
if (fdc->flags & FDC_FLAG_PCJR) {
if ((fdc->dor & 0x40) && !(val & 0x40)) {
timer_set_delay_u64(&fdc->watchdog_timer, 1000 * TIMER_USEC);
fdc->watchdog_count = 1000;
picintc(1 << fdc->irq);
}
if ((val & 0x80) && !(fdc->dor & 0x80)) {
timer_set_delay_u64(&fdc->timer, 8 * TIMER_USEC);
fdc->interrupt = -1;
ui_sb_update_icon(SB_FLOPPY | 0, 0);
fdc_ctrl_reset(fdc);
fdd_changed[0] = 1;
}
if (!fdd_get_flags(0))
val &= 0xfe;
fdd_set_motor_enable(0, val & 0x01);
fdc->st0 &= ~0x07;
fdc->st0 |= (fdd_get_head(0) ? 4 : 0);
} else {
if (!(val & 8) && (fdc->dor & 8)) {
fdc->tc = 1;
fdc_int(fdc, 1);
}
if (!(val & 4)) {
fdd_stop(real_drive(fdc, val & 3));
fdc->stat = 0x00;
fdc->pnum = fdc->ptot = 0;
}
if ((val & 4) && !(fdc->dor & 4)) {
if (fdc->power_down) {
timer_set_delay_u64(&fdc->timer, 1000 * TIMER_USEC);
fdc->interrupt = -5;
} else {
timer_set_delay_u64(&fdc->timer, 8 * TIMER_USEC);
fdc->interrupt = -1;
fdc->perp &= 0xfc;
for (i = 0; i < FDD_NUM; i++)
ui_sb_update_icon(SB_FLOPPY | i, 0);
fdc_ctrl_reset(fdc);
}
}
/* We can now simplify this since each motor now spins separately. */
for (i = 0; i < FDD_NUM; i++) {
drive_num = real_drive(fdc, i);
if ((!fdd_get_flags(drive_num)) || (drive_num >= FDD_NUM))
val &= ~(0x10 << drive_num);
else
fdd_set_motor_enable(i, (val & (0x10 << drive_num)));
}
drive_num = real_drive(fdc, val & 0x03);
current_drive = drive_num;
fdc->st0 = (fdc->st0 & 0xf8) | (val & 0x03) | (fdd_get_head(drive_num) ? 4 : 0);
}
fdc->dor = val;
return;
case 3: /* TDR */
if (fdc->enh_mode) {
drive = real_drive(fdc, fdc->dor & 3);
fdc_update_rwc(fdc, drive, (val & 0x30) >> 4);
}
return;
case 4:
if (!(fdc->flags & FDC_FLAG_NO_DSR_RESET)) {
if (!(val & 0x80)) {
timer_set_delay_u64(&fdc->timer, 8 * TIMER_USEC);
fdc->interrupt = -6;
}
if (fdc->power_down || ((val & 0x80) && !(fdc->dsr & 0x80))) {
if (fdc->power_down) {
timer_set_delay_u64(&fdc->timer, 1000 * TIMER_USEC);
fdc->interrupt = -5;
} else {
timer_set_delay_u64(&fdc->timer, 8 * TIMER_USEC);
fdc->interrupt = -1;
fdc->perp &= 0xfc;
for (i = 0; i < FDD_NUM; i++)
ui_sb_update_icon(SB_FLOPPY | i, 0);
fdc_ctrl_reset(fdc);
}
}
}
fdc->dsr = val;
return;
case 5: /*Command register*/
if ((fdc->stat & 0xf0) == 0xb0) {
if ((fdc->flags & FDC_FLAG_PCJR) || !fdc->fifo) {
fdc->dat = val;
fdc->stat &= ~0x80;
} else {
fifo_write(val, fdc->fifo_p);
if (fifo_get_full(fdc->fifo_p))
fdc->stat &= ~0x80;
}
break;
}
if (fdc->pnum == fdc->ptot) {
if ((fdc->stat & 0xf0) != 0x80) {
/* If bit 4 of the MSR is set, or the MSR is 0x00,
the fdc_t is NOT in the command phase, therefore
do NOT accept commands. */
return;
}
fdc->stat &= 0xf;
fdc->tc = 0;
fdc->data_ready = 0;
fdc->command = val;
fdc->stat |= 0x10;
fdc_log("Starting FDC command %02X\n", fdc->command);
fdc->error = 0;
if (((fdc->command & 0x1f) == 0x02) || ((fdc->command & 0x1f) == 0x05) ||
((fdc->command & 0x1f) == 0x06) || ((fdc->command & 0x1f) == 0x0a) ||
((fdc->command & 0x1f) == 0x0c) || ((fdc->command & 0x1f) == 0x0d) ||
((fdc->command & 0x1f) == 0x11) || ((fdc->command & 0x1f) == 0x16) ||
((fdc->command & 0x1f) == 0x19) || ((fdc->command & 0x1f) == 0x1d))
fdc->processed_cmd = fdc->command & 0x1f;
else
fdc->processed_cmd = fdc->command;
switch (fdc->processed_cmd) {
case 0x01: /*Mode*/
if (fdc->flags & FDC_FLAG_NSC) {
fdc->pnum = 0;
fdc->ptot = 4;
fdc->stat |= 0x90;
fdc->format_state = 0;
} else
fdc_bad_command(fdc);
break;
case 0x02: /*Read track*/
fdc->satisfying_sectors = 0;
fdc->sc = 0;
fdc->wrong_am = 0;
fdc->pnum = 0;
fdc->ptot = 8;
fdc->stat |= 0x90;
fdc->mfm = (fdc->command & 0x40) ? 1 : 0;
break;
case 0x03: /*Specify*/
fdc->pnum = 0;
fdc->ptot = 2;
fdc->stat |= 0x90;
break;
case 0x04: /*Sense drive status*/
fdc->pnum = 0;
fdc->ptot = 1;
fdc->stat |= 0x90;
break;
case 0x05: /*Write data*/
case 0x09: /*Write deleted data*/
fdc->satisfying_sectors = 0;
fdc->sc = 0;
fdc->wrong_am = 0;
fdc->deleted = ((fdc->command & 0x1F) == 9) ? 1 : 0;
fdc->pnum = 0;
fdc->ptot = 8;
fdc->stat |= 0x90;
fdc->mfm = (fdc->command & 0x40) ? 1 : 0;
break;
case 0x06: /*Read data*/
case 0x0c: /*Read deleted data*/
case 0x11: /*Scan equal*/
case 0x19: /*Scan low or equal*/
case 0x16: /*Verify*/
case 0x1d: /*Scan high or equal*/
fdc->satisfying_sectors = 0;
fdc->sc = 0;
fdc->wrong_am = 0;
fdc->deleted = ((fdc->command & 0x1F) == 0xC) ? 1 : 0;
if ((fdc->command & 0x1F) == 0x16)
fdc->deleted = 2;
fdc->deleted |= (fdc->command & 0x20);
fdc->pnum = 0;
fdc->ptot = 8;
fdc->stat |= 0x90;
fdc->mfm = (fdc->command & 0x40) ? 1 : 0;
break;
case 0x17: /*Powerdown mode*/
if (!(fdc->flags & FDC_FLAG_ALI)) {
fdc_bad_command(fdc);
break;
}
fallthrough;
case 0x07: /*Recalibrate*/
fdc->pnum = 0;
fdc->ptot = 1;
fdc->stat |= 0x90;
break;
case 0x08: /*Sense interrupt status*/
fdc_log("fdc->fintr = %i, fdc->reset_stat = %i\n", fdc->fintr, fdc->reset_stat);
fdc->lastdrive = fdc->drive;
fdc_sis(fdc);
break;
case 0x0a: /*Read sector ID*/
fdc->pnum = 0;
fdc->ptot = 1;
fdc->stat |= 0x90;
fdc->mfm = (fdc->command & 0x40) ? 1 : 0;
break;
case 0x0d: /*Format track*/
fdc->pnum = 0;
fdc->ptot = 5;
fdc->stat |= 0x90;
fdc->mfm = (fdc->command & 0x40) ? 1 : 0;
fdc->format_state = 0;
break;
case 0x0e: /*Dump registers*/
if (fdc->flags & FDC_FLAG_NEC) {
fdc_bad_command(fdc);
break;
}
fdc->lastdrive = fdc->drive;
fdc->interrupt = 0x0e;
fdc_callback(fdc);
break;
case 0x0f: /*Seek*/
fdc->pnum = 0;
fdc->ptot = 2;
fdc->stat |= 0x90;
break;
case 0x18: /*NSC*/
if (!(fdc->flags & FDC_FLAG_NSC)) {
fdc_bad_command(fdc);
break;
}
fallthrough;
case 0x10: /*Get version*/
case 0x14: /*Unlock*/
case 0x94: /*Lock*/
if (fdc->flags & FDC_FLAG_NEC) {
fdc_bad_command(fdc);
break;
}
fdc->lastdrive = fdc->drive;
fdc->interrupt = fdc->command;
fdc_callback(fdc);
break;
case 0x12: /*Set perpendicular mode*/
if ((fdc->flags & FDC_FLAG_AT) && !(fdc->flags & FDC_FLAG_PCJR)) {
fdc->pnum = 0;
fdc->ptot = 1;
fdc->stat |= 0x90;
} else
fdc_bad_command(fdc);
break;
case 0x13: /*Configure*/
if (fdc->flags & FDC_FLAG_NEC) {
fdc_bad_command(fdc);
break;
}
fdc->pnum = 0;
fdc->ptot = 3;
fdc->stat |= 0x90;
break;
default:
fdc_bad_command(fdc);
break;
}
} else {
fdc->stat = 0x10 | (fdc->stat & 0xf);
fdc->params[fdc->pnum++] = val;
if (fdc->pnum == 1) {
if (command_has_drivesel[fdc->command & 0x1F]) {
if (fdc->flags & FDC_FLAG_PCJR)
fdc->drive = 0;
else
fdc->drive = fdc->dor & 3;
fdc->rw_drive = fdc->params[0] & 3;
if (((fdc->command & 0x1F) == 7) || ((fdc->command & 0x1F) == 15))
fdc->stat |= (1 << real_drive(fdc, fdc->drive));
}
}
if (fdc->pnum == fdc->ptot) {
fdc_log("Got all params %02X\n", fdc->command);
fifo_reset(fdc->fifo_p);
fdc->interrupt = fdc->processed_cmd;
fdc->reset_stat = 0;
/* Disable timer if enabled. */
timer_disable(&fdc->timer);
/* Start timer if needed at this point. */
switch (fdc->interrupt & 0x1f) {
case 0x02: /* Read a track */
case 0x03: /* Specify */
case 0x0a: /* Read sector ID */
case 0x05: /* Write data */
case 0x06: /* Read data */
case 0x09: /* Write deleted data */
case 0x0c: /* Read deleted data */
case 0x11: /* Scan equal */
case 0x12: /* Perpendicular mode */
case 0x16: /* Verify */
case 0x19: /* Scan low or equal */
case 0x1d: /* Scan high or equal */
/* Do nothing. */
break;
case 0x07: /* Recalibrate */
case 0x0f: /* Seek */
if (fdc->flags & FDC_FLAG_PCJR)
timer_set_delay_u64(&fdc->timer, 1000 * TIMER_USEC);
else
timer_set_delay_u64(&fdc->timer, 256 * TIMER_USEC);
break;
default:
timer_set_delay_u64(&fdc->timer, 256 * TIMER_USEC);
break;
}
/* Process the firt phase of the command. */
switch (fdc->processed_cmd) {
case 0x02: /* Read a track */
fdc_io_command_phase1(fdc, 0);
fdc->read_track_sector.id.c = fdc->params[1];
fdc->read_track_sector.id.h = fdc->params[2];
fdc->read_track_sector.id.r = 1;
fdc->read_track_sector.id.n = fdc->params[4];
if ((fdc->head & 0x01) && !fdd_is_double_sided(real_drive(fdc, fdc->drive))) {
fdc_noidam(fdc);
return;
}
fdd_readsector(real_drive(fdc, fdc->drive), SECTOR_FIRST, fdc->params[1], fdc->head, fdc->rate, fdc->params[4]);
break;
case 0x03: /* Specify */
fdc->stat = 0x80;
fdc->specify[0] = fdc->params[0];
fdc->specify[1] = fdc->params[1];
fdc->dma = (fdc->specify[1] & 1) ^ 1;
if (!fdc->dma)
dma_set_drq(fdc->dma_ch, 0);
break;
case 0x04: /*Sense drive status*/
fdd_set_head(real_drive(fdc, fdc->drive), (fdc->params[0] & 4) ? 1 : 0);
break;
case 0x05: /* Write data */
case 0x09: /* Write deleted data */
fdc_io_command_phase1(fdc, 1);
if ((fdc->head & 0x01) && !fdd_is_double_sided(real_drive(fdc, fdc->drive))) {
fdc_noidam(fdc);
return;
}
fdd_writesector(real_drive(fdc, fdc->drive), fdc->sector, fdc->params[1], fdc->head, fdc->rate, fdc->params[4]);
break;
case 0x11: /* Scan equal */
case 0x19: /* Scan low or equal */
case 0x1d: /* Scan high or equal */
fdc_io_command_phase1(fdc, 1);
if ((fdc->head & 0x01) && !fdd_is_double_sided(real_drive(fdc, fdc->drive))) {
fdc_noidam(fdc);
return;
}
fdd_comparesector(real_drive(fdc, fdc->drive), fdc->sector, fdc->params[1], fdc->head, fdc->rate, fdc->params[4]);
break;
case 0x16: /* Verify */
if (fdc->params[0] & 0x80)
fdc->sc = fdc->params[7];
fallthrough;
case 0x06: /* Read data */
case 0x0c: /* Read deleted data */
fdc_io_command_phase1(fdc, 0);
fdc_log("Reading sector (drive %i) (%i) (%i %i %i %i) (%i %i %i)\n", fdc->drive, fdc->params[0], fdc->params[1], fdc->params[2], fdc->params[3], fdc->params[4], fdc->params[5], fdc->params[6], fdc->params[7]);
if ((fdc->head & 0x01) && !fdd_is_double_sided(real_drive(fdc, fdc->drive))) {
fdc_noidam(fdc);
return;
}
if (((dma_mode(2) & 0x0C) == 0x00) && !(fdc->flags & FDC_FLAG_PCJR) && fdc->dma) {
/* DMA is in verify mode, treat this like a VERIFY command. */
fdc_log("Verify-mode read!\n");
fdc->tc = 1;
fdc->deleted |= 2;
}
fdd_readsector(real_drive(fdc, fdc->drive), fdc->sector, fdc->params[1], fdc->head, fdc->rate, fdc->params[4]);
break;
case 0x07: /* Recalibrate */
fdc->rw_drive = fdc->params[0] & 3;
fdc->stat = (1 << real_drive(fdc, fdc->drive));
if (!(fdc->flags & FDC_FLAG_PCJR))
fdc->stat |= 0x80;
fdc->st0 = fdc->params[0] & 3;
fdc->st0 |= fdd_get_head(real_drive(fdc, fdc->drive)) ? 0x04 : 0x00;
fdc->st0 |= 0x80;
drive_num = real_drive(fdc, fdc->drive);
/* Three conditions under which the command should fail. */
if ((drive_num >= FDD_NUM) || !fdd_get_flags(drive_num) || !motoron[drive_num] || fdd_track0(drive_num)) {
fdc_log("Failed recalibrate\n");
if ((drive_num >= FDD_NUM) || !fdd_get_flags(drive_num) || !motoron[drive_num])
fdc->st0 = 0x70 | (fdc->params[0] & 3);
else
fdc->st0 = 0x20 | (fdc->params[0] & 3);
fdc->pcn[fdc->params[0] & 3] = 0;
if (fdc->flags & FDC_FLAG_PCJR) {
fdc->fintr = 1;
fdc->interrupt = -4;
} else {
timer_disable(&fdc->timer);
fdc->interrupt = -3;
fdc_callback(fdc);
}
break;
}
if ((real_drive(fdc, fdc->drive) != 1) || fdc->drv2en)
fdc_seek(fdc, fdc->drive, -fdc->max_track);
fdc_log("Recalibrating...\n");
fdc->seek_dir = fdc->step = 1;
break;
case 0x0a: /* Read sector ID */
fdc_rate(fdc, fdc->drive);
fdc->head = (fdc->params[0] & 4) ? 1 : 0;
fdd_set_head(real_drive(fdc, fdc->drive), (fdc->params[0] & 4) ? 1 : 0);
if ((real_drive(fdc, fdc->drive) != 1) || fdc->drv2en) {
fdd_readaddress(real_drive(fdc, fdc->drive), fdc->head, fdc->rate);
if ((fdc->flags & FDC_FLAG_PCJR) || !fdc->dma)
fdc->stat = 0x70;
else
fdc->stat = 0x50;
} else
fdc_noidam(fdc);
break;
case 0x0d: /* Format */
fdc_rate(fdc, fdc->drive);
fdc->head = (fdc->params[0] & 4) ? 1 : 0;
fdd_set_head(real_drive(fdc, fdc->drive), (fdc->params[0] & 4) ? 1 : 0);
fdc->gap = fdc->params[3];
fdc->format_sectors = fdc->params[2];
fdc->format_n = fdc->params[1];
fdc->format_state = 1;
fdc->stat = 0x10;
break;
case 0x0f: /* Seek */
fdc->rw_drive = fdc->params[0] & 3;
fdc->stat = (1 << fdc->drive);
if (!(fdc->flags & FDC_FLAG_PCJR))
fdc->stat |= 0x80;
fdc->head = 0; /* TODO: See if this is correct. */
fdc->st0 = fdc->params[0] & 0x03;
fdc->st0 |= (fdc->params[0] & 4);
fdc->st0 |= 0x80;
fdd_set_head(real_drive(fdc, fdc->drive), (fdc->params[0] & 4) ? 1 : 0);
drive_num = real_drive(fdc, fdc->drive);
/* Three conditions under which the command should fail. */
if (!fdd_get_flags(drive_num) || (drive_num >= FDD_NUM) || !motoron[drive_num]) {
/* Yes, failed SEEK's still report success, unlike failed RECALIBRATE's. */
fdc->st0 = 0x20 | (fdc->params[0] & 3);
if (fdc->command & 0x80) {
if (fdc->command & 0x40)
fdc->pcn[fdc->params[0] & 3] += fdc->params[1];
else
fdc->pcn[fdc->params[0] & 3] -= fdc->params[1];
} else
fdc->pcn[fdc->params[0] & 3] = fdc->params[1];
if (fdc->flags & FDC_FLAG_PCJR) {
fdc->fintr = 1;
fdc->interrupt = -4;
} else {
timer_disable(&fdc->timer);
fdc->interrupt = -3;
fdc_callback(fdc);
}
break;
}
if (fdc->command & 0x80) {
if (fdc->params[1]) {
if (fdc->command & 0x40) {
/* Relative seek inwards. */
fdc->seek_dir = 0;
fdc_seek(fdc, fdc->drive, fdc->params[1]);
fdc->pcn[fdc->params[0] & 3] += fdc->params[1];
} else {
/* Relative seek outwards. */
fdc->seek_dir = 1;
fdc_seek(fdc, fdc->drive, -fdc->params[1]);
fdc->pcn[fdc->params[0] & 3] -= fdc->params[1];
}
fdc->step = 1;
} else {
fdc->st0 = 0x20 | (fdc->params[0] & 3);
if (fdc->flags & FDC_FLAG_PCJR) {
fdc->fintr = 1;
fdc->interrupt = -4;
} else {
timer_disable(&fdc->timer);
fdc->interrupt = -3;
fdc_callback(fdc);
}
break;
}
} else {
fdc_log("Seeking to track %i (PCN = %i)...\n", fdc->params[1], fdc->pcn[fdc->params[0] & 3]);
if ((fdc->params[1] - fdc->pcn[fdc->params[0] & 3]) == 0) {
fdc_log("Failed seek\n");
fdc->st0 = 0x20 | (fdc->params[0] & 3);
if (fdc->flags & FDC_FLAG_PCJR) {
fdc->fintr = 1;
fdc->interrupt = -4;
} else {
timer_disable(&fdc->timer);
fdc->interrupt = -3;
fdc_callback(fdc);
}
break;
}
if (fdc->params[1] > fdc->pcn[fdc->params[0] & 3])
fdc->seek_dir = 0;
else
fdc->seek_dir = 1;
fdc_seek(fdc, fdc->drive, fdc->params[1] - fdc->pcn[fdc->params[0] & 3]);
fdc->pcn[fdc->params[0] & 3] = fdc->params[1];
fdc->step = 1;
}
break;
case 0x12: /* Perpendicular mode */
fdc->stat = 0x80;
if (fdc->params[0] & 0x80)
fdc->perp = fdc->params[0] & 0x3f;
else {
fdc->perp &= 0xfc;
fdc->perp |= (fdc->params[0] & 0x03);
}
return;
default:
break;
}
} else
fdc->stat = 0x90 | (fdc->stat & 0xf);
}
return;
case 7:
if (!(fdc->flags & FDC_FLAG_TOSHIBA) && !(fdc->flags & FDC_FLAG_AT) && !(fdc->flags & FDC_FLAG_UMC))
return;
fdc->rate = val & 0x03;
if (fdc->flags & FDC_FLAG_PS1)
fdc->noprec = !!(val & 0x04);
return;
default:
break;
}
}
uint8_t
fdc_read(uint16_t addr, void *priv)
{
fdc_t *fdc = (fdc_t *) priv;
uint8_t ret = 0xff;
int drive = 0;
cycles -= ISA_CYCLES(8);
if (!fdc->power_down || ((addr & 7) == 2)) switch (addr & 7) {
case 0: /* STA */
if (fdc->flags & FDC_FLAG_PS1) {
drive = real_drive(fdc, fdc->dor & 3);
ret = 0x00;
/* TODO:
Bit 2: INDEX (best return always 0 as it goes by very fast)
*/
if (fdc->seek_dir) /* nDIRECTION */
ret |= 0x01;
if (writeprot[drive]) /* WRITEPROT */
ret |= 0x02;
if (!fdd_get_head(drive)) /* nHDSEL */
ret |= 0x08;
if (fdd_track0(drive)) /* TRK0 */
ret |= 0x10;
if (fdc->step) /* STEP */
ret |= 0x20;
if (dma_get_drq(fdc->dma_ch)) /* DRQ */
ret |= 0x40;
if (fdc->fintr || fdc->reset_stat) /* INTR */
ret |= 0x80;
} else
ret = 0xff;
break;
case 1: /* STB */
if (fdc->flags & FDC_FLAG_PS1) {
drive = real_drive(fdc, fdc->dor & 3);
ret = 0x00;
/* -Drive 2 Installed */
if (!fdd_get_type(1))
ret |= 0x80;
/* -Drive Select 1,0 */
switch (drive) {
case 0:
ret |= 0x43;
break;
case 1:
ret |= 0x23;
break;
case 2:
ret |= 0x62;
break;
case 3:
ret |= 0x61;
break;
default:
break;
}
} else {
if (is486 || !fdc->enable_3f1)
ret = 0xff;
else {
if (fdc->flags & FDC_FLAG_UMC) {
drive = real_drive(fdc, fdc->dor & 1);
ret = !fdd_is_dd(drive) ? ((fdc->dor & 1) ? 2 : 1) : 0;
} else {
ret = 0x70;
drive = real_drive(fdc, fdc->dor & 3);
if (drive)
ret &= ~0x40;
else
ret &= ~0x20;
if (fdc->dor & 0x10)
ret |= 1;
if (fdc->dor & 0x20)
ret |= 2;
}
}
}
break;
case 2:
ret = fdc->dor;
break;
case 3:
drive = real_drive(fdc, fdc->dor & 3);
if (fdc->flags & FDC_FLAG_PS1) {
/* PS/1 Model 2121 seems return drive type in port
* 0x3f3, despite the 82077AA fdc_t not implementing
* this. This is presumably implemented outside the
* fdc_t on one of the motherboard's support chips.
*
* Confirmed: 00=1.44M 3.5
* 10=2.88M 3.5
* 20=1.2M 5.25
* 30=1.2M 5.25
*
* as reported by Configur.exe.
*/
if (fdd_is_525(drive))
ret = 0x20;
else if (fdd_is_ed(drive))
ret = 0x10;
else
ret = 0x00;
} else if (!fdc->enh_mode)
ret = 0x20;
else
ret = fdc->rwc[drive] << 4;
break;
case 4: /*Status*/
ret = fdc->stat;
break;
case 5: /*Data*/
if ((fdc->stat & 0xf0) == 0xf0) {
fdc->stat &= ~0x80;
if ((fdc->flags & FDC_FLAG_PCJR) || !fdc->fifo) {
fdc->data_ready = 0;
ret = fdc->dat;
} else
ret = fifo_read(fdc->fifo_p);
break;
}
if (fdc->paramstogo) {
fdc->stat &= ~0x80;
fdc_log("%i parameters to go\n", fdc->paramstogo);
fdc->paramstogo--;
ret = fdc->res[10 - fdc->paramstogo];
if (!fdc->paramstogo)
fdc->stat = 0x80;
else
fdc->stat |= 0xC0;
} else if (fdc->dma) {
ret = fdc->dat;
break;
} else {
fdc->stat &= ~0x80;
if (lastbyte)
fdc->stat = 0x80;
lastbyte = 0;
ret = fdc->dat;
fdc->data_ready = 0;
}
fdc->stat &= 0xf0;
break;
case 7: /*Disk change*/
drive = real_drive(fdc, fdc->dor & 3);
if (fdc->flags & FDC_FLAG_PS1) {
if (fdc->dor & (0x10 << drive)) {
ret = (fdd_changed[drive] || drive_empty[drive]) ? 0x00 : 0x80;
ret |= (fdc->dor & 0x08);
ret |= (fdc->noprec << 2);
ret |= (fdc->rate & 0x03);
} else
ret = 0x00;
} else {
if (fdc->dor & (0x10 << drive)) {
if ((drive == 1) && (fdc->flags & FDC_FLAG_TOSHIBA))
ret = 0x00;
else
ret = (fdd_changed[drive] || drive_empty[drive]) ? 0x80 : 0x00;
} else
ret = 0x00;
if (fdc->flags & FDC_FLAG_DISKCHG_ACTLOW) /*PC2086/3086 seem to reverse this bit*/
ret ^= 0x80;
/* 0 = ????, 1 = Ext. FDD off, 2 = Ext. FDD = FDD A, 3 = Ext. FDD = FDD B */
if (fdc->flags & FDC_FLAG_TOSHIBA) {
ret |= (3 << 5);
ret |= 0x01;
} else
ret |= 0x7F;
}
fdc->step = 0;
break;
default:
ret = 0xFF;
}
fdc_log("[%04X:%08X] Read FDC %04X %02X [%i:%02X]\n", CS, cpu_state.pc, addr, ret, drive, fdc->dor & (0x10 << drive));
return ret;
}
static void
fdc_poll_common_finish(fdc_t *fdc, int compare, int st5)
{
fdc_int(fdc, 1);
if (!(fdc->flags & FDC_FLAG_PS1))
fdc->fintr = 0;
fdc->stat = 0xD0;
fdc->st0 = fdc->res[4] = (fdd_get_head(real_drive(fdc, fdc->drive)) ? 4 : 0) | fdc->rw_drive;
fdc->res[5] = st5;
fdc->res[6] = 0;
if (fdc->error) {
fdc->error = 0;
fdc->st0 |= 0x40;
fdc->res[4] |= 0x40;
fdc->res[5] |= fdc->st5;
fdc->res[6] |= fdc->st6;
}
if (fdc->wrong_am) {
fdc->res[6] |= 0x40;
fdc->wrong_am = 0;
}
if (compare == 1) {
if (!fdc->satisfying_sectors)
fdc->res[6] |= 4;
else if (fdc->satisfying_sectors == (fdc->params[5] << ((fdc->command & 80) ? 1 : 0)))
fdc->res[6] |= 8;
} else if (compare == 2) {
if (fdc->satisfying_sectors & 1)
fdc->res[5] |= 0x20;
if (fdc->satisfying_sectors & 2) {
fdc->res[5] |= 0x20;
fdc->res[6] |= 0x20;
}
if (fdc->satisfying_sectors & 4)
fdc->res[5] |= 0x04;
if (fdc->satisfying_sectors & 8) {
fdc->res[5] |= 0x04;
fdc->res[6] |= 0x02;
}
if (fdc->satisfying_sectors & 0x10) {
fdc->res[5] |= 0x04;
fdc->res[6] |= 0x10;
}
}
fdc->res[7] = fdc->rw_track;
fdc->res[8] = fdc->head;
fdc->res[9] = fdc->sector;
fdc->res[10] = fdc->params[4];
fdc_log("Read/write finish (%02X %02X %02X %02X %02X %02X %02X)\n", fdc->res[4], fdc->res[5], fdc->res[6], fdc->res[7], fdc->res[8], fdc->res[9], fdc->res[10]);
ui_sb_update_icon(SB_FLOPPY | real_drive(fdc, fdc->drive), 0);
fdc->paramstogo = 7;
dma_set_drq(fdc->dma_ch, 0);
}
static void
fdc_poll_readwrite_finish(fdc_t *fdc, int compare)
{
if ((fdc->interrupt == 5) || (fdc->interrupt == 9))
fdd_do_writeback(real_drive(fdc, fdc->drive));
fdc->interrupt = -2;
fdc_poll_common_finish(fdc, compare, 0);
}
static void
fdc_no_dma_end(fdc_t *fdc, int compare)
{
timer_disable(&fdc->timer);
fdc_poll_common_finish(fdc, compare, 0x80);
}
static void
fdc_callback(void *priv)
{
fdc_t *fdc = (fdc_t *) priv;
int compare = 0;
int drive_num = 0;
int old_sector = 0;
fdc_log("fdc_callback(): %i\n", fdc->interrupt);
switch (fdc->interrupt) {
case -3: /*End of command with interrupt*/
case -4: /*Recalibrate/seek interrupt (PCjr only)*/
fdc_int(fdc, fdc->interrupt & 1);
fdc->stat = (fdc->stat & 0xf) | 0x80;
return;
case -2: /*End of command*/
fdc->stat = (fdc->stat & 0xf) | 0x80;
return;
case -5: /*Reset in power down mode */
fdc->perp &= 0xfc;
for (uint8_t i = 0; i < FDD_NUM; i++)
ui_sb_update_icon(SB_FLOPPY | i, 0);
fdc_ctrl_reset(fdc);
fdc->fintr = 0;
memset(fdc->pcn, 0x00, 4 * sizeof(uint16_t));
return;
case -1: /*Reset*/
fdc_int(fdc, 1);
fdc->fintr = 0;
memset(fdc->pcn, 0x00, 4 * sizeof(uint16_t));
fdc->reset_stat = 4;
return;
case -6: /*DSR Reset clear*/
fdc->dsr |= 0x80;
return;
case 0x01: /* Mode */
fdc->stat = 0x80;
fdc->densel_force = (fdc->params[2] & 0xC0) >> 6;
return;
case 0x02: /* Read track */
ui_sb_update_icon(SB_FLOPPY | real_drive(fdc, fdc->drive), 1);
fdc->eot[fdc->drive]--;
fdc->read_track_sector.id.r++;
if (!fdc->eot[fdc->drive] || fdc->tc) {
fdc_poll_readwrite_finish(fdc, 2);
return;
} else {
fdd_readsector(real_drive(fdc, fdc->drive), SECTOR_NEXT, fdc->rw_track, fdc->head, fdc->rate, fdc->params[4]);
if ((fdc->flags & FDC_FLAG_PCJR) || !fdc->dma)
fdc->stat = 0x70;
else {
dma_set_drq(fdc->dma_ch, 1);
fdc->stat = 0x50;
}
}
return;
case 0x04: /* Sense drive status */
fdc->res[10] = (fdc->params[0] & 7) | 0x20;
if (fdd_is_double_sided(real_drive(fdc, fdc->drive)))
fdc->res[10] |= 0x08;
if ((real_drive(fdc, fdc->drive) != 1) || fdc->drv2en) {
if (fdd_track0(real_drive(fdc, fdc->drive)))
fdc->res[10] |= 0x10;
}
if (writeprot[fdc->drive])
fdc->res[10] |= 0x40;
fdc->stat = (fdc->stat & 0xf) | 0xd0;
fdc->paramstogo = 1;
fdc->interrupt = 0;
return;
case 0x05: /* Write data */
case 0x09: /* Write deleted data */
case 0x06: /* Read data */
case 0x0c: /* Read deleted data */
case 0x11: /* Scan equal */
case 0x19: /* Scan low or equal */
case 0x1c: /* Verify */
case 0x1d: /* Scan high or equal */
if ((fdc->interrupt == 0x11) || (fdc->interrupt == 0x19) || (fdc->interrupt == 0x1D))
compare = 1;
else
compare = 0;
if ((fdc->interrupt == 6) || (fdc->interrupt == 0xC)) {
if (fdc->wrong_am && !(fdc->deleted & 0x20)) {
/* Mismatching data address mark and no skip, set TC. */
fdc->tc = 1;
}
}
old_sector = fdc->sector;
if (fdc->tc) {
/* This is needed so that the correct results are returned
in case of TC. */
if (fdc->sector == fdc->params[5]) {
if (!(fdc->command & 0x80)) {
fdc->rw_track++;
fdc->sector = 1;
} else {
if (fdc->head)
fdc->rw_track++;
fdc->head ^= 1;
fdd_set_head(real_drive(fdc, fdc->drive), fdc->head);
fdc->sector = 1;
}
} else
fdc->sector++;
fdc_poll_readwrite_finish(fdc, compare);
return;
}
if ((fdc->interrupt == 0x16) && (fdc->params[0] & 0x80)) {
/* VERIFY command, EC set */
fdc->sc--;
if (!fdc->sc) {
fdc->sector++;
fdc_poll_readwrite_finish(fdc, 0);
return;
}
/* The rest is processed normally per MT flag and EOT. */
} else if ((fdc->interrupt == 0x16) && !(fdc->params[0] & 0x80)) {
/* VERIFY command, EC clear */
if ((fdc->sector == old_sector) && (fdc->head == (fdc->command & 0x80) ? 1 : 0)) {
fdc->sector++;
fdc_poll_readwrite_finish(fdc, 0);
return;
}
}
if (fdc->sector == fdc->params[5]) {
/* Reached end of track, MT bit is clear */
if (!(fdc->command & 0x80)) {
if (fdc->dma) {
fdc->rw_track++;
fdc->sector = 1;
}
if (!(fdc->flags & FDC_FLAG_PCJR) && fdc->dma && (old_sector == 255))
fdc_no_dma_end(fdc, compare);
else
fdc_poll_readwrite_finish(fdc, compare);
return;
}
/* Reached end of track, MT bit is set, head is 1 */
if (fdd_get_head(real_drive(fdc, fdc->drive)) == 1) {
if (fdc->dma) {
fdc->rw_track++;
fdc->sector = 1;
fdc->head &= 0xFE;
fdd_set_head(real_drive(fdc, fdc->drive), 0);
}
if (!(fdc->flags & FDC_FLAG_PCJR) && fdc->dma && (old_sector == 255))
fdc_no_dma_end(fdc, compare);
else
fdc_poll_readwrite_finish(fdc, compare);
return;
}
if (fdd_get_head(real_drive(fdc, fdc->drive)) == 0) {
fdc->sector = 1;
fdc->head |= 1;
fdd_set_head(real_drive(fdc, fdc->drive), 1);
if (!fdd_is_double_sided(real_drive(fdc, fdc->drive))) {
fdc_noidam(fdc);
return;
}
}
} else if (fdc->sector < fdc->params[5])
fdc->sector++;
else if (fdc->params[5] == 0)
fdc->sector++;
ui_sb_update_icon(SB_FLOPPY | real_drive(fdc, fdc->drive), 1);
switch (fdc->interrupt) {
case 5:
case 9:
fdd_writesector(real_drive(fdc, fdc->drive), fdc->sector, fdc->rw_track, fdc->head, fdc->rate, fdc->params[4]);
if ((fdc->flags & FDC_FLAG_PCJR) || !fdc->dma)
fdc->stat = 0xb0;
else {
dma_set_drq(fdc->dma_ch, 1);
fdc->stat = 0x10;
}
break;
case 6:
case 0xC:
case 0x16:
fdd_readsector(real_drive(fdc, fdc->drive), fdc->sector, fdc->rw_track, fdc->head, fdc->rate, fdc->params[4]);
if ((fdc->flags & FDC_FLAG_PCJR) || !fdc->dma)
fdc->stat = 0x70;
else {
dma_set_drq(fdc->dma_ch, 1);
fdc->stat = 0x50;
}
break;
case 0x11:
case 0x19:
case 0x1D:
fdd_comparesector(real_drive(fdc, fdc->drive), fdc->sector, fdc->rw_track, fdc->head, fdc->rate, fdc->params[4]);
if ((fdc->flags & FDC_FLAG_PCJR) || !fdc->dma)
fdc->stat = 0xb0;
else {
dma_set_drq(fdc->dma_ch, 1);
fdc->stat = 0x10;
}
break;
default:
break;
}
return;
case 0x07: /* Recalibrate */
fdc->pcn[fdc->params[0] & 3] = 0;
drive_num = real_drive(fdc, fdc->rw_drive);
fdc->st0 = 0x20 | (fdc->params[0] & 3);
if (!fdd_track0(drive_num))
fdc->st0 |= 0x50;
if (fdc->flags & FDC_FLAG_PCJR) {
fdc->fintr = 1;
fdc->interrupt = -4;
} else
fdc->interrupt = -3;
timer_set_delay_u64(&fdc->timer, 2048 * TIMER_USEC);
fdc->stat = 0x80 | (1 << fdc->rw_drive);
return;
case 0x0d: /*Format track*/
if (fdc->format_state == 1) {
fdc->format_state = 2;
timer_set_delay_u64(&fdc->timer, 8 * TIMER_USEC);
} else if (fdc->format_state == 2) {
fdd_format(real_drive(fdc, fdc->drive), fdc->head, fdc->rate, fdc->params[4]);
fdc->format_state = 3;
} else {
fdc->interrupt = -2;
fdc_int(fdc, 1);
if (!(fdc->flags & FDC_FLAG_PS1))
fdc->fintr = 0;
fdc->stat = 0xD0;
fdc->st0 = fdc->res[4] = (fdd_get_head(real_drive(fdc, fdc->drive)) ? 4 : 0) | fdc->drive;
fdc->res[5] = fdc->res[6] = 0;
fdc->res[7] = fdc->format_sector_id.id.c;
fdc->res[8] = fdc->format_sector_id.id.h;
fdc->res[9] = fdc->format_sector_id.id.r;
fdc->res[10] = fdc->format_sector_id.id.n;
fdc->paramstogo = 7;
fdc->format_state = 0;
return;
}
return;
case 0x0e: /*Dump registers*/
fdc->stat = (fdc->stat & 0xf) | 0xd0;
fdc->res[1] = fdc->pcn[0];
fdc->res[2] = fdc->pcn[1];
fdc->res[3] = fdc->pcn[2];
fdc->res[4] = fdc->pcn[3];
fdc->res[5] = fdc->specify[0];
fdc->res[6] = fdc->specify[1];
fdc->res[7] = fdc->eot[fdc->drive];
fdc->res[8] = (fdc->perp & 0x7f) | ((fdc->lock) ? 0x80 : 0);
fdc->res[9] = fdc->config;
fdc->res[10] = fdc->pretrk;
fdc->paramstogo = 10;
fdc->interrupt = 0;
return;
case 0x0f: /*Seek*/
fdc->st0 = 0x20 | (fdc->params[0] & 3);
fdc->stat = 0x80 | (1 << fdc->rw_drive);
if (fdc->flags & FDC_FLAG_PCJR) {
fdc->fintr = 1;
fdc->interrupt = -4;
timer_set_delay_u64(&fdc->timer, 1024 * TIMER_USEC);
} else {
fdc->interrupt = -3;
fdc_callback(fdc);
}
return;
case 0x10: /*Version*/
case 0x18: /*NSC*/
fdc->stat = (fdc->stat & 0xf) | 0xd0;
fdc->res[10] = (fdc->interrupt & 0x08) ? 0x73 : 0x90;
fdc->paramstogo = 1;
fdc->interrupt = 0;
return;
case 0x17: /*Powerdown mode*/
fdc->stat = (fdc->stat & 0xf) | 0xd0;
fdc->res[10] = fdc->params[0];
fdc->paramstogo = 1;
fdc->interrupt = 0;
return;
case 0x13: /*Configure*/
fdc->config = fdc->params[1];
fdc->pretrk = fdc->params[2];
fdc->fifo = (fdc->params[1] & 0x20) ? 0 : 1;
fdc->tfifo = (fdc->params[1] & 0xF);
fifo_reset(fdc->fifo_p);
fifo_set_len(fdc->fifo_p, fdc->tfifo + 1);
fifo_set_trigger_len(fdc->fifo_p, fdc->tfifo + 1);
fdc->stat = 0x80;
return;
case 0x14: /*Unlock*/
case 0x94: /*Lock*/
fdc->lock = (fdc->interrupt & 0x80) ? 1 : 0;
fdc->stat = (fdc->stat & 0xf) | 0xd0;
fdc->res[10] = (fdc->interrupt & 0x80) ? 0x10 : 0x00;
fdc->paramstogo = 1;
fdc->interrupt = 0;
return;
case 0xfc: /*Invalid*/
fdc->dat = fdc->st0 = 0x80;
fdc->stat = (fdc->stat & 0xf) | 0xd0;
fdc->res[10] = fdc->st0;
fdc->paramstogo = 1;
fdc->interrupt = 0;
return;
default:
break;
}
}
void
fdc_error(fdc_t *fdc, int st5, int st6)
{
dma_set_drq(fdc->dma_ch, 0);
timer_disable(&fdc->timer);
fdc_int(fdc, 1);
if (!(fdc->flags & FDC_FLAG_PS1))
fdc->fintr = 0;
fdc->stat = 0xD0;
fdc->st0 = fdc->res[4] = 0x40 | (fdd_get_head(real_drive(fdc, fdc->drive)) ? 4 : 0) | fdc->rw_drive;
if (fdc->head && !fdd_is_double_sided(real_drive(fdc, fdc->drive)))
fdc->st0 |= 0x08;
fdc->res[5] = st5;
fdc->res[6] = st6;
if (fdc->wrong_am) {
fdc->res[6] |= 0x40;
fdc->wrong_am = 0;
}
fdc_log("FDC Error: %02X %02X %02X\n", fdc->res[4], fdc->res[5], fdc->res[6]);
switch (fdc->interrupt) {
case 0x02:
case 0x05:
case 0x06:
case 0x09:
case 0x0C:
case 0x11:
case 0x16:
case 0x19:
case 0x1D:
fdc->res[7] = fdc->rw_track;
fdc->res[8] = fdc->head;
fdc->res[9] = fdc->sector;
fdc->res[10] = fdc->params[4];
break;
default:
fdc->res[7] = 0;
fdc->res[8] = 0;
fdc->res[9] = 0;
fdc->res[10] = 0;
break;
}
ui_sb_update_icon(SB_FLOPPY | real_drive(fdc, fdc->drive), 0);
fdc->paramstogo = 7;
}
void
fdc_overrun(fdc_t *fdc)
{
fdd_stop(fdc->drive);
fdc_error(fdc, 0x10, 0);
}
int
fdc_is_verify(fdc_t *fdc)
{
return (fdc->deleted & 2) ? 1 : 0;
}
int
fdc_data(fdc_t *fdc, uint8_t data, int last)
{
int result = 0;
if (fdc->deleted & 2) {
/* We're in a VERIFY command, so return with 0. */
return 0;
}
if ((fdc->flags & FDC_FLAG_PCJR) || !fdc->dma) {
if (fdc->tc)
return 0;
if (fdc->data_ready) {
fdc_overrun(fdc);
return -1;
}
if ((fdc->flags & FDC_FLAG_PCJR) || !fdc->fifo || (fdc->tfifo < 1)) {
fdc->dat = data;
fdc->data_ready = 1;
fdc->stat = 0xf0;
} else {
/* FIFO enabled */
fifo_write(data, fdc->fifo_p);
if (fifo_get_full(fdc->fifo_p)) {
/* We have wrapped around, means FIFO is over */
fdc->data_ready = 1;
fdc->stat = 0xf0;
}
}
} else {
if (fdc->tc)
return -1;
if (!fdc->fifo || (fdc->tfifo < 1)) {
fdc->data_ready = 1;
fdc->stat = 0x50;
dma_set_drq(fdc->dma_ch, 1);
fdc->dat = data;
result = dma_channel_write(fdc->dma_ch, data);
if (result & DMA_OVER) {
dma_set_drq(fdc->dma_ch, 0);
fdc->tc = 1;
return -1;
}
dma_set_drq(fdc->dma_ch, 0);
} else {
/* FIFO enabled */
fifo_write(data, fdc->fifo_p);
if (last || fifo_get_full(fdc->fifo_p)) {
/* We have wrapped around, means FIFO is over */
fdc->data_ready = 1;
fdc->stat = 0x50;
dma_set_drq(fdc->dma_ch, 1);
while (!fifo_get_empty(fdc->fifo_p)) {
result = dma_channel_write(fdc->dma_ch, fifo_read(fdc->fifo_p));
if (result & DMA_OVER) {
dma_set_drq(fdc->dma_ch, 0);
fdc->tc = 1;
return -1;
}
}
dma_set_drq(fdc->dma_ch, 0);
}
}
}
return 0;
}
void
fdc_track_finishread(fdc_t *fdc, int condition)
{
fdc->stat = 0x10;
fdc->satisfying_sectors |= condition;
fdc_callback(fdc);
}
void
fdc_sector_finishcompare(fdc_t *fdc, int satisfying)
{
fdc->stat = 0x10;
if (satisfying)
fdc->satisfying_sectors++;
fdc_callback(fdc);
}
void
fdc_sector_finishread(fdc_t *fdc)
{
fdc->stat = 0x10;
fdc_callback(fdc);
}
/* There is no sector ID. */
void
fdc_noidam(fdc_t *fdc)
{
fdc_error(fdc, 1, 0);
}
/* Sector ID's are there, but there is no sector. */
void
fdc_nosector(fdc_t *fdc)
{
fdc_error(fdc, 4, 0);
}
/* There is no sector data. */
void
fdc_nodataam(fdc_t *fdc)
{
fdc_error(fdc, 1, 1);
}
/* Abnormal termination with both status 1 and 2 set to 0, used when abnormally
terminating the fdc_t FORMAT TRACK command. */
void
fdc_cannotformat(fdc_t *fdc)
{
fdc_error(fdc, 0, 0);
}
void
fdc_datacrcerror(fdc_t *fdc)
{
fdc_error(fdc, 0x20, 0x20);
}
void
fdc_headercrcerror(fdc_t *fdc)
{
fdc_error(fdc, 0x20, 0);
}
void
fdc_wrongcylinder(fdc_t *fdc)
{
fdc_error(fdc, 4, 0x10);
}
void
fdc_badcylinder(fdc_t *fdc)
{
fdc_error(fdc, 4, 0x02);
}
void
fdc_writeprotect(fdc_t *fdc)
{
fdc_error(fdc, 0x02, 0);
}
int
fdc_getdata(fdc_t *fdc, int last)
{
int data = 0;
if ((fdc->flags & FDC_FLAG_PCJR) || !fdc->dma) {
if ((fdc->flags & FDC_FLAG_PCJR) || !fdc->fifo || (fdc->tfifo < 1)) {
data = fdc->dat;
if (!last)
fdc->stat = 0xb0;
} else {
data = fifo_read(fdc->fifo_p);
if (!last && fifo_get_empty(fdc->fifo_p))
fdc->stat = 0xb0;
}
} else {
if (!fdc->fifo || (fdc->tfifo < 1)) {
data = dma_channel_read(fdc->dma_ch);
dma_set_drq(fdc->dma_ch, 0);
if (data & DMA_OVER)
fdc->tc = 1;
if (!last) {
dma_set_drq(fdc->dma_ch, 1);
fdc->stat = 0x10;
}
} else {
if (fifo_get_empty(fdc->fifo_p)) {
while (!fifo_get_full(fdc->fifo_p)) {
data = dma_channel_read(fdc->dma_ch);
fifo_write(data, fdc->fifo_p);
if (data & DMA_OVER) {
dma_set_drq(fdc->dma_ch, 0);
fdc->tc = 1;
break;
}
}
dma_set_drq(fdc->dma_ch, 0);
}
data = fifo_read(fdc->fifo_p);
if (!last && fifo_get_empty(fdc->fifo_p)) {
dma_set_drq(fdc->dma_ch, 1);
fdc->stat = 0x10;
}
}
}
return data & 0xff;
}
void
fdc_sectorid(fdc_t *fdc, uint8_t track, uint8_t side, uint8_t sector, uint8_t size, UNUSED(uint8_t crc1), UNUSED(uint8_t crc2))
{
fdc_int(fdc, 1);
fdc->stat = 0xD0;
fdc->st0 = fdc->res[4] = (fdd_get_head(real_drive(fdc, fdc->drive)) ? 4 : 0) | fdc->drive;
fdc->res[5] = 0;
fdc->res[6] = 0;
fdc->res[7] = track;
fdc->res[8] = side;
fdc->res[9] = sector;
fdc->res[10] = size;
ui_sb_update_icon(SB_FLOPPY | real_drive(fdc, fdc->drive), 0);
fdc->paramstogo = 7;
dma_set_drq(fdc->dma_ch, 0);
}
uint8_t
fdc_get_swwp(fdc_t *fdc)
{
return fdc->swwp;
}
void
fdc_set_swwp(fdc_t *fdc, uint8_t swwp)
{
fdc->swwp = swwp;
}
uint8_t
fdc_get_diswr(fdc_t *fdc)
{
if (!fdc)
return 0;
return fdc->disable_write;
}
void
fdc_set_diswr(fdc_t *fdc, uint8_t diswr)
{
fdc->disable_write = diswr;
}
uint8_t
fdc_get_swap(fdc_t *fdc)
{
return fdc->swap;
}
void
fdc_set_swap(fdc_t *fdc, uint8_t swap)
{
fdc->swap = swap;
}
void
fdc_set_irq(fdc_t *fdc, int irq)
{
fdc->irq = irq;
}
void
fdc_set_dma_ch(fdc_t *fdc, int dma_ch)
{
fdc->dma_ch = dma_ch;
}
void
fdc_set_base(fdc_t *fdc, int base)
{
int super_io = (fdc->flags & FDC_FLAG_SUPERIO);
if (fdc->flags & FDC_FLAG_NSC) {
io_sethandler(base + 2, 0x0001, fdc_read, NULL, NULL, fdc_write, NULL, NULL, fdc);
io_sethandler(base + 4, 0x0002, fdc_read, NULL, NULL, fdc_write, NULL, NULL, fdc);
io_sethandler(base + 7, 0x0001, fdc_read, NULL, NULL, fdc_write, NULL, NULL, fdc);
} else {
if ((fdc->flags & FDC_FLAG_AT) || (fdc->flags & FDC_FLAG_AMSTRAD)) {
io_sethandler(base + (super_io ? 2 : 0), super_io ? 0x0004 : 0x0006, fdc_read, NULL, NULL, fdc_write, NULL, NULL, fdc);
io_sethandler(base + 7, 0x0001, fdc_read, NULL, NULL, fdc_write, NULL, NULL, fdc);
} else {
if (fdc->flags & FDC_FLAG_PCJR)
io_sethandler(base, 0x0010, fdc_read, NULL, NULL, fdc_write, NULL, NULL, fdc);
else {
if (fdc->flags & FDC_FLAG_UMC)
io_sethandler(base + 0x0001, 0x0001, fdc_read, NULL, NULL, NULL, NULL, NULL, fdc);
io_sethandler(base + 0x0002, 0x0001, NULL, NULL, NULL, fdc_write, NULL, NULL, fdc);
io_sethandler(base + 0x0004, 0x0001, fdc_read, NULL, NULL, NULL, NULL, NULL, fdc);
io_sethandler(base + 0x0005, 0x0001, fdc_read, NULL, NULL, fdc_write, NULL, NULL, fdc);
if ((fdc->flags & FDC_FLAG_TOSHIBA) || (fdc->flags & FDC_FLAG_UMC))
io_sethandler(base + 0x0007, 0x0001, fdc_read, NULL, NULL, fdc_write, NULL, NULL, fdc);
}
}
}
fdc->base_address = base;
fdc_log("FDC Base address set%s (%04X)\n", super_io ? " for Super I/O" : "", fdc->base_address);
}
void
fdc_remove(fdc_t *fdc)
{
int super_io = (fdc->flags & FDC_FLAG_SUPERIO);
fdc_log("FDC Removed (%04X)\n", fdc->base_address);
if (fdc->flags & FDC_FLAG_NSC) {
io_removehandler(fdc->base_address + 2, 0x0001, fdc_read, NULL, NULL, fdc_write, NULL, NULL, fdc);
io_removehandler(fdc->base_address + 4, 0x0002, fdc_read, NULL, NULL, fdc_write, NULL, NULL, fdc);
io_removehandler(fdc->base_address + 7, 0x0001, fdc_read, NULL, NULL, fdc_write, NULL, NULL, fdc);
} else {
if ((fdc->flags & FDC_FLAG_AT) || (fdc->flags & FDC_FLAG_AMSTRAD)) {
io_removehandler(fdc->base_address + (super_io ? 2 : 0), super_io ? 0x0004 : 0x0006, fdc_read, NULL, NULL, fdc_write, NULL, NULL, fdc);
io_removehandler(fdc->base_address + 7, 0x0001, fdc_read, NULL, NULL, fdc_write, NULL, NULL, fdc);
} else {
if (fdc->flags & FDC_FLAG_PCJR)
io_removehandler(fdc->base_address, 0x0010, fdc_read, NULL, NULL, fdc_write, NULL, NULL, fdc);
else {
if (fdc->flags & FDC_FLAG_UMC)
io_removehandler(fdc->base_address + 0x0001, 0x0001, fdc_read, NULL, NULL, NULL, NULL, NULL, fdc);
io_removehandler(fdc->base_address + 0x0002, 0x0001, NULL, NULL, NULL, fdc_write, NULL, NULL, fdc);
io_removehandler(fdc->base_address + 0x0004, 0x0001, fdc_read, NULL, NULL, NULL, NULL, NULL, fdc);
io_removehandler(fdc->base_address + 0x0005, 0x0001, fdc_read, NULL, NULL, fdc_write, NULL, NULL, fdc);
if ((fdc->flags & FDC_FLAG_TOSHIBA) || (fdc->flags & FDC_FLAG_UMC))
io_removehandler(fdc->base_address + 0x0007, 0x0001, fdc_read, NULL, NULL, fdc_write, NULL, NULL, fdc);
}
}
}
}
void
fdc_reset(void *priv)
{
uint8_t default_rwc;
fdc_t *fdc = (fdc_t *) priv;
default_rwc = (fdc->flags & FDC_FLAG_START_RWC_1) ? 1 : 0;
fdc->enable_3f1 = 1;
fdc_update_enh_mode(fdc, 0);
if (fdc->flags & FDC_FLAG_PS1)
fdc_update_densel_polarity(fdc, 0);
else
fdc_update_densel_polarity(fdc, 1);
if (fdc->flags & FDC_FLAG_NSC)
fdc_update_densel_force(fdc, 3);
else
fdc_update_densel_force(fdc, 0);
fdc_update_rwc(fdc, 0, default_rwc);
fdc_update_rwc(fdc, 1, default_rwc);
fdc_update_rwc(fdc, 2, default_rwc);
fdc_update_rwc(fdc, 3, default_rwc);
fdc_update_drvrate(fdc, 0, 0);
fdc_update_drvrate(fdc, 1, 0);
fdc_update_drvrate(fdc, 2, 0);
fdc_update_drvrate(fdc, 3, 0);
fdc_update_drv2en(fdc, 1);
fdc_update_rates(fdc);
fdc->fifo = 0;
fdc->tfifo = 1;
if (fdc->flags & FDC_FLAG_PCJR) {
fdc->dma = 0;
fdc->specify[1] = 1;
} else if (fdc->flags & FDC_FLAG_SEC) {
fdc->dma = 1;
fdc->specify[1] = 0;
} else if (fdc->flags & FDC_FLAG_TER) {
fdc->dma = 1;
fdc->specify[1] = 0;
} else if (fdc->flags & FDC_FLAG_QUA) {
fdc->dma = 1;
fdc->specify[1] = 0;
} else {
fdc->dma = 1;
fdc->specify[1] = 0;
}
fdc->config = 0x20;
fdc->pretrk = 0;
fdc->swwp = 0;
fdc->disable_write = 0;
fdc_ctrl_reset(fdc);
fdc->max_track = (fdc->flags & FDC_FLAG_MORE_TRACKS) ? 85 : 79;
fdc_remove(fdc);
if (fdc->flags & FDC_FLAG_SEC)
fdc_set_base(fdc, FDC_SECONDARY_ADDR);
else if (fdc->flags & FDC_FLAG_TER)
fdc_set_base(fdc, FDC_TERTIARY_ADDR);
else if (fdc->flags & FDC_FLAG_QUA)
fdc_set_base(fdc, FDC_QUATERNARY_ADDR);
else
fdc_set_base(fdc, (fdc->flags & FDC_FLAG_PCJR) ? FDC_PRIMARY_PCJR_ADDR : FDC_PRIMARY_ADDR);
current_drive = 0;
for (uint8_t i = 0; i < FDD_NUM; i++)
ui_sb_update_icon(SB_FLOPPY | i, 0);
fdc->power_down = 0;
}
static void
fdc_close(void *priv)
{
fdc_t *fdc = (fdc_t *) priv;
/* Stop timers. */
timer_disable(&fdc->watchdog_timer);
timer_disable(&fdc->timer);
fifo_close(fdc->fifo_p);
free(fdc);
}
static void *
fdc_init(const device_t *info)
{
fdc_t *fdc = (fdc_t *) malloc(sizeof(fdc_t));
memset(fdc, 0, sizeof(fdc_t));
fdc->flags = info->local;
if (fdc->flags & FDC_FLAG_SEC)
fdc->irq = FDC_SECONDARY_IRQ;
else if (fdc->flags & FDC_FLAG_TER)
fdc->irq = FDC_TERTIARY_IRQ;
else if (fdc->flags & FDC_FLAG_QUA)
fdc->irq = FDC_QUATERNARY_IRQ;
else
fdc->irq = FDC_PRIMARY_IRQ;
if (fdc->flags & FDC_FLAG_PCJR)
timer_add(&fdc->watchdog_timer, fdc_watchdog_poll, fdc, 0);
else if (fdc->flags & FDC_FLAG_SEC)
fdc->dma_ch = FDC_SECONDARY_DMA;
else if (fdc->flags & FDC_FLAG_TER)
fdc->dma_ch = FDC_TERTIARY_DMA;
else if (fdc->flags & FDC_FLAG_QUA)
fdc->dma_ch = FDC_QUATERNARY_DMA;
else
fdc->dma_ch = FDC_PRIMARY_DMA;
fdc_log("FDC added: %04X (flags: %08X)\n", fdc->base_address, fdc->flags);
fdc->fifo_p = (void *) fifo16_init();
timer_add(&fdc->timer, fdc_callback, fdc, 0);
d86f_set_fdc(fdc);
fdi_set_fdc(fdc);
fdd_set_fdc(fdc);
imd_set_fdc(fdc);
img_set_fdc(fdc);
mfm_set_fdc(fdc);
fdc_reset(fdc);
return fdc;
}
void
fdc_3f1_enable(fdc_t *fdc, int enable)
{
fdc->enable_3f1 = !!enable;
}
const device_t fdc_xt_device = {
.name = "PC/XT Floppy Drive Controller",
.internal_name = "fdc_xt",
.flags = 0,
.local = 0,
.init = fdc_init,
.close = fdc_close,
.reset = fdc_reset,
{ .available = NULL },
.speed_changed = NULL,
.force_redraw = NULL,
.config = NULL
};
const device_t fdc_xt_sec_device = {
.name = "PC/XT Floppy Drive Controller (Secondary)",
.internal_name = "fdc_xt_sec",
.flags = FDC_FLAG_SEC,
.local = 0,
.init = fdc_init,
.close = fdc_close,
.reset = fdc_reset,
{ .available = NULL },
.speed_changed = NULL,
.force_redraw = NULL,
.config = NULL
};
const device_t fdc_xt_ter_device = {
.name = "PC/XT Floppy Drive Controller (Tertiary)",
.internal_name = "fdc_xt_ter",
.flags = FDC_FLAG_TER,
.local = 0,
.init = fdc_init,
.close = fdc_close,
.reset = fdc_reset,
{ .available = NULL },
.speed_changed = NULL,
.force_redraw = NULL,
.config = NULL
};
const device_t fdc_xt_qua_device = {
.name = "PC/XT Floppy Drive Controller (Quaternary)",
.internal_name = "fdc_xt_qua",
.flags = FDC_FLAG_QUA,
.local = 0,
.init = fdc_init,
.close = fdc_close,
.reset = fdc_reset,
{ .available = NULL },
.speed_changed = NULL,
.force_redraw = NULL,
.config = NULL
};
const device_t fdc_xt_t1x00_device = {
.name = "PC/XT Floppy Drive Controller (Toshiba)",
.internal_name = "fdc_xt_t1x00",
.flags = 0,
.local = FDC_FLAG_TOSHIBA,
.init = fdc_init,
.close = fdc_close,
.reset = fdc_reset,
{ .available = NULL },
.speed_changed = NULL,
.force_redraw = NULL,
.config = NULL
};
const device_t fdc_xt_amstrad_device = {
.name = "PC/XT Floppy Drive Controller (Amstrad)",
.internal_name = "fdc_xt_amstrad",
.flags = 0,
.local = FDC_FLAG_DISKCHG_ACTLOW | FDC_FLAG_AMSTRAD,
.init = fdc_init,
.close = fdc_close,
.reset = fdc_reset,
{ .available = NULL },
.speed_changed = NULL,
.force_redraw = NULL,
.config = NULL
};
const device_t fdc_xt_tandy_device = {
.name = "PC/XT Floppy Drive Controller (Tandy)",
.internal_name = "fdc_xt_tandy",
.flags = 0,
.local = FDC_FLAG_AMSTRAD,
.init = fdc_init,
.close = fdc_close,
.reset = fdc_reset,
{ .available = NULL },
.speed_changed = NULL,
.force_redraw = NULL,
.config = NULL
};
const device_t fdc_pcjr_device = {
.name = "PCjr Floppy Drive Controller",
.internal_name = "fdc_pcjr",
.flags = 0,
.local = FDC_FLAG_PCJR,
.init = fdc_init,
.close = fdc_close,
.reset = fdc_reset,
{ .available = NULL },
.speed_changed = NULL,
.force_redraw = NULL,
.config = NULL
};
const device_t fdc_at_device = {
.name = "PC/AT Floppy Drive Controller",
.internal_name = "fdc_at",
.flags = 0,
.local = FDC_FLAG_AT,
.init = fdc_init,
.close = fdc_close,
.reset = fdc_reset,
{ .available = NULL },
.speed_changed = NULL,
.force_redraw = NULL,
.config = NULL
};
const device_t fdc_at_sec_device = {
.name = "PC/AT Floppy Drive Controller (Secondary)",
.internal_name = "fdc_at_sec",
.flags = 0,
.local = FDC_FLAG_AT | FDC_FLAG_SEC,
.init = fdc_init,
.close = fdc_close,
.reset = fdc_reset,
{ .available = NULL },
.speed_changed = NULL,
.force_redraw = NULL,
.config = NULL
};
const device_t fdc_at_ter_device = {
.name = "PC/AT Floppy Drive Controller (Tertiary)",
.internal_name = "fdc_at_ter",
.flags = 0,
.local = FDC_FLAG_AT | FDC_FLAG_TER,
.init = fdc_init,
.close = fdc_close,
.reset = fdc_reset,
{ .available = NULL },
.speed_changed = NULL,
.force_redraw = NULL,
.config = NULL
};
const device_t fdc_at_qua_device = {
.name = "PC/AT Floppy Drive Controller (Quaternary)",
.internal_name = "fdc_at_qua",
.flags = 0,
.local = FDC_FLAG_AT | FDC_FLAG_QUA,
.init = fdc_init,
.close = fdc_close,
.reset = fdc_reset,
{ .available = NULL },
.speed_changed = NULL,
.force_redraw = NULL,
.config = NULL
};
const device_t fdc_at_actlow_device = {
.name = "PC/AT Floppy Drive Controller (Active low)",
.internal_name = "fdc_at_actlow",
.flags = 0,
.local = FDC_FLAG_DISKCHG_ACTLOW | FDC_FLAG_AT,
.init = fdc_init,
.close = fdc_close,
.reset = fdc_reset,
{ .available = NULL },
.speed_changed = NULL,
.force_redraw = NULL,
.config = NULL
};
const device_t fdc_at_ps1_device = {
.name = "PC/AT Floppy Drive Controller (PS/1, PS/2 ISA)",
.internal_name = "fdc_at_ps1",
.flags = 0,
.local = FDC_FLAG_DISKCHG_ACTLOW | FDC_FLAG_AT | FDC_FLAG_PS1,
.init = fdc_init,
.close = fdc_close,
.reset = fdc_reset,
{ .available = NULL },
.speed_changed = NULL,
.force_redraw = NULL,
.config = NULL
};
const device_t fdc_at_ps1_2121_device = {
.name = "PC/AT Floppy Drive Controller (PS/1, PS/2 ISA)",
.internal_name = "fdc_at_ps1",
.flags = 0,
.local = FDC_FLAG_NO_DSR_RESET | FDC_FLAG_DISKCHG_ACTLOW | FDC_FLAG_AT | FDC_FLAG_PS1,
.init = fdc_init,
.close = fdc_close,
.reset = fdc_reset,
{ .available = NULL },
.speed_changed = NULL,
.force_redraw = NULL,
.config = NULL
};
const device_t fdc_at_smc_device = {
.name = "PC/AT Floppy Drive Controller (SM(s)C FDC37Cxxx)",
.internal_name = "fdc_at_smc",
.flags = 0,
.local = FDC_FLAG_AT | FDC_FLAG_SUPERIO,
.init = fdc_init,
.close = fdc_close,
.reset = fdc_reset,
{ .available = NULL },
.speed_changed = NULL,
.force_redraw = NULL,
.config = NULL
};
const device_t fdc_at_ali_device = {
.name = "PC/AT Floppy Drive Controller (ALi M512x/M1543C)",
.internal_name = "fdc_at_ali",
.flags = 0,
.local = FDC_FLAG_AT | FDC_FLAG_SUPERIO | FDC_FLAG_ALI,
.init = fdc_init,
.close = fdc_close,
.reset = fdc_reset,
{ .available = NULL },
.speed_changed = NULL,
.force_redraw = NULL,
.config = NULL
};
const device_t fdc_at_winbond_device = {
.name = "PC/AT Floppy Drive Controller (Winbond W83x77F)",
.internal_name = "fdc_at_winbond",
.flags = 0,
.local = FDC_FLAG_AT | FDC_FLAG_SUPERIO | FDC_FLAG_START_RWC_1 | FDC_FLAG_MORE_TRACKS,
.init = fdc_init,
.close = fdc_close,
.reset = fdc_reset,
{ .available = NULL },
.speed_changed = NULL,
.force_redraw = NULL,
.config = NULL
};
const device_t fdc_at_nsc_device = {
.name = "PC/AT Floppy Drive Controller (NSC PC8730x)",
.internal_name = "fdc_at_nsc",
.flags = 0,
.local = FDC_FLAG_AT | FDC_FLAG_MORE_TRACKS | FDC_FLAG_NSC,
.init = fdc_init,
.close = fdc_close,
.reset = fdc_reset,
{ .available = NULL },
.speed_changed = NULL,
.force_redraw = NULL,
.config = NULL
};
const device_t fdc_dp8473_device = {
.name = "NS DP8473 Floppy Drive Controller",
.internal_name = "fdc_dp8473",
.flags = 0,
.local = FDC_FLAG_AT | FDC_FLAG_NEC | FDC_FLAG_NO_DSR_RESET,
.init = fdc_init,
.close = fdc_close,
.reset = fdc_reset,
{ .available = NULL },
.speed_changed = NULL,
.force_redraw = NULL,
.config = NULL
};
const device_t fdc_um8398_device = {
.name = "UMC UM8398 Floppy Drive Controller",
.internal_name = "fdc_um8398",
.flags = 0,
.local = FDC_FLAG_UMC,
.init = fdc_init,
.close = fdc_close,
.reset = fdc_reset,
{ .available = NULL },
.speed_changed = NULL,
.force_redraw = NULL,
.config = NULL
};
``` | /content/code_sandbox/src/floppy/fdc.c | c | 2016-06-25T22:29:10 | 2024-08-16T19:09:21 | 86Box | 86Box/86Box | 2,616 | 24,612 |
```c
/*
* 86Box A hypervisor and IBM PC system emulator that specializes in
* running old operating systems and software designed for IBM
* PC systems and compatibles from 1981 through fairly recent
* system designs based on the PCI bus.
*
* This file is part of the 86Box distribution.
*
* Shared code for all the floppy modules.
*
*
*
* Authors: Fred N. van Kempen, <decwiz@yahoo.com>
*
*/
#include <stdio.h>
#include <stdint.h>
#include <string.h>
#include <stdlib.h>
#include <wchar.h>
#include <86box/86box.h>
#include <86box/timer.h>
#include <86box/fdd.h>
#include <86box/fdd_common.h>
const uint8_t fdd_holes[6] = { 0, 0, 0, 1, 1, 2 };
const uint8_t fdd_rates[6] = { 2, 2, 1, 4, 0, 3 };
const double fdd_bit_rates_300[6] = {
(250.0 * 300.0) / 360.0,
250.0,
300.0,
(500.0 * 300.0) / 360.0,
500.0,
1000.0
};
/*
* First dimension is possible sector sizes (0 = 128, 7 = 16384),
* second is possible bit rates (250/360, 250, 300, 500/360, 500, 1000).
*
* Disks formatted at 250 kbps @ 360 RPM can be read with a 360 RPM
* single-RPM 5.25" drive by setting the rate to 250 kbps.
*
* Disks formatted at 300 kbps @ 300 RPM can be read with any 300 RPM
* single-RPM drive by setting the rate to 300 kbps.
*/
const uint8_t fdd_max_sectors[8][6] = {
{ 26, 31, 38, 53, 64, 118 }, /* 128 */
{ 15, 19, 23, 32, 38, 73 }, /* 256 */
{ 7, 10, 12, 17, 22, 41 }, /* 512 */
{ 3, 5, 6, 9, 11, 22 }, /* 1024 */
{ 2, 2, 3, 4, 5, 11 }, /* 2048 */
{ 1, 1, 1, 2, 2, 5 }, /* 4096 */
{ 0, 0, 0, 1, 1, 3 }, /* 8192 */
{ 0, 0, 0, 0, 0, 1 } /* 16384 */
};
const uint8_t fdd_dmf_r[21] = {
12, 2, 13, 3, 14, 4, 15, 5, 16, 6, 17, 7, 18, 8, 19, 9, 20, 10, 21, 11, 1
};
static const uint8_t fdd_gap3_sizes[5][8][48] = {
{
{ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, /* [0][0] */
0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 },
{ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, /* [0][1] */
0x54,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 },
{ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, /* [0][2] */
0x00,0x00,0x6C,0x48,0x2A,0x08,0x02,0x01,
0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 },
{ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
0x00,0x00,0x83,0x26,0x00,0x00,0x00,0x00, /* [0][3] */
0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 },
{ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, /* [0][4] */
0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 },
{ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, /* [0][5] */
0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 },
{ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, /* [0][6] */
0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 },
{ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, /* [0][7] */
0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 }
},
{
{ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, /* [1][0] */
0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 },
{ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, /* [1][1] */
0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 },
{ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
0x00,0x00,0x00,0x54,0x1C,0x0E,0x00,0x00, /* [1][2] */
0x00,0x00,0x6C,0x48,0x2A,0x08,0x02,0x01,
0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 },
{ 0x00,0x00,0x00,0x00,0x00,0x00,0x79,0x06,
0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, /* [1][3] */
0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 },
{ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, /* [1][4] */
0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 },
{ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, /* [1][5] */
0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 },
{ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, /* [1][6] */
0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 },
{ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, /* [1][7] */
0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 }
},
{
{ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, /* [2][0] */
0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 },
{ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
0x00,0x00,0x32,0x0C,0x00,0x00,0x00,0x36, /* [2][1] */
0x32,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 },
{ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
0x58,0x50,0x2E,0x00,0x00,0x00,0x00,0x00, /* [2][2] */
0x00,0x00,0x00,0x00,0x00,0x1C,0x1C,0x00,
0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 },
{ 0x00,0x00,0x00,0x00,0xF0,0x74,0x00,0x00,
0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, /* [2][3] */
0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 },
{ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, /* [2][4] */
0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 },
{ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, /* [2][5] */
0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 },
{ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, /* [2][6] */
0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 },
{ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, /* [2][7] */
0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 }
},
{
{ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, /* [3][0] */
0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 },
{ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, /* [3][1] */
0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 },
{ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, /* [3][2] */
0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
0x00,0x00,0x00,0x00,0x53,0x4E,0x3D,0x2C,
0x1C,0x0D,0x02,0x00,0x00,0x00,0x01,0x00 },
{ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, /* [3][3] */
0x00,0x00,0xF7,0xAF,0x6F,0x55,0x1F,0x00,
0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 },
{ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, /* [3][4] */
0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 },
{ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, /* [3][5] */
0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 },
{ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, /* [3][6] */
0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 },
{ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, /* [3][7] */
0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 }
},
{
{ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, /* [4][0] */
0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 },
{ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, /* [4][1] */
0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
0x36,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 },
{ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
0x00,0x00,0x00,0x00,0x00,0x00,0x92,0x54, /* [4][2] */
0x38,0x23,0x00,0x01,0x00,0x00,0x00,0x00,
0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 },
{ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
0x74,0x24,0x00,0x00,0x00,0x00,0x00,0x00, /* [4][3] */
0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 },
{ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, /* [4][4] */
0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 },
{ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, /* [4][5] */
0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 },
{ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, /* [4][6] */
0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 },
{ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, /* [4][7] */
0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 }
}
};
int
fdd_get_gap3_size(int rate, int size, int sector)
{
return (fdd_gap3_sizes[rate][size][sector]);
}
uint8_t
fdd_sector_size_code(int size)
{
uint8_t ret = 2;
switch (size) {
case 128:
ret = 0;
break;
case 256:
ret = 1;
break;
case 512:
ret = 2;
break;
case 1024:
ret = 3;
break;
case 2048:
ret = 4;
break;
case 4096:
ret = 5;
break;
case 8192:
ret = 6;
break;
case 16384:
ret = 7;
break;
default:
break;
}
return ret;
}
int
fdd_sector_code_size(uint8_t code)
{
return (128 << code);
}
int
fdd_bps_valid(uint16_t bps)
{
for (uint8_t i = 0; i <= 8; i++) {
if (bps == (128 << i)) {
return 1;
}
}
return 0;
}
int
fdd_interleave(int sector, int skew, int spt)
{
uint32_t add = (spt & 1);
uint32_t adjust = (spt >> 1);
uint32_t adjusted_r;
uint32_t skewed_i;
skewed_i = (sector + skew) % spt;
adjusted_r = (skewed_i >> 1) + 1;
if (skewed_i & 1) {
adjusted_r += (adjust + add);
}
return adjusted_r;
}
``` | /content/code_sandbox/src/floppy/fdd_common.c | c | 2016-06-25T22:29:10 | 2024-08-16T19:09:21 | 86Box | 86Box/86Box | 2,616 | 9,692 |
```c
/*
* 86Box A hypervisor and IBM PC system emulator that specializes in
* running old operating systems and software designed for IBM
* PC systems and compatibles from 1981 through fairly recent
* system designs based on the PCI bus.
*
* This file is part of the 86Box distribution.
*
* Implementation of the pcjs v2 floppy image format (read-only)
*
* Authors: cold-brewed
*
*/
#include <stdarg.h>
#include <stdint.h>
#include <stdio.h>
#include <string.h>
#include <stdlib.h>
#include <wchar.h>
#include <unistd.h>
#define HAVE_STDARG_H
#include <86box/86box.h>
#include <86box/timer.h>
#include <86box/plat.h>
#include <86box/fdd.h>
#include <86box/fdd_86f.h>
#include <86box/fdd_common.h>
#include <86box/fdd_pcjs.h>
#include <cJSON.h>
static pcjs_t *images[FDD_NUM];
static pcjs_error_t pcjs_error = E_SUCCESS;
struct pcjs_error_description {
int code;
const char *message;
} pcjs_error_description[] = {
{ E_SUCCESS, "No error" },
{ E_MISSING_KEY, "The requested key was missing" },
{ E_UNEXPECTED_VALUE, "The value was not of the expected type" },
{ E_INTEGRITY, "Integrity check failed" },
{ E_INVALID_OBJECT, "Object is missing or invalid" },
{ E_ALLOC, "Memory allocation failure" },
{ E_PARSE, "Parsing failure" },
{ -1, "Unknown error" },
};
#ifdef ENABLE_PCJS_LOG
int pcjs_do_log = ENABLE_PCJS_LOG;
static void
pcjs_log(const char *fmt, ...)
{
if (pcjs_do_log) {
va_list ap;
va_start(ap, fmt);
pclog_ex(fmt, ap);
va_end(ap);
}
}
#else
# define pcjs_log(fmt, ...)
#endif
void
pcjs_init(void)
{
memset(images, 0x00, sizeof(images));
}
const char* pcjs_errmsg(void)
{
int i = 0;
while (pcjs_error_description[i].code >= 0) {
if (pcjs_error_description[i].code == pcjs_error) {
return pcjs_error_description[i].message;
}
i++;
}
return "Unknown error";
}
int parse_image_info(pcjs_t *dev, const cJSON *parsed_json)
{
const cJSON *imageInfo = NULL;
if(dev == NULL || parsed_json == NULL) {
pcjs_log("Null values passed\n");
pcjs_error = E_INTEGRITY;
return 1;
}
imageInfo = cJSON_GetObjectItemCaseSensitive(parsed_json, "imageInfo");
if (imageInfo == NULL || !cJSON_IsObject(imageInfo)) {
pcjs_log("imageInfo object does not exist or is invalid\n");
pcjs_error = E_INVALID_OBJECT;
return 1;
}
/* Macros are used here to avoid repetition */
/* First get strings */
IMAGE_INFO_GET_STRING(type)
IMAGE_INFO_GET_STRING(name)
IMAGE_INFO_GET_STRING(format)
IMAGE_INFO_GET_STRING(hash)
IMAGE_INFO_GET_STRING(version)
IMAGE_INFO_GET_STRING(repository)
/* Then the numbers */
IMAGE_INFO_GET_NUMBER(cylinders)
IMAGE_INFO_GET_NUMBER(heads)
IMAGE_INFO_GET_NUMBER(trackDefault)
IMAGE_INFO_GET_NUMBER(sectorDefault)
IMAGE_INFO_GET_NUMBER(diskSize)
/* Special cases */
/* Convert bootSector to array if it exists */
/* For some reason the array itself is stored as a string
* which needs to be converted into an array before parsing. */
dev->image_info.boot_sector_array_size = 0;
const cJSON *array_string = cJSON_GetObjectItemCaseSensitive(imageInfo, "bootSector");
cJSON *bootSector = NULL;
if(cJSON_IsString(array_string) && array_string != NULL) {
bootSector = cJSON_Parse(array_string->valuestring);
}
if(cJSON_IsArray(bootSector)) {
const int array_size = cJSON_GetArraySize(bootSector);
dev->image_info.boot_sector_array_size = array_size;
const cJSON *array_item = NULL;
int array_index = 0;
cJSON_ArrayForEach(array_item, bootSector)
{
/* Make sure each item is a number */
if(!cJSON_IsNumber(array_item)) {
pcjs_log("Non-number item in bootSector array\n");
dev->image_info.boot_sector_array_size = 0;
/* Prevent the loop from continuing */
array_item = NULL;
break;
}
/* Make sure each number is in range */
const int value = array_item->valueint;
if (value < 0 || value > 255) {
pcjs_log("bootSector value %i out of range (0-255)\n", value);
dev->image_info.boot_sector_array_size = 0;
/* Prevent the loop from continuing */
array_item = NULL;
break;
}
/* Make sure we don't exceed the array length */
if (array_index + 1 > PCJS_IMAGE_INFO_ARRAY_LEN) {
pcjs_log("bootSector array length exceeded (max %i)\n", PCJS_IMAGE_INFO_ARRAY_LEN);
dev->image_info.boot_sector_array_size = 0;
/* Prevent the loop from continuing */
array_item = NULL;
break;
}
dev->image_info.boot_sector[array_index] = value;
array_index++;
}
}
/* checksum: Can't use the number macro like the others because it uses valueInt
* which is 32-bit signed and we need unsigned. Use the double value (valuedouble) instead. */
const cJSON *checksum_json = cJSON_GetObjectItemCaseSensitive(imageInfo, "checksum");
if (cJSON_IsNumber(checksum_json)) {
dev->image_info.checksum = checksum_json->valuedouble;
} else {
pcjs_log("Required number value for \"%s\" missing from imageInfo\n", "checksum");
pcjs_error = E_MISSING_KEY;
cJSON_Delete(bootSector);
return 1;
}
/* Use the metadata as the official source */
dev->total_tracks = dev->image_info.cylinders;
dev->total_sides = dev->image_info.heads;
dev->total_sectors = dev->image_info.trackDefault;
cJSON_Delete(bootSector);
return 0;
}
int parse_file_table(pcjs_t *dev, const cJSON *parsed_json)
{
const cJSON *fileTable = NULL;
if(dev == NULL || parsed_json == NULL) {
pcjs_log("Null values passed\n");
pcjs_error = E_INTEGRITY;
return 1;
}
fileTable = cJSON_GetObjectItemCaseSensitive(parsed_json, "fileTable");
if (fileTable == NULL || !cJSON_IsArray(fileTable)) {
pcjs_log("fileTable object does not exist or is invalid\n");
pcjs_error = E_INVALID_OBJECT;
return 1;
}
const cJSON *each_file_table = NULL;
dev->file_table.num_entries = cJSON_GetArraySize(fileTable);
uint16_t processed_entries = 0;
uint16_t current_entry = 0;
if (dev->file_table.num_entries == 0) {
pcjs_log("No fileTable entries to process\n");
return 0;
}
pcjs_log("Processing %i file table entries\n", dev->file_table.num_entries);
/* Allocate the entries */
dev->file_table.entries = (pcjs_file_table_entry_t *)calloc(dev->file_table.num_entries, sizeof(pcjs_file_table_entry_t));
if (dev->file_table.entries == NULL ) {
pcjs_log("Failed to allocate file table entries\n");
pcjs_error = E_ALLOC;
return 1;
}
cJSON_ArrayForEach(each_file_table, fileTable)
{
/* The -1 length of the temporary buffer brought to you by gcc's -Wstringop-truncation */
char hash[PCJS_FILE_TABLE_STRING_LEN-1] = {0};
char path[PCJS_FILE_TABLE_STRING_LEN-1] = {0};
char attr[PCJS_FILE_TABLE_STRING_LEN-1] = {0};
char date[PCJS_FILE_TABLE_STRING_LEN-1] = {0};
uint16_t f_size = 0;
JSON_GET_OBJECT_STRING_OPTIONAL(hash, each_file_table, PCJS_OBJECT_KEY_FT_HASH)
JSON_GET_OBJECT_STRING_OPTIONAL(path, each_file_table, PCJS_OBJECT_KEY_FT_PATH)
JSON_GET_OBJECT_STRING_REQUIRED(attr, each_file_table, PCJS_OBJECT_KEY_FT_ATTR)
JSON_GET_OBJECT_STRING_REQUIRED(date, each_file_table, PCJS_OBJECT_KEY_FT_DATE)
JSON_GET_OBJECT_NUMBER_OPTIONAL(f_size, each_file_table, PCJS_OBJECT_KEY_FT_SIZE)
strncpy(dev->file_table.entries[current_entry].hash, hash, sizeof(dev->file_table.entries[current_entry].hash) - 1);
strncpy(dev->file_table.entries[current_entry].path, path, sizeof(dev->file_table.entries[current_entry].path) - 1);
strncpy(dev->file_table.entries[current_entry].attr, attr, sizeof(dev->file_table.entries[current_entry].attr) - 1);
strncpy(dev->file_table.entries[current_entry].date, date, sizeof(dev->file_table.entries[current_entry].date) - 1);
dev->file_table.entries[current_entry].size = f_size;
processed_entries++;
current_entry++;
}
if(processed_entries != dev->file_table.num_entries) {
pcjs_log("fileTable entries processed (%i) inconsistent with number of entries in the table (%i)\n", processed_entries, dev->file_table.num_entries);
pcjs_error = E_INTEGRITY;
goto fail;
}
return 0;
fail:
/* Deallocate the array */
free(dev->file_table.entries);
return 1;
}
int json_parse(pcjs_t *dev)
{
const cJSON *diskData = NULL;
/* Determine the size of the file, reset back */
fseek(dev->fp, 0L, SEEK_END);
const long numbytes = ftell(dev->fp);
fseek(dev->fp, 0L, SEEK_SET);
/* Allocate memory for the contents */
char *buffer = calloc(numbytes + 1, sizeof(char));
if(buffer == NULL) {
pcjs_error = E_ALLOC;
return 1;
}
/* Read and null terminate */
(void) !fread(buffer, sizeof(char), numbytes, dev->fp);
buffer[numbytes] = '\0';
cJSON *parsed_json = cJSON_Parse(buffer);
if (parsed_json == NULL)
{
const char *error_ptr = cJSON_GetErrorPtr();
if (error_ptr != NULL) {
fprintf(stderr, "Error parsing json before: %s\n", error_ptr);
}
pcjs_error = E_PARSE;
goto fail;
}
if(parse_image_info(dev, parsed_json)) {
pcjs_log("Failed to parse imageInfo metadata\n");
goto fail;
}
/* File table metadata is optional */
if(parse_file_table(dev, parsed_json)) {
pcjs_log("File table metadata is not present or invalid\n");
}
diskData = cJSON_GetObjectItemCaseSensitive(parsed_json, "diskData");
const cJSON *each_track = NULL;
int total_c = 0;
/* The diskData array is essentially [c][h][s] */
/* Start with the tracks in [c] */
cJSON_ArrayForEach(each_track, diskData)
{
int total_heads = 0;
const cJSON *each_head = NULL;
/* For each track, loop on each head */
/* Now in [c][h] */
cJSON_ArrayForEach(each_head, each_track)
{
int total_sectors = 0;
const cJSON *each_sector = NULL;
/* Now loop on the sectors in [c][h][s] */
/* Each sector item will have the information needed to fill in a pcjs_sector_t */
cJSON_ArrayForEach(each_sector, each_head)
{
const cJSON *data = NULL;
const cJSON *each_data = NULL;
int data_array_size = 0;
int total_d = 0;
int32_t current_track = 0;
int32_t current_head = 0;
int32_t current_sector = 0;
int32_t current_length = 0;
int32_t file_mapping = 0;
int32_t offset = 0;
pcjs_sector_t *sector = NULL;
/* Macros to keep things tidy */
JSON_GET_OBJECT_NUMBER_REQUIRED(current_track, each_sector, PCJS_OBJECT_KEY_TRACK)
JSON_GET_OBJECT_NUMBER_REQUIRED(current_head, each_sector, PCJS_OBJECT_KEY_HEAD)
JSON_GET_OBJECT_NUMBER_REQUIRED(current_sector, each_sector, PCJS_OBJECT_KEY_SECTOR)
JSON_GET_OBJECT_NUMBER_REQUIRED(current_length, each_sector, PCJS_OBJECT_KEY_LENGTH)
JSON_GET_OBJECT_NUMBER_OPTIONAL_DEFAULT(offset, each_sector, PCJS_OBJECT_KEY_OFFSET, -1)
JSON_GET_OBJECT_NUMBER_OPTIONAL_DEFAULT(file_mapping, each_sector, PCJS_OBJECT_KEY_FILE, -1)
/* NOTE: The sectors array is zero indexed, but the metadata for each sector shows its conventional sector number */
sector = &dev->sectors[current_track][current_head][current_sector-1];
if (sector->data == NULL ) {
/* We could verify the sector size against the metadata here */
sector->data = (uint8_t *)calloc(1, current_length);
if (sector->data == NULL ) {
pcjs_log("Failed to allocate\n");
pcjs_error = E_ALLOC;
goto fail;
}
}
sector->track = current_track;
sector->side = current_head;
sector->sector = current_sector;
sector->size = current_length;
sector->encoded_size = fdd_sector_size_code(current_length);
sector->offset = offset;
sector->file = file_mapping;
sector->pattern_repeat = 0;
sector->last_entry = 0;
data = cJSON_GetObjectItemCaseSensitive(each_sector, PCJS_OBJECT_KEY_DATA);
if(data != NULL && cJSON_IsArray(data)) {
data_array_size = cJSON_GetArraySize(data);
cJSON_ArrayForEach(each_data, data)
{
/* total_d is our current position in the data array */
/* That number will be used to determine where to store the
* value in its destination (sector->data).
* Each value in the data array is a 32-bit integer, but the
* destination (sector->data) is a uint8_t array. Therefore
* we'll need to manually calculate offsets and place the bytes.
*/
const int dest_offset = total_d * 4;
if(total_d == data_array_size - 1) {
/* This is the last value in the data array. Check to see if we'll need it
* for the repeating pattern.
* We use current_length / 4 because each data element is 32 bits in size.
* For example, if current_length = 512
* then 512 / 4 = 128
* so anything less than that value will have padding */
if (total_d + 1 < current_length / 4) {
sector->last_entry = each_data->valueint;
/* total_d + 1 because it is zero indexed at this point */
sector->pattern_repeat = current_length / 4 - (total_d + 1);
}
}
const int value = each_data->valueint;
/* Take each value and shift in as necessary */
for (int i = 0; i < 4; i++) {
sector->data[dest_offset + i] = (value >> i * 8) & 0xff;
}
total_d++;
}
} else {
pcjs_log("Data array missing from [%d][%d][%d]", current_track, current_head, current_sector);
pcjs_error = E_MISSING_KEY;
goto fail;
}
/* Fill in the repeating pattern if needed */
/* total_d was already advanced at the end of the previous loop */
for (int i = 0; i < sector->pattern_repeat; i++ ) {
const int position = total_d + i;
const int dest_offset = position * 4;
if(position >= (sector->size / 4)) {
/* Something is wrong */
pcjs_log("Out of bounds write attempt to data array at %i", position);
pcjs_error = E_INTEGRITY;
goto fail;
}
for (int j = 0; j < 4; j++) {
sector->data[dest_offset + j] = (sector->last_entry >> j * 8) & 0xff;
}
}
total_sectors++;
dev->calc_total_sectors = total_sectors;
/* End sectors */
}
dev->spt[total_c][total_heads] = total_sectors;
total_heads++;
dev->calc_total_sides = total_heads;
/* End heads */
}
total_c++;
dev->calc_total_tracks = total_c;
/* End tracks */
}
pcjs_log("calculated totals: c/h/s %i/%i/%i\n", dev->calc_total_tracks, dev->calc_total_sides, dev->calc_total_sectors);
pcjs_log("metadata totals: c/h/s %i/%i/%i\n", dev->image_info.cylinders, dev->image_info.heads, dev->image_info.trackDefault);
free(buffer);
cJSON_Delete(parsed_json);
return 0;
fail:
free(buffer);
cJSON_Delete(parsed_json);
return pcjs_error;
}
/* Handlers */
static uint16_t
disk_flags(int drive)
{
const pcjs_t *dev = images[drive];
return dev->disk_flags;
}
static uint16_t
track_flags(int drive)
{
const pcjs_t *dev = images[drive];
return dev->track_flags;
}
static void
set_sector(int drive, int side, uint8_t c, uint8_t h, uint8_t r, uint8_t n)
{
pcjs_t *dev = images[drive];
dev->current_sector[side] = 0;
/* Make sure we are on the desired track. */
if (c != dev->current_track)
return;
/* Set the desired side. */
dev->current_side = side;
/* Sectors are stored zero indexed, but sector zero should not be requested */
if(r == 0) {
pcjs_log("set_sector: Sector 0 requested?\n");
} else {
dev->current_sector[side] = r - 1;
}
/* The ifdef is necessary because if ENABLE_PCJS_LOG is not defined gcc throws an unused variable warning */
#ifdef ENABLE_PCJS_LOG
const int file_index = dev->sectors[dev->current_track][side][dev->current_sector[side]].file;
pcjs_log("set sector: %i/%i/%i %s%s%s\n", c, h, r,
file_index == -1 ? "" : "(",
file_index == -1 ? "" : dev->file_table.entries[file_index].path,
file_index == -1 ? "" : ")");
#endif
}
static uint8_t
poll_read_data(int drive, int side, uint16_t pos)
{
const pcjs_t *dev = images[drive];
const uint8_t sec = dev->current_sector[side];
return (dev->sectors[dev->current_track][side][sec].data[pos]);
}
static void
pcjs_seek(int drive, int track)
{
uint8_t id[4] = { 0, 0, 0, 0 };
pcjs_t *dev = images[drive];
int rate;
int gap2;
int gap3;
int pos;
int ssize;
int rsec;
int asec;
if (dev->fp == NULL) {
pcjs_log("pcjs_seek: no file loaded\n");
return;
}
/* Allow for doublestepping tracks. */
if (!dev->track_width && fdd_doublestep_40(drive))
track /= 2;
/* Set the new track. */
dev->current_track = track;
d86f_set_cur_track(drive, track);
/* Reset the 86F state machine. */
d86f_reset_index_hole_pos(drive, 0);
d86f_destroy_linked_lists(drive, 0);
d86f_reset_index_hole_pos(drive, 1);
d86f_destroy_linked_lists(drive, 1);
if (track > dev->total_tracks) {
d86f_zero_track(drive);
return;
}
pcjs_log("seeking to track %i\n", track);
for (uint8_t side = 0; side < dev->total_sides; side++) {
/* Get transfer rate for this side. */
rate = dev->track_flags & 0x07;
if (!rate && (dev->track_flags & 0x20))
rate = 4;
/* Get correct GAP3 value for this side. */
gap3 = fdd_get_gap3_size(rate,
// dev->sectors[track][side][0].size,
dev->sectors[track][side][0].encoded_size,
dev->spt[track][side]);
/* Get correct GAP2 value for this side. */
gap2 = ((dev->track_flags & 0x07) >= 3) ? 41 : 22;
pos = d86f_prepare_pretrack(drive, side, 0);
for (uint8_t sector = 0; sector < dev->spt[track][side]; sector++) {
rsec = dev->sectors[track][side][sector].sector;
asec = sector;
id[0] = track;
id[1] = side;
id[2] = rsec;
if (dev->sectors[track][side][asec].encoded_size > 255)
perror("PCJS: pcjs_seek: sector size too big.");
id[3] = dev->sectors[track][side][asec].encoded_size & 0xff;
ssize = fdd_sector_code_size(dev->sectors[track][side][asec].encoded_size & 0xff);
pos = d86f_prepare_sector(
drive, side, pos, id,
dev->sectors[track][side][asec].data,
ssize, gap2, gap3,
0
);
if (sector == 0)
d86f_initialize_last_sector_id(drive, id[0], id[1], id[2], id[3]);
}
}
}
static int
pcjs_load_image(pcjs_t *dev)
{
if (dev->fp == NULL) {
pcjs_log("No file loaded!\n");
return 1;
}
/* Initialize. */
for (uint16_t i = 0; i < PCJS_MAX_TRACKS; i++) {
for (uint8_t j = 0; j < PCJS_MAX_SIDES; j++)
memset(dev->sectors[i][j], 0x00, sizeof(pcjs_sector_t));
}
dev->current_track = 0;
dev->current_side = 0;
return json_parse(dev);
}
void
pcjs_load(int drive, char *fn)
{
double bit_rate = 0;
int temp_rate;
const pcjs_sector_t *sector;
pcjs_t *dev;
d86f_unregister(drive);
/* Allocate a drive block */
dev = (pcjs_t *) malloc(sizeof(pcjs_t));
memset(dev, 0x00, sizeof(pcjs_t));
/* Open the image file, read-only */
dev->fp = plat_fopen(fn, "rb");
if (dev->fp == NULL) {
free(dev);
memset(fn, 0x00, sizeof(char));
return;
}
pcjs_log("Opening filename: %s\n", fn);
/* Always set the drive to write-protected mode */
writeprot[drive] = 1;
/* Place in the correct slot */
images[drive] = dev;
/* Parse and load the information from the json file */
if (pcjs_load_image(dev)) {
pcjs_log("Failed to initialize: %s\n", pcjs_errmsg());
(void) fclose(dev->fp);
free(dev);
images[drive] = NULL;
memset(fn, 0x00, sizeof(char));
return;
}
pcjs_log("Drive %d: %s (%i tracks, %i sides, %i sectors, sector size %i)\n",
drive, fn, dev->image_info.cylinders, dev->image_info.heads, dev->image_info.trackDefault, dev->image_info.sectorDefault);
/*
* If the image has more than 43 tracks, then
* the tracks are thin (96 tpi).
*/
dev->track_width = (dev->total_tracks > 43) ? 1 : 0;
/* If the image has 2 sides, mark it as such. */
dev->disk_flags = 0x00;
if (dev->total_sides == 2)
dev->disk_flags |= 0x08;
/* PCJS files are always assumed to be MFM-encoded. */
dev->track_flags = 0x08;
dev->interleave = 0;
temp_rate = 0xff;
sector = &dev->sectors[0][0][0];
for (uint8_t i = 0; i < 6; i++) {
if (dev->spt[0][0] > fdd_max_sectors[sector->encoded_size][i])
continue;
bit_rate = fdd_bit_rates_300[i];
temp_rate = fdd_rates[i];
dev->disk_flags |= (fdd_holes[i] << 1);
if ((bit_rate == 500.0) && (dev->spt[0][0] == 21) && (sector->encoded_size == 2) && (dev->total_tracks >= 80) && (dev->total_tracks <= 82) && (dev->total_sides == 2)) {
/*
* This is a DMF floppy, set the flag so
* we know to interleave the sectors.
*/
dev->dmf = 1;
} else {
if ((bit_rate == 500.0) && (dev->spt[0][0] == 22) && (sector->encoded_size == 2) && (dev->total_tracks >= 80) && (dev->total_tracks <= 82) && (dev->total_sides == 2)) {
/*
* This is marked specially because of the
* track flag (a RPM slow down is needed).
*/
dev->interleave = 2;
}
dev->dmf = 0;
}
break;
}
if (temp_rate == 0xff) {
pcjs_log("Invalid image (temp_rate=0xff)\n");
(void) fclose(dev->fp);
dev->fp = NULL;
free(dev);
images[drive] = NULL;
memset(fn, 0x00, sizeof(char));
return;
}
if (dev->interleave == 2) {
dev->interleave = 1;
dev->disk_flags |= 0x60;
}
dev->gap2_len = (temp_rate == 3) ? 41 : 22;
if (dev->dmf)
dev->gap3_len = 8;
else
dev->gap3_len = fdd_get_gap3_size(temp_rate, sector->encoded_size, dev->spt[0][0]);
if (!dev->gap3_len) {
pcjs_log("Image of unknown format was inserted into drive %c:\n",
'C' + drive);
(void) fclose(dev->fp);
dev->fp = NULL;
free(dev);
images[drive] = NULL;
memset(fn, 0x00, sizeof(char));
return;
}
dev->track_flags |= (temp_rate & 0x03); /* data rate */
if (temp_rate & 0x04)
dev->track_flags |= 0x20; /* RPM */
pcjs_log(" disk_flags: 0x%02x, track_flags: 0x%02x, GAP3 length: %i\n",
dev->disk_flags, dev->track_flags, dev->gap3_len);
pcjs_log(" bit rate 300: %.2f, temporary rate: %i, hole: %i, DMF: %i\n",
bit_rate, temp_rate, (dev->disk_flags >> 1), dev->dmf);
pcjs_log(" encoded_size: %i spt: %i\n", sector->encoded_size, dev->spt[0][0]);
/* Set up 86F handlers */
d86f_handler[drive].disk_flags = disk_flags;
d86f_handler[drive].side_flags = track_flags;
d86f_handler[drive].writeback = null_writeback;
d86f_handler[drive].set_sector = set_sector;
d86f_handler[drive].read_data = poll_read_data;
d86f_handler[drive].write_data = null_write_data;
d86f_handler[drive].format_conditions = null_format_conditions;
d86f_handler[drive].extra_bit_cells = null_extra_bit_cells;
d86f_handler[drive].encoded_data = common_encoded_data;
d86f_handler[drive].read_revolution = common_read_revolution;
d86f_handler[drive].index_hole_pos = null_index_hole_pos;
d86f_handler[drive].get_raw_size = common_get_raw_size;
d86f_handler[drive].check_crc = 1;
d86f_set_version(drive, 0x0063);
d86f_common_handlers(drive);
drives[drive].seek = pcjs_seek;
}
void
pcjs_close(int drive)
{
pcjs_t *dev = images[drive];
if (dev == NULL)
return;
/* Unlink image from the system. */
d86f_unregister(drive);
/* Release all the sector buffers. */
for (int c = 0; c < PCJS_MAX_TRACKS; c++) {
for (int h = 0; h < PCJS_MAX_SIDES; h++) {
for (uint16_t s = 0; s < PCJS_MAX_SECTORS; s++) {
if (dev->sectors[c][h][s].data != NULL)
free(dev->sectors[c][h][s].data);
dev->sectors[c][h][s].data = NULL;
}
}
}
/* Release file table entries */
if(dev->file_table.entries != NULL)
free(dev->file_table.entries);
dev->file_table.entries = NULL;
dev->file_table.num_entries = 0;
if (dev->fp != NULL)
(void) fclose(dev->fp);
/* Release the memory. */
free(dev);
images[drive] = NULL;
}
``` | /content/code_sandbox/src/floppy/fdd_pcjs.c | c | 2016-06-25T22:29:10 | 2024-08-16T19:09:21 | 86Box | 86Box/86Box | 2,616 | 6,966 |
```c
/*
* VARCem Virtual ARchaeological Computer EMulator.
* An emulator of (mostly) x86-based PC systems and devices,
* using the ISA,EISA,VLB,MCA and PCI system buses, roughly
* spanning the era between 1981 and 1995.
*
* Implementation of the DTK MiniMicro series of Floppy Disk Controllers.
* Original code from VARCem. Fully rewritten, fixed and improved for 86Box.
*
* Authors: Fred N. van Kempen, <decwiz@yahoo.com>,
* Tiseno100
*
*
* Redistribution and use in source and binary forms, with
* or without modification, are permitted provided that the
* following conditions are met:
*
* 1. Redistributions of source code must retain the entire
* above notice, this list of conditions and the following
* disclaimer.
*
* 2. Redistributions in binary form must reproduce the above
* copyright notice, this list of conditions and the
* following disclaimer in the documentation and/or other
* materials provided with the distribution.
*
* 3. Neither the name of the copyright holder nor the names
* of its contributors may be used to endorse or promote
* products derived from this software without specific
* prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
* PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
/*
Notes:
VARCem uses the DP8473 for both floppy disk controllers. The statement though is wrong.
MiniMicro 4 uses a Zilog Z0765A08PSC(Clone of the NEC 765)
MiniMicro 1 uses a National Semiconductor DP8473(Clone of the NEC 765 with additional NSC commands)
Issues:
MiniMicro 4 works only with a few XT machines. This statement has to be confirmed by someone with the real card itself.
MiniMicro 4 also won't work with the XT FDC which the Zilog claims to be.
*/
#include <stdarg.h>
#include <stdint.h>
#include <stdio.h>
#include <string.h>
#include <stdlib.h>
#include <wchar.h>
#define HAVE_STDARG_H
#include <86box/86box.h>
#include <86box/device.h>
#include <86box/io.h>
#include <86box/mem.h>
#include <86box/rom.h>
#include <86box/machine.h>
#include <86box/timer.h>
#include <86box/fdd.h>
#include <86box/fdc.h>
#include <86box/fdc_ext.h>
#define DTK_VARIANT ((info->local == 158) ? ROM_PII_158B : ROM_PII_151B)
#define DTK_CHIP ((info->local == 158) ? &fdc_xt_device : &fdc_dp8473_device)
#define BIOS_ADDR (uint32_t)(device_get_config_hex20("bios_addr") & 0x000fffff)
#define ROM_PII_151B "roms/floppy/dtk/pii-151b.rom"
#define ROM_PII_158B "roms/floppy/dtk/pii-158b.rom"
typedef struct pii_t {
rom_t bios_rom;
} pii_t;
static void
pii_close(void *priv)
{
pii_t *dev = (pii_t *) priv;
free(dev);
}
static void *
pii_init(const device_t *info)
{
pii_t *dev;
dev = (pii_t *) malloc(sizeof(pii_t));
memset(dev, 0, sizeof(pii_t));
if (BIOS_ADDR != 0)
rom_init(&dev->bios_rom, DTK_VARIANT, BIOS_ADDR, 0x2000, 0x1ffff, 0, MEM_MAPPING_EXTERNAL);
device_add(DTK_CHIP);
return dev;
}
static int
pii_151b_available(void)
{
return rom_present(ROM_PII_151B);
}
static int
pii_158_available(void)
{
return rom_present(ROM_PII_158B);
}
static const device_config_t pii_config[] = {
// clang-format off
{
.name = "bios_addr",
.description = "BIOS Address:",
.type = CONFIG_HEX20,
.default_string = "",
.default_int = 0xce000,
.file_filter = "",
.spinner = { 0 },
.selection = {
{ .description = "Disabled", .value = 0 },
{ .description = "CA00H", .value = 0xca000 },
{ .description = "CC00H", .value = 0xcc000 },
{ .description = "CE00H", .value = 0xce000 },
{ .description = "" }
}
},
{ .name = "", .description = "", .type = CONFIG_END }
// clang-format on
};
const device_t fdc_pii151b_device = {
.name = "DTK PII-151B (MiniMicro) Floppy Drive Controller",
.internal_name = "dtk_pii151b",
.flags = DEVICE_ISA,
.local = 151,
.init = pii_init,
.close = pii_close,
.reset = NULL,
{ .available = pii_151b_available },
.speed_changed = NULL,
.force_redraw = NULL,
.config = pii_config
};
const device_t fdc_pii158b_device = {
.name = "DTK PII-158B (MiniMicro4) Floppy Drive Controller",
.internal_name = "dtk_pii158b",
.flags = DEVICE_ISA,
.local = 158,
.init = pii_init,
.close = pii_close,
.reset = NULL,
{ .available = pii_158_available },
.speed_changed = NULL,
.force_redraw = NULL,
.config = pii_config
};
``` | /content/code_sandbox/src/floppy/fdc_pii15xb.c | c | 2016-06-25T22:29:10 | 2024-08-16T19:09:21 | 86Box | 86Box/86Box | 2,616 | 1,483 |
```objective-c
/* config.h.in. Generated automatically from configure.in by autoheader 2.13. */
/* Define to empty if the keyword does not work. */
#undef const
/* Define if you have the ANSI C header files. */
#undef STDC_HEADERS
/* The number of bytes in a int. */
#undef SIZEOF_INT
/* The number of bytes in a long. */
#undef SIZEOF_LONG
/* The number of bytes in a short. */
#undef SIZEOF_SHORT
``` | /content/code_sandbox/src/floppy/lzf/config.h | objective-c | 2016-06-25T22:29:10 | 2024-08-16T19:09:21 | 86Box | 86Box/86Box | 2,616 | 104 |
```objective-c
/*
*
* Redistribution and use in source and binary forms, with or without modifica-
* tion, are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MER-
* CHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO
* EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPE-
* CIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTH-
* ERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED
* OF THE POSSIBILITY OF SUCH DAMAGE.
*
* Alternatively, the contents of this file may be used under the terms of
* in which case the provisions of the GPL are applicable instead of
* the above. If you wish to allow the use of your version of this file
* only under the terms of the GPL and not to allow others to use your
* version of this file under the BSD license, indicate your decision
* by deleting the provisions above and replace them with the notice
* and other provisions required by the GPL. If you do not delete the
* provisions above, a recipient may use your version of this file under
* either the BSD or the GPL.
*/
#ifndef LZFP_h
#define LZFP_h
#define STANDALONE 1 /* at the moment, this is ok. */
#ifndef STANDALONE
# include "lzf.h"
#endif
/*
* Size of hashtable is (1 << HLOG) * sizeof (char *)
* decompression is independent of the hash table size
* the difference between 15 and 14 is very small
* for small blocks (and 14 is usually a bit faster).
* For a low-memory/faster configuration, use HLOG == 13;
* For best compression, use 15 or 16 (or more, up to 22).
*/
#ifndef HLOG
# define HLOG 16
#endif
/*
* Sacrifice very little compression quality in favour of compression speed.
* This gives almost the same compression as the default code, and is
* (very roughly) 15% faster. This is the preferred mode of operation.
*/
#ifndef VERY_FAST
# define VERY_FAST 1
#endif
/*
* Sacrifice some more compression quality in favour of compression speed.
* (roughly 1-2% worse compression for large blocks and
* 9-10% for small, redundant, blocks and >>20% better speed in both cases)
* In short: when in need for speed, enable this for binary data,
* possibly disable this for text data.
*/
#ifndef ULTRA_FAST
# define ULTRA_FAST 1
#endif
/*
* Unconditionally aligning does not cost very much, so do it if unsure
*/
#ifndef STRICT_ALIGN
# define STRICT_ALIGN !(defined(__i386) || defined (__amd64))
#endif
/*
* You may choose to pre-set the hash table (might be faster on some
* modern cpus and large (>>64k) blocks, and also makes compression
* deterministic/repeatable when the configuration otherwise is the same).
*/
#ifndef INIT_HTAB
# define INIT_HTAB 1
#endif
/*
* Avoid assigning values to errno variable? for some embedding purposes
* (linux kernel for example), this is necessary. NOTE: this breaks
* the documentation in lzf.h. Avoiding errno has no speed impact.
*/
#ifndef AVOID_ERRNO
# define AVOID_ERRNO 0
#endif
/*
* Whether to pass the LZF_STATE variable as argument, or allocate it
* on the stack. For small-stack environments, define this to 1.
* NOTE: this breaks the prototype in lzf.h.
*/
#ifndef LZF_STATE_ARG
# define LZF_STATE_ARG 0
#endif
/*
* Whether to add extra checks for input validity in lzf_decompress
* and return EINVAL if the input stream has been corrupted. This
* only shields against overflowing the input buffer and will not
* detect most corrupted streams.
* This check is not normally noticeable on modern hardware
* (<1% slowdown), but might slow down older cpus considerably.
*/
#ifndef CHECK_INPUT
# define CHECK_INPUT 1
#endif
/*
* Whether to store pointers or offsets inside the hash table. On
* 64 bit architetcures, pointers take up twice as much space,
* and might also be slower. Default is to autodetect.
*/
/*#define LZF_USER_OFFSETS autodetect */
/*****************************************************************************/
/* nothing should be changed below */
#ifdef __cplusplus
# include <cstring>
# include <climits>
using namespace std;
#else
# include <string.h>
# include <limits.h>
#endif
#ifndef LZF_USE_OFFSETS
# if defined(_WIN32)
# define LZF_USE_OFFSETS defined(_M_X64)
# else
# if __cplusplus > 199711L
# include <cstdint>
# else
# include <stdint.h>
# endif
# define LZF_USE_OFFSETS (UINTPTR_MAX > 0xffffffffU)
# endif
#endif
typedef unsigned char u8;
#if LZF_USE_OFFSETS
# define LZF_HSLOT_BIAS ((const u8 *)in_data)
typedef unsigned int LZF_HSLOT;
#else
# define LZF_HSLOT_BIAS 0
typedef const u8 *LZF_HSLOT;
#endif
typedef LZF_HSLOT LZF_STATE[1 << (HLOG)];
#if !STRICT_ALIGN
/* for unaligned accesses we need a 16 bit datatype. */
# if USHRT_MAX == 65535
typedef unsigned short u16;
# elif UINT_MAX == 65535
typedef unsigned int u16;
# else
# undef STRICT_ALIGN
# define STRICT_ALIGN 1
# endif
#endif
#if ULTRA_FAST
# undef VERY_FAST
#endif
#endif
``` | /content/code_sandbox/src/floppy/lzf/lzfP.h | objective-c | 2016-06-25T22:29:10 | 2024-08-16T19:09:21 | 86Box | 86Box/86Box | 2,616 | 1,378 |
```c
/*
*
* Redistribution and use in source and binary forms, with or without modifica-
* tion, are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MER-
* CHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO
* EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPE-
* CIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTH-
* ERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED
* OF THE POSSIBILITY OF SUCH DAMAGE.
*
* Alternatively, the contents of this file may be used under the terms of
* in which case the provisions of the GPL are applicable instead of
* the above. If you wish to allow the use of your version of this file
* only under the terms of the GPL and not to allow others to use your
* version of this file under the BSD license, indicate your decision
* by deleting the provisions above and replace them with the notice
* and other provisions required by the GPL. If you do not delete the
* provisions above, a recipient may use your version of this file under
* either the BSD or the GPL.
*/
#include "lzfP.h"
#if AVOID_ERRNO
# define SET_ERRNO(n)
#else
# include <errno.h>
# define SET_ERRNO(n) errno = (n)
#endif
#if USE_REP_MOVSB /* small win on amd, big loss on intel */
#if (__i386 || __amd64) && __GNUC__ >= 3
# define lzf_movsb(dst, src, len) \
asm ("rep movsb" \
: "=D" (dst), "=S" (src), "=c" (len) \
: "0" (dst), "1" (src), "2" (len));
#endif
#endif
unsigned int
lzf_decompress (const void *const in_data, unsigned int in_len,
void *out_data, unsigned int out_len)
{
u8 const *ip = (const u8 *)in_data;
u8 *op = (u8 *)out_data;
u8 const *const in_end = ip + in_len;
u8 *const out_end = op + out_len;
do
{
unsigned int ctrl = *ip++;
if (ctrl < (1 << 5)) /* literal run */
{
ctrl++;
if (op + ctrl > out_end)
{
SET_ERRNO (E2BIG);
return 0;
}
#if CHECK_INPUT
if (ip + ctrl > in_end)
{
SET_ERRNO (EINVAL);
return 0;
}
#endif
#ifdef lzf_movsb
lzf_movsb (op, ip, ctrl);
#else
switch (ctrl)
{
case 32: *op++ = *ip++; case 31: *op++ = *ip++; case 30: *op++ = *ip++; case 29: *op++ = *ip++;
case 28: *op++ = *ip++; case 27: *op++ = *ip++; case 26: *op++ = *ip++; case 25: *op++ = *ip++;
case 24: *op++ = *ip++; case 23: *op++ = *ip++; case 22: *op++ = *ip++; case 21: *op++ = *ip++;
case 20: *op++ = *ip++; case 19: *op++ = *ip++; case 18: *op++ = *ip++; case 17: *op++ = *ip++;
case 16: *op++ = *ip++; case 15: *op++ = *ip++; case 14: *op++ = *ip++; case 13: *op++ = *ip++;
case 12: *op++ = *ip++; case 11: *op++ = *ip++; case 10: *op++ = *ip++; case 9: *op++ = *ip++;
case 8: *op++ = *ip++; case 7: *op++ = *ip++; case 6: *op++ = *ip++; case 5: *op++ = *ip++;
case 4: *op++ = *ip++; case 3: *op++ = *ip++; case 2: *op++ = *ip++; case 1: *op++ = *ip++;
}
#endif
}
else /* back reference */
{
unsigned int len = ctrl >> 5;
u8 *ref = op - ((ctrl & 0x1f) << 8) - 1;
#if CHECK_INPUT
if (ip >= in_end)
{
SET_ERRNO (EINVAL);
return 0;
}
#endif
if (len == 7)
{
len += *ip++;
#if CHECK_INPUT
if (ip >= in_end)
{
SET_ERRNO (EINVAL);
return 0;
}
#endif
}
ref -= *ip++;
if (op + len + 2 > out_end)
{
SET_ERRNO (E2BIG);
return 0;
}
if (ref < (u8 *)out_data)
{
SET_ERRNO (EINVAL);
return 0;
}
#ifdef lzf_movsb
len += 2;
lzf_movsb (op, ref, len);
#else
switch (len)
{
default:
len += 2;
if (op >= ref + len)
{
/* disjunct areas */
memcpy (op, ref, len);
op += len;
}
else
{
/* overlapping, use octte by octte copying */
do
*op++ = *ref++;
while (--len);
}
break;
case 9: *op++ = *ref++;
case 8: *op++ = *ref++;
case 7: *op++ = *ref++;
case 6: *op++ = *ref++;
case 5: *op++ = *ref++;
case 4: *op++ = *ref++;
case 3: *op++ = *ref++;
case 2: *op++ = *ref++;
case 1: *op++ = *ref++;
case 0: *op++ = *ref++; /* two octets more */
*op++ = *ref++;
}
#endif
}
}
while (ip < in_end);
return op - (u8 *)out_data;
}
``` | /content/code_sandbox/src/floppy/lzf/lzf_d.c | c | 2016-06-25T22:29:10 | 2024-08-16T19:09:21 | 86Box | 86Box/86Box | 2,616 | 1,597 |
```c
/*
*
* Redistribution and use in source and binary forms, with or without modifica-
* tion, are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MER-
* CHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO
* EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPE-
* CIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTH-
* ERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED
* OF THE POSSIBILITY OF SUCH DAMAGE.
*
* Alternatively, the contents of this file may be used under the terms of
* in which case the provisions of the GPL are applicable instead of
* the above. If you wish to allow the use of your version of this file
* only under the terms of the GPL and not to allow others to use your
* version of this file under the BSD license, indicate your decision
* by deleting the provisions above and replace them with the notice
* and other provisions required by the GPL. If you do not delete the
* provisions above, a recipient may use your version of this file under
* either the BSD or the GPL.
*/
#include "config.h"
#include <stdio.h>
#include <string.h>
#include <stdlib.h>
#include <unistd.h>
#include <sys/types.h>
#include <sys/stat.h>
#include <fcntl.h>
#include <errno.h>
#include <limits.h>
#include "lzf.h"
#ifdef HAVE_GETOPT_H
# include <getopt.h>
#endif
#define BLOCKSIZE (1024 * 64 - 1)
#define MAX_BLOCKSIZE BLOCKSIZE
typedef unsigned char u8;
static off_t nr_read, nr_written;
static const char *imagename;
static enum { compress, uncompress, lzcat } mode = compress;
static int verbose = 0;
static int force = 0;
static long blocksize = BLOCKSIZE;
#ifdef HAVE_GETOPT_LONG
struct option longopts[] = {
{"compress", 0, 0, 'c'},
{"decompress", 0, 0, 'd'},
{"uncompress", 0, 0, 'd'},
{"force", 0, 0, 'f'},
{"help", 0, 0, 'h'},
{"verbose", 0, 0, 'v'},
{"blocksize", 1, 0, 'b'},
{0, 0, 0, 0}
};
static const char *opt =
"-c --compress compress\n"
"-d --decompress decompress\n"
"-f --force force overwrite of output file\n"
"-h --help give this help\n" "-v --verbose verbose mode\n" "-b # --blocksize # set blocksize\n" "\n";
#else
static const char *opt =
"-c compress\n"
"-d decompress\n"
"-f force overwrite of output file\n"
"-h give this help\n"
"-v verbose mode\n"
"-b # set blocksize\n"
"\n";
#endif
static void
usage (int rc)
{
fprintf (stderr, "\n"
"lzf, a very lightweight compression/decompression utility written by Stefan Traby.\n"
"uses liblzf written by Marc Lehmann <schmorp@schmorp.de> You can find more info at\n"
"path_to_url"
"\n"
"usage: lzf [-dufhvb] [file ...]\n"
" unlzf [file ...]\n"
" lzcat [file ...]\n"
"\n%s",
opt);
exit (rc);
}
static inline ssize_t
rread (int fd, void *buf, size_t len)
{
ssize_t rc = 0, offset = 0;
char *p = buf;
while (len && (rc = read (fd, &p[offset], len)) > 0)
{
offset += rc;
len -= rc;
}
nr_read += offset;
if (rc < 0)
return rc;
return offset;
}
/* returns 0 if all written else -1 */
static inline ssize_t
wwrite (int fd, void *buf, size_t len)
{
ssize_t rc;
char *b = buf;
size_t l = len;
while (l)
{
rc = write (fd, b, l);
if (rc < 0)
{
fprintf (stderr, "%s: write error: ", imagename);
perror ("");
return -1;
}
l -= rc;
b += rc;
}
nr_written += len;
return 0;
}
/*
* Anatomy: an lzf file consists of any number of blocks in the following format:
*
* \x00 EOF (optional)
* "ZV\0" 2-byte-usize <uncompressed data>
* "ZV\1" 2-byte-csize 2-byte-usize <compressed data>
* "ZV\2" 4-byte-crc32-0xdebb20e3 (NYI)
*/
#define TYPE0_HDR_SIZE 5
#define TYPE1_HDR_SIZE 7
#define MAX_HDR_SIZE 7
#define MIN_HDR_SIZE 5
static int
compress_fd (int from, int to)
{
ssize_t us, cs, len;
u8 buf1[MAX_BLOCKSIZE + MAX_HDR_SIZE + 16];
u8 buf2[MAX_BLOCKSIZE + MAX_HDR_SIZE + 16];
u8 *header;
nr_read = nr_written = 0;
while ((us = rread (from, &buf1[MAX_HDR_SIZE], blocksize)) > 0)
{
cs = lzf_compress (&buf1[MAX_HDR_SIZE], us, &buf2[MAX_HDR_SIZE], us > 4 ? us - 4 : us);
if (cs)
{
header = &buf2[MAX_HDR_SIZE - TYPE1_HDR_SIZE];
header[0] = 'Z';
header[1] = 'V';
header[2] = 1;
header[3] = cs >> 8;
header[4] = cs & 0xff;
header[5] = us >> 8;
header[6] = us & 0xff;
len = cs + TYPE1_HDR_SIZE;
}
else
{ // write uncompressed
header = &buf1[MAX_HDR_SIZE - TYPE0_HDR_SIZE];
header[0] = 'Z';
header[1] = 'V';
header[2] = 0;
header[3] = us >> 8;
header[4] = us & 0xff;
len = us + TYPE0_HDR_SIZE;
}
if (wwrite (to, header, len) == -1)
return -1;
}
return 0;
}
static int
uncompress_fd (int from, int to)
{
u8 header[MAX_HDR_SIZE];
u8 buf1[MAX_BLOCKSIZE + MAX_HDR_SIZE + 16];
u8 buf2[MAX_BLOCKSIZE + MAX_HDR_SIZE + 16];
u8 *p;
int l, rd;
ssize_t rc, cs, us, bytes, over = 0;
nr_read = nr_written = 0;
while (1)
{
rc = rread (from, header + over, MAX_HDR_SIZE - over);
if (rc < 0)
{
fprintf (stderr, "%s: read error: ", imagename);
perror ("");
return -1;
}
rc += over;
over = 0;
if (!rc || header[0] == 0)
return 0;
if (rc < MIN_HDR_SIZE || header[0] != 'Z' || header[1] != 'V')
{
fprintf (stderr, "%s: invalid data stream - magic not found or short header\n", imagename);
return -1;
}
switch (header[2])
{
case 0:
cs = -1;
us = (header[3] << 8) | header[4];
p = &header[TYPE0_HDR_SIZE];
break;
case 1:
if (rc < TYPE1_HDR_SIZE)
{
goto short_read;
}
cs = (header[3] << 8) | header[4];
us = (header[5] << 8) | header[6];
p = &header[TYPE1_HDR_SIZE];
break;
default:
fprintf (stderr, "%s: unknown blocktype\n", imagename);
return -1;
}
bytes = cs == -1 ? us : cs;
l = &header[rc] - p;
if (l > 0)
memcpy (buf1, p, l);
if (l > bytes)
{
over = l - bytes;
memmove (header, &p[bytes], over);
}
p = &buf1[l];
rd = bytes - l;
if (rd > 0)
if ((rc = rread (from, p, rd)) != rd)
goto short_read;
if (cs == -1)
{
if (wwrite (to, buf1, us))
return -1;
}
else
{
if (lzf_decompress (buf1, cs, buf2, us) != us)
{
fprintf (stderr, "%s: decompress: invalid stream - data corrupted\n", imagename);
return -1;
}
if (wwrite (to, buf2, us))
return -1;
}
}
return 0;
short_read:
fprintf (stderr, "%s: short data\n", imagename);
return -1;
}
static int
open_out (const char *name)
{
int fd;
int m = O_EXCL;
if (force)
m = 0;
fd = open (name, O_CREAT | O_WRONLY | O_TRUNC | m, 600);
#if defined(__MINGW32__)
_setmode(fd, _O_BINARY);
#endif
return fd;
}
static int
compose_name (const char *fname, char *oname)
{
char *p;
if (mode == compress)
{
if (strlen (fname) > PATH_MAX - 4)
{
fprintf (stderr, "%s: %s.lzf: name too long", imagename, fname);
return -1;
}
strcpy (oname, fname);
strcat (oname, ".lzf");
}
else
{
if (strlen (fname) > PATH_MAX)
{
fprintf (stderr, "%s: %s: name too long\n", imagename, fname);
return -1;
}
strcpy (oname, fname);
p = &oname[strlen (oname)] - 4;
if (p < oname || strcmp (p, ".lzf"))
{
fprintf (stderr, "%s: %s: unknown suffix\n", imagename, fname);
return -1;
}
*p = 0;
}
return 0;
}
static int
run_file (const char *fname)
{
int fd, fd2;
int rc;
struct stat mystat;
char oname[PATH_MAX + 1];
if (mode != lzcat)
if (compose_name (fname, oname))
return -1;
#if !defined(__MINGW32__)
rc = lstat (fname, &mystat);
#else
rc = stat (fname, &mystat);
#endif
fd = open (fname, O_RDONLY);
#if defined(__MINGW32__)
_setmode(fd, _O_BINARY);
#endif
if (rc || fd == -1)
{
fprintf (stderr, "%s: %s: ", imagename, fname);
perror ("");
return -1;
}
if (!S_ISREG (mystat.st_mode))
{
fprintf (stderr, "%s: %s: not a regular file.\n", imagename, fname);
close (fd);
return -1;
}
if (mode == lzcat)
{
rc = uncompress_fd (fd, 1);
close (fd);
return rc;
}
fd2 = open_out (oname);
if (fd2 == -1)
{
fprintf (stderr, "%s: %s: ", imagename, oname);
perror ("");
close (fd);
return -1;
}
if (mode == compress)
{
rc = compress_fd (fd, fd2);
if (!rc && verbose)
fprintf (stderr, "%s: %5.1f%% -- replaced with %s\n",
fname, nr_read == 0 ? 0 : 100.0 - nr_written / ((double) nr_read / 100.0), oname);
}
else
{
rc = uncompress_fd (fd, fd2);
if (!rc && verbose)
fprintf (stderr, "%s: %5.1f%% -- replaced with %s\n",
fname, nr_written == 0 ? 0 : 100.0 - nr_read / ((double) nr_written / 100.0), oname);
}
#if !defined(__MINGW32__)
fchmod (fd2, mystat.st_mode);
#else
chmod (oname, mystat.st_mode);
#endif
close (fd);
close (fd2);
if (!rc)
unlink (fname);
return rc;
}
int
main (int argc, char *argv[])
{
char *p = argv[0];
int optc;
int rc = 0;
errno = 0;
p = getenv ("LZF_BLOCKSIZE");
if (p)
{
blocksize = strtoul (p, 0, 0);
if (errno || !blocksize || blocksize > MAX_BLOCKSIZE)
blocksize = BLOCKSIZE;
}
p = strrchr (argv[0], '/');
imagename = p ? ++p : argv[0];
if (!strncmp (imagename, "un", 2) || !strncmp (imagename, "de", 2))
mode = uncompress;
if (strstr (imagename, "cat"))
mode = lzcat;
#ifdef HAVE_GETOPT_LONG
while ((optc = getopt_long (argc, argv, "cdfhvb:", longopts, 0)) != -1)
#else
while ((optc = getopt (argc, argv, "cdfhvb:")) != -1)
#endif
{
switch (optc)
{
case 'c':
mode = compress;
break;
case 'd':
mode = uncompress;
break;
case 'f':
force = 1;
break;
case 'h':
usage (0);
break;
case 'v':
verbose = 1;
break;
case 'b':
errno = 0;
blocksize = strtoul (optarg, 0, 0);
if (errno || !blocksize || blocksize > MAX_BLOCKSIZE)
blocksize = BLOCKSIZE;
break;
default:
usage (1);
break;
}
}
if (optind == argc)
{ // stdin stdout
if (!force)
{
if ((mode == uncompress || mode == lzcat) && isatty (0))
{
fprintf (stderr, "%s: compressed data not read from a terminal. Use -f to force decompression.\n", imagename);
exit (1);
}
if (mode == compress && isatty (1))
{
fprintf (stderr, "%s: compressed data not written to a terminal. Use -f to force compression.\n", imagename);
exit (1);
}
}
if (mode == compress)
rc = compress_fd (0, 1);
else
rc = uncompress_fd (0, 1);
exit (rc ? 1 : 0);
}
while (optind < argc)
rc |= run_file (argv[optind++]);
exit (rc ? 1 : 0);
}
``` | /content/code_sandbox/src/floppy/lzf/lzf.c | c | 2016-06-25T22:29:10 | 2024-08-16T19:09:21 | 86Box | 86Box/86Box | 2,616 | 3,715 |
```objective-c
/*
*
* Redistribution and use in source and binary forms, with or without modifica-
* tion, are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MER-
* CHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO
* EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPE-
* CIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTH-
* ERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED
* OF THE POSSIBILITY OF SUCH DAMAGE.
*
* Alternatively, the contents of this file may be used under the terms of
* in which case the provisions of the GPL are applicable instead of
* the above. If you wish to allow the use of your version of this file
* only under the terms of the GPL and not to allow others to use your
* version of this file under the BSD license, indicate your decision
* by deleting the provisions above and replace them with the notice
* and other provisions required by the GPL. If you do not delete the
* provisions above, a recipient may use your version of this file under
* either the BSD or the GPL.
*/
#ifndef LZF_H
#define LZF_H
/***********************************************************************
**
** lzf -- an extremely fast/free compression/decompression-method
** path_to_url
**
** This algorithm is believed to be patent-free.
**
***********************************************************************/
#define LZF_VERSION 0x0105 /* 1.5, API version */
/*
* Compress in_len bytes stored at the memory block starting at
* in_data and write the result to out_data, up to a maximum length
* of out_len bytes.
*
* If the output buffer is not large enough or any error occurs return 0,
* otherwise return the number of bytes used, which might be considerably
* more than in_len (but less than 104% of the original size), so it
* makes sense to always use out_len == in_len - 1), to ensure _some_
* compression, and store the data uncompressed otherwise (with a flag, of
* course.
*
* lzf_compress might use different algorithms on different systems and
* even different runs, thus might result in different compressed strings
* depending on the phase of the moon or similar factors. However, all
* these strings are architecture-independent and will result in the
* original data when decompressed using lzf_decompress.
*
* The buffers must not be overlapping.
*
* If the option LZF_STATE_ARG is enabled, an extra argument must be
* supplied which is not reflected in this header file. Refer to lzfP.h
* and lzf_c.c.
*
*/
unsigned int
lzf_compress (const void *const in_data, unsigned int in_len,
void *out_data, unsigned int out_len);
/*
* Decompress data compressed with some version of the lzf_compress
* function and stored at location in_data and length in_len. The result
* will be stored at out_data up to a maximum of out_len characters.
*
* If the output buffer is not large enough to hold the decompressed
* data, a 0 is returned and errno is set to E2BIG. Otherwise the number
* of decompressed bytes (i.e. the original length of the data) is
* returned.
*
* If an error in the compressed data is detected, a zero is returned and
* errno is set to EINVAL.
*
* This function is very fast, about as fast as a copying loop.
*/
unsigned int
lzf_decompress (const void *const in_data, unsigned int in_len,
void *out_data, unsigned int out_len);
#endif
``` | /content/code_sandbox/src/floppy/lzf/lzf.h | objective-c | 2016-06-25T22:29:10 | 2024-08-16T19:09:21 | 86Box | 86Box/86Box | 2,616 | 927 |
```objective-c
#ifndef CRC32_H
#define CRC32_H
/* crc32 0xdebb20e3 table and supplementary functions. */
static const u32 crc_32_tab[] =
{
0x00000000UL, 0x77073096UL, 0xee0e612cUL, 0x990951baUL, 0x076dc419UL,
0x706af48fUL, 0xe963a535UL, 0x9e6495a3UL, 0x0edb8832UL, 0x79dcb8a4UL,
0xe0d5e91eUL, 0x97d2d988UL, 0x09b64c2bUL, 0x7eb17cbdUL, 0xe7b82d07UL,
0x90bf1d91UL, 0x1db71064UL, 0x6ab020f2UL, 0xf3b97148UL, 0x84be41deUL,
0x1adad47dUL, 0x6ddde4ebUL, 0xf4d4b551UL, 0x83d385c7UL, 0x136c9856UL,
0x646ba8c0UL, 0xfd62f97aUL, 0x8a65c9ecUL, 0x14015c4fUL, 0x63066cd9UL,
0xfa0f3d63UL, 0x8d080df5UL, 0x3b6e20c8UL, 0x4c69105eUL, 0xd56041e4UL,
0xa2677172UL, 0x3c03e4d1UL, 0x4b04d447UL, 0xd20d85fdUL, 0xa50ab56bUL,
0x35b5a8faUL, 0x42b2986cUL, 0xdbbbc9d6UL, 0xacbcf940UL, 0x32d86ce3UL,
0x45df5c75UL, 0xdcd60dcfUL, 0xabd13d59UL, 0x26d930acUL, 0x51de003aUL,
0xc8d75180UL, 0xbfd06116UL, 0x21b4f4b5UL, 0x56b3c423UL, 0xcfba9599UL,
0xb8bda50fUL, 0x2802b89eUL, 0x5f058808UL, 0xc60cd9b2UL, 0xb10be924UL,
0x2f6f7c87UL, 0x58684c11UL, 0xc1611dabUL, 0xb6662d3dUL, 0x76dc4190UL,
0x01db7106UL, 0x98d220bcUL, 0xefd5102aUL, 0x71b18589UL, 0x06b6b51fUL,
0x9fbfe4a5UL, 0xe8b8d433UL, 0x7807c9a2UL, 0x0f00f934UL, 0x9609a88eUL,
0xe10e9818UL, 0x7f6a0dbbUL, 0x086d3d2dUL, 0x91646c97UL, 0xe6635c01UL,
0x6b6b51f4UL, 0x1c6c6162UL, 0x856530d8UL, 0xf262004eUL, 0x6c0695edUL,
0x1b01a57bUL, 0x8208f4c1UL, 0xf50fc457UL, 0x65b0d9c6UL, 0x12b7e950UL,
0x8bbeb8eaUL, 0xfcb9887cUL, 0x62dd1ddfUL, 0x15da2d49UL, 0x8cd37cf3UL,
0xfbd44c65UL, 0x4db26158UL, 0x3ab551ceUL, 0xa3bc0074UL, 0xd4bb30e2UL,
0x4adfa541UL, 0x3dd895d7UL, 0xa4d1c46dUL, 0xd3d6f4fbUL, 0x4369e96aUL,
0x346ed9fcUL, 0xad678846UL, 0xda60b8d0UL, 0x44042d73UL, 0x33031de5UL,
0xaa0a4c5fUL, 0xdd0d7cc9UL, 0x5005713cUL, 0x270241aaUL, 0xbe0b1010UL,
0xc90c2086UL, 0x5768b525UL, 0x206f85b3UL, 0xb966d409UL, 0xce61e49fUL,
0x5edef90eUL, 0x29d9c998UL, 0xb0d09822UL, 0xc7d7a8b4UL, 0x59b33d17UL,
0x2eb40d81UL, 0xb7bd5c3bUL, 0xc0ba6cadUL, 0xedb88320UL, 0x9abfb3b6UL,
0x03b6e20cUL, 0x74b1d29aUL, 0xead54739UL, 0x9dd277afUL, 0x04db2615UL,
0x73dc1683UL, 0xe3630b12UL, 0x94643b84UL, 0x0d6d6a3eUL, 0x7a6a5aa8UL,
0xe40ecf0bUL, 0x9309ff9dUL, 0x0a00ae27UL, 0x7d079eb1UL, 0xf00f9344UL,
0x8708a3d2UL, 0x1e01f268UL, 0x6906c2feUL, 0xf762575dUL, 0x806567cbUL,
0x196c3671UL, 0x6e6b06e7UL, 0xfed41b76UL, 0x89d32be0UL, 0x10da7a5aUL,
0x67dd4accUL, 0xf9b9df6fUL, 0x8ebeeff9UL, 0x17b7be43UL, 0x60b08ed5UL,
0xd6d6a3e8UL, 0xa1d1937eUL, 0x38d8c2c4UL, 0x4fdff252UL, 0xd1bb67f1UL,
0xa6bc5767UL, 0x3fb506ddUL, 0x48b2364bUL, 0xd80d2bdaUL, 0xaf0a1b4cUL,
0x36034af6UL, 0x41047a60UL, 0xdf60efc3UL, 0xa867df55UL, 0x316e8eefUL,
0x4669be79UL, 0xcb61b38cUL, 0xbc66831aUL, 0x256fd2a0UL, 0x5268e236UL,
0xcc0c7795UL, 0xbb0b4703UL, 0x220216b9UL, 0x5505262fUL, 0xc5ba3bbeUL,
0xb2bd0b28UL, 0x2bb45a92UL, 0x5cb36a04UL, 0xc2d7ffa7UL, 0xb5d0cf31UL,
0x2cd99e8bUL, 0x5bdeae1dUL, 0x9b64c2b0UL, 0xec63f226UL, 0x756aa39cUL,
0x026d930aUL, 0x9c0906a9UL, 0xeb0e363fUL, 0x72076785UL, 0x05005713UL,
0x95bf4a82UL, 0xe2b87a14UL, 0x7bb12baeUL, 0x0cb61b38UL, 0x92d28e9bUL,
0xe5d5be0dUL, 0x7cdcefb7UL, 0x0bdbdf21UL, 0x86d3d2d4UL, 0xf1d4e242UL,
0x68ddb3f8UL, 0x1fda836eUL, 0x81be16cdUL, 0xf6b9265bUL, 0x6fb077e1UL,
0x18b74777UL, 0x88085ae6UL, 0xff0f6a70UL, 0x66063bcaUL, 0x11010b5cUL,
0x8f659effUL, 0xf862ae69UL, 0x616bffd3UL, 0x166ccf45UL, 0xa00ae278UL,
0xd70dd2eeUL, 0x4e048354UL, 0x3903b3c2UL, 0xa7672661UL, 0xd06016f7UL,
0x4969474dUL, 0x3e6e77dbUL, 0xaed16a4aUL, 0xd9d65adcUL, 0x40df0b66UL,
0x37d83bf0UL, 0xa9bcae53UL, 0xdebb9ec5UL, 0x47b2cf7fUL, 0x30b5ffe9UL,
0xbdbdf21cUL, 0xcabac28aUL, 0x53b39330UL, 0x24b4a3a6UL, 0xbad03605UL,
0xcdd70693UL, 0x54de5729UL, 0x23d967bfUL, 0xb3667a2eUL, 0xc4614ab8UL,
0x5d681b02UL, 0x2a6f2b94UL, 0xb40bbe37UL, 0xc30c8ea1UL, 0x5a05df1bUL,
0x2d02ef8dL
};
#define crc32(crc,byte) (crc_32_tab[(u8)(crc) ^ (u8)(byte)] ^ ((crc) >> 8))
#endif
``` | /content/code_sandbox/src/floppy/lzf/crc32.h | objective-c | 2016-06-25T22:29:10 | 2024-08-16T19:09:21 | 86Box | 86Box/86Box | 2,616 | 2,599 |
```c
/*
*
* Redistribution and use in source and binary forms, with or without modifica-
* tion, are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MER-
* CHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO
* EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPE-
* CIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTH-
* ERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED
* OF THE POSSIBILITY OF SUCH DAMAGE.
*
* Alternatively, the contents of this file may be used under the terms of
* in which case the provisions of the GPL are applicable instead of
* the above. If you wish to allow the use of your version of this file
* only under the terms of the GPL and not to allow others to use your
* version of this file under the BSD license, indicate your decision
* by deleting the provisions above and replace them with the notice
* and other provisions required by the GPL. If you do not delete the
* provisions above, a recipient may use your version of this file under
* either the BSD or the GPL.
*/
#include <stdint.h>
#include "lzfP.h"
#define HSIZE (1 << (HLOG))
/*
* don't play with this unless you benchmark!
* the data format is not dependent on the hash function.
* the hash function might seem strange, just believe me,
* it works ;)
*/
#ifndef FRST
# define FRST(p) (((p[0]) << 8) | p[1])
# define NEXT(v,p) (((v) << 8) | p[2])
# if ULTRA_FAST
# define IDX(h) ((( h >> (3*8 - HLOG)) - h ) & (HSIZE - 1))
# elif VERY_FAST
# define IDX(h) ((( h >> (3*8 - HLOG)) - h*5) & (HSIZE - 1))
# else
# define IDX(h) ((((h ^ (h << 5)) >> (3*8 - HLOG)) - h*5) & (HSIZE - 1))
# endif
#endif
/*
* IDX works because it is very similar to a multiplicative hash, e.g.
* ((h * 57321 >> (3*8 - HLOG)) & (HSIZE - 1))
* the latter is also quite fast on newer CPUs, and compresses similarly.
*
* the next one is also quite good, albeit slow ;)
* (int)(cos(h & 0xffffff) * 1e6)
*/
#if 0
/* original lzv-like hash function, much worse and thus slower */
# define FRST(p) (p[0] << 5) ^ p[1]
# define NEXT(v,p) ((v) << 5) ^ p[2]
# define IDX(h) ((h) & (HSIZE - 1))
#endif
#define MAX_LIT (1 << 5)
#define MAX_OFF (1 << 13)
#define MAX_REF ((1 << 8) + (1 << 3))
#if __GNUC__ >= 3
# define expect(expr,value) __builtin_expect ((expr),(value))
# define inline inline
#else
# define expect(expr,value) (expr)
# define inline static
#endif
#define expect_false(expr) expect ((expr) != 0, 0)
#define expect_true(expr) expect ((expr) != 0, 1)
/*
* compressed format
*
* 000LLLLL <L+1> ; literal, L+1=1..33 octets
* LLLooooo oooooooo ; backref L+1=1..7 octets, o+1=1..4096 offset
* 111ooooo LLLLLLLL oooooooo ; backref L+8 octets, o+1=1..4096 offset
*
*/
unsigned int
lzf_compress (const void *const in_data, unsigned int in_len,
void *out_data, unsigned int out_len
#if LZF_STATE_ARG
, LZF_STATE htab
#endif
)
{
#if !LZF_STATE_ARG
LZF_STATE htab;
#endif
const u8 *ip = (const u8 *)in_data;
u8 *op = (u8 *)out_data;
const u8 *in_end = ip + in_len;
u8 *out_end = op + out_len;
const u8 *ref;
/* off requires a type wide enough to hold a general pointer difference.
* ISO C doesn't have that (size_t might not be enough and ptrdiff_t only
* works for differences within a single object). We also assume that no
* no bit pattern traps. Since the only platform that is both non-POSIX
* and fails to support both assumptions is windows 64 bit, we make a
* special workaround for it.
*/
#if defined(_WIN32) && defined(_M_X64)
uint64_t off; /* workaround for missing POSIX compliance */
#else
unsigned long off;
#endif
unsigned int hval;
int lit;
if (!in_len || !out_len)
return 0;
#if INIT_HTAB
memset (htab, 0, sizeof (htab));
#endif
lit = 0; op++; /* start run */
hval = FRST (ip);
while (ip < in_end - 2)
{
LZF_HSLOT *hslot;
hval = NEXT (hval, ip);
hslot = htab + IDX (hval);
ref = *hslot + LZF_HSLOT_BIAS; *hslot = ip - LZF_HSLOT_BIAS;
if (1
#if INIT_HTAB
&& ref < ip /* the next test will actually take care of this, but this is faster */
#endif
&& (off = ip - ref - 1) < MAX_OFF
&& ref > (u8 *)in_data
&& ref[2] == ip[2]
#if STRICT_ALIGN
&& ((ref[1] << 8) | ref[0]) == ((ip[1] << 8) | ip[0])
#else
&& *(u16 *)ref == *(u16 *)ip
#endif
)
{
/* match found at *ref++ */
unsigned int len = 2;
unsigned int maxlen = in_end - ip - len;
maxlen = maxlen > MAX_REF ? MAX_REF : maxlen;
if (expect_false (op + 3 + 1 >= out_end)) /* first a faster conservative test */
if (op - !lit + 3 + 1 >= out_end) /* second the exact but rare test */
return 0;
op [- lit - 1] = lit - 1; /* stop run */
op -= !lit; /* undo run if length is zero */
for (;;)
{
if (expect_true (maxlen > 16))
{
len++; if (ref [len] != ip [len]) break;
len++; if (ref [len] != ip [len]) break;
len++; if (ref [len] != ip [len]) break;
len++; if (ref [len] != ip [len]) break;
len++; if (ref [len] != ip [len]) break;
len++; if (ref [len] != ip [len]) break;
len++; if (ref [len] != ip [len]) break;
len++; if (ref [len] != ip [len]) break;
len++; if (ref [len] != ip [len]) break;
len++; if (ref [len] != ip [len]) break;
len++; if (ref [len] != ip [len]) break;
len++; if (ref [len] != ip [len]) break;
len++; if (ref [len] != ip [len]) break;
len++; if (ref [len] != ip [len]) break;
len++; if (ref [len] != ip [len]) break;
len++; if (ref [len] != ip [len]) break;
}
do
len++;
while (len < maxlen && ref[len] == ip[len]);
break;
}
len -= 2; /* len is now #octets - 1 */
ip++;
if (len < 7)
{
*op++ = (off >> 8) + (len << 5);
}
else
{
*op++ = (off >> 8) + ( 7 << 5);
*op++ = len - 7;
}
*op++ = off;
lit = 0; op++; /* start run */
ip += len + 1;
if (expect_false (ip >= in_end - 2))
break;
#if ULTRA_FAST || VERY_FAST
--ip;
# if VERY_FAST && !ULTRA_FAST
--ip;
# endif
hval = FRST (ip);
hval = NEXT (hval, ip);
htab[IDX (hval)] = ip - LZF_HSLOT_BIAS;
ip++;
# if VERY_FAST && !ULTRA_FAST
hval = NEXT (hval, ip);
htab[IDX (hval)] = ip - LZF_HSLOT_BIAS;
ip++;
# endif
#else
ip -= len + 1;
do
{
hval = NEXT (hval, ip);
htab[IDX (hval)] = ip - LZF_HSLOT_BIAS;
ip++;
}
while (len--);
#endif
}
else
{
/* one more literal byte we must copy */
if (expect_false (op >= out_end))
return 0;
lit++; *op++ = *ip++;
if (expect_false (lit == MAX_LIT))
{
op [- lit - 1] = lit - 1; /* stop run */
lit = 0; op++; /* start run */
}
}
}
if (op + 3 > out_end) /* at most 3 bytes can be missing here */
return 0;
while (ip < in_end)
{
lit++; *op++ = *ip++;
if (expect_false (lit == MAX_LIT))
{
op [- lit - 1] = lit - 1; /* stop run */
lit = 0; op++; /* start run */
}
}
op [- lit - 1] = lit - 1; /* end run */
op -= !lit; /* undo run if length is zero */
return op - (u8 *)out_data;
}
``` | /content/code_sandbox/src/floppy/lzf/lzf_c.c | c | 2016-06-25T22:29:10 | 2024-08-16T19:09:21 | 86Box | 86Box/86Box | 2,616 | 2,498 |
```objective-c
/***************************************************************************
* Header for Lempel-Ziv-Welch Encoding and Decoding Library
*
* File : lzwlocal.h
* Purpose : Provides constant definitions for functions values used within
* the functions for Lempel-Ziv-Welch encoding/decoding.
* Author : Michael Dipperstein
* Date : February 22, 2015
*
****************************************************************************
*
* LZW: An ANSI C Lempel-Ziv-Welch Encoding/Decoding Routines
* Michael Dipperstein (mdipperstein@gmail.com)
*
* This file is part of the lzw library.
*
* The lzw library is free software; you can redistribute it and/or
* published by the Free Software Foundation; either version 3 of the
*
* The lzw library is distributed in the hope that it will be useful, but
* WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser
*
* along with this program. If not, see <path_to_url
*
***************************************************************************/
#ifndef _LZWLOCAL_H_
#define _LZWLOCAL_H_
/***************************************************************************
* INCLUDED FILES
***************************************************************************/
#include <stdio.h>
#include <limits.h>
/***************************************************************************
* CONSTANTS
***************************************************************************/
#define MIN_CODE_LEN 12 /* min # bits in a code word */
#define MAX_CODE_LEN 12 /* max # bits in a code word */
#define FIRST_CODE (1 << CHAR_BIT) /* value of 1st string code */
#define MAX_CODES (1 << MAX_CODE_LEN)
#if (MIN_CODE_LEN <= CHAR_BIT)
#error Code words must be larger than 1 character
#endif
#if ((MAX_CODES - 1) > INT_MAX)
#error There cannot be more codes than can fit in an integer
#endif
/***************************************************************************
* MACROS
***************************************************************************/
#define CURRENT_MAX_CODES(bits) ((unsigned int)(1 << (bits)))
#endif /* ndef _LZWLOCAL_H_ */
``` | /content/code_sandbox/src/floppy/lzw/lzwlocal.h | objective-c | 2016-06-25T22:29:10 | 2024-08-16T19:09:21 | 86Box | 86Box/86Box | 2,616 | 423 |
```c
/***************************************************************************
* Lempel-Ziv-Welch Decoding Functions
*
* File : lzwdecode.c
* Purpose : Provides a function for decoding Lempel-Ziv-Welch encoded
* file streams
* Author : Michael Dipperstein
* Date : January 30, 2005
*
****************************************************************************
*
* LZW: An ANSI C Lempel-Ziv-Welch Encoding/Decoding Routines
* Michael Dipperstein (mdipperstein@gmail.com)
*
* This file is part of the lzw library.
*
* The lzw library is free software; you can redistribute it and/or
* published by the Free Software Foundation; either version 3 of the
*
* The lzw library is distributed in the hope that it will be useful, but
* WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser
*
* along with this program. If not, see <path_to_url
*
***************************************************************************/
/***************************************************************************
* INCLUDED FILES
***************************************************************************/
#include <inttypes.h>
#include <stdint.h>
#include <stdio.h>
#include <stdlib.h>
#include <string.h>
#include <errno.h>
#include "lzw.h"
#include "lzwlocal.h"
/***************************************************************************
* TYPE DEFINITIONS
***************************************************************************/
typedef struct
{
uint8_t suffixChar; /* last char in encoded string */
uint16_t prefixCode; /* code for remaining chars in string */
} decode_dictionary_t;
/***************************************************************************
* CONSTANTS
***************************************************************************/
/***************************************************************************
* MACROS
***************************************************************************/
/***************************************************************************
* GLOBAL VARIABLES
***************************************************************************/
/* dictionary of string the code word is the dictionary index */
static decode_dictionary_t dictionary[(MAX_CODES - FIRST_CODE)];
/***************************************************************************
* PROTOTYPES
***************************************************************************/
static uint8_t DecodeRecursive(unsigned int code, char **dest);
/* read encoded data */
static int GetCodeWord(char *src);
static uint16_t bufPos = 0x0000;
static uint16_t bufLen = 0x0000;
static uint32_t bufOutPos = 0x00000000;
/***************************************************************************
* FUNCTIONS
***************************************************************************/
/***************************************************************************
* Function : LZWDecodeFile
* Description: This routine reads an input file 1 encoded string at a
* time and decodes it using the LZW algorithm.
* Parameters : fpIn - pointer to the open binary file to decode
* fpOut - pointer to the open binary file to write decoded
* output
* Effects : fpIn is decoded using the LZW algorithm with CODE_LEN codes
* and written to fpOut. Neither file is closed after exit.
* Returned : 0 for success, -1 for failure. errno will be set in the
* event of a failure.
***************************************************************************/
int
LZWDecodeFile_Internal(char *dest, char *src)
{
uint16_t nextCode; /* value of next code */
uint16_t lastCode; /* last decoded code word */
int code; /* code word to decode */
uint8_t c; /* last decoded character */
/* validate arguments */
if (dest == NULL) {
errno = ENOENT;
return -1;
}
bufPos = 0x0000;
bufOutPos = 0x00000000;
/* initialize for decoding */
nextCode = FIRST_CODE; /* code for next (first) string */
/* first code from file must be a character. use it for initial values */
lastCode = GetCodeWord(src);
c = lastCode;
*(dest++) = lastCode;
bufOutPos++;
/* decode rest of file */
while ((int)(code = GetCodeWord(src)) != EOF) {
if (code < nextCode) {
/* we have a known code. decode it */
c = DecodeRecursive(code, &dest);
} else {
/***************************************************************
* We got a code that's not in our dictionary. This must be due
* to the string + char + string + char + string exception.
* Build the decoded string using the last character + the
* string from the last code.
***************************************************************/
unsigned char tmp;
tmp = c;
c = DecodeRecursive(lastCode, &dest);
*(dest++) = tmp;
bufOutPos++;
}
/* if room, add new code to the dictionary */
if (nextCode < MAX_CODES) {
dictionary[nextCode - FIRST_CODE].prefixCode = lastCode;
dictionary[nextCode - FIRST_CODE].suffixChar = c;
nextCode++;
}
/* save character and code for use in unknown code word case */
lastCode = code;
}
return 0;
}
int
LZWDecodeFile(char *dest, char *src, uint64_t *dst_len, uint64_t src_len)
{
uint16_t size = 0x0000;
uint64_t pos = 0x0000000000000000ULL;
/* validate arguments */
if ((dest == NULL) || (src == NULL)) {
errno = ENOENT;
return -1;
}
if (dst_len != NULL)
*dst_len = 0x0000000000000000ULL;
while (1) {
size = *(uint16_t *) src;
src += 2;
bufLen = size;
size >>= 1;
if (bufLen & 1)
size++;
if (size > 0x1800)
return -1;
LZWDecodeFile_Internal(dest, src);
src += size;
dest += bufOutPos;
if (dst_len != NULL)
*dst_len += bufOutPos;
pos += (size + 2);
if ((size < 0x1800) || (pos >= src_len))
/* We have just decoded a block smaller than 0x3000 bytes,
this means this has been the last block, end. */
break;
}
return 0;
}
/***************************************************************************
* Function : DecodeRecursive
* Description: This function uses the dictionary to decode a code word
* into the string it represents and write it to the output
* file. The string is actually built in reverse order and
* recursion is used to write it out in the correct order.
* Parameters : code - the code word to decode
* fpOut - the file that the decoded code word is written to
* Effects : Decoded code word is written to a file
* Returned : The first character in the decoded string
***************************************************************************/
static uint8_t
DecodeRecursive(unsigned int code, char **dest)
{
unsigned char c;
unsigned char firstChar;
if (code >= FIRST_CODE) {
/* code word is string + c */
c = dictionary[code - FIRST_CODE].suffixChar;
code = dictionary[code - FIRST_CODE].prefixCode;
/* evaluate new code word for remaining string */
firstChar = DecodeRecursive(code, dest);
} else {
/* code word is just c */
c = code;
firstChar = code;
}
*((*dest)++) = c;
bufOutPos++;
return firstChar;
}
/***************************************************************************
* Function : GetCodeWord
* Description: This function reads and returns a code word from an
* encoded file. In order to deal with endian issue the
* code word is read least significant byte followed by the
* remaining bits.
* Parameters : fpIn - file containing the encoded data
* codeLen - number of bits in code word
* Effects : code word is read from encoded input
* Returned : The next code word in the encoded file. EOF if the end
* of file has been reached.
*
* NOTE: If the code word contains more than 16 bits, this routine should
* be modified to read in all the bytes from least significant to
* most significant followed by any left over bits.
***************************************************************************/
static int
GetCodeWord(char *src)
{
int code = 0;
static unsigned int realPos;
realPos = bufPos >> 1;
if (bufPos >= bufLen)
/* End of buffer. */
code = EOF;
else if (bufPos & 1)
/* Odd position. */
code = (((uint8_t) src[realPos] & 0xf0) >> 4) | ((uint8_t) src[realPos + 1] << 4);
else
/* Even position. */
code = ((uint8_t) src[realPos] & 0xff) | (((uint8_t) src[realPos + 1] & 0xf) << 8);
bufPos += 3;
return code;
}
``` | /content/code_sandbox/src/floppy/lzw/lzwdecode.c | c | 2016-06-25T22:29:10 | 2024-08-16T19:09:21 | 86Box | 86Box/86Box | 2,616 | 1,915 |
```objective-c
/***************************************************************************
* Header for Lempel-Ziv-Welch Encoding and Decoding Library
*
* File : lzw.h
* Purpose : Provides prototypes for functions that use Lempel-Ziv-Welch
* coding to encode/decode files.
* Author : Michael Dipperstein
* Date : January 30, 2004
*
****************************************************************************
*
* LZW: An ANSI C Lempel-Ziv-Welch Encoding/Decoding Routines
* Michael Dipperstein (mdipperstein@gmail.com)
*
* This file is part of the lzw library.
*
* The lzw library is free software; you can redistribute it and/or
* published by the Free Software Foundation; either version 3 of the
*
* The lzw library is distributed in the hope that it will be useful, but
* WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser
*
* along with this program. If not, see <path_to_url
*
***************************************************************************/
#ifndef _LZW_H_
#define _LZW_H_
/***************************************************************************
* CONSTANTS
***************************************************************************/
/***************************************************************************
* PROTOTYPES
***************************************************************************/
/* encode inFile */
int LZWEncodeFile(char *dest, char *src, uint64_t *dst_len, uint64_t src_len);
/* decode inFile*/
int LZWDecodeFile(char *dest, char *src, uint64_t *dst_len, uint64_t src_len);
#endif /* ndef _LZW_H_ */
``` | /content/code_sandbox/src/floppy/lzw/lzw.h | objective-c | 2016-06-25T22:29:10 | 2024-08-16T19:09:21 | 86Box | 86Box/86Box | 2,616 | 329 |
```c
/***************************************************************************
* Lempel-Ziv-Welch Encoding Functions
*
* File : lzwencode.c
* Purpose : Provides a function for Lempel-Ziv-Welch encoding of file
* streams
* Author : Michael Dipperstein
* Date : January 30, 2005
*
****************************************************************************
*
* LZW: An ANSI C Lempel-Ziv-Welch Encoding/Decoding Routines
* Michael Dipperstein (mdipperstein@gmail.com)
*
* This file is part of the lzw library.
*
* The lzw library is free software; you can redistribute it and/or
* published by the Free Software Foundation; either version 3 of the
*
* The lzw library is distributed in the hope that it will be useful, but
* WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser
*
* along with this program. If not, see <path_to_url
*
***************************************************************************/
/***************************************************************************
* INCLUDED FILES
***************************************************************************/
#include <inttypes.h>
#include <stdint.h>
#include <stdio.h>
#include <stdlib.h>
#include <string.h>
#include <errno.h>
#include "lzw.h"
#include "lzwlocal.h"
/***************************************************************************
* TYPE DEFINITIONS
***************************************************************************/
/* node in dictionary tree */
typedef struct dict_node_t
{
unsigned int codeWord; /* code word for this entry */
unsigned char suffixChar; /* last char in encoded string */
unsigned int prefixCode; /* code for remaining chars in string */
/* pointer to child nodes */
struct dict_node_t *left; /* child with < key */
struct dict_node_t *right; /* child with >= key */
} dict_node_t;
/***************************************************************************
* CONSTANTS
***************************************************************************/
/***************************************************************************
* MACROS
***************************************************************************/
/***************************************************************************
* GLOBAL VARIABLES
***************************************************************************/
/***************************************************************************
* PROTOTYPES
***************************************************************************/
/* dictionary tree node create/free */
static dict_node_t *MakeNode(const unsigned int codeWord, const unsigned int prefixCode,
const unsigned char suffixChar);
static void FreeTree(dict_node_t *node);
/* searches tree for matching dictionary entry */
static dict_node_t *FindDictionaryEntry(dict_node_t *root, const int unsigned prefixCode,
const unsigned char c);
/* makes key from prefix code and character */
static unsigned int MakeKey(const unsigned int prefixCode, const unsigned char suffixChar);
/* write encoded data */
static int PutCodeWord(char *dest, int code);
static char *src_base;
static uint64_t src_length = 0x0000000000000000ULL;
static uint32_t bufPos = 0x00000000;
static uint32_t bufInPos = 0x00000000;
static int
is_eob(char *src)
{
return ((uint64_t) (uintptr_t) (src - src_base)) >= src_length;
}
static int
get_char(char **src)
{
int ret = EOF;
if (!is_eob(*src)) {
ret = (uint8_t) **src;
(*src)++;
}
return ret;
}
/***************************************************************************
* FUNCTIONS
***************************************************************************/
static int
LZWEncodeFile_Internal(char *dest, char *src)
{
unsigned int code; /* code for current string */
unsigned int nextCode; /* next available code index */
int c; /* character to add to string */
dict_node_t *dictRoot; /* root of dictionary tree */
dict_node_t *node; /* node of dictionary tree */
/* validate arguments */
if (src == NULL) {
errno = ENOENT;
return -1;
}
/* initialize dictionary as empty */
dictRoot = NULL;
nextCode = FIRST_CODE; /* code for next (first) string */
bufPos = 0x00000000;
bufInPos = 0x00000000;
/* now start the actual encoding process */
c = get_char(&src);
if (c == EOF)
return -1; /* empty file */
else {
bufInPos++;
code = c; /* start with code string = first character */
}
/* create a tree root from 1st 2 character string */
if ((c = get_char(&src)) != EOF) {
bufInPos++;
/* special case for NULL root */
dictRoot = MakeNode(nextCode, code, c);
if (dictRoot == NULL) {
perror("Making Dictionary Root");
return -1;
}
nextCode++;
/* write code for 1st char */
(void) PutCodeWord(dest, code);
/* new code is just 2nd char */
code = c;
}
/* now encode normally */
while ((c = get_char(&src)) != EOF) {
/* look for code + c in the dictionary */
node = FindDictionaryEntry(dictRoot, code, c);
if ((node->prefixCode == code) && (node->suffixChar == c))
/* code + c is in the dictionary, make it's code the new code */
code = node->codeWord;
else {
/* code + c is not in the dictionary, add it if there's room */
if (nextCode < MAX_CODES) {
dict_node_t *tmp = MakeNode(nextCode, code, c);
if (tmp == NULL) {
perror("Making Dictionary Node");
FreeTree(dictRoot);
return -1;
}
nextCode++;
if (MakeKey(code, c) < MakeKey(node->prefixCode, node->suffixChar))
node->left = tmp;
else
node->right = tmp;
}
/* write out code for the string before c was added */
if (PutCodeWord(dest, code))
break;
/* new code is just c */
code = c;
}
bufInPos++;
}
/* no more input. write out last of the code. */
(void) PutCodeWord(dest, code);
/* free the dictionary */
FreeTree(dictRoot);
return (c == EOF) ? 1 : 0;
}
/***************************************************************************
* Function : LZWEncodeFile
* Description: This routine reads an input file 1 character at a time and
* writes out an LZW encoded version of that file.
* Parameters : fpIn - pointer to the open binary file to encode
* fpOut - pointer to the open binary file to write encoded
* output
* Effects : fpIn is encoded using the LZW algorithm with CODE_LEN codes
* and written to fpOut. Neither file is closed after exit.
* Returned : 0 for success, -1 for failure. errno will be set in the
* event of a failure.
***************************************************************************/
int
LZWEncodeFile(char *dest, char *src, uint64_t *dst_len, uint64_t src_len)
{
uint64_t pos = 0x0000000000000000ULL;
/* validate arguments */
if ((dest == NULL) || (src == NULL)) {
errno = ENOENT;
return -1;
}
if (dst_len != NULL)
*dst_len = 0x0000000000000000ULL;
src_base = src;
src_length = src_len;
while (1) {
int ret = LZWEncodeFile_Internal(dest + 2, src);
if (ret == -1)
break;
*(uint16_t *) dest = bufPos;
if (bufPos & 1)
bufPos = (bufPos >> 1) + 1;
else
bufPos >>= 1;
dest += (bufPos + 2);
if (dst_len != NULL)
*dst_len += (bufPos + 2);
/* TODO: Why do we need this - 1 clunkfest? */
src += bufInPos;
pos += bufInPos;
if ((ret == 1) || (pos >= src_len) || (bufPos < 0x1800))
break;
}
return 0;
}
/***************************************************************************
* Function : MakeKey
* Description: This routine creates a simple key from a prefix code and
* an appended character. The key may be used to establish
* an order when building/searching a dictionary tree.
* Parameters : prefixCode - code for all but the last character of a
* string.
* suffixChar - the last character of a string
* Effects : None
* Returned : Key built from string represented as a prefix + char. Key
* format is {ms nibble of c} + prefix + {ls nibble of c}
***************************************************************************/
static unsigned int
MakeKey(const unsigned int prefixCode, const unsigned char suffixChar)
{
unsigned int key;
/* position ms nibble */
key = suffixChar & 0xF0;
key <<= MAX_CODE_LEN;
/* include prefix code */
key |= (prefixCode << 4);
/* inclulde ls nibble */
key |= (suffixChar & 0x0F);
return key;
}
/***************************************************************************
* Function : MakeNode
* Description: This routine creates and initializes a dictionary entry
* for a string and the code word that encodes it.
* Parameters : codeWord - code word used to encode the string prefixCode +
* suffixChar
* prefixCode - code for all but the last character of a
* string.
* suffixChar - the last character of a string
* Effects : Node is allocated for new dictionary entry
* Returned : Pointer to newly allocated node or NULL on error.
* errno will be set on an error.
***************************************************************************/
static dict_node_t *
MakeNode(const unsigned int codeWord, const unsigned int prefixCode, const unsigned char suffixChar)
{
dict_node_t *node;
node = malloc(sizeof(dict_node_t));
if (node != NULL) {
node->codeWord = codeWord;
node->prefixCode = prefixCode;
node->suffixChar = suffixChar;
node->left = NULL;
node->right = NULL;
}
return node;
}
/***************************************************************************
* Function : FreeTree
* Description: This routine will free all nodes of a tree rooted at the
* node past as a parameter.
* Parameters : node - root of tree to free
* Effects : frees allocated tree node from initial parameter down.
* Returned : none
***************************************************************************/
static void
FreeTree(dict_node_t *node)
{
if (node == NULL)
/* nothing to free */
return;
/* free left branch */
if (node->left != NULL)
FreeTree(node->left);
/* free right branch */
if (node->right != NULL)
FreeTree(node->right);
/* free root */
free(node);
}
/***************************************************************************
* Function : FindDictionaryEntry
* Description: This routine searches the dictionary tree for an entry
* with a matching string (prefix code + suffix character).
* If one isn't found, the parent node for that string is
* returned.
* Parameters : prefixCode - code for the prefix of string
* c - last character in string
* Effects : None
* Returned : If string is in dictionary, pointer to node containing
* string, otherwise pointer to suitable parent node. NULL
* is returned for an empty tree.
***************************************************************************/
static dict_node_t *
FindDictionaryEntry(dict_node_t *root, const int unsigned prefixCode, const unsigned char c)
{
unsigned int searchKey, key;
if (root == NULL)
return NULL;
searchKey = MakeKey(prefixCode, c); /* key of string to find */
while (1) {
/* key of current node */
key = MakeKey(root->prefixCode, root->suffixChar);
if (key == searchKey)
/* current node contains string */
return root;
else if (searchKey < key) {
if (root->left != NULL)
/* check left branch for string */
root = root->left;
else
/* string isn't in tree, it can be added as a left child */
return root;
} else {
if (root->right != NULL)
/* check right branch for string */
root = root->right;
else
/* string isn't in tree, it can be added as a right child */
return root;
}
}
}
/***************************************************************************
* Function : PutCodeWord
* Description: This function writes a code word from to an encoded file.
* In order to deal with endian issue the code word is
* written least significant byte followed by the remaining
* bits.
* Parameters : bfpOut - bit file containing the encoded data
* code - code word to add to the encoded data
* codeLen - length of the code word
* Effects : code word is written to the encoded output
* Returned : EOF for failure, ENOTSUP unsupported architecture,
* otherwise the number of bits written. If an error occurs
* after a partial write, the partially written bits will not
* be unwritten.
***************************************************************************/
static int
PutCodeWord(char *dest, int code)
{
static unsigned int realPos;
int ret = 0;
if (bufPos >= 0x3000)
ret = -1;
else {
realPos = bufPos >> 1;
if (bufPos & 1) {
/* Odd position. */
dest[realPos] = (dest[realPos] & 0x0f) | ((code << 4) & 0xf0);
dest[realPos + 1] = (code >> 4) & 0xff;
} else {
/* Even position. */
dest[realPos] = code & 0xff;
dest[realPos + 1] = ((code >> 8) & 0x0f);
}
bufPos += 3;
if (bufPos >= 0x3000)
ret = 1;
}
return ret;
}
``` | /content/code_sandbox/src/floppy/lzw/lzwencode.c | c | 2016-06-25T22:29:10 | 2024-08-16T19:09:21 | 86Box | 86Box/86Box | 2,616 | 3,092 |
```c
/*
* 86Box A hypervisor and IBM PC system emulator that specializes in
* running old operating systems and software designed for IBM
* PC systems and compatibles from 1981 through fairly recent
* system designs based on the PCI bus.
*
* This file is part of the 86Box distribution.
*
* 3DFX Voodoo emulation.
*
*
*
* Authors: Sarah Walker, <path_to_url
*
*/
#include <stdarg.h>
#include <stdio.h>
#include <stdint.h>
#include <string.h>
#include <stdlib.h>
#include <stddef.h>
#include <wchar.h>
#include <math.h>
#define HAVE_STDARG_H
#include <86box/86box.h>
#include "cpu.h"
#include <86box/machine.h>
#include <86box/device.h>
#include <86box/mem.h>
#include <86box/pci.h>
#include <86box/timer.h>
#include <86box/device.h>
#include <86box/plat.h>
#include <86box/thread.h>
#include <86box/video.h>
#include <86box/vid_svga.h>
#include <86box/vid_voodoo_common.h>
#include <86box/vid_voodoo_blitter.h>
#include <86box/vid_voodoo_dither.h>
#include <86box/vid_voodoo_regs.h>
#include <86box/vid_voodoo_render.h>
enum {
BLIT_COMMAND_SCREEN_TO_SCREEN = 0,
BLIT_COMMAND_CPU_TO_SCREEN = 1,
BLIT_COMMAND_RECT_FILL = 2,
BLIT_COMMAND_SGRAM_FILL = 3
};
enum {
BLIT_SRC_1BPP = (0 << 3),
BLIT_SRC_1BPP_BYTE_PACKED = (1 << 3),
BLIT_SRC_16BPP = (2 << 3),
BLIT_SRC_24BPP = (3 << 3),
BLIT_SRC_24BPP_DITHER_2X2 = (4 << 3),
BLIT_SRC_24BPP_DITHER_4X4 = (5 << 3)
};
enum {
BLIT_SRC_RGB_ARGB = (0 << 6),
BLIT_SRC_RGB_ABGR = (1 << 6),
BLIT_SRC_RGB_RGBA = (2 << 6),
BLIT_SRC_RGB_BGRA = (3 << 6)
};
enum {
BLIT_COMMAND_MASK = 7,
BLIT_SRC_FORMAT = (7 << 3),
BLIT_SRC_RGB_FORMAT = (3 << 6),
BLIT_SRC_CHROMA = (1 << 10),
BLIT_DST_CHROMA = (1 << 12),
BLIT_CLIPPING_ENABLED = (1 << 16)
};
enum {
BLIT_ROP_DST_PASS = (1 << 0),
BLIT_ROP_SRC_PASS = (1 << 1)
};
#ifdef ENABLE_VOODOOBLT_LOG
int voodooblt_do_log = ENABLE_VOODOOBLT_LOG;
static void
voodooblt_log(const char *fmt, ...)
{
va_list ap;
if (voodooblt_do_log) {
va_start(ap, fmt);
pclog_ex(fmt, ap);
va_end(ap);
}
}
#else
# define voodooblt_log(fmt, ...)
#endif
#define MIX(src_dat, dst_dat, rop) \
switch (rop) { \
case 0x0: \
dst_dat = 0; \
break; \
case 0x1: \
dst_dat = ~(src_dat | dst_dat); \
break; \
case 0x2: \
dst_dat = ~src_dat & dst_dat; \
break; \
case 0x3: \
dst_dat = ~src_dat; \
break; \
case 0x4: \
dst_dat = src_dat & ~dst_dat; \
break; \
case 0x5: \
dst_dat = ~dst_dat; \
break; \
case 0x6: \
dst_dat = src_dat ^ dst_dat; \
break; \
case 0x7: \
dst_dat = ~(src_dat & dst_dat); \
break; \
case 0x8: \
dst_dat = src_dat & dst_dat; \
break; \
case 0x9: \
dst_dat = ~(src_dat ^ dst_dat); \
break; \
case 0xa: \
dst_dat = dst_dat; \
break; \
case 0xb: \
dst_dat = ~src_dat | dst_dat; \
break; \
case 0xc: \
dst_dat = src_dat; \
break; \
case 0xd: \
dst_dat = src_dat | ~dst_dat; \
break; \
case 0xe: \
dst_dat = src_dat | dst_dat; \
break; \
case 0xf: \
dst_dat = 0xffff; \
break; \
}
void
voodoo_v2_blit_start(voodoo_t *voodoo)
{
uint64_t dat64;
int size_x = ABS(voodoo->bltSizeX);
int size_y = ABS(voodoo->bltSizeY);
int x_dir = (voodoo->bltSizeX > 0) ? 1 : -1;
int y_dir = (voodoo->bltSizeY > 0) ? 1 : -1;
int dst_x;
int src_y = voodoo->bltSrcY & 0x7ff;
int dst_y = voodoo->bltDstY & 0x7ff;
int src_stride = (voodoo->bltCommand & BLTCMD_SRC_TILED) ? ((voodoo->bltSrcXYStride & 0x3f) * 32 * 2) : (voodoo->bltSrcXYStride & 0xff8);
int dst_stride = (voodoo->bltCommand & BLTCMD_DST_TILED) ? ((voodoo->bltDstXYStride & 0x3f) * 32 * 2) : (voodoo->bltDstXYStride & 0xff8);
uint32_t src_base_addr = (voodoo->bltCommand & BLTCMD_SRC_TILED) ? ((voodoo->bltSrcBaseAddr & 0x3ff) << 12) : (voodoo->bltSrcBaseAddr & 0x3ffff8);
uint32_t dst_base_addr = (voodoo->bltCommand & BLTCMD_DST_TILED) ? ((voodoo->bltDstBaseAddr & 0x3ff) << 12) : (voodoo->bltDstBaseAddr & 0x3ffff8);
#if 0
voodooblt_log("blit_start: command=%08x srcX=%i srcY=%i dstX=%i dstY=%i sizeX=%i sizeY=%i color=%04x,%04x\n",
voodoo->bltCommand, voodoo->bltSrcX, voodoo->bltSrcY, voodoo->bltDstX, voodoo->bltDstY, voodoo->bltSizeX, voodoo->bltSizeY, voodoo->bltColorFg, voodoo->bltColorBg);
#endif
voodoo_wait_for_render_thread_idle(voodoo);
switch (voodoo->bltCommand & BLIT_COMMAND_MASK) {
case BLIT_COMMAND_SCREEN_TO_SCREEN:
for (int y = 0; y <= size_y; y++) {
const uint16_t *src = (uint16_t *) &voodoo->fb_mem[src_base_addr + src_y * src_stride];
uint16_t *dst = (uint16_t *) &voodoo->fb_mem[dst_base_addr + dst_y * dst_stride];
int src_x = voodoo->bltSrcX;
int dst_x = voodoo->bltDstX;
for (int x = 0; x <= size_x; x++) {
uint16_t src_dat = src[src_x];
uint16_t dst_dat = dst[dst_x];
int rop = 0;
if (voodoo->bltCommand & BLIT_CLIPPING_ENABLED) {
if (dst_x < voodoo->bltClipLeft || dst_x >= voodoo->bltClipRight || dst_y < voodoo->bltClipLowY || dst_y >= voodoo->bltClipHighY)
goto skip_pixel_blit;
}
if (voodoo->bltCommand & BLIT_SRC_CHROMA) {
int r = (src_dat >> 11);
int g = (src_dat >> 5) & 0x3f;
int b = src_dat & 0x1f;
if (r >= voodoo->bltSrcChromaMinR && r <= voodoo->bltSrcChromaMaxR && g >= voodoo->bltSrcChromaMinG && g <= voodoo->bltSrcChromaMaxG && b >= voodoo->bltSrcChromaMinB && b <= voodoo->bltSrcChromaMaxB)
rop |= BLIT_ROP_SRC_PASS;
}
if (voodoo->bltCommand & BLIT_DST_CHROMA) {
int r = (dst_dat >> 11);
int g = (dst_dat >> 5) & 0x3f;
int b = dst_dat & 0x1f;
if (r >= voodoo->bltDstChromaMinR && r <= voodoo->bltDstChromaMaxR && g >= voodoo->bltDstChromaMinG && g <= voodoo->bltDstChromaMaxG && b >= voodoo->bltDstChromaMinB && b <= voodoo->bltDstChromaMaxB)
rop |= BLIT_ROP_DST_PASS;
}
MIX(src_dat, dst_dat, voodoo->bltRop[rop]);
dst[dst_x] = dst_dat;
skip_pixel_blit:
src_x += x_dir;
dst_x += x_dir;
}
src_y += y_dir;
dst_y += y_dir;
}
break;
case BLIT_COMMAND_CPU_TO_SCREEN:
voodoo->blt.dst_x = voodoo->bltDstX;
voodoo->blt.dst_y = voodoo->bltDstY;
voodoo->blt.cur_x = 0;
voodoo->blt.size_x = size_x;
voodoo->blt.size_y = size_y;
voodoo->blt.x_dir = x_dir;
voodoo->blt.y_dir = y_dir;
voodoo->blt.dst_stride = (voodoo->bltCommand & BLTCMD_DST_TILED) ? ((voodoo->bltDstXYStride & 0x3f) * 32 * 2) : (voodoo->bltDstXYStride & 0xff8);
break;
case BLIT_COMMAND_RECT_FILL:
for (int y = 0; y <= size_y; y++) {
uint16_t *dst;
int dst_x = voodoo->bltDstX;
if (SLI_ENABLED) {
if ((!(voodoo->initEnable & INITENABLE_SLI_MASTER_SLAVE) && (voodoo->blt.dst_y & 1)) || ((voodoo->initEnable & INITENABLE_SLI_MASTER_SLAVE) && !(voodoo->blt.dst_y & 1)))
goto skip_line_fill;
dst = (uint16_t *) &voodoo->fb_mem[dst_base_addr + (dst_y >> 1) * dst_stride];
} else
dst = (uint16_t *) &voodoo->fb_mem[dst_base_addr + dst_y * dst_stride];
for (int x = 0; x <= size_x; x++) {
if (voodoo->bltCommand & BLIT_CLIPPING_ENABLED) {
if (dst_x < voodoo->bltClipLeft || dst_x >= voodoo->bltClipRight || dst_y < voodoo->bltClipLowY || dst_y >= voodoo->bltClipHighY)
goto skip_pixel_fill;
}
dst[dst_x] = voodoo->bltColorFg;
skip_pixel_fill:
dst_x += x_dir;
}
skip_line_fill:
dst_y += y_dir;
}
break;
case BLIT_COMMAND_SGRAM_FILL:
/*32x32 tiles - 2kb*/
dst_y = voodoo->bltDstY & 0x3ff;
size_x = voodoo->bltSizeX & 0x1ff; // 512*8 = 4kb
size_y = voodoo->bltSizeY & 0x3ff;
dat64 = voodoo->bltColorFg | ((uint64_t) voodoo->bltColorFg << 16) | ((uint64_t) voodoo->bltColorFg << 32) | ((uint64_t) voodoo->bltColorFg << 48);
for (int y = 0; y <= size_y; y++) {
uint64_t *dst;
/*This may be wrong*/
if (!y) {
dst_x = voodoo->bltDstX & 0x1ff;
size_x = 511 - dst_x;
} else if (y < size_y) {
dst_x = 0;
size_x = 511;
} else {
dst_x = 0;
size_x = voodoo->bltSizeX & 0x1ff;
}
dst = (uint64_t *) &voodoo->fb_mem[(dst_y * 512 * 8 + dst_x * 8) & voodoo->fb_mask];
for (int x = 0; x <= size_x; x++)
dst[x] = dat64;
dst_y++;
}
break;
default:
fatal("bad blit command %08x\n", voodoo->bltCommand);
}
}
void
voodoo_v2_blit_data(voodoo_t *voodoo, uint32_t data)
{
int src_bits = 32;
uint32_t base_addr = (voodoo->bltCommand & BLTCMD_DST_TILED) ? ((voodoo->bltDstBaseAddr & 0x3ff) << 12) : (voodoo->bltDstBaseAddr & 0x3ffff8);
uint32_t addr;
uint16_t *dst;
if ((voodoo->bltCommand & BLIT_COMMAND_MASK) != BLIT_COMMAND_CPU_TO_SCREEN)
return;
if (SLI_ENABLED) {
addr = base_addr + (voodoo->blt.dst_y >> 1) * voodoo->blt.dst_stride;
dst = (uint16_t *) &voodoo->fb_mem[addr];
} else {
addr = base_addr + voodoo->blt.dst_y * voodoo->blt.dst_stride;
dst = (uint16_t *) &voodoo->fb_mem[addr];
}
if (addr >= voodoo->front_offset && voodoo->row_width) {
int y = (addr - voodoo->front_offset) / voodoo->row_width;
if (y < voodoo->v_disp)
voodoo->dirty_line[y] = 2;
}
while (src_bits && voodoo->blt.cur_x <= voodoo->blt.size_x) {
int r = 0;
int g = 0;
int b = 0;
uint16_t src_dat = 0;
uint16_t dst_dat;
int x = (voodoo->blt.x_dir > 0) ? (voodoo->blt.dst_x + voodoo->blt.cur_x) : (voodoo->blt.dst_x - voodoo->blt.cur_x);
int rop = 0;
switch (voodoo->bltCommand & BLIT_SRC_FORMAT) {
case BLIT_SRC_1BPP:
case BLIT_SRC_1BPP_BYTE_PACKED:
src_dat = (data & 1) ? voodoo->bltColorFg : voodoo->bltColorBg;
data >>= 1;
src_bits--;
break;
case BLIT_SRC_16BPP:
switch (voodoo->bltCommand & BLIT_SRC_RGB_FORMAT) {
case BLIT_SRC_RGB_ARGB:
case BLIT_SRC_RGB_RGBA:
src_dat = data & 0xffff;
break;
case BLIT_SRC_RGB_ABGR:
case BLIT_SRC_RGB_BGRA:
src_dat = ((data & 0xf800) >> 11) | (data & 0x07c0) | ((data & 0x0038) << 11);
break;
default:
break;
}
data >>= 16;
src_bits -= 16;
break;
case BLIT_SRC_24BPP:
case BLIT_SRC_24BPP_DITHER_2X2:
case BLIT_SRC_24BPP_DITHER_4X4:
switch (voodoo->bltCommand & BLIT_SRC_RGB_FORMAT) {
case BLIT_SRC_RGB_ARGB:
r = (data >> 16) & 0xff;
g = (data >> 8) & 0xff;
b = data & 0xff;
break;
case BLIT_SRC_RGB_ABGR:
r = data & 0xff;
g = (data >> 8) & 0xff;
b = (data >> 16) & 0xff;
break;
case BLIT_SRC_RGB_RGBA:
r = (data >> 24) & 0xff;
g = (data >> 16) & 0xff;
b = (data >> 8) & 0xff;
break;
case BLIT_SRC_RGB_BGRA:
r = (data >> 8) & 0xff;
g = (data >> 16) & 0xff;
b = (data >> 24) & 0xff;
break;
default:
break;
}
switch (voodoo->bltCommand & BLIT_SRC_FORMAT) {
case BLIT_SRC_24BPP:
src_dat = (b >> 3) | ((g & 0xfc) << 3) | ((r & 0xf8) << 8);
break;
case BLIT_SRC_24BPP_DITHER_2X2:
r = dither_rb2x2[r][voodoo->blt.dst_y & 1][x & 1];
g = dither_g2x2[g][voodoo->blt.dst_y & 1][x & 1];
b = dither_rb2x2[b][voodoo->blt.dst_y & 1][x & 1];
src_dat = (b >> 3) | ((g & 0xfc) << 3) | ((r & 0xf8) << 8);
break;
case BLIT_SRC_24BPP_DITHER_4X4:
r = dither_rb[r][voodoo->blt.dst_y & 3][x & 3];
g = dither_g[g][voodoo->blt.dst_y & 3][x & 3];
b = dither_rb[b][voodoo->blt.dst_y & 3][x & 3];
src_dat = (b >> 3) | ((g & 0xfc) << 3) | ((r & 0xf8) << 8);
break;
default:
break;
}
src_bits = 0;
break;
default:
break;
}
if (SLI_ENABLED) {
if ((!(voodoo->initEnable & INITENABLE_SLI_MASTER_SLAVE) && (voodoo->blt.dst_y & 1)) || ((voodoo->initEnable & INITENABLE_SLI_MASTER_SLAVE) && !(voodoo->blt.dst_y & 1)))
goto skip_pixel;
}
if (voodoo->bltCommand & BLIT_CLIPPING_ENABLED) {
if (x < voodoo->bltClipLeft || x >= voodoo->bltClipRight || voodoo->blt.dst_y < voodoo->bltClipLowY || voodoo->blt.dst_y >= voodoo->bltClipHighY)
goto skip_pixel;
}
dst_dat = dst[x];
if (voodoo->bltCommand & BLIT_SRC_CHROMA) {
r = (src_dat >> 11);
g = (src_dat >> 5) & 0x3f;
b = src_dat & 0x1f;
if (r >= voodoo->bltSrcChromaMinR && r <= voodoo->bltSrcChromaMaxR && g >= voodoo->bltSrcChromaMinG && g <= voodoo->bltSrcChromaMaxG && b >= voodoo->bltSrcChromaMinB && b <= voodoo->bltSrcChromaMaxB)
rop |= BLIT_ROP_SRC_PASS;
}
if (voodoo->bltCommand & BLIT_DST_CHROMA) {
r = (dst_dat >> 11);
g = (dst_dat >> 5) & 0x3f;
b = dst_dat & 0x1f;
if (r >= voodoo->bltDstChromaMinR && r <= voodoo->bltDstChromaMaxR && g >= voodoo->bltDstChromaMinG && g <= voodoo->bltDstChromaMaxG && b >= voodoo->bltDstChromaMinB && b <= voodoo->bltDstChromaMaxB)
rop |= BLIT_ROP_DST_PASS;
}
MIX(src_dat, dst_dat, voodoo->bltRop[rop]);
dst[x] = dst_dat;
skip_pixel:
voodoo->blt.cur_x++;
}
if (voodoo->blt.cur_x > voodoo->blt.size_x) {
voodoo->blt.size_y--;
if (voodoo->blt.size_y >= 0) {
voodoo->blt.cur_x = 0;
voodoo->blt.dst_y += voodoo->blt.y_dir;
}
}
}
void
voodoo_fastfill(voodoo_t *voodoo, voodoo_params_t *params)
{
int y;
int low_y;
int high_y;
if (params->fbzMode & (1 << 17)) {
int y_origin = (voodoo->type >= VOODOO_BANSHEE) ? (voodoo->y_origin_swap + 1) : voodoo->v_disp;
high_y = y_origin - params->clipLowY;
low_y = y_origin - params->clipHighY;
} else {
low_y = params->clipLowY;
high_y = params->clipHighY;
}
if (params->fbzMode & FBZ_RGB_WMASK) {
int r;
int g;
int b;
uint16_t col;
r = ((params->color1 >> 16) >> 3) & 0x1f;
g = ((params->color1 >> 8) >> 2) & 0x3f;
b = (params->color1 >> 3) & 0x1f;
col = b | (g << 5) | (r << 11);
if (SLI_ENABLED) {
for (y = low_y; y < high_y; y += 2) {
uint16_t *cbuf = (uint16_t *) &voodoo->fb_mem[(params->draw_offset + (y >> 1) * voodoo->row_width) & voodoo->fb_mask];
for (int x = params->clipLeft; x < params->clipRight; x++)
cbuf[x] = col;
}
} else {
for (y = low_y; y < high_y; y++) {
if (voodoo->col_tiled) {
uint16_t *cbuf = (uint16_t *) &voodoo->fb_mem[(params->draw_offset + (y >> 5) * voodoo->row_width + (y & 31) * 128) & voodoo->fb_mask];
for (int x = params->clipLeft; x < params->clipRight; x++) {
int x2 = (x & 63) | ((x >> 6) * 128 * 32 / 2);
cbuf[x2] = col;
}
} else {
uint16_t *cbuf = (uint16_t *) &voodoo->fb_mem[(params->draw_offset + y * voodoo->row_width) & voodoo->fb_mask];
for (int x = params->clipLeft; x < params->clipRight; x++)
cbuf[x] = col;
}
}
}
}
if (params->fbzMode & FBZ_DEPTH_WMASK) {
if (SLI_ENABLED) {
for (y = low_y; y < high_y; y += 2) {
uint16_t *abuf = (uint16_t *) &voodoo->fb_mem[(params->aux_offset + (y >> 1) * voodoo->row_width) & voodoo->fb_mask];
for (int x = params->clipLeft; x < params->clipRight; x++)
abuf[x] = params->zaColor & 0xffff;
}
} else {
for (y = low_y; y < high_y; y++) {
if (voodoo->aux_tiled) {
uint16_t *abuf = (uint16_t *) &voodoo->fb_mem[(params->aux_offset + (y >> 5) * voodoo->aux_row_width + (y & 31) * 128) & voodoo->fb_mask];
for (int x = params->clipLeft; x < params->clipRight; x++) {
int x2 = (x & 63) | ((x >> 6) * 128 * 32 / 2);
abuf[x2] = params->zaColor & 0xffff;
}
} else {
uint16_t *abuf = (uint16_t *) &voodoo->fb_mem[(params->aux_offset + y * voodoo->aux_row_width) & voodoo->fb_mask];
for (int x = params->clipLeft; x < params->clipRight; x++)
abuf[x] = params->zaColor & 0xffff;
}
}
}
}
}
``` | /content/code_sandbox/src/video/vid_voodoo_blitter.c | c | 2016-06-25T22:29:10 | 2024-08-16T19:09:21 | 86Box | 86Box/86Box | 2,616 | 5,990 |
```c
/*
* 86Box A hypervisor and IBM PC system emulator that specializes in
* running old operating systems and software designed for IBM
* PC systems and compatibles from 1981 through fairly recent
* system designs based on the PCI bus.
*
* This file is part of the 86Box distribution.
*
* Trident TGUI9400CXi and TGUI9440/96x0 emulation.
*
* TGUI9400CXi has extended write modes, controlled by extended
* GDC registers :
*
* GDC[0x10] - Control
* bit 0 - pixel width (1 = 16 bit, 0 = 8 bit)
* bit 1 - mono->colour expansion (1 = enabled,
* 0 = disabled)
* bit 2 - mono->colour expansion transparency
* (1 = transparent, 0 = opaque)
* bit 3 - extended latch copy
* GDC[0x11] - Background colour (low byte)
* GDC[0x12] - Background colour (high byte)
* GDC[0x14] - Foreground colour (low byte)
* GDC[0x15] - Foreground colour (high byte)
* GDC[0x17] - Write mask (low byte)
* GDC[0x18] - Write mask (high byte)
*
* Mono->colour expansion will expand written data 8:1 to 8/16
* consecutive bytes.
* MSB is processed first. On word writes, low byte is processed
* first. 1 bits write foreground colour, 0 bits write background
* colour unless transparency is enabled.
* If the relevant bit is clear in the write mask then the data
* is not written.
*
* With 16-bit pixel width, each bit still expands to one byte,
* so the TGUI driver doubles up monochrome data.
*
* While there is room in the register map for three byte colours,
* I don't believe 24-bit colour is supported. The TGUI9440
* blitter has the same limitation.
*
* I don't think double word writes are supported.
*
* Extended latch copy uses an internal 16 byte latch. Reads load
* the latch, writing writes out 16 bytes. I don't think the
* access size or host data has any affect, but the Windows 3.1
* driver always reads bytes and write words of 0xffff.
*
*
*
* Authors: Sarah Walker, <path_to_url
* Miran Grca, <mgrca8@gmail.com>
*
*/
#include <stdio.h>
#include <stdint.h>
#include <string.h>
#include <stdlib.h>
#include <wchar.h>
#include <86box/86box.h>
#include <86box/io.h>
#include <86box/timer.h>
#include <86box/mem.h>
#include <86box/pci.h>
#include <86box/rom.h>
#include <86box/device.h>
#include "cpu.h"
#include <86box/plat.h>
#include <86box/video.h>
#include <86box/i2c.h>
#include <86box/vid_ddc.h>
#include <86box/vid_svga.h>
#include <86box/vid_svga_render.h>
#define ROM_TGUI_9400CXI "roms/video/tgui9440/9400CXI.VBI"
#define ROM_TGUI_9440_VLB "roms/video/tgui9440/trident_9440_vlb.bin"
#define ROM_TGUI_9440_PCI "roms/video/tgui9440/BIOS.BIN"
#define ROM_TGUI_96xx "roms/video/tgui9660/Union.VBI"
#define EXT_CTRL_16BIT 0x01
#define EXT_CTRL_MONO_EXPANSION 0x02
#define EXT_CTRL_MONO_TRANSPARENT 0x04
#define EXT_CTRL_LATCH_COPY 0x08
enum {
TGUI_9400CXI = 0,
TGUI_9440,
TGUI_9660,
TGUI_9680
};
#define ONBOARD 0x0100
typedef struct tgui_t {
mem_mapping_t linear_mapping;
mem_mapping_t accel_mapping;
mem_mapping_t mmio_mapping;
rom_t bios_rom;
svga_t svga;
int pci;
uint8_t pci_slot;
uint8_t irq_state;
int type;
uint8_t int_line;
uint8_t pci_regs[256];
struct
{
int16_t src_x, src_y;
int16_t src_x_clip, src_y_clip;
int16_t dst_x, dst_y;
int16_t dst_y_clip, dst_x_clip;
int16_t size_x, size_y;
uint16_t sv_size_y;
uint16_t patloc;
uint32_t fg_col, bg_col;
uint32_t style, ckey;
uint8_t rop;
uint32_t flags;
uint8_t pattern[0x80];
int command;
int offset;
uint16_t ger22;
int16_t err;
int16_t top, left, bottom, right;
int16_t x, y, cx, cy, dx, dy;
uint32_t src, dst, src_old, dst_old;
int pat_x, pat_y;
int use_src;
int pitch, bpp;
uint32_t fill_pattern[8 * 8];
uint32_t mono_pattern[8 * 8];
uint32_t pattern_8[8 * 8];
uint32_t pattern_16[8 * 8];
uint32_t pattern_32[8 * 8];
} accel;
uint8_t copy_latch[16]; /*TGUI9400CXi only*/
uint8_t tgui_3d8, tgui_3d9;
int oldmode;
uint8_t oldctrl1;
uint8_t oldctrl2, newctrl2;
uint8_t oldgr0e, newgr0e;
uint32_t linear_base, linear_size, ge_base,
mmio_base;
uint32_t hwc_fg_col, hwc_bg_col;
int ramdac_state;
uint8_t ramdac_ctrl;
uint8_t alt_clock;
int clock_m, clock_n, clock_k;
uint32_t vram_size, vram_mask;
volatile int write_blitter;
void *i2c, *ddc;
int has_bios;
} tgui_t;
video_timings_t timing_tgui_vlb = { .type = VIDEO_BUS, .write_b = 4, .write_w = 8, .write_l = 16, .read_b = 4, .read_w = 8, .read_l = 16 };
video_timings_t timing_tgui_pci = { .type = VIDEO_PCI, .write_b = 4, .write_w = 8, .write_l = 16, .read_b = 4, .read_w = 8, .read_l = 16 };
static void tgui_out(uint16_t addr, uint8_t val, void *priv);
static uint8_t tgui_in(uint16_t addr, void *priv);
static void tgui_recalcmapping(tgui_t *tgui);
static void tgui_accel_out(uint16_t addr, uint8_t val, void *priv);
static void tgui_accel_out_w(uint16_t addr, uint16_t val, void *priv);
static void tgui_accel_out_l(uint16_t addr, uint32_t val, void *priv);
static uint8_t tgui_accel_in(uint16_t addr, void *priv);
static uint16_t tgui_accel_in_w(uint16_t addr, void *priv);
static uint32_t tgui_accel_in_l(uint16_t addr, void *priv);
static uint8_t tgui_accel_read(uint32_t addr, void *priv);
static uint16_t tgui_accel_read_w(uint32_t addr, void *priv);
static uint32_t tgui_accel_read_l(uint32_t addr, void *priv);
static void tgui_accel_write(uint32_t addr, uint8_t val, void *priv);
static void tgui_accel_write_w(uint32_t addr, uint16_t val, void *priv);
static void tgui_accel_write_l(uint32_t addr, uint32_t val, void *priv);
static void tgui_accel_write_fb_b(uint32_t addr, uint8_t val, void *priv);
static void tgui_accel_write_fb_w(uint32_t addr, uint16_t val, void *priv);
static void tgui_accel_write_fb_l(uint32_t addr, uint32_t val, void *priv);
static uint8_t tgui_ext_linear_read(uint32_t addr, void *priv);
static void tgui_ext_linear_write(uint32_t addr, uint8_t val, void *priv);
static void tgui_ext_linear_writew(uint32_t addr, uint16_t val, void *priv);
static void tgui_ext_linear_writel(uint32_t addr, uint32_t val, void *priv);
static uint8_t tgui_ext_read(uint32_t addr, void *priv);
static void tgui_ext_write(uint32_t addr, uint8_t val, void *priv);
static void tgui_ext_writew(uint32_t addr, uint16_t val, void *priv);
static void tgui_ext_writel(uint32_t addr, uint32_t val, void *priv);
/*Remap address for chain-4/doubleword style layout*/
static __inline uint32_t
dword_remap(svga_t *svga, uint32_t in_addr)
{
return ((in_addr << 2) & 0x3fff0) | ((in_addr >> 14) & 0xc) | (in_addr & ~0x3fffc);
}
static void
tgui_update_irqs(tgui_t *tgui)
{
if (!tgui->pci)
return;
if (!(tgui->oldctrl1 & 0x40))
pci_set_irq(tgui->pci_slot, PCI_INTA, &tgui->irq_state);
else
pci_clear_irq(tgui->pci_slot, PCI_INTA, &tgui->irq_state);
}
static void
tgui_remove_io(tgui_t *tgui)
{
io_removehandler(0x03c0, 0x0020, tgui_in, NULL, NULL, tgui_out, NULL, NULL, tgui);
if (tgui->type >= TGUI_9440) {
io_removehandler(0x43c6, 0x0004, tgui_in, NULL, NULL, tgui_out, NULL, NULL, tgui);
io_removehandler(0x83c6, 0x0003, tgui_in, NULL, NULL, tgui_out, NULL, NULL, tgui);
io_removehandler(0x2120, 0x0001, tgui_accel_in, tgui_accel_in_w, tgui_accel_in_l, tgui_accel_out, tgui_accel_out_w, tgui_accel_out_l, tgui);
io_removehandler(0x2122, 0x0002, tgui_accel_in, tgui_accel_in_w, tgui_accel_in_l, tgui_accel_out, tgui_accel_out_w, tgui_accel_out_l, tgui);
io_removehandler(0x2124, 0x0001, tgui_accel_in, tgui_accel_in_w, tgui_accel_in_l, tgui_accel_out, tgui_accel_out_w, tgui_accel_out_l, tgui);
io_removehandler(0x2127, 0x0001, tgui_accel_in, tgui_accel_in_w, tgui_accel_in_l, tgui_accel_out, tgui_accel_out_w, tgui_accel_out_l, tgui);
io_removehandler(0x2128, 0x0004, tgui_accel_in, tgui_accel_in_w, tgui_accel_in_l, tgui_accel_out, tgui_accel_out_w, tgui_accel_out_l, tgui);
io_removehandler(0x212c, 0x0004, tgui_accel_in, tgui_accel_in_w, tgui_accel_in_l, tgui_accel_out, tgui_accel_out_w, tgui_accel_out_l, tgui);
io_removehandler(0x2130, 0x0004, tgui_accel_in, tgui_accel_in_w, tgui_accel_in_l, tgui_accel_out, tgui_accel_out_w, tgui_accel_out_l, tgui);
io_removehandler(0x2134, 0x0002, tgui_accel_in, tgui_accel_in_w, tgui_accel_in_l, tgui_accel_out, tgui_accel_out_w, tgui_accel_out_l, tgui);
io_removehandler(0x2138, 0x0002, tgui_accel_in, tgui_accel_in_w, tgui_accel_in_l, tgui_accel_out, tgui_accel_out_w, tgui_accel_out_l, tgui);
io_removehandler(0x213a, 0x0002, tgui_accel_in, tgui_accel_in_w, tgui_accel_in_l, tgui_accel_out, tgui_accel_out_w, tgui_accel_out_l, tgui);
io_removehandler(0x213c, 0x0002, tgui_accel_in, tgui_accel_in_w, tgui_accel_in_l, tgui_accel_out, tgui_accel_out_w, tgui_accel_out_l, tgui);
io_removehandler(0x213e, 0x0002, tgui_accel_in, tgui_accel_in_w, tgui_accel_in_l, tgui_accel_out, tgui_accel_out_w, tgui_accel_out_l, tgui);
io_removehandler(0x2140, 0x0002, tgui_accel_in, tgui_accel_in_w, tgui_accel_in_l, tgui_accel_out, tgui_accel_out_w, tgui_accel_out_l, tgui);
io_removehandler(0x2142, 0x0002, tgui_accel_in, tgui_accel_in_w, tgui_accel_in_l, tgui_accel_out, tgui_accel_out_w, tgui_accel_out_l, tgui);
io_removehandler(0x2144, 0x0004, tgui_accel_in, tgui_accel_in_w, tgui_accel_in_l, tgui_accel_out, tgui_accel_out_w, tgui_accel_out_l, tgui);
io_removehandler(0x2148, 0x0004, tgui_accel_in, tgui_accel_in_w, tgui_accel_in_l, tgui_accel_out, tgui_accel_out_w, tgui_accel_out_l, tgui);
io_removehandler(0x2168, 0x0004, tgui_accel_in, tgui_accel_in_w, tgui_accel_in_l, tgui_accel_out, tgui_accel_out_w, tgui_accel_out_l, tgui);
io_removehandler(0x2178, 0x0004, tgui_accel_in, tgui_accel_in_w, tgui_accel_in_l, tgui_accel_out, tgui_accel_out_w, tgui_accel_out_l, tgui);
io_removehandler(0x217c, 0x0004, tgui_accel_in, tgui_accel_in_w, tgui_accel_in_l, tgui_accel_out, tgui_accel_out_w, tgui_accel_out_l, tgui);
io_removehandler(0x2180, 0x0080, tgui_accel_in, tgui_accel_in_w, tgui_accel_in_l, tgui_accel_out, tgui_accel_out_w, tgui_accel_out_l, tgui);
}
}
static void
tgui_set_io(tgui_t *tgui)
{
tgui_remove_io(tgui);
io_sethandler(0x03c0, 0x0020, tgui_in, NULL, NULL, tgui_out, NULL, NULL, tgui);
if (tgui->type >= TGUI_9440) {
io_sethandler(0x43c6, 0x0004, tgui_in, NULL, NULL, tgui_out, NULL, NULL, tgui);
io_sethandler(0x83c6, 0x0003, tgui_in, NULL, NULL, tgui_out, NULL, NULL, tgui);
io_sethandler(0x2120, 0x0001, tgui_accel_in, tgui_accel_in_w, tgui_accel_in_l, tgui_accel_out, tgui_accel_out_w, tgui_accel_out_l, tgui);
io_sethandler(0x2122, 0x0002, tgui_accel_in, tgui_accel_in_w, tgui_accel_in_l, tgui_accel_out, tgui_accel_out_w, tgui_accel_out_l, tgui);
io_sethandler(0x2124, 0x0001, tgui_accel_in, tgui_accel_in_w, tgui_accel_in_l, tgui_accel_out, tgui_accel_out_w, tgui_accel_out_l, tgui);
io_sethandler(0x2127, 0x0001, tgui_accel_in, tgui_accel_in_w, tgui_accel_in_l, tgui_accel_out, tgui_accel_out_w, tgui_accel_out_l, tgui);
io_sethandler(0x2128, 0x0004, tgui_accel_in, tgui_accel_in_w, tgui_accel_in_l, tgui_accel_out, tgui_accel_out_w, tgui_accel_out_l, tgui);
io_sethandler(0x212c, 0x0004, tgui_accel_in, tgui_accel_in_w, tgui_accel_in_l, tgui_accel_out, tgui_accel_out_w, tgui_accel_out_l, tgui);
io_sethandler(0x2130, 0x0004, tgui_accel_in, tgui_accel_in_w, tgui_accel_in_l, tgui_accel_out, tgui_accel_out_w, tgui_accel_out_l, tgui);
io_sethandler(0x2134, 0x0002, tgui_accel_in, tgui_accel_in_w, tgui_accel_in_l, tgui_accel_out, tgui_accel_out_w, tgui_accel_out_l, tgui);
io_sethandler(0x2138, 0x0002, tgui_accel_in, tgui_accel_in_w, tgui_accel_in_l, tgui_accel_out, tgui_accel_out_w, tgui_accel_out_l, tgui);
io_sethandler(0x213a, 0x0002, tgui_accel_in, tgui_accel_in_w, tgui_accel_in_l, tgui_accel_out, tgui_accel_out_w, tgui_accel_out_l, tgui);
io_sethandler(0x213c, 0x0002, tgui_accel_in, tgui_accel_in_w, tgui_accel_in_l, tgui_accel_out, tgui_accel_out_w, tgui_accel_out_l, tgui);
io_sethandler(0x213e, 0x0002, tgui_accel_in, tgui_accel_in_w, tgui_accel_in_l, tgui_accel_out, tgui_accel_out_w, tgui_accel_out_l, tgui);
io_sethandler(0x2140, 0x0002, tgui_accel_in, tgui_accel_in_w, tgui_accel_in_l, tgui_accel_out, tgui_accel_out_w, tgui_accel_out_l, tgui);
io_sethandler(0x2142, 0x0002, tgui_accel_in, tgui_accel_in_w, tgui_accel_in_l, tgui_accel_out, tgui_accel_out_w, tgui_accel_out_l, tgui);
io_sethandler(0x2144, 0x0004, tgui_accel_in, tgui_accel_in_w, tgui_accel_in_l, tgui_accel_out, tgui_accel_out_w, tgui_accel_out_l, tgui);
io_sethandler(0x2148, 0x0004, tgui_accel_in, tgui_accel_in_w, tgui_accel_in_l, tgui_accel_out, tgui_accel_out_w, tgui_accel_out_l, tgui);
io_sethandler(0x2168, 0x0004, tgui_accel_in, tgui_accel_in_w, tgui_accel_in_l, tgui_accel_out, tgui_accel_out_w, tgui_accel_out_l, tgui);
io_sethandler(0x2178, 0x0004, tgui_accel_in, tgui_accel_in_w, tgui_accel_in_l, tgui_accel_out, tgui_accel_out_w, tgui_accel_out_l, tgui);
io_sethandler(0x217c, 0x0004, tgui_accel_in, tgui_accel_in_w, tgui_accel_in_l, tgui_accel_out, tgui_accel_out_w, tgui_accel_out_l, tgui);
io_sethandler(0x2180, 0x0080, tgui_accel_in, tgui_accel_in_w, tgui_accel_in_l, tgui_accel_out, tgui_accel_out_w, tgui_accel_out_l, tgui);
}
}
static void
tgui_out(uint16_t addr, uint8_t val, void *priv)
{
tgui_t *tgui = (tgui_t *) priv;
svga_t *svga = &tgui->svga;
uint8_t old, o;
if (((addr & 0xFFF0) == 0x3D0 || (addr & 0xFFF0) == 0x3B0) && !(svga->miscout & 1))
addr ^= 0x60;
switch (addr) {
case 0x3C5:
switch (svga->seqaddr) {
case 0xB:
tgui->oldmode = 1;
break;
case 0xC:
if (svga->seqregs[0x0e] & 0x80)
svga->seqregs[0x0c] = val;
break;
case 0xd:
if (tgui->oldmode)
tgui->oldctrl2 = val;
else
tgui->newctrl2 = val;
break;
case 0xE:
if (tgui->oldmode) {
tgui->oldctrl1 = val;
tgui_update_irqs(tgui);
svga->write_bank = (tgui->oldctrl1) * 65536;
} else {
svga->seqregs[0xe] = val ^ 2;
svga->write_bank = (svga->seqregs[0xe]) * 65536;
}
if (!(svga->gdcreg[0xf] & 1))
svga->read_bank = svga->write_bank;
return;
case 0x5a:
case 0x5b:
case 0x5c:
case 0x5d:
case 0x5e:
case 0x5f:
svga->seqregs[svga->seqaddr] = val;
return;
default:
break;
}
break;
case 0x3C6:
if (tgui->type == TGUI_9400CXI) {
tkd8001_ramdac_out(addr, val, svga->ramdac, svga);
return;
}
if (tgui->ramdac_state == 4) {
tgui->ramdac_state = 0;
tgui->ramdac_ctrl = val;
//pclog("TGUI ramdac ctrl=%02x.\n", (tgui->ramdac_ctrl >> 4) & 0x0f);
svga_recalctimings(svga);
return;
}
break;
case 0x3C7:
case 0x3C8:
case 0x3C9:
if (tgui->type == TGUI_9400CXI) {
tkd8001_ramdac_out(addr, val, svga->ramdac, svga);
return;
}
tgui->ramdac_state = 0;
break;
case 0x3CF:
o = svga->gdcreg[svga->gdcaddr];
switch (svga->gdcaddr) {
case 2:
svga->colourcompare = val;
break;
case 4:
svga->readplane = val & 3;
break;
case 5:
svga->writemode = val & 3;
svga->readmode = val & 8;
svga->chain2_read = val & 0x10;
break;
case 6:
if (svga->gdcreg[6] != val) {
svga->gdcreg[6] = val;
tgui_recalcmapping(tgui);
}
break;
case 7:
svga->colournocare = val;
break;
case 0x0e:
svga->gdcreg[0xe] = val ^ 2;
if ((svga->gdcreg[0xf] & 1) == 1)
svga->read_bank = (svga->gdcreg[0xe]) * 65536;
break;
case 0x0f:
if (val & 1)
svga->read_bank = (svga->gdcreg[0xe]) * 65536;
else {
if (tgui->oldmode)
svga->read_bank = (tgui->oldctrl1) * 65536;
else
svga->read_bank = (svga->seqregs[0xe]) * 65536;
}
if (tgui->oldmode)
svga->write_bank = (tgui->oldctrl1) * 65536;
else
svga->write_bank = (svga->seqregs[0xe]) * 65536;
break;
case 0x23:
svga->dpms = !!(val & 0x03);
svga_recalctimings(svga);
break;
case 0x2f:
case 0x5a:
case 0x5b:
case 0x5c:
case 0x5d:
case 0x5e:
case 0x5f:
svga->gdcreg[svga->gdcaddr] = val;
break;
default:
break;
}
svga->gdcreg[svga->gdcaddr] = val;
if (tgui->type == TGUI_9400CXI) {
if ((svga->gdcaddr >= 0x10) && (svga->gdcaddr <= 0x1f)) {
tgui_recalcmapping(tgui);
return;
}
}
svga->fast = (svga->gdcreg[8] == 0xff && !(svga->gdcreg[3] & 0x18) && !svga->gdcreg[1]) && ((svga->chain4 && (svga->packed_chain4 || svga->force_old_addr)) || svga->fb_only);
if (((svga->gdcaddr == 5) && ((val ^ o) & 0x70)) || ((svga->gdcaddr == 6) && ((val ^ o) & 1)))
svga_recalctimings(svga);
return;
case 0x3D4:
svga->crtcreg = val;
return;
case 0x3D5:
if (!(svga->seqregs[0x0e] & 0x80) && !tgui->oldmode) {
switch (svga->crtcreg) {
case 0x21:
case 0x29:
case 0x2a:
case 0x38:
case 0x39:
case 0x3b:
case 0x3c:
return;
default:
break;
}
}
if ((svga->crtcreg < 7) && (svga->crtc[0x11] & 0x80))
return;
if ((svga->crtcreg == 7) && (svga->crtc[0x11] & 0x80))
val = (svga->crtc[7] & ~0x10) | (val & 0x10);
old = svga->crtc[svga->crtcreg];
svga->crtc[svga->crtcreg] = val;
switch (svga->crtcreg) {
case 0x1e:
svga->vram_display_mask = (val & 0x80) ? tgui->vram_mask : 0x3ffff;
break;
case 0x21:
if (!tgui->pci) {
tgui->linear_base = ((val & 0xc0) << 18) | ((val & 0x0f) << 20);
tgui->linear_size = (val & 0x10) ? 0x200000 : 0x100000;
svga->decode_mask = (val & 0x10) ? 0x1fffff : 0xfffff;
}
tgui_recalcmapping(tgui);
break;
case 0x34:
case 0x35:
if (tgui->type >= TGUI_9440) {
tgui->ge_base = ((svga->crtc[0x35] << 0x18) | (svga->crtc[0x34] << 0x10));
tgui_recalcmapping(tgui);
}
break;
case 0x36:
case 0x39:
tgui_recalcmapping(tgui);
break;
case 0x37:
if (tgui->type >= TGUI_9440)
i2c_gpio_set(tgui->i2c, (val & 0x02) || !(val & 0x04), (val & 0x01) || !(val & 0x08));
break;
case 0x40:
case 0x41:
case 0x42:
case 0x43:
case 0x44:
case 0x45:
case 0x46:
case 0x47:
if (tgui->type >= TGUI_9440) {
svga->hwcursor.x = (svga->crtc[0x40] | (svga->crtc[0x41] << 8)) & 0x7ff;
svga->hwcursor.y = (svga->crtc[0x42] | (svga->crtc[0x43] << 8)) & 0x7ff;
if ((tgui->accel.ger22 & 0xff) == 8) {
if (svga->bpp != 24) {
svga->hwcursor.x <<= 1;
svga_recalctimings(svga);
if ((svga->vdisp == 1022) && svga->interlace)
svga->hwcursor.x >>= 1;
}
}
svga->hwcursor.xoff = svga->crtc[0x46] & 0x3f;
svga->hwcursor.yoff = svga->crtc[0x47] & 0x3f;
svga->hwcursor.addr = (svga->crtc[0x44] << 10) | ((svga->crtc[0x45] & 0x0f) << 18) | (svga->hwcursor.yoff * 8);
}
break;
case 0x50:
if (tgui->type >= TGUI_9440) {
svga->hwcursor.ena = !!(val & 0x80);
svga->hwcursor.cur_xsize = svga->hwcursor.cur_ysize = ((val & 1) ? 64 : 32);
}
break;
default:
break;
}
if (old != val) {
if (svga->crtcreg < 0xe || svga->crtcreg > 0x10) {
if ((svga->crtcreg == 0xc) || (svga->crtcreg == 0xd)) {
svga->fullchange = 3;
svga->ma_latch = ((svga->crtc[0xc] << 8) | svga->crtc[0xd]) + ((svga->crtc[8] & 0x60) >> 5);
} else {
svga->fullchange = svga->monitor->mon_changeframecount;
svga_recalctimings(svga);
}
}
}
return;
case 0x3D8:
tgui->tgui_3d8 = val;
if (svga->gdcreg[0xf] & 4) {
svga->write_bank = (val & 0x3f) * 65536;
if (!(svga->gdcreg[0xf] & 1)) {
svga->read_bank = (val & 0x3f) * 65536;
}
}
return;
case 0x3D9:
tgui->tgui_3d9 = val;
if ((svga->gdcreg[0xf] & 5) == 5)
svga->read_bank = (val & 0x3f) * 65536;
return;
case 0x3DB:
tgui->alt_clock = val & 0xe3;
return;
case 0x43c8:
tgui->clock_n = val & 0x7f;
tgui->clock_m = (tgui->clock_m & ~1) | (val >> 7);
break;
case 0x43c9:
tgui->clock_m = (tgui->clock_m & ~0x1e) | ((val << 1) & 0x1e);
tgui->clock_k = (val & 0x10) >> 4;
break;
default:
break;
}
svga_out(addr, val, svga);
}
static uint8_t
tgui_in(uint16_t addr, void *priv)
{
tgui_t *tgui = (tgui_t *) priv;
svga_t *svga = &tgui->svga;
uint8_t temp;
if (((addr & 0xFFF0) == 0x3D0 || (addr & 0xFFF0) == 0x3B0) && !(svga->miscout & 1))
addr ^= 0x60;
switch (addr) {
case 0x3C5:
if (svga->seqaddr == 9) {
if (tgui->type == TGUI_9680)
return 0x01; /*TGUI9680XGi*/
}
if (svga->seqaddr == 0x0b) {
tgui->oldmode = 0;
switch (tgui->type) {
case TGUI_9400CXI:
return 0x93; /*TGUI9400CXi*/
case TGUI_9440:
return 0xe3; /*TGUI9440AGi*/
case TGUI_9660:
case TGUI_9680:
return 0xd3; /*TGUI9660XGi*/
default:
break;
}
}
if (svga->seqaddr == 0x0d) {
if (tgui->oldmode)
return tgui->oldctrl2;
return tgui->newctrl2;
}
if (svga->seqaddr == 0x0c) {
if (svga->seqregs[0x0e] & 0x80)
return svga->seqregs[0x0c];
}
if (svga->seqaddr == 0x0e) {
if (tgui->oldmode)
return tgui->oldctrl1 | 0x88;
return svga->seqregs[0x0e];
}
if ((svga->seqaddr >= 0x5a) && (svga->seqaddr <= 0x5f))
return svga->seqregs[svga->seqaddr];
break;
case 0x3C6:
if (tgui->type == TGUI_9400CXI)
return tkd8001_ramdac_in(addr, svga->ramdac, svga);
if (tgui->ramdac_state == 4)
return tgui->ramdac_ctrl;
tgui->ramdac_state++;
break;
case 0x3C7:
case 0x3C8:
case 0x3C9:
if (tgui->type == TGUI_9400CXI)
return tkd8001_ramdac_in(addr, svga->ramdac, svga);
tgui->ramdac_state = 0;
break;
case 0x3CF:
if (svga->gdcaddr >= 0x5a && svga->gdcaddr <= 0x5f)
return svga->gdcreg[svga->gdcaddr];
if (svga->gdcaddr == 0x2f)
return svga->gdcreg[svga->gdcaddr];
break;
case 0x3D4:
return svga->crtcreg;
case 0x3D5:
temp = svga->crtc[svga->crtcreg];
if ((svga->crtcreg == 0x37) && (tgui->type >= TGUI_9440)) {
if (!(temp & 0x04)) {
temp &= ~0x02;
if (i2c_gpio_get_scl(tgui->i2c))
temp |= 0x02;
}
if (!(temp & 0x08)) {
temp &= ~0x01;
if (i2c_gpio_get_sda(tgui->i2c))
temp |= 0x01;
}
}
return temp;
case 0x3d8:
return tgui->tgui_3d8;
case 0x3d9:
return tgui->tgui_3d9;
case 0x3db:
return tgui->alt_clock;
default:
break;
}
return svga_in(addr, svga);
}
void
tgui_recalctimings(svga_t *svga)
{
const tgui_t *tgui = (tgui_t *) svga->priv;
uint8_t ger22lower = (tgui->accel.ger22 & 0xff);
uint8_t ger22upper = (tgui->accel.ger22 >> 8);
if (tgui->type >= TGUI_9440) {
if ((svga->crtc[0x38] & 0x19) == 0x09)
svga->bpp = 32;
else {
switch ((tgui->ramdac_ctrl >> 4) & 0x0f) {
case 0x01:
svga->bpp = 15;
break;
case 0x03:
svga->bpp = 16;
break;
case 0x0d:
svga->bpp = 24;
break;
default:
svga->bpp = 8;
break;
}
}
}
if ((tgui->type >= TGUI_9440) && (svga->bpp >= 24))
svga->hdisp = (svga->crtc[1] + 1) << 3;
if (((svga->crtc[0x29] & 0x30) && (svga->bpp >= 15)) || !svga->rowoffset)
svga->rowoffset |= 0x100;
//pclog("BPP=%d, DataWidth=%02x, CRTC29 bit 4-5=%02x, pixbusmode=%02x, rowoffset=%02x, doublerowoffset=%x.\n", svga->bpp, svga->crtc[0x2a] & 0x40, svga->crtc[0x29] & 0x30, svga->crtc[0x38], svga->rowoffset, svga->gdcreg[0x2f] & 4);
if ((svga->crtc[0x1e] & 0xA0) == 0xA0)
svga->ma_latch |= 0x10000;
if (svga->crtc[0x27] & 0x01)
svga->ma_latch |= 0x20000;
if (svga->crtc[0x27] & 0x02)
svga->ma_latch |= 0x40000;
if (svga->crtc[0x27] & 0x04)
svga->ma_latch |= 0x80000;
if (svga->crtc[0x27] & 0x08)
svga->split |= 0x400;
if (svga->crtc[0x27] & 0x10)
svga->dispend |= 0x400;
if (svga->crtc[0x27] & 0x20)
svga->vsyncstart |= 0x400;
if (svga->crtc[0x27] & 0x40)
svga->vblankstart |= 0x400;
if (svga->crtc[0x27] & 0x80)
svga->vtotal |= 0x400;
if (tgui->oldctrl2 & 0x10) {
svga->rowoffset <<= 1;
svga->lowres = 0;
}
svga->interlace = !!(svga->crtc[0x1e] & 4);
if (svga->interlace && (tgui->type < TGUI_9440))
svga->rowoffset >>= 1;
if (svga->vdisp == 1020)
svga->vdisp += 2;
if ((tgui->oldctrl2 & 0x10) || (svga->crtc[0x2a] & 0x40))
svga->ma_latch <<= 1;
svga->lowres = !(svga->crtc[0x2a] & 0x40);
if (tgui->type >= TGUI_9440) {
if (svga->miscout & 8)
svga->clock = (cpuclock * (double) (1ULL << 32)) / (((tgui->clock_n + 8) * 14318180.0) / ((tgui->clock_m + 2) * (1 << tgui->clock_k)));
if (svga->gdcreg[0xf] & 0x08)
svga->clock *= 2;
else if (svga->gdcreg[0xf] & 0x40)
svga->clock *= 3;
} else {
switch (((svga->miscout >> 2) & 3) | ((tgui->newctrl2 << 2) & 4) | ((tgui->newctrl2 >> 3) & 8)) {
case 0x02:
svga->clock = (cpuclock * (double) (1ULL << 32)) / 44900000.0;
break;
case 0x03:
svga->clock = (cpuclock * (double) (1ULL << 32)) / 36000000.0;
break;
case 0x04:
svga->clock = (cpuclock * (double) (1ULL << 32)) / 57272000.0;
break;
case 0x05:
svga->clock = (cpuclock * (double) (1ULL << 32)) / 65000000.0;
break;
case 0x06:
svga->clock = (cpuclock * (double) (1ULL << 32)) / 50350000.0;
break;
case 0x07:
svga->clock = (cpuclock * (double) (1ULL << 32)) / 40000000.0;
break;
case 0x08:
svga->clock = (cpuclock * (double) (1ULL << 32)) / 88000000.0;
break;
case 0x09:
svga->clock = (cpuclock * (double) (1ULL << 32)) / 98000000.0;
break;
case 0x0a:
svga->clock = (cpuclock * (double) (1ULL << 32)) / 118800000.0;
break;
case 0x0b:
svga->clock = (cpuclock * (double) (1ULL << 32)) / 108000000.0;
break;
case 0x0c:
svga->clock = (cpuclock * (double) (1ULL << 32)) / 72000000.0;
break;
case 0x0d:
svga->clock = (cpuclock * (double) (1ULL << 32)) / 77000000.0;
break;
case 0x0e:
svga->clock = (cpuclock * (double) (1ULL << 32)) / 80000000.0;
break;
case 0x0f:
svga->clock = (cpuclock * (double) (1ULL << 32)) / 75000000.0;
break;
default:
break;
}
if (svga->gdcreg[0xf] & 0x08) {
svga->htotal <<= 1;
svga->hdisp <<= 1;
svga->hdisp_time <<= 1;
}
}
if ((tgui->oldctrl2 & 0x10) || (svga->crtc[0x2a] & 0x40)) {
switch (svga->bpp) {
case 8:
svga->render = svga_render_8bpp_highres;
if (svga->vdisp == 1022) {
if (svga->interlace)
svga->dispend++;
else
svga->dispend += 2;
}
if (tgui->type >= TGUI_9660) {
switch (svga->vdisp) {
case 1024:
case 1200:
svga->htotal <<= 1;
svga->hdisp <<= 1;
svga->hdisp_time <<= 1;
break;
default:
break;
}
#if OLD_CODE
if (svga->dispend == ((1024 >> 1) - 2))
svga->dispend += 2;
if (svga->dispend == (1024 >> 1))
svga->hdisp <<= 1;
else if ((svga->hdisp == (1600 >> 1)) && (svga->dispend == (1200 >> 1)) && svga->interlace)
svga->hdisp <<= 1;
else if (svga->hdisp == (1024 >> 1)) {
if (svga->interlace && (svga->dispend == (768 >> 1)))
svga->hdisp <<= 1;
else if (!svga->interlace && (svga->dispend == 768))
svga->hdisp <<= 1;
}
#endif
if (ger22upper & 0x80) {
svga->htotal <<= 1;
svga->hdisp <<= 1;
svga->hdisp_time <<= 1;
}
switch (svga->hdisp) {
case 640:
if (!ger22lower)
svga->rowoffset = 0x50;
break;
default:
break;
}
}
break;
case 15:
svga->render = svga_render_15bpp_highres;
if (tgui->type < TGUI_9440)
svga->hdisp >>= 1;
break;
case 16:
svga->render = svga_render_16bpp_highres;
if (tgui->type < TGUI_9440)
svga->hdisp >>= 1;
break;
case 24:
svga->render = svga_render_24bpp_highres;
if (tgui->type < TGUI_9440)
svga->hdisp = (svga->hdisp << 1) / 3;
break;
case 32:
if (svga->rowoffset == 0x100)
svga->rowoffset <<= 1;
svga->render = svga_render_32bpp_highres;
break;
default:
break;
}
}
}
static void
tgui_recalcmapping(tgui_t *tgui)
{
svga_t *svga = &tgui->svga;
if (tgui->type == TGUI_9400CXI) {
if (svga->gdcreg[0x10] & EXT_CTRL_LATCH_COPY) {
mem_mapping_set_handler(&tgui->linear_mapping,
tgui_ext_linear_read, NULL, NULL,
tgui_ext_linear_write, tgui_ext_linear_writew, tgui_ext_linear_writel);
mem_mapping_set_handler(&svga->mapping,
tgui_ext_read, NULL, NULL,
tgui_ext_write, tgui_ext_writew, tgui_ext_writel);
} else if (svga->gdcreg[0x10] & EXT_CTRL_MONO_EXPANSION) {
mem_mapping_set_handler(&tgui->linear_mapping,
svga_read_linear, svga_readw_linear, svga_readl_linear,
tgui_ext_linear_write, tgui_ext_linear_writew, tgui_ext_linear_writel);
mem_mapping_set_handler(&svga->mapping,
svga_read, svga_readw, svga_readl,
tgui_ext_write, tgui_ext_writew, tgui_ext_writel);
} else {
mem_mapping_set_handler(&tgui->linear_mapping,
svga_read_linear, svga_readw_linear, svga_readl_linear,
svga_write_linear, svga_writew_linear, svga_writel_linear);
mem_mapping_set_handler(&svga->mapping,
svga_read, svga_readw, svga_readl,
svga_write, svga_writew, svga_writel);
}
}
if (tgui->pci && !(tgui->pci_regs[PCI_REG_COMMAND] & PCI_COMMAND_MEM)) {
mem_mapping_disable(&svga->mapping);
mem_mapping_disable(&tgui->linear_mapping);
mem_mapping_disable(&tgui->accel_mapping);
mem_mapping_disable(&tgui->mmio_mapping);
return;
}
if (svga->crtc[0x21] & 0x20) {
mem_mapping_disable(&svga->mapping);
mem_mapping_set_addr(&tgui->linear_mapping, tgui->linear_base, tgui->linear_size);
if (tgui->type >= TGUI_9440) {
if ((svga->crtc[0x36] & 0x03) == 0x01)
mem_mapping_set_addr(&tgui->accel_mapping, 0xb4000, 0x4000);
else if ((svga->crtc[0x36] & 0x03) == 0x02)
mem_mapping_set_addr(&tgui->accel_mapping, 0xbc000, 0x4000);
else if ((svga->crtc[0x36] & 0x03) == 0x03)
mem_mapping_set_addr(&tgui->accel_mapping, tgui->ge_base, 0x4000);
} else {
switch (svga->gdcreg[6] & 0xC) {
case 0x0: /*128k at A0000*/
mem_mapping_set_addr(&svga->mapping, 0xa0000, 0x20000);
svga->banked_mask = 0xffff;
break;
case 0x4: /*64k at A0000*/
mem_mapping_set_addr(&svga->mapping, 0xa0000, 0x10000);
svga->banked_mask = 0xffff;
break;
case 0x8: /*32k at B0000*/
mem_mapping_set_addr(&svga->mapping, 0xb0000, 0x08000);
svga->banked_mask = 0x7fff;
break;
case 0xC: /*32k at B8000*/
mem_mapping_set_addr(&svga->mapping, 0xb8000, 0x08000);
svga->banked_mask = 0x7fff;
break;
default:
break;
}
}
} else {
mem_mapping_disable(&tgui->linear_mapping);
switch (svga->gdcreg[6] & 0xC) {
case 0x0: /*128k at A0000*/
mem_mapping_set_addr(&svga->mapping, 0xa0000, 0x20000);
svga->banked_mask = 0xffff;
break;
case 0x4: /*64k at A0000*/
mem_mapping_set_addr(&svga->mapping, 0xa0000, 0x10000);
svga->banked_mask = 0xffff;
break;
case 0x8: /*32k at B0000*/
mem_mapping_set_addr(&svga->mapping, 0xb0000, 0x08000);
svga->banked_mask = 0x7fff;
break;
case 0xC: /*32k at B8000*/
mem_mapping_set_addr(&svga->mapping, 0xb8000, 0x08000);
svga->banked_mask = 0x7fff;
break;
default:
break;
}
if (tgui->pci && tgui->linear_base) /*Assume that, with PCI, linear addressing is always enabled.*/
mem_mapping_set_addr(&tgui->linear_mapping, tgui->linear_base, tgui->linear_size);
if ((svga->crtc[0x36] & 0x03) == 0x01)
mem_mapping_set_addr(&tgui->accel_mapping, 0xb4000, 0x4000);
else if ((svga->crtc[0x36] & 0x03) == 0x02)
mem_mapping_set_addr(&tgui->accel_mapping, 0xbc000, 0x4000);
else if ((svga->crtc[0x36] & 0x03) == 0x03)
mem_mapping_set_addr(&tgui->accel_mapping, tgui->ge_base, 0x4000);
else
mem_mapping_disable(&tgui->accel_mapping);
}
if (tgui->type >= TGUI_9440) {
if ((tgui->mmio_base != 0x00000000) && (svga->crtc[0x39] & 0x01))
mem_mapping_set_addr(&tgui->mmio_mapping, tgui->mmio_base, 0x10000);
else
mem_mapping_disable(&tgui->mmio_mapping);
}
}
static void
tgui_hwcursor_draw(svga_t *svga, int displine)
{
uint32_t dat[2];
int offset = svga->hwcursor_latch.x - svga->hwcursor_latch.xoff;
int pitch = (svga->hwcursor_latch.cur_xsize == 64) ? 16 : 8;
if (svga->interlace && svga->hwcursor_oddeven)
svga->hwcursor_latch.addr += pitch;
dat[0] = (svga->vram[svga->hwcursor_latch.addr] << 24) | (svga->vram[svga->hwcursor_latch.addr + 1] << 16) | (svga->vram[svga->hwcursor_latch.addr + 2] << 8) | svga->vram[svga->hwcursor_latch.addr + 3];
dat[1] = (svga->vram[svga->hwcursor_latch.addr + 4] << 24) | (svga->vram[svga->hwcursor_latch.addr + 5] << 16) | (svga->vram[svga->hwcursor_latch.addr + 6] << 8) | svga->vram[svga->hwcursor_latch.addr + 7];
for (uint8_t xx = 0; xx < 32; xx++) {
if (svga->crtc[0x50] & 0x40) {
if (offset >= svga->hwcursor_latch.x) {
if (dat[0] & 0x80000000)
(buffer32->line[displine])[svga->x_add + offset] = (dat[1] & 0x80000000) ? 0xffffff : 0;
}
} else {
if (offset >= svga->hwcursor_latch.x) {
if (!(dat[0] & 0x80000000))
(buffer32->line[displine])[svga->x_add + offset] = (dat[1] & 0x80000000) ? 0xffffff : 0;
else if (dat[1] & 0x80000000)
(buffer32->line[displine])[svga->x_add + offset] ^= 0xffffff;
}
}
offset++;
dat[0] <<= 1;
dat[1] <<= 1;
}
svga->hwcursor_latch.addr += pitch;
if (svga->interlace && !svga->hwcursor_oddeven)
svga->hwcursor_latch.addr += pitch;
}
uint8_t
tgui_pci_read(UNUSED(int func), int addr, void *priv)
{
const tgui_t *tgui = (tgui_t *) priv;
switch (addr) {
case 0x00:
return 0x23; /*Trident*/
case 0x01:
return 0x10;
case 0x02:
return (tgui->type == TGUI_9440) ? 0x40 : 0x60; /*TGUI9440AGi or TGUI96x0XGi*/
case 0x03:
return (tgui->type == TGUI_9440) ? 0x94 : 0x96;
case PCI_REG_COMMAND:
return tgui->pci_regs[PCI_REG_COMMAND] | 0x80; /*Respond to IO and memory accesses*/
case 0x07:
return 1 << 1; /*Medium DEVSEL timing*/
case 0x08:
return 0; /*Revision ID*/
case 0x09:
return 0; /*Programming interface*/
case 0x0a:
return 0x01; /*Supports VGA interface, XGA compatible*/
case 0x0b:
return 0x03;
case 0x10:
return 0x00; /*Linear frame buffer address*/
case 0x11:
return 0x00;
case 0x12:
return tgui->linear_base >> 16;
case 0x13:
return tgui->linear_base >> 24;
case 0x14:
return 0x00; /*MMIO address*/
case 0x15:
return 0x00;
case 0x16:
return tgui->mmio_base >> 16;
case 0x17:
return tgui->mmio_base >> 24;
case 0x30:
return tgui->has_bios ? (tgui->pci_regs[0x30] & 0x01) : 0x00; /*BIOS ROM address*/
case 0x31:
return 0x00;
case 0x32:
return tgui->has_bios ? tgui->pci_regs[0x32] : 0x00;
case 0x33:
return tgui->has_bios ? tgui->pci_regs[0x33] : 0x00;
case 0x3c:
return tgui->int_line;
case 0x3d:
return PCI_INTA;
default:
break;
}
return 0;
}
void
tgui_pci_write(UNUSED(int func), int addr, uint8_t val, void *priv)
{
tgui_t *tgui = (tgui_t *) priv;
svga_t *svga = &tgui->svga;
switch (addr) {
case PCI_REG_COMMAND:
tgui->pci_regs[PCI_REG_COMMAND] = val & 0x23;
if (val & PCI_COMMAND_IO)
tgui_set_io(tgui);
else
tgui_remove_io(tgui);
tgui_recalcmapping(tgui);
break;
case 0x12:
if (tgui->type >= TGUI_9660)
tgui->linear_base = (tgui->linear_base & 0xff000000) | ((val & 0xc0) << 16);
else
tgui->linear_base = (tgui->linear_base & 0xff000000) | ((val & 0xe0) << 16);
tgui->linear_size = tgui->vram_size;
svga->decode_mask = tgui->vram_mask;
tgui_recalcmapping(tgui);
break;
case 0x13:
if (tgui->type >= TGUI_9660)
tgui->linear_base = (tgui->linear_base & 0xc00000) | (val << 24);
else
tgui->linear_base = (tgui->linear_base & 0xe00000) | (val << 24);
tgui->linear_size = tgui->vram_size;
svga->decode_mask = tgui->vram_mask;
tgui_recalcmapping(tgui);
break;
case 0x16:
if (tgui->type >= TGUI_9660)
tgui->mmio_base = (tgui->mmio_base & 0xff000000) | ((val & 0xc0) << 16);
else
tgui->mmio_base = (tgui->mmio_base & 0xff000000) | ((val & 0xe0) << 16);
tgui_recalcmapping(tgui);
break;
case 0x17:
if (tgui->type >= TGUI_9660)
tgui->mmio_base = (tgui->mmio_base & 0x00c00000) | (val << 24);
else
tgui->mmio_base = (tgui->mmio_base & 0x00e00000) | (val << 24);
tgui_recalcmapping(tgui);
break;
case 0x30:
case 0x32:
case 0x33:
if (tgui->has_bios) {
tgui->pci_regs[addr] = val;
if (tgui->pci_regs[0x30] & 0x01) {
uint32_t biosaddr = (tgui->pci_regs[0x32] << 16) | (tgui->pci_regs[0x33] << 24);
mem_mapping_set_addr(&tgui->bios_rom.mapping, biosaddr, 0x8000);
} else {
mem_mapping_disable(&tgui->bios_rom.mapping);
}
}
return;
case 0x3c:
tgui->int_line = val;
return;
default:
break;
}
}
static uint8_t
tgui_ext_linear_read(uint32_t addr, void *priv)
{
svga_t *svga = (svga_t *) priv;
tgui_t *tgui = (tgui_t *) svga->priv;
cycles -= svga->monitor->mon_video_timing_read_b;
addr &= svga->decode_mask;
if (addr >= svga->vram_max)
return 0xff;
addr &= svga->vram_mask;
addr &= ~0x0f;
addr = dword_remap(svga, addr);
for (int i = 0; i < 16; i++) {
tgui->copy_latch[i] = svga->vram[addr];
addr += ((i & 3) == 3) ? 0x0d : 0x01;
}
addr &= svga->vram_mask;
return svga->vram[addr];
}
static uint8_t
tgui_ext_read(uint32_t addr, void *priv)
{
svga_t *svga = (svga_t *) priv;
addr = (addr & svga->banked_mask) + svga->read_bank;
return tgui_ext_linear_read(addr, svga);
}
static void
tgui_ext_linear_write(uint32_t addr, uint8_t val, void *priv)
{
svga_t *svga = (svga_t *) priv;
const tgui_t *tgui = (tgui_t *) svga->priv;
int bpp = (svga->gdcreg[0x10] & EXT_CTRL_16BIT);
uint8_t fg[2] = { svga->gdcreg[0x14], svga->gdcreg[0x15] };
uint8_t bg[2] = { svga->gdcreg[0x11], svga->gdcreg[0x12] };
cycles -= svga->monitor->mon_video_timing_write_b;
addr &= svga->decode_mask;
if (addr >= svga->vram_max)
return;
addr &= svga->vram_mask;
addr &= (svga->gdcreg[0x10] & EXT_CTRL_LATCH_COPY) ? ~0x0f : ~0x07;
addr = dword_remap(svga, addr);
svga->changedvram[addr >> 12] = svga->monitor->mon_changeframecount;
if (svga->gdcreg[0x10] & EXT_CTRL_LATCH_COPY) {
for (int i = 0; i < 8; i++) {
if (val & (0x80 >> i))
svga->vram[addr] = tgui->copy_latch[i];
addr += ((i & 3) == 3) ? 0x0d : 0x01;
addr &= svga->vram_mask;
}
} else {
if (svga->gdcreg[0x10] & EXT_CTRL_MONO_TRANSPARENT) {
if (bpp) {
for (int i = 0; i < 8; i++) {
if (val & (0x80 >> i))
svga->vram[addr] = fg[i & 1];
addr += ((i & 3) == 3) ? 0x0d : 0x01;
addr &= svga->vram_mask;
}
} else {
for (int i = 0; i < 8; i++) {
if (val & (0x80 >> i))
svga->vram[addr] = fg[0];
addr += ((i & 3) == 3) ? 0x0d : 0x01;
addr &= svga->vram_mask;
}
}
} else {
if (bpp) {
for (int i = 0; i < 8; i++) {
if (val & (0x80 >> i)) {
if (svga->gdcreg[0x17] & (0x80 >> i))
svga->vram[addr] = fg[i & 1];
} else {
if (svga->gdcreg[0x17] & (0x80 >> i))
svga->vram[addr] = bg[i & 1];
}
addr += ((i & 3) == 3) ? 0x0d : 0x01;
addr &= svga->vram_mask;
}
} else {
for (int i = 0; i < 8; i++) {
if (val & (0x80 >> i)) {
if (svga->gdcreg[0x17] & (0x80 >> i))
svga->vram[addr] = fg[0];
} else {
if (svga->gdcreg[0x17] & (0x80 >> i))
svga->vram[addr] = bg[0];
}
addr += ((i & 3) == 3) ? 0x0d : 0x01;
addr &= svga->vram_mask;
}
}
}
}
}
static void
tgui_ext_linear_writew(uint32_t addr, uint16_t val, void *priv)
{
svga_t *svga = (svga_t *) priv;
const tgui_t *tgui = (tgui_t *) svga->priv;
int bpp = (svga->gdcreg[0x10] & EXT_CTRL_16BIT);
uint8_t fg[2] = { svga->gdcreg[0x14], svga->gdcreg[0x15] };
uint8_t bg[2] = { svga->gdcreg[0x11], svga->gdcreg[0x12] };
uint16_t mask = svga->gdcreg[0x18] | (svga->gdcreg[0x17] << 8);
cycles -= svga->monitor->mon_video_timing_write_w;
addr &= svga->decode_mask;
if (addr >= svga->vram_max)
return;
addr &= svga->vram_mask;
addr &= ~0x0f;
addr = dword_remap(svga, addr);
svga->changedvram[addr >> 12] = svga->monitor->mon_changeframecount;
val = (val >> 8) | (val << 8);
if (svga->gdcreg[0x10] & EXT_CTRL_LATCH_COPY) {
for (int i = 0; i < 16; i++) {
if (val & (0x8000 >> i))
svga->vram[addr] = tgui->copy_latch[i];
addr += ((i & 3) == 3) ? 0x0d : 0x01;
addr &= svga->vram_mask;
}
} else {
if (svga->gdcreg[0x10] & EXT_CTRL_MONO_TRANSPARENT) {
if (bpp) {
for (int i = 0; i < 16; i++) {
if (val & (0x8000 >> i))
svga->vram[addr] = fg[i & 1];
addr += ((i & 3) == 3) ? 0x0d : 0x01;
addr &= svga->vram_mask;
}
} else {
for (int i = 0; i < 16; i++) {
if (val & (0x8000 >> i))
svga->vram[addr] = fg[0];
addr += ((i & 3) == 3) ? 0x0d : 0x01;
addr &= svga->vram_mask;
}
}
} else {
if (bpp) {
for (int i = 0; i < 16; i++) {
if (val & (0x8000 >> i)) {
if (mask & (0x8000 >> i))
svga->vram[addr] = fg[i & 1];
} else {
if (mask & (0x8000 >> i))
svga->vram[addr] = bg[i & 1];
}
addr += ((i & 3) == 3) ? 0x0d : 0x01;
addr &= svga->vram_mask;
}
} else {
for (int i = 0; i < 16; i++) {
if (val & (0x8000 >> i)) {
if (mask & (0x8000 >> i))
svga->vram[addr] = fg[0];
} else {
if (mask & (0x8000 >> i))
svga->vram[addr] = bg[0];
}
addr += ((i & 3) == 3) ? 0x0d : 0x01;
addr &= svga->vram_mask;
}
}
}
}
}
static void
tgui_ext_linear_writel(uint32_t addr, uint32_t val, void *priv)
{
tgui_ext_linear_writew(addr, val, priv);
}
static void
tgui_ext_write(uint32_t addr, uint8_t val, void *priv)
{
svga_t *svga = (svga_t *) priv;
addr = (addr & svga->banked_mask) + svga->write_bank;
tgui_ext_linear_write(addr, val, svga);
}
static void
tgui_ext_writew(uint32_t addr, uint16_t val, void *priv)
{
svga_t *svga = (svga_t *) priv;
addr = (addr & svga->banked_mask) + svga->write_bank;
tgui_ext_linear_writew(addr, val, svga);
}
static void
tgui_ext_writel(uint32_t addr, uint32_t val, void *priv)
{
svga_t *svga = (svga_t *) priv;
addr = (addr & svga->banked_mask) + svga->write_bank;
tgui_ext_linear_writel(addr, val, svga);
}
enum {
TGUI_BITBLT = 1,
TGUI_SCANLINE = 3,
TGUI_BRESENHAMLINE = 4,
TGUI_SHORTVECTOR = 5,
TGUI_FASTLINE = 6
};
enum {
TGUI_SRCCPU = 0,
TGUI_SRCPAT = 0x02, /*Source is from pattern*/
TGUI_SRCDISP = 0x04, /*Source is from display*/
TGUI_PATMONO = 0x20, /*Pattern is monochrome and needs expansion*/
TGUI_SRCMONO = 0x40, /*Source is monochrome from CPU and needs expansion*/
TGUI_TRANSENA = 0x1000, /*Transparent (no draw when source == bg col)*/
TGUI_TRANSREV = 0x2000, /*Reverse fg/bg for transparent*/
TGUI_SOLIDFILL = 0x4000, /*Pattern set to foreground color*/
TGUI_STENCIL = 0x8000 /*Stencil*/
};
#define READ(addr, dat) \
if (tgui->accel.bpp == 0) \
dat = svga->vram[(addr) &tgui->vram_mask]; \
else if (tgui->accel.bpp == 1) \
dat = vram_w[(addr) & (tgui->vram_mask >> 1)]; \
else \
dat = vram_l[(addr) & (tgui->vram_mask >> 2)];
#define MIX() \
do { \
out = 0; \
for (c = 0; c < 32; c++) { \
d = (dst_dat & (1 << c)) ? 1 : 0; \
if (src_dat & (1 << c)) \
d |= 2; \
if (pat_dat & (1 << c)) \
d |= 4; \
if (tgui->accel.rop & (1 << d)) \
out |= (1 << c); \
} \
} while (0)
#define WRITE(addr, dat) \
if (tgui->accel.bpp == 0) { \
svga->vram[(addr) &tgui->vram_mask] = dat; \
svga->changedvram[((addr) & (tgui->vram_mask)) >> 12] = svga->monitor->mon_changeframecount; \
} else if (tgui->accel.bpp == 1) { \
vram_w[(addr) & (tgui->vram_mask >> 1)] = dat; \
svga->changedvram[((addr) & (tgui->vram_mask >> 1)) >> 11] = svga->monitor->mon_changeframecount; \
} else { \
vram_l[(addr) & (tgui->vram_mask >> 2)] = dat; \
svga->changedvram[((addr) & (tgui->vram_mask >> 2)) >> 10] = svga->monitor->mon_changeframecount; \
}
static void
tgui_accel_command(int count, uint32_t cpu_dat, tgui_t *tgui)
{
svga_t *svga = &tgui->svga;
const uint32_t *pattern_data;
int x;
int y;
int c;
int d;
uint32_t out;
uint32_t src_dat = 0;
uint32_t dst_dat;
uint32_t pat_dat;
int xdir = (tgui->accel.flags & 0x200) ? -1 : 1;
int ydir = (tgui->accel.flags & 0x100) ? -1 : 1;
uint32_t trans_col = (tgui->accel.flags & TGUI_TRANSREV) ? tgui->accel.fg_col : tgui->accel.bg_col;
uint16_t *vram_w = (uint16_t *) svga->vram;
uint32_t *vram_l = (uint32_t *) svga->vram;
if (tgui->accel.bpp == 0) {
trans_col &= 0xff;
} else if (tgui->accel.bpp == 1) {
trans_col &= 0xffff;
}
if ((count != -1) && !tgui->accel.x && (tgui->accel.flags & TGUI_SRCMONO)) {
count -= (tgui->accel.flags >> 24) & 7;
cpu_dat <<= (tgui->accel.flags >> 24) & 7;
}
if (count == -1)
tgui->accel.x = tgui->accel.y = 0;
if (tgui->accel.flags & TGUI_SOLIDFILL) {
for (y = 0; y < 8; y++) {
for (x = 0; x < 8; x++) {
tgui->accel.fill_pattern[(y * 8) + (7 - x)] = tgui->accel.fg_col;
}
}
pattern_data = tgui->accel.fill_pattern;
} else if (tgui->accel.flags & TGUI_PATMONO) {
for (y = 0; y < 8; y++) {
for (x = 0; x < 8; x++) {
tgui->accel.mono_pattern[(y * 8) + (7 - x)] = (tgui->accel.pattern[y] & (1 << x)) ? tgui->accel.fg_col : tgui->accel.bg_col;
}
}
pattern_data = tgui->accel.mono_pattern;
} else {
if (tgui->accel.bpp == 0) {
for (y = 0; y < 8; y++) {
for (x = 0; x < 8; x++) {
tgui->accel.pattern_8[(y * 8) + (7 - x)] = tgui->accel.pattern[x + y * 8];
}
}
pattern_data = tgui->accel.pattern_8;
} else if (tgui->accel.bpp == 1) {
for (y = 0; y < 8; y++) {
for (x = 0; x < 8; x++) {
tgui->accel.pattern_16[(y * 8) + (7 - x)] = tgui->accel.pattern[x * 2 + y * 16] | (tgui->accel.pattern[x * 2 + y * 16 + 1] << 8);
}
}
pattern_data = tgui->accel.pattern_16;
} else {
for (y = 0; y < 4; y++) {
for (x = 0; x < 8; x++) {
tgui->accel.pattern_32[(y * 8) + (7 - x)] = tgui->accel.pattern[x * 4 + y * 32] | (tgui->accel.pattern[x * 4 + y * 32 + 1] << 8) | (tgui->accel.pattern[x * 4 + y * 32 + 2] << 16) | (tgui->accel.pattern[x * 4 + y * 32 + 3] << 24);
tgui->accel.pattern_32[((y + 4) * 8) + (7 - x)] = tgui->accel.pattern[x * 4 + y * 32] | (tgui->accel.pattern[x * 4 + y * 32 + 1] << 8) | (tgui->accel.pattern[x * 4 + y * 32 + 2] << 16) | (tgui->accel.pattern[x * 4 + y * 32 + 3] << 24);
}
}
pattern_data = tgui->accel.pattern_32;
}
}
/* See Linux kernel drivers/video/tridentfb.c for the pitch */
tgui->accel.pitch = svga->rowoffset;
switch (svga->bpp) {
case 8:
case 24:
tgui->accel.pitch <<= 3;
break;
case 15:
case 16:
tgui->accel.pitch <<= 2;
break;
case 32:
tgui->accel.pitch <<= 1;
break;
default:
break;
}
#if 0
pclog("TGUI accel command = %x, ger22 = %04x, hdisp = %d, dispend = %d, vtotal = %d, rowoffset = %d, svgabpp = %d, interlace = %d, accelbpp = %d, pitch = %d.\n", tgui->accel.command, tgui->accel.ger22, svga->hdisp, svga->dispend, svga->vtotal, svga->rowoffset, svga->bpp, svga->interlace, tgui->accel.bpp, tgui->accel.pitch);
#endif
switch (tgui->accel.command) {
case TGUI_BITBLT:
if (count == -1) {
tgui->accel.src_old = tgui->accel.src_x + (tgui->accel.src_y * tgui->accel.pitch);
tgui->accel.src = tgui->accel.src_old;
tgui->accel.dst_old = tgui->accel.dst_x + (tgui->accel.dst_y * tgui->accel.pitch);
tgui->accel.dst = tgui->accel.dst_old;
tgui->accel.pat_x = tgui->accel.dst_x;
tgui->accel.pat_y = tgui->accel.dst_y;
tgui->accel.dx = tgui->accel.dst_x & 0xfff;
tgui->accel.dy = tgui->accel.dst_y & 0xfff;
tgui->accel.left = tgui->accel.src_x_clip & 0xfff;
tgui->accel.right = tgui->accel.dst_x_clip & 0xfff;
tgui->accel.top = tgui->accel.src_y_clip & 0xfff;
tgui->accel.bottom = tgui->accel.dst_y_clip & 0xfff;
if (tgui->accel.bpp == 1) {
tgui->accel.left >>= 1;
tgui->accel.right >>= 1;
} else if (tgui->accel.bpp == 3) {
tgui->accel.left >>= 2;
tgui->accel.right >>= 2;
}
}
switch (tgui->accel.flags & (TGUI_SRCMONO | TGUI_SRCDISP)) {
case TGUI_SRCCPU:
if (count == -1) {
if (svga->crtc[0x21] & 0x20)
tgui->write_blitter = 1;
if (tgui->accel.use_src)
return;
} else
count >>= 3;
while (count) {
if ((tgui->type == TGUI_9440) || ((tgui->type >= TGUI_9660) && tgui->accel.dx >= tgui->accel.left && tgui->accel.dx <= tgui->accel.right && tgui->accel.dy >= tgui->accel.top && tgui->accel.dy <= tgui->accel.bottom)) {
if (tgui->accel.bpp == 0) {
src_dat = cpu_dat >> 24;
cpu_dat <<= 8;
} else if (tgui->accel.bpp == 1) {
src_dat = (cpu_dat >> 24) | ((cpu_dat >> 8) & 0xff00);
cpu_dat <<= 16;
count--;
} else {
src_dat = (cpu_dat >> 24) | ((cpu_dat >> 8) & 0x0000ff00) | ((cpu_dat << 8) & 0x00ff0000);
cpu_dat <<= 16;
count -= 3;
}
READ(tgui->accel.dst, dst_dat);
pat_dat = pattern_data[((tgui->accel.pat_y & 7) * 8) + (tgui->accel.pat_x & 7)];
if (tgui->accel.bpp == 0)
pat_dat &= 0xff;
else if (tgui->accel.bpp == 1)
pat_dat &= 0xffff;
if ((((tgui->accel.flags & (TGUI_PATMONO | TGUI_TRANSENA)) == (TGUI_TRANSENA | TGUI_PATMONO)) && (pat_dat != trans_col)) || !(tgui->accel.flags & TGUI_PATMONO) || ((tgui->accel.flags & (TGUI_PATMONO | TGUI_TRANSENA)) == TGUI_PATMONO) || (tgui->accel.ger22 & 0x200)) {
MIX();
WRITE(tgui->accel.dst, out);
}
}
tgui->accel.src += xdir;
tgui->accel.dst += xdir;
tgui->accel.pat_x += xdir;
if (tgui->type >= TGUI_9660)
tgui->accel.dx += xdir;
tgui->accel.x++;
if (tgui->accel.x > tgui->accel.size_x) {
tgui->accel.x = 0;
tgui->accel.pat_x = tgui->accel.dst_x;
tgui->accel.pat_y += ydir;
if (tgui->type >= TGUI_9660) {
tgui->accel.dx = tgui->accel.dst_x & 0xfff;
tgui->accel.dy += ydir;
}
tgui->accel.src_old += (ydir * tgui->accel.pitch);
tgui->accel.dst_old += (ydir * tgui->accel.pitch);
tgui->accel.src = tgui->accel.src_old;
tgui->accel.dst = tgui->accel.dst_old;
tgui->accel.y++;
if (tgui->accel.y > tgui->accel.size_y) {
if (svga->crtc[0x21] & 0x20)
tgui->write_blitter = 0;
return;
}
if (tgui->accel.use_src)
return;
}
count--;
}
break;
case TGUI_SRCMONO | TGUI_SRCCPU:
if (count == -1) {
if (svga->crtc[0x21] & 0x20)
tgui->write_blitter = 1;
if (tgui->accel.use_src)
return;
}
while (count--) {
if ((tgui->type == TGUI_9440) || ((tgui->type >= TGUI_9660) && tgui->accel.dx >= tgui->accel.left && tgui->accel.dx <= tgui->accel.right && tgui->accel.dy >= tgui->accel.top && tgui->accel.dy <= tgui->accel.bottom)) {
src_dat = ((cpu_dat >> 31) ? tgui->accel.fg_col : tgui->accel.bg_col);
if (tgui->accel.bpp == 0)
src_dat &= 0xff;
else if (tgui->accel.bpp == 1)
src_dat &= 0xffff;
READ(tgui->accel.dst, dst_dat);
pat_dat = pattern_data[((tgui->accel.pat_y & 7) * 8) + (tgui->accel.pat_x & 7)];
if (tgui->accel.bpp == 0)
pat_dat &= 0xff;
else if (tgui->accel.bpp == 1)
pat_dat &= 0xffff;
if (!(tgui->accel.flags & TGUI_TRANSENA) || (src_dat != trans_col)) {
MIX();
WRITE(tgui->accel.dst, out);
}
}
cpu_dat <<= 1;
tgui->accel.src += xdir;
tgui->accel.dst += xdir;
tgui->accel.pat_x += xdir;
if (tgui->type >= TGUI_9660)
tgui->accel.dx += xdir;
tgui->accel.x++;
if (tgui->accel.x > tgui->accel.size_x) {
tgui->accel.x = 0;
tgui->accel.pat_x = tgui->accel.dst_x;
tgui->accel.pat_y += ydir;
if (tgui->type >= TGUI_9660) {
tgui->accel.dx = tgui->accel.dst_x & 0xfff;
tgui->accel.dy += ydir;
}
tgui->accel.src = tgui->accel.src_old = tgui->accel.src_old + (ydir * tgui->accel.pitch);
tgui->accel.dst = tgui->accel.dst_old = tgui->accel.dst_old + (ydir * tgui->accel.pitch);
tgui->accel.y++;
if (tgui->accel.y > tgui->accel.size_y) {
if (svga->crtc[0x21] & 0x20)
tgui->write_blitter = 0;
return;
}
if (tgui->accel.use_src)
return;
}
}
break;
default:
while (count--) {
READ(tgui->accel.src, src_dat);
READ(tgui->accel.dst, dst_dat);
pat_dat = pattern_data[((tgui->accel.pat_y & 7) * 8) + (tgui->accel.pat_x & 7)];
if (tgui->accel.bpp == 0)
pat_dat &= 0xff;
else if (tgui->accel.bpp == 1)
pat_dat &= 0xffff;
if (!(tgui->accel.flags & TGUI_TRANSENA) || (src_dat != trans_col)) {
MIX();
WRITE(tgui->accel.dst, out);
}
tgui->accel.src += xdir;
tgui->accel.dst += xdir;
tgui->accel.pat_x += xdir;
tgui->accel.x++;
if (tgui->accel.x > tgui->accel.size_x) {
tgui->accel.x = 0;
tgui->accel.y++;
tgui->accel.pat_x = tgui->accel.dst_x;
tgui->accel.pat_y += ydir;
tgui->accel.src = tgui->accel.src_old = tgui->accel.src_old + (ydir * tgui->accel.pitch);
tgui->accel.dst = tgui->accel.dst_old = tgui->accel.dst_old + (ydir * tgui->accel.pitch);
if (tgui->accel.y > tgui->accel.size_y)
return;
}
}
break;
}
break;
case TGUI_SCANLINE:
if (count == -1) {
tgui->accel.src_old = tgui->accel.src_x + (tgui->accel.src_y * tgui->accel.pitch);
tgui->accel.src = tgui->accel.src_old;
tgui->accel.dst_old = tgui->accel.dst_x + (tgui->accel.dst_y * tgui->accel.pitch);
tgui->accel.dst = tgui->accel.dst_old;
tgui->accel.pat_x = tgui->accel.dst_x;
tgui->accel.pat_y = tgui->accel.dst_y;
}
while (count--) {
READ(tgui->accel.src, src_dat);
READ(tgui->accel.dst, dst_dat);
pat_dat = pattern_data[((tgui->accel.pat_y & 7) * 8) + (tgui->accel.pat_x & 7)];
if (tgui->accel.bpp == 0)
pat_dat &= 0xff;
else if (tgui->accel.bpp == 1)
pat_dat &= 0xffff;
if (!(tgui->accel.flags & TGUI_TRANSENA) || (src_dat != trans_col)) {
MIX();
WRITE(tgui->accel.dst, out);
}
tgui->accel.src += xdir;
tgui->accel.dst += xdir;
tgui->accel.pat_x += xdir;
tgui->accel.x++;
if (tgui->accel.x > tgui->accel.size_x) {
tgui->accel.x = 0;
tgui->accel.pat_x = tgui->accel.dst_x;
tgui->accel.src = tgui->accel.src_old = tgui->accel.src_old + (ydir * tgui->accel.pitch);
tgui->accel.dst = tgui->accel.dst_old = tgui->accel.dst_old + (ydir * tgui->accel.pitch);
tgui->accel.pat_y += ydir;
return;
}
}
break;
case TGUI_BRESENHAMLINE:
if (count == -1) {
tgui->accel.dx = tgui->accel.dst_x & 0xfff;
tgui->accel.dy = tgui->accel.dst_y & 0xfff;
tgui->accel.y = tgui->accel.size_y;
tgui->accel.left = tgui->accel.src_x_clip & 0xfff;
tgui->accel.right = tgui->accel.dst_x_clip & 0xfff;
tgui->accel.top = tgui->accel.src_y_clip & 0xfff;
tgui->accel.bottom = tgui->accel.dst_y_clip & 0xfff;
if (tgui->accel.bpp == 1) {
tgui->accel.left >>= 1;
tgui->accel.right >>= 1;
} else if (tgui->accel.bpp == 3) {
tgui->accel.left >>= 2;
tgui->accel.right >>= 2;
}
}
while (count--) {
/*Note by TC1995: I suppose the x/y clipping max is always more than 0 in the TGUI 96xx, but the TGUI 9440 lacks clipping*/
if ((tgui->type == TGUI_9440) || ((tgui->type >= TGUI_9660) && ((tgui->accel.dx & 0xfff) >= tgui->accel.left) && ((tgui->accel.dx & 0xfff) <= tgui->accel.right) && ((tgui->accel.dy & 0xfff) >= tgui->accel.top) && ((tgui->accel.dy & 0xfff) <= tgui->accel.bottom))) {
READ(tgui->accel.dx + (tgui->accel.dy * tgui->accel.pitch), dst_dat);
pat_dat = tgui->accel.fg_col;
MIX();
WRITE(tgui->accel.dx + (tgui->accel.dy * tgui->accel.pitch), out);
}
if (!tgui->accel.y)
break;
if (tgui->accel.size_x >= 0) {
tgui->accel.size_x += tgui->accel.src_x;
/*Step minor axis*/
switch ((tgui->accel.flags >> 8) & 7) {
case 0:
case 2:
tgui->accel.dy++;
break;
case 1:
case 3:
tgui->accel.dy--;
break;
case 4:
case 5:
tgui->accel.dx++;
break;
case 6:
case 7:
tgui->accel.dx--;
break;
default:
break;
}
} else
tgui->accel.size_x += tgui->accel.src_y;
/*Step major axis*/
switch ((tgui->accel.flags >> 8) & 7) {
case 0:
case 1:
tgui->accel.dx++;
break;
case 2:
case 3:
tgui->accel.dx--;
break;
case 4:
case 6:
tgui->accel.dy++;
break;
case 5:
case 7:
tgui->accel.dy--;
break;
default:
break;
}
tgui->accel.y--;
tgui->accel.dx &= 0xfff;
tgui->accel.dy &= 0xfff;
}
break;
case TGUI_SHORTVECTOR:
if (count == -1) {
tgui->accel.dx = tgui->accel.dst_x & 0xfff;
tgui->accel.dy = tgui->accel.dst_y & 0xfff;
tgui->accel.y = tgui->accel.sv_size_y & 0xfff;
tgui->accel.left = tgui->accel.src_x_clip & 0xfff;
tgui->accel.right = tgui->accel.dst_x_clip & 0xfff;
tgui->accel.top = tgui->accel.src_y_clip & 0xfff;
tgui->accel.bottom = tgui->accel.dst_y_clip & 0xfff;
if (tgui->accel.bpp == 1) {
tgui->accel.left >>= 1;
tgui->accel.right >>= 1;
} else if (tgui->accel.bpp == 3) {
tgui->accel.left >>= 2;
tgui->accel.right >>= 2;
}
}
while (count--) {
/*Note by TC1995: I suppose the x/y clipping max is always more than 0 in the TGUI 96xx, but the TGUI 9440 lacks clipping*/
if ((tgui->type == TGUI_9440) || ((tgui->type >= TGUI_9660) && ((tgui->accel.dx & 0xfff) >= tgui->accel.left) && ((tgui->accel.dx & 0xfff) <= tgui->accel.right) && ((tgui->accel.dy & 0xfff) >= tgui->accel.top) && ((tgui->accel.dy & 0xfff) <= tgui->accel.bottom))) {
READ(tgui->accel.dx + (tgui->accel.dy * tgui->accel.pitch), dst_dat);
pat_dat = tgui->accel.fg_col;
MIX();
WRITE(tgui->accel.dx + (tgui->accel.dy * tgui->accel.pitch), out);
}
if (!tgui->accel.y)
break;
switch ((tgui->accel.sv_size_y >> 8) & 0xe0) {
case 0x00:
tgui->accel.dx++;
break;
case 0x20:
tgui->accel.dx++;
tgui->accel.dy--;
break;
case 0x40:
tgui->accel.dy--;
break;
case 0x60:
tgui->accel.dx--;
tgui->accel.dy--;
break;
case 0x80:
tgui->accel.dx--;
break;
case 0xa0:
tgui->accel.dx--;
tgui->accel.dy++;
break;
case 0xc0:
tgui->accel.dy++;
break;
case 0xe0:
tgui->accel.dx++;
tgui->accel.dy++;
break;
default:
break;
}
tgui->accel.y--;
tgui->accel.dx &= 0xfff;
tgui->accel.dy &= 0xfff;
}
break;
case TGUI_FASTLINE:
if (tgui->type < TGUI_9660)
break;
if (count == -1) {
tgui->accel.dx = tgui->accel.dst_x & 0xfff;
tgui->accel.dy = tgui->accel.dst_y & 0xfff;
tgui->accel.y = tgui->accel.size_y;
tgui->accel.left = tgui->accel.src_x_clip & 0xfff;
tgui->accel.right = tgui->accel.dst_x_clip & 0xfff;
tgui->accel.top = tgui->accel.src_y_clip & 0xfff;
tgui->accel.bottom = tgui->accel.dst_y_clip & 0xfff;
if (tgui->accel.bpp == 1) {
tgui->accel.left >>= 1;
tgui->accel.right >>= 1;
} else if (tgui->accel.bpp == 3) {
tgui->accel.left >>= 2;
tgui->accel.right >>= 2;
}
}
while (count--) {
/*Note by TC1995: I suppose the x/y clipping max is always more than 0 in the TGUI 96xx, but the TGUI 9440 lacks clipping*/
if ((tgui->type == TGUI_9440) || ((tgui->type >= TGUI_9660) && ((tgui->accel.dx & 0xfff) >= tgui->accel.left) && ((tgui->accel.dx & 0xfff) <= tgui->accel.right) && ((tgui->accel.dy & 0xfff) >= tgui->accel.top) && ((tgui->accel.dy & 0xfff) <= tgui->accel.bottom))) {
READ(tgui->accel.dx + (tgui->accel.dy * tgui->accel.pitch), dst_dat);
pat_dat = tgui->accel.fg_col;
MIX();
WRITE(tgui->accel.dx + (tgui->accel.dy * tgui->accel.pitch), out);
}
if (!tgui->accel.y)
break;
switch ((tgui->accel.size_y >> 8) & 0xe0) {
case 0x00:
tgui->accel.dx++;
break;
case 0x20:
tgui->accel.dx++;
tgui->accel.dy--;
break;
case 0x40:
tgui->accel.dy--;
break;
case 0x60:
tgui->accel.dx--;
tgui->accel.dy--;
break;
case 0x80:
tgui->accel.dx--;
break;
case 0xa0:
tgui->accel.dx--;
tgui->accel.dy++;
break;
case 0xc0:
tgui->accel.dy++;
break;
case 0xe0:
tgui->accel.dx++;
tgui->accel.dy++;
break;
default:
break;
}
tgui->accel.y--;
tgui->accel.dx &= 0xfff;
tgui->accel.dy &= 0xfff;
}
break;
default:
break;
}
}
static void
tgui_accel_out(uint16_t addr, uint8_t val, void *priv)
{
tgui_t *tgui = (tgui_t *) priv;
svga_t *svga = &tgui->svga;
switch (addr) {
case 0x2122:
tgui->accel.ger22 = (tgui->accel.ger22 & 0xff00) | val;
switch (svga->bpp) {
case 8:
case 24:
tgui->accel.bpp = 0;
break;
case 15:
case 16:
tgui->accel.bpp = 1;
break;
case 32:
tgui->accel.bpp = 3;
break;
default:
break;
}
break;
case 0x2123:
tgui->accel.ger22 = (tgui->accel.ger22 & 0xff) | (val << 8);
//pclog("Pitch IO23: val = %02x, rowoffset = %x.\n", tgui->accel.ger22, svga->crtc[0x13]);
switch (svga->bpp) {
case 8:
case 24:
tgui->accel.bpp = 0;
break;
case 15:
case 16:
tgui->accel.bpp = 1;
break;
case 32:
tgui->accel.bpp = 3;
break;
}
break;
case 0x2124: /*Command*/
tgui->accel.command = val;
tgui_accel_command(-1, 0, tgui);
break;
case 0x2127: /*ROP*/
tgui->accel.rop = val;
tgui->accel.use_src = (val & 0x33) ^ ((val >> 2) & 0x33);
break;
case 0x2128: /*Flags*/
tgui->accel.flags = (tgui->accel.flags & 0xffffff00) | val;
break;
case 0x2129: /*Flags*/
tgui->accel.flags = (tgui->accel.flags & 0xffff00ff) | (val << 8);
break;
case 0x212a: /*Flags*/
tgui->accel.flags = (tgui->accel.flags & 0xff00ffff) | (val << 16);
break;
case 0x212b: /*Flags*/
tgui->accel.flags = (tgui->accel.flags & 0x0000ffff) | (val << 24);
break;
case 0x212c: /*Foreground colour*/
case 0x2178:
tgui->accel.fg_col = (tgui->accel.fg_col & 0xffffff00) | val;
break;
case 0x212d: /*Foreground colour*/
case 0x2179:
tgui->accel.fg_col = (tgui->accel.fg_col & 0xffff00ff) | (val << 8);
break;
case 0x212e: /*Foreground colour*/
case 0x217a:
tgui->accel.fg_col = (tgui->accel.fg_col & 0xff00ffff) | (val << 16);
break;
case 0x212f: /*Foreground colour*/
case 0x217b:
tgui->accel.fg_col = (tgui->accel.fg_col & 0x00ffffff) | (val << 24);
break;
case 0x2130: /*Background colour*/
case 0x217c:
tgui->accel.bg_col = (tgui->accel.bg_col & 0xffffff00) | val;
break;
case 0x2131: /*Background colour*/
case 0x217d:
tgui->accel.bg_col = (tgui->accel.bg_col & 0xffff00ff) | (val << 8);
break;
case 0x2132: /*Background colour*/
case 0x217e:
tgui->accel.bg_col = (tgui->accel.bg_col & 0xff00ffff) | (val << 16);
break;
case 0x2133: /*Background colour*/
case 0x217f:
tgui->accel.bg_col = (tgui->accel.bg_col & 0x00ffffff) | (val << 24);
break;
case 0x2134: /*Pattern location*/
tgui->accel.patloc = (tgui->accel.patloc & 0xff00) | val;
break;
case 0x2135: /*Pattern location*/
tgui->accel.patloc = (tgui->accel.patloc & 0xff) | (val << 8);
break;
case 0x2138: /*Dest X*/
tgui->accel.dst_x = (tgui->accel.dst_x & 0xff00) | val;
break;
case 0x2139: /*Dest X*/
tgui->accel.dst_x = (tgui->accel.dst_x & 0xff) | (val << 8);
break;
case 0x213a: /*Dest Y*/
tgui->accel.dst_y = (tgui->accel.dst_y & 0xff00) | val;
break;
case 0x213b: /*Dest Y*/
tgui->accel.dst_y = (tgui->accel.dst_y & 0xff) | (val << 8);
break;
case 0x213c: /*Src X, Diagonal Step Constant*/
tgui->accel.src_x = (tgui->accel.src_x & 0x3f00) | val;
break;
case 0x213d: /*Src X, Diagonal Step Constant*/
tgui->accel.src_x = (tgui->accel.src_x & 0xff) | ((val & 0x3f) << 8);
if (val & 0x20)
tgui->accel.src_x |= ~0x3fff;
break;
case 0x213e: /*Src Y, Axial Step Constant*/
tgui->accel.src_y = (tgui->accel.src_y & 0x3f00) | val;
break;
case 0x213f: /*Src Y, Axial Step Constant*/
tgui->accel.src_y = (tgui->accel.src_y & 0xff) | ((val & 0x3f) << 8);
if (val & 0x20)
tgui->accel.src_y |= ~0x3fff;
break;
case 0x2140: /*Size X, Line Error Term*/
tgui->accel.size_x = (tgui->accel.size_x & 0x3f00) | val;
break;
case 0x2141: /*Size X, Line Error Term*/
tgui->accel.size_x = (tgui->accel.size_x & 0xff) | ((val & 0x3f) << 8);
if (val & 0x20)
tgui->accel.size_x |= ~0x1fff;
break;
case 0x2142: /*Size Y, Major Axis Pixel Count*/
tgui->accel.size_y = (tgui->accel.size_y & 0xf00) | val;
tgui->accel.sv_size_y = (tgui->accel.sv_size_y & 0xff00) | val;
break;
case 0x2143: /*Size Y, Major Axis Pixel Count*/
tgui->accel.size_y = (tgui->accel.size_y & 0xff) | ((val & 0x0f) << 8);
tgui->accel.sv_size_y = (tgui->accel.sv_size_y & 0xff) | (val << 8);
break;
case 0x2144: /*Style*/
tgui->accel.style = (tgui->accel.style & 0xffffff00) | val;
break;
case 0x2145: /*Style*/
tgui->accel.style = (tgui->accel.style & 0xffff00ff) | (val << 8);
break;
case 0x2146: /*Style*/
tgui->accel.style = (tgui->accel.style & 0xff00ffff) | (val << 16);
break;
case 0x2147: /*Style*/
tgui->accel.style = (tgui->accel.style & 0x00ffffff) | (val << 24);
break;
case 0x2148: /*Clip Src X*/
tgui->accel.src_x_clip = (tgui->accel.src_x_clip & 0xff00) | val;
break;
case 0x2149: /*Clip Src X*/
tgui->accel.src_x_clip = (tgui->accel.src_x_clip & 0xff) | (val << 8);
break;
case 0x214a: /*Clip Src Y*/
tgui->accel.src_y_clip = (tgui->accel.src_y_clip & 0xff00) | val;
break;
case 0x214b: /*Clip Src Y*/
tgui->accel.src_y_clip = (tgui->accel.src_y_clip & 0xff) | (val << 8);
break;
case 0x214c: /*Clip Dest X*/
tgui->accel.dst_x_clip = (tgui->accel.dst_x_clip & 0xff00) | val;
break;
case 0x214d: /*Clip Dest X*/
tgui->accel.dst_x_clip = (tgui->accel.dst_x_clip & 0xff) | (val << 8);
break;
case 0x214e: /*Clip Dest Y*/
tgui->accel.dst_y_clip = (tgui->accel.dst_y_clip & 0xff00) | val;
break;
case 0x214f: /*Clip Dest Y*/
tgui->accel.dst_y_clip = (tgui->accel.dst_y_clip & 0xff) | (val << 8);
break;
case 0x2168: /*CKey*/
tgui->accel.ckey = (tgui->accel.ckey & 0xffffff00) | val;
break;
case 0x2169: /*CKey*/
tgui->accel.ckey = (tgui->accel.ckey & 0xffff00ff) | (val << 8);
break;
case 0x216a: /*CKey*/
tgui->accel.ckey = (tgui->accel.ckey & 0xff00ffff) | (val << 16);
break;
case 0x216b: /*CKey*/
tgui->accel.ckey = (tgui->accel.ckey & 0x00ffffff) | (val << 24);
break;
case 0x2180:
case 0x2181:
case 0x2182:
case 0x2183:
case 0x2184:
case 0x2185:
case 0x2186:
case 0x2187:
case 0x2188:
case 0x2189:
case 0x218a:
case 0x218b:
case 0x218c:
case 0x218d:
case 0x218e:
case 0x218f:
case 0x2190:
case 0x2191:
case 0x2192:
case 0x2193:
case 0x2194:
case 0x2195:
case 0x2196:
case 0x2197:
case 0x2198:
case 0x2199:
case 0x219a:
case 0x219b:
case 0x219c:
case 0x219d:
case 0x219e:
case 0x219f:
case 0x21a0:
case 0x21a1:
case 0x21a2:
case 0x21a3:
case 0x21a4:
case 0x21a5:
case 0x21a6:
case 0x21a7:
case 0x21a8:
case 0x21a9:
case 0x21aa:
case 0x21ab:
case 0x21ac:
case 0x21ad:
case 0x21ae:
case 0x21af:
case 0x21b0:
case 0x21b1:
case 0x21b2:
case 0x21b3:
case 0x21b4:
case 0x21b5:
case 0x21b6:
case 0x21b7:
case 0x21b8:
case 0x21b9:
case 0x21ba:
case 0x21bb:
case 0x21bc:
case 0x21bd:
case 0x21be:
case 0x21bf:
case 0x21c0:
case 0x21c1:
case 0x21c2:
case 0x21c3:
case 0x21c4:
case 0x21c5:
case 0x21c6:
case 0x21c7:
case 0x21c8:
case 0x21c9:
case 0x21ca:
case 0x21cb:
case 0x21cc:
case 0x21cd:
case 0x21ce:
case 0x21cf:
case 0x21d0:
case 0x21d1:
case 0x21d2:
case 0x21d3:
case 0x21d4:
case 0x21d5:
case 0x21d6:
case 0x21d7:
case 0x21d8:
case 0x21d9:
case 0x21da:
case 0x21db:
case 0x21dc:
case 0x21dd:
case 0x21de:
case 0x21df:
case 0x21e0:
case 0x21e1:
case 0x21e2:
case 0x21e3:
case 0x21e4:
case 0x21e5:
case 0x21e6:
case 0x21e7:
case 0x21e8:
case 0x21e9:
case 0x21ea:
case 0x21eb:
case 0x21ec:
case 0x21ed:
case 0x21ee:
case 0x21ef:
case 0x21f0:
case 0x21f1:
case 0x21f2:
case 0x21f3:
case 0x21f4:
case 0x21f5:
case 0x21f6:
case 0x21f7:
case 0x21f8:
case 0x21f9:
case 0x21fa:
case 0x21fb:
case 0x21fc:
case 0x21fd:
case 0x21fe:
case 0x21ff:
tgui->accel.pattern[addr & 0x7f] = val;
break;
default:
break;
}
}
static void
tgui_accel_out_w(uint16_t addr, uint16_t val, void *priv)
{
tgui_t *tgui = (tgui_t *) priv;
tgui_accel_out(addr, val, tgui);
tgui_accel_out(addr + 1, val >> 8, tgui);
}
static void
tgui_accel_out_l(uint16_t addr, uint32_t val, void *priv)
{
tgui_t *tgui = (tgui_t *) priv;
switch (addr) {
case 0x2124: /*Long version of Command and ROP together*/
tgui->accel.command = val & 0xff;
tgui->accel.rop = val >> 24;
tgui->accel.use_src = (tgui->accel.rop & 0x33) ^ ((tgui->accel.rop >> 2) & 0x33);
tgui_accel_command(-1, 0, tgui);
break;
default:
tgui_accel_out(addr, val, tgui);
tgui_accel_out(addr + 1, val >> 8, tgui);
tgui_accel_out(addr + 2, val >> 16, tgui);
tgui_accel_out(addr + 3, val >> 24, tgui);
break;
}
}
static uint8_t
tgui_accel_in(uint16_t addr, void *priv)
{
const tgui_t *tgui = (tgui_t *) priv;
switch (addr) {
case 0x2120: /*Status*/
return 0;
case 0x2122:
return tgui->accel.ger22 & 0xff;
case 0x2123:
return tgui->accel.ger22 >> 8;
case 0x2127: /*ROP*/
return tgui->accel.rop;
case 0x2128: /*Flags*/
return tgui->accel.flags & 0xff;
case 0x2129: /*Flags*/
return tgui->accel.flags >> 8;
case 0x212a: /*Flags*/
return tgui->accel.flags >> 16;
case 0x212b:
return tgui->accel.flags >> 24;
case 0x212c: /*Foreground colour*/
case 0x2178:
return tgui->accel.fg_col & 0xff;
case 0x212d: /*Foreground colour*/
case 0x2179:
return tgui->accel.fg_col >> 8;
case 0x212e: /*Foreground colour*/
case 0x217a:
return tgui->accel.fg_col >> 16;
case 0x212f: /*Foreground colour*/
case 0x217b:
return tgui->accel.fg_col >> 24;
case 0x2130: /*Background colour*/
case 0x217c:
return tgui->accel.bg_col & 0xff;
case 0x2131: /*Background colour*/
case 0x217d:
return tgui->accel.bg_col >> 8;
case 0x2132: /*Background colour*/
case 0x217e:
return tgui->accel.bg_col >> 16;
case 0x2133: /*Background colour*/
case 0x217f:
return tgui->accel.bg_col >> 24;
case 0x2134: /*Pattern location*/
return tgui->accel.patloc & 0xff;
case 0x2135: /*Pattern location*/
return tgui->accel.patloc >> 8;
case 0x2138: /*Dest X*/
return tgui->accel.dst_x & 0xff;
case 0x2139: /*Dest X*/
return tgui->accel.dst_x >> 8;
case 0x213a: /*Dest Y*/
return tgui->accel.dst_y & 0xff;
case 0x213b: /*Dest Y*/
return tgui->accel.dst_y >> 8;
case 0x213c: /*Src X*/
return tgui->accel.src_x & 0xff;
case 0x213d: /*Src X*/
return tgui->accel.src_x >> 8;
case 0x213e: /*Src Y*/
return tgui->accel.src_y & 0xff;
case 0x213f: /*Src Y*/
return tgui->accel.src_y >> 8;
case 0x2140: /*Size X*/
return tgui->accel.size_x & 0xff;
case 0x2141: /*Size X*/
return tgui->accel.size_x >> 8;
case 0x2142: /*Size Y*/
return tgui->accel.size_y & 0xff;
case 0x2143: /*Size Y*/
return tgui->accel.size_y >> 8;
case 0x2144: /*Style*/
return tgui->accel.style & 0xff;
case 0x2145: /*Style*/
return tgui->accel.style >> 8;
case 0x2146: /*Style*/
return tgui->accel.style >> 16;
case 0x2147: /*Style*/
return tgui->accel.style >> 24;
case 0x2148: /*Clip Src X*/
return tgui->accel.src_x_clip & 0xff;
case 0x2149: /*Clip Src X*/
return tgui->accel.src_x_clip >> 8;
case 0x214a: /*Clip Src Y*/
return tgui->accel.src_y_clip & 0xff;
case 0x214b: /*Clip Src Y*/
return tgui->accel.src_y_clip >> 8;
case 0x214c: /*Clip Dest X*/
return tgui->accel.dst_x_clip & 0xff;
case 0x214d: /*Clip Dest X*/
return tgui->accel.dst_x_clip >> 8;
case 0x214e: /*Clip Dest Y*/
return tgui->accel.dst_y_clip & 0xff;
case 0x214f: /*Clip Dest Y*/
return tgui->accel.dst_y_clip >> 8;
case 0x2168: /*CKey*/
return tgui->accel.ckey & 0xff;
case 0x2169: /*CKey*/
return tgui->accel.ckey >> 8;
case 0x216a: /*CKey*/
return tgui->accel.ckey >> 16;
case 0x216b: /*CKey*/
return tgui->accel.ckey >> 24;
case 0x2180:
case 0x2181:
case 0x2182:
case 0x2183:
case 0x2184:
case 0x2185:
case 0x2186:
case 0x2187:
case 0x2188:
case 0x2189:
case 0x218a:
case 0x218b:
case 0x218c:
case 0x218d:
case 0x218e:
case 0x218f:
case 0x2190:
case 0x2191:
case 0x2192:
case 0x2193:
case 0x2194:
case 0x2195:
case 0x2196:
case 0x2197:
case 0x2198:
case 0x2199:
case 0x219a:
case 0x219b:
case 0x219c:
case 0x219d:
case 0x219e:
case 0x219f:
case 0x21a0:
case 0x21a1:
case 0x21a2:
case 0x21a3:
case 0x21a4:
case 0x21a5:
case 0x21a6:
case 0x21a7:
case 0x21a8:
case 0x21a9:
case 0x21aa:
case 0x21ab:
case 0x21ac:
case 0x21ad:
case 0x21ae:
case 0x21af:
case 0x21b0:
case 0x21b1:
case 0x21b2:
case 0x21b3:
case 0x21b4:
case 0x21b5:
case 0x21b6:
case 0x21b7:
case 0x21b8:
case 0x21b9:
case 0x21ba:
case 0x21bb:
case 0x21bc:
case 0x21bd:
case 0x21be:
case 0x21bf:
case 0x21c0:
case 0x21c1:
case 0x21c2:
case 0x21c3:
case 0x21c4:
case 0x21c5:
case 0x21c6:
case 0x21c7:
case 0x21c8:
case 0x21c9:
case 0x21ca:
case 0x21cb:
case 0x21cc:
case 0x21cd:
case 0x21ce:
case 0x21cf:
case 0x21d0:
case 0x21d1:
case 0x21d2:
case 0x21d3:
case 0x21d4:
case 0x21d5:
case 0x21d6:
case 0x21d7:
case 0x21d8:
case 0x21d9:
case 0x21da:
case 0x21db:
case 0x21dc:
case 0x21dd:
case 0x21de:
case 0x21df:
case 0x21e0:
case 0x21e1:
case 0x21e2:
case 0x21e3:
case 0x21e4:
case 0x21e5:
case 0x21e6:
case 0x21e7:
case 0x21e8:
case 0x21e9:
case 0x21ea:
case 0x21eb:
case 0x21ec:
case 0x21ed:
case 0x21ee:
case 0x21ef:
case 0x21f0:
case 0x21f1:
case 0x21f2:
case 0x21f3:
case 0x21f4:
case 0x21f5:
case 0x21f6:
case 0x21f7:
case 0x21f8:
case 0x21f9:
case 0x21fa:
case 0x21fb:
case 0x21fc:
case 0x21fd:
case 0x21fe:
case 0x21ff:
return tgui->accel.pattern[addr & 0x7f];
default:
break;
}
return 0;
}
static uint16_t
tgui_accel_in_w(uint16_t addr, void *priv)
{
tgui_t *tgui = (tgui_t *) priv;
return tgui_accel_in(addr, tgui) | (tgui_accel_in(addr + 1, tgui) << 8);
}
static uint32_t
tgui_accel_in_l(uint16_t addr, void *priv)
{
tgui_t *tgui = (tgui_t *) priv;
return tgui_accel_in_w(addr, tgui) | (tgui_accel_in_w(addr + 2, tgui) << 16);
}
static void
tgui_accel_write(uint32_t addr, uint8_t val, void *priv)
{
tgui_t *tgui = (tgui_t *) priv;
svga_t *svga = &tgui->svga;
if ((svga->crtc[0x36] & 0x03) == 0x02) {
if ((addr & ~0xff) != 0xbff00)
return;
} else if ((svga->crtc[0x36] & 0x03) == 0x01) {
if ((addr & ~0xff) != 0xb7f00)
return;
}
tgui_accel_out((addr & 0xff) + 0x2100, val, tgui);
}
static void
tgui_accel_write_w(uint32_t addr, uint16_t val, void *priv)
{
tgui_t *tgui = (tgui_t *) priv;
tgui_accel_write(addr, val, tgui);
tgui_accel_write(addr + 1, val >> 8, tgui);
}
static void
tgui_accel_write_l(uint32_t addr, uint32_t val, void *priv)
{
tgui_t *tgui = (tgui_t *) priv;
const svga_t *svga = &tgui->svga;
switch (addr & 0xff) {
case 0x24: /*Long version of Command and ROP together*/
if ((svga->crtc[0x36] & 0x03) == 0x02) {
if ((addr & ~0xff) != 0xbff00)
return;
} else if ((svga->crtc[0x36] & 0x03) == 0x01) {
if ((addr & ~0xff) != 0xb7f00)
return;
}
tgui->accel.command = val & 0xff;
tgui->accel.rop = val >> 24;
tgui->accel.use_src = ((val >> 24) & 0x33) ^ (((val >> 24) >> 2) & 0x33);
tgui_accel_command(-1, 0, tgui);
break;
default:
tgui_accel_write_w(addr, val, tgui);
tgui_accel_write_w(addr + 2, val >> 16, tgui);
break;
}
}
static uint8_t
tgui_accel_read(uint32_t addr, void *priv)
{
const tgui_t *tgui = (tgui_t *) priv;
const svga_t *svga = &tgui->svga;
if ((svga->crtc[0x36] & 0x03) == 0x02) {
if ((addr & ~0xff) != 0xbff00)
return 0xff;
} else if ((svga->crtc[0x36] & 0x03) == 0x01) {
if ((addr & ~0xff) != 0xb7f00)
return 0xff;
}
switch (addr & 0xff) {
case 0x20: /*Status*/
return 0;
case 0x22:
return tgui->accel.ger22 & 0xff;
case 0x23:
return tgui->accel.ger22 >> 8;
case 0x27: /*ROP*/
return tgui->accel.rop;
case 0x28: /*Flags*/
return tgui->accel.flags & 0xff;
case 0x29: /*Flags*/
return tgui->accel.flags >> 8;
case 0x2a: /*Flags*/
return tgui->accel.flags >> 16;
case 0x2b:
return tgui->accel.flags >> 24;
case 0x2c: /*Foreground colour*/
case 0x78:
return tgui->accel.fg_col & 0xff;
case 0x2d: /*Foreground colour*/
case 0x79:
return tgui->accel.fg_col >> 8;
case 0x2e: /*Foreground colour*/
case 0x7a:
return tgui->accel.fg_col >> 16;
case 0x2f: /*Foreground colour*/
case 0x7b:
return tgui->accel.fg_col >> 24;
case 0x30: /*Background colour*/
case 0x7c:
return tgui->accel.bg_col & 0xff;
case 0x31: /*Background colour*/
case 0x7d:
return tgui->accel.bg_col >> 8;
case 0x32: /*Background colour*/
case 0x7e:
return tgui->accel.bg_col >> 16;
case 0x33: /*Background colour*/
case 0x7f:
return tgui->accel.bg_col >> 24;
case 0x34: /*Pattern location*/
return tgui->accel.patloc & 0xff;
case 0x35: /*Pattern location*/
return tgui->accel.patloc >> 8;
case 0x38: /*Dest X*/
return tgui->accel.dst_x & 0xff;
case 0x39: /*Dest X*/
return tgui->accel.dst_x >> 8;
case 0x3a: /*Dest Y*/
return tgui->accel.dst_y & 0xff;
case 0x3b: /*Dest Y*/
return tgui->accel.dst_y >> 8;
case 0x3c: /*Src X*/
return tgui->accel.src_x & 0xff;
case 0x3d: /*Src X*/
return tgui->accel.src_x >> 8;
case 0x3e: /*Src Y*/
return tgui->accel.src_y & 0xff;
case 0x3f: /*Src Y*/
return tgui->accel.src_y >> 8;
case 0x40: /*Size X*/
return tgui->accel.size_x & 0xff;
case 0x41: /*Size X*/
return tgui->accel.size_x >> 8;
case 0x42: /*Size Y*/
return tgui->accel.size_y & 0xff;
case 0x43: /*Size Y*/
return tgui->accel.size_y >> 8;
case 0x44: /*Style*/
return tgui->accel.style & 0xff;
case 0x45: /*Style*/
return tgui->accel.style >> 8;
case 0x46: /*Style*/
return tgui->accel.style >> 16;
case 0x47: /*Style*/
return tgui->accel.style >> 24;
case 0x48: /*Clip Src X*/
return tgui->accel.src_x_clip & 0xff;
case 0x49: /*Clip Src X*/
return tgui->accel.src_x_clip >> 8;
case 0x4a: /*Clip Src Y*/
return tgui->accel.src_y_clip & 0xff;
case 0x4b: /*Clip Src Y*/
return tgui->accel.src_y_clip >> 8;
case 0x4c: /*Clip Dest X*/
return tgui->accel.dst_x_clip & 0xff;
case 0x4d: /*Clip Dest X*/
return tgui->accel.dst_x_clip >> 8;
case 0x4e: /*Clip Dest Y*/
return tgui->accel.dst_y_clip & 0xff;
case 0x4f: /*Clip Dest Y*/
return tgui->accel.dst_y_clip >> 8;
case 0x68: /*CKey*/
return tgui->accel.ckey & 0xff;
case 0x69: /*CKey*/
return tgui->accel.ckey >> 8;
case 0x6a: /*CKey*/
return tgui->accel.ckey >> 16;
case 0x6b: /*CKey*/
return tgui->accel.ckey >> 24;
case 0x80:
case 0x81:
case 0x82:
case 0x83:
case 0x84:
case 0x85:
case 0x86:
case 0x87:
case 0x88:
case 0x89:
case 0x8a:
case 0x8b:
case 0x8c:
case 0x8d:
case 0x8e:
case 0x8f:
case 0x90:
case 0x91:
case 0x92:
case 0x93:
case 0x94:
case 0x95:
case 0x96:
case 0x97:
case 0x98:
case 0x99:
case 0x9a:
case 0x9b:
case 0x9c:
case 0x9d:
case 0x9e:
case 0x9f:
case 0xa0:
case 0xa1:
case 0xa2:
case 0xa3:
case 0xa4:
case 0xa5:
case 0xa6:
case 0xa7:
case 0xa8:
case 0xa9:
case 0xaa:
case 0xab:
case 0xac:
case 0xad:
case 0xae:
case 0xaf:
case 0xb0:
case 0xb1:
case 0xb2:
case 0xb3:
case 0xb4:
case 0xb5:
case 0xb6:
case 0xb7:
case 0xb8:
case 0xb9:
case 0xba:
case 0xbb:
case 0xbc:
case 0xbd:
case 0xbe:
case 0xbf:
case 0xc0:
case 0xc1:
case 0xc2:
case 0xc3:
case 0xc4:
case 0xc5:
case 0xc6:
case 0xc7:
case 0xc8:
case 0xc9:
case 0xca:
case 0xcb:
case 0xcc:
case 0xcd:
case 0xce:
case 0xcf:
case 0xd0:
case 0xd1:
case 0xd2:
case 0xd3:
case 0xd4:
case 0xd5:
case 0xd6:
case 0xd7:
case 0xd8:
case 0xd9:
case 0xda:
case 0xdb:
case 0xdc:
case 0xdd:
case 0xde:
case 0xdf:
case 0xe0:
case 0xe1:
case 0xe2:
case 0xe3:
case 0xe4:
case 0xe5:
case 0xe6:
case 0xe7:
case 0xe8:
case 0xe9:
case 0xea:
case 0xeb:
case 0xec:
case 0xed:
case 0xee:
case 0xef:
case 0xf0:
case 0xf1:
case 0xf2:
case 0xf3:
case 0xf4:
case 0xf5:
case 0xf6:
case 0xf7:
case 0xf8:
case 0xf9:
case 0xfa:
case 0xfb:
case 0xfc:
case 0xfd:
case 0xfe:
case 0xff:
return tgui->accel.pattern[addr & 0x7f];
default:
break;
}
return 0xff;
}
static uint16_t
tgui_accel_read_w(uint32_t addr, void *priv)
{
tgui_t *tgui = (tgui_t *) priv;
return tgui_accel_read(addr, tgui) | (tgui_accel_read(addr + 1, tgui) << 8);
}
static uint32_t
tgui_accel_read_l(uint32_t addr, void *priv)
{
tgui_t *tgui = (tgui_t *) priv;
return tgui_accel_read_w(addr, tgui) | (tgui_accel_read_w(addr + 2, tgui) << 16);
}
static void
tgui_accel_write_fb_b(uint32_t addr, uint8_t val, void *priv)
{
svga_t *svga = (svga_t *) priv;
tgui_t *tgui = (tgui_t *) svga->priv;
if (tgui->write_blitter) {
tgui_accel_command(8, val << 24, tgui);
} else
svga_write_linear(addr, val, svga);
}
static void
tgui_accel_write_fb_w(uint32_t addr, uint16_t val, void *priv)
{
svga_t *svga = (svga_t *) priv;
tgui_t *tgui = (tgui_t *) svga->priv;
if (tgui->write_blitter)
tgui_accel_command(16, (((val & 0xff00) >> 8) | ((val & 0x00ff) << 8)) << 16, tgui);
else
svga_writew_linear(addr, val, svga);
}
static void
tgui_accel_write_fb_l(uint32_t addr, uint32_t val, void *priv)
{
svga_t *svga = (svga_t *) priv;
tgui_t *tgui = (tgui_t *) svga->priv;
if (tgui->write_blitter)
tgui_accel_command(32, ((val & 0xff000000) >> 24) | ((val & 0x00ff0000) >> 8) | ((val & 0x0000ff00) << 8) | ((val & 0x000000ff) << 24), tgui);
else
svga_writel_linear(addr, val, svga);
}
static void
tgui_mmio_write(uint32_t addr, uint8_t val, void *priv)
{
const tgui_t *tgui = (tgui_t *) priv;
const svga_t *svga = &tgui->svga;
addr &= 0x0000ffff;
if (((svga->crtc[0x36] & 0x03) == 0x00) && (addr >= 0x2100 && addr <= 0x21ff))
tgui_accel_out(addr, val, priv);
else if (((svga->crtc[0x36] & 0x03) > 0x00) && (addr <= 0xff))
tgui_accel_write(addr, val, priv);
else
tgui_out(addr, val, priv);
}
static void
tgui_mmio_write_w(uint32_t addr, uint16_t val, void *priv)
{
const tgui_t *tgui = (tgui_t *) priv;
const svga_t *svga = &tgui->svga;
addr &= 0x0000ffff;
if (((svga->crtc[0x36] & 0x03) == 0x00) && (addr >= 0x2100 && addr <= 0x21ff))
tgui_accel_out_w(addr, val, priv);
else if (((svga->crtc[0x36] & 0x03) > 0x00) && (addr <= 0xff))
tgui_accel_write_w(addr, val, priv);
else {
tgui_out(addr, val & 0xff, priv);
tgui_out(addr + 1, val >> 8, priv);
}
}
static void
tgui_mmio_write_l(uint32_t addr, uint32_t val, void *priv)
{
const tgui_t *tgui = (tgui_t *) priv;
const svga_t *svga = &tgui->svga;
addr &= 0x0000ffff;
if (((svga->crtc[0x36] & 0x03) == 0x00) && (addr >= 0x2100 && addr <= 0x21ff))
tgui_accel_out_l(addr, val, priv);
else if (((svga->crtc[0x36] & 0x03) > 0x00) && (addr <= 0xff))
tgui_accel_write_l(addr, val, priv);
else {
tgui_out(addr, val & 0xff, priv);
tgui_out(addr + 1, val >> 8, priv);
tgui_out(addr + 2, val >> 16, priv);
tgui_out(addr + 3, val >> 24, priv);
}
}
static uint8_t
tgui_mmio_read(uint32_t addr, void *priv)
{
const tgui_t *tgui = (tgui_t *) priv;
const svga_t *svga = &tgui->svga;
uint8_t ret = 0xff;
addr &= 0x0000ffff;
if (((svga->crtc[0x36] & 0x03) == 0x00) && (addr >= 0x2100 && addr <= 0x21ff))
ret = tgui_accel_in(addr, priv);
else if (((svga->crtc[0x36] & 0x03) > 0x00) && (addr <= 0xff))
ret = tgui_accel_read(addr, priv);
else
ret = tgui_in(addr, priv);
return ret;
}
static uint16_t
tgui_mmio_read_w(uint32_t addr, void *priv)
{
const tgui_t *tgui = (tgui_t *) priv;
const svga_t *svga = &tgui->svga;
uint16_t ret = 0xffff;
addr &= 0x0000ffff;
if (((svga->crtc[0x36] & 0x03) == 0x00) && (addr >= 0x2100 && addr <= 0x21ff))
ret = tgui_accel_in_w(addr, priv);
else if (((svga->crtc[0x36] & 0x03) > 0x00) && (addr <= 0xff))
ret = tgui_accel_read_w(addr, priv);
else
ret = tgui_in(addr, priv) | (tgui_in(addr + 1, priv) << 8);
return ret;
}
static uint32_t
tgui_mmio_read_l(uint32_t addr, void *priv)
{
const tgui_t *tgui = (tgui_t *) priv;
const svga_t *svga = &tgui->svga;
uint32_t ret = 0xffffffff;
addr &= 0x0000ffff;
if (((svga->crtc[0x36] & 0x03) == 0x00) && (addr >= 0x2100 && addr <= 0x21ff))
ret = tgui_accel_in_l(addr, priv);
else if (((svga->crtc[0x36] & 0x03) > 0x00) && (addr <= 0xff))
ret = tgui_accel_read_l(addr, priv);
else
ret = tgui_in(addr, priv) | (tgui_in(addr + 1, priv) << 8) | (tgui_in(addr + 2, priv) << 16) | (tgui_in(addr + 3, priv) << 24);
return ret;
}
static void *
tgui_init(const device_t *info)
{
const char *bios_fn;
tgui_t *tgui = malloc(sizeof(tgui_t));
svga_t *svga = &tgui->svga;
memset(tgui, 0, sizeof(tgui_t));
tgui->vram_size = device_get_config_int("memory") << 20;
tgui->vram_mask = tgui->vram_size - 1;
tgui->type = info->local & 0xff;
tgui->pci = !!(info->flags & DEVICE_PCI);
switch (tgui->type) {
case TGUI_9400CXI:
bios_fn = ROM_TGUI_9400CXI;
break;
case TGUI_9440:
if (tgui->pci)
bios_fn = (info->local & ONBOARD) ? NULL : ROM_TGUI_9440_PCI;
else
bios_fn = ROM_TGUI_9440_VLB;
break;
case TGUI_9660:
case TGUI_9680:
bios_fn = (info->local & ONBOARD) ? NULL : ROM_TGUI_96xx;
break;
default:
free(tgui);
return NULL;
}
tgui->has_bios = (bios_fn != NULL);
if (tgui->has_bios) {
rom_init(&tgui->bios_rom, bios_fn, 0xc0000, 0x8000, 0x7fff, 0, MEM_MAPPING_EXTERNAL);
if (tgui->pci)
mem_mapping_disable(&tgui->bios_rom.mapping);
}
if (tgui->pci)
video_inform(VIDEO_FLAG_TYPE_SPECIAL, &timing_tgui_pci);
else
video_inform(VIDEO_FLAG_TYPE_SPECIAL, &timing_tgui_vlb);
svga_init(info, svga, tgui, tgui->vram_size,
tgui_recalctimings,
tgui_in, tgui_out,
tgui_hwcursor_draw,
NULL);
if (tgui->type == TGUI_9400CXI)
svga->ramdac = device_add(&tkd8001_ramdac_device);
mem_mapping_add(&tgui->linear_mapping, 0, 0, svga_read_linear, svga_readw_linear, svga_readl_linear, tgui_accel_write_fb_b, tgui_accel_write_fb_w, tgui_accel_write_fb_l, NULL, MEM_MAPPING_EXTERNAL, svga);
mem_mapping_add(&tgui->accel_mapping, 0, 0, tgui_accel_read, tgui_accel_read_w, tgui_accel_read_l, tgui_accel_write, tgui_accel_write_w, tgui_accel_write_l, NULL, MEM_MAPPING_EXTERNAL, tgui);
if (tgui->type >= TGUI_9440)
mem_mapping_add(&tgui->mmio_mapping, 0, 0, tgui_mmio_read, tgui_mmio_read_w, tgui_mmio_read_l, tgui_mmio_write, tgui_mmio_write_w, tgui_mmio_write_l, NULL, MEM_MAPPING_EXTERNAL, tgui);
mem_mapping_disable(&tgui->accel_mapping);
mem_mapping_disable(&tgui->mmio_mapping);
if (tgui->vram_size == (2 << 20))
svga->crtc[0x21] |= 0x10;
tgui_set_io(tgui);
if (tgui->pci && (tgui->type >= TGUI_9440)) {
if (tgui->has_bios)
pci_add_card(PCI_ADD_NORMAL, tgui_pci_read, tgui_pci_write, tgui, &tgui->pci_slot);
else
pci_add_card(PCI_ADD_VIDEO | PCI_ADD_STRICT, tgui_pci_read, tgui_pci_write, tgui, &tgui->pci_slot);
}
tgui->pci_regs[PCI_REG_COMMAND] = 0x83;
if (tgui->has_bios) {
tgui->pci_regs[0x30] = 0x00;
tgui->pci_regs[0x32] = 0x0c;
tgui->pci_regs[0x33] = 0x00;
}
if (tgui->type >= TGUI_9440) {
svga->packed_chain4 = 1;
tgui->i2c = i2c_gpio_init("ddc_tgui");
tgui->ddc = ddc_init(i2c_gpio_get_bus(tgui->i2c));
}
return tgui;
}
static int
tgui9400cxi_available(void)
{
return rom_present(ROM_TGUI_9400CXI);
}
static int
tgui9440_vlb_available(void)
{
return rom_present(ROM_TGUI_9440_VLB);
}
static int
tgui9440_pci_available(void)
{
return rom_present(ROM_TGUI_9440_PCI);
}
static int
tgui96xx_available(void)
{
return rom_present(ROM_TGUI_96xx);
}
void
tgui_close(void *priv)
{
tgui_t *tgui = (tgui_t *) priv;
svga_close(&tgui->svga);
if (tgui->type >= TGUI_9440) {
ddc_close(tgui->ddc);
i2c_gpio_close(tgui->i2c);
}
free(tgui);
}
void
tgui_speed_changed(void *priv)
{
tgui_t *tgui = (tgui_t *) priv;
svga_recalctimings(&tgui->svga);
}
void
tgui_force_redraw(void *priv)
{
tgui_t *tgui = (tgui_t *) priv;
tgui->svga.fullchange = tgui->svga.monitor->mon_changeframecount;
}
// clang-format off
static const device_config_t tgui9440_config[] = {
{
.name = "memory",
.description = "Memory size",
.type = CONFIG_SELECTION,
.selection = {
{
.description = "1 MB",
.value = 1
},
{
.description = "2 MB",
.value = 2
},
{
.description = ""
}
},
.default_int = 2
},
{
.type = CONFIG_END
}
};
static const device_config_t tgui96xx_config[] = {
{
.name = "memory",
.description = "Memory size",
.type = CONFIG_SELECTION,
.selection = {
{
.description = "1 MB",
.value = 1
},
{
.description = "2 MB",
.value = 2
},
{
.description = "4 MB",
.value = 4
},
{
.description = ""
}
},
.default_int = 4
},
{
.type = CONFIG_END
}
};
// clang-format on
const device_t tgui9400cxi_device = {
.name = "Trident TGUI 9400CXi",
.internal_name = "tgui9400cxi_vlb",
.flags = DEVICE_VLB,
.local = TGUI_9400CXI,
.init = tgui_init,
.close = tgui_close,
.reset = NULL,
{ .available = tgui9400cxi_available },
.speed_changed = tgui_speed_changed,
.force_redraw = tgui_force_redraw,
.config = tgui9440_config
};
const device_t tgui9440_vlb_device = {
.name = "Trident TGUI 9440AGi VLB",
.internal_name = "tgui9440_vlb",
.flags = DEVICE_VLB,
.local = TGUI_9440,
.init = tgui_init,
.close = tgui_close,
.reset = NULL,
{ .available = tgui9440_vlb_available },
.speed_changed = tgui_speed_changed,
.force_redraw = tgui_force_redraw,
.config = tgui9440_config
};
const device_t tgui9440_pci_device = {
.name = "Trident TGUI 9440AGi PCI",
.internal_name = "tgui9440_pci",
.flags = DEVICE_PCI,
.local = TGUI_9440,
.init = tgui_init,
.close = tgui_close,
.reset = NULL,
{ .available = tgui9440_pci_available },
.speed_changed = tgui_speed_changed,
.force_redraw = tgui_force_redraw,
.config = tgui9440_config
};
const device_t tgui9440_onboard_pci_device = {
.name = "Trident TGUI 9440AGi On-Board PCI",
.internal_name = "tgui9440_onboard_pci",
.flags = DEVICE_PCI,
.local = TGUI_9440 | ONBOARD,
.init = tgui_init,
.close = tgui_close,
.reset = NULL,
{ .available = NULL },
.speed_changed = tgui_speed_changed,
.force_redraw = tgui_force_redraw,
.config = tgui9440_config
};
const device_t tgui9660_pci_device = {
.name = "Trident TGUI 9660XGi PCI",
.internal_name = "tgui9660_pci",
.flags = DEVICE_PCI,
.local = TGUI_9660,
.init = tgui_init,
.close = tgui_close,
.reset = NULL,
{ .available = tgui96xx_available },
.speed_changed = tgui_speed_changed,
.force_redraw = tgui_force_redraw,
.config = tgui96xx_config
};
const device_t tgui9660_onboard_pci_device = {
.name = "Trident TGUI 9660XGi On-Board PCI",
.internal_name = "tgui9660_onboard_pci",
.flags = DEVICE_PCI,
.local = TGUI_9660 | ONBOARD,
.init = tgui_init,
.close = tgui_close,
.reset = NULL,
{ .available = NULL },
.speed_changed = tgui_speed_changed,
.force_redraw = tgui_force_redraw,
.config = tgui96xx_config
};
const device_t tgui9680_pci_device = {
.name = "Trident TGUI 9680XGi PCI",
.internal_name = "tgui9680_pci",
.flags = DEVICE_PCI,
.local = TGUI_9680,
.init = tgui_init,
.close = tgui_close,
.reset = NULL,
{ .available = tgui96xx_available },
.speed_changed = tgui_speed_changed,
.force_redraw = tgui_force_redraw,
.config = tgui96xx_config
};
``` | /content/code_sandbox/src/video/vid_tgui9440.c | c | 2016-06-25T22:29:10 | 2024-08-16T19:09:21 | 86Box | 86Box/86Box | 2,616 | 36,976 |
```c
/*
* 86Box A hypervisor and IBM PC system emulator that specializes in
* running old operating systems and software designed for IBM
* PC systems and compatibles from 1981 through fairly recent
* system designs based on the PCI bus.
*
* This file is part of the 86Box distribution.
*
* ICD2061 clock generator emulation.
* Also emulates the ICS9161 which is the same as the ICD2016,
* but without the need for tuning (which is irrelevant in
* emulation anyway).
*
* Used by ET4000w32/p (Diamond Stealth 32) and the S3
* Vision964 family.
*
*
*
* Authors: Miran Grca, <mgrca8@gmail.com>
*
*/
#include <stdarg.h>
#include <stdio.h>
#include <stdint.h>
#include <stdlib.h>
#include <string.h>
#include <wchar.h>
#define HAVE_STDARG_H
#include <86box/86box.h>
#include <86box/device.h>
#include <86box/plat_unused.h>
typedef struct icd2061_t {
float freq[3];
int count;
int bit_count;
int unlocked;
int state;
uint32_t data;
uint32_t ctrl;
} icd2061_t;
#ifdef ENABLE_ICD2061_LOG
int icd2061_do_log = ENABLE_ICD2061_LOG;
static void
icd2061_log(const char *fmt, ...)
{
va_list ap;
if (icd2061_do_log) {
va_start(ap, fmt);
pclog_ex(fmt, ap);
va_end(ap);
}
}
#else
# define icd2061_log(fmt, ...)
#endif
void
icd2061_write(void *priv, int val)
{
icd2061_t *icd2061 = (icd2061_t *) priv;
int nd;
int oc;
int nc;
int a;
int qa;
int q;
int pa;
int p_;
int m;
int ps;
nd = (val & 2) >> 1; /* Old data. */
oc = icd2061->state & 1; /* Old clock. */
nc = val & 1; /* New clock. */
icd2061->state = val;
if (nc && !oc) { /* Low-to-high transition of CLK. */
if (!icd2061->unlocked) {
if (nd) { /* DATA high. */
icd2061->count++;
icd2061_log("Low-to-high transition of CLK with DATA high, %i total\n", icd2061->count);
} else { /* DATA low. */
if (icd2061->count >= 5) {
icd2061->unlocked = 1;
icd2061->bit_count = icd2061->data = 0;
#ifdef ENABLE_ICD2061_LOG
icd2061_log("ICD2061 unlocked\n");
#endif
} else {
icd2061->count = 0;
#ifdef ENABLE_ICD2061_LOG
icd2061_log("ICD2061 locked\n");
#endif
}
}
} else if (nc) {
icd2061->data |= (nd << icd2061->bit_count);
icd2061->bit_count++;
if (icd2061->bit_count == 26) {
icd2061_log("26 bits received, data = %08X\n", icd2061->data);
a = ((icd2061->data >> 22) & 0x07); /* A */
icd2061_log("A = %01X\n", a);
if (a < 3) {
pa = ((icd2061->data >> 11) & 0x7f); /* P' (ICD2061) / N' (ICS9161) */
m = ((icd2061->data >> 8) & 0x07); /* M (ICD2061) / R (ICS9161) */
qa = ((icd2061->data >> 1) & 0x7f); /* Q' (ICD2061) / M' (ICS9161) */
p_ = pa + 3; /* P (ICD2061) / N (ICS9161) */
m = 1 << m;
q = qa + 2; /* Q (ICD2061) / M (ICS9161) */
ps = (icd2061->ctrl & (1 << a)) ? 4 : 2; /* Prescale */
icd2061->freq[a] = ((float) (p_ * ps) / (float) (q * m)) * 14318184.0f;
icd2061_log("P = %02X, M = %01X, Q = %02X, freq[%i] = %f\n", p_, m, q, a, icd2061->freq[a]);
} else if (a == 6) {
icd2061->ctrl = ((icd2061->data >> 13) & 0xff);
icd2061_log("ctrl = %02X\n", icd2061->ctrl);
}
icd2061->count = icd2061->bit_count = icd2061->data = 0;
icd2061->unlocked = 0;
#ifdef ENABLE_ICD2061_LOG
icd2061_log("ICD2061 locked\n");
#endif
}
}
}
}
float
icd2061_getclock(int clock, void *priv)
{
const icd2061_t *icd2061 = (icd2061_t *) priv;
if (clock > 2)
clock = 2;
return icd2061->freq[clock];
}
static void *
icd2061_init(UNUSED(const device_t *info))
{
icd2061_t *icd2061 = (icd2061_t *) malloc(sizeof(icd2061_t));
memset(icd2061, 0, sizeof(icd2061_t));
icd2061->freq[0] = 25175000.0;
icd2061->freq[1] = 28322000.0;
icd2061->freq[2] = 28322000.0;
return icd2061;
}
static void
icd2061_close(void *priv)
{
icd2061_t *icd2061 = (icd2061_t *) priv;
if (icd2061)
free(icd2061);
}
const device_t icd2061_device = {
.name = "ICD2061 Clock Generator",
.internal_name = "icd2061",
.flags = 0,
.local = 0,
.init = icd2061_init,
.close = icd2061_close,
.reset = NULL,
{ .available = NULL },
.speed_changed = NULL,
.force_redraw = NULL,
.config = NULL
};
const device_t ics9161_device = {
.name = "ICS9161 Clock Generator",
.internal_name = "ics9161",
.flags = 0,
.local = 0,
.init = icd2061_init,
.close = icd2061_close,
.reset = NULL,
{ .available = NULL },
.speed_changed = NULL,
.force_redraw = NULL,
.config = NULL
};
``` | /content/code_sandbox/src/video/vid_icd2061.c | c | 2016-06-25T22:29:10 | 2024-08-16T19:09:21 | 86Box | 86Box/86Box | 2,616 | 1,718 |
```c
/*
* 86Box A hypervisor and IBM PC system emulator that specializes in
* running old operating systems and software designed for IBM
* PC systems and compatibles from 1981 through fairly recent
* system designs based on the PCI bus.
*
* This file is part of the 86Box distribution.
*
* ATI 18800 emulation (VGA Edge-16)
*
*
*
* Authors: Sarah Walker, <path_to_url
* Miran Grca, <mgrca8@gmail.com>
*
*/
#include <stdio.h>
#include <stdint.h>
#include <string.h>
#include <stdlib.h>
#include <wchar.h>
#include <86box/86box.h>
#include <86box/io.h>
#include <86box/mem.h>
#include <86box/rom.h>
#include <86box/device.h>
#include <86box/timer.h>
#include <86box/video.h>
#include <86box/vid_ati_eeprom.h>
#include <86box/vid_svga.h>
#include <86box/vid_svga_render.h>
#define BIOS_ROM_PATH_WONDER "roms/video/ati18800/VGA_Wonder_V3-1.02.bin"
#define BIOS_ROM_PATH_VGA88 "roms/video/ati18800/vga88.bin"
#define BIOS_ROM_PATH_EDGE16 "roms/video/ati18800/vgaedge16.vbi"
enum {
ATI18800_WONDER = 0,
ATI18800_VGA88,
ATI18800_EDGE16
};
typedef struct ati18800_t {
svga_t svga;
ati_eeprom_t eeprom;
rom_t bios_rom;
uint8_t regs[256];
int index;
int type;
uint32_t memory;
} ati18800_t;
static video_timings_t timing_ati18800 = { .type = VIDEO_ISA, .write_b = 8, .write_w = 16, .write_l = 32, .read_b = 8, .read_w = 16, .read_l = 32 };
static void
ati18800_out(uint16_t addr, uint8_t val, void *priv)
{
ati18800_t *ati18800 = (ati18800_t *) priv;
svga_t *svga = &ati18800->svga;
uint8_t old;
if (((addr & 0xfff0) == 0x3d0 || (addr & 0xfff0) == 0x3b0) && !(svga->miscout & 1))
addr ^= 0x60;
switch (addr) {
case 0x1ce:
ati18800->index = val;
break;
case 0x1cf:
old = ati18800->regs[ati18800->index];
ati18800->regs[ati18800->index] = val;
switch (ati18800->index) {
case 0xb0:
if ((old ^ val) & 6)
svga_recalctimings(svga);
break;
case 0xb2:
case 0xbe:
if (ati18800->regs[0xbe] & 8) { /*Read/write bank mode*/
svga->read_bank = ((ati18800->regs[0xb2] & 0xe0) >> 5) * 0x10000;
svga->write_bank = ((ati18800->regs[0xb2] & 0x0e) >> 1) * 0x10000;
} else /*Single bank mode*/
svga->read_bank = svga->write_bank = ((ati18800->regs[0xb2] & 0x0e) >> 1) * 0x10000;
break;
case 0xb3:
ati_eeprom_write(&ati18800->eeprom, val & 8, val & 2, val & 1);
break;
default:
break;
}
break;
case 0x3D4:
svga->crtcreg = val & 0x3f;
return;
case 0x3D5:
if ((svga->crtcreg < 7) && (svga->crtc[0x11] & 0x80) && !(ati18800->regs[0xb4] & 0x80))
return;
if ((svga->crtcreg == 7) && (svga->crtc[0x11] & 0x80) && !(ati18800->regs[0xb4] & 0x80))
val = (svga->crtc[7] & ~0x10) | (val & 0x10);
old = svga->crtc[svga->crtcreg];
svga->crtc[svga->crtcreg] = val;
if (old != val) {
if (svga->crtcreg < 0xe || svga->crtcreg > 0x10) {
if ((svga->crtcreg == 0xc) || (svga->crtcreg == 0xd)) {
svga->fullchange = 3;
svga->ma_latch = ((svga->crtc[0xc] << 8) | svga->crtc[0xd]) + ((svga->crtc[8] & 0x60) >> 5);
} else {
svga->fullchange = changeframecount;
svga_recalctimings(svga);
}
}
}
break;
default:
break;
}
svga_out(addr, val, svga);
}
static uint8_t
ati18800_in(uint16_t addr, void *priv)
{
ati18800_t *ati18800 = (ati18800_t *) priv;
svga_t *svga = &ati18800->svga;
uint8_t temp = 0xff;
if (((addr & 0xFFF0) == 0x3D0 || (addr & 0xFFF0) == 0x3B0) && !(svga->miscout & 1))
addr ^= 0x60;
switch (addr) {
case 0x1ce:
temp = ati18800->index;
break;
case 0x1cf:
switch (ati18800->index) {
case 0xb7:
temp = ati18800->regs[ati18800->index] & ~8;
if (ati_eeprom_read(&ati18800->eeprom))
temp |= 8;
break;
default:
temp = ati18800->regs[ati18800->index];
break;
}
break;
case 0x3D4:
temp = svga->crtcreg;
break;
case 0x3D5:
temp = svga->crtc[svga->crtcreg];
break;
default:
temp = svga_in(addr, svga);
break;
}
return temp;
}
static void
ati18800_recalctimings(svga_t *svga)
{
const ati18800_t *ati18800 = (ati18800_t *) svga->priv;
int clock_sel;
clock_sel = ((svga->miscout >> 2) & 3) | ((ati18800->regs[0xbe] & 0x10) >> 1) | ((ati18800->regs[0xb9] & 2) << 1);
if (ati18800->regs[0xb6] & 0x10) {
svga->hdisp <<= 1;
svga->htotal <<= 1;
svga->rowoffset <<= 1;
svga->gdcreg[5] &= ~0x40;
}
if (ati18800->regs[0xb0] & 6) {
svga->gdcreg[5] |= 0x40;
if ((ati18800->regs[0xb6] & 0x18) >= 0x10)
svga->packed_4bpp = 1;
else
svga->packed_4bpp = 0;
} else
svga->packed_4bpp = 0;
if ((ati18800->regs[0xb6] & 0x18) == 8) {
svga->hdisp <<= 1;
svga->htotal <<= 1;
svga->ati_4color = 1;
} else
svga->ati_4color = 0;
if (!svga->scrblank && (svga->crtc[0x17] & 0x80) && svga->attr_palette_enable) {
if ((svga->gdcreg[6] & 1) || (svga->attrregs[0x10] & 1)) {
svga->clock = (cpuclock * (double) (1ULL << 32)) / svga->getclock(clock_sel, svga->clock_gen);
switch (svga->gdcreg[5] & 0x60) {
case 0x00:
if (svga->seqregs[1] & 8) /*Low res (320)*/
svga->render = svga_render_4bpp_lowres;
else
svga->render = svga_render_4bpp_highres;
break;
case 0x20: /*4 colours*/
if (svga->seqregs[1] & 8) /*Low res (320)*/
svga->render = svga_render_2bpp_lowres;
else
svga->render = svga_render_2bpp_highres;
break;
case 0x40:
case 0x60: /*256+ colours*/
switch (svga->bpp) {
default:
case 8:
svga->map8 = svga->pallook;
if (svga->lowres)
svga->render = svga_render_8bpp_lowres;
else {
svga->render = svga_render_8bpp_highres;
if (!svga->packed_4bpp) {
svga->ma_latch <<= 1;
svga->rowoffset <<= 1;
}
}
break;
}
break;
default:
break;
}
}
}
}
static void *
ati18800_init(const device_t *info)
{
ati18800_t *ati18800 = malloc(sizeof(ati18800_t));
memset(ati18800, 0, sizeof(ati18800_t));
video_inform(VIDEO_FLAG_TYPE_SPECIAL, &timing_ati18800);
ati18800->type = info->local;
switch (info->local) {
default:
case ATI18800_WONDER:
rom_init(&ati18800->bios_rom, BIOS_ROM_PATH_WONDER, 0xc0000, 0x8000, 0x7fff, 0, MEM_MAPPING_EXTERNAL);
ati18800->memory = device_get_config_int("memory");
break;
case ATI18800_VGA88:
rom_init(&ati18800->bios_rom, BIOS_ROM_PATH_VGA88, 0xc0000, 0x8000, 0x7fff, 0, MEM_MAPPING_EXTERNAL);
ati18800->memory = 256;
break;
case ATI18800_EDGE16:
rom_init(&ati18800->bios_rom, BIOS_ROM_PATH_EDGE16, 0xc0000, 0x8000, 0x7fff, 0, MEM_MAPPING_EXTERNAL);
ati18800->memory = 512;
break;
}
svga_init(info, &ati18800->svga, ati18800, ati18800->memory << 10,
ati18800_recalctimings,
ati18800_in, ati18800_out,
NULL,
NULL);
ati18800->svga.clock_gen = device_add(&ati18810_device);
ati18800->svga.getclock = ics2494_getclock;
io_sethandler(0x01ce, 0x0002, ati18800_in, NULL, NULL, ati18800_out, NULL, NULL, ati18800);
io_sethandler(0x03c0, 0x0020, ati18800_in, NULL, NULL, ati18800_out, NULL, NULL, ati18800);
ati18800->svga.miscout = 1;
ati18800->svga.bpp = 8;
ati_eeprom_load(&ati18800->eeprom, "ati18800.nvr", 0);
return ati18800;
}
static int
ati18800_wonder_available(void)
{
return rom_present(BIOS_ROM_PATH_WONDER);
}
static int
ati18800_vga88_available(void)
{
return rom_present(BIOS_ROM_PATH_VGA88);
}
static int
ati18800_available(void)
{
return rom_present(BIOS_ROM_PATH_EDGE16);
}
static void
ati18800_close(void *priv)
{
ati18800_t *ati18800 = (ati18800_t *) priv;
svga_close(&ati18800->svga);
free(ati18800);
}
static void
ati18800_speed_changed(void *priv)
{
ati18800_t *ati18800 = (ati18800_t *) priv;
svga_recalctimings(&ati18800->svga);
}
static void
ati18800_force_redraw(void *priv)
{
ati18800_t *ati18800 = (ati18800_t *) priv;
ati18800->svga.fullchange = changeframecount;
}
static const device_config_t ati18800_wonder_config[] = {
{
.name = "memory",
.description = "Memory size",
.type = CONFIG_SELECTION,
.default_int = 512,
.selection = {
{
.description = "256 kB",
.value = 256
},
{
.description = "512 kB",
.value = 512
},
{
.description = ""
}
}
},
{
.type = CONFIG_END
}
};
const device_t ati18800_wonder_device = {
.name = "ATI-18800",
.internal_name = "ati18800w",
.flags = DEVICE_ISA,
.local = ATI18800_WONDER,
.init = ati18800_init,
.close = ati18800_close,
.reset = NULL,
{ .available = ati18800_wonder_available },
.speed_changed = ati18800_speed_changed,
.force_redraw = ati18800_force_redraw,
.config = ati18800_wonder_config
};
const device_t ati18800_vga88_device = {
.name = "ATI 18800-1",
.internal_name = "ati18800v",
.flags = DEVICE_ISA,
.local = ATI18800_VGA88,
.init = ati18800_init,
.close = ati18800_close,
.reset = NULL,
{ .available = ati18800_vga88_available },
.speed_changed = ati18800_speed_changed,
.force_redraw = ati18800_force_redraw,
.config = NULL
};
const device_t ati18800_device = {
.name = "ATI VGA Edge 16",
.internal_name = "ati18800",
.flags = DEVICE_ISA,
.local = ATI18800_EDGE16,
.init = ati18800_init,
.close = ati18800_close,
.reset = NULL,
{ .available = ati18800_available },
.speed_changed = ati18800_speed_changed,
.force_redraw = ati18800_force_redraw,
.config = NULL
};
``` | /content/code_sandbox/src/video/vid_ati18800.c | c | 2016-06-25T22:29:10 | 2024-08-16T19:09:21 | 86Box | 86Box/86Box | 2,616 | 3,631 |
```c
/*
* 86Box A hypervisor and IBM PC system emulator that specializes in
* running old operating systems and software designed for IBM
* PC systems and compatibles from 1981 through fairly recent
* system designs based on the PCI bus.
*
* This file is part of the 86Box distribution.
*
* Hercules emulation.
*
*
*
* Authors: Sarah Walker, <path_to_url
* Miran Grca, <mgrca8@gmail.com>
*
*/
#include <stdio.h>
#include <stdint.h>
#include <stdlib.h>
#include <string.h>
#include <wchar.h>
#include <86box/86box.h>
#include "cpu.h"
#include <86box/mem.h>
#include <86box/rom.h>
#include <86box/io.h>
#include <86box/timer.h>
#include <86box/lpt.h>
#include <86box/pit.h>
#include <86box/device.h>
#include <86box/video.h>
#include <86box/vid_hercules.h>
#include <86box/plat_unused.h>
static video_timings_t timing_hercules = { .type = VIDEO_ISA, .write_b = 8, .write_w = 16, .write_l = 32, .read_b = 8, .read_w = 16, .read_l = 32 };
static void
recalc_timings(hercules_t *dev)
{
double disptime;
double _dispontime;
double _dispofftime;
disptime = dev->crtc[0] + 1;
_dispontime = dev->crtc[1];
_dispofftime = disptime - _dispontime;
_dispontime *= HERCCONST;
_dispofftime *= HERCCONST;
dev->dispontime = (uint64_t) (_dispontime);
dev->dispofftime = (uint64_t) (_dispofftime);
}
static uint8_t crtcmask[32] = {
0xff, 0xff, 0xff, 0xff, 0x7f, 0x1f, 0x7f, 0x7f, 0xf3, 0x1f, 0x7f, 0x1f, 0x3f, 0xff, 0x3f, 0xff,
0xff, 0xff, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
};
static void
hercules_out(uint16_t addr, uint8_t val, void *priv)
{
hercules_t *dev = (hercules_t *) priv;
uint8_t old;
VIDEO_MONITOR_PROLOGUE()
switch (addr) {
case 0x03b0:
case 0x03b2:
case 0x03b4:
case 0x03b6:
dev->crtcreg = val & 31;
break;
case 0x03b1:
case 0x03b3:
case 0x03b5:
case 0x03b7:
old = dev->crtc[dev->crtcreg];
dev->crtc[dev->crtcreg] = val & crtcmask[dev->crtcreg];
/*
* Fix for Generic Turbo XT BIOS, which
* sets up cursor registers wrong.
*/
if (dev->crtc[10] == 6 && dev->crtc[11] == 7) {
dev->crtc[10] = 0xb;
dev->crtc[11] = 0xc;
}
if (old != val) {
if ((dev->crtcreg < 0xe) || (dev->crtcreg > 0x10)) {
dev->fullchange = changeframecount;
recalc_timings(dev);
}
}
break;
case 0x03b8:
old = dev->ctrl;
/* Prevent setting of bits if they are disabled in CTRL2. */
if ((old & 0x02) && !(val & 0x02))
dev->ctrl &= 0xfd;
else if ((val & 0x02) && (dev->ctrl2 & 0x01))
dev->ctrl |= 0x02;
if ((old & 0x80) && !(val & 0x80))
dev->ctrl &= 0x7f;
else if ((val & 0x80) && (dev->ctrl2 & 0x02))
dev->ctrl |= 0x80;
dev->ctrl = (dev->ctrl & 0x82) | (val & 0x7d);
if (old ^ val)
recalc_timings(dev);
break;
case 0x03b9:
case 0x03bb:
dev->lp_ff = !(addr & 0x0002);
break;
case 0x03bf:
old = dev->ctrl2;
dev->ctrl2 = val;
/* According to the Programmer's guide to the Hercules graphics cars
by David B. Doty from 1988, the CTRL2 modes (bits 1,0) are as follow:
- 00: DIAG: Text mode only, only page 0 accessible;
- 01: HALF: Graphics mode allowed, only page 0 accessible;
- 11: FULL: Graphics mode allowed, both pages accessible. */
if (val & 0x01)
mem_mapping_set_exec(&dev->mapping, dev->vram);
else
mem_mapping_set_exec(&dev->mapping, NULL);
if (val & 0x02)
mem_mapping_set_addr(&dev->mapping, 0xb0000, 0x10000);
else
mem_mapping_set_addr(&dev->mapping, 0xb0000, 0x08000);
if (old ^ val)
recalc_timings(dev);
break;
default:
break;
}
VIDEO_MONITOR_EPILOGUE()
}
static uint8_t
hercules_in(uint16_t addr, void *priv)
{
const hercules_t *dev = (hercules_t *) priv;
uint8_t ret = 0xff;
switch (addr) {
case 0x03b0:
case 0x03b2:
case 0x03b4:
case 0x03b6:
ret = dev->crtcreg;
break;
case 0x03b1:
case 0x03b3:
case 0x03b5:
case 0x03b7:
if (dev->crtcreg == 0x0c)
ret = (dev->ma >> 8) & 0x3f;
else if (dev->crtcreg == 0x0d)
ret = dev->ma & 0xff;
else
ret = dev->crtc[dev->crtcreg];
break;
case 0x03ba:
ret = 0x70; /* Hercules ident */
ret |= (dev->lp_ff ? 2 : 0);
ret |= (dev->stat & 0x01);
if (dev->stat & 0x08)
ret |= 0x80;
if ((ret & 0x81) == 0x80)
ret |= 0x08;
break;
default:
break;
}
return ret;
}
static void
hercules_waitstates(UNUSED(void *priv))
{
int ws_array[16] = { 3, 4, 5, 6, 7, 8, 4, 5, 6, 7, 8, 4, 5, 6, 7, 8 };
int ws;
ws = ws_array[cycles & 0xf];
cycles -= ws;
}
static void
hercules_write(uint32_t addr, uint8_t val, void *priv)
{
hercules_t *dev = (hercules_t *) priv;
if (dev->ctrl2 & 0x01)
addr &= 0xffff;
else
addr &= 0x0fff;
dev->vram[addr] = val;
hercules_waitstates(dev);
}
static uint8_t
hercules_read(uint32_t addr, void *priv)
{
hercules_t *dev = (hercules_t *) priv;
uint8_t ret = 0xff;
if (dev->ctrl2 & 0x01)
addr &= 0xffff;
else
addr &= 0x0fff;
hercules_waitstates(dev);
ret = dev->vram[addr];
return ret;
}
static void
hercules_render_overscan_left(hercules_t *dev)
{
uint32_t width;
if (dev->ctrl & 0x02)
width = (((uint32_t) dev->crtc[1]) << 4);
else
width = (((uint32_t) dev->crtc[1]) * 9);
if ((dev->displine + 14) < 0)
return;
if (width == 0)
return;
for (uint8_t i = 0; i < 8; i++)
buffer32->line[dev->displine + 14][i] = 0x00000000;
}
static void
hercules_render_overscan_right(hercules_t *dev)
{
uint32_t width;
if (dev->ctrl & 0x02)
width = (((uint32_t) dev->crtc[1]) << 4);
else
width = (((uint32_t) dev->crtc[1]) * 9);
if ((dev->displine + 14) < 0)
return;
if (width == 0)
return;
for (uint8_t i = 0; i < 8; i++)
buffer32->line[dev->displine + 14][8 + width + i] = 0x00000000;
}
static void
hercules_poll(void *priv)
{
hercules_t *dev = (hercules_t *) priv;
uint8_t chr;
uint8_t attr;
uint16_t ca;
uint16_t dat;
uint16_t pa;
int oldsc;
int blink;
int x;
int xx;
int y;
int yy;
int c;
int oldvc;
int drawcursor;
uint32_t *p;
VIDEO_MONITOR_PROLOGUE()
ca = (dev->crtc[15] | (dev->crtc[14] << 8)) & 0x3fff;
if (!dev->linepos) {
timer_advance_u64(&dev->timer, dev->dispofftime);
dev->stat |= 1;
dev->linepos = 1;
oldsc = dev->sc;
if ((dev->crtc[8] & 3) == 3)
dev->sc = (dev->sc << 1) & 7;
if (dev->dispon) {
if (dev->displine < dev->firstline) {
dev->firstline = dev->displine;
video_wait_for_buffer();
}
dev->lastline = dev->displine;
hercules_render_overscan_left(dev);
if (dev->ctrl & 0x02) {
ca = (dev->sc & 3) * 0x2000;
if (dev->ctrl & 0x80)
ca += 0x8000;
for (x = 0; x < dev->crtc[1]; x++) {
if (dev->ctrl & 8)
dat = (dev->vram[((dev->ma << 1) & 0x1fff) + ca] << 8) | dev->vram[((dev->ma << 1) & 0x1fff) + ca + 1];
else
dat = 0;
dev->ma++;
for (c = 0; c < 16; c++)
buffer32->line[dev->displine + 14][(x << 4) + c + 8] = (dat & (32768 >> c)) ? 7 : 0;
for (c = 0; c < 16; c += 8)
video_blend((x << 4) + c + 8, dev->displine + 14);
}
} else {
for (x = 0; x < dev->crtc[1]; x++) {
if (dev->ctrl & 8) {
/* Undocumented behavior: page 1 in text mode means characters are read
from page 1 and attributes from page 0. */
chr = dev->charbuffer[x << 1];
attr = dev->charbuffer[(x << 1) + 1];
} else
chr = attr = 0;
drawcursor = ((dev->ma == ca) && dev->con && dev->cursoron);
blink = ((dev->blink & 16) && (dev->ctrl & 0x20) && (attr & 0x80) && !drawcursor);
if (dev->sc == 12 && ((attr & 7) == 1)) {
for (c = 0; c < 9; c++)
buffer32->line[dev->displine + 14][(x * 9) + c + 8] = dev->cols[attr][blink][1];
} else {
for (c = 0; c < 8; c++)
buffer32->line[dev->displine + 14][(x * 9) + c + 8] = dev->cols[attr][blink][(fontdatm[chr][dev->sc] & (1 << (c ^ 7))) ? 1 : 0];
if ((chr & ~0x1f) == 0xc0)
buffer32->line[dev->displine + 14][(x * 9) + 8 + 8] = dev->cols[attr][blink][fontdatm[chr][dev->sc] & 1];
else
buffer32->line[dev->displine + 14][(x * 9) + 8 + 8] = dev->cols[attr][blink][0];
}
if (dev->ctrl2 & 0x01)
dev->ma = (dev->ma + 1) & 0x3fff;
else
dev->ma = (dev->ma + 1) & 0x7ff;
if (drawcursor) {
for (c = 0; c < 9; c++)
buffer32->line[dev->displine + 14][(x * 9) + c + 8] ^= dev->cols[attr][0][1];
}
}
}
hercules_render_overscan_right(dev);
if (dev->ctrl & 0x02)
x = dev->crtc[1] << 4;
else
x = dev->crtc[1] * 9;
video_process_8(x + 16, dev->displine + 14);
}
dev->sc = oldsc;
if (dev->vc == dev->crtc[7] && !dev->sc)
dev->stat |= 8;
dev->displine++;
if (dev->displine >= 500)
dev->displine = 0;
} else {
timer_advance_u64(&dev->timer, dev->dispontime);
if (dev->dispon)
dev->stat &= ~1;
dev->linepos = 0;
if (dev->vsynctime) {
dev->vsynctime--;
if (!dev->vsynctime)
dev->stat &= ~8;
}
if (dev->sc == (dev->crtc[11] & 31) || ((dev->crtc[8] & 3) == 3 && dev->sc == ((dev->crtc[11] & 31) >> 1))) {
dev->con = 0;
dev->coff = 1;
}
if (dev->vadj) {
dev->sc++;
dev->sc &= 31;
dev->ma = dev->maback;
dev->vadj--;
if (!dev->vadj) {
dev->dispon = 1;
dev->ma = dev->maback = (dev->crtc[13] | (dev->crtc[12] << 8)) & 0x3fff;
dev->sc = 0;
}
} else if (((dev->crtc[8] & 3) != 3 && dev->sc == dev->crtc[9]) || ((dev->crtc[8] & 3) == 3 && dev->sc == (dev->crtc[9] >> 1))) {
dev->maback = dev->ma;
dev->sc = 0;
oldvc = dev->vc;
dev->vc++;
dev->vc &= 127;
if (dev->vc == dev->crtc[6])
dev->dispon = 0;
if (oldvc == dev->crtc[4]) {
dev->vc = 0;
dev->vadj = dev->crtc[5];
if (!dev->vadj) {
dev->dispon = 1;
dev->ma = dev->maback = (dev->crtc[13] | (dev->crtc[12] << 8)) & 0x3fff;
}
switch (dev->crtc[10] & 0x60) {
case 0x20:
dev->cursoron = 0;
break;
case 0x60:
dev->cursoron = dev->blink & 0x10;
break;
default:
dev->cursoron = dev->blink & 0x08;
break;
}
}
if (dev->vc == dev->crtc[7]) {
dev->dispon = 0;
dev->displine = 0;
if ((dev->crtc[8] & 3) == 3)
dev->vsynctime = ((int32_t) dev->crtc[4] * ((dev->crtc[9] >> 1) + 1)) + dev->crtc[5] - dev->crtc[7] + 1;
else
dev->vsynctime = ((int32_t) dev->crtc[4] * (dev->crtc[9] + 1)) + dev->crtc[5] - dev->crtc[7] + 1;
if (dev->crtc[7]) {
if (dev->ctrl & 0x02)
x = dev->crtc[1] << 4;
else
x = dev->crtc[1] * 9;
dev->lastline++;
y = (dev->lastline - dev->firstline);
if ((dev->ctrl & 8) && x && y && ((x != xsize) || (y != ysize) || video_force_resize_get())) {
xsize = x;
ysize = y;
if (xsize < 64)
xsize = enable_overscan ? 640 : 656;
if (ysize < 32)
ysize = 200;
set_screen_size(xsize + (enable_overscan ? 16 : 0), ysize + (enable_overscan ? 28 : 0));
if (video_force_resize_get())
video_force_resize_set(0);
}
if ((x >= 160) && ((y + 1) >= 120)) {
/* Draw (overscan_size) lines of overscan on top and bottom. */
for (yy = 0; yy < 14; yy++) {
p = &(buffer32->line[(dev->firstline + yy) & 0x7ff][0]);
for (xx = 0; xx < (x + 16); xx++)
p[xx] = 0x00000000;
}
for (yy = 0; yy < 14; yy++) {
p = &(buffer32->line[(dev->firstline + 14 + y + yy) & 0x7ff][0]);
for (xx = 0; xx < (x + 16); xx++)
p[xx] = 0x00000000;
}
}
if (enable_overscan)
video_blit_memtoscreen(0, dev->firstline, xsize + 16, ysize + 28);
else
video_blit_memtoscreen(8, dev->firstline + 14, xsize, ysize);
frames++;
#if 0
if ((dev->ctrl & 2) && (dev->ctrl2 & 1)) {
#endif
if (dev->ctrl & 0x02) {
video_res_x = dev->crtc[1] * 16;
video_res_y = dev->crtc[6] * 4;
video_bpp = 1;
} else {
video_res_x = dev->crtc[1];
video_res_y = dev->crtc[6];
video_bpp = 0;
}
}
dev->firstline = 1000;
dev->lastline = 0;
dev->blink++;
}
} else {
dev->sc++;
dev->sc &= 31;
dev->ma = dev->maback;
}
if (dev->sc == (dev->crtc[10] & 31) || ((dev->crtc[8] & 3) == 3 && dev->sc == ((dev->crtc[10] & 31) >> 1)))
dev->con = 1;
if (dev->dispon && !(dev->ctrl & 0x02)) {
for (x = 0; x < (dev->crtc[1] << 1); x++) {
pa = (dev->ctrl & 0x80) ? ((x & 1) ? 0x0000 : 0x8000) : 0x0000;
dev->charbuffer[x] = dev->vram[(((dev->ma << 1) + x) & 0x3fff) + pa];
}
}
}
VIDEO_MONITOR_EPILOGUE()
}
static void *
hercules_init(UNUSED(const device_t *info))
{
hercules_t *dev;
dev = (hercules_t *) malloc(sizeof(hercules_t));
memset(dev, 0x00, sizeof(hercules_t));
dev->monitor_index = monitor_index_global;
overscan_x = 16;
overscan_y = 28;
dev->vram = (uint8_t *) malloc(0x10000);
timer_add(&dev->timer, hercules_poll, dev, 1);
mem_mapping_add(&dev->mapping, 0xb0000, 0x08000,
hercules_read, NULL, NULL, hercules_write, NULL, NULL,
NULL /*dev->vram*/, MEM_MAPPING_EXTERNAL, dev);
io_sethandler(0x03b0, 16,
hercules_in, NULL, NULL, hercules_out, NULL, NULL, dev);
for (uint16_t c = 0; c < 256; c++) {
dev->cols[c][0][0] = dev->cols[c][1][0] = dev->cols[c][1][1] = 16;
if (c & 0x08)
dev->cols[c][0][1] = 15 + 16;
else
dev->cols[c][0][1] = 7 + 16;
}
dev->cols[0x70][0][1] = 16;
dev->cols[0x70][0][0] = dev->cols[0x70][1][0] = dev->cols[0x70][1][1] = 16 + 15;
dev->cols[0xF0][0][1] = 16;
dev->cols[0xF0][0][0] = dev->cols[0xF0][1][0] = dev->cols[0xF0][1][1] = 16 + 15;
dev->cols[0x78][0][1] = 16 + 7;
dev->cols[0x78][0][0] = dev->cols[0x78][1][0] = dev->cols[0x78][1][1] = 16 + 15;
dev->cols[0xF8][0][1] = 16 + 7;
dev->cols[0xF8][0][0] = dev->cols[0xF8][1][0] = dev->cols[0xF8][1][1] = 16 + 15;
dev->cols[0x00][0][1] = dev->cols[0x00][1][1] = 16;
dev->cols[0x08][0][1] = dev->cols[0x08][1][1] = 16;
dev->cols[0x80][0][1] = dev->cols[0x80][1][1] = 16;
dev->cols[0x88][0][1] = dev->cols[0x88][1][1] = 16;
overscan_x = overscan_y = 0;
cga_palette = device_get_config_int("rgb_type") << 1;
if (cga_palette > 6)
cga_palette = 0;
cgapal_rebuild();
herc_blend = device_get_config_int("blend");
video_inform(VIDEO_FLAG_TYPE_MDA, &timing_hercules);
/* Force the LPT3 port to be enabled. */
lpt3_init(0x3BC);
return dev;
}
static void
hercules_close(void *priv)
{
hercules_t *dev = (hercules_t *) priv;
if (!dev)
return;
if (dev->vram)
free(dev->vram);
free(dev);
}
static void
speed_changed(void *priv)
{
hercules_t *dev = (hercules_t *) priv;
recalc_timings(dev);
}
static const device_config_t hercules_config[] = {
// clang-format off
{
.name = "rgb_type",
.description = "Display type",
.type = CONFIG_SELECTION,
.default_int = 0,
.selection = {
{
.description = "Default",
.value = 0
},
{
.description = "Green",
.value = 1
},
{
.description = "Amber",
.value = 2
},
{
.description = "Gray",
.value = 3
},
{
.description = ""
}
}
},
{
.name = "blend",
.description = "Blend",
.type = CONFIG_BINARY,
.default_int = 1
},
{
.type = CONFIG_END
}
// clang-format on
};
const device_t hercules_device = {
.name = "Hercules",
.internal_name = "hercules",
.flags = DEVICE_ISA,
.local = 0,
.init = hercules_init,
.close = hercules_close,
.reset = NULL,
{ .available = NULL },
.speed_changed = speed_changed,
.force_redraw = NULL,
.config = hercules_config
};
``` | /content/code_sandbox/src/video/vid_hercules.c | c | 2016-06-25T22:29:10 | 2024-08-16T19:09:21 | 86Box | 86Box/86Box | 2,616 | 6,342 |
```c
/*
* 86Box A hypervisor and IBM PC system emulator that specializes in
* running old operating systems and software designed for IBM
* PC systems and compatibles from 1981 through fairly recent
* system designs based on the PCI bus.
*
* This file is part of the 86Box distribution.
*
* Trident TVGA (8900D) emulation.
*
*
*
* Authors: Sarah Walker, <path_to_url
* Miran Grca, <mgrca8@gmail.com>
*
*/
#include <stdio.h>
#include <stdint.h>
#include <string.h>
#include <stdlib.h>
#include <wchar.h>
#include <86box/86box.h>
#include <86box/io.h>
#include <86box/timer.h>
#include <86box/mem.h>
#include <86box/rom.h>
#include <86box/device.h>
#include <86box/video.h>
#include <86box/vid_svga.h>
#include <86box/vid_svga_render.h>
#define TVGA8900B_ID 0x03
#define TVGA9000B_ID 0x23
#define TVGA8900CLD_ID 0x33
#define ROM_TVGA_8900B "roms/video/tvga/tvga8900b.vbi"
#define ROM_TVGA_8900CLD "roms/video/tvga/trident.bin"
#define ROM_TVGA_8900DR "roms/video/tvga/8900DR.VBI"
#define ROM_TVGA_9000B "roms/video/tvga/tvga9000b.bin"
#define ROM_TVGA_9000B_NEC_SV9000 "roms/video/tvga/SV9000.VBI"
typedef struct tvga_t {
mem_mapping_t linear_mapping;
mem_mapping_t accel_mapping;
svga_t svga;
rom_t bios_rom;
uint8_t card_id;
uint8_t tvga_3d8, tvga_3d9;
int oldmode;
uint8_t oldctrl1;
uint8_t oldctrl2, newctrl2;
int vram_size;
uint32_t vram_mask;
} tvga_t;
video_timings_t timing_tvga8900 = { .type = VIDEO_ISA, .write_b = 3, .write_w = 3, .write_l = 6, .read_b = 8, .read_w = 8, .read_l = 12 };
video_timings_t timing_tvga8900dr = { .type = VIDEO_ISA, .write_b = 3, .write_w = 3, .write_l = 6, .read_b = 5, .read_w = 5, .read_l = 10 };
video_timings_t timing_tvga9000 = { .type = VIDEO_ISA, .write_b = 7, .write_w = 7, .write_l = 12, .read_b = 7, .read_w = 7, .read_l = 12 };
static uint8_t crtc_mask[0x40] = {
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
0x7f, 0xff, 0x3f, 0x7f, 0xff, 0xff, 0xff, 0xff,
0xff, 0xff, 0xff, 0xff, 0x7f, 0xff, 0xff, 0xef,
0xff, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0xff,
0x7f, 0x00, 0x00, 0x2f, 0x00, 0x00, 0x00, 0x03,
0x00, 0x13, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
};
static void tvga_recalcbanking(tvga_t *tvga);
void
tvga_out(uint16_t addr, uint8_t val, void *priv)
{
tvga_t *tvga = (tvga_t *) priv;
svga_t *svga = &tvga->svga;
uint8_t old;
if (((addr & 0xFFF0) == 0x3D0 || (addr & 0xFFF0) == 0x3B0) && !(svga->miscout & 1))
addr ^= 0x60;
switch (addr) {
case 0x3C5:
switch (svga->seqaddr & 0xf) {
case 0xB:
tvga->oldmode = 1;
break;
case 0xC:
if (svga->seqregs[0xe] & 0x80)
svga->seqregs[0xc] = val;
break;
case 0xd:
if (tvga->oldmode)
tvga->oldctrl2 = val;
else {
tvga->newctrl2 = val;
svga_recalctimings(svga);
}
break;
case 0xE:
if (tvga->oldmode)
tvga->oldctrl1 = val;
else {
svga->seqregs[0xe] = val ^ 2;
tvga->tvga_3d8 = svga->seqregs[0xe] & 0xf;
tvga_recalcbanking(tvga);
}
return;
default:
break;
}
break;
case 0x3C6:
case 0x3C7:
case 0x3C8:
case 0x3C9:
if (tvga->card_id != TVGA9000B_ID) {
tkd8001_ramdac_out(addr, val, svga->ramdac, svga);
return;
}
break;
case 0x3CF:
switch (svga->gdcaddr & 15) {
case 0x6:
old = svga->gdcreg[6];
svga_out(addr, val, svga);
if ((old & 0xc) != 0 && (val & 0xc) == 0) {
/*override mask - TVGA supports linear 128k at A0000*/
svga->banked_mask = 0x1ffff;
}
return;
case 0xE:
svga->gdcreg[0xe] = val ^ 2;
tvga->tvga_3d9 = svga->gdcreg[0xe] & 0xf;
tvga_recalcbanking(tvga);
break;
case 0xF:
svga->gdcreg[0xf] = val;
tvga_recalcbanking(tvga);
break;
default:
break;
}
break;
case 0x3D4:
svga->crtcreg = val & 0x3f;
return;
case 0x3D5:
if ((svga->crtcreg < 7) && (svga->crtc[0x11] & 0x80))
return;
if ((svga->crtcreg == 7) && (svga->crtc[0x11] & 0x80))
val = (svga->crtc[7] & ~0x10) | (val & 0x10);
old = svga->crtc[svga->crtcreg];
val &= crtc_mask[svga->crtcreg];
svga->crtc[svga->crtcreg] = val;
if (old != val) {
if (svga->crtcreg < 0xe || svga->crtcreg > 0x10) {
if ((svga->crtcreg == 0xc) || (svga->crtcreg == 0xd)) {
svga->fullchange = 3;
svga->ma_latch = ((svga->crtc[0xc] << 8) | svga->crtc[0xd]) + ((svga->crtc[8] & 0x60) >> 5);
} else {
svga->fullchange = changeframecount;
svga_recalctimings(svga);
}
}
}
switch (svga->crtcreg) {
case 0x1e:
svga->vram_display_mask = (val & 0x80) ? tvga->vram_mask : 0x3ffff;
break;
default:
break;
}
return;
case 0x3D8:
if (svga->gdcreg[0xf] & 4) {
tvga->tvga_3d8 = val;
tvga_recalcbanking(tvga);
}
return;
case 0x3D9:
if (svga->gdcreg[0xf] & 4) {
tvga->tvga_3d9 = val;
tvga_recalcbanking(tvga);
}
return;
case 0x3DB:
if (tvga->card_id != TVGA9000B_ID) {
/*3db appears to be a 4 bit clock select register on 8900D*/
svga->miscout = (svga->miscout & ~0x0c) | ((val & 3) << 2);
tvga->newctrl2 = (tvga->newctrl2 & ~0x01) | ((val & 4) >> 2);
tvga->oldctrl1 = (tvga->oldctrl1 & ~0x10) | ((val & 8) << 1);
svga_recalctimings(svga);
}
break;
default:
break;
}
svga_out(addr, val, svga);
}
uint8_t
tvga_in(uint16_t addr, void *priv)
{
tvga_t *tvga = (tvga_t *) priv;
svga_t *svga = &tvga->svga;
if (((addr & 0xFFF0) == 0x3D0 || (addr & 0xFFF0) == 0x3B0) && !(svga->miscout & 1))
addr ^= 0x60;
switch (addr) {
case 0x3C5:
if ((svga->seqaddr & 0xf) == 0xb) {
tvga->oldmode = 0;
return tvga->card_id; /*Must be at least a TVGA8900*/
}
if ((svga->seqaddr & 0xf) == 0xd) {
if (tvga->oldmode)
return tvga->oldctrl2;
return tvga->newctrl2;
}
if ((svga->seqaddr & 0xf) == 0xe) {
if (tvga->oldmode)
return tvga->oldctrl1;
}
break;
case 0x3C6:
case 0x3C7:
case 0x3C8:
case 0x3C9:
if (tvga->card_id != TVGA9000B_ID) {
return tkd8001_ramdac_in(addr, svga->ramdac, svga);
}
break;
case 0x3D4:
return svga->crtcreg;
case 0x3D5:
if (svga->crtcreg > 0x18 && svga->crtcreg < 0x1e)
return 0xff;
return svga->crtc[svga->crtcreg];
case 0x3d8:
return tvga->tvga_3d8;
case 0x3d9:
return tvga->tvga_3d9;
default:
break;
}
return svga_in(addr, svga);
}
static void
tvga_recalcbanking(tvga_t *tvga)
{
svga_t *svga = &tvga->svga;
svga->write_bank = (tvga->tvga_3d8 & 0x1f) * 65536;
if (svga->gdcreg[0xf] & 1)
svga->read_bank = (tvga->tvga_3d9 & 0x1f) * 65536;
else
svga->read_bank = svga->write_bank;
}
void
tvga_recalctimings(svga_t *svga)
{
const tvga_t *tvga = (tvga_t *) svga->priv;
int clksel;
int high_res_256 = 0;
if (!svga->rowoffset)
svga->rowoffset = 0x100; /*This is the only sensible way I can see this being handled,
given that TVGA8900D has no overflow bits.
Some sort of overflow is required for 320x200x24 and 1024x768x16*/
if (svga->crtc[0x29] & 0x10)
svga->rowoffset += 0x100;
if (svga->bpp == 24)
svga->hdisp = (svga->crtc[1] + 1) * 8;
if ((svga->crtc[0x1e] & 0xA0) == 0xA0)
svga->ma_latch |= 0x10000;
if ((svga->crtc[0x27] & 0x01) == 0x01)
svga->ma_latch |= 0x20000;
if ((svga->crtc[0x27] & 0x02) == 0x02)
svga->ma_latch |= 0x40000;
if (tvga->oldctrl2 & 0x10) {
svga->rowoffset <<= 1;
svga->ma_latch <<= 1;
}
if (svga->gdcreg[0xf] & 0x08) {
svga->htotal *= 2;
svga->hdisp *= 2;
svga->hdisp_time *= 2;
}
svga->interlace = (svga->crtc[0x1e] & 4);
if (svga->interlace)
svga->rowoffset >>= 1;
if (tvga->card_id == TVGA8900CLD_ID)
clksel = ((svga->miscout >> 2) & 3) | ((tvga->newctrl2 & 0x01) << 2) | ((tvga->oldctrl1 & 0x10) >> 1);
else
clksel = ((svga->miscout >> 2) & 3) | ((tvga->newctrl2 & 0x01) << 2) | ((tvga->newctrl2 & 0x40) >> 3);
switch (clksel) {
case 0x2:
svga->clock = (cpuclock * (double) (1ULL << 32)) / 44900000.0;
break;
case 0x3:
svga->clock = (cpuclock * (double) (1ULL << 32)) / 36000000.0;
break;
case 0x4:
svga->clock = (cpuclock * (double) (1ULL << 32)) / 57272000.0;
break;
case 0x5:
svga->clock = (cpuclock * (double) (1ULL << 32)) / 65000000.0;
break;
case 0x6:
svga->clock = (cpuclock * (double) (1ULL << 32)) / 50350000.0;
break;
case 0x7:
svga->clock = (cpuclock * (double) (1ULL << 32)) / 40000000.0;
break;
case 0x8:
svga->clock = (cpuclock * (double) (1ULL << 32)) / 88000000.0;
break;
case 0x9:
svga->clock = (cpuclock * (double) (1ULL << 32)) / 98000000.0;
break;
case 0xa:
svga->clock = (cpuclock * (double) (1ULL << 32)) / 118800000.0;
break;
case 0xb:
svga->clock = (cpuclock * (double) (1ULL << 32)) / 108000000.0;
break;
case 0xc:
svga->clock = (cpuclock * (double) (1ULL << 32)) / 72000000.0;
break;
case 0xd:
svga->clock = (cpuclock * (double) (1ULL << 32)) / 77000000.0;
break;
case 0xe:
svga->clock = (cpuclock * (double) (1ULL << 32)) / 80000000.0;
break;
case 0xf:
svga->clock = (cpuclock * (double) (1ULL << 32)) / 75000000.0;
break;
default:
break;
}
if (tvga->card_id != TVGA8900CLD_ID) {
/*TVGA9000 doesn't seem to have support for a 'high res' 256 colour mode
(without the VGA pixel doubling). Instead it implements these modes by
doubling the horizontal pixel count and pixel clock. Hence we use a
basic heuristic to detect this*/
if (svga->interlace)
high_res_256 = (svga->htotal * 8) > (svga->vtotal * 4);
else
high_res_256 = (svga->htotal * 8) > (svga->vtotal * 2);
}
if ((tvga->oldctrl2 & 0x10) || high_res_256) {
if (high_res_256)
svga->hdisp /= 2;
switch (svga->bpp) {
case 8:
svga->render = svga_render_8bpp_highres;
break;
case 15:
svga->render = svga_render_15bpp_highres;
svga->hdisp /= 2;
break;
case 16:
svga->render = svga_render_16bpp_highres;
svga->hdisp /= 2;
break;
case 24:
svga->render = svga_render_24bpp_highres;
svga->hdisp /= 3;
break;
default:
break;
}
svga->lowres = 0;
}
}
static void *
tvga_init(const device_t *info)
{
const char *bios_fn;
tvga_t *tvga = malloc(sizeof(tvga_t));
memset(tvga, 0, sizeof(tvga_t));
tvga->card_id = info->local & 0xFF;
if (tvga->card_id == TVGA9000B_ID) {
video_inform(VIDEO_FLAG_TYPE_SPECIAL, &timing_tvga9000);
tvga->vram_size = 512 << 10;
} else {
if (info->local & 0x0100)
video_inform(VIDEO_FLAG_TYPE_SPECIAL, &timing_tvga8900dr);
else
video_inform(VIDEO_FLAG_TYPE_SPECIAL, &timing_tvga8900);
tvga->vram_size = device_get_config_int("memory") << 10;
}
tvga->vram_mask = tvga->vram_size - 1;
switch (tvga->card_id) {
case TVGA8900B_ID:
bios_fn = ROM_TVGA_8900B;
break;
case TVGA8900CLD_ID:
if (info->local & 0x0100)
bios_fn = ROM_TVGA_8900DR;
else
bios_fn = ROM_TVGA_8900CLD;
break;
case TVGA9000B_ID:
bios_fn = (info->local & 0x100) ? ROM_TVGA_9000B_NEC_SV9000 : ROM_TVGA_9000B;
break;
default:
free(tvga);
return NULL;
}
rom_init(&tvga->bios_rom, bios_fn, 0xc0000, 0x8000, 0x7fff, 0, MEM_MAPPING_EXTERNAL);
svga_init(info, &tvga->svga, tvga, tvga->vram_size,
tvga_recalctimings,
tvga_in, tvga_out,
NULL,
NULL);
if (tvga->card_id != TVGA9000B_ID)
tvga->svga.ramdac = device_add(&tkd8001_ramdac_device);
io_sethandler(0x03c0, 0x0020, tvga_in, NULL, NULL, tvga_out, NULL, NULL, tvga);
return tvga;
}
static int
tvga8900b_available(void)
{
return rom_present(ROM_TVGA_8900B);
}
static int
tvga8900d_available(void)
{
return rom_present(ROM_TVGA_8900CLD);
}
static int
tvga8900dr_available(void)
{
return rom_present(ROM_TVGA_8900DR);
}
static int
tvga9000b_available(void)
{
return rom_present(ROM_TVGA_9000B);
}
static int
tvga9000b_nec_sv9000_available(void)
{
return rom_present(ROM_TVGA_9000B_NEC_SV9000);
}
void
tvga_close(void *priv)
{
tvga_t *tvga = (tvga_t *) priv;
svga_close(&tvga->svga);
free(tvga);
}
void
tvga_speed_changed(void *priv)
{
tvga_t *tvga = (tvga_t *) priv;
svga_recalctimings(&tvga->svga);
}
void
tvga_force_redraw(void *priv)
{
tvga_t *tvga = (tvga_t *) priv;
tvga->svga.fullchange = changeframecount;
}
static const device_config_t tvga_config[] = {
// clang-format off
{
.name = "memory",
.description = "Memory size",
.type = CONFIG_SELECTION,
.default_int = 1024,
.selection = {
{
.description = "256 kB",
.value = 256
},
{
.description = "512 kB",
.value = 512
},
{
.description = "1 MB",
.value = 1024
},
/*Chip supports 2mb, but drivers are buggy*/
{
.description = ""
}
}
},
{
.type = CONFIG_END
}
// clang-format off
};
const device_t tvga8900b_device = {
.name = "Trident TVGA 8900B",
.internal_name = "tvga8900b",
.flags = DEVICE_ISA,
.local = TVGA8900B_ID,
.init = tvga_init,
.close = tvga_close,
.reset = NULL,
{ .available = tvga8900b_available },
.speed_changed = tvga_speed_changed,
.force_redraw = tvga_force_redraw,
.config = tvga_config
};
const device_t tvga8900d_device = {
.name = "Trident TVGA 8900D",
.internal_name = "tvga8900d",
.flags = DEVICE_ISA,
.local = TVGA8900CLD_ID,
.init = tvga_init,
.close = tvga_close,
.reset = NULL,
{ .available = tvga8900d_available },
.speed_changed = tvga_speed_changed,
.force_redraw = tvga_force_redraw,
.config = tvga_config
};
const device_t tvga8900dr_device = {
.name = "Trident TVGA 8900D-R",
.internal_name = "tvga8900dr",
.flags = DEVICE_ISA,
.local = TVGA8900CLD_ID | 0x0100,
.init = tvga_init,
.close = tvga_close,
.reset = NULL,
{ .available = tvga8900dr_available },
.speed_changed = tvga_speed_changed,
.force_redraw = tvga_force_redraw,
.config = tvga_config
};
const device_t tvga9000b_device = {
.name = "Trident TVGA 9000B",
.internal_name = "tvga9000b",
.flags = DEVICE_ISA,
.local = TVGA9000B_ID,
.init = tvga_init,
.close = tvga_close,
.reset = NULL,
{ .available = tvga9000b_available },
.speed_changed = tvga_speed_changed,
.force_redraw = tvga_force_redraw,
.config = NULL
};
const device_t nec_sv9000_device = {
.name = "NEC SV9000 (Trident TVGA 9000B)",
.internal_name = "nec_sv9000",
.flags = DEVICE_ISA,
.local = TVGA9000B_ID | 0x100,
.init = tvga_init,
.close = tvga_close,
.reset = NULL,
{ .available = tvga9000b_nec_sv9000_available },
.speed_changed = tvga_speed_changed,
.force_redraw = tvga_force_redraw,
.config = NULL
};
``` | /content/code_sandbox/src/video/vid_tvga.c | c | 2016-06-25T22:29:10 | 2024-08-16T19:09:21 | 86Box | 86Box/86Box | 2,616 | 5,982 |
```c
/*
* 86Box A hypervisor and IBM PC system emulator that specializes in
* running old operating systems and software designed for IBM
* PC systems and compatibles from 1981 through fairly recent
* system designs based on the PCI bus.
*
* This file is part of the 86Box distribution.
*
* Oak OTI037C/67/077 emulation.
*
*
*
* Authors: Sarah Walker, <path_to_url
* Miran Grca, <mgrca8@gmail.com>
*
*/
#include <stdint.h>
#include <stdlib.h>
#include <string.h>
#include <wchar.h>
#include <86box/86box.h>
#include <86box/io.h>
#include <86box/timer.h>
#include <86box/mem.h>
#include <86box/rom.h>
#include <86box/device.h>
#include <86box/video.h>
#include <86box/vid_svga.h>
#include <86box/vid_svga_render.h>
#include <86box/plat_unused.h>
#define BIOS_037C_PATH "roms/video/oti/bios.bin"
#define BIOS_067_AMA932J_PATH "roms/machines/ama932j/OTI067.BIN"
#define BIOS_067_M300_08_PATH "roms/machines/m30008/EVC_BIOS.ROM"
#define BIOS_067_M300_15_PATH "roms/machines/m30015/EVC_BIOS.ROM"
#define BIOS_077_PATH "roms/video/oti/oti077.vbi"
#define BIOS_077_ACER100T_PATH "roms/machines/acer100t/oti077_acer100t.BIN"
enum {
OTI_037C = 0,
OTI_067 = 2,
OTI_067_AMA932J = 3,
OTI_067_M300 = 4,
OTI_077 = 5,
OTI_077_ACER100T = 6
};
typedef struct {
svga_t svga;
rom_t bios_rom;
int index;
uint8_t regs[32];
uint8_t chip_id;
uint8_t pos;
uint8_t enable_register;
uint8_t dipswitch_val;
uint32_t vram_size;
uint32_t vram_mask;
} oti_t;
static video_timings_t timing_oti = { .type = VIDEO_ISA, .write_b = 6, .write_w = 8, .write_l = 16, .read_b = 6, .read_w = 8, .read_l = 16 };
static void
oti_out(uint16_t addr, uint8_t val, void *priv)
{
oti_t *oti = (oti_t *) priv;
svga_t *svga = &oti->svga;
uint8_t old;
uint8_t idx;
uint8_t enable;
if (!oti->chip_id && !(oti->enable_register & 1) && (addr != 0x3C3))
return;
if ((((addr & 0xFFF0) == 0x3D0 || (addr & 0xFFF0) == 0x3B0) && addr < 0x3de) && !(svga->miscout & 1))
addr ^= 0x60;
switch (addr) {
case 0x3C3:
if (!oti->chip_id) {
oti->enable_register = val & 1;
return;
}
svga_out(addr, val, svga);
return;
case 0x3c6:
case 0x3c7:
case 0x3c8:
case 0x3c9:
if (oti->chip_id == OTI_077 || oti->chip_id == OTI_077_ACER100T)
sc1148x_ramdac_out(addr, 0, val, svga->ramdac, svga);
else
svga_out(addr, val, svga);
return;
case 0x3D4:
if (oti->chip_id)
svga->crtcreg = val & 0x3f;
else
svga->crtcreg = val; /* FIXME: The BIOS wants to set the test bit? */
return;
case 0x3D5:
if (oti->chip_id && (svga->crtcreg & 0x20))
return;
idx = svga->crtcreg;
if (!oti->chip_id)
idx &= 0x1f;
if ((idx < 7) && (svga->crtc[0x11] & 0x80))
return;
if ((idx == 7) && (svga->crtc[0x11] & 0x80))
val = (svga->crtc[7] & ~0x10) | (val & 0x10);
old = svga->crtc[idx];
svga->crtc[idx] = val;
if (old != val) {
if ((idx < 0x0e) || (idx > 0x10)) {
if (idx == 0x0c || idx == 0x0d) {
svga->fullchange = 3;
svga->ma_latch = ((svga->crtc[0xc] << 8) | svga->crtc[0xd]) + ((svga->crtc[8] & 0x60) >> 5);
} else {
svga->fullchange = changeframecount;
svga_recalctimings(svga);
}
}
}
break;
case 0x3DE:
if (oti->chip_id)
oti->index = val & 0x1f;
else
oti->index = val;
return;
case 0x3DF:
idx = oti->index;
if (!oti->chip_id)
idx &= 0x1f;
oti->regs[idx] = val;
switch (idx) {
case 0xD:
if (oti->chip_id == OTI_067) {
svga->vram_display_mask = (val & 0x0c) ? oti->vram_mask : 0x3ffff;
if (!(val & 0x80))
svga->vram_display_mask = 0x3ffff;
if ((val & 0x80) && oti->vram_size == 256)
mem_mapping_disable(&svga->mapping);
else
mem_mapping_enable(&svga->mapping);
} else if (oti->chip_id == OTI_077 || oti->chip_id == OTI_077_ACER100T) {
svga->vram_display_mask = (val & 0x0c) ? oti->vram_mask : 0x3ffff;
switch ((val & 0xc0) >> 6) {
default:
case 0x00: /* 256 kB of memory */
enable = (oti->vram_size >= 256);
if (val & 0x0c)
svga->vram_display_mask = MIN(oti->vram_mask, 0x3ffff);
break;
case 0x01: /* 1 MB of memory */
case 0x03:
enable = (oti->vram_size >= 1024);
if (val & 0x0c)
svga->vram_display_mask = MIN(oti->vram_mask, 0xfffff);
break;
case 0x02: /* 512 kB of memory */
enable = (oti->vram_size >= 512);
if (val & 0x0c)
svga->vram_display_mask = MIN(oti->vram_mask, 0x7ffff);
break;
}
if (enable)
mem_mapping_enable(&svga->mapping);
else
mem_mapping_disable(&svga->mapping);
} else {
if (val & 0x80)
mem_mapping_disable(&svga->mapping);
else
mem_mapping_enable(&svga->mapping);
}
break;
case 0x11:
svga->read_bank = (val & 0xf) * 65536;
svga->write_bank = (val >> 4) * 65536;
break;
default:
break;
}
return;
default:
break;
}
svga_out(addr, val, svga);
}
static uint8_t
oti_in(uint16_t addr, void *priv)
{
oti_t *oti = (oti_t *) priv;
svga_t *svga = &oti->svga;
uint8_t idx;
uint8_t temp;
if (!oti->chip_id && !(oti->enable_register & 1) && (addr != 0x3C3))
return 0xff;
if ((((addr & 0xFFF0) == 0x3D0 || (addr & 0xFFF0) == 0x3B0) && addr < 0x3de) && !(svga->miscout & 1))
addr ^= 0x60;
switch (addr) {
case 0x3C2:
if ((svga->vgapal[0].r + svga->vgapal[0].g + svga->vgapal[0].b) >= 0x50)
temp = 0;
else
temp = 0x10;
break;
case 0x3C3:
if (oti->chip_id)
temp = svga_in(addr, svga);
else
temp = oti->enable_register;
break;
case 0x3c6:
case 0x3c7:
case 0x3c8:
case 0x3c9:
if (oti->chip_id == OTI_077 || oti->chip_id == OTI_077_ACER100T)
return sc1148x_ramdac_in(addr, 0, svga->ramdac, svga);
return svga_in(addr, svga);
case 0x3CF:
return svga->gdcreg[svga->gdcaddr & 0xf];
case 0x3D4:
temp = svga->crtcreg;
break;
case 0x3D5:
if (oti->chip_id) {
if (svga->crtcreg & 0x20)
temp = 0xff;
else
temp = svga->crtc[svga->crtcreg];
} else
temp = svga->crtc[svga->crtcreg & 0x1f];
break;
case 0x3DA:
if (oti->chip_id) {
temp = svga_in(addr, svga);
break;
}
svga->attrff = 0;
/*The OTI-037C BIOS waits for bits 0 and 3 in 0x3da to go low, then reads 0x3da again
and expects the diagnostic bits to equal the current border colour. As I understand
it, the 0x3da active enable status does not include the border time, so this may be
an area where OTI-037C is not entirely VGA compatible.*/
svga->cgastat &= ~0x30;
/* copy color diagnostic info from the overscan color register */
switch (svga->attrregs[0x12] & 0x30) {
case 0x00: /* P0 and P2 */
if (svga->attrregs[0x11] & 0x01)
svga->cgastat |= 0x10;
if (svga->attrregs[0x11] & 0x04)
svga->cgastat |= 0x20;
break;
case 0x10: /* P4 and P5 */
if (svga->attrregs[0x11] & 0x10)
svga->cgastat |= 0x10;
if (svga->attrregs[0x11] & 0x20)
svga->cgastat |= 0x20;
break;
case 0x20: /* P1 and P3 */
if (svga->attrregs[0x11] & 0x02)
svga->cgastat |= 0x10;
if (svga->attrregs[0x11] & 0x08)
svga->cgastat |= 0x20;
break;
case 0x30: /* P6 and P7 */
if (svga->attrregs[0x11] & 0x40)
svga->cgastat |= 0x10;
if (svga->attrregs[0x11] & 0x80)
svga->cgastat |= 0x20;
break;
default:
break;
}
temp = svga->cgastat;
break;
case 0x3DE:
temp = oti->index;
if (oti->chip_id)
temp |= (oti->chip_id << 5);
break;
case 0x3DF:
idx = oti->index;
if (!oti->chip_id)
idx &= 0x1f;
if (idx == 0x10)
temp = oti->dipswitch_val;
else
temp = oti->regs[idx];
break;
default:
temp = svga_in(addr, svga);
break;
}
return temp;
}
static void
oti_pos_out(UNUSED(uint16_t addr), uint8_t val, void *priv)
{
oti_t *oti = (oti_t *) priv;
if ((val ^ oti->pos) & 8) {
if (val & 8)
io_sethandler(0x03c0, 32, oti_in, NULL, NULL,
oti_out, NULL, NULL, oti);
else
io_removehandler(0x03c0, 32, oti_in, NULL, NULL,
oti_out, NULL, NULL, oti);
}
oti->pos = val;
}
static uint8_t
oti_pos_in(UNUSED(uint16_t addr), void *priv)
{
const oti_t *oti = (oti_t *) priv;
return (oti->pos);
}
static float
oti_getclock(int clock)
{
float ret = 0.0;
switch (clock) {
default:
case 0:
ret = 25175000.0;
break;
case 1:
ret = 28322000.0;
break;
case 4:
ret = 14318000.0;
break;
case 5:
ret = 16257000.0;
break;
case 7:
ret = 35500000.0;
break;
}
return ret;
}
static void
oti_recalctimings(svga_t *svga)
{
const oti_t *oti = (oti_t *) svga->priv;
int clk_sel = ((svga->miscout >> 2) & 3) | ((oti->regs[0x0d] & 0x20) >> 3);
svga->clock = (cpuclock * (double) (1ULL << 32)) / oti_getclock(clk_sel);
if (oti->chip_id > 0) {
if (oti->regs[0x14] & 0x08)
svga->ma_latch |= 0x10000;
if (oti->regs[0x16] & 0x08)
svga->ma_latch |= 0x20000;
if (oti->regs[0x14] & 0x01)
svga->vtotal += 0x400;
if (oti->regs[0x14] & 0x02)
svga->dispend += 0x400;
if (oti->regs[0x14] & 0x04)
svga->vsyncstart += 0x400;
svga->interlace = oti->regs[0x14] & 0x80;
}
if ((oti->regs[0x0d] & 0x0c) && !(oti->regs[0x0d] & 0x10))
svga->rowoffset <<= 1;
if (svga->bpp == 16) {
svga->render = svga_render_16bpp_highres;
svga->hdisp >>= 1;
} else if (svga->bpp == 15) {
svga->render = svga_render_15bpp_highres;
svga->hdisp >>= 1;
}
}
static void *
oti_init(const device_t *info)
{
oti_t *oti = malloc(sizeof(oti_t));
const char *romfn = NULL;
memset(oti, 0x00, sizeof(oti_t));
oti->chip_id = info->local;
oti->dipswitch_val = 0x18;
switch (oti->chip_id) {
case OTI_037C:
romfn = BIOS_037C_PATH;
oti->vram_size = 256;
oti->regs[0] = 0x08; /* FIXME: The BIOS wants to read this at index 0? This index is undocumented. */
#if 0
io_sethandler(0x03c0, 32,
oti_in, NULL, NULL, oti_out, NULL, NULL, oti);
#endif
break;
case OTI_067_AMA932J:
romfn = BIOS_067_AMA932J_PATH;
oti->chip_id = 2;
oti->vram_size = device_get_config_int("memory");
oti->dipswitch_val |= 0x20;
oti->pos = 0x08; /* Tell the BIOS the I/O ports are already enabled to avoid a double I/O handler mess. */
io_sethandler(0x46e8, 1, oti_pos_in, NULL, NULL, oti_pos_out, NULL, NULL, oti);
break;
case OTI_067_M300:
if (rom_present(BIOS_067_M300_15_PATH))
romfn = BIOS_067_M300_15_PATH;
else
romfn = BIOS_067_M300_08_PATH;
oti->vram_size = device_get_config_int("memory");
oti->pos = 0x08; /* Tell the BIOS the I/O ports are already enabled to avoid a double I/O handler mess. */
io_sethandler(0x46e8, 1, oti_pos_in, NULL, NULL, oti_pos_out, NULL, NULL, oti);
break;
case OTI_067:
case OTI_077:
romfn = BIOS_077_PATH;
oti->vram_size = device_get_config_int("memory");
oti->pos = 0x08; /* Tell the BIOS the I/O ports are already enabled to avoid a double I/O handler mess. */
io_sethandler(0x46e8, 1, oti_pos_in, NULL, NULL, oti_pos_out, NULL, NULL, oti);
break;
case OTI_077_ACER100T:
romfn = BIOS_077_ACER100T_PATH;
oti->vram_size = device_get_config_int("memory");
oti->pos = 0x08; /* Tell the BIOS the I/O ports are already enabled to avoid a double I/O handler mess. */
io_sethandler(0x46e8, 1, oti_pos_in, NULL, NULL, oti_pos_out, NULL, NULL, oti);
break;
default:
break;
}
if (romfn != NULL) {
rom_init(&oti->bios_rom, romfn,
0xc0000, 0x8000, 0x7fff, 0, MEM_MAPPING_EXTERNAL);
}
oti->vram_mask = (oti->vram_size << 10) - 1;
if (oti->chip_id == OTI_077_ACER100T){
/* josephillips: Required to show all BIOS
information on Acer 100T only
*/
video_inform(0x1,&timing_oti);
}else{
video_inform(VIDEO_FLAG_TYPE_SPECIAL, &timing_oti);
}
svga_init(info, &oti->svga, oti, oti->vram_size << 10,
oti_recalctimings, oti_in, oti_out, NULL, NULL);
if (oti->chip_id == OTI_077 || oti->chip_id == OTI_077_ACER100T)
oti->svga.ramdac = device_add(&sc11487_ramdac_device); /*Actually a 82c487, probably a clone.*/
io_sethandler(0x03c0, 32,
oti_in, NULL, NULL, oti_out, NULL, NULL, oti);
oti->svga.miscout = 1;
oti->svga.packed_chain4 = 1;
return oti;
}
static void
oti_close(void *priv)
{
oti_t *oti = (oti_t *) priv;
svga_close(&oti->svga);
free(oti);
}
static void
oti_speed_changed(void *priv)
{
oti_t *oti = (oti_t *) priv;
svga_recalctimings(&oti->svga);
}
static void
oti_force_redraw(void *priv)
{
oti_t *oti = (oti_t *) priv;
oti->svga.fullchange = changeframecount;
}
static int
oti037c_available(void)
{
return (rom_present(BIOS_037C_PATH));
}
static int
oti067_ama932j_available(void)
{
return (rom_present(BIOS_067_AMA932J_PATH));
}
static int
oti077_acer100t_available(void)
{
return (rom_present(BIOS_077_ACER100T_PATH));
}
static int
oti067_077_available(void)
{
return (rom_present(BIOS_077_PATH));
}
static int
oti067_m300_available(void)
{
if (rom_present(BIOS_067_M300_15_PATH))
return (rom_present(BIOS_067_M300_15_PATH));
else
return (rom_present(BIOS_067_M300_08_PATH));
}
// clang-format off
static const device_config_t oti067_config[] = {
{
.name = "memory",
.description = "Memory size",
.type = CONFIG_SELECTION,
.default_int = 512,
.selection = {
{
.description = "256 kB",
.value = 256
},
{
.description = "512 kB",
.value = 512
},
{
.description = ""
}
}
},
{
.type = CONFIG_END
}
};
static const device_config_t oti067_ama932j_config[] = {
{
.name = "memory",
.description = "Memory size",
.type = CONFIG_SELECTION,
.default_int = 256,
.selection = {
{
.description = "256 kB",
.value = 256
},
{
.description = "512 kB",
.value = 512
},
{
.description = ""
}
}
},
{
.type = CONFIG_END
}
};
static const device_config_t oti077_acer100t_config[] = {
{
.name = "memory",
.description = "Memory size",
.type = CONFIG_SELECTION,
.default_int = 512,
.selection = {
{
.description = "256 kB",
.value = 256
},
{
.description = "512 kB",
.value = 512
},
{
.description = "1 MB",
.value = 1024
},
{
.description = ""
}
}
},
{
.type = CONFIG_END
}
};
static const device_config_t oti077_config[] = {
{
.name = "memory",
.description = "Memory size",
.type = CONFIG_SELECTION,
.default_int = 1024,
.selection = {
{
.description = "256 kB",
.value = 256
},
{
.description = "512 kB",
.value = 512
},
{
.description = "1 MB",
.value = 1024
},
{
.description = ""
}
}
},
{
.type = CONFIG_END
}
};
// clang-format on
const device_t oti037c_device = {
.name = "Oak OTI-037C",
.internal_name = "oti037c",
.flags = DEVICE_ISA,
.local = 0,
.init = oti_init,
.close = oti_close,
.reset = NULL,
{ .available = oti037c_available },
.speed_changed = oti_speed_changed,
.force_redraw = oti_force_redraw,
.config = NULL
};
const device_t oti067_device = {
.name = "Oak OTI-067",
.internal_name = "oti067",
.flags = DEVICE_ISA,
.local = 2,
.init = oti_init,
.close = oti_close,
.reset = NULL,
{ .available = oti067_077_available },
.speed_changed = oti_speed_changed,
.force_redraw = oti_force_redraw,
.config = oti067_config
};
const device_t oti067_m300_device = {
.name = "Oak OTI-067 (Olivetti M300-08/15)",
.internal_name = "oti067_m300",
.flags = DEVICE_ISA,
.local = 4,
.init = oti_init,
.close = oti_close,
.reset = NULL,
{ .available = oti067_m300_available },
.speed_changed = oti_speed_changed,
.force_redraw = oti_force_redraw,
.config = oti067_config
};
const device_t oti067_ama932j_device = {
.name = "Oak OTI-067 (AMA-932J)",
.internal_name = "oti067_ama932j",
.flags = DEVICE_ISA,
.local = 3,
.init = oti_init,
.close = oti_close,
.reset = NULL,
{ .available = oti067_ama932j_available },
.speed_changed = oti_speed_changed,
.force_redraw = oti_force_redraw,
.config = oti067_ama932j_config
};
const device_t oti077_acer100t_device = {
.name = "Oak OTI-077 (Acer 100T)",
.internal_name = "oti077_acer100t",
.flags = DEVICE_ISA,
.local = 6,
.init = oti_init,
.close = oti_close,
.reset = NULL,
{ .available = oti077_acer100t_available },
.speed_changed = oti_speed_changed,
.force_redraw = oti_force_redraw,
.config = oti077_acer100t_config
};
const device_t oti077_device = {
.name = "Oak OTI-077",
.internal_name = "oti077",
.flags = DEVICE_ISA,
.local = 5,
.init = oti_init,
.close = oti_close,
.reset = NULL,
{ .available = oti067_077_available },
.speed_changed = oti_speed_changed,
.force_redraw = oti_force_redraw,
.config = oti077_config
};
``` | /content/code_sandbox/src/video/vid_oak_oti.c | c | 2016-06-25T22:29:10 | 2024-08-16T19:09:21 | 86Box | 86Box/86Box | 2,616 | 6,375 |
```c
/*
* 86Box A hypervisor and IBM PC system emulator that specializes in
* running old operating systems and software designed for IBM
* PC systems and compatibles from 1981 through fairly recent
* system designs based on the PCI bus.
*
* This file is part of the 86Box distribution.
*
* This implements just enough of the Professional Graphics
* Controller to act as a basis for the Vermont Microsystems
* IM-1024.
*
* PGC features implemented include:
* > The CGA-compatible display modes
* > Switching to and from native mode
* > Communicating with the host PC
*
* Numerous features are implemented partially or not at all,
* such as:
* > 2D drawing
* > 3D drawing
* > Command lists
* Some of these are marked TODO.
*
* The PGC has two display modes: CGA (in which it appears in
* the normal CGA memory and I/O ranges) and native (in which
* all functions are accessed through reads and writes to 1K
* of memory at 0xC6000).
*
* The PGC's 8088 processor monitors this buffer and executes
* instructions left there for it. We simulate this behavior
* with a separate thread.
*
* **NOTE** This driver is not finished yet:
*
* - cursor will blink at very high speed if used on a machine
* with clock greater than 4.77MHz. We should "scale down"
* this speed, to become relative to a 4.77MHz-based system.
*
* - pgc_plot() should be overloaded by clones if they support
* modes other than WRITE and INVERT, like the IM-1024.
*
* - test it with the Windows 1.x driver?
*
* This is expected to be done shortly.
*
*
*
* Authors: Fred N. van Kempen, <decwiz@yahoo.com>
* John Elliott, <jce@seasip.info>
*
*
* This program is free software; you can redistribute it and/or modify
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful, but
* WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
*
* along with this program; if not, write to the:
*
* Free Software Foundation, Inc.
* 59 Temple Place - Suite 330
* Boston, MA 02111-1307
* USA.
*/
#include <stdarg.h>
#include <stdio.h>
#include <stdint.h>
#include <string.h>
#include <stdlib.h>
#include <wchar.h>
#include <ctype.h>
#include <math.h>
#define HAVE_STDARG_H
#include <86box/86box.h>
#include <86box/io.h>
#include <86box/mem.h>
#include <86box/rom.h>
#include <86box/timer.h>
#include <86box/device.h>
#include <86box/pit.h>
#include <86box/plat.h>
#include <86box/thread.h>
#include <86box/video.h>
#include <86box/vid_cga.h>
#include <86box/vid_pgc.h>
#define PGC_CGA_WIDTH 640
#define PGC_CGA_HEIGHT 400
#define HWORD(u) ((u) >> 16)
#define LWORD(u) ((u) &0xffff)
#define WAKE_DELAY (TIMER_USEC * 500)
static const char *pgc_err_msgs[] = {
"Range \r",
"Integer \r",
"Memory \r",
"Overflow\r",
"Digit \r",
"Opcode \r",
"Running \r",
"Stack \r",
"Too long\r",
"Area \r",
"Missing \r",
"Unknown \r"
};
/* Initial palettes */
static const uint32_t init_palette[6][256] = {
#include <86box/vid_pgc_palette.h>
};
static video_timings_t timing_pgc = { .type = VIDEO_ISA, .write_b = 8, .write_w = 16, .write_l = 32, .read_b = 8, .read_w = 16, .read_l = 32 };
#ifdef ENABLE_PGC_LOG
int pgc_do_log = ENABLE_PGC_LOG;
static void
pgc_log(const char *fmt, ...)
{
va_list ap;
if (pgc_do_log) {
va_start(ap, fmt);
pclog_ex(fmt, ap);
va_end(ap);
}
}
#else
# define pgc_log(fmt, ...)
#endif
static inline int
is_whitespace(char ch)
{
return (ch != 0 && strchr(" \r\n\t,;()+-", ch) != NULL);
}
/*
* Write a byte to the output buffer.
*
* If buffer is full will sleep until it is not. Returns 0 if
* a PGC reset has been triggered by a write to 0xC63FF.
*/
static int
output_byte(pgc_t *dev, uint8_t val)
{
/* If output buffer full, wait for it to empty. */
while (!dev->stopped && dev->mapram[0x302] == (uint8_t) (dev->mapram[0x303] - 1)) {
pgc_log("PGC: output buffer state: %02x %02x Sleeping\n",
dev->mapram[0x302], dev->mapram[0x303]);
dev->waiting_output_fifo = 1;
pgc_sleep(dev);
}
if (dev->mapram[0x3ff]) {
/* Reset triggered. */
pgc_reset(dev);
return 0;
}
dev->mapram[0x100 + dev->mapram[0x302]] = val;
dev->mapram[0x302]++;
pgc_log("PGC: output %02x: new state: %02x %02x\n", val,
dev->mapram[0x302], dev->mapram[0x303]);
return 1;
}
/* Helper to write an entire string to the output buffer. */
static int
output_string(pgc_t *dev, const char *s)
{
while (*s) {
if (!output_byte(dev, *s))
return 0;
s++;
}
return 1;
}
/* As output_byte, for the error buffer. */
static int
error_byte(pgc_t *dev, uint8_t val)
{
/* If error buffer full, wait for it to empty. */
while (!dev->stopped && dev->mapram[0x304] == dev->mapram[0x305] - 1) {
dev->waiting_error_fifo = 1;
pgc_sleep(dev);
}
if (dev->mapram[0x3ff]) {
/* Reset triggered. */
pgc_reset(dev);
return 0;
}
dev->mapram[0x200 + dev->mapram[0x304]] = val;
dev->mapram[0x304]++;
return 1;
}
/* As output_string, for the error buffer. */
static int
error_string(pgc_t *dev, const char *s)
{
while (*s) {
if (!error_byte(dev, *s))
return 0;
s++;
}
return 1;
}
/*
* Read next byte from the input buffer.
*
* If no byte available will sleep until one is. Returns 0 if
* a PGC reset has been triggered by a write to 0xC63FF.
*/
static int
input_byte(pgc_t *dev, uint8_t *result)
{
/* If input buffer empty, wait for it to fill. */
while (!dev->stopped && (dev->mapram[0x300] == dev->mapram[0x301])) {
dev->waiting_input_fifo = 1;
pgc_sleep(dev);
}
if (dev->stopped)
return 0;
if (dev->mapram[0x3ff]) {
/* Reset triggered. */
pgc_reset(dev);
return 0;
}
*result = dev->mapram[dev->mapram[0x301]];
dev->mapram[0x301]++;
return 1;
}
/*
* Read a byte and interpret as ASCII.
*
* Ignore control characters other than CR, LF or tab.
*/
static int
input_char(pgc_t *dev, char *result)
{
uint8_t ch;
while (1) {
if (!dev->inputbyte(dev, &ch))
return 0;
ch &= 0x7f;
if (ch == '\r' || ch == '\n' || ch == '\t' || ch >= ' ') {
*result = toupper(ch);
return 1;
}
}
}
/*
* Read in the next command.
*
* This can be either as hex (1 byte) or ASCII (up to 6 characters).
*/
static int
read_command(pgc_t *dev)
{
if (dev->stopped)
return 0;
if (dev->clcur)
return pgc_clist_byte(dev, &dev->hex_command);
if (dev->ascii_mode) {
char ch;
int count = 0;
while (count < 7) {
if (dev->stopped)
return 0;
if (!input_char(dev, &ch))
return 0;
if (is_whitespace(ch)) {
/* Pad to 6 characters */
while (count < 6)
dev->asc_command[count++] = ' ';
dev->asc_command[6] = 0;
return 1;
}
dev->asc_command[count++] = toupper(ch);
}
return 1;
}
return dev->inputbyte(dev, &dev->hex_command);
}
/* Read in the next command and parse it. */
static int
parse_command(pgc_t *dev, const pgc_cmd_t **pcmd)
{
char match[7];
*pcmd = NULL;
dev->hex_command = 0;
memset(dev->asc_command, ' ', 6);
dev->asc_command[6] = 0;
if (!read_command(dev)) {
/* PGC has been reset. */
return 0;
}
/*
* Scan the list of valid commands.
*
* dev->commands may be a subclass list (terminated with '*')
* or the core list (terminated with '@')
*/
for (const pgc_cmd_t *cmd = dev->commands; cmd->ascii[0] != '@'; cmd++) {
/* End of subclass command list, chain to core. */
if (cmd->ascii[0] == '*')
cmd = dev->master;
/* If in ASCII mode match on the ASCII command. */
if (dev->ascii_mode && !dev->clcur) {
sprintf(match, "%-6.6s", cmd->ascii);
if (!strncmp(match, dev->asc_command, 6)) {
*pcmd = cmd;
dev->hex_command = cmd->hex;
break;
}
} else {
/* Otherwise match on the hex command. */
if (cmd->hex == dev->hex_command) {
sprintf(dev->asc_command, "%-6.6s", cmd->ascii);
*pcmd = cmd;
break;
}
}
}
return 1;
}
/*
* Beginning of a command list.
*
* Parse commands up to the next CLEND, storing
* them (in hex form) in the named command list.
*/
static void
hndl_clbeg(pgc_t *dev)
{
const pgc_cmd_t *cmd;
uint8_t param = 0;
pgc_cl_t cl;
if (!pgc_param_byte(dev, ¶m))
return;
pgc_log("PGC: CLBEG(%i)\n", param);
memset(&cl, 0x00, sizeof(pgc_cl_t));
while (1) {
if (!parse_command(dev, &cmd)) {
/* PGC has been reset. */
return;
}
if (!cmd) {
pgc_error(dev, PGC_ERROR_OPCODE);
return;
} else if (dev->hex_command == 0x71) {
/* CLEND */
dev->clist[param] = cl;
return;
} else {
if (!pgc_cl_append(&cl, dev->hex_command)) {
pgc_error(dev, PGC_ERROR_OVERFLOW);
return;
}
if (cmd->parser) {
if (!(*cmd->parser)(dev, &cl, cmd->p))
return;
}
}
}
}
static void
hndl_clend(UNUSED(pgc_t *dev))
{
/* Should not happen outside a CLBEG. */
}
/*
* Execute a command list.
*
* If one was already executing, remember
* it so we can return to it afterwards.
*/
static void
hndl_clrun(pgc_t *dev)
{
pgc_cl_t *clprev = dev->clcur;
uint8_t param = 0;
if (!pgc_param_byte(dev, ¶m))
return;
dev->clcur = &dev->clist[param];
dev->clcur->rdptr = 0;
dev->clcur->repeat = 1;
dev->clcur->chain = clprev;
}
/* Execute a command list multiple times. */
static void
hndl_cloop(pgc_t *dev)
{
pgc_cl_t *clprev = dev->clcur;
uint8_t param = 0;
int16_t repeat = 0;
if (!pgc_param_byte(dev, ¶m))
return;
if (!pgc_param_word(dev, &repeat))
return;
dev->clcur = &dev->clist[param];
dev->clcur->rdptr = 0;
dev->clcur->repeat = repeat;
dev->clcur->chain = clprev;
}
/* Read back a command list. */
static void
hndl_clread(pgc_t *dev)
{
uint8_t param = 0;
if (!pgc_param_byte(dev, ¶m))
return;
for (uint32_t n = 0; n < dev->clist[param].wrptr; n++) {
if (!pgc_result_byte(dev, dev->clist[param].list[n]))
return;
}
}
/* Delete a command list. */
static void
hndl_cldel(pgc_t *dev)
{
uint8_t param = 0;
if (!pgc_param_byte(dev, ¶m))
return;
memset(&dev->clist[param], 0, sizeof(pgc_cl_t));
}
/* Clear the screen to a specified color. */
static void
hndl_clears(pgc_t *dev)
{
uint8_t param = 0;
if (!pgc_param_byte(dev, ¶m))
return;
for (uint32_t y = 0; y < dev->screenh; y++)
memset(dev->vram + y * dev->maxw, param, dev->screenw);
}
/* Select drawing color. */
static void
hndl_color(pgc_t *dev)
{
uint8_t param = 0;
if (!pgc_param_byte(dev, ¶m))
return;
pgc_log("PGC: COLOR(%i)\n", param);
dev->color = param;
}
/*
* Set drawing mode.
*
* 0 => Draw
* 1 => Invert
*/
static void
hndl_linfun(pgc_t *dev)
{
uint8_t param = 0;
if (!pgc_param_byte(dev, ¶m))
return;
pgc_log("PGC: LINFUN(%i)\n", param);
if (param < 2)
dev->draw_mode = param;
else
pgc_error(dev, PGC_ERROR_RANGE);
}
/* Set the line drawing pattern. */
static void
hndl_linpat(pgc_t *dev)
{
uint16_t param = 0;
if (!pgc_param_word(dev, (int16_t *) ¶m))
return;
pgc_log("PGC: LINPAT(0x%04x)\n", param);
dev->line_pattern = param;
}
/* Set the polygon fill mode (0=hollow, 1=filled, 2=fast fill). */
static void
hndl_prmfil(pgc_t *dev)
{
uint8_t param = 0;
if (!pgc_param_byte(dev, ¶m))
return;
pgc_log("PGC: PRMFIL(%i)\n", param);
if (param < 3)
dev->fill_mode = param;
else
pgc_error(dev, PGC_ERROR_RANGE);
}
/* Set the 2D drawing position. */
static void
hndl_move(pgc_t *dev)
{
int32_t x = 0;
int32_t y = 0;
if (!pgc_param_coord(dev, &x))
return;
if (!pgc_param_coord(dev, &y))
return;
pgc_log("PCG: MOVE %x.%04x,%x.%04x\n",
HWORD(x), LWORD(x), HWORD(y), LWORD(y));
dev->x = x;
dev->y = y;
}
/* Set the 3D drawing position. */
static void
hndl_move3(pgc_t *dev)
{
int32_t x = 0;
int32_t y = 0;
int32_t z = 0;
if (!pgc_param_coord(dev, &x))
return;
if (!pgc_param_coord(dev, &y))
return;
if (!pgc_param_coord(dev, &z))
return;
dev->x = x;
dev->y = y;
dev->z = z;
}
/* Relative move (2D). */
static void
hndl_mover(pgc_t *dev)
{
int32_t x = 0;
int32_t y = 0;
if (!pgc_param_coord(dev, &x))
return;
if (!pgc_param_coord(dev, &y))
return;
dev->x += x;
dev->y += y;
}
/* Relative move (3D). */
static void
hndl_mover3(pgc_t *dev)
{
int32_t x = 0;
int32_t y = 0;
int32_t z = 0;
if (!pgc_param_coord(dev, &x))
return;
if (!pgc_param_coord(dev, &y))
return;
if (!pgc_param_coord(dev, &z))
return;
dev->x += x;
dev->y += y;
dev->z += z;
}
/* Given raster coordinates, find the matching address in PGC video RAM. */
uint8_t *
pgc_vram_addr(pgc_t *dev, int16_t x, int16_t y)
{
int offset;
/* We work from the bottom left-hand corner. */
if (y < 0 || (uint32_t) y >= dev->maxh || x < 0 || (uint32_t) x >= dev->maxw)
return NULL;
offset = (dev->maxh - 1 - y) * (dev->maxw) + x;
pgc_log("PGC: vram_addr(x=%i,y=%i) = %i\n", x, y, offset);
if (offset < 0 || (uint32_t) offset >= (dev->maxw * dev->maxh))
return NULL;
return &dev->vram[offset];
}
/*
* Write a screen pixel.
* X and Y are raster coordinates, ink is the value to write.
*/
void
pgc_write_pixel(pgc_t *dev, uint16_t x, uint16_t y, uint8_t ink)
{
uint8_t *vram;
/* Suppress out-of-range writes; clip to viewport. */
if (x < dev->vp_x1 || x > dev->vp_x2 || x >= dev->maxw || y < dev->vp_y1 || y > dev->vp_y2 || y >= dev->maxh) {
pgc_log("PGC: write_pixel clipped: (%i,%i) "
"vp_x1=%i vp_y1=%i vp_x2=%i vp_y2=%i "
"ink=0x%02x\n",
x, y, dev->vp_x1, dev->vp_y1, dev->vp_x2, dev->vp_y2, ink);
return;
}
vram = pgc_vram_addr(dev, x, y);
if (vram)
*vram = ink;
}
/* Read a screen pixel (x and y are raster coordinates). */
uint8_t
pgc_read_pixel(pgc_t *dev, uint16_t x, uint16_t y)
{
const uint8_t *vram;
/* Suppress out-of-range reads. */
if (x >= dev->maxw || y >= dev->maxh)
return 0;
vram = pgc_vram_addr(dev, x, y);
if (vram)
return *vram;
return 0;
}
/*
* Plot a point in the current color and draw mode. Raster coordinates.
*
* FIXME: this should be overloaded by clones if they support
* modes other than WRITE and INVERT, like the IM-1024.
*/
void
pgc_plot(pgc_t *dev, uint16_t x, uint16_t y)
{
uint8_t *vram;
/* Only allow plotting within the current viewport. */
if (x < dev->vp_x1 || x > dev->vp_x2 || x >= dev->maxw || y < dev->vp_y1 || y > dev->vp_y2 || y >= dev->maxh) {
pgc_log("PGC: plot clipped: (%i,%i) %i <= x <= %i; %i <= y <= %i; "
"mode=%i ink=0x%02x\n",
x, y,
dev->vp_x1, dev->vp_x2, dev->vp_y1, dev->vp_y2,
dev->draw_mode, dev->color);
return;
}
vram = pgc_vram_addr(dev, x, y);
if (!vram)
return;
/* TODO: Does not implement the PGC plane mask (set by MASK). */
switch (dev->draw_mode) {
default:
case 0: /* WRITE */
*vram = dev->color;
break;
case 1: /* INVERT */
*vram ^= 0xff;
break;
case 2: /* XOR color */
// FIXME: see notes
*vram ^= dev->color;
break;
case 3: /* AND color */
// FIXME: see notes
*vram &= dev->color;
break;
}
}
/*
* Draw a line (using raster coordinates).
*
* Bresenham's Algorithm from:
* <path_to_url#C>
*
* The line pattern mask to use is passed in. Return value is the
* line pattern mask, rotated by the number of points drawn.
*/
uint16_t
pgc_draw_line_r(pgc_t *dev, int32_t x0, int32_t y0, int32_t x1, int32_t y1, uint16_t linemask)
{
int32_t dx;
int32_t dy;
int32_t sx;
int32_t sy;
int32_t err;
int32_t e2;
dx = abs(x1 - x0);
dy = abs(y1 - y0);
sx = (x0 < x1) ? 1 : -1;
sy = (y0 < y1) ? 1 : -1;
err = (dx > dy ? dx : -dy) / 2;
for (;;) {
if (linemask & 0x8000) {
pgc_plot(dev, x0, y0);
linemask = (linemask << 1) | 1;
} else
linemask = (linemask << 1);
if (x0 == x1 && y0 == y1)
break;
e2 = err;
if (e2 > -dx) {
err -= dy;
x0 += sx;
}
if (e2 < dy) {
err += dx;
y0 += sy;
}
}
return linemask;
}
/* Draw a line (using PGC fixed-point coordinates). */
uint16_t
pgc_draw_line(pgc_t *dev, int32_t x0, int32_t y0, int32_t x1, int32_t y1, uint16_t linemask)
{
pgc_log("pgc_draw_line: (%i,%i) to (%i,%i)\n",
x0 >> 16, y0 >> 16, x1 >> 16, y1 >> 16);
/* Convert from PGC fixed-point to device coordinates */
x0 >>= 16;
y0 >>= 16;
pgc_ito_raster(dev, &x0, &y0);
x1 >>= 16;
y1 >>= 16;
pgc_ito_raster(dev, &x1, &y1);
return pgc_draw_line_r(dev, x0, y0, x1, y1, linemask);
}
/*
* Draw a horizontal line in the current fill pattern
* (using raster coordinates).
*/
void
pgc_fill_line_r(pgc_t *dev, int32_t x0, int32_t x1, int32_t y0)
{
int32_t mask = 0x8000 >> (x0 & 0x0f);
int32_t x;
if (x0 > x1) {
x = x1;
x1 = x0;
x0 = x;
}
for (x = x0; x <= x1; x++) {
if (dev->fill_pattern[y0 & 0x0F] & mask)
pgc_plot(dev, x, y0);
mask = mask >> 1;
if (mask == 0)
mask = 0x8000;
}
}
/* For sorting polygon nodes. */
static int
compare_double(const void *a, const void *b)
{
const double *da = (const double *) a;
const double *db = (const double *) b;
if (*da < *db)
return 1;
if (*da > *db)
return -1;
return 0;
}
/* Draw a filled polygon (using PGC fixed-point coordinates). */
void
pgc_fill_polygon(pgc_t *dev, unsigned corners, int32_t *x, int32_t *y)
{
double *nodex;
double *dx;
double *dy;
unsigned nodes;
unsigned i;
unsigned j;
double ymin;
double ymax;
pgc_log("PGC: fill_polygon(%i corners)\n", corners);
if (!x || !y || (corners < 2))
return; /* Degenerate polygon */
nodex = (double *) malloc(corners * sizeof(double));
dx = (double *) malloc(corners * sizeof(double));
dy = (double *) malloc(corners * sizeof(double));
if (!nodex || !dx || !dy) {
if (nodex) {
free(nodex);
nodex = NULL;
}
if (dx) {
free(dx);
dx = NULL;
}
if (dy) {
free(dy);
dy = NULL;
}
return;
}
ymin = ymax = y[0] / 65536.0;
for (unsigned int n = 0; n < corners; n++) {
/* Convert from PGC fixed-point to native floating-point. */
dx[n] = x[n] / 65536.0;
dy[n] = y[n] / 65536.0;
if (dy[n] < ymin)
ymin = dy[n];
if (dy[n] > ymax)
ymax = dy[n];
}
/* Polygon fill. Based on <path_to_url */
/* For each row, work out where the polygon lines intersect with
* that row. */
for (double ypos = ymin; ypos <= ymax; ypos++) {
nodes = 0;
j = corners - 1;
for (i = 0; i < corners; i++) {
if ((dy[i] < ypos && dy[j] >= ypos) || (dy[j] < ypos && dy[i] >= ypos)) /* Line crosses */ {
nodex[nodes++] = dx[i] + (ypos - dy[i]) / (dy[j] - dy[i]) * (dx[j] - dx[i]);
}
j = i;
}
/* Sort the intersections. */
if (nodes)
qsort(nodex, nodes, sizeof(double), compare_double);
/* And fill between them. */
for (i = 0; i < nodes; i += 2) {
int16_t x1 = (int16_t) nodex[i];
int16_t x2 = (int16_t) nodex[i + 1];
int16_t y1 = (int16_t) ypos;
int16_t y2 = (int16_t) ypos;
pgc_sto_raster(dev, &x1, &y1);
pgc_sto_raster(dev, &x2, &y2);
pgc_fill_line_r(dev, x1, x2, y1);
}
}
free(nodex);
free(dx);
free(dy);
}
/* Draw a filled ellipse (using PGC fixed-point coordinates). */
void
pgc_draw_ellipse(pgc_t *dev, int32_t x, int32_t y)
{
/* Convert from PGC fixed-point to native floating-point. */
double h = y / 65536.0;
double w = x / 65536.0;
double y0 = dev->y / 65536.0;
double x0 = dev->x / 65536.0;
double x1;
double xlast = 0.0;
int16_t linemask = dev->line_pattern;
pgc_log("PGC: ellipse(color=%i drawmode=%i fill=%i)\n",
dev->color, dev->draw_mode, dev->fill_mode);
pgc_dto_raster(dev, &x0, &y0);
for (double ypos = 0; ypos <= h; ypos++) {
if (ypos == 0) {
if (dev->fill_mode)
pgc_fill_line_r(dev, (uint16_t) (x0 - w),
(uint16_t) (x0 + w), (uint16_t) y0);
if (linemask & 0x8000) {
pgc_plot(dev, (uint16_t) (x0 + w), (uint16_t) y0);
pgc_plot(dev, (uint16_t) (x0 - w), (uint16_t) y0);
linemask = (linemask << 1) | 1;
} else
linemask = linemask << 1;
xlast = w;
} else {
x1 = sqrt((h * h) - (ypos * ypos)) * w / h;
if (dev->fill_mode) {
pgc_fill_line_r(dev, (uint16_t) (x0 - x1),
(uint16_t) (x0 + x1),
(uint16_t) (y0 + ypos));
pgc_fill_line_r(dev, (uint16_t) (x0 - x1),
(uint16_t) (x0 + x1),
(uint16_t) (y0 - ypos));
}
/* Draw border. */
for (double xpos = xlast; xpos >= x1; xpos--) {
if (linemask & 0x8000) {
pgc_plot(dev, (uint16_t) (x0 + xpos),
(uint16_t) (y0 + ypos));
pgc_plot(dev, (uint16_t) (x0 - xpos),
(uint16_t) (y0 + ypos));
pgc_plot(dev, (uint16_t) (x0 + xpos),
(uint16_t) (y0 - ypos));
pgc_plot(dev, (uint16_t) (x0 - xpos),
(uint16_t) (y0 - ypos));
linemask = (linemask << 1) | 1;
} else
linemask = linemask << 1;
}
xlast = x1;
}
}
}
/* Handle the ELIPSE (sic) command. */
static void
hndl_ellipse(pgc_t *dev)
{
int32_t x = 0;
int32_t y = 0;
if (!pgc_param_coord(dev, &x))
return;
if (!pgc_param_coord(dev, &y))
return;
pgc_draw_ellipse(dev, x, y);
}
/* Handle the POLY command. */
static void
hndl_poly(pgc_t *dev)
{
uint8_t count;
int32_t x[256];
int32_t y[256];
if (!pgc_param_byte(dev, &count))
return;
pgc_log("PGC: POLY (%i)\n", count);
for (uint8_t n = 0; n < count; n++) {
if (!pgc_param_coord(dev, &x[n]))
return;
if (!pgc_param_coord(dev, &y[n]))
return;
}
}
/* Parse but don't execute a POLY command (for adding to a command list) */
static int
parse_poly(pgc_t *dev, pgc_cl_t *cl, UNUSED(int c))
{
uint8_t count;
#ifdef ENABLE_PGC_LOG
pgc_log("PCG: parse_poly\n");
#endif
if (!pgc_param_byte(dev, &count))
return 0;
pgc_log("PCG: parse_poly: count=%02x\n", count);
if (!pgc_cl_append(cl, count)) {
pgc_error(dev, PGC_ERROR_OVERFLOW);
return 0;
}
pgc_log("PCG: parse_poly: parse %i coords\n", 2 * count);
return pgc_parse_coords(dev, cl, 2 * count);
}
/* Handle the DISPLAY command. */
static void
hndl_display(pgc_t *dev)
{
uint8_t param;
if (!pgc_param_byte(dev, ¶m))
return;
pgc_log("PGC: DISPLAY(%i)\n", param);
if (param > 1)
pgc_error(dev, PGC_ERROR_RANGE);
else
pgc_setdisplay(dev, param);
}
/* Handle the IMAGEW command (memory to screen blit). */
static void
hndl_imagew(pgc_t *dev)
{
int16_t row;
int16_t col1;
int16_t col2;
uint8_t v1;
uint8_t v2;
if (!pgc_param_word(dev, &row))
return;
if (!pgc_param_word(dev, &col1))
return;
if (!pgc_param_word(dev, &col2))
return;
if ((uint32_t) row >= dev->screenh || (uint32_t) col1 >= dev->maxw || (uint32_t) col2 >= dev->maxw) {
pgc_error(dev, PGC_ERROR_RANGE);
return;
}
/* In ASCII mode, what is written is a stream of bytes. */
if (dev->ascii_mode) {
while (col1 <= col2) {
if (!pgc_param_byte(dev, &v1))
return;
pgc_write_pixel(dev, col1, row, v1);
col1++;
}
return;
}
/* In hex mode, it's RLE compressed. */
while (col1 <= col2) {
if (!pgc_param_byte(dev, &v1))
return;
if (v1 & 0x80) {
/* Literal run. */
v1 -= 0x7f;
while (col1 <= col2 && v1 != 0) {
if (!pgc_param_byte(dev, &v2))
return;
pgc_write_pixel(dev, col1, row, v2);
col1++;
v1--;
}
} else {
/* Repeated run. */
if (!pgc_param_byte(dev, &v2))
return;
v1++;
while (col1 <= col2 && v1 != 0) {
pgc_write_pixel(dev, col1, row, v2);
col1++;
v1--;
}
}
}
}
/* Select one of the built-in palettes. */
static void
init_lut(pgc_t *dev, int param)
{
if (param >= 0 && param < 6)
memcpy(dev->palette, init_palette[param], sizeof(dev->palette));
else if (param == 0xff)
memcpy(dev->palette, dev->userpal, sizeof(dev->palette));
else
pgc_error(dev, PGC_ERROR_RANGE);
}
/* Save the current palette. */
static void
hndl_lutsav(pgc_t *dev)
{
memcpy(dev->userpal, dev->palette, sizeof(dev->palette));
}
/* Handle LUTINT (select palette). */
static void
hndl_lutint(pgc_t *dev)
{
uint8_t param;
if (!pgc_param_byte(dev, ¶m))
return;
init_lut(dev, param);
}
/* Handle LUTRD (read palette register). */
static void
hndl_lutrd(pgc_t *dev)
{
uint8_t param;
uint32_t col;
if (!pgc_param_byte(dev, ¶m))
return;
col = dev->palette[param];
pgc_result_byte(dev, (col >> 20) & 0x0f);
pgc_result_byte(dev, (col >> 12) & 0x0f);
pgc_result_byte(dev, (col >> 4) & 0x0f);
}
/* Handle LUT (write palette register). */
static void
hndl_lut(pgc_t *dev)
{
uint8_t param[4];
for (uint8_t n = 0; n < 4; n++) {
if (!pgc_param_byte(dev, ¶m[n]))
return;
if (n > 0 && param[n] > 15) {
pgc_error(dev, PGC_ERROR_RANGE);
param[n] &= 0x0f;
}
}
dev->palette[param[0]] = makecol((param[1] * 0x11),
(param[2] * 0x11),
(param[3] * 0x11));
}
/*
* LUT8RD and LUT8 are extensions implemented by several PGC clones,
* so here are functions that implement them even though they aren't
* used by the PGC.
*/
void
pgc_hndl_lut8rd(pgc_t *dev)
{
uint8_t param;
uint32_t col;
if (!pgc_param_byte(dev, ¶m))
return;
col = dev->palette[param];
pgc_result_byte(dev, (col >> 16) & 0xff);
pgc_result_byte(dev, (col >> 8) & 0xff);
pgc_result_byte(dev, col & 0xff);
}
void
pgc_hndl_lut8(pgc_t *dev)
{
uint8_t param[4];
for (uint8_t n = 0; n < 4; n++)
if (!pgc_param_byte(dev, ¶m[n]))
return;
dev->palette[param[0]] = makecol((param[1]), (param[2]), (param[3]));
}
/* Handle AREAPT (set 16x16 fill pattern). */
static void
hndl_areapt(pgc_t *dev)
{
int16_t pat[16];
for (uint8_t n = 0; n < 16; n++)
if (!pgc_param_word(dev, &pat[n]))
return;
pgc_log("PGC: AREAPT(%04x %04x %04x %04x...)\n",
pat[0] & 0xffff, pat[1] & 0xffff, pat[2] & 0xffff, pat[3] & 0xffff);
memcpy(dev->fill_pattern, pat, sizeof(dev->fill_pattern));
}
/* Handle CA (select ASCII mode). */
static void
hndl_ca(pgc_t *dev)
{
dev->ascii_mode = 1;
}
/* Handle CX (select hex mode). */
static void
hndl_cx(pgc_t *dev)
{
dev->ascii_mode = 0;
}
/*
* CA and CX remain valid in hex mode; they are handled
* as command 0x43 ('C') with a one-byte parameter.
*/
static void
hndl_c(pgc_t *dev)
{
uint8_t param;
if (!dev->inputbyte(dev, ¶m))
return;
if (param == 'A')
dev->ascii_mode = 1;
if (param == 'X')
dev->ascii_mode = 0;
}
/* RESETF resets the PGC. */
static void
hndl_resetf(pgc_t *dev)
{
pgc_reset(dev);
}
/* TJUST sets text justify settings. */
static void
hndl_tjust(pgc_t *dev)
{
uint8_t param[2];
if (!dev->inputbyte(dev, ¶m[0]))
return;
if (!dev->inputbyte(dev, ¶m[1]))
return;
if (param[0] >= 1 && param[0] <= 3 && param[1] >= 1 && param[1] <= 3) {
dev->tjust_h = param[0];
dev->tjust_v = param[1];
} else
pgc_error(dev, PGC_ERROR_RANGE);
}
/* TSIZE controls text horizontal spacing. */
static void
hndl_tsize(pgc_t *pgc)
{
int32_t param = 0;
if (!pgc_param_coord(pgc, ¶m))
return;
pgc_log("PGC: TSIZE %i\n", param);
pgc->tsize = param;
}
/*
* VWPORT sets up the viewport (roughly, the clip rectangle) in
* raster coordinates, measured from the bottom left of the screen.
*/
static void
hndl_vwport(pgc_t *dev)
{
int16_t x1;
int16_t x2;
int16_t y1;
int16_t y2;
if (!pgc_param_word(dev, &x1))
return;
if (!pgc_param_word(dev, &x2))
return;
if (!pgc_param_word(dev, &y1))
return;
if (!pgc_param_word(dev, &y2))
return;
pgc_log("PGC: VWPORT %i,%i,%i,%i\n", x1, x2, y1, y2);
dev->vp_x1 = x1;
dev->vp_x2 = x2;
dev->vp_y1 = y1;
dev->vp_y2 = y2;
}
/* WINDOW defines the coordinate system in use. */
static void
hndl_window(pgc_t *dev)
{
int16_t x1;
int16_t x2;
int16_t y1;
int16_t y2;
if (!pgc_param_word(dev, &x1))
return;
if (!pgc_param_word(dev, &x2))
return;
if (!pgc_param_word(dev, &y1))
return;
if (!pgc_param_word(dev, &y2))
return;
pgc_log("PGC: WINDOW %i,%i,%i,%i\n", x1, x2, y1, y2);
dev->win_x1 = x1;
dev->win_x2 = x2;
dev->win_y1 = y1;
dev->win_y2 = y2;
}
/*
* The list of commands implemented by this mini-PGC.
*
* In order to support the original PGC and clones, we support two lists;
* core commands (listed below) and subclass commands (listed in the clone).
*
* Each row has five parameters:
* ASCII-mode command
* Hex-mode command
* Function that executes this command
* Function that parses this command when building a command list
* Parameter for the parse function
*
* TODO: This list omits numerous commands present in a genuine PGC
* (ARC, AREA, AREABC, BUFFER, CIRCLE etc etc).
* TODO: Some commands don't have a parse function (for example, IMAGEW)
*
* The following ASCII entries have special meaning:
* ~~~~~~ command is valid only in hex mode
* ****** end of subclass command list, now process core command list
* @@@@@@ end of core command list
*
*/
static const pgc_cmd_t pgc_commands[] = {
{"AREAPT", 0xe7, hndl_areapt, pgc_parse_words, 16},
{ "AP", 0xe7, hndl_areapt, pgc_parse_words, 16},
{ "~~~~~~", 0x43, hndl_c, NULL, 0 },
{ "CA", 0xd2, hndl_ca, NULL, 0 },
{ "CLBEG", 0x70, hndl_clbeg, NULL, 0 },
{ "CB", 0x70, hndl_clbeg, NULL, 0 },
{ "CLDEL", 0x74, hndl_cldel, pgc_parse_bytes, 1 },
{ "CD", 0x74, hndl_cldel, pgc_parse_bytes, 1 },
{ "CLEND", 0x71, hndl_clend, NULL, 0 },
{ "CLRUN", 0x72, hndl_clrun, pgc_parse_bytes, 1 },
{ "CR", 0x72, hndl_clrun, pgc_parse_bytes, 1 },
{ "CLRD", 0x75, hndl_clread, pgc_parse_bytes, 1 },
{ "CRD", 0x75, hndl_clread, pgc_parse_bytes, 1 },
{ "CLOOP", 0x73, hndl_cloop, NULL, 0 },
{ "CL", 0x73, hndl_cloop, NULL, 0 },
{ "CLEARS", 0x0f, hndl_clears, pgc_parse_bytes, 1 },
{ "CLS", 0x0f, hndl_clears, pgc_parse_bytes, 1 },
{ "COLOR", 0x06, hndl_color, pgc_parse_bytes, 1 },
{ "C", 0x06, hndl_color, pgc_parse_bytes, 1 },
{ "CX", 0xd1, hndl_cx, NULL, 0 },
{ "DISPLA", 0xd0, hndl_display, pgc_parse_bytes, 1 },
{ "DI", 0xd0, hndl_display, pgc_parse_bytes, 1 },
{ "ELIPSE", 0x39, hndl_ellipse, pgc_parse_coords, 2 },
{ "EL", 0x39, hndl_ellipse, pgc_parse_coords, 2 },
{ "IMAGEW", 0xd9, hndl_imagew, NULL, 0 },
{ "IW", 0xd9, hndl_imagew, NULL, 0 },
{ "LINFUN", 0xeb, hndl_linfun, pgc_parse_bytes, 1 },
{ "LF", 0xeb, hndl_linfun, pgc_parse_bytes, 1 },
{ "LINPAT", 0xea, hndl_linpat, pgc_parse_words, 1 },
{ "LP", 0xea, hndl_linpat, pgc_parse_words, 1 },
{ "LUTINT", 0xec, hndl_lutint, pgc_parse_bytes, 1 },
{ "LI", 0xec, hndl_lutint, pgc_parse_bytes, 1 },
{ "LUTRD", 0x50, hndl_lutrd, pgc_parse_bytes, 1 },
{ "LUTSAV", 0xed, hndl_lutsav, NULL, 0 },
{ "LUT", 0xee, hndl_lut, pgc_parse_bytes, 4 },
{ "MOVE", 0x10, hndl_move, pgc_parse_coords, 2 },
{ "M", 0x10, hndl_move, pgc_parse_coords, 2 },
{ "MOVE3", 0x12, hndl_move3, pgc_parse_coords, 3 },
{ "M3", 0x12, hndl_move3, pgc_parse_coords, 3 },
{ "MOVER", 0x11, hndl_mover, pgc_parse_coords, 2 },
{ "MR", 0x11, hndl_mover, pgc_parse_coords, 2 },
{ "MOVER3", 0x13, hndl_mover3, pgc_parse_coords, 3 },
{ "MR3", 0x13, hndl_mover3, pgc_parse_coords, 3 },
{ "PRMFIL", 0xe9, hndl_prmfil, pgc_parse_bytes, 1 },
{ "PF", 0xe9, hndl_prmfil, pgc_parse_bytes, 1 },
{ "POLY", 0x30, hndl_poly, parse_poly, 0 },
{ "P", 0x30, hndl_poly, parse_poly, 0 },
{ "RESETF", 0x04, hndl_resetf, NULL, 0 },
{ "RF", 0x04, hndl_resetf, NULL, 0 },
{ "TJUST", 0x85, hndl_tjust, pgc_parse_bytes, 2 },
{ "TJ", 0x85, hndl_tjust, pgc_parse_bytes, 2 },
{ "TSIZE", 0x81, hndl_tsize, pgc_parse_coords, 1 },
{ "TS", 0x81, hndl_tsize, pgc_parse_coords, 1 },
{ "VWPORT", 0xb2, hndl_vwport, pgc_parse_words, 4 },
{ "VWP", 0xb2, hndl_vwport, pgc_parse_words, 4 },
{ "WINDOW", 0xb3, hndl_window, pgc_parse_words, 4 },
{ "WI", 0xb3, hndl_window, pgc_parse_words, 4 },
{ "@@@@@@", 0x00, NULL, NULL, 0 }
};
/* When the wake timer expires, that's when the drawing thread is actually
* woken */
static void
wake_timer(void *priv)
{
pgc_t *dev = (pgc_t *) priv;
#ifdef ENABLE_PGC_LOG
pgc_log("PGC: woke up\n");
#endif
thread_set_event(dev->pgc_wake_thread);
}
/*
* The PGC drawing thread main loop.
*
* Read in commands and execute them ad infinitum.
*/
static void
pgc_thread(void *priv)
{
pgc_t *dev = (pgc_t *) priv;
const pgc_cmd_t *cmd;
#ifdef ENABLE_PGC_LOG
pgc_log("PGC: thread begins\n");
#endif
for (;;) {
if (!parse_command(dev, &cmd)) {
/* Are we shutting down? */
if (dev->stopped) {
#ifdef ENABLE_PGC_LOG
pgc_log("PGC: Thread stopping...\n");
#endif
dev->stopped = 0;
break;
}
/* Nope, just a reset. */
continue;
}
pgc_log("PGC: Command: [%02x] '%s' found = %i\n",
dev->hex_command, dev->asc_command, (cmd != NULL));
if (cmd) {
dev->result_count = 0;
(*cmd->handler)(dev);
} else
pgc_error(dev, PGC_ERROR_OPCODE);
}
#ifdef ENABLE_PGC_LOG
pgc_log("PGC: thread stopped\n");
#endif
}
/* Parameter passed is not a number: abort. */
static int
err_digit(pgc_t *dev)
{
uint8_t asc;
do {
/* Swallow everything until the next separator */
if (!dev->inputbyte(dev, &asc))
return 0;
} while (!is_whitespace(asc));
pgc_error(dev, PGC_ERROR_DIGIT);
return 0;
}
/* Output a byte, either as hex or ASCII depending on the mode. */
int
pgc_result_byte(pgc_t *dev, uint8_t val)
{
char buf[20];
if (!dev->ascii_mode)
return output_byte(dev, val);
if (dev->result_count) {
if (!output_byte(dev, ','))
return 0;
}
sprintf(buf, "%i", val);
dev->result_count++;
return output_string(dev, buf);
}
/* Output a word, either as hex or ASCII depending on the mode. */
int
pgc_result_word(pgc_t *dev, int16_t val)
{
char buf[20];
if (!dev->ascii_mode) {
if (!output_byte(dev, val & 0xFF))
return 0;
return output_byte(dev, val >> 8);
}
if (dev->result_count) {
if (!output_byte(dev, ','))
return 0;
}
sprintf(buf, "%i", val);
dev->result_count++;
return output_string(dev, buf);
}
/* Report an error, either in ASCII or in hex. */
int
pgc_error(pgc_t *dev, int err)
{
if (dev->mapram[0x307]) {
/* Errors enabled? */
if (dev->ascii_mode) {
if (err >= PGC_ERROR_RANGE && err <= PGC_ERROR_MISSING)
return error_string(dev, pgc_err_msgs[err]);
return error_string(dev, "Unknown error\r");
} else {
return error_byte(dev, err);
}
}
return 1;
}
/* Initialize RAM and registers to default values. */
void
pgc_reset(pgc_t *dev)
{
memset(dev->mapram, 0x00, sizeof(dev->mapram));
/* The 'CGA disable' jumper is not currently implemented. */
dev->mapram[0x30b] = dev->cga_enabled = 1;
dev->mapram[0x30c] = dev->cga_enabled;
dev->mapram[0x30d] = dev->cga_enabled;
dev->mapram[0x3f8] = 0x03; /* minor version */
dev->mapram[0x3f9] = 0x01; /* minor version */
dev->mapram[0x3fb] = 0xa5; /* } */
dev->mapram[0x3fc] = 0x5a; /* PGC self-test passed */
dev->mapram[0x3fd] = 0x55; /* } */
dev->mapram[0x3fe] = 0x5a; /* } */
dev->ascii_mode = 1; /* start off in ASCII mode */
dev->line_pattern = 0xffff;
memset(dev->fill_pattern, 0xff, sizeof(dev->fill_pattern));
dev->color = 0xff;
dev->tjust_h = 1;
dev->tjust_v = 1;
/* Reset panning. */
dev->pan_x = 0;
dev->pan_y = 0;
/* Reset clipping. */
dev->vp_x1 = 0;
dev->vp_y1 = 0;
dev->vp_x2 = dev->visw - 1;
dev->vp_y2 = dev->vish - 1;
/* Empty command lists. */
for (uint16_t n = 0; n < 256; n++) {
dev->clist[n].wrptr = 0;
dev->clist[n].rdptr = 0;
dev->clist[n].repeat = 0;
dev->clist[n].chain = 0;
}
dev->clcur = NULL;
/* Select CGA display. */
dev->cga_selected = -1;
pgc_setdisplay(dev, dev->cga_enabled);
/* Default palette is 0. */
init_lut(dev, 0);
hndl_lutsav(dev);
}
/* Switch between CGA mode (DISPLAY 1) and native mode (DISPLAY 0). */
void
pgc_setdisplay(pgc_t *dev, int cga)
{
pgc_log("PGC: setdisplay(%i): cga_selected=%i cga_enabled=%i\n",
cga, dev->cga_selected, dev->cga_enabled);
if (dev->cga_selected != (dev->cga_enabled && cga)) {
dev->cga_selected = (dev->cga_enabled && cga);
dev->displine = 0;
if (dev->cga_selected) {
mem_mapping_enable(&dev->cga_mapping);
dev->screenw = PGC_CGA_WIDTH;
dev->screenh = PGC_CGA_HEIGHT;
} else {
mem_mapping_disable(&dev->cga_mapping);
dev->screenw = dev->visw;
dev->screenh = dev->vish;
}
pgc_recalctimings(dev);
}
}
/*
* When idle, the PGC drawing thread sleeps. pgc_wake() awakens it - but
* not immediately. Like the Voodoo, it has a short delay so that writes
* can be batched.
*/
void
pgc_wake(pgc_t *dev)
{
if (!timer_is_enabled(&dev->wake_timer))
timer_set_delay_u64(&dev->wake_timer, WAKE_DELAY);
}
/* Wait for more input data, or for output to drain. */
void
pgc_sleep(pgc_t *dev)
{
pgc_log("PGC: sleeping on %i %i %i %i 0x%02x 0x%02x\n",
dev->stopped,
dev->waiting_input_fifo, dev->waiting_output_fifo,
dev->waiting_error_fifo, dev->mapram[0x300], dev->mapram[0x301]);
/* Avoid entering waiting state. */
if (dev->stopped) {
dev->waiting_input_fifo = 0;
dev->waiting_output_fifo = 0;
return;
}
/* Race condition: If host wrote to the PGC during the that
* won't be noticed */
if (dev->waiting_input_fifo && dev->mapram[0x300] != dev->mapram[0x301]) {
dev->waiting_input_fifo = 0;
return;
}
/* Same if they read. */
if (dev->waiting_output_fifo && dev->mapram[0x302] != (uint8_t) (dev->mapram[0x303] - 1)) {
dev->waiting_output_fifo = 0;
return;
}
thread_wait_event(dev->pgc_wake_thread, -1);
thread_reset_event(dev->pgc_wake_thread);
}
/* Pull the next byte from the current command list. */
int
pgc_clist_byte(pgc_t *dev, uint8_t *val)
{
if (dev->clcur == NULL)
return 0;
if (dev->clcur->rdptr < dev->clcur->wrptr)
*val = dev->clcur->list[dev->clcur->rdptr++];
else
*val = 0;
/* If we've reached the end, reset to the beginning and
* (if repeating) run the repeat */
if (dev->clcur->rdptr >= dev->clcur->wrptr) {
dev->clcur->rdptr = 0;
dev->clcur->repeat--;
if (dev->clcur->repeat == 0)
dev->clcur = dev->clcur->chain;
}
return 1;
}
/*
* Read in a byte, either as hex (1 byte) or ASCII (decimal).
* Returns 0 if PGC reset detected while the value is being read.
*/
int
pgc_param_byte(pgc_t *dev, uint8_t *val)
{
int32_t c;
if (dev->clcur)
return pgc_clist_byte(dev, val);
if (!dev->ascii_mode)
return dev->inputbyte(dev, val);
if (!pgc_param_coord(dev, &c))
return 0;
c = (c >> 16); /* drop fractional part */
if (c > 255) {
pgc_error(dev, PGC_ERROR_RANGE);
return 0;
}
*val = (uint8_t) c;
return 1;
}
/*
* Read in a word, either as hex (2 bytes) or ASCII (decimal).
* Returns 0 if PGC reset detected while the value is being read.
*/
int
pgc_param_word(pgc_t *dev, int16_t *val)
{
uint8_t lo;
uint8_t hi;
int32_t c;
if (dev->clcur) {
if (!pgc_clist_byte(dev, &lo))
return 0;
if (!pgc_clist_byte(dev, &hi))
return 0;
*val = (((int16_t) hi) << 8) | lo;
return 1;
}
if (!dev->ascii_mode) {
if (!dev->inputbyte(dev, &lo))
return 0;
if (!dev->inputbyte(dev, &hi))
return 0;
*val = (((int16_t) hi) << 8) | lo;
return 1;
}
if (!pgc_param_coord(dev, &c))
return 0;
c = (c >> 16);
if (c > 0x7fff || c < -0x7fff) {
pgc_error(dev, PGC_ERROR_RANGE);
return 0;
}
*val = (int16_t) c;
return 1;
}
typedef enum {
PS_MAIN,
PS_FRACTION,
PS_EXPONENT
} parse_state_t;
/*
* Read in a PGC coordinate.
*
* Either as hex (4 bytes) or ASCII (xxxx.yyyyEeee)
*
* Returns 0 if PGC reset detected while the value is being read.
*/
int
pgc_param_coord(pgc_t *dev, int32_t *value)
{
uint8_t asc;
int sign = 1;
int esign = 1;
int n;
uint16_t dp = 1;
uint16_t integer = 0;
uint16_t frac = 0;
uint16_t exponent = 0;
uint32_t res;
parse_state_t state = PS_MAIN;
uint8_t encoded[4];
/* If there is a command list running, pull the bytes out of that
* command list */
if (dev->clcur) {
for (n = 0; n < 4; n++)
if (!pgc_clist_byte(dev, &encoded[n]))
return 0;
integer = (((int16_t) encoded[1]) << 8) | encoded[0];
frac = (((int16_t) encoded[3]) << 8) | encoded[2];
*value = (((int32_t) integer) << 16) | frac;
return 1;
}
/* If in hex mode, read in the encoded integer and fraction parts
* from the hex stream */
if (!dev->ascii_mode) {
for (n = 0; n < 4; n++)
if (!dev->inputbyte(dev, &encoded[n]))
return 0;
integer = (((int16_t) encoded[1]) << 8) | encoded[0];
frac = (((int16_t) encoded[3]) << 8) | encoded[2];
*value = (((int32_t) integer) << 16) | frac;
return 1;
}
/* Parsing an ASCII value; skip separators. */
do {
if (!dev->inputbyte(dev, &asc))
return 0;
if (asc == '-')
sign = -1;
} while (is_whitespace(asc));
/* There had better be a digit next. */
if (!isdigit(asc)) {
pgc_error(dev, PGC_ERROR_MISSING);
return 0;
}
do {
switch (asc) {
/* Decimal point is acceptable in 'main' state
* (start of fraction) not otherwise */
case '.':
if (state == PS_MAIN) {
if (!dev->inputbyte(dev, &asc))
return 0;
state = PS_FRACTION;
continue;
} else {
pgc_error(dev, PGC_ERROR_MISSING);
return err_digit(dev);
}
/* Scientific notation. */
case 'd':
case 'D':
case 'e':
case 'E':
esign = 1;
if (!dev->inputbyte(dev, &asc))
return 0;
if (asc == '-') {
sign = -1;
if (!dev->inputbyte(dev, &asc))
return 0;
}
state = PS_EXPONENT;
continue;
/* Should be a number or a separator. */
default:
if (is_whitespace(asc))
break;
if (!isdigit(asc)) {
pgc_error(dev, PGC_ERROR_MISSING);
return err_digit(dev);
}
asc -= '0'; /* asc is digit */
switch (state) {
case PS_MAIN:
integer = (integer * 10) + asc;
if (integer & 0x8000) {
/* Overflow */
pgc_error(dev, PGC_ERROR_RANGE);
integer = 0x7fff;
}
break;
case PS_FRACTION:
frac = (frac * 10) + asc;
dp *= 10;
break;
case PS_EXPONENT:
exponent = (exponent * 10) + asc;
break;
}
}
if (!dev->inputbyte(dev, &asc))
return 0;
} while (!is_whitespace(asc));
res = (frac << 16) / dp;
pgc_log("PGC: integer=%u frac=%u exponent=%u dp=%i res=0x%08lx\n",
integer, frac, exponent, dp, res);
res = (res & 0xffff) | (integer << 16);
if (exponent) {
for (n = 0; n < exponent; n++) {
if (esign > 0)
res *= 10;
else
res /= 10;
}
}
*value = sign * res;
return 1;
}
/*
* Add a byte to a command list.
*
* We allow command lists to be arbitrarily large.
*/
int
pgc_cl_append(pgc_cl_t *list, uint8_t v)
{
uint8_t *buf;
if (list->listmax == 0 || list->list == NULL) {
list->list = (uint8_t *) malloc(4096);
if (!list->list) {
#ifdef ENABLE_PGC_LOG
pgc_log("PGC: out of memory initializing command list\n");
#endif
return 0;
}
list->listmax = 4096;
}
while (list->wrptr >= list->listmax) {
buf = (uint8_t *) realloc(list->list, 2 * list->listmax);
if (!buf) {
#ifdef ENABLE_PGC_LOG
pgc_log("PGC: out of memory growing command list\n");
#endif
return 0;
}
list->list = buf;
list->listmax *= 2;
}
list->list[list->wrptr++] = v;
return 1;
}
/* Parse but don't execute a command with a fixed number of byte parameters. */
int
pgc_parse_bytes(pgc_t *dev, pgc_cl_t *cl, int count)
{
uint8_t *param = (uint8_t *) malloc(count);
if (!param) {
pgc_error(dev, PGC_ERROR_OVERFLOW);
return 0;
}
for (int n = 0; n < count; n++) {
if (!pgc_param_byte(dev, ¶m[n])) {
free(param);
return 0;
}
if (!pgc_cl_append(cl, param[n])) {
pgc_error(dev, PGC_ERROR_OVERFLOW);
free(param);
return 0;
}
}
free(param);
return 1;
}
/* Parse but don't execute a command with a fixed number of word parameters. */
int
pgc_parse_words(pgc_t *dev, pgc_cl_t *cl, int count)
{
int16_t *param = (int16_t *) malloc(count * sizeof(int16_t));
if (!param) {
pgc_error(dev, PGC_ERROR_OVERFLOW);
return 0;
}
for (int n = 0; n < count; n++) {
if (!pgc_param_word(dev, ¶m[n])) {
free(param);
return 0;
}
if (!pgc_cl_append(cl, param[n] & 0xff) || !pgc_cl_append(cl, param[n] >> 8)) {
pgc_error(dev, PGC_ERROR_OVERFLOW);
free(param);
return 0;
}
}
free(param);
return 1;
}
/* Parse but don't execute a command with a fixed number of coord parameters */
int
pgc_parse_coords(pgc_t *dev, pgc_cl_t *cl, int count)
{
int32_t *param = (int32_t *) malloc(count * sizeof(int32_t));
int n;
if (!param) {
pgc_error(dev, PGC_ERROR_OVERFLOW);
return 0;
}
for (n = 0; n < count; n++) {
if (!pgc_param_coord(dev, ¶m[n])) {
free(param);
return 0;
}
}
/* Here is how the real PGC serializes coords:
*
* 100.5 -> 64 00 00 80 ie 0064.8000
* 100.3 -> 64 00 CD 4C ie 0064.4CCD
*/
for (n = 0; n < count; n++) {
/* Serialize integer part. */
if (!pgc_cl_append(cl, (param[n] >> 16) & 0xff) || !pgc_cl_append(cl, (param[n] >> 24) & 0xff) ||
/* Serialize fraction part. */
!pgc_cl_append(cl, (param[n]) & 0xff) || !pgc_cl_append(cl, (param[n] >> 8) & 0xff)) {
pgc_error(dev, PGC_ERROR_OVERFLOW);
free(param);
return 0;
}
}
free(param);
return 1;
}
/* Convert coordinates based on the current window / viewport to raster
* coordinates. */
void
pgc_dto_raster(pgc_t *dev, double *x, double *y)
{
#ifdef ENABLE_PGC_LOG
double x0 = *x, y0 = *y;
#endif
*x += (dev->vp_x1 - dev->win_x1);
*y += (dev->vp_y1 - dev->win_y1);
pgc_log("PGC: coords to raster: (%f, %f) -> (%f, %f)\n", x0, y0, *x, *y);
}
/* Overloads that take ints. */
void
pgc_sto_raster(pgc_t *dev, int16_t *x, int16_t *y)
{
double xd = *x;
double yd = *y;
pgc_dto_raster(dev, &xd, &yd);
*x = (int16_t) xd;
*y = (int16_t) yd;
}
void
pgc_ito_raster(pgc_t *dev, int32_t *x, int32_t *y)
{
double xd = *x;
double yd = *y;
pgc_dto_raster(dev, &xd, &yd);
*x = (int32_t) xd;
*y = (int32_t) yd;
}
void
pgc_recalctimings(pgc_t *dev)
{
double disptime;
double _dispontime;
double _dispofftime;
double pixel_clock = (cpuclock / (dev->cga_selected ? 25175000.0 : dev->native_pixel_clock) * (double) (1ULL << 32));
uint8_t crtc0 = 97; /* Value from MDA, taken from there due to the 25 MHz refresh rate. */
uint8_t crtc1 = 80; /* Value from MDA, taken from there due to the 25 MHz refresh rate. */
/* Multiply pixel clock by 8. */
pixel_clock *= 8.0;
/* Use a fixed 640x400 display. */
disptime = crtc0 + 1;
_dispontime = crtc1;
_dispofftime = disptime - _dispontime;
_dispontime *= pixel_clock;
_dispofftime *= pixel_clock;
dev->dispontime = (uint64_t) (_dispontime);
dev->dispofftime = (uint64_t) (_dispofftime);
}
/* Write to CGA registers are copied into the transfer memory buffer. */
void
pgc_out(uint16_t addr, uint8_t val, void *priv)
{
pgc_t *dev = (pgc_t *) priv;
pgc_log("PGC: out(%04x, %02x)\n", addr, val);
switch (addr) {
case 0x03d0: /* CRTC Index register */
case 0x03d2:
case 0x03d4:
case 0x03d6:
dev->mapram[0x03d0] = val;
break;
case 0x03d1: /* CRTC Data register */
case 0x03d3:
case 0x03d5:
case 0x03d7:
if (dev->mapram[0x03d0] < 18)
dev->mapram[0x03e0 + dev->mapram[0x03d0]] = val;
break;
case 0x03d8: /* CRTC Mode Control register */
dev->mapram[0x03d8] = val;
break;
case 0x03d9: /* CRTC Color Select register */
dev->mapram[0x03d9] = val;
break;
default:
break;
}
}
/* Read back the CGA registers. */
uint8_t
pgc_in(uint16_t addr, void *priv)
{
const pgc_t *dev = (pgc_t *) priv;
uint8_t ret = 0xff;
switch (addr) {
case 0x03d0: /* CRTC Index register */
case 0x03d2:
case 0x03d4:
case 0x03d6:
ret = dev->mapram[0x03d0];
break;
case 0x03d1: /* CRTC Data register */
case 0x03d3:
case 0x03d5:
case 0x03d7:
if (dev->mapram[0x03d0] < 18)
ret = dev->mapram[0x03e0 + dev->mapram[0x03d0]];
break;
case 0x03d8: /* CRTC Mode Control register */
ret = dev->mapram[0x03d8];
break;
case 0x03d9: /* CRTC Color Select register */
ret = dev->mapram[0x03d9];
break;
case 0x03da: /* CRTC Status register */
ret = dev->mapram[0x03da];
break;
default:
break;
}
pgc_log("PGC: in(%04x) = %02x\n", addr, ret);
return ret;
}
/* Memory write to the transfer buffer. */
/* TODO: Check the CGA mapping repeat stuff. */
void
pgc_write(uint32_t addr, uint8_t val, void *priv)
{
pgc_t *dev = (pgc_t *) priv;
/*
* It seems variable whether the PGC maps 1K or 2K at 0xc6000.
*
* Map 2K here in case a clone requires it.
*/
if (addr >= 0xc6000 && addr < 0xc6800) {
addr &= 0x7ff;
/* If one of the FIFOs has been updated, this may cause
* the drawing thread to be woken */
if (dev->mapram[addr] != val) {
dev->mapram[addr] = val;
switch (addr) {
case 0x300: /* input write pointer */
if (dev->waiting_input_fifo && dev->mapram[0x300] != dev->mapram[0x301]) {
dev->waiting_input_fifo = 0;
pgc_wake(dev);
}
break;
case 0x303: /* output read pointer */
if (dev->waiting_output_fifo && dev->mapram[0x302] != (uint8_t) (dev->mapram[0x303] - 1)) {
dev->waiting_output_fifo = 0;
pgc_wake(dev);
}
break;
case 0x305: /* error read pointer */
if (dev->waiting_error_fifo && dev->mapram[0x304] != (uint8_t) (dev->mapram[0x305] - 1)) {
dev->waiting_error_fifo = 0;
pgc_wake(dev);
}
break;
case 0x306: /* cold start flag */
/* XXX This should be in IM-1024 specific code */
dev->mapram[0x306] = 0;
break;
case 0x30c: /* display type */
pgc_setdisplay(priv, dev->mapram[0x30c]);
dev->mapram[0x30d] = dev->mapram[0x30c];
break;
case 0x3ff: /* reboot the PGC */
pgc_wake(dev);
break;
default:
break;
}
}
}
if (addr >= 0xb8000 && addr < 0xc0000 && dev->cga_selected) {
addr &= 0x3fff;
dev->cga_vram[addr] = val;
}
}
/* TODO: Check the CGA mapping repeat stuff. */
uint8_t
pgc_read(uint32_t addr, void *priv)
{
const pgc_t *dev = (pgc_t *) priv;
uint8_t ret = 0xff;
if (addr >= 0xc6000 && addr < 0xc6800) {
addr &= 0x7ff;
ret = dev->mapram[addr];
} else if (addr >= 0xb8000 && addr < 0xc0000 && dev->cga_selected) {
addr &= 0x3fff;
ret = dev->cga_vram[addr];
}
return ret;
}
/* Draw the display in CGA (640x400) text mode. */
void
pgc_cga_text(pgc_t *dev, int w)
{
uint8_t chr;
uint8_t attr;
int drawcursor = 0;
uint32_t cols[2];
int pitch = (dev->mapram[0x3e9] + 1) * 2;
uint16_t sc = (dev->displine & 0x0f) % pitch;
uint16_t ma = (dev->mapram[0x3ed] | (dev->mapram[0x3ec] << 8)) & 0x3fff;
uint16_t ca = (dev->mapram[0x3ef] | (dev->mapram[0x3ee] << 8)) & 0x3fff;
const uint8_t *addr;
uint32_t val;
int cw = (w == 80) ? 8 : 16;
addr = &dev->cga_vram[((ma + ((dev->displine / pitch) * w)) * 2) & 0x3ffe];
ma += (dev->displine / pitch) * w;
for (int x = 0; x < w; x++) {
chr = *addr++;
attr = *addr++;
/* Cursor enabled? */
if (ma == ca && (dev->cgablink & 8) && (dev->mapram[0x3ea] & 0x60) != 0x20) {
drawcursor = ((dev->mapram[0x3ea] & 0x1f) <= (sc >> 1)) && ((dev->mapram[0x3eb] & 0x1f) >= (sc >> 1));
} else
drawcursor = 0;
if (dev->mapram[0x3d8] & 0x20) {
cols[1] = (attr & 15) + 16;
cols[0] = ((attr >> 4) & 7) + 16;
if ((dev->cgablink & 8) && (attr & 0x80) && !drawcursor)
cols[1] = cols[0];
} else {
cols[1] = (attr & 15) + 16;
cols[0] = (attr >> 4) + 16;
}
for (int c = 0; c < cw; c++) {
if (drawcursor)
val = cols[(fontdatm[chr + dev->fontbase][sc] & (1 << (c ^ 7))) ? 1 : 0] ^ 0x0f;
else
val = cols[(fontdatm[chr + dev->fontbase][sc] & (1 << (c ^ 7))) ? 1 : 0];
if (cw == 8) /* 80x25 CGA text screen. */
buffer32->line[dev->displine][(x * cw) + c] = val;
else { /* 40x25 CGA text screen. */
buffer32->line[dev->displine][(x * cw) + (c * 2)] = val;
buffer32->line[dev->displine][(x * cw) + (c * 2) + 1] = val;
}
}
ma++;
}
}
/* Draw the display in CGA (320x200) graphics mode. */
void
pgc_cga_gfx40(pgc_t *dev)
{
uint32_t cols[4];
int col;
uint16_t ma = (dev->mapram[0x3ed] | (dev->mapram[0x3ec] << 8)) & 0x3fff;
const uint8_t *addr;
uint16_t dat;
cols[0] = (dev->mapram[0x3d9] & 15) + 16;
col = ((dev->mapram[0x3d9] & 16) ? 8 : 0) + 16;
/* From John Elliott's site:
On a real CGA, if bit 2 of port 03D8h and bit 5 of port 03D9h are both set,
the palette used in graphics modes is red/cyan/white. On a PGC, it's
magenta/cyan/white. You still get red/cyan/white if bit 5 of port 03D9h is
not set. This is a firmware issue rather than hardware. */
if (dev->mapram[0x3d9] & 32) {
cols[1] = col | 3;
cols[2] = col | 5;
cols[3] = col | 7;
} else if (dev->mapram[0x3d8] & 4) {
cols[1] = col | 3;
cols[2] = col | 4;
cols[3] = col | 7;
} else {
cols[1] = col | 2;
cols[2] = col | 4;
cols[3] = col | 6;
}
for (uint8_t x = 0; x < 40; x++) {
addr = &dev->cga_vram[(ma + 2 * x + 80 * (dev->displine >> 2) + 0x2000 * ((dev->displine >> 1) & 1)) & 0x3fff];
dat = (addr[0] << 8) | addr[1];
dev->ma++;
for (uint8_t c = 0; c < 8; c++) {
buffer32->line[dev->displine][(x << 4) + (c << 1)] = buffer32->line[dev->displine][(x << 4) + (c << 1) + 1] = cols[dat >> 14];
dat <<= 2;
}
}
}
/* Draw the display in CGA (640x200) graphics mode. */
void
pgc_cga_gfx80(pgc_t *dev)
{
uint32_t cols[2];
uint16_t ma = (dev->mapram[0x3ed] | (dev->mapram[0x3ec] << 8)) & 0x3fff;
const uint8_t *addr;
uint16_t dat;
cols[0] = 16;
cols[1] = (dev->mapram[0x3d9] & 15) + 16;
for (uint8_t x = 0; x < 40; x++) {
addr = &dev->cga_vram[(ma + 2 * x + 80 * (dev->displine >> 2) + 0x2000 * ((dev->displine >> 1) & 1)) & 0x3fff];
dat = (addr[0] << 8) | addr[1];
dev->ma++;
for (uint8_t c = 0; c < 16; c++) {
buffer32->line[dev->displine][(x << 4) + c] = cols[dat >> 15];
dat <<= 1;
}
}
}
/* Draw the screen in CGA mode. */
void
pgc_cga_poll(pgc_t *dev)
{
uint32_t cols[2];
if (!dev->linepos) {
timer_advance_u64(&dev->timer, dev->dispofftime);
dev->mapram[0x03da] |= 1;
dev->linepos = 1;
if (dev->cgadispon) {
if (dev->displine == 0)
video_wait_for_buffer();
if ((dev->mapram[0x03d8] & 0x12) == 0x12)
pgc_cga_gfx80(dev);
else if (dev->mapram[0x03d8] & 0x02)
pgc_cga_gfx40(dev);
else if (dev->mapram[0x03d8] & 0x01)
pgc_cga_text(dev, 80);
else
pgc_cga_text(dev, 40);
} else {
cols[0] = ((dev->mapram[0x03d8] & 0x12) == 0x12) ? 0 : ((dev->mapram[0x03d9] & 15) + 16);
hline(buffer32, 0, dev->displine, PGC_CGA_WIDTH, cols[0]);
}
video_process_8(PGC_CGA_WIDTH, dev->displine);
if (++dev->displine == PGC_CGA_HEIGHT) {
dev->mapram[0x3da] |= 8;
dev->cgadispon = 0;
}
if (dev->displine == PGC_CGA_HEIGHT + 32) {
dev->mapram[0x3da] &= ~8;
dev->cgadispon = 1;
dev->displine = 0;
}
} else {
if (dev->cgadispon)
dev->mapram[0x3da] &= ~1;
timer_advance_u64(&dev->timer, dev->dispontime);
dev->linepos = 0;
if (dev->displine == PGC_CGA_HEIGHT) {
if (PGC_CGA_WIDTH != xsize || PGC_CGA_HEIGHT != ysize) {
xsize = PGC_CGA_WIDTH;
ysize = PGC_CGA_HEIGHT;
set_screen_size(xsize, ysize);
if (video_force_resize_get())
video_force_resize_set(0);
}
video_blit_memtoscreen(0, 0, xsize, ysize);
frames++;
/* We have a fixed 640x400 screen for CGA modes. */
video_res_x = PGC_CGA_WIDTH;
video_res_y = PGC_CGA_HEIGHT;
switch (dev->mapram[0x3d8] & 0x12) {
case 0x12:
video_bpp = 1;
break;
case 0x02:
video_bpp = 2;
break;
default:
video_bpp = 0;
break;
}
dev->cgablink++;
}
}
}
/* Draw the screen in CGA or native mode. */
void
pgc_poll(void *priv)
{
pgc_t *dev = (pgc_t *) priv;
uint32_t y;
if (dev->cga_selected) {
pgc_cga_poll(dev);
return;
}
/* Not CGA, so must be native mode. */
if (!dev->linepos) {
timer_advance_u64(&dev->timer, dev->dispofftime);
dev->mapram[0x3da] |= 1;
dev->linepos = 1;
if (dev->cgadispon && (uint32_t) dev->displine < dev->maxh) {
if (dev->displine == 0)
video_wait_for_buffer();
/* Don't know why pan needs to be multiplied by -2, but
* the IM1024 driver uses PAN -112 for an offset of
* 224. */
y = dev->displine - 2 * dev->pan_y;
for (uint32_t x = 0; x < dev->screenw; x++) {
if (x + dev->pan_x < dev->maxw)
buffer32->line[dev->displine][x] = dev->palette[dev->vram[y * dev->maxw + x]];
else
buffer32->line[dev->displine][x] = dev->palette[0];
}
} else {
hline(buffer32, 0, dev->displine, dev->screenw, dev->palette[0]);
}
if (++dev->displine == dev->screenh) {
dev->mapram[0x3da] |= 8;
dev->cgadispon = 0;
}
if (dev->displine == dev->screenh + 32) {
dev->mapram[0x3da] &= ~8;
dev->cgadispon = 1;
dev->displine = 0;
}
} else {
if (dev->cgadispon)
dev->mapram[0x3da] &= ~1;
timer_advance_u64(&dev->timer, dev->dispontime);
dev->linepos = 0;
if (dev->displine == dev->screenh) {
if (dev->screenw != xsize || dev->screenh != ysize) {
xsize = dev->screenw;
ysize = dev->screenh;
set_screen_size(xsize, ysize);
if (video_force_resize_get())
video_force_resize_set(0);
}
video_blit_memtoscreen(0, 0, xsize, ysize);
frames++;
video_res_x = dev->screenw;
video_res_y = dev->screenh;
video_bpp = 8;
dev->cgablink++;
}
}
}
void
pgc_speed_changed(void *priv)
{
pgc_t *dev = (pgc_t *) priv;
pgc_recalctimings(dev);
}
void
pgc_close_common(void *priv)
{
pgc_t *dev = (pgc_t *) priv;
/*
* Close down the worker thread by setting a
* flag, and then simulating a reset so it
* stops reading data.
*/
#ifdef ENABLE_PGC_LOG
pgc_log("PGC: telling thread to stop...\n");
#endif
dev->stopped = 1;
dev->mapram[0x3ff] = 1;
if (dev->waiting_input_fifo || dev->waiting_output_fifo) {
/* Do an immediate wake-up. */
wake_timer(priv);
}
/* Wait for thread to stop. */
#ifdef ENABLE_PGC_LOG
pgc_log("PGC: waiting for thread to stop...\n");
#endif
// while (dev->stopped);
thread_wait(dev->pgc_thread);
#ifdef ENABLE_PGC_LOG
pgc_log("PGC: thread stopped, closing up.\n");
#endif
if (dev->cga_vram)
free(dev->cga_vram);
if (dev->vram)
free(dev->vram);
}
void
pgc_close(void *priv)
{
pgc_t *dev = (pgc_t *) priv;
pgc_close_common(priv);
free(dev);
}
/*
* Initialization code common to the PGC and its subclasses.
*
* Pass the 'input byte' function in since this is overridden in
* the IM-1024, and needs to be set before the drawing thread is
* launched.
*/
void
pgc_init(pgc_t *dev, int maxw, int maxh, int visw, int vish,
int (*inpbyte)(pgc_t *, uint8_t *), double npc)
{
/* Make it a 16k mapping at C4000 (will be C4000-C7FFF),
because of the emulator's granularity - the original
mapping will conflict with hard disk controller BIOS'es. */
mem_mapping_add(&dev->mapping, 0xc4000, 16384,
pgc_read, NULL, NULL, pgc_write, NULL, NULL,
NULL, MEM_MAPPING_EXTERNAL, dev);
mem_mapping_add(&dev->cga_mapping, 0xb8000, 32768,
pgc_read, NULL, NULL, pgc_write, NULL, NULL,
NULL, MEM_MAPPING_EXTERNAL, dev);
io_sethandler(0x03d0, 16,
pgc_in, NULL, NULL, pgc_out, NULL, NULL, dev);
dev->maxw = maxw;
dev->maxh = maxh;
dev->visw = visw;
dev->vish = vish;
dev->vram = (uint8_t *) malloc((size_t) maxw * maxh);
memset(dev->vram, 0x00, (size_t) maxw * maxh);
dev->cga_vram = (uint8_t *) malloc(16384);
memset(dev->cga_vram, 0x00, 16384);
/* Create and initialize command lists. */
dev->clist = (pgc_cl_t *) malloc(256 * sizeof(pgc_cl_t));
memset(dev->clist, 0x00, 256 * sizeof(pgc_cl_t));
for (uint16_t i = 0; i < 256; i++) {
dev->clist[i].list = NULL;
dev->clist[i].listmax = 0;
dev->clist[i].wrptr = 0;
dev->clist[i].rdptr = 0;
dev->clist[i].repeat = 0;
dev->clist[i].chain = NULL;
}
dev->clcur = NULL;
dev->native_pixel_clock = npc;
pgc_reset(dev);
dev->inputbyte = inpbyte;
dev->master = dev->commands = pgc_commands;
dev->pgc_wake_thread = thread_create_event();
dev->pgc_thread = thread_create(pgc_thread, dev);
timer_add(&dev->timer, pgc_poll, dev, 1);
timer_add(&dev->wake_timer, wake_timer, dev, 0);
}
static void *
pgc_standalone_init(const device_t *info)
{
pgc_t *dev;
dev = (pgc_t *) malloc(sizeof(pgc_t));
memset(dev, 0x00, sizeof(pgc_t));
dev->type = info->local;
/* Framebuffer and screen are both 640x480. */
pgc_init(dev, 640, 480, 640, 480, input_byte, 25175000.0);
video_inform(VIDEO_FLAG_TYPE_CGA, &timing_pgc);
return dev;
}
const device_t pgc_device = {
.name = "IBM PGC",
.internal_name = "pgc",
.flags = DEVICE_ISA,
.local = 0,
.init = pgc_standalone_init,
.close = pgc_close,
.reset = NULL,
{ .available = NULL },
.speed_changed = pgc_speed_changed,
.force_redraw = NULL,
.config = NULL
};
``` | /content/code_sandbox/src/video/vid_pgc.c | c | 2016-06-25T22:29:10 | 2024-08-16T19:09:21 | 86Box | 86Box/86Box | 2,616 | 22,325 |
```c
/*
* 86Box A hypervisor and IBM PC system emulator that specializes in
* running old operating systems and software designed for IBM
* PC systems and compatibles from 1981 through fairly recent
* system designs based on the PCI bus.
*
* This file is part of the 86Box distribution.
*
* Bochs VBE SVGA emulation.
*
* Uses code from libxcvt to calculate CRTC timings.
*
* Authors: Cacodemon345
* The Bochs Project
* Fabrice Bellard
* The libxcvt authors
*
*
* See path_to_url for libxcvt license details
*/
#include <stdbool.h>
#include <stdio.h>
#include <stdint.h>
#include <string.h>
#include <stdlib.h>
#include <wchar.h>
#include <86box/86box.h>
#include <86box/io.h>
#include <86box/mem.h>
#include <86box/rom.h>
#include <86box/device.h>
#include <86box/timer.h>
#include <86box/video.h>
#include <86box/vid_svga.h>
#include <86box/vid_svga_render.h>
#include <86box/pci.h>
#include <86box/i2c.h>
#include <86box/vid_ddc.h>
#define VBE_DISPI_BANK_SIZE_KB 64
#define VBE_DISPI_BANK_GRANULARITY_KB 32
#define VBE_DISPI_MAX_XRES 1920
#define VBE_DISPI_MAX_YRES 1600
#define VBE_DISPI_IOPORT_INDEX 0x01CE
#define VBE_DISPI_IOPORT_DATA 0x01CF
#define VBE_DISPI_INDEX_ID 0x0
#define VBE_DISPI_INDEX_XRES 0x1
#define VBE_DISPI_INDEX_YRES 0x2
#define VBE_DISPI_INDEX_BPP 0x3
#define VBE_DISPI_INDEX_ENABLE 0x4
#define VBE_DISPI_INDEX_BANK 0x5
#define VBE_DISPI_INDEX_VIRT_WIDTH 0x6
#define VBE_DISPI_INDEX_VIRT_HEIGHT 0x7
#define VBE_DISPI_INDEX_X_OFFSET 0x8
#define VBE_DISPI_INDEX_Y_OFFSET 0x9
#define VBE_DISPI_INDEX_VIDEO_MEMORY_64K 0xa
#define VBE_DISPI_INDEX_DDC 0xb
#define VBE_DISPI_ID0 0xB0C0
#define VBE_DISPI_ID1 0xB0C1
#define VBE_DISPI_ID2 0xB0C2
#define VBE_DISPI_ID3 0xB0C3
#define VBE_DISPI_ID4 0xB0C4
#define VBE_DISPI_ID5 0xB0C5
#define VBE_DISPI_DISABLED 0x00
#define VBE_DISPI_ENABLED 0x01
#define VBE_DISPI_GETCAPS 0x02
#define VBE_DISPI_BANK_GRANULARITY_32K 0x10
#define VBE_DISPI_8BIT_DAC 0x20
#define VBE_DISPI_LFB_ENABLED 0x40
#define VBE_DISPI_NOCLEARMEM 0x80
#define VBE_DISPI_BANK_WR 0x4000
#define VBE_DISPI_BANK_RD 0x8000
#define VBE_DISPI_BANK_RW 0xc000
typedef struct vbe_mode_info_t {
uint32_t hdisplay;
uint32_t vdisplay;
float vrefresh;
float hsync;
uint64_t dot_clock;
uint16_t hsync_start;
uint16_t hsync_end;
uint16_t htotal;
uint16_t vsync_start;
uint16_t vsync_end;
uint16_t vtotal;
} vbe_mode_info_t;
static video_timings_t timing_bochs = { .type = VIDEO_PCI, .write_b = 2, .write_w = 2, .write_l = 1, .read_b = 20, .read_w = 20, .read_l = 21 };
typedef struct bochs_vbe_t {
svga_t svga;
uint8_t pci_conf_status;
uint8_t pci_rom_enable;
uint8_t pci_line_interrupt;
uint8_t slot;
uint8_t pci_regs[256];
uint16_t vbe_index;
uint16_t bank_gran;
uint16_t rom_addr;
uint16_t id5_val;
uint16_t vbe_regs[16];
uint32_t vram_size;
rom_t bios_rom;
mem_mapping_t linear_mapping;
mem_mapping_t linear_mapping_2;
uint32_t ma_latch_old;
void * i2c;
void * ddc;
} bochs_vbe_t;
static bochs_vbe_t *reset_state = NULL;
static void
gen_mode_info(int hdisplay, int vdisplay, float vrefresh, vbe_mode_info_t* mode_info)
{
int vsync;
int vsync_and_back_porch;
mode_info->hdisplay = hdisplay;
mode_info->vdisplay = vdisplay;
mode_info->vrefresh = vrefresh;
/* 1) top/bottom margin size (% of height) - default: 1.8 */
#define CVT_MARGIN_PERCENTAGE 1.8
/* 2) character cell horizontal granularity (pixels) - default 8 */
#define CVT_H_GRANULARITY 8
/* 4) Minimum vertical front porch (lines) - default 3 */
#define CVT_MIN_V_PORCH_RND 3
/* 4) Minimum number of vertical back porch lines - default 6 */
#define CVT_MIN_V_BPORCH 6
/* Pixel Clock step (kHz) */
#define CVT_CLOCK_STEP 250
/* CVT default is 60.0Hz */
if (!mode_info->vrefresh)
mode_info->vrefresh = 60.0;
/* 1. Required field rate */
const float vfield_rate = mode_info->vrefresh;
/* 2. Horizontal pixels */
const int hdisplay_rnd = mode_info->hdisplay - (mode_info->hdisplay % CVT_H_GRANULARITY);
/* 3. Determine left and right borders */
const int hmargin = 0;
/* 4. Find total active pixels */
mode_info->hdisplay = hdisplay_rnd + (2 * hmargin);
/* 5. Find number of lines per field */
const int vdisplay_rnd = mode_info->vdisplay;
/* 6. Find top and bottom margins */
const int vmargin = 0;
mode_info->vdisplay = mode_info->vdisplay + 2 * vmargin;
/* 7. interlace */
/* Please rename this */
const float interlace = 0.0;
/* Determine vsync Width from aspect ratio */
if (!(mode_info->vdisplay % 3) && ((mode_info->vdisplay * 4 / 3) == mode_info->hdisplay))
vsync = 4;
else if (!(mode_info->vdisplay % 9) &&
((mode_info->vdisplay * 16 / 9) == mode_info->hdisplay))
vsync = 5;
else if (!(mode_info->vdisplay % 10) &&
((mode_info->vdisplay * 16 / 10) == mode_info->hdisplay))
vsync = 6;
else if (!(mode_info->vdisplay % 4) &&
((mode_info->vdisplay * 5 / 4) == mode_info->hdisplay))
vsync = 7;
else if (!(mode_info->vdisplay % 9) &&
((mode_info->vdisplay * 15 / 9) == mode_info->hdisplay))
vsync = 7;
else /* Custom */
vsync = 10;
/* Simplified GTF calculation. */
/* 4) Minimum time of vertical sync + back porch interval (s)
* default 550.0 */
#define CVT_MIN_VSYNC_BP 550.0
/* 3) Nominal HSync width (% of line period) - default 8 */
#define CVT_HSYNC_PERCENTAGE 8
/* 8. Estimated Horizontal period */
const float hperiod = ((float) (1000000.0 / vfield_rate - CVT_MIN_VSYNC_BP)) /
(vdisplay_rnd + 2 * vmargin + CVT_MIN_V_PORCH_RND + interlace);
/* 9. Find number of lines in sync + backporch */
if (((int) (CVT_MIN_VSYNC_BP / hperiod) + 1) < (vsync + CVT_MIN_V_BPORCH))
vsync_and_back_porch = vsync + CVT_MIN_V_BPORCH;
else
vsync_and_back_porch = (int) (CVT_MIN_VSYNC_BP / hperiod) + 1;
/* 10. Find number of lines in back porch */
/* 11. Find total number of lines in vertical field */
mode_info->vtotal = vdisplay_rnd + (2 * vmargin) + vsync_and_back_porch + interlace +
CVT_MIN_V_PORCH_RND;
/* 5) Definition of Horizontal blanking time limitation */
/* Gradient (%/kHz) - default 600 */
#define CVT_M_FACTOR 600
/* Offset (%) - default 40 */
#define CVT_C_FACTOR 40
/* Blanking time scaling factor - default 128 */
#define CVT_K_FACTOR 128
/* Scaling factor weighting - default 20 */
#define CVT_J_FACTOR 20
#define CVT_M_PRIME CVT_M_FACTOR * CVT_K_FACTOR / 256
#define CVT_C_PRIME (CVT_C_FACTOR - CVT_J_FACTOR) * CVT_K_FACTOR / 256 + \
CVT_J_FACTOR
/* 12. Find ideal blanking duty cycle from formula */
float hblank_percentage = CVT_C_PRIME - CVT_M_PRIME * hperiod / 1000.0;
/* 13. Blanking time */
if (hblank_percentage < 20)
hblank_percentage = 20;
int hblank = mode_info->hdisplay * hblank_percentage / (100.0 - hblank_percentage);
hblank -= hblank % (2 * CVT_H_GRANULARITY);
/* 14. Find total number of pixels in a line. */
mode_info->htotal = mode_info->hdisplay + hblank;
/* Fill in HSync values */
mode_info->hsync_end = mode_info->hdisplay + hblank / 2;
int hsync_w = (mode_info->htotal * CVT_HSYNC_PERCENTAGE) / 100;
hsync_w -= hsync_w % CVT_H_GRANULARITY;
mode_info->hsync_start = mode_info->hsync_end - hsync_w;
/* Fill in vsync values */
mode_info->vsync_start = mode_info->vdisplay + CVT_MIN_V_PORCH_RND;
mode_info->vsync_end = mode_info->vsync_start + vsync;
/* 15/13. Find pixel clock frequency (kHz for xf86) */
mode_info->dot_clock = mode_info->htotal * 1000.0 / hperiod;
mode_info->dot_clock -= mode_info->dot_clock % CVT_CLOCK_STEP;
/* 16/14. Find actual Horizontal Frequency (kHz) */
mode_info->hsync = ((float) mode_info->dot_clock) / ((float) mode_info->htotal);
/* 17/15. Find actual Field rate */
mode_info->vrefresh = (1000.0 * ((float) mode_info->dot_clock)) /
((float) (mode_info->htotal * mode_info->vtotal));
/* 18/16. Find actual vertical frame frequency */
/* ignore - we don't do interlace here */
}
void
bochs_vbe_recalctimings(svga_t* svga)
{
bochs_vbe_t *dev = (bochs_vbe_t *) svga->priv;
if (dev->vbe_regs[VBE_DISPI_INDEX_ENABLE] & VBE_DISPI_ENABLED) {
vbe_mode_info_t mode = { 0 };
svga->bpp = dev->vbe_regs[VBE_DISPI_INDEX_BPP];
dev->vbe_regs[VBE_DISPI_INDEX_XRES] &= ~7;
if (dev->vbe_regs[VBE_DISPI_INDEX_XRES] == 0) {
dev->vbe_regs[VBE_DISPI_INDEX_XRES] = 8;
}
if (dev->vbe_regs[VBE_DISPI_INDEX_VIRT_WIDTH] > VBE_DISPI_MAX_XRES)
dev->vbe_regs[VBE_DISPI_INDEX_VIRT_WIDTH] = VBE_DISPI_MAX_XRES;
if (dev->vbe_regs[VBE_DISPI_INDEX_VIRT_WIDTH] < dev->vbe_regs[VBE_DISPI_INDEX_XRES])
dev->vbe_regs[VBE_DISPI_INDEX_VIRT_WIDTH] = dev->vbe_regs[VBE_DISPI_INDEX_XRES];
if (dev->vbe_regs[VBE_DISPI_INDEX_X_OFFSET] > VBE_DISPI_MAX_XRES)
dev->vbe_regs[VBE_DISPI_INDEX_X_OFFSET] = VBE_DISPI_MAX_XRES;
if (dev->vbe_regs[VBE_DISPI_INDEX_Y_OFFSET] > VBE_DISPI_MAX_YRES)
dev->vbe_regs[VBE_DISPI_INDEX_Y_OFFSET] = VBE_DISPI_MAX_YRES;
if (dev->vbe_regs[VBE_DISPI_INDEX_YRES] == 0)
dev->vbe_regs[VBE_DISPI_INDEX_YRES] = 1;
if (dev->vbe_regs[VBE_DISPI_INDEX_YRES] > VBE_DISPI_MAX_YRES)
dev->vbe_regs[VBE_DISPI_INDEX_YRES] = VBE_DISPI_MAX_YRES;
gen_mode_info(dev->vbe_regs[VBE_DISPI_INDEX_XRES],
dev->vbe_regs[VBE_DISPI_INDEX_YRES], 72.f, &mode);
svga->char_width = 1;
svga->dots_per_clock = 1;
svga->clock = (cpuclock * (double) (1ULL << 32)) / (mode.dot_clock * 1000.);
svga->dispend = mode.vdisplay;
svga->hdisp = mode.hdisplay;
svga->vsyncstart = mode.vsync_start;
svga->vtotal = mode.vtotal;
svga->htotal = mode.htotal;
svga->hblankstart = mode.hdisplay;
svga->hblankend = mode.hdisplay + (mode.htotal - mode.hdisplay - 1);
svga->vblankstart = svga->dispend; /* no vertical overscan. */
svga->rowcount = 0;
svga->hoverride = 1;
if (dev->vbe_regs[VBE_DISPI_INDEX_BPP] != 4) {
svga->fb_only = 1;
svga->adv_flags |= FLAG_NO_SHIFT3;
} else {
svga->fb_only = 0;
svga->adv_flags &= ~FLAG_NO_SHIFT3;
}
svga->bpp = dev->vbe_regs[VBE_DISPI_INDEX_BPP];
if (svga->bpp == 4) {
svga->rowoffset = (dev->vbe_regs[VBE_DISPI_INDEX_VIRT_WIDTH] / 2) >> 3;
svga->ma_latch = (dev->vbe_regs[VBE_DISPI_INDEX_Y_OFFSET] * svga->rowoffset) +
(dev->vbe_regs[VBE_DISPI_INDEX_X_OFFSET] >> 3);
} else {
svga->rowoffset = dev->vbe_regs[VBE_DISPI_INDEX_VIRT_WIDTH] * ((svga->bpp == 15) ? 2 : (svga->bpp / 8));
svga->ma_latch = (dev->vbe_regs[VBE_DISPI_INDEX_Y_OFFSET] * svga->rowoffset) +
(dev->vbe_regs[VBE_DISPI_INDEX_X_OFFSET] * ((svga->bpp == 15) ? 2 : (svga->bpp / 8)));
}
if (svga->ma_latch != dev->ma_latch_old) {
if (svga->bpp == 4) {
svga->maback = (svga->maback - (dev->ma_latch_old << 2)) +
(svga->ma_latch << 2);
} else {
svga->maback = (svga->maback - (dev->ma_latch_old)) +
(svga->ma_latch);
dev->ma_latch_old = svga->ma_latch;
}
}
if (svga->bpp == 4)
dev->vbe_regs[VBE_DISPI_INDEX_VIRT_HEIGHT] = (svga->vram_max * 2) / dev->vbe_regs[VBE_DISPI_INDEX_VIRT_WIDTH];
else
dev->vbe_regs[VBE_DISPI_INDEX_VIRT_HEIGHT] = (svga->vram_max / ((svga->bpp == 15) ? 2 : (svga->bpp / 8))) / dev->vbe_regs[VBE_DISPI_INDEX_VIRT_WIDTH];
svga->split = 0xffffff;
switch (svga->bpp) {
case 4:
svga->render = svga_render_4bpp_highres;
break;
default:
case 8:
svga->render = svga_render_8bpp_clone_highres;
break;
case 15:
svga->render = svga_render_15bpp_highres;
break;
case 16:
svga->render = svga_render_16bpp_highres;
break;
case 24:
svga->render = svga_render_24bpp_highres;
break;
case 32:
svga->render = svga_render_32bpp_highres;
break;
}
} else {
svga->fb_only = 0;
svga->packed_4bpp = 0;
svga->adv_flags &= ~FLAG_NO_SHIFT3;
svga->hoverride = 0;
}
}
uint16_t
bochs_vbe_inw(const uint16_t addr, void *priv)
{
const bochs_vbe_t *dev = (bochs_vbe_t *) priv;
const bool vbe_get_caps = !!(dev->vbe_regs[VBE_DISPI_INDEX_ENABLE] &
VBE_DISPI_GETCAPS);
uint16_t ret;
if (addr == 0x1ce)
ret = dev->vbe_index;
else switch (dev->vbe_index) {
default:
ret = dev->vbe_regs[dev->vbe_index];
break;
case VBE_DISPI_INDEX_XRES:
ret = vbe_get_caps ? VBE_DISPI_MAX_XRES : dev->vbe_regs[dev->vbe_index];
break;
case VBE_DISPI_INDEX_YRES:
ret = vbe_get_caps ? VBE_DISPI_MAX_YRES : dev->vbe_regs[dev->vbe_index];
break;
case VBE_DISPI_INDEX_BPP:
ret = vbe_get_caps ? 32 : dev->vbe_regs[dev->vbe_index];
break;
case VBE_DISPI_INDEX_VIDEO_MEMORY_64K:
ret = dev->vram_size >> 16;
break;
case VBE_DISPI_INDEX_BANK:
ret = vbe_get_caps ? (VBE_DISPI_BANK_GRANULARITY_32K << 8) :
dev->vbe_regs[dev->vbe_index];
break;
case VBE_DISPI_INDEX_DDC:
if (dev->vbe_regs[dev->vbe_index] & (1 << 7)) {
ret = dev->vbe_regs[dev->vbe_index] & ((1 << 7) | 0x3);
if ((ret & 0x01) && i2c_gpio_get_scl(dev->i2c))
ret |= 0x04;
if ((ret & 0x02) && i2c_gpio_get_sda(dev->i2c))
ret |= 0x08;
} else
ret = 0x000f;
break;
}
return ret;
}
uint32_t
bochs_vbe_inl(const uint16_t addr, void *priv)
{
const bochs_vbe_t *dev = (bochs_vbe_t *) priv;
uint32_t ret;
if (addr == 0x1ce)
ret = dev->vbe_index;
else
ret = dev->vram_size;
return ret;
}
void
bochs_vbe_outw(const uint16_t addr, const uint16_t val, void *priv)
{
bochs_vbe_t *dev = (bochs_vbe_t *) priv;
if (addr == 0x1ce)
dev->vbe_index = val;
else if ((addr == 0x1cf) || (addr == 0x1d0)) switch (dev->vbe_index) {
default:
break;
case VBE_DISPI_INDEX_ID:
if ((val == VBE_DISPI_ID0) || (val == VBE_DISPI_ID1) ||
(val == VBE_DISPI_ID2) || (val == VBE_DISPI_ID3) ||
(val == VBE_DISPI_ID4))
dev->vbe_regs[dev->vbe_index] = val;
else if (val == VBE_DISPI_ID5)
dev->vbe_regs[dev->vbe_index] = dev->id5_val;
break;
case VBE_DISPI_INDEX_XRES:
case VBE_DISPI_INDEX_YRES:
case VBE_DISPI_INDEX_BPP:
case VBE_DISPI_INDEX_VIRT_WIDTH:
case VBE_DISPI_INDEX_X_OFFSET:
case VBE_DISPI_INDEX_Y_OFFSET:
dev->vbe_regs[dev->vbe_index] = val;
if (dev->vbe_index == VBE_DISPI_INDEX_X_OFFSET || dev->vbe_index == VBE_DISPI_INDEX_Y_OFFSET) {
svga_t *svga = &dev->svga;
if (svga->bpp == 4) {
svga->rowoffset = (dev->vbe_regs[VBE_DISPI_INDEX_VIRT_WIDTH] / 2) >> 3;
svga->ma_latch = (dev->vbe_regs[VBE_DISPI_INDEX_Y_OFFSET] * svga->rowoffset) +
(dev->vbe_regs[VBE_DISPI_INDEX_X_OFFSET] >> 3);
} else {
svga->rowoffset = dev->vbe_regs[VBE_DISPI_INDEX_VIRT_WIDTH] * ((svga->bpp == 15) ? 2 : (svga->bpp / 8));
svga->ma_latch = (dev->vbe_regs[VBE_DISPI_INDEX_Y_OFFSET] * svga->rowoffset) +
(dev->vbe_regs[VBE_DISPI_INDEX_X_OFFSET] * ((svga->bpp == 15) ? 2 : (svga->bpp / 8)));
}
if (svga->ma_latch != dev->ma_latch_old) {
if (svga->bpp == 4) {
svga->maback = (svga->maback - (dev->ma_latch_old << 2)) +
(svga->ma_latch << 2);
} else {
svga->maback = (svga->maback - (dev->ma_latch_old)) +
(svga->ma_latch);
dev->ma_latch_old = svga->ma_latch;
}
}
}
else
svga_recalctimings(&dev->svga);
break;
case VBE_DISPI_INDEX_BANK:
if (val & VBE_DISPI_BANK_RD)
dev->svga.read_bank = (val & 0x1ff) * (dev->bank_gran << 10);
if (val & VBE_DISPI_BANK_WR)
dev->svga.write_bank = (val & 0x1ff) * (dev->bank_gran << 10);
break;
case VBE_DISPI_INDEX_DDC:
if (val & (1 << 7)) {
i2c_gpio_set(dev->i2c, !!(val & 1), !!(val & 2));
dev->vbe_regs[dev->vbe_index] = val;
} else
dev->vbe_regs[dev->vbe_index] &= ~(1 << 7);
break;
case VBE_DISPI_INDEX_ENABLE: {
uint32_t new_bank_gran;
dev->vbe_regs[dev->vbe_index] = val;
if ((val & VBE_DISPI_ENABLED) &&
!(dev->vbe_regs[VBE_DISPI_ENABLED] & VBE_DISPI_ENABLED)) {
dev->vbe_regs[dev->vbe_index] = val;
dev->vbe_regs[VBE_DISPI_INDEX_X_OFFSET] = 0;
dev->vbe_regs[VBE_DISPI_INDEX_Y_OFFSET] = 0;
dev->vbe_regs[VBE_DISPI_INDEX_VIRT_WIDTH] = 0;
svga_recalctimings(&dev->svga);
if (!(val & VBE_DISPI_NOCLEARMEM)) {
memset(dev->svga.vram, 0,
dev->vbe_regs[VBE_DISPI_INDEX_YRES] * dev->svga.rowoffset);
}
} else
dev->svga.read_bank = dev->svga.write_bank = 0;
if ((val & VBE_DISPI_BANK_GRANULARITY_32K) != 0)
new_bank_gran = 32;
else
new_bank_gran = 64;
if (dev->bank_gran != new_bank_gran) {
dev->bank_gran = new_bank_gran;
dev->svga.read_bank = dev->svga.write_bank = 0;
}
if (val & VBE_DISPI_8BIT_DAC)
dev->svga.adv_flags &= ~FLAG_RAMDAC_SHIFT;
else
dev->svga.adv_flags |= FLAG_RAMDAC_SHIFT;
dev->vbe_regs[dev->vbe_index] &= ~VBE_DISPI_NOCLEARMEM;
}
}
}
void
bochs_vbe_outl(const uint16_t addr, const uint32_t val, void *priv)
{
bochs_vbe_outw(addr, val & 0xffff, priv);
bochs_vbe_outw(addr + 2, val >> 16, priv);
}
void
bochs_vbe_out(uint16_t addr, uint8_t val, void *priv)
{
bochs_vbe_t *dev = (bochs_vbe_t *) priv;
svga_t * svga = &dev->svga;
uint8_t old;
if (((addr & 0xfff0) == 0x3d0 || (addr & 0xfff0) == 0x3b0) && !(svga->miscout & 1))
addr ^= 0x60;
switch (addr) {
case VBE_DISPI_IOPORT_INDEX:
dev->vbe_index = val;
return;
case VBE_DISPI_IOPORT_DATA:
bochs_vbe_outw(0x1cf, val | (bochs_vbe_inw(0x1cf, dev) & 0xFF00), dev);
return;
case VBE_DISPI_IOPORT_DATA + 1:
bochs_vbe_outw(0x1cf, (val << 8) | (bochs_vbe_inw(0x1cf, dev) & 0xFF), dev);
return;
case 0x3D4:
svga->crtcreg = val & 0x3f;
return;
case 0x3D5:
if (svga->crtcreg & 0x20)
return;
if ((svga->crtcreg < 7) && (svga->crtc[0x11] & 0x80))
return;
if ((svga->crtcreg == 7) && (svga->crtc[0x11] & 0x80))
val = (svga->crtc[7] & ~0x10) | (val & 0x10);
old = svga->crtc[svga->crtcreg];
svga->crtc[svga->crtcreg] = val;
if (old != val) {
if (svga->crtcreg < 0xe || svga->crtcreg > 0x10) {
if ((svga->crtcreg == 0xc) || (svga->crtcreg == 0xd)) {
svga->fullchange = 3;
svga->ma_latch = ((svga->crtc[0xc] << 8) | svga->crtc[0xd]) + ((svga->crtc[8] & 0x60) >> 5);
} else {
svga->fullchange = changeframecount;
svga_recalctimings(svga);
}
}
}
break;
default:
break;
}
svga_out(addr, val, svga);
}
uint8_t
bochs_vbe_in(uint16_t addr, void *priv)
{
bochs_vbe_t *dev = (bochs_vbe_t *) priv;
svga_t * svga = &dev->svga;
uint8_t ret;
if (((addr & 0xfff0) == 0x3d0 || (addr & 0xfff0) == 0x3b0) && !(svga->miscout & 1))
addr ^= 0x60;
switch (addr) {
default:
ret = svga_in(addr, svga);
break;
case VBE_DISPI_IOPORT_INDEX:
ret = dev->vbe_index;
break;
case VBE_DISPI_IOPORT_DATA:
ret = bochs_vbe_inw(0x1cf, dev);
break;
case VBE_DISPI_IOPORT_DATA + 1:
ret = bochs_vbe_inw(0x1cf, dev) >> 8;
break;
case 0x3D4:
ret = svga->crtcreg;
break;
case 0x3D5:
if (svga->crtcreg & 0x20)
ret = 0xff;
else
ret = svga->crtc[svga->crtcreg];
break;
}
return ret;
}
static uint8_t
bochs_vbe_pci_read(const int func, const int addr, void *priv)
{
const bochs_vbe_t *dev = (bochs_vbe_t *) priv;
uint8_t ret = 0x00;
if (func == 0x00) switch (addr) {
default:
break;
case 0x00:
ret = (dev->id5_val == VBE_DISPI_ID5) ? 0x34 : 0xee;
break;
case 0x01:
ret = (dev->id5_val == VBE_DISPI_ID5) ? 0x12 : 0x80;
break;
case 0x02:
ret = (dev->id5_val == VBE_DISPI_ID5) ? 0x11 : 0xef;
break;
case 0x03:
ret = (dev->id5_val == VBE_DISPI_ID5) ? 0x11 : 0xbe;
break;
case 0x04:
ret = (dev->pci_conf_status & 0b11100011) | 0x80;
break;
case 0x06:
ret = 0x80;
break;
case 0x07:
ret = 0x02;
break;
case 0x0b:
ret = 0x03;
break;
case 0x13:
ret = dev->pci_regs[addr];
break;
case 0x17:
ret = (dev->pci_regs[0x13] != 0x00) ? 0xe0 : 0x00;
break;
case 0x30:
ret = dev->pci_rom_enable & 0x01;
break;
case 0x32:
ret = dev->rom_addr & 0xff;
break;
case 0x33:
ret = (dev->rom_addr & 0xff00) >> 8;
break;
case 0x3c:
ret = dev->pci_line_interrupt;
break;
case 0x3d:
ret = 0x01;
break;
} else
ret = 0xff;
return ret;
}
static void
bochs_vbe_disable_handlers(bochs_vbe_t *dev)
{
io_removehandler(0x03c0, 0x0020, bochs_vbe_in, NULL, NULL,
bochs_vbe_out, NULL, NULL, dev);
io_removehandler(0x01ce, 0x0003, bochs_vbe_in, bochs_vbe_inw,
bochs_vbe_inl, bochs_vbe_out, bochs_vbe_outw, bochs_vbe_outl, dev);
mem_mapping_disable(&dev->linear_mapping_2);
mem_mapping_disable(&dev->linear_mapping);
mem_mapping_disable(&dev->svga.mapping);
mem_mapping_disable(&dev->bios_rom.mapping);
/* Save all the mappings and the timers because they are part of linked lists. */
reset_state->linear_mapping_2 = dev->linear_mapping_2;
reset_state->linear_mapping = dev->linear_mapping;
reset_state->svga.mapping = dev->svga.mapping;
reset_state->bios_rom.mapping = dev->bios_rom.mapping;
reset_state->svga.timer = dev->svga.timer;
reset_state->svga.timer8514 = dev->svga.timer8514;
}
static void
bochs_vbe_pci_write(const int func, const int addr, const uint8_t val, void *priv)
{
bochs_vbe_t *dev = (bochs_vbe_t *) priv;
if (func == 0x00) switch (addr) {
default:
break;
case 0x04:
dev->pci_conf_status = val;
io_removehandler(0x03c0, 0x0020, bochs_vbe_in, NULL, NULL,
bochs_vbe_out, NULL, NULL, dev);
io_removehandler(0x01ce, 0x0003, bochs_vbe_in, bochs_vbe_inw,
bochs_vbe_inl, bochs_vbe_out, bochs_vbe_outw, bochs_vbe_outl, dev);
mem_mapping_disable(&dev->linear_mapping_2);
mem_mapping_disable(&dev->linear_mapping);
mem_mapping_disable(&dev->svga.mapping);
if (dev->pci_conf_status & PCI_COMMAND_IO) {
io_sethandler(0x03c0, 0x0020, bochs_vbe_in, NULL, NULL,
bochs_vbe_out, NULL, NULL, dev);
io_sethandler(0x01ce, 0x0003, bochs_vbe_in, bochs_vbe_inw, bochs_vbe_inl,
bochs_vbe_out, bochs_vbe_outw, bochs_vbe_outl, dev);
}
if (dev->pci_conf_status & PCI_COMMAND_MEM) {
mem_mapping_enable(&dev->svga.mapping);
if (dev->pci_regs[0x13] != 0x00) {
mem_mapping_enable(&dev->linear_mapping);
if (dev->pci_regs[0x13] != 0xe0)
mem_mapping_enable(&dev->linear_mapping_2);
}
}
break;
case 0x13:
dev->pci_regs[addr] = val;
mem_mapping_disable(&dev->linear_mapping_2);
mem_mapping_disable(&dev->linear_mapping);
if ((dev->pci_conf_status & PCI_COMMAND_MEM) && (val != 0x00)) {
mem_mapping_set_addr(&dev->linear_mapping, val << 24, 0x01000000);
if (val != 0xe0)
mem_mapping_set_addr(&dev->linear_mapping_2, 0xe0000000, 0x01000000);
}
break;
case 0x3c:
dev->pci_line_interrupt = val;
break;
case 0x30:
dev->pci_rom_enable = val & 0x01;
mem_mapping_disable(&dev->bios_rom.mapping);
if (dev->pci_rom_enable)
mem_mapping_set_addr(&dev->bios_rom.mapping, dev->rom_addr << 16, 0x10000);
break;
case 0x32:
dev->rom_addr = (dev->rom_addr & 0xff00) | (val & 0xfc);
if (dev->pci_rom_enable)
mem_mapping_set_addr(&dev->bios_rom.mapping, dev->rom_addr << 16, 0x10000);
break;
case 0x33:
dev->rom_addr = (dev->rom_addr & 0x00ff) | (val << 8);
if (dev->pci_rom_enable)
mem_mapping_set_addr(&dev->bios_rom.mapping, dev->rom_addr << 16, 0x10000);
break;
}
}
static void
bochs_vbe_reset(void *priv)
{
bochs_vbe_t *dev = (bochs_vbe_t *) priv;
if (reset_state != NULL) {
bochs_vbe_disable_handlers(dev);
reset_state->slot = dev->slot;
*dev = *reset_state;
}
}
static void *
bochs_vbe_init(const device_t *info)
{
bochs_vbe_t *dev = calloc(1, sizeof(bochs_vbe_t));
reset_state = calloc(1, sizeof(bochs_vbe_t));
dev->id5_val = device_get_config_int("revision");
dev->vram_size = device_get_config_int("memory") * (1 << 20);
rom_init(&dev->bios_rom, "roms/video/bochs/VGABIOS-lgpl-latest.bin",
0xc0000, 0x10000, 0xffff, 0x0000,
MEM_MAPPING_EXTERNAL);
if (dev->id5_val == VBE_DISPI_ID4) {
/* Patch the BIOS to match the PCI ID. */
dev->bios_rom.rom[0x010c] = 0xee;
dev->bios_rom.rom[0x8dff] -= (0xee - 0x34);
dev->bios_rom.rom[0x010d] = 0x80;
dev->bios_rom.rom[0x8dff] -= (0x80 - 0x12);
dev->bios_rom.rom[0x010e] = 0xef;
dev->bios_rom.rom[0x8dff] -= (0xef - 0x11);
dev->bios_rom.rom[0x010f] = 0xbe;
dev->bios_rom.rom[0x8dff] -= (0xbe - 0x11);
}
video_inform(VIDEO_FLAG_TYPE_SPECIAL, &timing_bochs);
svga_init(info, &dev->svga, dev, dev->vram_size,
bochs_vbe_recalctimings,
bochs_vbe_in, bochs_vbe_out,
NULL,
NULL);
mem_mapping_add(&dev->linear_mapping, 0, 0,
svga_readb_linear, svga_readw_linear, svga_readl_linear,
svga_writeb_linear, svga_writew_linear, svga_writel_linear,
NULL, MEM_MAPPING_EXTERNAL, &dev->svga);
/* Hack: If the mapping gets mapped anywhere other than at 0xe0000000,
enable this second copy of it at 0xe0000000 so michaln's driver works. */
mem_mapping_add(&dev->linear_mapping_2, 0, 0,
svga_readb_linear, svga_readw_linear, svga_readl_linear,
svga_writeb_linear, svga_writew_linear, svga_writel_linear,
NULL, MEM_MAPPING_EXTERNAL, &dev->svga);
mem_mapping_disable(&dev->bios_rom.mapping);
mem_mapping_disable(&dev->svga.mapping);
mem_mapping_disable(&dev->linear_mapping);
mem_mapping_disable(&dev->linear_mapping_2);
dev->svga.bpp = 8;
dev->svga.miscout = 1;
dev->bank_gran = 64;
svga_set_ramdac_type(&dev->svga, RAMDAC_8BIT);
dev->svga.adv_flags |= FLAG_RAMDAC_SHIFT;
dev->svga.decode_mask = 0xffffff;
dev->i2c = i2c_gpio_init("ddc_bochs");
dev->ddc = ddc_init(i2c_gpio_get_bus(dev->i2c));
dev->svga.packed_chain4 = 1;
pci_add_card(PCI_ADD_NORMAL, bochs_vbe_pci_read, bochs_vbe_pci_write, dev, &dev->slot);
*reset_state = *dev;
return dev;
}
static int
bochs_vbe_available(void)
{
return rom_present("roms/video/bochs/VGABIOS-lgpl-latest.bin");
}
void
bochs_vbe_close(void *priv)
{
bochs_vbe_t *dev = (bochs_vbe_t *) priv;
ddc_close(dev->ddc);
i2c_gpio_close(dev->i2c);
svga_close(&dev->svga);
free(reset_state);
reset_state = NULL;
free(dev);
}
void
bochs_vbe_speed_changed(void *priv)
{
bochs_vbe_t *bochs_vbe = (bochs_vbe_t *) priv;
svga_recalctimings(&bochs_vbe->svga);
}
void
bochs_vbe_force_redraw(void *priv)
{
bochs_vbe_t *bochs_vbe = (bochs_vbe_t *) priv;
bochs_vbe->svga.fullchange = changeframecount;
}
static const device_config_t bochs_vbe_config[] = {
// clang-format off
{
.name = "revision",
.description = "Revision",
.type = CONFIG_SELECTION,
.selection = {
{
.description = "VirtualBox",
.value = VBE_DISPI_ID4
},
{
.description = "Bochs latest",
.value = VBE_DISPI_ID5
},
{
.description = ""
}
},
.default_int = VBE_DISPI_ID5
},
{
.name = "memory",
.description = "Memory size",
.type = CONFIG_SELECTION,
.selection = {
{
.description = "4 MB",
.value = 4
},
{
.description = "8 MB",
.value = 8
},
{
.description = "16 MB",
.value = 16
},
{
.description = ""
}
},
.default_int = 16
},
{
.type = CONFIG_END
}
// clang-format on
};
const device_t bochs_svga_device = {
.name = "Bochs SVGA",
.internal_name = "bochs_svga",
.flags = DEVICE_PCI,
.local = 0,
.init = bochs_vbe_init,
.close = bochs_vbe_close,
.reset = bochs_vbe_reset,
{ .available = bochs_vbe_available },
.speed_changed = bochs_vbe_speed_changed,
.force_redraw = bochs_vbe_force_redraw,
.config = bochs_vbe_config
};
``` | /content/code_sandbox/src/video/vid_bochs_vbe.c | c | 2016-06-25T22:29:10 | 2024-08-16T19:09:21 | 86Box | 86Box/86Box | 2,616 | 9,996 |
```c
/*
* 86Box A hypervisor and IBM PC system emulator that specializes in
* running old operating systems and software designed for IBM
* PC systems and compatibles from 1981 through fairly recent
* system designs based on the PCI bus.
*
* This file is part of the 86Box distribution.
*
* Trident TKD8001 RAMDAC emulation.
*
*
*
* Authors: Sarah Walker, <path_to_url
* Miran Grca, <mgrca8@gmail.com>
*
*/
#include <stdio.h>
#include <stdint.h>
#include <stdlib.h>
#include <string.h>
#include <wchar.h>
#include <86box/86box.h>
#include <86box/device.h>
#include <86box/timer.h>
#include <86box/mem.h>
#include <86box/video.h>
#include <86box/vid_svga.h>
#include <86box/plat_unused.h>
typedef struct tkd8001_ramdac_t {
int state;
uint8_t ctrl;
} tkd8001_ramdac_t;
void
tkd8001_ramdac_out(uint16_t addr, uint8_t val, void *priv, svga_t *svga)
{
tkd8001_ramdac_t *ramdac = (tkd8001_ramdac_t *) priv;
switch (addr) {
case 0x3C6:
if (ramdac->state == 4) {
ramdac->state = 0;
ramdac->ctrl = val;
switch (val >> 5) {
case 0:
case 1:
case 2:
case 3:
svga->bpp = 8;
break;
case 5:
svga->bpp = 15;
break;
case 6:
svga->bpp = 24;
break;
case 7:
svga->bpp = 16;
break;
default:
break;
}
return;
}
break;
case 0x3C7:
case 0x3C8:
case 0x3C9:
ramdac->state = 0;
break;
default:
break;
}
svga_out(addr, val, svga);
}
uint8_t
tkd8001_ramdac_in(uint16_t addr, void *priv, svga_t *svga)
{
tkd8001_ramdac_t *ramdac = (tkd8001_ramdac_t *) priv;
switch (addr) {
case 0x3C6:
if (ramdac->state == 4)
return ramdac->ctrl;
ramdac->state++;
break;
case 0x3C7:
case 0x3C8:
case 0x3C9:
ramdac->state = 0;
break;
default:
break;
}
return svga_in(addr, svga);
}
static void *
tkd8001_ramdac_init(UNUSED(const device_t *info))
{
tkd8001_ramdac_t *ramdac = (tkd8001_ramdac_t *) malloc(sizeof(tkd8001_ramdac_t));
memset(ramdac, 0, sizeof(tkd8001_ramdac_t));
return ramdac;
}
static void
tkd8001_ramdac_close(void *priv)
{
tkd8001_ramdac_t *ramdac = (tkd8001_ramdac_t *) priv;
if (ramdac)
free(ramdac);
}
const device_t tkd8001_ramdac_device = {
.name = "Trident TKD8001 RAMDAC",
.internal_name = "tkd8001_ramdac",
.flags = 0,
.local = 0,
.init = tkd8001_ramdac_init,
.close = tkd8001_ramdac_close,
.reset = NULL,
{ .available = NULL },
.speed_changed = NULL,
.force_redraw = NULL,
.config = NULL
};
``` | /content/code_sandbox/src/video/vid_tkd8001_ramdac.c | c | 2016-06-25T22:29:10 | 2024-08-16T19:09:21 | 86Box | 86Box/86Box | 2,616 | 887 |
```c
/*
* 86Box A hypervisor and IBM PC system emulator that specializes in
* running old operating systems and software designed for IBM
* PC systems and compatibles from 1981 through fairly recent
* system designs based on the PCI bus.
*
* This file is part of the 86Box distribution.
*
* Emulation of the EGA and Chips & Technologies SuperEGA
* graphics cards.
*
*
*
* Authors: Sarah Walker, <path_to_url
* Miran Grca, <mgrca8@gmail.com>
*
*/
#include <stdbool.h>
#include <stdio.h>
#include <stdint.h>
#include <string.h>
#include <stdlib.h>
#include <wchar.h>
#include <86box/86box.h>
#include "cpu.h"
#include <86box/io.h>
#include <86box/timer.h>
#include <86box/pic.h>
#include <86box/pit.h>
#include <86box/mem.h>
#include <86box/rom.h>
#include <86box/device.h>
#include <86box/video.h>
#include <86box/vid_ati_eeprom.h>
#include <86box/vid_ega.h>
void ega_doblit(int wx, int wy, ega_t *ega);
#define BIOS_IBM_PATH "roms/video/ega/ibm_6277356_ega_card_u44_27128.bin"
#define BIOS_CPQ_PATH "roms/video/ega/108281-001.bin"
#define BIOS_SEGA_PATH "roms/video/ega/lega.vbi"
#define BIOS_ATIEGA800P_PATH "roms/video/ega/ATI EGA Wonder 800+ N1.00.BIN"
#define BIOS_ISKRA_PATH "roms/video/ega/143-02.bin", "roms/video/ega/143-03.bin"
#define BIOS_TSENG_PATH "roms/video/ega/EGA ET2000.BIN"
enum {
EGA_IBM = 0,
EGA_COMPAQ,
EGA_SUPEREGA,
EGA_ATI800P,
EGA_ISKRA,
EGA_TSENG
};
enum {
EGA_TYPE_IBM = 0,
EGA_TYPE_OTHER = 1,
EGA_TYPE_COMPAQ = 2
};
static video_timings_t timing_ega = { .type = VIDEO_ISA, .write_b = 8, .write_w = 16, .write_l = 32, .read_b = 8, .read_w = 16, .read_l = 32 };
static uint8_t ega_rotate[8][256];
static int active = 0;
static uint32_t pallook16[256];
static uint32_t pallook64[256];
static int ega_type = EGA_TYPE_IBM;
static int old_overscan_color = 0;
/* 3C2 controls default mode on EGA. On VGA, it determines monitor type (mono or colour):
7=CGA mode (200 lines), 9=EGA mode (350 lines), 8=EGA mode (200 lines). */
int egaswitchread;
int egaswitches = 9;
int update_overscan = 0;
uint8_t ega_in(uint16_t addr, void *priv);
void
ega_out(uint16_t addr, uint8_t val, void *priv)
{
ega_t *ega = (ega_t *) priv;
uint8_t o;
uint8_t old;
if (((addr & 0xfff0) == 0x3d0 || (addr & 0xfff0) == 0x3b0) && !(ega->miscout & 1))
addr ^= 0x60;
switch (addr) {
case 0x1ce:
ega->index = val;
break;
case 0x1cf:
ega->regs[ega->index] = val;
switch (ega->index) {
case 0xb0:
ega_recalctimings(ega);
break;
case 0xb3:
ati_eeprom_write((ati_eeprom_t *) ega->eeprom, val & 8, val & 2, val & 1);
break;
default:
break;
}
break;
case 0x3c0:
case 0x3c1:
if (!ega->attrff) {
ega->attraddr = val & 31;
if ((val & 0x20) != ega->attr_palette_enable) {
ega->fullchange = 3;
ega->attr_palette_enable = val & 0x20;
ega_recalctimings(ega);
}
} else {
if ((ega->attraddr == 0x13) && (ega->attrregs[0x13] != val))
ega->fullchange = changeframecount;
o = ega->attrregs[ega->attraddr & 31];
ega->attrregs[ega->attraddr & 31] = val;
if (ega->attraddr < 16)
ega->fullchange = changeframecount;
if (ega->attraddr == 0x10 || ega->attraddr == 0x14 || ega->attraddr < 0x10) {
for (uint8_t c = 0; c < 16; c++) {
if (ega->attrregs[0x10] & 0x80)
ega->egapal[c] = (ega->attrregs[c] & 0xf) | ((ega->attrregs[0x14] & 0xf) << 4);
else
ega->egapal[c] = (ega->attrregs[c] & 0x3f) | ((ega->attrregs[0x14] & 0xc) << 4);
}
ega->fullchange = changeframecount;
}
/* Recalculate timings on change of attribute register 0x11
(overscan border color) too. */
if (ega->attraddr == 0x10) {
if (o != val)
ega_recalctimings(ega);
} else if (ega->attraddr == 0x11) {
ega->overscan_color = ega->vres ? pallook16[val & 0x0f] : pallook64[val & 0x3f];
if (o != val)
ega_recalctimings(ega);
} else if (ega->attraddr == 0x12)
ega->plane_mask = val & 0xf;
}
ega->attrff ^= 1;
break;
case 0x3c2:
o = ega->miscout;
egaswitchread = (val & 0xc) >> 2;
ega->vres = !(val & 0x80);
ega->pallook = ega->vres ? pallook16 : pallook64;
ega->vidclock = val & 4;
ega->miscout = val;
ega->overscan_color = ega->vres ? pallook16[ega->attrregs[0x11] & 0x0f] : pallook64[ega->attrregs[0x11] & 0x3f];
io_removehandler(0x03a0, 0x0020, ega_in, NULL, NULL, ega_out, NULL, NULL, ega);
if (!(val & 1))
io_sethandler(0x03a0, 0x0020, ega_in, NULL, NULL, ega_out, NULL, NULL, ega);
ega_recalctimings(ega);
if ((ega_type == EGA_TYPE_COMPAQ) && !(val & 0x02))
mem_mapping_disable(&ega->mapping);
else switch (ega->gdcreg[6] & 0xc) {
case 0x0: /*128k at A0000*/
mem_mapping_set_addr(&ega->mapping, 0xa0000, 0x20000);
break;
case 0x4: /*64k at A0000*/
mem_mapping_set_addr(&ega->mapping, 0xa0000, 0x10000);
break;
case 0x8: /*32k at B0000*/
mem_mapping_set_addr(&ega->mapping, 0xb0000, 0x08000);
break;
case 0xC: /*32k at B8000*/
mem_mapping_set_addr(&ega->mapping, 0xb8000, 0x08000);
break;
default:
break;
}
break;
case 0x3c4:
ega->seqaddr = val;
break;
case 0x3c5:
o = ega->seqregs[ega->seqaddr & 0xf];
ega->seqregs[ega->seqaddr & 0xf] = val;
if (o != val && (ega->seqaddr & 0xf) == 1)
ega_recalctimings(ega);
switch (ega->seqaddr & 0xf) {
case 1:
if (ega->scrblank && !(val & 0x20))
ega->fullchange = 3;
ega->scrblank = (ega->scrblank & ~0x20) | (val & 0x20);
break;
case 2:
ega->writemask = val & 0xf;
break;
case 3:
ega->charsetb = (((val >> 2) & 3) * 0x10000) + 2;
ega->charseta = ((val & 3) * 0x10000) + 2;
break;
case 4:
ega->chain2_write = !(val & 4);
break;
default:
break;
}
break;
case 0x3c6:
if (ega_type == EGA_TYPE_COMPAQ)
ega->ctl_mode = val;
break;
case 0x3ce:
ega->gdcaddr = val;
break;
case 0x3cf:
ega->gdcreg[ega->gdcaddr & 15] = val;
switch (ega->gdcaddr & 15) {
case 2:
ega->colourcompare = val;
break;
case 4:
ega->readplane = val & 3;
break;
case 5:
ega->writemode = val & 3;
ega->readmode = val & 8;
ega->chain2_read = val & 0x10;
break;
case 6:
if ((ega_type == EGA_TYPE_COMPAQ) && !(ega->miscout & 0x02))
mem_mapping_disable(&ega->mapping);
else switch (val & 0xc) {
case 0x0: /*128k at A0000*/
mem_mapping_set_addr(&ega->mapping, 0xa0000, 0x20000);
break;
case 0x4: /*64k at A0000*/
mem_mapping_set_addr(&ega->mapping, 0xa0000, 0x10000);
break;
case 0x8: /*32k at B0000*/
mem_mapping_set_addr(&ega->mapping, 0xb0000, 0x08000);
break;
case 0xC: /*32k at B8000*/
mem_mapping_set_addr(&ega->mapping, 0xb8000, 0x08000);
break;
default:
break;
}
break;
case 7:
ega->colournocare = val;
break;
default:
break;
}
break;
case 0x3d0:
case 0x3d4:
if (ega->chipset)
ega->crtcreg = val & 0x3f;
else
ega->crtcreg = val & 0x1f;
return;
case 0x3d1:
case 0x3d5:
if (ega->chipset) {
if ((ega->crtcreg < 7) && (ega->crtc[0x11] & 0x80) && !(ega->regs[0xb4] & 0x80))
return;
if ((ega->crtcreg == 7) && (ega->crtc[0x11] & 0x80) && !(ega->regs[0xb4] & 0x80))
val = (ega->crtc[7] & ~0x10) | (val & 0x10);
} else {
if ((ega->crtcreg < 7) && (ega->crtc[0x11] & 0x80))
return;
if ((ega->crtcreg == 7) && (ega->crtc[0x11] & 0x80))
val = (ega->crtc[7] & ~0x10) | (val & 0x10);
}
old = ega->crtc[ega->crtcreg];
ega->crtc[ega->crtcreg] = val;
if (old != val) {
if (ega->crtcreg < 0xe || ega->crtcreg > 0x10) {
if ((ega->crtcreg == 0xc) || (ega->crtcreg == 0xd)) {
ega->fullchange = 3;
ega->ma_latch = ((ega->crtc[0xc] << 8) | ega->crtc[0xd]) + ((ega->crtc[8] & 0x60) >> 5);
} else {
ega->fullchange = changeframecount;
ega_recalctimings(ega);
}
}
}
break;
default:
break;
}
}
uint8_t
ega_in(uint16_t addr, void *priv)
{
ega_t *ega = (ega_t *) priv;
uint8_t ret = 0xff;
if (((addr & 0xfff0) == 0x3d0 || (addr & 0xfff0) == 0x3b0) && !(ega->miscout & 1))
addr ^= 0x60;
switch (addr) {
case 0x1ce:
ret = ega->index;
break;
case 0x1cf:
switch (ega->index) {
case 0xb7:
ret = ega->regs[ega->index] & ~8;
if (ati_eeprom_read((ati_eeprom_t *) ega->eeprom))
ret |= 8;
break;
default:
ret = ega->regs[ega->index];
break;
}
break;
case 0x3c0:
if (ega_type == EGA_TYPE_OTHER)
ret = ega->attraddr | ega->attr_palette_enable;
break;
case 0x3c1:
if (ega_type == EGA_TYPE_OTHER)
ret = ega->attrregs[ega->attraddr];
break;
case 0x3c2:
ret = (egaswitches & (8 >> egaswitchread)) ? 0x10 : 0x00;
break;
case 0x3c4:
if (ega_type == EGA_TYPE_OTHER)
ret = ega->seqaddr;
break;
case 0x3c5:
if (ega_type == EGA_TYPE_OTHER)
ret = ega->seqregs[ega->seqaddr & 0xf];
break;
case 0x3c6:
if (ega_type == EGA_TYPE_COMPAQ)
ret = ega->ctl_mode;
break;
case 0x3c8:
if (ega_type == EGA_TYPE_OTHER)
ret = 2;
break;
case 0x3cc:
if (ega_type == EGA_TYPE_OTHER)
ret = ega->miscout;
break;
case 0x3ce:
if (ega_type == EGA_TYPE_OTHER)
ret = ega->gdcaddr;
break;
case 0x3cf:
if (ega_type == EGA_TYPE_OTHER)
ret = ega->gdcreg[ega->gdcaddr & 0xf];
break;
case 0x3d0:
case 0x3d4:
if (ega_type == EGA_TYPE_OTHER)
ret = ega->crtcreg;
break;
case 0x3d1:
case 0x3d5:
switch (ega->crtcreg) {
case 0xc:
case 0xd:
case 0xe:
case 0xf:
ret = ega->crtc[ega->crtcreg];
break;
case 0x10:
if (ega_type == EGA_TYPE_OTHER)
ret = ega->crtc[ega->crtcreg];
else
ret = ega->light_pen >> 8;
break;
case 0x11:
if (ega_type == EGA_TYPE_OTHER)
ret = ega->crtc[ega->crtcreg];
else
ret = ega->light_pen & 0xff;
break;
default:
if (ega_type == EGA_TYPE_OTHER)
ret = ega->crtc[ega->crtcreg];
break;
}
break;
case 0x3da:
ega->attrff = 0;
if (ega_type == EGA_TYPE_COMPAQ) {
ret = ega->stat & 0xcf;
switch ((ega->attrregs[0x12] >> 4) & 0x03) {
case 0x00:
/* 00 = Pri. Red (5), Pri. Blue (4) */
ret |= (ega->color_mux & 0x04) ? 0x20 : 0x00;
ret |= (ega->color_mux & 0x01) ? 0x10 : 0x00;
break;
case 0x01:
case 0x03:
/* 01 = Sec. Red (5), Sec. Green (4) */
/* 11 = Sec. Red (5), Sec. Green (4) */
ret |= (ega->color_mux & 0x20) ? 0x20 : 0x00;
ret |= (ega->color_mux & 0x10) ? 0x10 : 0x00;
break;
case 0x02:
/* 10 = Sec. Blue (5), Pri. Green (4) */
ret |= (ega->color_mux & 0x08) ? 0x20 : 0x00;
ret |= (ega->color_mux & 0x02) ? 0x10 : 0x00;
break;
}
} else {
ega->stat ^= 0x30; /* Fools IBM EGA video BIOS self-test. */
ret = ega->stat;
}
break;
case 0x7c6:
ret = 0xfd; /* EGA mode supported. */
break;
case 0xbc6:
/* 0000 = None;
0001 = Compaq Dual-Mode (DM) Monitor;
0010 = RGBI Color Monitor;
0011 = COMPAQ Color Monitor (RrGgBb) or Compatible;
0100 - 1111 = Reserved. */
ret = 0x01;
break;
case 0xfc6:
ret = 0xfd;
break;
default:
break;
}
return ret;
}
void
ega_recalctimings(ega_t *ega)
{
int clksel;
int color;
double _dispontime;
double _dispofftime;
double disptime;
double crtcconst;
ega->vtotal = ega->crtc[6];
ega->dispend = ega->crtc[0x12];
ega->vsyncstart = ega->crtc[0x10];
ega->split = ega->crtc[0x18];
if (ega->crtc[7] & 1)
ega->vtotal |= 0x100;
if (ega->crtc[7] & 32)
ega->vtotal |= 0x200;
ega->vtotal += 2;
if (ega->crtc[7] & 2)
ega->dispend |= 0x100;
if (ega->crtc[7] & 64)
ega->dispend |= 0x200;
ega->dispend++;
if (ega->crtc[7] & 4)
ega->vsyncstart |= 0x100;
if (ega->crtc[7] & 128)
ega->vsyncstart |= 0x200;
ega->vsyncstart++;
if (ega->crtc[7] & 0x10)
ega->split |= 0x100;
if (ega->crtc[9] & 0x40)
ega->split |= 0x200;
ega->split++;
ega->hdisp = ega->crtc[1];
ega->hdisp++;
ega->rowoffset = ega->crtc[0x13];
ega->linedbl = ega->crtc[9] & 0x80;
ega->rowcount = ega->crtc[9] & 0x1f;
if (ega_type == EGA_TYPE_COMPAQ) {
color = (ega->miscout & 1);
clksel = ((ega->miscout & 0xc) >> 2);
if (color) {
if (ega->vidclock)
crtcconst = (cpuclock / 16257000.0 * (double) (1ULL << 32));
else
crtcconst = (cpuclock / (157500000.0 / 11.0) * (double) (1ULL << 32));
} else {
if (ega->vidclock)
crtcconst = (cpuclock / 18981000.0 * (double) (1ULL << 32));
else
crtcconst = (cpuclock / 16872000.0 * (double) (1ULL << 32));
}
if (!(ega->seqregs[1] & 1))
crtcconst *= 9.0;
else
crtcconst *= 8.0;
} else if (ega->eeprom) {
clksel = ((ega->miscout & 0xc) >> 2) | ((ega->regs[0xbe] & 0x10) ? 4 : 0);
switch (clksel) {
case 0:
crtcconst = (cpuclock / 25175000.0 * (double) (1ULL << 32));
break;
case 1:
crtcconst = (cpuclock / 28322000.0 * (double) (1ULL << 32));
break;
case 4:
crtcconst = (cpuclock / 14318181.0 * (double) (1ULL << 32));
break;
case 5:
crtcconst = (cpuclock / 16257000.0 * (double) (1ULL << 32));
break;
case 7:
default:
crtcconst = (cpuclock / 36000000.0 * (double) (1ULL << 32));
break;
}
if (!(ega->seqregs[1] & 1))
crtcconst *= 9.0;
else
crtcconst *= 8.0;
} else {
if (ega->vidclock)
crtcconst = (ega->seqregs[1] & 1) ? MDACONST : (MDACONST * (9.0 / 8.0));
else
crtcconst = (ega->seqregs[1] & 1) ? CGACONST : (CGACONST * (9.0 / 8.0));
}
if (!(ega->seqregs[1] & 1))
ega->dot_clock = crtcconst / 9.0;
else
ega->dot_clock = crtcconst / 8.0;
ega->interlace = 0;
ega->ma_latch = (ega->crtc[0xc] << 8) | ega->crtc[0xd];
ega->render = ega_render_blank;
if (!ega->scrblank && ega->attr_palette_enable) {
if (!(ega->gdcreg[6] & 1)) {
if (ega->seqregs[1] & 8)
ega->hdisp *= (ega->seqregs[1] & 1) ? 16 : 18;
else
ega->hdisp *= (ega->seqregs[1] & 1) ? 8 : 9;
ega->render = ega_render_text;
ega->hdisp_old = ega->hdisp;
} else {
ega->hdisp *= (ega->seqregs[1] & 8) ? 16 : 8;
ega->render = ega_render_graphics;
ega->hdisp_old = ega->hdisp;
}
}
if (ega->chipset) {
if (ega->hdisp > 640) {
ega->dispend <<= 1;
ega->vtotal <<= 1;
ega->split <<= 1;
ega->vsyncstart <<= 1;
}
}
overscan_y = (ega->rowcount + 1) << 1;
if (overscan_y < 16)
overscan_y = 16;
overscan_x = (ega->seqregs[1] & 1) ? 16 : 18;
if (ega->vres)
overscan_y <<= 1;
if (ega->seqregs[1] & 8)
overscan_x <<= 1;
ega->y_add = (overscan_y >> 1);
ega->x_add = (overscan_x >> 1) - ega->scrollcache;
if (ega->vres)
ega->y_add >>= 1;
if (ega->seqregs[1] & 8) {
disptime = (double) ((ega->crtc[0] + 2) << 1);
_dispontime = (double) ((ega->crtc[1] + 1) << 1);
} else {
disptime = (double) (ega->crtc[0] + 2);
_dispontime = (double) (ega->crtc[1] + 1);
}
_dispofftime = disptime - _dispontime;
_dispontime *= crtcconst;
_dispofftime *= crtcconst;
ega->dispontime = (uint64_t) (_dispontime);
ega->dispofftime = (uint64_t) (_dispofftime);
if (ega->dispontime < TIMER_USEC)
ega->dispontime = TIMER_USEC;
if (ega->dispofftime < TIMER_USEC)
ega->dispofftime = TIMER_USEC;
if (ega_type == EGA_TYPE_COMPAQ) {
ega->dot_time = (uint64_t) (ega->dot_clock);
if (ega->dot_time < TIMER_USEC)
ega->dot_time = TIMER_USEC;
timer_disable(&ega->dot_timer);
timer_set_delay_u64(&ega->dot_timer, ega->dot_time);
ega->cca = 0;
active = 1;
ega->dot = 0;
}
ega_recalc_remap_func(ega);
}
/* This is needed for the Compaq EGA so that it can pass the 3DA
palette mux part of the self-test. */
void
ega_dot_poll(void *priv)
{
ega_t *ega = (ega_t *) priv;
static uint8_t chr;
static uint8_t attr;
const bool doublewidth = ((ega->seqregs[1] & 8) != 0);
const bool attrblink = ((ega->attrregs[0x10] & 8) != 0);
const bool attrlinechars = (ega->attrregs[0x10] & 4);
const bool crtcreset = ((ega->crtc[0x17] & 0x80) == 0);
const bool seq9dot = ((ega->seqregs[1] & 1) == 0);
const bool blinked = ega->blink & 0x10;
const int dwshift = doublewidth ? 1 : 0;
const int dotwidth = 1 << dwshift;
const int charwidth = dotwidth * (seq9dot ? 9 : 8);
const int cursoron = (ega->sc == (ega->crtc[10] & 31));
const int cursoraddr = (ega->crtc[0xe] << 8) | ega->crtc[0xf];
uint32_t addr;
int drawcursor;
uint32_t charaddr;
static int fg = 0;
static int bg = 0;
static uint32_t dat = 0x00000000;
static int cclock = 0;
static int disptime;
static int _dispontime;
static int _dispofftime;
if (ega->seqregs[1] & 8) {
disptime = ((ega->crtc[0] + 2) << 1);
_dispontime = ((ega->crtc[1] + 1) << 1);
} else {
disptime = (ega->crtc[0] + 2);
_dispontime = (ega->crtc[1] + 1);
}
_dispofftime = disptime - _dispontime;
timer_advance_u64(&ega->dot_timer, ega->dot_time);
if (ega->render == ega_render_text)
ega->color_mux = (dat & (0x100 >> (ega->dot >> dwshift))) ? fg : bg;
else
ega->color_mux = 0x00;
addr = ega->remap_func(ega, ega->cca) & ega->vrammask;
if (!crtcreset) {
chr = ega->vram[addr];
attr = ega->vram[addr + 1];
} else
chr = attr = 0;
drawcursor = ((ega->cca == cursoraddr) && cursoron && ega->cursoron);
if (attr & 8)
charaddr = ega->charsetb + (chr * 0x80);
else
charaddr = ega->charseta + (chr * 0x80);
dat = ega->vram[charaddr + (ega->sc << 2)];
dat <<= 1;
if ((chr & ~0x1F) == 0xC0 && attrlinechars)
dat |= (dat >> 1) & 1;
if (!active)
dat = 0x200;
if (drawcursor) {
bg = ega->egapal[attr & 0x0f];
fg = ega->egapal[attr >> 4];
} else {
fg = ega->egapal[attr & 0x0f];
bg = ega->egapal[attr >> 4];
if ((attr & 0x80) && attrblink) {
bg = ega->egapal[(attr >> 4) & 7];
if (blinked)
fg = bg;
}
}
ega->dot = (ega->dot + 1) % charwidth;
if (ega->dot == 0) {
ega->cca = (ega->cca + 4) & 0x3ffff;
cclock++;
if (active && (cclock == _dispofftime))
active = 0;
else if (!active && (cclock == _dispontime))
active = 1;
}
}
void
ega_poll(void *priv)
{
ega_t *ega = (ega_t *) priv;
int x, y;
int old_ma;
int wx = 640;
int wy = 350;
uint32_t blink_delay;
if (!ega->linepos) {
timer_advance_u64(&ega->timer, ega->dispofftime);
ega->stat |= 1;
ega->linepos = 1;
if (ega->dispon) {
ega->hdisp_on = 1;
ega->ma &= ega->vrammask;
if (ega->firstline == 2000) {
ega->firstline = ega->displine;
video_wait_for_buffer();
}
old_ma = ega->ma;
ega->displine *= ega->vres + 1;
ega->y_add *= ega->vres + 1;
for (y = 0; y <= ega->vres; y++) {
/* Render scanline */
ega->render(ega);
/* Render overscan */
ega->x_add = (overscan_x >> 1);
ega_render_overscan_left(ega);
ega_render_overscan_right(ega);
ega->x_add = (overscan_x >> 1) - ega->scrollcache;
if (y != ega->vres) {
ega->ma = old_ma;
ega->displine++;
}
}
ega->displine /= ega->vres + 1;
ega->y_add /= ega->vres + 1;
if (ega->lastline < ega->displine)
ega->lastline = ega->displine;
}
ega->displine++;
if (ega->interlace)
ega->displine++;
if ((ega->stat & 8) && ((ega->displine & 15) == (ega->crtc[0x11] & 15)) && ega->vslines)
ega->stat &= ~8;
ega->vslines++;
if (ega->chipset) {
if (ega->hdisp > 640) {
if (ega->displine > 2000)
ega->displine = 0;
} else {
if (ega->displine > 500)
ega->displine = 0;
}
} else {
if (ega->displine > 500)
ega->displine = 0;
}
} else {
timer_advance_u64(&ega->timer, ega->dispontime);
if (ega->dispon)
ega->stat &= ~1;
ega->hdisp_on = 0;
ega->linepos = 0;
if ((ega->sc == (ega->crtc[11] & 31)) || (ega->sc == ega->rowcount))
ega->con = 0;
if (ega->dispon) {
/* TODO: Verify real hardware behaviour for out-of-range fine vertical scroll */
if (ega->linedbl && !ega->linecountff) {
ega->linecountff = 1;
ega->ma = ega->maback;
ega->cca = ega->maback;
}
if (ega->sc == (ega->crtc[9] & 31)) {
ega->linecountff = 0;
ega->sc = 0;
ega->maback += (ega->rowoffset << 3);
if (ega->interlace)
ega->maback += (ega->rowoffset << 3);
ega->maback &= ega->vrammask;
ega->ma = ega->maback;
ega->cca = ega->maback;
} else {
ega->linecountff = 0;
ega->sc++;
ega->sc &= 31;
ega->ma = ega->maback;
ega->cca = ega->maback;
}
}
ega->vc++;
if (ega->chipset) {
if (ega->hdisp > 640)
ega->vc &= 1023;
else
ega->vc &= 511;
} else
ega->vc &= 511;
if (ega->vc == ega->split) {
// TODO: Implement the hardware bug where the first scanline is drawn twice when the split happens
if (ega->interlace && ega->oddeven)
ega->ma = ega->maback = ega->rowoffset << 1;
else
ega->ma = ega->maback = 0;
ega->ma <<= 2;
ega->cca = ega->ma;
ega->maback <<= 2;
ega->sc = 0;
}
if (ega->vc == ega->dispend) {
ega->dispon = 0;
blink_delay = (ega->crtc[11] & 0x60) >> 5;
if (ega->crtc[10] & 0x20)
ega->cursoron = 0;
else if (blink_delay == 2)
ega->cursoron = ((ega->blink % 96) >= 48);
else
ega->cursoron = ega->blink & (16 + (16 * blink_delay));
if (!(ega->gdcreg[6] & 1) && !(ega->blink & 15))
ega->fullchange = 2;
ega->blink = (ega->blink + 1) & 0x7f;
if (ega->fullchange)
ega->fullchange--;
}
if (ega->vc == ega->vsyncstart) {
ega->dispon = 0;
ega->stat |= 8;
#if 0
picint(1 << 2);
#endif
x = ega->hdisp;
if (ega->interlace && !ega->oddeven)
ega->lastline++;
if (ega->interlace && ega->oddeven)
ega->firstline--;
wx = x;
if (ega->vres) {
wy = (ega->lastline - ega->firstline) << 1;
ega_doblit(wx, wy, ega);
} else {
wy = ega->lastline - ega->firstline;
ega_doblit(wx, wy, ega);
}
frames++;
ega->firstline = 2000;
ega->lastline = 0;
ega->firstline_draw = 2000;
ega->lastline_draw = 0;
ega->oddeven ^= 1;
changeframecount = ega->interlace ? 3 : 2;
ega->vslines = 0;
if (ega->interlace && ega->oddeven)
ega->ma = ega->maback = ega->ma_latch + (ega->rowoffset << 1);
else
ega->ma = ega->maback = ega->ma_latch;
ega->ca = (ega->crtc[0xe] << 8) | ega->crtc[0xf];
ega->ma <<= 2;
ega->maback <<= 2;
ega->ca <<= 2;
ega->cca = ega->ma;
}
if (ega->vc == ega->vtotal) {
ega->vc = 0;
ega->sc = (ega->crtc[0x8] & 0x1f);
ega->dispon = 1;
ega->displine = (ega->interlace && ega->oddeven) ? 1 : 0;
ega->scrollcache = (ega->attrregs[0x13] & 0x0f);
if (ega->scrollcache >= 0x8)
ega->scrollcache = 0;
else
ega->scrollcache++;
if (ega->seqregs[1] & 8)
ega->scrollcache <<= 1;
ega->x_add = (overscan_x >> 1) - ega->scrollcache;
ega->linecountff = 0;
}
if (ega->sc == (ega->crtc[10] & 31))
ega->con = 1;
}
}
void
ega_doblit(int wx, int wy, ega_t *ega)
{
int unscaled_overscan_y = ega->vres ? overscan_y >> 1 : overscan_y;
int y_add = enable_overscan ? unscaled_overscan_y : 0;
int x_add = enable_overscan ? overscan_x : 0;
int y_start = enable_overscan ? 0 : (unscaled_overscan_y >> 1);
int x_start = enable_overscan ? 0 : (overscan_x >> 1);
int bottom = (unscaled_overscan_y >> 1);
uint32_t *p;
int i;
int j;
int xs_temp;
int ys_temp;
if (ega->vres) {
y_add <<= 1;
y_start <<= 1;
bottom <<= 1;
}
if ((wx <= 0) || (wy <= 0))
return;
if (ega->vres)
ega->y_add <<= 1;
xs_temp = wx;
ys_temp = wy + 1;
if (ega->vres)
ys_temp++;
if (xs_temp < 64)
xs_temp = 640;
if (ys_temp < 32)
ys_temp = 200;
if ((ega->crtc[0x17] & 0x80) && ((xs_temp != xsize) || (ys_temp != ysize) || video_force_resize_get())) {
/* Screen res has changed.. fix up, and let them know. */
xsize = xs_temp;
ysize = ys_temp;
if ((xsize > 1984) || (ysize > 2016)) {
/* 2048x2048 is the biggest safe render texture, to account for overscan,
we suppress overscan starting from x 1984 and y 2016. */
x_add = 0;
y_add = 0;
suppress_overscan = 1;
} else
suppress_overscan = 0;
set_screen_size(xsize + x_add, ysize + y_add);
if (video_force_resize_get())
video_force_resize_set(0);
}
if ((wx >= 160) && ((wy + 1) >= 120)) {
/* Draw (overscan_size - scroll size) lines of overscan on top and bottom. */
for (i = 0; i < ega->y_add; i++) {
p = &buffer32->line[i & 0x7ff][0];
for (j = 0; j < (xsize + x_add); j++)
p[j] = ega->overscan_color;
}
for (i = 0; i < bottom; i++) {
p = &buffer32->line[(ysize + ega->y_add + i) & 0x7ff][0];
for (j = 0; j < (xsize + x_add); j++)
p[j] = ega->overscan_color;
}
}
video_blit_memtoscreen(x_start, y_start, xsize + x_add, ysize + y_add);
if (ega->vres)
ega->y_add >>= 1;
}
uint32_t
ega_remap_cpu_addr(uint32_t inaddr, ega_t *ega)
{
int a0mux;
uint32_t addr = inaddr;
// The CPU A0 line is multiplexed via a 3-to-8 mux.
// Input bits are:
// bit 0: 1 = 64K, 0 = 128K+ (from memory expansion connector)
// bit 1: 1 = Odd/Even mode, 0 = normal mode (from GC reg 6 bit 1)
// bit 2: 1 = 128K mapping, 0 = other mapping (from memory decode PROM)
a0mux = 0;
if (ega->gdcreg[6] & 2) {
a0mux |= 2;
}
if (ega->vram_limit <= 64 * 1024) {
a0mux |= 1;
}
switch (ega->gdcreg[6] & 0xC) {
case 0x0: // 128K A000
addr &= 0xFFFF;
// TODO: Confirm the behaviour of this on actual hardware
a0mux |= 4;
break;
case 0x4: // 64K A000
addr &= 0xFFFF;
break;
case 0x8: // 32K B000
addr &= 0x7FFF;
break;
case 0xC: // 32K B800
addr &= 0x7FFF;
break;
default:
break;
}
switch (a0mux) {
case 0:
case 1:
case 4:
case 5:
case 7: // A0 becomes A0
break;
case 2:
// A0 becomes the inversion of PGSEL (reg 0x3C2, miscout, bit 5)
// That is, 1 selects the "low" 64k, and 0 selects the "high" 64k.
addr &= ~1;
addr |= (~ega->miscout >> 5) & 1;
break;
case 3: // A0 becomes A14
addr &= ~1;
addr |= (inaddr >> 14) & 1;
break;
case 6: // A0 becomes A16
addr &= ~1;
addr |= (inaddr >> 16) & 1;
break;
default:
break;
}
// In 64k mode, only select the first 16Kword/64KB bank
if (!(ega->seqregs[4] & 2)) {
addr &= 0x3FFF;
}
return addr;
}
void
ega_write(uint32_t addr, uint8_t val, void *priv)
{
ega_t *ega = (ega_t *) priv;
uint8_t vala;
uint8_t valb;
uint8_t valc;
uint8_t vald;
int writemask2 = ega->writemask;
cycles -= video_timing_write_b;
if (ega->chain2_write) {
writemask2 &= ~0xa;
if (addr & 1)
writemask2 <<= 1;
}
addr = ega_remap_cpu_addr(addr, ega);
addr <<= 2;
if (addr >= ega->vram_limit)
return;
if (!(ega->gdcreg[6] & 1))
ega->fullchange = 2;
switch (ega->writemode) {
case 1:
if (writemask2 & 1)
ega->vram[addr] = ega->la;
if (writemask2 & 2)
ega->vram[addr | 0x1] = ega->lb;
if (writemask2 & 4)
ega->vram[addr | 0x2] = ega->lc;
if (writemask2 & 8)
ega->vram[addr | 0x3] = ega->ld;
break;
case 0:
if (ega->gdcreg[3] & 7)
val = ega_rotate[ega->gdcreg[3] & 7][val];
if ((ega->gdcreg[8] == 0xff) && !(ega->gdcreg[3] & 0x18) && !ega->gdcreg[1]) {
if (writemask2 & 1)
ega->vram[addr] = val;
if (writemask2 & 2)
ega->vram[addr | 0x1] = val;
if (writemask2 & 4)
ega->vram[addr | 0x2] = val;
if (writemask2 & 8)
ega->vram[addr | 0x3] = val;
} else {
if (ega->gdcreg[1] & 1)
vala = (ega->gdcreg[0] & 1) ? 0xff : 0;
else
vala = val;
if (ega->gdcreg[1] & 2)
valb = (ega->gdcreg[0] & 2) ? 0xff : 0;
else
valb = val;
if (ega->gdcreg[1] & 4)
valc = (ega->gdcreg[0] & 4) ? 0xff : 0;
else
valc = val;
if (ega->gdcreg[1] & 8)
vald = (ega->gdcreg[0] & 8) ? 0xff : 0;
else
vald = val;
switch (ega->gdcreg[3] & 0x18) {
case 0: /*Set*/
if (writemask2 & 1)
ega->vram[addr] = (vala & ega->gdcreg[8]) | (ega->la & ~ega->gdcreg[8]);
if (writemask2 & 2)
ega->vram[addr | 0x1] = (valb & ega->gdcreg[8]) | (ega->lb & ~ega->gdcreg[8]);
if (writemask2 & 4)
ega->vram[addr | 0x2] = (valc & ega->gdcreg[8]) | (ega->lc & ~ega->gdcreg[8]);
if (writemask2 & 8)
ega->vram[addr | 0x3] = (vald & ega->gdcreg[8]) | (ega->ld & ~ega->gdcreg[8]);
break;
case 8: /*AND*/
if (writemask2 & 1)
ega->vram[addr] = (vala | ~ega->gdcreg[8]) & ega->la;
if (writemask2 & 2)
ega->vram[addr | 0x1] = (valb | ~ega->gdcreg[8]) & ega->lb;
if (writemask2 & 4)
ega->vram[addr | 0x2] = (valc | ~ega->gdcreg[8]) & ega->lc;
if (writemask2 & 8)
ega->vram[addr | 0x3] = (vald | ~ega->gdcreg[8]) & ega->ld;
break;
case 0x10: /*OR*/
if (writemask2 & 1)
ega->vram[addr] = (vala & ega->gdcreg[8]) | ega->la;
if (writemask2 & 2)
ega->vram[addr | 0x1] = (valb & ega->gdcreg[8]) | ega->lb;
if (writemask2 & 4)
ega->vram[addr | 0x2] = (valc & ega->gdcreg[8]) | ega->lc;
if (writemask2 & 8)
ega->vram[addr | 0x3] = (vald & ega->gdcreg[8]) | ega->ld;
break;
case 0x18: /*XOR*/
if (writemask2 & 1)
ega->vram[addr] = (vala & ega->gdcreg[8]) ^ ega->la;
if (writemask2 & 2)
ega->vram[addr | 0x1] = (valb & ega->gdcreg[8]) ^ ega->lb;
if (writemask2 & 4)
ega->vram[addr | 0x2] = (valc & ega->gdcreg[8]) ^ ega->lc;
if (writemask2 & 8)
ega->vram[addr | 0x3] = (vald & ega->gdcreg[8]) ^ ega->ld;
break;
default:
break;
}
}
break;
case 2:
if (!(ega->gdcreg[3] & 0x18) && !ega->gdcreg[1]) {
if (writemask2 & 1)
ega->vram[addr] = (((val & 1) ? 0xff : 0) & ega->gdcreg[8]) | (ega->la & ~ega->gdcreg[8]);
if (writemask2 & 2)
ega->vram[addr | 0x1] = (((val & 2) ? 0xff : 0) & ega->gdcreg[8]) | (ega->lb & ~ega->gdcreg[8]);
if (writemask2 & 4)
ega->vram[addr | 0x2] = (((val & 4) ? 0xff : 0) & ega->gdcreg[8]) | (ega->lc & ~ega->gdcreg[8]);
if (writemask2 & 8)
ega->vram[addr | 0x3] = (((val & 8) ? 0xff : 0) & ega->gdcreg[8]) | (ega->ld & ~ega->gdcreg[8]);
} else {
vala = ((val & 1) ? 0xff : 0);
valb = ((val & 2) ? 0xff : 0);
valc = ((val & 4) ? 0xff : 0);
vald = ((val & 8) ? 0xff : 0);
switch (ega->gdcreg[3] & 0x18) {
case 0: /*Set*/
if (writemask2 & 1)
ega->vram[addr] = (vala & ega->gdcreg[8]) | (ega->la & ~ega->gdcreg[8]);
if (writemask2 & 2)
ega->vram[addr | 0x1] = (valb & ega->gdcreg[8]) | (ega->lb & ~ega->gdcreg[8]);
if (writemask2 & 4)
ega->vram[addr | 0x2] = (valc & ega->gdcreg[8]) | (ega->lc & ~ega->gdcreg[8]);
if (writemask2 & 8)
ega->vram[addr | 0x3] = (vald & ega->gdcreg[8]) | (ega->ld & ~ega->gdcreg[8]);
break;
case 8: /*AND*/
if (writemask2 & 1)
ega->vram[addr] = (vala | ~ega->gdcreg[8]) & ega->la;
if (writemask2 & 2)
ega->vram[addr | 0x1] = (valb | ~ega->gdcreg[8]) & ega->lb;
if (writemask2 & 4)
ega->vram[addr | 0x2] = (valc | ~ega->gdcreg[8]) & ega->lc;
if (writemask2 & 8)
ega->vram[addr | 0x3] = (vald | ~ega->gdcreg[8]) & ega->ld;
break;
case 0x10: /*OR*/
if (writemask2 & 1)
ega->vram[addr] = (vala & ega->gdcreg[8]) | ega->la;
if (writemask2 & 2)
ega->vram[addr | 0x1] = (valb & ega->gdcreg[8]) | ega->lb;
if (writemask2 & 4)
ega->vram[addr | 0x2] = (valc & ega->gdcreg[8]) | ega->lc;
if (writemask2 & 8)
ega->vram[addr | 0x3] = (vald & ega->gdcreg[8]) | ega->ld;
break;
case 0x18: /*XOR*/
if (writemask2 & 1)
ega->vram[addr] = (vala & ega->gdcreg[8]) ^ ega->la;
if (writemask2 & 2)
ega->vram[addr | 0x1] = (valb & ega->gdcreg[8]) ^ ega->lb;
if (writemask2 & 4)
ega->vram[addr | 0x2] = (valc & ega->gdcreg[8]) ^ ega->lc;
if (writemask2 & 8)
ega->vram[addr | 0x3] = (vald & ega->gdcreg[8]) ^ ega->ld;
break;
default:
break;
}
}
break;
default:
break;
}
}
uint8_t
ega_read(uint32_t addr, void *priv)
{
ega_t *ega = (ega_t *) priv;
uint8_t temp;
uint8_t temp2;
uint8_t temp3;
uint8_t temp4;
int readplane = ega->readplane;
cycles -= video_timing_read_b;
if (ega->chain2_read) {
readplane = (readplane & 2) | (addr & 1);
}
addr = ega_remap_cpu_addr(addr, ega);
addr <<= 2;
if (addr >= ega->vram_limit)
return 0xff;
ega->la = ega->vram[addr];
ega->lb = ega->vram[addr | 0x1];
ega->lc = ega->vram[addr | 0x2];
ega->ld = ega->vram[addr | 0x3];
if (ega->readmode) {
temp = ega->la;
temp ^= (ega->colourcompare & 1) ? 0xff : 0;
temp &= (ega->colournocare & 1) ? 0xff : 0;
temp2 = ega->lb;
temp2 ^= (ega->colourcompare & 2) ? 0xff : 0;
temp2 &= (ega->colournocare & 2) ? 0xff : 0;
temp3 = ega->lc;
temp3 ^= (ega->colourcompare & 4) ? 0xff : 0;
temp3 &= (ega->colournocare & 4) ? 0xff : 0;
temp4 = ega->ld;
temp4 ^= (ega->colourcompare & 8) ? 0xff : 0;
temp4 &= (ega->colournocare & 8) ? 0xff : 0;
return ~(temp | temp2 | temp3 | temp4);
}
if ((ega_type == EGA_TYPE_COMPAQ) && (ega->gdcreg[4] & 0x04))
return 0xff;
return ega->vram[addr | readplane];
}
void
ega_init(ega_t *ega, int monitor_type, int is_mono)
{
int c;
int d;
int e;
ega->vram = malloc(0x40000);
ega->vrammask = 0x3ffff;
for (c = 0; c < 256; c++) {
e = c;
for (d = 0; d < 8; d++) {
ega_rotate[d][c] = e;
e = (e >> 1) | ((e & 1) ? 0x80 : 0);
}
}
if (is_mono) {
for (c = 0; c < 256; c++) {
if (((c >> 3) & 3) == 0)
pallook64[c] = pallook16[c] = makecol32(0, 0, 0);
else
switch (monitor_type >> 4) {
case DISPLAY_GREEN:
switch ((c >> 3) & 3) {
case 1:
pallook64[c] = pallook16[c] = makecol32(0x08, 0xc7, 0x2c);
break;
case 2:
pallook64[c] = pallook16[c] = makecol32(0x04, 0x8a, 0x20);
break;
case 3:
pallook64[c] = pallook16[c] = makecol32(0x34, 0xff, 0x5d);
break;
default:
break;
}
break;
case DISPLAY_AMBER:
switch ((c >> 3) & 3) {
case 1:
pallook64[c] = pallook16[c] = makecol32(0xef, 0x79, 0x00);
break;
case 2:
pallook64[c] = pallook16[c] = makecol32(0xb2, 0x4d, 0x00);
break;
case 3:
pallook64[c] = pallook16[c] = makecol32(0xff, 0xe3, 0x34);
break;
default:
break;
}
break;
case DISPLAY_WHITE:
default:
switch ((c >> 3) & 3) {
case 1:
pallook64[c] = pallook16[c] = makecol32(0xaf, 0xb3, 0xb0);
break;
case 2:
pallook64[c] = pallook16[c] = makecol32(0x7a, 0x81, 0x83);
break;
case 3:
pallook64[c] = pallook16[c] = makecol32(0xff, 0xfd, 0xed);
break;
default:
break;
}
break;
}
}
io_sethandler(0x03a0, 0x0020, ega_in, NULL, NULL, ega_out, NULL, NULL, ega);
} else {
for (c = 0; c < 256; c++) {
pallook64[c] = makecol32(((c >> 2) & 1) * 0xaa, ((c >> 1) & 1) * 0xaa, (c & 1) * 0xaa);
pallook64[c] += makecol32(((c >> 5) & 1) * 0x55, ((c >> 4) & 1) * 0x55, ((c >> 3) & 1) * 0x55);
pallook16[c] = makecol32(((c >> 2) & 1) * 0xaa, ((c >> 1) & 1) * 0xaa, (c & 1) * 0xaa);
pallook16[c] += makecol32(((c >> 4) & 1) * 0x55, ((c >> 4) & 1) * 0x55, ((c >> 4) & 1) * 0x55);
if ((c & 0x17) == 6)
pallook16[c] = makecol32(0xaa, 0x55, 0);
}
ega->miscout |= 1;
}
ega->pallook = pallook16;
egaswitches = monitor_type & 0xf;
ega->vram_limit = 256 * 1024;
ega->vrammask = ega->vram_limit - 1;
old_overscan_color = 0;
ega->miscout |= 0x22;
ega->oddeven_page = 0;
ega->seqregs[4] |= 2;
ega->extvram = 1;
update_overscan = 0;
ega->crtc[0] = 63;
ega->crtc[6] = 255;
timer_add(&ega->timer, ega_poll, ega, 1);
if (ega_type == EGA_TYPE_COMPAQ)
timer_add(&ega->dot_timer, ega_dot_poll, ega, 1);
}
static void *
ega_standalone_init(const device_t *info)
{
ega_t *ega = malloc(sizeof(ega_t));
int monitor_type;
memset(ega, 0x00, sizeof(ega_t));
video_inform(VIDEO_FLAG_TYPE_SPECIAL, &timing_ega);
overscan_x = 16;
overscan_y = 28;
ega->x_add = 8;
ega->y_add = 14;
if ((info->local == EGA_IBM) || (info->local == EGA_ISKRA) || (info->local == EGA_TSENG))
ega_type = EGA_TYPE_IBM;
else if (info->local == EGA_COMPAQ)
ega_type = EGA_TYPE_COMPAQ;
else
ega_type = EGA_TYPE_OTHER;
ega->actual_type = info->local;
ega->chipset = 0;
switch (info->local) {
default:
case EGA_IBM:
rom_init(&ega->bios_rom, BIOS_IBM_PATH,
0xc0000, 0x8000, 0x7fff, 0, MEM_MAPPING_EXTERNAL);
break;
case EGA_COMPAQ:
ega->ctl_mode = 0x21;
rom_init(&ega->bios_rom, BIOS_CPQ_PATH,
0xc0000, 0x8000, 0x7fff, 0, MEM_MAPPING_EXTERNAL);
break;
case EGA_SUPEREGA:
rom_init(&ega->bios_rom, BIOS_SEGA_PATH,
0xc0000, 0x8000, 0x7fff, 0, MEM_MAPPING_EXTERNAL);
break;
case EGA_ATI800P:
rom_init(&ega->bios_rom, BIOS_ATIEGA800P_PATH,
0xc0000, 0x8000, 0x7fff, 0, MEM_MAPPING_EXTERNAL);
ega->chipset = 1;
break;
case EGA_ISKRA:
rom_init_interleaved(&ega->bios_rom, BIOS_ISKRA_PATH,
0xc0000, 0x8000, 0x7fff, 0, MEM_MAPPING_EXTERNAL);
break;
case EGA_TSENG:
rom_init(&ega->bios_rom, BIOS_TSENG_PATH,
0xc0000, 0x8000, 0x7fff, 0, MEM_MAPPING_EXTERNAL);
break;
}
if ((ega->bios_rom.rom[0x3ffe] == 0xaa) && (ega->bios_rom.rom[0x3fff] == 0x55)) {
for (uint16_t c = 0; c < 0x2000; c++) {
uint8_t temp = ega->bios_rom.rom[c];
ega->bios_rom.rom[c] = ega->bios_rom.rom[0x3fff - c];
ega->bios_rom.rom[0x3fff - c] = temp;
}
}
monitor_type = device_get_config_int("monitor_type");
ega_init(ega, monitor_type, (monitor_type & 0x0F) == 0x0B);
ega->vram_limit = device_get_config_int("memory") * 1024;
ega->vrammask = ega->vram_limit - 1;
mem_mapping_add(&ega->mapping, 0xa0000, 0x20000, ega_read, NULL, NULL, ega_write, NULL, NULL, NULL, MEM_MAPPING_EXTERNAL, ega);
if (ega_type == EGA_TYPE_COMPAQ)
mem_mapping_disable(&ega->mapping);
io_sethandler(0x03c0, 0x0020, ega_in, NULL, NULL, ega_out, NULL, NULL, ega);
if (ega->chipset) {
io_sethandler(0x01ce, 0x0002, ega_in, NULL, NULL, ega_out, NULL, NULL, ega);
ega->eeprom = malloc(sizeof(ati_eeprom_t));
memset(ega->eeprom, 0, sizeof(ati_eeprom_t));
ati_eeprom_load((ati_eeprom_t *) ega->eeprom, "egawonder800p.nvr", 0);
} else if (info->local == EGA_COMPAQ) {
io_sethandler(0x0084, 0x0001, ega_in, NULL, NULL, ega_out, NULL, NULL, ega);
io_sethandler(0x07c6, 0x0001, ega_in, NULL, NULL, ega_out, NULL, NULL, ega);
io_sethandler(0x0bc6, 0x0001, ega_in, NULL, NULL, ega_out, NULL, NULL, ega);
io_sethandler(0x0fc6, 0x0001, ega_in, NULL, NULL, ega_out, NULL, NULL, ega);
}
return ega;
}
static int
ega_standalone_available(void)
{
return rom_present(BIOS_IBM_PATH);
}
static int
cpqega_standalone_available(void)
{
return rom_present(BIOS_CPQ_PATH);
}
static int
sega_standalone_available(void)
{
return rom_present(BIOS_SEGA_PATH);
}
static int
atiega800p_standalone_available(void)
{
return rom_present(BIOS_ATIEGA800P_PATH);
}
static int
iskra_ega_standalone_available(void)
{
return rom_present("roms/video/ega/143-02.bin") && rom_present("roms/video/ega/143-03.bin");
}
static int
et2000_standalone_available(void)
{
return rom_present(BIOS_TSENG_PATH);
}
static void
ega_close(void *priv)
{
ega_t *ega = (ega_t *) priv;
if (ega->eeprom)
free(ega->eeprom);
free(ega->vram);
free(ega);
}
static void
ega_speed_changed(void *priv)
{
ega_t *ega = (ega_t *) priv;
ega_recalctimings(ega);
}
/* SW1 SW2 SW3 SW4
OFF OFF ON OFF Monochrome (5151) 1011 0x0B
ON OFF OFF ON Color 40x25 (5153) 0110 0x06
OFF OFF OFF ON Color 80x25 (5153) 0111 0x07
ON ON ON OFF Enhanced Color - Normal Mode (5154) 1000 0x08
OFF ON ON OFF Enhanced Color - Enhanced Mode (5154) 1001 0x09
0 = Switch closed (ON);
1 = Switch open (OFF). */
static const device_config_t ega_config[] = {
// clang-format off
{
.name = "memory",
.description = "Memory size",
.type = CONFIG_SELECTION,
.default_int = 256,
.selection = {
{
.description = "32 kB",
.value = 32
},
{
.description = "64 kB",
.value = 64
},
{
.description = "128 kB",
.value = 128
},
{
.description = "256 kB",
.value = 256
},
{
.description = ""
}
}
},
{
.name = "monitor_type",
.description = "Monitor type",
.type = CONFIG_SELECTION,
.selection = {
{
.description = "Monochrome (5151/MDA) (white)",
.value = 0x0B | (DISPLAY_WHITE << 4)
},
{
.description = "Monochrome (5151/MDA) (green)",
.value = 0x0B | (DISPLAY_GREEN << 4)
},
{
.description = "Monochrome (5151/MDA) (amber)",
.value = 0x0B | (DISPLAY_AMBER << 4)
},
{
.description = "Color 40x25 (5153/CGA)",
.value = 0x06
},
{
.description = "Color 80x25 (5153/CGA)",
.value = 0x07
},
{
.description = "Enhanced Color - Normal Mode (5154/ECD)",
.value = 0x08
},
{
.description = "Enhanced Color - Enhanced Mode (5154/ECD)",
.value = 0x09
},
{
.description = ""
}
},
.default_int = 9
},
{
.type = CONFIG_END
}
// clang-format on
};
const device_t ega_device = {
.name = "IBM EGA",
.internal_name = "ega",
.flags = DEVICE_ISA,
.local = EGA_IBM,
.init = ega_standalone_init,
.close = ega_close,
.reset = NULL,
{ .available = ega_standalone_available },
.speed_changed = ega_speed_changed,
.force_redraw = NULL,
.config = ega_config
};
const device_t cpqega_device = {
.name = "Compaq EGA",
.internal_name = "compaq_ega",
.flags = DEVICE_ISA,
.local = EGA_COMPAQ,
.init = ega_standalone_init,
.close = ega_close,
.reset = NULL,
{ .available = cpqega_standalone_available },
.speed_changed = ega_speed_changed,
.force_redraw = NULL,
.config = ega_config
};
const device_t sega_device = {
.name = "SuperEGA",
.internal_name = "superega",
.flags = DEVICE_ISA,
.local = EGA_SUPEREGA,
.init = ega_standalone_init,
.close = ega_close,
.reset = NULL,
{ .available = sega_standalone_available },
.speed_changed = ega_speed_changed,
.force_redraw = NULL,
.config = ega_config
};
const device_t atiega800p_device = {
.name = "ATI EGA Wonder 800+",
.internal_name = "egawonder800p",
.flags = DEVICE_ISA,
.local = EGA_ATI800P,
.init = ega_standalone_init,
.close = ega_close,
.reset = NULL,
{ .available = atiega800p_standalone_available },
.speed_changed = ega_speed_changed,
.force_redraw = NULL,
.config = ega_config
};
const device_t iskra_ega_device = {
.name = "Iskra EGA (Cyrillic ROM)",
.internal_name = "iskra_ega",
.flags = DEVICE_ISA,
.local = EGA_ISKRA,
.init = ega_standalone_init,
.close = ega_close,
.reset = NULL,
{ .available = iskra_ega_standalone_available },
.speed_changed = ega_speed_changed,
.force_redraw = NULL,
.config = ega_config
};
const device_t et2000_device = {
.name = "Tseng Labs ET2000",
.internal_name = "et2000",
.flags = DEVICE_ISA,
.local = EGA_TSENG,
.init = ega_standalone_init,
.close = ega_close,
.reset = NULL,
{ .available = et2000_standalone_available },
.speed_changed = ega_speed_changed,
.force_redraw = NULL,
.config = ega_config
};
``` | /content/code_sandbox/src/video/vid_ega.c | c | 2016-06-25T22:29:10 | 2024-08-16T19:09:21 | 86Box | 86Box/86Box | 2,616 | 17,935 |
```c
/*
* 86Box A hypervisor and IBM PC system emulator that specializes in
* running old operating systems and software designed for IBM
* PC systems and compatibles from 1981 through fairly recent
* system designs based on the PCI bus.
*
* This file is part of the 86Box distribution.
*
* Emulation of the IBM RGB 528 true colour RAMDAC.
*
*
*
* Authors: Miran Grca, <mgrca8@gmail.com>
*
*/
#include <stdio.h>
#include <stdint.h>
#include <stdlib.h>
#include <string.h>
#include <wchar.h>
#include <86box/86box.h>
#include <86box/device.h>
#include <86box/mem.h>
#include <86box/timer.h>
#include <86box/video.h>
#include <86box/vid_svga.h>
#include <86box/plat_unused.h>
typedef union ibm_rgb528_pixel8_t {
uint8_t pixel;
struct {
uint8_t b : 2;
uint8_t g : 3;
uint8_t r : 2;
};
} ibm_rgb528_pixel8_t;
typedef union ibm_rgb528_pixel16_t {
uint16_t pixel;
struct {
uint16_t b_ : 5;
uint16_t g_ : 6;
uint16_t r_ : 5;
};
struct {
uint16_t b : 5;
uint16_t g : 5;
uint16_t r : 5;
uint16_t c : 1;
};
} ibm_rgb528_pixel16_t;
typedef union ibm_rgb528_pixel32_t {
uint32_t pixel;
struct {
uint8_t b;
uint8_t g;
uint8_t r;
uint8_t a;
};
} ibm_rgb528_pixel32_t;
typedef struct ibm_rgb528_ramdac_t {
PALETTE extpal;
uint32_t extpallook[256];
uint8_t indexed_data[2048];
uint8_t cursor32_data[256];
uint8_t cursor64_data[1024];
uint8_t palettes[3][256];
ibm_rgb528_pixel32_t extra_pal[4];
int16_t hwc_y;
int16_t hwc_x;
uint16_t index;
uint16_t smlc_part;
uint8_t cmd_r0;
uint8_t cmd_r1;
uint8_t cmd_r2;
uint8_t cmd_r3;
uint8_t cmd_r4;
uint8_t status;
uint8_t indx_cntl;
uint8_t cursor_array;
uint8_t cursor_hotspot_x;
uint8_t cursor_hotspot_y;
} ibm_rgb528_ramdac_t;
void
ibm_rgb528_render_4bpp(svga_t *svga)
{
uint32_t *p;
ibm_rgb528_pixel32_t dat_out;
uint8_t dat;
uint32_t dat32 = 0x00000000;
uint64_t dat64 = 0x0000000000000000ULL;
uint64_t dat642 = 0x0000000000000000ULL;
const ibm_rgb528_ramdac_t *ramdac = (ibm_rgb528_ramdac_t *) svga->ramdac;
uint8_t b8_dcol = (ramdac->indexed_data[0x0c] & 0xc0) >> 6;
uint8_t partition = (ramdac->indexed_data[0x07] & 0x0f) << 4;
uint8_t swap_word = ramdac->indexed_data[0x72] & 0x10;
uint8_t swap_nib = ramdac->indexed_data[0x72] & 0x21;
uint8_t vram_size = ramdac->indexed_data[0x70] & 0x03;
if ((svga->displine + svga->y_add) < 0)
return;
if (svga->changedvram[svga->ma >> 12] || svga->changedvram[(svga->ma >> 12) + 1] || svga->changedvram[(svga->ma >> 12) + 2] || svga->fullchange) {
p = &buffer32->line[svga->displine + svga->y_add][svga->x_add];
if (svga->firstline_draw == 2000)
svga->firstline_draw = svga->displine;
svga->lastline_draw = svga->displine;
for (int x = 0; x <= (svga->hdisp + svga->scrollcache); x++) {
if (vram_size == 3) {
if (!(x & 31)) {
dat64 = *(uint64_t *) (&svga->vram[svga->ma]);
dat642 = *(uint64_t *) (&svga->vram[svga->ma + 8]);
if (swap_word) {
dat64 = (dat64 << 32ULL) | (dat64 >> 32ULL);
dat642 = (dat642 << 32ULL) | (dat642 >> 32ULL);
}
}
if (swap_nib)
dat = (((x & 16) ? dat642 : dat64) >> ((x & 15) << 2)) & 0xf;
else
dat = (((x & 16) ? dat642 : dat64) >> (((x & 15) << 2) ^ 4)) & 0xf;
} else if (vram_size == 1) {
if (!(x & 15)) {
dat64 = *(uint64_t *) (&svga->vram[svga->ma]);
if (swap_word)
dat64 = (dat64 << 32ULL) | (dat64 >> 32ULL);
}
if (swap_nib)
dat = (dat64 >> ((x & 15) << 2)) & 0xf;
else
dat = (dat64 >> (((x & 15) << 2) ^ 4)) & 0xf;
} else {
if (!(x & 7))
dat32 = *(uint32_t *) (&svga->vram[svga->ma]);
if (swap_nib)
dat = (dat32 >> ((x & 7) << 2)) & 0xf;
else
dat = (dat32 >> (((x & 7) << 2) ^ 4)) & 0xf;
}
if (b8_dcol == 0x00) {
dat_out.a = 0x00;
dat_out.r = ramdac->palettes[0][partition | dat];
dat_out.g = ramdac->palettes[1][partition | dat];
dat_out.b = ramdac->palettes[2][partition | dat];
} else
dat_out.pixel = video_8togs[dat];
if (svga->lowres) {
p[x << 1] = p[(x << 1) + 1] = dat_out.pixel & 0xffffff;
} else
p[x] = dat_out.pixel & 0xffffff;
if ((vram_size == 3) && ((x & 31) == 31))
svga->ma = (svga->ma + 16) & svga->vram_display_mask;
if ((vram_size == 1) && ((x & 15) == 15))
svga->ma = (svga->ma + 8) & svga->vram_display_mask;
else if ((!vram_size) && ((x & 7) == 7))
svga->ma = (svga->ma + 4) & svga->vram_display_mask;
}
}
}
void
ibm_rgb528_render_8bpp(svga_t *svga)
{
uint32_t *p;
ibm_rgb528_pixel32_t dat_out;
uint8_t dat;
uint32_t dat32 = 0x00000000;
uint64_t dat64 = 0x0000000000000000ULL;
uint64_t dat642 = 0x0000000000000000ULL;
const ibm_rgb528_ramdac_t *ramdac = (ibm_rgb528_ramdac_t *) svga->ramdac;
uint8_t b8_dcol = (ramdac->indexed_data[0x0c] & 0xc0) >> 6;
uint8_t swap_word = ramdac->indexed_data[0x72] & 0x10;
uint8_t vram_size = ramdac->indexed_data[0x70] & 0x03;
if ((svga->displine + svga->y_add) < 0)
return;
if (svga->changedvram[svga->ma >> 12] || svga->changedvram[(svga->ma >> 12) + 1] || svga->changedvram[(svga->ma >> 12) + 2] || svga->fullchange) {
p = &buffer32->line[svga->displine + svga->y_add][svga->x_add];
if (svga->firstline_draw == 2000)
svga->firstline_draw = svga->displine;
svga->lastline_draw = svga->displine;
for (int x = 0; x <= (svga->hdisp + svga->scrollcache); x++) {
if (vram_size == 3) {
if (!(x & 15)) {
dat64 = *(uint64_t *) (&svga->vram[svga->ma]);
dat642 = *(uint64_t *) (&svga->vram[svga->ma + 8]);
if (swap_word) {
dat64 = (dat64 << 32ULL) | (dat64 >> 32ULL);
dat642 = (dat642 << 32ULL) | (dat642 >> 32ULL);
}
}
dat = (((x & 8) ? dat642 : dat64) >> ((x & 7) << 3)) & 0xff;
} else if (vram_size == 1) {
if (!(x & 7)) {
dat64 = *(uint64_t *) (&svga->vram[svga->ma]);
if (swap_word)
dat64 = (dat64 << 32ULL) | (dat64 >> 32ULL);
}
dat = (dat64 >> ((x & 7) << 3)) & 0xff;
} else {
if (!(x & 3))
dat32 = *(uint32_t *) (&svga->vram[svga->ma]);
dat = (dat32 >> ((x & 3) << 3)) & 0xff;
}
if (b8_dcol == 0x00) {
dat_out.a = 0x00;
dat_out.r = ramdac->palettes[0][dat];
dat_out.g = ramdac->palettes[1][dat];
dat_out.b = ramdac->palettes[2][dat];
} else
dat_out.pixel = video_8togs[dat];
if (svga->lowres) {
p[x << 1] = p[(x << 1) + 1] = dat_out.pixel & 0xffffff;
} else
p[x] = dat_out.pixel & 0xffffff;
if ((vram_size == 3) && ((x & 15) == 15))
svga->ma = (svga->ma + 16) & svga->vram_display_mask;
else if ((vram_size == 1) && ((x & 7) == 7))
svga->ma = (svga->ma + 8) & svga->vram_display_mask;
else if ((!vram_size) && ((x & 3) == 3))
svga->ma = (svga->ma + 4) & svga->vram_display_mask;
}
}
}
void
ibm_rgb528_render_15_16bpp(svga_t *svga)
{
uint32_t *p;
ibm_rgb528_pixel16_t *dat_ex;
ibm_rgb528_pixel32_t dat_out;
uint16_t dat;
uint32_t dat32 = 0x00000000;
uint64_t dat64 = 0x0000000000000000ULL;
uint64_t dat642 = 0x0000000000000000ULL;
const ibm_rgb528_ramdac_t *ramdac = (ibm_rgb528_ramdac_t *) svga->ramdac;
uint8_t b16_dcol = (ramdac->indexed_data[0x0c] & 0xc0) >> 6;
uint8_t by16_pol = ramdac->indexed_data[0x0c] & 0x20;
uint8_t b555_565 = ramdac->indexed_data[0x0c] & 0x02;
uint8_t bspr_cnt = ramdac->indexed_data[0x0c] & 0x01;
uint8_t partition = (ramdac->indexed_data[0x07] & 0x0e) << 4;
uint8_t b6bit_lin = ramdac->indexed_data[0x07] & 0x80;
uint8_t swaprb = ramdac->indexed_data[0x72] & 0x80;
uint8_t swap_word = ramdac->indexed_data[0x72] & 0x10;
uint8_t vram_size = ramdac->indexed_data[0x70] & 0x01;
uint8_t temp;
if ((svga->displine + svga->y_add) < 0)
return;
if (b555_565 && (b16_dcol != 0x01))
partition &= 0xc0;
if (svga->changedvram[svga->ma >> 12] || svga->changedvram[(svga->ma >> 12) + 1] || svga->changedvram[(svga->ma >> 12) + 2] || svga->fullchange) {
p = &buffer32->line[svga->displine + svga->y_add][svga->x_add];
if (svga->firstline_draw == 2000)
svga->firstline_draw = svga->displine;
svga->lastline_draw = svga->displine;
for (int x = 0; x <= (svga->hdisp + svga->scrollcache); x++) {
if (vram_size == 2) {
if (!(x & 7)) {
dat64 = *(uint64_t *) (&svga->vram[svga->ma]);
dat642 = *(uint64_t *) (&svga->vram[svga->ma + 8]);
if (swap_word) {
dat64 = (dat64 << 32ULL) | (dat64 >> 32ULL);
dat642 = (dat64 << 32ULL) | (dat642 >> 32ULL);
}
}
dat = (((x & 4) ? dat642 : dat64) >> ((x & 3) << 4)) & 0xffff;
} else if (vram_size == 1) {
if (!(x & 3)) {
dat64 = *(uint64_t *) (&svga->vram[svga->ma]);
if (swap_word)
dat64 = (dat64 << 32ULL) | (dat64 >> 32ULL);
}
dat = (dat64 >> ((x & 3) << 4)) & 0xffff;
} else {
if (!(x & 1))
dat32 = *(uint32_t *) (&svga->vram[svga->ma]);
dat = (dat32 >> ((x & 1) << 4)) & 0xffff;
}
dat_ex = (ibm_rgb528_pixel16_t *) &dat;
if (b555_565 && (b16_dcol != 0x01)) {
if (swaprb) {
temp = dat_ex->r_;
dat_ex->r_ = dat_ex->b_;
dat_ex->b_ = temp;
}
if (b16_dcol == 0x00) {
dat_out.a = 0x00;
if (bspr_cnt) {
dat_out.r = ramdac->palettes[0][partition | dat_ex->r_];
dat_out.g = ramdac->palettes[1][partition | dat_ex->g_];
dat_out.b = ramdac->palettes[2][partition | dat_ex->b_];
} else {
dat_out.r = ramdac->palettes[0][dat_ex->r_ << 3];
dat_out.g = ramdac->palettes[1][dat_ex->g_ << 2];
dat_out.b = ramdac->palettes[2][dat_ex->b_ << 3];
}
if ((svga->ramdac_type != RAMDAC_8BIT) && !b6bit_lin) {
dat_out.r |= ((dat_out.r & 0xc0) >> 6);
dat_out.g |= ((dat_out.g & 0xc0) >> 6);
dat_out.b |= ((dat_out.b & 0xc0) >> 6);
}
} else
dat_out.pixel = video_16to32[dat_ex->pixel];
} else {
if (swaprb) {
temp = dat_ex->r;
dat_ex->r = dat_ex->b;
dat_ex->b = temp;
}
if (by16_pol)
dat ^= 0x8000;
if ((b16_dcol == 0x00) || ((b16_dcol == 0x01) && !(dat & 0x8000))) {
dat_out.a = 0x00;
if (bspr_cnt) {
dat_out.r = ramdac->palettes[0][partition | dat_ex->r];
dat_out.g = ramdac->palettes[1][partition | dat_ex->g];
dat_out.b = ramdac->palettes[2][partition | dat_ex->b];
} else {
dat_out.r = ramdac->palettes[0][dat_ex->r << 3];
dat_out.g = ramdac->palettes[1][dat_ex->g << 3];
dat_out.b = ramdac->palettes[2][dat_ex->b << 3];
}
if ((svga->ramdac_type != RAMDAC_8BIT) && !b6bit_lin) {
dat_out.r |= ((dat_out.r & 0xc0) >> 6);
dat_out.g |= ((dat_out.g & 0xc0) >> 6);
dat_out.b |= ((dat_out.b & 0xc0) >> 6);
}
} else
dat_out.pixel = video_15to32[dat_ex->pixel & 0x7fff];
}
if (svga->lowres) {
p[x << 1] = p[(x << 1) + 1] = dat_out.pixel & 0xffffff;
} else
p[x] = dat_out.pixel & 0xffffff;
if ((vram_size == 3) && ((x & 7) == 7))
svga->ma = (svga->ma + 16) & svga->vram_display_mask;
else if ((vram_size == 1) && ((x & 3) == 3))
svga->ma = (svga->ma + 8) & svga->vram_display_mask;
else if (!vram_size && ((x & 1) == 1))
svga->ma = (svga->ma + 4) & svga->vram_display_mask;
}
}
}
void
ibm_rgb528_render_24bpp(svga_t *svga)
{
uint32_t *p;
ibm_rgb528_pixel32_t *dat_ex;
uint32_t dat;
uint64_t dat64[6];
uint8_t *dat8 = (uint8_t *) dat64;
const ibm_rgb528_ramdac_t *ramdac = (ibm_rgb528_ramdac_t *) svga->ramdac;
uint8_t b24_dcol = ramdac->indexed_data[0x0d] & 0x01;
uint8_t swaprb = ramdac->indexed_data[0x72] & 0x80;
uint8_t swap_word = ramdac->indexed_data[0x72] & 0x10;
uint8_t vram_size = ramdac->indexed_data[0x70] & 0x01;
uint8_t b6bit_lin = ramdac->indexed_data[0x07] & 0x80;
uint8_t temp;
if ((svga->displine + svga->y_add) < 0)
return;
if (svga->changedvram[svga->ma >> 12] || svga->changedvram[(svga->ma >> 12) + 1] || svga->changedvram[(svga->ma >> 12) + 2] || svga->fullchange) {
p = &buffer32->line[svga->displine + svga->y_add][svga->x_add];
if (svga->firstline_draw == 2000)
svga->firstline_draw = svga->displine;
svga->lastline_draw = svga->displine;
for (int x = 0; x <= (svga->hdisp + svga->scrollcache); x++) {
dat_ex = (ibm_rgb528_pixel32_t *) &dat;
if (vram_size == 3) {
if ((x & 15) == 0) {
dat64[0] = *(uint64_t *) (&svga->vram[svga->ma & svga->vram_display_mask]);
dat64[1] = *(uint64_t *) (&svga->vram[(svga->ma + 8) & svga->vram_display_mask]);
dat64[2] = *(uint64_t *) (&svga->vram[(svga->ma + 16) & svga->vram_display_mask]);
dat64[3] = *(uint64_t *) (&svga->vram[(svga->ma + 24) & svga->vram_display_mask]);
dat64[4] = *(uint64_t *) (&svga->vram[(svga->ma + 32) & svga->vram_display_mask]);
dat64[5] = *(uint64_t *) (&svga->vram[(svga->ma + 40) & svga->vram_display_mask]);
if (swap_word) {
dat64[0] = (dat64[0] << 32ULL) | (dat64[0] >> 32ULL);
dat64[1] = (dat64[1] << 32ULL) | (dat64[1] >> 32ULL);
dat64[2] = (dat64[2] << 32ULL) | (dat64[2] >> 32ULL);
dat64[3] = (dat64[3] << 32ULL) | (dat64[3] >> 32ULL);
dat64[4] = (dat64[4] << 32ULL) | (dat64[4] >> 32ULL);
dat64[5] = (dat64[5] << 32ULL) | (dat64[5] >> 32ULL);
}
}
dat_ex = (ibm_rgb528_pixel32_t *) &(dat8[(x & 15) * 3]);
} else if (vram_size == 1) {
if ((x & 7) == 0) {
dat64[0] = *(uint64_t *) (&svga->vram[svga->ma & svga->vram_display_mask]);
dat64[1] = *(uint64_t *) (&svga->vram[(svga->ma + 8) & svga->vram_display_mask]);
dat64[2] = *(uint64_t *) (&svga->vram[(svga->ma + 16) & svga->vram_display_mask]);
if (swap_word) {
dat64[0] = (dat64[0] << 32ULL) | (dat64[0] >> 32ULL);
dat64[1] = (dat64[1] << 32ULL) | (dat64[1] >> 32ULL);
dat64[2] = (dat64[2] << 32ULL) | (dat64[2] >> 32ULL);
}
}
dat_ex = (ibm_rgb528_pixel32_t *) &(dat8[(x & 7) * 3]);
} else
dat = 0x00000000;
if (swaprb) {
temp = dat_ex->r;
dat_ex->r = dat_ex->b;
dat_ex->b = temp;
}
if (b24_dcol == 0x00) {
dat_ex->a = 0x00;
dat_ex->r = ramdac->palettes[0][dat_ex->r];
dat_ex->g = ramdac->palettes[1][dat_ex->g];
dat_ex->g = ramdac->palettes[2][dat_ex->b];
if ((svga->ramdac_type != RAMDAC_8BIT) && !b6bit_lin) {
dat_ex->r |= ((dat_ex->r & 0xc0) >> 6);
dat_ex->g |= ((dat_ex->g & 0xc0) >> 6);
dat_ex->b |= ((dat_ex->b & 0xc0) >> 6);
}
}
if (svga->lowres) {
p[x << 1] = p[(x << 1) + 1] = dat_ex->pixel & 0xffffff;
} else
p[x] = dat_ex->pixel & 0xffffff;
if ((vram_size == 3) && ((x & 15) == 15))
svga->ma = (svga->ma + 48) & svga->vram_display_mask;
else if ((vram_size == 1) && ((x & 7) == 7))
svga->ma = (svga->ma + 24) & svga->vram_display_mask;
}
}
}
void
ibm_rgb528_render_32bpp(svga_t *svga)
{
uint32_t *p;
ibm_rgb528_pixel32_t *dat_ex;
uint32_t dat = 0x00000000;
uint64_t dat64 = 0x0000000000000000ULL;
uint64_t dat642 = 0x0000000000000000ULL;
const ibm_rgb528_ramdac_t *ramdac = (ibm_rgb528_ramdac_t *) svga->ramdac;
uint8_t b32_dcol = ramdac->indexed_data[0x0e] & 0x03;
uint8_t by32_pol = ramdac->indexed_data[0x0e] & 0x04;
uint8_t swaprb = ramdac->indexed_data[0x72] & 0x80;
uint8_t swap_word = ramdac->indexed_data[0x72] & 0x10;
uint8_t vram_size = ramdac->indexed_data[0x70] & 0x01;
uint8_t b6bit_lin = ramdac->indexed_data[0x07] & 0x80;
uint8_t temp;
if ((svga->displine + svga->y_add) < 0)
return;
if (svga->changedvram[svga->ma >> 12] || svga->changedvram[(svga->ma >> 12) + 1] || svga->changedvram[(svga->ma >> 12) + 2] || svga->fullchange) {
p = &buffer32->line[svga->displine + svga->y_add][svga->x_add];
if (svga->firstline_draw == 2000)
svga->firstline_draw = svga->displine;
svga->lastline_draw = svga->displine;
for (int x = 0; x <= (svga->hdisp + svga->scrollcache); x++) {
if (vram_size == 3) {
if (!(x & 3)) {
dat64 = *(uint64_t *) (&svga->vram[svga->ma]);
dat642 = *(uint64_t *) (&svga->vram[svga->ma + 8]);
if (swap_word) {
dat64 = (dat64 << 32ULL) | (dat64 >> 32ULL);
dat642 = (dat642 << 32ULL) | (dat642 >> 32ULL);
}
}
dat = (((x & 2) ? dat642 : dat64) >> ((x & 1ULL) << 5ULL)) & 0xffffffff;
} else if (vram_size == 1) {
if (!(x & 1)) {
dat64 = *(uint64_t *) (&svga->vram[svga->ma]);
if (swap_word)
dat64 = (dat64 << 32ULL) | (dat64 >> 32ULL);
}
dat = (dat64 >> ((x & 1ULL) << 5ULL)) & 0xffffffff;
} else
dat = *(uint32_t *) (&svga->vram[svga->ma]);
dat_ex = (ibm_rgb528_pixel32_t *) &dat;
if (swaprb) {
temp = dat_ex->r;
dat_ex->r = dat_ex->b;
dat_ex->b = temp;
}
if ((b32_dcol < 0x03) && by32_pol)
dat ^= 0x01000000;
if ((b32_dcol == 0x00) || ((b32_dcol == 0x01) && !(dat & 0x01000000))) {
dat_ex->a = 0x00;
dat_ex->r = ramdac->palettes[0][dat_ex->r];
dat_ex->g = ramdac->palettes[1][dat_ex->g];
dat_ex->g = ramdac->palettes[2][dat_ex->b];
if ((svga->ramdac_type != RAMDAC_8BIT) && !b6bit_lin) {
dat_ex->r |= ((dat_ex->r & 0xc0) >> 6);
dat_ex->g |= ((dat_ex->g & 0xc0) >> 6);
dat_ex->b |= ((dat_ex->b & 0xc0) >> 6);
}
}
if (svga->lowres) {
p[x << 1] = p[(x << 1) + 1] = dat_ex->pixel & 0xffffff;
} else
p[x] = dat_ex->pixel & 0xffffff;
if ((vram_size == 3) && ((x & 3) == 3))
svga->ma = (svga->ma + 16) & svga->vram_display_mask;
else if ((vram_size == 1) && ((x & 1) == 1))
svga->ma = (svga->ma + 8) & svga->vram_display_mask;
else if (!vram_size)
svga->ma = (svga->ma + 4) & svga->vram_display_mask;
}
}
}
static void
ibm_rgb528_set_bpp(ibm_rgb528_ramdac_t *ramdac, svga_t *svga)
{
uint8_t b16_dcol = (ramdac->indexed_data[0x0c] & 0xc0) >> 6;
uint8_t b555_565 = ramdac->indexed_data[0x0c] & 0x02;
if (ramdac->indexed_data[0x071] & 0x01)
switch (ramdac->indexed_data[0x00a] & 0x07) {
case 0x02:
svga->bpp = 4;
break;
case 0x03:
default:
svga->bpp = 8;
break;
case 0x04:
if (b555_565 && (b16_dcol != 0x01))
svga->bpp = 16;
else
svga->bpp = 15;
break;
case 0x05:
svga->bpp = 24;
break;
case 0x06:
svga->bpp = 32;
break;
}
else
svga->bpp = 8;
svga_recalctimings(svga);
}
void
ibm_rgb528_ramdac_out(uint16_t addr, int rs2, uint8_t val, void *priv, svga_t *svga)
{
ibm_rgb528_ramdac_t *ramdac = (ibm_rgb528_ramdac_t *) priv;
uint16_t index;
uint8_t rs = (addr & 0x03);
uint16_t da_mask = 0x03ff;
uint8_t updt_cntl = (ramdac->indexed_data[0x30] & 0x08);
rs |= (!!rs2 << 2);
switch (rs) {
case 0x00: /* Palette Write Index Register (RS value = 0000) */
case 0x03:
svga->dac_pos = 0;
svga->dac_status = addr & 0x03;
svga->dac_addr = val;
if (svga->dac_status)
svga->dac_addr = (svga->dac_addr + 1) & da_mask;
break;
case 0x01: /* Palette Data Register (RS value = 0001) */
index = svga->dac_addr & 255;
if (svga->ramdac_type == RAMDAC_8BIT)
ramdac->palettes[svga->dac_pos][index] = val;
else
ramdac->palettes[svga->dac_pos][index] = (val & 0x3f) << 2;
svga_out(addr, val, svga);
break;
case 0x02: /* Pixel Read Mask Register (RS value = 0010) */
svga_out(addr, val, svga);
break;
case 0x04:
ramdac->index = (ramdac->index & 0x0700) | val;
if ((ramdac->index >= 0x0100) && (ramdac->index <= 0x04ff))
ramdac->cursor_array = 1;
break;
case 0x05:
ramdac->index = (ramdac->index & 0x00ff) | ((val & 0x07) << 0x08);
if ((ramdac->index >= 0x0100) && (ramdac->index <= 0x04ff))
ramdac->cursor_array = 1;
break;
case 0x06:
if ((ramdac->index < 0x0100) || (ramdac->index > 0x04ff) || ramdac->cursor_array)
ramdac->indexed_data[ramdac->index] = val;
switch (ramdac->index) {
case 0x00a:
case 0x00c:
ibm_rgb528_set_bpp(ramdac, svga);
break;
case 0x030:
switch (val & 0xc0) {
case 0x00:
ramdac->smlc_part = 0x0100;
break;
case 0x40:
ramdac->smlc_part = 0x0200;
break;
case 0x80:
ramdac->smlc_part = 0x0300;
break;
case 0xc0:
ramdac->smlc_part = 0x0400;
break;
default:
break;
}
svga->dac_hwcursor.addr = ramdac->smlc_part;
svga->dac_hwcursor.cur_xsize = svga->dac_hwcursor.cur_ysize = (val & 0x04) ? 64 : 32;
svga->dac_hwcursor.ena = ((val & 0x03) != 0x00);
break;
case 0x031:
if (!updt_cntl)
break;
ramdac->hwc_x = (ramdac->hwc_x & 0xff00) | val;
svga->dac_hwcursor.x = ((int) ramdac->hwc_x) - ramdac->cursor_hotspot_x;
break;
case 0x032:
/* Sign-extend the sign bit (7) to the remaining bits (6-4). */
val &= 0x8f;
if (val & 0x80)
val |= 0x70;
ramdac->indexed_data[ramdac->index] = val;
if (!updt_cntl)
break;
ramdac->hwc_x = (ramdac->hwc_x & 0x00ff) | (val << 8);
svga->dac_hwcursor.x = ((int) ramdac->hwc_x) - ramdac->cursor_hotspot_x;
break;
case 0x033:
if (!updt_cntl)
break;
ramdac->hwc_y = (ramdac->hwc_y & 0xff00) | val;
svga->dac_hwcursor.y = ((int) ramdac->hwc_y) - ramdac->cursor_hotspot_y;
break;
case 0x034:
/* Sign-extend the sign bit (7) to the remaining bits (6-4). */
val &= 0x8f;
if (val & 0x80)
val |= 0x70;
ramdac->indexed_data[ramdac->index] = val;
if (updt_cntl) {
ramdac->hwc_y = (ramdac->hwc_y & 0x00ff) | (val << 8);
svga->dac_hwcursor.y = ((int) ramdac->hwc_y) - ramdac->cursor_hotspot_y;
} else {
ramdac->hwc_x = ramdac->indexed_data[0x031];
ramdac->hwc_x |= (ramdac->indexed_data[0x032] << 8);
ramdac->hwc_y = ramdac->indexed_data[0x033];
ramdac->hwc_y |= (val << 8);
svga->dac_hwcursor.x = ((int) ramdac->hwc_x) - ramdac->cursor_hotspot_x;
svga->dac_hwcursor.y = ((int) ramdac->hwc_y) - ramdac->cursor_hotspot_y;
}
break;
case 0x035:
if (svga->dac_hwcursor.cur_xsize == 64)
ramdac->cursor_hotspot_x = (val & 0x3f);
else
ramdac->cursor_hotspot_x = (val & 0x1f);
svga->dac_hwcursor.x = ((int) ramdac->hwc_x) - ramdac->cursor_hotspot_x;
break;
case 0x036:
if (svga->dac_hwcursor.cur_xsize == 64)
ramdac->cursor_hotspot_y = (val & 0x3f);
else
ramdac->cursor_hotspot_y = (val & 0x1f);
svga->dac_hwcursor.y = ((int) ramdac->hwc_y) - ramdac->cursor_hotspot_y;
break;
case 0x040:
case 0x043:
case 0x046:
ramdac->extra_pal[(ramdac->index - 0x40) / 3].r = val;
break;
case 0x041:
case 0x044:
case 0x047:
ramdac->extra_pal[(ramdac->index - 0x41) / 3].g = val;
break;
case 0x042:
case 0x045:
case 0x048:
ramdac->extra_pal[(ramdac->index - 0x42) / 3].b = val;
break;
case 0x060:
ramdac->extra_pal[3].r = val;
break;
case 0x061:
ramdac->extra_pal[3].g = val;
break;
case 0x062:
ramdac->extra_pal[3].b = val;
break;
case 0x071:
svga->ramdac_type = (val & 0x04) ? RAMDAC_8BIT : RAMDAC_6BIT;
ibm_rgb528_set_bpp(ramdac, svga);
break;
default:
break;
}
if (ramdac->indx_cntl) {
if (ramdac->index == 0x00ff)
ramdac->cursor_array = 0;
ramdac->index = (ramdac->index + 1) & 0x07ff;
}
break;
case 0x07:
ramdac->indx_cntl = val & 0x01;
break;
default:
break;
}
return;
}
uint8_t
ibm_rgb528_ramdac_in(uint16_t addr, int rs2, void *priv, svga_t *svga)
{
ibm_rgb528_ramdac_t *ramdac = (ibm_rgb528_ramdac_t *) priv;
uint8_t temp = 0xff;
uint8_t rs = (addr & 0x03);
uint8_t loc_read = (ramdac->indexed_data[0x30] & 0x10);
rs |= (!!rs2 << 2);
switch (rs) {
case 0x00: /* Palette Write Index Register (RS value = 0000) */
case 0x01: /* Palette Data Register (RS value = 0001) */
case 0x02: /* Pixel Read Mask Register (RS value = 0010) */
temp = svga_in(addr, svga);
break;
case 0x03: /* Palette Read Index Register (RS value = 0011) */
temp = svga->dac_addr & 0xff;
if (ramdac->indexed_data[0x070] & 0x20)
temp = (temp & 0xfc) | svga->dac_status;
break;
case 0x04:
temp = ramdac->index & 0xff;
break;
case 0x05:
temp = ramdac->index >> 8;
break;
case 0x06:
temp = ramdac->indexed_data[ramdac->index];
switch (ramdac->index) {
case 0x0000: /* Revision */
temp = 0xe0;
break;
case 0x0001: /* ID */
temp = 0x02;
break;
case 0x0031:
if (loc_read)
temp = ramdac->hwc_x & 0xff;
break;
case 0x0032:
if (loc_read)
temp = ramdac->hwc_x >> 8;
break;
case 0x0033:
if (loc_read)
temp = ramdac->hwc_y & 0xff;
break;
case 0x0034:
if (loc_read)
temp = ramdac->hwc_y >> 8;
break;
default:
temp = ramdac->indexed_data[ramdac->index];
break;
}
if (ramdac->indx_cntl) {
if (ramdac->index == 0x00ff)
ramdac->cursor_array = 0;
ramdac->index = (ramdac->index + 1) & 0x07ff;
}
break;
case 0x07:
temp = ramdac->indx_cntl;
break;
default:
break;
}
return temp;
}
void
ibm_rgb528_recalctimings(void *priv, svga_t *svga)
{
const ibm_rgb528_ramdac_t *ramdac = (ibm_rgb528_ramdac_t *) priv;
svga->interlace = ramdac->indexed_data[0x071] & 0x20;
if (svga->scrblank || !svga->attr_palette_enable) {
if ((svga->gdcreg[6] & 1) || (svga->attrregs[0x10] & 1)) {
if (((svga->gdcreg[5] & 0x60) == 0x40) || ((svga->gdcreg[5] & 0x60) == 0x60)) {
if (ramdac->indexed_data[0x071] & 0x01) {
switch (svga->bpp) {
case 4:
svga->render = ibm_rgb528_render_4bpp;
break;
case 8:
svga->render = ibm_rgb528_render_8bpp;
break;
case 15:
case 16:
svga->render = ibm_rgb528_render_15_16bpp;
break;
case 24:
svga->render = ibm_rgb528_render_24bpp;
break;
case 32:
svga->render = ibm_rgb528_render_32bpp;
break;
default:
break;
}
}
}
}
}
}
void
ibm_rgb528_hwcursor_draw(svga_t *svga, int displine)
{
uint8_t dat;
uint8_t four_pixels = 0x00;
int pitch;
int x_pos;
int y_pos;
int offset = svga->dac_hwcursor_latch.x - svga->dac_hwcursor_latch.xoff;
uint32_t *p;
const ibm_rgb528_ramdac_t *ramdac = (ibm_rgb528_ramdac_t *) svga->ramdac;
uint8_t pix_ordr = ramdac->indexed_data[0x30] & 0x20;
uint8_t cursor_mode = ramdac->indexed_data[0x30] & 0x03;
/* The planes come in one part, and each plane is 2bpp,
so a 32x32 cursor has 8 bytes per line, and a 64x64
cursor has 16 bytes per line. */
pitch = (svga->dac_hwcursor_latch.cur_xsize >> 2); /* Bytes per line. */
if ((ramdac->indexed_data[0x071] & 0x20) && svga->dac_hwcursor_oddeven)
svga->dac_hwcursor_latch.addr += pitch;
y_pos = displine;
x_pos = offset + svga->x_add;
p = buffer32->line[y_pos];
for (int x = 0; x < svga->dac_hwcursor_latch.cur_xsize; x++) {
if (!(x & 3))
four_pixels = ramdac->indexed_data[svga->dac_hwcursor_latch.addr];
if (pix_ordr)
dat = (four_pixels >> (((3 - x) & 3) << 1)) & 0x03;
else
dat = (four_pixels >> ((x & 3) << 1)) & 0x03;
x_pos = offset + svga->x_add + x;
switch (cursor_mode) {
case 0x01:
switch (dat) {
case 0x01:
/* Cursor Color 1 */
p[x_pos] = ramdac->extra_pal[0].pixel;
break;
case 0x02:
/* Cursor Color 2 */
p[x_pos] = ramdac->extra_pal[1].pixel;
break;
case 0x03:
/* Cursor Color 3 */
p[x_pos] = ramdac->extra_pal[2].pixel;
break;
default:
break;
}
break;
case 0x02:
switch (dat) {
case 0x00:
/* Cursor Color 1 */
p[x_pos] = ramdac->extra_pal[0].pixel;
break;
case 0x01:
/* Cursor Color 2 */
p[x_pos] = ramdac->extra_pal[1].pixel;
break;
case 0x03:
/* Complement */
p[x_pos] ^= 0xffffff;
break;
default:
break;
}
break;
case 0x03:
switch (dat) {
case 0x02:
/* Cursor Color 1 */
p[x_pos] = ramdac->extra_pal[0].pixel;
break;
case 0x03:
/* Cursor Color 2 */
p[x_pos] = ramdac->extra_pal[1].pixel;
break;
default:
break;
}
break;
default:
break;
}
if ((x & 3) == 3)
svga->dac_hwcursor_latch.addr++;
}
if ((ramdac->indexed_data[0x071] & 0x20) && !svga->dac_hwcursor_oddeven)
svga->dac_hwcursor_latch.addr += pitch;
}
void *
ibm_rgb528_ramdac_init(UNUSED(const device_t *info))
{
ibm_rgb528_ramdac_t *ramdac = (ibm_rgb528_ramdac_t *) malloc(sizeof(ibm_rgb528_ramdac_t));
memset(ramdac, 0, sizeof(ibm_rgb528_ramdac_t));
ramdac->smlc_part = 0x0100;
ramdac->indexed_data[0x0008] = 0x0001;
ramdac->indexed_data[0x0015] = 0x0008;
ramdac->indexed_data[0x0016] = 0x0041;
return ramdac;
}
static void
ibm_rgb528_ramdac_close(void *priv)
{
ibm_rgb528_ramdac_t *ramdac = (ibm_rgb528_ramdac_t *) priv;
if (ramdac)
free(ramdac);
}
const device_t ibm_rgb528_ramdac_device = {
.name = "IBM RGB528 RAMDAC",
.internal_name = "ibm_rgb528_ramdac",
.flags = 0,
.local = 0,
.init = ibm_rgb528_ramdac_init,
.close = ibm_rgb528_ramdac_close,
.reset = NULL,
{ .available = NULL },
.speed_changed = NULL,
.force_redraw = NULL,
.config = NULL
};
``` | /content/code_sandbox/src/video/vid_ibm_rgb528_ramdac.c | c | 2016-06-25T22:29:10 | 2024-08-16T19:09:21 | 86Box | 86Box/86Box | 2,616 | 11,670 |
```c
/*
* 86Box A hypervisor and IBM PC system emulator that specializes in
* running old operating systems and software designed for IBM
* PC systems and compatibles from 1981 through fairly recent
* system designs based on the PCI bus.
*
* This file is part of the 86Box distribution.
*
* Emulation of the Brooktree BT484-485A true colour RAMDAC
* family.
*
*
*
* Authors: Miran Grca, <mgrca8@gmail.com>
* TheCollector1995,
*
*/
#include <stdio.h>
#include <stdint.h>
#include <stdlib.h>
#include <string.h>
#include <wchar.h>
#include <86box/86box.h>
#include <86box/device.h>
#include <86box/mem.h>
#include <86box/timer.h>
#include <86box/video.h>
#include <86box/vid_svga.h>
typedef struct bt48x_ramdac_t {
PALETTE extpal;
uint32_t extpallook[256];
uint8_t cursor32_data[256];
uint8_t cursor64_data[1024];
int hwc_y;
int hwc_x;
uint8_t cmd_r0;
uint8_t cmd_r1;
uint8_t cmd_r2;
uint8_t cmd_r3;
uint8_t cmd_r4;
uint8_t status;
uint8_t type;
} bt48x_ramdac_t;
enum {
BT484 = 0,
ATT20C504,
BT485,
ATT20C505,
BT485A
};
static void
bt48x_set_bpp(bt48x_ramdac_t *ramdac, svga_t *svga)
{
if ((!(ramdac->cmd_r2 & 0x20)) || ((ramdac->type >= BT485A) && ((ramdac->cmd_r3 & 0x60) == 0x60)))
svga->bpp = 8;
else if ((ramdac->type >= BT485A) && ((ramdac->cmd_r3 & 0x60) == 0x40))
svga->bpp = 24;
else
switch (ramdac->cmd_r1 & 0x60) {
case 0x00:
svga->bpp = 32;
break;
case 0x20:
if (ramdac->cmd_r1 & 0x08)
svga->bpp = 16;
else
svga->bpp = 15;
break;
case 0x40:
svga->bpp = 8;
break;
case 0x60:
svga->bpp = 4;
break;
default:
break;
}
svga_recalctimings(svga);
}
void
bt48x_ramdac_out(uint16_t addr, int rs2, int rs3, uint8_t val, void *priv, svga_t *svga)
{
bt48x_ramdac_t *ramdac = (bt48x_ramdac_t *) priv;
uint32_t o32;
uint8_t *cd;
uint16_t index;
uint8_t rs = (addr & 0x03);
uint16_t da_mask = 0x03ff;
rs |= (!!rs2 << 2);
rs |= (!!rs3 << 3);
if (ramdac->type < BT485)
da_mask = 0x00ff;
switch (rs) {
case 0x00: /* Palette Write Index Register (RS value = 0000) */
case 0x04: /* Ext Palette Write Index Register (RS value = 0100) */
case 0x03:
case 0x07: /* Ext Palette Read Index Register (RS value = 0111) */
svga->dac_pos = 0;
svga->dac_status = addr & 0x03;
svga->dac_addr = val;
if (ramdac->type >= BT485)
svga->dac_addr |= ((ramdac->cmd_r3 & 0x03) << 8);
if (svga->dac_status)
svga->dac_addr = (svga->dac_addr + 1) & da_mask;
break;
case 0x01: /* Palette Data Register (RS value = 0001) */
case 0x02: /* Pixel Read Mask Register (RS value = 0010) */
svga_out(addr, val, svga);
break;
case 0x05: /* Ext Palette Data Register (RS value = 0101) */
svga->dac_status = 0;
svga->fullchange = changeframecount;
switch (svga->dac_pos) {
case 0:
svga->dac_r = val;
svga->dac_pos++;
break;
case 1:
svga->dac_g = val;
svga->dac_pos++;
break;
case 2:
index = svga->dac_addr & 3;
ramdac->extpal[index].r = svga->dac_r;
ramdac->extpal[index].g = svga->dac_g;
ramdac->extpal[index].b = val;
if (svga->ramdac_type == RAMDAC_8BIT)
ramdac->extpallook[index] = makecol32(ramdac->extpal[index].r, ramdac->extpal[index].g, ramdac->extpal[index].b);
else
ramdac->extpallook[index] = makecol32(video_6to8[ramdac->extpal[index].r & 0x3f], video_6to8[ramdac->extpal[index].g & 0x3f], video_6to8[ramdac->extpal[index].b & 0x3f]);
if (svga->ext_overscan && !index) {
o32 = svga->overscan_color;
svga->overscan_color = ramdac->extpallook[0];
if (o32 != svga->overscan_color)
svga_recalctimings(svga);
}
svga->dac_addr = (svga->dac_addr + 1) & 0xff;
svga->dac_pos = 0;
break;
default:
break;
}
break;
case 0x06: /* Command Register 0 (RS value = 0110) */
ramdac->cmd_r0 = val;
svga->ramdac_type = (val & 0x02) ? RAMDAC_8BIT : RAMDAC_6BIT;
break;
case 0x08: /* Command Register 1 (RS value = 1000) */
ramdac->cmd_r1 = val;
bt48x_set_bpp(ramdac, svga);
break;
case 0x09: /* Command Register 2 (RS value = 1001) */
ramdac->cmd_r2 = val;
svga->dac_hwcursor.ena = !!(val & 0x03);
bt48x_set_bpp(ramdac, svga);
break;
case 0x0a:
if ((ramdac->type >= BT485) && (ramdac->cmd_r0 & 0x80)) {
switch (svga->dac_addr & ((ramdac->type >= BT485A) ? 0xff : 0x3f)) {
case 0x01:
/* Command Register 3 (RS value = 1010) */
ramdac->cmd_r3 = val;
if (ramdac->type >= BT485A)
bt48x_set_bpp(ramdac, svga);
svga->dac_hwcursor.cur_xsize = svga->dac_hwcursor.cur_ysize = (val & 4) ? 64 : 32;
svga->dac_hwcursor.x = ramdac->hwc_x - svga->dac_hwcursor.cur_xsize;
svga->dac_hwcursor.y = ramdac->hwc_y - svga->dac_hwcursor.cur_ysize;
svga->dac_addr = (svga->dac_addr & 0x00ff) | ((val & 0x03) << 8);
svga_recalctimings(svga);
break;
case 0x02:
case 0x20:
case 0x21:
case 0x22:
if (ramdac->type != BT485A)
break;
else if (svga->dac_addr == 2) {
ramdac->cmd_r4 = val;
break;
}
break;
default:
break;
}
}
break;
case 0x0b: /* Cursor RAM Data Register (RS value = 1011) */
index = svga->dac_addr & da_mask;
if ((ramdac->type >= BT485) && (svga->dac_hwcursor.cur_xsize == 64))
cd = (uint8_t *) ramdac->cursor64_data;
else {
index &= 0xff;
cd = (uint8_t *) ramdac->cursor32_data;
}
cd[index] = val;
svga->dac_addr = (svga->dac_addr + 1) & da_mask;
break;
case 0x0c: /* Cursor X Low Register (RS value = 1100) */
ramdac->hwc_x = (ramdac->hwc_x & 0x0f00) | val;
svga->dac_hwcursor.x = ramdac->hwc_x - svga->dac_hwcursor.cur_xsize;
break;
case 0x0d: /* Cursor X High Register (RS value = 1101) */
ramdac->hwc_x = (ramdac->hwc_x & 0x00ff) | ((val & 0x0f) << 8);
svga->dac_hwcursor.x = ramdac->hwc_x - svga->dac_hwcursor.cur_xsize;
break;
case 0x0e: /* Cursor Y Low Register (RS value = 1110) */
ramdac->hwc_y = (ramdac->hwc_y & 0x0f00) | val;
svga->dac_hwcursor.y = ramdac->hwc_y - svga->dac_hwcursor.cur_ysize;
break;
case 0x0f: /* Cursor Y High Register (RS value = 1111) */
ramdac->hwc_y = (ramdac->hwc_y & 0x00ff) | ((val & 0x0f) << 8);
svga->dac_hwcursor.y = ramdac->hwc_y - svga->dac_hwcursor.cur_ysize;
break;
default:
break;
}
return;
}
uint8_t
bt48x_ramdac_in(uint16_t addr, int rs2, int rs3, void *priv, svga_t *svga)
{
bt48x_ramdac_t *ramdac = (bt48x_ramdac_t *) priv;
uint8_t temp = 0xff;
const uint8_t *cd;
uint16_t index;
uint8_t rs = (addr & 0x03);
uint16_t da_mask = 0x03ff;
rs |= (!!rs2 << 2);
rs |= (!!rs3 << 3);
if (ramdac->type < BT485)
da_mask = 0x00ff;
switch (rs) {
case 0x00: /* Palette Write Index Register (RS value = 0000) */
case 0x01: /* Palette Data Register (RS value = 0001) */
case 0x02: /* Pixel Read Mask Register (RS value = 0010) */
case 0x04: /* Ext Palette Write Index Register (RS value = 0100) */
temp = svga_in(addr, svga);
break;
case 0x03: /* Palette Read Index Register (RS value = 0011) */
case 0x07: /* Ext Palette Read Index Register (RS value = 0111) */
temp = svga->dac_addr & 0xff;
break;
case 0x05: /* Ext Palette Data Register (RS value = 0101) */
index = (svga->dac_addr - 1) & 3;
svga->dac_status = 3;
switch (svga->dac_pos) {
case 0:
svga->dac_pos++;
if (svga->ramdac_type == RAMDAC_8BIT)
temp = ramdac->extpal[index].r;
else
temp = ramdac->extpal[index].r & 0x3f;
break;
case 1:
svga->dac_pos++;
if (svga->ramdac_type == RAMDAC_8BIT)
temp = ramdac->extpal[index].g;
else
temp = ramdac->extpal[index].g & 0x3f;
break;
case 2:
svga->dac_pos = 0;
svga->dac_addr = svga->dac_addr + 1;
if (svga->ramdac_type == RAMDAC_8BIT)
temp = ramdac->extpal[index].b;
else
temp = ramdac->extpal[index].b & 0x3f;
break;
default:
break;
}
break;
case 0x06: /* Command Register 0 (RS value = 0110) */
temp = ramdac->cmd_r0;
break;
case 0x08: /* Command Register 1 (RS value = 1000) */
temp = ramdac->cmd_r1;
break;
case 0x09: /* Command Register 2 (RS value = 1001) */
temp = ramdac->cmd_r2;
break;
case 0x0a:
if ((ramdac->type >= BT485) && (ramdac->cmd_r0 & 0x80)) {
switch (svga->dac_addr & ((ramdac->type >= BT485A) ? 0xff : 0x3f)) {
default:
case 0x00:
temp = ramdac->status | (svga->dac_status ? 0x04 : 0x00);
break;
case 0x01:
temp = ramdac->cmd_r3 & 0xfc;
temp |= (svga->dac_addr & 0x300) >> 8;
break;
case 0x02:
case 0x20:
case 0x21:
case 0x22:
if (ramdac->type != BT485A)
break;
else if (svga->dac_addr == 2) {
temp = ramdac->cmd_r4;
break;
} else {
/* TODO: Red, Green, and Blue Signature Analysis Registers */
temp = 0xff;
break;
}
}
} else
temp = ramdac->status | (svga->dac_status ? 0x04 : 0x00);
break;
case 0x0b: /* Cursor RAM Data Register (RS value = 1011) */
index = (svga->dac_addr - 1) & da_mask;
if ((ramdac->type >= BT485) && (svga->dac_hwcursor.cur_xsize == 64))
cd = (uint8_t *) ramdac->cursor64_data;
else {
index &= 0xff;
cd = (uint8_t *) ramdac->cursor32_data;
}
temp = cd[index];
svga->dac_addr = (svga->dac_addr + 1) & da_mask;
break;
case 0x0c: /* Cursor X Low Register (RS value = 1100) */
temp = ramdac->hwc_x & 0xff;
break;
case 0x0d: /* Cursor X High Register (RS value = 1101) */
temp = (ramdac->hwc_x >> 8) & 0xff;
break;
case 0x0e: /* Cursor Y Low Register (RS value = 1110) */
temp = ramdac->hwc_y & 0xff;
break;
case 0x0f: /* Cursor Y High Register (RS value = 1111) */
temp = (ramdac->hwc_y >> 8) & 0xff;
break;
default:
break;
}
return temp;
}
void
bt48x_recalctimings(void *priv, svga_t *svga)
{
const bt48x_ramdac_t *ramdac = (bt48x_ramdac_t *) priv;
svga->interlace = ramdac->cmd_r2 & 0x08;
if (ramdac->cmd_r3 & 0x08)
svga->hdisp *= 2; /* x2 clock multiplier */
}
void
bt48x_hwcursor_draw(svga_t *svga, int displine)
{
int comb;
int b0;
int b1;
uint16_t dat[2];
int offset = svga->dac_hwcursor_latch.x - svga->dac_hwcursor_latch.xoff;
int pitch;
int bppl;
int mode;
int x_pos;
int y_pos;
uint32_t clr1;
uint32_t clr2;
uint32_t clr3;
uint32_t *p;
const uint8_t *cd;
bt48x_ramdac_t *ramdac = (bt48x_ramdac_t *) svga->ramdac;
clr1 = ramdac->extpallook[1];
clr2 = ramdac->extpallook[2];
clr3 = ramdac->extpallook[3];
/* The planes come in two parts, and each plane is 1bpp,
so a 32x32 cursor has 4 bytes per line, and a 64x64
cursor has 8 bytes per line. */
pitch = (svga->dac_hwcursor_latch.cur_xsize >> 3); /* Bytes per line. */
/* A 32x32 cursor has 128 bytes per line, and a 64x64
cursor has 512 bytes per line. */
bppl = (pitch * svga->dac_hwcursor_latch.cur_ysize); /* Bytes per plane. */
mode = ramdac->cmd_r2 & 0x03;
if (svga->interlace && svga->dac_hwcursor_oddeven)
svga->dac_hwcursor_latch.addr += pitch;
if (svga->dac_hwcursor_latch.cur_xsize == 64)
cd = (uint8_t *) ramdac->cursor64_data;
else
cd = (uint8_t *) ramdac->cursor32_data;
for (int x = 0; x < svga->dac_hwcursor_latch.cur_xsize; x += 16) {
dat[0] = (cd[svga->dac_hwcursor_latch.addr] << 8) | cd[svga->dac_hwcursor_latch.addr + 1];
dat[1] = (cd[svga->dac_hwcursor_latch.addr + bppl] << 8) | cd[svga->dac_hwcursor_latch.addr + bppl + 1];
for (uint8_t xx = 0; xx < 16; xx++) {
b0 = (dat[0] >> (15 - xx)) & 1;
b1 = (dat[1] >> (15 - xx)) & 1;
comb = (b0 | (b1 << 1));
y_pos = displine;
x_pos = (offset + svga->x_add) & 2047;
p = buffer32->line[y_pos];
if (offset >= svga->dac_hwcursor_latch.x) {
switch (mode) {
case 1: /* Three Color */
switch (comb) {
case 1:
p[x_pos] = clr1;
break;
case 2:
p[x_pos] = clr2;
break;
case 3:
p[x_pos] = clr3;
break;
default:
break;
}
break;
case 2: /* PM/Windows */
switch (comb) {
case 0:
p[x_pos] = clr1;
break;
case 1:
p[x_pos] = clr2;
break;
case 3:
p[x_pos] ^= 0xffffff;
break;
default:
break;
}
break;
case 3: /* X-Windows */
switch (comb) {
case 2:
p[x_pos] = clr1;
break;
case 3:
p[x_pos] = clr2;
break;
default:
break;
}
break;
default:
break;
}
}
offset++;
}
svga->dac_hwcursor_latch.addr += 2;
}
if (svga->interlace && !svga->dac_hwcursor_oddeven)
svga->dac_hwcursor_latch.addr += pitch;
}
void *
bt48x_ramdac_init(const device_t *info)
{
bt48x_ramdac_t *ramdac = (bt48x_ramdac_t *) malloc(sizeof(bt48x_ramdac_t));
memset(ramdac, 0, sizeof(bt48x_ramdac_t));
ramdac->type = info->local;
/* Set the RAM DAC status byte to the correct ID bits.
Both the BT484 and BT485 datasheets say this:
SR7-SR6: These bits are identification values. SR7=0 and SR6=1.
But all other sources seem to assume SR7=1 and SR6=0. */
switch (ramdac->type) {
case BT484:
ramdac->status = 0x40;
break;
case ATT20C504:
ramdac->status = 0x40;
break;
case BT485:
ramdac->status = 0x60;
break;
case ATT20C505:
ramdac->status = 0xd0;
break;
case BT485A:
ramdac->status = 0x20;
break;
default:
break;
}
return ramdac;
}
static void
bt48x_ramdac_close(void *priv)
{
bt48x_ramdac_t *ramdac = (bt48x_ramdac_t *) priv;
if (ramdac)
free(ramdac);
}
const device_t bt484_ramdac_device = {
.name = "Brooktree Bt484 RAMDAC",
.internal_name = "bt484_ramdac",
.flags = 0,
.local = BT484,
.init = bt48x_ramdac_init,
.close = bt48x_ramdac_close,
.reset = NULL,
{ .available = NULL },
.speed_changed = NULL,
.force_redraw = NULL,
.config = NULL
};
const device_t att20c504_ramdac_device = {
.name = "AT&T 20c504 RAMDAC",
.internal_name = "att20c504_ramdac",
.flags = 0,
.local = ATT20C504,
.init = bt48x_ramdac_init,
.close = bt48x_ramdac_close,
.reset = NULL,
{ .available = NULL },
.speed_changed = NULL,
.force_redraw = NULL,
.config = NULL
};
const device_t bt485_ramdac_device = {
.name = "Brooktree Bt485 RAMDAC",
.internal_name = "bt485_ramdac",
.flags = 0,
.local = BT485,
.init = bt48x_ramdac_init,
.close = bt48x_ramdac_close,
.reset = NULL,
{ .available = NULL },
.speed_changed = NULL,
.force_redraw = NULL,
.config = NULL
};
const device_t att20c505_ramdac_device = {
.name = "AT&T 20c505 RAMDAC",
.internal_name = "att20c505_ramdac",
.flags = 0,
.local = ATT20C505,
.init = bt48x_ramdac_init,
.close = bt48x_ramdac_close,
.reset = NULL,
{ .available = NULL },
.speed_changed = NULL,
.force_redraw = NULL,
.config = NULL
};
const device_t bt485a_ramdac_device = {
.name = "Brooktree Bt485A RAMDAC",
.internal_name = "bt485a_ramdac",
.flags = 0,
.local = BT485A,
.init = bt48x_ramdac_init,
.close = bt48x_ramdac_close,
.reset = NULL,
{ .available = NULL },
.speed_changed = NULL,
.force_redraw = NULL,
.config = NULL
};
``` | /content/code_sandbox/src/video/vid_bt48x_ramdac.c | c | 2016-06-25T22:29:10 | 2024-08-16T19:09:21 | 86Box | 86Box/86Box | 2,616 | 5,680 |
```c
/*
* 86Box A hypervisor and IBM PC system emulator that specializes in
* running old operating systems and software designed for IBM
* PC systems and compatibles from 1981 through fairly recent
* system designs based on the PCI bus.
*
* This file is part of the 86Box distribution.
*
* Matrox MGA graphics card emulation.
*
*
*
* Authors: Sarah Walker, <path_to_url
*
*/
#include <stdio.h>
#include <stdbool.h>
#include <stdint.h>
#include <string.h>
#include <stdlib.h>
#include <wchar.h>
#include <stdatomic.h>
#include <86box/86box.h>
#include <86box/io.h>
#include <86box/timer.h>
#include <86box/mem.h>
#include <86box/pci.h>
#include <86box/rom.h>
#include <86box/device.h>
#include <86box/dma.h>
#include <86box/plat.h>
#include <86box/thread.h>
#include <86box/video.h>
#include <86box/i2c.h>
#include <86box/vid_ddc.h>
#include <86box/vid_svga.h>
#include <86box/vid_svga_render.h>
#define ROM_MILLENNIUM "roms/video/matrox/matrox2064wr2.BIN"
#define ROM_MILLENNIUM_II "roms/video/matrox/matrox2164wpc.BIN"
#define ROM_MYSTIQUE "roms/video/matrox/MYSTIQUE.VBI"
#define ROM_MYSTIQUE_220 "roms/video/matrox/Myst220_66-99mhz.vbi"
#define ROM_G100 "roms/video/matrox/productiva8mbsdr.BIN"
#define FIFO_SIZE 65536
#define FIFO_MASK (FIFO_SIZE - 1)
#define FIFO_ENTRY_SIZE (1 << 31)
#define FIFO_THRESHOLD 0xe000
#define WAKE_DELAY (100 * TIMER_USEC) /* 100us */
#define FIFO_ENTRIES (mystique->fifo_write_idx - mystique->fifo_read_idx)
#define FIFO_FULL ((mystique->fifo_write_idx - mystique->fifo_read_idx) >= (FIFO_SIZE - 1))
#define FIFO_EMPTY (mystique->fifo_read_idx == mystique->fifo_write_idx)
#define FIFO_TYPE 0xff000000
#define FIFO_ADDR 0x00ffffff
#define DMA_POLL_TIME_US 100 /*100us*/
#define DMA_MAX_WORDS (20 * 14) /*280 quad words per 100us poll*/
/*These registers are also mirrored into 0x1dxx, with the mirrored versions starting
the blitter*/
#define REG_DWGCTL 0x1c00
#define REG_MACCESS 0x1c04
#define REG_MCTLWTST 0x1c08
#define REG_ZORG 0x1c0c
#define REG_PAT0 0x1c10
#define REG_PAT1 0x1c14
#define REG_PLNWT 0x1c1c
#define REG_BCOL 0x1c20
#define REG_FCOL 0x1c24
#define REG_SRC0 0x1c30
#define REG_SRC1 0x1c34
#define REG_SRC2 0x1c38
#define REG_SRC3 0x1c3c
#define REG_XYSTRT 0x1c40
#define REG_XYEND 0x1c44
#define REG_SHIFT 0x1c50
#define REG_DMAPAD 0x1c54
#define REG_SGN 0x1c58
#define REG_LEN 0x1c5c
#define REG_AR0 0x1c60
#define REG_AR1 0x1c64
#define REG_AR2 0x1c68
#define REG_AR3 0x1c6c
#define REG_AR4 0x1c70
#define REG_AR5 0x1c74
#define REG_AR6 0x1c78
#define REG_CXBNDRY 0x1c80
#define REG_FXBNDRY 0x1c84
#define REG_YDSTLEN 0x1c88
#define REG_PITCH 0x1c8c
#define REG_YDST 0x1c90
#define REG_YDSTORG 0x1c94
#define REG_YTOP 0x1c98
#define REG_YBOT 0x1c9c
#define REG_CXLEFT 0x1ca0
#define REG_CXRIGHT 0x1ca4
#define REG_FXLEFT 0x1ca8
#define REG_FXRIGHT 0x1cac
#define REG_XDST 0x1cb0
#define REG_DR0 0x1cc0
#define REG_DR2 0x1cc8
#define REG_DR3 0x1ccc
#define REG_DR4 0x1cd0
#define REG_DR6 0x1cd8
#define REG_DR7 0x1cdc
#define REG_DR8 0x1ce0
#define REG_DR10 0x1ce8
#define REG_DR11 0x1cec
#define REG_DR12 0x1cf0
#define REG_DR14 0x1cf8
#define REG_DR15 0x1cfc
#define REG_DR0_Z32LSB 0x2c50
#define REG_DR0_Z32MSB 0x2c54
#define REG_DR2_Z32LSB 0x2c60
#define REG_DR2_Z32MSB 0x2c64
#define REG_DR3_Z32LSB 0x2c68
#define REG_DR3_Z32MSB 0x2c6c
#define REG_TEXFILTER 0x2c58
#define REG_FIFOSTATUS 0x1e10
#define REG_STATUS 0x1e14
#define REG_ICLEAR 0x1e18
#define REG_IEN 0x1e1c
#define REG_VCOUNT 0x1e20
#define REG_DMAMAP 0x1e30
#define REG_RST 0x1e40
#define REG_OPMODE 0x1e54
#define REG_PRIMADDRESS 0x1e58
#define REG_PRIMEND 0x1e5c
#define REG_DWG_INDIR_WT 0x1e80
#define REG_ATTR_IDX 0x1fc0
#define REG_ATTR_DATA 0x1fc1
#define REG_INSTS0 0x1fc2
#define REG_MISC 0x1fc2
#define REG_SEQ_IDX 0x1fc4
#define REG_SEQ_DATA 0x1fc5
#define REG_MISCREAD 0x1fcc
#define REG_GCTL_IDX 0x1fce
#define REG_GCTL_DATA 0x1fcf
#define REG_CRTC_IDX 0x1fd4
#define REG_CRTC_DATA 0x1fd5
#define REG_INSTS1 0x1fda
#define REG_CRTCEXT_IDX 0x1fde
#define REG_CRTCEXT_DATA 0x1fdf
#define REG_CACHEFLUSH 0x1fff
/*Mystique only*/
#define REG_TMR0 0x2c00
#define REG_TMR1 0x2c04
#define REG_TMR2 0x2c08
#define REG_TMR3 0x2c0c
#define REG_TMR4 0x2c10
#define REG_TMR5 0x2c14
#define REG_TMR6 0x2c18
#define REG_TMR7 0x2c1c
#define REG_TMR8 0x2c20
#define REG_TEXORG 0x2c24
#define REG_TEXWIDTH 0x2c28
#define REG_TEXHEIGHT 0x2c2c
#define REG_TEXCTL 0x2c30
#define REG_TEXTRANS 0x2c34
#define REG_SECADDRESS 0x2c40
#define REG_SECEND 0x2c44
#define REG_SOFTRAP 0x2c48
#define REG_ALPHASTART 0x2c70
#define REG_ALPHACTRL 0x2c7c
#define REG_ALPHAXINC 0x2c74
#define REG_ALPHAYINC 0x2c78
#define REG_FOGSTART 0x1cc4
#define REG_FOGXINC 0x1cd4
#define REG_FOGYINC 0x1ce4
#define REG_FOGCOL 0x1cf4
/*Mystique only*/
#define REG_PALWTADD 0x3c00
#define REG_PALDATA 0x3c01
#define REG_PIXRDMSK 0x3c02
#define REG_PALRDADD 0x3c03
#define REG_X_DATAREG 0x3c0a
#define REG_CURPOSX 0x3c0c
#define REG_CURPOSY 0x3c0e
#define REG_STATUS_VSYNCSTS (1 << 3)
#define CRTCX_R0_STARTADD_MASK (0xf << 0)
#define CRTCX_R0_OFFSET_MASK (3 << 4)
#define CRTCX_R1_HTOTAL8 (1 << 0)
#define CRTCX_R1_HBLKSTRT8 (1 << 1)
#define CRTCX_R1_HBLKEND6 (1 << 6)
#define CRTCX_R2_VTOTAL10 (1 << 0)
#define CRTCX_R2_VTOTAL11 (1 << 1)
#define CRTCX_R2_VDISPEND10 (1 << 2)
#define CRTCX_R2_VBLKSTR10 (1 << 3)
#define CRTCX_R2_VBLKSTR11 (1 << 4)
#define CRTCX_R2_VSYNCSTR10 (1 << 5)
#define CRTCX_R2_VSYNCSTR11 (1 << 6)
#define CRTCX_R2_LINECOMP10 (1 << 7)
#define CRTCX_R3_MGAMODE (1 << 7)
#define XREG_XCURADDL 0x04
#define XREG_XCURADDH 0x05
#define XREG_XCURCTRL 0x06
#define XREG_XCURCOL0R 0x08
#define XREG_XCURCOL0G 0x09
#define XREG_XCURCOL0B 0x0a
#define XREG_XCURCOL1R 0x0c
#define XREG_XCURCOL1G 0x0d
#define XREG_XCURCOL1B 0x0e
#define XREG_XCURCOL2R 0x10
#define XREG_XCURCOL2G 0x11
#define XREG_XCURCOL2B 0x12
#define XREG_XVREFCTRL 0x18
#define XREG_XMULCTRL 0x19
#define XREG_XPIXCLKCTRL 0x1a
#define XREG_XGENCTRL 0x1d
#define XREG_XMISCCTRL 0x1e
#define XREG_XGENIOCTRL 0x2a
#define XREG_XGENIODATA 0x2b
#define XREG_XSYSPLLM 0x2c
#define XREG_XSYSPLLN 0x2d
#define XREG_XSYSPLLP 0x2e
#define XREG_XSYSPLLSTAT 0x2f
#define XREG_XZOOMCTRL 0x38
#define XREG_XSENSETEST 0x3a
#define XREG_XCRCREML 0x3c
#define XREG_XCRCREMH 0x3d
#define XREG_XCRCBITSEL 0x3e
#define XREG_XCOLKEYMSKL 0x40
#define XREG_XCOLKEYMSKH 0x41
#define XREG_XCOLKEYL 0x42
#define XREG_XCOLKEYH 0x43
#define XREG_XPIXPLLCM 0x4c
#define XREG_XPIXPLLCN 0x4d
#define XREG_XPIXPLLCP 0x4e
#define XREG_XPIXPLLSTAT 0x4f
#define XMISCCTRL_VGA8DAC (1 << 3)
#define XMISCCTRL_RAMCS (1 << 4)
#define XMULCTRL_DEPTH_MASK (7 << 0)
#define XMULCTRL_DEPTH_8 (0 << 0)
#define XMULCTRL_DEPTH_15 (1 << 0)
#define XMULCTRL_DEPTH_16 (2 << 0)
#define XMULCTRL_DEPTH_24 (3 << 0)
#define XMULCTRL_DEPTH_32_OVERLAYED (4 << 0)
#define XMULCTRL_DEPTH_2G8V16 (5 << 0)
#define XMULCTRL_DEPTH_G16V16 (6 << 0)
#define XMULCTRL_DEPTH_32 (7 << 0)
#define XSYSPLLSTAT_SYSLOCK (1 << 6)
#define XPIXPLLSTAT_SYSLOCK (1 << 6)
#define XCURCTRL_CURMODE_MASK (3 << 0)
#define XCURCTRL_CURMODE_3COL (1 << 0)
#define XCURCTRL_CURMODE_XGA (2 << 0)
#define XCURCTRL_CURMODE_XWIN (3 << 0)
#define DWGCTRL_OPCODE_MASK (0xf << 0)
#define DWGCTRL_OPCODE_LINE_OPEN (0x0 << 0)
#define DWGCTRL_OPCODE_AUTOLINE_OPEN (0x1 << 0)
#define DWGCTRL_OPCODE_LINE_CLOSE (0x2 << 0)
#define DWGCTRL_OPCODE_AUTOLINE_CLOSE (0x3 << 0)
#define DWGCTRL_OPCODE_TRAP (0x4 << 0)
#define DWGCTRL_OPCODE_TEXTURE_TRAP (0x6 << 0)
#define DWGCTRL_OPCODE_ILOAD_HIGH (0x7 << 0)
#define DWGCTRL_OPCODE_BITBLT (0x8 << 0)
#define DWGCTRL_OPCODE_ILOAD (0x9 << 0)
#define DWGCTRL_OPCODE_IDUMP (0xa << 0)
#define DWGCTRL_OPCODE_FBITBLT (0xc << 0)
#define DWGCTRL_OPCODE_ILOAD_SCALE (0xd << 0)
#define DWGCTRL_OPCODE_ILOAD_HIGHV (0xe << 0)
#define DWGCTRL_OPCODE_ILOAD_FILTER (0xf << 0) /* Not implemented. */
#define DWGCTRL_ATYPE_MASK (7 << 4)
#define DWGCTRL_ATYPE_RPL (0 << 4)
#define DWGCTRL_ATYPE_RSTR (1 << 4)
#define DWGCTRL_ATYPE_ZI (3 << 4)
#define DWGCTRL_ATYPE_BLK (4 << 4)
#define DWGCTRL_ATYPE_I (7 << 4)
#define DWGCTRL_LINEAR (1 << 7)
#define DWGCTRL_ZMODE_MASK (7 << 8)
#define DWGCTRL_ZMODE_NOZCMP (0 << 8)
#define DWGCTRL_ZMODE_ZE (2 << 8)
#define DWGCTRL_ZMODE_ZNE (3 << 8)
#define DWGCTRL_ZMODE_ZLT (4 << 8)
#define DWGCTRL_ZMODE_ZLTE (5 << 8)
#define DWGCTRL_ZMODE_ZGT (6 << 8)
#define DWGCTRL_ZMODE_ZGTE (7 << 8)
#define DWGCTRL_SOLID (1 << 11)
#define DWGCTRL_ARZERO (1 << 12)
#define DWGCTRL_SGNZERO (1 << 13)
#define DWGCTRL_SHTZERO (1 << 14)
#define DWGCTRL_BOP_MASK (0xf << 16)
#define DWGCTRL_TRANS_SHIFT (20)
#define DWGCTRL_TRANS_MASK (0xf << DWGCTRL_TRANS_SHIFT)
#define DWGCTRL_BLTMOD_MASK (0xf << 25)
#define DWGCTRL_BLTMOD_BMONOLEF (0x0 << 25)
#define DWGCTRL_BLTMOD_BPLAN (0x1 << 25)
#define DWGCTRL_BLTMOD_BFCOL (0x2 << 25)
#define DWGCTRL_BLTMOD_BU32BGR (0x3 << 25)
#define DWGCTRL_BLTMOD_BMONOWF (0x4 << 25)
#define DWGCTRL_BLTMOD_BU32RGB (0x7 << 25)
#define DWGCTRL_BLTMOD_BUYUV (0xe << 25)
#define DWGCTRL_BLTMOD_BU24RGB (0xf << 25)
#define DWGCTRL_PATTERN (1 << 29)
#define DWGCTRL_TRANSC (1 << 30)
#define BOP(x) ((x) << 16)
#define MACCESS_PWIDTH_MASK (3 << 0)
#define MACCESS_PWIDTH_8 (0 << 0)
#define MACCESS_PWIDTH_16 (1 << 0)
#define MACCESS_PWIDTH_32 (2 << 0)
#define MACCESS_PWIDTH_24 (3 << 0)
#define MACCESS_ZWIDTH (1 << 3)
#define MACCESS_FOGEN (1 << 26)
#define MACCESS_TLUTLOAD (1 << 29)
#define MACCESS_NODITHER (1 << 30)
#define MACCESS_DIT555 (1 << 31)
#define PITCH_MASK 0xfe0
#define PITCH_YLIN (1 << 15)
#define SGN_SDYDXL (1 << 0)
#define SGN_SCANLEFT (1 << 0)
#define SGN_SDXL (1 << 1)
#define SGN_SDY (1 << 2)
#define SGN_SDXR (1 << 5)
#define DMA_ADDR_MASK 0xfffffffc
#define DMA_MODE_MASK 3
#define DMA_MODE_REG 0
#define DMA_MODE_BLIT 1
#define DMA_MODE_VECTOR 2
#define STATUS_SOFTRAPEN (1 << 0)
#define STATUS_VSYNCPEN (1 << 4)
#define STATUS_VLINEPEN (1 << 5)
#define STATUS_DWGENGSTS (1 << 16)
#define STATUS_ENDPRDMASTS (1 << 17)
#define ICLEAR_SOFTRAPICLR (1 << 0)
#define ICLEAR_VLINEICLR (1 << 5)
#define IEN_SOFTRAPEN (1 << 0)
#define TEXCTL_TEXFORMAT_MASK (7 << 0)
#define TEXCTL_TEXFORMAT_TW4 (0 << 0)
#define TEXCTL_TEXFORMAT_TW8 (1 << 0)
#define TEXCTL_TEXFORMAT_TW15 (2 << 0)
#define TEXCTL_TEXFORMAT_TW16 (3 << 0)
#define TEXCTL_TEXFORMAT_TW12 (4 << 0)
#define TEXCTL_PALSEL_MASK (0xf << 4)
#define TEXCTL_TPITCH_SHIFT (16)
#define TEXCTL_TPITCH_MASK (7 << TEXCTL_TPITCH_SHIFT)
#define TEXCTL_TPITCHLIN (1 << 8)
#define TEXCTL_TPITCHEXT_MASK (0x7ff << 9)
#define TEXCTL_NPCEN (1 << 21)
#define TEXCTL_AZEROEXTEND (1 << 23)
#define TEXCTL_DECALCKEY (1 << 24)
#define TEXCTL_TAKEY (1 << 25)
#define TEXCTL_TAMASK (1 << 26)
#define TEXCTL_CLAMPV (1 << 27)
#define TEXCTL_CLAMPU (1 << 28)
#define TEXCTL_TMODULATE (1 << 29)
#define TEXCTL_STRANS (1 << 30)
#define TEXCTL_ITRANS (1 << 31)
#define TEXHEIGHT_TH_MASK (0x3f << 0)
#define TEXHEIGHT_THMASK_SHIFT (18)
#define TEXHEIGHT_THMASK_MASK (0x7ff << TEXHEIGHT_THMASK_SHIFT)
#define TEXWIDTH_TW_MASK (0x3f << 0)
#define TEXWIDTH_TWMASK_SHIFT (18)
#define TEXWIDTH_TWMASK_MASK (0x7ff << TEXWIDTH_TWMASK_SHIFT)
#define TEXTRANS_TCKEY_MASK (0xffff)
#define TEXTRANS_TKMASK_SHIFT (16)
#define TEXTRANS_TKMASK_MASK (0xffff << TEXTRANS_TKMASK_SHIFT)
#define DITHER_565 0
#define DITHER_NONE_565 1
#define DITHER_555 2
#define DITHER_NONE_555 3
/*PCI configuration registers*/
#define OPTION_INTERLEAVE (1 << 12)
enum {
MGA_2064W, /*Millennium*/
MGA_1064SG, /*Mystique*/
MGA_1164SG, /*Mystique 220*/
MGA_2164W, /*Millennium II*/
MGA_G100, /*Productiva G100*/
};
enum {
FIFO_INVALID = (0x00 << 24),
FIFO_WRITE_CTRL_BYTE = (0x01 << 24),
FIFO_WRITE_CTRL_LONG = (0x02 << 24),
FIFO_WRITE_ILOAD_LONG = (0x03 << 24)
};
enum {
DMA_STATE_IDLE = 0,
DMA_STATE_PRI,
DMA_STATE_SEC
};
typedef struct
{
uint32_t addr_type;
uint32_t val;
} fifo_entry_t;
typedef struct mystique_t {
svga_t svga;
rom_t bios_rom;
int type;
mem_mapping_t lfb_mapping, ctrl_mapping,
iload_mapping;
uint8_t int_line, xcurctrl,
xsyspllm, xsysplln, xsyspllp,
xgenioctrl, xgeniodata,
xmulctrl, xgenctrl,
xmiscctrl, xpixclkctrl,
xvrefctrl, ien, dmamod,
dmadatasiz, dirdatasiz,
xcolkeymskl, xcolkeymskh,
xcolkeyl, xcolkeyh,
xcrcbitsel;
uint8_t pci_slot, irq_state, pad, pad0;
uint8_t pci_regs[256], crtcext_regs[6],
xreg_regs[256], dmamap[16];
int vram_size, crtcext_idx, xreg_idx, xzoomctrl;
atomic_int busy, blitter_submit_refcount,
blitter_submit_dma_refcount, blitter_complete_refcount,
endprdmasts_pending, softrap_pending,
fifo_read_idx, fifo_write_idx;
uint32_t vram_mask, vram_mask_w, vram_mask_l,
lfb_base, ctrl_base, iload_base,
ma_latch_old, maccess, mctlwtst, maccess_running,
softrap_pending_val;
atomic_uint status;
atomic_bool softrap_status_read;
uint64_t blitter_time, status_time;
pc_timer_t softrap_pending_timer, wake_timer;
fifo_entry_t fifo[FIFO_SIZE];
thread_t *fifo_thread;
event_t *wake_fifo_thread, *fifo_not_full_event;
struct
{
int m, n, p, s;
} xpixpll[3];
struct
{
uint8_t funcnt : 7, stylelen,
dmamod;
int16_t fxleft, fxright,
xdst;
uint16_t cxleft, cxright,
length;
int xoff, yoff, selline, ydst,
length_cur, iload_rem_count, idump_end_of_line, words,
ta_key, ta_mask, lastpix_r, lastpix_g,
lastpix_b, highv_line, beta, dither, err, k1, k2;
bool pattern[8][16];
uint32_t dwgctrl, dwgctrl_running, bcol, fcol,
pitch, plnwt, ybot, ydstorg,
ytop, texorg, texwidth, texheight,
texctl, textrans, zorg, ydst_lin,
src_addr, z_base, iload_rem_data, highv_data,
fogcol, fogxinc : 24, fogyinc : 24, fogstart : 24,
alphactrl, alphaxinc : 24, alphayinc : 24, alphastart : 24,
texfilter;
uint32_t src[4], ar[7],
dr[16], tmr[9];
uint64_t extended_dr[4];
struct
{
int sdydxl, scanleft, sdxl, sdy,
sdxr;
} sgn;
} dwgreg;
struct
{
uint8_t r, g, b;
} lut[256];
struct
{
uint16_t pos_x, pos_y,
addr;
uint32_t col[3];
} cursor;
struct
{
atomic_int pri_state, sec_state, iload_state, state;
atomic_uint primaddress, primend, secaddress, secend,
pri_header, sec_header,
iload_header;
atomic_uint words_expected;
mutex_t *lock;
} dma;
uint8_t thread_run;
void *i2c, *i2c_ddc, *ddc;
} mystique_t;
static const uint8_t trans_masks[16][16] = {
// clang-format off
{
1, 1, 1, 1,
1, 1, 1, 1,
1, 1, 1, 1,
1, 1, 1, 1
},
{
1, 0, 1, 0,
0, 1, 0, 1,
1, 0, 1, 0,
0, 1, 0, 1
},
{
0, 1, 0, 1,
1, 0, 1, 0,
0, 1, 0, 1,
1, 0, 1, 0
},
{
1, 0, 1, 0,
0, 0, 0, 0,
1, 0, 1, 0,
0, 0, 0, 0
},
{
0, 1, 0, 1,
0, 0, 0, 0,
0, 1, 0, 1,
0, 0, 0, 0
},
{
0, 0, 0, 0,
1, 0, 1, 0,
0, 0, 0, 0,
1, 0, 1, 0
},
{
0, 0, 0, 0,
0, 1, 0, 1,
0, 0, 0, 0,
0, 1, 0, 1
},
{
1, 0, 0, 0,
0, 0, 0, 0,
0, 0, 1, 0,
0, 0, 0, 0
},
{
0, 0, 0, 0,
0, 1, 0, 0,
0, 0, 0, 0,
0, 0, 0, 1
},
{
0, 0, 0, 1,
0, 0, 0, 0,
0, 1, 0, 0,
0, 0, 0, 0
},
{
0, 0, 0, 0,
0, 0, 1, 0,
0, 0, 0, 0,
1, 0, 0, 0
},
{
0, 0, 0, 0,
1, 0, 0, 0,
0, 0, 0, 0,
0, 0, 1, 0
},
{
0, 1, 0, 0,
0, 0, 0, 0,
0, 0, 0, 1,
0, 0, 0, 0
},
{
0, 0, 0, 0,
0, 0, 0, 1,
0, 0, 0, 0,
0, 1, 0, 0
},
{
0, 0, 1, 0,
0, 0, 0, 0,
1, 0, 0, 0,
0, 0, 0, 0
},
{
0, 0, 0, 0,
0, 0, 0, 0,
0, 0, 0, 0,
0, 0, 0, 0
}
// clang-format on
};
static int8_t dither5[256][2][2];
static int8_t dither6[256][2][2];
static double bayer_mat[4][4] =
{
{ 0.0, 8. / 16., 2. / 16., 10. / 16.},
{ 12. / 16., 4. / 16., 14. / 16., 6. / 16.},
{ 3. / 16., 11. / 16., 1. / 16., 9. / 16.},
{ 15. / 16., 7. / 16., 13. / 16., 5. / 16.},
};
static video_timings_t timing_matrox_millennium = { .type = VIDEO_PCI, .write_b = 2, .write_w = 2, .write_l = 1, .read_b = 10, .read_w = 10, .read_l = 10 };
static video_timings_t timing_matrox_mystique = { .type = VIDEO_PCI, .write_b = 4, .write_w = 4, .write_l = 4, .read_b = 10, .read_w = 10, .read_l = 10 };
static void mystique_start_blit(mystique_t *mystique);
static void mystique_update_irqs(mystique_t *mystique);
static void wake_fifo_thread(mystique_t *mystique);
static void wait_fifo_idle(mystique_t *mystique);
static void mystique_queue(mystique_t *mystique, uint32_t addr, uint32_t val, uint32_t type);
static uint8_t mystique_readb_linear(uint32_t addr, void *priv);
static uint16_t mystique_readw_linear(uint32_t addr, void *priv);
static uint32_t mystique_readl_linear(uint32_t addr, void *priv);
static void mystique_writeb_linear(uint32_t addr, uint8_t val, void *priv);
static void mystique_writew_linear(uint32_t addr, uint16_t val, void *priv);
static void mystique_writel_linear(uint32_t addr, uint32_t val, void *priv);
static void mystique_recalc_mapping(mystique_t *mystique);
static int mystique_line_compare(svga_t *svga);
static uint8_t mystique_iload_read_b(uint32_t addr, void *priv);
static uint32_t mystique_iload_read_l(uint32_t addr, void *priv);
static void mystique_iload_write_b(uint32_t addr, uint8_t val, void *priv);
static void mystique_iload_write_l(uint32_t addr, uint32_t val, void *priv);
static uint32_t blit_idump_read(mystique_t *mystique);
static void blit_iload_write(mystique_t *mystique, uint32_t data, int size);
void
mystique_out(uint16_t addr, uint8_t val, void *priv)
{
mystique_t *mystique = (mystique_t *) priv;
svga_t *svga = &mystique->svga;
uint8_t old;
if ((((addr & 0xFFF0) == 0x3D0 || (addr & 0xFFF0) == 0x3B0) && addr < 0x3de) && !(svga->miscout & 1))
addr ^= 0x60;
switch (addr) {
case 0x3c8:
mystique->xreg_idx = val;
fallthrough;
case 0x3c6:
case 0x3c7:
case 0x3c9:
if (mystique->type == MGA_2064W || mystique->type == MGA_2164W) {
tvp3026_ramdac_out(addr, 0, 0, val, svga->ramdac, svga);
return;
}
break;
case 0x3cf:
if ((svga->gdcaddr & 15) == 6 && svga->gdcreg[6] != val) {
svga->gdcreg[svga->gdcaddr & 15] = val;
mystique_recalc_mapping(mystique);
return;
}
break;
case 0x3D4:
svga->crtcreg = val & 0x3f;
return;
case 0x3D5:
if (((svga->crtcreg & 0x3f) < 7) && (svga->crtc[0x11] & 0x80))
return;
if (((svga->crtcreg & 0x3f) == 7) && (svga->crtc[0x11] & 0x80))
val = (svga->crtc[7] & ~0x10) | (val & 0x10);
old = svga->crtc[svga->crtcreg & 0x3f];
svga->crtc[svga->crtcreg & 0x3f] = val;
if (old != val) {
if ((svga->crtcreg & 0x3f) < 0xE || (svga->crtcreg & 0x3f) > 0x10) {
if (((svga->crtcreg & 0x3f) == 0xc) || ((svga->crtcreg & 0x3f) == 0xd)) {
svga->fullchange = 3;
svga->ma_latch = ((svga->crtc[0xc] << 8) | svga->crtc[0xd]) + ((svga->crtc[8] & 0x60) >> 5);
} else {
svga->fullchange = changeframecount;
svga_recalctimings(svga);
}
}
if (svga->crtcreg == 0x11) {
if (!(val & 0x10))
mystique->status &= ~STATUS_VSYNCPEN;
mystique_update_irqs(mystique);
}
}
break;
case 0x3de:
mystique->crtcext_idx = val;
break;
case 0x3df:
if (mystique->crtcext_idx == 1)
svga->dpms = !!(val & 0x30);
old = mystique->crtcext_regs[mystique->crtcext_idx];
if (mystique->crtcext_idx < 6)
mystique->crtcext_regs[mystique->crtcext_idx] = val;
if ((mystique->type >= MGA_1064SG) && (mystique->crtcext_idx == 0) &&
(mystique->crtcext_regs[3] & CRTCX_R3_MGAMODE)) {
svga->rowoffset = svga->crtc[0x13] |
((mystique->crtcext_regs[0] & CRTCX_R0_OFFSET_MASK) << 4);
if (!(mystique->type >= MGA_2164W))
svga->rowoffset <<= 1;
svga->ma_latch = ((mystique->crtcext_regs[0] & CRTCX_R0_STARTADD_MASK) << 16) |
(svga->crtc[0xc] << 8) | svga->crtc[0xd];
if ((mystique->pci_regs[0x41] & (OPTION_INTERLEAVE >> 8))) {
svga->rowoffset <<= 1;
svga->ma_latch <<= 1;
}
if (!(mystique->type >= MGA_2164W))
svga->ma_latch <<= 1;
if (svga->ma_latch != mystique->ma_latch_old) {
if (svga->interlace && svga->oddeven)
svga->maback = (svga->maback - (mystique->ma_latch_old << 2)) +
(svga->ma_latch << 2) + (svga->rowoffset << 1);
else
svga->maback = (svga->maback - (mystique->ma_latch_old << 2)) +
(svga->ma_latch << 2);
mystique->ma_latch_old = svga->ma_latch;
}
}
if (mystique->crtcext_idx == 4) {
if (svga->gdcreg[6] & 0xc) {
/*64k banks*/
if (mystique->type >= MGA_2164W) {
svga->read_bank = val << 16;
svga->write_bank = val << 16;
} else {
svga->read_bank = (val & 0x7f) << 16;
svga->write_bank = (val & 0x7f) << 16;
}
} else {
/*128k banks*/
if (mystique->type >= MGA_2164W) {
svga->read_bank = (val & 0xfe) << 16;
svga->write_bank = (val & 0xfe) << 16;
} else {
svga->read_bank = (val & 0x7e) << 16;
svga->write_bank = (val & 0x7e) << 16;
}
}
}
if (!((mystique->type >= MGA_1064SG) && (mystique->crtcext_idx == 0) &&
(mystique->crtcext_regs[3] & CRTCX_R3_MGAMODE)))
svga_recalctimings(svga);
break;
default:
break;
}
svga_out(addr, val, svga);
}
uint8_t
mystique_in(uint16_t addr, void *priv)
{
mystique_t *mystique = (mystique_t *) priv;
svga_t *svga = &mystique->svga;
uint8_t temp = 0xff;
if ((((addr & 0xFFF0) == 0x3D0 || (addr & 0xFFF0) == 0x3B0) && addr < 0x3de) && !(svga->miscout & 1))
addr ^= 0x60;
switch (addr) {
case 0x3c1:
if (svga->attraddr >= 0x15)
temp = 0;
else
temp = svga->attrregs[svga->attraddr];
break;
case 0x3c6:
case 0x3c7:
case 0x3c8:
case 0x3c9:
if (mystique->type == MGA_2064W || mystique->type == MGA_2164W)
temp = tvp3026_ramdac_in(addr, 0, 0, svga->ramdac, svga);
else
temp = svga_in(addr, svga);
break;
case 0x3D4:
temp = svga->crtcreg;
break;
case 0x3D5:
if ((svga->crtcreg >= 0x19 && svga->crtcreg <= 0x21) || svga->crtcreg == 0x23 || svga->crtcreg == 0x25 || svga->crtcreg >= 0x27)
temp = 0;
else
temp = svga->crtc[svga->crtcreg & 0x3f];
break;
case 0x3de:
temp = mystique->crtcext_idx;
break;
case 0x3df:
if (mystique->crtcext_idx < 6)
temp = mystique->crtcext_regs[mystique->crtcext_idx];
break;
default:
temp = svga_in(addr, svga);
break;
}
return temp;
}
static int
mystique_line_compare(svga_t *svga)
{
mystique_t *mystique = (mystique_t *) svga->priv;
mystique->status |= STATUS_VLINEPEN;
mystique_update_irqs(mystique);
return 0;
}
static void
mystique_vblank_start(svga_t *svga)
{
mystique_t *mystique = (mystique_t *) svga->priv;
if (mystique->crtcext_regs[3] & CRTCX_R3_MGAMODE) {
svga->ma_latch = ((mystique->crtcext_regs[0] & CRTCX_R0_STARTADD_MASK) << 16) | (svga->crtc[0xc] << 8) | svga->crtc[0xd];
if (mystique->pci_regs[0x41] & (OPTION_INTERLEAVE >> 8))
svga->ma_latch <<= 1;
}
}
static void
mystique_vsync_callback(svga_t *svga)
{
mystique_t *mystique = (mystique_t *) svga->priv;
if (svga->crtc[0x11] & 0x10) {
mystique->status |= STATUS_VSYNCPEN;
mystique_update_irqs(mystique);
}
}
static float
mystique_getclock(int clock, void *priv)
{
const mystique_t *mystique = (mystique_t *) priv;
if (clock == 0)
return 25175000.0;
if (clock == 1)
return 28322000.0;
int m = mystique->xpixpll[2].m;
int n = mystique->xpixpll[2].n;
int pl = mystique->xpixpll[2].p;
float fvco = 14318181.0 * (n + 1) / (m + 1);
float fo = fvco / (pl + 1);
return fo;
}
void
mystique_recalctimings(svga_t *svga)
{
mystique_t *mystique = (mystique_t *) svga->priv;
int clk_sel = (svga->miscout >> 2) & 3;
svga->clock = (cpuclock * (float) (1ULL << 32)) / svga->getclock(clk_sel & 3, svga->clock_gen);
if (mystique->crtcext_regs[1] & CRTCX_R1_HTOTAL8)
svga->htotal |= 0x100;
svga->hblankstart = (((mystique->crtcext_regs[1] & 0x02) >> 2) << 8) + svga->crtc[2];
if (mystique->crtcext_regs[2] & CRTCX_R2_VTOTAL10)
svga->vtotal |= 0x400;
if (mystique->crtcext_regs[2] & CRTCX_R2_VTOTAL11)
svga->vtotal |= 0x800;
if (mystique->crtcext_regs[2] & CRTCX_R2_VDISPEND10)
svga->dispend |= 0x400;
if (mystique->crtcext_regs[2] & CRTCX_R2_VBLKSTR10)
svga->vblankstart |= 0x400;
if (mystique->crtcext_regs[2] & CRTCX_R2_VBLKSTR11)
svga->vblankstart |= 0x800;
if (mystique->crtcext_regs[2] & CRTCX_R2_VSYNCSTR10)
svga->vsyncstart |= 0x400;
if (mystique->crtcext_regs[2] & CRTCX_R2_VSYNCSTR11)
svga->vsyncstart |= 0x800;
if (mystique->crtcext_regs[2] & CRTCX_R2_LINECOMP10)
svga->split |= 0x400;
if (mystique->type == MGA_2064W || mystique->type == MGA_2164W) {
tvp3026_recalctimings(svga->ramdac, svga);
svga->interlace |= !!(mystique->crtcext_regs[0] & 0x80);
} else
svga->interlace = !!(mystique->crtcext_regs[0] & 0x80);
if (mystique->crtcext_regs[3] & CRTCX_R3_MGAMODE) {
svga->lowres = 0;
svga->char_width = 8;
svga->hdisp = (svga->crtc[1] + 1) << 3;
svga->hdisp_time = svga->hdisp;
svga->rowoffset = svga->crtc[0x13] | ((mystique->crtcext_regs[0] & CRTCX_R0_OFFSET_MASK) << 4);
svga->dots_per_clock = 8;
svga->hblank_end_val = (svga->crtc[3] & 0x1f) | (((svga->crtc[5] & 0x80) >> 7) << 5) |
(((mystique->crtcext_regs[1] & 0x40) >> 6) << 6);
svga->hblank_end_mask = 0x0000007f;
if (mystique->type != MGA_2164W && mystique->type != MGA_2064W)
svga->lut_map = !!(mystique->xmiscctrl & XMISCCTRL_RAMCS);
if (mystique->type >= MGA_1064SG)
svga->ma_latch = ((mystique->crtcext_regs[0] & CRTCX_R0_STARTADD_MASK) << 16) | (svga->crtc[0xc] << 8) | svga->crtc[0xd];
if ((mystique->pci_regs[0x41] & (OPTION_INTERLEAVE >> 8))) {
svga->rowoffset <<= 1;
if (mystique->type >= MGA_1064SG)
svga->ma_latch <<= 1;
}
if (mystique->type >= MGA_1064SG) {
/*Mystique and later, unlike most SVGA cards, allows display start to take
effect mid-screen*/
if (!(mystique->type >= MGA_2164W))
svga->ma_latch <<= 1;
/* Only change maback so the new display start will take effect on the next
horizontal retrace. */
if (svga->ma_latch != mystique->ma_latch_old) {
if (svga->interlace && svga->oddeven)
svga->maback = (svga->maback - (mystique->ma_latch_old << 2)) +
(svga->ma_latch << 2) + (svga->rowoffset << 1);
else
svga->maback = (svga->maback - (mystique->ma_latch_old << 2)) +
(svga->ma_latch << 2);
mystique->ma_latch_old = svga->ma_latch;
}
if (!(mystique->type >= MGA_2164W))
svga->rowoffset <<= 1;
if (mystique->type != MGA_2164W) {
switch (mystique->xmulctrl & XMULCTRL_DEPTH_MASK) {
case XMULCTRL_DEPTH_8:
case XMULCTRL_DEPTH_2G8V16:
svga->render = svga_render_8bpp_highres;
svga->bpp = 8;
break;
case XMULCTRL_DEPTH_15:
case XMULCTRL_DEPTH_G16V16:
svga->render = svga_render_15bpp_highres;
svga->bpp = 15;
break;
case XMULCTRL_DEPTH_16:
svga->render = svga_render_16bpp_highres;
svga->bpp = 16;
break;
case XMULCTRL_DEPTH_24:
svga->render = svga_render_24bpp_highres;
svga->bpp = 24;
break;
case XMULCTRL_DEPTH_32:
case XMULCTRL_DEPTH_32_OVERLAYED:
svga->render = svga_render_32bpp_highres;
svga->bpp = 32;
break;
default:
break;
}
} else {
switch (svga->bpp) {
case 8:
svga->render = svga_render_8bpp_highres;
break;
case 15:
svga->render = svga_render_15bpp_highres;
break;
case 16:
svga->render = svga_render_16bpp_highres;
break;
case 24:
svga->render = svga_render_24bpp_highres;
break;
case 32:
svga->render = svga_render_32bpp_highres;
break;
}
}
} else {
switch (svga->bpp) {
case 8:
svga->render = svga_render_8bpp_highres;
break;
case 15:
svga->render = svga_render_15bpp_highres;
break;
case 16:
svga->render = svga_render_16bpp_highres;
break;
case 24:
svga->render = svga_render_24bpp_highres;
break;
case 32:
svga->render = svga_render_32bpp_highres;
break;
}
}
svga->packed_chain4 = 1;
svga->line_compare = mystique_line_compare;
if (mystique->type < MGA_1064SG)
svga->vblank_start = mystique_vblank_start;
} else {
svga->packed_chain4 = 0;
svga->line_compare = NULL;
svga->lut_map = 0;
if (mystique->type >= MGA_1064SG)
svga->bpp = 8;
else
svga->vblank_start = NULL;
}
svga->fb_only = svga->packed_chain4;
svga->disable_blink = (svga->bpp > 4);
video_force_resize_set_monitor(1, svga->monitor_index);
#if 0
pclog("PackedChain4=%d, chain4=%x, fast=%x, bit6 attrreg10=%02x, bits 5-6 gdcreg5=%02x, extmode=%02x.\n", svga->packed_chain4, svga->chain4, svga->fast, svga->attrregs[0x10] & 0x40, svga->gdcreg[5] & 0x60, mystique->pci_regs[0x41] & 1, mystique->crtcext_regs[3] & CRTCX_R3_MGAMODE);
#endif
}
static void
mystique_recalc_mapping(mystique_t *mystique)
{
svga_t *svga = &mystique->svga;
io_removehandler(0x03c0, 0x0020, mystique_in, NULL, NULL, mystique_out, NULL, NULL, mystique);
if ((mystique->pci_regs[PCI_REG_COMMAND] & PCI_COMMAND_IO) && (mystique->pci_regs[0x41] & 1))
io_sethandler(0x03c0, 0x0020, mystique_in, NULL, NULL, mystique_out, NULL, NULL, mystique);
if (!(mystique->pci_regs[PCI_REG_COMMAND] & PCI_COMMAND_MEM)) {
mem_mapping_disable(&svga->mapping);
mem_mapping_disable(&mystique->ctrl_mapping);
mem_mapping_disable(&mystique->lfb_mapping);
mem_mapping_disable(&mystique->iload_mapping);
return;
}
if (mystique->ctrl_base)
mem_mapping_set_addr(&mystique->ctrl_mapping, mystique->ctrl_base, 0x4000);
else
mem_mapping_disable(&mystique->ctrl_mapping);
if (mystique->lfb_base)
mem_mapping_set_addr(&mystique->lfb_mapping, mystique->lfb_base, (mystique->type >= MGA_2164W) ? 0x1000000 : 0x800000);
else
mem_mapping_disable(&mystique->lfb_mapping);
if (mystique->iload_base)
mem_mapping_set_addr(&mystique->iload_mapping, mystique->iload_base, 0x800000);
else
mem_mapping_disable(&mystique->iload_mapping);
if (mystique->pci_regs[0x41] & 1) {
switch (svga->gdcreg[6] & 0x0C) {
case 0x0: /*128k at A0000*/
mem_mapping_set_addr(&svga->mapping, 0xa0000, 0x20000);
svga->banked_mask = 0xffff;
break;
case 0x4: /*64k at A0000*/
mem_mapping_set_addr(&svga->mapping, 0xa0000, 0x10000);
svga->banked_mask = 0xffff;
break;
case 0x8: /*32k at B0000*/
mem_mapping_set_addr(&svga->mapping, 0xb0000, 0x08000);
svga->banked_mask = 0x7fff;
break;
case 0xC: /*32k at B8000*/
mem_mapping_set_addr(&svga->mapping, 0xb8000, 0x08000);
svga->banked_mask = 0x7fff;
break;
default:
break;
}
if (svga->gdcreg[6] & 0xc) {
/*64k banks*/
svga->read_bank = (mystique->crtcext_regs[4] & 0x7f) << 16;
svga->write_bank = (mystique->crtcext_regs[4] & 0x7f) << 16;
} else {
/*128k banks*/
svga->read_bank = (mystique->crtcext_regs[4] & 0x7e) << 16;
svga->write_bank = (mystique->crtcext_regs[4] & 0x7e) << 16;
}
} else
mem_mapping_disable(&svga->mapping);
}
static void
mystique_update_irqs(mystique_t *mystique)
{
const svga_t *svga = &mystique->svga;
int irq = 0;
if ((mystique->status & mystique->ien) & STATUS_SOFTRAPEN)
irq = 1;
if ((mystique->status & mystique->ien) & STATUS_VLINEPEN)
irq = 1;
if ((mystique->status & STATUS_VSYNCPEN) && (svga->crtc[0x11] & 0x30) == 0x10)
irq = 1;
if (irq)
pci_set_irq(mystique->pci_slot, PCI_INTA, &mystique->irq_state);
else
pci_clear_irq(mystique->pci_slot, PCI_INTA, &mystique->irq_state);
}
#define READ8(addr, var) \
switch ((addr) &3) { \
case 0: \
ret = (var) &0xff; \
break; \
case 1: \
ret = ((var) >> 8) & 0xff; \
break; \
case 2: \
ret = ((var) >> 16) & 0xff; \
break; \
case 3: \
ret = ((var) >> 24) & 0xff; \
break; \
}
#define WRITE8(addr, var, val) \
switch ((addr) &3) { \
case 0: \
var = (var & 0xffffff00) | (val); \
break; \
case 1: \
var = (var & 0xffff00ff) | ((val) << 8); \
break; \
case 2: \
var = (var & 0xff00ffff) | ((val) << 16); \
break; \
case 3: \
var = (var & 0x00ffffff) | ((val) << 24); \
break; \
}
static uint8_t
mystique_read_xreg(mystique_t *mystique, int reg)
{
uint8_t ret = 0xff;
switch (reg) {
case XREG_XCURADDL:
ret = mystique->cursor.addr & 0xff;
break;
case XREG_XCURADDH:
ret = mystique->cursor.addr >> 8;
break;
case XREG_XCURCTRL:
ret = mystique->xcurctrl;
break;
case XREG_XCURCOL0R:
case XREG_XCURCOL0G:
case XREG_XCURCOL0B:
READ8(reg, mystique->cursor.col[0]);
break;
case XREG_XCURCOL1R:
case XREG_XCURCOL1G:
case XREG_XCURCOL1B:
READ8(reg, mystique->cursor.col[1]);
break;
case XREG_XCURCOL2R:
case XREG_XCURCOL2G:
case XREG_XCURCOL2B:
READ8(reg, mystique->cursor.col[2]);
break;
case XREG_XMULCTRL:
ret = mystique->xmulctrl;
break;
case XREG_XMISCCTRL:
ret = mystique->xmiscctrl;
break;
case XREG_XGENCTRL:
ret = mystique->xgenctrl;
break;
case XREG_XVREFCTRL:
ret = mystique->xvrefctrl;
break;
case XREG_XGENIOCTRL:
ret = mystique->xgenioctrl;
break;
case XREG_XGENIODATA:
ret = mystique->xgeniodata & 0xf0;
if (i2c_gpio_get_scl(mystique->i2c_ddc))
ret |= 0x08;
if (i2c_gpio_get_scl(mystique->i2c))
ret |= 0x04;
if (i2c_gpio_get_sda(mystique->i2c_ddc))
ret |= 0x02;
if (i2c_gpio_get_sda(mystique->i2c))
ret |= 0x01;
break;
case XREG_XSYSPLLM:
ret = mystique->xsyspllm;
break;
case XREG_XSYSPLLN:
ret = mystique->xsysplln;
break;
case XREG_XSYSPLLP:
ret = mystique->xsyspllp;
break;
case XREG_XZOOMCTRL:
ret = mystique->xzoomctrl;
break;
case XREG_XSENSETEST:
ret = 0;
if (mystique->svga.vgapal[0].b < 0x80)
ret |= 1;
if (mystique->svga.vgapal[0].g < 0x80)
ret |= 2;
if (mystique->svga.vgapal[0].r < 0x80)
ret |= 4;
break;
case XREG_XCRCREML: /*CRC not implemented*/
ret = 0;
break;
case XREG_XCRCREMH:
ret = 0;
break;
case XREG_XCRCBITSEL:
ret = mystique->xcrcbitsel;
break;
case XREG_XCOLKEYMSKL:
ret = mystique->xcolkeymskl;
break;
case XREG_XCOLKEYMSKH:
ret = mystique->xcolkeymskh;
break;
case XREG_XCOLKEYL:
ret = mystique->xcolkeyl;
break;
case XREG_XCOLKEYH:
ret = mystique->xcolkeyh;
break;
case XREG_XPIXCLKCTRL:
ret = mystique->xpixclkctrl;
break;
case XREG_XSYSPLLSTAT:
ret = XSYSPLLSTAT_SYSLOCK;
break;
case XREG_XPIXPLLSTAT:
ret = XPIXPLLSTAT_SYSLOCK;
break;
case XREG_XPIXPLLCM:
ret = mystique->xpixpll[2].m;
break;
case XREG_XPIXPLLCN:
ret = mystique->xpixpll[2].n;
break;
case XREG_XPIXPLLCP:
ret = mystique->xpixpll[2].p | (mystique->xpixpll[2].s << 3);
break;
case 0x00:
case 0x20:
case 0x3f:
ret = 0xff;
break;
default:
if (reg >= 0x50)
ret = 0xff;
break;
}
return ret;
}
static void
mystique_write_xreg(mystique_t *mystique, int reg, uint8_t val)
{
svga_t *svga = &mystique->svga;
switch (reg) {
case XREG_XCURADDL:
mystique->cursor.addr = (mystique->cursor.addr & 0x1f00) | val;
svga->hwcursor.addr = mystique->cursor.addr << 10;
break;
case XREG_XCURADDH:
mystique->cursor.addr = (mystique->cursor.addr & 0x00ff) | ((val & 0x1f) << 8);
svga->hwcursor.addr = mystique->cursor.addr << 10;
break;
case XREG_XCURCTRL:
mystique->xcurctrl = val;
svga->hwcursor.ena = (val & 3) ? 1 : 0;
break;
case XREG_XCURCOL0R:
case XREG_XCURCOL0G:
case XREG_XCURCOL0B:
WRITE8(reg, mystique->cursor.col[0], val);
break;
case XREG_XCURCOL1R:
case XREG_XCURCOL1G:
case XREG_XCURCOL1B:
WRITE8(reg, mystique->cursor.col[1], val);
break;
case XREG_XCURCOL2R:
case XREG_XCURCOL2G:
case XREG_XCURCOL2B:
WRITE8(reg, mystique->cursor.col[2], val);
break;
case XREG_XMULCTRL:
mystique->xmulctrl = val;
break;
case XREG_XMISCCTRL:
mystique->xmiscctrl = val;
svga_set_ramdac_type(svga, (val & XMISCCTRL_VGA8DAC) ? RAMDAC_8BIT : RAMDAC_6BIT);
if (mystique->crtcext_regs[3] & CRTCX_R3_MGAMODE)
svga->lut_map = !!(mystique->xmiscctrl & XMISCCTRL_RAMCS);
break;
case XREG_XGENCTRL:
mystique->xgenctrl = val;
break;
case XREG_XVREFCTRL:
mystique->xvrefctrl = val;
break;
case XREG_XGENIOCTRL:
mystique->xgenioctrl = val;
i2c_gpio_set(mystique->i2c_ddc, !(mystique->xgenioctrl & 0x08) || (mystique->xgeniodata & 0x08), !(mystique->xgenioctrl & 0x02) || (mystique->xgeniodata & 0x02));
i2c_gpio_set(mystique->i2c, !(mystique->xgenioctrl & 0x04) || (mystique->xgeniodata & 0x04), !(mystique->xgenioctrl & 0x01) || (mystique->xgeniodata & 0x01));
break;
case XREG_XGENIODATA:
mystique->xgeniodata = val;
break;
case XREG_XSYSPLLM:
mystique->xsyspllm = val;
break;
case XREG_XSYSPLLN:
mystique->xsysplln = val;
break;
case XREG_XSYSPLLP:
mystique->xsyspllp = val;
break;
case XREG_XZOOMCTRL:
mystique->xzoomctrl = val & 3;
break;
case XREG_XSENSETEST:
break;
case XREG_XCRCREML: /*CRC not implemented*/
break;
case XREG_XCRCREMH:
break;
case XREG_XCRCBITSEL:
mystique->xcrcbitsel = val & 0x1f;
break;
case XREG_XCOLKEYMSKL:
mystique->xcolkeymskl = val;
break;
case XREG_XCOLKEYMSKH:
mystique->xcolkeymskh = val;
break;
case XREG_XCOLKEYL:
mystique->xcolkeyl = val;
break;
case XREG_XCOLKEYH:
mystique->xcolkeyh = val;
break;
case XREG_XSYSPLLSTAT:
break;
case XREG_XPIXPLLSTAT:
break;
case XREG_XPIXCLKCTRL:
mystique->xpixclkctrl = val;
break;
case XREG_XPIXPLLCM:
mystique->xpixpll[2].m = val;
break;
case XREG_XPIXPLLCN:
mystique->xpixpll[2].n = val;
break;
case XREG_XPIXPLLCP:
mystique->xpixpll[2].p = val & 7;
mystique->xpixpll[2].s = (val >> 3) & 3;
break;
case 0x00:
case 0x01:
case 0x02:
case 0x03:
case 0x07:
case 0x0b:
case 0x0f:
case 0x13:
case 0x14:
case 0x15:
case 0x16:
case 0x17:
case 0x1b:
case 0x1c:
case 0x20:
case 0x39:
case 0x3b:
case 0x3f:
case 0x47:
case 0x4b:
break;
default:
break;
}
}
static uint8_t
mystique_ctrl_read_b(uint32_t addr, void *priv)
{
mystique_t *mystique = (mystique_t *) priv;
svga_t *svga = &mystique->svga;
uint8_t ret = 0xff;
int fifocount;
uint8_t addr_0x0f = 0;
uint16_t addr_0x03 = 0;
int rs2 = 0;
int rs3 = 0;
if ((mystique->type == MGA_2064W || mystique->type == MGA_2164W) && (addr & 0x3e00) == 0x3c00) {
/*RAMDAC*/
addr_0x0f = addr & 0x0f;
if ((addr_0x0f & 3) == 0)
addr_0x03 = 0x3c8;
else if ((addr_0x0f & 3) == 1)
addr_0x03 = 0x3c9;
else if ((addr_0x0f & 3) == 2)
addr_0x03 = 0x3c6;
else if ((addr_0x0f & 3) == 3)
addr_0x03 = 0x3c7;
if ((addr_0x0f >= 0x04) && (addr_0x0f <= 0x07)) {
rs2 = 1;
rs3 = 0;
} else if ((addr_0x0f >= 0x08) && (addr_0x0f <= 0x0b)) {
rs2 = 0;
rs3 = 1;
} else if ((addr_0x0f >= 0x0c) && (addr_0x0f <= 0x0f)) {
rs2 = 1;
rs3 = 1;
}
ret = tvp3026_ramdac_in(addr_0x03, rs2, rs3, svga->ramdac, svga);
} else
switch (addr & 0x3fff) {
case REG_FIFOSTATUS:
fifocount = FIFO_SIZE - FIFO_ENTRIES;
if (fifocount > (mystique->type <= MGA_1064SG ? 32 : 64))
fifocount = (mystique->type <= MGA_1064SG ? 32 : 64);
ret = fifocount;
break;
case REG_FIFOSTATUS + 1:
if (FIFO_EMPTY)
ret |= 2;
else if (FIFO_ENTRIES >= (mystique->type <= MGA_1064SG ? 32 : 64))
ret |= 1;
break;
case REG_FIFOSTATUS + 2:
case REG_FIFOSTATUS + 3:
ret = 0;
break;
case REG_STATUS:
ret = mystique->status & 0xff;
if (svga->cgastat & 8)
ret |= REG_STATUS_VSYNCSTS;
if (ret & 1)
mystique->softrap_status_read = 1;
if (mystique->softrap_status_read == 0 && !(ret & 1)) {
mystique->softrap_status_read = 1;
ret |= 1;
}
break;
case REG_STATUS + 1:
ret = (mystique->status >> 8) & 0xff;
break;
case REG_STATUS + 2:
ret = (mystique->status >> 16) & 0xff;
if (mystique->busy || ((mystique->blitter_submit_refcount + mystique->blitter_submit_dma_refcount) != mystique->blitter_complete_refcount) || !FIFO_EMPTY
|| mystique->dma.state != DMA_STATE_IDLE || mystique->softrap_pending || mystique->endprdmasts_pending)
ret |= (STATUS_DWGENGSTS >> 16);
break;
case REG_STATUS + 3:
ret = (mystique->status >> 24) & 0xff;
break;
case REG_IEN:
ret = mystique->ien & 0x65;
break;
case REG_IEN + 1:
case REG_IEN + 2:
case REG_IEN + 3:
ret = 0;
break;
case REG_OPMODE:
ret = mystique->dmamod << 2;
break;
case REG_OPMODE + 1:
ret = mystique->dmadatasiz;
break;
case REG_OPMODE + 2:
ret = mystique->dirdatasiz;
break;
case REG_OPMODE + 3:
ret = 0;
break;
case REG_PRIMADDRESS:
case REG_PRIMADDRESS + 1:
case REG_PRIMADDRESS + 2:
case REG_PRIMADDRESS + 3:
READ8(addr, mystique->dma.primaddress);
break;
case REG_PRIMEND:
case REG_PRIMEND + 1:
case REG_PRIMEND + 2:
case REG_PRIMEND + 3:
READ8(addr, mystique->dma.primend);
break;
case REG_SECADDRESS:
case REG_SECADDRESS + 1:
case REG_SECADDRESS + 2:
case REG_SECADDRESS + 3:
READ8(addr, mystique->dma.secaddress);
break;
case REG_VCOUNT:
case REG_VCOUNT + 1:
case REG_VCOUNT + 2:
case REG_VCOUNT + 3:
READ8(addr, svga->vc);
break;
case REG_ATTR_IDX:
ret = svga_in(0x3c0, svga);
break;
case REG_ATTR_DATA:
ret = svga_in(0x3c1, svga);
break;
case REG_INSTS0:
ret = svga_in(0x3c2, svga);
break;
case REG_SEQ_IDX:
ret = svga_in(0x3c4, svga);
break;
case REG_SEQ_DATA:
ret = svga_in(0x3c5, svga);
break;
case REG_MISCREAD:
ret = svga_in(0x3cc, svga);
break;
case REG_GCTL_IDX:
ret = mystique_in(0x3ce, mystique);
break;
case REG_GCTL_DATA:
ret = mystique_in(0x3cf, mystique);
break;
case REG_CRTC_IDX:
ret = mystique_in(0x3d4, mystique);
break;
case REG_CRTC_DATA:
ret = mystique_in(0x3d5, mystique);
break;
case REG_INSTS1:
ret = mystique_in(0x3da, mystique);
break;
case REG_CRTCEXT_IDX:
ret = mystique_in(0x3de, mystique);
break;
case REG_CRTCEXT_DATA:
ret = mystique_in(0x3df, mystique);
break;
case REG_PALWTADD:
ret = svga_in(0x3c8, svga);
break;
case REG_PALDATA:
ret = svga_in(0x3c9, svga);
break;
case REG_PIXRDMSK:
ret = svga_in(0x3c6, svga);
break;
case REG_PALRDADD:
ret = svga_in(0x3c7, svga);
break;
case REG_X_DATAREG:
ret = mystique_read_xreg(mystique, mystique->xreg_idx);
break;
case 0x1c40:
case 0x1c41:
case 0x1c42:
case 0x1c43:
case 0x1d44:
case 0x1d45:
case 0x1d46:
case 0x1d47:
case 0x1e50:
case 0x1e51:
case 0x1e52:
case 0x1e53:
case REG_ICLEAR:
case REG_ICLEAR + 1:
case REG_ICLEAR + 2:
case REG_ICLEAR + 3:
case 0x2c30:
case 0x2c31:
case 0x2c32:
case 0x2c33:
case 0x3e08:
break;
case 0x3c08:
case 0x3c09:
case 0x3c0b:
break;
default:
if ((addr & 0x3fff) >= 0x2c00 && (addr & 0x3fff) < 0x2c40)
break;
if ((addr & 0x3fff) >= 0x3e00)
break;
break;
}
return ret;
}
static void
mystique_accel_ctrl_write_b(uint32_t addr, uint8_t val, void *priv)
{
mystique_t *mystique = (mystique_t *) priv;
int start_blit = 0;
if ((addr & 0x300) == 0x100) {
addr &= ~0x100;
start_blit = 1;
}
switch (addr & 0x3fff) {
case REG_MACCESS:
case REG_MACCESS + 1:
case REG_MACCESS + 2:
case REG_MACCESS + 3:
WRITE8(addr, mystique->maccess, val);
mystique->dwgreg.dither = mystique->maccess >> 30;
if (mystique->type < MGA_2164W)
mystique->maccess &= ~MACCESS_ZWIDTH;
else
mystique->dwgreg.z_base = mystique->dwgreg.ydstorg * ((mystique->maccess & MACCESS_ZWIDTH) ? 4 : 2) + mystique->dwgreg.zorg;
break;
case REG_MCTLWTST:
case REG_MCTLWTST + 1:
case REG_MCTLWTST + 2:
case REG_MCTLWTST + 3:
WRITE8(addr, mystique->mctlwtst, val);
break;
case REG_PAT0:
case REG_PAT0 + 1:
case REG_PAT0 + 2:
case REG_PAT0 + 3:
case REG_PAT1:
case REG_PAT1 + 1:
case REG_PAT1 + 2:
case REG_PAT1 + 3:
for (uint8_t x = 0; x < 8; x++)
mystique->dwgreg.pattern[addr & 7][x] = mystique->dwgreg.pattern[addr & 7][x + 8] = val & (1 << (7 - x));
break;
case REG_XYSTRT:
case REG_XYSTRT + 1:
WRITE8(addr & 1, mystique->dwgreg.ar[5], val);
if (mystique->dwgreg.ar[5] & 0x8000)
mystique->dwgreg.ar[5] |= 0xffff8000;
else
mystique->dwgreg.ar[5] &= ~0xffff8000;
WRITE8(addr & 1, mystique->dwgreg.xdst, val);
break;
case REG_XYSTRT + 2:
case REG_XYSTRT + 3:
WRITE8(addr & 1, mystique->dwgreg.ar[6], val);
if (mystique->dwgreg.ar[6] & 0x8000)
mystique->dwgreg.ar[6] |= 0xffff8000;
else
mystique->dwgreg.ar[6] &= ~0xffff8000;
WRITE8(addr & 1, mystique->dwgreg.ydst, val);
mystique->dwgreg.ydst_lin = ((int32_t) (int16_t) mystique->dwgreg.ydst * (mystique->dwgreg.pitch & PITCH_MASK)) + mystique->dwgreg.ydstorg;
break;
case REG_XYEND:
case REG_XYEND + 1:
WRITE8(addr & 1, mystique->dwgreg.ar[0], val);
if (mystique->dwgreg.ar[0] & 0x8000)
mystique->dwgreg.ar[0] |= 0xffff8000;
else
mystique->dwgreg.ar[0] &= ~0xffff8000;
break;
case REG_XYEND + 2:
case REG_XYEND + 3:
WRITE8(addr & 1, mystique->dwgreg.ar[2], val);
if (mystique->dwgreg.ar[2] & 0x8000)
mystique->dwgreg.ar[2] |= 0xffff8000;
else
mystique->dwgreg.ar[2] &= ~0xffff8000;
break;
case REG_SGN:
mystique->dwgreg.sgn.sdydxl = val & SGN_SDYDXL;
mystique->dwgreg.sgn.scanleft = val & SGN_SCANLEFT;
mystique->dwgreg.sgn.sdxl = val & SGN_SDXL;
mystique->dwgreg.sgn.sdy = val & SGN_SDY;
mystique->dwgreg.sgn.sdxr = val & SGN_SDXR;
break;
case REG_SGN + 1:
case REG_SGN + 2:
case REG_SGN + 3:
break;
case REG_LEN:
case REG_LEN + 1:
WRITE8(addr, mystique->dwgreg.length, val);
break;
case REG_LEN + 2:
break;
case REG_LEN + 3:
mystique->dwgreg.beta = val >> 4;
if (!mystique->dwgreg.beta)
mystique->dwgreg.beta = 16;
break;
case REG_CXBNDRY:
case REG_CXBNDRY + 1:
WRITE8(addr, mystique->dwgreg.cxleft, val);
break;
case REG_CXBNDRY + 2:
case REG_CXBNDRY + 3:
WRITE8(addr & 1, mystique->dwgreg.cxright, val);
break;
case REG_FXBNDRY:
case REG_FXBNDRY + 1:
WRITE8(addr, mystique->dwgreg.fxleft, val);
break;
case REG_FXBNDRY + 2:
case REG_FXBNDRY + 3:
WRITE8(addr & 1, mystique->dwgreg.fxright, val);
break;
case REG_YDSTLEN:
case REG_YDSTLEN + 1:
WRITE8(addr, mystique->dwgreg.length, val);
#if 0
pclog("Write YDSTLEN+%i %i\n", addr&1, mystique->dwgreg.length);
#endif
break;
case REG_YDSTLEN + 2:
mystique->dwgreg.ydst = (mystique->dwgreg.ydst & ~0xff) | val;
if (mystique->dwgreg.pitch & PITCH_YLIN)
mystique->dwgreg.ydst_lin = (mystique->dwgreg.ydst << 5) + mystique->dwgreg.ydstorg;
else {
mystique->dwgreg.ydst_lin = ((int32_t) (int16_t) mystique->dwgreg.ydst * (mystique->dwgreg.pitch & PITCH_MASK)) + mystique->dwgreg.ydstorg;
mystique->dwgreg.selline = val & 7;
}
break;
case REG_YDSTLEN + 3:
mystique->dwgreg.ydst = (mystique->dwgreg.ydst & 0xff) | (((int32_t) (int8_t) val) << 8);
if (mystique->dwgreg.pitch & PITCH_YLIN)
mystique->dwgreg.ydst_lin = (mystique->dwgreg.ydst << 5) + mystique->dwgreg.ydstorg;
else
mystique->dwgreg.ydst_lin = ((int32_t) (int16_t) mystique->dwgreg.ydst * (mystique->dwgreg.pitch & PITCH_MASK)) + mystique->dwgreg.ydstorg;
break;
case REG_XDST:
case REG_XDST + 1:
WRITE8(addr & 1, mystique->dwgreg.xdst, val);
break;
case REG_XDST + 2:
case REG_XDST + 3:
break;
case REG_YDSTORG:
case REG_YDSTORG + 1:
case REG_YDSTORG + 2:
case REG_YDSTORG + 3:
WRITE8(addr, mystique->dwgreg.ydstorg, val);
mystique->dwgreg.z_base = mystique->dwgreg.ydstorg * ((mystique->maccess & MACCESS_ZWIDTH) ? 4 : 2) + mystique->dwgreg.zorg;
break;
case REG_YTOP:
case REG_YTOP + 1:
case REG_YTOP + 2:
case REG_YTOP + 3:
WRITE8(addr, mystique->dwgreg.ytop, val);
break;
case REG_YBOT:
case REG_YBOT + 1:
case REG_YBOT + 2:
case REG_YBOT + 3:
WRITE8(addr, mystique->dwgreg.ybot, val);
break;
case REG_CXLEFT:
case REG_CXLEFT + 1:
WRITE8(addr, mystique->dwgreg.cxleft, val);
break;
case REG_CXLEFT + 2:
case REG_CXLEFT + 3:
break;
case REG_CXRIGHT:
case REG_CXRIGHT + 1:
WRITE8(addr, mystique->dwgreg.cxright, val);
break;
case REG_CXRIGHT + 2:
case REG_CXRIGHT + 3:
break;
case REG_FXLEFT:
case REG_FXLEFT + 1:
WRITE8(addr, mystique->dwgreg.fxleft, val);
break;
case REG_FXLEFT + 2:
case REG_FXLEFT + 3:
break;
case REG_FXRIGHT:
case REG_FXRIGHT + 1:
WRITE8(addr, mystique->dwgreg.fxright, val);
break;
case REG_FXRIGHT + 2:
case REG_FXRIGHT + 3:
break;
case REG_SECADDRESS:
case REG_SECADDRESS + 1:
case REG_SECADDRESS + 2:
case REG_SECADDRESS + 3:
WRITE8(addr, mystique->dma.secaddress, val);
mystique->dma.sec_state = 0;
break;
case REG_TMR0:
case REG_TMR0 + 1:
case REG_TMR0 + 2:
case REG_TMR0 + 3:
WRITE8(addr, mystique->dwgreg.tmr[0], val);
break;
case REG_TMR1:
case REG_TMR1 + 1:
case REG_TMR1 + 2:
case REG_TMR1 + 3:
WRITE8(addr, mystique->dwgreg.tmr[1], val);
break;
case REG_TMR2:
case REG_TMR2 + 1:
case REG_TMR2 + 2:
case REG_TMR2 + 3:
WRITE8(addr, mystique->dwgreg.tmr[2], val);
break;
case REG_TMR3:
case REG_TMR3 + 1:
case REG_TMR3 + 2:
case REG_TMR3 + 3:
WRITE8(addr, mystique->dwgreg.tmr[3], val);
break;
case REG_TMR4:
case REG_TMR4 + 1:
case REG_TMR4 + 2:
case REG_TMR4 + 3:
WRITE8(addr, mystique->dwgreg.tmr[4], val);
break;
case REG_TMR5:
case REG_TMR5 + 1:
case REG_TMR5 + 2:
case REG_TMR5 + 3:
WRITE8(addr, mystique->dwgreg.tmr[5], val);
break;
case REG_TMR6:
case REG_TMR6 + 1:
case REG_TMR6 + 2:
case REG_TMR6 + 3:
WRITE8(addr, mystique->dwgreg.tmr[6], val);
break;
case REG_TMR7:
case REG_TMR7 + 1:
case REG_TMR7 + 2:
case REG_TMR7 + 3:
WRITE8(addr, mystique->dwgreg.tmr[7], val);
break;
case REG_TMR8:
case REG_TMR8 + 1:
case REG_TMR8 + 2:
case REG_TMR8 + 3:
WRITE8(addr, mystique->dwgreg.tmr[8], val);
break;
case REG_TEXORG:
case REG_TEXORG + 1:
case REG_TEXORG + 2:
case REG_TEXORG + 3:
WRITE8(addr, mystique->dwgreg.texorg, val);
break;
case REG_TEXWIDTH:
case REG_TEXWIDTH + 1:
case REG_TEXWIDTH + 2:
case REG_TEXWIDTH + 3:
WRITE8(addr, mystique->dwgreg.texwidth, val);
break;
case REG_TEXHEIGHT:
case REG_TEXHEIGHT + 1:
case REG_TEXHEIGHT + 2:
case REG_TEXHEIGHT + 3:
WRITE8(addr, mystique->dwgreg.texheight, val);
break;
case REG_TEXCTL:
case REG_TEXCTL + 1:
case REG_TEXCTL + 2:
case REG_TEXCTL + 3:
WRITE8(addr, mystique->dwgreg.texctl, val);
mystique->dwgreg.ta_key = (mystique->dwgreg.texctl & TEXCTL_TAKEY) ? 1 : 0;
mystique->dwgreg.ta_mask = (mystique->dwgreg.texctl & TEXCTL_TAMASK) ? 1 : 0;
break;
case REG_TEXTRANS:
case REG_TEXTRANS + 1:
case REG_TEXTRANS + 2:
case REG_TEXTRANS + 3:
WRITE8(addr, mystique->dwgreg.textrans, val);
break;
case 0x1c18:
case 0x1c19:
case 0x1c1a:
case 0x1c1b:
case 0x1c28:
case 0x1c29:
case 0x1c2a:
case 0x1c2b:
case 0x1c2c:
case 0x1c2d:
case 0x1c2e:
case 0x1c2f:
case 0x1cc4:
case 0x1cc5:
case 0x1cc6:
case 0x1cc7:
case 0x1cd4:
case 0x1cd5:
case 0x1cd6:
case 0x1cd7:
case 0x1ce4:
case 0x1ce5:
case 0x1ce6:
case 0x1ce7:
case 0x1cf4:
case 0x1cf5:
case 0x1cf6:
case 0x1cf7:
break;
case REG_OPMODE:
mystique->dwgreg.dmamod = (val >> 2) & 3;
mystique->dma.iload_state = 0;
break;
default:
if ((addr & 0x3fff) >= 0x2c4c && (addr & 0x3fff) <= 0x2cff)
break;
break;
}
if (start_blit)
mystique_start_blit(mystique);
}
static void
mystique_ctrl_write_b(uint32_t addr, uint8_t val, void *priv)
{
mystique_t *mystique = (mystique_t *) priv;
svga_t *svga = &mystique->svga;
uint8_t addr_0x0f = 0;
uint16_t addr_0x03 = 0;
int rs2 = 0;
int rs3 = 0;
if ((mystique->type == MGA_2064W || mystique->type == MGA_2164W) && (addr & 0x3e00) == 0x3c00) {
/*RAMDAC*/
addr_0x0f = addr & 0x0f;
if ((addr & 3) == 0)
addr_0x03 = 0x3c8;
else if ((addr & 3) == 1)
addr_0x03 = 0x3c9;
else if ((addr & 3) == 2)
addr_0x03 = 0x3c6;
else if ((addr & 3) == 3)
addr_0x03 = 0x3c7;
if ((addr_0x0f >= 0x04) && (addr_0x0f <= 0x07)) {
rs2 = 1;
rs3 = 0;
} else if ((addr_0x0f >= 0x08) && (addr_0x0f <= 0x0b)) {
rs2 = 0;
rs3 = 1;
} else if ((addr_0x0f >= 0x0c) && (addr_0x0f <= 0x0f)) {
rs2 = 1;
rs3 = 1;
}
tvp3026_ramdac_out(addr_0x03, rs2, rs3, val, svga->ramdac, svga);
return;
}
if ((addr & 0x3fff) < 0x1c00) {
mystique_iload_write_b(addr, val, priv);
return;
}
if ((addr & 0x3e00) == 0x1c00 || (addr & 0x3e00) == 0x2c00) {
if ((addr & 0x300) == 0x100)
mystique->blitter_submit_refcount++;
mystique_queue(mystique, addr & 0x3fff, val, FIFO_WRITE_CTRL_BYTE);
return;
}
switch (addr & 0x3fff) {
case REG_ICLEAR:
if (val & ICLEAR_SOFTRAPICLR) {
//pclog("softrapiclr\n");
mystique->status &= ~STATUS_SOFTRAPEN;
mystique_update_irqs(mystique);
}
if (val & ICLEAR_VLINEICLR) {
mystique->status &= ~STATUS_VLINEPEN;
mystique_update_irqs(mystique);
}
break;
case REG_ICLEAR + 1:
case REG_ICLEAR + 2:
case REG_ICLEAR + 3:
break;
case REG_IEN:
mystique->ien = val & 0x65;
break;
case REG_IEN + 1:
case REG_IEN + 2:
case REG_IEN + 3:
break;
case REG_OPMODE:
thread_wait_mutex(mystique->dma.lock);
mystique->dma.state = DMA_STATE_IDLE; /* Interrupt DMA. */
thread_release_mutex(mystique->dma.lock);
mystique->dmamod = (val >> 2) & 3;
mystique_queue(mystique, addr & 0x3fff, val, FIFO_WRITE_CTRL_BYTE);
break;
case REG_OPMODE + 1:
mystique->dmadatasiz = val & 3;
break;
case REG_OPMODE + 2:
mystique->dirdatasiz = val & 3;
break;
case REG_OPMODE + 3:
break;
case REG_PRIMADDRESS:
case REG_PRIMADDRESS + 1:
case REG_PRIMADDRESS + 2:
case REG_PRIMADDRESS + 3:
thread_wait_mutex(mystique->dma.lock);
WRITE8(addr, mystique->dma.primaddress, val);
mystique->dma.pri_state = 0;
if (mystique->dma.state == DMA_STATE_IDLE && !(mystique->softrap_pending || mystique->endprdmasts_pending || !mystique->softrap_status_read)) {
mystique->dma.words_expected = 0;
}
mystique->dma.state = DMA_STATE_IDLE;
thread_release_mutex(mystique->dma.lock);
break;
case REG_DMAMAP:
case REG_DMAMAP + 0x1:
case REG_DMAMAP + 0x2:
case REG_DMAMAP + 0x3:
case REG_DMAMAP + 0x4:
case REG_DMAMAP + 0x5:
case REG_DMAMAP + 0x6:
case REG_DMAMAP + 0x7:
case REG_DMAMAP + 0x8:
case REG_DMAMAP + 0x9:
case REG_DMAMAP + 0xa:
case REG_DMAMAP + 0xb:
case REG_DMAMAP + 0xc:
case REG_DMAMAP + 0xd:
case REG_DMAMAP + 0xe:
case REG_DMAMAP + 0xf:
mystique->dmamap[addr & 0xf] = val;
break;
case REG_RST:
case REG_RST + 1:
case REG_RST + 2:
case REG_RST + 3:
wait_fifo_idle(mystique);
mystique->busy = 0;
mystique->blitter_submit_refcount = 0;
mystique->blitter_submit_dma_refcount = 0;
mystique->blitter_complete_refcount = 0;
mystique->dwgreg.iload_rem_count = 0;
mystique->status = STATUS_ENDPRDMASTS;
thread_wait_mutex(mystique->dma.lock);
mystique->dma.pri_state = 0;
mystique->dma.sec_state = 0;
mystique->dma.state = DMA_STATE_IDLE;
mystique->dma.words_expected = 0;
thread_release_mutex(mystique->dma.lock);
break;
case REG_ATTR_IDX:
svga_out(0x3c0, val, svga);
break;
case REG_ATTR_DATA:
svga_out(0x3c1, val, svga);
break;
case REG_MISC:
svga_out(0x3c2, val, svga);
break;
case REG_SEQ_IDX:
svga_out(0x3c4, val, svga);
break;
case REG_SEQ_DATA:
svga_out(0x3c5, val, svga);
break;
case REG_GCTL_IDX:
mystique_out(0x3ce, val, mystique);
break;
case REG_GCTL_DATA:
mystique_out(0x3cf, val, mystique);
break;
case REG_CRTC_IDX:
mystique_out(0x3d4, val, mystique);
break;
case REG_CRTC_DATA:
mystique_out(0x3d5, val, mystique);
break;
case REG_CRTCEXT_IDX:
mystique_out(0x3de, val, mystique);
break;
case REG_CRTCEXT_DATA:
mystique_out(0x3df, val, mystique);
break;
case REG_CACHEFLUSH:
break;
case REG_PALWTADD:
svga_out(0x3c8, val, svga);
mystique->xreg_idx = val;
break;
case REG_PALDATA:
svga_out(0x3c9, val, svga);
break;
case REG_PIXRDMSK:
svga_out(0x3c6, val, svga);
break;
case REG_PALRDADD:
svga_out(0x3c7, val, svga);
break;
case REG_X_DATAREG:
mystique_write_xreg(mystique, mystique->xreg_idx, val);
break;
case REG_CURPOSX:
case REG_CURPOSX + 1:
WRITE8(addr, mystique->cursor.pos_x, val);
svga->hwcursor.x = mystique->cursor.pos_x - 64;
break;
case REG_CURPOSY:
case REG_CURPOSY + 1:
WRITE8(addr & 1, mystique->cursor.pos_y, val);
svga->hwcursor.y = mystique->cursor.pos_y - 64;
break;
case 0x1e50:
case 0x1e51:
case 0x1e52:
case 0x1e53:
case 0x3c0b:
case 0x3e02:
case 0x3e08:
break;
default:
if ((addr & 0x3fff) >= 0x2c4c && (addr & 0x3fff) <= 0x2cff)
break;
if ((addr & 0x3fff) >= 0x3e00)
break;
break;
}
}
static uint32_t
mystique_ctrl_read_l(uint32_t addr, void *priv)
{
uint32_t ret;
if ((addr & 0x3fff) < 0x1c00)
return mystique_iload_read_l(addr, priv);
ret = mystique_ctrl_read_b(addr, priv);
ret |= mystique_ctrl_read_b(addr + 1, priv) << 8;
ret |= mystique_ctrl_read_b(addr + 2, priv) << 16;
ret |= mystique_ctrl_read_b(addr + 3, priv) << 24;
return ret;
}
static void
mystique_accel_ctrl_write_l(uint32_t addr, uint32_t val, void *priv)
{
mystique_t *mystique = (mystique_t *) priv;
int start_blit = 0;
if ((addr & 0x300) == 0x100) {
addr &= ~0x100;
start_blit = 1;
}
switch (addr & 0x3ffc) {
case REG_DWGCTL:
mystique->dwgreg.dwgctrl = val;
if (val & DWGCTRL_SOLID) {
for (uint8_t y = 0; y < 8; y++) {
for (uint8_t x = 0; x < 16; x++)
mystique->dwgreg.pattern[y][x] = 1;
}
mystique->dwgreg.src[0] = 0xffffffff;
mystique->dwgreg.src[1] = 0xffffffff;
mystique->dwgreg.src[2] = 0xffffffff;
mystique->dwgreg.src[3] = 0xffffffff;
}
if (val & DWGCTRL_ARZERO) {
mystique->dwgreg.ar[0] = 0;
mystique->dwgreg.ar[1] = 0;
mystique->dwgreg.ar[2] = 0;
mystique->dwgreg.ar[4] = 0;
mystique->dwgreg.ar[5] = 0;
mystique->dwgreg.ar[6] = 0;
}
if (val & DWGCTRL_SGNZERO) {
mystique->dwgreg.sgn.sdydxl = 0;
mystique->dwgreg.sgn.scanleft = 0;
mystique->dwgreg.sgn.sdxl = 0;
mystique->dwgreg.sgn.sdy = 0;
mystique->dwgreg.sgn.sdxr = 0;
}
if (val & DWGCTRL_SHTZERO) {
mystique->dwgreg.funcnt = 0;
mystique->dwgreg.stylelen = 0;
mystique->dwgreg.xoff = 0;
mystique->dwgreg.yoff = 0;
}
break;
case REG_ZORG:
mystique->dwgreg.zorg = val;
mystique->dwgreg.z_base = mystique->dwgreg.ydstorg * ((mystique->maccess & MACCESS_ZWIDTH) ? 4 : 2) + mystique->dwgreg.zorg;
break;
case REG_PLNWT:
mystique->dwgreg.plnwt = val;
break;
case REG_SHIFT:
mystique->dwgreg.funcnt = val & 0x7f;
mystique->dwgreg.xoff = val & 7;
mystique->dwgreg.yoff = (val >> 4) & 7;
mystique->dwgreg.stylelen = (val >> 16) & 0x7f;
break;
case REG_PITCH:
mystique->dwgreg.pitch = val & 0xffff;
if (mystique->dwgreg.pitch & PITCH_YLIN)
mystique->dwgreg.ydst_lin = (mystique->dwgreg.ydst << 5) + mystique->dwgreg.ydstorg;
else
mystique->dwgreg.ydst_lin = ((int32_t) (int16_t) mystique->dwgreg.ydst * (mystique->dwgreg.pitch & PITCH_MASK)) + mystique->dwgreg.ydstorg;
break;
case REG_YDST:
mystique->dwgreg.ydst = val & 0x3fffff;
if (mystique->dwgreg.pitch & PITCH_YLIN) {
mystique->dwgreg.ydst_lin = (mystique->dwgreg.ydst << 5) + mystique->dwgreg.ydstorg;
mystique->dwgreg.selline = val >> 29;
} else {
mystique->dwgreg.ydst_lin = ((int32_t) (int16_t) mystique->dwgreg.ydst * (mystique->dwgreg.pitch & PITCH_MASK)) + mystique->dwgreg.ydstorg;
mystique->dwgreg.selline = val & 7;
}
break;
case REG_BCOL:
mystique->dwgreg.bcol = val;
break;
case REG_FCOL:
mystique->dwgreg.fcol = val;
break;
case REG_SRC0:
{
mystique->dwgreg.src[0] = val;
for (uint8_t y = 0; y < 2; y++) {
for (uint8_t x = 0; x < 16; x++) {
mystique->dwgreg.pattern[y][x] = val & (1 << (x + (y * 16)));
}
}
#if 0
pclog("SRC0 = 0x%08X\n", val);
#endif
if (mystique->busy && (mystique->dwgreg.dwgctrl_running & DWGCTRL_OPCODE_MASK) == DWGCTRL_OPCODE_ILOAD)
blit_iload_write(mystique, mystique->dwgreg.src[0], 32);
}
break;
case REG_SRC1:
{
mystique->dwgreg.src[1] = val;
for (uint8_t y = 2; y < 4; y++) {
for (uint8_t x = 0; x < 16; x++) {
mystique->dwgreg.pattern[y][x] = val & (1 << (x + ((y - 2) * 16)));
}
}
#if 0
pclog("SRC1 = 0x%08X\n", val);
#endif
if (mystique->busy && (mystique->dwgreg.dwgctrl_running & DWGCTRL_OPCODE_MASK) == DWGCTRL_OPCODE_ILOAD)
blit_iload_write(mystique, mystique->dwgreg.src[1], 32);
}
break;
case REG_SRC2:
{
mystique->dwgreg.src[2] = val;
for (uint8_t y = 4; y < 6; y++) {
for (uint8_t x = 0; x < 16; x++) {
mystique->dwgreg.pattern[y][x] = val & (1 << (x + ((y - 4) * 16)));
}
}
#if 0
pclog("SRC2 = 0x%08X\n", val);
#endif
if (mystique->busy && (mystique->dwgreg.dwgctrl_running & DWGCTRL_OPCODE_MASK) == DWGCTRL_OPCODE_ILOAD)
blit_iload_write(mystique, mystique->dwgreg.src[2], 32);
break;
}
case REG_SRC3:
{
mystique->dwgreg.src[3] = val;
for (uint8_t y = 6; y < 8; y++) {
for (uint8_t x = 0; x < 16; x++) {
mystique->dwgreg.pattern[y][x] = val & (1 << (x + ((y - 6) * 16)));
}
}
#if 0
pclog("SRC3 = 0x%08X\n", val);
#endif
if (mystique->busy && (mystique->dwgreg.dwgctrl_running & DWGCTRL_OPCODE_MASK) == DWGCTRL_OPCODE_ILOAD)
blit_iload_write(mystique, mystique->dwgreg.src[3], 32);
break;
}
case REG_DMAPAD:
if (mystique->busy && (mystique->dwgreg.dwgctrl_running & DWGCTRL_OPCODE_MASK) == DWGCTRL_OPCODE_ILOAD)
blit_iload_write(mystique, val, 32);
break;
case REG_AR0:
mystique->dwgreg.ar[0] = val;
break;
case REG_AR1:
mystique->dwgreg.ar[1] = val;
break;
case REG_AR2:
mystique->dwgreg.ar[2] = val;
break;
case REG_AR3:
mystique->dwgreg.ar[3] = val;
break;
case REG_AR4:
mystique->dwgreg.ar[4] = val;
break;
case REG_AR5:
mystique->dwgreg.ar[5] = val;
break;
case REG_AR6:
mystique->dwgreg.ar[6] = val;
break;
case REG_DR0_Z32LSB:
mystique->dwgreg.extended_dr[0] = (mystique->dwgreg.extended_dr[0] & ~0xFFFFFFFF) | val;
mystique->dwgreg.dr[0] = (mystique->dwgreg.extended_dr[0] >> 16) & 0xFFFFFFFF;
break;
case REG_DR0_Z32MSB:
mystique->dwgreg.extended_dr[0] = (mystique->dwgreg.extended_dr[0] & 0xFFFFFFFF) | ((val & 0xFFFFull) << 32ull);
mystique->dwgreg.dr[0] = (mystique->dwgreg.extended_dr[0] >> 16) & 0xFFFFFFFF;
break;
case REG_DR2_Z32LSB:
mystique->dwgreg.extended_dr[2] = (mystique->dwgreg.extended_dr[2] & ~0xFFFFFFFF) | val;
mystique->dwgreg.dr[2] = (mystique->dwgreg.extended_dr[2] >> 16) & 0xFFFFFFFF;
break;
case REG_DR2_Z32MSB:
mystique->dwgreg.extended_dr[2] = (mystique->dwgreg.extended_dr[2] & 0xFFFFFFFF) | ((val & 0xFFFFull) << 32ull);
mystique->dwgreg.dr[2] = (mystique->dwgreg.extended_dr[2] >> 16) & 0xFFFFFFFF;
break;
case REG_DR3_Z32LSB:
mystique->dwgreg.extended_dr[3] = (mystique->dwgreg.extended_dr[3] & ~0xFFFFFFFF) | val;
mystique->dwgreg.dr[3] = (mystique->dwgreg.extended_dr[3] >> 16) & 0xFFFFFFFF;
break;
case REG_DR3_Z32MSB:
mystique->dwgreg.extended_dr[3] = (mystique->dwgreg.extended_dr[3] & 0xFFFFFFFF) | ((val & 0xFFFFull) << 32ull);
mystique->dwgreg.dr[3] = (mystique->dwgreg.extended_dr[3] >> 16) & 0xFFFFFFFF;
break;
case REG_DR0:
mystique->dwgreg.dr[0] = val;
mystique->dwgreg.extended_dr[0] = (mystique->dwgreg.extended_dr[0] & ~0xFFFFull) | ((uint64_t)val << 16ull);
break;
case REG_DR2:
mystique->dwgreg.dr[2] = val;
mystique->dwgreg.extended_dr[2] = (mystique->dwgreg.extended_dr[2] & ~0xFFFFull) | ((uint64_t)val << 16ull);
break;
case REG_DR3:
mystique->dwgreg.dr[3] = val;
mystique->dwgreg.extended_dr[3] = (mystique->dwgreg.extended_dr[3] & ~0xFFFFull) | ((uint64_t)val << 16ull);
break;
case REG_DR4:
mystique->dwgreg.dr[4] = val;
break;
case REG_DR6:
mystique->dwgreg.dr[6] = val;
break;
case REG_DR7:
mystique->dwgreg.dr[7] = val;
break;
case REG_DR8:
mystique->dwgreg.dr[8] = val;
break;
case REG_DR10:
mystique->dwgreg.dr[10] = val;
break;
case REG_DR11:
mystique->dwgreg.dr[11] = val;
break;
case REG_DR12:
mystique->dwgreg.dr[12] = val;
break;
case REG_DR14:
mystique->dwgreg.dr[14] = val;
break;
case REG_DR15:
mystique->dwgreg.dr[15] = val;
break;
case REG_SECEND:
mystique->dma.secend = val;
if (mystique->dma.state != DMA_STATE_SEC && (mystique->dma.secaddress & DMA_ADDR_MASK) != (mystique->dma.secend & DMA_ADDR_MASK))
mystique->dma.state = DMA_STATE_SEC;
break;
case REG_SOFTRAP:
mystique->dma.state = DMA_STATE_IDLE;
mystique->dma.pri_state = 0;
mystique->dma.words_expected = 0;
mystique->endprdmasts_pending = 1;
mystique->softrap_pending_val = val;
mystique->softrap_pending += 1;
break;
case REG_ALPHACTRL:
mystique->dwgreg.alphactrl = val;
break;
case REG_ALPHASTART:
mystique->dwgreg.alphastart = val;
break;
case REG_ALPHAXINC:
mystique->dwgreg.alphaxinc = val;
break;
case REG_ALPHAYINC:
mystique->dwgreg.alphayinc = val;
break;
case REG_FOGCOL:
mystique->dwgreg.fogcol = val;
break;
case REG_FOGSTART:
mystique->dwgreg.fogstart = val;
break;
case REG_FOGXINC:
mystique->dwgreg.fogxinc = val;
break;
case REG_FOGYINC:
mystique->dwgreg.fogyinc = val;
break;
case REG_TEXFILTER:
mystique->dwgreg.texfilter = val;
break;
default:
mystique_accel_ctrl_write_b(addr, val & 0xff, priv);
mystique_accel_ctrl_write_b(addr + 1, (val >> 8) & 0xff, priv);
mystique_accel_ctrl_write_b(addr + 2, (val >> 16) & 0xff, priv);
mystique_accel_ctrl_write_b(addr + 3, (val >> 24) & 0xff, priv);
break;
}
if (start_blit)
mystique_start_blit(mystique);
}
static void
mystique_ctrl_write_l(uint32_t addr, uint32_t val, void *priv)
{
mystique_t *mystique = (mystique_t *) priv;
uint32_t reg_addr;
if ((addr & 0x3fff) < 0x1c00) {
mystique_iload_write_l(addr, val, priv);
return;
}
if ((addr & 0x3e00) == 0x1c00 || (addr & 0x3e00) == 0x2c00) {
if ((addr & 0x300) == 0x100)
mystique->blitter_submit_refcount++;
mystique_queue(mystique, addr & 0x3fff, val, FIFO_WRITE_CTRL_LONG);
return;
}
switch (addr & 0x3ffc) {
case REG_PRIMEND:
thread_wait_mutex(mystique->dma.lock);
mystique->dma.primend = val;
//pclog("PRIMADDRESS = 0x%08X, PRIMEND = 0x%08X\n", mystique->dma.primaddress, mystique->dma.primend);
if (mystique->dma.state == DMA_STATE_IDLE && (mystique->dma.primaddress & DMA_ADDR_MASK) != (mystique->dma.primend & DMA_ADDR_MASK)) {
mystique->endprdmasts_pending = 0;
mystique->status &= ~STATUS_ENDPRDMASTS;
mystique->dma.state = DMA_STATE_PRI;
//mystique->dma.pri_state = 0;
wake_fifo_thread(mystique);
}
/* HACK: For DirectX 9.0b Direct3D testing on Windows 98 SE.
The 4.12.013 drivers give an out-of-bounds busmastering range when dxdiag enumerates Direct3D, with exactly 16384 bytes of difference.
Don't attempt busmastering in such cases. This isn't ideal, but there are no more crashes faced in this case. */
if ((mystique->dma.primend & DMA_ADDR_MASK) < (mystique->dma.primaddress & DMA_ADDR_MASK) && ((mystique->dma.primaddress & DMA_ADDR_MASK) - (mystique->dma.primend & DMA_ADDR_MASK)) == 0x4000)
{
mystique->dma.primaddress = mystique->dma.primend;
mystique->endprdmasts_pending = 1;
mystique->dma.state = DMA_STATE_IDLE;
}
thread_release_mutex(mystique->dma.lock);
break;
case REG_DWG_INDIR_WT:
case REG_DWG_INDIR_WT + 0x04:
case REG_DWG_INDIR_WT + 0x08:
case REG_DWG_INDIR_WT + 0x0c:
case REG_DWG_INDIR_WT + 0x10:
case REG_DWG_INDIR_WT + 0x14:
case REG_DWG_INDIR_WT + 0x18:
case REG_DWG_INDIR_WT + 0x1c:
case REG_DWG_INDIR_WT + 0x20:
case REG_DWG_INDIR_WT + 0x24:
case REG_DWG_INDIR_WT + 0x28:
case REG_DWG_INDIR_WT + 0x2c:
case REG_DWG_INDIR_WT + 0x30:
case REG_DWG_INDIR_WT + 0x34:
case REG_DWG_INDIR_WT + 0x38:
case REG_DWG_INDIR_WT + 0x3c:
reg_addr = (mystique->dmamap[(addr >> 2) & 0xf] & 0x7f) << 2;
if (mystique->dmamap[(addr >> 2) & 0xf] & 0x80)
reg_addr += 0x2c00;
else
reg_addr += 0x1c00;
if ((reg_addr & 0x300) == 0x100)
mystique->blitter_submit_refcount++;
mystique_queue(mystique, reg_addr, val, FIFO_WRITE_CTRL_LONG);
break;
default:
mystique_ctrl_write_b(addr, val & 0xff, priv);
mystique_ctrl_write_b(addr + 1, (val >> 8) & 0xff, priv);
mystique_ctrl_write_b(addr + 2, (val >> 16) & 0xff, priv);
mystique_ctrl_write_b(addr + 3, (val >> 24) & 0xff, priv);
break;
}
}
static uint8_t
mystique_iload_read_b(UNUSED(uint32_t addr), void *priv)
{
mystique_t *mystique = (mystique_t *) priv;
wait_fifo_idle(mystique);
if (!mystique->busy)
return 0xff;
return blit_idump_read(mystique);
}
static uint32_t
mystique_iload_read_l(UNUSED(uint32_t addr), void *priv)
{
mystique_t *mystique = (mystique_t *) priv;
wait_fifo_idle(mystique);
if (!mystique->busy)
return 0xffffffff;
mystique->dwgreg.words++;
return blit_idump_read(mystique);
}
static void
mystique_iload_write_b(UNUSED(uint32_t addr), UNUSED(uint8_t val), UNUSED(void *priv))
{
//
}
static void
mystique_iload_write_l(UNUSED(uint32_t addr), uint32_t val, void *priv)
{
mystique_t *mystique = (mystique_t *) priv;
mystique_queue(mystique, 0, val, FIFO_WRITE_ILOAD_LONG);
}
static void
mystique_accel_iload_write_l(UNUSED(uint32_t addr), uint32_t val, void *priv)
{
mystique_t *mystique = (mystique_t *) priv;
switch (mystique->dwgreg.dmamod) {
case DMA_MODE_REG:
if (mystique->dma.iload_state == 0) {
mystique->dma.iload_header = val;
mystique->dma.iload_state = 1;
} else {
uint32_t reg_addr = (mystique->dma.iload_header & 0x7f) << 2;
if (mystique->dma.iload_header & 0x80)
reg_addr += 0x2c00;
else
reg_addr += 0x1c00;
if ((reg_addr & 0x300) == 0x100)
mystique->blitter_submit_dma_refcount++;
mystique_accel_ctrl_write_l(reg_addr, val, mystique);
mystique->dma.iload_header >>= 8;
mystique->dma.iload_state = (mystique->dma.iload_state == 4) ? 0 : (mystique->dma.iload_state + 1);
}
break;
case DMA_MODE_BLIT:
if (mystique->busy)
blit_iload_write(mystique, val, 32);
break;
default:
#if 0
pclog("ILOAD write DMAMOD %i\n", mystique->dwgreg.dmamod); */
#endif
break;
}
}
static uint8_t
mystique_readb_linear(uint32_t addr, void *priv)
{
const svga_t *svga = (svga_t *) priv;
cycles -= svga->monitor->mon_video_timing_read_b;
if (!svga->fast) {
if (svga->chain2_read) {
addr &= ~1;
addr <<= 2;
}
}
addr &= svga->decode_mask;
if (addr >= svga->vram_max)
return 0xff;
return svga->vram[addr & svga->vram_mask];
}
static uint16_t
mystique_readw_linear(uint32_t addr, void *priv)
{
svga_t *svga = (svga_t *) priv;
cycles -= svga->monitor->mon_video_timing_read_w;
addr &= svga->decode_mask;
if (addr >= svga->vram_max)
return 0xffff;
return *(uint16_t *) &svga->vram[addr & svga->vram_mask];
}
static uint32_t
mystique_readl_linear(uint32_t addr, void *priv)
{
svga_t *svga = (svga_t *) priv;
cycles -= svga->monitor->mon_video_timing_read_l;
addr &= svga->decode_mask;
if (addr >= svga->vram_max)
return 0xffffffff;
return *(uint32_t *) &svga->vram[addr & svga->vram_mask];
}
static void
mystique_writeb_linear(uint32_t addr, uint8_t val, void *priv)
{
svga_t *svga = (svga_t *) priv;
cycles -= svga->monitor->mon_video_timing_write_b;
if (!svga->fast) {
if (svga->chain2_write) {
addr &= ~1;
addr <<= 2;
}
}
addr &= svga->decode_mask;
if (addr >= svga->vram_max)
return;
addr &= svga->vram_mask;
svga->changedvram[addr >> 12] = svga->monitor->mon_changeframecount;
svga->vram[addr] = val;
}
static void
mystique_writew_linear(uint32_t addr, uint16_t val, void *priv)
{
svga_t *svga = (svga_t *) priv;
cycles -= svga->monitor->mon_video_timing_write_w;
addr &= svga->decode_mask;
if (addr >= svga->vram_max)
return;
addr &= svga->vram_mask;
svga->changedvram[addr >> 12] = svga->monitor->mon_changeframecount;
*(uint16_t *) &svga->vram[addr] = val;
}
static void
mystique_writel_linear(uint32_t addr, uint32_t val, void *priv)
{
svga_t *svga = (svga_t *) priv;
cycles -= svga->monitor->mon_video_timing_write_l;
addr &= svga->decode_mask;
if (addr >= svga->vram_max)
return;
addr &= svga->vram_mask;
svga->changedvram[addr >> 12] = svga->monitor->mon_changeframecount;
*(uint32_t *) &svga->vram[addr] = val;
}
static void
run_dma(mystique_t *mystique)
{
int words_transferred = 0;
thread_wait_mutex(mystique->dma.lock);
if (mystique->softrap_pending || mystique->endprdmasts_pending || !mystique->softrap_status_read)
{
thread_release_mutex(mystique->dma.lock);
return;
}
if (mystique->dma.state == DMA_STATE_IDLE) {
if (!(mystique->status & STATUS_ENDPRDMASTS))
{
/* Force this to appear. */
mystique->endprdmasts_pending = 1;
}
thread_release_mutex(mystique->dma.lock);
return;
}
while (words_transferred < DMA_MAX_WORDS && mystique->dma.state != DMA_STATE_IDLE) {
switch (atomic_load(&mystique->dma.state)) {
case DMA_STATE_PRI:
switch (mystique->dma.primaddress & DMA_MODE_MASK) {
case DMA_MODE_REG:
if ((mystique->dma.primaddress & DMA_ADDR_MASK) == (mystique->dma.primend & DMA_ADDR_MASK)) {
mystique->endprdmasts_pending = 1;
mystique->dma.state = DMA_STATE_IDLE;
break;
}
if (mystique->dma.pri_state == 0 && !mystique->dma.words_expected) {
dma_bm_read(mystique->dma.primaddress & DMA_ADDR_MASK, (uint8_t *) &mystique->dma.pri_header, 4, 4);
//pclog("DMA header: 0x%08X\n", mystique->dma.pri_header);
mystique->dma.primaddress += 4;
mystique->dma.words_expected = 4;
words_transferred++;
}
if ((mystique->dma.primaddress & DMA_ADDR_MASK) == (mystique->dma.primend & DMA_ADDR_MASK)) {
mystique->endprdmasts_pending = 1;
mystique->dma.state = DMA_STATE_IDLE;
break;
}
{
uint32_t val;
uint32_t reg_addr;
dma_bm_read(mystique->dma.primaddress & DMA_ADDR_MASK, (uint8_t *) &val, 4, 4);
words_transferred++;
reg_addr = (mystique->dma.pri_header & 0x7f) << 2;
if (mystique->dma.pri_header & 0x80)
reg_addr += 0x2c00;
else
reg_addr += 0x1c00;
if ((reg_addr & 0x300) == 0x100)
mystique->blitter_submit_dma_refcount++;
//pclog("DMA value: 0x%08X to reg 0x%04X\n", val, reg_addr);
mystique_accel_ctrl_write_l(reg_addr, val, mystique);
if (reg_addr == REG_SOFTRAP) {
mystique->dma.primaddress += 4;
break;
}
}
if (mystique->dma.words_expected)
mystique->dma.words_expected--;
mystique->dma.primaddress += 4;
mystique->dma.pri_header >>= 8;
mystique->dma.pri_state = (mystique->dma.pri_state + 1) & 3;
if (mystique->dma.state == DMA_STATE_SEC) {
mystique->dma.sec_state = 0;
}
else if ((mystique->dma.primaddress & DMA_ADDR_MASK) == (mystique->dma.primend & DMA_ADDR_MASK)) {
mystique->endprdmasts_pending = 1;
mystique->dma.state = DMA_STATE_IDLE;
}
break;
default:
fatal("DMA_STATE_PRI: mode %i\n", mystique->dma.primaddress & DMA_MODE_MASK);
}
break;
case DMA_STATE_SEC:
switch (mystique->dma.secaddress & DMA_MODE_MASK) {
case DMA_MODE_REG:
if ((mystique->dma.secaddress & DMA_ADDR_MASK) >= (mystique->dma.secend & DMA_ADDR_MASK)) {
if ((mystique->dma.primaddress & DMA_ADDR_MASK) == (mystique->dma.primend & DMA_ADDR_MASK)) {
mystique->endprdmasts_pending = 1;
mystique->dma.state = DMA_STATE_IDLE;
mystique->dma.pri_state = 0;
mystique->dma.words_expected = 0;
} else {
mystique->dma.state = DMA_STATE_PRI;
mystique->dma.words_expected = 0;
mystique->dma.pri_state = 0;
}
}
if (mystique->dma.sec_state == 0) {
dma_bm_read(mystique->dma.secaddress & DMA_ADDR_MASK, (uint8_t *) &mystique->dma.sec_header, 4, 4);
mystique->dma.secaddress += 4;
//pclog("DMA header (secondary): 0x%08X\n", mystique->dma.sec_header);
words_transferred++;
}
if ((mystique->dma.secaddress & DMA_ADDR_MASK) >= (mystique->dma.secend & DMA_ADDR_MASK)) {
if ((mystique->dma.primaddress & DMA_ADDR_MASK) == (mystique->dma.primend & DMA_ADDR_MASK)) {
mystique->endprdmasts_pending = 1;
mystique->dma.state = DMA_STATE_IDLE;
mystique->dma.pri_state = 0;
mystique->dma.words_expected = 0;
} else {
mystique->dma.state = DMA_STATE_PRI;
mystique->dma.words_expected = 0;
mystique->dma.pri_state = 0;
}
}
uint32_t val;
uint32_t reg_addr;
dma_bm_read(mystique->dma.secaddress & DMA_ADDR_MASK, (uint8_t *) &val, 4, 4);
mystique->dma.secaddress += 4;
reg_addr = (mystique->dma.sec_header & 0x7f) << 2;
if (mystique->dma.sec_header & 0x80)
reg_addr += 0x2c00;
else
reg_addr += 0x1c00;
if ((reg_addr & 0x300) == 0x100)
mystique->blitter_submit_dma_refcount++;
mystique_accel_ctrl_write_l(reg_addr, val, mystique);
//pclog("DMA value (secondary): 0x%08X\n", val);
mystique->dma.sec_header >>= 8;
mystique->dma.sec_state = (mystique->dma.sec_state + 1) & 3;
words_transferred++;
if ((mystique->dma.secaddress & DMA_ADDR_MASK) >= (mystique->dma.secend & DMA_ADDR_MASK)) {
if ((mystique->dma.primaddress & DMA_ADDR_MASK) == (mystique->dma.primend & DMA_ADDR_MASK)) {
mystique->endprdmasts_pending = 1;
mystique->dma.state = DMA_STATE_IDLE;
mystique->dma.pri_state = 0;
mystique->dma.words_expected = 0;
} else {
mystique->dma.state = DMA_STATE_PRI;
mystique->dma.words_expected = 0;
mystique->dma.pri_state = 0;
}
}
break;
case DMA_MODE_BLIT:
{
uint32_t val;
if ((mystique->dma.secaddress & DMA_ADDR_MASK) >= (mystique->dma.secend & DMA_ADDR_MASK)) {
if ((mystique->dma.primaddress & DMA_ADDR_MASK) == (mystique->dma.primend & DMA_ADDR_MASK)) {
mystique->endprdmasts_pending = 1;
mystique->dma.state = DMA_STATE_IDLE;
mystique->dma.words_expected = 0;
mystique->dma.pri_state = 0;
} else {
mystique->dma.state = DMA_STATE_PRI;
mystique->dma.words_expected = 0;
mystique->dma.pri_state = 0;
}
}
dma_bm_read(mystique->dma.secaddress & DMA_ADDR_MASK, (uint8_t *) &val, 4, 4);
mystique->dma.secaddress += 4;
if (mystique->busy)
blit_iload_write(mystique, val, 32);
words_transferred++;
if ((mystique->dma.secaddress & DMA_ADDR_MASK) >= (mystique->dma.secend & DMA_ADDR_MASK)) {
if ((mystique->dma.primaddress & DMA_ADDR_MASK) == (mystique->dma.primend & DMA_ADDR_MASK)) {
mystique->endprdmasts_pending = 1;
mystique->dma.state = DMA_STATE_IDLE;
mystique->dma.words_expected = 0;
mystique->dma.pri_state = 0;
} else {
mystique->dma.state = DMA_STATE_PRI;
mystique->dma.words_expected = 0;
mystique->dma.pri_state = 0;
}
}
}
break;
default:
fatal("DMA_STATE_SEC: mode %i\n", mystique->dma.secaddress & DMA_MODE_MASK);
}
break;
default:
break;
}
}
thread_release_mutex(mystique->dma.lock);
}
static void
fifo_thread(void *priv)
{
mystique_t *mystique = (mystique_t *) priv;
while (mystique->thread_run) {
thread_set_event(mystique->fifo_not_full_event);
thread_wait_event(mystique->wake_fifo_thread, -1);
thread_reset_event(mystique->wake_fifo_thread);
while (!FIFO_EMPTY || mystique->dma.state != DMA_STATE_IDLE) {
int words_transferred = 0;
while (!FIFO_EMPTY && words_transferred < 100) {
fifo_entry_t *fifo = &mystique->fifo[mystique->fifo_read_idx & FIFO_MASK];
switch (fifo->addr_type & FIFO_TYPE) {
case FIFO_WRITE_CTRL_BYTE:
mystique_accel_ctrl_write_b(fifo->addr_type & FIFO_ADDR, fifo->val, mystique);
break;
case FIFO_WRITE_CTRL_LONG:
mystique_accel_ctrl_write_l(fifo->addr_type & FIFO_ADDR, fifo->val, mystique);
break;
case FIFO_WRITE_ILOAD_LONG:
mystique_accel_iload_write_l(fifo->addr_type & FIFO_ADDR, fifo->val, mystique);
break;
default:
break;
}
fifo->addr_type = FIFO_INVALID;
mystique->fifo_read_idx++;
if (FIFO_ENTRIES > FIFO_THRESHOLD)
thread_set_event(mystique->fifo_not_full_event);
words_transferred++;
}
/*Only run DMA once the FIFO is empty. Required by
Screamer 2 / Rally which will incorrectly clip an ILOAD
if DMA runs ahead*/
if (!words_transferred)
run_dma(mystique);
}
}
}
static void
wake_fifo_thread(mystique_t *mystique)
{
if (!timer_is_enabled(&mystique->wake_timer)) {
/* Don't wake FIFO thread immediately - if we do that it will probably
process one word and go back to sleep, requiring it to be woken on
almost every write. Instead, wait a short while so that the CPU
emulation writes more data so we have more batched-up work. */
timer_set_delay_u64(&mystique->wake_timer, WAKE_DELAY);
}
}
static void
wake_fifo_thread_now(mystique_t *mystique)
{
thread_set_event(mystique->wake_fifo_thread);
}
static void
mystique_wake_timer(void *priv)
{
mystique_t *mystique = (mystique_t *) priv;
thread_set_event(mystique->wake_fifo_thread); /*Wake up FIFO thread if moving from idle*/
}
static void
wait_fifo_idle(mystique_t *mystique)
{
while (!FIFO_EMPTY) {
wake_fifo_thread_now(mystique);
thread_wait_event(mystique->fifo_not_full_event, 1);
}
}
/*IRQ code (PCI & PIC) is not currently thread safe. SOFTRAP IRQ requests must
therefore be submitted from the main emulation thread, in this case via a timer
callback. End-of-DMA status is also deferred here to prevent races between
SOFTRAP IRQs and code reading the status register. Croc will get into an IRQ
loop and triple fault if the ENDPRDMASTS flag is seen before the IRQ is taken*/
static void
mystique_softrap_pending_timer(void *priv)
{
mystique_t *mystique = (mystique_t *) priv;
timer_advance_u64(&mystique->softrap_pending_timer, TIMER_USEC * 100);
if (mystique->endprdmasts_pending) {
mystique->endprdmasts_pending = 0;
mystique->status |= STATUS_ENDPRDMASTS;
}
if (mystique->softrap_pending) {
mystique->dma.secaddress = mystique->softrap_pending_val;
mystique->status |= STATUS_SOFTRAPEN;
mystique->softrap_status_read = 0;
//pclog("softrapen\n");
mystique_update_irqs(mystique);
mystique->softrap_pending--;
}
}
static void
mystique_queue(mystique_t *mystique, uint32_t addr, uint32_t val, uint32_t type)
{
fifo_entry_t *fifo = &mystique->fifo[mystique->fifo_write_idx & FIFO_MASK];
if (FIFO_FULL) {
thread_reset_event(mystique->fifo_not_full_event);
if (FIFO_FULL)
thread_wait_event(mystique->fifo_not_full_event, -1); /* Wait for room in ringbuffer */
}
fifo->val = val;
fifo->addr_type = (addr & FIFO_ADDR) | type;
mystique->fifo_write_idx++;
if (FIFO_ENTRIES > FIFO_THRESHOLD || FIFO_ENTRIES < 8)
wake_fifo_thread(mystique);
}
static uint32_t
bitop(uint32_t src, uint32_t dst, uint32_t dwgctrl)
{
switch (dwgctrl & DWGCTRL_BOP_MASK) {
case BOP(0x0):
return 0;
case BOP(0x1):
return ~(dst | src);
case BOP(0x2):
return dst & ~src;
case BOP(0x3):
return ~src;
case BOP(0x4):
return ~dst & src;
case BOP(0x5):
return ~dst;
case BOP(0x6):
return dst ^ src;
case BOP(0x7):
return ~(dst & src);
case BOP(0x8):
return dst & src;
case BOP(0x9):
return ~(dst ^ src);
case BOP(0xa):
return dst;
case BOP(0xb):
return dst | ~src;
case BOP(0xc):
return src;
case BOP(0xd):
return ~dst | src;
case BOP(0xe):
return dst | src;
case BOP(0xf):
return ~0;
default:
break;
}
return 0;
}
static uint16_t
dither(mystique_t *mystique, int r, int g, int b, int x, int y)
{
switch (mystique->dwgreg.dither) {
case DITHER_NONE_555:
return (b >> 3) | ((g >> 3) << 5) | ((r >> 3) << 10);
case DITHER_NONE_565:
return (b >> 3) | ((g >> 2) << 5) | ((r >> 3) << 11);
case DITHER_555:
return dither5[b][y][x] | (dither5[g][y][x] << 5) | (dither5[r][y][x] << 10);
case DITHER_565:
default:
return dither5[b][y][x] | (dither6[g][y][x] << 5) | (dither5[r][y][x] << 11);
}
}
static uint32_t
blit_idump_idump(mystique_t *mystique)
{
svga_t *svga = &mystique->svga;
uint64_t val64 = 0;
uint32_t val = 0;
int count = 0;
switch (mystique->dwgreg.dwgctrl_running & DWGCTRL_ATYPE_MASK) {
case DWGCTRL_ATYPE_RPL:
switch (mystique->dwgreg.dwgctrl_running & DWGCTRL_BLTMOD_MASK) {
case DWGCTRL_BLTMOD_BU32RGB:
case DWGCTRL_BLTMOD_BFCOL:
switch (mystique->maccess_running & MACCESS_PWIDTH_MASK) {
case MACCESS_PWIDTH_8:
while (count < 32) {
val |= (svga->vram[mystique->dwgreg.src_addr & mystique->vram_mask] << count);
if (mystique->dwgreg.src_addr == mystique->dwgreg.ar[0]) {
mystique->dwgreg.ar[0] += mystique->dwgreg.ar[5];
mystique->dwgreg.ar[3] += mystique->dwgreg.ar[5];
mystique->dwgreg.src_addr = mystique->dwgreg.ar[3];
} else
mystique->dwgreg.src_addr++;
if (mystique->dwgreg.xdst == mystique->dwgreg.fxright) {
mystique->dwgreg.xdst = mystique->dwgreg.fxleft;
mystique->dwgreg.length_cur--;
if (!mystique->dwgreg.length_cur) {
mystique->busy = 0;
mystique->blitter_complete_refcount++;
break;
}
break;
} else
mystique->dwgreg.xdst = (mystique->dwgreg.xdst + 1) & 0xffff;
count += 8;
}
break;
case MACCESS_PWIDTH_16:
while (count < 32) {
val |= (((uint16_t *) svga->vram)[mystique->dwgreg.src_addr & mystique->vram_mask_w] << count);
if (mystique->dwgreg.src_addr == mystique->dwgreg.ar[0]) {
mystique->dwgreg.ar[0] += mystique->dwgreg.ar[5];
mystique->dwgreg.ar[3] += mystique->dwgreg.ar[5];
mystique->dwgreg.src_addr = mystique->dwgreg.ar[3];
} else
mystique->dwgreg.src_addr++;
if (mystique->dwgreg.xdst == mystique->dwgreg.fxright) {
mystique->dwgreg.xdst = mystique->dwgreg.fxleft;
mystique->dwgreg.length_cur--;
if (!mystique->dwgreg.length_cur) {
mystique->busy = 0;
mystique->blitter_complete_refcount++;
break;
}
break;
} else
mystique->dwgreg.xdst = (mystique->dwgreg.xdst + 1) & 0xffff;
count += 16;
}
break;
case MACCESS_PWIDTH_24:
if (mystique->dwgreg.idump_end_of_line) {
mystique->dwgreg.idump_end_of_line = 0;
val = mystique->dwgreg.iload_rem_data;
mystique->dwgreg.iload_rem_count = 0;
mystique->dwgreg.iload_rem_data = 0;
if (!mystique->dwgreg.length_cur) {
mystique->busy = 0;
mystique->blitter_complete_refcount++;
}
break;
}
count += mystique->dwgreg.iload_rem_count;
val64 = mystique->dwgreg.iload_rem_data;
while ((count < 32) && !mystique->dwgreg.idump_end_of_line) {
val64 |= (uint64_t) ((*(uint32_t *) &svga->vram[(mystique->dwgreg.src_addr * 3) & mystique->vram_mask]) & 0xffffff) << count;
if (mystique->dwgreg.src_addr == mystique->dwgreg.ar[0]) {
mystique->dwgreg.ar[0] += mystique->dwgreg.ar[5];
mystique->dwgreg.ar[3] += mystique->dwgreg.ar[5];
mystique->dwgreg.src_addr = mystique->dwgreg.ar[3];
} else
mystique->dwgreg.src_addr++;
if (mystique->dwgreg.xdst == mystique->dwgreg.fxright) {
mystique->dwgreg.xdst = mystique->dwgreg.fxleft;
mystique->dwgreg.length_cur--;
if (!mystique->dwgreg.length_cur) {
if (count > 8)
mystique->dwgreg.idump_end_of_line = 1;
else {
count = 32;
mystique->busy = 0;
mystique->blitter_complete_refcount++;
}
break;
}
if (!(mystique->dwgreg.dwgctrl_running & DWGCTRL_LINEAR)) {
if (count > 8)
mystique->dwgreg.idump_end_of_line = 1;
else {
count = 32;
break;
}
}
} else
mystique->dwgreg.xdst = (mystique->dwgreg.xdst + 1) & 0xffff;
count += 24;
}
if (count > 32)
mystique->dwgreg.iload_rem_count = count - 32;
else
mystique->dwgreg.iload_rem_count = 0;
mystique->dwgreg.iload_rem_data = (uint32_t) (val64 >> 32);
val = val64 & 0xffffffff;
break;
case MACCESS_PWIDTH_32:
val = (((uint32_t *) svga->vram)[mystique->dwgreg.src_addr & mystique->vram_mask_l] << count);
if (mystique->dwgreg.src_addr == mystique->dwgreg.ar[0]) {
mystique->dwgreg.ar[0] += mystique->dwgreg.ar[5];
mystique->dwgreg.ar[3] += mystique->dwgreg.ar[5];
mystique->dwgreg.src_addr = mystique->dwgreg.ar[3];
} else
mystique->dwgreg.src_addr++;
if (mystique->dwgreg.xdst == mystique->dwgreg.fxright) {
mystique->dwgreg.xdst = mystique->dwgreg.fxleft;
mystique->dwgreg.length_cur--;
if (!mystique->dwgreg.length_cur) {
mystique->busy = 0;
mystique->blitter_complete_refcount++;
break;
}
break;
} else
mystique->dwgreg.xdst = (mystique->dwgreg.xdst + 1) & 0xffff;
break;
default:
fatal("IDUMP DWGCTRL_BLTMOD_BU32RGB %x %08x\n", mystique->maccess_running & MACCESS_PWIDTH_MASK, mystique->maccess_running);
}
break;
default:
fatal("IDUMP DWGCTRL_ATYPE_RPL %08x %08x\n", mystique->dwgreg.dwgctrl_running & DWGCTRL_BLTMOD_MASK, mystique->dwgreg.dwgctrl_running);
break;
}
break;
default:
fatal("Unknown IDUMP atype %03x %08x\n", mystique->dwgreg.dwgctrl_running & DWGCTRL_ATYPE_MASK, mystique->dwgreg.dwgctrl_running);
}
return val;
}
static uint32_t
blit_idump_read(mystique_t *mystique)
{
uint32_t ret = 0xffffffff;
switch (mystique->dwgreg.dwgctrl_running & DWGCTRL_OPCODE_MASK) {
case DWGCTRL_OPCODE_IDUMP:
ret = blit_idump_idump(mystique);
break;
default:
/* pclog("blit_idump_read: bad opcode %08x\n", mystique->dwgreg.dwgctrl_running); */
break;
}
return ret;
}
static void
blit_fbitblt(mystique_t *mystique)
{
svga_t *svga = &mystique->svga;
uint32_t src_addr;
int x_dir = mystique->dwgreg.sgn.scanleft ? -1 : 1;
int16_t x_start = mystique->dwgreg.sgn.scanleft ? mystique->dwgreg.fxright : mystique->dwgreg.fxleft;
int16_t x_end = mystique->dwgreg.sgn.scanleft ? mystique->dwgreg.fxleft : mystique->dwgreg.fxright;
src_addr = mystique->dwgreg.ar[3];
for (uint16_t y = 0; y < mystique->dwgreg.length; y++) {
int16_t x = x_start;
while (1) {
if (x >= mystique->dwgreg.cxleft && x <= mystique->dwgreg.cxright && mystique->dwgreg.ydst_lin >= mystique->dwgreg.ytop && mystique->dwgreg.ydst_lin <= mystique->dwgreg.ybot) {
uint32_t src;
uint32_t old_dst;
switch (mystique->maccess_running & MACCESS_PWIDTH_MASK) {
case MACCESS_PWIDTH_8:
src = svga->vram[src_addr & mystique->vram_mask];
svga->vram[(mystique->dwgreg.ydst_lin + x) & mystique->vram_mask] = src;
svga->changedvram[((mystique->dwgreg.ydst_lin + x) & mystique->vram_mask) >> 12] = changeframecount;
break;
case MACCESS_PWIDTH_16:
src = ((uint16_t *) svga->vram)[src_addr & mystique->vram_mask_w];
((uint16_t *) svga->vram)[(mystique->dwgreg.ydst_lin + x) & mystique->vram_mask_w] = src;
svga->changedvram[((mystique->dwgreg.ydst_lin + x) & mystique->vram_mask_w) >> 11] = changeframecount;
break;
case MACCESS_PWIDTH_24:
src = *(uint32_t *) &svga->vram[(src_addr * 3) & mystique->vram_mask];
old_dst = *(uint32_t *) &svga->vram[((mystique->dwgreg.ydst_lin + x) * 3) & mystique->vram_mask];
*(uint32_t *) &svga->vram[((mystique->dwgreg.ydst_lin + x) * 3) & mystique->vram_mask] = (src & 0xffffff) | (old_dst & 0xff000000);
svga->changedvram[(((mystique->dwgreg.ydst_lin + x) * 3) & mystique->vram_mask) >> 12] = changeframecount;
break;
case MACCESS_PWIDTH_32:
src = ((uint32_t *) svga->vram)[src_addr & mystique->vram_mask_l];
((uint32_t *) svga->vram)[(mystique->dwgreg.ydst_lin + x) & mystique->vram_mask_l] = src;
svga->changedvram[((mystique->dwgreg.ydst_lin + x) & mystique->vram_mask_l) >> 10] = changeframecount;
break;
default:
fatal("BITBLT RPL BFCOL PWIDTH %x %08x\n", mystique->maccess_running & MACCESS_PWIDTH_MASK, mystique->dwgreg.dwgctrl_running);
}
}
if (src_addr == mystique->dwgreg.ar[0]) {
mystique->dwgreg.ar[0] += mystique->dwgreg.ar[5];
mystique->dwgreg.ar[3] += mystique->dwgreg.ar[5];
src_addr = mystique->dwgreg.ar[3];
break;
} else
src_addr += x_dir;
if (x != x_end)
x += x_dir;
else
break;
}
if (mystique->dwgreg.sgn.sdy)
mystique->dwgreg.ydst_lin -= (mystique->dwgreg.pitch & PITCH_MASK);
else
mystique->dwgreg.ydst_lin += (mystique->dwgreg.pitch & PITCH_MASK);
}
mystique->blitter_complete_refcount++;
}
static uint8_t
dither_24_to_8(int r, int g, int b)
{
return ((b >> 6) & 3) | (((g >> 5) & 7) << 2) | (((r >> 5) & 7) << 5);
}
static void
blit_iload_iload(mystique_t *mystique, uint32_t data, int size)
{
svga_t *svga = &mystique->svga;
uint32_t src;
uint32_t dst;
uint32_t dst2;
uint64_t data64;
int min_size = 8;
uint32_t bltckey = mystique->dwgreg.fcol;
uint32_t bltcmsk = mystique->dwgreg.bcol;
const int transc = mystique->dwgreg.dwgctrl_running & DWGCTRL_TRANSC;
const int trans_sel = (mystique->dwgreg.dwgctrl_running & DWGCTRL_TRANS_MASK) >> DWGCTRL_TRANS_SHIFT;
uint8_t const *const trans = &trans_masks[trans_sel][(mystique->dwgreg.selline & 3) * 4];
uint32_t data_mask = 1;
switch (mystique->maccess_running & MACCESS_PWIDTH_MASK) {
case MACCESS_PWIDTH_8:
bltckey &= 0xff;
bltcmsk &= 0xff;
break;
case MACCESS_PWIDTH_16:
bltckey &= 0xffff;
bltcmsk &= 0xffff;
break;
}
mystique->dwgreg.words++;
switch (mystique->dwgreg.dwgctrl_running & DWGCTRL_ATYPE_MASK) {
case DWGCTRL_ATYPE_RPL:
if (mystique->maccess_running & MACCESS_TLUTLOAD) {
while ((mystique->dwgreg.length_cur > 0) && (size >= 16)) {
uint16_t src = data & 0xffff;
mystique->lut[mystique->dwgreg.ydst & 0xff].r = (src >> 11) << 3;
mystique->lut[mystique->dwgreg.ydst & 0xff].g = ((src >> 5) & 0x3f) << 2;
mystique->lut[mystique->dwgreg.ydst & 0xff].b = (src & 0x1f) << 3;
mystique->dwgreg.ydst++;
mystique->dwgreg.length_cur--;
data >>= 16;
size -= 16;
}
if (!mystique->dwgreg.length_cur) {
mystique->busy = 0;
mystique->blitter_complete_refcount++;
}
break;
}
case DWGCTRL_ATYPE_RSTR:
case DWGCTRL_ATYPE_BLK:
switch (mystique->dwgreg.dwgctrl_running & DWGCTRL_BLTMOD_MASK) {
case DWGCTRL_BLTMOD_BFCOL:
size += mystique->dwgreg.iload_rem_count;
data64 = mystique->dwgreg.iload_rem_data | ((uint64_t) data << mystique->dwgreg.iload_rem_count);
switch (mystique->maccess_running & MACCESS_PWIDTH_MASK) {
case MACCESS_PWIDTH_8:
min_size = 8;
break;
case MACCESS_PWIDTH_16:
min_size = 16;
break;
case MACCESS_PWIDTH_24:
min_size = 24;
break;
case MACCESS_PWIDTH_32:
min_size = 32;
break;
default:
break;
}
while (size >= min_size) {
int draw = (!transc || (data & bltcmsk) != bltckey) && trans[mystique->dwgreg.xdst & 3];
switch (mystique->maccess_running & MACCESS_PWIDTH_MASK) {
case MACCESS_PWIDTH_8:
if (mystique->dwgreg.xdst >= mystique->dwgreg.cxleft && mystique->dwgreg.xdst <= mystique->dwgreg.cxright && mystique->dwgreg.ydst_lin >= mystique->dwgreg.ytop && mystique->dwgreg.ydst_lin <= mystique->dwgreg.ybot && draw) {
dst = svga->vram[(mystique->dwgreg.ydst_lin + mystique->dwgreg.xdst) & mystique->vram_mask];
dst = bitop(data & 0xff, dst, mystique->dwgreg.dwgctrl_running);
svga->vram[(mystique->dwgreg.ydst_lin + mystique->dwgreg.xdst) & mystique->vram_mask] = dst;
svga->changedvram[((mystique->dwgreg.ydst_lin + mystique->dwgreg.xdst) & mystique->vram_mask) >> 12] = changeframecount;
}
data >>= 8;
size -= 8;
break;
case MACCESS_PWIDTH_16:
if (mystique->dwgreg.xdst >= mystique->dwgreg.cxleft && mystique->dwgreg.xdst <= mystique->dwgreg.cxright && mystique->dwgreg.ydst_lin >= mystique->dwgreg.ytop && mystique->dwgreg.ydst_lin <= mystique->dwgreg.ybot && draw) {
dst = ((uint16_t *) svga->vram)[(mystique->dwgreg.ydst_lin + mystique->dwgreg.xdst) & mystique->vram_mask_w];
dst = bitop(data & 0xffff, dst, mystique->dwgreg.dwgctrl_running);
((uint16_t *) svga->vram)[(mystique->dwgreg.ydst_lin + mystique->dwgreg.xdst) & mystique->vram_mask_w] = dst;
svga->changedvram[((mystique->dwgreg.ydst_lin + mystique->dwgreg.xdst) & mystique->vram_mask_w) >> 11] = changeframecount;
}
data >>= 16;
size -= 16;
break;
case MACCESS_PWIDTH_24:
if (mystique->dwgreg.xdst >= mystique->dwgreg.cxleft && mystique->dwgreg.xdst <= mystique->dwgreg.cxright && mystique->dwgreg.ydst_lin >= mystique->dwgreg.ytop && mystique->dwgreg.ydst_lin <= mystique->dwgreg.ybot) {
uint32_t old_dst = *((uint32_t *) &svga->vram[((mystique->dwgreg.ydst_lin + mystique->dwgreg.xdst) * 3) & mystique->vram_mask]);
dst = bitop(data64, old_dst, mystique->dwgreg.dwgctrl_running);
*((uint32_t *) &svga->vram[((mystique->dwgreg.ydst_lin + mystique->dwgreg.xdst) * 3) & mystique->vram_mask]) = (dst & 0xffffff) | (old_dst & 0xff000000);
svga->changedvram[(((mystique->dwgreg.ydst_lin + mystique->dwgreg.xdst) * 3) & mystique->vram_mask) >> 12] = changeframecount;
}
data64 >>= 24;
size -= 24;
break;
case MACCESS_PWIDTH_32:
if (mystique->dwgreg.xdst >= mystique->dwgreg.cxleft && mystique->dwgreg.xdst <= mystique->dwgreg.cxright && mystique->dwgreg.ydst_lin >= mystique->dwgreg.ytop && mystique->dwgreg.ydst_lin <= mystique->dwgreg.ybot && draw) {
dst = ((uint32_t *) svga->vram)[(mystique->dwgreg.ydst_lin + mystique->dwgreg.xdst) & mystique->vram_mask_l];
dst = bitop(data, dst, mystique->dwgreg.dwgctrl_running);
((uint32_t *) svga->vram)[(mystique->dwgreg.ydst_lin + mystique->dwgreg.xdst) & mystique->vram_mask_l] = dst;
svga->changedvram[((mystique->dwgreg.ydst_lin + mystique->dwgreg.xdst) & mystique->vram_mask_l) >> 10] = changeframecount;
}
size = 0;
break;
default:
fatal("ILOAD RSTR/RPL BFCOL pwidth %08x\n", mystique->maccess_running & MACCESS_PWIDTH_MASK);
}
if (mystique->dwgreg.xdst == mystique->dwgreg.fxright) {
mystique->dwgreg.xdst = mystique->dwgreg.fxleft;
mystique->dwgreg.ydst_lin += (mystique->dwgreg.pitch & PITCH_MASK);
mystique->dwgreg.selline = (mystique->dwgreg.selline + 1) & 7;
mystique->dwgreg.length_cur--;
if (!mystique->dwgreg.length_cur) {
mystique->busy = 0;
mystique->blitter_complete_refcount++;
break;
}
data64 = 0;
size = 0;
break;
} else
mystique->dwgreg.xdst = (mystique->dwgreg.xdst + 1) & 0xffff;
}
mystique->dwgreg.iload_rem_count = size;
mystique->dwgreg.iload_rem_data = data64;
break;
case DWGCTRL_BLTMOD_BMONOWF:
data = (data >> 24) | ((data & 0x00ff0000) >> 8) | ((data & 0x0000ff00) << 8) | (data << 24);
data_mask = (1 << 31);
case DWGCTRL_BLTMOD_BMONOLEF:
while (size) {
if (mystique->dwgreg.xdst >= mystique->dwgreg.cxleft && mystique->dwgreg.xdst <= mystique->dwgreg.cxright && mystique->dwgreg.ydst_lin >= mystique->dwgreg.ytop && mystique->dwgreg.ydst_lin <= mystique->dwgreg.ybot && ((data & data_mask) || !(mystique->dwgreg.dwgctrl_running & DWGCTRL_TRANSC)) && trans[mystique->dwgreg.xdst & 3]) {
uint32_t old_dst;
src = (data & data_mask) ? mystique->dwgreg.fcol : mystique->dwgreg.bcol;
switch (mystique->maccess_running & MACCESS_PWIDTH_MASK) {
case MACCESS_PWIDTH_8:
dst = svga->vram[(mystique->dwgreg.ydst_lin + mystique->dwgreg.xdst) & mystique->vram_mask];
dst = bitop(src, dst, mystique->dwgreg.dwgctrl_running);
svga->vram[(mystique->dwgreg.ydst_lin + mystique->dwgreg.xdst) & mystique->vram_mask] = dst;
svga->changedvram[((mystique->dwgreg.ydst_lin + mystique->dwgreg.xdst) & mystique->vram_mask) >> 12] = changeframecount;
break;
case MACCESS_PWIDTH_16:
dst = ((uint16_t *) svga->vram)[(mystique->dwgreg.ydst_lin + mystique->dwgreg.xdst) & mystique->vram_mask_w];
dst = bitop(src, dst, mystique->dwgreg.dwgctrl_running);
((uint16_t *) svga->vram)[(mystique->dwgreg.ydst_lin + mystique->dwgreg.xdst) & mystique->vram_mask_w] = dst;
svga->changedvram[((mystique->dwgreg.ydst_lin + mystique->dwgreg.xdst) & mystique->vram_mask_w) >> 11] = changeframecount;
break;
case MACCESS_PWIDTH_24:
old_dst = *(uint32_t *) &svga->vram[((mystique->dwgreg.ydst_lin + mystique->dwgreg.xdst) * 3) & mystique->vram_mask];
dst = bitop(src, old_dst, mystique->dwgreg.dwgctrl_running);
*(uint32_t *) &svga->vram[((mystique->dwgreg.ydst_lin + mystique->dwgreg.xdst) * 3) & mystique->vram_mask] = (dst & 0xffffff) | (old_dst & 0xff000000);
svga->changedvram[(((mystique->dwgreg.ydst_lin + mystique->dwgreg.xdst) * 3) & mystique->vram_mask) >> 12] = changeframecount;
break;
case MACCESS_PWIDTH_32:
dst = ((uint32_t *) svga->vram)[(mystique->dwgreg.ydst_lin + mystique->dwgreg.xdst) & mystique->vram_mask_l];
dst = bitop(src, dst, mystique->dwgreg.dwgctrl_running);
((uint32_t *) svga->vram)[(mystique->dwgreg.ydst_lin + mystique->dwgreg.xdst) & mystique->vram_mask_l] = dst;
svga->changedvram[((mystique->dwgreg.ydst_lin + mystique->dwgreg.xdst) & mystique->vram_mask_l) >> 10] = changeframecount;
break;
default:
fatal("ILOAD RSTR/RPL BMONOWF pwidth %08x\n", mystique->maccess_running & MACCESS_PWIDTH_MASK);
}
}
if (mystique->dwgreg.xdst == mystique->dwgreg.fxright) {
mystique->dwgreg.xdst = mystique->dwgreg.fxleft;
mystique->dwgreg.ydst_lin += (mystique->dwgreg.pitch & PITCH_MASK);
mystique->dwgreg.length_cur--;
if (!mystique->dwgreg.length_cur) {
mystique->busy = 0;
mystique->blitter_complete_refcount++;
break;
}
if (!(mystique->dwgreg.dwgctrl_running & DWGCTRL_LINEAR))
break;
} else
mystique->dwgreg.xdst = (mystique->dwgreg.xdst + 1) & 0xffff;
if (data_mask == 1)
data >>= 1;
else
data <<= 1;
size--;
}
break;
case DWGCTRL_BLTMOD_BU24RGB:
size += mystique->dwgreg.iload_rem_count;
data64 = mystique->dwgreg.iload_rem_data | ((uint64_t) data << mystique->dwgreg.iload_rem_count);
while (size >= 24) {
if (mystique->dwgreg.xdst >= mystique->dwgreg.cxleft && mystique->dwgreg.xdst <= mystique->dwgreg.cxright && mystique->dwgreg.ydst_lin >= mystique->dwgreg.ytop && mystique->dwgreg.ydst_lin <= mystique->dwgreg.ybot) {
switch (mystique->maccess_running & MACCESS_PWIDTH_MASK) {
case MACCESS_PWIDTH_16:
{
dst = ((uint16_t *) svga->vram)[(mystique->dwgreg.ydst_lin + mystique->dwgreg.xdst) & mystique->vram_mask_w];
dst = bitop(dither(mystique, (data64 >> 16) & 0xFF, (data64 >> 8) & 0xFF, data64 & 0xFF, mystique->dwgreg.xdst & 1, mystique->dwgreg.selline & 1), dst, mystique->dwgreg.dwgctrl_running);
((uint16_t *) svga->vram)[(mystique->dwgreg.ydst_lin + mystique->dwgreg.xdst) & mystique->vram_mask_w] = dst;
svga->changedvram[((mystique->dwgreg.ydst_lin + mystique->dwgreg.xdst) & mystique->vram_mask_w) >> 11] = changeframecount;
break;
}
case MACCESS_PWIDTH_8:
{
dst = ((uint8_t *) svga->vram)[(mystique->dwgreg.ydst_lin + mystique->dwgreg.xdst) & mystique->vram_mask];
dst = bitop(dither_24_to_8((data64 >> 16) & 0xFF, (data64 >> 8) & 0xFF, data64 & 0xFF), dst, mystique->dwgreg.dwgctrl_running);
((uint8_t *) svga->vram)[(mystique->dwgreg.ydst_lin + mystique->dwgreg.xdst) & mystique->vram_mask] = dst;
svga->changedvram[((mystique->dwgreg.ydst_lin + mystique->dwgreg.xdst) & mystique->vram_mask) >> 12] = changeframecount;
break;
}
case MACCESS_PWIDTH_32:
dst = ((uint32_t *) svga->vram)[(mystique->dwgreg.ydst_lin + mystique->dwgreg.xdst) & mystique->vram_mask_l];
dst = bitop(data64 & 0xffffff, dst, mystique->dwgreg.dwgctrl_running);
((uint32_t *) svga->vram)[(mystique->dwgreg.ydst_lin + mystique->dwgreg.xdst) & mystique->vram_mask_l] = dst;
svga->changedvram[((mystique->dwgreg.ydst_lin + mystique->dwgreg.xdst) & mystique->vram_mask_l) >> 10] = changeframecount;
break;
default:
fatal("ILOAD RSTR/RPL BU24RGB pwidth %08x\n", mystique->maccess_running & MACCESS_PWIDTH_MASK);
}
}
data64 >>= 24;
size -= 24;
if (mystique->dwgreg.xdst == mystique->dwgreg.fxright) {
mystique->dwgreg.xdst = mystique->dwgreg.fxleft;
mystique->dwgreg.ydst_lin += (mystique->dwgreg.pitch & PITCH_MASK);
mystique->dwgreg.length_cur--;
if (!mystique->dwgreg.length_cur) {
mystique->busy = 0;
mystique->blitter_complete_refcount++;
break;
}
data64 = 0;
size = 0;
break;
} else
mystique->dwgreg.xdst = (mystique->dwgreg.xdst + 1) & 0xffff;
}
mystique->dwgreg.iload_rem_count = size;
mystique->dwgreg.iload_rem_data = data64;
break;
case DWGCTRL_BLTMOD_BU32RGB:
size += mystique->dwgreg.iload_rem_count;
data64 = mystique->dwgreg.iload_rem_data | ((uint64_t) data << mystique->dwgreg.iload_rem_count);
while (size >= 32) {
int draw = (!transc || (data & bltcmsk) != bltckey) && trans[mystique->dwgreg.xdst & 3];
if (mystique->dwgreg.xdst >= mystique->dwgreg.cxleft && mystique->dwgreg.xdst <= mystique->dwgreg.cxright && mystique->dwgreg.ydst_lin >= mystique->dwgreg.ytop && mystique->dwgreg.ydst_lin <= mystique->dwgreg.ybot && draw) {
switch (mystique->maccess_running & MACCESS_PWIDTH_MASK) {
case MACCESS_PWIDTH_16:
{
dst = ((uint16_t *) svga->vram)[(mystique->dwgreg.ydst_lin + mystique->dwgreg.xdst) & mystique->vram_mask_w];
dst = bitop(dither(mystique, (data64 >> 16) & 0xFF, (data64 >> 8) & 0xFF, data64 & 0xFF, mystique->dwgreg.xdst & 1, mystique->dwgreg.selline & 1), dst, mystique->dwgreg.dwgctrl_running);
((uint16_t *) svga->vram)[(mystique->dwgreg.ydst_lin + mystique->dwgreg.xdst) & mystique->vram_mask_w] = dst;
svga->changedvram[((mystique->dwgreg.ydst_lin + mystique->dwgreg.xdst) & mystique->vram_mask_w) >> 11] = changeframecount;
break;
}
case MACCESS_PWIDTH_8:
{
dst = ((uint8_t *) svga->vram)[(mystique->dwgreg.ydst_lin + mystique->dwgreg.xdst) & mystique->vram_mask];
dst = bitop(dither_24_to_8((data64 >> 16) & 0xFF, (data64 >> 8) & 0xFF, data64 & 0xFF), dst, mystique->dwgreg.dwgctrl_running);
((uint8_t *) svga->vram)[(mystique->dwgreg.ydst_lin + mystique->dwgreg.xdst) & mystique->vram_mask] = dst;
svga->changedvram[((mystique->dwgreg.ydst_lin + mystique->dwgreg.xdst) & mystique->vram_mask) >> 12] = changeframecount;
break;
}
default: {
dst = ((uint32_t *) svga->vram)[(mystique->dwgreg.ydst_lin + mystique->dwgreg.xdst) & mystique->vram_mask_l];
dst = bitop(data, dst, mystique->dwgreg.dwgctrl_running);
((uint32_t *) svga->vram)[(mystique->dwgreg.ydst_lin + mystique->dwgreg.xdst) & mystique->vram_mask_l] = dst;
svga->changedvram[((mystique->dwgreg.ydst_lin + mystique->dwgreg.xdst) & mystique->vram_mask_l) >> 10] = changeframecount;
break;
}
}
}
size = 0;
if (mystique->dwgreg.xdst == mystique->dwgreg.fxright) {
mystique->dwgreg.xdst = mystique->dwgreg.fxleft;
mystique->dwgreg.ydst_lin += (mystique->dwgreg.pitch & PITCH_MASK);
mystique->dwgreg.selline = (mystique->dwgreg.selline + 1) & 7;
mystique->dwgreg.length_cur--;
if (!mystique->dwgreg.length_cur) {
mystique->busy = 0;
mystique->blitter_complete_refcount++;
break;
}
data64 = 0;
size = 0;
break;
} else
mystique->dwgreg.xdst = (mystique->dwgreg.xdst + 1) & 0xffff;
}
mystique->dwgreg.iload_rem_count = size;
mystique->dwgreg.iload_rem_data = data64;
break;
case DWGCTRL_BLTMOD_BU32BGR:
size += mystique->dwgreg.iload_rem_count;
while (size >= 32) {
if (mystique->dwgreg.xdst >= mystique->dwgreg.cxleft && mystique->dwgreg.xdst <= mystique->dwgreg.cxright && mystique->dwgreg.ydst_lin >= mystique->dwgreg.ytop && mystique->dwgreg.ydst_lin <= mystique->dwgreg.ybot) {
switch (mystique->maccess_running & MACCESS_PWIDTH_MASK) {
case MACCESS_PWIDTH_32:
dst = ((uint32_t *) svga->vram)[(mystique->dwgreg.ydst_lin + mystique->dwgreg.xdst) & mystique->vram_mask_l];
dst2 = ((dst >> 16) & 0xff) | (dst & 0xff00) | ((dst & 0xff) << 16); /* BGR to RGB */
dst = bitop(data, dst2, mystique->dwgreg.dwgctrl_running);
((uint32_t *) svga->vram)[(mystique->dwgreg.ydst_lin + mystique->dwgreg.xdst) & mystique->vram_mask_l] = dst;
svga->changedvram[((mystique->dwgreg.ydst_lin + mystique->dwgreg.xdst) & mystique->vram_mask_l) >> 10] = changeframecount;
break;
default:
fatal("ILOAD RSTR/RPL BU32RGB pwidth %08x\n", mystique->maccess_running & MACCESS_PWIDTH_MASK);
}
}
size = 0;
if (mystique->dwgreg.xdst == mystique->dwgreg.fxright) {
mystique->dwgreg.xdst = mystique->dwgreg.fxleft;
mystique->dwgreg.ydst_lin += (mystique->dwgreg.pitch & PITCH_MASK);
mystique->dwgreg.length_cur--;
if (!mystique->dwgreg.length_cur) {
mystique->busy = 0;
mystique->blitter_complete_refcount++;
break;
}
break;
} else
mystique->dwgreg.xdst = (mystique->dwgreg.xdst + 1) & 0xffff;
}
mystique->dwgreg.iload_rem_count = size;
break;
default:
fatal("ILOAD DWGCTRL_ATYPE_RPL\n");
break;
}
break;
default:
fatal("Unknown ILOAD iload atype %03x %08x\n", mystique->dwgreg.dwgctrl_running & DWGCTRL_ATYPE_MASK, mystique->dwgreg.dwgctrl_running);
}
}
#define CLAMP(x) \
do { \
if ((x) & ~0xff) \
x = ((x) < 0) ? 0 : 0xff; \
} while (0)
static void
blit_iload_iload_scale(mystique_t *mystique, uint32_t data, int size)
{
svga_t *svga = &mystique->svga;
uint64_t data64 = 0;
int y0;
int y1;
int u;
int v;
int dR;
int dG;
int dB;
int r0;
int g0;
int b0;
int r1;
int g1;
int b1;
switch (mystique->dwgreg.dwgctrl_running & DWGCTRL_BLTMOD_MASK) {
case DWGCTRL_BLTMOD_BUYUV:
y0 = (298 * ((int) (data & 0xff) - 16)) >> 8;
u = ((data >> 8) & 0xff) - 0x80;
y1 = (298 * ((int) ((data >> 16) & 0xff) - 16)) >> 8;
v = ((data >> 24) & 0xff) - 0x80;
dR = (309 * v) >> 8;
dG = (100 * u + 208 * v) >> 8;
dB = (516 * u) >> 8;
r0 = y0 + dR;
CLAMP(r0);
g0 = y0 - dG;
CLAMP(g0);
b0 = y0 + dB;
CLAMP(b0);
r1 = y1 + dR;
CLAMP(r1);
g1 = y1 - dG;
CLAMP(g1);
b1 = y1 + dB;
CLAMP(b1);
switch (mystique->maccess_running & MACCESS_PWIDTH_MASK) {
case MACCESS_PWIDTH_16:
data = (b0 >> 3) | ((g0 >> 2) << 5) | ((r0 >> 3) << 11);
data |= (((b1 >> 3) | ((g1 >> 2) << 5) | ((r1 >> 3) << 11)) << 16);
size = 32;
break;
case MACCESS_PWIDTH_32:
data64 = b0 | (g0 << 8) | (r0 << 16);
data64 |= ((uint64_t) b0 << 32) | ((uint64_t) g0 << 40) | ((uint64_t) r0 << 48);
size = 64;
break;
default:
fatal("blit_iload_iload_scale BUYUV pwidth %i\n", mystique->maccess_running & MACCESS_PWIDTH_MASK);
}
break;
default:
fatal("blit_iload_iload_scale bltmod %08x\n", mystique->dwgreg.dwgctrl_running & DWGCTRL_BLTMOD_MASK);
break;
}
switch (mystique->maccess_running & MACCESS_PWIDTH_MASK) {
case MACCESS_PWIDTH_16:
while (size >= 16) {
if (mystique->dwgreg.xdst >= mystique->dwgreg.cxleft && mystique->dwgreg.xdst <= mystique->dwgreg.cxright && mystique->dwgreg.ydst_lin >= mystique->dwgreg.ytop && mystique->dwgreg.ydst_lin <= mystique->dwgreg.ybot) {
uint16_t dst = ((uint16_t *) svga->vram)[(mystique->dwgreg.ydst_lin + mystique->dwgreg.xdst) & mystique->vram_mask_w];
dst = bitop(data & 0xffff, dst, mystique->dwgreg.dwgctrl_running);
((uint16_t *) svga->vram)[(mystique->dwgreg.ydst_lin + mystique->dwgreg.xdst) & mystique->vram_mask_w] = dst;
svga->changedvram[((mystique->dwgreg.ydst_lin + mystique->dwgreg.xdst) & mystique->vram_mask_w) >> 11] = changeframecount;
}
mystique->dwgreg.ar[6] += mystique->dwgreg.ar[2];
if ((int32_t) mystique->dwgreg.ar[6] >= 0) {
mystique->dwgreg.ar[6] -= (mystique->dwgreg.fxright - mystique->dwgreg.fxleft);
data >>= 16;
size -= 16;
}
mystique->dwgreg.xdst = (mystique->dwgreg.xdst + 1) & 0xffff;
if (mystique->dwgreg.xdst == mystique->dwgreg.fxright) {
mystique->dwgreg.xdst = mystique->dwgreg.fxleft;
mystique->dwgreg.ydst_lin += (mystique->dwgreg.pitch & PITCH_MASK);
mystique->dwgreg.ar[0] += mystique->dwgreg.ar[5];
mystique->dwgreg.ar[3] += mystique->dwgreg.ar[5];
mystique->dwgreg.ar[6] = mystique->dwgreg.ar[2] - (mystique->dwgreg.fxright - mystique->dwgreg.fxleft);
mystique->dwgreg.length_cur--;
if (!mystique->dwgreg.length_cur) {
mystique->busy = 0;
mystique->blitter_complete_refcount++;
break;
}
break;
}
}
break;
case MACCESS_PWIDTH_32:
while (size >= 32) {
if (mystique->dwgreg.xdst >= mystique->dwgreg.cxleft && mystique->dwgreg.xdst <= mystique->dwgreg.cxright && mystique->dwgreg.ydst_lin >= mystique->dwgreg.ytop && mystique->dwgreg.ydst_lin <= mystique->dwgreg.ybot) {
uint32_t dst = ((uint32_t *) svga->vram)[(mystique->dwgreg.ydst_lin + mystique->dwgreg.xdst) & mystique->vram_mask_l];
dst = bitop(data64, dst, mystique->dwgreg.dwgctrl_running);
((uint32_t *) svga->vram)[(mystique->dwgreg.ydst_lin + mystique->dwgreg.xdst) & mystique->vram_mask_l] = dst;
svga->changedvram[((mystique->dwgreg.ydst_lin + mystique->dwgreg.xdst) & mystique->vram_mask_l) >> 10] = changeframecount;
}
mystique->dwgreg.ar[6] += mystique->dwgreg.ar[2];
if ((int32_t) mystique->dwgreg.ar[6] >= 0) {
mystique->dwgreg.ar[6] -= (mystique->dwgreg.fxright - mystique->dwgreg.fxleft);
data64 >>= 32;
size -= 32;
}
mystique->dwgreg.xdst = (mystique->dwgreg.xdst + 1) & 0xffff;
if (mystique->dwgreg.xdst == mystique->dwgreg.fxright) {
mystique->dwgreg.xdst = mystique->dwgreg.fxleft;
mystique->dwgreg.ydst_lin += (mystique->dwgreg.pitch & PITCH_MASK);
mystique->dwgreg.ar[0] += mystique->dwgreg.ar[5];
mystique->dwgreg.ar[3] += mystique->dwgreg.ar[5];
mystique->dwgreg.ar[6] = mystique->dwgreg.ar[2] - (mystique->dwgreg.fxright - mystique->dwgreg.fxleft);
mystique->dwgreg.length_cur--;
if (!mystique->dwgreg.length_cur) {
mystique->busy = 0;
mystique->blitter_complete_refcount++;
break;
}
break;
}
}
break;
default:
fatal("ILOAD_SCALE pwidth %08x\n", mystique->maccess_running & MACCESS_PWIDTH_MASK);
}
}
static void
blit_iload_iload_high(mystique_t *mystique, uint32_t data, int size)
{
svga_t *svga = &mystique->svga;
uint32_t out_data;
int y0;
int y1;
int u;
int v;
int dR;
int dG;
int dB;
int r = 0;
int g = 0;
int b = 0;
int next_r = 0;
int next_g = 0;
int next_b = 0;
switch (mystique->dwgreg.dwgctrl_running & DWGCTRL_BLTMOD_MASK) {
case DWGCTRL_BLTMOD_BUYUV:
y0 = (298 * ((int) (data & 0xff) - 16)) >> 8;
u = ((data >> 8) & 0xff) - 0x80;
y1 = (298 * ((int) ((data >> 16) & 0xff) - 16)) >> 8;
v = ((data >> 24) & 0xff) - 0x80;
dR = (309 * v) >> 8;
dG = (100 * u + 208 * v) >> 8;
dB = (516 * u) >> 8;
r = y0 + dR;
CLAMP(r);
g = y0 - dG;
CLAMP(g);
b = y0 + dB;
CLAMP(b);
next_r = y1 + dR;
CLAMP(next_r);
next_g = y1 - dG;
CLAMP(next_g);
next_b = y1 + dB;
CLAMP(next_b);
size = 32;
break;
case DWGCTRL_BLTMOD_BU32BGR:
r = ((data >> 16) & 0xff);
CLAMP(r);
g = ((data >> 8) & 0xff);
CLAMP(g);
b = (data & 0xff);
CLAMP(b);
next_r = r;
next_g = g;
next_b = b;
size = 32;
break;
default:
fatal("blit_iload_iload_high bltmod %08x\n", mystique->dwgreg.dwgctrl_running & DWGCTRL_BLTMOD_MASK);
break;
}
while (size >= 16) {
if (mystique->dwgreg.xdst >= mystique->dwgreg.cxleft && mystique->dwgreg.xdst <= mystique->dwgreg.cxright && mystique->dwgreg.ydst_lin >= mystique->dwgreg.ytop && mystique->dwgreg.ydst_lin <= mystique->dwgreg.ybot) {
uint32_t dst;
int f1 = (mystique->dwgreg.ar[6] >> 12) & 0xf;
int f0 = 0x10 - f1;
int out_r = ((mystique->dwgreg.lastpix_r * f0) + (r * f1)) >> 4;
int out_g = ((mystique->dwgreg.lastpix_g * f0) + (g * f1)) >> 4;
int out_b = ((mystique->dwgreg.lastpix_b * f0) + (b * f1)) >> 4;
switch (mystique->maccess_running & MACCESS_PWIDTH_MASK) {
case MACCESS_PWIDTH_16:
out_data = (out_b >> 3) | ((out_g >> 2) << 5) | ((out_r >> 3) << 11);
dst = ((uint16_t *) svga->vram)[(mystique->dwgreg.ydst_lin + mystique->dwgreg.xdst) & mystique->vram_mask_w];
dst = bitop(out_data, dst, mystique->dwgreg.dwgctrl_running);
((uint16_t *) svga->vram)[(mystique->dwgreg.ydst_lin + mystique->dwgreg.xdst) & mystique->vram_mask_w] = dst;
svga->changedvram[((mystique->dwgreg.ydst_lin + mystique->dwgreg.xdst) & mystique->vram_mask_w) >> 11] = changeframecount;
break;
case MACCESS_PWIDTH_32:
out_data = out_b | (out_g << 8) | (out_r << 16);
dst = ((uint32_t *) svga->vram)[(mystique->dwgreg.ydst_lin + mystique->dwgreg.xdst) & mystique->vram_mask_l];
dst = bitop(out_data, dst, mystique->dwgreg.dwgctrl_running);
((uint32_t *) svga->vram)[(mystique->dwgreg.ydst_lin + mystique->dwgreg.xdst) & mystique->vram_mask_l] = dst;
svga->changedvram[((mystique->dwgreg.ydst_lin + mystique->dwgreg.xdst) & mystique->vram_mask_l) >> 10] = changeframecount;
break;
default:
fatal("ILOAD_SCALE_HIGH RSTR/RPL BUYUV pwidth %08x\n", mystique->maccess_running & MACCESS_PWIDTH_MASK);
}
}
mystique->dwgreg.ar[6] += mystique->dwgreg.ar[2];
if ((int32_t) mystique->dwgreg.ar[6] >= 0) {
mystique->dwgreg.ar[6] -= 65536;
size -= 16;
mystique->dwgreg.lastpix_r = r;
mystique->dwgreg.lastpix_g = g;
mystique->dwgreg.lastpix_b = b;
r = next_r;
g = next_g;
b = next_b;
}
if (mystique->dwgreg.xdst == mystique->dwgreg.fxright) {
mystique->dwgreg.xdst = mystique->dwgreg.fxleft;
mystique->dwgreg.ydst_lin += (mystique->dwgreg.pitch & PITCH_MASK);
mystique->dwgreg.ar[6] = mystique->dwgreg.ar[2] - (mystique->dwgreg.fxright - mystique->dwgreg.fxleft);
mystique->dwgreg.lastpix_r = 0;
mystique->dwgreg.lastpix_g = 0;
mystique->dwgreg.lastpix_b = 0;
mystique->dwgreg.length_cur--;
if (!mystique->dwgreg.length_cur) {
mystique->busy = 0;
mystique->blitter_complete_refcount++;
break;
}
break;
} else
mystique->dwgreg.xdst = (mystique->dwgreg.xdst + 1) & 0xffff;
}
}
static void
blit_iload_iload_highv(mystique_t *mystique, uint32_t data, UNUSED(int size))
{
const uint8_t *src0;
uint8_t *src1;
switch (mystique->dwgreg.dwgctrl_running & DWGCTRL_BLTMOD_MASK) {
case DWGCTRL_BLTMOD_BUYUV:
if (!mystique->dwgreg.highv_line) {
mystique->dwgreg.highv_data = data;
mystique->dwgreg.highv_line = 1;
return;
}
mystique->dwgreg.highv_line = 0;
src0 = (uint8_t *) &mystique->dwgreg.highv_data;
src1 = (uint8_t *) &data;
src1[0] = ((src0[0] * mystique->dwgreg.beta) + (src1[0] * (16 - mystique->dwgreg.beta))) >> 4;
src1[1] = ((src0[1] * mystique->dwgreg.beta) + (src1[1] * (16 - mystique->dwgreg.beta))) >> 4;
src1[2] = ((src0[2] * mystique->dwgreg.beta) + (src1[2] * (16 - mystique->dwgreg.beta))) >> 4;
src1[3] = ((src0[3] * mystique->dwgreg.beta) + (src1[3] * (16 - mystique->dwgreg.beta))) >> 4;
blit_iload_iload_high(mystique, data, 32);
break;
default:
fatal("blit_iload_iload_highv bltmod %08x\n", mystique->dwgreg.dwgctrl_running & DWGCTRL_BLTMOD_MASK);
break;
}
}
static void
blit_iload_write(mystique_t *mystique, uint32_t data, int size)
{
switch (mystique->dwgreg.dwgctrl_running & DWGCTRL_OPCODE_MASK) {
case DWGCTRL_OPCODE_ILOAD:
blit_iload_iload(mystique, data, size);
break;
case DWGCTRL_OPCODE_ILOAD_SCALE:
blit_iload_iload_scale(mystique, data, size);
break;
case DWGCTRL_OPCODE_ILOAD_HIGH:
blit_iload_iload_high(mystique, data, size);
break;
case DWGCTRL_OPCODE_ILOAD_HIGHV:
blit_iload_iload_highv(mystique, data, size);
break;
default:
fatal("blit_iload_write: bad opcode %08x\n", mystique->dwgreg.dwgctrl_running);
}
}
static int
z_check(uint16_t z, uint16_t old_z, uint32_t z_mode) // mystique->dwgreg.dwgctrl & DWGCTRL_ZMODE_MASK)
{
switch (z_mode) {
case DWGCTRL_ZMODE_ZE:
return (z == old_z);
case DWGCTRL_ZMODE_ZNE:
return (z != old_z);
case DWGCTRL_ZMODE_ZLT:
return (z < old_z);
case DWGCTRL_ZMODE_ZLTE:
return (z <= old_z);
case DWGCTRL_ZMODE_ZGT:
return (z > old_z);
case DWGCTRL_ZMODE_ZGTE:
return (z >= old_z);
case DWGCTRL_ZMODE_NOZCMP:
default:
return 1;
}
}
static int
z_check_32(uint32_t z, uint32_t old_z, uint32_t z_mode) // mystique->dwgreg.dwgctrl & DWGCTRL_ZMODE_MASK)
{
switch (z_mode) {
case DWGCTRL_ZMODE_ZE:
return (z == old_z);
case DWGCTRL_ZMODE_ZNE:
return (z != old_z);
case DWGCTRL_ZMODE_ZLT:
return (z < old_z);
case DWGCTRL_ZMODE_ZLTE:
return (z <= old_z);
case DWGCTRL_ZMODE_ZGT:
return (z > old_z);
case DWGCTRL_ZMODE_ZGTE:
return (z >= old_z);
case DWGCTRL_ZMODE_NOZCMP:
default:
return 1;
}
}
static void
blit_line(mystique_t *mystique, int closed, int autoline)
{
svga_t *svga = &mystique->svga;
uint32_t src = 0;
uint32_t dst;
uint32_t old_dst;
int x = mystique->dwgreg.xdst;
int z_write;
int pattern_x, pattern_y;
bool transc = !!(mystique->dwgreg.dwgctrl_running & DWGCTRL_TRANSC);
switch (mystique->dwgreg.dwgctrl_running & DWGCTRL_ATYPE_MASK) {
case DWGCTRL_ATYPE_RSTR:
case DWGCTRL_ATYPE_RPL:
while (mystique->dwgreg.length >= 0) {
if (x >= mystique->dwgreg.cxleft && x <= mystique->dwgreg.cxright && mystique->dwgreg.ydst_lin >= mystique->dwgreg.ytop && mystique->dwgreg.ydst_lin <= mystique->dwgreg.ybot) {
pattern_y = ((mystique->dwgreg.funcnt % (mystique->dwgreg.stylelen + 1)) >> 4) & 0x7;
pattern_x = (mystique->dwgreg.funcnt % (mystique->dwgreg.stylelen + 1)) & 0xf;
if (!transc || (transc && (mystique->dwgreg.pattern[pattern_y][pattern_x])))
switch (mystique->maccess_running & MACCESS_PWIDTH_MASK) {
case MACCESS_PWIDTH_8:
src = mystique->dwgreg.pattern[pattern_y][pattern_x] ? mystique->dwgreg.fcol : mystique->dwgreg.bcol;
dst = svga->vram[(mystique->dwgreg.ydst_lin + x) & mystique->vram_mask];
dst = bitop(src, dst, mystique->dwgreg.dwgctrl_running);
if (closed) {
svga->vram[(mystique->dwgreg.ydst_lin + x) & mystique->vram_mask] = dst;
svga->changedvram[((mystique->dwgreg.ydst_lin + x) & mystique->vram_mask) >> 12] = changeframecount;
} else if (!closed && (mystique->dwgreg.length > 0) && ((mystique->dwgreg.err > 0) || (mystique->dwgreg.err < 0)) && !autoline) {
svga->vram[(mystique->dwgreg.ydst_lin + x) & mystique->vram_mask] = dst;
svga->changedvram[((mystique->dwgreg.ydst_lin + x) & mystique->vram_mask) >> 12] = changeframecount;
} else if (!closed && (mystique->dwgreg.length > 0) && autoline) {
svga->vram[(mystique->dwgreg.ydst_lin + x) & mystique->vram_mask] = dst;
svga->changedvram[((mystique->dwgreg.ydst_lin + x) & mystique->vram_mask) >> 12] = changeframecount;
}
break;
case MACCESS_PWIDTH_16:
src = mystique->dwgreg.pattern[pattern_y][pattern_x] ? mystique->dwgreg.fcol : mystique->dwgreg.bcol;
dst = ((uint16_t *) svga->vram)[(mystique->dwgreg.ydst_lin + x) & mystique->vram_mask_w];
dst = bitop(src, dst, mystique->dwgreg.dwgctrl_running);
if (closed) {
((uint16_t *) svga->vram)[(mystique->dwgreg.ydst_lin + x) & mystique->vram_mask_w] = dst;
svga->changedvram[((mystique->dwgreg.ydst_lin + x) & mystique->vram_mask_w) >> 11] = changeframecount;
} else if (!closed && (mystique->dwgreg.length > 0) && ((mystique->dwgreg.err > 0) || (mystique->dwgreg.err < 0)) && !autoline) {
((uint16_t *) svga->vram)[(mystique->dwgreg.ydst_lin + x) & mystique->vram_mask_w] = dst;
svga->changedvram[((mystique->dwgreg.ydst_lin + x) & mystique->vram_mask_w) >> 11] = changeframecount;
} else if (!closed && (mystique->dwgreg.length > 0) && autoline) {
((uint16_t *) svga->vram)[(mystique->dwgreg.ydst_lin + x) & mystique->vram_mask_w] = dst;
svga->changedvram[((mystique->dwgreg.ydst_lin + x) & mystique->vram_mask_w) >> 11] = changeframecount;
}
break;
case MACCESS_PWIDTH_24:
src = mystique->dwgreg.pattern[pattern_y][pattern_x] ? mystique->dwgreg.fcol : mystique->dwgreg.bcol;
old_dst = *(uint32_t *) &svga->vram[((mystique->dwgreg.ydst_lin + x) * 3) & mystique->vram_mask];
dst = bitop(src, old_dst, mystique->dwgreg.dwgctrl_running);
if (closed) {
*(uint32_t *) &svga->vram[((mystique->dwgreg.ydst_lin + x) * 3) & mystique->vram_mask] = (dst & 0xffffff) | (old_dst & 0xff000000);
svga->changedvram[(((mystique->dwgreg.ydst_lin + x) * 3) & mystique->vram_mask) >> 12] = changeframecount;
} else if (!closed && (mystique->dwgreg.length > 0) && ((mystique->dwgreg.err > 0) || (mystique->dwgreg.err < 0)) && !autoline) {
*(uint32_t *) &svga->vram[((mystique->dwgreg.ydst_lin + x) * 3) & mystique->vram_mask] = (dst & 0xffffff) | (old_dst & 0xff000000);
svga->changedvram[(((mystique->dwgreg.ydst_lin + x) * 3) & mystique->vram_mask) >> 12] = changeframecount;
} else if (!closed && (mystique->dwgreg.length > 0) && autoline) {
*(uint32_t *) &svga->vram[((mystique->dwgreg.ydst_lin + x) * 3) & mystique->vram_mask] = (dst & 0xffffff) | (old_dst & 0xff000000);
svga->changedvram[(((mystique->dwgreg.ydst_lin + x) * 3) & mystique->vram_mask) >> 12] = changeframecount;
}
break;
case MACCESS_PWIDTH_32:
src = mystique->dwgreg.pattern[pattern_y][pattern_x] ? mystique->dwgreg.fcol : mystique->dwgreg.bcol;
dst = ((uint32_t *) svga->vram)[(mystique->dwgreg.ydst_lin + x) & mystique->vram_mask_l];
dst = bitop(src, dst, mystique->dwgreg.dwgctrl_running);
if (closed) {
((uint32_t *) svga->vram)[(mystique->dwgreg.ydst_lin + x) & mystique->vram_mask_l] = dst;
svga->changedvram[((mystique->dwgreg.ydst_lin + x) & mystique->vram_mask_l) >> 10] = changeframecount;
} else if (!closed && (mystique->dwgreg.length > 0) && ((mystique->dwgreg.err > 0) || (mystique->dwgreg.err < 0)) && !autoline) {
((uint32_t *) svga->vram)[(mystique->dwgreg.ydst_lin + x) & mystique->vram_mask_l] = dst;
svga->changedvram[((mystique->dwgreg.ydst_lin + x) & mystique->vram_mask_l) >> 10] = changeframecount;
} else if (!closed && (mystique->dwgreg.length > 0) && autoline) {
((uint32_t *) svga->vram)[(mystique->dwgreg.ydst_lin + x) & mystique->vram_mask_l] = dst;
svga->changedvram[((mystique->dwgreg.ydst_lin + x) & mystique->vram_mask_l) >> 10] = changeframecount;
}
break;
default:
fatal("LINE RSTR/RPL PWIDTH %x %08x\n", mystique->maccess_running & MACCESS_PWIDTH_MASK, mystique->dwgreg.dwgctrl_running);
}
}
if (!mystique->dwgreg.length)
break;
if (mystique->dwgreg.sgn.sdydxl)
x += (mystique->dwgreg.sgn.sdxl ? -1 : 1);
else {
mystique->dwgreg.ydst += (mystique->dwgreg.sgn.sdy ? -1 : 1);
mystique->dwgreg.ydst &= 0x7fffff;
mystique->dwgreg.ydst_lin += (mystique->dwgreg.sgn.sdy ? -(mystique->dwgreg.pitch & PITCH_MASK) : (mystique->dwgreg.pitch & PITCH_MASK));
}
if (mystique->dwgreg.err >= 0) {
mystique->dwgreg.err += mystique->dwgreg.k2;
if (mystique->dwgreg.sgn.sdydxl) {
mystique->dwgreg.ydst += (mystique->dwgreg.sgn.sdy ? -1 : 1);
mystique->dwgreg.ydst &= 0x7fffff;
mystique->dwgreg.ydst_lin += (mystique->dwgreg.sgn.sdy ? -(mystique->dwgreg.pitch & PITCH_MASK) : (mystique->dwgreg.pitch & PITCH_MASK));
} else
x += (mystique->dwgreg.sgn.sdxl ? -1 : 1);
} else
mystique->dwgreg.err += mystique->dwgreg.k1;
mystique->dwgreg.length--;
mystique->dwgreg.funcnt--;
}
break;
case DWGCTRL_ATYPE_I:
case DWGCTRL_ATYPE_ZI:
z_write = ((mystique->dwgreg.dwgctrl_running & DWGCTRL_ATYPE_MASK) == DWGCTRL_ATYPE_ZI);
while (mystique->dwgreg.length > 0) {
if (x >= mystique->dwgreg.cxleft && x <= mystique->dwgreg.cxright && mystique->dwgreg.ydst_lin >= mystique->dwgreg.ytop && mystique->dwgreg.ydst_lin <= mystique->dwgreg.ybot) {
bool z_check_pass = false;
if (mystique->maccess_running & MACCESS_ZWIDTH) {
uint32_t z = (mystique->dwgreg.extended_dr[0] & (1ull << 47ull)) ? 0 : (mystique->dwgreg.extended_dr[0] >> 15ull);
uint32_t *z_p = (uint32_t *) &svga->vram[(mystique->dwgreg.ydst_lin * 4 + mystique->dwgreg.zorg) & mystique->vram_mask];
uint32_t old_z = z_p[x];
z_check_pass = z_check_32(z, old_z, mystique->dwgreg.dwgctrl_running & DWGCTRL_ZMODE_MASK);
if (z_write && z_check_pass) {
z_p[x] = z;
}
} else {
uint16_t z = ((int32_t) mystique->dwgreg.dr[0] < 0) ? 0 : (mystique->dwgreg.dr[0] >> 15);
uint16_t *z_p = (uint16_t *) &svga->vram[(mystique->dwgreg.ydst_lin * 2 + mystique->dwgreg.zorg) & mystique->vram_mask];
uint16_t old_z = z_p[x];
z_check_pass = z_check(z, old_z, mystique->dwgreg.dwgctrl_running & DWGCTRL_ZMODE_MASK);
if (z_write && z_check_pass) {
z_p[x] = z;
}
}
if (z_check_pass) {
int r = 0;
int g = 0;
int b = 0;
switch (mystique->maccess_running & MACCESS_PWIDTH_MASK) {
case MACCESS_PWIDTH_8:
if (!(mystique->dwgreg.dr[4] & (1 << 23)))
r = (mystique->dwgreg.dr[4] >> 20) & 0x7;
if (!(mystique->dwgreg.dr[8] & (1 << 23)))
g = (mystique->dwgreg.dr[8] >> 20) & 0x7;
if (!(mystique->dwgreg.dr[12] & (1 << 23)))
b = (mystique->dwgreg.dr[12] >> 21) & 0x3;
dst = (r << 5) | (g << 2) | b;
((uint8_t *) svga->vram)[(mystique->dwgreg.ydst_lin + x) & mystique->vram_mask] = dst;
svga->changedvram[((mystique->dwgreg.ydst_lin + x) & mystique->vram_mask) >> 12] = changeframecount;
break;
case MACCESS_PWIDTH_16:
if (!(mystique->dwgreg.dr[4] & (1 << 23)))
r = (mystique->dwgreg.dr[4] >> 18) & 0x1f;
if (!(mystique->dwgreg.dr[8] & (1 << 23)))
g = (mystique->dwgreg.dr[8] >> 17) & 0x3f;
if (!(mystique->dwgreg.dr[12] & (1 << 23)))
b = (mystique->dwgreg.dr[12] >> 18) & 0x1f;
dst = (r << 11) | (g << 5) | b;
((uint16_t *) svga->vram)[(mystique->dwgreg.ydst_lin + x) & mystique->vram_mask_w] = dst;
svga->changedvram[((mystique->dwgreg.ydst_lin + x) & mystique->vram_mask_w) >> 11] = changeframecount;
break;
case MACCESS_PWIDTH_24:
old_dst = *(uint32_t *) &svga->vram[((mystique->dwgreg.ydst_lin + x) * 3) & mystique->vram_mask];
if (!(mystique->dwgreg.dr[4] & (1 << 23)))
r = (mystique->dwgreg.dr[4] >> 15) & 0xff;
if (!(mystique->dwgreg.dr[8] & (1 << 23)))
g = (mystique->dwgreg.dr[8] >> 15) & 0xff;
if (!(mystique->dwgreg.dr[12] & (1 << 23)))
b = (mystique->dwgreg.dr[12] >> 15) & 0xff;
dst = (r << 16) | (g << 8) | b;
((uint32_t *) svga->vram)[((mystique->dwgreg.ydst_lin + x) * 3) & mystique->vram_mask] = dst | (old_dst & 0xFF000000);
svga->changedvram[(((mystique->dwgreg.ydst_lin + x) * 3) & mystique->vram_mask) >> 12] = changeframecount;
break;
case MACCESS_PWIDTH_32:
if (!(mystique->dwgreg.dr[4] & (1 << 23)))
r = (mystique->dwgreg.dr[4] >> 15) & 0xff;
if (!(mystique->dwgreg.dr[8] & (1 << 23)))
g = (mystique->dwgreg.dr[8] >> 15) & 0xff;
if (!(mystique->dwgreg.dr[12] & (1 << 23)))
b = (mystique->dwgreg.dr[12] >> 15) & 0xff;
dst = (r << 16) | (g << 8) | b;
((uint32_t *) svga->vram)[(mystique->dwgreg.ydst_lin + x) & mystique->vram_mask_l] = dst;
svga->changedvram[((mystique->dwgreg.ydst_lin + x) & mystique->vram_mask_l) >> 10] = changeframecount;
break;
default:
fatal("LINE I/ZI PWIDTH %x %08x\n", mystique->maccess_running & MACCESS_PWIDTH_MASK, mystique->dwgreg.dwgctrl_running);
}
}
}
if (mystique->dwgreg.sgn.sdydxl)
x += (mystique->dwgreg.sgn.sdxl ? -1 : 1);
else
mystique->dwgreg.ydst_lin += (mystique->dwgreg.sgn.sdy ? -(mystique->dwgreg.pitch & PITCH_MASK) : (mystique->dwgreg.pitch & PITCH_MASK));
if (mystique->maccess_running & MACCESS_ZWIDTH) {
mystique->dwgreg.extended_dr[0] += mystique->dwgreg.extended_dr[2];
mystique->dwgreg.dr[0] = (mystique->dwgreg.extended_dr[0] >> 16) & 0xFFFFFFFF;
} else {
mystique->dwgreg.dr[0] += mystique->dwgreg.dr[2];
mystique->dwgreg.extended_dr[0] = (mystique->dwgreg.extended_dr[0] & ~0xFFFFull) | ((uint64_t)mystique->dwgreg.dr[0] << 16ull);
}
mystique->dwgreg.dr[4] += mystique->dwgreg.dr[6];
mystique->dwgreg.dr[8] += mystique->dwgreg.dr[10];
mystique->dwgreg.dr[12] += mystique->dwgreg.dr[14];
if (mystique->dwgreg.err >= 0) {
mystique->dwgreg.err += mystique->dwgreg.k2;
if (mystique->dwgreg.sgn.sdydxl)
mystique->dwgreg.ydst_lin += (mystique->dwgreg.sgn.sdy ? -(mystique->dwgreg.pitch & PITCH_MASK) : (mystique->dwgreg.pitch & PITCH_MASK));
else
x += (mystique->dwgreg.sgn.sdxl ? -1 : 1);
if (mystique->maccess_running & MACCESS_ZWIDTH) {
mystique->dwgreg.extended_dr[0] += mystique->dwgreg.extended_dr[3];
mystique->dwgreg.dr[0] = (mystique->dwgreg.extended_dr[0] >> 16) & 0xFFFFFFFF;
} else {
mystique->dwgreg.dr[0] += mystique->dwgreg.dr[3];
mystique->dwgreg.extended_dr[0] = (mystique->dwgreg.extended_dr[0] & ~0xFFFFull) | ((uint64_t)mystique->dwgreg.dr[0] << 16ull);
}
mystique->dwgreg.dr[4] += mystique->dwgreg.dr[7];
mystique->dwgreg.dr[8] += mystique->dwgreg.dr[11];
mystique->dwgreg.dr[12] += mystique->dwgreg.dr[15];
} else
mystique->dwgreg.err += mystique->dwgreg.k1;
mystique->dwgreg.length--;
}
break;
default:
#if 0
pclog("Unknown atype %03x %08x LINE\n", mystique->dwgreg.dwgctrl_running & DWGCTRL_ATYPE_MASK, mystique->dwgreg.dwgctrl_running);
#endif
break;
}
mystique->blitter_complete_refcount++;
}
static void
blit_line_start(mystique_t *mystique, int closed, int autoline)
{
int start_x = (int32_t) mystique->dwgreg.ar[5];
int start_y = (int32_t) mystique->dwgreg.ar[6];
int end_x = (int32_t) mystique->dwgreg.ar[0];
int end_y = (int32_t) mystique->dwgreg.ar[2];
int dx = end_x - start_x;
int dy = end_y - start_y;
if (autoline) {
if (ABS(dx) > ABS(dy)) {
mystique->dwgreg.sgn.sdydxl = 1;
mystique->dwgreg.k1 = 2 * ABS(dy);
mystique->dwgreg.err = 2 * ABS(dy) - ABS(dx) - ((start_y > end_y) ? 1 : 0);
mystique->dwgreg.k2 = 2 * ABS(dy) - 2 * ABS(dx);
mystique->dwgreg.length = ABS(end_x - start_x);
} else {
mystique->dwgreg.sgn.sdydxl = 0;
mystique->dwgreg.k1 = 2 * ABS(dx);
mystique->dwgreg.err = 2 * ABS(dx) - ABS(dy) - ((start_y > end_y) ? 1 : 0);
mystique->dwgreg.k2 = 2 * ABS(dx) - 2 * ABS(dy);
mystique->dwgreg.length = ABS(end_y - start_y);
}
mystique->dwgreg.sgn.sdxl = (start_x > end_x) ? 1 : 0;
mystique->dwgreg.sgn.sdy = (start_y > end_y) ? 1 : 0;
} else {
mystique->dwgreg.k1 = (int32_t) mystique->dwgreg.ar[0];
mystique->dwgreg.err = (int32_t) mystique->dwgreg.ar[1];
mystique->dwgreg.k2 = (int32_t) mystique->dwgreg.ar[2];
}
blit_line(mystique, closed, autoline);
if (autoline) {
mystique->dwgreg.ar[5] = end_x;
mystique->dwgreg.xdst = end_x;
mystique->dwgreg.ar[6] = end_y;
mystique->dwgreg.ydst = end_y;
mystique->dwgreg.ydst_lin = ((int32_t) (int16_t) mystique->dwgreg.ydst * (mystique->dwgreg.pitch & PITCH_MASK)) + mystique->dwgreg.ydstorg;
}
}
static void
blit_trap(mystique_t *mystique)
{
svga_t *svga = &mystique->svga;
uint64_t z_back_32;
uint32_t z_back;
uint32_t r_back;
uint32_t g_back;
uint32_t b_back;
int z_write;
int y;
int err_l = (int32_t)mystique->dwgreg.ar[1];
int err_r = (int32_t)mystique->dwgreg.ar[4];
const int trans_sel = (mystique->dwgreg.dwgctrl_running & DWGCTRL_TRANS_MASK) >> DWGCTRL_TRANS_SHIFT;
switch (mystique->dwgreg.dwgctrl_running & DWGCTRL_ATYPE_MASK) {
case DWGCTRL_ATYPE_BLK:
case DWGCTRL_ATYPE_RPL:
for (y = 0; y < mystique->dwgreg.length; y++) {
uint8_t const *const trans = &trans_masks[trans_sel][(mystique->dwgreg.selline & 3) * 4];
int16_t x_l = mystique->dwgreg.fxleft & 0xffff;
int16_t x_r = mystique->dwgreg.fxright & 0xffff;
int yoff = (mystique->dwgreg.yoff + mystique->dwgreg.ydst) & 7;
int len;
if (x_l > x_r)
len = x_l - x_r;
else
len = x_r - x_l;
while (len > 0) {
if (x_l >= mystique->dwgreg.cxleft && x_l <= mystique->dwgreg.cxright && mystique->dwgreg.ydst_lin >= mystique->dwgreg.ytop && mystique->dwgreg.ydst_lin <= mystique->dwgreg.ybot && trans[x_l & 3]) {
int xoff = (mystique->dwgreg.xoff + (x_l & 7)) & 15;
int pattern = mystique->dwgreg.pattern[yoff][xoff];
uint32_t dst;
switch (mystique->maccess_running & MACCESS_PWIDTH_MASK) {
case MACCESS_PWIDTH_8:
svga->vram[(mystique->dwgreg.ydst_lin + x_l) & mystique->vram_mask] = (pattern ? mystique->dwgreg.fcol : mystique->dwgreg.bcol) & 0xff;
svga->changedvram[((mystique->dwgreg.ydst_lin + x_l) & mystique->vram_mask) >> 12] = changeframecount;
break;
case MACCESS_PWIDTH_16:
((uint16_t *) svga->vram)[(mystique->dwgreg.ydst_lin + x_l) & mystique->vram_mask_w] = (pattern ? mystique->dwgreg.fcol : mystique->dwgreg.bcol) & 0xffff;
svga->changedvram[((mystique->dwgreg.ydst_lin + x_l) & mystique->vram_mask_w) >> 11] = changeframecount;
break;
case MACCESS_PWIDTH_24:
dst = *(uint32_t *) (&svga->vram[((mystique->dwgreg.ydst_lin + x_l) * 3) & mystique->vram_mask]) & 0xff000000;
*(uint32_t *) (&svga->vram[((mystique->dwgreg.ydst_lin + x_l) * 3) & mystique->vram_mask]) = ((pattern ? mystique->dwgreg.fcol : mystique->dwgreg.bcol) & 0xffffff) | dst;
svga->changedvram[(((mystique->dwgreg.ydst_lin + x_l) * 3) & mystique->vram_mask) >> 12] = changeframecount;
break;
case MACCESS_PWIDTH_32:
((uint32_t *) svga->vram)[(mystique->dwgreg.ydst_lin + x_l) & mystique->vram_mask_l] = pattern ? mystique->dwgreg.fcol : mystique->dwgreg.bcol;
svga->changedvram[((mystique->dwgreg.ydst_lin + x_l) & mystique->vram_mask_l) >> 10] = changeframecount;
break;
default:
fatal("TRAP BLK/RPL PWIDTH %x %08x\n", mystique->maccess_running & MACCESS_PWIDTH_MASK, mystique->dwgreg.dwgctrl_running);
}
}
len--;
x_l++;
}
while ((err_l < 0) && mystique->dwgreg.ar[0]) {
err_l += mystique->dwgreg.ar[0];
mystique->dwgreg.fxleft += (mystique->dwgreg.sgn.sdxl ? -1 : 1);
}
err_l += mystique->dwgreg.ar[2];
while ((err_r < 0) && mystique->dwgreg.ar[6]) {
err_r += mystique->dwgreg.ar[6];
mystique->dwgreg.fxright += (mystique->dwgreg.sgn.sdxr ? -1 : 1);
}
err_r += mystique->dwgreg.ar[5];
mystique->dwgreg.ydst++;
mystique->dwgreg.ydst &= 0x7fffff;
mystique->dwgreg.ydst_lin += (mystique->dwgreg.pitch & PITCH_MASK);
mystique->dwgreg.selline = (mystique->dwgreg.selline + 1) & 7;
}
break;
case DWGCTRL_ATYPE_RSTR:
for (y = 0; y < mystique->dwgreg.length; y++) {
uint8_t const *const trans = &trans_masks[trans_sel][(mystique->dwgreg.selline & 3) * 4];
int16_t x_l = mystique->dwgreg.fxleft & 0xffff;
int16_t x_r = mystique->dwgreg.fxright & 0xffff;
int yoff = (mystique->dwgreg.yoff + mystique->dwgreg.ydst) & 7;
int len;
if (x_l > x_r)
len = x_l - x_r;
else
len = x_r - x_l;
while (len > 0) {
if (x_l >= mystique->dwgreg.cxleft && x_l <= mystique->dwgreg.cxright && mystique->dwgreg.ydst_lin >= mystique->dwgreg.ytop && mystique->dwgreg.ydst_lin <= mystique->dwgreg.ybot && trans[x_l & 3]) {
int xoff = (mystique->dwgreg.xoff + (x_l & 7)) & 15;
int pattern = mystique->dwgreg.pattern[yoff][xoff];
uint32_t src = pattern ? mystique->dwgreg.fcol : mystique->dwgreg.bcol;
uint32_t dst;
uint32_t old_dst;
switch (mystique->maccess_running & MACCESS_PWIDTH_MASK) {
case MACCESS_PWIDTH_8:
dst = svga->vram[(mystique->dwgreg.ydst_lin + x_l) & mystique->vram_mask];
dst = bitop(src, dst, mystique->dwgreg.dwgctrl_running);
svga->vram[(mystique->dwgreg.ydst_lin + x_l) & mystique->vram_mask] = dst;
svga->changedvram[((mystique->dwgreg.ydst_lin + x_l) & mystique->vram_mask) >> 12] = changeframecount;
break;
case MACCESS_PWIDTH_16:
dst = ((uint16_t *) svga->vram)[(mystique->dwgreg.ydst_lin + x_l) & mystique->vram_mask_w];
dst = bitop(src, dst, mystique->dwgreg.dwgctrl_running);
((uint16_t *) svga->vram)[(mystique->dwgreg.ydst_lin + x_l) & mystique->vram_mask_w] = dst;
svga->changedvram[((mystique->dwgreg.ydst_lin + x_l) & mystique->vram_mask_w) >> 11] = changeframecount;
break;
case MACCESS_PWIDTH_24:
old_dst = *(uint32_t *) &svga->vram[((mystique->dwgreg.ydst_lin + x_l) * 3) & mystique->vram_mask];
dst = bitop(src, old_dst, mystique->dwgreg.dwgctrl_running);
*(uint32_t *) &svga->vram[((mystique->dwgreg.ydst_lin + x_l) * 3) & mystique->vram_mask] = (dst & 0xffffff) | (old_dst & 0xff000000);
svga->changedvram[(((mystique->dwgreg.ydst_lin + x_l) * 3) & mystique->vram_mask) >> 12] = changeframecount;
break;
case MACCESS_PWIDTH_32:
dst = ((uint32_t *) svga->vram)[(mystique->dwgreg.ydst_lin + x_l) & mystique->vram_mask_l];
dst = bitop(src, dst, mystique->dwgreg.dwgctrl_running);
((uint32_t *) svga->vram)[(mystique->dwgreg.ydst_lin + x_l) & mystique->vram_mask_l] = dst;
svga->changedvram[((mystique->dwgreg.ydst_lin + x_l) & mystique->vram_mask_l) >> 10] = changeframecount;
break;
default:
fatal("TRAP RSTR PWIDTH %x %08x\n", mystique->maccess_running & MACCESS_PWIDTH_MASK, mystique->dwgreg.dwgctrl_running);
}
}
x_l++;
len--;
}
while ((err_l < 0) && mystique->dwgreg.ar[0]) {
err_l += mystique->dwgreg.ar[0];
mystique->dwgreg.fxleft += (mystique->dwgreg.sgn.sdxl ? -1 : 1);
}
err_l += mystique->dwgreg.ar[2];
while ((err_r < 0) && mystique->dwgreg.ar[6]) {
err_r += mystique->dwgreg.ar[6];
mystique->dwgreg.fxright += (mystique->dwgreg.sgn.sdxr ? -1 : 1);
}
err_r += mystique->dwgreg.ar[5];
mystique->dwgreg.ydst++;
mystique->dwgreg.ydst &= 0x7fffff;
mystique->dwgreg.ydst_lin += (mystique->dwgreg.pitch & PITCH_MASK);
mystique->dwgreg.selline = (mystique->dwgreg.selline + 1) & 7;
}
break;
case DWGCTRL_ATYPE_I:
case DWGCTRL_ATYPE_ZI:
z_write = ((mystique->dwgreg.dwgctrl_running & DWGCTRL_ATYPE_MASK) == DWGCTRL_ATYPE_ZI);
for (y = 0; y < mystique->dwgreg.length; y++) {
uint8_t const *const trans = &trans_masks[trans_sel][(mystique->dwgreg.selline & 3) * 4];
uint16_t *z_p = (uint16_t *) &svga->vram[(mystique->dwgreg.ydst_lin * ((mystique->maccess_running & MACCESS_ZWIDTH) ? 4 : 2) + mystique->dwgreg.zorg) & mystique->vram_mask];
int16_t x_l = mystique->dwgreg.fxleft & 0xffff;
int16_t x_r = mystique->dwgreg.fxright & 0xffff;
int16_t old_x_l = x_l;
int dx;
z_back_32 = mystique->dwgreg.extended_dr[0];
z_back = mystique->dwgreg.dr[0];
r_back = mystique->dwgreg.dr[4];
g_back = mystique->dwgreg.dr[8];
b_back = mystique->dwgreg.dr[12];
while (x_l != x_r) {
if (x_l >= mystique->dwgreg.cxleft && x_l <= mystique->dwgreg.cxright && mystique->dwgreg.ydst_lin >= mystique->dwgreg.ytop && mystique->dwgreg.ydst_lin <= mystique->dwgreg.ybot && trans[x_l & 3]) {
bool z_check_pass = false;
if (mystique->maccess_running & MACCESS_ZWIDTH) {
uint32_t z = (mystique->dwgreg.extended_dr[0] & (1ull << 47ull)) ? 0 : (mystique->dwgreg.extended_dr[0] >> 15ull);
uint32_t old_z = *(uint32_t*)&z_p[x_l * 2];
z_check_pass = z_check_32(z, old_z, mystique->dwgreg.dwgctrl_running & DWGCTRL_ZMODE_MASK);
} else {
uint16_t z = ((int32_t) mystique->dwgreg.dr[0] < 0) ? 0 : (mystique->dwgreg.dr[0] >> 15);
uint16_t old_z = z_p[x_l];
z_check_pass = z_check(z, old_z, mystique->dwgreg.dwgctrl_running & DWGCTRL_ZMODE_MASK);
}
if (z_check_pass) {
uint32_t dst = 0;
uint32_t old_dst;
int r = 0;
int g = 0;
int b = 0;
if (!(mystique->dwgreg.dr[4] & (1 << 23)))
r = (mystique->dwgreg.dr[4] >> 15) & 0xff;
if (!(mystique->dwgreg.dr[8] & (1 << 23)))
g = (mystique->dwgreg.dr[8] >> 15) & 0xff;
if (!(mystique->dwgreg.dr[12] & (1 << 23)))
b = (mystique->dwgreg.dr[12] >> 15) & 0xff;
if (z_write) {
if (mystique->maccess_running & MACCESS_ZWIDTH) {
*(uint32_t*)(&z_p[x_l * 2]) = (mystique->dwgreg.extended_dr[0] & (1ull << 47ull)) ? 0 : (mystique->dwgreg.extended_dr[0] >> 15ull);
}
else
z_p[x_l] = ((int32_t) mystique->dwgreg.dr[0] < 0) ? 0 : (mystique->dwgreg.dr[0] >> 15);
}
switch (mystique->maccess_running & MACCESS_PWIDTH_MASK) {
case MACCESS_PWIDTH_8:
svga->vram[(mystique->dwgreg.ydst_lin + x_l) & mystique->vram_mask] = dst;
svga->changedvram[((mystique->dwgreg.ydst_lin + x_l) & mystique->vram_mask) >> 12] = changeframecount;
break;
case MACCESS_PWIDTH_16:
dst = dither(mystique, r, g, b, x_l & 1, mystique->dwgreg.selline & 1);
((uint16_t *) svga->vram)[(mystique->dwgreg.ydst_lin + x_l) & mystique->vram_mask_w] = dst;
svga->changedvram[((mystique->dwgreg.ydst_lin + x_l) & mystique->vram_mask_w) >> 11] = changeframecount;
break;
case MACCESS_PWIDTH_24:
old_dst = *(uint32_t *) (&svga->vram[((mystique->dwgreg.ydst_lin + x_l) * 3) & mystique->vram_mask]) & 0xff000000;
*(uint32_t *) (&svga->vram[((mystique->dwgreg.ydst_lin + x_l) * 3) & mystique->vram_mask]) = old_dst | dst;
svga->changedvram[(((mystique->dwgreg.ydst_lin + x_l) * 3) & mystique->vram_mask) >> 12] = changeframecount;
break;
case MACCESS_PWIDTH_32:
((uint32_t *) svga->vram)[(mystique->dwgreg.ydst_lin + x_l) & mystique->vram_mask_l] = b | (g << 8) | (r << 16);
svga->changedvram[((mystique->dwgreg.ydst_lin + x_l) & mystique->vram_mask_l) >> 10] = changeframecount;
break;
default:
fatal("TRAP BLK/RPL PWIDTH %x %08x\n", mystique->maccess_running & MACCESS_PWIDTH_MASK, mystique->dwgreg.dwgctrl_running);
}
}
}
if (mystique->maccess_running & MACCESS_ZWIDTH) {
mystique->dwgreg.extended_dr[0] += mystique->dwgreg.extended_dr[2];
mystique->dwgreg.dr[0] = (mystique->dwgreg.extended_dr[0] >> 16) & 0xFFFFFFFF;
} else {
mystique->dwgreg.dr[0] += mystique->dwgreg.dr[2];
mystique->dwgreg.extended_dr[0] = (mystique->dwgreg.extended_dr[0] & ~0xFFFFull) | ((uint64_t)mystique->dwgreg.dr[0] << 16ull);
}
mystique->dwgreg.dr[4] += mystique->dwgreg.dr[6];
mystique->dwgreg.dr[8] += mystique->dwgreg.dr[10];
mystique->dwgreg.dr[12] += mystique->dwgreg.dr[14];
if (x_l > x_r)
x_l--;
else
x_l++;
}
if (mystique->maccess_running & MACCESS_ZWIDTH) {
mystique->dwgreg.extended_dr[0] = z_back_32 + mystique->dwgreg.extended_dr[3];
mystique->dwgreg.dr[0] = (mystique->dwgreg.extended_dr[0] >> 16) & 0xFFFFFFFF;
} else {
mystique->dwgreg.dr[0] = z_back + mystique->dwgreg.dr[3];
mystique->dwgreg.extended_dr[0] = (mystique->dwgreg.extended_dr[0] & ~0xFFFFull) | ((uint64_t)mystique->dwgreg.dr[0] << 16ull);
}
mystique->dwgreg.dr[4] = r_back + mystique->dwgreg.dr[7];
mystique->dwgreg.dr[8] = g_back + mystique->dwgreg.dr[11];
mystique->dwgreg.dr[12] = b_back + mystique->dwgreg.dr[15];
while ((int32_t) mystique->dwgreg.ar[1] < 0 && mystique->dwgreg.ar[0]) {
mystique->dwgreg.ar[1] += mystique->dwgreg.ar[0];
mystique->dwgreg.fxleft += (mystique->dwgreg.sgn.sdxl ? -1 : 1);
}
mystique->dwgreg.ar[1] += mystique->dwgreg.ar[2];
while ((int32_t) mystique->dwgreg.ar[4] < 0 && mystique->dwgreg.ar[6]) {
mystique->dwgreg.ar[4] += mystique->dwgreg.ar[6];
mystique->dwgreg.fxright += (mystique->dwgreg.sgn.sdxr ? -1 : 1);
}
mystique->dwgreg.ar[4] += mystique->dwgreg.ar[5];
dx = (int16_t) ((mystique->dwgreg.fxleft - old_x_l) & 0xffff);
if (mystique->maccess_running & MACCESS_ZWIDTH) {
mystique->dwgreg.extended_dr[0] += dx * mystique->dwgreg.extended_dr[2];
mystique->dwgreg.dr[0] = (mystique->dwgreg.extended_dr[0] >> 16) & 0xFFFFFFFF;
} else {
mystique->dwgreg.dr[0] += dx * mystique->dwgreg.dr[2];
mystique->dwgreg.extended_dr[0] = (mystique->dwgreg.extended_dr[0] & ~0xFFFFull) | ((uint64_t)mystique->dwgreg.dr[0] << 16ull);
}
mystique->dwgreg.dr[4] += dx * mystique->dwgreg.dr[6];
mystique->dwgreg.dr[8] += dx * mystique->dwgreg.dr[10];
mystique->dwgreg.dr[12] += dx * mystique->dwgreg.dr[14];
mystique->dwgreg.ydst++;
mystique->dwgreg.ydst &= 0x7fffff;
mystique->dwgreg.ydst_lin += (mystique->dwgreg.pitch & PITCH_MASK);
mystique->dwgreg.selline = (mystique->dwgreg.selline + 1) & 7;
}
break;
default:
#if 0
pclog("Unknown atype %03x %08x TRAP\n", mystique->dwgreg.dwgctrl_running & DWGCTRL_ATYPE_MASK, mystique->dwgreg.dwgctrl_running);
#endif
break;
}
mystique->blitter_complete_refcount++;
}
static uint16_t texture_texel_fetch(mystique_t *mystique, int *tex_r, int *tex_g, int *tex_b, int *tex_a, int *atransp, int s, int t, int tex_pitch)
{
const unsigned int w_mask = (mystique->dwgreg.texwidth & TEXWIDTH_TWMASK_MASK) >> TEXWIDTH_TWMASK_SHIFT;
const unsigned int h_mask = (mystique->dwgreg.texheight & TEXHEIGHT_THMASK_MASK) >> TEXHEIGHT_THMASK_SHIFT;
const unsigned int palsel = mystique->dwgreg.texctl & TEXCTL_PALSEL_MASK;
svga_t* svga = &mystique->svga;
uint16_t src = 0x0;
int atransp_dummy = 0;
if (!atransp)
atransp = &atransp_dummy;
if (mystique->dwgreg.texctl & TEXCTL_CLAMPU) {
if (s < 0)
s = 0;
else if (s > w_mask)
s = w_mask;
} else
s &= w_mask;
if (mystique->dwgreg.texctl & TEXCTL_CLAMPV) {
if (t < 0)
t = 0;
else if (t > h_mask)
t = h_mask;
} else
t &= h_mask;
switch (mystique->dwgreg.texctl & TEXCTL_TEXFORMAT_MASK) {
case TEXCTL_TEXFORMAT_TW4:
src = svga->vram[(mystique->dwgreg.texorg + (((t * tex_pitch) + s) >> 1)) & mystique->vram_mask];
if (s & 1)
src >>= 4;
else
src &= 0xf;
*tex_r = mystique->lut[src | palsel].r;
*tex_g = mystique->lut[src | palsel].g;
*tex_b = mystique->lut[src | palsel].b;
*atransp = 0;
break;
case TEXCTL_TEXFORMAT_TW8:
src = svga->vram[(mystique->dwgreg.texorg + (t * tex_pitch) + s) & mystique->vram_mask];
*tex_r = mystique->lut[src].r;
*tex_g = mystique->lut[src].g;
*tex_b = mystique->lut[src].b;
*atransp = 0;
break;
case TEXCTL_TEXFORMAT_TW15:
src = ((uint16_t *) svga->vram)[((mystique->dwgreg.texorg >> 1) + (t * tex_pitch) + s) & mystique->vram_mask_w];
*tex_r = ((src >> 10) & 0x1f) << 3;
*tex_g = ((src >> 5) & 0x1f) << 3;
*tex_b = (src & 0x1f) << 3;
if (((src >> 15) & mystique->dwgreg.ta_mask) == mystique->dwgreg.ta_key)
*atransp = 1;
else
*atransp = 0;
break;
case TEXCTL_TEXFORMAT_TW12:
src = ((uint16_t *) svga->vram)[((mystique->dwgreg.texorg >> 1) + (t * tex_pitch) + s) & mystique->vram_mask_w];
*tex_r = ((src >> 8) & 0xf) << 4;
*tex_g = ((src >> 4) & 0xf) << 4;
*tex_b = (src & 0xf) << 4;
*tex_a = ((src >> 12) & 0xf) << 4;
if (mystique->dwgreg.texctl & TEXCTL_AZEROEXTEND) {
*atransp = (((src >> 12) & 0xf) & mystique->dwgreg.ta_mask) == mystique->dwgreg.ta_key;
} else {
uint8_t ta_mask = mystique->dwgreg.ta_mask ? 0xf : 0x0;
uint8_t ta_key = mystique->dwgreg.ta_key ? 0xf : 0x0;
*atransp = (((src >> 12) & 0xf) & ta_mask) == ta_key;
}
break;
case TEXCTL_TEXFORMAT_TW16:
src = ((uint16_t *) svga->vram)[((mystique->dwgreg.texorg >> 1) + (t * tex_pitch) + s) & mystique->vram_mask_w];
*tex_r = (src >> 11) << 3;
*tex_g = ((src >> 5) & 0x3f) << 2;
*tex_b = (src & 0x1f) << 3;
*atransp = 0;
break;
default:
fatal("Unknown texture format %i\n", mystique->dwgreg.texctl & TEXCTL_TEXFORMAT_MASK);
break;
}
return src;
}
static double lerp(double v0, double v1, double t) {
return (1. - t) * v0 + t * v1;
}
static int
texture_read(mystique_t *mystique, int *tex_r, int *tex_g, int *tex_b, int *atransp, int *tex_a)
{
const int tex_shift = 3 + ((mystique->dwgreg.texctl & TEXCTL_TPITCH_MASK) >> TEXCTL_TPITCH_SHIFT);
const uint16_t tckey = mystique->dwgreg.textrans & TEXTRANS_TCKEY_MASK;
const uint16_t tkmask = (mystique->dwgreg.textrans & TEXTRANS_TKMASK_MASK) >> TEXTRANS_TKMASK_SHIFT;
const unsigned int w_mask = (mystique->dwgreg.texwidth & TEXWIDTH_TWMASK_MASK) >> TEXWIDTH_TWMASK_SHIFT;
const unsigned int h_mask = (mystique->dwgreg.texheight & TEXHEIGHT_THMASK_MASK) >> TEXHEIGHT_THMASK_SHIFT;
uint16_t src = 0;
int s;
int t;
int tex_pitch = 1 << tex_shift;
double s_frac = 0;
double t_frac = 0;
*tex_a = 255;
if (mystique->type >= MGA_G100 && (mystique->dwgreg.texctl & TEXCTL_TPITCHLIN))
{
tex_pitch = (mystique->dwgreg.texctl & TEXCTL_TPITCHEXT_MASK) >> 9;
if (tex_pitch == 0)
tex_pitch = 2048;
}
if (mystique->dwgreg.texctl & TEXCTL_NPCEN) {
const int s_shift = 20 - (mystique->dwgreg.texwidth & TEXWIDTH_TW_MASK);
const int t_shift = 20 - (mystique->dwgreg.texheight & TEXHEIGHT_TH_MASK);
s = (int32_t) mystique->dwgreg.tmr[6] >> s_shift;
t = (int32_t) mystique->dwgreg.tmr[7] >> t_shift;
s_frac = (((int32_t) mystique->dwgreg.tmr[6]) & ((1 << s_shift) - 1)) / (double)(1 << s_shift);
t_frac = (((int32_t) mystique->dwgreg.tmr[7]) & ((1 << t_shift) - 1)) / (double)(1 << t_shift);
} else {
const int s_shift = (20 + 16) - (mystique->dwgreg.texwidth & TEXWIDTH_TW_MASK);
const int t_shift = (20 + 16) - (mystique->dwgreg.texheight & TEXHEIGHT_TH_MASK);
int64_t q = mystique->dwgreg.tmr[8] ? (0x100000000LL / (int64_t) (int32_t) mystique->dwgreg.tmr[8]) : 0;
s = ((int64_t) (int32_t) mystique->dwgreg.tmr[6] * q) >> s_shift;
t = ((int64_t) (int32_t) mystique->dwgreg.tmr[7] * q) >> t_shift;
s_frac = (((int64_t) (int32_t) mystique->dwgreg.tmr[6] * q) & ((1 << s_shift) - 1)) / (double)(1 << s_shift);
t_frac = (((int64_t) (int32_t) mystique->dwgreg.tmr[7] * q) & ((1 << t_shift) - 1)) / (double)(1 << t_shift);
}
if (mystique->dwgreg.texctl & TEXCTL_CLAMPU) {
if (s < 0)
s = 0;
else if (s > w_mask)
s = w_mask;
} else
s &= w_mask;
if (mystique->dwgreg.texctl & TEXCTL_CLAMPV) {
if (t < 0)
t = 0;
else if (t > h_mask)
t = h_mask;
} else
t &= h_mask;
src = texture_texel_fetch(mystique, tex_r, tex_g, tex_b, tex_a, atransp, s, t, tex_pitch);
switch (mystique->dwgreg.texfilter & 3)
{
case 0:
s_frac = t_frac = 0;
break;
case 1:
case 2:
break;
case 3:
s_frac = t_frac = .25;
break;
}
if (s_frac && s != w_mask)
{
int s_tex_r = 0, s_tex_g = 0, s_tex_b = 0, s_tex_a = 255;
texture_texel_fetch(mystique, &s_tex_r, &s_tex_g, &s_tex_b, &s_tex_a, NULL, s + 1, t, tex_pitch);
*tex_r = (int)lerp(*tex_r, s_tex_r, s_frac);
*tex_g = (int)lerp(*tex_g, s_tex_g, s_frac);
*tex_b = (int)lerp(*tex_b, s_tex_b, s_frac);
*tex_a = (int)lerp(*tex_a, s_tex_a, s_frac);
if (*tex_r > 255) *tex_r = 255;
if (*tex_g > 255) *tex_g = 255;
if (*tex_b > 255) *tex_b = 255;
if (*tex_a > 255) *tex_a = 255;
}
if (t_frac && t != h_mask)
{
int t_tex_r = 0, t_tex_g = 0, t_tex_b = 0, t_tex_a = 255;
texture_texel_fetch(mystique, &t_tex_r, &t_tex_g, &t_tex_b, &t_tex_a, NULL, s, t + 1, tex_pitch);
*tex_r = (int)lerp(*tex_r, t_tex_r, t_frac);
*tex_g = (int)lerp(*tex_g, t_tex_g, t_frac);
*tex_b = (int)lerp(*tex_b, t_tex_b, t_frac);
*tex_a = (int)lerp(*tex_a, t_tex_a, t_frac);
if (*tex_r > 255) *tex_r = 255;
if (*tex_g > 255) *tex_g = 255;
if (*tex_b > 255) *tex_b = 255;
if (*tex_a > 255) *tex_a = 255;
}
return ((src & tkmask) == tckey);
}
static void
blit_texture_trap(mystique_t *mystique)
{
svga_t *svga = &mystique->svga;
int y;
int z_write;
const int trans_sel = (mystique->dwgreg.dwgctrl_running & DWGCTRL_TRANS_MASK) >> DWGCTRL_TRANS_SHIFT;
const int dest32 = ((mystique->maccess_running & MACCESS_PWIDTH_MASK) == MACCESS_PWIDTH_32);
switch (mystique->dwgreg.dwgctrl_running & DWGCTRL_ATYPE_MASK) {
case DWGCTRL_ATYPE_I:
case DWGCTRL_ATYPE_ZI:
z_write = ((mystique->dwgreg.dwgctrl_running & DWGCTRL_ATYPE_MASK) == DWGCTRL_ATYPE_ZI);
for (y = 0; y < mystique->dwgreg.length; y++) {
uint8_t const *const trans = &trans_masks[trans_sel][(mystique->dwgreg.selline & 3) * 4];
uint16_t *z_p = (uint16_t *) &svga->vram[(mystique->dwgreg.ydst_lin * ((mystique->maccess_running & MACCESS_ZWIDTH) ? 4 : 2) + mystique->dwgreg.zorg) & mystique->vram_mask];
int16_t x_l = mystique->dwgreg.fxleft & 0xffff;
int16_t x_r = mystique->dwgreg.fxright & 0xffff;
int16_t old_x_l = x_l;
int dx;
uint64_t z_back_32 = mystique->dwgreg.extended_dr[0];
uint32_t z_back = mystique->dwgreg.dr[0];
uint32_t r_back = mystique->dwgreg.dr[4];
uint32_t g_back = mystique->dwgreg.dr[8];
uint32_t b_back = mystique->dwgreg.dr[12];
uint32_t s_back = mystique->dwgreg.tmr[6];
uint32_t t_back = mystique->dwgreg.tmr[7];
uint32_t q_back = mystique->dwgreg.tmr[8];
uint32_t a_back = mystique->dwgreg.alphastart;
uint32_t fog_back = mystique->dwgreg.fogstart;
while (x_l != x_r) {
if (x_l >= mystique->dwgreg.cxleft && x_l <= mystique->dwgreg.cxright && mystique->dwgreg.ydst_lin >= mystique->dwgreg.ytop && mystique->dwgreg.ydst_lin <= mystique->dwgreg.ybot && trans[x_l & 3]) {
bool z_check_pass = false;
if (mystique->maccess_running & MACCESS_ZWIDTH) {
uint32_t z = (mystique->dwgreg.extended_dr[0] & (1ull << 47ull)) ? 0 : (mystique->dwgreg.extended_dr[0] >> 15ull);
uint32_t old_z = *(uint32_t*)&z_p[x_l * 2];
z_check_pass = z_check_32(z, old_z, mystique->dwgreg.dwgctrl_running & DWGCTRL_ZMODE_MASK);
} else {
uint16_t z = ((int32_t) mystique->dwgreg.dr[0] < 0) ? 0 : (mystique->dwgreg.dr[0] >> 15);
uint16_t old_z = z_p[x_l];
z_check_pass = z_check(z, old_z, mystique->dwgreg.dwgctrl_running & DWGCTRL_ZMODE_MASK);
}
if (z_check_pass) {
int tex_r = 0;
int tex_g = 0;
int tex_b = 0;
int tex_a = 255;
int ctransp;
int atransp = 0;
int i_r = 0;
int i_g = 0;
int i_b = 0;
int i_a = 255;
int i_fog = 0;
uint8_t final_a = 255;
if (!(mystique->dwgreg.dr[4] & (1 << 23)))
i_r = (mystique->dwgreg.dr[4] >> 15) & 0xff;
if (!(mystique->dwgreg.dr[8] & (1 << 23)))
i_g = (mystique->dwgreg.dr[8] >> 15) & 0xff;
if (!(mystique->dwgreg.dr[12] & (1 << 23)))
i_b = (mystique->dwgreg.dr[12] >> 15) & 0xff;
if (mystique->type >= MGA_G100)
{
if (!(mystique->dwgreg.alphastart & (1 << 23)))
i_a = (mystique->dwgreg.alphastart >> 15) & 0xff;
else
i_a = 0;
if (!(mystique->dwgreg.fogstart & (1 << 23)))
i_fog = (mystique->dwgreg.fogstart >> 15) & 0xff;
else
i_fog = 0;
}
ctransp = texture_read(mystique, &tex_r, &tex_g, &tex_b, &atransp, &tex_a);
if (mystique->type >= MGA_G100)
{
uint8_t alpha_sel = (mystique->dwgreg.alphactrl >> 24) & 3;
switch (alpha_sel)
{
case 0x0: /* alpha from texture */
final_a = tex_a;
break;
default:
case 0x1: /* interpolated alpha */
if ((mystique->dwgreg.alphactrl & (1 << 11)))
final_a = i_a;
break;
case 0x2: /* modulated alpha */
if (!(mystique->dwgreg.alphactrl & (1 << 11)))
final_a = tex_a;
else
final_a = ((i_a * tex_a) >> 8) & 0xFF;
break;
}
}
switch (mystique->dwgreg.texctl & (TEXCTL_TMODULATE | TEXCTL_STRANS | TEXCTL_ITRANS | TEXCTL_DECALCKEY)) {
case 0:
if (ctransp)
goto skip_pixel;
if (atransp) {
tex_r = i_r;
tex_g = i_g;
tex_b = i_b;
}
break;
case TEXCTL_DECALCKEY:
if (ctransp) {
tex_r = i_r;
tex_g = i_g;
tex_b = i_b;
}
break;
case (TEXCTL_STRANS | TEXCTL_DECALCKEY):
if (ctransp)
goto skip_pixel;
break;
case TEXCTL_TMODULATE:
if (ctransp)
goto skip_pixel;
if (mystique->dwgreg.texctl & TEXCTL_TMODULATE) {
tex_r = (tex_r * i_r) >> 8;
tex_g = (tex_g * i_g) >> 8;
tex_b = (tex_b * i_b) >> 8;
}
break;
case (TEXCTL_TMODULATE | TEXCTL_STRANS):
if (ctransp || atransp)
goto skip_pixel;
if (mystique->dwgreg.texctl & TEXCTL_TMODULATE) {
tex_r = (tex_r * i_r) >> 8;
tex_g = (tex_g * i_g) >> 8;
tex_b = (tex_b * i_b) >> 8;
}
break;
case (TEXCTL_STRANS | TEXCTL_ITRANS | TEXCTL_DECALCKEY):
if (!ctransp)
goto skip_pixel;
tex_r = i_r;
tex_g = i_g;
tex_b = i_b;
break;
default:
fatal("Bad TEXCTL %08x %08x\n", mystique->dwgreg.texctl, mystique->dwgreg.texctl & (TEXCTL_TMODULATE | TEXCTL_STRANS | TEXCTL_ITRANS | TEXCTL_DECALCKEY));
}
if (mystique->type >= MGA_G100 && (mystique->maccess_running & MACCESS_FOGEN))
{
tex_r = (tex_r * ((i_fog) / 255.)) + (mystique->dwgreg.fogcol >> 16) * ((255 - i_fog) / 255.);
tex_g = (tex_g * ((i_fog) / 255.)) + ((mystique->dwgreg.fogcol >> 8) & 0xFF) * ((255 - i_fog) / 255.);
tex_b = (tex_b * ((i_fog) / 255.)) + ((mystique->dwgreg.fogcol) & 0xFF) * ((255 - i_fog) / 255.);
}
if (final_a != 255)
{
{
double threshold = bayer_mat[mystique->dwgreg.selline & 3][x_l & 3];
double final_a_frac = (final_a) / 255.;
if (final_a_frac >= threshold) {
final_a = 255;
} else {
goto skip_pixel;
}
}
}
if (dest32) {
((uint32_t *) svga->vram)[(mystique->dwgreg.ydst_lin + x_l) & mystique->vram_mask_l] = tex_b | (tex_g << 8) | (tex_r << 16);
svga->changedvram[((mystique->dwgreg.ydst_lin + x_l) & mystique->vram_mask_l) >> 10] = changeframecount;
} else {
((uint16_t *) svga->vram)[(mystique->dwgreg.ydst_lin + x_l) & mystique->vram_mask_w] = dither(mystique, tex_r, tex_g, tex_b, x_l & 1, mystique->dwgreg.selline & 1);
svga->changedvram[((mystique->dwgreg.ydst_lin + x_l) & mystique->vram_mask_w) >> 11] = changeframecount;
}
if (z_write) {
if (mystique->maccess_running & MACCESS_ZWIDTH) {
*(uint32_t*)(&z_p[x_l * 2]) = (mystique->dwgreg.extended_dr[0] & (1ull << 47ull)) ? 0 : (mystique->dwgreg.extended_dr[0] >> 15ull);
}
else
z_p[x_l] = ((int32_t) mystique->dwgreg.dr[0] < 0) ? 0 : (mystique->dwgreg.dr[0] >> 15);
}
}
}
skip_pixel:
if (x_l > x_r)
x_l--;
else
x_l++;
if (mystique->maccess_running & MACCESS_ZWIDTH) {
mystique->dwgreg.extended_dr[0] += mystique->dwgreg.extended_dr[2];
mystique->dwgreg.dr[0] = (mystique->dwgreg.extended_dr[0] >> 16) & 0xFFFFFFFF;
} else {
mystique->dwgreg.dr[0] += mystique->dwgreg.dr[2];
mystique->dwgreg.extended_dr[0] = (mystique->dwgreg.extended_dr[0] & ~0xFFFFull) | ((uint64_t)mystique->dwgreg.dr[0] << 16ull);
}
mystique->dwgreg.dr[4] += mystique->dwgreg.dr[6];
mystique->dwgreg.dr[8] += mystique->dwgreg.dr[10];
mystique->dwgreg.dr[12] += mystique->dwgreg.dr[14];
mystique->dwgreg.tmr[6] += mystique->dwgreg.tmr[0];
mystique->dwgreg.tmr[7] += mystique->dwgreg.tmr[2];
mystique->dwgreg.tmr[8] += mystique->dwgreg.tmr[4];
mystique->dwgreg.fogstart += mystique->dwgreg.fogxinc;
mystique->dwgreg.alphastart += mystique->dwgreg.alphaxinc;
mystique->dwgreg.fogstart &= 0xFFFFFF;
mystique->dwgreg.alphastart &= 0xFFFFFF;
}
if (mystique->maccess_running & MACCESS_ZWIDTH) {
mystique->dwgreg.extended_dr[0] = z_back_32 + mystique->dwgreg.extended_dr[3];
mystique->dwgreg.dr[0] = (mystique->dwgreg.extended_dr[0] >> 16) & 0xFFFFFFFF;
} else {
mystique->dwgreg.dr[0] = z_back + mystique->dwgreg.dr[3];
mystique->dwgreg.extended_dr[0] = (mystique->dwgreg.extended_dr[0] & ~0xFFFFull) | ((uint64_t)mystique->dwgreg.dr[0] << 16ull);
}
mystique->dwgreg.dr[4] = r_back + mystique->dwgreg.dr[7];
mystique->dwgreg.dr[8] = g_back + mystique->dwgreg.dr[11];
mystique->dwgreg.dr[12] = b_back + mystique->dwgreg.dr[15];
mystique->dwgreg.tmr[6] = s_back + mystique->dwgreg.tmr[1];
mystique->dwgreg.tmr[7] = t_back + mystique->dwgreg.tmr[3];
mystique->dwgreg.tmr[8] = q_back + mystique->dwgreg.tmr[5];
mystique->dwgreg.fogstart = fog_back + mystique->dwgreg.fogyinc;
mystique->dwgreg.alphastart = a_back + mystique->dwgreg.alphayinc;
mystique->dwgreg.fogstart &= 0xFFFFFF;
mystique->dwgreg.alphastart &= 0xFFFFFF;
while ((int32_t) mystique->dwgreg.ar[1] < 0 && mystique->dwgreg.ar[0]) {
mystique->dwgreg.ar[1] += mystique->dwgreg.ar[0];
mystique->dwgreg.fxleft += (mystique->dwgreg.sgn.sdxl ? -1 : 1);
}
mystique->dwgreg.ar[1] += mystique->dwgreg.ar[2];
while ((int32_t) mystique->dwgreg.ar[4] < 0 && mystique->dwgreg.ar[6]) {
mystique->dwgreg.ar[4] += mystique->dwgreg.ar[6];
mystique->dwgreg.fxright += (mystique->dwgreg.sgn.sdxr ? -1 : 1);
}
mystique->dwgreg.ar[4] += mystique->dwgreg.ar[5];
dx = (int16_t) ((mystique->dwgreg.fxleft - old_x_l) & 0xffff);
if (mystique->maccess_running & MACCESS_ZWIDTH) {
mystique->dwgreg.extended_dr[0] += dx * mystique->dwgreg.extended_dr[2];
mystique->dwgreg.dr[0] = (mystique->dwgreg.extended_dr[0] >> 16) & 0xFFFFFFFF;
} else {
mystique->dwgreg.dr[0] += dx * mystique->dwgreg.dr[2];
mystique->dwgreg.extended_dr[0] = (mystique->dwgreg.extended_dr[0] & ~0xFFFFull) | ((uint64_t)mystique->dwgreg.dr[0] << 16ull);
}
mystique->dwgreg.dr[4] += dx * mystique->dwgreg.dr[6];
mystique->dwgreg.dr[8] += dx * mystique->dwgreg.dr[10];
mystique->dwgreg.dr[12] += dx * mystique->dwgreg.dr[14];
mystique->dwgreg.tmr[6] += dx * mystique->dwgreg.tmr[0];
mystique->dwgreg.tmr[7] += dx * mystique->dwgreg.tmr[2];
mystique->dwgreg.tmr[8] += dx * mystique->dwgreg.tmr[4];
mystique->dwgreg.fogstart += dx * mystique->dwgreg.fogxinc;
mystique->dwgreg.alphastart += dx * mystique->dwgreg.alphaxinc;
mystique->dwgreg.fogstart &= 0xFFFFFF;
mystique->dwgreg.alphastart &= 0xFFFFFF;
mystique->dwgreg.ydst++;
mystique->dwgreg.ydst &= 0x7fffff;
mystique->dwgreg.ydst_lin += (mystique->dwgreg.pitch & PITCH_MASK);
mystique->dwgreg.selline = (mystique->dwgreg.selline + 1) & 7;
}
break;
default:
fatal("Unknown atype %03x %08x TEXTURE_TRAP\n", mystique->dwgreg.dwgctrl_running & DWGCTRL_ATYPE_MASK, mystique->dwgreg.dwgctrl_running);
}
mystique->blitter_complete_refcount++;
}
static void
blit_bitblt(mystique_t *mystique)
{
svga_t *svga = &mystique->svga;
uint32_t src_addr;
int y;
int x_dir = mystique->dwgreg.sgn.scanleft ? -1 : 1;
int16_t x_start = mystique->dwgreg.sgn.scanleft ? mystique->dwgreg.fxright : mystique->dwgreg.fxleft;
int16_t x_end = mystique->dwgreg.sgn.scanleft ? mystique->dwgreg.fxleft : mystique->dwgreg.fxright;
const int trans_sel = (mystique->dwgreg.dwgctrl_running & DWGCTRL_TRANS_MASK) >> DWGCTRL_TRANS_SHIFT;
uint32_t bltckey = mystique->dwgreg.fcol;
uint32_t bltcmsk = mystique->dwgreg.bcol;
switch (mystique->maccess_running & MACCESS_PWIDTH_MASK) {
case MACCESS_PWIDTH_8:
bltckey &= 0xff;
bltcmsk &= 0xff;
break;
case MACCESS_PWIDTH_16:
bltckey &= 0xffff;
bltcmsk &= 0xffff;
break;
}
switch (mystique->dwgreg.dwgctrl_running & DWGCTRL_ATYPE_MASK) {
case DWGCTRL_ATYPE_BLK:
switch (mystique->dwgreg.dwgctrl_running & DWGCTRL_BLTMOD_MASK) {
case DWGCTRL_BLTMOD_BMONOLEF:
case DWGCTRL_BLTMOD_BMONOWF:
src_addr = mystique->dwgreg.ar[3];
for (y = 0; y < mystique->dwgreg.length; y++) {
int16_t x = x_start;
while (1) {
if (x >= mystique->dwgreg.cxleft && x <= mystique->dwgreg.cxright && mystique->dwgreg.ydst_lin >= mystique->dwgreg.ytop && mystique->dwgreg.ydst_lin <= mystique->dwgreg.ybot) {
uint32_t byte_addr = (src_addr >> 3) & mystique->vram_mask;
int bit_offset = ((mystique->dwgreg.dwgctrl_running & DWGCTRL_BLTMOD_MASK) == DWGCTRL_BLTMOD_BMONOWF) ? (7 - (src_addr & 7)) : (src_addr & 7);
uint32_t old_dst;
switch (mystique->maccess_running & MACCESS_PWIDTH_MASK) {
case MACCESS_PWIDTH_8:
if (mystique->dwgreg.dwgctrl_running & DWGCTRL_TRANSC) {
if (svga->vram[byte_addr] & (1 << bit_offset))
svga->vram[(mystique->dwgreg.ydst_lin + x) & mystique->vram_mask] = mystique->dwgreg.fcol;
} else
svga->vram[(mystique->dwgreg.ydst_lin + x) & mystique->vram_mask] = (svga->vram[byte_addr] & (1 << bit_offset)) ? mystique->dwgreg.fcol : mystique->dwgreg.bcol;
svga->changedvram[((mystique->dwgreg.ydst_lin + x) & mystique->vram_mask) >> 12] = changeframecount;
break;
case MACCESS_PWIDTH_16:
if (mystique->dwgreg.dwgctrl_running & DWGCTRL_TRANSC) {
if (svga->vram[byte_addr] & (1 << bit_offset))
((uint16_t *) svga->vram)[(mystique->dwgreg.ydst_lin + x) & mystique->vram_mask_w] = mystique->dwgreg.fcol;
} else
((uint16_t *) svga->vram)[(mystique->dwgreg.ydst_lin + x) & mystique->vram_mask_w] = (svga->vram[byte_addr] & (1 << bit_offset)) ? mystique->dwgreg.fcol : mystique->dwgreg.bcol;
svga->changedvram[((mystique->dwgreg.ydst_lin + x) & mystique->vram_mask_w) >> 11] = changeframecount;
break;
case MACCESS_PWIDTH_24:
old_dst = *(uint32_t *) &svga->vram[((mystique->dwgreg.ydst_lin + x) * 3) & mystique->vram_mask];
if (mystique->dwgreg.dwgctrl_running & DWGCTRL_TRANSC) {
if (svga->vram[byte_addr] & (1 << bit_offset))
*(uint32_t *) &svga->vram[((mystique->dwgreg.ydst_lin + x) * 3) & mystique->vram_mask] = (old_dst & 0xff000000) | (mystique->dwgreg.fcol & 0xffffff);
} else
*(uint32_t *) &svga->vram[((mystique->dwgreg.ydst_lin + x) * 3) & mystique->vram_mask] = (old_dst & 0xff000000) | (((svga->vram[byte_addr] & (1 << bit_offset)) ? mystique->dwgreg.fcol : mystique->dwgreg.bcol) & 0xffffff);
svga->changedvram[(((mystique->dwgreg.ydst_lin + x) * 3) & mystique->vram_mask) >> 12] = changeframecount;
break;
case MACCESS_PWIDTH_32:
if (mystique->dwgreg.dwgctrl_running & DWGCTRL_TRANSC) {
if (svga->vram[byte_addr] & (1 << bit_offset))
((uint32_t *) svga->vram)[(mystique->dwgreg.ydst_lin + x) & mystique->vram_mask_l] = mystique->dwgreg.fcol;
} else
((uint32_t *) svga->vram)[(mystique->dwgreg.ydst_lin + x) & mystique->vram_mask_l] = (svga->vram[byte_addr] & (1 << bit_offset)) ? mystique->dwgreg.fcol : mystique->dwgreg.bcol;
svga->changedvram[((mystique->dwgreg.ydst_lin + x) & mystique->vram_mask_l) >> 11] = changeframecount;
break;
default:
fatal("BITBLT DWGCTRL_ATYPE_BLK unknown MACCESS %i\n", mystique->maccess_running & MACCESS_PWIDTH_MASK);
}
}
if (src_addr == mystique->dwgreg.ar[0]) {
mystique->dwgreg.ar[0] += mystique->dwgreg.ar[5];
mystique->dwgreg.ar[3] += mystique->dwgreg.ar[5];
src_addr = mystique->dwgreg.ar[3];
} else
src_addr += x_dir;
if (x != x_end) {
if ((x > x_end) && (x_dir == 1))
x--;
else if ((x < x_end) && (x_dir == -1))
x++;
else
x += x_dir;
} else
break;
}
if (mystique->dwgreg.sgn.sdy)
mystique->dwgreg.ydst_lin -= (mystique->dwgreg.pitch & PITCH_MASK);
else
mystique->dwgreg.ydst_lin += (mystique->dwgreg.pitch & PITCH_MASK);
}
break;
default:
fatal("BITBLT BLK %08x\n", mystique->dwgreg.dwgctrl_running & DWGCTRL_BLTMOD_MASK);
break;
}
break;
case DWGCTRL_ATYPE_RPL:
if (mystique->maccess_running & MACCESS_TLUTLOAD) {
src_addr = mystique->dwgreg.ar[3];
y = mystique->dwgreg.ydst;
while (mystique->dwgreg.length) {
uint16_t src = ((uint16_t *) svga->vram)[src_addr & mystique->vram_mask_w];
mystique->lut[y & 0xff].r = (src >> 11) << 3;
mystique->lut[y & 0xff].g = ((src >> 5) & 0x3f) << 2;
mystique->lut[y & 0xff].b = (src & 0x1f) << 3;
src_addr++;
y++;
mystique->dwgreg.length--;
}
break;
}
case DWGCTRL_ATYPE_RSTR:
switch (mystique->dwgreg.dwgctrl_running & DWGCTRL_BLTMOD_MASK) {
/* TODO: This isn't exactly perfect. */
case DWGCTRL_BLTMOD_BPLAN:
if (mystique->dwgreg.dwgctrl_running & DWGCTRL_PATTERN)
fatal("BITBLT RPL/RSTR BPLAN with pattern\n");
src_addr = mystique->dwgreg.ar[3];
for (y = 0; y < mystique->dwgreg.length; y++) {
uint8_t const *const trans = &trans_masks[trans_sel][(mystique->dwgreg.selline & 3) * 4];
int16_t x = x_start;
while (1) {
uint32_t byte_addr = src_addr & mystique->vram_mask;
if (x >= mystique->dwgreg.cxleft && x <= mystique->dwgreg.cxright && mystique->dwgreg.ydst_lin >= mystique->dwgreg.ytop && mystique->dwgreg.ydst_lin <= mystique->dwgreg.ybot && ((svga->vram[byte_addr] & 1) || !(mystique->dwgreg.dwgctrl_running & DWGCTRL_TRANSC)) && trans[x & 3]) {
uint32_t src = (svga->vram[byte_addr] & 1) ? mystique->dwgreg.fcol : mystique->dwgreg.bcol;
uint32_t dst;
uint32_t old_dst;
switch (mystique->maccess_running & MACCESS_PWIDTH_MASK) {
case MACCESS_PWIDTH_8:
dst = svga->vram[(mystique->dwgreg.ydst_lin + x) & mystique->vram_mask];
dst = bitop(src, dst, mystique->dwgreg.dwgctrl_running);
svga->vram[(mystique->dwgreg.ydst_lin + x) & mystique->vram_mask] = dst;
svga->changedvram[((mystique->dwgreg.ydst_lin + x) & mystique->vram_mask) >> 12] = changeframecount;
break;
case MACCESS_PWIDTH_16:
dst = ((uint16_t *) svga->vram)[(mystique->dwgreg.ydst_lin + x) & mystique->vram_mask_w];
dst = bitop(src, dst, mystique->dwgreg.dwgctrl_running);
((uint16_t *) svga->vram)[(mystique->dwgreg.ydst_lin + x) & mystique->vram_mask_w] = dst;
svga->changedvram[((mystique->dwgreg.ydst_lin + x) & mystique->vram_mask_w) >> 11] = changeframecount;
break;
case MACCESS_PWIDTH_24:
old_dst = *(uint32_t *) &svga->vram[((mystique->dwgreg.ydst_lin + x) * 3) & mystique->vram_mask];
dst = bitop(src, old_dst, mystique->dwgreg.dwgctrl_running); // & DWGCTRL_BOP_MASK
*(uint32_t *) &svga->vram[((mystique->dwgreg.ydst_lin + x) * 3) & mystique->vram_mask] = (dst & 0xffffff) | (old_dst & 0xff000000);
svga->changedvram[(((mystique->dwgreg.ydst_lin + x) * 3) & mystique->vram_mask) >> 12] = changeframecount;
break;
case MACCESS_PWIDTH_32:
dst = ((uint32_t *) svga->vram)[(mystique->dwgreg.ydst_lin + x) & mystique->vram_mask_l];
dst = bitop(src, dst, mystique->dwgreg.dwgctrl_running);
((uint32_t *) svga->vram)[(mystique->dwgreg.ydst_lin + x) & mystique->vram_mask_l] = dst;
svga->changedvram[((mystique->dwgreg.ydst_lin + x) & mystique->vram_mask_l) >> 10] = changeframecount;
break;
default:
fatal("BITBLT RPL BPLAN PWIDTH %x %08x\n", mystique->maccess_running & MACCESS_PWIDTH_MASK, mystique->dwgreg.dwgctrl_running);
}
}
if (src_addr == mystique->dwgreg.ar[0]) {
mystique->dwgreg.ar[0] += mystique->dwgreg.ar[5];
mystique->dwgreg.ar[3] += mystique->dwgreg.ar[5];
src_addr = mystique->dwgreg.ar[3];
} else
src_addr += x_dir;
if (x != x_end) {
if ((x > x_end) && (x_dir == 1))
x--;
else if ((x < x_end) && (x_dir == -1))
x++;
else
x += x_dir;
} else
break;
}
if (mystique->dwgreg.sgn.sdy)
mystique->dwgreg.ydst_lin -= (mystique->dwgreg.pitch & PITCH_MASK);
else
mystique->dwgreg.ydst_lin += (mystique->dwgreg.pitch & PITCH_MASK);
}
break;
case DWGCTRL_BLTMOD_BMONOLEF:
case DWGCTRL_BLTMOD_BMONOWF:
if (mystique->dwgreg.dwgctrl_running & DWGCTRL_PATTERN)
fatal("BITBLT RPL/RSTR BMONOLEF with pattern\n");
src_addr = mystique->dwgreg.ar[3];
for (y = 0; y < mystique->dwgreg.length; y++) {
uint8_t const *const trans = &trans_masks[trans_sel][(mystique->dwgreg.selline & 3) * 4];
int16_t x = x_start;
while (1) {
uint32_t byte_addr = (src_addr >> 3) & mystique->vram_mask;
int bit_offset = ((mystique->dwgreg.dwgctrl_running & DWGCTRL_BLTMOD_MASK) == DWGCTRL_BLTMOD_BMONOWF) ? (7 - (src_addr & 7)) : (src_addr & 7);
if (x >= mystique->dwgreg.cxleft && x <= mystique->dwgreg.cxright && mystique->dwgreg.ydst_lin >= mystique->dwgreg.ytop && mystique->dwgreg.ydst_lin <= mystique->dwgreg.ybot && ((svga->vram[byte_addr] & (1 << bit_offset)) || !(mystique->dwgreg.dwgctrl_running & DWGCTRL_TRANSC)) && trans[x & 3]) {
uint32_t src = (svga->vram[byte_addr] & (1 << bit_offset)) ? mystique->dwgreg.fcol : mystique->dwgreg.bcol;
uint32_t dst;
uint32_t old_dst;
switch (mystique->maccess_running & MACCESS_PWIDTH_MASK) {
case MACCESS_PWIDTH_8:
dst = svga->vram[(mystique->dwgreg.ydst_lin + x) & mystique->vram_mask];
dst = bitop(src, dst, mystique->dwgreg.dwgctrl_running);
svga->vram[(mystique->dwgreg.ydst_lin + x) & mystique->vram_mask] = dst;
svga->changedvram[((mystique->dwgreg.ydst_lin + x) & mystique->vram_mask) >> 12] = changeframecount;
break;
case MACCESS_PWIDTH_16:
dst = ((uint16_t *) svga->vram)[(mystique->dwgreg.ydst_lin + x) & mystique->vram_mask_w];
dst = bitop(src, dst, mystique->dwgreg.dwgctrl_running);
((uint16_t *) svga->vram)[(mystique->dwgreg.ydst_lin + x) & mystique->vram_mask_w] = dst;
svga->changedvram[((mystique->dwgreg.ydst_lin + x) & mystique->vram_mask_w) >> 11] = changeframecount;
break;
case MACCESS_PWIDTH_24:
old_dst = *(uint32_t *) &svga->vram[((mystique->dwgreg.ydst_lin + x) * 3) & mystique->vram_mask];
dst = bitop(src, old_dst, mystique->dwgreg.dwgctrl_running); // & DWGCTRL_BOP_MASK
*(uint32_t *) &svga->vram[((mystique->dwgreg.ydst_lin + x) * 3) & mystique->vram_mask] = (dst & 0xffffff) | (old_dst & 0xff000000);
svga->changedvram[(((mystique->dwgreg.ydst_lin + x) * 3) & mystique->vram_mask) >> 12] = changeframecount;
break;
case MACCESS_PWIDTH_32:
dst = ((uint32_t *) svga->vram)[(mystique->dwgreg.ydst_lin + x) & mystique->vram_mask_l];
dst = bitop(src, dst, mystique->dwgreg.dwgctrl_running);
((uint32_t *) svga->vram)[(mystique->dwgreg.ydst_lin + x) & mystique->vram_mask_l] = dst;
svga->changedvram[((mystique->dwgreg.ydst_lin + x) & mystique->vram_mask_l) >> 10] = changeframecount;
break;
default:
fatal("BITBLT RPL BMONOLEF PWIDTH %x %08x\n", mystique->maccess_running & MACCESS_PWIDTH_MASK, mystique->dwgreg.dwgctrl_running);
}
}
if (src_addr == mystique->dwgreg.ar[0]) {
mystique->dwgreg.ar[0] += mystique->dwgreg.ar[5];
mystique->dwgreg.ar[3] += mystique->dwgreg.ar[5];
src_addr = mystique->dwgreg.ar[3];
} else
src_addr += x_dir;
if (x != x_end) {
if ((x > x_end) && (x_dir == 1))
x--;
else if ((x < x_end) && (x_dir == -1))
x++;
else
x += x_dir;
} else
break;
}
if (mystique->dwgreg.sgn.sdy)
mystique->dwgreg.ydst_lin -= (mystique->dwgreg.pitch & PITCH_MASK);
else
mystique->dwgreg.ydst_lin += (mystique->dwgreg.pitch & PITCH_MASK);
}
break;
case DWGCTRL_BLTMOD_BFCOL:
case DWGCTRL_BLTMOD_BU32RGB:
src_addr = mystique->dwgreg.ar[3];
for (y = 0; y < mystique->dwgreg.length; y++) {
uint8_t const *const trans = &trans_masks[trans_sel][(mystique->dwgreg.selline & 3) * 4];
uint32_t old_src_addr = src_addr;
int16_t x = x_start;
while (1) {
if (x >= mystique->dwgreg.cxleft && x <= mystique->dwgreg.cxright && mystique->dwgreg.ydst_lin >= mystique->dwgreg.ytop && mystique->dwgreg.ydst_lin <= mystique->dwgreg.ybot && trans[x & 3]) {
uint32_t src;
uint32_t dst;
uint32_t old_dst;
switch (mystique->maccess_running & MACCESS_PWIDTH_MASK) {
case MACCESS_PWIDTH_8:
src = svga->vram[src_addr & mystique->vram_mask];
dst = svga->vram[(mystique->dwgreg.ydst_lin + x) & mystique->vram_mask];
if (!((!(mystique->dwgreg.dwgctrl_running & DWGCTRL_TRANSC) || (src & bltcmsk) != bltckey)))
break;
dst = bitop(src, dst, mystique->dwgreg.dwgctrl_running);
svga->vram[(mystique->dwgreg.ydst_lin + x) & mystique->vram_mask] = dst;
svga->changedvram[((mystique->dwgreg.ydst_lin + x) & mystique->vram_mask) >> 12] = changeframecount;
break;
case MACCESS_PWIDTH_16:
src = ((uint16_t *) svga->vram)[src_addr & mystique->vram_mask_w];
dst = ((uint16_t *) svga->vram)[(mystique->dwgreg.ydst_lin + x) & mystique->vram_mask_w];
if (!((!(mystique->dwgreg.dwgctrl_running & DWGCTRL_TRANSC) || (src & bltcmsk) != bltckey)))
break;
dst = bitop(src, dst, mystique->dwgreg.dwgctrl_running);
((uint16_t *) svga->vram)[(mystique->dwgreg.ydst_lin + x) & mystique->vram_mask_w] = dst;
svga->changedvram[((mystique->dwgreg.ydst_lin + x) & mystique->vram_mask_w) >> 11] = changeframecount;
break;
case MACCESS_PWIDTH_24:
src = *(uint32_t *) &svga->vram[(src_addr * 3) & mystique->vram_mask];
old_dst = *(uint32_t *) &svga->vram[((mystique->dwgreg.ydst_lin + x) * 3) & mystique->vram_mask];
if (!((!(mystique->dwgreg.dwgctrl_running & DWGCTRL_TRANSC) || (src & bltcmsk) != bltckey)))
break;
dst = bitop(src, old_dst, mystique->dwgreg.dwgctrl_running);
*(uint32_t *) &svga->vram[((mystique->dwgreg.ydst_lin + x) * 3) & mystique->vram_mask] = (dst & 0xffffff) | (old_dst & 0xff000000);
svga->changedvram[(((mystique->dwgreg.ydst_lin + x) * 3) & mystique->vram_mask) >> 12] = changeframecount;
break;
case MACCESS_PWIDTH_32:
src = ((uint32_t *) svga->vram)[src_addr & mystique->vram_mask_l];
dst = ((uint32_t *) svga->vram)[(mystique->dwgreg.ydst_lin + x) & mystique->vram_mask_l];
if (!((!(mystique->dwgreg.dwgctrl_running & DWGCTRL_TRANSC) || (src & bltcmsk) != bltckey)))
break;
dst = bitop(src, dst, mystique->dwgreg.dwgctrl_running);
((uint32_t *) svga->vram)[(mystique->dwgreg.ydst_lin + x) & mystique->vram_mask_l] = dst;
svga->changedvram[((mystique->dwgreg.ydst_lin + x) & mystique->vram_mask_l) >> 10] = changeframecount;
break;
default:
fatal("BITBLT RPL BFCOL PWIDTH %x %08x\n", mystique->maccess_running & MACCESS_PWIDTH_MASK, mystique->dwgreg.dwgctrl_running);
}
}
if (mystique->dwgreg.dwgctrl_running & DWGCTRL_PATTERN)
src_addr = ((src_addr + x_dir) & 7) | (src_addr & ~7);
else if (src_addr == mystique->dwgreg.ar[0]) {
mystique->dwgreg.ar[0] += mystique->dwgreg.ar[5];
mystique->dwgreg.ar[3] += mystique->dwgreg.ar[5];
src_addr = mystique->dwgreg.ar[3];
} else
src_addr += x_dir;
if (x != x_end) {
if ((x > x_end) && (x_dir == 1))
x--;
else if ((x < x_end) && (x_dir == -1))
x++;
else
x += x_dir;
} else
break;
}
if (mystique->dwgreg.dwgctrl_running & DWGCTRL_PATTERN) {
src_addr = old_src_addr;
if (mystique->dwgreg.sgn.sdy)
src_addr = ((src_addr - 32) & 0xe0) | (src_addr & ~0xe0);
else
src_addr = ((src_addr + 32) & 0xe0) | (src_addr & ~0xe0);
}
if (mystique->dwgreg.sgn.sdy)
mystique->dwgreg.ydst_lin -= (mystique->dwgreg.pitch & PITCH_MASK);
else
mystique->dwgreg.ydst_lin += (mystique->dwgreg.pitch & PITCH_MASK);
}
break;
default:
fatal("BITBLT DWGCTRL_ATYPE_RPL unknown BLTMOD %08x %08x\n", mystique->dwgreg.dwgctrl_running & DWGCTRL_BLTMOD_MASK, mystique->dwgreg.dwgctrl_running);
}
break;
default:
#if 0
pclog("Unknown BITBLT atype %03x %08x\n", mystique->dwgreg.dwgctrl_running & DWGCTRL_ATYPE_MASK, mystique->dwgreg.dwgctrl_running);
#endif
break;
}
mystique->blitter_complete_refcount++;
}
static void
blit_iload(mystique_t *mystique)
{
switch (mystique->dwgreg.dwgctrl_running & DWGCTRL_ATYPE_MASK) {
case DWGCTRL_ATYPE_RPL:
case DWGCTRL_ATYPE_RSTR:
case DWGCTRL_ATYPE_BLK:
#if 0
pclog("ILOAD BLTMOD DWGCTRL = %08x\n", mystique->dwgreg.dwgctrl_running & DWGCTRL_BLTMOD_MASK);
#endif
switch (mystique->dwgreg.dwgctrl_running & DWGCTRL_BLTMOD_MASK) {
case DWGCTRL_BLTMOD_BFCOL:
case DWGCTRL_BLTMOD_BMONOLEF:
case DWGCTRL_BLTMOD_BMONOWF:
case DWGCTRL_BLTMOD_BU24RGB:
case DWGCTRL_BLTMOD_BU32RGB:
mystique->dwgreg.length_cur = mystique->dwgreg.length;
mystique->dwgreg.xdst = mystique->dwgreg.fxleft;
mystique->dwgreg.iload_rem_data = 0;
mystique->dwgreg.iload_rem_count = 0;
mystique->busy = 1;
#if 0
pclog("ILOAD busy\n");
#endif
mystique->dwgreg.words = 0;
break;
default:
fatal("ILOAD DWGCTRL_ATYPE_RPL %08x %08x\n", mystique->dwgreg.dwgctrl_running & DWGCTRL_BLTMOD_MASK, mystique->dwgreg.dwgctrl_running);
break;
}
break;
default:
fatal("Unknown ILOAD atype %03x %08x\n", mystique->dwgreg.dwgctrl_running & DWGCTRL_ATYPE_MASK, mystique->dwgreg.dwgctrl_running);
}
}
static void
blit_idump(mystique_t *mystique)
{
switch (mystique->dwgreg.dwgctrl_running & DWGCTRL_ATYPE_MASK) {
case DWGCTRL_ATYPE_RPL:
mystique->dwgreg.length_cur = mystique->dwgreg.length;
mystique->dwgreg.xdst = mystique->dwgreg.fxleft;
mystique->dwgreg.src_addr = mystique->dwgreg.ar[3];
mystique->dwgreg.words = 0;
mystique->dwgreg.iload_rem_count = 0;
mystique->dwgreg.iload_rem_data = 0;
mystique->dwgreg.idump_end_of_line = 0;
mystique->busy = 1;
#if 0
pclog("IDUMP ATYPE RPL busy\n");
#endif
break;
default:
fatal("Unknown IDUMP atype %03x %08x\n", mystique->dwgreg.dwgctrl_running & DWGCTRL_ATYPE_MASK, mystique->dwgreg.dwgctrl_running);
}
}
static void
blit_iload_scale(mystique_t *mystique)
{
switch (mystique->dwgreg.dwgctrl_running & DWGCTRL_ATYPE_MASK) {
case DWGCTRL_ATYPE_RPL:
switch (mystique->dwgreg.dwgctrl_running & DWGCTRL_BLTMOD_MASK) {
case DWGCTRL_BLTMOD_BUYUV:
mystique->dwgreg.length_cur = mystique->dwgreg.length;
mystique->dwgreg.xdst = mystique->dwgreg.fxleft;
mystique->dwgreg.iload_rem_data = 0;
mystique->dwgreg.iload_rem_count = 0;
mystique->busy = 1;
mystique->dwgreg.words = 0;
/* pclog("ILOAD SCALE ATYPE RPL BLTMOD BUYUV busy\n"); */
break;
default:
fatal("ILOAD_SCALE DWGCTRL_ATYPE_RPL %08x %08x\n", mystique->dwgreg.dwgctrl_running & DWGCTRL_BLTMOD_MASK, mystique->dwgreg.dwgctrl_running);
break;
}
break;
default:
fatal("Unknown ILOAD_SCALE atype %03x %08x\n", mystique->dwgreg.dwgctrl_running & DWGCTRL_ATYPE_MASK, mystique->dwgreg.dwgctrl_running);
}
}
static void
blit_iload_high(mystique_t *mystique)
{
switch (mystique->dwgreg.dwgctrl_running & DWGCTRL_ATYPE_MASK) {
case DWGCTRL_ATYPE_RPL:
switch (mystique->dwgreg.dwgctrl_running & DWGCTRL_BLTMOD_MASK) {
case DWGCTRL_BLTMOD_BUYUV:
case DWGCTRL_BLTMOD_BU32BGR:
mystique->dwgreg.length_cur = mystique->dwgreg.length;
mystique->dwgreg.xdst = mystique->dwgreg.fxleft;
mystique->dwgreg.iload_rem_data = 0;
mystique->dwgreg.iload_rem_count = 0;
mystique->busy = 1;
mystique->dwgreg.words = 0;
/* pclog("ILOAD HIGH ATYPE RPL BLTMOD BUYUV busy\n"); */
break;
default:
fatal("ILOAD_HIGH DWGCTRL_ATYPE_RPL %08x %08x\n", mystique->dwgreg.dwgctrl_running & DWGCTRL_BLTMOD_MASK, mystique->dwgreg.dwgctrl_running);
break;
}
break;
default:
fatal("Unknown ILOAD_HIGH atype %03x %08x\n", mystique->dwgreg.dwgctrl_running & DWGCTRL_ATYPE_MASK, mystique->dwgreg.dwgctrl_running);
}
}
static void
blit_iload_highv(mystique_t *mystique)
{
switch (mystique->dwgreg.dwgctrl_running & DWGCTRL_ATYPE_MASK) {
case DWGCTRL_ATYPE_RPL:
switch (mystique->dwgreg.dwgctrl_running & DWGCTRL_BLTMOD_MASK) {
case DWGCTRL_BLTMOD_BUYUV:
mystique->dwgreg.length_cur = mystique->dwgreg.length;
mystique->dwgreg.xdst = mystique->dwgreg.fxleft;
mystique->dwgreg.iload_rem_data = 0;
mystique->dwgreg.iload_rem_count = 0;
mystique->busy = 1;
mystique->dwgreg.words = 0;
mystique->dwgreg.highv_line = 0;
mystique->dwgreg.lastpix_r = 0;
mystique->dwgreg.lastpix_g = 0;
mystique->dwgreg.lastpix_b = 0;
/* pclog("ILOAD HIGHV ATYPE RPL BLTMOD BUYUV busy\n"); */
break;
default:
fatal("ILOAD_HIGHV DWGCTRL_ATYPE_RPL %08x %08x\n", mystique->dwgreg.dwgctrl_running & DWGCTRL_BLTMOD_MASK, mystique->dwgreg.dwgctrl_running);
break;
}
break;
default:
fatal("Unknown ILOAD_HIGHV atype %03x %08x\n", mystique->dwgreg.dwgctrl_running & DWGCTRL_ATYPE_MASK, mystique->dwgreg.dwgctrl_running);
}
}
static void
mystique_start_blit(mystique_t *mystique)
{
svga_t *svga = &mystique->svga;
uint64_t start_time = plat_timer_read();
uint64_t end_time;
/*Make sure we don't get any artifacts.*/
svga->chain2_write = 0;
svga->chain2_read = 0;
mystique->dwgreg.dwgctrl_running = mystique->dwgreg.dwgctrl;
mystique->maccess_running = mystique->maccess;
switch (mystique->dwgreg.dwgctrl_running & DWGCTRL_OPCODE_MASK) {
case DWGCTRL_OPCODE_LINE_OPEN:
blit_line_start(mystique, 0, 0);
break;
case DWGCTRL_OPCODE_AUTOLINE_OPEN:
blit_line_start(mystique, 0, 1);
break;
case DWGCTRL_OPCODE_LINE_CLOSE:
blit_line_start(mystique, 1, 0);
break;
case DWGCTRL_OPCODE_AUTOLINE_CLOSE:
blit_line_start(mystique, 1, 1);
break;
case DWGCTRL_OPCODE_TRAP:
blit_trap(mystique);
break;
case DWGCTRL_OPCODE_TEXTURE_TRAP:
blit_texture_trap(mystique);
break;
case DWGCTRL_OPCODE_ILOAD_HIGH:
blit_iload_high(mystique);
break;
case DWGCTRL_OPCODE_BITBLT:
blit_bitblt(mystique);
break;
case DWGCTRL_OPCODE_FBITBLT:
blit_fbitblt(mystique);
break;
case DWGCTRL_OPCODE_ILOAD:
blit_iload(mystique);
break;
case DWGCTRL_OPCODE_IDUMP:
blit_idump(mystique);
break;
case DWGCTRL_OPCODE_ILOAD_SCALE:
blit_iload_scale(mystique);
break;
case DWGCTRL_OPCODE_ILOAD_HIGHV:
blit_iload_highv(mystique);
break;
case DWGCTRL_OPCODE_ILOAD_FILTER:
/* TODO: Actually implement this. */
break;
default:
fatal("mystique_start_blit: unknown blit %08x\n", mystique->dwgreg.dwgctrl_running & DWGCTRL_OPCODE_MASK);
break;
}
end_time = plat_timer_read();
mystique->blitter_time += end_time - start_time;
}
static void
mystique_hwcursor_draw(svga_t *svga, int displine)
{
const mystique_t *mystique = (mystique_t *) svga->priv;
uint64_t dat[2];
int offset = svga->hwcursor_latch.x - svga->hwcursor_latch.xoff;
if (svga->interlace && svga->hwcursor_oddeven)
svga->hwcursor_latch.addr += 16;
dat[0] = *(uint64_t *) (&svga->vram[svga->hwcursor_latch.addr]);
dat[1] = *(uint64_t *) (&svga->vram[svga->hwcursor_latch.addr + 8]);
svga->hwcursor_latch.addr += 16;
switch (mystique->xcurctrl & XCURCTRL_CURMODE_MASK) {
case XCURCTRL_CURMODE_XGA:
for (uint8_t x = 0; x < 64; x++) {
if (!(dat[1] & (1ULL << 63)))
svga->monitor->target_buffer->line[displine][(offset + svga->x_add) & 2047] = (dat[0] & (1ULL << 63)) ? svga_lookup_lut_ram(svga, mystique->cursor.col[1]) : svga_lookup_lut_ram(svga, mystique->cursor.col[0]);
else if (dat[0] & (1ULL << 63))
svga->monitor->target_buffer->line[displine][(offset + svga->x_add) & 2047] ^= 0xffffff;
offset++;
dat[0] <<= 1;
dat[1] <<= 1;
}
break;
case XCURCTRL_CURMODE_XWIN:
for (uint8_t x = 0; x < 64; x++) {
if ((dat[1] & (1ULL << 63)))
svga->monitor->target_buffer->line[displine][(offset + svga->x_add) & 2047] = (dat[0] & (1ULL << 63)) ? (mystique->cursor.col[1]) : (mystique->cursor.col[0]);
offset++;
dat[0] <<= 1;
dat[1] <<= 1;
}
break;
default:
break;
}
if (svga->interlace && !svga->hwcursor_oddeven)
svga->hwcursor_latch.addr += 16;
}
static uint8_t
mystique_tvp3026_gpio_read(uint8_t cntl, void *priv)
{
mystique_t *mystique = (mystique_t *) priv;
uint8_t ret = 0xff;
if (!i2c_gpio_get_scl(mystique->i2c_ddc))
ret &= ~0x10;
if (!i2c_gpio_get_sda(mystique->i2c_ddc))
ret &= ~0x04;
return ret;
}
static void
mystique_tvp3026_gpio_write(uint8_t cntl, uint8_t data, void *priv)
{
mystique_t *mystique = (mystique_t *) priv;
i2c_gpio_set(mystique->i2c_ddc, !(cntl & 0x10) || (data & 0x10), !(cntl & 0x04) || (data & 0x04));
}
static uint8_t
mystique_pci_read(UNUSED(int func), int addr, void *priv)
{
mystique_t *mystique = (mystique_t *) priv;
uint8_t ret = 0x00;
if ((addr >= 0x30) && (addr <= 0x33) && !(mystique->pci_regs[0x43] & 0x40))
ret = 0x00;
else
switch (addr) {
case 0x00:
ret = 0x2b;
break; /*Matrox*/
case 0x01:
ret = 0x10;
break;
case 0x02:
if (mystique->type == MGA_G100)
ret = 0x01;
else
ret = (mystique->type == MGA_2164W) ? 0x1b : ((mystique->type == MGA_2064W) ? 0x19 : 0x1a);
break; /*MGA*/
case 0x03:
if (mystique->type == MGA_G100)
ret = 0x10;
else
ret = 0x05;
break;
case PCI_REG_COMMAND:
ret = mystique->pci_regs[PCI_REG_COMMAND] | 0x80;
break; /*Respond to IO and memory accesses*/
case 0x05:
ret = 0x00;
break;
case 0x06:
ret = 0x80;
break;
case 0x07:
ret = mystique->pci_regs[0x07];
break; /*Fast DEVSEL timing*/
case 0x08:
ret = (mystique->type == MGA_1164SG) ? 3 : 0;
break; /*Revision ID*/
case 0x09:
ret = 0;
break; /*Programming interface*/
case 0x0a:
ret = 0x00;
break; /*Supports VGA interface*/
case 0x0b:
ret = 0x03;
break;
case 0x10:
ret = 0x00;
break; /*Control aperture for Millennium and Mystique, LFB for Mystique 220 and later*/
case 0x11:
if (mystique->type >= MGA_1164SG)
ret = 0x00;
else
ret = (mystique->ctrl_base >> 8) & 0xc0;
break;
case 0x12:
if (mystique->type >= MGA_1164SG)
ret = (mystique->type >= MGA_2164W) ? 0x00 : ((mystique->lfb_base >> 16) & 0x80);
else
ret = mystique->ctrl_base >> 16;
break;
case 0x13:
if (mystique->type >= MGA_1164SG)
ret = mystique->lfb_base >> 24;
else
ret = mystique->ctrl_base >> 24;
break;
case 0x14:
ret = 0x00;
break; /*LFB for Millennium and Mystique, Control aperture for Mystique 220 and later*/
case 0x15:
if (mystique->type >= MGA_1164SG)
ret = (mystique->ctrl_base >> 8) & 0xc0;
else
ret = 0x00;
break;
case 0x16:
if (mystique->type >= MGA_1164SG)
ret = mystique->ctrl_base >> 16;
else
ret = (mystique->lfb_base >> 16) & 0x80;
break;
case 0x17:
if (mystique->type >= MGA_1164SG)
ret = mystique->ctrl_base >> 24;
else
ret = mystique->lfb_base >> 24;
break;
case 0x18:
ret = 0x00;
break; /*Pseudo-DMA (ILOAD)*/
case 0x1a:
ret = (mystique->iload_base >> 16) & 0x80;
break;
case 0x1b:
ret = mystique->iload_base >> 24;
break;
case 0x2c:
ret = mystique->pci_regs[0x2c];
break;
case 0x2d:
ret = mystique->pci_regs[0x2d];
break;
case 0x2e:
ret = mystique->pci_regs[0x2e];
break;
case 0x2f:
ret = mystique->pci_regs[0x2f];
break;
case 0x30:
ret = mystique->pci_regs[0x30] & 0x01;
break; /*BIOS ROM address*/
case 0x31:
ret = 0x00;
break;
case 0x32:
ret = mystique->pci_regs[0x32];
break;
case 0x33:
ret = mystique->pci_regs[0x33];
break;
case 0x34:
ret = (mystique->type == MGA_G100) ? 0xdc : 0x00;
break;
case 0x3c:
ret = mystique->int_line;
break;
case 0x3d:
ret = PCI_INTA;
break;
case 0x40:
ret = mystique->pci_regs[0x40];
break;
case 0x41:
ret = mystique->pci_regs[0x41];
break;
case 0x42:
ret = mystique->pci_regs[0x42];
break;
case 0x43:
ret = mystique->pci_regs[0x43];
break;
case 0x44:
ret = mystique->pci_regs[0x44];
break;
case 0x45:
ret = mystique->pci_regs[0x45];
break;
case 0x48:
case 0x49:
case 0x4a:
case 0x4b:
addr = (mystique->pci_regs[0x44] & 0xfc) | ((mystique->pci_regs[0x45] & 0x3f) << 8) | (addr & 3);
ret = mystique_ctrl_read_b(addr, mystique);
break;
case 0xdc:
ret = 0x01;
break;
case 0xdd:
ret = 0xf0;
break;
case 0xde:
ret = 0x21;
break;
/* No support for turning off the video adapter yet. */
case 0xe0:
ret = 0x0;
break;
case 0xf0:
ret = 0x02;
break;
case 0xf1:
ret = 0x00;
break;
case 0xf2:
ret = 0x10;
break;
case 0xf4:
ret = 0x1;
break;
case 0xf5:
ret = 0x2;
break;
case 0xf7:
ret = 0x1;
break;
case 0xf8:
ret = mystique->pci_regs[0xf8] & 0x7;
break;
case 0xf9:
ret = mystique->pci_regs[0xf9] & 0x3;
break;
case 0xfb:
ret = mystique->pci_regs[0xfb];
break;
default:
break;
}
return ret;
}
static void
mystique_pci_write(UNUSED(int func), int addr, uint8_t val, void *priv)
{
mystique_t *mystique = (mystique_t *) priv;
switch (addr) {
case PCI_REG_COMMAND:
mystique->pci_regs[PCI_REG_COMMAND] = (val & 0x27) | 0x80;
mystique_recalc_mapping(mystique);
break;
case 0x07:
mystique->pci_regs[0x07] &= ~(val & 0x38);
break;
case 0x0d:
mystique->pci_regs[0x0d] = val;
break;
case 0x11:
if (mystique->type >= MGA_1164SG)
break;
else {
mystique->ctrl_base = (mystique->ctrl_base & 0xffff0000) | ((val & 0xc0) << 8);
mystique_recalc_mapping(mystique);
}
break;
case 0x12:
if (mystique->type >= MGA_1164SG) {
if (mystique->type >= MGA_2164W)
break;
mystique->lfb_base = (mystique->lfb_base & 0xff000000) | ((val & 0x80) << 16);
mystique_recalc_mapping(mystique);
} else {
mystique->ctrl_base = (mystique->ctrl_base & 0xff00c000) | (val << 16);
mystique_recalc_mapping(mystique);
}
break;
case 0x13:
if (mystique->type >= MGA_1164SG) {
if (mystique->type >= MGA_2164W)
mystique->lfb_base = val << 24;
else
mystique->lfb_base = (mystique->lfb_base & 0x00800000) | (val << 24);
mystique_recalc_mapping(mystique);
} else {
mystique->ctrl_base = (mystique->ctrl_base & 0x00ffc000) | (val << 24);
mystique_recalc_mapping(mystique);
}
break;
case 0x15:
if (mystique->type >= MGA_1164SG) {
mystique->ctrl_base = (mystique->ctrl_base & 0xffff0000) | ((val & 0xc0) << 8);
mystique_recalc_mapping(mystique);
}
break;
case 0x16:
if (mystique->type >= MGA_1164SG) {
mystique->ctrl_base = (mystique->ctrl_base & 0xff00c000) | (val << 16);
mystique_recalc_mapping(mystique);
} else {
mystique->lfb_base = (mystique->lfb_base & 0xff000000) | ((val & 0x80) << 16);
mystique_recalc_mapping(mystique);
}
break;
case 0x17:
if (mystique->type >= MGA_1164SG) {
mystique->ctrl_base = (mystique->ctrl_base & 0x00ffc000) | (val << 24);
mystique_recalc_mapping(mystique);
} else {
mystique->lfb_base = (mystique->lfb_base & 0x00800000) | (val << 24);
mystique_recalc_mapping(mystique);
}
break;
case 0x1a:
mystique->iload_base = (mystique->iload_base & 0xff000000) | ((val & 0x80) << 16);
mystique_recalc_mapping(mystique);
break;
case 0x1b:
mystique->iload_base = (mystique->iload_base & 0x00800000) | (val << 24);
mystique_recalc_mapping(mystique);
break;
case 0x30:
case 0x32:
case 0x33:
if (!(mystique->pci_regs[0x43] & 0x40))
return;
mystique->pci_regs[addr] = val;
if (addr == 0x30)
mystique->pci_regs[addr] &= 1;
if (mystique->pci_regs[0x30] & 0x01) {
uint32_t biosaddr = (mystique->pci_regs[0x32] << 16) | (mystique->pci_regs[0x33] << 24);
mem_mapping_set_addr(&mystique->bios_rom.mapping, biosaddr, (mystique->type == MGA_G100) ? 0x10000 : 0x8000);
} else
mem_mapping_disable(&mystique->bios_rom.mapping);
return;
case 0x3c:
mystique->int_line = val;
return;
case 0x40:
mystique->pci_regs[addr] = val & 0x3f;
break;
case 0x41:
mystique->pci_regs[addr] = val;
break;
case 0x42:
mystique->pci_regs[addr] = val & 0x1f;
break;
case 0x43:
mystique->pci_regs[addr] = val;
if (addr == 0x43) {
if (val & 0x40) {
if (mystique->pci_regs[0x30] & 0x01) {
uint32_t biosaddr = (mystique->pci_regs[0x32] << 16) | (mystique->pci_regs[0x33] << 24);
mem_mapping_set_addr(&mystique->bios_rom.mapping, biosaddr, (mystique->type == MGA_G100) ? 0x10000 : 0x8000);
} else
mem_mapping_disable(&mystique->bios_rom.mapping);
} else
mem_mapping_set_addr(&mystique->bios_rom.mapping, 0x000c0000, (mystique->type == MGA_G100) ? 0x10000 : 0x8000);
}
break;
case 0x4c:
case 0x4d:
case 0x4e:
case 0x4f:
mystique->pci_regs[addr - 0x20] = val;
break;
case 0x44:
mystique->pci_regs[addr] = val & 0xfc;
break;
case 0x45:
mystique->pci_regs[addr] = val & 0x3f;
break;
case 0x48:
case 0x49:
case 0x4a:
case 0x4b:
addr = (mystique->pci_regs[0x44] & 0xfc) | ((mystique->pci_regs[0x45] & 0x3f) << 8) | (addr & 3);
#if 0
pclog("mystique_ctrl_write_b(%04X, %02X)\n", addr, val);
#endif
mystique_ctrl_write_b(addr, val, mystique);
break;
case 0xf8:
mystique->pci_regs[0xf8] = val & 0x7;
break;
case 0xf9:
mystique->pci_regs[0xf9] = val & 0x3;
break;
case 0xfb:
mystique->pci_regs[0xfb] = val;
break;
default:
break;
}
}
static uint32_t
mystique_conv_16to32(svga_t* svga, uint16_t color, uint8_t bpp)
{
mystique_t *mystique = (mystique_t*)svga->priv;
uint32_t ret = 0x00000000;
if (svga->lut_map) {
if (bpp == 15) {
if (mystique->xgenctrl & (1 << 2))
color &= 0x7FFF;
#if 0
uint8_t b = getcolr(svga->pallook[(color & 0x1F) | (!!(color & 0x8000) >> 8)]);
uint8_t g = getcolg(svga->pallook[((color & 0x3E0) >> 5) | (!!(color & 0x8000) >> 8)]);
uint8_t r = getcolb(svga->pallook[((color & 0x7C00) >> 10) | (!!(color & 0x8000) >> 8)]);
#else
uint8_t b = getcolr(svga->pallook[color & 0x1f]);
uint8_t g = getcolg(svga->pallook[(color & 0x3e0) >> 5]);
uint8_t r = getcolb(svga->pallook[(color & 0x7c00) >> 10]);
#endif
ret = (video_15to32[color] & 0xFF000000) | makecol(r, g, b);
} else {
uint8_t b = getcolr(svga->pallook[color & 0x1f]);
uint8_t g = getcolg(svga->pallook[(color & 0x7e0) >> 5]);
uint8_t r = getcolb(svga->pallook[(color & 0xf800) >> 11]);
ret = (video_16to32[color] & 0xFF000000) | makecol(r, g, b);
}
} else
ret = (bpp == 15) ? video_15to32[color] : video_16to32[color];
return ret;
}
static void *
mystique_init(const device_t *info)
{
mystique_t *mystique = malloc(sizeof(mystique_t));
const char *romfn = NULL;
memset(mystique, 0, sizeof(mystique_t));
mystique->type = info->local;
if (mystique->type == MGA_2064W)
romfn = ROM_MILLENNIUM;
else if (mystique->type == MGA_2164W)
romfn = ROM_MILLENNIUM_II;
else if (mystique->type == MGA_1064SG)
romfn = ROM_MYSTIQUE;
else if (mystique->type == MGA_G100)
romfn = ROM_G100;
else
romfn = ROM_MYSTIQUE_220;
if (mystique->type == MGA_G100)
rom_init(&mystique->bios_rom, romfn, 0xc0000, 0x10000, 0xffff, 0, MEM_MAPPING_EXTERNAL);
else
rom_init(&mystique->bios_rom, romfn, 0xc0000, 0x8000, 0x7fff, 0, MEM_MAPPING_EXTERNAL);
mem_mapping_disable(&mystique->bios_rom.mapping);
mystique->vram_size = device_get_config_int("memory");
mystique->vram_mask = (mystique->vram_size << 20) - 1;
mystique->vram_mask_w = mystique->vram_mask >> 1;
mystique->vram_mask_l = mystique->vram_mask >> 2;
video_inform(VIDEO_FLAG_TYPE_SPECIAL, &timing_matrox_mystique);
if (mystique->type == MGA_2064W || mystique->type == MGA_2164W) {
video_inform(VIDEO_FLAG_TYPE_SPECIAL, (mystique->type == MGA_2164W) ? &timing_matrox_mystique : &timing_matrox_millennium);
svga_init(info, &mystique->svga, mystique, mystique->vram_size << 20,
mystique_recalctimings,
mystique_in, mystique_out,
NULL,
NULL);
mystique->svga.dac_hwcursor_draw = tvp3026_hwcursor_draw;
mystique->svga.ramdac = device_add(&tvp3026_ramdac_device);
mystique->svga.clock_gen = mystique->svga.ramdac;
mystique->svga.getclock = tvp3026_getclock;
mystique->svga.conv_16to32 = tvp3026_conv_16to32;
if (mystique->type == MGA_2164W)
mystique->svga.decode_mask = 0xffffff;
tvp3026_gpio(mystique_tvp3026_gpio_read, mystique_tvp3026_gpio_write, mystique, mystique->svga.ramdac);
} else {
video_inform(VIDEO_FLAG_TYPE_SPECIAL, &timing_matrox_mystique);
svga_init(info, &mystique->svga, mystique, mystique->vram_size << 20,
mystique_recalctimings,
mystique_in, mystique_out,
mystique_hwcursor_draw,
NULL);
mystique->svga.clock_gen = mystique;
mystique->svga.getclock = mystique_getclock;
if (mystique->type == MGA_G100)
mystique->svga.decode_mask = 0xffffff;
}
io_sethandler(0x03c0, 0x0020, mystique_in, NULL, NULL, mystique_out, NULL, NULL, mystique);
mem_mapping_add(&mystique->ctrl_mapping, 0, 0,
mystique_ctrl_read_b, NULL, mystique_ctrl_read_l,
mystique_ctrl_write_b, NULL, mystique_ctrl_write_l,
NULL, 0, mystique);
mem_mapping_disable(&mystique->ctrl_mapping);
mem_mapping_add(&mystique->lfb_mapping, 0, 0,
mystique_readb_linear, mystique_readw_linear, mystique_readl_linear,
mystique_writeb_linear, mystique_writew_linear, mystique_writel_linear,
NULL, 0, &mystique->svga);
mem_mapping_disable(&mystique->lfb_mapping);
mem_mapping_add(&mystique->iload_mapping, 0, 0,
mystique_iload_read_b, NULL, mystique_iload_read_l,
mystique_iload_write_b, NULL, mystique_iload_write_l,
NULL, 0, mystique);
mem_mapping_disable(&mystique->iload_mapping);
if (romfn == NULL)
pci_add_card(PCI_ADD_VIDEO, mystique_pci_read, mystique_pci_write, mystique, &mystique->pci_slot);
else
pci_add_card((info->flags & DEVICE_AGP) ? PCI_ADD_AGP : PCI_ADD_NORMAL, mystique_pci_read, mystique_pci_write, mystique, &mystique->pci_slot);
mystique->pci_regs[0x06] = 0x80;
mystique->pci_regs[0x07] = 0 << 1;
mystique->pci_regs[0x2c] = mystique->bios_rom.rom[0x7ff8];
mystique->pci_regs[0x2d] = mystique->bios_rom.rom[0x7ff9];
mystique->pci_regs[0x2e] = mystique->bios_rom.rom[0x7ffa];
mystique->pci_regs[0x2f] = mystique->bios_rom.rom[0x7ffb];
mystique->svga.miscout = 1;
mystique->pci_regs[0x41] = 0x01; /* vgaboot = 1 */
mystique->pci_regs[0x43] = 0x40; /* biosen = 1 */
for (uint16_t c = 0; c < 256; c++) {
dither5[c][0][0] = c >> 3;
dither5[c][1][1] = (c + 2) >> 3;
dither5[c][1][0] = (c + 4) >> 3;
dither5[c][0][1] = (c + 6) >> 3;
if (dither5[c][1][1] > 31)
dither5[c][1][1] = 31;
if (dither5[c][1][0] > 31)
dither5[c][1][0] = 31;
if (dither5[c][0][1] > 31)
dither5[c][0][1] = 31;
dither6[c][0][0] = c >> 2;
dither6[c][1][1] = (c + 1) >> 2;
dither6[c][1][0] = (c + 2) >> 2;
dither6[c][0][1] = (c + 3) >> 2;
if (dither6[c][1][1] > 63)
dither6[c][1][1] = 63;
if (dither6[c][1][0] > 63)
dither6[c][1][0] = 63;
if (dither6[c][0][1] > 63)
dither6[c][0][1] = 63;
}
mystique->wake_fifo_thread = thread_create_event();
mystique->fifo_not_full_event = thread_create_event();
mystique->thread_run = 1;
mystique->fifo_thread = thread_create(fifo_thread, mystique);
mystique->dma.lock = thread_create_mutex();
timer_add(&mystique->wake_timer, mystique_wake_timer, (void *) mystique, 0);
timer_add(&mystique->softrap_pending_timer, mystique_softrap_pending_timer, (void *) mystique, 1);
mystique->status = STATUS_ENDPRDMASTS;
mystique->softrap_status_read = 1;
mystique->svga.vsync_callback = mystique_vsync_callback;
if (mystique->type != MGA_2064W && mystique->type != MGA_2164W)
mystique->svga.conv_16to32 = mystique_conv_16to32;
mystique->i2c = i2c_gpio_init("i2c_mga");
mystique->i2c_ddc = i2c_gpio_init("ddc_mga");
mystique->ddc = ddc_init(i2c_gpio_get_bus(mystique->i2c_ddc));
return mystique;
}
static void
mystique_close(void *priv)
{
mystique_t *mystique = (mystique_t *) priv;
mystique->thread_run = 0;
thread_set_event(mystique->wake_fifo_thread);
thread_wait(mystique->fifo_thread);
thread_destroy_event(mystique->wake_fifo_thread);
thread_destroy_event(mystique->fifo_not_full_event);
thread_close_mutex(mystique->dma.lock);
svga_close(&mystique->svga);
ddc_close(mystique->ddc);
i2c_gpio_close(mystique->i2c_ddc);
i2c_gpio_close(mystique->i2c);
free(mystique);
}
static int
millennium_available(void)
{
return rom_present(ROM_MILLENNIUM);
}
static int
mystique_available(void)
{
return rom_present(ROM_MYSTIQUE);
}
static int
mystique_220_available(void)
{
return rom_present(ROM_MYSTIQUE_220);
}
static int
millennium_ii_available(void)
{
return rom_present(ROM_MILLENNIUM_II);
}
#ifdef USE_G100
static int
matrox_g100_available(void)
{
return rom_present(ROM_G100);
}
#endif
static void
mystique_speed_changed(void *priv)
{
mystique_t *mystique = (mystique_t *) priv;
svga_recalctimings(&mystique->svga);
}
static void
mystique_force_redraw(void *priv)
{
mystique_t *mystique = (mystique_t *) priv;
mystique->svga.fullchange = changeframecount;
}
static const device_config_t mystique_config[] = {
// clang-format off
{
.name = "memory",
.description = "Memory size",
.type = CONFIG_SELECTION,
.selection =
{
{
.description = "2 MB",
.value = 2
},
{
.description = "4 MB",
.value = 4
},
{
.description = "8 MB",
.value = 8
},
{
.description = ""
}
},
.default_int = 8
},
{
.type = CONFIG_END
}
// clang-format on
};
static const device_config_t millennium_ii_config[] = {
// clang-format off
{
.name = "memory",
.description = "Memory size",
.type = CONFIG_SELECTION,
.selection =
{
{
.description = "4 MB",
.value = 4
},
{
.description = "8 MB",
.value = 8
},
{
.description = "16 MB",
.value = 16
},
{
.description = ""
}
},
.default_int = 8
},
{
.type = CONFIG_END
}
// clang-format on
};
const device_t millennium_device = {
.name = "Matrox Millennium",
.internal_name = "millennium",
.flags = DEVICE_PCI,
.local = MGA_2064W,
.init = mystique_init,
.close = mystique_close,
.reset = NULL,
{ .available = millennium_available },
.speed_changed = mystique_speed_changed,
.force_redraw = mystique_force_redraw,
.config = mystique_config
};
const device_t mystique_device = {
.name = "Matrox Mystique",
.internal_name = "mystique",
.flags = DEVICE_PCI,
.local = MGA_1064SG,
.init = mystique_init,
.close = mystique_close,
.reset = NULL,
{ .available = mystique_available },
.speed_changed = mystique_speed_changed,
.force_redraw = mystique_force_redraw,
.config = mystique_config
};
const device_t mystique_220_device = {
.name = "Matrox Mystique 220",
.internal_name = "mystique_220",
.flags = DEVICE_PCI,
.local = MGA_1164SG,
.init = mystique_init,
.close = mystique_close,
.reset = NULL,
{ .available = mystique_220_available },
.speed_changed = mystique_speed_changed,
.force_redraw = mystique_force_redraw,
.config = mystique_config
};
const device_t millennium_ii_device = {
.name = "Matrox Millennium II",
.internal_name = "millennium_ii",
.flags = DEVICE_PCI,
.local = MGA_2164W,
.init = mystique_init,
.close = mystique_close,
.reset = NULL,
{ .available = millennium_ii_available },
.speed_changed = mystique_speed_changed,
.force_redraw = mystique_force_redraw,
.config = millennium_ii_config
};
#ifdef USE_G100
const device_t productiva_g100_device = {
.name = "Matrox Productiva G100",
.internal_name = "productiva_g100",
.flags = DEVICE_AGP,
.local = MGA_G100,
.init = mystique_init,
.close = mystique_close,
.reset = NULL,
{ .available = matrox_g100_available },
.speed_changed = mystique_speed_changed,
.force_redraw = mystique_force_redraw,
.config = millennium_ii_config
};
#endif
``` | /content/code_sandbox/src/video/vid_mga.c | c | 2016-06-25T22:29:10 | 2024-08-16T19:09:21 | 86Box | 86Box/86Box | 2,616 | 79,594 |
```c
/*
* 86Box A hypervisor and IBM PC system emulator that specializes in
* running old operating systems and software designed for IBM
* PC systems and compatibles from 1981 through fairly recent
* system designs based on the PCI bus.
*
* This file is part of the 86Box distribution.
*
* 3DFX Voodoo emulation.
*
*
*
* Authors: Sarah Walker, <path_to_url
*
*/
#include <stdarg.h>
#include <stdio.h>
#include <stdint.h>
#include <string.h>
#include <stdlib.h>
#include <stddef.h>
#include <wchar.h>
#include <math.h>
#define HAVE_STDARG_H
#include <86box/86box.h>
#include "cpu.h"
#include <86box/machine.h>
#include <86box/device.h>
#include <86box/mem.h>
#include <86box/timer.h>
#include <86box/device.h>
#include <86box/plat.h>
#include <86box/thread.h>
#include <86box/video.h>
#include <86box/vid_svga.h>
#include <86box/vid_voodoo_common.h>
#include <86box/vid_voodoo_dither.h>
#include <86box/vid_voodoo_regs.h>
#include <86box/vid_voodoo_render.h>
#include <86box/vid_voodoo_texture.h>
#ifdef ENABLE_VOODOO_TEXTURE_LOG
int voodoo_texture_do_log = ENABLE_VOODOO_TEXTURE_LOG;
static void
voodoo_texture_log(const char *fmt, ...)
{
va_list ap;
if (voodoo_texture_do_log) {
va_start(ap, fmt);
pclog_ex(fmt, ap);
va_end(ap);
}
}
#else
# define voodoo_texture_log(fmt, ...)
#endif
void
voodoo_recalc_tex12(voodoo_t *voodoo, int tmu)
{
int aspect = (voodoo->params.tLOD[tmu] >> 21) & 3;
int width = 256;
int height = 256;
int shift = 8;
uint32_t base = voodoo->params.texBaseAddr[tmu];
uint32_t offset = 0;
int tex_lod = 0;
if (voodoo->params.tLOD[tmu] & LOD_S_IS_WIDER)
height >>= aspect;
else {
width >>= aspect;
shift -= aspect;
}
if ((voodoo->params.tLOD[tmu] & LOD_SPLIT) && (voodoo->params.tLOD[tmu] & LOD_ODD)) {
width >>= 1;
height >>= 1;
shift--;
tex_lod++;
if (voodoo->params.tLOD[tmu] & LOD_TMULTIBASEADDR)
base = voodoo->params.texBaseAddr1[tmu];
}
for (uint8_t lod = 0; lod <= LOD_MAX + 1; lod++) {
if (!width)
width = 1;
if (!height)
height = 1;
if (shift < 0)
shift = 0;
voodoo->params.tex_base[tmu][lod] = base + offset;
if (voodoo->params.tformat[tmu] & 8)
voodoo->params.tex_end[tmu][lod] = base + offset + (width * height * 2);
else
voodoo->params.tex_end[tmu][lod] = base + offset + (width * height);
voodoo->params.tex_w_mask[tmu][lod] = width - 1;
voodoo->params.tex_w_nmask[tmu][lod] = ~(width - 1);
voodoo->params.tex_h_mask[tmu][lod] = height - 1;
voodoo->params.tex_shift[tmu][lod] = shift;
voodoo->params.tex_lod[tmu][lod] = tex_lod;
if (!(voodoo->params.tLOD[tmu] & LOD_SPLIT) || ((lod & 1) && (voodoo->params.tLOD[tmu] & LOD_ODD)) || (!(lod & 1) && !(voodoo->params.tLOD[tmu] & LOD_ODD))) {
if (!(voodoo->params.tLOD[tmu] & LOD_ODD) || lod != 0) {
if (voodoo->params.tformat[tmu] & 8)
offset += width * height * 2;
else
offset += width * height;
if (voodoo->params.tLOD[tmu] & LOD_SPLIT) {
width >>= 2;
height >>= 2;
shift -= 2;
tex_lod += 2;
} else {
width >>= 1;
height >>= 1;
shift--;
tex_lod++;
}
if (voodoo->params.tLOD[tmu] & LOD_TMULTIBASEADDR) {
switch (tex_lod) {
case 0:
base = voodoo->params.texBaseAddr[tmu];
break;
case 1:
base = voodoo->params.texBaseAddr1[tmu];
break;
case 2:
base = voodoo->params.texBaseAddr2[tmu];
break;
default:
base = voodoo->params.texBaseAddr38[tmu];
break;
}
}
}
}
}
voodoo->params.tex_width[tmu] = width;
}
void
voodoo_recalc_tex3(voodoo_t *voodoo, int tmu)
{
int aspect = (voodoo->params.tLOD[tmu] >> 21) & 3;
int width = 256;
int height = 256;
int shift = 8;
int lod;
uint32_t base = voodoo->params.texBaseAddr[tmu];
uint32_t offset = 0;
int tex_lod = 0;
uint32_t offsets[LOD_MAX + 3];
int widths[LOD_MAX + 3];
int heights[LOD_MAX + 3];
int shifts[LOD_MAX + 3];
if (voodoo->params.tLOD[tmu] & LOD_S_IS_WIDER)
height >>= aspect;
else {
width >>= aspect;
shift -= aspect;
}
for (lod = 0; lod <= LOD_MAX + 2; lod++) {
offsets[lod] = offset;
widths[lod] = width >> lod;
heights[lod] = height >> lod;
shifts[lod] = shift - lod;
if (!widths[lod])
widths[lod] = 1;
if (!heights[lod])
heights[lod] = 1;
if (shifts[lod] < 0)
shifts[lod] = 0;
if (!(voodoo->params.tLOD[tmu] & LOD_SPLIT) || ((lod & 1) && (voodoo->params.tLOD[tmu] & LOD_ODD)) || (!(lod & 1) && !(voodoo->params.tLOD[tmu] & LOD_ODD))) {
if (voodoo->params.tformat[tmu] & 8)
offset += (width >> lod) * (height >> lod) * 2;
else
offset += (width >> lod) * (height >> lod);
}
}
if ((voodoo->params.textureMode[tmu] & TEXTUREMODE_TRILINEAR) && (voodoo->params.tLOD[tmu] & LOD_ODD))
tex_lod++; /*Skip LOD 0*/
#if 0
voodoo_texture_log("TMU %i: %08x\n", tmu, voodoo->params.textureMode[tmu]);
#endif
for (lod = 0; lod <= LOD_MAX + 1; lod++) {
if (voodoo->params.tLOD[tmu] & LOD_TMULTIBASEADDR) {
switch (tex_lod) {
case 0:
base = voodoo->params.texBaseAddr[tmu];
break;
case 1:
base = voodoo->params.texBaseAddr1[tmu];
break;
case 2:
base = voodoo->params.texBaseAddr2[tmu];
break;
default:
base = voodoo->params.texBaseAddr38[tmu];
break;
}
}
voodoo->params.tex_base[tmu][lod] = base + offsets[tex_lod];
if (voodoo->params.tformat[tmu] & 8)
voodoo->params.tex_end[tmu][lod] = base + offsets[tex_lod] + (widths[tex_lod] * heights[tex_lod] * 2);
else
voodoo->params.tex_end[tmu][lod] = base + offsets[tex_lod] + (widths[tex_lod] * heights[tex_lod]);
voodoo->params.tex_w_mask[tmu][lod] = widths[tex_lod] - 1;
voodoo->params.tex_w_nmask[tmu][lod] = ~(widths[tex_lod] - 1);
voodoo->params.tex_h_mask[tmu][lod] = heights[tex_lod] - 1;
voodoo->params.tex_shift[tmu][lod] = shifts[tex_lod];
voodoo->params.tex_lod[tmu][lod] = tex_lod;
if (!(voodoo->params.textureMode[tmu] & TEXTUREMODE_TRILINEAR) || ((lod & 1) && (voodoo->params.tLOD[tmu] & LOD_ODD)) || (!(lod & 1) && !(voodoo->params.tLOD[tmu] & LOD_ODD))) {
if (!(voodoo->params.tLOD[tmu] & LOD_ODD) || lod != 0) {
if (voodoo->params.textureMode[tmu] & TEXTUREMODE_TRILINEAR)
tex_lod += 2;
else
tex_lod++;
}
}
}
voodoo->params.tex_width[tmu] = width;
}
#define makergba(r, g, b, a) ((b) | ((g) << 8) | ((r) << 16) | ((a) << 24))
void
voodoo_use_texture(voodoo_t *voodoo, voodoo_params_t *params, int tmu)
{
int c;
int lod_min;
int lod_max;
uint32_t addr = 0;
uint32_t addr_end;
uint32_t palette_checksum;
lod_min = (params->tLOD[tmu] >> 2) & 15;
lod_max = (params->tLOD[tmu] >> 8) & 15;
if (params->tformat[tmu] == TEX_PAL8 || params->tformat[tmu] == TEX_APAL8 || params->tformat[tmu] == TEX_APAL88) {
if (voodoo->palette_dirty[tmu]) {
palette_checksum = 0;
for (c = 0; c < 256; c++)
palette_checksum ^= voodoo->palette[tmu][c].u;
voodoo->palette_checksum[tmu] = palette_checksum;
voodoo->palette_dirty[tmu] = 0;
} else
palette_checksum = voodoo->palette_checksum[tmu];
} else
palette_checksum = 0;
if ((voodoo->params.tLOD[tmu] & LOD_SPLIT) && (voodoo->params.tLOD[tmu] & LOD_ODD) && (voodoo->params.tLOD[tmu] & LOD_TMULTIBASEADDR))
addr = params->texBaseAddr1[tmu];
else
addr = params->texBaseAddr[tmu];
/*Try to find texture in cache*/
for (c = 0; c < TEX_CACHE_MAX; c++) {
if (voodoo->texture_cache[tmu][c].base == addr && voodoo->texture_cache[tmu][c].tLOD == (params->tLOD[tmu] & 0xf00fff) && voodoo->texture_cache[tmu][c].palette_checksum == palette_checksum) {
params->tex_entry[tmu] = c;
voodoo->texture_cache[tmu][c].refcount++;
return;
}
}
/*Texture not found, search for unused texture*/
do {
for (c = 0; c < TEX_CACHE_MAX; c++) {
voodoo->texture_last_removed++;
voodoo->texture_last_removed &= (TEX_CACHE_MAX - 1);
if (voodoo->texture_cache[tmu][voodoo->texture_last_removed].refcount == voodoo->texture_cache[tmu][voodoo->texture_last_removed].refcount_r[0] && (voodoo->render_threads == 1 || voodoo->texture_cache[tmu][voodoo->texture_last_removed].refcount == voodoo->texture_cache[tmu][voodoo->texture_last_removed].refcount_r[1]))
break;
}
if (c == TEX_CACHE_MAX)
voodoo_wait_for_render_thread_idle(voodoo);
} while (c == TEX_CACHE_MAX);
if (c == TEX_CACHE_MAX)
fatal("Texture cache full!\n");
c = voodoo->texture_last_removed;
if ((voodoo->params.tLOD[tmu] & LOD_SPLIT) && (voodoo->params.tLOD[tmu] & LOD_ODD) && (voodoo->params.tLOD[tmu] & LOD_TMULTIBASEADDR))
voodoo->texture_cache[tmu][c].base = params->texBaseAddr1[tmu];
else
voodoo->texture_cache[tmu][c].base = params->texBaseAddr[tmu];
voodoo->texture_cache[tmu][c].tLOD = params->tLOD[tmu] & 0xf00fff;
lod_min = (params->tLOD[tmu] >> 2) & 15;
lod_max = (params->tLOD[tmu] >> 8) & 15;
#if 0
voodoo_texture_log(" add new texture to %i tformat=%i %08x LOD=%i-%i tmu=%i\n", c, voodoo->params.tformat[tmu], params->texBaseAddr[tmu], lod_min, lod_max, tmu);
#endif
lod_min = MIN(lod_min, 8);
lod_max = MIN(lod_max, 8);
for (int lod = lod_min; lod <= lod_max; lod++) {
uint32_t *base = &voodoo->texture_cache[tmu][c].data[texture_offset[lod]];
uint32_t tex_addr = params->tex_base[tmu][lod] & voodoo->texture_mask;
int x;
int y;
int shift = 8 - params->tex_lod[tmu][lod];
const rgba_u *pal;
#if 0
voodoo_texture_log(" LOD %i : %08x - %08x %i %i,%i\n", lod, params->tex_base[tmu][lod] & voodoo->texture_mask, addr, voodoo->params.tformat[tmu], voodoo->params.tex_w_mask[tmu][lod],voodoo->params.tex_h_mask[tmu][lod]);
#endif
switch (params->tformat[tmu]) {
case TEX_RGB332:
for (y = 0; y < voodoo->params.tex_h_mask[tmu][lod] + 1; y++) {
for (x = 0; x < voodoo->params.tex_w_mask[tmu][lod] + 1; x++) {
uint8_t dat = voodoo->tex_mem[tmu][(tex_addr + x) & voodoo->texture_mask];
base[x] = makergba(rgb332[dat].r, rgb332[dat].g, rgb332[dat].b, 0xff);
}
tex_addr += (1 << voodoo->params.tex_shift[tmu][lod]);
base += (1 << shift);
}
break;
case TEX_Y4I2Q2:
pal = voodoo->ncc_lookup[tmu][(voodoo->params.textureMode[tmu] & TEXTUREMODE_NCC_SEL) ? 1 : 0];
for (y = 0; y < voodoo->params.tex_h_mask[tmu][lod] + 1; y++) {
for (x = 0; x < voodoo->params.tex_w_mask[tmu][lod] + 1; x++) {
uint8_t dat = voodoo->tex_mem[tmu][(tex_addr + x) & voodoo->texture_mask];
base[x] = makergba(pal[dat].rgba.r, pal[dat].rgba.g, pal[dat].rgba.b, 0xff);
}
tex_addr += (1 << voodoo->params.tex_shift[tmu][lod]);
base += (1 << shift);
}
break;
case TEX_A8:
for (y = 0; y < voodoo->params.tex_h_mask[tmu][lod] + 1; y++) {
for (x = 0; x < voodoo->params.tex_w_mask[tmu][lod] + 1; x++) {
uint8_t dat = voodoo->tex_mem[tmu][(tex_addr + x) & voodoo->texture_mask];
base[x] = makergba(dat, dat, dat, dat);
}
tex_addr += (1 << voodoo->params.tex_shift[tmu][lod]);
base += (1 << shift);
}
break;
case TEX_I8:
for (y = 0; y < voodoo->params.tex_h_mask[tmu][lod] + 1; y++) {
for (x = 0; x < voodoo->params.tex_w_mask[tmu][lod] + 1; x++) {
uint8_t dat = voodoo->tex_mem[tmu][(tex_addr + x) & voodoo->texture_mask];
base[x] = makergba(dat, dat, dat, 0xff);
}
tex_addr += (1 << voodoo->params.tex_shift[tmu][lod]);
base += (1 << shift);
}
break;
case TEX_AI8:
for (y = 0; y < voodoo->params.tex_h_mask[tmu][lod] + 1; y++) {
for (x = 0; x < voodoo->params.tex_w_mask[tmu][lod] + 1; x++) {
uint8_t dat = voodoo->tex_mem[tmu][(tex_addr + x) & voodoo->texture_mask];
base[x] = makergba((dat & 0x0f) | ((dat << 4) & 0xf0), (dat & 0x0f) | ((dat << 4) & 0xf0), (dat & 0x0f) | ((dat << 4) & 0xf0), (dat & 0xf0) | ((dat >> 4) & 0x0f));
}
tex_addr += (1 << voodoo->params.tex_shift[tmu][lod]);
base += (1 << shift);
}
break;
case TEX_PAL8:
pal = voodoo->palette[tmu];
for (y = 0; y < voodoo->params.tex_h_mask[tmu][lod] + 1; y++) {
for (x = 0; x < voodoo->params.tex_w_mask[tmu][lod] + 1; x++) {
uint8_t dat = voodoo->tex_mem[tmu][(tex_addr + x) & voodoo->texture_mask];
base[x] = makergba(pal[dat].rgba.r, pal[dat].rgba.g, pal[dat].rgba.b, 0xff);
}
tex_addr += (1 << voodoo->params.tex_shift[tmu][lod]);
base += (1 << shift);
}
break;
case TEX_APAL8:
pal = voodoo->palette[tmu];
for (y = 0; y < voodoo->params.tex_h_mask[tmu][lod] + 1; y++) {
for (x = 0; x < voodoo->params.tex_w_mask[tmu][lod] + 1; x++) {
uint8_t dat = voodoo->tex_mem[tmu][(tex_addr + x) & voodoo->texture_mask];
int r = ((pal[dat].rgba.r & 3) << 6) | ((pal[dat].rgba.g & 0xf0) >> 2) | (pal[dat].rgba.r & 3);
int g = ((pal[dat].rgba.g & 0xf) << 4) | ((pal[dat].rgba.b & 0xc0) >> 4) | ((pal[dat].rgba.g & 0xf) >> 2);
int b = ((pal[dat].rgba.b & 0x3f) << 2) | ((pal[dat].rgba.b & 0x30) >> 4);
int a = (pal[dat].rgba.r & 0xfc) | ((pal[dat].rgba.r & 0xc0) >> 6);
base[x] = makergba(r, g, b, a);
}
tex_addr += (1 << voodoo->params.tex_shift[tmu][lod]);
base += (1 << shift);
}
break;
case TEX_ARGB8332:
for (y = 0; y < voodoo->params.tex_h_mask[tmu][lod] + 1; y++) {
for (x = 0; x < voodoo->params.tex_w_mask[tmu][lod] + 1; x++) {
uint16_t dat = *(uint16_t *) &voodoo->tex_mem[tmu][(tex_addr + x * 2) & voodoo->texture_mask];
base[x] = makergba(rgb332[dat & 0xff].r, rgb332[dat & 0xff].g, rgb332[dat & 0xff].b, dat >> 8);
}
tex_addr += (1 << (voodoo->params.tex_shift[tmu][lod] + 1));
base += (1 << shift);
}
break;
case TEX_A8Y4I2Q2:
pal = voodoo->ncc_lookup[tmu][(voodoo->params.textureMode[tmu] & TEXTUREMODE_NCC_SEL) ? 1 : 0];
for (y = 0; y < voodoo->params.tex_h_mask[tmu][lod] + 1; y++) {
for (x = 0; x < voodoo->params.tex_w_mask[tmu][lod] + 1; x++) {
uint16_t dat = *(uint16_t *) &voodoo->tex_mem[tmu][(tex_addr + x * 2) & voodoo->texture_mask];
base[x] = makergba(pal[dat & 0xff].rgba.r, pal[dat & 0xff].rgba.g, pal[dat & 0xff].rgba.b, dat >> 8);
}
tex_addr += (1 << (voodoo->params.tex_shift[tmu][lod] + 1));
base += (1 << shift);
}
break;
case TEX_R5G6B5:
for (y = 0; y < voodoo->params.tex_h_mask[tmu][lod] + 1; y++) {
for (x = 0; x < voodoo->params.tex_w_mask[tmu][lod] + 1; x++) {
uint16_t dat = *(uint16_t *) &voodoo->tex_mem[tmu][(tex_addr + x * 2) & voodoo->texture_mask];
base[x] = makergba(rgb565[dat].r, rgb565[dat].g, rgb565[dat].b, 0xff);
}
tex_addr += (1 << (voodoo->params.tex_shift[tmu][lod] + 1));
base += (1 << shift);
}
break;
case TEX_ARGB1555:
for (y = 0; y < voodoo->params.tex_h_mask[tmu][lod] + 1; y++) {
for (x = 0; x < voodoo->params.tex_w_mask[tmu][lod] + 1; x++) {
uint16_t dat = *(uint16_t *) &voodoo->tex_mem[tmu][(tex_addr + x * 2) & voodoo->texture_mask];
base[x] = makergba(argb1555[dat].r, argb1555[dat].g, argb1555[dat].b, argb1555[dat].a);
}
tex_addr += (1 << (voodoo->params.tex_shift[tmu][lod] + 1));
base += (1 << shift);
}
break;
case TEX_ARGB4444:
for (y = 0; y < voodoo->params.tex_h_mask[tmu][lod] + 1; y++) {
for (x = 0; x < voodoo->params.tex_w_mask[tmu][lod] + 1; x++) {
uint16_t dat = *(uint16_t *) &voodoo->tex_mem[tmu][(tex_addr + x * 2) & voodoo->texture_mask];
base[x] = makergba(argb4444[dat].r, argb4444[dat].g, argb4444[dat].b, argb4444[dat].a);
}
tex_addr += (1 << (voodoo->params.tex_shift[tmu][lod] + 1));
base += (1 << shift);
}
break;
case TEX_A8I8:
for (y = 0; y < voodoo->params.tex_h_mask[tmu][lod] + 1; y++) {
for (x = 0; x < voodoo->params.tex_w_mask[tmu][lod] + 1; x++) {
uint16_t dat = *(uint16_t *) &voodoo->tex_mem[tmu][(tex_addr + x * 2) & voodoo->texture_mask];
base[x] = makergba(dat & 0xff, dat & 0xff, dat & 0xff, dat >> 8);
}
tex_addr += (1 << (voodoo->params.tex_shift[tmu][lod] + 1));
base += (1 << shift);
}
break;
case TEX_APAL88:
pal = voodoo->palette[tmu];
for (y = 0; y < voodoo->params.tex_h_mask[tmu][lod] + 1; y++) {
for (x = 0; x < voodoo->params.tex_w_mask[tmu][lod] + 1; x++) {
uint16_t dat = *(uint16_t *) &voodoo->tex_mem[tmu][(tex_addr + x * 2) & voodoo->texture_mask];
base[x] = makergba(pal[dat & 0xff].rgba.r, pal[dat & 0xff].rgba.g, pal[dat & 0xff].rgba.b, dat >> 8);
}
tex_addr += (1 << (voodoo->params.tex_shift[tmu][lod] + 1));
base += (1 << shift);
}
break;
default:
fatal("Unknown texture format %i\n", params->tformat[tmu]);
}
}
voodoo->texture_cache[tmu][c].is16 = voodoo->params.tformat[tmu] & 8;
if (params->tformat[tmu] == TEX_PAL8 || params->tformat[tmu] == TEX_APAL8 || params->tformat[tmu] == TEX_APAL88)
voodoo->texture_cache[tmu][c].palette_checksum = palette_checksum;
else
voodoo->texture_cache[tmu][c].palette_checksum = 0;
if (lod_min == 0) {
voodoo->texture_cache[tmu][c].addr_start[0] = voodoo->params.tex_base[tmu][0];
voodoo->texture_cache[tmu][c].addr_end[0] = voodoo->params.tex_end[tmu][0];
} else
voodoo->texture_cache[tmu][c].addr_start[0] = voodoo->texture_cache[tmu][c].addr_end[0] = 0;
if (lod_min <= 1 && lod_max >= 1) {
voodoo->texture_cache[tmu][c].addr_start[1] = voodoo->params.tex_base[tmu][1];
voodoo->texture_cache[tmu][c].addr_end[1] = voodoo->params.tex_end[tmu][1];
} else
voodoo->texture_cache[tmu][c].addr_start[1] = voodoo->texture_cache[tmu][c].addr_end[1] = 0;
if (lod_min <= 2 && lod_max >= 2) {
voodoo->texture_cache[tmu][c].addr_start[2] = voodoo->params.tex_base[tmu][2];
voodoo->texture_cache[tmu][c].addr_end[2] = voodoo->params.tex_end[tmu][2];
} else
voodoo->texture_cache[tmu][c].addr_start[2] = voodoo->texture_cache[tmu][c].addr_end[2] = 0;
if (lod_max >= 3) {
voodoo->texture_cache[tmu][c].addr_start[3] = voodoo->params.tex_base[tmu][(lod_min > 3) ? lod_min : 3];
voodoo->texture_cache[tmu][c].addr_end[3] = voodoo->params.tex_end[tmu][(lod_max < 8) ? lod_max : 8];
} else
voodoo->texture_cache[tmu][c].addr_start[3] = voodoo->texture_cache[tmu][c].addr_end[3] = 0;
for (uint8_t d = 0; d < 4; d++) {
addr = voodoo->texture_cache[tmu][c].addr_start[d];
addr_end = voodoo->texture_cache[tmu][c].addr_end[d];
if (addr_end != 0) {
for (; addr <= addr_end; addr += (1 << TEX_DIRTY_SHIFT))
voodoo->texture_present[tmu][(addr & voodoo->texture_mask) >> TEX_DIRTY_SHIFT] = 1;
}
}
params->tex_entry[tmu] = c;
voodoo->texture_cache[tmu][c].refcount++;
}
void
flush_texture_cache(voodoo_t *voodoo, uint32_t dirty_addr, int tmu)
{
int wait_for_idle = 0;
memset(voodoo->texture_present[tmu], 0, sizeof(voodoo->texture_present[0]));
#if 0
voodoo_texture_log("Evict %08x %i\n", dirty_addr, sizeof(voodoo->texture_present));
#endif
for (uint8_t c = 0; c < TEX_CACHE_MAX; c++) {
if (voodoo->texture_cache[tmu][c].base != -1) {
for (uint8_t d = 0; d < 4; d++) {
int addr_start = voodoo->texture_cache[tmu][c].addr_start[d];
int addr_end = voodoo->texture_cache[tmu][c].addr_end[d];
if (addr_end != 0) {
int addr_start_masked = addr_start & voodoo->texture_mask & ~0x3ff;
int addr_end_masked = ((addr_end & voodoo->texture_mask) + 0x3ff) & ~0x3ff;
if (addr_end_masked < addr_start_masked)
addr_end_masked = voodoo->texture_mask + 1;
if (dirty_addr >= addr_start_masked && dirty_addr < addr_end_masked) {
#if 0
voodoo_texture_log(" Evict texture %i %08x\n", c, voodoo->texture_cache[tmu][c].base);
#endif
if (voodoo->texture_cache[tmu][c].refcount != voodoo->texture_cache[tmu][c].refcount_r[0] || (voodoo->render_threads == 2 && voodoo->texture_cache[tmu][c].refcount != voodoo->texture_cache[tmu][c].refcount_r[1]))
wait_for_idle = 1;
voodoo->texture_cache[tmu][c].base = -1;
} else {
for (; addr_start <= addr_end; addr_start += (1 << TEX_DIRTY_SHIFT))
voodoo->texture_present[tmu][(addr_start & voodoo->texture_mask) >> TEX_DIRTY_SHIFT] = 1;
}
}
}
}
}
if (wait_for_idle)
voodoo_wait_for_render_thread_idle(voodoo);
}
void
voodoo_tex_writel(uint32_t addr, uint32_t val, void *priv)
{
int lod;
int s;
int t;
voodoo_t *voodoo = (voodoo_t *) priv;
int tmu;
if (addr & 0x400000)
return; /*TREX != 0*/
tmu = (addr & 0x200000) ? 1 : 0;
if (tmu && !voodoo->dual_tmus)
return;
if (voodoo->type < VOODOO_BANSHEE) {
if (!(voodoo->params.tformat[tmu] & 8) && voodoo->type >= VOODOO_BANSHEE) {
lod = (addr >> 16) & 0xf;
t = (addr >> 8) & 0xff;
} else {
lod = (addr >> 17) & 0xf;
t = (addr >> 9) & 0xff;
}
if (voodoo->params.tformat[tmu] & 8)
s = (addr >> 1) & 0xfe;
else {
if ((voodoo->params.textureMode[tmu] & (1 << 31)) || voodoo->type >= VOODOO_BANSHEE)
s = addr & 0xfc;
else
s = (addr >> 1) & 0xfc;
}
if (lod > LOD_MAX)
return;
#if 0
if (addr >= 0x200000)
return;
#endif
if (voodoo->params.tformat[tmu] & 8)
addr = voodoo->params.tex_base[tmu][lod] + s * 2 + (t << voodoo->params.tex_shift[tmu][lod]) * 2;
else
addr = voodoo->params.tex_base[tmu][lod] + s + (t << voodoo->params.tex_shift[tmu][lod]);
} else
addr = (addr & 0x1ffffc) + voodoo->params.tex_base[tmu][0];
if (voodoo->texture_present[tmu][(addr & voodoo->texture_mask) >> TEX_DIRTY_SHIFT]) {
#if 0
voodoo_texture_log("texture_present at %08x %i\n", addr, (addr & voodoo->texture_mask) >> TEX_DIRTY_SHIFT);
#endif
flush_texture_cache(voodoo, addr & voodoo->texture_mask, tmu);
}
if (voodoo->type == VOODOO_3 && voodoo->texture_present[tmu ^ 1][(addr & voodoo->texture_mask) >> TEX_DIRTY_SHIFT]) {
#if 0
voodoo_texture_log("texture_present at %08x %i\n", addr, (addr & voodoo->texture_mask) >> TEX_DIRTY_SHIFT);
#endif
flush_texture_cache(voodoo, addr & voodoo->texture_mask, tmu ^ 1);
}
*(uint32_t *) (&voodoo->tex_mem[tmu][addr & voodoo->texture_mask]) = val;
}
``` | /content/code_sandbox/src/video/vid_voodoo_texture.c | c | 2016-06-25T22:29:10 | 2024-08-16T19:09:21 | 86Box | 86Box/86Box | 2,616 | 8,202 |
```c
/*
* 86Box A hypervisor and IBM PC system emulator that specializes in
* running old operating systems and software designed for IBM
* PC systems and compatibles from 1981 through fairly recent
* system designs based on the PCI bus.
*
* This file is part of the 86Box distribution.
*
* Wyse-700 emulation.
*
*
*
* Authors: Sarah Walker, <path_to_url
* Miran Grca, <mgrca8@gmail.com>
*
*/
#include <stdio.h>
#include <stdint.h>
#include <string.h>
#include <stdlib.h>
#include <wchar.h>
#include <86box/86box.h>
#include <86box/io.h>
#include <86box/timer.h>
#include <86box/pit.h>
#include <86box/mem.h>
#include <86box/device.h>
#include <86box/video.h>
#include <86box/plat_unused.h>
#define WY700_XSIZE 1280
#define WY700_YSIZE 800
void updatewindowsize(int x, int y);
/* The Wyse 700 is an unusual video card. Though it has an MC6845 CRTC, this
* is not exposed directly to the host PC. Instead, the CRTC is controlled by
* an MC68705P3 microcontroller.
*
* Rather than emulate the real CRTC, I'm writing this as more or less a
* fixed-frequency card with a 1280x800 display, and scaling its selection
* of modes to that window.
*
* By default, the card responds to both the CGA and MDA I/O and memory
* ranges. Either range can be disabled by means of jumpers; this allows
* the Wy700 to coexist with a CGA or MDA.
*
* wy700->wy700_mode indicates which of the supported video modes is in use:
*
* 0x00: 40x 25 text (CGA compatible) [32x32 character cell]
* 0x02: 80x 25 text (CGA / MDA compatible) [16x32 character cell]
* 0x04: 320x200x4 graphics (CGA compatible)
* 0x06: 640x200x2 graphics (CGA compatible)
* 0x80: 640x400x2 graphics
* 0x90: 320x400x4 graphics
* 0xA0: 1280x400x2 graphics
* 0xB0: 640x400x4 graphics
* 0xC0: 1280x800x2 graphics (interleaved)
* 0xD0: 640x800x4 graphics (interleaved)
* In hi-res graphics modes, bit 3 of the mode byte is the enable flag.
*
*/
/* What works (or appears to) :
* MDA/CGA 80x25 text mode
* CGA 40x25 text mode
* CGA 640x200 graphics mode
* CGA 320x200 graphics mode
* Hi-res graphics modes
* Font selection
* Display enable / disable
* -- via Wy700 mode register (in hi-res modes)
* -- via Wy700 command register (in text & CGA modes)
* -- via CGA/MDA control register (in text & CGA modes)
*
* What doesn't work, is untested or not well understood:
* - Cursor detach (commands 4 and 5)
*/
/* The microcontroller sets up the real CRTC with one of five fixed mode
* definitions. As written, this is a fairly simplistic emulation that
* doesn't attempt to closely follow the actual working of the CRTC; but I've
* included the definitions here for information. */
static uint8_t mode_1280x800[] = {
0x31, /* Horizontal total */
0x28, /* Horizontal displayed */
0x29, /* Horizontal sync position */
0x06, /* Horizontal sync width */
0x1b, /* Vertical total */
0x00, /* Vertical total adjust */
0x19, /* Vertical displayed */
0x1a, /* Vsync position */
0x03, /* Interlace and skew */
0x0f, /* Maximum raster address */
};
static uint8_t mode_1280x400[] = {
0x31, /* Horizontal total */
0x28, /* Horizontal displayed */
0x29, /* Horizontal sync position */
0x06, /* Horizontal sync width */
0x1b, /* Vertical total */
0x00, /* Vertical total adjust */
0x19, /* Vertical displayed */
0x1a, /* Vsync position */
0x01, /* Interlace and skew */
0x0f, /* Maximum raster address */
};
static uint8_t mode_640x400[] = {
0x18, /* Horizontal total */
0x14, /* Horizontal displayed */
0x14, /* Horizontal sync position */
0x03, /* Horizontal sync width */
0x1b, /* Vertical total */
0x00, /* Vertical total adjust */
0x19, /* Vertical displayed */
0x1a, /* Vsync position */
0x01, /* Interlace and skew */
0x0f, /* Maximum raster address */
};
static uint8_t mode_640x200[] = {
0x18, /* Horizontal total */
0x14, /* Horizontal displayed */
0x14, /* Horizontal sync position */
0xff, /* Horizontal sync width */
0x37, /* Vertical total */
0x00, /* Vertical total adjust */
0x32, /* Vertical displayed */
0x34, /* Vsync position */
0x03, /* Interlace and skew */
0x07, /* Maximum raster address */
};
static uint8_t mode_80x24[] = {
0x31, /* Horizontal total */
0x28, /* Horizontal displayed */
0x2A, /* Horizontal sync position */
0xff, /* Horizontal sync width */
0x1b, /* Vertical total */
0x00, /* Vertical total adjust */
0x19, /* Vertical displayed */
0x1a, /* Vsync position */
0x01, /* Interlace and skew */
0x0f, /* Maximum raster address */
};
static uint8_t mode_40x24[] = {
0x18, /* Horizontal total */
0x14, /* Horizontal displayed */
0x15, /* Horizontal sync position */
0xff, /* Horizontal sync width */
0x1b, /* Vertical total */
0x00, /* Vertical total adjust */
0x19, /* Vertical displayed */
0x1a, /* Vsync position */
0x01, /* Interlace and skew */
0x0f, /* Maximum raster address */
};
/* Font ROM: Two fonts, each containing 256 characters, 16x16 pixels */
extern uint8_t fontdatw[512][32];
typedef struct wy700_t {
mem_mapping_t mapping;
/* The microcontroller works by watching four ports:
* 0x3D8 / 0x3B8 (mode control register)
* 0x3DD (top scanline address)
* 0x3DF (Wy700 control register)
* CRTC reg 14 (cursor location high)
*
* It will do nothing until one of these registers is touched. When
* one is, it then reconfigures the internal 6845 based on what it
* sees.
*/
uint8_t last_03D8; /* Copies of values written to the listed */
uint8_t last_03DD; /* I/O ports */
uint8_t last_03DF;
uint8_t last_crtc_0E;
uint8_t cga_crtc[32]; /* The 'CRTC' as the host PC sees it */
uint8_t real_crtc[32]; /* The internal CRTC as the microcontroller */
/* sees it */
int cga_crtcreg; /* Current CRTC register */
uint16_t wy700_base; /* Framebuffer base address (native modes) */
uint8_t wy700_control; /* Native control / command register */
uint8_t wy700_mode; /* Current mode (see list at top of file) */
uint8_t cga_ctrl; /* Emulated MDA/CGA control register */
uint8_t cga_colour; /* Emulated CGA colour register (ignored) */
uint8_t mda_stat; /* MDA status (IN 0x3BA) */
uint8_t cga_stat; /* CGA status (IN 0x3DA) */
int font; /* Current font, 0 or 1 */
int enabled; /* Display enabled, 0 or 1 */
int detach; /* Detach cursor, 0 or 1 */
uint64_t dispontime, dispofftime;
pc_timer_t timer;
int linepos, displine;
int vc;
int dispon, blink;
int vsynctime;
uint8_t *vram;
} wy700_t;
/* Mapping of attributes to colours, in CGA emulation... */
static int cgacols[256][2][2];
/* ... and MDA emulation. */
static int mdacols[256][2][2];
void wy700_recalctimings(wy700_t *wy700);
void wy700_write(uint32_t addr, uint8_t val, void *priv);
uint8_t wy700_read(uint32_t addr, void *priv);
void wy700_checkchanges(wy700_t *wy700);
static video_timings_t timing_wy700 = { .type = VIDEO_ISA, .write_b = 8, .write_w = 16, .write_l = 32, .read_b = 8, .read_w = 16, .read_l = 32 };
void
wy700_out(uint16_t addr, uint8_t val, void *priv)
{
wy700_t *wy700 = (wy700_t *) priv;
switch (addr) {
/* These three registers are only mapped in the 3Dx range,
* not the 3Bx range. */
case 0x3DD: /* Base address (low) */
wy700->wy700_base &= 0xFF00;
wy700->wy700_base |= val;
wy700_checkchanges(wy700);
break;
case 0x3DE: /* Base address (high) */
wy700->wy700_base &= 0xFF;
wy700->wy700_base |= ((uint16_t) val) << 8;
wy700_checkchanges(wy700);
break;
case 0x3DF: /* Command / control register */
wy700->wy700_control = val;
wy700_checkchanges(wy700);
break;
/* Emulated CRTC, register select */
case 0x3b0:
case 0x3b2:
case 0x3b4:
case 0x3b6:
case 0x3d0:
case 0x3d2:
case 0x3d4:
case 0x3d6:
wy700->cga_crtcreg = val & 31;
break;
/* Emulated CRTC, value */
case 0x3b1:
case 0x3b3:
case 0x3b5:
case 0x3b7:
case 0x3d1:
case 0x3d3:
case 0x3d5:
case 0x3d7:
wy700->cga_crtc[wy700->cga_crtcreg] = val;
wy700_checkchanges(wy700);
wy700_recalctimings(wy700);
return;
/* Emulated MDA / CGA control register */
case 0x3b8:
case 0x3D8:
wy700->cga_ctrl = val;
wy700_checkchanges(wy700);
return;
/* Emulated CGA colour register */
case 0x3D9:
wy700->cga_colour = val;
return;
default:
break;
}
}
uint8_t
wy700_in(uint16_t addr, void *priv)
{
const wy700_t *wy700 = (wy700_t *) priv;
switch (addr) {
case 0x3b0:
case 0x3b2:
case 0x3b4:
case 0x3b6:
case 0x3d0:
case 0x3d2:
case 0x3d4:
case 0x3d6:
return wy700->cga_crtcreg;
case 0x3b1:
case 0x3b3:
case 0x3b5:
case 0x3b7:
case 0x3d1:
case 0x3d3:
case 0x3d5:
case 0x3d7:
return wy700->cga_crtc[wy700->cga_crtcreg];
case 0x3b8:
case 0x3d8:
return wy700->cga_ctrl;
case 0x3d9:
return wy700->cga_colour;
case 0x3ba:
return wy700->mda_stat;
case 0x3da:
return wy700->cga_stat;
default:
break;
}
return 0xff;
}
/* Check if any of the four key registers has changed. If so, check for a
* mode change or cursor size change */
void
wy700_checkchanges(wy700_t *wy700)
{
uint8_t curstart;
uint8_t curend;
if (wy700->last_03D8 == wy700->cga_ctrl && wy700->last_03DD == (wy700->wy700_base & 0xFF) && wy700->last_03DF == wy700->wy700_control && wy700->last_crtc_0E == wy700->cga_crtc[0x0E]) {
return; /* Nothing changed */
}
/* Check for control register changes */
if (wy700->last_03DF != wy700->wy700_control) {
wy700->last_03DF = wy700->wy700_control;
/* Values 1-7 are commands. */
switch (wy700->wy700_control) {
case 1: /* Reset */
wy700->font = 0;
wy700->enabled = 1;
wy700->detach = 0;
break;
case 2: /* Font 1 */
wy700->font = 0;
break;
case 3: /* Font 2 */
wy700->font = 1;
break;
/* Even with the microprogram from an original card, I can't really work out
* what commands 4 and 5 (which I've called 'cursor detach' / 'cursor attach')
* do. Command 4 sets a flag in microcontroller RAM, and command 5 clears
* it. When the flag is set, the real cursor doesn't track the cursor in the
* emulated CRTC, and its blink rate increases. Possibly it's a self-test
* function of some kind.
*
* The card documentation doesn't cover these commands.
*/
case 4: /* Detach cursor */
wy700->detach = 1;
break;
case 5: /* Attach cursor */
wy700->detach = 0;
break;
case 6: /* Disable display */
wy700->enabled = 0;
break;
case 7: /* Enable display */
wy700->enabled = 1;
break;
default:
break;
}
/* A control write with the top bit set selects graphics mode */
if (wy700->wy700_control & 0x80) {
/* Select hi-res graphics mode; map framebuffer at A0000 */
mem_mapping_set_addr(&wy700->mapping, 0xa0000, 0x20000);
wy700->wy700_mode = wy700->wy700_control;
/* Select appropriate preset timings */
if (wy700->wy700_mode & 0x40) {
memcpy(wy700->real_crtc, mode_1280x800,
sizeof(mode_1280x800));
} else if (wy700->wy700_mode & 0x20) {
memcpy(wy700->real_crtc, mode_1280x400,
sizeof(mode_1280x400));
} else {
memcpy(wy700->real_crtc, mode_640x400,
sizeof(mode_640x400));
}
}
}
/* An attempt to program the CGA / MDA selects low-res mode */
else if (wy700->last_03D8 != wy700->cga_ctrl) {
wy700->last_03D8 = wy700->cga_ctrl;
/* Set lo-res text or graphics mode.
* (Strictly speaking, when not in hi-res mode the card
* should be mapped at B0000-B3FFF and B8000-BBFFF, leaving
* a 16k hole between the two ranges) */
mem_mapping_set_addr(&wy700->mapping, 0xb0000, 0x0C000);
if (wy700->cga_ctrl & 2) /* Graphics mode */
{
wy700->wy700_mode = (wy700->cga_ctrl & 0x10) ? 6 : 4;
memcpy(wy700->real_crtc, mode_640x200,
sizeof(mode_640x200));
} else if (wy700->cga_ctrl & 1) /* Text mode 80x24 */
{
wy700->wy700_mode = 2;
memcpy(wy700->real_crtc, mode_80x24, sizeof(mode_80x24));
} else /* Text mode 40x24 */
{
wy700->wy700_mode = 0;
memcpy(wy700->real_crtc, mode_40x24, sizeof(mode_40x24));
}
}
/* Convert the cursor sizes from the ones used by the CGA or MDA
* to native */
if (wy700->cga_crtc[9] == 13) /* MDA scaling */
{
curstart = wy700->cga_crtc[10] & 0x1F;
wy700->real_crtc[10] = ((curstart + 5) >> 3) + curstart;
if (wy700->real_crtc[10] > 31)
wy700->real_crtc[10] = 31;
/* And bring 'cursor disabled' flag across */
if ((wy700->cga_crtc[10] & 0x60) == 0x20) {
wy700->real_crtc[10] |= 0x20;
}
curend = wy700->cga_crtc[11] & 0x1F;
wy700->real_crtc[11] = ((curend + 5) >> 3) + curend;
if (wy700->real_crtc[11] > 31)
wy700->real_crtc[11] = 31;
} else /* CGA scaling */
{
curstart = wy700->cga_crtc[10] & 0x1F;
wy700->real_crtc[10] = curstart << 1;
if (wy700->real_crtc[10] > 31)
wy700->real_crtc[10] = 31;
/* And bring 'cursor disabled' flag across */
if ((wy700->cga_crtc[10] & 0x60) == 0x20) {
wy700->real_crtc[10] |= 0x20;
}
curend = wy700->cga_crtc[11] & 0x1F;
wy700->real_crtc[11] = curend << 1;
if (wy700->real_crtc[11] > 31)
wy700->real_crtc[11] = 31;
}
}
void
wy700_write(uint32_t addr, uint8_t val, void *priv)
{
wy700_t *wy700 = (wy700_t *) priv;
if (wy700->wy700_mode & 0x80) /* High-res mode. */
{
addr &= 0xFFFF;
/* In 800-line modes, bit 1 of the control register sets the high bit of the
* write address. */
if ((wy700->wy700_mode & 0x42) == 0x42) {
addr |= 0x10000;
}
wy700->vram[addr] = val;
} else {
wy700->vram[addr & 0x3fff] = val;
}
}
uint8_t
wy700_read(uint32_t addr, void *priv)
{
const wy700_t *wy700 = (wy700_t *) priv;
if (wy700->wy700_mode & 0x80) { /* High-res mode. */
addr &= 0xFFFF;
/* In 800-line modes, bit 0 of the control register sets the high bit of the
* read address. */
if ((wy700->wy700_mode & 0x41) == 0x41) {
addr |= 0x10000;
}
return wy700->vram[addr];
} else {
return wy700->vram[addr & 0x3fff];
}
}
void
wy700_recalctimings(wy700_t *wy700)
{
double disptime;
double _dispontime;
double _dispofftime;
disptime = wy700->real_crtc[0] + 1;
_dispontime = wy700->real_crtc[1];
_dispofftime = disptime - _dispontime;
_dispontime *= MDACONST;
_dispofftime *= MDACONST;
wy700->dispontime = (uint64_t) (_dispontime);
wy700->dispofftime = (uint64_t) (_dispofftime);
}
/* Draw a single line of the screen in either text mode */
void
wy700_textline(wy700_t *wy700)
{
int w = (wy700->wy700_mode == 0) ? 40 : 80;
int cw = (wy700->wy700_mode == 0) ? 32 : 16;
uint8_t chr;
uint8_t attr;
uint8_t bitmap[2];
const uint8_t *fontbase = &fontdatw[0][0];
int blink;
int c;
int drawcursor;
int cursorline;
int mda = 0;
uint16_t addr;
uint8_t sc;
uint16_t ma = (wy700->cga_crtc[13] | (wy700->cga_crtc[12] << 8)) & 0x3fff;
uint16_t ca = (wy700->cga_crtc[15] | (wy700->cga_crtc[14] << 8)) & 0x3fff;
/* The fake CRTC character height register selects whether MDA or CGA
* attributes are used */
if (wy700->cga_crtc[9] == 0 || wy700->cga_crtc[9] == 13) {
mda = 1;
}
if (wy700->font) {
fontbase += 256 * 32;
}
addr = ((ma & ~1) + (wy700->displine >> 5) * w) * 2;
sc = (wy700->displine >> 1) & 15;
ma += ((wy700->displine >> 5) * w);
if ((wy700->real_crtc[10] & 0x60) == 0x20) {
cursorline = 0;
} else {
cursorline = ((wy700->real_crtc[10] & 0x1F) <= sc) && ((wy700->real_crtc[11] & 0x1F) >= sc);
}
for (int x = 0; x < w; x++) {
chr = wy700->vram[(addr + 2 * x) & 0x3FFF];
attr = wy700->vram[(addr + 2 * x + 1) & 0x3FFF];
drawcursor = ((ma == ca) && cursorline && wy700->enabled && (wy700->cga_ctrl & 8) && (wy700->blink & 16));
blink = ((wy700->blink & 16) && (wy700->cga_ctrl & 0x20) && (attr & 0x80) && !drawcursor);
if (wy700->cga_ctrl & 0x20)
attr &= 0x7F;
/* MDA underline */
if (sc == 14 && mda && ((attr & 7) == 1)) {
for (c = 0; c < cw; c++)
buffer32->line[wy700->displine][(x * cw) + c] = mdacols[attr][blink][1];
} else /* Draw 16 pixels of character */
{
bitmap[0] = fontbase[chr * 32 + 2 * sc];
bitmap[1] = fontbase[chr * 32 + 2 * sc + 1];
for (c = 0; c < 16; c++) {
int col;
if (c < 8)
col = (mda ? mdacols : cgacols)[attr][blink][(bitmap[0] & (1 << (c ^ 7))) ? 1 : 0];
else
col = (mda ? mdacols : cgacols)[attr][blink][(bitmap[1] & (1 << ((c & 7) ^ 7))) ? 1 : 0];
if (!(wy700->enabled) || !(wy700->cga_ctrl & 8))
col = mdacols[0][0][0];
if (w == 40) {
buffer32->line[wy700->displine][(x * cw) + 2 * c] = col;
buffer32->line[wy700->displine][(x * cw) + 2 * c + 1] = col;
} else
buffer32->line[wy700->displine][(x * cw) + c] = col;
}
if (drawcursor) {
for (c = 0; c < cw; c++)
buffer32->line[wy700->displine][(x * cw) + c] ^= (mda ? mdacols : cgacols)[attr][0][1];
}
++ma;
}
}
}
/* Draw a line in either of the CGA graphics modes (320x200 or 640x200) */
void
wy700_cgaline(wy700_t *wy700)
{
int c;
uint32_t dat;
uint8_t ink = 0;
uint16_t addr;
uint16_t ma = (wy700->cga_crtc[13] | (wy700->cga_crtc[12] << 8)) & 0x3fff;
addr = ((wy700->displine >> 2) & 1) * 0x2000 + (wy700->displine >> 3) * 80 + ((ma & ~1) << 1);
/* The fixed mode setting here programs the real CRTC with a screen
* width to 20, so draw in 20 fixed chunks of 4 bytes each */
for (uint8_t x = 0; x < 20; x++) {
dat = ((wy700->vram[addr & 0x3FFF] << 24) | (wy700->vram[(addr + 1) & 0x3FFF] << 16) | (wy700->vram[(addr + 2) & 0x3FFF] << 8) | (wy700->vram[(addr + 3) & 0x3FFF]));
addr += 4;
if (wy700->wy700_mode == 6) {
for (c = 0; c < 32; c++) {
ink = (dat & 0x80000000) ? 16 + 15 : 16 + 0;
if (!(wy700->enabled) || !(wy700->cga_ctrl & 8))
ink = 16;
buffer32->line[wy700->displine][x * 64 + 2 * c] = buffer32->line[wy700->displine][x * 64 + 2 * c + 1] = ink;
dat = dat << 1;
}
} else {
for (c = 0; c < 16; c++) {
switch ((dat >> 30) & 3) {
case 0:
ink = 16 + 0;
break;
case 1:
ink = 16 + 8;
break;
case 2:
ink = 16 + 7;
break;
case 3:
ink = 16 + 15;
break;
default:
break;
}
if (!(wy700->enabled) || !(wy700->cga_ctrl & 8))
ink = 16;
buffer32->line[wy700->displine][x * 64 + 4 * c] = buffer32->line[wy700->displine][x * 64 + 4 * c + 1] = buffer32->line[wy700->displine][x * 64 + 4 * c + 2] = buffer32->line[wy700->displine][x * 64 + 4 * c + 3] = ink;
dat = dat << 2;
}
}
}
}
/* Draw a line in the medium-resolution graphics modes (640x400 or 320x400) */
void
wy700_medresline(wy700_t *wy700)
{
int c;
uint32_t dat;
uint8_t ink = 0;
uint32_t addr;
addr = (wy700->displine >> 1) * 80 + 4 * wy700->wy700_base;
for (uint8_t x = 0; x < 20; x++) {
dat = ((wy700->vram[addr & 0x1FFFF] << 24) | (wy700->vram[(addr + 1) & 0x1FFFF] << 16) | (wy700->vram[(addr + 2) & 0x1FFFF] << 8) | (wy700->vram[(addr + 3) & 0x1FFFF]));
addr += 4;
if (wy700->wy700_mode & 0x10) {
for (c = 0; c < 16; c++) {
switch ((dat >> 30) & 3) {
case 0:
ink = 16 + 0;
break;
case 1:
ink = 16 + 8;
break;
case 2:
ink = 16 + 7;
break;
case 3:
ink = 16 + 15;
break;
default:
break;
}
/* Display disabled? */
if (!(wy700->wy700_mode & 8))
ink = 16;
buffer32->line[wy700->displine][x * 64 + 4 * c] = buffer32->line[wy700->displine][x * 64 + 4 * c + 1] = buffer32->line[wy700->displine][x * 64 + 4 * c + 2] = buffer32->line[wy700->displine][x * 64 + 4 * c + 3] = ink;
dat = dat << 2;
}
} else {
for (c = 0; c < 32; c++) {
ink = (dat & 0x80000000) ? 16 + 15 : 16 + 0;
/* Display disabled? */
if (!(wy700->wy700_mode & 8))
ink = 16;
buffer32->line[wy700->displine][x * 64 + 2 * c] = buffer32->line[wy700->displine][x * 64 + 2 * c + 1] = ink;
dat = dat << 1;
}
}
}
}
/* Draw a line in one of the high-resolution modes */
void
wy700_hiresline(wy700_t *wy700)
{
int c;
uint32_t dat;
uint8_t ink = 0;
uint32_t addr;
addr = (wy700->displine >> 1) * 160 + 4 * wy700->wy700_base;
if (wy700->wy700_mode & 0x40) /* 800-line interleaved modes */
{
if (wy700->displine & 1)
addr += 0x10000;
}
for (uint8_t x = 0; x < 40; x++) {
dat = ((wy700->vram[addr & 0x1FFFF] << 24) | (wy700->vram[(addr + 1) & 0x1FFFF] << 16) | (wy700->vram[(addr + 2) & 0x1FFFF] << 8) | (wy700->vram[(addr + 3) & 0x1FFFF]));
addr += 4;
if (wy700->wy700_mode & 0x10) {
for (c = 0; c < 16; c++) {
switch ((dat >> 30) & 3) {
case 0:
ink = 16 + 0;
break;
case 1:
ink = 16 + 8;
break;
case 2:
ink = 16 + 7;
break;
case 3:
ink = 16 + 15;
break;
default:
break;
}
/* Display disabled? */
if (!(wy700->wy700_mode & 8))
ink = 16;
buffer32->line[wy700->displine][x * 32 + 2 * c] = buffer32->line[wy700->displine][x * 32 + 2 * c + 1] = ink;
dat = dat << 2;
}
} else {
for (c = 0; c < 32; c++) {
ink = (dat & 0x80000000) ? 16 + 15 : 16 + 0;
/* Display disabled? */
if (!(wy700->wy700_mode & 8))
ink = 16;
buffer32->line[wy700->displine][x * 32 + c] = ink;
dat = dat << 1;
}
}
}
}
void
wy700_poll(void *priv)
{
wy700_t *wy700 = (wy700_t *) priv;
int mode;
if (!wy700->linepos) {
timer_advance_u64(&wy700->timer, wy700->dispofftime);
wy700->cga_stat |= 1;
wy700->mda_stat |= 1;
wy700->linepos = 1;
if (wy700->dispon) {
if (wy700->displine == 0) {
video_wait_for_buffer();
}
if (wy700->wy700_mode & 0x80)
mode = wy700->wy700_mode & 0xF0;
else
mode = wy700->wy700_mode & 0x0F;
switch (mode) {
default:
case 0x00:
case 0x02:
wy700_textline(wy700);
break;
case 0x04:
case 0x06:
wy700_cgaline(wy700);
break;
case 0x80:
case 0x90:
wy700_medresline(wy700);
break;
case 0xA0:
case 0xB0:
case 0xC0:
case 0xD0:
case 0xE0:
case 0xF0:
wy700_hiresline(wy700);
break;
}
}
video_process_8(WY700_XSIZE, wy700->displine);
wy700->displine++;
/* Hardcode a fixed refresh rate and VSYNC timing */
if (wy700->displine == 800) /* Start of VSYNC */
{
wy700->cga_stat |= 8;
wy700->dispon = 0;
}
if (wy700->displine == 832) /* End of VSYNC */
{
wy700->displine = 0;
wy700->cga_stat &= ~8;
wy700->dispon = 1;
}
} else {
if (wy700->dispon) {
wy700->cga_stat &= ~1;
wy700->mda_stat &= ~1;
}
timer_advance_u64(&wy700->timer, wy700->dispontime);
wy700->linepos = 0;
if (wy700->displine == 800) {
/* Hardcode 1280x800 window size */
if ((WY700_XSIZE != xsize) || (WY700_YSIZE != ysize) || video_force_resize_get()) {
xsize = WY700_XSIZE;
ysize = WY700_YSIZE;
if (xsize < 64)
xsize = 656;
if (ysize < 32)
ysize = 200;
set_screen_size(xsize, ysize);
if (video_force_resize_get())
video_force_resize_set(0);
}
video_blit_memtoscreen(0, 0, xsize, ysize);
frames++;
/* Fixed 1280x800 resolution */
video_res_x = WY700_XSIZE;
video_res_y = WY700_YSIZE;
if (wy700->wy700_mode & 0x80)
mode = wy700->wy700_mode & 0xF0;
else
mode = wy700->wy700_mode & 0x0F;
switch (mode) {
case 0x00:
case 0x02:
video_bpp = 0;
break;
case 0x04:
case 0x90:
case 0xB0:
case 0xD0:
case 0xF0:
video_bpp = 2;
break;
default:
video_bpp = 1;
break;
}
wy700->blink++;
}
}
}
void *
wy700_init(UNUSED(const device_t *info))
{
int c;
wy700_t *wy700 = malloc(sizeof(wy700_t));
memset(wy700, 0, sizeof(wy700_t));
video_inform(VIDEO_FLAG_TYPE_CGA, &timing_wy700);
/* 128k video RAM */
wy700->vram = malloc(0x20000);
loadfont("roms/video/wyse700/wy700.rom", 3);
timer_add(&wy700->timer, wy700_poll, wy700, 1);
/* Occupy memory between 0xB0000 and 0xBFFFF (moves to 0xA0000 in
* high-resolution modes) */
mem_mapping_add(&wy700->mapping, 0xb0000, 0x10000, wy700_read, NULL, NULL, wy700_write, NULL, NULL, NULL, MEM_MAPPING_EXTERNAL, wy700);
/* Respond to both MDA and CGA I/O ports */
io_sethandler(0x03b0, 0x000C, wy700_in, NULL, NULL, wy700_out, NULL, NULL, wy700);
io_sethandler(0x03d0, 0x0010, wy700_in, NULL, NULL, wy700_out, NULL, NULL, wy700);
/* Set up the emulated attributes.
* CGA is done in four groups: 00-0F, 10-7F, 80-8F, 90-FF */
for (c = 0; c < 0x10; c++) {
cgacols[c][0][0] = cgacols[c][1][0] = cgacols[c][1][1] = 16;
if (c & 8)
cgacols[c][0][1] = 15 + 16;
else
cgacols[c][0][1] = 7 + 16;
}
for (c = 0x10; c < 0x80; c++) {
cgacols[c][0][0] = cgacols[c][1][0] = cgacols[c][1][1] = 16 + 7;
if (c & 8)
cgacols[c][0][1] = 15 + 16;
else
cgacols[c][0][1] = 0 + 16;
if ((c & 0x0F) == 8)
cgacols[c][0][1] = 8 + 16;
}
/* With special cases for 00, 11, 22, ... 77 */
cgacols[0x00][0][1] = cgacols[0x00][1][1] = 16;
for (c = 0x11; c <= 0x77; c += 0x11) {
cgacols[c][0][1] = cgacols[c][1][1] = 16 + 7;
}
for (c = 0x80; c < 0x90; c++) {
cgacols[c][0][0] = 16 + 8;
if (c & 8)
cgacols[c][0][1] = 15 + 16;
else
cgacols[c][0][1] = 7 + 16;
cgacols[c][1][0] = cgacols[c][1][1] = cgacols[c - 0x80][0][0];
}
for (c = 0x90; c < 0x100; c++) {
cgacols[c][0][0] = 16 + 15;
if (c & 8)
cgacols[c][0][1] = 8 + 16;
else
cgacols[c][0][1] = 7 + 16;
if ((c & 0x0F) == 0)
cgacols[c][0][1] = 16;
cgacols[c][1][0] = cgacols[c][1][1] = cgacols[c - 0x80][0][0];
}
/* Also special cases for 99, AA, ..., FF */
for (c = 0x99; c <= 0xFF; c += 0x11) {
cgacols[c][0][1] = 16 + 15;
}
/* Special cases for 08, 80 and 88 */
cgacols[0x08][0][1] = 16 + 8;
cgacols[0x80][0][1] = 16;
cgacols[0x88][0][1] = 16 + 8;
/* MDA attributes */
for (c = 0; c < 256; c++) {
mdacols[c][0][0] = mdacols[c][1][0] = mdacols[c][1][1] = 16;
if (c & 8)
mdacols[c][0][1] = 15 + 16;
else
mdacols[c][0][1] = 7 + 16;
}
mdacols[0x70][0][1] = 16;
mdacols[0x70][0][0] = mdacols[0x70][1][0] = mdacols[0x70][1][1] = 16 + 15;
mdacols[0xF0][0][1] = 16;
mdacols[0xF0][0][0] = mdacols[0xF0][1][0] = mdacols[0xF0][1][1] = 16 + 15;
mdacols[0x78][0][1] = 16 + 7;
mdacols[0x78][0][0] = mdacols[0x78][1][0] = mdacols[0x78][1][1] = 16 + 15;
mdacols[0xF8][0][1] = 16 + 7;
mdacols[0xF8][0][0] = mdacols[0xF8][1][0] = mdacols[0xF8][1][1] = 16 + 15;
mdacols[0x00][0][1] = mdacols[0x00][1][1] = 16;
mdacols[0x08][0][1] = mdacols[0x08][1][1] = 16;
mdacols[0x80][0][1] = mdacols[0x80][1][1] = 16;
mdacols[0x88][0][1] = mdacols[0x88][1][1] = 16;
/* Start off in 80x25 text mode */
wy700->cga_stat = 0xF4;
wy700->wy700_mode = 2;
wy700->enabled = 1;
memcpy(wy700->real_crtc, mode_80x24, sizeof(mode_80x24));
return wy700;
}
void
wy700_close(void *priv)
{
wy700_t *wy700 = (wy700_t *) priv;
free(wy700->vram);
free(wy700);
}
void
wy700_speed_changed(void *priv)
{
wy700_t *wy700 = (wy700_t *) priv;
wy700_recalctimings(wy700);
}
const device_t wy700_device = {
.name = "Wyse 700",
.internal_name = "wy700",
.flags = DEVICE_ISA,
.local = 0,
.init = wy700_init,
.close = wy700_close,
.reset = NULL,
{ .available = NULL },
.speed_changed = wy700_speed_changed,
.force_redraw = NULL,
.config = NULL
};
``` | /content/code_sandbox/src/video/vid_wy700.c | c | 2016-06-25T22:29:10 | 2024-08-16T19:09:21 | 86Box | 86Box/86Box | 2,616 | 10,679 |
```c
/*
* 86Box A hypervisor and IBM PC system emulator that specializes in
* running old operating systems and software designed for IBM
* PC systems and compatibles from 1981 through fairly recent
* system designs based on the PCI bus.
*
* This file is part of the 86Box distribution.
*
* S3 emulation.
*
*
*
* Authors: Sarah Walker, <path_to_url
* Miran Grca, <mgrca8@gmail.com>
*
*/
#include <stdarg.h>
#include <stdio.h>
#include <stdint.h>
#include <string.h>
#include <stdlib.h>
#include <math.h>
#include <wchar.h>
#include <stdatomic.h>
#define HAVE_STDARG_H
#include <86box/86box.h>
#include <86box/device.h>
#include <86box/io.h>
#include <86box/timer.h>
#include <86box/mem.h>
#include <86box/pci.h>
#include <86box/rom.h>
#include <86box/plat.h>
#include <86box/thread.h>
#include <86box/video.h>
#include <86box/i2c.h>
#include <86box/vid_ddc.h>
#include <86box/vid_svga.h>
#include <86box/vid_svga_render.h>
#include "cpu.h"
#define ROM_ORCHID_86C911 "roms/video/s3/BIOS.BIN"
#define ROM_DIAMOND_STEALTH_VRAM "roms/video/s3/Diamond Stealth VRAM BIOS v2.31 U14.BIN"
#define ROM_AMI_86C924 "roms/video/s3/S3924AMI.BIN"
#define ROM_METHEUS_86C928 "roms/video/s3/928.VBI"
#define ROM_SPEA_MERCURY_LITE_PCI "roms/video/s3/SPEAVGA.VBI"
#define ROM_SPEA_MIRAGE_86C801 "roms/video/s3/V7MIRAGE.VBI"
#define ROM_SPEA_MIRAGE_86C805 "roms/video/s3/86c805pspeavlbus.BIN"
#define ROM_MIROCRYSTAL8S_805 "roms/video/s3/S3_805VL_ATT20C491_miroCRYSTAL_8s_ver1.4.BIN"
#define ROM_MIROCRYSTAL10SD_805 "roms/video/s3/MIROcrystal10SD_VLB.VBI"
#define ROM_MIROCRYSTAL20SV_964_VLB "roms/video/s3/S3_964VL_BT485_27C256_miroCRYSTAL_20sv_ver1.2.bin"
#define ROM_MIROCRYSTAL20SV_964_PCI "roms/video/s3/mirocrystal.VBI"
#define ROM_MIROCRYSTAL20SD_864_VLB "roms/video/s3/Miro20SD.BIN"
#define ROM_PHOENIX_86C80X "roms/video/s3/805.VBI"
#define ROM_PARADISE_BAHAMAS64 "roms/video/s3/bahamas64.bin"
#define ROM_PHOENIX_VISION864 "roms/video/s3/86c864p.bin"
#define ROM_DIAMOND_STEALTH64_964 "roms/video/s3/964_107h.rom"
#define ROM_PHOENIX_TRIO32 "roms/video/s3/86c732p.bin"
#define ROM_SPEA_MIRAGE_P64 "roms/video/s3/S3_764VL_SPEAMirageP64VL_ver5_03.BIN"
#define ROM_NUMBER9_9FX "roms/video/s3/s3_764.bin"
#define ROM_PHOENIX_TRIO64 "roms/video/s3/86c764x1.bin"
#define ROM_DIAMOND_STEALTH64_764 "roms/video/s3/stealt64.bin"
#define ROM_TRIO64V2_DX_VBE20 "roms/video/s3/86c775_2.bin"
#define ROM_STB_POWERGRAPH_64_VIDEO "roms/video/s3/VBIOS.BIN"
#define ROM_PHOENIX_TRIO64VPLUS "roms/video/s3/64V1506.ROM"
#define ROM_CARDEX_TRIO64VPLUS "roms/video/s3/S3T64VP.VBI"
#define ROM_DIAMOND_STEALTH_SE "roms/video/s3/DiamondStealthSE.VBI"
#define ROM_ELSAWIN2KPROX_964 "roms/video/s3/elsaw20004m.BIN"
#define ROM_ELSAWIN2KPROX "roms/video/s3/elsaw20008m.BIN"
#define ROM_NUMBER9_9FX_531 "roms/video/s3/numbernine.BIN"
#define ROM_PHOENIX_VISION868 "roms/video/s3/1-DSV3868.BIN"
#define ROM_MIROVIDEO40SV_ERGO_968_PCI "roms/video/s3/S3_968PCI_TVP3026_miroVideo40SV_PCI_1.04.BIN"
#define ROM_SPEA_MERCURY_P64V "roms/video/s3/S3_968PCI_TVP3026_SPEAMecuryP64V_ver1.01.BIN"
#define ROM_NUMBER9_9FX_771 "roms/video/s3/no9motionfx771.BIN"
#define ROM_PHOENIX_VISION968 "roms/video/s3/1-DSV3968P.BIN"
#define ROM_DIAMOND_STEALTH64_968 "roms/video/s3/vv_303.rom"
enum {
S3_NUMBER9_9FX,
S3_PARADISE_BAHAMAS64,
S3_DIAMOND_STEALTH64_964,
S3_PHOENIX_TRIO32,
S3_PHOENIX_TRIO32_ONBOARD,
S3_PHOENIX_TRIO64,
S3_PHOENIX_TRIO64_ONBOARD,
S3_PHOENIX_VISION864,
S3_DIAMOND_STEALTH64_764,
S3_SPEA_MIRAGE_86C801,
S3_SPEA_MIRAGE_86C805,
S3_PHOENIX_86C801,
S3_PHOENIX_86C805,
S3_ORCHID_86C911,
S3_METHEUS_86C928,
S3_AMI_86C924,
S3_TRIO64V2_DX,
S3_TRIO64V2_DX_ONBOARD,
S3_STB_POWERGRAPH_64_VIDEO,
S3_PHOENIX_TRIO64VPLUS,
S3_PHOENIX_TRIO64VPLUS_ONBOARD,
S3_CARDEX_TRIO64VPLUS,
S3_DIAMOND_STEALTH_SE,
S3_DIAMOND_STEALTH_VRAM,
S3_ELSAWIN2KPROX_964,
S3_ELSAWIN2KPROX,
S3_PHOENIX_VISION868,
S3_MIROVIDEO40SV_ERGO_968,
S3_MIROCRYSTAL10SD_805,
S3_SPEA_MIRAGE_P64,
S3_SPEA_MERCURY_P64V,
S3_MIROCRYSTAL20SV_964,
S3_MIROCRYSTAL20SD_864,
S3_PHOENIX_VISION968,
S3_MIROCRYSTAL8S_805,
S3_NUMBER9_9FX_531,
S3_NUMBER9_9FX_771,
S3_SPEA_MERCURY_LITE_PCI,
S3_86C805_ONBOARD,
S3_DIAMOND_STEALTH64_968
};
enum {
S3_86C911 = 0x00,
S3_86C924 = 0x02,
S3_86C928 = 0x04,
S3_86C928PCI = 0x06,
S3_86C801 = 0x07,
S3_86C805 = 0x08,
S3_VISION964 = 0x18,
S3_VISION968 = 0x20,
S3_VISION864 = 0x28,
S3_VISION868 = 0x30,
S3_TRIO32 = 0x38,
S3_TRIO64 = 0x40,
S3_TRIO64V = 0x48,
S3_TRIO64V2 = 0x50
};
static video_timings_t timing_s3_86c911 = { .type = VIDEO_ISA, .write_b = 4, .write_w = 4, .write_l = 5, .read_b = 20, .read_w = 20, .read_l = 35 };
static video_timings_t timing_s3_86c801 = { .type = VIDEO_ISA, .write_b = 4, .write_w = 4, .write_l = 5, .read_b = 20, .read_w = 20, .read_l = 35 };
static video_timings_t timing_s3_86c805 = { .type = VIDEO_BUS, .write_b = 4, .write_w = 4, .write_l = 5, .read_b = 20, .read_w = 20, .read_l = 35 };
static video_timings_t timing_s3_86c928pci = { .type = VIDEO_PCI, .write_b = 2, .write_w = 2, .write_l = 4, .read_b = 26, .read_w = 26, .read_l = 42 };
static video_timings_t timing_s3_stealth64_vlb = { .type = VIDEO_BUS, .write_b = 2, .write_w = 2, .write_l = 4, .read_b = 26, .read_w = 26, .read_l = 42 };
static video_timings_t timing_s3_stealth64_pci = { .type = VIDEO_PCI, .write_b = 2, .write_w = 2, .write_l = 4, .read_b = 26, .read_w = 26, .read_l = 42 };
static video_timings_t timing_s3_vision864_vlb = { .type = VIDEO_BUS, .write_b = 4, .write_w = 4, .write_l = 5, .read_b = 20, .read_w = 20, .read_l = 35 };
static video_timings_t timing_s3_vision864_pci = { .type = VIDEO_PCI, .write_b = 4, .write_w = 4, .write_l = 5, .read_b = 20, .read_w = 20, .read_l = 35 };
static video_timings_t timing_s3_vision868_pci = { .type = VIDEO_PCI, .write_b = 4, .write_w = 4, .write_l = 5, .read_b = 20, .read_w = 20, .read_l = 35 };
static video_timings_t timing_s3_vision964_vlb = { .type = VIDEO_BUS, .write_b = 2, .write_w = 2, .write_l = 4, .read_b = 20, .read_w = 20, .read_l = 35 };
static video_timings_t timing_s3_vision964_pci = { .type = VIDEO_PCI, .write_b = 2, .write_w = 2, .write_l = 4, .read_b = 20, .read_w = 20, .read_l = 35 };
static video_timings_t timing_s3_vision968_vlb = { .type = VIDEO_BUS, .write_b = 2, .write_w = 2, .write_l = 4, .read_b = 20, .read_w = 20, .read_l = 35 };
static video_timings_t timing_s3_vision968_pci = { .type = VIDEO_PCI, .write_b = 2, .write_w = 2, .write_l = 4, .read_b = 20, .read_w = 20, .read_l = 35 };
static video_timings_t timing_s3_trio32_vlb = { .type = VIDEO_BUS, .write_b = 4, .write_w = 3, .write_l = 5, .read_b = 26, .read_w = 26, .read_l = 42 };
static video_timings_t timing_s3_trio32_pci = { .type = VIDEO_PCI, .write_b = 4, .write_w = 3, .write_l = 5, .read_b = 26, .read_w = 26, .read_l = 42 };
static video_timings_t timing_s3_trio64_vlb = { .type = VIDEO_BUS, .write_b = 3, .write_w = 2, .write_l = 4, .read_b = 25, .read_w = 25, .read_l = 40 };
static video_timings_t timing_s3_trio64_pci = { .type = VIDEO_PCI, .write_b = 3, .write_w = 2, .write_l = 4, .read_b = 25, .read_w = 25, .read_l = 40 };
static video_timings_t timing_s3_trio64vp_cardex_pci = { .type = VIDEO_PCI, .write_b = 2, .write_w = 2, .write_l = 3, .read_b = 19, .read_w = 19, .read_l = 30 };
enum {
VRAM_4MB = 0,
VRAM_8MB = 3,
VRAM_2MB = 4,
VRAM_1MB = 6,
VRAM_512KB = 7
};
#define FIFO_SIZE 65536
#define FIFO_MASK (FIFO_SIZE - 1)
#define FIFO_ENTRY_SIZE (1 << 31)
#define FIFO_ENTRIES (s3->fifo_write_idx - s3->fifo_read_idx)
#define FIFO_FULL ((s3->fifo_write_idx - s3->fifo_read_idx) >= (FIFO_SIZE - 4))
#define FIFO_EMPTY (s3->fifo_read_idx == s3->fifo_write_idx)
#define FIFO_TYPE 0xff000000
#define FIFO_ADDR 0x00ffffff
enum {
FIFO_INVALID = (0x00 << 24),
FIFO_WRITE_BYTE = (0x01 << 24),
FIFO_WRITE_WORD = (0x02 << 24),
FIFO_WRITE_DWORD = (0x03 << 24),
FIFO_OUT_BYTE = (0x04 << 24),
FIFO_OUT_WORD = (0x05 << 24),
FIFO_OUT_DWORD = (0x06 << 24)
};
typedef struct
{
uint32_t addr_type;
uint32_t val;
} fifo_entry_t;
typedef struct s3_t {
mem_mapping_t linear_mapping;
mem_mapping_t mmio_mapping;
mem_mapping_t new_mmio_mapping;
uint8_t has_bios;
rom_t bios_rom;
svga_t svga;
uint8_t bank;
uint8_t ma_ext;
int width, bpp;
int chip;
int pci, vlb;
int atbus;
uint8_t id, id_ext, id_ext_pci;
uint8_t int_line;
int packed_mmio;
uint32_t linear_base, linear_size;
uint8_t pci_regs[256];
uint8_t pci_slot;
uint8_t irq_state;
uint32_t vram_mask;
uint8_t data_available;
int card_type;
struct
{
uint16_t subsys_cntl;
uint16_t setup_md;
uint8_t advfunc_cntl;
uint16_t cur_y, cur_y2;
uint16_t cur_x, cur_x2;
uint16_t x2, ropmix;
uint16_t pat_x, pat_y;
int16_t desty_axstp, desty_axstp2;
int16_t destx_distp;
int16_t maj_axis_pcnt, maj_axis_pcnt2;
int16_t err_term, err_term2;
uint16_t cmd, cmd2;
uint16_t short_stroke;
uint32_t pat_bg_color, pat_fg_color;
uint32_t bkgd_color;
uint32_t frgd_color;
uint32_t wrt_mask;
uint32_t rd_mask;
uint32_t color_cmp;
uint8_t bkgd_mix;
uint8_t frgd_mix;
uint16_t multifunc_cntl;
uint16_t multifunc[16];
uint8_t pix_trans[4];
int ssv_state;
int16_t cx, cy;
int16_t px, py;
int16_t sx, sy;
int16_t dx, dy;
uint32_t src, dest, pattern;
int poly_cx, poly_cx2;
int poly_cy, poly_cy2;
int poly_line_cx;
int point_1_updated, point_2_updated;
int poly_dx1, poly_dx2;
int poly_x;
uint32_t dat_buf;
int dat_count;
int b2e8_pix, temp_cnt;
int ssv_len;
uint8_t ssv_dir;
uint8_t ssv_draw;
uint8_t dat_buf_16bit;
uint8_t frgd_color_actual[2];
uint8_t bkgd_color_actual[2];
uint8_t wrt_mask_actual[2];
uint8_t rd_mask_actual[2];
uint8_t *pix_trans_ptr;
int pix_trans_ptr_cnt;
int pix_trans_x_count;
int pix_trans_x_count2;
int color_16bit_check;
int color_16bit_check_rectfill;
uint16_t minus, srcminus;
/*For non-threaded FIFO*/
int setup_fifo_slot;
int draw_fifo_slot;
int setup_fifo, setup_fifo2;
int draw_fifo, draw_fifo2;
} accel;
struct {
uint32_t nop;
uint32_t cntl;
uint32_t stretch_filt_const;
uint32_t src_dst_step;
uint32_t crop;
uint32_t src_base, dest_base;
uint32_t src, dest;
uint32_t srcbase, dstbase;
int32_t dda_init_accumulator;
int32_t k1, k2;
int dm_index;
int dither_matrix_idx;
int src_step, dst_step;
int sx, sx_backup, sy;
double cx, dx;
double cy, dy;
int sx_scale_int, sx_scale_int_backup;
double sx_scale;
double sx_scale_dec;
double sx_scale_inc;
double sx_scale_backup;
double sx_scale_len;
int dither, host_data, scale_down;
int input;
int len, start;
int odf, idf, yuv;
atomic_int busy;
} videoengine;
struct
{
uint32_t pri_ctrl;
uint32_t chroma_ctrl;
uint32_t sec_ctrl;
uint32_t chroma_upper_bound;
uint32_t sec_filter;
uint32_t blend_ctrl;
uint32_t pri_fb0, pri_fb1;
uint32_t pri_stride;
uint32_t buffer_ctrl;
uint32_t sec_fb0, sec_fb1;
uint32_t sec_stride;
uint32_t overlay_ctrl;
int32_t k1_vert_scale;
int32_t k2_vert_scale;
int32_t dda_vert_accumulator;
int32_t k1_horiz_scale;
int32_t k2_horiz_scale;
int32_t dda_horiz_accumulator;
uint32_t fifo_ctrl;
uint32_t pri_start;
uint32_t pri_size;
uint32_t sec_start;
uint32_t sec_size;
int sdif;
int pri_x, pri_y, pri_w, pri_h;
int sec_x, sec_y, sec_w, sec_h;
} streams;
fifo_entry_t fifo[FIFO_SIZE];
atomic_int fifo_read_idx, fifo_write_idx;
uint8_t fifo_thread_run;
thread_t *fifo_thread;
event_t *wake_fifo_thread;
event_t *fifo_not_full_event;
int blitter_busy;
uint64_t blitter_time;
uint64_t status_time;
uint8_t subsys_cntl, subsys_stat;
uint32_t hwc_fg_col, hwc_bg_col;
int hwc_col_stack_pos;
int translate;
int enable_8514;
int color_16bit;
atomic_int busy, force_busy;
uint8_t thread_run, serialport;
void *i2c, *ddc;
int vram;
void (*accel_start)(int count, int cpu_input, uint32_t mix_dat, uint32_t cpu_dat, void *priv);
} s3_t;
static s3_t *reset_state = NULL;
#define INT_VSY (1 << 0)
#define INT_GE_BSY (1 << 1)
#define INT_FIFO_OVR (1 << 2)
#define INT_FIFO_EMP (1 << 3)
#define INT_MASK 0xf
#define SERIAL_PORT_SCW (1 << 0)
#define SERIAL_PORT_SDW (1 << 1)
#define SERIAL_PORT_SCR (1 << 2)
#define SERIAL_PORT_SDR (1 << 3)
static void s3_updatemapping(s3_t *s3);
static void s3_accel_write(uint32_t addr, uint8_t val, void *priv);
static void s3_accel_write_w(uint32_t addr, uint16_t val, void *priv);
static void s3_accel_write_l(uint32_t addr, uint32_t val, void *priv);
static uint8_t s3_accel_read(uint32_t addr, void *priv);
static uint16_t s3_accel_read_w(uint32_t addr, void *priv);
static uint32_t s3_accel_read_l(uint32_t addr, void *priv);
static void s3_out(uint16_t addr, uint8_t val, void *priv);
static uint8_t s3_in(uint16_t addr, void *priv);
static void s3_accel_out(uint16_t port, uint8_t val, void *priv);
static void s3_accel_out_w(uint16_t port, uint16_t val, void *priv);
static void s3_accel_out_l(uint16_t port, uint32_t val, void *priv);
static uint8_t s3_accel_in(uint16_t port, void *priv);
static uint16_t s3_accel_in_w(uint16_t port, void *priv);
static uint32_t s3_accel_in_l(uint16_t port, void *priv);
static uint8_t s3_pci_read(int func, int addr, void *priv);
static void s3_pci_write(int func, int addr, uint8_t val, void *priv);
#ifdef ENABLE_S3_LOG
int s3_do_log = ENABLE_S3_LOG;
static void
s3_log(const char *fmt, ...)
{
va_list ap;
if (s3_do_log) {
va_start(ap, fmt);
pclog_ex(fmt, ap);
va_end(ap);
}
}
#else
# define s3_log(fmt, ...)
#endif
/*Remap address for chain-4/doubleword style layout.
These will stay for convenience.*/
static __inline uint32_t
dword_remap(svga_t *svga, uint32_t in_addr)
{
if (svga->packed_chain4 || svga->force_old_addr)
return in_addr;
return ((in_addr << 2) & 0x3fff0) | ((in_addr >> 14) & 0xc) | (in_addr & ~0x3fffc);
}
static __inline uint32_t
dword_remap_w(svga_t *svga, uint32_t in_addr)
{
if (svga->packed_chain4 || svga->force_old_addr)
return in_addr;
return ((in_addr << 2) & 0x1fff8) | ((in_addr >> 14) & 0x6) | (in_addr & ~0x1fffe);
}
static __inline uint32_t
dword_remap_l(svga_t *svga, uint32_t in_addr)
{
if (svga->packed_chain4 || svga->force_old_addr)
return in_addr;
return ((in_addr << 2) & 0xfffc) | ((in_addr >> 14) & 0x3) | (in_addr & ~0xffff);
}
static __inline void
wake_fifo_thread(s3_t *s3)
{
thread_set_event(s3->wake_fifo_thread); /*Wake up FIFO thread if moving from idle*/
}
static void
s3_wait_fifo_idle(s3_t *s3)
{
while (!FIFO_EMPTY) {
wake_fifo_thread(s3);
thread_wait_event(s3->fifo_not_full_event, 1);
}
}
static void
s3_queue(s3_t *s3, uint32_t addr, uint32_t val, uint32_t type)
{
fifo_entry_t *fifo = &s3->fifo[s3->fifo_write_idx & FIFO_MASK];
if (FIFO_FULL) {
thread_reset_event(s3->fifo_not_full_event);
if (FIFO_FULL) {
thread_wait_event(s3->fifo_not_full_event, -1); /*Wait for room in ringbuffer*/
}
}
fifo->val = val;
fifo->addr_type = (addr & FIFO_ADDR) | type;
s3->fifo_write_idx++;
if (FIFO_ENTRIES > 0xe000 || FIFO_ENTRIES < 8)
wake_fifo_thread(s3);
}
static void
s3_update_irqs(s3_t *s3)
{
if (!s3->pci)
return;
if (s3->subsys_cntl & s3->subsys_stat & INT_MASK) {
pci_set_irq(s3->pci_slot, PCI_INTA, &s3->irq_state);
} else {
pci_clear_irq(s3->pci_slot, PCI_INTA, &s3->irq_state);
}
}
void s3_accel_start(int count, int cpu_input, uint32_t mix_dat, uint32_t cpu_dat, void *priv);
void s3_short_stroke_start(int count, int cpu_input, uint32_t mix_dat, uint32_t cpu_dat, s3_t *s3, uint8_t ssv);
static void s3_visionx68_video_engine_op(uint32_t cpu_dat, s3_t *s3);
#define WRITE8(addr, var, val) \
switch ((addr) &3) { \
case 0: \
var = (var & 0xffffff00) | (val); \
break; \
case 1: \
var = (var & 0xffff00ff) | ((val) << 8); \
break; \
case 2: \
var = (var & 0xff00ffff) | ((val) << 16); \
break; \
case 3: \
var = (var & 0x00ffffff) | ((val) << 24); \
break; \
}
#define READ_PIXTRANS_BYTE_IO(n) \
s3->accel.pix_trans[n] = svga->vram[dword_remap(svga, (s3->accel.dest + s3->accel.cx + n - s3->accel.minus)) & s3->vram_mask];
#define READ_PIXTRANS_BYTE_MM \
temp = svga->vram[dword_remap(svga, (s3->accel.dest + s3->accel.cx)) & s3->vram_mask];
#define READ_PIXTRANS_WORD \
if ((s3->bpp == 0) && !s3->color_16bit) { \
temp = svga->vram[dword_remap(svga, (s3->accel.dest + s3->accel.cx)) & s3->vram_mask]; \
temp |= (svga->vram[dword_remap(svga, (s3->accel.dest + s3->accel.cx + 1)) & s3->vram_mask] << 8); \
} else { \
temp = vram_w[dword_remap_w(svga, (s3->accel.dest + s3->accel.cx - s3->accel.minus)) & (s3->vram_mask >> 1)]; \
}
#define READ_PIXTRANS_LONG \
if ((s3->bpp == 0) && !s3->color_16bit) { \
temp = svga->vram[dword_remap(svga, (s3->accel.dest + s3->accel.cx)) & s3->vram_mask]; \
temp |= (svga->vram[dword_remap(svga, (s3->accel.dest + s3->accel.cx + 1)) & s3->vram_mask] << 8); \
temp |= (svga->vram[dword_remap(svga, (s3->accel.dest + s3->accel.cx + 2)) & s3->vram_mask] << 16); \
temp |= (svga->vram[dword_remap(svga, (s3->accel.dest + s3->accel.cx + 3)) & s3->vram_mask] << 24); \
} else { \
temp = vram_w[dword_remap_w(svga, (s3->accel.dest + s3->accel.cx)) & (s3->vram_mask >> 1)]; \
temp |= (vram_w[dword_remap_w(svga, (s3->accel.dest + s3->accel.cx + 2)) & (s3->vram_mask >> 1)] << 16); \
}
static int
s3_cpu_src(s3_t *s3)
{
if (!(s3->accel.cmd & 0x100))
return 0;
if (s3->chip >= S3_VISION964)
return 1;
if (s3->accel.cmd & 1)
return 1;
return 0;
}
static int
s3_cpu_dest(s3_t *s3)
{
if (!(s3->accel.cmd & 0x100))
return 0;
if (s3->chip >= S3_VISION964)
return 0;
if (s3->accel.cmd & 1)
return 0;
return 1;
}
static int
s3_enable_fifo(s3_t *s3)
{
const svga_t *svga = &s3->svga;
if ((s3->chip == S3_TRIO32) || (s3->chip == S3_TRIO64) || (s3->chip == S3_TRIO64V) || (s3->chip == S3_TRIO64V2) || (s3->chip == S3_VISION864) || (s3->chip == S3_VISION964) || (s3->chip == S3_VISION968) || (s3->chip == S3_VISION868))
return 1; /* FIFO always enabled on these chips. */
return !!((svga->crtc[0x40] & 0x08) || (s3->accel.advfunc_cntl & 0x40));
}
static void
s3_accel_out_pixtrans_w(s3_t *s3, uint16_t val)
{
const svga_t *svga = &s3->svga;
if (s3->accel.cmd & 0x100) {
s3_log("S3 PIXTRANS_W write: cmd=%03x, pixelcntl=%02x, frgdmix=%02x, bkgdmix=%02x, "
"curx=%d, val=%04x.\n", s3->accel.cmd, s3->accel.multifunc[0x0a],
s3->accel.frgd_mix, s3->accel.bkgd_mix, s3->accel.cur_x, val);
switch (s3->accel.cmd & 0x600) {
case 0x000:
if (((s3->accel.multifunc[0xa] & 0xc0) == 0x80) || (s3->accel.cmd & 2)) {
if (((s3->accel.frgd_mix & 0x60) != 0x40) || ((s3->accel.bkgd_mix & 0x60) != 0x40)) {
if (s3->accel.cmd & 0x1000)
val = (val >> 8) | (val << 8);
s3->accel_start(8, 1, val | (val << 16), 0, s3);
} else
s3->accel_start(1, 1, 0xffffffff, val | (val << 16), s3);
} else {
if (s3->accel.color_16bit_check_rectfill) {
if (s3->accel.color_16bit_check) {
if (s3->accel.pix_trans_x_count < s3->accel.pix_trans_ptr_cnt) {
s3_log("Word: CPU data CMD=%04x, byte write=%02x, "
"cnt=%d, check=%d.\n", s3->accel.cmd, val & 0xff,
s3->accel.pix_trans_x_count, s3->accel.color_16bit_check);
s3->accel.pix_trans_ptr[s3->accel.pix_trans_x_count] = val & 0xff;
s3->accel.pix_trans_ptr[s3->accel.pix_trans_x_count + 1] = val >> 8;
s3->accel.pix_trans_x_count += 2;
}
}
break;
}
s3->accel_start(1, 1, 0xffffffff, val | (val << 16), s3);
}
break;
case 0x200:
if (((s3->accel.multifunc[0xa] & 0xc0) == 0x80) || (s3->accel.cmd & 2)) {
if (((s3->accel.frgd_mix & 0x60) != 0x40) || ((s3->accel.bkgd_mix & 0x60) != 0x40)) {
if (s3->accel.cmd & 0x1000)
val = (val >> 8) | (val << 8);
s3->accel_start(16, 1, val | (val << 16), 0, s3);
} else
s3->accel_start(2, 1, 0xffffffff, val | (val << 16), s3);
} else {
if (s3->accel.color_16bit_check_rectfill) {
if (s3->accel.color_16bit_check) {
if (s3->accel.pix_trans_x_count < s3->accel.pix_trans_ptr_cnt) {
s3_log("Word: CPU data CMD=%04x, word write=%04x, cnt=%d, check=%d, "
"totalptrcnt=%d.\n", s3->accel.cmd, val,
s3->accel.pix_trans_x_count, s3->accel.color_16bit_check,
s3->accel.pix_trans_ptr_cnt);
s3->accel.pix_trans_ptr[s3->accel.pix_trans_x_count] = val & 0xff;
s3->accel.pix_trans_ptr[s3->accel.pix_trans_x_count + 1] = val >> 8;
s3->accel.pix_trans_x_count += 2;
s3->accel.pix_trans_x_count2 = s3->accel.pix_trans_x_count;
}
} else {
if (s3->accel.pix_trans_x_count < s3->accel.pix_trans_ptr_cnt) {
s3_log("Word: CPU data CMD=%04x, word write=%04x, cnt=%d, check=%d, "
"totalptrcnt=%d.\n", s3->accel.cmd, val,
s3->accel.pix_trans_x_count, s3->accel.color_16bit_check,
s3->accel.pix_trans_ptr_cnt);
s3->accel.pix_trans_ptr[s3->accel.pix_trans_x_count2] = val & 0xff;
s3->accel.pix_trans_ptr[s3->accel.pix_trans_x_count2 + 1] = val >> 8;
s3->accel.pix_trans_x_count += 2;
}
if (s3->accel.pix_trans_x_count2 == s3->accel.pix_trans_ptr_cnt) {
for (int i = 0; i < s3->accel.pix_trans_ptr_cnt; i += 2) {
s3_log("Transferring write count=%d, bytes=%08x.\n", i,
s3->accel.pix_trans_ptr[i] |
(s3->accel.pix_trans_ptr[i + 1] << 8) |
(s3->accel.pix_trans_ptr[i + 2] << 16) |
(s3->accel.pix_trans_ptr[i + 3] << 24));
s3->accel_start(2, 1, 0xffffffff, s3->accel.pix_trans_ptr[i] |
(s3->accel.pix_trans_ptr[i + 1] << 8), s3);
}
s3->accel.pix_trans_x_count2 = 0;
s3->accel.color_16bit_check_rectfill = 0;
if (s3->accel.pix_trans_ptr != NULL) {
free(s3->accel.pix_trans_ptr);
s3->accel.pix_trans_ptr = NULL;
}
}
}
break;
}
s3->accel_start(2, 1, 0xffffffff, val | (val << 16), s3);
}
break;
case 0x400:
if (svga->crtc[0x53] & 0x08) {
if (((s3->accel.multifunc[0xa] & 0xc0) == 0x80) || (s3->accel.cmd & 2)) {
if (((s3->accel.frgd_mix & 0x60) != 0x40) || ((s3->accel.bkgd_mix & 0x60) != 0x40)) {
if (s3->accel.cmd & 0x1000)
val = (val >> 8) | (val << 8);
s3->accel_start(32, 1, val | (val << 16), 0, s3);
} else
s3->accel_start(4, 1, 0xffffffff, val | (val << 16), s3);
} else
s3->accel_start(4, 1, 0xffffffff, val | (val << 16), s3);
} else {
if (((s3->accel.multifunc[0xa] & 0xc0) == 0x80) || (s3->accel.cmd & 2)) {
if (((s3->accel.frgd_mix & 0x60) != 0x40) || ((s3->accel.bkgd_mix & 0x60) != 0x40)) {
if (s3->accel.cmd & 0x1000)
val = (val >> 8) | (val << 8);
s3->accel_start(16, 1, val | (val << 16), 0, s3);
} else
s3->accel_start(4, 1, 0xffffffff, val | (val << 16), s3);
} else
s3->accel_start(4, 1, 0xffffffff, val | (val << 16), s3);
}
break;
case 0x600:
if (s3->chip == S3_TRIO32 || s3->chip == S3_VISION968 || s3->chip == S3_VISION868 || s3->chip >= S3_TRIO64V) {
if (((s3->accel.multifunc[0xa] & 0xc0) == 0x80) || (s3->accel.cmd & 2)) {
if (((s3->accel.frgd_mix & 0x60) != 0x40) || ((s3->accel.bkgd_mix & 0x60) != 0x40)) {
if (s3->accel.cmd & 0x1000)
val = (val >> 8) | (val << 8);
s3->accel_start(8, 1, (val >> 8) & 0xff, 0, s3);
s3->accel_start(8, 1, val & 0xff, 0, s3);
}
}
}
break;
default:
break;
}
}
}
static void
s3_accel_out_pixtrans_l(s3_t *s3, uint32_t val)
{
if (s3->accel.cmd & 0x100) {
switch (s3->accel.cmd & 0x600) {
case 0x000:
if (((s3->accel.multifunc[0xa] & 0xc0) == 0x80) || (s3->accel.cmd & 2)) {
if (((s3->accel.frgd_mix & 0x60) != 0x40) || ((s3->accel.bkgd_mix & 0x60) != 0x40)) {
if (s3->accel.cmd & 0x1000)
val = ((val & 0xff00ff00) >> 8) | ((val & 0x00ff00ff) << 8);
s3->accel_start(8, 1, val, 0, s3);
s3->accel_start(8, 1, val >> 16, 0, s3);
} else {
s3->accel_start(1, 1, 0xffffffff, val, s3);
s3->accel_start(1, 1, 0xffffffff, val >> 16, s3);
}
} else {
s3->accel_start(1, 1, 0xffffffff, val, s3);
s3->accel_start(1, 1, 0xffffffff, val >> 16, s3);
}
break;
case 0x200:
if (((s3->accel.multifunc[0xa] & 0xc0) == 0x80) || (s3->accel.cmd & 2)) {
if (((s3->accel.frgd_mix & 0x60) != 0x40) || ((s3->accel.bkgd_mix & 0x60) != 0x40)) {
if (s3->accel.cmd & 0x1000)
val = ((val & 0xff00ff00) >> 8) | ((val & 0x00ff00ff) << 8);
s3->accel_start(16, 1, val, 0, s3);
s3->accel_start(16, 1, val >> 16, 0, s3);
} else {
s3->accel_start(2, 1, 0xffffffff, val, s3);
s3->accel_start(2, 1, 0xffffffff, val >> 16, s3);
}
} else {
s3->accel_start(2, 1, 0xffffffff, val, s3);
s3->accel_start(2, 1, 0xffffffff, val >> 16, s3);
}
break;
case 0x400:
if (((s3->accel.multifunc[0xa] & 0xc0) == 0x80) || (s3->accel.cmd & 2)) {
if (((s3->accel.frgd_mix & 0x60) != 0x40) || ((s3->accel.bkgd_mix & 0x60) != 0x40)) {
if (s3->accel.cmd & 0x1000)
val = ((val & 0xff000000) >> 24) | ((val & 0x00ff0000) >> 8) | ((val & 0x0000ff00) << 8) | ((val & 0x000000ff) << 24);
s3->accel_start(32, 1, val, 0, s3);
} else
s3->accel_start(4, 1, 0xffffffff, val, s3);
} else
s3->accel_start(4, 1, 0xffffffff, val, s3);
break;
case 0x600:
if (s3->chip == S3_TRIO32 || s3->chip == S3_VISION968 || s3->chip == S3_VISION868 || s3->chip >= S3_TRIO64V) {
if (((s3->accel.multifunc[0xa] & 0xc0) == 0x80) || (s3->accel.cmd & 2)) {
if (((s3->accel.frgd_mix & 0x60) != 0x40) || ((s3->accel.bkgd_mix & 0x60) != 0x40)) {
if (s3->accel.cmd & 0x1000)
val = ((val & 0xff000000) >> 24) | ((val & 0x00ff0000) >> 8) | ((val & 0x0000ff00) << 8) | ((val & 0x000000ff) << 24);
s3->accel_start(8, 1, (val >> 24) & 0xff, 0, s3);
s3->accel_start(8, 1, (val >> 16) & 0xff, 0, s3);
s3->accel_start(8, 1, (val >> 8) & 0xff, 0, s3);
s3->accel_start(8, 1, val & 0xff, 0, s3);
}
}
}
break;
default:
break;
}
}
}
static void
s3_accel_out_fifo(s3_t *s3, uint16_t port, uint8_t val)
{
const svga_t *svga = &s3->svga;
switch (port) {
case 0x8148:
case 0x82e8:
s3->accel.cur_y = (s3->accel.cur_y & 0xf00) | val;
s3->accel.poly_cy = s3->accel.cur_y;
break;
case 0x8149:
case 0x82e9:
s3->accel.cur_y = (s3->accel.cur_y & 0xff) | ((val & 0x0f) << 8);
s3->accel.poly_cy = s3->accel.cur_y;
break;
case 0x814a:
case 0x82ea:
s3->accel.cur_y2 = (s3->accel.cur_y2 & 0xf00) | val;
s3->accel.poly_cy2 = s3->accel.cur_y2;
break;
case 0x814b:
case 0x82eb:
s3->accel.cur_y2 = (s3->accel.cur_y2 & 0xff) | ((val & 0x0f) << 8);
s3->accel.poly_cy2 = s3->accel.cur_y2;
break;
case 0x8548:
case 0x86e8:
s3->accel.cur_x = (s3->accel.cur_x & 0xf00) | val;
s3->accel.poly_cx = s3->accel.cur_x << 20;
s3->accel.poly_x = s3->accel.poly_cx >> 20;
break;
case 0x8549:
case 0x86e9:
s3->accel.cur_x = (s3->accel.cur_x & 0xff) | ((val & 0x0f) << 8);
s3->accel.poly_cx = s3->accel.poly_x = s3->accel.cur_x << 20;
s3->accel.poly_x = s3->accel.poly_cx >> 20;
break;
case 0x854a:
case 0x86ea:
s3->accel.cur_x2 = (s3->accel.cur_x2 & 0xf00) | val;
s3->accel.poly_cx2 = s3->accel.cur_x2 << 20;
break;
case 0x854b:
case 0x86eb:
s3->accel.cur_x2 = (s3->accel.cur_x2 & 0xff) | ((val & 0x0f) << 8);
s3->accel.poly_cx2 = s3->accel.cur_x2 << 20;
break;
case 0xcae8:
case 0x8948:
case 0x8ae8:
s3->accel.desty_axstp = (s3->accel.desty_axstp & 0x3f00) | val;
s3->accel.point_1_updated = 1;
break;
case 0xcae9:
case 0x8949:
case 0x8ae9:
s3->accel.desty_axstp = (s3->accel.desty_axstp & 0xff) | ((val & 0x3f) << 8);
if (val & 0x20)
s3->accel.desty_axstp |= ~0x3fff;
s3->accel.point_1_updated = 1;
break;
case 0x894a:
case 0x8aea:
s3->accel.desty_axstp2 = (s3->accel.desty_axstp2 & 0x3f00) | val;
s3->accel.point_2_updated = 1;
break;
case 0x849b:
case 0x8aeb:
s3->accel.desty_axstp2 = (s3->accel.desty_axstp2 & 0xff) | ((val & 0x3f) << 8);
if (val & 0x20)
s3->accel.desty_axstp2 |= ~0x3fff;
s3->accel.point_2_updated = 1;
break;
case 0x8d48:
case 0x8ee8:
s3->accel.destx_distp = (s3->accel.destx_distp & 0x3f00) | val;
s3->accel.point_1_updated = 1;
break;
case 0x8d49:
case 0x8ee9:
s3->accel.destx_distp = (s3->accel.destx_distp & 0xff) | ((val & 0x3f) << 8);
if (val & 0x20)
s3->accel.destx_distp |= ~0x3fff;
s3->accel.point_1_updated = 1;
break;
case 0x8d4a:
case 0x8eea:
s3->accel.x2 = (s3->accel.x2 & 0xf00) | val;
s3->accel.point_2_updated = 1;
break;
case 0x8d4b:
case 0x8eeb:
s3->accel.x2 = (s3->accel.x2 & 0xff) | ((val & 0x0f) << 8);
s3->accel.point_2_updated = 1;
break;
case 0x9148:
case 0x92e8:
s3->accel.err_term = (s3->accel.err_term & 0x3f00) | val;
break;
case 0x9149:
case 0x92e9:
s3->accel.err_term = (s3->accel.err_term & 0xff) | ((val & 0x3f) << 8);
if (val & 0x20)
s3->accel.err_term |= ~0x1fff;
break;
case 0x914a:
case 0x92ea:
s3->accel.err_term2 = (s3->accel.err_term2 & 0x3f00) | val;
break;
case 0x914b:
case 0x92eb:
s3->accel.err_term2 = (s3->accel.err_term2 & 0xff) | ((val & 0x3f) << 8);
if (val & 0x20)
s3->accel.err_term2 |= ~0x1fff;
break;
case 0x9548:
case 0x96e8:
s3->accel.maj_axis_pcnt = (s3->accel.maj_axis_pcnt & 0xf00) | val;
break;
case 0x9459:
case 0x96e9:
s3->accel.maj_axis_pcnt = (s3->accel.maj_axis_pcnt & 0xff) | ((val & 0x0f) << 8);
break;
case 0x954a:
case 0x96ea:
s3->accel.maj_axis_pcnt2 = (s3->accel.maj_axis_pcnt2 & 0xf00) | val;
break;
case 0x954b:
case 0x96eb:
s3->accel.maj_axis_pcnt2 = (s3->accel.maj_axis_pcnt2 & 0xff) | ((val & 0x0f) << 8);
break;
case 0x9948:
case 0x9ae8:
s3->accel.cmd = (s3->accel.cmd & 0xff00) | val;
s3->data_available = 0;
s3->accel.b2e8_pix = 0;
break;
case 0x9949:
case 0x9ae9:
s3->accel.cmd = (s3->accel.cmd & 0xff) | (val << 8);
s3->accel.ssv_state = 0;
s3->accel_start(-1, 0, 0xffffffff, 0, s3);
break;
case 0x994a:
case 0x9aea:
s3->accel.cmd2 = (s3->accel.cmd2 & 0xff00) | val;
break;
case 0x994b:
case 0x9aeb:
s3->accel.cmd2 = (s3->accel.cmd2 & 0xff) | (val << 8);
break;
case 0x9d48:
case 0x9ee8:
s3->accel.short_stroke = (s3->accel.short_stroke & 0xff00) | val;
break;
case 0x9d49:
case 0x9ee9:
s3->accel.short_stroke = (s3->accel.short_stroke & 0xff) | (val << 8);
s3->accel.ssv_state = 1;
s3->accel.cx = s3->accel.cur_x & 0xfff;
s3->accel.cy = s3->accel.cur_y & 0xfff;
if (s3->accel.cmd & 0x1000) {
s3_short_stroke_start(-1, 0, 0xffffffff, 0, s3, s3->accel.short_stroke & 0xff);
s3_short_stroke_start(-1, 0, 0xffffffff, 0, s3, s3->accel.short_stroke >> 8);
} else {
s3_short_stroke_start(-1, 0, 0xffffffff, 0, s3, s3->accel.short_stroke >> 8);
s3_short_stroke_start(-1, 0, 0xffffffff, 0, s3, s3->accel.short_stroke & 0xff);
}
break;
case 0xa148:
case 0xa2e8:
if ((s3->bpp == 3) && (s3->accel.multifunc[0xe] & 0x10) && !(s3->accel.multifunc[0xe] & 0x200))
s3->accel.bkgd_color = (s3->accel.bkgd_color & ~0x00ff0000) | (val << 16);
else
s3->accel.bkgd_color = (s3->accel.bkgd_color & ~0x000000ff) | val;
break;
case 0xa149:
case 0xa2e9:
if ((s3->bpp == 3) && (s3->accel.multifunc[0xe] & 0x10) && !(s3->accel.multifunc[0xe] & 0x200))
s3->accel.bkgd_color = (s3->accel.bkgd_color & ~0xff000000) | (val << 24);
else
s3->accel.bkgd_color = (s3->accel.bkgd_color & ~0x0000ff00) | (val << 8);
if (!(s3->accel.multifunc[0xe] & 0x200))
s3->accel.multifunc[0xe] ^= 0x10;
if (s3->accel.color_16bit_check)
s3->accel.bkgd_color_actual[1] = s3->accel.bkgd_color & 0xff;
else
s3->accel.bkgd_color_actual[0] = s3->accel.bkgd_color & 0xff;
break;
case 0xa14a:
case 0xa2ea:
if (s3->accel.multifunc[0xe] & 0x200)
s3->accel.bkgd_color = (s3->accel.bkgd_color & ~0x00ff0000) | (val << 16);
else if (s3->bpp == 3) {
if (s3->accel.multifunc[0xe] & 0x10)
s3->accel.bkgd_color = (s3->accel.bkgd_color & ~0x00ff0000) | (val << 16);
else
s3->accel.bkgd_color = (s3->accel.bkgd_color & ~0x000000ff) | val;
}
break;
case 0xa14b:
case 0xa2eb:
if (s3->accel.multifunc[0xe] & 0x200)
s3->accel.bkgd_color = (s3->accel.bkgd_color & ~0xff000000) | (val << 24);
else if (s3->bpp == 3) {
if (s3->accel.multifunc[0xe] & 0x10)
s3->accel.bkgd_color = (s3->accel.bkgd_color & ~0xff000000) | (val << 24);
else
s3->accel.bkgd_color = (s3->accel.bkgd_color & ~0x0000ff00) | (val << 8);
s3->accel.multifunc[0xe] ^= 0x10;
}
break;
case 0xa548:
case 0xa6e8:
if ((s3->bpp == 3) && (s3->accel.multifunc[0xe] & 0x10) && !(s3->accel.multifunc[0xe] & 0x200))
s3->accel.frgd_color = (s3->accel.frgd_color & ~0x00ff0000) | (val << 16);
else
s3->accel.frgd_color = (s3->accel.frgd_color & ~0x000000ff) | val;
break;
case 0xa549:
case 0xa6e9:
if ((s3->bpp == 3) && (s3->accel.multifunc[0xe] & 0x10) && !(s3->accel.multifunc[0xe] & 0x200))
s3->accel.frgd_color = (s3->accel.frgd_color & ~0xff000000) | (val << 24);
else
s3->accel.frgd_color = (s3->accel.frgd_color & ~0x0000ff00) | (val << 8);
if (!(s3->accel.multifunc[0xe] & 0x200))
s3->accel.multifunc[0xe] ^= 0x10;
if (s3->accel.color_16bit_check)
s3->accel.frgd_color_actual[1] = s3->accel.frgd_color & 0xff;
else
s3->accel.frgd_color_actual[0] = s3->accel.frgd_color & 0xff;
break;
case 0xa54a:
case 0xa6ea:
if (s3->accel.multifunc[0xe] & 0x200)
s3->accel.frgd_color = (s3->accel.frgd_color & ~0x00ff0000) | (val << 16);
else if (s3->bpp == 3) {
if (s3->accel.multifunc[0xe] & 0x10)
s3->accel.frgd_color = (s3->accel.frgd_color & ~0x00ff0000) | (val << 16);
else
s3->accel.frgd_color = (s3->accel.frgd_color & ~0x000000ff) | val;
}
break;
case 0xa54b:
case 0xa6eb:
if (s3->accel.multifunc[0xe] & 0x200)
s3->accel.frgd_color = (s3->accel.frgd_color & ~0xff000000) | (val << 24);
else if (s3->bpp == 3) {
if (s3->accel.multifunc[0xe] & 0x10)
s3->accel.frgd_color = (s3->accel.frgd_color & ~0xff000000) | (val << 24);
else
s3->accel.frgd_color = (s3->accel.frgd_color & ~0x0000ff00) | (val << 8);
s3->accel.multifunc[0xe] ^= 0x10;
}
break;
case 0xa948:
case 0xaae8:
if ((s3->bpp == 3) && (s3->accel.multifunc[0xe] & 0x10) && !(s3->accel.multifunc[0xe] & 0x200))
s3->accel.wrt_mask = (s3->accel.wrt_mask & ~0x00ff0000) | (val << 16);
else
s3->accel.wrt_mask = (s3->accel.wrt_mask & ~0x000000ff) | val;
break;
case 0xa949:
case 0xaae9:
if ((s3->bpp == 3) && (s3->accel.multifunc[0xe] & 0x10) && !(s3->accel.multifunc[0xe] & 0x200))
s3->accel.wrt_mask = (s3->accel.wrt_mask & ~0xff000000) | (val << 24);
else
s3->accel.wrt_mask = (s3->accel.wrt_mask & ~0x0000ff00) | (val << 8);
if (!(s3->accel.multifunc[0xe] & 0x200))
s3->accel.multifunc[0xe] ^= 0x10;
if (s3->accel.color_16bit_check)
s3->accel.wrt_mask_actual[1] = s3->accel.wrt_mask & 0xff;
else
s3->accel.wrt_mask_actual[0] = s3->accel.wrt_mask & 0xff;
break;
case 0xa94a:
case 0xaaea:
if (s3->accel.multifunc[0xe] & 0x200)
s3->accel.wrt_mask = (s3->accel.wrt_mask & ~0x00ff0000) | (val << 16);
else if (s3->bpp == 3) {
if (s3->accel.multifunc[0xe] & 0x10)
s3->accel.wrt_mask = (s3->accel.wrt_mask & ~0x00ff0000) | (val << 16);
else
s3->accel.wrt_mask = (s3->accel.wrt_mask & ~0x000000ff) | val;
}
break;
case 0xa94b:
case 0xaaeb:
if (s3->accel.multifunc[0xe] & 0x200)
s3->accel.wrt_mask = (s3->accel.wrt_mask & ~0xff000000) | (val << 24);
else if (s3->bpp == 3) {
if (s3->accel.multifunc[0xe] & 0x10)
s3->accel.wrt_mask = (s3->accel.wrt_mask & ~0xff000000) | (val << 24);
else
s3->accel.wrt_mask = (s3->accel.wrt_mask & ~0x0000ff00) | (val << 8);
s3->accel.multifunc[0xe] ^= 0x10;
}
break;
case 0xad48:
case 0xaee8:
if ((s3->bpp == 3) && (s3->accel.multifunc[0xe] & 0x10) && !(s3->accel.multifunc[0xe] & 0x200))
s3->accel.rd_mask = (s3->accel.rd_mask & ~0x00ff0000) | (val << 16);
else
s3->accel.rd_mask = (s3->accel.rd_mask & ~0x000000ff) | val;
break;
case 0xad49:
case 0xaee9:
if ((s3->bpp == 3) && (s3->accel.multifunc[0xe] & 0x10) && !(s3->accel.multifunc[0xe] & 0x200))
s3->accel.rd_mask = (s3->accel.rd_mask & ~0xff000000) | (val << 24);
else
s3->accel.rd_mask = (s3->accel.rd_mask & ~0x0000ff00) | (val << 8);
if (!(s3->accel.multifunc[0xe] & 0x200))
s3->accel.multifunc[0xe] ^= 0x10;
break;
case 0xad4a:
case 0xaeea:
if (s3->accel.multifunc[0xe] & 0x200)
s3->accel.rd_mask = (s3->accel.rd_mask & ~0x00ff0000) | (val << 16);
else if (s3->bpp == 3) {
if (s3->accel.multifunc[0xe] & 0x10)
s3->accel.rd_mask = (s3->accel.rd_mask & ~0x00ff0000) | (val << 16);
else
s3->accel.rd_mask = (s3->accel.rd_mask & ~0x000000ff) | val;
}
break;
case 0xad4b:
case 0xaeeb:
if (s3->accel.multifunc[0xe] & 0x200)
s3->accel.rd_mask = (s3->accel.rd_mask & ~0xff000000) | (val << 24);
else if (s3->bpp == 3) {
if (s3->accel.multifunc[0xe] & 0x10)
s3->accel.rd_mask = (s3->accel.rd_mask & ~0xff000000) | (val << 24);
else
s3->accel.rd_mask = (s3->accel.rd_mask & ~0x0000ff00) | (val << 8);
s3->accel.multifunc[0xe] ^= 0x10;
}
break;
case 0xb148:
case 0xb2e8:
if ((s3->bpp == 3) && (s3->accel.multifunc[0xe] & 0x10) && !(s3->accel.multifunc[0xe] & 0x200))
s3->accel.color_cmp = (s3->accel.color_cmp & ~0x00ff0000) | (val << 16);
else
s3->accel.color_cmp = (s3->accel.color_cmp & ~0x000000ff) | val;
break;
case 0xb149:
case 0xb2e9:
if ((s3->bpp == 3) && (s3->accel.multifunc[0xe] & 0x10) && !(s3->accel.multifunc[0xe] & 0x200))
s3->accel.color_cmp = (s3->accel.color_cmp & ~0xff000000) | (val << 24);
else
s3->accel.color_cmp = (s3->accel.color_cmp & ~0x0000ff00) | (val << 8);
if (!(s3->accel.multifunc[0xe] & 0x200))
s3->accel.multifunc[0xe] ^= 0x10;
break;
case 0xb14a:
case 0xb2ea:
if (s3->accel.multifunc[0xe] & 0x200)
s3->accel.color_cmp = (s3->accel.color_cmp & ~0x00ff0000) | (val << 16);
else if (s3->bpp == 3) {
if (s3->accel.multifunc[0xe] & 0x10)
s3->accel.color_cmp = (s3->accel.color_cmp & ~0x00ff0000) | (val << 16);
else
s3->accel.color_cmp = (s3->accel.color_cmp & ~0x000000ff) | val;
}
break;
case 0xb14b:
case 0xb2eb:
if (s3->accel.multifunc[0xe] & 0x200)
s3->accel.color_cmp = (s3->accel.color_cmp & ~0xff000000) | (val << 24);
else if (s3->bpp == 3) {
if (s3->accel.multifunc[0xe] & 0x10)
s3->accel.color_cmp = (s3->accel.color_cmp & ~0xff000000) | (val << 24);
else
s3->accel.color_cmp = (s3->accel.color_cmp & ~0x0000ff00) | (val << 8);
s3->accel.multifunc[0xe] ^= 0x10;
}
break;
case 0xb548:
case 0xb6e8:
s3->accel.bkgd_mix = val;
break;
case 0xb948:
case 0xbae8:
s3->accel.frgd_mix = val;
break;
case 0xbd48:
case 0xbee8:
s3->accel.multifunc_cntl = (s3->accel.multifunc_cntl & 0xff00) | val;
break;
case 0xbd49:
case 0xbee9:
s3->accel.multifunc_cntl = (s3->accel.multifunc_cntl & 0xff) | (val << 8);
s3->accel.multifunc[s3->accel.multifunc_cntl >> 12] = s3->accel.multifunc_cntl & 0xfff;
break;
case 0xd148:
case 0xd2e8:
s3->accel.ropmix = (s3->accel.ropmix & 0xff00) | val;
break;
case 0xd149:
case 0xd2e9:
s3->accel.ropmix = (s3->accel.ropmix & 0x00ff) | (val << 8);
break;
case 0xe548:
case 0xe6e8:
if ((s3->bpp == 3) && (s3->accel.multifunc[0xe] & 0x10) && !(s3->accel.multifunc[0xe] & 0x200))
s3->accel.pat_bg_color = (s3->accel.pat_bg_color & ~0x00ff0000) | (val << 16);
else
s3->accel.pat_bg_color = (s3->accel.pat_bg_color & ~0x000000ff) | val;
break;
case 0xe549:
case 0xe6e9:
if ((s3->bpp == 3) && (s3->accel.multifunc[0xe] & 0x10) && !(s3->accel.multifunc[0xe] & 0x200))
s3->accel.pat_bg_color = (s3->accel.pat_bg_color & ~0xff000000) | (val << 24);
else
s3->accel.pat_bg_color = (s3->accel.pat_bg_color & ~0x0000ff00) | (val << 8);
if (!(s3->accel.multifunc[0xe] & 0x200))
s3->accel.multifunc[0xe] ^= 0x10;
break;
case 0xe54a:
case 0xe6ea:
if (s3->accel.multifunc[0xe] & 0x200)
s3->accel.pat_bg_color = (s3->accel.pat_bg_color & ~0x00ff0000) | (val << 16);
else if (s3->bpp == 3) {
if (s3->accel.multifunc[0xe] & 0x10)
s3->accel.pat_bg_color = (s3->accel.pat_bg_color & ~0x00ff0000) | (val << 16);
else
s3->accel.pat_bg_color = (s3->accel.pat_bg_color & ~0x000000ff) | val;
}
break;
case 0xe54b:
case 0xe6eb:
if (s3->accel.multifunc[0xe] & 0x200)
s3->accel.pat_bg_color = (s3->accel.pat_bg_color & ~0xff000000) | (val << 24);
else if (s3->bpp == 3) {
if (s3->accel.multifunc[0xe] & 0x10)
s3->accel.pat_bg_color = (s3->accel.pat_bg_color & ~0xff000000) | (val << 24);
else
s3->accel.pat_bg_color = (s3->accel.pat_bg_color & ~0x0000ff00) | (val << 8);
s3->accel.multifunc[0xe] ^= 0x10;
}
break;
case 0xe948:
case 0xeae8:
s3->accel.pat_y = (s3->accel.pat_y & 0xf00) | val;
break;
case 0xe949:
case 0xeae9:
s3->accel.pat_y = (s3->accel.pat_y & 0xff) | ((val & 0x1f) << 8);
break;
case 0xe94a:
case 0xeaea:
s3->accel.pat_x = (s3->accel.pat_x & 0xf00) | val;
break;
case 0xe94b:
case 0xeaeb:
s3->accel.pat_x = (s3->accel.pat_x & 0xff) | ((val & 0x1f) << 8);
break;
case 0xed48:
case 0xeee8:
if ((s3->bpp == 3) && (s3->accel.multifunc[0xe] & 0x10) && !(s3->accel.multifunc[0xe] & 0x200))
s3->accel.pat_fg_color = (s3->accel.pat_fg_color & ~0x00ff0000) | (val << 16);
else
s3->accel.pat_fg_color = (s3->accel.pat_fg_color & ~0x000000ff) | val;
break;
case 0xed49:
case 0xeee9:
if ((s3->bpp == 3) && (s3->accel.multifunc[0xe] & 0x10) && !(s3->accel.multifunc[0xe] & 0x200))
s3->accel.pat_fg_color = (s3->accel.pat_fg_color & ~0xff000000) | (val << 24);
else
s3->accel.pat_fg_color = (s3->accel.pat_fg_color & ~0x0000ff00) | (val << 8);
if (!(s3->accel.multifunc[0xe] & 0x200))
s3->accel.multifunc[0xe] ^= 0x10;
break;
case 0xed4a:
case 0xeeea:
if (s3->accel.multifunc[0xe] & 0x200)
s3->accel.pat_fg_color = (s3->accel.pat_fg_color & ~0x00ff0000) | (val << 16);
else if (s3->bpp == 3) {
if (s3->accel.multifunc[0xe] & 0x10)
s3->accel.pat_fg_color = (s3->accel.pat_fg_color & ~0x00ff0000) | (val << 16);
else
s3->accel.pat_fg_color = (s3->accel.pat_fg_color & ~0x000000ff) | val;
}
break;
case 0xed4b:
case 0xeeeb:
if (s3->accel.multifunc[0xe] & 0x200)
s3->accel.pat_fg_color = (s3->accel.pat_fg_color & ~0xff000000) | (val << 24);
else if (s3->bpp == 3) {
if (s3->accel.multifunc[0xe] & 0x10)
s3->accel.pat_fg_color = (s3->accel.pat_fg_color & ~0xff000000) | (val << 24);
else
s3->accel.pat_fg_color = (s3->accel.pat_fg_color & ~0x0000ff00) | (val << 8);
s3->accel.multifunc[0xe] ^= 0x10;
}
break;
case 0xe148:
case 0xe2e8:
s3->accel.b2e8_pix = 0;
if (s3_cpu_dest(s3))
break;
s3->accel.pix_trans[0] = val;
if (s3->accel.cmd & 0x100) {
switch (s3->accel.cmd & 0x600) {
case 0x000:
if (((s3->accel.multifunc[0xa] & 0xc0) == 0x80) || (s3->accel.cmd & 2)) {
if (((s3->accel.frgd_mix & 0x60) != 0x40) || ((s3->accel.bkgd_mix & 0x60) != 0x40))
s3->accel_start(8, 1, s3->accel.pix_trans[0], 0, s3);
else
s3->accel_start(1, 1, 0xffffffff, s3->accel.pix_trans[0], s3);
} else {
if (s3->accel.color_16bit_check_rectfill) {
if (s3->accel.color_16bit_check) {
if (s3->accel.pix_trans_x_count < s3->accel.pix_trans_ptr_cnt) {
s3_log("Byte: CPU data CMD=%04x, byte write=%02x, cnt=%d, "
"check=%d.\n", s3->accel.cmd, val,
s3->accel.pix_trans_x_count, s3->accel.color_16bit_check);
s3->accel.pix_trans_ptr[s3->accel.pix_trans_x_count] = val;
s3->accel.pix_trans_x_count++;
s3->accel.pix_trans_x_count2 = s3->accel.pix_trans_x_count;
}
} else {
if (s3->accel.pix_trans_x_count2 < s3->accel.pix_trans_ptr_cnt) {
s3_log("Byte: CPU data CMD=%04x, byte write=%02x, cnt=%d, "
"check=%d.\n", s3->accel.cmd, val,
s3->accel.pix_trans_x_count2, s3->accel.color_16bit_check);
s3->accel.pix_trans_ptr[s3->accel.pix_trans_x_count2] = val;
s3->accel.pix_trans_x_count2++;
}
s3_log("WriteCNT=%d, TotalCNT=%d.\n", s3->accel.pix_trans_x_count2,
s3->accel.pix_trans_ptr_cnt);
if (s3->accel.pix_trans_x_count2 == s3->accel.pix_trans_ptr_cnt) {
for (int i = 0; i < s3->accel.pix_trans_ptr_cnt; i += 2) {
s3_log("Transferring write count=%d, bytes=%04x.\n", i,
s3->accel.pix_trans_ptr[i] |
(s3->accel.pix_trans_ptr[i + 1] << 8));
s3->accel_start(1, 1, 0xffffffff, s3->accel.pix_trans_ptr[i] |
(s3->accel.pix_trans_ptr[i + 1] << 8), s3);
}
s3->accel.pix_trans_x_count2 = 0;
s3->accel.color_16bit_check_rectfill = 0;
if (s3->accel.pix_trans_ptr != NULL) {
free(s3->accel.pix_trans_ptr);
s3->accel.pix_trans_ptr = NULL;
}
}
}
break;
}
s3->accel_start(1, 1, 0xffffffff, s3->accel.pix_trans[0], s3);
}
break;
default:
break;
}
}
break;
case 0xe149:
case 0xe2e9:
s3->accel.b2e8_pix = 0;
if (s3_cpu_dest(s3))
break;
s3->accel.pix_trans[1] = val;
if (s3->accel.cmd & 0x100) {
s3_log("S3 PIXTRANS_B write (E2E9): cmd=%03x, pixelcntl=%02x, frgdmix=%02x, "
"bkgdmix=%02x, curx=%d, val=%04x.\n", s3->accel.cmd, s3->accel.multifunc[0x0a],
s3->accel.frgd_mix, s3->accel.bkgd_mix, s3->accel.cur_x, val);
switch (s3->accel.cmd & 0x600) {
case 0x000:
if (((s3->accel.multifunc[0xa] & 0xc0) == 0x80) || (s3->accel.cmd & 2)) {
if (((s3->accel.frgd_mix & 0x60) != 0x40) ||
((s3->accel.bkgd_mix & 0x60) != 0x40))
s3->accel_start(8, 1, s3->accel.pix_trans[0] |
(s3->accel.pix_trans[1] << 8), 0, s3);
else
s3->accel_start(1, 1, 0xffffffff, s3->accel.pix_trans[0] |
(s3->accel.pix_trans[1] << 8), s3);
} else
s3->accel_start(1, 1, 0xffffffff, s3->accel.pix_trans[0] |
(s3->accel.pix_trans[1] << 8), s3);
break;
case 0x200:
if (((s3->accel.multifunc[0xa] & 0xc0) == 0x80) || (s3->accel.cmd & 2)) {
if (((s3->accel.frgd_mix & 0x60) != 0x40) ||
((s3->accel.bkgd_mix & 0x60) != 0x40)) {
if (s3->accel.cmd & 0x1000)
s3->accel_start(16, 1, s3->accel.pix_trans[1] |
(s3->accel.pix_trans[0] << 8), 0, s3);
else
s3->accel_start(16, 1, s3->accel.pix_trans[0] |
(s3->accel.pix_trans[1] << 8), 0, s3);
} else {
if (s3->accel.cmd & 0x1000)
s3->accel_start(2, 1, 0xffffffff, s3->accel.pix_trans[1] |
(s3->accel.pix_trans[0] << 8), s3);
else
s3->accel_start(2, 1, 0xffffffff, s3->accel.pix_trans[0] |
(s3->accel.pix_trans[1] << 8), s3);
}
} else {
if (s3->accel.cmd & 0x1000)
s3->accel_start(2, 1, 0xffffffff, s3->accel.pix_trans[1] |
(s3->accel.pix_trans[0] << 8), s3);
else
s3->accel_start(2, 1, 0xffffffff, s3->accel.pix_trans[0] |
(s3->accel.pix_trans[1] << 8), s3);
}
break;
case 0x400:
if (svga->crtc[0x53] & 0x08) {
if (((s3->accel.multifunc[0xa] & 0xc0) == 0x80) || (s3->accel.cmd & 2)) {
if (((s3->accel.frgd_mix & 0x60) != 0x40) || ((s3->accel.bkgd_mix & 0x60) != 0x40))
s3->accel_start(32, 1, s3->accel.pix_trans[0] | (s3->accel.pix_trans[1] << 8), 0, s3);
else
s3->accel_start(4, 1, 0xffffffff, s3->accel.pix_trans[0] | (s3->accel.pix_trans[1] << 8), s3);
} else
s3->accel_start(4, 1, 0xffffffff, s3->accel.pix_trans[0] | (s3->accel.pix_trans[1] << 8), s3);
}
break;
case 0x600:
if (s3->chip == S3_TRIO32 || s3->chip == S3_VISION968 || s3->chip == S3_VISION868 || s3->chip >= S3_TRIO64V) {
if (((s3->accel.multifunc[0xa] & 0xc0) == 0x80) || (s3->accel.cmd & 2)) {
if (((s3->accel.frgd_mix & 0x60) != 0x40) || ((s3->accel.bkgd_mix & 0x60) != 0x40)) {
s3->accel_start(8, 1, s3->accel.pix_trans[1], 0, s3);
s3->accel_start(8, 1, s3->accel.pix_trans[0], 0, s3);
}
}
}
break;
default:
break;
}
}
break;
case 0xe14a:
case 0xe2ea:
if (s3_cpu_dest(s3))
break;
s3->accel.pix_trans[2] = val;
break;
case 0xe14b:
case 0xe2eb:
if (s3_cpu_dest(s3))
break;
s3->accel.pix_trans[3] = val;
if (s3->accel.cmd & 0x100) {
switch (s3->accel.cmd & 0x600) {
case 0x000:
if (((s3->accel.multifunc[0xa] & 0xc0) == 0x80) || (s3->accel.cmd & 2)) {
if (((s3->accel.frgd_mix & 0x60) != 0x40) || ((s3->accel.bkgd_mix & 0x60) != 0x40))
s3->accel_start(8, 1, s3->accel.pix_trans[0] | (s3->accel.pix_trans[1] << 8) | (s3->accel.pix_trans[2] << 16) | (s3->accel.pix_trans[3] << 24), 0, s3);
else
s3->accel_start(1, 1, 0xffffffff, s3->accel.pix_trans[0] | (s3->accel.pix_trans[1] << 8) | (s3->accel.pix_trans[2] << 16) | (s3->accel.pix_trans[3] << 24), s3);
} else
s3->accel_start(1, 1, 0xffffffff, s3->accel.pix_trans[0] | (s3->accel.pix_trans[1] << 8) | (s3->accel.pix_trans[2] << 16) | (s3->accel.pix_trans[3] << 24), s3);
break;
case 0x200:
if (((s3->accel.multifunc[0xa] & 0xc0) == 0x80) || (s3->accel.cmd & 2)) {
if (((s3->accel.frgd_mix & 0x60) != 0x40) || ((s3->accel.bkgd_mix & 0x60) != 0x40)) {
if (s3->accel.cmd & 0x1000)
s3->accel_start(16, 1, s3->accel.pix_trans[3] | (s3->accel.pix_trans[2] << 8) | (s3->accel.pix_trans[1] << 16) | (s3->accel.pix_trans[0] << 24), 0, s3);
else
s3->accel_start(16, 1, s3->accel.pix_trans[0] | (s3->accel.pix_trans[1] << 8) | (s3->accel.pix_trans[2] << 16) | (s3->accel.pix_trans[3] << 24), 0, s3);
} else {
if (s3->accel.cmd & 0x1000)
s3->accel_start(2, 1, 0xffffffff, s3->accel.pix_trans[3] | (s3->accel.pix_trans[2] << 8) | (s3->accel.pix_trans[1] << 16) | (s3->accel.pix_trans[0] << 24), s3);
else
s3->accel_start(2, 1, 0xffffffff, s3->accel.pix_trans[0] | (s3->accel.pix_trans[1] << 8) | (s3->accel.pix_trans[2] << 16) | (s3->accel.pix_trans[3] << 24), s3);
}
} else {
if (s3->accel.cmd & 0x1000)
s3->accel_start(2, 1, 0xffffffff, s3->accel.pix_trans[3] | (s3->accel.pix_trans[2] << 8) | (s3->accel.pix_trans[1] << 16) | (s3->accel.pix_trans[0] << 24), s3);
else
s3->accel_start(2, 1, 0xffffffff, s3->accel.pix_trans[0] | (s3->accel.pix_trans[1] << 8) | (s3->accel.pix_trans[2] << 16) | (s3->accel.pix_trans[3] << 24), s3);
}
break;
case 0x400:
if (((s3->accel.multifunc[0xa] & 0xc0) == 0x80) || (s3->accel.cmd & 2)) {
if (((s3->accel.frgd_mix & 0x60) != 0x40) || ((s3->accel.bkgd_mix & 0x60) != 0x40))
s3->accel_start(32, 1, s3->accel.pix_trans[0] | (s3->accel.pix_trans[1] << 8) | (s3->accel.pix_trans[2] << 16) | (s3->accel.pix_trans[3] << 24), 0, s3);
else
s3->accel_start(4, 1, 0xffffffff, s3->accel.pix_trans[0] | (s3->accel.pix_trans[1] << 8) | (s3->accel.pix_trans[2] << 16) | (s3->accel.pix_trans[3] << 24), s3);
} else
s3->accel_start(4, 1, 0xffffffff, s3->accel.pix_trans[0] | (s3->accel.pix_trans[1] << 8) | (s3->accel.pix_trans[2] << 16) | (s3->accel.pix_trans[3] << 24), s3);
break;
case 0x600:
if (s3->chip == S3_TRIO32 || s3->chip == S3_VISION968 || s3->chip == S3_VISION868 || s3->chip >= S3_TRIO64V) {
if (((s3->accel.multifunc[0xa] & 0xc0) == 0x80) || (s3->accel.cmd & 2)) {
if (((s3->accel.frgd_mix & 0x60) != 0x40) || ((s3->accel.bkgd_mix & 0x60) != 0x40)) {
s3->accel_start(8, 1, s3->accel.pix_trans[3], 0, s3);
s3->accel_start(8, 1, s3->accel.pix_trans[2], 0, s3);
s3->accel_start(8, 1, s3->accel.pix_trans[1], 0, s3);
s3->accel_start(8, 1, s3->accel.pix_trans[0], 0, s3);
}
}
}
break;
default:
break;
}
}
break;
default:
break;
}
}
static void
s3_accel_out_fifo_w(s3_t *s3, uint16_t port, uint16_t val)
{
if (port != 0x9ee8 && port != 0x9d48) {
if (port == 0xb2e8 || port == 0xb148) {
s3->accel.b2e8_pix = 1;
} else {
s3->accel.b2e8_pix = 0;
}
s3_accel_out_pixtrans_w(s3, val);
} else {
s3->accel.short_stroke = val;
s3->accel.ssv_state = 1;
s3->accel.cx = s3->accel.cur_x & 0xfff;
s3->accel.cy = s3->accel.cur_y & 0xfff;
if (s3->accel.cmd & 0x1000) {
s3_short_stroke_start(-1, 0, 0xffffffff, 0, s3, s3->accel.short_stroke & 0xff);
s3_short_stroke_start(-1, 0, 0xffffffff, 0, s3, s3->accel.short_stroke >> 8);
} else {
s3_short_stroke_start(-1, 0, 0xffffffff, 0, s3, s3->accel.short_stroke >> 8);
s3_short_stroke_start(-1, 0, 0xffffffff, 0, s3, s3->accel.short_stroke & 0xff);
}
}
}
static void
s3_accel_out_fifo_l(s3_t *s3, uint16_t port, uint32_t val)
{
if (port == 0xb2e8 || port == 0xb148)
s3->accel.b2e8_pix = 1;
else
s3->accel.b2e8_pix = 0;
s3_accel_out_pixtrans_l(s3, val);
}
static void
s3_accel_write_fifo(s3_t *s3, uint32_t addr, uint8_t val)
{
const svga_t *svga = &s3->svga;
if (s3->packed_mmio) {
int addr_lo = addr & 1;
if (svga->crtc[0x53] & 0x08) {
if ((addr >= 0x08000) && (addr <= 0x0803f))
s3_pci_write(0, addr & 0xff, val, s3);
}
switch (addr & 0x1fffe) {
case 0x8100:
addr = 0x82e8;
break; /*ALT_CURXY*/
case 0x8102:
addr = 0x86e8;
break;
case 0x8104:
addr = 0x82ea;
break; /*ALT_CURXY2*/
case 0x8106:
addr = 0x86ea;
break;
case 0x8108:
addr = 0x8ae8;
break; /*ALT_STEP*/
case 0x810a:
addr = 0x8ee8;
break;
case 0x810c:
addr = 0x8aea;
break; /*ALT_STEP2*/
case 0x810e:
addr = 0x8eea;
break;
case 0x8110:
addr = 0x92e8;
break; /*ALT_ERR*/
case 0x8112:
addr = 0x92ee;
break;
case 0x8118:
addr = 0x9ae8;
break; /*ALT_CMD*/
case 0x811a:
addr = 0x9aea;
break;
case 0x811c:
addr = 0x9ee8;
break;
case 0x8120:
case 0x8122: /*BKGD_COLOR*/
WRITE8(addr, s3->accel.bkgd_color, val);
return;
case 0x8124:
case 0x8126: /*FRGD_COLOR*/
WRITE8(addr, s3->accel.frgd_color, val);
return;
case 0x8128:
case 0x812a: /*WRT_MASK*/
WRITE8(addr, s3->accel.wrt_mask, val);
return;
case 0x812c:
case 0x812e: /*RD_MASK*/
WRITE8(addr, s3->accel.rd_mask, val);
return;
case 0x8130:
case 0x8132: /*COLOR_CMP*/
WRITE8(addr, s3->accel.color_cmp, val);
return;
case 0x8134:
addr = 0xb6e8;
break; /*ALT_MIX*/
case 0x8136:
addr = 0xbae8;
break;
case 0x8138: /*SCISSORS_T*/
WRITE8(addr & 1, s3->accel.multifunc[1], val);
return;
case 0x813a: /*SCISSORS_L*/
WRITE8(addr & 1, s3->accel.multifunc[2], val);
return;
case 0x813c: /*SCISSORS_B*/
WRITE8(addr & 1, s3->accel.multifunc[3], val);
return;
case 0x813e: /*SCISSORS_R*/
WRITE8(addr & 1, s3->accel.multifunc[4], val);
return;
case 0x8140: /*PIX_CNTL*/
WRITE8(addr & 1, s3->accel.multifunc[0xa], val);
return;
case 0x8142: /*MULT_MISC2*/
WRITE8(addr & 1, s3->accel.multifunc[0xd], val);
return;
case 0x8144: /*MULT_MISC*/
WRITE8(addr & 1, s3->accel.multifunc[0xe], val);
return;
case 0x8146: /*READ_SEL*/
WRITE8(addr & 1, s3->accel.multifunc[0xf], val);
return;
case 0x8148: /*ALT_PCNT*/
WRITE8(addr & 1, s3->accel.multifunc[0], val);
return;
case 0x814a:
addr = 0x96e8;
break;
case 0x814c:
addr = 0x96ea;
break;
case 0x8150:
addr = 0xd2e8;
break;
case 0x8154:
addr = 0x8ee8;
break;
case 0x8156:
addr = 0x96e8;
break;
case 0x8164:
case 0x8166:
WRITE8(addr, s3->accel.pat_bg_color, val);
return;
case 0x8168:
addr = 0xeae8;
break;
case 0x816a:
addr = 0xeaea;
break;
case 0x816c:
case 0x816e:
WRITE8(addr, s3->accel.pat_fg_color, val);
return;
default:
break;
}
addr |= addr_lo;
}
if (svga->crtc[0x53] & 0x08) {
if ((addr & 0x1ffff) < 0x8000) {
if (s3->accel.cmd & 0x100) {
if (((s3->accel.multifunc[0xa] & 0xc0) == 0x80) || (s3->accel.cmd & 2)) {
if (((s3->accel.frgd_mix & 0x60) != 0x40) || ((s3->accel.bkgd_mix & 0x60) != 0x40))
s3->accel_start(8, 1, val | (val << 8) | (val << 16) | (val << 24), 0, s3);
else
s3->accel_start(1, 1, 0xffffffff, val | (val << 8) | (val << 16) | (val << 24), s3);
} else
s3->accel_start(1, 1, 0xffffffff, val | (val << 8) | (val << 16) | (val << 24), s3);
}
} else {
switch (addr & 0x1ffff) {
case 0x83b0:
case 0x83b1:
case 0x83b2:
case 0x83b3:
case 0x83b4:
case 0x83b5:
case 0x83b6:
case 0x83b7:
case 0x83b8:
case 0x83b9:
case 0x83ba:
case 0x83bb:
case 0x83bc:
case 0x83bd:
case 0x83be:
case 0x83bf:
case 0x83c0:
case 0x83c1:
case 0x83c2:
case 0x83c3:
case 0x83c4:
case 0x83c5:
case 0x83c6:
case 0x83c7:
case 0x83c8:
case 0x83c9:
case 0x83ca:
case 0x83cb:
case 0x83cc:
case 0x83cd:
case 0x83ce:
case 0x83cf:
case 0x83d0:
case 0x83d1:
case 0x83d2:
case 0x83d3:
case 0x83d4:
case 0x83d5:
case 0x83d6:
case 0x83d7:
case 0x83d8:
case 0x83d9:
case 0x83da:
case 0x83db:
case 0x83dc:
case 0x83dd:
case 0x83de:
case 0x83df:
s3_out(addr & 0x3ff, val, s3);
break;
case 0x8504:
s3->subsys_stat &= ~val;
s3_update_irqs(s3);
break;
case 0x8505:
s3->subsys_cntl = val;
s3_update_irqs(s3);
break;
case 0x850c:
s3->accel.advfunc_cntl = val;
s3_updatemapping(s3);
break;
case 0xff20:
s3->serialport = val;
i2c_gpio_set(s3->i2c, !!(val & SERIAL_PORT_SCW), !!(val & SERIAL_PORT_SDW));
break;
default:
s3_accel_out_fifo(s3, addr & 0xffff, val);
break;
}
}
} else {
if (addr & 0x8000) {
if ((addr == 0xe2e8) || (addr == 0xe2e9) || (addr == 0xe2ea) || (addr == 0xe2eb)) {
if ((s3->chip == S3_86C801) || (s3->chip == S3_86C805))
goto mmio_byte_write;
else
s3_accel_out_fifo(s3, addr & 0xffff, val);
} else
s3_accel_out_fifo(s3, addr & 0xffff, val);
} else {
mmio_byte_write:
if (s3->accel.cmd & 0x100) {
if ((s3->accel.cmd & 0x600) == 0x200) {
if (((s3->accel.multifunc[0xa] & 0xc0) == 0x80) || (s3->accel.cmd & 2)) {
if (((s3->accel.frgd_mix & 0x60) != 0x40) || ((s3->accel.bkgd_mix & 0x60) != 0x40))
s3->accel_start(16, 1, val | (val << 8) | (val << 16) | (val << 24), 0, s3);
else
s3->accel_start(2, 1, 0xffffffff, val | (val << 8) | (val << 16) | (val << 24), s3);
} else
s3->accel_start(2, 1, 0xffffffff, val | (val << 8) | (val << 16) | (val << 24), s3);
} else {
if (((s3->accel.multifunc[0xa] & 0xc0) == 0x80) || (s3->accel.cmd & 2)) {
if (((s3->accel.frgd_mix & 0x60) != 0x40) || ((s3->accel.bkgd_mix & 0x60) != 0x40))
s3->accel_start(8, 1, val | (val << 8) | (val << 16) | (val << 24), 0, s3);
else
s3->accel_start(1, 1, 0xffffffff, val | (val << 8) | (val << 16) | (val << 24), s3);
} else
s3->accel_start(1, 1, 0xffffffff, val | (val << 8) | (val << 16) | (val << 24), s3);
}
}
}
}
}
static void
s3_accel_write_fifo_w(s3_t *s3, uint32_t addr, uint16_t val)
{
const svga_t *svga = &s3->svga;
if (svga->crtc[0x53] & 0x08) {
if ((addr & 0x1fffe) < 0x8000) {
s3_accel_out_pixtrans_w(s3, val);
} else {
switch (addr & 0x1fffe) {
default:
case 0x83d4:
s3_accel_write_fifo(s3, addr, val);
s3_accel_write_fifo(s3, addr + 1, val >> 8);
break;
case 0xff20:
s3_accel_write_fifo(s3, addr, val);
break;
case 0x811c:
s3_accel_out_fifo_w(s3, 0x9ee8, val);
break;
}
}
} else {
if (addr & 0x8000) {
if (addr == 0x811c)
s3_accel_out_fifo_w(s3, 0x9ee8, val);
else {
if ((addr == 0xe2e8) || (addr == 0xe2ea)) {
if ((s3->chip == S3_86C801) || (s3->chip == S3_86C805) || (s3->chip == S3_86C928) || (s3->chip == S3_86C928PCI))
s3_accel_out_pixtrans_w(s3, val);
else {
s3_accel_write_fifo(s3, addr, val);
s3_accel_write_fifo(s3, addr + 1, val >> 8);
}
} else {
s3_accel_write_fifo(s3, addr, val);
s3_accel_write_fifo(s3, addr + 1, val >> 8);
}
}
} else {
s3_accel_out_pixtrans_w(s3, val);
}
}
}
static void
s3_accel_write_fifo_l(s3_t *s3, uint32_t addr, uint32_t val)
{
svga_t *svga = &s3->svga;
if (svga->crtc[0x53] & 0x08) {
if ((addr & 0x1fffc) < 0x8000 || ((addr & 0x1fffc) >= 0x10000 && (addr & 0x1fffc) < 0x18000)) {
if ((addr & 0x1fffc) >= 0x10000 && (addr & 0x1fffc) < 0x18000) {
s3_visionx68_video_engine_op(val, s3);
} else if ((addr & 0x1fffc) < 0x8000) {
s3_accel_out_pixtrans_l(s3, val);
}
} else {
switch (addr & 0x1fffc) {
case 0x8180:
s3->streams.pri_ctrl = val;
svga_recalctimings(svga);
svga->fullchange = svga->monitor->mon_changeframecount;
break;
case 0x8184:
s3->streams.chroma_ctrl = val;
break;
case 0x8190:
s3->streams.sec_ctrl = val;
s3->streams.dda_horiz_accumulator = val & 0xfff;
if (val & (1 << 11))
s3->streams.dda_horiz_accumulator |= 0xfffff800;
s3->streams.sdif = (val >> 24) & 7;
break;
case 0x8194:
s3->streams.chroma_upper_bound = val;
break;
case 0x8198:
s3->streams.sec_filter = val;
s3->streams.k1_horiz_scale = val & 0x7ff;
if (val & (1 << 10))
s3->streams.k1_horiz_scale |= 0xfffff800;
s3->streams.k2_horiz_scale = (val >> 16) & 0x7ff;
if ((val >> 16) & (1 << 10))
s3->streams.k2_horiz_scale |= 0xfffff800;
break;
case 0x81a0:
s3->streams.blend_ctrl = val;
break;
case 0x81c0:
s3->streams.pri_fb0 = val & 0x3fffff;
svga_recalctimings(svga);
svga->fullchange = svga->monitor->mon_changeframecount;
break;
case 0x81c4:
s3->streams.pri_fb1 = val & 0x3fffff;
svga_recalctimings(svga);
svga->fullchange = svga->monitor->mon_changeframecount;
break;
case 0x81c8:
s3->streams.pri_stride = val & 0xfff;
svga_recalctimings(svga);
svga->fullchange = svga->monitor->mon_changeframecount;
break;
case 0x81cc:
s3->streams.buffer_ctrl = val;
svga_recalctimings(svga);
svga->fullchange = svga->monitor->mon_changeframecount;
break;
case 0x81d0:
s3->streams.sec_fb0 = val;
svga_recalctimings(svga);
svga->fullchange = svga->monitor->mon_changeframecount;
break;
case 0x81d4:
s3->streams.sec_fb1 = val;
svga_recalctimings(svga);
svga->fullchange = svga->monitor->mon_changeframecount;
break;
case 0x81d8:
s3->streams.sec_stride = val;
svga_recalctimings(svga);
svga->fullchange = svga->monitor->mon_changeframecount;
break;
case 0x81dc:
s3->streams.overlay_ctrl = val;
break;
case 0x81e0:
s3->streams.k1_vert_scale = val & 0x7ff;
if (val & (1 << 10))
s3->streams.k1_vert_scale |= 0xfffff800;
break;
case 0x81e4:
s3->streams.k2_vert_scale = val & 0x7ff;
if (val & (1 << 10))
s3->streams.k2_vert_scale |= 0xfffff800;
break;
case 0x81e8:
s3->streams.dda_vert_accumulator = val & 0xfff;
if (val & (1 << 11))
s3->streams.dda_vert_accumulator |= 0xfffff800;
break;
case 0x81ec:
s3->streams.fifo_ctrl = val;
break;
case 0x81f0:
s3->streams.pri_start = val;
s3->streams.pri_x = (val >> 16) & 0x7ff;
s3->streams.pri_y = val & 0x7ff;
svga_recalctimings(svga);
svga->fullchange = svga->monitor->mon_changeframecount;
break;
case 0x81f4:
s3->streams.pri_size = val;
s3->streams.pri_w = (val >> 16) & 0x7ff;
s3->streams.pri_h = val & 0x7ff;
svga_recalctimings(svga);
svga->fullchange = svga->monitor->mon_changeframecount;
break;
case 0x81f8:
s3->streams.sec_start = val;
s3->streams.sec_x = (val >> 16) & 0x7ff;
s3->streams.sec_y = val & 0x7ff;
svga_recalctimings(svga);
svga->fullchange = svga->monitor->mon_changeframecount;
break;
case 0x81fc:
s3->streams.sec_size = val;
s3->streams.sec_w = (val >> 16) & 0x7ff;
s3->streams.sec_h = val & 0x7ff;
svga_recalctimings(svga);
svga->fullchange = svga->monitor->mon_changeframecount;
break;
case 0x8504:
s3->subsys_stat &= ~(val & 0xff);
s3->subsys_cntl = (val >> 8);
s3_update_irqs(s3);
break;
case 0x850c:
s3->accel.advfunc_cntl = val & 0xff;
s3_updatemapping(s3);
break;
case 0xff20:
s3_accel_write_fifo(s3, addr, val);
break;
case 0x18080:
s3->videoengine.nop = 1;
break;
case 0x18088:
s3->videoengine.cntl = val;
s3->videoengine.dda_init_accumulator = val & 0xfff;
s3->videoengine.odf = (val >> 16) & 7;
s3->videoengine.yuv = !!(val & (1 << 19));
s3->videoengine.idf = (val >> 20) & 7;
s3->videoengine.dither = !!(val & (1 << 29));
s3->videoengine.dm_index = (val >> 23) & 7;
break;
case 0x1808c:
s3->videoengine.stretch_filt_const = val;
s3->videoengine.k2 = val & 0x7ff;
s3->videoengine.k1 = (val >> 16) & 0x7ff;
s3->videoengine.host_data = !!(val & (1 << 30));
s3->videoengine.scale_down = !!(val & (1 << 31));
break;
case 0x18090:
s3->videoengine.src_dst_step = val;
s3->videoengine.dst_step = val & 0x1fff;
s3->videoengine.src_step = (val >> 16) & 0x1fff;
break;
case 0x18094:
s3->videoengine.crop = val;
s3->videoengine.len = val & 0xfff;
s3->videoengine.start = (val >> 16) & 0xfff;
s3->videoengine.input = 1;
break;
case 0x18098:
s3->videoengine.src_base = val & 0xffffff;
break;
case 0x1809c:
s3->videoengine.dest_base = val & 0xffffff;
break;
default:
s3_accel_write_fifo(s3, addr, val);
s3_accel_write_fifo(s3, addr + 1, val >> 8);
s3_accel_write_fifo(s3, addr + 2, val >> 16);
s3_accel_write_fifo(s3, addr + 3, val >> 24);
break;
}
}
} else {
if (addr & 0x8000) {
if (addr == 0xe2e8) {
if ((s3->chip == S3_86C928) || (s3->chip == S3_86C928PCI))
s3_accel_out_pixtrans_l(s3, val);
else {
s3_accel_write_fifo(s3, addr, val);
s3_accel_write_fifo(s3, addr + 1, val >> 8);
s3_accel_write_fifo(s3, addr + 2, val >> 16);
s3_accel_write_fifo(s3, addr + 3, val >> 24);
}
} else {
s3_accel_write_fifo(s3, addr, val);
s3_accel_write_fifo(s3, addr + 1, val >> 8);
s3_accel_write_fifo(s3, addr + 2, val >> 16);
s3_accel_write_fifo(s3, addr + 3, val >> 24);
}
} else {
s3_accel_out_pixtrans_l(s3, val);
}
}
}
static void
s3_vblank_start(svga_t *svga)
{
s3_t *s3 = (s3_t *) svga->priv;
s3->subsys_stat |= INT_VSY;
s3_update_irqs(s3);
}
static uint32_t
s3_hwcursor_convert_addr(svga_t *svga)
{
if ((svga->bpp == 8) && (((svga->gdcreg[5] & 0x60) == 0x20) || (svga->crtc[0x3a] & 0x10)) && (svga->crtc[0x45] & 0x10)) {
if (svga->crtc[0x3a] & 0x10)
return ((svga->hwcursor_latch.addr & 0xfffff1ff) | ((svga->hwcursor_latch.addr & 0x200) << 2)) | 0x600;
else if ((svga->gdcreg[5] & 0x60) == 0x20)
return ((svga->hwcursor_latch.addr & 0xfffff0ff) | ((svga->hwcursor_latch.addr & 0x300) << 2)) | 0x300;
else
return svga->hwcursor_latch.addr;
} else
return svga->hwcursor_latch.addr;
}
static void
s3_hwcursor_draw(svga_t *svga, int displine)
{
const s3_t *s3 = (s3_t *) svga->priv;
int shift = 1;
int width = 16;
uint16_t dat[2];
int xx;
int offset = svga->hwcursor_latch.x - svga->hwcursor_latch.xoff;
uint32_t fg;
uint32_t bg;
uint32_t real_addr;
uint32_t remapped_addr;
switch (svga->bpp) {
case 15:
fg = video_15to32[s3->hwc_fg_col & 0xffff];
bg = video_15to32[s3->hwc_bg_col & 0xffff];
if (s3->chip >= S3_86C928 && s3->chip <= S3_86C805) {
if (s3->card_type != S3_MIROCRYSTAL10SD_805 && s3->card_type != S3_MIROCRYSTAL8S_805) {
if (!(svga->crtc[0x45] & 0x04)) {
shift = 2;
width = 8;
}
}
}
break;
case 16:
fg = video_16to32[s3->hwc_fg_col & 0xffff];
bg = video_16to32[s3->hwc_bg_col & 0xffff];
if (s3->chip >= S3_86C928 && s3->chip <= S3_86C805) {
if ((s3->card_type != S3_MIROCRYSTAL10SD_805) && (s3->card_type != S3_MIROCRYSTAL8S_805)) {
if (!(svga->crtc[0x45] & 0x04)) {
shift = 2;
width = 8;
}
} else if (s3->card_type == S3_MIROCRYSTAL10SD_805) {
if (!(svga->crtc[0x45] & 0x04)) {
offset <<= 1;
}
}
}
break;
case 24:
if (s3->chip <= S3_86C805) {
fg = svga->pallook[svga->crtc[0xe]];
bg = svga->pallook[svga->crtc[0xf]];
} else {
fg = s3->hwc_fg_col;
bg = s3->hwc_bg_col;
}
break;
case 32:
fg = s3->hwc_fg_col;
bg = s3->hwc_bg_col;
break;
default:
if (s3->chip >= S3_TRIO32) {
fg = svga->pallook[s3->hwc_fg_col & 0xff];
bg = svga->pallook[s3->hwc_bg_col & 0xff];
} else {
fg = svga->pallook[svga->crtc[0xe]];
bg = svga->pallook[svga->crtc[0xf]];
}
break;
}
if (svga->interlace && svga->hwcursor_oddeven)
svga->hwcursor_latch.addr += 16;
real_addr = s3_hwcursor_convert_addr(svga);
for (uint8_t x = 0; x < 64; x += 16) {
remapped_addr = dword_remap(svga, real_addr);
dat[0] = (svga->vram[remapped_addr & s3->vram_mask] << 8) | svga->vram[(remapped_addr + 1) & s3->vram_mask];
dat[1] = (svga->vram[(remapped_addr + 2) & s3->vram_mask] << 8) | svga->vram[(remapped_addr + 3) & s3->vram_mask];
if (svga->crtc[0x55] & 0x10) {
/*X11*/
for (xx = 0; xx < 16; xx++) {
if (offset >= 0) {
if (dat[0] & 0x8000)
buffer32->line[displine][offset + svga->x_add] = (dat[1] & 0x8000) ? fg : bg;
}
offset++;
dat[0] <<= shift;
dat[1] <<= shift;
}
} else {
/*Windows*/
for (xx = 0; xx < width; xx++) {
if (offset >= 0) {
if (!(dat[0] & 0x8000))
buffer32->line[displine][offset + svga->x_add] = (dat[1] & 0x8000) ? fg : bg;
else if (dat[1] & 0x8000)
buffer32->line[displine][offset + svga->x_add] ^= 0xffffff;
}
offset++;
dat[0] <<= shift;
dat[1] <<= shift;
}
}
svga->hwcursor_latch.addr += 4;
real_addr = s3_hwcursor_convert_addr(svga);
}
if (svga->interlace && !svga->hwcursor_oddeven)
svga->hwcursor_latch.addr += 16;
}
#define CLAMP(x) \
do { \
if ((x) & ~0xff) \
x = ((x) < 0) ? 0 : 0xff; \
} while (0)
#define DECODE_YCbCr() \
do { \
int c; \
\
for (c = 0; c < 2; c++) { \
uint8_t y1, y2; \
int8_t Cr, Cb; \
int dR, dG, dB; \
\
y1 = src[0]; \
Cr = src[1] - 0x80; \
y2 = src[2]; \
Cb = src[3] - 0x80; \
src += 4; \
\
dR = (359 * Cr) >> 8; \
dG = (88 * Cb + 183 * Cr) >> 8; \
dB = (453 * Cb) >> 8; \
\
r[x_write] = y1 + dR; \
CLAMP(r[x_write]); \
g[x_write] = y1 - dG; \
CLAMP(g[x_write]); \
b[x_write] = y1 + dB; \
CLAMP(b[x_write]); \
\
r[x_write + 1] = y2 + dR; \
CLAMP(r[x_write + 1]); \
g[x_write + 1] = y2 - dG; \
CLAMP(g[x_write + 1]); \
b[x_write + 1] = y2 + dB; \
CLAMP(b[x_write + 1]); \
\
x_write = (x_write + 2) & 7; \
} \
} while (0)
/*Both YUV formats are untested*/
#define DECODE_YUV211() \
do { \
uint8_t y1, y2, y3, y4; \
int8_t U, V; \
int dR, dG, dB; \
\
U = src[0] - 0x80; \
y1 = (298 * (src[1] - 16)) >> 8; \
y2 = (298 * (src[2] - 16)) >> 8; \
V = src[3] - 0x80; \
y3 = (298 * (src[4] - 16)) >> 8; \
y4 = (298 * (src[5] - 16)) >> 8; \
src += 6; \
\
dR = (309 * V) >> 8; \
dG = (100 * U + 208 * V) >> 8; \
dB = (516 * U) >> 8; \
\
r[x_write] = y1 + dR; \
CLAMP(r[x_write]); \
g[x_write] = y1 - dG; \
CLAMP(g[x_write]); \
b[x_write] = y1 + dB; \
CLAMP(b[x_write]); \
\
r[x_write + 1] = y2 + dR; \
CLAMP(r[x_write + 1]); \
g[x_write + 1] = y2 - dG; \
CLAMP(g[x_write + 1]); \
b[x_write + 1] = y2 + dB; \
CLAMP(b[x_write + 1]); \
\
r[x_write + 2] = y3 + dR; \
CLAMP(r[x_write + 2]); \
g[x_write + 2] = y3 - dG; \
CLAMP(g[x_write + 2]); \
b[x_write + 2] = y3 + dB; \
CLAMP(b[x_write + 2]); \
\
r[x_write + 3] = y4 + dR; \
CLAMP(r[x_write + 3]); \
g[x_write + 3] = y4 - dG; \
CLAMP(g[x_write + 3]); \
b[x_write + 3] = y4 + dB; \
CLAMP(b[x_write + 3]); \
\
x_write = (x_write + 4) & 7; \
} while (0)
#define DECODE_YUV422() \
do { \
int c; \
\
for (c = 0; c < 2; c++) { \
uint8_t y1, y2; \
int8_t U, V; \
int dR, dG, dB; \
\
U = src[0] - 0x80; \
y1 = (298 * (src[1] - 16)) >> 8; \
V = src[2] - 0x80; \
y2 = (298 * (src[3] - 16)) >> 8; \
src += 4; \
\
dR = (309 * V) >> 8; \
dG = (100 * U + 208 * V) >> 8; \
dB = (516 * U) >> 8; \
\
r[x_write] = y1 + dR; \
CLAMP(r[x_write]); \
g[x_write] = y1 - dG; \
CLAMP(g[x_write]); \
b[x_write] = y1 + dB; \
CLAMP(b[x_write]); \
\
r[x_write + 1] = y2 + dR; \
CLAMP(r[x_write + 1]); \
g[x_write + 1] = y2 - dG; \
CLAMP(g[x_write + 1]); \
b[x_write + 1] = y2 + dB; \
CLAMP(b[x_write + 1]); \
\
x_write = (x_write + 2) & 7; \
} \
} while (0)
#define DECODE_RGB555() \
do { \
int c; \
\
for (c = 0; c < 4; c++) { \
uint16_t dat; \
\
dat = *(uint16_t *) src; \
src += 2; \
\
r[x_write + c] = ((dat & 0x001f) << 3) | ((dat & 0x001f) >> 2); \
g[x_write + c] = ((dat & 0x03e0) >> 2) | ((dat & 0x03e0) >> 7); \
b[x_write + c] = ((dat & 0x7c00) >> 7) | ((dat & 0x7c00) >> 12); \
} \
x_write = (x_write + 4) & 7; \
} while (0)
#define DECODE_RGB565() \
do { \
int c; \
\
for (c = 0; c < 4; c++) { \
uint16_t dat; \
\
dat = *(uint16_t *) src; \
src += 2; \
\
r[x_write + c] = ((dat & 0x001f) << 3) | ((dat & 0x001f) >> 2); \
g[x_write + c] = ((dat & 0x07e0) >> 3) | ((dat & 0x07e0) >> 9); \
b[x_write + c] = ((dat & 0xf800) >> 8) | ((dat & 0xf800) >> 13); \
} \
x_write = (x_write + 4) & 7; \
} while (0)
#define DECODE_RGB888() \
do { \
int c; \
\
for (c = 0; c < 4; c++) { \
r[x_write + c] = src[0]; \
g[x_write + c] = src[1]; \
b[x_write + c] = src[2]; \
src += 3; \
} \
x_write = (x_write + 4) & 7; \
} while (0)
#define DECODE_XRGB8888() \
do { \
int c; \
\
for (c = 0; c < 4; c++) { \
r[x_write + c] = src[0]; \
g[x_write + c] = src[1]; \
b[x_write + c] = src[2]; \
src += 4; \
} \
x_write = (x_write + 4) & 7; \
} while (0)
#define OVERLAY_SAMPLE() \
do { \
switch (s3->streams.sdif) { \
case 1: \
DECODE_YCbCr(); \
break; \
case 2: \
DECODE_YUV422(); \
break; \
case 3: \
DECODE_RGB555(); \
break; \
case 4: \
DECODE_YUV211(); \
break; \
case 5: \
DECODE_RGB565(); \
break; \
case 6: \
DECODE_RGB888(); \
break; \
case 7: \
default: \
DECODE_XRGB8888(); \
break; \
} \
} while (0)
static void
s3_trio64v_overlay_draw(svga_t *svga, int displine)
{
const s3_t *s3 = (s3_t *) svga->priv;
int offset = (s3->streams.sec_x - s3->streams.pri_x) + 1;
int h_acc = s3->streams.dda_horiz_accumulator;
int r[8];
int g[8];
int b[8];
int x_size;
int x_read = 4;
int x_write = 4;
uint32_t *p;
uint8_t *src = &svga->vram[svga->overlay_latch.addr];
p = &(buffer32->line[displine][offset + svga->x_add]);
if ((offset + s3->streams.sec_w) > s3->streams.pri_w)
x_size = (s3->streams.pri_w - s3->streams.sec_x) + 1;
else
x_size = s3->streams.sec_w + 1;
OVERLAY_SAMPLE();
for (int x = 0; x < x_size; x++) {
*p++ = r[x_read] | (g[x_read] << 8) | (b[x_read] << 16);
h_acc += s3->streams.k1_horiz_scale;
if (h_acc >= 0) {
if ((x_read ^ (x_read + 1)) & ~3)
OVERLAY_SAMPLE();
x_read = (x_read + 1) & 7;
h_acc += (s3->streams.k2_horiz_scale - s3->streams.k1_horiz_scale);
}
}
svga->overlay_latch.v_acc += s3->streams.k1_vert_scale;
if (svga->overlay_latch.v_acc >= 0) {
svga->overlay_latch.v_acc += (s3->streams.k2_vert_scale - s3->streams.k1_vert_scale);
svga->overlay_latch.addr += s3->streams.sec_stride;
}
}
static void
s3_io_remove_alt(s3_t *s3)
{
if (!s3->translate)
return;
io_removehandler(0x4148, 0x0002, s3_accel_in, NULL, NULL, s3_accel_out, NULL, NULL, s3);
io_removehandler(0x4548, 0x0002, s3_accel_in, NULL, NULL, s3_accel_out, NULL, NULL, s3);
io_removehandler(0x4948, 0x0002, s3_accel_in, NULL, NULL, s3_accel_out, NULL, NULL, s3);
io_removehandler(0x8148, 0x0004, s3_accel_in, NULL, NULL, s3_accel_out, NULL, NULL, s3);
io_removehandler(0x8548, 0x0004, s3_accel_in, NULL, NULL, s3_accel_out, NULL, NULL, s3);
io_removehandler(0x8948, 0x0004, s3_accel_in, NULL, NULL, s3_accel_out, NULL, NULL, s3);
io_removehandler(0x8d48, 0x0004, s3_accel_in, NULL, NULL, s3_accel_out, NULL, NULL, s3);
io_removehandler(0x9148, 0x0004, s3_accel_in, NULL, NULL, s3_accel_out, NULL, NULL, s3);
io_removehandler(0x9548, 0x0004, s3_accel_in, NULL, NULL, s3_accel_out, NULL, NULL, s3);
io_removehandler(0x9948, 0x0004, s3_accel_in, NULL, NULL, s3_accel_out, NULL, NULL, s3);
io_removehandler(0x9d48, 0x0002, s3_accel_in, s3_accel_in_w, NULL, s3_accel_out, s3_accel_out_w, NULL, s3);
io_removehandler(0xa148, 0x0004, s3_accel_in, NULL, NULL, s3_accel_out, NULL, NULL, s3);
io_removehandler(0xa548, 0x0004, s3_accel_in, NULL, NULL, s3_accel_out, NULL, NULL, s3);
io_removehandler(0xa948, 0x0004, s3_accel_in, NULL, NULL, s3_accel_out, NULL, NULL, s3);
io_removehandler(0xad48, 0x0004, s3_accel_in, NULL, NULL, s3_accel_out, NULL, NULL, s3);
if (s3->chip >= S3_86C928)
io_removehandler(0xb148, 0x0004, s3_accel_in, NULL, NULL, s3_accel_out, NULL, NULL, s3);
else
io_removehandler(0xb148, 0x0002, s3_accel_in, s3_accel_in_w, NULL, s3_accel_out, s3_accel_out_w, s3_accel_out_l, s3);
io_removehandler(0xb548, 0x0002, s3_accel_in, NULL, NULL, s3_accel_out, NULL, NULL, s3);
io_removehandler(0xb948, 0x0002, s3_accel_in, NULL, NULL, s3_accel_out, NULL, NULL, s3);
io_removehandler(0xbd48, 0x0002, s3_accel_in, NULL, NULL, s3_accel_out, NULL, NULL, s3);
io_removehandler(0xd148, 0x0002, s3_accel_in, NULL, NULL, s3_accel_out, NULL, NULL, s3);
io_removehandler(0xe148, 0x0004, s3_accel_in, s3_accel_in_w, s3_accel_in_l, s3_accel_out, s3_accel_out_w, s3_accel_out_l, s3);
io_removehandler(0xe548, 0x0004, s3_accel_in, NULL, NULL, s3_accel_out, NULL, NULL, s3);
io_removehandler(0xe948, 0x0004, s3_accel_in, NULL, NULL, s3_accel_out, NULL, NULL, s3);
io_removehandler(0xed48, 0x0004, s3_accel_in, NULL, NULL, s3_accel_out, NULL, NULL, s3);
}
static void
s3_io_remove(s3_t *s3)
{
io_removehandler(0x03c0, 0x0020, s3_in, NULL, NULL, s3_out, NULL, NULL, s3);
io_removehandler(0x42e8, 0x0002, s3_accel_in, NULL, NULL, s3_accel_out, NULL, NULL, s3);
io_removehandler(0x46e8, 0x0002, s3_accel_in, NULL, NULL, s3_accel_out, NULL, NULL, s3);
io_removehandler(0x4ae8, 0x0002, s3_accel_in, NULL, NULL, s3_accel_out, NULL, NULL, s3);
io_removehandler(0x82e8, 0x0004, s3_accel_in, NULL, NULL, s3_accel_out, NULL, NULL, s3);
io_removehandler(0x86e8, 0x0004, s3_accel_in, NULL, NULL, s3_accel_out, NULL, NULL, s3);
io_removehandler(0x8ae8, 0x0004, s3_accel_in, NULL, NULL, s3_accel_out, NULL, NULL, s3);
io_removehandler(0x8ee8, 0x0004, s3_accel_in, NULL, NULL, s3_accel_out, NULL, NULL, s3);
io_removehandler(0x92e8, 0x0004, s3_accel_in, NULL, NULL, s3_accel_out, NULL, NULL, s3);
io_removehandler(0x96e8, 0x0004, s3_accel_in, NULL, NULL, s3_accel_out, NULL, NULL, s3);
io_removehandler(0x9ae8, 0x0002, s3_accel_in, NULL, NULL, s3_accel_out, NULL, NULL, s3);
io_removehandler(0x9ee8, 0x0002, s3_accel_in, s3_accel_in_w, NULL, s3_accel_out, s3_accel_out_w, NULL, s3);
io_removehandler(0xa2e8, 0x0004, s3_accel_in, NULL, NULL, s3_accel_out, NULL, NULL, s3);
io_removehandler(0xa6e8, 0x0004, s3_accel_in, NULL, NULL, s3_accel_out, NULL, NULL, s3);
io_removehandler(0xaae8, 0x0004, s3_accel_in, NULL, NULL, s3_accel_out, NULL, NULL, s3);
io_removehandler(0xaee8, 0x0004, s3_accel_in, NULL, NULL, s3_accel_out, NULL, NULL, s3);
if (s3->chip >= S3_86C928)
io_removehandler(0xb2e8, 0x0004, s3_accel_in, NULL, NULL, s3_accel_out, NULL, NULL, s3);
else
io_removehandler(0xb2e8, 0x0002, s3_accel_in, s3_accel_in_w, NULL, s3_accel_out, s3_accel_out_w, s3_accel_out_l, s3);
io_removehandler(0xb6e8, 0x0002, s3_accel_in, NULL, NULL, s3_accel_out, NULL, NULL, s3);
io_removehandler(0xbae8, 0x0002, s3_accel_in, NULL, NULL, s3_accel_out, NULL, NULL, s3);
io_removehandler(0xbee8, 0x0002, s3_accel_in, NULL, NULL, s3_accel_out, NULL, NULL, s3);
io_removehandler(0xcae8, 0x0002, s3_accel_in, NULL, NULL, s3_accel_out, NULL, NULL, s3);
io_removehandler(0xd2e8, 0x0002, s3_accel_in, NULL, NULL, s3_accel_out, NULL, NULL, s3);
io_removehandler(0xe2e8, 0x0004, s3_accel_in, s3_accel_in_w, s3_accel_in_l, s3_accel_out, s3_accel_out_w, s3_accel_out_l, s3);
io_removehandler(0xe6e8, 0x0004, s3_accel_in, NULL, NULL, s3_accel_out, NULL, NULL, s3);
io_removehandler(0xeae8, 0x0004, s3_accel_in, NULL, NULL, s3_accel_out, NULL, NULL, s3);
io_removehandler(0xeee8, 0x0004, s3_accel_in, NULL, NULL, s3_accel_out, NULL, NULL, s3);
io_removehandler(0xfee8, 0x0002, s3_accel_in, NULL, NULL, s3_accel_out, NULL, NULL, s3);
s3_io_remove_alt(s3);
}
static void
s3_io_set_alt(s3_t *s3)
{
const svga_t *svga = &s3->svga;
if (!s3->translate)
return;
if ((s3->chip == S3_VISION968 || s3->chip == S3_VISION868) && (svga->seqregs[9] & 0x80)) {
return;
}
io_sethandler(0x4148, 0x0002, s3_accel_in, NULL, NULL, s3_accel_out, NULL, NULL, s3);
io_sethandler(0x4548, 0x0002, s3_accel_in, NULL, NULL, s3_accel_out, NULL, NULL, s3);
io_sethandler(0x4948, 0x0002, s3_accel_in, NULL, NULL, s3_accel_out, NULL, NULL, s3);
if (s3->chip == S3_TRIO64 || s3->chip >= S3_TRIO64V || s3->chip == S3_VISION968 || s3->chip == S3_VISION868) {
io_sethandler(0x8148, 0x0004, s3_accel_in, NULL, NULL, s3_accel_out, NULL, NULL, s3);
io_sethandler(0x8548, 0x0004, s3_accel_in, NULL, NULL, s3_accel_out, NULL, NULL, s3);
io_sethandler(0x8948, 0x0004, s3_accel_in, NULL, NULL, s3_accel_out, NULL, NULL, s3);
io_sethandler(0x8d48, 0x0004, s3_accel_in, NULL, NULL, s3_accel_out, NULL, NULL, s3);
io_sethandler(0x9148, 0x0004, s3_accel_in, NULL, NULL, s3_accel_out, NULL, NULL, s3);
io_sethandler(0x9548, 0x0004, s3_accel_in, NULL, NULL, s3_accel_out, NULL, NULL, s3);
} else {
io_sethandler(0x8148, 0x0002, s3_accel_in, NULL, NULL, s3_accel_out, NULL, NULL, s3);
io_sethandler(0x8548, 0x0002, s3_accel_in, NULL, NULL, s3_accel_out, NULL, NULL, s3);
io_sethandler(0x8948, 0x0002, s3_accel_in, NULL, NULL, s3_accel_out, NULL, NULL, s3);
io_sethandler(0x8d48, 0x0002, s3_accel_in, NULL, NULL, s3_accel_out, NULL, NULL, s3);
io_sethandler(0x9148, 0x0002, s3_accel_in, NULL, NULL, s3_accel_out, NULL, NULL, s3);
io_sethandler(0x9548, 0x0002, s3_accel_in, NULL, NULL, s3_accel_out, NULL, NULL, s3);
}
if (s3->chip == S3_VISION968 || s3->chip == S3_VISION868)
io_sethandler(0x9948, 0x0004, s3_accel_in, NULL, NULL, s3_accel_out, NULL, NULL, s3);
else
io_sethandler(0x9948, 0x0002, s3_accel_in, NULL, NULL, s3_accel_out, NULL, NULL, s3);
io_sethandler(0x9d48, 0x0002, s3_accel_in, s3_accel_in_w, NULL, s3_accel_out, s3_accel_out_w, NULL, s3);
io_sethandler(0xa148, 0x0004, s3_accel_in, NULL, NULL, s3_accel_out, NULL, NULL, s3);
io_sethandler(0xa548, 0x0004, s3_accel_in, NULL, NULL, s3_accel_out, NULL, NULL, s3);
io_sethandler(0xa948, 0x0004, s3_accel_in, NULL, NULL, s3_accel_out, NULL, NULL, s3);
io_sethandler(0xad48, 0x0004, s3_accel_in, NULL, NULL, s3_accel_out, NULL, NULL, s3);
if (s3->chip >= S3_86C928)
io_sethandler(0xb148, 0x0004, s3_accel_in, NULL, NULL, s3_accel_out, NULL, NULL, s3);
else
io_sethandler(0xb148, 0x0002, s3_accel_in, s3_accel_in_w, NULL, s3_accel_out, s3_accel_out_w, s3_accel_out_l, s3);
io_sethandler(0xb548, 0x0002, s3_accel_in, NULL, NULL, s3_accel_out, NULL, NULL, s3);
io_sethandler(0xb948, 0x0002, s3_accel_in, NULL, NULL, s3_accel_out, NULL, NULL, s3);
io_sethandler(0xbd48, 0x0002, s3_accel_in, NULL, NULL, s3_accel_out, NULL, NULL, s3);
io_sethandler(0xe148, 0x0004, s3_accel_in, s3_accel_in_w, s3_accel_in_l, s3_accel_out, s3_accel_out_w, s3_accel_out_l, s3);
if (s3->chip == S3_VISION968 || s3->chip == S3_VISION868) {
io_sethandler(0xd148, 0x0002, s3_accel_in, NULL, NULL, s3_accel_out, NULL, NULL, s3);
io_sethandler(0xe548, 0x0004, s3_accel_in, NULL, NULL, s3_accel_out, NULL, NULL, s3);
io_sethandler(0xe948, 0x0004, s3_accel_in, NULL, NULL, s3_accel_out, NULL, NULL, s3);
io_sethandler(0xed48, 0x0004, s3_accel_in, NULL, NULL, s3_accel_out, NULL, NULL, s3);
}
}
static void
s3_io_set(s3_t *s3)
{
const svga_t *svga = &s3->svga;
s3_io_remove(s3);
io_sethandler(0x03c0, 0x0020, s3_in, NULL, NULL, s3_out, NULL, NULL, s3);
if ((s3->chip == S3_VISION968 || s3->chip == S3_VISION868) && (svga->seqregs[9] & 0x80)) {
return;
}
io_sethandler(0x42e8, 0x0002, s3_accel_in, NULL, NULL, s3_accel_out, NULL, NULL, s3);
io_sethandler(0x46e8, 0x0002, s3_accel_in, NULL, NULL, s3_accel_out, NULL, NULL, s3);
io_sethandler(0x4ae8, 0x0002, s3_accel_in, NULL, NULL, s3_accel_out, NULL, NULL, s3);
if (s3->chip == S3_TRIO64 || s3->chip >= S3_TRIO64V || s3->chip == S3_VISION968 || s3->chip == S3_VISION868) {
io_sethandler(0x82e8, 0x0004, s3_accel_in, NULL, NULL, s3_accel_out, NULL, NULL, s3);
io_sethandler(0x86e8, 0x0004, s3_accel_in, NULL, NULL, s3_accel_out, NULL, NULL, s3);
io_sethandler(0x8ae8, 0x0004, s3_accel_in, NULL, NULL, s3_accel_out, NULL, NULL, s3);
io_sethandler(0x8ee8, 0x0004, s3_accel_in, NULL, NULL, s3_accel_out, NULL, NULL, s3);
io_sethandler(0x92e8, 0x0004, s3_accel_in, NULL, NULL, s3_accel_out, NULL, NULL, s3);
io_sethandler(0x96e8, 0x0004, s3_accel_in, NULL, NULL, s3_accel_out, NULL, NULL, s3);
} else {
io_sethandler(0x82e8, 0x0002, s3_accel_in, NULL, NULL, s3_accel_out, NULL, NULL, s3);
io_sethandler(0x86e8, 0x0002, s3_accel_in, NULL, NULL, s3_accel_out, NULL, NULL, s3);
io_sethandler(0x8ae8, 0x0002, s3_accel_in, NULL, NULL, s3_accel_out, NULL, NULL, s3);
io_sethandler(0x8ee8, 0x0002, s3_accel_in, NULL, NULL, s3_accel_out, NULL, NULL, s3);
io_sethandler(0x92e8, 0x0002, s3_accel_in, NULL, NULL, s3_accel_out, NULL, NULL, s3);
io_sethandler(0x96e8, 0x0002, s3_accel_in, NULL, NULL, s3_accel_out, NULL, NULL, s3);
}
if (s3->chip == S3_VISION968 || s3->chip == S3_VISION868)
io_sethandler(0x9ae8, 0x0004, s3_accel_in, NULL, NULL, s3_accel_out, NULL, NULL, s3);
else
io_sethandler(0x9ae8, 0x0002, s3_accel_in, NULL, NULL, s3_accel_out, NULL, NULL, s3);
io_sethandler(0x9ee8, 0x0002, s3_accel_in, s3_accel_in_w, NULL, s3_accel_out, s3_accel_out_w, NULL, s3);
io_sethandler(0xa2e8, 0x0004, s3_accel_in, NULL, NULL, s3_accel_out, NULL, NULL, s3);
io_sethandler(0xa6e8, 0x0004, s3_accel_in, NULL, NULL, s3_accel_out, NULL, NULL, s3);
io_sethandler(0xaae8, 0x0004, s3_accel_in, NULL, NULL, s3_accel_out, NULL, NULL, s3);
io_sethandler(0xaee8, 0x0004, s3_accel_in, NULL, NULL, s3_accel_out, NULL, NULL, s3);
if (s3->chip >= S3_86C928)
io_sethandler(0xb2e8, 0x0004, s3_accel_in, NULL, NULL, s3_accel_out, NULL, NULL, s3);
else
io_sethandler(0xb2e8, 0x0002, s3_accel_in, s3_accel_in_w, NULL, s3_accel_out, s3_accel_out_w, s3_accel_out_l, s3);
io_sethandler(0xb6e8, 0x0002, s3_accel_in, NULL, NULL, s3_accel_out, NULL, NULL, s3);
io_sethandler(0xbae8, 0x0002, s3_accel_in, NULL, NULL, s3_accel_out, NULL, NULL, s3);
io_sethandler(0xbee8, 0x0002, s3_accel_in, NULL, NULL, s3_accel_out, NULL, NULL, s3);
io_sethandler(0xcae8, 0x0002, s3_accel_in, NULL, NULL, s3_accel_out, NULL, NULL, s3);
io_sethandler(0xe2e8, 0x0004, s3_accel_in, s3_accel_in_w, s3_accel_in_l, s3_accel_out, s3_accel_out_w, s3_accel_out_l, s3);
if (s3->chip == S3_VISION968 || s3->chip == S3_VISION868) {
io_sethandler(0xd2e8, 0x0002, s3_accel_in, NULL, NULL, s3_accel_out, NULL, NULL, s3);
io_sethandler(0xe6e8, 0x0004, s3_accel_in, NULL, NULL, s3_accel_out, NULL, NULL, s3);
io_sethandler(0xeae8, 0x0004, s3_accel_in, NULL, NULL, s3_accel_out, NULL, NULL, s3);
io_sethandler(0xeee8, 0x0004, s3_accel_in, NULL, NULL, s3_accel_out, NULL, NULL, s3);
}
io_sethandler(0xfee8, 0x0002, s3_accel_in, NULL, NULL, s3_accel_out, NULL, NULL, s3);
s3_io_set_alt(s3);
}
static void
s3_out(uint16_t addr, uint8_t val, void *priv)
{
s3_t *s3 = (s3_t *) priv;
svga_t *svga = &s3->svga;
uint8_t old;
int rs2;
int rs3;
if (((addr & 0xfff0) == 0x3d0 || (addr & 0xfff0) == 0x3b0) && !(svga->miscout & 1))
addr ^= 0x60;
switch (addr) {
case 0x3c2:
if ((s3->chip == S3_VISION964) || (s3->chip == S3_VISION968) || (s3->chip == S3_86C928)) {
if ((s3->card_type != S3_SPEA_MERCURY_P64V) && (s3->card_type != S3_MIROVIDEO40SV_ERGO_968)) {
if (((val >> 2) & 3) != 3)
icd2061_write(svga->clock_gen, (val >> 2) & 3);
}
}
break;
case 0x3c5:
if (svga->seqaddr >= 0x10 && svga->seqaddr < 0x20) {
svga->seqregs[svga->seqaddr] = val;
switch (svga->seqaddr) {
case 0x12:
case 0x13:
svga_recalctimings(svga);
return;
default:
break;
}
}
if (svga->seqaddr == 4) /*Chain-4 - update banking*/
{
if (val & 0x08)
svga->write_bank = svga->read_bank = s3->bank << 16;
else
svga->write_bank = svga->read_bank = s3->bank << 14;
} else if (svga->seqaddr == 9) {
svga->seqregs[svga->seqaddr] = val & 0x80;
s3_io_set(s3);
return;
} else if (svga->seqaddr == 0xa) {
svga->seqregs[svga->seqaddr] = val & 0x80;
return;
} else if (s3->chip >= S3_VISION964) {
if (svga->seqaddr == 0x08) {
svga->seqregs[svga->seqaddr] = val & 0x0f;
return;
} else if ((svga->seqaddr == 0x0d) && (svga->seqregs[0x08] == 0x06)) {
svga->seqregs[svga->seqaddr] = val;
svga->dpms = ((s3->chip >= S3_VISION964) && (svga->seqregs[0x0d] & 0x50)) || (svga->crtc[0x56] & ((s3->chip >= S3_TRIO32) ? 0x06 : 0x20));
svga_recalctimings(svga);
return;
}
}
break;
case 0x3C6:
case 0x3C7:
case 0x3C8:
case 0x3C9:
case 0x3CA: /*0x3c6 alias*/
case 0x3CB: /*0x3c7 alias*/
rs2 = (svga->crtc[0x55] & 0x01) || !!(svga->crtc[0x43] & 2);
if (s3->chip >= S3_TRIO32)
svga_out(addr, val, svga);
else if ((s3->chip == S3_VISION964 && s3->card_type != S3_ELSAWIN2KPROX_964) || (s3->chip == S3_86C928)) {
rs3 = !!(svga->crtc[0x55] & 0x02);
bt48x_ramdac_out(addr, rs2, rs3, val, svga->ramdac, svga);
} else if ((s3->chip == S3_VISION964 && s3->card_type == S3_ELSAWIN2KPROX_964) || (s3->chip == S3_VISION968 && (s3->card_type == S3_DIAMOND_STEALTH64_968 || s3->card_type == S3_ELSAWIN2KPROX || s3->card_type == S3_PHOENIX_VISION968 || s3->card_type == S3_NUMBER9_9FX_771)))
ibm_rgb528_ramdac_out(addr, rs2, val, svga->ramdac, svga);
else if (s3->chip == S3_VISION968 && (s3->card_type == S3_SPEA_MERCURY_P64V || s3->card_type == S3_MIROVIDEO40SV_ERGO_968)) {
rs3 = !!(svga->crtc[0x55] & 0x02);
tvp3026_ramdac_out(addr, rs2, rs3, val, svga->ramdac, svga);
} else if (((s3->chip == S3_86C801) || (s3->chip == S3_86C805) || (s3->chip == S3_86C924)) &&
((s3->card_type != S3_MIROCRYSTAL10SD_805) && (s3->card_type != S3_MIROCRYSTAL8S_805)))
att49x_ramdac_out(addr, rs2, val, svga->ramdac, svga);
else if (s3->chip == S3_86C911) {
sc1148x_ramdac_out(addr, rs2, val, svga->ramdac, svga);
} else if (s3->card_type == S3_NUMBER9_9FX_531)
att498_ramdac_out(addr, rs2, val, svga->ramdac, svga);
else if ((s3->chip == S3_86C928PCI) && (s3->card_type == S3_SPEA_MERCURY_LITE_PCI))
sc1502x_ramdac_out(addr, val, svga->ramdac, svga);
else
sdac_ramdac_out(addr, rs2, val, svga->ramdac, svga);
return;
case 0x3D4:
svga->crtcreg = (s3->chip == S3_TRIO64V2) ? val : (val & 0x7f);
return;
case 0x3D5:
if ((svga->crtcreg < 7) && (svga->crtc[0x11] & 0x80))
return;
if ((svga->crtcreg == 7) && (svga->crtc[0x11] & 0x80))
val = (svga->crtc[7] & ~0x10) | (val & 0x10);
if ((svga->crtcreg >= 0x20) && (svga->crtcreg < 0x40) && (svga->crtcreg != 0x36) && (svga->crtcreg != 0x38) && (svga->crtcreg != 0x39) && ((svga->crtc[0x38] & 0xcc) != 0x48))
return;
if ((svga->crtcreg >= 0x40) && ((svga->crtc[0x39] & 0xe0) != 0xa0))
return;
if ((svga->crtcreg == 0x36) && (svga->crtc[0x39] != 0xa5))
return;
if ((s3->chip == S3_TRIO64V2) && (svga->crtcreg >= 0x80))
return;
if ((s3->chip <= S3_86C924) && (svga->crtcreg >= 0x50))
return;
old = svga->crtc[svga->crtcreg];
svga->crtc[svga->crtcreg] = val;
switch (svga->crtcreg) {
case 0x31:
s3->ma_ext = (s3->ma_ext & 0x1c) | ((val & 0x30) >> 4);
svga->force_dword_mode = !!(val & 0x08);
break;
case 0x40:
s3->enable_8514 = (val & 0x01);
break;
case 0x50:
s3->bpp = (svga->crtc[0x50] >> 4) & 3;
if (s3->bpp == 3) {
if (!(s3->accel.multifunc[0xe] & 0x200)) /*On True Color mode change, reset bit 4 of Misc Index register*/
s3->accel.multifunc[0xe] &= ~0x10;
}
break;
case 0x5c:
if ((val & 0xa0) == 0x80)
i2c_gpio_set(s3->i2c, !!(val & 0x40), !!(val & 0x10));
if (s3->card_type == S3_PHOENIX_VISION868 || s3->card_type == S3_PHOENIX_VISION968) {
if ((val & 0x20) && (!(svga->crtc[0x55] & 0x01) && !(svga->crtc[0x43] & 2)))
svga->dac_addr |= 0x20;
} else if (s3->card_type == S3_MIROVIDEO40SV_ERGO_968) {
if ((val & 0x80) && (!(svga->crtc[0x55] & 0x01) && !(svga->crtc[0x43] & 2)))
svga->dac_addr |= 0x02;
}
break;
case 0x69:
if (s3->chip >= S3_VISION964)
s3->ma_ext = val & 0x1f;
break;
case 0x35:
s3->bank = (s3->bank & 0x70) | (val & 0xf);
if (svga->chain4)
svga->write_bank = svga->read_bank = s3->bank << 16;
else
svga->write_bank = svga->read_bank = s3->bank << 14;
break;
case 0x51:
if (s3->chip == S3_86C801 || s3->chip == S3_86C805) {
s3->bank = (s3->bank & 0x6f) | ((val & 0x4) << 2);
s3->ma_ext = (s3->ma_ext & ~0x4) | ((val & 1) << 2);
} else {
s3->bank = (s3->bank & 0x4f) | ((val & 0xc) << 2);
s3->ma_ext = (s3->ma_ext & ~0xc) | ((val & 3) << 2);
}
if (svga->chain4)
svga->write_bank = svga->read_bank = s3->bank << 16;
else
svga->write_bank = svga->read_bank = s3->bank << 14;
break;
case 0x6a:
if (s3->chip >= S3_VISION964) {
s3->bank = val;
if (svga->chain4)
svga->write_bank = svga->read_bank = s3->bank << 16;
else
svga->write_bank = svga->read_bank = s3->bank << 14;
}
break;
case 0x45:
if (s3->chip == S3_VISION964 || s3->chip == S3_VISION968)
break;
svga->hwcursor.ena = val & 1;
break;
case 0x46:
case 0x47:
case 0x48:
case 0x49:
case 0x4c:
case 0x4d:
case 0x4e:
case 0x4f:
if (s3->chip == S3_VISION964 || s3->chip == S3_VISION968)
break;
svga->hwcursor.x = ((svga->crtc[0x46] << 8) | svga->crtc[0x47]) & 0x7ff;
if (svga->bpp == 32)
svga->hwcursor.x >>= 1;
svga->hwcursor.y = ((svga->crtc[0x48] << 8) | svga->crtc[0x49]) & 0x7ff;
svga->hwcursor.xoff = svga->crtc[0x4e] & 0x3f;
svga->hwcursor.yoff = svga->crtc[0x4f] & 0x3f;
svga->hwcursor.addr = ((((svga->crtc[0x4c] << 8) | svga->crtc[0x4d]) & 0xfff) * 1024) + (svga->hwcursor.yoff * 16);
if ((s3->chip >= S3_TRIO32) && svga->bpp == 32)
svga->hwcursor.x <<= 1;
else if ((s3->chip >= S3_86C928 && s3->chip <= S3_86C805) && (svga->bpp == 15 || svga->bpp == 16)) {
if ((s3->card_type == S3_MIROCRYSTAL10SD_805) && !(svga->crtc[0x45] & 0x04) && svga->bpp == 16)
svga->hwcursor.x >>= 2;
else
svga->hwcursor.x >>= 1;
} else if ((s3->chip >= S3_86C928 && s3->chip <= S3_86C805) && (svga->bpp == 24))
svga->hwcursor.x /= 3;
else if ((s3->chip <= S3_86C805) && s3->color_16bit)
svga->hwcursor.x >>= 1;
break;
case 0x4a:
switch (s3->hwc_col_stack_pos) {
case 0:
s3->hwc_fg_col = (s3->hwc_fg_col & 0xffff00) | val;
break;
case 1:
s3->hwc_fg_col = (s3->hwc_fg_col & 0xff00ff) | (val << 8);
break;
case 2:
s3->hwc_fg_col = (s3->hwc_fg_col & 0x00ffff) | (val << 16);
break;
default:
break;
}
s3->hwc_col_stack_pos = (s3->hwc_col_stack_pos + 1) & 3;
break;
case 0x4b:
switch (s3->hwc_col_stack_pos) {
case 0:
s3->hwc_bg_col = (s3->hwc_bg_col & 0xffff00) | val;
break;
case 1:
s3->hwc_bg_col = (s3->hwc_bg_col & 0xff00ff) | (val << 8);
break;
case 2:
s3->hwc_bg_col = (s3->hwc_bg_col & 0x00ffff) | (val << 16);
break;
default:
break;
}
s3->hwc_col_stack_pos = (s3->hwc_col_stack_pos + 1) & 3;
break;
case 0x53:
case 0x58:
case 0x59:
case 0x5a:
s3_log("[%04X:%08X]: Write CRTC%02x=%02x.\n", CS, cpu_state.pc, svga->crtcreg, svga->crtc[svga->crtcreg]);
s3_updatemapping(s3);
break;
case 0x55:
s3_log("[%04X:%08X]: Write CRTC%02x=%02x.\n", CS, cpu_state.pc, svga->crtcreg, svga->crtc[svga->crtcreg]);
if (s3->chip == S3_86C928) {
if (val & 0x28) {
svga->hwcursor_draw = NULL;
svga->dac_hwcursor_draw = bt48x_hwcursor_draw;
} else {
svga->hwcursor_draw = s3_hwcursor_draw;
svga->dac_hwcursor_draw = NULL;
}
}
break;
case 0x42:
if ((s3->chip == S3_VISION964) || (s3->chip == S3_VISION968) || (s3->chip == S3_86C928)) {
if (((svga->miscout >> 2) & 3) == 3)
icd2061_write(svga->clock_gen, svga->crtc[0x42] & 0x0f);
}
break;
case 0x43:
if (s3->chip < S3_VISION964) {
if (s3->chip <= S3_86C805) {
s3->color_16bit = !!(val & 8);
if (s3->color_16bit) {
s3->width = 1024;
} else {
if (s3->chip <= S3_86C924)
s3->width = 1024;
else {
if (s3->accel.advfunc_cntl & 4)
s3->width = 1024;
else
s3->width = 640;
}
}
}
s3_io_remove_alt(s3);
s3->translate = !!(val & 0x10);
s3_io_set_alt(s3);
}
break;
case 0x56:
svga->dpms = ((s3->chip >= S3_VISION964) && (svga->seqregs[0x0d] & 0x50)) || (svga->crtc[0x56] & ((s3->chip >= S3_TRIO32) ? 0x06 : 0x20));
old = ~val; /* force recalc */
break;
case 0x67:
if (s3->chip >= S3_TRIO32) {
switch (val >> 4) {
case 3:
svga->bpp = 15;
break;
case 5:
svga->bpp = 16;
break;
case 7:
svga->bpp = 24;
break;
case 13:
svga->bpp = 32;
break;
default:
svga->bpp = 8;
break;
}
}
break;
default:
break;
}
if (old != val) {
if (svga->crtcreg < 0xe || svga->crtcreg > 0x10) {
if ((svga->crtcreg == 0xc) || (svga->crtcreg == 0xd)) {
svga->fullchange = 3;
svga->ma_latch = ((svga->crtc[0xc] << 8) | svga->crtc[0xd]) + ((svga->crtc[8] & 0x60) >> 5);
if ((((svga->crtc[0x67] & 0xc) != 0xc) && (s3->chip >= S3_TRIO64V)) || (s3->chip < S3_TRIO64V))
svga->ma_latch |= (s3->ma_ext << 16);
} else {
svga->fullchange = svga->monitor->mon_changeframecount;
svga_recalctimings(svga);
}
}
}
break;
default:
break;
}
svga_out(addr, val, svga);
}
static uint8_t
s3_in(uint16_t addr, void *priv)
{
s3_t *s3 = (s3_t *) priv;
svga_t *svga = &s3->svga;
int rs2;
int rs3;
uint8_t temp;
if (((addr & 0xfff0) == 0x3d0 || (addr & 0xfff0) == 0x3b0) && !(svga->miscout & 1))
addr ^= 0x60;
switch (addr) {
case 0x3c1:
if (svga->attraddr > 0x14)
return 0xff;
break;
case 0x3c2:
if (s3->chip <= S3_86C924)
return svga_in(addr, svga) | 0x10;
break;
case 0x3c5:
if (svga->seqaddr >= 0x10 && svga->seqaddr < 0x20) {
temp = svga->seqregs[svga->seqaddr];
/* This is needed for the Intel Advanced/ATX's built-in S3 Trio64V+ BIOS to not
get stuck in an infinite loop. */
if (((s3->card_type == S3_STB_POWERGRAPH_64_VIDEO) ||
(s3->card_type == S3_PHOENIX_TRIO64VPLUS_ONBOARD) ||
(s3->card_type == S3_CARDEX_TRIO64VPLUS)) && (svga->seqaddr == 0x17))
svga->seqregs[svga->seqaddr] ^= 0x01;
return temp;
} else if ((svga->seqaddr >= 5) && (svga->seqaddr < 8))
return 0xff;
else
return svga->seqregs[svga->seqaddr];
break;
case 0x3c6:
case 0x3c7:
case 0x3c8:
case 0x3c9:
case 0x3ca: /*0x3c6 alias*/
case 0x3cb: /*0x3c7 alias*/
rs2 = (svga->crtc[0x55] & 0x01) || !!(svga->crtc[0x43] & 2);
if (s3->chip >= S3_TRIO32)
return svga_in(addr, svga);
else if ((s3->chip == S3_VISION964 && s3->card_type != S3_ELSAWIN2KPROX_964) || (s3->chip == S3_86C928)) {
if (s3->chip == S3_86C928)
rs3 = !!(svga->crtc[0x55] & 0x28) || !!(svga->crtc[0x45] & 0x20) || !!(svga->crtc[0x55] & 0x02); /*Quite insane but Win95's S3 driver wants it set at all costs for 8bpp+ mode*/
else
rs3 = !!(svga->crtc[0x55] & 0x02);
temp = bt48x_ramdac_in(addr, rs2, rs3, svga->ramdac, svga);
return temp;
} else if ((s3->chip == S3_VISION964 && s3->card_type == S3_ELSAWIN2KPROX_964) || (s3->chip == S3_VISION968 && (s3->card_type == S3_DIAMOND_STEALTH64_968 || s3->card_type == S3_ELSAWIN2KPROX || s3->card_type == S3_PHOENIX_VISION968 || s3->card_type == S3_NUMBER9_9FX_771)))
return ibm_rgb528_ramdac_in(addr, rs2, svga->ramdac, svga);
else if (s3->chip == S3_VISION968 && (s3->card_type == S3_SPEA_MERCURY_P64V || s3->card_type == S3_MIROVIDEO40SV_ERGO_968)) {
rs3 = !!(svga->crtc[0x55] & 0x02);
return tvp3026_ramdac_in(addr, rs2, rs3, svga->ramdac, svga);
} else if (((s3->chip == S3_86C801) || (s3->chip == S3_86C805) || (s3->chip == S3_86C924)) &&
((s3->card_type != S3_MIROCRYSTAL10SD_805) && (s3->card_type != S3_MIROCRYSTAL8S_805)))
return att49x_ramdac_in(addr, rs2, svga->ramdac, svga);
else if (s3->chip == S3_86C911)
return sc1148x_ramdac_in(addr, rs2, svga->ramdac, svga);
else if (s3->card_type == S3_NUMBER9_9FX_531)
return att498_ramdac_in(addr, rs2, svga->ramdac, svga);
else if ((s3->chip == S3_86C928PCI) && (s3->card_type == S3_SPEA_MERCURY_LITE_PCI))
return sc1502x_ramdac_in(addr, svga->ramdac, svga);
else
return sdac_ramdac_in(addr, rs2, svga->ramdac, svga);
case 0x3d4:
return svga->crtcreg;
case 0x3d5:
switch (svga->crtcreg) {
case 0x2d:
return (s3->chip == S3_TRIO64V2) ? 0x89 : 0x88; /*Extended chip ID*/
case 0x2e:
return s3->id_ext; /*New chip ID*/
case 0x2f: switch (s3->chip) { /*Revision level*/
case S3_TRIO64V:
return 0x40;
case S3_TRIO64V2:
return 0x16; /*Confirmed on an onboard 64V2/DX*/
default:
return 0x00;
}
break;
case 0x30:
return s3->id; /*Chip ID*/
case 0x31:
return (svga->crtc[0x31] & 0xcf) | ((s3->ma_ext & 3) << 4);
case 0x35:
return (svga->crtc[0x35] & 0xf0) | (s3->bank & 0xf);
case 0x45:
s3->hwc_col_stack_pos = 0;
return svga->crtc[0x45];
case 0x51:
return (svga->crtc[0x51] & 0xf0) | ((s3->bank >> 2) & 0xc) | ((s3->ma_ext >> 2) & 3);
case 0x5c: /* General Output Port Register */
temp = svga->crtc[svga->crtcreg] & 0xa0;
if (((svga->miscout >> 2) & 3) == 3)
temp |= svga->crtc[0x42] & 0x0f;
else
temp |= ((svga->miscout >> 2) & 3);
if ((temp & 0xa0) == 0xa0) {
if ((svga->crtc[0x5c] & 0x40) && i2c_gpio_get_scl(s3->i2c))
temp |= 0x40;
if ((svga->crtc[0x5c] & 0x10) && i2c_gpio_get_sda(s3->i2c))
temp |= 0x10;
}
return temp;
case 0x69:
return s3->ma_ext;
case 0x6a:
return s3->bank;
/* Phoenix S3 video BIOS'es seem to expect CRTC registers 6B and 6C
to be mirrors of 59 and 5A. */
case 0x6b:
s3_log("[%04X:%08X]: Read CRTC6b=%02x.\n", CS, cpu_state.pc, svga->crtc[0x6b]);
if (s3->chip != S3_TRIO64V2) {
if (svga->crtc[0x53] & 0x08) {
return (s3->chip == S3_TRIO64V) ? (svga->crtc[0x59] & 0xfc) : (svga->crtc[0x59] & 0xfe);
} else {
return svga->crtc[0x59];
}
} else
return svga->crtc[0x6b];
break;
case 0x6c:
s3_log("[%04X:%08X]: Read CRTC6c=%02x.\n", CS, cpu_state.pc, svga->crtc[0x6c]);
if (s3->chip != S3_TRIO64V2) {
if (svga->crtc[0x53] & 0x08) {
return 0x00;
} else
return (svga->crtc[0x5a] & 0x80);
} else
return svga->crtc[0x6c];
break;
default:
break;
}
return svga->crtc[svga->crtcreg];
default:
break;
}
return svga_in(addr, svga);
}
static void
s3_recalctimings(svga_t *svga)
{
s3_t *s3 = (s3_t *) svga->priv;
int clk_sel = (svga->miscout >> 2) & 3;
uint8_t mask = 0xc0;
if (svga->crtc[0x33] & 0x20) {
/* In this mode, the dots per clock are always 8 or 16, never 9 or 18. */
if (!svga->scrblank && svga->attr_palette_enable)
svga->dots_per_clock = (svga->seqregs[1] & 8) ? 16 : 8;
} else {
if (!svga->scrblank && svga->attr_palette_enable && (svga->crtc[0x43] & 0x80)) {
/* TODO: In case of bug reports, disable 9-dots-wide character clocks in graphics modes. */
svga->dots_per_clock = ((svga->seqregs[1] & 1) ? 16 : 18);
}
}
svga->hdisp = svga->hdisp_old;
svga->ma_latch |= (s3->ma_ext << 16);
svga->lowres = (!!(svga->attrregs[0x10] & 0x40) && !(svga->crtc[0x3a] & 0x10));
if (s3->chip >= S3_86C928) {
if (svga->crtc[0x5d] & 0x01)
svga->htotal |= 0x100;
if (svga->crtc[0x5d] & 0x02) {
svga->hdisp_time |= 0x100;
svga->hdisp |= (0x100 * svga->dots_per_clock);
}
if (svga->crtc[0x5e] & 0x01)
svga->vtotal |= 0x400;
if (svga->crtc[0x5e] & 0x02)
svga->dispend |= 0x400;
if (svga->crtc[0x5e] & 0x04)
svga->vblankstart |= 0x400;
else if ((svga->crtc[0x3a] & 0x10) && !svga->lowres)
svga->vblankstart = svga->dispend; /*Applies only to Enhanced modes*/
if (svga->crtc[0x5e] & 0x10)
svga->vsyncstart |= 0x400;
if (svga->crtc[0x5e] & 0x40)
svga->split |= 0x400;
if (s3->accel.advfunc_cntl & 0x01)
svga->split = 0x7fff;
if (svga->crtc[0x51] & 0x30)
svga->rowoffset |= (svga->crtc[0x51] & 0x30) << 4;
else if (svga->crtc[0x43] & 0x04)
svga->rowoffset |= 0x100;
} else if (svga->crtc[0x43] & 0x04)
svga->rowoffset |= 0x100;
if (!svga->rowoffset)
svga->rowoffset = 0x100;
if ((s3->chip == S3_VISION964) || (s3->chip == S3_86C928)) {
if (s3->card_type == S3_ELSAWIN2KPROX_964)
ibm_rgb528_recalctimings(svga->ramdac, svga);
else {
bt48x_recalctimings(svga->ramdac, svga);
svga->interlace |= (!!(svga->crtc[0x42] & 0x20));
}
} else if (s3->chip == S3_VISION968) {
if ((s3->card_type == S3_SPEA_MERCURY_P64V) || (s3->card_type == S3_MIROVIDEO40SV_ERGO_968))
tvp3026_recalctimings(svga->ramdac, svga);
else
ibm_rgb528_recalctimings(svga->ramdac, svga);
} else
svga->interlace = !!(svga->crtc[0x42] & 0x20);
if ((((svga->miscout >> 2) & 3) == 3) && (s3->chip < S3_TRIO32))
clk_sel = svga->crtc[0x42] & 0x0f;
svga->clock = (cpuclock * (double) (1ULL << 32)) / svga->getclock(clk_sel, svga->clock_gen);
switch (svga->crtc[0x67] >> 4) {
case 3:
case 5:
case 7:
svga->clock /= 2;
break;
default:
break;
}
if (s3->chip != S3_86C801)
mask |= 0x01;
switch (svga->crtc[0x50] & mask) {
case 0x00:
if (s3->color_16bit)
s3->width = 1024;
else
s3->width = (svga->crtc[0x31] & 2) ? 2048 : 1024;
break;
case 0x01:
s3->width = 1152;
break;
case 0x40:
s3->width = 640;
break;
case 0x80:
s3->width = ((s3->chip > S3_86C805) && (s3->accel.advfunc_cntl & 4)) ? 1600 : 800;
break;
case 0x81:
s3->width = 1600;
break;
case 0xc0:
s3->width = 1280;
break;
default:
break;
}
if (svga->crtc[0x33] & 0x20) {
/* The S3 version of the Cirrus' special blanking mode, with identical behavior. */
svga->hblankstart = (((svga->crtc[0x5d] & 0x02) >> 1) << 8) + svga->crtc[1]/* +
((svga->crtc[3] >> 5) & 3) + 1*/;
svga->hblank_end_val = svga->htotal - 1 /* + ((svga->crtc[3] >> 5) & 3)*/;
svga->monitor->mon_overscan_y = 0;
svga->monitor->mon_overscan_x = 0;
/* Also make sure vertical blanking starts on display end. */
svga->vblankstart = svga->dispend;
if (s3->chip >= S3_VISION964)
svga->hblank_end_mask = 0x7f;
} else if (s3->chip >= S3_86C801) {
svga->hblankstart = (((svga->crtc[0x5d] & 0x04) >> 2) << 8) + svga->crtc[2];
if (s3->chip >= S3_VISION964) {
/* NOTE: The S3 Trio64V+ datasheet says this is bit 7, but then where is bit 6?
The datasheets for the pre-Trio64V+ cards say +64, which implies bit 6,
and, contrary to VGADOC, it also exists on Trio32, Trio64, Vision868,
and Vision968. */
svga->hblank_end_val = (svga->crtc[3] & 0x1f) | (((svga->crtc[5] & 0x80) >> 7) << 5) |
(((svga->crtc[0x5d] & 0x08) >> 3) << 6);
svga->hblank_end_mask = 0x7f;
}
}
#ifdef OLD_CODE_REFERENCE
if (s3->card_type == S3_MIROCRYSTAL10SD_805 || s3->card_type == S3_MIROCRYSTAL20SD_864 || s3->card_type == S3_MIROCRYSTAL20SV_964 || s3->card_type == S3_SPEA_MIRAGE_86C801 || s3->card_type == S3_SPEA_MIRAGE_86C805 || s3->card_type == S3_MIROCRYSTAL8S_805 || s3->card_type == S3_NUMBER9_9FX_531 || s3->card_type == S3_SPEA_MERCURY_LITE_PCI) {
if (!(svga->crtc[0x5e] & 0x04))
svga->vblankstart = svga->dispend;
if (svga->bpp != 32) {
if (svga->crtc[0x31] & 2)
s3->width = 2048;
else {
if (s3->card_type == S3_MIROCRYSTAL10SD_805) {
if (svga->hdisp == 1280 && s3->width == 1024) {
s3->width = 1280;
}
}
}
} else {
if (s3->card_type == S3_NUMBER9_9FX_531) {
if ((svga->hdisp == 1600) && (s3->width == 1600))
s3->width = 800;
}
}
} else if (s3->chip == S3_86C928) {
if (svga->bpp == 15) {
if (s3->width == 800)
s3->width = 1024;
}
}
#endif
if ((svga->crtc[0x3a] & 0x10) && !svga->lowres) {
svga->vram_display_mask = s3->vram_mask;
s3_log("BPP=%d, pitch=%d, width=%02x, double?=%x, 16bit?=%d, highres?=%d, "
"attr=%02x, hdisp=%d.\n", svga->bpp, s3->width, svga->crtc[0x50],
svga->crtc[0x31] & 0x02, s3->color_16bit, s3->accel.advfunc_cntl & 4,
svga->attrregs[0x10] & 0x40, svga->hdisp);
switch (svga->bpp) {
case 8:
svga->render = svga_render_8bpp_highres;
switch (s3->chip) {
case S3_86C928:
switch (s3->card_type) {
case S3_METHEUS_86C928:
switch (s3->width) {
case 1280: /*Account for the 1280x1024 resolution*/
switch (svga->hdisp) {
case 320:
svga->hdisp <<= 2;
svga->dots_per_clock <<= 2;
break;
case 640:
svga->hdisp <<= 1;
svga->dots_per_clock <<= 1;
break;
default:
break;
}
break;
case 2048: /*Account for the 1280x1024 resolution*/
switch (svga->hdisp) {
case 320:
svga->hdisp <<= 2;
svga->dots_per_clock <<= 2;
break;
case 640:
svga->hdisp <<= 1;
svga->dots_per_clock <<= 1;
break;
default:
break;
}
break;
default:
break;
}
break;
default:
break;
}
break;
case S3_86C928PCI:
switch (s3->card_type) {
case S3_SPEA_MERCURY_LITE_PCI:
switch (s3->width) {
case 640:
svga->hdisp >>= 1;
svga->dots_per_clock >>= 1;
break;
default:
break;
}
break;
default:
break;
}
break;
case S3_VISION964:
switch (s3->card_type) {
case S3_ELSAWIN2KPROX_964:
switch (s3->width) {
case 1280:
case 1600:
svga->hdisp <<= 1;
svga->dots_per_clock <<= 1;
default:
break;
}
break;
default:
break;
}
break;
case S3_VISION968:
switch (s3->card_type) {
case S3_MIROVIDEO40SV_ERGO_968:
if (svga->hdisp == 832)
svga->hdisp -= 32;
break;
case S3_DIAMOND_STEALTH64_968:
case S3_NUMBER9_9FX_771:
case S3_PHOENIX_VISION968:
case S3_SPEA_MERCURY_P64V:
svga->hdisp <<= 1;
svga->dots_per_clock <<= 1;
if (svga->hdisp == 832)
svga->hdisp -= 32;
break;
case S3_ELSAWIN2KPROX:
switch (s3->width) {
case 1280:
case 1600:
svga->hdisp <<= 1;
svga->dots_per_clock <<= 1;
default:
break;
}
break;
default:
break;
}
break;
default:
break;
}
#ifdef OLD_CODE_REFERENCE
if (s3->chip != S3_VISION868) {
if (s3->chip == S3_86C928) {
if (s3->width == 2048 || s3->width == 1280 || s3->width == 1600) {
if ((s3->width != 1600) && (svga->dispend == 1024) && (svga->hdisp != 1280))
svga->hdisp <<= 2;
else
svga->hdisp <<= 1;
}
} else if ((s3->chip != S3_86C801) && (s3->chip != S3_86C805) && (s3->chip != S3_TRIO32) && (s3->chip != S3_TRIO64) && (s3->chip != S3_VISION964) && (s3->chip != S3_VISION968)) {
if (s3->width == 1280 || s3->width == 1600)
svga->hdisp <<= 1;
} else if ((s3->card_type == S3_ELSAWIN2KPROX_964) || (s3->card_type == S3_ELSAWIN2KPROX)) {
if (s3->width == 1280 || s3->width == 1600)
svga->hdisp <<= 1;
} else if (s3->card_type == S3_SPEA_MERCURY_P64V) {
if (s3->width == 1280 || s3->width == 1600)
svga->hdisp <<= 1;
}
} else if (s3->card_type == S3_NUMBER9_9FX_771)
svga->hdisp <<= 1;
}
#endif
break;
case 15:
svga->render = svga_render_15bpp_highres;
switch (s3->chip) {
case S3_86C911:
case S3_86C924:
svga->hdisp >>= 1;
svga->dots_per_clock >>= 1;
break;
case S3_86C801:
switch (s3->card_type) {
case S3_PHOENIX_86C801:
svga->hdisp >>= 1;
svga->dots_per_clock >>= 1;
break;
default:
break;
}
break;
case S3_86C805:
switch (s3->card_type) {
case S3_MIROCRYSTAL8S_805:
case S3_MIROCRYSTAL10SD_805:
case S3_PHOENIX_86C805:
case S3_86C805_ONBOARD:
svga->hdisp >>= 1;
svga->dots_per_clock >>= 1;
break;
case S3_SPEA_MIRAGE_86C805:
svga->hdisp >>= 1;
svga->dots_per_clock >>= 1;
switch (s3->width) {
case 800:
case 1024:
if (svga->hdisp == 400) {
/*SPEA specific drivers + its VBE RAM BIOS...*/
svga->hdisp <<= 1;
svga->dots_per_clock <<= 1;
}
break;
default:
break;
}
break;
default:
break;
}
break;
case S3_86C928:
switch (s3->card_type) {
case S3_METHEUS_86C928:
if (!s3->color_16bit) {
svga->hdisp <<= 1;
svga->dots_per_clock <<= 1;
}
switch (svga->hdisp) { /*This might be a driver issue*/
case 800:
s3->width = 1024;
break;
case 1280:
s3->width = 2048;
break;
default:
break;
}
break;
default:
break;
}
break;
case S3_86C928PCI:
switch (s3->card_type) {
case S3_SPEA_MERCURY_LITE_PCI:
switch (s3->width) {
case 640:
svga->hdisp >>= 1;
svga->dots_per_clock >>= 1;
break;
default:
break;
}
break;
default:
break;
}
break;
case S3_VISION864:
svga->hdisp >>= 1;
svga->dots_per_clock >>= 1;
break;
case S3_VISION964:
switch (s3->card_type) {
case S3_ELSAWIN2KPROX_964:
switch (s3->width) {
case 1280:
case 1600:
svga->hdisp <<= 1;
svga->dots_per_clock <<= 1;
break;
default:
break;
}
break;
default:
break;
}
break;
case S3_VISION868:
switch (s3->card_type) {
case S3_PHOENIX_VISION868:
case S3_NUMBER9_9FX_531:
svga->hdisp >>= 1;
svga->dots_per_clock >>= 1;
break;
default:
break;
}
break;
case S3_VISION968:
switch (s3->card_type) {
case S3_MIROVIDEO40SV_ERGO_968:
if (svga->hdisp == 832)
svga->hdisp -= 32;
break;
case S3_DIAMOND_STEALTH64_968:
case S3_NUMBER9_9FX_771:
case S3_PHOENIX_VISION968:
case S3_SPEA_MERCURY_P64V:
svga->hdisp <<= 1;
svga->dots_per_clock <<= 1;
/* TODO: Is this still needed? */
if (svga->hdisp == 832)
svga->hdisp -= 32;
break;
case S3_ELSAWIN2KPROX:
switch (s3->width) {
case 1280:
case 1600:
svga->hdisp <<= 1;
svga->dots_per_clock <<= 1;
break;
default:
break;
}
break;
default:
break;
}
break;
case S3_TRIO64:
case S3_TRIO32:
svga->hdisp >>= 1;
svga->dots_per_clock >>= 1;
break;
default:
break;
}
#ifdef OLD_CODE_REFERENCE
if ((s3->chip != S3_VISION964) && (s3->card_type != S3_SPEA_MIRAGE_86C801) && (s3->card_type != S3_SPEA_MIRAGE_86C805)) {
if (s3->chip == S3_86C928)
svga->hdisp <<= 1;
else if (s3->chip != S3_VISION968)
svga->hdisp >>= 1;
}
if ((s3->chip != S3_VISION868) && (s3->chip != S3_TRIO32) && (s3->chip != S3_TRIO64) && (s3->chip != S3_VISION964)) {
if (s3->width == 1280 || s3->width == 1600)
svga->hdisp <<= 1;
else if (s3->card_type == S3_NUMBER9_9FX_771)
svga->hdisp <<= 1;
}
if (s3->card_type == S3_MIROVIDEO40SV_ERGO_968 || s3->card_type == S3_PHOENIX_VISION968 || s3->card_type == S3_SPEA_MERCURY_P64V) {
if (svga->hdisp == (1408 * 2))
svga->hdisp >>= 1;
else
svga->hdisp = s3->width;
}
if (s3->card_type == S3_SPEA_MIRAGE_86C801 || s3->card_type == S3_SPEA_MIRAGE_86C805 || s3->card_type == S3_SPEA_MERCURY_LITE_PCI)
svga->hdisp = s3->width;
#endif
break;
case 16:
svga->render = svga_render_16bpp_highres;
switch (s3->chip) {
case S3_86C911:
case S3_86C924:
svga->hdisp >>= 1;
svga->dots_per_clock >>= 1;
break;
case S3_86C801:
switch (s3->card_type) {
case S3_PHOENIX_86C801:
svga->hdisp >>= 1;
svga->dots_per_clock >>= 1;
break;
default:
break;
}
break;
case S3_86C805:
switch (s3->card_type) {
case S3_MIROCRYSTAL8S_805:
case S3_MIROCRYSTAL10SD_805:
case S3_PHOENIX_86C805:
case S3_86C805_ONBOARD:
svga->hdisp >>= 1;
svga->dots_per_clock >>= 1;
break;
case S3_SPEA_MIRAGE_86C805:
svga->hdisp >>= 1;
switch (s3->width) {
case 800:
case 1024:
if (svga->hdisp == 400) {
/*SPEA specific drivers + its VBE RAM BIOS...*/
svga->hdisp <<= 1;
svga->dots_per_clock <<= 1;
}
break;
default:
break;
}
break;
default:
break;
}
break;
case S3_86C928:
switch (s3->card_type) {
case S3_METHEUS_86C928:
svga->hdisp <<= 1;
svga->dots_per_clock <<= 1;
switch (svga->hdisp) { /*This might be a driver issue*/
case 800:
s3->width = 1024;
break;
case 1280:
s3->width = 2048;
break;
default:
break;
}
break;
default:
break;
}
break;
case S3_86C928PCI:
switch (s3->card_type) {
case S3_SPEA_MERCURY_LITE_PCI:
switch (s3->width) {
case 640:
svga->hdisp >>= 1;
svga->dots_per_clock >>= 1;
break;
default:
break;
}
break;
default:
break;
}
break;
case S3_VISION864:
svga->hdisp >>= 1;
svga->dots_per_clock >>= 1;
break;
case S3_VISION868:
switch (s3->card_type) {
case S3_PHOENIX_VISION868:
case S3_NUMBER9_9FX_531:
svga->hdisp >>= 1;
svga->dots_per_clock >>= 1;
break;
default:
break;
}
break;
case S3_VISION964:
switch (s3->card_type) {
case S3_ELSAWIN2KPROX_964:
switch (s3->width) {
case 1280:
case 1600:
svga->hdisp <<= 1;
svga->dots_per_clock <<= 1;
break;
default:
break;
}
break;
default:
break;
}
break;
case S3_VISION968:
switch (s3->card_type) {
case S3_MIROVIDEO40SV_ERGO_968:
if (svga->hdisp == 832)
svga->hdisp -= 32;
break;
case S3_DIAMOND_STEALTH64_968:
case S3_NUMBER9_9FX_771:
case S3_PHOENIX_VISION968:
case S3_SPEA_MERCURY_P64V:
svga->hdisp <<= 1;
svga->dots_per_clock <<= 1;
/* TODO: Is this still needed? */
if (svga->hdisp == 832)
svga->hdisp -= 32;
break;
case S3_ELSAWIN2KPROX:
switch (s3->width) {
case 1280:
case 1600:
svga->hdisp <<= 1;
svga->dots_per_clock <<= 1;
break;
default:
break;
}
break;
default:
break;
}
break;
case S3_TRIO64:
case S3_TRIO32:
svga->hdisp >>= 1;
svga->dots_per_clock >>= 1;
break;
default:
break;
}
#ifdef OLD_CODE_REFERENCE
if ((s3->card_type == S3_ELSAWIN2KPROX_964) || (s3->card_type == S3_ELSAWIN2KPROX)) {
if (s3->width == 1280 || s3->width == 1600)
svga->hdisp <<= 1;
}
if ((s3->chip != S3_VISION964) && (s3->card_type != S3_SPEA_MIRAGE_86C801) && (s3->card_type != S3_SPEA_MIRAGE_86C805)) {
if (s3->chip == S3_86C928)
svga->hdisp <<= 1;
else if (s3->chip != S3_VISION968)
svga->hdisp >>= 1;
} else if ((s3->card_type == S3_SPEA_MIRAGE_86C801) || (s3->card_type == S3_SPEA_MIRAGE_86C805))
svga->hdisp >>= 1;
if ((s3->chip != S3_VISION868) && (s3->chip != S3_TRIO32) && (s3->chip != S3_TRIO64) && (s3->chip != S3_VISION964)) {
if (s3->width == 1280 || s3->width == 1600)
svga->hdisp <<= 1;
else if (s3->card_type == S3_NUMBER9_9FX_771)
svga->hdisp <<= 1;
}
if (s3->card_type == S3_MIROVIDEO40SV_ERGO_968 || s3->card_type == S3_PHOENIX_VISION968 || s3->card_type == S3_SPEA_MERCURY_P64V) {
if (svga->hdisp == (1408 << 1))
svga->hdisp >>= 1;
else
svga->hdisp = s3->width;
}
if (s3->card_type == S3_SPEA_MIRAGE_86C801 || s3->card_type == S3_SPEA_MIRAGE_86C805 || s3->card_type == S3_SPEA_MERCURY_LITE_PCI)
svga->hdisp = s3->width;
#endif
break;
case 24:
svga->render = svga_render_24bpp_highres;
switch (s3->chip) {
case S3_86C924:
switch (s3->card_type) {
case S3_AMI_86C924:
svga->hdisp = (svga->hdisp << 1) / 3;
svga->dots_per_clock = (svga->dots_per_clock << 1) / 3;
/* TODO: Is this still needed? */
if (svga->hdisp == 645)
svga->hdisp -= 5;
break;
default:
break;
}
break;
case S3_86C801:
switch (s3->card_type) {
case S3_PHOENIX_86C801:
case S3_SPEA_MIRAGE_86C801:
svga->hdisp = (svga->hdisp << 1) / 3;
svga->dots_per_clock = (svga->dots_per_clock << 1) / 3;
break;
default:
break;
}
break;
case S3_86C805:
switch (s3->card_type) {
case S3_MIROCRYSTAL8S_805:
case S3_MIROCRYSTAL10SD_805:
case S3_PHOENIX_86C805:
case S3_SPEA_MIRAGE_86C805:
case S3_86C805_ONBOARD:
svga->hdisp = (svga->hdisp << 1) / 3;
svga->dots_per_clock = (svga->dots_per_clock << 1) / 3;
break;
default:
break;
}
break;
case S3_86C928PCI:
switch (s3->card_type) {
case S3_SPEA_MERCURY_LITE_PCI:
svga->hdisp = (svga->hdisp << 1) / 3;
svga->dots_per_clock = (svga->dots_per_clock << 1) / 3;
break;
default:
break;
}
break;
case S3_VISION864:
svga->hdisp = (svga->hdisp << 1) / 3;
svga->dots_per_clock = (svga->dots_per_clock << 1) / 3;
break;
case S3_VISION968:
switch (s3->card_type) {
case S3_MIROVIDEO40SV_ERGO_968:
svga->hdisp = (svga->hdisp / 3) << 2;
svga->dots_per_clock = (svga->hdisp / 3) << 2;
break;
default:
break;
}
break;
case S3_TRIO64:
case S3_TRIO32:
svga->hdisp /= 3;
svga->dots_per_clock /= 3;
break;
default:
break;
}
#ifdef OLD_CODE_REFERENCE
if (s3->chip != S3_VISION968) {
if (s3->chip != S3_86C928 && s3->chip != S3_86C801 && s3->chip != S3_86C805)
svga->hdisp /= 3;
else
svga->hdisp = (svga->hdisp * 2) / 3;
if (s3->card_type == S3_SPEA_MERCURY_LITE_PCI) {
if (s3->width == 2048) {
switch (svga->dispend) {
case 480:
svga->hdisp = 640;
break;
default:
break;
}
}
} else if (s3->chip == S3_86C924) {
if (svga->dispend == 480)
svga->hdisp = 640;
}
} else {
if ((s3->card_type == S3_MIROVIDEO40SV_ERGO_968) ||
(s3->card_type == S3_PHOENIX_VISION968) || (s3->card_type == S3_SPEA_MERCURY_P64V))
svga->hdisp = s3->width;
}
#endif
break;
case 32:
svga->render = svga_render_32bpp_highres;
switch (s3->chip) {
case S3_VISION864:
svga->hdisp >>= 2;
svga->dots_per_clock >>= 2;
break;
case S3_VISION868:
switch (s3->card_type) {
case S3_PHOENIX_VISION868:
case S3_NUMBER9_9FX_531:
svga->hdisp >>= 1;
svga->dots_per_clock >>= 1;
break;
default:
break;
}
break;
case S3_VISION964:
switch (s3->card_type) {
case S3_MIROCRYSTAL20SV_964:
switch (s3->width) {
case 800:
case 1024:
svga->hdisp >>= 1;
svga->dots_per_clock >>= 1;
break;
default:
break;
}
break;
case S3_ELSAWIN2KPROX_964:
switch (s3->width) {
case 1280:
case 1600:
svga->hdisp <<= 1;
svga->dots_per_clock <<= 1;
break;
default:
break;
}
break;
default:
break;
}
break;
case S3_VISION968:
switch (s3->card_type) {
case S3_MIROVIDEO40SV_ERGO_968:
if (svga->hdisp == 832)
svga->hdisp -= 32;
break;
case S3_DIAMOND_STEALTH64_968:
case S3_NUMBER9_9FX_771:
case S3_PHOENIX_VISION968:
case S3_SPEA_MERCURY_P64V:
svga->hdisp <<= 1;
svga->dots_per_clock <<= 1;
/* TODO: Is this still needed? */
if (svga->hdisp == 832)
svga->hdisp -= 32;
break;
case S3_ELSAWIN2KPROX:
switch (s3->width) {
case 1280:
case 1600:
svga->hdisp <<= 1;
svga->dots_per_clock <<= 1;
break;
default:
break;
}
break;
default:
break;
}
break;
default:
break;
}
#ifdef OLD_CODE_REFERENCE
if ((s3->chip < S3_TRIO32) && (s3->chip != S3_VISION964) && (s3->chip != S3_VISION968) && (s3->chip != S3_86C928)) {
if (s3->chip == S3_VISION868)
svga->hdisp >>= 1;
else
svga->hdisp >>= 2;
}
if (s3->width == 1280 || s3->width == 1600 || (s3->card_type == S3_SPEA_MERCURY_P64V || s3->card_type == S3_NUMBER9_9FX_771))
svga->hdisp <<= 1;
if (s3->card_type == S3_NUMBER9_9FX_771) {
if (svga->hdisp == 832)
svga->hdisp -= 32;
}
if (s3->card_type == S3_MIROVIDEO40SV_ERGO_968 || s3->card_type == S3_MIROCRYSTAL20SV_964 || s3->card_type == S3_MIROCRYSTAL20SD_864 || s3->card_type == S3_PHOENIX_VISION968 || s3->card_type == S3_SPEA_MERCURY_P64V) {
svga->hdisp = s3->width;
if (s3->card_type == S3_MIROCRYSTAL20SD_864 || s3->card_type == S3_MIROCRYSTAL20SV_964) {
if (s3->width == 800 || s3->width == 1024 || s3->width == 1600) {
switch (svga->dispend) {
case 400:
case 480:
svga->hdisp = 640;
break;
case 576:
if (s3->width == 1600)
s3->width = 800;
svga->hdisp = 768;
break;
case 600:
if (s3->width == 1600)
s3->width = 800;
svga->hdisp = 800;
break;
default:
break;
}
}
}
}
#endif
break;
default:
break;
}
} else {
svga->vram_display_mask = (svga->crtc[0x32] & 0x40) ? 0x3ffff : s3->vram_mask;
if (!svga->scrblank && (svga->crtc[0x17] & 0x80) && svga->attr_palette_enable) {
if ((svga->gdcreg[6] & 1) || (svga->attrregs[0x10] & 1)) {
if (svga->crtc[0x31] & 0x08) {
svga->vram_display_mask = s3->vram_mask;
if (svga->bpp == 8) {
if (!(svga->crtc[0x5e] & 0x04))
svga->vblankstart = svga->dispend; /*Applies only to Enhanced modes*/
/*Enhanced 4bpp mode, just like the 8bpp mode per the spec. */
svga->render = svga_render_8bpp_highres;
svga->rowoffset <<= 1;
}
}
}
}
}
if ((s3->chip == S3_TRIO32) || (s3->chip == S3_TRIO64) || (s3->chip == S3_VISION864))
svga->hoverride = 1;
else
svga->hoverride = 0;
if (svga->render == svga_render_2bpp_lowres)
svga->render = svga_render_2bpp_s3_lowres;
else if (svga->render == svga_render_2bpp_highres)
svga->render = svga_render_2bpp_s3_highres;
}
static void
s3_trio64v_recalctimings(svga_t *svga)
{
s3_t *s3 = (s3_t *) svga->priv;
int clk_sel = (svga->miscout >> 2) & 3;
if (!svga->scrblank && svga->attr_palette_enable && (svga->crtc[0x43] & 0x80)) {
/* TODO: In case of bug reports, disable 9-dots-wide character clocks in graphics modes. */
svga->dots_per_clock = ((svga->seqregs[1] & 1) ? 16 : 18);
}
if ((svga->crtc[0x33] & 0x20) ||((svga->crtc[0x67] & 0xc) == 0xc)) {
/* In this mode, the dots per clock are always 8 or 16, never 9 or 18. */
if (!svga->scrblank && svga->attr_palette_enable)
svga->dots_per_clock = (svga->seqregs[1] & 8) ? 16 : 8;
}
svga->hdisp = svga->hdisp_old;
if (svga->crtc[0x5d] & 0x01)
svga->htotal |= 0x100;
if (svga->crtc[0x5d] & 0x02) {
svga->hdisp_time |= 0x100;
svga->hdisp |= 0x100 * svga->dots_per_clock;
}
if (svga->crtc[0x5e] & 0x01)
svga->vtotal |= 0x400;
if (svga->crtc[0x5e] & 0x02)
svga->dispend |= 0x400;
if (svga->crtc[0x5e] & 0x04)
svga->vblankstart |= 0x400;
if (svga->crtc[0x5e] & 0x10)
svga->vsyncstart |= 0x400;
if (svga->crtc[0x5e] & 0x40)
svga->split |= 0x400;
svga->interlace = svga->crtc[0x42] & 0x20;
svga->clock = (cpuclock * (double) (1ULL << 32)) / svga->getclock(clk_sel, svga->clock_gen);
switch (svga->crtc[0x50] & 0xc1) {
case 0x00:
s3->width = (svga->crtc[0x31] & 2) ? 2048 : 1024;
break;
case 0x01:
s3->width = 1152;
break;
case 0x40:
s3->width = 640;
break;
case 0x80:
s3->width = (s3->accel.advfunc_cntl & 4) ? 1600 : 800;
break;
case 0x81:
s3->width = 1600;
break;
case 0xc0:
s3->width = 1280;
break;
default:
break;
}
if ((svga->crtc[0x33] & 0x20) || ((svga->crtc[0x67] & 0xc) == 0xc)) {
/* The S3 version of the Cirrus' special blanking mode, with identical behavior. */
svga->hblankstart = (((svga->crtc[0x5d] & 0x02) >> 1) << 8) + svga->crtc[1]/* +
((svga->crtc[3] >> 5) & 3)*/;
svga->hblank_end_val = svga->htotal - 1 /* + ((svga->crtc[3] >> 5) & 3)*/;
svga->monitor->mon_overscan_y = 0;
svga->monitor->mon_overscan_x = 0;
/* Also make sure vertical blanking starts on display end. */
svga->vblankstart = svga->dispend;
} else {
svga->hblankstart = (((svga->crtc[0x5d] & 0x04) >> 2) << 8) + svga->crtc[2];
/* NOTE: The S3 Trio64V+ datasheet says this is bit 7, but then where is bit 6?
The datasheets for the pre-Trio64V+ cards say +64, which implies bit 6,
and, contrary to VGADOC, it also exists on Trio32, Trio64, Vision868,
and Vision968. */
svga->hblank_end_val = (svga->crtc[3] & 0x1f) | (((svga->crtc[5] & 0x80) >> 7) << 5) |
(((svga->crtc[0x5d] & 0x08) >> 3) << 6);
svga->hblank_end_mask = 0x7f;
}
if ((svga->crtc[0x67] & 0xc) != 0xc) /*VGA mode*/
{
svga->ma_latch |= (s3->ma_ext << 16);
if (svga->crtc[0x51] & 0x30)
svga->rowoffset |= (svga->crtc[0x51] & 0x30) << 4;
else if (svga->crtc[0x43] & 0x04)
svga->rowoffset |= 0x100;
if (!svga->rowoffset)
svga->rowoffset = 256;
svga->lowres = (!!(svga->attrregs[0x10] & 0x40) && !(svga->crtc[0x3a] & 0x10));
if ((svga->crtc[0x3a] & 0x10) && !svga->lowres) {
svga->vram_display_mask = s3->vram_mask;
switch (svga->bpp) {
case 8:
svga->render = svga_render_8bpp_highres;
break;
case 15:
svga->render = svga_render_15bpp_highres;
svga->hdisp >>= 1;
svga->dots_per_clock >>= 1;
break;
case 16:
svga->render = svga_render_16bpp_highres;
svga->hdisp >>= 1;
svga->dots_per_clock >>= 1;
break;
case 24:
svga->render = svga_render_24bpp_highres;
svga->hdisp /= 3;
svga->dots_per_clock /= 3;
break;
case 32:
svga->render = svga_render_32bpp_highres;
break;
default:
break;
}
} else
svga->vram_display_mask = (svga->crtc[0x32] & 0x40) ? 0x3ffff : s3->vram_mask;
} else /*Streams mode*/
{
if (s3->streams.buffer_ctrl & 1)
svga->ma_latch = s3->streams.pri_fb1 >> 2;
else
svga->ma_latch = s3->streams.pri_fb0 >> 2;
svga->hdisp = s3->streams.pri_w + 1;
if (s3->streams.pri_h < svga->dispend)
svga->dispend = s3->streams.pri_h;
svga->overlay.x = s3->streams.sec_x - s3->streams.pri_x;
svga->overlay.y = s3->streams.sec_y - s3->streams.pri_y;
svga->overlay.cur_ysize = s3->streams.sec_h;
if (s3->streams.buffer_ctrl & 2)
svga->overlay.addr = s3->streams.sec_fb1;
else
svga->overlay.addr = s3->streams.sec_fb0;
svga->overlay.ena = (svga->overlay.x >= 0);
svga->overlay.v_acc = s3->streams.dda_vert_accumulator;
svga->rowoffset = s3->streams.pri_stride >> 3;
svga->vram_display_mask = s3->vram_mask;
switch ((s3->streams.pri_ctrl >> 24) & 0x7) {
case 0: /*RGB-8 (CLUT)*/
svga->render = svga_render_8bpp_highres;
break;
case 3: /*KRGB-16 (1.5.5.5)*/
svga->multiplier = 0.5;
svga->render = svga_render_15bpp_highres;
break;
case 5: /*RGB-16 (5.6.5)*/
svga->multiplier = 0.5;
svga->render = svga_render_16bpp_highres;
break;
case 6: /*RGB-24 (8.8.8)*/
svga->render = svga_render_24bpp_highres;
break;
case 7: /*XRGB-32 (X.8.8.8)*/
svga->render = svga_render_32bpp_highres;
break;
default:
break;
}
}
svga->hoverride = 1;
if (svga->render == svga_render_2bpp_lowres)
svga->render = svga_render_2bpp_s3_lowres;
else if (svga->render == svga_render_2bpp_highres)
svga->render = svga_render_2bpp_s3_highres;
}
static void
s3_updatemapping(s3_t *s3)
{
svga_t *svga = &s3->svga;
if (s3->pci && !(s3->pci_regs[PCI_REG_COMMAND] & PCI_COMMAND_MEM)) {
mem_mapping_disable(&svga->mapping);
mem_mapping_disable(&s3->linear_mapping);
mem_mapping_disable(&s3->mmio_mapping);
mem_mapping_disable(&s3->new_mmio_mapping);
return;
}
/*Banked framebuffer*/
if (svga->crtc[0x31] & 0x08) /*Enhanced mode mappings*/
{
s3_log("Enhanced Mode Mapping.\n");
/* Enhanced mode forces 64kb at 0xa0000*/
mem_mapping_set_addr(&svga->mapping, 0xa0000, 0x10000);
svga->banked_mask = 0xffff;
} else
switch (svga->gdcreg[6] & 0xc) { /*VGA mapping*/
case 0x0: /*128k at A0000*/
mem_mapping_set_addr(&svga->mapping, 0xa0000, 0x20000);
svga->banked_mask = 0xffff;
break;
case 0x4: /*64k at A0000*/
mem_mapping_set_addr(&svga->mapping, 0xa0000, 0x10000);
svga->banked_mask = 0xffff;
break;
case 0x8: /*32k at B0000*/
mem_mapping_set_addr(&svga->mapping, 0xb0000, 0x08000);
svga->banked_mask = 0x7fff;
break;
case 0xC: /*32k at B8000*/
mem_mapping_set_addr(&svga->mapping, 0xb8000, 0x08000);
svga->banked_mask = 0x7fff;
break;
default:
break;
}
if (s3->chip >= S3_86C928) {
s3->linear_base = (svga->crtc[0x5a] << 16) | (svga->crtc[0x59] << 24);
if (s3->chip >= S3_86C928 && s3->chip <= S3_86C805) {
if (s3->vlb)
s3->linear_base &= 0x03ffffff;
else
s3->linear_base &= 0x00ffffff;
}
s3_log("LinearBase=%x, crtc58bits=%x.\n", s3->linear_base, svga->crtc[0x58] & 0x13);
if ((svga->crtc[0x58] & 0x10) || (s3->accel.advfunc_cntl & 0x10)) {
/*Linear framebuffer*/
mem_mapping_disable(&svga->mapping);
switch (svga->crtc[0x58] & 3) {
case 0: /*64k*/
s3->linear_size = 0x10000;
break;
case 1: /*1mb*/
s3->linear_size = 0x100000;
break;
case 2: /*2mb*/
s3->linear_size = 0x200000;
break;
case 3: /*8mb*/
switch (s3->chip) { /* Not on video cards that don't support 4MB*/
case S3_TRIO64:
case S3_TRIO64V:
case S3_TRIO64V2:
case S3_86C928:
case S3_86C928PCI:
s3->linear_size = 0x400000;
break;
default:
s3->linear_size = 0x800000;
break;
}
break;
default:
break;
}
s3->linear_base &= ~(s3->linear_size - 1);
if (s3->linear_base == 0xa0000) {
mem_mapping_disable(&s3->linear_mapping);
if (!(svga->crtc[0x53] & 0x10)) {
mem_mapping_set_addr(&svga->mapping, s3->linear_base, 0x10000);
svga->banked_mask = 0xffff;
}
} else {
if (s3->chip >= S3_TRIO64V)
s3->linear_base &= 0xfc000000;
else if ((s3->chip == S3_VISION968) || (s3->chip == S3_VISION868))
s3->linear_base &= 0xfe000000;
s3_log("LinearBase update=%x, size=%x.\n", s3->linear_base, s3->linear_size);
if (s3->linear_base)
mem_mapping_set_addr(&s3->linear_mapping, s3->linear_base, s3->linear_size);
else
mem_mapping_disable(&s3->linear_mapping);
}
svga->fb_only = 1;
} else {
svga->fb_only = 0;
mem_mapping_disable(&s3->linear_mapping);
}
/* Memory mapped I/O. */
if ((svga->crtc[0x53] & 0x10) || (s3->accel.advfunc_cntl & 0x20)) {
mem_mapping_disable(&svga->mapping);
if (s3->chip >= S3_TRIO64V) {
if (svga->crtc[0x53] & 0x20)
mem_mapping_set_addr(&s3->mmio_mapping, 0xb8000, 0x8000);
else
mem_mapping_set_addr(&s3->mmio_mapping, 0xa0000, 0x10000);
}
mem_mapping_enable(&s3->mmio_mapping);
} else {
mem_mapping_disable(&s3->mmio_mapping);
}
/* New MMIO. */
if (svga->crtc[0x53] & 0x08) {
if (s3->linear_base)
mem_mapping_set_addr(&s3->new_mmio_mapping, s3->linear_base + 0x1000000, 0x20000);
else
mem_mapping_disable(&s3->new_mmio_mapping);
}
else
mem_mapping_disable(&s3->new_mmio_mapping);
}
}
static float
s3_trio64_getclock(int clock, void *priv)
{
const s3_t *s3 = (s3_t *) priv;
const svga_t *svga = &s3->svga;
float t;
int m;
int n1;
int n2;
if (clock == 0)
return 25175000.0;
if (clock == 1)
return 28322000.0;
m = svga->seqregs[0x13] + 2;
n1 = (svga->seqregs[0x12] & 0x1f) + 2;
n2 = ((svga->seqregs[0x12] >> 5) & 0x07);
t = (14318184.0 * ((float) m / (float) n1)) / (float) (1 << n2);
return t;
}
static void
s3_accel_out(uint16_t port, uint8_t val, void *priv)
{
s3_t *s3 = (s3_t *) priv;
svga_t *svga = &s3->svga;
if (port >= 0x8000) {
if (!s3->enable_8514)
return;
if (s3_enable_fifo(s3))
s3_queue(s3, port, val, FIFO_OUT_BYTE);
else
s3_accel_out_fifo(s3, port, val);
} else {
switch (port) {
case 0x4148:
case 0x42e8:
s3->subsys_stat &= ~val;
s3_update_irqs(s3);
break;
case 0x4149:
case 0x42e9:
s3->subsys_cntl = val;
s3_update_irqs(s3);
break;
case 0x4548:
case 0x46e8:
s3->accel.setup_md = val;
break;
case 0x4948:
case 0x4ae8:
s3->accel.advfunc_cntl = val;
if ((s3->chip > S3_86C805) && ((svga->crtc[0x50] & 0xc1) == 0x80)) {
s3->width = (val & 4) ? 1600 : 800;
svga->fullchange = svga->monitor->mon_changeframecount;
svga_recalctimings(svga);
} else if (s3->chip <= S3_86C805) {
svga->fullchange = svga->monitor->mon_changeframecount;
svga_recalctimings(svga);
}
s3_updatemapping(s3);
break;
default:
break;
}
}
}
static void
s3_accel_out_w(uint16_t port, uint16_t val, void *priv)
{
s3_t *s3 = (s3_t *) priv;
if (!s3->enable_8514)
return;
if (s3_enable_fifo(s3))
s3_queue(s3, port, val, FIFO_OUT_WORD);
else
s3_accel_out_fifo_w(s3, port, val);
}
static void
s3_accel_out_l(uint16_t port, uint32_t val, void *priv)
{
s3_t *s3 = (s3_t *) priv;
if (!s3->enable_8514)
return;
if (s3_enable_fifo(s3))
s3_queue(s3, port, val, FIFO_OUT_DWORD);
else
s3_accel_out_fifo_l(s3, port, val);
}
static uint8_t
s3_accel_in(uint16_t port, void *priv)
{
s3_t *s3 = (s3_t *) priv;
svga_t *svga = &s3->svga;
int temp;
uint8_t temp2;
if (!s3->enable_8514)
return 0xff;
switch (port) {
case 0x4148:
case 0x42e8:
return s3->subsys_stat;
case 0x4149:
case 0x42e9:
return s3->subsys_cntl;
case 0x8148:
case 0x82e8:
if (s3_enable_fifo(s3))
s3_wait_fifo_idle(s3);
return s3->accel.cur_y & 0xff;
case 0x8149:
case 0x82e9:
if (s3_enable_fifo(s3))
s3_wait_fifo_idle(s3);
return s3->accel.cur_y >> 8;
case 0x8548:
case 0x86e8:
if (s3_enable_fifo(s3))
s3_wait_fifo_idle(s3);
return s3->accel.cur_x & 0xff;
case 0x8549:
case 0x86e9:
if (s3_enable_fifo(s3))
s3_wait_fifo_idle(s3);
return s3->accel.cur_x >> 8;
case 0x8948:
case 0x8ae8:
if (s3->chip >= S3_86C928) {
if (s3_enable_fifo(s3))
s3_wait_fifo_idle(s3);
return s3->accel.desty_axstp & 0xff;
}
break;
case 0x8949:
case 0x8ae9:
if (s3->chip >= S3_86C928) {
if (s3_enable_fifo(s3))
s3_wait_fifo_idle(s3);
return s3->accel.desty_axstp >> 8;
}
break;
case 0x8d48:
case 0x8ee8:
if (s3->chip >= S3_86C928) {
if (s3_enable_fifo(s3))
s3_wait_fifo_idle(s3);
return s3->accel.destx_distp & 0xff;
}
break;
case 0x8d49:
case 0x8ee9:
if (s3->chip >= S3_86C928) {
if (s3_enable_fifo(s3))
s3_wait_fifo_idle(s3);
return s3->accel.destx_distp >> 8;
}
break;
case 0x9148:
case 0x92e8:
if (s3_enable_fifo(s3))
s3_wait_fifo_idle(s3);
return s3->accel.err_term & 0xff;
case 0x9149:
case 0x92e9:
if (s3_enable_fifo(s3))
s3_wait_fifo_idle(s3);
return s3->accel.err_term >> 8;
case 0x9548:
case 0x96e8:
if (s3->chip >= S3_86C928) {
return s3->accel.maj_axis_pcnt & 0xff;
}
break;
case 0x9549:
case 0x96e9:
if (s3->chip >= S3_86C928) {
if (s3_enable_fifo(s3))
s3_wait_fifo_idle(s3);
return s3->accel.maj_axis_pcnt >> 8;
}
break;
case 0x8118:
case 0x9948:
case 0x9ae8:
temp = 0; /* FIFO empty */
if (s3_enable_fifo(s3)) {
if (!s3->blitter_busy)
wake_fifo_thread(s3);
if (FIFO_FULL)
temp = 0xff;
}
return temp;
case 0x8119:
case 0x9949:
case 0x9ae9:
temp = 0;
if (s3_enable_fifo(s3)) {
if (!s3->blitter_busy)
wake_fifo_thread(s3);
if (!FIFO_EMPTY || s3->force_busy)
temp |= 0x02; /*Hardware busy*/
else
temp |= 0x04; /*FIFO empty*/
s3->force_busy = 0;
if (s3->chip >= S3_VISION964) {
if (FIFO_FULL)
temp |= 0xf8; /*FIFO full*/
}
if (s3->data_available) {
temp |= 0x01; /*Read Data available*/
s3->data_available = 0;
}
} else {
if (s3->force_busy)
temp |= 0x02; /*Hardware busy*/
else {
switch (s3->accel.cmd >> 13) { /*Some drivers may not set FIFO on but may still turn on FIFO empty bits!*/
case 0:
if (!s3->accel.ssv_len)
temp |= 0x04;
break;
case 1:
if (!s3->accel.sy)
temp |= 0x04;
break;
case 2:
case 6:
case 7:
if (s3->accel.sy < 0)
temp |= 0x04;
break;
default:
break;
}
}
s3->force_busy = 0;
if (s3->data_available) {
temp |= 0x01; /*Read Data available*/
s3->data_available = 0;
}
}
s3_log("FIFO Status Temp=%02x.\n", temp);
return temp;
case 0x9d48:
case 0x9ee8:
if (s3->chip >= S3_86C928) {
if (s3_enable_fifo(s3))
s3_wait_fifo_idle(s3);
return s3->accel.short_stroke & 0xff;
}
break;
case 0x9d49:
case 0x9ee9:
if (s3->chip >= S3_86C928) {
if (s3_enable_fifo(s3))
s3_wait_fifo_idle(s3);
return s3->accel.short_stroke >> 8;
}
break;
case 0xa148:
case 0xa2e8:
if (s3->chip >= S3_86C928) {
if (s3_enable_fifo(s3))
s3_wait_fifo_idle(s3);
if ((s3->bpp == 3) && (s3->accel.multifunc[0xe] & 0x10) && !(s3->accel.multifunc[0xe] & 0x200))
temp2 = s3->accel.bkgd_color >> 16;
else
temp2 = s3->accel.bkgd_color & 0xff;
return temp2;
}
break;
case 0xa149:
case 0xa2e9:
if (s3->chip >= S3_86C928) {
if (s3_enable_fifo(s3))
s3_wait_fifo_idle(s3);
if ((s3->bpp == 3) && (s3->accel.multifunc[0xe] & 0x10) && !(s3->accel.multifunc[0xe] & 0x200))
temp2 = s3->accel.bkgd_color >> 24;
else
temp2 = s3->accel.bkgd_color >> 8;
if (!(s3->accel.multifunc[0xe] & 0x200))
s3->accel.multifunc[0xe] ^= 0x10;
return temp2;
}
break;
case 0xa14a:
case 0xa2ea:
if (s3_enable_fifo(s3))
s3_wait_fifo_idle(s3);
if ((s3->bpp == 3) && (s3->accel.multifunc[0xe] & 0x10) && !(s3->accel.multifunc[0xe] & 0x200))
temp2 = s3->accel.bkgd_color & 0xff;
else
temp2 = s3->accel.bkgd_color >> 16;
return temp2;
case 0xa14b:
case 0xa2eb:
if (s3_enable_fifo(s3))
s3_wait_fifo_idle(s3);
if ((s3->bpp == 3) && (s3->accel.multifunc[0xe] & 0x10) && !(s3->accel.multifunc[0xe] & 0x200))
temp2 = s3->accel.bkgd_color >> 8;
else
temp2 = s3->accel.bkgd_color >> 24;
if (!(s3->accel.multifunc[0xe] & 0x200))
s3->accel.multifunc[0xe] ^= 0x10;
return temp2;
case 0xa548:
case 0xa6e8:
if (s3->chip >= S3_86C928) {
if (s3_enable_fifo(s3))
s3_wait_fifo_idle(s3);
if ((s3->bpp == 3) && (s3->accel.multifunc[0xe] & 0x10) && !(s3->accel.multifunc[0xe] & 0x200))
temp2 = s3->accel.frgd_color >> 16;
else
temp2 = s3->accel.frgd_color & 0xff;
return temp2;
}
break;
case 0xa549:
case 0xa6e9:
if (s3->chip >= S3_86C928) {
if (s3_enable_fifo(s3))
s3_wait_fifo_idle(s3);
if ((s3->bpp == 3) && (s3->accel.multifunc[0xe] & 0x10) && !(s3->accel.multifunc[0xe] & 0x200))
temp2 = s3->accel.frgd_color >> 24;
else
temp2 = s3->accel.frgd_color >> 8;
if (!(s3->accel.multifunc[0xe] & 0x200))
s3->accel.multifunc[0xe] ^= 0x10;
return temp2;
}
break;
case 0xa54a:
case 0xa6ea:
if (s3_enable_fifo(s3))
s3_wait_fifo_idle(s3);
if ((s3->bpp == 3) && (s3->accel.multifunc[0xe] & 0x10) && !(s3->accel.multifunc[0xe] & 0x200))
temp2 = s3->accel.frgd_color & 0xff;
else
temp2 = s3->accel.frgd_color >> 16;
return temp2;
case 0xa54b:
case 0xa6eb:
if (s3_enable_fifo(s3))
s3_wait_fifo_idle(s3);
if ((s3->bpp == 3) && (s3->accel.multifunc[0xe] & 0x10) && !(s3->accel.multifunc[0xe] & 0x200))
temp2 = s3->accel.frgd_color >> 8;
else
temp2 = s3->accel.frgd_color >> 24;
if (!(s3->accel.multifunc[0xe] & 0x200))
s3->accel.multifunc[0xe] ^= 0x10;
return temp2;
case 0xa948:
case 0xaae8:
if (s3->chip >= S3_86C928) {
if (s3_enable_fifo(s3))
s3_wait_fifo_idle(s3);
if ((s3->bpp == 3) && (s3->accel.multifunc[0xe] & 0x10) && !(s3->accel.multifunc[0xe] & 0x200))
temp2 = s3->accel.wrt_mask >> 16;
else
temp2 = s3->accel.wrt_mask & 0xff;
return temp2;
}
break;
case 0xa949:
case 0xaae9:
if (s3->chip >= S3_86C928) {
if (s3_enable_fifo(s3))
s3_wait_fifo_idle(s3);
if ((s3->bpp == 3) && (s3->accel.multifunc[0xe] & 0x10) && !(s3->accel.multifunc[0xe] & 0x200))
temp2 = s3->accel.wrt_mask >> 24;
else
temp2 = s3->accel.wrt_mask >> 8;
if (!(s3->accel.multifunc[0xe] & 0x200))
s3->accel.multifunc[0xe] ^= 0x10;
return temp2;
}
break;
case 0xa94a:
case 0xaaea:
if (s3_enable_fifo(s3))
s3_wait_fifo_idle(s3);
if ((s3->bpp == 3) && (s3->accel.multifunc[0xe] & 0x10) && !(s3->accel.multifunc[0xe] & 0x200))
temp2 = s3->accel.wrt_mask & 0xff;
else
temp2 = s3->accel.wrt_mask >> 16;
return temp2;
case 0xa94b:
case 0xaaeb:
if (s3_enable_fifo(s3))
s3_wait_fifo_idle(s3);
if ((s3->bpp == 3) && (s3->accel.multifunc[0xe] & 0x10) && !(s3->accel.multifunc[0xe] & 0x200))
temp2 = s3->accel.wrt_mask >> 8;
else
temp2 = s3->accel.wrt_mask >> 24;
if (!(s3->accel.multifunc[0xe] & 0x200))
s3->accel.multifunc[0xe] ^= 0x10;
return temp2;
case 0xad48:
case 0xaee8:
if (s3->chip >= S3_86C928) {
if (s3_enable_fifo(s3))
s3_wait_fifo_idle(s3);
if ((s3->bpp == 3) && (s3->accel.multifunc[0xe] & 0x10) && !(s3->accel.multifunc[0xe] & 0x200))
temp2 = s3->accel.rd_mask >> 16;
else
temp2 = s3->accel.rd_mask & 0xff;
return temp2;
}
break;
case 0xad49:
case 0xaee9:
if (s3->chip >= S3_86C928) {
if (s3_enable_fifo(s3))
s3_wait_fifo_idle(s3);
if ((s3->bpp == 3) && (s3->accel.multifunc[0xe] & 0x10) && !(s3->accel.multifunc[0xe] & 0x200))
temp2 = s3->accel.rd_mask >> 24;
else
temp2 = s3->accel.rd_mask >> 8;
if (!(s3->accel.multifunc[0xe] & 0x200))
s3->accel.multifunc[0xe] ^= 0x10;
return temp2;
}
break;
case 0xad4a:
case 0xaeea:
if (s3_enable_fifo(s3))
s3_wait_fifo_idle(s3);
if ((s3->bpp == 3) && (s3->accel.multifunc[0xe] & 0x10) && !(s3->accel.multifunc[0xe] & 0x200))
temp2 = s3->accel.rd_mask & 0xff;
else
temp2 = s3->accel.rd_mask >> 16;
return temp2;
case 0xad4b:
case 0xaeeb:
if (s3_enable_fifo(s3))
s3_wait_fifo_idle(s3);
if ((s3->bpp == 3) && (s3->accel.multifunc[0xe] & 0x10) && !(s3->accel.multifunc[0xe] & 0x200))
temp2 = s3->accel.rd_mask >> 8;
else
temp2 = s3->accel.rd_mask >> 24;
if (!(s3->accel.multifunc[0xe] & 0x200))
s3->accel.multifunc[0xe] ^= 0x10;
return temp2;
case 0xb148:
case 0xb2e8:
if (s3->chip >= S3_86C928) {
if (s3_enable_fifo(s3))
s3_wait_fifo_idle(s3);
if ((s3->bpp == 3) && (s3->accel.multifunc[0xe] & 0x10) && !(s3->accel.multifunc[0xe] & 0x200))
temp2 = s3->accel.color_cmp >> 16;
else
temp2 = s3->accel.color_cmp & 0xff;
return temp2;
}
break;
case 0xb149:
case 0xb2e9:
if (s3->chip >= S3_86C928) {
if (s3_enable_fifo(s3))
s3_wait_fifo_idle(s3);
if ((s3->bpp == 3) && (s3->accel.multifunc[0xe] & 0x10) && !(s3->accel.multifunc[0xe] & 0x200))
temp2 = s3->accel.color_cmp >> 24;
else
temp2 = s3->accel.color_cmp >> 8;
if (!(s3->accel.multifunc[0xe] & 0x200))
s3->accel.multifunc[0xe] ^= 0x10;
return temp2;
}
break;
case 0xb14a:
case 0xb2ea:
if (s3_enable_fifo(s3))
s3_wait_fifo_idle(s3);
if ((s3->bpp == 3) && (s3->accel.multifunc[0xe] & 0x10) && !(s3->accel.multifunc[0xe] & 0x200))
temp2 = s3->accel.color_cmp & 0xff;
else
temp2 = s3->accel.color_cmp >> 16;
return temp2;
case 0xb14b:
case 0xb2eb:
if (s3_enable_fifo(s3))
s3_wait_fifo_idle(s3);
if ((s3->bpp == 3) && (s3->accel.multifunc[0xe] & 0x10) && !(s3->accel.multifunc[0xe] & 0x200))
temp2 = s3->accel.color_cmp >> 8;
else
temp2 = s3->accel.color_cmp >> 24;
if (!(s3->accel.multifunc[0xe] & 0x200))
s3->accel.multifunc[0xe] ^= 0x10;
return temp2;
case 0xb548:
case 0xb6e8:
if (s3->chip >= S3_86C928) {
if (s3_enable_fifo(s3))
s3_wait_fifo_idle(s3);
return s3->accel.bkgd_mix;
}
break;
case 0xb948:
case 0xbae8:
if (s3->chip >= S3_86C928) {
if (s3_enable_fifo(s3))
s3_wait_fifo_idle(s3);
return s3->accel.frgd_mix;
}
break;
case 0xbd48:
case 0xbee8:
if (s3->chip >= S3_86C928) {
if (s3_enable_fifo(s3))
s3_wait_fifo_idle(s3);
temp = s3->accel.multifunc[0xf] & 0xf;
switch (temp) {
case 0x0:
return s3->accel.multifunc[0x0] & 0xff;
case 0x1:
return s3->accel.multifunc[0x1] & 0xff;
case 0x2:
return s3->accel.multifunc[0x2] & 0xff;
case 0x3:
return s3->accel.multifunc[0x3] & 0xff;
case 0x4:
return s3->accel.multifunc[0x4] & 0xff;
case 0x5:
return s3->accel.multifunc[0xa] & 0xff;
case 0x6:
return s3->accel.multifunc[0xe] & 0xff;
case 0x7:
return s3->accel.cmd & 0xff;
case 0x8:
return s3->accel.subsys_cntl & 0xff;
case 0x9:
return s3->accel.setup_md & 0xff;
case 0xa:
return s3->accel.multifunc[0xd] & 0xff;
default:
break;
}
return 0xff;
}
break;
case 0xbd49:
case 0xbee9:
if (s3->chip >= S3_86C928) {
if (s3_enable_fifo(s3))
s3_wait_fifo_idle(s3);
temp = s3->accel.multifunc[0xf] & 0xf;
s3->accel.multifunc[0xf]++;
switch (temp) {
case 0x0:
return s3->accel.multifunc[0x0] >> 8;
case 0x1:
return s3->accel.multifunc[0x1] >> 8;
case 0x2:
return s3->accel.multifunc[0x2] >> 8;
case 0x3:
return s3->accel.multifunc[0x3] >> 8;
case 0x4:
return s3->accel.multifunc[0x4] >> 8;
case 0x5:
return s3->accel.multifunc[0xa] >> 8;
case 0x6:
return s3->accel.multifunc[0xe] >> 8;
case 0x7:
return s3->accel.cmd >> 8;
case 0x8:
return (s3->accel.subsys_cntl >> 8) & ~0xe000;
case 0x9:
return (s3->accel.setup_md >> 8) & ~0xf000;
case 0xa:
return s3->accel.multifunc[0xd] >> 8;
default:
break;
}
return 0xff;
}
break;
case 0xd148:
case 0xd2e8:
if (s3_enable_fifo(s3))
s3_wait_fifo_idle(s3);
return s3->accel.ropmix & 0xff;
case 0xd149:
case 0xd2e9:
if (s3_enable_fifo(s3))
s3_wait_fifo_idle(s3);
return s3->accel.ropmix >> 8;
case 0xe548:
case 0xe6e8:
if (s3_enable_fifo(s3))
s3_wait_fifo_idle(s3);
if ((s3->bpp == 3) && (s3->accel.multifunc[0xe] & 0x10) && !(s3->accel.multifunc[0xe] & 0x200))
temp2 = s3->accel.pat_bg_color >> 16;
else
temp2 = s3->accel.pat_bg_color & 0xff;
return temp2;
case 0xe549:
case 0xe6e9:
if (s3_enable_fifo(s3))
s3_wait_fifo_idle(s3);
if ((s3->bpp == 3) && (s3->accel.multifunc[0xe] & 0x10) && !(s3->accel.multifunc[0xe] & 0x200))
temp2 = s3->accel.pat_bg_color >> 24;
else
temp2 = s3->accel.pat_bg_color >> 8;
if (!(s3->accel.multifunc[0xe] & 0x200))
s3->accel.multifunc[0xe] ^= 0x10;
return temp2;
case 0xe54a:
case 0xe6ea:
if (s3_enable_fifo(s3))
s3_wait_fifo_idle(s3);
if ((s3->bpp == 3) && (s3->accel.multifunc[0xe] & 0x10) && !(s3->accel.multifunc[0xe] & 0x200))
temp2 = s3->accel.pat_bg_color & 0xff;
else
temp2 = s3->accel.pat_bg_color >> 16;
return temp2;
case 0xe54b:
case 0xe6eb:
if (s3_enable_fifo(s3))
s3_wait_fifo_idle(s3);
if ((s3->bpp == 3) && (s3->accel.multifunc[0xe] & 0x10) && !(s3->accel.multifunc[0xe] & 0x200))
temp2 = s3->accel.pat_bg_color >> 8;
else
temp2 = s3->accel.pat_bg_color >> 24;
if (!(s3->accel.multifunc[0xe] & 0x200))
s3->accel.multifunc[0xe] ^= 0x10;
return temp2;
case 0xe948:
case 0xeae8:
if (s3_enable_fifo(s3))
s3_wait_fifo_idle(s3);
return s3->accel.pat_y & 0xff;
case 0xe949:
case 0xeae9:
if (s3_enable_fifo(s3))
s3_wait_fifo_idle(s3);
return s3->accel.pat_y >> 8;
case 0xe94a:
case 0xeaea:
if (s3_enable_fifo(s3))
s3_wait_fifo_idle(s3);
return s3->accel.pat_x & 0xff;
case 0xe94b:
case 0xeaeb:
if (s3_enable_fifo(s3))
s3_wait_fifo_idle(s3);
return s3->accel.pat_x >> 8;
case 0xed48:
case 0xeee8:
if (s3_enable_fifo(s3))
s3_wait_fifo_idle(s3);
if ((s3->bpp == 3) && (s3->accel.multifunc[0xe] & 0x10) && !(s3->accel.multifunc[0xe] & 0x200))
temp2 = s3->accel.pat_fg_color >> 16;
else
temp2 = s3->accel.pat_fg_color & 0xff;
return temp2;
case 0xed49:
case 0xeee9:
if (s3_enable_fifo(s3))
s3_wait_fifo_idle(s3);
if ((s3->bpp == 3) && (s3->accel.multifunc[0xe] & 0x10) && !(s3->accel.multifunc[0xe] & 0x200))
temp2 = s3->accel.pat_fg_color >> 24;
else
temp2 = s3->accel.pat_fg_color >> 8;
if (!(s3->accel.multifunc[0xe] & 0x200))
s3->accel.multifunc[0xe] ^= 0x10;
return temp2;
case 0xed4a:
case 0xeeea:
if (s3_enable_fifo(s3))
s3_wait_fifo_idle(s3);
if ((s3->bpp == 3) && (s3->accel.multifunc[0xe] & 0x10) && !(s3->accel.multifunc[0xe] & 0x200))
temp2 = s3->accel.pat_fg_color & 0xff;
else
temp2 = s3->accel.pat_fg_color >> 16;
return temp2;
case 0xed4b:
case 0xeeeb:
if (s3_enable_fifo(s3))
s3_wait_fifo_idle(s3);
if ((s3->bpp == 3) && (s3->accel.multifunc[0xe] & 0x10) && !(s3->accel.multifunc[0xe] & 0x200))
temp2 = s3->accel.pat_fg_color >> 8;
else
temp2 = s3->accel.pat_fg_color >> 24;
if (!(s3->accel.multifunc[0xe] & 0x200))
s3->accel.multifunc[0xe] ^= 0x10;
return temp2;
case 0xe148:
case 0xe2e8:
if (!s3_cpu_dest(s3))
break;
READ_PIXTRANS_BYTE_IO(0);
if (s3->accel.cmd & 0x100) {
switch (s3->accel.cmd & 0x600) {
case 0x000:
if (((s3->accel.multifunc[0xa] & 0xc0) == 0x80) || (s3->accel.cmd & 2)) {
if (((s3->accel.frgd_mix & 0x60) != 0x40) || ((s3->accel.bkgd_mix & 0x60) != 0x40))
s3->accel_start(8, 1, s3->accel.pix_trans[0], 0, s3);
else
s3->accel_start(1, 1, 0xffffffff, s3->accel.pix_trans[0], s3);
} else
s3->accel_start(1, 1, 0xffffffff, s3->accel.pix_trans[0], s3);
break;
case 0x200:
if (((s3->accel.multifunc[0xa] & 0xc0) == 0x80) || (s3->accel.cmd & 2)) {
if (((s3->accel.frgd_mix & 0x60) != 0x40) || ((s3->accel.bkgd_mix & 0x60) != 0x40))
s3->accel_start(16, 1, s3->accel.pix_trans[0], 0, s3);
else
s3->accel_start(2, 1, 0xffffffff, s3->accel.pix_trans[0], s3);
} else
s3->accel_start(2, 1, 0xffffffff, s3->accel.pix_trans[0], s3);
break;
default:
break;
}
}
return s3->accel.pix_trans[0];
case 0xe149:
case 0xe2e9:
if (!s3_cpu_dest(s3))
break;
READ_PIXTRANS_BYTE_IO(1);
if (s3->accel.cmd & 0x100) {
switch (s3->accel.cmd & 0x600) {
case 0x000:
if (((s3->accel.multifunc[0xa] & 0xc0) == 0x80) || (s3->accel.cmd & 2)) {
if (((s3->accel.frgd_mix & 0x60) != 0x40) || ((s3->accel.bkgd_mix & 0x60) != 0x40))
s3->accel_start(8, 1, s3->accel.pix_trans[0] | (s3->accel.pix_trans[1] << 8), 0, s3);
else
s3->accel_start(1, 1, 0xffffffff, s3->accel.pix_trans[0] | (s3->accel.pix_trans[1] << 8), s3);
} else
s3->accel_start(1, 1, 0xffffffff, s3->accel.pix_trans[0] | (s3->accel.pix_trans[1] << 8), s3);
break;
case 0x200:
if (((s3->accel.multifunc[0xa] & 0xc0) == 0x80) || (s3->accel.cmd & 2)) {
if (((s3->accel.frgd_mix & 0x60) != 0x40) || ((s3->accel.bkgd_mix & 0x60) != 0x40)) {
if (s3->accel.cmd & 0x1000)
s3->accel_start(16, 1, s3->accel.pix_trans[1] | (s3->accel.pix_trans[0] << 8), 0, s3);
else
s3->accel_start(16, 1, s3->accel.pix_trans[0] | (s3->accel.pix_trans[1] << 8), 0, s3);
} else {
if (s3->accel.cmd & 0x1000)
s3->accel_start(2, 1, 0xffffffff, s3->accel.pix_trans[1] | (s3->accel.pix_trans[0] << 8), s3);
else
s3->accel_start(2, 1, 0xffffffff, s3->accel.pix_trans[0] | (s3->accel.pix_trans[1] << 8), s3);
}
} else {
if (s3->accel.cmd & 0x1000)
s3->accel_start(2, 1, 0xffffffff, s3->accel.pix_trans[1] | (s3->accel.pix_trans[0] << 8), s3);
else
s3->accel_start(2, 1, 0xffffffff, s3->accel.pix_trans[0] | (s3->accel.pix_trans[1] << 8), s3);
}
break;
default:
break;
}
}
return s3->accel.pix_trans[1];
case 0xe14a:
case 0xe2ea:
if (!s3_cpu_dest(s3))
break;
READ_PIXTRANS_BYTE_IO(2);
return s3->accel.pix_trans[2];
case 0xe14b:
case 0xe2eb:
if (!s3_cpu_dest(s3))
break;
READ_PIXTRANS_BYTE_IO(3);
if (s3->accel.cmd & 0x100) {
switch (s3->accel.cmd & 0x600) {
case 0x000:
if (((s3->accel.multifunc[0xa] & 0xc0) == 0x80) || (s3->accel.cmd & 2)) {
if (((s3->accel.frgd_mix & 0x60) != 0x40) || ((s3->accel.bkgd_mix & 0x60) != 0x40))
s3->accel_start(8, 1, s3->accel.pix_trans[0] | (s3->accel.pix_trans[1] << 8) | (s3->accel.pix_trans[2] << 16) | (s3->accel.pix_trans[3] << 24), 0, s3);
else
s3->accel_start(1, 1, 0xffffffff, s3->accel.pix_trans[0] | (s3->accel.pix_trans[1] << 8) | (s3->accel.pix_trans[2] << 16) | (s3->accel.pix_trans[3] << 24), s3);
} else
s3->accel_start(1, 1, 0xffffffff, s3->accel.pix_trans[0] | (s3->accel.pix_trans[1] << 8) | (s3->accel.pix_trans[2] << 16) | (s3->accel.pix_trans[3] << 24), s3);
break;
case 0x200:
if (((s3->accel.multifunc[0xa] & 0xc0) == 0x80) || (s3->accel.cmd & 2)) {
if (((s3->accel.frgd_mix & 0x60) != 0x40) || ((s3->accel.bkgd_mix & 0x60) != 0x40)) {
if (s3->accel.cmd & 0x1000)
s3->accel_start(16, 1, s3->accel.pix_trans[3] | (s3->accel.pix_trans[2] << 8) | (s3->accel.pix_trans[1] << 16) | (s3->accel.pix_trans[0] << 24), 0, s3);
else
s3->accel_start(16, 1, s3->accel.pix_trans[0] | (s3->accel.pix_trans[1] << 8) | (s3->accel.pix_trans[2] << 16) | (s3->accel.pix_trans[3] << 24), 0, s3);
} else {
if (s3->accel.cmd & 0x1000)
s3->accel_start(2, 1, 0xffffffff, s3->accel.pix_trans[3] | (s3->accel.pix_trans[2] << 8) | (s3->accel.pix_trans[1] << 16) | (s3->accel.pix_trans[0] << 24), s3);
else
s3->accel_start(2, 1, 0xffffffff, s3->accel.pix_trans[0] | (s3->accel.pix_trans[1] << 8) | (s3->accel.pix_trans[2] << 16) | (s3->accel.pix_trans[3] << 24), s3);
}
} else {
if (s3->accel.cmd & 0x1000)
s3->accel_start(2, 1, 0xffffffff, s3->accel.pix_trans[3] | (s3->accel.pix_trans[2] << 8) | (s3->accel.pix_trans[1] << 16) | (s3->accel.pix_trans[0] << 24), s3);
else
s3->accel_start(2, 1, 0xffffffff, s3->accel.pix_trans[0] | (s3->accel.pix_trans[1] << 8) | (s3->accel.pix_trans[2] << 16) | (s3->accel.pix_trans[3] << 24), s3);
}
break;
default:
break;
}
}
return s3->accel.pix_trans[3];
case 0xff20:
case 0xff21:
temp = s3->serialport & ~(SERIAL_PORT_SCR | SERIAL_PORT_SDR);
if ((s3->serialport & SERIAL_PORT_SCW) && i2c_gpio_get_scl(s3->i2c))
temp |= SERIAL_PORT_SCR;
if ((s3->serialport & SERIAL_PORT_SDW) && i2c_gpio_get_sda(s3->i2c))
temp |= SERIAL_PORT_SDR;
return temp;
default:
break;
}
return 0xff;
}
static uint16_t
s3_accel_in_w(uint16_t port, void *priv)
{
s3_t *s3 = (s3_t *) priv;
svga_t *svga = &s3->svga;
uint16_t temp = 0x0000;
const uint16_t *vram_w = (uint16_t *) svga->vram;
if (!s3->enable_8514)
return 0xffff;
if (port != 0x9ee8 && port != 0x9d48) {
if (s3_cpu_dest(s3)) {
READ_PIXTRANS_WORD
switch (s3->accel.cmd & 0x600) {
case 0x000:
if (((s3->accel.multifunc[0xa] & 0xc0) == 0x80) || (s3->accel.cmd & 2)) {
if (((s3->accel.frgd_mix & 0x60) != 0x40) || ((s3->accel.bkgd_mix & 0x60) != 0x40)) {
if (s3->accel.cmd & 0x1000)
temp = (temp >> 8) | (temp << 8);
s3->accel_start(8, 1, temp | (temp << 16), 0, s3);
} else
s3->accel_start(1, 1, 0xffffffff, temp | (temp << 16), s3);
} else
s3->accel_start(1, 1, 0xffffffff, temp | (temp << 16), s3);
break;
case 0x200:
if (((s3->accel.multifunc[0xa] & 0xc0) == 0x80) || (s3->accel.cmd & 2)) {
if (((s3->accel.frgd_mix & 0x60) != 0x40) || ((s3->accel.bkgd_mix & 0x60) != 0x40)) {
if (s3->accel.cmd & 0x1000)
temp = (temp >> 8) | (temp << 8);
s3->accel_start(16, 1, temp | (temp << 16), 0, s3);
} else
s3->accel_start(2, 1, 0xffffffff, temp | (temp << 16), s3);
} else {
s3->accel_start(2, 1, 0xffffffff, temp | (temp << 16), s3);
}
break;
default:
break;
}
}
} else {
if (s3_enable_fifo(s3))
s3_wait_fifo_idle(s3);
temp = s3->accel.short_stroke;
}
return temp;
}
static uint32_t
s3_accel_in_l(UNUSED(uint16_t port), void *priv)
{
s3_t *s3 = (s3_t *) priv;
svga_t *svga = &s3->svga;
uint32_t temp = 0x00000000;
const uint16_t *vram_w = (uint16_t *) svga->vram;
if (!s3->enable_8514)
return 0xffffffff;
if (s3_cpu_dest(s3)) {
READ_PIXTRANS_LONG
switch (s3->accel.cmd & 0x600) {
case 0x000:
if (((s3->accel.multifunc[0xa] & 0xc0) == 0x80) || (s3->accel.cmd & 2)) {
if (((s3->accel.frgd_mix & 0x60) != 0x40) || ((s3->accel.bkgd_mix & 0x60) != 0x40)) {
if (s3->accel.cmd & 0x1000)
temp = ((temp & 0xff00ff00) >> 8) | ((temp & 0x00ff00ff) << 8);
s3->accel_start(8, 1, temp, 0, s3);
s3->accel_start(8, 1, temp >> 16, 0, s3);
} else {
s3->accel_start(1, 1, 0xffffffff, temp, s3);
s3->accel_start(1, 1, 0xffffffff, temp >> 16, s3);
}
} else {
s3->accel_start(1, 1, 0xffffffff, temp, s3);
s3->accel_start(1, 1, 0xffffffff, temp >> 16, s3);
}
break;
case 0x200:
if (((s3->accel.multifunc[0xa] & 0xc0) == 0x80) || (s3->accel.cmd & 2)) {
if (((s3->accel.frgd_mix & 0x60) != 0x40) || ((s3->accel.bkgd_mix & 0x60) != 0x40)) {
if (s3->accel.cmd & 0x1000)
temp = ((temp & 0xff00ff00) >> 8) | ((temp & 0x00ff00ff) << 8);
s3->accel_start(16, 1, temp, 0, s3);
s3->accel_start(16, 1, temp >> 16, 0, s3);
} else {
s3->accel_start(2, 1, 0xffffffff, temp, s3);
s3->accel_start(2, 1, 0xffffffff, temp >> 16, s3);
}
} else {
s3->accel_start(2, 1, 0xffffffff, temp, s3);
s3->accel_start(2, 1, 0xffffffff, temp >> 16, s3);
}
break;
default:
break;
}
}
return temp;
}
static void
s3_accel_write(uint32_t addr, uint8_t val, void *priv)
{
s3_t *s3 = (s3_t *) priv;
const svga_t *svga = &s3->svga;
if (!s3->enable_8514)
return;
if (s3_enable_fifo(s3)) {
if (svga->crtc[0x53] & 0x08)
s3_queue(s3, addr & 0x1ffff, val, FIFO_WRITE_BYTE);
else
s3_queue(s3, addr & 0xffff, val, FIFO_WRITE_BYTE);
} else
s3_accel_write_fifo(s3, addr & 0xffff, val);
}
static void
s3_accel_write_w(uint32_t addr, uint16_t val, void *priv)
{
s3_t *s3 = (s3_t *) priv;
const svga_t *svga = &s3->svga;
if (!s3->enable_8514)
return;
if (s3_enable_fifo(s3)) {
if (svga->crtc[0x53] & 0x08)
s3_queue(s3, addr & 0x1ffff, val, FIFO_WRITE_WORD);
else
s3_queue(s3, addr & 0xffff, val, FIFO_WRITE_WORD);
} else
s3_accel_write_fifo_w(s3, addr & 0xffff, val);
}
static void
s3_accel_write_l(uint32_t addr, uint32_t val, void *priv)
{
s3_t *s3 = (s3_t *) priv;
const svga_t *svga = &s3->svga;
if (!s3->enable_8514)
return;
if (s3_enable_fifo(s3)) {
if (svga->crtc[0x53] & 0x08)
s3_queue(s3, addr & 0x1ffff, val, FIFO_WRITE_DWORD);
else
s3_queue(s3, addr & 0xffff, val, FIFO_WRITE_DWORD);
} else
s3_accel_write_fifo_l(s3, addr & 0xffff, val);
}
static uint8_t
s3_accel_read(uint32_t addr, void *priv)
{
s3_t *s3 = (s3_t *) priv;
svga_t *svga = &s3->svga;
uint8_t temp = 0x00;
if (!s3->enable_8514)
return 0xff;
if (svga->crtc[0x53] & 0x08) {
if ((addr >= 0x08000) && (addr <= 0x0803f))
return s3_pci_read(0, addr & 0xff, s3);
switch (addr & 0x1ffff) {
case 0x83b0:
case 0x83b1:
case 0x83b2:
case 0x83b3:
case 0x83b4:
case 0x83b5:
case 0x83b6:
case 0x83b7:
case 0x83b8:
case 0x83b9:
case 0x83ba:
case 0x83bb:
case 0x83bc:
case 0x83bd:
case 0x83be:
case 0x83bf:
case 0x83c0:
case 0x83c1:
case 0x83c2:
case 0x83c3:
case 0x83c4:
case 0x83c5:
case 0x83c6:
case 0x83c7:
case 0x83c8:
case 0x83c9:
case 0x83ca:
case 0x83cb:
case 0x83cc:
case 0x83cd:
case 0x83ce:
case 0x83cf:
case 0x83d0:
case 0x83d1:
case 0x83d2:
case 0x83d3:
case 0x83d4:
case 0x83d5:
case 0x83d6:
case 0x83d7:
case 0x83d8:
case 0x83d9:
case 0x83da:
case 0x83db:
case 0x83dc:
case 0x83dd:
case 0x83de:
case 0x83df:
return s3_in(addr & 0x3ff, s3);
case 0x8504:
return s3->subsys_stat;
case 0x8505:
return s3->subsys_cntl;
default:
return s3_accel_in(addr & 0xffff, priv);
}
return 0xff;
} else {
if (addr & 0x8000) {
temp = s3_accel_in(addr & 0xffff, priv);
} else if (s3_cpu_dest(s3)) {
READ_PIXTRANS_BYTE_MM
switch (s3->accel.cmd & 0x600) {
case 0x000:
if (((s3->accel.multifunc[0xa] & 0xc0) == 0x80) || (s3->accel.cmd & 2)) {
if (((s3->accel.frgd_mix & 0x60) != 0x40) || ((s3->accel.bkgd_mix & 0x60) != 0x40))
s3->accel_start(8, 1, temp | (temp << 8) | (temp << 16) | (temp << 24), 0, s3);
else
s3->accel_start(1, 1, 0xffffffff, temp | (temp << 8) | (temp << 16) | (temp << 24), s3);
} else
s3->accel_start(1, 1, 0xffffffff, temp | (temp << 8) | (temp << 16) | (temp << 24), s3);
break;
case 0x200:
if (((s3->accel.multifunc[0xa] & 0xc0) == 0x80) || (s3->accel.cmd & 2)) {
if (((s3->accel.frgd_mix & 0x60) != 0x40) || ((s3->accel.bkgd_mix & 0x60) != 0x40))
s3->accel_start(16, 1, temp | (temp << 8) | (temp << 16) | (temp << 24), 0, s3);
else
s3->accel_start(2, 1, 0xffffffff, temp | (temp << 8) | (temp << 16) | (temp << 24), s3);
} else
s3->accel_start(2, 1, 0xffffffff, temp | (temp << 8) | (temp << 16) | (temp << 24), s3);
break;
default:
break;
}
}
}
return temp;
}
static uint16_t
s3_accel_read_w(uint32_t addr, void *priv)
{
s3_t *s3 = (s3_t *) priv;
svga_t *svga = &s3->svga;
uint16_t temp = 0x0000;
const uint16_t *vram_w = (uint16_t *) svga->vram;
if (!s3->enable_8514)
return 0xffff;
if (svga->crtc[0x53] & 0x08) {
switch (addr & 0x1fffe) {
case 0x811c:
if (s3_enable_fifo(s3))
s3_wait_fifo_idle(s3);
return s3->accel.short_stroke;
default:
return s3_accel_read(addr, priv) | s3_accel_read(addr + 1, priv) << 8;
}
return 0xffff;
} else {
if (addr & 0x8000) {
if (addr == 0x811c) {
if (s3_enable_fifo(s3))
s3_wait_fifo_idle(s3);
temp = s3->accel.short_stroke;
} else {
temp = s3_accel_read((addr & 0xfffe), priv);
temp |= s3_accel_read((addr & 0xfffe) + 1, priv) << 8;
}
} else if (s3_cpu_dest(s3)) {
READ_PIXTRANS_WORD
switch (s3->accel.cmd & 0x600) {
case 0x000:
if (((s3->accel.multifunc[0xa] & 0xc0) == 0x80) || (s3->accel.cmd & 2)) {
if (((s3->accel.frgd_mix & 0x60) != 0x40) || ((s3->accel.bkgd_mix & 0x60) != 0x40))
s3->accel_start(8, 1, temp | (temp << 16), 0, s3);
else
s3->accel_start(1, 1, 0xffffffff, temp | (temp << 16), s3);
} else
s3->accel_start(1, 1, 0xffffffff, temp | (temp << 16), s3);
break;
case 0x200:
if (((s3->accel.multifunc[0xa] & 0xc0) == 0x80) || (s3->accel.cmd & 2)) {
if (((s3->accel.frgd_mix & 0x60) != 0x40) || ((s3->accel.bkgd_mix & 0x60) != 0x40))
s3->accel_start(16, 1, temp | (temp << 16), 0, s3);
else
s3->accel_start(2, 1, 0xffffffff, temp | (temp << 16), s3);
} else
s3->accel_start(2, 1, 0xffffffff, temp | (temp << 16), s3);
break;
default:
break;
}
}
}
return temp;
}
static uint32_t
s3_accel_read_l(uint32_t addr, void *priv)
{
s3_t *s3 = (s3_t *) priv;
svga_t *svga = &s3->svga;
uint32_t temp = 0x00000000;
const uint16_t *vram_w = (uint16_t *) svga->vram;
if (!s3->enable_8514)
return 0xffffffff;
if (svga->crtc[0x53] & 0x08) {
switch (addr & 0x1fffc) {
case 0x8180:
temp = s3->streams.pri_ctrl;
break;
case 0x8184:
temp = s3->streams.chroma_ctrl;
break;
case 0x8190:
temp = s3->streams.sec_ctrl;
break;
case 0x8194:
temp = s3->streams.chroma_upper_bound;
break;
case 0x8198:
temp = s3->streams.sec_filter;
break;
case 0x81a0:
temp = s3->streams.blend_ctrl;
break;
case 0x81c0:
temp = s3->streams.pri_fb0;
break;
case 0x81c4:
temp = s3->streams.pri_fb1;
break;
case 0x81c8:
temp = s3->streams.pri_stride;
break;
case 0x81cc:
temp = s3->streams.buffer_ctrl;
break;
case 0x81d0:
temp = s3->streams.sec_fb0;
break;
case 0x81d4:
temp = s3->streams.sec_fb1;
break;
case 0x81d8:
temp = s3->streams.sec_stride;
break;
case 0x81dc:
temp = s3->streams.overlay_ctrl;
break;
case 0x81e0:
temp = s3->streams.k1_vert_scale;
break;
case 0x81e4:
temp = s3->streams.k2_vert_scale;
break;
case 0x81e8:
temp = s3->streams.dda_vert_accumulator;
break;
case 0x81ec:
temp = s3->streams.fifo_ctrl;
break;
case 0x81f0:
temp = s3->streams.pri_start;
break;
case 0x81f4:
temp = s3->streams.pri_size;
break;
case 0x81f8:
temp = s3->streams.sec_start;
break;
case 0x81fc:
temp = s3->streams.sec_size;
break;
case 0x18080:
if (s3_enable_fifo(s3))
s3_wait_fifo_idle(s3);
temp = 0;
break;
case 0x18088:
if (s3_enable_fifo(s3))
s3_wait_fifo_idle(s3);
temp = s3->videoengine.cntl;
if (s3->bpp == 1) { /*The actual bpp is decided by the guest when idf is the same as odf*/
if (s3->videoengine.idf == 0 && s3->videoengine.odf == 0) {
if (svga->bpp == 15)
temp |= 0x600000;
else
temp |= 0x700000;
}
} else if (s3->bpp > 1) {
if (s3->videoengine.idf == 0 && s3->videoengine.odf == 0)
temp |= 0x300000;
}
break;
case 0x1808c:
if (s3_enable_fifo(s3))
s3_wait_fifo_idle(s3);
temp = s3->videoengine.stretch_filt_const;
break;
case 0x18090:
if (s3_enable_fifo(s3))
s3_wait_fifo_idle(s3);
temp = s3->videoengine.src_dst_step;
break;
case 0x18094:
if (s3_enable_fifo(s3))
s3_wait_fifo_idle(s3);
temp = s3->videoengine.crop;
break;
case 0x18098:
if (s3_enable_fifo(s3))
s3_wait_fifo_idle(s3);
temp = s3->videoengine.src_base;
break;
case 0x1809c:
if (s3_enable_fifo(s3))
s3_wait_fifo_idle(s3);
temp = s3->videoengine.dest_base;
if (s3->videoengine.busy) {
temp |= (1 << 31);
} else {
temp &= ~(1 << 31);
}
break;
default:
temp = s3_accel_read_w(addr, priv) | (s3_accel_read_w(addr + 2, priv) << 16);
break;
}
} else {
if (addr & 0x8000) {
temp = s3_accel_read((addr & 0xfffc), priv);
temp |= s3_accel_read((addr & 0xfffc) + 1, priv) << 8;
temp |= s3_accel_read((addr & 0xfffc) + 2, priv) << 16;
temp |= s3_accel_read((addr & 0xfffc) + 3, priv) << 24;
} else if (s3_cpu_dest(s3)) {
READ_PIXTRANS_LONG
switch (s3->accel.cmd & 0x600) {
case 0x000:
if (((s3->accel.multifunc[0xa] & 0xc0) == 0x80) || (s3->accel.cmd & 2)) {
if (((s3->accel.frgd_mix & 0x60) != 0x40) || ((s3->accel.bkgd_mix & 0x60) != 0x40)) {
s3->accel_start(8, 1, temp, 0, s3);
s3->accel_start(8, 1, temp >> 16, 0, s3);
} else {
s3->accel_start(1, 1, 0xffffffff, temp, s3);
s3->accel_start(1, 1, 0xffffffff, temp >> 16, s3);
}
} else {
s3->accel_start(1, 1, 0xffffffff, temp, s3);
s3->accel_start(1, 1, 0xffffffff, temp >> 16, s3);
}
break;
case 0x200:
if (((s3->accel.multifunc[0xa] & 0xc0) == 0x80) || (s3->accel.cmd & 2)) {
if (((s3->accel.frgd_mix & 0x60) != 0x40) || ((s3->accel.bkgd_mix & 0x60) != 0x40)) {
s3->accel_start(16, 1, temp, 0, s3);
s3->accel_start(16, 1, temp >> 16, 0, s3);
} else {
s3->accel_start(2, 1, 0xffffffff, temp, s3);
s3->accel_start(2, 1, 0xffffffff, temp >> 16, s3);
}
} else {
s3->accel_start(2, 1, 0xffffffff, temp, s3);
s3->accel_start(2, 1, 0xffffffff, temp >> 16, s3);
}
break;
default:
break;
}
}
}
return temp;
}
static void
polygon_setup(s3_t *s3)
{
if (s3->accel.point_1_updated) {
int start_x = s3->accel.poly_cx;
int start_y = s3->accel.poly_cy;
int end_x = s3->accel.destx_distp << 20;
int end_y = s3->accel.desty_axstp;
if (end_y - start_y)
s3->accel.poly_dx1 = (end_x - start_x) / (end_y - start_y);
else
s3->accel.poly_dx1 = 0;
s3->accel.point_1_updated = 0;
if (end_y == s3->accel.poly_cy) {
s3->accel.poly_cx = end_x;
s3->accel.poly_x = end_x >> 20;
}
}
if (s3->accel.point_2_updated) {
int start_x = s3->accel.poly_cx2;
int start_y = s3->accel.poly_cy2;
int end_x = s3->accel.x2 << 20;
int end_y = s3->accel.desty_axstp2;
if (end_y - start_y)
s3->accel.poly_dx2 = (end_x - start_x) / (end_y - start_y);
else
s3->accel.poly_dx2 = 0;
s3->accel.point_2_updated = 0;
if (end_y == s3->accel.poly_cy)
s3->accel.poly_cx2 = end_x;
}
}
#define READ(addr, dat) \
if ((s3->bpp == 0) && !s3->color_16bit) \
dat = svga->vram[dword_remap(svga, addr) & s3->vram_mask]; \
else if ((s3->bpp == 1) || (s3->color_16bit && (svga->bpp < 24))) \
dat = vram_w[dword_remap_w(svga, addr) & (s3->vram_mask >> 1)]; \
else if (s3->bpp == 2) \
dat = svga->vram[dword_remap(svga, addr) & s3->vram_mask]; \
else if (s3->color_16bit && (svga->bpp == 24)) { \
dat = vram_w[dword_remap_w(svga, addr) & (s3->vram_mask >> 1)]; \
} else \
dat = vram_l[dword_remap_l(svga, addr) & (s3->vram_mask >> 2)];
#define MIX_READ \
{ \
switch ((mix_dat & mix_mask) ? (s3->accel.frgd_mix & 0xf) : (s3->accel.bkgd_mix & 0xf)) { \
case 0x0: \
dest_dat = ~dest_dat; \
break; \
case 0x1: \
dest_dat = 0; \
break; \
case 0x2: \
dest_dat = ~0; \
break; \
case 0x3: \
dest_dat = dest_dat; \
break; \
case 0x4: \
dest_dat = ~src_dat; \
break; \
case 0x5: \
dest_dat = src_dat ^ dest_dat; \
break; \
case 0x6: \
dest_dat = ~(src_dat ^ dest_dat); \
break; \
case 0x7: \
dest_dat = src_dat; \
break; \
case 0x8: \
dest_dat = ~(src_dat & dest_dat); \
break; \
case 0x9: \
dest_dat = ~src_dat | dest_dat; \
break; \
case 0xa: \
dest_dat = src_dat | ~dest_dat; \
break; \
case 0xb: \
dest_dat = src_dat | dest_dat; \
break; \
case 0xc: \
dest_dat = src_dat & dest_dat; \
break; \
case 0xd: \
dest_dat = src_dat & ~dest_dat; \
break; \
case 0xe: \
dest_dat = ~src_dat & dest_dat; \
break; \
case 0xf: \
dest_dat = ~(src_dat | dest_dat); \
break; \
} \
}
#define MIX \
{ \
old_dest_dat = dest_dat; \
MIX_READ \
dest_dat = (dest_dat & wrt_mask) | (old_dest_dat & ~wrt_mask); \
}
#define ROPMIX_READ(D, P, S) \
{ \
switch (rop) { \
case 0x00: \
out = 0; \
break; \
case 0x01: \
out = ~(D | (P | S)); \
break; \
case 0x02: \
out = D & ~(P | S); \
break; \
case 0x03: \
out = ~(P | S); \
break; \
case 0x04: \
out = S & ~(D | P); \
break; \
case 0x05: \
out = ~(D | P); \
break; \
case 0x06: \
out = ~(P | ~(D ^ S)); \
break; \
case 0x07: \
out = ~(P | (D & S)); \
break; \
case 0x08: \
out = S & (D & ~P); \
break; \
case 0x09: \
out = ~(P | (D ^ S)); \
break; \
case 0x0a: \
out = D & ~P; \
break; \
case 0x0b: \
out = ~(P | (S & ~D)); \
break; \
case 0x0c: \
out = S & ~P; \
break; \
case 0x0d: \
out = ~(P | (D & ~S)); \
break; \
case 0x0e: \
out = ~(P | ~(D | S)); \
break; \
case 0x0f: \
out = ~P; \
break; \
case 0x10: \
out = P & ~(D | S); \
break; \
case 0x11: \
out = ~(D | S); \
break; \
case 0x12: \
out = ~(S | ~(D ^ P)); \
break; \
case 0x13: \
out = ~(S | (D & P)); \
break; \
case 0x14: \
out = ~(D | ~(P ^ S)); \
break; \
case 0x15: \
out = ~(D | (P & S)); \
break; \
case 0x16: \
out = P ^ (S ^ (D & ~(P & S))); \
break; \
case 0x17: \
out = ~(S ^ ((S ^ P) & (D ^ S))); \
break; \
case 0x18: \
out = (S ^ P) & (P ^ D); \
break; \
case 0x19: \
out = ~(S ^ (D & ~(P & S))); \
break; \
case 0x1a: \
out = P ^ (D | (S & P)); \
break; \
case 0x1b: \
out = ~(S ^ (D & (P ^ S))); \
break; \
case 0x1c: \
out = P ^ (S | (D & P)); \
break; \
case 0x1d: \
out = ~(D ^ (S & (P ^ D))); \
break; \
case 0x1e: \
out = P ^ (D | S); \
break; \
case 0x1f: \
out = ~(P & (D | S)); \
break; \
case 0x20: \
out = D & (P & ~S); \
break; \
case 0x21: \
out = ~(S | (D ^ P)); \
break; \
case 0x22: \
out = D & ~S; \
break; \
case 0x23: \
out = ~(S | (P & ~D)); \
break; \
case 0x24: \
out = (S ^ P) & (D ^ S); \
break; \
case 0x25: \
out = ~(P ^ (D & ~(S & P))); \
break; \
case 0x26: \
out = S ^ (D | (P & S)); \
break; \
case 0x27: \
out = S ^ (D | ~(P ^ S)); \
break; \
case 0x28: \
out = D & (P ^ S); \
break; \
case 0x29: \
out = ~(P ^ (S ^ (D | (P & S)))); \
break; \
case 0x2a: \
out = D & ~(P & S); \
break; \
case 0x2b: \
out = ~(S ^ ((S ^ P) & (P ^ D))); \
break; \
case 0x2c: \
out = S ^ (P & (D | S)); \
break; \
case 0x2d: \
out = P ^ (S | ~D); \
break; \
case 0x2e: \
out = P ^ (S | (D ^ P)); \
break; \
case 0x2f: \
out = ~(P & (S | ~D)); \
break; \
case 0x30: \
out = P & ~S; \
break; \
case 0x31: \
out = ~(S | (D & ~P)); \
break; \
case 0x32: \
out = S ^ (D | (P | S)); \
break; \
case 0x33: \
out = ~S; \
break; \
case 0x34: \
out = S ^ (P | (D & S)); \
break; \
case 0x35: \
out = S ^ (P | ~(D ^ S)); \
break; \
case 0x36: \
out = S ^ (D | P); \
break; \
case 0x37: \
out = ~(S & (D | P)); \
break; \
case 0x38: \
out = P ^ (S & (D | P)); \
break; \
case 0x39: \
out = S ^ (P | ~D); \
break; \
case 0x3a: \
out = S ^ (P | (D ^ S)); \
break; \
case 0x3b: \
out = ~(S & (P | ~D)); \
break; \
case 0x3c: \
out = P ^ S; \
break; \
case 0x3d: \
out = S ^ (P | ~(D | S)); \
break; \
case 0x3e: \
out = S ^ (P | (D & ~S)); \
break; \
case 0x3f: \
out = ~(P & S); \
break; \
case 0x40: \
out = P & (S & ~D); \
break; \
case 0x41: \
out = ~(D | (P ^ S)); \
break; \
case 0x42: \
out = (S ^ D) & (P ^ D); \
break; \
case 0x43: \
out = ~(S ^ (P & ~(D & S))); \
break; \
case 0x44: \
out = S & ~D; \
break; \
case 0x45: \
out = ~(D | (P & ~S)); \
break; \
case 0x46: \
out = D ^ (S | (P & D)); \
break; \
case 0x47: \
out = ~(P ^ (S & (D ^ P))); \
break; \
case 0x48: \
out = S & (D ^ P); \
break; \
case 0x49: \
out = ~(P ^ (D ^ (S | (P & D)))); \
break; \
case 0x4a: \
out = D ^ (P & (S | D)); \
break; \
case 0x4b: \
out = P ^ (D | ~S); \
break; \
case 0x4c: \
out = S & ~(D & P); \
break; \
case 0x4d: \
out = ~(S ^ ((S ^ P) | (D ^ S))); \
break; \
case 0x4e: \
out = P ^ (D | (S ^ P)); \
break; \
case 0x4f: \
out = ~(P & (D | ~S)); \
break; \
case 0x50: \
out = P & ~D; \
break; \
case 0x51: \
out = ~(D | (S & ~P)); \
break; \
case 0x52: \
out = D ^ (P | (S & D)); \
break; \
case 0x53: \
out = ~(S ^ (P & (D ^ S))); \
break; \
case 0x54: \
out = ~(D | ~(P | S)); \
break; \
case 0x55: \
out = ~D; \
break; \
case 0x56: \
out = D ^ (P | S); \
break; \
case 0x57: \
out = ~(D & (P | S)); \
break; \
case 0x58: \
out = P ^ (D & (S | P)); \
break; \
case 0x59: \
out = D ^ (P | ~S); \
break; \
case 0x5a: \
out = D ^ P; \
break; \
case 0x5b: \
out = D ^ (P | ~(S | D)); \
break; \
case 0x5c: \
out = D ^ (P | (S ^ D)); \
break; \
case 0x5d: \
out = ~(D & (P | ~S)); \
break; \
case 0x5e: \
out = D ^ (P | (S & ~D)); \
break; \
case 0x5f: \
out = ~(D & P); \
break; \
case 0x60: \
out = P & (D ^ S); \
break; \
case 0x61: \
out = ~(D ^ (S ^ (P | (D & S)))); \
break; \
case 0x62: \
out = D ^ (S & (P | D)); \
break; \
case 0x63: \
out = S ^ (D | ~P); \
break; \
case 0x64: \
out = S ^ (D & (P | S)); \
break; \
case 0x65: \
out = D ^ (S | ~P); \
break; \
case 0x66: \
out = D ^ S; \
break; \
case 0x67: \
out = S ^ (D | ~(P | S)); \
break; \
case 0x68: \
out = ~(D ^ (S ^ (P | ~(D | S)))); \
break; \
case 0x69: \
out = ~(P ^ (D ^ S)); \
break; \
case 0x6a: \
out = D ^ (P & S); \
break; \
case 0x6b: \
out = ~(P ^ (S ^ (D & (P | S)))); \
break; \
case 0x6c: \
out = S ^ (D & P); \
break; \
case 0x6d: \
out = ~(P ^ (D ^ (S & (P | D)))); \
break; \
case 0x6e: \
out = S ^ (D & (P | ~S)); \
break; \
case 0x6f: \
out = ~(P & ~(D ^ S)); \
break; \
case 0x70: \
out = P & ~(D & S); \
break; \
case 0x71: \
out = ~(S ^ ((S ^ D) & (P ^ D))); \
break; \
case 0x72: \
out = S ^ (D | (P ^ S)); \
break; \
case 0x73: \
out = ~(S & (D | ~P)); \
break; \
case 0x74: \
out = D ^ (S | (P ^ D)); \
break; \
case 0x75: \
out = ~(D & (S | ~P)); \
break; \
case 0x76: \
out = S ^ (D | (P & ~S)); \
break; \
case 0x77: \
out = ~(D & S); \
break; \
case 0x78: \
out = P ^ (D & S); \
break; \
case 0x79: \
out = ~(D ^ (S ^ (P & (D | S)))); \
break; \
case 0x7a: \
out = D ^ (P & (S | ~D)); \
break; \
case 0x7b: \
out = ~(S & ~(D ^ P)); \
break; \
case 0x7c: \
out = S ^ (P & (D | ~S)); \
break; \
case 0x7d: \
out = ~(D & ~(P ^ S)); \
break; \
case 0x7e: \
out = (S ^ P) | (D ^ S); \
break; \
case 0x7f: \
out = ~(D & (P & S)); \
break; \
case 0x80: \
out = D & (P & S); \
break; \
case 0x81: \
out = ~((S ^ P) | (D ^ S)); \
break; \
case 0x82: \
out = D & ~(P ^ S); \
break; \
case 0x83: \
out = ~(S ^ (P & (D | ~S))); \
break; \
case 0x84: \
out = S & ~(D ^ P); \
break; \
case 0x85: \
out = ~(P ^ (D & (S | ~P))); \
break; \
case 0x86: \
out = D ^ (S ^ (P & (D | S))); \
break; \
case 0x87: \
out = ~(P ^ (D & S)); \
break; \
case 0x88: \
out = D & S; \
break; \
case 0x89: \
out = ~(S ^ (D | (P & ~S))); \
break; \
case 0x8a: \
out = D & (S | ~P); \
break; \
case 0x8b: \
out = ~(D ^ (S | (P ^ D))); \
break; \
case 0x8c: \
out = S & (D | ~P); \
break; \
case 0x8d: \
out = ~(S ^ (D | (P ^ S))); \
break; \
case 0x8e: \
out = S ^ ((S ^ D) & (P ^ D)); \
break; \
case 0x8f: \
out = ~(P & ~(D & S)); \
break; \
case 0x90: \
out = P & ~(D ^ S); \
break; \
case 0x91: \
out = ~(S ^ (D & (P | ~S))); \
break; \
case 0x92: \
out = D ^ (P ^ (S & (D | P))); \
break; \
case 0x93: \
out = ~(S ^ (P & D)); \
break; \
case 0x94: \
out = P ^ (S ^ (D & (P | S))); \
break; \
case 0x95: \
out = ~(D ^ (P & S)); \
break; \
case 0x96: \
out = D ^ (P ^ S); \
break; \
case 0x97: \
out = P ^ (S ^ (D | ~(P | S))); \
break; \
case 0x98: \
out = ~(S ^ (D | ~(P | S))); \
break; \
case 0x99: \
out = ~(D ^ S); \
break; \
case 0x9a: \
out = D ^ (P & ~S); \
break; \
case 0x9b: \
out = ~(S ^ (D & (P | S))); \
break; \
case 0x9c: \
out = S ^ (P & ~D); \
break; \
case 0x9d: \
out = ~(D ^ (S & (P | D))); \
break; \
case 0x9e: \
out = D ^ (S ^ (P | (D & S))); \
break; \
case 0x9f: \
out = ~(P & (D ^ S)); \
break; \
case 0xa0: \
out = D & P; \
break; \
case 0xa1: \
out = ~(P ^ (D | (S & ~P))); \
break; \
case 0xa2: \
out = D & (P | ~S); \
break; \
case 0xa3: \
out = ~(D ^ (P | (S ^ D))); \
break; \
case 0xa4: \
out = ~(P ^ (D | ~(S | P))); \
break; \
case 0xa5: \
out = ~(P ^ D); \
break; \
case 0xa6: \
out = D ^ (S & ~P); \
break; \
case 0xa7: \
out = ~(P ^ (D & (S | P))); \
break; \
case 0xa8: \
out = D & (P | S); \
break; \
case 0xa9: \
out = ~(D ^ (P | S)); \
break; \
case 0xaa: \
out = D; \
break; \
case 0xab: \
out = D | ~(P | S); \
break; \
case 0xac: \
out = S ^ (P & (D ^ S)); \
break; \
case 0xad: \
out = ~(D ^ (P | (S & D))); \
break; \
case 0xae: \
out = D | (S & ~P); \
break; \
case 0xaf: \
out = D | ~P; \
break; \
case 0xb0: \
out = P & (D | ~S); \
break; \
case 0xb1: \
out = ~(P ^ (D | (S ^ P))); \
break; \
case 0xb2: \
out = S ^ ((S ^ P) | (D ^ S)); \
break; \
case 0xb3: \
out = ~(S & ~(D & P)); \
break; \
case 0xb4: \
out = P ^ (S & ~D); \
break; \
case 0xb5: \
out = ~(D ^ (P & (S | D))); \
break; \
case 0xb6: \
out = D ^ (P ^ (S | (D & P))); \
break; \
case 0xb7: \
out = ~(S & (D ^ P)); \
break; \
case 0xb8: \
out = P ^ (S & (D ^ P)); \
break; \
case 0xb9: \
out = ~(D ^ (S | (P & D))); \
break; \
case 0xba: \
out = D | (P & ~S); \
break; \
case 0xbb: \
out = D | ~S; \
break; \
case 0xbc: \
out = S ^ (P & ~(D & S)); \
break; \
case 0xbd: \
out = ~((S ^ D) & (P ^ D)); \
break; \
case 0xbe: \
out = D | (P ^ S); \
break; \
case 0xbf: \
out = D | ~(P & S); \
break; \
case 0xc0: \
out = P & S; \
break; \
case 0xc1: \
out = ~(S ^ (P | (D & ~S))); \
break; \
case 0xc2: \
out = ~(S ^ (P | ~(D | S))); \
break; \
case 0xc3: \
out = ~(P ^ S); \
break; \
case 0xc4: \
out = S & (P | ~D); \
break; \
case 0xc5: \
out = ~(S ^ (P | (D ^ S))); \
break; \
case 0xc6: \
out = S ^ (D & ~P); \
break; \
case 0xc7: \
out = ~(P ^ (S & (D | P))); \
break; \
case 0xc8: \
out = S & (D | P); \
break; \
case 0xc9: \
out = ~(S ^ (P | D)); \
break; \
case 0xca: \
out = D ^ (P & (S ^ D)); \
break; \
case 0xcb: \
out = ~(S ^ (P | (D & S))); \
break; \
case 0xcc: \
out = S; \
break; \
case 0xcd: \
out = S | ~(D | P); \
break; \
case 0xce: \
out = S | (D & ~P); \
break; \
case 0xcf: \
out = S | ~P; \
break; \
case 0xd0: \
out = P & (S | ~D); \
break; \
case 0xd1: \
out = ~(P ^ (S | (D ^ P))); \
break; \
case 0xd2: \
out = P ^ (D & ~S); \
break; \
case 0xd3: \
out = ~(S ^ (P & (D | S))); \
break; \
case 0xd4: \
out = S ^ ((S ^ P) & (P ^ D)); \
break; \
case 0xd5: \
out = ~(D & ~(P & S)); \
break; \
case 0xd6: \
out = P ^ (S ^ (D | (P & S))); \
break; \
case 0xd7: \
out = ~(D & (P ^ S)); \
break; \
case 0xd8: \
out = P ^ (D & (S ^ P)); \
break; \
case 0xd9: \
out = ~(S ^ (D | (P & S))); \
break; \
case 0xda: \
out = D ^ (P & ~(S & D)); \
break; \
case 0xdb: \
out = ~((S ^ P) & (D ^ S)); \
break; \
case 0xdc: \
out = S | (P & ~D); \
break; \
case 0xdd: \
out = S | ~D; \
break; \
case 0xde: \
out = S | (D ^ P); \
break; \
case 0xdf: \
out = S | ~(D & P); \
break; \
case 0xe0: \
out = P & (D | S); \
break; \
case 0xe1: \
out = ~(P ^ (D | S)); \
break; \
case 0xe2: \
out = D ^ (S & (P ^ D)); \
break; \
case 0xe3: \
out = ~(P ^ (S | (D & P))); \
break; \
case 0xe4: \
out = S ^ (D & (P ^ S)); \
break; \
case 0xe5: \
out = ~(P ^ (D | (S & P))); \
break; \
case 0xe6: \
out = S ^ (D & ~(P & S)); \
break; \
case 0xe7: \
out = ~((S ^ P) & (P ^ D)); \
break; \
case 0xe8: \
out = S ^ ((S ^ P) & (D ^ S)); \
break; \
case 0xe9: \
out = ~(D ^ (S ^ (P & ~(D & S)))); \
break; \
case 0xea: \
out = D | (P & S); \
break; \
case 0xeb: \
out = D | ~(P ^ S); \
break; \
case 0xec: \
out = S | (D & P); \
break; \
case 0xed: \
out = S | ~(D ^ P); \
break; \
case 0xee: \
out = D | S; \
break; \
case 0xef: \
out = S | (D | ~P); \
break; \
case 0xf0: \
out = P; \
break; \
case 0xf1: \
out = P | ~(D | S); \
break; \
case 0xf2: \
out = P | (D & ~S); \
break; \
case 0xf3: \
out = P | ~S; \
break; \
case 0xf4: \
out = P | (S & ~D); \
break; \
case 0xf5: \
out = P | ~D; \
break; \
case 0xf6: \
out = P | (D ^ S); \
break; \
case 0xf7: \
out = P | ~(D & S); \
break; \
case 0xf8: \
out = P | (D & S); \
break; \
case 0xf9: \
out = P | ~(D ^ S); \
break; \
case 0xfa: \
out = D | P; \
break; \
case 0xfb: \
out = D | (P | ~S); \
break; \
case 0xfc: \
out = P | S; \
break; \
case 0xfd: \
out = P | (S | ~D); \
break; \
case 0xfe: \
out = D | (P | S); \
break; \
case 0xff: \
out = ~0; \
break; \
} \
}
#define ROPMIX \
{ \
old_dest_dat = dest_dat; \
ROPMIX_READ(dest_dat, pat_dat, src_dat); \
out = (out & s3->accel.wrt_mask) | (old_dest_dat & ~s3->accel.wrt_mask); \
}
#define WRITE(addr, dat) \
if ((s3->bpp == 0) && !s3->color_16bit) { \
svga->vram[dword_remap(svga, addr) & s3->vram_mask] = dat; \
svga->changedvram[(dword_remap(svga, addr) & s3->vram_mask) >> 12] = svga->monitor->mon_changeframecount; \
} else if ((s3->bpp == 1) || (s3->color_16bit && (svga->bpp < 24))) { \
vram_w[dword_remap_w(svga, addr) & (s3->vram_mask >> 1)] = dat; \
svga->changedvram[(dword_remap_w(svga, addr) & (s3->vram_mask >> 1)) >> 11] = svga->monitor->mon_changeframecount; \
} else if (s3->bpp == 2) { \
svga->vram[dword_remap(svga, addr) & s3->vram_mask] = dat; \
svga->changedvram[(dword_remap(svga, addr) & s3->vram_mask) >> 12] = svga->monitor->mon_changeframecount; \
} else if (s3->color_16bit && (svga->bpp == 24)) { \
vram_w[dword_remap_w(svga, addr) & (s3->vram_mask >> 1)] = dat; \
svga->changedvram[(dword_remap_w(svga, addr) & (s3->vram_mask >> 1)) >> 11] = svga->monitor->mon_changeframecount; \
} else { \
vram_l[dword_remap_l(svga, addr) & (s3->vram_mask >> 2)] = dat; \
svga->changedvram[(dword_remap_l(svga, addr) & (s3->vram_mask >> 2)) >> 10] = svga->monitor->mon_changeframecount; \
}
static __inline void
convert_to_rgb32(int idf, int is_yuv, uint32_t val, uint8_t *r, uint8_t *g, uint8_t *b, uint8_t *r2, uint8_t *g2, uint8_t *b2)
{
static double dr = 0.0;
static double dg = 0.0;
static double db = 0.0;
static double dY1 = 0.0;
static double dCr = 0.0;
static double dY2 = 0.0;
static double dCb = 0.0;
static double dU = 0.0;
static double dV = 0.0;
switch (idf) {
case 0: /* 8 bpp, RGB 3-3-2 */
dr = (double) ((val >> 5) & 0x07);
dg = (double) ((val >> 2) & 0x07);
db = (double) (val & 0x03);
dr = (dr / 7.0) * 255.0;
dg = (dg / 7.0) * 255.0;
db = (db / 3.0) * 255.0;
break;
case 3: /* 32bpp, RGB 8-8-8 */
dr = (double) ((val >> 16) & 0xff);
dg = (double) ((val >> 8) & 0xff);
db = (double) (val & 0xff);
break;
case 4: /* YCbCr */
if (is_yuv) {
dU = ((double) (val & 0xff)) - 128.0;
dY1 = (double) ((val >> 8) & 0xff);
dY1 = (298.0 * (dY1 - 16.0)) / 256.0;
dV = ((double) ((val >> 16) & 0xff)) - 128.0;
dY2 = (double) ((val >> 24) & 0xff);
dY2 = (298.0 * (dY2 - 16.0)) / 256.0;
dr = (309.0 * dV) / 256.0;
dg = ((100.0 * dU) + (208.0 * dV)) / 256.0;
db = (516.0 * dU) / 256.0;
} else {
dY1 = (double) (val & 0xff);
dCr = ((double) ((val >> 8) & 0xff)) - 128.0;
dY2 = (double) ((val >> 16) & 0xff);
dCb = ((double) ((val >> 24) & 0xff)) - 128.0;
dr = (359.0 * dCr) / 256.0;
dg = ((88.0 * dCb) + (183.0 * dCr)) / 2560.0;
db = (453.0 * dCr) / 256.0;
}
*r = (uint8_t) round(dY1 + dr);
CLAMP(*r);
*g = (uint8_t) round(dY1 - dg);
CLAMP(*g);
*b = (uint8_t) round(dY1 + db);
CLAMP(*b);
*r2 = (uint8_t) round(dY2 + dr);
CLAMP(*r2);
*g2 = (uint8_t) round(dY2 - dg);
CLAMP(*g2);
*b2 = (uint8_t) round(dY2 + db);
CLAMP(*b2);
return;
case 5: /* 16bpp, raw */
case 7: /* 16bpp, RGB 5-6-5 */
dr = (double) ((val >> 11) & 0x1f);
dg = (double) ((val >> 5) & 0x03f);
db = (double) (val & 0x1f);
dr = (dr / 31.0) * 255.0;
dg = (dg / 63.0) * 255.0;
db = (db / 31.0) * 255.0;
break;
case 6: /* 15bpp, RGB 5-5-5 */
dr = (double) ((val >> 10) & 0x1f);
dg = (double) ((val >> 5) & 0x01f);
db = (double) (val & 0x1f);
dr = (dr / 31.0) * 255.0;
dg = (dg / 31.0) * 255.0;
db = (db / 31.0) * 255.0;
break;
default:
break;
}
*r = (uint8_t) round(dr);
*g = (uint8_t) round(dg);
*b = (uint8_t) round(db);
}
static __inline void
convert_from_rgb32(int idf, int odf, int is_yuv, uint32_t *val, uint8_t r, uint8_t g, uint8_t b, uint8_t r2, uint8_t g2, uint8_t b2)
{
static double dr = 0.0;
static double dg = 0.0;
static double db = 0.0;
static double dr2 = 0.0;
static double dg2 = 0.0;
static double db2 = 0.0;
static double dY1 = 0.0;
static double dCr = 0.0;
static double dY2 = 0.0;
static double dCb = 0.0;
static double dU = 0.0;
static double dV = 0.0;
dr = (double) r;
dg = (double) g;
db = (double) b;
switch (odf) {
case 0: /* 8 bpp, RGB 3-3-2 */
switch (idf) {
case 3:
*val = (((uint32_t) round(dr)) << 16) + (((uint32_t) round(dg)) << 8) + ((uint32_t) round(db));
break;
case 5:
case 7:
dr = (dr / 255.0) * 31.0;
dg = (dg / 255.0) * 63.0;
db = (db / 255.0) * 31.0;
*val = (((uint32_t) round(dr)) << 11) + (((uint32_t) round(dg)) << 5) + ((uint32_t) round(db));
break;
case 6:
dr = (dr / 255.0) * 31.0;
dg = (dg / 255.0) * 31.0;
db = (db / 255.0) * 31.0;
*val = (((uint32_t) round(dr)) << 10) + (((uint32_t) round(dg)) << 5) + ((uint32_t) round(db));
break;
case 0:
default:
dr = (dr / 255.0) * 7.0;
dg = (dg / 255.0) * 7.0;
db = (db / 255.0) * 3.0;
*val = (((uint32_t) round(dr)) << 5) + (((uint32_t) round(dg)) << 2) + ((uint32_t) round(db));
break;
}
break;
case 3: /* 32bpp, RGB 8-8-8 */
*val = (((uint32_t) round(dr)) << 16) + (((uint32_t) round(dg)) << 8) + ((uint32_t) round(db));
break;
case 4: /* YCbCr */
dr2 = (double) r2;
dg2 = (double) g2;
db2 = (double) b2;
if (is_yuv) {
dU = ((113046.0 * dg2) - (71552.0 * dr2) - (69488.0 * db2)) / 28509.0;
dV = ((3328.0 * dr2) + (800.0 * db2) - (4128.0 * dg2)) / 663.0;
dY1 = dr - ((309 * dV) / 256.0);
dY2 = dr2 - ((309 * dV) / 256.0);
*val = ((uint32_t) round(dU)) + (((uint32_t) round(dY1)) << 8) + (((uint32_t) round(dV)) << 16) + (((uint32_t) round(dY2)) << 24);
} else {
dCr = ((128.0 * db2) - (128.0 * dr2)) / 47.0;
dCb = ((128.0 * dr2) - (128.0 * dg2) - (271.0 * dCr)) / 44.0;
dY1 = dr - ((359.0 * dCr) / 256.0);
dY2 = dr2 - ((359.0 * dCr) / 256.0);
*val = ((uint32_t) round(dY1)) + (((uint32_t) round(dCr)) << 8) + (((uint32_t) round(dY2)) << 16) + (((uint32_t) round(dCb)) << 24);
}
return;
case 5: /* 16bpp, raw */
case 7: /* 16bpp, RGB 5-6-5 */
dr = (dr / 255.0) * 31.0;
dg = (dg / 255.0) * 63.0;
db = (db / 255.0) * 31.0;
*val = (((uint32_t) round(dr)) << 11) + (((uint32_t) round(dg)) << 5) + ((uint32_t) round(db));
break;
case 6: /* 15bpp, RGB 5-5-5 */
dr = (dr / 255.0) * 31.0;
dg = (dg / 255.0) * 31.0;
db = (db / 255.0) * 31.0;
*val = (((uint32_t) round(dr)) << 10) + (((uint32_t) round(dg)) << 5) + ((uint32_t) round(db));
break;
default:
break;
}
}
/*To Do: Dithering, color space conversion.*/
static void
s3_visionx68_video_engine_op(uint32_t cpu_dat, s3_t *s3)
{
svga_t *svga = &s3->svga;
int idf;
int odf;
int host;
int is_yuv;
uint32_t src;
uint32_t dest = 0x00000000;
uint8_t r = 0x00;
uint8_t g = 0x00;
uint8_t b = 0x00;
uint8_t r2 = 0x00;
uint8_t g2 = 0x00;
uint8_t b2 = 0x00;
uint16_t *vram_w = (uint16_t *) svga->vram;
uint32_t *vram_l = (uint32_t *) svga->vram;
uint32_t k2 = 0;
uint32_t dda = 0;
uint32_t diff = 0;
int count = -1;
idf = s3->videoengine.idf;
odf = s3->videoengine.odf;
is_yuv = s3->videoengine.yuv;
host = s3->videoengine.host_data;
k2 = s3->videoengine.k2 - 0x700;
dda = s3->videoengine.dda_init_accumulator - 0xf00;
diff = 0xff - k2;
s3->videoengine.busy = 1;
if (host) {
if (idf == 0 && odf == 0) {
if (s3->bpp == 0)
count = 4;
else if (s3->bpp == 1)
count = 2;
else
count = 1;
} else {
if (idf == 0)
count = 4;
else if (idf == 3)
count = 1;
else
count = 2;
}
}
if (s3->videoengine.input == 1) {
if (s3->videoengine.scale_down) {
if (s3->bpp > 1) {
s3->videoengine.sx = k2 - dda + diff;
s3->videoengine.sx_backup = s3->videoengine.len - s3->videoengine.start;
} else {
s3->videoengine.sx = k2 - dda + diff - 1;
s3->videoengine.sx_backup = s3->videoengine.len - s3->videoengine.start - 1;
}
s3->videoengine.sx_scale_inc = (double) (s3->videoengine.sx_backup >> 1);
s3->videoengine.sx_scale_inc = s3->videoengine.sx_scale_inc / (double) (s3->videoengine.sx >> 1);
} else {
s3->videoengine.sx_scale = (double) (s3->videoengine.k1 - 2);
s3->videoengine.sx_scale_dec = (s3->videoengine.sx_scale / (double) (s3->videoengine.len - s3->videoengine.start - 2));
if (s3->videoengine.sx_scale_dec >= 0.5) {
s3->videoengine.sx_scale++;
}
}
if (s3->bpp == 0) {
s3->videoengine.dest = s3->videoengine.dest_base + s3->width;
s3->videoengine.src = s3->videoengine.src_base + s3->width;
} else if (s3->bpp == 1) {
s3->videoengine.dest = (s3->videoengine.dest_base >> 1) + s3->width;
s3->videoengine.src = (s3->videoengine.src_base >> 1) + s3->width;
} else {
s3->videoengine.dest = (s3->videoengine.dest_base >> 2) + s3->width;
s3->videoengine.src = (s3->videoengine.src_base >> 2) + s3->width;
}
s3->videoengine.input = 2;
s3->videoengine.cx = 0.0;
s3->videoengine.dx = 0.0;
}
while (count) {
if (host) { /*Source data is CPU*/
src = cpu_dat;
} else { /*Source data is display memory*/
READ(s3->videoengine.src + lround(s3->videoengine.cx), src);
}
convert_to_rgb32(idf, is_yuv, src, &r, &g, &b, &r2, &g2, &b2);
convert_from_rgb32(idf, odf, is_yuv, &dest, r, g, b, r2, g2, b2);
WRITE(s3->videoengine.dest + lround(s3->videoengine.dx), dest);
if (s3->videoengine.scale_down) { /*Data shrink*/
s3->videoengine.dx += s3->videoengine.sx_scale_inc;
if (!host)
s3->videoengine.cx += s3->videoengine.sx_scale_inc;
s3->videoengine.sx--;
if (host) {
if (s3->bpp == 0) {
cpu_dat >>= 8;
} else {
cpu_dat >>= 16;
}
count--;
}
if (s3->videoengine.sx < 0) {
if (s3->bpp > 1) {
s3->videoengine.sx = k2 - dda + diff;
s3->videoengine.sx_backup = s3->videoengine.len - s3->videoengine.start;
} else {
s3->videoengine.sx = k2 - dda + diff - 1;
s3->videoengine.sx_backup = s3->videoengine.len - s3->videoengine.start - 1;
}
s3->videoengine.sx_scale_inc = (double) (s3->videoengine.sx_backup >> 1);
s3->videoengine.sx_scale_inc = s3->videoengine.sx_scale_inc / (double) (s3->videoengine.sx >> 1);
s3->videoengine.cx = 0.0;
s3->videoengine.dx = 0.0;
if (s3->bpp == 0) {
s3->videoengine.dest = s3->videoengine.dest_base + s3->width;
s3->videoengine.src = s3->videoengine.src_base + s3->width;
} else if (s3->bpp == 1) {
s3->videoengine.dest = (s3->videoengine.dest_base >> 1) + s3->width;
s3->videoengine.src = (s3->videoengine.src_base >> 1) + s3->width;
} else {
s3->videoengine.dest = (s3->videoengine.dest_base >> 2) + s3->width;
s3->videoengine.src = (s3->videoengine.src_base >> 2) + s3->width;
}
if (s3->videoengine.input >= 1) {
s3->videoengine.busy = 0;
return;
}
}
} else { /*Data stretch*/
s3->videoengine.dx++;
s3->videoengine.sx_scale -= s3->videoengine.sx_scale_dec;
s3->videoengine.sx_scale_backup = (s3->videoengine.sx_scale - s3->videoengine.sx_scale_dec);
s3->videoengine.sx = lround(s3->videoengine.sx_scale);
s3->videoengine.sx_scale_int = lround(s3->videoengine.sx_scale_backup);
if (s3->videoengine.sx > s3->videoengine.sx_scale_int) {
if (host) {
if (s3->bpp == 0)
cpu_dat >>= 8;
else
cpu_dat >>= 16;
count--;
} else {
s3->videoengine.cx++;
}
}
if (s3->videoengine.sx < 0) {
s3->videoengine.sx_scale = (double) (s3->videoengine.k1 - 2);
s3->videoengine.sx_scale_dec = (s3->videoengine.sx_scale / (double) (s3->videoengine.len - s3->videoengine.start - 2));
if (s3->videoengine.sx_scale_dec >= 0.5) {
s3->videoengine.sx_scale++;
}
s3->videoengine.cx = 0.0;
s3->videoengine.dx = 0.0;
if (s3->bpp == 0) {
s3->videoengine.dest = s3->videoengine.dest_base + s3->width;
s3->videoengine.src = s3->videoengine.src_base + s3->width;
} else if (s3->bpp == 1) {
s3->videoengine.dest = (s3->videoengine.dest_base >> 1) + s3->width;
s3->videoengine.src = (s3->videoengine.src_base >> 1) + s3->width;
} else {
s3->videoengine.dest = (s3->videoengine.dest_base >> 2) + s3->width;
s3->videoengine.src = (s3->videoengine.src_base >> 2) + s3->width;
}
if (s3->videoengine.input >= 1) {
s3->videoengine.busy = 0;
return;
}
}
}
}
}
void
s3_911_accel_start(int count, int cpu_input, uint32_t mix_dat, uint32_t cpu_dat, void *priv)
{
s3_t *s3 = (s3_t *)priv;
svga_t *svga = &s3->svga;
uint32_t src_dat = 0;
uint32_t dest_dat;
uint32_t old_dest_dat;
int frgd_mix;
int bkgd_mix;
int clip_t = s3->accel.multifunc[1] & 0xfff;
int clip_l = s3->accel.multifunc[2] & 0xfff;
int clip_b = s3->accel.multifunc[3] & 0xfff;
int clip_r = s3->accel.multifunc[4] & 0xfff;
int vram_mask = (s3->accel.multifunc[0xa] & 0xc0) == 0xc0;
uint32_t mix_mask = (s3->accel.cmd & 0x200) ? 0x8000 : 0x80;
uint16_t *vram_w = (uint16_t *) svga->vram;
uint32_t *vram_l = (uint32_t *) svga->vram;
uint32_t rd_mask = s3->accel.rd_mask;
uint32_t wrt_mask = s3->accel.wrt_mask;
uint32_t frgd_color = s3->accel.frgd_color;
uint32_t bkgd_color = s3->accel.bkgd_color;
int cmd = s3->accel.cmd >> 13;
if ((s3->accel.cmd & 0x100) && (s3_cpu_src(s3) || (s3_cpu_dest(s3))) && (!cpu_input || (s3_enable_fifo(s3) == 0)))
s3->force_busy = 1;
if (cpu_input && (((s3->accel.multifunc[0xa] & 0xc0) != 0x80) || (!(s3->accel.cmd & 2)))) {
if (s3->color_16bit) {
if (count > 1)
count >>= 1;
}
}
if (s3->color_16bit)
rd_mask &= 0xffff;
else
rd_mask &= 0xff;
/*Bit 4 of the Command register is the draw yes bit, which enables writing to memory/reading from memory when enabled.
When this bit is disabled, no writing to memory/reading from memory is allowed. (This bit is almost meaningless on
the NOP command)*/
switch (cmd) {
case 0: /*NOP (Short Stroke Vectors)*/
if (s3->accel.ssv_state == 0)
break;
frgd_mix = (s3->accel.frgd_mix >> 5) & 3;
bkgd_mix = (s3->accel.bkgd_mix >> 5) & 3;
if (s3->accel.cmd & 8) { /*Radial*/
while (count-- && s3->accel.ssv_len >= 0) {
if ((s3->accel.cx & 0xfff) >= clip_l && (s3->accel.cx & 0xfff) <= clip_r && (s3->accel.cy & 0xfff) >= clip_t && (s3->accel.cy & 0xfff) <= clip_b) {
switch ((mix_dat & mix_mask) ? frgd_mix : bkgd_mix) {
case 0:
src_dat = bkgd_color;
break;
case 1:
src_dat = frgd_color;
break;
case 2:
src_dat = cpu_dat;
break;
case 3:
src_dat = 0;
break;
default:
break;
}
READ((s3->accel.cy * s3->width) + s3->accel.cx, dest_dat);
MIX
if (s3->accel.ssv_draw) {
WRITE((s3->accel.cy * s3->width) + s3->accel.cx, dest_dat);
}
}
mix_dat <<= 1;
mix_dat |= 1;
if (s3->bpp == 0)
cpu_dat >>= 8;
else
cpu_dat >>= 16;
if (!s3->accel.ssv_len)
break;
switch (s3->accel.ssv_dir & 0xe0) {
case 0x00:
s3->accel.cx++;
break;
case 0x20:
s3->accel.cx++;
s3->accel.cy--;
break;
case 0x40:
s3->accel.cy--;
break;
case 0x60:
s3->accel.cx--;
s3->accel.cy--;
break;
case 0x80:
s3->accel.cx--;
break;
case 0xa0:
s3->accel.cx--;
s3->accel.cy++;
break;
case 0xc0:
s3->accel.cy++;
break;
case 0xe0:
s3->accel.cx++;
s3->accel.cy++;
break;
default:
break;
}
s3->accel.ssv_len--;
s3->accel.cx &= 0xfff;
s3->accel.cy &= 0xfff;
}
s3->accel.cur_x = s3->accel.cx;
s3->accel.cur_y = s3->accel.cy;
}
break;
case 1: /*Draw line*/
if (!cpu_input) {
s3->accel.cx = s3->accel.cur_x & 0xfff;
s3->accel.cy = s3->accel.cur_y & 0xfff;
s3->accel.sy = s3->accel.maj_axis_pcnt & 0x7ff;
if (s3->color_16bit && (svga->bpp < 24)) {
if (s3->accel.wrt_mask != 0xffff) {
if (s3->accel.cur_x & 0x400) {
s3->accel.color_16bit_check = 0;
s3->accel.minus = 0x400;
} else {
s3->accel.color_16bit_check = 1;
s3->accel.minus = 0;
}
} else {
if (s3->accel.cur_x & 0x400)
s3->accel.color_16bit_check = 1;
else
s3->accel.color_16bit_check = 0;
s3->accel.minus = 0;
}
} else {
s3->accel.color_16bit_check = 0;
s3->accel.minus = 0;
}
if (s3_cpu_src(s3))
return; /*Wait for data from CPU*/
}
frgd_mix = (s3->accel.frgd_mix >> 5) & 3;
bkgd_mix = (s3->accel.bkgd_mix >> 5) & 3;
if (s3->accel.cmd & 8) { /*Radial*/
if (s3->color_16bit && (svga->bpp < 24)) {
if (s3->accel.color_16bit_check)
return;
if (s3->accel.wrt_mask != 0xffff)
wrt_mask = (s3->accel.wrt_mask_actual[0] | (s3->accel.wrt_mask_actual[1] << 8));
}
while (count-- && s3->accel.sy >= 0) {
if ((s3->accel.cx & 0xfff) >= clip_l && (s3->accel.cx & 0xfff) <= clip_r && (s3->accel.cy & 0xfff) >= clip_t && (s3->accel.cy & 0xfff) <= clip_b) {
switch ((mix_dat & mix_mask) ? frgd_mix : bkgd_mix) {
case 0:
src_dat = bkgd_color;
if (s3->color_16bit && (svga->bpp < 24))
src_dat = s3->accel.bkgd_color_actual[0] | (s3->accel.bkgd_color_actual[1] << 8);
break;
case 1:
src_dat = frgd_color;
if (s3->color_16bit && (svga->bpp < 24))
src_dat = s3->accel.frgd_color_actual[0] | (s3->accel.frgd_color_actual[1] << 8);
break;
case 2:
src_dat = cpu_dat;
break;
case 3:
src_dat = 0;
break;
default:
break;
}
READ((s3->accel.cy * s3->width) + s3->accel.cx - s3->accel.minus, dest_dat);
MIX
WRITE((s3->accel.cy * s3->width) + s3->accel.cx - s3->accel.minus, dest_dat);
}
mix_dat <<= 1;
mix_dat |= 1;
if ((s3->bpp == 0) && !s3->color_16bit)
cpu_dat >>= 8;
else
cpu_dat >>= 16;
if (!s3->accel.sy)
break;
switch (s3->accel.cmd & 0xe0) {
case 0x00:
s3->accel.cx++;
break;
case 0x20:
s3->accel.cx++;
s3->accel.cy--;
break;
case 0x40:
s3->accel.cy--;
break;
case 0x60:
s3->accel.cx--;
s3->accel.cy--;
break;
case 0x80:
s3->accel.cx--;
break;
case 0xa0:
s3->accel.cx--;
s3->accel.cy++;
break;
case 0xc0:
s3->accel.cy++;
break;
case 0xe0:
s3->accel.cx++;
s3->accel.cy++;
break;
default:
break;
}
s3->accel.sy--;
s3->accel.cx &= 0xfff;
s3->accel.cy &= 0xfff;
}
s3->accel.cur_x = s3->accel.cx;
s3->accel.cur_y = s3->accel.cy;
} else { /*Bresenham*/
if (s3->accel.b2e8_pix && s3_cpu_src(s3) && (count == 16)) { /*Stupid undocumented 0xB2E8 on 911/924*/
count = s3->accel.maj_axis_pcnt + 1;
s3->accel.temp_cnt = 16;
}
if (s3->color_16bit && (svga->bpp < 24)) {
if (!s3->accel.b2e8_pix) {
if (!s3->accel.color_16bit_check)
wrt_mask = (s3->accel.wrt_mask_actual[0] | (s3->accel.wrt_mask_actual[1] << 8));
else
return;
}
}
s3_log("CMD=%04x, curx=%d, lwrtmask=%04x, actual wrtmask=%04x, frgdmix=%d, "
"bkgdmix=%d, input=%d, cnt=%d.\n", s3->accel.cmd, s3->accel.cur_x,
wrt_mask, s3->accel.wrt_mask, frgd_mix, bkgd_mix, cpu_input, count);
while (count-- && s3->accel.sy >= 0) {
if (s3->accel.b2e8_pix && s3_cpu_src(s3) && !s3->accel.temp_cnt) {
mix_dat >>= 16;
s3->accel.temp_cnt = 16;
}
if ((s3->accel.cx & 0xfff) >= clip_l && (s3->accel.cx & 0xfff) <= clip_r &&
(s3->accel.cy & 0xfff) >= clip_t && (s3->accel.cy & 0xfff) <= clip_b) {
switch ((mix_dat & mix_mask) ? frgd_mix : bkgd_mix) {
case 0:
src_dat = bkgd_color;
if (s3->color_16bit && (svga->bpp < 24) && !s3->accel.b2e8_pix) {
if (!s3->accel.color_16bit_check)
src_dat = s3->accel.bkgd_color_actual[0] |
(s3->accel.bkgd_color_actual[1] << 8);
}
break;
case 1:
src_dat = frgd_color;
if (s3->color_16bit && (svga->bpp < 24) && !s3->accel.b2e8_pix) {
if (!s3->accel.color_16bit_check)
src_dat = s3->accel.frgd_color_actual[0] |
(s3->accel.frgd_color_actual[1] << 8);
}
break;
case 2:
src_dat = cpu_dat;
break;
case 3:
src_dat = 0;
break;
default:
break;
}
READ((s3->accel.cy * s3->width) + s3->accel.cx - s3->accel.minus, dest_dat);
MIX
if (s3->accel.cmd & 0x10) {
WRITE((s3->accel.cy * s3->width) + s3->accel.cx - s3->accel.minus, dest_dat);
}
}
if (s3->accel.b2e8_pix && s3_cpu_src(s3)) {
if (s3->accel.temp_cnt > 0) {
s3->accel.temp_cnt--;
mix_dat <<= 1;
mix_dat |= 1;
}
} else {
mix_dat <<= 1;
mix_dat |= 1;
}
if (s3->color_16bit)
cpu_dat >>= 16;
else
cpu_dat >>= 8;
if (!s3->accel.sy)
break;
if (s3->accel.cmd & 0x40) {
if (s3->accel.cmd & 0x80)
s3->accel.cy++;
else
s3->accel.cy--;
if (s3->accel.err_term >= 0) {
s3->accel.err_term += s3->accel.destx_distp;
if (s3->accel.cmd & 0x20)
s3->accel.cx++;
else
s3->accel.cx--;
} else
s3->accel.err_term += s3->accel.desty_axstp;
} else {
if (s3->accel.cmd & 0x20)
s3->accel.cx++;
else
s3->accel.cx--;
if (s3->accel.err_term >= 0) {
s3->accel.err_term += s3->accel.destx_distp;
if (s3->accel.cmd & 0x80)
s3->accel.cy++;
else
s3->accel.cy--;
} else
s3->accel.err_term += s3->accel.desty_axstp;
}
s3->accel.sy--;
s3->accel.cx &= 0xfff;
s3->accel.cy &= 0xfff;
}
s3->accel.cur_x = s3->accel.cx;
s3->accel.cur_y = s3->accel.cy;
}
break;
case 2: /*Rectangle fill*/
if (!cpu_input) { /*!cpu_input is trigger to start operation*/
s3->accel.sx = s3->accel.maj_axis_pcnt & 0xfff;
s3->accel.sy = s3->accel.multifunc[0] & 0xfff;
s3->accel.cx = s3->accel.cur_x & 0xfff;
s3->accel.cy = s3->accel.cur_y & 0xfff;
s3->accel.pix_trans_x_count = 0;
s3->accel.dest = s3->accel.cy * s3->width;
if (s3->color_16bit && (svga->bpp < 24)) {
if (s3->accel.cur_x & 0x400) {
s3->accel.color_16bit_check = 0;
s3->accel.minus = 0x400;
} else {
s3->accel.color_16bit_check = 1;
s3->accel.minus = 0;
}
if (s3->accel.color_16bit_check) {
if (((s3->accel.multifunc[0xa] & 0xc0) == 0x00) && !(s3->accel.cmd & 2))
s3->accel.color_16bit_check_rectfill = !!s3_cpu_src(s3);
else
s3->accel.color_16bit_check_rectfill = 0;
}
if (s3->accel.color_16bit_check_rectfill) {
if (s3->accel.color_16bit_check) {
s3->accel.pix_trans_ptr = (uint8_t *) calloc(1, (s3->accel.sx + 1) << 1);
s3->accel.pix_trans_ptr_cnt = (s3->accel.sx + 1) << 1;
}
} else
s3->accel.pix_trans_x_count = 0;
} else {
s3->accel.pix_trans_x_count = 0;
s3->accel.color_16bit_check = 0;
s3->accel.color_16bit_check_rectfill = 0;
s3->accel.minus = 0;
}
if (s3_cpu_src(s3)) {
s3->data_available = 0;
return; /*Wait for data from CPU*/
} else if (s3_cpu_dest(s3)) {
s3->data_available = 1;
return;
}
}
frgd_mix = (s3->accel.frgd_mix >> 5) & 3;
bkgd_mix = (s3->accel.bkgd_mix >> 5) & 3;
if (s3->accel.b2e8_pix && s3_cpu_src(s3) && count == 16) { /*Stupid undocumented 0xB2E8 on 911/924*/
count = s3->accel.maj_axis_pcnt + 1;
s3->accel.temp_cnt = 16;
}
if (s3->color_16bit && (svga->bpp < 24)) {
if (!s3->accel.b2e8_pix) {
if (!s3->accel.color_16bit_check) {
wrt_mask = (s3->accel.wrt_mask_actual[0] | (s3->accel.wrt_mask_actual[1] << 8));
} else if (s3->accel.color_16bit_check && (s3->accel.cmd == 0x40f3))
return;
}
}
while (count-- && s3->accel.sy >= 0) {
if (s3->accel.b2e8_pix && s3_cpu_src(s3) && !s3->accel.temp_cnt) {
mix_dat >>= 16;
s3->accel.temp_cnt = 16;
}
if ((s3->accel.cx & 0xfff) >= clip_l && (s3->accel.cx & 0xfff) <= clip_r && (s3->accel.cy & 0xfff) >= clip_t && (s3->accel.cy & 0xfff) <= clip_b) {
if (s3_cpu_dest(s3) && ((s3->accel.multifunc[0xa] & 0xc0) == 0x00)) {
mix_dat = mix_mask; /* Mix data = forced to foreground register. */
} else if (s3_cpu_dest(s3) && vram_mask) {
/* Mix data = current video memory value. */
READ(s3->accel.dest + s3->accel.cx - s3->accel.minus, mix_dat);
mix_dat = ((mix_dat & rd_mask) == rd_mask);
mix_dat = mix_dat ? mix_mask : 0;
}
if (s3_cpu_dest(s3)) {
READ(s3->accel.dest + s3->accel.cx - s3->accel.minus, src_dat);
if (vram_mask)
src_dat = ((src_dat & rd_mask) == rd_mask);
} else {
switch ((mix_dat & mix_mask) ? frgd_mix : bkgd_mix) {
case 0:
src_dat = bkgd_color;
if (s3->color_16bit && (svga->bpp < 24) && !s3->accel.b2e8_pix && (s3->accel.cmd != 0x41b3)) {
if (!s3->accel.color_16bit_check)
src_dat = s3->accel.bkgd_color_actual[0] | (s3->accel.bkgd_color_actual[1] << 8);
}
break;
case 1:
src_dat = frgd_color;
if (s3->color_16bit && (svga->bpp < 24) && !s3->accel.b2e8_pix && (s3->accel.cmd != 0x41b3)) {
if (!s3->accel.color_16bit_check)
src_dat = s3->accel.frgd_color_actual[0] | (s3->accel.frgd_color_actual[1] << 8);
}
break;
case 2:
src_dat = cpu_dat;
break;
case 3:
src_dat = 0;
break;
default:
break;
}
}
READ(s3->accel.dest + s3->accel.cx - s3->accel.minus, dest_dat);
MIX
if (s3->accel.cmd & 0x10) {
WRITE(s3->accel.dest + s3->accel.cx - s3->accel.minus, dest_dat);
}
}
if (s3->accel.b2e8_pix && s3_cpu_src(s3)) {
if (s3->accel.temp_cnt > 0) {
s3->accel.temp_cnt--;
mix_dat <<= 1;
mix_dat |= 1;
}
} else {
mix_dat <<= 1;
mix_dat |= 1;
}
if (s3->color_16bit)
cpu_dat >>= 16;
else
cpu_dat >>= 8;
if (s3->accel.cmd & 0x20)
s3->accel.cx++;
else
s3->accel.cx--;
s3->accel.cx &= 0xfff;
s3->accel.sx--;
if (s3->accel.sx < 0) {
if (s3->accel.cmd & 0x20)
s3->accel.cx -= (s3->accel.maj_axis_pcnt & 0xfff) + 1;
else
s3->accel.cx += (s3->accel.maj_axis_pcnt & 0xfff) + 1;
s3->accel.sx = s3->accel.maj_axis_pcnt & 0xfff;
if (s3->accel.cmd & 0x80)
s3->accel.cy++;
else
s3->accel.cy--;
s3->accel.cy &= 0xfff;
s3->accel.dest = s3->accel.cy * s3->width;
s3->accel.sy--;
if (cpu_input) {
if (s3->accel.b2e8_pix) {
s3->accel.cur_x = s3->accel.cx;
s3->accel.cur_y = s3->accel.cy;
}
return;
}
if (s3->accel.sy < 0) {
s3->accel.cur_x = s3->accel.cx;
s3->accel.cur_y = s3->accel.cy;
return;
}
}
}
break;
case 6: /*BitBlt*/
if (!cpu_input) { /*!cpu_input is trigger to start operation*/
s3->accel.sx = s3->accel.maj_axis_pcnt & 0xfff;
s3->accel.sy = s3->accel.multifunc[0] & 0xfff;
s3->accel.dx = s3->accel.destx_distp & 0xfff;
s3->accel.dy = s3->accel.desty_axstp & 0xfff;
s3->accel.cx = s3->accel.cur_x & 0xfff;
s3->accel.cy = s3->accel.cur_y & 0xfff;
s3->accel.src = s3->accel.cy * s3->width;
s3->accel.dest = s3->accel.dy * s3->width;
if (s3->color_16bit && (svga->bpp < 24)) {
if (s3->accel.destx_distp & 0x400) {
s3->accel.color_16bit_check = 0;
s3->accel.minus = 0x400;
} else {
s3->accel.color_16bit_check = 1;
s3->accel.minus = 0;
}
s3->accel.srcminus = 0x400;
} else {
s3->accel.color_16bit_check = 0;
s3->accel.minus = 0;
s3->accel.srcminus = 0;
}
}
if ((s3->accel.cmd & 0x100) && !cpu_input)
return; /*Wait for data from CPU*/
frgd_mix = (s3->accel.frgd_mix >> 5) & 3;
bkgd_mix = (s3->accel.bkgd_mix >> 5) & 3;
if (s3->color_16bit && (svga->bpp < 24)) {
if (!s3->accel.color_16bit_check)
wrt_mask = (s3->accel.wrt_mask_actual[0] | (s3->accel.wrt_mask_actual[1] << 8));
else
return;
}
if (!cpu_input && (frgd_mix == 3) && !vram_mask && ((s3->accel.cmd & 0xa0) == 0xa0) && ((s3->accel.frgd_mix & 0xf) == 7) && ((s3->accel.bkgd_mix & 0xf) == 7)) {
while (1) {
if ((s3->accel.dx & 0xfff) >= clip_l && (s3->accel.dx & 0xfff) <= clip_r && (s3->accel.dy & 0xfff) >= clip_t && (s3->accel.dy & 0xfff) <= clip_b) {
READ(s3->accel.src + s3->accel.cx - s3->accel.srcminus, src_dat);
READ(s3->accel.dest + s3->accel.dx - s3->accel.minus, dest_dat);
dest_dat = (src_dat & wrt_mask) | (dest_dat & ~wrt_mask);
WRITE(s3->accel.dest + s3->accel.dx - s3->accel.minus, dest_dat);
}
s3->accel.cx++;
s3->accel.dx++;
s3->accel.sx--;
s3->accel.dx &= 0xfff;
if (s3->accel.sx < 0) {
s3->accel.cx -= (s3->accel.maj_axis_pcnt & 0xfff) + 1;
s3->accel.dx -= (s3->accel.maj_axis_pcnt & 0xfff) + 1;
s3->accel.sx = s3->accel.maj_axis_pcnt & 0xfff;
s3->accel.cy++;
s3->accel.dy++;
s3->accel.dy &= 0xfff;
s3->accel.src = s3->accel.cy * s3->width;
s3->accel.dest = s3->accel.dy * s3->width;
s3->accel.sy--;
if (s3->accel.sy < 0) { /*It's evident that this is a clear undocumented difference compared to later chips, per what NT 3.5+ does to DX/DY.*/
s3->accel.destx_distp = s3->accel.dx;
s3->accel.desty_axstp = s3->accel.dy;
return;
}
}
}
} else {
while (count-- && s3->accel.sy >= 0) {
if ((s3->accel.dx & 0xfff) >= clip_l && (s3->accel.dx & 0xfff) <= clip_r && ((s3->accel.dy & 0xfff) >= clip_t && (s3->accel.dy & 0xfff) <= clip_b)) {
if (vram_mask && (s3->accel.cmd & 0x10)) {
READ(s3->accel.src + s3->accel.cx - s3->accel.srcminus, mix_dat);
mix_dat = ((mix_dat & rd_mask) == rd_mask);
mix_dat = mix_dat ? mix_mask : 0;
}
switch ((mix_dat & mix_mask) ? frgd_mix : bkgd_mix) {
case 0:
src_dat = bkgd_color;
if (s3->color_16bit && (svga->bpp < 24)) {
if (!s3->accel.color_16bit_check)
src_dat = s3->accel.bkgd_color_actual[0] | (s3->accel.bkgd_color_actual[1] << 8);
}
break;
case 1:
src_dat = frgd_color;
if (s3->color_16bit && (svga->bpp < 24)) {
if (!s3->accel.color_16bit_check)
src_dat = s3->accel.frgd_color_actual[0] | (s3->accel.frgd_color_actual[1] << 8);
}
break;
case 2:
src_dat = cpu_dat;
break;
case 3:
READ(s3->accel.src + s3->accel.cx - s3->accel.srcminus, src_dat);
if (vram_mask && (s3->accel.cmd & 0x10))
src_dat = ((src_dat & rd_mask) == rd_mask);
break;
default:
break;
}
READ(s3->accel.dest + s3->accel.dx - s3->accel.minus, dest_dat);
MIX
if ((!(s3->accel.cmd & 0x10) && vram_mask) || (s3->accel.cmd & 0x10)) {
WRITE(s3->accel.dest + s3->accel.dx - s3->accel.minus, dest_dat);
}
}
mix_dat <<= 1;
mix_dat |= 1;
if (s3->color_16bit)
cpu_dat >>= 16;
else
cpu_dat >>= 8;
if (s3->accel.cmd & 0x20) {
s3->accel.cx++;
s3->accel.dx++;
} else {
s3->accel.cx--;
s3->accel.dx--;
}
s3->accel.dx &= 0xfff;
s3->accel.sx--;
if (s3->accel.sx < 0) {
if (s3->accel.cmd & 0x20) {
s3->accel.cx -= ((s3->accel.maj_axis_pcnt & 0xfff) + 1);
s3->accel.dx -= ((s3->accel.maj_axis_pcnt & 0xfff) + 1);
} else {
s3->accel.cx += ((s3->accel.maj_axis_pcnt & 0xfff) + 1);
s3->accel.dx += ((s3->accel.maj_axis_pcnt & 0xfff) + 1);
}
s3->accel.sx = s3->accel.maj_axis_pcnt & 0xfff;
if (s3->accel.cmd & 0x80) {
s3->accel.cy++;
s3->accel.dy++;
} else {
s3->accel.cy--;
s3->accel.dy--;
}
s3->accel.dy &= 0xfff;
s3->accel.src = s3->accel.cy * s3->width;
s3->accel.dest = s3->accel.dy * s3->width;
s3->accel.sy--;
if (cpu_input)
return;
if (s3->accel.sy < 0) { /*It's evident that this is a clear undocumented difference compared to later chips, per what NT 3.5+ does to DX/DY.*/
s3->accel.destx_distp = s3->accel.dx;
s3->accel.desty_axstp = s3->accel.dy;
return;
}
}
}
}
break;
default:
break;
}
}
void
s3_short_stroke_start(int count, int cpu_input, uint32_t mix_dat, uint32_t cpu_dat, s3_t *s3, uint8_t ssv)
{
if (!cpu_input) {
s3->accel.ssv_len = ssv & 0x0f;
s3->accel.ssv_dir = ssv & 0xe0;
s3->accel.ssv_draw = ssv & 0x10;
if (s3_cpu_src(s3)) {
return; /*Wait for data from CPU*/
}
}
s3->accel_start(count, cpu_input, mix_dat, cpu_dat, s3);
}
void
s3_accel_start(int count, int cpu_input, uint32_t mix_dat, uint32_t cpu_dat, void *priv)
{
s3_t *s3 = (s3_t *)priv;
svga_t *svga = &s3->svga;
uint32_t src_dat = 0;
uint32_t dest_dat;
uint32_t old_dest_dat;
uint32_t out;
uint32_t pat_dat = 0;
int frgd_mix;
int bkgd_mix;
int clip_t = s3->accel.multifunc[1] & 0xfff;
int clip_l = s3->accel.multifunc[2] & 0xfff;
int clip_b = s3->accel.multifunc[3] & 0xfff;
int clip_r = s3->accel.multifunc[4] & 0xfff;
int vram_mask = (s3->accel.multifunc[0xa] & 0xc0) == 0xc0;
uint32_t mix_mask = 0;
uint16_t *vram_w = (uint16_t *) svga->vram;
uint32_t *vram_l = (uint32_t *) svga->vram;
uint32_t compare = s3->accel.color_cmp;
uint8_t rop = s3->accel.ropmix & 0xff;
int compare_mode = (s3->accel.multifunc[0xe] >> 7) & 3;
uint32_t rd_mask = s3->accel.rd_mask;
uint32_t wrt_mask = s3->accel.wrt_mask;
uint32_t frgd_color = s3->accel.frgd_color;
uint32_t bkgd_color = s3->accel.bkgd_color;
int cmd = s3->accel.cmd >> 13;
uint32_t srcbase;
uint32_t dstbase;
s3->accel.srcminus = 0;
s3->accel.minus = 0;
if ((s3->chip >= S3_TRIO64 || s3->chip == S3_VISION968 || s3->chip == S3_VISION868) && (s3->accel.cmd & (1 << 11)))
cmd |= 8;
// SRC-BASE/DST-BASE
if ((s3->accel.multifunc[0xd] >> 4) & 7)
srcbase = 0x100000 * ((s3->accel.multifunc[0xd] >> 4) & 3);
else
srcbase = 0x100000 * ((s3->accel.multifunc[0xe] >> 2) & 3);
if ((s3->accel.multifunc[0xd] >> 0) & 7)
dstbase = 0x100000 * ((s3->accel.multifunc[0xd] >> 0) & 3);
else
dstbase = 0x100000 * ((s3->accel.multifunc[0xe] >> 0) & 3);
if ((s3->bpp == 1) || s3->color_16bit) {
srcbase >>= 1;
dstbase >>= 1;
} else if (s3->bpp == 3) {
srcbase >>= 2;
dstbase >>= 2;
}
if ((s3->accel.cmd & 0x100) && (s3_cpu_src(s3) || (s3_cpu_dest(s3))) && (!cpu_input || (s3_enable_fifo(s3) == 0)))
s3->force_busy = 1;
if (!cpu_input)
s3->accel.dat_count = 0;
if (cpu_input && (((s3->accel.multifunc[0xa] & 0xc0) != 0x80) || (!(s3->accel.cmd & 2)))) {
if ((s3->bpp == 3) && (count == 2)) {
if (s3->accel.dat_count) {
cpu_dat = ((cpu_dat & 0xffff) << 16) | s3->accel.dat_buf;
count = 4;
s3->accel.dat_count = 0;
} else {
s3->accel.dat_buf = cpu_dat & 0xffff;
s3->accel.dat_count = 1;
}
}
if ((s3->bpp == 1) || s3->color_16bit)
count >>= 1;
else if (s3->bpp == 3)
count >>= 2;
}
if ((s3->bpp == 0) && !s3->color_16bit)
rd_mask &= 0xff;
else if ((s3->bpp == 1) || s3->color_16bit)
rd_mask &= 0xffff;
if (s3->bpp == 0)
compare &= 0xff;
else if (s3->bpp == 1)
compare &= 0xffff;
switch (s3->accel.cmd & 0x600) {
case 0x000:
mix_mask = 0x80;
break;
case 0x200:
mix_mask = 0x8000;
break;
case 0x400:
mix_mask = 0x80000000;
break;
case 0x600:
mix_mask = (s3->chip == S3_TRIO32 || s3->chip >= S3_TRIO64V || s3->chip == S3_VISION968 || s3->chip == S3_VISION868) ? 0x80 : 0x80000000;
break;
default:
break;
}
/*Bit 4 of the Command register is the draw yes bit, which enables writing to memory/reading from memory when enabled.
When this bit is disabled, no writing to memory/reading from memory is allowed. (This bit is almost meaningless on
the NOP command)*/
switch (cmd) {
case 0: /*NOP (Short Stroke Vectors)*/
if (s3->accel.ssv_state == 0)
break;
frgd_mix = (s3->accel.frgd_mix >> 5) & 3;
bkgd_mix = (s3->accel.bkgd_mix >> 5) & 3;
if (s3->accel.cmd & 8) /*Radial*/
{
while (count-- && s3->accel.ssv_len >= 0) {
if ((s3->accel.cx & 0xfff) >= clip_l && (s3->accel.cx & 0xfff) <= clip_r && (s3->accel.cy & 0xfff) >= clip_t && (s3->accel.cy & 0xfff) <= clip_b) {
switch ((mix_dat & mix_mask) ? frgd_mix : bkgd_mix) {
case 0:
src_dat = bkgd_color;
break;
case 1:
src_dat = frgd_color;
break;
case 2:
src_dat = cpu_dat;
break;
case 3:
src_dat = 0;
break;
default:
break;
}
if ((compare_mode == 2 && src_dat != compare) || (compare_mode == 3 && src_dat == compare) || compare_mode < 2) {
READ((s3->accel.cy * s3->width) + s3->accel.cx, dest_dat);
MIX
if (s3->accel.ssv_draw) {
WRITE((s3->accel.cy * s3->width) + s3->accel.cx, dest_dat);
}
}
}
mix_dat <<= 1;
mix_dat |= 1;
if (s3->bpp == 0 && !s3->color_16bit)
cpu_dat >>= 8;
else
cpu_dat >>= 16;
if (!s3->accel.ssv_len)
break;
switch (s3->accel.ssv_dir & 0xe0) {
case 0x00:
s3->accel.cx++;
break;
case 0x20:
s3->accel.cx++;
s3->accel.cy--;
break;
case 0x40:
s3->accel.cy--;
break;
case 0x60:
s3->accel.cx--;
s3->accel.cy--;
break;
case 0x80:
s3->accel.cx--;
break;
case 0xa0:
s3->accel.cx--;
s3->accel.cy++;
break;
case 0xc0:
s3->accel.cy++;
break;
case 0xe0:
s3->accel.cx++;
s3->accel.cy++;
break;
default:
break;
}
s3->accel.ssv_len--;
s3->accel.cx &= 0xfff;
s3->accel.cy &= 0xfff;
}
s3->accel.cur_x = s3->accel.cx & 0xfff;
s3->accel.cur_y = s3->accel.cy & 0xfff;
}
break;
case 1: /*Draw line*/
if (!cpu_input) {
s3->accel.cx = s3->accel.cur_x & 0xfff;
s3->accel.cy = s3->accel.cur_y & 0xfff;
s3->accel.sy = s3->accel.maj_axis_pcnt;
if (s3_cpu_src(s3))
return; /*Wait for data from CPU*/
}
frgd_mix = (s3->accel.frgd_mix >> 5) & 3;
bkgd_mix = (s3->accel.bkgd_mix >> 5) & 3;
if (s3->accel.cmd & 8) { /*Radial*/
while (count-- && s3->accel.sy >= 0) {
if ((s3->accel.cx & 0xfff) >= clip_l && (s3->accel.cx & 0xfff) <= clip_r && (s3->accel.cy & 0xfff) >= clip_t && (s3->accel.cy & 0xfff) <= clip_b) {
switch ((mix_dat & mix_mask) ? frgd_mix : bkgd_mix) {
case 0:
src_dat = bkgd_color;
break;
case 1:
src_dat = frgd_color;
break;
case 2:
src_dat = cpu_dat;
break;
case 3:
src_dat = 0;
break;
default:
break;
}
if ((compare_mode == 2 && src_dat != compare) || (compare_mode == 3 && src_dat == compare) || compare_mode < 2) {
READ((s3->accel.cy * s3->width) + s3->accel.cx, dest_dat);
MIX
WRITE((s3->accel.cy * s3->width) + s3->accel.cx, dest_dat);
}
}
mix_dat <<= 1;
mix_dat |= 1;
if ((s3->bpp == 0) && !s3->color_16bit)
cpu_dat >>= 8;
else
cpu_dat >>= 16;
if (!s3->accel.sy)
break;
switch (s3->accel.cmd & 0xe0) {
case 0x00:
s3->accel.cx++;
break;
case 0x20:
s3->accel.cx++;
s3->accel.cy--;
break;
case 0x40:
s3->accel.cy--;
break;
case 0x60:
s3->accel.cx--;
s3->accel.cy--;
break;
case 0x80:
s3->accel.cx--;
break;
case 0xa0:
s3->accel.cx--;
s3->accel.cy++;
break;
case 0xc0:
s3->accel.cy++;
break;
case 0xe0:
s3->accel.cx++;
s3->accel.cy++;
break;
default:
break;
}
s3->accel.sy--;
s3->accel.cx &= 0xfff;
s3->accel.cy &= 0xfff;
}
s3->accel.cur_x = s3->accel.cx & 0xfff;
s3->accel.cur_y = s3->accel.cy & 0xfff;
} else { /*Bresenham*/
if (s3->accel.b2e8_pix && s3_cpu_src(s3) && (count == 16)) { /*Stupid undocumented 0xB2E8 on 911/924*/
count = s3->accel.maj_axis_pcnt + 1;
s3->accel.temp_cnt = 16;
}
while (count-- && s3->accel.sy >= 0) {
if (s3->accel.b2e8_pix && s3_cpu_src(s3) && !s3->accel.temp_cnt) {
mix_dat >>= 16;
s3->accel.temp_cnt = 16;
}
if ((s3->accel.cx & 0xfff) >= clip_l && (s3->accel.cx & 0xfff) <= clip_r && (s3->accel.cy & 0xfff) >= clip_t && (s3->accel.cy & 0xfff) <= clip_b) {
switch ((mix_dat & mix_mask) ? frgd_mix : bkgd_mix) {
case 0:
src_dat = bkgd_color;
break;
case 1:
src_dat = frgd_color;
break;
case 2:
src_dat = cpu_dat;
break;
case 3:
src_dat = 0;
break;
default:
break;
}
if ((compare_mode == 2 && src_dat != compare) || (compare_mode == 3 && src_dat == compare) || compare_mode < 2) {
READ((s3->accel.cy * s3->width) + s3->accel.cx, dest_dat);
MIX
WRITE((s3->accel.cy * s3->width) + s3->accel.cx, dest_dat);
}
}
if (s3->accel.b2e8_pix && s3_cpu_src(s3)) {
if (s3->accel.temp_cnt > 0) {
s3->accel.temp_cnt--;
mix_dat <<= 1;
mix_dat |= 1;
}
} else {
mix_dat <<= 1;
mix_dat |= 1;
}
if (s3->bpp == 0 && !s3->color_16bit)
cpu_dat >>= 8;
else
cpu_dat >>= 16;
if (!s3->accel.sy)
break;
if (s3->accel.cmd & 0x40) {
if (s3->accel.cmd & 0x80)
s3->accel.cy++;
else
s3->accel.cy--;
if (s3->accel.err_term >= 0) {
s3->accel.err_term += s3->accel.destx_distp;
if (s3->accel.cmd & 0x20)
s3->accel.cx++;
else
s3->accel.cx--;
} else
s3->accel.err_term += s3->accel.desty_axstp;
} else {
if (s3->accel.cmd & 0x20)
s3->accel.cx++;
else
s3->accel.cx--;
if (s3->accel.err_term >= 0) {
s3->accel.err_term += s3->accel.destx_distp;
if (s3->accel.cmd & 0x80)
s3->accel.cy++;
else
s3->accel.cy--;
} else
s3->accel.err_term += s3->accel.desty_axstp;
}
s3->accel.sy--;
s3->accel.cx &= 0xfff;
s3->accel.cy &= 0xfff;
}
s3->accel.cur_x = s3->accel.cx & 0xfff;
s3->accel.cur_y = s3->accel.cy & 0xfff;
}
break;
case 2: /*Rectangle fill*/
if (!cpu_input) /*!cpu_input is trigger to start operation*/
{
s3->accel.sx = s3->accel.maj_axis_pcnt & 0xfff;
s3->accel.sy = s3->accel.multifunc[0] & 0xfff;
s3->accel.cx = s3->accel.cur_x & 0xfff;
s3->accel.cy = s3->accel.cur_y & 0xfff;
s3->accel.dest = dstbase + s3->accel.cy * s3->width;
if (s3_cpu_src(s3)) {
s3->data_available = 0;
return; /*Wait for data from CPU*/
} else if (s3_cpu_dest(s3)) {
s3->data_available = 1;
return;
}
}
frgd_mix = (s3->accel.frgd_mix >> 5) & 3;
bkgd_mix = (s3->accel.bkgd_mix >> 5) & 3;
if (s3->accel.b2e8_pix && s3_cpu_src(s3) && count == 16) { /*Stupid undocumented 0xB2E8 on 911/924*/
count = s3->accel.maj_axis_pcnt + 1;
s3->accel.temp_cnt = 16;
}
while (count-- && s3->accel.sy >= 0) {
if (s3->accel.b2e8_pix && s3_cpu_src(s3) && s3->accel.temp_cnt == 0) {
mix_dat >>= 16;
s3->accel.temp_cnt = 16;
}
if ((s3->accel.cx & 0xfff) >= clip_l && (s3->accel.cx & 0xfff) <= clip_r && (s3->accel.cy & 0xfff) >= clip_t && (s3->accel.cy & 0xfff) <= clip_b) {
if (s3_cpu_dest(s3) && ((s3->accel.multifunc[0xa] & 0xc0) == 0x00)) {
mix_dat = mix_mask; /* Mix data = forced to foreground register. */
} else if (s3_cpu_dest(s3) && vram_mask) {
/* Mix data = current video memory value. */
READ(s3->accel.dest + s3->accel.cx, mix_dat);
mix_dat = ((mix_dat & rd_mask) == rd_mask);
mix_dat = mix_dat ? mix_mask : 0;
}
if (s3_cpu_dest(s3)) {
READ(s3->accel.dest + s3->accel.cx, src_dat);
if (vram_mask)
src_dat = ((src_dat & rd_mask) == rd_mask);
} else {
switch ((mix_dat & mix_mask) ? frgd_mix : bkgd_mix) {
case 0:
src_dat = bkgd_color;
break;
case 1:
src_dat = frgd_color;
break;
case 2:
src_dat = cpu_dat;
break;
case 3:
src_dat = 0;
break;
default:
break;
}
}
if ((compare_mode == 2 && src_dat != compare) || (compare_mode == 3 && src_dat == compare) || compare_mode < 2) {
READ(s3->accel.dest + s3->accel.cx, dest_dat);
MIX
if (s3->accel.cmd & 0x10) {
WRITE(s3->accel.dest + s3->accel.cx, dest_dat);
}
}
}
if (s3->accel.b2e8_pix && s3_cpu_src(s3)) {
if (s3->accel.temp_cnt > 0) {
s3->accel.temp_cnt--;
mix_dat <<= 1;
mix_dat |= 1;
}
} else {
mix_dat <<= 1;
mix_dat |= 1;
}
if (s3->bpp == 0 && !s3->color_16bit)
cpu_dat >>= 8;
else
cpu_dat >>= 16;
if (s3->accel.cmd & 0x20)
s3->accel.cx++;
else
s3->accel.cx--;
s3->accel.cx &= 0xfff;
s3->accel.sx--;
if (s3->accel.sx < 0) {
if (s3->accel.cmd & 0x20)
s3->accel.cx -= (s3->accel.maj_axis_pcnt & 0xfff) + 1;
else
s3->accel.cx += (s3->accel.maj_axis_pcnt & 0xfff) + 1;
s3->accel.sx = s3->accel.maj_axis_pcnt & 0xfff;
if (s3->accel.cmd & 0x80)
s3->accel.cy++;
else
s3->accel.cy--;
s3->accel.cy &= 0xfff;
s3->accel.dest = dstbase + s3->accel.cy * s3->width;
s3->accel.sy--;
if (cpu_input) {
if (s3->accel.b2e8_pix) {
s3->accel.cur_x = s3->accel.cx;
s3->accel.cur_y = s3->accel.cy;
}
return;
}
if (s3->accel.sy < 0) {
s3->accel.cur_x = s3->accel.cx;
s3->accel.cur_y = s3->accel.cy;
return;
}
}
}
break;
case 3: /*Polygon Fill Solid (Vision868/968 and Trio64 only)*/
{
int end_y1;
int end_y2;
if (s3->chip != S3_TRIO64 && s3->chip != S3_VISION968 && s3->chip != S3_VISION868)
break;
polygon_setup(s3);
if ((s3->accel.cmd & 0x100) && !cpu_input)
return; /*Wait for data from CPU*/
end_y1 = s3->accel.desty_axstp;
end_y2 = s3->accel.desty_axstp2;
frgd_mix = (s3->accel.frgd_mix >> 5) & 3;
while ((s3->accel.poly_cy < end_y1) && (s3->accel.poly_cy2 < end_y2)) {
int y = s3->accel.poly_cy;
int x_count = ABS((s3->accel.poly_cx2 >> 20) - s3->accel.poly_x) + 1;
s3->accel.dest = dstbase + y * s3->width;
while (x_count-- && count--) {
if ((s3->accel.poly_x & 0xfff) >= clip_l && (s3->accel.poly_x & 0xfff) <= clip_r && (s3->accel.poly_cy & 0xfff) >= clip_t && (s3->accel.poly_cy & 0xfff) <= clip_b) {
switch (frgd_mix) {
case 0:
src_dat = s3->accel.bkgd_color;
break;
case 1:
src_dat = s3->accel.frgd_color;
break;
case 2:
src_dat = cpu_dat;
break;
case 3:
src_dat = 0; /*Not supported?*/
break;
default:
break;
}
if ((compare_mode == 2 && src_dat != compare) || (compare_mode == 3 && src_dat == compare) || compare_mode < 2) {
READ(s3->accel.dest + s3->accel.poly_x, dest_dat);
MIX
if (s3->accel.cmd & 0x10) {
WRITE(s3->accel.dest + s3->accel.poly_x, dest_dat);
}
}
}
if (s3->bpp == 0)
cpu_dat >>= 8;
else
cpu_dat >>= 16;
if (s3->accel.poly_x < (s3->accel.poly_cx2 >> 20))
s3->accel.poly_x++;
else
s3->accel.poly_x--;
}
s3->accel.poly_cx += s3->accel.poly_dx1;
s3->accel.poly_cx2 += s3->accel.poly_dx2;
s3->accel.poly_x = s3->accel.poly_cx >> 20;
s3->accel.poly_cy++;
s3->accel.poly_cy2++;
if (!count)
break;
}
s3->accel.cur_x = s3->accel.poly_cx & 0xfff;
s3->accel.cur_y = s3->accel.poly_cy & 0xfff;
s3->accel.cur_x2 = s3->accel.poly_cx2 & 0xfff;
s3->accel.cur_y2 = s3->accel.poly_cy & 0xfff;
}
break;
case 6: /*BitBlt*/
if (!cpu_input) { /*!cpu_input is trigger to start operation*/
s3->accel.sx = s3->accel.maj_axis_pcnt & 0xfff;
s3->accel.sy = s3->accel.multifunc[0] & 0xfff;
s3->accel.dx = s3->accel.destx_distp & 0xfff;
s3->accel.dy = s3->accel.desty_axstp & 0xfff;
s3->accel.cx = s3->accel.cur_x & 0xfff;
s3->accel.cy = s3->accel.cur_y & 0xfff;
s3->accel.src = srcbase + s3->accel.cy * s3->width;
s3->accel.dest = dstbase + s3->accel.dy * s3->width;
}
if ((s3->accel.cmd & 0x100) && !cpu_input) {
return; /*Wait for data from CPU*/
}
frgd_mix = (s3->accel.frgd_mix >> 5) & 3;
bkgd_mix = (s3->accel.bkgd_mix >> 5) & 3;
if (!cpu_input && frgd_mix == 3 && !vram_mask && !compare_mode && (s3->accel.cmd & 0xa0) == 0xa0 && (s3->accel.frgd_mix & 0xf) == 7 && (s3->accel.bkgd_mix & 0xf) == 7) {
while (1) {
if ((s3->accel.dx & 0xfff) >= clip_l && (s3->accel.dx & 0xfff) <= clip_r && (s3->accel.dy & 0xfff) >= clip_t && (s3->accel.dy & 0xfff) <= clip_b) {
READ(s3->accel.src + s3->accel.cx, src_dat);
READ(s3->accel.dest + s3->accel.dx, dest_dat);
dest_dat = (src_dat & wrt_mask) | (dest_dat & ~wrt_mask);
WRITE(s3->accel.dest + s3->accel.dx, dest_dat);
}
s3->accel.cx++;
s3->accel.dx++;
s3->accel.sx--;
s3->accel.dx &= 0xfff;
if (s3->accel.sx < 0) {
s3->accel.cx -= (s3->accel.maj_axis_pcnt & 0xfff) + 1;
s3->accel.dx -= (s3->accel.maj_axis_pcnt & 0xfff) + 1;
s3->accel.sx = s3->accel.maj_axis_pcnt & 0xfff;
s3->accel.cy++;
s3->accel.dy++;
s3->accel.dy &= 0xfff;
s3->accel.src = srcbase + s3->accel.cy * s3->width;
s3->accel.dest = dstbase + s3->accel.dy * s3->width;
s3->accel.sy--;
if (s3->accel.sy < 0) {
s3->accel.destx_distp = s3->accel.dx;
s3->accel.desty_axstp = s3->accel.dy;
return;
}
}
}
} else {
while (count-- && s3->accel.sy >= 0) {
if ((s3->accel.dx & 0xfff) >= clip_l && (s3->accel.dx & 0xfff) <= clip_r && ((s3->accel.dy & 0xfff) >= clip_t && (s3->accel.dy & 0xfff) <= clip_b)) {
if (vram_mask && (s3->accel.cmd & 0x10)) {
READ(s3->accel.src + s3->accel.cx, mix_dat);
mix_dat = ((mix_dat & rd_mask) == rd_mask);
mix_dat = mix_dat ? mix_mask : 0;
}
switch ((mix_dat & mix_mask) ? frgd_mix : bkgd_mix) {
case 0:
src_dat = bkgd_color;
break;
case 1:
src_dat = frgd_color;
break;
case 2:
src_dat = cpu_dat;
break;
case 3:
READ(s3->accel.src + s3->accel.cx, src_dat);
if (vram_mask && (s3->accel.cmd & 0x10))
src_dat = ((src_dat & rd_mask) == rd_mask);
break;
default:
break;
}
if ((compare_mode == 2 && src_dat != compare) || (compare_mode == 3 && src_dat == compare) || compare_mode < 2) {
READ(s3->accel.dest + s3->accel.dx, dest_dat);
MIX
if ((!(s3->accel.cmd & 0x10) && vram_mask) || (s3->accel.cmd & 0x10)) {
WRITE(s3->accel.dest + s3->accel.dx, dest_dat);
}
}
}
mix_dat <<= 1;
mix_dat |= 1;
if (s3->bpp == 0 && !s3->color_16bit)
cpu_dat >>= 8;
else
cpu_dat >>= 16;
if (s3->accel.cmd & 0x20) {
s3->accel.cx++;
s3->accel.dx++;
} else {
s3->accel.cx--;
s3->accel.dx--;
}
s3->accel.dx &= 0xfff;
s3->accel.sx--;
if (s3->accel.sx < 0) {
if (s3->accel.cmd & 0x20) {
s3->accel.cx -= ((s3->accel.maj_axis_pcnt & 0xfff) + 1);
s3->accel.dx -= ((s3->accel.maj_axis_pcnt & 0xfff) + 1);
} else {
s3->accel.cx += ((s3->accel.maj_axis_pcnt & 0xfff) + 1);
s3->accel.dx += ((s3->accel.maj_axis_pcnt & 0xfff) + 1);
}
s3->accel.sx = s3->accel.maj_axis_pcnt & 0xfff;
if (s3->accel.cmd & 0x80) {
s3->accel.cy++;
s3->accel.dy++;
} else {
s3->accel.cy--;
s3->accel.dy--;
}
s3->accel.dy &= 0xfff;
s3->accel.src = srcbase + s3->accel.cy * s3->width;
s3->accel.dest = dstbase + s3->accel.dy * s3->width;
s3->accel.sy--;
if (cpu_input)
return;
if (s3->accel.sy < 0) {
s3->accel.destx_distp = s3->accel.dx;
s3->accel.desty_axstp = s3->accel.dy;
return;
}
}
}
}
break;
case 7: /*Pattern fill - BitBlt but with source limited to 8x8*/
if (!cpu_input) /*!cpu_input is trigger to start operation*/
{
s3->accel.sx = s3->accel.maj_axis_pcnt & 0xfff;
s3->accel.sy = s3->accel.multifunc[0] & 0xfff;
s3->accel.dx = s3->accel.destx_distp & 0xfff;
s3->accel.dy = s3->accel.desty_axstp & 0xfff;
s3->accel.cx = s3->accel.cur_x & 0xfff;
s3->accel.cy = s3->accel.cur_y & 0xfff;
/*Align source with destination*/
s3->accel.pattern = (s3->accel.cy * s3->width) + s3->accel.cx;
s3->accel.dest = dstbase + s3->accel.dy * s3->width;
s3->accel.cx = s3->accel.dx & 7;
s3->accel.cy = s3->accel.dy & 7;
s3->accel.src = srcbase + s3->accel.pattern + (s3->accel.cy * s3->width);
}
if ((s3->accel.cmd & 0x100) && !cpu_input) {
return; /*Wait for data from CPU*/
}
frgd_mix = (s3->accel.frgd_mix >> 5) & 3;
bkgd_mix = (s3->accel.bkgd_mix >> 5) & 3;
while (count-- && s3->accel.sy >= 0) {
if ((s3->accel.dx & 0xfff) >= clip_l && (s3->accel.dx & 0xfff) <= clip_r && (s3->accel.dy & 0xfff) >= clip_t && (s3->accel.dy & 0xfff) <= clip_b) {
if (vram_mask) {
READ(s3->accel.src + s3->accel.cx, mix_dat);
mix_dat = ((mix_dat & rd_mask) == rd_mask);
mix_dat = mix_dat ? mix_mask : 0;
}
switch ((mix_dat & mix_mask) ? frgd_mix : bkgd_mix) {
case 0:
src_dat = s3->accel.bkgd_color;
break;
case 1:
src_dat = s3->accel.frgd_color;
break;
case 2:
src_dat = cpu_dat;
break;
case 3:
READ(s3->accel.src + s3->accel.cx, src_dat);
if (vram_mask)
src_dat = ((src_dat & rd_mask) == rd_mask);
break;
default:
break;
}
if ((compare_mode == 2 && src_dat != compare) || (compare_mode == 3 && src_dat == compare) || compare_mode < 2) {
READ(s3->accel.dest + s3->accel.dx, dest_dat);
MIX
if (s3->accel.cmd & 0x10) {
WRITE(s3->accel.dest + s3->accel.dx, dest_dat);
}
}
}
mix_dat <<= 1;
mix_dat |= 1;
if (s3->bpp == 0 && !s3->color_16bit)
cpu_dat >>= 8;
else
cpu_dat >>= 16;
if (s3->accel.cmd & 0x20) {
s3->accel.cx = ((s3->accel.cx + 1) & 7) | (s3->accel.cx & ~7);
s3->accel.dx++;
} else {
s3->accel.cx = ((s3->accel.cx - 1) & 7) | (s3->accel.cx & ~7);
s3->accel.dx--;
}
s3->accel.dx &= 0xfff;
s3->accel.sx--;
if (s3->accel.sx < 0) {
if (s3->accel.cmd & 0x20) {
s3->accel.cx = ((s3->accel.cx - (((s3->accel.maj_axis_pcnt & 0xfff) + 1))) & 7) | (s3->accel.cx & ~7);
s3->accel.dx -= ((s3->accel.maj_axis_pcnt & 0xfff) + 1);
} else {
s3->accel.cx = ((s3->accel.cx + (((s3->accel.maj_axis_pcnt & 0xfff) + 1))) & 7) | (s3->accel.cx & ~7);
s3->accel.dx += ((s3->accel.maj_axis_pcnt & 0xfff) + 1);
}
s3->accel.sx = s3->accel.maj_axis_pcnt & 0xfff;
if (s3->accel.cmd & 0x80) {
s3->accel.cy = ((s3->accel.cy + 1) & 7) | (s3->accel.cy & ~7);
s3->accel.dy++;
} else {
s3->accel.cy = ((s3->accel.cy - 1) & 7) | (s3->accel.cy & ~7);
s3->accel.dy--;
}
s3->accel.dy &= 0xfff;
s3->accel.src = srcbase + s3->accel.pattern + (s3->accel.cy * s3->width);
s3->accel.dest = dstbase + s3->accel.dy * s3->width;
s3->accel.sy--;
if (cpu_input) {
return;
}
if (s3->accel.sy < 0) {
s3->accel.destx_distp = s3->accel.dx;
s3->accel.desty_axstp = s3->accel.dy;
return;
}
}
}
break;
case 9: /*Polyline/2-Point Line (Vision868/968 and Trio64 only)*/
{
int error;
if (s3->chip != S3_TRIO64 && s3->chip != S3_VISION968 && s3->chip != S3_VISION868)
break;
if (!cpu_input) {
s3->accel.dx = ABS(s3->accel.destx_distp - s3->accel.cur_x);
if (s3->accel.destx_distp & 0x1000)
s3->accel.dx |= ~0xfff;
s3->accel.dy = ABS(s3->accel.desty_axstp - s3->accel.cur_y);
if (s3->accel.desty_axstp & 0x1000)
s3->accel.dy |= ~0xfff;
s3->accel.cx = s3->accel.cur_x & 0xfff;
s3->accel.cy = s3->accel.cur_y & 0xfff;
}
if ((s3->accel.cmd & 0x100) && !cpu_input)
return; /*Wait for data from CPU*/
if (s3->accel.dx > s3->accel.dy) {
error = s3->accel.dx / 2;
while (s3->accel.cx != s3->accel.destx_distp && count--) {
if ((s3->accel.cx & 0xfff) >= clip_l && (s3->accel.cx & 0xfff) <= clip_r && (s3->accel.cy & 0xfff) >= clip_t && (s3->accel.cy & 0xfff) <= clip_b) {
src_dat = s3->accel.frgd_color;
if (((compare_mode == 2 && src_dat != compare) || (compare_mode == 3 && src_dat == compare) || compare_mode < 2) && (s3->accel.cmd & 0x10)) {
READ((s3->accel.cy * s3->width) + s3->accel.cx, dest_dat);
MIX
if (s3->accel.cmd & 0x10) {
WRITE((s3->accel.cy * s3->width) + s3->accel.cx, dest_dat);
}
}
}
error -= s3->accel.dy;
if (error < 0) {
error += s3->accel.dx;
if (s3->accel.desty_axstp > s3->accel.cur_y)
s3->accel.cy++;
else
s3->accel.cy--;
s3->accel.cy &= 0xfff;
}
if (s3->accel.destx_distp > s3->accel.cur_x)
s3->accel.cx++;
else
s3->accel.cx--;
s3->accel.cx &= 0xfff;
}
} else {
error = s3->accel.dy / 2;
while (s3->accel.cy != s3->accel.desty_axstp && count--) {
if ((s3->accel.cx & 0xfff) >= clip_l && (s3->accel.cx & 0xfff) <= clip_r && (s3->accel.cy & 0xfff) >= clip_t && (s3->accel.cy & 0xfff) <= clip_b) {
src_dat = s3->accel.frgd_color;
if ((compare_mode == 2 && src_dat != compare) || (compare_mode == 3 && src_dat == compare) || compare_mode < 2) {
READ((s3->accel.cy * s3->width) + s3->accel.cx, dest_dat);
MIX
if (s3->accel.cmd & 0x10) {
WRITE((s3->accel.cy * s3->width) + s3->accel.cx, dest_dat);
}
}
}
error -= s3->accel.dx;
if (error < 0) {
error += s3->accel.dy;
if (s3->accel.destx_distp > s3->accel.cur_x)
s3->accel.cx++;
else
s3->accel.cx--;
s3->accel.cx &= 0xfff;
}
if (s3->accel.desty_axstp > s3->accel.cur_y)
s3->accel.cy++;
else
s3->accel.cy--;
s3->accel.cy &= 0xfff;
}
}
s3->accel.cur_x = s3->accel.cx;
s3->accel.cur_y = s3->accel.cy;
}
break;
case 11: /*Polygon Fill Pattern (Vision868/968 and Trio64 only)*/
{
int end_y1;
int end_y2;
if (s3->chip != S3_TRIO64 && s3->chip != S3_VISION968 && s3->chip != S3_VISION868)
break;
polygon_setup(s3);
if ((s3->accel.cmd & 0x100) && !cpu_input)
return; /*Wait for data from CPU*/
end_y1 = s3->accel.desty_axstp;
end_y2 = s3->accel.desty_axstp2;
frgd_mix = (s3->accel.frgd_mix >> 5) & 3;
bkgd_mix = (s3->accel.bkgd_mix >> 5) & 3;
while ((s3->accel.poly_cy < end_y1) && (s3->accel.poly_cy2 < end_y2)) {
int y = s3->accel.poly_cy;
int x_count = ABS((s3->accel.poly_cx2 >> 20) - s3->accel.poly_x) + 1;
s3->accel.src = srcbase + s3->accel.pattern + ((y & 7) * s3->width);
s3->accel.dest = dstbase + y * s3->width;
while (x_count-- && count--) {
int pat_x = s3->accel.poly_x & 7;
if ((s3->accel.poly_x & 0xfff) >= clip_l && (s3->accel.poly_x & 0xfff) <= clip_r && (s3->accel.poly_cy & 0xfff) >= clip_t && (s3->accel.poly_cy & 0xfff) <= clip_b) {
if (vram_mask) {
READ(s3->accel.src + pat_x, mix_dat);
mix_dat = ((mix_dat & rd_mask) == rd_mask);
mix_dat = mix_dat ? mix_mask : 0;
}
switch ((mix_dat & mix_mask) ? frgd_mix : bkgd_mix) {
case 0:
src_dat = s3->accel.bkgd_color;
break;
case 1:
src_dat = s3->accel.frgd_color;
break;
case 2:
src_dat = cpu_dat;
break;
case 3:
READ(s3->accel.src + pat_x, src_dat);
if (vram_mask)
src_dat = ((src_dat & rd_mask) == rd_mask);
break;
default:
break;
}
if ((compare_mode == 2 && src_dat != compare) || (compare_mode == 3 && src_dat == compare) || compare_mode < 2) {
READ(s3->accel.dest + s3->accel.poly_x, dest_dat);
MIX
if (s3->accel.cmd & 0x10) {
WRITE(s3->accel.dest + s3->accel.poly_x, dest_dat);
}
}
}
if (s3->bpp == 0)
cpu_dat >>= 8;
else
cpu_dat >>= 16;
mix_dat <<= 1;
mix_dat |= 1;
if (s3->accel.poly_x < (s3->accel.poly_cx2 >> 20))
s3->accel.poly_x++;
else
s3->accel.poly_x--;
}
s3->accel.poly_cx += s3->accel.poly_dx1;
s3->accel.poly_cx2 += s3->accel.poly_dx2;
s3->accel.poly_x = s3->accel.poly_cx >> 20;
s3->accel.poly_cy++;
s3->accel.poly_cy2++;
if (!count)
break;
}
s3->accel.cur_x = s3->accel.poly_cx & 0xfff;
s3->accel.cur_y = s3->accel.poly_cy & 0xfff;
s3->accel.cur_x2 = s3->accel.poly_cx2 & 0xfff;
s3->accel.cur_y2 = s3->accel.poly_cy & 0xfff;
}
break;
case 14: /*ROPBlt (Vision868/968 only)*/
if (s3->chip != S3_VISION968 && s3->chip != S3_VISION868)
break;
if (!cpu_input) /*!cpu_input is trigger to start operation*/
{
s3->accel.sx = s3->accel.maj_axis_pcnt & 0xfff;
s3->accel.sy = s3->accel.multifunc[0] & 0xfff;
s3->accel.dx = s3->accel.destx_distp & 0xfff;
if (s3->accel.destx_distp & 0x1000)
s3->accel.dx |= ~0xfff;
s3->accel.dy = s3->accel.desty_axstp & 0xfff;
if (s3->accel.desty_axstp & 0x1000)
s3->accel.dy |= ~0xfff;
s3->accel.cx = s3->accel.cur_x & 0xfff;
s3->accel.cy = s3->accel.cur_y & 0xfff;
s3->accel.px = s3->accel.pat_x & 0xfff;
s3->accel.py = s3->accel.pat_y & 0xfff;
s3->accel.dest = dstbase + (s3->accel.dy * s3->width);
s3->accel.src = srcbase + (s3->accel.cy * s3->width);
s3->accel.pattern = (s3->accel.py * s3->width);
}
if ((s3->accel.cmd & 0x100) && !cpu_input)
return; /*Wait for data from CPU*/
frgd_mix = (s3->accel.frgd_mix >> 5) & 3;
bkgd_mix = (s3->accel.bkgd_mix >> 5) & 3;
while (count-- && s3->accel.sy >= 0) {
if ((s3->accel.dx & 0xfff) >= clip_l && (s3->accel.dx & 0xfff) <= clip_r && (s3->accel.dy & 0xfff) >= clip_t && (s3->accel.dy & 0xfff) <= clip_b) {
switch ((mix_dat & mix_mask) ? frgd_mix : bkgd_mix) {
case 0:
src_dat = s3->accel.bkgd_color;
break;
case 1:
src_dat = s3->accel.frgd_color;
break;
case 2:
src_dat = cpu_dat;
break;
case 3:
READ(s3->accel.src + s3->accel.cx, src_dat);
break;
default:
break;
}
if (s3->accel.ropmix & 0x100) {
switch ((mix_dat & mix_mask) ? frgd_mix : bkgd_mix) {
case 0:
pat_dat = s3->accel.pat_bg_color;
break;
case 1:
pat_dat = s3->accel.pat_fg_color;
break;
case 2:
pat_dat = cpu_dat;
break;
case 3:
READ(s3->accel.pattern + s3->accel.px, pat_dat);
break;
default:
break;
}
} else {
switch ((mix_dat & mix_mask) ? frgd_mix : bkgd_mix) {
case 0:
pat_dat = s3->accel.bkgd_color;
break;
case 1:
pat_dat = s3->accel.frgd_color;
break;
case 2:
pat_dat = cpu_dat;
break;
case 3:
READ(s3->accel.pattern + s3->accel.px, pat_dat);
break;
default:
break;
}
}
if ((compare_mode == 2 && src_dat != compare) || (compare_mode == 3 && src_dat == compare) || compare_mode < 2) {
READ(s3->accel.dest + s3->accel.dx, dest_dat);
ROPMIX
if (s3->accel.cmd & 0x10) {
WRITE(s3->accel.dest + s3->accel.dx, out);
}
}
}
mix_dat <<= 1;
mix_dat |= 1;
if (s3->bpp == 0)
cpu_dat >>= 8;
else
cpu_dat >>= 16;
if (s3->accel.cmd & 0x20) {
s3->accel.cx++;
s3->accel.dx++;
s3->accel.px++;
} else {
s3->accel.cx--;
s3->accel.dx--;
s3->accel.px--;
}
s3->accel.sx--;
if (s3->accel.sx < 0) {
if (s3->accel.cmd & 0x20) {
s3->accel.cx -= ((s3->accel.maj_axis_pcnt & 0xfff) + 1);
s3->accel.dx -= ((s3->accel.maj_axis_pcnt & 0xfff) + 1);
s3->accel.px -= ((s3->accel.maj_axis_pcnt & 0xfff) + 1);
} else {
s3->accel.cx += ((s3->accel.maj_axis_pcnt & 0xfff) + 1);
s3->accel.dx += ((s3->accel.maj_axis_pcnt & 0xfff) + 1);
s3->accel.px += ((s3->accel.maj_axis_pcnt & 0xfff) + 1);
}
s3->accel.sx = s3->accel.maj_axis_pcnt & 0xfff;
if (s3->accel.cmd & 0x80) {
s3->accel.cy++;
s3->accel.dy++;
s3->accel.py++;
} else {
s3->accel.cy--;
s3->accel.dy--;
s3->accel.py--;
}
s3->accel.src = srcbase + (s3->accel.cy * s3->width);
s3->accel.dest = dstbase + (s3->accel.dy * s3->width);
s3->accel.pattern = (s3->accel.py * s3->width);
s3->accel.sy--;
if (cpu_input /* && (s3->accel.multifunc[0xa] & 0xc0) == 0x80*/)
return;
if (s3->accel.sy < 0) {
return;
}
}
}
break;
default:
break;
}
}
static uint8_t
s3_pci_read(UNUSED(int func), int addr, void *priv)
{
const s3_t *s3 = (s3_t *) priv;
const svga_t *svga = &s3->svga;
switch (addr) {
case 0x00:
return 0x33; /*'S3'*/
case 0x01:
return 0x53;
case 0x02:
return s3->id_ext_pci;
case 0x03:
return (s3->chip == S3_TRIO64V2) ? 0x89 : 0x88;
case PCI_REG_COMMAND:
if (s3->chip == S3_VISION968 || s3->chip == S3_VISION868)
return s3->pci_regs[PCI_REG_COMMAND] | 0x80; /*Respond to IO and memory accesses*/
else
return s3->pci_regs[PCI_REG_COMMAND]; /*Respond to IO and memory accesses*/
break;
case 0x07:
return (s3->chip == S3_TRIO64V2) ? (s3->pci_regs[0x07] & 0x36) : (1 << 1); /*Medium DEVSEL timing*/
case 0x08: switch (s3->chip) { /*Revision ID*/
case S3_TRIO64V:
return 0x40;
case S3_TRIO64V2:
return 0x16; /*Confirmed on an onboard 64V2/DX*/
default:
return 0x00;
}
break;
case 0x09:
return 0; /*Programming interface*/
case 0x0a:
if (s3->chip >= S3_TRIO32 || s3->chip == S3_VISION968 || s3->chip == S3_VISION868)
return 0x00; /*Supports VGA interface*/
else
return 0x01;
break;
case 0x0b:
if (s3->chip >= S3_TRIO32 || s3->chip == S3_VISION968 || s3->chip == S3_VISION868)
return 0x03;
else
return 0x00;
break;
case 0x0d:
return (s3->chip == S3_TRIO64V2) ? (s3->pci_regs[0x0d] & 0xf8) : 0x00;
case 0x10:
return 0x00; /*Linear frame buffer address*/
case 0x11:
return 0x00;
case 0x12:
if (svga->crtc[0x53] & 0x08)
return 0x00;
else
return (svga->crtc[0x5a] & 0x80);
break;
case 0x13:
if (svga->crtc[0x53] & 0x08) {
return (s3->chip >= S3_TRIO64V) ? (svga->crtc[0x59] & 0xfc) : (svga->crtc[0x59] & 0xfe);
} else {
return svga->crtc[0x59];
}
break;
case 0x30:
return s3->has_bios ? (s3->pci_regs[0x30] & 0x01) : 0x00; /*BIOS ROM address*/
case 0x31:
return 0x00;
case 0x32:
return s3->has_bios ? s3->pci_regs[0x32] : 0x00;
case 0x33:
return s3->has_bios ? s3->pci_regs[0x33] : 0x00;
case 0x3c:
return s3->int_line;
case 0x3d:
return PCI_INTA;
case 0x3e:
return (s3->chip == S3_TRIO64V2) ? 0x04 : 0x00;
case 0x3f:
return (s3->chip == S3_TRIO64V2) ? 0xff : 0x00;
default:
break;
}
return 0;
}
static void
s3_pci_write(UNUSED(int func), int addr, uint8_t val, void *priv)
{
s3_t *s3 = (s3_t *) priv;
svga_t *svga = &s3->svga;
switch (addr) {
case 0x00:
case 0x01:
case 0x02:
case 0x03:
case 0x08:
case 0x09:
case 0x0a:
case 0x0b:
case 0x3d:
case 0x3e:
case 0x3f:
if (s3->chip == S3_TRIO64V2)
return;
break;
case PCI_REG_COMMAND:
if (val & PCI_COMMAND_IO)
s3_io_set(s3);
else
s3_io_remove(s3);
s3->pci_regs[PCI_REG_COMMAND] = (val & 0x23);
s3_updatemapping(s3);
break;
case 0x07:
if (s3->chip == S3_TRIO64V2) {
s3->pci_regs[0x07] = val & 0x3e;
return;
}
break;
case 0x0d:
if (s3->chip == S3_TRIO64V2) {
s3->pci_regs[0x0d] = val & 0xf8;
return;
}
break;
case 0x12:
if (!(svga->crtc[0x53] & 0x08)) {
svga->crtc[0x5a] = (svga->crtc[0x5a] & 0x7f) | (val & 0x80);
s3_updatemapping(s3);
}
break;
case 0x13:
if (svga->crtc[0x53] & 0x08) {
svga->crtc[0x59] = (s3->chip >= S3_TRIO64V) ? (val & 0xfc) : (val & 0xfe);
} else {
svga->crtc[0x59] = val;
}
s3_updatemapping(s3);
break;
case 0x30:
case 0x32:
case 0x33:
if (!s3->has_bios)
return;
s3->pci_regs[addr] = val;
if (s3->pci_regs[0x30] & 0x01) {
uint32_t biosaddr = (s3->pci_regs[0x32] << 16) | (s3->pci_regs[0x33] << 24);
mem_mapping_set_addr(&s3->bios_rom.mapping, biosaddr, 0x8000);
} else {
mem_mapping_disable(&s3->bios_rom.mapping);
}
return;
case 0x3c:
s3->int_line = val;
return;
default:
break;
}
}
static void
fifo_thread(void *param)
{
s3_t *s3 = (s3_t *) param;
uint64_t start_time;
uint64_t end_time;
while (s3->fifo_thread_run) {
thread_set_event(s3->fifo_not_full_event);
thread_wait_event(s3->wake_fifo_thread, -1);
thread_reset_event(s3->wake_fifo_thread);
s3->blitter_busy = 1;
while (!FIFO_EMPTY) {
start_time = plat_timer_read();
fifo_entry_t *fifo = &s3->fifo[s3->fifo_read_idx & FIFO_MASK];
switch (fifo->addr_type & FIFO_TYPE) {
case FIFO_WRITE_BYTE:
s3_accel_write_fifo(s3, fifo->addr_type & FIFO_ADDR, fifo->val);
break;
case FIFO_WRITE_WORD:
s3_accel_write_fifo_w(s3, fifo->addr_type & FIFO_ADDR, fifo->val);
break;
case FIFO_WRITE_DWORD:
s3_accel_write_fifo_l(s3, fifo->addr_type & FIFO_ADDR, fifo->val);
break;
case FIFO_OUT_BYTE:
s3_accel_out_fifo(s3, fifo->addr_type & FIFO_ADDR, fifo->val);
break;
case FIFO_OUT_WORD:
s3_accel_out_fifo_w(s3, fifo->addr_type & FIFO_ADDR, fifo->val);
break;
case FIFO_OUT_DWORD:
s3_accel_out_fifo_l(s3, fifo->addr_type & FIFO_ADDR, fifo->val);
break;
default:
break;
}
s3->fifo_read_idx++;
fifo->addr_type = FIFO_INVALID;
if (FIFO_ENTRIES > 0xe000)
thread_set_event(s3->fifo_not_full_event);
end_time = plat_timer_read();
s3->blitter_time += (end_time - start_time);
}
s3->blitter_busy = 0;
s3->subsys_stat |= INT_FIFO_EMP;
s3_update_irqs(s3);
}
}
static int vram_sizes[] = {
7, /*512 kB*/
6, /*1 MB*/
4, /*2 MB*/
0,
0, /*4 MB*/
0,
0, /*6 MB*/
0,
3 /*8 MB*/
};
static void
s3_disable_handlers(s3_t *s3)
{
s3_io_remove(s3);
mem_mapping_disable(&s3->linear_mapping);
mem_mapping_disable(&s3->mmio_mapping);
mem_mapping_disable(&s3->new_mmio_mapping);
mem_mapping_disable(&s3->svga.mapping);
if (s3->pci)
mem_mapping_disable(&s3->bios_rom.mapping);
/* Save all the mappings and the timers because they are part of linked lists. */
reset_state->linear_mapping = s3->linear_mapping;
reset_state->mmio_mapping = s3->mmio_mapping;
reset_state->new_mmio_mapping = s3->new_mmio_mapping;
reset_state->svga.mapping = s3->svga.mapping;
reset_state->bios_rom.mapping = s3->bios_rom.mapping;
reset_state->svga.timer = s3->svga.timer;
reset_state->svga.timer8514 = s3->svga.timer8514;
}
static void
s3_reset(void *priv)
{
s3_t *s3 = (s3_t *) priv;
if (reset_state != NULL) {
s3->accel.multifunc[0xe] &= ~(0x200 | 0x10);
s3_disable_handlers(s3);
if (s3->pci)
reset_state->pci_slot = s3->pci_slot;
*s3 = *reset_state;
}
}
static void *
s3_init(const device_t *info)
{
const char *bios_fn;
int chip;
int stepping;
s3_t *s3 = calloc(1, sizeof(s3_t));
reset_state = calloc(1, sizeof(s3_t));
svga_t *svga = &s3->svga;
int vram;
uint32_t vram_size;
switch (info->local) {
case S3_ORCHID_86C911:
bios_fn = ROM_ORCHID_86C911;
chip = S3_86C911;
video_inform(VIDEO_FLAG_TYPE_SPECIAL, &timing_s3_86c911);
break;
case S3_DIAMOND_STEALTH_VRAM:
bios_fn = ROM_DIAMOND_STEALTH_VRAM;
chip = S3_86C911;
video_inform(VIDEO_FLAG_TYPE_SPECIAL, &timing_s3_86c911);
break;
case S3_AMI_86C924:
bios_fn = ROM_AMI_86C924;
chip = S3_86C924;
video_inform(VIDEO_FLAG_TYPE_SPECIAL, &timing_s3_86c911);
break;
case S3_SPEA_MIRAGE_86C801:
bios_fn = ROM_SPEA_MIRAGE_86C801;
chip = S3_86C801;
video_inform(VIDEO_FLAG_TYPE_SPECIAL, &timing_s3_86c801);
break;
case S3_86C805_ONBOARD:
bios_fn = NULL;
chip = S3_86C805;
video_inform(VIDEO_FLAG_TYPE_SPECIAL, &timing_s3_86c805);
break;
case S3_SPEA_MIRAGE_86C805:
bios_fn = ROM_SPEA_MIRAGE_86C805;
chip = S3_86C805;
video_inform(VIDEO_FLAG_TYPE_SPECIAL, &timing_s3_86c805);
break;
case S3_MIROCRYSTAL8S_805:
bios_fn = ROM_MIROCRYSTAL8S_805;
chip = S3_86C805;
video_inform(VIDEO_FLAG_TYPE_SPECIAL, &timing_s3_86c805);
break;
case S3_MIROCRYSTAL10SD_805:
bios_fn = ROM_MIROCRYSTAL10SD_805;
chip = S3_86C805;
video_inform(VIDEO_FLAG_TYPE_SPECIAL, &timing_s3_86c805);
break;
case S3_PHOENIX_86C801:
bios_fn = ROM_PHOENIX_86C80X;
chip = S3_86C801;
video_inform(VIDEO_FLAG_TYPE_SPECIAL, &timing_s3_86c801);
break;
case S3_PHOENIX_86C805:
bios_fn = ROM_PHOENIX_86C80X;
chip = S3_86C805;
video_inform(VIDEO_FLAG_TYPE_SPECIAL, &timing_s3_86c805);
break;
case S3_METHEUS_86C928:
bios_fn = ROM_METHEUS_86C928;
chip = S3_86C928;
if (info->flags & DEVICE_VLB)
video_inform(VIDEO_FLAG_TYPE_SPECIAL, &timing_s3_86c805);
else
video_inform(VIDEO_FLAG_TYPE_SPECIAL, &timing_s3_86c801);
break;
case S3_SPEA_MERCURY_LITE_PCI:
bios_fn = ROM_SPEA_MERCURY_LITE_PCI;
chip = S3_86C928PCI;
video_inform(VIDEO_FLAG_TYPE_SPECIAL, &timing_s3_86c928pci);
break;
case S3_MIROCRYSTAL20SD_864:
bios_fn = ROM_MIROCRYSTAL20SD_864_VLB;
chip = S3_VISION864;
video_inform(VIDEO_FLAG_TYPE_SPECIAL, &timing_s3_vision864_vlb);
break;
case S3_PARADISE_BAHAMAS64:
bios_fn = ROM_PARADISE_BAHAMAS64;
chip = S3_VISION864;
if (info->flags & DEVICE_PCI)
video_inform(VIDEO_FLAG_TYPE_SPECIAL, &timing_s3_vision864_pci);
else
video_inform(VIDEO_FLAG_TYPE_SPECIAL, &timing_s3_vision864_vlb);
break;
case S3_PHOENIX_VISION864:
bios_fn = ROM_PHOENIX_VISION864;
chip = S3_VISION864;
if (info->flags & DEVICE_PCI)
video_inform(VIDEO_FLAG_TYPE_SPECIAL, &timing_s3_vision864_pci);
else
video_inform(VIDEO_FLAG_TYPE_SPECIAL, &timing_s3_vision864_vlb);
break;
case S3_NUMBER9_9FX_531:
bios_fn = ROM_NUMBER9_9FX_531;
chip = S3_VISION868;
video_inform(VIDEO_FLAG_TYPE_SPECIAL, &timing_s3_vision868_pci);
break;
case S3_PHOENIX_VISION868:
bios_fn = ROM_PHOENIX_VISION868;
chip = S3_VISION868;
video_inform(VIDEO_FLAG_TYPE_SPECIAL, &timing_s3_vision868_pci);
break;
case S3_DIAMOND_STEALTH64_964:
bios_fn = ROM_DIAMOND_STEALTH64_964;
chip = S3_VISION964;
if (info->flags & DEVICE_PCI)
video_inform(VIDEO_FLAG_TYPE_SPECIAL, &timing_s3_vision964_pci);
else
video_inform(VIDEO_FLAG_TYPE_SPECIAL, &timing_s3_vision964_vlb);
break;
case S3_MIROCRYSTAL20SV_964:
chip = S3_VISION964;
if (info->flags & DEVICE_PCI) {
bios_fn = ROM_MIROCRYSTAL20SV_964_PCI;
video_inform(VIDEO_FLAG_TYPE_SPECIAL, &timing_s3_vision964_pci);
} else {
bios_fn = ROM_MIROCRYSTAL20SV_964_VLB;
video_inform(VIDEO_FLAG_TYPE_SPECIAL, &timing_s3_vision964_vlb);
}
break;
case S3_DIAMOND_STEALTH64_968:
bios_fn = ROM_DIAMOND_STEALTH64_968;
chip = S3_VISION968;
if (info->flags & DEVICE_PCI)
video_inform(VIDEO_FLAG_TYPE_SPECIAL, &timing_s3_vision968_pci);
else
video_inform(VIDEO_FLAG_TYPE_SPECIAL, &timing_s3_vision968_vlb);
break;
case S3_MIROVIDEO40SV_ERGO_968:
bios_fn = ROM_MIROVIDEO40SV_ERGO_968_PCI;
chip = S3_VISION968;
video_inform(VIDEO_FLAG_TYPE_SPECIAL, &timing_s3_vision968_pci);
break;
case S3_NUMBER9_9FX_771:
bios_fn = ROM_NUMBER9_9FX_771;
chip = S3_VISION968;
video_inform(VIDEO_FLAG_TYPE_SPECIAL, &timing_s3_vision968_pci);
break;
case S3_PHOENIX_VISION968:
bios_fn = ROM_PHOENIX_VISION968;
chip = S3_VISION968;
video_inform(VIDEO_FLAG_TYPE_SPECIAL, &timing_s3_vision968_pci);
break;
case S3_ELSAWIN2KPROX_964:
bios_fn = ROM_ELSAWIN2KPROX_964;
chip = S3_VISION964;
video_inform(VIDEO_FLAG_TYPE_SPECIAL, &timing_s3_vision964_pci);
break;
case S3_ELSAWIN2KPROX:
bios_fn = ROM_ELSAWIN2KPROX;
chip = S3_VISION968;
video_inform(VIDEO_FLAG_TYPE_SPECIAL, &timing_s3_vision968_pci);
break;
case S3_SPEA_MERCURY_P64V:
bios_fn = ROM_SPEA_MERCURY_P64V;
chip = S3_VISION968;
video_inform(VIDEO_FLAG_TYPE_SPECIAL, &timing_s3_vision968_pci);
break;
case S3_PHOENIX_TRIO32:
bios_fn = ROM_PHOENIX_TRIO32;
chip = S3_TRIO32;
if (info->flags & DEVICE_PCI)
video_inform(VIDEO_FLAG_TYPE_SPECIAL, &timing_s3_trio32_pci);
else
video_inform(VIDEO_FLAG_TYPE_SPECIAL, &timing_s3_trio32_vlb);
break;
case S3_PHOENIX_TRIO32_ONBOARD:
bios_fn = NULL;
chip = S3_TRIO32;
if (info->flags & DEVICE_PCI)
video_inform(VIDEO_FLAG_TYPE_SPECIAL, &timing_s3_trio32_pci);
else
video_inform(VIDEO_FLAG_TYPE_SPECIAL, &timing_s3_trio32_vlb);
break;
case S3_DIAMOND_STEALTH_SE:
bios_fn = ROM_DIAMOND_STEALTH_SE;
chip = S3_TRIO32;
if (info->flags & DEVICE_PCI)
video_inform(VIDEO_FLAG_TYPE_SPECIAL, &timing_s3_trio32_pci);
else
video_inform(VIDEO_FLAG_TYPE_SPECIAL, &timing_s3_trio32_vlb);
break;
case S3_PHOENIX_TRIO64:
bios_fn = ROM_PHOENIX_TRIO64;
chip = S3_TRIO64;
if (info->flags & DEVICE_PCI)
video_inform(VIDEO_FLAG_TYPE_SPECIAL, &timing_s3_trio64_pci);
else
video_inform(VIDEO_FLAG_TYPE_SPECIAL, &timing_s3_trio64_vlb);
break;
case S3_SPEA_MIRAGE_P64:
bios_fn = ROM_SPEA_MIRAGE_P64;
chip = S3_TRIO64;
video_inform(VIDEO_FLAG_TYPE_SPECIAL, &timing_s3_trio64_vlb);
break;
case S3_PHOENIX_TRIO64_ONBOARD:
bios_fn = NULL;
chip = S3_TRIO64;
if (info->flags & DEVICE_PCI)
video_inform(VIDEO_FLAG_TYPE_SPECIAL, &timing_s3_trio64_pci);
else
video_inform(VIDEO_FLAG_TYPE_SPECIAL, &timing_s3_trio64_vlb);
break;
case S3_STB_POWERGRAPH_64_VIDEO:
bios_fn = ROM_STB_POWERGRAPH_64_VIDEO;
chip = S3_TRIO64V;
if (info->flags & DEVICE_PCI)
video_inform(VIDEO_FLAG_TYPE_SPECIAL, &timing_s3_trio64_pci);
else
video_inform(VIDEO_FLAG_TYPE_SPECIAL, &timing_s3_trio64_vlb);
break;
case S3_PHOENIX_TRIO64VPLUS:
bios_fn = ROM_PHOENIX_TRIO64VPLUS;
chip = S3_TRIO64V;
if (info->flags & DEVICE_PCI)
video_inform(VIDEO_FLAG_TYPE_SPECIAL, &timing_s3_trio64_pci);
else
video_inform(VIDEO_FLAG_TYPE_SPECIAL, &timing_s3_trio64_vlb);
break;
case S3_PHOENIX_TRIO64VPLUS_ONBOARD:
bios_fn = NULL;
chip = S3_TRIO64V;
if (info->flags & DEVICE_PCI)
video_inform(VIDEO_FLAG_TYPE_SPECIAL, &timing_s3_trio64_pci);
else
video_inform(VIDEO_FLAG_TYPE_SPECIAL, &timing_s3_trio64_vlb);
break;
case S3_CARDEX_TRIO64VPLUS:
bios_fn = ROM_CARDEX_TRIO64VPLUS;
chip = S3_TRIO64V;
video_inform(VIDEO_FLAG_TYPE_SPECIAL, &timing_s3_trio64vp_cardex_pci);
break;
case S3_DIAMOND_STEALTH64_764:
bios_fn = ROM_DIAMOND_STEALTH64_764;
chip = S3_TRIO64;
if (info->flags & DEVICE_PCI)
video_inform(VIDEO_FLAG_TYPE_SPECIAL, &timing_s3_stealth64_pci);
else
video_inform(VIDEO_FLAG_TYPE_SPECIAL, &timing_s3_stealth64_vlb);
break;
case S3_NUMBER9_9FX:
bios_fn = ROM_NUMBER9_9FX;
chip = S3_TRIO64;
if (info->flags & DEVICE_PCI)
video_inform(VIDEO_FLAG_TYPE_SPECIAL, &timing_s3_trio64_pci);
else
video_inform(VIDEO_FLAG_TYPE_SPECIAL, &timing_s3_trio64_vlb);
break;
case S3_TRIO64V2_DX:
bios_fn = ROM_TRIO64V2_DX_VBE20;
chip = S3_TRIO64V2;
video_inform(VIDEO_FLAG_TYPE_SPECIAL, &timing_s3_trio64_pci);
break;
case S3_TRIO64V2_DX_ONBOARD:
bios_fn = NULL;
chip = S3_TRIO64V2;
video_inform(VIDEO_FLAG_TYPE_SPECIAL, &timing_s3_trio64_pci);
break;
default:
free(s3);
return NULL;
}
vram = device_get_config_int("memory");
if (vram)
vram_size = vram << 20;
else
vram_size = 512 << 10;
s3->vram_mask = vram_size - 1;
s3->vram = vram;
s3->has_bios = (bios_fn != NULL);
if (s3->has_bios) {
rom_init(&s3->bios_rom, bios_fn, 0xc0000, 0x8000, 0x7fff, 0, MEM_MAPPING_EXTERNAL);
if (info->flags & DEVICE_PCI)
mem_mapping_disable(&s3->bios_rom.mapping);
}
s3->pci = !!(info->flags & DEVICE_PCI);
s3->vlb = !!(info->flags & DEVICE_VLB);
mem_mapping_add(&s3->linear_mapping, 0, 0,
svga_read_linear, svga_readw_linear, svga_readl_linear,
svga_write_linear, svga_writew_linear, svga_writel_linear,
NULL, MEM_MAPPING_EXTERNAL, &s3->svga);
/*It's hardcoded to 0xa0000 before the Trio64V+ and expects so*/
if (chip >= S3_TRIO64V)
mem_mapping_add(&s3->mmio_mapping, 0, 0,
s3_accel_read, s3_accel_read_w, s3_accel_read_l,
s3_accel_write, s3_accel_write_w, s3_accel_write_l,
NULL, MEM_MAPPING_EXTERNAL, s3);
else
mem_mapping_add(&s3->mmio_mapping, 0xa0000, 0x10000,
s3_accel_read, s3_accel_read_w, s3_accel_read_l,
s3_accel_write, s3_accel_write_w, s3_accel_write_l,
NULL, MEM_MAPPING_EXTERNAL, s3);
mem_mapping_add(&s3->new_mmio_mapping, 0, 0,
s3_accel_read, s3_accel_read_w, s3_accel_read_l,
s3_accel_write, s3_accel_write_w, s3_accel_write_l,
NULL, MEM_MAPPING_EXTERNAL, s3);
mem_mapping_disable(&s3->mmio_mapping);
mem_mapping_disable(&s3->new_mmio_mapping);
if ((chip == S3_VISION964) || (chip == S3_VISION968))
svga_init(info, &s3->svga, s3, vram_size,
s3_recalctimings,
s3_in, s3_out,
NULL,
NULL);
else {
if (chip >= S3_TRIO64V) {
svga_init(info, svga, s3, vram_size,
s3_trio64v_recalctimings,
s3_in, s3_out,
s3_hwcursor_draw,
s3_trio64v_overlay_draw);
} else {
svga_init(info, svga, s3, vram_size,
s3_recalctimings,
s3_in, s3_out,
s3_hwcursor_draw,
NULL);
}
}
svga->hwcursor.cur_ysize = 64;
switch (chip) {
case S3_VISION964:
switch (info->local) {
case S3_ELSAWIN2KPROX_964:
svga->dac_hwcursor_draw = ibm_rgb528_hwcursor_draw;
break;
default:
svga->dac_hwcursor_draw = bt48x_hwcursor_draw;
break;
}
break;
case S3_VISION968:
switch (info->local) {
case S3_DIAMOND_STEALTH64_968:
case S3_ELSAWIN2KPROX:
case S3_PHOENIX_VISION968:
case S3_NUMBER9_9FX_771:
svga->dac_hwcursor_draw = ibm_rgb528_hwcursor_draw;
break;
default:
svga->dac_hwcursor_draw = tvp3026_hwcursor_draw;
break;
}
break;
}
if (chip >= S3_VISION964) {
switch (vram) {
case 0: /* 512 kB */
svga->vram_mask = (1 << 19) - 1;
svga->vram_max = 1 << 19;
break;
case 1: /* 1 MB */
/* VRAM in first MB, mirrored in 2nd MB, 3rd and 4th MBs are open bus.
This works with the #9 9FX BIOS, and matches how my real Trio64 behaves,
but does not work with the Phoenix EDO BIOS. Possibly an FPM/EDO difference? */
svga->vram_mask = (1 << 20) - 1;
svga->vram_max = 1 << 20;
break;
case 2:
default: /*2 MB */
/* VRAM in first 2 MB, 3rd and 4th MBs are open bus. */
svga->vram_mask = (2 << 20) - 1;
svga->vram_max = 2 << 20;
break;
case 4: /*4MB*/
svga->vram_mask = (4 << 20) - 1;
svga->vram_max = 4 << 20;
break;
case 8: /*8MB*/
svga->vram_mask = (8 << 20) - 1;
svga->vram_max = 8 << 20;
break;
}
}
if (s3->pci)
svga->crtc[0x36] = 2 | (3 << 2) | (1 << 4);
else if (s3->vlb)
svga->crtc[0x36] = 1 | (3 << 2) | (1 << 4);
else
svga->crtc[0x36] = 3 | (1 << 4);
if (chip >= S3_86C928)
svga->crtc[0x36] |= (vram_sizes[vram] << 5);
else {
svga->crtc[0x36] |= ((vram == 1) ? 0x00 : 0x20) | 0x98;
svga->crtc[0x41] = (vram == 1) ? 0x10 : 0x00;
}
svga->crtc[0x37] = 1 | (7 << 5);
if (chip >= S3_86C928)
svga->crtc[0x37] |= 0x04;
svga->vblank_start = s3_vblank_start;
s3_io_set(s3);
s3->pci_regs[PCI_REG_COMMAND] = 7;
s3->pci_regs[0x30] = 0x00;
s3->pci_regs[0x32] = 0x0c;
s3->pci_regs[0x33] = 0x00;
s3->chip = chip;
s3->int_line = 0;
s3->card_type = info->local;
svga->force_old_addr = 1;
if (s3->chip <= S3_86C924)
s3->accel_start = s3_911_accel_start;
else
s3->accel_start = s3_accel_start;
switch (s3->card_type) {
case S3_ORCHID_86C911:
case S3_DIAMOND_STEALTH_VRAM:
svga->decode_mask = (1 << 20) - 1;
stepping = 0x81; /*86C911*/
s3->id = stepping;
s3->id_ext = stepping;
s3->id_ext_pci = 0;
s3->packed_mmio = 0;
s3->width = 1024;
svga->ramdac = device_add(&sc11483_ramdac_device);
if (s3->card_type == S3_ORCHID_86C911) {
svga->clock_gen = device_add(&av9194_device);
svga->getclock = av9194_getclock;
} else {
/* DCS2824-0 = Diamond ICD2061A-compatible. */
svga->clock_gen = device_add(&icd2061_device);
svga->getclock = icd2061_getclock;
}
break;
case S3_AMI_86C924:
svga->decode_mask = (1 << 20) - 1;
stepping = 0x82; /*86C911A/86C924*/
s3->id = stepping;
s3->id_ext = stepping;
s3->id_ext_pci = 0;
s3->packed_mmio = 0;
s3->width = 1024;
svga->ramdac = device_add(&att490_ramdac_device);
svga->clock_gen = device_add(&ics2494an_305_device);
svga->getclock = ics2494_getclock;
break;
case S3_MIROCRYSTAL8S_805:
case S3_MIROCRYSTAL10SD_805:
svga->decode_mask = (2 << 20) - 1;
stepping = 0xa0; /*86C801/86C805*/
s3->id = stepping;
s3->id_ext = stepping;
s3->id_ext_pci = 0;
s3->packed_mmio = 0;
svga->crtc[0x5a] = 0x0a;
svga->ramdac = device_add(&gendac_ramdac_device);
svga->clock_gen = svga->ramdac;
svga->getclock = sdac_getclock;
break;
case S3_SPEA_MIRAGE_86C801:
case S3_SPEA_MIRAGE_86C805:
svga->decode_mask = (2 << 20) - 1;
stepping = 0xa2; /*86C801/86C805*/
s3->id = stepping;
s3->id_ext = stepping;
s3->id_ext_pci = 0;
s3->packed_mmio = 0;
svga->crtc[0x5a] = 0x0a;
svga->ramdac = device_add(&att491_ramdac_device);
svga->clock_gen = device_add(&av9194_device);
svga->getclock = av9194_getclock;
break;
case S3_86C805_ONBOARD:
svga->decode_mask = (2 << 20) - 1;
stepping = 0xa0; /*86C801/86C805*/
s3->id = stepping;
s3->id_ext = stepping;
s3->id_ext_pci = 0;
s3->packed_mmio = 0;
svga->crtc[0x5a] = 0x0a;
svga->ramdac = device_add(&att490_ramdac_device);
svga->clock_gen = device_add(&av9194_device);
svga->getclock = av9194_getclock;
break;
case S3_PHOENIX_86C801:
case S3_PHOENIX_86C805:
svga->decode_mask = (2 << 20) - 1;
stepping = 0xa0; /*86C801/86C805*/
s3->id = stepping;
s3->id_ext = stepping;
s3->id_ext_pci = 0;
s3->packed_mmio = 0;
svga->crtc[0x5a] = 0x0a;
svga->ramdac = device_add(&att492_ramdac_device);
svga->clock_gen = device_add(&av9194_device);
svga->getclock = av9194_getclock;
break;
case S3_METHEUS_86C928:
svga->decode_mask = (4 << 20) - 1;
stepping = 0x91; /*86C928D*/
s3->id = stepping;
s3->id_ext = stepping;
s3->id_ext_pci = 0;
s3->packed_mmio = 0;
svga->crtc[0x5a] = 0x0a;
svga->ramdac = device_add(&bt485_ramdac_device);
svga->clock_gen = device_add(&icd2061_device);
svga->getclock = icd2061_getclock;
break;
case S3_SPEA_MERCURY_LITE_PCI:
svga->decode_mask = (4 << 20) - 1;
stepping = 0xb0; /*86C928PCI*/
s3->id = stepping;
s3->id_ext = stepping;
s3->id_ext_pci = stepping;
s3->packed_mmio = 0;
svga->crtc[0x5a] = 0x0a;
svga->ramdac = device_add(&sc1502x_ramdac_device);
svga->clock_gen = device_add(&av9194_device);
svga->getclock = av9194_getclock;
break;
case S3_PARADISE_BAHAMAS64:
case S3_PHOENIX_VISION864:
case S3_MIROCRYSTAL20SD_864: /*BIOS 3.xx has a SDAC ramdac.*/
svga->decode_mask = (8 << 20) - 1;
if (info->local == S3_PARADISE_BAHAMAS64)
stepping = 0xc0; /*Vision864*/
else
stepping = 0xc1; /*Vision864P*/
s3->id = stepping;
s3->id_ext = s3->id_ext_pci = stepping;
s3->packed_mmio = 0;
svga->crtc[0x5a] = 0x0a;
svga->ramdac = device_add(&sdac_ramdac_device);
svga->clock_gen = svga->ramdac;
svga->getclock = sdac_getclock;
break;
case S3_DIAMOND_STEALTH64_964:
case S3_ELSAWIN2KPROX_964:
case S3_MIROCRYSTAL20SV_964:
svga->decode_mask = (8 << 20) - 1;
stepping = 0xd0; /*Vision964*/
s3->id = stepping;
s3->id_ext = s3->id_ext_pci = stepping;
s3->packed_mmio = 1;
svga->crtc[0x5a] = 0x0a;
switch (info->local) {
case S3_ELSAWIN2KPROX_964:
svga->ramdac = device_add(&ibm_rgb528_ramdac_device);
svga->clock_gen = device_add(&icd2061_device);
svga->getclock = icd2061_getclock;
break;
default:
svga->ramdac = device_add(&bt485_ramdac_device);
svga->clock_gen = device_add(&icd2061_device);
svga->getclock = icd2061_getclock;
break;
}
break;
case S3_DIAMOND_STEALTH64_968:
case S3_ELSAWIN2KPROX:
case S3_SPEA_MERCURY_P64V:
case S3_MIROVIDEO40SV_ERGO_968:
case S3_NUMBER9_9FX_771:
case S3_PHOENIX_VISION968:
svga->decode_mask = (8 << 20) - 1;
s3->id = 0xe1; /*Vision968*/
s3->id_ext = 0xf0;
s3->id_ext_pci = s3->id_ext;
s3->packed_mmio = 1;
if (s3->pci) {
svga->crtc[0x53] = 0x18;
svga->crtc[0x58] = 0x10;
svga->crtc[0x59] = 0x70;
svga->crtc[0x5a] = 0x00;
svga->crtc[0x6c] = 1;
} else {
svga->crtc[0x53] = 0x00;
svga->crtc[0x59] = 0x00;
svga->crtc[0x5a] = 0x0a;
}
switch (info->local) {
case S3_DIAMOND_STEALTH64_968:
case S3_ELSAWIN2KPROX:
case S3_PHOENIX_VISION968:
case S3_NUMBER9_9FX_771:
svga->ramdac = device_add(&ibm_rgb528_ramdac_device);
svga->clock_gen = device_add(&icd2061_device);
svga->getclock = icd2061_getclock;
break;
default:
svga->ramdac = device_add(&tvp3026_ramdac_device);
svga->clock_gen = svga->ramdac;
svga->getclock = tvp3026_getclock;
svga->conv_16to32 = tvp3026_conv_16to32;
break;
}
break;
case S3_NUMBER9_9FX_531:
case S3_PHOENIX_VISION868:
svga->decode_mask = (8 << 20) - 1;
s3->id = 0xe1; /*Vision868*/
s3->id_ext = 0x90;
s3->id_ext_pci = 0x80;
s3->packed_mmio = 1;
if (s3->pci) {
svga->crtc[0x53] = 0x18;
svga->crtc[0x58] = 0x10;
svga->crtc[0x59] = 0x70;
svga->crtc[0x5a] = 0x00;
svga->crtc[0x6c] = 1;
} else {
svga->crtc[0x53] = 0x00;
svga->crtc[0x59] = 0x00;
svga->crtc[0x5a] = 0x0a;
}
if (info->local == S3_NUMBER9_9FX_531) {
svga->ramdac = device_add(&att498_ramdac_device);
svga->clock_gen = device_add(&icd2061_device);
svga->getclock = icd2061_getclock;
} else {
svga->ramdac = device_add(&sdac_ramdac_device);
svga->clock_gen = svga->ramdac;
svga->getclock = sdac_getclock;
}
break;
case S3_PHOENIX_TRIO32:
case S3_PHOENIX_TRIO32_ONBOARD:
case S3_DIAMOND_STEALTH_SE:
svga->decode_mask = (4 << 20) - 1;
s3->id = 0xe1; /*Trio32*/
s3->id_ext = 0x10;
s3->id_ext_pci = 0x11;
s3->packed_mmio = 1;
svga->clock_gen = s3;
svga->getclock = s3_trio64_getclock;
break;
case S3_PHOENIX_TRIO64:
case S3_PHOENIX_TRIO64_ONBOARD:
case S3_STB_POWERGRAPH_64_VIDEO:
case S3_PHOENIX_TRIO64VPLUS:
case S3_PHOENIX_TRIO64VPLUS_ONBOARD:
case S3_CARDEX_TRIO64VPLUS:
case S3_DIAMOND_STEALTH64_764:
case S3_SPEA_MIRAGE_P64:
if (device_get_config_int("memory") == 1)
svga->vram_max = 1 << 20; /* Phoenix BIOS does not expect VRAM to be mirrored. */
/* Fall over. */
fallthrough;
case S3_NUMBER9_9FX:
svga->decode_mask = (4 << 20) - 1;
s3->id = 0xe1; /*Trio64*/
s3->id_ext = s3->id_ext_pci = 0x11;
s3->packed_mmio = 1;
if (s3->chip == S3_TRIO64V)
svga->crtc[0x53] = 0x08;
svga->clock_gen = s3;
svga->getclock = s3_trio64_getclock;
break;
case S3_TRIO64V2_DX:
case S3_TRIO64V2_DX_ONBOARD:
svga->decode_mask = (4 << 20) - 1;
s3->id = 0xe1; /*Trio64V2*/
s3->id_ext = s3->id_ext_pci = 0x01;
s3->packed_mmio = 1;
svga->crtc[0x53] = 0x08;
svga->crtc[0x59] = 0x70;
svga->crtc[0x5a] = 0x00;
svga->crtc[0x6c] = 1;
s3->pci_regs[0x05] = 0;
s3->pci_regs[0x06] = 0;
s3->pci_regs[0x07] = 2;
s3->pci_regs[0x3d] = 1;
s3->pci_regs[0x3e] = 4;
s3->pci_regs[0x3f] = 0xff;
svga->clock_gen = s3;
svga->getclock = s3_trio64_getclock;
break;
default:
return NULL;
}
if (s3->pci) {
if (bios_fn == NULL)
pci_add_card(PCI_ADD_VIDEO, s3_pci_read, s3_pci_write, s3, &s3->pci_slot);
else
pci_add_card(PCI_ADD_NORMAL, s3_pci_read, s3_pci_write, s3, &s3->pci_slot);
}
s3->i2c = i2c_gpio_init("ddc_s3");
s3->ddc = ddc_init(i2c_gpio_get_bus(s3->i2c));
s3->wake_fifo_thread = thread_create_event();
s3->fifo_not_full_event = thread_create_event();
s3->fifo_thread_run = 1;
s3->fifo_thread = thread_create(fifo_thread, s3);
*reset_state = *s3;
return s3;
}
static int
s3_orchid_86c911_available(void)
{
return rom_present(ROM_ORCHID_86C911);
}
static int
s3_diamond_stealth_vram_available(void)
{
return rom_present(ROM_DIAMOND_STEALTH_VRAM);
}
static int
s3_ami_86c924_available(void)
{
return rom_present(ROM_AMI_86C924);
}
static int
s3_spea_mirage_86c801_available(void)
{
return rom_present(ROM_SPEA_MIRAGE_86C801);
}
static int
s3_spea_mirage_86c805_available(void)
{
return rom_present(ROM_SPEA_MIRAGE_86C805);
}
static int
s3_phoenix_86c80x_available(void)
{
return rom_present(ROM_PHOENIX_86C80X);
}
static int
s3_mirocrystal_8s_805_available(void)
{
return rom_present(ROM_MIROCRYSTAL8S_805);
}
static int
s3_mirocrystal_10sd_805_available(void)
{
return rom_present(ROM_MIROCRYSTAL10SD_805);
}
static int
s3_metheus_86c928_available(void)
{
return rom_present(ROM_METHEUS_86C928);
}
static int
s3_spea_mercury_lite_pci_available(void)
{
return rom_present(ROM_SPEA_MERCURY_LITE_PCI);
}
static int
s3_bahamas64_available(void)
{
return rom_present(ROM_PARADISE_BAHAMAS64);
}
static int
s3_phoenix_vision864_available(void)
{
return rom_present(ROM_PHOENIX_VISION864);
}
static int
s3_9fx_531_available(void)
{
return rom_present(ROM_NUMBER9_9FX_531);
}
static int
s3_phoenix_vision868_available(void)
{
return rom_present(ROM_PHOENIX_VISION868);
}
static int
s3_mirocrystal_20sv_964_vlb_available(void)
{
return rom_present(ROM_MIROCRYSTAL20SV_964_VLB);
}
static int
s3_mirocrystal_20sv_964_pci_available(void)
{
return rom_present(ROM_MIROCRYSTAL20SV_964_PCI);
}
static int
s3_diamond_stealth64_964_available(void)
{
return rom_present(ROM_DIAMOND_STEALTH64_964);
}
static int
s3_diamond_stealth64_968_available(void)
{
return rom_present(ROM_DIAMOND_STEALTH64_968);
}
static int
s3_mirovideo_40sv_ergo_968_pci_available(void)
{
return rom_present(ROM_MIROVIDEO40SV_ERGO_968_PCI);
}
static int
s3_9fx_771_available(void)
{
return rom_present(ROM_NUMBER9_9FX_771);
}
static int
s3_phoenix_vision968_available(void)
{
return rom_present(ROM_PHOENIX_VISION968);
}
static int
s3_mirocrystal_20sd_864_vlb_available(void)
{
return rom_present(ROM_MIROCRYSTAL20SD_864_VLB);
}
static int
s3_spea_mercury_p64v_pci_available(void)
{
return rom_present(ROM_SPEA_MERCURY_P64V);
}
static int
s3_elsa_winner2000_pro_x_964_available(void)
{
return rom_present(ROM_ELSAWIN2KPROX_964);
}
static int
s3_elsa_winner2000_pro_x_available(void)
{
return rom_present(ROM_ELSAWIN2KPROX);
}
static int
s3_phoenix_trio32_available(void)
{
return rom_present(ROM_PHOENIX_TRIO32);
}
static int
s3_diamond_stealth_se_available(void)
{
return rom_present(ROM_DIAMOND_STEALTH_SE);
}
static int
s3_9fx_available(void)
{
return rom_present(ROM_NUMBER9_9FX);
}
static int
s3_spea_mirage_p64_vlb_available(void)
{
return rom_present(ROM_SPEA_MIRAGE_P64);
}
static int
s3_phoenix_trio64_available(void)
{
return rom_present(ROM_PHOENIX_TRIO64);
}
static int
s3_stb_powergraph_64_video_available(void)
{
return rom_present(ROM_STB_POWERGRAPH_64_VIDEO);
}
static int
s3_phoenix_trio64vplus_available(void)
{
return rom_present(ROM_PHOENIX_TRIO64VPLUS);
}
static int
s3_cardex_trio64vplus_available(void)
{
return rom_present(ROM_PHOENIX_TRIO64VPLUS);
}
static int
s3_diamond_stealth64_764_available(void)
{
return rom_present(ROM_DIAMOND_STEALTH64_764);
}
static int
s3_trio64v2_dx_available(void)
{
return rom_present(ROM_TRIO64V2_DX_VBE20);
}
static void
s3_close(void *priv)
{
s3_t *s3 = (s3_t *) priv;
s3->fifo_thread_run = 0;
thread_set_event(s3->wake_fifo_thread);
thread_wait(s3->fifo_thread);
thread_destroy_event(s3->fifo_not_full_event);
thread_destroy_event(s3->wake_fifo_thread);
svga_close(&s3->svga);
ddc_close(s3->ddc);
i2c_gpio_close(s3->i2c);
free(reset_state);
reset_state = NULL;
free(s3);
}
static void
s3_speed_changed(void *priv)
{
s3_t *s3 = (s3_t *) priv;
svga_recalctimings(&s3->svga);
}
static void
s3_force_redraw(void *priv)
{
s3_t *s3 = (s3_t *) priv;
s3->svga.fullchange = s3->svga.monitor->mon_changeframecount;
}
static const device_config_t s3_orchid_86c911_config[] = {
{ .name = "memory",
.description = "Memory size",
.type = CONFIG_SELECTION,
.default_int = 1,
.selection = {
{ .description = "512 KB",
.value = 0 },
{ .description = "1 MB",
.value = 1 },
{ .description = "" } } },
{ .type = CONFIG_END }
};
static const device_config_t s3_9fx_config[] = {
{ .name = "memory",
.description = "Memory size",
.type = CONFIG_SELECTION,
.default_int = 2,
.selection = {
{ .description = "1 MB",
.value = 1 },
{ .description = "2 MB",
.value = 2 },
/*Trio64 also supports 4 MB, however the Number Nine BIOS does not*/
{
.description = "" } } },
{ .type = CONFIG_END }
};
static const device_config_t s3_phoenix_trio32_config[] = {
{ .name = "memory",
.description = "Memory size",
.type = CONFIG_SELECTION,
.default_int = 2,
.selection = {
{ .description = "512 KB",
.value = 0 },
{ .description = "1 MB",
.value = 1 },
{ .description = "2 MB",
.value = 2 },
{ .description = "" } } },
{ .type = CONFIG_END }
};
static const device_config_t s3_standard_config[] = {
{ .name = "memory",
.description = "Memory size",
.type = CONFIG_SELECTION,
.default_int = 4,
.selection = {
{ .description = "1 MB",
.value = 1 },
{ .description = "2 MB",
.value = 2 },
{ .description = "4 MB",
.value = 4 },
{ .description = "" } } },
{ .type = CONFIG_END }
};
static const device_config_t s3_968_config[] = {
{ .name = "memory",
.description = "Memory size",
.type = CONFIG_SELECTION,
.default_int = 4,
.selection = {
{ .description = "1 MB",
.value = 1 },
{ .description = "2 MB",
.value = 2 },
{ .description = "4 MB",
.value = 4 },
{ .description = "8 MB",
.value = 8 },
{ .description = "" } } },
{ .type = CONFIG_END }
};
static const device_config_t s3_standard_config2[] = {
{ .name = "memory",
.description = "Memory size",
.type = CONFIG_SELECTION,
.default_int = 4,
.selection = {
{ .description = "2 MB",
.value = 2 },
{ .description = "4 MB",
.value = 4 },
{ .description = "" } } },
{ .type = CONFIG_END }
};
const device_t s3_orchid_86c911_isa_device = {
.name = "S3 86c911 ISA (Orchid Fahrenheit 1280)",
.internal_name = "orchid_s3_911",
.flags = DEVICE_AT | DEVICE_ISA,
.local = S3_ORCHID_86C911,
.init = s3_init,
.close = s3_close,
.reset = s3_reset,
{ .available = s3_orchid_86c911_available },
.speed_changed = s3_speed_changed,
.force_redraw = s3_force_redraw,
.config = s3_orchid_86c911_config
};
const device_t s3_diamond_stealth_vram_isa_device = {
.name = "S3 86c911 ISA (Diamond Stealth VRAM)",
.internal_name = "stealthvram_isa",
.flags = DEVICE_AT | DEVICE_ISA,
.local = S3_DIAMOND_STEALTH_VRAM,
.init = s3_init,
.close = s3_close,
.reset = s3_reset,
{ .available = s3_diamond_stealth_vram_available },
.speed_changed = s3_speed_changed,
.force_redraw = s3_force_redraw,
.config = s3_orchid_86c911_config
};
const device_t s3_ami_86c924_isa_device = {
.name = "S3 86c924 ISA (AMI)",
.internal_name = "ami_s3_924",
.flags = DEVICE_AT | DEVICE_ISA,
.local = S3_AMI_86C924,
.init = s3_init,
.close = s3_close,
.reset = s3_reset,
{ .available = s3_ami_86c924_available },
.speed_changed = s3_speed_changed,
.force_redraw = s3_force_redraw,
.config = s3_orchid_86c911_config
};
const device_t s3_spea_mirage_86c801_isa_device = {
.name = "S3 86c801 ISA (SPEA Mirage ISA)",
.internal_name = "px_s3_v7_801_isa",
.flags = DEVICE_AT | DEVICE_ISA,
.local = S3_SPEA_MIRAGE_86C801,
.init = s3_init,
.close = s3_close,
.reset = s3_reset,
{ .available = s3_spea_mirage_86c801_available },
.speed_changed = s3_speed_changed,
.force_redraw = s3_force_redraw,
.config = s3_9fx_config
};
const device_t s3_86c805_onboard_vlb_device = {
.name = "S3 86c805 VLB On-Board",
.internal_name = "px_s3_805_onboard_vlb",
.flags = DEVICE_VLB,
.local = S3_86C805_ONBOARD,
.init = s3_init,
.close = s3_close,
.reset = s3_reset,
{ .available = NULL },
.speed_changed = s3_speed_changed,
.force_redraw = s3_force_redraw,
.config = s3_9fx_config
};
const device_t s3_spea_mirage_86c805_vlb_device = {
.name = "S3 86c805 VLB (SPEA Mirage VL)",
.internal_name = "px_s3_v7_805_vlb",
.flags = DEVICE_VLB,
.local = S3_SPEA_MIRAGE_86C805,
.init = s3_init,
.close = s3_close,
.reset = s3_reset,
{ .available = s3_spea_mirage_86c805_available },
.speed_changed = s3_speed_changed,
.force_redraw = s3_force_redraw,
.config = s3_9fx_config
};
const device_t s3_mirocrystal_8s_805_vlb_device = {
.name = "S3 86c805 VLB (MiroCRYSTAL 8S)",
.internal_name = "mirocrystal8s_vlb",
.flags = DEVICE_VLB,
.local = S3_MIROCRYSTAL8S_805,
.init = s3_init,
.close = s3_close,
.reset = s3_reset,
{ .available = s3_mirocrystal_8s_805_available },
.speed_changed = s3_speed_changed,
.force_redraw = s3_force_redraw,
.config = s3_9fx_config
};
const device_t s3_mirocrystal_10sd_805_vlb_device = {
.name = "S3 86c805 VLB (MiroCRYSTAL 10SD)",
.internal_name = "mirocrystal10sd_vlb",
.flags = DEVICE_VLB,
.local = S3_MIROCRYSTAL10SD_805,
.init = s3_init,
.close = s3_close,
.reset = s3_reset,
{ .available = s3_mirocrystal_10sd_805_available },
.speed_changed = s3_speed_changed,
.force_redraw = s3_force_redraw,
.config = s3_9fx_config
};
const device_t s3_phoenix_86c801_isa_device = {
.name = "S3 86c801 ISA (Phoenix)",
.internal_name = "px_86c801_isa",
.flags = DEVICE_AT | DEVICE_ISA,
.local = S3_PHOENIX_86C801,
.init = s3_init,
.close = s3_close,
.reset = s3_reset,
{ .available = s3_phoenix_86c80x_available },
.speed_changed = s3_speed_changed,
.force_redraw = s3_force_redraw,
.config = s3_9fx_config
};
const device_t s3_phoenix_86c805_vlb_device = {
.name = "S3 86c805 VLB (Phoenix)",
.internal_name = "px_86c805_vlb",
.flags = DEVICE_VLB,
.local = S3_PHOENIX_86C805,
.init = s3_init,
.close = s3_close,
.reset = s3_reset,
{ .available = s3_phoenix_86c80x_available },
.speed_changed = s3_speed_changed,
.force_redraw = s3_force_redraw,
.config = s3_9fx_config
};
const device_t s3_metheus_86c928_isa_device = {
.name = "S3 86c928 ISA (Metheus Premier 928)",
.internal_name = "metheus928_isa",
.flags = DEVICE_AT | DEVICE_ISA,
.local = S3_METHEUS_86C928,
.init = s3_init,
.close = s3_close,
.reset = s3_reset,
{ .available = s3_metheus_86c928_available },
.speed_changed = s3_speed_changed,
.force_redraw = s3_force_redraw,
.config = s3_standard_config
};
const device_t s3_metheus_86c928_vlb_device = {
.name = "S3 86c928 VLB (Metheus Premier 928)",
.internal_name = "metheus928_vlb",
.flags = DEVICE_VLB,
.local = S3_METHEUS_86C928,
.init = s3_init,
.close = s3_close,
.reset = s3_reset,
{ .available = s3_metheus_86c928_available },
.speed_changed = s3_speed_changed,
.force_redraw = s3_force_redraw,
.config = s3_standard_config
};
const device_t s3_spea_mercury_lite_86c928_pci_device = {
.name = "S3 86c928 PCI (SPEA Mercury Lite)",
.internal_name = "spea_mercurylite_pci",
.flags = DEVICE_PCI,
.local = S3_SPEA_MERCURY_LITE_PCI,
.init = s3_init,
.close = s3_close,
.reset = s3_reset,
{ .available = s3_spea_mercury_lite_pci_available },
.speed_changed = s3_speed_changed,
.force_redraw = s3_force_redraw,
.config = s3_orchid_86c911_config
};
const device_t s3_mirocrystal_20sd_864_vlb_device = {
.name = "S3 Vision864 VLB (MiroCRYSTAL 20SD)",
.internal_name = "mirocrystal20sd_vlb",
.flags = DEVICE_VLB,
.local = S3_MIROCRYSTAL20SD_864,
.init = s3_init,
.close = s3_close,
.reset = s3_reset,
{ .available = s3_mirocrystal_20sd_864_vlb_available },
.speed_changed = s3_speed_changed,
.force_redraw = s3_force_redraw,
.config = s3_9fx_config
};
const device_t s3_bahamas64_vlb_device = {
.name = "S3 Vision864 VLB (Paradise Bahamas 64)",
.internal_name = "bahamas64_vlb",
.flags = DEVICE_VLB,
.local = S3_PARADISE_BAHAMAS64,
.init = s3_init,
.close = s3_close,
.reset = s3_reset,
{ .available = s3_bahamas64_available },
.speed_changed = s3_speed_changed,
.force_redraw = s3_force_redraw,
.config = s3_9fx_config
};
const device_t s3_bahamas64_pci_device = {
.name = "S3 Vision864 PCI (Paradise Bahamas 64)",
.internal_name = "bahamas64_pci",
.flags = DEVICE_PCI,
.local = S3_PARADISE_BAHAMAS64,
.init = s3_init,
.close = s3_close,
.reset = s3_reset,
{ .available = s3_bahamas64_available },
.speed_changed = s3_speed_changed,
.force_redraw = s3_force_redraw,
.config = s3_9fx_config
};
const device_t s3_mirocrystal_20sv_964_vlb_device = {
.name = "S3 Vision964 VLB (MiroCRYSTAL 20SV)",
.internal_name = "mirocrystal20sv_vlb",
.flags = DEVICE_VLB,
.local = S3_MIROCRYSTAL20SV_964,
.init = s3_init,
.close = s3_close,
.reset = s3_reset,
{ .available = s3_mirocrystal_20sv_964_vlb_available },
.speed_changed = s3_speed_changed,
.force_redraw = s3_force_redraw,
.config = s3_9fx_config
};
const device_t s3_mirocrystal_20sv_964_pci_device = {
.name = "S3 Vision964 PCI (MiroCRYSTAL 20SV)",
.internal_name = "mirocrystal20sv_pci",
.flags = DEVICE_PCI,
.local = S3_MIROCRYSTAL20SV_964,
.init = s3_init,
.close = s3_close,
.reset = s3_reset,
{ .available = s3_mirocrystal_20sv_964_pci_available },
.speed_changed = s3_speed_changed,
.force_redraw = s3_force_redraw,
.config = s3_9fx_config
};
const device_t s3_diamond_stealth64_964_vlb_device = {
.name = "S3 Vision964 VLB (Diamond Stealth64 VRAM)",
.internal_name = "stealth64v_vlb",
.flags = DEVICE_VLB,
.local = S3_DIAMOND_STEALTH64_964,
.init = s3_init,
.close = s3_close,
.reset = s3_reset,
{ .available = s3_diamond_stealth64_964_available },
.speed_changed = s3_speed_changed,
.force_redraw = s3_force_redraw,
.config = s3_standard_config
};
const device_t s3_diamond_stealth64_964_pci_device = {
.name = "S3 Vision964 PCI (Diamond Stealth64 VRAM)",
.internal_name = "stealth64v_pci",
.flags = DEVICE_PCI,
.local = S3_DIAMOND_STEALTH64_964,
.init = s3_init,
.close = s3_close,
.reset = s3_reset,
{ .available = s3_diamond_stealth64_964_available },
.speed_changed = s3_speed_changed,
.force_redraw = s3_force_redraw,
.config = s3_standard_config
};
const device_t s3_diamond_stealth64_968_vlb_device = {
.name = "S3 Vision968 VLB (Diamond Stealth64 Video VRAM)",
.internal_name = "stealth64vv_vlb",
.flags = DEVICE_VLB,
.local = S3_DIAMOND_STEALTH64_968,
.init = s3_init,
.close = s3_close,
.reset = s3_reset,
{ .available = s3_diamond_stealth64_968_available },
.speed_changed = s3_speed_changed,
.force_redraw = s3_force_redraw,
.config = s3_standard_config2
};
const device_t s3_diamond_stealth64_968_pci_device = {
.name = "S3 Vision968 PCI (Diamond Stealth64 Video VRAM)",
.internal_name = "stealth64vv_pci",
.flags = DEVICE_PCI,
.local = S3_DIAMOND_STEALTH64_968,
.init = s3_init,
.close = s3_close,
.reset = s3_reset,
{ .available = s3_diamond_stealth64_968_available },
.speed_changed = s3_speed_changed,
.force_redraw = s3_force_redraw,
.config = s3_standard_config2
};
const device_t s3_9fx_771_pci_device = {
.name = "S3 Vision968 PCI (Number 9 9FX 771)",
.internal_name = "n9_9fx_771_pci",
.flags = DEVICE_PCI,
.local = S3_NUMBER9_9FX_771,
.init = s3_init,
.close = s3_close,
.reset = s3_reset,
{ .available = s3_9fx_771_available },
.speed_changed = s3_speed_changed,
.force_redraw = s3_force_redraw,
.config = s3_968_config
};
const device_t s3_phoenix_vision968_pci_device = {
.name = "S3 Vision968 PCI (Phoenix)",
.internal_name = "px_vision968_pci",
.flags = DEVICE_PCI,
.local = S3_PHOENIX_VISION968,
.init = s3_init,
.close = s3_close,
.reset = s3_reset,
{ .available = s3_phoenix_vision968_available },
.speed_changed = s3_speed_changed,
.force_redraw = s3_force_redraw,
.config = s3_standard_config
};
const device_t s3_mirovideo_40sv_ergo_968_pci_device = {
.name = "S3 Vision968 PCI (MiroVIDEO 40SV Ergo)",
.internal_name = "mirovideo40sv_pci",
.flags = DEVICE_PCI,
.local = S3_MIROVIDEO40SV_ERGO_968,
.init = s3_init,
.close = s3_close,
.reset = s3_reset,
{ .available = s3_mirovideo_40sv_ergo_968_pci_available },
.speed_changed = s3_speed_changed,
.force_redraw = s3_force_redraw,
.config = s3_standard_config
};
const device_t s3_spea_mercury_p64v_pci_device = {
.name = "S3 Vision968 PCI (SPEA Mercury P64V)",
.internal_name = "spea_mercury64p_pci",
.flags = DEVICE_PCI,
.local = S3_SPEA_MERCURY_P64V,
.init = s3_init,
.close = s3_close,
.reset = s3_reset,
{ .available = s3_spea_mercury_p64v_pci_available },
.speed_changed = s3_speed_changed,
.force_redraw = s3_force_redraw,
.config = s3_standard_config
};
const device_t s3_9fx_vlb_device = {
.name = "S3 Trio64 VLB (Number 9 9FX 330)",
.internal_name = "n9_9fx_vlb",
.flags = DEVICE_VLB,
.local = S3_NUMBER9_9FX,
.init = s3_init,
.close = s3_close,
.reset = s3_reset,
{ .available = s3_9fx_available },
.speed_changed = s3_speed_changed,
.force_redraw = s3_force_redraw,
.config = s3_9fx_config
};
const device_t s3_9fx_pci_device = {
.name = "S3 Trio64 PCI (Number 9 9FX 330)",
.internal_name = "n9_9fx_pci",
.flags = DEVICE_PCI,
.local = S3_NUMBER9_9FX,
.init = s3_init,
.close = s3_close,
.reset = s3_reset,
{ .available = s3_9fx_available },
.speed_changed = s3_speed_changed,
.force_redraw = s3_force_redraw,
.config = s3_9fx_config
};
const device_t s3_phoenix_trio32_onboard_vlb_device = {
.name = "S3 Trio32 VLB On-Board (Phoenix)",
.internal_name = "px_trio32_onboard_vlb",
.flags = DEVICE_VLB,
.local = S3_PHOENIX_TRIO32_ONBOARD,
.init = s3_init,
.close = s3_close,
.reset = s3_reset,
{ .available = NULL },
.speed_changed = s3_speed_changed,
.force_redraw = s3_force_redraw,
.config = s3_phoenix_trio32_config
};
const device_t s3_phoenix_trio32_vlb_device = {
.name = "S3 Trio32 VLB (Phoenix)",
.internal_name = "px_trio32_vlb",
.flags = DEVICE_VLB,
.local = S3_PHOENIX_TRIO32,
.init = s3_init,
.close = s3_close,
.reset = s3_reset,
{ .available = s3_phoenix_trio32_available },
.speed_changed = s3_speed_changed,
.force_redraw = s3_force_redraw,
.config = s3_phoenix_trio32_config
};
const device_t s3_phoenix_trio32_onboard_pci_device = {
.name = "S3 Trio32 PCI On-Board (Phoenix)",
.internal_name = "px_trio32_onboard_pci",
.flags = DEVICE_PCI,
.local = S3_PHOENIX_TRIO32_ONBOARD,
.init = s3_init,
.close = s3_close,
.reset = s3_reset,
{ .available = NULL },
.speed_changed = s3_speed_changed,
.force_redraw = s3_force_redraw,
.config = s3_phoenix_trio32_config
};
const device_t s3_phoenix_trio32_pci_device = {
.name = "S3 Trio32 PCI (Phoenix)",
.internal_name = "px_trio32_pci",
.flags = DEVICE_PCI,
.local = S3_PHOENIX_TRIO32,
.init = s3_init,
.close = s3_close,
.reset = s3_reset,
{ .available = s3_phoenix_trio32_available },
.speed_changed = s3_speed_changed,
.force_redraw = s3_force_redraw,
.config = s3_phoenix_trio32_config
};
const device_t s3_diamond_stealth_se_vlb_device = {
.name = "S3 Trio32 VLB (Diamond Stealth SE)",
.internal_name = "stealthse_vlb",
.flags = DEVICE_VLB,
.local = S3_DIAMOND_STEALTH_SE,
.init = s3_init,
.close = s3_close,
.reset = s3_reset,
{ .available = s3_diamond_stealth_se_available },
.speed_changed = s3_speed_changed,
.force_redraw = s3_force_redraw,
.config = s3_phoenix_trio32_config
};
const device_t s3_diamond_stealth_se_pci_device = {
.name = "S3 Trio32 PCI (Diamond Stealth SE)",
.internal_name = "stealthse_pci",
.flags = DEVICE_PCI,
.local = S3_DIAMOND_STEALTH_SE,
.init = s3_init,
.close = s3_close,
.reset = s3_reset,
{ .available = s3_diamond_stealth_se_available },
.speed_changed = s3_speed_changed,
.force_redraw = s3_force_redraw,
.config = s3_phoenix_trio32_config
};
const device_t s3_phoenix_trio64_vlb_device = {
.name = "S3 Trio64 VLB (Phoenix)",
.internal_name = "px_trio64_vlb",
.flags = DEVICE_VLB,
.local = S3_PHOENIX_TRIO64,
.init = s3_init,
.close = s3_close,
.reset = s3_reset,
{ .available = s3_phoenix_trio64_available },
.speed_changed = s3_speed_changed,
.force_redraw = s3_force_redraw,
.config = s3_standard_config
};
const device_t s3_phoenix_trio64_onboard_pci_device = {
.name = "S3 Trio64 PCI On-Board (Phoenix)",
.internal_name = "px_trio64_onboard_pci",
.flags = DEVICE_PCI,
.local = S3_PHOENIX_TRIO64_ONBOARD,
.init = s3_init,
.close = s3_close,
.reset = s3_reset,
{ .available = NULL },
.speed_changed = s3_speed_changed,
.force_redraw = s3_force_redraw,
.config = s3_standard_config
};
const device_t s3_phoenix_trio64_pci_device = {
.name = "S3 Trio64 PCI (Phoenix)",
.internal_name = "px_trio64_pci",
.flags = DEVICE_PCI,
.local = S3_PHOENIX_TRIO64,
.init = s3_init,
.close = s3_close,
.reset = s3_reset,
{ .available = s3_phoenix_trio64_available },
.speed_changed = s3_speed_changed,
.force_redraw = s3_force_redraw,
.config = s3_standard_config
};
const device_t s3_stb_powergraph_64_video_vlb_device = {
.name = "S3 Trio64V+ (STB PowerGraph 64 Video) VLB",
.internal_name = "stb_trio64vplus_vlb",
.flags = DEVICE_VLB,
.local = S3_STB_POWERGRAPH_64_VIDEO,
.init = s3_init,
.close = s3_close,
.reset = s3_reset,
{ .available = s3_stb_powergraph_64_video_available },
.speed_changed = s3_speed_changed,
.force_redraw = s3_force_redraw,
.config = s3_phoenix_trio32_config
};
const device_t s3_phoenix_trio64vplus_onboard_pci_device = {
.name = "S3 Trio64V+ PCI On-Board (Phoenix)",
.internal_name = "px_trio64vplus_onboard_pci",
.flags = DEVICE_PCI,
.local = S3_PHOENIX_TRIO64VPLUS_ONBOARD,
.init = s3_init,
.close = s3_close,
.reset = s3_reset,
{ .available = NULL },
.speed_changed = s3_speed_changed,
.force_redraw = s3_force_redraw,
.config = s3_standard_config
};
const device_t s3_phoenix_trio64vplus_pci_device = {
.name = "S3 Trio64V+ PCI (Phoenix)",
.internal_name = "px_trio64vplus_pci",
.flags = DEVICE_PCI,
.local = S3_PHOENIX_TRIO64VPLUS,
.init = s3_init,
.close = s3_close,
.reset = s3_reset,
{ .available = s3_phoenix_trio64vplus_available },
.speed_changed = s3_speed_changed,
.force_redraw = s3_force_redraw,
.config = s3_standard_config
};
const device_t s3_cardex_trio64vplus_pci_device = {
.name = "S3 Trio64V+ PCI (Cardex)",
.internal_name = "cardex_trio64vplus_pci",
.flags = DEVICE_PCI,
.local = S3_CARDEX_TRIO64VPLUS,
.init = s3_init,
.close = s3_close,
.reset = s3_reset,
{ .available = s3_cardex_trio64vplus_available },
.speed_changed = s3_speed_changed,
.force_redraw = s3_force_redraw,
.config = s3_standard_config
};
const device_t s3_phoenix_vision864_vlb_device = {
.name = "S3 Vision864 VLB (Phoenix)",
.internal_name = "px_vision864_vlb",
.flags = DEVICE_VLB,
.local = S3_PHOENIX_VISION864,
.init = s3_init,
.close = s3_close,
.reset = s3_reset,
{ .available = s3_phoenix_vision864_available },
.speed_changed = s3_speed_changed,
.force_redraw = s3_force_redraw,
.config = s3_standard_config
};
const device_t s3_phoenix_vision864_pci_device = {
.name = "S3 Vision864 PCI (Phoenix)",
.internal_name = "px_vision864_pci",
.flags = DEVICE_PCI,
.local = S3_PHOENIX_VISION864,
.init = s3_init,
.close = s3_close,
.reset = s3_reset,
{ .available = s3_phoenix_vision864_available },
.speed_changed = s3_speed_changed,
.force_redraw = s3_force_redraw,
.config = s3_standard_config
};
const device_t s3_9fx_531_pci_device = {
.name = "S3 Vision868 PCI (Number 9 9FX 531)",
.internal_name = "n9_9fx_531_pci",
.flags = DEVICE_PCI,
.local = S3_NUMBER9_9FX_531,
.init = s3_init,
.close = s3_close,
.reset = s3_reset,
{ .available = s3_9fx_531_available },
.speed_changed = s3_speed_changed,
.force_redraw = s3_force_redraw,
.config = s3_9fx_config
};
const device_t s3_phoenix_vision868_pci_device = {
.name = "S3 Vision868 PCI (Phoenix)",
.internal_name = "px_vision868_pci",
.flags = DEVICE_PCI,
.local = S3_PHOENIX_VISION868,
.init = s3_init,
.close = s3_close,
.reset = s3_reset,
{ .available = s3_phoenix_vision868_available },
.speed_changed = s3_speed_changed,
.force_redraw = s3_force_redraw,
.config = s3_standard_config
};
const device_t s3_diamond_stealth64_vlb_device = {
.name = "S3 Trio64 VLB (Diamond Stealth64 DRAM)",
.internal_name = "stealth64d_vlb",
.flags = DEVICE_VLB,
.local = S3_DIAMOND_STEALTH64_764,
.init = s3_init,
.close = s3_close,
.reset = s3_reset,
{ .available = s3_diamond_stealth64_764_available },
.speed_changed = s3_speed_changed,
.force_redraw = s3_force_redraw,
.config = s3_9fx_config
};
const device_t s3_diamond_stealth64_pci_device = {
.name = "S3 Trio64 PCI (Diamond Stealth64 DRAM)",
.internal_name = "stealth64d_pci",
.flags = DEVICE_PCI,
.local = S3_DIAMOND_STEALTH64_764,
.init = s3_init,
.close = s3_close,
.reset = s3_reset,
{ .available = s3_diamond_stealth64_764_available },
.speed_changed = s3_speed_changed,
.force_redraw = s3_force_redraw,
.config = s3_9fx_config
};
const device_t s3_spea_mirage_p64_vlb_device = {
.name = "S3 Trio64 VLB (SPEA Mirage P64)",
.internal_name = "spea_miragep64_vlb",
.flags = DEVICE_VLB,
.local = S3_SPEA_MIRAGE_P64,
.init = s3_init,
.close = s3_close,
.reset = s3_reset,
{ .available = s3_spea_mirage_p64_vlb_available },
.speed_changed = s3_speed_changed,
.force_redraw = s3_force_redraw,
.config = s3_9fx_config
};
const device_t s3_elsa_winner2000_pro_x_964_pci_device = {
.name = "S3 Vision964 PCI (ELSA Winner 2000 Pro/X)",
.internal_name = "elsawin2kprox_964_pci",
.flags = DEVICE_PCI,
.local = S3_ELSAWIN2KPROX_964,
.init = s3_init,
.close = s3_close,
.reset = s3_reset,
{ .available = s3_elsa_winner2000_pro_x_964_available },
.speed_changed = s3_speed_changed,
.force_redraw = s3_force_redraw,
.config = s3_968_config
};
const device_t s3_elsa_winner2000_pro_x_pci_device = {
.name = "S3 Vision968 PCI (ELSA Winner 2000 Pro/X)",
.internal_name = "elsawin2kprox_pci",
.flags = DEVICE_PCI,
.local = S3_ELSAWIN2KPROX,
.init = s3_init,
.close = s3_close,
.reset = s3_reset,
{ .available = s3_elsa_winner2000_pro_x_available },
.speed_changed = s3_speed_changed,
.force_redraw = s3_force_redraw,
.config = s3_968_config
};
const device_t s3_trio64v2_dx_pci_device = {
.name = "S3 Trio64V2/DX PCI",
.internal_name = "trio64v2dx_pci",
.flags = DEVICE_PCI,
.local = S3_TRIO64V2_DX,
.init = s3_init,
.close = s3_close,
.reset = s3_reset,
{ .available = s3_trio64v2_dx_available },
.speed_changed = s3_speed_changed,
.force_redraw = s3_force_redraw,
.config = s3_standard_config
};
const device_t s3_trio64v2_dx_onboard_pci_device = {
.name = "S3 Trio64V2/DX On-Board PCI",
.internal_name = "trio64v2dx_onboard_pci",
.flags = DEVICE_PCI,
.local = S3_TRIO64V2_DX_ONBOARD,
.init = s3_init,
.close = s3_close,
.reset = NULL,
{ .available = NULL },
.speed_changed = s3_speed_changed,
.force_redraw = s3_force_redraw,
.config = s3_standard_config
};
``` | /content/code_sandbox/src/video/vid_s3.c | c | 2016-06-25T22:29:10 | 2024-08-16T19:09:21 | 86Box | 86Box/86Box | 2,616 | 126,841 |
```c
/*
* 86Box A hypervisor and IBM PC system emulator that specializes in
* running old operating systems and software designed for IBM
* PC systems and compatibles from 1981 through fairly recent
* system designs based on the PCI bus.
*
* This file is part of the 86Box distribution.
*
* Emulation of a Sierra SC1502X RAMDAC.
*
* Used by the TLIVESA1 driver for ET4000.
*
*
*
* Authors: Sarah Walker, <path_to_url
* Miran Grca, <mgrca8@gmail.com>
*
*/
#include <stdio.h>
#include <stdint.h>
#include <stdlib.h>
#include <string.h>
#include <wchar.h>
#include <86box/86box.h>
#include <86box/device.h>
#include <86box/mem.h>
#include <86box/timer.h>
#include <86box/video.h>
#include <86box/vid_svga.h>
#include <86box/plat_unused.h>
typedef struct sc1502x_ramdac_t {
int state;
uint8_t ctrl;
uint8_t idx;
uint8_t regs[256];
uint32_t pixel_mask;
uint8_t enable_ext;
} sc1502x_ramdac_t;
static void
sc1502x_ramdac_bpp(uint8_t val, sc1502x_ramdac_t *ramdac, svga_t *svga)
{
int oldbpp = 0;
if (val == 0xff)
return;
ramdac->ctrl = val;
oldbpp = svga->bpp;
switch ((val & 1) | ((val & 0xc0) >> 5)) {
case 0:
svga->bpp = 8;
break;
case 2:
case 3:
switch (val & 0x20) {
case 0x00:
svga->bpp = 32;
break;
case 0x20:
svga->bpp = 24;
break;
default:
break;
}
break;
case 4:
case 5:
svga->bpp = 15;
break;
case 6:
svga->bpp = 16;
break;
case 7:
if (val & 4) {
switch (val & 0x20) {
case 0x00:
svga->bpp = 32;
break;
case 0x20:
svga->bpp = 24;
break;
default:
break;
}
} else
svga->bpp = 16;
break;
default:
break;
}
if (oldbpp != svga->bpp)
svga_recalctimings(svga);
}
void
sc1502x_ramdac_out(uint16_t addr, uint8_t val, void *priv, svga_t *svga)
{
sc1502x_ramdac_t *ramdac = (sc1502x_ramdac_t *) priv;
switch (addr) {
case 0x3C6:
if (ramdac->state == 0)
ramdac->enable_ext = (val == 0x10);
if (ramdac->state == 4) {
ramdac->state = 0;
sc1502x_ramdac_bpp(val, ramdac, svga);
return;
}
ramdac->state = 0;
break;
case 0x3C7:
if (ramdac->enable_ext) {
ramdac->idx = val;
return;
}
ramdac->state = 0;
break;
case 0x3C8:
if (ramdac->enable_ext) {
switch (ramdac->idx) {
case 8:
ramdac->regs[ramdac->idx] = val;
svga_set_ramdac_type(svga, (ramdac->regs[ramdac->idx] & 1) ? RAMDAC_8BIT : RAMDAC_6BIT);
break;
case 0x0d:
ramdac->pixel_mask = val & svga->dac_mask;
break;
case 0x0e:
ramdac->pixel_mask |= ((val & svga->dac_mask) << 8);
break;
case 0x0f:
ramdac->pixel_mask |= ((val & svga->dac_mask) << 16);
break;
default:
ramdac->regs[ramdac->idx] = val;
break;
}
return;
}
ramdac->state = 0;
break;
case 0x3C9:
if (ramdac->enable_ext)
return;
ramdac->state = 0;
break;
default:
break;
}
svga_out(addr, val, svga);
}
uint8_t
sc1502x_ramdac_in(uint16_t addr, void *priv, svga_t *svga)
{
sc1502x_ramdac_t *ramdac = (sc1502x_ramdac_t *) priv;
uint8_t temp = svga_in(addr, svga);
switch (addr) {
case 0x3C6:
if (ramdac->state == 4) {
ramdac->state = 0;
temp = ramdac->ctrl;
break;
}
ramdac->state++;
break;
case 0x3C7:
ramdac->state = 0;
break;
case 0x3C8:
if (ramdac->enable_ext) {
switch (ramdac->idx) {
case 9:
temp = 0x53;
break;
case 0x0a:
temp = 0x3a;
break;
case 0x0b:
temp = 0xb1;
break;
case 0x0c:
temp = 0x41;
break;
case 0x0d:
temp = ramdac->pixel_mask & 0xff;
break;
case 0x0e:
temp = ramdac->pixel_mask >> 8;
break;
case 0x0f:
temp = ramdac->pixel_mask >> 16;
break;
default:
temp = ramdac->regs[ramdac->idx];
break;
}
} else
ramdac->state = 0;
break;
case 0x3C9:
if (ramdac->enable_ext)
temp = ramdac->idx;
else
ramdac->state = 0;
break;
default:
break;
}
return temp;
}
static void *
sc1502x_ramdac_init(UNUSED(const device_t *info))
{
sc1502x_ramdac_t *ramdac = (sc1502x_ramdac_t *) malloc(sizeof(sc1502x_ramdac_t));
memset(ramdac, 0, sizeof(sc1502x_ramdac_t));
ramdac->ctrl = 0;
ramdac->pixel_mask = 0xffffff;
return ramdac;
}
static void
sc1502x_ramdac_close(void *priv)
{
sc1502x_ramdac_t *ramdac = (sc1502x_ramdac_t *) priv;
if (ramdac)
free(ramdac);
}
const device_t sc1502x_ramdac_device = {
.name = "Sierra SC1502x RAMDAC",
.internal_name = "sc1502x_ramdac",
.flags = 0,
.local = 0,
.init = sc1502x_ramdac_init,
.close = sc1502x_ramdac_close,
.reset = NULL,
{ .available = NULL },
.speed_changed = NULL,
.force_redraw = NULL,
.config = NULL
};
``` | /content/code_sandbox/src/video/vid_sc1502x_ramdac.c | c | 2016-06-25T22:29:10 | 2024-08-16T19:09:21 | 86Box | 86Box/86Box | 2,616 | 1,748 |
```c
/*
* 86Box A hypervisor and IBM PC system emulator that specializes in
* running old operating systems and software designed for IBM
* PC systems and compatibles from 1981 through fairly recent
* system designs based on the PCI bus.
*
* This file is part of the 86Box distribution.
*
* Emulation of the TI CF62011 SVGA chip.
*
* This chip was used in several of IBM's later machines, such
* as the PS/1 Model 2121, and a number of PS/2 models. As noted
* in an article on Usenet:
*
* "In the early 90s IBM looked for some cheap VGA card to
* substitute the (relatively) expensive XGA-2 adapter for
* *servers*, where the primary purpose is supervision of the
* machine rather than real *work* with it in Hi-Res. It was
* just to supply a base video, where a XGA-2 were a waste of
* potential. They had a contract with TI for some DSPs in
* multimedia already (the MWave for instance is based on
* TI-DSPs as well as many Thinkpad internal chipsets) and TI
* offered them a rather cheap and inexpensive chipset
* and combined it with a cheap clock oscillator and an Inmos
* RAMDAC. That chipset was already pretty much outdated at
* that time but IBM decided it would suffice for that low
* end purpose.
*
* Driver support was given under DOS and OS/2 only for base
* functions like selection of the vertical refresh and few
* different modes only. Not even the Win 3.x support has
* been finalized. Technically the adapter could do better
* than VGA, but its video BIOS is largely undocumented and
* intentionally crippled down to a few functions."
*
* This chip is reportedly the same one as used in the MCA
* IBM SVGA Adapter/A (ID 090EEh), which mostly had faster
* VRAM and RAMDAC. The VESA DOS graphics driver for that
* card can be used: m95svga.exe
*
* The controller responds at ports in the range 0x2100-0x210F,
* which are the same as the XGA. It supports up to 1MB of VRAM,
* but we lock it down to 512K. The PS/1 2122 had 256K.
*
*
*
* Authors: Sarah Walker, <path_to_url
* Miran Grca, <mgrca8@gmail.com>
* Fred N. van Kempen, <decwiz@yahoo.com>
*
*/
#include <stdio.h>
#include <stdint.h>
#include <stdlib.h>
#include <string.h>
#include <wchar.h>
#include <86box/86box.h>
#include <86box/io.h>
#include <86box/timer.h>
#include <86box/mem.h>
#include <86box/rom.h>
#include <86box/device.h>
#include <86box/video.h>
#include <86box/vid_svga.h>
typedef struct {
svga_t svga;
rom_t bios_rom;
int enabled;
uint32_t vram_size;
uint8_t banking;
uint8_t reg_2100;
uint8_t reg_210a;
} tivga_t;
static video_timings_t timing_ti_cf62011 = { .type = VIDEO_ISA, .write_b = 6, .write_w = 8, .write_l = 16, .read_b = 6, .read_w = 8, .read_l = 16 };
static void
vid_out(uint16_t addr, uint8_t val, void *priv)
{
tivga_t *ti = (tivga_t *) priv;
svga_t *svga = &ti->svga;
uint8_t old;
#if 0
if (((addr & 0xfff0) == 0x03d0 || (addr & 0xfff0) == 0x03b0) &&
!(svga->miscout & 1)) addr ^= 0x60;
#endif
switch (addr) {
case 0x0102:
ti->enabled = (val & 0x01);
return;
case 0x03d4:
svga->crtcreg = val & 0x3f;
return;
case 0x03d5:
if (svga->crtcreg & 0x20)
return;
if ((svga->crtcreg < 7) && (svga->crtc[0x11] & 0x80))
return;
if ((svga->crtcreg == 7) && (svga->crtc[0x11] & 0x80))
val = (svga->crtc[7] & ~0x10) | (val & 0x10);
old = svga->crtc[svga->crtcreg];
svga->crtc[svga->crtcreg] = val;
if (old != val) {
if (svga->crtcreg < 0xe || svga->crtcreg > 0x10) {
svga->fullchange = changeframecount;
svga_recalctimings(svga);
}
}
break;
case 0x2100:
ti->reg_2100 = val;
if ((val & 7) < 4)
svga->read_bank = svga->write_bank = 0;
else
svga->read_bank = svga->write_bank = (ti->banking & 0x7) * 0x10000;
break;
case 0x2108:
if ((ti->reg_2100 & 7) >= 4)
svga->read_bank = svga->write_bank = (val & 0x7) * 0x10000;
ti->banking = val;
break;
case 0x210a:
ti->reg_210a = val;
break;
default:
break;
}
svga_out(addr, val, svga);
}
static uint8_t
vid_in(uint16_t addr, void *priv)
{
tivga_t *ti = (tivga_t *) priv;
svga_t *svga = &ti->svga;
uint8_t ret;
#if 0
if (((addr & 0xfff0) == 0x03d0 || (addr & 0xfff0) == 0x03b0) &&
!(svga->miscout & 1)) addr ^= 0x60;
#endif
switch (addr) {
case 0x0100:
ret = 0xfe;
break;
case 0x0101:
ret = 0xe8;
break;
case 0x0102:
ret = ti->enabled;
break;
case 0x03d4:
ret = svga->crtcreg;
break;
case 0x03d5:
if (svga->crtcreg & 0x20)
ret = 0xff;
else
ret = svga->crtc[svga->crtcreg];
break;
case 0x2100:
ret = ti->reg_2100;
break;
case 0x2108:
ret = ti->banking;
break;
case 0x210a:
ret = ti->reg_210a;
break;
default:
ret = svga_in(addr, svga);
break;
}
return ret;
}
static void
vid_speed_changed(void *priv)
{
tivga_t *ti = (tivga_t *) priv;
svga_recalctimings(&ti->svga);
}
static void
vid_force_redraw(void *priv)
{
tivga_t *ti = (tivga_t *) priv;
ti->svga.fullchange = changeframecount;
}
static void
vid_close(void *priv)
{
tivga_t *ti = (tivga_t *) priv;
svga_close(&ti->svga);
free(ti);
}
static void *
vid_init(const device_t *info)
{
tivga_t *ti;
/* Allocate control block and initialize. */
ti = (tivga_t *) malloc(sizeof(tivga_t));
memset(ti, 0x00, sizeof(tivga_t));
/* Set amount of VRAM in KB. */
if (info->local == 0)
ti->vram_size = device_get_config_int("vram_size");
else
ti->vram_size = info->local;
video_inform(VIDEO_FLAG_TYPE_SPECIAL, &timing_ti_cf62011);
svga_init(info, &ti->svga, ti,
ti->vram_size << 10,
NULL, vid_in, vid_out, NULL, NULL);
io_sethandler(0x0100, 2, vid_in, NULL, NULL, NULL, NULL, NULL, ti);
io_sethandler(0x03c0, 32, vid_in, NULL, NULL, vid_out, NULL, NULL, ti);
io_sethandler(0x2100, 16, vid_in, NULL, NULL, vid_out, NULL, NULL, ti);
ti->svga.bpp = 8;
ti->svga.miscout = 1;
return ti;
}
const device_t ibm_ps1_2121_device = {
.name = "IBM PS/1 Model 2121 SVGA",
.internal_name = "ibm_ps1_2121",
.flags = DEVICE_ISA,
.local = 512,
.init = vid_init,
.close = vid_close,
.reset = NULL,
{ .available = NULL },
.speed_changed = vid_speed_changed,
.force_redraw = vid_force_redraw,
.config = NULL
};
``` | /content/code_sandbox/src/video/vid_ti_cf62011.c | c | 2016-06-25T22:29:10 | 2024-08-16T19:09:21 | 86Box | 86Box/86Box | 2,616 | 2,254 |
```c
/*
* 86Box A hypervisor and IBM PC system emulator that specializes in
* running old operating systems and software designed for IBM
* PC systems and compatibles from 1981 through fairly recent
* system designs based on the PCI bus.
*
* This file is part of the 86Box distribution.
*
* 3DFX Voodoo emulation.
*
*
*
* Authors: Sarah Walker, <path_to_url
*
*/
#include <assert.h>
#include <stdarg.h>
#include <stdio.h>
#include <stdint.h>
#include <string.h>
#include <stdlib.h>
#include <stddef.h>
#include <wchar.h>
#include <math.h>
#define HAVE_STDARG_H
#include <86box/86box.h>
#include "cpu.h"
#include <86box/machine.h>
#include <86box/device.h>
#include <86box/mem.h>
#include <86box/timer.h>
#include <86box/device.h>
#include <86box/plat.h>
#include <86box/thread.h>
#include <86box/video.h>
#include <86box/vid_svga.h>
#include <86box/vid_voodoo_common.h>
#include <86box/vid_voodoo_display.h>
#include <86box/vid_voodoo_regs.h>
#include <86box/vid_voodoo_render.h>
#ifdef ENABLE_VOODOODISP_LOG
int voodoodisp_do_log = ENABLE_VOODOODISP_LOG;
static void
voodoodisp_log(const char *fmt, ...)
{
va_list ap;
if (voodoodisp_do_log) {
va_start(ap, fmt);
pclog_ex(fmt, ap);
va_end(ap);
}
}
#else
# define voodoodisp_log(fmt, ...)
#endif
void
voodoo_update_ncc(voodoo_t *voodoo, int tmu)
{
for (uint8_t tbl = 0; tbl < 2; tbl++) {
for (uint16_t col = 0; col < 256; col++) {
int y = (col >> 4);
int i = (col >> 2) & 3;
int q = col & 3;
int i_r;
int i_g;
int i_b;
int q_r;
int q_g;
int q_b;
y = (voodoo->nccTable[tmu][tbl].y[y >> 2] >> ((y & 3) * 8)) & 0xff;
i_r = (voodoo->nccTable[tmu][tbl].i[i] >> 18) & 0x1ff;
if (i_r & 0x100)
i_r |= 0xfffffe00;
i_g = (voodoo->nccTable[tmu][tbl].i[i] >> 9) & 0x1ff;
if (i_g & 0x100)
i_g |= 0xfffffe00;
i_b = voodoo->nccTable[tmu][tbl].i[i] & 0x1ff;
if (i_b & 0x100)
i_b |= 0xfffffe00;
q_r = (voodoo->nccTable[tmu][tbl].q[q] >> 18) & 0x1ff;
if (q_r & 0x100)
q_r |= 0xfffffe00;
q_g = (voodoo->nccTable[tmu][tbl].q[q] >> 9) & 0x1ff;
if (q_g & 0x100)
q_g |= 0xfffffe00;
q_b = voodoo->nccTable[tmu][tbl].q[q] & 0x1ff;
if (q_b & 0x100)
q_b |= 0xfffffe00;
voodoo->ncc_lookup[tmu][tbl][col].rgba.r = CLAMP(y + i_r + q_r);
voodoo->ncc_lookup[tmu][tbl][col].rgba.g = CLAMP(y + i_g + q_g);
voodoo->ncc_lookup[tmu][tbl][col].rgba.b = CLAMP(y + i_b + q_b);
voodoo->ncc_lookup[tmu][tbl][col].rgba.a = 0xff;
}
}
}
void
voodoo_pixelclock_update(voodoo_t *voodoo)
{
int m = (voodoo->dac_pll_regs[0] & 0x7f) + 2;
int n1 = ((voodoo->dac_pll_regs[0] >> 8) & 0x1f) + 2;
int n2 = ((voodoo->dac_pll_regs[0] >> 13) & 0x07);
float t = (14318184.0 * ((float) m / (float) n1)) / (float) (1 << n2);
double clock_const;
int line_length;
if ((voodoo->dac_data[6] & 0xf0) == 0x20 || (voodoo->dac_data[6] & 0xf0) == 0x60 || (voodoo->dac_data[6] & 0xf0) == 0x70)
t /= 2.0f;
line_length = (voodoo->hSync & 0xff) + ((voodoo->hSync >> 16) & 0x3ff);
// voodoodisp_log("Pixel clock %f MHz hsync %08x line_length %d\n", t, voodoo->hSync, line_length);
voodoo->pixel_clock = t;
clock_const = cpuclock / t;
voodoo->line_time = (uint64_t) ((double) line_length * clock_const * (double) (1ULL << 32));
}
static void
voodoo_calc_clutData(voodoo_t *voodoo)
{
int c;
for (c = 0; c < 256; c++) {
voodoo->clutData256[c].r = (voodoo->clutData[c >> 3].r * (8 - (c & 7)) + voodoo->clutData[(c >> 3) + 1].r * (c & 7)) >> 3;
voodoo->clutData256[c].g = (voodoo->clutData[c >> 3].g * (8 - (c & 7)) + voodoo->clutData[(c >> 3) + 1].g * (c & 7)) >> 3;
voodoo->clutData256[c].b = (voodoo->clutData[c >> 3].b * (8 - (c & 7)) + voodoo->clutData[(c >> 3) + 1].b * (c & 7)) >> 3;
}
for (c = 0; c < 65536; c++) {
int r = (c >> 8) & 0xf8;
int g = (c >> 3) & 0xfc;
int b = (c << 3) & 0xf8;
#if 0
r |= (r >> 5);
g |= (g >> 6);
b |= (b >> 5);
#endif
voodoo->video_16to32[c] = (voodoo->clutData256[r].r << 16) | (voodoo->clutData256[g].g << 8) | voodoo->clutData256[b].b;
}
}
#define FILTDIV 256
static int FILTCAP;
static int FILTCAPG;
static int FILTCAPB = 0; /* color filter threshold values */
void
voodoo_generate_filter_v1(voodoo_t *voodoo)
{
float difference;
float diffg;
float diffb;
float thiscol;
float thiscolg;
float thiscolb;
float lined;
float fcr;
float fcg;
float fcb;
fcr = FILTCAP * 5;
fcg = FILTCAPG * 6;
fcb = FILTCAPB * 5;
for (uint16_t g = 0; g < FILTDIV; g++) // pixel 1
{
for (uint16_t h = 0; h < FILTDIV; h++) // pixel 2
{
difference = (float) (h - g);
diffg = difference;
diffb = difference;
thiscol = thiscolg = thiscolb = g;
if (difference > FILTCAP)
difference = FILTCAP;
if (difference < -FILTCAP)
difference = -FILTCAP;
if (diffg > FILTCAPG)
diffg = FILTCAPG;
if (diffg < -FILTCAPG)
diffg = -FILTCAPG;
if (diffb > FILTCAPB)
diffb = FILTCAPB;
if (diffb < -FILTCAPB)
diffb = -FILTCAPB;
// hack - to make it not bleed onto black
// if (g == 0){
// difference = diffg = diffb = 0;
//}
if ((difference < fcr) || (-difference > -fcr))
thiscol = g + (difference / 2);
if ((diffg < fcg) || (-diffg > -fcg))
thiscolg = g + (diffg / 2); /* need these divides so we can actually undither! */
if ((diffb < fcb) || (-diffb > -fcb))
thiscolb = g + (diffb / 2);
if (thiscol < 0)
thiscol = 0;
if (thiscol > FILTDIV - 1)
thiscol = FILTDIV - 1;
if (thiscolg < 0)
thiscolg = 0;
if (thiscolg > FILTDIV - 1)
thiscolg = FILTDIV - 1;
if (thiscolb < 0)
thiscolb = 0;
if (thiscolb > FILTDIV - 1)
thiscolb = FILTDIV - 1;
voodoo->thefilter[g][h] = thiscol;
voodoo->thefilterg[g][h] = thiscolg;
voodoo->thefilterb[g][h] = thiscolb;
}
lined = g + 4;
if (lined > 255)
lined = 255;
voodoo->purpleline[g][0] = lined;
voodoo->purpleline[g][2] = lined;
lined = g + 0;
if (lined > 255)
lined = 255;
voodoo->purpleline[g][1] = lined;
}
}
void
voodoo_generate_filter_v2(voodoo_t *voodoo)
{
float difference;
float thiscol;
float thiscolg;
float thiscolb;
float clr;
float clg;
float clb = 0;
float fcr;
float fcg;
float fcb = 0;
// pre-clamping
fcr = FILTCAP;
fcg = FILTCAPG;
fcb = FILTCAPB;
if (fcr > 32)
fcr = 32;
if (fcg > 32)
fcg = 32;
if (fcb > 32)
fcb = 32;
for (uint16_t g = 0; g < 256; g++) // pixel 1 - our target pixel we want to bleed into
{
for (uint16_t h = 0; h < 256; h++) // pixel 2 - our main pixel
{
float avg;
float avgdiff;
difference = (float) (g - h);
avg = (float) ((g + g + g + g + h) / 5);
avgdiff = avg - (float) ((g + h + h + h + h) / 5);
if (avgdiff < 0)
avgdiff *= -1;
if (difference < 0)
difference *= -1;
thiscol = thiscolg = thiscolb = g;
// try lighten
if (h > g) {
clr = clg = clb = avgdiff;
if (clr > fcr)
clr = fcr;
if (clg > fcg)
clg = fcg;
if (clb > fcb)
clb = fcb;
thiscol = g + clr;
thiscolg = g + clg;
thiscolb = g + clb;
if (thiscol > g + FILTCAP)
thiscol = g + FILTCAP;
if (thiscolg > g + FILTCAPG)
thiscolg = g + FILTCAPG;
if (thiscolb > g + FILTCAPB)
thiscolb = g + FILTCAPB;
if (thiscol > g + avgdiff)
thiscol = g + avgdiff;
if (thiscolg > g + avgdiff)
thiscolg = g + avgdiff;
if (thiscolb > g + avgdiff)
thiscolb = g + avgdiff;
}
if (difference > FILTCAP)
thiscol = g;
if (difference > FILTCAPG)
thiscolg = g;
if (difference > FILTCAPB)
thiscolb = g;
// clamp
if (thiscol < 0)
thiscol = 0;
if (thiscolg < 0)
thiscolg = 0;
if (thiscolb < 0)
thiscolb = 0;
if (thiscol > 255)
thiscol = 255;
if (thiscolg > 255)
thiscolg = 255;
if (thiscolb > 255)
thiscolb = 255;
// add to the table
voodoo->thefilter[g][h] = thiscol;
voodoo->thefilterg[g][h] = thiscolg;
voodoo->thefilterb[g][h] = thiscolb;
// debug the ones that don't give us much of a difference
// if (difference < FILTCAP)
// voodoodisp_log("Voodoofilter: %ix%i - %f difference, %f average difference, R=%f, G=%f, B=%f\n", g, h, difference, avgdiff, thiscol, thiscolg, thiscolb);
}
}
}
void
voodoo_threshold_check(voodoo_t *voodoo)
{
int r;
int g;
int b;
if (!voodoo->scrfilterEnabled)
return; /* considered disabled; don't check and generate */
/* Check for changes, to generate anew table */
if (voodoo->scrfilterThreshold != voodoo->scrfilterThresholdOld) {
r = (voodoo->scrfilterThreshold >> 16) & 0xFF;
g = (voodoo->scrfilterThreshold >> 8) & 0xFF;
b = voodoo->scrfilterThreshold & 0xFF;
FILTCAP = r;
FILTCAPG = g;
FILTCAPB = b;
voodoodisp_log("Voodoo Filter Threshold Check: %06x - RED %i GREEN %i BLUE %i\n", voodoo->scrfilterThreshold, r, g, b);
voodoo->scrfilterThresholdOld = voodoo->scrfilterThreshold;
if (voodoo->type == VOODOO_2)
voodoo_generate_filter_v2(voodoo);
else
voodoo_generate_filter_v1(voodoo);
if (voodoo->type >= VOODOO_BANSHEE)
voodoo_generate_vb_filters(voodoo, FILTCAP, FILTCAPG);
}
}
static void
voodoo_filterline_v1(voodoo_t *voodoo, uint8_t *fil, int column, uint16_t *src, int line)
{
// Scratchpad for avoiding feedback streaks
uint8_t fil3[4096 * 3];
assert(voodoo->h_disp <= 4096);
/* 16 to 32-bit */
for (int x = 0; x < column; x++) {
fil[x * 3] = ((src[x] & 31) << 3);
fil[x * 3 + 1] = (((src[x] >> 5) & 63) << 2);
fil[x * 3 + 2] = (((src[x] >> 11) & 31) << 3);
// Copy to our scratchpads
fil3[x * 3 + 0] = fil[x * 3 + 0];
fil3[x * 3 + 1] = fil[x * 3 + 1];
fil3[x * 3 + 2] = fil[x * 3 + 2];
}
/* lines */
if (line & 1) {
for (int x = 0; x < column; x++) {
fil[x * 3] = voodoo->purpleline[fil[x * 3]][0];
fil[x * 3 + 1] = voodoo->purpleline[fil[x * 3 + 1]][1];
fil[x * 3 + 2] = voodoo->purpleline[fil[x * 3 + 2]][2];
}
}
/* filtering time */
for (int x = 1; x < column; x++) {
fil3[x * 3] = voodoo->thefilterb[fil[x * 3]][fil[(x - 1) * 3]];
fil3[x * 3 + 1] = voodoo->thefilterg[fil[x * 3 + 1]][fil[(x - 1) * 3 + 1]];
fil3[x * 3 + 2] = voodoo->thefilter[fil[x * 3 + 2]][fil[(x - 1) * 3 + 2]];
}
for (int x = 1; x < column; x++) {
fil[x * 3] = voodoo->thefilterb[fil3[x * 3]][fil3[(x - 1) * 3]];
fil[x * 3 + 1] = voodoo->thefilterg[fil3[x * 3 + 1]][fil3[(x - 1) * 3 + 1]];
fil[x * 3 + 2] = voodoo->thefilter[fil3[x * 3 + 2]][fil3[(x - 1) * 3 + 2]];
}
for (int x = 1; x < column; x++) {
fil3[x * 3] = voodoo->thefilterb[fil[x * 3]][fil[(x - 1) * 3]];
fil3[x * 3 + 1] = voodoo->thefilterg[fil[x * 3 + 1]][fil[(x - 1) * 3 + 1]];
fil3[x * 3 + 2] = voodoo->thefilter[fil[x * 3 + 2]][fil[(x - 1) * 3 + 2]];
}
for (int x = 0; x < column - 1; x++) {
fil[x * 3] = voodoo->thefilterb[fil3[x * 3]][fil3[(x + 1) * 3]];
fil[x * 3 + 1] = voodoo->thefilterg[fil3[x * 3 + 1]][fil3[(x + 1) * 3 + 1]];
fil[x * 3 + 2] = voodoo->thefilter[fil3[x * 3 + 2]][fil3[(x + 1) * 3 + 2]];
}
}
static void
voodoo_filterline_v2(voodoo_t *voodoo, uint8_t *fil, int column, uint16_t *src, UNUSED(int line))
{
int x;
// Scratchpad for blending filter
uint8_t fil3[4096 * 3];
assert(voodoo->h_disp <= 4096);
/* 16 to 32-bit */
for (x = 0; x < column; x++) {
// Blank scratchpads
fil3[x * 3 + 0] = fil[x * 3 + 0] = ((src[x] & 31) << 3);
fil3[x * 3 + 1] = fil[x * 3 + 1] = (((src[x] >> 5) & 63) << 2);
fil3[x * 3 + 2] = fil[x * 3 + 2] = (((src[x] >> 11) & 31) << 3);
}
/* filtering time */
for (x = 1; x < column - 3; x++) {
fil3[(x + 3) * 3] = voodoo->thefilterb[(src[x + 3] & 31) << 3][(src[x] & 31) << 3];
fil3[(x + 3) * 3 + 1] = voodoo->thefilterg[((src[x + 3] >> 5) & 63) << 2][((src[x] >> 5) & 63) << 2];
fil3[(x + 3) * 3 + 2] = voodoo->thefilter[((src[x + 3] >> 11) & 31) << 3][((src[x] >> 11) & 31) << 3];
fil[(x + 2) * 3] = voodoo->thefilterb[fil3[(x + 2) * 3]][(src[x] & 31) << 3];
fil[(x + 2) * 3 + 1] = voodoo->thefilterg[fil3[(x + 2) * 3 + 1]][((src[x] >> 5) & 63) << 2];
fil[(x + 2) * 3 + 2] = voodoo->thefilter[fil3[(x + 2) * 3 + 2]][((src[x] >> 11) & 31) << 3];
fil3[(x + 1) * 3] = voodoo->thefilterb[fil[(x + 1) * 3]][(src[x] & 31) << 3];
fil3[(x + 1) * 3 + 1] = voodoo->thefilterg[fil[(x + 1) * 3 + 1]][((src[x] >> 5) & 63) << 2];
fil3[(x + 1) * 3 + 2] = voodoo->thefilter[fil[(x + 1) * 3 + 2]][((src[x] >> 11) & 31) << 3];
fil[(x - 1) * 3] = voodoo->thefilterb[fil3[(x - 1) * 3]][(src[x] & 31) << 3];
fil[(x - 1) * 3 + 1] = voodoo->thefilterg[fil3[(x - 1) * 3 + 1]][((src[x] >> 5) & 63) << 2];
fil[(x - 1) * 3 + 2] = voodoo->thefilter[fil3[(x - 1) * 3 + 2]][((src[x] >> 11) & 31) << 3];
}
// unroll for edge cases
fil3[(column - 3) * 3] = voodoo->thefilterb[(src[column - 3] & 31) << 3][(src[column] & 31) << 3];
fil3[(column - 3) * 3 + 1] = voodoo->thefilterg[((src[column - 3] >> 5) & 63) << 2][((src[column] >> 5) & 63) << 2];
fil3[(column - 3) * 3 + 2] = voodoo->thefilter[((src[column - 3] >> 11) & 31) << 3][((src[column] >> 11) & 31) << 3];
fil3[(column - 2) * 3] = voodoo->thefilterb[(src[column - 2] & 31) << 3][(src[column] & 31) << 3];
fil3[(column - 2) * 3 + 1] = voodoo->thefilterg[((src[column - 2] >> 5) & 63) << 2][((src[column] >> 5) & 63) << 2];
fil3[(column - 2) * 3 + 2] = voodoo->thefilter[((src[column - 2] >> 11) & 31) << 3][((src[column] >> 11) & 31) << 3];
fil3[(column - 1) * 3] = voodoo->thefilterb[(src[column - 1] & 31) << 3][(src[column] & 31) << 3];
fil3[(column - 1) * 3 + 1] = voodoo->thefilterg[((src[column - 1] >> 5) & 63) << 2][((src[column] >> 5) & 63) << 2];
fil3[(column - 1) * 3 + 2] = voodoo->thefilter[((src[column - 1] >> 11) & 31) << 3][((src[column] >> 11) & 31) << 3];
fil[(column - 2) * 3] = voodoo->thefilterb[fil3[(column - 2) * 3]][(src[column] & 31) << 3];
fil[(column - 2) * 3 + 1] = voodoo->thefilterg[fil3[(column - 2) * 3 + 1]][((src[column] >> 5) & 63) << 2];
fil[(column - 2) * 3 + 2] = voodoo->thefilter[fil3[(column - 2) * 3 + 2]][((src[column] >> 11) & 31) << 3];
fil[(column - 1) * 3] = voodoo->thefilterb[fil3[(column - 1) * 3]][(src[column] & 31) << 3];
fil[(column - 1) * 3 + 1] = voodoo->thefilterg[fil3[(column - 1) * 3 + 1]][((src[column] >> 5) & 63) << 2];
fil[(column - 1) * 3 + 2] = voodoo->thefilter[fil3[(column - 1) * 3 + 2]][((src[column] >> 11) & 31) << 3];
fil3[(column - 1) * 3] = voodoo->thefilterb[fil[(column - 1) * 3]][(src[column] & 31) << 3];
fil3[(column - 1) * 3 + 1] = voodoo->thefilterg[fil[(column - 1) * 3 + 1]][((src[column] >> 5) & 63) << 2];
fil3[(column - 1) * 3 + 2] = voodoo->thefilter[fil[(column - 1) * 3 + 2]][((src[column] >> 11) & 31) << 3];
}
void
voodoo_callback(void *priv)
{
voodoo_t *voodoo = (voodoo_t *) priv;
const monitor_t *monitor = &monitors[voodoo->monitor_index];
int v_y_add = (monitor->mon_overscan_y >> 1);
int v_x_add = (monitor->mon_overscan_x >> 1);
if (voodoo->fbiInit0 & FBIINIT0_VGA_PASS) {
if (voodoo->line < voodoo->v_disp) {
voodoo_t *draw_voodoo;
int draw_line;
if (SLI_ENABLED) {
if (voodoo == voodoo->set->voodoos[1])
goto skip_draw;
if (((voodoo->initEnable & INITENABLE_SLI_MASTER_SLAVE) ? 1 : 0) == (voodoo->line & 1))
draw_voodoo = voodoo;
else
draw_voodoo = voodoo->set->voodoos[1];
draw_line = voodoo->line >> 1;
} else {
if (!(voodoo->fbiInit0 & 1))
goto skip_draw;
draw_voodoo = voodoo;
draw_line = voodoo->line;
}
if (draw_voodoo->dirty_line[draw_line]) {
uint32_t *p = &monitor->target_buffer->line[voodoo->line + v_y_add][v_x_add];
uint16_t *src = (uint16_t *) &draw_voodoo->fb_mem[draw_voodoo->front_offset + draw_line * draw_voodoo->row_width];
int x;
draw_voodoo->dirty_line[draw_line] = 0;
if (voodoo->line < voodoo->dirty_line_low) {
voodoo->dirty_line_low = voodoo->line;
video_wait_for_buffer_monitor(voodoo->monitor_index);
}
if (voodoo->line > voodoo->dirty_line_high)
voodoo->dirty_line_high = voodoo->line;
/* Draw left overscan. */
for (x = 0; x < v_x_add; x++)
monitor->target_buffer->line[voodoo->line + v_y_add][x] = 0x00000000;
if (voodoo->scrfilter && voodoo->scrfilterEnabled) {
uint8_t fil[4096 * 3]; /* interleaved 24-bit RGB */
assert(voodoo->h_disp <= 4096);
if (voodoo->type == VOODOO_2)
voodoo_filterline_v2(voodoo, fil, voodoo->h_disp, src, voodoo->line);
else
voodoo_filterline_v1(voodoo, fil, voodoo->h_disp, src, voodoo->line);
for (x = 0; x < voodoo->h_disp; x++) {
p[x] = (voodoo->clutData256[fil[x * 3]].b << 0 | voodoo->clutData256[fil[x * 3 + 1]].g << 8 | voodoo->clutData256[fil[x * 3 + 2]].r << 16);
}
} else {
for (x = 0; x < voodoo->h_disp; x++) {
p[x] = draw_voodoo->video_16to32[src[x]];
}
}
/* Draw right overscan. */
for (x = 0; x < v_x_add; x++)
monitor->target_buffer->line[voodoo->line + v_y_add][voodoo->h_disp + x + v_x_add] =
0x00000000;
}
}
}
skip_draw:
if (voodoo->line == voodoo->v_disp) {
#if 0
voodoodisp_log("retrace %i %i %08x %i\n", voodoo->retrace_count, voodoo->swap_interval, voodoo->swap_offset, voodoo->swap_pending);
#endif
voodoo->retrace_count++;
if (SLI_ENABLED && (voodoo->fbiInit2 & FBIINIT2_SWAP_ALGORITHM_MASK) == FBIINIT2_SWAP_ALGORITHM_SLI_SYNC) {
if (voodoo == voodoo->set->voodoos[0]) {
voodoo_t *voodoo_1 = voodoo->set->voodoos[1];
thread_wait_mutex(voodoo->swap_mutex);
/*Only swap if both Voodoos are waiting for buffer swap*/
if (voodoo->swap_pending && (voodoo->retrace_count > voodoo->swap_interval) && voodoo_1->swap_pending && (voodoo_1->retrace_count > voodoo_1->swap_interval)) {
memset(voodoo->dirty_line, 1, 1024);
voodoo->retrace_count = 0;
voodoo->front_offset = voodoo->swap_offset;
if (voodoo->swap_count > 0)
voodoo->swap_count--;
voodoo->swap_pending = 0;
memset(voodoo_1->dirty_line, 1, 1024);
voodoo_1->retrace_count = 0;
voodoo_1->front_offset = voodoo_1->swap_offset;
if (voodoo_1->swap_count > 0)
voodoo_1->swap_count--;
voodoo_1->swap_pending = 0;
thread_release_mutex(voodoo->swap_mutex);
thread_set_event(voodoo->wake_fifo_thread);
thread_set_event(voodoo_1->wake_fifo_thread);
voodoo->frame_count++;
voodoo_1->frame_count++;
} else
thread_release_mutex(voodoo->swap_mutex);
}
} else {
thread_wait_mutex(voodoo->swap_mutex);
if (voodoo->swap_pending && (voodoo->retrace_count > voodoo->swap_interval)) {
voodoo->front_offset = voodoo->swap_offset;
if (voodoo->swap_count > 0)
voodoo->swap_count--;
voodoo->swap_pending = 0;
thread_release_mutex(voodoo->swap_mutex);
memset(voodoo->dirty_line, 1, 1024);
voodoo->retrace_count = 0;
thread_set_event(voodoo->wake_fifo_thread);
voodoo->frame_count++;
} else
thread_release_mutex(voodoo->swap_mutex);
}
voodoo->v_retrace = 1;
}
voodoo->line++;
if (voodoo->fbiInit0 & FBIINIT0_VGA_PASS) {
if (voodoo->line == voodoo->v_disp) {
int force_blit = 0;
thread_wait_mutex(voodoo->force_blit_mutex);
if (voodoo->force_blit_count) {
force_blit = 1;
if (--voodoo->force_blit_count < 0)
voodoo->force_blit_count = 0;
}
thread_release_mutex(voodoo->force_blit_mutex);
if (voodoo->dirty_line_high > voodoo->dirty_line_low || force_blit)
svga_doblit(voodoo->h_disp, voodoo->v_disp - 1, voodoo->svga);
if (voodoo->clutData_dirty) {
voodoo->clutData_dirty = 0;
voodoo_calc_clutData(voodoo);
}
voodoo->dirty_line_high = -1;
voodoo->dirty_line_low = 2000;
}
}
if (voodoo->line >= voodoo->v_total) {
voodoo->line = 0;
voodoo->v_retrace = 0;
}
if (voodoo->line_time)
timer_advance_u64(&voodoo->timer, voodoo->line_time);
else
timer_advance_u64(&voodoo->timer, TIMER_USEC * 32);
}
``` | /content/code_sandbox/src/video/vid_voodoo_display.c | c | 2016-06-25T22:29:10 | 2024-08-16T19:09:21 | 86Box | 86Box/86Box | 2,616 | 8,087 |
```c
/*
* 86Box A hypervisor and IBM PC system emulator that specializes in
* running old operating systems and software designed for IBM
* PC systems and compatibles from 1981 through fairly recent
* system designs based on the PCI bus.
*
* This file is part of the 86Box distribution.
*
* Emulation of the Mach32-compatible ATI 68875 RAMDAC and clones.
*
*
*
* Authors: TheCollector1995.
*
*/
#include <stdio.h>
#include <stdint.h>
#include <stdlib.h>
#include <string.h>
#include <wchar.h>
#include <86box/86box.h>
#include <86box/device.h>
#include <86box/mem.h>
#include <86box/timer.h>
#include <86box/video.h>
#include <86box/vid_svga.h>
#include <86box/vid_svga_render.h>
#include <86box/plat_unused.h>
typedef struct ati68875_ramdac_t {
uint8_t gen_cntl;
uint8_t in_clk_sel;
uint8_t out_clk_sel;
uint8_t mux_cntl;
uint8_t palette_page_sel;
uint8_t test_reg;
} ati68875_ramdac_t;
void
ati68875_ramdac_out(uint16_t addr, int rs2, int rs3, uint8_t val, void *priv, svga_t *svga)
{
ati68875_ramdac_t *ramdac = (ati68875_ramdac_t *) priv;
uint8_t rs = (addr & 0x03);
rs |= (!!rs2 << 2);
rs |= (!!rs3 << 3);
switch (rs) {
case 0x00: /* Palette Write Index Register (RS value = 0000) */
case 0x01: /* Palette Data Register (RS value = 0001) */
case 0x02: /* Pixel Read Mask Register (RS value = 0010) */
case 0x03:
svga_out(addr, val, svga);
break;
case 0x08: /* General Control Register (RS value = 1000) */
ramdac->gen_cntl = val;
break;
case 0x09: /* Input Clock Selection Register (RS value = 1001) */
ramdac->in_clk_sel = val;
break;
case 0x0a: /* Output Clock Selection Register (RS value = 1010) */
ramdac->out_clk_sel = val;
break;
case 0x0b: /* MUX Control Register (RS value = 1011) */
ramdac->mux_cntl = val;
break;
case 0x0c: /* Palette Page Register (RS value = 1100) */
ramdac->palette_page_sel = val;
break;
case 0x0e: /* Test Register (RS value = 1110) */
ramdac->test_reg = val;
break;
case 0x0f: /* Reset State (RS value = 1111) */
ramdac->mux_cntl = 0x2d;
break;
default:
break;
}
return;
}
uint8_t
ati68875_ramdac_in(uint16_t addr, int rs2, int rs3, void *priv, svga_t *svga)
{
const ati68875_ramdac_t *ramdac = (ati68875_ramdac_t *) priv;
uint8_t rs = (addr & 0x03);
uint8_t temp = 0;
rs |= (!!rs2 << 2);
rs |= (!!rs3 << 3);
switch (rs) {
case 0x00: /* Palette Write Index Register (RS value = 0000) */
case 0x01: /* Palette Data Register (RS value = 0001) */
case 0x02: /* Pixel Read Mask Register (RS value = 0010) */
case 0x03:
temp = svga_in(addr, svga);
break;
case 0x08: /* General Control Register (RS value = 1000) */
temp = ramdac->gen_cntl;
break;
case 0x09: /* Input Clock Selection Register (RS value = 1001) */
temp = ramdac->in_clk_sel;
break;
case 0x0a: /* Output Clock Selection Register (RS value = 1010) */
temp = ramdac->out_clk_sel;
break;
case 0x0b: /* MUX Control Register (RS value = 1011) */
temp = ramdac->mux_cntl;
break;
case 0x0c: /* Palette Page Register (RS value = 1100) */
temp = ramdac->palette_page_sel;
break;
case 0x0e: /* Test Register (RS value = 1110) */
switch (ramdac->test_reg & 0x07) {
case 0x03:
temp = 0x75;
break;
default:
break;
}
break;
default:
break;
}
return temp;
}
static void *
ati68875_ramdac_init(UNUSED(const device_t *info))
{
ati68875_ramdac_t *ramdac = (ati68875_ramdac_t *) malloc(sizeof(ati68875_ramdac_t));
memset(ramdac, 0, sizeof(ati68875_ramdac_t));
ramdac->mux_cntl = 0x2d;
return ramdac;
}
static void
ati68875_ramdac_close(void *priv)
{
ati68875_ramdac_t *ramdac = (ati68875_ramdac_t *) priv;
if (ramdac)
free(ramdac);
}
const device_t ati68875_ramdac_device = {
.name = "ATI 68875 RAMDAC",
.internal_name = "ati68875_ramdac",
.flags = 0,
.local = 0,
.init = ati68875_ramdac_init,
.close = ati68875_ramdac_close,
.reset = NULL,
{ .available = NULL },
.speed_changed = NULL,
.force_redraw = NULL,
.config = NULL
};
``` | /content/code_sandbox/src/video/vid_ati68875_ramdac.c | c | 2016-06-25T22:29:10 | 2024-08-16T19:09:21 | 86Box | 86Box/86Box | 2,616 | 1,390 |
```c
/*
* 86Box A hypervisor and IBM PC system emulator that specializes in
* running old operating systems and software designed for IBM
* PC systems and compatibles from 1981 through fairly recent
* system designs based on the PCI bus.
*
* This file is part of the 86Box distribution.
*
* IBM CGA composite filter, borrowed from reenigne's DOSBox
* patch and ported to C.
*
*
*
* Authors: reenigne,
* Miran Grca, <mgrca8@gmail.com>
*
*/
#include <stdio.h>
#include <stdint.h>
#include <string.h>
#include <stdlib.h>
#include <wchar.h>
#include <math.h>
#include <86box/86box.h>
#include <86box/timer.h>
#include <86box/mem.h>
#include <86box/vid_cga.h>
#include <86box/vid_cga_comp.h>
int CGA_Composite_Table[1024];
static double brightness = 0;
static double contrast = 100;
static double saturation = 100;
static double sharpness = 0;
static double hue_offset = 0;
/* New algorithm by reenigne
Works in all CGA modes/color settings and can simulate older and newer CGA revisions */
static const double tau = 6.28318531; /* == 2*pi */
static unsigned char chroma_multiplexer[256] = {
// clang-format off
2, 2, 2, 2, 114,174, 4, 3, 2, 1,133,135, 2,113,150, 4,
133, 2, 1, 99, 151,152, 2, 1, 3, 2, 96,136, 151,152,151,152,
2, 56, 62, 4, 111,250,118, 4, 0, 51,207,137, 1,171,209, 5,
140, 50, 54,100, 133,202, 57, 4, 2, 50,153,149, 128,198,198,135,
32, 1, 36, 81, 147,158, 1, 42, 33, 1,210,254, 34,109,169, 77,
177, 2, 0,165, 189,154, 3, 44, 33, 0, 91,197, 178,142,144,192,
4, 2, 61, 67, 117,151,112, 83, 4, 0,249,255, 3,107,249,117,
147, 1, 50,162, 143,141, 52, 54, 3, 0,145,206, 124,123,192,193,
72, 78, 2, 0, 159,208, 4, 0, 53, 58,164,159, 37,159,171, 1,
248,117, 4, 98, 212,218, 5, 2, 54, 59, 93,121, 176,181,134,130,
1, 61, 31, 0, 160,255, 34, 1, 1, 58,197,166, 0,177,194, 2,
162,111, 34, 96, 205,253, 32, 1, 1, 57,123,125, 119,188,150,112,
78, 4, 0, 75, 166,180, 20, 38, 78, 1,143,246, 42,113,156, 37,
252, 4, 1,188, 175,129, 1, 37, 118, 4, 88,249, 202,150,145,200,
61, 59, 60, 60, 228,252,117, 77, 60, 58,248,251, 81,212,254,107,
198, 59, 58,169, 250,251, 81, 80, 100, 58,154,250, 251,252,252,252
// clang-format on
};
static double intensity[4] = {
77.175381, 88.654656, 166.564623, 174.228438
};
#define NEW_CGA(c, i, r, g, b) (((c) / 0.72) * 0.29 + ((i) / 0.28) * 0.32 + ((r) / 0.28) * 0.1 + ((g) / 0.28) * 0.22 + ((b) / 0.28) * 0.07)
double mode_brightness;
double mode_contrast;
double mode_hue;
double min_v;
double max_v;
double video_ri;
double video_rq;
double video_gi;
double video_gq;
double video_bi;
double video_bq;
int video_sharpness;
int tandy_mode_control = 0;
static bool new_cga = 0;
void
update_cga16_color(uint8_t cgamode)
{
double c;
double i;
double v;
double q;
double a;
double s;
double r;
double iq_adjust_i;
double iq_adjust_q;
double i0;
double i3;
double mode_saturation;
static const double ri = 0.9563;
static const double rq = 0.6210;
static const double gi = -0.2721;
static const double gq = -0.6474;
static const double bi = -1.1069;
static const double bq = 1.7046;
if (!new_cga) {
min_v = chroma_multiplexer[0] + intensity[0];
max_v = chroma_multiplexer[255] + intensity[3];
} else {
i0 = intensity[0];
i3 = intensity[3];
min_v = NEW_CGA(chroma_multiplexer[0], i0, i0, i0, i0);
max_v = NEW_CGA(chroma_multiplexer[255], i3, i3, i3, i3);
}
mode_contrast = 256 / (max_v - min_v);
mode_brightness = -min_v * mode_contrast;
if ((cgamode & 3) == 1)
mode_hue = 14;
else
mode_hue = 4;
mode_contrast *= contrast * (new_cga ? 1.2 : 1) / 100; /* new CGA: 120% */
mode_brightness += (new_cga ? brightness - 10 : brightness) * 5; /* new CGA: -10 */
mode_saturation = (new_cga ? 4.35 : 2.9) * saturation / 100; /* new CGA: 150% */
for (uint16_t x = 0; x < 1024; ++x) {
int phase = x & 3;
int right = (x >> 2) & 15;
int left = (x >> 6) & 15;
int rc = right;
int lc = left;
if ((cgamode & 4) != 0) {
rc = (right & 8) | ((right & 7) != 0 ? 7 : 0);
lc = (left & 8) | ((left & 7) != 0 ? 7 : 0);
}
c = chroma_multiplexer[((lc & 7) << 5) | ((rc & 7) << 2) | phase];
i = intensity[(left >> 3) | ((right >> 2) & 2)];
if (!new_cga)
v = c + i;
else {
double r = intensity[((left >> 2) & 1) | ((right >> 1) & 2)];
double g = intensity[((left >> 1) & 1) | (right & 2)];
double b = intensity[(left & 1) | ((right << 1) & 2)];
v = NEW_CGA(c, i, r, g, b);
}
CGA_Composite_Table[x] = (int) (v * mode_contrast + mode_brightness);
}
i = CGA_Composite_Table[6 * 68] - CGA_Composite_Table[6 * 68 + 2];
q = CGA_Composite_Table[6 * 68 + 1] - CGA_Composite_Table[6 * 68 + 3];
a = tau * (33 + 90 + hue_offset + mode_hue) / 360.0;
c = cos(a);
s = sin(a);
r = 256 * mode_saturation / sqrt(i * i + q * q);
iq_adjust_i = -(i * c + q * s) * r;
iq_adjust_q = (q * c - i * s) * r;
video_ri = (int) (ri * iq_adjust_i + rq * iq_adjust_q);
video_rq = (int) (-ri * iq_adjust_q + rq * iq_adjust_i);
video_gi = (int) (gi * iq_adjust_i + gq * iq_adjust_q);
video_gq = (int) (-gi * iq_adjust_q + gq * iq_adjust_i);
video_bi = (int) (bi * iq_adjust_i + bq * iq_adjust_q);
video_bq = (int) (-bi * iq_adjust_q + bq * iq_adjust_i);
video_sharpness = (int) (sharpness * 256 / 100);
}
static uint8_t
byte_clamp(int v)
{
v >>= 13;
return v < 0 ? 0 : (v > 255 ? 255 : v);
}
/* 2048x1536 is the maximum we can possibly support. */
#define SCALER_MAXWIDTH 2048
static int temp[SCALER_MAXWIDTH + 10] = { 0 };
static int atemp[SCALER_MAXWIDTH + 2] = { 0 };
static int btemp[SCALER_MAXWIDTH + 2] = { 0 };
uint32_t *
Composite_Process(uint8_t cgamode, uint8_t border, uint32_t blocks /*, bool doublewidth*/, uint32_t *TempLine)
{
uint32_t x2;
int w = blocks * 4;
int *o;
const uint32_t *rgbi;
const int *b;
int *i;
uint32_t *srgb;
int *ap;
int *bp;
#define COMPOSITE_CONVERT(I, Q) \
do { \
i[1] = (i[1] << 3) - ap[1]; \
a = ap[0]; \
b = bp[0]; \
c = i[0] + i[0]; \
d = i[-1] + i[1]; \
y = ((c + d) << 8) + video_sharpness * (c - d); \
rr = y + video_ri * (I) + video_rq * (Q); \
gg = y + video_gi * (I) + video_gq * (Q); \
bb = y + video_bi * (I) + video_bq * (Q); \
++i; \
++ap; \
++bp; \
*srgb = (byte_clamp(rr) << 16) | (byte_clamp(gg) << 8) | byte_clamp(bb); \
++srgb; \
} while (0)
#define OUT(v) \
do { \
*o = (v); \
++o; \
} while (0)
/* Simulate CGA composite output */
o = temp;
rgbi = TempLine;
b = &CGA_Composite_Table[border * 68];
for (uint8_t x = 0; x < 4; ++x)
OUT(b[(x + 3) & 3]);
OUT(CGA_Composite_Table[(border << 6) | ((*rgbi & 0x0f) << 2) | 3]);
for (int x = 0; x < w - 1; ++x) {
OUT(CGA_Composite_Table[((rgbi[0] & 0x0f) << 6) | ((rgbi[1] & 0x0f) << 2) | (x & 3)]);
++rgbi;
}
OUT(CGA_Composite_Table[((*rgbi & 0x0f) << 6) | (border << 2) | 3]);
for (uint8_t x = 0; x < 5; ++x)
OUT(b[x & 3]);
if ((cgamode & 4) != 0) {
/* Decode */
i = temp + 5;
srgb = TempLine;
for (x2 = 0; x2 < blocks * 4; ++x2) {
int c = (i[0] + i[0]) << 3;
int d = (i[-1] + i[1]) << 3;
int y = ((c + d) << 8) + video_sharpness * (c - d);
++i;
*srgb = byte_clamp(y) * 0x10101;
++srgb;
}
} else {
/* Store chroma */
i = temp + 4;
ap = atemp + 1;
bp = btemp + 1;
for (int x = -1; x < w + 1; ++x) {
ap[x] = i[-4] - ((i[-2] - i[0] + i[2]) << 1) + i[4];
bp[x] = (i[-3] - i[-1] + i[1] - i[3]) << 1;
++i;
}
/* Decode */
i = temp + 5;
i[-1] = (i[-1] << 3) - ap[-1];
i[0] = (i[0] << 3) - ap[0];
srgb = TempLine;
for (x2 = 0; x2 < blocks; ++x2) {
int y;
int a;
int b;
int c;
int d;
int rr;
int gg;
int bb;
COMPOSITE_CONVERT(a, b);
COMPOSITE_CONVERT(-b, a);
COMPOSITE_CONVERT(-a, -b);
COMPOSITE_CONVERT(b, -a);
}
}
#undef COMPOSITE_CONVERT
#undef OUT
return TempLine;
}
void
IncreaseHue(uint8_t cgamode)
{
hue_offset += 5.0;
update_cga16_color(cgamode);
}
void
DecreaseHue(uint8_t cgamode)
{
hue_offset -= 5.0;
update_cga16_color(cgamode);
}
void
IncreaseSaturation(uint8_t cgamode)
{
saturation += 5;
update_cga16_color(cgamode);
}
void
DecreaseSaturation(uint8_t cgamode)
{
saturation -= 5;
update_cga16_color(cgamode);
}
void
IncreaseContrast(uint8_t cgamode)
{
contrast += 5;
update_cga16_color(cgamode);
}
void
DecreaseContrast(uint8_t cgamode)
{
contrast -= 5;
update_cga16_color(cgamode);
}
void
IncreaseBrightness(uint8_t cgamode)
{
brightness += 5;
update_cga16_color(cgamode);
}
void
DecreaseBrightness(uint8_t cgamode)
{
brightness -= 5;
update_cga16_color(cgamode);
}
void
IncreaseSharpness(uint8_t cgamode)
{
sharpness += 10;
update_cga16_color(cgamode);
}
void
DecreaseSharpness(uint8_t cgamode)
{
sharpness -= 10;
update_cga16_color(cgamode);
}
void
cga_comp_init(int revision)
{
new_cga = revision;
/* Making sure this gets reset after reset. */
brightness = 0;
contrast = 100;
saturation = 100;
sharpness = 0;
hue_offset = 0;
update_cga16_color(0);
}
``` | /content/code_sandbox/src/video/vid_cga_comp.c | c | 2016-06-25T22:29:10 | 2024-08-16T19:09:21 | 86Box | 86Box/86Box | 2,616 | 3,872 |
```c
/*
* 86Box A hypervisor and IBM PC system emulator that specializes in
* running old operating systems and software designed for IBM
* PC systems and compatibles from 1981 through fairly recent
* system designs based on the PCI bus.
*
* This file is part of the 86Box distribution.
*
* AGP Graphics Address Remapping Table remapping emulation.
*
*
*
* Authors: RichardG, <richardg867@gmail.com>
*
*/
#include <stdarg.h>
#include <stdio.h>
#include <stdint.h>
#include <stdlib.h>
#include <string.h>
#define HAVE_STDARG_H
#include <86box/86box.h>
#include <86box/device.h>
#include <86box/mem.h>
#include <86box/agpgart.h>
#include <86box/plat_unused.h>
#ifdef ENABLE_AGPGART_LOG
int agpgart_do_log = ENABLE_AGPGART_LOG;
static void
agpgart_log(const char *fmt, ...)
{
va_list ap;
if (agpgart_do_log) {
va_start(ap, fmt);
pclog_ex(fmt, ap);
va_end(ap);
}
}
#else
# define agpgart_log(fmt, ...)
#endif
void
agpgart_set_aperture(agpgart_t *dev, uint32_t base, uint32_t size, int enable)
{
agpgart_log("AGP GART: set_aperture(%08X, %d, %d)\n", base, size, enable);
/* Disable old aperture mapping. */
mem_mapping_disable(&dev->aperture_mapping);
/* Set new aperture base address, size, mask and enable. */
dev->aperture_base = base;
dev->aperture_size = size;
dev->aperture_mask = size - 1;
dev->aperture_enable = enable;
/* Enable new aperture mapping if requested. */
if (dev->aperture_base && dev->aperture_size && dev->aperture_enable) {
mem_mapping_set_addr(&dev->aperture_mapping, dev->aperture_base, dev->aperture_size);
mem_mapping_enable(&dev->aperture_mapping);
}
}
void
agpgart_set_gart(agpgart_t *dev, uint32_t base)
{
agpgart_log("AGP GART: set_gart(%08X)\n", base);
/* Set GART base address. */
dev->gart_base = base;
}
static uint32_t
agpgart_translate(uint32_t addr, agpgart_t *dev)
{
/* Extract the bits we care about. */
addr &= dev->aperture_mask;
/* Get the GART pointer for this page. */
register uint32_t gart_ptr = mem_readl_phys(dev->gart_base + ((addr >> 10) & 0xfffffffc)) & 0xfffff000;
/* Return remapped address with the page offset. */
return gart_ptr | (addr & 0x00000fff);
}
static uint8_t
agpgart_aperture_readb(uint32_t addr, void *priv)
{
agpgart_t *dev = (agpgart_t *) priv;
return mem_readb_phys(agpgart_translate(addr, dev));
}
static uint16_t
agpgart_aperture_readw(uint32_t addr, void *priv)
{
agpgart_t *dev = (agpgart_t *) priv;
return mem_readw_phys(agpgart_translate(addr, dev));
}
static uint32_t
agpgart_aperture_readl(uint32_t addr, void *priv)
{
agpgart_t *dev = (agpgart_t *) priv;
return mem_readl_phys(agpgart_translate(addr, dev));
}
static void
agpgart_aperture_writeb(uint32_t addr, uint8_t val, void *priv)
{
agpgart_t *dev = (agpgart_t *) priv;
mem_writeb_phys(agpgart_translate(addr, dev), val);
}
static void
agpgart_aperture_writew(uint32_t addr, uint16_t val, void *priv)
{
agpgart_t *dev = (agpgart_t *) priv;
mem_writew_phys(agpgart_translate(addr, dev), val);
}
static void
agpgart_aperture_writel(uint32_t addr, uint32_t val, void *priv)
{
agpgart_t *dev = (agpgart_t *) priv;
mem_writel_phys(agpgart_translate(addr, dev), val);
}
static void *
agpgart_init(UNUSED(const device_t *info))
{
agpgart_t *dev = malloc(sizeof(agpgart_t));
memset(dev, 0, sizeof(agpgart_t));
agpgart_log("AGP GART: init()\n");
/* Create aperture mapping. */
mem_mapping_add(&dev->aperture_mapping, 0, 0,
agpgart_aperture_readb, agpgart_aperture_readw, agpgart_aperture_readl,
agpgart_aperture_writeb, agpgart_aperture_writew, agpgart_aperture_writel,
NULL, MEM_MAPPING_EXTERNAL, dev);
return dev;
}
static void
agpgart_close(void *priv)
{
agpgart_t *dev = (agpgart_t *) priv;
agpgart_log("AGP GART: close()\n");
/* Disable aperture. */
mem_mapping_disable(&dev->aperture_mapping);
free(dev);
}
const device_t agpgart_device = {
.name = "AGP Graphics Address Remapping Table",
.internal_name = "agpgart",
.flags = DEVICE_PCI,
.local = 0,
.init = agpgart_init,
.close = agpgart_close,
.reset = NULL,
{ .available = NULL },
.speed_changed = NULL,
.force_redraw = NULL,
.config = NULL
};
``` | /content/code_sandbox/src/video/agpgart.c | c | 2016-06-25T22:29:10 | 2024-08-16T19:09:21 | 86Box | 86Box/86Box | 2,616 | 1,301 |
```c
/*
* 86Box A hypervisor and IBM PC system emulator that specializes in
* running old operating systems and software designed for IBM
* PC systems and compatibles from 1981 through fairly recent
* system designs based on the PCI bus.
*
* This file is part of the 86Box distribution.
*
* Emulation of the Realtek RTG series of VGA ISA chips.
*
*
*
* Authors: TheCollector1995, <mariogplayer90@gmail.com>
*
*/
#include <stdio.h>
#include <stdint.h>
#include <string.h>
#include <stdlib.h>
#include <wchar.h>
#include <86box/86box.h>
#include <86box/io.h>
#include <86box/mem.h>
#include <86box/rom.h>
#include <86box/device.h>
#include <86box/timer.h>
#include <86box/video.h>
#include <86box/vid_svga.h>
#include <86box/vid_svga_render.h>
#define RTG_3105_BIOS_ROM_PATH "roms/video/rtg/RTG3105I.VBI"
#define RTG_3106_BIOS_ROM_PATH "roms/video/rtg/realtekrtg3106.BIN"
typedef struct {
const char *name;
int type;
svga_t svga;
rom_t bios_rom;
uint8_t bank3d6,
bank3d7;
uint32_t vram_size,
vram_mask;
} rtg_t;
static video_timings_t timing_rtg_isa = { .type = VIDEO_ISA, .write_b = 3, .write_w = 3, .write_l = 6, .read_b = 5, .read_w = 5, .read_l = 10 };
static void
rtg_recalcbanking(rtg_t *dev)
{
svga_t *svga = &dev->svga;
svga->write_bank = (dev->bank3d7 & 0x0f) * 65536;
if (svga->gdcreg[0x0f] & 4)
svga->read_bank = (dev->bank3d6 & 0x0f) * 65536;
else
svga->read_bank = svga->write_bank;
}
static uint8_t
rtg_in(uint16_t addr, void *priv)
{
rtg_t *dev = (rtg_t *) priv;
svga_t *svga = &dev->svga;
uint8_t ret = 0;
if (((addr & 0xfff0) == 0x3d0 || (addr & 0xfff0) == 0x3b0) && !(svga->miscout & 1))
addr ^= 0x60;
switch (addr) {
case 0x3ce:
return svga->gdcaddr;
case 0x3cf:
if (svga->gdcaddr == 0x0c)
return svga->gdcreg[0x0c] | 4;
else if ((svga->gdcaddr > 8) && (svga->gdcaddr != 0x0c))
return svga->gdcreg[svga->gdcaddr];
break;
case 0x3d4:
return svga->crtcreg;
case 0x3d5:
if (svga->crtcreg == 0x1a)
return dev->type << 6;
if (svga->crtcreg == 0x1e) {
ret = svga->crtc[0x1e];
ret &= ~3;
if (dev->vram_size == 1024)
ret = 2;
else if (dev->vram_size == 512)
ret = 1;
else
ret = 0;
return ret;
}
return svga->crtc[svga->crtcreg];
case 0x3d6:
return dev->bank3d6;
case 0x3d7:
return dev->bank3d7;
default:
break;
}
return svga_in(addr, svga);
}
static void
rtg_out(uint16_t addr, uint8_t val, void *priv)
{
rtg_t *dev = (rtg_t *) priv;
svga_t *svga = &dev->svga;
uint8_t old;
if (((addr & 0xfff0) == 0x3d0 || (addr & 0xfff0) == 0x3b0) && !(svga->miscout & 1))
addr ^= 0x60;
switch (addr) {
case 0x3ce:
svga->gdcaddr = val;
return;
case 0x3cf:
if (svga->gdcaddr > 8) {
svga->gdcreg[svga->gdcaddr] = val;
switch (svga->gdcaddr) {
case 0x0b:
case 0x0c:
svga->fullchange = changeframecount;
svga_recalctimings(svga);
break;
case 0x0f:
rtg_recalcbanking(dev);
return;
default:
break;
}
}
break;
case 0x3d4:
svga->crtcreg = val & 0x3f;
return;
case 0x3d5:
if ((svga->crtcreg < 7) && (svga->crtc[0x11] & 0x80))
return;
if ((svga->crtcreg == 7) && (svga->crtc[0x11] & 0x80))
val = (svga->crtc[7] & ~0x10) | (val & 0x10);
old = svga->crtc[svga->crtcreg];
svga->crtc[svga->crtcreg] = val;
if (svga->crtc[0x1e] & 0x80) {
switch (svga->crtcreg) {
case 0x19:
svga->vram_display_mask = (val & 0x20) ? dev->vram_mask : 0x3ffff;
svga->fullchange = changeframecount;
svga_recalctimings(svga);
break;
default:
break;
}
}
if (old != val) {
if (svga->crtcreg < 0xe || svga->crtcreg > 0x10) {
if ((svga->crtcreg == 0xc) || (svga->crtcreg == 0xd)) {
svga->fullchange = 3;
svga->ma_latch = ((svga->crtc[0xc] << 8) | svga->crtc[0xd]) + ((svga->crtc[8] & 0x60) >> 5);
} else {
svga->fullchange = changeframecount;
svga_recalctimings(svga);
}
}
}
break;
case 0x3d6:
dev->bank3d6 = val;
rtg_recalcbanking(dev);
return;
case 0x3d7:
dev->bank3d7 = val;
rtg_recalcbanking(dev);
return;
default:
break;
}
svga_out(addr, val, svga);
}
static void
rtg_recalctimings(svga_t *svga)
{
const rtg_t *dev = (rtg_t *) svga->priv;
svga->ma_latch |= ((svga->crtc[0x19] & 0x10) << 16) | ((svga->crtc[0x19] & 0x40) << 17);
svga->interlace = (svga->crtc[0x19] & 1);
/*Clock table not available, currently a guesswork*/
switch (((svga->miscout >> 2) & 3) | ((svga->gdcreg[0x0c] & 0x20) >> 3)) {
case 0:
case 1:
break;
case 2:
svga->clock = (cpuclock * (double) (1ULL << 32)) / 36000000.0;
break;
case 3:
svga->clock = (cpuclock * (double) (1ULL << 32)) / 65100000.0;
break;
case 4:
svga->clock = (cpuclock * (double) (1ULL << 32)) / 44900000.0;
break;
case 5:
svga->clock = (cpuclock * (double) (1ULL << 32)) / 50000000.0;
break;
case 6:
svga->clock = (cpuclock * (double) (1ULL << 32)) / 80000000.0;
break;
case 7:
svga->clock = (cpuclock * (double) (1ULL << 32)) / 75000000.0;
break;
default:
break;
}
switch (svga->gdcreg[0x0c] & 3) {
case 1:
svga->clock /= 1.5;
break;
case 2:
svga->clock /= 2;
break;
case 3:
svga->clock /= 4;
break;
default:
break;
}
if (!svga->scrblank && (svga->crtc[0x17] & 0x80) && svga->attr_palette_enable) {
if ((svga->gdcreg[6] & 1) || (svga->attrregs[0x10] & 1)) {
switch (svga->gdcreg[5] & 0x60) {
case 0x00:
if (svga->seqregs[1] & 8) /*Low res (320)*/
svga->render = svga_render_4bpp_lowres;
else {
if (svga->hdisp == 1280)
svga->rowoffset >>= 1;
svga->render = svga_render_4bpp_highres;
}
break;
case 0x20: /*4 colours*/
if (svga->seqregs[1] & 8) /*Low res (320)*/
svga->render = svga_render_2bpp_lowres;
else
svga->render = svga_render_2bpp_highres;
break;
case 0x40:
case 0x60:
if (svga->crtc[0x19] & 2) {
if (svga->hdisp == 1280)
svga->hdisp >>= 1;
else if (dev->type == 2)
svga->rowoffset <<= 1;
svga->render = svga_render_8bpp_highres;
} else
svga->render = svga_render_8bpp_lowres;
break;
default:
break;
}
}
}
}
static void *
rtg_init(const device_t *info)
{
const char *fn;
rtg_t *dev;
dev = (rtg_t *) malloc(sizeof(rtg_t));
memset(dev, 0x00, sizeof(rtg_t));
dev->name = info->name;
dev->type = info->local;
fn = NULL;
switch (dev->type) {
case 1: /* ISA RTG3105 */
fn = RTG_3105_BIOS_ROM_PATH;
dev->vram_size = device_get_config_int("memory");
video_inform(VIDEO_FLAG_TYPE_SPECIAL, &timing_rtg_isa);
svga_init(info, &dev->svga, dev, dev->vram_size << 10,
rtg_recalctimings, rtg_in, rtg_out,
NULL, NULL);
io_sethandler(0x03c0, 32,
rtg_in, NULL, NULL, rtg_out, NULL, NULL, dev);
break;
case 2: /* ISA RTG3106 */
fn = RTG_3106_BIOS_ROM_PATH;
dev->vram_size = device_get_config_int("memory");
video_inform(VIDEO_FLAG_TYPE_SPECIAL, &timing_rtg_isa);
svga_init(info, &dev->svga, dev, dev->vram_size << 10,
rtg_recalctimings, rtg_in, rtg_out,
NULL, NULL);
io_sethandler(0x03c0, 32,
rtg_in, NULL, NULL, rtg_out, NULL, NULL, dev);
break;
default:
break;
}
dev->svga.bpp = 8;
dev->svga.miscout = 1;
dev->vram_mask = dev->vram_size - 1;
rom_init(&dev->bios_rom, fn,
0xc0000, 0x8000, 0x7fff, 0, MEM_MAPPING_EXTERNAL);
return dev;
}
static void
rtg_close(void *priv)
{
rtg_t *dev = (rtg_t *) priv;
svga_close(&dev->svga);
free(dev);
}
static void
rtg_speed_changed(void *priv)
{
rtg_t *dev = (rtg_t *) priv;
svga_recalctimings(&dev->svga);
}
static void
rtg_force_redraw(void *priv)
{
rtg_t *dev = (rtg_t *) priv;
dev->svga.fullchange = changeframecount;
}
static int
rtg3105_available(void)
{
return rom_present(RTG_3105_BIOS_ROM_PATH);
}
static int
rtg3106_available(void)
{
return rom_present(RTG_3106_BIOS_ROM_PATH);
}
static const device_config_t rtg3105_config[] = {
// clang-format off
{
.name = "memory",
.description = "Memory size",
.type = CONFIG_SELECTION,
.default_int = 512,
.selection = {
{
.description = "256 KB",
.value = 256
},
{
.description = "512 KB",
.value = 512
},
{
.description = ""
}
}
},
{
.type = CONFIG_END
}
// clang-format on
};
static const device_config_t rtg3106_config[] = {
// clang-format off
{
.name = "memory",
.description = "Memory size",
.type = CONFIG_SELECTION,
.default_int = 1024,
.selection = {
{
.description = "256 KB",
.value = 256
},
{
.description = "512 KB",
.value = 512
},
{
.description = "1 MB",
.value = 1024
},
{
.description = ""
}
}
},
{
.type = CONFIG_END
}
// clang-format on
};
const device_t realtek_rtg3105_device = {
.name = "Realtek RTG3105 (ISA)",
.internal_name = "rtg3105",
.flags = DEVICE_ISA,
.local = 1,
.init = rtg_init,
.close = rtg_close,
.reset = NULL,
{ .available = rtg3105_available },
.speed_changed = rtg_speed_changed,
.force_redraw = rtg_force_redraw,
.config = rtg3105_config
};
const device_t realtek_rtg3106_device = {
.name = "Realtek RTG3106 (ISA)",
.internal_name = "rtg3106",
.flags = DEVICE_ISA,
.local = 2,
.init = rtg_init,
.close = rtg_close,
.reset = NULL,
{ .available = rtg3106_available },
.speed_changed = rtg_speed_changed,
.force_redraw = rtg_force_redraw,
.config = rtg3106_config
};
``` | /content/code_sandbox/src/video/vid_rtg310x.c | c | 2016-06-25T22:29:10 | 2024-08-16T19:09:21 | 86Box | 86Box/86Box | 2,616 | 3,736 |
```c
/*
* 86Box A hypervisor and IBM PC system emulator that specializes in
* running old operating systems and software designed for IBM
* PC systems and compatibles from 1981 through fairly recent
* system designs based on the PCI bus.
*
* This file is part of the 86Box distribution.
*
* MDA emulation.
*
*
*
* Authors: Sarah Walker, <path_to_url
* Miran Grca, <mgrca8@gmail.com>
*
*/
#include <stdio.h>
#include <stdint.h>
#include <string.h>
#include <stdlib.h>
#include <wchar.h>
#include <86box/86box.h>
#include <86box/io.h>
#include <86box/timer.h>
#include <86box/lpt.h>
#include <86box/pit.h>
#include <86box/mem.h>
#include <86box/rom.h>
#include <86box/device.h>
#include <86box/video.h>
#include <86box/vid_mda.h>
#include <86box/plat_unused.h>
static int mdacols[256][2][2];
static video_timings_t timing_mda = { .type = VIDEO_ISA, .write_b = 8, .write_w = 16, .write_l = 32, .read_b = 8, .read_w = 16, .read_l = 32 };
void mda_recalctimings(mda_t *mda);
void
mda_out(uint16_t addr, uint8_t val, void *priv)
{
mda_t *mda = (mda_t *) priv;
switch (addr) {
case 0x3b0:
case 0x3b2:
case 0x3b4:
case 0x3b6:
mda->crtcreg = val & 31;
return;
case 0x3b1:
case 0x3b3:
case 0x3b5:
case 0x3b7:
mda->crtc[mda->crtcreg] = val;
if (mda->crtc[10] == 6 && mda->crtc[11] == 7) /*Fix for Generic Turbo XT BIOS, which sets up cursor registers wrong*/
{
mda->crtc[10] = 0xb;
mda->crtc[11] = 0xc;
}
mda_recalctimings(mda);
return;
case 0x3b8:
mda->ctrl = val;
return;
default:
break;
}
}
uint8_t
mda_in(uint16_t addr, void *priv)
{
const mda_t *mda = (mda_t *) priv;
switch (addr) {
case 0x3b0:
case 0x3b2:
case 0x3b4:
case 0x3b6:
return mda->crtcreg;
case 0x3b1:
case 0x3b3:
case 0x3b5:
case 0x3b7:
return mda->crtc[mda->crtcreg];
case 0x3ba:
return mda->stat | 0xF0;
default:
break;
}
return 0xff;
}
void
mda_write(uint32_t addr, uint8_t val, void *priv)
{
mda_t *mda = (mda_t *) priv;
mda->vram[addr & 0xfff] = val;
}
uint8_t
mda_read(uint32_t addr, void *priv)
{
const mda_t *mda = (mda_t *) priv;
return mda->vram[addr & 0xfff];
}
void
mda_recalctimings(mda_t *mda)
{
double _dispontime;
double _dispofftime;
double disptime;
disptime = mda->crtc[0] + 1;
_dispontime = mda->crtc[1];
_dispofftime = disptime - _dispontime;
_dispontime *= MDACONST;
_dispofftime *= MDACONST;
mda->dispontime = (uint64_t) (_dispontime);
mda->dispofftime = (uint64_t) (_dispofftime);
}
void
mda_poll(void *priv)
{
mda_t *mda = (mda_t *) priv;
uint16_t ca = (mda->crtc[15] | (mda->crtc[14] << 8)) & 0x3fff;
int drawcursor;
int x;
int c;
int oldvc;
uint8_t chr;
uint8_t attr;
int oldsc;
int blink;
VIDEO_MONITOR_PROLOGUE()
if (!mda->linepos) {
timer_advance_u64(&mda->timer, mda->dispofftime);
mda->stat |= 1;
mda->linepos = 1;
oldsc = mda->sc;
if ((mda->crtc[8] & 3) == 3)
mda->sc = (mda->sc << 1) & 7;
if (mda->dispon) {
if (mda->displine < mda->firstline) {
mda->firstline = mda->displine;
video_wait_for_buffer();
}
mda->lastline = mda->displine;
for (x = 0; x < mda->crtc[1]; x++) {
chr = mda->vram[(mda->ma << 1) & 0xfff];
attr = mda->vram[((mda->ma << 1) + 1) & 0xfff];
drawcursor = ((mda->ma == ca) && mda->con && mda->cursoron);
blink = ((mda->blink & 16) && (mda->ctrl & 0x20) && (attr & 0x80) && !drawcursor);
if (mda->sc == 12 && ((attr & 7) == 1)) {
for (c = 0; c < 9; c++)
buffer32->line[mda->displine][(x * 9) + c] = mdacols[attr][blink][1];
} else {
for (c = 0; c < 8; c++)
buffer32->line[mda->displine][(x * 9) + c] = mdacols[attr][blink][(fontdatm[chr + mda->fontbase][mda->sc] & (1 << (c ^ 7))) ? 1 : 0];
if ((chr & ~0x1f) == 0xc0)
buffer32->line[mda->displine][(x * 9) + 8] = mdacols[attr][blink][fontdatm[chr + mda->fontbase][mda->sc] & 1];
else
buffer32->line[mda->displine][(x * 9) + 8] = mdacols[attr][blink][0];
}
mda->ma++;
if (drawcursor) {
for (c = 0; c < 9; c++)
buffer32->line[mda->displine][(x * 9) + c] ^= mdacols[attr][0][1];
}
}
video_process_8(mda->crtc[1] * 9, mda->displine);
}
mda->sc = oldsc;
if (mda->vc == mda->crtc[7] && !mda->sc) {
mda->stat |= 8;
}
mda->displine++;
if (mda->displine >= 500)
mda->displine = 0;
} else {
timer_advance_u64(&mda->timer, mda->dispontime);
if (mda->dispon)
mda->stat &= ~1;
mda->linepos = 0;
if (mda->vsynctime) {
mda->vsynctime--;
if (!mda->vsynctime) {
mda->stat &= ~8;
}
}
if (mda->sc == (mda->crtc[11] & 31) || ((mda->crtc[8] & 3) == 3 && mda->sc == ((mda->crtc[11] & 31) >> 1))) {
mda->con = 0;
mda->coff = 1;
}
if (mda->vadj) {
mda->sc++;
mda->sc &= 31;
mda->ma = mda->maback;
mda->vadj--;
if (!mda->vadj) {
mda->dispon = 1;
mda->ma = mda->maback = (mda->crtc[13] | (mda->crtc[12] << 8)) & 0x3fff;
mda->sc = 0;
}
} else if (mda->sc == mda->crtc[9] || ((mda->crtc[8] & 3) == 3 && mda->sc == (mda->crtc[9] >> 1))) {
mda->maback = mda->ma;
mda->sc = 0;
oldvc = mda->vc;
mda->vc++;
mda->vc &= 127;
if (mda->vc == mda->crtc[6])
mda->dispon = 0;
if (oldvc == mda->crtc[4]) {
mda->vc = 0;
mda->vadj = mda->crtc[5];
if (!mda->vadj)
mda->dispon = 1;
if (!mda->vadj)
mda->ma = mda->maback = (mda->crtc[13] | (mda->crtc[12] << 8)) & 0x3fff;
if ((mda->crtc[10] & 0x60) == 0x20)
mda->cursoron = 0;
else
mda->cursoron = mda->blink & 16;
}
if (mda->vc == mda->crtc[7]) {
mda->dispon = 0;
mda->displine = 0;
mda->vsynctime = 16;
if (mda->crtc[7]) {
x = mda->crtc[1] * 9;
mda->lastline++;
if ((x != xsize) || ((mda->lastline - mda->firstline) != ysize) || video_force_resize_get()) {
xsize = x;
ysize = mda->lastline - mda->firstline;
if (xsize < 64)
xsize = 656;
if (ysize < 32)
ysize = 200;
set_screen_size(xsize, ysize);
if (video_force_resize_get())
video_force_resize_set(0);
}
video_blit_memtoscreen(0, mda->firstline, xsize, ysize);
frames++;
video_res_x = mda->crtc[1];
video_res_y = mda->crtc[6];
video_bpp = 0;
}
mda->firstline = 1000;
mda->lastline = 0;
mda->blink++;
}
} else {
mda->sc++;
mda->sc &= 31;
mda->ma = mda->maback;
}
if (mda->sc == (mda->crtc[10] & 31) || ((mda->crtc[8] & 3) == 3 && mda->sc == ((mda->crtc[10] & 31) >> 1))) {
mda->con = 1;
}
}
VIDEO_MONITOR_EPILOGUE();
}
void
mda_init(mda_t *mda)
{
for (uint16_t c = 0; c < 256; c++) {
mdacols[c][0][0] = mdacols[c][1][0] = mdacols[c][1][1] = 16;
if (c & 8)
mdacols[c][0][1] = 15 + 16;
else
mdacols[c][0][1] = 7 + 16;
}
mdacols[0x70][0][1] = 16;
mdacols[0x70][0][0] = mdacols[0x70][1][0] = mdacols[0x70][1][1] = 16 + 15;
mdacols[0xF0][0][1] = 16;
mdacols[0xF0][0][0] = mdacols[0xF0][1][0] = mdacols[0xF0][1][1] = 16 + 15;
mdacols[0x78][0][1] = 16 + 7;
mdacols[0x78][0][0] = mdacols[0x78][1][0] = mdacols[0x78][1][1] = 16 + 15;
mdacols[0xF8][0][1] = 16 + 7;
mdacols[0xF8][0][0] = mdacols[0xF8][1][0] = mdacols[0xF8][1][1] = 16 + 15;
mdacols[0x00][0][1] = mdacols[0x00][1][1] = 16;
mdacols[0x08][0][1] = mdacols[0x08][1][1] = 16;
mdacols[0x80][0][1] = mdacols[0x80][1][1] = 16;
mdacols[0x88][0][1] = mdacols[0x88][1][1] = 16;
overscan_x = overscan_y = 0;
mda->monitor_index = monitor_index_global;
cga_palette = device_get_config_int("rgb_type") << 1;
if (cga_palette > 6) {
cga_palette = 0;
}
cgapal_rebuild();
timer_add(&mda->timer, mda_poll, mda, 1);
}
void *
mda_standalone_init(UNUSED(const device_t *info))
{
mda_t *mda = malloc(sizeof(mda_t));
memset(mda, 0, sizeof(mda_t));
video_inform(VIDEO_FLAG_TYPE_MDA, &timing_mda);
mda->vram = malloc(0x1000);
mem_mapping_add(&mda->mapping, 0xb0000, 0x08000, mda_read, NULL, NULL, mda_write, NULL, NULL, NULL, MEM_MAPPING_EXTERNAL, mda);
io_sethandler(0x03b0, 0x0010, mda_in, NULL, NULL, mda_out, NULL, NULL, mda);
mda_init(mda);
lpt3_init(0x3BC);
return mda;
}
void
mda_setcol(int chr, int blink, int fg, uint8_t cga_ink)
{
mdacols[chr][blink][fg] = 16 + cga_ink;
}
void
mda_close(void *priv)
{
mda_t *mda = (mda_t *) priv;
free(mda->vram);
free(mda);
}
void
mda_speed_changed(void *priv)
{
mda_t *mda = (mda_t *) priv;
mda_recalctimings(mda);
}
static const device_config_t mda_config[] = {
// clang-format off
{
.name = "rgb_type",
.description = "Display type",
.type = CONFIG_SELECTION,
.default_int = 0,
.selection = {
{
.description = "Default",
.value = 0
},
{
.description = "Green",
.value = 1
},
{
.description = "Amber",
.value = 2
},
{
.description = "Gray",
.value = 3
},
{
.description = ""
}
}
},
{
.type = CONFIG_END
}
// clang-format on
};
const device_t mda_device = {
.name = "IBM MDA",
.internal_name = "mda",
.flags = DEVICE_ISA,
.local = 0,
.init = mda_standalone_init,
.close = mda_close,
.reset = NULL,
{ .available = NULL },
.speed_changed = mda_speed_changed,
.force_redraw = NULL,
.config = mda_config
};
``` | /content/code_sandbox/src/video/vid_mda.c | c | 2016-06-25T22:29:10 | 2024-08-16T19:09:21 | 86Box | 86Box/86Box | 2,616 | 3,954 |
```c
/*
* 86Box A hypervisor and IBM PC system emulator that specializes in
* running old operating systems and software designed for IBM
* PC systems and compatibles from 1981 through fairly recent
* system designs based on the PCI bus.
*
* This file is part of the 86Box distribution.
*
* Emulation of the NCR NGA (K511, K201) video cards.
*
*
*
* Authors: Sarah Walker, <path_to_url
* Miran Grca, <mgrca8@gmail.com>
* Fred N. van Kempen, <decwiz@yahoo.com>
* EngiNerd, <webmaster.crrc@yahoo.it>
*
*/
#include <stdio.h>
#include <stdint.h>
#include <string.h>
#include <stdlib.h>
#include <stdarg.h>
#include <wchar.h>
#include <86box/io.h>
#include <86box/video.h>
#include <86box/86box.h>
#include <86box/timer.h>
#include <86box/mem.h>
#include <86box/pit.h>
#include <86box/rom.h>
#include <86box/device.h>
#include <86box/vid_cga.h>
#include <86box/vid_nga.h>
#include <86box/vid_cga_comp.h>
#include <86box/plat_unused.h>
#define CGA_RGB 0
#define CGA_COMPOSITE 1
#define COMPOSITE_OLD 0
#define COMPOSITE_NEW 1
static video_timings_t timing_nga = { .type = VIDEO_ISA, .write_b = 8, .write_w = 16, .write_l = 32, .read_b = 8, .read_w = 16, .read_l = 32 };
void
nga_recalctimings(nga_t *nga)
{
double _dispontime;
double _dispofftime;
double disptime;
if (nga->cga.cgamode & 1) {
disptime = nga->cga.crtc[0] + 1;
_dispontime = nga->cga.crtc[1];
} else {
disptime = (nga->cga.crtc[0] + 1) << 1;
_dispontime = nga->cga.crtc[1] << 1;
}
_dispofftime = disptime - _dispontime;
_dispontime *= CGACONST / 2;
_dispofftime *= CGACONST / 2;
nga->cga.dispontime = (uint64_t) (_dispontime);
nga->cga.dispofftime = (uint64_t) (_dispofftime);
}
void
nga_out(uint16_t addr, uint8_t val, void *priv)
{
nga_t *nga = (nga_t *) priv;
cga_out(addr, val, &nga->cga);
}
uint8_t
nga_in(uint16_t addr, void *priv)
{
nga_t *nga = (nga_t *) priv;
return cga_in(addr, &nga->cga);
}
void
nga_waitstates(UNUSED(void *priv))
{
int ws_array[16] = { 3, 4, 5, 6, 7, 8, 4, 5, 6, 7, 8, 4, 5, 6, 7, 8 };
int ws;
ws = ws_array[cycles & 0xf];
sub_cycles(ws);
}
void
nga_write(uint32_t addr, uint8_t val, void *priv)
{
nga_t *nga = (nga_t *) priv;
int offset;
/* a8000-affff */
if (!(addr & 0x10000))
nga->vram_64k[addr & 0x7FFF] = val;
/* b8000-bffff */
else
nga->cga.vram[addr & 0x7FFF] = val;
if (nga->cga.snow_enabled) {
/* recreate snow effect */
offset = ((timer_get_remaining_u64(&nga->cga.timer) / CGACONST) * 4) & 0xfc;
nga->cga.charbuffer[offset] = nga->cga.vram[addr & 0x7fff];
nga->cga.charbuffer[offset | 1] = nga->cga.vram[addr & 0x7fff];
}
nga_waitstates(&nga->cga);
}
uint8_t
nga_read(uint32_t addr, void *priv)
{
nga_t *nga = (nga_t *) priv;
int offset;
uint8_t ret;
/* a8000-affff */
if (!(addr & 0x10000))
ret = nga->vram_64k[addr & 0x7FFF];
else
ret = nga->cga.vram[addr & 0x7FFF];
nga_waitstates(&nga->cga);
if (nga->cga.snow_enabled) {
/* recreate snow effect */
offset = ((timer_get_remaining_u64(&nga->cga.timer) / CGACONST) * 4) & 0xfc;
nga->cga.charbuffer[offset] = nga->cga.vram[addr & 0x7fff];
nga->cga.charbuffer[offset | 1] = nga->cga.vram[addr & 0x7fff];
}
return ret;
}
void
nga_poll(void *priv)
{
nga_t *nga = (nga_t *) priv;
/* set cursor position in memory */
uint16_t ca = (nga->cga.crtc[15] | (nga->cga.crtc[14] << 8)) & 0x3fff;
int drawcursor;
int x;
int c;
int xs_temp;
int ys_temp;
int oldvc;
uint8_t chr;
uint8_t attr;
uint16_t dat;
uint16_t dat2;
int cols[4];
int col;
int oldsc;
/* graphic mode and not high-res modes */
if ((nga->cga.cgamode & 2) && !(nga->cga.cgamode & 0x40)) {
/* standard cga mode */
cga_poll(&nga->cga);
return;
} else {
/* high-res or text mode */
if (!nga->cga.linepos) {
timer_advance_u64(&nga->cga.timer, nga->cga.dispofftime);
nga->cga.cgastat |= 1;
nga->cga.linepos = 1;
oldsc = nga->cga.sc;
/* if interlaced */
if ((nga->cga.crtc[8] & 3) == 3)
nga->cga.sc = ((nga->cga.sc << 1) + nga->cga.oddeven) & 7;
if (nga->cga.cgadispon) {
if (nga->cga.displine < nga->cga.firstline) {
nga->cga.firstline = nga->cga.displine;
video_wait_for_buffer();
}
nga->cga.lastline = nga->cga.displine;
/* 80-col */
if ((nga->cga.cgamode & 1) && !(nga->cga.cgamode & 2)) {
/* for each text column */
for (x = 0; x < nga->cga.crtc[1]; x++) {
/* video output enabled */
if (nga->cga.cgamode & 8) {
/* character */
chr = nga->cga.charbuffer[x << 1];
/* text attributes */
attr = nga->cga.charbuffer[(x << 1) + 1];
} else
chr = attr = 0;
/* check if cursor has to be drawn */
drawcursor = ((nga->cga.ma == ca) && nga->cga.con && nga->cga.cursoron);
/* set foreground */
cols[1] = (attr & 15) + 16;
/* blink active */
if (nga->cga.cgamode & 0x20) {
cols[0] = ((attr >> 4) & 7) + 16;
/* attribute 7 active and not cursor */
if ((nga->cga.cgablink & 8) && (attr & 0x80) && !nga->cga.drawcursor) {
/* set blinking */
cols[1] = cols[0];
}
} else {
/* Set intensity bit */
cols[0] = (attr >> 4) + 16;
}
if (drawcursor) {
for (c = 0; c < 8; c++)
buffer32->line[nga->cga.displine][(x << 3) + c + 8] = cols[(fontdatm[chr][((nga->cga.sc & 7) << 1) | nga->lineff] & (1 << (c ^ 7))) ? 1 : 0] ^ 15;
} else {
for (c = 0; c < 8; c++)
buffer32->line[nga->cga.displine][(x << 3) + c + 8] = cols[(fontdatm[chr][((nga->cga.sc & 7) << 1) | nga->lineff] & (1 << (c ^ 7))) ? 1 : 0];
}
nga->cga.ma++;
}
}
/* 40-col */
else if (!(nga->cga.cgamode & 2)) {
/* for each text column */
for (x = 0; x < nga->cga.crtc[1]; x++) {
if (nga->cga.cgamode & 8) {
chr = nga->cga.vram[((nga->cga.ma << 1) & 0x3fff) + nga->base];
attr = nga->cga.vram[(((nga->cga.ma << 1) + 1) & 0x3fff) + nga->base];
} else {
chr = attr = 0;
}
drawcursor = ((nga->cga.ma == ca) && nga->cga.con && nga->cga.cursoron);
/* set foreground */
cols[1] = (attr & 15) + 16;
/* blink active */
if (nga->cga.cgamode & 0x20) {
cols[0] = ((attr >> 4) & 7) + 16;
if ((nga->cga.cgablink & 8) && (attr & 0x80) && !nga->cga.drawcursor) {
/* set blinking */
cols[1] = cols[0];
}
} else {
/* Set intensity bit */
cols[0] = (attr >> 4) + 16;
}
if (drawcursor) {
for (c = 0; c < 8; c++)
buffer32->line[nga->cga.displine][(x << 4) + (c << 1) + 8] = buffer32->line[nga->cga.displine][(x << 4) + (c << 1) + 1 + 8] = cols[(fontdatm[chr][((nga->cga.sc & 7) << 1) | nga->lineff] & (1 << (c ^ 7))) ? 1 : 0] ^ 15;
} else {
for (c = 0; c < 8; c++)
buffer32->line[nga->cga.displine][(x << 4) + (c << 1) + 8] = buffer32->line[nga->cga.displine][(x << 4) + (c << 1) + 1 + 8] = cols[(fontdatm[chr][((nga->cga.sc & 7) << 1) | nga->lineff] & (1 << (c ^ 7))) ? 1 : 0];
}
nga->cga.ma++;
}
} else {
/* high res modes */
if (nga->cga.cgamode & 0x40) {
/* 640x400x2 mode */
if (nga->cga.cgamode & 0x4 || nga->cga.cgamode & 0x10) {
/*
* Scanlines are read in the following order:
* 0b8000-0b9f3f even scans (0,4,...)
* 0ba000-0bbf3f odd scans (2,6,...)
* 0bc000-0bdf3f even scans (1,5,...)
* 0be000-0bff3f odd scans (3,7,...)
*/
dat2 = ((nga->cga.sc & 1) * 0x2000) | (nga->lineff * 0x4000);
cols[0] = 0;
cols[1] = 15 + 16;
/* 640x400x4 mode */
} else {
cols[0] = (nga->cga.cgacol & 15) | 16;
col = (nga->cga.cgacol & 16) ? 24 : 16;
if (nga->cga.cgamode & 4) {
cols[1] = col | 3; /* Cyan */
cols[2] = col | 4; /* Red */
cols[3] = col | 7; /* White */
} else if (nga->cga.cgacol & 32) {
cols[1] = col | 3; /* Cyan */
cols[2] = col | 5; /* Magenta */
cols[3] = col | 7; /* White */
} else {
cols[1] = col | 2; /* Green */
cols[2] = col | 4; /* Red */
cols[3] = col | 6; /* Yellow */
}
/*
* Scanlines are read in the following order:
* 0b8000-0bbf3f even scans (0,4,...)
* 0bc000-0bff3f odd scans (1,5,...)
* 0a8000-0abf3f even scans (2,6,...)
* 0ac000-0aff3f odd scans (3,7,...)
*/
dat2 = (nga->cga.sc & 1) * 0x4000;
}
} else {
dat2 = (nga->cga.sc & 1) * 0x2000;
cols[0] = 0;
cols[1] = (nga->cga.cgacol & 15) + 16;
}
/* for each text column */
for (x = 0; x < nga->cga.crtc[1]; x++) {
/* video out */
if (nga->cga.cgamode & 8) {
/* 640x400x2 */
if (nga->cga.cgamode & 0x4 || nga->cga.cgamode & 0x10) {
/* read two bytes at a time */
dat = (nga->cga.vram[((nga->cga.ma << 1) & 0x1fff) + dat2] << 8) | nga->cga.vram[((nga->cga.ma << 1) & 0x1fff) + dat2 + 1];
/* each pixel is represented by one bit, so draw 16 pixels at a time */
/* crtc[1] is 40 column, so 40x16=640 pixels */
for (c = 0; c < 16; c++) {
buffer32->line[nga->cga.displine][(x << 4) + c + 8] = cols[dat >> 15];
dat <<= 1;
}
/* 640x400x4 */
} else {
/* lines 2,3,6,7,etc. */
if (nga->cga.sc & 2)
/* read two bytes at a time */
dat = (nga->vram_64k[((nga->cga.ma << 1) & 0x7fff) + dat2] << 8) | nga->vram_64k[((nga->cga.ma << 1) & 0x7fff) + dat2 + 1];
/* lines 0,1,4,5,etc. */
else
/* read two bytes at a time */
dat = (nga->cga.vram[((nga->cga.ma << 1) & 0x7fff) + dat2] << 8) | nga->cga.vram[((nga->cga.ma << 1) & 0x7fff) + dat2 + 1];
/* each pixel is represented by two bits, so draw 8 pixels at a time */
/* crtc[1] is 80 column, so 80x8=640 pixels */
for (c = 0; c < 8; c++) {
buffer32->line[nga->cga.displine][(x << 3) + c + 8] = cols[dat >> 14];
dat <<= 2;
}
}
} else {
dat = 0;
}
nga->cga.ma++;
}
}
} else {
/* nga specific */
cols[0] = ((nga->cga.cgamode & 0x12) == 0x12) ? 0 : (nga->cga.cgacol & 15) + 16;
/* 80-col */
if (nga->cga.cgamode & 1) {
hline(buffer32, 0, (nga->cga.displine << 1), ((nga->cga.crtc[1] << 3) + 16) << 2, cols[0]);
hline(buffer32, 0, (nga->cga.displine << 1) + 1, ((nga->cga.crtc[1] << 3) + 16) << 2, cols[0]);
} else {
hline(buffer32, 0, (nga->cga.displine << 1), ((nga->cga.crtc[1] << 4) + 16) << 2, cols[0]);
hline(buffer32, 0, (nga->cga.displine << 1) + 1, ((nga->cga.crtc[1] << 4) + 16) << 2, cols[0]);
}
}
if (nga->cga.cgamode & 1)
/* set screen width */
x = (nga->cga.crtc[1] << 3) + 16;
else
x = (nga->cga.crtc[1] << 4) + 16;
video_process_8(x, nga->cga.displine);
nga->cga.sc = oldsc;
/* vertical sync */
if (nga->cga.vc == nga->cga.crtc[7] && !nga->cga.sc)
nga->cga.cgastat |= 8;
nga->cga.displine++;
if (nga->cga.displine >= 720)
nga->cga.displine = 0;
} else {
timer_advance_u64(&nga->cga.timer, nga->cga.dispontime);
if (nga->cga.cgadispon)
nga->cga.cgastat &= ~1;
nga->cga.linepos = 0;
/* nga specific */
nga->lineff ^= 1;
/* text mode or 640x400x2 */
if (nga->lineff && !((nga->cga.cgamode & 1) && (nga->cga.cgamode & 0x40))) {
nga->cga.ma = nga->cga.maback;
/* 640x400x4 */
} else {
if (nga->cga.vsynctime) {
nga->cga.vsynctime--;
if (!nga->cga.vsynctime)
nga->cga.cgastat &= ~8;
}
/* cursor stop scanline */
if (nga->cga.sc == (nga->cga.crtc[11] & 31) || ((nga->cga.crtc[8] & 3) == 3 && nga->cga.sc == ((nga->cga.crtc[11] & 31) >> 1))) {
nga->cga.con = 0;
nga->cga.coff = 1;
}
/* interlaced and max scanline per char reached */
if ((nga->cga.crtc[8] & 3) == 3 && nga->cga.sc == (nga->cga.crtc[9] >> 1))
nga->cga.maback = nga->cga.ma;
if (nga->cga.vadj) {
nga->cga.sc++;
nga->cga.sc &= 31;
nga->cga.ma = nga->cga.maback;
nga->cga.vadj--;
if (!nga->cga.vadj) {
nga->cga.cgadispon = 1;
/* change start of displayed page (crtc 12-13) */
nga->cga.ma = nga->cga.maback = (nga->cga.crtc[13] | (nga->cga.crtc[12] << 8)) & 0x7fff;
nga->cga.sc = 0;
}
/* nga specific */
/* end of character line reached */
} else if (nga->cga.sc == nga->cga.crtc[9] || ((nga->cga.crtc[8] & 3) == 3 && nga->cga.sc == (nga->cga.crtc[9] >> 1))) {
nga->cga.maback = nga->cga.ma;
nga->cga.sc = 0;
oldvc = nga->cga.vc;
nga->cga.vc++;
nga->cga.vc &= 127;
/* lines of character displayed */
if (nga->cga.vc == nga->cga.crtc[6])
nga->cga.cgadispon = 0;
/* total vertical lines */
if (oldvc == nga->cga.crtc[4]) {
nga->cga.vc = 0;
/* adjust vertical lines */
nga->cga.vadj = nga->cga.crtc[5];
if (!nga->cga.vadj) {
nga->cga.cgadispon = 1;
/* change start of displayed page (crtc 12-13) */
nga->cga.ma = nga->cga.maback = (nga->cga.crtc[13] | (nga->cga.crtc[12] << 8)) & 0x7fff;
}
/* cursor start */
switch (nga->cga.crtc[10] & 0x60) {
case 0x20:
nga->cga.cursoron = 0;
break;
case 0x60:
nga->cga.cursoron = nga->cga.cgablink & 0x10;
break;
default:
nga->cga.cursoron = nga->cga.cgablink & 0x08;
break;
}
}
/* vertical line position */
if (nga->cga.vc == nga->cga.crtc[7]) {
nga->cga.cgadispon = 0;
nga->cga.displine = 0;
/* nga specific */
nga->cga.vsynctime = 16;
/* vsync pos */
if (nga->cga.crtc[7]) {
if (nga->cga.cgamode & 1)
/* set screen width */
x = (nga->cga.crtc[1] << 3) + 16;
else
x = (nga->cga.crtc[1] << 4) + 16;
nga->cga.lastline++;
xs_temp = x;
ys_temp = (nga->cga.lastline - nga->cga.firstline);
if ((xs_temp > 0) && (ys_temp > 0)) {
if (xsize < 64)
xs_temp = 656;
/* nga specific */
if (ysize < 32)
ys_temp = 400;
if (!enable_overscan)
xs_temp -= 16;
if ((nga->cga.cgamode & 8) && ((xs_temp != xsize) || (ys_temp != ysize) || video_force_resize_get())) {
xsize = xs_temp;
ysize = ys_temp;
set_screen_size(xsize, ysize + (enable_overscan ? 16 : 0));
if (video_force_resize_get())
video_force_resize_set(0);
}
/* nga specific */
if (enable_overscan) {
video_blit_memtoscreen(0, (nga->cga.firstline - 8),
xsize, (nga->cga.lastline - nga->cga.firstline) + 16);
} else {
video_blit_memtoscreen(8, nga->cga.firstline,
xsize, (nga->cga.lastline - nga->cga.firstline));
}
}
frames++;
video_res_x = xsize;
video_res_y = ysize;
/* 80-col */
if ((nga->cga.cgamode & 1) && !(nga->cga.cgamode & 0x40)) {
video_res_x /= 8;
video_res_y /= (nga->cga.crtc[9] + 1) * 2;
video_bpp = 0;
/* 40-col */
} else if (!(nga->cga.cgamode & 2)) {
video_res_x /= 16;
video_res_y /= (nga->cga.crtc[9] + 1) * 2;
video_bpp = 0;
} else if (nga->cga.cgamode & 0x40) {
video_res_x /= 8;
video_res_y /= 2;
video_bpp = 1;
}
}
nga->cga.firstline = 1000;
nga->cga.lastline = 0;
nga->cga.cgablink++;
nga->cga.oddeven ^= 1;
}
} else {
nga->cga.sc++;
nga->cga.sc &= 31;
nga->cga.ma = nga->cga.maback;
}
if (nga->cga.cgadispon)
nga->cga.cgastat &= ~1;
/* enable cursor if its scanline was reached */
if (nga->cga.sc == (nga->cga.crtc[10] & 31) || ((nga->cga.crtc[8] & 3) == 3 && nga->cga.sc == ((nga->cga.crtc[10] & 31) >> 1)))
nga->cga.con = 1;
}
/* 80-columns */
if (nga->cga.cgadispon && (nga->cga.cgamode & 1)) {
/* for each character per line */
for (x = 0; x < (nga->cga.crtc[1] << 1); x++)
nga->cga.charbuffer[x] = nga->cga.vram[(((nga->cga.ma << 1) + x) & 0x3fff) + nga->base];
}
}
}
}
void
nga_close(void *priv)
{
nga_t *nga = (nga_t *) priv;
free(nga->vram_64k);
free(nga->cga.vram);
free(nga);
}
void
nga_speed_changed(void *priv)
{
nga_t *nga = (nga_t *) priv;
nga_recalctimings(nga);
}
void *
nga_init(UNUSED(const device_t *info))
{
int mem;
uint8_t charset;
nga_t *nga = (nga_t *) malloc(sizeof(nga_t));
memset(nga, 0x00, sizeof(nga_t));
video_inform(VIDEO_FLAG_TYPE_CGA, &timing_nga);
charset = device_get_config_int("charset");
loadfont_ex("roms/video/nga/ncr_nga_35122.bin", 1, 4096 * charset);
nga->cga.composite = 0;
nga->cga.snow_enabled = device_get_config_int("snow_enabled");
nga->cga.vram = malloc(0x8000);
nga->vram_64k = malloc(0x8000);
timer_add(&nga->cga.timer, nga_poll, nga, 1);
mem_mapping_add(&nga->cga.mapping, 0xb8000, 0x8000,
nga_read, NULL, NULL,
nga_write, NULL, NULL, NULL, 0, nga);
mem = device_get_config_int("memory");
if (mem > 32) {
/* make optional 32KB addessable */
mem_mapping_add(&nga->mapping_64k, 0xa8000, 0x8000,
nga_read, NULL, NULL,
nga_write, NULL, NULL, NULL, 0, nga);
}
io_sethandler(0x03d0, 16, nga_in, NULL, NULL, nga_out, NULL, NULL, nga);
overscan_x = overscan_y = 16;
nga->cga.rgb_type = device_get_config_int("rgb_type");
cga_palette = (nga->cga.rgb_type << 1);
cgapal_rebuild();
return nga;
}
const device_config_t nga_config[] = {
// clang-format off
{
.name = "rgb_type",
.description = "RGB type",
.type = CONFIG_SELECTION,
.default_int = 0,
.selection = {
{
.description = "Color",
.value = 0
},
{
.description = "Green Monochrome",
.value = 1
},
{
.description = "Amber Monochrome",
.value = 2
},
{
.description = "Gray Monochrome",
.value = 3
},
{
.description = "Color (no brown)",
.value = 4
},
{
.description = ""
}
}
},
{
.name = "snow_enabled",
.description = "Snow emulation",
.type = CONFIG_BINARY,
.default_int = 1
},
{
.name = "memory",
.description = "Memory size",
.type = CONFIG_SELECTION,
.default_int = 64,
.selection = {
{
.description = "32 KB",
.value = 32
},
{
.description = "64 KB",
.value = 64
},
{
.description = ""
}
}
},
{
.name = "charset",
.description = "Character set",
.type = CONFIG_SELECTION,
.default_int = 0,
.selection = {
{
.description = "U.S. English",
.value = 0
},
{
.description = "Scandinavian",
.value = 1
},
{
.description = "Other languages",
.value = 2
},
{
.description = "E.F. Hutton",
.value = 3
},
{
.description = ""
}
}
},
{
.type = CONFIG_END
}
// clang-format on
};
const device_t nga_device = {
.name = "NCR NGA",
.internal_name = "nga",
.flags = DEVICE_ISA,
.local = 0,
.init = nga_init,
.close = nga_close,
.reset = NULL,
{ .available = NULL },
.speed_changed = nga_speed_changed,
.force_redraw = NULL,
.config = nga_config
};
``` | /content/code_sandbox/src/video/vid_nga.c | c | 2016-06-25T22:29:10 | 2024-08-16T19:09:21 | 86Box | 86Box/86Box | 2,616 | 7,300 |
```c
/*
* 86Box A hypervisor and IBM PC system emulator that specializes in
* running old operating systems and software designed for IBM
* PC systems and compatibles from 1981 through fairly recent
* system designs based on the PCI bus.
*
* This file is part of the 86Box distribution.
*
* Emulation of the Tseng Labs ET3000.
*
*
*
* Authors: Miran Grca, <mgrca8@gmail.com>
*
*/
#include <stdarg.h>
#include <stdint.h>
#include <stdio.h>
#include <string.h>
#include <stdlib.h>
#include <wchar.h>
#define HAVE_STDARG_H
#include <86box/86box.h>
#include <86box/io.h>
#include <86box/mca.h>
#include <86box/mem.h>
#include <86box/rom.h>
#include <86box/device.h>
#include <86box/timer.h>
#include <86box/video.h>
#include <86box/vid_svga.h>
#include <86box/vid_svga_render.h>
#define BIOS_ROM_PATH "roms/video/et3000/Tseng ET3000AX ISA VGA-VGA ULTRA.bin"
typedef struct {
const char *name;
int type;
svga_t svga;
rom_t bios_rom;
uint8_t pel_wd;
uint8_t banking;
uint8_t reg_3d8;
uint8_t reg_3bf;
uint8_t tries;
uint8_t ext_enable;
} et3000_t;
static video_timings_t timing_et3000_isa = { VIDEO_ISA, 3, 3, 6, 5, 5, 10 };
static uint8_t et3000_in(uint16_t addr, void *priv);
static void et3000_out(uint16_t addr, uint8_t val, void *priv);
#ifdef ENABLE_ET3000_LOG
int svga_do_log = ENABLE_ET3000_LOG;
static void
et3000_log(const char *fmt, ...)
{
va_list ap;
if (et3000_do_log) {
va_start(ap, fmt);
pclog_ex(fmt, ap);
va_end(ap);
}
}
#else
# define et3000_log(fmt, ...)
#endif
static uint8_t
et3000_in(uint16_t addr, void *priv)
{
et3000_t *dev = (et3000_t *) priv;
svga_t *svga = &dev->svga;
uint8_t ret = 0xff;
if ((addr >= 0x03b0) && (addr < 0x03bc) && (svga->miscout & 1))
return 0xff;
if ((addr >= 0x03d0) && (addr < 0x03dc) && !(svga->miscout & 1))
return 0xff;
switch (addr) {
default:
ret = svga_in(addr, svga);
#ifdef ENABLE_ET3000_LOG
if (addr != 0x03da)
et3000_log("[%04X:%08X] [R] %04X = %02X\n", CS, cpu_state.pc, addr, ret);
#endif
break;
case 0x3c1:
/* It appears the extended attribute registers are **NOT**
protected by key on the ET3000AX, as the BIOS attempts to
write to attribute register 16h without the key. */
ret = svga_in(addr, svga);
et3000_log("[%04X:%08X] [R] %04X: %02X = %02X (%i)\n", CS, cpu_state.pc,
addr, svga->attraddr, ret, dev->ext_enable);
break;
case 0x3c5:
if ((svga->seqaddr >= 6) && !dev->ext_enable)
ret = 0xff;
else
ret = svga_in(addr, svga);
et3000_log("[%04X:%08X] [R] %04X: %02X = %02X (%i)\n", CS, cpu_state.pc,
addr, svga->seqaddr, ret, dev->ext_enable);
break;
case 0x3cf:
if ((svga->gdcaddr >= 0x0d) && !dev->ext_enable)
ret = 0xff;
else
ret = svga_in(addr, svga);
et3000_log("[%04X:%08X] [R] %04X: %02X = %02X (%i)\n", CS, cpu_state.pc,
addr, svga->gdcaddr & 15, ret, dev->ext_enable);
break;
case 0x3cb: /*PEL Address/Data Wd*/
ret = dev->pel_wd;
et3000_log("[%04X:%08X] [R] %04X = %02X\n", CS, cpu_state.pc, addr, ret);
break;
case 0x3cd: /*Banking*/
ret = dev->banking;
et3000_log("[%04X:%08X] [R] %04X = %02X\n", CS, cpu_state.pc, addr, ret);
break;
case 0x3b4:
case 0x3d4:
ret = svga->crtcreg;
et3000_log("[%04X:%08X] [R] %04X = %02X\n", CS, cpu_state.pc, addr, ret);
break;
case 0x3b5:
case 0x3d5:
if ((svga->crtcreg >= 0x18) && (svga->crtcreg < 0x23) && !dev->ext_enable)
ret = 0xff;
else if (svga->crtcreg > 0x25)
ret = 0xff;
else
ret = svga->crtc[svga->crtcreg];
et3000_log("[%04X:%08X] [R] %04X: %02X = %02X\n", CS, cpu_state.pc,
addr, svga->crtcreg, ret);
break;
case 0x3b8:
case 0x3d8:
ret = dev->reg_3d8;
et3000_log("[%04X:%08X] [R] %04X = %02X\n", CS, cpu_state.pc, addr, ret);
break;
case 0x3ba:
case 0x3da:
svga->attrff = 0;
if (svga->cgastat & 0x01)
svga->cgastat &= ~0x30;
else
svga->cgastat ^= 0x30;
ret = svga->cgastat;
if ((svga->fcr & 0x08) && svga->dispon)
ret |= 0x08;
break;
case 0x3bf:
ret = dev->reg_3bf;
et3000_log("[%04X:%08X] [R] %04X = %02X\n", CS, cpu_state.pc, addr, ret);
break;
}
return ret;
}
static void
et3000_out(uint16_t addr, uint8_t val, void *priv)
{
et3000_t *dev = (et3000_t *) priv;
svga_t *svga = &dev->svga;
uint8_t old;
uint8_t index;
et3000_log("[%04X:%08X] [W] %04X = %02X\n", CS, cpu_state.pc, addr, val);
if ((addr >= 0x03b0) && (addr < 0x03bc) && (svga->miscout & 1))
return;
if ((addr >= 0x03d0) && (addr < 0x03dc) && !(svga->miscout & 1))
return;
switch (addr) {
case 0x3c0:
/* It appears the extended attribute registers are **NOT**
protected by key on the ET3000AX, as the BIOS attempts to
write to attribute register 16h without the key. */
if (svga->attrff && (svga->attraddr == 0x11) && (svga->attrregs[0x16] & 0x01))
val = (val & 0xf0) | (svga->attrregs[0x11] & 0x0f);
#ifdef ENABLE_ET3000_LOG
if (svga->attrff && (svga->attraddr > 0x14))
et3000_log("3C1: %02X = %02X\n", svga->attraddr, val);
#endif
if (svga->attrff && (svga->attraddr == 0x16)) {
svga->attrregs[0x16] = val;
svga->chain4 &= ~0x10;
if (svga->gdcreg[5] & 0x40)
svga->chain4 |= (svga->attrregs[0x16] & 0x10);
svga_recalctimings(svga);
return;
}
break;
case 0x3c1:
return;
case 0x3c2:
svga->miscout = val;
svga->vidclock = val & 4;
svga_recalctimings(svga);
return;
case 0x3c4:
svga->seqaddr = val & 0x07;
return;
case 0x3c5:
if ((svga->seqaddr >= 6) && !dev->ext_enable)
return;
if (svga->seqaddr == 4) {
svga->seqregs[4] = val;
svga->chain2_write = !(val & 4);
svga->chain4 = (svga->chain4 & ~8) | (val & 8);
et3000_log("CHAIN2 = %i, CHAIN4 = %i\n", svga->chain2_write, svga->chain4);
svga->fast = (svga->gdcreg[8] == 0xff && !(svga->gdcreg[3] & 0x18) &&
!svga->gdcreg[1]) && svga->chain4 &&
!(svga->adv_flags & FLAG_ADDR_BY8);
return;
}
#ifdef ENABLE_ET3000_LOG
else if (svga->seqaddr > 4)
et3000_log("3C5: %02X = %02X\n", svga->seqaddr, val);
#endif
break;
case 0x3c9:
if (svga->adv_flags & FLAG_RAMDAC_SHIFT)
val <<= 2;
svga->fullchange = svga->monitor->mon_changeframecount;
switch (svga->dac_pos) {
case 0:
if (!(svga->attrregs[0x16] & 0x02) && !(svga->attrregs[0x17] & 0x80))
svga->dac_r = val;
svga->dac_pos++;
break;
case 1:
if (!(svga->attrregs[0x16] & 0x02) && !(svga->attrregs[0x17] & 0x80))
svga->dac_g = val;
svga->dac_pos++;
break;
case 2:
index = svga->dac_addr & 255;
if (!(svga->attrregs[0x16] & 0x02) && !(svga->attrregs[0x17] & 0x80)) {
svga->dac_b = val;
svga->vgapal[index].r = svga->dac_r;
svga->vgapal[index].g = svga->dac_g;
svga->vgapal[index].b = svga->dac_b;
if (svga->ramdac_type == RAMDAC_8BIT)
svga->pallook[index] = makecol32(svga->vgapal[index].r, svga->vgapal[index].g,
svga->vgapal[index].b);
else
svga->pallook[index] = makecol32(video_6to8[svga->vgapal[index].r & 0x3f],
video_6to8[svga->vgapal[index].g & 0x3f],
video_6to8[svga->vgapal[index].b & 0x3f]);
}
svga->dac_pos = 0;
svga->dac_addr = (svga->dac_addr + 1) & 255;
break;
default:
break;
}
return;
case 0x3cb: /*PEL Address/Data Wd*/
et3000_log("3CB = %02X\n", val);
dev->pel_wd = val;
break;
case 0x3cd: /*Banking*/
et3000_log("3CD = %02X\n", val);
if (!(svga->crtc[0x23] & 0x80) && !(svga->gdcreg[6] & 0x08)) {
switch ((val >> 6) & 3) {
case 0: /*128K segments*/
svga->write_bank = ((val >> 0) & 7) << 17;
svga->read_bank = ((val >> 3) & 7) << 17;
break;
case 1: /*64K segments*/
svga->write_bank = (val & 7) << 16;
svga->read_bank = ((val >> 3) & 7) << 16;
break;
default:
break;
}
}
dev->banking = val;
return;
case 0x3ce:
svga->gdcaddr = val & 0x0f;
return;
case 0x3cf:
if ((svga->gdcaddr >= 0x0d) && !dev->ext_enable)
return;
if ((svga->gdcaddr & 15) == 5) {
svga->chain4 &= ~0x10;
if (val & 0x40)
svga->chain4 |= (svga->attrregs[0x16] & 0x10);
} else if ((svga->gdcaddr & 15) == 6) {
if (!(svga->crtc[0x23] & 0x80) && !(val & 0x08)) {
switch ((dev->banking >> 6) & 3) {
case 0: /*128K segments*/
svga->write_bank = ((dev->banking >> 0) & 7) << 17;
svga->read_bank = ((dev->banking >> 3) & 7) << 17;
break;
case 1: /*64K segments*/
svga->write_bank = (dev->banking & 7) << 16;
svga->read_bank = ((dev->banking >> 3) & 7) << 16;
break;
default:
break;
}
} else
svga->write_bank = svga->read_bank = 0;
old = svga->gdcreg[6];
svga_out(addr, val, svga);
if ((old & 0xc) != 0 && (val & 0xc) == 0) {
/* Override mask - ET3000 supports linear 128k at A0000. */
svga->banked_mask = 0x1ffff;
}
return;
}
#ifdef ENABLE_ET3000_LOG
else if ((svga->gdcaddr & 15) > 8)
et3000_log("3CF: %02X = %02X\n", (svga->gdcaddr & 15), val);
#endif
break;
case 0x3b4:
case 0x3d4:
svga->crtcreg = val & 0x3f;
return;
case 0x3b5:
case 0x3d5:
if ((svga->crtcreg >= 0x18) && (svga->crtcreg < 0x23) && !dev->ext_enable)
return;
else if (svga->crtcreg > 0x25)
return;
/* Unlike the ET4000AX, which protects all bits of the
overflow high register (0x35 there, 0x25 here) except for
bits 4 and 7, if bit 7 of CRTC 11h is set, the ET3000AX
does not to that. */
if ((svga->crtcreg < 7) && (svga->crtc[0x11] & 0x80))
return;
if ((svga->crtcreg == 7) && (svga->crtc[0x11] & 0x80))
val = (svga->crtc[7] & ~0x10) | (val & 0x10);
old = svga->crtc[svga->crtcreg];
svga->crtc[svga->crtcreg] = val;
#ifdef ENABLE_ET3000_LOG
if (svga->crtcreg > 0x18)
et3000_log("3D5: %02X = %02X\n", svga->crtcreg, val);
#endif
if (old != val) {
if (svga->crtcreg < 0x0e || svga->crtcreg > 0x10) {
svga->fullchange = changeframecount;
svga_recalctimings(svga);
}
}
break;
case 0x3b8:
case 0x3d8:
et3000_log("%04X = %02X\n", addr, val);
dev->reg_3d8 = val;
if ((val == 0xa0) && (dev->tries == 1)) {
dev->ext_enable = 1;
dev->tries = 0;
} else if (val == 0x29)
dev->tries = 1;
return;
case 0x3bf:
et3000_log("%04X = %02X\n", addr, val);
dev->reg_3bf = val;
if ((val == 0x01) && (dev->tries == 1)) {
dev->ext_enable = 0;
dev->tries = 0;
} else if (val == 0x03)
dev->tries = 1;
return;
default:
break;
}
svga_out(addr, val, svga);
}
static void
et3000_recalctimings(svga_t *svga)
{
svga->ma_latch |= (svga->crtc[0x23] & 2) << 15;
if (svga->crtc[0x25] & 1)
svga->vblankstart |= 0x400;
if (svga->crtc[0x25] & 2)
svga->vtotal |= 0x400;
if (svga->crtc[0x25] & 4)
svga->dispend |= 0x400;
if (svga->crtc[0x25] & 8)
svga->vsyncstart |= 0x400;
if (svga->crtc[0x25] & 0x10)
svga->split |= 0x400;
svga->interlace = !!(svga->crtc[0x25] & 0x80);
if (svga->attrregs[0x16] & 0x10) {
svga->ma_latch <<= (1 << 0);
svga->rowoffset <<= (1 << 0);
switch (svga->gdcreg[5] & 0x60) {
case 0x00:
svga->render = svga_render_4bpp_highres;
svga->hdisp *= 2;
break;
case 0x20:
svga->render = svga_render_2bpp_highres;
break;
case 0x40:
case 0x60:
svga->render = svga_render_8bpp_highres;
break;
default:
break;
}
}
et3000_log("HDISP = %i, HTOTAL = %i, ROWOFFSET = %i, INTERLACE = %i\n",
svga->hdisp, svga->htotal, svga->rowoffset, svga->interlace);
switch (((svga->miscout >> 2) & 3) | ((svga->crtc[0x24] << 1) & 4)) {
case 0:
case 1:
break;
case 3:
svga->clock = (cpuclock * (double) (1ULL << 32)) / 40000000.0;
break;
case 5:
svga->clock = (cpuclock * (double) (1ULL << 32)) / 65000000.0;
break;
default:
svga->clock = (cpuclock * (double) (1ULL << 32)) / 36000000.0;
break;
}
}
static void *
et3000_init(const device_t *info)
{
const char *fn;
et3000_t *dev;
dev = (et3000_t *) malloc(sizeof(et3000_t));
memset(dev, 0x00, sizeof(et3000_t));
dev->name = info->name;
dev->type = info->local;
fn = BIOS_ROM_PATH;
switch (dev->type) {
case 0: /* ISA ET3000AX */
video_inform(VIDEO_FLAG_TYPE_SPECIAL, &timing_et3000_isa);
svga_init(info, &dev->svga, dev, device_get_config_int("memory") << 10,
et3000_recalctimings, et3000_in, et3000_out,
NULL, NULL);
io_sethandler(0x03b0, 48,
et3000_in, NULL, NULL, et3000_out, NULL, NULL, dev);
break;
default:
break;
}
rom_init(&dev->bios_rom, fn,
0xc0000, 0x8000, 0x7fff, 0, MEM_MAPPING_EXTERNAL);
dev->svga.bpp = 8;
dev->svga.miscout = 1;
dev->svga.packed_chain4 = 1;
return dev;
}
static void
et3000_close(void *priv)
{
et3000_t *dev = (et3000_t *) priv;
svga_close(&dev->svga);
free(dev);
}
static void
et3000_speed_changed(void *priv)
{
et3000_t *dev = (et3000_t *) priv;
svga_recalctimings(&dev->svga);
}
static void
et3000_force_redraw(void *priv)
{
et3000_t *dev = (et3000_t *) priv;
dev->svga.fullchange = changeframecount;
}
static int
et3000_available(void)
{
return rom_present(BIOS_ROM_PATH);
}
static const device_config_t et3000_config[] = {
{ .name = "memory",
.description = "Memory size",
.type = CONFIG_SELECTION,
.default_int = 512,
.selection = {
{ .description = "256 KB",
.value = 256 },
{ .description = "512 KB",
.value = 512 },
{ .description = "" } } },
{ .type = CONFIG_END }
};
const device_t et3000_isa_device = {
.name = "Tseng Labs ET3000AX (ISA)",
.internal_name = "et3000ax",
.flags = DEVICE_ISA,
.local = 0,
.init = et3000_init,
.close = et3000_close,
.reset = NULL,
{ .available = et3000_available },
.speed_changed = et3000_speed_changed,
.force_redraw = et3000_force_redraw,
.config = et3000_config
};
``` | /content/code_sandbox/src/video/vid_et3000.c | c | 2016-06-25T22:29:10 | 2024-08-16T19:09:21 | 86Box | 86Box/86Box | 2,616 | 5,600 |
```c
/*
* 86Box A hypervisor and IBM PC system emulator that specializes in
* running old operating systems and software designed for IBM
* PC systems and compatibles from 1981 through fairly recent
* system designs based on the PCI bus.
*
* This file is part of the 86Box distribution.
*
* Hercules Plus emulation.
*
*
*
* Authors: Sarah Walker, <path_to_url
* Miran Grca, <mgrca8@gmail.com>
*
*/
#include <stdio.h>
#include <stdint.h>
#include <stdlib.h>
#include <string.h>
#include <wchar.h>
#include <86box/86box.h>
#include <86box/io.h>
#include <86box/lpt.h>
#include <86box/timer.h>
#include <86box/pit.h>
#include <86box/mem.h>
#include <86box/rom.h>
#include <86box/device.h>
#include <86box/video.h>
#include <86box/plat_unused.h>
/* extended CRTC registers */
#define HERCULESPLUS_CRTC_XMODE 20 /* xMode register */
#define HERCULESPLUS_CRTC_UNDER 21 /* Underline */
#define HERCULESPLUS_CRTC_OVER 22 /* Overstrike */
/* character width */
#define HERCULESPLUS_CW ((dev->crtc[HERCULESPLUS_CRTC_XMODE] & HERCULESPLUS_XMODE_90COL) ? 8 : 9)
/* mode control register */
#define HERCULESPLUS_CTRL_GRAPH 0x02
#define HERCULESPLUS_CTRL_ENABLE 0x08
#define HERCULESPLUS_CTRL_BLINK 0x20
#define HERCULESPLUS_CTRL_PAGE1 0x80
/* CRTC status register */
#define HERCULESPLUS_STATUS_HSYNC 0x01 /* horizontal sync */
#define HERCULESPLUS_STATUS_LIGHT 0x02
#define HERCULESPLUS_STATUS_VIDEO 0x08
#define HERCULESPLUS_STATUS_ID 0x10 /* Card identification */
#define HERCULESPLUS_STATUS_VSYNC 0x80 /* -vertical sync */
/* configuration switch register */
#define HERCULESPLUS_CTRL2_GRAPH 0x01
#define HERCULESPLUS_CTRL2_PAGE1 0x02
/* extended mode register */
#define HERCULESPLUS_XMODE_RAMFONT 0x01
#define HERCULESPLUS_XMODE_90COL 0x02
typedef struct {
mem_mapping_t mapping;
uint8_t crtc[32];
int crtcreg;
uint8_t ctrl, ctrl2, stat;
uint64_t dispontime, dispofftime;
pc_timer_t timer;
int firstline, lastline;
int linepos, displine;
int vc, sc;
uint16_t ma, maback;
int con, coff, cursoron;
int dispon, blink;
int vsynctime;
int vadj;
int monitor_index, prev_monitor_index;
int cols[256][2][2];
uint8_t *vram;
} herculesplus_t;
#define VIDEO_MONITOR_PROLOGUE() \
{ \
dev->prev_monitor_index = monitor_index_global; \
monitor_index_global = dev->monitor_index; \
}
#define VIDEO_MONITOR_EPILOGUE() \
{ \
monitor_index_global = dev->prev_monitor_index; \
}
static video_timings_t timing_herculesplus = { .type = VIDEO_ISA, .write_b = 8, .write_w = 16, .write_l = 32, .read_b = 8, .read_w = 16, .read_l = 32 };
static void
recalc_timings(herculesplus_t *dev)
{
double disptime;
double _dispontime;
double _dispofftime;
disptime = dev->crtc[0] + 1;
_dispontime = dev->crtc[1];
_dispofftime = disptime - _dispontime;
_dispontime *= HERCCONST;
_dispofftime *= HERCCONST;
dev->dispontime = (uint64_t) (_dispontime);
dev->dispofftime = (uint64_t) (_dispofftime);
}
static void
herculesplus_out(uint16_t port, uint8_t val, void *priv)
{
herculesplus_t *dev = (herculesplus_t *) priv;
uint8_t old;
switch (port) {
case 0x3b0:
case 0x3b2:
case 0x3b4:
case 0x3b6:
dev->crtcreg = val & 31;
return;
case 0x3b1:
case 0x3b3:
case 0x3b5:
case 0x3b7:
if (dev->crtcreg > 22)
return;
old = dev->crtc[dev->crtcreg];
dev->crtc[dev->crtcreg] = val;
if (dev->crtc[10] == 6 && dev->crtc[11] == 7) {
/*Fix for Generic Turbo XT BIOS,
*which sets up cursor registers wrong*/
dev->crtc[10] = 0xb;
dev->crtc[11] = 0xc;
}
if (old ^ val)
recalc_timings(dev);
return;
case 0x3b8:
old = dev->ctrl;
dev->ctrl = val;
if (old ^ val)
recalc_timings(dev);
return;
case 0x3bf:
dev->ctrl2 = val;
if (val & 2)
mem_mapping_set_addr(&dev->mapping, 0xb0000, 0x10000);
else
mem_mapping_set_addr(&dev->mapping, 0xb0000, 0x08000);
return;
default:
break;
}
}
static uint8_t
herculesplus_in(uint16_t port, void *priv)
{
const herculesplus_t *dev = (herculesplus_t *) priv;
uint8_t ret = 0xff;
switch (port) {
case 0x3b0:
case 0x3b2:
case 0x3b4:
case 0x3b6:
ret = dev->crtcreg;
break;
case 0x3b1:
case 0x3b3:
case 0x3b5:
case 0x3b7:
if (dev->crtcreg <= 22)
ret = dev->crtc[dev->crtcreg];
break;
case 0x3ba:
/* 0x10: Hercules Plus card identity */
ret = (dev->stat & 0xf) | ((dev->stat & 8) << 4) | 0x10;
break;
default:
break;
}
return ret;
}
static void
herculesplus_write(uint32_t addr, uint8_t val, void *priv)
{
herculesplus_t *dev = (herculesplus_t *) priv;
dev->vram[addr & 0xffff] = val;
}
static uint8_t
herculesplus_read(uint32_t addr, void *priv)
{
const herculesplus_t *dev = (herculesplus_t *) priv;
return dev->vram[addr & 0xffff];
}
static void
draw_char_rom(herculesplus_t *dev, int x, uint8_t chr, uint8_t attr)
{
unsigned ull;
unsigned val;
unsigned ifg;
unsigned ibg;
const uint8_t *fnt;
int elg;
int blk;
int cw = HERCULESPLUS_CW;
int blink = dev->ctrl & HERCULESPLUS_CTRL_BLINK;
blk = 0;
if (blink) {
if (attr & 0x80)
blk = (dev->blink & 16);
attr &= 0x7f;
}
/* MDA-compatible attributes */
ibg = 0;
ifg = 7;
if ((attr & 0x77) == 0x70) { /* Invert */
ifg = 0;
ibg = 7;
}
if (attr & 8)
ifg |= 8; /* High intensity FG */
if (attr & 0x80)
ibg |= 8; /* High intensity BG */
if ((attr & 0x77) == 0) /* Blank */
ifg = ibg;
ull = ((attr & 0x07) == 1) ? 13 : 0xffff;
if (dev->crtc[HERCULESPLUS_CRTC_XMODE] & HERCULESPLUS_XMODE_90COL)
elg = 0;
else
elg = ((chr >= 0xc0) && (chr <= 0xdf));
fnt = &(fontdatm[chr][dev->sc]);
if (blk) {
val = 0x000; /* Blinking, draw all background */
} else if (dev->sc == ull) {
val = 0x1ff; /* Underscore, draw all foreground */
} else {
val = fnt[0] << 1;
if (elg)
val |= (val >> 1) & 1;
}
for (int i = 0; i < cw; i++) {
buffer32->line[dev->displine][x * cw + i] = (val & 0x100) ? ifg : ibg;
val = val << 1;
}
}
static void
draw_char_ram4(herculesplus_t *dev, int x, uint8_t chr, uint8_t attr)
{
unsigned ull;
unsigned val;
unsigned ifg;
unsigned ibg;
const uint8_t *fnt;
int elg;
int blk;
int cw = HERCULESPLUS_CW;
int blink = dev->ctrl & HERCULESPLUS_CTRL_BLINK;
blk = 0;
if (blink) {
if (attr & 0x80)
blk = (dev->blink & 16);
attr &= 0x7f;
}
/* MDA-compatible attributes */
ibg = 0;
ifg = 7;
if ((attr & 0x77) == 0x70) { /* Invert */
ifg = 0;
ibg = 7;
}
if (attr & 8)
ifg |= 8; /* High intensity FG */
if (attr & 0x80)
ibg |= 8; /* High intensity BG */
if ((attr & 0x77) == 0) /* Blank */
ifg = ibg;
ull = ((attr & 0x07) == 1) ? 13 : 0xffff;
if (dev->crtc[HERCULESPLUS_CRTC_XMODE] & HERCULESPLUS_XMODE_90COL)
elg = 0;
else
elg = ((chr >= 0xc0) && (chr <= 0xdf));
fnt = dev->vram + 0x4000 + 16 * chr + dev->sc;
if (blk) {
val = 0x000; /* Blinking, draw all background */
} else if (dev->sc == ull) {
val = 0x1ff; /* Underscore, draw all foreground */
} else {
val = fnt[0] << 1;
if (elg)
val |= (val >> 1) & 1;
}
for (int i = 0; i < cw; i++) {
buffer32->line[dev->displine][x * cw + i] = (val & 0x100) ? ifg : ibg;
val = val << 1;
}
}
static void
draw_char_ram48(herculesplus_t *dev, int x, uint8_t chr, uint8_t attr)
{
unsigned ull;
unsigned val;
unsigned ifg;
unsigned ibg;
const uint8_t *fnt;
int elg;
int blk;
int cw = HERCULESPLUS_CW;
int blink = dev->ctrl & HERCULESPLUS_CTRL_BLINK;
int font = (attr & 0x0F);
if (font >= 12)
font &= 7;
attr = (attr >> 4) ^ 0x0f;
blk = 0;
if (blink) {
if (attr & 0x80)
blk = (dev->blink & 16);
attr &= 0x7f;
}
/* MDA-compatible attributes */
ibg = 0;
ifg = 7;
if ((attr & 0x77) == 0x70) { /* Invert */
ifg = 0;
ibg = 7;
}
if (attr & 8)
ifg |= 8; /* High intensity FG */
if (attr & 0x80)
ibg |= 8; /* High intensity BG */
if ((attr & 0x77) == 0) /* Blank */
ifg = ibg;
ull = ((attr & 0x07) == 1) ? 13 : 0xffff;
if (dev->crtc[HERCULESPLUS_CRTC_XMODE] & HERCULESPLUS_XMODE_90COL)
elg = 0;
else
elg = ((chr >= 0xc0) && (chr <= 0xdf));
fnt = dev->vram + 0x4000 + 16 * chr + 4096 * font + dev->sc;
if (blk) {
val = 0x000; /* Blinking, draw all background */
} else if (dev->sc == ull) {
val = 0x1ff; /* Underscore, draw all foreground */
} else {
val = fnt[0] << 1;
if (elg)
val |= (val >> 1) & 1;
}
for (int i = 0; i < cw; i++) {
buffer32->line[dev->displine][x * cw + i] = (val & 0x100) ? ifg : ibg;
val = val << 1;
}
}
static void
text_line(herculesplus_t *dev, uint16_t ca)
{
int drawcursor;
uint8_t chr;
uint8_t attr;
uint32_t col;
for (uint8_t x = 0; x < dev->crtc[1]; x++) {
if (dev->ctrl & 8) {
chr = dev->vram[(dev->ma << 1) & 0x3fff];
attr = dev->vram[((dev->ma << 1) + 1) & 0x3fff];
} else
chr = attr = 0;
drawcursor = ((dev->ma == ca) && dev->con && dev->cursoron);
switch (dev->crtc[HERCULESPLUS_CRTC_XMODE] & 5) {
case 0:
case 4: /* ROM font */
draw_char_rom(dev, x, chr, attr);
break;
case 1: /* 4k RAMfont */
draw_char_ram4(dev, x, chr, attr);
break;
case 5: /* 48k RAMfont */
draw_char_ram48(dev, x, chr, attr);
break;
default:
break;
}
++dev->ma;
if (drawcursor) {
int cw = HERCULESPLUS_CW;
col = dev->cols[attr][0][1];
for (int c = 0; c < cw; c++)
buffer32->line[dev->displine][x * cw + c] = col;
}
}
}
static void
graphics_line(herculesplus_t *dev)
{
uint16_t ca;
int c;
int plane = 0;
uint16_t val;
/* Graphics mode. */
ca = (dev->sc & 3) * 0x2000;
if ((dev->ctrl & HERCULESPLUS_CTRL_PAGE1) && (dev->ctrl2 & HERCULESPLUS_CTRL2_PAGE1))
ca += 0x8000;
for (uint8_t x = 0; x < dev->crtc[1]; x++) {
if (dev->ctrl & 8)
val = (dev->vram[((dev->ma << 1) & 0x1fff) + ca + 0x10000 * plane] << 8)
| dev->vram[((dev->ma << 1) & 0x1fff) + ca + 0x10000 * plane + 1];
else
val = 0;
dev->ma++;
for (c = 0; c < 16; c++) {
buffer32->line[dev->displine][(x << 4) + c] = (val & 0x8000) ? 7 : 0;
val <<= 1;
}
for (c = 0; c < 16; c += 8)
video_blend((x << 4) + c, dev->displine);
}
}
static void
herculesplus_poll(void *priv)
{
herculesplus_t *dev = (herculesplus_t *) priv;
uint16_t ca = (dev->crtc[15] | (dev->crtc[14] << 8)) & 0x3fff;
int x;
int oldvc;
int oldsc;
int cw = HERCULESPLUS_CW;
VIDEO_MONITOR_PROLOGUE();
if (!dev->linepos) {
timer_advance_u64(&dev->timer, dev->dispofftime);
dev->stat |= 1;
dev->linepos = 1;
oldsc = dev->sc;
if ((dev->crtc[8] & 3) == 3)
dev->sc = (dev->sc << 1) & 7;
if (dev->dispon) {
if (dev->displine < dev->firstline) {
dev->firstline = dev->displine;
video_wait_for_buffer();
}
dev->lastline = dev->displine;
if ((dev->ctrl & HERCULESPLUS_CTRL_GRAPH) && (dev->ctrl2 & HERCULESPLUS_CTRL2_GRAPH))
graphics_line(dev);
else
text_line(dev, ca);
if ((dev->ctrl & HERCULESPLUS_CTRL_GRAPH) && (dev->ctrl2 & HERCULESPLUS_CTRL2_GRAPH))
x = dev->crtc[1] << 4;
else
x = dev->crtc[1] * cw;
video_process_8(x, dev->displine);
}
dev->sc = oldsc;
if (dev->vc == dev->crtc[7] && !dev->sc)
dev->stat |= 8;
dev->displine++;
if (dev->displine >= 500)
dev->displine = 0;
} else {
timer_advance_u64(&dev->timer, dev->dispontime);
if (dev->dispon)
dev->stat &= ~1;
dev->linepos = 0;
if (dev->vsynctime) {
dev->vsynctime--;
if (!dev->vsynctime)
dev->stat &= ~8;
}
if (dev->sc == (dev->crtc[11] & 31) || ((dev->crtc[8] & 3) == 3 && dev->sc == ((dev->crtc[11] & 31) >> 1))) {
dev->con = 0;
dev->coff = 1;
}
if (dev->vadj) {
dev->sc++;
dev->sc &= 31;
dev->ma = dev->maback;
dev->vadj--;
if (!dev->vadj) {
dev->dispon = 1;
dev->ma = dev->maback = (dev->crtc[13] | (dev->crtc[12] << 8)) & 0x3fff;
dev->sc = 0;
}
} else if (dev->sc == dev->crtc[9] || ((dev->crtc[8] & 3) == 3 && dev->sc == (dev->crtc[9] >> 1))) {
dev->maback = dev->ma;
dev->sc = 0;
oldvc = dev->vc;
dev->vc++;
dev->vc &= 127;
if (dev->vc == dev->crtc[6])
dev->dispon = 0;
if (oldvc == dev->crtc[4]) {
dev->vc = 0;
dev->vadj = dev->crtc[5];
if (!dev->vadj)
dev->dispon = 1;
if (!dev->vadj)
dev->ma = dev->maback = (dev->crtc[13] | (dev->crtc[12] << 8)) & 0x3fff;
if ((dev->crtc[10] & 0x60) == 0x20)
dev->cursoron = 0;
else
dev->cursoron = dev->blink & 16;
}
if (dev->vc == dev->crtc[7]) {
dev->dispon = 0;
dev->displine = 0;
dev->vsynctime = 16;
if (dev->crtc[7]) {
if ((dev->ctrl & HERCULESPLUS_CTRL_GRAPH) && (dev->ctrl2 & HERCULESPLUS_CTRL2_GRAPH))
x = dev->crtc[1] << 4;
else
x = dev->crtc[1] * cw;
dev->lastline++;
if ((dev->ctrl & 8) && ((x != xsize) || ((dev->lastline - dev->firstline) != ysize) || video_force_resize_get())) {
xsize = x;
ysize = dev->lastline - dev->firstline;
if (xsize < 64)
xsize = 656;
if (ysize < 32)
ysize = 200;
set_screen_size(xsize, ysize);
if (video_force_resize_get())
video_force_resize_set(0);
}
video_blit_memtoscreen(0, dev->firstline, xsize, dev->lastline - dev->firstline);
frames++;
if ((dev->ctrl & HERCULESPLUS_CTRL_GRAPH) && (dev->ctrl2 & HERCULESPLUS_CTRL2_GRAPH)) {
video_res_x = dev->crtc[1] * 16;
video_res_y = dev->crtc[6] * 4;
video_bpp = 1;
} else {
video_res_x = dev->crtc[1];
video_res_y = dev->crtc[6];
video_bpp = 0;
}
}
dev->firstline = 1000;
dev->lastline = 0;
dev->blink++;
}
} else {
dev->sc++;
dev->sc &= 31;
dev->ma = dev->maback;
}
if (dev->sc == (dev->crtc[10] & 31) || ((dev->crtc[8] & 3) == 3 && dev->sc == ((dev->crtc[10] & 31) >> 1)))
dev->con = 1;
}
VIDEO_MONITOR_EPILOGUE();
}
static void *
herculesplus_init(UNUSED(const device_t *info))
{
herculesplus_t *dev;
dev = (herculesplus_t *) malloc(sizeof(herculesplus_t));
memset(dev, 0, sizeof(herculesplus_t));
dev->vram = (uint8_t *) malloc(0x10000); /* 64k VRAM */
dev->monitor_index = monitor_index_global;
timer_add(&dev->timer, herculesplus_poll, dev, 1);
mem_mapping_add(&dev->mapping, 0xb0000, 0x08000,
herculesplus_read, NULL, NULL,
herculesplus_write, NULL, NULL,
dev->vram, MEM_MAPPING_EXTERNAL, dev);
io_sethandler(0x03b0, 16,
herculesplus_in, NULL, NULL, herculesplus_out, NULL, NULL, dev);
for (uint16_t c = 0; c < 256; c++) {
dev->cols[c][0][0] = dev->cols[c][1][0] = dev->cols[c][1][1] = 16;
if (c & 8)
dev->cols[c][0][1] = 15 + 16;
else
dev->cols[c][0][1] = 7 + 16;
}
dev->cols[0x70][0][1] = 16;
dev->cols[0x70][0][0] = dev->cols[0x70][1][0] = dev->cols[0x70][1][1] = 16 + 15;
dev->cols[0xF0][0][1] = 16;
dev->cols[0xF0][0][0] = dev->cols[0xF0][1][0] = dev->cols[0xF0][1][1] = 16 + 15;
dev->cols[0x78][0][1] = 16 + 7;
dev->cols[0x78][0][0] = dev->cols[0x78][1][0] = dev->cols[0x78][1][1] = 16 + 15;
dev->cols[0xF8][0][1] = 16 + 7;
dev->cols[0xF8][0][0] = dev->cols[0xF8][1][0] = dev->cols[0xF8][1][1] = 16 + 15;
dev->cols[0x00][0][1] = dev->cols[0x00][1][1] = 16;
dev->cols[0x08][0][1] = dev->cols[0x08][1][1] = 16;
dev->cols[0x80][0][1] = dev->cols[0x80][1][1] = 16;
dev->cols[0x88][0][1] = dev->cols[0x88][1][1] = 16;
herc_blend = device_get_config_int("blend");
cga_palette = device_get_config_int("rgb_type") << 1;
if (cga_palette > 6)
cga_palette = 0;
cgapal_rebuild();
video_inform(VIDEO_FLAG_TYPE_MDA, &timing_herculesplus);
/* Force the LPT3 port to be enabled. */
lpt3_init(0x3BC);
return dev;
}
static void
herculesplus_close(void *priv)
{
herculesplus_t *dev = (herculesplus_t *) priv;
if (!dev)
return;
if (dev->vram)
free(dev->vram);
free(dev);
}
static void
speed_changed(void *priv)
{
herculesplus_t *dev = (herculesplus_t *) priv;
recalc_timings(dev);
}
static const device_config_t herculesplus_config[] = {
// clang-format off
{
.name = "rgb_type",
.description = "Display type",
.type = CONFIG_SELECTION,
.default_int = 0,
.selection = {
{
.description = "Default",
.value = 0
},
{
.description = "Green",
.value = 1
},
{
.description = "Amber",
.value = 2
},
{
.description = "Gray",
.value = 3
},
{
.description = ""
}
}
},
{
.name = "blend",
.description = "Blend",
.type = CONFIG_BINARY,
.default_int = 1
},
{
.type = CONFIG_END
}
// clang-format on
};
const device_t herculesplus_device = {
.name = "Hercules Plus",
.internal_name = "hercules_plus",
.flags = DEVICE_ISA,
.local = 0,
.init = herculesplus_init,
.close = herculesplus_close,
.reset = NULL,
{ .available = NULL },
.speed_changed = speed_changed,
.force_redraw = NULL,
.config = herculesplus_config
};
``` | /content/code_sandbox/src/video/vid_herculesplus.c | c | 2016-06-25T22:29:10 | 2024-08-16T19:09:21 | 86Box | 86Box/86Box | 2,616 | 6,676 |
```c
/*
* 86Box A hypervisor and IBM PC system emulator that specializes in
* running old operating systems and software designed for IBM
* PC systems and compatibles from 1981 through fairly recent
* system designs based on the PCI bus.
*
* This file is part of the 86Box distribution.
*
* AV9194 clock generator emulation.
*
* Used by the S3 86c801 (V7-Mirage) card.
*
*
*
* Authors: Miran Grca, <mgrca8@gmail.com>
*
*/
#include <stdio.h>
#include <stdint.h>
#include <stdlib.h>
#include <string.h>
#include <wchar.h>
#include <86box/86box.h>
#include <86box/device.h>
#include <86box/mem.h>
#include <86box/timer.h>
#include <86box/video.h>
#include <86box/vid_svga.h>
#include <86box/plat_unused.h>
float
av9194_getclock(int clock, UNUSED(void *priv))
{
float ret = 0.0;
switch (clock & 0x0f) {
case 0:
ret = 25175000.0;
break;
case 1:
ret = 28322000.0;
break;
case 2:
ret = 40000000.0;
break;
case 4:
ret = 50000000.0;
break;
case 5:
ret = 77000000.0;
break;
case 6:
ret = 36000000.0;
break;
case 7:
ret = 44900000.0;
break;
case 8:
ret = 130000000.0;
break;
case 9:
ret = 120000000.0;
break;
case 0xa:
ret = 80000000.0;
break;
case 0xb:
ret = 31500000.0;
break;
case 0xc:
ret = 110000000.0;
break;
case 0xd:
ret = 65000000.0;
break;
case 0xe:
ret = 75000000.0;
break;
case 0xf:
ret = 94500000.0;
break;
default:
break;
}
return ret;
}
static void *
av9194_init(UNUSED(const device_t *info))
{
/* Return something non-NULL. */
return (void *) &av9194_device;
}
const device_t av9194_device = {
.name = "AV9194 Clock Generator",
.internal_name = "av9194",
.flags = 0,
.local = 0,
.init = av9194_init,
.close = NULL,
.reset = NULL,
{ .available = NULL },
.speed_changed = NULL,
.force_redraw = NULL,
.config = NULL
};
``` | /content/code_sandbox/src/video/vid_av9194.c | c | 2016-06-25T22:29:10 | 2024-08-16T19:09:21 | 86Box | 86Box/86Box | 2,616 | 669 |
```c
/*
* 86Box A hypervisor and IBM PC system emulator that specializes in
* running old operating systems and software designed for IBM
* PC systems and compatibles from 1981 through fairly recent
* system designs based on the PCI bus.
*
* This file is part of the 86Box distribution.
*
* IBM XGA emulation.
*
*
*
* Authors: TheCollector1995.
*
*/
#include <stdio.h>
#include <stdint.h>
#include <string.h>
#include <stdlib.h>
#include <wchar.h>
#include <86box/bswap.h>
#include <86box/86box.h>
#include <86box/io.h>
#include <86box/machine.h>
#include <86box/mem.h>
#include <86box/dma.h>
#include <86box/rom.h>
#include <86box/mca.h>
#include <86box/device.h>
#include <86box/timer.h>
#include <86box/video.h>
#include <86box/vid_xga.h>
#include <86box/vid_svga.h>
#include <86box/vid_svga_render.h>
#include <86box/vid_xga_device.h>
#include "cpu.h"
#include <86box/plat_unused.h>
#define XGA_BIOS_PATH "roms/video/xga/XGA_37F9576_Ver200.BIN"
#define XGA2_BIOS_PATH "roms/video/xga/xga2_v300.bin"
#define INMOS_XGA_BIOS_PATH "roms/video/xga/InMOS XGA - Fairchild NM27C256Q-150.BIN"
static video_timings_t timing_xga_isa = { .type = VIDEO_ISA, .write_b = 3, .write_w = 3, .write_l = 6, .read_b = 5, .read_w = 5, .read_l = 10 };
static video_timings_t timing_xga_mca = { .type = VIDEO_MCA, .write_b = 4, .write_w = 5, .write_l = 10, .read_b = 5, .read_w = 5, .read_l = 10 };
static void xga_ext_outb(uint16_t addr, uint8_t val, void *priv);
static uint8_t xga_ext_inb(uint16_t addr, void *priv);
static void xga_writew(uint32_t addr, uint16_t val, void *priv);
static uint16_t xga_readw(uint32_t addr, void *priv);
static void xga_render_4bpp(svga_t *svga);
static void xga_render_8bpp(svga_t *svga);
static void xga_render_16bpp(svga_t *svga);
int xga_active = 0;
#ifdef ENABLE_XGA_LOG
int xga_do_log = ENABLE_XGA_LOG;
static void
xga_log(const char *fmt, ...)
{
va_list ap;
if (xga_do_log) {
va_start(ap, fmt);
pclog_ex(fmt, ap);
va_end(ap);
}
}
#else
# define xga_log(fmt, ...)
#endif
void
svga_xga_out(uint16_t addr, uint8_t val, void *priv)
{
svga_t *svga = (svga_t *) priv;
uint8_t old;
if (((addr & 0xfff0) == 0x3d0 || (addr & 0xfff0) == 0x3b0) && !(svga->miscout & 1))
addr ^= 0x60;
switch (addr) {
case 0x3D4:
svga->crtcreg = val & 0x3f;
return;
case 0x3D5:
if (svga->crtcreg & 0x20)
return;
if ((svga->crtcreg < 7) && (svga->crtc[0x11] & 0x80))
return;
if ((svga->crtcreg == 7) && (svga->crtc[0x11] & 0x80))
val = (svga->crtc[7] & ~0x10) | (val & 0x10);
old = svga->crtc[svga->crtcreg];
svga->crtc[svga->crtcreg] = val;
if (old != val) {
if (svga->crtcreg < 0xe || svga->crtcreg > 0x10) {
if ((svga->crtcreg == 0xc) || (svga->crtcreg == 0xd)) {
svga->fullchange = 3;
svga->ma_latch = ((svga->crtc[0xc] << 8) | svga->crtc[0xd]) + ((svga->crtc[8] & 0x60) >> 5);
} else {
svga->fullchange = changeframecount;
svga_recalctimings(svga);
}
}
}
break;
default:
break;
}
svga_out(addr, val, svga);
}
uint8_t
svga_xga_in(uint16_t addr, void *priv)
{
svga_t *svga = (svga_t *) priv;
uint8_t temp;
if (((addr & 0xfff0) == 0x3d0 || (addr & 0xfff0) == 0x3b0) && !(svga->miscout & 1))
addr ^= 0x60;
switch (addr) {
case 0x3D4:
temp = svga->crtcreg;
break;
case 0x3D5:
if (svga->crtcreg & 0x20)
temp = 0xff;
else
temp = svga->crtc[svga->crtcreg];
break;
default:
temp = svga_in(addr, svga);
break;
}
return temp;
}
void
xga_updatemapping(svga_t *svga)
{
xga_t *xga = (xga_t *) svga->xga;
xga_log("OpMode = %x, linear base = %08x, aperture cntl = %d, access mode = %x, map = %x, "
"endian reverse = %d, a5test = %d, XGA on = %d.\n", xga->op_mode, xga->linear_base,
xga->aperture_cntl, xga->access_mode, svga->gdcreg[6] & 0x0c,
xga->linear_endian_reverse, xga->a5_test, xga->on);
switch (xga->op_mode & 7) {
case 0:
xga_log("XGA: VGA mode address decode disabled.\n");
break;
case 1:
xga_log("XGA: VGA mode address decode enabled.\n");
break;
case 2:
xga_log("XGA: 132-Column mode address decode disabled.\n");
break;
case 3:
xga_log("XGA: 132-Column mode address decode enabled.\n");
break;
default:
xga_log("XGA: Extended Graphics mode.\n");
switch (xga->aperture_cntl) {
case 0:
xga_log("XGA: No 64KB aperture.\n");
if (xga->base_addr_1mb)
mem_mapping_set_addr(&xga->linear_mapping, xga->base_addr_1mb, 0x100000);
else if (xga->linear_base)
mem_mapping_set_addr(&xga->linear_mapping, xga->linear_base, 0x400000);
else
mem_mapping_disable(&xga->linear_mapping);
mem_mapping_disable(&xga->video_mapping);
break;
case 1:
xga_log("XGA: 64KB aperture at A0000.\n");
mem_mapping_set_addr(&xga->video_mapping, 0xa0000, 0x10000);
mem_mapping_enable(&xga->video_mapping);
xga->banked_mask = 0xffff;
break;
case 2:
xga_log("XGA: 64KB aperture at B0000.\n");
mem_mapping_set_addr(&xga->video_mapping, 0xb0000, 0x10000);
mem_mapping_enable(&xga->video_mapping);
xga->banked_mask = 0xffff;
break;
default:
break;
}
break;
}
}
void
xga_recalctimings(svga_t *svga)
{
xga_t *xga = (xga_t *) svga->xga;
if (xga->on) {
xga->v_total = xga->vtotal + 1;
xga->dispend = xga->vdispend + 1;
xga->v_syncstart = xga->vsyncstart + 1;
xga->split = xga->linecmp + 1;
xga->v_blankstart = xga->vblankstart + 1;
xga->h_disp = (xga->hdisp + 1) << 3;
xga->rowoffset = xga->hdisp + 1;
xga->interlace = !!(xga->disp_cntl_1 & 0x08);
xga->rowcount = (xga->disp_cntl_2 & 0xc0) >> 6;
if (xga->interlace) {
xga->v_total >>= 1;
xga->dispend >>= 1;
xga->v_syncstart >>= 1;
xga->split >>= 1;
xga->v_blankstart >>= 1;
}
xga->ma_latch = xga->disp_start_addr;
if ((xga->disp_cntl_2 & 7) == 2)
xga->rowoffset >>= 1;
else if ((xga->disp_cntl_2 & 7) == 4)
xga->rowoffset <<= 1;
xga_log("XGA ClkSel1 = %d, ClkSel2 = %02x.\n", (xga->clk_sel_1 >> 2) & 3, xga->clk_sel_2 & 0x80);
switch ((xga->clk_sel_1 >> 2) & 3) {
case 0:
xga_log("HDISP VGA0 = %d, XGA = %d.\n", svga->hdisp, xga->h_disp);
if (xga->clk_sel_2 & 0x80)
svga->clock = (cpuclock * (double) (1ULL << 32)) / 41539000.0;
else
svga->clock = (cpuclock * (double) (1ULL << 32)) / 25175000.0;
break;
case 1:
xga_log("HDISP VGA1 = %d, XGA = %d.\n", svga->hdisp, xga->h_disp);
svga->clock = (cpuclock * (double) (1ULL << 32)) / 28322000.0;
break;
case 3:
svga->clock = (cpuclock * (double) (1ULL << 32)) / 44900000.0;
break;
default:
break;
}
}
}
static void
xga_ext_out_reg(xga_t *xga, svga_t *svga, uint8_t idx, uint8_t val)
{
uint8_t index;
switch (idx) {
case 0x10:
xga->htotal = (xga->htotal & 0xff00) | val;
break;
case 0x11:
xga->htotal = (xga->htotal & 0xff) | (val << 8);
svga_recalctimings(svga);
break;
case 0x12:
xga->hdisp = (xga->hdisp & 0xff00) | val;
break;
case 0x13:
xga->hdisp = (xga->hdisp & 0xff) | (val << 8);
svga_recalctimings(svga);
break;
case 0x20:
xga->vtotal = (xga->vtotal & 0xff00) | val;
break;
case 0x21:
xga->vtotal = (xga->vtotal & 0xff) | (val << 8);
svga_recalctimings(svga);
break;
case 0x22:
xga->vdispend = (xga->vdispend & 0xff00) | val;
break;
case 0x23:
xga->vdispend = (xga->vdispend & 0xff) | (val << 8);
svga_recalctimings(svga);
break;
case 0x24:
xga->vblankstart = (xga->vblankstart & 0xff00) | val;
break;
case 0x25:
xga->vblankstart = (xga->vblankstart & 0xff) | (val << 8);
svga_recalctimings(svga);
break;
case 0x28:
xga->vsyncstart = (xga->vsyncstart & 0xff00) | val;
break;
case 0x29:
xga->vsyncstart = (xga->vsyncstart & 0xff) | (val << 8);
svga_recalctimings(svga);
break;
case 0x2c:
xga->linecmp = (xga->linecmp & 0xff00) | val;
break;
case 0x2d:
xga->linecmp = (xga->linecmp & 0xff) | (val << 8);
svga_recalctimings(svga);
break;
case 0x30:
xga->hwc_pos_x = (xga->hwc_pos_x & 0x0700) | val;
xga->hwcursor.x = xga->hwc_pos_x;
break;
case 0x31:
xga->hwc_pos_x = (xga->hwc_pos_x & 0xff) | ((val & 0x07) << 8);
xga->hwcursor.x = xga->hwc_pos_x;
break;
case 0x32:
xga->hwc_hotspot_x = val & 0x3f;
xga->hwcursor.xoff = val & 0x3f;
break;
case 0x33:
xga->hwc_pos_y = (xga->hwc_pos_y & 0x0700) | val;
xga->hwcursor.y = xga->hwc_pos_y;
break;
case 0x34:
xga->hwc_pos_y = (xga->hwc_pos_y & 0xff) | ((val & 0x07) << 8);
xga->hwcursor.y = xga->hwc_pos_y;
break;
case 0x35:
xga->hwc_hotspot_y = val & 0x3f;
xga->hwcursor.yoff = val & 0x3f;
break;
case 0x36:
xga->hwc_control = val;
xga->hwcursor.ena = xga->hwc_control & 1;
break;
case 0x38:
xga->hwc_color0 = (xga->hwc_color0 & 0xffff00) | val;
break;
case 0x39:
xga->hwc_color0 = (xga->hwc_color0 & 0xff00ff) | (val << 8);
break;
case 0x3a:
xga->hwc_color0 = (xga->hwc_color0 & 0x00ffff) | (val << 16);
break;
case 0x3b:
xga->hwc_color1 = (xga->hwc_color1 & 0xffff00) | val;
break;
case 0x3c:
xga->hwc_color1 = (xga->hwc_color1 & 0xff00ff) | (val << 8);
break;
case 0x3d:
xga->hwc_color1 = (xga->hwc_color1 & 0x00ffff) | (val << 16);
break;
case 0x40:
xga->disp_start_addr = (xga->disp_start_addr & 0x7ff00) | val;
break;
case 0x41:
xga->disp_start_addr = (xga->disp_start_addr & 0x700ff) | (val << 8);
break;
case 0x42:
xga->disp_start_addr = (xga->disp_start_addr & 0x0ffff) | ((val & 0x07) << 16);
svga_recalctimings(svga);
break;
case 0x43:
xga->pix_map_width = (xga->pix_map_width & 0x700) | val;
break;
case 0x44:
xga->pix_map_width = (xga->pix_map_width & 0xff) | ((val & 0x07) << 8);
break;
case 0x50:
xga_log("Reg50 write = %02x.\n", val);
xga->disp_cntl_1 = val;
svga_recalctimings(svga);
break;
case 0x51:
xga_log("Reg51 write = %02x.\n", val);
xga->disp_cntl_2 = val;
xga->on = ((val & 7) >= 2);
vga_on = !xga->on;
svga_recalctimings(svga);
break;
case 0x54:
xga_log("Reg54 write = %02x.\n", val);
xga->clk_sel_1 = val;
svga_recalctimings(svga);
break;
case 0x55:
xga->border_color = val;
break;
case 0x59:
xga->direct_color = val;
break;
case 0x60:
xga->sprite_pal_addr_idx = (xga->sprite_pal_addr_idx & 0x3f00) | val;
svga->dac_pos = 0;
svga->dac_addr = val & 0xff;
break;
case 0x61:
xga->sprite_pal_addr_idx = (xga->sprite_pal_addr_idx & 0xff) | ((val & 0x3f) << 8);
xga->sprite_pos = xga->sprite_pal_addr_idx & 0x1ff;
xga_log("Sprite POS = %d, data on = %d, idx = %d, apcntl = %d\n", xga->sprite_pos,
xga->cursor_data_on, xga->sprite_pal_addr_idx, xga->aperture_cntl);
break;
case 0x62:
xga->sprite_pal_addr_idx_prefetch = (xga->sprite_pal_addr_idx_prefetch & 0x3f00) | val;
svga->dac_pos = 0;
svga->dac_addr = val & 0xff;
break;
case 0x63:
xga->sprite_pal_addr_idx_prefetch = (xga->sprite_pal_addr_idx_prefetch & 0xff) | ((val & 0x3f) << 8);
xga->sprite_pos_prefetch = xga->sprite_pal_addr_idx_prefetch & 0x1ff;
break;
case 0x64:
svga->dac_mask = val;
break;
case 0x65:
svga->fullchange = svga->monitor->mon_changeframecount;
switch (svga->dac_pos) {
case 0:
svga->dac_r = val;
svga->dac_pos++;
break;
case 1:
svga->dac_g = val;
svga->dac_pos++;
break;
case 2:
xga->pal_b = val;
index = svga->dac_addr & 0xff;
svga->vgapal[index].r = svga->dac_r;
svga->vgapal[index].g = svga->dac_g;
svga->vgapal[index].b = xga->pal_b;
xga->pallook[index] = makecol32(svga->vgapal[index].r, svga->vgapal[index].g, svga->vgapal[index].b);
svga->dac_pos = 0;
svga->dac_addr = (svga->dac_addr + 1) & 0xff;
break;
default:
break;
}
break;
case 0x66:
xga->pal_seq = val;
break;
case 0x67:
svga->dac_r = val;
break;
case 0x68:
xga->pal_b = val;
break;
case 0x69:
svga->dac_g = val;
break;
case 0x6a:
xga->sprite_data[xga->sprite_pos] = val;
xga->sprite_pos = (xga->sprite_pos + 1) & 0x3ff;
break;
case 0x70:
xga_log("Reg70 write = %02x.\n", val);
xga->clk_sel_2 = val;
svga_recalctimings(svga);
break;
default:
break;
}
}
static void
xga_ext_outb(uint16_t addr, uint8_t val, void *priv)
{
svga_t *svga = (svga_t *) priv;
xga_t *xga = (xga_t *) svga->xga;
xga_log("[%04X:%08X]: EXT OUTB = %02x, val = %02x\n", CS, cpu_state.pc, addr, val);
switch (addr & 0x0f) {
case 0:
xga->op_mode = val;
break;
case 1:
xga->aperture_cntl = val & 3;
xga_updatemapping(svga);
break;
case 4:
if ((xga->disp_cntl_2 & 7) == 4)
xga->aperture_cntl = 0;
break;
case 8:
xga->ap_idx = val;
xga_log("Aperture CNTL = %d, val = %02x, up to bit6 = %02x\n", xga->aperture_cntl,
val, val & 0x3f);
if ((xga->op_mode & 7) < 4) {
xga->write_bank = xga->read_bank = 0;
} else {
if (xga->base_addr_1mb) {
if (xga->aperture_cntl) {
xga->write_bank = (xga->ap_idx & 0x3f) << 16;
xga->read_bank = xga->write_bank;
} else {
xga->write_bank = (xga->ap_idx & 0x30) << 16;
xga->read_bank = xga->write_bank;
}
} else {
xga->write_bank = (xga->ap_idx & 0x3f) << 16;
xga->read_bank = xga->write_bank;
}
}
break;
case 9:
xga->access_mode = val;
break;
case 0x0a:
xga->regs_idx = val;
break;
case 0x0b:
case 0x0c:
case 0x0d:
case 0x0e:
case 0x0f:
xga->regs[xga->regs_idx] = val;
xga_log("EXT OUT Reg=%02x, val=%02x.\n", xga->regs_idx, val);
xga_ext_out_reg(xga, svga, xga->regs_idx, xga->regs[xga->regs_idx]);
break;
default:
break;
}
}
static uint8_t
xga_ext_inb(uint16_t addr, void *priv)
{
svga_t *svga = (svga_t *) priv;
xga_t *xga = (xga_t *) svga->xga;
uint8_t ret = 0;
uint8_t index;
switch (addr & 0x0f) {
case 0:
ret = xga->op_mode;
break;
case 1:
ret = xga->aperture_cntl;
break;
case 8:
ret = xga->ap_idx;
break;
case 9:
ret = xga->access_mode;
break;
case 0x0a:
ret = xga->regs_idx;
break;
case 0x0b:
case 0x0c:
case 0x0d:
case 0x0e:
case 0x0f:
switch (xga->regs_idx) {
case 4:
if (xga->bus & DEVICE_MCA)
ret = 0x01; /*32-bit MCA*/
else
ret = 0x10; /*16-bit ISA*/
break;
case 0x10:
ret = xga->htotal & 0xff;
break;
case 0x11:
ret = xga->htotal >> 8;
break;
case 0x12:
ret = xga->hdisp & 0xff;
break;
case 0x13:
ret = xga->hdisp >> 8;
break;
case 0x20:
ret = xga->vtotal & 0xff;
break;
case 0x21:
ret = xga->vtotal >> 8;
break;
case 0x22:
ret = xga->vdispend & 0xff;
break;
case 0x23:
ret = xga->vdispend >> 8;
break;
case 0x24:
ret = xga->vblankstart & 0xff;
break;
case 0x25:
ret = xga->vblankstart >> 8;
break;
case 0x28:
ret = xga->vsyncstart & 0xff;
break;
case 0x29:
ret = xga->vsyncstart >> 8;
break;
case 0x2c:
ret = xga->linecmp & 0xff;
break;
case 0x2d:
ret = xga->linecmp >> 8;
break;
case 0x30:
ret = xga->hwc_pos_x & 0xff;
break;
case 0x31:
ret = xga->hwc_pos_x >> 8;
break;
case 0x32:
ret = xga->hwc_hotspot_x;
break;
case 0x33:
ret = xga->hwc_pos_y & 0xff;
break;
case 0x34:
ret = xga->hwc_pos_y >> 8;
break;
case 0x35:
ret = xga->hwc_hotspot_y;
break;
case 0x36:
ret = xga->hwc_control;
break;
case 0x38:
ret = xga->hwc_color0 & 0xff;
break;
case 0x39:
ret = xga->hwc_color0 >> 8;
break;
case 0x3a:
ret = xga->hwc_color0 >> 16;
break;
case 0x3b:
ret = xga->hwc_color1 & 0xff;
break;
case 0x3c:
ret = xga->hwc_color1 >> 8;
break;
case 0x3d:
ret = xga->hwc_color1 >> 16;
break;
case 0x40:
ret = xga->disp_start_addr & 0xff;
break;
case 0x41:
ret = xga->disp_start_addr >> 8;
break;
case 0x42:
ret = xga->disp_start_addr >> 16;
break;
case 0x43:
ret = xga->pix_map_width & 0xff;
break;
case 0x44:
ret = xga->pix_map_width >> 8;
break;
case 0x50:
ret = xga->disp_cntl_1 | 0x20;
break;
case 0x51:
ret = xga->disp_cntl_2;
break;
case 0x52:
ret = xga->type ? 0xfa : 0xea;
break;
case 0x53:
ret = xga->type ? 0x53 : 0x30;
break;
case 0x54:
ret = xga->clk_sel_1;
break;
case 0x55:
ret = xga->border_color;
break;
case 0x59:
ret = xga->direct_color;
break;
case 0x60:
ret = xga->sprite_pal_addr_idx & 0xff;
break;
case 0x61:
ret = xga->sprite_pal_addr_idx >> 8;
break;
case 0x62:
ret = xga->sprite_pal_addr_idx_prefetch & 0xff;
break;
case 0x63:
ret = xga->sprite_pal_addr_idx_prefetch >> 8;
break;
case 0x64:
ret = svga->dac_mask;
break;
case 0x65:
index = svga->dac_addr & 0xff;
switch (svga->dac_pos) {
case 0:
svga->dac_pos++;
ret = svga->vgapal[index].r;
break;
case 1:
svga->dac_pos++;
ret = svga->vgapal[index].g;
break;
case 2:
svga->dac_pos = 0;
svga->dac_addr = (svga->dac_addr + 1) & 0xff;
ret = svga->vgapal[index].b;
break;
default:
break;
}
break;
case 0x66:
ret = xga->pal_seq;
break;
case 0x67:
ret = svga->dac_r;
break;
case 0x68:
ret = xga->pal_b;
break;
case 0x69:
ret = svga->dac_g;
break;
case 0x6a:
xga_log("Sprite POS Read = %d, addr idx = %04x\n", xga->sprite_pos,
xga->sprite_pal_addr_idx_prefetch);
ret = xga->sprite_data[xga->sprite_pos_prefetch];
xga->sprite_pos_prefetch = (xga->sprite_pos_prefetch + 1) & 0x3ff;
break;
case 0x70:
ret = xga->clk_sel_2;
break;
case 0x74:
if (xga->bus & DEVICE_MCA)
ret = xga->regs[xga->regs_idx];
else {
ret = (xga->dma_channel << 1);
if (xga->dma_channel)
ret |= 1;
}
break;
default:
ret = xga->regs[xga->regs_idx];
if ((xga->regs_idx == 0x0c) || (xga->regs_idx == 0x0d))
xga_log("EXT IN Reg=%02x, val=%02x.\n", xga->regs_idx, ret);
break;
}
break;
default:
break;
}
xga_log("[%04X:%08X]: EXT INB = %02x, ret = %02x.\n\n", CS, cpu_state.pc, addr, ret);
return ret;
}
#define READ(addr, dat) \
dat = xga->vram[(addr) & (xga->vram_mask)];
#define WRITE(addr, dat) \
xga->vram[((addr)) & (xga->vram_mask)] = dat; \
xga->changedvram[(((addr)) & (xga->vram_mask)) >> 12] = svga->monitor->mon_changeframecount;
#define READW(addr, dat) \
dat = *(uint16_t *) &xga->vram[(addr) & (xga->vram_mask)];
#define READW_INV(addr, dat) \
dat = xga->vram[(addr + 1) & (xga->vram_mask)]; \
dat |= (xga->vram[(addr) & (xga->vram_mask)] << 8);
#define WRITEW(addr, dat) \
*(uint16_t *) &xga->vram[((addr)) & (xga->vram_mask)] = dat; \
xga->changedvram[(((addr)) & (xga->vram_mask)) >> 12] = svga->monitor->mon_changeframecount;
#define WRITEW_INV(addr, dat) \
xga->vram[((addr + 1)) & (xga->vram_mask)] = dat & 0xff; \
xga->vram[((addr)) & (xga->vram_mask)] = dat >> 8; \
xga->changedvram[(((addr)) & (xga->vram_mask)) >> 12] = svga->monitor->mon_changeframecount;
#define ROP(mix, d, s) \
{ \
switch ((mix) ? (xga->accel.frgd_mix & 0x1f) : (xga->accel.bkgd_mix & 0x1f)) { \
case 0x00: \
d = 0; \
break; \
case 0x01: \
d = s & d; \
break; \
case 0x02: \
d = s & ~d; \
break; \
case 0x03: \
d = s; \
break; \
case 0x04: \
d = ~s & d; \
break; \
case 0x05: \
d = d; \
break; \
case 0x06: \
d = s ^ d; \
break; \
case 0x07: \
d = s | d; \
break; \
case 0x08: \
d = ~s & ~d; \
break; \
case 0x09: \
d = s ^ ~d; \
break; \
case 0x0a: \
d = ~d; \
break; \
case 0x0b: \
d = s | ~d; \
break; \
case 0x0c: \
d = ~s; \
break; \
case 0x0d: \
d = ~s | d; \
break; \
case 0x0e: \
d = ~s | ~d; \
break; \
case 0x0f: \
d = ~0; \
break; \
case 0x10: \
d = MAX(s, d); \
break; \
case 0x11: \
d = MIN(s, d); \
break; \
case 0x12: \
d = MIN(~0, s + d); \
break; \
case 0x13: \
d = MAX(0, d - s); \
break; \
case 0x14: \
d = MAX(0, s - d); \
break; \
case 0x15: \
d = (s + d) >> 1; \
break; \
} \
}
static uint32_t
xga_accel_read_pattern_map_pixel(svga_t *svga, int x, int y, int map, uint32_t base, int width)
{
const xga_t *xga = (xga_t *) svga->xga;
uint32_t addr = base;
int bits;
uint8_t byte;
uint8_t px;
int skip = 0;
if (xga->base_addr_1mb) {
if (addr < xga->base_addr_1mb || (addr > (xga->base_addr_1mb + 0xfffff)))
skip = 1;
} else {
if (addr < xga->linear_base || (addr > (xga->linear_base + 0xfffff)))
skip = 1;
}
addr += (y * (width >> 3));
addr += (x >> 3);
if (!skip) {
READ(addr, byte);
} else
byte = mem_readb_phys(addr);
if (xga->linear_endian_reverse)
bits = 7 - (x & 7);
else {
if (xga->accel.px_map_format[xga->accel.dst_map] & 8) {
if ((xga->accel.px_map_format[xga->accel.src_map] & 8) && (xga->accel.px_map_format[map] & 8))
bits = (x & 7);
else
bits = 7 - (x & 7);
} else {
if ((xga->accel.px_map_format[map] & 8) && !(xga->access_mode & 8))
bits = (x & 7);
else
bits = 7 - (x & 7);
}
}
px = (byte >> bits) & 1;
return px;
}
static uint32_t
xga_accel_read_map_pixel(svga_t *svga, int x, int y, int map, uint32_t base, int width, UNUSED(int usesrc))
{
xga_t *xga = (xga_t *) svga->xga;
uint32_t addr = base;
int bits;
uint32_t byte;
uint8_t px;
int skip = 0;
if (xga->base_addr_1mb) {
if (addr < xga->base_addr_1mb || (addr > (xga->base_addr_1mb + 0xfffff)))
skip = 1;
} else {
if (addr < xga->linear_base || (addr > (xga->linear_base + 0xfffff)))
skip = 1;
}
switch (xga->accel.px_map_format[map] & 7) {
case 0: /*1-bit*/
addr += (y * (width >> 3));
addr += (x >> 3);
if (!skip) {
READ(addr, byte);
} else
byte = mem_readb_phys(addr);
if (xga->linear_endian_reverse)
bits = 7 - (x & 7);
else {
if ((xga->accel.px_map_format[map] & 8) && !(xga->access_mode & 8))
bits = (x & 7);
else
bits = 7 - (x & 7);
}
px = (byte >> bits) & 1;
return px;
case 2: /*4-bit*/
addr += (y * (width >> 1));
addr += (x >> 1);
if (!skip) {
READ(addr, byte);
} else
byte = mem_readb_phys(addr);
return byte;
case 3: /*8-bit*/
addr += (y * width);
addr += x;
if (!skip) {
READ(addr, byte);
} else
byte = mem_readb_phys(addr);
return byte;
case 4: /*16-bit*/
addr += (y * (width << 1));
addr += (x << 1);
if (xga->linear_endian_reverse) {
byte = mem_readw_phys(addr);
if ((xga->access_mode & 7) == 4)
byte = ((byte & 0xff00) >> 8) | ((byte & 0x00ff) << 8);
else if (xga->access_mode & 8)
byte = ((byte & 0xff00) >> 8) | ((byte & 0x00ff) << 8);
} else {
if (!skip) {
READW(addr, byte);
} else
byte = mem_readb_phys(addr) | (mem_readb_phys(addr + 1) << 8);
}
return byte;
default:
break;
}
return 0;
}
static void
xga_accel_write_map_pixel(svga_t *svga, int x, int y, int map, uint32_t base, uint32_t pixel, int width)
{
xga_t *xga = (xga_t *) svga->xga;
uint32_t addr = base;
uint8_t byte;
uint8_t mask;
int skip = 0;
if (xga->base_addr_1mb) {
if (addr < xga->base_addr_1mb || (addr > (xga->base_addr_1mb + 0xfffff)))
skip = 1;
} else {
if (addr < xga->linear_base || (addr > (xga->linear_base + 0xfffff)))
skip = 1;
}
switch (xga->accel.px_map_format[map] & 7) {
case 0: /*1-bit*/
addr += (y * (width >> 3));
addr += (x >> 3);
if (!skip) {
READ(addr, byte);
} else
byte = mem_readb_phys(addr);
if (xga->linear_endian_reverse) {
mask = 1 << (7 - (x & 7));
} else {
if ((xga->accel.px_map_format[map] & 8) && !(xga->access_mode & 8)) {
mask = 1 << (x & 7);
} else {
mask = 1 << (7 - (x & 7));
}
}
byte = (byte & ~mask) | ((pixel ? 0xff : 0) & mask);
if (pixel & 1) {
if (!skip) {
xga->vram[addr & (xga->vram_mask)] |= mask;
xga->changedvram[(addr & (xga->vram_mask)) >> 12] = svga->monitor->mon_changeframecount;
}
} else {
if (!skip) {
xga->vram[addr & (xga->vram_mask)] &= ~mask;
xga->changedvram[(addr & (xga->vram_mask)) >> 12] = svga->monitor->mon_changeframecount;
}
}
mem_writeb_phys(addr, byte);
break;
case 2: /*4-bit*/
addr += (y * (width >> 1));
addr += (x >> 1);
if (!skip) {
READ(addr, byte);
} else {
byte = mem_readb_phys(addr);
}
if (xga->linear_endian_reverse)
mask = 0x0f << ((1 - (x & 1)) << 2);
else {
if ((xga->accel.px_map_format[map] & 8) && !(xga->access_mode & 8))
mask = 0x0f << ((x & 1) << 2);
else
mask = 0x0f << ((1 - (x & 1)) << 2);
}
byte = (byte & ~mask) | (pixel & mask);
if (!skip) {
WRITE(addr, byte);
}
mem_writeb_phys(addr, byte);
break;
case 3: /*8-bit*/
addr += (y * width);
addr += x;
if (!skip) {
WRITE(addr, pixel & 0xff);
}
mem_writeb_phys(addr, pixel & 0xff);
break;
case 4: /*16-bit*/
addr += (y * width << 1);
addr += (x << 1);
if (xga->linear_endian_reverse) {
if ((xga->access_mode & 7) == 4)
pixel = ((pixel & 0xff00) >> 8) | ((pixel & 0x00ff) << 8);
else if (xga->access_mode & 8)
pixel = ((pixel & 0xff00) >> 8) | ((pixel & 0x00ff) << 8);
} else {
if (!skip) {
WRITEW(addr, pixel);
}
}
mem_writew_phys(addr, pixel);
break;
default:
break;
}
}
static void
xga_short_stroke(svga_t *svga, uint8_t ssv)
{
xga_t *xga = (xga_t *) svga->xga;
uint32_t src_dat;
uint32_t dest_dat;
uint32_t old_dest_dat;
uint32_t color_cmp = xga->accel.color_cmp;
uint32_t plane_mask = xga->accel.plane_mask;
uint32_t dstbase = xga->accel.px_map_base[xga->accel.dst_map];
uint32_t srcbase = xga->accel.px_map_base[xga->accel.src_map];
int y = ssv & 0x0f;
int x = 0;
int16_t dx;
int16_t dy;
int dirx = 0;
int diry = 0;
dx = xga->accel.dst_map_x & 0x1fff;
if (xga->accel.dst_map_x >= 0x1800)
dx |= ~0x17ff;
dy = xga->accel.dst_map_y & 0x1fff;
if (xga->accel.dst_map_y >= 0x1800)
dy |= ~0x17ff;
switch ((ssv >> 5) & 7) {
case 0:
dirx = 1;
diry = 0;
break;
case 1:
dirx = 1;
diry = -1;
break;
case 2:
dirx = 0;
diry = -1;
break;
case 3:
dirx = -1;
diry = -1;
break;
case 4:
dirx = -1;
diry = 0;
break;
case 5:
dirx = -1;
diry = 1;
break;
case 6:
dirx = 0;
diry = 1;
break;
case 7:
dirx = 1;
diry = 1;
break;
default:
break;
}
if (xga->accel.pat_src == 8) {
while (y >= 0) {
if (xga->accel.command & 0xc0) {
if ((dx >= xga->accel.mask_map_origin_x_off) && (dx <= ((xga->accel.px_map_width[0] & 0xfff) + xga->accel.mask_map_origin_x_off)) && (dy >= xga->accel.mask_map_origin_y_off) && (dy <= ((xga->accel.px_map_height[0] & 0xfff) + xga->accel.mask_map_origin_y_off))) {
src_dat = (((xga->accel.command >> 28) & 3) == 2) ? xga_accel_read_map_pixel(svga, xga->accel.src_map_x & 0xfff, xga->accel.src_map_y & 0xfff, xga->accel.src_map, srcbase, xga->accel.px_map_width[xga->accel.src_map] + 1, 1) : xga->accel.frgd_color;
dest_dat = xga_accel_read_map_pixel(svga, dx, dy, xga->accel.dst_map, dstbase, xga->accel.px_map_width[xga->accel.dst_map] + 1, 0);
if ((xga->accel.cc_cond == 4) || ((xga->accel.cc_cond == 1) && (dest_dat > color_cmp)) || ((xga->accel.cc_cond == 2) && (dest_dat == color_cmp)) || ((xga->accel.cc_cond == 3) && (dest_dat < color_cmp)) || ((xga->accel.cc_cond == 5) && (dest_dat >= color_cmp)) || ((xga->accel.cc_cond == 6) && (dest_dat != color_cmp)) || ((xga->accel.cc_cond == 7) && (dest_dat <= color_cmp))) {
old_dest_dat = dest_dat;
ROP(1, dest_dat, src_dat);
dest_dat = (dest_dat & plane_mask) | (old_dest_dat & ~plane_mask);
if ((xga->accel.command & 0x30) == 0) {
if (ssv & 0x10)
xga_accel_write_map_pixel(svga, dx, dy, xga->accel.dst_map, dstbase, dest_dat, xga->accel.px_map_width[xga->accel.dst_map] + 1);
} else if (((xga->accel.command & 0x30) == 0x10) && x) {
if (ssv & 0x10)
xga_accel_write_map_pixel(svga, dx, dy, xga->accel.dst_map, dstbase, dest_dat, xga->accel.px_map_width[xga->accel.dst_map] + 1);
} else if (((xga->accel.command & 0x30) == 0x20) && y) {
if (ssv & 0x10)
xga_accel_write_map_pixel(svga, dx, dy, xga->accel.dst_map, dstbase, dest_dat, xga->accel.px_map_width[xga->accel.dst_map] + 1);
}
}
}
} else {
src_dat = (((xga->accel.command >> 28) & 3) == 2) ? xga_accel_read_map_pixel(svga, xga->accel.src_map_x & 0xfff, xga->accel.src_map_y & 0xfff, xga->accel.src_map, srcbase, xga->accel.px_map_width[xga->accel.src_map] + 1, 1) : xga->accel.frgd_color;
dest_dat = xga_accel_read_map_pixel(svga, dx, dy, xga->accel.dst_map, dstbase, xga->accel.px_map_width[xga->accel.dst_map] + 1, 0);
if ((xga->accel.cc_cond == 4) || ((xga->accel.cc_cond == 1) && (dest_dat > color_cmp)) || ((xga->accel.cc_cond == 2) && (dest_dat == color_cmp)) || ((xga->accel.cc_cond == 3) && (dest_dat < color_cmp)) || ((xga->accel.cc_cond == 5) && (dest_dat >= color_cmp)) || ((xga->accel.cc_cond == 6) && (dest_dat != color_cmp)) || ((xga->accel.cc_cond == 7) && (dest_dat <= color_cmp))) {
old_dest_dat = dest_dat;
ROP(1, dest_dat, src_dat);
dest_dat = (dest_dat & plane_mask) | (old_dest_dat & ~plane_mask);
if ((xga->accel.command & 0x30) == 0) {
if (ssv & 0x10)
xga_accel_write_map_pixel(svga, dx, dy, xga->accel.dst_map, dstbase, dest_dat, xga->accel.px_map_width[xga->accel.dst_map] + 1);
} else if (((xga->accel.command & 0x30) == 0x10) && x) {
if (ssv & 0x10)
xga_accel_write_map_pixel(svga, dx, dy, xga->accel.dst_map, dstbase, dest_dat, xga->accel.px_map_width[xga->accel.dst_map] + 1);
} else if (((xga->accel.command & 0x30) == 0x20) && y) {
if (ssv & 0x10)
xga_accel_write_map_pixel(svga, dx, dy, xga->accel.dst_map, dstbase, dest_dat, xga->accel.px_map_width[xga->accel.dst_map] + 1);
}
}
}
if (!y)
break;
dx += dirx;
dy += diry;
x++;
y--;
}
}
xga->accel.dst_map_x = dx;
xga->accel.dst_map_y = dy;
}
static void
xga_line_draw_write(svga_t *svga)
{
xga_t *xga = (xga_t *) svga->xga;
uint32_t src_dat;
uint32_t dest_dat;
uint32_t old_dest_dat = 0x00000000;
uint32_t color_cmp = xga->accel.color_cmp;
uint32_t plane_mask = xga->accel.plane_mask;
uint32_t dstbase = xga->accel.px_map_base[xga->accel.dst_map];
uint32_t srcbase = xga->accel.px_map_base[xga->accel.src_map];
int y = xga->accel.blt_width;
int x = 0;
int16_t dx;
int16_t dy;
int16_t cx;
int16_t cy;
int err = xga->accel.bres_err_term;
int draw_pixel = 0;
cx = xga->accel.src_map_x & 0xfff;
cy = xga->accel.src_map_y & 0xfff;
dx = xga->accel.dst_map_x & 0x1fff;
if (xga->accel.dst_map_x >= 0x1800)
dx |= ~0x17ff;
dy = xga->accel.dst_map_y & 0x1fff;
if (xga->accel.dst_map_y >= 0x1800)
dy |= ~0x17ff;
if ((xga->accel.command & 0x30) == 0x30)
xga_log("Line Draw Write: BLTWIDTH=%d, BLTHEIGHT=%d, FRGDCOLOR=%04x, XDIR=%i, YDIR=%i, steep=%s, ERR=%04x.\n", xga->accel.blt_width, xga->accel.blt_height, xga->accel.frgd_color & 0xffff, xdir, ydir, (xga->accel.octant & 0x01) ? "0" : "1", err);
if (xga->accel.pat_src == 8) {
if ((xga->accel.command & 0x30) == 0x30) {
while (y >= 0) {
draw_pixel = 0;
if (xga->accel.octant & 0x01) {
if (xga->accel.octant & 0x02) { /*Bottom-to-Top*/
if (x)
draw_pixel = 1;
} else { /*Top-to-Bottom*/
if (y)
draw_pixel = 1;
}
} else if (!(xga->accel.octant & 0x04) && (err < (xga->accel.bres_k2 + xga->accel.bres_k1))) /*X+*/
draw_pixel = 1;
else if ((xga->accel.octant & 0x04) && (err >= 0)) /*X-*/
draw_pixel = 1;
if (xga->accel.command & 0xc0) {
if ((dx >= xga->accel.mask_map_origin_x_off) && (dx <= ((xga->accel.px_map_width[0] & 0xfff) + xga->accel.mask_map_origin_x_off)) && (dy >= xga->accel.mask_map_origin_y_off) && (dy <= ((xga->accel.px_map_height[0] & 0xfff) + xga->accel.mask_map_origin_y_off))) {
if (draw_pixel) {
src_dat = (((xga->accel.command >> 28) & 3) == 2) ? xga_accel_read_map_pixel(svga, cx, cy, xga->accel.src_map, srcbase, xga->accel.px_map_width[xga->accel.src_map] + 1, 1) : xga->accel.frgd_color;
dest_dat = xga_accel_read_map_pixel(svga, dx, dy, xga->accel.dst_map, dstbase, xga->accel.px_map_width[xga->accel.dst_map] + 1, 0);
if ((xga->accel.cc_cond == 4) || ((xga->accel.cc_cond == 1) && (dest_dat > color_cmp)) || ((xga->accel.cc_cond == 2) && (dest_dat == color_cmp)) || ((xga->accel.cc_cond == 3) && (dest_dat < color_cmp)) || ((xga->accel.cc_cond == 5) && (dest_dat >= color_cmp)) || ((xga->accel.cc_cond == 6) && (dest_dat != color_cmp)) || ((xga->accel.cc_cond == 7) && (dest_dat <= color_cmp))) {
ROP(1, dest_dat, src_dat);
xga_accel_write_map_pixel(svga, dx, dy, xga->accel.dst_map, dstbase, dest_dat, xga->accel.px_map_width[xga->accel.dst_map] + 1);
}
}
}
} else {
if (draw_pixel) {
src_dat = (((xga->accel.command >> 28) & 3) == 2) ? xga_accel_read_map_pixel(svga, cx, cy, xga->accel.src_map, srcbase, xga->accel.px_map_width[xga->accel.src_map] + 1, 1) : xga->accel.frgd_color;
dest_dat = xga_accel_read_map_pixel(svga, dx, dy, xga->accel.dst_map, dstbase, xga->accel.px_map_width[xga->accel.dst_map] + 1, 0);
if ((xga->accel.cc_cond == 4) || ((xga->accel.cc_cond == 1) && (dest_dat > color_cmp)) || ((xga->accel.cc_cond == 2) && (dest_dat == color_cmp)) || ((xga->accel.cc_cond == 3) && (dest_dat < color_cmp)) || ((xga->accel.cc_cond == 5) && (dest_dat >= color_cmp)) || ((xga->accel.cc_cond == 6) && (dest_dat != color_cmp)) || ((xga->accel.cc_cond == 7) && (dest_dat <= color_cmp))) {
ROP(1, dest_dat, src_dat);
xga_accel_write_map_pixel(svga, dx, dy, xga->accel.dst_map, dstbase, dest_dat, xga->accel.px_map_width[xga->accel.dst_map] + 1);
}
}
}
if (x == xga->accel.blt_width)
break;
if (xga->accel.octant & 0x01) {
if (xga->accel.octant & 0x02)
dy--;
else
dy++;
if (err >= 0) {
err += xga->accel.bres_k2;
if (xga->accel.octant & 0x04)
dx--;
else
dx++;
} else
err += xga->accel.bres_k1;
} else {
if (xga->accel.octant & 0x04)
dx--;
else
dx++;
if (err >= 0) {
err += xga->accel.bres_k2;
if (xga->accel.octant & 0x02)
dy--;
else
dy++;
} else
err += xga->accel.bres_k1;
}
x++;
y--;
}
} else {
while (y >= 0) {
if (xga->accel.command & 0xc0) {
if ((dx >= xga->accel.mask_map_origin_x_off) && (dx <= ((xga->accel.px_map_width[0] & 0xfff) + xga->accel.mask_map_origin_x_off)) && (dy >= xga->accel.mask_map_origin_y_off) && (dy <= ((xga->accel.px_map_height[0] & 0xfff) + xga->accel.mask_map_origin_y_off))) {
src_dat = (((xga->accel.command >> 28) & 3) == 2) ? xga_accel_read_map_pixel(svga, xga->accel.src_map_x & 0xfff, xga->accel.src_map_y & 0xfff, xga->accel.src_map, srcbase, xga->accel.px_map_width[xga->accel.src_map] + 1, 1) : xga->accel.frgd_color;
dest_dat = xga_accel_read_map_pixel(svga, dx, dy, xga->accel.dst_map, dstbase, xga->accel.px_map_width[xga->accel.dst_map] + 1, 0);
if ((xga->accel.cc_cond == 4) || ((xga->accel.cc_cond == 1) && (dest_dat > color_cmp)) || ((xga->accel.cc_cond == 2) && (dest_dat == color_cmp)) || ((xga->accel.cc_cond == 3) && (dest_dat < color_cmp)) || ((xga->accel.cc_cond == 5) && (dest_dat >= color_cmp)) || ((xga->accel.cc_cond == 6) && (dest_dat != color_cmp)) || ((xga->accel.cc_cond == 7) && (dest_dat <= color_cmp))) {
old_dest_dat = dest_dat;
ROP(1, dest_dat, src_dat);
dest_dat = (dest_dat & plane_mask) | (old_dest_dat & ~plane_mask);
if ((xga->accel.command & 0x30) == 0)
xga_accel_write_map_pixel(svga, dx, dy, xga->accel.dst_map, dstbase, dest_dat, xga->accel.px_map_width[xga->accel.dst_map] + 1);
else if (((xga->accel.command & 0x30) == 0x10) && x)
xga_accel_write_map_pixel(svga, dx, dy, xga->accel.dst_map, dstbase, dest_dat, xga->accel.px_map_width[xga->accel.dst_map] + 1);
else if (((xga->accel.command & 0x30) == 0x20) && y)
xga_accel_write_map_pixel(svga, dx, dy, xga->accel.dst_map, dstbase, dest_dat, xga->accel.px_map_width[xga->accel.dst_map] + 1);
}
}
} else {
src_dat = (((xga->accel.command >> 28) & 3) == 2) ? xga_accel_read_map_pixel(svga, xga->accel.src_map_x & 0xfff, xga->accel.src_map_y & 0xfff, xga->accel.src_map, srcbase, xga->accel.px_map_width[xga->accel.src_map] + 1, 1) : xga->accel.frgd_color;
dest_dat = xga_accel_read_map_pixel(svga, dx, dy, xga->accel.dst_map, dstbase, xga->accel.px_map_width[xga->accel.dst_map] + 1, 0);
if ((xga->accel.cc_cond == 4) || ((xga->accel.cc_cond == 1) && (dest_dat > color_cmp)) || ((xga->accel.cc_cond == 2) && (dest_dat == color_cmp)) || ((xga->accel.cc_cond == 3) && (dest_dat < color_cmp)) || ((xga->accel.cc_cond == 5) && (dest_dat >= color_cmp)) || ((xga->accel.cc_cond == 6) && (dest_dat != color_cmp)) || ((xga->accel.cc_cond == 7) && (dest_dat <= color_cmp))) {
old_dest_dat = dest_dat;
ROP(1, dest_dat, src_dat);
dest_dat = (dest_dat & plane_mask) | (old_dest_dat & ~plane_mask);
if ((xga->accel.command & 0x30) == 0)
xga_accel_write_map_pixel(svga, dx, dy, xga->accel.dst_map, dstbase, dest_dat, xga->accel.px_map_width[xga->accel.dst_map] + 1);
else if (((xga->accel.command & 0x30) == 0x10) && x)
xga_accel_write_map_pixel(svga, dx, dy, xga->accel.dst_map, dstbase, dest_dat, xga->accel.px_map_width[xga->accel.dst_map] + 1);
else if (((xga->accel.command & 0x30) == 0x20) && y)
xga_accel_write_map_pixel(svga, dx, dy, xga->accel.dst_map, dstbase, dest_dat, xga->accel.px_map_width[xga->accel.dst_map] + 1);
}
}
if (!y) {
xga->accel.dst_map_x = dx;
xga->accel.dst_map_y = dy;
break;
}
if (xga->accel.octant & 0x01) {
if (xga->accel.octant & 0x02)
dy--;
else
dy++;
if (err >= 0) {
err += xga->accel.bres_k2;
if (xga->accel.octant & 0x04)
dx--;
else
dx++;
} else
err += xga->accel.bres_k1;
} else {
if (xga->accel.octant & 0x04)
dx--;
else
dx++;
if (err >= 0) {
err += xga->accel.bres_k2;
if (xga->accel.octant & 0x02)
dy--;
else
dy++;
} else
err += xga->accel.bres_k1;
}
y--;
x++;
}
}
}
}
static void
xga_bitblt(svga_t *svga)
{
xga_t *xga = (xga_t *) svga->xga;
uint32_t src_dat;
uint32_t dest_dat;
uint32_t old_dest_dat;
uint32_t color_cmp = xga->accel.color_cmp;
uint32_t plane_mask = xga->accel.plane_mask;
uint32_t patbase = xga->accel.px_map_base[xga->accel.pat_src];
uint32_t dstbase = xga->accel.px_map_base[xga->accel.dst_map];
uint32_t srcbase = xga->accel.px_map_base[xga->accel.src_map];
uint32_t patwidth = xga->accel.px_map_width[xga->accel.pat_src];
uint32_t dstwidth = xga->accel.px_map_width[xga->accel.dst_map];
uint32_t srcwidth = xga->accel.px_map_width[xga->accel.src_map];
uint32_t patheight = xga->accel.px_map_height[xga->accel.pat_src];
uint32_t srcheight = xga->accel.px_map_height[xga->accel.src_map];
uint32_t dstheight = xga->accel.px_map_height[xga->accel.dst_map];
uint32_t frgdcol = xga->accel.frgd_color;
uint32_t bkgdcol = xga->accel.bkgd_color;
int16_t dx;
int16_t dy;
int mix = 0;
int xdir = (xga->accel.octant & 0x04) ? -1 : 1;
int ydir = (xga->accel.octant & 0x02) ? -1 : 1;
xga->accel.x = xga->accel.blt_width & 0xfff;
xga->accel.y = xga->accel.blt_height & 0xfff;
xga->accel.sx = xga->accel.src_map_x & 0xfff;
xga->accel.sy = xga->accel.src_map_y & 0xfff;
xga->accel.px = xga->accel.pat_map_x & 0xfff;
xga->accel.py = xga->accel.pat_map_y & 0xfff;
dx = xga->accel.dst_map_x & 0x1fff;
dy = xga->accel.dst_map_y & 0x1fff;
if (xga->accel.dst_map_x >= 0x1800)
dx |= ~0x17ff;
if (xga->accel.dst_map_y >= 0x1800)
dy |= ~0x17ff;
xga_log("D(%d,%d), SWH(%d,%d), BLT(%d,%d), dstwidth=%d.\n", dx, dy, xga->accel.x, xga->accel.y, srcwidth, srcheight, dstwidth);
xga->accel.pattern = 0;
xga->accel.filling = 0;
xga_log("XGA bitblt linear endian reverse=%d, access_mode=%x, octanty=%d, src command = %08x, "
"pxsrcmap=%x, pxpatmap=%x, pxdstmap=%x, srcmap=%d, patmap=%d, dstmap=%d, "
"usesrcvramfr=%d, usevrambk=%d.\n",
xga->linear_endian_reverse, xga->access_mode & 0x0f, ydir, xga->accel.command,
xga->accel.px_map_format[xga->accel.src_map] & 0x0f,
xga->accel.px_map_format[xga->accel.pat_src] & 0x0f,
xga->accel.px_map_format[xga->accel.dst_map] & 0x0f,
xga->accel.src_map, xga->accel.pat_src,
xga->accel.dst_map, ((xga->accel.command >> 28) & 3), ((xga->accel.command >> 30) & 3));
if (xga->accel.pat_src == 8) {
if (srcheight == 7)
xga->accel.pattern = 1;
else {
if ((dstwidth == (xga->h_disp - 1)) && (srcwidth == 1)) {
if ((xga->accel.dst_map == 1) && (xga->accel.src_map == 2)) {
if ((xga->accel.px_map_format[xga->accel.dst_map] >= 0x0b) && (xga->accel.px_map_format[xga->accel.src_map] >= 0x0b))
xga->accel.pattern = 1;
}
}
}
xga_log("PAT8: PatFormat=%x, SrcFormat=%x, DstFormat=%x.\n", xga->accel.px_map_format[xga->accel.pat_src] & 8, (xga->accel.px_map_format[xga->accel.src_map]), (xga->accel.px_map_format[xga->accel.dst_map]));
xga_log("Pattern Map = 8: CMD = %08x: SRCBase = %08x, DSTBase = %08x, from/to vram dir = %d, "
"cmd dir = %06x\n", xga->accel.command, srcbase, dstbase, xga->from_to_vram,
xga->accel.dir_cmd);
xga_log("CMD = %08x: Y = %d, X = %d, patsrc = %02x, srcmap = %d, dstmap = %d, py = %d, "
"sy = %d, dy = %d, width0 = %d, width1 = %d, width2 = %d, width3 = %d\n",
xga->accel.command, xga->accel.y, xga->accel.x, xga->accel.pat_src, xga->accel.src_map,
xga->accel.dst_map, xga->accel.py, xga->accel.sy, dy,
xga->accel.px_map_width[0], xga->accel.px_map_width[1],
xga->accel.px_map_width[2], xga->accel.px_map_width[3]);
xga_log("PAT8: Pattern Enabled?=%d, xdir=%d, ydir=%d.\n", xga->accel.pattern, xdir, ydir);
while (xga->accel.y >= 0) {
if (xga->accel.command & 0xc0) {
if ((dx >= xga->accel.mask_map_origin_x_off) && (dx <= ((xga->accel.px_map_width[0] & 0xfff) + xga->accel.mask_map_origin_x_off)) && (dy >= xga->accel.mask_map_origin_y_off) && (dy <= ((xga->accel.px_map_height[0] & 0xfff) + xga->accel.mask_map_origin_y_off))) {
src_dat = (((xga->accel.command >> 28) & 3) == 2) ? xga_accel_read_map_pixel(svga, xga->accel.sx, xga->accel.sy, xga->accel.src_map, srcbase, srcwidth + 1, 1) : frgdcol;
dest_dat = xga_accel_read_map_pixel(svga, dx, dy, xga->accel.dst_map, dstbase, dstwidth + 1, 0);
if ((xga->accel.cc_cond == 4) || ((xga->accel.cc_cond == 1) && (dest_dat > color_cmp)) || ((xga->accel.cc_cond == 2) && (dest_dat == color_cmp)) || ((xga->accel.cc_cond == 3) && (dest_dat < color_cmp)) || ((xga->accel.cc_cond == 5) && (dest_dat >= color_cmp)) || ((xga->accel.cc_cond == 6) && (dest_dat != color_cmp)) || ((xga->accel.cc_cond == 7) && (dest_dat <= color_cmp))) {
old_dest_dat = dest_dat;
ROP(1, dest_dat, src_dat);
dest_dat = (dest_dat & plane_mask) | (old_dest_dat & ~plane_mask);
xga_accel_write_map_pixel(svga, dx, dy, xga->accel.dst_map, dstbase, dest_dat, dstwidth + 1);
}
}
} else {
if ((dx >= 0) && (dx <= dstwidth) && (dy >= 0) && (dy <= dstheight)) {
src_dat = (((xga->accel.command >> 28) & 3) == 2) ? xga_accel_read_map_pixel(svga, xga->accel.sx, xga->accel.sy, xga->accel.src_map, srcbase, srcwidth + 1, 1) : frgdcol;
dest_dat = xga_accel_read_map_pixel(svga, dx, dy, xga->accel.dst_map, dstbase, dstwidth + 1, 0);
if ((xga->accel.cc_cond == 4) || ((xga->accel.cc_cond == 1) && (dest_dat > color_cmp)) || ((xga->accel.cc_cond == 2) && (dest_dat == color_cmp)) || ((xga->accel.cc_cond == 3) && (dest_dat < color_cmp)) || ((xga->accel.cc_cond == 5) && (dest_dat >= color_cmp)) || ((xga->accel.cc_cond == 6) && (dest_dat != color_cmp)) || ((xga->accel.cc_cond == 7) && (dest_dat <= color_cmp))) {
old_dest_dat = dest_dat;
ROP(1, dest_dat, src_dat);
dest_dat = (dest_dat & plane_mask) | (old_dest_dat & ~plane_mask);
xga_accel_write_map_pixel(svga, dx, dy, xga->accel.dst_map, dstbase, dest_dat, dstwidth + 1);
}
}
}
if (xga->accel.pattern)
xga->accel.sx = ((xga->accel.sx + xdir) & srcwidth) | (xga->accel.sx & ~srcwidth);
else
xga->accel.sx += xdir;
dx += xdir;
xga->accel.x--;
if (xga->accel.x < 0) {
xga->accel.x = xga->accel.blt_width & 0xfff;
dx = xga->accel.dst_map_x & 0x1fff;
if (xga->accel.dst_map_x >= 0x1800)
dx |= ~0x17ff;
xga->accel.sx = xga->accel.src_map_x & 0xfff;
dy += ydir;
if (xga->accel.pattern)
xga->accel.sy = ((xga->accel.sy + ydir) & srcheight) | (xga->accel.sy & ~srcheight);
else
xga->accel.sy += ydir;
xga->accel.y--;
if (xga->accel.y < 0) {
xga->accel.dst_map_x = dx;
xga->accel.dst_map_y = dy;
return;
}
}
}
} else if (xga->accel.pat_src >= 1) {
if (patheight == 7) {
if (xga->accel.src_map != 1)
xga->accel.pattern = 1;
else if ((xga->accel.src_map == 1) && (patwidth == 7))
xga->accel.pattern = 1;
} else {
if (dstwidth == (xga->h_disp - 1)) {
if (srcwidth == (xga->h_disp - 1)) {
if ((xga->accel.src_map == 1) && (xga->accel.dst_map == 1) && (xga->accel.pat_src == 2)) {
if ((xga->accel.px_map_format[xga->accel.dst_map] >= 0x0b) && (xga->accel.px <= 7) && (xga->accel.py <= 3))
xga->accel.pattern = 1;
}
} else {
if (!xga->accel.src_map && (xga->accel.dst_map == 1) && (xga->accel.pat_src == 2)) {
if ((xga->accel.px_map_format[xga->accel.dst_map] >= 0x0b) && (xga->accel.px <= 7) && (xga->accel.py <= 3)) {
if ((patwidth >= 7) && ((xga->accel.command & 0xc0) == 0x40))
xga->accel.pattern = 0;
else
xga->accel.pattern = 1;
}
}
}
}
}
xga_log("PAT%d: PatFormat=%x, SrcFormat=%x, DstFormat=%x.\n", xga->accel.pat_src, xga->accel.px_map_format[xga->accel.pat_src] & 8, (xga->accel.px_map_format[xga->accel.src_map]), (xga->accel.px_map_format[xga->accel.dst_map]));
xga_log("XGA bitblt linear endian reverse=%d, octanty=%d, src command = %08x, pxsrcmap=%x, "
"pxdstmap=%x, srcmap=%d, patmap=%d, dstmap=%d, dstwidth=%d, dstheight=%d, srcwidth=%d, "
"srcheight=%d, dstbase=%08x, srcbase=%08x.\n", xga->linear_endian_reverse, ydir,
xga->accel.command, xga->accel.px_map_format[xga->accel.src_map] & 0x0f,
xga->accel.px_map_format[xga->accel.dst_map] & 0x0f, xga->accel.src_map,
xga->accel.pat_src, xga->accel.dst_map, dstwidth, dstheight, srcwidth, srcheight,
dstbase, srcbase);
xga_log("Pattern Map = %d: CMD = %08x: PATBase = %08x, SRCBase = %08x, DSTBase = %08x\n",
xga->accel.pat_src, xga->accel.command, patbase, srcbase, dstbase);
xga_log("CMD = %08x: Y = %d, X = %d, patsrc = %02x, srcmap = %d, dstmap = %d, py = %d, "
"sy = %d, dy = %d, width0 = %d, width1 = %d, width2 = %d, width3 = %d, bkgdcol = %02x\n",
xga->accel.command, xga->accel.y, xga->accel.x, xga->accel.pat_src,
xga->accel.src_map, xga->accel.dst_map, xga->accel.py, xga->accel.sy, xga->accel.dy,
xga->accel.px_map_width[0], xga->accel.px_map_width[1],
xga->accel.px_map_width[2], xga->accel.px_map_width[3], bkgdcol);
xga_log("Pattern Enabled?=%d, patwidth=%d, patheight=%d, P(%d,%d).\n", xga->accel.pattern, patwidth, patheight, xga->accel.px, xga->accel.py);
if ((((xga->accel.command >> 24) & 0x0f) == 0x0a) && ((xga->accel.bkgd_mix & 0x1f) == 5)) {
while (xga->accel.y >= 0) {
mix = xga_accel_read_pattern_map_pixel(svga, xga->accel.px, xga->accel.py, xga->accel.pat_src, patbase, patwidth + 1);
if (mix)
xga->accel.filling = !xga->accel.filling;
if (xga->accel.command & 0xc0) {
if ((dx >= xga->accel.mask_map_origin_x_off) && (dx <= ((xga->accel.px_map_width[0] & 0xfff) + xga->accel.mask_map_origin_x_off)) && (dy >= xga->accel.mask_map_origin_y_off) && (dy <= ((xga->accel.px_map_height[0] & 0xfff) + xga->accel.mask_map_origin_y_off))) {
src_dat = (((xga->accel.command >> 28) & 3) == 2) ? xga_accel_read_map_pixel(svga, xga->accel.sx, xga->accel.sy, xga->accel.src_map, srcbase, srcwidth + 1, 1) : frgdcol;
if (xga->accel.filling) {
dest_dat = xga_accel_read_map_pixel(svga, dx, dy, xga->accel.dst_map, dstbase, 1024, 0);
if ((xga->accel.cc_cond == 4) || ((xga->accel.cc_cond == 1) && (dest_dat > color_cmp)) || ((xga->accel.cc_cond == 2) && (dest_dat == color_cmp)) || ((xga->accel.cc_cond == 3) && (dest_dat < color_cmp)) || ((xga->accel.cc_cond == 5) && (dest_dat >= color_cmp)) || ((xga->accel.cc_cond == 6) && (dest_dat != color_cmp)) || ((xga->accel.cc_cond == 7) && (dest_dat <= color_cmp))) {
old_dest_dat = dest_dat;
ROP(1, dest_dat, src_dat);
dest_dat = (dest_dat & plane_mask) | (old_dest_dat & ~plane_mask);
xga_log("1SRCDat=%02x, DSTDat=%02x, Old=%02x, MIX=%d.\n", src_dat, dest_dat, old_dest_dat, area_state);
xga_accel_write_map_pixel(svga, dx, dy, xga->accel.dst_map, dstbase, dest_dat, dstwidth + 1);
}
}
}
} else {
if ((dx >= 0) && (dx <= dstwidth) && (dy >= 0) && (dy <= dstheight)) {
src_dat = (((xga->accel.command >> 28) & 3) == 2) ? xga_accel_read_map_pixel(svga, xga->accel.sx, xga->accel.sy, xga->accel.src_map, srcbase, srcwidth + 1, 1) : frgdcol;
if (xga->accel.filling) {
dest_dat = xga_accel_read_map_pixel(svga, dx, dy, xga->accel.dst_map, dstbase, dstwidth + 1, 0);
if ((xga->accel.cc_cond == 4) || ((xga->accel.cc_cond == 1) && (dest_dat > color_cmp)) || ((xga->accel.cc_cond == 2) && (dest_dat == color_cmp)) || ((xga->accel.cc_cond == 3) && (dest_dat < color_cmp)) || ((xga->accel.cc_cond == 5) && (dest_dat >= color_cmp)) || ((xga->accel.cc_cond == 6) && (dest_dat != color_cmp)) || ((xga->accel.cc_cond == 7) && (dest_dat <= color_cmp))) {
old_dest_dat = dest_dat;
ROP(1, dest_dat, src_dat);
dest_dat = (dest_dat & plane_mask) | (old_dest_dat & ~plane_mask);
xga_log("2Fill: NumXY(%d,%d): DXY(%d,%d): SRCDat=%02x, DSTDat=%02x, Old=%02x, frgdcol=%02x, bkgdcol=%02x, MIX=%d, frgdmix=%02x, bkgdmix=%02x, dstmapfmt=%02x, srcmapfmt=%02x, srcmapnum=%d.\n", x, y, dx, dy, src_dat, dest_dat, old_dest_dat, frgdcol, bkgdcol, area_state, xga->accel.frgd_mix & 0x1f, xga->accel.bkgd_mix & 0x1f, xga->accel.px_map_format[xga->accel.dst_map] & 0x0f, xga->accel.px_map_format[xga->accel.src_map] & 0x0f, xga->accel.src_map);
xga_accel_write_map_pixel(svga, dx, dy, xga->accel.dst_map, dstbase, dest_dat, dstwidth + 1);
}
}
}
}
xga->accel.sx = ((xga->accel.sx + xdir) & srcwidth) | (xga->accel.sx & ~srcwidth);
xga->accel.px++;
dx++;
xga->accel.x--;
if (xga->accel.x < 0) {
xga->accel.y--;
xga->accel.x = xga->accel.blt_width & 0xfff;
dx = xga->accel.dst_map_x & 0x1fff;
if (xga->accel.dst_map_x >= 0x1800)
dx |= ~0x17ff;
xga->accel.sx = xga->accel.src_map_x & 0xfff;
xga->accel.px = xga->accel.pat_map_x & 0xfff;
xga->accel.sy = ((xga->accel.sy + ydir) & srcheight) | (xga->accel.sy & ~srcheight);
xga->accel.py++;
dy++;
xga->accel.filling = 0;
if (xga->accel.y < 0)
return;
}
}
} else {
while (xga->accel.y >= 0) {
mix = xga_accel_read_pattern_map_pixel(svga, xga->accel.px, xga->accel.py, xga->accel.pat_src, patbase, patwidth + 1);
if (xga->accel.command & 0xc0) {
if ((dx >= xga->accel.mask_map_origin_x_off) && (dx <= ((xga->accel.px_map_width[0] & 0xfff) + xga->accel.mask_map_origin_x_off)) && (dy >= xga->accel.mask_map_origin_y_off) && (dy <= ((xga->accel.px_map_height[0] & 0xfff) + xga->accel.mask_map_origin_y_off))) {
if (mix)
src_dat = (((xga->accel.command >> 28) & 3) == 2) ? xga_accel_read_map_pixel(svga, xga->accel.sx, xga->accel.sy, xga->accel.src_map, srcbase, srcwidth + 1, 1) : frgdcol;
else
src_dat = (((xga->accel.command >> 30) & 3) == 2) ? xga_accel_read_map_pixel(svga, xga->accel.sx, xga->accel.sy, xga->accel.src_map, srcbase, srcwidth + 1, 1) : bkgdcol;
dest_dat = xga_accel_read_map_pixel(svga, dx, dy, xga->accel.dst_map, dstbase, dstwidth + 1, 0);
if ((xga->accel.cc_cond == 4) || ((xga->accel.cc_cond == 1) && (dest_dat > color_cmp)) || ((xga->accel.cc_cond == 2) && (dest_dat == color_cmp)) || ((xga->accel.cc_cond == 3) && (dest_dat < color_cmp)) || ((xga->accel.cc_cond == 5) && (dest_dat >= color_cmp)) || ((xga->accel.cc_cond == 6) && (dest_dat != color_cmp)) || ((xga->accel.cc_cond == 7) && (dest_dat <= color_cmp))) {
old_dest_dat = dest_dat;
ROP(mix, dest_dat, src_dat);
dest_dat = (dest_dat & plane_mask) | (old_dest_dat & ~plane_mask);
xga_accel_write_map_pixel(svga, dx, dy, xga->accel.dst_map, dstbase, dest_dat, dstwidth + 1);
}
}
} else {
if ((dx >= 0) && (dx <= dstwidth) && (dy >= 0) && (dy <= dstheight)) {
if (mix)
src_dat = (((xga->accel.command >> 28) & 3) == 2) ? xga_accel_read_map_pixel(svga, xga->accel.sx, xga->accel.sy, xga->accel.src_map, srcbase, srcwidth + 1, 1) : frgdcol;
else
src_dat = (((xga->accel.command >> 30) & 3) == 2) ? xga_accel_read_map_pixel(svga, xga->accel.sx, xga->accel.sy, xga->accel.src_map, srcbase, srcwidth + 1, 1) : bkgdcol;
dest_dat = xga_accel_read_map_pixel(svga, dx, dy, xga->accel.dst_map, dstbase, dstwidth + 1, 0);
if ((xga->accel.cc_cond == 4) || ((xga->accel.cc_cond == 1) && (dest_dat > color_cmp)) || ((xga->accel.cc_cond == 2) && (dest_dat == color_cmp)) || ((xga->accel.cc_cond == 3) && (dest_dat < color_cmp)) || ((xga->accel.cc_cond == 5) && (dest_dat >= color_cmp)) || ((xga->accel.cc_cond == 6) && (dest_dat != color_cmp)) || ((xga->accel.cc_cond == 7) && (dest_dat <= color_cmp))) {
old_dest_dat = dest_dat;
ROP(mix, dest_dat, src_dat);
dest_dat = (dest_dat & plane_mask) | (old_dest_dat & ~plane_mask);
xga_accel_write_map_pixel(svga, dx, dy, xga->accel.dst_map, dstbase, dest_dat, dstwidth + 1);
}
}
}
xga->accel.sx += xdir;
if (xga->accel.pattern)
xga->accel.px = ((xga->accel.px + xdir) & patwidth) | (xga->accel.px & ~patwidth);
else
xga->accel.px += xdir;
dx += xdir;
xga->accel.x--;
if (xga->accel.x < 0) {
xga->accel.y--;
xga->accel.x = xga->accel.blt_width & 0xfff;
dx = xga->accel.dst_map_x & 0x1fff;
if (xga->accel.dst_map_x >= 0x1800)
dx |= ~0x17ff;
xga->accel.sx = xga->accel.src_map_x & 0xfff;
xga->accel.px = xga->accel.pat_map_x & 0xfff;
xga->accel.sy += ydir;
if (xga->accel.pattern)
xga->accel.py = ((xga->accel.py + ydir) & patheight) | (xga->accel.py & ~patheight);
else
xga->accel.py += ydir;
dy += ydir;
if (xga->accel.y < 0) {
xga->accel.dst_map_x = dx;
xga->accel.dst_map_y = dy;
return;
}
}
}
}
}
}
static void
xga_mem_write(uint32_t addr, uint32_t val, xga_t *xga, svga_t *svga, int len)
{
addr &= 0x1fff;
if (addr >= 0x1800) {
switch (addr & 0x7f) {
case 0x11:
xga->accel.control = val;
xga_log("Control=%02x.\n", val);
break;
case 0x12:
xga->accel.px_map_idx = val & 3;
break;
case 0x14:
if (len == 4)
xga->accel.px_map_base[xga->accel.px_map_idx] = val;
else if (len == 2)
xga->accel.px_map_base[xga->accel.px_map_idx] = (xga->accel.px_map_base[xga->accel.px_map_idx] & 0xffff0000) | val;
else
xga->accel.px_map_base[xga->accel.px_map_idx] = (xga->accel.px_map_base[xga->accel.px_map_idx] & 0xffffff00) | val;
break;
case 0x15:
if (len == 1)
xga->accel.px_map_base[xga->accel.px_map_idx] = (xga->accel.px_map_base[xga->accel.px_map_idx] & 0xffff00ff) | (val << 8);
break;
case 0x16:
if (len == 2)
xga->accel.px_map_base[xga->accel.px_map_idx] = (xga->accel.px_map_base[xga->accel.px_map_idx] & 0x0000ffff) | (val << 16);
else
xga->accel.px_map_base[xga->accel.px_map_idx] = (xga->accel.px_map_base[xga->accel.px_map_idx] & 0xff00ffff) | (val << 16);
break;
case 0x17:
if (len == 1)
xga->accel.px_map_base[xga->accel.px_map_idx] = (xga->accel.px_map_base[xga->accel.px_map_idx] & 0x00ffffff) | (val << 24);
break;
case 0x18:
if (len == 4) {
xga->accel.px_map_width[xga->accel.px_map_idx] = val & 0xffff;
xga->accel.px_map_height[xga->accel.px_map_idx] = (val >> 16) & 0xffff;
} else if (len == 2) {
xga->accel.px_map_width[xga->accel.px_map_idx] = val & 0xffff;
} else
xga->accel.px_map_width[xga->accel.px_map_idx] = (xga->accel.px_map_width[xga->accel.px_map_idx] & 0xff00) | val;
break;
case 0x19:
if (len == 1)
xga->accel.px_map_width[xga->accel.px_map_idx] = (xga->accel.px_map_width[xga->accel.px_map_idx] & 0xff) | (val << 8);
break;
case 0x1a:
if (len == 2)
xga->accel.px_map_height[xga->accel.px_map_idx] = val & 0xffff;
else
xga->accel.px_map_height[xga->accel.px_map_idx] = (xga->accel.px_map_height[xga->accel.px_map_idx] & 0xff00) | val;
break;
case 0x1b:
if (len == 1)
xga->accel.px_map_height[xga->accel.px_map_idx] = (xga->accel.px_map_height[xga->accel.px_map_idx] & 0xff) | (val << 8);
break;
case 0x1c:
xga->accel.px_map_format[xga->accel.px_map_idx] = val;
break;
case 0x20:
if (len >= 2) {
xga->accel.bres_err_term = val & 0x3fff;
if (val & 0x2000)
xga->accel.bres_err_term |= ~0x1fff;
} else
xga->accel.bres_err_term = (xga->accel.bres_err_term & 0x3f00) | val;
break;
case 0x21:
if (len == 1) {
xga->accel.bres_err_term = (xga->accel.bres_err_term & 0xff) | ((val & 0x3f) << 8);
if (val & 0x20)
xga->accel.bres_err_term |= ~0x1fff;
}
break;
case 0x24:
if (len >= 2) {
xga->accel.bres_k1 = val & 0x3fff;
if (val & 0x2000)
xga->accel.bres_k1 |= ~0x1fff;
} else
xga->accel.bres_k1 = (xga->accel.bres_k1 & 0x3f00) | val;
break;
case 0x25:
if (len == 1) {
xga->accel.bres_k1 = (xga->accel.bres_k1 & 0xff) | ((val & 0x3f) << 8);
if (val & 0x20)
xga->accel.bres_k1 |= ~0x1fff;
}
break;
case 0x28:
if (len >= 2) {
xga->accel.bres_k2 = val & 0x3fff;
if (val & 0x2000)
xga->accel.bres_k2 |= ~0x1fff;
} else
xga->accel.bres_k2 = (xga->accel.bres_k2 & 0x3f00) | val;
break;
case 0x29:
if (len == 1) {
xga->accel.bres_k2 = (xga->accel.bres_k2 & 0xff) | ((val & 0x3f) << 8);
if (val & 0x20)
xga->accel.bres_k2 |= ~0x1fff;
}
break;
case 0x2c:
if (len == 4) {
xga->accel.short_stroke = val;
xga->accel.short_stroke_vector1 = xga->accel.short_stroke & 0xff;
xga->accel.short_stroke_vector2 = (xga->accel.short_stroke >> 8) & 0xff;
xga->accel.short_stroke_vector3 = (xga->accel.short_stroke >> 16) & 0xff;
xga->accel.short_stroke_vector4 = (xga->accel.short_stroke >> 24) & 0xff;
xga_log("1Vector = %02x, 2Vector = %02x, 3Vector = %02x, 4Vector = %02x\n",
xga->accel.short_stroke_vector1, xga->accel.short_stroke_vector2,
xga->accel.short_stroke_vector3, xga->accel.short_stroke_vector4);
xga_short_stroke(svga, xga->accel.short_stroke_vector1);
xga_short_stroke(svga, xga->accel.short_stroke_vector2);
xga_short_stroke(svga, xga->accel.short_stroke_vector3);
xga_short_stroke(svga, xga->accel.short_stroke_vector4);
} else if (len == 2)
xga->accel.short_stroke = (xga->accel.short_stroke & 0xffff0000) | val;
else
xga->accel.short_stroke = (xga->accel.short_stroke & 0xffffff00) | val;
break;
case 0x2d:
if (len == 1)
xga->accel.short_stroke = (xga->accel.short_stroke & 0xffff00ff) | (val << 8);
break;
case 0x2e:
if (len == 2) {
xga->accel.short_stroke = (xga->accel.short_stroke & 0x0000ffff) | (val << 16);
} else
xga->accel.short_stroke = (xga->accel.short_stroke & 0xff00ffff) | (val << 16);
break;
case 0x2f:
if (len == 1) {
xga->accel.short_stroke = (xga->accel.short_stroke & 0x00ffffff) | (val << 24);
}
break;
case 0x48:
xga->accel.frgd_mix = val & 0xff;
if (len == 4) {
xga->accel.bkgd_mix = (val >> 8) & 0xff;
xga->accel.cc_cond = (val >> 16) & 0x07;
} else if (len == 2) {
xga->accel.bkgd_mix = (val >> 8) & 0xff;
}
break;
case 0x49:
xga->accel.bkgd_mix = val & 0xff;
break;
case 0x4a:
xga->accel.cc_cond = val & 0x07;
break;
case 0x4c:
if (len == 4)
xga->accel.color_cmp = val;
else if (len == 2)
xga->accel.color_cmp = (xga->accel.color_cmp & 0xffff0000) | val;
else
xga->accel.color_cmp = (xga->accel.color_cmp & 0xffffff00) | val;
break;
case 0x4d:
if (len == 1)
xga->accel.color_cmp = (xga->accel.color_cmp & 0xffff00ff) | (val << 8);
break;
case 0x4e:
if (len == 2)
xga->accel.color_cmp = (xga->accel.color_cmp & 0x0000ffff) | (val << 16);
else
xga->accel.color_cmp = (xga->accel.color_cmp & 0xff00ffff) | (val << 16);
break;
case 0x4f:
if (len == 1)
xga->accel.color_cmp = (xga->accel.color_cmp & 0x00ffffff) | (val << 24);
break;
case 0x50:
if (len == 4)
xga->accel.plane_mask = val;
else if (len == 2)
xga->accel.plane_mask = (xga->accel.plane_mask & 0xffff0000) | val;
else
xga->accel.plane_mask = (xga->accel.plane_mask & 0xffffff00) | val;
break;
case 0x51:
if (len == 1)
xga->accel.plane_mask = (xga->accel.plane_mask & 0xffff00ff) | (val << 8);
break;
case 0x52:
if (len == 2)
xga->accel.plane_mask = (xga->accel.plane_mask & 0x0000ffff) | (val << 16);
else
xga->accel.plane_mask = (xga->accel.plane_mask & 0xff00ffff) | (val << 16);
break;
case 0x53:
if (len == 1)
xga->accel.plane_mask = (xga->accel.plane_mask & 0x00ffffff) | (val << 24);
break;
case 0x54:
if (len == 4)
xga->accel.carry_chain = val;
else if (len == 2)
xga->accel.carry_chain = (xga->accel.carry_chain & 0xffff0000) | val;
else
xga->accel.carry_chain = (xga->accel.carry_chain & 0xffffff00) | val;
break;
case 0x55:
if (len == 1)
xga->accel.carry_chain = (xga->accel.carry_chain & 0xffff00ff) | (val << 8);
break;
case 0x56:
if (len == 2)
xga->accel.carry_chain = (xga->accel.carry_chain & 0x0000ffff) | (val << 16);
else
xga->accel.carry_chain = (xga->accel.carry_chain & 0xff00ffff) | (val << 16);
break;
case 0x57:
if (len == 1)
xga->accel.carry_chain = (xga->accel.carry_chain & 0x00ffffff) | (val << 24);
break;
case 0x58:
if (len == 4)
xga->accel.frgd_color = val;
else if (len == 2)
xga->accel.frgd_color = (xga->accel.frgd_color & 0xffff0000) | val;
else
xga->accel.frgd_color = (xga->accel.frgd_color & 0xffffff00) | val;
break;
case 0x59:
if (len == 1)
xga->accel.frgd_color = (xga->accel.frgd_color & 0xffff00ff) | (val << 8);
break;
case 0x5a:
if (len == 2)
xga->accel.frgd_color = (xga->accel.frgd_color & 0x0000ffff) | (val << 16);
else
xga->accel.frgd_color = (xga->accel.frgd_color & 0xff00ffff) | (val << 16);
break;
case 0x5b:
if (len == 1)
xga->accel.frgd_color = (xga->accel.frgd_color & 0x00ffffff) | (val << 24);
break;
case 0x5c:
if (len == 4)
xga->accel.bkgd_color = val;
else if (len == 2)
xga->accel.bkgd_color = (xga->accel.bkgd_color & 0xffff0000) | val;
else
xga->accel.bkgd_color = (xga->accel.bkgd_color & 0xffffff00) | val;
break;
case 0x5d:
if (len == 1)
xga->accel.bkgd_color = (xga->accel.bkgd_color & 0xffff00ff) | (val << 8);
break;
case 0x5e:
if (len == 2)
xga->accel.bkgd_color = (xga->accel.bkgd_color & 0x0000ffff) | (val << 16);
else
xga->accel.bkgd_color = (xga->accel.bkgd_color & 0xff00ffff) | (val << 16);
break;
case 0x5f:
if (len == 1)
xga->accel.bkgd_color = (xga->accel.bkgd_color & 0x00ffffff) | (val << 24);
break;
case 0x60:
if (len == 4) {
xga->accel.blt_width = val & 0xffff;
xga->accel.blt_height = (val >> 16) & 0xffff;
} else if (len == 2) {
xga->accel.blt_width = val;
} else
xga->accel.blt_width = (xga->accel.blt_width & 0xff00) | val;
break;
case 0x61:
if (len == 1)
xga->accel.blt_width = (xga->accel.blt_width & 0xff) | (val << 8);
break;
case 0x62:
if (len == 2)
xga->accel.blt_height = val;
else
xga->accel.blt_height = (xga->accel.blt_height & 0xff00) | val;
break;
case 0x63:
if (len == 1)
xga->accel.blt_height = (xga->accel.blt_height & 0xff) | (val << 8);
break;
case 0x6c:
if (len == 4) {
xga->accel.mask_map_origin_x_off = val & 0xffff;
xga->accel.mask_map_origin_y_off = (val >> 16) & 0xffff;
} else if (len == 2) {
xga->accel.mask_map_origin_x_off = val;
} else
xga->accel.mask_map_origin_x_off = (xga->accel.mask_map_origin_x_off & 0xff00) | val;
break;
case 0x6d:
if (len == 1)
xga->accel.mask_map_origin_x_off = (xga->accel.mask_map_origin_x_off & 0xff) | (val << 8);
break;
case 0x6e:
if (len == 2)
xga->accel.mask_map_origin_y_off = val;
else
xga->accel.mask_map_origin_y_off = (xga->accel.mask_map_origin_y_off & 0xff00) | val;
break;
case 0x6f:
if (len == 1)
xga->accel.mask_map_origin_y_off = (xga->accel.mask_map_origin_y_off & 0xff) | (val << 8);
break;
case 0x70:
if (len == 4) {
xga->accel.src_map_x = val & 0xffff;
xga->accel.src_map_y = (val >> 16) & 0xffff;
} else if (len == 2)
xga->accel.src_map_x = val;
else
xga->accel.src_map_x = (xga->accel.src_map_x & 0xff00) | val;
break;
case 0x71:
if (len == 1)
xga->accel.src_map_x = (xga->accel.src_map_x & 0xff) | (val << 8);
break;
case 0x72:
if (len == 2)
xga->accel.src_map_y = val;
else
xga->accel.src_map_y = (xga->accel.src_map_y & 0xff00) | val;
break;
case 0x73:
if (len == 1)
xga->accel.src_map_y = (xga->accel.src_map_y & 0xff) | (val << 8);
break;
case 0x74:
if (len == 4) {
xga->accel.pat_map_x = val & 0xffff;
xga->accel.pat_map_y = (val >> 16) & 0xffff;
} else if (len == 2)
xga->accel.pat_map_x = val;
else
xga->accel.pat_map_x = (xga->accel.pat_map_x & 0xff00) | val;
break;
case 0x75:
if (len == 1)
xga->accel.pat_map_x = (xga->accel.pat_map_x & 0xff) | (val << 8);
break;
case 0x76:
if (len == 2)
xga->accel.pat_map_y = val;
else
xga->accel.pat_map_y = (xga->accel.pat_map_y & 0xff00) | val;
break;
case 0x77:
if (len == 1)
xga->accel.pat_map_y = (xga->accel.pat_map_y & 0xff) | (val << 8);
break;
case 0x78:
if (len == 4) {
xga->accel.dst_map_x = val & 0xffff;
xga->accel.dst_map_y = (val >> 16) & 0xffff;
} else if (len == 2)
xga->accel.dst_map_x = val;
else
xga->accel.dst_map_x = (xga->accel.dst_map_x & 0xff00) | val;
break;
case 0x79:
if (len == 1)
xga->accel.dst_map_x = (xga->accel.dst_map_x & 0xff) | (val << 8);
break;
case 0x7a:
if (len == 2)
xga->accel.dst_map_y = val;
else
xga->accel.dst_map_y = (xga->accel.dst_map_y & 0xff00) | val;
break;
case 0x7b:
if (len == 1)
xga->accel.dst_map_y = (xga->accel.dst_map_y & 0xff) | (val << 8);
break;
case 0x7c:
if (len == 4) {
xga->accel.command = val;
exec_command:
xga->accel.octant = xga->accel.command & 0x07;
xga->accel.draw_mode = xga->accel.command & 0x30;
xga->accel.pat_src = ((xga->accel.command >> 12) & 0x0f);
xga->accel.dst_map = ((xga->accel.command >> 16) & 0x0f);
xga->accel.src_map = ((xga->accel.command >> 20) & 0x0f);
#ifdef ENABLE_XGA_LOG
if (xga->accel.pat_src)
xga_log("[%04X:%08X]: Accel Command = %02x, full = %08x, patwidth = %d, "
"dstwidth = %d, srcwidth = %d, patheight = %d, dstheight = %d, "
"srcheight = %d, px = %d, py = %d, dx = %d, dy = %d, sx = %d, "
"sy = %d, patsrc = %d, dstmap = %d, srcmap = %d, dstbase = %08x, "
"srcbase = %08x, patbase = %08x, dstformat = %x, srcformat = %x, "
"planemask = %08x\n\n",
CS, cpu_state.pc, ((xga->accel.command >> 24) & 0x0f),
xga->accel.command, xga->accel.px_map_width[xga->accel.pat_src],
xga->accel.px_map_width[xga->accel.dst_map],
xga->accel.px_map_width[xga->accel.src_map],
xga->accel.px_map_height[xga->accel.pat_src],
xga->accel.px_map_height[xga->accel.dst_map],
xga->accel.px_map_height[xga->accel.src_map],
xga->accel.pat_map_x, xga->accel.pat_map_y,
xga->accel.dst_map_x, xga->accel.dst_map_y,
xga->accel.src_map_x, xga->accel.src_map_y,
xga->accel.pat_src, xga->accel.dst_map,
xga->accel.src_map, xga->accel.px_map_base[xga->accel.dst_map],
xga->accel.px_map_base[xga->accel.src_map],
xga->accel.px_map_base[xga->accel.pat_src],
xga->accel.px_map_format[xga->accel.dst_map] & 0x0f,
xga->accel.px_map_format[xga->accel.src_map] & 0x0f,
xga->accel.plane_mask);
#endif
switch ((xga->accel.command >> 24) & 0x0f) {
case 2: /*Short Stroke Vectors Read */
xga_log("Short Stroke Vectors Read.\n");
break;
case 3: /*Bresenham Line Draw Read*/
xga_log("Line Draw Read\n");
break;
case 4: /*Short Stroke Vectors Write*/
xga_log("Short Stroke Vectors Write.\n");
break;
case 5: /*Bresenham Line Draw Write*/
xga_log("Line Draw Write.\n");
xga_line_draw_write(svga);
break;
case 8: /*BitBLT*/
xga_log("BitBLT.\n");
xga_bitblt(svga);
break;
case 9: /*Inverting BitBLT*/
xga_log("Inverting BitBLT\n");
break;
case 0x0a: /*Area Fill*/
xga_log("Area Fill BitBLT.\n");
xga_bitblt(svga);
break;
default:
break;
}
} else if (len == 2) {
xga->accel.command = (xga->accel.command & 0xffff0000) | val;
} else
xga->accel.command = (xga->accel.command & 0xffffff00) | val;
break;
case 0x7d:
if (len == 1)
xga->accel.command = (xga->accel.command & 0xffff00ff) | (val << 8);
break;
case 0x7e:
if (len == 2) {
xga->accel.command = (xga->accel.command & 0x0000ffff) | (val << 16);
goto exec_command;
} else
xga->accel.command = (xga->accel.command & 0xff00ffff) | (val << 16);
break;
case 0x7f:
if (len == 1) {
xga->accel.command = (xga->accel.command & 0x00ffffff) | (val << 24);
goto exec_command;
}
break;
default:
break;
}
}
}
static void
xga_memio_writeb(uint32_t addr, uint8_t val, void *priv)
{
svga_t *svga = (svga_t *) priv;
xga_t *xga = (xga_t *) svga->xga;
xga_mem_write(addr, val, xga, svga, 1);
xga_log("Write MEMIOB = %04x, val = %02x\n", addr & 0x7f, val);
}
static void
xga_memio_writew(uint32_t addr, uint16_t val, void *priv)
{
svga_t *svga = (svga_t *) priv;
xga_t *xga = (xga_t *) svga->xga;
xga_mem_write(addr, val, xga, svga, 2);
xga_log("Write MEMIOW = %04x, val = %04x\n", addr & 0x7f, val);
}
static void
xga_memio_writel(uint32_t addr, uint32_t val, void *priv)
{
svga_t *svga = (svga_t *) priv;
xga_t *xga = (xga_t *) svga->xga;
xga_mem_write(addr, val, xga, svga, 4);
xga_log("Write MEMIOL = %04x, val = %08x\n", addr & 0x7f, val);
}
static uint8_t
xga_mem_read(uint32_t addr, xga_t *xga, UNUSED(svga_t *svga))
{
uint8_t temp = 0;
addr &= 0x1fff;
if (addr < 0x1800) {
if (xga_standalone_enabled)
temp = xga->bios_rom.rom[addr];
else
temp = xga->vga_bios_rom.rom[addr];
} else {
switch (addr & 0x7f) {
case 0x11:
temp = xga->accel.control;
if (xga->accel.control & 0x08)
temp |= 0x10;
else
temp &= ~0x10;
break;
case 0x20:
temp = xga->accel.bres_err_term & 0xff;
break;
case 0x21:
temp = xga->accel.bres_err_term >> 8;
break;
case 0x22:
temp = xga->accel.bres_err_term >> 16;
break;
case 0x23:
temp = xga->accel.bres_err_term >> 24;
break;
case 0x70:
temp = xga->accel.src_map_x & 0xff;
break;
case 0x71:
temp = xga->accel.src_map_x >> 8;
break;
case 0x72:
temp = xga->accel.src_map_y & 0xff;
break;
case 0x73:
temp = xga->accel.src_map_y >> 8;
break;
case 0x74:
temp = xga->accel.pat_map_x & 0xff;
break;
case 0x75:
temp = xga->accel.pat_map_x >> 8;
break;
case 0x76:
temp = xga->accel.pat_map_y & 0xff;
break;
case 0x77:
temp = xga->accel.pat_map_y >> 8;
break;
case 0x78:
temp = xga->accel.dst_map_x & 0xff;
break;
case 0x79:
temp = xga->accel.dst_map_x >> 8;
break;
case 0x7a:
temp = xga->accel.dst_map_y & 0xff;
break;
case 0x7b:
temp = xga->accel.dst_map_y >> 8;
break;
default:
break;
}
}
return temp;
}
static uint8_t
xga_memio_readb(uint32_t addr, void *priv)
{
svga_t *svga = (svga_t *) priv;
xga_t *xga = (xga_t *) svga->xga;
uint8_t temp;
temp = xga_mem_read(addr, xga, svga);
xga_log("[%04X:%08X]: Read MEMIOB = %04x, temp = %02x\n", CS, cpu_state.pc, addr, temp);
return temp;
}
static uint16_t
xga_memio_readw(uint32_t addr, void *priv)
{
svga_t *svga = (svga_t *) priv;
xga_t *xga = (xga_t *) svga->xga;
uint16_t temp;
temp = xga_mem_read(addr, xga, svga);
temp |= (xga_mem_read(addr + 1, xga, svga) << 8);
xga_log("[%04X:%08X]: Read MEMIOW = %04x, temp = %04x\n", CS, cpu_state.pc, addr, temp);
return temp;
}
static uint32_t
xga_memio_readl(uint32_t addr, void *priv)
{
svga_t *svga = (svga_t *) priv;
xga_t *xga = (xga_t *) svga->xga;
uint32_t temp;
temp = xga_mem_read(addr, xga, svga);
temp |= (xga_mem_read(addr + 1, xga, svga) << 8);
temp |= (xga_mem_read(addr + 2, xga, svga) << 16);
temp |= (xga_mem_read(addr + 3, xga, svga) << 24);
xga_log("[%04X:%08X]: Read MEMIOL = %04x, temp = %08x\n", CS, cpu_state.pc, addr, temp);
return temp;
}
static void
xga_hwcursor_draw(svga_t *svga, int displine)
{
xga_t *xga = (xga_t *) svga->xga;
int comb;
uint8_t dat = 0;
int offset = xga->hwcursor_latch.x - xga->hwcursor_latch.xoff;
int idx = 0;
int x_pos;
int y_pos;
uint32_t *p;
const uint8_t *cd;
if (xga->hwcursor_latch.xoff & 0x20)
idx = 32;
cd = (uint8_t *) xga->sprite_data;
if (xga->interlace && xga->hwcursor_oddeven)
xga->hwcursor_latch.addr += 16;
for (int x = 0; x < xga->hwcursor_latch.cur_xsize; x++) {
dat = cd[xga->hwcursor_latch.addr & 0x3ff];
comb = (dat >> ((x & 0x03) << 1)) & 0x03;
y_pos = displine;
x_pos = offset + svga->x_add;
p = buffer32->line[y_pos];
if (x >= idx) {
switch (comb) {
case 0x00:
/* Cursor Color 1 */
p[x_pos] = xga->hwc_color0;
break;
case 0x01:
/* Cursor Color 2 */
p[x_pos] = xga->hwc_color1;
break;
case 0x03:
/* Complement */
p[x_pos] ^= 0xffffff;
break;
default:
break;
}
}
offset++;
xga_log("P=%08x, xpos=%d, comb=%x, ypos=%d, offset=%d, latchx=%d, latchxoff=%d.\n", p[x_pos], x_pos, comb, y_pos, offset, xga->hwcursor_latch.x, xga->hwcursor_latch.xoff);
if ((x & 0x03) == 0x03)
xga->hwcursor_latch.addr++;
}
if (xga->interlace && !xga->hwcursor_oddeven)
xga->hwcursor_latch.addr += 16;
}
static void
xga_render_overscan_left(xga_t *xga, svga_t *svga)
{
if ((xga->displine + svga->y_add) < 0)
return;
if (svga->scrblank || (xga->h_disp == 0))
return;
uint32_t *line_ptr = svga->monitor->target_buffer->line[xga->displine + svga->y_add];
for (int i = 0; i < svga->x_add; i++)
*line_ptr++ = svga->overscan_color;
}
static void
xga_render_overscan_right(xga_t *xga, svga_t *svga)
{
int right;
if ((xga->displine + svga->y_add) < 0)
return;
if (svga->scrblank || (xga->h_disp == 0))
return;
uint32_t *line_ptr = &svga->monitor->target_buffer->line[xga->displine + svga->y_add][svga->x_add + xga->h_disp];
right = (overscan_x >> 1);
for (int i = 0; i < right; i++)
*line_ptr++ = svga->overscan_color;
}
static void
xga_render_4bpp(svga_t *svga)
{
xga_t *xga = (xga_t *) svga->xga;
uint32_t *p;
uint32_t dat;
if ((xga->displine + svga->y_add) < 0)
return;
if (xga->changedvram[xga->ma >> 12] || xga->changedvram[(xga->ma >> 12) + 1] || svga->fullchange) {
p = &svga->monitor->target_buffer->line[xga->displine + svga->y_add][svga->x_add];
if (xga->firstline_draw == 2000)
xga->firstline_draw = xga->displine;
xga->lastline_draw = xga->displine;
for (int x = 0; x <= xga->h_disp; x += 16) {
dat = *(uint32_t *) (&xga->vram[xga->ma & xga->vram_mask]);
p[0] = xga->pallook[dat & 0x0f];
p[1] = xga->pallook[(dat >> 4) & 0x0f];
p[2] = xga->pallook[(dat >> 8) & 0x0f];
p[3] = xga->pallook[(dat >> 12) & 0x0f];
p[4] = xga->pallook[(dat >> 16) & 0x0f];
p[5] = xga->pallook[(dat >> 20) & 0x0f];
p[6] = xga->pallook[(dat >> 24) & 0x0f];
p[7] = xga->pallook[(dat >> 28) & 0x0f];
dat = *(uint32_t *) (&xga->vram[(xga->ma + 4) & xga->vram_mask]);
p[8] = xga->pallook[dat & 0x0f];
p[9] = xga->pallook[(dat >> 4) & 0x0f];
p[10] = xga->pallook[(dat >> 8) & 0x0f];
p[11] = xga->pallook[(dat >> 12) & 0x0f];
p[12] = xga->pallook[(dat >> 16) & 0x0f];
p[13] = xga->pallook[(dat >> 20) & 0x0f];
p[14] = xga->pallook[(dat >> 24) & 0x0f];
p[15] = xga->pallook[(dat >> 28) & 0x0f];
xga->ma += 8;
p += 16;
}
xga->ma &= xga->vram_mask;
}
}
static void
xga_render_8bpp(svga_t *svga)
{
xga_t *xga = (xga_t *) svga->xga;
uint32_t *p;
uint32_t dat;
if ((xga->displine + svga->y_add) < 0)
return;
if (xga->changedvram[xga->ma >> 12] || xga->changedvram[(xga->ma >> 12) + 1] || svga->fullchange) {
p = &svga->monitor->target_buffer->line[xga->displine + svga->y_add][svga->x_add];
if (xga->firstline_draw == 2000)
xga->firstline_draw = xga->displine;
xga->lastline_draw = xga->displine;
for (int x = 0; x <= xga->h_disp; x += 8) {
dat = *(uint32_t *) (&xga->vram[xga->ma & xga->vram_mask]);
p[0] = xga->pallook[dat & 0xff];
p[1] = xga->pallook[(dat >> 8) & 0xff];
p[2] = xga->pallook[(dat >> 16) & 0xff];
p[3] = xga->pallook[(dat >> 24) & 0xff];
dat = *(uint32_t *) (&xga->vram[(xga->ma + 4) & xga->vram_mask]);
p[4] = xga->pallook[dat & 0xff];
p[5] = xga->pallook[(dat >> 8) & 0xff];
p[6] = xga->pallook[(dat >> 16) & 0xff];
p[7] = xga->pallook[(dat >> 24) & 0xff];
xga->ma += 8;
p += 8;
}
xga->ma &= xga->vram_mask;
}
}
static void
xga_render_16bpp(svga_t *svga)
{
xga_t *xga = (xga_t *) svga->xga;
int x;
uint32_t *p;
uint32_t dat;
if ((xga->displine + svga->y_add) < 0)
return;
if (xga->changedvram[xga->ma >> 12] || xga->changedvram[(xga->ma >> 12) + 1] || svga->fullchange) {
p = &svga->monitor->target_buffer->line[xga->displine + svga->y_add][svga->x_add];
if (xga->firstline_draw == 2000)
xga->firstline_draw = xga->displine;
xga->lastline_draw = xga->displine;
for (x = 0; x <= xga->h_disp; x += 8) {
dat = *(uint32_t *) (&xga->vram[(xga->ma + (x << 1)) & xga->vram_mask]);
p[x] = video_16to32[dat & 0xffff];
p[x + 1] = video_16to32[dat >> 16];
dat = *(uint32_t *) (&xga->vram[(xga->ma + (x << 1) + 4) & xga->vram_mask]);
p[x + 2] = video_16to32[dat & 0xffff];
p[x + 3] = video_16to32[dat >> 16];
dat = *(uint32_t *) (&xga->vram[(xga->ma + (x << 1) + 8) & xga->vram_mask]);
p[x + 4] = video_16to32[dat & 0xffff];
p[x + 5] = video_16to32[dat >> 16];
dat = *(uint32_t *) (&xga->vram[(xga->ma + (x << 1) + 12) & xga->vram_mask]);
p[x + 6] = video_16to32[dat & 0xffff];
p[x + 7] = video_16to32[dat >> 16];
}
xga->ma += x << 1;
xga->ma &= xga->vram_mask;
}
}
static void
xga_write(uint32_t addr, uint8_t val, void *priv)
{
svga_t *svga = (svga_t *) priv;
xga_t *xga = (xga_t *) svga->xga;
if (!xga->on) {
svga_write(addr, val, svga);
return;
}
addr &= xga->banked_mask;
addr += xga->write_bank;
if (addr >= xga->vram_size)
return;
cycles -= svga->monitor->mon_video_timing_write_b;
if (xga->access_mode & 8) {
if ((xga->access_mode & 7) == 4)
addr ^= 1;
}
xga->changedvram[(addr & xga->vram_mask) >> 12] = svga->monitor->mon_changeframecount;
xga->vram[addr & xga->vram_mask] = val;
}
static void
xga_writew(uint32_t addr, uint16_t val, void *priv)
{
svga_t *svga = (svga_t *) priv;
xga_t *xga = (xga_t *) svga->xga;
if (!xga->on) {
svga_writew(addr, val, svga);
return;
}
xga_write(addr, val & 0xff, svga);
xga_write(addr + 1, val >> 8, svga);
}
static void
xga_writel(uint32_t addr, uint32_t val, void *priv)
{
svga_t *svga = (svga_t *) priv;
xga_t *xga = (xga_t *) svga->xga;
if (!xga->on) {
svga_writel(addr, val, svga);
return;
}
xga_write(addr, val & 0xff, svga);
xga_write(addr + 1, (val >> 8) & 0xff, svga);
xga_write(addr + 2, (val >> 16) & 0xff, svga);
xga_write(addr + 3, (val >> 24) & 0xff, svga);
}
static uint8_t
xga_read(uint32_t addr, void *priv)
{
svga_t *svga = (svga_t *) priv;
xga_t *xga = (xga_t *) svga->xga;
uint8_t ret = 0xff;
if (!xga->on) {
ret = svga_read(addr, svga);
return ret;
}
addr &= xga->banked_mask;
addr += xga->read_bank;
if (addr >= xga->vram_size)
return ret;
cycles -= svga->monitor->mon_video_timing_read_b;
if (xga->access_mode & 8) {
if ((xga->access_mode & 7) == 4)
addr ^= 1;
}
ret = xga->vram[addr & xga->vram_mask];
return ret;
}
static uint16_t
xga_readw(uint32_t addr, void *priv)
{
svga_t *svga = (svga_t *) priv;
xga_t *xga = (xga_t *) svga->xga;
uint16_t ret = 0xffff;
if (!xga->on) {
ret = svga_readw(addr, svga);
return ret;
}
ret = xga_read(addr, svga);
ret |= (xga_read(addr + 1, svga) << 8);
return ret;
}
static uint32_t
xga_readl(uint32_t addr, void *priv)
{
svga_t *svga = (svga_t *) priv;
xga_t *xga = (xga_t *) svga->xga;
uint32_t ret = 0xffffffff;
if (!xga->on) {
ret = svga_readl(addr, svga);
return ret;
}
ret = xga_read(addr, svga);
ret |= (xga_read(addr + 1, svga) << 8);
ret |= (xga_read(addr + 2, svga) << 16);
ret |= (xga_read(addr + 3, svga) << 24);
return ret;
}
static void
xga_write_linear(uint32_t addr, uint8_t val, void *priv)
{
svga_t *svga = (svga_t *) priv;
xga_t *xga = (xga_t *) svga->xga;
if (!xga->on) {
svga_write_linear(addr, val, svga);
return;
}
addr &= svga->decode_mask;
if (addr >= xga->vram_size)
return;
cycles -= svga->monitor->mon_video_timing_write_b;
if (xga->linear_endian_reverse) {
if ((xga->access_mode & 7) == 4) {
if ((xga->accel.px_map_format[xga->accel.dst_map] & 7) == 4)
addr ^= 1;
} else if (xga->access_mode & 8) {
if ((xga->accel.px_map_format[xga->accel.dst_map] & 7) == 4)
addr ^= 1;
}
}
xga->changedvram[(addr & xga->vram_mask) >> 12] = svga->monitor->mon_changeframecount;
xga->vram[addr & xga->vram_mask] = val;
}
static void
xga_writew_linear(uint32_t addr, uint16_t val, void *priv)
{
svga_t *svga = (svga_t *) priv;
const xga_t *xga = (xga_t *) svga->xga;
if (!xga->on) {
svga_writew_linear(addr, val, svga);
return;
}
xga_write_linear(addr, val, priv);
xga_write_linear(addr + 1, val >> 8, priv);
}
static void
xga_writel_linear(uint32_t addr, uint32_t val, void *priv)
{
svga_t *svga = (svga_t *) priv;
const xga_t *xga = (xga_t *) svga->xga;
if (!xga->on) {
svga_writel_linear(addr, val, svga);
return;
}
xga_write_linear(addr, val, priv);
xga_write_linear(addr + 1, val >> 8, priv);
xga_write_linear(addr + 2, val >> 16, priv);
xga_write_linear(addr + 3, val >> 24, priv);
}
static uint8_t
xga_read_linear(uint32_t addr, void *priv)
{
svga_t *svga = (svga_t *) priv;
const xga_t *xga = (xga_t *) svga->xga;
uint8_t ret = 0xff;
if (!xga->on)
return svga_read_linear(addr, svga);
addr &= svga->decode_mask;
if (addr >= xga->vram_size)
return ret;
cycles -= svga->monitor->mon_video_timing_read_b;
if (xga->linear_endian_reverse) {
if ((xga->access_mode & 7) == 4) {
if ((xga->accel.px_map_format[xga->accel.dst_map] & 7) == 4)
addr ^= 1;
} else if (xga->access_mode & 8) {
if ((xga->accel.px_map_format[xga->accel.dst_map] & 7) == 4)
addr ^= 1;
}
}
return xga->vram[addr & xga->vram_mask];
}
static uint16_t
xga_readw_linear(uint32_t addr, void *priv)
{
svga_t *svga = (svga_t *) priv;
const xga_t *xga = (xga_t *) svga->xga;
uint16_t ret;
if (!xga->on)
return svga_readw_linear(addr, svga);
ret = xga_read_linear(addr, svga);
ret |= (xga_read_linear(addr + 1, svga) << 8);
return ret;
}
static uint32_t
xga_readl_linear(uint32_t addr, void *priv)
{
svga_t *svga = (svga_t *) priv;
const xga_t *xga = (xga_t *) svga->xga;
uint32_t ret;
if (!xga->on)
return svga_readl_linear(addr, svga);
ret = xga_read_linear(addr, svga);
ret |= (xga_read_linear(addr + 1, svga) << 8);
ret |= (xga_read_linear(addr + 2, svga) << 16);
ret |= (xga_read_linear(addr + 3, svga) << 24);
return ret;
}
static void
xga_do_render(svga_t *svga)
{
xga_t *xga = (xga_t *) svga->xga;
xga_log("DISPCNTL = %d, vga = %d.\n", xga->disp_cntl_2 & 7, vga_on);
switch (xga->disp_cntl_2 & 7) {
case 2:
xga_render_4bpp(svga);
break;
case 3:
xga_render_8bpp(svga);
break;
case 4:
xga_render_16bpp(svga);
break;
default:
break;
}
svga->x_add = (overscan_x >> 1);
xga_render_overscan_left(xga, svga);
xga_render_overscan_right(xga, svga);
svga->x_add = (overscan_x >> 1);
if (xga->hwcursor_on) {
xga_hwcursor_draw(svga, xga->displine + svga->y_add);
xga->hwcursor_on--;
if (xga->hwcursor_on && xga->interlace)
xga->hwcursor_on--;
}
}
void
xga_poll(void *priv, svga_t *svga)
{
xga_t *xga = (xga_t *) priv;
uint32_t x;
int wx;
int wy;
if (!xga->linepos) {
if (xga->displine == xga->hwcursor_latch.y && xga->hwcursor_latch.ena) {
xga->hwcursor_on = xga->hwcursor_latch.cur_ysize - ((xga->hwcursor_latch.yoff & 0x20) ? 32 : 0);
xga->hwcursor_oddeven = 0;
}
if (xga->displine == (xga->hwcursor_latch.y + 1) && xga->hwcursor_latch.ena && xga->interlace) {
xga->hwcursor_on = xga->hwcursor_latch.cur_ysize - ((xga->hwcursor_latch.yoff & 0x20) ? 33 : 1);
xga->hwcursor_oddeven = 1;
}
timer_advance_u64(&svga->timer, svga->dispofftime);
xga->linepos = 1;
if (xga->dispon) {
xga->h_disp_on = 1;
xga->ma &= xga->vram_mask;
if (xga->firstline == 2000) {
xga->firstline = xga->displine;
video_wait_for_buffer_monitor(svga->monitor_index);
}
if (xga->hwcursor_on)
xga->changedvram[xga->ma >> 12] = xga->changedvram[(xga->ma >> 12) + 1] = xga->interlace ? 3 : 2;
xga_do_render(svga);
if (xga->lastline < xga->displine)
xga->lastline = xga->displine;
}
xga->displine++;
if (xga->interlace)
xga->displine++;
if (xga->displine > 1500)
xga->displine = 0;
} else {
timer_advance_u64(&svga->timer, svga->dispontime);
xga->h_disp_on = 0;
xga->linepos = 0;
if (xga->dispon) {
if (xga->sc == xga->rowcount) {
xga->sc = 0;
xga->maback += (xga->rowoffset << 3);
if (xga->interlace)
xga->maback += (xga->rowoffset << 3);
xga->maback &= xga->vram_mask;
xga->ma = xga->maback;
} else {
xga->sc++;
xga->sc &= 0x1f;
xga->ma = xga->maback;
}
}
xga->vc++;
xga->vc &= 0x7ff;
if (xga->vc == xga->split) {
if (xga->interlace && xga->oddeven)
xga->ma = xga->maback = (xga->rowoffset << 1);
else
xga->ma = xga->maback = 0;
xga->ma = (xga->ma << 2);
xga->maback = (xga->maback << 2);
xga->sc = 0;
}
if (xga->vc == xga->dispend) {
xga->dispon = 0;
for (x = 0; x < ((xga->vram_mask + 1) >> 12); x++) {
if (xga->changedvram[x])
xga->changedvram[x]--;
}
if (svga->fullchange)
svga->fullchange--;
}
if (xga->vc == xga->v_syncstart) {
xga->dispon = 0;
x = xga->h_disp;
if (xga->interlace && !xga->oddeven)
xga->lastline++;
if (xga->interlace && xga->oddeven)
xga->firstline--;
wx = x;
wy = xga->lastline - xga->firstline;
svga_doblit(wx, wy, svga);
xga->firstline = 2000;
xga->lastline = 0;
xga->firstline_draw = 2000;
xga->lastline_draw = 0;
xga->oddeven ^= 1;
svga->monitor->mon_changeframecount = xga->interlace ? 3 : 2;
if (xga->interlace && xga->oddeven)
xga->ma = xga->maback = xga->ma_latch + (xga->rowoffset << 1);
else
xga->ma = xga->maback = xga->ma_latch;
xga->ma = (xga->ma << 2);
xga->maback = (xga->maback << 2);
}
if (xga->vc == xga->v_total) {
xga->vc = 0;
xga->sc = 0;
xga->dispon = 1;
xga->displine = (xga->interlace && xga->oddeven) ? 1 : 0;
svga->x_add = (overscan_x >> 1);
xga->hwcursor_on = 0;
xga->hwcursor_latch = xga->hwcursor;
}
}
}
static uint8_t
xga_mca_read(int port, void *priv)
{
const svga_t *svga = (svga_t *) priv;
const xga_t *xga = (xga_t *) svga->xga;
uint8_t ret = xga->pos_regs[port & 7];
if (((port & 7) == 3) && !(ret & 1)) /*Always enable the mapping.*/
ret |= 1;
xga_log("[%04X:%08X]: POS Read Port = %x, val = %02x\n", CS, cpu_state.pc,
port & 7, xga->pos_regs[port & 7]);
return ret;
}
static void
xga_mca_write(int port, uint8_t val, void *priv)
{
svga_t *svga = (svga_t *) priv;
xga_t *xga = (xga_t *) svga->xga;
/* MCA does not write registers below 0x0100. */
if (port < 0x0102)
return;
io_removehandler(0x2100 + (xga->instance << 4), 0x0010, xga_ext_inb, NULL, NULL, xga_ext_outb, NULL, NULL, svga);
mem_mapping_disable(&xga->bios_rom.mapping);
mem_mapping_disable(&xga->memio_mapping);
xga->on = 0;
vga_on = 1;
xga->linear_endian_reverse = 0;
xga->a5_test = 0;
/* Save the MCA register value. */
xga->pos_regs[port & 7] = val;
if (!(xga->pos_regs[4] & 1) && (mem_size >= 16384)) /*MCA 4MB addressing on systems with more than 16MB of memory*/
xga->pos_regs[4] |= 1;
if (xga->pos_regs[2] & 1) {
xga->instance = (xga->pos_regs[2] & 0x0e) >> 1;
xga->base_addr_1mb = (xga->pos_regs[5] & 0x0f) << 20;
xga->linear_base = ((xga->pos_regs[4] & 0xfe) * 0x1000000) + (xga->instance << 22);
xga->rom_addr = 0xc0000 + (((xga->pos_regs[2] & 0xf0) >> 4) * 0x2000);
io_sethandler(0x2100 + (xga->instance << 4), 0x0010, xga_ext_inb, NULL, NULL, xga_ext_outb, NULL, NULL, svga);
if (xga->pos_regs[3] & 1)
mem_mapping_set_addr(&xga->bios_rom.mapping, xga->rom_addr, 0x2000);
else
mem_mapping_set_addr(&xga->memio_mapping, xga->rom_addr + 0x1c00 + (xga->instance * 0x80), 0x80);
}
xga_log("[%04X:%08X]: POS Write Port = %x, val = %02x, linear base = %08x, instance = %d, "
"rom addr = %05x\n", CS, cpu_state.pc, port & 7, val, xga->linear_base,
xga->instance, xga->rom_addr);
}
static uint8_t
xga_mca_feedb(void *priv)
{
const svga_t *svga = (svga_t *) priv;
const xga_t *xga = (xga_t *) svga->xga;
return xga->pos_regs[2] & 1;
}
static void
xga_mca_reset(void *priv)
{
svga_t *svga = (svga_t *) priv;
xga_t *xga = (xga_t *) svga->xga;
mem_mapping_disable(&xga->bios_rom.mapping);
mem_mapping_disable(&xga->memio_mapping);
xga->on = 0;
vga_on = 1;
xga_mca_write(0x102, 0, svga);
xga->linear_endian_reverse = 0;
xga->a5_test = 0;
}
static void
xga_reset(void *priv)
{
svga_t *svga = (svga_t *) priv;
xga_t *xga = (xga_t *) svga->xga;
mem_mapping_disable(&xga->bios_rom.mapping);
mem_mapping_disable(&xga->memio_mapping);
xga->on = 0;
vga_on = 1;
xga->linear_endian_reverse = 0;
xga->a5_test = 0;
}
static uint8_t
xga_pos_in(uint16_t addr, void *priv)
{
svga_t *svga = (svga_t *) priv;
xga_t *xga = (xga_t *) svga->xga;
uint8_t ret = 0xff;
if (!xga_standalone_enabled) {
switch (addr) {
case 0x0100:
case 0x0101:
if (xga->instance_isa == xga->instance_num)
ret = xga->pos_regs[addr & 7];
else
ret = 0xff;
break;
case 0x0102:
case 0x0105:
ret = xga->pos_regs[addr & 7];
break;
case 0x0106:
ret = xga->pos_idx >> 8;
break;
case 0x0107:
ret = xga->pos_idx & 0xff;
break;
case 0x0103:
if (!(xga->pos_idx & 3))
ret = xga->pos_regs[3];
else
ret = 0;
xga_log("POS IDX for 0103 = %d, ret = %02x.\n", xga->pos_idx & 3, ret);
break;
case 0x0104:
switch (xga->pos_idx & 3) {
case 0:
ret = xga->pos_regs[4];
break;
case 1:
ret = xga->pos_regs[0];
break;
case 2:
ret = xga->pos_regs[1];
break;
case 3:
ret = 0;
break;
default:
break;
}
xga_log("POS IDX for 0104 = %d, ret = %02x.\n", xga->pos_idx & 3, ret);
break;
case 0x0108:
case 0x0109:
case 0x010a:
case 0x010b:
case 0x010c:
case 0x010d:
case 0x010e:
case 0x010f:
xga->instance_num = addr & 7;
if (xga->instance_isa == xga->instance_num)
ret = xga->instance_isa;
else
ret = 0;
ret |= xga->isa_pos_enable;
break;
default:
break;
}
} else {
switch (addr) {
case 0x0100:
case 0x0101:
ret = xga->pos_regs[addr & 7];
break;
case 0x0103:
ret = xga->pos_regs[3] | 7;
ret |= (xga->dma_channel << 3);
break;
case 0x0102:
case 0x0104:
case 0x0105:
case 0x0106:
case 0x0107:
ret = (xga_mca_read(addr, svga));
break;
case 0x0108:
case 0x0109:
case 0x010a:
case 0x010b:
case 0x010c:
case 0x010d:
case 0x010e:
case 0x010f:
xga->instance_num = addr & 7;
if (xga->instance_isa == xga->instance_num)
ret = xga->instance_isa;
else
ret = 0;
ret |= xga->isa_pos_enable;
break;
default:
break;
}
}
return ret;
}
static void
xga_pos_out(uint16_t addr, uint8_t val, void *priv)
{
svga_t *svga = (svga_t *) priv;
xga_t *xga = (xga_t *) svga->xga;
if (!xga_standalone_enabled) {
switch (addr) {
case 0x0106:
xga->pos_idx = (xga->pos_idx & 0x00ff) | (val << 8);
break;
case 0x0107:
xga->pos_idx = (xga->pos_idx & 0xff00) | val;
xga_log("POS IDX Write = %04x.\n", xga->pos_idx);
break;
case 0x0108:
case 0x0109:
case 0x010a:
case 0x010b:
case 0x010c:
case 0x010d:
case 0x010e:
case 0x010f:
xga->instance_num = addr & 7;
xga->isa_pos_enable = val & 0x08;
break;
default:
break;
}
} else {
switch (addr) {
case 0x0108:
case 0x0109:
case 0x010a:
case 0x010b:
case 0x010c:
case 0x010d:
case 0x010e:
case 0x010f:
xga->instance_num = addr & 7;
xga->isa_pos_enable = val & 0x08;
break;
default:
break;
}
}
}
static void *
xga_init(const device_t *info)
{
if (svga_get_pri() == NULL)
return NULL;
svga_t *svga = svga_get_pri();
xga_t *xga = (xga_t *) calloc(1, sizeof(xga_t));
FILE *fp;
uint8_t *rom = NULL;
svga->xga = xga;
xga->ext_mem_addr = device_get_config_hex16("ext_mem_addr");
xga->instance_isa = device_get_config_int("instance");
xga->type = device_get_config_int("type");
xga->dma_channel = device_get_config_int("dma");
xga->bus = info->flags;
xga->vram_size = (1024 << 10);
xga->vram_mask = xga->vram_size - 1;
xga->vram = calloc(xga->vram_size, 1);
xga->changedvram = calloc((xga->vram_size >> 12) + 1, 1);
xga->on = 0;
xga->hwcursor.cur_xsize = 64;
xga->hwcursor.cur_ysize = 64;
xga->bios_rom.sz = 0x2000;
xga->linear_endian_reverse = 0;
xga->a5_test = 0;
fp = rom_fopen(xga->type ? XGA2_BIOS_PATH : XGA_BIOS_PATH, "rb");
(void) fseek(fp, 0L, SEEK_END);
(void) fseek(fp, 0L, SEEK_SET);
rom = malloc(xga->bios_rom.sz);
memset(rom, 0xff, xga->bios_rom.sz);
(void) !fread(rom, xga->bios_rom.sz, 1, fp);
(void) fclose(fp);
xga->bios_rom.rom = rom;
xga->bios_rom.mask = xga->bios_rom.sz - 1;
if (fp != NULL) {
free(rom);
}
xga->base_addr_1mb = 0;
if (info->flags & DEVICE_MCA) {
video_inform(VIDEO_FLAG_TYPE_SPECIAL, &timing_xga_mca);
xga->linear_base = 0;
xga->instance = 0;
xga->rom_addr = 0;
rom_init(&xga->bios_rom, xga->type ? XGA2_BIOS_PATH : XGA_BIOS_PATH, 0xc0000, 0x2000, 0x1fff, 0, MEM_MAPPING_EXTERNAL);
} else {
if (!xga_standalone_enabled)
rom_init(&xga->vga_bios_rom, INMOS_XGA_BIOS_PATH, 0xc0000, 0x8000, 0x7fff, 0, MEM_MAPPING_EXTERNAL);
else
video_inform(VIDEO_FLAG_TYPE_SPECIAL, &timing_xga_isa);
xga->pos_regs[2] = 1 | (xga->instance_isa << 1) | xga->ext_mem_addr;
xga->instance = (xga->pos_regs[2] & 0x0e) >> 1;
xga->pos_regs[4] = 1 | 2;
xga->linear_base = ((xga->pos_regs[4] & 0xfe) * 0x1000000) + (xga->instance << 22);
xga->rom_addr = 0xc0000 + (((xga->pos_regs[2] & 0xf0) >> 4) * 0x2000);
}
mem_mapping_add(&xga->video_mapping, 0, 0, xga_read, xga_readw, xga_readl,
xga_write, xga_writew, xga_writel,
NULL, MEM_MAPPING_EXTERNAL, svga);
mem_mapping_add(&xga->linear_mapping, 0, 0, xga_read_linear, xga_readw_linear, xga_readl_linear,
xga_write_linear, xga_writew_linear, xga_writel_linear,
NULL, MEM_MAPPING_EXTERNAL, svga);
mem_mapping_add(&xga->memio_mapping, 0, 0, xga_memio_readb, xga_memio_readw, xga_memio_readl,
xga_memio_writeb, xga_memio_writew, xga_memio_writel,
!xga_standalone_enabled ? xga->vga_bios_rom.rom : xga->bios_rom.rom, MEM_MAPPING_EXTERNAL, svga);
mem_mapping_disable(&xga->linear_mapping);
mem_mapping_disable(&xga->memio_mapping);
xga->pos_regs[0] = xga->type ? 0xda : 0xdb;
xga->pos_regs[1] = 0x8f;
if (xga->bus & DEVICE_MCA) {
mca_add(xga_mca_read, xga_mca_write, xga_mca_feedb, xga_mca_reset, svga);
} else {
io_sethandler(0x0100, 0x0008, xga_pos_in, NULL, NULL, NULL, NULL, NULL, svga);
if (!xga_standalone_enabled)
io_sethandler(0x0106, 0x0002, NULL, NULL, NULL, xga_pos_out, NULL, NULL, svga);
io_sethandler(0x2100 + (xga->instance << 4), 0x0010, xga_ext_inb, NULL, NULL, xga_ext_outb, NULL, NULL, svga);
io_sethandler(0x0108, 0x0008, xga_pos_in, NULL, NULL, xga_pos_out, NULL, NULL, svga);
mem_mapping_set_addr(&xga->memio_mapping, xga->rom_addr + 0x1c00 + (xga->instance * 0x80), 0x80);
}
return svga;
}
static void *
svga_xga_init(const device_t *info)
{
svga_t *svga = (svga_t *) calloc(1, sizeof(svga_t));
video_inform(VIDEO_FLAG_TYPE_XGA, &timing_xga_isa);
svga_init(info, svga, svga, 1 << 18, /*256kB*/
NULL,
svga_xga_in, svga_xga_out,
NULL,
NULL);
io_sethandler(0x03c0, 0x0020, svga_xga_in, NULL, NULL, svga_xga_out, NULL, NULL, svga);
svga->bpp = 8;
svga->miscout = 1;
xga_active = 1;
return xga_init(info);
}
static void
xga_close(void *priv)
{
svga_t *svga = (svga_t *) priv;
xga_t *xga = (xga_t *) svga->xga;
if (svga) {
free(xga->vram);
free(xga->changedvram);
free(xga);
}
}
static int
xga_available(void)
{
return rom_present(XGA_BIOS_PATH) && rom_present(XGA2_BIOS_PATH);
}
static int
inmos_xga_available(void)
{
return rom_present(INMOS_XGA_BIOS_PATH);
}
static void
xga_speed_changed(void *priv)
{
svga_t *svga = (svga_t *) priv;
svga_recalctimings(svga);
}
static void
xga_force_redraw(void *priv)
{
svga_t *svga = (svga_t *) priv;
svga->fullchange = svga->monitor->mon_changeframecount;
}
static const device_config_t xga_mca_configuration[] = {
// clang-format off
{
.name = "type",
.description = "XGA type",
.type = CONFIG_SELECTION,
.default_string = "",
.default_int = 0,
.file_filter = "",
.spinner = { 0 },
.selection = {
{
.description = "XGA-1",
.value = 0
},
{
.description = "XGA-2",
.value = 1
},
{ .description = "" }
}
},
{ .name = "", .description = "", .type = CONFIG_END }
// clang-format on
};
static const device_config_t xga_isa_configuration[] = {
// clang-format off
{
.name = "type",
.description = "XGA type",
.type = CONFIG_SELECTION,
.default_string = "",
.default_int = 0,
.file_filter = "",
.spinner = { 0 },
.selection = {
{
.description = "XGA-1",
.value = 0
},
{
.description = "XGA-2",
.value = 1
},
{ .description = "" }
}
},
{
.name = "instance",
.description = "Instance",
.type = CONFIG_SELECTION,
.default_string = "",
.default_int = 6,
.file_filter = "",
.spinner = { 0 },
.selection = {
{ .description = "0 (2100h-210Fh)", .value = 0 },
{ .description = "1 (2110h-211Fh)", .value = 1 },
{ .description = "2 (2120h-212Fh)", .value = 2 },
{ .description = "3 (2130h-213Fh)", .value = 3 },
{ .description = "4 (2140h-214Fh)", .value = 4 },
{ .description = "5 (2150h-215Fh)", .value = 5 },
{ .description = "6 (2160h-216Fh)", .value = 6 },
{ .description = "7 (2170h-217Fh)", .value = 7 },
{ .description = "" }
},
},
{
.name = "ext_mem_addr",
.description = "MMIO address",
.type = CONFIG_HEX16,
.default_string = "",
.default_int = 0x00f0,
.file_filter = "",
.spinner = { 0 },
.selection = {
{ .description = "C800h", .value = 0x0040 },
{ .description = "CA00h", .value = 0x0050 },
{ .description = "CC00h", .value = 0x0060 },
{ .description = "CE00h", .value = 0x0070 },
{ .description = "D000h", .value = 0x0080 },
{ .description = "D200h", .value = 0x0090 },
{ .description = "D400h", .value = 0x00a0 },
{ .description = "D600h", .value = 0x00b0 },
{ .description = "D800h", .value = 0x00c0 },
{ .description = "DA00h", .value = 0x00d0 },
{ .description = "DC00h", .value = 0x00e0 },
{ .description = "DE00h", .value = 0x00f0 },
{ .description = "" }
},
},
{
.name = "dma",
.description = "DMA channel",
.type = CONFIG_SELECTION,
.default_string = "",
.default_int = 7,
.file_filter = "",
.spinner = { 0 },
.selection = {
{ .description = "Disabled", .value = 0 },
{ .description = "DMA 6", .value = 6 },
{ .description = "DMA 7", .value = 7 },
{ .description = "" }
},
},
{ .name = "", .description = "", .type = CONFIG_END }
// clang-format on
};
const device_t xga_device = {
.name = "XGA (MCA)",
.internal_name = "xga_mca",
.flags = DEVICE_MCA,
.local = 0,
.init = xga_init,
.close = xga_close,
.reset = xga_reset,
{ .available = xga_available },
.speed_changed = xga_speed_changed,
.force_redraw = xga_force_redraw,
.config = xga_mca_configuration
};
const device_t xga_isa_device = {
.name = "XGA (ISA)",
.internal_name = "xga_isa",
.flags = DEVICE_ISA | DEVICE_AT,
.local = 0,
.init = xga_init,
.close = xga_close,
.reset = xga_reset,
{ .available = xga_available },
.speed_changed = xga_speed_changed,
.force_redraw = xga_force_redraw,
.config = xga_isa_configuration
};
const device_t inmos_isa_device = {
.name = "INMOS XGA (ISA)",
.internal_name = "inmos_xga_isa",
.flags = DEVICE_ISA | DEVICE_AT,
.local = 0,
.init = svga_xga_init,
.close = xga_close,
.reset = xga_reset,
{ .available = inmos_xga_available },
.speed_changed = xga_speed_changed,
.force_redraw = xga_force_redraw,
.config = xga_isa_configuration
};
void
xga_device_add(void)
{
if (!xga_standalone_enabled)
return;
if (machine_has_bus(machine, MACHINE_BUS_MCA))
device_add(&xga_device);
else
device_add(&xga_isa_device);
}
``` | /content/code_sandbox/src/video/vid_xga.c | c | 2016-06-25T22:29:10 | 2024-08-16T19:09:21 | 86Box | 86Box/86Box | 2,616 | 40,712 |
```c
/*
* 86Box A hypervisor and IBM PC system emulator that specializes in
* running old operating systems and software designed for IBM
* PC systems and compatibles from 1981 through fairly recent
* system designs based on the PCI bus.
*
* This file is part of the 86Box distribution.
*
* Define all known video cards.
*
*
*
* Authors: Miran Grca, <mgrca8@gmail.com>
* Fred N. van Kempen, <decwiz@yahoo.com>
*
*/
#include <stdarg.h>
#include <stdint.h>
#include <stdio.h>
#include <stdlib.h>
#include <string.h>
#include <wchar.h>
#define HAVE_STDARG_H
#include <86box/86box.h>
#include <86box/timer.h>
#include <86box/machine.h>
#include <86box/mem.h>
#include <86box/device.h>
#include <86box/plat.h>
#include <86box/video.h>
#include <86box/vid_svga.h>
#include <86box/vid_cga.h>
#include <86box/vid_ega.h>
#include <86box/vid_colorplus.h>
#include <86box/vid_mda.h>
#include <86box/vid_xga_device.h>
typedef struct video_card_t {
const device_t *device;
int flags;
} VIDEO_CARD;
static video_timings_t timing_default = { .type = VIDEO_ISA, .write_b = 8, .write_w = 16, .write_l = 32, .read_b = 8, .read_w = 16, .read_l = 32 };
static int was_reset = 0;
static const VIDEO_CARD
video_cards[] = {
// clang-format off
{ &device_none },
{ &device_internal },
{ &atiega800p_device },
{ &mach8_vga_isa_device, VIDEO_FLAG_TYPE_8514 },
{ &mach32_isa_device, VIDEO_FLAG_TYPE_8514 },
{ &mach64gx_isa_device },
{ &ati28800k_device },
{ &ati18800_vga88_device },
{ &ati28800_device },
{ &compaq_ati28800_device },
#ifdef USE_XL24
{ &ati28800_wonderxl24_device },
#endif /* USE_XL24 */
{ &ati18800_device },
{ &ati18800_wonder_device },
{ &cga_device },
{ &sega_device },
{ &gd5401_isa_device },
{ &gd5402_isa_device },
{ &gd5420_isa_device },
{ &gd5422_isa_device },
{ &gd5426_isa_device },
{ &gd5426_diamond_speedstar_pro_a1_isa_device },
{ &gd5428_boca_isa_device },
{ &gd5428_isa_device },
{ &gd5429_isa_device },
{ &gd5434_isa_device },
{ &gd5434_diamond_speedstar_64_a3_isa_device },
{ &compaq_cga_device },
{ &compaq_cga_2_device },
{ &cpqega_device },
{ &ega_device },
{ &g2_gc205_device },
{ &hercules_device, VIDEO_FLAG_TYPE_MDA },
{ &herculesplus_device, VIDEO_FLAG_TYPE_MDA },
{ &incolor_device },
{ &inmos_isa_device, VIDEO_FLAG_TYPE_XGA },
{ &im1024_device },
{ &iskra_ega_device },
{ &et4000_kasan_isa_device },
{ &mda_device, VIDEO_FLAG_TYPE_MDA },
{ &genius_device },
{ &nga_device },
{ &ogc_device },
{ &oti037c_device },
{ &oti067_device },
{ &oti077_device },
{ ¶dise_pvga1a_device },
{ ¶dise_wd90c11_device },
{ ¶dise_wd90c30_device },
{ &colorplus_device },
{ &pgc_device },
{ &cga_pravetz_device },
{ &radius_svga_multiview_isa_device },
{ &realtek_rtg3105_device },
{ &realtek_rtg3106_device },
{ &s3_diamond_stealth_vram_isa_device },
{ &s3_orchid_86c911_isa_device },
{ &s3_ami_86c924_isa_device },
{ &s3_metheus_86c928_isa_device },
{ &s3_phoenix_86c801_isa_device },
{ &s3_spea_mirage_86c801_isa_device },
{ &sigma_device },
{ &tvga8900b_device },
{ &tvga8900d_device },
{ &tvga8900dr_device },
{ &tvga9000b_device },
{ &nec_sv9000_device },
{ &et4000k_isa_device },
{ &et2000_device },
{ &et3000_isa_device },
{ &et4000_tc6058af_isa_device },
{ &et4000_isa_device },
{ &et4000w32_device },
{ &et4000w32i_isa_device },
{ &vga_device },
{ &v7_vga_1024i_device },
{ &wy700_device },
{ &mach32_mca_device, VIDEO_FLAG_TYPE_8514 },
{ &gd5426_mca_device },
{ &gd5428_mca_device },
{ &et4000_mca_device },
{ &radius_svga_multiview_mca_device },
{ &mach32_pci_device, VIDEO_FLAG_TYPE_8514 },
{ &mach64gx_pci_device },
{ &mach64vt2_device },
{ &bochs_svga_device },
{ &chips_69000_device },
{ &gd5430_pci_device, },
{ &gd5434_pci_device },
{ &gd5436_pci_device, VIDEO_FLAG_TYPE_SPECIAL },
{ &gd5440_pci_device },
{ &gd5446_pci_device, VIDEO_FLAG_TYPE_SPECIAL },
{ &gd5446_stb_pci_device, VIDEO_FLAG_TYPE_SPECIAL },
{ &gd5480_pci_device },
{ &et4000w32p_videomagic_revb_pci_device },
{ &et4000w32p_revc_pci_device },
{ &et4000w32p_cardex_pci_device },
{ &et4000w32p_noncardex_pci_device },
{ &et4000w32p_pci_device },
{ &s3_spea_mercury_lite_86c928_pci_device },
{ &s3_diamond_stealth64_964_pci_device },
{ &s3_elsa_winner2000_pro_x_964_pci_device },
{ &s3_mirocrystal_20sv_964_pci_device },
{ &s3_bahamas64_pci_device },
{ &s3_phoenix_vision864_pci_device },
{ &s3_diamond_stealth_se_pci_device },
{ &s3_phoenix_trio32_pci_device },
{ &s3_diamond_stealth64_pci_device },
{ &s3_9fx_pci_device },
{ &s3_phoenix_trio64_pci_device },
{ &s3_diamond_stealth64_968_pci_device },
{ &s3_elsa_winner2000_pro_x_pci_device },
{ &s3_mirovideo_40sv_ergo_968_pci_device },
{ &s3_9fx_771_pci_device },
{ &s3_phoenix_vision968_pci_device },
{ &s3_spea_mercury_p64v_pci_device },
{ &s3_9fx_531_pci_device },
{ &s3_phoenix_vision868_pci_device },
{ &s3_cardex_trio64vplus_pci_device },
{ &s3_phoenix_trio64vplus_pci_device },
{ &s3_trio64v2_dx_pci_device },
{ &s3_virge_325_pci_device },
{ &s3_diamond_stealth_2000_pci_device },
{ &s3_diamond_stealth_3000_pci_device },
{ &s3_stb_velocity_3d_pci_device },
{ &s3_virge_375_pci_device },
{ &s3_diamond_stealth_2000pro_pci_device },
{ &s3_virge_385_pci_device },
{ &s3_virge_357_pci_device },
{ &s3_diamond_stealth_4000_pci_device },
{ &s3_trio3d2x_pci_device },
{ &millennium_device },
{ &millennium_ii_device },
{ &mystique_device },
{ &mystique_220_device },
{ &tgui9440_pci_device },
{ &tgui9660_pci_device },
{ &tgui9680_pci_device },
{ &voodoo_banshee_device },
{ &creative_voodoo_banshee_device },
{ &voodoo_3_1000_device },
{ &voodoo_3_2000_device },
{ &voodoo_3_3000_device },
{ &mach32_vlb_device, VIDEO_FLAG_TYPE_8514 },
{ &mach64gx_vlb_device },
{ &et4000w32i_vlb_device },
{ &et4000w32p_videomagic_revb_vlb_device },
{ &et4000w32p_revc_vlb_device },
{ &et4000w32p_cardex_vlb_device },
{ &et4000w32p_vlb_device },
{ &et4000w32p_noncardex_vlb_device },
{ &gd5424_vlb_device },
{ &gd5426_vlb_device },
{ &gd5428_vlb_device },
{ &gd5428_diamond_speedstar_pro_b1_vlb_device },
{ &gd5429_vlb_device },
{ &gd5430_diamond_speedstar_pro_se_a8_vlb_device },
{ &gd5430_vlb_device },
{ &gd5434_vlb_device },
{ &s3_metheus_86c928_vlb_device },
{ &s3_mirocrystal_8s_805_vlb_device },
{ &s3_mirocrystal_10sd_805_vlb_device },
{ &s3_phoenix_86c805_vlb_device },
{ &s3_spea_mirage_86c805_vlb_device },
{ &s3_diamond_stealth64_964_vlb_device },
{ &s3_mirocrystal_20sv_964_vlb_device },
{ &s3_mirocrystal_20sd_864_vlb_device },
{ &s3_bahamas64_vlb_device },
{ &s3_phoenix_vision864_vlb_device },
{ &s3_diamond_stealth_se_vlb_device },
{ &s3_phoenix_trio32_vlb_device },
{ &s3_diamond_stealth64_vlb_device },
{ &s3_9fx_vlb_device },
{ &s3_phoenix_trio64_vlb_device },
{ &s3_spea_mirage_p64_vlb_device },
{ &s3_diamond_stealth64_968_vlb_device },
{ &s3_stb_powergraph_64_video_vlb_device },
{ &ht216_32_standalone_device },
{ &tgui9400cxi_device },
{ &tgui9440_vlb_device },
{ &s3_virge_357_agp_device },
{ &s3_diamond_stealth_4000_agp_device },
{ &s3_trio3d2x_agp_device },
#ifdef USE_G100
{ &productiva_g100_device, VIDEO_FLAG_TYPE_SPECIAL },
#endif /*USE_G100 */
{ &velocity_100_agp_device },
{ &velocity_200_agp_device },
{ &voodoo_3_1000_agp_device },
{ &voodoo_3_2000_agp_device },
{ &voodoo_3_3000_agp_device },
{ &voodoo_3_3500_agp_ntsc_device },
{ &voodoo_3_3500_agp_pal_device },
{ &compaq_voodoo_3_3500_agp_device },
{ &voodoo_3_3500_se_agp_device },
{ &voodoo_3_3500_si_agp_device },
{ NULL }
// clang-format on
};
#ifdef ENABLE_VID_TABLE_LOG
int vid_table_do_log = ENABLE_VID_TABLE_LOG;
static void
vid_table_log(const char *fmt, ...)
{
va_list ap;
if (vid_table_do_log) {
va_start(ap, fmt);
pclog_ex(fmt, ap);
va_end(ap);
}
}
#else
# define vid_table_log(fmt, ...)
#endif
void
video_reset_close(void)
{
for (int i = 1; i < MONITORS_NUM; i++)
video_monitor_close(i);
monitor_index_global = 0;
video_inform(VIDEO_FLAG_TYPE_NONE, &timing_default);
was_reset = 0;
}
static void
video_prepare(void)
{
/* Reset (deallocate) the video font arrays. */
if (fontdatksc5601) {
free(fontdatksc5601);
fontdatksc5601 = NULL;
}
/* Reset the blend. */
herc_blend = 0;
for (int i = 0; i < MONITORS_NUM; i++) {
/* Reset the CGA palette. */
if (monitors[i].mon_cga_palette)
*monitors[i].mon_cga_palette = 0;
cgapal_rebuild_monitor(i);
/* Do an inform on the default values, so that that there's some sane values initialized
even if the device init function does not do an inform of its own. */
video_inform_monitor(VIDEO_FLAG_TYPE_SPECIAL, &timing_default, i);
}
}
void
video_pre_reset(int card)
{
if ((card == VID_NONE) || (card == VID_INTERNAL) || machine_has_flags(machine, MACHINE_VIDEO_ONLY))
video_prepare();
}
void
video_reset(int card)
{
/* This is needed to avoid duplicate resets. */
if ((video_get_type() != VIDEO_FLAG_TYPE_NONE) && was_reset)
return;
vid_table_log("VIDEO: reset (gfxcard[0]=%d, internal=%d)\n",
card, machine_has_flags(machine, MACHINE_VIDEO) ? 1 : 0);
monitor_index_global = 0;
loadfont("roms/video/mda/mda.rom", 0);
for (uint8_t i = 1; i < GFXCARD_MAX; i ++) {
if ((card != VID_NONE) && !machine_has_flags(machine, MACHINE_VIDEO_ONLY) &&
(gfxcard[i] > VID_INTERNAL) && device_is_valid(video_card_getdevice(gfxcard[i]), machine)) {
video_monitor_init(i);
monitor_index_global = 1;
device_add(video_cards[gfxcard[i]].device);
monitor_index_global = 0;
}
}
/* Do not initialize internal cards here. */
if ((card > VID_INTERNAL) && !machine_has_flags(machine, MACHINE_VIDEO_ONLY)) {
vid_table_log("VIDEO: initializing '%s'\n", video_cards[card].device->name);
video_prepare();
/* Initialize the video card. */
device_add(video_cards[card].device);
}
was_reset = 1;
}
void
video_post_reset(void)
{
int ibm8514_has_vga = 0;
if (gfxcard[0] == VID_INTERNAL)
ibm8514_has_vga = (video_get_type_monitor(0) == VIDEO_FLAG_TYPE_8514);
else if (gfxcard[0] != VID_NONE)
ibm8514_has_vga = (video_card_get_flags(gfxcard[0]) == VIDEO_FLAG_TYPE_8514);
else
ibm8514_has_vga = 0;
if (ibm8514_has_vga)
ibm8514_active = 1;
if (ibm8514_standalone_enabled)
ibm8514_device_add();
if (xga_standalone_enabled)
xga_device_add();
/* Reset the graphics card (or do nothing if it was already done
by the machine's init function). */
video_reset(gfxcard[0]);
}
void
video_voodoo_init(void)
{
/* Enable the Voodoo if configured. */
if (voodoo_enabled)
device_add(&voodoo_device);
}
int
video_card_available(int card)
{
if (video_cards[card].device)
return (device_available(video_cards[card].device));
return 1;
}
int
video_card_get_flags(int card)
{
return video_cards[card].flags;
}
const device_t *
video_card_getdevice(int card)
{
return (video_cards[card].device);
}
int
video_card_has_config(int card)
{
if (video_cards[card].device == NULL)
return 0;
return (device_has_config(video_cards[card].device) ? 1 : 0);
}
const char *
video_get_internal_name(int card)
{
return device_get_internal_name(video_cards[card].device);
}
int
video_get_video_from_internal_name(char *s)
{
int c = 0;
while (video_cards[c].device != NULL) {
if (!strcmp(video_cards[c].device->internal_name, s))
return c;
c++;
}
return 0;
}
int
video_is_mda(void)
{
return (video_get_type() == VIDEO_FLAG_TYPE_MDA);
}
int
video_is_cga(void)
{
return (video_get_type() == VIDEO_FLAG_TYPE_CGA);
}
int
video_is_ega_vga(void)
{
return (video_get_type() == VIDEO_FLAG_TYPE_SPECIAL);
}
int
video_is_8514(void)
{
return (video_get_type() == VIDEO_FLAG_TYPE_8514);
}
int
video_is_xga(void)
{
return (video_get_type() == VIDEO_FLAG_TYPE_XGA);
}
``` | /content/code_sandbox/src/video/vid_table.c | c | 2016-06-25T22:29:10 | 2024-08-16T19:09:21 | 86Box | 86Box/86Box | 2,616 | 4,239 |
```c
/*
* 86Box A hypervisor and IBM PC system emulator that specializes in
* running old operating systems and software designed for IBM
* PC systems and compatibles from 1981 through fairly recent
* system designs based on the PCI bus.
*
* This file is part of the 86Box distribution.
*
* EGA renderers.
*
*
*
* Authors: Sarah Walker, <path_to_url
* Miran Grca, <mgrca8@gmail.com>
*
*/
#include <stdio.h>
#include <stdint.h>
#include <stdbool.h>
#include <string.h>
#include <wchar.h>
#include <86box/86box.h>
#include <86box/device.h>
#include <86box/timer.h>
#include <86box/mem.h>
#include <86box/rom.h>
#include <86box/video.h>
#include <86box/vid_ega.h>
#include <86box/vid_ega_render_remap.h>
int
ega_display_line(ega_t *ega)
{
int y_add = enable_overscan ? (overscan_y >> 1) : 0;
unsigned int dl = ega->displine;
if (ega->crtc[9] & 0x1f)
dl -= (ega->crtc[8] & 0x1f);
dl += y_add;
dl &= 0x7ff;
return dl;
}
void
ega_render_blank(ega_t *ega)
{
if ((ega->displine + ega->y_add) < 0)
return;
for (int x = 0; x < (ega->hdisp + ega->scrollcache); x++) {
switch (ega->seqregs[1] & 9) {
case 0:
for (uint8_t xx = 0; xx < 9; xx++)
buffer32->line[ega->displine + ega->y_add][ega->x_add + (x * 9) + xx] = 0;
break;
case 1:
for (uint8_t xx = 0; xx < 8; xx++)
buffer32->line[ega->displine + ega->y_add][ega->x_add + (x * 8) + xx] = 0;
break;
case 8:
for (uint8_t xx = 0; xx < 18; xx++)
buffer32->line[ega->displine + ega->y_add][ega->x_add + (x * 18) + xx] = 0;
break;
case 9:
for (uint8_t xx = 0; xx < 16; xx++)
buffer32->line[ega->displine + ega->y_add][ega->x_add + (x * 16) + xx] = 0;
break;
default:
break;
}
}
}
void
ega_render_overscan_left(ega_t *ega)
{
if ((ega->displine + ega->y_add) < 0)
return;
if (ega->scrblank || (ega->hdisp == 0))
return;
for (int i = 0; i < ega->x_add; i++)
buffer32->line[ega->displine + ega->y_add][i] = ega->overscan_color;
}
void
ega_render_overscan_right(ega_t *ega)
{
int right;
if ((ega->displine + ega->y_add) < 0)
return;
if (ega->scrblank || (ega->hdisp == 0))
return;
right = (overscan_x >> 1) + ega->scrollcache;
for (int i = 0; i < right; i++)
buffer32->line[ega->displine + ega->y_add][ega->x_add + ega->hdisp + i] = ega->overscan_color;
}
void
ega_render_text(ega_t *ega)
{
if ((ega->displine + ega->y_add) < 0)
return;
if (ega->firstline_draw == 2000)
ega->firstline_draw = ega->displine;
ega->lastline_draw = ega->displine;
if (ega->fullchange) {
const bool doublewidth = ((ega->seqregs[1] & 8) != 0);
const bool attrblink = ((ega->attrregs[0x10] & 8) != 0);
const bool attrlinechars = (ega->attrregs[0x10] & 4);
const bool crtcreset = ((ega->crtc[0x17] & 0x80) == 0);
const bool seq9dot = ((ega->seqregs[1] & 1) == 0);
const int dwshift = doublewidth ? 1 : 0;
const int dotwidth = 1 << dwshift;
const int charwidth = dotwidth * (seq9dot ? 9 : 8);
const bool blinked = ega->blink & 0x10;
uint32_t *p = &buffer32->line[ega->displine + ega->y_add][ega->x_add];
/* Compensate for 8dot scroll */
if (!seq9dot) {
for (int x = 0; x < dotwidth; x++) {
p[x] = ega->overscan_color;
}
p += dotwidth;
}
for (int x = 0; x < (ega->hdisp + ega->scrollcache); x += charwidth) {
uint32_t addr = ega->remap_func(ega, ega->ma) & ega->vrammask;
int drawcursor = ((ega->ma == ega->ca) && ega->con && ega->cursoron);
uint32_t chr;
uint32_t attr;
if (!crtcreset) {
chr = ega->vram[addr];
attr = ega->vram[addr + 1];
} else
chr = attr = 0;
uint32_t charaddr;
if (attr & 8)
charaddr = ega->charsetb + (chr * 0x80);
else
charaddr = ega->charseta + (chr * 0x80);
int fg;
int bg;
if (drawcursor) {
bg = ega->pallook[ega->egapal[attr & 0x0f]];
fg = ega->pallook[ega->egapal[attr >> 4]];
} else {
fg = ega->pallook[ega->egapal[attr & 0x0f]];
bg = ega->pallook[ega->egapal[attr >> 4]];
if ((attr & 0x80) && attrblink) {
bg = ega->pallook[ega->egapal[(attr >> 4) & 7]];
if (blinked)
fg = bg;
}
}
uint32_t dat = ega->vram[charaddr + (ega->sc << 2)];
dat <<= 1;
if ((chr & ~0x1F) == 0xC0 && attrlinechars)
dat |= (dat >> 1) & 1;
for (int xx = 0; xx < charwidth; xx++)
p[xx] = (dat & (0x100 >> (xx >> dwshift))) ? fg : bg;
ega->ma += 4;
p += charwidth;
}
ega->ma &= 0x3ffff;
}
}
void
ega_render_graphics(ega_t *ega)
{
if ((ega->displine + ega->y_add) < 0)
return;
if (ega->firstline_draw == 2000)
ega->firstline_draw = ega->displine;
ega->lastline_draw = ega->displine;
const bool doublewidth = ((ega->seqregs[1] & 8) != 0);
const bool cga2bpp = ((ega->gdcreg[5] & 0x20) != 0);
const bool attrblink = ((ega->attrregs[0x10] & 8) != 0);
const bool blinked = ega->blink & 0x10;
const bool crtcreset = ((ega->crtc[0x17] & 0x80) == 0);
const bool seq9dot = ((ega->seqregs[1] & 1) == 0);
const bool seqoddeven = ((ega->seqregs[1] & 4) != 0);
const uint8_t blinkmask = (attrblink ? 0x8 : 0x0);
const uint8_t blinkval = (attrblink && blinked ? 0x8 : 0x0);
uint32_t *p = &buffer32->line[ega->displine + ega->y_add][ega->x_add];
const int dwshift = doublewidth ? 1 : 0;
const int dotwidth = 1 << dwshift;
const int charwidth = dotwidth * 8;
int secondcclk = 0;
/* Compensate for 8dot scroll */
if (!seq9dot) {
for (int x = 0; x < dotwidth; x++) {
p[x] = ega->overscan_color;
}
p += dotwidth;
}
for (int x = 0; x <= (ega->hdisp + ega->scrollcache); x += charwidth) {
uint32_t addr = ega->remap_func(ega, ega->ma) & ega->vrammask;
uint8_t edat[4];
if (seqoddeven) {
// FIXME: Verify the behaviour of planes 1,3 on actual hardware
edat[0] = ega->vram[(addr | 0) ^ secondcclk];
edat[1] = ega->vram[(addr | 1) ^ secondcclk];
edat[2] = ega->vram[(addr | 2) ^ secondcclk];
edat[3] = ega->vram[(addr | 3) ^ secondcclk];
secondcclk = (secondcclk + 1) & 1;
if (secondcclk == 0)
ega->ma += 4;
} else {
*(uint32_t *) (&edat[0]) = *(uint32_t *) (&ega->vram[addr]);
ega->ma += 4;
}
ega->ma &= 0x3ffff;
if (cga2bpp) {
// Remap CGA 2bpp-chunky data into fully planar data
uint8_t dat0 = egaremap2bpp[edat[1]] | (egaremap2bpp[edat[0]] << 4);
uint8_t dat1 = egaremap2bpp[edat[1] >> 1] | (egaremap2bpp[edat[0] >> 1] << 4);
uint8_t dat2 = egaremap2bpp[edat[3]] | (egaremap2bpp[edat[2]] << 4);
uint8_t dat3 = egaremap2bpp[edat[3] >> 1] | (egaremap2bpp[edat[2] >> 1] << 4);
edat[0] = dat0;
edat[1] = dat1;
edat[2] = dat2;
edat[3] = dat3;
}
if (!crtcreset) {
for (int i = 0; i < 8; i += 2) {
const int outoffs = i << dwshift;
const int inshift = 6 - i;
uint8_t dat = (edatlookup[(edat[0] >> inshift) & 3][(edat[1] >> inshift) & 3])
| (edatlookup[(edat[2] >> inshift) & 3][(edat[3] >> inshift) & 3] << 2);
// FIXME: Confirm blink behaviour is actually XOR on real hardware
uint32_t c0 = (dat >> 4) & 0xF;
uint32_t c1 = dat & 0xF;
c0 = ((c0 & ega->plane_mask & ~blinkmask) |
((c0 | ~ega->plane_mask) & blinkmask & blinkval)) ^ blinkmask;
c1 = ((c1 & ega->plane_mask & ~blinkmask) |
((c1 | ~ega->plane_mask) & blinkmask & blinkval)) ^ blinkmask;
uint32_t p0 = ega->pallook[ega->egapal[c0]];
uint32_t p1 = ega->pallook[ega->egapal[c1]];
for (int subx = 0; subx < dotwidth; subx++)
p[outoffs + subx] = p0;
for (int subx = 0; subx < dotwidth; subx++)
p[outoffs + subx + dotwidth] = p1;
}
} else
memset(p, 0x00, charwidth * sizeof(uint32_t));
p += charwidth;
}
}
``` | /content/code_sandbox/src/video/vid_ega_render.c | c | 2016-06-25T22:29:10 | 2024-08-16T19:09:21 | 86Box | 86Box/86Box | 2,616 | 3,057 |
```c
/*
* 86Box A hypervisor and IBM PC system emulator that specializes in
* running old operating systems and software designed for IBM
* PC systems and compatibles from 1981 through fairly recent
* system designs based on the PCI bus.
*
* This file is part of the 86Box distribution.
*
* Main video-rendering module.
*
* Video timing settings -
*
* 8-bit - 1mb/sec
* B = 8 ISA clocks
* W = 16 ISA clocks
* L = 32 ISA clocks
*
* Slow 16-bit - 2mb/sec
* B = 6 ISA clocks
* W = 8 ISA clocks
* L = 16 ISA clocks
*
* Fast 16-bit - 4mb/sec
* B = 3 ISA clocks
* W = 3 ISA clocks
* L = 6 ISA clocks
*
* Slow VLB/PCI - 8mb/sec (ish)
* B = 4 bus clocks
* W = 8 bus clocks
* L = 16 bus clocks
*
* Mid VLB/PCI -
* B = 4 bus clocks
* W = 5 bus clocks
* L = 10 bus clocks
*
* Fast VLB/PCI -
* B = 3 bus clocks
* W = 3 bus clocks
* L = 4 bus clocks
*
*
*
* Authors: Sarah Walker, <path_to_url
* Miran Grca, <mgrca8@gmail.com>
*
*/
#include <stdatomic.h>
#define PNG_DEBUG 0
#include <png.h>
#include <stdarg.h>
#include <stdio.h>
#include <stdint.h>
#include <string.h>
#include <stdlib.h>
#include <wchar.h>
#include <math.h>
#define HAVE_STDARG_H
#include <86box/86box.h>
#include "cpu.h"
#include <86box/device.h>
#include <86box/io.h>
#include <86box/mem.h>
#include <86box/rom.h>
#include <86box/config.h>
#include <86box/timer.h>
#include <86box/path.h>
#include <86box/plat.h>
#include <86box/ui.h>
#include <86box/thread.h>
#include <86box/video.h>
#include <86box/vid_svga.h>
#include <minitrace/minitrace.h>
volatile int screenshots = 0;
uint8_t edatlookup[4][4];
uint8_t egaremap2bpp[256];
uint8_t fontdat[2048][8]; /* IBM CGA font */
uint8_t fontdatm[2048][16]; /* IBM MDA font */
uint8_t fontdat2[2048][8]; /* IBM CGA 2nd instance font */
uint8_t fontdatm2[2048][16]; /* IBM MDA 2nd instance font */
uint8_t fontdatw[512][32]; /* Wyse700 font */
uint8_t fontdat8x12[256][16]; /* MDSI Genius font */
uint8_t fontdat12x18[256][36]; /* IM1024 font */
dbcs_font_t *fontdatksc5601 = NULL; /* Korean KSC-5601 font */
dbcs_font_t *fontdatksc5601_user = NULL; /* Korean KSC-5601 user defined font */
int herc_blend = 0;
int frames = 0;
int fullchange = 0;
int video_grayscale = 0;
int video_graytype = 0;
int monitor_index_global = 0;
uint32_t *video_6to8 = NULL;
uint32_t *video_8togs = NULL;
uint32_t *video_8to32 = NULL;
uint32_t *video_15to32 = NULL;
uint32_t *video_16to32 = NULL;
monitor_t monitors[MONITORS_NUM];
monitor_settings_t monitor_settings[MONITORS_NUM];
atomic_bool doresize_monitors[MONITORS_NUM];
#ifdef _WIN32
void * (*__cdecl video_copy)(void *_Dst, const void *_Src, size_t _Size) = memcpy;
#else
void *(*video_copy)(void *__restrict, const void *__restrict, size_t);
#endif
PALETTE cgapal = {
{0,0,0}, {0,42,0}, {42,0,0}, {42,21,0},
{0,0,0}, {0,42,42}, {42,0,42}, {42,42,42},
{0,0,0}, {21,63,21}, {63,21,21}, {63,63,21},
{0,0,0}, {21,63,63}, {63,21,63}, {63,63,63},
{0,0,0}, {0,0,42}, {0,42,0}, {0,42,42},
{42,0,0}, {42,0,42}, {42,21,00}, {42,42,42},
{21,21,21}, {21,21,63}, {21,63,21}, {21,63,63},
{63,21,21}, {63,21,63}, {63,63,21}, {63,63,63},
{0,0,0}, {0,21,0}, {0,0,42}, {0,42,42},
{42,0,21}, {21,10,21}, {42,0,42}, {42,0,63},
{21,21,21}, {21,63,21}, {42,21,42}, {21,63,63},
{63,0,0}, {42,42,0}, {63,21,42}, {41,41,41},
{0,0,0}, {0,42,42}, {42,0,0}, {42,42,42},
{0,0,0}, {0,42,42}, {42,0,0}, {42,42,42},
{0,0,0}, {0,63,63}, {63,0,0}, {63,63,63},
{0,0,0}, {0,63,63}, {63,0,0}, {63,63,63},
};
PALETTE cgapal_mono[6] = {
{ /* 0 - green, 4-color-optimized contrast. */
{0x00,0x00,0x00},{0x00,0x0d,0x03},{0x01,0x17,0x05},
{0x01,0x1a,0x06},{0x02,0x28,0x09},{0x02,0x2c,0x0a},
{0x03,0x39,0x0d},{0x03,0x3c,0x0e},{0x00,0x07,0x01},
{0x01,0x13,0x04},{0x01,0x1f,0x07},{0x01,0x23,0x08},
{0x02,0x31,0x0b},{0x02,0x35,0x0c},{0x05,0x3f,0x11},{0x0d,0x3f,0x17},
},
{ /* 1 - green, 16-color-optimized contrast. */
{0x00,0x00,0x00},{0x00,0x0d,0x03},{0x01,0x15,0x05},
{0x01,0x17,0x05},{0x01,0x21,0x08},{0x01,0x24,0x08},
{0x02,0x2e,0x0b},{0x02,0x31,0x0b},{0x01,0x22,0x08},
{0x02,0x28,0x09},{0x02,0x30,0x0b},{0x02,0x32,0x0c},
{0x03,0x39,0x0d},{0x03,0x3b,0x0e},{0x09,0x3f,0x14},{0x0d,0x3f,0x17},
},
{ /* 2 - amber, 4-color-optimized contrast. */
{0x00,0x00,0x00},{0x15,0x05,0x00},{0x20,0x0b,0x00},
{0x24,0x0d,0x00},{0x33,0x18,0x00},{0x37,0x1b,0x00},
{0x3f,0x26,0x01},{0x3f,0x2b,0x06},{0x0b,0x02,0x00},
{0x1b,0x08,0x00},{0x29,0x11,0x00},{0x2e,0x14,0x00},
{0x3b,0x1e,0x00},{0x3e,0x21,0x00},{0x3f,0x32,0x0a},{0x3f,0x38,0x0d},
},
{ /* 3 - amber, 16-color-optimized contrast. */
{0x00,0x00,0x00},{0x15,0x05,0x00},{0x1e,0x09,0x00},
{0x21,0x0b,0x00},{0x2b,0x12,0x00},{0x2f,0x15,0x00},
{0x38,0x1c,0x00},{0x3b,0x1e,0x00},{0x2c,0x13,0x00},
{0x32,0x17,0x00},{0x3a,0x1e,0x00},{0x3c,0x1f,0x00},
{0x3f,0x27,0x01},{0x3f,0x2a,0x04},{0x3f,0x36,0x0c},{0x3f,0x38,0x0d},
},
{ /* 4 - grey, 4-color-optimized contrast. */
{0x00,0x00,0x00},{0x0e,0x0f,0x10},{0x15,0x17,0x18},
{0x18,0x1a,0x1b},{0x24,0x25,0x25},{0x27,0x28,0x28},
{0x33,0x34,0x32},{0x37,0x38,0x35},{0x09,0x0a,0x0b},
{0x11,0x12,0x13},{0x1c,0x1e,0x1e},{0x20,0x22,0x22},
{0x2c,0x2d,0x2c},{0x2f,0x30,0x2f},{0x3c,0x3c,0x38},{0x3f,0x3f,0x3b},
},
{ /* 5 - grey, 16-color-optimized contrast. */
{0x00,0x00,0x00},{0x0e,0x0f,0x10},{0x13,0x14,0x15},
{0x15,0x17,0x18},{0x1e,0x20,0x20},{0x20,0x22,0x22},
{0x29,0x2a,0x2a},{0x2c,0x2d,0x2c},{0x1f,0x21,0x21},
{0x23,0x25,0x25},{0x2b,0x2c,0x2b},{0x2d,0x2e,0x2d},
{0x34,0x35,0x33},{0x37,0x37,0x34},{0x3e,0x3e,0x3a},{0x3f,0x3f,0x3b},
}
};
const uint32_t shade[5][256] = {
{0}, // RGB Color (unused)
{0}, // RGB Grayscale (unused)
{ // Amber monitor
0x000000, 0x060000, 0x090000, 0x0d0000, 0x100000, 0x120100, 0x150100, 0x170100, 0x1a0100, 0x1c0100, 0x1e0200, 0x210200, 0x230200, 0x250300, 0x270300, 0x290300,
0x2b0400, 0x2d0400, 0x2f0400, 0x300500, 0x320500, 0x340500, 0x360600, 0x380600, 0x390700, 0x3b0700, 0x3d0700, 0x3f0800, 0x400800, 0x420900, 0x440900, 0x450a00,
0x470a00, 0x480b00, 0x4a0b00, 0x4c0c00, 0x4d0c00, 0x4f0d00, 0x500d00, 0x520e00, 0x530e00, 0x550f00, 0x560f00, 0x581000, 0x591000, 0x5b1100, 0x5c1200, 0x5e1200,
0x5f1300, 0x601300, 0x621400, 0x631500, 0x651500, 0x661600, 0x671600, 0x691700, 0x6a1800, 0x6c1800, 0x6d1900, 0x6e1a00, 0x701a00, 0x711b00, 0x721c00, 0x741c00,
0x751d00, 0x761e00, 0x781e00, 0x791f00, 0x7a2000, 0x7c2000, 0x7d2100, 0x7e2200, 0x7f2300, 0x812300, 0x822400, 0x832500, 0x842600, 0x862600, 0x872700, 0x882800,
0x8a2900, 0x8b2900, 0x8c2a00, 0x8d2b00, 0x8e2c00, 0x902c00, 0x912d00, 0x922e00, 0x932f00, 0x953000, 0x963000, 0x973100, 0x983200, 0x993300, 0x9b3400, 0x9c3400,
0x9d3500, 0x9e3600, 0x9f3700, 0xa03800, 0xa23900, 0xa33a00, 0xa43a00, 0xa53b00, 0xa63c00, 0xa73d00, 0xa93e00, 0xaa3f00, 0xab4000, 0xac4000, 0xad4100, 0xae4200,
0xaf4300, 0xb14400, 0xb24500, 0xb34600, 0xb44700, 0xb54800, 0xb64900, 0xb74a00, 0xb94a00, 0xba4b00, 0xbb4c00, 0xbc4d00, 0xbd4e00, 0xbe4f00, 0xbf5000, 0xc05100,
0xc15200, 0xc25300, 0xc45400, 0xc55500, 0xc65600, 0xc75700, 0xc85800, 0xc95900, 0xca5a00, 0xcb5b00, 0xcc5c00, 0xcd5d00, 0xce5e00, 0xcf5f00, 0xd06000, 0xd26101,
0xd36201, 0xd46301, 0xd56401, 0xd66501, 0xd76601, 0xd86701, 0xd96801, 0xda6901, 0xdb6a01, 0xdc6b01, 0xdd6c01, 0xde6d01, 0xdf6e01, 0xe06f01, 0xe17001, 0xe27201,
0xe37301, 0xe47401, 0xe57501, 0xe67602, 0xe77702, 0xe87802, 0xe97902, 0xeb7a02, 0xec7b02, 0xed7c02, 0xee7e02, 0xef7f02, 0xf08002, 0xf18103, 0xf28203, 0xf38303,
0xf48403, 0xf58503, 0xf68703, 0xf78803, 0xf88903, 0xf98a04, 0xfa8b04, 0xfb8c04, 0xfc8d04, 0xfd8f04, 0xfe9005, 0xff9105, 0xff9205, 0xff9305, 0xff9405, 0xff9606,
0xff9706, 0xff9806, 0xff9906, 0xff9a07, 0xff9b07, 0xff9d07, 0xff9e08, 0xff9f08, 0xffa008, 0xffa109, 0xffa309, 0xffa409, 0xffa50a, 0xffa60a, 0xffa80a, 0xffa90b,
0xffaa0b, 0xffab0c, 0xffac0c, 0xffae0d, 0xffaf0d, 0xffb00e, 0xffb10e, 0xffb30f, 0xffb40f, 0xffb510, 0xffb610, 0xffb811, 0xffb912, 0xffba12, 0xffbb13, 0xffbd14,
0xffbe14, 0xffbf15, 0xffc016, 0xffc217, 0xffc317, 0xffc418, 0xffc619, 0xffc71a, 0xffc81b, 0xffca1c, 0xffcb1d, 0xffcc1e, 0xffcd1f, 0xffcf20, 0xffd021, 0xffd122,
0xffd323, 0xffd424, 0xffd526, 0xffd727, 0xffd828, 0xffd92a, 0xffdb2b, 0xffdc2c, 0xffdd2e, 0xffdf2f, 0xffe031, 0xffe133, 0xffe334, 0xffe436, 0xffe538, 0xffe739
},
{ // Green monitor
0x000000, 0x000400, 0x000700, 0x000900, 0x000b00, 0x000d00, 0x000f00, 0x001100, 0x001300, 0x001500, 0x001600, 0x001800, 0x001a00, 0x001b00, 0x001d00, 0x001e00,
0x002000, 0x002100, 0x002300, 0x002400, 0x002601, 0x002701, 0x002901, 0x002a01, 0x002b01, 0x002d01, 0x002e01, 0x002f01, 0x003101, 0x003201, 0x003301, 0x003401,
0x003601, 0x003702, 0x003802, 0x003902, 0x003b02, 0x003c02, 0x003d02, 0x003e02, 0x004002, 0x004102, 0x004203, 0x004303, 0x004403, 0x004503, 0x004703, 0x004803,
0x004903, 0x004a03, 0x004b04, 0x004c04, 0x004d04, 0x004e04, 0x005004, 0x005104, 0x005205, 0x005305, 0x005405, 0x005505, 0x005605, 0x005705, 0x005806, 0x005906,
0x005a06, 0x005b06, 0x005d06, 0x005e07, 0x005f07, 0x006007, 0x006107, 0x006207, 0x006308, 0x006408, 0x006508, 0x006608, 0x006708, 0x006809, 0x006909, 0x006a09,
0x006b09, 0x016c0a, 0x016d0a, 0x016e0a, 0x016f0a, 0x01700b, 0x01710b, 0x01720b, 0x01730b, 0x01740c, 0x01750c, 0x01760c, 0x01770c, 0x01780d, 0x01790d, 0x017a0d,
0x017b0d, 0x017b0e, 0x017c0e, 0x017d0e, 0x017e0f, 0x017f0f, 0x01800f, 0x018110, 0x028210, 0x028310, 0x028410, 0x028511, 0x028611, 0x028711, 0x028812, 0x028912,
0x028a12, 0x028a13, 0x028b13, 0x028c13, 0x028d14, 0x028e14, 0x038f14, 0x039015, 0x039115, 0x039215, 0x039316, 0x039416, 0x039417, 0x039517, 0x039617, 0x039718,
0x049818, 0x049918, 0x049a19, 0x049b19, 0x049c19, 0x049c1a, 0x049d1a, 0x049e1b, 0x059f1b, 0x05a01b, 0x05a11c, 0x05a21c, 0x05a31c, 0x05a31d, 0x05a41d, 0x06a51e,
0x06a61e, 0x06a71f, 0x06a81f, 0x06a920, 0x06aa20, 0x07aa21, 0x07ab21, 0x07ac21, 0x07ad22, 0x07ae22, 0x08af23, 0x08b023, 0x08b024, 0x08b124, 0x08b225, 0x09b325,
0x09b426, 0x09b526, 0x09b527, 0x0ab627, 0x0ab728, 0x0ab828, 0x0ab929, 0x0bba29, 0x0bba2a, 0x0bbb2a, 0x0bbc2b, 0x0cbd2b, 0x0cbe2c, 0x0cbf2c, 0x0dbf2d, 0x0dc02d,
0x0dc12e, 0x0ec22e, 0x0ec32f, 0x0ec42f, 0x0fc430, 0x0fc530, 0x0fc631, 0x10c731, 0x10c832, 0x10c932, 0x11c933, 0x11ca33, 0x11cb34, 0x12cc35, 0x12cd35, 0x12cd36,
0x13ce36, 0x13cf37, 0x13d037, 0x14d138, 0x14d139, 0x14d239, 0x15d33a, 0x15d43a, 0x16d43b, 0x16d53b, 0x17d63c, 0x17d73d, 0x17d83d, 0x18d83e, 0x18d93e, 0x19da3f,
0x19db40, 0x1adc40, 0x1adc41, 0x1bdd41, 0x1bde42, 0x1cdf43, 0x1ce043, 0x1de044, 0x1ee145, 0x1ee245, 0x1fe346, 0x1fe446, 0x20e447, 0x20e548, 0x21e648, 0x22e749,
0x22e74a, 0x23e84a, 0x23e94b, 0x24ea4c, 0x25ea4c, 0x25eb4d, 0x26ec4e, 0x27ed4e, 0x27ee4f, 0x28ee50, 0x29ef50, 0x29f051, 0x2af152, 0x2bf153, 0x2cf253, 0x2cf354,
0x2df455, 0x2ef455, 0x2ff556, 0x2ff657, 0x30f758, 0x31f758, 0x32f859, 0x32f95a, 0x33fa5a, 0x34fa5b, 0x35fb5c, 0x36fc5d, 0x37fd5d, 0x38fd5e, 0x38fe5f, 0x39ff60
},
{ // White monitor
0x000000, 0x010102, 0x020203, 0x020304, 0x030406, 0x040507, 0x050608, 0x060709, 0x07080a, 0x08090c, 0x080a0d, 0x090b0e, 0x0a0c0f, 0x0b0d10, 0x0c0e11, 0x0d0f12,
0x0e1013, 0x0f1115, 0x101216, 0x111317, 0x121418, 0x121519, 0x13161a, 0x14171b, 0x15181c, 0x16191d, 0x171a1e, 0x181b1f, 0x191c20, 0x1a1d21, 0x1b1e22, 0x1c1f23,
0x1d2024, 0x1e2125, 0x1f2226, 0x202327, 0x212428, 0x222529, 0x22262b, 0x23272c, 0x24282d, 0x25292e, 0x262a2f, 0x272b30, 0x282c30, 0x292d31, 0x2a2e32, 0x2b2f33,
0x2c3034, 0x2d3035, 0x2e3136, 0x2f3237, 0x303338, 0x313439, 0x32353a, 0x33363b, 0x34373c, 0x35383d, 0x36393e, 0x373a3f, 0x383b40, 0x393c41, 0x3a3d42, 0x3b3e43,
0x3c3f44, 0x3d4045, 0x3e4146, 0x3f4247, 0x404348, 0x414449, 0x42454a, 0x43464b, 0x44474c, 0x45484d, 0x46494d, 0x474a4e, 0x484b4f, 0x484c50, 0x494d51, 0x4a4e52,
0x4b4f53, 0x4c5054, 0x4d5155, 0x4e5256, 0x4f5357, 0x505458, 0x515559, 0x52565a, 0x53575b, 0x54585b, 0x55595c, 0x565a5d, 0x575b5e, 0x585c5f, 0x595d60, 0x5a5e61,
0x5b5f62, 0x5c6063, 0x5d6164, 0x5e6265, 0x5f6366, 0x606466, 0x616567, 0x626668, 0x636769, 0x64686a, 0x65696b, 0x666a6c, 0x676b6d, 0x686c6e, 0x696d6f, 0x6a6e70,
0x6b6f70, 0x6c7071, 0x6d7172, 0x6f7273, 0x707374, 0x707475, 0x717576, 0x727677, 0x747778, 0x757879, 0x767979, 0x777a7a, 0x787b7b, 0x797c7c, 0x7a7d7d, 0x7b7e7e,
0x7c7f7f, 0x7d8080, 0x7e8181, 0x7f8281, 0x808382, 0x818483, 0x828584, 0x838685, 0x848786, 0x858887, 0x868988, 0x878a89, 0x888b89, 0x898c8a, 0x8a8d8b, 0x8b8e8c,
0x8c8f8d, 0x8d8f8e, 0x8e908f, 0x8f9190, 0x909290, 0x919391, 0x929492, 0x939593, 0x949694, 0x959795, 0x969896, 0x979997, 0x989a98, 0x999b98, 0x9a9c99, 0x9b9d9a,
0x9c9e9b, 0x9d9f9c, 0x9ea09d, 0x9fa19e, 0xa0a29f, 0xa1a39f, 0xa2a4a0, 0xa3a5a1, 0xa4a6a2, 0xa6a7a3, 0xa7a8a4, 0xa8a9a5, 0xa9aaa5, 0xaaaba6, 0xabaca7, 0xacada8,
0xadaea9, 0xaeafaa, 0xafb0ab, 0xb0b1ac, 0xb1b2ac, 0xb2b3ad, 0xb3b4ae, 0xb4b5af, 0xb5b6b0, 0xb6b7b1, 0xb7b8b2, 0xb8b9b2, 0xb9bab3, 0xbabbb4, 0xbbbcb5, 0xbcbdb6,
0xbdbeb7, 0xbebfb8, 0xbfc0b8, 0xc0c1b9, 0xc1c2ba, 0xc2c3bb, 0xc3c4bc, 0xc5c5bd, 0xc6c6be, 0xc7c7be, 0xc8c8bf, 0xc9c9c0, 0xcacac1, 0xcbcbc2, 0xccccc3, 0xcdcdc3,
0xcecec4, 0xcfcfc5, 0xd0d0c6, 0xd1d1c7, 0xd2d2c8, 0xd3d3c9, 0xd4d4c9, 0xd5d5ca, 0xd6d6cb, 0xd7d7cc, 0xd8d8cd, 0xd9d9ce, 0xdadacf, 0xdbdbcf, 0xdcdcd0, 0xdeddd1,
0xdfded2, 0xe0dfd3, 0xe1e0d4, 0xe2e1d4, 0xe3e2d5, 0xe4e3d6, 0xe5e4d7, 0xe6e5d8, 0xe7e6d9, 0xe8e7d9, 0xe9e8da, 0xeae9db, 0xebeadc, 0xecebdd, 0xedecde, 0xeeeddf,
0xefeedf, 0xf0efe0, 0xf1f0e1, 0xf2f1e2, 0xf3f2e3, 0xf4f3e3, 0xf6f3e4, 0xf7f4e5, 0xf8f5e6, 0xf9f6e7, 0xfaf7e8, 0xfbf8e9, 0xfcf9e9, 0xfdfaea, 0xfefbeb, 0xfffcec
}
};
typedef struct blit_data_struct {
int x, y, w, h;
int busy;
int buffer_in_use;
int thread_run;
int monitor_index;
thread_t *blit_thread;
event_t *wake_blit_thread;
event_t *blit_complete;
event_t *buffer_not_in_use;
} blit_data_t;
static uint32_t cga_2_table[16];
static void (*blit_func)(int x, int y, int w, int h, int monitor_index);
#ifdef ENABLE_VIDEO_LOG
int video_do_log = ENABLE_VIDEO_LOG;
static void
video_log(const char *fmt, ...)
{
va_list ap;
if (video_do_log) {
va_start(ap, fmt);
pclog_ex(fmt, ap);
va_end(ap);
}
}
#else
# define video_log(fmt, ...)
#endif
void
video_setblit(void (*blit)(int, int, int, int, int))
{
blit_func = blit;
}
void
video_blit_complete_monitor(int monitor_index)
{
blit_data_t *blit_data_ptr = monitors[monitor_index].mon_blit_data_ptr;
blit_data_ptr->buffer_in_use = 0;
thread_set_event(blit_data_ptr->buffer_not_in_use);
}
void
video_wait_for_blit_monitor(int monitor_index)
{
blit_data_t *blit_data_ptr = monitors[monitor_index].mon_blit_data_ptr;
while (blit_data_ptr->busy)
thread_wait_event(blit_data_ptr->blit_complete, -1);
thread_reset_event(blit_data_ptr->blit_complete);
}
void
video_wait_for_buffer_monitor(int monitor_index)
{
blit_data_t *blit_data_ptr = monitors[monitor_index].mon_blit_data_ptr;
while (blit_data_ptr->buffer_in_use)
thread_wait_event(blit_data_ptr->buffer_not_in_use, -1);
thread_reset_event(blit_data_ptr->buffer_not_in_use);
}
static png_structp png_ptr[MONITORS_NUM];
static png_infop info_ptr[MONITORS_NUM];
static void
video_take_screenshot_monitor(const char *fn, uint32_t *buf, int start_x, int start_y, int row_len, int monitor_index)
{
png_bytep *b_rgb = NULL;
FILE *fp = NULL;
uint32_t temp = 0x00000000;
const blit_data_t *blit_data_ptr = monitors[monitor_index].mon_blit_data_ptr;
/* create file */
fp = plat_fopen(fn, (const char *) "wb");
if (!fp) {
video_log("[video_take_screenshot] File %s could not be opened for writing", fn);
return;
}
/* initialize stuff */
png_ptr[monitor_index] = png_create_write_struct(PNG_LIBPNG_VER_STRING, NULL, NULL, NULL);
if (!png_ptr[monitor_index]) {
video_log("[video_take_screenshot] png_create_write_struct failed");
fclose(fp);
return;
}
info_ptr[monitor_index] = png_create_info_struct(png_ptr[monitor_index]);
if (!info_ptr[monitor_index]) {
video_log("[video_take_screenshot] png_create_info_struct failed");
fclose(fp);
return;
}
png_init_io(png_ptr[monitor_index], fp);
png_set_IHDR(png_ptr[monitor_index], info_ptr[monitor_index], blit_data_ptr->w, blit_data_ptr->h,
8, PNG_COLOR_TYPE_RGB, PNG_INTERLACE_NONE,
PNG_COMPRESSION_TYPE_BASE, PNG_FILTER_TYPE_BASE);
b_rgb = (png_bytep *) malloc(sizeof(png_bytep) * blit_data_ptr->h);
if (b_rgb == NULL) {
video_log("[video_take_screenshot] Unable to Allocate RGB Bitmap Memory");
fclose(fp);
return;
}
for (int y = 0; y < blit_data_ptr->h; ++y) {
b_rgb[y] = (png_byte *) malloc(png_get_rowbytes(png_ptr[monitor_index], info_ptr[monitor_index]));
for (int x = 0; x < blit_data_ptr->w; ++x) {
if (buf == NULL)
memset(&(b_rgb[y][x * 3]), 0x00, 3);
else {
temp = buf[((start_y + y) * row_len) + start_x + x];
b_rgb[y][x * 3] = (temp >> 16) & 0xff;
b_rgb[y][(x * 3) + 1] = (temp >> 8) & 0xff;
b_rgb[y][(x * 3) + 2] = temp & 0xff;
}
}
}
png_write_info(png_ptr[monitor_index], info_ptr[monitor_index]);
png_write_image(png_ptr[monitor_index], b_rgb);
png_write_end(png_ptr[monitor_index], NULL);
/* cleanup heap allocation */
for (int i = 0; i < blit_data_ptr->h; i++)
if (b_rgb[i])
free(b_rgb[i]);
if (b_rgb)
free(b_rgb);
if (fp)
fclose(fp);
}
void
video_screenshot_monitor(uint32_t *buf, int start_x, int start_y, int row_len, int monitor_index)
{
char path[1024];
char fn[256];
memset(fn, 0, sizeof(fn));
memset(path, 0, sizeof(path));
path_append_filename(path, usr_path, SCREENSHOT_PATH);
if (!plat_dir_check(path))
plat_dir_create(path);
path_slash(path);
strcat(path, "Monitor_");
snprintf(&path[strlen(path)], 42, "%d_", monitor_index + 1);
plat_tempfile(fn, NULL, ".png");
strcat(path, fn);
video_log("taking screenshot to: %s\n", path);
video_take_screenshot_monitor((const char *) path, buf, start_x, start_y, row_len, monitor_index);
png_destroy_write_struct(&png_ptr[monitor_index], &info_ptr[monitor_index]);
atomic_fetch_sub(&monitors[monitor_index].mon_screenshots, 1);
}
void
video_screenshot(uint32_t *buf, int start_x, int start_y, int row_len)
{
video_screenshot_monitor(buf, start_x, start_y, row_len, 0);
}
#ifdef _WIN32
void *__cdecl video_transform_copy(void *_Dst, const void *_Src, size_t _Size)
#else
void *
video_transform_copy(void *__restrict _Dst, const void *__restrict _Src, size_t _Size)
#endif
{
uint32_t *dest_ex = (uint32_t *) _Dst;
const uint32_t *src_ex = (const uint32_t *) _Src;
_Size /= sizeof(uint32_t);
if ((dest_ex != NULL) && (src_ex != NULL)) {
for (size_t i = 0; i < _Size; i++) {
*dest_ex = video_color_transform(*src_ex);
dest_ex++;
src_ex++;
}
}
return _Dst;
}
static void
blit_thread(void *param)
{
blit_data_t *data = param;
while (data->thread_run) {
thread_wait_event(data->wake_blit_thread, -1);
thread_reset_event(data->wake_blit_thread);
MTR_BEGIN("video", "blit_thread");
if (blit_func)
blit_func(data->x, data->y, data->w, data->h, data->monitor_index);
data->busy = 0;
MTR_END("video", "blit_thread");
thread_set_event(data->blit_complete);
}
}
void
video_blit_memtoscreen_monitor(int x, int y, int w, int h, int monitor_index)
{
MTR_BEGIN("video", "video_blit_memtoscreen");
if ((w <= 0) || (h <= 0))
return;
video_wait_for_blit_monitor(monitor_index);
monitors[monitor_index].mon_blit_data_ptr->busy = 1;
monitors[monitor_index].mon_blit_data_ptr->buffer_in_use = 1;
monitors[monitor_index].mon_blit_data_ptr->x = x;
monitors[monitor_index].mon_blit_data_ptr->y = y;
monitors[monitor_index].mon_blit_data_ptr->w = w;
monitors[monitor_index].mon_blit_data_ptr->h = h;
thread_set_event(monitors[monitor_index].mon_blit_data_ptr->wake_blit_thread);
MTR_END("video", "video_blit_memtoscreen");
}
uint8_t
pixels8(uint32_t *pixels)
{
uint8_t temp = 0;
for (uint8_t i = 0; i < 8; i++)
temp |= (!!*(pixels + i) << (i ^ 7));
return temp;
}
uint32_t
pixel_to_color(uint8_t *pixels32, uint8_t pos)
{
uint32_t temp;
temp = *(pixels32 + pos) & 0x03;
switch (temp) {
default:
case 0:
return 0x00;
case 1:
return 0x07;
case 2:
return 0x0f;
}
}
void
video_blend_monitor(int x, int y, int monitor_index)
{
uint32_t pixels32_1;
uint32_t pixels32_2;
unsigned int val1;
unsigned int val2;
static unsigned int carry = 0;
if (!herc_blend)
return;
if (!x)
carry = 0;
val1 = pixels8(&(monitors[monitor_index].target_buffer->line[y][x]));
val2 = (val1 >> 1) + carry;
carry = (val1 & 1) << 7;
pixels32_1 = cga_2_table[val1 >> 4] + cga_2_table[val2 >> 4];
pixels32_2 = cga_2_table[val1 & 0xf] + cga_2_table[val2 & 0xf];
for (uint8_t xx = 0; xx < 4; xx++) {
monitors[monitor_index].target_buffer->line[y][x + xx] = pixel_to_color((uint8_t *) &pixels32_1, xx);
monitors[monitor_index].target_buffer->line[y][x + (xx | 4)] = pixel_to_color((uint8_t *) &pixels32_2, xx);
}
}
void
video_process_8_monitor(int x, int y, int monitor_index)
{
for (int xx = 0; xx < x; xx++) {
if (monitors[monitor_index].target_buffer->line[y][xx] <= 0xff)
monitors[monitor_index].target_buffer->line[y][xx] = monitors[monitor_index].mon_pal_lookup[monitors[monitor_index].target_buffer->line[y][xx]];
else
monitors[monitor_index].target_buffer->line[y][xx] = 0x00000000;
}
}
void
cgapal_rebuild_monitor(int monitor_index)
{
int c;
uint32_t *palette_lookup = monitors[monitor_index].mon_pal_lookup;
int cga_palette_monitor = 0;
/* We cannot do this (yet) if we have not been enabled yet. */
if (video_6to8 == NULL)
return;
if (monitors[monitor_index].target_buffer == NULL || monitors[monitor_index].mon_cga_palette == NULL)
return;
cga_palette_monitor = *monitors[monitor_index].mon_cga_palette;
for (c = 0; c < 256; c++) {
palette_lookup[c] = makecol(video_6to8[cgapal[c].r],
video_6to8[cgapal[c].g],
video_6to8[cgapal[c].b]);
}
if ((cga_palette_monitor > 1) && (cga_palette_monitor < 7)) {
if (vid_cga_contrast != 0) {
for (c = 0; c < 16; c++) {
palette_lookup[c] = makecol(video_6to8[cgapal_mono[cga_palette_monitor - 2][c].r],
video_6to8[cgapal_mono[cga_palette_monitor - 2][c].g],
video_6to8[cgapal_mono[cga_palette_monitor - 2][c].b]);
palette_lookup[c + 16] = makecol(video_6to8[cgapal_mono[cga_palette_monitor - 2][c].r],
video_6to8[cgapal_mono[cga_palette_monitor - 2][c].g],
video_6to8[cgapal_mono[cga_palette_monitor - 2][c].b]);
palette_lookup[c + 32] = makecol(video_6to8[cgapal_mono[cga_palette_monitor - 2][c].r],
video_6to8[cgapal_mono[cga_palette_monitor - 2][c].g],
video_6to8[cgapal_mono[cga_palette_monitor - 2][c].b]);
palette_lookup[c + 48] = makecol(video_6to8[cgapal_mono[cga_palette_monitor - 2][c].r],
video_6to8[cgapal_mono[cga_palette_monitor - 2][c].g],
video_6to8[cgapal_mono[cga_palette_monitor - 2][c].b]);
}
} else {
for (c = 0; c < 16; c++) {
palette_lookup[c] = makecol(video_6to8[cgapal_mono[cga_palette_monitor - 1][c].r],
video_6to8[cgapal_mono[cga_palette_monitor - 1][c].g],
video_6to8[cgapal_mono[cga_palette_monitor - 1][c].b]);
palette_lookup[c + 16] = makecol(video_6to8[cgapal_mono[cga_palette_monitor - 1][c].r],
video_6to8[cgapal_mono[cga_palette_monitor - 1][c].g],
video_6to8[cgapal_mono[cga_palette_monitor - 1][c].b]);
palette_lookup[c + 32] = makecol(video_6to8[cgapal_mono[cga_palette_monitor - 1][c].r],
video_6to8[cgapal_mono[cga_palette_monitor - 1][c].g],
video_6to8[cgapal_mono[cga_palette_monitor - 1][c].b]);
palette_lookup[c + 48] = makecol(video_6to8[cgapal_mono[cga_palette_monitor - 1][c].r],
video_6to8[cgapal_mono[cga_palette_monitor - 1][c].g],
video_6to8[cgapal_mono[cga_palette_monitor - 1][c].b]);
}
}
}
if (cga_palette_monitor == 8)
palette_lookup[0x16] = makecol(video_6to8[42], video_6to8[42], video_6to8[0]);
else if (cga_palette_monitor == 10) {
/* IBM 5153 CRT, colors by VileR */
palette_lookup[0x10] = 0x00000000;
palette_lookup[0x11] = 0x000000c4;
palette_lookup[0x12] = 0x0000c400;
palette_lookup[0x13] = 0x0000c4c4;
palette_lookup[0x14] = 0x00c40000;
palette_lookup[0x15] = 0x00c400c4;
palette_lookup[0x16] = 0x00c47e00;
palette_lookup[0x17] = 0x00c4c4c4;
palette_lookup[0x18] = 0x004e4e4e;
palette_lookup[0x19] = 0x004e4edc;
palette_lookup[0x1a] = 0x004edc4e;
palette_lookup[0x1b] = 0x004ef3f3;
palette_lookup[0x1c] = 0x00dc4e4e;
palette_lookup[0x1d] = 0x00f34ef3;
palette_lookup[0x1e] = 0x00f3f34e;
palette_lookup[0x1f] = 0x00ffffff;
}
}
void
video_inform_monitor(int type, const video_timings_t *ptr, int monitor_index)
{
monitor_t *monitor = &monitors[monitor_index];
monitor->mon_vid_type = type;
monitor->mon_vid_timings = ptr;
}
int
video_get_type_monitor(int monitor_index)
{
return monitors[monitor_index].mon_vid_type;
}
void
video_update_timing(void)
{
const video_timings_t *monitor_vid_timings = NULL;
int *vid_timing_read_b = NULL;
int *vid_timing_read_l = NULL;
int *vid_timing_read_w = NULL;
int *vid_timing_write_b = NULL;
int *vid_timing_write_l = NULL;
int *vid_timing_write_w = NULL;
for (uint8_t i = 0; i < MONITORS_NUM; i++) {
monitor_vid_timings = monitors[i].mon_vid_timings;
if (!monitor_vid_timings)
continue;
vid_timing_read_b = &monitors[i].mon_video_timing_read_b;
vid_timing_read_l = &monitors[i].mon_video_timing_read_l;
vid_timing_read_w = &monitors[i].mon_video_timing_read_w;
vid_timing_write_b = &monitors[i].mon_video_timing_write_b;
vid_timing_write_l = &monitors[i].mon_video_timing_write_l;
vid_timing_write_w = &monitors[i].mon_video_timing_write_w;
if (monitor_vid_timings->type == VIDEO_ISA) {
*vid_timing_read_b = ISA_CYCLES(monitor_vid_timings->read_b);
*vid_timing_read_w = ISA_CYCLES(monitor_vid_timings->read_w);
*vid_timing_read_l = ISA_CYCLES(monitor_vid_timings->read_l);
*vid_timing_write_b = ISA_CYCLES(monitor_vid_timings->write_b);
*vid_timing_write_w = ISA_CYCLES(monitor_vid_timings->write_w);
*vid_timing_write_l = ISA_CYCLES(monitor_vid_timings->write_l);
} else if (monitor_vid_timings->type == VIDEO_PCI) {
*vid_timing_read_b = (int) (pci_timing * monitor_vid_timings->read_b);
*vid_timing_read_w = (int) (pci_timing * monitor_vid_timings->read_w);
*vid_timing_read_l = (int) (pci_timing * monitor_vid_timings->read_l);
*vid_timing_write_b = (int) (pci_timing * monitor_vid_timings->write_b);
*vid_timing_write_w = (int) (pci_timing * monitor_vid_timings->write_w);
*vid_timing_write_l = (int) (pci_timing * monitor_vid_timings->write_l);
} else if (monitor_vid_timings->type == VIDEO_AGP) {
*vid_timing_read_b = (int) (agp_timing * monitor_vid_timings->read_b);
*vid_timing_read_w = (int) (agp_timing * monitor_vid_timings->read_w);
*vid_timing_read_l = (int) (agp_timing * monitor_vid_timings->read_l);
*vid_timing_write_b = (int) (agp_timing * monitor_vid_timings->write_b);
*vid_timing_write_w = (int) (agp_timing * monitor_vid_timings->write_w);
*vid_timing_write_l = (int) (agp_timing * monitor_vid_timings->write_l);
} else {
*vid_timing_read_b = (int) (bus_timing * monitor_vid_timings->read_b);
*vid_timing_read_w = (int) (bus_timing * monitor_vid_timings->read_w);
*vid_timing_read_l = (int) (bus_timing * monitor_vid_timings->read_l);
*vid_timing_write_b = (int) (bus_timing * monitor_vid_timings->write_b);
*vid_timing_write_w = (int) (bus_timing * monitor_vid_timings->write_w);
*vid_timing_write_l = (int) (bus_timing * monitor_vid_timings->write_l);
}
if (cpu_16bitbus) {
*vid_timing_read_l = *vid_timing_read_w * 2;
*vid_timing_write_l = *vid_timing_write_w * 2;
}
}
}
int
calc_6to8(int c)
{
int ic;
int i8;
double d8;
ic = c;
if (ic == 64)
ic = 63;
else
ic &= 0x3f;
d8 = (ic / 63.0) * 255.0;
i8 = (int) d8;
return (i8 & 0xff);
}
int
calc_8to32(int c)
{
int b;
int g;
int r;
double db;
double dg;
double dr;
b = (c & 3);
g = ((c >> 2) & 7);
r = ((c >> 5) & 7);
db = (((double) b) / 3.0) * 255.0;
dg = (((double) g) / 7.0) * 255.0;
dr = (((double) r) / 7.0) * 255.0;
b = (int) db;
g = ((int) dg) << 8;
r = ((int) dr) << 16;
return (b | g | r);
}
int
calc_15to32(int c)
{
int b;
int g;
int r;
double db;
double dg;
double dr;
b = (c & 31);
g = ((c >> 5) & 31);
r = ((c >> 10) & 31);
db = (((double) b) / 31.0) * 255.0;
dg = (((double) g) / 31.0) * 255.0;
dr = (((double) r) / 31.0) * 255.0;
b = (int) db;
g = ((int) dg) << 8;
r = ((int) dr) << 16;
return (b | g | r);
}
int
calc_16to32(int c)
{
int b;
int g;
int r;
double db;
double dg;
double dr;
b = (c & 31);
g = ((c >> 5) & 63);
r = ((c >> 11) & 31);
db = (((double) b) / 31.0) * 255.0;
dg = (((double) g) / 63.0) * 255.0;
dr = (((double) r) / 31.0) * 255.0;
b = (int) db;
g = ((int) dg) << 8;
r = ((int) dr) << 16;
return (b | g | r);
}
void
hline(bitmap_t *b, int x1, int y, int x2, uint32_t col)
{
if (y < 0 || y >= b->h)
return;
for (int x = x1; x < x2; x++)
b->line[y][x] = col;
}
void
blit(UNUSED(bitmap_t *src), UNUSED(bitmap_t *dst), UNUSED(int x1), UNUSED(int y1), UNUSED(int x2), UNUSED(int y2), UNUSED(int xs), UNUSED(int ys))
{
//
}
void
stretch_blit(UNUSED(bitmap_t *src), UNUSED(bitmap_t *dst), UNUSED(int x1), UNUSED(int y1), UNUSED(int xs1), UNUSED(int ys1), UNUSED(int x2), UNUSED(int y2), UNUSED(int xs2), UNUSED(int ys2))
{
//
}
void
rectfill(UNUSED(bitmap_t *b), UNUSED(int x1), UNUSED(int y1), UNUSED(int x2), UNUSED(int y2), UNUSED(uint32_t col))
{
//
}
void
set_palette(UNUSED(PALETTE p))
{
//
}
void
destroy_bitmap(bitmap_t *b)
{
if ((b != NULL) && (b->dat != NULL))
free(b->dat);
if (b != NULL)
free(b);
}
bitmap_t *
create_bitmap(int x, int y)
{
bitmap_t *b = calloc(sizeof(bitmap_t), (y * sizeof(uint32_t *)));
b->dat = calloc((size_t) x * y, 4);
for (int c = 0; c < y; c++)
b->line[c] = &(b->dat[c * x]);
b->w = x;
b->h = y;
return b;
}
void
video_monitor_init(int index)
{
memset(&monitors[index], 0, sizeof(monitor_t));
monitors[index].mon_xsize = 640;
monitors[index].mon_ysize = 480;
monitors[index].mon_res_x = 640;
monitors[index].mon_res_y = 480;
monitors[index].mon_scrnsz_x = 640;
monitors[index].mon_scrnsz_y = 480;
monitors[index].mon_efscrnsz_y = 480;
monitors[index].mon_unscaled_size_x = 480;
monitors[index].mon_unscaled_size_y = 480;
monitors[index].mon_bpp = 8;
monitors[index].mon_changeframecount = 2;
monitors[index].target_buffer = create_bitmap(2048, 2048);
monitors[index].mon_blit_data_ptr = calloc(1, sizeof(blit_data_t));
monitors[index].mon_blit_data_ptr->wake_blit_thread = thread_create_event();
monitors[index].mon_blit_data_ptr->blit_complete = thread_create_event();
monitors[index].mon_blit_data_ptr->buffer_not_in_use = thread_create_event();
monitors[index].mon_blit_data_ptr->thread_run = 1;
monitors[index].mon_blit_data_ptr->monitor_index = index;
monitors[index].mon_pal_lookup = calloc(sizeof(uint32_t), 256);
monitors[index].mon_cga_palette = calloc(1, sizeof(int));
monitors[index].mon_force_resize = 1;
monitors[index].mon_vid_type = VIDEO_FLAG_TYPE_NONE;
atomic_init(&doresize_monitors[index], 0);
atomic_init(&monitors[index].mon_screenshots, 0);
if (index >= 1)
ui_init_monitor(index);
monitors[index].mon_blit_data_ptr->blit_thread = thread_create(blit_thread, monitors[index].mon_blit_data_ptr);
}
void
video_monitor_close(int monitor_index)
{
if (monitors[monitor_index].target_buffer == NULL) {
return;
}
monitors[monitor_index].mon_blit_data_ptr->thread_run = 0;
thread_set_event(monitors[monitor_index].mon_blit_data_ptr->wake_blit_thread);
thread_wait(monitors[monitor_index].mon_blit_data_ptr->blit_thread);
if (monitor_index >= 1)
ui_deinit_monitor(monitor_index);
thread_destroy_event(monitors[monitor_index].mon_blit_data_ptr->buffer_not_in_use);
thread_destroy_event(monitors[monitor_index].mon_blit_data_ptr->blit_complete);
thread_destroy_event(monitors[monitor_index].mon_blit_data_ptr->wake_blit_thread);
free(monitors[monitor_index].mon_blit_data_ptr);
if (!monitors[monitor_index].mon_pal_lookup_static)
free(monitors[monitor_index].mon_pal_lookup);
if (!monitors[monitor_index].mon_cga_palette_static)
free(monitors[monitor_index].mon_cga_palette);
destroy_bitmap(monitors[monitor_index].target_buffer);
monitors[monitor_index].target_buffer = NULL;
memset(&monitors[monitor_index], 0, sizeof(monitor_t));
}
void
video_init(void)
{
uint8_t total[2] = { 0, 1 };
for (uint8_t c = 0; c < 16; c++) {
cga_2_table[c] = (total[(c >> 3) & 1] << 0) | (total[(c >> 2) & 1] << 8) | (total[(c >> 1) & 1] << 16) | (total[(c >> 0) & 1] << 24);
}
for (uint8_t c = 0; c < 64; c++) {
cgapal[c + 64].r = (((c & 4) ? 2 : 0) | ((c & 0x10) ? 1 : 0)) * 21;
cgapal[c + 64].g = (((c & 2) ? 2 : 0) | ((c & 0x10) ? 1 : 0)) * 21;
cgapal[c + 64].b = (((c & 1) ? 2 : 0) | ((c & 0x10) ? 1 : 0)) * 21;
if ((c & 0x17) == 6)
cgapal[c + 64].g >>= 1;
}
for (uint8_t c = 0; c < 64; c++) {
cgapal[c + 128].r = (((c & 4) ? 2 : 0) | ((c & 0x20) ? 1 : 0)) * 21;
cgapal[c + 128].g = (((c & 2) ? 2 : 0) | ((c & 0x10) ? 1 : 0)) * 21;
cgapal[c + 128].b = (((c & 1) ? 2 : 0) | ((c & 0x08) ? 1 : 0)) * 21;
}
for (uint8_t c = 0; c < 4; c++) {
for (uint8_t d = 0; d < 4; d++) {
edatlookup[c][d] = 0;
if (c & 1)
edatlookup[c][d] |= 1;
if (d & 1)
edatlookup[c][d] |= 2;
if (c & 2)
edatlookup[c][d] |= 0x10;
if (d & 2)
edatlookup[c][d] |= 0x20;
}
}
for (uint16_t c = 0; c < 256; c++) {
egaremap2bpp[c] = 0;
if (c & 0x01)
egaremap2bpp[c] |= 0x01;
if (c & 0x04)
egaremap2bpp[c] |= 0x02;
if (c & 0x10)
egaremap2bpp[c] |= 0x04;
if (c & 0x40)
egaremap2bpp[c] |= 0x08;
}
video_6to8 = malloc(4 * 256);
for (uint16_t c = 0; c < 256; c++)
video_6to8[c] = calc_6to8(c);
video_8togs = malloc(4 * 256);
for (uint16_t c = 0; c < 256; c++)
video_8togs[c] = c | (c << 16) | (c << 24);
video_8to32 = malloc(4 * 256);
for (uint16_t c = 0; c < 256; c++)
video_8to32[c] = calc_8to32(c);
video_15to32 = malloc(4 * 65536);
for (uint32_t c = 0; c < 65536; c++)
video_15to32[c] = calc_15to32(c & 0x7fff);
video_16to32 = malloc(4 * 65536);
for (uint32_t c = 0; c < 65536; c++)
video_16to32[c] = calc_16to32(c);
memset(monitors, 0, sizeof(monitors));
video_monitor_init(0);
}
void
video_close(void)
{
video_monitor_close(0);
free(video_16to32);
free(video_15to32);
free(video_8to32);
free(video_8togs);
free(video_6to8);
if (fontdatksc5601) {
free(fontdatksc5601);
fontdatksc5601 = NULL;
}
if (fontdatksc5601_user) {
free(fontdatksc5601_user);
fontdatksc5601_user = NULL;
}
}
uint8_t
video_force_resize_get_monitor(int monitor_index)
{
return monitors[monitor_index].mon_force_resize;
}
void
video_force_resize_set_monitor(uint8_t res, int monitor_index)
{
monitors[monitor_index].mon_force_resize = res;
}
void
loadfont_common(FILE *f, int format)
{
int c;
int d;
switch (format) {
case 0: /* MDA */
for (c = 0; c < 256; c++)
for (d = 0; d < 8; d++)
fontdatm[c][d] = fgetc(f) & 0xff;
for (c = 0; c < 256; c++)
for (d = 0; d < 8; d++)
fontdatm[c][d + 8] = fgetc(f) & 0xff;
(void) fseek(f, 4096 + 2048, SEEK_SET);
for (c = 0; c < 256; c++)
for (d = 0; d < 8; d++)
fontdat[c][d] = fgetc(f) & 0xff;
break;
case 1: /* PC200 */
for (d = 0; d < 4; d++) {
/* There are 4 fonts in the ROM */
for (c = 0; c < 256; c++) /* 8x14 MDA in 8x16 cell */
(void) !fread(&fontdatm[256 * d + c][0], 1, 16, f);
for (c = 0; c < 256; c++) { /* 8x8 CGA in 8x16 cell */
(void) !fread(&fontdat[256 * d + c][0], 1, 8, f);
fseek(f, 8, SEEK_CUR);
}
}
break;
default:
case 2: /* CGA */
for (c = 0; c < 256; c++)
for (d = 0; d < 8; d++)
fontdat[c][d] = fgetc(f) & 0xff;
break;
case 3: /* Wyse 700 */
for (c = 0; c < 512; c++)
for (d = 0; d < 32; d++)
fontdatw[c][d] = fgetc(f) & 0xff;
break;
case 4: /* MDSI Genius */
for (c = 0; c < 256; c++)
for (d = 0; d < 16; d++)
fontdat8x12[c][d] = fgetc(f) & 0xff;
break;
case 5: /* Toshiba 3100e */
for (d = 0; d < 2048; d += 512) { /* Four languages... */
for (c = d; c < d + 256; c++) {
(void) !fread(&fontdatm[c][8], 1, 8, f);
}
for (c = d + 256; c < d + 512; c++) {
(void) !fread(&fontdatm[c][8], 1, 8, f);
}
for (c = d; c < d + 256; c++) {
(void) !fread(&fontdatm[c][0], 1, 8, f);
}
for (c = d + 256; c < d + 512; c++) {
(void) !fread(&fontdatm[c][0], 1, 8, f);
}
fseek(f, 4096, SEEK_CUR); /* Skip blank section */
for (c = d; c < d + 256; c++) {
(void) !fread(&fontdat[c][0], 1, 8, f);
}
for (c = d + 256; c < d + 512; c++) {
(void) !fread(&fontdat[c][0], 1, 8, f);
}
}
break;
case 6: /* Korean KSC-5601 */
if (!fontdatksc5601)
fontdatksc5601 = malloc(16384 * sizeof(dbcs_font_t));
if (!fontdatksc5601_user)
fontdatksc5601_user = malloc(192 * sizeof(dbcs_font_t));
for (c = 0; c < 16384; c++) {
for (d = 0; d < 32; d++)
fontdatksc5601[c].chr[d] = fgetc(f) & 0xff;
}
break;
case 7: /* Sigma Color 400 */
/* The first 4k of the character ROM holds an 8x8 font */
for (c = 0; c < 256; c++) {
(void) !fread(&fontdat[c][0], 1, 8, f);
fseek(f, 8, SEEK_CUR);
}
/* The second 4k holds an 8x16 font */
for (c = 0; c < 256; c++) {
if (fread(&fontdatm[c][0], 1, 16, f) != 16)
fatal("loadfont(): Error reading 8x16 font in Sigma Color 400 mode, c = %i\n", c);
}
break;
case 8: /* Amstrad PC1512, Toshiba T1000/T1200 */
for (c = 0; c < 2048; c++) /* Allow up to 2048 chars */
for (d = 0; d < 8; d++)
fontdat[c][d] = fgetc(f) & 0xff;
break;
case 9: /* Image Manager 1024 native font */
for (c = 0; c < 256; c++)
(void) !fread(&fontdat12x18[c][0], 1, 36, f);
break;
case 10: /* Pravetz */
for (c = 0; c < 1024; c++) /* Allow up to 1024 chars */
for (d = 0; d < 8; d++)
fontdat[c][d] = fgetc(f) & 0xff;
break;
case 11: /* PC200 */
for (d = 0; d < 4; d++) {
/* There are 4 fonts in the ROM */
for (c = 0; c < 256; c++) /* 8x14 MDA in 8x16 cell */
(void) !fread(&fontdatm2[256 * d + c][0], 1, 16, f);
for (c = 0; c < 256; c++) { /* 8x8 CGA in 8x16 cell */
(void) !fread(&fontdat2[256 * d + c][0], 1, 8, f);
fseek(f, 8, SEEK_CUR);
}
}
break;
}
(void) fclose(f);
}
void
loadfont_ex(char *s, int format, int offset)
{
FILE *fp;
fp = rom_fopen(s, "rb");
if (fp == NULL)
return;
fseek(fp, offset, SEEK_SET);
loadfont_common(fp, format);
}
void
loadfont(char *s, int format)
{
loadfont_ex(s, format, 0);
}
uint32_t
video_color_transform(uint32_t color)
{
uint8_t *clr8 = (uint8_t *) &color;
#if 0
if (!video_grayscale && !invert_display)
return color;
#endif
if (video_grayscale) {
if (video_graytype) {
if (video_graytype == 1)
color = ((54 * (uint32_t) clr8[2]) + (183 * (uint32_t) clr8[1]) + (18 * (uint32_t) clr8[0])) / 255;
else
color = ((uint32_t) clr8[2] + (uint32_t) clr8[1] + (uint32_t) clr8[0]) / 3;
} else
color = ((76 * (uint32_t) clr8[2]) + (150 * (uint32_t) clr8[1]) + (29 * (uint32_t) clr8[0])) / 255;
switch (video_grayscale) {
case 2:
case 3:
case 4:
color = shade[video_grayscale][color];
break;
default:
clr8[3] = 0;
clr8[0] = color;
clr8[1] = clr8[2] = clr8[0];
break;
}
}
if (invert_display)
color ^= 0x00ffffff;
return color;
}
``` | /content/code_sandbox/src/video/video.c | c | 2016-06-25T22:29:10 | 2024-08-16T19:09:21 | 86Box | 86Box/86Box | 2,616 | 17,989 |
```c
/*
* 86Box A hypervisor and IBM PC system emulator that specializes in
* running old operating systems and software designed for IBM
* PC systems and compatibles from 1981 through fairly recent
* system designs based on the PCI bus.
*
* This file is part of the 86Box distribution.
*
* C&T 69000 emulation.
*
*
*
* Authors: Cacodemon345
*
*/
#include <stdio.h>
#include <stdbool.h>
#include <stdint.h>
#include <string.h>
#include <stdlib.h>
#include <wchar.h>
#include <time.h>
#include <stdatomic.h>
#include <86box/86box.h>
#include <86box/io.h>
#include <86box/mem.h>
#include <86box/rom.h>
#include <86box/device.h>
#include <86box/timer.h>
#include <86box/video.h>
#include <86box/vid_svga.h>
#include <86box/vid_svga_render.h>
#include <86box/pci.h>
#include <86box/thread.h>
#include <86box/i2c.h>
#include <86box/vid_ddc.h>
#include <86box/plat_unused.h>
#include <86box/bswap.h>
#include <assert.h>
#pragma pack(push, 1)
typedef struct chips_69000_bitblt_t
{
/* BR00 - Source and Destination Span Register. */
uint16_t source_span;
uint16_t destination_span;
/* BR01 - Pattern/Source Expansion Background Color & Transparency Key Register. */
uint32_t pattern_source_key_bg;
/* BR02 - Pattern/Source Expansion Foreground Color Register. */
uint32_t pattern_source_key_fg;
/* BR03 - Monochrome Source Control Register. */
uint8_t monochrome_source_left_clip;
uint8_t monochrome_source_right_clip;
uint8_t monochrome_source_initial_discard;
uint8_t monochrome_source_alignment : 3;
uint8_t monochrome_source_expansion_color_reg_select : 1;
uint8_t dummy_8 : 4;
/* BR04 - BitBLT Control Register. */
uint32_t bitblt_control;
/* BR05 - Pattern Address Register. */
uint32_t pat_addr;
/* BR06 - Source Address Register. */
uint32_t source_addr;
/* BR07 - Destination Address Register. */
uint32_t destination_addr;
/* BR08 - Destination Width & Height Register. */
uint16_t destination_width;
uint16_t destination_height;
/* BR09 - Source Expansion Background Color & Transparency Key Register. */
uint32_t source_key_bg;
/* BR0A - Source Expansion Foreground Color Register. */
uint32_t source_key_fg;
} chips_69000_bitblt_t;
#pragma pack(pop)
typedef struct chips_69000_t {
svga_t svga;
uint8_t pci_conf_status;
uint8_t slot, irq_state;
uint8_t pci_line_interrupt;
uint8_t pci_rom_enable;
uint8_t read_write_bank;
bool engine_active;
bool quit;
thread_t *accel_thread;
event_t *fifo_event, *fifo_data_event;
pc_timer_t decrement_timer;
uint16_t rom_addr;
mem_mapping_t linear_mapping;
uint8_t on_board;
rgb_t cursor_palette[8];
uint32_t cursor_pallook[8];
uint8_t mm_regs[256], mm_index;
uint8_t flat_panel_regs[256], flat_panel_index;
uint8_t ext_regs[256], ext_index;
union {
uint32_t mem_regs[4];
uint16_t mem_regs_w[4 * 2];
uint8_t mem_regs_b[4 * 4];
};
union {
uint32_t bitblt_regs[11];
uint16_t bitblt_regs_w[11 * 2];
uint8_t bitblt_regs_b[11 * 4];
struct chips_69000_bitblt_t bitblt;
};
struct
{
struct chips_69000_bitblt_t bitblt;
uint32_t actual_source_height;
uint32_t actual_destination_height;
uint32_t actual_destination_width;
uint32_t count_x, count_y;
int x, y;
int x_dir, y_dir;
uint8_t bytes_per_pixel;
/* Byte counter for BitBLT port writes. */
uint8_t bytes_written;
uint8_t bytes_skip;
uint32_t mono_bytes_pitch;
uint8_t mono_bits_skip_left;
uint32_t bytes_counter;
uint32_t bytes_in_line_written;
uint8_t bytes_port[256];
} bitblt_running;
union {
uint16_t subsys_vid;
uint8_t subsys_vid_b[2];
};
union {
uint16_t subsys_pid;
uint8_t subsys_pid_b[2];
};
rom_t bios_rom;
void *i2c, *ddc;
uint8_t st01;
} chips_69000_t;
static chips_69000_t *reset_state = NULL;
/* TODO: Probe timings on real hardware. */
static video_timings_t timing_chips = { .type = VIDEO_PCI, .write_b = 2, .write_w = 2, .write_l = 1, .read_b = 10, .read_w = 10, .read_l = 10 };
uint8_t chips_69000_readb_linear(uint32_t addr, void *p);
uint16_t chips_69000_readw_linear(uint32_t addr, void *p);
uint32_t chips_69000_readl_linear(uint32_t addr, void *p);
void chips_69000_writeb_linear(uint32_t addr, uint8_t val, void *p);
void chips_69000_writew_linear(uint32_t addr, uint16_t val, void *p);
void chips_69000_writel_linear(uint32_t addr, uint32_t val, void *p);
/* Multimedia handling. */
uint8_t
chips_69000_read_multimedia(chips_69000_t* chips)
{
switch (chips->mm_index) {
case 0:
/* Report no playback/capture capability. */
return 0;
default:
return chips->mm_regs[chips->mm_index];
}
return chips->mm_regs[chips->mm_index];
}
/* Multimedia (write) handling. */
void
chips_69000_write_multimedia(chips_69000_t* chips, uint8_t val)
{
switch (chips->mm_index) {
case 0:
return;
default:
chips->mm_regs[chips->mm_index] = val;
break;
}
chips->mm_regs[chips->mm_index] = val;
}
/* Flat panel handling. */
uint8_t
chips_69000_read_flat_panel(chips_69000_t* chips)
{
switch (chips->flat_panel_index) {
case 0:
return 1;
default:
return chips->flat_panel_regs[chips->flat_panel_index];
}
return chips->flat_panel_regs[chips->flat_panel_index];
}
/* Flat panel (write) handling. */
void
chips_69000_write_flat_panel(chips_69000_t* chips, uint8_t val)
{
switch (chips->flat_panel_index) {
case 0:
return;
case 1:
case 0x20 ... 0x33:
case 0x35:
case 0x36:
chips->flat_panel_regs[chips->flat_panel_index] = val;
svga_recalctimings(&chips->svga);
return;
default:
chips->flat_panel_regs[chips->flat_panel_index] = val;
break;
}
chips->flat_panel_regs[chips->flat_panel_index] = val;
}
void
chips_69000_interrupt(chips_69000_t* chips)
{
pci_irq(chips->slot, PCI_INTA, 0, !!((chips->mem_regs[0] & chips->mem_regs[1]) & 0x80004040), &chips->irq_state);
}
void
chips_69000_bitblt_interrupt(chips_69000_t* chips)
{
chips->engine_active = 0;
chips->mem_regs[1] |= 1 << 31;
chips_69000_interrupt(chips);
}
void
chips_69000_do_rop_8bpp(uint8_t *dst, uint8_t src, uint8_t rop)
{
switch (rop) {
case 0x00:
*dst = 0;
break;
case 0x11:
*dst = ~(*dst) & ~src;
break;
case 0x22:
*dst &= ~src;
break;
case 0x33:
*dst = ~src;
break;
case 0x44:
*dst = src & ~(*dst);
break;
case 0x55:
*dst = ~*dst;
break;
case 0x66:
*dst ^= src;
break;
case 0x77:
*dst = ~src | ~(*dst);
break;
case 0x88:
*dst &= src;
break;
case 0x99:
*dst ^= ~src;
break;
case 0xAA:
break; /* No-op. */
case 0xBB:
*dst |= ~src;
break;
case 0xCC:
*dst = src;
break;
case 0xDD:
*dst = src | ~(*dst);
break;
case 0xEE:
*dst |= src;
break;
case 0xFF:
*dst = 0xFF;
break;
}
}
void
chips_69000_do_rop_16bpp(uint16_t *dst, uint16_t src, uint8_t rop)
{
switch (rop) {
case 0x00:
*dst = 0;
break;
case 0x11:
*dst = ~(*dst) & ~src;
break;
case 0x22:
*dst &= ~src;
break;
case 0x33:
*dst = ~src;
break;
case 0x44:
*dst = src & ~(*dst);
break;
case 0x55:
*dst = ~*dst;
break;
case 0x66:
*dst ^= src;
break;
case 0x77:
*dst = ~src | ~(*dst);
break;
case 0x88:
*dst &= src;
break;
case 0x99:
*dst ^= ~src;
break;
case 0xAA:
break; /* No-op. */
case 0xBB:
*dst |= ~src;
break;
case 0xCC:
*dst = src;
break;
case 0xDD:
*dst = src | ~(*dst);
break;
case 0xEE:
*dst |= src;
break;
case 0xFF:
*dst = 0xFFFF;
break;
}
}
void
chips_69000_do_rop_24bpp(uint32_t *dst, uint32_t src, uint8_t rop)
{
switch (rop) {
case 0x00:
*dst = 0;
break;
case 0x11:
*dst = ~(*dst) & ~src;
break;
case 0x22:
*dst &= ~src;
break;
case 0x33:
*dst = ~src;
break;
case 0x44:
*dst = src & ~(*dst);
break;
case 0x55:
*dst = ~*dst;
break;
case 0x66:
*dst ^= src;
break;
case 0x77:
*dst = ~src | ~(*dst);
break;
case 0x88:
*dst &= src;
break;
case 0x99:
*dst ^= ~src;
break;
case 0xAA:
break; /* No-op. */
case 0xBB:
*dst |= ~src;
break;
case 0xCC:
*dst = src;
break;
case 0xDD:
*dst = src | ~(*dst);
break;
case 0xEE:
*dst |= src;
break;
case 0xFF:
*dst = 0xFFFFFF;
break;
}
}
void
chips_69000_do_rop_8bpp_patterned(uint8_t *dst, uint8_t pattern, uint8_t src, uint8_t rop)
{
if ((rop & 0xF) == ((rop >> 4) & 0xF)) {
return chips_69000_do_rop_8bpp(dst, src, rop);
}
switch (rop) {
case 0x00:
*dst = 0;
break;
case 0x05:
*dst = ~(*dst) & ~pattern;
break;
case 0x0A:
*dst &= ~pattern;
break;
case 0x0F:
*dst = ~pattern;
break;
case 0x1A:
*dst = pattern ^ (*dst | (pattern & src));
break;
case 0x2A:
*dst = *dst & (~(src & pattern));
break;
case 0x3A:
*dst = src ^ (pattern | (*dst ^ src));
break;
case 0x4A:
*dst = *dst ^ (pattern & (src | *dst));
break;
case 0x50:
*dst = pattern & ~(*dst);
break;
case 0x55:
*dst = ~*dst;
break;
case 0x5A:
*dst ^= pattern;
break;
case 0x5F:
*dst = ~pattern | ~(*dst);
break;
case 0x6A:
*dst = *dst ^ (pattern & src);
break;
case 0x7A:
*dst = *dst ^ (pattern & (src | (~*dst)));
break;
case 0x8A:
*dst = *dst & (src | (~pattern));
break;
case 0x9A:
*dst = *dst ^ (pattern & (~src));
break;
case 0xB8:
*dst = (((pattern ^ *dst) & src) ^ pattern);
break;
case 0xA0:
*dst &= pattern;
break;
case 0xA5:
*dst ^= ~pattern;
break;
case 0xAA:
break; /* No-op. */
case 0xAC:
*dst = src ^ (pattern & (*dst ^ src));
break;
case 0xAF:
*dst |= ~pattern;
break;
case 0xBA:
*dst |= (pattern & ~src);
break;
case 0xCA:
*dst ^= (pattern & (src ^ *dst));
break;
case 0xE2:
*dst ^= (src & (pattern ^ *dst));
break;
case 0xDA:
*dst ^= pattern & (~(src & *dst));
break;
case 0xEA:
*dst |= pattern & src;
break;
case 0xF0:
*dst = pattern;
break;
case 0xF5:
*dst = pattern | ~(*dst);
break;
case 0xFA:
*dst |= pattern;
break;
case 0xFF:
*dst = 0xFF;
break;
default:
pclog("Unknown ROP 0x%X\n", rop);
break;
}
}
void
chips_69000_do_rop_16bpp_patterned(uint16_t *dst, uint16_t pattern, uint16_t src, uint8_t rop)
{
if ((rop & 0xF) == ((rop >> 4) & 0xF)) {
return chips_69000_do_rop_16bpp(dst, src, rop);
}
switch (rop) {
default:
pclog("Unknown ROP 0x%X\n", rop);
break;
case 0x00:
*dst = 0;
break;
case 0x05:
*dst = ~(*dst) & ~pattern;
break;
case 0x0A:
*dst &= ~pattern;
break;
case 0x0F:
*dst = ~pattern;
break;
case 0x1A:
*dst = pattern ^ (*dst | (pattern & src));
break;
case 0x2A:
*dst = *dst & (~(src & pattern));
break;
case 0x3A:
*dst = src ^ (pattern | (*dst ^ src));
break;
case 0x4A:
*dst = *dst ^ (pattern & (src | *dst));
break;
case 0x50:
*dst = pattern & ~(*dst);
break;
case 0x55:
*dst = ~*dst;
break;
case 0x5A:
*dst ^= pattern;
break;
case 0x5F:
*dst = ~pattern | ~(*dst);
break;
case 0x6A:
*dst = *dst ^ (pattern & src);
break;
case 0x7A:
*dst = *dst ^ (pattern & (src | (~*dst)));
break;
case 0x8A:
*dst = *dst & (src | (~pattern));
break;
case 0x9A:
*dst = *dst ^ (pattern & (~src));
break;
case 0xB8:
*dst = (((pattern ^ *dst) & src) ^ pattern);
break;
case 0xA0:
*dst &= pattern;
break;
case 0xA5:
*dst ^= ~pattern;
break;
case 0xAA:
break; /* No-op. */
case 0xAC:
*dst = src ^ (pattern & (*dst ^ src));
break;
case 0xAF:
*dst |= ~pattern;
break;
case 0xBA:
*dst |= (pattern & ~src);
break;
case 0xCA:
*dst ^= (pattern & (src ^ *dst));
break;
case 0xE2:
*dst ^= (src & (pattern ^ *dst));
break;
case 0xDA:
*dst ^= pattern & (~(src & *dst));
break;
case 0xEA:
*dst |= pattern & src;
break;
case 0xF0:
*dst = pattern;
break;
case 0xF5:
*dst = pattern | ~(*dst);
break;
case 0xFA:
*dst |= pattern;
break;
case 0xFF:
*dst = 0xFF;
break;
}
}
void
chips_69000_do_rop_24bpp_patterned(uint32_t *dst, uint32_t pattern, uint32_t src, uint8_t rop)
{
uint32_t orig_dst = *dst & 0xFF000000;
if ((rop & 0xF) == ((rop >> 4) & 0xF)) {
return chips_69000_do_rop_24bpp(dst, src, rop);
}
switch (rop) {
default:
pclog("Unknown ROP 0x%X\n", rop);
break;
case 0x00:
*dst = 0;
break;
case 0x05:
*dst = ~(*dst) & ~pattern;
break;
case 0x0A:
*dst &= ~pattern;
break;
case 0x0F:
*dst = ~pattern;
break;
case 0x1A:
*dst = pattern ^ (*dst | (pattern & src));
break;
case 0x2A:
*dst = *dst & (~(src & pattern));
break;
case 0x3A:
*dst = src ^ (pattern | (*dst ^ src));
break;
case 0x4A:
*dst = *dst ^ (pattern & (src | *dst));
break;
case 0x50:
*dst = pattern & ~(*dst);
break;
case 0x55:
*dst = ~*dst;
break;
case 0x5A:
*dst ^= pattern;
break;
case 0x5F:
*dst = ~pattern | ~(*dst);
break;
case 0x6A:
*dst = *dst ^ (pattern & src);
break;
case 0x7A:
*dst = *dst ^ (pattern & (src | (~*dst)));
break;
case 0x8A:
*dst = *dst & (src | (~pattern));
break;
case 0x9A:
*dst = *dst ^ (pattern & (~src));
break;
case 0xB8:
*dst = (((pattern ^ *dst) & src) ^ pattern);
break;
case 0xA0:
*dst &= pattern;
break;
case 0xA5:
*dst ^= ~pattern;
break;
case 0xAA:
break; /* No-op. */
case 0xAC:
*dst = src ^ (pattern & (*dst ^ src));
break;
case 0xAF:
*dst |= ~pattern;
break;
case 0xBA:
*dst |= (pattern & ~src);
break;
case 0xCA:
*dst ^= (pattern & (src ^ *dst));
break;
case 0xDA:
*dst ^= pattern & (~(src & *dst));
break;
case 0xE2:
*dst ^= (src & (pattern ^ *dst));
break;
case 0xEA:
*dst |= pattern & src;
break;
case 0xF0:
*dst = pattern;
break;
case 0xF5:
*dst = pattern | ~(*dst);
break;
case 0xFA:
*dst |= pattern;
break;
case 0xFF:
*dst = 0xFF;
break;
}
*dst &= 0xFFFFFF;
*dst |= orig_dst;
}
void
chips_69000_recalctimings(svga_t *svga)
{
chips_69000_t *chips = (chips_69000_t *) svga->priv;
svga->clock = (cpuclock * (double) (1ULL << 32)) / svga->getclock((svga->miscout >> 2) & 3, svga->priv);
if (chips->ext_regs[0x81] & 0x10) {
svga->htotal -= 5;
}
if (((chips->ext_regs[0x61] & 0x8) && !(chips->ext_regs[0x61] & 0x4))
|| ((chips->ext_regs[0x61] & 0x2) && !(chips->ext_regs[0x61] & 0x1))) {
svga->dpms = 1;
} else
svga->dpms = 0;
if (chips->ext_regs[0x09] & 0x1) {
svga->vtotal -= 2;
svga->vtotal &= 0xFF;
svga->vtotal |= (svga->crtc[0x30] & 0xF) << 8;
svga->vtotal += 2;
svga->dispend--;
svga->dispend &= 0xFF;
svga->dispend |= (svga->crtc[0x31] & 0xF) << 8;
svga->dispend++;
svga->vsyncstart--;
svga->vsyncstart &= 0xFF;
svga->vsyncstart |= (svga->crtc[0x32] & 0xF) << 8;
svga->vsyncstart++;
svga->vblankstart--;
svga->vblankstart &= 0xFF;
svga->vblankstart |= (svga->crtc[0x33] & 0xF) << 8;
svga->vblankstart++;
if (!(chips->ext_regs[0x81] & 0x10))
svga->htotal -= 5;
svga->htotal |= (svga->crtc[0x38] & 0x1) << 8;
if (!(chips->ext_regs[0x81] & 0x10))
svga->htotal += 5;
svga->hblank_end_val = ((svga->crtc[3] & 0x1f) | ((svga->crtc[5] & 0x80) ? 0x20 : 0x00)) | (svga->crtc[0x3c] & 0b11000000);
svga->hblank_end_mask = 0xff;
svga->ma_latch |= (svga->crtc[0x40] & 0xF) << 16;
svga->rowoffset |= (svga->crtc[0x41] & 0xF) << 8;
svga->interlace = !!(svga->crtc[0x70] & 0x80);
if (svga->hdisp == 1280 && svga->dispend == 1024) {
svga->interlace = 0;
}
switch (chips->ext_regs[0x81] & 0xF) {
default:
svga->bpp = 8;
break;
case 0b0010:
svga->bpp = 8;
svga->render = svga_render_8bpp_highres;
break;
case 0b0100:
svga->bpp = 15;
svga->render = svga_render_15bpp_highres;
break;
case 0b0101:
svga->bpp = 16;
svga->render = svga_render_16bpp_highres;
break;
case 0b0110:
svga->bpp = 24;
svga->render = svga_render_24bpp_highres;
break;
case 0b0111:
svga->bpp = 32;
svga->render = svga_render_32bpp_highres;
break;
}
#if 1
if (chips->flat_panel_regs[0x01] & 0x2) {
/* TODO: Fix horizontal parameter calculations. */
if (svga->hdisp > (((chips->flat_panel_regs[0x20] | ((chips->flat_panel_regs[0x25] & 0xF) << 8)) + 1) << 3)) {
svga->hdisp = ((chips->flat_panel_regs[0x20] | ((chips->flat_panel_regs[0x25] & 0xF) << 8)) + 1) << 3;
//svga->htotal = ((chips->flat_panel_regs[0x23] | ((chips->flat_panel_regs[0x26] & 0xF) << 8)) + 5) << 3;
//svga->hblank_end_val = svga->htotal - 1;
svga->hoverride = 1;
} else
svga->hoverride = 0;
if (svga->dispend > (((chips->flat_panel_regs[0x30] | ((chips->flat_panel_regs[0x35] & 0xF) << 8)) + 1))) {
svga->dispend = svga->vsyncstart = svga->vblankstart = ((chips->flat_panel_regs[0x30] | ((chips->flat_panel_regs[0x35] & 0xF) << 8)) + 1);
}
//svga->hdisp = ((chips->flat_panel_regs[0x20] | ((chips->flat_panel_regs[0x25] & 0xF) << 8)) + 1) << 3;
//svga->htotal = ((chips->flat_panel_regs[0x23] | ((chips->flat_panel_regs[0x26] & 0xF) << 8)) + 5) << 3;
//svga->hblank_end_val = svga->htotal - 1;
//svga->dispend = svga->vsyncstart = svga->vblankstart = ((chips->flat_panel_regs[0x30] | ((chips->flat_panel_regs[0x35] & 0xF) << 8)) + 1);
//svga->vsyncstart = ((chips->flat_panel_regs[0x31] | ((chips->flat_panel_regs[0x35] & 0xF0) << 4)) + 1);
//svga->vtotal = ((chips->flat_panel_regs[0x33] | ((chips->flat_panel_regs[0x36] & 0xF) << 8)) + 2);
svga->clock = (cpuclock * (double) (1ULL << 32)) / svga->getclock((chips->flat_panel_regs[0x03] >> 2) & 3, svga->priv);
} else {
svga->hoverride = 0;
}
#endif
} else {
svga->bpp = 8;
svga->hoverride = 0;
}
}
void
chips_69000_decrement_timer(void* p)
{
chips_69000_t *chips = (chips_69000_t*)p;
chips->ext_regs[0xD2]--;
timer_on_auto(&chips->decrement_timer, 1000000. / 2000.);
}
void
chips_69000_recalc_banking(chips_69000_t *chips)
{
svga_t* svga = &chips->svga;
chips->svga.read_bank = chips->svga.write_bank = 0;
svga->chain2_write = !(svga->seqregs[0x4] & 4);
svga->chain4 = (svga->seqregs[0x4] & 8) || (chips->ext_regs[0xA] & 0x4);
svga->fast = (svga->gdcreg[8] == 0xff && !(svga->gdcreg[3] & 0x18) && !svga->gdcreg[1]) && ((svga->chain4 && (svga->packed_chain4 || svga->force_old_addr)) || svga->fb_only) && !(svga->adv_flags & FLAG_ADDR_BY8);
if (chips->ext_regs[0xA] & 1) {
chips->svga.read_bank = chips->svga.write_bank = 0x10000 * (chips->ext_regs[0xE] & 0x7f);
}
/*if (chips->ext_regs[0x40] & 2) {
svga->decode_mask = (1 << 18) - 1;
} else {
svga->decode_mask = (1 << 21) - 1;
}*/
}
void
chips_69000_process_pixel(chips_69000_t* chips, uint32_t pixel)
{
uint32_t pattern_fg = chips->bitblt_running.bitblt.pattern_source_key_fg;
uint32_t pattern_bg = chips->bitblt_running.bitblt.pattern_source_key_bg;
uint8_t pattern_data = 0;
uint32_t pattern_pixel = 0;
uint32_t dest_pixel = 0;
uint32_t dest_addr = chips->bitblt_running.bitblt.destination_addr + (chips->bitblt_running.y * chips->bitblt_running.bitblt.destination_span) + (chips->bitblt_running.x * chips->bitblt_running.bytes_per_pixel);
uint8_t vert_pat_alignment = (chips->bitblt_running.bitblt.bitblt_control >> 20) & 7;
uint8_t orig_dest_addr_bit = chips->bitblt_running.bitblt.destination_addr & 1;
switch (chips->bitblt_running.bytes_per_pixel) {
case 1: /* 8 bits-per-pixel. */
{
dest_pixel = chips_69000_readb_linear(dest_addr, chips);
break;
}
case 2: /* 16 bits-per-pixel. */
{
dest_pixel = chips_69000_readb_linear(dest_addr, chips);
dest_pixel |= chips_69000_readb_linear(dest_addr + 1, chips) << 8;
break;
}
case 3: /* 24 bits-per-pixel. */
{
dest_pixel = chips_69000_readb_linear(dest_addr, chips);
dest_pixel |= chips_69000_readb_linear(dest_addr + 1, chips) << 8;
dest_pixel |= chips_69000_readb_linear(dest_addr + 2, chips) << 16;
break;
}
}
if (chips->bitblt_running.bytes_per_pixel == 2) {
chips->bitblt_running.bitblt.destination_addr >>= 1;
}
if (chips->bitblt_running.bitblt.bitblt_control & (1 << 18)) {
uint8_t is_true = 0;
if (chips->bitblt_running.bitblt.bitblt_control & (1 << 19))
pattern_data = 0;
else
pattern_data = chips_69000_readb_linear(chips->bitblt_running.bitblt.pat_addr + ((vert_pat_alignment + (chips->bitblt_running.y & 7)) & 7), chips);
is_true = !!(pattern_data & (1 << (7 - ((chips->bitblt_running.bitblt.destination_addr + chips->bitblt_running.x) & 7))));
if (!is_true && (chips->bitblt_running.bitblt.bitblt_control & (1 << 17))) {
if (chips->bitblt_running.bytes_per_pixel == 2) {
chips->bitblt_running.bitblt.destination_addr <<= 1;
chips->bitblt_running.bitblt.destination_addr |= orig_dest_addr_bit;
}
return;
}
pattern_pixel = is_true ? pattern_fg : pattern_bg;
pattern_pixel &= (1 << (8 * (chips->bitblt_running.bytes_per_pixel))) - 1;
} else {
if (chips->bitblt_running.bytes_per_pixel == 1) {
pattern_pixel = chips_69000_readb_linear(chips->bitblt_running.bitblt.pat_addr
+ 8 * ((vert_pat_alignment + chips->bitblt_running.y) & 7)
+ (((chips->bitblt_running.bitblt.destination_addr & 7) + chips->bitblt_running.x) & 7), chips);
}
if (chips->bitblt_running.bytes_per_pixel == 2) {
pattern_pixel = chips_69000_readb_linear(chips->bitblt_running.bitblt.pat_addr
+ (2 * 8 * ((vert_pat_alignment + chips->bitblt_running.y) & 7))
+ (2 * (((chips->bitblt_running.bitblt.destination_addr & 7) + chips->bitblt_running.x) & 7)), chips);
pattern_pixel |= chips_69000_readb_linear(chips->bitblt_running.bitblt.pat_addr
+ (2 * 8 * ((vert_pat_alignment + chips->bitblt_running.y) & 7))
+ (2 * (((chips->bitblt_running.bitblt.destination_addr & 7) + chips->bitblt_running.x) & 7)) + 1, chips) << 8;
}
if (chips->bitblt_running.bytes_per_pixel == 3) {
pattern_pixel = chips_69000_readb_linear(chips->bitblt_running.bitblt.pat_addr
+ (4 * 8 * ((vert_pat_alignment + chips->bitblt_running.y) & 7))
+ (3 * (((chips->bitblt_running.bitblt.destination_addr & 7) + chips->bitblt_running.x) & 7)), chips);
pattern_pixel |= chips_69000_readb_linear(chips->bitblt_running.bitblt.pat_addr
+ (4 * 8 * ((vert_pat_alignment + chips->bitblt_running.y) & 7))
+ (3 * (((chips->bitblt_running.bitblt.destination_addr & 7) + chips->bitblt_running.x) & 7)) + 1, chips) << 8;
pattern_pixel |= chips_69000_readb_linear(chips->bitblt_running.bitblt.pat_addr
+ (4 * 8 * ((vert_pat_alignment + chips->bitblt_running.y) & 7))
+ (3 * (((chips->bitblt_running.bitblt.destination_addr & 7) + chips->bitblt_running.x) & 7)) + 2, chips) << 16;
}
}
if (chips->bitblt_running.bytes_per_pixel == 2) {
chips->bitblt_running.bitblt.destination_addr <<= 1;
chips->bitblt_running.bitblt.destination_addr |= orig_dest_addr_bit;
}
if (chips->bitblt_running.bitblt.bitblt_control & (1 << 14)) {
switch ((chips->bitblt_running.bitblt.bitblt_control >> 15) & 3) {
case 1:
case 3:
{
uint32_t color_key = (chips->bitblt_running.bitblt.monochrome_source_expansion_color_reg_select)
? chips->bitblt_running.bitblt.source_key_bg
: chips->bitblt_running.bitblt.pattern_source_key_bg;
color_key &= (1 << (8 * (chips->bitblt_running.bytes_per_pixel))) - 1;
if (!!(color_key == dest_pixel) == !!(chips->bitblt_running.bitblt.bitblt_control & (1 << 16))) {
return;
}
break;
}
}
}
switch (chips->bitblt_running.bytes_per_pixel) {
case 1: /* 8 bits-per-pixel. */
{
chips_69000_do_rop_8bpp_patterned((uint8_t*)&dest_pixel, pattern_pixel, pixel, chips->bitblt_running.bitblt.bitblt_control & 0xFF);
break;
}
case 2: /* 16 bits-per-pixel. */
{
chips_69000_do_rop_16bpp_patterned((uint16_t*)&dest_pixel, pattern_pixel, pixel, chips->bitblt_running.bitblt.bitblt_control & 0xFF);
break;
}
case 3: /* 24 bits-per-pixel. */
{
chips_69000_do_rop_24bpp_patterned((uint32_t*)&dest_pixel, pattern_pixel, pixel, chips->bitblt_running.bitblt.bitblt_control & 0xFF);
break;
}
}
if (chips->bitblt_running.bitblt.bitblt_control & (1 << 14)) {
switch ((chips->bitblt_running.bitblt.bitblt_control >> 15) & 3) {
case 0:
case 2:
{
uint32_t color_key = (chips->bitblt_running.bitblt.monochrome_source_expansion_color_reg_select)
? chips->bitblt_running.bitblt.source_key_bg
: chips->bitblt_running.bitblt.pattern_source_key_bg;
color_key &= (1 << (8 * (chips->bitblt_running.bytes_per_pixel))) - 1;
dest_pixel &= (1 << (8 * (chips->bitblt_running.bytes_per_pixel))) - 1;
if (!!(color_key == dest_pixel) == !!(chips->bitblt_running.bitblt.bitblt_control & (1 << 16))) {
return;
}
break;
}
}
}
switch (chips->bitblt_running.bytes_per_pixel) {
case 1: /* 8 bits-per-pixel. */
{
chips_69000_writeb_linear(dest_addr, dest_pixel & 0xFF, chips);
break;
}
case 2: /* 16 bits-per-pixel. */
{
chips_69000_writeb_linear(dest_addr, dest_pixel & 0xFF, chips);
chips_69000_writeb_linear(dest_addr + 1, (dest_pixel >> 8) & 0xFF, chips);
break;
}
case 3: /* 24 bits-per-pixel. */
{
chips_69000_writeb_linear(dest_addr, dest_pixel & 0xFF, chips);
chips_69000_writeb_linear(dest_addr + 1, (dest_pixel >> 8) & 0xFF, chips);
chips_69000_writeb_linear(dest_addr + 2, (dest_pixel >> 16) & 0xFF, chips);
break;
}
}
}
void
chips_69000_process_mono_bit(chips_69000_t* chips, uint8_t val)
{
uint32_t pixel = 0x0;
uint8_t is_true = !!val;
uint32_t source_fg = chips->bitblt_running.bitblt.pattern_source_key_fg;
uint32_t source_bg = chips->bitblt_running.bitblt.pattern_source_key_bg;
if (!chips->engine_active)
return;
if (chips->bitblt_running.bitblt.monochrome_source_expansion_color_reg_select) {
source_fg = chips->bitblt_running.bitblt.source_key_fg;
source_bg = chips->bitblt_running.bitblt.source_key_bg;
}
if (chips->bitblt_running.bitblt.monochrome_source_initial_discard) {
chips->bitblt_running.bitblt.monochrome_source_initial_discard--;
return;
}
if (chips->bitblt_running.mono_bits_skip_left) {
chips->bitblt_running.mono_bits_skip_left--;
return;
}
if (!is_true && (chips->bitblt_running.bitblt.bitblt_control & (1 << 13))) {
goto advance;
}
pixel = is_true ? source_fg : source_bg;
pixel &= (1 << (8 * (chips->bitblt_running.bytes_per_pixel))) - 1;
chips_69000_process_pixel(chips, pixel);
advance:
chips->bitblt_running.x += chips->bitblt_running.x_dir;
chips->bitblt_running.count_x += 1;
if (chips->bitblt_running.count_x >= chips->bitblt_running.actual_destination_width) {
chips->bitblt_running.count_y += 1;
chips->bitblt_running.y += chips->bitblt_running.y_dir * 1;
chips->bitblt_running.count_x = 0;
chips->bitblt_running.x = 0;
chips->bitblt_running.mono_bits_skip_left = chips->bitblt_running.bitblt.monochrome_source_left_clip;
if (chips->bitblt_running.count_y >= (chips->bitblt_running.actual_destination_height))
chips_69000_bitblt_interrupt(chips);
}
}
void chips_69000_bitblt_write(chips_69000_t* chips, uint8_t data);
void
chips_69000_setup_bitblt(chips_69000_t* chips)
{
chips->engine_active = 1;
memset(&chips->bitblt_running, 0, sizeof(chips->bitblt_running));
chips->bitblt_running.bitblt = chips->bitblt;
chips->bitblt_running.actual_source_height = chips->bitblt.destination_height;
chips->bitblt_running.actual_destination_height = chips->bitblt.destination_height;
chips->bitblt_running.count_x = chips->bitblt_running.count_y = 0;
chips->bitblt_running.bytes_written = 0;
chips->bitblt_running.bytes_counter = 0;
chips->bitblt_running.bytes_in_line_written = 0;
chips->bitblt_running.bytes_skip = 0;
chips->bitblt_running.mono_bytes_pitch = 0;
chips->bitblt_running.mono_bits_skip_left = 0;
int orig_cycles = cycles;
if (chips->bitblt.bitblt_control & (1 << 23)) {
chips->bitblt_running.bytes_per_pixel = 1 + ((chips->bitblt.bitblt_control >> 24) & 3);
} else {
chips->bitblt_running.bytes_per_pixel = 1 + ((chips->ext_regs[0x20] >> 4) & 3);
}
chips->bitblt_running.actual_destination_width = chips->bitblt_running.bitblt.destination_width / chips->bitblt_running.bytes_per_pixel;
chips->bitblt_running.x = 0;
chips->bitblt_running.y = 0;
switch ((chips->bitblt_running.bitblt.bitblt_control >> 8) & 3) {
case 0:
chips->bitblt_running.x_dir = 1;
chips->bitblt_running.y_dir = 1;
break;
case 1:
chips->bitblt_running.x_dir = -1;
chips->bitblt_running.y_dir = 1;
if (!(chips->bitblt_running.bitblt.bitblt_control & (1 << 10)))
chips->bitblt_running.bitblt.source_addr -= (chips->bitblt_running.bytes_per_pixel - 1);
chips->bitblt_running.bitblt.destination_addr -= (chips->bitblt_running.bytes_per_pixel - 1);
break;
case 2:
chips->bitblt_running.x_dir = 1;
chips->bitblt_running.y_dir = -1;
break;
case 3:
chips->bitblt_running.x_dir = -1;
chips->bitblt_running.y_dir = -1;
if (!(chips->bitblt_running.bitblt.bitblt_control & (1 << 10)))
chips->bitblt_running.bitblt.source_addr -= (chips->bitblt_running.bytes_per_pixel - 1);
chips->bitblt_running.bitblt.destination_addr -= (chips->bitblt_running.bytes_per_pixel - 1);
break;
}
/* Drawing is pointless if monochrome pattern is enabled, monochrome write-masking is enabled and solid pattern is enabled. */
if ((chips->bitblt_running.bitblt.bitblt_control & (1 << 17))
&& (chips->bitblt_running.bitblt.bitblt_control & (1 << 18))
&& (chips->bitblt_running.bitblt.bitblt_control & (1 << 19))) {
chips_69000_bitblt_interrupt(chips);
return;
}
#if 0
if (chips->bitblt_running.bitblt.bitblt_control & (1 << 12)) {
pclog("C&T: Monochrome blit (monochrome_source_alignment = %d, "
"monochrome left clip = %d, "
"monochrome right clip = %d, "
"monochrome initial discard = %d, "
"destination_width = %d, destination_height = %d)\n", chips->bitblt_running.bitblt.monochrome_source_alignment,
chips->bitblt_running.bitblt.monochrome_source_left_clip,
chips->bitblt_running.bitblt.monochrome_source_right_clip,
chips->bitblt_running.bitblt.monochrome_source_initial_discard,
chips->bitblt_running.bitblt.destination_width,
chips->bitblt_running.bitblt.destination_height);
}
#endif
if (chips->bitblt_running.bitblt.bitblt_control & (1 << 10)) {
chips->bitblt_running.bitblt.source_addr &= 7;
if (!(chips->bitblt_running.bitblt.bitblt_control & (1 << 12))) {
/* Yes, the NT 4.0 and Linux drivers will send this many amount of bytes to the video adapter on quadword-boundary-crossing image blits.
This weird calculation is intended and deliberate.
*/
if ((chips->bitblt_running.bitblt.source_addr + (chips->bitblt_running.bitblt.destination_width)) > ((chips->bitblt_running.bitblt.destination_width + 7) & ~7))
chips->bitblt_running.bytes_skip = 8 + (((chips->bitblt_running.bitblt.destination_width + 7) & ~7) - chips->bitblt_running.bitblt.destination_width);
} else {
chips->bitblt_running.mono_bits_skip_left = chips->bitblt_running.bitblt.monochrome_source_left_clip;
if (chips->bitblt_running.bitblt.monochrome_source_alignment == 5)
chips->bitblt_running.bitblt.monochrome_source_alignment = 0;
if (chips->bitblt_running.bitblt.monochrome_source_alignment == 0) {
chips->bitblt_running.mono_bytes_pitch = ((chips->bitblt_running.actual_destination_width + chips->bitblt_running.bitblt.monochrome_source_left_clip + 63) & ~63) / 8;
}
}
return;
}
if (chips->bitblt_running.bitblt.bitblt_control & (1 << 12)) {
uint32_t source_addr = chips->bitblt_running.bitblt.source_addr;
while (chips->engine_active) {
switch (chips->bitblt_running.bitblt.monochrome_source_alignment) {
case 0: /* Source-span aligned. */
{
/* Note: This value means quadword-alignment when BitBLT port is the source. */
/* TODO: This is handled purely on a best case basis. */
uint32_t orig_count_y = chips->bitblt_running.count_y;
uint32_t orig_source_addr = chips->bitblt_running.bitblt.source_addr;
while (orig_count_y == chips->bitblt_running.count_y) {
int i = 0;
uint8_t data = chips_69000_readb_linear(orig_source_addr, chips);
orig_source_addr++;
for (i = 0; i < 8; i++) {
chips_69000_process_mono_bit(chips, !!(data & (1 << (7 - i))));
if (orig_count_y != chips->bitblt_running.count_y) {
break;
}
}
if ((source_addr + chips->bitblt_running.bitblt.source_span) == orig_source_addr)
break;
}
source_addr = chips->bitblt_running.bitblt.source_addr + chips->bitblt_running.bitblt.source_span;
chips->bitblt_running.bitblt.source_addr = source_addr;
break;
}
case 1: /* Bit-aligned */
case 2: /* Byte-aligned */
{
uint32_t data = chips_69000_readb_linear(source_addr, chips);
chips_69000_bitblt_write(chips, data & 0xFF);
source_addr += 1;
break;
}
case 3: /* Word-aligned*/
{
uint32_t data = chips_69000_readw_linear(source_addr, chips);
chips_69000_bitblt_write(chips, data & 0xFF);
chips_69000_bitblt_write(chips, (data >> 8) & 0xFF);
source_addr += 2;
break;
}
case 4: /* Doubleword-aligned*/
{
uint32_t data = chips_69000_readl_linear(source_addr, chips);
chips_69000_bitblt_write(chips, data & 0xFF);
chips_69000_bitblt_write(chips, (data >> 8) & 0xFF);
chips_69000_bitblt_write(chips, (data >> 16) & 0xFF);
chips_69000_bitblt_write(chips, (data >> 24) & 0xFF);
source_addr += 4;
break;
}
case 5: /* Quadword-aligned*/
{
uint64_t data = (uint64_t)chips_69000_readl_linear(source_addr, chips) | ((uint64_t)chips_69000_readl_linear(source_addr + 4, chips) << 32ull);
chips_69000_bitblt_write(chips, data & 0xFF);
chips_69000_bitblt_write(chips, (data >> 8) & 0xFF);
chips_69000_bitblt_write(chips, (data >> 16) & 0xFF);
chips_69000_bitblt_write(chips, (data >> 24) & 0xFF);
chips_69000_bitblt_write(chips, (data >> 32ull) & 0xFF);
chips_69000_bitblt_write(chips, (data >> 40ull) & 0xFF);
chips_69000_bitblt_write(chips, (data >> 48ull) & 0xFF);
chips_69000_bitblt_write(chips, (data >> 56ull) & 0xFF);
source_addr += 8;
break;
}
}
}
return;
}
do {
do {
uint32_t pixel = 0;
uint32_t source_addr = chips->bitblt_running.bitblt.source_addr + (chips->bitblt_running.y * chips->bitblt.source_span) + (chips->bitblt_running.x * chips->bitblt_running.bytes_per_pixel);
switch (chips->bitblt_running.bytes_per_pixel) {
case 1: /* 8 bits-per-pixel. */
{
pixel = chips_69000_readb_linear(source_addr, chips);
break;
}
case 2: /* 16 bits-per-pixel. */
{
pixel = chips_69000_readb_linear(source_addr, chips);
pixel |= chips_69000_readb_linear(source_addr + 1, chips) << 8;
break;
}
case 3: /* 24 bits-per-pixel. */
{
pixel = chips_69000_readb_linear(source_addr, chips);
pixel |= chips_69000_readb_linear(source_addr + 1, chips) << 8;
pixel |= chips_69000_readb_linear(source_addr + 2, chips) << 16;
break;
}
}
chips_69000_process_pixel(chips, pixel);
chips->bitblt_running.x += chips->bitblt_running.x_dir;
} while ((++chips->bitblt_running.count_x) < chips->bitblt_running.actual_destination_width);
chips->bitblt_running.y += chips->bitblt_running.y_dir;
chips->bitblt_running.count_x = 0;
chips->bitblt_running.x = 0;
} while ((++chips->bitblt_running.count_y) < chips->bitblt_running.actual_destination_height);
cycles = orig_cycles;
chips_69000_bitblt_interrupt(chips);
}
void
chips_69000_bitblt_write(chips_69000_t* chips, uint8_t data) {
if (!chips->engine_active) {
return;
}
if (chips->bitblt_running.bitblt.bitblt_control & (1 << 12)) {
int orig_cycles = cycles;
chips->bitblt_running.bytes_port[chips->bitblt_running.bytes_written++] = data;
if (chips->bitblt_running.bitblt.monochrome_source_alignment == 1) {
uint8_t val = chips->bitblt_running.bytes_port[0];
int i = 0;
chips->bitblt_running.bytes_written = 0;
for (i = 0; i < 8; i++) {
chips_69000_process_mono_bit(chips, !!(val & (1 << (7 - i))));
}
} else if (chips->bitblt_running.bitblt.monochrome_source_alignment == 0 && chips->bitblt_running.mono_bytes_pitch && chips->bitblt_running.mono_bytes_pitch == chips->bitblt_running.bytes_written) {
int orig_count_y = chips->bitblt_running.count_y;
int i = 0, j = 0;
chips->bitblt_running.bytes_written = 0;
for (j = 0; j < chips->bitblt_running.mono_bytes_pitch; j++) {
for (i = 0; i < 8; i++) {
chips_69000_process_mono_bit(chips, !!(chips->bitblt_running.bytes_port[j] & (1 << (7 - i))));
if (orig_count_y != chips->bitblt_running.count_y) {
cycles = orig_cycles;
return;
}
}
}
}
else if ((chips->bitblt_running.bitblt.monochrome_source_alignment == 0 && !chips->bitblt_running.mono_bytes_pitch)
|| chips->bitblt_running.bitblt.monochrome_source_alignment == 2) {
int orig_count_y = chips->bitblt_running.count_y;
int i = 0;
uint8_t val = chips->bitblt_running.bytes_port[0];
chips->bitblt_running.bytes_written = 0;
for (i = 0; i < 8; i++) {
chips_69000_process_mono_bit(chips, !!(val & (1 << (7 - i))));
if (orig_count_y != chips->bitblt_running.count_y && chips->bitblt_running.bitblt.monochrome_source_alignment != 1) {
cycles = orig_cycles;
return;
}
}
} else if (chips->bitblt_running.bitblt.monochrome_source_alignment == 3
&& chips->bitblt_running.bytes_written == 2) {
int orig_count_y = chips->bitblt_running.count_y;
int i = 0;
uint16_t val = (chips->bitblt_running.bytes_port[1]) | (chips->bitblt_running.bytes_port[0] << 8);
chips->bitblt_running.bytes_written = 0;
for (i = 0; i < 16; i++) {
chips_69000_process_mono_bit(chips, !!(val & (1 << (15 - i))));
if (orig_count_y != chips->bitblt_running.count_y) {
cycles = orig_cycles;
return;
}
}
} else if (chips->bitblt_running.bitblt.monochrome_source_alignment == 4
&& chips->bitblt_running.bytes_written == 4) {
int orig_count_y = chips->bitblt_running.count_y;
int i = 0;
uint32_t val = chips->bitblt_running.bytes_port[3] | (chips->bitblt_running.bytes_port[2] << 8) | (chips->bitblt_running.bytes_port[1] << 16) | (chips->bitblt_running.bytes_port[0] << 24);
chips->bitblt_running.bytes_written = 0;
for (i = 0; i < 32; i++) {
chips_69000_process_mono_bit(chips, !!(val & (1 << (31 - i))));
if (orig_count_y != chips->bitblt_running.count_y) {
cycles = orig_cycles;
return;
}
}
} else if (chips->bitblt_running.bitblt.monochrome_source_alignment == 5 && chips->bitblt_running.bytes_written == 8) {
int orig_count_y = chips->bitblt_running.count_y;
int i = 0;
uint64_t val = 0;
val |= chips->bitblt_running.bytes_port[7];
val |= chips->bitblt_running.bytes_port[6] << 8;
val |= chips->bitblt_running.bytes_port[5] << 16;
val |= chips->bitblt_running.bytes_port[4] << 24;
val |= (uint64_t)chips->bitblt_running.bytes_port[3] << 32ULL;
val |= (uint64_t)chips->bitblt_running.bytes_port[2] << 40ULL;
val |= (uint64_t)chips->bitblt_running.bytes_port[1] << 48ULL;
val |= (uint64_t)chips->bitblt_running.bytes_port[0] << 56ULL;
chips->bitblt_running.bytes_written = 0;
for (i = 0; i < 64; i++) {
chips_69000_process_mono_bit(chips, !!(val & (1 << (63 - i))));
if (orig_count_y != chips->bitblt_running.count_y) {
cycles = orig_cycles;
return;
}
}
}
cycles = orig_cycles;
return;
}
chips->bitblt_running.bytes_counter++;
if (chips->bitblt_running.bytes_counter <= (chips->bitblt_running.bitblt.source_addr)) {
return;
}
chips->bitblt_running.bytes_port[chips->bitblt_running.bytes_written++] = data;
if (chips->bitblt_running.bytes_written == chips->bitblt_running.bytes_per_pixel) {
int orig_cycles = cycles;
uint32_t source_pixel = chips->bitblt_running.bytes_port[0];
chips->bitblt_running.bytes_written = 0;
if (chips->bitblt_running.bytes_per_pixel >= 2)
source_pixel |= (chips->bitblt_running.bytes_port[1] << 8);
if (chips->bitblt_running.bytes_per_pixel >= 3)
source_pixel |= (chips->bitblt_running.bytes_port[2] << 16);
chips->bitblt_running.bytes_in_line_written += chips->bitblt_running.bytes_per_pixel;
chips_69000_process_pixel(chips, source_pixel);
cycles = orig_cycles;
chips->bitblt_running.x += chips->bitblt_running.x_dir;
if (chips->bitblt_running.bytes_in_line_written >= chips->bitblt_running.bitblt.destination_width) {
if (chips->bitblt_running.bytes_skip) {
chips->bitblt_running.bitblt.source_addr = chips->bitblt_running.bytes_skip;
}
else if (chips->bitblt_running.bitblt.destination_width & 7)
chips->bitblt_running.bitblt.source_addr = 8 - ((chips->bitblt_running.bitblt.destination_width) & 7);
else
chips->bitblt_running.bitblt.source_addr = 0;
chips->bitblt_running.y += chips->bitblt_running.y_dir;
chips->bitblt_running.count_y++;
chips->bitblt_running.bytes_counter = 0;
chips->bitblt_running.bytes_in_line_written = 0;
chips->bitblt_running.count_x = 0;
chips->bitblt_running.x = 0;
if (chips->bitblt_running.count_y >= chips->bitblt_running.actual_destination_height) {
chips_69000_bitblt_interrupt(chips);
return;
}
}
}
}
uint8_t
chips_69000_read_ext_reg(chips_69000_t* chips)
{
uint8_t index = chips->ext_index;
uint8_t val = chips->ext_regs[index];
switch (index) {
case 0x00:
val = 0x2C;
break;
case 0x01:
val = 0x10;
break;
case 0x02:
val = 0xC0;
break;
case 0x03:
val = 0x00;
break;
case 0x04:
val = 0x62;
break;
case 0x05:
val = 0x00;
break;
case 0x06:
val = chips->linear_mapping.base >> 24;
break;
case 0x08:
val = 0x02;
break;
case 0x0A:
val = chips->ext_regs[index] & 0x37;
break;
case 0x20:
val &= ~1;
val |= !!chips->engine_active;
/* TODO: Handle BitBLT reset, if required. */
break;
case 0x63:
{
val = chips->ext_regs[index];
if (!(chips->ext_regs[0x62] & 0x8))
val = (val & ~8) | (i2c_gpio_get_scl(chips->i2c) << 3);
if (!(chips->ext_regs[0x62] & 0x4))
val = (val & ~4) | (i2c_gpio_get_sda(chips->i2c) << 2);
break;
}
case 0x70:
val = 0x3;
break;
case 0x71:
val = 0b01101000;
break;
case 0xD0:
val |= 1;
break;
}
return val;
}
void
chips_69000_write_ext_reg(chips_69000_t* chips, uint8_t val)
{
switch (chips->ext_index) {
case 0xA:
chips->ext_regs[chips->ext_index] = val & 0x37;
chips_69000_recalc_banking(chips);
break;
case 0xB:
chips->ext_regs[chips->ext_index] = val & 0xD;
break;
case 0xE:
chips->ext_regs[chips->ext_index] = val & 0x7f;
chips_69000_recalc_banking(chips);
break;
case 0x9:
chips->ext_regs[chips->ext_index] = val & 0x3;
svga_recalctimings(&chips->svga);
break;
case 0x40:
chips->ext_regs[chips->ext_index] = val & 0x3;
chips_69000_recalc_banking(chips);
svga_recalctimings(&chips->svga);
break;
case 0x60:
chips->ext_regs[chips->ext_index] = val & 0x43;
break;
case 0x20:
chips->ext_regs[chips->ext_index] = val & 0x3f;
break;
case 0x61:
chips->ext_regs[chips->ext_index] = val & 0x7f;
svga_recalctimings(&chips->svga);
break;
case 0x62:
chips->ext_regs[chips->ext_index] = val & 0x9C;
break;
case 0x63:
{
uint8_t scl = 0, sda = 0;
if (chips->ext_regs[0x62] & 0x8)
scl = !!(val & 8);
else
scl = i2c_gpio_get_scl(chips->i2c);
if (chips->ext_regs[0x62] & 0x4)
sda = !!(val & 4);
else
scl = i2c_gpio_get_sda(chips->i2c);
i2c_gpio_set(chips->i2c, scl, sda);
chips->ext_regs[chips->ext_index] = val & 0x9F;
break;
}
case 0x67:
chips->ext_regs[chips->ext_index] = val & 0x2;
break;
case 0x80:
chips->ext_regs[chips->ext_index] = val & 0xBF;
svga_set_ramdac_type(&chips->svga, (val & 0x80) ? RAMDAC_8BIT : RAMDAC_6BIT);
break;
case 0x81:
chips->ext_regs[chips->ext_index] = val & 0x1f;
svga_recalctimings(&chips->svga);
break;
case 0x82:
chips->ext_regs[chips->ext_index] = val & 0xf;
chips->svga.lut_map = !!(val & 0x8);
break;
case 0xA0:
chips->ext_regs[chips->ext_index] = val;
chips->svga.hwcursor.ena = ((val & 7) == 0b101) || ((val & 7) == 0b1);
chips->svga.hwcursor.cur_xsize = chips->svga.hwcursor.cur_ysize = ((val & 7) == 0b1) ? 32 : 64;
break;
case 0xA2:
chips->ext_regs[chips->ext_index] = val;
chips->svga.hwcursor.addr = (val << 8) | ((chips->ext_regs[0xA3] & 0x3F) << 16);
break;
case 0xA3:
chips->ext_regs[chips->ext_index] = val;
chips->svga.hwcursor.addr = ((chips->ext_regs[0xA2]) << 8) | ((val & 0x3F) << 16);
break;
case 0xA4:
chips->ext_regs[chips->ext_index] = val;
chips->svga.hwcursor.x = val | (chips->ext_regs[0xA5] & 7) << 8;
if (chips->ext_regs[0xA5] & 0x80)
chips->svga.hwcursor.x = -chips->svga.hwcursor.x;
break;
case 0xA5:
chips->ext_regs[chips->ext_index] = val;
chips->svga.hwcursor.x = chips->ext_regs[0xA4] | (val & 7) << 8;
if (chips->ext_regs[0xA5] & 0x80)
chips->svga.hwcursor.x = -chips->svga.hwcursor.x;
break;
case 0xA6:
chips->ext_regs[chips->ext_index] = val;
chips->svga.hwcursor.y = val | (chips->ext_regs[0xA7] & 7) << 8;
if (chips->ext_regs[0xA7] & 0x80) {
chips->svga.hwcursor.y = -chips->svga.hwcursor.y;
}
break;
case 0xA7:
chips->ext_regs[chips->ext_index] = val;
chips->svga.hwcursor.y = chips->ext_regs[0xA6] | (val & 7) << 8;
if (chips->ext_regs[0xA7] & 0x80) {
chips->svga.hwcursor.y = -chips->svga.hwcursor.y;
}
break;
case 0xC8:
case 0xC9:
case 0xCB:
chips->ext_regs[chips->ext_index] = val;
svga_recalctimings(&chips->svga);
break;
case 0xD2:
break;
default:
chips->ext_regs[chips->ext_index] = val;
break;
}
}
void
chips_69000_out(uint16_t addr, uint8_t val, void *p)
{
chips_69000_t *chips = (chips_69000_t *) p;
svga_t *svga = &chips->svga;
uint8_t old, index;
if (((addr & 0xfff0) == 0x3d0 || (addr & 0xfff0) == 0x3b0) && !(svga->miscout & 1))
addr ^= 0x60;
switch (addr) {
case 0x3c0:
if (!(chips->ext_regs[0x09] & 0x02))
break;
svga->attraddr = val & 31;
if ((val & 0x20) != svga->attr_palette_enable) {
svga->fullchange = 3;
svga->attr_palette_enable = val & 0x20;
svga_recalctimings(svga);
}
return;
case 0x3c1:
if ((chips->ext_regs[0x09] & 0x02))
{
svga->attrff = 1;
svga_out(addr, val, svga);
svga->attrff = 0;
return;
}
break;
case 0x3c9:
if (!(chips->ext_regs[0x80] & 0x01))
break;
if (svga->adv_flags & FLAG_RAMDAC_SHIFT)
val <<= 2;
svga->fullchange = svga->monitor->mon_changeframecount;
switch (svga->dac_pos) {
case 0:
svga->dac_r = val;
svga->dac_pos++;
break;
case 1:
svga->dac_g = val;
svga->dac_pos++;
break;
case 2:
index = svga->dac_addr & 7;
chips->cursor_palette[index].r = svga->dac_r;
chips->cursor_palette[index].g = svga->dac_g;
chips->cursor_palette[index].b = val;
if (svga->ramdac_type == RAMDAC_8BIT)
chips->cursor_pallook[index] = makecol32(chips->cursor_palette[index].r, chips->cursor_palette[index].g, chips->cursor_palette[index].b);
else
chips->cursor_pallook[index] = makecol32(video_6to8[chips->cursor_palette[index].r & 0x3f], video_6to8[chips->cursor_palette[index].g & 0x3f], video_6to8[chips->cursor_palette[index].b & 0x3f]);
svga->dac_pos = 0;
svga->dac_addr = (svga->dac_addr + 1) & 255;
break;
}
return;
case 0x3c5:
svga_out(addr, val, svga);
chips_69000_recalc_banking(chips);
return;
case 0x3D0:
chips->flat_panel_index = val;
return;
case 0x3D1:
return chips_69000_write_flat_panel(chips, val);
case 0x3D2:
chips->mm_index = val;
return;
case 0x3D3:
return chips_69000_write_multimedia(chips, val);
case 0x3D4:
svga->crtcreg = val & 0xff;
return;
case 0x3D5:
if ((svga->crtcreg < 7) && (svga->crtc[0x11] & 0x80))
return;
if ((svga->crtcreg == 7) && (svga->crtc[0x11] & 0x80))
val = (svga->crtc[7] & ~0x10) | (val & 0x10);
old = svga->crtc[svga->crtcreg];
svga->crtc[svga->crtcreg] = val;
if (old != val) {
if (svga->crtcreg < 0xe || svga->crtcreg > 0x10) {
if ((svga->crtcreg == 0xc) || (svga->crtcreg == 0xd)) {
svga->fullchange = 3;
svga->ma_latch = ((svga->crtc[0xc] << 8) | svga->crtc[0xd]) + ((svga->crtc[8] & 0x60) >> 5);
} else {
svga->fullchange = changeframecount;
svga_recalctimings(svga);
}
}
}
break;
case 0x3B6:
case 0x3D6:
chips->ext_index = val;
return;
case 0x3B7:
case 0x3D7:
return chips_69000_write_ext_reg(chips, val);
}
svga_out(addr, val, svga);
}
uint8_t
chips_69000_in(uint16_t addr, void *p)
{
chips_69000_t *chips = (chips_69000_t *) p;
svga_t *svga = &chips->svga;
uint8_t temp = 0, index;
if (((addr & 0xfff0) == 0x3d0 || (addr & 0xfff0) == 0x3b0) && !(svga->miscout & 1))
addr ^= 0x60;
switch (addr) {
case 0x3C5:
return svga->seqregs[svga->seqaddr];
case 0x3c9:
if (!(chips->ext_regs[0x80] & 0x01)) {
temp = svga_in(addr, svga);
break;
}
index = (svga->dac_addr - 1) & 7;
switch (svga->dac_pos) {
case 0:
svga->dac_pos++;
if (svga->ramdac_type == RAMDAC_8BIT)
temp = chips->cursor_palette[index].r;
else
temp = chips->cursor_palette[index].r & 0x3f;
break;
case 1:
svga->dac_pos++;
if (svga->ramdac_type == RAMDAC_8BIT)
temp = chips->cursor_palette[index].g;
else
temp = chips->cursor_palette[index].g & 0x3f;
break;
case 2:
svga->dac_pos = 0;
svga->dac_addr = (svga->dac_addr + 1) & 255;
if (svga->ramdac_type == RAMDAC_8BIT)
temp = chips->cursor_palette[index].b;
else
temp = chips->cursor_palette[index].b & 0x3f;
break;
}
if (svga->adv_flags & FLAG_RAMDAC_SHIFT)
temp >>= 2;
break;
case 0x3D0:
return chips->flat_panel_index;
case 0x3D1:
return chips_69000_read_flat_panel(chips);
case 0x3D2:
return chips->mm_index;
case 0x3D3:
return chips_69000_read_multimedia(chips);
case 0x3D4:
temp = svga->crtcreg;
break;
case 0x3D5:
if (svga->crtcreg & 0x20)
temp = 0xff;
else
temp = svga->crtc[svga->crtcreg];
break;
case 0x3B6:
case 0x3D6:
temp = chips->ext_index;
break;
case 0x3B7:
case 0x3D7:
temp = chips_69000_read_ext_reg(chips);
break;
default:
temp = svga_in(addr, svga);
break;
}
return temp;
}
static uint8_t
chips_69000_pci_read(int func, int addr, void *p)
{
chips_69000_t *chips = (chips_69000_t *) p;
{
switch (addr) {
case 0x00:
return 0x2C;
case 0x01:
return 0x10;
case 0x02:
return 0xC0;
case 0x03:
return 0x00;
case 0x04:
return (chips->pci_conf_status & 0b11100011) | 0x80;
case 0x06:
return 0x80;
case 0x07:
return 0x02;
case 0x08:
case 0x09:
case 0x0a:
return 0x00;
case 0x0b:
return 0x03;
case 0x13:
return chips->linear_mapping.base >> 24;
case 0x30:
return chips->pci_rom_enable & 0x1;
case 0x31:
return 0x0;
case 0x32:
return chips->rom_addr & 0xFF;
case 0x33:
return (chips->rom_addr & 0xFF00) >> 8;
case 0x3c:
return chips->pci_line_interrupt;
case 0x3d:
return 0x01;
case 0x2C:
case 0x2D:
case 0x6C:
case 0x6D:
return (chips->subsys_vid >> ((addr & 1) * 8)) & 0xFF;
case 0x2E:
case 0x2F:
case 0x6E:
case 0x6F:
return (chips->subsys_pid >> ((addr & 1) * 8)) & 0xFF;
default:
return 0x00;
}
}
}
static void
chips_69000_pci_write(int func, int addr, uint8_t val, void *p)
{
chips_69000_t *chips = (chips_69000_t *) p;
{
switch (addr) {
case 0x04:
{
chips->pci_conf_status = val;
io_removehandler(0x03c0, 0x0020, chips_69000_in, NULL, NULL, chips_69000_out, NULL, NULL, chips);
mem_mapping_disable(&chips->linear_mapping);
mem_mapping_disable(&chips->svga.mapping);
if (chips->pci_conf_status & PCI_COMMAND_IO) {
io_sethandler(0x03c0, 0x0020, chips_69000_in, NULL, NULL, chips_69000_out, NULL, NULL, chips);
}
if (chips->pci_conf_status & PCI_COMMAND_MEM) {
mem_mapping_enable(&chips->svga.mapping);
if (chips->linear_mapping.base)
mem_mapping_set_addr(&chips->linear_mapping, chips->linear_mapping.base, (1 << 24));
}
break;
}
case 0x13:
{
chips->linear_mapping.base = val << 24;
if (chips->linear_mapping.base)
mem_mapping_set_addr(&chips->linear_mapping, chips->linear_mapping.base, (1 << 24));
break;
}
case 0x3c:
chips->pci_line_interrupt = val;
break;
case 0x30:
if (chips->on_board) break;
chips->pci_rom_enable = val & 0x1;
mem_mapping_disable(&chips->bios_rom.mapping);
if (chips->pci_rom_enable & 1) {
mem_mapping_set_addr(&chips->bios_rom.mapping, chips->rom_addr << 16, 0x10000);
}
break;
case 0x32:
if (chips->on_board) break;
chips->rom_addr &= ~0xFF;
chips->rom_addr |= val & 0xFC;
if (chips->pci_rom_enable & 1) {
mem_mapping_set_addr(&chips->bios_rom.mapping, chips->rom_addr << 16, 0x10000);
}
break;
case 0x33:
if (chips->on_board) break;
chips->rom_addr &= ~0xFF00;
chips->rom_addr |= (val << 8);
if (chips->pci_rom_enable & 1) {
mem_mapping_set_addr(&chips->bios_rom.mapping, chips->rom_addr << 16, 0x10000);
}
break;
case 0x6C:
case 0x6D:
chips->subsys_vid_b[addr & 1] = val;
break;
case 0x6E:
case 0x6F:
chips->subsys_pid_b[addr & 1] = val;
break;
}
}
}
uint8_t
chips_69000_readb_mmio(uint32_t addr, chips_69000_t* chips)
{
addr &= 0xFFF;
switch (addr & 0xFFF) {
case 0x00 ... 0x2B:
if (addr == 0x13) {
return (chips->bitblt_regs_b[addr & 0xFF] & 0x7F) | (chips->engine_active ? 0x80 : 0x00);
}
return chips->bitblt_regs_b[addr & 0xFF];
case 0x3b:
return (chips->engine_active ? 0x80 : 0x00);
case 0x38:
return 0x7F;
case 0x600 ... 0x60F:
return chips->mem_regs_b[addr & 0xF];
case 0x768:
return chips_69000_in(0x3b4, chips);
case 0x769:
return chips_69000_in(0x3b5, chips);
case 0x774:
return chips_69000_in(0x3ba, chips);
case 0x780:
return chips_69000_in(0x3c0, chips);
case 0x781:
return chips_69000_in(0x3c1, chips);
case 0x784:
return chips_69000_in(0x3c2, chips);
case 0x788:
return chips_69000_in(0x3c4, chips);
case 0x789:
return chips_69000_in(0x3c5, chips);
case 0x78C:
return chips_69000_in(0x3c6, chips);
case 0x78D:
return chips_69000_in(0x3c7, chips);
case 0x790:
return chips_69000_in(0x3c8, chips);
case 0x791:
return chips_69000_in(0x3c9, chips);
case 0x794:
return chips_69000_in(0x3ca, chips);
case 0x798:
return chips_69000_in(0x3cc, chips);
case 0x79C:
return chips_69000_in(0x3ce, chips);
case 0x79D:
return chips_69000_in(0x3cf, chips);
case 0x7A0:
return chips_69000_in(0x3d0, chips);
case 0x7A1:
return chips_69000_in(0x3d1, chips);
case 0x7A4:
return chips_69000_in(0x3d2, chips);
case 0x7A5:
return chips_69000_in(0x3d3, chips);
case 0x7A8:
return chips_69000_in(0x3d4, chips);
case 0x7A9:
return chips_69000_in(0x3d5, chips);
case 0x7AC:
return chips_69000_in(0x3d6, chips);
case 0x7AD:
return chips_69000_in(0x3d7, chips);
case 0x7B4:
return chips_69000_in(0x3da, chips);
}
return 0x00;
}
uint16_t
chips_69000_readw_mmio(uint32_t addr, chips_69000_t* chips)
{
addr &= 0xFFF;
switch (addr & 0xFFF) {
default:
return chips_69000_readb_mmio(addr, chips) | (chips_69000_readb_mmio(addr + 1, chips) << 8);
}
return 0xFFFF;
}
uint32_t
chips_69000_readl_mmio(uint32_t addr, chips_69000_t* chips)
{
addr &= 0xFFF;
switch (addr & 0xFFF) {
default:
return chips_69000_readw_mmio(addr, chips) | (chips_69000_readw_mmio(addr + 2, chips) << 16);
}
return 0xFFFFFFFF;
}
void
chips_69000_writeb_mmio(uint32_t addr, uint8_t val, chips_69000_t* chips)
{
//pclog("C&T Write 0x%X, val = 0x%02X\n", addr, val);
if (addr & 0x10000) {
chips_69000_bitblt_write(chips, val);
return;
}
addr &= 0xFFF;
switch (addr & 0xFFF) {
case 0x00 ... 0x2B:
if (addr <= 0x3) {
//pclog("[%04X:%08X] C&T Write span 0x%X, val = 0x%02X\n", CS, cpu_state.pc, addr, val);
}
chips->bitblt_regs_b[addr & 0xFF] = val;
if ((addr & 0xFFF) == 0x023 && chips->bitblt_regs[0x8] != 0) {
chips_69000_setup_bitblt(chips);
}
break;
default:
pclog("C&T Write (unknown) 0x%X, val = 0x%02X\n", addr, val);
break;
case 0x600 ... 0x60F:
switch (addr & 0xFFF)
{
case 0x600 ... 0x603:
{
chips->mem_regs_b[addr & 0xF] = val;
chips->mem_regs[(addr >> 2) & 0x3] &= 0x80004040;
if (addr == 0x605 || addr == 0x607)
chips_69000_interrupt(chips);
break;
}
case 0x604 ... 0x607:
{
chips->mem_regs_b[addr & 0xF] &= ~val;
chips->mem_regs[(addr >> 2) & 0x3] &= 0x80004040;
if (addr == 0x605 || addr == 0x607)
chips_69000_interrupt(chips);
break;
}
case 0x60c ... 0x60f:
{
chips->mem_regs_b[addr & 0xF] = val;
break;
}
}
chips->mem_regs_b[addr & 0xF] = val;
break;
case 0x768:
chips_69000_out(0x3b4, val, chips); break;
case 0x769:
chips_69000_out(0x3b5, val, chips); break;
case 0x774:
chips_69000_out(0x3ba, val, chips); break;
case 0x780:
chips_69000_out(0x3c0, val, chips); break;
case 0x781:
chips_69000_out(0x3c1, val, chips); break;
case 0x784:
chips_69000_out(0x3c2, val, chips); break;
case 0x788:
chips_69000_out(0x3c4, val, chips); break;
case 0x789:
chips_69000_out(0x3c5, val, chips); break;
case 0x78C:
chips_69000_out(0x3c6, val, chips); break;
case 0x78D:
chips_69000_out(0x3c7, val, chips); break;
case 0x790:
chips_69000_out(0x3c8, val, chips); break;
case 0x791:
chips_69000_out(0x3c9, val, chips); break;
case 0x794:
chips_69000_out(0x3ca, val, chips); break;
case 0x798:
chips_69000_out(0x3cc, val, chips); break;
case 0x79C:
chips_69000_out(0x3ce, val, chips); break;
case 0x79D:
chips_69000_out(0x3cf, val, chips); break;
case 0x7A0:
chips_69000_out(0x3d0, val, chips); break;
case 0x7A1:
chips_69000_out(0x3d1, val, chips); break;
case 0x7A4:
chips_69000_out(0x3d2, val, chips); break;
case 0x7A5:
chips_69000_out(0x3d3, val, chips); break;
case 0x7A8:
chips_69000_out(0x3d4, val, chips); break;
case 0x7A9:
chips_69000_out(0x3d5, val, chips); break;
case 0x7AC:
chips_69000_out(0x3d6, val, chips); break;
case 0x7AD:
chips_69000_out(0x3d7, val, chips); break;
case 0x7B4:
chips_69000_out(0x3da, val, chips); break;
}
}
void
chips_69000_writew_mmio(uint32_t addr, uint16_t val, chips_69000_t* chips)
{
if (addr & 0x10000) {
if ((chips->bitblt_running.bitblt.bitblt_control & (1 << 12))) {
//pclog("BitBLT mono 0x%04X\n", val);
}
chips_69000_bitblt_write(chips, val & 0xFF);
chips_69000_bitblt_write(chips, (val >> 8) & 0xFF);
return;
}
addr &= 0xFFF;
switch (addr & 0xFFF) {
default:
chips_69000_writeb_mmio(addr, val, chips);
chips_69000_writeb_mmio(addr + 1, val >> 8, chips);
break;
}
}
void
chips_69000_writel_mmio(uint32_t addr, uint32_t val, chips_69000_t* chips)
{
if (addr & 0x10000) {
if ((chips->bitblt_running.bitblt.bitblt_control & (1 << 12))) {
//pclog("BitBLT mono 0x%08X\n", val);
}
chips_69000_bitblt_write(chips, val & 0xFF);
chips_69000_bitblt_write(chips, (val >> 8) & 0xFF);
chips_69000_bitblt_write(chips, (val >> 16) & 0xFF);
chips_69000_bitblt_write(chips, (val >> 24) & 0xFF);
return;
}
addr &= 0xFFF;
switch (addr & 0xFFF) {
default:
chips_69000_writew_mmio(addr, val, chips);
chips_69000_writew_mmio(addr + 2, val >> 16, chips);
break;
}
}
uint8_t
chips_69000_readb_linear(uint32_t addr, void *p)
{
svga_t *svga = (svga_t *) p;
chips_69000_t *chips = (chips_69000_t *) svga->priv;
if (addr & 0x400000)
return chips_69000_readb_mmio(addr, chips);
return svga_readb_linear(addr & 0x1FFFFF, p);
}
uint16_t
chips_69000_readw_linear(uint32_t addr, void *p)
{
svga_t *svga = (svga_t *) p;
chips_69000_t *chips = (chips_69000_t *) svga->priv;
if (addr & 0x800000) {
if (addr & 0x400000)
return bswap16(chips_69000_readw_mmio(addr, chips));
return bswap16(svga_readw_linear(addr & 0x1FFFFF, p));
}
if (addr & 0x400000)
return chips_69000_readw_mmio(addr, chips);
return svga_readw_linear(addr & 0x1FFFFF, p);
}
uint32_t
chips_69000_readl_linear(uint32_t addr, void *p)
{
svga_t *svga = (svga_t *) p;
chips_69000_t *chips = (chips_69000_t *) svga->priv;
if (addr & 0x800000) {
if (addr & 0x400000)
return bswap32(chips_69000_readl_mmio(addr, chips));
return bswap32(svga_readl_linear(addr & 0x1FFFFF, p));
}
if (addr & 0x400000)
return chips_69000_readl_mmio(addr, chips);
return svga_readl_linear(addr & 0x1FFFFF, p);
}
void
chips_69000_writeb_linear(uint32_t addr, uint8_t val, void *p)
{
svga_t *svga = (svga_t *) p;
chips_69000_t *chips = (chips_69000_t *) svga->priv;
if (addr & 0x400000)
return chips_69000_writeb_mmio(addr, val, chips);
svga_writeb_linear(addr & 0x1FFFFF, val, p);
}
void
chips_69000_writew_linear(uint32_t addr, uint16_t val, void *p)
{
svga_t *svga = (svga_t *) p;
chips_69000_t *chips = (chips_69000_t *) svga->priv;
if (addr & 0x800000)
val = bswap16(val);
if (addr & 0x400000)
return chips_69000_writew_mmio(addr, val, chips);
svga_writew_linear(addr & 0x1FFFFF, val, p);
}
void
chips_69000_writel_linear(uint32_t addr, uint32_t val, void *p)
{
svga_t *svga = (svga_t *) p;
chips_69000_t *chips = (chips_69000_t *) svga->priv;
if (addr & 0x800000)
val = bswap32(val);
if (addr & 0x400000)
return chips_69000_writel_mmio(addr, val, chips);
svga_writel_linear(addr & 0x1FFFFF, val, p);
}
void
chips_69000_vblank_start(svga_t *svga)
{
chips_69000_t *chips = (chips_69000_t *) svga->priv;
chips->mem_regs[1] |= 1 << 14;
chips->svga.crtc[0x40] &= ~0x80;
chips_69000_interrupt(chips);
}
static void
chips_69000_hwcursor_draw_64x64(svga_t *svga, int displine)
{
chips_69000_t *chips = (chips_69000_t *) svga->priv;
uint64_t dat[2];
int offset = svga->hwcursor_latch.x - svga->hwcursor_latch.xoff;
if (svga->interlace && svga->hwcursor_oddeven)
svga->hwcursor_latch.addr += 16;
dat[1] = bswap64(*(uint64_t *) (&svga->vram[svga->hwcursor_latch.addr]));
dat[0] = bswap64(*(uint64_t *) (&svga->vram[svga->hwcursor_latch.addr + 8]));
svga->hwcursor_latch.addr += 16;
for (uint8_t x = 0; x < 64; x++) {
if (!(dat[1] & (1ULL << 63)))
svga->monitor->target_buffer->line[displine][(offset + svga->x_add) & 2047] = (dat[0] & (1ULL << 63)) ? svga_lookup_lut_ram(svga, chips->cursor_pallook[5]) : svga_lookup_lut_ram(svga, chips->cursor_pallook[4]);
else if (dat[0] & (1ULL << 63))
svga->monitor->target_buffer->line[displine][(offset + svga->x_add) & 2047] ^= 0xffffff;
offset++;
dat[0] <<= 1;
dat[1] <<= 1;
}
if (svga->interlace && !svga->hwcursor_oddeven)
svga->hwcursor_latch.addr += 16;
}
static void
chips_69000_hwcursor_draw(svga_t *svga, int displine)
{
chips_69000_t *chips = (chips_69000_t *) svga->priv;
uint64_t dat[2];
int offset = svga->hwcursor_latch.x - svga->hwcursor_latch.xoff;
if ((chips->ext_regs[0xa0] & 7) == 0b101)
return chips_69000_hwcursor_draw_64x64(svga, displine);
if (svga->interlace) {
dat[1] = bswap64(*(uint64_t *) (&svga->vram[svga->hwcursor_latch.addr]));
dat[0] = bswap64(*(uint64_t *) (&svga->vram[svga->hwcursor_latch.addr + 8]));
svga->hwcursor_latch.addr += 16;
if (svga->hwcursor_oddeven) {
dat[1] <<= 32ULL;
dat[0] <<= 32ULL;
}
for (uint8_t x = 0; x < 32; x++) {
if (!(dat[1] & (1ULL << 63)))
svga->monitor->target_buffer->line[displine & 2047][(offset + svga->x_add) & 2047] = (dat[0] & (1ULL << 63)) ? svga_lookup_lut_ram(svga, chips->cursor_pallook[5]) : svga_lookup_lut_ram(svga, chips->cursor_pallook[4]);
else if (dat[0] & (1ULL << 63))
svga->monitor->target_buffer->line[displine & 2047][(offset + svga->x_add) & 2047] ^= 0xffffff;
offset++;
dat[0] <<= 1;
dat[1] <<= 1;
}
return;
}
if ((svga->hwcursor_on & 1)) {
dat[1] = bswap64(*(uint64_t *) (&svga->vram[svga->hwcursor_latch.addr - 16]));
dat[0] = bswap64(*(uint64_t *) (&svga->vram[(svga->hwcursor_latch.addr - 16) + 8]));
dat[1] <<= 32ULL;
dat[0] <<= 32ULL;
}
else {
dat[1] = bswap64(*(uint64_t *) (&svga->vram[svga->hwcursor_latch.addr]));
dat[0] = bswap64(*(uint64_t *) (&svga->vram[svga->hwcursor_latch.addr + 8]));
svga->hwcursor_latch.addr += 16;
}
for (uint8_t x = 0; x < 32; x++) {
if (!(dat[1] & (1ULL << 63)))
svga->monitor->target_buffer->line[displine & 2047][(offset + svga->x_add) & 2047] = (dat[0] & (1ULL << 63)) ? svga_lookup_lut_ram(svga, chips->cursor_pallook[5]) : svga_lookup_lut_ram(svga, chips->cursor_pallook[4]);
else if (dat[0] & (1ULL << 63))
svga->monitor->target_buffer->line[displine & 2047][(offset + svga->x_add) & 2047] ^= 0xffffff;
offset++;
dat[0] <<= 1;
dat[1] <<= 1;
}
}
static float
chips_69000_getclock(int clock, void *priv)
{
const chips_69000_t *chips = (chips_69000_t *) priv;
if (clock == 0)
return 25175000.0;
if (clock == 1)
return 28322000.0;
int m = chips->ext_regs[0xc8];
int n = chips->ext_regs[0xc9];
int pl = ((chips->ext_regs[0xcb] >> 4) & 7);
float fvco = 14318181.0 * ((float)(m + 2) / (float)(n + 2));
if (chips->ext_regs[0xcb] & 4)
fvco *= 4.0;
float fo = fvco / (float)(1 << pl);
return fo;
}
uint32_t
chips_69000_conv_16to32(svga_t* svga, uint16_t color, uint8_t bpp)
{
uint32_t ret = 0x00000000;
if (svga->lut_map) {
if (bpp == 15) {
uint8_t b = getcolr(svga->pallook[(color & 0x1f) << 3]);
uint8_t g = getcolg(svga->pallook[(color & 0x3e0) >> 2]);
uint8_t r = getcolb(svga->pallook[(color & 0x7c00) >> 7]);
ret = (video_15to32[color] & 0xFF000000) | makecol(r, g, b);
} else {
uint8_t b = getcolr(svga->pallook[(color & 0x1f) << 3]);
uint8_t g = getcolg(svga->pallook[(color & 0x7e0) >> 3]);
uint8_t r = getcolb(svga->pallook[(color & 0xf800) >> 8]);
ret = (video_16to32[color] & 0xFF000000) | makecol(r, g, b);
}
} else
ret = (bpp == 15) ? video_15to32[color] : video_16to32[color];
return ret;
}
static int
chips_69000_line_compare(svga_t* svga)
{
const chips_69000_t *chips = (chips_69000_t *) svga->priv;
if (chips->ext_regs[0x81] & 0xF) {
return 0;
}
return 1;
}
static void
chips_69000_disable_handlers(chips_69000_t *chips)
{
io_removehandler(0x03c0, 0x0020, chips_69000_in, NULL, NULL, chips_69000_out, NULL, NULL, chips);
mem_mapping_disable(&chips->linear_mapping);
mem_mapping_disable(&chips->svga.mapping);
if (!chips->on_board)
mem_mapping_disable(&chips->bios_rom.mapping);
/* Save all the mappings and the timers because they are part of linked lists. */
reset_state->linear_mapping = chips->linear_mapping;
reset_state->svga.mapping = chips->svga.mapping;
reset_state->bios_rom.mapping = chips->bios_rom.mapping;
reset_state->decrement_timer = chips->decrement_timer;
reset_state->svga.timer = chips->svga.timer;
reset_state->svga.timer8514 = chips->svga.timer8514;
}
static void
chips_69000_reset(void *priv)
{
chips_69000_t *chips = (chips_69000_t *) priv;
if (reset_state != NULL) {
chips_69000_disable_handlers(chips);
reset_state->slot = chips->slot;
*chips = *reset_state;
}
}
static void *
chips_69000_init(const device_t *info)
{
chips_69000_t *chips = calloc(1, sizeof(chips_69000_t));
reset_state = calloc(1, sizeof(chips_69000_t));
/* Appears to have an odd VBIOS size. */
if (!info->local) {
rom_init(&chips->bios_rom, "roms/video/chips/69000.ROM", 0xc0000, 0x10000, 0xffff, 0x0000, MEM_MAPPING_EXTERNAL);
mem_mapping_disable(&chips->bios_rom.mapping);
}
video_inform(VIDEO_FLAG_TYPE_SPECIAL, &timing_chips);
svga_init(info, &chips->svga, chips, 1 << 21, /*2048kb*/
chips_69000_recalctimings,
chips_69000_in, chips_69000_out,
chips_69000_hwcursor_draw,
NULL);
io_sethandler(0x03c0, 0x0020, chips_69000_in, NULL, NULL, chips_69000_out, NULL, NULL, chips);
pci_add_card(info->local ? PCI_ADD_VIDEO : PCI_ADD_NORMAL, chips_69000_pci_read, chips_69000_pci_write, chips, &chips->slot);
chips->svga.bpp = 8;
chips->svga.miscout = 1;
chips->svga.vblank_start = chips_69000_vblank_start;
chips->svga.getclock = chips_69000_getclock;
chips->svga.conv_16to32 = chips_69000_conv_16to32;
chips->svga.line_compare = chips_69000_line_compare;
mem_mapping_add(&chips->linear_mapping, 0, 0, chips_69000_readb_linear, chips_69000_readw_linear, chips_69000_readl_linear, chips_69000_writeb_linear, chips_69000_writew_linear, chips_69000_writel_linear, NULL, MEM_MAPPING_EXTERNAL, chips);
chips->quit = 0;
chips->engine_active = 0;
chips->on_board = !!(info->local);
chips->svga.packed_chain4 = 1;
timer_add(&chips->decrement_timer, chips_69000_decrement_timer, chips, 0);
timer_on_auto(&chips->decrement_timer, 1000000. / 2000.);
chips->i2c = i2c_gpio_init("ddc_chips_69000");
chips->ddc = ddc_init(i2c_gpio_get_bus(chips->i2c));
chips->flat_panel_regs[0x01] = 1;
*reset_state = *chips;
return chips;
}
static int
chips_69000_available(void)
{
return rom_present("roms/video/chips/69000.ROM");
}
void
chips_69000_close(void *p)
{
chips_69000_t *chips = (chips_69000_t *) p;
chips->quit = 1;
// thread_set_event(chips->fifo_event);
// thread_wait(chips->accel_thread);
ddc_close(chips->ddc);
i2c_gpio_close(chips->i2c);
svga_close(&chips->svga);
free(reset_state);
reset_state = NULL;
free(chips);
}
void
chips_69000_speed_changed(void *p)
{
chips_69000_t *chips = (chips_69000_t *) p;
svga_recalctimings(&chips->svga);
}
void
chips_69000_force_redraw(void *p)
{
chips_69000_t *chips = (chips_69000_t *) p;
chips->svga.fullchange = chips->svga.monitor->mon_changeframecount;
}
const device_t chips_69000_device = {
.name = "Chips & Technologies B69000",
.internal_name = "chips_69000",
.flags = DEVICE_PCI,
.local = 0,
.init = chips_69000_init,
.close = chips_69000_close,
.reset = chips_69000_reset,
{ .available = chips_69000_available },
.speed_changed = chips_69000_speed_changed,
.force_redraw = chips_69000_force_redraw,
.config = NULL
};
const device_t chips_69000_onboard_device = {
.name = "Chips & Technologies B69000 On-Board",
.internal_name = "chips_69000_onboard",
.flags = DEVICE_PCI,
.local = 1,
.init = chips_69000_init,
.close = chips_69000_close,
.reset = chips_69000_reset,
{ .available = chips_69000_available },
.speed_changed = chips_69000_speed_changed,
.force_redraw = chips_69000_force_redraw,
.config = NULL
};
``` | /content/code_sandbox/src/video/vid_chips_69000.c | c | 2016-06-25T22:29:10 | 2024-08-16T19:09:21 | 86Box | 86Box/86Box | 2,616 | 26,053 |
```c
/*
* 86Box A hypervisor and IBM PC system emulator that specializes in
* running old operating systems and software designed for IBM
* PC systems and compatibles from 1981 through fairly recent
* system designs based on the PCI bus.
*
* This file is part of the 86Box distribution.
*
* Emulation of the old and new IBM CGA graphics cards.
*
*
*
* Authors: Sarah Walker, <path_to_url
* Miran Grca, <mgrca8@gmail.com>
* W. M. Martinez, <anikom15@outlook.com>
*
*/
#include <stdio.h>
#include <stdint.h>
#include <string.h>
#include <stdlib.h>
#include <wchar.h>
#include <math.h>
#include <86box/86box.h>
#include "cpu.h"
#include <86box/io.h>
#include <86box/timer.h>
#include <86box/pit.h>
#include <86box/mem.h>
#include <86box/rom.h>
#include <86box/device.h>
#include <86box/video.h>
#include <86box/vid_cga.h>
#include <86box/vid_cga_comp.h>
#include <86box/plat_unused.h>
#define CGA_RGB 0
#define CGA_COMPOSITE 1
#define COMPOSITE_OLD 0
#define COMPOSITE_NEW 1
#define DOUBLE_NONE 0
#define DOUBLE_SIMPLE 1
#define DOUBLE_INTERPOLATE_SRGB 2
#define DOUBLE_INTERPOLATE_LINEAR 3
typedef union
{
uint32_t color;
struct {
uint8_t b;
uint8_t g;
uint8_t r;
uint8_t a;
};
} color_t;
static uint8_t crtcmask[32] = {
0xff, 0xff, 0xff, 0xff, 0x7f, 0x1f, 0x7f, 0x7f, 0xf3, 0x1f, 0x7f, 0x1f, 0x3f, 0xff, 0x3f, 0xff,
0xff, 0xff, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
};
static uint8_t interp_lut[2][256][256];
static video_timings_t timing_cga = { .type = VIDEO_ISA, .write_b = 8, .write_w = 16, .write_l = 32, .read_b = 8, .read_w = 16, .read_l = 32 };
void cga_recalctimings(cga_t *cga);
void
cga_out(uint16_t addr, uint8_t val, void *priv)
{
cga_t *cga = (cga_t *) priv;
uint8_t old;
if ((addr >= 0x3d0) && (addr <= 0x3d7))
addr = (addr & 0xff9) | 0x004;
switch (addr) {
case 0x3D4:
cga->crtcreg = val & 31;
return;
case 0x3D5:
old = cga->crtc[cga->crtcreg];
cga->crtc[cga->crtcreg] = val & crtcmask[cga->crtcreg];
if (old != val) {
if ((cga->crtcreg < 0xe) || (cga->crtcreg > 0x10)) {
cga->fullchange = changeframecount;
cga_recalctimings(cga);
}
}
return;
case 0x3D8:
old = cga->cgamode;
cga->cgamode = val;
if (old ^ val) {
if ((old ^ val) & 0x07)
update_cga16_color(val);
cga_recalctimings(cga);
}
return;
case 0x3D9:
old = cga->cgacol;
cga->cgacol = val;
if (old ^ val)
cga_recalctimings(cga);
return;
default:
break;
}
}
uint8_t
cga_in(uint16_t addr, void *priv)
{
const cga_t *cga = (cga_t *) priv;
uint8_t ret = 0xff;
if ((addr >= 0x3d0) && (addr <= 0x3d7))
addr = (addr & 0xff9) | 0x004;
switch (addr) {
case 0x3D4:
ret = cga->crtcreg;
break;
case 0x3D5:
ret = cga->crtc[cga->crtcreg];
break;
case 0x3DA:
ret = cga->cgastat;
break;
default:
break;
}
return ret;
}
void
cga_pravetz_out(UNUSED(uint16_t addr), uint8_t val, void *priv)
{
cga_t *cga = (cga_t *) priv;
cga->fontbase = (((unsigned int) val) << 8);
}
uint8_t
cga_pravetz_in(UNUSED(uint16_t addr), void *priv)
{
const cga_t *cga = (cga_t *) priv;
return (cga->fontbase >> 8);
}
void
cga_waitstates(UNUSED(void *priv))
{
int ws_array[16] = { 3, 4, 5, 6, 7, 8, 4, 5, 6, 7, 8, 4, 5, 6, 7, 8 };
int ws;
ws = ws_array[cycles & 0xf];
cycles -= ws;
}
void
cga_write(uint32_t addr, uint8_t val, void *priv)
{
cga_t *cga = (cga_t *) priv;
cga->vram[addr & 0x3fff] = val;
if (cga->snow_enabled) {
int offset = ((timer_get_remaining_u64(&cga->timer) / CGACONST) * 2) & 0xfc;
cga->charbuffer[offset] = cga->vram[addr & 0x3fff];
cga->charbuffer[offset | 1] = cga->vram[addr & 0x3fff];
}
cga_waitstates(cga);
}
uint8_t
cga_read(uint32_t addr, void *priv)
{
cga_t *cga = (cga_t *) priv;
cga_waitstates(cga);
if (cga->snow_enabled) {
int offset = ((timer_get_remaining_u64(&cga->timer) / CGACONST) * 2) & 0xfc;
cga->charbuffer[offset] = cga->vram[addr & 0x3fff];
cga->charbuffer[offset | 1] = cga->vram[addr & 0x3fff];
}
return cga->vram[addr & 0x3fff];
}
void
cga_recalctimings(cga_t *cga)
{
double disptime;
double _dispontime;
double _dispofftime;
if (cga->cgamode & 1) {
disptime = (double) (cga->crtc[0] + 1);
_dispontime = (double) cga->crtc[1];
} else {
disptime = (double) ((cga->crtc[0] + 1) << 1);
_dispontime = (double) (cga->crtc[1] << 1);
}
_dispofftime = disptime - _dispontime;
_dispontime = _dispontime * CGACONST;
_dispofftime = _dispofftime * CGACONST;
cga->dispontime = (uint64_t) (_dispontime);
cga->dispofftime = (uint64_t) (_dispofftime);
}
static void
cga_render(cga_t *cga, int line)
{
uint16_t ca = (cga->crtc[15] | (cga->crtc[14] << 8)) & 0x3fff;
int drawcursor;
int x;
int c;
uint8_t chr;
uint8_t attr;
uint16_t dat;
int cols[4];
int col;
if ((cga->cgamode & 0x12) == 0x12) {
for (c = 0; c < 8; ++c) {
buffer32->line[line][c] = 0;
if (cga->cgamode & 1)
buffer32->line[line][c + (cga->crtc[1] << 3) + 8] = 0;
else
buffer32->line[line][c + (cga->crtc[1] << 4) + 8] = 0;
}
} else {
for (c = 0; c < 8; ++c) {
buffer32->line[line][c] = (cga->cgacol & 15) + 16;
if (cga->cgamode & 1)
buffer32->line[line][c + (cga->crtc[1] << 3) + 8] = (cga->cgacol & 15) + 16;
else
buffer32->line[line][c + (cga->crtc[1] << 4) + 8] = (cga->cgacol & 15) + 16;
}
}
if (cga->cgamode & 1) {
for (x = 0; x < cga->crtc[1]; x++) {
if (cga->cgamode & 8) {
chr = cga->charbuffer[x << 1];
attr = cga->charbuffer[(x << 1) + 1];
} else
chr = attr = 0;
drawcursor = ((cga->ma == ca) && cga->con && cga->cursoron);
cols[1] = (attr & 15) + 16;
if (cga->cgamode & 0x20) {
cols[0] = ((attr >> 4) & 7) + 16;
if ((cga->cgablink & 8) && (attr & 0x80) && !cga->drawcursor)
cols[1] = cols[0];
} else
cols[0] = (attr >> 4) + 16;
if (drawcursor) {
for (c = 0; c < 8; c++) {
buffer32->line[line][(x << 3) + c + 8]
= cols[(fontdat[chr + cga->fontbase][cga->sc & 7] & (1 << (c ^ 7))) ? 1 : 0] ^ 15;
}
} else {
for (c = 0; c < 8; c++) {
buffer32->line[line][(x << 3) + c + 8]
= cols[(fontdat[chr + cga->fontbase][cga->sc & 7] & (1 << (c ^ 7))) ? 1 : 0];
}
}
cga->ma++;
}
} else if (!(cga->cgamode & 2)) {
for (x = 0; x < cga->crtc[1]; x++) {
if (cga->cgamode & 8) {
chr = cga->vram[(cga->ma << 1) & 0x3fff];
attr = cga->vram[((cga->ma << 1) + 1) & 0x3fff];
} else
chr = attr = 0;
drawcursor = ((cga->ma == ca) && cga->con && cga->cursoron);
cols[1] = (attr & 15) + 16;
if (cga->cgamode & 0x20) {
cols[0] = ((attr >> 4) & 7) + 16;
if ((cga->cgablink & 8) && (attr & 0x80))
cols[1] = cols[0];
} else
cols[0] = (attr >> 4) + 16;
cga->ma++;
if (drawcursor) {
for (c = 0; c < 8; c++) {
buffer32->line[line][(x << 4) + (c << 1) + 8]
= buffer32->line[line][(x << 4) + (c << 1) + 9]
= cols[(fontdat[chr + cga->fontbase][cga->sc & 7] & (1 << (c ^ 7))) ? 1 : 0] ^ 15;
}
} else {
for (c = 0; c < 8; c++) {
buffer32->line[line][(x << 4) + (c << 1) + 8]
= buffer32->line[line][(x << 4) + (c << 1) + 9]
= cols[(fontdat[chr + cga->fontbase][cga->sc & 7] & (1 << (c ^ 7))) ? 1 : 0];
}
}
}
} else if (!(cga->cgamode & 16)) {
cols[0] = (cga->cgacol & 15) | 16;
col = (cga->cgacol & 16) ? 24 : 16;
if (cga->cgamode & 4) {
cols[1] = col | 3; /* Cyan */
cols[2] = col | 4; /* Red */
cols[3] = col | 7; /* White */
} else if (cga->cgacol & 32) {
cols[1] = col | 3; /* Cyan */
cols[2] = col | 5; /* Magenta */
cols[3] = col | 7; /* White */
} else {
cols[1] = col | 2; /* Green */
cols[2] = col | 4; /* Red */
cols[3] = col | 6; /* Yellow */
}
for (x = 0; x < cga->crtc[1]; x++) {
if (cga->cgamode & 8)
dat = (cga->vram[((cga->ma << 1) & 0x1fff) + ((cga->sc & 1) * 0x2000)] << 8) |
cga->vram[((cga->ma << 1) & 0x1fff) + ((cga->sc & 1) * 0x2000) + 1];
else
dat = 0;
cga->ma++;
for (c = 0; c < 8; c++) {
buffer32->line[line][(x << 4) + (c << 1) + 8]
= buffer32->line[line][(x << 4) + (c << 1) + 9]
= cols[dat >> 14];
dat <<= 2;
}
}
} else {
cols[0] = 0;
cols[1] = (cga->cgacol & 15) + 16;
for (x = 0; x < cga->crtc[1]; x++) {
if (cga->cgamode & 8)
dat = (cga->vram[((cga->ma << 1) & 0x1fff) + ((cga->sc & 1) * 0x2000)] << 8) |
cga->vram[((cga->ma << 1) & 0x1fff) + ((cga->sc & 1) * 0x2000) + 1];
else
dat = 0;
cga->ma++;
for (c = 0; c < 16; c++) {
buffer32->line[line][(x << 4) + c + 8] = cols[dat >> 15];
dat <<= 1;
}
}
}
}
static void
cga_render_blank(cga_t *cga, int line)
{
int col = ((cga->cgamode & 0x12) == 0x12) ? 0 : (cga->cgacol & 15) + 16;
if (cga->cgamode & 1)
hline(buffer32, 0, line, (cga->crtc[1] << 3) + 16, col);
else
hline(buffer32, 0, line, (cga->crtc[1] << 4) + 16, col);
}
static void
cga_render_process(cga_t *cga, int line)
{
int x;
uint8_t border;
if (cga->cgamode & 1)
x = (cga->crtc[1] << 3) + 16;
else
x = (cga->crtc[1] << 4) + 16;
if (cga->composite) {
border = ((cga->cgamode & 0x12) == 0x12) ? 0 : (cga->cgacol & 15);
Composite_Process(cga->cgamode, border, x >> 2, buffer32->line[line]);
} else
video_process_8(x, line);
}
static uint8_t
cga_interpolate_srgb(uint8_t co1, uint8_t co2, double fraction)
{
uint8_t ret = ((co2 - co1) * fraction + co1);
return ret;
}
static uint8_t
cga_interpolate_linear(uint8_t co1, uint8_t co2, double fraction)
{
double c1, c2;
double r1, r2;
uint8_t ret;
c1 = ((double) co1) / 255.0;
c1 = pow((co1 >= 0) ? c1 : -c1, 2.19921875);
if (co1 <= 0)
c1 = -c1;
c2 = ((double) co2) / 255.0;
c2 = pow((co2 >= 0) ? c2 : -c2, 2.19921875);
if (co2 <= 0)
c2 = -c2;
r1 = ((c2 - c1) * fraction + c1);
r2 = pow((r1 >= 0.0) ? r1 : -r1, 1.0 / 2.19921875);
if (r1 <= 0.0)
r2 = -r2;
ret = (uint8_t) (r2 * 255.0);
return ret;
}
static color_t
cga_interpolate_lookup(cga_t *cga, color_t color1, color_t color2, double fraction)
{
color_t ret;
uint8_t dt = cga->double_type - DOUBLE_INTERPOLATE_SRGB;
ret.a = 0x00;
ret.r = interp_lut[dt][color1.r][color2.r];
ret.g = interp_lut[dt][color1.g][color2.g];
ret.b = interp_lut[dt][color1.b][color2.b];
return ret;
}
static void
cga_interpolate(cga_t *cga, int x, int y, int w, int h)
{
double quotient = 0.5;
for (int i = y; i < (y + h); i++) {
if (i & 1) for (int j = x; j < (x + w); j++) {
int prev = i - 1;
int next = i + 1;
color_t prev_color, next_color;
color_t black;
color_t interim_1, interim_2;
color_t final;
if (i < 0)
continue;
black.color = 0x00000000;
if ((prev >= 0) && (prev < (y + h)))
prev_color.color = buffer32->line[prev][j];
else
prev_color.color = 0x00000000;
if ((next >= 0) && (next < (y + h)))
next_color.color = buffer32->line[next][j];
else
next_color.color = 0x00000000;
interim_1 = cga_interpolate_lookup(cga, prev_color, black, quotient);
interim_2 = cga_interpolate_lookup(cga, black, next_color, quotient);
final = cga_interpolate_lookup(cga, interim_1, interim_2, quotient);
buffer32->line[i][j] = final.color;
}
}
}
static void
cga_blit_memtoscreen(cga_t *cga, int x, int y, int w, int h)
{
if (cga->double_type > DOUBLE_SIMPLE)
cga_interpolate(cga, x, y, w, h);
video_blit_memtoscreen(x, y, w, h);
}
void
cga_poll(void *priv)
{
cga_t *cga = (cga_t *) priv;
int x;
int oldsc;
int oldvc;
int xs_temp;
int ys_temp;
int old_ma;
if (!cga->linepos) {
timer_advance_u64(&cga->timer, cga->dispofftime);
cga->cgastat |= 1;
cga->linepos = 1;
oldsc = cga->sc;
if ((cga->crtc[8] & 3) == 3)
cga->sc = ((cga->sc << 1) + cga->oddeven) & 7;
if (cga->cgadispon) {
if (cga->displine < cga->firstline) {
cga->firstline = cga->displine;
video_wait_for_buffer();
}
cga->lastline = cga->displine;
switch (cga->double_type) {
default:
cga_render(cga, cga->displine << 1);
cga_render_blank(cga, (cga->displine << 1) + 1);
break;
case DOUBLE_NONE:
cga_render(cga, cga->displine);
break;
case DOUBLE_SIMPLE:
old_ma = cga->ma;
cga_render(cga, cga->displine << 1);
cga->ma = old_ma;
cga_render(cga, (cga->displine << 1) + 1);
break;
}
} else {
switch (cga->double_type) {
default:
cga_render_blank(cga, cga->displine << 1);
break;
case DOUBLE_NONE:
cga_render_blank(cga, cga->displine);
break;
case DOUBLE_SIMPLE:
cga_render_blank(cga, cga->displine << 1);
cga_render_blank(cga, (cga->displine << 1) + 1);
break;
}
}
switch (cga->double_type) {
default:
cga_render_process(cga, cga->displine << 1);
cga_render_process(cga, (cga->displine << 1) + 1);
break;
case DOUBLE_NONE:
cga_render_process(cga, cga->displine);
break;
}
cga->sc = oldsc;
if (cga->vc == cga->crtc[7] && !cga->sc)
cga->cgastat |= 8;
cga->displine++;
if (cga->displine >= 360)
cga->displine = 0;
} else {
timer_advance_u64(&cga->timer, cga->dispontime);
cga->linepos = 0;
if (cga->vsynctime) {
cga->vsynctime--;
if (!cga->vsynctime)
cga->cgastat &= ~8;
}
if (cga->sc == (cga->crtc[11] & 31) || ((cga->crtc[8] & 3) == 3 &&
cga->sc == ((cga->crtc[11] & 31) >> 1))) {
cga->con = 0;
cga->coff = 1;
}
if ((cga->crtc[8] & 3) == 3 && cga->sc == (cga->crtc[9] >> 1))
cga->maback = cga->ma;
if (cga->vadj) {
cga->sc++;
cga->sc &= 31;
cga->ma = cga->maback;
cga->vadj--;
if (!cga->vadj) {
cga->cgadispon = 1;
cga->ma = cga->maback = (cga->crtc[13] | (cga->crtc[12] << 8)) & 0x3fff;
cga->sc = 0;
}
} else if (cga->sc == cga->crtc[9]) {
cga->maback = cga->ma;
cga->sc = 0;
oldvc = cga->vc;
cga->vc++;
cga->vc &= 127;
if (cga->vc == cga->crtc[6])
cga->cgadispon = 0;
if (oldvc == cga->crtc[4]) {
cga->vc = 0;
cga->vadj = cga->crtc[5];
if (!cga->vadj) {
cga->cgadispon = 1;
cga->ma = cga->maback = (cga->crtc[13] | (cga->crtc[12] << 8)) & 0x3fff;
}
switch (cga->crtc[10] & 0x60) {
case 0x20:
cga->cursoron = 0;
break;
case 0x60:
cga->cursoron = cga->cgablink & 0x10;
break;
default:
cga->cursoron = cga->cgablink & 0x08;
break;
}
}
if (cga->vc == cga->crtc[7]) {
cga->cgadispon = 0;
cga->displine = 0;
cga->vsynctime = 16;
if (cga->crtc[7]) {
if (cga->cgamode & 1)
x = (cga->crtc[1] << 3) + 16;
else
x = (cga->crtc[1] << 4) + 16;
cga->lastline++;
xs_temp = x;
ys_temp = cga->lastline - cga->firstline;
if (cga->double_type > DOUBLE_NONE)
ys_temp <<= 1;
if ((xs_temp > 0) && (ys_temp > 0)) {
if (xs_temp < 64)
xs_temp = 656;
if (ys_temp < 32)
ys_temp = 200;
if (!enable_overscan)
xs_temp -= 16;
if ((cga->cgamode & 8) && ((xs_temp != xsize) ||
(ys_temp != ysize) || video_force_resize_get())) {
xsize = xs_temp;
ysize = ys_temp;
if (cga->double_type > DOUBLE_NONE)
set_screen_size(xsize, ysize + (enable_overscan ? 16 : 0));
else
set_screen_size(xsize, ysize + (enable_overscan ? 8 : 0));
if (video_force_resize_get())
video_force_resize_set(0);
}
if (cga->double_type > DOUBLE_NONE) {
if (enable_overscan)
cga_blit_memtoscreen(cga, 0, (cga->firstline - 4) << 1,
xsize, ((cga->lastline - cga->firstline) << 1) + 16);
else
cga_blit_memtoscreen(cga, 8, cga->firstline << 1,
xsize, (cga->lastline - cga->firstline) << 1);
} else {
if (enable_overscan)
video_blit_memtoscreen(0, cga->firstline - 4,
xsize, (cga->lastline - cga->firstline) + 8);
else
video_blit_memtoscreen(8, cga->firstline,
xsize, cga->lastline - cga->firstline);
}
}
frames++;
video_res_x = xsize;
video_res_y = ysize;
if (cga->cgamode & 1) {
video_res_x /= 8;
video_res_y /= cga->crtc[9] + 1;
video_bpp = 0;
} else if (!(cga->cgamode & 2)) {
video_res_x /= 16;
video_res_y /= cga->crtc[9] + 1;
video_bpp = 0;
} else if (!(cga->cgamode & 16)) {
video_res_x /= 2;
video_bpp = 2;
} else
video_bpp = 1;
}
cga->firstline = 1000;
cga->lastline = 0;
cga->cgablink++;
cga->oddeven ^= 1;
}
} else {
cga->sc++;
cga->sc &= 31;
cga->ma = cga->maback;
}
if (cga->cgadispon)
cga->cgastat &= ~1;
if (cga->sc == (cga->crtc[10] & 31) || ((cga->crtc[8] & 3) == 3 &&
cga->sc == ((cga->crtc[10] & 31) >> 1)))
cga->con = 1;
if (cga->cgadispon && (cga->cgamode & 1)) {
for (x = 0; x < (cga->crtc[1] << 1); x++)
cga->charbuffer[x] = cga->vram[((cga->ma << 1) + x) & 0x3fff];
}
}
}
void
cga_init(cga_t *cga)
{
timer_add(&cga->timer, cga_poll, cga, 1);
cga->composite = 0;
}
void *
cga_standalone_init(UNUSED(const device_t *info))
{
int display_type;
cga_t *cga = malloc(sizeof(cga_t));
memset(cga, 0, sizeof(cga_t));
video_inform(VIDEO_FLAG_TYPE_CGA, &timing_cga);
display_type = device_get_config_int("display_type");
cga->composite = (display_type != CGA_RGB);
cga->revision = device_get_config_int("composite_type");
cga->snow_enabled = device_get_config_int("snow_enabled");
cga->vram = malloc(0x4000);
cga_comp_init(cga->revision);
timer_add(&cga->timer, cga_poll, cga, 1);
mem_mapping_add(&cga->mapping, 0xb8000, 0x08000, cga_read, NULL, NULL, cga_write, NULL, NULL, NULL /*cga->vram*/, MEM_MAPPING_EXTERNAL, cga);
io_sethandler(0x03d0, 0x0010, cga_in, NULL, NULL, cga_out, NULL, NULL, cga);
overscan_x = overscan_y = 16;
cga->rgb_type = device_get_config_int("rgb_type");
cga_palette = (cga->rgb_type << 1);
cgapal_rebuild();
update_cga16_color(cga->cgamode);
cga->double_type = device_get_config_int("double_type");
for (uint16_t i = 0; i < 256; i++) {
for (uint16_t j = 0; j < 256; j++) {
interp_lut[0][i][j] = cga_interpolate_srgb(i, j, 0.5);
interp_lut[1][i][j] = cga_interpolate_linear(i, j, 0.5);
}
}
return cga;
}
void *
cga_pravetz_init(const device_t *info)
{
cga_t *cga = cga_standalone_init(info);
loadfont("roms/video/cga/PRAVETZ-VDC2.BIN", 10);
io_removehandler(0x03dd, 0x0001, cga_in, NULL, NULL, cga_out, NULL, NULL, cga);
io_sethandler(0x03dd, 0x0001, cga_pravetz_in, NULL, NULL, cga_pravetz_out, NULL, NULL, cga);
cga->fontbase = 0x0300;
return cga;
}
void
cga_close(void *priv)
{
cga_t *cga = (cga_t *) priv;
free(cga->vram);
free(cga);
}
void
cga_speed_changed(void *priv)
{
cga_t *cga = (cga_t *) priv;
cga_recalctimings(cga);
}
// clang-format off
const device_config_t cga_config[] = {
{
.name = "display_type",
.description = "Display type",
.type = CONFIG_SELECTION,
.default_int = CGA_RGB,
.selection = {
{
.description = "RGB",
.value = CGA_RGB
},
{
.description = "Composite",
.value = CGA_COMPOSITE
},
{
.description = ""
}
}
},
{
.name = "composite_type",
.description = "Composite type",
.type = CONFIG_SELECTION,
.default_int = COMPOSITE_OLD,
.selection = {
{
.description = "Old",
.value = COMPOSITE_OLD
},
{
.description = "New",
.value = COMPOSITE_NEW
},
{
.description = ""
}
}
},
{
.name = "rgb_type",
.description = "RGB type",
.type = CONFIG_SELECTION,
.default_int = 5,
.selection = {
{
.description = "Color (generic)",
.value = 0
},
{
.description = "Green Monochrome",
.value = 1
},
{
.description = "Amber Monochrome",
.value = 2
},
{
.description = "Gray Monochrome",
.value = 3
},
{
.description = "Color (no brown)",
.value = 4
},
{
.description = "Color (IBM 5153)",
.value = 5
},
{
.description = ""
}
}
},
{
.name = "double_type",
.description = "Line doubling type",
.type = CONFIG_SELECTION,
.default_int = DOUBLE_NONE,
.selection = {
{
.description = "None",
.value = DOUBLE_NONE
},
{
.description = "Simple doubling",
.value = DOUBLE_SIMPLE
},
{
.description = "sRGB interpolation",
.value = DOUBLE_INTERPOLATE_SRGB
},
{
.description = "Linear interpolation",
.value = DOUBLE_INTERPOLATE_LINEAR
},
{
.description = ""
}
}
},
{
.name = "snow_enabled",
.description = "Snow emulation",
.type = CONFIG_BINARY,
.default_int = 1
},
{
.type = CONFIG_END
}
};
// clang-format on
const device_t cga_device = {
.name = "IBM CGA",
.internal_name = "cga",
.flags = DEVICE_ISA,
.local = 0,
.init = cga_standalone_init,
.close = cga_close,
.reset = NULL,
{ .available = NULL },
.speed_changed = cga_speed_changed,
.force_redraw = NULL,
.config = cga_config
};
const device_t cga_pravetz_device = {
.name = "Pravetz VDC-2",
.internal_name = "cga_pravetz",
.flags = DEVICE_ISA,
.local = 0,
.init = cga_pravetz_init,
.close = cga_close,
.reset = NULL,
{ .available = NULL },
.speed_changed = cga_speed_changed,
.force_redraw = NULL,
.config = cga_config
};
``` | /content/code_sandbox/src/video/vid_cga.c | c | 2016-06-25T22:29:10 | 2024-08-16T19:09:21 | 86Box | 86Box/86Box | 2,616 | 8,721 |
```c
/*
* 86Box A hypervisor and IBM PC system emulator that specializes in
* running old operating systems and software designed for IBM
* PC systems and compatibles from 1981 through fairly recent
* system designs based on the PCI bus.
*
* This file is part of the 86Box distribution.
*
* Emulation of a AT&T 2xc498 RAMDAC.
*
*
*
* Authors: Miran Grca, <mgrca8@gmail.com>
*
*/
#include <stdio.h>
#include <stdint.h>
#include <stdlib.h>
#include <string.h>
#include <wchar.h>
#include <86box/86box.h>
#include <86box/device.h>
#include <86box/mem.h>
#include <86box/timer.h>
#include <86box/video.h>
#include <86box/vid_svga.h>
typedef struct att498_ramdac_t {
int type;
int state;
int loop;
uint8_t ctrl;
} att498_ramdac_t;
static void
att498_ramdac_control(uint8_t val, void *priv, svga_t *svga)
{
att498_ramdac_t *ramdac = (att498_ramdac_t *) priv;
ramdac->ctrl = val;
if (val == 0xff)
return;
switch ((ramdac->ctrl >> 4) & 0x0f) {
default:
svga->bpp = 8;
break;
case 1:
if (ramdac->ctrl & 4)
svga->bpp = 15;
else
svga->bpp = 8;
break;
case 3:
case 6:
svga->bpp = 16;
break;
case 5:
case 7:
svga->bpp = 32;
break;
case 0x0e:
svga->bpp = 24;
break;
}
svga_set_ramdac_type(svga, (ramdac->ctrl & 2) ? RAMDAC_8BIT : RAMDAC_6BIT);
svga_recalctimings(svga);
}
void
att498_ramdac_out(uint16_t addr, int rs2, uint8_t val, void *priv, svga_t *svga)
{
att498_ramdac_t *ramdac = (att498_ramdac_t *) priv;
uint8_t rs = (addr & 0x03);
rs |= ((!!rs2) << 2);
switch (rs) {
case 0x00:
case 0x01:
case 0x03:
case 0x04:
case 0x05:
case 0x07:
svga_out(addr, val, svga);
ramdac->state = 0;
break;
case 0x02:
switch (ramdac->state) {
case 4:
att498_ramdac_control(val, ramdac, svga);
break;
default:
svga_out(addr, val, svga);
break;
}
break;
case 0x06:
att498_ramdac_control(val, ramdac, svga);
break;
default:
break;
}
}
uint8_t
att498_ramdac_in(uint16_t addr, int rs2, void *priv, svga_t *svga)
{
att498_ramdac_t *ramdac = (att498_ramdac_t *) priv;
uint8_t temp = 0xff;
uint8_t rs = (addr & 0x03);
rs |= ((!!rs2) << 2);
switch (rs) {
case 0x00:
case 0x01:
case 0x03:
case 0x04:
case 0x05:
case 0x07:
temp = svga_in(addr, svga);
ramdac->state = 0;
break;
case 0x02:
switch (ramdac->state) {
case 4:
temp = ramdac->ctrl;
ramdac->state++;
break;
case 5:
temp = 0x84;
ramdac->state++;
break;
case 6:
temp = ramdac->ctrl;
ramdac->state = 0;
break;
default:
temp = svga_in(addr, svga);
ramdac->state++;
break;
}
break;
case 0x06:
temp = ramdac->ctrl;
ramdac->state = 0;
break;
default:
break;
}
return temp;
}
static void *
att498_ramdac_init(const device_t *info)
{
att498_ramdac_t *ramdac = (att498_ramdac_t *) malloc(sizeof(att498_ramdac_t));
memset(ramdac, 0, sizeof(att498_ramdac_t));
ramdac->type = info->local;
return ramdac;
}
static void
att498_ramdac_close(void *priv)
{
att498_ramdac_t *ramdac = (att498_ramdac_t *) priv;
if (ramdac)
free(ramdac);
}
const device_t att498_ramdac_device = {
.name = "AT&T 22c498 RAMDAC",
.internal_name = "att498_ramdac",
.flags = 0,
.local = 0,
.init = att498_ramdac_init,
.close = att498_ramdac_close,
.reset = NULL,
{ .available = NULL },
.speed_changed = NULL,
.force_redraw = NULL,
.config = NULL
};
``` | /content/code_sandbox/src/video/vid_att2xc498_ramdac.c | c | 2016-06-25T22:29:10 | 2024-08-16T19:09:21 | 86Box | 86Box/86Box | 2,616 | 1,254 |
```c
/*
* 86Box A hypervisor and IBM PC system emulator that specializes in
* running old operating systems and software designed for IBM
* PC systems and compatibles from 1981 through fairly recent
* system designs based on the PCI bus.
*
* This file is part of the 86Box distribution.
*
* ATI 68860 RAMDAC emulation (for Mach64)
*
* ATI 68860/68880 Truecolor DACs:
* REG08 (R/W):
* bit 0-? Always 2 ??
*
* REG0A (R/W):
* bit 0-? Always 1Dh ??
*
* REG0B (R/W): (GMR ?)
* bit 0-7 Mode. 82h: 4bpp, 83h: 8bpp,
* A0h: 15bpp, A1h: 16bpp, C0h: 24bpp,
* E3h: 32bpp (80h for VGA modes ?)
*
* REG0C (R/W): Device Setup Register A
* bit 0 Controls 6/8bit DAC. 0: 8bit DAC/LUT, 1: 6bit DAC/LUT
* 2-3 Depends on Video memory (= VRAM width ?) .
* 1: Less than 1Mb, 2: 1Mb, 3: > 1Mb
* 5-6 Always set ?
* 7 If set can remove "snow" in some cases
* (A860_Delay_L ?) ??
*
*
*
* Authors: Sarah Walker, <path_to_url
* Miran Grca, <mgrca8@gmail.com>
*
*/
#include <stdio.h>
#include <stdint.h>
#include <stdlib.h>
#include <string.h>
#include <wchar.h>
#include <86box/86box.h>
#include <86box/device.h>
#include <86box/mem.h>
#include <86box/rom.h>
#include <86box/timer.h>
#include <86box/video.h>
#include <86box/vid_8514a.h>
#include <86box/vid_svga.h>
#include <86box/vid_svga_render.h>
#include <86box/plat_unused.h>
typedef struct ati68860_ramdac_t {
uint8_t regs[16];
void (*render)(struct svga_t *svga);
int dac_addr;
int dac_pos;
int dac_r;
int dac_g;
PALETTE pal;
uint32_t pallook[2];
int ramdac_type;
} ati68860_ramdac_t;
void
ati68860_ramdac_out(uint16_t addr, uint8_t val, void *priv, svga_t *svga)
{
ati68860_ramdac_t *ramdac = (ati68860_ramdac_t *) priv;
const ibm8514_t *dev = (ibm8514_t *) svga->dev8514;
switch (addr) {
case 0:
svga_out((dev && (dev->on[0] || dev->on[1])) ? 0x2ec : 0x3c8, val, svga);
break;
case 1:
svga_out((dev && (dev->on[0] || dev->on[1])) ? 0x2ed : 0x3c9, val, svga);
break;
case 2:
svga_out((dev && (dev->on[0] || dev->on[1])) ? 0x2ea : 0x3c6, val, svga);
break;
case 3:
svga_out((dev && (dev->on[0] || dev->on[1])) ? 0x2eb : 0x3c7, val, svga);
break;
default:
ramdac->regs[addr & 0xf] = val;
switch (addr & 0xf) {
case 0x4:
ramdac->dac_addr = val;
ramdac->dac_pos = 0;
break;
case 0x5:
switch (ramdac->dac_pos) {
case 0:
ramdac->dac_r = val;
ramdac->dac_pos++;
break;
case 1:
ramdac->dac_g = val;
ramdac->dac_pos++;
break;
case 2:
if (ramdac->dac_addr > 1)
break;
ramdac->pal[ramdac->dac_addr].r = ramdac->dac_r;
ramdac->pal[ramdac->dac_addr].g = ramdac->dac_g;
ramdac->pal[ramdac->dac_addr].b = val;
if (ramdac->ramdac_type == RAMDAC_8BIT)
ramdac->pallook[ramdac->dac_addr] = makecol32(ramdac->pal[ramdac->dac_addr].r,
ramdac->pal[ramdac->dac_addr].g,
ramdac->pal[ramdac->dac_addr].b);
else
ramdac->pallook[ramdac->dac_addr] = makecol32(video_6to8[ramdac->pal[ramdac->dac_addr].r & 0x3f],
video_6to8[ramdac->pal[ramdac->dac_addr].g & 0x3f],
video_6to8[ramdac->pal[ramdac->dac_addr].b & 0x3f]);
ramdac->dac_pos = 0;
ramdac->dac_addr = (ramdac->dac_addr + 1) & 255;
break;
default:
break;
}
break;
case 0xb:
switch (val) {
case 0x82:
ramdac->render = svga_render_4bpp_highres;
break;
case 0x83:
/*FIXME*/
ramdac->render = svga_render_8bpp_clone_highres;
break;
case 0xa0:
case 0xb0:
ramdac->render = svga_render_15bpp_highres;
break;
case 0xa1:
case 0xb1:
ramdac->render = svga_render_16bpp_highres;
break;
case 0xc0:
case 0xd0:
ramdac->render = svga_render_24bpp_highres;
break;
case 0xe2:
case 0xf7:
ramdac->render = svga_render_32bpp_highres;
break;
case 0xe3:
ramdac->render = svga_render_ABGR8888_highres;
break;
case 0xf2:
ramdac->render = svga_render_RGBA8888_highres;
break;
default:
/*FIXME*/
ramdac->render = svga_render_8bpp_clone_highres;
break;
}
break;
case 0xc:
svga_set_ramdac_type(svga, (val & 1) ? RAMDAC_6BIT : RAMDAC_8BIT);
break;
default:
break;
}
break;
}
}
uint8_t
ati68860_ramdac_in(uint16_t addr, void *priv, svga_t *svga)
{
const ati68860_ramdac_t *ramdac = (ati68860_ramdac_t *) priv;
const ibm8514_t *dev = (ibm8514_t *) svga->dev8514;
uint8_t temp = 0;
switch (addr) {
case 0:
temp = svga_in((dev && (dev->on[0] || dev->on[1])) ? 0x2ec : 0x3c8, svga);
break;
case 1:
temp = svga_in((dev && (dev->on[0] || dev->on[1])) ? 0x2ed : 0x3c9, svga);
break;
case 2:
temp = svga_in((dev && (dev->on[0] || dev->on[1])) ? 0x2ea : 0x3c6, svga);
break;
case 3:
temp = svga_in((dev && (dev->on[0] || dev->on[1])) ? 0x2eb : 0x3c7, svga);
break;
case 4:
case 8:
temp = 2;
break;
case 6:
case 0xa:
temp = 0x1d;
break;
case 0xf:
temp = 0xd0;
break;
default:
temp = ramdac->regs[addr & 0xf];
break;
}
return temp;
}
void
ati68860_set_ramdac_type(void *priv, int type)
{
ati68860_ramdac_t *ramdac = (ati68860_ramdac_t *) priv;
if (ramdac->ramdac_type != type) {
ramdac->ramdac_type = type;
for (uint8_t c = 0; c < 2; c++) {
if (ramdac->ramdac_type == RAMDAC_8BIT)
ramdac->pallook[c] = makecol32(ramdac->pal[c].r, ramdac->pal[c].g,
ramdac->pal[c].b);
else
ramdac->pallook[c] = makecol32(video_6to8[ramdac->pal[c].r & 0x3f], video_6to8[ramdac->pal[c].g & 0x3f],
video_6to8[ramdac->pal[c].b & 0x3f]);
}
}
}
static void *
ati68860_ramdac_init(UNUSED(const device_t *info))
{
ati68860_ramdac_t *ramdac = (ati68860_ramdac_t *) malloc(sizeof(ati68860_ramdac_t));
memset(ramdac, 0, sizeof(ati68860_ramdac_t));
/*FIXME*/
ramdac->render = svga_render_8bpp_clone_highres;
return ramdac;
}
void
ati68860_ramdac_set_render(void *priv, svga_t *svga)
{
ati68860_ramdac_t *ramdac = (ati68860_ramdac_t *) priv;
svga->render = ramdac->render;
}
void
ati68860_ramdac_set_pallook(void *priv, int i, uint32_t col)
{
ati68860_ramdac_t *ramdac = (ati68860_ramdac_t *) priv;
ramdac->pallook[i] = col;
}
void
ati68860_hwcursor_draw(svga_t *svga, int displine)
{
const ati68860_ramdac_t *ramdac = (ati68860_ramdac_t *) svga->ramdac;
int offset;
uint8_t dat;
uint32_t col0 = ramdac->pallook[0];
uint32_t col1 = ramdac->pallook[1];
offset = svga->dac_hwcursor_latch.xoff;
for (uint32_t x = 0; x < 64 - svga->dac_hwcursor_latch.xoff; x += 4) {
dat = svga->vram[svga->dac_hwcursor_latch.addr + (offset >> 2)];
if (!(dat & 2))
buffer32->line[displine][svga->dac_hwcursor_latch.x + x + svga->x_add] = (dat & 1) ? col1 : col0;
else if ((dat & 3) == 3)
buffer32->line[displine][svga->dac_hwcursor_latch.x + x + svga->x_add] ^= 0xFFFFFF;
dat >>= 2;
if (!(dat & 2))
buffer32->line[displine][svga->dac_hwcursor_latch.x + x + svga->x_add + 1] = (dat & 1) ? col1 : col0;
else if ((dat & 3) == 3)
buffer32->line[displine][svga->dac_hwcursor_latch.x + x + svga->x_add + 1] ^= 0xFFFFFF;
dat >>= 2;
if (!(dat & 2))
buffer32->line[displine][svga->dac_hwcursor_latch.x + x + svga->x_add + 2] = (dat & 1) ? col1 : col0;
else if ((dat & 3) == 3)
buffer32->line[displine][svga->dac_hwcursor_latch.x + x + svga->x_add + 2] ^= 0xFFFFFF;
dat >>= 2;
if (!(dat & 2))
buffer32->line[displine][svga->dac_hwcursor_latch.x + x + svga->x_add + 3] = (dat & 1) ? col1 : col0;
else if ((dat & 3) == 3)
buffer32->line[displine][svga->dac_hwcursor_latch.x + x + svga->x_add + 3] ^= 0xFFFFFF;
dat >>= 2;
offset += 4;
}
svga->dac_hwcursor_latch.addr += 16;
}
static void
ati68860_ramdac_close(void *priv)
{
ati68860_ramdac_t *ramdac = (ati68860_ramdac_t *) priv;
if (ramdac)
free(ramdac);
}
const device_t ati68860_ramdac_device = {
.name = "ATI-68860 RAMDAC",
.internal_name = "ati68860_ramdac",
.flags = 0,
.local = 0,
.init = ati68860_ramdac_init,
.close = ati68860_ramdac_close,
.reset = NULL,
{ .available = NULL },
.speed_changed = NULL,
.force_redraw = NULL,
.config = NULL
};
``` | /content/code_sandbox/src/video/vid_ati68860_ramdac.c | c | 2016-06-25T22:29:10 | 2024-08-16T19:09:21 | 86Box | 86Box/86Box | 2,616 | 3,177 |
```c
/*
* 86Box A hypervisor and IBM PC system emulator that specializes in
* running old operating systems and software designed for IBM
* PC systems and compatibles from 1981 through fairly recent
* system designs based on the PCI bus.
*
* This file is part of the 86Box distribution.
*
* IBM VGA emulation.
*
*
*
* Authors: Sarah Walker, <path_to_url
* Miran Grca, <mgrca8@gmail.com>
*
*/
#include <stdio.h>
#include <stdint.h>
#include <string.h>
#include <stdlib.h>
#include <wchar.h>
#include <86box/86box.h>
#include <86box/io.h>
#include <86box/mem.h>
#include <86box/rom.h>
#include <86box/device.h>
#include <86box/timer.h>
#include <86box/video.h>
#include <86box/vid_svga.h>
#include <86box/vid_vga.h>
static video_timings_t timing_ps1_svga_isa = { .type = VIDEO_ISA, .write_b = 6, .write_w = 8, .write_l = 16, .read_b = 6, .read_w = 8, .read_l = 16 };
static video_timings_t timing_ps1_svga_mca = { .type = VIDEO_MCA, .write_b = 6, .write_w = 8, .write_l = 16, .read_b = 6, .read_w = 8, .read_l = 16 };
void
vga_out(uint16_t addr, uint8_t val, void *priv)
{
vga_t *vga = (vga_t *) priv;
svga_t *svga = &vga->svga;
uint8_t old;
if (((addr & 0xfff0) == 0x3d0 || (addr & 0xfff0) == 0x3b0) && !(svga->miscout & 1))
addr ^= 0x60;
switch (addr) {
case 0x3D4:
svga->crtcreg = val & 0x3f;
return;
case 0x3D5:
if (svga->crtcreg & 0x20)
return;
if ((svga->crtcreg < 7) && (svga->crtc[0x11] & 0x80))
return;
if ((svga->crtcreg == 7) && (svga->crtc[0x11] & 0x80))
val = (svga->crtc[7] & ~0x10) | (val & 0x10);
old = svga->crtc[svga->crtcreg];
svga->crtc[svga->crtcreg] = val;
if (old != val) {
if (svga->crtcreg < 0xe || svga->crtcreg > 0x10) {
if ((svga->crtcreg == 0xc) || (svga->crtcreg == 0xd)) {
svga->fullchange = 3;
svga->ma_latch = ((svga->crtc[0xc] << 8) | svga->crtc[0xd]) + ((svga->crtc[8] & 0x60) >> 5);
} else {
svga->fullchange = changeframecount;
svga_recalctimings(svga);
}
}
}
break;
default:
break;
}
svga_out(addr, val, svga);
}
uint8_t
vga_in(uint16_t addr, void *priv)
{
vga_t *vga = (vga_t *) priv;
svga_t *svga = &vga->svga;
uint8_t temp;
if (((addr & 0xfff0) == 0x3d0 || (addr & 0xfff0) == 0x3b0) && !(svga->miscout & 1))
addr ^= 0x60;
switch (addr) {
case 0x3D4:
temp = svga->crtcreg;
break;
case 0x3D5:
if (svga->crtcreg & 0x20)
temp = 0xff;
else
temp = svga->crtc[svga->crtcreg];
break;
default:
temp = svga_in(addr, svga);
break;
}
return temp;
}
static void *
vga_init(const device_t *info)
{
vga_t *vga = malloc(sizeof(vga_t));
memset(vga, 0, sizeof(vga_t));
rom_init(&vga->bios_rom, "roms/video/vga/ibm_vga.bin", 0xc0000, 0x8000, 0x7fff, 0x2000, MEM_MAPPING_EXTERNAL);
video_inform(VIDEO_FLAG_TYPE_SPECIAL, &timing_vga);
svga_init(info, &vga->svga, vga, 1 << 18, /*256kb*/
NULL,
vga_in, vga_out,
NULL,
NULL);
io_sethandler(0x03c0, 0x0020, vga_in, NULL, NULL, vga_out, NULL, NULL, vga);
vga->svga.bpp = 8;
vga->svga.miscout = 1;
return vga;
}
/*PS/1 uses a standard VGA controller, but with no option ROM*/
void *
ps1vga_init(const device_t *info)
{
vga_t *vga = malloc(sizeof(vga_t));
memset(vga, 0, sizeof(vga_t));
if (info->flags & DEVICE_MCA)
video_inform(VIDEO_FLAG_TYPE_SPECIAL, &timing_ps1_svga_mca);
else
video_inform(VIDEO_FLAG_TYPE_SPECIAL, &timing_ps1_svga_isa);
svga_init(info, &vga->svga, vga, 1 << 18, /*256kb*/
NULL,
vga_in, vga_out,
NULL,
NULL);
io_sethandler(0x03c0, 0x0020, vga_in, NULL, NULL, vga_out, NULL, NULL, vga);
vga->svga.bpp = 8;
vga->svga.miscout = 1;
return vga;
}
static int
vga_available(void)
{
return rom_present("roms/video/vga/ibm_vga.bin");
}
void
vga_close(void *priv)
{
vga_t *vga = (vga_t *) priv;
svga_close(&vga->svga);
free(vga);
}
void
vga_speed_changed(void *priv)
{
vga_t *vga = (vga_t *) priv;
svga_recalctimings(&vga->svga);
}
void
vga_force_redraw(void *priv)
{
vga_t *vga = (vga_t *) priv;
vga->svga.fullchange = changeframecount;
}
const device_t vga_device = {
.name = "IBM VGA",
.internal_name = "vga",
.flags = DEVICE_ISA,
.local = 0,
.init = vga_init,
.close = vga_close,
.reset = NULL,
{ .available = vga_available },
.speed_changed = vga_speed_changed,
.force_redraw = vga_force_redraw,
.config = NULL
};
const device_t ps1vga_device = {
.name = "IBM PS/1 VGA",
.internal_name = "ps1vga",
.flags = DEVICE_ISA,
.local = 0,
.init = ps1vga_init,
.close = vga_close,
.reset = NULL,
{ .available = vga_available },
.speed_changed = vga_speed_changed,
.force_redraw = vga_force_redraw,
.config = NULL
};
const device_t ps1vga_mca_device = {
.name = "IBM PS/1 VGA",
.internal_name = "ps1vga_mca",
.flags = DEVICE_MCA,
.local = 0,
.init = ps1vga_init,
.close = vga_close,
.reset = NULL,
{ .available = vga_available },
.speed_changed = vga_speed_changed,
.force_redraw = vga_force_redraw,
.config = NULL
};
``` | /content/code_sandbox/src/video/vid_vga.c | c | 2016-06-25T22:29:10 | 2024-08-16T19:09:21 | 86Box | 86Box/86Box | 2,616 | 1,976 |
```c
/*
* 86Box A hypervisor and IBM PC system emulator that specializes in
* running old operating systems and software designed for IBM
* PC systems and compatibles from 1981 through fairly recent
* system designs based on the PCI bus.
*
* This file is part of the 86Box distribution.
*
* MDSI Genius VHR emulation.
*
*
*
* Authors: John Elliott, <jce@seasip.info>
* Miran Grca, <mgrca8@gmail.com>
*
*/
#include <stdio.h>
#include <stdint.h>
#include <string.h>
#include <stdlib.h>
#include <wchar.h>
#include <86box/86box.h>
#include "cpu.h"
#include <86box/io.h>
#include <86box/timer.h>
#include <86box/pit.h>
#include <86box/mem.h>
#include <86box/rom.h>
#include <86box/device.h>
#include <86box/plat.h>
#include <86box/video.h>
#define BIOS_ROM_PATH "roms/video/genius/8x12.bin"
#define GENIUS_XSIZE 728
#define GENIUS_YSIZE 1008
extern uint8_t fontdat8x12[256][16];
static video_timings_t timing_genius = { .type = VIDEO_ISA, .write_b = 8, .write_w = 16, .write_l = 32, .read_b = 8, .read_w = 16, .read_l = 32 };
/* I'm at something of a disadvantage writing this emulation: I don't have an
* MDSI Genius card, nor do I have the BIOS extension (VHRBIOS.SYS) that came
* with it. What I do have are the GEM and Windows 1.04 drivers, plus a driver
* for a later MCA version of the card. The latter can be found at
* <path_to_url and is necessary if you
* want the Windows driver to work.
*
* This emulation appears to work correctly with:
* The MCA drivers GMC_ANSI.SYS and INS_ANSI.SYS
* The GEM driver SDGEN9.VGA
* The Windows 1.04 driver GENIUS.DRV
*
* As far as I can see, the card uses a fixed resolution of 728x1008 pixels.
* It has the following modes of operation:
*
* > MDA-compatible: 80x25 text, each character 9x15 pixels.
* > CGA-compatible: 640x200 mono graphics
* > Dual: MDA text in the top half, CGA graphics in the bottom
* > Native text: 80x66 text, each character 9x15 pixels.
* > Native graphics: 728x1008 mono graphics.
*
* Under the covers, this seems to translate to:
* > Text framebuffer. At B000:0000, 16k. Displayed if enable bit is set
* in the MDA control register.
* > Graphics framebuffer. In native modes goes from A000:0000 to A000:FFFF
* and B800:0000 to B800:FFFF. In CGA-compatible
* mode only the section at B800:0000 to B800:7FFF
* is visible. Displayed if enable bit is set in the
* CGA control register.
*
* Two card-specific registers control text and graphics display:
*
* 03B0: Control register.
* Bit 0: Map all graphics framebuffer into memory.
* Bit 2: Unknown. Set by GMC /M; cleared by mode set or GMC /T.
* Bit 4: Set for CGA-compatible graphics, clear for native graphics.
* Bit 5: Set for black on white, clear for white on black.
*
* 03B1: Character height register.
* Bits 0-1: Character cell height (0 => 15, 1 => 14, 2 => 13, 3 => 12)
* Bit 4: Set to double character cell height (scanlines are doubled)
* Bit 7: Unknown, seems to be set for all modes except 80x66
*
* Not having the card also means I don't have its font. According to the
* card brochure the font is an 8x12 bitmap in a 9x15 character cell. I
* therefore generated it by taking the MDA font, increasing graphics to
* 16 pixels in height and reducing the height of characters so they fit
* in an 8x12 cell if necessary.
*/
typedef struct genius_t {
mem_mapping_t mapping;
uint8_t mda_crtc[32]; /* The 'CRTC' as the host PC sees it */
int mda_crtcreg; /* Current CRTC register */
uint8_t cga_crtc[32]; /* The 'CRTC' as the host PC sees it */
int cga_crtcreg; /* Current CRTC register */
uint8_t genius_control; /* Native control register
* I think bit 0 enables the full
* framebuffer.
*/
uint8_t genius_charh; /* Native character height register:
* 00h => chars are 15 pixels high
* 81h => chars are 14 pixels high
* 83h => chars are 12 pixels high
* 90h => chars are 30 pixels high [15 x 2]
* 93h => chars are 24 pixels high [12 x 2]
*/
uint8_t genius_mode; /* Current mode (see list at top of file) */
uint8_t cga_ctrl; /* Emulated CGA control register */
uint8_t mda_ctrl; /* Emulated MDA control register */
uint8_t cga_colour; /* Emulated CGA colour register (ignored) */
uint8_t mda_stat; /* MDA status (IN 0x3BA) */
uint8_t cga_stat; /* CGA status (IN 0x3DA) */
int font; /* Current font, 0 or 1 */
int enabled; /* Display enabled, 0 or 1 */
int detach; /* Detach cursor, 0 or 1 */
uint64_t dispontime, dispofftime;
pc_timer_t timer;
int linepos, displine;
int vc;
int dispon, blink;
int vsynctime;
uint8_t *vram;
} genius_t;
static uint8_t genius_pal[4];
/* Mapping of attributes to colours, in MDA emulation mode */
static uint8_t mdaattr[256][2][2];
void genius_recalctimings(genius_t *genius);
void genius_write(uint32_t addr, uint8_t val, void *priv);
uint8_t genius_read(uint32_t addr, void *priv);
void
genius_out(uint16_t addr, uint8_t val, void *priv)
{
genius_t *genius = (genius_t *) priv;
switch (addr) {
case 0x3b0: /* Command / control register */
genius->genius_control = val;
if (val & 1)
mem_mapping_set_addr(&genius->mapping, 0xa0000, 0x28000);
else
mem_mapping_set_addr(&genius->mapping, 0xb0000, 0x10000);
break;
case 0x3b1:
genius->genius_charh = val;
break;
/* Emulated CRTC, register select */
case 0x3b2:
case 0x3b4:
case 0x3b6:
genius->mda_crtcreg = val & 31;
break;
/* Emulated CRTC, value */
case 0x3b3:
case 0x3b5:
case 0x3b7:
genius->mda_crtc[genius->mda_crtcreg] = val;
genius_recalctimings(genius);
return;
/* Emulated MDA control register */
case 0x3b8:
genius->mda_ctrl = val;
return;
/* Emulated CRTC, register select */
case 0x3d0:
case 0x3d2:
case 0x3d4:
case 0x3d6:
genius->cga_crtcreg = val & 31;
break;
/* Emulated CRTC, value */
case 0x3d1:
case 0x3d3:
case 0x3d5:
case 0x3d7:
genius->cga_crtc[genius->cga_crtcreg] = val;
genius_recalctimings(genius);
return;
/* Emulated CGA control register */
case 0x3d8:
genius->cga_ctrl = val;
return;
/* Emulated CGA colour register */
case 0x3d9:
genius->cga_colour = val;
return;
default:
break;
}
}
uint8_t
genius_in(uint16_t addr, void *priv)
{
const genius_t *genius = (genius_t *) priv;
uint8_t ret = 0xff;
switch (addr) {
case 0x3b0:
case 0x3b2:
case 0x3b4:
case 0x3b6:
ret = genius->mda_crtcreg;
break;
case 0x3b1:
case 0x3b3:
case 0x3b5:
case 0x3b7:
ret = genius->mda_crtc[genius->mda_crtcreg];
break;
case 0x3b8:
ret = genius->mda_ctrl;
break;
case 0x3ba:
ret = genius->mda_stat;
break;
case 0x3d0:
case 0x3d2:
case 0x3d4:
case 0x3d6:
ret = genius->cga_crtcreg;
break;
case 0x3d1:
case 0x3d3:
case 0x3d5:
case 0x3d7:
ret = genius->cga_crtc[genius->cga_crtcreg];
break;
case 0x3d8:
ret = genius->cga_ctrl;
break;
case 0x3d9:
ret = genius->cga_colour;
break;
case 0x3da:
ret = genius->cga_stat;
break;
default:
break;
}
return ret;
}
static void
genius_waitstates(void)
{
int ws_array[16] = { 3, 4, 5, 6, 7, 8, 4, 5, 6, 7, 8, 4, 5, 6, 7, 8 };
int ws;
ws = ws_array[cycles & 0xf];
cycles -= ws;
}
void
genius_write(uint32_t addr, uint8_t val, void *priv)
{
genius_t *genius = (genius_t *) priv;
genius_waitstates();
if (genius->genius_control & 1) {
if ((addr >= 0xa0000) && (addr < 0xb0000))
addr = (addr - 0xa0000) & 0xffff;
else if ((addr >= 0xb0000) && (addr < 0xb8000))
addr = ((addr - 0xb0000) & 0x7fff) + 0x10000;
else
addr = ((addr - 0xb8000) & 0xffff) + 0x18000;
} else {
/* If hi-res memory is disabled, only visible in the B000 segment */
if (addr >= 0xb8000)
addr = (addr & 0x3FFF) + 0x18000;
else
addr = (addr & 0x7FFF) + 0x10000;
}
genius->vram[addr] = val;
}
uint8_t
genius_read(uint32_t addr, void *priv)
{
const genius_t *genius = (genius_t *) priv;
uint8_t ret;
genius_waitstates();
if (genius->genius_control & 1) {
if ((addr >= 0xa0000) && (addr < 0xb0000))
addr = (addr - 0xa0000) & 0xffff;
else if ((addr >= 0xb0000) && (addr < 0xb8000))
addr = ((addr - 0xb0000) & 0x7fff) + 0x10000;
else
addr = ((addr - 0xb8000) & 0xffff) + 0x18000;
} else {
/* If hi-res memory is disabled, only visible in the B000 segment */
if (addr >= 0xb8000)
addr = (addr & 0x3FFF) + 0x18000;
else
addr = (addr & 0x7FFF) + 0x10000;
}
ret = genius->vram[addr];
return ret;
}
void
genius_recalctimings(genius_t *genius)
{
double disptime;
double _dispontime;
double _dispofftime;
disptime = 0x31;
_dispontime = 0x28;
_dispofftime = disptime - _dispontime;
_dispontime *= MDACONST;
_dispofftime *= MDACONST;
genius->dispontime = (uint64_t) (_dispontime);
genius->dispofftime = (uint64_t) (_dispofftime);
}
static int
genius_lines(genius_t *genius)
{
int ret = 350;
switch (genius->genius_charh & 0x13) {
case 0x00:
ret = 990; /* 80x66 */
break;
case 0x01:
ret = 980; /* 80x70 */
break;
case 0x02:
ret = 988; /* Guess: 80x76 */
break;
case 0x03:
ret = 984; /* 80x82 */
break;
case 0x10:
ret = 375; /* Logic says 80x33 but it appears to be 80x25 */
break;
case 0x11:
ret = 490; /* Guess: 80x35, fits the logic as well, half of 80x70 */
break;
case 0x12:
ret = 494; /* Guess: 80x38 */
break;
case 0x13:
ret = 492; /* 80x41 */
break;
default:
break;
}
return ret;
}
/* Draw a single line of the screen in either text mode */
static void
genius_textline(genius_t *genius, uint8_t background, int mda, int cols80)
{
int w = 80; /* 80 characters across */
int cw = 9; /* Each character is 9 pixels wide */
uint8_t chr;
uint8_t attr;
uint8_t sc;
uint8_t ctrl;
const uint8_t *crtc;
uint8_t bitmap[2];
int blink;
int c;
int row;
int charh;
int drawcursor;
int cursorline;
uint16_t addr;
uint16_t ma = (genius->mda_crtc[13] | (genius->mda_crtc[12] << 8)) & 0x3fff;
uint16_t ca = (genius->mda_crtc[15] | (genius->mda_crtc[14] << 8)) & 0x3fff;
const uint8_t *framebuf = genius->vram + 0x10000;
uint32_t col;
uint32_t dl = genius->displine;
/* Character height is 12-15 */
if (mda) {
if (genius->displine >= genius_lines(genius))
return;
crtc = genius->mda_crtc;
ctrl = genius->mda_ctrl;
charh = 15 - (genius->genius_charh & 3);
#if 0
if (genius->genius_charh & 0x10) {
row = ((dl >> 1) / charh);
sc = ((dl >> 1) % charh);
} else {
row = (dl / charh);
sc = (dl % charh);
}
#else
row = (dl / charh);
sc = (dl % charh);
#endif
} else {
if ((genius->displine < 512) || (genius->displine >= 912))
return;
crtc = genius->cga_crtc;
ctrl = genius->cga_ctrl;
framebuf += 0x08000;
dl -= 512;
w = crtc[1];
cw = 8;
charh = crtc[9] + 1;
row = ((dl >> 1) / charh);
sc = ((dl >> 1) % charh);
}
ma = (crtc[13] | (crtc[12] << 8)) & 0x3fff;
ca = (crtc[15] | (crtc[14] << 8)) & 0x3fff;
addr = ((ma & ~1) + row * w) * 2;
if (!mda)
dl += 512;
ma += (row * w);
if ((crtc[10] & 0x60) == 0x20)
cursorline = 0;
else
cursorline = ((crtc[10] & 0x1F) <= sc) && ((crtc[11] & 0x1F) >= sc);
for (int x = 0; x < w; x++) {
#if 0
if ((genius->genius_charh & 0x10) && ((addr + 2 * x) > 0x0FFF))
chr = 0x00;
if ((genius->genius_charh & 0x10) && ((addr + 2 * x + 1) > 0x0FFF))
attr = 0x00;
#endif
chr = framebuf[(addr + 2 * x) & 0x3FFF];
attr = framebuf[(addr + 2 * x + 1) & 0x3FFF];
drawcursor = ((ma == ca) && cursorline && genius->enabled && (ctrl & 8));
switch (crtc[10] & 0x60) {
case 0x00:
drawcursor = drawcursor && (genius->blink & 16);
break;
case 0x60:
drawcursor = drawcursor && (genius->blink & 32);
break;
default:
break;
}
blink = ((genius->blink & 16) && (ctrl & 0x20) && (attr & 0x80) && !drawcursor);
if (ctrl & 0x20)
attr &= 0x7F;
/* MDA underline */
if (mda && (sc == charh) && ((attr & 7) == 1)) {
col = mdaattr[attr][blink][1];
if (genius->genius_control & 0x20)
col ^= 15;
for (c = 0; c < cw; c++) {
if (col != background) {
if (cols80)
buffer32->line[dl][(x * cw) + c] = col;
else {
buffer32->line[dl][((x * cw) << 1) + (c << 1)] = buffer32->line[dl][((x * cw) << 1) + (c << 1) + 1] = col;
}
}
}
} else { /* Draw 8 pixels of character */
if (mda)
bitmap[0] = fontdat8x12[chr][sc];
else
bitmap[0] = fontdat[chr][sc];
for (c = 0; c < 8; c++) {
col = mdaattr[attr][blink][(bitmap[0] & (1 << (c ^ 7))) ? 1 : 0];
if (!(genius->enabled) || !(ctrl & 8))
col = mdaattr[0][0][0];
if (genius->genius_control & 0x20)
col ^= 15;
if (col != background) {
if (cols80)
buffer32->line[dl][(x * cw) + c] = col;
else {
buffer32->line[dl][((x * cw) << 1) + (c << 1)] = buffer32->line[dl][((x * cw) << 1) + (c << 1) + 1] = col;
}
}
}
if (cw == 9) {
/* The ninth pixel column... */
if ((chr & ~0x1f) == 0xc0) {
/* Echo column 8 for the graphics chars */
if (cols80) {
col = buffer32->line[dl][(x * cw) + 7];
if (col != background)
buffer32->line[dl][(x * cw) + 8] = col;
} else {
col = buffer32->line[dl][((x * cw) << 1) + 14];
if (col != background) {
buffer32->line[dl][((x * cw) << 1) + 16] = buffer32->line[dl][((x * cw) << 1) + 17] = col;
}
}
} else { /* Otherwise fill with background */
col = mdaattr[attr][blink][0];
if (genius->genius_control & 0x20)
col ^= 15;
if (col != background) {
if (cols80)
buffer32->line[dl][(x * cw) + 8] = col;
else {
buffer32->line[dl][((x * cw) << 1) + 16] = buffer32->line[dl][((x * cw) << 1) + 17] = col;
}
}
}
}
if (drawcursor) {
for (c = 0; c < cw; c++) {
if (cols80)
buffer32->line[dl][(x * cw) + c] ^= mdaattr[attr][0][1];
else {
buffer32->line[dl][((x * cw) << 1) + (c << 1)] ^= mdaattr[attr][0][1];
buffer32->line[dl][((x * cw) << 1) + (c << 1) + 1] ^= mdaattr[attr][0][1];
}
}
}
++ma;
}
}
}
/* Draw a line in the CGA 640x200 mode */
void
genius_cgaline(genius_t *genius)
{
uint32_t dat;
uint32_t addr;
uint8_t ink_f;
uint8_t ink_b;
ink_f = (genius->genius_control & 0x20) ? genius_pal[0] : genius_pal[3];
ink_b = (genius->genius_control & 0x20) ? genius_pal[3] : genius_pal[0];
/* We draw the CGA at row 512 */
if ((genius->displine < 512) || (genius->displine >= 912))
return;
addr = 0x18000 + 80 * ((genius->displine - 512) >> 2);
if ((genius->displine - 512) & 2)
addr += 0x2000;
for (uint8_t x = 0; x < 80; x++) {
dat = genius->vram[addr];
addr++;
for (uint8_t c = 0; c < 8; c++) {
if (dat & 0x80)
buffer32->line[genius->displine][(x << 3) + c] = ink_f;
else
buffer32->line[genius->displine][(x << 3) + c] = ink_b;
dat = dat << 1;
}
}
}
/* Draw a line in the native high-resolution mode */
void
genius_hiresline(genius_t *genius)
{
uint32_t dat;
uint32_t addr;
uint8_t ink_f;
uint8_t ink_b;
ink_f = (genius->genius_control & 0x20) ? genius_pal[0] : genius_pal[3];
ink_b = (genius->genius_control & 0x20) ? genius_pal[3] : genius_pal[0];
/* The first 512 lines live at A0000 */
if (genius->displine < 512)
addr = 128 * genius->displine;
else /* The second 496 live at B8000 */
addr = 0x18000 + (128 * (genius->displine - 512));
for (uint8_t x = 0; x < 91; x++) {
dat = genius->vram[addr + x];
for (uint8_t c = 0; c < 8; c++) {
if (dat & 0x80)
buffer32->line[genius->displine][(x << 3) + c] = ink_f;
else
buffer32->line[genius->displine][(x << 3) + c] = ink_b;
dat = dat << 1;
}
}
}
void
genius_poll(void *priv)
{
genius_t *genius = (genius_t *) priv;
uint8_t background;
if (!genius->linepos) {
timer_advance_u64(&genius->timer, genius->dispofftime);
genius->cga_stat |= 1;
genius->mda_stat |= 1;
genius->linepos = 1;
if (genius->dispon) {
if (genius->genius_control & 0x20)
background = genius_pal[3];
else
background = genius_pal[0];
if (genius->displine == 0)
video_wait_for_buffer();
/* Start off with a blank line */
for (uint16_t x = 0; x < GENIUS_XSIZE; x++)
buffer32->line[genius->displine][x] = background;
/* If graphics display enabled, draw graphics on top
* of the blanked line */
if (genius->cga_ctrl & 8) {
if (((genius->genius_control & 0x11) == 0x00) || (genius->genius_control & 0x08))
genius_cgaline(genius);
else if ((genius->genius_control & 0x11) == 0x01)
genius_hiresline(genius);
else {
if (genius->cga_ctrl & 2)
genius_cgaline(genius);
else {
if (genius->cga_ctrl & 1)
genius_textline(genius, background, 0, 1);
else
genius_textline(genius, background, 0, 0);
}
}
}
/* If MDA display is enabled, draw MDA text on top
* of the lot */
if (genius->mda_ctrl & 8)
genius_textline(genius, background, 1, 1);
video_process_8(GENIUS_XSIZE, genius->displine);
}
genius->displine++;
/* Hardcode a fixed refresh rate and VSYNC timing */
if (genius->displine == 1008) { /* Start of VSYNC */
genius->cga_stat |= 8;
genius->mda_stat |= 8;
genius->dispon = 0;
}
if (genius->displine == 1040) { /* End of VSYNC */
genius->displine = 0;
genius->cga_stat &= ~8;
genius->mda_stat &= ~8;
genius->dispon = 1;
}
} else {
if (genius->dispon) {
genius->cga_stat &= ~1;
genius->mda_stat &= ~1;
}
timer_advance_u64(&genius->timer, genius->dispontime);
genius->linepos = 0;
if (genius->displine == 1008) {
/* Hardcode GENIUS_XSIZE * GENIUS_YSIZE window size */
if (GENIUS_XSIZE != xsize || GENIUS_YSIZE != ysize) {
xsize = GENIUS_XSIZE;
ysize = GENIUS_YSIZE;
if (xsize < 64)
xsize = 656;
if (ysize < 32)
ysize = 200;
set_screen_size(xsize, ysize);
if (video_force_resize_get())
video_force_resize_set(0);
}
video_blit_memtoscreen(0, 0, xsize, ysize);
frames++;
/* Fixed 728x1008 resolution */
video_res_x = GENIUS_XSIZE;
video_res_y = GENIUS_YSIZE;
video_bpp = 1;
genius->blink++;
}
}
}
void *
genius_init(UNUSED(const device_t *info))
{
genius_t *genius = malloc(sizeof(genius_t));
memset(genius, 0, sizeof(genius_t));
video_inform(VIDEO_FLAG_TYPE_MDA, &timing_genius);
/* 160k video RAM */
genius->vram = malloc(0x28000);
loadfont(BIOS_ROM_PATH, 4);
timer_add(&genius->timer, genius_poll, genius, 1);
/* Occupy memory between 0xB0000 and 0xBFFFF (moves to 0xA0000 in
* high-resolution modes) */
mem_mapping_add(&genius->mapping, 0xb0000, 0x10000, genius_read, NULL, NULL, genius_write, NULL, NULL, NULL, MEM_MAPPING_EXTERNAL, genius);
/* Respond to both MDA and CGA I/O ports */
io_sethandler(0x03b0, 0x000C, genius_in, NULL, NULL, genius_out, NULL, NULL, genius);
io_sethandler(0x03d0, 0x0010, genius_in, NULL, NULL, genius_out, NULL, NULL, genius);
genius_pal[0] = 0 + 16; /* 0 */
genius_pal[1] = 8 + 16; /* 8 */
genius_pal[2] = 7 + 16; /* 7 */
genius_pal[3] = 15 + 16; /* F */
/* MDA attributes */
/* I don't know if the Genius's MDA emulation actually does
* emulate bright / non-bright. For the time being pretend it does. */
for (uint16_t c = 0; c < 256; c++) {
mdaattr[c][0][0] = mdaattr[c][1][0] = mdaattr[c][1][1] = genius_pal[0];
if (c & 8)
mdaattr[c][0][1] = genius_pal[3];
else
mdaattr[c][0][1] = genius_pal[2];
}
mdaattr[0x70][0][1] = genius_pal[0];
mdaattr[0x70][0][0] = mdaattr[0x70][1][0] = mdaattr[0x70][1][1] = genius_pal[3];
mdaattr[0xF0][0][1] = genius_pal[0];
mdaattr[0xF0][0][0] = mdaattr[0xF0][1][0] = mdaattr[0xF0][1][1] = genius_pal[3];
mdaattr[0x78][0][1] = genius_pal[2];
mdaattr[0x78][0][0] = mdaattr[0x78][1][0] = mdaattr[0x78][1][1] = genius_pal[3];
mdaattr[0xF8][0][1] = genius_pal[2];
mdaattr[0xF8][0][0] = mdaattr[0xF8][1][0] = mdaattr[0xF8][1][1] = genius_pal[3];
mdaattr[0x00][0][1] = mdaattr[0x00][1][1] = genius_pal[0];
mdaattr[0x08][0][1] = mdaattr[0x08][1][1] = genius_pal[0];
mdaattr[0x80][0][1] = mdaattr[0x80][1][1] = genius_pal[0];
mdaattr[0x88][0][1] = mdaattr[0x88][1][1] = genius_pal[0];
/* Start off in 80x25 text mode */
genius->cga_stat = 0xF4;
genius->genius_mode = 2;
genius->enabled = 1;
genius->genius_charh = 0x90; /* Native character height register */
genius->genius_control |= 0x10;
return genius;
}
void
genius_close(void *priv)
{
genius_t *genius = (genius_t *) priv;
free(genius->vram);
free(genius);
}
static int
genius_available(void)
{
return rom_present(BIOS_ROM_PATH);
}
void
genius_speed_changed(void *priv)
{
genius_t *genius = (genius_t *) priv;
genius_recalctimings(genius);
}
const device_t genius_device = {
.name = "Genius VHR",
.internal_name = "genius",
.flags = DEVICE_ISA,
.local = 0,
.init = genius_init,
.close = genius_close,
.reset = NULL,
{ .available = genius_available },
.speed_changed = genius_speed_changed,
.force_redraw = NULL,
.config = NULL
};
``` | /content/code_sandbox/src/video/vid_genius.c | c | 2016-06-25T22:29:10 | 2024-08-16T19:09:21 | 86Box | 86Box/86Box | 2,616 | 7,947 |
```c
/*
* 86Box A hypervisor and IBM PC system emulator that specializes in
* running old operating systems and software designed for IBM
* PC systems and compatibles from 1981 through fairly recent
* system designs based on the PCI bus.
*
* This file is part of the 86Box distribution.
*
* 3DFX Voodoo emulation.
*
*
*
* Authors: Sarah Walker, <path_to_url
*
*/
#include <stdarg.h>
#include <stdio.h>
#include <stdint.h>
#include <string.h>
#include <stdlib.h>
#include <stddef.h>
#include <wchar.h>
#include <math.h>
#define HAVE_STDARG_H
#include <86box/86box.h>
#include "cpu.h"
#include <86box/machine.h>
#include <86box/device.h>
#include <86box/mem.h>
#include <86box/timer.h>
#include <86box/device.h>
#include <86box/plat.h>
#include <86box/thread.h>
#include <86box/video.h>
#include <86box/vid_svga.h>
#include <86box/vid_voodoo_common.h>
#include <86box/vid_voodoo_dither.h>
#include <86box/vid_voodoo_regs.h>
#include <86box/vid_voodoo_render.h>
#include <86box/vid_voodoo_fb.h>
#ifdef ENABLE_VOODOO_FB_LOG
int voodoo_fb_do_log = ENABLE_VOODOO_FB_LOG;
static void
voodoo_fb_log(const char *fmt, ...)
{
va_list ap;
if (voodoo_fb_do_log) {
va_start(ap, fmt);
pclog_ex(fmt, ap);
va_end(ap);
}
}
#else
# define voodoo_fb_log(fmt, ...)
#endif
uint16_t
voodoo_fb_readw(uint32_t addr, void *priv)
{
voodoo_t *voodoo = (voodoo_t *) priv;
int x;
int y;
uint32_t read_addr;
uint16_t temp;
if (voodoo->type >= VOODOO_BANSHEE) {
x = addr & 0xffe;
y = (addr >> 12) & 0x3ff;
} else {
x = addr & 0x7fe;
y = (addr >> 11) & 0x3ff;
}
if (SLI_ENABLED) {
const voodoo_set_t *set = voodoo->set;
if (y & 1)
voodoo = set->voodoos[1];
else
voodoo = set->voodoos[0];
y >>= 1;
}
if (voodoo->col_tiled)
read_addr = voodoo->fb_read_offset + (x & 127) + (x >> 7) * 128 * 32 + (y & 31) * 128 + (y >> 5) * voodoo->row_width;
else
read_addr = voodoo->fb_read_offset + x + (y * voodoo->row_width);
if (read_addr > voodoo->fb_mask)
return 0xffff;
temp = *(uint16_t *) (&voodoo->fb_mem[read_addr & voodoo->fb_mask]);
// voodoo_fb_log("voodoo_fb_readw : %08X %08X %i %i %08X %08X %08x:%08x %i\n", addr, temp, x, y, read_addr, *(uint32_t *)(&voodoo->fb_mem[4]), cs, pc, fb_reads++);
return temp;
}
uint32_t
voodoo_fb_readl(uint32_t addr, void *priv)
{
voodoo_t *voodoo = (voodoo_t *) priv;
int x;
int y;
uint32_t read_addr;
uint32_t temp;
if (voodoo->type >= VOODOO_BANSHEE) {
x = addr & 0xffe;
y = (addr >> 12) & 0x3ff;
} else {
x = addr & 0x7fe;
y = (addr >> 11) & 0x3ff;
}
if (SLI_ENABLED) {
const voodoo_set_t *set = voodoo->set;
if (y & 1)
voodoo = set->voodoos[1];
else
voodoo = set->voodoos[0];
y >>= 1;
}
if (voodoo->col_tiled)
read_addr = voodoo->fb_read_offset + (x & 127) + (x >> 7) * 128 * 32 + (y & 31) * 128 + (y >> 5) * voodoo->row_width;
else
read_addr = voodoo->fb_read_offset + x + (y * voodoo->row_width);
if (read_addr > voodoo->fb_mask)
return 0xffffffff;
temp = *(uint32_t *) (&voodoo->fb_mem[read_addr & voodoo->fb_mask]);
// voodoo_fb_log("voodoo_fb_readl : %08X %08x %08X x=%i y=%i %08X %08X %08x:%08x %i ro=%08x rw=%i\n", addr, read_addr, temp, x, y, read_addr, *(uint32_t *)(&voodoo->fb_mem[4]), cs, pc, fb_reads++, voodoo->fb_read_offset, voodoo->row_width);
return temp;
}
static inline uint16_t
do_dither(voodoo_params_t *params, rgba8_t col, int x, int y)
{
int r;
int g;
int b;
if (dither) {
if (dither2x2) {
r = dither_rb2x2[col.r][y & 1][x & 1];
g = dither_g2x2[col.g][y & 1][x & 1];
b = dither_rb2x2[col.b][y & 1][x & 1];
} else {
r = dither_rb[col.r][y & 3][x & 3];
g = dither_g[col.g][y & 3][x & 3];
b = dither_rb[col.b][y & 3][x & 3];
}
} else {
r = col.r >> 3;
g = col.g >> 2;
b = col.b >> 3;
}
return b | (g << 5) | (r << 11);
}
void
voodoo_fb_writew(uint32_t addr, uint16_t val, void *priv)
{
voodoo_t *voodoo = (voodoo_t *) priv;
const voodoo_params_t *params = &voodoo->params;
int x;
int y;
uint32_t write_addr;
uint32_t write_addr_aux;
rgba8_t colour_data;
uint16_t depth_data;
uint8_t alpha_data;
int write_mask = 0;
colour_data.r = colour_data.g = colour_data.b = colour_data.a = 0;
depth_data = voodoo->params.zaColor & 0xffff;
alpha_data = voodoo->params.zaColor >> 24;
#if 0
while (!RB_EMPTY)
thread_reset_event(voodoo->not_full_event);
#endif
#if 0
voodoo_fb_log("voodoo_fb_writew : %08X %04X\n", addr, val);
#endif
switch (voodoo->lfbMode & LFB_FORMAT_MASK) {
case LFB_FORMAT_RGB565:
colour_data = rgb565[val];
alpha_data = 0xff;
write_mask = LFB_WRITE_COLOUR;
break;
case LFB_FORMAT_RGB555:
colour_data = argb1555[val];
alpha_data = 0xff;
write_mask = LFB_WRITE_COLOUR;
break;
case LFB_FORMAT_ARGB1555:
colour_data = argb1555[val];
alpha_data = colour_data.a;
write_mask = LFB_WRITE_COLOUR;
break;
case LFB_FORMAT_DEPTH:
depth_data = val;
write_mask = LFB_WRITE_DEPTH;
break;
default:
fatal("voodoo_fb_writew : bad LFB format %08X\n", voodoo->lfbMode);
}
if (voodoo->type >= VOODOO_BANSHEE) {
x = addr & 0xffe;
y = (addr >> 12) & 0x3ff;
} else {
x = addr & 0x7fe;
y = (addr >> 11) & 0x3ff;
}
if (SLI_ENABLED) {
if ((!(voodoo->initEnable & INITENABLE_SLI_MASTER_SLAVE) && (y & 1)) || ((voodoo->initEnable & INITENABLE_SLI_MASTER_SLAVE) && !(y & 1)))
return;
y >>= 1;
}
if (voodoo->fb_write_offset == voodoo->params.front_offset && y < 2048)
voodoo->dirty_line[y] = 1;
if (voodoo->col_tiled)
write_addr = voodoo->fb_write_offset + (x & 127) + (x >> 7) * 128 * 32 + (y & 31) * 128 + (y >> 5) * voodoo->row_width;
else
write_addr = voodoo->fb_write_offset + x + (y * voodoo->row_width);
if (voodoo->aux_tiled)
write_addr_aux = voodoo->params.aux_offset + (x & 127) + (x >> 7) * 128 * 32 + (y & 31) * 128 + (y >> 5) * voodoo->row_width;
else
write_addr_aux = voodoo->params.aux_offset + x + (y * voodoo->row_width);
// voodoo_fb_log("fb_writew %08x %i %i %i %08x\n", addr, x, y, voodoo->row_width, write_addr);
if (voodoo->lfbMode & 0x100) {
{
rgba8_t write_data = colour_data;
uint16_t new_depth = depth_data;
if (params->fbzMode & FBZ_DEPTH_ENABLE) {
uint16_t old_depth = *(uint16_t *) (&voodoo->fb_mem[write_addr_aux & voodoo->fb_mask]);
DEPTH_TEST(new_depth);
}
if ((params->fbzMode & FBZ_CHROMAKEY) && write_data.r == params->chromaKey_r && write_data.g == params->chromaKey_g && write_data.b == params->chromaKey_b)
goto skip_pixel;
if (params->fogMode & FOG_ENABLE) {
int32_t z = new_depth << 12;
int64_t w_depth = (int64_t) (int32_t) new_depth;
int32_t ia = alpha_data << 12;
APPLY_FOG(write_data.r, write_data.g, write_data.b, z, ia, w_depth);
}
if (params->alphaMode & 1)
ALPHA_TEST(alpha_data);
if (params->alphaMode & (1 << 4)) {
uint16_t dat = *(uint16_t *) (&voodoo->fb_mem[write_addr & voodoo->fb_mask]);
int dest_r;
int dest_g;
int dest_b;
int dest_a;
dest_r = (dat >> 8) & 0xf8;
dest_g = (dat >> 3) & 0xfc;
dest_b = (dat << 3) & 0xf8;
dest_r |= (dest_r >> 5);
dest_g |= (dest_g >> 6);
dest_b |= (dest_b >> 5);
dest_a = 0xff;
ALPHA_BLEND(write_data.r, write_data.g, write_data.b, alpha_data);
}
if (params->fbzMode & FBZ_RGB_WMASK)
*(uint16_t *) (&voodoo->fb_mem[write_addr & voodoo->fb_mask]) = do_dither(&voodoo->params, write_data, x >> 1, y);
if (params->fbzMode & FBZ_DEPTH_WMASK)
*(uint16_t *) (&voodoo->fb_mem[write_addr_aux & voodoo->fb_mask]) = new_depth;
skip_pixel:
return;
}
} else {
if (write_mask & LFB_WRITE_COLOUR)
*(uint16_t *) (&voodoo->fb_mem[write_addr & voodoo->fb_mask]) = do_dither(&voodoo->params, colour_data, x >> 1, y);
if (write_mask & LFB_WRITE_DEPTH)
*(uint16_t *) (&voodoo->fb_mem[write_addr_aux & voodoo->fb_mask]) = depth_data;
}
}
void
voodoo_fb_writel(uint32_t addr, uint32_t val, void *priv)
{
voodoo_t *voodoo = (voodoo_t *) priv;
const voodoo_params_t *params = &voodoo->params;
int x;
int y;
uint32_t write_addr;
uint32_t write_addr_aux;
rgba8_t colour_data[2];
uint16_t depth_data[2];
uint8_t alpha_data[2];
int write_mask = 0;
int count = 1;
depth_data[0] = depth_data[1] = voodoo->params.zaColor & 0xffff;
alpha_data[0] = alpha_data[1] = voodoo->params.zaColor >> 24;
#if 0
while (!RB_EMPTY)
thread_reset_event(voodoo->not_full_event);
#endif
#if 0
voodoo_fb_log("voodoo_fb_writel : %08X %08X\n", addr, val);
#endif
switch (voodoo->lfbMode & LFB_FORMAT_MASK) {
case LFB_FORMAT_RGB565:
colour_data[0] = rgb565[val & 0xffff];
colour_data[1] = rgb565[val >> 16];
write_mask = LFB_WRITE_COLOUR;
count = 2;
break;
case LFB_FORMAT_RGB555:
colour_data[0] = argb1555[val & 0xffff];
colour_data[1] = argb1555[val >> 16];
write_mask = LFB_WRITE_COLOUR;
count = 2;
break;
case LFB_FORMAT_ARGB1555:
colour_data[0] = argb1555[val & 0xffff];
alpha_data[0] = colour_data[0].a;
colour_data[1] = argb1555[val >> 16];
alpha_data[1] = colour_data[1].a;
write_mask = LFB_WRITE_COLOUR;
count = 2;
break;
case LFB_FORMAT_ARGB8888:
colour_data[0].b = val & 0xff;
colour_data[0].g = (val >> 8) & 0xff;
colour_data[0].r = (val >> 16) & 0xff;
alpha_data[0] = (val >> 24) & 0xff;
write_mask = LFB_WRITE_COLOUR;
addr >>= 1;
break;
case LFB_FORMAT_DEPTH:
depth_data[0] = val;
depth_data[1] = val >> 16;
write_mask = LFB_WRITE_DEPTH;
count = 2;
break;
default:
fatal("voodoo_fb_writel : bad LFB format %08X\n", voodoo->lfbMode);
}
if (voodoo->type >= VOODOO_BANSHEE) {
x = addr & 0xffe;
y = (addr >> 12) & 0x3ff;
} else {
x = addr & 0x7fe;
y = (addr >> 11) & 0x3ff;
}
if (SLI_ENABLED) {
if ((!(voodoo->initEnable & INITENABLE_SLI_MASTER_SLAVE) && (y & 1)) || ((voodoo->initEnable & INITENABLE_SLI_MASTER_SLAVE) && !(y & 1)))
return;
y >>= 1;
}
if (voodoo->fb_write_offset == voodoo->params.front_offset && y < 2048)
voodoo->dirty_line[y] = 1;
if (voodoo->col_tiled)
write_addr = voodoo->fb_write_offset + (x & 127) + (x >> 7) * 128 * 32 + (y & 31) * 128 + (y >> 5) * voodoo->row_width;
else
write_addr = voodoo->fb_write_offset + x + (y * voodoo->row_width);
if (voodoo->aux_tiled)
write_addr_aux = voodoo->params.aux_offset + (x & 127) + (x >> 7) * 128 * 32 + (y & 31) * 128 + (y >> 5) * voodoo->row_width;
else
write_addr_aux = voodoo->params.aux_offset + x + (y * voodoo->row_width);
#if 0
voodoo_fb_log("fb_writel %08x x=%i y=%i rw=%i %08x wo=%08x\n", addr, x, y, voodoo->row_width, write_addr, voodoo->fb_write_offset);
#endif
if (voodoo->lfbMode & 0x100) {
for (int c = 0; c < count; c++) {
rgba8_t write_data = colour_data[c];
uint16_t new_depth = depth_data[c];
if (params->fbzMode & FBZ_DEPTH_ENABLE) {
uint16_t old_depth = *(uint16_t *) (&voodoo->fb_mem[write_addr_aux & voodoo->fb_mask]);
DEPTH_TEST(new_depth);
}
if ((params->fbzMode & FBZ_CHROMAKEY) && write_data.r == params->chromaKey_r && write_data.g == params->chromaKey_g && write_data.b == params->chromaKey_b)
goto skip_pixel;
if (params->fogMode & FOG_ENABLE) {
int32_t z = new_depth << 12;
int64_t w_depth = new_depth;
int32_t ia = alpha_data[c] << 12;
APPLY_FOG(write_data.r, write_data.g, write_data.b, z, ia, w_depth);
}
if (params->alphaMode & 1)
ALPHA_TEST(alpha_data[c]);
if (params->alphaMode & (1 << 4)) {
uint16_t dat = *(uint16_t *) (&voodoo->fb_mem[write_addr & voodoo->fb_mask]);
int dest_r;
int dest_g;
int dest_b;
int dest_a;
dest_r = (dat >> 8) & 0xf8;
dest_g = (dat >> 3) & 0xfc;
dest_b = (dat << 3) & 0xf8;
dest_r |= (dest_r >> 5);
dest_g |= (dest_g >> 6);
dest_b |= (dest_b >> 5);
dest_a = 0xff;
ALPHA_BLEND(write_data.r, write_data.g, write_data.b, alpha_data[c]);
}
if (params->fbzMode & FBZ_RGB_WMASK)
*(uint16_t *) (&voodoo->fb_mem[write_addr & voodoo->fb_mask]) = do_dither(&voodoo->params, write_data, (x >> 1) + c, y);
if (params->fbzMode & FBZ_DEPTH_WMASK)
*(uint16_t *) (&voodoo->fb_mem[write_addr_aux & voodoo->fb_mask]) = new_depth;
skip_pixel:
write_addr += 2;
write_addr_aux += 2;
}
} else {
for (int c = 0; c < count; c++) {
if (write_mask & LFB_WRITE_COLOUR)
*(uint16_t *) (&voodoo->fb_mem[write_addr & voodoo->fb_mask]) = do_dither(&voodoo->params, colour_data[c], (x >> 1) + c, y);
if (write_mask & LFB_WRITE_DEPTH)
*(uint16_t *) (&voodoo->fb_mem[write_addr_aux & voodoo->fb_mask]) = depth_data[c];
write_addr += 2;
write_addr_aux += 2;
}
}
}
``` | /content/code_sandbox/src/video/vid_voodoo_fb.c | c | 2016-06-25T22:29:10 | 2024-08-16T19:09:21 | 86Box | 86Box/86Box | 2,616 | 4,650 |
```c
/*
* 86Box A hypervisor and IBM PC system emulator that specializes in
* running old operating systems and software designed for IBM
* PC systems and compatibles from 1981 through fairly recent
* system designs based on the PCI bus.
*
* This file is part of the 86Box distribution.
*
* S3 ViRGE emulation.
*
*
*
* Authors: Sarah Walker, <path_to_url
* Miran Grca, <mgrca8@gmail.com>
*
*/
#include <stdarg.h>
#include <stdint.h>
#include <stdio.h>
#include <string.h>
#include <stdlib.h>
#include <wchar.h>
#include <stdatomic.h>
#define HAVE_STDARG_H
#include <86box/86box.h>
#include <86box/io.h>
#include <86box/timer.h>
#include <86box/dma.h>
#include <86box/mem.h>
#include <86box/pci.h>
#include <86box/rom.h>
#include <86box/device.h>
#include <86box/plat.h>
#include <86box/thread.h>
#include <86box/video.h>
#include <86box/i2c.h>
#include <86box/vid_ddc.h>
#include <86box/vid_svga.h>
#include <86box/vid_svga_render.h>
#ifdef MIN
#undef MIN
#endif
#ifdef MAX
#undef MAX
#endif
#ifdef CLAMP
#undef CLAMP
#endif
static uint64_t virge_time = 0;
static int dither[4][4] = {
{0, 4, 1, 5},
{6, 2, 7, 3},
{1, 5, 0, 4},
{7, 3, 6, 2}
};
#define ROM_VIRGE_325 "roms/video/s3virge/86c325.bin"
#define ROM_DIAMOND_STEALTH3D_2000 "roms/video/s3virge/s3virge.bin"
#define ROM_DIAMOND_STEALTH3D_3000 "roms/video/s3virge/diamondstealth3000.vbi"
#define ROM_STB_VELOCITY_3D "roms/video/s3virge/stb_velocity3d_110.BIN"
#define ROM_VIRGE_DX "roms/video/s3virge/86c375_1.bin"
#define ROM_DIAMOND_STEALTH3D_2000PRO "roms/video/s3virge/virgedxdiamond.vbi"
#define ROM_VIRGE_GX "roms/video/s3virge/86c375_4.bin"
#define ROM_VIRGE_GX2 "roms/video/s3virge/flagpoint.VBI"
#define ROM_DIAMOND_STEALTH3D_4000 "roms/video/s3virge/DS3D4K v1.03 Brightness bug fix.bin"
#define ROM_TRIO3D2X "roms/video/s3virge/TRIO3D2X_8mbsdr.VBI"
#define RB_SIZE 256
#define RB_MASK (RB_SIZE - 1)
#define RB_ENTRIES (virge->s3d_write_idx - virge->s3d_read_idx)
#define RB_FULL (RB_ENTRIES == RB_SIZE)
#define RB_EMPTY (!RB_ENTRIES)
#define FIFO_SIZE 65536
#define FIFO_MASK (FIFO_SIZE - 1)
#define FIFO_ENTRY_SIZE (1 << 31)
#define FIFO_ENTRIES (virge->fifo_write_idx - virge->fifo_read_idx)
#define FIFO_FULL ((virge->fifo_write_idx - virge->fifo_read_idx) >= FIFO_SIZE)
#define FIFO_EMPTY (virge->fifo_read_idx == virge->fifo_write_idx)
#define FIFO_TYPE 0xff000000
#define FIFO_ADDR 0x00ffffff
enum {
S3_VIRGE_325,
S3_DIAMOND_STEALTH3D_2000,
S3_DIAMOND_STEALTH3D_3000,
S3_STB_VELOCITY_3D,
S3_VIRGE_DX,
S3_DIAMOND_STEALTH3D_2000PRO,
S3_VIRGE_GX,
S3_VIRGE_GX2,
S3_DIAMOND_STEALTH3D_4000,
S3_TRIO_3D2X
};
enum {
S3_VIRGE,
S3_VIRGEVX,
S3_VIRGEDX,
S3_VIRGEGX2,
S3_TRIO3D2X
};
enum {
FIFO_INVALID = (0x00 << 24),
FIFO_WRITE_BYTE = (0x01 << 24),
FIFO_WRITE_WORD = (0x02 << 24),
FIFO_WRITE_DWORD = (0x03 << 24)
};
typedef struct {
uint32_t addr_type;
uint32_t val;
} fifo_entry_t;
typedef struct s3d_t {
uint32_t cmd_set;
int clip_l;
int clip_r;
int clip_t;
int clip_b;
uint32_t dest_base;
uint32_t dest_str;
uint32_t z_base;
uint32_t z_str;
uint32_t tex_base;
uint32_t tex_bdr_clr;
uint32_t tbv;
uint32_t tbu;
int32_t TdVdX;
int32_t TdUdX;
int32_t TdVdY;
int32_t TdUdY;
uint32_t tus;
uint32_t tvs;
int32_t TdZdX;
int32_t TdZdY;
uint32_t tzs;
int32_t TdWdX;
int32_t TdWdY;
uint32_t tws;
int32_t TdDdX;
int32_t TdDdY;
uint32_t tds;
int16_t TdGdX;
int16_t TdBdX;
int16_t TdRdX;
int16_t TdAdX;
int16_t TdGdY;
int16_t TdBdY;
int16_t TdRdY;
int16_t TdAdY;
uint32_t tgs;
uint32_t tbs;
uint32_t trs;
uint32_t tas;
uint32_t TdXdY12;
uint32_t txend12;
uint32_t TdXdY01;
uint32_t txend01;
uint32_t TdXdY02;
uint32_t txs;
uint32_t tys;
int ty01;
int ty12;
int tlr;
uint8_t fog_r;
uint8_t fog_g;
uint8_t fog_b;
} s3d_t;
typedef struct virge_t {
mem_mapping_t linear_mapping;
mem_mapping_t mmio_mapping;
mem_mapping_t new_mmio_mapping;
rom_t bios_rom;
svga_t svga;
uint8_t bank;
uint8_t ma_ext;
uint8_t virge_id;
uint8_t virge_id_high;
uint8_t virge_id_low;
uint8_t virge_rev;
uint32_t linear_base;
uint32_t linear_size;
uint8_t pci_regs[256];
uint8_t pci_slot;
int chip;
int bilinear_enabled;
int dithering_enabled;
int memory_size;
int pixel_count;
int tri_count;
thread_t * render_thread;
event_t * wake_render_thread;
event_t * wake_main_thread;
event_t * not_full_event;
uint32_t hwc_fg_col;
uint32_t hwc_bg_col;
int hwc_col_stack_pos;
struct {
uint32_t src_base;
uint32_t dest_base;
int clip_l;
int clip_r;
int clip_t;
int clip_b;
int dest_str;
int src_str;
uint32_t mono_pat_0;
uint32_t mono_pat_1;
uint32_t pat_bg_clr;
uint32_t pat_fg_clr;
uint32_t src_bg_clr;
uint32_t src_fg_clr;
uint32_t cmd_set;
int r_width;
int r_height;
int rsrc_x;
int rsrc_y;
int rdest_x;
int rdest_y;
int lxend0;
int lxend1;
int32_t ldx;
uint32_t lxstart;
uint32_t lystart;
int lycnt;
int line_dir;
int src_x;
int src_y;
int dest_x;
int dest_y;
int w;
int h;
uint8_t rop;
int data_left_count;
uint32_t data_left;
uint32_t pattern_8[8 * 8];
uint32_t pattern_16[8 * 8];
uint32_t pattern_24[8 * 8];
uint32_t pattern_32[8 * 8];
uint32_t prdx;
uint32_t prxstart;
uint32_t pldx;
uint32_t plxstart;
uint32_t pystart;
uint32_t pycnt;
uint32_t dest_l, dest_r;
} s3d;
s3d_t s3d_tri;
s3d_t s3d_buffer[RB_SIZE];
atomic_int s3d_read_idx;
atomic_int s3d_write_idx;
atomic_int s3d_busy;
struct {
uint32_t pri_ctrl;
uint32_t chroma_ctrl;
uint32_t sec_ctrl;
uint32_t chroma_upper_bound;
uint32_t sec_filter;
uint32_t blend_ctrl;
uint32_t pri_fb0, pri_fb1;
uint32_t pri_stride;
uint32_t buffer_ctrl;
uint32_t sec_fb0, sec_fb1;
uint32_t sec_stride;
uint32_t overlay_ctrl;
int32_t k1_vert_scale;
int32_t k2_vert_scale;
int32_t dda_vert_accumulator;
int32_t k1_horiz_scale;
int32_t k2_horiz_scale;
int32_t dda_horiz_accumulator;
uint32_t fifo_ctrl;
uint32_t pri_start;
uint32_t pri_size;
uint32_t sec_start;
uint32_t sec_size;
int sdif;
int pri_x;
int pri_y;
int pri_w;
int pri_h;
int sec_x;
int sec_y;
int sec_w;
int sec_h;
} streams;
fifo_entry_t fifo[FIFO_SIZE];
atomic_int fifo_read_idx, fifo_write_idx;
atomic_int fifo_thread_run, render_thread_run;
thread_t * fifo_thread;
event_t *wake_fifo_thread;
event_t * fifo_not_full_event;
atomic_int virge_busy;
uint8_t subsys_stat;
uint8_t subsys_cntl;
int local;
uint8_t serialport;
uint8_t irq_state;
uint8_t advfunc_cntl;
void *i2c, *ddc;
int onboard;
int fifo_slots_num;
uint32_t vram_mask;
uint8_t reg6b;
uint8_t lfb_bios;
uint8_t int_line;
uint8_t cmd_dma;
uint32_t cmd_dma_base;
uint32_t cmd_dma_buf_size;
uint32_t cmd_dma_buf_size_mask;
uint32_t cmd_base_addr;
uint32_t cmd_dma_write_ptr_reg;
uint32_t cmd_dma_write_ptr_update;
uint32_t cmd_dma_read_ptr_reg;
uint32_t dma_val;
uint32_t dma_dbl_words;
uint32_t dma_mmio_addr;
uint32_t dma_data_type;
int pci;
int is_agp;
} virge_t;
static __inline void
wake_fifo_thread(virge_t *virge) {
/* Wake up FIFO thread if moving from idle */
thread_set_event(virge->wake_fifo_thread);
}
static virge_t *reset_state = NULL;
static video_timings_t timing_diamond_stealth3d_2000_pci = { .type = VIDEO_PCI, .write_b = 2, .write_w = 2, .write_l = 3, .read_b = 28, .read_w = 28, .read_l = 45 };
static video_timings_t timing_diamond_stealth3d_3000_pci = { .type = VIDEO_PCI, .write_b = 2, .write_w = 2, .write_l = 4, .read_b = 26, .read_w = 26, .read_l = 42 };
static video_timings_t timing_virge_dx_pci = { .type = VIDEO_PCI, .write_b = 2, .write_w = 2, .write_l = 3, .read_b = 28, .read_w = 28, .read_l = 45 };
static video_timings_t timing_virge_agp = { .type = VIDEO_AGP, .write_b = 2, .write_w = 2, .write_l = 3, .read_b = 28, .read_w = 28, .read_l = 45 };
static void queue_triangle(virge_t *virge);
static void s3_virge_recalctimings(svga_t *svga);
static void s3_virge_updatemapping(virge_t *virge);
static void s3_virge_bitblt(virge_t *virge, int count, uint32_t cpu_dat);
static uint8_t s3_virge_mmio_read(uint32_t addr, void *priv);
static uint16_t s3_virge_mmio_read_w(uint32_t addr, void *priv);
static uint32_t s3_virge_mmio_read_l(uint32_t addr, void *priv);
static void s3_virge_mmio_write(uint32_t addr, uint8_t val, void *priv);
static void s3_virge_mmio_write_w(uint32_t addr, uint16_t val, void *priv);
static void s3_virge_mmio_write_l(uint32_t addr, uint32_t val, void *priv);
static void s3_virge_queue(virge_t *virge, uint32_t addr, uint32_t val, uint32_t type);
enum {
CMD_SET_AE = 1,
CMD_SET_HC = (1 << 1),
CMD_SET_FORMAT_MASK = (7 << 2),
CMD_SET_FORMAT_8 = (0 << 2),
CMD_SET_FORMAT_16 = (1 << 2),
CMD_SET_FORMAT_24 = (2 << 2),
CMD_SET_MS = (1 << 6),
CMD_SET_IDS = (1 << 7),
CMD_SET_MP = (1 << 8),
CMD_SET_TP = (1 << 9),
CMD_SET_ITA_MASK = (3 << 10),
CMD_SET_ITA_BYTE = (0 << 10),
CMD_SET_ITA_WORD = (1 << 10),
CMD_SET_ITA_DWORD = (2 << 10),
CMD_SET_ZUP = (1 << 23),
CMD_SET_ZB_MODE = (3 << 24),
CMD_SET_XP = (1 << 25),
CMD_SET_YP = (1 << 26),
CMD_SET_COMMAND_MASK = (15 << 27)
};
#define CMD_SET_FE (1 << 17)
#define CMD_SET_ABC_SRC (1 << 18)
#define CMD_SET_ABC_ENABLE (1 << 19)
#define CMD_SET_TWE (1 << 26)
enum {
CMD_SET_COMMAND_BITBLT = (0 << 27),
CMD_SET_COMMAND_RECTFILL = (2 << 27),
CMD_SET_COMMAND_LINE = (3 << 27),
CMD_SET_COMMAND_POLY = (5 << 27),
CMD_SET_COMMAND_NOP = (15 << 27)
};
#define INT_VSY (1 << 0)
#define INT_S3D_DONE (1 << 1)
#define INT_FIFO_OVF (1 << 2)
#define INT_FIFO_EMP (1 << 3)
#define INT_HOST_DONE (1 << 4)
#define INT_CMD_DONE (1 << 5)
#define INT_3DF_EMP (1 << 6)
#define INT_MASK 0xff
#define SERIAL_PORT_SCW (1 << 0)
#define SERIAL_PORT_SDW (1 << 1)
#define SERIAL_PORT_SCR (1 << 2)
#define SERIAL_PORT_SDR (1 << 3)
static void
s3_virge_update_irqs(virge_t *virge) {
if ((virge->svga.crtc[0x32] & 0x10) && (virge->subsys_stat & virge->subsys_cntl & INT_MASK))
pci_set_irq(virge->pci_slot, PCI_INTA, &virge->irq_state);
else
pci_clear_irq(virge->pci_slot, PCI_INTA, &virge->irq_state);
}
static void
s3_virge_out(uint16_t addr, uint8_t val, void *priv) {
virge_t *virge = (virge_t *) priv;
svga_t * svga = &virge->svga;
uint8_t old;
uint32_t cursoraddr;
if (((addr & 0xfff0) == 0x3d0 || (addr & 0xfff0) == 0x3b0) && !(svga->miscout & 1))
addr ^= 0x60;
switch (addr) {
case 0x3c5:
if (svga->seqaddr >= 0x10) {
svga->seqregs[svga->seqaddr & 0x1f] = val;
svga_recalctimings(svga);
return;
}
if (svga->seqaddr == 4) { /*Chain-4 - update banking*/
if (val & 8)
svga->write_bank = svga->read_bank = virge->bank << 16;
else
svga->write_bank = svga->read_bank = virge->bank << 14;
} else if (svga->seqaddr == 0x08) {
svga->seqregs[svga->seqaddr] = val & 0x0f;
return;
} else if ((svga->seqaddr == 0x0d) && (svga->seqregs[0x08] == 0x06)) {
svga->seqregs[svga->seqaddr] = val;
svga->dpms = (svga->seqregs[0x0d] & 0x50) || (svga->crtc[0x56] & 0x06);
svga_recalctimings(svga);
return;
}
break;
case 0x3d4:
svga->crtcreg = val;
return;
case 0x3d5:
if ((svga->crtcreg < 7) && (svga->crtc[0x11] & 0x80))
return;
if ((svga->crtcreg == 7) && (svga->crtc[0x11] & 0x80))
val = (svga->crtc[7] & ~0x10) | (val & 0x10);
if ((svga->crtcreg >= 0x20) && (svga->crtcreg < 0x40) &&
(svga->crtcreg != 0x36) && (svga->crtcreg != 0x38) &&
(svga->crtcreg != 0x39) && ((svga->crtc[0x38] & 0xcc) != 0x48))
return;
if ((svga->crtcreg >= 0x40) && ((svga->crtc[0x39] & 0xe0) != 0xa0))
return;
if ((svga->crtcreg == 0x36) && (svga->crtc[0x39] != 0xa5))
return;
if (svga->crtcreg >= 0x80)
return;
old = svga->crtc[svga->crtcreg];
svga->crtc[svga->crtcreg] = val;
switch (svga->crtcreg) {
case 0x31:
virge->ma_ext = (virge->ma_ext & 0x1c) | ((val & 0x30) >> 4);
break;
case 0x32:
s3_virge_update_irqs(virge);
break;
case 0x69:
virge->ma_ext = val & 0x1f;
break;
case 0x35:
virge->bank = (virge->bank & 0x70) | (val & 0xf);
if (svga->chain4)
svga->write_bank = svga->read_bank = virge->bank << 16;
else
svga->write_bank = svga->read_bank = virge->bank << 14;
break;
case 0x51:
virge->bank = (virge->bank & 0x4f) | ((val & 0xc) << 2);
if (svga->chain4)
svga->write_bank = svga->read_bank = virge->bank << 16;
else
svga->write_bank = svga->read_bank = virge->bank << 14;
virge->ma_ext = (virge->ma_ext & ~0xc) | ((val & 3) << 2);
break;
case 0x6a:
virge->bank = val;
if (svga->chain4)
svga->write_bank = svga->read_bank = virge->bank << 16;
else
svga->write_bank = svga->read_bank = virge->bank << 14;
break;
case 0x3a:
if (val & 0x10)
svga->gdcreg[5] |= 0x40; /*Horrible cheat*/
break;
case 0x45:
svga->hwcursor.ena = val & 1;
break;
case 0x46:
case 0x47:
case 0x48:
case 0x49:
case 0x4c:
case 0x4d:
case 0x4e:
case 0x4f:
svga->hwcursor.x = ((svga->crtc[0x46] << 8) | svga->crtc[0x47]) & 0x7ff;
svga->hwcursor.y = ((svga->crtc[0x48] << 8) | svga->crtc[0x49]) & 0x7ff;
svga->hwcursor.xoff = svga->crtc[0x4e] & 0x3f;
svga->hwcursor.yoff = svga->crtc[0x4f] & 0x3f;
cursoraddr = (virge->memory_size == 8) ? 0x1fff : 0x0fff;
svga->hwcursor.addr = ((((svga->crtc[0x4c] << 8) |
svga->crtc[0x4d]) & cursoraddr) * 1024) + (svga->hwcursor.yoff * 16);
break;
case 0x4a:
switch (virge->hwc_col_stack_pos) {
case 0:
virge->hwc_fg_col = (virge->hwc_fg_col & 0xffff00) | val;
break;
case 1:
virge->hwc_fg_col = (virge->hwc_fg_col & 0xff00ff) | (val << 8);
break;
case 2:
virge->hwc_fg_col = (virge->hwc_fg_col & 0x00ffff) | (val << 16);
break;
default:
break;
}
virge->hwc_col_stack_pos = (virge->hwc_col_stack_pos + 1) & 3;
break;
case 0x4b:
switch (virge->hwc_col_stack_pos) {
case 0:
virge->hwc_bg_col = (virge->hwc_bg_col & 0xffff00) | val;
break;
case 1:
virge->hwc_bg_col = (virge->hwc_bg_col & 0xff00ff) | (val << 8);
break;
case 2:
virge->hwc_bg_col = (virge->hwc_bg_col & 0x00ffff) | (val << 16);
break;
default:
break;
}
virge->hwc_col_stack_pos = (virge->hwc_col_stack_pos + 1) & 3;
break;
case 0x53:
case 0x58:
case 0x59:
case 0x5a:
s3_virge_updatemapping(virge);
break;
case 0x56:
svga->dpms = (svga->seqregs[0x0d] & 0x50) || (svga->crtc[0x56] & 0x06);
old = ~val; /* force recalc */
break;
case 0x5c:
if ((val & 0xa0) == 0x80)
i2c_gpio_set(virge->i2c, !!(val & 0x40), !!(val & 0x10));
break;
case 0x67:
switch (val >> 4) {
case 2:
case 3:
svga->bpp = 15;
break;
case 4:
case 5:
svga->bpp = 16;
break;
case 7:
svga->bpp = 24;
break;
case 13:
svga->bpp = (virge->chip == S3_VIRGEVX) ? 24 : 32;
break;
default:
svga->bpp = 8;
break;
}
break;
case 0xaa:
i2c_gpio_set(virge->i2c, !!(val & SERIAL_PORT_SCW), !!(val & SERIAL_PORT_SDW));
break;
default:
break;
}
if (old != val) {
if (svga->crtcreg < 0xe || svga->crtcreg > 0x10) {
if ((svga->crtcreg == 0xc) || (svga->crtcreg == 0xd)) {
svga->fullchange = 3;
svga->ma_latch = ((svga->crtc[0xc] << 8) | svga->crtc[0xd]) +
((svga->crtc[8] & 0x60) >> 5);
if ((svga->crtc[0x67] & 0xc) != 0xc)
svga->ma_latch |= (virge->ma_ext << 16);
} else {
svga->fullchange = changeframecount;
svga_recalctimings(svga);
}
}
}
break;
default:
break;
}
svga_out(addr, val, svga);
}
static uint8_t
s3_virge_in(uint16_t addr, void *priv) {
virge_t *virge = (virge_t *) priv;
svga_t * svga = &virge->svga;
uint8_t ret;
if (((addr & 0xfff0) == 0x3d0 || (addr & 0xfff0) == 0x3b0) && !(svga->miscout & 1))
addr ^= 0x60;
switch (addr) {
case 0x3c1:
if (svga->attraddr > 0x14)
ret = 0xff;
else
ret = svga_in(addr, svga);
break;
case 0x3c5:
if (svga->seqaddr >= 8)
ret = svga->seqregs[svga->seqaddr & 0x1f];
else if (svga->seqaddr <= 4)
ret = svga_in(addr, svga);
else
ret = 0xff;
break;
case 0x3d4:
ret = svga->crtcreg;
break;
case 0x3d5:
switch (svga->crtcreg) {
case 0x2d:
ret = virge->virge_id_high;
break; /*Extended chip ID*/
case 0x2e:
ret = virge->virge_id_low;
break; /*New chip ID*/
case 0x2f:
ret = virge->virge_rev;
break;
case 0x30:
ret = virge->virge_id;
break; /*Chip ID*/
case 0x31:
ret = (svga->crtc[0x31] & 0xcf) | ((virge->ma_ext & 3) << 4);
break;
case 0x33:
ret = (svga->crtc[0x33] | 0x04);
break;
case 0x35:
ret = (svga->crtc[0x35] & 0xf0) | (virge->bank & 0xf);
break;
case 0x45:
virge->hwc_col_stack_pos = 0;
ret = svga->crtc[0x45];
break;
case 0x51:
ret = (svga->crtc[0x51] & 0xf0) | ((virge->bank >> 2) & 0xc) | ((virge->ma_ext >> 2) & 3);
break;
case 0x5c: /* General Output Port Register */
ret = svga->crtc[svga->crtcreg] & 0xa0;
if (((svga->miscout >> 2) & 3) == 3)
ret |= svga->crtc[0x42] & 0x0f;
else
ret |= ((svga->miscout >> 2) & 3);
if ((ret & 0xa0) == 0xa0) {
if ((svga->crtc[0x5c] & 0x40) && i2c_gpio_get_scl(virge->i2c))
ret |= 0x40;
if ((svga->crtc[0x5c] & 0x10) && i2c_gpio_get_sda(virge->i2c))
ret |= 0x10;
}
break;
case 0x69:
ret = virge->ma_ext;
break;
case 0x6a:
ret = virge->bank;
break;
case 0xaa: /* DDC */
if (virge->chip >= S3_VIRGEGX2) {
ret = svga->crtc[0xaa] & ~(SERIAL_PORT_SCR | SERIAL_PORT_SDR);
if ((svga->crtc[0xaa] & SERIAL_PORT_SCW) && i2c_gpio_get_scl(virge->i2c))
ret |= SERIAL_PORT_SCR;
if ((svga->crtc[0xaa] & SERIAL_PORT_SDW) && i2c_gpio_get_sda(virge->i2c))
ret |= SERIAL_PORT_SDR;
break;
} else
ret = svga->crtc[0xaa];
break;
default:
ret = svga->crtc[svga->crtcreg];
break;
}
break;
default:
ret = svga_in(addr, svga);
break;
}
return ret;
}
static void
s3_virge_recalctimings(svga_t *svga)
{
virge_t *virge = (virge_t *) svga->priv;
svga->hdisp = svga->hdisp_old;
if (!svga->scrblank && svga->attr_palette_enable && (svga->crtc[0x43] & 0x80)) {
/* TODO: In case of bug reports, disable 9-dots-wide character clocks in graphics modes. */
svga->dots_per_clock = ((svga->seqregs[1] & 1) ? 16 : 18);
}
if ((svga->crtc[0x33] & 0x20) || ((svga->crtc[0x67] & 0xc) == 0xc)) {
/* In this mode, the dots per clock are always 8 or 16, never 9 or 18. */
if (!svga->scrblank && svga->attr_palette_enable)
svga->dots_per_clock = (svga->seqregs[1] & 8) ? 16 : 8;
}
if (svga->crtc[0x5d] & 0x01)
svga->htotal |= 0x100;
if (svga->crtc[0x5d] & 0x02) {
svga->hdisp_time |= 0x100;
svga->hdisp |= (0x100 * svga->dots_per_clock);
}
if (svga->crtc[0x5e] & 0x01)
svga->vtotal |= 0x400;
if (svga->crtc[0x5e] & 0x02)
svga->dispend |= 0x400;
if (svga->crtc[0x5e] & 0x04)
svga->vblankstart |= 0x400;
if (svga->crtc[0x5e] & 0x10)
svga->vsyncstart |= 0x400;
if (svga->crtc[0x5e] & 0x40)
svga->split |= 0x400;
svga->interlace = svga->crtc[0x42] & 0x20;
if (((svga->miscout >> 2) & 3) == 3) {
int n = svga->seqregs[0x12] & 0x1f;
int r = (svga->seqregs[0x12] >> 5);
if ((virge->chip == S3_VIRGEVX) || (virge->chip == S3_VIRGEDX))
r &= 7;
else if (virge->chip >= S3_VIRGEGX2)
r &= 10;
else
r &= 3;
int m = svga->seqregs[0x13] & 0x7f;
double freq = (((double) m + 2) / (((double) n + 2) * (double) (1 << r))) * 14318184.0;
svga->clock = (cpuclock * (float) (1ULL << 32)) / freq;
}
if ((svga->crtc[0x33] & 0x20) || ((svga->crtc[0x67] & 0xc) == 0xc)) {
/* The S3 version of the Cirrus' special blanking mode, with identical behavior. */
svga->hblankstart = (((svga->crtc[0x5d] & 0x02) >> 1) << 8) + svga->crtc[1]/* +
((svga->crtc[3] >> 5) & 3) + 1*/;
svga->hblank_end_val = svga->htotal - 1 /* + ((svga->crtc[3] >> 5) & 3)*/;
svga->monitor->mon_overscan_y = 0;
svga->monitor->mon_overscan_x = 0;
/* Also make sure vertical blanking starts on display end. */
svga->vblankstart = svga->dispend;
video_force_resize_set_monitor(1, svga->monitor_index);
} else {
svga->hblankstart = (((svga->crtc[0x5d] & 0x04) >> 2) << 8) + svga->crtc[2];
svga->hblank_end_val = (svga->crtc[3] & 0x1f) | (((svga->crtc[5] & 0x80) >> 7) << 5) |
(((svga->crtc[0x5d] & 0x08) >> 3) << 6);
svga->hblank_end_mask = 0x7f;
video_force_resize_set_monitor(1, svga->monitor_index);
}
if (((svga->crtc[0x67] & 0xc) != 0xc) || (virge->chip >= S3_VIRGEGX2)) { /*VGA mode*/
svga->ma_latch |= (virge->ma_ext << 16);
if (svga->crtc[0x51] & 0x30)
svga->rowoffset |= (svga->crtc[0x51] & 0x30) << 4;
else if (svga->crtc[0x43] & 0x04)
svga->rowoffset |= 0x100;
if (!svga->rowoffset)
svga->rowoffset = 256;
svga->lowres = !((svga->gdcreg[5] & 0x40) && (svga->crtc[0x3a] & 0x10));
if ((svga->gdcreg[5] & 0x40) && (svga->crtc[0x3a] & 0x10)) switch (svga->bpp) {
case 8:
svga->render = svga_render_8bpp_highres;
break;
case 15:
svga->render = svga_render_15bpp_highres;
if ((virge->chip != S3_VIRGEVX) && (virge->chip < S3_VIRGEGX2)) {
svga->hdisp >>= 1;
svga->dots_per_clock >>= 1;
}
break;
case 16:
svga->render = svga_render_16bpp_highres;
if ((virge->chip != S3_VIRGEVX) && (virge->chip < S3_VIRGEGX2)) {
svga->hdisp >>= 1;
svga->dots_per_clock >>= 1;
}
break;
case 24:
svga->render = svga_render_24bpp_highres;
if ((virge->chip != S3_VIRGEVX) && (virge->chip < S3_VIRGEGX2))
svga->rowoffset = (svga->rowoffset * 3) / 4; /*Hack*/
break;
case 32:
svga->render = svga_render_32bpp_highres;
break;
default:
break;
}
svga->vram_display_mask = (!(svga->crtc[0x31] & 0x08) &&
(svga->crtc[0x32] & 0x40)) ? 0x3ffff : virge->vram_mask;
svga->overlay.ena = 0;
if (virge->chip >= S3_VIRGEGX2 && (svga->crtc[0x67] & 0xc) == 0xc) {
/* ViRGE/GX2 and later does not use primary stream registers. */
svga->overlay.x = virge->streams.sec_x;
svga->overlay.y = virge->streams.sec_y;
svga->overlay.cur_ysize = virge->streams.sec_h;
if (virge->streams.buffer_ctrl & 2)
svga->overlay.addr = virge->streams.sec_fb1;
else
svga->overlay.addr = virge->streams.sec_fb0;
svga->overlay.ena = (svga->overlay.x >= 0) && !!(virge->streams.blend_ctrl & 0x20);
svga->overlay.v_acc = virge->streams.dda_vert_accumulator;
svga->rowoffset = virge->streams.pri_stride >> 3;
svga->vram_display_mask = virge->vram_mask;
}
} else { /*Streams mode*/
if (virge->streams.buffer_ctrl & 1)
svga->ma_latch = virge->streams.pri_fb1 >> 2;
else
svga->ma_latch = virge->streams.pri_fb0 >> 2;
svga->hdisp = virge->streams.pri_w + 1;
if (virge->streams.pri_h < svga->dispend)
svga->dispend = virge->streams.pri_h;
svga->overlay.x = virge->streams.sec_x - virge->streams.pri_x;
svga->overlay.y = virge->streams.sec_y - virge->streams.pri_y;
svga->overlay.cur_ysize = virge->streams.sec_h;
if (virge->streams.buffer_ctrl & 2)
svga->overlay.addr = virge->streams.sec_fb1;
else
svga->overlay.addr = virge->streams.sec_fb0;
svga->overlay.ena = (svga->overlay.x >= 0);
svga->overlay.v_acc = virge->streams.dda_vert_accumulator;
svga->rowoffset = virge->streams.pri_stride >> 3;
if (virge->chip <= S3_VIRGEDX && svga->overlay.ena) {
svga->overlay.ena = (((virge->streams.blend_ctrl >> 24) & 7) == 0b000) ||
(((virge->streams.blend_ctrl >> 24) & 7) == 0b101);
} else if (virge->chip == S3_VIRGEGX2 && svga->overlay.ena) {
/* 0x20 = Secondary Stream enabled */
/* 0x2000 = Primary Stream enabled */
svga->overlay.ena = !!(virge->streams.blend_ctrl & 0x20);
}
switch ((virge->streams.pri_ctrl >> 24) & 0x7) {
case 0: /*RGB-8 (CLUT)*/
svga->render = svga_render_8bpp_highres;
break;
case 3: /*KRGB-16 (1.5.5.5)*/
svga->render = svga_render_15bpp_highres;
break;
case 5: /*RGB-16 (5.6.5)*/
svga->render = svga_render_16bpp_highres;
break;
case 6: /*RGB-24 (8.8.8)*/
svga->render = svga_render_24bpp_highres;
break;
case 7: /*XRGB-32 (X.8.8.8)*/
svga->render = svga_render_32bpp_highres;
break;
}
svga->vram_display_mask = virge->vram_mask;
}
svga->hoverride = 1;
if (svga->render == svga_render_2bpp_lowres)
svga->render = svga_render_2bpp_s3_lowres;
else if (svga->render == svga_render_2bpp_highres)
svga->render = svga_render_2bpp_s3_highres;
}
static void
s3_virge_update_buffer(virge_t *virge)
{
svga_t *svga = &virge->svga;
if ((svga->crtc[0x67] & 0xc) != 0xc)
return;
if (virge->chip < S3_VIRGEGX2) {
if (virge->streams.buffer_ctrl & 1)
svga->ma_latch = virge->streams.pri_fb1 >> 2;
else
svga->ma_latch = virge->streams.pri_fb0 >> 2;
}
if (virge->streams.buffer_ctrl & 2)
svga->overlay.addr = virge->streams.sec_fb1;
else
svga->overlay.addr = virge->streams.sec_fb0;
svga->rowoffset = virge->streams.pri_stride >> 3;
}
static void
s3_virge_updatemapping(virge_t *virge) {
svga_t *svga = &virge->svga;
if (!(virge->pci_regs[PCI_REG_COMMAND] & PCI_COMMAND_MEM)) {
mem_mapping_disable(&svga->mapping);
mem_mapping_disable(&virge->linear_mapping);
mem_mapping_disable(&virge->mmio_mapping);
mem_mapping_disable(&virge->new_mmio_mapping);
return;
}
switch (svga->gdcreg[6] & 0xc) { /*Banked framebuffer*/
case 0x0: /*128k at A0000*/
mem_mapping_set_addr(&svga->mapping, 0xa0000, 0x20000);
svga->banked_mask = 0xffff;
break;
case 0x4: /*64k at A0000*/
mem_mapping_set_addr(&svga->mapping, 0xa0000, 0x10000);
svga->banked_mask = 0xffff;
break;
case 0x8: /*32k at B0000*/
mem_mapping_set_addr(&svga->mapping, 0xb0000, 0x08000);
svga->banked_mask = 0x7fff;
break;
case 0xC: /*32k at B8000*/
mem_mapping_set_addr(&svga->mapping, 0xb8000, 0x08000);
svga->banked_mask = 0x7fff;
break;
}
virge->linear_base = (svga->crtc[0x5a] << 16) | (svga->crtc[0x59] << 24);
if ((svga->crtc[0x58] & 0x10) || (virge->advfunc_cntl & 0x10)) { /*Linear framebuffer*/
switch (svga->crtc[0x58] & 7) {
case 0: /*64k*/
virge->linear_size = 0x10000;
break;
case 1: /*1mb*/
virge->linear_size = 0x100000;
break;
case 2: /*2mb*/
virge->linear_size = 0x200000;
break;
case 3: /*4mb on other than ViRGE/VX, 8mb on ViRGE/VX*/
if ((virge->chip == S3_VIRGEVX) || (virge->chip == S3_TRIO3D2X))
virge->linear_size = 0x800000;
else
virge->linear_size = 0x400000;
break;
case 7:
virge->linear_size = 0x800000;
break;
}
virge->linear_base &= ~(virge->linear_size - 1);
if (virge->linear_base == 0xa0000) {
mem_mapping_set_addr(&svga->mapping, 0xa0000, 0x10000);
mem_mapping_disable(&virge->linear_mapping);
} else {
if ((virge->chip == S3_VIRGEVX) || (virge->chip == S3_TRIO3D2X))
virge->linear_base &= 0xfe000000;
else
virge->linear_base &= 0xfc000000;
mem_mapping_set_addr(&virge->linear_mapping, virge->linear_base, virge->linear_size);
}
svga->fb_only = 1;
} else {
mem_mapping_disable(&virge->linear_mapping);
svga->fb_only = 0;
}
if ((svga->crtc[0x53] & 0x10) || (virge->advfunc_cntl & 0x20)) { /*Old MMIO*/
if (svga->crtc[0x53] & 0x20)
mem_mapping_set_addr(&virge->mmio_mapping, 0xb8000, 0x8000);
else
mem_mapping_set_addr(&virge->mmio_mapping, 0xa0000, 0x10000);
} else
mem_mapping_disable(&virge->mmio_mapping);
if (svga->crtc[0x53] & 0x08) /*New MMIO*/
mem_mapping_set_addr(&virge->new_mmio_mapping, virge->linear_base + 0x1000000, 0x10000);
else
mem_mapping_disable(&virge->new_mmio_mapping);
}
static void
s3_virge_vblank_start(svga_t *svga) {
virge_t *virge = (virge_t *) svga->priv;
virge->subsys_stat |= INT_VSY;
s3_virge_update_irqs(virge);
}
static void
s3_virge_wait_fifo_idle(virge_t *virge) {
while (!FIFO_EMPTY) {
wake_fifo_thread(virge);
thread_wait_event(virge->fifo_not_full_event, 1);
}
}
static uint8_t
s3_virge_mmio_read(uint32_t addr, void *priv)
{
virge_t *virge = (virge_t *) priv;
uint8_t ret;
switch (addr & 0xffff) {
case 0x8504:
if (!virge->virge_busy)
wake_fifo_thread(virge);
ret = virge->subsys_stat;
return ret;
case 0x8505:
ret = 0xc0;
if (virge->s3d_busy || virge->virge_busy || !FIFO_EMPTY)
ret |= 0x10;
else
ret |= 0x30;
if (!virge->virge_busy)
wake_fifo_thread(virge);
return ret;
case 0x850c:
ret = virge->advfunc_cntl & 0x3f;
ret |= virge->fifo_slots_num << 6;
ret &= 0xff;
return ret;
case 0x850d:
ret = virge->fifo_slots_num >> 2;
return ret;
case 0x83b0 ... 0x83df:
return s3_virge_in(addr & 0x3ff, priv);
case 0x859c:
return virge->cmd_dma;
case 0xff20:
case 0xff21:
ret = virge->serialport & ~(SERIAL_PORT_SCR | SERIAL_PORT_SDR);
if ((virge->serialport & SERIAL_PORT_SCW) && i2c_gpio_get_scl(virge->i2c))
ret |= SERIAL_PORT_SCR;
if ((virge->serialport & SERIAL_PORT_SDW) && i2c_gpio_get_sda(virge->i2c))
ret |= SERIAL_PORT_SDR;
return ret;
}
return 0xff;
}
static uint16_t
s3_virge_mmio_read_w(uint32_t addr, void *priv)
{
virge_t *virge = (virge_t *) priv;
uint16_t ret;
switch (addr & 0xfffe) {
case 0x8504:
ret = 0xc000;
if (virge->s3d_busy || virge->virge_busy || !FIFO_EMPTY)
ret |= 0x1000;
else
ret |= 0x3000;
ret |= virge->subsys_stat;
if (!virge->virge_busy)
wake_fifo_thread(virge);
return ret;
case 0x850c:
ret = virge->advfunc_cntl & 0x3f;
ret |= virge->fifo_slots_num << 6;
return ret;
case 0x859c:
return virge->cmd_dma;
default:
return s3_virge_mmio_read(addr, priv) | (s3_virge_mmio_read(addr + 1, priv) << 8);
}
return 0xffff;
}
static uint32_t
s3_virge_mmio_read_l(uint32_t addr, void *priv) {
virge_t *virge = (virge_t *) priv;
uint32_t ret = 0xffffffff;
switch (addr & 0xfffc) {
case 0x8180:
ret = virge->streams.pri_ctrl;
break;
case 0x8184:
ret = virge->streams.chroma_ctrl;
break;
case 0x8190:
ret = virge->streams.sec_ctrl;
break;
case 0x8194:
ret = virge->streams.chroma_upper_bound;
break;
case 0x8198:
ret = virge->streams.sec_filter;
break;
case 0x81a0:
ret = virge->streams.blend_ctrl;
break;
case 0x81c0:
ret = virge->streams.pri_fb0;
break;
case 0x81c4:
ret = virge->streams.pri_fb1;
break;
case 0x81c8:
ret = virge->streams.pri_stride;
break;
case 0x81cc:
ret = virge->streams.buffer_ctrl;
break;
case 0x81d0:
ret = virge->streams.sec_fb0;
break;
case 0x81d4:
ret = virge->streams.sec_fb1;
break;
case 0x81d8:
ret = virge->streams.sec_stride;
break;
case 0x81dc:
ret = virge->streams.overlay_ctrl;
break;
case 0x81e0:
ret = virge->streams.k1_vert_scale;
break;
case 0x81e4:
ret = virge->streams.k2_vert_scale;
break;
case 0x81e8:
ret = virge->streams.dda_vert_accumulator;
break;
case 0x81ec:
ret = virge->streams.fifo_ctrl;
break;
case 0x81f0:
ret = virge->streams.pri_start;
break;
case 0x81f4:
ret = virge->streams.pri_size;
break;
case 0x81f8:
ret = virge->streams.sec_start;
break;
case 0x81fc:
ret = virge->streams.sec_size;
break;
case 0x8504:
ret = 0x0000c000;
if (virge->s3d_busy || virge->virge_busy || !FIFO_EMPTY)
ret |= 0x00001000;
else
ret |= 0x00003000;
ret |= virge->subsys_stat;
if (!virge->virge_busy)
wake_fifo_thread(virge);
break;
case 0x850c:
ret = virge->advfunc_cntl & 0x3f;
ret |= virge->fifo_slots_num << 6;
break;
case 0x8590:
ret = virge->cmd_dma_base;
break;
case 0x8594:
ret = virge->cmd_dma_write_ptr_reg;
break;
case 0x8598:
ret = virge->cmd_dma_read_ptr_reg;
if (ret > virge->cmd_dma_write_ptr_reg)
ret = virge->cmd_dma_write_ptr_reg;
break;
case 0x859c:
ret = 0; /*To prevent DMA overflows.*/
break;
case 0xa4d4:
case 0xa8d4:
case 0xacd4:
s3_virge_wait_fifo_idle(virge);
ret = virge->s3d.src_base;
break;
case 0xa4d8:
case 0xa8d8:
case 0xacd8:
s3_virge_wait_fifo_idle(virge);
ret = virge->s3d.dest_base;
break;
case 0xa4dc:
case 0xa8dc:
case 0xacdc:
s3_virge_wait_fifo_idle(virge);
ret = (virge->s3d.clip_l << 16) | virge->s3d.clip_r;
break;
case 0xa4e0:
case 0xa8e0:
case 0xace0:
s3_virge_wait_fifo_idle(virge);
ret = (virge->s3d.clip_t << 16) | virge->s3d.clip_b;
break;
case 0xa4e4:
case 0xa8e4:
case 0xace4:
s3_virge_wait_fifo_idle(virge);
ret = (virge->s3d.dest_str << 16) | virge->s3d.src_str;
break;
case 0xa4e8:
case 0xace8:
s3_virge_wait_fifo_idle(virge);
ret = virge->s3d.mono_pat_0;
break;
case 0xa4ec:
case 0xacec:
s3_virge_wait_fifo_idle(virge);
ret = virge->s3d.mono_pat_1;
break;
case 0xa4f0:
case 0xacf0:
s3_virge_wait_fifo_idle(virge);
ret = virge->s3d.pat_bg_clr;
break;
case 0xa4f4:
case 0xa8f4:
case 0xacf4:
s3_virge_wait_fifo_idle(virge);
ret = virge->s3d.pat_fg_clr;
break;
case 0xa4f8:
s3_virge_wait_fifo_idle(virge);
ret = virge->s3d.src_bg_clr;
break;
case 0xa4fc:
s3_virge_wait_fifo_idle(virge);
ret = virge->s3d.src_fg_clr;
break;
case 0xa500:
case 0xa900:
case 0xad00:
s3_virge_wait_fifo_idle(virge);
ret = virge->s3d.cmd_set;
break;
case 0xa504:
s3_virge_wait_fifo_idle(virge);
ret = (virge->s3d.r_width << 16) | virge->s3d.r_height;
break;
case 0xa508:
s3_virge_wait_fifo_idle(virge);
ret = (virge->s3d.rsrc_x << 16) | virge->s3d.rsrc_y;
break;
case 0xa50c:
s3_virge_wait_fifo_idle(virge);
ret = (virge->s3d.rdest_x << 16) | virge->s3d.rdest_y;
break;
case 0xa96c:
s3_virge_wait_fifo_idle(virge);
ret = (virge->s3d.lxend0 << 16) | virge->s3d.lxend1;
break;
case 0xa970:
s3_virge_wait_fifo_idle(virge);
ret = virge->s3d.ldx;
break;
case 0xa974:
s3_virge_wait_fifo_idle(virge);
ret = virge->s3d.lxstart;
break;
case 0xa978:
s3_virge_wait_fifo_idle(virge);
ret = virge->s3d.lystart;
break;
case 0xa97c:
s3_virge_wait_fifo_idle(virge);
ret = (virge->s3d.line_dir << 31) | virge->s3d.lycnt;
break;
case 0xad68:
s3_virge_wait_fifo_idle(virge);
ret = virge->s3d.prdx;
break;
case 0xad6c:
s3_virge_wait_fifo_idle(virge);
ret = virge->s3d.prxstart;
break;
case 0xad70:
s3_virge_wait_fifo_idle(virge);
ret = virge->s3d.pldx;
break;
case 0xad74:
s3_virge_wait_fifo_idle(virge);
ret = virge->s3d.plxstart;
break;
case 0xad78:
s3_virge_wait_fifo_idle(virge);
ret = virge->s3d.pystart;
break;
case 0xad7c:
s3_virge_wait_fifo_idle(virge);
ret = virge->s3d.pycnt;
break;
default:
ret = s3_virge_mmio_read_w(addr, priv) | (s3_virge_mmio_read_w(addr + 2, priv) << 16);
break;
}
//pclog("MMIO ReadL=%04x, ret=%08x.\n", addr & 0xfffc, ret);
return ret;
}
static void
s3_virge_mmio_write_fifo_l(virge_t *virge, uint32_t addr, uint32_t val)
{
switch (addr) {
case 0xa000 ... 0xa1fc:
{
int x = addr & 4;
int y = (addr >> 3) & 7;
int color;
int byte;
uint32_t newaddr = addr;
virge->s3d.pattern_8[y * 8 + x] = val & 0xff;
virge->s3d.pattern_8[y * 8 + x + 1] = val >> 8;
virge->s3d.pattern_8[y * 8 + x + 2] = val >> 16;
virge->s3d.pattern_8[y * 8 + x + 3] = val >> 24;
x = (addr >> 1) & 6;
y = (addr >> 4) & 7;
virge->s3d.pattern_16[y * 8 + x] = val & 0xffff;
virge->s3d.pattern_16[y * 8 + x + 1] = val >> 16;
newaddr &= 0x00ff;
for (uint8_t xx = 0; xx < 4; xx++) {
x = ((newaddr + xx) / 3) % 8;
y = ((newaddr + xx) / 24) % 8;
color = ((newaddr + xx) % 3) << 3;
byte = (xx << 3);
virge->s3d.pattern_24[y * 8 + x] &= ~(0xff << color);
virge->s3d.pattern_24[y * 8 + x] |= ((val >> byte) & 0xff) << color;
}
x = (addr >> 2) & 7;
y = (addr >> 5) & 7;
virge->s3d.pattern_32[y * 8 + x] = val & 0xffffff;
} break;
case 0xa4d4:
case 0xa8d4:
case 0xacd4:
virge->s3d.src_base = val & ((virge->memory_size == 8) ?
(val & 0x7ffff8) : (val & 0x3ffff8));
break;
case 0xa4d8:
case 0xa8d8:
case 0xacd8:
virge->s3d.dest_base = val & ((virge->memory_size == 8) ?
(val & 0x7ffff8) : (val & 0x3ffff8));
break;
case 0xa4dc:
case 0xa8dc:
case 0xacdc:
virge->s3d.clip_l = (val >> 16) & 0x7ff;
virge->s3d.clip_r = val & 0x7ff;
break;
case 0xa4e0:
case 0xa8e0:
case 0xace0:
virge->s3d.clip_t = (val >> 16) & 0x7ff;
virge->s3d.clip_b = val & 0x7ff;
break;
case 0xa4e4:
case 0xa8e4:
case 0xace4:
virge->s3d.dest_str = (val >> 16) & 0xff8;
virge->s3d.src_str = val & 0xff8;
break;
case 0xa4e8:
case 0xace8:
virge->s3d.mono_pat_0 = val;
break;
case 0xa4ec:
case 0xacec:
virge->s3d.mono_pat_1 = val;
break;
case 0xa4f0:
case 0xacf0:
virge->s3d.pat_bg_clr = val;
break;
case 0xa4f4:
case 0xa8f4:
case 0xacf4:
virge->s3d.pat_fg_clr = val;
break;
case 0xa4f8:
virge->s3d.src_bg_clr = val;
break;
case 0xa4fc:
virge->s3d.src_fg_clr = val;
break;
case 0xa500:
case 0xa900:
case 0xad00:
virge->s3d.cmd_set = val;
if (!(val & CMD_SET_AE))
s3_virge_bitblt(virge, -1, 0);
break;
case 0xa504:
virge->s3d.r_width = (val >> 16) & 0x7ff;
virge->s3d.r_height = val & 0x7ff;
break;
case 0xa508:
virge->s3d.rsrc_x = (val >> 16) & 0x7ff;
virge->s3d.rsrc_y = val & 0x7ff;
break;
case 0xa50c:
virge->s3d.rdest_x = (val >> 16) & 0x7ff;
virge->s3d.rdest_y = val & 0x7ff;
if (virge->s3d.cmd_set & CMD_SET_AE)
s3_virge_bitblt(virge, -1, 0);
break;
case 0xa96c:
virge->s3d.lxend0 = (val >> 16) & 0x7ff;
virge->s3d.lxend1 = val & 0x7ff;
break;
case 0xa970:
virge->s3d.ldx = (int32_t)val;
break;
case 0xa974:
virge->s3d.lxstart = val;
break;
case 0xa978:
virge->s3d.lystart = val & 0x7ff;
break;
case 0xa97c:
virge->s3d.lycnt = val & 0x7ff;
virge->s3d.line_dir = val >> 31;
if (virge->s3d.cmd_set & CMD_SET_AE)
s3_virge_bitblt(virge, -1, 0);
break;
case 0xad68:
virge->s3d.prdx = val;
break;
case 0xad6c:
virge->s3d.prxstart = val;
break;
case 0xad70:
virge->s3d.pldx = val;
break;
case 0xad74:
virge->s3d.plxstart = val;
break;
case 0xad78:
virge->s3d.pystart = val & 0x7ff;
break;
case 0xad7c:
virge->s3d.pycnt = val & 0x300007ff;
if (virge->s3d.cmd_set & CMD_SET_AE)
s3_virge_bitblt(virge, -1, 0);
break;
case 0xb0d4:
case 0xb4d4:
virge->s3d_tri.z_base = val & ((virge->memory_size == 8) ?
(val & 0x7ffff8) : (val & 0x3ffff8));
break;
case 0xb0d8:
case 0xb4d8:
virge->s3d_tri.dest_base = val & ((virge->memory_size == 8) ?
(val & 0x7ffff8) : (val & 0x3ffff8));
break;
case 0xb0dc:
case 0xb4dc:
virge->s3d_tri.clip_l = (val >> 16) & 0x7ff;
virge->s3d_tri.clip_r = val & 0x7ff;
break;
case 0xb0e0:
case 0xb4e0:
virge->s3d_tri.clip_t = (val >> 16) & 0x7ff;
virge->s3d_tri.clip_b = val & 0x7ff;
break;
case 0xb0e4:
case 0xb4e4:
virge->s3d_tri.dest_str = (val >> 16) & 0xff8;
virge->s3d.src_str = val & 0xff8;
break;
case 0xb0e8:
case 0xb4e8:
virge->s3d_tri.z_str = val & 0xff8;
break;
case 0xb4ec:
virge->s3d_tri.tex_base = val & ((virge->memory_size == 8) ?
(val & 0x7ffff8) : (val & 0x3ffff8));
break;
case 0xb4f0:
virge->s3d_tri.tex_bdr_clr = val & 0xffffff;
break;
case 0xb0f4:
case 0xb4f4:
virge->s3d_tri.fog_b = val & 0xff;
virge->s3d_tri.fog_g = (val >> 8) & 0xff;
virge->s3d_tri.fog_r = (val >> 16) & 0xff;
break;
case 0xb100:
case 0xb500:
virge->s3d_tri.cmd_set = val;
if (!(val & CMD_SET_AE))
queue_triangle(virge);
break;
case 0xb504:
virge->s3d_tri.tbv = val & 0xfffff;
break;
case 0xb508:
virge->s3d_tri.tbu = val & 0xfffff;
break;
case 0xb50c:
virge->s3d_tri.TdWdX = val;
break;
case 0xb510:
virge->s3d_tri.TdWdY = val;
break;
case 0xb514:
virge->s3d_tri.tws = val;
break;
case 0xb518:
virge->s3d_tri.TdDdX = val;
break;
case 0xb51c:
virge->s3d_tri.TdVdX = val;
break;
case 0xb520:
virge->s3d_tri.TdUdX = val;
break;
case 0xb524:
virge->s3d_tri.TdDdY = val;
break;
case 0xb528:
virge->s3d_tri.TdVdY = val;
break;
case 0xb52c:
virge->s3d_tri.TdUdY = val;
break;
case 0xb530:
virge->s3d_tri.tds = val;
break;
case 0xb534:
virge->s3d_tri.tvs = val;
break;
case 0xb538:
virge->s3d_tri.tus = val;
break;
case 0xb53c:
virge->s3d_tri.TdGdX = val >> 16;
virge->s3d_tri.TdBdX = val & 0xffff;
break;
case 0xb540:
virge->s3d_tri.TdAdX = val >> 16;
virge->s3d_tri.TdRdX = val & 0xffff;
break;
case 0xb544:
virge->s3d_tri.TdGdY = val >> 16;
virge->s3d_tri.TdBdY = val & 0xffff;
break;
case 0xb548:
virge->s3d_tri.TdAdY = val >> 16;
virge->s3d_tri.TdRdY = val & 0xffff;
break;
case 0xb54c:
virge->s3d_tri.tgs = (val >> 16) & 0xffff;
virge->s3d_tri.tbs = val & 0xffff;
break;
case 0xb550:
virge->s3d_tri.tas = (val >> 16) & 0xffff;
virge->s3d_tri.trs = val & 0xffff;
break;
case 0xb554:
virge->s3d_tri.TdZdX = val;
break;
case 0xb558:
virge->s3d_tri.TdZdY = val;
break;
case 0xb55c:
virge->s3d_tri.tzs = val;
break;
case 0xb560:
virge->s3d_tri.TdXdY12 = val;
break;
case 0xb564:
virge->s3d_tri.txend12 = val;
break;
case 0xb568:
virge->s3d_tri.TdXdY01 = val;
break;
case 0xb56c:
virge->s3d_tri.txend01 = val;
break;
case 0xb570:
virge->s3d_tri.TdXdY02 = val;
break;
case 0xb574:
virge->s3d_tri.txs = val;
break;
case 0xb578:
virge->s3d_tri.tys = val;
break;
case 0xb57c:
virge->s3d_tri.ty01 = (val >> 16) & 0x7ff;
virge->s3d_tri.ty12 = val & 0x7ff;
virge->s3d_tri.tlr = val >> 31;
if (virge->s3d_tri.cmd_set & CMD_SET_AE)
queue_triangle(virge);
break;
}
}
static void
fifo_thread(void *param)
{
virge_t *virge = (virge_t *)param;
while (virge->fifo_thread_run) {
thread_set_event(virge->fifo_not_full_event);
thread_wait_event(virge->wake_fifo_thread, -1);
thread_reset_event(virge->wake_fifo_thread);
virge->virge_busy = 1;
while (!FIFO_EMPTY) {
uint64_t start_time = plat_timer_read();
uint64_t end_time;
fifo_entry_t *fifo = &virge->fifo[virge->fifo_read_idx & FIFO_MASK];
uint32_t val = fifo->val;
switch (fifo->addr_type & FIFO_TYPE) {
case FIFO_WRITE_BYTE:
if (((fifo->addr_type & FIFO_ADDR) & 0xffff) < 0x8000)
s3_virge_bitblt(virge, 8, val);
break;
case FIFO_WRITE_WORD:
if (((fifo->addr_type & FIFO_ADDR) & 0xfffe) < 0x8000) {
if (virge->s3d.cmd_set & CMD_SET_MS)
s3_virge_bitblt(virge, 16, ((val >> 8) | (val << 8)) << 16);
else
s3_virge_bitblt(virge, 16, val);
}
break;
case FIFO_WRITE_DWORD:
if (((fifo->addr_type & FIFO_ADDR) & 0xfffc) < 0x8000) {
if (virge->s3d.cmd_set & CMD_SET_MS)
s3_virge_bitblt(virge, 32,
((val & 0xff000000) >> 24) | ((val & 0x00ff0000) >> 8) |
((val & 0x0000ff00) << 8) | ((val & 0x000000ff) << 24));
else
s3_virge_bitblt(virge, 32, val);
} else
s3_virge_mmio_write_fifo_l(virge, (fifo->addr_type & FIFO_ADDR) & 0xfffc, val);
break;
}
virge->fifo_read_idx++;
fifo->addr_type = FIFO_INVALID;
if (FIFO_ENTRIES > 0xe000)
thread_set_event(virge->fifo_not_full_event);
end_time = plat_timer_read();
virge_time += end_time - start_time;
}
virge->virge_busy = 0;
virge->subsys_stat |= INT_FIFO_EMP | INT_3DF_EMP;
if (virge->cmd_dma)
virge->subsys_stat |= INT_HOST_DONE | INT_CMD_DONE;
s3_virge_update_irqs(virge);
}
}
static void
s3_virge_queue(virge_t *virge, uint32_t addr, uint32_t val, uint32_t type)
{
fifo_entry_t *fifo = &virge->fifo[virge->fifo_write_idx & FIFO_MASK];
int limit = 0;
if (type == FIFO_WRITE_DWORD) {
switch (addr & 0xfffc) {
case 0xa500:
if (val & CMD_SET_AE)
limit = 1;
break;
default:
break;
}
}
if (limit) {
if (FIFO_ENTRIES >= 16) {
thread_reset_event(virge->fifo_not_full_event);
if (FIFO_ENTRIES >= 16)
thread_wait_event(virge->fifo_not_full_event, -1); /*Wait for room in ringbuffer*/
}
} else {
if (FIFO_FULL) {
thread_reset_event(virge->fifo_not_full_event);
if (FIFO_FULL)
thread_wait_event(virge->fifo_not_full_event, -1); /*Wait for room in ringbuffer*/
}
}
fifo->val = val;
fifo->addr_type = (addr & FIFO_ADDR) | type;
virge->fifo_write_idx++;
if (FIFO_ENTRIES > 0xe000)
wake_fifo_thread(virge);
if (FIFO_ENTRIES > 0xe000 || FIFO_ENTRIES < 8)
wake_fifo_thread(virge);
}
static void
s3_virge_mmio_write(uint32_t addr, uint8_t val, void *priv) {
virge_t *virge = (virge_t *) priv;
if ((addr & 0xffff) < 0x8000)
s3_virge_queue(virge, addr, val, FIFO_WRITE_BYTE);
else switch (addr & 0xffff) {
case 0x83b0 ... 0x83df:
s3_virge_out(addr & 0x3ff, val, priv);
break;
case 0xff20:
virge->serialport = val;
i2c_gpio_set(virge->i2c, !!(val & SERIAL_PORT_SCW), !!(val & SERIAL_PORT_SDW));
break;
}
}
static void
s3_virge_mmio_write_w(uint32_t addr, uint16_t val, void *priv) {
virge_t *virge = (virge_t *) priv;
if ((addr & 0xfffe) < 0x8000)
s3_virge_queue(virge, addr, val, FIFO_WRITE_WORD);
else switch (addr & 0xfffe) {
default:
case 0x83d4:
s3_virge_mmio_write(addr, val, priv);
s3_virge_mmio_write(addr + 1, val >> 8, priv);
break;
case 0xff20:
s3_virge_mmio_write(addr, val, priv);
break;
}
}
static void
s3_virge_mmio_write_l(uint32_t addr, uint32_t val, void *priv) {
virge_t *virge = (virge_t *) priv;
svga_t *svga = &virge->svga;
if ((addr & 0xfffc) < 0x8000)
s3_virge_queue(virge, addr, val, FIFO_WRITE_DWORD);
else if ((addr & 0xe000) == 0xa000)
s3_virge_queue(virge, addr, val, FIFO_WRITE_DWORD);
else {
switch (addr & 0xfffc) {
case 0x8180:
virge->streams.pri_ctrl = val;
svga_recalctimings(svga);
svga->fullchange = changeframecount;
break;
case 0x8184:
virge->streams.chroma_ctrl = val;
break;
case 0x8190:
virge->streams.sec_ctrl = val;
virge->streams.dda_horiz_accumulator = val & 0xfff;
if (val & (1 << 11))
virge->streams.dda_horiz_accumulator |= 0xfffff800;
virge->streams.sdif = (val >> 24) & 7;
break;
case 0x8194:
virge->streams.chroma_upper_bound = val;
break;
case 0x8198:
virge->streams.sec_filter = val;
virge->streams.k1_horiz_scale = val & 0x7ff;
if (val & (1 << 10))
virge->streams.k1_horiz_scale |= 0xfffff800;
virge->streams.k2_horiz_scale = (val >> 16) & 0x7ff;
if ((val >> 16) & (1 << 10))
virge->streams.k2_horiz_scale |= 0xfffff800;
break;
case 0x81a0:
virge->streams.blend_ctrl = val;
break;
case 0x81c0:
virge->streams.pri_fb0 = val & ((virge->memory_size == 8) ?
(val & 0x7fffff) : (val & 0x3fffff));
s3_virge_update_buffer(virge);
svga->fullchange = changeframecount;
break;
case 0x81c4:
virge->streams.pri_fb1 = ((virge->memory_size == 8) ?
(val & 0x7fffff) : (val & 0x3fffff));
s3_virge_update_buffer(virge);
svga->fullchange = changeframecount;
break;
case 0x81c8:
virge->streams.pri_stride = val & 0xfff;
s3_virge_update_buffer(virge);
svga->fullchange = changeframecount;
break;
case 0x81cc:
virge->streams.buffer_ctrl = val;
s3_virge_update_buffer(virge);
svga->fullchange = changeframecount;
break;
case 0x81d0:
virge->streams.sec_fb0 = val;
s3_virge_update_buffer(virge);
svga->fullchange = changeframecount;
break;
case 0x81d4:
virge->streams.sec_fb1 = val;
s3_virge_update_buffer(virge);
svga->fullchange = changeframecount;
break;
case 0x81d8:
virge->streams.sec_stride = val;
s3_virge_update_buffer(virge);
svga->fullchange = changeframecount;
break;
case 0x81dc:
virge->streams.overlay_ctrl = val;
break;
case 0x81e0:
virge->streams.k1_vert_scale = val & 0x7ff;
if (val & (1 << 10))
virge->streams.k1_vert_scale |= 0xfffff800;
break;
case 0x81e4:
virge->streams.k2_vert_scale = val & 0x7ff;
if (val & (1 << 10))
virge->streams.k2_vert_scale |= 0xfffff800;
break;
case 0x81e8:
virge->streams.dda_vert_accumulator = val & 0xfff;
if (val & (1 << 11))
virge->streams.dda_vert_accumulator |= 0xfffff800;
break;
case 0x81ec:
virge->streams.fifo_ctrl = val;
break;
case 0x81f0:
virge->streams.pri_start = val;
virge->streams.pri_x = (val >> 16) & 0x7ff;
virge->streams.pri_y = val & 0x7ff;
svga_recalctimings(svga);
svga->fullchange = changeframecount;
break;
case 0x81f4:
virge->streams.pri_size = val;
virge->streams.pri_w = (val >> 16) & 0x7ff;
virge->streams.pri_h = val & 0x7ff;
svga_recalctimings(svga);
svga->fullchange = changeframecount;
break;
case 0x81f8:
virge->streams.sec_start = val;
virge->streams.sec_x = (val >> 16) & 0x7ff;
virge->streams.sec_y = val & 0x7ff;
svga_recalctimings(svga);
svga->fullchange = changeframecount;
break;
case 0x81fc:
virge->streams.sec_size = val;
virge->streams.sec_w = (val >> 16) & 0x7ff;
virge->streams.sec_h = val & 0x7ff;
svga_recalctimings(svga);
svga->fullchange = changeframecount;
break;
case 0x8504:
virge->subsys_stat &= ~(val & 0xff);
virge->subsys_cntl = (val >> 8);
s3_virge_update_irqs(virge);
break;
case 0x850c:
virge->advfunc_cntl = val & 0xff;
s3_virge_updatemapping(virge);
break;
case 0x8590:
virge->cmd_dma_base = val;
virge->cmd_dma_buf_size = (val & 2) ? 0x10000 : 0x1000;
virge->cmd_dma_buf_size_mask = virge->cmd_dma_buf_size - 1;
virge->cmd_base_addr = (val & 2) ? (val & 0xffff0000) : (val & 0xfffff000);
break;
case 0x8594:
virge->cmd_dma_write_ptr_update = val & (1 << 16);
if (virge->cmd_dma_write_ptr_update) {
virge->cmd_dma_write_ptr_reg = (virge->cmd_dma_buf_size == 0x10000) ? (val & 0xffff) : (val & 0xfff);
virge->dma_dbl_words = 0;
virge->dma_data_type = 0;
virge->dma_val = 0;
if (virge->cmd_dma) {
while (virge->cmd_dma_read_ptr_reg != virge->cmd_dma_write_ptr_reg) {
virge->cmd_dma_write_ptr_update = 0;
dma_bm_read(virge->cmd_base_addr + virge->cmd_dma_read_ptr_reg, (uint8_t *)&virge->dma_val, 4, 4);
if (!virge->dma_dbl_words) {
virge->dma_dbl_words = (virge->dma_val & 0xffff);
virge->dma_data_type = !!(virge->dma_val & (1 << 31));
if (virge->dma_data_type)
virge->dma_mmio_addr = 0;
else
virge->dma_mmio_addr = ((virge->dma_val >> 16) << 2) & 0xfffc;
} else {
s3_virge_mmio_write_l(virge->dma_mmio_addr, virge->dma_val, virge);
virge->dma_dbl_words--;
virge->dma_mmio_addr = (virge->dma_mmio_addr + 4) & 0xfffc;
}
virge->cmd_dma_read_ptr_reg = (virge->cmd_dma_read_ptr_reg + 4) & (virge->cmd_dma_buf_size_mask - 3);
}
}
}
break;
case 0x8598:
virge->cmd_dma_read_ptr_reg = (virge->cmd_dma_buf_size == 0x10000) ? (val & 0xffff) : (val & 0xfff);
break;
case 0x859c:
virge->cmd_dma = val & 1;
virge->cmd_dma_write_ptr_reg = 0;
virge->cmd_dma_read_ptr_reg = 0;
break;
case 0xff20:
s3_virge_mmio_write(addr, val, priv);
break;
}
}
}
#define READ(addr, val) \
do { \
switch (bpp) { \
case 0: /*8 bpp*/ \
val = vram[addr & virge->vram_mask]; \
break; \
case 1: /*16 bpp*/ \
val = *(uint16_t *)&vram[addr & virge->vram_mask]; \
break; \
case 2: /*24 bpp*/ \
val = (*(uint32_t *)&vram[addr & virge->vram_mask]) & 0xffffff; \
break; \
} \
} while (0)
#define Z_READ(addr) *(uint16_t *)&vram[addr & virge->vram_mask]
#define Z_WRITE(addr, val) \
if (!(s3d_tri->cmd_set & CMD_SET_ZB_MODE)) \
*(uint16_t *)&vram[addr & virge->vram_mask] = val
#define CLIP(x, y) \
do { \
if ((virge->s3d.cmd_set & CMD_SET_HC) && \
(x < virge->s3d.clip_l || x > virge->s3d.clip_r || \
y < virge->s3d.clip_t || y > virge->s3d.clip_b)) \
update = 0; \
} while (0)
#define CLIP_3D(x, y) \
do { \
if ((s3d_tri->cmd_set & CMD_SET_HC) && (x < s3d_tri->clip_l || \
x > s3d_tri->clip_r || y < s3d_tri->clip_t || \
y > s3d_tri->clip_b)) \
update = 0; \
} while (0)
#define Z_CLIP(Zzb, Zs) \
do { \
if (!(s3d_tri->cmd_set & CMD_SET_ZB_MODE)) \
switch ((s3d_tri->cmd_set >> 20) & 7) { \
case 0: \
update = 0; \
break; \
case 1: \
if (Zs <= Zzb) \
update = 0; \
else \
Zzb = Zs; \
break; \
case 2: \
if (Zs != Zzb) \
update = 0; \
else \
Zzb = Zs; \
break; \
case 3: \
if (Zs < Zzb) \
update = 0; \
else \
Zzb = Zs; \
break; \
case 4: \
if (Zs >= Zzb) \
update = 0; \
else \
Zzb = Zs; \
break; \
case 5: \
if (Zs == Zzb) \
update = 0; \
else \
Zzb = Zs; \
break; \
case 6: \
if (Zs > Zzb) \
update = 0; \
else \
Zzb = Zs; \
break; \
case 7: \
update = 1; \
Zzb = Zs; \
break; \
} \
} while (0)
#define MIX() \
do { \
int c; \
for (c = 0; c < 24; c++) { \
int d = (dest & (1 << c)) ? 1 : 0; \
if (source & (1 << c)) \
d |= 2; \
if (pattern & (1 << c)) \
d |= 4; \
if (virge->s3d.rop & (1 << d)) \
out |= (1 << c); \
} \
} while (0)
#define WRITE(addr, val) \
do { \
switch (bpp) { \
case 0: /*8 bpp*/ \
vram[addr & virge->vram_mask] = val; \
virge->svga.changedvram[(addr & virge->vram_mask) >> 12] = \
changeframecount; \
break; \
case 1: /*16 bpp*/ \
*(uint16_t *)&vram[addr & virge->vram_mask] = val; \
virge->svga.changedvram[(addr & virge->vram_mask) >> 12] = \
changeframecount; \
break; \
case 2: /*24 bpp*/ \
*(uint32_t *)&vram[addr & virge->vram_mask] = (val & 0xffffff) |\
(vram[(addr + 3) & virge->vram_mask] << 24); \
virge->svga.changedvram[(addr & virge->vram_mask) >> 12] = \
changeframecount; \
break; \
} \
} while (0)
static void
s3_virge_bitblt(virge_t *virge, int count, uint32_t cpu_dat) {
uint8_t *vram = virge->svga.vram;
uint32_t mono_pattern[64];
int count_mask;
int x_inc = (virge->s3d.cmd_set & CMD_SET_XP) ? 1 : -1;
int y_inc = (virge->s3d.cmd_set & CMD_SET_YP) ? 1 : -1;
int bpp;
int x_mul;
int cpu_dat_shift;
uint32_t *pattern_data;
uint32_t src_fg_clr;
uint32_t src_bg_clr;
switch (virge->s3d.cmd_set & CMD_SET_FORMAT_MASK) {
case CMD_SET_FORMAT_8:
bpp = 0;
x_mul = 1;
cpu_dat_shift = 8;
pattern_data = virge->s3d.pattern_8;
src_fg_clr = virge->s3d.src_fg_clr & 0xff;
src_bg_clr = virge->s3d.src_bg_clr & 0xff;
break;
case CMD_SET_FORMAT_16:
bpp = 1;
x_mul = 2;
cpu_dat_shift = 16;
pattern_data = virge->s3d.pattern_16;
src_fg_clr = virge->s3d.src_fg_clr & 0xffff;
src_bg_clr = virge->s3d.src_bg_clr & 0xffff;
break;
case CMD_SET_FORMAT_24:
default:
bpp = 2;
x_mul = 3;
cpu_dat_shift = 24;
pattern_data = virge->s3d.pattern_24;
src_fg_clr = virge->s3d.src_fg_clr;
src_bg_clr = virge->s3d.src_bg_clr;
break;
}
if (virge->s3d.cmd_set & CMD_SET_MP)
pattern_data = mono_pattern;
switch (virge->s3d.cmd_set & CMD_SET_ITA_MASK) {
case CMD_SET_ITA_BYTE:
count_mask = ~0x7;
break;
case CMD_SET_ITA_WORD:
count_mask = ~0xf;
break;
case CMD_SET_ITA_DWORD:
default:
count_mask = ~0x1f;
break;
}
if (virge->s3d.cmd_set & CMD_SET_MP) {
int x;
int y;
for (y = 0; y < 4; y++) {
for (x = 0; x < 8; x++) {
if (virge->s3d.mono_pat_0 & (1 << (x + y * 8)))
mono_pattern[y * 8 + (7 - x)] = virge->s3d.pat_fg_clr;
else
mono_pattern[y * 8 + (7 - x)] = virge->s3d.pat_bg_clr;
if (virge->s3d.mono_pat_1 & (1 << (x + y * 8)))
mono_pattern[(y + 4) * 8 + (7 - x)] = virge->s3d.pat_fg_clr;
else
mono_pattern[(y + 4) * 8 + (7 - x)] = virge->s3d.pat_bg_clr;
}
}
}
switch (virge->s3d.cmd_set & CMD_SET_COMMAND_MASK) {
case CMD_SET_COMMAND_NOP:
break;
case CMD_SET_COMMAND_BITBLT:
if (count == -1) {
virge->s3d.src_x = virge->s3d.rsrc_x;
virge->s3d.src_y = virge->s3d.rsrc_y;
virge->s3d.dest_x = virge->s3d.rdest_x;
virge->s3d.dest_y = virge->s3d.rdest_y;
virge->s3d.w = virge->s3d.r_width;
virge->s3d.h = virge->s3d.r_height;
virge->s3d.rop = (virge->s3d.cmd_set >> 17) & 0xff;
virge->s3d.data_left_count = 0;
if (virge->s3d.cmd_set & CMD_SET_IDS)
return;
}
if (!virge->s3d.h)
return;
while (count) {
uint32_t src_addr = virge->s3d.src_base + (virge->s3d.src_x * x_mul) +
(virge->s3d.src_y * virge->s3d.src_str);
uint32_t dest_addr = virge->s3d.dest_base + (virge->s3d.dest_x * x_mul) +
(virge->s3d.dest_y * virge->s3d.dest_str);
uint32_t source = 0;
uint32_t dest = 0;
uint32_t pattern;
uint32_t out = 0;
int update = 1;
switch (virge->s3d.cmd_set & (CMD_SET_MS | CMD_SET_IDS)) {
case 0:
case CMD_SET_MS:
READ(src_addr, source);
if ((virge->s3d.cmd_set & CMD_SET_TP) && source == src_fg_clr)
update = 0;
break;
case CMD_SET_IDS:
if (virge->s3d.data_left_count) {
/*Handle shifting for 24-bit data*/
source = virge->s3d.data_left;
source |= ((cpu_dat << virge->s3d.data_left_count) & ~0xff000000);
cpu_dat >>= (cpu_dat_shift - virge->s3d.data_left_count);
count -= (cpu_dat_shift - virge->s3d.data_left_count);
virge->s3d.data_left_count = 0;
if (count < cpu_dat_shift) {
virge->s3d.data_left = cpu_dat;
virge->s3d.data_left_count = count;
count = 0;
}
} else {
source = cpu_dat;
cpu_dat >>= cpu_dat_shift;
count -= cpu_dat_shift;
if (count < cpu_dat_shift) {
virge->s3d.data_left = cpu_dat;
virge->s3d.data_left_count = count;
count = 0;
}
}
if ((virge->s3d.cmd_set & CMD_SET_TP) && source == src_fg_clr)
update = 0;
break;
case CMD_SET_IDS | CMD_SET_MS:
source = (cpu_dat & (1 << 31)) ? src_fg_clr : src_bg_clr;
if ((virge->s3d.cmd_set & CMD_SET_TP) && !(cpu_dat & (1 << 31)))
update = 0;
cpu_dat <<= 1;
count--;
break;
}
CLIP(virge->s3d.dest_x, virge->s3d.dest_y);
if (update) {
READ(dest_addr, dest);
pattern = pattern_data[(virge->s3d.dest_y & 7) * 8 + (virge->s3d.dest_x & 7)];
MIX();
WRITE(dest_addr, out);
}
virge->s3d.src_x += x_inc;
virge->s3d.src_x &= 0x7ff;
virge->s3d.dest_x += x_inc;
virge->s3d.dest_x &= 0x7ff;
if (!virge->s3d.w) {
virge->s3d.src_x = virge->s3d.rsrc_x;
virge->s3d.dest_x = virge->s3d.rdest_x;
virge->s3d.w = virge->s3d.r_width;
virge->s3d.src_y += y_inc;
virge->s3d.dest_y += y_inc;
virge->s3d.h--;
switch (virge->s3d.cmd_set & (CMD_SET_MS | CMD_SET_IDS)) {
case CMD_SET_IDS:
cpu_dat >>= (count - (count & count_mask));
count &= count_mask;
virge->s3d.data_left_count = 0;
break;
case CMD_SET_IDS | CMD_SET_MS:
cpu_dat <<= (count - (count & count_mask));
count &= count_mask;
break;
}
if (!virge->s3d.h)
return;
} else
virge->s3d.w--;
}
break;
case CMD_SET_COMMAND_RECTFILL:
/*No source, pattern = pat_fg_clr*/
if (count == -1) {
virge->s3d.src_x = virge->s3d.rsrc_x;
virge->s3d.src_y = virge->s3d.rsrc_y;
virge->s3d.dest_x = virge->s3d.rdest_x;
virge->s3d.dest_y = virge->s3d.rdest_y;
virge->s3d.w = virge->s3d.r_width;
virge->s3d.h = virge->s3d.r_height;
virge->s3d.rop = (virge->s3d.cmd_set >> 17) & 0xff;
}
while (count && virge->s3d.h) {
uint32_t dest_addr = virge->s3d.dest_base + (virge->s3d.dest_x * x_mul) +
(virge->s3d.dest_y * virge->s3d.dest_str);
uint32_t source = 0;
uint32_t dest = 0;
uint32_t pattern = virge->s3d.pat_fg_clr;
uint32_t out = 0;
int update = 1;
CLIP(virge->s3d.dest_x, virge->s3d.dest_y);
if (update) {
READ(dest_addr, dest);
MIX();
WRITE(dest_addr, out);
}
virge->s3d.src_x += x_inc;
virge->s3d.src_x &= 0x7ff;
virge->s3d.dest_x += x_inc;
virge->s3d.dest_x &= 0x7ff;
if (!virge->s3d.w) {
virge->s3d.src_x = virge->s3d.rsrc_x;
virge->s3d.dest_x = virge->s3d.rdest_x;
virge->s3d.w = virge->s3d.r_width;
virge->s3d.src_y += y_inc;
virge->s3d.dest_y += y_inc;
virge->s3d.h--;
if (!virge->s3d.h)
return;
} else
virge->s3d.w--;
count--;
}
break;
case CMD_SET_COMMAND_LINE:
if (count == -1) {
virge->s3d.dest_x = virge->s3d.lxstart;
virge->s3d.dest_y = virge->s3d.lystart;
virge->s3d.h = virge->s3d.lycnt;
virge->s3d.rop = (virge->s3d.cmd_set >> 17) & 0xff;
}
while (virge->s3d.h) {
int x;
int new_x;
int first_pixel = 1;
x = virge->s3d.dest_x >> 20;
if (virge->s3d.h == virge->s3d.lycnt && ((virge->s3d.line_dir && x > virge->s3d.lxend0) ||
(!virge->s3d.line_dir && x < virge->s3d.lxend0)))
x = virge->s3d.lxend0;
if (virge->s3d.h == 1)
new_x = virge->s3d.lxend1 + (virge->s3d.line_dir ? 1 : -1);
else
new_x = (virge->s3d.dest_x + virge->s3d.ldx) >> 20;
if ((virge->s3d.line_dir && x > new_x) || (!virge->s3d.line_dir && x < new_x))
goto skip_line;
do {
uint32_t dest_addr = virge->s3d.dest_base + (x * x_mul) +
(virge->s3d.dest_y * virge->s3d.dest_str);
uint32_t source = 0;
uint32_t dest = 0;
uint32_t pattern;
uint32_t out = 0;
int update = 1;
if ((virge->s3d.h == virge->s3d.lycnt || !first_pixel) &&
((virge->s3d.line_dir && x < virge->s3d.lxend0) ||
(!virge->s3d.line_dir && x > virge->s3d.lxend0)))
update = 0;
if ((virge->s3d.h == 1 || !first_pixel) &&
((virge->s3d.line_dir && x > virge->s3d.lxend1) ||
(!virge->s3d.line_dir && x < virge->s3d.lxend1)))
update = 0;
CLIP(x, virge->s3d.dest_y);
if (update) {
READ(dest_addr, dest);
pattern = virge->s3d.pat_fg_clr;
MIX();
WRITE(dest_addr, out);
}
if (x < new_x)
x++;
else if (x > new_x)
x--;
first_pixel = 0;
} while (x != new_x);
skip_line:
virge->s3d.dest_x += virge->s3d.ldx;
virge->s3d.dest_y--;
virge->s3d.h--;
}
break;
case CMD_SET_COMMAND_POLY:
/*No source*/
if (virge->s3d.pycnt & (1 << 28))
virge->s3d.dest_r = virge->s3d.prxstart;
if (virge->s3d.pycnt & (1 << 29))
virge->s3d.dest_l = virge->s3d.plxstart;
virge->s3d.h = virge->s3d.pycnt & 0x7ff;
virge->s3d.rop = (virge->s3d.cmd_set >> 17) & 0xff;
while (virge->s3d.h) {
int x = virge->s3d.dest_l >> 20;
int xend = virge->s3d.dest_r >> 20;
int y = virge->s3d.pystart & 0x7ff;
int xdir = (x < xend) ? 1 : -1;
do {
uint32_t dest_addr = virge->s3d.dest_base + (x * x_mul) + (y * virge->s3d.dest_str);
uint32_t source = 0;
uint32_t dest = 0;
uint32_t pattern;
uint32_t out = 0;
int update = 1;
CLIP(x, y);
if (update) {
READ(dest_addr, dest);
pattern = pattern_data[(y & 7) * 8 + (x & 7)];
MIX();
WRITE(dest_addr, out);
}
x = (x + xdir) & 0x7ff;
} while (x != (xend + xdir));
virge->s3d.dest_l += virge->s3d.pldx;
virge->s3d.dest_r += virge->s3d.prdx;
virge->s3d.h--;
virge->s3d.pystart = (virge->s3d.pystart - 1) & 0x7ff;
}
break;
default:
fatal("s3_virge_bitblt : blit command %i %08x\n",
(virge->s3d.cmd_set >> 27) & 0xf, virge->s3d.cmd_set);
}
}
#define RGB15_TO_24(val, r, g, b) \
b = ((val & 0x001f) << 3) | ((val & 0x001f) >> 2); \
g = ((val & 0x03e0) >> 2) | ((val & 0x03e0) >> 7); \
r = ((val & 0x7c00) >> 7) | ((val & 0x7c00) >> 12);
#define RGB24_TO_24(val, r, g, b) \
b = val & 0xff; \
g = (val & 0xff00) >> 8; \
r = (val & 0xff0000) >> 16
#define RGB15(r, g, b, dest) \
if (virge->dithering_enabled) { \
int add = dither[_y & 3][_x & 3]; \
int _r = (r > 248) ? 248 : r + add; \
int _g = (g > 248) ? 248 : g + add; \
int _b = (b > 248) ? 248 : b + add; \
dest = ((_b >> 3) & 0x1f) | \
(((_g >> 3) & 0x1f) << 5) | \
(((_r >> 3) & 0x1f) << 10); \
} else \
dest = ((b >> 3) & 0x1f) | \
(((g >> 3) & 0x1f) << 5) | \
(((r >> 3) & 0x1f) << 10)
#define RGB24(r, g, b) ((b) | ((g) << 8) | ((r) << 16))
typedef struct rgba_t {
int r, g, b, a;
} rgba_t;
typedef struct s3d_state_t {
int32_t r;
int32_t g;
int32_t b;
int32_t a;
int32_t u;
int32_t v;
int32_t d;
int32_t w;
int32_t base_r;
int32_t base_g;
int32_t base_b;
int32_t base_a;
int32_t base_u;
int32_t base_v;
int32_t base_d;
int32_t base_w;
uint32_t base_z;
uint32_t tbu;
uint32_t tbv;
uint32_t cmd_set;
int max_d;
uint16_t *texture[10];
uint32_t tex_bdr_clr;
int32_t x1;
int32_t x2;
int y;
rgba_t dest_rgba;
} s3d_state_t;
typedef struct s3d_texture_state_t {
int level;
int texture_shift;
int32_t u;
int32_t v;
} s3d_texture_state_t;
static void (*tex_read)(s3d_state_t *state, s3d_texture_state_t *texture_state, rgba_t *out);
static void (*tex_sample)(s3d_state_t *state);
static void (*dest_pixel)(s3d_state_t *state);
#define MAX(a, b) ((a) > (b) ? (a) : (b))
#define MIN(a, b) ((a) < (b) ? (a) : (b))
static int _x;
static int _y;
static void
tex_ARGB1555(s3d_state_t *state, s3d_texture_state_t *texture_state, rgba_t *out) {
int offset = ((texture_state->u & 0x7fc0000) >> texture_state->texture_shift) +
(((texture_state->v & 0x7fc0000) >> texture_state->texture_shift) << texture_state->level);
uint16_t val = state->texture[texture_state->level][offset];
out->r = ((val & 0x7c00) >> 7) | ((val & 0x7000) >> 12);
out->g = ((val & 0x03e0) >> 2) | ((val & 0x0380) >> 7);
out->b = ((val & 0x001f) << 3) | ((val & 0x001c) >> 2);
out->a = (val & 0x8000) ? 0xff : 0;
}
static void
tex_ARGB1555_nowrap(s3d_state_t *state, s3d_texture_state_t *texture_state, rgba_t *out) {
int offset = ((texture_state->u & 0x7fc0000) >> texture_state->texture_shift) +
(((texture_state->v & 0x7fc0000) >> texture_state->texture_shift) << texture_state->level);
uint16_t val = state->texture[texture_state->level][offset];
if (((texture_state->u | texture_state->v) & 0xf8000000) == 0xf8000000)
val = state->tex_bdr_clr;
out->r = ((val & 0x7c00) >> 7) | ((val & 0x7000) >> 12);
out->g = ((val & 0x03e0) >> 2) | ((val & 0x0380) >> 7);
out->b = ((val & 0x001f) << 3) | ((val & 0x001c) >> 2);
out->a = (val & 0x8000) ? 0xff : 0;
}
static void
tex_ARGB4444(s3d_state_t *state, s3d_texture_state_t *texture_state, rgba_t *out) {
int offset = ((texture_state->u & 0x7fc0000) >> texture_state->texture_shift) +
(((texture_state->v & 0x7fc0000) >> texture_state->texture_shift) << texture_state->level);
uint16_t val = state->texture[texture_state->level][offset];
out->r = ((val & 0x0f00) >> 4) | ((val & 0x0f00) >> 8);
out->g = (val & 0x00f0) | ((val & 0x00f0) >> 4);
out->b = ((val & 0x000f) << 4) | (val & 0x000f);
out->a = ((val & 0xf000) >> 8) | ((val & 0xf000) >> 12);
}
static void
tex_ARGB4444_nowrap(s3d_state_t *state, s3d_texture_state_t *texture_state, rgba_t *out) {
int offset = ((texture_state->u & 0x7fc0000) >> texture_state->texture_shift) +
(((texture_state->v & 0x7fc0000) >> texture_state->texture_shift) << texture_state->level);
uint16_t val = state->texture[texture_state->level][offset];
if (((texture_state->u | texture_state->v) & 0xf8000000) == 0xf8000000)
val = state->tex_bdr_clr;
out->r = ((val & 0x0f00) >> 4) | ((val & 0x0f00) >> 8);
out->g = (val & 0x00f0) | ((val & 0x00f0) >> 4);
out->b = ((val & 0x000f) << 4) | (val & 0x000f);
out->a = ((val & 0xf000) >> 8) | ((val & 0xf000) >> 12);
}
static void
tex_ARGB8888(s3d_state_t *state, s3d_texture_state_t *texture_state, rgba_t *out) {
int offset = ((texture_state->u & 0x7fc0000) >> texture_state->texture_shift) +
(((texture_state->v & 0x7fc0000) >> texture_state->texture_shift) << texture_state->level);
uint32_t val = ((uint32_t *)state->texture[texture_state->level])[offset];
out->r = (val >> 16) & 0xff;
out->g = (val >> 8) & 0xff;
out->b = val & 0xff;
out->a = (val >> 24) & 0xff;
}
static void
tex_ARGB8888_nowrap(s3d_state_t *state, s3d_texture_state_t *texture_state, rgba_t *out) {
int offset = ((texture_state->u & 0x7fc0000) >> texture_state->texture_shift) +
(((texture_state->v & 0x7fc0000) >> texture_state->texture_shift) << texture_state->level);
uint32_t val = ((uint32_t *)state->texture[texture_state->level])[offset];
if (((texture_state->u | texture_state->v) & 0xf8000000) == 0xf8000000)
val = state->tex_bdr_clr;
out->r = (val >> 16) & 0xff;
out->g = (val >> 8) & 0xff;
out->b = val & 0xff;
out->a = (val >> 24) & 0xff;
}
static void
tex_sample_normal(s3d_state_t *state) {
s3d_texture_state_t texture_state;
texture_state.level = state->max_d;
texture_state.texture_shift = 18 + (9 - texture_state.level);
texture_state.u = state->u + state->tbu;
texture_state.v = state->v + state->tbv;
tex_read(state, &texture_state, &state->dest_rgba);
}
static void
tex_sample_normal_filter(s3d_state_t *state) {
s3d_texture_state_t texture_state;
int tex_offset;
rgba_t tex_samples[4];
int du;
int dv;
int d[4];
texture_state.level = state->max_d;
texture_state.texture_shift = 18 + (9 - texture_state.level);
tex_offset = 1 << texture_state.texture_shift;
texture_state.u = state->u + state->tbu;
texture_state.v = state->v + state->tbv;
tex_read(state, &texture_state, &tex_samples[0]);
du = (texture_state.u >> (texture_state.texture_shift - 8)) & 0xff;
dv = (texture_state.v >> (texture_state.texture_shift - 8)) & 0xff;
texture_state.u = state->u + state->tbu + tex_offset;
texture_state.v = state->v + state->tbv;
tex_read(state, &texture_state, &tex_samples[1]);
texture_state.u = state->u + state->tbu;
texture_state.v = state->v + state->tbv + tex_offset;
tex_read(state, &texture_state, &tex_samples[2]);
texture_state.u = state->u + state->tbu + tex_offset;
texture_state.v = state->v + state->tbv + tex_offset;
tex_read(state, &texture_state, &tex_samples[3]);
d[0] = (256 - du) * (256 - dv);
d[1] = du * (256 - dv);
d[2] = (256 - du) * dv;
d[3] = du * dv;
state->dest_rgba.r = (tex_samples[0].r * d[0] + tex_samples[1].r * d[1] +
tex_samples[2].r * d[2] + tex_samples[3].r * d[3]) >> 16;
state->dest_rgba.g = (tex_samples[0].g * d[0] + tex_samples[1].g * d[1] +
tex_samples[2].g * d[2] + tex_samples[3].g * d[3]) >> 16;
state->dest_rgba.b = (tex_samples[0].b * d[0] + tex_samples[1].b * d[1] +
tex_samples[2].b * d[2] + tex_samples[3].b * d[3]) >> 16;
state->dest_rgba.a = (tex_samples[0].a * d[0] + tex_samples[1].a * d[1] +
tex_samples[2].a * d[2] + tex_samples[3].a * d[3]) >> 16;
}
static void
tex_sample_mipmap(s3d_state_t *state) {
s3d_texture_state_t texture_state;
texture_state.level = (state->d < 0) ? state->max_d : state->max_d - ((state->d >> 27) & 0xf);
if (texture_state.level < 0)
texture_state.level = 0;
texture_state.texture_shift = 18 + (9 - texture_state.level);
texture_state.u = state->u + state->tbu;
texture_state.v = state->v + state->tbv;
tex_read(state, &texture_state, &state->dest_rgba);
}
static void
tex_sample_mipmap_filter(s3d_state_t *state) {
s3d_texture_state_t texture_state;
int tex_offset;
rgba_t tex_samples[4];
int du;
int dv;
int d[4];
texture_state.level = (state->d < 0) ? state->max_d : state->max_d - ((state->d >> 27) & 0xf);
if (texture_state.level < 0)
texture_state.level = 0;
texture_state.texture_shift = 18 + (9 - texture_state.level);
tex_offset = 1 << texture_state.texture_shift;
texture_state.u = state->u + state->tbu;
texture_state.v = state->v + state->tbv;
tex_read(state, &texture_state, &tex_samples[0]);
du = (texture_state.u >> (texture_state.texture_shift - 8)) & 0xff;
dv = (texture_state.v >> (texture_state.texture_shift - 8)) & 0xff;
texture_state.u = state->u + state->tbu + tex_offset;
texture_state.v = state->v + state->tbv;
tex_read(state, &texture_state, &tex_samples[1]);
texture_state.u = state->u + state->tbu;
texture_state.v = state->v + state->tbv + tex_offset;
tex_read(state, &texture_state, &tex_samples[2]);
texture_state.u = state->u + state->tbu + tex_offset;
texture_state.v = state->v + state->tbv + tex_offset;
tex_read(state, &texture_state, &tex_samples[3]);
d[0] = (256 - du) * (256 - dv);
d[1] = du * (256 - dv);
d[2] = (256 - du) * dv;
d[3] = du * dv;
state->dest_rgba.r = (tex_samples[0].r * d[0] + tex_samples[1].r * d[1] +
tex_samples[2].r * d[2] + tex_samples[3].r * d[3]) >> 16;
state->dest_rgba.g = (tex_samples[0].g * d[0] + tex_samples[1].g * d[1] +
tex_samples[2].g * d[2] + tex_samples[3].g * d[3]) >> 16;
state->dest_rgba.b = (tex_samples[0].b * d[0] + tex_samples[1].b * d[1] +
tex_samples[2].b * d[2] + tex_samples[3].b * d[3]) >> 16;
state->dest_rgba.a = (tex_samples[0].a * d[0] + tex_samples[1].a * d[1] +
tex_samples[2].a * d[2] + tex_samples[3].a * d[3]) >> 16;
}
static void
tex_sample_persp_normal(s3d_state_t *state) {
s3d_texture_state_t texture_state;
int32_t w = 0;
if (state->w)
w = (int32_t)(((1ULL << 27) << 19) / (int64_t)state->w);
texture_state.level = state->max_d;
texture_state.texture_shift = 18 + (9 - texture_state.level);
texture_state.u = (int32_t)(((int64_t)state->u * (int64_t)w) >> (12 + state->max_d)) + state->tbu;
texture_state.v = (int32_t)(((int64_t)state->v * (int64_t)w) >> (12 + state->max_d)) + state->tbv;
tex_read(state, &texture_state, &state->dest_rgba);
}
static void
tex_sample_persp_normal_filter(s3d_state_t *state) {
s3d_texture_state_t texture_state;
int32_t w = 0;
int32_t u;
int32_t v;
int tex_offset;
rgba_t tex_samples[4];
int du;
int dv;
int d[4];
if (state->w)
w = (int32_t)(((1ULL << 27) << 19) / (int64_t)state->w);
u = (int32_t)(((int64_t)state->u * (int64_t)w) >> (12 + state->max_d)) + state->tbu;
v = (int32_t)(((int64_t)state->v * (int64_t)w) >> (12 + state->max_d)) + state->tbv;
texture_state.level = state->max_d;
texture_state.texture_shift = 18 + (9 - texture_state.level);
tex_offset = 1 << texture_state.texture_shift;
texture_state.u = u;
texture_state.v = v;
tex_read(state, &texture_state, &tex_samples[0]);
du = (u >> (texture_state.texture_shift - 8)) & 0xff;
dv = (v >> (texture_state.texture_shift - 8)) & 0xff;
texture_state.u = u + tex_offset;
texture_state.v = v;
tex_read(state, &texture_state, &tex_samples[1]);
texture_state.u = u;
texture_state.v = v + tex_offset;
tex_read(state, &texture_state, &tex_samples[2]);
texture_state.u = u + tex_offset;
texture_state.v = v + tex_offset;
tex_read(state, &texture_state, &tex_samples[3]);
d[0] = (256 - du) * (256 - dv);
d[1] = du * (256 - dv);
d[2] = (256 - du) * dv;
d[3] = du * dv;
state->dest_rgba.r = (tex_samples[0].r * d[0] + tex_samples[1].r * d[1] +
tex_samples[2].r * d[2] + tex_samples[3].r * d[3]) >> 16;
state->dest_rgba.g = (tex_samples[0].g * d[0] + tex_samples[1].g * d[1] +
tex_samples[2].g * d[2] + tex_samples[3].g * d[3]) >> 16;
state->dest_rgba.b = (tex_samples[0].b * d[0] + tex_samples[1].b * d[1] +
tex_samples[2].b * d[2] + tex_samples[3].b * d[3]) >> 16;
state->dest_rgba.a = (tex_samples[0].a * d[0] + tex_samples[1].a * d[1] +
tex_samples[2].a * d[2] + tex_samples[3].a * d[3]) >> 16;
}
static void
tex_sample_persp_normal_375(s3d_state_t *state) {
s3d_texture_state_t texture_state;
int32_t w = 0;
if (state->w)
w = (int32_t)(((1ULL << 27) << 19) / (int64_t)state->w);
texture_state.level = state->max_d;
texture_state.texture_shift = 18 + (9 - texture_state.level);
texture_state.u = (int32_t)(((int64_t)state->u * (int64_t)w) >> (8 + state->max_d)) + state->tbu;
texture_state.v = (int32_t)(((int64_t)state->v * (int64_t)w) >> (8 + state->max_d)) + state->tbv;
tex_read(state, &texture_state, &state->dest_rgba);
}
static void
tex_sample_persp_normal_filter_375(s3d_state_t *state) {
s3d_texture_state_t texture_state;
int32_t w = 0;
int32_t u;
int32_t v;
int tex_offset;
rgba_t tex_samples[4];
int du;
int dv;
int d[4];
if (state->w)
w = (int32_t)(((1ULL << 27) << 19) / (int64_t)state->w);
u = (int32_t)(((int64_t)state->u * (int64_t)w) >> (8 + state->max_d)) + state->tbu;
v = (int32_t)(((int64_t)state->v * (int64_t)w) >> (8 + state->max_d)) + state->tbv;
texture_state.level = state->max_d;
texture_state.texture_shift = 18 + (9 - texture_state.level);
tex_offset = 1 << texture_state.texture_shift;
texture_state.u = u;
texture_state.v = v;
tex_read(state, &texture_state, &tex_samples[0]);
du = (u >> (texture_state.texture_shift - 8)) & 0xff;
dv = (v >> (texture_state.texture_shift - 8)) & 0xff;
texture_state.u = u + tex_offset;
texture_state.v = v;
tex_read(state, &texture_state, &tex_samples[1]);
texture_state.u = u;
texture_state.v = v + tex_offset;
tex_read(state, &texture_state, &tex_samples[2]);
texture_state.u = u + tex_offset;
texture_state.v = v + tex_offset;
tex_read(state, &texture_state, &tex_samples[3]);
d[0] = (256 - du) * (256 - dv);
d[1] = du * (256 - dv);
d[2] = (256 - du) * dv;
d[3] = du * dv;
state->dest_rgba.r = (tex_samples[0].r * d[0] + tex_samples[1].r * d[1] +
tex_samples[2].r * d[2] + tex_samples[3].r * d[3]) >> 16;
state->dest_rgba.g = (tex_samples[0].g * d[0] + tex_samples[1].g * d[1] +
tex_samples[2].g * d[2] + tex_samples[3].g * d[3]) >> 16;
state->dest_rgba.b = (tex_samples[0].b * d[0] + tex_samples[1].b * d[1] +
tex_samples[2].b * d[2] + tex_samples[3].b * d[3]) >> 16;
state->dest_rgba.a = (tex_samples[0].a * d[0] + tex_samples[1].a * d[1] +
tex_samples[2].a * d[2] + tex_samples[3].a * d[3]) >> 16;
}
static void
tex_sample_persp_mipmap(s3d_state_t *state) {
s3d_texture_state_t texture_state;
int32_t w = 0;
if (state->w)
w = (int32_t)(((1ULL << 27) << 19) / (int64_t)state->w);
texture_state.level = (state->d < 0) ? state->max_d : state->max_d - ((state->d >> 27) & 0xf);
if (texture_state.level < 0)
texture_state.level = 0;
texture_state.texture_shift = 18 + (9 - texture_state.level);
texture_state.u = (int32_t)(((int64_t)state->u * (int64_t)w) >> (12 + state->max_d)) + state->tbu;
texture_state.v = (int32_t)(((int64_t)state->v * (int64_t)w) >> (12 + state->max_d)) + state->tbv;
tex_read(state, &texture_state, &state->dest_rgba);
}
static void
tex_sample_persp_mipmap_filter(s3d_state_t *state) {
s3d_texture_state_t texture_state;
int32_t w = 0;
int32_t u;
int32_t v;
int tex_offset;
rgba_t tex_samples[4];
int du;
int dv;
int d[4];
if (state->w)
w = (int32_t)(((1ULL << 27) << 19) / (int64_t)state->w);
u = (int32_t)(((int64_t)state->u * (int64_t)w) >> (12 + state->max_d)) + state->tbu;
v = (int32_t)(((int64_t)state->v * (int64_t)w) >> (12 + state->max_d)) + state->tbv;
texture_state.level = (state->d < 0) ? state->max_d : state->max_d - ((state->d >> 27) & 0xf);
if (texture_state.level < 0)
texture_state.level = 0;
texture_state.texture_shift = 18 + (9 - texture_state.level);
tex_offset = 1 << texture_state.texture_shift;
texture_state.u = u;
texture_state.v = v;
tex_read(state, &texture_state, &tex_samples[0]);
du = (u >> (texture_state.texture_shift - 8)) & 0xff;
dv = (v >> (texture_state.texture_shift - 8)) & 0xff;
texture_state.u = u + tex_offset;
texture_state.v = v;
tex_read(state, &texture_state, &tex_samples[1]);
texture_state.u = u;
texture_state.v = v + tex_offset;
tex_read(state, &texture_state, &tex_samples[2]);
texture_state.u = u + tex_offset;
texture_state.v = v + tex_offset;
tex_read(state, &texture_state, &tex_samples[3]);
d[0] = (256 - du) * (256 - dv);
d[1] = du * (256 - dv);
d[2] = (256 - du) * dv;
d[3] = du * dv;
state->dest_rgba.r = (tex_samples[0].r * d[0] + tex_samples[1].r * d[1] +
tex_samples[2].r * d[2] + tex_samples[3].r * d[3]) >> 16;
state->dest_rgba.g = (tex_samples[0].g * d[0] + tex_samples[1].g * d[1] +
tex_samples[2].g * d[2] + tex_samples[3].g * d[3]) >> 16;
state->dest_rgba.b = (tex_samples[0].b * d[0] + tex_samples[1].b * d[1] +
tex_samples[2].b * d[2] + tex_samples[3].b * d[3]) >> 16;
state->dest_rgba.a = (tex_samples[0].a * d[0] + tex_samples[1].a * d[1] +
tex_samples[2].a * d[2] + tex_samples[3].a * d[3]) >> 16;
}
static void
tex_sample_persp_mipmap_375(s3d_state_t *state) {
s3d_texture_state_t texture_state;
int32_t w = 0;
if (state->w)
w = (int32_t)(((1ULL << 27) << 19) / (int64_t)state->w);
texture_state.level = (state->d < 0) ? state->max_d : state->max_d - ((state->d >> 27) & 0xf);
if (texture_state.level < 0)
texture_state.level = 0;
texture_state.texture_shift = 18 + (9 - texture_state.level);
texture_state.u = (int32_t)(((int64_t)state->u * (int64_t)w) >> (8 + state->max_d)) + state->tbu;
texture_state.v = (int32_t)(((int64_t)state->v * (int64_t)w) >> (8 + state->max_d)) + state->tbv;
tex_read(state, &texture_state, &state->dest_rgba);
}
static void
tex_sample_persp_mipmap_filter_375(s3d_state_t *state) {
s3d_texture_state_t texture_state;
int32_t w = 0;
int32_t u;
int32_t v;
int tex_offset;
rgba_t tex_samples[4];
int du;
int dv;
int d[4];
if (state->w)
w = (int32_t)(((1ULL << 27) << 19) / (int64_t)state->w);
u = (int32_t)(((int64_t)state->u * (int64_t)w) >> (8 + state->max_d)) + state->tbu;
v = (int32_t)(((int64_t)state->v * (int64_t)w) >> (8 + state->max_d)) + state->tbv;
texture_state.level = (state->d < 0) ? state->max_d : state->max_d - ((state->d >> 27) & 0xf);
if (texture_state.level < 0)
texture_state.level = 0;
texture_state.texture_shift = 18 + (9 - texture_state.level);
tex_offset = 1 << texture_state.texture_shift;
texture_state.u = u;
texture_state.v = v;
tex_read(state, &texture_state, &tex_samples[0]);
du = (u >> (texture_state.texture_shift - 8)) & 0xff;
dv = (v >> (texture_state.texture_shift - 8)) & 0xff;
texture_state.u = u + tex_offset;
texture_state.v = v;
tex_read(state, &texture_state, &tex_samples[1]);
texture_state.u = u;
texture_state.v = v + tex_offset;
tex_read(state, &texture_state, &tex_samples[2]);
texture_state.u = u + tex_offset;
texture_state.v = v + tex_offset;
tex_read(state, &texture_state, &tex_samples[3]);
d[0] = (256 - du) * (256 - dv);
d[1] = du * (256 - dv);
d[2] = (256 - du) * dv;
d[3] = du * dv;
state->dest_rgba.r = (tex_samples[0].r * d[0] + tex_samples[1].r * d[1] +
tex_samples[2].r * d[2] + tex_samples[3].r * d[3]) >> 16;
state->dest_rgba.g = (tex_samples[0].g * d[0] + tex_samples[1].g * d[1] +
tex_samples[2].g * d[2] + tex_samples[3].g * d[3]) >> 16;
state->dest_rgba.b = (tex_samples[0].b * d[0] + tex_samples[1].b * d[1] +
tex_samples[2].b * d[2] + tex_samples[3].b * d[3]) >> 16;
state->dest_rgba.a = (tex_samples[0].a * d[0] + tex_samples[1].a * d[1] +
tex_samples[2].a * d[2] + tex_samples[3].a * d[3]) >> 16;
}
#define CLAMP(x) \
do { \
if ((x) & ~0xff) \
x = ((x) < 0) ? 0 : 0xff; \
} while (0)
#define CLAMP_RGBA(r, g, b, a) \
if ((r) & ~0xff) \
r = ((r) < 0) ? 0 : 0xff; \
if ((g) & ~0xff) \
g = ((g) < 0) ? 0 : 0xff; \
if ((b) & ~0xff) \
b = ((b) < 0) ? 0 : 0xff; \
if ((a) & ~0xff) \
a = ((a) < 0) ? 0 : 0xff;
#define CLAMP_RGB(r, g, b) \
do { \
if ((r) < 0) \
r = 0; \
if ((r) > 0xff) \
r = 0xff; \
if ((g) < 0) \
g = 0; \
if ((g) > 0xff) \
g = 0xff; \
if ((b) < 0) \
b = 0; \
if ((b) > 0xff) \
b = 0xff; \
} while (0)
static void
dest_pixel_gouraud_shaded_triangle(s3d_state_t *state) {
state->dest_rgba.r = state->r >> 7;
CLAMP(state->dest_rgba.r);
state->dest_rgba.g = state->g >> 7;
CLAMP(state->dest_rgba.g);
state->dest_rgba.b = state->b >> 7;
CLAMP(state->dest_rgba.b);
state->dest_rgba.a = state->a >> 7;
CLAMP(state->dest_rgba.a);
}
static void
dest_pixel_unlit_texture_triangle(s3d_state_t *state) {
tex_sample(state);
if (state->cmd_set & CMD_SET_ABC_SRC)
state->dest_rgba.a = state->a >> 7;
}
static void
dest_pixel_lit_texture_decal(s3d_state_t *state) {
tex_sample(state);
if (state->cmd_set & CMD_SET_ABC_SRC)
state->dest_rgba.a = state->a >> 7;
}
static void
dest_pixel_lit_texture_reflection(s3d_state_t *state) {
tex_sample(state);
state->dest_rgba.r += (state->r >> 7);
state->dest_rgba.g += (state->g >> 7);
state->dest_rgba.b += (state->b >> 7);
if (state->cmd_set & CMD_SET_ABC_SRC)
state->dest_rgba.a += (state->a >> 7);
CLAMP_RGBA(state->dest_rgba.r, state->dest_rgba.g, state->dest_rgba.b, state->dest_rgba.a);
}
static void
dest_pixel_lit_texture_modulate(s3d_state_t *state) {
int r = state->r >> 7;
int g = state->g >> 7;
int b = state->b >> 7;
int a = state->a >> 7;
tex_sample(state);
CLAMP_RGBA(r, g, b, a);
state->dest_rgba.r = ((state->dest_rgba.r) * r) >> 8;
state->dest_rgba.g = ((state->dest_rgba.g) * g) >> 8;
state->dest_rgba.b = ((state->dest_rgba.b) * b) >> 8;
if (state->cmd_set & CMD_SET_ABC_SRC)
state->dest_rgba.a = a;
}
static void
tri(virge_t *virge, s3d_t *s3d_tri, s3d_state_t *state, int yc, int32_t dx1, int32_t dx2) {
uint8_t *vram = virge->svga.vram;
int x_dir = s3d_tri->tlr ? 1 : -1;
int use_z = !(s3d_tri->cmd_set & CMD_SET_ZB_MODE);
int y_count = yc;
int bpp = (s3d_tri->cmd_set >> 2) & 7;
uint32_t dest_offset;
uint32_t z_offset;
dest_offset = s3d_tri->dest_base + (state->y * s3d_tri->dest_str);
z_offset = s3d_tri->z_base + (state->y * s3d_tri->z_str);
if (s3d_tri->cmd_set & CMD_SET_HC) {
if (state->y < s3d_tri->clip_t)
return;
if (state->y > s3d_tri->clip_b) {
int diff_y = state->y - s3d_tri->clip_b;
if (diff_y > y_count)
diff_y = y_count;
state->base_u += (s3d_tri->TdUdY * diff_y);
state->base_v += (s3d_tri->TdVdY * diff_y);
state->base_z += (s3d_tri->TdZdY * diff_y);
state->base_r += (s3d_tri->TdRdY * diff_y);
state->base_g += (s3d_tri->TdGdY * diff_y);
state->base_b += (s3d_tri->TdBdY * diff_y);
state->base_a += (s3d_tri->TdAdY * diff_y);
state->base_d += (s3d_tri->TdDdY * diff_y);
state->base_w += (s3d_tri->TdWdY * diff_y);
state->x1 += (dx1 * diff_y);
state->x2 += (dx2 * diff_y);
state->y -= diff_y;
dest_offset -= s3d_tri->dest_str;
z_offset -= s3d_tri->z_str;
y_count -= diff_y;
}
if ((state->y - y_count) < s3d_tri->clip_t)
y_count = (state->y - s3d_tri->clip_t) + 1;
}
for (; y_count > 0; y_count--) {
int x = (state->x1 + ((1 << 20) - 1)) >> 20;
int xe = (state->x2 + ((1 << 20) - 1)) >> 20;
uint32_t z = (state->base_z > 0) ? (state->base_z << 1) : 0;
if (x_dir < 0) {
x--;
xe--;
}
if (x != xe && ((x_dir > 0 && x < xe) || (x_dir < 0 && x > xe))) {
uint32_t dest_addr;
uint32_t z_addr;
int dx = (x_dir > 0) ? ((31 - ((state->x1 - 1) >> 15)) & 0x1f) :
(((state->x1 - 1) >> 15) & 0x1f);
int x_offset = x_dir * (bpp + 1);
int xz_offset = x_dir << 1;
if (x_dir > 0)
dx += 1;
state->r = state->base_r + ((s3d_tri->TdRdX * dx) >> 5);
state->g = state->base_g + ((s3d_tri->TdGdX * dx) >> 5);
state->b = state->base_b + ((s3d_tri->TdBdX * dx) >> 5);
state->a = state->base_a + ((s3d_tri->TdAdX * dx) >> 5);
state->u = state->base_u + ((s3d_tri->TdUdX * dx) >> 5);
state->v = state->base_v + ((s3d_tri->TdVdX * dx) >> 5);
state->w = state->base_w + ((s3d_tri->TdWdX * dx) >> 5);
state->d = state->base_d + ((s3d_tri->TdDdX * dx) >> 5);
z += ((s3d_tri->TdZdX * dx) >> 5);
if (s3d_tri->cmd_set & CMD_SET_HC) {
if (x_dir > 0) {
if (x > s3d_tri->clip_r)
goto tri_skip_line;
if (xe < s3d_tri->clip_l)
goto tri_skip_line;
if (xe > s3d_tri->clip_r)
xe = s3d_tri->clip_r + 1;
if (x < s3d_tri->clip_l) {
int diff_x = s3d_tri->clip_l - x;
z += (s3d_tri->TdZdX * diff_x);
state->u += (s3d_tri->TdUdX * diff_x);
state->v += (s3d_tri->TdVdX * diff_x);
state->r += (s3d_tri->TdRdX * diff_x);
state->g += (s3d_tri->TdGdX * diff_x);
state->b += (s3d_tri->TdBdX * diff_x);
state->a += (s3d_tri->TdAdX * diff_x);
state->d += (s3d_tri->TdDdX * diff_x);
state->w += (s3d_tri->TdWdX * diff_x);
x = s3d_tri->clip_l;
}
} else {
if (x < s3d_tri->clip_l)
goto tri_skip_line;
if (xe > s3d_tri->clip_r)
goto tri_skip_line;
if (xe < s3d_tri->clip_l)
xe = s3d_tri->clip_l - 1;
if (x > s3d_tri->clip_r) {
int diff_x = x - s3d_tri->clip_r;
z += (s3d_tri->TdZdX * diff_x);
state->u += (s3d_tri->TdUdX * diff_x);
state->v += (s3d_tri->TdVdX * diff_x);
state->r += (s3d_tri->TdRdX * diff_x);
state->g += (s3d_tri->TdGdX * diff_x);
state->b += (s3d_tri->TdBdX * diff_x);
state->a += (s3d_tri->TdAdX * diff_x);
state->d += (s3d_tri->TdDdX * diff_x);
state->w += (s3d_tri->TdWdX * diff_x);
x = s3d_tri->clip_r;
}
}
}
virge->svga.changedvram[(dest_offset & virge->vram_mask) >> 12] = changeframecount;
dest_addr = dest_offset + (x * (bpp + 1));
z_addr = z_offset + (x << 1);
x &= 0xfff;
xe &= 0xfff;
for (; x != xe; x = (x + x_dir) & 0xfff) {
int update = 1;
uint16_t src_z = 0;
_x = x;
_y = state->y;
if (use_z) {
src_z = Z_READ(z_addr);
Z_CLIP(src_z, z >> 16);
}
if (update) {
uint32_t dest_col;
dest_pixel(state);
if (s3d_tri->cmd_set & CMD_SET_FE) {
int a = state->a >> 7;
state->dest_rgba.r = ((state->dest_rgba.r * a) + (s3d_tri->fog_r * (255 - a))) / 255;
state->dest_rgba.g = ((state->dest_rgba.g * a) + (s3d_tri->fog_g * (255 - a))) / 255;
state->dest_rgba.b = ((state->dest_rgba.b * a) + (s3d_tri->fog_b * (255 - a))) / 255;
}
if (s3d_tri->cmd_set & CMD_SET_ABC_ENABLE) {
uint32_t src_col;
int src_r = 0;
uint32_t src_g = 0;
uint32_t src_b = 0;
switch (bpp) {
case 0: /*8 bpp*/
/*Not implemented yet*/
break;
case 1: /*16 bpp*/
src_col = *(uint16_t *)&vram[dest_addr & virge->vram_mask];
RGB15_TO_24(src_col, src_r, src_g, src_b);
break;
case 2: /*24 bpp*/
src_col = (*(uint32_t *)&vram[dest_addr & virge->vram_mask]) & 0xffffff;
RGB24_TO_24(src_col, src_r, src_g, src_b);
break;
}
state->dest_rgba.r = ((state->dest_rgba.r * state->dest_rgba.a) +
(src_r * (255 - state->dest_rgba.a))) / 255;
state->dest_rgba.g = ((state->dest_rgba.g * state->dest_rgba.a) +
(src_g * (255 - state->dest_rgba.a))) / 255;
state->dest_rgba.b = ((state->dest_rgba.b * state->dest_rgba.a) +
(src_b * (255 - state->dest_rgba.a))) / 255;
}
switch (bpp) {
case 0: /*8 bpp*/
/*Not implemented yet*/
break;
case 1: /*16 bpp*/
RGB15(state->dest_rgba.r, state->dest_rgba.g, state->dest_rgba.b, dest_col);
*(uint16_t *)&vram[dest_addr] = dest_col;
break;
case 2: /*24 bpp*/
dest_col = RGB24(state->dest_rgba.r, state->dest_rgba.g, state->dest_rgba.b);
*(uint8_t *)&vram[dest_addr] = dest_col & 0xff;
*(uint8_t *)&vram[dest_addr + 1] = (dest_col >> 8) & 0xff;
*(uint8_t *)&vram[dest_addr + 2] = (dest_col >> 16) & 0xff;
break;
}
if (use_z && (s3d_tri->cmd_set & CMD_SET_ZUP))
Z_WRITE(z_addr, src_z);
}
z += s3d_tri->TdZdX;
state->u += s3d_tri->TdUdX;
state->v += s3d_tri->TdVdX;
state->r += s3d_tri->TdRdX;
state->g += s3d_tri->TdGdX;
state->b += s3d_tri->TdBdX;
state->a += s3d_tri->TdAdX;
state->d += s3d_tri->TdDdX;
state->w += s3d_tri->TdWdX;
dest_addr += x_offset;
z_addr += xz_offset;
virge->pixel_count++;
}
}
tri_skip_line:
state->x1 += dx1;
state->x2 += dx2;
state->base_u += s3d_tri->TdUdY;
state->base_v += s3d_tri->TdVdY;
state->base_z += s3d_tri->TdZdY;
state->base_r += s3d_tri->TdRdY;
state->base_g += s3d_tri->TdGdY;
state->base_b += s3d_tri->TdBdY;
state->base_a += s3d_tri->TdAdY;
state->base_d += s3d_tri->TdDdY;
state->base_w += s3d_tri->TdWdY;
state->y--;
dest_offset -= s3d_tri->dest_str;
z_offset -= s3d_tri->z_str;
}
}
static int tex_size[8] = {4 * 2, 2 * 2, 2 * 2, 1 * 2, 2 / 1, 2 / 1, 1 * 2, 1 * 2};
static void
s3_virge_triangle(virge_t *virge, s3d_t *s3d_tri) {
s3d_state_t state;
uint32_t tex_base;
int c;
uint64_t start_time = plat_timer_read();
uint64_t end_time;
state.tbu = s3d_tri->tbu << 11;
state.tbv = s3d_tri->tbv << 11;
state.max_d = (s3d_tri->cmd_set >> 8) & 15;
state.tex_bdr_clr = s3d_tri->tex_bdr_clr;
state.cmd_set = s3d_tri->cmd_set;
state.base_u = s3d_tri->tus;
state.base_v = s3d_tri->tvs;
state.base_z = s3d_tri->tzs;
state.base_r = (int32_t)s3d_tri->trs;
state.base_g = (int32_t)s3d_tri->tgs;
state.base_b = (int32_t)s3d_tri->tbs;
state.base_a = (int32_t)s3d_tri->tas;
state.base_d = s3d_tri->tds;
state.base_w = s3d_tri->tws;
tex_base = s3d_tri->tex_base;
for (c = 9; c >= 0; c--) {
state.texture[c] = (uint16_t *)&virge->svga.vram[tex_base];
if (c <= state.max_d)
tex_base += ((1 << (c * 2)) * tex_size[(s3d_tri->cmd_set >> 5) & 7]) / 2;
}
switch ((s3d_tri->cmd_set >> 27) & 0xf) {
case 0:
dest_pixel = dest_pixel_gouraud_shaded_triangle;
break;
case 1:
case 5:
switch ((s3d_tri->cmd_set >> 15) & 0x3) {
case 0:
dest_pixel = dest_pixel_lit_texture_reflection;
break;
case 1:
dest_pixel = dest_pixel_lit_texture_modulate;
break;
case 2:
dest_pixel = dest_pixel_lit_texture_decal;
break;
default:
return;
}
break;
case 2:
case 6:
dest_pixel = dest_pixel_unlit_texture_triangle;
break;
default:
return;
}
switch (((s3d_tri->cmd_set >> 12) & 7) | ((s3d_tri->cmd_set & (1 << 29)) ? 8 : 0)) {
case 0:
case 1:
tex_sample = tex_sample_mipmap;
break;
case 2:
case 3:
tex_sample = virge->bilinear_enabled ? tex_sample_mipmap_filter : tex_sample_mipmap;
break;
case 4:
case 5:
tex_sample = tex_sample_normal;
break;
case 6:
case 7:
tex_sample = virge->bilinear_enabled ? tex_sample_normal_filter : tex_sample_normal;
break;
case (0 | 8):
case (1 | 8):
if ((virge->chip == S3_VIRGEDX) || (virge->chip >= S3_VIRGEGX2))
tex_sample = tex_sample_persp_mipmap_375;
else
tex_sample = tex_sample_persp_mipmap;
break;
case (2 | 8):
case (3 | 8):
if ((virge->chip == S3_VIRGEDX) || (virge->chip >= S3_VIRGEGX2))
tex_sample = virge->bilinear_enabled ? tex_sample_persp_mipmap_filter_375 :
tex_sample_persp_mipmap_375;
else
tex_sample = virge->bilinear_enabled ? tex_sample_persp_mipmap_filter :
tex_sample_persp_mipmap;
break;
case (4 | 8):
case (5 | 8):
if ((virge->chip == S3_VIRGEDX) || (virge->chip >= S3_VIRGEGX2))
tex_sample = tex_sample_persp_normal_375;
else
tex_sample = tex_sample_persp_normal;
break;
case (6 | 8):
case (7 | 8):
if ((virge->chip == S3_VIRGEDX) || (virge->chip >= S3_VIRGEGX2))
tex_sample = virge->bilinear_enabled ? tex_sample_persp_normal_filter_375 :
tex_sample_persp_normal_375;
else
tex_sample = virge->bilinear_enabled ? tex_sample_persp_normal_filter :
tex_sample_persp_normal;
break;
}
switch ((s3d_tri->cmd_set >> 5) & 7) {
case 0:
tex_read = (s3d_tri->cmd_set & CMD_SET_TWE) ? tex_ARGB8888 : tex_ARGB8888_nowrap;
break;
case 1:
tex_read = (s3d_tri->cmd_set & CMD_SET_TWE) ? tex_ARGB4444 : tex_ARGB4444_nowrap;
break;
case 2:
tex_read = (s3d_tri->cmd_set & CMD_SET_TWE) ? tex_ARGB1555 : tex_ARGB1555_nowrap;
break;
default:
tex_read = (s3d_tri->cmd_set & CMD_SET_TWE) ? tex_ARGB1555 : tex_ARGB1555_nowrap;
break;
}
state.y = s3d_tri->tys;
state.x1 = s3d_tri->txs;
state.x2 = s3d_tri->txend01;
tri(virge, s3d_tri, &state, s3d_tri->ty01, s3d_tri->TdXdY02, s3d_tri->TdXdY01);
state.x2 = s3d_tri->txend12;
tri(virge, s3d_tri, &state, s3d_tri->ty12, s3d_tri->TdXdY02, s3d_tri->TdXdY12);
virge->tri_count++;
end_time = plat_timer_read();
virge_time += end_time - start_time;
}
static void
render_thread(void *param)
{
virge_t *virge = (virge_t *)param;
while (virge->render_thread_run) {
thread_wait_event(virge->wake_render_thread, -1);
thread_reset_event(virge->wake_render_thread);
virge->s3d_busy = 1;
while (!RB_EMPTY) {
s3_virge_triangle(virge, &virge->s3d_buffer[virge->s3d_read_idx & RB_MASK]);
virge->s3d_read_idx++;
if (RB_ENTRIES == RB_MASK)
thread_set_event(virge->not_full_event);
}
virge->s3d_busy = 0;
virge->subsys_stat |= INT_S3D_DONE;
s3_virge_update_irqs(virge);
}
}
static void
queue_triangle(virge_t *virge)
{
if (RB_FULL) {
thread_reset_event(virge->not_full_event);
if (RB_FULL)
thread_wait_event(virge->not_full_event, -1); /*Wait for room in ringbuffer*/
}
virge->s3d_buffer[virge->s3d_write_idx & RB_MASK] = virge->s3d_tri;
virge->s3d_write_idx++;
if (!virge->s3d_busy)
thread_set_event(virge->wake_render_thread); /*Wake up render thread if moving from idle*/
}
static void s3_virge_hwcursor_draw(svga_t *svga, int displine) {
virge_t *virge = (virge_t *) svga->priv;
int x;
uint16_t dat[2] = { 0, 0 };
int xx;
int offset = svga->hwcursor_latch.x - svga->hwcursor_latch.xoff;
uint32_t fg;
uint32_t bg;
uint32_t vram_mask = virge->vram_mask;
if (svga->interlace && svga->hwcursor_oddeven)
svga->hwcursor_latch.addr += 16;
switch (svga->bpp) {
default:
if (virge->chip != S3_VIRGEGX2) {
fg = svga->pallook[virge->hwc_fg_col & 0xff];
bg = svga->pallook[virge->hwc_bg_col & 0xff];
break;
}
fallthrough;
case 15:
if (virge->chip != S3_VIRGEGX2) {
fg = video_15to32[virge->hwc_fg_col & 0xffff];
bg = video_15to32[virge->hwc_bg_col & 0xffff];
break;
}
fallthrough;
case 16:
if (virge->chip != S3_VIRGEGX2) {
fg = video_16to32[virge->hwc_fg_col & 0xffff];
bg = video_16to32[virge->hwc_bg_col & 0xffff];
break;
}
fallthrough;
case 24:
case 32:
fg = virge->hwc_fg_col;
bg = virge->hwc_bg_col;
break;
}
for (x = 0; x < 64; x += 16) {
dat[0] = (svga->vram[svga->hwcursor_latch.addr & vram_mask] << 8) |
svga->vram[(svga->hwcursor_latch.addr + 1) & vram_mask];
dat[1] = (svga->vram[(svga->hwcursor_latch.addr + 2) & vram_mask] << 8) |
svga->vram[(svga->hwcursor_latch.addr + 3) & vram_mask];
if (svga->crtc[0x55] & 0x10) {
/*X11*/
for (xx = 0; xx < 16; xx++) {
if (offset >= svga->hwcursor_latch.x) {
if (virge->chip == S3_VIRGEGX2)
dat[0] ^= 0x8000;
if (dat[0] & 0x8000)
buffer32->line[displine][offset + svga->x_add] = (dat[1] & 0x8000) ? fg : bg;
}
offset++;
dat[0] <<= 1;
dat[1] <<= 1;
}
} else {
/*Windows*/
for (xx = 0; xx < 16; xx++) {
if (offset >= svga->hwcursor_latch.x) {
if (!(dat[0] & 0x8000))
buffer32->line[displine][offset + svga->x_add] = (dat[1] & 0x8000) ? fg : bg;
else if (dat[1] & 0x8000)
buffer32->line[displine][offset + svga->x_add] ^= 0xffffff;
}
offset++;
dat[0] <<= 1;
dat[1] <<= 1;
}
}
svga->hwcursor_latch.addr += 4;
}
if (svga->interlace && !svga->hwcursor_oddeven)
svga->hwcursor_latch.addr += 16;
}
#define DECODE_YCbCr() \
do { \
int c; \
\
for (c = 0; c < 2; c++) { \
uint8_t y1, y2; \
int8_t Cr; \
int8_t Cb; \
int dR; \
int dG; \
int dB; \
\
y1 = src[0]; \
Cr = src[1] - 0x80; \
y2 = src[2]; \
Cb = src[3] - 0x80; \
src += 4; \
\
dR = (359 * Cr) >> 8; \
dG = (88 * Cb + 183 * Cr) >> 8; \
dB = (453 * Cb) >> 8; \
\
r[x_write] = y1 + dR; \
CLAMP(r[x_write]); \
g[x_write] = y1 - dG; \
CLAMP(g[x_write]); \
b[x_write] = y1 + dB; \
CLAMP(b[x_write]); \
\
r[x_write + 1] = y2 + dR; \
CLAMP(r[x_write + 1]); \
g[x_write + 1] = y2 - dG; \
CLAMP(g[x_write + 1]); \
b[x_write + 1] = y2 + dB; \
CLAMP(b[x_write + 1]); \
\
x_write = (x_write + 2) & 7; \
} \
} while (0)
/*Both YUV formats are untested*/
#define DECODE_YUV211() \
do { \
uint8_t y1, y2, y3, y4; \
int8_t U, V; \
int dR; \
int dG; \
int dB; \
\
U = src[0] - 0x80; \
y1 = (298 * (src[1] - 16)) >> 8; \
y2 = (298 * (src[2] - 16)) >> 8; \
V = src[3] - 0x80; \
y3 = (298 * (src[4] - 16)) >> 8; \
y4 = (298 * (src[5] - 16)) >> 8; \
src += 6; \
\
dR = (309 * V) >> 8; \
dG = (100 * U + 208 * V) >> 8; \
dB = (516 * U) >> 8; \
\
r[x_write] = y1 + dR; \
CLAMP(r[x_write]); \
g[x_write] = y1 - dG; \
CLAMP(g[x_write]); \
b[x_write] = y1 + dB; \
CLAMP(b[x_write]); \
\
r[x_write + 1] = y2 + dR; \
CLAMP(r[x_write + 1]); \
g[x_write + 1] = y2 - dG; \
CLAMP(g[x_write + 1]); \
b[x_write + 1] = y2 + dB; \
CLAMP(b[x_write + 1]); \
\
r[x_write + 2] = y3 + dR; \
CLAMP(r[x_write + 2]); \
g[x_write + 2] = y3 - dG; \
CLAMP(g[x_write + 2]); \
b[x_write + 2] = y3 + dB; \
CLAMP(b[x_write + 2]); \
\
r[x_write + 3] = y4 + dR; \
CLAMP(r[x_write + 3]); \
g[x_write + 3] = y4 - dG; \
CLAMP(g[x_write + 3]); \
b[x_write + 3] = y4 + dB; \
CLAMP(b[x_write + 3]); \
\
x_write = (x_write + 4) & 7; \
} while (0)
#define DECODE_YUV422() \
do { \
int c; \
\
for (c = 0; c < 2; c++) { \
uint8_t y1; \
uint8_t y2; \
int8_t U; \
int8_t V; \
int dR; \
int dG; \
int dB; \
\
U = src[0] - 0x80; \
y1 = (298 * (src[1] - 16)) >> 8; \
V = src[2] - 0x80; \
y2 = (298 * (src[3] - 16)) >> 8; \
src += 4; \
\
dR = (309 * V) >> 8; \
dG = (100 * U + 208 * V) >> 8; \
dB = (516 * U) >> 8; \
\
r[x_write] = y1 + dR; \
CLAMP(r[x_write]); \
g[x_write] = y1 - dG; \
CLAMP(g[x_write]); \
b[x_write] = y1 + dB; \
CLAMP(b[x_write]); \
\
r[x_write + 1] = y2 + dR; \
CLAMP(r[x_write + 1]); \
g[x_write + 1] = y2 - dG; \
CLAMP(g[x_write + 1]); \
b[x_write + 1] = y2 + dB; \
CLAMP(b[x_write + 1]); \
\
x_write = (x_write + 2) & 7; \
} \
} while (0)
#define DECODE_RGB555() \
do { \
int c; \
\
for (c = 0; c < 4; c++) { \
uint16_t dat; \
\
dat = *(uint16_t *)src; \
src += 2; \
\
r[x_write + c] = \
((dat & 0x001f) << 3) | \
((dat & 0x001f) >> 2); \
g[x_write + c] = \
((dat & 0x03e0) >> 2) | \
((dat & 0x03e0) >> 7); \
b[x_write + c] = \
((dat & 0x7c00) >> 7) | \
((dat & 0x7c00) >> 12); \
} \
x_write = (x_write + 4) & 7; \
} while (0)
#define DECODE_RGB565() \
do { \
int c; \
\
for (c = 0; c < 4; c++) { \
uint16_t dat; \
\
dat = *(uint16_t *)src; \
src += 2; \
\
r[x_write + c] = \
((dat & 0x001f) << 3) | \
((dat & 0x001f) >> 2); \
g[x_write + c] = \
((dat & 0x07e0) >> 3) | \
((dat & 0x07e0) >> 9); \
b[x_write + c] = \
((dat & 0xf800) >> 8) | \
((dat & 0xf800) >> 13); \
} \
x_write = (x_write + 4) & 7; \
} while (0)
#define DECODE_RGB888() \
do { \
int c; \
\
for (c = 0; c < 4; c++) { \
r[x_write + c] = src[0]; \
g[x_write + c] = src[1]; \
b[x_write + c] = src[2]; \
src += 3; \
} \
x_write = (x_write + 4) & 7; \
} while (0)
#define DECODE_XRGB8888() \
do { \
int c; \
\
for (c = 0; c < 4; c++) { \
r[x_write + c] = src[0]; \
g[x_write + c] = src[1]; \
b[x_write + c] = src[2]; \
src += 4; \
} \
x_write = (x_write + 4) & 7; \
} while (0)
#define OVERLAY_SAMPLE() \
do { \
switch (virge->streams.sdif) { \
case 1: \
DECODE_YCbCr(); \
break; \
case 2: \
DECODE_YUV422(); \
break; \
case 3: \
DECODE_RGB555(); \
break; \
case 4: \
DECODE_YUV211(); \
break; \
case 5: \
DECODE_RGB565(); \
break; \
case 6: \
DECODE_RGB888(); \
break; \
case 7: \
default: \
DECODE_XRGB8888(); \
break; \
} \
} while (0)
static void
s3_virge_overlay_draw(svga_t *svga, int displine) {
virge_t *virge = (virge_t *) svga->priv;
int offset = (virge->streams.sec_x - virge->streams.pri_x) + 1;
int h_acc = virge->streams.dda_horiz_accumulator;
int r[8];
int g[8];
int b[8];
int x_size;
int x_read = 4;
int x_write = 4;
int x;
uint32_t *p;
uint8_t *src = &svga->vram[svga->overlay_latch.addr];
p = &((uint32_t *)buffer32->line[displine])[offset + svga->x_add];
if ((offset + virge->streams.sec_w) > virge->streams.pri_w)
x_size = (virge->streams.pri_w - virge->streams.sec_x) + 1;
else
x_size = virge->streams.sec_w + 1;
OVERLAY_SAMPLE();
for (x = 0; x < x_size; x++) {
*p++ = r[x_read] | (g[x_read] << 8) | (b[x_read] << 16);
h_acc += virge->streams.k1_horiz_scale;
if (h_acc >= 0) {
if ((x_read ^ (x_read + 1)) & ~3)
OVERLAY_SAMPLE();
x_read = (x_read + 1) & 7;
h_acc += (virge->streams.k2_horiz_scale - virge->streams.k1_horiz_scale);
}
}
svga->overlay_latch.v_acc += virge->streams.k1_vert_scale;
if (svga->overlay_latch.v_acc >= 0) {
svga->overlay_latch.v_acc += (virge->streams.k2_vert_scale - virge->streams.k1_vert_scale);
svga->overlay_latch.addr += virge->streams.sec_stride;
}
}
static uint8_t
s3_virge_pci_read(UNUSED(int func), int addr, void *priv)
{
const virge_t *virge = (virge_t *) priv;
const svga_t *svga = &virge->svga;
uint8_t ret = 0;
switch (addr) {
case 0x00:
ret = 0x33;
break; /*'S3'*/
case 0x01:
ret = 0x53;
break;
case 0x02:
ret = virge->virge_id_low;
break;
case 0x03:
ret = virge->virge_id_high;
break;
case PCI_REG_COMMAND:
ret = virge->pci_regs[PCI_REG_COMMAND] & 0x27;
break;
case 0x07:
ret = virge->pci_regs[0x07] & 0x36;
break;
case 0x08:
ret = virge->virge_rev;
break; /*Revision ID*/
case 0x09:
ret = 0;
break; /*Programming interface*/
case 0x0a:
ret = 0x00;
break; /*Supports VGA interface*/
case 0x0b:
ret = 0x03;
break;
case 0x0d:
ret = virge->pci_regs[0x0d] & 0xf8;
break;
case 0x10:
ret = 0x00;
break; /*Linear frame buffer address*/
case 0x11:
ret = 0x00;
break;
case 0x12:
ret = 0x00;
break;
case 0x13:
ret = (virge->chip == S3_VIRGEVX || virge->chip == S3_TRIO3D2X) ? (svga->crtc[0x59] & 0xfe) : (svga->crtc[0x59] & 0xfc);
break;
case 0x2c:
ret = 0x33;
break; /* Subsystem vendor ID */
case 0x2d:
ret = 0x53;
break;
case 0x2e:
ret = virge->virge_id_low;
break;
case 0x2f:
ret = virge->virge_id_high;
break;
case 0x30:
ret = (!virge->onboard) ? (virge->pci_regs[0x30] & 0x01) : 0x00;
break; /*BIOS ROM address*/
case 0x31:
ret = 0x00;
break;
case 0x32:
ret = (!virge->onboard) ? virge->pci_regs[0x32] : 0x00;
break;
case 0x33:
ret = (!virge->onboard) ? virge->pci_regs[0x33] : 0x00;
break;
case 0x34:
ret = (virge->chip >= S3_VIRGEGX2) ? 0xdc : 0x00;
break;
case 0x3c:
ret = virge->pci_regs[0x3c];
break;
case 0x3d:
ret = PCI_INTA;
break; /*INTA*/
case 0x3e:
ret = 0x04;
break;
case 0x3f:
ret = 0xff;
break;
case 0x80:
ret = 0x02;
break; /* AGP capability */
case 0x81:
ret = 0x00;
break;
case 0x82:
ret = 0x10;
break; /* assumed AGP 1.0 */
case 0x84:
ret = (virge->chip >= S3_TRIO3D2X) ? 0x03 : 0x01;
break;
case 0x87:
ret = 0x1f;
break;
case 0x88:
ret = virge->pci_regs[0x88];
break;
case 0x89:
ret = virge->pci_regs[0x89];
break;
case 0x8a:
ret = virge->pci_regs[0x8a];
break;
case 0x8b:
ret = virge->pci_regs[0x8b];
break;
case 0xdc:
ret = 0x01;
break; /* PCI Power Management capability */
case 0xdd:
ret = virge->is_agp ? 0x80 : 0x00;
break;
case 0xde:
ret = 0x21;
break;
case 0xe0:
ret = virge->pci_regs[0xe0];
break;
case 0xe1:
ret = virge->pci_regs[0xe1];
break;
case 0xe2:
ret = virge->pci_regs[0xe2];
break;
case 0xe3:
ret = virge->pci_regs[0xe3];
break;
default:
break;
}
return ret;
}
static void
s3_virge_pci_write(UNUSED(int func), int addr, uint8_t val, void *priv)
{
virge_t *virge = (virge_t *) priv;
svga_t *svga = &virge->svga;
switch (addr) {
case 0x00:
case 0x01:
case 0x02:
case 0x03:
case 0x08:
case 0x09:
case 0x0a:
case 0x0b:
case 0x3d:
case 0x3e:
case 0x3f:
return;
case PCI_REG_COMMAND:
if (val & PCI_COMMAND_IO) {
io_removehandler(0x03c0, 0x0020, s3_virge_in, NULL, NULL, s3_virge_out, NULL, NULL, virge);
io_sethandler(0x03c0, 0x0020, s3_virge_in, NULL, NULL, s3_virge_out, NULL, NULL, virge);
} else
io_removehandler(0x03c0, 0x0020, s3_virge_in, NULL, NULL, s3_virge_out, NULL, NULL, virge);
virge->pci_regs[PCI_REG_COMMAND] = val & 0x27;
s3_virge_updatemapping(virge);
return;
case 0x07:
virge->pci_regs[0x07] = val & 0x3e;
return;
case 0x0d:
virge->pci_regs[0x0d] = val & 0xf8;
return;
case 0x13:
svga->crtc[0x59] = (virge->chip == S3_VIRGEVX || virge->chip == S3_TRIO3D2X) ? (val & 0xfe) : (val & 0xfc);
s3_virge_updatemapping(virge);
return;
case 0x30:
case 0x32:
case 0x33:
if (virge->onboard)
return;
virge->pci_regs[addr] = val;
if (virge->pci_regs[0x30] & 0x01) {
uint32_t biosaddr = (virge->pci_regs[0x32] << 16) | (virge->pci_regs[0x33] << 24);
if (virge->chip == S3_VIRGEGX2)
mem_mapping_set_addr(&virge->bios_rom.mapping, biosaddr, 0x10000);
else
mem_mapping_set_addr(&virge->bios_rom.mapping, biosaddr, 0x8000);
} else {
mem_mapping_disable(&virge->bios_rom.mapping);
}
return;
case 0x3c:
virge->pci_regs[0x3c] = val;
return;
case 0x88:
virge->pci_regs[0x88] = val & 0x27;
return;
case 0x89:
virge->pci_regs[0x89] = val & 0x03;
return;
case 0x8b:
case 0xe1:
case 0xe3:
virge->pci_regs[addr] = val;
return;
case 0xe0:
virge->pci_regs[0xe0] = val & 0x03;
return;
case 0xe2:
virge->pci_regs[0xe2] = val & 0xc0;
return;
default:
break;
}
}
static void
s3_virge_disable_handlers(virge_t *dev)
{
io_removehandler(0x03c0, 0x0020, s3_virge_in, NULL, NULL,
s3_virge_out, NULL, NULL, dev);
mem_mapping_disable(&dev->linear_mapping);
mem_mapping_disable(&dev->mmio_mapping);
mem_mapping_disable(&dev->new_mmio_mapping);
mem_mapping_disable(&dev->svga.mapping);
mem_mapping_disable(&dev->bios_rom.mapping);
/* Save all the mappings and the timers because they are part of linked lists. */
reset_state->linear_mapping = dev->linear_mapping;
reset_state->mmio_mapping = dev->mmio_mapping;
reset_state->new_mmio_mapping = dev->new_mmio_mapping;
reset_state->svga.mapping = dev->svga.mapping;
reset_state->bios_rom.mapping = dev->bios_rom.mapping;
reset_state->svga.timer = dev->svga.timer;
reset_state->svga.timer8514 = dev->svga.timer8514;
}
static void
s3_virge_reset(void *priv)
{
virge_t *dev = (virge_t *) priv;
if (reset_state != NULL) {
s3_virge_disable_handlers(dev);
dev->virge_busy = 0;
dev->fifo_write_idx = 0;
dev->fifo_read_idx = 0;
dev->s3d_busy = 0;
dev->s3d_write_idx = 0;
dev->s3d_read_idx = 0;
reset_state->pci_slot = dev->pci_slot;
*dev = *reset_state;
}
}
static void *
s3_virge_init(const device_t *info)
{
const char *bios_fn;
virge_t *virge = (virge_t *) calloc(1, sizeof(virge_t));
reset_state = calloc(1, sizeof(virge_t));
virge->bilinear_enabled = device_get_config_int("bilinear");
virge->dithering_enabled = device_get_config_int("dithering");
if (info->local >= S3_VIRGE_GX2)
virge->memory_size = 4;
else
virge->memory_size = device_get_config_int("memory");
virge->onboard = !!(info->local & 0x100);
switch (info->local) {
case S3_VIRGE_325:
bios_fn = ROM_VIRGE_325;
break;
case S3_DIAMOND_STEALTH3D_2000:
bios_fn = ROM_DIAMOND_STEALTH3D_2000;
break;
case S3_DIAMOND_STEALTH3D_3000:
bios_fn = ROM_DIAMOND_STEALTH3D_3000;
break;
case S3_STB_VELOCITY_3D:
bios_fn = ROM_STB_VELOCITY_3D;
break;
case S3_VIRGE_DX:
bios_fn = virge->onboard ? NULL : ROM_VIRGE_DX;
break;
case S3_DIAMOND_STEALTH3D_2000PRO:
bios_fn = ROM_DIAMOND_STEALTH3D_2000PRO;
break;
case S3_VIRGE_GX:
bios_fn = ROM_VIRGE_GX;
break;
case S3_VIRGE_GX2:
bios_fn = ROM_VIRGE_GX2;
break;
case S3_DIAMOND_STEALTH3D_4000:
bios_fn = ROM_DIAMOND_STEALTH3D_4000;
break;
case S3_TRIO_3D2X:
bios_fn = ROM_TRIO3D2X;
break;
default:
free(virge);
return NULL;
}
svga_init(info, &virge->svga, virge, virge->memory_size << 20,
s3_virge_recalctimings,
s3_virge_in, s3_virge_out,
s3_virge_hwcursor_draw,
s3_virge_overlay_draw);
virge->svga.hwcursor.cur_ysize = 64;
if (bios_fn != NULL) {
if (info->local == S3_VIRGE_GX2)
rom_init(&virge->bios_rom, bios_fn, 0xc0000, 0x10000, 0xffff, 0, MEM_MAPPING_EXTERNAL);
else
rom_init(&virge->bios_rom, bios_fn, 0xc0000, 0x8000, 0x7fff, 0, MEM_MAPPING_EXTERNAL);
mem_mapping_disable(&virge->bios_rom.mapping);
}
mem_mapping_add(&virge->linear_mapping, 0, 0,
svga_read_linear,
svga_readw_linear,
svga_readl_linear,
svga_write_linear,
svga_writew_linear,
svga_writel_linear,
NULL,
MEM_MAPPING_EXTERNAL,
&virge->svga);
mem_mapping_add(&virge->mmio_mapping, 0, 0,
s3_virge_mmio_read,
s3_virge_mmio_read_w,
s3_virge_mmio_read_l,
s3_virge_mmio_write,
s3_virge_mmio_write_w,
s3_virge_mmio_write_l,
NULL,
MEM_MAPPING_EXTERNAL,
virge);
mem_mapping_add(&virge->new_mmio_mapping, 0, 0,
s3_virge_mmio_read,
s3_virge_mmio_read_w,
s3_virge_mmio_read_l,
s3_virge_mmio_write,
s3_virge_mmio_write_w,
s3_virge_mmio_write_l,
NULL,
MEM_MAPPING_EXTERNAL,
virge);
io_sethandler(0x03c0, 0x0020, s3_virge_in, NULL, NULL, s3_virge_out, NULL, NULL, virge);
virge->pci_regs[PCI_REG_COMMAND] = 7;
virge->pci_regs[0x05] = 0;
virge->pci_regs[0x06] = 0;
virge->pci_regs[0x07] = 2;
virge->pci_regs[0x32] = 0x0c;
virge->pci_regs[0x3d] = 1;
virge->pci_regs[0x3e] = 4;
virge->pci_regs[0x3f] = 0xff;
virge->virge_rev = 0;
virge->virge_id = 0xe1;
virge->is_agp = !!(info->flags & DEVICE_AGP);
switch (info->local) {
case S3_VIRGE_325:
case S3_DIAMOND_STEALTH3D_2000:
virge->fifo_slots_num = 8;
virge->svga.decode_mask = (4 << 20) - 1;
virge->virge_id_high = 0x56;
virge->virge_id_low = 0x31;
virge->svga.crtc[0x59] = 0x70;
virge->chip = S3_VIRGE;
video_inform(VIDEO_FLAG_TYPE_SPECIAL, &timing_diamond_stealth3d_2000_pci);
break;
case S3_DIAMOND_STEALTH3D_3000:
case S3_STB_VELOCITY_3D:
virge->fifo_slots_num = 8;
virge->svga.decode_mask = (8 << 20) - 1;
virge->virge_id_high = 0x88;
virge->virge_id_low = 0x3d;
virge->svga.crtc[0x59] = 0x70;
virge->chip = S3_VIRGEVX;
video_inform(VIDEO_FLAG_TYPE_SPECIAL, &timing_diamond_stealth3d_3000_pci);
break;
case S3_VIRGE_GX2:
case S3_DIAMOND_STEALTH3D_4000:
virge->fifo_slots_num = 16;
virge->svga.decode_mask = (4 << 20) - 1;
virge->virge_id_high = 0x8a;
virge->virge_id_low = 0x10;
virge->svga.crtc[0x6c] = 1;
virge->svga.crtc[0x59] = 0x70;
virge->svga.vblank_start = s3_virge_vblank_start;
virge->chip = S3_VIRGEGX2;
video_inform(VIDEO_FLAG_TYPE_SPECIAL, virge->is_agp ? &timing_virge_agp : &timing_virge_dx_pci);
break;
case S3_TRIO_3D2X:
virge->fifo_slots_num = 16;
virge->svga.decode_mask = (8 << 20) - 1;
virge->virge_id_high = 0x8a;
virge->virge_id_low = 0x13;
virge->virge_rev = 0x01;
virge->svga.crtc[0x6c] = 1;
virge->svga.crtc[0x59] = 0x70;
virge->svga.vblank_start = s3_virge_vblank_start;
virge->chip = S3_TRIO3D2X;
video_inform(VIDEO_FLAG_TYPE_SPECIAL, virge->is_agp ? &timing_virge_agp : &timing_virge_dx_pci);
break;
case S3_VIRGE_GX:
virge->virge_rev = 0x01;
fallthrough;
default:
virge->fifo_slots_num = 8;
virge->svga.decode_mask = (4 << 20) - 1;
virge->virge_id_high = 0x8a;
virge->virge_id_low = 0x01;
virge->svga.crtc[0x6c] = 1;
virge->svga.crtc[0x59] = 0x70;
virge->svga.vblank_start = s3_virge_vblank_start;
virge->chip = S3_VIRGEDX;
video_inform(VIDEO_FLAG_TYPE_SPECIAL, &timing_virge_dx_pci);
break;
}
if (virge->chip == S3_VIRGEGX2) {
virge->vram_mask = (4 << 20) - 1;
virge->svga.vram_mask = (4 << 20) - 1;
virge->svga.vram_max = 4 << 20;
virge->svga.crtc[0x36] = 2 | (2 << 2) | (1 << 4) | (1 << 5);
} else {
switch (virge->memory_size) {
case 2:
virge->vram_mask = (2 << 20) - 1;
virge->svga.vram_mask = (2 << 20) - 1;
virge->svga.vram_max = 2 << 20;
if (virge->chip == S3_VIRGEVX) {
virge->svga.crtc[0x36] = (0 << 5);
} else
virge->svga.crtc[0x36] = 2 | (0 << 2) | (1 << 4) | (4 << 5);
break;
case 8:
virge->vram_mask = (8 << 20) - 1;
virge->svga.vram_mask = (8 << 20) - 1;
virge->svga.vram_max = 8 << 20;
if (virge->chip == S3_TRIO3D2X)
virge->svga.crtc[0x36] = 2 | (2 << 2) | (1 << 4) | (0 << 5);
else
virge->svga.crtc[0x36] = (3 << 5);
break;
case 4:
virge->vram_mask = (4 << 20) - 1;
virge->svga.vram_mask = (4 << 20) - 1;
virge->svga.vram_max = 4 << 20;
if (virge->chip == S3_VIRGEVX)
virge->svga.crtc[0x36] = (1 << 5);
else if (virge->chip == S3_TRIO3D2X)
virge->svga.crtc[0x36] = 2 | (2 << 2) | (1 << 4) | (2 << 5);
else
virge->svga.crtc[0x36] = 2 | (0 << 2) | (1 << 4) | (0 << 5);
break;
default:
break;
}
if (info->local == S3_VIRGE_GX)
virge->svga.crtc[0x36] |= (1 << 2);
}
virge->svga.crtc[0x37] = 1 | (7 << 5);
virge->svga.crtc[0x53] = 8;
if (bios_fn == NULL)
pci_add_card(virge->is_agp ? PCI_ADD_AGP : PCI_ADD_VIDEO, s3_virge_pci_read, s3_virge_pci_write, virge, &virge->pci_slot);
else
pci_add_card(virge->is_agp ? PCI_ADD_AGP : PCI_ADD_NORMAL, s3_virge_pci_read, s3_virge_pci_write, virge, &virge->pci_slot);
virge->i2c = i2c_gpio_init("ddc_s3_virge");
virge->ddc = ddc_init(i2c_gpio_get_bus(virge->i2c));
virge->svga.force_old_addr = 1;
virge->render_thread_run = 1;
virge->wake_render_thread = thread_create_event();
virge->wake_main_thread = thread_create_event();
virge->not_full_event = thread_create_event();
virge->render_thread = thread_create(render_thread, virge);
virge->fifo_thread_run = 1;
virge->wake_fifo_thread = thread_create_event();
virge->fifo_not_full_event = thread_create_event();
virge->fifo_thread = thread_create(fifo_thread, virge);
virge->local = info->local;
*reset_state = *virge;
return virge;
}
static void
s3_virge_close(void *priv)
{
virge_t *virge = (virge_t *) priv;
virge->render_thread_run = 0;
thread_set_event(virge->wake_render_thread);
thread_wait(virge->render_thread);
thread_destroy_event(virge->not_full_event);
thread_destroy_event(virge->wake_main_thread);
thread_destroy_event(virge->wake_render_thread);
virge->fifo_thread_run = 0;
thread_set_event(virge->wake_fifo_thread);
thread_wait(virge->fifo_thread);
thread_destroy_event(virge->fifo_not_full_event);
thread_destroy_event(virge->wake_fifo_thread);
svga_close(&virge->svga);
ddc_close(virge->ddc);
i2c_gpio_close(virge->i2c);
free(reset_state);
reset_state = NULL;
free(virge);
}
static int
s3_virge_325_diamond_available(void)
{
return rom_present(ROM_DIAMOND_STEALTH3D_2000);
}
static int
s3_virge_325_available(void)
{
return rom_present(ROM_VIRGE_325);
}
static int
s3_virge_988_diamond_available(void)
{
return rom_present(ROM_DIAMOND_STEALTH3D_3000);
}
static int
s3_virge_988_stb_available(void)
{
return rom_present(ROM_STB_VELOCITY_3D);
}
static int
s3_virge_375_available(void)
{
return rom_present(ROM_VIRGE_DX);
}
static int
s3_virge_375_diamond_available(void)
{
return rom_present(ROM_DIAMOND_STEALTH3D_2000PRO);
}
static int
s3_virge_385_available(void)
{
return rom_present(ROM_VIRGE_GX);
}
static int
s3_virge_357_available(void)
{
return rom_present(ROM_VIRGE_GX2);
}
static int
s3_virge_357_diamond_available(void)
{
return rom_present(ROM_DIAMOND_STEALTH3D_4000);
}
static int
s3_trio3d2x_available(void)
{
return rom_present(ROM_TRIO3D2X);
}
static void
s3_virge_speed_changed(void *priv)
{
virge_t *virge = (virge_t *) priv;
svga_recalctimings(&virge->svga);
}
static void
s3_virge_force_redraw(void *priv)
{
virge_t *virge = (virge_t *) priv;
virge->svga.fullchange = changeframecount;
}
static const device_config_t s3_virge_config[] = {
// clang-format off
{
.name = "memory",
.description = "Memory size",
.type = CONFIG_SELECTION,
.default_int = 4,
.selection = {
{
.description = "2 MB",
.value = 2
},
{
.description = "4 MB",
.value = 4
},
{
.description = ""
}
}
},
{
.name = "bilinear",
.description = "Bilinear filtering",
.type = CONFIG_BINARY,
.default_int = 1
},
{
.name = "dithering",
.description = "Dithering",
.type = CONFIG_BINARY,
.default_int = 1
},
{
.type = CONFIG_END
}
// clang-format on
};
static const device_config_t s3_virge_stb_config[] = {
// clang-format off
{
.name = "memory",
.description = "Memory size",
.type = CONFIG_SELECTION,
.default_int = 4,
.selection = {
{
.description = "2 MB",
.value = 2
},
{
.description = "4 MB",
.value = 4
},
{
.description = "8 MB",
.value = 8
},
{
.description = ""
}
}
},
{
.name = "bilinear",
.description = "Bilinear filtering",
.type = CONFIG_BINARY,
.default_int = 1
},
{
.name = "dithering",
.description = "Dithering",
.type = CONFIG_BINARY,
.default_int = 1
},
{
.type = CONFIG_END
}
// clang-format on
};
static const device_config_t s3_virge_357_config[] = {
// clang-format off
{
.name = "bilinear",
.description = "Bilinear filtering",
.type = CONFIG_BINARY,
.default_int = 1
},
{
.name = "dithering",
.description = "Dithering",
.type = CONFIG_BINARY,
.default_int = 1
},
{
.type = CONFIG_END
}
// clang-format on
};
static const device_config_t s3_trio3d2x_config[] = {
// clang-format off
{
.name = "memory",
.description = "Memory size",
.type = CONFIG_SELECTION,
.default_int = 4,
.selection = {
{
.description = "4 MB",
.value = 4
},
{
.description = "8 MB",
.value = 8
},
{
.description = ""
}
}
},
{
.name = "bilinear",
.description = "Bilinear filtering",
.type = CONFIG_BINARY,
.default_int = 1
},
{
.name = "dithering",
.description = "Dithering",
.type = CONFIG_BINARY,
.default_int = 1
},
{
.type = CONFIG_END
}
// clang-format on
};
const device_t s3_virge_325_pci_device = {
.name = "S3 ViRGE (325) PCI",
.internal_name = "virge325_pci",
.flags = DEVICE_PCI,
.local = S3_VIRGE_325,
.init = s3_virge_init,
.close = s3_virge_close,
.reset = s3_virge_reset,
{ .available = s3_virge_325_available },
.speed_changed = s3_virge_speed_changed,
.force_redraw = s3_virge_force_redraw,
.config = s3_virge_config
};
const device_t s3_diamond_stealth_2000_pci_device = {
.name = "S3 ViRGE (Diamond Stealth 3D 2000) PCI",
.internal_name = "stealth3d_2000_pci",
.flags = DEVICE_PCI,
.local = S3_DIAMOND_STEALTH3D_2000,
.init = s3_virge_init,
.close = s3_virge_close,
.reset = s3_virge_reset,
{ .available = s3_virge_325_diamond_available },
.speed_changed = s3_virge_speed_changed,
.force_redraw = s3_virge_force_redraw,
.config = s3_virge_config
};
const device_t s3_diamond_stealth_3000_pci_device = {
.name = "S3 ViRGE/VX (Diamond Stealth 3D 3000) PCI",
.internal_name = "stealth3d_3000_pci",
.flags = DEVICE_PCI,
.local = S3_DIAMOND_STEALTH3D_3000,
.init = s3_virge_init,
.close = s3_virge_close,
.reset = s3_virge_reset,
{ .available = s3_virge_988_diamond_available },
.speed_changed = s3_virge_speed_changed,
.force_redraw = s3_virge_force_redraw,
.config = s3_virge_stb_config
};
const device_t s3_stb_velocity_3d_pci_device = {
.name = "S3 ViRGE/VX (STB Velocity 3D) PCI",
.internal_name = "stb_velocity3d_pci",
.flags = DEVICE_PCI,
.local = S3_STB_VELOCITY_3D,
.init = s3_virge_init,
.close = s3_virge_close,
.reset = s3_virge_reset,
{ .available = s3_virge_988_stb_available },
.speed_changed = s3_virge_speed_changed,
.force_redraw = s3_virge_force_redraw,
.config = s3_virge_stb_config
};
const device_t s3_virge_375_pci_device = {
.name = "S3 ViRGE/DX (375) PCI",
.internal_name = "virge375_pci",
.flags = DEVICE_PCI,
.local = S3_VIRGE_DX,
.init = s3_virge_init,
.close = s3_virge_close,
.reset = s3_virge_reset,
{ .available = s3_virge_375_available },
.speed_changed = s3_virge_speed_changed,
.force_redraw = s3_virge_force_redraw,
.config = s3_virge_config
};
const device_t s3_virge_375_onboard_pci_device = {
.name = "S3 ViRGE/DX (375) On-Board PCI",
.internal_name = "virge375_onboard_pci",
.flags = DEVICE_PCI,
.local = S3_VIRGE_DX | 0x100,
.init = s3_virge_init,
.close = s3_virge_close,
.reset = s3_virge_reset,
{ .available = NULL },
.speed_changed = s3_virge_speed_changed,
.force_redraw = s3_virge_force_redraw,
.config = s3_virge_config
};
const device_t s3_diamond_stealth_2000pro_pci_device = {
.name = "S3 ViRGE/DX (Diamond Stealth 3D 2000 Pro) PCI",
.internal_name = "stealth3d_2000pro_pci",
.flags = DEVICE_PCI,
.local = S3_DIAMOND_STEALTH3D_2000PRO,
.init = s3_virge_init,
.close = s3_virge_close,
.reset = s3_virge_reset,
{ .available = s3_virge_375_diamond_available },
.speed_changed = s3_virge_speed_changed,
.force_redraw = s3_virge_force_redraw,
.config = s3_virge_config
};
const device_t s3_virge_385_pci_device = {
.name = "S3 ViRGE/GX (385) PCI",
.internal_name = "virge385_pci",
.flags = DEVICE_PCI,
.local = S3_VIRGE_GX,
.init = s3_virge_init,
.close = s3_virge_close,
.reset = s3_virge_reset,
{ .available = s3_virge_385_available },
.speed_changed = s3_virge_speed_changed,
.force_redraw = s3_virge_force_redraw,
.config = s3_virge_config
};
const device_t s3_virge_357_pci_device = {
.name = "S3 ViRGE/GX2 (357) PCI",
.internal_name = "virge357_pci",
.flags = DEVICE_PCI,
.local = S3_VIRGE_GX2,
.init = s3_virge_init,
.close = s3_virge_close,
.reset = s3_virge_reset,
{ .available = s3_virge_357_available },
.speed_changed = s3_virge_speed_changed,
.force_redraw = s3_virge_force_redraw,
.config = s3_virge_357_config
};
const device_t s3_virge_357_agp_device = {
.name = "S3 ViRGE/GX2 (357) AGP",
.internal_name = "virge357_agp",
.flags = DEVICE_AGP,
.local = S3_VIRGE_GX2,
.init = s3_virge_init,
.close = s3_virge_close,
.reset = s3_virge_reset,
{ .available = s3_virge_357_available },
.speed_changed = s3_virge_speed_changed,
.force_redraw = s3_virge_force_redraw,
.config = s3_virge_357_config
};
const device_t s3_diamond_stealth_4000_pci_device = {
.name = "S3 ViRGE/GX2 (Diamond Stealth 3D 4000) PCI",
.internal_name = "stealth3d_4000_pci",
.flags = DEVICE_PCI,
.local = S3_DIAMOND_STEALTH3D_4000,
.init = s3_virge_init,
.close = s3_virge_close,
.reset = s3_virge_reset,
{ .available = s3_virge_357_diamond_available },
.speed_changed = s3_virge_speed_changed,
.force_redraw = s3_virge_force_redraw,
.config = s3_virge_357_config
};
const device_t s3_diamond_stealth_4000_agp_device = {
.name = "S3 ViRGE/GX2 (Diamond Stealth 3D 4000) AGP",
.internal_name = "stealth3d_4000_agp",
.flags = DEVICE_AGP,
.local = S3_DIAMOND_STEALTH3D_4000,
.init = s3_virge_init,
.close = s3_virge_close,
.reset = s3_virge_reset,
{ .available = s3_virge_357_diamond_available },
.speed_changed = s3_virge_speed_changed,
.force_redraw = s3_virge_force_redraw,
.config = s3_virge_357_config
};
const device_t s3_trio3d2x_pci_device = {
.name = "S3 Trio3D/2X (362) PCI",
.internal_name = "trio3d2x",
.flags = DEVICE_PCI,
.local = S3_TRIO_3D2X,
.init = s3_virge_init,
.close = s3_virge_close,
.reset = s3_virge_reset,
{ .available = s3_trio3d2x_available },
.speed_changed = s3_virge_speed_changed,
.force_redraw = s3_virge_force_redraw,
.config = s3_trio3d2x_config
};
const device_t s3_trio3d2x_agp_device = {
.name = "S3 Trio3D/2X (362) AGP",
.internal_name = "trio3d2x_agp",
.flags = DEVICE_AGP,
.local = S3_TRIO_3D2X,
.init = s3_virge_init,
.close = s3_virge_close,
.reset = s3_virge_reset,
{ .available = s3_trio3d2x_available },
.speed_changed = s3_virge_speed_changed,
.force_redraw = s3_virge_force_redraw,
.config = s3_trio3d2x_config
};
``` | /content/code_sandbox/src/video/vid_s3_virge.c | c | 2016-06-25T22:29:10 | 2024-08-16T19:09:21 | 86Box | 86Box/86Box | 2,616 | 51,836 |
```c
/*
* 86Box A hypervisor and IBM PC system emulator that specializes in
* running old operating systems and software designed for IBM
* PC systems and compatibles from 1981 through fairly recent
* system designs based on the PCI bus.
*
* This file is part of the 86Box distribution.
*
* 3DFX Voodoo emulation.
*
*
*
* Authors: Sarah Walker, <path_to_url
*
*/
#include <stdarg.h>
#include <stdio.h>
#include <stdint.h>
#include <string.h>
#include <stdlib.h>
#include <stddef.h>
#include <wchar.h>
#include <math.h>
#define HAVE_STDARG_H
#include <86box/86box.h>
#include "cpu.h"
#include <86box/machine.h>
#include <86box/device.h>
#include <86box/mem.h>
#include <86box/timer.h>
#include <86box/device.h>
#include <86box/plat.h>
#include <86box/thread.h>
#include <86box/video.h>
#include <86box/vid_svga.h>
#include <86box/vid_voodoo_common.h>
#include <86box/vid_voodoo_regs.h>
#include <86box/vid_voodoo_render.h>
#include <86box/vid_voodoo_setup.h>
#ifdef ENABLE_VOODOO_SETUP_LOG
int voodoo_setup_do_log = ENABLE_VOODOO_SETUP_LOG;
static void
voodoo_setup_log(const char *fmt, ...)
{
va_list ap;
if (voodoo_setup_do_log) {
va_start(ap, fmt);
pclog_ex(fmt, ap);
va_end(ap);
}
}
#else
# define voodoo_setup_log(fmt, ...)
#endif
void
voodoo_triangle_setup(voodoo_t *voodoo)
{
float dxAB;
float dxBC;
float dyAB;
float dyBC;
float area;
int va = 0;
int vb = 1;
int vc = 2;
vert_t verts[3];
verts[0] = voodoo->verts[0];
verts[1] = voodoo->verts[1];
verts[2] = voodoo->verts[2];
if (verts[0].sVy < verts[1].sVy) {
if (verts[1].sVy < verts[2].sVy) {
/* V1>V0, V2>V1, V2>V1>V0*/
va = 0; /*OK*/
vb = 1;
vc = 2;
} else {
/* V1>V0, V1>V2*/
if (verts[0].sVy < verts[2].sVy) {
/* V1>V0, V1>V2, V2>V0, V1>V2>V0*/
va = 0;
vb = 2;
vc = 1;
} else {
/* V1>V0, V1>V2, V0>V2, V1>V0>V2*/
va = 2;
vb = 0;
vc = 1;
}
}
} else {
if (verts[1].sVy < verts[2].sVy) {
/* V0>V1, V2>V1*/
if (verts[0].sVy < verts[2].sVy) {
/* V0>V1, V2>V1, V2>V0, V2>V0>V1*/
va = 1;
vb = 0;
vc = 2;
} else {
/* V0>V1, V2>V1, V0>V2, V0>V2>V1*/
va = 1;
vb = 2;
vc = 0;
}
} else {
/*V0>V1>V2*/
va = 2;
vb = 1;
vc = 0;
}
}
dxAB = verts[0].sVx - verts[1].sVx;
dxBC = verts[1].sVx - verts[2].sVx;
dyAB = verts[0].sVy - verts[1].sVy;
dyBC = verts[1].sVy - verts[2].sVy;
area = dxAB * dyBC - dxBC * dyAB;
if (area == 0.0)
return;
if (voodoo->sSetupMode & SETUPMODE_CULLING_ENABLE) {
int cull_sign = voodoo->sSetupMode & SETUPMODE_CULLING_SIGN;
int sign = (area < 0.0);
if ((voodoo->sSetupMode & (SETUPMODE_CULLING_ENABLE | SETUPMODE_DISABLE_PINGPONG))
== SETUPMODE_CULLING_ENABLE
&& voodoo->cull_pingpong)
cull_sign = !cull_sign;
if (cull_sign && sign)
return;
if (!cull_sign && !sign)
return;
}
dxAB = verts[va].sVx - verts[vb].sVx;
dxBC = verts[vb].sVx - verts[vc].sVx;
dyAB = verts[va].sVy - verts[vb].sVy;
dyBC = verts[vb].sVy - verts[vc].sVy;
area = dxAB * dyBC - dxBC * dyAB;
dxAB /= area;
dxBC /= area;
dyAB /= area;
dyBC /= area;
voodoo->params.vertexAx = (int32_t) (int16_t) ((int32_t) (verts[va].sVx * 16.0f) & 0xffff);
voodoo->params.vertexAy = (int32_t) (int16_t) ((int32_t) (verts[va].sVy * 16.0f) & 0xffff);
voodoo->params.vertexBx = (int32_t) (int16_t) ((int32_t) (verts[vb].sVx * 16.0f) & 0xffff);
voodoo->params.vertexBy = (int32_t) (int16_t) ((int32_t) (verts[vb].sVy * 16.0f) & 0xffff);
voodoo->params.vertexCx = (int32_t) (int16_t) ((int32_t) (verts[vc].sVx * 16.0f) & 0xffff);
voodoo->params.vertexCy = (int32_t) (int16_t) ((int32_t) (verts[vc].sVy * 16.0f) & 0xffff);
if (voodoo->params.vertexAy > voodoo->params.vertexBy || voodoo->params.vertexBy > voodoo->params.vertexCy) {
voodoo_setup_log("triangle_setup wrong order %d %d %d\n", voodoo->params.vertexAy, voodoo->params.vertexBy, voodoo->params.vertexCy);
return;
}
if (voodoo->sSetupMode & SETUPMODE_RGB) {
voodoo->params.startR = (int32_t) (verts[va].sRed * 4096.0f);
voodoo->params.dRdX = (int32_t) (((verts[va].sRed - verts[vb].sRed) * dyBC - (verts[vb].sRed - verts[vc].sRed) * dyAB) * 4096.0f);
voodoo->params.dRdY = (int32_t) (((verts[vb].sRed - verts[vc].sRed) * dxAB - (verts[va].sRed - verts[vb].sRed) * dxBC) * 4096.0f);
voodoo->params.startG = (int32_t) (verts[va].sGreen * 4096.0f);
voodoo->params.dGdX = (int32_t) (((verts[va].sGreen - verts[vb].sGreen) * dyBC - (verts[vb].sGreen - verts[vc].sGreen) * dyAB) * 4096.0f);
voodoo->params.dGdY = (int32_t) (((verts[vb].sGreen - verts[vc].sGreen) * dxAB - (verts[va].sGreen - verts[vb].sGreen) * dxBC) * 4096.0f);
voodoo->params.startB = (int32_t) (verts[va].sBlue * 4096.0f);
voodoo->params.dBdX = (int32_t) (((verts[va].sBlue - verts[vb].sBlue) * dyBC - (verts[vb].sBlue - verts[vc].sBlue) * dyAB) * 4096.0f);
voodoo->params.dBdY = (int32_t) (((verts[vb].sBlue - verts[vc].sBlue) * dxAB - (verts[va].sBlue - verts[vb].sBlue) * dxBC) * 4096.0f);
}
if (voodoo->sSetupMode & SETUPMODE_ALPHA) {
voodoo->params.startA = (int32_t) (verts[va].sAlpha * 4096.0f);
voodoo->params.dAdX = (int32_t) (((verts[va].sAlpha - verts[vb].sAlpha) * dyBC - (verts[vb].sAlpha - verts[vc].sAlpha) * dyAB) * 4096.0f);
voodoo->params.dAdY = (int32_t) (((verts[vb].sAlpha - verts[vc].sAlpha) * dxAB - (verts[va].sAlpha - verts[vb].sAlpha) * dxBC) * 4096.0f);
}
if (voodoo->sSetupMode & SETUPMODE_Z) {
voodoo->params.startZ = (int32_t) (verts[va].sVz * 4096.0f);
voodoo->params.dZdX = (int32_t) (((verts[va].sVz - verts[vb].sVz) * dyBC - (verts[vb].sVz - verts[vc].sVz) * dyAB) * 4096.0f);
voodoo->params.dZdY = (int32_t) (((verts[vb].sVz - verts[vc].sVz) * dxAB - (verts[va].sVz - verts[vb].sVz) * dxBC) * 4096.0f);
}
if (voodoo->sSetupMode & SETUPMODE_Wb) {
voodoo->params.startW = (int64_t) (verts[va].sWb * 4294967296.0f);
voodoo->params.dWdX = (int64_t) (((verts[va].sWb - verts[vb].sWb) * dyBC - (verts[vb].sWb - verts[vc].sWb) * dyAB) * 4294967296.0f);
voodoo->params.dWdY = (int64_t) (((verts[vb].sWb - verts[vc].sWb) * dxAB - (verts[va].sWb - verts[vb].sWb) * dxBC) * 4294967296.0f);
voodoo->params.tmu[0].startW = voodoo->params.tmu[1].startW = voodoo->params.startW;
voodoo->params.tmu[0].dWdX = voodoo->params.tmu[1].dWdX = voodoo->params.dWdX;
voodoo->params.tmu[0].dWdY = voodoo->params.tmu[1].dWdY = voodoo->params.dWdY;
}
if (voodoo->sSetupMode & SETUPMODE_W0) {
voodoo->params.tmu[0].startW = (int64_t) (verts[va].sW0 * 4294967296.0f);
voodoo->params.tmu[0].dWdX = (int64_t) (((verts[va].sW0 - verts[vb].sW0) * dyBC - (verts[vb].sW0 - verts[vc].sW0) * dyAB) * 4294967296.0f);
voodoo->params.tmu[0].dWdY = (int64_t) (((verts[vb].sW0 - verts[vc].sW0) * dxAB - (verts[va].sW0 - verts[vb].sW0) * dxBC) * 4294967296.0f);
voodoo->params.tmu[1].startW = voodoo->params.tmu[0].startW;
voodoo->params.tmu[1].dWdX = voodoo->params.tmu[0].dWdX;
voodoo->params.tmu[1].dWdY = voodoo->params.tmu[0].dWdY;
}
if (voodoo->sSetupMode & SETUPMODE_S0_T0) {
voodoo->params.tmu[0].startS = (int64_t) (verts[va].sS0 * 4294967296.0f);
voodoo->params.tmu[0].dSdX = (int64_t) (((verts[va].sS0 - verts[vb].sS0) * dyBC - (verts[vb].sS0 - verts[vc].sS0) * dyAB) * 4294967296.0f);
voodoo->params.tmu[0].dSdY = (int64_t) (((verts[vb].sS0 - verts[vc].sS0) * dxAB - (verts[va].sS0 - verts[vb].sS0) * dxBC) * 4294967296.0f);
voodoo->params.tmu[0].startT = (int64_t) (verts[va].sT0 * 4294967296.0f);
voodoo->params.tmu[0].dTdX = (int64_t) (((verts[va].sT0 - verts[vb].sT0) * dyBC - (verts[vb].sT0 - verts[vc].sT0) * dyAB) * 4294967296.0f);
voodoo->params.tmu[0].dTdY = (int64_t) (((verts[vb].sT0 - verts[vc].sT0) * dxAB - (verts[va].sT0 - verts[vb].sT0) * dxBC) * 4294967296.0f);
voodoo->params.tmu[1].startS = voodoo->params.tmu[0].startS;
voodoo->params.tmu[1].dSdX = voodoo->params.tmu[0].dSdX;
voodoo->params.tmu[1].dSdY = voodoo->params.tmu[0].dSdY;
voodoo->params.tmu[1].startT = voodoo->params.tmu[0].startT;
voodoo->params.tmu[1].dTdX = voodoo->params.tmu[0].dTdX;
voodoo->params.tmu[1].dTdY = voodoo->params.tmu[0].dTdY;
}
if (voodoo->sSetupMode & SETUPMODE_W1) {
voodoo->params.tmu[1].startW = (int64_t) (verts[va].sW1 * 4294967296.0f);
voodoo->params.tmu[1].dWdX = (int64_t) (((verts[va].sW1 - verts[vb].sW1) * dyBC - (verts[vb].sW1 - verts[vc].sW1) * dyAB) * 4294967296.0f);
voodoo->params.tmu[1].dWdY = (int64_t) (((verts[vb].sW1 - verts[vc].sW1) * dxAB - (verts[va].sW1 - verts[vb].sW1) * dxBC) * 4294967296.0f);
}
if (voodoo->sSetupMode & SETUPMODE_S1_T1) {
voodoo->params.tmu[1].startS = (int64_t) (verts[va].sS1 * 4294967296.0f);
voodoo->params.tmu[1].dSdX = (int64_t) (((verts[va].sS1 - verts[vb].sS1) * dyBC - (verts[vb].sS1 - verts[vc].sS1) * dyAB) * 4294967296.0f);
voodoo->params.tmu[1].dSdY = (int64_t) (((verts[vb].sS1 - verts[vc].sS1) * dxAB - (verts[va].sS1 - verts[vb].sS1) * dxBC) * 4294967296.0f);
voodoo->params.tmu[1].startT = (int64_t) (verts[va].sT1 * 4294967296.0f);
voodoo->params.tmu[1].dTdX = (int64_t) (((verts[va].sT1 - verts[vb].sT1) * dyBC - (verts[vb].sT1 - verts[vc].sT1) * dyAB) * 4294967296.0f);
voodoo->params.tmu[1].dTdY = (int64_t) (((verts[vb].sT1 - verts[vc].sT1) * dxAB - (verts[va].sT1 - verts[vb].sT1) * dxBC) * 4294967296.0f);
}
voodoo->params.sign = (area < 0.0);
if (voodoo->ncc_dirty[0])
voodoo_update_ncc(voodoo, 0);
if (voodoo->ncc_dirty[1])
voodoo_update_ncc(voodoo, 1);
voodoo->ncc_dirty[0] = voodoo->ncc_dirty[1] = 0;
voodoo_queue_triangle(voodoo, &voodoo->params);
}
``` | /content/code_sandbox/src/video/vid_voodoo_setup.c | c | 2016-06-25T22:29:10 | 2024-08-16T19:09:21 | 86Box | 86Box/86Box | 2,616 | 4,165 |
```c
/*
* 86Box A hypervisor and IBM PC system emulator that specializes in
* running old operating systems and software designed for IBM
* PC systems and compatibles from 1981 through fairly recent
* system designs based on the PCI bus.
*
* This file is part of the 86Box distribution.
*
* ATi Mach64 graphics card emulation.
*
*
*
* Authors: Sarah Walker, <path_to_url
* Miran Grca, <mgrca8@gmail.com>
*
*/
#include <stdarg.h>
#include <stdint.h>
#include <stdio.h>
#include <string.h>
#include <stdlib.h>
#include <wchar.h>
#include <stdatomic.h>
#define HAVE_STDARG_H
#include <86box/86box.h>
#include <86box/device.h>
#include <86box/io.h>
#include <86box/mem.h>
#include <86box/timer.h>
#include <86box/pci.h>
#include <86box/rom.h>
#include <86box/plat.h>
#include <86box/thread.h>
#include <86box/video.h>
#include <86box/i2c.h>
#include <86box/vid_ddc.h>
#include <86box/vid_svga.h>
#include <86box/vid_svga_render.h>
#include <86box/vid_ati_eeprom.h>
#ifdef CLAMP
# undef CLAMP
#endif
#define BIOS_ROM_PATH "roms/video/mach64/bios.bin"
#define BIOS_ISA_ROM_PATH "roms/video/mach64/M64-1994.VBI"
#define BIOS_VLB_ROM_PATH "roms/video/mach64/mach64_vlb_vram.bin"
#define BIOS_ROMVT2_PATH "roms/video/mach64/atimach64vt2pci.bin"
#define FIFO_SIZE 65536
#define FIFO_MASK (FIFO_SIZE - 1)
#define FIFO_ENTRY_SIZE (1 << 31)
#define FIFO_ENTRIES (mach64->fifo_write_idx - mach64->fifo_read_idx)
#define FIFO_FULL ((mach64->fifo_write_idx - mach64->fifo_read_idx) >= FIFO_SIZE)
#define FIFO_EMPTY (mach64->fifo_read_idx == mach64->fifo_write_idx)
#define FIFO_TYPE 0xff000000
#define FIFO_ADDR 0x00ffffff
enum {
FIFO_INVALID = (0x00 << 24),
FIFO_WRITE_BYTE = (0x01 << 24),
FIFO_WRITE_WORD = (0x02 << 24),
FIFO_WRITE_DWORD = (0x03 << 24)
};
typedef struct fifo_entry_t {
uint32_t addr_type;
uint32_t val;
} fifo_entry_t;
enum {
MACH64_GX = 0,
MACH64_VT2
};
typedef struct mach64_t {
mem_mapping_t linear_mapping;
mem_mapping_t mmio_mapping;
mem_mapping_t mmio_linear_mapping;
mem_mapping_t mmio_linear_mapping_2;
ati_eeprom_t eeprom;
svga_t svga;
rom_t bios_rom;
uint8_t regs[256];
int index;
int type;
int pci;
uint8_t pci_slot;
uint8_t irq_state;
uint8_t pci_regs[256];
uint8_t int_line;
int bank_r[2];
int bank_w[2];
uint32_t vram_size;
uint32_t vram_mask;
uint32_t config_cntl;
uint32_t context_load_cntl;
uint32_t context_mask;
uint32_t crtc_gen_cntl;
uint8_t crtc_int_cntl;
uint32_t crtc_h_sync_strt_wid;
uint32_t crtc_h_total_disp;
uint32_t crtc_v_sync_strt_wid;
uint32_t crtc_v_total_disp;
uint32_t crtc_off_pitch;
uint32_t clock_cntl;
uint32_t clr_cmp_clr;
uint32_t clr_cmp_cntl;
uint32_t clr_cmp_mask;
uint32_t cur_horz_vert_off;
uint32_t cur_horz_vert_posn;
uint32_t cur_offset;
uint32_t dac_cntl;
uint32_t dp_bkgd_clr;
uint32_t dp_frgd_clr;
uint32_t dp_mix;
uint32_t dp_pix_width;
uint32_t dp_src;
uint32_t dst_bres_lnth;
uint32_t dst_bres_dec;
uint32_t dst_bres_err;
uint32_t dst_bres_inc;
uint32_t dst_cntl;
uint32_t dst_height_width;
uint32_t dst_off_pitch;
uint32_t dst_y_x;
uint32_t gen_test_cntl;
uint32_t gui_traj_cntl;
uint32_t host_cntl;
uint32_t mem_cntl;
uint32_t ovr_clr;
uint32_t ovr_wid_left_right;
uint32_t ovr_wid_top_bottom;
uint32_t pat_cntl;
uint32_t pat_reg0;
uint32_t pat_reg1;
uint32_t sc_left_right;
uint32_t sc_top_bottom;
uint32_t scratch_reg0;
uint32_t scratch_reg1;
uint32_t src_cntl;
uint32_t src_off_pitch;
uint32_t src_y_x;
uint32_t src_y_x_start;
uint32_t src_height1_width1;
uint32_t src_height2_width2;
uint32_t write_mask;
uint32_t chain_mask;
uint32_t linear_base;
uint32_t io_base;
struct {
int op;
int dst_x;
int dst_y;
int dst_x_start;
int dst_y_start;
int src_x;
int src_y;
int src_x_start;
int src_y_start;
int xinc;
int yinc;
int x_count;
int y_count;
int xx_count;
int src_x_count;
int src_y_count;
int src_width1;
int src_height1;
int src_width2;
int src_height2;
uint32_t src_offset;
uint32_t src_pitch;
uint32_t dst_offset;
uint32_t dst_pitch;
int mix_bg;
int mix_fg;
int source_bg;
int source_fg;
int source_mix;
int source_host;
int dst_width;
int dst_height;
int busy;
int pattern[8][8];
uint8_t pattern_clr4x2[2][4];
uint8_t pattern_clr8x1[8];
int sc_left;
int sc_right;
int sc_top;
int sc_bottom;
int dst_pix_width;
int src_pix_width;
int host_pix_width;
int dst_size;
int src_size;
int host_size;
int temp_cnt;
uint32_t dp_bkgd_clr;
uint32_t dp_frgd_clr;
uint32_t write_mask;
uint32_t clr_cmp_clr;
uint32_t clr_cmp_mask;
int clr_cmp_fn;
int clr_cmp_src;
int err;
int poly_draw;
} accel;
fifo_entry_t fifo[FIFO_SIZE];
atomic_int fifo_read_idx;
atomic_int fifo_write_idx;
thread_t *fifo_thread;
event_t *wake_fifo_thread;
event_t *fifo_not_full_event;
int blitter_busy;
uint64_t blitter_time;
uint64_t status_time;
uint16_t pci_id;
uint32_t config_chip_id;
uint32_t block_decoded_io;
int use_block_decoded_io;
int pll_addr;
uint8_t pll_regs[16];
double pll_freq[4];
uint32_t config_stat0;
uint32_t cur_clr0;
uint32_t cur_clr1;
uint32_t overlay_dat[1024];
uint32_t overlay_graphics_key_clr;
uint32_t overlay_graphics_key_msk;
uint32_t overlay_video_key_clr;
uint32_t overlay_video_key_msk;
uint32_t overlay_key_cntl;
uint32_t overlay_scale_inc;
uint32_t overlay_scale_cntl;
uint32_t overlay_y_x_start;
uint32_t overlay_y_x_end;
uint32_t scaler_height_width;
int scaler_format;
int scaler_update;
uint32_t buf_offset[2];
uint32_t buf_pitch[2];
int overlay_v_acc;
uint8_t thread_run;
void *i2c;
void *ddc;
} mach64_t;
static video_timings_t timing_mach64_isa = { .type = VIDEO_ISA, .write_b = 3, .write_w = 3, .write_l = 6, .read_b = 5, .read_w = 5, .read_l = 10 };
static video_timings_t timing_mach64_vlb = { .type = VIDEO_BUS, .write_b = 2, .write_w = 2, .write_l = 1, .read_b = 20, .read_w = 20, .read_l = 21 };
static video_timings_t timing_mach64_pci = { .type = VIDEO_PCI, .write_b = 2, .write_w = 2, .write_l = 1, .read_b = 20, .read_w = 20, .read_l = 21 };
enum {
SRC_BG = 0,
SRC_FG = 1,
SRC_HOST = 2,
SRC_BLITSRC = 3,
SRC_PAT = 4
};
enum {
MONO_SRC_1 = 0,
MONO_SRC_PAT = 1,
MONO_SRC_HOST = 2,
MONO_SRC_BLITSRC = 3
};
enum {
BPP_1 = 0,
BPP_4 = 1,
BPP_8 = 2,
BPP_15 = 3,
BPP_16 = 4,
BPP_24 = 5,
BPP_32 = 6
};
enum {
OP_RECT,
OP_LINE
};
enum {
SRC_PATT_EN = 1,
SRC_PATT_ROT_EN = 2,
SRC_LINEAR_EN = 4
};
enum {
DP_BYTE_PIX_ORDER = (1 << 24)
};
#define WIDTH_1BIT 3
static int mach64_width[8] = { WIDTH_1BIT, 0, 0, 1, 1, 2, 2, 0 };
enum {
DST_X_DIR = 0x01,
DST_Y_DIR = 0x02,
DST_Y_MAJOR = 0x04,
DST_X_TILE = 0x08,
DST_Y_TILE = 0x10,
DST_LAST_PEL = 0x20,
DST_POLYGON_EN = 0x40,
DST_24_ROT_EN = 0x80
};
enum {
HOST_BYTE_ALIGN = (1 << 0)
};
void mach64_write(uint32_t addr, uint8_t val, void *priv);
void mach64_writew(uint32_t addr, uint16_t val, void *priv);
void mach64_writel(uint32_t addr, uint32_t val, void *priv);
uint8_t mach64_read(uint32_t addr, void *priv);
uint16_t mach64_readw(uint32_t addr, void *priv);
uint32_t mach64_readl(uint32_t addr, void *priv);
void mach64_updatemapping(mach64_t *mach64);
void mach64_recalctimings(svga_t *svga);
void mach64_start_fill(mach64_t *mach64);
void mach64_start_line(mach64_t *mach64);
void mach64_blit(uint32_t cpu_dat, int count, mach64_t *mach64);
void mach64_load_context(mach64_t *mach64);
uint8_t mach64_ext_readb(uint32_t addr, void *priv);
uint16_t mach64_ext_readw(uint32_t addr, void *priv);
uint32_t mach64_ext_readl(uint32_t addr, void *priv);
void mach64_ext_writeb(uint32_t addr, uint8_t val, void *priv);
void mach64_ext_writew(uint32_t addr, uint16_t val, void *priv);
void mach64_ext_writel(uint32_t addr, uint32_t val, void *priv);
#ifdef ENABLE_MACH64_LOG
int mach64_do_log = ENABLE_MACH64_LOG;
static void
mach64_log(const char *fmt, ...)
{
va_list ap;
if (mach64_do_log) {
va_start(ap, fmt);
pclog_ex(fmt, ap);
va_end(ap);
}
}
#else
# define mach64_log(fmt, ...)
#endif
void
mach64_out(uint16_t addr, uint8_t val, void *priv)
{
mach64_t *mach64 = priv;
svga_t *svga = &mach64->svga;
uint8_t old;
if (((addr & 0xFFF0) == 0x3D0 || (addr & 0xFFF0) == 0x3B0) && !(svga->miscout & 1))
addr ^= 0x60;
switch (addr) {
case 0x1ce:
mach64->index = val;
break;
case 0x1cf:
mach64->regs[mach64->index & 0x3f] = val;
if ((mach64->index & 0x3f) == 0x36)
svga_recalctimings(svga);
break;
case 0x3C6:
case 0x3C7:
case 0x3C8:
case 0x3C9:
if (mach64->type == MACH64_GX)
ati68860_ramdac_out((addr & 3) | ((mach64->dac_cntl & 3) << 2), val, svga->ramdac, svga);
else
svga_out(addr, val, svga);
return;
case 0x3cf:
if (svga->gdcaddr == 6) {
uint8_t old_val = svga->gdcreg[6];
svga->gdcreg[6] = val;
if ((svga->gdcreg[6] & 0xc) != (old_val & 0xc))
mach64_updatemapping(mach64);
return;
}
break;
case 0x3D4:
svga->crtcreg = val & 0x3f;
return;
case 0x3D5:
if (svga->crtcreg > 0x20)
return;
if ((svga->crtcreg < 7) && (svga->crtc[0x11] & 0x80))
return;
if ((svga->crtcreg == 7) && (svga->crtc[0x11] & 0x80))
val = (svga->crtc[7] & ~0x10) | (val & 0x10);
old = svga->crtc[svga->crtcreg];
svga->crtc[svga->crtcreg] = val;
if (old != val) {
if (svga->crtcreg < 0xe || svga->crtcreg > 0x10) {
if ((svga->crtcreg == 0xc) || (svga->crtcreg == 0xd)) {
svga->fullchange = 3;
svga->ma_latch = ((svga->crtc[0xc] << 8) | svga->crtc[0xd]) + ((svga->crtc[8] & 0x60) >> 5);
} else {
svga->fullchange = svga->monitor->mon_changeframecount;
svga_recalctimings(svga);
}
}
}
break;
default:
break;
}
svga_out(addr, val, svga);
}
uint8_t
mach64_in(uint16_t addr, void *priv)
{
mach64_t *mach64 = priv;
svga_t *svga = &mach64->svga;
if (((addr & 0xFFF0) == 0x3D0 || (addr & 0xFFF0) == 0x3B0) && !(svga->miscout & 1))
addr ^= 0x60;
switch (addr) {
case 0x1ce:
return mach64->index;
case 0x1cf:
return mach64->regs[mach64->index & 0x3f];
case 0x3C6:
case 0x3C7:
case 0x3C8:
case 0x3C9:
if (mach64->type == MACH64_GX)
return ati68860_ramdac_in((addr & 3) | ((mach64->dac_cntl & 3) << 2), svga->ramdac, svga);
return svga_in(addr, svga);
case 0x3D4:
return svga->crtcreg;
case 0x3D5:
if (svga->crtcreg > 0x20)
return 0xff;
return svga->crtc[svga->crtcreg];
default:
break;
}
return svga_in(addr, svga);
}
void
mach64_recalctimings(svga_t *svga)
{
const mach64_t *mach64 = (mach64_t *) svga->priv;
if (((mach64->crtc_gen_cntl >> 24) & 3) == 3) {
svga->vtotal = (mach64->crtc_v_total_disp & 2047) + 1;
svga->dispend = ((mach64->crtc_v_total_disp >> 16) & 2047) + 1;
svga->htotal = (mach64->crtc_h_total_disp & 255) + 1;
svga->hdisp_time = svga->hdisp = ((mach64->crtc_h_total_disp >> 16) & 255) + 1;
svga->hblankstart = (mach64->crtc_h_sync_strt_wid & 255) +
((mach64->crtc_h_sync_strt_wid >> 8) & 7);
svga->hblank_end_val = (svga->hblankstart +
((mach64->crtc_h_sync_strt_wid >> 16) & 31) - 1) & 63;
svga->vsyncstart = (mach64->crtc_v_sync_strt_wid & 2047) + 1;
svga->rowoffset = (mach64->crtc_off_pitch >> 22);
svga->clock = (cpuclock * (double) (1ULL << 32)) / ics2595_getclock(svga->clock_gen);
svga->ma_latch = (mach64->crtc_off_pitch & 0x1fffff) * 2;
svga->linedbl = svga->rowcount = 0;
svga->split = 0xffffff;
svga->vblankstart = svga->dispend;
svga->rowcount = mach64->crtc_gen_cntl & 1;
svga->rowoffset <<= 1;
if (mach64->type == MACH64_GX)
ati68860_ramdac_set_render(svga->ramdac, svga);
switch ((mach64->crtc_gen_cntl >> 8) & 7) {
case BPP_4:
if (mach64->type != MACH64_GX)
svga->render = svga_render_4bpp_highres;
svga->hdisp <<= 3;
break;
case BPP_8:
if (mach64->type != MACH64_GX)
svga->render = svga_render_8bpp_highres;
svga->hdisp <<= 3;
svga->rowoffset >>= 1;
break;
case BPP_15:
if (mach64->type != MACH64_GX)
svga->render = svga_render_15bpp_highres;
svga->hdisp <<= 3;
break;
case BPP_16:
if (mach64->type != MACH64_GX)
svga->render = svga_render_16bpp_highres;
svga->hdisp <<= 3;
break;
case BPP_24:
if (mach64->type != MACH64_GX)
svga->render = svga_render_24bpp_highres;
svga->hdisp <<= 3;
svga->rowoffset = (svga->rowoffset * 3) / 2;
break;
case BPP_32:
if (mach64->type != MACH64_GX)
svga->render = svga_render_32bpp_highres;
svga->hdisp <<= 3;
svga->rowoffset <<= 1;
break;
default:
break;
}
svga->vram_display_mask = mach64->vram_mask;
} else
svga->vram_display_mask = (mach64->regs[0x36] & 0x01) ? mach64->vram_mask : 0x3ffff;
}
void
mach64_updatemapping(mach64_t *mach64)
{
svga_t *svga = &mach64->svga;
if (mach64->pci && !(mach64->pci_regs[PCI_REG_COMMAND] & PCI_COMMAND_MEM)) {
mach64_log("Update mapping - PCI disabled\n");
mem_mapping_disable(&svga->mapping);
mem_mapping_disable(&mach64->linear_mapping);
mem_mapping_disable(&mach64->mmio_mapping);
mem_mapping_disable(&mach64->mmio_linear_mapping);
mem_mapping_disable(&mach64->mmio_linear_mapping_2);
return;
}
mem_mapping_disable(&mach64->mmio_mapping);
switch (svga->gdcreg[6] & 0xc) {
case 0x0: /*128k at A0000*/
mem_mapping_set_handler(&svga->mapping, mach64_read, mach64_readw, mach64_readl, mach64_write, mach64_writew, mach64_writel);
mem_mapping_set_p(&svga->mapping, mach64);
mem_mapping_set_addr(&svga->mapping, 0xa0000, 0x20000);
mem_mapping_enable(&mach64->mmio_mapping);
svga->banked_mask = 0xffff;
break;
case 0x4: /*64k at A0000*/
mem_mapping_set_handler(&svga->mapping, mach64_read, mach64_readw, mach64_readl, mach64_write, mach64_writew, mach64_writel);
mem_mapping_set_p(&svga->mapping, mach64);
mem_mapping_set_addr(&svga->mapping, 0xa0000, 0x10000);
svga->banked_mask = 0xffff;
break;
case 0x8: /*32k at B0000*/
mem_mapping_set_handler(&svga->mapping, svga_read, svga_readw, svga_readl, svga_write, svga_writew, svga_writel);
mem_mapping_set_p(&svga->mapping, svga);
mem_mapping_set_addr(&svga->mapping, 0xb0000, 0x08000);
svga->banked_mask = 0x7fff;
break;
case 0xC: /*32k at B8000*/
mem_mapping_set_handler(&svga->mapping, svga_read, svga_readw, svga_readl, svga_write, svga_writew, svga_writel);
mem_mapping_set_p(&svga->mapping, svga);
mem_mapping_set_addr(&svga->mapping, 0xb8000, 0x08000);
svga->banked_mask = 0x7fff;
break;
default:
break;
}
if (mach64->linear_base) {
if (mach64->type == MACH64_GX) {
if ((mach64->config_cntl & 3) == 2) {
/*8 MB aperture*/
mach64_log("Mach64 linear aperture=%08x, cfgcntl=%x, mapping=%x, VGAAP=%x.\n", mach64->linear_base + ((8 << 20) - 0x4000), mach64->config_cntl & 3, svga->gdcreg[6] & 0xc, mach64->config_cntl & 4);
mem_mapping_set_addr(&mach64->linear_mapping, mach64->linear_base, (8 << 20) - 0x4000);
mem_mapping_set_addr(&mach64->mmio_linear_mapping, mach64->linear_base + ((8 << 20) - 0x4000), 0x4000);
} else {
/*4 MB aperture*/
mem_mapping_set_addr(&mach64->linear_mapping, mach64->linear_base, (4 << 20) - 0x4000);
mem_mapping_set_addr(&mach64->mmio_linear_mapping, mach64->linear_base + ((4 << 20) - 0x4000), 0x4000);
}
} else {
/*2*8 MB aperture*/
mem_mapping_set_addr(&mach64->linear_mapping, mach64->linear_base, (8 << 20) - 0x4000);
mem_mapping_set_addr(&mach64->mmio_linear_mapping, mach64->linear_base + ((8 << 20) - 0x4000), 0x4000);
mem_mapping_set_addr(&mach64->mmio_linear_mapping_2, mach64->linear_base + ((16 << 20) - 0x4000), 0x4000);
}
} else {
mem_mapping_disable(&mach64->linear_mapping);
mem_mapping_disable(&mach64->mmio_linear_mapping);
mem_mapping_disable(&mach64->mmio_linear_mapping_2);
}
}
static void
mach64_update_irqs(mach64_t *mach64)
{
if (!mach64->pci) {
return;
}
if ((mach64->crtc_int_cntl & 0xaa0024) & ((mach64->crtc_int_cntl << 1) & 0xaa0024))
pci_set_irq(mach64->pci_slot, PCI_INTA, &mach64->irq_state);
else
pci_clear_irq(mach64->pci_slot, PCI_INTA, &mach64->irq_state);
}
#if 0
static __inline void
wake_fifo_thread(mach64_t *mach64)
{
thread_set_event(mach64->wake_fifo_thread); /*Wake up FIFO thread if moving from idle*/
}
static void
mach64_wait_fifo_idle(mach64_t *mach64)
{
while (!FIFO_EMPTY) {
wake_fifo_thread(mach64);
thread_wait_event(mach64->fifo_not_full_event, 1);
}
}
#endif
#define READ8(addr, var) \
switch ((addr) &3) { \
case 0: \
ret = (var) &0xff; \
break; \
case 1: \
ret = ((var) >> 8) & 0xff; \
break; \
case 2: \
ret = ((var) >> 16) & 0xff; \
break; \
case 3: \
ret = ((var) >> 24) & 0xff; \
break; \
}
#define WRITE8(addr, var, val) \
switch ((addr) &3) { \
case 0: \
var = (var & 0xffffff00) | (val); \
break; \
case 1: \
var = (var & 0xffff00ff) | ((val) << 8); \
break; \
case 2: \
var = (var & 0xff00ffff) | ((val) << 16); \
break; \
case 3: \
var = (var & 0x00ffffff) | ((val) << 24); \
break; \
}
static void
mach64_accel_write_fifo(mach64_t *mach64, uint32_t addr, uint8_t val)
{
switch (addr & 0x3ff) {
case 0x100:
case 0x101:
case 0x102:
case 0x103:
WRITE8(addr, mach64->dst_off_pitch, val);
break;
case 0x104:
case 0x105:
case 0x11c:
case 0x11d:
WRITE8(addr + 2, mach64->dst_y_x, val);
break;
case 0x108:
case 0x109:
WRITE8(addr, mach64->dst_y_x, val);
break;
case 0x10c:
case 0x10d:
case 0x10e:
case 0x10f:
WRITE8(addr, mach64->dst_y_x, val);
break;
case 0x110:
case 0x111:
WRITE8(addr + 2, mach64->dst_height_width, val);
break;
case 0x114:
case 0x115:
case 0x118:
case 0x119:
case 0x11a:
case 0x11b:
case 0x11e:
case 0x11f:
WRITE8(addr, mach64->dst_height_width, val);
fallthrough;
case 0x113:
if (((addr & 0x3ff) == 0x11b || (addr & 0x3ff) == 0x11f || (addr & 0x3ff) == 0x113) && !(val & 0x80)) {
mach64_start_fill(mach64);
mach64_log("%i %i %i %i %i %08x\n", (mach64->dst_height_width & 0x7ff), (mach64->dst_height_width & 0x7ff0000),
((mach64->dp_src & 7) != SRC_HOST), (((mach64->dp_src >> 8) & 7) != SRC_HOST),
(((mach64->dp_src >> 16) & 3) != MONO_SRC_HOST), mach64->dp_src);
if ((mach64->dst_height_width & 0x7ff) && (mach64->dst_height_width & 0x7ff0000) && ((mach64->dp_src & 7) != SRC_HOST) && (((mach64->dp_src >> 8) & 7) != SRC_HOST) && (((mach64->dp_src >> 16) & 3) != MONO_SRC_HOST))
mach64_blit(0, -1, mach64);
}
break;
case 0x120:
case 0x121:
case 0x122:
case 0x123:
WRITE8(addr, mach64->dst_bres_lnth, val);
if ((addr & 0x3ff) == 0x123 && !(val & 0x80)) {
mach64_start_line(mach64);
if ((mach64->dst_bres_lnth & 0x7fff) && ((mach64->dp_src & 7) != SRC_HOST) && (((mach64->dp_src >> 8) & 7) != SRC_HOST) && (((mach64->dp_src >> 16) & 3) != MONO_SRC_HOST))
mach64_blit(0, -1, mach64);
}
break;
case 0x124:
case 0x125:
case 0x126:
case 0x127:
WRITE8(addr, mach64->dst_bres_err, val);
break;
case 0x128:
case 0x129:
case 0x12a:
case 0x12b:
WRITE8(addr, mach64->dst_bres_inc, val);
break;
case 0x12c:
case 0x12d:
case 0x12e:
case 0x12f:
WRITE8(addr, mach64->dst_bres_dec, val);
break;
case 0x130:
case 0x131:
case 0x132:
case 0x133:
WRITE8(addr, mach64->dst_cntl, val);
break;
case 0x180:
case 0x181:
case 0x182:
case 0x183:
WRITE8(addr, mach64->src_off_pitch, val);
break;
case 0x184:
case 0x185:
WRITE8(addr, mach64->src_y_x, val);
break;
case 0x188:
case 0x189:
WRITE8(addr + 2, mach64->src_y_x, val);
break;
case 0x18c:
case 0x18d:
case 0x18e:
case 0x18f:
WRITE8(addr, mach64->src_y_x, val);
break;
case 0x190:
case 0x191:
WRITE8(addr + 2, mach64->src_height1_width1, val);
break;
case 0x194:
case 0x195:
WRITE8(addr, mach64->src_height1_width1, val);
break;
case 0x198:
case 0x199:
case 0x19a:
case 0x19b:
WRITE8(addr, mach64->src_height1_width1, val);
break;
case 0x19c:
case 0x19d:
WRITE8(addr, mach64->src_y_x_start, val);
break;
case 0x1a0:
case 0x1a1:
WRITE8(addr + 2, mach64->src_y_x_start, val);
break;
case 0x1a4:
case 0x1a5:
case 0x1a6:
case 0x1a7:
WRITE8(addr, mach64->src_y_x_start, val);
break;
case 0x1a8:
case 0x1a9:
WRITE8(addr + 2, mach64->src_height2_width2, val);
break;
case 0x1ac:
case 0x1ad:
WRITE8(addr, mach64->src_height2_width2, val);
break;
case 0x1b0:
case 0x1b1:
case 0x1b2:
case 0x1b3:
WRITE8(addr, mach64->src_height2_width2, val);
break;
case 0x1b4:
case 0x1b5:
case 0x1b6:
case 0x1b7:
WRITE8(addr, mach64->src_cntl, val);
break;
case 0x200:
case 0x201:
case 0x202:
case 0x203:
case 0x204:
case 0x205:
case 0x206:
case 0x207:
case 0x208:
case 0x209:
case 0x20a:
case 0x20b:
case 0x20c:
case 0x20d:
case 0x20e:
case 0x20f:
case 0x210:
case 0x211:
case 0x212:
case 0x213:
case 0x214:
case 0x215:
case 0x216:
case 0x217:
case 0x218:
case 0x219:
case 0x21a:
case 0x21b:
case 0x21c:
case 0x21d:
case 0x21e:
case 0x21f:
case 0x220:
case 0x221:
case 0x222:
case 0x223:
case 0x224:
case 0x225:
case 0x226:
case 0x227:
case 0x228:
case 0x229:
case 0x22a:
case 0x22b:
case 0x22c:
case 0x22d:
case 0x22e:
case 0x22f:
case 0x230:
case 0x231:
case 0x232:
case 0x233:
case 0x234:
case 0x235:
case 0x236:
case 0x237:
case 0x238:
case 0x239:
case 0x23a:
case 0x23b:
case 0x23c:
case 0x23d:
case 0x23e:
case 0x23f:
mach64_blit(val, 8, mach64);
break;
case 0x240:
case 0x241:
case 0x242:
case 0x243:
WRITE8(addr, mach64->host_cntl, val);
break;
case 0x280:
case 0x281:
case 0x282:
case 0x283:
WRITE8(addr, mach64->pat_reg0, val);
break;
case 0x284:
case 0x285:
case 0x286:
case 0x287:
WRITE8(addr, mach64->pat_reg1, val);
break;
case 0x288:
case 0x289:
case 0x28a:
case 0x28b:
WRITE8(addr, mach64->pat_cntl, val);
break;
case 0x2a0:
case 0x2a1:
case 0x2a8:
case 0x2a9:
WRITE8(addr, mach64->sc_left_right, val);
break;
case 0x2a4:
case 0x2a5:
addr += 2;
fallthrough;
case 0x2aa:
case 0x2ab:
WRITE8(addr, mach64->sc_left_right, val);
break;
case 0x2ac:
case 0x2ad:
case 0x2b4:
case 0x2b5:
WRITE8(addr, mach64->sc_top_bottom, val);
break;
case 0x2b0:
case 0x2b1:
addr += 2;
fallthrough;
case 0x2b6:
case 0x2b7:
WRITE8(addr, mach64->sc_top_bottom, val);
break;
case 0x2c0:
case 0x2c1:
case 0x2c2:
case 0x2c3:
WRITE8(addr, mach64->dp_bkgd_clr, val);
break;
case 0x2c4:
case 0x2c5:
case 0x2c6:
case 0x2c7:
WRITE8(addr, mach64->dp_frgd_clr, val);
break;
case 0x2c8:
case 0x2c9:
case 0x2ca:
case 0x2cb:
WRITE8(addr, mach64->write_mask, val);
break;
case 0x2cc:
case 0x2cd:
case 0x2ce:
case 0x2cf:
WRITE8(addr, mach64->chain_mask, val);
break;
case 0x2d0:
case 0x2d1:
case 0x2d2:
case 0x2d3:
WRITE8(addr, mach64->dp_pix_width, val);
break;
case 0x2d4:
case 0x2d5:
case 0x2d6:
case 0x2d7:
WRITE8(addr, mach64->dp_mix, val);
break;
case 0x2d8:
case 0x2d9:
case 0x2da:
case 0x2db:
WRITE8(addr, mach64->dp_src, val);
break;
case 0x300:
case 0x301:
case 0x302:
case 0x303:
WRITE8(addr, mach64->clr_cmp_clr, val);
break;
case 0x304:
case 0x305:
case 0x306:
case 0x307:
WRITE8(addr, mach64->clr_cmp_mask, val);
break;
case 0x308:
case 0x309:
case 0x30a:
case 0x30b:
WRITE8(addr, mach64->clr_cmp_cntl, val);
break;
case 0x320:
case 0x321:
case 0x322:
case 0x323:
WRITE8(addr, mach64->context_mask, val);
break;
case 0x330:
case 0x331:
WRITE8(addr, mach64->dst_cntl, val);
break;
case 0x332:
WRITE8(addr - 2, mach64->src_cntl, val);
break;
case 0x333:
WRITE8(addr - 3, mach64->pat_cntl, val & 7);
if (val & 0x10)
mach64->host_cntl |= HOST_BYTE_ALIGN;
else
mach64->host_cntl &= ~HOST_BYTE_ALIGN;
break;
default:
break;
}
}
static void
mach64_accel_write_fifo_w(mach64_t *mach64, uint32_t addr, uint16_t val)
{
switch (addr & 0x3fe) {
case 0x200:
case 0x202:
case 0x204:
case 0x206:
case 0x208:
case 0x20a:
case 0x20c:
case 0x20e:
case 0x210:
case 0x212:
case 0x214:
case 0x216:
case 0x218:
case 0x21a:
case 0x21c:
case 0x21e:
case 0x220:
case 0x222:
case 0x224:
case 0x226:
case 0x228:
case 0x22a:
case 0x22c:
case 0x22e:
case 0x230:
case 0x232:
case 0x234:
case 0x236:
case 0x238:
case 0x23a:
case 0x23c:
case 0x23e:
mach64_blit(val, 16, mach64);
break;
case 0x32c:
mach64->context_load_cntl = (mach64->context_load_cntl & 0xffff0000) | val;
break;
case 0x32e:
mach64->context_load_cntl = (mach64->context_load_cntl & 0x0000ffff) | (val << 16);
if (val & 0x30000)
mach64_load_context(mach64);
break;
default:
mach64_accel_write_fifo(mach64, addr, val);
mach64_accel_write_fifo(mach64, addr + 1, val >> 8);
break;
}
}
static void
mach64_accel_write_fifo_l(mach64_t *mach64, uint32_t addr, uint32_t val)
{
switch (addr & 0x3fc) {
case 0x32c:
mach64->context_load_cntl = val;
if (val & 0x30000)
mach64_load_context(mach64);
break;
case 0x200:
case 0x204:
case 0x208:
case 0x20c:
case 0x210:
case 0x214:
case 0x218:
case 0x21c:
case 0x220:
case 0x224:
case 0x228:
case 0x22c:
case 0x230:
case 0x234:
case 0x238:
case 0x23c:
if (mach64->accel.source_host || (mach64->dp_pix_width & DP_BYTE_PIX_ORDER))
mach64_blit(val, 32, mach64);
else
mach64_blit(((val & 0xff000000) >> 24) | ((val & 0x00ff0000) >> 8) | ((val & 0x0000ff00) << 8) | ((val & 0x000000ff) << 24), 32, mach64);
break;
default:
mach64_accel_write_fifo_w(mach64, addr, val);
mach64_accel_write_fifo_w(mach64, addr + 2, val >> 16);
break;
}
}
#if 0
static void
fifo_thread(void *param)
{
mach64_t *mach64 = (mach64_t *) param;
while (mach64->thread_run) {
thread_set_event(mach64->fifo_not_full_event);
thread_wait_event(mach64->wake_fifo_thread, -1);
thread_reset_event(mach64->wake_fifo_thread);
mach64->blitter_busy = 1;
while (!FIFO_EMPTY) {
uint64_t start_time = plat_timer_read();
uint64_t end_time;
fifo_entry_t *fifo = &mach64->fifo[mach64->fifo_read_idx & FIFO_MASK];
switch (fifo->addr_type & FIFO_TYPE) {
case FIFO_WRITE_BYTE:
mach64_accel_write_fifo(mach64, fifo->addr_type & FIFO_ADDR, fifo->val);
break;
case FIFO_WRITE_WORD:
mach64_accel_write_fifo_w(mach64, fifo->addr_type & FIFO_ADDR, fifo->val);
break;
case FIFO_WRITE_DWORD:
mach64_accel_write_fifo_l(mach64, fifo->addr_type & FIFO_ADDR, fifo->val);
break;
default:
break;
}
mach64->fifo_read_idx++;
fifo->addr_type = FIFO_INVALID;
if (FIFO_ENTRIES > 0xe000)
thread_set_event(mach64->fifo_not_full_event);
end_time = plat_timer_read();
mach64->blitter_time += end_time - start_time;
}
mach64->blitter_busy = 0;
}
}
static void
mach64_queue(mach64_t *mach64, uint32_t addr, uint32_t val, uint32_t type)
{
fifo_entry_t *fifo = &mach64->fifo[mach64->fifo_write_idx & FIFO_MASK];
if (FIFO_FULL) {
thread_reset_event(mach64->fifo_not_full_event);
if (FIFO_FULL) {
thread_wait_event(mach64->fifo_not_full_event, -1); /*Wait for room in ringbuffer*/
}
}
fifo->val = val;
fifo->addr_type = (addr & FIFO_ADDR) | type;
mach64->fifo_write_idx++;
if (FIFO_ENTRIES > 0xe000 || FIFO_ENTRIES < 8)
wake_fifo_thread(mach64);
}
#endif
void
mach64_start_fill(mach64_t *mach64)
{
mach64->accel.dst_x = 0;
mach64->accel.dst_y = 0;
mach64->accel.dst_x_start = (mach64->dst_y_x >> 16) & 0xfff;
if ((mach64->dst_y_x >> 16) & 0x1000)
mach64->accel.dst_x_start |= ~0xfff;
mach64->accel.dst_y_start = mach64->dst_y_x & 0x3fff;
if (mach64->dst_y_x & 0x4000)
mach64->accel.dst_y_start |= ~0x3fff;
mach64->accel.dst_width = (mach64->dst_height_width >> 16) & 0x1fff;
mach64->accel.dst_height = mach64->dst_height_width & 0x1fff;
if (((mach64->dp_src >> 16) & 7) == MONO_SRC_BLITSRC) {
if (mach64->accel.dst_width & 7)
mach64->accel.dst_width = (mach64->accel.dst_width & ~7) + 8;
}
mach64->accel.x_count = mach64->accel.dst_width;
mach64->accel.xx_count = 0;
mach64->accel.src_x = 0;
mach64->accel.src_y = 0;
mach64->accel.src_x_start = (mach64->src_y_x >> 16) & 0xfff;
if ((mach64->src_y_x >> 16) & 0x1000)
mach64->accel.src_x_start |= ~0xfff;
mach64->accel.src_y_start = mach64->src_y_x & 0x3fff;
if (mach64->src_y_x & 0x4000)
mach64->accel.src_y_start |= ~0x3fff;
if (mach64->src_cntl & SRC_LINEAR_EN)
mach64->accel.src_x_count = 0x7ffffff; /*Essentially infinite*/
else
mach64->accel.src_x_count = (mach64->src_height1_width1 >> 16) & 0x7fff;
if (!(mach64->src_cntl & SRC_PATT_EN))
mach64->accel.src_y_count = 0x7ffffff; /*Essentially infinite*/
else
mach64->accel.src_y_count = mach64->src_height1_width1 & 0x1fff;
mach64->accel.src_width1 = (mach64->src_height1_width1 >> 16) & 0x7fff;
mach64->accel.src_height1 = mach64->src_height1_width1 & 0x1fff;
mach64->accel.src_width2 = (mach64->src_height2_width2 >> 16) & 0x7fff;
mach64->accel.src_height2 = mach64->src_height2_width2 & 0x1fff;
mach64_log("src %i %i %i %i %08X %08X\n", mach64->accel.src_x_count,
mach64->accel.src_y_count,
mach64->accel.src_width1,
mach64->accel.src_height1,
mach64->src_height1_width1,
mach64->src_height2_width2);
mach64->accel.src_pitch = (mach64->src_off_pitch >> 22) << 3;
mach64->accel.src_offset = (mach64->src_off_pitch & 0xfffff) << 3;
mach64->accel.dst_pitch = (mach64->dst_off_pitch >> 22) << 3;
mach64->accel.dst_offset = (mach64->dst_off_pitch & 0xfffff) << 3;
mach64->accel.mix_fg = (mach64->dp_mix >> 16) & 0x1f;
mach64->accel.mix_bg = mach64->dp_mix & 0x1f;
mach64->accel.source_bg = mach64->dp_src & 7;
mach64->accel.source_fg = (mach64->dp_src >> 8) & 7;
mach64->accel.source_mix = (mach64->dp_src >> 16) & 7;
mach64->accel.dst_pix_width = mach64->dp_pix_width & 7;
mach64->accel.src_pix_width = (mach64->dp_pix_width >> 8) & 7;
mach64->accel.host_pix_width = (mach64->dp_pix_width >> 16) & 7;
mach64->accel.dst_size = mach64_width[mach64->accel.dst_pix_width];
mach64->accel.src_size = mach64_width[mach64->accel.src_pix_width];
mach64->accel.host_size = mach64_width[mach64->accel.host_pix_width];
if (mach64->accel.src_size == WIDTH_1BIT)
mach64->accel.src_offset <<= 3;
else
mach64->accel.src_offset >>= mach64->accel.src_size;
if (mach64->accel.dst_size == WIDTH_1BIT)
mach64->accel.dst_offset <<= 3;
else
mach64->accel.dst_offset >>= mach64->accel.dst_size;
mach64->accel.xinc = (mach64->dst_cntl & DST_X_DIR) ? 1 : -1;
mach64->accel.yinc = (mach64->dst_cntl & DST_Y_DIR) ? 1 : -1;
mach64->accel.source_host = ((mach64->dp_src & 7) == SRC_HOST) || (((mach64->dp_src >> 8) & 7) == SRC_HOST);
if (mach64->pat_cntl & 1) {
for (uint8_t y = 0; y < 8; y++) {
for (uint8_t x = 0; x < 8; x++) {
uint32_t temp = (y & 4) ? mach64->pat_reg1 : mach64->pat_reg0;
mach64->accel.pattern[y][7 - x] = (temp >> (x + ((y & 3) << 3))) & 1;
}
}
}
if (mach64->pat_cntl & 2) {
mach64->accel.pattern_clr4x2[0][0] = (mach64->pat_reg0 & 0xff);
mach64->accel.pattern_clr4x2[0][1] = ((mach64->pat_reg0 >> 8) & 0xff);
mach64->accel.pattern_clr4x2[0][2] = ((mach64->pat_reg0 >> 16) & 0xff);
mach64->accel.pattern_clr4x2[0][3] = ((mach64->pat_reg0 >> 24) & 0xff);
mach64->accel.pattern_clr4x2[1][0] = (mach64->pat_reg1 & 0xff);
mach64->accel.pattern_clr4x2[1][1] = ((mach64->pat_reg1 >> 8) & 0xff);
mach64->accel.pattern_clr4x2[1][2] = ((mach64->pat_reg1 >> 16) & 0xff);
mach64->accel.pattern_clr4x2[1][3] = ((mach64->pat_reg1 >> 24) & 0xff);
}
if (mach64->pat_cntl & 4) {
mach64->accel.pattern_clr8x1[0] = (mach64->pat_reg0 & 0xff);
mach64->accel.pattern_clr8x1[1] = ((mach64->pat_reg0 >> 8) & 0xff);
mach64->accel.pattern_clr8x1[2] = ((mach64->pat_reg0 >> 16) & 0xff);
mach64->accel.pattern_clr8x1[3] = ((mach64->pat_reg0 >> 24) & 0xff);
mach64->accel.pattern_clr8x1[4] = (mach64->pat_reg1 & 0xff);
mach64->accel.pattern_clr8x1[5] = ((mach64->pat_reg1 >> 8) & 0xff);
mach64->accel.pattern_clr8x1[6] = ((mach64->pat_reg1 >> 16) & 0xff);
mach64->accel.pattern_clr8x1[7] = ((mach64->pat_reg1 >> 24) & 0xff);
}
mach64->accel.sc_left = mach64->sc_left_right & 0x1fff;
mach64->accel.sc_right = (mach64->sc_left_right >> 16) & 0x1fff;
mach64->accel.sc_top = mach64->sc_top_bottom & 0x7fff;
mach64->accel.sc_bottom = (mach64->sc_top_bottom >> 16) & 0x7fff;
mach64->accel.dp_frgd_clr = mach64->dp_frgd_clr;
mach64->accel.dp_bkgd_clr = mach64->dp_bkgd_clr;
mach64->accel.write_mask = mach64->write_mask;
mach64->accel.clr_cmp_clr = mach64->clr_cmp_clr & mach64->clr_cmp_mask;
mach64->accel.clr_cmp_mask = mach64->clr_cmp_mask;
mach64->accel.clr_cmp_fn = mach64->clr_cmp_cntl & 7;
mach64->accel.clr_cmp_src = mach64->clr_cmp_cntl & (1 << 24);
mach64->accel.poly_draw = 0;
mach64->accel.busy = 1;
mach64_log("mach64_start_fill : dst %i, %i src %i, %i size %i, %i src pitch %i offset %X dst pitch %i offset %X scissor %i %i %i %i src_fg %i mix %02X %02X\n", mach64->accel.dst_x_start, mach64->accel.dst_y_start, mach64->accel.src_x_start, mach64->accel.src_y_start, mach64->accel.dst_width, mach64->accel.dst_height, mach64->accel.src_pitch, mach64->accel.src_offset, mach64->accel.dst_pitch, mach64->accel.dst_offset, mach64->accel.sc_left, mach64->accel.sc_right, mach64->accel.sc_top, mach64->accel.sc_bottom, mach64->accel.source_fg, mach64->accel.mix_fg, mach64->accel.mix_bg);
mach64->accel.op = OP_RECT;
}
void
mach64_start_line(mach64_t *mach64)
{
mach64->accel.dst_x = (mach64->dst_y_x >> 16) & 0xfff;
if ((mach64->dst_y_x >> 16) & 0x1000)
mach64->accel.dst_x |= ~0xfff;
mach64->accel.dst_y = mach64->dst_y_x & 0x3fff;
if (mach64->dst_y_x & 0x4000)
mach64->accel.dst_y |= ~0x3fff;
mach64->accel.src_x = (mach64->src_y_x >> 16) & 0xfff;
if ((mach64->src_y_x >> 16) & 0x1000)
mach64->accel.src_x |= ~0xfff;
mach64->accel.src_y = mach64->src_y_x & 0x3fff;
if (mach64->src_y_x & 0x4000)
mach64->accel.src_y |= ~0x3fff;
mach64->accel.src_pitch = (mach64->src_off_pitch >> 22) << 3;
mach64->accel.src_offset = (mach64->src_off_pitch & 0xfffff) << 3;
mach64->accel.dst_pitch = (mach64->dst_off_pitch >> 22) << 3;
mach64->accel.dst_offset = (mach64->dst_off_pitch & 0xfffff) << 3;
mach64->accel.mix_fg = (mach64->dp_mix >> 16) & 0x1f;
mach64->accel.mix_bg = mach64->dp_mix & 0x1f;
mach64->accel.source_bg = mach64->dp_src & 7;
mach64->accel.source_fg = (mach64->dp_src >> 8) & 7;
mach64->accel.source_mix = (mach64->dp_src >> 16) & 7;
mach64->accel.dst_pix_width = mach64->dp_pix_width & 7;
mach64->accel.src_pix_width = (mach64->dp_pix_width >> 8) & 7;
mach64->accel.host_pix_width = (mach64->dp_pix_width >> 16) & 7;
mach64->accel.dst_size = mach64_width[mach64->accel.dst_pix_width];
mach64->accel.src_size = mach64_width[mach64->accel.src_pix_width];
mach64->accel.host_size = mach64_width[mach64->accel.host_pix_width];
if (mach64->accel.src_size == WIDTH_1BIT)
mach64->accel.src_offset <<= 3;
else
mach64->accel.src_offset >>= mach64->accel.src_size;
if (mach64->accel.dst_size == WIDTH_1BIT)
mach64->accel.dst_offset <<= 3;
else
mach64->accel.dst_offset >>= mach64->accel.dst_size;
mach64->accel.source_host = ((mach64->dp_src & 7) == SRC_HOST) || (((mach64->dp_src >> 8) & 7) == SRC_HOST);
if (mach64->pat_cntl & 1) {
for (uint8_t y = 0; y < 8; y++) {
for (uint8_t x = 0; x < 8; x++) {
uint32_t temp = (y & 4) ? mach64->pat_reg1 : mach64->pat_reg0;
mach64->accel.pattern[y][7 - x] = (temp >> (x + ((y & 3) << 3))) & 1;
}
}
}
mach64->accel.sc_left = mach64->sc_left_right & 0x1fff;
mach64->accel.sc_right = (mach64->sc_left_right >> 16) & 0x1fff;
mach64->accel.sc_top = mach64->sc_top_bottom & 0x7fff;
mach64->accel.sc_bottom = (mach64->sc_top_bottom >> 16) & 0x7fff;
mach64->accel.dp_frgd_clr = mach64->dp_frgd_clr;
mach64->accel.dp_bkgd_clr = mach64->dp_bkgd_clr;
mach64->accel.write_mask = mach64->write_mask;
mach64->accel.x_count = mach64->dst_bres_lnth & 0x7fff;
mach64->accel.err = (mach64->dst_bres_err & 0x3ffff) | ((mach64->dst_bres_err & 0x40000) ? 0xfffc0000 : 0);
mach64->accel.clr_cmp_clr = mach64->clr_cmp_clr & mach64->clr_cmp_mask;
mach64->accel.clr_cmp_mask = mach64->clr_cmp_mask;
mach64->accel.clr_cmp_fn = mach64->clr_cmp_cntl & 7;
mach64->accel.clr_cmp_src = mach64->clr_cmp_cntl & (1 << 24);
mach64->accel.xinc = (mach64->dst_cntl & DST_X_DIR) ? 1 : -1;
mach64->accel.yinc = (mach64->dst_cntl & DST_Y_DIR) ? 1 : -1;
mach64->accel.busy = 1;
mach64_log("mach64_start_line\n");
mach64->accel.op = OP_LINE;
}
#define READ(addr, dat, width) \
if (width == 0) \
dat = svga->vram[((addr)) & mach64->vram_mask]; \
else if (width == 1) \
dat = *(uint16_t *) &svga->vram[((addr) << 1) & mach64->vram_mask]; \
else if (width == 2) \
dat = *(uint32_t *) &svga->vram[((addr) << 2) & mach64->vram_mask]; \
else if (mach64->dp_pix_width & DP_BYTE_PIX_ORDER) \
dat = (svga->vram[((addr) >> 3) & mach64->vram_mask] >> ((addr) &7)) & 1; \
else \
dat = (svga->vram[((addr) >> 3) & mach64->vram_mask] >> (7 - ((addr) &7))) & 1;
#define MIX \
switch (mix ? mach64->accel.mix_fg : mach64->accel.mix_bg) { \
case 0x0: \
dest_dat = ~dest_dat; \
break; \
case 0x1: \
dest_dat = 0; \
break; \
case 0x2: \
dest_dat = 0xffffffff; \
break; \
case 0x3: \
dest_dat = dest_dat; \
break; \
case 0x4: \
dest_dat = ~src_dat; \
break; \
case 0x5: \
dest_dat = src_dat ^ dest_dat; \
break; \
case 0x6: \
dest_dat = ~(src_dat ^ dest_dat); \
break; \
case 0x7: \
dest_dat = src_dat; \
break; \
case 0x8: \
dest_dat = ~(src_dat & dest_dat); \
break; \
case 0x9: \
dest_dat = ~src_dat | dest_dat; \
break; \
case 0xa: \
dest_dat = src_dat | ~dest_dat; \
break; \
case 0xb: \
dest_dat = src_dat | dest_dat; \
break; \
case 0xc: \
dest_dat = src_dat & dest_dat; \
break; \
case 0xd: \
dest_dat = src_dat & ~dest_dat; \
break; \
case 0xe: \
dest_dat = ~src_dat & dest_dat; \
break; \
case 0xf: \
dest_dat = ~(src_dat | dest_dat); \
break; \
case 0x17: \
dest_dat = (dest_dat + src_dat) >> 1; \
break; \
}
#define WRITE(addr, width) \
if (width == 0) { \
svga->vram[(addr) &mach64->vram_mask] = dest_dat; \
svga->changedvram[((addr) &mach64->vram_mask) >> 12] = svga->monitor->mon_changeframecount; \
} else if (width == 1) { \
*(uint16_t *) &svga->vram[((addr) << 1) & mach64->vram_mask] = dest_dat; \
svga->changedvram[(((addr) << 1) & mach64->vram_mask) >> 12] = svga->monitor->mon_changeframecount; \
} else if (width == 2) { \
*(uint32_t *) &svga->vram[((addr) << 2) & mach64->vram_mask] = dest_dat; \
svga->changedvram[(((addr) << 2) & mach64->vram_mask) >> 12] = svga->monitor->mon_changeframecount; \
} else { \
if (dest_dat & 1) { \
if (mach64->dp_pix_width & DP_BYTE_PIX_ORDER) \
svga->vram[((addr) >> 3) & mach64->vram_mask] |= 1 << ((addr) &7); \
else \
svga->vram[((addr) >> 3) & mach64->vram_mask] |= 1 << (7 - ((addr) &7)); \
} else { \
if (mach64->dp_pix_width & DP_BYTE_PIX_ORDER) \
svga->vram[((addr) >> 3) & mach64->vram_mask] &= ~(1 << ((addr) &7)); \
else \
svga->vram[((addr) >> 3) & mach64->vram_mask] &= ~(1 << (7 - ((addr) &7))); \
} \
svga->changedvram[(((addr) >> 3) & mach64->vram_mask) >> 12] = svga->monitor->mon_changeframecount; \
}
void
mach64_blit(uint32_t cpu_dat, int count, mach64_t *mach64)
{
svga_t *svga = &mach64->svga;
int cmp_clr = 0;
int mix = 0;
if (!mach64->accel.busy) {
mach64_log("mach64_blit : return as not busy\n");
return;
}
switch (mach64->accel.op) {
case OP_RECT:
while (count) {
uint8_t write_mask = 0;
uint32_t src_dat = 0;
uint32_t dest_dat;
uint32_t host_dat = 0;
uint32_t old_dest_dat;
int dst_x;
int dst_y;
int src_x;
int src_y;
dst_x = (mach64->accel.dst_x + mach64->accel.dst_x_start) & 0xfff;
dst_y = (mach64->accel.dst_y + mach64->accel.dst_y_start) & 0x3fff;
if (mach64->src_cntl & SRC_LINEAR_EN)
src_x = mach64->accel.src_x;
else
src_x = (mach64->accel.src_x + mach64->accel.src_x_start) & 0xfff;
src_y = (mach64->accel.src_y + mach64->accel.src_y_start) & 0x3fff;
if (mach64->accel.source_host) {
host_dat = cpu_dat;
switch (mach64->accel.host_size) {
case 0:
cpu_dat >>= 8;
count -= 8;
break;
case 1:
cpu_dat >>= 16;
count -= 16;
break;
case 2:
count -= 32;
break;
default:
break;
}
} else
count--;
switch (mach64->accel.source_mix) {
case MONO_SRC_HOST:
if (mach64->dp_pix_width & DP_BYTE_PIX_ORDER) {
mix = cpu_dat & 1;
cpu_dat >>= 1;
} else {
mix = cpu_dat >> 0x1f;
cpu_dat <<= 1;
}
break;
case MONO_SRC_PAT:
if (mach64->dst_cntl & DST_24_ROT_EN) {
if (!mach64->accel.xx_count)
mix = mach64->accel.pattern[dst_y & 7][dst_x & 7];
} else
mix = mach64->accel.pattern[dst_y & 7][dst_x & 7];
break;
case MONO_SRC_1:
mix = 1;
break;
case MONO_SRC_BLITSRC:
if (mach64->src_cntl & SRC_LINEAR_EN) {
READ(mach64->accel.src_offset + src_x, mix, WIDTH_1BIT);
} else {
READ(mach64->accel.src_offset + (src_y * mach64->accel.src_pitch) + src_x, mix, WIDTH_1BIT);
}
break;
default:
break;
}
if (dst_x >= mach64->accel.sc_left && dst_x <= mach64->accel.sc_right && dst_y >= mach64->accel.sc_top && dst_y <= mach64->accel.sc_bottom) {
switch (mix ? mach64->accel.source_fg : mach64->accel.source_bg) {
case SRC_HOST:
src_dat = host_dat;
break;
case SRC_BLITSRC:
READ(mach64->accel.src_offset + (src_y * mach64->accel.src_pitch) + src_x, src_dat, mach64->accel.src_size);
break;
case SRC_FG:
if (mach64->dst_cntl & DST_24_ROT_EN) {
if (mach64->accel.xinc == -1) {
if (mach64->accel.xx_count == 2)
src_dat = mach64->accel.dp_frgd_clr & 0xff;
else if (mach64->accel.xx_count == 1)
src_dat = (mach64->accel.dp_frgd_clr >> 8) & 0xff;
else
src_dat = (mach64->accel.dp_frgd_clr >> 16) & 0xff;
} else {
if (mach64->accel.xx_count == 2)
src_dat = (mach64->accel.dp_frgd_clr >> 16) & 0xff;
else if (mach64->accel.xx_count == 1)
src_dat = (mach64->accel.dp_frgd_clr >> 8) & 0xff;
else
src_dat = mach64->accel.dp_frgd_clr & 0xff;
}
} else
src_dat = mach64->accel.dp_frgd_clr;
break;
case SRC_BG:
if (mach64->dst_cntl & DST_24_ROT_EN) {
if (mach64->accel.xinc == -1) {
if (mach64->accel.xx_count == 2)
src_dat = mach64->accel.dp_bkgd_clr & 0xff;
else if (mach64->accel.xx_count == 1)
src_dat = (mach64->accel.dp_bkgd_clr >> 8) & 0xff;
else
src_dat = (mach64->accel.dp_bkgd_clr >> 16) & 0xff;
} else {
if (mach64->accel.xx_count == 2)
src_dat = (mach64->accel.dp_bkgd_clr >> 16) & 0xff;
else if (mach64->accel.xx_count == 1)
src_dat = (mach64->accel.dp_bkgd_clr >> 8) & 0xff;
else
src_dat = mach64->accel.dp_bkgd_clr & 0xff;
}
} else
src_dat = mach64->accel.dp_bkgd_clr;
break;
case SRC_PAT:
if (mach64->pat_cntl & 2) {
src_dat = mach64->accel.pattern_clr4x2[dst_y & 1][dst_x & 3];
break;
} else if (mach64->pat_cntl & 4) {
src_dat = mach64->accel.pattern_clr8x1[dst_x & 7];
break;
}
default:
src_dat = 0;
break;
}
if (mach64->dst_cntl & DST_POLYGON_EN) {
int poly_src;
READ(mach64->accel.src_offset + (src_y * mach64->accel.src_pitch) + src_x, poly_src, mach64->accel.src_size);
if (poly_src)
mach64->accel.poly_draw = !mach64->accel.poly_draw;
}
if (!(mach64->dst_cntl & DST_POLYGON_EN) || mach64->accel.poly_draw) {
READ(mach64->accel.dst_offset + ((dst_y) *mach64->accel.dst_pitch) + (dst_x), dest_dat, mach64->accel.dst_size);
switch (mach64->accel.clr_cmp_fn) {
case 1: /*TRUE*/
cmp_clr = 1;
break;
case 4: /*DST_CLR != CLR_CMP_CLR*/
cmp_clr = (((mach64->accel.clr_cmp_src) ? src_dat : dest_dat) & mach64->accel.clr_cmp_mask) != mach64->accel.clr_cmp_clr;
break;
case 5: /*DST_CLR == CLR_CMP_CLR*/
cmp_clr = (((mach64->accel.clr_cmp_src) ? src_dat : dest_dat) & mach64->accel.clr_cmp_mask) == mach64->accel.clr_cmp_clr;
break;
default:
break;
}
if (!cmp_clr) {
old_dest_dat = dest_dat;
MIX
if (mach64->dst_cntl & DST_24_ROT_EN) {
if (mach64->accel.xinc == -1) {
if (mach64->accel.xx_count == 2)
write_mask = mach64->accel.write_mask & 0xff;
else if (mach64->accel.xx_count == 1)
write_mask = (mach64->accel.write_mask >> 8) & 0xff;
else
write_mask = (mach64->accel.write_mask >> 16) & 0xff;
} else {
if (mach64->accel.xx_count == 2)
write_mask = (mach64->accel.write_mask >> 16) & 0xff;
else if (mach64->accel.xx_count == 1)
write_mask = (mach64->accel.write_mask >> 8) & 0xff;
else
write_mask = mach64->accel.write_mask & 0xff;
}
dest_dat = (dest_dat & write_mask) | (old_dest_dat & ~write_mask);
} else
dest_dat = (dest_dat & mach64->accel.write_mask) | (old_dest_dat & ~mach64->accel.write_mask);
}
WRITE(mach64->accel.dst_offset + ((dst_y) * mach64->accel.dst_pitch) + (dst_x), mach64->accel.dst_size);
}
}
mach64->accel.src_x += mach64->accel.xinc;
mach64->accel.dst_x += mach64->accel.xinc;
if (!(mach64->src_cntl & SRC_LINEAR_EN)) {
mach64->accel.src_x_count--;
if (mach64->accel.src_x_count <= 0) {
mach64->accel.src_x = 0;
if ((mach64->src_cntl & (SRC_PATT_ROT_EN | SRC_PATT_EN)) == (SRC_PATT_ROT_EN | SRC_PATT_EN)) {
mach64->accel.src_x_start = (mach64->src_y_x_start >> 16) & 0xfff;
if ((mach64->src_y_x_start >> 16) & 0x1000)
mach64->accel.src_x_start |= ~0xfff;
mach64->accel.src_x_count = mach64->accel.src_width2;
} else
mach64->accel.src_x_count = mach64->accel.src_width1;
}
}
mach64->accel.x_count--;
mach64->accel.xx_count = (mach64->accel.xx_count + 1) % 3;
if (mach64->accel.x_count <= 0) {
mach64->accel.x_count = mach64->accel.dst_width;
mach64->accel.xx_count = 0;
mach64->accel.dst_x = 0;
mach64->accel.dst_y += mach64->accel.yinc;
mach64->accel.src_x_start = (mach64->src_y_x >> 16) & 0xfff;
mach64->accel.src_x_count = mach64->accel.src_width1;
if (!(mach64->src_cntl & SRC_LINEAR_EN)) {
mach64->accel.src_x = 0;
mach64->accel.src_y += mach64->accel.yinc;
mach64->accel.src_y_count--;
if (mach64->accel.src_y_count <= 0) {
mach64->accel.src_y = 0;
if ((mach64->src_cntl & (SRC_PATT_ROT_EN | SRC_PATT_EN)) == (SRC_PATT_ROT_EN | SRC_PATT_EN)) {
mach64->accel.src_y_start = mach64->src_y_x_start & 0x3fff;
if (mach64->src_y_x_start & 0x4000)
mach64->accel.src_y_start |= ~0x3fff;
mach64->accel.src_y_count = mach64->accel.src_height2;
} else
mach64->accel.src_y_count = mach64->accel.src_height1;
}
}
mach64->accel.poly_draw = 0;
mach64->accel.dst_height--;
if (mach64->accel.dst_height <= 0) {
/*Blit finished*/
mach64_log("mach64 blit finished\n");
mach64->accel.busy = 0;
if (mach64->dst_cntl & DST_X_TILE)
mach64->dst_y_x = (mach64->dst_y_x & 0xfff) | ((mach64->dst_y_x + (mach64->accel.dst_width << 16)) & 0xfff0000);
if (mach64->dst_cntl & DST_Y_TILE)
mach64->dst_y_x = (mach64->dst_y_x & 0xfff0000) | ((mach64->dst_y_x + (mach64->dst_height_width & 0x1fff)) & 0xfff);
return;
}
if (mach64->host_cntl & HOST_BYTE_ALIGN) {
if (mach64->accel.source_mix == MONO_SRC_HOST) {
if (mach64->dp_pix_width & DP_BYTE_PIX_ORDER)
cpu_dat >>= (count & 7);
else
cpu_dat <<= (count & 7);
count &= ~7;
}
}
}
}
break;
case OP_LINE:
if (((mach64->crtc_gen_cntl >> 8) & 7) == BPP_24) {
int x = 0;
while (count) {
uint32_t src_dat = 0;
uint32_t dest_dat;
uint32_t host_dat = 0;
int mix = 0;
if (mach64->accel.source_host) {
host_dat = cpu_dat;
switch (mach64->accel.host_size) {
case 0:
cpu_dat >>= 8;
count -= 8;
break;
case 1:
cpu_dat >>= 16;
count -= 16;
break;
case 2:
count -= 32;
break;
default:
break;
}
} else
count--;
switch (mach64->accel.source_mix) {
case MONO_SRC_HOST:
if (mach64->dp_pix_width & DP_BYTE_PIX_ORDER) {
mix = cpu_dat & 1;
cpu_dat >>= 1;
} else {
mix = cpu_dat >> 31;
cpu_dat <<= 1;
}
break;
case MONO_SRC_PAT:
mix = mach64->accel.pattern[mach64->accel.dst_y & 7][mach64->accel.dst_x & 7];
break;
case MONO_SRC_1:
mix = 1;
break;
case MONO_SRC_BLITSRC:
READ(mach64->accel.src_offset + (mach64->accel.src_y * mach64->accel.src_pitch) + mach64->accel.src_x, mix, WIDTH_1BIT);
break;
default:
break;
}
if ((mach64->accel.dst_x >= mach64->accel.sc_left) && (mach64->accel.dst_x <= mach64->accel.sc_right) && (mach64->accel.dst_y >= mach64->accel.sc_top) && (mach64->accel.dst_y <= mach64->accel.sc_bottom)) {
switch (mix ? mach64->accel.source_fg : mach64->accel.source_bg) {
case SRC_HOST:
src_dat = host_dat;
break;
case SRC_BLITSRC:
READ(mach64->accel.src_offset + (mach64->accel.src_y * mach64->accel.src_pitch) + mach64->accel.src_x, src_dat, mach64->accel.src_size);
break;
case SRC_FG:
src_dat = mach64->accel.dp_frgd_clr;
break;
case SRC_BG:
src_dat = mach64->accel.dp_bkgd_clr;
break;
case SRC_PAT:
if (mach64->pat_cntl & 2) {
src_dat = mach64->accel.pattern_clr4x2[mach64->accel.dst_y & 1][mach64->accel.dst_x & 3];
break;
} else if (mach64->pat_cntl & 4) {
src_dat = mach64->accel.pattern_clr8x1[mach64->accel.dst_x & 7];
break;
}
default:
src_dat = 0;
break;
}
READ(mach64->accel.dst_offset + (mach64->accel.dst_y * mach64->accel.dst_pitch) + mach64->accel.dst_x, dest_dat, mach64->accel.dst_size);
switch (mach64->accel.clr_cmp_fn) {
case 1: /*TRUE*/
cmp_clr = 1;
break;
case 4: /*DST_CLR != CLR_CMP_CLR*/
cmp_clr = (((mach64->accel.clr_cmp_src) ? src_dat : dest_dat) & mach64->accel.clr_cmp_mask) != mach64->accel.clr_cmp_clr;
break;
case 5: /*DST_CLR == CLR_CMP_CLR*/
cmp_clr = (((mach64->accel.clr_cmp_src) ? src_dat : dest_dat) & mach64->accel.clr_cmp_mask) == mach64->accel.clr_cmp_clr;
break;
default:
break;
}
if (!cmp_clr)
MIX
if (!(mach64->dst_cntl & DST_Y_MAJOR)) {
if (!x)
dest_dat &= ~1;
} else {
if (x == (mach64->accel.x_count - 1))
dest_dat &= ~1;
}
WRITE(mach64->accel.dst_offset + (mach64->accel.dst_y * mach64->accel.dst_pitch) + mach64->accel.dst_x, mach64->accel.dst_size);
}
x++;
if (x >= mach64->accel.x_count) {
mach64->accel.busy = 0;
mach64_log("mach64 line24 finished\n");
return;
}
if (mach64->dst_cntl & DST_Y_MAJOR) {
mach64->accel.dst_y += mach64->accel.yinc;
if (mach64->accel.err >= 0) {
mach64->accel.err += mach64->dst_bres_dec;
mach64->accel.dst_x += mach64->accel.xinc;
} else {
mach64->accel.err += mach64->dst_bres_inc;
}
} else {
mach64->accel.dst_x += mach64->accel.xinc;
if (mach64->accel.err >= 0) {
mach64->accel.err += mach64->dst_bres_dec;
mach64->accel.dst_y += mach64->accel.yinc;
} else {
mach64->accel.err += mach64->dst_bres_inc;
}
}
}
} else {
while (count) {
uint32_t src_dat = 0;
uint32_t dest_dat;
uint32_t host_dat = 0;
int mix = 0;
int draw_pixel = !(mach64->dst_cntl & DST_POLYGON_EN);
if (mach64->accel.source_host) {
host_dat = cpu_dat;
switch (mach64->accel.host_size) {
case 0:
cpu_dat >>= 8;
count -= 8;
break;
case 1:
cpu_dat >>= 16;
count -= 16;
break;
case 2:
count -= 32;
break;
default:
break;
}
} else
count--;
switch (mach64->accel.source_mix) {
case MONO_SRC_HOST:
mix = cpu_dat >> 31;
cpu_dat <<= 1;
break;
case MONO_SRC_PAT:
mix = mach64->accel.pattern[mach64->accel.dst_y & 7][mach64->accel.dst_x & 7];
break;
case MONO_SRC_1:
default:
mix = 1;
break;
}
if (mach64->dst_cntl & DST_POLYGON_EN) {
if (mach64->dst_cntl & DST_Y_MAJOR)
draw_pixel = 1;
else if ((mach64->dst_cntl & DST_X_DIR) && mach64->accel.err < (mach64->dst_bres_dec + mach64->dst_bres_inc)) /*X+*/
draw_pixel = 1;
else if (!(mach64->dst_cntl & DST_X_DIR) && mach64->accel.err >= 0) /*X-*/
draw_pixel = 1;
}
if (mach64->accel.x_count == 1 && !(mach64->dst_cntl & DST_LAST_PEL))
draw_pixel = 0;
if (mach64->accel.dst_x >= mach64->accel.sc_left && mach64->accel.dst_x <= mach64->accel.sc_right && mach64->accel.dst_y >= mach64->accel.sc_top && mach64->accel.dst_y <= mach64->accel.sc_bottom && draw_pixel) {
switch (mix ? mach64->accel.source_fg : mach64->accel.source_bg) {
case SRC_HOST:
src_dat = host_dat;
break;
case SRC_BLITSRC:
READ(mach64->accel.src_offset + (mach64->accel.src_y * mach64->accel.src_pitch) + mach64->accel.src_x, src_dat, mach64->accel.src_size);
break;
case SRC_FG:
src_dat = mach64->accel.dp_frgd_clr;
break;
case SRC_BG:
src_dat = mach64->accel.dp_bkgd_clr;
break;
default:
src_dat = 0;
break;
}
READ(mach64->accel.dst_offset + (mach64->accel.dst_y * mach64->accel.dst_pitch) + mach64->accel.dst_x, dest_dat, mach64->accel.dst_size);
switch (mach64->accel.clr_cmp_fn) {
case 1: /*TRUE*/
cmp_clr = 1;
break;
case 4: /*DST_CLR != CLR_CMP_CLR*/
cmp_clr = (((mach64->accel.clr_cmp_src) ? src_dat : dest_dat) & mach64->accel.clr_cmp_mask) != mach64->accel.clr_cmp_clr;
break;
case 5: /*DST_CLR == CLR_CMP_CLR*/
cmp_clr = (((mach64->accel.clr_cmp_src) ? src_dat : dest_dat) & mach64->accel.clr_cmp_mask) == mach64->accel.clr_cmp_clr;
break;
default:
break;
}
if (!cmp_clr)
MIX
WRITE(mach64->accel.dst_offset + (mach64->accel.dst_y * mach64->accel.dst_pitch) + mach64->accel.dst_x, mach64->accel.dst_size);
}
mach64->accel.x_count--;
if (mach64->accel.x_count <= 0) {
/*Blit finished*/
mach64_log("mach64 blit finished\n");
mach64->accel.busy = 0;
return;
}
switch (mach64->dst_cntl & 7) {
case 0:
case 2:
mach64->accel.src_x--;
mach64->accel.dst_x--;
break;
case 1:
case 3:
mach64->accel.src_x++;
mach64->accel.dst_x++;
break;
case 4:
case 5:
mach64->accel.src_y--;
mach64->accel.dst_y--;
break;
case 6:
case 7:
mach64->accel.src_y++;
mach64->accel.dst_y++;
break;
default:
break;
}
mach64_log("x %i y %i err %i inc %i dec %i\n", mach64->accel.dst_x, mach64->accel.dst_y, mach64->accel.err, mach64->dst_bres_inc, mach64->dst_bres_dec);
if (mach64->accel.err >= 0) {
mach64->accel.err += mach64->dst_bres_dec;
switch (mach64->dst_cntl & 7) {
case 0:
case 1:
mach64->accel.src_y--;
mach64->accel.dst_y--;
break;
case 2:
case 3:
mach64->accel.src_y++;
mach64->accel.dst_y++;
break;
case 4:
case 6:
mach64->accel.src_x--;
mach64->accel.dst_x--;
break;
case 5:
case 7:
mach64->accel.src_x++;
mach64->accel.dst_x++;
break;
default:
break;
}
} else
mach64->accel.err += mach64->dst_bres_inc;
}
}
break;
default:
break;
}
}
void
mach64_load_context(mach64_t *mach64)
{
svga_t *svga = &mach64->svga;
uint32_t addr;
while (mach64->context_load_cntl & 0x30000) {
addr = ((0x3fff - (mach64->context_load_cntl & 0x3fff)) * 256) & mach64->vram_mask;
mach64->context_mask = *(uint32_t *) &svga->vram[addr];
mach64_log("mach64_load_context %08X from %08X : mask %08X\n", mach64->context_load_cntl, addr, mach64->context_mask);
if (mach64->context_mask & (1 << 2))
mach64_accel_write_fifo_l(mach64, 0x100, *(uint32_t *) &svga->vram[addr + 0x08]);
if (mach64->context_mask & (1 << 3))
mach64_accel_write_fifo_l(mach64, 0x10c, *(uint32_t *) &svga->vram[addr + 0x0c]);
if (mach64->context_mask & (1 << 4))
mach64_accel_write_fifo_l(mach64, 0x118, *(uint32_t *) &svga->vram[addr + 0x10]);
if (mach64->context_mask & (1 << 5))
mach64_accel_write_fifo_l(mach64, 0x124, *(uint32_t *) &svga->vram[addr + 0x14]);
if (mach64->context_mask & (1 << 6))
mach64_accel_write_fifo_l(mach64, 0x128, *(uint32_t *) &svga->vram[addr + 0x18]);
if (mach64->context_mask & (1 << 7))
mach64_accel_write_fifo_l(mach64, 0x12c, *(uint32_t *) &svga->vram[addr + 0x1c]);
if (mach64->context_mask & (1 << 8))
mach64_accel_write_fifo_l(mach64, 0x180, *(uint32_t *) &svga->vram[addr + 0x20]);
if (mach64->context_mask & (1 << 9))
mach64_accel_write_fifo_l(mach64, 0x18c, *(uint32_t *) &svga->vram[addr + 0x24]);
if (mach64->context_mask & (1 << 10))
mach64_accel_write_fifo_l(mach64, 0x198, *(uint32_t *) &svga->vram[addr + 0x28]);
if (mach64->context_mask & (1 << 11))
mach64_accel_write_fifo_l(mach64, 0x1a4, *(uint32_t *) &svga->vram[addr + 0x2c]);
if (mach64->context_mask & (1 << 12))
mach64_accel_write_fifo_l(mach64, 0x1b0, *(uint32_t *) &svga->vram[addr + 0x30]);
if (mach64->context_mask & (1 << 13))
mach64_accel_write_fifo_l(mach64, 0x280, *(uint32_t *) &svga->vram[addr + 0x34]);
if (mach64->context_mask & (1 << 14))
mach64_accel_write_fifo_l(mach64, 0x284, *(uint32_t *) &svga->vram[addr + 0x38]);
if (mach64->context_mask & (1 << 15))
mach64_accel_write_fifo_l(mach64, 0x2a8, *(uint32_t *) &svga->vram[addr + 0x3c]);
if (mach64->context_mask & (1 << 16))
mach64_accel_write_fifo_l(mach64, 0x2b4, *(uint32_t *) &svga->vram[addr + 0x40]);
if (mach64->context_mask & (1 << 17))
mach64_accel_write_fifo_l(mach64, 0x2c0, *(uint32_t *) &svga->vram[addr + 0x44]);
if (mach64->context_mask & (1 << 18))
mach64_accel_write_fifo_l(mach64, 0x2c4, *(uint32_t *) &svga->vram[addr + 0x48]);
if (mach64->context_mask & (1 << 19))
mach64_accel_write_fifo_l(mach64, 0x2c8, *(uint32_t *) &svga->vram[addr + 0x4c]);
if (mach64->context_mask & (1 << 20))
mach64_accel_write_fifo_l(mach64, 0x2cc, *(uint32_t *) &svga->vram[addr + 0x50]);
if (mach64->context_mask & (1 << 21))
mach64_accel_write_fifo_l(mach64, 0x2d0, *(uint32_t *) &svga->vram[addr + 0x54]);
if (mach64->context_mask & (1 << 22))
mach64_accel_write_fifo_l(mach64, 0x2d4, *(uint32_t *) &svga->vram[addr + 0x58]);
if (mach64->context_mask & (1 << 23))
mach64_accel_write_fifo_l(mach64, 0x2d8, *(uint32_t *) &svga->vram[addr + 0x5c]);
if (mach64->context_mask & (1 << 24))
mach64_accel_write_fifo_l(mach64, 0x300, *(uint32_t *) &svga->vram[addr + 0x60]);
if (mach64->context_mask & (1 << 25))
mach64_accel_write_fifo_l(mach64, 0x304, *(uint32_t *) &svga->vram[addr + 0x64]);
if (mach64->context_mask & (1 << 26))
mach64_accel_write_fifo_l(mach64, 0x308, *(uint32_t *) &svga->vram[addr + 0x68]);
if (mach64->context_mask & (1 << 27))
mach64_accel_write_fifo_l(mach64, 0x330, *(uint32_t *) &svga->vram[addr + 0x6c]);
mach64->context_load_cntl = *(uint32_t *) &svga->vram[addr + 0x70];
}
}
#define PLL_REF_DIV 0x2
#define VCLK_POST_DIV 0x6
#define VCLK0_FB_DIV 0x7
static void
pll_write(mach64_t *mach64, uint32_t addr, uint8_t val)
{
switch (addr & 3) {
case 0: /*Clock sel*/
break;
case 1: /*Addr*/
mach64->pll_addr = (val >> 2) & 0xf;
break;
case 2: /*Data*/
mach64->pll_regs[mach64->pll_addr] = val;
mach64_log("pll_write %02x,%02x\n", mach64->pll_addr, val);
for (uint8_t c = 0; c < 4; c++) {
double m = (double) mach64->pll_regs[PLL_REF_DIV];
double n = (double) mach64->pll_regs[VCLK0_FB_DIV + c];
double r = 14318184.0;
double p = (double) (1 << ((mach64->pll_regs[VCLK_POST_DIV] >> (c * 2)) & 3));
mach64_log("PLLfreq %i = %g %g m=%02x n=%02x p=%02x\n", c, (2.0 * r * n) / (m * p), p, mach64->pll_regs[PLL_REF_DIV], mach64->pll_regs[VCLK0_FB_DIV + c], mach64->pll_regs[VCLK_POST_DIV]);
mach64->pll_freq[c] = (2.0 * r * n) / (m * p);
mach64_log(" %g\n", mach64->pll_freq[c]);
}
break;
default:
break;
}
}
#define OVERLAY_EN (1 << 30)
static void
mach64_vblank_start(svga_t *svga)
{
mach64_t *mach64 = (mach64_t *) svga->priv;
int overlay_cmp_mix = (mach64->overlay_key_cntl >> 8) & 0xf;
mach64->crtc_int_cntl |= 4;
mach64_update_irqs(mach64);
svga->overlay.x = (mach64->overlay_y_x_start >> 16) & 0x7ff;
svga->overlay.y = mach64->overlay_y_x_start & 0x7ff;
svga->overlay.cur_xsize = ((mach64->overlay_y_x_end >> 16) & 0x7ff) - svga->overlay.x;
svga->overlay.cur_ysize = (mach64->overlay_y_x_end & 0x7ff) - svga->overlay.y;
svga->overlay.addr = mach64->buf_offset[0] & 0x3ffff8;
svga->overlay.pitch = mach64->buf_pitch[0] & 0xfff;
svga->overlay.ena = (mach64->overlay_scale_cntl & OVERLAY_EN) && (overlay_cmp_mix != 1);
mach64->overlay_v_acc = 0;
mach64->scaler_update = 1;
}
uint8_t
mach64_ext_readb(uint32_t addr, void *priv)
{
mach64_t *mach64 = (mach64_t *) priv;
uint8_t ret = 0xff;
if (!(addr & 0x400)) {
mach64_log("nmach64_ext_readb: addr=%04x\n", addr);
switch (addr & 0x3ff) {
case 0x00:
case 0x01:
case 0x02:
case 0x03:
READ8(addr, mach64->overlay_y_x_start);
break;
case 0x04:
case 0x05:
case 0x06:
case 0x07:
READ8(addr, mach64->overlay_y_x_end);
break;
case 0x08:
case 0x09:
case 0x0a:
case 0x0b:
READ8(addr, mach64->overlay_video_key_clr);
break;
case 0x0c:
case 0x0d:
case 0x0e:
case 0x0f:
READ8(addr, mach64->overlay_video_key_msk);
break;
case 0x10:
case 0x11:
case 0x12:
case 0x13:
READ8(addr, mach64->overlay_graphics_key_clr);
break;
case 0x14:
case 0x15:
case 0x16:
case 0x17:
READ8(addr, mach64->overlay_graphics_key_msk);
break;
case 0x18:
case 0x19:
case 0x1a:
case 0x1b:
READ8(addr, mach64->overlay_key_cntl);
break;
case 0x20:
case 0x21:
case 0x22:
case 0x23:
READ8(addr, mach64->overlay_scale_inc);
break;
case 0x24:
case 0x25:
case 0x26:
case 0x27:
READ8(addr, mach64->overlay_scale_cntl);
break;
case 0x28:
case 0x29:
case 0x2a:
case 0x2b:
READ8(addr, mach64->scaler_height_width);
break;
case 0x4a:
ret = mach64->scaler_format;
break;
default:
ret = 0xff;
break;
}
} else {
switch (addr & 0x3ff) {
case 0x00:
case 0x01:
case 0x02:
case 0x03:
READ8(addr, mach64->crtc_h_total_disp);
break;
case 0x04:
case 0x05:
case 0x06:
case 0x07:
READ8(addr, mach64->crtc_h_sync_strt_wid);
break;
case 0x08:
case 0x09:
case 0x0a:
case 0x0b:
READ8(addr, mach64->crtc_v_total_disp);
break;
case 0x0c:
case 0x0d:
case 0x0e:
case 0x0f:
READ8(addr, mach64->crtc_v_sync_strt_wid);
break;
case 0x12:
case 0x13:
READ8(addr - 2, mach64->svga.vc);
break;
case 0x14:
case 0x15:
case 0x16:
case 0x17:
READ8(addr, mach64->crtc_off_pitch);
break;
case 0x18:
ret = mach64->crtc_int_cntl & ~1;
if (mach64->svga.cgastat & 8)
ret |= 1;
break;
case 0x1c:
case 0x1d:
case 0x1e:
case 0x1f:
READ8(addr, mach64->crtc_gen_cntl);
break;
case 0x40:
case 0x41:
case 0x42:
case 0x43:
READ8(addr, mach64->ovr_clr);
break;
case 0x44:
case 0x45:
case 0x46:
case 0x47:
READ8(addr, mach64->ovr_wid_left_right);
break;
case 0x48:
case 0x49:
case 0x4a:
case 0x4b:
READ8(addr, mach64->ovr_wid_top_bottom);
break;
case 0x60:
case 0x61:
case 0x62:
case 0x63:
READ8(addr, mach64->cur_clr0);
break;
case 0x64:
case 0x65:
case 0x66:
case 0x67:
READ8(addr, mach64->cur_clr1);
break;
case 0x68:
case 0x69:
case 0x6a:
case 0x6b:
READ8(addr, mach64->cur_offset);
break;
case 0x6c:
case 0x6d:
case 0x6e:
case 0x6f:
READ8(addr, mach64->cur_horz_vert_posn);
break;
case 0x70:
case 0x71:
case 0x72:
case 0x73:
READ8(addr, mach64->cur_horz_vert_off);
break;
case 0x79:
ret = 0x30;
break;
case 0x80:
case 0x81:
case 0x82:
case 0x83:
READ8(addr, mach64->scratch_reg0);
break;
case 0x84:
case 0x85:
case 0x86:
case 0x87:
READ8(addr, mach64->scratch_reg1);
break;
case 0x90:
case 0x91:
case 0x92:
case 0x93:
READ8(addr, mach64->clock_cntl);
break;
case 0xb0:
case 0xb1:
case 0xb2:
case 0xb3:
READ8(addr, mach64->mem_cntl);
break;
case 0xc0:
case 0xc1:
case 0xc2:
case 0xc3:
if (mach64->type == MACH64_GX)
ret = ati68860_ramdac_in((addr & 3) | ((mach64->dac_cntl & 3) << 2), mach64->svga.ramdac, &mach64->svga);
else
ret = ati68860_ramdac_in(addr & 3, mach64->svga.ramdac, &mach64->svga);
break;
case 0xc4:
case 0xc5:
case 0xc6:
READ8(addr, mach64->dac_cntl);
break;
case 0xc7:
READ8(addr, mach64->dac_cntl);
if (mach64->type == MACH64_VT2) {
ret &= 0xf9;
if (i2c_gpio_get_scl(mach64->i2c))
ret |= 0x04;
if (i2c_gpio_get_sda(mach64->i2c))
ret |= 0x02;
}
break;
case 0xd0:
case 0xd1:
case 0xd2:
case 0xd3:
READ8(addr, mach64->gen_test_cntl);
break;
case 0xdc:
case 0xdd:
case 0xde:
case 0xdf:
if (mach64->type == MACH64_GX)
mach64->config_cntl = (mach64->config_cntl & ~0x3ff0) | ((mach64->linear_base >> 22) << 4);
else
mach64->config_cntl = (mach64->config_cntl & ~0x3ff0) | ((mach64->linear_base >> 24) << 4);
READ8(addr, mach64->config_cntl);
break;
case 0xe0:
case 0xe1:
case 0xe2:
case 0xe3:
READ8(addr, mach64->config_chip_id);
break;
case 0xe4:
case 0xe5:
case 0xe6:
case 0xe7:
READ8(addr, mach64->config_stat0);
break;
case 0x100:
case 0x101:
case 0x102:
case 0x103:
//mach64_wait_fifo_idle(mach64);
READ8(addr, mach64->dst_off_pitch);
break;
case 0x104:
case 0x105:
//mach64_wait_fifo_idle(mach64);
READ8(addr, mach64->dst_y_x);
break;
case 0x108:
case 0x109:
case 0x11c:
case 0x11d:
//mach64_wait_fifo_idle(mach64);
READ8(addr + 2, mach64->dst_y_x);
break;
case 0x10c:
case 0x10d:
case 0x10e:
case 0x10f:
//mach64_wait_fifo_idle(mach64);
READ8(addr, mach64->dst_y_x);
break;
case 0x110:
case 0x111:
addr += 2;
fallthrough;
case 0x114:
case 0x115:
case 0x118:
case 0x119:
case 0x11a:
case 0x11b:
case 0x11e:
case 0x11f:
//mach64_wait_fifo_idle(mach64);
READ8(addr, mach64->dst_height_width);
break;
case 0x120:
case 0x121:
case 0x122:
case 0x123:
//mach64_wait_fifo_idle(mach64);
READ8(addr, mach64->dst_bres_lnth);
break;
case 0x124:
case 0x125:
case 0x126:
case 0x127:
//mach64_wait_fifo_idle(mach64);
READ8(addr, mach64->dst_bres_err);
break;
case 0x128:
case 0x129:
case 0x12a:
case 0x12b:
//mach64_wait_fifo_idle(mach64);
READ8(addr, mach64->dst_bres_inc);
break;
case 0x12c:
case 0x12d:
case 0x12e:
case 0x12f:
//mach64_wait_fifo_idle(mach64);
READ8(addr, mach64->dst_bres_dec);
break;
case 0x130:
case 0x131:
case 0x132:
case 0x133:
//mach64_wait_fifo_idle(mach64);
READ8(addr, mach64->dst_cntl);
break;
case 0x180:
case 0x181:
case 0x182:
case 0x183:
//mach64_wait_fifo_idle(mach64);
READ8(addr, mach64->src_off_pitch);
break;
case 0x184:
case 0x185:
//mach64_wait_fifo_idle(mach64);
READ8(addr, mach64->src_y_x);
break;
case 0x188:
case 0x189:
//mach64_wait_fifo_idle(mach64);
READ8(addr + 2, mach64->src_y_x);
break;
case 0x18c:
case 0x18d:
case 0x18e:
case 0x18f:
//mach64_wait_fifo_idle(mach64);
READ8(addr, mach64->src_y_x);
break;
case 0x190:
case 0x191:
//mach64_wait_fifo_idle(mach64);
READ8(addr + 2, mach64->src_height1_width1);
break;
case 0x194:
case 0x195:
//mach64_wait_fifo_idle(mach64);
READ8(addr, mach64->src_height1_width1);
break;
case 0x198:
case 0x199:
case 0x19a:
case 0x19b:
//mach64_wait_fifo_idle(mach64);
READ8(addr, mach64->src_height1_width1);
break;
case 0x19c:
case 0x19d:
//mach64_wait_fifo_idle(mach64);
READ8(addr, mach64->src_y_x_start);
break;
case 0x1a0:
case 0x1a1:
//mach64_wait_fifo_idle(mach64);
READ8(addr + 2, mach64->src_y_x_start);
break;
case 0x1a4:
case 0x1a5:
case 0x1a6:
case 0x1a7:
//mach64_wait_fifo_idle(mach64);
READ8(addr, mach64->src_y_x_start);
break;
case 0x1a8:
case 0x1a9:
//mach64_wait_fifo_idle(mach64);
READ8(addr + 2, mach64->src_height2_width2);
break;
case 0x1ac:
case 0x1ad:
//mach64_wait_fifo_idle(mach64);
READ8(addr, mach64->src_height2_width2);
break;
case 0x1b0:
case 0x1b1:
case 0x1b2:
case 0x1b3:
//mach64_wait_fifo_idle(mach64);
READ8(addr, mach64->src_height2_width2);
break;
case 0x1b4:
case 0x1b5:
case 0x1b6:
case 0x1b7:
//mach64_wait_fifo_idle(mach64);
READ8(addr, mach64->src_cntl);
break;
case 0x240:
case 0x241:
case 0x242:
case 0x243:
//mach64_wait_fifo_idle(mach64);
READ8(addr, mach64->host_cntl);
break;
case 0x280:
case 0x281:
case 0x282:
case 0x283:
//mach64_wait_fifo_idle(mach64);
READ8(addr, mach64->pat_reg0);
break;
case 0x284:
case 0x285:
case 0x286:
case 0x287:
//mach64_wait_fifo_idle(mach64);
READ8(addr, mach64->pat_reg1);
break;
case 0x288:
case 0x289:
case 0x28a:
case 0x28b:
//mach64_wait_fifo_idle(mach64);
READ8(addr, mach64->pat_cntl);
break;
case 0x2a0:
case 0x2a1:
case 0x2a8:
case 0x2a9:
//mach64_wait_fifo_idle(mach64);
READ8(addr, mach64->sc_left_right);
break;
case 0x2a4:
case 0x2a5:
addr += 2;
fallthrough;
case 0x2aa:
case 0x2ab:
//mach64_wait_fifo_idle(mach64);
READ8(addr, mach64->sc_left_right);
break;
case 0x2ac:
case 0x2ad:
case 0x2b4:
case 0x2b5:
//mach64_wait_fifo_idle(mach64);
READ8(addr, mach64->sc_top_bottom);
break;
case 0x2b0:
case 0x2b1:
addr += 2;
fallthrough;
case 0x2b6:
case 0x2b7:
//mach64_wait_fifo_idle(mach64);
READ8(addr, mach64->sc_top_bottom);
break;
case 0x2c0:
case 0x2c1:
case 0x2c2:
case 0x2c3:
//mach64_wait_fifo_idle(mach64);
READ8(addr, mach64->dp_bkgd_clr);
break;
case 0x2c4:
case 0x2c5:
case 0x2c6:
case 0x2c7:
//mach64_wait_fifo_idle(mach64);
READ8(addr, mach64->dp_frgd_clr);
break;
case 0x2c8:
case 0x2c9:
case 0x2ca:
case 0x2cb:
//mach64_wait_fifo_idle(mach64);
READ8(addr, mach64->write_mask);
break;
case 0x2cc:
case 0x2cd:
case 0x2ce:
case 0x2cf:
//mach64_wait_fifo_idle(mach64);
READ8(addr, mach64->chain_mask);
break;
case 0x2d0:
case 0x2d1:
case 0x2d2:
case 0x2d3:
//mach64_wait_fifo_idle(mach64);
READ8(addr, mach64->dp_pix_width);
break;
case 0x2d4:
case 0x2d5:
case 0x2d6:
case 0x2d7:
//mach64_wait_fifo_idle(mach64);
READ8(addr, mach64->dp_mix);
break;
case 0x2d8:
case 0x2d9:
case 0x2da:
case 0x2db:
//mach64_wait_fifo_idle(mach64);
READ8(addr, mach64->dp_src);
break;
case 0x300:
case 0x301:
case 0x302:
case 0x303:
//mach64_wait_fifo_idle(mach64);
READ8(addr, mach64->clr_cmp_clr);
break;
case 0x304:
case 0x305:
case 0x306:
case 0x307:
//mach64_wait_fifo_idle(mach64);
READ8(addr, mach64->clr_cmp_mask);
break;
case 0x308:
case 0x309:
case 0x30a:
case 0x30b:
//mach64_wait_fifo_idle(mach64);
READ8(addr, mach64->clr_cmp_cntl);
break;
case 0x310:
case 0x311:
ret = 0;
break;
case 0x320:
case 0x321:
case 0x322:
case 0x323:
//mach64_wait_fifo_idle(mach64);
READ8(addr, mach64->context_mask);
break;
case 0x330:
case 0x331:
//mach64_wait_fifo_idle(mach64);
READ8(addr, mach64->dst_cntl);
break;
case 0x332:
//mach64_wait_fifo_idle(mach64);
READ8(addr - 2, mach64->src_cntl);
break;
case 0x333:
//mach64_wait_fifo_idle(mach64);
READ8(addr - 3, mach64->pat_cntl);
break;
case 0x338:
ret = 0;
break;
default:
ret = 0;
break;
}
}
if ((addr & 0x3fc) != 0x018)
mach64_log("mach64_ext_readb : addr %08X ret %02X\n", addr, ret);
return ret;
}
uint16_t
mach64_ext_readw(uint32_t addr, void *priv)
{
const mach64_t *mach64 = (mach64_t *) priv;
uint16_t ret;
if (!(addr & 0x400)) {
mach64_log("nmach64_ext_readw: addr=%04x\n", addr);
ret = 0xffff;
} else
switch (addr & 0x3ff) {
case 0xb4:
case 0xb6:
ret = (mach64->bank_w[(addr & 2) >> 1] >> 15);
break;
case 0xb8:
case 0xba:
ret = (mach64->bank_r[(addr & 2) >> 1] >> 15);
break;
default:
ret = mach64_ext_readb(addr, priv);
ret |= mach64_ext_readb(addr + 1, priv) << 8;
break;
}
if ((addr & 0x3fc) != 0x018)
mach64_log("mach64_ext_readw : addr %08X ret %04X\n", addr, ret);
return ret;
}
uint32_t
mach64_ext_readl(uint32_t addr, void *priv)
{
const mach64_t *mach64 = (mach64_t *) priv;
uint32_t ret;
if (!(addr & 0x400)) {
mach64_log("nmach64_ext_readl: addr=%04x\n", addr);
ret = 0xffffffff;
} else
switch (addr & 0x3ff) {
case 0x18:
ret = mach64->crtc_int_cntl & ~1;
if (mach64->svga.cgastat & 8)
ret |= 1;
break;
case 0xb4:
ret = (mach64->bank_w[0] >> 15) | ((mach64->bank_w[1] >> 15) << 16);
break;
case 0xb8:
ret = (mach64->bank_r[0] >> 15) | ((mach64->bank_r[1] >> 15) << 16);
break;
default:
ret = mach64_ext_readw(addr, priv);
ret |= mach64_ext_readw(addr + 2, priv) << 16;
break;
}
if ((addr & 0x3fc) != 0x018)
mach64_log("mach64_ext_readl : addr %08X ret %08X\n", addr, ret);
return ret;
}
void
mach64_ext_writeb(uint32_t addr, uint8_t val, void *priv)
{
mach64_t *mach64 = (mach64_t *) priv;
svga_t *svga = &mach64->svga;
mach64_log("mach64_ext_writeb : addr %08X val %02X\n", addr, val);
if (!(addr & 0x400)) {
switch (addr & 0x3ff) {
case 0x00:
case 0x01:
case 0x02:
case 0x03:
WRITE8(addr, mach64->overlay_y_x_start, val);
break;
case 0x04:
case 0x05:
case 0x06:
case 0x07:
WRITE8(addr, mach64->overlay_y_x_end, val);
break;
case 0x08:
case 0x09:
case 0x0a:
case 0x0b:
WRITE8(addr, mach64->overlay_video_key_clr, val);
break;
case 0x0c:
case 0x0d:
case 0x0e:
case 0x0f:
WRITE8(addr, mach64->overlay_video_key_msk, val);
break;
case 0x10:
case 0x11:
case 0x12:
case 0x13:
WRITE8(addr, mach64->overlay_graphics_key_clr, val);
break;
case 0x14:
case 0x15:
case 0x16:
case 0x17:
WRITE8(addr, mach64->overlay_graphics_key_msk, val);
break;
case 0x18:
case 0x19:
case 0x1a:
case 0x1b:
WRITE8(addr, mach64->overlay_key_cntl, val);
break;
case 0x20:
case 0x21:
case 0x22:
case 0x23:
WRITE8(addr, mach64->overlay_scale_inc, val);
break;
case 0x24:
case 0x25:
case 0x26:
case 0x27:
WRITE8(addr, mach64->overlay_scale_cntl, val);
break;
case 0x28:
case 0x29:
case 0x2a:
case 0x2b:
WRITE8(addr, mach64->scaler_height_width, val);
break;
case 0x4a:
mach64->scaler_format = val & 0xf;
break;
case 0x80:
case 0x81:
case 0x82:
case 0x83:
WRITE8(addr, mach64->buf_offset[0], val);
break;
case 0x8c:
case 0x8d:
case 0x8e:
case 0x8f:
WRITE8(addr, mach64->buf_pitch[0], val);
break;
case 0x98:
case 0x99:
case 0x9a:
case 0x9b:
WRITE8(addr, mach64->buf_offset[1], val);
break;
case 0xa4:
case 0xa5:
case 0xa6:
case 0xa7:
WRITE8(addr, mach64->buf_pitch[1], val);
break;
default:
break;
}
mach64_log("nmach64_ext_writeb: addr=%04x val=%02x\n", addr, val);
} else if (addr & 0x300) {
mach64_accel_write_fifo(mach64, addr & 0x3ff, val);
} else {
switch (addr & 0x3ff) {
case 0x00:
case 0x01:
case 0x02:
case 0x03:
WRITE8(addr, mach64->crtc_h_total_disp, val);
svga_recalctimings(&mach64->svga);
svga->fullchange = svga->monitor->mon_changeframecount;
break;
case 0x04:
case 0x05:
case 0x06:
case 0x07:
WRITE8(addr, mach64->crtc_h_sync_strt_wid, val);
svga_recalctimings(&mach64->svga);
svga->fullchange = svga->monitor->mon_changeframecount;
break;
case 0x08:
case 0x09:
case 0x0a:
case 0x0b:
WRITE8(addr, mach64->crtc_v_total_disp, val);
svga_recalctimings(&mach64->svga);
svga->fullchange = svga->monitor->mon_changeframecount;
break;
case 0x0c:
case 0x0d:
case 0x0e:
case 0x0f:
WRITE8(addr, mach64->crtc_v_sync_strt_wid, val);
svga_recalctimings(&mach64->svga);
svga->fullchange = svga->monitor->mon_changeframecount;
break;
case 0x14:
case 0x15:
case 0x16:
case 0x17:
WRITE8(addr, mach64->crtc_off_pitch, val);
svga_recalctimings(&mach64->svga);
svga->fullchange = svga->monitor->mon_changeframecount;
break;
case 0x18:
mach64->crtc_int_cntl = (mach64->crtc_int_cntl & 0x75) | (val & ~0x75);
if (val & 4)
mach64->crtc_int_cntl &= ~4;
mach64_update_irqs(mach64);
break;
case 0x1c:
case 0x1d:
case 0x1e:
case 0x1f:
WRITE8(addr, mach64->crtc_gen_cntl, val);
if (((mach64->crtc_gen_cntl >> 24) & 3) == 3)
svga->fb_only = 1;
else
svga->fb_only = 0;
svga->dpms = !!(mach64->crtc_gen_cntl & 0x0c);
svga_recalctimings(&mach64->svga);
svga->fullchange = svga->monitor->mon_changeframecount;
break;
case 0x40:
case 0x41:
case 0x42:
case 0x43:
WRITE8(addr, mach64->ovr_clr, val);
break;
case 0x44:
case 0x45:
case 0x46:
case 0x47:
WRITE8(addr, mach64->ovr_wid_left_right, val);
break;
case 0x48:
case 0x49:
case 0x4a:
case 0x4b:
WRITE8(addr, mach64->ovr_wid_top_bottom, val);
break;
case 0x60:
case 0x61:
case 0x62:
case 0x63:
WRITE8(addr, mach64->cur_clr0, val);
if (mach64->type == MACH64_VT2)
ati68860_ramdac_set_pallook(mach64->svga.ramdac, 0, makecol32((mach64->cur_clr0 >> 24) & 0xff, (mach64->cur_clr0 >> 16) & 0xff, (mach64->cur_clr0 >> 8) & 0xff));
break;
case 0x64:
case 0x65:
case 0x66:
case 0x67:
WRITE8(addr, mach64->cur_clr1, val);
if (mach64->type == MACH64_VT2)
ati68860_ramdac_set_pallook(mach64->svga.ramdac, 1, makecol32((mach64->cur_clr1 >> 24) & 0xff, (mach64->cur_clr1 >> 16) & 0xff, (mach64->cur_clr1 >> 8) & 0xff));
break;
case 0x68:
case 0x69:
case 0x6a:
case 0x6b:
WRITE8(addr, mach64->cur_offset, val);
svga->dac_hwcursor.addr = (mach64->cur_offset & 0xfffff) * 8;
break;
case 0x6c:
case 0x6d:
case 0x6e:
case 0x6f:
WRITE8(addr, mach64->cur_horz_vert_posn, val);
svga->dac_hwcursor.x = mach64->cur_horz_vert_posn & 0x7ff;
svga->dac_hwcursor.y = (mach64->cur_horz_vert_posn >> 16) & 0x7ff;
break;
case 0x70:
case 0x71:
case 0x72:
case 0x73:
WRITE8(addr, mach64->cur_horz_vert_off, val);
svga->dac_hwcursor.xoff = mach64->cur_horz_vert_off & 0x3f;
svga->dac_hwcursor.yoff = (mach64->cur_horz_vert_off >> 16) & 0x3f;
break;
case 0x80:
case 0x81:
case 0x82:
case 0x83:
WRITE8(addr, mach64->scratch_reg0, val);
break;
case 0x84:
case 0x85:
case 0x86:
case 0x87:
WRITE8(addr, mach64->scratch_reg1, val);
break;
case 0x90:
case 0x91:
case 0x92:
case 0x93:
WRITE8(addr, mach64->clock_cntl, val);
if (mach64->type == MACH64_GX)
ics2595_write(svga->clock_gen, val & 0x40, val & 0xf);
else {
pll_write(mach64, addr, val);
ics2595_setclock(svga->clock_gen, mach64->pll_freq[mach64->clock_cntl & 3]);
}
svga_recalctimings(&mach64->svga);
break;
case 0xb0:
case 0xb1:
case 0xb2:
case 0xb3:
WRITE8(addr, mach64->mem_cntl, val);
break;
case 0xb4:
mach64->bank_w[0] = val * 32768;
mach64_log("mach64 : write bank A0000-A7FFF set to %08X\n", mach64->bank_w[0]);
break;
case 0xb5:
case 0xb6:
mach64->bank_w[1] = val * 32768;
mach64_log("mach64 : write bank A8000-AFFFF set to %08X\n", mach64->bank_w[1]);
break;
case 0xb8:
mach64->bank_r[0] = val * 32768;
mach64_log("mach64 : read bank A0000-A7FFF set to %08X\n", mach64->bank_r[0]);
break;
case 0xb9:
case 0xba:
mach64->bank_r[1] = val * 32768;
mach64_log("mach64 : read bank A8000-AFFFF set to %08X\n", mach64->bank_r[1]);
break;
case 0xc0:
case 0xc1:
case 0xc2:
case 0xc3:
if (mach64->type == MACH64_GX)
ati68860_ramdac_out((addr & 3) | ((mach64->dac_cntl & 3) << 2), val, svga->ramdac, svga);
else
ati68860_ramdac_out(addr & 3, val, svga->ramdac, svga);
break;
case 0xc4:
case 0xc5:
case 0xc6:
case 0xc7:
WRITE8(addr, mach64->dac_cntl, val);
mach64_log("Ext RAMDAC TYPE write=%x, bit set=%03x.\n", addr & 0x3ff, mach64->dac_cntl & 0x100);
if ((addr & 3) >= 1) {
svga_set_ramdac_type(svga, !!(mach64->dac_cntl & 0x100));
ati68860_set_ramdac_type(svga->ramdac, !!(mach64->dac_cntl & 0x100));
}
i2c_gpio_set(mach64->i2c, !(mach64->dac_cntl & 0x20000000) || (mach64->dac_cntl & 0x04000000), !(mach64->dac_cntl & 0x10000000) || (mach64->dac_cntl & 0x02000000));
break;
case 0xd0:
case 0xd1:
case 0xd2:
case 0xd3:
WRITE8(addr, mach64->gen_test_cntl, val);
ati_eeprom_write(&mach64->eeprom, mach64->gen_test_cntl & 0x10, mach64->gen_test_cntl & 2, mach64->gen_test_cntl & 1);
mach64->gen_test_cntl = (mach64->gen_test_cntl & ~8) | (ati_eeprom_read(&mach64->eeprom) ? 8 : 0);
svga->dac_hwcursor.ena = mach64->gen_test_cntl & 0x80;
break;
case 0xdc:
case 0xdd:
case 0xde:
case 0xdf:
WRITE8(addr, mach64->config_cntl, val);
mach64_updatemapping(mach64);
break;
case 0xe4:
case 0xe5:
case 0xe6:
case 0xe7:
if (mach64->type != MACH64_GX)
WRITE8(addr, mach64->config_stat0, val);
break;
default:
break;
}
}
}
void
mach64_ext_writew(uint32_t addr, uint16_t val, void *priv)
{
mach64_t *mach64 = (mach64_t *) priv;
mach64_log("mach64_ext_writew : addr %08X val %04X\n", addr, val);
if (!(addr & 0x400)) {
mach64_log("mach64_ext_writew: addr=%04x val=%04x\n", addr, val);
mach64_ext_writeb(addr, val, priv);
mach64_ext_writeb(addr + 1, val >> 8, priv);
} else if (addr & 0x300) {
mach64_accel_write_fifo_w(mach64, addr & 0x3fe, val);
} else
switch (addr & 0x3fe) {
default:
mach64_ext_writeb(addr, val, priv);
mach64_ext_writeb(addr + 1, val >> 8, priv);
break;
}
}
void
mach64_ext_writel(uint32_t addr, uint32_t val, void *priv)
{
mach64_t *mach64 = (mach64_t *) priv;
if ((addr & 0x3c0) != 0x200)
mach64_log("mach64_ext_writel : addr %08X val %08X\n", addr, val);
if (!(addr & 0x400)) {
mach64_log("mach64_ext_writel: addr=%04x val=%08x\n", addr, val);
mach64_ext_writew(addr, val, priv);
mach64_ext_writew(addr + 2, val >> 16, priv);
} else if (addr & 0x300) {
mach64_accel_write_fifo_l(mach64, addr & 0x3fc, val);
} else
switch (addr & 0x3fc) {
default:
mach64_ext_writew(addr, val, priv);
mach64_ext_writew(addr + 2, val >> 16, priv);
break;
}
}
uint8_t
mach64_ext_inb(uint16_t port, void *priv)
{
mach64_t *mach64 = (mach64_t *) priv;
uint8_t ret = 0xff;
switch (port) {
case 0x02ec:
case 0x02ed:
case 0x02ee:
case 0x02ef:
case 0x7eec:
case 0x7eed:
case 0x7eee:
case 0x7eef:
ret = mach64_ext_readb(0x400 | 0x00 | (port & 3), priv);
break;
case 0x0aec:
case 0x0aed:
case 0x0aee:
case 0x0aef:
ret = mach64_ext_readb(0x400 | 0x08 | (port & 3), priv);
break;
case 0x0eec:
case 0x0eed:
case 0x0eee:
case 0x0eef:
ret = mach64_ext_readb(0x400 | 0x0c | (port & 3), priv);
break;
case 0x12ec:
case 0x12ed:
case 0x12ee:
case 0x12ef:
ret = mach64_ext_readb(0x400 | 0x10 | (port & 3), priv);
break;
case 0x16ec:
case 0x16ed:
case 0x16ee:
case 0x16ef:
ret = mach64_ext_readb(0x400 | 0x14 | (port & 3), priv);
break;
case 0x1aec:
ret = mach64_ext_readb(0x400 | 0x18, priv);
break;
case 0x1eec:
case 0x1eed:
case 0x1eee:
case 0x1eef:
ret = mach64_ext_readb(0x400 | 0x1c | (port & 3), priv);
break;
case 0x22ec:
case 0x22ed:
case 0x22ee:
case 0x22ef:
ret = mach64_ext_readb(0x400 | 0x40 | (port & 3), priv);
break;
case 0x26ec:
case 0x26ed:
case 0x26ee:
case 0x26ef:
ret = mach64_ext_readb(0x400 | 0x44 | (port & 3), priv);
break;
case 0x2aec:
case 0x2aed:
case 0x2aee:
case 0x2aef:
ret = mach64_ext_readb(0x400 | 0x48 | (port & 3), priv);
break;
case 0x2eec:
case 0x2eed:
case 0x2eee:
case 0x2eef:
ret = mach64_ext_readb(0x400 | 0x60 | (port & 3), priv);
break;
case 0x32ec:
case 0x32ed:
case 0x32ee:
case 0x32ef:
ret = mach64_ext_readb(0x400 | 0x64 | (port & 3), priv);
break;
case 0x36ec:
case 0x36ed:
case 0x36ee:
case 0x36ef:
ret = mach64_ext_readb(0x400 | 0x68 | (port & 3), priv);
break;
case 0x3aec:
case 0x3aed:
case 0x3aee:
case 0x3aef:
ret = mach64_ext_readb(0x400 | 0x6c | (port & 3), priv);
break;
case 0x3eec:
case 0x3eed:
case 0x3eee:
case 0x3eef:
ret = mach64_ext_readb(0x400 | 0x70 | (port & 3), priv);
break;
case 0x42ec:
case 0x42ed:
case 0x42ee:
case 0x42ef:
ret = mach64_ext_readb(0x400 | 0x80 | (port & 3), priv);
break;
case 0x46ec:
case 0x46ed:
case 0x46ee:
case 0x46ef:
ret = mach64_ext_readb(0x400 | 0x84 | (port & 3), priv);
break;
case 0x4aec:
case 0x4aed:
case 0x4aee:
case 0x4aef:
ret = mach64_ext_readb(0x400 | 0x90 | (port & 3), priv);
break;
case 0x52ec:
case 0x52ed:
case 0x52ee:
case 0x52ef:
ret = mach64_ext_readb(0x400 | 0xb0 | (port & 3), priv);
break;
case 0x56ec:
ret = mach64_ext_readb(0x400 | 0xb4, priv);
break;
case 0x56ed:
case 0x56ee:
ret = mach64_ext_readb(0x400 | 0xb5, priv);
break;
case 0x5aec:
ret = mach64_ext_readb(0x400 | 0xb8, priv);
break;
case 0x5aed:
case 0x5aee:
ret = mach64_ext_readb(0x400 | 0xb9, priv);
break;
case 0x5eec:
case 0x5eed:
case 0x5eee:
case 0x5eef:
if (mach64->type == MACH64_GX)
ret = ati68860_ramdac_in((port & 3) | ((mach64->dac_cntl & 3) << 2), mach64->svga.ramdac, &mach64->svga);
else
ret = ati68860_ramdac_in(port & 3, mach64->svga.ramdac, &mach64->svga);
break;
case 0x62ec:
case 0x62ed:
case 0x62ee:
case 0x62ef:
ret = mach64_ext_readb(0x400 | 0xc4 | (port & 3), priv);
break;
case 0x66ec:
case 0x66ed:
case 0x66ee:
case 0x66ef:
ret = mach64_ext_readb(0x400 | 0xd0 | (port & 3), priv);
break;
case 0x6aec:
case 0x6aed:
case 0x6aee:
case 0x6aef:
mach64->config_cntl = (mach64->config_cntl & ~0x3ff0) | ((mach64->linear_base >> 22) << 4);
READ8(port, mach64->config_cntl);
break;
case 0x6eec:
case 0x6eed:
case 0x6eee:
case 0x6eef:
ret = mach64_ext_readb(0x400 | 0xe0 | (port & 3), priv);
break;
case 0x72ec:
case 0x72ed:
case 0x72ee:
case 0x72ef:
ret = mach64_ext_readb(0x400 | 0xe4 | (port & 3), priv);
break;
default:
ret = 0;
break;
}
mach64_log("mach64_ext_inb : port %04X ret %02X\n", port, ret);
return ret;
}
uint16_t
mach64_ext_inw(uint16_t port, void *priv)
{
uint16_t ret;
switch (port) {
default:
ret = mach64_ext_inb(port, priv);
ret |= (mach64_ext_inb(port + 1, priv) << 8);
break;
}
mach64_log("mach64_ext_inw : port %04X ret %04X\n", port, ret);
return ret;
}
uint32_t
mach64_ext_inl(uint16_t port, void *priv)
{
uint32_t ret;
switch (port) {
case 0x56ec:
ret = mach64_ext_readl(0x400 | 0xb4, priv);
break;
case 0x5aec:
ret = mach64_ext_readl(0x400 | 0xb8, priv);
break;
default:
ret = mach64_ext_inw(port, priv);
ret |= (mach64_ext_inw(port + 2, priv) << 16);
break;
}
mach64_log("mach64_ext_inl : port %04X ret %08X\n", port, ret);
return ret;
}
void
mach64_ext_outb(uint16_t port, uint8_t val, void *priv)
{
mach64_t *mach64 = (mach64_t *) priv;
svga_t *svga = &mach64->svga;
mach64_log("mach64_ext_outb : port %04X val %02X\n", port, val);
switch (port) {
case 0x02ec:
case 0x02ed:
case 0x02ee:
case 0x02ef:
case 0x7eec:
case 0x7eed:
case 0x7eee:
case 0x7eef:
mach64_ext_writeb(0x400 | 0x00 | (port & 3), val, priv);
break;
case 0x0aec:
case 0x0aed:
case 0x0aee:
case 0x0aef:
mach64_ext_writeb(0x400 | 0x08 | (port & 3), val, priv);
break;
case 0x0eec:
case 0x0eed:
case 0x0eee:
case 0x0eef:
mach64_ext_writeb(0x400 | 0x0c | (port & 3), val, priv);
break;
case 0x16ec:
case 0x16ed:
case 0x16ee:
case 0x16ef:
mach64_ext_writeb(0x400 | 0x14 | (port & 3), val, priv);
break;
case 0x1aec:
mach64_ext_writeb(0x400 | 0x18, val, priv);
break;
case 0x1eec:
case 0x1eed:
case 0x1eee:
case 0x1eef:
mach64_ext_writeb(0x400 | 0x1c | (port & 3), val, priv);
break;
case 0x22ec:
case 0x22ed:
case 0x22ee:
case 0x22ef:
mach64_ext_writeb(0x400 | 0x40 | (port & 3), val, priv);
break;
case 0x26ec:
case 0x26ed:
case 0x26ee:
case 0x26ef:
mach64_ext_writeb(0x400 | 0x44 | (port & 3), val, priv);
break;
case 0x2aec:
case 0x2aed:
case 0x2aee:
case 0x2aef:
mach64_ext_writeb(0x400 | 0x48 | (port & 3), val, priv);
break;
case 0x2eec:
case 0x2eed:
case 0x2eee:
case 0x2eef:
mach64_ext_writeb(0x400 | 0x60 | (port & 3), val, priv);
break;
case 0x32ec:
case 0x32ed:
case 0x32ee:
case 0x32ef:
mach64_ext_writeb(0x400 | 0x64 | (port & 3), val, priv);
break;
case 0x36ec:
case 0x36ed:
case 0x36ee:
case 0x36ef:
mach64_ext_writeb(0x400 | 0x68 | (port & 3), val, priv);
break;
case 0x3aec:
case 0x3aed:
case 0x3aee:
case 0x3aef:
mach64_ext_writeb(0x400 | 0x6c | (port & 3), val, priv);
break;
case 0x3eec:
case 0x3eed:
case 0x3eee:
case 0x3eef:
mach64_ext_writeb(0x400 | 0x70 | (port & 3), val, priv);
break;
case 0x42ec:
case 0x42ed:
case 0x42ee:
case 0x42ef:
mach64_ext_writeb(0x400 | 0x80 | (port & 3), val, priv);
break;
case 0x46ec:
case 0x46ed:
case 0x46ee:
case 0x46ef:
mach64_ext_writeb(0x400 | 0x84 | (port & 3), val, priv);
break;
case 0x4aec:
case 0x4aed:
case 0x4aee:
case 0x4aef:
mach64_ext_writeb(0x400 | 0x90 | (port & 3), val, priv);
break;
case 0x52ec:
case 0x52ed:
case 0x52ee:
case 0x52ef:
mach64_ext_writeb(0x400 | 0xb0 | (port & 3), val, priv);
break;
case 0x56ec:
mach64_ext_writeb(0x400 | 0xb4, val, priv);
break;
case 0x56ed:
case 0x56ee:
mach64_ext_writeb(0x400 | 0xb5, val, priv);
break;
case 0x5aec:
mach64_ext_writeb(0x400 | 0xb8, val, priv);
break;
case 0x5aed:
case 0x5aee:
mach64_ext_writeb(0x400 | 0xb9, val, priv);
break;
case 0x5eec:
case 0x5eed:
case 0x5eee:
case 0x5eef:
if (mach64->type == MACH64_GX)
ati68860_ramdac_out((port & 3) | ((mach64->dac_cntl & 3) << 2), val, svga->ramdac, svga);
else
ati68860_ramdac_out(port & 3, val, svga->ramdac, svga);
break;
case 0x62ec:
case 0x62ed:
case 0x62ee:
case 0x62ef:
mach64_ext_writeb(0x400 | 0xc4 | (port & 3), val, priv);
break;
case 0x66ec:
case 0x66ed:
case 0x66ee:
case 0x66ef:
mach64_ext_writeb(0x400 | 0xd0 | (port & 3), val, priv);
break;
case 0x6aec:
case 0x6aed:
case 0x6aee:
case 0x6aef:
WRITE8(port, mach64->config_cntl, val);
mach64_updatemapping(mach64);
break;
default:
break;
}
}
void
mach64_ext_outw(uint16_t port, uint16_t val, void *priv)
{
mach64_log("mach64_ext_outw : port %04X val %04X\n", port, val);
switch (port) {
default:
mach64_ext_outb(port, val, priv);
mach64_ext_outb(port + 1, val >> 8, priv);
break;
}
}
void
mach64_ext_outl(uint16_t port, uint32_t val, void *priv)
{
mach64_log("mach64_ext_outl : port %04X val %08X\n", port, val);
switch (port) {
default:
mach64_ext_outw(port, val, priv);
mach64_ext_outw(port + 2, val >> 16, priv);
break;
}
}
static uint8_t
mach64_block_inb(uint16_t port, void *priv)
{
mach64_t *mach64 = (mach64_t *) priv;
uint8_t ret;
ret = mach64_ext_readb(0x400 | (port & 0x3ff), mach64);
mach64_log("mach64_block_inb : port %04X ret %02X\n", port, ret);
return ret;
}
static uint16_t
mach64_block_inw(uint16_t port, void *priv)
{
mach64_t *mach64 = (mach64_t *) priv;
uint16_t ret;
ret = mach64_ext_readw(0x400 | (port & 0x3ff), mach64);
mach64_log("mach64_block_inw : port %04X ret %04X\n", port, ret);
return ret;
}
static uint32_t
mach64_block_inl(uint16_t port, void *priv)
{
mach64_t *mach64 = (mach64_t *) priv;
uint32_t ret;
ret = mach64_ext_readl(0x400 | (port & 0x3ff), mach64);
mach64_log("mach64_block_inl : port %04X ret %08X\n", port, ret);
return ret;
}
static void
mach64_block_outb(uint16_t port, uint8_t val, void *priv)
{
mach64_t *mach64 = (mach64_t *) priv;
mach64_log("mach64_block_outb : port %04X val %02X\n ", port, val);
mach64_ext_writeb(0x400 | (port & 0x3ff), val, mach64);
}
static void
mach64_block_outw(uint16_t port, uint16_t val, void *priv)
{
mach64_t *mach64 = (mach64_t *) priv;
mach64_log("mach64_block_outw : port %04X val %04X\n ", port, val);
mach64_ext_writew(0x400 | (port & 0x3ff), val, mach64);
}
static void
mach64_block_outl(uint16_t port, uint32_t val, void *priv)
{
mach64_t *mach64 = (mach64_t *) priv;
mach64_log("mach64_block_outl : port %04X val %08X\n ", port, val);
mach64_ext_writel(0x400 | (port & 0x3ff), val, mach64);
}
void
mach64_write(uint32_t addr, uint8_t val, void *priv)
{
mach64_t *mach64 = (mach64_t *) priv;
svga_t *svga = &mach64->svga;
addr = (addr & 0x7fff) + mach64->bank_w[(addr >> 15) & 1];
svga_write_linear(addr, val, svga);
}
void
mach64_writew(uint32_t addr, uint16_t val, void *priv)
{
mach64_t *mach64 = (mach64_t *) priv;
svga_t *svga = &mach64->svga;
addr = (addr & 0x7fff) + mach64->bank_w[(addr >> 15) & 1];
svga_writew_linear(addr, val, svga);
}
void
mach64_writel(uint32_t addr, uint32_t val, void *priv)
{
mach64_t *mach64 = (mach64_t *) priv;
svga_t *svga = &mach64->svga;
addr = (addr & 0x7fff) + mach64->bank_w[(addr >> 15) & 1];
svga_writel_linear(addr, val, svga);
}
uint8_t
mach64_read(uint32_t addr, void *priv)
{
mach64_t *mach64 = (mach64_t *) priv;
svga_t *svga = &mach64->svga;
uint8_t ret;
addr = (addr & 0x7fff) + mach64->bank_r[(addr >> 15) & 1];
ret = svga_read_linear(addr, svga);
return ret;
}
uint16_t
mach64_readw(uint32_t addr, void *priv)
{
mach64_t *mach64 = (mach64_t *) priv;
svga_t *svga = &mach64->svga;
uint16_t ret;
addr = (addr & 0x7fff) + mach64->bank_r[(addr >> 15) & 1];
ret = svga_readw_linear(addr, svga);
return ret;
}
uint32_t
mach64_readl(uint32_t addr, void *priv)
{
mach64_t *mach64 = (mach64_t *) priv;
svga_t *svga = &mach64->svga;
uint32_t ret;
addr = (addr & 0x7fff) + mach64->bank_r[(addr >> 15) & 1];
ret = svga_readl_linear(addr, svga);
return ret;
}
#define CLAMP(x) \
do { \
if ((x) & ~0xff) \
x = ((x) < 0) ? 0 : 0xff; \
} while (0)
#define DECODE_ARGB1555() \
do { \
for (x = 0; x < mach64->svga.overlay_latch.cur_xsize; x++) { \
uint16_t dat = ((uint16_t *) src)[x]; \
\
int b = dat & 0x1f; \
int g = (dat >> 5) & 0x1f; \
int r = (dat >> 10) & 0x1f; \
\
b = (b << 3) | (b >> 2); \
g = (g << 3) | (g >> 2); \
r = (r << 3) | (r >> 2); \
\
mach64->overlay_dat[x] = (r << 16) | (g << 8) | b; \
} \
} while (0)
#define DECODE_RGB565() \
do { \
for (x = 0; x < mach64->svga.overlay_latch.cur_xsize; x++) { \
uint16_t dat = ((uint16_t *) src)[x]; \
\
int b = dat & 0x1f; \
int g = (dat >> 5) & 0x3f; \
int r = (dat >> 11) & 0x1f; \
\
b = (b << 3) | (b >> 2); \
g = (g << 2) | (g >> 4); \
r = (r << 3) | (r >> 2); \
\
mach64->overlay_dat[x] = (r << 16) | (g << 8) | b; \
} \
} while (0)
#define DECODE_ARGB8888() \
do { \
for (x = 0; x < mach64->svga.overlay_latch.cur_xsize; x++) { \
int b = src[0]; \
int g = src[1]; \
int r = src[2]; \
src += 4; \
\
mach64->overlay_dat[x] = (r << 16) | (g << 8) | b; \
} \
} while (0)
#define DECODE_VYUY422() \
do { \
for (x = 0; x < mach64->svga.overlay_latch.cur_xsize; x += 2) { \
uint8_t y1, y2; \
int8_t u, v; \
int dR, dG, dB; \
int r, g, b; \
\
y1 = src[0]; \
u = src[1] - 0x80; \
y2 = src[2]; \
v = src[3] - 0x80; \
src += 4; \
\
dR = (359 * v) >> 8; \
dG = (88 * u + 183 * v) >> 8; \
dB = (453 * u) >> 8; \
\
r = y1 + dR; \
CLAMP(r); \
g = y1 - dG; \
CLAMP(g); \
b = y1 + dB; \
CLAMP(b); \
mach64->overlay_dat[x] = (r << 16) | (g << 8) | b; \
\
r = y2 + dR; \
CLAMP(r); \
g = y2 - dG; \
CLAMP(g); \
b = y2 + dB; \
CLAMP(b); \
mach64->overlay_dat[x + 1] = (r << 16) | (g << 8) | b; \
} \
} while (0)
#define DECODE_YVYU422() \
do { \
for (x = 0; x < mach64->svga.overlay_latch.cur_xsize; x += 2) { \
uint8_t y1, y2; \
int8_t u, v; \
int dR, dG, dB; \
int r, g, b; \
\
u = src[0] - 0x80; \
y1 = src[1]; \
v = src[2] - 0x80; \
y2 = src[3]; \
src += 4; \
\
dR = (359 * v) >> 8; \
dG = (88 * u + 183 * v) >> 8; \
dB = (453 * u) >> 8; \
\
r = y1 + dR; \
CLAMP(r); \
g = y1 - dG; \
CLAMP(g); \
b = y1 + dB; \
CLAMP(b); \
mach64->overlay_dat[x] = (r << 16) | (g << 8) | b; \
\
r = y2 + dR; \
CLAMP(r); \
g = y2 - dG; \
CLAMP(g); \
b = y2 + dB; \
CLAMP(b); \
mach64->overlay_dat[x + 1] = (r << 16) | (g << 8) | b; \
} \
} while (0)
void
mach64_overlay_draw(svga_t *svga, int displine)
{
mach64_t *mach64 = (mach64_t *) svga->priv;
int x;
int h_acc = 0;
int h_max = (mach64->scaler_height_width >> 16) & 0x3ff;
int h_inc = mach64->overlay_scale_inc >> 16;
int v_max = mach64->scaler_height_width & 0x3ff;
int v_inc = mach64->overlay_scale_inc & 0xffff;
uint32_t *p;
uint8_t *src = &svga->vram[svga->overlay.addr];
int old_y = mach64->overlay_v_acc;
int y_diff;
int video_key_fn = mach64->overlay_key_cntl & 5;
int graphics_key_fn = (mach64->overlay_key_cntl >> 4) & 5;
int overlay_cmp_mix = (mach64->overlay_key_cntl >> 8) & 0xf;
p = &buffer32->line[displine][svga->x_add + mach64->svga.overlay_latch.x];
if (mach64->scaler_update) {
switch (mach64->scaler_format) {
case 0x3:
DECODE_ARGB1555();
break;
case 0x4:
DECODE_RGB565();
break;
case 0x6:
DECODE_ARGB8888();
break;
case 0xb:
DECODE_VYUY422();
break;
case 0xc:
DECODE_YVYU422();
break;
default:
mach64_log("Unknown Mach64 scaler format %x\n", mach64->scaler_format);
/*Fill buffer with something recognisably wrong*/
for (x = 0; x < mach64->svga.overlay_latch.cur_xsize; x++)
mach64->overlay_dat[x] = 0xff00ff;
break;
}
}
if (overlay_cmp_mix == 2) {
for (x = 0; x < mach64->svga.overlay_latch.cur_xsize; x++) {
int h = h_acc >> 12;
p[x] = mach64->overlay_dat[h];
h_acc += h_inc;
if (h_acc > (h_max << 12))
h_acc = (h_max << 12);
}
} else {
for (x = 0; x < mach64->svga.overlay_latch.cur_xsize; x++) {
int h = h_acc >> 12;
int gr_cmp = 0;
int vid_cmp = 0;
int use_video = 0;
switch (video_key_fn) {
case 0:
vid_cmp = 0;
break;
case 1:
vid_cmp = 1;
break;
case 4:
vid_cmp = ((mach64->overlay_dat[h] ^ mach64->overlay_video_key_clr) & mach64->overlay_video_key_msk);
break;
case 5:
vid_cmp = !((mach64->overlay_dat[h] ^ mach64->overlay_video_key_clr) & mach64->overlay_video_key_msk);
break;
default:
break;
}
switch (graphics_key_fn) {
case 0:
gr_cmp = 0;
break;
case 1:
gr_cmp = 1;
break;
case 4:
gr_cmp = (((p[x]) ^ mach64->overlay_graphics_key_clr) & mach64->overlay_graphics_key_msk & 0xffffff);
break;
case 5:
gr_cmp = !(((p[x]) ^ mach64->overlay_graphics_key_clr) & mach64->overlay_graphics_key_msk & 0xffffff);
break;
default:
break;
}
vid_cmp = vid_cmp ? -1 : 0;
gr_cmp = gr_cmp ? -1 : 0;
switch (overlay_cmp_mix) {
case 0x0:
use_video = gr_cmp;
break;
case 0x1:
use_video = 0;
break;
case 0x2:
use_video = ~0;
break;
case 0x3:
use_video = ~gr_cmp;
break;
case 0x4:
use_video = ~vid_cmp;
break;
case 0x5:
use_video = gr_cmp ^ vid_cmp;
break;
case 0x6:
use_video = ~gr_cmp ^ vid_cmp;
break;
case 0x7:
use_video = vid_cmp;
break;
case 0x8:
use_video = ~gr_cmp | ~vid_cmp;
break;
case 0x9:
use_video = gr_cmp | ~vid_cmp;
break;
case 0xa:
use_video = ~gr_cmp | vid_cmp;
break;
case 0xb:
use_video = gr_cmp | vid_cmp;
break;
case 0xc:
use_video = gr_cmp & vid_cmp;
break;
case 0xd:
use_video = ~gr_cmp & vid_cmp;
break;
case 0xe:
use_video = gr_cmp & ~vid_cmp;
break;
case 0xf:
use_video = ~gr_cmp & ~vid_cmp;
break;
default:
break;
}
if (use_video)
p[x] = mach64->overlay_dat[h];
h_acc += h_inc;
if (h_acc > (h_max << 12))
h_acc = (h_max << 12);
}
}
mach64->overlay_v_acc += v_inc;
if (mach64->overlay_v_acc > (v_max << 12))
mach64->overlay_v_acc = v_max << 12;
y_diff = (mach64->overlay_v_acc >> 12) - (old_y >> 12);
if (mach64->scaler_format == 6)
svga->overlay.addr += svga->overlay.pitch * 4 * y_diff;
else
svga->overlay.addr += svga->overlay.pitch * 2 * y_diff;
mach64->scaler_update = y_diff;
}
static void
mach64_io_remove(mach64_t *mach64)
{
uint16_t io_base = 0x02ec;
switch (mach64->io_base) {
default:
case 0:
io_base = 0x02ec;
break;
case 1:
io_base = 0x01cc;
break;
case 2:
io_base = 0x01c8;
break;
case 3:
fatal("Attempting to use the reserved value for I/O Base\n");
return;
}
io_removehandler(0x03c0, 0x0020, mach64_in, NULL, NULL, mach64_out, NULL, NULL, mach64);
for (uint8_t c = 0; c < 8; c++) {
io_removehandler((c * 0x1000) + 0x0000 + io_base, 0x0004, mach64_ext_inb, mach64_ext_inw, mach64_ext_inl, mach64_ext_outb, mach64_ext_outw, mach64_ext_outl, mach64);
io_removehandler((c * 0x1000) + 0x0400 + io_base, 0x0004, mach64_ext_inb, mach64_ext_inw, mach64_ext_inl, mach64_ext_outb, mach64_ext_outw, mach64_ext_outl, mach64);
io_removehandler((c * 0x1000) + 0x0800 + io_base, 0x0004, mach64_ext_inb, mach64_ext_inw, mach64_ext_inl, mach64_ext_outb, mach64_ext_outw, mach64_ext_outl, mach64);
io_removehandler((c * 0x1000) + 0x0c00 + io_base, 0x0004, mach64_ext_inb, mach64_ext_inw, mach64_ext_inl, mach64_ext_outb, mach64_ext_outw, mach64_ext_outl, mach64);
}
io_removehandler(0x01ce, 0x0002, mach64_in, NULL, NULL, mach64_out, NULL, NULL, mach64);
if (mach64->block_decoded_io && mach64->block_decoded_io < 0x10000)
io_removehandler(mach64->block_decoded_io, 0x0400, mach64_block_inb, mach64_block_inw, mach64_block_inl, mach64_block_outb, mach64_block_outw, mach64_block_outl, mach64);
}
static void
mach64_io_set(mach64_t *mach64)
{
uint16_t io_base = 0x02ec;
mach64_io_remove(mach64);
switch (mach64->io_base) {
default:
case 0:
io_base = 0x02ec;
break;
case 1:
io_base = 0x01cc;
break;
case 2:
io_base = 0x01c8;
break;
case 3:
fatal("Attempting to use the reserved value for I/O Base\n");
return;
}
io_sethandler(0x03c0, 0x0020, mach64_in, NULL, NULL, mach64_out, NULL, NULL, mach64);
if (!mach64->use_block_decoded_io) {
for (uint8_t c = 0; c < 8; c++) {
io_sethandler((c * 0x1000) + 0x0000 + io_base, 0x0004, mach64_ext_inb, mach64_ext_inw, mach64_ext_inl, mach64_ext_outb, mach64_ext_outw, mach64_ext_outl, mach64);
io_sethandler((c * 0x1000) + 0x0400 + io_base, 0x0004, mach64_ext_inb, mach64_ext_inw, mach64_ext_inl, mach64_ext_outb, mach64_ext_outw, mach64_ext_outl, mach64);
io_sethandler((c * 0x1000) + 0x0800 + io_base, 0x0004, mach64_ext_inb, mach64_ext_inw, mach64_ext_inl, mach64_ext_outb, mach64_ext_outw, mach64_ext_outl, mach64);
io_sethandler((c * 0x1000) + 0x0c00 + io_base, 0x0004, mach64_ext_inb, mach64_ext_inw, mach64_ext_inl, mach64_ext_outb, mach64_ext_outw, mach64_ext_outl, mach64);
}
}
io_sethandler(0x01ce, 0x0002, mach64_in, NULL, NULL, mach64_out, NULL, NULL, mach64);
if (mach64->use_block_decoded_io && mach64->block_decoded_io && mach64->block_decoded_io < 0x10000)
io_sethandler(mach64->block_decoded_io, 0x0400, mach64_block_inb, mach64_block_inw, mach64_block_inl, mach64_block_outb, mach64_block_outw, mach64_block_outl, mach64);
}
static uint8_t
mach64_read_linear(uint32_t addr, void *priv)
{
const svga_t *svga = (svga_t *) priv;
cycles -= svga->monitor->mon_video_timing_read_b;
addr &= svga->decode_mask;
if (addr >= svga->vram_max)
return 0xff;
return svga->vram[addr & svga->vram_mask];
}
static uint16_t
mach64_readw_linear(uint32_t addr, void *priv)
{
svga_t *svga = (svga_t *) priv;
cycles -= svga->monitor->mon_video_timing_read_w;
addr &= svga->decode_mask;
if (addr >= svga->vram_max)
return 0xffff;
return *(uint16_t *) &svga->vram[addr & svga->vram_mask];
}
static uint32_t
mach64_readl_linear(uint32_t addr, void *priv)
{
svga_t *svga = (svga_t *) priv;
cycles -= svga->monitor->mon_video_timing_read_l;
addr &= svga->decode_mask;
if (addr >= svga->vram_max)
return 0xffffffff;
return *(uint32_t *) &svga->vram[addr & svga->vram_mask];
}
static void
mach64_write_linear(uint32_t addr, uint8_t val, void *priv)
{
svga_t *svga = (svga_t *) priv;
cycles -= svga->monitor->mon_video_timing_write_b;
addr &= svga->decode_mask;
if (addr >= svga->vram_max)
return;
addr &= svga->vram_mask;
svga->changedvram[addr >> 12] = svga->monitor->mon_changeframecount;
svga->vram[addr] = val;
}
static void
mach64_writew_linear(uint32_t addr, uint16_t val, void *priv)
{
svga_t *svga = (svga_t *) priv;
cycles -= svga->monitor->mon_video_timing_write_w;
addr &= svga->decode_mask;
if (addr >= svga->vram_max)
return;
addr &= svga->vram_mask;
svga->changedvram[addr >> 12] = svga->monitor->mon_changeframecount;
*(uint16_t *) &svga->vram[addr] = val;
}
static void
mach64_writel_linear(uint32_t addr, uint32_t val, void *priv)
{
svga_t *svga = (svga_t *) priv;
cycles -= svga->monitor->mon_video_timing_write_l;
addr &= svga->decode_mask;
if (addr >= svga->vram_max)
return;
addr &= svga->vram_mask;
svga->changedvram[addr >> 12] = svga->monitor->mon_changeframecount;
*(uint32_t *) &svga->vram[addr] = val;
}
uint8_t
mach64_pci_read(UNUSED(int func), int addr, void *priv)
{
const mach64_t *mach64 = (mach64_t *) priv;
switch (addr) {
case 0x00:
return 0x02; /*ATi*/
case 0x01:
return 0x10;
case 0x02:
return mach64->pci_id & 0xff;
case 0x03:
return mach64->pci_id >> 8;
case PCI_REG_COMMAND:
return mach64->pci_regs[PCI_REG_COMMAND]; /*Respond to IO and memory accesses*/
case 0x07:
return 1 << 1; /*Medium DEVSEL timing*/
case 0x08: /*Revision ID*/
if (mach64->type == MACH64_GX)
return 0;
return 0x40;
case 0x09:
return 0; /*Programming interface*/
case 0x0a:
return 0x01; /*Supports VGA interface, XGA compatible*/
case 0x0b:
return 0x03;
case 0x10:
return 0x00; /*Linear frame buffer address*/
case 0x11:
return 0x00;
case 0x12:
return mach64->linear_base >> 16;
case 0x13:
return mach64->linear_base >> 24;
case 0x14:
if (mach64->type == MACH64_VT2)
return 0x01; /*Block decoded IO address*/
return 0x00;
case 0x15:
if (mach64->type == MACH64_VT2)
return mach64->block_decoded_io >> 8;
return 0x00;
case 0x16:
if (mach64->type == MACH64_VT2)
return mach64->block_decoded_io >> 16;
return 0x00;
case 0x17:
if (mach64->type == MACH64_VT2)
return mach64->block_decoded_io >> 24;
return 0x00;
case 0x30:
return mach64->pci_regs[0x30] & 0x01; /*BIOS ROM address*/
case 0x31:
return 0x00;
case 0x32:
return mach64->pci_regs[0x32];
case 0x33:
return mach64->pci_regs[0x33];
case 0x3c:
return mach64->int_line;
case 0x3d:
return PCI_INTA;
case 0x40:
return mach64->use_block_decoded_io | mach64->io_base;
default:
break;
}
return 0;
}
void
mach64_pci_write(UNUSED(int func), int addr, uint8_t val, void *priv)
{
mach64_t *mach64 = (mach64_t *) priv;
switch (addr) {
case PCI_REG_COMMAND:
mach64->pci_regs[PCI_REG_COMMAND] = val & 0x27;
if (val & PCI_COMMAND_IO)
mach64_io_set(mach64);
else
mach64_io_remove(mach64);
mach64_updatemapping(mach64);
break;
case 0x12:
if (mach64->type == MACH64_VT2)
val = 0;
mach64->linear_base = (mach64->linear_base & 0xff000000) | ((val & 0x80) << 16);
mach64_updatemapping(mach64);
break;
case 0x13:
mach64->linear_base = (mach64->linear_base & 0x800000) | (val << 24);
mach64_updatemapping(mach64);
break;
case 0x15:
if (mach64->type == MACH64_VT2) {
if (mach64->pci_regs[PCI_REG_COMMAND] & PCI_COMMAND_IO)
mach64_io_remove(mach64);
mach64->block_decoded_io = (mach64->block_decoded_io & 0xffff0000) | ((val & 0xfc) << 8);
if (mach64->pci_regs[PCI_REG_COMMAND] & PCI_COMMAND_IO)
mach64_io_set(mach64);
}
break;
case 0x16:
if (mach64->type == MACH64_VT2) {
if (mach64->pci_regs[PCI_REG_COMMAND] & PCI_COMMAND_IO)
mach64_io_remove(mach64);
mach64->block_decoded_io = (mach64->block_decoded_io & 0xff00fc00) | (val << 16);
if (mach64->pci_regs[PCI_REG_COMMAND] & PCI_COMMAND_IO)
mach64_io_set(mach64);
}
break;
case 0x17:
if (mach64->type == MACH64_VT2) {
if (mach64->pci_regs[PCI_REG_COMMAND] & PCI_COMMAND_IO)
mach64_io_remove(mach64);
mach64->block_decoded_io = (mach64->block_decoded_io & 0x00fffc00) | (val << 24);
if (mach64->pci_regs[PCI_REG_COMMAND] & PCI_COMMAND_IO)
mach64_io_set(mach64);
}
break;
case 0x30:
case 0x32:
case 0x33:
mach64->pci_regs[addr] = val;
if (mach64->pci_regs[0x30] & 0x01) {
uint32_t biosaddr = (mach64->pci_regs[0x32] << 16) | (mach64->pci_regs[0x33] << 24);
mach64_log("Mach64 bios_rom enabled at %08x\n", biosaddr);
mem_mapping_set_addr(&mach64->bios_rom.mapping, biosaddr, 0x8000);
} else {
mach64_log("Mach64 bios_rom disabled\n");
mem_mapping_disable(&mach64->bios_rom.mapping);
}
return;
case 0x3c:
mach64->int_line = val;
break;
case 0x40:
if (mach64->pci_regs[PCI_REG_COMMAND] & PCI_COMMAND_IO)
mach64_io_remove(mach64);
mach64->io_base = val & 0x03;
if (mach64->type == MACH64_VT2)
mach64->use_block_decoded_io = val & 0x04;
if (mach64->pci_regs[PCI_REG_COMMAND] & PCI_COMMAND_IO)
mach64_io_set(mach64);
break;
default:
break;
}
}
static void *
mach64_common_init(const device_t *info)
{
svga_t *svga;
mach64_t *mach64 = malloc(sizeof(mach64_t));
memset(mach64, 0, sizeof(mach64_t));
svga = &mach64->svga;
mach64->vram_size = device_get_config_int("memory");
mach64->vram_mask = (mach64->vram_size << 20) - 1;
svga_init(info, svga, mach64, mach64->vram_size << 20,
mach64_recalctimings,
mach64_in, mach64_out,
NULL,
mach64_overlay_draw);
svga->dac_hwcursor.cur_ysize = 64;
mem_mapping_add(&mach64->linear_mapping, 0, 0, mach64_read_linear, mach64_readw_linear, mach64_readl_linear, mach64_write_linear, mach64_writew_linear, mach64_writel_linear, NULL, MEM_MAPPING_EXTERNAL, svga);
mem_mapping_add(&mach64->mmio_linear_mapping, 0, 0, mach64_ext_readb, mach64_ext_readw, mach64_ext_readl, mach64_ext_writeb, mach64_ext_writew, mach64_ext_writel, NULL, MEM_MAPPING_EXTERNAL, mach64);
mem_mapping_add(&mach64->mmio_linear_mapping_2, 0, 0, mach64_ext_readb, mach64_ext_readw, mach64_ext_readl, mach64_ext_writeb, mach64_ext_writew, mach64_ext_writel, NULL, MEM_MAPPING_EXTERNAL, mach64);
mem_mapping_add(&mach64->mmio_mapping, 0xbc000, 0x04000, mach64_ext_readb, mach64_ext_readw, mach64_ext_readl, mach64_ext_writeb, mach64_ext_writew, mach64_ext_writel, NULL, MEM_MAPPING_EXTERNAL, mach64);
mem_mapping_disable(&mach64->mmio_mapping);
mach64_io_set(mach64);
if (info->flags & DEVICE_PCI)
pci_add_card(PCI_ADD_NORMAL, mach64_pci_read, mach64_pci_write, mach64, &mach64->pci_slot);
mach64->pci_regs[PCI_REG_COMMAND] = 3;
mach64->pci_regs[0x30] = 0x00;
mach64->pci_regs[0x32] = 0x0c;
mach64->pci_regs[0x33] = 0x00;
svga->ramdac = device_add(&ati68860_ramdac_device);
svga->dac_hwcursor_draw = ati68860_hwcursor_draw;
svga->clock_gen = device_add(&ics2595_device);
mach64->dst_cntl = 3;
mach64->i2c = i2c_gpio_init("ddc_ati_mach64");
mach64->ddc = ddc_init(i2c_gpio_get_bus(mach64->i2c));
return mach64;
}
static void *
mach64gx_init(const device_t *info)
{
mach64_t *mach64 = mach64_common_init(info);
if (info->flags & DEVICE_ISA)
video_inform(VIDEO_FLAG_TYPE_SPECIAL, &timing_mach64_isa);
else if (info->flags & DEVICE_PCI)
video_inform(VIDEO_FLAG_TYPE_SPECIAL, &timing_mach64_pci);
else
video_inform(VIDEO_FLAG_TYPE_SPECIAL, &timing_mach64_vlb);
mach64->type = MACH64_GX;
mach64->pci = !!(info->flags & DEVICE_PCI);
mach64->pci_id = 'X' | ('G' << 8);
mach64->config_chip_id = 0x000000d7;
mach64->dac_cntl = 5 << 16; /*ATI 68860 RAMDAC*/
mach64->config_stat0 = (5 << 9) | (3 << 3); /*ATI-68860, 256Kx16 DRAM*/
if (info->flags & DEVICE_PCI) {
mach64->config_stat0 |= 7; /*PCI, 256Kx16 DRAM*/
ati_eeprom_load(&mach64->eeprom, "mach64_pci.nvr", 1);
rom_init(&mach64->bios_rom, BIOS_ROM_PATH, 0xc0000, 0x8000, 0x7fff, 0, MEM_MAPPING_EXTERNAL);
mem_mapping_disable(&mach64->bios_rom.mapping);
} else if (info->flags & DEVICE_VLB) {
mach64->config_stat0 |= 6; /*VLB, 256Kx16 DRAM*/
ati_eeprom_load(&mach64->eeprom, "mach64_vlb.nvr", 1);
rom_init(&mach64->bios_rom, BIOS_VLB_ROM_PATH, 0xc0000, 0x8000, 0x7fff, 0, MEM_MAPPING_EXTERNAL);
} else if (info->flags & DEVICE_ISA) {
mach64->config_stat0 |= 0; /*ISA 16-bit, 256k16 DRAM*/
ati_eeprom_load(&mach64->eeprom, "mach64.nvr", 1);
rom_init(&mach64->bios_rom, BIOS_ISA_ROM_PATH, 0xc0000, 0x8000, 0x7fff, 0, MEM_MAPPING_EXTERNAL);
}
return mach64;
}
static void *
mach64vt2_init(const device_t *info)
{
mach64_t *mach64 = mach64_common_init(info);
svga_t *svga = &mach64->svga;
video_inform(VIDEO_FLAG_TYPE_SPECIAL, &timing_mach64_pci);
mach64->type = MACH64_VT2;
mach64->pci = 1;
mach64->pci_id = 0x5654;
mach64->config_chip_id = 0x40005654;
mach64->dac_cntl = 1 << 16; /*Internal 24-bit DAC*/
mach64->config_stat0 = 4;
mach64->use_block_decoded_io = 4;
ati_eeprom_load(&mach64->eeprom, "mach64vt.nvr", 1);
rom_init(&mach64->bios_rom, BIOS_ROMVT2_PATH, 0xc0000, 0x8000, 0x7fff, 0, MEM_MAPPING_EXTERNAL);
mem_mapping_disable(&mach64->bios_rom.mapping);
svga->vblank_start = mach64_vblank_start;
return mach64;
}
int
mach64gx_available(void)
{
return rom_present(BIOS_ROM_PATH);
}
int
mach64gx_isa_available(void)
{
return rom_present(BIOS_ISA_ROM_PATH);
}
int
mach64gx_vlb_available(void)
{
return rom_present(BIOS_VLB_ROM_PATH);
}
int
mach64vt2_available(void)
{
return rom_present(BIOS_ROMVT2_PATH);
}
void
mach64_close(void *priv)
{
mach64_t *mach64 = (mach64_t *) priv;
svga_close(&mach64->svga);
ddc_close(mach64->ddc);
i2c_gpio_close(mach64->i2c);
free(mach64);
}
void
mach64_speed_changed(void *priv)
{
mach64_t *mach64 = (mach64_t *) priv;
svga_recalctimings(&mach64->svga);
}
void
mach64_force_redraw(void *priv)
{
mach64_t *mach64 = (mach64_t *) priv;
mach64->svga.fullchange = mach64->svga.monitor->mon_changeframecount;
}
// clang-format off
static const device_config_t mach64gx_config[] = {
{
.name = "memory",
.description = "Memory size",
.type = CONFIG_SELECTION,
.default_int = 4,
.selection = {
{
.description = "1 MB",
.value = 1
},
{
.description = "2 MB",
.value = 2
},
{
.description = "4 MB",
.value = 4
},
{
.description = ""
}
}
},
{
.type = CONFIG_END
}
};
static const device_config_t mach64vt2_config[] = {
{
.name = "memory",
.description = "Memory size",
.type = CONFIG_SELECTION,
.default_int = 4,
.selection = {
{
.description = "2 MB",
.value = 2
},
{
.description = "4 MB",
.value = 4
},
{
.description = ""
}
}
},
{
.type = CONFIG_END
}
};
// clang-format on
const device_t mach64gx_isa_device = {
.name = "ATI Mach64GX ISA",
.internal_name = "mach64gx_isa",
.flags = DEVICE_AT | DEVICE_ISA,
.local = 0,
.init = mach64gx_init,
.close = mach64_close,
.reset = NULL,
{ .available = mach64gx_isa_available },
.speed_changed = mach64_speed_changed,
.force_redraw = mach64_force_redraw,
.config = mach64gx_config
};
const device_t mach64gx_vlb_device = {
.name = "ATI Mach64GX VLB",
.internal_name = "mach64gx_vlb",
.flags = DEVICE_VLB,
.local = 0,
.init = mach64gx_init,
.close = mach64_close,
.reset = NULL,
{ .available = mach64gx_vlb_available },
.speed_changed = mach64_speed_changed,
.force_redraw = mach64_force_redraw,
.config = mach64gx_config
};
const device_t mach64gx_pci_device = {
.name = "ATI Mach64GX PCI",
.internal_name = "mach64gx_pci",
.flags = DEVICE_PCI,
.local = 0,
.init = mach64gx_init,
.close = mach64_close,
.reset = NULL,
{ .available = mach64gx_available },
.speed_changed = mach64_speed_changed,
.force_redraw = mach64_force_redraw,
.config = mach64gx_config
};
const device_t mach64vt2_device = {
.name = "ATI Mach64VT2",
.internal_name = "mach64vt2",
.flags = DEVICE_PCI,
.local = 0,
.init = mach64vt2_init,
.close = mach64_close,
.reset = NULL,
{ .available = mach64vt2_available },
.speed_changed = mach64_speed_changed,
.force_redraw = mach64_force_redraw,
.config = mach64vt2_config
};
``` | /content/code_sandbox/src/video/vid_ati_mach64.c | c | 2016-06-25T22:29:10 | 2024-08-16T19:09:21 | 86Box | 86Box/86Box | 2,616 | 46,119 |
```c
/*Current issues :
- missing screen->screen scaled blits with format conversion
- missing YUV blits (YUV -> 32-bit, 24-bit, or 16-bit RGB now done)
- missing linestyle
- missing wait for vsync
- missing reversible lines
Notes :
- 16 bpp runs with tiled framebuffer - to aid 3D?
8 and 32 bpp use linear
*/
#include <stdarg.h>
#include <stdio.h>
#include <stdint.h>
#include <string.h>
#include <stdlib.h>
#include <stddef.h>
#include <wchar.h>
#include <math.h>
#define HAVE_STDARG_H
#include <86box/86box.h>
#include "cpu.h"
#include <86box/machine.h>
#include <86box/device.h>
#include <86box/mem.h>
#include <86box/timer.h>
#include <86box/device.h>
#include <86box/plat.h>
#include <86box/thread.h>
#include <86box/video.h>
#include <86box/vid_svga.h>
#include <86box/vid_voodoo_common.h>
#include <86box/vid_voodoo_banshee_blitter.h>
#include <86box/vid_voodoo_render.h>
#define COMMAND_CMD_MASK (0xf)
#define COMMAND_CMD_NOP (0 << 0)
#define COMMAND_CMD_SCREEN_TO_SCREEN_BLT (1 << 0)
#define COMMAND_CMD_SCREEN_TO_SCREEN_STRETCH_BLT (2 << 0)
#define COMMAND_CMD_HOST_TO_SCREEN_BLT (3 << 0)
#define COMMAND_CMD_HOST_TO_SCREEN_STRETCH_BLT (4 << 0)
#define COMMAND_CMD_RECTFILL (5 << 0)
#define COMMAND_CMD_LINE (6 << 0)
#define COMMAND_CMD_POLYLINE (7 << 0)
#define COMMAND_CMD_POLYFILL (8 << 0)
#define COMMAND_INITIATE (1 << 8)
#define COMMAND_INC_X_START (1 << 10)
#define COMMAND_INC_Y_START (1 << 11)
#define COMMAND_STIPPLE_LINE (1 << 12)
#define COMMAND_PATTERN_MONO (1 << 13)
#define COMMAND_DX (1 << 14)
#define COMMAND_DY (1 << 15)
#define COMMAND_TRANS_MONO (1 << 16)
#define COMMAND_PATOFF_X_MASK (7 << 17)
#define COMMAND_PATOFF_X_SHIFT (17)
#define COMMAND_PATOFF_Y_MASK (7 << 20)
#define COMMAND_PATOFF_Y_SHIFT (20)
#define COMMAND_CLIP_SEL (1 << 23)
#define CMDEXTRA_SRC_COLORKEY (1 << 0)
#define CMDEXTRA_DST_COLORKEY (1 << 1)
#define CMDEXTRA_FORCE_PAT_ROW0 (1 << 3)
#define SRC_FORMAT_STRIDE_MASK (0x1fff)
#define SRC_FORMAT_COL_MASK (0xf << 16)
#define SRC_FORMAT_COL_1_BPP (0 << 16)
#define SRC_FORMAT_COL_8_BPP (1 << 16)
#define SRC_FORMAT_COL_16_BPP (3 << 16)
#define SRC_FORMAT_COL_24_BPP (4 << 16)
#define SRC_FORMAT_COL_32_BPP (5 << 16)
#define SRC_FORMAT_COL_YUYV (8 << 16)
#define SRC_FORMAT_COL_UYVY (9 << 16)
#define SRC_FORMAT_BYTE_SWIZZLE (1 << 20)
#define SRC_FORMAT_WORD_SWIZZLE (1 << 21)
#define SRC_FORMAT_PACKING_MASK (3 << 22)
#define SRC_FORMAT_PACKING_STRIDE (0 << 22)
#define SRC_FORMAT_PACKING_BYTE (1 << 22)
#define SRC_FORMAT_PACKING_WORD (2 << 22)
#define SRC_FORMAT_PACKING_DWORD (3 << 22)
#define DST_FORMAT_STRIDE_MASK (0x1fff)
#define DST_FORMAT_COL_MASK (0xf << 16)
#define DST_FORMAT_COL_8_BPP (1 << 16)
#define DST_FORMAT_COL_16_BPP (3 << 16)
#define DST_FORMAT_COL_24_BPP (4 << 16)
#define DST_FORMAT_COL_32_BPP (5 << 16)
#define BRES_ERROR_MASK (0xffff)
#define BRES_ERROR_USE (1 << 31)
enum {
COLORKEY_8,
COLORKEY_16,
COLORKEY_32
};
#ifdef ENABLE_BANSHEEBLT_LOG
int bansheeblt_do_log = ENABLE_BANSHEEBLT_LOG;
static void
bansheeblt_log(const char *fmt, ...)
{
va_list ap;
if (bansheeblt_do_log) {
va_start(ap, fmt);
pclog_ex(fmt, ap);
va_end(ap);
}
}
#else
# define bansheeblt_log(fmt, ...)
#endif
static int
colorkey(voodoo_t *voodoo, uint32_t src, int src_notdst, int color_format)
{
uint32_t min = src_notdst ? voodoo->banshee_blt.srcColorkeyMin : voodoo->banshee_blt.dstColorkeyMin;
uint32_t max = src_notdst ? voodoo->banshee_blt.srcColorkeyMax : voodoo->banshee_blt.dstColorkeyMax;
if (!(voodoo->banshee_blt.commandExtra & (src_notdst ? CMDEXTRA_SRC_COLORKEY : CMDEXTRA_DST_COLORKEY)))
return 0;
switch (color_format) {
case COLORKEY_8:
return ((src & 0xff) >= (min & 0xff)) && ((src & 0xff) <= (max & 0xff));
case COLORKEY_16:
{
int r = (src >> 11) & 0x1f;
int r_min = (min >> 11) & 0x1f;
int r_max = (max >> 11) & 0x1f;
int g = (src >> 5) & 0x3f;
int g_min = (min >> 5) & 0x3f;
int g_max = (max >> 5) & 0x3f;
int b = src & 0x1f;
int b_min = min & 0x1f;
int b_max = max & 0x1f;
return (r >= r_min) && (r <= r_max) && (g >= g_min) && (g <= g_max) && (b >= b_min) && (b <= b_max);
}
case COLORKEY_32:
{
int r = (src >> 16) & 0xff;
int r_min = (min >> 16) & 0xff;
int r_max = (max >> 16) & 0xff;
int g = (src >> 8) & 0xff;
int g_min = (min >> 8) & 0xff;
int g_max = (max >> 8) & 0xff;
int b = src & 0xff;
int b_min = min & 0xff;
int b_max = max & 0xff;
return (r >= r_min) && (r <= r_max) && (g >= g_min) && (g <= g_max) && (b >= b_min) && (b <= b_max);
}
default:
return 0;
}
}
static uint32_t
MIX(voodoo_t *voodoo, uint32_t dest, uint32_t src, uint32_t pattern, int colour_format_src, int colour_format_dest)
{
int rop_nr = 0;
uint32_t result = 0;
uint32_t rop;
if (colorkey(voodoo, src, 1, colour_format_src))
rop_nr |= 2;
if (colorkey(voodoo, dest, 0, colour_format_dest))
rop_nr |= 1;
rop = voodoo->banshee_blt.rops[rop_nr];
if (rop & 0x01)
result |= (~pattern & ~src & ~dest);
if (rop & 0x02)
result |= (~pattern & ~src & dest);
if (rop & 0x04)
result |= (~pattern & src & ~dest);
if (rop & 0x08)
result |= (~pattern & src & dest);
if (rop & 0x10)
result |= (pattern & ~src & ~dest);
if (rop & 0x20)
result |= (pattern & ~src & dest);
if (rop & 0x40)
result |= (pattern & src & ~dest);
if (rop & 0x80)
result |= (pattern & src & dest);
return result;
}
static uint32_t
get_addr(voodoo_t *voodoo, int x, int y, int src_notdst, uint32_t src_stride)
{
uint32_t stride = src_notdst ? src_stride : voodoo->banshee_blt.dst_stride;
uint32_t base_addr = src_notdst ? voodoo->banshee_blt.srcBaseAddr : voodoo->banshee_blt.dstBaseAddr;
if (src_notdst ? voodoo->banshee_blt.srcBaseAddr_tiled : voodoo->banshee_blt.dstBaseAddr_tiled)
return (base_addr + (x & 127) + ((x >> 7) * 128 * 32) + ((y & 31) * 128) + (y >> 5) * stride) & voodoo->fb_mask;
else
return (base_addr + x + y * stride) & voodoo->fb_mask;
}
static void
PLOT(voodoo_t *voodoo, int x, int y, int pat_x, int pat_y, uint8_t pattern_mask, UNUSED(uint8_t rop), uint32_t src, int src_colorkey)
{
switch (voodoo->banshee_blt.dstFormat & DST_FORMAT_COL_MASK) {
case DST_FORMAT_COL_8_BPP:
{
uint32_t addr = get_addr(voodoo, x, y, 0, 0); //(voodoo->banshee_blt.dstBaseAddr + x + y*voodoo->banshee_blt.dst_stride) & voodoo->fb_mask;
uint32_t dest = voodoo->vram[addr];
uint32_t pattern = (voodoo->banshee_blt.command & COMMAND_PATTERN_MONO) ? ((pattern_mask & (1 << (7 - (pat_x & 7)))) ? voodoo->banshee_blt.colorFore : voodoo->banshee_blt.colorBack) : voodoo->banshee_blt.colorPattern8[(pat_x & 7) + (pat_y & 7) * 8];
if (addr > voodoo->fb_mask)
break;
voodoo->vram[addr] = MIX(voodoo, dest, src, pattern, src_colorkey, COLORKEY_8);
voodoo->changedvram[addr >> 12] = changeframecount;
break;
}
case DST_FORMAT_COL_16_BPP:
{
uint32_t addr = get_addr(voodoo, x * 2, y, 0, 0); //(voodoo->banshee_blt.dstBaseAddr + x*2 + y*voodoo->banshee_blt.dst_stride) & voodoo->fb_mask;
uint32_t dest = *(uint16_t *) &voodoo->vram[addr];
uint32_t pattern = (voodoo->banshee_blt.command & COMMAND_PATTERN_MONO) ? ((pattern_mask & (1 << (7 - (pat_x & 7)))) ? voodoo->banshee_blt.colorFore : voodoo->banshee_blt.colorBack) : voodoo->banshee_blt.colorPattern16[(pat_x & 7) + (pat_y & 7) * 8];
if (addr > voodoo->fb_mask)
break;
*(uint16_t *) &voodoo->vram[addr] = MIX(voodoo, dest, src, pattern, src_colorkey, COLORKEY_16);
voodoo->changedvram[addr >> 12] = changeframecount;
break;
}
case DST_FORMAT_COL_24_BPP:
{
uint32_t addr = get_addr(voodoo, x * 3, y, 0, 0); //(voodoo->banshee_blt.dstBaseAddr + x*3 + y*voodoo->banshee_blt.dst_stride) & voodoo->fb_mask;
uint32_t dest = *(uint32_t *) &voodoo->vram[addr];
uint32_t pattern = (voodoo->banshee_blt.command & COMMAND_PATTERN_MONO) ? ((pattern_mask & (1 << (7 - (pat_x & 7)))) ? voodoo->banshee_blt.colorFore : voodoo->banshee_blt.colorBack) : voodoo->banshee_blt.colorPattern24[(pat_x & 7) + (pat_y & 7) * 8];
if (addr > voodoo->fb_mask)
break;
*(uint32_t *) &voodoo->vram[addr] = (MIX(voodoo, dest, src, pattern, src_colorkey, COLORKEY_32) & 0xffffff) | (dest & 0xff000000);
voodoo->changedvram[addr >> 12] = changeframecount;
break;
}
case DST_FORMAT_COL_32_BPP:
{
uint32_t addr = get_addr(voodoo, x * 4, y, 0, 0); //(voodoo->banshee_blt.dstBaseAddr + x*4 + y*voodoo->banshee_blt.dst_stride) & voodoo->fb_mask;
uint32_t dest = *(uint32_t *) &voodoo->vram[addr];
uint32_t pattern = (voodoo->banshee_blt.command & COMMAND_PATTERN_MONO) ? ((pattern_mask & (1 << (7 - (pat_x & 7)))) ? voodoo->banshee_blt.colorFore : voodoo->banshee_blt.colorBack) : voodoo->banshee_blt.colorPattern[(pat_x & 7) + (pat_y & 7) * 8];
if (addr > voodoo->fb_mask)
break;
*(uint32_t *) &voodoo->vram[addr] = MIX(voodoo, dest, src, pattern, src_colorkey, COLORKEY_32);
voodoo->changedvram[addr >> 12] = changeframecount;
break;
}
default:
break;
}
}
static void
PLOT_LINE(voodoo_t *voodoo, int x, int y, UNUSED(uint8_t rop), uint32_t pattern, int src_colorkey)
{
switch (voodoo->banshee_blt.dstFormat & DST_FORMAT_COL_MASK) {
case DST_FORMAT_COL_8_BPP:
{
uint32_t addr = get_addr(voodoo, x, y, 0, 0); //(voodoo->banshee_blt.dstBaseAddr + x + y*voodoo->banshee_blt.dst_stride) & voodoo->fb_mask;
uint32_t dest = voodoo->vram[addr];
if (addr > voodoo->fb_mask)
break;
voodoo->vram[addr] = MIX(voodoo, dest, voodoo->banshee_blt.colorFore, pattern, src_colorkey, COLORKEY_8);
voodoo->changedvram[addr >> 12] = changeframecount;
break;
}
case DST_FORMAT_COL_16_BPP:
{
uint32_t addr = get_addr(voodoo, x * 2, y, 0, 0); //(voodoo->banshee_blt.dstBaseAddr + x*2 + y*voodoo->banshee_blt.dst_stride) & voodoo->fb_mask;
uint32_t dest = *(uint16_t *) &voodoo->vram[addr];
if (addr > voodoo->fb_mask)
break;
*(uint16_t *) &voodoo->vram[addr] = MIX(voodoo, dest, voodoo->banshee_blt.colorFore, pattern, src_colorkey, COLORKEY_16);
voodoo->changedvram[addr >> 12] = changeframecount;
break;
}
case DST_FORMAT_COL_24_BPP:
{
uint32_t addr = get_addr(voodoo, x * 3, y, 0, 0); //(voodoo->banshee_blt.dstBaseAddr + x*3 + y*voodoo->banshee_blt.dst_stride) & voodoo->fb_mask;
uint32_t dest = *(uint32_t *) &voodoo->vram[addr];
if (addr > voodoo->fb_mask)
break;
*(uint32_t *) &voodoo->vram[addr] = (MIX(voodoo, dest, voodoo->banshee_blt.colorFore, pattern, src_colorkey, COLORKEY_32) & 0xffffff) | (dest & 0xff000000);
voodoo->changedvram[addr >> 12] = changeframecount;
break;
}
case DST_FORMAT_COL_32_BPP:
{
uint32_t addr = get_addr(voodoo, x * 4, y, 0, 0); //(voodoo->banshee_blt.dstBaseAddr + x*4 + y*voodoo->banshee_blt.dst_stride) & voodoo->fb_mask;
uint32_t dest = *(uint32_t *) &voodoo->vram[addr];
if (addr > voodoo->fb_mask)
break;
*(uint32_t *) &voodoo->vram[addr] = MIX(voodoo, dest, voodoo->banshee_blt.colorFore, pattern, src_colorkey, COLORKEY_32);
voodoo->changedvram[addr >> 12] = changeframecount;
break;
}
default:
break;
}
}
static void
update_src_stride(voodoo_t *voodoo)
{
int bpp;
switch (voodoo->banshee_blt.srcFormat & SRC_FORMAT_COL_MASK) {
case SRC_FORMAT_COL_1_BPP:
bpp = 1;
break;
case SRC_FORMAT_COL_8_BPP:
bpp = 8;
break;
case SRC_FORMAT_COL_16_BPP:
bpp = 16;
break;
case SRC_FORMAT_COL_24_BPP:
bpp = 24;
break;
case SRC_FORMAT_COL_32_BPP:
case SRC_FORMAT_COL_YUYV:
case SRC_FORMAT_COL_UYVY:
bpp = 32;
break;
default:
bpp = 16;
break;
}
switch (voodoo->banshee_blt.srcFormat & SRC_FORMAT_PACKING_MASK) {
case SRC_FORMAT_PACKING_STRIDE:
voodoo->banshee_blt.src_stride_src = voodoo->banshee_blt.src_stride; // voodoo->banshee_blt.srcFormat & SRC_FORMAT_STRIDE_MASK;
voodoo->banshee_blt.src_stride_dest = voodoo->banshee_blt.src_stride; // voodoo->banshee_blt.srcFormat & SRC_FORMAT_STRIDE_MASK;
voodoo->banshee_blt.host_data_size_src = (voodoo->banshee_blt.srcSizeX * bpp + 7) >> 3;
voodoo->banshee_blt.host_data_size_dest = (voodoo->banshee_blt.dstSizeX * bpp + 7) >> 3;
#if 0
bansheeblt_log("Stride packing %08x %08x bpp=%i dstSizeX=%i\n", voodoo->banshee_blt.src_stride_dest, voodoo->banshee_blt.host_data_size_dest, bpp, voodoo->banshee_blt.dstSizeX);
#endif
break;
case SRC_FORMAT_PACKING_BYTE:
voodoo->banshee_blt.src_stride_src = (voodoo->banshee_blt.srcSizeX * bpp + 7) >> 3;
voodoo->banshee_blt.src_stride_dest = (voodoo->banshee_blt.dstSizeX * bpp + 7) >> 3;
voodoo->banshee_blt.host_data_size_src = voodoo->banshee_blt.src_stride_src;
voodoo->banshee_blt.host_data_size_dest = voodoo->banshee_blt.src_stride_dest;
#if 0
bansheeblt_log("Byte packing %08x %08x\n", voodoo->banshee_blt.src_stride_dest, voodoo->banshee_blt.host_data_size_dest);
#endif
break;
case SRC_FORMAT_PACKING_WORD:
voodoo->banshee_blt.src_stride_src = ((voodoo->banshee_blt.srcSizeX * bpp + 15) >> 4) * 2;
voodoo->banshee_blt.src_stride_dest = ((voodoo->banshee_blt.dstSizeX * bpp + 15) >> 4) * 2;
voodoo->banshee_blt.host_data_size_src = voodoo->banshee_blt.src_stride_src;
voodoo->banshee_blt.host_data_size_dest = voodoo->banshee_blt.src_stride_dest;
#if 0
bansheeblt_log("Word packing %08x %08x\n", voodoo->banshee_blt.src_stride_dest, voodoo->banshee_blt.host_data_size_dest);
#endif
break;
case SRC_FORMAT_PACKING_DWORD:
voodoo->banshee_blt.src_stride_src = ((voodoo->banshee_blt.srcSizeX * bpp + 31) >> 5) * 4;
voodoo->banshee_blt.src_stride_dest = ((voodoo->banshee_blt.dstSizeX * bpp + 31) >> 5) * 4;
voodoo->banshee_blt.host_data_size_src = voodoo->banshee_blt.src_stride_src;
voodoo->banshee_blt.host_data_size_dest = voodoo->banshee_blt.src_stride_dest;
#if 0
bansheeblt_log("Dword packing %08x %08x\n", voodoo->banshee_blt.src_stride_dest, voodoo->banshee_blt.host_data_size_dest);
#endif
break;
default:
break;
}
}
static void
end_command(voodoo_t *voodoo)
{
/*Update dest coordinates if required*/
if (voodoo->banshee_blt.command & COMMAND_INC_X_START) {
voodoo->banshee_blt.dstXY &= ~0x0000ffff;
voodoo->banshee_blt.dstXY |= (voodoo->banshee_blt.dstX & 0xffff);
}
if (voodoo->banshee_blt.command & COMMAND_INC_Y_START) {
voodoo->banshee_blt.dstXY &= ~0xffff0000;
voodoo->banshee_blt.dstXY |= (voodoo->banshee_blt.dstY << 16);
}
}
static void
banshee_do_rectfill(voodoo_t *voodoo)
{
const clip_t *clip = &voodoo->banshee_blt.clip[(voodoo->banshee_blt.command & COMMAND_CLIP_SEL) ? 1 : 0];
int dst_y = voodoo->banshee_blt.dstY;
const uint8_t *pattern_mono = (uint8_t *) voodoo->banshee_blt.colorPattern;
int pat_y = (voodoo->banshee_blt.commandExtra & CMDEXTRA_FORCE_PAT_ROW0) ? 0 : (voodoo->banshee_blt.patoff_y + voodoo->banshee_blt.dstY);
int use_pattern_trans = (voodoo->banshee_blt.command & (COMMAND_PATTERN_MONO | COMMAND_TRANS_MONO)) == (COMMAND_PATTERN_MONO | COMMAND_TRANS_MONO);
uint8_t rop = voodoo->banshee_blt.command >> 24;
#if 0
bansheeblt_log("banshee_do_rectfill: size=%i,%i dst=%i,%i\n", voodoo->banshee_blt.dstSizeX, voodoo->banshee_blt.dstSizeY, voodoo->banshee_blt.dstX, voodoo->banshee_blt.dstY);
bansheeblt_log("clipping: %i,%i -> %i,%i\n", clip->x_min, clip->y_min, clip->x_max, clip->y_max);
bansheeblt_log("colorFore=%08x\n", voodoo->banshee_blt.colorFore);
#endif
for (voodoo->banshee_blt.cur_y = 0; voodoo->banshee_blt.cur_y < voodoo->banshee_blt.dstSizeY; voodoo->banshee_blt.cur_y++) {
int dst_x = voodoo->banshee_blt.dstX;
if (dst_y >= clip->y_min && dst_y < clip->y_max) {
int pat_x = voodoo->banshee_blt.patoff_x + voodoo->banshee_blt.dstX;
uint8_t pattern_mask = pattern_mono[pat_y & 7];
for (voodoo->banshee_blt.cur_x = 0; voodoo->banshee_blt.cur_x < voodoo->banshee_blt.dstSizeX; voodoo->banshee_blt.cur_x++) {
int pattern_trans = use_pattern_trans ? (pattern_mask & (1 << (7 - (pat_x & 7)))) : 1;
if (dst_x >= clip->x_min && dst_x < clip->x_max && pattern_trans)
PLOT(voodoo, dst_x, dst_y, pat_x, pat_y, pattern_mask, rop, voodoo->banshee_blt.colorFore, COLORKEY_32);
dst_x += (voodoo->banshee_blt.command & COMMAND_DX) ? -1 : 1;
pat_x += (voodoo->banshee_blt.command & COMMAND_DX) ? -1 : 1;
}
}
dst_y += (voodoo->banshee_blt.command & COMMAND_DY) ? -1 : 1;
if (!(voodoo->banshee_blt.commandExtra & CMDEXTRA_FORCE_PAT_ROW0))
pat_y += (voodoo->banshee_blt.command & COMMAND_DY) ? -1 : 1;
}
end_command(voodoo);
}
void
DECODE_YUYV422(uint32_t *buf, uint8_t *src)
{
do {
int wp = 0;
uint8_t y1;
uint8_t y2;
int8_t Cr;
int8_t Cb;
int dR;
int dG;
int dB;
int r;
int g;
int b;
y1 = src[0];
Cr = src[1] - 0x80;
y2 = src[2];
Cb = src[3] - 0x80;
dR = (359 * Cr) >> 8;
dG = (88 * Cb + 183 * Cr) >> 8;
dB = (453 * Cb) >> 8;
r = y1 + dR;
r = CLAMP(r);
g = y1 - dG;
g = CLAMP(g);
b = y1 + dB;
b = CLAMP(b);
buf[wp++] = r | (g << 8) | (b << 16);
r = y2 + dR;
r = CLAMP(r);
g = y2 - dG;
g = CLAMP(g);
b = y2 + dB;
b = CLAMP(b);
buf[wp++] = r | (g << 8) | (b << 16);
} while (0);
}
void
DECODE_YUYV422_16BPP(uint16_t *buf, uint8_t *src)
{
do {
int wp = 0;
uint8_t y1;
uint8_t y2;
int8_t Cr;
int8_t Cb;
int dR;
int dG;
int dB;
int r;
int g;
int b;
y1 = src[0];
Cr = src[1] - 0x80;
y2 = src[2];
Cb = src[3] - 0x80;
dR = (359 * Cr) >> 8;
dG = (88 * Cb + 183 * Cr) >> 8;
dB = (453 * Cb) >> 8;
r = y1 + dR;
r = CLAMP(r);
r >>= 3;
g = y1 - dG;
g = CLAMP(g);
g >>= 2;
b = y1 + dB;
b = CLAMP(b);
b >>= 3;
buf[wp++] = r | (g << 5) | (b << 11);
r = y2 + dR;
r = CLAMP(r);
r >>= 3;
g = y2 - dG;
g = CLAMP(g);
g >>= 2;
b = y2 + dB;
b = CLAMP(b);
b >>= 3;
buf[wp++] = r | (g << 5) | (b << 11);
} while (0);
}
static void
do_screen_to_screen_line(voodoo_t *voodoo, uint8_t *src_p, int use_x_dir, int src_x, int src_tiled)
{
const clip_t *clip = &voodoo->banshee_blt.clip[(voodoo->banshee_blt.command & COMMAND_CLIP_SEL) ? 1 : 0];
int dst_y = voodoo->banshee_blt.dstY;
int pat_y = (voodoo->banshee_blt.commandExtra & CMDEXTRA_FORCE_PAT_ROW0) ? 0 : (voodoo->banshee_blt.patoff_y + voodoo->banshee_blt.dstY);
const uint8_t *pattern_mono = (uint8_t *) voodoo->banshee_blt.colorPattern;
int use_pattern_trans = (voodoo->banshee_blt.command & (COMMAND_PATTERN_MONO | COMMAND_TRANS_MONO)) == (COMMAND_PATTERN_MONO | COMMAND_TRANS_MONO);
uint8_t rop = voodoo->banshee_blt.command >> 24;
int src_colorkey;
switch (voodoo->banshee_blt.srcFormat & SRC_FORMAT_COL_MASK) {
case SRC_FORMAT_COL_8_BPP:
src_colorkey = COLORKEY_8;
break;
case SRC_FORMAT_COL_16_BPP:
src_colorkey = COLORKEY_16;
break;
default:
src_colorkey = COLORKEY_32;
break;
}
#if 0
bansheeblt_log("do_screen_to_screen_line: srcFormat=%08x dst=%08x\n", voodoo->banshee_blt.srcFormat, voodoo->banshee_blt.dstFormat);
#endif
if ((voodoo->banshee_blt.srcFormat & SRC_FORMAT_COL_MASK) == (voodoo->banshee_blt.dstFormat & DST_FORMAT_COL_MASK)) {
/*No conversion required*/
if (dst_y >= clip->y_min && dst_y < clip->y_max) {
int dst_x = voodoo->banshee_blt.dstX;
int pat_x = voodoo->banshee_blt.patoff_x + voodoo->banshee_blt.dstX;
uint8_t pattern_mask = pattern_mono[pat_y & 7];
for (voodoo->banshee_blt.cur_x = 0; voodoo->banshee_blt.cur_x < voodoo->banshee_blt.dstSizeX; voodoo->banshee_blt.cur_x++) {
int pattern_trans = use_pattern_trans ? (pattern_mask & (1 << (7 - (pat_x & 7)))) : 1;
int src_x_real = (src_x * voodoo->banshee_blt.src_bpp) >> 3;
if (src_tiled)
src_x_real = (src_x_real & 127) + ((src_x_real >> 7) * 128 * 32);
if (dst_x >= clip->x_min && dst_x < clip->x_max && pattern_trans) {
switch (voodoo->banshee_blt.dstFormat & DST_FORMAT_COL_MASK) {
case DST_FORMAT_COL_8_BPP:
{
uint32_t dst_addr = get_addr(voodoo, dst_x, dst_y, 0, 0); //(voodoo->banshee_blt.dstBaseAddr + dst_x + dst_y*voodoo->banshee_blt.dst_stride) & voodoo->fb_mask;
uint32_t src = src_p[src_x_real];
uint32_t dest = voodoo->vram[dst_addr];
uint32_t pattern = (voodoo->banshee_blt.command & COMMAND_PATTERN_MONO) ? ((pattern_mask & (1 << (7 - (pat_x & 7)))) ? voodoo->banshee_blt.colorFore : voodoo->banshee_blt.colorBack) : voodoo->banshee_blt.colorPattern8[(pat_x & 7) + (pat_y & 7) * 8];
if (dst_addr > voodoo->fb_mask)
break;
voodoo->vram[dst_addr] = MIX(voodoo, dest, src, pattern, COLORKEY_8, COLORKEY_8);
voodoo->changedvram[dst_addr >> 12] = changeframecount;
break;
}
case DST_FORMAT_COL_16_BPP:
{
uint32_t dst_addr = get_addr(voodoo, dst_x * 2, dst_y, 0, 0); // dst_addr = (voodoo->banshee_blt.dstBaseAddr + dst_x*2 + dst_y*voodoo->banshee_blt.dst_stride) & voodoo->fb_mask;
uint32_t src = *(uint16_t *) &src_p[src_x_real];
uint32_t dest = *(uint16_t *) &voodoo->vram[dst_addr];
uint32_t pattern = (voodoo->banshee_blt.command & COMMAND_PATTERN_MONO) ? ((pattern_mask & (1 << (7 - (pat_x & 7)))) ? voodoo->banshee_blt.colorFore : voodoo->banshee_blt.colorBack) : voodoo->banshee_blt.colorPattern16[(pat_x & 7) + (pat_y & 7) * 8];
if (dst_addr > voodoo->fb_mask)
break;
*(uint16_t *) &voodoo->vram[dst_addr] = MIX(voodoo, dest, src, pattern, COLORKEY_16, COLORKEY_16);
voodoo->changedvram[dst_addr >> 12] = changeframecount;
break;
}
case DST_FORMAT_COL_24_BPP:
{
uint32_t dst_addr = get_addr(voodoo, dst_x * 3, dst_y, 0, 0); // dst_addr = (voodoo->banshee_blt.dstBaseAddr + dst_x*3 + dst_y*voodoo->banshee_blt.dst_stride) & voodoo->fb_mask;
uint32_t src = *(uint32_t *) &src_p[src_x_real];
uint32_t dest = *(uint32_t *) &voodoo->vram[dst_addr];
uint32_t pattern = (voodoo->banshee_blt.command & COMMAND_PATTERN_MONO) ? ((pattern_mask & (1 << (7 - (pat_x & 7)))) ? voodoo->banshee_blt.colorFore : voodoo->banshee_blt.colorBack) : voodoo->banshee_blt.colorPattern24[(pat_x & 7) + (pat_y & 7) * 8];
if (dst_addr > voodoo->fb_mask)
break;
*(uint32_t *) &voodoo->vram[dst_addr] = (MIX(voodoo, dest, src, pattern, COLORKEY_32, COLORKEY_32) & 0xffffff) | (dest & 0xff000000);
voodoo->changedvram[dst_addr >> 12] = changeframecount;
break;
}
case DST_FORMAT_COL_32_BPP:
{
uint32_t dst_addr = get_addr(voodoo, dst_x * 4, dst_y, 0, 0); // dst_addr = (voodoo->banshee_blt.dstBaseAddr + dst_x*4 + dst_y*voodoo->banshee_blt.dst_stride) & voodoo->fb_mask;
uint32_t src = *(uint32_t *) &src_p[src_x_real];
uint32_t dest = *(uint32_t *) &voodoo->vram[dst_addr];
uint32_t pattern = (voodoo->banshee_blt.command & COMMAND_PATTERN_MONO) ? ((pattern_mask & (1 << (7 - (pat_x & 7)))) ? voodoo->banshee_blt.colorFore : voodoo->banshee_blt.colorBack) : voodoo->banshee_blt.colorPattern[(pat_x & 7) + (pat_y & 7) * 8];
if (dst_addr > voodoo->fb_mask)
break;
*(uint32_t *) &voodoo->vram[dst_addr] = MIX(voodoo, dest, src, pattern, COLORKEY_32, COLORKEY_32);
voodoo->changedvram[dst_addr >> 12] = changeframecount;
break;
}
default:
break;
}
}
if (use_x_dir) {
src_x += (voodoo->banshee_blt.command & COMMAND_DX) ? -1 : 1;
dst_x += (voodoo->banshee_blt.command & COMMAND_DX) ? -1 : 1;
pat_x += (voodoo->banshee_blt.command & COMMAND_DX) ? -1 : 1;
} else {
src_x++;
dst_x++;
pat_x++;
}
}
}
voodoo->banshee_blt.srcY += (voodoo->banshee_blt.command & COMMAND_DY) ? -1 : 1;
voodoo->banshee_blt.dstY += (voodoo->banshee_blt.command & COMMAND_DY) ? -1 : 1;
} else {
/*Conversion required*/
if (dst_y >= clip->y_min && dst_y < clip->y_max) {
#if 0
int src_x = voodoo->banshee_blt.srcX;
#endif
int dst_x = voodoo->banshee_blt.dstX;
int pat_x = voodoo->banshee_blt.patoff_x + voodoo->banshee_blt.dstX;
uint8_t pattern_mask = pattern_mono[pat_y & 7];
for (voodoo->banshee_blt.cur_x = 0; voodoo->banshee_blt.cur_x < voodoo->banshee_blt.dstSizeX; voodoo->banshee_blt.cur_x++) {
int pattern_trans = use_pattern_trans ? (pattern_mask & (1 << (7 - (pat_x & 7)))) : 1;
int src_x_real = (src_x * voodoo->banshee_blt.src_bpp) >> 3;
if (src_tiled)
src_x_real = (src_x_real & 127) + ((src_x_real >> 7) * 128 * 32);
if (dst_x >= clip->x_min && dst_x < clip->x_max && pattern_trans) {
uint32_t src_data = 0;
uint32_t src_data_yuv = 0; /* Used in YUYV-to-RGB convesions. */
int transparent = 0;
switch (voodoo->banshee_blt.srcFormat & SRC_FORMAT_COL_MASK) {
case SRC_FORMAT_COL_1_BPP:
{
uint8_t src_byte = src_p[src_x_real];
src_data = (src_byte & (0x80 >> (src_x & 7))) ? voodoo->banshee_blt.colorFore : voodoo->banshee_blt.colorBack;
if (voodoo->banshee_blt.command & COMMAND_TRANS_MONO)
transparent = !(src_byte & (0x80 >> (src_x & 7)));
#if 0
bansheeblt_log(" 1bpp src_byte=%02x src_x=%i src_data=%x transparent=%i\n", src_byte, src_x, src_data, transparent);
#endif
break;
}
case SRC_FORMAT_COL_8_BPP:
{
src_data = src_p[src_x_real];
break;
}
case SRC_FORMAT_COL_16_BPP:
{
uint16_t src_16 = *(uint16_t *) &src_p[src_x_real];
int r = (src_16 >> 11);
int g = (src_16 >> 5) & 0x3f;
int b = src_16 & 0x1f;
r = (r << 3) | (r >> 2);
g = (g << 2) | (g >> 4);
b = (b << 3) | (b >> 2);
src_data = (r << 16) | (g << 8) | b;
break;
}
case SRC_FORMAT_COL_24_BPP:
{
src_data = *(uint32_t *) &src_p[src_x_real];
break;
}
case SRC_FORMAT_COL_32_BPP:
{
src_data = *(uint32_t *) &src_p[src_x_real];
break;
}
case SRC_FORMAT_COL_YUYV:
{
src_data_yuv = *(uint32_t *) &src_p[src_x_real];
break;
}
case SRC_FORMAT_COL_UYVY:
{
src_data_yuv = *(uint32_t *) &src_p[src_x_real];
src_data_yuv = ((src_data_yuv & 0xFF00) >> 8) | ((src_data_yuv & 0xFF) << 8) |
((src_data_yuv & 0xFF000000) >> 8) | ((src_data_yuv & 0xFF0000) << 8);
break;
}
default:
fatal("banshee_do_screen_to_screen_blt: unknown srcFormat %08x\n", voodoo->banshee_blt.srcFormat);
}
if ((voodoo->banshee_blt.dstFormat & DST_FORMAT_COL_MASK) == DST_FORMAT_COL_16_BPP && (voodoo->banshee_blt.srcFormat & SRC_FORMAT_COL_MASK) != SRC_FORMAT_COL_1_BPP) {
int r = src_data >> 16;
int g = (src_data >> 8) & 0xff;
int b = src_data & 0xff;
src_data = (b >> 3) | ((g >> 2) << 5) | ((r >> 3) << 11);
}
if ((voodoo->banshee_blt.srcFormat & SRC_FORMAT_COL_MASK) == SRC_FORMAT_COL_YUYV
|| (voodoo->banshee_blt.srcFormat & SRC_FORMAT_COL_MASK) == SRC_FORMAT_COL_UYVY) {
if (((voodoo->banshee_blt.dstFormat & DST_FORMAT_COL_MASK) == DST_FORMAT_COL_24_BPP) ||
((voodoo->banshee_blt.dstFormat & DST_FORMAT_COL_MASK) == DST_FORMAT_COL_32_BPP)) {
uint32_t rgbcol[2] = { 0, 0 };
DECODE_YUYV422(rgbcol, (uint8_t *) &src_data_yuv);
bansheeblt_log("YUV -> 24 bpp or 32 bpp\n");
if (!transparent) {
PLOT(voodoo, dst_x, dst_y, pat_x, pat_y, pattern_mask, rop, rgbcol[0], src_colorkey);
}
if (use_x_dir) {
dst_x += (voodoo->banshee_blt.command & COMMAND_DX) ? -1 : 1;
} else {
dst_x++;
}
if (!transparent) {
PLOT(voodoo, dst_x, dst_y, pat_x, pat_y, pattern_mask, rop, rgbcol[1], src_colorkey);
}
} else if ((voodoo->banshee_blt.dstFormat & DST_FORMAT_COL_MASK) == DST_FORMAT_COL_16_BPP) {
uint32_t rgbcol = 0;
DECODE_YUYV422_16BPP((uint16_t *) &rgbcol, (uint8_t *) &src_data_yuv);
bansheeblt_log("YUV -> 16 bpp\n");
if (!transparent) {
PLOT(voodoo, dst_x, dst_y, pat_x, pat_y, pattern_mask, rop, rgbcol & 0xffff, src_colorkey);
}
if (use_x_dir) {
dst_x += (voodoo->banshee_blt.command & COMMAND_DX) ? -1 : 1;
} else {
dst_x++;
}
if (!transparent) {
PLOT(voodoo, dst_x, dst_y, pat_x, pat_y, pattern_mask, rop, rgbcol >> 16, src_colorkey);
}
} else
fatal("banshee_do_screen_to_screen_blt: unknown dstFormat %08x\n", voodoo->banshee_blt.dstFormat);
} else {
if (!transparent)
PLOT(voodoo, dst_x, dst_y, pat_x, pat_y, pattern_mask, rop, src_data, src_colorkey);
}
}
if (use_x_dir) {
src_x += (voodoo->banshee_blt.command & COMMAND_DX) ? -1 : 1;
dst_x += (voodoo->banshee_blt.command & COMMAND_DX) ? -1 : 1;
pat_x += (voodoo->banshee_blt.command & COMMAND_DX) ? -1 : 1;
} else {
src_x++;
dst_x++;
pat_x++;
}
}
}
voodoo->banshee_blt.srcY += (voodoo->banshee_blt.command & COMMAND_DY) ? -1 : 1;
voodoo->banshee_blt.dstY += (voodoo->banshee_blt.command & COMMAND_DY) ? -1 : 1;
}
}
static void
banshee_do_screen_to_screen_blt(voodoo_t *voodoo)
{
#if 0
bansheeblt_log("screen_to_screen: %08x %08x %08x\n", voodoo->banshee_blt.srcFormat, voodoo->banshee_blt.src_stride, voodoo->banshee_blt.src_stride_dest);
return;
#endif
for (voodoo->banshee_blt.cur_y = 0; voodoo->banshee_blt.cur_y < voodoo->banshee_blt.dstSizeY; voodoo->banshee_blt.cur_y++) {
uint32_t src_addr = get_addr(voodoo, 0, voodoo->banshee_blt.srcY, 1, voodoo->banshee_blt.src_stride_dest);
#if 0
if ((voodoo->banshee_blt.srcFormat & SRC_FORMAT_COL_MASK) == SRC_FORMAT_COL_1_BPP)
bansheeblt_log(" srcY=%i src_addr=%08x\n", voodoo->banshee_blt.srcY, src_addr);
#endif
do_screen_to_screen_line(voodoo, &voodoo->vram[src_addr], 1, voodoo->banshee_blt.srcX, voodoo->banshee_blt.srcBaseAddr_tiled);
}
end_command(voodoo);
}
static void
banshee_do_host_to_screen_blt(voodoo_t *voodoo, UNUSED(int count), uint32_t data)
{
#if 0
if (voodoo->banshee_blt.dstBaseAddr == 0xee5194)
bansheeblt_log("banshee_do_host_to_screen_blt: data=%08x host_data_count=%i src_stride_dest=%i host_data_size_dest=%i\n", data, voodoo->banshee_blt.host_data_count, voodoo->banshee_blt.src_stride_dest, voodoo->banshee_blt.host_data_size_dest);
#endif
if (voodoo->banshee_blt.srcFormat & SRC_FORMAT_BYTE_SWIZZLE)
data = (data >> 24) | ((data >> 8) & 0xff00) | ((data << 8) & 0xff0000) | (data << 24);
if (voodoo->banshee_blt.srcFormat & SRC_FORMAT_WORD_SWIZZLE)
data = (data >> 16) | (data << 16);
if ((voodoo->banshee_blt.srcFormat & SRC_FORMAT_PACKING_MASK) == SRC_FORMAT_PACKING_STRIDE) {
int last_byte;
if ((voodoo->banshee_blt.srcFormat & SRC_FORMAT_COL_MASK) == SRC_FORMAT_COL_1_BPP)
last_byte = ((voodoo->banshee_blt.srcX & 31) + voodoo->banshee_blt.dstSizeX + 7) >> 3;
else
last_byte = (voodoo->banshee_blt.srcX & 3) + voodoo->banshee_blt.host_data_size_dest;
*(uint32_t *) &voodoo->banshee_blt.host_data[voodoo->banshee_blt.host_data_count] = data;
voodoo->banshee_blt.host_data_count += 4;
if (voodoo->banshee_blt.host_data_count >= last_byte) {
#if 0
bansheeblt_log(" %i %i srcX=%i srcFormat=%08x\n", voodoo->banshee_blt.cur_y, voodoo->banshee_blt.dstSizeY, voodoo->banshee_blt.srcX);
#endif
if (voodoo->banshee_blt.cur_y < voodoo->banshee_blt.dstSizeY) {
if ((voodoo->banshee_blt.srcFormat & SRC_FORMAT_COL_MASK) == SRC_FORMAT_COL_1_BPP)
do_screen_to_screen_line(voodoo, &voodoo->banshee_blt.host_data[(voodoo->banshee_blt.srcX >> 3) & 3], 0, voodoo->banshee_blt.srcX & 7, 0);
else
do_screen_to_screen_line(voodoo, &voodoo->banshee_blt.host_data[voodoo->banshee_blt.srcX & 3], 0, 0, 0);
voodoo->banshee_blt.cur_y++;
if (voodoo->banshee_blt.cur_y == voodoo->banshee_blt.dstSizeY)
end_command(voodoo);
}
if ((voodoo->banshee_blt.srcFormat & SRC_FORMAT_COL_MASK) == SRC_FORMAT_COL_1_BPP)
voodoo->banshee_blt.srcX += (voodoo->banshee_blt.srcFormat & SRC_FORMAT_STRIDE_MASK) << 3;
else
voodoo->banshee_blt.srcX += (voodoo->banshee_blt.srcFormat & SRC_FORMAT_STRIDE_MASK);
voodoo->banshee_blt.host_data_count = 0;
}
} else {
*(uint32_t *) &voodoo->banshee_blt.host_data[voodoo->banshee_blt.host_data_count] = data;
voodoo->banshee_blt.host_data_count += 4;
while (voodoo->banshee_blt.host_data_count >= voodoo->banshee_blt.src_stride_dest) {
voodoo->banshee_blt.host_data_count -= voodoo->banshee_blt.src_stride_dest;
#if 0
bansheeblt_log(" %i %i\n", voodoo->banshee_blt.cur_y, voodoo->banshee_blt.dstSizeY);
#endif
if (voodoo->banshee_blt.cur_y < voodoo->banshee_blt.dstSizeY) {
do_screen_to_screen_line(voodoo, voodoo->banshee_blt.host_data, 0, 0, 0);
voodoo->banshee_blt.cur_y++;
if (voodoo->banshee_blt.cur_y == voodoo->banshee_blt.dstSizeY)
end_command(voodoo);
}
if (voodoo->banshee_blt.host_data_count) {
#if 0
bansheeblt_log(" remaining=%i\n", voodoo->banshee_blt.host_data_count);
#endif
*(uint32_t *) &voodoo->banshee_blt.host_data[0] = data >> (4 - voodoo->banshee_blt.host_data_count) * 8;
}
}
}
}
static void
do_screen_to_screen_stretch_line(voodoo_t *voodoo, uint8_t *src_p, int src_x, int *src_y)
{
const clip_t *clip = &voodoo->banshee_blt.clip[(voodoo->banshee_blt.command & COMMAND_CLIP_SEL) ? 1 : 0];
#if 0
int src_y = voodoo->banshee_blt.srcY;
#endif
int dst_y = voodoo->banshee_blt.dstY;
int pat_y = (voodoo->banshee_blt.commandExtra & CMDEXTRA_FORCE_PAT_ROW0) ? 0 : (voodoo->banshee_blt.patoff_y + voodoo->banshee_blt.dstY);
const uint8_t *pattern_mono = (uint8_t *) voodoo->banshee_blt.colorPattern;
int use_pattern_trans = (voodoo->banshee_blt.command & (COMMAND_PATTERN_MONO | COMMAND_TRANS_MONO)) == (COMMAND_PATTERN_MONO | COMMAND_TRANS_MONO);
const uint32_t *colorPattern = voodoo->banshee_blt.colorPattern;
#if 0
int error_y = voodoo->banshee_blt.dstSizeY / 2;
bansheeblt_log("banshee_do_screen_to_screen_stretch_blt:\n");
bansheeblt_log(" srcXY=%i,%i srcsizeXY=%i,%i\n", voodoo->banshee_blt.srcX, voodoo->banshee_blt.srcY, voodoo->banshee_blt.srcSizeX, voodoo->banshee_blt.srcSizeY);
bansheeblt_log(" dstXY=%i,%i dstsizeXY=%i,%i\n", voodoo->banshee_blt.dstX, voodoo->banshee_blt.dstY, voodoo->banshee_blt.dstSizeX, voodoo->banshee_blt.dstSizeY);*/
#endif
if (dst_y >= clip->y_min && dst_y < clip->y_max) {
#if 0
int src_x = voodoo->banshee_blt.srcX;
#endif
int dst_x = voodoo->banshee_blt.dstX;
int pat_x = voodoo->banshee_blt.patoff_x + voodoo->banshee_blt.dstX;
uint8_t pattern_mask = pattern_mono[pat_y & 7];
int error_x = voodoo->banshee_blt.dstSizeX / 2;
#if 0
bansheeblt_log(" Plot dest line %03i : src line %03i\n", dst_y, src_y);
#endif
for (voodoo->banshee_blt.cur_x = 0; voodoo->banshee_blt.cur_x < voodoo->banshee_blt.dstSizeX; voodoo->banshee_blt.cur_x++) {
int pattern_trans = use_pattern_trans ? (pattern_mask & (1 << (7 - (pat_x & 7)))) : 1;
if (dst_x >= clip->x_min && dst_x < clip->x_max && pattern_trans) {
switch (voodoo->banshee_blt.dstFormat & DST_FORMAT_COL_MASK) {
case DST_FORMAT_COL_8_BPP:
{
uint32_t dst_addr = get_addr(voodoo, dst_x, dst_y, 0, 0); //(voodoo->banshee_blt.dstBaseAddr + dst_x + dst_y*voodoo->banshee_blt.dst_stride) & voodoo->fb_mask;
uint32_t src = src_p[src_x];
uint32_t dest = voodoo->vram[dst_addr];
uint32_t pattern = (voodoo->banshee_blt.command & COMMAND_PATTERN_MONO) ? ((pattern_mask & (1 << (7 - (pat_x & 7)))) ? voodoo->banshee_blt.colorFore : voodoo->banshee_blt.colorBack) : colorPattern[(pat_x & 7) + (pat_y & 7) * 8];
if (dst_addr > voodoo->fb_mask)
break;
voodoo->vram[dst_addr] = MIX(voodoo, dest, src, pattern, COLORKEY_8, COLORKEY_8);
#if 0
bansheeblt_log("%i,%i : sdp=%02x,%02x,%02x res=%02x\n", voodoo->banshee_blt.cur_x, voodoo->banshee_blt.cur_y, src, dest, pattern, voodoo->vram[dst_addr]);
#endif
voodoo->changedvram[dst_addr >> 12] = changeframecount;
break;
}
case DST_FORMAT_COL_16_BPP:
{
uint32_t dst_addr = get_addr(voodoo, dst_x * 2, dst_y, 0, 0); //(voodoo->banshee_blt.dstBaseAddr + dst_x*2 + dst_y*voodoo->banshee_blt.dst_stride) & voodoo->fb_mask;
uint32_t src = *(uint16_t *) &src_p[src_x * 2];
uint32_t dest = *(uint16_t *) &voodoo->vram[dst_addr];
uint32_t pattern = (voodoo->banshee_blt.command & COMMAND_PATTERN_MONO) ? ((pattern_mask & (1 << (7 - (pat_x & 7)))) ? voodoo->banshee_blt.colorFore : voodoo->banshee_blt.colorBack) : colorPattern[(pat_x & 7) + (pat_y & 7) * 8];
if (dst_addr > voodoo->fb_mask)
break;
*(uint16_t *) &voodoo->vram[dst_addr] = MIX(voodoo, dest, src, pattern, COLORKEY_16, COLORKEY_16);
#if 0
bansheeblt_log("%i,%i : sdp=%02x,%02x,%02x res=%02x\n", voodoo->banshee_blt.cur_x, voodoo->banshee_blt.cur_y, src, dest, pattern, *(uint16_t *)&voodoo->vram[dst_addr]);
#endif
voodoo->changedvram[dst_addr >> 12] = changeframecount;
break;
}
case DST_FORMAT_COL_24_BPP:
{
uint32_t dst_addr = get_addr(voodoo, dst_x * 3, dst_y, 0, 0); //(voodoo->banshee_blt.dstBaseAddr + dst_x*3 + dst_y*voodoo->banshee_blt.dst_stride) & voodoo->fb_mask;
uint32_t src = *(uint32_t *) &src_p[src_x * 3];
uint32_t dest = *(uint32_t *) &voodoo->vram[dst_addr];
uint32_t pattern = (voodoo->banshee_blt.command & COMMAND_PATTERN_MONO) ? ((pattern_mask & (1 << (7 - (pat_x & 7)))) ? voodoo->banshee_blt.colorFore : voodoo->banshee_blt.colorBack) : colorPattern[(pat_x & 7) + (pat_y & 7) * 8];
if (dst_addr > voodoo->fb_mask)
break;
*(uint32_t *) &voodoo->vram[dst_addr] = (MIX(voodoo, dest, src, pattern, COLORKEY_32, COLORKEY_32) & 0xffffff) | (*(uint32_t *) &voodoo->vram[dst_addr] & 0xff000000);
#if 0
bansheeblt_log("%i,%i : sdp=%02x,%02x,%02x res=%02x\n", voodoo->banshee_blt.cur_x, voodoo->banshee_blt.cur_y, src, dest, pattern, voodoo->vram[dst_addr]);
#endif
voodoo->changedvram[dst_addr >> 12] = changeframecount;
break;
}
case DST_FORMAT_COL_32_BPP:
{
uint32_t dst_addr = get_addr(voodoo, dst_x * 4, dst_y, 0, 0); //(voodoo->banshee_blt.dstBaseAddr + dst_x*4 + dst_y*voodoo->banshee_blt.dst_stride) & voodoo->fb_mask;
uint32_t src = *(uint32_t *) &src_p[src_x * 4];
uint32_t dest = *(uint32_t *) &voodoo->vram[dst_addr];
uint32_t pattern = (voodoo->banshee_blt.command & COMMAND_PATTERN_MONO) ? ((pattern_mask & (1 << (7 - (pat_x & 7)))) ? voodoo->banshee_blt.colorFore : voodoo->banshee_blt.colorBack) : colorPattern[(pat_x & 7) + (pat_y & 7) * 8];
if (dst_addr > voodoo->fb_mask)
break;
*(uint32_t *) &voodoo->vram[dst_addr] = MIX(voodoo, dest, src, pattern, COLORKEY_32, COLORKEY_32);
#if 0
bansheeblt_log("%i,%i : sdp=%02x,%02x,%02x res=%02x\n", voodoo->banshee_blt.cur_x, voodoo->banshee_blt.cur_y, src, dest, pattern, voodoo->vram[dst_addr]);
#endif
voodoo->changedvram[dst_addr >> 12] = changeframecount;
break;
}
default:
break;
}
}
error_x -= voodoo->banshee_blt.srcSizeX;
while (error_x < 0) {
error_x += voodoo->banshee_blt.dstSizeX;
src_x++;
}
dst_x++;
pat_x++;
}
}
voodoo->banshee_blt.bres_error_0 -= voodoo->banshee_blt.srcSizeY;
while (voodoo->banshee_blt.bres_error_0 < 0) {
voodoo->banshee_blt.bres_error_0 += voodoo->banshee_blt.dstSizeY;
if (src_y)
(*src_y) += (voodoo->banshee_blt.command & COMMAND_DY) ? -1 : 1;
}
voodoo->banshee_blt.dstY += (voodoo->banshee_blt.command & COMMAND_DY) ? -1 : 1;
#if 0
pat_y += (voodoo->banshee_blt.command & COMMAND_DY) ? -1 : 1;
#endif
}
static void
banshee_do_screen_to_screen_stretch_blt(voodoo_t *voodoo)
{
#if 0
bansheeblt_log("screen_to_screen: %08x %08x %08x\n", voodoo->banshee_blt.srcFormat, voodoo->banshee_blt.src_stride, voodoo->banshee_blt.src_stride_dest);
return;
#endif
for (voodoo->banshee_blt.cur_y = 0; voodoo->banshee_blt.cur_y < voodoo->banshee_blt.dstSizeY; voodoo->banshee_blt.cur_y++) {
uint32_t src_addr = get_addr(voodoo, 0, voodoo->banshee_blt.srcY, 1, voodoo->banshee_blt.src_stride_src); //(voodoo->banshee_blt.srcBaseAddr + voodoo->banshee_blt.srcY*voodoo->banshee_blt.src_stride_src) & voodoo->fb_mask;
#if 0
bansheeblt_log("scale_blit %i %08x %08x\n", voodoo->banshee_blt.cur_y, src_addr, voodoo->banshee_blt.command);
if ((voodoo->banshee_blt.srcFormat & SRC_FORMAT_COL_MASK) == SRC_FORMAT_COL_1_BPP)
bansheeblt_log(" srcY=%i src_addr=%08x\n", voodoo->banshee_blt.srcY, src_addr);
#endif
do_screen_to_screen_stretch_line(voodoo, &voodoo->vram[src_addr], voodoo->banshee_blt.srcX, &voodoo->banshee_blt.srcY);
}
end_command(voodoo);
}
static void
banshee_do_host_to_screen_stretch_blt(voodoo_t *voodoo, UNUSED(int count), uint32_t data)
{
#if 0
if (voodoo->banshee_blt.dstBaseAddr == 0xee5194)
bansheeblt_log("banshee_do_host_to_screen_blt: data=%08x host_data_count=%i src_stride_dest=%i host_data_size_dest=%i\n", data, voodoo->banshee_blt.host_data_count, voodoo->banshee_blt.src_stride_dest, voodoo->banshee_blt.host_data_size_dest);
#endif
if (voodoo->banshee_blt.srcFormat & SRC_FORMAT_BYTE_SWIZZLE)
data = (data >> 24) | ((data >> 8) & 0xff00) | ((data << 8) & 0xff0000) | (data << 24);
if (voodoo->banshee_blt.srcFormat & SRC_FORMAT_WORD_SWIZZLE)
data = (data >> 16) | (data << 16);
if ((voodoo->banshee_blt.srcFormat & SRC_FORMAT_PACKING_MASK) == SRC_FORMAT_PACKING_STRIDE) {
int last_byte = (voodoo->banshee_blt.srcX & 3) + voodoo->banshee_blt.host_data_size_src;
*(uint32_t *) &voodoo->banshee_blt.host_data[voodoo->banshee_blt.host_data_count] = data;
voodoo->banshee_blt.host_data_count += 4;
if (voodoo->banshee_blt.host_data_count >= last_byte) {
#if 0
bansheeblt_log(" %i %i srcX=%i srcFormat=%08x\n", voodoo->banshee_blt.cur_y, voodoo->banshee_blt.dstSizeY, voodoo->banshee_blt.srcX);
#endif
if (voodoo->banshee_blt.cur_y < voodoo->banshee_blt.dstSizeY) {
if ((voodoo->banshee_blt.srcFormat & SRC_FORMAT_COL_MASK) == SRC_FORMAT_COL_1_BPP)
do_screen_to_screen_stretch_line(voodoo, &voodoo->banshee_blt.host_data[(voodoo->banshee_blt.srcX >> 3) & 3], voodoo->banshee_blt.srcX & 7, NULL);
else
do_screen_to_screen_stretch_line(voodoo, &voodoo->banshee_blt.host_data[voodoo->banshee_blt.srcX & 3], 0, NULL);
voodoo->banshee_blt.cur_y++;
if (voodoo->banshee_blt.cur_y == voodoo->banshee_blt.dstSizeY)
end_command(voodoo);
}
if ((voodoo->banshee_blt.srcFormat & SRC_FORMAT_COL_MASK) == SRC_FORMAT_COL_1_BPP)
voodoo->banshee_blt.srcX += (voodoo->banshee_blt.srcFormat & SRC_FORMAT_STRIDE_MASK) << 3;
else
voodoo->banshee_blt.srcX += (voodoo->banshee_blt.srcFormat & SRC_FORMAT_STRIDE_MASK);
voodoo->banshee_blt.host_data_count = 0;
}
} else {
*(uint32_t *) &voodoo->banshee_blt.host_data[voodoo->banshee_blt.host_data_count] = data;
voodoo->banshee_blt.host_data_count += 4;
while (voodoo->banshee_blt.host_data_count >= voodoo->banshee_blt.src_stride_src) {
voodoo->banshee_blt.host_data_count -= voodoo->banshee_blt.src_stride_src;
#if 0
bansheeblt_log(" %i %i\n", voodoo->banshee_blt.cur_y, voodoo->banshee_blt.dstSizeY);
#endif
if (voodoo->banshee_blt.cur_y < voodoo->banshee_blt.dstSizeY) {
do_screen_to_screen_stretch_line(voodoo, voodoo->banshee_blt.host_data, 0, NULL);
voodoo->banshee_blt.cur_y++;
if (voodoo->banshee_blt.cur_y == voodoo->banshee_blt.dstSizeY)
end_command(voodoo);
}
if (voodoo->banshee_blt.host_data_count) {
#if 0
bansheeblt_log(" remaining=%i\n", voodoo->banshee_blt.host_data_count);
#endif
*(uint32_t *) &voodoo->banshee_blt.host_data[0] = data >> (4 - voodoo->banshee_blt.host_data_count) * 8;
}
}
}
}
static void
step_line(voodoo_t *voodoo)
{
if (voodoo->banshee_blt.line_pix_pos == voodoo->banshee_blt.line_rep_cnt) {
voodoo->banshee_blt.line_pix_pos = 0;
if (voodoo->banshee_blt.line_bit_pos == voodoo->banshee_blt.line_bit_mask_size)
voodoo->banshee_blt.line_bit_pos = 0;
else
voodoo->banshee_blt.line_bit_pos++;
} else
voodoo->banshee_blt.line_pix_pos++;
}
static void
banshee_do_line(voodoo_t *voodoo, int draw_last_pixel)
{
const clip_t *clip = &voodoo->banshee_blt.clip[(voodoo->banshee_blt.command & COMMAND_CLIP_SEL) ? 1 : 0];
uint8_t rop = voodoo->banshee_blt.command >> 24;
int dx = ABS(voodoo->banshee_blt.dstX - voodoo->banshee_blt.srcX);
int dy = ABS(voodoo->banshee_blt.dstY - voodoo->banshee_blt.srcY);
int x_inc = (voodoo->banshee_blt.dstX > voodoo->banshee_blt.srcX) ? 1 : -1;
int y_inc = (voodoo->banshee_blt.dstY > voodoo->banshee_blt.srcY) ? 1 : -1;
int x = voodoo->banshee_blt.srcX;
int y = voodoo->banshee_blt.srcY;
int error;
uint32_t stipple = (voodoo->banshee_blt.command & COMMAND_STIPPLE_LINE) ? voodoo->banshee_blt.lineStipple : ~0;
if (dx > dy) /*X major*/
{
error = dx / 2;
while (x != voodoo->banshee_blt.dstX) {
int mask = stipple & (1 << voodoo->banshee_blt.line_bit_pos);
int pattern_trans = (voodoo->banshee_blt.command & COMMAND_TRANS_MONO) ? mask : 1;
if (y >= clip->y_min && y < clip->y_max && x >= clip->x_min && x < clip->x_max && pattern_trans)
PLOT_LINE(voodoo, x, y, rop, mask ? voodoo->banshee_blt.colorFore : voodoo->banshee_blt.colorBack, COLORKEY_32);
error -= dy;
if (error < 0) {
error += dx;
y += y_inc;
}
x += x_inc;
step_line(voodoo);
}
} else /*Y major*/
{
error = dy / 2;
while (y != voodoo->banshee_blt.dstY) {
int mask = stipple & (1 << voodoo->banshee_blt.line_bit_pos);
int pattern_trans = (voodoo->banshee_blt.command & COMMAND_TRANS_MONO) ? mask : 1;
if (y >= clip->y_min && y < clip->y_max && x >= clip->x_min && x < clip->x_max && pattern_trans)
PLOT_LINE(voodoo, x, y, rop, mask ? voodoo->banshee_blt.colorFore : voodoo->banshee_blt.colorBack, COLORKEY_32);
error -= dx;
if (error < 0) {
error += dy;
x += x_inc;
}
y += y_inc;
step_line(voodoo);
}
}
if (draw_last_pixel) {
int mask = stipple & (1 << voodoo->banshee_blt.line_bit_pos);
int pattern_trans = (voodoo->banshee_blt.command & COMMAND_TRANS_MONO) ? mask : 1;
if (y >= clip->y_min && y < clip->y_max && x >= clip->x_min && x < clip->x_max && pattern_trans)
PLOT_LINE(voodoo, x, y, rop, mask ? voodoo->banshee_blt.colorFore : voodoo->banshee_blt.colorBack, COLORKEY_32);
}
voodoo->banshee_blt.srcXY = (x & 0xffff) | (y << 16);
voodoo->banshee_blt.srcX = x;
voodoo->banshee_blt.srcY = y;
}
static void
banshee_polyfill_start(voodoo_t *voodoo)
{
voodoo->banshee_blt.lx[0] = voodoo->banshee_blt.srcX;
voodoo->banshee_blt.ly[0] = voodoo->banshee_blt.srcY;
voodoo->banshee_blt.rx[0] = voodoo->banshee_blt.dstX;
voodoo->banshee_blt.ry[0] = voodoo->banshee_blt.dstY;
voodoo->banshee_blt.lx[1] = voodoo->banshee_blt.srcX;
voodoo->banshee_blt.ly[1] = voodoo->banshee_blt.srcY;
voodoo->banshee_blt.rx[1] = voodoo->banshee_blt.dstX;
voodoo->banshee_blt.ry[1] = voodoo->banshee_blt.dstY;
voodoo->banshee_blt.lx_cur = voodoo->banshee_blt.srcX;
voodoo->banshee_blt.rx_cur = voodoo->banshee_blt.dstX;
}
static void
banshee_polyfill_continue(voodoo_t *voodoo, uint32_t data)
{
const clip_t *clip = &voodoo->banshee_blt.clip[(voodoo->banshee_blt.command & COMMAND_CLIP_SEL) ? 1 : 0];
const uint8_t *pattern_mono = (uint8_t *) voodoo->banshee_blt.colorPattern;
int use_pattern_trans = (voodoo->banshee_blt.command & (COMMAND_PATTERN_MONO | COMMAND_TRANS_MONO)) == (COMMAND_PATTERN_MONO | COMMAND_TRANS_MONO);
uint8_t rop = voodoo->banshee_blt.command >> 24;
int y = MAX(voodoo->banshee_blt.ly[0], voodoo->banshee_blt.ry[0]);
int y_end;
#if 0
bansheeblt_log("Polyfill : data %08x\n", data);
#endif
/*if r1.y>=l1.y, next vertex is left*/
if (voodoo->banshee_blt.ry[1] >= voodoo->banshee_blt.ly[1]) {
voodoo->banshee_blt.lx[1] = ((int32_t) (data << 19)) >> 19;
voodoo->banshee_blt.ly[1] = ((int32_t) (data << 3)) >> 19;
voodoo->banshee_blt.dx[0] = ABS(voodoo->banshee_blt.lx[1] - voodoo->banshee_blt.lx[0]);
voodoo->banshee_blt.dy[0] = ABS(voodoo->banshee_blt.ly[1] - voodoo->banshee_blt.ly[0]);
voodoo->banshee_blt.x_inc[0] = (voodoo->banshee_blt.lx[1] > voodoo->banshee_blt.lx[0]) ? 1 : -1;
voodoo->banshee_blt.error[0] = voodoo->banshee_blt.dy[0] / 2;
} else {
voodoo->banshee_blt.rx[1] = ((int32_t) (data << 19)) >> 19;
voodoo->banshee_blt.ry[1] = ((int32_t) (data << 3)) >> 19;
voodoo->banshee_blt.dx[1] = ABS(voodoo->banshee_blt.rx[1] - voodoo->banshee_blt.rx[0]);
voodoo->banshee_blt.dy[1] = ABS(voodoo->banshee_blt.ry[1] - voodoo->banshee_blt.ry[0]);
voodoo->banshee_blt.x_inc[1] = (voodoo->banshee_blt.rx[1] > voodoo->banshee_blt.rx[0]) ? 1 : -1;
voodoo->banshee_blt.error[1] = voodoo->banshee_blt.dy[1] / 2;
}
#if 0
bansheeblt_log(" verts now : %03i,%03i %03i,%03i\n", voodoo->banshee_blt.lx[0], voodoo->banshee_blt.ly[0], voodoo->banshee_blt.rx[0], voodoo->banshee_blt.ry[0]);
bansheeblt_log(" %03i,%03i %03i,%03i\n", voodoo->banshee_blt.lx[1], voodoo->banshee_blt.ly[1], voodoo->banshee_blt.rx[1], voodoo->banshee_blt.ry[1]);
bansheeblt_log(" left dx=%i dy=%i x_inc=%i error=%i\n", voodoo->banshee_blt.dx[0],voodoo->banshee_blt.dy[0],voodoo->banshee_blt.x_inc[0],voodoo->banshee_blt.error[0]);
bansheeblt_log(" right dx=%i dy=%i x_inc=%i error=%i\n", voodoo->banshee_blt.dx[1],voodoo->banshee_blt.dy[1],voodoo->banshee_blt.x_inc[1],voodoo->banshee_blt.error[1]);
#endif
y_end = MIN(voodoo->banshee_blt.ly[1], voodoo->banshee_blt.ry[1]);
#if 0
bansheeblt_log("Polyfill : draw spans from %i-%i\n", y, y_end);
#endif
for (; y < y_end; y++) {
#if 0
bansheeblt_log(" %i: %i %i\n", y, voodoo->banshee_blt.lx_cur, voodoo->banshee_blt.rx_cur);
#endif
/*Draw span from lx_cur to rx_cur*/
if (y >= clip->y_min && y < clip->y_max) {
int pat_y = (voodoo->banshee_blt.commandExtra & CMDEXTRA_FORCE_PAT_ROW0) ? 0 : (voodoo->banshee_blt.patoff_y + y);
uint8_t pattern_mask = pattern_mono[pat_y & 7];
for (int x = voodoo->banshee_blt.lx_cur; x < voodoo->banshee_blt.rx_cur; x++) {
int pat_x = voodoo->banshee_blt.patoff_x + x;
int pattern_trans = use_pattern_trans ? (pattern_mask & (1 << (7 - (pat_x & 7)))) : 1;
if (x >= clip->x_min && x < clip->x_max && pattern_trans)
PLOT(voodoo, x, y, pat_x, pat_y, pattern_mask, rop, voodoo->banshee_blt.colorFore, COLORKEY_32);
}
}
voodoo->banshee_blt.error[0] -= voodoo->banshee_blt.dx[0];
while (voodoo->banshee_blt.error[0] < 0) {
voodoo->banshee_blt.error[0] += voodoo->banshee_blt.dy[0];
voodoo->banshee_blt.lx_cur += voodoo->banshee_blt.x_inc[0];
}
voodoo->banshee_blt.error[1] -= voodoo->banshee_blt.dx[1];
while (voodoo->banshee_blt.error[1] < 0) {
voodoo->banshee_blt.error[1] += voodoo->banshee_blt.dy[1];
voodoo->banshee_blt.rx_cur += voodoo->banshee_blt.x_inc[1];
}
}
if (voodoo->banshee_blt.ry[1] == voodoo->banshee_blt.ly[1]) {
voodoo->banshee_blt.lx[0] = voodoo->banshee_blt.lx[1];
voodoo->banshee_blt.ly[0] = voodoo->banshee_blt.ly[1];
voodoo->banshee_blt.rx[0] = voodoo->banshee_blt.rx[1];
voodoo->banshee_blt.ry[0] = voodoo->banshee_blt.ry[1];
} else if (voodoo->banshee_blt.ry[1] >= voodoo->banshee_blt.ly[1]) {
voodoo->banshee_blt.lx[0] = voodoo->banshee_blt.lx[1];
voodoo->banshee_blt.ly[0] = voodoo->banshee_blt.ly[1];
} else {
voodoo->banshee_blt.rx[0] = voodoo->banshee_blt.rx[1];
voodoo->banshee_blt.ry[0] = voodoo->banshee_blt.ry[1];
}
}
static void
banshee_do_2d_blit(voodoo_t *voodoo, int count, uint32_t data)
{
switch (voodoo->banshee_blt.command & COMMAND_CMD_MASK) {
case COMMAND_CMD_NOP:
break;
case COMMAND_CMD_SCREEN_TO_SCREEN_BLT:
banshee_do_screen_to_screen_blt(voodoo);
break;
case COMMAND_CMD_SCREEN_TO_SCREEN_STRETCH_BLT:
banshee_do_screen_to_screen_stretch_blt(voodoo);
break;
case COMMAND_CMD_HOST_TO_SCREEN_BLT:
banshee_do_host_to_screen_blt(voodoo, count, data);
break;
case COMMAND_CMD_HOST_TO_SCREEN_STRETCH_BLT:
banshee_do_host_to_screen_stretch_blt(voodoo, count, data);
break;
case COMMAND_CMD_RECTFILL:
banshee_do_rectfill(voodoo);
break;
case COMMAND_CMD_LINE:
banshee_do_line(voodoo, 1);
break;
case COMMAND_CMD_POLYLINE:
banshee_do_line(voodoo, 0);
break;
default:
fatal("banshee_do_2d_blit: unknown command=%08x\n", voodoo->banshee_blt.command);
}
}
void
voodoo_2d_reg_writel(voodoo_t *voodoo, uint32_t addr, uint32_t val)
{
#if 0
if ((addr & 0x1fc) != 0x80)
bansheeblt_log("2D reg write %03x %08x\n", addr & 0x1fc, val);
#endif
switch (addr & 0x1fc) {
case 0x08:
voodoo->banshee_blt.clip0Min = val;
voodoo->banshee_blt.clip[0].x_min = val & 0xfff;
voodoo->banshee_blt.clip[0].y_min = (val >> 16) & 0xfff;
break;
case 0x0c:
voodoo->banshee_blt.clip0Max = val;
voodoo->banshee_blt.clip[0].x_max = val & 0xfff;
voodoo->banshee_blt.clip[0].y_max = (val >> 16) & 0xfff;
break;
case 0x10:
voodoo->banshee_blt.dstBaseAddr = val & 0xffffff;
voodoo->banshee_blt.dstBaseAddr_tiled = val & 0x80000000;
if (voodoo->banshee_blt.dstBaseAddr_tiled)
voodoo->banshee_blt.dst_stride = (voodoo->banshee_blt.dstFormat & DST_FORMAT_STRIDE_MASK) * 128 * 32;
else
voodoo->banshee_blt.dst_stride = voodoo->banshee_blt.dstFormat & DST_FORMAT_STRIDE_MASK;
#if 0
bansheeblt_log("dstBaseAddr=%08x\n", val);
#endif
break;
case 0x14:
voodoo->banshee_blt.dstFormat = val;
if (voodoo->banshee_blt.dstBaseAddr_tiled)
voodoo->banshee_blt.dst_stride = (voodoo->banshee_blt.dstFormat & DST_FORMAT_STRIDE_MASK) * 128 * 32;
else
voodoo->banshee_blt.dst_stride = voodoo->banshee_blt.dstFormat & DST_FORMAT_STRIDE_MASK;
#if 0
bansheeblt_log("dstFormat=%08x\n", val);
#endif
break;
case 0x18:
voodoo->banshee_blt.srcColorkeyMin = val & 0xffffff;
break;
case 0x1c:
voodoo->banshee_blt.srcColorkeyMax = val & 0xffffff;
break;
case 0x20:
voodoo->banshee_blt.dstColorkeyMin = val & 0xffffff;
break;
case 0x24:
voodoo->banshee_blt.dstColorkeyMax = val & 0xffffff;
break;
case 0x28:
voodoo->banshee_blt.bresError0 = val;
voodoo->banshee_blt.bres_error_0 = val & 0xffff;
break;
case 0x2c:
voodoo->banshee_blt.bresError1 = val;
voodoo->banshee_blt.bres_error_1 = val & 0xffff;
break;
case 0x30:
voodoo->banshee_blt.rop = val;
voodoo->banshee_blt.rops[1] = val & 0xff;
voodoo->banshee_blt.rops[2] = (val >> 8) & 0xff;
voodoo->banshee_blt.rops[3] = (val >> 16) & 0xff;
#if 0
bansheeblt_log("rop=%08x\n", val);
#endif
break;
case 0x34:
voodoo->banshee_blt.srcBaseAddr = val & 0xffffff;
voodoo->banshee_blt.srcBaseAddr_tiled = val & 0x80000000;
if (voodoo->banshee_blt.srcBaseAddr_tiled)
voodoo->banshee_blt.src_stride = (voodoo->banshee_blt.srcFormat & SRC_FORMAT_STRIDE_MASK) * 128 * 32;
else
voodoo->banshee_blt.src_stride = voodoo->banshee_blt.srcFormat & SRC_FORMAT_STRIDE_MASK;
update_src_stride(voodoo);
#if 0
bansheeblt_log("srcBaseAddr=%08x\n", val);
#endif
break;
case 0x38:
voodoo->banshee_blt.commandExtra = val;
#if 0
bansheeblt_log("commandExtra=%08x\n", val);
#endif
break;
case 0x3c:
voodoo->banshee_blt.lineStipple = val;
break;
case 0x40:
voodoo->banshee_blt.lineStyle = val;
voodoo->banshee_blt.line_rep_cnt = val & 0xff;
voodoo->banshee_blt.line_bit_mask_size = (val >> 8) & 0x1f;
voodoo->banshee_blt.line_pix_pos = (val >> 16) & 0xff;
voodoo->banshee_blt.line_bit_pos = (val >> 24) & 0x1f;
break;
case 0x44:
voodoo->banshee_blt.colorPattern[0] = val;
#if 0
bansheeblt_log("colorPattern0=%08x\n", val);
#endif
voodoo->banshee_blt.colorPattern24[0] = val & 0xffffff;
voodoo->banshee_blt.colorPattern24[1] = (voodoo->banshee_blt.colorPattern24[1] & 0xffff00) | (val >> 24);
voodoo->banshee_blt.colorPattern16[0] = val & 0xffff;
voodoo->banshee_blt.colorPattern16[1] = (val >> 16) & 0xffff;
voodoo->banshee_blt.colorPattern8[0] = val & 0xff;
voodoo->banshee_blt.colorPattern8[1] = (val >> 8) & 0xff;
voodoo->banshee_blt.colorPattern8[2] = (val >> 16) & 0xff;
voodoo->banshee_blt.colorPattern8[3] = (val >> 24) & 0xff;
break;
case 0x48:
voodoo->banshee_blt.colorPattern[1] = val;
#if 0
bansheeblt_log("colorPattern1=%08x\n", val);
#endif
voodoo->banshee_blt.colorPattern24[1] = (voodoo->banshee_blt.colorPattern24[1] & 0xff) | ((val & 0xffff) << 8);
voodoo->banshee_blt.colorPattern24[2] = (voodoo->banshee_blt.colorPattern24[2] & 0xff0000) | (val >> 16);
voodoo->banshee_blt.colorPattern16[2] = val & 0xffff;
voodoo->banshee_blt.colorPattern16[3] = (val >> 16) & 0xffff;
voodoo->banshee_blt.colorPattern8[4] = val & 0xff;
voodoo->banshee_blt.colorPattern8[5] = (val >> 8) & 0xff;
voodoo->banshee_blt.colorPattern8[6] = (val >> 16) & 0xff;
voodoo->banshee_blt.colorPattern8[7] = (val >> 24) & 0xff;
break;
case 0x4c:
voodoo->banshee_blt.clip1Min = val;
voodoo->banshee_blt.clip[1].x_min = val & 0xfff;
voodoo->banshee_blt.clip[1].y_min = (val >> 16) & 0xfff;
break;
case 0x50:
voodoo->banshee_blt.clip1Max = val;
voodoo->banshee_blt.clip[1].x_max = val & 0xfff;
voodoo->banshee_blt.clip[1].y_max = (val >> 16) & 0xfff;
break;
case 0x54:
voodoo->banshee_blt.srcFormat = val;
if (voodoo->banshee_blt.srcBaseAddr_tiled)
voodoo->banshee_blt.src_stride = (voodoo->banshee_blt.srcFormat & SRC_FORMAT_STRIDE_MASK) * 128 * 32;
else
voodoo->banshee_blt.src_stride = voodoo->banshee_blt.srcFormat & SRC_FORMAT_STRIDE_MASK;
update_src_stride(voodoo);
switch (voodoo->banshee_blt.srcFormat & SRC_FORMAT_COL_MASK) {
case SRC_FORMAT_COL_1_BPP:
voodoo->banshee_blt.src_bpp = 1;
break;
case SRC_FORMAT_COL_8_BPP:
voodoo->banshee_blt.src_bpp = 8;
break;
case SRC_FORMAT_COL_24_BPP:
voodoo->banshee_blt.src_bpp = 24;
break;
case SRC_FORMAT_COL_32_BPP:
case SRC_FORMAT_COL_YUYV:
case SRC_FORMAT_COL_UYVY:
voodoo->banshee_blt.src_bpp = 32;
break;
case SRC_FORMAT_COL_16_BPP:
default:
voodoo->banshee_blt.src_bpp = 16;
break;
}
#if 0
bansheeblt_log("srcFormat=%08x\n", val);
#endif
break;
case 0x58:
voodoo->banshee_blt.srcSize = val;
voodoo->banshee_blt.srcSizeX = voodoo->banshee_blt.srcSize & 0x1fff;
voodoo->banshee_blt.srcSizeY = (voodoo->banshee_blt.srcSize >> 16) & 0x1fff;
update_src_stride(voodoo);
#if 0
bansheeblt_log("srcSize=%08x\n", val);
#endif
break;
case 0x5c:
voodoo->banshee_blt.srcXY = val;
voodoo->banshee_blt.srcX = ((int32_t) (val << 19)) >> 19;
voodoo->banshee_blt.srcY = ((int32_t) (val << 3)) >> 19;
update_src_stride(voodoo);
#if 0
bansheeblt_log("srcXY=%08x\n", val);
#endif
break;
case 0x60:
voodoo->banshee_blt.colorBack = val;
break;
case 0x64:
voodoo->banshee_blt.colorFore = val;
break;
case 0x68:
voodoo->banshee_blt.dstSize = val;
voodoo->banshee_blt.dstSizeX = voodoo->banshee_blt.dstSize & 0x1fff;
voodoo->banshee_blt.dstSizeY = (voodoo->banshee_blt.dstSize >> 16) & 0x1fff;
update_src_stride(voodoo);
#if 0
bansheeblt_log("dstSize=%08x\n", val);
#endif
break;
case 0x6c:
voodoo->banshee_blt.dstXY = val;
voodoo->banshee_blt.dstX = ((int32_t) (val << 19)) >> 19;
voodoo->banshee_blt.dstY = ((int32_t) (val << 3)) >> 19;
#if 0
bansheeblt_log("dstXY=%08x\n", val);
#endif
break;
case 0x70:
voodoo_wait_for_render_thread_idle(voodoo);
voodoo->banshee_blt.command = val;
voodoo->banshee_blt.rops[0] = val >> 24;
#if 0
bansheeblt_log("command=%x %08x\n", voodoo->banshee_blt.command & COMMAND_CMD_MASK, val);
#endif
voodoo->banshee_blt.patoff_x = (val & COMMAND_PATOFF_X_MASK) >> COMMAND_PATOFF_X_SHIFT;
voodoo->banshee_blt.patoff_y = (val & COMMAND_PATOFF_Y_MASK) >> COMMAND_PATOFF_Y_SHIFT;
voodoo->banshee_blt.cur_x = 0;
voodoo->banshee_blt.cur_y = 0;
voodoo->banshee_blt.dstX = ((int32_t) (voodoo->banshee_blt.dstXY << 19)) >> 19;
voodoo->banshee_blt.dstY = ((int32_t) (voodoo->banshee_blt.dstXY << 3)) >> 19;
voodoo->banshee_blt.srcX = ((int32_t) (voodoo->banshee_blt.srcXY << 19)) >> 19;
voodoo->banshee_blt.srcY = ((int32_t) (voodoo->banshee_blt.srcXY << 3)) >> 19;
voodoo->banshee_blt.old_srcX = voodoo->banshee_blt.srcX;
voodoo->banshee_blt.host_data_remainder = 0;
voodoo->banshee_blt.host_data_count = 0;
switch (voodoo->banshee_blt.command & COMMAND_CMD_MASK) {
#if 0
case COMMAND_CMD_SCREEN_TO_SCREEN_STRETCH_BLT:
if (voodoo->banshee_blt.bresError0 & BRES_ERROR_USE)
voodoo->banshee_blt.bres_error_0 = (int32_t)(int16_t)(voodoo->banshee_blt.bresError0 & BRES_ERROR_MASK);
else
voodoo->banshee_blt.bres_error_0 = voodoo->banshee_blt.dstSizeY / 2;
if (voodoo->banshee_blt.bresError1 & BRES_ERROR_USE)
voodoo->banshee_blt.bres_error_1 = (int32_t)(int16_t)(voodoo->banshee_blt.bresError1 & BRES_ERROR_MASK);
else
voodoo->banshee_blt.bres_error_1 = voodoo->banshee_blt.dstSizeX / 2;
if (val & COMMAND_INITIATE)
banshee_do_2d_blit(voodoo, -1, 0);
break;*/
#endif
case COMMAND_CMD_POLYFILL:
if (val & COMMAND_INITIATE) {
voodoo->banshee_blt.dstXY = voodoo->banshee_blt.srcXY;
voodoo->banshee_blt.dstX = voodoo->banshee_blt.srcX;
voodoo->banshee_blt.dstY = voodoo->banshee_blt.srcY;
}
banshee_polyfill_start(voodoo);
break;
default:
if (val & COMMAND_INITIATE) {
banshee_do_2d_blit(voodoo, -1, 0);
#if 0
fatal("Initiate command!\n");
#endif
}
break;
}
break;
case 0x80:
case 0x84:
case 0x88:
case 0x8c:
case 0x90:
case 0x94:
case 0x98:
case 0x9c:
case 0xa0:
case 0xa4:
case 0xa8:
case 0xac:
case 0xb0:
case 0xb4:
case 0xb8:
case 0xbc:
case 0xc0:
case 0xc4:
case 0xc8:
case 0xcc:
case 0xd0:
case 0xd4:
case 0xd8:
case 0xdc:
case 0xe0:
case 0xe4:
case 0xe8:
case 0xec:
case 0xf0:
case 0xf4:
case 0xf8:
case 0xfc:
#if 0
bansheeblt_log("launch %08x %08x %08x %08x\n", voodoo->banshee_blt.command, voodoo->banshee_blt.commandExtra, voodoo->banshee_blt.srcColorkeyMin, voodoo->banshee_blt.srcColorkeyMax);
#endif
switch (voodoo->banshee_blt.command & COMMAND_CMD_MASK) {
case COMMAND_CMD_SCREEN_TO_SCREEN_BLT:
voodoo->banshee_blt.srcXY = val;
voodoo->banshee_blt.srcX = ((int32_t) (val << 19)) >> 19;
voodoo->banshee_blt.srcY = ((int32_t) (val << 3)) >> 19;
banshee_do_screen_to_screen_blt(voodoo);
break;
case COMMAND_CMD_HOST_TO_SCREEN_BLT:
banshee_do_2d_blit(voodoo, 32, val);
break;
case COMMAND_CMD_HOST_TO_SCREEN_STRETCH_BLT:
banshee_do_2d_blit(voodoo, 32, val);
break;
case COMMAND_CMD_RECTFILL:
voodoo->banshee_blt.dstXY = val;
voodoo->banshee_blt.dstX = ((int32_t) (val << 19)) >> 19;
voodoo->banshee_blt.dstY = ((int32_t) (val << 3)) >> 19;
banshee_do_rectfill(voodoo);
break;
case COMMAND_CMD_LINE:
voodoo->banshee_blt.dstXY = val;
voodoo->banshee_blt.dstX = ((int32_t) (val << 19)) >> 19;
voodoo->banshee_blt.dstY = ((int32_t) (val << 3)) >> 19;
banshee_do_line(voodoo, 1);
break;
case COMMAND_CMD_POLYLINE:
voodoo->banshee_blt.dstXY = val;
voodoo->banshee_blt.dstX = ((int32_t) (val << 19)) >> 19;
voodoo->banshee_blt.dstY = ((int32_t) (val << 3)) >> 19;
banshee_do_line(voodoo, 0);
break;
case COMMAND_CMD_POLYFILL:
banshee_polyfill_continue(voodoo, val);
break;
default:
fatal("launch area write, command=%08x\n", voodoo->banshee_blt.command);
}
break;
case 0x100:
case 0x104:
case 0x108:
case 0x10c:
case 0x110:
case 0x114:
case 0x118:
case 0x11c:
case 0x120:
case 0x124:
case 0x128:
case 0x12c:
case 0x130:
case 0x134:
case 0x138:
case 0x13c:
case 0x140:
case 0x144:
case 0x148:
case 0x14c:
case 0x150:
case 0x154:
case 0x158:
case 0x15c:
case 0x160:
case 0x164:
case 0x168:
case 0x16c:
case 0x170:
case 0x174:
case 0x178:
case 0x17c:
case 0x180:
case 0x184:
case 0x188:
case 0x18c:
case 0x190:
case 0x194:
case 0x198:
case 0x19c:
case 0x1a0:
case 0x1a4:
case 0x1a8:
case 0x1ac:
case 0x1b0:
case 0x1b4:
case 0x1b8:
case 0x1bc:
case 0x1c0:
case 0x1c4:
case 0x1c8:
case 0x1cc:
case 0x1d0:
case 0x1d4:
case 0x1d8:
case 0x1dc:
case 0x1e0:
case 0x1e4:
case 0x1e8:
case 0x1ec:
case 0x1f0:
case 0x1f4:
case 0x1f8:
case 0x1fc:
voodoo->banshee_blt.colorPattern[(addr >> 2) & 63] = val;
if ((addr & 0x1fc) < 0x1c0) {
int base_addr = (addr & 0xfc) / 0xc;
uintptr_t src_p = (uintptr_t) &voodoo->banshee_blt.colorPattern[base_addr * 3];
int col24 = base_addr * 4;
voodoo->banshee_blt.colorPattern24[col24] = *(uint32_t *) src_p & 0xffffff;
voodoo->banshee_blt.colorPattern24[col24 + 1] = *(uint32_t *) (src_p + 3) & 0xffffff;
voodoo->banshee_blt.colorPattern24[col24 + 2] = *(uint32_t *) (src_p + 6) & 0xffffff;
voodoo->banshee_blt.colorPattern24[col24 + 3] = *(uint32_t *) (src_p + 9) & 0xffffff;
}
if ((addr & 0x1fc) < 0x180) {
voodoo->banshee_blt.colorPattern16[(addr >> 1) & 62] = val & 0xffff;
voodoo->banshee_blt.colorPattern16[((addr >> 1) & 62) + 1] = (val >> 16) & 0xffff;
}
if ((addr & 0x1fc) < 0x140) {
voodoo->banshee_blt.colorPattern8[addr & 60] = val & 0xff;
voodoo->banshee_blt.colorPattern8[(addr & 60) + 1] = (val >> 8) & 0xff;
voodoo->banshee_blt.colorPattern8[(addr & 60) + 2] = (val >> 16) & 0xff;
voodoo->banshee_blt.colorPattern8[(addr & 60) + 3] = (val >> 24) & 0xff;
}
#if 0
bansheeblt_log("colorPattern%02x=%08x\n", (addr >> 2) & 63, val);
#endif
break;
default:
fatal("Unknown 2D reg write %03x %08x\n", addr & 0x1fc, val);
}
}
``` | /content/code_sandbox/src/video/vid_voodoo_banshee_blitter.c | c | 2016-06-25T22:29:10 | 2024-08-16T19:09:21 | 86Box | 86Box/86Box | 2,616 | 24,767 |
```c
/*
* 86Box A hypervisor and IBM PC system emulator that specializes in
* running old operating systems and software designed for IBM
* PC systems and compatibles from 1981 through fairly recent
* system designs based on the PCI bus.
*
* This file is part of the 86Box distribution.
*
* 3DFX Voodoo emulation.
*
*
*
* Authors: Sarah Walker, <path_to_url
*
*/
#include <stdarg.h>
#include <stdio.h>
#include <stdint.h>
#include <string.h>
#include <stdlib.h>
#include <stddef.h>
#include <wchar.h>
#include <math.h>
#define HAVE_STDARG_H
#include <86box/86box.h>
#include "cpu.h"
#include <86box/machine.h>
#include <86box/device.h>
#include <86box/mem.h>
#include <86box/timer.h>
#include <86box/device.h>
#include <86box/plat.h>
#include <86box/thread.h>
#include <86box/video.h>
#include <86box/vid_svga.h>
#include <86box/vid_voodoo_common.h>
#include <86box/vid_voodoo_banshee.h>
#include <86box/vid_voodoo_blitter.h>
#include <86box/vid_voodoo_dither.h>
#include <86box/vid_voodoo_fifo.h>
#include <86box/vid_voodoo_regs.h>
#include <86box/vid_voodoo_render.h>
#include <86box/vid_voodoo_setup.h>
#include <86box/vid_voodoo_texture.h>
enum {
CHIP_FBI = 0x1,
CHIP_TREX0 = 0x2,
CHIP_TREX1 = 0x4,
CHIP_TREX2 = 0x8
};
#ifdef ENABLE_VOODOO_REG_LOG
int voodoo_reg_do_log = ENABLE_VOODOO_REG_LOG;
static void
voodoo_reg_log(const char *fmt, ...)
{
va_list ap;
if (voodoo_reg_do_log) {
va_start(ap, fmt);
pclog_ex(fmt, ap);
va_end(ap);
}
}
#else
# define voodoo_reg_log(fmt, ...)
#endif
void
voodoo_reg_writel(uint32_t addr, uint32_t val, void *priv)
{
voodoo_t *voodoo = (voodoo_t *) priv;
void (*voodoo_recalc_tex)(voodoo_t * voodoo, int tmu) = NULL;
union {
uint32_t i;
float f;
} tempif;
int ad21 = addr & (1 << 21);
int chip = (addr >> 10) & 0xf;
if (!chip)
chip = 0xf;
if (voodoo->type == VOODOO_3)
voodoo_recalc_tex = voodoo_recalc_tex3;
else
voodoo_recalc_tex = voodoo_recalc_tex12;
tempif.i = val;
#if 0
voodoo_reg_log("voodoo_reg_write_l: addr=%08x val=%08x(%f) chip=%x\n", addr, val, tempif.f, chip);
#endif
addr &= 0x3fc;
if ((voodoo->fbiInit3 & FBIINIT3_REMAP) && addr < 0x100 && ad21)
addr |= 0x400;
switch (addr) {
case SST_swapbufferCMD:
if (voodoo->type >= VOODOO_BANSHEE) {
#if 0
voodoo_reg_log("swapbufferCMD %08x %08x\n", val, voodoo->leftOverlayBuf);
#endif
voodoo_wait_for_render_thread_idle(voodoo);
if (!(val & 1)) {
banshee_set_overlay_addr(voodoo->priv, voodoo->leftOverlayBuf);
thread_wait_mutex(voodoo->swap_mutex);
if (voodoo->swap_count > 0)
voodoo->swap_count--;
thread_release_mutex(voodoo->swap_mutex);
voodoo->frame_count++;
} else if (TRIPLE_BUFFER) {
if (voodoo->swap_pending)
voodoo_wait_for_swap_complete(voodoo);
voodoo->swap_interval = (val >> 1) & 0xff;
voodoo->swap_offset = voodoo->leftOverlayBuf;
voodoo->swap_pending = 1;
} else {
voodoo->swap_interval = (val >> 1) & 0xff;
voodoo->swap_offset = voodoo->leftOverlayBuf;
voodoo->swap_pending = 1;
voodoo_wait_for_swap_complete(voodoo);
}
voodoo->cmd_read++;
break;
}
if (TRIPLE_BUFFER) {
voodoo->disp_buffer = (voodoo->disp_buffer + 1) % 3;
voodoo->draw_buffer = (voodoo->draw_buffer + 1) % 3;
} else {
voodoo->disp_buffer = !voodoo->disp_buffer;
voodoo->draw_buffer = !voodoo->draw_buffer;
}
voodoo_recalc(voodoo);
voodoo->params.swapbufferCMD = val;
#if 0
voodoo_reg_log("Swap buffer %08x %d %p %i\n", val, voodoo->swap_count, &voodoo->swap_count, (voodoo == voodoo->set->voodoos[1]) ? 1 : 0);
voodoo->front_offset = params->front_offset;
#endif
voodoo_wait_for_render_thread_idle(voodoo);
if (!(val & 1)) {
memset(voodoo->dirty_line, 1, sizeof(voodoo->dirty_line));
voodoo->front_offset = voodoo->params.front_offset;
thread_wait_mutex(voodoo->swap_mutex);
if (voodoo->swap_count > 0)
voodoo->swap_count--;
thread_release_mutex(voodoo->swap_mutex);
} else if (TRIPLE_BUFFER) {
if (voodoo->swap_pending)
voodoo_wait_for_swap_complete(voodoo);
voodoo->swap_interval = (val >> 1) & 0xff;
voodoo->swap_offset = voodoo->params.front_offset;
voodoo->swap_pending = 1;
} else {
voodoo->swap_interval = (val >> 1) & 0xff;
voodoo->swap_offset = voodoo->params.front_offset;
voodoo->swap_pending = 1;
voodoo_wait_for_swap_complete(voodoo);
}
voodoo->cmd_read++;
break;
case SST_vertexAx:
case SST_remap_vertexAx:
voodoo->params.vertexAx = val & 0xffff;
break;
case SST_vertexAy:
case SST_remap_vertexAy:
voodoo->params.vertexAy = val & 0xffff;
break;
case SST_vertexBx:
case SST_remap_vertexBx:
voodoo->params.vertexBx = val & 0xffff;
break;
case SST_vertexBy:
case SST_remap_vertexBy:
voodoo->params.vertexBy = val & 0xffff;
break;
case SST_vertexCx:
case SST_remap_vertexCx:
voodoo->params.vertexCx = val & 0xffff;
break;
case SST_vertexCy:
case SST_remap_vertexCy:
voodoo->params.vertexCy = val & 0xffff;
break;
case SST_startR:
case SST_remap_startR:
voodoo->params.startR = val & 0xffffff;
break;
case SST_startG:
case SST_remap_startG:
voodoo->params.startG = val & 0xffffff;
break;
case SST_startB:
case SST_remap_startB:
voodoo->params.startB = val & 0xffffff;
break;
case SST_startZ:
case SST_remap_startZ:
voodoo->params.startZ = val;
break;
case SST_startA:
case SST_remap_startA:
voodoo->params.startA = val & 0xffffff;
break;
case SST_startS:
case SST_remap_startS:
if (chip & CHIP_TREX0)
voodoo->params.tmu[0].startS = ((int64_t) (int32_t) val) << 14;
if (chip & CHIP_TREX1)
voodoo->params.tmu[1].startS = ((int64_t) (int32_t) val) << 14;
break;
case SST_startT:
case SST_remap_startT:
if (chip & CHIP_TREX0)
voodoo->params.tmu[0].startT = ((int64_t) (int32_t) val) << 14;
if (chip & CHIP_TREX1)
voodoo->params.tmu[1].startT = ((int64_t) (int32_t) val) << 14;
break;
case SST_startW:
case SST_remap_startW:
if (chip & CHIP_FBI)
voodoo->params.startW = (int64_t) (int32_t) val << 2;
if (chip & CHIP_TREX0)
voodoo->params.tmu[0].startW = (int64_t) (int32_t) val << 2;
if (chip & CHIP_TREX1)
voodoo->params.tmu[1].startW = (int64_t) (int32_t) val << 2;
break;
case SST_dRdX:
case SST_remap_dRdX:
voodoo->params.dRdX = (val & 0xffffff) | ((val & 0x800000) ? 0xff000000 : 0);
break;
case SST_dGdX:
case SST_remap_dGdX:
voodoo->params.dGdX = (val & 0xffffff) | ((val & 0x800000) ? 0xff000000 : 0);
break;
case SST_dBdX:
case SST_remap_dBdX:
voodoo->params.dBdX = (val & 0xffffff) | ((val & 0x800000) ? 0xff000000 : 0);
break;
case SST_dZdX:
case SST_remap_dZdX:
voodoo->params.dZdX = val;
break;
case SST_dAdX:
case SST_remap_dAdX:
voodoo->params.dAdX = (val & 0xffffff) | ((val & 0x800000) ? 0xff000000 : 0);
break;
case SST_dSdX:
case SST_remap_dSdX:
if (chip & CHIP_TREX0)
voodoo->params.tmu[0].dSdX = ((int64_t) (int32_t) val) << 14;
if (chip & CHIP_TREX1)
voodoo->params.tmu[1].dSdX = ((int64_t) (int32_t) val) << 14;
break;
case SST_dTdX:
case SST_remap_dTdX:
if (chip & CHIP_TREX0)
voodoo->params.tmu[0].dTdX = ((int64_t) (int32_t) val) << 14;
if (chip & CHIP_TREX1)
voodoo->params.tmu[1].dTdX = ((int64_t) (int32_t) val) << 14;
break;
case SST_dWdX:
case SST_remap_dWdX:
if (chip & CHIP_TREX0)
voodoo->params.tmu[0].dWdX = (int64_t) (int32_t) val << 2;
if (chip & CHIP_TREX1)
voodoo->params.tmu[1].dWdX = (int64_t) (int32_t) val << 2;
if (chip & CHIP_FBI)
voodoo->params.dWdX = (int64_t) (int32_t) val << 2;
break;
case SST_dRdY:
case SST_remap_dRdY:
voodoo->params.dRdY = (val & 0xffffff) | ((val & 0x800000) ? 0xff000000 : 0);
break;
case SST_dGdY:
case SST_remap_dGdY:
voodoo->params.dGdY = (val & 0xffffff) | ((val & 0x800000) ? 0xff000000 : 0);
break;
case SST_dBdY:
case SST_remap_dBdY:
voodoo->params.dBdY = (val & 0xffffff) | ((val & 0x800000) ? 0xff000000 : 0);
break;
case SST_dZdY:
case SST_remap_dZdY:
voodoo->params.dZdY = val;
break;
case SST_dAdY:
case SST_remap_dAdY:
voodoo->params.dAdY = (val & 0xffffff) | ((val & 0x800000) ? 0xff000000 : 0);
break;
case SST_dSdY:
case SST_remap_dSdY:
if (chip & CHIP_TREX0)
voodoo->params.tmu[0].dSdY = ((int64_t) (int32_t) val) << 14;
if (chip & CHIP_TREX1)
voodoo->params.tmu[1].dSdY = ((int64_t) (int32_t) val) << 14;
break;
case SST_dTdY:
case SST_remap_dTdY:
if (chip & CHIP_TREX0)
voodoo->params.tmu[0].dTdY = ((int64_t) (int32_t) val) << 14;
if (chip & CHIP_TREX1)
voodoo->params.tmu[1].dTdY = ((int64_t) (int32_t) val) << 14;
break;
case SST_dWdY:
case SST_remap_dWdY:
if (chip & CHIP_TREX0)
voodoo->params.tmu[0].dWdY = (int64_t) (int32_t) val << 2;
if (chip & CHIP_TREX1)
voodoo->params.tmu[1].dWdY = (int64_t) (int32_t) val << 2;
if (chip & CHIP_FBI)
voodoo->params.dWdY = (int64_t) (int32_t) val << 2;
break;
case SST_triangleCMD:
case SST_remap_triangleCMD:
voodoo->params.sign = val & (1 << 31);
if (voodoo->ncc_dirty[0])
voodoo_update_ncc(voodoo, 0);
if (voodoo->ncc_dirty[1])
voodoo_update_ncc(voodoo, 1);
voodoo->ncc_dirty[0] = voodoo->ncc_dirty[1] = 0;
voodoo_queue_triangle(voodoo, &voodoo->params);
voodoo->cmd_read++;
break;
case SST_fvertexAx:
case SST_remap_fvertexAx:
voodoo->fvertexAx.i = val;
voodoo->params.vertexAx = (int32_t) (int16_t) (int32_t) (voodoo->fvertexAx.f * 16.0f) & 0xffff;
break;
case SST_fvertexAy:
case SST_remap_fvertexAy:
voodoo->fvertexAy.i = val;
voodoo->params.vertexAy = (int32_t) (int16_t) (int32_t) (voodoo->fvertexAy.f * 16.0f) & 0xffff;
break;
case SST_fvertexBx:
case SST_remap_fvertexBx:
voodoo->fvertexBx.i = val;
voodoo->params.vertexBx = (int32_t) (int16_t) (int32_t) (voodoo->fvertexBx.f * 16.0f) & 0xffff;
break;
case SST_fvertexBy:
case SST_remap_fvertexBy:
voodoo->fvertexBy.i = val;
voodoo->params.vertexBy = (int32_t) (int16_t) (int32_t) (voodoo->fvertexBy.f * 16.0f) & 0xffff;
break;
case SST_fvertexCx:
case SST_remap_fvertexCx:
voodoo->fvertexCx.i = val;
voodoo->params.vertexCx = (int32_t) (int16_t) (int32_t) (voodoo->fvertexCx.f * 16.0f) & 0xffff;
break;
case SST_fvertexCy:
case SST_remap_fvertexCy:
voodoo->fvertexCy.i = val;
voodoo->params.vertexCy = (int32_t) (int16_t) (int32_t) (voodoo->fvertexCy.f * 16.0f) & 0xffff;
break;
case SST_fstartR:
case SST_remap_fstartR:
tempif.i = val;
voodoo->params.startR = (int32_t) (tempif.f * 4096.0f);
break;
case SST_fstartG:
case SST_remap_fstartG:
tempif.i = val;
voodoo->params.startG = (int32_t) (tempif.f * 4096.0f);
break;
case SST_fstartB:
case SST_remap_fstartB:
tempif.i = val;
voodoo->params.startB = (int32_t) (tempif.f * 4096.0f);
break;
case SST_fstartZ:
case SST_remap_fstartZ:
tempif.i = val;
voodoo->params.startZ = (int32_t) (tempif.f * 4096.0f);
break;
case SST_fstartA:
case SST_remap_fstartA:
tempif.i = val;
voodoo->params.startA = (int32_t) (tempif.f * 4096.0f);
break;
case SST_fstartS:
case SST_remap_fstartS:
tempif.i = val;
if (chip & CHIP_TREX0)
voodoo->params.tmu[0].startS = (int64_t) (tempif.f * 4294967296.0f);
if (chip & CHIP_TREX1)
voodoo->params.tmu[1].startS = (int64_t) (tempif.f * 4294967296.0f);
break;
case SST_fstartT:
case SST_remap_fstartT:
tempif.i = val;
if (chip & CHIP_TREX0)
voodoo->params.tmu[0].startT = (int64_t) (tempif.f * 4294967296.0f);
if (chip & CHIP_TREX1)
voodoo->params.tmu[1].startT = (int64_t) (tempif.f * 4294967296.0f);
break;
case SST_fstartW:
case SST_remap_fstartW:
tempif.i = val;
if (chip & CHIP_TREX0)
voodoo->params.tmu[0].startW = (int64_t) (tempif.f * 4294967296.0f);
if (chip & CHIP_TREX1)
voodoo->params.tmu[1].startW = (int64_t) (tempif.f * 4294967296.0f);
if (chip & CHIP_FBI)
voodoo->params.startW = (int64_t) (tempif.f * 4294967296.0f);
break;
case SST_fdRdX:
case SST_remap_fdRdX:
tempif.i = val;
voodoo->params.dRdX = (int32_t) (tempif.f * 4096.0f);
break;
case SST_fdGdX:
case SST_remap_fdGdX:
tempif.i = val;
voodoo->params.dGdX = (int32_t) (tempif.f * 4096.0f);
break;
case SST_fdBdX:
case SST_remap_fdBdX:
tempif.i = val;
voodoo->params.dBdX = (int32_t) (tempif.f * 4096.0f);
break;
case SST_fdZdX:
case SST_remap_fdZdX:
tempif.i = val;
voodoo->params.dZdX = (int32_t) (tempif.f * 4096.0f);
break;
case SST_fdAdX:
case SST_remap_fdAdX:
tempif.i = val;
voodoo->params.dAdX = (int32_t) (tempif.f * 4096.0f);
break;
case SST_fdSdX:
case SST_remap_fdSdX:
tempif.i = val;
if (chip & CHIP_TREX0)
voodoo->params.tmu[0].dSdX = (int64_t) (tempif.f * 4294967296.0f);
if (chip & CHIP_TREX1)
voodoo->params.tmu[1].dSdX = (int64_t) (tempif.f * 4294967296.0f);
break;
case SST_fdTdX:
case SST_remap_fdTdX:
tempif.i = val;
if (chip & CHIP_TREX0)
voodoo->params.tmu[0].dTdX = (int64_t) (tempif.f * 4294967296.0f);
if (chip & CHIP_TREX1)
voodoo->params.tmu[1].dTdX = (int64_t) (tempif.f * 4294967296.0f);
break;
case SST_fdWdX:
case SST_remap_fdWdX:
tempif.i = val;
if (chip & CHIP_TREX0)
voodoo->params.tmu[0].dWdX = (int64_t) (tempif.f * 4294967296.0f);
if (chip & CHIP_TREX1)
voodoo->params.tmu[1].dWdX = (int64_t) (tempif.f * 4294967296.0f);
if (chip & CHIP_FBI)
voodoo->params.dWdX = (int64_t) (tempif.f * 4294967296.0f);
break;
case SST_fdRdY:
case SST_remap_fdRdY:
tempif.i = val;
voodoo->params.dRdY = (int32_t) (tempif.f * 4096.0f);
break;
case SST_fdGdY:
case SST_remap_fdGdY:
tempif.i = val;
voodoo->params.dGdY = (int32_t) (tempif.f * 4096.0f);
break;
case SST_fdBdY:
case SST_remap_fdBdY:
tempif.i = val;
voodoo->params.dBdY = (int32_t) (tempif.f * 4096.0f);
break;
case SST_fdZdY:
case SST_remap_fdZdY:
tempif.i = val;
voodoo->params.dZdY = (int32_t) (tempif.f * 4096.0f);
break;
case SST_fdAdY:
case SST_remap_fdAdY:
tempif.i = val;
voodoo->params.dAdY = (int32_t) (tempif.f * 4096.0f);
break;
case SST_fdSdY:
case SST_remap_fdSdY:
tempif.i = val;
if (chip & CHIP_TREX0)
voodoo->params.tmu[0].dSdY = (int64_t) (tempif.f * 4294967296.0f);
if (chip & CHIP_TREX1)
voodoo->params.tmu[1].dSdY = (int64_t) (tempif.f * 4294967296.0f);
break;
case SST_fdTdY:
case SST_remap_fdTdY:
tempif.i = val;
if (chip & CHIP_TREX0)
voodoo->params.tmu[0].dTdY = (int64_t) (tempif.f * 4294967296.0f);
if (chip & CHIP_TREX1)
voodoo->params.tmu[1].dTdY = (int64_t) (tempif.f * 4294967296.0f);
break;
case SST_fdWdY:
case SST_remap_fdWdY:
tempif.i = val;
if (chip & CHIP_TREX0)
voodoo->params.tmu[0].dWdY = (int64_t) (tempif.f * 4294967296.0f);
if (chip & CHIP_TREX1)
voodoo->params.tmu[1].dWdY = (int64_t) (tempif.f * 4294967296.0f);
if (chip & CHIP_FBI)
voodoo->params.dWdY = (int64_t) (tempif.f * 4294967296.0f);
break;
case SST_ftriangleCMD:
voodoo->params.sign = val & (1 << 31);
if (voodoo->ncc_dirty[0])
voodoo_update_ncc(voodoo, 0);
if (voodoo->ncc_dirty[1])
voodoo_update_ncc(voodoo, 1);
voodoo->ncc_dirty[0] = voodoo->ncc_dirty[1] = 0;
voodoo_queue_triangle(voodoo, &voodoo->params);
voodoo->cmd_read++;
break;
case SST_fbzColorPath:
voodoo->params.fbzColorPath = val;
voodoo->rgb_sel = val & 3;
break;
case SST_fogMode:
voodoo->params.fogMode = val;
break;
case SST_alphaMode:
voodoo->params.alphaMode = val;
break;
case SST_fbzMode:
voodoo->params.fbzMode = val;
voodoo_recalc(voodoo);
break;
case SST_lfbMode:
voodoo->lfbMode = val;
voodoo_recalc(voodoo);
break;
case SST_clipLeftRight:
if (voodoo->type >= VOODOO_2) {
voodoo->params.clipRight = val & 0xfff;
voodoo->params.clipLeft = (val >> 16) & 0xfff;
} else {
voodoo->params.clipRight = val & 0x3ff;
voodoo->params.clipLeft = (val >> 16) & 0x3ff;
}
break;
case SST_clipLowYHighY:
if (voodoo->type >= VOODOO_2) {
voodoo->params.clipHighY = val & 0xfff;
voodoo->params.clipLowY = (val >> 16) & 0xfff;
} else {
voodoo->params.clipHighY = val & 0x3ff;
voodoo->params.clipLowY = (val >> 16) & 0x3ff;
}
break;
case SST_nopCMD:
voodoo->cmd_read++;
voodoo->fbiPixelsIn = 0;
voodoo->fbiChromaFail = 0;
voodoo->fbiZFuncFail = 0;
voodoo->fbiAFuncFail = 0;
voodoo->fbiPixelsOut = 0;
break;
case SST_fastfillCMD:
voodoo_wait_for_render_thread_idle(voodoo);
voodoo_fastfill(voodoo, &voodoo->params);
voodoo->cmd_read++;
break;
case SST_fogColor:
voodoo->params.fogColor.r = (val >> 16) & 0xff;
voodoo->params.fogColor.g = (val >> 8) & 0xff;
voodoo->params.fogColor.b = val & 0xff;
break;
case SST_zaColor:
voodoo->params.zaColor = val;
break;
case SST_chromaKey:
voodoo->params.chromaKey_r = (val >> 16) & 0xff;
voodoo->params.chromaKey_g = (val >> 8) & 0xff;
voodoo->params.chromaKey_b = val & 0xff;
voodoo->params.chromaKey = val & 0xffffff;
break;
case SST_stipple:
voodoo->params.stipple = val;
break;
case SST_color0:
voodoo->params.color0 = val;
break;
case SST_color1:
voodoo->params.color1 = val;
break;
case SST_fogTable00:
case SST_fogTable01:
case SST_fogTable02:
case SST_fogTable03:
case SST_fogTable04:
case SST_fogTable05:
case SST_fogTable06:
case SST_fogTable07:
case SST_fogTable08:
case SST_fogTable09:
case SST_fogTable0a:
case SST_fogTable0b:
case SST_fogTable0c:
case SST_fogTable0d:
case SST_fogTable0e:
case SST_fogTable0f:
case SST_fogTable10:
case SST_fogTable11:
case SST_fogTable12:
case SST_fogTable13:
case SST_fogTable14:
case SST_fogTable15:
case SST_fogTable16:
case SST_fogTable17:
case SST_fogTable18:
case SST_fogTable19:
case SST_fogTable1a:
case SST_fogTable1b:
case SST_fogTable1c:
case SST_fogTable1d:
case SST_fogTable1e:
case SST_fogTable1f:
addr = (addr - SST_fogTable00) >> 1;
voodoo->params.fogTable[addr].dfog = val & 0xff;
voodoo->params.fogTable[addr].fog = (val >> 8) & 0xff;
voodoo->params.fogTable[addr + 1].dfog = (val >> 16) & 0xff;
voodoo->params.fogTable[addr + 1].fog = (val >> 24) & 0xff;
break;
case SST_clipLeftRight1:
if (voodoo->type >= VOODOO_BANSHEE) {
voodoo->params.clipRight1 = val & 0xfff;
voodoo->params.clipLeft1 = (val >> 16) & 0xfff;
}
break;
case SST_clipTopBottom1:
if (voodoo->type >= VOODOO_BANSHEE) {
voodoo->params.clipHighY1 = val & 0xfff;
voodoo->params.clipLowY1 = (val >> 16) & 0xfff;
}
break;
case SST_colBufferAddr:
if (voodoo->type >= VOODOO_BANSHEE) {
voodoo->params.draw_offset = val & 0xfffff0;
voodoo->fb_write_offset = voodoo->params.draw_offset;
#if 0
voodoo_reg_log("colorBufferAddr=%06x\n", voodoo->params.draw_offset);
#endif
}
break;
case SST_colBufferStride:
if (voodoo->type >= VOODOO_BANSHEE) {
voodoo->col_tiled = val & (1 << 15);
voodoo->params.col_tiled = voodoo->col_tiled;
if (voodoo->col_tiled) {
voodoo->row_width = (val & 0x7f) * 128 * 32;
#if 0
voodoo_reg_log("colBufferStride tiled = %i bytes, tiled %08x\n", voodoo->row_width, val);
#endif
} else {
voodoo->row_width = val & 0x3fff;
#if 0
voodoo_reg_log("colBufferStride linear = %i bytes, linear\n", voodoo->row_width);
#endif
}
voodoo->params.row_width = voodoo->row_width;
}
break;
case SST_auxBufferAddr:
if (voodoo->type >= VOODOO_BANSHEE) {
voodoo->params.aux_offset = val & 0xfffff0;
#if 0
pclog("auxBufferAddr=%06x\n", voodoo->params.aux_offset);
#endif
}
break;
case SST_auxBufferStride:
if (voodoo->type >= VOODOO_BANSHEE) {
voodoo->aux_tiled = val & (1 << 15);
voodoo->params.aux_tiled = voodoo->aux_tiled;
if (voodoo->aux_tiled) {
voodoo->aux_row_width = (val & 0x7f) * 128 * 32;
#if 0
voodoo_reg_log("auxBufferStride tiled = %i bytes, tiled\n", voodoo->aux_row_width);
#endif
} else {
voodoo->aux_row_width = val & 0x3fff;
#if 0
voodoo_reg_log("auxBufferStride linear = %i bytes, linear\n", voodoo->aux_row_width);
#endif
}
voodoo->params.aux_row_width = voodoo->aux_row_width;
}
break;
case SST_clutData:
voodoo->clutData[(val >> 24) & 0x3f].b = val & 0xff;
voodoo->clutData[(val >> 24) & 0x3f].g = (val >> 8) & 0xff;
voodoo->clutData[(val >> 24) & 0x3f].r = (val >> 16) & 0xff;
if (val & 0x20000000) {
voodoo->clutData[(val >> 24) & 0x3f].b = 255;
voodoo->clutData[(val >> 24) & 0x3f].g = 255;
voodoo->clutData[(val >> 24) & 0x3f].r = 255;
}
voodoo->clutData_dirty = 1;
break;
case SST_sSetupMode:
voodoo->sSetupMode = val;
break;
case SST_sVx:
tempif.i = val;
voodoo->verts[3].sVx = tempif.f;
#if 0
voodoo_reg_log("sVx[%i]=%f\n", voodoo->vertex_num, tempif.f);
#endif
break;
case SST_sVy:
tempif.i = val;
voodoo->verts[3].sVy = tempif.f;
#if 0
voodoo_reg_log("sVy[%i]=%f\n", voodoo->vertex_num, tempif.f);
#endif
break;
case SST_sARGB:
voodoo->verts[3].sBlue = (float) (val & 0xff);
voodoo->verts[3].sGreen = (float) ((val >> 8) & 0xff);
voodoo->verts[3].sRed = (float) ((val >> 16) & 0xff);
voodoo->verts[3].sAlpha = (float) ((val >> 24) & 0xff);
break;
case SST_sRed:
tempif.i = val;
voodoo->verts[3].sRed = tempif.f;
break;
case SST_sGreen:
tempif.i = val;
voodoo->verts[3].sGreen = tempif.f;
break;
case SST_sBlue:
tempif.i = val;
voodoo->verts[3].sBlue = tempif.f;
break;
case SST_sAlpha:
tempif.i = val;
voodoo->verts[3].sAlpha = tempif.f;
break;
case SST_sVz:
tempif.i = val;
voodoo->verts[3].sVz = tempif.f;
break;
case SST_sWb:
tempif.i = val;
voodoo->verts[3].sWb = tempif.f;
break;
case SST_sW0:
tempif.i = val;
voodoo->verts[3].sW0 = tempif.f;
break;
case SST_sS0:
tempif.i = val;
voodoo->verts[3].sS0 = tempif.f;
break;
case SST_sT0:
tempif.i = val;
voodoo->verts[3].sT0 = tempif.f;
break;
case SST_sW1:
tempif.i = val;
voodoo->verts[3].sW1 = tempif.f;
break;
case SST_sS1:
tempif.i = val;
voodoo->verts[3].sS1 = tempif.f;
break;
case SST_sT1:
tempif.i = val;
voodoo->verts[3].sT1 = tempif.f;
break;
case SST_sBeginTriCMD:
#if 0
voodoo_reg_log("sBeginTriCMD %i %f\n", voodoo->vertex_num, voodoo->verts[4].sVx);
#endif
voodoo->verts[0] = voodoo->verts[3];
voodoo->verts[1] = voodoo->verts[3];
voodoo->verts[2] = voodoo->verts[3];
voodoo->vertex_next_age = 0;
voodoo->vertex_ages[0] = voodoo->vertex_next_age++;
voodoo->num_verticies = 1;
voodoo->cull_pingpong = 0;
break;
case SST_sDrawTriCMD:
#if 0
voodoo_reg_log("sDrawTriCMD %i %i\n", voodoo->num_verticies, voodoo->sSetupMode & SETUPMODE_STRIP_MODE);
#endif
/*I'm not sure this is the vertex selection algorithm actually used in the 3dfx
chips, but this works with a number of games that switch between strip and fan
mode in the middle of a run (eg Black & White, Viper Racing)*/
if (voodoo->vertex_next_age < 3) {
/*Fewer than three vertices already written, store in next slot*/
int vertex_nr = voodoo->vertex_next_age;
voodoo->verts[vertex_nr] = voodoo->verts[3];
voodoo->vertex_ages[vertex_nr] = voodoo->vertex_next_age++;
} else {
int vertex_nr = 0;
if (!(voodoo->sSetupMode & SETUPMODE_STRIP_MODE)) {
/*Strip - find oldest vertex*/
if ((voodoo->vertex_ages[0] < voodoo->vertex_ages[1]) && (voodoo->vertex_ages[0] < voodoo->vertex_ages[2]))
vertex_nr = 0;
else if ((voodoo->vertex_ages[1] < voodoo->vertex_ages[0]) && (voodoo->vertex_ages[1] < voodoo->vertex_ages[2]))
vertex_nr = 1;
else
vertex_nr = 2;
} else {
/*Fan - find second oldest vertex (ie pivot around oldest)*/
if ((voodoo->vertex_ages[1] < voodoo->vertex_ages[0]) && (voodoo->vertex_ages[0] < voodoo->vertex_ages[2]))
vertex_nr = 0;
else if ((voodoo->vertex_ages[2] < voodoo->vertex_ages[0]) && (voodoo->vertex_ages[0] < voodoo->vertex_ages[1]))
vertex_nr = 0;
else if ((voodoo->vertex_ages[0] < voodoo->vertex_ages[1]) && (voodoo->vertex_ages[1] < voodoo->vertex_ages[2]))
vertex_nr = 1;
else if ((voodoo->vertex_ages[2] < voodoo->vertex_ages[1]) && (voodoo->vertex_ages[1] < voodoo->vertex_ages[0]))
vertex_nr = 1;
else
vertex_nr = 2;
}
voodoo->verts[vertex_nr] = voodoo->verts[3];
voodoo->vertex_ages[vertex_nr] = voodoo->vertex_next_age++;
}
voodoo->num_verticies++;
if (voodoo->num_verticies == 3) {
#if 0
voodoo_reg_log("triangle_setup\n");
#endif
voodoo_triangle_setup(voodoo);
voodoo->cull_pingpong = !voodoo->cull_pingpong;
voodoo->num_verticies = 2;
}
break;
case SST_bltSrcBaseAddr:
voodoo->bltSrcBaseAddr = val & 0x3fffff;
break;
case SST_bltDstBaseAddr:
#if 0
voodoo_reg_log("Write bltDstBaseAddr %08x\n", val);
#endif
voodoo->bltDstBaseAddr = val & 0x3fffff;
break;
case SST_bltXYStrides:
voodoo->bltSrcXYStride = val & 0xfff;
voodoo->bltDstXYStride = (val >> 16) & 0xfff;
// voodoo_reg_log("Write bltXYStrides %08x\n", val);
break;
case SST_bltSrcChromaRange:
voodoo->bltSrcChromaRange = val;
voodoo->bltSrcChromaMinB = val & 0x1f;
voodoo->bltSrcChromaMinG = (val >> 5) & 0x3f;
voodoo->bltSrcChromaMinR = (val >> 11) & 0x1f;
voodoo->bltSrcChromaMaxB = (val >> 16) & 0x1f;
voodoo->bltSrcChromaMaxG = (val >> 21) & 0x3f;
voodoo->bltSrcChromaMaxR = (val >> 27) & 0x1f;
break;
case SST_bltDstChromaRange:
voodoo->bltDstChromaRange = val;
voodoo->bltDstChromaMinB = val & 0x1f;
voodoo->bltDstChromaMinG = (val >> 5) & 0x3f;
voodoo->bltDstChromaMinR = (val >> 11) & 0x1f;
voodoo->bltDstChromaMaxB = (val >> 16) & 0x1f;
voodoo->bltDstChromaMaxG = (val >> 21) & 0x3f;
voodoo->bltDstChromaMaxR = (val >> 27) & 0x1f;
break;
case SST_bltClipX:
voodoo->bltClipRight = val & 0xfff;
voodoo->bltClipLeft = (val >> 16) & 0xfff;
break;
case SST_bltClipY:
voodoo->bltClipHighY = val & 0xfff;
voodoo->bltClipLowY = (val >> 16) & 0xfff;
break;
case SST_bltSrcXY:
voodoo->bltSrcX = val & 0x7ff;
voodoo->bltSrcY = (val >> 16) & 0x7ff;
break;
case SST_bltDstXY:
// voodoo_reg_log("Write bltDstXY %08x\n", val);
voodoo->bltDstX = val & 0x7ff;
voodoo->bltDstY = (val >> 16) & 0x7ff;
if (val & (1 << 31))
voodoo_v2_blit_start(voodoo);
break;
case SST_bltSize:
// voodoo_reg_log("Write bltSize %08x\n", val);
voodoo->bltSizeX = val & 0xfff;
if (voodoo->bltSizeX & 0x800)
voodoo->bltSizeX |= 0xfffff000;
voodoo->bltSizeY = (val >> 16) & 0xfff;
if (voodoo->bltSizeY & 0x800)
voodoo->bltSizeY |= 0xfffff000;
if (val & (1 << 31))
voodoo_v2_blit_start(voodoo);
break;
case SST_bltRop:
voodoo->bltRop[0] = val & 0xf;
voodoo->bltRop[1] = (val >> 4) & 0xf;
voodoo->bltRop[2] = (val >> 8) & 0xf;
voodoo->bltRop[3] = (val >> 12) & 0xf;
break;
case SST_bltColor:
// voodoo_reg_log("Write bltColor %08x\n", val);
voodoo->bltColorFg = val & 0xffff;
voodoo->bltColorBg = (val >> 16) & 0xffff;
break;
case SST_bltCommand:
voodoo->bltCommand = val;
// voodoo_reg_log("Write bltCommand %08x\n", val);
if (val & (1 << 31))
voodoo_v2_blit_start(voodoo);
break;
case SST_bltData:
voodoo_v2_blit_data(voodoo, val);
break;
case SST_textureMode:
if (chip & CHIP_TREX0) {
voodoo->params.textureMode[0] = val;
voodoo->params.tformat[0] = (val >> 8) & 0xf;
}
if (chip & CHIP_TREX1) {
voodoo->params.textureMode[1] = val;
voodoo->params.tformat[1] = (val >> 8) & 0xf;
}
break;
case SST_tLOD:
if (chip & CHIP_TREX0) {
voodoo->params.tLOD[0] = val;
voodoo_recalc_tex(voodoo, 0);
}
if (chip & CHIP_TREX1) {
voodoo->params.tLOD[1] = val;
voodoo_recalc_tex(voodoo, 1);
}
break;
case SST_tDetail:
if (chip & CHIP_TREX0) {
voodoo->params.detail_max[0] = val & 0xff;
voodoo->params.detail_bias[0] = (val >> 8) & 0x3f;
voodoo->params.detail_scale[0] = (val >> 14) & 7;
}
if (chip & CHIP_TREX1) {
voodoo->params.detail_max[1] = val & 0xff;
voodoo->params.detail_bias[1] = (val >> 8) & 0x3f;
voodoo->params.detail_scale[1] = (val >> 14) & 7;
}
break;
case SST_texBaseAddr:
if (chip & CHIP_TREX0) {
if (voodoo->type >= VOODOO_BANSHEE)
voodoo->params.texBaseAddr[0] = val & 0xfffff0;
else
voodoo->params.texBaseAddr[0] = (val & 0x7ffff) << 3;
#if 0
voodoo_reg_log("texBaseAddr = %08x %08x\n", voodoo->params.texBaseAddr[0], val);
#endif
voodoo_recalc_tex(voodoo, 0);
}
if (chip & CHIP_TREX1) {
if (voodoo->type >= VOODOO_BANSHEE)
voodoo->params.texBaseAddr[1] = val & 0xfffff0;
else
voodoo->params.texBaseAddr[1] = (val & 0x7ffff) << 3;
voodoo_recalc_tex(voodoo, 1);
}
break;
case SST_texBaseAddr1:
if (chip & CHIP_TREX0) {
if (voodoo->type >= VOODOO_BANSHEE)
voodoo->params.texBaseAddr1[0] = val & 0xfffff0;
else
voodoo->params.texBaseAddr1[0] = (val & 0x7ffff) << 3;
voodoo_recalc_tex(voodoo, 0);
}
if (chip & CHIP_TREX1) {
if (voodoo->type >= VOODOO_BANSHEE)
voodoo->params.texBaseAddr1[1] = val & 0xfffff0;
else
voodoo->params.texBaseAddr1[1] = (val & 0x7ffff) << 3;
voodoo_recalc_tex(voodoo, 1);
}
break;
case SST_texBaseAddr2:
if (chip & CHIP_TREX0) {
if (voodoo->type >= VOODOO_BANSHEE)
voodoo->params.texBaseAddr2[0] = val & 0xfffff0;
else
voodoo->params.texBaseAddr2[0] = (val & 0x7ffff) << 3;
voodoo_recalc_tex(voodoo, 0);
}
if (chip & CHIP_TREX1) {
if (voodoo->type >= VOODOO_BANSHEE)
voodoo->params.texBaseAddr2[1] = val & 0xfffff0;
else
voodoo->params.texBaseAddr2[1] = (val & 0x7ffff) << 3;
voodoo_recalc_tex(voodoo, 1);
}
break;
case SST_texBaseAddr38:
if (chip & CHIP_TREX0) {
if (voodoo->type >= VOODOO_BANSHEE)
voodoo->params.texBaseAddr38[0] = val & 0xfffff0;
else
voodoo->params.texBaseAddr38[0] = (val & 0x7ffff) << 3;
voodoo_recalc_tex(voodoo, 0);
}
if (chip & CHIP_TREX1) {
if (voodoo->type >= VOODOO_BANSHEE)
voodoo->params.texBaseAddr38[1] = val & 0xfffff0;
else
voodoo->params.texBaseAddr38[1] = (val & 0x7ffff) << 3;
voodoo_recalc_tex(voodoo, 1);
}
break;
case SST_trexInit1:
if (chip & CHIP_TREX0)
voodoo->trexInit1[0] = val;
if (chip & CHIP_TREX1)
voodoo->trexInit1[1] = val;
break;
case SST_nccTable0_Y0:
if (chip & CHIP_TREX0) {
voodoo->nccTable[0][0].y[0] = val;
voodoo->ncc_dirty[0] = 1;
}
if (chip & CHIP_TREX1) {
voodoo->nccTable[1][0].y[0] = val;
voodoo->ncc_dirty[1] = 1;
}
break;
case SST_nccTable0_Y1:
if (chip & CHIP_TREX0) {
voodoo->nccTable[0][0].y[1] = val;
voodoo->ncc_dirty[0] = 1;
}
if (chip & CHIP_TREX1) {
voodoo->nccTable[1][0].y[1] = val;
voodoo->ncc_dirty[1] = 1;
}
break;
case SST_nccTable0_Y2:
if (chip & CHIP_TREX0) {
voodoo->nccTable[0][0].y[2] = val;
voodoo->ncc_dirty[0] = 1;
}
if (chip & CHIP_TREX1) {
voodoo->nccTable[1][0].y[2] = val;
voodoo->ncc_dirty[1] = 1;
}
break;
case SST_nccTable0_Y3:
if (chip & CHIP_TREX0) {
voodoo->nccTable[0][0].y[3] = val;
voodoo->ncc_dirty[0] = 1;
}
if (chip & CHIP_TREX1) {
voodoo->nccTable[1][0].y[3] = val;
voodoo->ncc_dirty[1] = 1;
}
break;
case SST_nccTable0_I0:
if (!(val & (1 << 31))) {
if (chip & CHIP_TREX0) {
voodoo->nccTable[0][0].i[0] = val;
voodoo->ncc_dirty[0] = 1;
}
if (chip & CHIP_TREX1) {
voodoo->nccTable[1][0].i[0] = val;
voodoo->ncc_dirty[1] = 1;
}
break;
}
fallthrough;
case SST_nccTable0_I2:
if (!(val & (1 << 31))) {
if (chip & CHIP_TREX0) {
voodoo->nccTable[0][0].i[2] = val;
voodoo->ncc_dirty[0] = 1;
}
if (chip & CHIP_TREX1) {
voodoo->nccTable[1][0].i[2] = val;
voodoo->ncc_dirty[1] = 1;
}
break;
}
case SST_nccTable0_Q0:
if (!(val & (1 << 31))) {
if (chip & CHIP_TREX0) {
voodoo->nccTable[0][0].q[0] = val;
voodoo->ncc_dirty[0] = 1;
}
if (chip & CHIP_TREX1) {
voodoo->nccTable[1][0].q[0] = val;
voodoo->ncc_dirty[1] = 1;
}
break;
}
case SST_nccTable0_Q2:
if (!(val & (1 << 31))) {
if (chip & CHIP_TREX0) {
voodoo->nccTable[0][0].i[2] = val;
voodoo->ncc_dirty[0] = 1;
}
if (chip & CHIP_TREX1) {
voodoo->nccTable[1][0].i[2] = val;
voodoo->ncc_dirty[1] = 1;
}
break;
}
if (val & (1 << 31)) {
int p = (val >> 23) & 0xfe;
if (chip & CHIP_TREX0) {
voodoo->palette[0][p].u = val | 0xff000000;
voodoo->palette_dirty[0] = 1;
}
if (chip & CHIP_TREX1) {
voodoo->palette[1][p].u = val | 0xff000000;
voodoo->palette_dirty[1] = 1;
}
}
break;
case SST_nccTable0_I1:
if (!(val & (1 << 31))) {
if (chip & CHIP_TREX0) {
voodoo->nccTable[0][0].i[1] = val;
voodoo->ncc_dirty[0] = 1;
}
if (chip & CHIP_TREX1) {
voodoo->nccTable[1][0].i[1] = val;
voodoo->ncc_dirty[1] = 1;
}
break;
}
case SST_nccTable0_I3:
if (!(val & (1 << 31))) {
if (chip & CHIP_TREX0) {
voodoo->nccTable[0][0].i[3] = val;
voodoo->ncc_dirty[0] = 1;
}
if (chip & CHIP_TREX1) {
voodoo->nccTable[1][0].i[3] = val;
voodoo->ncc_dirty[1] = 1;
}
break;
}
case SST_nccTable0_Q1:
if (!(val & (1 << 31))) {
if (chip & CHIP_TREX0) {
voodoo->nccTable[0][0].q[1] = val;
voodoo->ncc_dirty[0] = 1;
}
if (chip & CHIP_TREX1) {
voodoo->nccTable[1][0].q[1] = val;
voodoo->ncc_dirty[1] = 1;
}
break;
}
case SST_nccTable0_Q3:
if (!(val & (1 << 31))) {
if (chip & CHIP_TREX0) {
voodoo->nccTable[0][0].q[3] = val;
voodoo->ncc_dirty[0] = 1;
}
if (chip & CHIP_TREX1) {
voodoo->nccTable[1][0].q[3] = val;
voodoo->ncc_dirty[1] = 1;
}
break;
}
if (val & (1 << 31)) {
int p = ((val >> 23) & 0xfe) | 0x01;
if (chip & CHIP_TREX0) {
voodoo->palette[0][p].u = val | 0xff000000;
voodoo->palette_dirty[0] = 1;
}
if (chip & CHIP_TREX1) {
voodoo->palette[1][p].u = val | 0xff000000;
voodoo->palette_dirty[1] = 1;
}
}
break;
case SST_nccTable1_Y0:
if (chip & CHIP_TREX0) {
voodoo->nccTable[0][1].y[0] = val;
voodoo->ncc_dirty[0] = 1;
}
if (chip & CHIP_TREX1) {
voodoo->nccTable[1][1].y[0] = val;
voodoo->ncc_dirty[1] = 1;
}
break;
case SST_nccTable1_Y1:
if (chip & CHIP_TREX0) {
voodoo->nccTable[0][1].y[1] = val;
voodoo->ncc_dirty[0] = 1;
}
if (chip & CHIP_TREX1) {
voodoo->nccTable[1][1].y[1] = val;
voodoo->ncc_dirty[1] = 1;
}
break;
case SST_nccTable1_Y2:
if (chip & CHIP_TREX0) {
voodoo->nccTable[0][1].y[2] = val;
voodoo->ncc_dirty[0] = 1;
}
if (chip & CHIP_TREX1) {
voodoo->nccTable[1][1].y[2] = val;
voodoo->ncc_dirty[1] = 1;
}
break;
case SST_nccTable1_Y3:
if (chip & CHIP_TREX0) {
voodoo->nccTable[0][1].y[3] = val;
voodoo->ncc_dirty[0] = 1;
}
if (chip & CHIP_TREX1) {
voodoo->nccTable[1][1].y[3] = val;
voodoo->ncc_dirty[1] = 1;
}
break;
case SST_nccTable1_I0:
if (chip & CHIP_TREX0) {
voodoo->nccTable[0][1].i[0] = val;
voodoo->ncc_dirty[0] = 1;
}
if (chip & CHIP_TREX1) {
voodoo->nccTable[1][1].i[0] = val;
voodoo->ncc_dirty[1] = 1;
}
break;
case SST_nccTable1_I1:
if (chip & CHIP_TREX0) {
voodoo->nccTable[0][1].i[1] = val;
voodoo->ncc_dirty[0] = 1;
}
if (chip & CHIP_TREX1) {
voodoo->nccTable[1][1].i[1] = val;
voodoo->ncc_dirty[1] = 1;
}
break;
case SST_nccTable1_I2:
if (chip & CHIP_TREX0) {
voodoo->nccTable[0][1].i[2] = val;
voodoo->ncc_dirty[0] = 1;
}
if (chip & CHIP_TREX1) {
voodoo->nccTable[1][1].i[2] = val;
voodoo->ncc_dirty[1] = 1;
}
break;
case SST_nccTable1_I3:
if (chip & CHIP_TREX0) {
voodoo->nccTable[0][1].i[3] = val;
voodoo->ncc_dirty[0] = 1;
}
if (chip & CHIP_TREX1) {
voodoo->nccTable[1][1].i[3] = val;
voodoo->ncc_dirty[1] = 1;
}
break;
case SST_nccTable1_Q0:
if (chip & CHIP_TREX0) {
voodoo->nccTable[0][1].q[0] = val;
voodoo->ncc_dirty[0] = 1;
}
if (chip & CHIP_TREX1) {
voodoo->nccTable[1][1].q[0] = val;
voodoo->ncc_dirty[1] = 1;
}
break;
case SST_nccTable1_Q1:
if (chip & CHIP_TREX0) {
voodoo->nccTable[0][1].q[1] = val;
voodoo->ncc_dirty[0] = 1;
}
if (chip & CHIP_TREX1) {
voodoo->nccTable[1][1].q[1] = val;
voodoo->ncc_dirty[1] = 1;
}
break;
case SST_nccTable1_Q2:
if (chip & CHIP_TREX0) {
voodoo->nccTable[0][1].q[2] = val;
voodoo->ncc_dirty[0] = 1;
}
if (chip & CHIP_TREX1) {
voodoo->nccTable[1][1].q[2] = val;
voodoo->ncc_dirty[1] = 1;
}
break;
case SST_nccTable1_Q3:
if (chip & CHIP_TREX0) {
voodoo->nccTable[0][1].q[3] = val;
voodoo->ncc_dirty[0] = 1;
}
if (chip & CHIP_TREX1) {
voodoo->nccTable[1][1].q[3] = val;
voodoo->ncc_dirty[1] = 1;
}
break;
case SST_userIntrCMD:
fatal("userIntrCMD write %08x from FIFO\n", val);
break;
case SST_leftOverlayBuf:
voodoo->leftOverlayBuf = val;
break;
default:
break;
}
}
``` | /content/code_sandbox/src/video/vid_voodoo_reg.c | c | 2016-06-25T22:29:10 | 2024-08-16T19:09:21 | 86Box | 86Box/86Box | 2,616 | 14,866 |
```c
/*
* 86Box A hypervisor and IBM PC system emulator that specializes in
* running old operating systems and software designed for IBM
* PC systems and compatibles from 1981 through fairly recent
* system designs based on the PCI bus.
*
* This file is part of the 86Box distribution.
*
* 3DFX Voodoo emulation.
*
*
*
* Authors: Sarah Walker, <path_to_url
*
*/
#include <stdarg.h>
#include <stdio.h>
#include <stdint.h>
#include <string.h>
#include <stdlib.h>
#include <stddef.h>
#include <wchar.h>
#include <math.h>
#define HAVE_STDARG_H
#include <86box/86box.h>
#include "cpu.h"
#include <86box/machine.h>
#include <86box/device.h>
#include <86box/mem.h>
#include <86box/timer.h>
#include <86box/device.h>
#include <86box/plat.h>
#include <86box/thread.h>
#include <86box/video.h>
#include <86box/vid_svga.h>
#include <86box/vid_voodoo_common.h>
#include <86box/vid_voodoo_dither.h>
#include <86box/vid_voodoo_regs.h>
#include <86box/vid_voodoo_render.h>
#include <86box/vid_voodoo_texture.h>
typedef struct voodoo_state_t {
int xstart, xend, xdir;
uint32_t base_r, base_g, base_b, base_a, base_z;
struct
{
int64_t base_s, base_t, base_w;
int lod;
} tmu[2];
int64_t base_w;
int lod;
int lod_min[2], lod_max[2];
int dx1, dx2;
int y, yend, ydir;
int32_t dxAB, dxAC, dxBC;
int tex_b[2], tex_g[2], tex_r[2], tex_a[2];
int tex_s, tex_t;
int clamp_s[2], clamp_t[2];
int32_t vertexAx, vertexAy, vertexBx, vertexBy, vertexCx, vertexCy;
uint32_t *tex[2][LOD_MAX + 1];
int tformat;
int *tex_w_mask[2];
int *tex_h_mask[2];
int *tex_shift[2];
int *tex_lod[2];
uint16_t *fb_mem, *aux_mem;
int32_t ib, ig, ir, ia;
int32_t z;
int32_t new_depth;
int64_t tmu0_s, tmu0_t;
int64_t tmu0_w;
int64_t tmu1_s, tmu1_t;
int64_t tmu1_w;
int64_t w;
int pixel_count, texel_count;
int x, x2, x_tiled;
uint32_t w_depth;
float log_temp;
uint32_t ebp_store;
uint32_t texBaseAddr;
int lod_frac[2];
} voodoo_state_t;
#ifdef ENABLE_VOODOO_RENDER_LOG
int voodoo_render_do_log = ENABLE_VOODOO_RENDER_LOG;
static void
voodoo_render_log(const char *fmt, ...)
{
va_list ap;
if (voodoo_render_do_log) {
va_start(ap, fmt);
pclog_ex(fmt, ap);
va_end(ap);
}
}
#else
# define voodoo_render_log(fmt, ...)
#endif
static uint8_t logtable[256] = {
0x00, 0x01, 0x02, 0x04, 0x05, 0x07, 0x08, 0x09, 0x0b, 0x0c, 0x0e, 0x0f, 0x10, 0x12, 0x13, 0x15,
0x16, 0x17, 0x19, 0x1a, 0x1b, 0x1d, 0x1e, 0x1f, 0x21, 0x22, 0x23, 0x25, 0x26, 0x27, 0x28, 0x2a,
0x2b, 0x2c, 0x2e, 0x2f, 0x30, 0x31, 0x33, 0x34, 0x35, 0x36, 0x38, 0x39, 0x3a, 0x3b, 0x3d, 0x3e,
0x3f, 0x40, 0x41, 0x43, 0x44, 0x45, 0x46, 0x47, 0x49, 0x4a, 0x4b, 0x4c, 0x4d, 0x4e, 0x50, 0x51,
0x52, 0x53, 0x54, 0x55, 0x57, 0x58, 0x59, 0x5a, 0x5b, 0x5c, 0x5d, 0x5e, 0x60, 0x61, 0x62, 0x63,
0x64, 0x65, 0x66, 0x67, 0x68, 0x69, 0x6a, 0x6c, 0x6d, 0x6e, 0x6f, 0x70, 0x71, 0x72, 0x73, 0x74,
0x75, 0x76, 0x77, 0x78, 0x79, 0x7a, 0x7b, 0x7c, 0x7d, 0x7e, 0x7f, 0x80, 0x81, 0x83, 0x84, 0x85,
0x86, 0x87, 0x88, 0x89, 0x8a, 0x8b, 0x8c, 0x8c, 0x8d, 0x8e, 0x8f, 0x90, 0x91, 0x92, 0x93, 0x94,
0x95, 0x96, 0x97, 0x98, 0x99, 0x9a, 0x9b, 0x9c, 0x9d, 0x9e, 0x9f, 0xa0, 0xa1, 0xa2, 0xa2, 0xa3,
0xa4, 0xa5, 0xa6, 0xa7, 0xa8, 0xa9, 0xaa, 0xab, 0xac, 0xad, 0xad, 0xae, 0xaf, 0xb0, 0xb1, 0xb2,
0xb3, 0xb4, 0xb5, 0xb5, 0xb6, 0xb7, 0xb8, 0xb9, 0xba, 0xbb, 0xbc, 0xbc, 0xbd, 0xbe, 0xbf, 0xc0,
0xc1, 0xc2, 0xc2, 0xc3, 0xc4, 0xc5, 0xc6, 0xc7, 0xc8, 0xc8, 0xc9, 0xca, 0xcb, 0xcc, 0xcd, 0xcd,
0xce, 0xcf, 0xd0, 0xd1, 0xd1, 0xd2, 0xd3, 0xd4, 0xd5, 0xd6, 0xd6, 0xd7, 0xd8, 0xd9, 0xda, 0xda,
0xdb, 0xdc, 0xdd, 0xde, 0xde, 0xdf, 0xe0, 0xe1, 0xe1, 0xe2, 0xe3, 0xe4, 0xe5, 0xe5, 0xe6, 0xe7,
0xe8, 0xe8, 0xe9, 0xea, 0xeb, 0xeb, 0xec, 0xed, 0xee, 0xef, 0xef, 0xf0, 0xf1, 0xf2, 0xf2, 0xf3,
0xf4, 0xf5, 0xf5, 0xf6, 0xf7, 0xf7, 0xf8, 0xf9, 0xfa, 0xfa, 0xfb, 0xfc, 0xfd, 0xfd, 0xfe, 0xff
};
static __inline int
fastlog(uint64_t val)
{
uint64_t oldval = val;
int exp = 63;
int frac;
if (!val || val & (1ULL << 63))
return 0x80000000;
if (!(val & 0xffffffff00000000)) {
exp -= 32;
val <<= 32;
}
if (!(val & 0xffff000000000000)) {
exp -= 16;
val <<= 16;
}
if (!(val & 0xff00000000000000)) {
exp -= 8;
val <<= 8;
}
if (!(val & 0xf000000000000000)) {
exp -= 4;
val <<= 4;
}
if (!(val & 0xc000000000000000)) {
exp -= 2;
val <<= 2;
}
if (!(val & 0x8000000000000000)) {
exp -= 1;
val <<= 1;
}
if (exp >= 8)
frac = (oldval >> (exp - 8)) & 0xff;
else
frac = (oldval << (8 - exp)) & 0xff;
return (exp << 8) | logtable[frac];
}
static inline int
voodoo_fls(uint16_t val)
{
int num = 0;
#if 0
voodoo_render_log("fls(%04x) = ", val);
#endif
if (!(val & 0xff00)) {
num += 8;
val <<= 8;
}
if (!(val & 0xf000)) {
num += 4;
val <<= 4;
}
if (!(val & 0xc000)) {
num += 2;
val <<= 2;
}
if (!(val & 0x8000)) {
num += 1;
val <<= 1;
}
#if 0
voodoo_render_log("%i %04x\n", num, val);
#endif
return num;
}
typedef struct voodoo_texture_state_t {
int s, t;
int w_mask, h_mask;
int tex_shift;
} voodoo_texture_state_t;
static inline void
tex_read(voodoo_state_t *state, voodoo_texture_state_t *texture_state, int tmu)
{
uint32_t dat;
if (texture_state->s & ~texture_state->w_mask) {
if (state->clamp_s[tmu]) {
if (texture_state->s < 0)
texture_state->s = 0;
if (texture_state->s > texture_state->w_mask)
texture_state->s = texture_state->w_mask;
} else
texture_state->s &= texture_state->w_mask;
}
if (texture_state->t & ~texture_state->h_mask) {
if (state->clamp_t[tmu]) {
if (texture_state->t < 0)
texture_state->t = 0;
if (texture_state->t > texture_state->h_mask)
texture_state->t = texture_state->h_mask;
} else
texture_state->t &= texture_state->h_mask;
}
dat = state->tex[tmu][state->lod][texture_state->s + (texture_state->t << texture_state->tex_shift)];
state->tex_b[tmu] = dat & 0xff;
state->tex_g[tmu] = (dat >> 8) & 0xff;
state->tex_r[tmu] = (dat >> 16) & 0xff;
state->tex_a[tmu] = (dat >> 24) & 0xff;
}
#define LOW4(x) ((x & 0x0f) | ((x & 0x0f) << 4))
#define HIGH4(x) ((x & 0xf0) | ((x & 0xf0) >> 4))
static inline void
tex_read_4(voodoo_state_t *state, voodoo_texture_state_t *texture_state, int s, int t, int *d, int tmu, UNUSED(int x))
{
rgba_u dat[4];
if (((s | (s + 1)) & ~texture_state->w_mask) || ((t | (t + 1)) & ~texture_state->h_mask)) {
for (uint8_t c = 0; c < 4; c++) {
int _s = s + (c & 1);
int _t = t + ((c & 2) >> 1);
if (_s & ~texture_state->w_mask) {
if (state->clamp_s[tmu]) {
if (_s < 0)
_s = 0;
if (_s > texture_state->w_mask)
_s = texture_state->w_mask;
} else
_s &= texture_state->w_mask;
}
if (_t & ~texture_state->h_mask) {
if (state->clamp_t[tmu]) {
if (_t < 0)
_t = 0;
if (_t > texture_state->h_mask)
_t = texture_state->h_mask;
} else
_t &= texture_state->h_mask;
}
dat[c].u = state->tex[tmu][state->lod][_s + (_t << texture_state->tex_shift)];
}
} else {
dat[0].u = state->tex[tmu][state->lod][s + (t << texture_state->tex_shift)];
dat[1].u = state->tex[tmu][state->lod][s + 1 + (t << texture_state->tex_shift)];
dat[2].u = state->tex[tmu][state->lod][s + ((t + 1) << texture_state->tex_shift)];
dat[3].u = state->tex[tmu][state->lod][s + 1 + ((t + 1) << texture_state->tex_shift)];
}
state->tex_r[tmu] = (dat[0].rgba.r * d[0] + dat[1].rgba.r * d[1] + dat[2].rgba.r * d[2] + dat[3].rgba.r * d[3]) >> 8;
state->tex_g[tmu] = (dat[0].rgba.g * d[0] + dat[1].rgba.g * d[1] + dat[2].rgba.g * d[2] + dat[3].rgba.g * d[3]) >> 8;
state->tex_b[tmu] = (dat[0].rgba.b * d[0] + dat[1].rgba.b * d[1] + dat[2].rgba.b * d[2] + dat[3].rgba.b * d[3]) >> 8;
state->tex_a[tmu] = (dat[0].rgba.a * d[0] + dat[1].rgba.a * d[1] + dat[2].rgba.a * d[2] + dat[3].rgba.a * d[3]) >> 8;
}
static inline void
voodoo_get_texture(voodoo_t *voodoo, voodoo_params_t *params, voodoo_state_t *state, int tmu, int x)
{
voodoo_texture_state_t texture_state;
int d[4];
int s;
int t;
int tex_lod = state->tex_lod[tmu][state->lod];
texture_state.w_mask = state->tex_w_mask[tmu][state->lod];
texture_state.h_mask = state->tex_h_mask[tmu][state->lod];
texture_state.tex_shift = 8 - tex_lod;
if (params->tLOD[tmu] & LOD_TMIRROR_S) {
if (state->tex_s & 0x1000)
state->tex_s = ~state->tex_s;
}
if (params->tLOD[tmu] & LOD_TMIRROR_T) {
if (state->tex_t & 0x1000)
state->tex_t = ~state->tex_t;
}
if (voodoo->bilinear_enabled && params->textureMode[tmu] & 6) {
int _ds;
int dt;
state->tex_s -= 1 << (3 + tex_lod);
state->tex_t -= 1 << (3 + tex_lod);
s = state->tex_s >> tex_lod;
t = state->tex_t >> tex_lod;
_ds = s & 0xf;
dt = t & 0xf;
s >>= 4;
t >>= 4;
#if 0
if (x == 80)
if (voodoo_output)
voodoo_render_log("s=%08x t=%08x _ds=%02x _dt=%02x\n", s, t, _ds, dt);
#endif
d[0] = (16 - _ds) * (16 - dt);
d[1] = _ds * (16 - dt);
d[2] = (16 - _ds) * dt;
d[3] = _ds * dt;
#if 0
texture_state.s = s;
texture_state.t = t;
#endif
tex_read_4(state, &texture_state, s, t, d, tmu, x);
#if 0
state->tex_r = (tex_samples[0].rgba.r * d[0] + tex_samples[1].rgba.r * d[1] + tex_samples[2].rgba.r * d[2] + tex_samples[3].rgba.r * d[3]) >> 8;
state->tex_g = (tex_samples[0].rgba.g * d[0] + tex_samples[1].rgba.g * d[1] + tex_samples[2].rgba.g * d[2] + tex_samples[3].rgba.g * d[3]) >> 8;
state->tex_b = (tex_samples[0].rgba.b * d[0] + tex_samples[1].rgba.b * d[1] + tex_samples[2].rgba.b * d[2] + tex_samples[3].rgba.b * d[3]) >> 8;
state->tex_a = (tex_samples[0].rgba.a * d[0] + tex_samples[1].rgba.a * d[1] + tex_samples[2].rgba.a * d[2] + tex_samples[3].rgba.a * d[3]) >> 8;*/
#endif
#if 0
state->tex_r = tex_samples[0].r;
state->tex_g = tex_samples[0].g;
state->tex_b = tex_samples[0].b;
state->tex_a = tex_samples[0].a;
#endif
} else {
#if 0
rgba_t tex_samples;
voodoo_texture_state_t texture_state;
int s = state->tex_s >> (18+state->lod);
int t = state->tex_t >> (18+state->lod);
state->tex_s -= 1 << (17+state->lod);
state->tex_t -= 1 << (17+state->lod);
#endif
s = state->tex_s >> (4 + tex_lod);
t = state->tex_t >> (4 + tex_lod);
texture_state.s = s;
texture_state.t = t;
tex_read(state, &texture_state, tmu);
#if 0
state->tex_r = tex_samples[0].rgba.r;
state->tex_g = tex_samples[0].rgba.g;
state->tex_b = tex_samples[0].rgba.b;
state->tex_a = tex_samples[0].rgba.a;
#endif
}
}
static inline void
voodoo_tmu_fetch(voodoo_t *voodoo, voodoo_params_t *params, voodoo_state_t *state, int tmu, int x)
{
if (params->textureMode[tmu] & 1) {
int64_t _w = 0;
if (tmu) {
if (state->tmu1_w)
_w = (int64_t) ((1ULL << 48) / state->tmu1_w);
state->tex_s = (int32_t) (((((state->tmu1_s + (1 << 13)) >> 14) * _w) + (1 << 29)) >> 30);
state->tex_t = (int32_t) (((((state->tmu1_t + (1 << 13)) >> 14) * _w) + (1 << 29)) >> 30);
} else {
if (state->tmu0_w)
_w = (int64_t) ((1ULL << 48) / state->tmu0_w);
state->tex_s = (int32_t) (((((state->tmu0_s + (1 << 13)) >> 14) * _w) + (1 << 29)) >> 30);
state->tex_t = (int32_t) (((((state->tmu0_t + (1 << 13)) >> 14) * _w) + (1 << 29)) >> 30);
}
state->lod = state->tmu[tmu].lod + (fastlog(_w) - (19 << 8));
} else {
if (tmu) {
state->tex_s = (int32_t) (state->tmu1_s >> (14 + 14));
state->tex_t = (int32_t) (state->tmu1_t >> (14 + 14));
} else {
state->tex_s = (int32_t) (state->tmu0_s >> (14 + 14));
state->tex_t = (int32_t) (state->tmu0_t >> (14 + 14));
}
state->lod = state->tmu[tmu].lod;
}
if (state->lod < state->lod_min[tmu])
state->lod = state->lod_min[tmu];
else if (state->lod > state->lod_max[tmu])
state->lod = state->lod_max[tmu];
state->lod_frac[tmu] = state->lod & 0xff;
state->lod >>= 8;
voodoo_get_texture(voodoo, params, state, tmu, x);
}
/*Perform texture fetch and blending for both TMUs*/
static inline void
voodoo_tmu_fetch_and_blend(voodoo_t *voodoo, voodoo_params_t *params, voodoo_state_t *state, int x)
{
int r;
int g;
int b;
int a;
int c_reverse;
int a_reverse;
#if 0
int c_reverse1;
int a_reverse1;
#endif
int factor_r = 0;
int factor_g = 0;
int factor_b = 0;
int factor_a = 0;
voodoo_tmu_fetch(voodoo, params, state, 1, x);
if ((params->textureMode[1] & TEXTUREMODE_TRILINEAR) && (state->lod & 1)) {
c_reverse = tc_reverse_blend;
a_reverse = tca_reverse_blend;
} else {
c_reverse = !tc_reverse_blend;
a_reverse = !tca_reverse_blend;
}
#if 0
c_reverse1 = c_reverse;
a_reverse1 = a_reverse;
#endif
if (tc_sub_clocal_1) {
switch (tc_mselect_1) {
case TC_MSELECT_ZERO:
factor_r = factor_g = factor_b = 0;
break;
case TC_MSELECT_CLOCAL:
factor_r = state->tex_r[1];
factor_g = state->tex_g[1];
factor_b = state->tex_b[1];
break;
case TC_MSELECT_AOTHER:
factor_r = factor_g = factor_b = 0;
break;
case TC_MSELECT_ALOCAL:
factor_r = factor_g = factor_b = state->tex_a[1];
break;
case TC_MSELECT_DETAIL:
factor_r = (params->detail_bias[1] - state->lod) << params->detail_scale[1];
if (factor_r > params->detail_max[1])
factor_r = params->detail_max[1];
factor_g = factor_b = factor_r;
break;
case TC_MSELECT_LOD_FRAC:
factor_r = factor_g = factor_b = state->lod_frac[1];
break;
default:
break;
}
if (!c_reverse) {
r = (-state->tex_r[1] * (factor_r + 1)) >> 8;
g = (-state->tex_g[1] * (factor_g + 1)) >> 8;
b = (-state->tex_b[1] * (factor_b + 1)) >> 8;
} else {
r = (-state->tex_r[1] * ((factor_r ^ 0xff) + 1)) >> 8;
g = (-state->tex_g[1] * ((factor_g ^ 0xff) + 1)) >> 8;
b = (-state->tex_b[1] * ((factor_b ^ 0xff) + 1)) >> 8;
}
if (tc_add_clocal_1) {
r += state->tex_r[1];
g += state->tex_g[1];
b += state->tex_b[1];
} else if (tc_add_alocal_1) {
r += state->tex_a[1];
g += state->tex_a[1];
b += state->tex_a[1];
}
state->tex_r[1] = CLAMP(r);
state->tex_g[1] = CLAMP(g);
state->tex_b[1] = CLAMP(b);
}
if (tca_sub_clocal_1) {
switch (tca_mselect_1) {
case TCA_MSELECT_ZERO:
factor_a = 0;
break;
case TCA_MSELECT_CLOCAL:
factor_a = state->tex_a[1];
break;
case TCA_MSELECT_AOTHER:
factor_a = 0;
break;
case TCA_MSELECT_ALOCAL:
factor_a = state->tex_a[1];
break;
case TCA_MSELECT_DETAIL:
factor_a = (params->detail_bias[1] - state->lod) << params->detail_scale[1];
if (factor_a > params->detail_max[1])
factor_a = params->detail_max[1];
break;
case TCA_MSELECT_LOD_FRAC:
factor_a = state->lod_frac[1];
break;
default:
break;
}
if (!a_reverse)
a = (-state->tex_a[1] * ((factor_a ^ 0xff) + 1)) >> 8;
else
a = (-state->tex_a[1] * (factor_a + 1)) >> 8;
if (tca_add_clocal_1 || tca_add_alocal_1)
a += state->tex_a[1];
state->tex_a[1] = CLAMP(a);
}
voodoo_tmu_fetch(voodoo, params, state, 0, x);
if ((params->textureMode[0] & TEXTUREMODE_TRILINEAR) && (state->lod & 1)) {
c_reverse = tc_reverse_blend;
a_reverse = tca_reverse_blend;
} else {
c_reverse = !tc_reverse_blend;
a_reverse = !tca_reverse_blend;
}
if (!tc_zero_other) {
r = state->tex_r[1];
g = state->tex_g[1];
b = state->tex_b[1];
} else
r = g = b = 0;
if (tc_sub_clocal) {
r -= state->tex_r[0];
g -= state->tex_g[0];
b -= state->tex_b[0];
}
switch (tc_mselect) {
case TC_MSELECT_ZERO:
factor_r = factor_g = factor_b = 0;
break;
case TC_MSELECT_CLOCAL:
factor_r = state->tex_r[0];
factor_g = state->tex_g[0];
factor_b = state->tex_b[0];
break;
case TC_MSELECT_AOTHER:
factor_r = factor_g = factor_b = state->tex_a[1];
break;
case TC_MSELECT_ALOCAL:
factor_r = factor_g = factor_b = state->tex_a[0];
break;
case TC_MSELECT_DETAIL:
factor_r = (params->detail_bias[0] - state->lod) << params->detail_scale[0];
if (factor_r > params->detail_max[0])
factor_r = params->detail_max[0];
factor_g = factor_b = factor_r;
break;
case TC_MSELECT_LOD_FRAC:
factor_r = factor_g = factor_b = state->lod_frac[0];
break;
default:
break;
}
if (!c_reverse) {
r = (r * (factor_r + 1)) >> 8;
g = (g * (factor_g + 1)) >> 8;
b = (b * (factor_b + 1)) >> 8;
} else {
r = (r * ((factor_r ^ 0xff) + 1)) >> 8;
g = (g * ((factor_g ^ 0xff) + 1)) >> 8;
b = (b * ((factor_b ^ 0xff) + 1)) >> 8;
}
if (tc_add_clocal) {
r += state->tex_r[0];
g += state->tex_g[0];
b += state->tex_b[0];
} else if (tc_add_alocal) {
r += state->tex_a[0];
g += state->tex_a[0];
b += state->tex_a[0];
}
if (!tca_zero_other)
a = state->tex_a[1];
else
a = 0;
if (tca_sub_clocal)
a -= state->tex_a[0];
switch (tca_mselect) {
case TCA_MSELECT_ZERO:
factor_a = 0;
break;
case TCA_MSELECT_CLOCAL:
factor_a = state->tex_a[0];
break;
case TCA_MSELECT_AOTHER:
factor_a = state->tex_a[1];
break;
case TCA_MSELECT_ALOCAL:
factor_a = state->tex_a[0];
break;
case TCA_MSELECT_DETAIL:
factor_a = (params->detail_bias[0] - state->lod) << params->detail_scale[0];
if (factor_a > params->detail_max[0])
factor_a = params->detail_max[0];
break;
case TCA_MSELECT_LOD_FRAC:
factor_a = state->lod_frac[0];
break;
default:
break;
}
if (a_reverse)
a = (a * ((factor_a ^ 0xff) + 1)) >> 8;
else
a = (a * (factor_a + 1)) >> 8;
if (tca_add_clocal || tca_add_alocal)
a += state->tex_a[0];
state->tex_r[0] = CLAMP(r);
state->tex_g[0] = CLAMP(g);
state->tex_b[0] = CLAMP(b);
state->tex_a[0] = CLAMP(a);
if (tc_invert_output) {
state->tex_r[0] ^= 0xff;
state->tex_g[0] ^= 0xff;
state->tex_b[0] ^= 0xff;
}
if (tca_invert_output)
state->tex_a[0] ^= 0xff;
}
#if (defined i386 || defined __i386 || defined __i386__ || defined _X86_ || defined _M_IX86) && !(defined __amd64__ || defined _M_X64)
# include <86box/vid_voodoo_codegen_x86.h>
#elif (defined __amd64__ || defined _M_X64)
# include <86box/vid_voodoo_codegen_x86-64.h>
#else
int voodoo_recomp = 0;
#endif
static void
voodoo_half_triangle(voodoo_t *voodoo, voodoo_params_t *params, voodoo_state_t *state, int ystart, int yend, int odd_even)
{
#if 0
int rgb_sel = params->fbzColorPath & 3;
int a_sel = (params->fbzColorPath >> 2) & 3;
int cc_localselect = params->fbzColorPath & (1 << 4);
int cca_localselect = (params->fbzColorPath >> 5) & 3;
int cc_localselect_override = params->fbzColorPath & (1 << 7);
int cc_zero_other = params->fbzColorPath & (1 << 8);
int cc_sub_clocal = params->fbzColorPath & (1 << 9);
int cc_mselect = (params->fbzColorPath >> 10) & 7;
int cc_reverse_blend = params->fbzColorPath & (1 << 13);
int cc_add = (params->fbzColorPath >> 14) & 3;
int cc_add_alocal = params->fbzColorPath & (1 << 15);
int cc_invert_output = params->fbzColorPath & (1 << 16);
int cca_zero_other = params->fbzColorPath & (1 << 17);
int cca_sub_clocal = params->fbzColorPath & (1 << 18);
int cca_mselect = (params->fbzColorPath >> 19) & 7;
int cca_reverse_blend = params->fbzColorPath & (1 << 22);
int cca_add = (params->fbzColorPath >> 23) & 3;
int cca_invert_output = params->fbzColorPath & (1 << 25);
int src_afunc = (params->alphaMode >> 8) & 0xf;
int dest_afunc = (params->alphaMode >> 12) & 0xf;
int alpha_func = (params->alphaMode >> 1) & 7;
int a_ref = params->alphaMode >> 24;
int depth_op = (params->fbzMode >> 5) & 7;
int dither = params->fbzMode & FBZ_DITHER;*/
#endif
int texels;
#ifndef NO_CODEGEN
uint8_t (*voodoo_draw)(voodoo_state_t * state, voodoo_params_t * params, int x, int real_y);
#endif
int y_diff = SLI_ENABLED ? 2 : 1;
int y_origin = (voodoo->type >= VOODOO_BANSHEE) ? voodoo->y_origin_swap : (voodoo->v_disp - 1);
if ((params->textureMode[0] & TEXTUREMODE_MASK) == TEXTUREMODE_PASSTHROUGH || (params->textureMode[0] & TEXTUREMODE_LOCAL_MASK) == TEXTUREMODE_LOCAL)
texels = 1;
else
texels = 2;
state->clamp_s[0] = params->textureMode[0] & TEXTUREMODE_TCLAMPS;
state->clamp_t[0] = params->textureMode[0] & TEXTUREMODE_TCLAMPT;
state->clamp_s[1] = params->textureMode[1] & TEXTUREMODE_TCLAMPS;
state->clamp_t[1] = params->textureMode[1] & TEXTUREMODE_TCLAMPT;
// int last_x;
// voodoo_render_log("voodoo_triangle : bottom-half %X %X %X %X %X %i %i %i %i\n", xstart, xend, dx1, dx2, dx2 * 36, xdir, y, yend, ydir);
for (uint8_t c = 0; c <= LOD_MAX; c++) {
state->tex[0][c] = &voodoo->texture_cache[0][params->tex_entry[0]].data[texture_offset[c]];
state->tex[1][c] = &voodoo->texture_cache[1][params->tex_entry[1]].data[texture_offset[c]];
}
state->tformat = params->tformat[0];
state->tex_w_mask[0] = params->tex_w_mask[0];
state->tex_h_mask[0] = params->tex_h_mask[0];
state->tex_shift[0] = params->tex_shift[0];
state->tex_lod[0] = params->tex_lod[0];
state->tex_w_mask[1] = params->tex_w_mask[1];
state->tex_h_mask[1] = params->tex_h_mask[1];
state->tex_shift[1] = params->tex_shift[1];
state->tex_lod[1] = params->tex_lod[1];
if ((params->fbzMode & 1) && (ystart < params->clipLowY)) {
int dy = params->clipLowY - ystart;
state->base_r += params->dRdY * dy;
state->base_g += params->dGdY * dy;
state->base_b += params->dBdY * dy;
state->base_a += params->dAdY * dy;
state->base_z += params->dZdY * dy;
state->tmu[0].base_s += params->tmu[0].dSdY * dy;
state->tmu[0].base_t += params->tmu[0].dTdY * dy;
state->tmu[0].base_w += params->tmu[0].dWdY * dy;
state->tmu[1].base_s += params->tmu[1].dSdY * dy;
state->tmu[1].base_t += params->tmu[1].dTdY * dy;
state->tmu[1].base_w += params->tmu[1].dWdY * dy;
state->base_w += params->dWdY * dy;
state->xstart += state->dx1 * dy;
state->xend += state->dx2 * dy;
ystart = params->clipLowY;
}
if ((params->fbzMode & 1) && (yend >= params->clipHighY))
yend = params->clipHighY;
state->y = ystart;
#if 0
yend--;
#endif
if (SLI_ENABLED) {
int test_y;
if (params->fbzMode & (1 << 17))
test_y = y_origin - state->y;
else
test_y = state->y;
if ((!(voodoo->initEnable & INITENABLE_SLI_MASTER_SLAVE) && (test_y & 1)) || ((voodoo->initEnable & INITENABLE_SLI_MASTER_SLAVE) && !(test_y & 1))) {
state->y++;
state->base_r += params->dRdY;
state->base_g += params->dGdY;
state->base_b += params->dBdY;
state->base_a += params->dAdY;
state->base_z += params->dZdY;
state->tmu[0].base_s += params->tmu[0].dSdY;
state->tmu[0].base_t += params->tmu[0].dTdY;
state->tmu[0].base_w += params->tmu[0].dWdY;
state->tmu[1].base_s += params->tmu[1].dSdY;
state->tmu[1].base_t += params->tmu[1].dTdY;
state->tmu[1].base_w += params->tmu[1].dWdY;
state->base_w += params->dWdY;
state->xstart += state->dx1;
state->xend += state->dx2;
}
}
#ifndef NO_CODEGEN
if (voodoo->use_recompiler)
voodoo_draw = voodoo_get_block(voodoo, params, state, odd_even);
else
voodoo_draw = NULL;
#endif
voodoo_render_log("dxAB=%08x dxBC=%08x dxAC=%08x\n", state->dxAB, state->dxBC, state->dxAC);
#if 0
voodoo_render_log("Start %i %i\n", ystart, voodoo->fbzMode & (1 << 17));
#endif
for (; state->y < yend; state->y += y_diff) {
int x;
int x2;
int real_y = (state->y << 4) + 8;
int start_x;
int dx;
uint16_t *fb_mem;
uint16_t *aux_mem;
state->ir = state->base_r;
state->ig = state->base_g;
state->ib = state->base_b;
state->ia = state->base_a;
state->z = state->base_z;
state->tmu0_s = state->tmu[0].base_s;
state->tmu0_t = state->tmu[0].base_t;
state->tmu0_w = state->tmu[0].base_w;
state->tmu1_s = state->tmu[1].base_s;
state->tmu1_t = state->tmu[1].base_t;
state->tmu1_w = state->tmu[1].base_w;
state->w = state->base_w;
x = (state->vertexAx << 12) + ((state->dxAC * (real_y - state->vertexAy)) >> 4);
if (real_y < state->vertexBy)
x2 = (state->vertexAx << 12) + ((state->dxAB * (real_y - state->vertexAy)) >> 4);
else
x2 = (state->vertexBx << 12) + ((state->dxBC * (real_y - state->vertexBy)) >> 4);
if (params->fbzMode & (1 << 17))
real_y = y_origin - (real_y >> 4);
else
real_y >>= 4;
if (SLI_ENABLED) {
if (((real_y >> 1) & voodoo->odd_even_mask) != odd_even)
goto next_line;
} else {
if ((real_y & voodoo->odd_even_mask) != odd_even)
goto next_line;
}
start_x = x;
if (state->xdir > 0)
x2 -= (1 << 16);
else
x -= (1 << 16);
dx = ((x + 0x7000) >> 16) - (((state->vertexAx << 12) + 0x7000) >> 16);
x = (x + 0x7000) >> 16;
x2 = (x2 + 0x7000) >> 16;
voodoo_render_log("%03i:%03i : Ax=%08x start_x=%08x dSdX=%016llx dx=%08x s=%08x -> ", x, state->y, state->vertexAx << 8, start_x, params->tmu[0].dTdX, dx, state->tmu0_t);
state->ir += (params->dRdX * dx);
state->ig += (params->dGdX * dx);
state->ib += (params->dBdX * dx);
state->ia += (params->dAdX * dx);
state->z += (params->dZdX * dx);
state->tmu0_s += (params->tmu[0].dSdX * dx);
state->tmu0_t += (params->tmu[0].dTdX * dx);
state->tmu0_w += (params->tmu[0].dWdX * dx);
state->tmu1_s += (params->tmu[1].dSdX * dx);
state->tmu1_t += (params->tmu[1].dTdX * dx);
state->tmu1_w += (params->tmu[1].dWdX * dx);
state->w += (params->dWdX * dx);
voodoo_render_log("%08llx %lli %lli\n", state->tmu0_t, state->tmu0_t >> (18 + state->lod), (state->tmu0_t + (1 << (17 + state->lod))) >> (18 + state->lod));
if (params->fbzMode & 1) {
if (state->xdir > 0) {
if (x < params->clipLeft) {
int dx = params->clipLeft - x;
state->ir += params->dRdX * dx;
state->ig += params->dGdX * dx;
state->ib += params->dBdX * dx;
state->ia += params->dAdX * dx;
state->z += params->dZdX * dx;
state->tmu0_s += params->tmu[0].dSdX * dx;
state->tmu0_t += params->tmu[0].dTdX * dx;
state->tmu0_w += params->tmu[0].dWdX * dx;
state->tmu1_s += params->tmu[1].dSdX * dx;
state->tmu1_t += params->tmu[1].dTdX * dx;
state->tmu1_w += params->tmu[1].dWdX * dx;
state->w += params->dWdX * dx;
x = params->clipLeft;
}
if (x2 >= params->clipRight)
x2 = params->clipRight - 1;
} else {
if (x >= params->clipRight) {
int dx = (params->clipRight - 1) - x;
state->ir += params->dRdX * dx;
state->ig += params->dGdX * dx;
state->ib += params->dBdX * dx;
state->ia += params->dAdX * dx;
state->z += params->dZdX * dx;
state->tmu0_s += params->tmu[0].dSdX * dx;
state->tmu0_t += params->tmu[0].dTdX * dx;
state->tmu0_w += params->tmu[0].dWdX * dx;
state->tmu1_s += params->tmu[1].dSdX * dx;
state->tmu1_t += params->tmu[1].dTdX * dx;
state->tmu1_w += params->tmu[1].dWdX * dx;
state->w += params->dWdX * dx;
x = params->clipRight - 1;
}
if (x2 < params->clipLeft)
x2 = params->clipLeft;
}
}
if (x2 < x && state->xdir > 0)
goto next_line;
if (x2 > x && state->xdir < 0)
goto next_line;
if (SLI_ENABLED) {
state->fb_mem = fb_mem = (uint16_t *) &voodoo->fb_mem[params->draw_offset + ((real_y >> 1) * params->row_width)];
state->aux_mem = aux_mem = (uint16_t *) &voodoo->fb_mem[(params->aux_offset + ((real_y >> 1) * params->row_width)) & voodoo->fb_mask];
} else {
if (params->col_tiled)
state->fb_mem = fb_mem = (uint16_t *) &voodoo->fb_mem[params->draw_offset + (real_y >> 5) * params->row_width + (real_y & 31) * 128];
else
state->fb_mem = fb_mem = (uint16_t *) &voodoo->fb_mem[params->draw_offset + (real_y * params->row_width)];
if (params->aux_tiled)
state->aux_mem = aux_mem = (uint16_t *) &voodoo->fb_mem[(params->aux_offset + (real_y >> 5) * params->aux_row_width + (real_y & 31) * 128) & voodoo->fb_mask];
else
state->aux_mem = aux_mem = (uint16_t *) &voodoo->fb_mem[(params->aux_offset + (real_y * params->row_width)) & voodoo->fb_mask];
}
voodoo_render_log("%03i: x=%08x x2=%08x xstart=%08x xend=%08x dx=%08x\n", state->y, x, x2, state->xstart, state->xend, dx);
state->pixel_count = 0;
state->texel_count = 0;
state->x = x;
state->x2 = x2;
#ifndef NO_CODEGEN
if (voodoo->use_recompiler) {
voodoo_draw(state, params, x, real_y);
} else
#endif
do {
int x_tiled = (x & 63) | ((x >> 6) * 128 * 32 / 2);
start_x = x;
state->x = x;
voodoo->pixel_count[odd_even]++;
voodoo->texel_count[odd_even] += texels;
voodoo->fbiPixelsIn++;
voodoo_render_log(" X=%03i T=%08x\n", x, state->tmu0_t);
#if 0
if (voodoo->fbzMode & FBZ_RGB_WMASK)
#endif
{
int update = 1;
uint8_t cother_r = 0;
uint8_t cother_g = 0;
uint8_t cother_b = 0;
uint8_t aother;
uint8_t clocal_r;
uint8_t clocal_g;
uint8_t clocal_b;
uint8_t alocal;
int src_r = 0;
int src_g = 0;
int src_b = 0;
int src_a = 0;
int msel_r;
int msel_g;
int msel_b;
int msel_a;
uint8_t dest_r;
uint8_t dest_g;
uint8_t dest_b;
uint8_t dest_a;
uint16_t dat;
int sel;
int32_t new_depth;
int32_t w_depth;
if (state->w & 0xffff00000000)
w_depth = 0;
else if (!(state->w & 0xffff0000))
w_depth = 0xf001;
else {
int exp = voodoo_fls((uint16_t) ((uint32_t) state->w >> 16));
int mant = (~(uint32_t) state->w >> (19 - exp)) & 0xfff;
w_depth = (exp << 12) + mant + 1;
if (w_depth > 0xffff)
w_depth = 0xffff;
}
#if 0
w_depth = CLAMP16(w_depth);
#endif
if (params->fbzMode & FBZ_W_BUFFER)
new_depth = w_depth;
else
new_depth = CLAMP16(state->z >> 12);
if (params->fbzMode & FBZ_DEPTH_BIAS)
new_depth = CLAMP16(new_depth + (int16_t) params->zaColor);
if (params->fbzMode & FBZ_DEPTH_ENABLE) {
uint16_t old_depth = voodoo->params.aux_tiled ? aux_mem[x_tiled] : aux_mem[x];
DEPTH_TEST((params->fbzMode & FBZ_DEPTH_SOURCE) ? (params->zaColor & 0xffff) : new_depth);
}
dat = voodoo->params.col_tiled ? fb_mem[x_tiled] : fb_mem[x];
dest_r = (dat >> 8) & 0xf8;
dest_g = (dat >> 3) & 0xfc;
dest_b = (dat << 3) & 0xf8;
dest_r |= (dest_r >> 5);
dest_g |= (dest_g >> 6);
dest_b |= (dest_b >> 5);
dest_a = 0xff;
if (params->fbzColorPath & FBZCP_TEXTURE_ENABLED) {
if ((params->textureMode[0] & TEXTUREMODE_LOCAL_MASK) == TEXTUREMODE_LOCAL || !voodoo->dual_tmus) {
/*TMU0 only sampling local colour or only one TMU, only sample TMU0*/
voodoo_tmu_fetch(voodoo, params, state, 0, x);
} else if ((params->textureMode[0] & TEXTUREMODE_MASK) == TEXTUREMODE_PASSTHROUGH) {
/*TMU0 in pass-through mode, only sample TMU1*/
voodoo_tmu_fetch(voodoo, params, state, 1, x);
state->tex_r[0] = state->tex_r[1];
state->tex_g[0] = state->tex_g[1];
state->tex_b[0] = state->tex_b[1];
state->tex_a[0] = state->tex_a[1];
} else {
voodoo_tmu_fetch_and_blend(voodoo, params, state, x);
}
if ((params->fbzMode & FBZ_CHROMAKEY) && state->tex_r[0] == params->chromaKey_r && state->tex_g[0] == params->chromaKey_g && state->tex_b[0] == params->chromaKey_b) {
voodoo->fbiChromaFail++;
goto skip_pixel;
}
}
if (voodoo->trexInit1[0] & (1 << 18)) {
state->tex_r[0] = state->tex_g[0] = 0;
state->tex_b[0] = voodoo->tmuConfig;
}
if (cc_localselect_override)
sel = (state->tex_a[0] & 0x80) ? 1 : 0;
else
sel = cc_localselect;
if (sel) {
clocal_r = (params->color0 >> 16) & 0xff;
clocal_g = (params->color0 >> 8) & 0xff;
clocal_b = params->color0 & 0xff;
} else {
clocal_r = CLAMP(state->ir >> 12);
clocal_g = CLAMP(state->ig >> 12);
clocal_b = CLAMP(state->ib >> 12);
}
switch (_rgb_sel) {
case CC_LOCALSELECT_ITER_RGB: /*Iterated RGB*/
cother_r = CLAMP(state->ir >> 12);
cother_g = CLAMP(state->ig >> 12);
cother_b = CLAMP(state->ib >> 12);
break;
case CC_LOCALSELECT_TEX: /*TREX Color Output*/
cother_r = state->tex_r[0];
cother_g = state->tex_g[0];
cother_b = state->tex_b[0];
break;
case CC_LOCALSELECT_COLOR1: /*Color1 RGB*/
cother_r = (params->color1 >> 16) & 0xff;
cother_g = (params->color1 >> 8) & 0xff;
cother_b = params->color1 & 0xff;
break;
case CC_LOCALSELECT_LFB: /*Linear Frame Buffer*/
cother_r = src_r;
cother_g = src_g;
cother_b = src_b;
break;
default:
break;
}
switch (cca_localselect) {
case CCA_LOCALSELECT_ITER_A:
alocal = CLAMP(state->ia >> 12);
break;
case CCA_LOCALSELECT_COLOR0:
alocal = (params->color0 >> 24) & 0xff;
break;
case CCA_LOCALSELECT_ITER_Z:
alocal = CLAMP(state->z >> 20);
break;
default:
fatal("Bad cca_localselect %i\n", cca_localselect);
alocal = 0xff;
break;
}
switch (a_sel) {
case A_SEL_ITER_A:
aother = CLAMP(state->ia >> 12);
break;
case A_SEL_TEX:
aother = state->tex_a[0];
break;
case A_SEL_COLOR1:
aother = (params->color1 >> 24) & 0xff;
break;
default:
fatal("Bad a_sel %i\n", a_sel);
aother = 0;
break;
}
if (cc_zero_other) {
src_r = 0;
src_g = 0;
src_b = 0;
} else {
src_r = cother_r;
src_g = cother_g;
src_b = cother_b;
}
if (cca_zero_other)
src_a = 0;
else
src_a = aother;
if (cc_sub_clocal) {
src_r -= clocal_r;
src_g -= clocal_g;
src_b -= clocal_b;
}
if (cca_sub_clocal)
src_a -= alocal;
switch (cc_mselect) {
case CC_MSELECT_ZERO:
msel_r = 0;
msel_g = 0;
msel_b = 0;
break;
case CC_MSELECT_CLOCAL:
msel_r = clocal_r;
msel_g = clocal_g;
msel_b = clocal_b;
break;
case CC_MSELECT_AOTHER:
msel_r = aother;
msel_g = aother;
msel_b = aother;
break;
case CC_MSELECT_ALOCAL:
msel_r = alocal;
msel_g = alocal;
msel_b = alocal;
break;
case CC_MSELECT_TEX:
msel_r = state->tex_a[0];
msel_g = state->tex_a[0];
msel_b = state->tex_a[0];
break;
case CC_MSELECT_TEXRGB:
msel_r = state->tex_r[0];
msel_g = state->tex_g[0];
msel_b = state->tex_b[0];
break;
default:
fatal("Bad cc_mselect %i\n", cc_mselect);
msel_r = 0;
msel_g = 0;
msel_b = 0;
break;
}
switch (cca_mselect) {
case CCA_MSELECT_ZERO:
msel_a = 0;
break;
case CCA_MSELECT_ALOCAL:
msel_a = alocal;
break;
case CCA_MSELECT_AOTHER:
msel_a = aother;
break;
case CCA_MSELECT_ALOCAL2:
msel_a = alocal;
break;
case CCA_MSELECT_TEX:
msel_a = state->tex_a[0];
break;
default:
fatal("Bad cca_mselect %i\n", cca_mselect);
msel_a = 0;
break;
}
if (!cc_reverse_blend) {
msel_r ^= 0xff;
msel_g ^= 0xff;
msel_b ^= 0xff;
}
msel_r++;
msel_g++;
msel_b++;
if (!cca_reverse_blend)
msel_a ^= 0xff;
msel_a++;
src_r = (src_r * msel_r) >> 8;
src_g = (src_g * msel_g) >> 8;
src_b = (src_b * msel_b) >> 8;
src_a = (src_a * msel_a) >> 8;
switch (cc_add) {
case CC_ADD_CLOCAL:
src_r += clocal_r;
src_g += clocal_g;
src_b += clocal_b;
break;
case CC_ADD_ALOCAL:
src_r += alocal;
src_g += alocal;
src_b += alocal;
break;
case 0:
break;
default:
fatal("Bad cc_add %i\n", cc_add);
}
if (cca_add)
src_a += alocal;
src_r = CLAMP(src_r);
src_g = CLAMP(src_g);
src_b = CLAMP(src_b);
src_a = CLAMP(src_a);
if (cc_invert_output) {
src_r ^= 0xff;
src_g ^= 0xff;
src_b ^= 0xff;
}
if (cca_invert_output)
src_a ^= 0xff;
if (params->fogMode & FOG_ENABLE)
APPLY_FOG(src_r, src_g, src_b, state->z, state->ia, state->w);
if (params->alphaMode & 1)
ALPHA_TEST(src_a);
if (params->alphaMode & (1 << 4)) {
if (dithersub && !dither2x2 && voodoo->dithersub_enabled) {
dest_r = dithersub_rb[dest_r][real_y & 3][x & 3];
dest_g = dithersub_g[dest_g][real_y & 3][x & 3];
dest_b = dithersub_rb[dest_b][real_y & 3][x & 3];
}
if (dithersub && dither2x2 && voodoo->dithersub_enabled) {
dest_r = dithersub_rb2x2[dest_r][real_y & 1][x & 1];
dest_g = dithersub_g2x2[dest_g][real_y & 1][x & 1];
dest_b = dithersub_rb2x2[dest_b][real_y & 1][x & 1];
}
ALPHA_BLEND(src_r, src_g, src_b, src_a);
}
if (update) {
if (dither) {
if (dither2x2) {
src_r = dither_rb2x2[src_r][real_y & 1][x & 1];
src_g = dither_g2x2[src_g][real_y & 1][x & 1];
src_b = dither_rb2x2[src_b][real_y & 1][x & 1];
} else {
src_r = dither_rb[src_r][real_y & 3][x & 3];
src_g = dither_g[src_g][real_y & 3][x & 3];
src_b = dither_rb[src_b][real_y & 3][x & 3];
}
} else {
src_r >>= 3;
src_g >>= 2;
src_b >>= 3;
}
if (params->fbzMode & FBZ_RGB_WMASK) {
if (voodoo->params.col_tiled)
fb_mem[x_tiled] = src_b | (src_g << 5) | (src_r << 11);
else
fb_mem[x] = src_b | (src_g << 5) | (src_r << 11);
}
if ((params->fbzMode & (FBZ_DEPTH_WMASK | FBZ_DEPTH_ENABLE)) == (FBZ_DEPTH_WMASK | FBZ_DEPTH_ENABLE)) {
if (voodoo->params.aux_tiled)
aux_mem[x_tiled] = new_depth;
else
aux_mem[x] = new_depth;
}
}
}
voodoo->fbiPixelsOut++;
skip_pixel:
if (state->xdir > 0) {
state->ir += params->dRdX;
state->ig += params->dGdX;
state->ib += params->dBdX;
state->ia += params->dAdX;
state->z += params->dZdX;
state->tmu0_s += params->tmu[0].dSdX;
state->tmu0_t += params->tmu[0].dTdX;
state->tmu0_w += params->tmu[0].dWdX;
state->tmu1_s += params->tmu[1].dSdX;
state->tmu1_t += params->tmu[1].dTdX;
state->tmu1_w += params->tmu[1].dWdX;
state->w += params->dWdX;
} else {
state->ir -= params->dRdX;
state->ig -= params->dGdX;
state->ib -= params->dBdX;
state->ia -= params->dAdX;
state->z -= params->dZdX;
state->tmu0_s -= params->tmu[0].dSdX;
state->tmu0_t -= params->tmu[0].dTdX;
state->tmu0_w -= params->tmu[0].dWdX;
state->tmu1_s -= params->tmu[1].dSdX;
state->tmu1_t -= params->tmu[1].dTdX;
state->tmu1_w -= params->tmu[1].dWdX;
state->w -= params->dWdX;
}
x += state->xdir;
} while (start_x != x2);
voodoo->pixel_count[odd_even] += state->pixel_count;
voodoo->texel_count[odd_even] += state->texel_count;
voodoo->fbiPixelsIn += state->pixel_count;
if (voodoo->params.draw_offset == voodoo->params.front_offset && (real_y >> 1) < 2048)
voodoo->dirty_line[real_y >> 1] = 1;
next_line:
if (SLI_ENABLED) {
state->base_r += params->dRdY;
state->base_g += params->dGdY;
state->base_b += params->dBdY;
state->base_a += params->dAdY;
state->base_z += params->dZdY;
state->tmu[0].base_s += params->tmu[0].dSdY;
state->tmu[0].base_t += params->tmu[0].dTdY;
state->tmu[0].base_w += params->tmu[0].dWdY;
state->tmu[1].base_s += params->tmu[1].dSdY;
state->tmu[1].base_t += params->tmu[1].dTdY;
state->tmu[1].base_w += params->tmu[1].dWdY;
state->base_w += params->dWdY;
state->xstart += state->dx1;
state->xend += state->dx2;
}
state->base_r += params->dRdY;
state->base_g += params->dGdY;
state->base_b += params->dBdY;
state->base_a += params->dAdY;
state->base_z += params->dZdY;
state->tmu[0].base_s += params->tmu[0].dSdY;
state->tmu[0].base_t += params->tmu[0].dTdY;
state->tmu[0].base_w += params->tmu[0].dWdY;
state->tmu[1].base_s += params->tmu[1].dSdY;
state->tmu[1].base_t += params->tmu[1].dTdY;
state->tmu[1].base_w += params->tmu[1].dWdY;
state->base_w += params->dWdY;
state->xstart += state->dx1;
state->xend += state->dx2;
}
voodoo->texture_cache[0][params->tex_entry[0]].refcount_r[odd_even]++;
voodoo->texture_cache[1][params->tex_entry[1]].refcount_r[odd_even]++;
}
void
voodoo_triangle(voodoo_t *voodoo, voodoo_params_t *params, int odd_even)
{
voodoo_state_t state = { 0 };
int vertexAy_adjusted;
int vertexCy_adjusted;
int dx;
int dy;
uint64_t tempdx;
uint64_t tempdy;
uint64_t tempLOD;
int LOD;
int lodbias;
state.dx1 = state.dx2 = 0;
voodoo->tri_count++;
dx = 8 - (params->vertexAx & 0xf);
if ((params->vertexAx & 0xf) > 8)
dx += 16;
dy = 8 - (params->vertexAy & 0xf);
if ((params->vertexAy & 0xf) > 8)
dy += 16;
/* voodoo_render_log("voodoo_triangle %i %i %i : vA %f, %f vB %f, %f vC %f, %f f %i,%i %08x %08x %08x,%08x tex=%i,%i fogMode=%08x\n", odd_even, voodoo->params_read_idx[odd_even], voodoo->params_read_idx[odd_even] & PARAM_MASK, (float)params->vertexAx / 16.0, (float)params->vertexAy / 16.0,
(float)params->vertexBx / 16.0, (float)params->vertexBy / 16.0,
(float)params->vertexCx / 16.0, (float)params->vertexCy / 16.0,
(params->fbzColorPath & FBZCP_TEXTURE_ENABLED) ? params->tformat[0] : 0,
(params->fbzColorPath & FBZCP_TEXTURE_ENABLED) ? params->tformat[1] : 0, params->fbzColorPath, params->alphaMode, params->textureMode[0],params->textureMode[1], params->tex_entry[0],params->tex_entry[1], params->fogMode);*/
state.base_r = params->startR;
state.base_g = params->startG;
state.base_b = params->startB;
state.base_a = params->startA;
state.base_z = params->startZ;
state.tmu[0].base_s = params->tmu[0].startS;
state.tmu[0].base_t = params->tmu[0].startT;
state.tmu[0].base_w = params->tmu[0].startW;
state.tmu[1].base_s = params->tmu[1].startS;
state.tmu[1].base_t = params->tmu[1].startT;
state.tmu[1].base_w = params->tmu[1].startW;
state.base_w = params->startW;
if (params->fbzColorPath & FBZ_PARAM_ADJUST) {
state.base_r += (dx * params->dRdX + dy * params->dRdY) >> 4;
state.base_g += (dx * params->dGdX + dy * params->dGdY) >> 4;
state.base_b += (dx * params->dBdX + dy * params->dBdY) >> 4;
state.base_a += (dx * params->dAdX + dy * params->dAdY) >> 4;
state.base_z += (dx * params->dZdX + dy * params->dZdY) >> 4;
state.tmu[0].base_s += (dx * params->tmu[0].dSdX + dy * params->tmu[0].dSdY) >> 4;
state.tmu[0].base_t += (dx * params->tmu[0].dTdX + dy * params->tmu[0].dTdY) >> 4;
state.tmu[0].base_w += (dx * params->tmu[0].dWdX + dy * params->tmu[0].dWdY) >> 4;
state.tmu[1].base_s += (dx * params->tmu[1].dSdX + dy * params->tmu[1].dSdY) >> 4;
state.tmu[1].base_t += (dx * params->tmu[1].dTdX + dy * params->tmu[1].dTdY) >> 4;
state.tmu[1].base_w += (dx * params->tmu[1].dWdX + dy * params->tmu[1].dWdY) >> 4;
state.base_w += (dx * params->dWdX + dy * params->dWdY) >> 4;
}
tris++;
state.vertexAy = params->vertexAy & ~0xffff0000;
if (state.vertexAy & 0x8000)
state.vertexAy |= 0xffff0000;
state.vertexBy = params->vertexBy & ~0xffff0000;
if (state.vertexBy & 0x8000)
state.vertexBy |= 0xffff0000;
state.vertexCy = params->vertexCy & ~0xffff0000;
if (state.vertexCy & 0x8000)
state.vertexCy |= 0xffff0000;
state.vertexAx = params->vertexAx & ~0xffff0000;
if (state.vertexAx & 0x8000)
state.vertexAx |= 0xffff0000;
state.vertexBx = params->vertexBx & ~0xffff0000;
if (state.vertexBx & 0x8000)
state.vertexBx |= 0xffff0000;
state.vertexCx = params->vertexCx & ~0xffff0000;
if (state.vertexCx & 0x8000)
state.vertexCx |= 0xffff0000;
vertexAy_adjusted = (state.vertexAy + 7) >> 4;
vertexCy_adjusted = (state.vertexCy + 7) >> 4;
if (state.vertexBy - state.vertexAy)
state.dxAB = (int) ((((int64_t) state.vertexBx << 12) - ((int64_t) state.vertexAx << 12)) << 4) / (state.vertexBy - state.vertexAy);
else
state.dxAB = 0;
if (state.vertexCy - state.vertexAy)
state.dxAC = (int) ((((int64_t) state.vertexCx << 12) - ((int64_t) state.vertexAx << 12)) << 4) / (state.vertexCy - state.vertexAy);
else
state.dxAC = 0;
if (state.vertexCy - state.vertexBy)
state.dxBC = (int) ((((int64_t) state.vertexCx << 12) - ((int64_t) state.vertexBx << 12)) << 4) / (state.vertexCy - state.vertexBy);
else
state.dxBC = 0;
state.lod_min[0] = (params->tLOD[0] & 0x3f) << 6;
state.lod_max[0] = ((params->tLOD[0] >> 6) & 0x3f) << 6;
if (state.lod_max[0] > 0x800)
state.lod_max[0] = 0x800;
state.lod_min[1] = (params->tLOD[1] & 0x3f) << 6;
state.lod_max[1] = ((params->tLOD[1] >> 6) & 0x3f) << 6;
if (state.lod_max[1] > 0x800)
state.lod_max[1] = 0x800;
state.xstart = state.xend = state.vertexAx << 8;
state.xdir = params->sign ? -1 : 1;
state.y = (state.vertexAy + 8) >> 4;
state.ydir = 1;
tempdx = (params->tmu[0].dSdX >> 14) * (params->tmu[0].dSdX >> 14) + (params->tmu[0].dTdX >> 14) * (params->tmu[0].dTdX >> 14);
tempdy = (params->tmu[0].dSdY >> 14) * (params->tmu[0].dSdY >> 14) + (params->tmu[0].dTdY >> 14) * (params->tmu[0].dTdY >> 14);
if (tempdx > tempdy)
tempLOD = tempdx;
else
tempLOD = tempdy;
LOD = (int) (log2((double) tempLOD / (double) (1ULL << 36)) * 256);
LOD >>= 2;
lodbias = (params->tLOD[0] >> 12) & 0x3f;
if (lodbias & 0x20)
lodbias |= ~0x3f;
state.tmu[0].lod = LOD + (lodbias << 6);
tempdx = (params->tmu[1].dSdX >> 14) * (params->tmu[1].dSdX >> 14) + (params->tmu[1].dTdX >> 14) * (params->tmu[1].dTdX >> 14);
tempdy = (params->tmu[1].dSdY >> 14) * (params->tmu[1].dSdY >> 14) + (params->tmu[1].dTdY >> 14) * (params->tmu[1].dTdY >> 14);
if (tempdx > tempdy)
tempLOD = tempdx;
else
tempLOD = tempdy;
LOD = (int) (log2((double) tempLOD / (double) (1ULL << 36)) * 256);
LOD >>= 2;
lodbias = (params->tLOD[1] >> 12) & 0x3f;
if (lodbias & 0x20)
lodbias |= ~0x3f;
state.tmu[1].lod = LOD + (lodbias << 6);
voodoo_half_triangle(voodoo, params, &state, vertexAy_adjusted, vertexCy_adjusted, odd_even);
}
static void
render_thread(void *param, int odd_even)
{
voodoo_t *voodoo = (voodoo_t *) param;
while (voodoo->render_thread_run[odd_even]) {
thread_set_event(voodoo->render_not_full_event[odd_even]);
thread_wait_event(voodoo->wake_render_thread[odd_even], -1);
thread_reset_event(voodoo->wake_render_thread[odd_even]);
voodoo->render_voodoo_busy[odd_even] = 1;
while (!PARAM_EMPTY(odd_even)) {
uint64_t start_time = plat_timer_read();
uint64_t end_time;
voodoo_params_t *params = &voodoo->params_buffer[voodoo->params_read_idx[odd_even] & PARAM_MASK];
voodoo_triangle(voodoo, params, odd_even);
voodoo->params_read_idx[odd_even]++;
if (PARAM_ENTRIES(odd_even) > (PARAM_SIZE - 10))
thread_set_event(voodoo->render_not_full_event[odd_even]);
end_time = plat_timer_read();
voodoo->render_time[odd_even] += end_time - start_time;
}
voodoo->render_voodoo_busy[odd_even] = 0;
}
}
void
voodoo_render_thread_1(void *param)
{
render_thread(param, 0);
}
void
voodoo_render_thread_2(void *param)
{
render_thread(param, 1);
}
void
voodoo_render_thread_3(void *param)
{
render_thread(param, 2);
}
void
voodoo_render_thread_4(void *param)
{
render_thread(param, 3);
}
void
voodoo_queue_triangle(voodoo_t *voodoo, voodoo_params_t *params)
{
voodoo_params_t *params_new = &voodoo->params_buffer[voodoo->params_write_idx & PARAM_MASK];
while (PARAM_FULL(0) || (voodoo->render_threads >= 2 && PARAM_FULL(1)) || (voodoo->render_threads == 4 && (PARAM_FULL(2) || PARAM_FULL(3)))) {
thread_reset_event(voodoo->render_not_full_event[0]);
if (voodoo->render_threads >= 2)
thread_reset_event(voodoo->render_not_full_event[1]);
if (voodoo->render_threads == 4) {
thread_reset_event(voodoo->render_not_full_event[2]);
thread_reset_event(voodoo->render_not_full_event[3]);
}
if (PARAM_FULL(0))
thread_wait_event(voodoo->render_not_full_event[0], -1); /*Wait for room in ringbuffer*/
if (voodoo->render_threads >= 2 && PARAM_FULL(1))
thread_wait_event(voodoo->render_not_full_event[1], -1); /*Wait for room in ringbuffer*/
if (voodoo->render_threads == 4 && PARAM_FULL(2))
thread_wait_event(voodoo->render_not_full_event[2], -1); /*Wait for room in ringbuffer*/
if (voodoo->render_threads == 4 && PARAM_FULL(3))
thread_wait_event(voodoo->render_not_full_event[3], -1); /*Wait for room in ringbuffer*/
}
voodoo_use_texture(voodoo, params, 0);
if (voodoo->dual_tmus)
voodoo_use_texture(voodoo, params, 1);
memcpy(params_new, params, sizeof(voodoo_params_t));
voodoo->params_write_idx++;
if (PARAM_ENTRIES(0) < 4 || (voodoo->render_threads >= 2 && PARAM_ENTRIES(1) < 4) || (voodoo->render_threads == 4 && (PARAM_ENTRIES(2) < 4 || PARAM_ENTRIES(3) < 4)))
voodoo_wake_render_thread(voodoo);
}
``` | /content/code_sandbox/src/video/vid_voodoo_render.c | c | 2016-06-25T22:29:10 | 2024-08-16T19:09:21 | 86Box | 86Box/86Box | 2,616 | 18,987 |
```c
/*
* 86Box A hypervisor and IBM PC system emulator that specializes in
* running old operating systems and software designed for IBM
* PC systems and compatibles from 1981 through fairly recent
* system designs based on the PCI bus.
*
* This file is part of the 86Box distribution.
*
* Emulation of a AT&T 20c490/491 and 492/493 RAMDAC.
*
*
*
* Authors: Miran Grca, <mgrca8@gmail.com>
*
*/
#include <stdio.h>
#include <stdint.h>
#include <stdlib.h>
#include <string.h>
#include <wchar.h>
#include <86box/86box.h>
#include <86box/device.h>
#include <86box/mem.h>
#include <86box/timer.h>
#include <86box/video.h>
#include <86box/vid_svga.h>
typedef struct att49x_ramdac_t {
int type;
int state;
uint8_t ctrl;
} att49x_ramdac_t;
enum {
ATT_490 = 0,
ATT_491,
ATT_492
};
static void
att49x_ramdac_control(uint8_t val, void *priv, svga_t *svga)
{
att49x_ramdac_t *ramdac = (att49x_ramdac_t *) priv;
ramdac->ctrl = val;
switch ((ramdac->ctrl >> 5) & 7) {
case 0:
case 1:
case 2:
case 3:
svga->bpp = 8;
break;
case 4:
case 5:
svga->bpp = 15;
break;
case 6:
svga->bpp = 16;
break;
case 7:
svga->bpp = 24;
break;
default:
break;
}
if (ramdac->type == ATT_490 || ramdac->type == ATT_491)
svga_set_ramdac_type(svga, (val & 2) ? RAMDAC_8BIT : RAMDAC_6BIT);
svga_recalctimings(svga);
}
void
att49x_ramdac_out(uint16_t addr, int rs2, uint8_t val, void *priv, svga_t *svga)
{
att49x_ramdac_t *ramdac = (att49x_ramdac_t *) priv;
uint8_t rs = (addr & 0x03);
rs |= ((!!rs2) << 2);
switch (rs) {
case 0x00:
case 0x01:
case 0x03:
case 0x04:
case 0x05:
case 0x07:
svga_out(addr, val, svga);
ramdac->state = 0;
break;
case 0x02:
switch (ramdac->state) {
case 4:
att49x_ramdac_control(val, ramdac, svga);
break;
default:
svga_out(addr, val, svga);
break;
}
break;
case 0x06:
att49x_ramdac_control(val, ramdac, svga);
ramdac->state = 0;
break;
default:
break;
}
}
uint8_t
att49x_ramdac_in(uint16_t addr, int rs2, void *priv, svga_t *svga)
{
att49x_ramdac_t *ramdac = (att49x_ramdac_t *) priv;
uint8_t temp = 0xff;
uint8_t rs = (addr & 0x03);
rs |= ((!!rs2) << 2);
switch (rs) {
case 0x00:
case 0x01:
case 0x03:
case 0x04:
case 0x05:
case 0x07:
temp = svga_in(addr, svga);
ramdac->state = 0;
break;
case 0x02:
switch (ramdac->state) {
case 1:
case 2:
case 3:
temp = 0x00;
ramdac->state++;
break;
case 4:
temp = ramdac->ctrl;
ramdac->state = 0;
break;
default:
temp = svga_in(addr, svga);
ramdac->state++;
break;
}
break;
case 0x06:
temp = ramdac->ctrl;
ramdac->state = 0;
break;
default:
break;
}
return temp;
}
static void *
att49x_ramdac_init(const device_t *info)
{
att49x_ramdac_t *ramdac = (att49x_ramdac_t *) malloc(sizeof(att49x_ramdac_t));
memset(ramdac, 0, sizeof(att49x_ramdac_t));
ramdac->type = info->local;
return ramdac;
}
static void
att49x_ramdac_close(void *priv)
{
att49x_ramdac_t *ramdac = (att49x_ramdac_t *) priv;
if (ramdac)
free(ramdac);
}
const device_t att490_ramdac_device = {
.name = "AT&T 20c490 RAMDAC",
.internal_name = "att490_ramdac",
.flags = 0,
.local = ATT_490,
.init = att49x_ramdac_init,
.close = att49x_ramdac_close,
.reset = NULL,
{ .available = NULL },
.speed_changed = NULL,
.force_redraw = NULL,
.config = NULL
};
const device_t att491_ramdac_device = {
.name = "AT&T 20c491 RAMDAC",
.internal_name = "att491_ramdac",
.flags = 0,
.local = ATT_491,
.init = att49x_ramdac_init,
.close = att49x_ramdac_close,
.reset = NULL,
{ .available = NULL },
.speed_changed = NULL,
.force_redraw = NULL,
.config = NULL
};
const device_t att492_ramdac_device = {
.name = "AT&T 20c492 RAMDAC",
.internal_name = "att492_ramdac",
.flags = 0,
.local = ATT_492,
.init = att49x_ramdac_init,
.close = att49x_ramdac_close,
.reset = NULL,
{ .available = NULL },
.speed_changed = NULL,
.force_redraw = NULL,
.config = NULL
};
``` | /content/code_sandbox/src/video/vid_att20c49x_ramdac.c | c | 2016-06-25T22:29:10 | 2024-08-16T19:09:21 | 86Box | 86Box/86Box | 2,616 | 1,506 |
```c
/*
* 86Box A hypervisor and IBM PC system emulator that specializes in
* running old operating systems and software designed for IBM
* PC systems and compatibles from 1981 through fairly recent
* system designs based on the PCI bus.
*
* This file is part of the 86Box distribution.
*
* Emulation of the Compaq CGA graphics cards.
*
*
*
* Authors: John Elliott, <jce@seasip.info>
* Sarah Walker, <path_to_url
* Miran Grca, <mgrca8@gmail.com>
*
*/
#include <stdarg.h>
#include <stdio.h>
#include <stdint.h>
#include <string.h>
#include <stdlib.h>
#include <wchar.h>
#include <math.h>
#define HAVE_STDARG_H
#include <86box/86box.h>
#include "cpu.h"
#include <86box/io.h>
#include <86box/timer.h>
#include <86box/pit.h>
#include <86box/mem.h>
#include <86box/rom.h>
#include <86box/device.h>
#include <86box/video.h>
#include <86box/vid_cga.h>
#include <86box/vid_cga_comp.h>
#define CGA_RGB 0
#define CGA_COMPOSITE 1
static uint32_t vflags;
static uint8_t mdaattr[256][2][2];
typedef struct compaq_cga_t {
cga_t cga;
} compaq_cga_t;
#ifdef ENABLE_COMPAQ_CGA_LOG
int compaq_cga_do_log = ENABLE_COMPAQ_CGA_LOG;
static void
compaq_cga_log(const char *fmt, ...)
{
va_list ap;
if (compaq_cga_do_log) {
va_start(ap, fmt);
pclog_ex(fmt, ap);
va_end(ap);
}
}
#else
# define compaq_cga_log(fmt, ...)
#endif
void
compaq_cga_recalctimings(compaq_cga_t *self)
{
double _dispontime;
double _dispofftime;
double disptime;
disptime = self->cga.crtc[0] + 1;
_dispontime = self->cga.crtc[1];
_dispofftime = disptime - _dispontime;
_dispontime *= MDACONST;
_dispofftime *= MDACONST;
self->cga.dispontime = (uint64_t) (_dispontime);
self->cga.dispofftime = (uint64_t) (_dispofftime);
}
void
compaq_cga_poll(void *priv)
{
compaq_cga_t *self = (compaq_cga_t *) priv;
uint16_t ca = (self->cga.crtc[15] | (self->cga.crtc[14] << 8)) & 0x3fff;
int drawcursor;
int x;
int c;
int xs_temp;
int ys_temp;
int oldvc;
uint8_t chr;
uint8_t attr;
uint8_t border;
uint8_t cols[4];
int oldsc;
int underline = 0;
int blink = 0;
/* If in graphics mode or character height is not 13, behave as CGA */
if ((self->cga.cgamode & 0x12) || (self->cga.crtc[9] != 13)) {
overscan_x = overscan_y = 16;
cga_poll(&self->cga);
return;
} else
overscan_x = overscan_y = 0;
/* We are in Compaq 350-line CGA territory */
if (!self->cga.linepos) {
timer_advance_u64(&self->cga.timer, self->cga.dispofftime);
self->cga.cgastat |= 1;
self->cga.linepos = 1;
oldsc = self->cga.sc;
if ((self->cga.crtc[8] & 3) == 3)
self->cga.sc = ((self->cga.sc << 1) + self->cga.oddeven) & 7;
if (self->cga.cgadispon) {
if (self->cga.displine < self->cga.firstline) {
self->cga.firstline = self->cga.displine;
video_wait_for_buffer();
compaq_cga_log("Firstline %i\n", self->cga.firstline);
}
self->cga.lastline = self->cga.displine;
cols[0] = (self->cga.cgacol & 15) + 16;
for (c = 0; c < 8; c++) {
buffer32->line[self->cga.displine][c] = cols[0];
if (self->cga.cgamode & 1)
buffer32->line[self->cga.displine][c + (self->cga.crtc[1] << 3) + 8] = cols[0];
else
buffer32->line[self->cga.displine][c + (self->cga.crtc[1] << 4) + 8] = cols[0];
}
if (self->cga.cgamode & 1) {
for (x = 0; x < self->cga.crtc[1]; x++) {
chr = self->cga.charbuffer[x << 1];
attr = self->cga.charbuffer[(x << 1) + 1];
drawcursor = ((self->cga.ma == ca) && self->cga.con && self->cga.cursoron);
if (vflags) {
underline = 0;
blink = ((self->cga.cgablink & 8) && (self->cga.cgamode & 0x20) && (attr & 0x80) && !drawcursor);
}
if (vflags && (self->cga.cgamode & 0x80)) {
cols[0] = mdaattr[attr][blink][0];
cols[1] = mdaattr[attr][blink][1];
if ((self->cga.sc == 12) && ((attr & 7) == 1))
underline = 1;
} else if (self->cga.cgamode & 0x20) {
cols[1] = (attr & 15) + 16;
cols[0] = ((attr >> 4) & 7) + 16;
if (vflags) {
if (blink)
cols[1] = cols[0];
} else {
if ((self->cga.cgablink & 8) && (attr & 0x80) && !self->cga.drawcursor)
cols[1] = cols[0];
}
} else {
cols[1] = (attr & 15) + 16;
cols[0] = (attr >> 4) + 16;
}
if (vflags && underline) {
for (c = 0; c < 8; c++)
buffer32->line[self->cga.displine][(x << 3) + c + 8] = mdaattr[attr][blink][1];
} else if (drawcursor) {
for (c = 0; c < 8; c++)
buffer32->line[self->cga.displine][(x << 3) + c + 8] = cols[(fontdatm[chr + self->cga.fontbase][self->cga.sc & 15] & (1 << (c ^ 7))) ? 1 : 0] ^ 15;
} else {
for (c = 0; c < 8; c++)
buffer32->line[self->cga.displine][(x << 3) + c + 8] = cols[(fontdatm[chr + self->cga.fontbase][self->cga.sc & 15] & (1 << (c ^ 7))) ? 1 : 0];
}
self->cga.ma++;
}
} else {
for (x = 0; x < self->cga.crtc[1]; x++) {
chr = self->cga.vram[(self->cga.ma << 1) & 0x3fff];
attr = self->cga.vram[((self->cga.ma << 1) + 1) & 0x3fff];
drawcursor = ((self->cga.ma == ca) && self->cga.con && self->cga.cursoron);
if (vflags) {
underline = 0;
blink = ((self->cga.cgablink & 8) && (self->cga.cgamode & 0x20) && (attr & 0x80) && !drawcursor);
}
if (vflags && (self->cga.cgamode & 0x80)) {
cols[0] = mdaattr[attr][blink][0];
cols[1] = mdaattr[attr][blink][1];
if (self->cga.sc == 12 && (attr & 7) == 1)
underline = 1;
} else if (self->cga.cgamode & 0x20) {
cols[1] = (attr & 15) + 16;
cols[0] = ((attr >> 4) & 7) + 16;
if (vflags) {
if (blink)
cols[1] = cols[0];
} else {
if ((self->cga.cgablink & 8) && (attr & 0x80) && !self->cga.drawcursor)
cols[1] = cols[0];
}
} else {
cols[1] = (attr & 15) + 16;
cols[0] = (attr >> 4) + 16;
}
self->cga.ma++;
if (vflags && underline) {
for (c = 0; c < 8; c++)
buffer32->line[self->cga.displine][(x << 4) + (c << 1) + 8] = buffer32->line[self->cga.displine][(x << 4) + (c << 1) + 9] = mdaattr[attr][blink][1];
} else if (drawcursor) {
for (c = 0; c < 8; c++)
buffer32->line[self->cga.displine][(x << 4) + (c << 1) + 8] = buffer32->line[self->cga.displine][(x << 4) + (c << 1) + 1 + 8] = cols[(fontdatm[chr + self->cga.fontbase][self->cga.sc & 15] & (1 << (c ^ 7))) ? 1 : 0] ^ 15;
} else {
for (c = 0; c < 8; c++)
buffer32->line[self->cga.displine][(x << 4) + (c << 1) + 8] = buffer32->line[self->cga.displine][(x << 4) + (c << 1) + 1 + 8] = cols[(fontdatm[chr + self->cga.fontbase][self->cga.sc & 15] & (1 << (c ^ 7))) ? 1 : 0];
}
}
}
} else {
cols[0] = (self->cga.cgacol & 15) + 16;
if (self->cga.cgamode & 1)
hline(buffer32, 0, self->cga.displine, (self->cga.crtc[1] << 3) + 16, cols[0]);
else
hline(buffer32, 0, self->cga.displine, (self->cga.crtc[1] << 4) + 16, cols[0]);
}
if (self->cga.cgamode & 1)
x = (self->cga.crtc[1] << 3) + 16;
else
x = (self->cga.crtc[1] << 4) + 16;
if (self->cga.composite) {
if (self->cga.cgamode & 0x10)
border = 0x00;
else
border = self->cga.cgacol & 0x0f;
if (vflags)
Composite_Process(self->cga.cgamode & 0x7f, border, x >> 2, buffer32->line[self->cga.displine]);
else
Composite_Process(self->cga.cgamode, border, x >> 2, buffer32->line[self->cga.displine]);
} else
video_process_8(x, self->cga.displine);
self->cga.sc = oldsc;
if (self->cga.vc == self->cga.crtc[7] && !self->cga.sc)
self->cga.cgastat |= 8;
self->cga.displine++;
if (self->cga.displine >= 500)
self->cga.displine = 0;
} else {
timer_advance_u64(&self->cga.timer, self->cga.dispontime);
self->cga.linepos = 0;
if (self->cga.vsynctime) {
self->cga.vsynctime--;
if (!self->cga.vsynctime)
self->cga.cgastat &= ~8;
}
if (self->cga.sc == (self->cga.crtc[11] & 31) || ((self->cga.crtc[8] & 3) == 3 && self->cga.sc == ((self->cga.crtc[11] & 31) >> 1))) {
self->cga.con = 0;
self->cga.coff = 1;
}
if ((self->cga.crtc[8] & 3) == 3 && self->cga.sc == (self->cga.crtc[9] >> 1))
self->cga.maback = self->cga.ma;
if (self->cga.vadj) {
self->cga.sc++;
self->cga.sc &= 31;
self->cga.ma = self->cga.maback;
self->cga.vadj--;
if (!self->cga.vadj) {
self->cga.cgadispon = 1;
self->cga.ma = self->cga.maback = (self->cga.crtc[13] | (self->cga.crtc[12] << 8)) & 0x3fff;
self->cga.sc = 0;
}
} else if (self->cga.sc == self->cga.crtc[9]) {
self->cga.maback = self->cga.ma;
self->cga.sc = 0;
oldvc = self->cga.vc;
self->cga.vc++;
self->cga.vc &= 127;
if (self->cga.vc == self->cga.crtc[6])
self->cga.cgadispon = 0;
if (oldvc == self->cga.crtc[4]) {
self->cga.vc = 0;
self->cga.vadj = self->cga.crtc[5];
if (!self->cga.vadj)
self->cga.cgadispon = 1;
if (!self->cga.vadj)
self->cga.ma = self->cga.maback = (self->cga.crtc[13] | (self->cga.crtc[12] << 8)) & 0x3fff;
if ((self->cga.crtc[10] & 0x60) == 0x20)
self->cga.cursoron = 0;
else
self->cga.cursoron = self->cga.cgablink & 8;
}
if (self->cga.vc == self->cga.crtc[7]) {
self->cga.cgadispon = 0;
self->cga.displine = 0;
self->cga.vsynctime = 16;
if (self->cga.crtc[7]) {
compaq_cga_log("Lastline %i Firstline %i %i\n", self->cga.lastline,
self->cga.firstline, self->cga.lastline - self->cga.firstline);
if (self->cga.cgamode & 1)
x = (self->cga.crtc[1] << 3) + 16;
else
x = (self->cga.crtc[1] << 4) + 16;
self->cga.lastline++;
xs_temp = x;
ys_temp = (self->cga.lastline - self->cga.firstline);
if ((xs_temp > 0) && (ys_temp > 0)) {
if (xs_temp < 64)
xs_temp = 656;
if (ys_temp < 32)
ys_temp = 400;
if (!enable_overscan)
xs_temp -= 16;
if ((self->cga.cgamode & 8) && ((xs_temp != xsize) || (ys_temp != ysize) || video_force_resize_get())) {
xsize = xs_temp;
ysize = ys_temp;
set_screen_size(xsize, ysize + (enable_overscan ? 16 : 0));
if (video_force_resize_get())
video_force_resize_set(0);
}
if (enable_overscan)
video_blit_memtoscreen(0, self->cga.firstline - 8, xsize, (self->cga.lastline - self->cga.firstline) + 16);
else
video_blit_memtoscreen(8, self->cga.firstline, xsize, self->cga.lastline - self->cga.firstline);
}
frames++;
video_res_x = xsize;
if (enable_overscan)
xsize -= 16;
video_res_y = ysize;
if (self->cga.cgamode & 1) {
video_res_x /= 8;
video_res_y /= self->cga.crtc[9] + 1;
video_bpp = 0;
} else if (!(self->cga.cgamode & 2)) {
video_res_x /= 16;
video_res_y /= self->cga.crtc[9] + 1;
video_bpp = 0;
} else if (!(self->cga.cgamode & 16)) {
video_res_x /= 2;
video_bpp = 2;
} else
video_bpp = 1;
}
self->cga.firstline = 1000;
self->cga.lastline = 0;
self->cga.cgablink++;
self->cga.oddeven ^= 1;
}
} else {
self->cga.sc++;
self->cga.sc &= 31;
self->cga.ma = self->cga.maback;
}
if (self->cga.cgadispon)
self->cga.cgastat &= ~1;
if (self->cga.sc == (self->cga.crtc[10] & 31) || ((self->cga.crtc[8] & 3) == 3 && self->cga.sc == ((self->cga.crtc[10] & 31) >> 1)))
self->cga.con = 1;
if (self->cga.cgadispon && (self->cga.cgamode & 1)) {
for (x = 0; x < (self->cga.crtc[1] << 1); x++)
self->cga.charbuffer[x] = self->cga.vram[((self->cga.ma << 1) + x) & 0x3fff];
}
}
}
void *
compaq_cga_init(const device_t *info)
{
int display_type;
compaq_cga_t *self = malloc(sizeof(compaq_cga_t));
memset(self, 0, sizeof(compaq_cga_t));
display_type = device_get_config_int("display_type");
self->cga.composite = (display_type != CGA_RGB);
self->cga.revision = device_get_config_int("composite_type");
self->cga.snow_enabled = device_get_config_int("snow_enabled");
self->cga.vram = malloc(0x4000);
cga_comp_init(self->cga.revision);
timer_add(&self->cga.timer, compaq_cga_poll, self, 1);
mem_mapping_add(&self->cga.mapping, 0xb8000, 0x08000, cga_read, NULL, NULL, cga_write, NULL, NULL, NULL /*self->cga.vram*/, MEM_MAPPING_EXTERNAL, self);
io_sethandler(0x03d0, 0x0010, cga_in, NULL, NULL, cga_out, NULL, NULL, self);
if (info->local) {
for (uint16_t c = 0; c < 256; c++) {
mdaattr[c][0][0] = mdaattr[c][1][0] = mdaattr[c][1][1] = 16;
if (c & 8)
mdaattr[c][0][1] = 15 + 16;
else
mdaattr[c][0][1] = 7 + 16;
}
mdaattr[0x70][0][1] = 16;
mdaattr[0x70][0][0] = mdaattr[0x70][1][0] = mdaattr[0x70][1][1] = 16 + 15;
mdaattr[0xF0][0][1] = 16;
mdaattr[0xF0][0][0] = mdaattr[0xF0][1][0] = mdaattr[0xF0][1][1] = 16 + 15;
mdaattr[0x78][0][1] = 16 + 7;
mdaattr[0x78][0][0] = mdaattr[0x78][1][0] = mdaattr[0x78][1][1] = 16 + 15;
mdaattr[0xF8][0][1] = 16 + 7;
mdaattr[0xF8][0][0] = mdaattr[0xF8][1][0] = mdaattr[0xF8][1][1] = 16 + 15;
mdaattr[0x00][0][1] = mdaattr[0x00][1][1] = 16;
mdaattr[0x08][0][1] = mdaattr[0x08][1][1] = 16;
mdaattr[0x80][0][1] = mdaattr[0x80][1][1] = 16;
mdaattr[0x88][0][1] = mdaattr[0x88][1][1] = 16;
}
vflags = info->local;
overscan_x = overscan_y = 16;
self->cga.rgb_type = device_get_config_int("rgb_type");
cga_palette = (self->cga.rgb_type << 1);
cgapal_rebuild();
self->cga.crtc[9] = 13;
return self;
}
void
compaq_cga_close(void *priv)
{
compaq_cga_t *self = (compaq_cga_t *) priv;
free(self->cga.vram);
free(self);
}
void
compaq_cga_speed_changed(void *priv)
{
compaq_cga_t *self = (compaq_cga_t *) priv;
if (self->cga.crtc[9] == 13) /* Character height */
compaq_cga_recalctimings(self);
else
cga_recalctimings(&self->cga);
}
extern const device_config_t cga_config[];
const device_t compaq_cga_device = {
.name = "Compaq CGA",
.internal_name = "compaq_cga",
.flags = DEVICE_ISA,
.local = 0,
.init = compaq_cga_init,
.close = compaq_cga_close,
.reset = NULL,
{ .available = NULL },
.speed_changed = compaq_cga_speed_changed,
.force_redraw = NULL,
.config = cga_config
};
const device_t compaq_cga_2_device = {
.name = "Compaq CGA 2",
.internal_name = "compaq_cga_2",
.flags = DEVICE_ISA,
.local = 1,
.init = compaq_cga_init,
.close = compaq_cga_close,
.reset = NULL,
{ .available = NULL },
.speed_changed = compaq_cga_speed_changed,
.force_redraw = NULL,
.config = cga_config
};
``` | /content/code_sandbox/src/video/vid_compaq_cga.c | c | 2016-06-25T22:29:10 | 2024-08-16T19:09:21 | 86Box | 86Box/86Box | 2,616 | 5,768 |
```c
/*
* 86Box A hypervisor and IBM PC system emulator that specializes in
* running old operating systems and software designed for IBM
* PC systems and compatibles from 1981 through fairly recent
* system designs based on the PCI bus.
*
* This file is part of the 86Box distribution.
*
* Plantronics ColorPlus emulation.
*
*
*
* Authors: Sarah Walker, <path_to_url
* Miran Grca, <mgrca8@gmail.com>
*
*/
#include <stdio.h>
#include <stdint.h>
#include <string.h>
#include <stdlib.h>
#include <wchar.h>
#include <math.h>
#include <86box/86box.h>
#include "cpu.h"
#include <86box/io.h>
#include <86box/timer.h>
#include <86box/lpt.h>
#include <86box/pit.h>
#include <86box/mem.h>
#include <86box/device.h>
#include <86box/video.h>
#include <86box/vid_cga.h>
#include <86box/vid_colorplus.h>
#include <86box/vid_cga_comp.h>
#include <86box/plat_unused.h>
/* Bits in the colorplus control register: */
#define COLORPLUS_PLANE_SWAP 0x40 /* Swap planes at 0000h and 4000h */
#define COLORPLUS_640x200_MODE 0x20 /* 640x200x4 mode active */
#define COLORPLUS_320x200_MODE 0x10 /* 320x200x16 mode active */
#define COLORPLUS_EITHER_MODE 0x30 /* Either mode active */
/* Bits in the CGA graphics mode register */
#define CGA_GRAPHICS_MODE 0x02 /* CGA graphics mode selected? */
#define CGA_RGB 0
#define CGA_COMPOSITE 1
#define COMPOSITE_OLD 0
#define COMPOSITE_NEW 1
video_timings_t timing_colorplus = { .type = VIDEO_ISA, .write_b = 8, .write_w = 16, .write_l = 32, .read_b = 8, .read_w = 16, .read_l = 32 };
void cga_recalctimings(cga_t *cga);
void
colorplus_out(uint16_t addr, uint8_t val, void *priv)
{
colorplus_t *colorplus = (colorplus_t *) priv;
if (addr == 0x3DD) {
colorplus->control = val & 0x70;
} else {
cga_out(addr, val, &colorplus->cga);
}
}
uint8_t
colorplus_in(uint16_t addr, void *priv)
{
colorplus_t *colorplus = (colorplus_t *) priv;
return cga_in(addr, &colorplus->cga);
}
void
colorplus_write(uint32_t addr, uint8_t val, void *priv)
{
colorplus_t *colorplus = (colorplus_t *) priv;
if ((colorplus->control & COLORPLUS_PLANE_SWAP) && (colorplus->control & COLORPLUS_EITHER_MODE) && (colorplus->cga.cgamode & CGA_GRAPHICS_MODE)) {
addr ^= 0x4000;
} else if (!(colorplus->control & COLORPLUS_EITHER_MODE)) {
addr &= 0x3FFF;
}
colorplus->cga.vram[addr & 0x7fff] = val;
if (colorplus->cga.snow_enabled) {
int offset = ((timer_get_remaining_u64(&colorplus->cga.timer) / CGACONST) * 2) & 0xfc;
colorplus->cga.charbuffer[offset] = colorplus->cga.vram[addr & 0x7fff];
colorplus->cga.charbuffer[offset | 1] = colorplus->cga.vram[addr & 0x7fff];
}
cycles -= 4;
}
uint8_t
colorplus_read(uint32_t addr, void *priv)
{
colorplus_t *colorplus = (colorplus_t *) priv;
if ((colorplus->control & COLORPLUS_PLANE_SWAP) && (colorplus->control & COLORPLUS_EITHER_MODE) && (colorplus->cga.cgamode & CGA_GRAPHICS_MODE)) {
addr ^= 0x4000;
} else if (!(colorplus->control & COLORPLUS_EITHER_MODE)) {
addr &= 0x3FFF;
}
cycles -= 4;
if (colorplus->cga.snow_enabled) {
int offset = ((timer_get_remaining_u64(&colorplus->cga.timer) / CGACONST) * 2) & 0xfc;
colorplus->cga.charbuffer[offset] = colorplus->cga.vram[addr & 0x7fff];
colorplus->cga.charbuffer[offset | 1] = colorplus->cga.vram[addr & 0x7fff];
}
return colorplus->cga.vram[addr & 0x7fff];
}
void
colorplus_recalctimings(colorplus_t *colorplus)
{
cga_recalctimings(&colorplus->cga);
}
void
colorplus_poll(void *priv)
{
colorplus_t *colorplus = (colorplus_t *) priv;
int x;
int c;
int oldvc;
uint16_t dat0;
uint16_t dat1;
int cols[4];
int col;
int oldsc;
static const int cols16[16] = { 0x10, 0x12, 0x14, 0x16,
0x18, 0x1A, 0x1C, 0x1E,
0x11, 0x13, 0x15, 0x17,
0x19, 0x1B, 0x1D, 0x1F };
const uint8_t *plane0 = colorplus->cga.vram;
const uint8_t *plane1 = colorplus->cga.vram + 0x4000;
/* If one of the extra modes is not selected, drop down to the CGA
* drawing code. */
if (!((colorplus->control & COLORPLUS_EITHER_MODE) && (colorplus->cga.cgamode & CGA_GRAPHICS_MODE))) {
cga_poll(&colorplus->cga);
return;
}
if (!colorplus->cga.linepos) {
timer_advance_u64(&colorplus->cga.timer, colorplus->cga.dispofftime);
colorplus->cga.cgastat |= 1;
colorplus->cga.linepos = 1;
oldsc = colorplus->cga.sc;
if ((colorplus->cga.crtc[8] & 3) == 3)
colorplus->cga.sc = ((colorplus->cga.sc << 1) + colorplus->cga.oddeven) & 7;
if (colorplus->cga.cgadispon) {
if (colorplus->cga.displine < colorplus->cga.firstline) {
colorplus->cga.firstline = colorplus->cga.displine;
video_wait_for_buffer();
}
colorplus->cga.lastline = colorplus->cga.displine;
/* Left / right border */
for (c = 0; c < 8; c++) {
buffer32->line[colorplus->cga.displine][c] = buffer32->line[colorplus->cga.displine][c + (colorplus->cga.crtc[1] << 4) + 8] = (colorplus->cga.cgacol & 15) + 16;
}
if (colorplus->control & COLORPLUS_320x200_MODE) {
for (x = 0; x < colorplus->cga.crtc[1]; x++) {
dat0 = (plane0[((colorplus->cga.ma << 1) & 0x1fff) + ((colorplus->cga.sc & 1) * 0x2000)] << 8) | plane0[((colorplus->cga.ma << 1) & 0x1fff) + ((colorplus->cga.sc & 1) * 0x2000) + 1];
dat1 = (plane1[((colorplus->cga.ma << 1) & 0x1fff) + ((colorplus->cga.sc & 1) * 0x2000)] << 8) | plane1[((colorplus->cga.ma << 1) & 0x1fff) + ((colorplus->cga.sc & 1) * 0x2000) + 1];
colorplus->cga.ma++;
for (c = 0; c < 8; c++) {
buffer32->line[colorplus->cga.displine][(x << 4) + (c << 1) + 8] = buffer32->line[colorplus->cga.displine][(x << 4) + (c << 1) + 1 + 8] = cols16[(dat0 >> 14) | ((dat1 >> 14) << 2)];
dat0 <<= 2;
dat1 <<= 2;
}
}
} else if (colorplus->control & COLORPLUS_640x200_MODE) {
cols[0] = (colorplus->cga.cgacol & 15) | 16;
col = (colorplus->cga.cgacol & 16) ? 24 : 16;
if (colorplus->cga.cgamode & 4) {
cols[1] = col | 3;
cols[2] = col | 4;
cols[3] = col | 7;
} else if (colorplus->cga.cgacol & 32) {
cols[1] = col | 3;
cols[2] = col | 5;
cols[3] = col | 7;
} else {
cols[1] = col | 2;
cols[2] = col | 4;
cols[3] = col | 6;
}
for (x = 0; x < colorplus->cga.crtc[1]; x++) {
dat0 = (plane0[((colorplus->cga.ma << 1) & 0x1fff) + ((colorplus->cga.sc & 1) * 0x2000)] << 8) | plane0[((colorplus->cga.ma << 1) & 0x1fff) + ((colorplus->cga.sc & 1) * 0x2000) + 1];
dat1 = (plane1[((colorplus->cga.ma << 1) & 0x1fff) + ((colorplus->cga.sc & 1) * 0x2000)] << 8) | plane1[((colorplus->cga.ma << 1) & 0x1fff) + ((colorplus->cga.sc & 1) * 0x2000) + 1];
colorplus->cga.ma++;
for (c = 0; c < 16; c++) {
buffer32->line[colorplus->cga.displine][(x << 4) + c + 8] = cols[(dat0 >> 15) | ((dat1 >> 15) << 1)];
dat0 <<= 1;
dat1 <<= 1;
}
}
}
} else /* Top / bottom border */
{
cols[0] = (colorplus->cga.cgacol & 15) + 16;
hline(buffer32, 0, colorplus->cga.displine, (colorplus->cga.crtc[1] << 4) + 16, cols[0]);
}
x = (colorplus->cga.crtc[1] << 4) + 16;
if (colorplus->cga.composite)
Composite_Process(colorplus->cga.cgamode, 0, x >> 2, buffer32->line[colorplus->cga.displine]);
else
video_process_8(x, colorplus->cga.displine);
colorplus->cga.sc = oldsc;
if (colorplus->cga.vc == colorplus->cga.crtc[7] && !colorplus->cga.sc)
colorplus->cga.cgastat |= 8;
colorplus->cga.displine++;
if (colorplus->cga.displine >= 360)
colorplus->cga.displine = 0;
} else {
timer_advance_u64(&colorplus->cga.timer, colorplus->cga.dispontime);
colorplus->cga.linepos = 0;
if (colorplus->cga.vsynctime) {
colorplus->cga.vsynctime--;
if (!colorplus->cga.vsynctime)
colorplus->cga.cgastat &= ~8;
}
if (colorplus->cga.sc == (colorplus->cga.crtc[11] & 31) || ((colorplus->cga.crtc[8] & 3) == 3 && colorplus->cga.sc == ((colorplus->cga.crtc[11] & 31) >> 1))) {
colorplus->cga.con = 0;
colorplus->cga.coff = 1;
}
if ((colorplus->cga.crtc[8] & 3) == 3 && colorplus->cga.sc == (colorplus->cga.crtc[9] >> 1))
colorplus->cga.maback = colorplus->cga.ma;
if (colorplus->cga.vadj) {
colorplus->cga.sc++;
colorplus->cga.sc &= 31;
colorplus->cga.ma = colorplus->cga.maback;
colorplus->cga.vadj--;
if (!colorplus->cga.vadj) {
colorplus->cga.cgadispon = 1;
colorplus->cga.ma = colorplus->cga.maback = (colorplus->cga.crtc[13] | (colorplus->cga.crtc[12] << 8)) & 0x3fff;
colorplus->cga.sc = 0;
}
} else if (colorplus->cga.sc == colorplus->cga.crtc[9]) {
colorplus->cga.maback = colorplus->cga.ma;
colorplus->cga.sc = 0;
oldvc = colorplus->cga.vc;
colorplus->cga.vc++;
colorplus->cga.vc &= 127;
if (colorplus->cga.vc == colorplus->cga.crtc[6])
colorplus->cga.cgadispon = 0;
if (oldvc == colorplus->cga.crtc[4]) {
colorplus->cga.vc = 0;
colorplus->cga.vadj = colorplus->cga.crtc[5];
if (!colorplus->cga.vadj)
colorplus->cga.cgadispon = 1;
if (!colorplus->cga.vadj)
colorplus->cga.ma = colorplus->cga.maback = (colorplus->cga.crtc[13] | (colorplus->cga.crtc[12] << 8)) & 0x3fff;
if ((colorplus->cga.crtc[10] & 0x60) == 0x20)
colorplus->cga.cursoron = 0;
else
colorplus->cga.cursoron = colorplus->cga.cgablink & 8;
}
if (colorplus->cga.vc == colorplus->cga.crtc[7]) {
colorplus->cga.cgadispon = 0;
colorplus->cga.displine = 0;
colorplus->cga.vsynctime = 16;
if (colorplus->cga.crtc[7]) {
if (colorplus->cga.cgamode & 1)
x = (colorplus->cga.crtc[1] << 3) + 16;
else
x = (colorplus->cga.crtc[1] << 4) + 16;
colorplus->cga.lastline++;
if (x != xsize || (colorplus->cga.lastline - colorplus->cga.firstline) != ysize) {
xsize = x;
ysize = colorplus->cga.lastline - colorplus->cga.firstline;
if (xsize < 64)
xsize = 656;
if (ysize < 32)
ysize = 200;
set_screen_size(xsize, (ysize << 1) + 16);
}
video_blit_memtoscreen(0, colorplus->cga.firstline - 4, xsize, (colorplus->cga.lastline - colorplus->cga.firstline) + 8);
frames++;
video_res_x = xsize - 16;
video_res_y = ysize;
if (colorplus->cga.cgamode & 1) {
video_res_x /= 8;
video_res_y /= colorplus->cga.crtc[9] + 1;
video_bpp = 0;
} else if (!(colorplus->cga.cgamode & 2)) {
video_res_x /= 16;
video_res_y /= colorplus->cga.crtc[9] + 1;
video_bpp = 0;
} else if (!(colorplus->cga.cgamode & 16)) {
video_res_x /= 2;
video_bpp = 2;
} else {
video_bpp = 1;
}
}
colorplus->cga.firstline = 1000;
colorplus->cga.lastline = 0;
colorplus->cga.cgablink++;
colorplus->cga.oddeven ^= 1;
}
} else {
colorplus->cga.sc++;
colorplus->cga.sc &= 31;
colorplus->cga.ma = colorplus->cga.maback;
}
if (colorplus->cga.cgadispon)
colorplus->cga.cgastat &= ~1;
if (colorplus->cga.sc == (colorplus->cga.crtc[10] & 31) || ((colorplus->cga.crtc[8] & 3) == 3 && colorplus->cga.sc == ((colorplus->cga.crtc[10] & 31) >> 1)))
colorplus->cga.con = 1;
if (colorplus->cga.cgadispon && (colorplus->cga.cgamode & 1)) {
for (x = 0; x < (colorplus->cga.crtc[1] << 1); x++)
colorplus->cga.charbuffer[x] = colorplus->cga.vram[((colorplus->cga.ma << 1) + x) & 0x3fff];
}
}
}
void
colorplus_init(colorplus_t *colorplus)
{
cga_init(&colorplus->cga);
}
void *
colorplus_standalone_init(UNUSED(const device_t *info))
{
int display_type;
colorplus_t *colorplus = malloc(sizeof(colorplus_t));
memset(colorplus, 0, sizeof(colorplus_t));
video_inform(VIDEO_FLAG_TYPE_CGA, &timing_colorplus);
/* Copied from the CGA init. Ideally this would be done by
* calling a helper function rather than duplicating code */
display_type = device_get_config_int("display_type");
colorplus->cga.composite = (display_type != CGA_RGB);
colorplus->cga.revision = device_get_config_int("composite_type");
colorplus->cga.snow_enabled = device_get_config_int("snow_enabled");
colorplus->cga.vram = malloc(0x8000);
cga_comp_init(colorplus->cga.revision);
timer_add(&colorplus->cga.timer, colorplus_poll, colorplus, 1);
mem_mapping_add(&colorplus->cga.mapping, 0xb8000, 0x08000, colorplus_read, NULL, NULL, colorplus_write, NULL, NULL, NULL, MEM_MAPPING_EXTERNAL, colorplus);
io_sethandler(0x03d0, 0x0010, colorplus_in, NULL, NULL, colorplus_out, NULL, NULL, colorplus);
lpt3_init(0x3BC);
return colorplus;
}
void
colorplus_close(void *priv)
{
colorplus_t *colorplus = (colorplus_t *) priv;
free(colorplus->cga.vram);
free(colorplus);
}
void
colorplus_speed_changed(void *priv)
{
colorplus_t *colorplus = (colorplus_t *) priv;
cga_recalctimings(&colorplus->cga);
}
static const device_config_t colorplus_config[] = {
// clang-format off
{
.name = "display_type",
.description = "Display type",
.type = CONFIG_SELECTION,
.default_int = CGA_RGB,
.selection = {
{
.description = "RGB",
.value = CGA_RGB
},
{
.description = "Composite",
.value = CGA_COMPOSITE
},
{
.description = ""
}
}
},
{
.name = "composite_type",
.description = "Composite type",
.type = CONFIG_SELECTION,
.default_int = COMPOSITE_OLD,
.selection = {
{
.description = "Old",
.value = COMPOSITE_OLD
},
{
.description = "New",
.value = COMPOSITE_NEW
},
{
.description = ""
}
}
},
{
.name = "snow_enabled",
.description = "Snow emulation",
.type = CONFIG_BINARY,
.default_int = 1
},
{
.type = CONFIG_END
}
// clang-format on
};
const device_t colorplus_device = {
.name = "Colorplus",
.internal_name = "plantronics",
.flags = DEVICE_ISA,
.local = 0,
.init = colorplus_standalone_init,
.close = colorplus_close,
.reset = NULL,
{ .available = NULL },
.speed_changed = colorplus_speed_changed,
.force_redraw = NULL,
.config = colorplus_config
};
``` | /content/code_sandbox/src/video/vid_colorplus.c | c | 2016-06-25T22:29:10 | 2024-08-16T19:09:21 | 86Box | 86Box/86Box | 2,616 | 5,087 |
```c
/*
* 86Box A hypervisor and IBM PC system emulator that specializes in
* running old operating systems and software designed for IBM
* PC systems and compatibles from 1981 through fairly recent
* system designs based on the PCI bus.
*
* This file is part of the 86Box distribution.
*
* Hercules InColor emulation.
*
*
*
* Authors: Sarah Walker, <path_to_url
* Miran Grca, <mgrca8@gmail.com>
*
*/
#include <stdio.h>
#include <stdint.h>
#include <stdlib.h>
#include <string.h>
#include <wchar.h>
#include <86box/86box.h>
#include <86box/io.h>
#include <86box/timer.h>
#include <86box/lpt.h>
#include <86box/pit.h>
#include <86box/mem.h>
#include <86box/rom.h>
#include <86box/device.h>
#include <86box/video.h>
#include <86box/plat_unused.h>
/* extended CRTC registers */
#define INCOLOR_CRTC_XMODE 20 /* xMode register */
#define INCOLOR_CRTC_UNDER 21 /* Underline */
#define INCOLOR_CRTC_OVER 22 /* Overstrike */
#define INCOLOR_CRTC_EXCEPT 23 /* Exception */
#define INCOLOR_CRTC_MASK 24 /* Plane display mask & write mask */
#define INCOLOR_CRTC_RWCTRL 25 /* Read/write control */
#define INCOLOR_CRTC_RWCOL 26 /* Read/write colour */
#define INCOLOR_CRTC_PROTECT 27 /* Latch protect */
#define INCOLOR_CRTC_PALETTE 28 /* Palette */
/* character width */
#define INCOLOR_CW ((dev->crtc[INCOLOR_CRTC_XMODE] & INCOLOR_XMODE_90COL) ? 8 : 9)
/* mode control register */
#define INCOLOR_CTRL_GRAPH 0x02
#define INCOLOR_CTRL_ENABLE 0x08
#define INCOLOR_CTRL_BLINK 0x20
#define INCOLOR_CTRL_PAGE1 0x80
/* CRTC status register */
#define INCOLOR_STATUS_HSYNC 0x01 /* horizontal sync */
#define INCOLOR_STATUS_LIGHT 0x02
#define INCOLOR_STATUS_VIDEO 0x08
#define INCOLOR_STATUS_ID 0x50 /* Card identification */
#define INCOLOR_STATUS_VSYNC 0x80 /* -vertical sync */
/* configuration switch register */
#define INCOLOR_CTRL2_GRAPH 0x01
#define INCOLOR_CTRL2_PAGE1 0x02
/* extended mode register */
#define INCOLOR_XMODE_RAMFONT 0x01
#define INCOLOR_XMODE_90COL 0x02
/* Read/write control */
#define INCOLOR_RWCTRL_WRMODE 0x30
#define INCOLOR_RWCTRL_POLARITY 0x40
/* exception register */
#define INCOLOR_EXCEPT_CURSOR 0x0F /* Cursor colour */
#define INCOLOR_EXCEPT_PALETTE 0x10 /* Enable palette register */
#define INCOLOR_EXCEPT_ALTATTR 0x20 /* Use alternate attributes */
/* Default palette */
static const uint8_t defpal[16] = {
0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07,
0x38, 0x39, 0x3A, 0x3B, 0x3C, 0x3D, 0x3E, 0x3F
};
/* Mapping of inks to RGB */
static const uint8_t init_rgb[64][3] = {
/* rgbRGB */
{0x00, 0x00, 0x00}, /* 000000 */
{ 0x00, 0x00, 0xaa}, /* 000001 */
{ 0x00, 0xaa, 0x00}, /* 000010 */
{ 0x00, 0xaa, 0xaa}, /* 000011 */
{ 0xaa, 0x00, 0x00}, /* 000100 */
{ 0xaa, 0x00, 0xaa}, /* 000101 */
{ 0xaa, 0xaa, 0x00}, /* 000110 */
{ 0xaa, 0xaa, 0xaa}, /* 000111 */
{ 0x00, 0x00, 0x55}, /* 001000 */
{ 0x00, 0x00, 0xff}, /* 001001 */
{ 0x00, 0xaa, 0x55}, /* 001010 */
{ 0x00, 0xaa, 0xff}, /* 001011 */
{ 0xaa, 0x00, 0x55}, /* 001100 */
{ 0xaa, 0x00, 0xff}, /* 001101 */
{ 0xaa, 0xaa, 0x55}, /* 001110 */
{ 0xaa, 0xaa, 0xff}, /* 001111 */
{ 0x00, 0x55, 0x00}, /* 010000 */
{ 0x00, 0x55, 0xaa}, /* 010001 */
{ 0x00, 0xff, 0x00}, /* 010010 */
{ 0x00, 0xff, 0xaa}, /* 010011 */
{ 0xaa, 0x55, 0x00}, /* 010100 */
{ 0xaa, 0x55, 0xaa}, /* 010101 */
{ 0xaa, 0xff, 0x00}, /* 010110 */
{ 0xaa, 0xff, 0xaa}, /* 010111 */
{ 0x00, 0x55, 0x55}, /* 011000 */
{ 0x00, 0x55, 0xff}, /* 011001 */
{ 0x00, 0xff, 0x55}, /* 011010 */
{ 0x00, 0xff, 0xff}, /* 011011 */
{ 0xaa, 0x55, 0x55}, /* 011100 */
{ 0xaa, 0x55, 0xff}, /* 011101 */
{ 0xaa, 0xff, 0x55}, /* 011110 */
{ 0xaa, 0xff, 0xff}, /* 011111 */
{ 0x55, 0x00, 0x00}, /* 100000 */
{ 0x55, 0x00, 0xaa}, /* 100001 */
{ 0x55, 0xaa, 0x00}, /* 100010 */
{ 0x55, 0xaa, 0xaa}, /* 100011 */
{ 0xff, 0x00, 0x00}, /* 100100 */
{ 0xff, 0x00, 0xaa}, /* 100101 */
{ 0xff, 0xaa, 0x00}, /* 100110 */
{ 0xff, 0xaa, 0xaa}, /* 100111 */
{ 0x55, 0x00, 0x55}, /* 101000 */
{ 0x55, 0x00, 0xff}, /* 101001 */
{ 0x55, 0xaa, 0x55}, /* 101010 */
{ 0x55, 0xaa, 0xff}, /* 101011 */
{ 0xff, 0x00, 0x55}, /* 101100 */
{ 0xff, 0x00, 0xff}, /* 101101 */
{ 0xff, 0xaa, 0x55}, /* 101110 */
{ 0xff, 0xaa, 0xff}, /* 101111 */
{ 0x55, 0x55, 0x00}, /* 110000 */
{ 0x55, 0x55, 0xaa}, /* 110001 */
{ 0x55, 0xff, 0x00}, /* 110010 */
{ 0x55, 0xff, 0xaa}, /* 110011 */
{ 0xff, 0x55, 0x00}, /* 110100 */
{ 0xff, 0x55, 0xaa}, /* 110101 */
{ 0xff, 0xff, 0x00}, /* 110110 */
{ 0xff, 0xff, 0xaa}, /* 110111 */
{ 0x55, 0x55, 0x55}, /* 111000 */
{ 0x55, 0x55, 0xff}, /* 111001 */
{ 0x55, 0xff, 0x55}, /* 111010 */
{ 0x55, 0xff, 0xff}, /* 111011 */
{ 0xff, 0x55, 0x55}, /* 111100 */
{ 0xff, 0x55, 0xff}, /* 111101 */
{ 0xff, 0xff, 0x55}, /* 111110 */
{ 0xff, 0xff, 0xff}, /* 111111 */
};
typedef struct {
mem_mapping_t mapping;
uint8_t crtc[32];
int crtcreg;
uint8_t ctrl, ctrl2, stat;
uint64_t dispontime, dispofftime;
pc_timer_t timer;
int firstline, lastline;
int linepos, displine;
int vc, sc;
uint16_t ma, maback;
int con, coff, cursoron;
int dispon, blink;
int vsynctime;
int vadj;
uint8_t palette[16]; /* EGA-style 16 -> 64 palette registers */
uint8_t palette_idx; /* Palette write index */
uint8_t latch[4]; /* Memory read/write latches */
uint32_t rgb[64];
uint8_t *vram;
} incolor_t;
static video_timings_t timing_incolor = { .type = VIDEO_ISA, .write_b = 8, .write_w = 16, .write_l = 32, .read_b = 8, .read_w = 16, .read_l = 32 };
static void
recalc_timings(incolor_t *dev)
{
double disptime;
double _dispontime;
double _dispofftime;
disptime = dev->crtc[0] + 1;
_dispontime = dev->crtc[1];
_dispofftime = disptime - _dispontime;
_dispontime *= HERCCONST;
_dispofftime *= HERCCONST;
dev->dispontime = (uint64_t) (_dispontime);
dev->dispofftime = (uint64_t) (_dispofftime);
}
static void
incolor_out(uint16_t port, uint8_t val, void *priv)
{
incolor_t *dev = (incolor_t *) priv;
uint8_t old;
switch (port) {
case 0x3b0:
case 0x3b2:
case 0x3b4:
case 0x3b6:
dev->crtcreg = val & 31;
return;
case 0x3b1:
case 0x3b3:
case 0x3b5:
case 0x3b7:
if (dev->crtcreg > 28)
return;
/* Palette load register */
if (dev->crtcreg == INCOLOR_CRTC_PALETTE) {
dev->palette[dev->palette_idx % 16] = val;
++dev->palette_idx;
}
old = dev->crtc[dev->crtcreg];
dev->crtc[dev->crtcreg] = val;
if (dev->crtc[10] == 6 && dev->crtc[11] == 7) {
/*Fix for Generic Turbo XT BIOS,
* which sets up cursor registers wrong*/
dev->crtc[10] = 0xb;
dev->crtc[11] = 0xc;
}
if (old ^ val)
recalc_timings(dev);
return;
case 0x3b8:
old = dev->ctrl;
dev->ctrl = val;
if (old ^ val)
recalc_timings(dev);
return;
case 0x3bf:
dev->ctrl2 = val;
if (val & 2)
mem_mapping_set_addr(&dev->mapping, 0xb0000, 0x10000);
else
mem_mapping_set_addr(&dev->mapping, 0xb0000, 0x08000);
return;
default:
break;
}
}
static uint8_t
incolor_in(uint16_t port, void *priv)
{
incolor_t *dev = (incolor_t *) priv;
uint8_t ret = 0xff;
switch (port) {
case 0x3b0:
case 0x3b2:
case 0x3b4:
case 0x3b6:
ret = dev->crtcreg;
break;
case 0x3b1:
case 0x3b3:
case 0x3b5:
case 0x3b7:
if (dev->crtcreg > 28)
break;
dev->palette_idx = 0; /* Read resets the palette index */
ret = dev->crtc[dev->crtcreg];
break;
case 0x3ba:
/* 0x50: InColor card identity */
ret = (dev->stat & 0xf) | ((dev->stat & 8) << 4) | 0x50;
break;
default:
break;
}
return ret;
}
static void
incolor_write(uint32_t addr, uint8_t val, void *priv)
{
incolor_t *dev = (incolor_t *) priv;
unsigned char wmask = dev->crtc[INCOLOR_CRTC_MASK];
unsigned char wmode = dev->crtc[INCOLOR_CRTC_RWCTRL] & INCOLOR_RWCTRL_WRMODE;
unsigned char fg = dev->crtc[INCOLOR_CRTC_RWCOL] & 0x0F;
unsigned char bg = (dev->crtc[INCOLOR_CRTC_RWCOL] >> 4) & 0x0F;
unsigned char w = 0;
unsigned char pmask; /* Mask of plane within colour value */
unsigned char latch;
addr &= 0xffff;
/* In text mode, writes to the bottom 16k always touch all 4 planes */
if (!(dev->ctrl & INCOLOR_CTRL_GRAPH) && addr < 0x4000) {
dev->vram[addr] = val;
return;
}
/* There are four write modes:
* 0: 1 => foreground, 0 => background
* 1: 1 => foreground, 0 => source latch
* 2: 1 => source latch, 0 => background
* 3: 1 => source latch, 0 => ~source latch
*/
pmask = 1;
for (uint8_t plane = 0; plane < 4; pmask <<= 1, wmask >>= 1, addr += 0x10000, plane++) {
if (wmask & 0x10) /* Ignore writes to selected plane */
{
continue;
}
latch = dev->latch[plane];
for (unsigned char vmask = 0x80 /* Mask of bit within byte */; vmask != 0; vmask >>= 1) {
switch (wmode) {
case 0x00:
if (val & vmask)
w = (fg & pmask);
else
w = (bg & pmask);
break;
case 0x10:
if (val & vmask)
w = (fg & pmask);
else
w = (latch & vmask);
break;
case 0x20:
if (val & vmask)
w = (latch & vmask);
else
w = (bg & pmask);
break;
case 0x30:
if (val & vmask)
w = (latch & vmask);
else
w = ((~latch) & vmask);
break;
default:
break;
}
/* w is nonzero to write a 1, zero to write a 0 */
if (w)
dev->vram[addr] |= vmask;
else
dev->vram[addr] &= ~vmask;
}
}
}
static uint8_t
incolor_read(uint32_t addr, void *priv)
{
incolor_t *dev = (incolor_t *) priv;
unsigned plane;
unsigned char lp = dev->crtc[INCOLOR_CRTC_PROTECT];
unsigned char value = 0;
unsigned char dc; /* "don't care" register */
unsigned char bg; /* background colour */
unsigned char fg;
unsigned char pmask;
addr &= 0xffff;
/* Read the four planes into latches */
for (plane = 0; plane < 4; plane++, addr += 0x10000) {
dev->latch[plane] &= lp;
dev->latch[plane] |= (dev->vram[addr] & ~lp);
}
addr &= 0xffff;
/* In text mode, reads from the bottom 16k assume all planes have
* the same contents */
if (!(dev->ctrl & INCOLOR_CTRL_GRAPH) && addr < 0x4000) {
return dev->latch[0];
}
/* For each pixel, work out if its colour matches the background */
for (unsigned char mask = 0x80; mask != 0; mask >>= 1) {
fg = 0;
dc = dev->crtc[INCOLOR_CRTC_RWCTRL] & 0x0F;
bg = (dev->crtc[INCOLOR_CRTC_RWCOL] >> 4) & 0x0F;
for (plane = 0, pmask = 1; plane < 4; plane++, pmask <<= 1) {
if (dc & pmask) {
fg |= (bg & pmask);
} else if (dev->latch[plane] & mask) {
fg |= pmask;
}
}
if (bg == fg)
value |= mask;
}
if (dev->crtc[INCOLOR_CRTC_RWCTRL] & INCOLOR_RWCTRL_POLARITY)
value = ~value;
return value;
}
static void
draw_char_rom(incolor_t *dev, int x, uint8_t chr, uint8_t attr)
{
int elg;
int blk;
unsigned ull;
unsigned val;
unsigned ifg;
unsigned ibg;
const unsigned char *fnt;
uint32_t fg;
uint32_t bg;
int cw = INCOLOR_CW;
blk = 0;
if (dev->ctrl & INCOLOR_CTRL_BLINK) {
if (attr & 0x80) {
blk = (dev->blink & 16);
}
attr &= 0x7f;
}
if (dev->crtc[INCOLOR_CRTC_EXCEPT] & INCOLOR_EXCEPT_ALTATTR) {
/* MDA-compatible attributes */
ibg = 0;
ifg = 7;
if ((attr & 0x77) == 0x70) /* Invert */
{
ifg = 0;
ibg = 7;
}
if (attr & 8) {
ifg |= 8; /* High intensity FG */
}
if (attr & 0x80) {
ibg |= 8; /* High intensity BG */
}
if ((attr & 0x77) == 0) /* Blank */
{
ifg = ibg;
}
ull = ((attr & 0x07) == 1) ? 13 : 0xffff;
} else {
/* CGA-compatible attributes */
ull = 0xffff;
ifg = attr & 0x0F;
ibg = (attr >> 4) & 0x0F;
}
if (dev->crtc[INCOLOR_CRTC_EXCEPT] & INCOLOR_EXCEPT_PALETTE) {
fg = dev->rgb[dev->palette[ifg]];
bg = dev->rgb[dev->palette[ibg]];
} else {
fg = dev->rgb[defpal[ifg]];
bg = dev->rgb[defpal[ibg]];
}
/* ELG set to stretch 8px character to 9px */
if (dev->crtc[INCOLOR_CRTC_XMODE] & INCOLOR_XMODE_90COL) {
elg = 0;
} else {
elg = ((chr >= 0xc0) && (chr <= 0xdf));
}
fnt = &(fontdatm[chr][dev->sc]);
if (blk) {
val = 0x000; /* Blinking, draw all background */
} else if (dev->sc == ull) {
val = 0x1ff; /* Underscore, draw all foreground */
} else {
val = fnt[0] << 1;
if (elg) {
val |= (val >> 1) & 1;
}
}
for (int i = 0; i < cw; i++) {
buffer32->line[dev->displine][x * cw + i] = (val & 0x100) ? fg : bg;
val = val << 1;
}
}
static void
draw_char_ram4(incolor_t *dev, int x, uint8_t chr, uint8_t attr)
{
int elg;
int blk;
unsigned ull;
unsigned val[4];
unsigned ifg;
unsigned ibg;
unsigned cfg;
unsigned pmask;
const unsigned char *fnt;
uint32_t fg;
int cw = INCOLOR_CW;
int blink = dev->ctrl & INCOLOR_CTRL_BLINK;
int altattr = dev->crtc[INCOLOR_CRTC_EXCEPT] & INCOLOR_EXCEPT_ALTATTR;
int palette = dev->crtc[INCOLOR_CRTC_EXCEPT] & INCOLOR_EXCEPT_PALETTE;
blk = 0;
if (blink) {
if (attr & 0x80) {
blk = (dev->blink & 16);
}
attr &= 0x7f;
}
if (altattr) {
/* MDA-compatible attributes */
ibg = 0;
ifg = 7;
if ((attr & 0x77) == 0x70) /* Invert */
{
ifg = 0;
ibg = 7;
}
if (attr & 8) {
ifg |= 8; /* High intensity FG */
}
if (attr & 0x80) {
ibg |= 8; /* High intensity BG */
}
if ((attr & 0x77) == 0) /* Blank */
{
ifg = ibg;
}
ull = ((attr & 0x07) == 1) ? 13 : 0xffff;
} else {
/* CGA-compatible attributes */
ull = 0xffff;
ifg = attr & 0x0F;
ibg = (attr >> 4) & 0x0F;
}
if (dev->crtc[INCOLOR_CRTC_XMODE] & INCOLOR_XMODE_90COL) {
elg = 0;
} else {
elg = ((chr >= 0xc0) && (chr <= 0xdf));
}
fnt = dev->vram + 0x4000 + 16 * chr + dev->sc;
if (blk) {
/* Blinking, draw all background */
val[0] = val[1] = val[2] = val[3] = 0x000;
} else if (dev->sc == ull) {
/* Underscore, draw all foreground */
val[0] = val[1] = val[2] = val[3] = 0x1ff;
} else {
val[0] = fnt[0x00000] << 1;
val[1] = fnt[0x10000] << 1;
val[2] = fnt[0x20000] << 1;
val[3] = fnt[0x30000] << 1;
if (elg) {
val[0] |= (val[0] >> 1) & 1;
val[1] |= (val[1] >> 1) & 1;
val[2] |= (val[2] >> 1) & 1;
val[3] |= (val[3] >> 1) & 1;
}
}
for (int i = 0; i < cw; i++) {
/* Generate pixel colour */
cfg = 0;
pmask = 1;
for (uint8_t plane = 0; plane < 4; plane++, pmask = pmask << 1) {
if (val[plane] & 0x100)
cfg |= (ifg & pmask);
else
cfg |= (ibg & pmask);
}
/* cfg = colour of foreground pixels */
if (altattr && (attr & 0x77) == 0)
cfg = ibg; /* 'blank' attribute */
if (palette) {
fg = dev->rgb[dev->palette[cfg]];
} else {
fg = dev->rgb[defpal[cfg]];
}
buffer32->line[dev->displine][x * cw + i] = fg;
val[0] = val[0] << 1;
val[1] = val[1] << 1;
val[2] = val[2] << 1;
val[3] = val[3] << 1;
}
}
static void
draw_char_ram48(incolor_t *dev, int x, uint8_t chr, uint8_t attr)
{
int elg;
int blk;
int ul;
int ol;
int bld;
unsigned ull;
unsigned oll;
unsigned ulc = 0;
unsigned olc = 0;
unsigned val[4];
unsigned ifg = 0;
unsigned ibg;
unsigned cfg;
unsigned pmask;
const unsigned char *fnt;
uint32_t fg;
int cw = INCOLOR_CW;
int blink = dev->ctrl & INCOLOR_CTRL_BLINK;
int altattr = dev->crtc[INCOLOR_CRTC_EXCEPT] & INCOLOR_EXCEPT_ALTATTR;
int palette = dev->crtc[INCOLOR_CRTC_EXCEPT] & INCOLOR_EXCEPT_PALETTE;
int font = (attr & 0x0F);
if (font >= 12)
font &= 7;
blk = 0;
if (blink && altattr) {
if (attr & 0x40) {
blk = (dev->blink & 16);
}
attr &= 0x7f;
}
if (altattr) {
/* MDA-compatible attributes */
if (blink) {
ibg = (attr & 0x80) ? 8 : 0;
bld = 0;
ol = (attr & 0x20) ? 1 : 0;
ul = (attr & 0x10) ? 1 : 0;
} else {
bld = (attr & 0x80) ? 1 : 0;
ibg = (attr & 0x40) ? 0x0F : 0;
ol = (attr & 0x20) ? 1 : 0;
ul = (attr & 0x10) ? 1 : 0;
}
} else {
/* CGA-compatible attributes */
ibg = 0;
ifg = (attr >> 4) & 0x0F;
ol = 0;
ul = 0;
bld = 0;
}
if (ul) {
ull = dev->crtc[INCOLOR_CRTC_UNDER] & 0x0F;
ulc = (dev->crtc[INCOLOR_CRTC_UNDER] >> 4) & 0x0F;
if (ulc == 0)
ulc = 7;
} else {
ull = 0xFFFF;
}
if (ol) {
oll = dev->crtc[INCOLOR_CRTC_OVER] & 0x0F;
olc = (dev->crtc[INCOLOR_CRTC_OVER] >> 4) & 0x0F;
if (olc == 0)
olc = 7;
} else {
oll = 0xFFFF;
}
if (dev->crtc[INCOLOR_CRTC_XMODE] & INCOLOR_XMODE_90COL) {
elg = 0;
} else {
elg = ((chr >= 0xc0) && (chr <= 0xdf));
}
fnt = dev->vram + 0x4000 + 16 * chr + 4096 * font + dev->sc;
if (blk) {
/* Blinking, draw all background */
val[0] = val[1] = val[2] = val[3] = 0x000;
} else if (dev->sc == ull) {
/* Underscore, draw all foreground */
val[0] = val[1] = val[2] = val[3] = 0x1ff;
} else {
val[0] = fnt[0x00000] << 1;
val[1] = fnt[0x10000] << 1;
val[2] = fnt[0x20000] << 1;
val[3] = fnt[0x30000] << 1;
if (elg) {
val[0] |= (val[0] >> 1) & 1;
val[1] |= (val[1] >> 1) & 1;
val[2] |= (val[2] >> 1) & 1;
val[3] |= (val[3] >> 1) & 1;
}
if (bld) {
val[0] |= (val[0] >> 1);
val[1] |= (val[1] >> 1);
val[2] |= (val[2] >> 1);
val[3] |= (val[3] >> 1);
}
}
for (int i = 0; i < cw; i++) {
/* Generate pixel colour */
cfg = 0;
pmask = 1;
if (dev->sc == oll) {
cfg = olc ^ ibg; /* Strikethrough */
} else if (dev->sc == ull) {
cfg = ulc ^ ibg; /* Underline */
} else {
for (uint8_t plane = 0; plane < 4; plane++, pmask = pmask << 1) {
if (val[plane] & 0x100) {
if (altattr)
cfg |= ((~ibg) & pmask);
else
cfg |= ((~ifg) & pmask);
} else if (altattr)
cfg |= (ibg & pmask);
}
}
if (palette) {
fg = dev->rgb[dev->palette[cfg]];
} else {
fg = dev->rgb[defpal[cfg]];
}
buffer32->line[dev->displine][x * cw + i] = fg;
val[0] = val[0] << 1;
val[1] = val[1] << 1;
val[2] = val[2] << 1;
val[3] = val[3] << 1;
}
}
static void
text_line(incolor_t *dev, uint16_t ca)
{
int drawcursor;
uint8_t chr;
uint8_t attr;
uint32_t col;
for (uint8_t x = 0; x < dev->crtc[1]; x++) {
if (dev->ctrl & 8) {
chr = dev->vram[(dev->ma << 1) & 0x3fff];
attr = dev->vram[((dev->ma << 1) + 1) & 0x3fff];
} else
chr = attr = 0;
drawcursor = ((dev->ma == ca) && dev->con && dev->cursoron);
switch (dev->crtc[INCOLOR_CRTC_XMODE] & 5) {
case 0:
case 4: /* ROM font */
draw_char_rom(dev, x, chr, attr);
break;
case 1: /* 4k RAMfont */
draw_char_ram4(dev, x, chr, attr);
break;
case 5: /* 48k RAMfont */
draw_char_ram48(dev, x, chr, attr);
break;
default:
break;
}
++dev->ma;
if (drawcursor) {
int cw = INCOLOR_CW;
uint8_t ink = dev->crtc[INCOLOR_CRTC_EXCEPT] & INCOLOR_EXCEPT_CURSOR;
if (ink == 0)
ink = (attr & 0x08) | 7;
/* In MDA-compatible mode, cursor brightness comes from
* background */
if (dev->crtc[INCOLOR_CRTC_EXCEPT] & INCOLOR_EXCEPT_ALTATTR) {
ink = (attr & 0x08) | (ink & 7);
}
if (dev->crtc[INCOLOR_CRTC_EXCEPT] & INCOLOR_EXCEPT_PALETTE) {
col = dev->rgb[dev->palette[ink]];
} else {
col = dev->rgb[defpal[ink]];
}
for (int c = 0; c < cw; c++) {
buffer32->line[dev->displine][x * cw + c] = col;
}
}
}
}
static void
graphics_line(incolor_t *dev)
{
uint8_t mask;
uint16_t ca;
int plane;
int col;
uint8_t ink;
uint16_t val[4];
/* Graphics mode. */
ca = (dev->sc & 3) * 0x2000;
if ((dev->ctrl & INCOLOR_CTRL_PAGE1) && (dev->ctrl2 & INCOLOR_CTRL2_PAGE1))
ca += 0x8000;
for (uint8_t x = 0; x < dev->crtc[1]; x++) {
mask = dev->crtc[INCOLOR_CRTC_MASK]; /* Planes to display */
for (plane = 0; plane < 4; plane++, mask = mask >> 1) {
if (dev->ctrl & 8) {
if (mask & 1)
val[plane] = (dev->vram[((dev->ma << 1) & 0x1fff) + ca + 0x10000 * plane] << 8) | dev->vram[((dev->ma << 1) & 0x1fff) + ca + 0x10000 * plane + 1];
else
val[plane] = 0;
} else
val[plane] = 0;
}
dev->ma++;
for (uint8_t c = 0; c < 16; c++) {
ink = 0;
for (plane = 0; plane < 4; plane++) {
ink = ink >> 1;
if (val[plane] & 0x8000)
ink |= 8;
val[plane] = val[plane] << 1;
}
/* Is palette in use? */
if (dev->crtc[INCOLOR_CRTC_EXCEPT] & INCOLOR_EXCEPT_PALETTE)
col = dev->palette[ink];
else
col = defpal[ink];
buffer32->line[dev->displine][(x << 4) + c] = dev->rgb[col];
}
}
}
static void
incolor_poll(void *priv)
{
incolor_t *dev = (incolor_t *) priv;
uint16_t ca = (dev->crtc[15] | (dev->crtc[14] << 8)) & 0x3fff;
int x;
int oldvc;
int oldsc;
int cw = INCOLOR_CW;
if (!dev->linepos) {
timer_advance_u64(&dev->timer, dev->dispofftime);
dev->stat |= 1;
dev->linepos = 1;
oldsc = dev->sc;
if ((dev->crtc[8] & 3) == 3)
dev->sc = (dev->sc << 1) & 7;
if (dev->dispon) {
if (dev->displine < dev->firstline) {
dev->firstline = dev->displine;
video_wait_for_buffer();
}
dev->lastline = dev->displine;
if ((dev->ctrl & INCOLOR_CTRL_GRAPH) && (dev->ctrl2 & INCOLOR_CTRL2_GRAPH))
graphics_line(dev);
else
text_line(dev, ca);
}
dev->sc = oldsc;
if (dev->vc == dev->crtc[7] && !dev->sc)
dev->stat |= 8;
dev->displine++;
if (dev->displine >= 500)
dev->displine = 0;
} else {
timer_advance_u64(&dev->timer, dev->dispontime);
if (dev->dispon)
dev->stat &= ~1;
dev->linepos = 0;
if (dev->vsynctime) {
dev->vsynctime--;
if (!dev->vsynctime)
dev->stat &= ~8;
}
if (dev->sc == (dev->crtc[11] & 31) || ((dev->crtc[8] & 3) == 3 && dev->sc == ((dev->crtc[11] & 31) >> 1))) {
dev->con = 0;
dev->coff = 1;
}
if (dev->vadj) {
dev->sc++;
dev->sc &= 31;
dev->ma = dev->maback;
dev->vadj--;
if (!dev->vadj) {
dev->dispon = 1;
dev->ma = dev->maback = (dev->crtc[13] | (dev->crtc[12] << 8)) & 0x3fff;
dev->sc = 0;
}
} else if (dev->sc == dev->crtc[9] || ((dev->crtc[8] & 3) == 3 && dev->sc == (dev->crtc[9] >> 1))) {
dev->maback = dev->ma;
dev->sc = 0;
oldvc = dev->vc;
dev->vc++;
dev->vc &= 127;
if (dev->vc == dev->crtc[6])
dev->dispon = 0;
if (oldvc == dev->crtc[4]) {
dev->vc = 0;
dev->vadj = dev->crtc[5];
if (!dev->vadj)
dev->dispon = 1;
if (!dev->vadj)
dev->ma = dev->maback = (dev->crtc[13] | (dev->crtc[12] << 8)) & 0x3fff;
if ((dev->crtc[10] & 0x60) == 0x20)
dev->cursoron = 0;
else
dev->cursoron = dev->blink & 16;
}
if (dev->vc == dev->crtc[7]) {
dev->dispon = 0;
dev->displine = 0;
dev->vsynctime = 16;
if (dev->crtc[7]) {
if ((dev->ctrl & INCOLOR_CTRL_GRAPH) && (dev->ctrl2 & INCOLOR_CTRL2_GRAPH))
x = dev->crtc[1] << 4;
else
x = dev->crtc[1] * cw;
dev->lastline++;
if ((dev->ctrl & 8) && ((x != xsize) || ((dev->lastline - dev->firstline) != ysize) || video_force_resize_get())) {
xsize = x;
ysize = dev->lastline - dev->firstline;
if (xsize < 64)
xsize = 656;
if (ysize < 32)
ysize = 200;
set_screen_size(xsize, ysize);
if (video_force_resize_get())
video_force_resize_set(0);
}
video_blit_memtoscreen(0, dev->firstline, xsize, dev->lastline - dev->firstline);
frames++;
if ((dev->ctrl & INCOLOR_CTRL_GRAPH) && (dev->ctrl2 & INCOLOR_CTRL2_GRAPH)) {
video_res_x = dev->crtc[1] * 16;
video_res_y = dev->crtc[6] * 4;
video_bpp = 1;
} else {
video_res_x = dev->crtc[1];
video_res_y = dev->crtc[6];
video_bpp = 0;
}
}
dev->firstline = 1000;
dev->lastline = 0;
dev->blink++;
}
} else {
dev->sc++;
dev->sc &= 31;
dev->ma = dev->maback;
}
if (dev->sc == (dev->crtc[10] & 31) || ((dev->crtc[8] & 3) == 3 && dev->sc == ((dev->crtc[10] & 31) >> 1)))
dev->con = 1;
}
}
static void *
incolor_init(UNUSED(const device_t *info))
{
incolor_t *dev;
int c;
dev = (incolor_t *) malloc(sizeof(incolor_t));
memset(dev, 0x00, sizeof(incolor_t));
dev->vram = (uint8_t *) malloc(0x40000); /* 4 planes of 64k */
timer_add(&dev->timer, incolor_poll, dev, 1);
mem_mapping_add(&dev->mapping, 0xb0000, 0x08000,
incolor_read, NULL, NULL, incolor_write, NULL, NULL,
NULL, MEM_MAPPING_EXTERNAL, dev);
io_sethandler(0x03b0, 16,
incolor_in, NULL, NULL, incolor_out, NULL, NULL, dev);
for (c = 0; c < 64; c++) {
dev->rgb[c] = makecol32(init_rgb[c][0], init_rgb[c][1], init_rgb[c][2]);
}
/* Initialise CRTC regs to safe values */
dev->crtc[INCOLOR_CRTC_MASK] = 0x0F; /* All planes displayed */
dev->crtc[INCOLOR_CRTC_RWCTRL] = INCOLOR_RWCTRL_POLARITY;
dev->crtc[INCOLOR_CRTC_RWCOL] = 0x0F; /* White on black */
dev->crtc[INCOLOR_CRTC_EXCEPT] = INCOLOR_EXCEPT_ALTATTR;
for (c = 0; c < 16; c++)
dev->palette[c] = defpal[c];
dev->palette_idx = 0;
video_inform(VIDEO_FLAG_TYPE_MDA, &timing_incolor);
/* Force the LPT3 port to be enabled. */
lpt3_init(0x3BC);
return dev;
}
static void
incolor_close(void *priv)
{
incolor_t *dev = (incolor_t *) priv;
if (!dev)
return;
if (dev->vram)
free(dev->vram);
free(dev);
}
static void
speed_changed(void *priv)
{
incolor_t *dev = (incolor_t *) priv;
recalc_timings(dev);
}
const device_t incolor_device = {
.name = "Hercules InColor",
.internal_name = "incolor",
.flags = DEVICE_ISA,
.local = 0,
.init = incolor_init,
.close = incolor_close,
.reset = NULL,
{ .available = NULL },
.speed_changed = speed_changed,
.force_redraw = NULL,
.config = NULL
};
``` | /content/code_sandbox/src/video/vid_incolor.c | c | 2016-06-25T22:29:10 | 2024-08-16T19:09:21 | 86Box | 86Box/86Box | 2,616 | 10,335 |
```c
/*
* 86Box A hypervisor and IBM PC system emulator that specializes in
* running old operating systems and software designed for IBM
* PC systems and compatibles from 1981 through fairly recent
* system designs based on the PCI bus.
*
* This file is part of the 86Box distribution.
*
* Video 7 VGA 1024i emulation.
*
*
*
* Authors: Sarah Walker, <path_to_url
* Miran Grca, <mgrca8@gmail.com>
*
*/
#include <stdarg.h>
#include <stdio.h>
#include <stdint.h>
#include <string.h>
#include <stdlib.h>
#include <wchar.h>
#define HAVE_STDARG_H
#include <86box/86box.h>
#include "cpu.h"
#include <86box/io.h>
#include <86box/mca.h>
#include <86box/mem.h>
#include <86box/timer.h>
#include <86box/pic.h>
#include <86box/rom.h>
#include <86box/device.h>
#include <86box/video.h>
#include <86box/vid_svga.h>
#include <86box/vid_svga_render.h>
#include <86box/plat_fallthrough.h>
#include <86box/plat_unused.h>
typedef struct ht216_t {
svga_t svga;
mem_mapping_t linear_mapping;
rom_t bios_rom;
uint32_t vram_mask, linear_base;
uint8_t adjust_cursor, monitor_type;
int ext_reg_enable;
int isabus;
int mca;
uint8_t read_bank_reg[2], write_bank_reg[2];
uint16_t id, misc;
uint32_t read_banks[2], write_banks[2];
uint8_t bg_latch[8];
uint8_t fg_latch[4];
uint8_t bg_plane_sel, fg_plane_sel;
uint8_t ht_regs[256];
uint8_t extensions, reg_3cb;
uint8_t pos_regs[8];
} ht216_t;
#define HT_MISC_PAGE_SEL (1 << 5)
/*Shifts CPU VRAM read address by 3 bits, for use with fat pixel color expansion*/
#define HT_REG_C8_MOVSB (1 << 0)
#define HT_REG_C8_E256 (1 << 4)
#define HT_REG_C8_XLAM (1 << 6)
#define HT_REG_CD_P8PCEXP (1 << 0)
#define HT_REG_CD_FP8PCEXP (1 << 1)
#define HT_REG_CD_BMSKSL (3 << 2)
#define HT_REG_CD_RMWMDE (1 << 5)
/*Use GDC data rotate as offset when reading VRAM data into latches*/
#define HT_REG_CD_ASTODE (1 << 6)
#define HT_REG_CD_EXALU (1 << 7)
#define HT_REG_E0_SBAE (1 << 7)
#define HT_REG_F9_XPSEL (1 << 0)
/*Enables A[14:15] of VRAM address in chain-4 modes*/
#define HT_REG_FC_ECOLRE (1 << 2)
#define HT_REG_FE_FBRC (1 << 1)
#define HT_REG_FE_FBMC (3 << 2)
#define HT_REG_FE_FBRSL (3 << 4)
void ht216_remap(ht216_t *ht216);
void ht216_out(uint16_t addr, uint8_t val, void *priv);
uint8_t ht216_in(uint16_t addr, void *priv);
#define BIOS_G2_GC205_PATH "roms/video/video7/BIOS.BIN"
#define BIOS_VIDEO7_VGA_1024I_PATH "roms/video/video7/Video Seven VGA 1024i - BIOS - v2.19 - 435-0062-05 - U17 - 27C256.BIN"
#define BIOS_RADIUS_SVGA_MULTIVIEW_PATH "roms/video/video7/U18.BIN"
#define BIOS_HT216_32_PATH "roms/video/video7/HT21632.BIN"
static video_timings_t timing_v7vga_isa = { .type = VIDEO_ISA, .write_b = 3, .write_w = 3, .write_l = 6, .read_b = 5, .read_w = 5, .read_l = 10 };
static video_timings_t timing_v7vga_mca = { .type = VIDEO_MCA, .write_b = 4, .write_w = 5, .write_l = 10, .read_b = 5, .read_w = 5, .read_l = 10 };
static video_timings_t timing_v7vga_vlb = { .type = VIDEO_BUS, .write_b = 5, .write_w = 5, .write_l = 9, .read_b = 20, .read_w = 20, .read_l = 30 };
#ifdef ENABLE_HT216_LOG
int ht216_do_log = ENABLE_HT216_LOG;
static void
ht216_log(const char *fmt, ...)
{
va_list ap;
if (ht216_do_log) {
va_start(ap, fmt);
pclog_ex(fmt, ap);
va_end(ap);
}
}
#else
# define ht216_log(fmt, ...)
#endif
/*Remap address for chain-4/doubleword style layout*/
static __inline uint32_t
dword_remap(svga_t *svga, uint32_t in_addr)
{
if (svga->packed_chain4)
return in_addr;
return ((in_addr & 0xfffc) << 2) | ((in_addr & 0x30000) >> 14) | (in_addr & ~0x3ffff);
}
static void
ht216_recalc_bank_regs(ht216_t *ht216, int mode)
{
const svga_t *svga = &ht216->svga;
if (mode) {
ht216->read_bank_reg[0] = ht216->ht_regs[0xe8];
ht216->write_bank_reg[0] = ht216->ht_regs[0xe8];
ht216->read_bank_reg[1] = ht216->ht_regs[0xe9];
ht216->write_bank_reg[1] = ht216->ht_regs[0xe9];
} else {
ht216->read_bank_reg[0] = ((ht216->ht_regs[0xf6] & 0xc) << 4);
ht216->read_bank_reg[1] = ((ht216->ht_regs[0xf6] & 0xc) << 4);
ht216->write_bank_reg[0] = ((ht216->ht_regs[0xf6] & 0x3) << 6);
ht216->write_bank_reg[1] = ((ht216->ht_regs[0xf6] & 0x3) << 6);
if (svga->packed_chain4 || (ht216->ht_regs[0xfc] & HT_REG_FC_ECOLRE)) {
ht216->read_bank_reg[0] |= (ht216->misc & 0x20);
ht216->read_bank_reg[1] |= (ht216->misc & 0x20);
ht216->write_bank_reg[0] |= (ht216->misc & 0x20);
ht216->write_bank_reg[1] |= (ht216->misc & 0x20);
}
if (svga->packed_chain4 || ((ht216->ht_regs[0xfc] & 0x06) == 0x04)) {
ht216->read_bank_reg[0] |= ((ht216->ht_regs[0xf9] & 1) << 4);
ht216->read_bank_reg[1] |= ((ht216->ht_regs[0xf9] & 1) << 4);
ht216->write_bank_reg[0] |= ((ht216->ht_regs[0xf9] & 1) << 4);
ht216->write_bank_reg[1] |= ((ht216->ht_regs[0xf9] & 1) << 4);
}
}
}
void
ht216_out(uint16_t addr, uint8_t val, void *priv)
{
ht216_t *ht216 = (ht216_t *) priv;
svga_t *svga = &ht216->svga;
uint8_t old;
ht216_log("ht216 %i out %04X %02X %04X:%04X\n", svga->miscout & 1, addr, val, CS, cpu_state.pc);
if (((addr & 0xfff0) == 0x3d0 || (addr & 0xfff0) == 0x3b0) && !(svga->miscout & 1))
addr ^= 0x60;
switch (addr) {
case 0x3c2:
/*Bit 17 of the display memory address, only active on odd/even modes, has no effect on graphics modes.*/
ht216->misc = val;
svga->miscout = val;
ht216_log("HT216 misc val = %02x, mode = 0, chain4 = %x\n", val, svga->chain4);
ht216_recalc_bank_regs(ht216, 0);
ht216_remap(ht216);
svga_recalctimings(svga);
break;
case 0x3c4:
svga->seqaddr = val;
break;
case 0x3c5:
if (svga->seqaddr == 4) {
svga->chain2_write = !(val & 4);
svga->chain4 = val & 8;
ht216_remap(ht216);
} else if (svga->seqaddr == 6) {
if (val == 0xea)
ht216->ext_reg_enable = 1;
else if (val == 0xae)
ht216->ext_reg_enable = 0;
#ifdef ENABLE_HT216_LOG
/* Functionality to output to the console a dump of all registers for debugging purposes. */
} else if (svga->seqaddr == 0x7f) {
ht216_log(" 8 | 0 1 2 3 4 5 6 7 8 9 A B C D E F\n");
ht216_log("----+-------------------------------------------------\n");
ht216_log(" 8 | %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X\n",
ht216->ht_regs[0x80], ht216->ht_regs[0x81], ht216->ht_regs[0x82], ht216->ht_regs[0x83],
ht216->ht_regs[0x84], ht216->ht_regs[0x85], ht216->ht_regs[0x86], ht216->ht_regs[0x87],
ht216->ht_regs[0x88], ht216->ht_regs[0x89], ht216->ht_regs[0x8a], ht216->ht_regs[0x8b],
ht216->ht_regs[0x8c], ht216->ht_regs[0x8d], ht216->ht_regs[0x8e], ht216->ht_regs[0x8f]);
ht216_log(" 9 | %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X\n",
ht216->ht_regs[0x90], ht216->ht_regs[0x91], ht216->ht_regs[0x92], ht216->ht_regs[0x93],
ht216->ht_regs[0x94], ht216->ht_regs[0x95], ht216->ht_regs[0x96], ht216->ht_regs[0x97],
ht216->ht_regs[0x98], ht216->ht_regs[0x99], ht216->ht_regs[0x9a], ht216->ht_regs[0x9b],
ht216->ht_regs[0x9c], ht216->ht_regs[0x9d], ht216->ht_regs[0x9e], ht216->ht_regs[0x9f]);
ht216_log(" A | %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X\n",
ht216->ht_regs[0xa0], ht216->ht_regs[0xa1], ht216->ht_regs[0xa2], ht216->ht_regs[0xa3],
ht216->ht_regs[0xa4], ht216->ht_regs[0xa5], ht216->ht_regs[0xa6], ht216->ht_regs[0xa7],
ht216->ht_regs[0xa8], ht216->ht_regs[0xa9], ht216->ht_regs[0xaa], ht216->ht_regs[0xab],
ht216->ht_regs[0xac], ht216->ht_regs[0xad], ht216->ht_regs[0xae], ht216->ht_regs[0xaf]);
ht216_log(" B | %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X\n",
ht216->ht_regs[0xb0], ht216->ht_regs[0xb1], ht216->ht_regs[0xb2], ht216->ht_regs[0xb3],
ht216->ht_regs[0xb4], ht216->ht_regs[0xb5], ht216->ht_regs[0xb6], ht216->ht_regs[0xb7],
ht216->ht_regs[0xb8], ht216->ht_regs[0xb9], ht216->ht_regs[0xba], ht216->ht_regs[0xbb],
ht216->ht_regs[0xbc], ht216->ht_regs[0xbd], ht216->ht_regs[0xbe], ht216->ht_regs[0xbf]);
ht216_log(" C | %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X\n",
ht216->ht_regs[0xc0], ht216->ht_regs[0xc1], ht216->ht_regs[0xc2], ht216->ht_regs[0xc3],
ht216->ht_regs[0xc4], ht216->ht_regs[0xc5], ht216->ht_regs[0xc6], ht216->ht_regs[0xc7],
ht216->ht_regs[0xc8], ht216->ht_regs[0xc9], ht216->ht_regs[0xca], ht216->ht_regs[0xcb],
ht216->ht_regs[0xcc], ht216->ht_regs[0xcd], ht216->ht_regs[0xce], ht216->ht_regs[0xcf]);
ht216_log(" D | %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X\n",
ht216->ht_regs[0xd0], ht216->ht_regs[0xd1], ht216->ht_regs[0xd2], ht216->ht_regs[0xd3],
ht216->ht_regs[0xd4], ht216->ht_regs[0xd5], ht216->ht_regs[0xd6], ht216->ht_regs[0xd7],
ht216->ht_regs[0xd8], ht216->ht_regs[0xd9], ht216->ht_regs[0xda], ht216->ht_regs[0xdb],
ht216->ht_regs[0xdc], ht216->ht_regs[0xdd], ht216->ht_regs[0xde], ht216->ht_regs[0xdf]);
ht216_log(" E | %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X\n",
ht216->ht_regs[0xe0], ht216->ht_regs[0xe1], ht216->ht_regs[0xe2], ht216->ht_regs[0xe3],
ht216->ht_regs[0xe4], ht216->ht_regs[0xe5], ht216->ht_regs[0xe6], ht216->ht_regs[0xe7],
ht216->ht_regs[0xe8], ht216->ht_regs[0xe9], ht216->ht_regs[0xea], ht216->ht_regs[0xeb],
ht216->ht_regs[0xec], ht216->ht_regs[0xed], ht216->ht_regs[0xee], ht216->ht_regs[0xef]);
ht216_log(" F | %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X\n",
ht216->ht_regs[0xf0], ht216->ht_regs[0xf1], ht216->ht_regs[0xf2], ht216->ht_regs[0xf3],
ht216->ht_regs[0xf4], ht216->ht_regs[0xf5], ht216->ht_regs[0xf6], ht216->ht_regs[0xf7],
ht216->ht_regs[0xf8], ht216->ht_regs[0xf9], ht216->ht_regs[0xfa], ht216->ht_regs[0xfb],
ht216->ht_regs[0xfc], ht216->ht_regs[0xfd], ht216->ht_regs[0xfe], ht216->ht_regs[0xff]);
return;
#endif
} else if (svga->seqaddr >= 0x80 && ht216->ext_reg_enable) {
old = ht216->ht_regs[svga->seqaddr & 0xff];
ht216->ht_regs[svga->seqaddr & 0xff] = val;
switch (svga->seqaddr & 0xff) {
case 0x83:
svga->attraddr = val & 0x1f;
svga->attrff = !!(val & 0x80);
break;
case 0x94:
case 0xff:
svga->hwcursor.addr = ((ht216->ht_regs[0x94] << 6) | 0xc000 | ((ht216->ht_regs[0xff] & 0x60) << 11)) << 2;
svga->hwcursor.addr &= svga->vram_mask;
if (svga->crtc[0x17] == 0xeb) /*Looks like that 1024x768 mono mode expects 512K of video memory*/
svga->hwcursor.addr += 0x40000;
break;
case 0x9c:
case 0x9d:
svga->hwcursor.x = ht216->ht_regs[0x9d] | ((ht216->ht_regs[0x9c] & 7) << 8);
break;
case 0x9e:
case 0x9f:
svga->hwcursor.y = ht216->ht_regs[0x9f] | ((ht216->ht_regs[0x9e] & 3) << 8);
break;
case 0xa0:
svga->latch.b[0] = val;
break;
case 0xa1:
svga->latch.b[1] = val;
break;
case 0xa2:
svga->latch.b[2] = val;
break;
case 0xa3:
svga->latch.b[3] = val;
break;
case 0xa4:
case 0xf8:
svga->fullchange = changeframecount;
svga_recalctimings(svga);
break;
case 0xa5:
svga->hwcursor.ena = !!(val & 0x80);
break;
case 0xc0:
break;
case 0xc1:
break;
case 0xc8:
if ((old ^ val) & HT_REG_C8_E256) {
svga->fullchange = changeframecount;
svga_recalctimings(svga);
}
ht216_remap(ht216);
break;
case 0xca:
if (ht216->id == 0x7861)
svga_recalctimings(svga);
break;
case 0xc9:
case 0xcf:
ht216_remap(ht216);
break;
case 0xe0:
svga->adv_flags &= ~FLAG_RAMDAC_SHIFT;
if (val & 0x04)
svga->adv_flags |= FLAG_RAMDAC_SHIFT;
svga_recalctimings(svga);
fallthrough;
/*Bank registers*/
case 0xe8:
case 0xe9:
ht216_log("HT216 reg 0x%02x write = %02x, mode = 1, chain4 = %x\n", svga->seqaddr & 0xff, val, svga->chain4);
ht216_recalc_bank_regs(ht216, 1);
ht216_remap(ht216);
break;
case 0xec:
ht216->fg_latch[0] = val;
break;
case 0xed:
ht216->fg_latch[1] = val;
break;
case 0xee:
ht216->fg_latch[2] = val;
break;
case 0xef:
ht216->fg_latch[3] = val;
break;
case 0xf0:
ht216->fg_latch[ht216->fg_plane_sel] = val;
ht216->fg_plane_sel = (ht216->fg_plane_sel + 1) & 3;
break;
case 0xf1:
ht216->bg_plane_sel = val & 3;
ht216->fg_plane_sel = (val & 0x30) >> 4;
break;
case 0xf2:
svga->latch.b[ht216->bg_plane_sel] = val;
ht216->bg_plane_sel = (ht216->bg_plane_sel + 1) & 3;
break;
case 0xf6:
/*Bits 18 and 19 of the display memory address*/
ht216_log("HT216 reg 0xf6 write = %02x, mode = 0, chain4 = %x, vram mask = %08x, cr17 = %02x\n", val, svga->chain4, svga->vram_display_mask, svga->crtc[0x17]);
ht216_recalc_bank_regs(ht216, 0);
ht216_remap(ht216);
svga->fullchange = changeframecount;
svga_recalctimings(svga);
break;
case 0xf9:
/*Bit 16 of the display memory address, only active when in chain4 mode and 256 color mode.*/
ht216_log("HT216 reg 0xf9 write = %02x, mode = 0, chain4 = %x\n", val & HT_REG_F9_XPSEL, svga->chain4);
ht216_recalc_bank_regs(ht216, 0);
ht216_remap(ht216);
break;
case 0xfc:
ht216_log("HT216 reg 0xfc write = %02x, mode = 0, chain4 = %x, bit 7 = %02x, packedchain = %02x\n", val, svga->chain4, val & 0x80, val & 0x20);
svga->packed_chain4 = !!(val & 0x20);
ht216_recalc_bank_regs(ht216, 0);
ht216_remap(ht216);
svga->fullchange = changeframecount;
svga_recalctimings(svga);
break;
default:
break;
}
return;
}
break;
case 0x3c6:
case 0x3c7:
case 0x3c8:
case 0x3c9:
if (ht216->id == 0x7152)
sc1148x_ramdac_out(addr, 0, val, svga->ramdac, svga);
else
svga_out(addr, val, svga);
return;
case 0x3cb:
if (ht216->id == 0x7152) {
ht216->reg_3cb = val;
svga_set_ramdac_type(svga, (val & 0x20) ? RAMDAC_6BIT : RAMDAC_8BIT);
}
break;
case 0x3cf:
if (svga->gdcaddr == 5) {
svga->chain2_read = val & 0x10;
ht216_remap(ht216);
} else if (svga->gdcaddr == 6) {
if (val & 8)
svga->banked_mask = 0x7fff;
else
svga->banked_mask = 0xffff;
}
if (svga->gdcaddr <= 8) {
svga->fast = (svga->gdcreg[8] == 0xff && !(svga->gdcreg[3] & 0x18) && !svga->gdcreg[1]) && svga->chain4 && svga->packed_chain4;
}
break;
case 0x3D4:
svga->crtcreg = val & 0x3f;
return;
case 0x3D5:
if ((svga->crtcreg < 7) && (svga->crtc[0x11] & 0x80))
return;
if ((svga->crtcreg == 7) && (svga->crtc[0x11] & 0x80))
val = (svga->crtc[7] & ~0x10) | (val & 0x10);
old = svga->crtc[svga->crtcreg];
svga->crtc[svga->crtcreg] = val;
if (old != val) {
if (svga->crtcreg < 0xe || svga->crtcreg > 0x10) {
if ((svga->crtcreg == 0xc) || (svga->crtcreg == 0xd)) {
svga->fullchange = 3;
svga->ma_latch = ((svga->crtc[0xc] << 8) | svga->crtc[0xd]) + ((svga->crtc[8] & 0x60) >> 5);
} else {
svga->fullchange = changeframecount;
svga_recalctimings(svga);
}
}
}
break;
case 0x46e8:
io_removehandler(0x03c0, 0x0020, ht216_in, NULL, NULL, ht216_out, NULL, NULL, ht216);
mem_mapping_disable(&svga->mapping);
mem_mapping_disable(&ht216->linear_mapping);
if (val & 8) {
io_sethandler(0x03c0, 0x0020, ht216_in, NULL, NULL, ht216_out, NULL, NULL, ht216);
mem_mapping_enable(&svga->mapping);
ht216_remap(ht216);
}
break;
default:
break;
}
svga_out(addr, val, svga);
}
uint8_t
ht216_in(uint16_t addr, void *priv)
{
ht216_t *ht216 = (ht216_t *) priv;
svga_t *svga = &ht216->svga;
uint8_t ret = 0xff;
if (((addr & 0xfff0) == 0x3d0 || (addr & 0xfff0) == 0x3b0) && !(svga->miscout & 1))
addr ^= 0x60;
switch (addr) {
case 0x105:
if (ht216->isabus && (ht216->id == 0x7152)) {
ret &= ~0x03;
return ret;
}
break;
case 0x3c4:
return svga->seqaddr;
case 0x3c5:
if (svga->seqaddr == 6)
return ht216->ext_reg_enable;
else if (svga->seqaddr >= 0x80) {
if (ht216->ext_reg_enable) {
ret = ht216->ht_regs[svga->seqaddr & 0xff];
switch (svga->seqaddr & 0xff) {
case 0x83:
if (svga->attrff)
ret = svga->attraddr | 0x80;
else
ret = svga->attraddr;
break;
case 0x8e:
ret = ht216->id & 0xff;
break;
case 0x8f:
ret = (ht216->id >> 8) & 0xff;
break;
case 0xa0:
ret = svga->latch.b[0];
break;
case 0xa1:
ret = svga->latch.b[1];
break;
case 0xa2:
ret = svga->latch.b[2];
break;
case 0xa3:
ret = svga->latch.b[3];
break;
case 0xf0:
ret = ht216->fg_latch[ht216->fg_plane_sel];
ht216->fg_plane_sel = 0;
break;
case 0xf2:
ret = svga->latch.b[ht216->bg_plane_sel];
ht216->bg_plane_sel = 0;
break;
default:
break;
}
return ret;
} else
return 0xff;
}
break;
case 0x3c6:
case 0x3c7:
case 0x3c8:
case 0x3c9:
if (ht216->id == 0x7152)
return sc1148x_ramdac_in(addr, 0, svga->ramdac, svga);
return svga_in(addr, svga);
case 0x3cb:
if (ht216->id == 0x7152)
return ht216->reg_3cb;
break;
case 0x3cc:
return svga->miscout;
case 0x3D4:
return svga->crtcreg;
case 0x3D5:
if (svga->crtcreg == 0x1f)
return svga->crtc[0xc] ^ 0xea;
return svga->crtc[svga->crtcreg];
default:
break;
}
return svga_in(addr, svga);
}
void
ht216_remap(ht216_t *ht216)
{
svga_t *svga = &ht216->svga;
mem_mapping_disable(&ht216->linear_mapping);
if (ht216->ht_regs[0xc8] & HT_REG_C8_XLAM) {
/*Linear mapping enabled*/
ht216_log("Linear mapping enabled\n");
ht216->linear_base = ((ht216->ht_regs[0xc9] & 0xf) << 20) | (ht216->ht_regs[0xcf] << 24);
mem_mapping_disable(&svga->mapping);
mem_mapping_set_addr(&ht216->linear_mapping, ht216->linear_base, 0x100000);
}
ht216->read_banks[0] = ht216->read_bank_reg[0] << 12;
ht216->write_banks[0] = ht216->write_bank_reg[0] << 12;
/* Split bank: two banks used */
if (ht216->ht_regs[0xe0] & HT_REG_E0_SBAE) {
ht216->read_banks[1] = ht216->read_bank_reg[1] << 12;
ht216->write_banks[1] = ht216->write_bank_reg[1] << 12;
}
if (!svga->chain4) {
ht216->read_banks[0] = ((ht216->read_banks[0] & 0xc0000) >> 2) | (ht216->read_banks[0] & 0xffff);
ht216->read_banks[1] = ((ht216->read_banks[1] & 0xc0000) >> 2) | (ht216->read_banks[1] & 0xffff);
ht216->write_banks[0] = ((ht216->write_banks[0] & 0xc0000) >> 2) | (ht216->write_banks[0] & 0xffff);
ht216->write_banks[1] = ((ht216->write_banks[1] & 0xc0000) >> 2) | (ht216->write_banks[1] & 0xffff);
}
if (!(ht216->ht_regs[0xe0] & HT_REG_E0_SBAE)) {
ht216->read_banks[1] = ht216->read_banks[0] + 0x8000;
ht216->write_banks[1] = ht216->write_banks[0] + 0x8000;
}
#ifdef ENABLE_HT216_LOG
ht216_log("Registers: %02X, %02X, %02X, %02X, %02X\n", ht216->misc, ht216->ht_regs[0xe8], ht216->ht_regs[0xe9],
ht216->ht_regs[0xf6], ht216->ht_regs[0xf9]);
ht216_log("Banks: %08X, %08X, %08X, %08X\n", ht216->read_banks[0], ht216->read_banks[1],
ht216->write_banks[0], ht216->write_banks[1]);
#endif
}
void
ht216_recalctimings(svga_t *svga)
{
ht216_t *ht216 = (ht216_t *) svga->priv;
int high_res_256 = 0;
if (ht216->id == 0x7861) {
if (ht216->ht_regs[0xe0] & 0x20) {
if (ht216->ht_regs[0xca] & 0x01)
svga->htotal |= 0x200;
if (ht216->ht_regs[0xca] & 0x04)
svga->hblankstart |= 0x200;
}
}
switch ((((((svga->miscout >> 2) & 3) || ((ht216->ht_regs[0xa4] >> 2) & 3)) | ((ht216->ht_regs[0xa4] >> 2) & 4)) || ((ht216->ht_regs[0xf8] >> 5) & 0x0f)) | ((ht216->ht_regs[0xf8] << 1) & 8)) {
case 0:
case 1:
break;
case 4:
svga->clock = (cpuclock * (double) (1ULL << 32)) / 50350000.0;
break;
case 5:
svga->clock = (cpuclock * (double) (1ULL << 32)) / 65000000.0;
break;
case 7:
svga->clock = (cpuclock * (double) (1ULL << 32)) / 40000000.0;
break;
default:
svga->clock = (cpuclock * (double) (1ULL << 32)) / 36000000.0;
break;
}
svga->ma_latch |= ((ht216->ht_regs[0xf6] & 0x30) << 12);
if (ht216->ht_regs[0xf6] & 0x80)
svga->ma_latch = ((ht216->ht_regs[0xf6] & 0x30) << 12);
svga->interlace = ht216->ht_regs[0xe0] & 0x01;
if (svga->interlace)
high_res_256 = (svga->htotal << 3) > (svga->vtotal << 2);
else
high_res_256 = (svga->htotal << 3) > (svga->vtotal << 1);
ht216->adjust_cursor = 0;
if (!svga->scrblank && svga->attr_palette_enable) {
if (!(svga->gdcreg[6] & 1) && !(svga->attrregs[0x10] & 1)) { /*Text mode*/
if (svga->seqregs[1] & 8) /*40 column*/ {
svga->render = svga_render_text_40;
} else {
svga->render = svga_render_text_80;
}
} else {
if (svga->crtc[0x17] == 0xeb) {
svga->rowoffset <<= 1;
svga->render = svga_render_2bpp_headland_highres;
}
if (svga->bpp == 8) {
ht216_log("regC8 = %02x, gdcreg5 bit 6 = %02x, no lowres = %02x, regf8 bit 7 = %02x, regfc = %02x\n", ht216->ht_regs[0xc8] & HT_REG_C8_E256, svga->gdcreg[5] & 0x40, !svga->lowres, ht216->ht_regs[0xf6] & 0x80, ht216->ht_regs[0xfc] & HT_REG_FC_ECOLRE);
if (((ht216->ht_regs[0xc8] & HT_REG_C8_E256) || (svga->gdcreg[5] & 0x40)) && (!svga->lowres || (ht216->ht_regs[0xf6] & 0x80))) {
if (high_res_256) {
svga->hdisp >>= 1;
ht216->adjust_cursor = 1;
}
svga->render = svga_render_8bpp_highres;
} else if (svga->lowres) {
if (high_res_256) {
svga->hdisp >>= 1;
ht216->adjust_cursor = 1;
svga->render = svga_render_8bpp_highres;
} else {
ht216_log("8bpp low, packed = %02x, chain4 = %02x\n", svga->packed_chain4, svga->chain4);
svga->render = svga_render_8bpp_lowres;
}
} else if (ht216->ht_regs[0xfc] & HT_REG_FC_ECOLRE) {
if (ht216->id == 0x7152) {
svga->hdisp = svga->crtc[1] - ((svga->crtc[5] & 0x60) >> 5);
if (!(svga->crtc[1] & 1))
svga->hdisp--;
svga->hdisp++;
svga->hdisp *= svga->dots_per_clock;
svga->rowoffset <<= 1;
if ((svga->crtc[0x17] & 0x60) == 0x20) /*Would result in a garbled screen with trailing cursor glitches*/
svga->crtc[0x17] |= 0x40;
}
svga->render = svga_render_8bpp_highres;
}
} else if (svga->bpp == 15) {
svga->rowoffset <<= 1;
svga->hdisp >>= 1;
if ((svga->crtc[0x17] & 0x60) == 0x20) /*Would result in a garbled screen with trailing cursor glitches*/
svga->crtc[0x17] |= 0x40;
svga->render = svga_render_15bpp_highres;
}
}
}
if (svga->crtc[0x17] == 0xeb) /*Looks like 1024x768 mono mode expects 512K of video memory*/
svga->vram_display_mask = 0x7ffff;
else
svga->vram_display_mask = (ht216->ht_regs[0xf6] & 0x40) ? ht216->vram_mask : 0x3ffff;
}
static void
ht216_hwcursor_draw(svga_t *svga, int displine)
{
const ht216_t *ht216 = (ht216_t *) svga->priv;
int shift = (ht216->adjust_cursor ? 2 : 1);
uint32_t dat[2];
int offset = svga->hwcursor_latch.x + svga->hwcursor_latch.xoff;
int width = (ht216->adjust_cursor ? 16 : 32);
if (ht216->adjust_cursor)
offset >>= 1;
if (svga->interlace && svga->hwcursor_oddeven)
svga->hwcursor_latch.addr += 4;
dat[0] = (svga->vram[svga->hwcursor_latch.addr] << 24) | (svga->vram[svga->hwcursor_latch.addr + 1] << 16) | (svga->vram[svga->hwcursor_latch.addr + 2] << 8) | svga->vram[svga->hwcursor_latch.addr + 3];
dat[1] = (svga->vram[svga->hwcursor_latch.addr + 128] << 24) | (svga->vram[svga->hwcursor_latch.addr + 128 + 1] << 16) | (svga->vram[svga->hwcursor_latch.addr + 128 + 2] << 8) | svga->vram[svga->hwcursor_latch.addr + 128 + 3];
for (int x = 0; x < width; x++) {
if (!(dat[0] & 0x80000000))
svga->monitor->target_buffer->line[displine][svga->x_add + offset + x] = 0;
if (dat[1] & 0x80000000)
svga->monitor->target_buffer->line[displine][svga->x_add + offset + x] ^= 0xffffff;
dat[0] <<= shift;
dat[1] <<= shift;
}
svga->hwcursor_latch.addr += 4;
if (svga->interlace && !svga->hwcursor_oddeven)
svga->hwcursor_latch.addr += 4;
}
static __inline uint8_t
extalu(int op, uint8_t input_a, uint8_t input_b)
{
uint8_t val;
switch (op) {
case 0x0:
val = 0;
break;
case 0x1:
val = ~(input_a | input_b);
break;
case 0x2:
val = input_a & ~input_b;
break;
case 0x3:
val = ~input_b;
break;
case 0x4:
val = ~input_a & input_b;
break;
case 0x5:
val = ~input_a;
break;
case 0x6:
val = input_a ^ input_b;
break;
case 0x7:
val = ~(input_a & input_b);
break;
case 0x8:
val = input_a & input_b;
break;
case 0x9:
val = ~(input_a ^ input_b);
break;
case 0xa:
val = input_a;
break;
case 0xb:
val = input_a | ~input_b;
break;
case 0xc:
val = input_b;
break;
case 0xd:
val = ~input_a | input_b;
break;
case 0xe:
val = input_a | input_b;
break;
case 0xf:
default:
val = 0xff;
break;
}
return val;
}
static void
ht216_dm_write(ht216_t *ht216, uint32_t addr, uint8_t cpu_dat, uint8_t cpu_dat_unexpanded)
{
svga_t *svga = &ht216->svga;
int writemask2 = svga->writemask;
int reset_wm = 0;
latch_t vall;
uint8_t i;
uint8_t wm = svga->writemask;
uint8_t count = 4;
uint8_t fg_data[8] = { 0, 0, 0, 0, 0, 0, 0, 0 };
if (ht216->ht_regs[0xcd] & HT_REG_CD_P8PCEXP)
writemask2 = svga->seqregs[2];
if (!(svga->gdcreg[6] & 1))
svga->fullchange = 2;
if (svga->chain4) {
writemask2 = 1 << (addr & 3);
addr = dword_remap(svga, addr) & ~3;
} else if (svga->chain2_write && (svga->crtc[0x17] != 0xeb)) {
writemask2 &= ~0xa;
if (addr & 1)
writemask2 <<= 1;
addr &= ~1;
addr <<= 2;
} else
addr <<= 2;
if (addr >= svga->vram_max)
return;
svga->changedvram[addr >> 12] = changeframecount;
if (ht216->ht_regs[0xcd] & HT_REG_CD_P8PCEXP)
count = 8;
switch (ht216->ht_regs[0xfe] & HT_REG_FE_FBMC) {
case 0x00:
for (i = 0; i < count; i++)
fg_data[i] = cpu_dat;
break;
case 0x04:
if (ht216->ht_regs[0xfe] & HT_REG_FE_FBRC) {
for (i = 0; i < count; i++) {
if (ht216->ht_regs[0xfa] & (1 << i))
fg_data[i] = cpu_dat_unexpanded;
else if (ht216->ht_regs[0xfb] & (1 << i))
fg_data[i] = 0xff - cpu_dat_unexpanded;
}
} else {
for (i = 0; i < count; i++) {
if (ht216->ht_regs[0xfa] & (1 << i))
fg_data[i] = ht216->ht_regs[0xf5];
else if (ht216->ht_regs[0xfb] & (1 << i))
fg_data[i] = 0xff - ht216->ht_regs[0xf5];
}
}
break;
case 0x08:
case 0x0c:
for (i = 0; i < count; i++)
fg_data[i] = ht216->fg_latch[i];
break;
default:
break;
}
switch (svga->writemode) {
case 0:
if ((svga->gdcreg[8] == 0xff) && !(svga->gdcreg[3] & 0x18) && (!svga->gdcreg[1] || svga->set_reset_disabled)) {
for (i = 0; i < count; i++) {
if (ht216->ht_regs[0xcd] & HT_REG_CD_P8PCEXP) {
if (writemask2 & (0x80 >> i))
svga->vram[addr | i] = fg_data[i];
} else {
if (writemask2 & (1 << i))
svga->vram[addr | i] = fg_data[i];
}
}
return;
} else {
for (i = 0; i < count; i++) {
if (svga->gdcreg[1] & (1 << i))
vall.b[i] = !!(svga->gdcreg[0] & (1 << i)) * 0xff;
else
vall.b[i] = fg_data[i];
}
}
break;
case 1:
for (i = 0; i < count; i++) {
if (ht216->ht_regs[0xcd] & HT_REG_CD_P8PCEXP) {
if (writemask2 & (0x80 >> i))
svga->vram[addr | i] = svga->latch.b[i];
} else {
if (writemask2 & (1 << i))
svga->vram[addr | i] = svga->latch.b[i];
}
}
return;
case 2:
for (i = 0; i < count; i++)
vall.b[i] = !!(cpu_dat & (1 << i)) * 0xff;
if (!(svga->gdcreg[3] & 0x18) && (!svga->gdcreg[1] || svga->set_reset_disabled)) {
for (i = 0; i < count; i++) {
if (ht216->ht_regs[0xcd] & HT_REG_CD_P8PCEXP) {
if (writemask2 & (0x80 >> i))
svga->vram[addr | i] = (vall.b[i] & svga->gdcreg[8]) | (svga->latch.b[i] & ~svga->gdcreg[8]);
} else {
if (writemask2 & (1 << i))
svga->vram[addr | i] = (vall.b[i] & svga->gdcreg[8]) | (svga->latch.b[i] & ~svga->gdcreg[8]);
}
}
return;
}
break;
case 3:
wm = svga->gdcreg[8];
svga->gdcreg[8] &= cpu_dat;
for (i = 0; i < count; i++)
vall.b[i] = !!(svga->gdcreg[0] & (1 << i)) * 0xff;
reset_wm = 1;
break;
default:
break;
}
switch (svga->gdcreg[3] & 0x18) {
case 0x00: /* Set */
for (i = 0; i < count; i++) {
if (ht216->ht_regs[0xcd] & HT_REG_CD_P8PCEXP) {
if (writemask2 & (0x80 >> i))
svga->vram[addr | i] = (vall.b[i] & svga->gdcreg[8]) | (svga->latch.b[i] & ~svga->gdcreg[8]);
} else {
if (writemask2 & (1 << i))
svga->vram[addr | i] = (vall.b[i] & svga->gdcreg[8]) | (svga->latch.b[i] & ~svga->gdcreg[8]);
}
}
break;
case 0x08: /* AND */
for (i = 0; i < count; i++) {
if (ht216->ht_regs[0xcd] & HT_REG_CD_P8PCEXP) {
if (writemask2 & (0x80 >> i))
svga->vram[addr | i] = (vall.b[i] | ~svga->gdcreg[8]) & svga->latch.b[i];
} else {
if (writemask2 & (1 << i))
svga->vram[addr | i] = (vall.b[i] | ~svga->gdcreg[8]) & svga->latch.b[i];
}
}
break;
case 0x10: /* OR */
for (i = 0; i < count; i++) {
if (ht216->ht_regs[0xcd] & HT_REG_CD_P8PCEXP) {
if (writemask2 & (0x80 >> i))
svga->vram[addr | i] = (vall.b[i] & svga->gdcreg[8]) | svga->latch.b[i];
} else {
if (writemask2 & (1 << i))
svga->vram[addr | i] = (vall.b[i] & svga->gdcreg[8]) | svga->latch.b[i];
}
}
break;
case 0x18: /* XOR */
for (i = 0; i < count; i++) {
if (ht216->ht_regs[0xcd] & HT_REG_CD_P8PCEXP) {
if (writemask2 & (0x80 >> i))
svga->vram[addr | i] = (vall.b[i] & svga->gdcreg[8]) ^ svga->latch.b[i];
} else {
if (writemask2 & (1 << i))
svga->vram[addr | i] = (vall.b[i] & svga->gdcreg[8]) ^ svga->latch.b[i];
}
}
break;
default:
break;
}
if (reset_wm)
svga->gdcreg[8] = wm;
}
static void
ht216_dm_extalu_write(ht216_t *ht216, uint32_t addr, uint8_t cpu_dat, uint8_t bit_mask, uint8_t cpu_dat_unexpanded, uint8_t rop_select)
{
/*Input B = CD.5
Input A = FE[3:2]
00 = Set/Reset output mode
output = CPU-side ALU input
01 = Solid fg/bg mode (3C4:FA/FB)
Bit mask = 3CF.F5 or CPU byte
10 = Dithered fg (3CF:EC-EF)
11 = RMW (dest data) (set if CD.5 = 1)
F/B ROP select = FE[5:4]
00 = CPU byte
01 = Bit mask (3CF:8)
1x = (3C4:F5)*/
svga_t *svga = &ht216->svga;
uint8_t input_a = 0;
uint8_t input_b = 0;
uint8_t fg;
uint8_t bg;
uint8_t output;
uint32_t remapped_addr = dword_remap(svga, addr);
if (ht216->ht_regs[0xcd] & HT_REG_CD_RMWMDE) /*RMW*/
input_b = svga->vram[remapped_addr];
else
input_b = ht216->bg_latch[addr & 7];
switch (ht216->ht_regs[0xfe] & HT_REG_FE_FBMC) {
case 0x00:
input_a = cpu_dat;
break;
case 0x04:
if (ht216->ht_regs[0xfe] & HT_REG_FE_FBRC)
input_a = (cpu_dat_unexpanded & (1 << ((addr & 7) ^ 7))) ? ht216->ht_regs[0xfa] : ht216->ht_regs[0xfb];
else
input_a = (ht216->ht_regs[0xf5] & (1 << ((addr & 7) ^ 7))) ? ht216->ht_regs[0xfa] : ht216->ht_regs[0xfb];
break;
case 0x08:
input_a = ht216->fg_latch[addr & 3];
break;
case 0x0c:
input_a = ht216->bg_latch[addr & 7];
break;
default:
break;
}
fg = extalu(ht216->ht_regs[0xce] >> 4, input_a, input_b);
bg = extalu(ht216->ht_regs[0xce] & 0xf, input_a, input_b);
output = (fg & rop_select) | (bg & ~rop_select);
svga->vram[addr] = (svga->vram[remapped_addr] & ~bit_mask) | (output & bit_mask);
svga->changedvram[remapped_addr >> 12] = changeframecount;
}
static void
ht216_dm_masked_write(ht216_t *ht216, uint32_t addr, uint8_t val, uint8_t bit_mask)
{
svga_t *svga = &ht216->svga;
int writemask2 = svga->writemask;
uint8_t count = 4;
uint8_t i;
uint8_t full_mask = 0x0f;
if (ht216->ht_regs[0xcd] & HT_REG_CD_P8PCEXP)
writemask2 = svga->seqregs[2];
if (!(svga->gdcreg[6] & 1))
svga->fullchange = 2;
if (svga->chain4) {
writemask2 = 1 << (addr & 3);
addr = dword_remap(svga, addr) & ~3;
} else if (svga->chain2_write) {
writemask2 &= ~0xa;
if (addr & 1)
writemask2 <<= 1;
addr &= ~1;
addr <<= 2;
} else
addr <<= 2;
if (addr >= svga->vram_max)
return;
addr &= svga->decode_mask;
if (addr >= svga->vram_max)
return;
addr &= svga->vram_mask;
svga->changedvram[addr >> 12] = changeframecount;
if (ht216->ht_regs[0xcd] & HT_REG_CD_P8PCEXP) {
count = 8;
full_mask = 0xff;
}
if (bit_mask == 0xff) {
for (i = 0; i < count; i++) {
if (writemask2 & (1 << i))
svga->vram[addr | i] = val;
}
} else {
if (writemask2 == full_mask) {
for (i = 0; i < count; i++)
svga->vram[addr | i] = (svga->latch.b[i] & bit_mask) | (svga->vram[addr | i] & ~bit_mask);
} else {
for (i = 0; i < count; i++) {
if (writemask2 & (1 << i))
svga->vram[addr | i] = (val & bit_mask) | (svga->vram[addr | i] & ~bit_mask);
}
}
}
}
static void
ht216_write_common(ht216_t *ht216, uint32_t addr, uint8_t val)
{
/*Input B = CD.5
Input A = FE[3:2]
00 = Set/Reset output mode
output = CPU-side ALU input
01 = Solid fg/bg mode (3C4:FA/FB)
Bit mask = 3CF.F5 or CPU byte
10 = Dithered fg (3CF:EC-EF)
11 = RMW (dest data) (set if CD.5 = 1)
F/B ROP select = FE[5:4]
00 = CPU byte
01 = Bit mask (3CF:8)
1x = (3C4:F5)
*/
const svga_t *svga = &ht216->svga;
int i;
uint8_t bit_mask = 0;
uint8_t rop_select = 0;
cycles -= video_timing_write_b;
addr &= svga->vram_mask;
val = ((val >> (svga->gdcreg[3] & 7)) | (val << (8 - (svga->gdcreg[3] & 7))));
if (ht216->ht_regs[0xcd] & HT_REG_CD_EXALU) {
/*Extended ALU*/
switch (ht216->ht_regs[0xfe] & HT_REG_FE_FBRSL) {
case 0x00:
rop_select = val;
break;
case 0x10:
rop_select = svga->gdcreg[8];
break;
case 0x20:
case 0x30:
rop_select = ht216->ht_regs[0xf5];
break;
default:
break;
}
switch (ht216->ht_regs[0xcd] & HT_REG_CD_BMSKSL) {
case 0x00:
bit_mask = svga->gdcreg[8];
break;
case 0x04:
bit_mask = val;
break;
case 0x08:
case 0x0c:
bit_mask = ht216->ht_regs[0xf5];
break;
default:
break;
}
if (ht216->ht_regs[0xcd] & HT_REG_CD_FP8PCEXP) { /*1->8 bit expansion*/
addr = (addr << 3) & 0xfffff;
for (i = 0; i < 8; i++)
ht216_dm_extalu_write(ht216, addr + i, (val & (0x80 >> i)) ? 0xff : 0, (bit_mask & (0x80 >> i)) ? 0xff : 0, val, (rop_select & (0x80 >> i)) ? 0xff : 0);
} else {
ht216_dm_extalu_write(ht216, addr, val, bit_mask, val, rop_select);
}
} else if (ht216->ht_regs[0xf3]) {
if (ht216->ht_regs[0xf3] & 2) {
ht216_dm_masked_write(ht216, addr, val, val);
} else
ht216_dm_masked_write(ht216, addr, val, ht216->ht_regs[0xf4]);
} else {
if (ht216->ht_regs[0xcd] & HT_REG_CD_FP8PCEXP) { /*1->8 bit expansion*/
addr = (addr << 3) & 0xfffff;
for (i = 0; i < 8; i++)
ht216_dm_write(ht216, addr + i, (val & (0x80 >> i)) ? 0xff : 0, val);
} else {
ht216_dm_write(ht216, addr, val, val);
}
}
}
static void
ht216_write(uint32_t addr, uint8_t val, void *priv)
{
ht216_t *ht216 = (ht216_t *) priv;
svga_t *svga = &ht216->svga;
uint32_t prev_addr = addr;
addr &= svga->banked_mask;
addr = (addr & 0x7fff) + ht216->write_banks[(addr >> 15) & 1];
if (svga->crtc[0x17] == 0xeb && !(svga->gdcreg[6] & 0xc) && prev_addr >= 0xb0000)
addr += 0x10000;
else if (svga->chain4 && ((ht216->ht_regs[0xfc] & 0x06) == 0x06))
addr = (addr & 0xfffeffff) | (prev_addr & 0x10000);
if (!ht216->ht_regs[0xcd] && !ht216->ht_regs[0xfe] && !ht216->ht_regs[0xf3] && svga->crtc[0x17] != 0xeb) {
svga_write_linear(addr, val, svga);
} else
ht216_write_common(ht216, addr, val);
}
static void
ht216_writew(uint32_t addr, uint16_t val, void *priv)
{
ht216_t *ht216 = (ht216_t *) priv;
svga_t *svga = &ht216->svga;
uint32_t prev_addr = addr;
addr &= svga->banked_mask;
addr = (addr & 0x7fff) + ht216->write_banks[(addr >> 15) & 1];
if (svga->crtc[0x17] == 0xeb && !(svga->gdcreg[6] & 0xc) && prev_addr >= 0xb0000)
addr += 0x10000;
else if (svga->chain4 && ((ht216->ht_regs[0xfc] & 0x06) == 0x06))
addr = (addr & 0xfffeffff) | (prev_addr & 0x10000);
if (!ht216->ht_regs[0xcd] && !ht216->ht_regs[0xfe] && !ht216->ht_regs[0xf3] && svga->crtc[0x17] != 0xeb)
svga_writew_linear(addr, val, svga);
else {
ht216_write_common(ht216, addr, val);
ht216_write_common(ht216, addr + 1, val >> 8);
}
}
static void
ht216_writel(uint32_t addr, uint32_t val, void *priv)
{
ht216_t *ht216 = (ht216_t *) priv;
svga_t *svga = &ht216->svga;
uint32_t prev_addr = addr;
addr &= svga->banked_mask;
addr = (addr & 0x7fff) + ht216->write_banks[(addr >> 15) & 1];
if (svga->crtc[0x17] == 0xeb && !(svga->gdcreg[6] & 0xc) && prev_addr >= 0xb0000)
addr += 0x10000;
else if (svga->chain4 && ((ht216->ht_regs[0xfc] & 0x06) == 0x06))
addr = (addr & 0xfffeffff) | (prev_addr & 0x10000);
if (!ht216->ht_regs[0xcd] && !ht216->ht_regs[0xfe] && !ht216->ht_regs[0xf3] && svga->crtc[0x17] != 0xeb)
svga_writel_linear(addr, val, svga);
else {
ht216_write_common(ht216, addr, val);
ht216_write_common(ht216, addr + 1, val >> 8);
ht216_write_common(ht216, addr + 2, val >> 16);
ht216_write_common(ht216, addr + 3, val >> 24);
}
}
static void
ht216_write_linear(uint32_t addr, uint8_t val, void *priv)
{
ht216_t *ht216 = (ht216_t *) priv;
svga_t *svga = &ht216->svga;
addr -= ht216->linear_base;
if (!svga->chain4) /*Bits 16 and 17 of linear address are unused in planar modes*/
addr = (addr & 0xffff) | ((addr & 0xc0000) >> 2);
addr += ht216->write_banks[0];
if (!ht216->ht_regs[0xcd] && !ht216->ht_regs[0xfe])
svga_write_linear(addr, val, svga);
else
ht216_write_common(ht216, addr, val);
}
static void
ht216_writew_linear(uint32_t addr, uint16_t val, void *priv)
{
ht216_t *ht216 = (ht216_t *) priv;
svga_t *svga = &ht216->svga;
addr -= ht216->linear_base;
if (!svga->chain4) /*Bits 16 and 17 of linear address are unused in planar modes*/
addr = (addr & 0xffff) | ((addr & 0xc0000) >> 2);
addr += ht216->write_banks[0];
if (!ht216->ht_regs[0xcd] && !ht216->ht_regs[0xfe])
svga_writew_linear(addr, val, svga);
else {
ht216_write_common(ht216, addr, val);
ht216_write_common(ht216, addr + 1, val >> 8);
}
}
static void
ht216_writel_linear(uint32_t addr, uint32_t val, void *priv)
{
ht216_t *ht216 = (ht216_t *) priv;
svga_t *svga = &ht216->svga;
addr -= ht216->linear_base;
if (!svga->chain4) /*Bits 16 and 17 of linear address are unused in planar modes*/
addr = (addr & 0xffff) | ((addr & 0xc0000) >> 2);
addr += ht216->write_banks[0];
if (!ht216->ht_regs[0xcd] && !ht216->ht_regs[0xfe])
svga_writel_linear(addr, val, svga);
else {
ht216_write_common(ht216, addr, val);
ht216_write_common(ht216, addr + 1, val >> 8);
ht216_write_common(ht216, addr + 2, val >> 16);
ht216_write_common(ht216, addr + 3, val >> 24);
}
}
static uint8_t
ht216_read_common(ht216_t *ht216, uint32_t addr)
{
svga_t *svga = &ht216->svga;
uint32_t latch_addr = 0;
int offset;
int readplane = svga->readplane;
uint8_t or;
uint8_t count = 2;
uint8_t temp;
uint8_t ret;
if (ht216->ht_regs[0xc8] & HT_REG_C8_MOVSB)
addr <<= 3;
addr &= svga->vram_mask;
cycles -= video_timing_read_b;
count = (1 << count);
if (svga->chain4 && svga->packed_chain4) {
addr &= svga->decode_mask;
if (addr >= svga->vram_max)
return 0xff;
latch_addr = (addr & svga->vram_mask) & ~7;
if (ht216->ht_regs[0xcd] & HT_REG_CD_ASTODE)
latch_addr += (svga->gdcreg[3] & 7);
for (uint8_t i = 0; i < 8; i++)
ht216->bg_latch[i] = svga->vram[dword_remap(svga, latch_addr + i)];
return svga->vram[dword_remap(svga, addr) & svga->vram_mask];
} else if (svga->chain4) {
readplane = addr & 3;
addr = ((addr & 0xfffc) << 2) | ((addr & 0x30000) >> 14) | (addr & ~0x3ffff);
} else if (svga->chain2_read && (svga->crtc[0x17] != 0xeb)) {
readplane = (readplane & 2) | (addr & 1);
addr &= ~1;
addr <<= 2;
} else
addr <<= 2;
addr &= svga->decode_mask;
if (addr >= svga->vram_max)
return 0xff;
addr &= svga->vram_mask;
latch_addr = addr & ~7;
if (ht216->ht_regs[0xcd] & HT_REG_CD_ASTODE) {
offset = addr & 7;
for (uint8_t i = 0; i < 8; i++)
ht216->bg_latch[i] = svga->vram[latch_addr | ((offset + i) & 7)];
} else {
for (uint8_t i = 0; i < 8; i++)
ht216->bg_latch[i] = svga->vram[latch_addr | i];
}
or = addr & 4;
for (uint8_t i = 0; i < 4; i++)
svga->latch.b[i] = ht216->bg_latch[i | or ];
if (svga->readmode) {
temp = 0xff;
for (uint8_t pixel = 0; pixel < 8; pixel++) {
for (uint8_t plane = 0; plane < (uint8_t)(1 << count); plane++) {
if (svga->colournocare & (1 << plane)) {
/* If we care about a plane, and the pixel has a mismatch on it, clear its bit. */
if (((svga->latch.b[plane] >> pixel) & 1) != ((svga->colourcompare >> plane) & 1))
temp &= ~(1 << pixel);
}
}
}
ret = temp;
} else
ret = svga->vram[addr | readplane];
return ret;
}
static uint8_t
ht216_read(uint32_t addr, void *priv)
{
ht216_t *ht216 = (ht216_t *) priv;
const svga_t *svga = &ht216->svga;
uint32_t prev_addr = addr;
addr &= svga->banked_mask;
addr = (addr & 0x7fff) + ht216->read_banks[(addr >> 15) & 1];
if (svga->crtc[0x17] == 0xeb && !(svga->gdcreg[6] & 0xc) && prev_addr >= 0xb0000)
addr += 0x10000;
else if (svga->chain4 && ((ht216->ht_regs[0xfc] & 0x06) == 0x06))
addr = (addr & 0xfffeffff) | (prev_addr & 0x10000);
return ht216_read_common(ht216, addr);
}
static uint8_t
ht216_read_linear(uint32_t addr, void *priv)
{
ht216_t *ht216 = (ht216_t *) priv;
const svga_t *svga = &ht216->svga;
addr -= ht216->linear_base;
if (!svga->chain4) /*Bits 16 and 17 of linear address are unused in planar modes*/
addr = (addr & 0xffff) | ((addr & 0xc0000) >> 2);
addr += ht216->read_banks[0];
return ht216_read_common(ht216, addr);
}
static uint8_t
radius_mca_read(int port, void *priv)
{
const ht216_t *ht216 = (ht216_t *) priv;
ht216_log("Port %03x MCA read = %02x\n", port, ht216->pos_regs[port & 7]);
return (ht216->pos_regs[port & 7]);
}
static void
radius_mca_write(int port, uint8_t val, void *priv)
{
ht216_t *ht216 = (ht216_t *) priv;
/* MCA does not write registers below 0x0100. */
if (port < 0x0102)
return;
ht216_log("Port %03x MCA write = %02x, setup mode = %02x\n", port, val, ht216->ht_regs[0xfc] & 0x80);
/* Save the MCA register value. */
ht216->pos_regs[port & 7] = val;
}
static uint8_t
radius_mca_feedb(UNUSED(void *priv))
{
return 1;
}
void *
ht216_init(const device_t *info, uint32_t mem_size, int has_rom)
{
ht216_t *ht216 = malloc(sizeof(ht216_t));
svga_t *svga;
memset(ht216, 0, sizeof(ht216_t));
svga = &ht216->svga;
if (info->flags & DEVICE_VLB)
video_inform(VIDEO_FLAG_TYPE_SPECIAL, &timing_v7vga_vlb);
else if (info->flags & DEVICE_MCA)
video_inform(VIDEO_FLAG_TYPE_SPECIAL, &timing_v7vga_mca);
else
video_inform(VIDEO_FLAG_TYPE_SPECIAL, &timing_v7vga_isa);
svga_init(info, svga, ht216, mem_size,
ht216_recalctimings,
ht216_in, ht216_out,
ht216_hwcursor_draw,
NULL);
switch (has_rom) {
case 1:
rom_init(&ht216->bios_rom, BIOS_G2_GC205_PATH, 0xc0000, 0x8000, 0x7fff, 0, MEM_MAPPING_EXTERNAL);
break;
case 2:
rom_init(&ht216->bios_rom, BIOS_VIDEO7_VGA_1024I_PATH, 0xc0000, 0x8000, 0x7fff, 0, MEM_MAPPING_EXTERNAL);
break;
case 3:
ht216->monitor_type = device_get_config_int("monitor_type");
rom_init(&ht216->bios_rom, BIOS_HT216_32_PATH, 0xc0000, 0x8000, 0x7fff, 0, MEM_MAPPING_EXTERNAL);
/* Patch the BIOS for monitor type. */
if (ht216->monitor_type & 0x10) {
/* Color */
ht216->bios_rom.rom[0x0526] = 0x0c;
ht216->bios_rom.rom[0x0528] = 0xeb;
ht216->bios_rom.rom[0x7fff] += 0x26;
} else {
/* Mono */
ht216->bios_rom.rom[0x0526] = 0x24;
ht216->bios_rom.rom[0x0527] = 0xef;
ht216->bios_rom.rom[0x0528] = ht216->bios_rom.rom[0x0529] = 0x90;
ht216->bios_rom.rom[0x7fff] += 0xfe;
}
/* Patch bios for interlaced/non-interlaced. */
if (ht216->monitor_type & 0x08) {
/* Non-Interlaced */
ht216->bios_rom.rom[0x170b] = 0x0c;
ht216->bios_rom.rom[0x170d] = ht216->bios_rom.rom[0x170e] = 0x90;
ht216->bios_rom.rom[0x7fff] += 0xf4;
} else {
/* Interlaced */
ht216->bios_rom.rom[0x170b] = 0x24;
ht216->bios_rom.rom[0x170c] = 0xf7;
ht216->bios_rom.rom[0x170d] = 0xeb;
ht216->bios_rom.rom[0x7fff] += 0x1e;
}
break;
case 4:
if (info->local == 0x7152) {
if (info->flags & DEVICE_MCA) {
ht216->pos_regs[0] = 0xb7;
ht216->pos_regs[1] = 0x80;
mca_add(radius_mca_read, radius_mca_write, radius_mca_feedb, NULL, ht216);
} else
io_sethandler(0x0105, 0x0001, ht216_in, NULL, NULL, NULL, NULL, NULL, ht216);
}
rom_init(&ht216->bios_rom, BIOS_RADIUS_SVGA_MULTIVIEW_PATH, 0xc0000, 0x8000, 0x7fff, 0, MEM_MAPPING_EXTERNAL);
break;
default:
break;
}
svga->hwcursor.cur_ysize = 32;
ht216->vram_mask = mem_size - 1;
svga->decode_mask = mem_size - 1;
if (has_rom == 4)
svga->ramdac = device_add(&sc11484_nors2_ramdac_device);
if ((info->flags & DEVICE_VLB) || (info->flags & DEVICE_MCA)) {
mem_mapping_set_handler(&svga->mapping, ht216_read, NULL, NULL, ht216_write, ht216_writew, ht216_writel);
mem_mapping_add(&ht216->linear_mapping, 0, 0, ht216_read_linear, NULL, NULL, ht216_write_linear, ht216_writew_linear, ht216_writel_linear, NULL, MEM_MAPPING_EXTERNAL, svga);
} else {
mem_mapping_set_handler(&svga->mapping, ht216_read, NULL, NULL, ht216_write, ht216_writew, NULL);
mem_mapping_add(&ht216->linear_mapping, 0, 0, ht216_read_linear, NULL, NULL, ht216_write_linear, ht216_writew_linear, NULL, NULL, MEM_MAPPING_EXTERNAL, svga);
}
mem_mapping_set_p(&svga->mapping, ht216);
mem_mapping_disable(&ht216->linear_mapping);
ht216->id = info->local;
ht216->isabus = (info->flags & DEVICE_ISA);
ht216->mca = (info->flags & DEVICE_MCA);
io_sethandler(0x03c0, 0x0020, ht216_in, NULL, NULL, ht216_out, NULL, NULL, ht216);
io_sethandler(0x46e8, 0x0001, ht216_in, NULL, NULL, ht216_out, NULL, NULL, ht216);
svga->bpp = 8;
svga->miscout = 1;
if (ht216->id == 0x7861)
ht216->ht_regs[0xb4] = 0x08; /*32-bit DRAM bus*/
if (ht216->id == 0x7152)
ht216->reg_3cb = 0x20;
/* Initialize the cursor pointer towards the end of its segment, needed for ht256sf.drv to work correctly
when Windows 3.1 is started after boot. */
ht216->ht_regs[0x94] = 0xff;
svga->adv_flags = 0;
return ht216;
}
static void *
g2_gc205_init(const device_t *info)
{
ht216_t *ht216 = ht216_init(info, 1 << 19, 1);
return ht216;
}
static void *
v7_vga_1024i_init(const device_t *info)
{
ht216_t *ht216 = ht216_init(info, device_get_config_int("memory") << 10, 2);
return ht216;
}
static void *
ht216_pb410a_init(const device_t *info)
{
ht216_t *ht216 = ht216_init(info, 1 << 20, 0);
return ht216;
}
static void *
ht216_standalone_init(const device_t *info)
{
ht216_t *ht216 = ht216_init(info, 1 << 20, 3);
return ht216;
}
static void *
radius_svga_multiview_init(const device_t *info)
{
ht216_t *ht216 = ht216_init(info, 1 << 20, 4);
return ht216;
}
static int
g2_gc205_available(void)
{
return rom_present(BIOS_G2_GC205_PATH);
}
static int
v7_vga_1024i_available(void)
{
return rom_present(BIOS_VIDEO7_VGA_1024I_PATH);
}
static int
ht216_standalone_available(void)
{
return rom_present(BIOS_HT216_32_PATH);
}
static int
radius_svga_multiview_available(void)
{
return rom_present(BIOS_RADIUS_SVGA_MULTIVIEW_PATH);
}
void
ht216_close(void *priv)
{
ht216_t *ht216 = (ht216_t *) priv;
svga_close(&ht216->svga);
free(ht216);
}
void
ht216_speed_changed(void *priv)
{
ht216_t *ht216 = (ht216_t *) priv;
svga_recalctimings(&ht216->svga);
}
void
ht216_force_redraw(void *priv)
{
ht216_t *ht216 = (ht216_t *) priv;
ht216->svga.fullchange = changeframecount;
}
static const device_config_t v7_vga_1024i_config[] = {
{ .name = "memory",
.description = "Memory size",
.type = CONFIG_SELECTION,
.default_int = 512,
.selection = {
{ .description = "256 kB",
.value = 256 },
{ .description = "512 kB",
.value = 512 },
{ .description = "" } } },
{ .type = CONFIG_END }
};
// clang-format off
static const device_config_t ht216_32_standalone_config[] = {
{
.name = "monitor_type",
.description = "Monitor type",
.type = CONFIG_SELECTION,
.default_int = 0x18,
.selection = {
{
.description = "Mono Interlaced",
.value = 0x00
},
{
.description = "Mono Non-Interlaced",
.value = 0x08
},
{
.description = "Color Interlaced",
.value = 0x10
},
{
.description = "Color Non-Interlaced",
.value = 0x18
},
{
.description = ""
}
}
},
{
.type = CONFIG_END
}
};
// clang-format on
const device_t g2_gc205_device = {
.name = "G2 GC205",
.internal_name = "g2_gc205",
.flags = DEVICE_ISA,
.local = 0x7070,
.init = g2_gc205_init,
.close = ht216_close,
.reset = NULL,
{ .available = g2_gc205_available },
.speed_changed = ht216_speed_changed,
.force_redraw = ht216_force_redraw,
.config = NULL
};
const device_t v7_vga_1024i_device = {
.name = "Video 7 VGA 1024i (HT208)",
.internal_name = "v7_vga_1024i",
.flags = DEVICE_ISA,
.local = 0x7140,
.init = v7_vga_1024i_init,
.close = ht216_close,
.reset = NULL,
{ .available = v7_vga_1024i_available },
.speed_changed = ht216_speed_changed,
.force_redraw = ht216_force_redraw,
.config = v7_vga_1024i_config
};
const device_t ht216_32_pb410a_device = {
.name = "Headland HT216-32 (Packard Bell PB410A)",
.internal_name = "ht216_32_pb410a",
.flags = DEVICE_VLB,
.local = 0x7861, /*HT216-32*/
.init = ht216_pb410a_init,
.close = ht216_close,
.reset = NULL,
{ .available = NULL },
.speed_changed = ht216_speed_changed,
.force_redraw = ht216_force_redraw,
.config = NULL
};
const device_t ht216_32_standalone_device = {
.name = "Headland HT216-32",
.internal_name = "ht216_32",
.flags = DEVICE_VLB,
.local = 0x7861, /*HT216-32*/
.init = ht216_standalone_init,
.close = ht216_close,
.reset = NULL,
{ .available = ht216_standalone_available },
.speed_changed = ht216_speed_changed,
.force_redraw = ht216_force_redraw,
.config = ht216_32_standalone_config
};
const device_t radius_svga_multiview_isa_device = {
.name = "Radius SVGA Multiview ISA (HT209)",
.internal_name = "radius_isa",
.flags = DEVICE_ISA | DEVICE_AT,
.local = 0x7152, /*HT209*/
.init = radius_svga_multiview_init,
.close = ht216_close,
.reset = NULL,
{ .available = radius_svga_multiview_available },
.speed_changed = ht216_speed_changed,
.force_redraw = ht216_force_redraw,
.config = NULL
};
const device_t radius_svga_multiview_mca_device = {
.name = "Radius SVGA Multiview MCA (HT209)",
.internal_name = "radius_mc",
.flags = DEVICE_MCA,
.local = 0x7152, /*HT209*/
.init = radius_svga_multiview_init,
.close = ht216_close,
.reset = NULL,
{ .available = radius_svga_multiview_available },
.speed_changed = ht216_speed_changed,
.force_redraw = ht216_force_redraw,
.config = NULL
};
``` | /content/code_sandbox/src/video/vid_ht216.c | c | 2016-06-25T22:29:10 | 2024-08-16T19:09:21 | 86Box | 86Box/86Box | 2,616 | 20,593 |
```c
/*
* 86Box A hypervisor and IBM PC system emulator that specializes in
* running old operating systems and software designed for IBM
* PC systems and compatibles from 1981 through fairly recent
* system designs based on the PCI bus.
*
* This file is part of the 86Box distribution.
*
* SVGA renderers.
*
*
*
* Authors: Sarah Walker, <path_to_url
* Miran Grca, <mgrca8@gmail.com>
*
*/
#include <stdbool.h>
#include <stdio.h>
#include <stdint.h>
#include <string.h>
#include <wchar.h>
#include <86box/86box.h>
#include <86box/device.h>
#include <86box/mem.h>
#include <86box/timer.h>
#include <86box/video.h>
#include <86box/vid_svga.h>
#include <86box/vid_svga_render.h>
#include <86box/vid_svga_render_remap.h>
uint32_t
svga_lookup_lut_ram(svga_t* svga, uint32_t val)
{
if (!svga->lut_map)
return val;
uint8_t r = getcolr(svga->pallook[getcolr(val)]);
uint8_t g = getcolg(svga->pallook[getcolg(val)]);
uint8_t b = getcolb(svga->pallook[getcolb(val)]);
return makecol32(r, g, b) | (val & 0xFF000000);
}
#define lookup_lut(val) svga_lookup_lut_ram(svga, val)
void
svga_render_null(svga_t *svga)
{
if ((svga->displine + svga->y_add) < 0)
return;
if (svga->firstline_draw == 2000)
svga->firstline_draw = svga->displine;
svga->lastline_draw = svga->displine;
}
void
svga_render_blank(svga_t *svga)
{
if ((svga->displine + svga->y_add) < 0)
return;
if (svga->firstline_draw == 2000)
svga->firstline_draw = svga->displine;
svga->lastline_draw = svga->displine;
uint32_t char_width = 0;
switch (svga->seqregs[1] & 9) {
case 0:
char_width = 9;
break;
case 1:
char_width = 8;
break;
case 8:
char_width = 18;
break;
case 9:
char_width = 16;
break;
default:
break;
}
#if 0
pclog("svga->displine = %i, svga->y_add = %i, svga->x_add = %i\n", svga->displine, svga->y_add, svga->x_add);
#endif
uint32_t *line_ptr = &svga->monitor->target_buffer->line[svga->displine + svga->y_add][svga->x_add];
#if 0
pclog("svga->hdisp = %i, svga->scrollcache = %i, char_width = %i, sizeof(uint32_t) = %i\n", svga->hdisp, svga->scrollcache, char_width, sizeof(uint32_t));
#endif
uint32_t line_width = (uint32_t) (svga->hdisp + svga->scrollcache) * char_width * sizeof(uint32_t);
#if 0
pclog("line_width = %i\n", line_width);
#endif
if ((svga->hdisp + svga->scrollcache) > 0)
memset(line_ptr, 0, line_width);
}
void
svga_render_overscan_left(svga_t *svga)
{
if ((svga->displine + svga->y_add) < 0)
return;
if (svga->scrblank || (svga->hdisp <= 0))
return;
uint32_t *line_ptr = svga->monitor->target_buffer->line[svga->displine + svga->y_add];
for (int i = 0; i < svga->x_add; i++)
*line_ptr++ = svga->overscan_color;
}
void
svga_render_overscan_right(svga_t *svga)
{
int right;
if ((svga->displine + svga->y_add) < 0)
return;
if (svga->scrblank || (svga->hdisp <= 0))
return;
uint32_t *line_ptr = &svga->monitor->target_buffer->line[svga->displine + svga->y_add][svga->x_add + svga->hdisp];
right = (overscan_x >> 1);
for (int i = 0; i < right; i++)
*line_ptr++ = svga->overscan_color;
}
void
svga_render_text_40(svga_t *svga)
{
uint32_t *p;
int xx;
int drawcursor;
int xinc;
uint8_t chr;
uint8_t attr;
uint8_t dat;
uint32_t charaddr;
int fg;
int bg;
uint32_t addr = 0;
if ((svga->displine + svga->y_add) < 0)
return;
if (svga->firstline_draw == 2000)
svga->firstline_draw = svga->displine;
svga->lastline_draw = svga->displine;
if (svga->fullchange) {
p = &svga->monitor->target_buffer->line[svga->displine + svga->y_add][svga->x_add];
xinc = (svga->seqregs[1] & 1) ? 16 : 18;
for (int x = 0; x < (svga->hdisp + svga->scrollcache); x += xinc) {
if (!svga->force_old_addr)
addr = svga->remap_func(svga, svga->ma) & svga->vram_display_mask;
drawcursor = ((svga->ma == svga->ca) && svga->con && svga->cursoron);
if (svga->force_old_addr) {
chr = svga->vram[(svga->ma << 1) & svga->vram_display_mask];
attr = svga->vram[((svga->ma << 1) + 1) & svga->vram_display_mask];
} else {
chr = svga->vram[addr];
attr = svga->vram[addr + 1];
}
if (attr & 8)
charaddr = svga->charsetb + (chr * 128);
else
charaddr = svga->charseta + (chr * 128);
if (drawcursor) {
bg = svga->pallook[svga->egapal[attr & 15] & svga->dac_mask];
fg = svga->pallook[svga->egapal[attr >> 4] & svga->dac_mask];
} else {
fg = svga->pallook[svga->egapal[attr & 15] & svga->dac_mask];
bg = svga->pallook[svga->egapal[attr >> 4] & svga->dac_mask];
if (attr & 0x80 && svga->attrregs[0x10] & 8) {
bg = svga->pallook[svga->egapal[(attr >> 4) & 7] & svga->dac_mask];
if (svga->blink & 16)
fg = bg;
}
}
dat = svga->vram[charaddr + (svga->sc << 2)];
if (svga->seqregs[1] & 1) {
for (xx = 0; xx < 16; xx += 2)
p[xx] = p[xx + 1] = (dat & (0x80 >> (xx >> 1))) ? fg : bg;
} else {
for (xx = 0; xx < 16; xx += 2)
p[xx] = p[xx + 1] = (dat & (0x80 >> (xx >> 1))) ? fg : bg;
if ((chr & ~0x1f) != 0xc0 || !(svga->attrregs[0x10] & 4))
p[16] = p[17] = bg;
else
p[16] = p[17] = (dat & 1) ? fg : bg;
}
svga->ma += 4;
p += xinc;
}
svga->ma &= svga->vram_display_mask;
}
}
void
svga_render_text_80(svga_t *svga)
{
uint32_t *p;
int xx;
int drawcursor;
int xinc;
uint8_t chr;
uint8_t attr;
uint8_t dat;
uint32_t charaddr;
int fg;
int bg;
uint32_t addr = 0;
if ((svga->displine + svga->y_add) < 0)
return;
if (svga->firstline_draw == 2000)
svga->firstline_draw = svga->displine;
svga->lastline_draw = svga->displine;
if (svga->fullchange) {
p = &svga->monitor->target_buffer->line[svga->displine + svga->y_add][svga->x_add];
xinc = (svga->seqregs[1] & 1) ? 8 : 9;
for (int x = 0; x < (svga->hdisp + svga->scrollcache); x += xinc) {
if (!svga->force_old_addr)
addr = svga->remap_func(svga, svga->ma) & svga->vram_display_mask;
drawcursor = ((svga->ma == svga->ca) && svga->con && svga->cursoron);
if (svga->force_old_addr) {
chr = svga->vram[(svga->ma << 1) & svga->vram_display_mask];
attr = svga->vram[((svga->ma << 1) + 1) & svga->vram_display_mask];
} else {
chr = svga->vram[addr];
attr = svga->vram[addr + 1];
}
if (attr & 8)
charaddr = svga->charsetb + (chr * 128);
else
charaddr = svga->charseta + (chr * 128);
if (drawcursor) {
bg = svga->pallook[svga->egapal[attr & 15] & svga->dac_mask];
fg = svga->pallook[svga->egapal[attr >> 4] & svga->dac_mask];
} else {
fg = svga->pallook[svga->egapal[attr & 15] & svga->dac_mask];
bg = svga->pallook[svga->egapal[attr >> 4] & svga->dac_mask];
if (attr & 0x80 && svga->attrregs[0x10] & 8) {
bg = svga->pallook[svga->egapal[(attr >> 4) & 7] & svga->dac_mask];
if (svga->blink & 16)
fg = bg;
}
}
dat = svga->vram[charaddr + (svga->sc << 2)];
if (svga->seqregs[1] & 1) {
for (xx = 0; xx < 8; xx++)
p[xx] = (dat & (0x80 >> xx)) ? fg : bg;
} else {
for (xx = 0; xx < 8; xx++)
p[xx] = (dat & (0x80 >> xx)) ? fg : bg;
if ((chr & ~0x1F) != 0xC0 || !(svga->attrregs[0x10] & 4))
p[8] = bg;
else
p[8] = (dat & 1) ? fg : bg;
}
svga->ma += 4;
p += xinc;
}
svga->ma &= svga->vram_display_mask;
}
}
/*Not available on most generic cards.*/
void
svga_render_text_80_ksc5601(svga_t *svga)
{
uint32_t *p;
int xx;
int drawcursor;
int xinc;
uint8_t chr;
uint8_t attr;
uint8_t dat;
uint8_t nextchr;
uint32_t charaddr;
int fg;
int bg;
if ((svga->displine + svga->y_add) < 0)
return;
if (svga->firstline_draw == 2000)
svga->firstline_draw = svga->displine;
svga->lastline_draw = svga->displine;
if (svga->fullchange) {
p = &svga->monitor->target_buffer->line[svga->displine + svga->y_add][svga->x_add];
xinc = (svga->seqregs[1] & 1) ? 8 : 9;
for (int x = 0; x < (svga->hdisp + svga->scrollcache); x += xinc) {
uint32_t addr = svga->remap_func(svga, svga->ma) & svga->vram_display_mask;
drawcursor = ((svga->ma == svga->ca) && svga->con && svga->cursoron);
chr = svga->vram[addr];
nextchr = svga->vram[addr + 8];
attr = svga->vram[addr + 1];
if (drawcursor) {
bg = svga->pallook[svga->egapal[attr & 15] & svga->dac_mask];
fg = svga->pallook[svga->egapal[attr >> 4] & svga->dac_mask];
} else {
fg = svga->pallook[svga->egapal[attr & 15] & svga->dac_mask];
bg = svga->pallook[svga->egapal[attr >> 4] & svga->dac_mask];
if (attr & 0x80 && svga->attrregs[0x10] & 8) {
bg = svga->pallook[svga->egapal[(attr >> 4) & 7] & svga->dac_mask];
if (svga->blink & 16)
fg = bg;
}
}
if ((x + xinc) < svga->hdisp && (chr & (nextchr | svga->ksc5601_sbyte_mask) & 0x80)) {
if ((chr == svga->ksc5601_udc_area_msb[0] || chr == svga->ksc5601_udc_area_msb[1]) && (nextchr > 0xa0 && nextchr < 0xff))
dat = fontdatksc5601_user[(chr == svga->ksc5601_udc_area_msb[1] ? 96 : 0) + (nextchr & 0x7F) - 0x20].chr[svga->sc];
else if (nextchr & 0x80) {
if (svga->ksc5601_swap_mode == 1 && (nextchr > 0xa0 && nextchr < 0xff)) {
if (chr >= 0x80 && chr < 0x99)
chr += 0x30;
else if (chr >= 0xB0 && chr < 0xC9)
chr -= 0x30;
}
dat = fontdatksc5601[((chr & 0x7F) << 7) | (nextchr & 0x7F)].chr[svga->sc];
} else
dat = 0xff;
} else {
if (attr & 8)
charaddr = svga->charsetb + (chr * 128);
else
charaddr = svga->charseta + (chr * 128);
if ((svga->ksc5601_english_font_type >> 8) == 1)
dat = fontdatksc5601[((svga->ksc5601_english_font_type & 0x7F) << 7) | (chr >> 1)].chr[((chr & 1) << 4) | svga->sc];
else
dat = svga->vram[charaddr + (svga->sc << 2)];
}
if (svga->seqregs[1] & 1) {
for (xx = 0; xx < 8; xx++)
p[xx] = (dat & (0x80 >> xx)) ? fg : bg;
} else {
for (xx = 0; xx < 8; xx++)
p[xx] = (dat & (0x80 >> xx)) ? fg : bg;
if (((chr & ~0x1f) != 0xc0) || !(svga->attrregs[0x10] & 4))
p[8] = bg;
else
p[8] = (dat & 1) ? fg : bg;
}
svga->ma += 4;
p += xinc;
if ((x + xinc) < svga->hdisp && (chr & (nextchr | svga->ksc5601_sbyte_mask) & 0x80)) {
attr = svga->vram[((svga->ma << 1) + 1) & svga->vram_display_mask];
if (drawcursor) {
bg = svga->pallook[svga->egapal[attr & 15] & svga->dac_mask];
fg = svga->pallook[svga->egapal[attr >> 4] & svga->dac_mask];
} else {
fg = svga->pallook[svga->egapal[attr & 15] & svga->dac_mask];
bg = svga->pallook[svga->egapal[attr >> 4] & svga->dac_mask];
if (attr & 0x80 && svga->attrregs[0x10] & 8) {
bg = svga->pallook[svga->egapal[(attr >> 4) & 7] & svga->dac_mask];
if (svga->blink & 16)
fg = bg;
}
}
if ((chr == svga->ksc5601_udc_area_msb[0] || chr == svga->ksc5601_udc_area_msb[1]) && (nextchr > 0xa0 && nextchr < 0xff))
dat = fontdatksc5601_user[(chr == svga->ksc5601_udc_area_msb[1] ? 96 : 0) + (nextchr & 0x7F) - 0x20].chr[svga->sc + 16];
else if (nextchr & 0x80)
dat = fontdatksc5601[((chr & 0x7f) << 7) | (nextchr & 0x7F)].chr[svga->sc + 16];
else
dat = 0xff;
if (svga->seqregs[1] & 1) {
for (xx = 0; xx < 8; xx++)
p[xx] = (dat & (0x80 >> xx)) ? fg : bg;
} else {
for (xx = 0; xx < 8; xx++)
p[xx] = (dat & (0x80 >> xx)) ? fg : bg;
if (((chr & ~0x1f) != 0xc0) || !(svga->attrregs[0x10] & 4))
p[8] = bg;
else
p[8] = (dat & 1) ? fg : bg;
}
svga->ma += 4;
p += xinc;
x += xinc;
}
}
svga->ma &= svga->vram_display_mask;
}
}
void
svga_render_2bpp_s3_lowres(svga_t *svga)
{
int changed_offset;
int x;
uint8_t dat[2];
uint32_t addr;
uint32_t *p;
uint32_t changed_addr;
if ((svga->displine + svga->y_add) < 0)
return;
if (svga->force_old_addr) {
changed_offset = ((svga->ma << 1) + (svga->sc & ~svga->crtc[0x17] & 3) * 0x8000) >> 12;
if (svga->changedvram[changed_offset] || svga->changedvram[changed_offset + 1] || svga->fullchange) {
p = &svga->monitor->target_buffer->line[svga->displine + svga->y_add][svga->x_add];
if (svga->firstline_draw == 2000)
svga->firstline_draw = svga->displine;
svga->lastline_draw = svga->displine;
for (x = 0; x <= (svga->hdisp + svga->scrollcache); x += 16) {
addr = svga->ma;
if (!(svga->crtc[0x17] & 0x40)) {
addr = (addr << 1) & svga->vram_mask;
addr &= ~7;
if ((svga->crtc[0x17] & 0x20) && (svga->ma & 0x20000))
addr |= 4;
if (!(svga->crtc[0x17] & 0x20) && (svga->ma & 0x8000))
addr |= 4;
}
if (!(svga->crtc[0x17] & 0x01))
addr = (addr & ~0x8000) | ((svga->sc & 1) ? 0x8000 : 0);
if (!(svga->crtc[0x17] & 0x02))
addr = (addr & ~0x10000) | ((svga->sc & 2) ? 0x10000 : 0);
dat[0] = svga->vram[addr];
dat[1] = svga->vram[addr | 0x1];
if (svga->seqregs[1] & 4)
svga->ma += 2;
else
svga->ma += 4;
svga->ma &= svga->vram_mask;
p[0] = p[1] = svga->pallook[svga->egapal[(dat[0] >> 6) & 3] & svga->dac_mask];
p[2] = p[3] = svga->pallook[svga->egapal[(dat[0] >> 4) & 3] & svga->dac_mask];
p[4] = p[5] = svga->pallook[svga->egapal[(dat[0] >> 2) & 3] & svga->dac_mask];
p[6] = p[7] = svga->pallook[svga->egapal[dat[0] & 3] & svga->dac_mask];
p[8] = p[9] = svga->pallook[svga->egapal[(dat[1] >> 6) & 3] & svga->dac_mask];
p[10] = p[11] = svga->pallook[svga->egapal[(dat[1] >> 4) & 3] & svga->dac_mask];
p[12] = p[13] = svga->pallook[svga->egapal[(dat[1] >> 2) & 3] & svga->dac_mask];
p[14] = p[15] = svga->pallook[svga->egapal[dat[1] & 3] & svga->dac_mask];
p += 16;
}
}
} else {
changed_addr = svga->remap_func(svga, svga->ma);
if (svga->changedvram[changed_addr >> 12] || svga->changedvram[(changed_addr >> 12) + 1] || svga->fullchange) {
p = &svga->monitor->target_buffer->line[svga->displine + svga->y_add][svga->x_add];
if (svga->firstline_draw == 2000)
svga->firstline_draw = svga->displine;
svga->lastline_draw = svga->displine;
for (x = 0; x <= (svga->hdisp + svga->scrollcache); x += 16) {
addr = svga->remap_func(svga, svga->ma);
dat[0] = svga->vram[addr];
dat[1] = svga->vram[addr | 0x1];
if (svga->seqregs[1] & 4)
svga->ma += 2;
else
svga->ma += 4;
svga->ma &= svga->vram_mask;
p[0] = p[1] = svga->pallook[svga->egapal[(dat[0] >> 6) & 3] & svga->dac_mask];
p[2] = p[3] = svga->pallook[svga->egapal[(dat[0] >> 4) & 3] & svga->dac_mask];
p[4] = p[5] = svga->pallook[svga->egapal[(dat[0] >> 2) & 3] & svga->dac_mask];
p[6] = p[7] = svga->pallook[svga->egapal[dat[0] & 3] & svga->dac_mask];
p[8] = p[9] = svga->pallook[svga->egapal[(dat[1] >> 6) & 3] & svga->dac_mask];
p[10] = p[11] = svga->pallook[svga->egapal[(dat[1] >> 4) & 3] & svga->dac_mask];
p[12] = p[13] = svga->pallook[svga->egapal[(dat[1] >> 2) & 3] & svga->dac_mask];
p[14] = p[15] = svga->pallook[svga->egapal[dat[1] & 3] & svga->dac_mask];
p += 16;
}
}
}
}
void
svga_render_2bpp_s3_highres(svga_t *svga)
{
int changed_offset;
int x;
uint8_t dat[2];
uint32_t addr;
uint32_t *p;
uint32_t changed_addr;
if ((svga->displine + svga->y_add) < 0)
return;
if (svga->force_old_addr) {
changed_offset = ((svga->ma << 1) + (svga->sc & ~svga->crtc[0x17] & 3) * 0x8000) >> 12;
if (svga->changedvram[changed_offset] || svga->changedvram[changed_offset + 1] || svga->fullchange) {
p = &svga->monitor->target_buffer->line[svga->displine + svga->y_add][svga->x_add];
if (svga->firstline_draw == 2000)
svga->firstline_draw = svga->displine;
svga->lastline_draw = svga->displine;
for (x = 0; x <= (svga->hdisp + svga->scrollcache); x += 8) {
addr = svga->ma;
if (!(svga->crtc[0x17] & 0x40)) {
addr = (addr << 1) & svga->vram_mask;
addr &= ~7;
if ((svga->crtc[0x17] & 0x20) && (svga->ma & 0x20000))
addr |= 4;
if (!(svga->crtc[0x17] & 0x20) && (svga->ma & 0x8000))
addr |= 4;
}
if (!(svga->crtc[0x17] & 0x01))
addr = (addr & ~0x8000) | ((svga->sc & 1) ? 0x8000 : 0);
if (!(svga->crtc[0x17] & 0x02))
addr = (addr & ~0x10000) | ((svga->sc & 2) ? 0x10000 : 0);
dat[0] = svga->vram[addr];
dat[1] = svga->vram[addr | 0x1];
if (svga->seqregs[1] & 4)
svga->ma += 2;
else
svga->ma += 4;
svga->ma &= svga->vram_mask;
p[0] = svga->pallook[svga->egapal[(dat[0] >> 6) & 3] & svga->dac_mask];
p[1] = svga->pallook[svga->egapal[(dat[0] >> 4) & 3] & svga->dac_mask];
p[2] = svga->pallook[svga->egapal[(dat[0] >> 2) & 3] & svga->dac_mask];
p[3] = svga->pallook[svga->egapal[dat[0] & 3] & svga->dac_mask];
p[4] = svga->pallook[svga->egapal[(dat[1] >> 6) & 3] & svga->dac_mask];
p[5] = svga->pallook[svga->egapal[(dat[1] >> 4) & 3] & svga->dac_mask];
p[6] = svga->pallook[svga->egapal[(dat[1] >> 2) & 3] & svga->dac_mask];
p[7] = svga->pallook[svga->egapal[dat[1] & 3] & svga->dac_mask];
p += 8;
}
}
} else {
changed_addr = svga->remap_func(svga, svga->ma);
if (svga->changedvram[changed_addr >> 12] || svga->changedvram[(changed_addr >> 12) + 1] || svga->fullchange) {
p = &svga->monitor->target_buffer->line[svga->displine + svga->y_add][svga->x_add];
if (svga->firstline_draw == 2000)
svga->firstline_draw = svga->displine;
svga->lastline_draw = svga->displine;
for (x = 0; x <= (svga->hdisp + svga->scrollcache); x += 8) {
addr = svga->remap_func(svga, svga->ma);
dat[0] = svga->vram[addr];
dat[1] = svga->vram[addr | 0x1];
if (svga->seqregs[1] & 4)
svga->ma += 2;
else
svga->ma += 4;
svga->ma &= svga->vram_mask;
p[0] = svga->pallook[svga->egapal[(dat[0] >> 6) & 3] & svga->dac_mask];
p[1] = svga->pallook[svga->egapal[(dat[0] >> 4) & 3] & svga->dac_mask];
p[2] = svga->pallook[svga->egapal[(dat[0] >> 2) & 3] & svga->dac_mask];
p[3] = svga->pallook[svga->egapal[dat[0] & 3] & svga->dac_mask];
p[4] = svga->pallook[svga->egapal[(dat[1] >> 6) & 3] & svga->dac_mask];
p[5] = svga->pallook[svga->egapal[(dat[1] >> 4) & 3] & svga->dac_mask];
p[6] = svga->pallook[svga->egapal[(dat[1] >> 2) & 3] & svga->dac_mask];
p[7] = svga->pallook[svga->egapal[dat[1] & 3] & svga->dac_mask];
p += 8;
}
}
}
}
void
svga_render_2bpp_headland_highres(svga_t *svga)
{
int oddeven;
uint32_t addr;
uint32_t *p;
uint8_t edat[4];
uint8_t dat;
uint32_t changed_addr;
if ((svga->displine + svga->y_add) < 0)
return;
changed_addr = svga->remap_func(svga, svga->ma);
if (svga->changedvram[changed_addr >> 12] || svga->changedvram[(changed_addr >> 12) + 1] || svga->fullchange) {
p = &svga->monitor->target_buffer->line[svga->displine + svga->y_add][svga->x_add];
if (svga->firstline_draw == 2000)
svga->firstline_draw = svga->displine;
svga->lastline_draw = svga->displine;
for (int x = 0; x <= (svga->hdisp + svga->scrollcache); x += 8) {
addr = svga->remap_func(svga, svga->ma);
oddeven = 0;
if (svga->seqregs[1] & 4) {
oddeven = (addr & 4) ? 1 : 0;
edat[0] = svga->vram[addr | oddeven];
edat[2] = svga->vram[addr | oddeven | 0x2];
edat[1] = edat[3] = 0;
} else {
*(uint32_t *) (&edat[0]) = *(uint32_t *) (&svga->vram[addr]);
}
svga->ma += 4;
svga->ma &= svga->vram_mask;
dat = edatlookup[edat[0] >> 6][edat[1] >> 6] | (edatlookup[edat[2] >> 6][edat[3] >> 6] << 2);
p[0] = svga->pallook[svga->egapal[(dat >> 4) & svga->plane_mask] & svga->dac_mask];
p[1] = svga->pallook[svga->egapal[dat & svga->plane_mask] & svga->dac_mask];
dat = edatlookup[(edat[0] >> 4) & 3][(edat[1] >> 4) & 3] | (edatlookup[(edat[2] >> 4) & 3][(edat[3] >> 4) & 3] << 2);
p[2] = svga->pallook[svga->egapal[(dat >> 4) & svga->plane_mask] & svga->dac_mask];
p[3] = svga->pallook[svga->egapal[dat & svga->plane_mask] & svga->dac_mask];
dat = edatlookup[(edat[0] >> 2) & 3][(edat[1] >> 2) & 3] | (edatlookup[(edat[2] >> 2) & 3][(edat[3] >> 2) & 3] << 2);
p[4] = svga->pallook[svga->egapal[(dat >> 4) & svga->plane_mask] & svga->dac_mask];
p[5] = svga->pallook[svga->egapal[dat & svga->plane_mask] & svga->dac_mask];
dat = edatlookup[edat[0] & 3][edat[1] & 3] | (edatlookup[edat[2] & 3][edat[3] & 3] << 2);
p[6] = svga->pallook[svga->egapal[(dat >> 4) & svga->plane_mask] & svga->dac_mask];
p[7] = svga->pallook[svga->egapal[dat & svga->plane_mask] & svga->dac_mask];
p += 8;
}
}
}
static void
svga_render_indexed_gfx(svga_t *svga, bool highres, bool combine8bits)
{
int x;
uint32_t addr;
uint32_t *p;
uint32_t changed_offset;
const bool blinked = !!(svga->blink & 0x10);
const bool attrblink = (!svga->disable_blink) && ((svga->attrregs[0x10] & 0x08) != 0);
/*
The following is likely how it works on an IBM VGA - that is, it works with its BIOS.
But on some cards, certain modes are broken.
- S3 Trio: mode 13h (320x200x8), incbypow2 given as 2 treated as 0
- ET4000/W32i: mode 2Eh (640x480x8), incevery given as 2 treated as 1
*/
const bool forcepacked = combine8bits && (svga->force_old_addr || svga->packed_chain4);
/*
SVGA cards with a high-resolution 8bpp mode may actually bypass the VGA shifter logic.
- HT-216 (+ other Video7 chipsets?) has 0x3C4.0xC8 bit 4 which, when set to 1, loads
bytes directly, bypassing the shifters.
*/
const bool highres8bpp = combine8bits && highres;
const bool dwordload = ((svga->seqregs[0x01] & 0x10) != 0);
const bool wordload = ((svga->seqregs[0x01] & 0x04) != 0) && !dwordload;
const bool wordincr = ((svga->crtc[0x17] & 0x08) != 0);
const bool dwordincr = ((svga->crtc[0x14] & 0x20) != 0) && !wordincr;
const bool dwordshift = ((svga->crtc[0x14] & 0x40) != 0);
const bool wordshift = ((svga->crtc[0x17] & 0x40) == 0) && !dwordshift;
const uint32_t incbypow2 = forcepacked ? 0 : (dwordshift ? 2 : wordshift ? 1 : 0);
const uint32_t incevery = forcepacked ? 1 : (dwordincr ? 4 : wordincr ? 2 : 1);
const uint32_t loadevery = forcepacked ? 1 : (dwordload ? 4 : wordload ? 2 : 1);
const bool shift4bit = ((svga->gdcreg[0x05] & 0x40) == 0x40) || highres8bpp;
const bool shift2bit = (((svga->gdcreg[0x05] & 0x60) == 0x20) && !shift4bit);
const int dwshift = highres ? 0 : 1;
const int dotwidth = 1 << dwshift;
const int charwidth = dotwidth * ((combine8bits && !svga->packed_4bpp) ? 4 : 8);
const uint32_t planemask = 0x11111111 * (uint32_t) (svga->plane_mask);
const uint32_t blinkmask = (attrblink ? 0x88888888 : 0x0);
const uint32_t blinkval = (attrblink && blinked ? 0x88888888 : 0x0);
/*
This is actually a 8x 3-bit lookup table,
preshifted by 2 bits to allow shifting by multiples of 4 bits.
Anyway, when we perform a planar-to-chunky conversion,
we keep the pixel values in a scrambled order.
This lookup table unscrambles them.
WARNING: Octal values are used here!
*/
const uint32_t shift_values = (shift4bit
? ((067452301) << 2)
: shift2bit
? ((026370415) << 2)
: ((002461357) << 2));
if ((svga->displine + svga->y_add) < 0)
return;
if (svga->force_old_addr)
changed_offset = (svga->ma + (svga->sc & ~svga->crtc[0x17] & 3) * 0x8000) >> 12;
else
changed_offset = svga->remap_func(svga, svga->ma) >> 12;
if (!(svga->changedvram[changed_offset] || svga->changedvram[changed_offset + 1] || svga->fullchange))
return;
p = &svga->monitor->target_buffer->line[svga->displine + svga->y_add][svga->x_add];
if (svga->firstline_draw == 2000)
svga->firstline_draw = svga->displine;
svga->lastline_draw = svga->displine;
uint32_t incr_counter = 0;
uint32_t load_counter = 0;
uint32_t edat = 0;
for (x = 0; x <= (svga->hdisp + svga->scrollcache); x += charwidth) {
if (load_counter == 0) {
/* Find our address */
if (svga->force_old_addr) {
addr = ((svga->ma & ~0x3) << incbypow2);
if (incbypow2 == 2) {
if (svga->ma & (4 << 15))
addr |= 0x8;
if (svga->ma & (4 << 14))
addr |= 0x4;
} else if (incbypow2 == 1) {
if ((svga->crtc[0x17] & 0x20)) {
if (svga->ma & (4 << 15))
addr |= 0x4;
} else {
if (svga->ma & (4 << 13))
addr |= 0x4;
}
} else {
/* Nothing */
}
if (!(svga->crtc[0x17] & 0x01))
addr = (addr & ~0x8000) | ((svga->sc & 1) ? 0x8000 : 0);
if (!(svga->crtc[0x17] & 0x02))
addr = (addr & ~0x10000) | ((svga->sc & 2) ? 0x10000 : 0);
} else if (svga->remap_required)
addr = svga->remap_func(svga, svga->ma);
else
addr = svga->ma;
addr &= svga->vram_display_mask;
/* Load VRAM */
edat = *(uint32_t *) &svga->vram[addr];
/*
EGA and VGA actually use 4bpp planar as its native format.
But 4bpp chunky is generally easier to deal with on a modern CPU.
shift4bit is the native format for this renderer (4bpp chunky).
*/
if (svga->ati_4color || !shift4bit) {
if (shift2bit && !svga->ati_4color) {
/* Group 2x 2bpp values into 4bpp values */
edat = (edat & 0xCCCC3333) | ((edat << 14) & 0x33330000) | ((edat >> 14) & 0x0000CCCC);
} else {
/* Group 4x 1bpp values into 4bpp values */
edat = (edat & 0xAA55AA55) | ((edat << 7) & 0x55005500) | ((edat >> 7) & 0x00AA00AA);
edat = (edat & 0xCCCC3333) | ((edat << 14) & 0x33330000) | ((edat >> 14) & 0x0000CCCC);
}
}
} else {
/*
According to the 82C451 VGA clone chipset datasheet, all 4 planes chain in a ring.
So, rotate them all around.
Planar version: edat = (edat >> 8) | (edat << 24);
Here's the chunky version...
*/
edat = ((edat >> 1) & 0x77777777) | ((edat << 3) & 0x88888888);
}
load_counter += 1;
if (load_counter >= loadevery)
load_counter = 0;
incr_counter += 1;
if (incr_counter >= incevery) {
incr_counter = 0;
svga->ma += 4;
/* DISCREPANCY TODO FIXME 2/4bpp used vram_mask, 8bpp used vram_display_mask --GM */
svga->ma &= svga->vram_display_mask;
}
uint32_t current_shift = shift_values;
uint32_t out_edat = edat;
/*
Apply blink
FIXME: Confirm blink behaviour on real hardware
The VGA 4bpp graphics blink logic was a pain to work out.
If plane 3 is enabled in the attribute controller, then:
- if bit 3 is 0, then we force the output of it to be 1.
- if bit 3 is 1, then the output blinks.
This can be tested with Lotus 1-2-3 release 2.3 with the WYSIWYG addon.
If plane 3 is disabled in the attribute controller, then the output blinks.
This can be tested with QBASIC SCREEN 10 - anything using color #2 should
blink and nothing else.
If you can simplify the following and have it still work, give yourself a medal.
*/
out_edat = ((out_edat & planemask & ~blinkmask) | ((out_edat | ~planemask) & blinkmask & blinkval)) ^ blinkmask;
for (int i = 0; i < (8 + (svga->ati_4color ? 8 : 0)); i += (svga->ati_4color ? 4 : 2)) {
/*
c0 denotes the first 4bpp pixel shifted, while c1 denotes the second.
For 8bpp modes, the first 4bpp pixel is the upper 4 bits.
*/
uint32_t c0 = (out_edat >> (current_shift & 0x1C)) & 0xF;
current_shift >>= 3;
uint32_t c1 = (out_edat >> (current_shift & 0x1C)) & 0xF;
current_shift >>= 3;
if (svga->ati_4color) {
uint32_t q[4];
q[0] = svga->pallook[svga->egapal[(c0 & 0x0c) >> 2]];
q[1] = svga->pallook[svga->egapal[c0 & 0x03]];
q[2] = svga->pallook[svga->egapal[(c1 & 0x0c) >> 2]];
q[3] = svga->pallook[svga->egapal[c1 & 0x03]];
const int outoffs = i << dwshift;
for (int ch = 0; ch < 4; ch++) {
for (int subx = 0; subx < dotwidth; subx++)
p[outoffs + subx + (dotwidth * ch)] = q[ch];
}
} else if (combine8bits) {
if (svga->packed_4bpp) {
uint32_t p0 = svga->map8[c0 & svga->dac_mask];
uint32_t p1 = svga->map8[c1 & svga->dac_mask];
const int outoffs = i << dwshift;
for (int subx = 0; subx < dotwidth; subx++)
p[outoffs + subx] = p0;
for (int subx = 0; subx < dotwidth; subx++)
p[outoffs + subx + dotwidth] = p1;
} else {
uint32_t ccombined = (c0 << 4) | c1;
uint32_t p0 = svga->map8[ccombined & svga->dac_mask];
const int outoffs = (i >> 1) << dwshift;
for (int subx = 0; subx < dotwidth; subx++)
p[outoffs + subx] = p0;
}
} else {
uint32_t p0 = svga->pallook[svga->egapal[c0] & svga->dac_mask];
uint32_t p1 = svga->pallook[svga->egapal[c1] & svga->dac_mask];
const int outoffs = i << dwshift;
for (int subx = 0; subx < dotwidth; subx++)
p[outoffs + subx] = p0;
for (int subx = 0; subx < dotwidth; subx++)
p[outoffs + subx + dotwidth] = p1;
}
}
if (svga->ati_4color)
p += (charwidth << 1);
// p += charwidth;
else
p += charwidth;
}
}
/*
Remap these to the paletted renderer
(*, highres, combine8bits)
*/
void svga_render_2bpp_lowres(svga_t *svga) { svga_render_indexed_gfx(svga, false, false); }
void svga_render_2bpp_highres(svga_t *svga) { svga_render_indexed_gfx(svga, true, false); }
void svga_render_4bpp_lowres(svga_t *svga) { svga_render_indexed_gfx(svga, false, false); }
void svga_render_4bpp_highres(svga_t *svga) { svga_render_indexed_gfx(svga, true, false); }
void svga_render_8bpp_lowres(svga_t *svga) { svga_render_indexed_gfx(svga, false, true); }
void svga_render_8bpp_highres(svga_t *svga) { svga_render_indexed_gfx(svga, true, true); }
void
svga_render_8bpp_clone_highres(svga_t *svga)
{
int x;
uint32_t *p;
uint32_t dat;
uint32_t changed_addr;
uint32_t addr;
if ((svga->displine + svga->y_add) < 0)
return;
if (svga->force_old_addr) {
if (svga->changedvram[svga->ma >> 12] || svga->changedvram[(svga->ma >> 12) + 1] || svga->fullchange) {
p = &svga->monitor->target_buffer->line[svga->displine + svga->y_add][svga->x_add];
if (svga->firstline_draw == 2000)
svga->firstline_draw = svga->displine;
svga->lastline_draw = svga->displine;
for (x = 0; x <= (svga->hdisp /* + svga->scrollcache*/); x += 8) {
dat = *(uint32_t *) (&svga->vram[svga->ma & svga->vram_display_mask]);
p[0] = svga->map8[dat & svga->dac_mask & 0xff];
p[1] = svga->map8[(dat >> 8) & svga->dac_mask & 0xff];
p[2] = svga->map8[(dat >> 16) & svga->dac_mask & 0xff];
p[3] = svga->map8[(dat >> 24) & svga->dac_mask & 0xff];
dat = *(uint32_t *) (&svga->vram[(svga->ma + 4) & svga->vram_display_mask]);
p[4] = svga->map8[dat & svga->dac_mask & 0xff];
p[5] = svga->map8[(dat >> 8) & svga->dac_mask & 0xff];
p[6] = svga->map8[(dat >> 16) & svga->dac_mask & 0xff];
p[7] = svga->map8[(dat >> 24) & svga->dac_mask & 0xff];
svga->ma += 8;
p += 8;
}
svga->ma &= svga->vram_display_mask;
}
} else {
changed_addr = svga->remap_func(svga, svga->ma);
if (svga->changedvram[changed_addr >> 12] || svga->changedvram[(changed_addr >> 12) + 1] || svga->fullchange) {
p = &svga->monitor->target_buffer->line[svga->displine + svga->y_add][svga->x_add];
if (svga->firstline_draw == 2000)
svga->firstline_draw = svga->displine;
svga->lastline_draw = svga->displine;
if (!svga->remap_required) {
for (x = 0; x <= (svga->hdisp /* + svga->scrollcache*/); x += 8) {
dat = *(uint32_t *) (&svga->vram[svga->ma & svga->vram_display_mask]);
p[0] = svga->map8[dat & svga->dac_mask & 0xff];
p[1] = svga->map8[(dat >> 8) & svga->dac_mask & 0xff];
p[2] = svga->map8[(dat >> 16) & svga->dac_mask & 0xff];
p[3] = svga->map8[(dat >> 24) & svga->dac_mask & 0xff];
dat = *(uint32_t *) (&svga->vram[(svga->ma + 4) & svga->vram_display_mask]);
p[4] = svga->map8[dat & svga->dac_mask & 0xff];
p[5] = svga->map8[(dat >> 8) & svga->dac_mask & 0xff];
p[6] = svga->map8[(dat >> 16) & svga->dac_mask & 0xff];
p[7] = svga->map8[(dat >> 24) & svga->dac_mask & 0xff];
svga->ma += 8;
p += 8;
}
} else {
for (x = 0; x <= (svga->hdisp /* + svga->scrollcache*/); x += 4) {
addr = svga->remap_func(svga, svga->ma);
dat = *(uint32_t *) (&svga->vram[addr & svga->vram_display_mask]);
p[0] = svga->map8[dat & svga->dac_mask & 0xff];
p[1] = svga->map8[(dat >> 8) & svga->dac_mask & 0xff];
p[2] = svga->map8[(dat >> 16) & svga->dac_mask & 0xff];
p[3] = svga->map8[(dat >> 24) & svga->dac_mask & 0xff];
svga->ma += 4;
p += 4;
}
}
svga->ma &= svga->vram_display_mask;
}
}
}
// TODO: Integrate more of this into the generic paletted renderer --GM
#if 0
void
svga_render_8bpp_lowres(svga_t *svga)
{
int x;
uint32_t *p;
uint32_t dat;
uint32_t changed_addr;
uint32_t addr;
if ((svga->displine + svga->y_add) < 0)
return;
if (svga->force_old_addr) {
if (svga->changedvram[svga->ma >> 12] || svga->changedvram[(svga->ma >> 12) + 1] || svga->fullchange) {
p = &svga->monitor->target_buffer->line[svga->displine + svga->y_add][svga->x_add];
if (svga->firstline_draw == 2000)
svga->firstline_draw = svga->displine;
svga->lastline_draw = svga->displine;
for (x = 0; x <= (svga->hdisp + svga->scrollcache); x += 8) {
dat = *(uint32_t *) (&svga->vram[svga->ma & svga->vram_display_mask]);
p[0] = p[1] = svga->map8[dat & 0xff];
p[2] = p[3] = svga->map8[(dat >> 8) & 0xff];
p[4] = p[5] = svga->map8[(dat >> 16) & 0xff];
p[6] = p[7] = svga->map8[(dat >> 24) & 0xff];
svga->ma += 4;
p += 8;
}
svga->ma &= svga->vram_display_mask;
}
} else {
changed_addr = svga->remap_func(svga, svga->ma);
if (svga->changedvram[changed_addr >> 12] || svga->changedvram[(changed_addr >> 12) + 1] || svga->fullchange) {
p = &svga->monitor->target_buffer->line[svga->displine + svga->y_add][svga->x_add];
if (svga->firstline_draw == 2000)
svga->firstline_draw = svga->displine;
svga->lastline_draw = svga->displine;
if (!svga->remap_required) {
for (x = 0; x <= (svga->hdisp + svga->scrollcache); x += 8) {
dat = *(uint32_t *) (&svga->vram[svga->ma & svga->vram_display_mask]);
p[0] = p[1] = svga->map8[dat & svga->dac_mask & 0xff];
p[2] = p[3] = svga->map8[(dat >> 8) & svga->dac_mask & 0xff];
p[4] = p[5] = svga->map8[(dat >> 16) & svga->dac_mask & 0xff];
p[6] = p[7] = svga->map8[(dat >> 24) & svga->dac_mask & 0xff];
svga->ma += 4;
p += 8;
}
} else {
for (x = 0; x <= (svga->hdisp + svga->scrollcache); x += 8) {
addr = svga->remap_func(svga, svga->ma);
dat = *(uint32_t *) (&svga->vram[addr & svga->vram_display_mask]);
p[0] = p[1] = svga->map8[dat & svga->dac_mask & 0xff];
p[2] = p[3] = svga->map8[(dat >> 8) & svga->dac_mask & 0xff];
p[4] = p[5] = svga->map8[(dat >> 16) & svga->dac_mask & 0xff];
p[6] = p[7] = svga->map8[(dat >> 24) & svga->dac_mask & 0xff];
svga->ma += 4;
p += 8;
}
}
svga->ma &= svga->vram_display_mask;
}
}
}
void
svga_render_8bpp_highres(svga_t *svga)
{
int x;
uint32_t *p;
uint32_t dat;
uint32_t changed_addr;
uint32_t addr;
if ((svga->displine + svga->y_add) < 0)
return;
if (svga->force_old_addr) {
if (svga->changedvram[svga->ma >> 12] || svga->changedvram[(svga->ma >> 12) + 1] || svga->fullchange) {
p = &svga->monitor->target_buffer->line[svga->displine + svga->y_add][svga->x_add];
if (svga->firstline_draw == 2000)
svga->firstline_draw = svga->displine;
svga->lastline_draw = svga->displine;
for (x = 0; x <= (svga->hdisp /* + svga->scrollcache*/); x += 8) {
dat = *(uint32_t *) (&svga->vram[svga->ma & svga->vram_display_mask]);
p[0] = svga->map8[dat & svga->dac_mask & 0xff];
p[1] = svga->map8[(dat >> 8) & svga->dac_mask & 0xff];
p[2] = svga->map8[(dat >> 16) & svga->dac_mask & 0xff];
p[3] = svga->map8[(dat >> 24) & svga->dac_mask & 0xff];
dat = *(uint32_t *) (&svga->vram[(svga->ma + 4) & svga->vram_display_mask]);
p[4] = svga->map8[dat & svga->dac_mask & 0xff];
p[5] = svga->map8[(dat >> 8) & svga->dac_mask & 0xff];
p[6] = svga->map8[(dat >> 16) & svga->dac_mask & 0xff];
p[7] = svga->map8[(dat >> 24) & svga->dac_mask & 0xff];
svga->ma += 8;
p += 8;
}
svga->ma &= svga->vram_display_mask;
}
} else {
changed_addr = svga->remap_func(svga, svga->ma);
if (svga->changedvram[changed_addr >> 12] || svga->changedvram[(changed_addr >> 12) + 1] || svga->fullchange) {
p = &svga->monitor->target_buffer->line[svga->displine + svga->y_add][svga->x_add];
if (svga->firstline_draw == 2000)
svga->firstline_draw = svga->displine;
svga->lastline_draw = svga->displine;
if (!svga->remap_required) {
for (x = 0; x <= (svga->hdisp /* + svga->scrollcache*/); x += 8) {
dat = *(uint32_t *) (&svga->vram[svga->ma & svga->vram_display_mask]);
p[0] = svga->map8[dat & svga->dac_mask & 0xff];
p[1] = svga->map8[(dat >> 8) & svga->dac_mask & 0xff];
p[2] = svga->map8[(dat >> 16) & svga->dac_mask & 0xff];
p[3] = svga->map8[(dat >> 24) & svga->dac_mask & 0xff];
dat = *(uint32_t *) (&svga->vram[(svga->ma + 4) & svga->vram_display_mask]);
p[4] = svga->map8[dat & svga->dac_mask & 0xff];
p[5] = svga->map8[(dat >> 8) & svga->dac_mask & 0xff];
p[6] = svga->map8[(dat >> 16) & svga->dac_mask & 0xff];
p[7] = svga->map8[(dat >> 24) & svga->dac_mask & 0xff];
svga->ma += 8;
p += 8;
}
} else {
for (x = 0; x <= (svga->hdisp /* + svga->scrollcache*/); x += 4) {
addr = svga->remap_func(svga, svga->ma);
dat = *(uint32_t *) (&svga->vram[addr & svga->vram_display_mask]);
p[0] = svga->map8[dat & svga->dac_mask & 0xff];
p[1] = svga->map8[(dat >> 8) & svga->dac_mask & 0xff];
p[2] = svga->map8[(dat >> 16) & svga->dac_mask & 0xff];
p[3] = svga->map8[(dat >> 24) & svga->dac_mask & 0xff];
svga->ma += 4;
p += 4;
}
}
svga->ma &= svga->vram_display_mask;
}
}
}
#endif
void
svga_render_8bpp_tseng_lowres(svga_t *svga)
{
uint32_t *p;
uint32_t dat;
if ((svga->displine + svga->y_add) < 0)
return;
if (svga->changedvram[svga->ma >> 12] || svga->changedvram[(svga->ma >> 12) + 1] || svga->fullchange) {
p = &svga->monitor->target_buffer->line[svga->displine + svga->y_add][svga->x_add];
if (svga->firstline_draw == 2000)
svga->firstline_draw = svga->displine;
svga->lastline_draw = svga->displine;
for (int x = 0; x <= (svga->hdisp + svga->scrollcache); x += 8) {
dat = *(uint32_t *) (&svga->vram[svga->ma & svga->vram_display_mask]);
if (svga->attrregs[0x10] & 0x80)
dat = (dat & ~0xf0) | ((svga->attrregs[0x14] & 0x0f) << 4);
p[0] = p[1] = svga->map8[dat & svga->dac_mask & 0xff];
dat >>= 8;
if (svga->attrregs[0x10] & 0x80)
dat = (dat & ~0xf0) | ((svga->attrregs[0x14] & 0x0f) << 4);
p[2] = p[3] = svga->map8[dat & svga->dac_mask & 0xff];
dat >>= 8;
if (svga->attrregs[0x10] & 0x80)
dat = (dat & ~0xf0) | ((svga->attrregs[0x14] & 0x0f) << 4);
p[4] = p[5] = svga->map8[dat & svga->dac_mask & 0xff];
dat >>= 8;
if (svga->attrregs[0x10] & 0x80)
dat = (dat & ~0xf0) | ((svga->attrregs[0x14] & 0x0f) << 4);
p[6] = p[7] = svga->map8[dat & svga->dac_mask & 0xff];
svga->ma += 4;
p += 8;
}
svga->ma &= svga->vram_display_mask;
}
}
void
svga_render_8bpp_tseng_highres(svga_t *svga)
{
uint32_t *p;
uint32_t dat;
if ((svga->displine + svga->y_add) < 0)
return;
if (svga->changedvram[svga->ma >> 12] || svga->changedvram[(svga->ma >> 12) + 1] || svga->fullchange) {
p = &svga->monitor->target_buffer->line[svga->displine + svga->y_add][svga->x_add];
if (svga->firstline_draw == 2000)
svga->firstline_draw = svga->displine;
svga->lastline_draw = svga->displine;
for (int x = 0; x <= (svga->hdisp /* + svga->scrollcache*/); x += 8) {
dat = *(uint32_t *) (&svga->vram[svga->ma & svga->vram_display_mask]);
if (svga->attrregs[0x10] & 0x80)
dat = (dat & ~0xf0) | ((svga->attrregs[0x14] & 0x0f) << 4);
p[0] = svga->map8[dat & svga->dac_mask & 0xff];
dat >>= 8;
if (svga->attrregs[0x10] & 0x80)
dat = (dat & ~0xf0) | ((svga->attrregs[0x14] & 0x0f) << 4);
p[1] = svga->map8[dat & svga->dac_mask & 0xff];
dat >>= 8;
if (svga->attrregs[0x10] & 0x80)
dat = (dat & ~0xf0) | ((svga->attrregs[0x14] & 0x0f) << 4);
p[2] = svga->map8[dat & svga->dac_mask & 0xff];
dat >>= 8;
if (svga->attrregs[0x10] & 0x80)
dat = (dat & ~0xf0) | ((svga->attrregs[0x14] & 0x0f) << 4);
p[3] = svga->map8[dat & svga->dac_mask & 0xff];
dat = *(uint32_t *) (&svga->vram[(svga->ma + 4) & svga->vram_display_mask]);
if (svga->attrregs[0x10] & 0x80)
dat = (dat & ~0xf0) | ((svga->attrregs[0x14] & 0x0f) << 4);
p[4] = svga->map8[dat & svga->dac_mask & 0xff];
dat >>= 8;
if (svga->attrregs[0x10] & 0x80)
dat = (dat & ~0xf0) | ((svga->attrregs[0x14] & 0x0f) << 4);
p[5] = svga->map8[dat & svga->dac_mask & 0xff];
dat >>= 8;
if (svga->attrregs[0x10] & 0x80)
dat = (dat & ~0xf0) | ((svga->attrregs[0x14] & 0x0f) << 4);
p[6] = svga->map8[dat & svga->dac_mask & 0xff];
dat >>= 8;
if (svga->attrregs[0x10] & 0x80)
dat = (dat & ~0xf0) | ((svga->attrregs[0x14] & 0x0f) << 4);
p[7] = svga->map8[dat & svga->dac_mask & 0xff];
svga->ma += 8;
p += 8;
}
svga->ma &= svga->vram_display_mask;
}
}
void
svga_render_15bpp_lowres(svga_t *svga)
{
int x;
uint32_t *p;
uint32_t dat;
uint32_t changed_addr;
uint32_t addr;
if ((svga->displine + svga->y_add) < 0)
return;
if (svga->force_old_addr) {
if (svga->changedvram[svga->ma >> 12] || svga->changedvram[(svga->ma >> 12) + 1] || svga->fullchange) {
p = &svga->monitor->target_buffer->line[svga->displine + svga->y_add][svga->x_add];
if (svga->firstline_draw == 2000)
svga->firstline_draw = svga->displine;
svga->lastline_draw = svga->displine;
for (x = 0; x <= (svga->hdisp + svga->scrollcache); x += 4) {
dat = *(uint32_t *) (&svga->vram[(svga->ma + (x << 1)) & svga->vram_display_mask]);
p[x << 1] = p[(x << 1) + 1] = svga->conv_16to32(svga, dat & 0xffff, 15);
p[(x << 1) + 2] = p[(x << 1) + 3] = svga->conv_16to32(svga, dat >> 16, 15);
dat = *(uint32_t *) (&svga->vram[(svga->ma + (x << 1) + 4) & svga->vram_display_mask]);
p[(x << 1) + 4] = p[(x << 1) + 5] = svga->conv_16to32(svga, dat & 0xffff, 15);
p[(x << 1) + 6] = p[(x << 1) + 7] = svga->conv_16to32(svga, dat >> 16, 15);
}
svga->ma += x << 1;
svga->ma &= svga->vram_display_mask;
}
} else {
changed_addr = svga->remap_func(svga, svga->ma);
if (svga->changedvram[changed_addr >> 12] || svga->changedvram[(changed_addr >> 12) + 1] || svga->fullchange) {
p = &svga->monitor->target_buffer->line[svga->displine + svga->y_add][svga->x_add];
if (svga->firstline_draw == 2000)
svga->firstline_draw = svga->displine;
svga->lastline_draw = svga->displine;
if (!svga->remap_required) {
for (x = 0; x <= (svga->hdisp + svga->scrollcache); x += 4) {
dat = *(uint32_t *) (&svga->vram[(svga->ma + (x << 1)) & svga->vram_display_mask]);
*p++ = svga->conv_16to32(svga, dat & 0xffff, 15);
*p++ = svga->conv_16to32(svga, dat >> 16, 15);
dat = *(uint32_t *) (&svga->vram[(svga->ma + (x << 1) + 4) & svga->vram_display_mask]);
*p++ = svga->conv_16to32(svga, dat & 0xffff, 15);
*p++ = svga->conv_16to32(svga, dat >> 16, 15);
}
svga->ma += x << 1;
} else {
for (x = 0; x <= (svga->hdisp + svga->scrollcache); x += 2) {
addr = svga->remap_func(svga, svga->ma);
dat = *(uint32_t *) (&svga->vram[addr & svga->vram_display_mask]);
*p++ = svga->conv_16to32(svga, dat & 0xffff, 15);
*p++ = svga->conv_16to32(svga, dat >> 16, 15);
svga->ma += 4;
}
}
svga->ma &= svga->vram_display_mask;
}
}
}
void
svga_render_15bpp_highres(svga_t *svga)
{
int x;
uint32_t *p;
uint32_t dat;
uint32_t changed_addr;
uint32_t addr;
if ((svga->displine + svga->y_add) < 0)
return;
if (svga->force_old_addr) {
if (svga->changedvram[svga->ma >> 12] || svga->changedvram[(svga->ma >> 12) + 1] || svga->fullchange) {
p = &svga->monitor->target_buffer->line[svga->displine + svga->y_add][svga->x_add];
if (svga->firstline_draw == 2000)
svga->firstline_draw = svga->displine;
svga->lastline_draw = svga->displine;
for (x = 0; x <= (svga->hdisp + svga->scrollcache); x += 8) {
dat = *(uint32_t *) (&svga->vram[(svga->ma + (x << 1)) & svga->vram_display_mask]);
p[x] = svga->conv_16to32(svga, dat & 0xffff, 15);
p[x + 1] = svga->conv_16to32(svga, dat >> 16, 15);
dat = *(uint32_t *) (&svga->vram[(svga->ma + (x << 1) + 4) & svga->vram_display_mask]);
p[x + 2] = svga->conv_16to32(svga, dat & 0xffff, 15);
p[x + 3] = svga->conv_16to32(svga, dat >> 16, 15);
dat = *(uint32_t *) (&svga->vram[(svga->ma + (x << 1) + 8) & svga->vram_display_mask]);
p[x + 4] = svga->conv_16to32(svga, dat & 0xffff, 15);
p[x + 5] = svga->conv_16to32(svga, dat >> 16, 15);
dat = *(uint32_t *) (&svga->vram[(svga->ma + (x << 1) + 12) & svga->vram_display_mask]);
p[x + 6] = svga->conv_16to32(svga, dat & 0xffff, 15);
p[x + 7] = svga->conv_16to32(svga, dat >> 16, 15);
}
svga->ma += x << 1;
svga->ma &= svga->vram_display_mask;
}
} else {
changed_addr = svga->remap_func(svga, svga->ma);
if (svga->changedvram[changed_addr >> 12] || svga->changedvram[(changed_addr >> 12) + 1] || svga->fullchange) {
p = &svga->monitor->target_buffer->line[svga->displine + svga->y_add][svga->x_add];
if (svga->firstline_draw == 2000)
svga->firstline_draw = svga->displine;
svga->lastline_draw = svga->displine;
if (!svga->remap_required) {
for (x = 0; x <= (svga->hdisp + svga->scrollcache); x += 8) {
dat = *(uint32_t *) (&svga->vram[(svga->ma + (x << 1)) & svga->vram_display_mask]);
*p++ = svga->conv_16to32(svga, dat & 0xffff, 15);
*p++ = svga->conv_16to32(svga, dat >> 16, 15);
dat = *(uint32_t *) (&svga->vram[(svga->ma + (x << 1) + 4) & svga->vram_display_mask]);
*p++ = svga->conv_16to32(svga, dat & 0xffff, 15);
*p++ = svga->conv_16to32(svga, dat >> 16, 15);
dat = *(uint32_t *) (&svga->vram[(svga->ma + (x << 1) + 8) & svga->vram_display_mask]);
*p++ = svga->conv_16to32(svga, dat & 0xffff, 15);
*p++ = svga->conv_16to32(svga, dat >> 16, 15);
dat = *(uint32_t *) (&svga->vram[(svga->ma + (x << 1) + 12) & svga->vram_display_mask]);
*p++ = svga->conv_16to32(svga, dat & 0xffff, 15);
*p++ = svga->conv_16to32(svga, dat >> 16, 15);
}
svga->ma += x << 1;
} else {
for (x = 0; x <= (svga->hdisp + svga->scrollcache); x += 2) {
addr = svga->remap_func(svga, svga->ma);
dat = *(uint32_t *) (&svga->vram[addr & svga->vram_display_mask]);
*p++ = svga->conv_16to32(svga, dat & 0xffff, 15);
*p++ = svga->conv_16to32(svga, dat >> 16, 15);
svga->ma += 4;
}
}
svga->ma &= svga->vram_display_mask;
}
}
}
void
svga_render_15bpp_mix_lowres(svga_t *svga)
{
int x;
uint32_t *p;
uint32_t dat;
if ((svga->displine + svga->y_add) < 0)
return;
if (svga->changedvram[svga->ma >> 12] || svga->changedvram[(svga->ma >> 12) + 1] || svga->fullchange) {
p = &svga->monitor->target_buffer->line[svga->displine + svga->y_add][svga->x_add];
if (svga->firstline_draw == 2000)
svga->firstline_draw = svga->displine;
svga->lastline_draw = svga->displine;
for (x = 0; x <= (svga->hdisp + svga->scrollcache); x += 4) {
dat = *(uint32_t *) (&svga->vram[(svga->ma + (x << 1)) & svga->vram_display_mask]);
p[x << 1] = p[(x << 1) + 1] = (dat & 0x00008000) ? svga->pallook[dat & 0xff] : svga->conv_16to32(svga, dat & 0xffff, 15);
dat >>= 16;
p[(x << 1) + 2] = p[(x << 1) + 3] = (dat & 0x00008000) ? svga->pallook[dat & 0xff] : svga->conv_16to32(svga, dat & 0xffff, 15);
dat = *(uint32_t *) (&svga->vram[(svga->ma + (x << 1) + 4) & svga->vram_display_mask]);
p[(x << 1) + 4] = p[(x << 1) + 5] = (dat & 0x00008000) ? svga->pallook[dat & 0xff] : svga->conv_16to32(svga, dat & 0xffff, 15);
dat >>= 16;
p[(x << 1) + 6] = p[(x << 1) + 7] = (dat & 0x00008000) ? svga->pallook[dat & 0xff] : svga->conv_16to32(svga, dat & 0xffff, 15);
}
svga->ma += x << 1;
svga->ma &= svga->vram_display_mask;
}
}
void
svga_render_15bpp_mix_highres(svga_t *svga)
{
int x;
uint32_t *p;
uint32_t dat;
if ((svga->displine + svga->y_add) < 0)
return;
if (svga->changedvram[svga->ma >> 12] || svga->changedvram[(svga->ma >> 12) + 1] || svga->fullchange) {
p = &svga->monitor->target_buffer->line[svga->displine + svga->y_add][svga->x_add];
if (svga->firstline_draw == 2000)
svga->firstline_draw = svga->displine;
svga->lastline_draw = svga->displine;
for (x = 0; x <= (svga->hdisp + svga->scrollcache); x += 8) {
dat = *(uint32_t *) (&svga->vram[(svga->ma + (x << 1)) & svga->vram_display_mask]);
p[x] = (dat & 0x00008000) ? svga->pallook[dat & 0xff] : svga->conv_16to32(svga, dat & 0xffff, 15);
dat >>= 16;
p[x + 1] = (dat & 0x00008000) ? svga->pallook[dat & 0xff] : svga->conv_16to32(svga, dat & 0xffff, 15);
dat = *(uint32_t *) (&svga->vram[(svga->ma + (x << 1) + 4) & svga->vram_display_mask]);
p[x + 2] = (dat & 0x00008000) ? svga->pallook[dat & 0xff] : svga->conv_16to32(svga, dat & 0xffff, 15);
dat >>= 16;
p[x + 3] = (dat & 0x00008000) ? svga->pallook[dat & 0xff] : svga->conv_16to32(svga, dat & 0xffff, 15);
dat = *(uint32_t *) (&svga->vram[(svga->ma + (x << 1) + 8) & svga->vram_display_mask]);
p[x + 4] = (dat & 0x00008000) ? svga->pallook[dat & 0xff] : svga->conv_16to32(svga, dat & 0xffff, 15);
dat >>= 16;
p[x + 5] = (dat & 0x00008000) ? svga->pallook[dat & 0xff] : svga->conv_16to32(svga, dat & 0xffff, 15);
dat = *(uint32_t *) (&svga->vram[(svga->ma + (x << 1) + 12) & svga->vram_display_mask]);
p[x + 6] = (dat & 0x00008000) ? svga->pallook[dat & 0xff] : svga->conv_16to32(svga, dat & 0xffff, 15);
dat >>= 16;
p[x + 7] = (dat & 0x00008000) ? svga->pallook[dat & 0xff] : svga->conv_16to32(svga, dat & 0xffff, 15);
}
svga->ma += x << 1;
svga->ma &= svga->vram_display_mask;
}
}
void
svga_render_16bpp_lowres(svga_t *svga)
{
int x;
uint32_t *p;
uint32_t dat;
uint32_t changed_addr;
uint32_t addr;
if ((svga->displine + svga->y_add) < 0)
return;
if (svga->force_old_addr) {
if (svga->changedvram[svga->ma >> 12] || svga->changedvram[(svga->ma >> 12) + 1] || svga->fullchange) {
p = &svga->monitor->target_buffer->line[svga->displine + svga->y_add][svga->x_add];
if (svga->firstline_draw == 2000)
svga->firstline_draw = svga->displine;
svga->lastline_draw = svga->displine;
for (x = 0; x <= (svga->hdisp + svga->scrollcache); x += 4) {
dat = *(uint32_t *) (&svga->vram[(svga->ma + (x << 1)) & svga->vram_display_mask]);
p[x << 1] = p[(x << 1) + 1] = svga->conv_16to32(svga, dat & 0xffff, 16);
p[(x << 1) + 2] = p[(x << 1) + 3] = svga->conv_16to32(svga, dat >> 16, 16);
dat = *(uint32_t *) (&svga->vram[(svga->ma + (x << 1) + 4) & svga->vram_display_mask]);
p[(x << 1) + 4] = p[(x << 1) + 5] = svga->conv_16to32(svga, dat & 0xffff, 16);
p[(x << 1) + 6] = p[(x << 1) + 7] = svga->conv_16to32(svga, dat >> 16, 16);
}
svga->ma += x << 1;
svga->ma &= svga->vram_display_mask;
}
} else {
changed_addr = svga->remap_func(svga, svga->ma);
if (svga->changedvram[changed_addr >> 12] || svga->changedvram[(changed_addr >> 12) + 1] || svga->fullchange) {
p = &svga->monitor->target_buffer->line[svga->displine + svga->y_add][svga->x_add];
if (svga->firstline_draw == 2000)
svga->firstline_draw = svga->displine;
svga->lastline_draw = svga->displine;
if (!svga->remap_required) {
for (x = 0; x <= (svga->hdisp + svga->scrollcache); x += 4) {
dat = *(uint32_t *) (&svga->vram[(svga->ma + (x << 1)) & svga->vram_display_mask]);
*p++ = svga->conv_16to32(svga, dat & 0xffff, 16);
*p++ = svga->conv_16to32(svga, dat >> 16, 16);
dat = *(uint32_t *) (&svga->vram[(svga->ma + (x << 1) + 4) & svga->vram_display_mask]);
*p++ = svga->conv_16to32(svga, dat & 0xffff, 16);
*p++ = svga->conv_16to32(svga, dat >> 16, 16);
}
svga->ma += x << 1;
} else {
for (x = 0; x <= (svga->hdisp + svga->scrollcache); x += 2) {
addr = svga->remap_func(svga, svga->ma);
dat = *(uint32_t *) (&svga->vram[addr & svga->vram_display_mask]);
*p++ = svga->conv_16to32(svga, dat & 0xffff, 16);
*p++ = svga->conv_16to32(svga, dat >> 16, 16);
}
svga->ma += 4;
}
svga->ma &= svga->vram_display_mask;
}
}
}
void
svga_render_16bpp_highres(svga_t *svga)
{
int x;
uint32_t *p;
uint32_t dat;
uint32_t changed_addr;
uint32_t addr;
if ((svga->displine + svga->y_add) < 0)
return;
if (svga->force_old_addr) {
if (svga->changedvram[svga->ma >> 12] || svga->changedvram[(svga->ma >> 12) + 1] || svga->fullchange) {
p = &svga->monitor->target_buffer->line[svga->displine + svga->y_add][svga->x_add];
if (svga->firstline_draw == 2000)
svga->firstline_draw = svga->displine;
svga->lastline_draw = svga->displine;
for (x = 0; x <= (svga->hdisp + svga->scrollcache); x += 8) {
uint32_t dat = *(uint32_t *) (&svga->vram[(svga->ma + (x << 1)) & svga->vram_display_mask]);
p[x] = svga->conv_16to32(svga, dat & 0xffff, 16);
p[x + 1] = svga->conv_16to32(svga, dat >> 16, 16);
dat = *(uint32_t *) (&svga->vram[(svga->ma + (x << 1) + 4) & svga->vram_display_mask]);
p[x + 2] = svga->conv_16to32(svga, dat & 0xffff, 16);
p[x + 3] = svga->conv_16to32(svga, dat >> 16, 16);
dat = *(uint32_t *) (&svga->vram[(svga->ma + (x << 1) + 8) & svga->vram_display_mask]);
p[x + 4] = svga->conv_16to32(svga, dat & 0xffff, 16);
p[x + 5] = svga->conv_16to32(svga, dat >> 16, 16);
dat = *(uint32_t *) (&svga->vram[(svga->ma + (x << 1) + 12) & svga->vram_display_mask]);
p[x + 6] = svga->conv_16to32(svga, dat & 0xffff, 16);
p[x + 7] = svga->conv_16to32(svga, dat >> 16, 16);
}
svga->ma += x << 1;
svga->ma &= svga->vram_display_mask;
}
} else {
changed_addr = svga->remap_func(svga, svga->ma);
if (svga->changedvram[changed_addr >> 12] || svga->changedvram[(changed_addr >> 12) + 1] || svga->fullchange) {
p = &svga->monitor->target_buffer->line[svga->displine + svga->y_add][svga->x_add];
if (svga->firstline_draw == 2000)
svga->firstline_draw = svga->displine;
svga->lastline_draw = svga->displine;
if (!svga->remap_required) {
for (x = 0; x <= (svga->hdisp + svga->scrollcache); x += 8) {
dat = *(uint32_t *) (&svga->vram[(svga->ma + (x << 1)) & svga->vram_display_mask]);
*p++ = svga->conv_16to32(svga, dat & 0xffff, 16);
*p++ = svga->conv_16to32(svga, dat >> 16, 16);
dat = *(uint32_t *) (&svga->vram[(svga->ma + (x << 1) + 4) & svga->vram_display_mask]);
*p++ = svga->conv_16to32(svga, dat & 0xffff, 16);
*p++ = svga->conv_16to32(svga, dat >> 16, 16);
dat = *(uint32_t *) (&svga->vram[(svga->ma + (x << 1) + 8) & svga->vram_display_mask]);
*p++ = svga->conv_16to32(svga, dat & 0xffff, 16);
*p++ = svga->conv_16to32(svga, dat >> 16, 16);
dat = *(uint32_t *) (&svga->vram[(svga->ma + (x << 1) + 12) & svga->vram_display_mask]);
*p++ = svga->conv_16to32(svga, dat & 0xffff, 16);
*p++ = svga->conv_16to32(svga, dat >> 16, 16);
}
svga->ma += x << 1;
} else {
for (x = 0; x <= (svga->hdisp + svga->scrollcache); x += 2) {
addr = svga->remap_func(svga, svga->ma);
dat = *(uint32_t *) (&svga->vram[addr & svga->vram_display_mask]);
*p++ = svga->conv_16to32(svga, dat & 0xffff, 16);
*p++ = svga->conv_16to32(svga, dat >> 16, 16);
svga->ma += 4;
}
}
svga->ma &= svga->vram_display_mask;
}
}
}
void
svga_render_24bpp_lowres(svga_t *svga)
{
int x;
uint32_t *p;
uint32_t changed_addr;
uint32_t addr;
uint32_t dat0;
uint32_t dat1;
uint32_t dat2;
uint32_t fg;
if ((svga->displine + svga->y_add) < 0)
return;
if (svga->force_old_addr) {
if ((svga->displine + svga->y_add) < 0)
return;
if (svga->changedvram[svga->ma >> 12] || svga->changedvram[(svga->ma >> 12) + 1] || svga->fullchange) {
if (svga->firstline_draw == 2000)
svga->firstline_draw = svga->displine;
svga->lastline_draw = svga->displine;
for (x = 0; x <= (svga->hdisp + svga->scrollcache); x++) {
fg = svga->vram[svga->ma] | (svga->vram[svga->ma + 1] << 8) | (svga->vram[svga->ma + 2] << 16);
svga->ma += 3;
svga->ma &= svga->vram_display_mask;
svga->monitor->target_buffer->line[svga->displine + svga->y_add][(x << 1) + svga->x_add] = svga->monitor->target_buffer->line[svga->displine + svga->y_add][(x << 1) + 1 + svga->x_add] = lookup_lut(fg);
}
}
} else {
changed_addr = svga->remap_func(svga, svga->ma);
if (svga->changedvram[changed_addr >> 12] || svga->changedvram[(changed_addr >> 12) + 1] || svga->fullchange) {
p = &svga->monitor->target_buffer->line[svga->displine + svga->y_add][svga->x_add];
if (svga->firstline_draw == 2000)
svga->firstline_draw = svga->displine;
svga->lastline_draw = svga->displine;
if (!svga->remap_required) {
for (x = 0; x <= (svga->hdisp + svga->scrollcache); x++) {
dat0 = *(uint32_t *) (&svga->vram[svga->ma & svga->vram_display_mask]);
dat1 = *(uint32_t *) (&svga->vram[(svga->ma + 4) & svga->vram_display_mask]);
dat2 = *(uint32_t *) (&svga->vram[(svga->ma + 8) & svga->vram_display_mask]);
p[0] = p[1] = lookup_lut(dat0 & 0xffffff);
p[2] = p[3] = lookup_lut((dat0 >> 24) | ((dat1 & 0xffff) << 8));
p[4] = p[5] = lookup_lut((dat1 >> 16) | ((dat2 & 0xff) << 16));
p[6] = p[7] = lookup_lut(dat2 >> 8);
svga->ma += 12;
}
} else {
for (x = 0; x <= (svga->hdisp + svga->scrollcache); x += 4) {
addr = svga->remap_func(svga, svga->ma);
dat0 = *(uint32_t *) (&svga->vram[addr & svga->vram_display_mask]);
addr = svga->remap_func(svga, svga->ma + 4);
dat1 = *(uint32_t *) (&svga->vram[addr & svga->vram_display_mask]);
addr = svga->remap_func(svga, svga->ma + 8);
dat2 = *(uint32_t *) (&svga->vram[addr & svga->vram_display_mask]);
p[0] = p[1] = lookup_lut(dat0 & 0xffffff);
p[2] = p[3] = lookup_lut((dat0 >> 24) | ((dat1 & 0xffff) << 8));
p[4] = p[5] = lookup_lut((dat1 >> 16) | ((dat2 & 0xff) << 16));
p[6] = p[7] = lookup_lut(dat2 >> 8);
svga->ma += 12;
}
}
svga->ma &= svga->vram_display_mask;
}
}
}
void
svga_render_24bpp_highres(svga_t *svga)
{
int x;
uint32_t *p;
uint32_t changed_addr;
uint8_t addr;
uint32_t dat0;
uint32_t dat1;
uint32_t dat2;
uint32_t dat;
if ((svga->displine + svga->y_add) < 0)
return;
if (svga->force_old_addr) {
if (svga->changedvram[svga->ma >> 12] || svga->changedvram[(svga->ma >> 12) + 1] || svga->fullchange) {
p = &svga->monitor->target_buffer->line[svga->displine + svga->y_add][svga->x_add];
if (svga->firstline_draw == 2000)
svga->firstline_draw = svga->displine;
svga->lastline_draw = svga->displine;
for (x = 0; x <= (svga->hdisp + svga->scrollcache); x += 4) {
dat = *(uint32_t *) (&svga->vram[svga->ma & svga->vram_display_mask]);
p[x] = lookup_lut(dat & 0xffffff);
dat = *(uint32_t *) (&svga->vram[(svga->ma + 3) & svga->vram_display_mask]);
p[x + 1] = lookup_lut(dat & 0xffffff);
dat = *(uint32_t *) (&svga->vram[(svga->ma + 6) & svga->vram_display_mask]);
p[x + 2] = lookup_lut(dat & 0xffffff);
dat = *(uint32_t *) (&svga->vram[(svga->ma + 9) & svga->vram_display_mask]);
p[x + 3] = lookup_lut(dat & 0xffffff);
svga->ma += 12;
}
svga->ma &= svga->vram_display_mask;
}
} else {
changed_addr = svga->remap_func(svga, svga->ma);
if (svga->changedvram[changed_addr >> 12] || svga->changedvram[(changed_addr >> 12) + 1] || svga->fullchange) {
p = &svga->monitor->target_buffer->line[svga->displine + svga->y_add][svga->x_add];
if (svga->firstline_draw == 2000)
svga->firstline_draw = svga->displine;
svga->lastline_draw = svga->displine;
if (!svga->remap_required) {
for (x = 0; x <= (svga->hdisp + svga->scrollcache); x += 4) {
dat0 = *(uint32_t *) (&svga->vram[svga->ma & svga->vram_display_mask]);
dat1 = *(uint32_t *) (&svga->vram[(svga->ma + 4) & svga->vram_display_mask]);
dat2 = *(uint32_t *) (&svga->vram[(svga->ma + 8) & svga->vram_display_mask]);
*p++ = lookup_lut(dat0 & 0xffffff);
*p++ = lookup_lut((dat0 >> 24) | ((dat1 & 0xffff) << 8));
*p++ = lookup_lut((dat1 >> 16) | ((dat2 & 0xff) << 16));
*p++ = lookup_lut(dat2 >> 8);
svga->ma += 12;
}
} else {
for (x = 0; x <= (svga->hdisp + svga->scrollcache); x += 4) {
addr = svga->remap_func(svga, svga->ma);
dat0 = *(uint32_t *) (&svga->vram[addr & svga->vram_display_mask]);
addr = svga->remap_func(svga, svga->ma + 4);
dat1 = *(uint32_t *) (&svga->vram[addr & svga->vram_display_mask]);
addr = svga->remap_func(svga, svga->ma + 8);
dat2 = *(uint32_t *) (&svga->vram[addr & svga->vram_display_mask]);
*p++ = lookup_lut(dat0 & 0xffffff);
*p++ = lookup_lut((dat0 >> 24) | ((dat1 & 0xffff) << 8));
*p++ = lookup_lut((dat1 >> 16) | ((dat2 & 0xff) << 16));
*p++ = lookup_lut(dat2 >> 8);
svga->ma += 12;
}
}
svga->ma &= svga->vram_display_mask;
}
}
}
void
svga_render_32bpp_lowres(svga_t *svga)
{
int x;
uint32_t *p;
uint32_t dat;
uint32_t changed_addr;
uint32_t addr;
if ((svga->displine + svga->y_add) < 0)
return;
if (svga->force_old_addr) {
if (svga->changedvram[svga->ma >> 12] || svga->changedvram[(svga->ma >> 12) + 1] || svga->fullchange) {
if (svga->firstline_draw == 2000)
svga->firstline_draw = svga->displine;
svga->lastline_draw = svga->displine;
for (x = 0; x <= (svga->hdisp + svga->scrollcache); x++) {
dat = svga->vram[svga->ma] | (svga->vram[svga->ma + 1] << 8) | (svga->vram[svga->ma + 2] << 16);
svga->ma += 4;
svga->ma &= svga->vram_display_mask;
svga->monitor->target_buffer->line[svga->displine + svga->y_add][(x << 1) + svga->x_add] = svga->monitor->target_buffer->line[svga->displine + svga->y_add][(x << 1) + 1 + svga->x_add] = lookup_lut(dat);
}
}
} else {
changed_addr = svga->remap_func(svga, svga->ma);
if (svga->changedvram[changed_addr >> 12] || svga->changedvram[(changed_addr >> 12) + 1] || svga->fullchange) {
p = &svga->monitor->target_buffer->line[svga->displine + svga->y_add][svga->x_add];
if (svga->firstline_draw == 2000)
svga->firstline_draw = svga->displine;
svga->lastline_draw = svga->displine;
if (!svga->remap_required) {
for (x = 0; x <= (svga->hdisp + svga->scrollcache); x++) {
dat = *(uint32_t *) (&svga->vram[(svga->ma + (x << 2)) & svga->vram_display_mask]);
*p++ = lookup_lut(dat & 0xffffff);
*p++ = lookup_lut(dat & 0xffffff);
}
svga->ma += (x * 4);
} else {
for (x = 0; x <= (svga->hdisp + svga->scrollcache); x++) {
addr = svga->remap_func(svga, svga->ma);
dat = *(uint32_t *) (&svga->vram[addr & svga->vram_display_mask]);
*p++ = lookup_lut(dat & 0xffffff);
*p++ = lookup_lut(dat & 0xffffff);
svga->ma += 4;
}
svga->ma &= svga->vram_display_mask;
}
}
}
}
void
svga_render_32bpp_highres(svga_t *svga)
{
int x;
uint32_t *p;
uint32_t dat;
uint32_t changed_addr;
uint32_t addr;
if ((svga->displine + svga->y_add) < 0)
return;
if (svga->force_old_addr) {
if (svga->changedvram[svga->ma >> 12] || svga->changedvram[(svga->ma >> 12) + 1] || svga->changedvram[(svga->ma >> 12) + 2] || svga->fullchange) {
p = &svga->monitor->target_buffer->line[svga->displine + svga->y_add][svga->x_add];
if (svga->firstline_draw == 2000)
svga->firstline_draw = svga->displine;
svga->lastline_draw = svga->displine;
for (x = 0; x <= (svga->hdisp + svga->scrollcache); x++) {
dat = *(uint32_t *) (&svga->vram[(svga->ma + (x << 2)) & svga->vram_display_mask]);
p[x] = lookup_lut(dat & 0xffffff);
}
svga->ma += 4;
svga->ma &= svga->vram_display_mask;
}
} else {
changed_addr = svga->remap_func(svga, svga->ma);
if (svga->changedvram[changed_addr >> 12] || svga->changedvram[(changed_addr >> 12) + 1] || svga->fullchange) {
p = &svga->monitor->target_buffer->line[svga->displine + svga->y_add][svga->x_add];
if (svga->firstline_draw == 2000)
svga->firstline_draw = svga->displine;
svga->lastline_draw = svga->displine;
if (!svga->remap_required) {
for (x = 0; x <= (svga->hdisp + svga->scrollcache); x++) {
dat = *(uint32_t *) (&svga->vram[(svga->ma + (x << 2)) & svga->vram_display_mask]);
*p++ = lookup_lut(dat & 0xffffff);
}
svga->ma += (x * 4);
} else {
for (x = 0; x <= (svga->hdisp + svga->scrollcache); x++) {
addr = svga->remap_func(svga, svga->ma);
dat = *(uint32_t *) (&svga->vram[addr & svga->vram_display_mask]);
*p++ = lookup_lut(dat & 0xffffff);
svga->ma += 4;
}
}
svga->ma &= svga->vram_display_mask;
}
}
}
void
svga_render_ABGR8888_highres(svga_t *svga)
{
int x;
uint32_t *p;
uint32_t dat;
uint32_t changed_addr;
uint32_t addr;
if ((svga->displine + svga->y_add) < 0)
return;
changed_addr = svga->remap_func(svga, svga->ma);
if (svga->changedvram[changed_addr >> 12] || svga->changedvram[(changed_addr >> 12) + 1] || svga->fullchange) {
p = &svga->monitor->target_buffer->line[svga->displine + svga->y_add][svga->x_add];
if (svga->firstline_draw == 2000)
svga->firstline_draw = svga->displine;
svga->lastline_draw = svga->displine;
if (!svga->remap_required) {
for (x = 0; x <= (svga->hdisp + svga->scrollcache); x++) {
dat = *(uint32_t *) (&svga->vram[(svga->ma + (x << 2)) & svga->vram_display_mask]);
*p++ = lookup_lut(((dat & 0xff0000) >> 16) | (dat & 0x00ff00) | ((dat & 0x0000ff) << 16));
}
svga->ma += x * 4;
} else {
for (x = 0; x <= (svga->hdisp + svga->scrollcache); x++) {
addr = svga->remap_func(svga, svga->ma);
dat = *(uint32_t *) (&svga->vram[addr & svga->vram_display_mask]);
*p++ = lookup_lut(((dat & 0xff0000) >> 16) | (dat & 0x00ff00) | ((dat & 0x0000ff) << 16));
svga->ma += 4;
}
}
svga->ma &= svga->vram_display_mask;
}
}
void
svga_render_RGBA8888_highres(svga_t *svga)
{
int x;
uint32_t *p;
uint32_t dat;
uint32_t changed_addr;
uint32_t addr;
if ((svga->displine + svga->y_add) < 0)
return;
changed_addr = svga->remap_func(svga, svga->ma);
if (svga->changedvram[changed_addr >> 12] || svga->changedvram[(changed_addr >> 12) + 1] || svga->fullchange) {
p = &svga->monitor->target_buffer->line[svga->displine + svga->y_add][svga->x_add];
if (svga->firstline_draw == 2000)
svga->firstline_draw = svga->displine;
svga->lastline_draw = svga->displine;
if (!svga->remap_required) {
for (x = 0; x <= (svga->hdisp + svga->scrollcache); x++) {
dat = *(uint32_t *) (&svga->vram[(svga->ma + (x << 2)) & svga->vram_display_mask]);
*p++ = lookup_lut(dat >> 8);
}
svga->ma += (x * 4);
} else {
for (x = 0; x <= (svga->hdisp + svga->scrollcache); x++) {
addr = svga->remap_func(svga, svga->ma);
dat = *(uint32_t *) (&svga->vram[addr & svga->vram_display_mask]);
*p++ = lookup_lut(dat >> 8);
svga->ma += 4;
}
}
svga->ma &= svga->vram_display_mask;
}
}
``` | /content/code_sandbox/src/video/vid_svga_render.c | c | 2016-06-25T22:29:10 | 2024-08-16T19:09:21 | 86Box | 86Box/86Box | 2,616 | 27,853 |
```c
/*
* 86Box A hypervisor and IBM PC system emulator that specializes in
* running old operating systems and software designed for IBM
* PC systems and compatibles from 1981 through fairly recent
* system designs based on the PCI bus.
*
* This file is part of the 86Box distribution.
*
* ICS2595 clock chip emulation. Used by ATI Mach64.
*
*
*
* Authors: Sarah Walker, <path_to_url
* Miran Grca, <mgrca8@gmail.com>
*
*/
#include <stdio.h>
#include <stdint.h>
#include <stdlib.h>
#include <string.h>
#include <wchar.h>
#include <86box/86box.h>
#include <86box/device.h>
#include <86box/plat_unused.h>
typedef struct ics2595_t {
int oldfs3;
int oldfs2;
int dat;
int pos;
int state;
double clocks[16];
double output_clock;
} ics2595_t;
enum {
ICS2595_IDLE = 0,
ICS2595_WRITE,
ICS2595_READ
};
static int ics2595_div[4] = { 8, 4, 2, 1 };
void
ics2595_write(void *priv, int strobe, int dat)
{
ics2595_t *ics2595 = (ics2595_t *) priv;
int d;
int n;
int l;
if (strobe) {
if ((dat & 8) && !ics2595->oldfs3) { /*Data clock*/
switch (ics2595->state) {
case ICS2595_IDLE:
ics2595->state = (dat & 4) ? ICS2595_WRITE : ICS2595_IDLE;
ics2595->pos = 0;
break;
case ICS2595_WRITE:
ics2595->dat = (ics2595->dat >> 1);
if (dat & 4)
ics2595->dat |= (1 << 19);
ics2595->pos++;
if (ics2595->pos == 20) {
l = (ics2595->dat >> 2) & 0xf;
n = ((ics2595->dat >> 7) & 255) + 257;
d = ics2595_div[(ics2595->dat >> 16) & 3];
ics2595->clocks[l] = (14318181.8 * ((double) n / 46.0)) / (double) d;
ics2595->state = ICS2595_IDLE;
}
break;
default:
break;
}
}
ics2595->oldfs2 = dat & 4;
ics2595->oldfs3 = dat & 8;
}
ics2595->output_clock = ics2595->clocks[dat];
}
static void *
ics2595_init(UNUSED(const device_t *info))
{
ics2595_t *ics2595 = (ics2595_t *) malloc(sizeof(ics2595_t));
memset(ics2595, 0, sizeof(ics2595_t));
return ics2595;
}
static void
ics2595_close(void *priv)
{
ics2595_t *ics2595 = (ics2595_t *) priv;
if (ics2595)
free(ics2595);
}
double
ics2595_getclock(void *priv)
{
const ics2595_t *ics2595 = (ics2595_t *) priv;
return ics2595->output_clock;
}
void
ics2595_setclock(void *priv, double clock)
{
ics2595_t *ics2595 = (ics2595_t *) priv;
ics2595->output_clock = clock;
}
const device_t ics2595_device = {
.name = "ICS2595 clock chip",
.internal_name = "ics2595",
.flags = 0,
.local = 0,
.init = ics2595_init,
.close = ics2595_close,
.reset = NULL,
{ .available = NULL },
.speed_changed = NULL,
.force_redraw = NULL,
.config = NULL
};
``` | /content/code_sandbox/src/video/vid_ics2595.c | c | 2016-06-25T22:29:10 | 2024-08-16T19:09:21 | 86Box | 86Box/86Box | 2,616 | 966 |
```c
/*
* 86Box A hypervisor and IBM PC system emulator that specializes in
* running old operating systems and software designed for IBM
* PC systems and compatibles from 1981 through fairly recent
* system designs based on the PCI bus.
*
* This file is part of the 86Box distribution.
*
* Emulation of the 8514/A-compatible Mach8 and Mach32 graphics
* chips from ATI for the ISA/VLB/MCA/PCI buses.
*
*
*
* Authors: TheCollector1995.
*
*/
#include <stdarg.h>
#include <stdint.h>
#include <stdio.h>
#include <string.h>
#include <stdlib.h>
#include <wchar.h>
#include <stdatomic.h>
#define HAVE_STDARG_H
#include <86box/86box.h>
#include <86box/device.h>
#include <86box/io.h>
#include <86box/mem.h>
#include <86box/timer.h>
#include <86box/mca.h>
#include <86box/pci.h>
#include <86box/rom.h>
#include <86box/plat.h>
#include <86box/thread.h>
#include <86box/video.h>
#include <86box/i2c.h>
#include <86box/vid_ddc.h>
#include <86box/vid_8514a.h>
#include <86box/vid_svga.h>
#include <86box/vid_svga_render.h>
#include <86box/vid_ati_eeprom.h>
#include <86box/vid_ati_mach8.h>
#define BIOS_MACH8_VGA_ROM_PATH "roms/video/mach8/BIOS.BIN"
#define BIOS_MACH32_ISA_ROM_PATH "roms/video/mach32/ATi Mach32 Graphics Pro ISA.BIN"
#define BIOS_MACH32_VLB_ROM_PATH "roms/video/mach32/MACH32VLB.VBI"
#define BIOS_MACH32_MCA_ROM_PATH "roms/video/mach32/MACH32MCA_Olivetti.BIN"
#define BIOS_MACH32_PCI_ROM_PATH "roms/video/mach32/intelopt_00000.rom"
static video_timings_t timing_gfxultra_isa = { .type = VIDEO_ISA, .write_b = 3, .write_w = 3, .write_l = 6, .read_b = 5, .read_w = 5, .read_l = 10 };
static video_timings_t timing_mach32_vlb = { .type = VIDEO_BUS, .write_b = 2, .write_w = 2, .write_l = 1, .read_b = 20, .read_w = 20, .read_l = 21 };
static video_timings_t timing_mach32_mca = { .type = VIDEO_MCA, .write_b = 4, .write_w = 5, .write_l = 10, .read_b = 5, .read_w = 5, .read_l = 10 };
static video_timings_t timing_mach32_pci = { .type = VIDEO_PCI, .write_b = 2, .write_w = 2, .write_l = 1, .read_b = 20, .read_w = 20, .read_l = 21 };
static void mach_accel_outb(uint16_t port, uint8_t val, void *priv);
static void mach_accel_outw(uint16_t port, uint16_t val, void *priv);
static uint8_t mach_accel_inb(uint16_t port, void *priv);
static uint16_t mach_accel_inw(uint16_t port, void *priv);
static uint8_t mach_in(uint16_t addr, void *priv);
#ifdef ATI_8514_ULTRA
static void ati8514_accel_outb(uint16_t port, uint8_t val, void *priv);
static void ati8514_accel_outw(uint16_t port, uint16_t val, void *priv);
static void ati8514_accel_outl(uint16_t port, uint32_t val, void *priv);
static uint8_t ati8514_accel_inb(uint16_t port, void *priv);
static uint16_t ati8514_accel_inw(uint16_t port, void *priv);
static uint32_t ati8514_accel_inl(uint16_t port, void *priv);
#endif
static void mach32_updatemapping(mach_t *mach, svga_t *svga);
#ifdef ENABLE_MACH_LOG
int mach_do_log = ENABLE_MACH_LOG;
static void
mach_log(const char *fmt, ...)
{
va_list ap;
if (mach_do_log) {
va_start(ap, fmt);
pclog_ex(fmt, ap);
va_end(ap);
}
}
#else
# define mach_log(fmt, ...)
#endif
#define WRITE8(addr, var, val) \
switch ((addr) & 1) { \
case 0: \
var = (var & 0xff00) | (val); \
break; \
case 1: \
var = (var & 0x00ff) | ((val) << 8); \
break; \
}
#define READ8(addr, var) \
switch ((addr) & 1) { \
case 0: \
temp = (var) & 0xff; \
break; \
case 1: \
temp = ((var) >> 8) & 0xff; \
break; \
}
#define READ_PIXTRANS_BYTE_IO(cx, n) \
if ((mach->accel.cmd_type == 2) || (mach->accel.cmd_type == 5)) { \
if (dev->bpp) { \
if (n == 0) \
mach->accel.pix_trans[(n)] = vram_w[(dev->accel.dest + (cx) + (n)) & (dev->vram_mask >> 1)] & 0xff; \
else \
mach->accel.pix_trans[(n)] = vram_w[(dev->accel.dest + (cx) + (n)) & (dev->vram_mask >> 1)] >> 8; \
} else { \
mach->accel.pix_trans[(n)] = dev->vram[(dev->accel.dest + (cx) + (n)) & dev->vram_mask]; \
} \
}
#define READ_PIXTRANS_WORD(cx, n) \
if ((cmd == 0) || (cmd == 1) || (cmd == 5) || (mach->accel.cmd_type == -1)) { \
if (dev->bpp) \
temp = vram_w[((dev->accel.cy * dev->pitch) + (cx) + (n)) & (dev->vram_mask >> 1)]; \
else { \
temp = dev->vram[((dev->accel.cy * dev->pitch) + (cx) + (n)) & dev->vram_mask]; \
temp |= (dev->vram[((dev->accel.cy * dev->pitch) + (cx) + (n + 1)) & dev->vram_mask] << 8); \
} \
} else if ((mach->accel.cmd_type == 2) || (mach->accel.cmd_type == 5)) { \
if (dev->bpp) \
temp = vram_w[((dev->accel.dest) + (cx) + (n)) & (dev->vram_mask >> 1)]; \
else { \
temp = dev->vram[((dev->accel.dest) + (cx) + (n)) & dev->vram_mask]; \
temp |= (dev->vram[((dev->accel.dest) + (cx) + (n + 1)) & dev->vram_mask] << 8); \
} \
} else if ((mach->accel.cmd_type == 3) || (mach->accel.cmd_type == 4)) { \
if (dev->bpp) \
temp = vram_w[((mach->accel.ge_offset << 1) + ((dev->accel.cy) * (dev->pitch)) + (cx) + (n)) & (dev->vram_mask >> 1)]; \
else { \
temp = dev->vram[((mach->accel.ge_offset << 2) + ((dev->accel.cy) * (dev->pitch)) + (cx) + (n)) & dev->vram_mask]; \
temp |= (dev->vram[((mach->accel.ge_offset << 2) + ((dev->accel.cy) * (dev->pitch)) + (cx) + (n + 1)) & dev->vram_mask] << 8); \
} \
}
#define READ(addr, dat) \
if (dev->bpp) \
dat = vram_w[(addr) & (dev->vram_mask >> 1)]; \
else \
dat = dev->vram[(addr) & (dev->vram_mask)];
#define MIX(mixmode, dest_dat, src_dat) \
{ \
switch ((mixmode) ? (dev->accel.frgd_mix & 0x1f) : (dev->accel.bkgd_mix & 0x1f)) { \
case 0x00: \
dest_dat = ~dest_dat; \
break; \
case 0x01: \
dest_dat = 0; \
break; \
case 0x02: \
dest_dat = ~0; \
break; \
case 0x03: \
dest_dat = dest_dat; \
break; \
case 0x04: \
dest_dat = ~src_dat; \
break; \
case 0x05: \
dest_dat = src_dat ^ dest_dat; \
break; \
case 0x06: \
dest_dat = ~(src_dat ^ dest_dat); \
break; \
case 0x07: \
dest_dat = src_dat; \
break; \
case 0x08: \
dest_dat = ~(src_dat & dest_dat); \
break; \
case 0x09: \
dest_dat = ~src_dat | dest_dat; \
break; \
case 0x0a: \
dest_dat = src_dat | ~dest_dat; \
break; \
case 0x0b: \
dest_dat = src_dat | dest_dat; \
break; \
case 0x0c: \
dest_dat = src_dat & dest_dat; \
break; \
case 0x0d: \
dest_dat = src_dat & ~dest_dat; \
break; \
case 0x0e: \
dest_dat = ~src_dat & dest_dat; \
break; \
case 0x0f: \
dest_dat = ~(src_dat | dest_dat); \
break; \
case 0x10: \
dest_dat = MIN(src_dat, dest_dat); \
break; \
case 0x11: \
dest_dat = dest_dat - src_dat; \
break; \
case 0x12: \
dest_dat = src_dat - dest_dat; \
break; \
case 0x13: \
dest_dat = src_dat + dest_dat; \
break; \
case 0x14: \
dest_dat = MAX(src_dat, dest_dat); \
break; \
case 0x15: \
dest_dat = (dest_dat - src_dat) / 2; \
break; \
case 0x16: \
dest_dat = (src_dat - dest_dat) / 2; \
break; \
case 0x17: \
dest_dat = (dest_dat + src_dat) / 2; \
break; \
case 0x18: \
dest_dat = MAX(0, (dest_dat - src_dat)); \
break; \
case 0x19: \
dest_dat = MAX(0, (dest_dat - src_dat)); \
break; \
case 0x1a: \
dest_dat = MAX(0, (src_dat - dest_dat)); \
break; \
case 0x1b: \
dest_dat = MIN(0xff, (dest_dat + src_dat)); \
break; \
case 0x1c: \
dest_dat = MAX(0, (dest_dat - src_dat)) / 2; \
break; \
case 0x1d: \
dest_dat = MAX(0, (dest_dat - src_dat)) / 2; \
break; \
case 0x1e: \
dest_dat = MAX(0, (src_dat - dest_dat)) / 2; \
break; \
case 0x1f: \
dest_dat = (0xff < (src_dat + dest_dat)) ? 0xff : ((src_dat + dest_dat) / 2); \
break; \
} \
}
#define WRITE(addr, dat) \
if (dev->bpp) { \
vram_w[((addr)) & (dev->vram_mask >> 1)] = dat; \
dev->changedvram[(((addr)) & (dev->vram_mask >> 1)) >> 11] = changeframecount; \
} else { \
dev->vram[((addr)) & (dev->vram_mask)] = dat; \
dev->changedvram[(((addr)) & (dev->vram_mask)) >> 12] = changeframecount; \
}
static int
mach_pixel_write(mach_t *mach)
{
if (mach->accel.dp_config & 1)
return 1;
return 0;
}
static int
mach_pixel_read(mach_t *mach)
{
if (mach->accel.dp_config & 1)
return 0;
return 1;
}
static void
mach_accel_start(int cmd_type, int cpu_input, int count, uint32_t mix_dat, uint32_t cpu_dat, mach_t *mach, ibm8514_t *dev)
{
int compare_mode;
uint16_t poly_src = 0;
uint16_t rd_mask = dev->accel.rd_mask;
uint16_t wrt_mask = dev->accel.wrt_mask;
uint16_t dest_cmp_clr = dev->accel.color_cmp;
int frgd_sel;
int bkgd_sel;
int mono_src;
int compare = 0;
uint16_t src_dat = 0;
uint16_t dest_dat = 0;
uint16_t old_dest_dat;
uint16_t *vram_w = (uint16_t *) dev->vram;
uint16_t mix = 0;
int16_t clip_l = dev->accel.clip_left & 0x7ff;
int16_t clip_t = dev->accel.clip_top & 0x7ff;
int16_t clip_r = dev->accel.multifunc[4] & 0x7ff;
int16_t clip_b = dev->accel.multifunc[3] & 0x7ff;
uint32_t mono_dat0 = 0;
uint32_t mono_dat1 = 0;
if (!dev->bpp) {
rd_mask &= 0xff;
dest_cmp_clr &= 0xff;
}
compare_mode = (mach->accel.dest_cmp_fn >> 3) & 7;
frgd_sel = (mach->accel.dp_config >> 13) & 7;
bkgd_sel = (mach->accel.dp_config >> 7) & 3;
mono_src = (mach->accel.dp_config >> 5) & 3;
if ((mono_src == 2) || (bkgd_sel == 2) || (frgd_sel == 2) || mach_pixel_read(mach)) {
mach->force_busy = 1;
dev->force_busy = 1;
dev->force_busy2 = 1;
}
if (cpu_input) {
if (dev->bpp) {
if ((mach->accel.dp_config & 0x200) && (count == 2)) {
count >>= 1;
}
}
}
if ((dev->accel_bpp == 8) || (dev->accel_bpp == 15) || (dev->accel_bpp == 16) || (dev->accel_bpp == 24)) {
if ((cmd_type == 2) && cpu_input) {
mach_log("RdMask=%04x, DPCONFIG=%04x, Clipping: l=%d, r=%d, t=%d, b=%d, LineDrawOpt=%04x, BPP=%d, CMDType = %d, offs=%08x, cnt = %d, input = %d, mono_src = %d, frgdsel = %d, d(%d,%d), dstxend = %d, pitch = %d, extcrt = %d, rw = %x, monpattern = %x.\n", rd_mask, mach->accel.dp_config, clip_l, clip_r, clip_t, clip_b, mach->accel.linedraw_opt, dev->accel_bpp, cmd_type, mach->accel.ge_offset, count, cpu_input, mono_src, frgd_sel, dev->accel.cur_x, dev->accel.cur_y, mach->accel.dest_x_end, dev->ext_pitch, dev->ext_crt_pitch, mach->accel.dp_config & 1, mach->accel.mono_pattern_enable);
}
}
switch (cmd_type) {
case 1: /*Extended Raw Linedraw from bres_count register (0x96ee)*/
if (!cpu_input) {
dev->accel.dx = dev->accel.cur_x;
if (dev->accel.cur_x >= 0x600)
dev->accel.dx |= ~0x5ff;
dev->accel.dy = dev->accel.cur_y;
if (dev->accel.cur_y >= 0x600)
dev->accel.dy |= ~0x5ff;
dev->accel.cx = dev->accel.destx_distp;
if (dev->accel.destx_distp >= 0x600)
dev->accel.cx |= ~0x5ff;
dev->accel.cy = dev->accel.desty_axstp;
if (dev->accel.desty_axstp >= 0x600)
dev->accel.cy |= ~0x5ff;
mach->accel.width = mach->accel.bres_count;
dev->accel.sx = 0;
mach->accel.poly_fill = 0;
mach->accel.color_pattern_idx = ((dev->accel.cx + (dev->accel.cy << 3)) & mach->accel.patt_len);
mach->accel.stepx = (mach->accel.linedraw_opt & 0x20) ? 1 : -1;
mach->accel.stepy = (mach->accel.linedraw_opt & 0x80) ? 1 : -1;
mach_log("Extended bresenham, CUR(%d,%d), DEST(%d,%d), width = %d, options = %04x, dpconfig = %04x, opt_ena = %03x.\n", dev->accel.dx, dev->accel.dy, dev->accel.cx, dev->accel.cy, mach->accel.width, mach->accel.linedraw_opt, mach->accel.dp_config, mach->accel.max_waitstates & 0x100);
if ((mono_src == 2) || (bkgd_sel == 2) || (frgd_sel == 2) || mach_pixel_read(mach)) {
if (mach_pixel_write(mach)) {
dev->data_available = 0;
dev->data_available2 = 0;
return;
} else if (mach_pixel_read(mach)) {
dev->data_available = 1;
dev->data_available2 = 1;
return;
}
}
}
if (frgd_sel == 5) {
for (int x = 0; x <= mach->accel.patt_len; x++) {
mach->accel.color_pattern[x] = mach->accel.patt_data[x & mach->accel.patt_len];
}
/*The destination coordinates should match the pattern index.*/
if (mach->accel.color_pattern_idx != mach->accel.patt_idx)
mach->accel.color_pattern_idx = mach->accel.patt_idx;
}
if (mono_src == 1) {
count = mach->accel.width;
mix_dat = mach->accel.patt_data[0x10];
dev->accel.temp_cnt = 8;
}
if (mach->accel.linedraw_opt & 0x08) { /*Vector Line*/
while (count--) {
switch (mono_src) {
case 0:
mix = 1;
break;
case 1:
if (!dev->accel.temp_cnt) {
dev->accel.temp_cnt = 8;
mix_dat >>= 8;
}
mix = (mix_dat & 0x80);
dev->accel.temp_cnt--;
mix_dat <<= 1;
mix_dat |= 1;
break;
case 2:
if (mach->accel.dp_config & 0x1000) {
mix = mix_dat >> 0x1f;
mix_dat <<= 1;
} else {
if (mach->accel.dp_config & 0x200) {
mix = mix_dat & 1;
mix_dat >>= 1;
} else {
mix = mix_dat & 0x80;
mix_dat <<= 1;
mix_dat |= 1;
}
}
break;
case 3:
if (dev->bpp) {
READ((mach->accel.ge_offset << 1) + ((dev->accel.cy) * (dev->pitch)) + (dev->accel.cx), mix);
} else {
READ((mach->accel.ge_offset << 2) + ((dev->accel.cy) * (dev->pitch)) + (dev->accel.cx), mix);
}
mix = (mix & rd_mask) == rd_mask;
break;
default:
break;
}
if (((dev->accel.dx) >= clip_l) && ((dev->accel.dx) <= clip_r) && ((dev->accel.dy) >= clip_t) && ((dev->accel.dy) <= clip_b)) {
switch (mix ? frgd_sel : bkgd_sel) {
case 0:
src_dat = dev->accel.bkgd_color;
break;
case 1:
src_dat = dev->accel.frgd_color;
break;
case 2:
src_dat = cpu_dat;
break;
case 3:
if (mach_pixel_read(mach))
src_dat = cpu_dat;
else {
if (dev->bpp) {
READ((mach->accel.ge_offset << 1) + ((dev->accel.cy) * (dev->pitch)) + (dev->accel.cx), src_dat);
} else {
READ((mach->accel.ge_offset << 2) + ((dev->accel.cy) * (dev->pitch)) + (dev->accel.cx), src_dat);
}
if (mono_src == 3) {
src_dat = (src_dat & rd_mask) == rd_mask;
}
}
break;
case 5:
if (mix) {
src_dat = mach->accel.color_pattern[((dev->accel.dx) + ((dev->accel.dy) << 3)) & mach->accel.patt_len];
} else
src_dat = 0;
break;
default:
break;
}
if (mach->accel.linedraw_opt & 0x02) {
if (dev->bpp) {
READ((mach->accel.ge_offset << 1) + ((dev->accel.cy) * (dev->pitch)) + (dev->accel.cx), poly_src);
} else {
READ((mach->accel.ge_offset << 2) + ((dev->accel.cy) * (dev->pitch)) + (dev->accel.cx), poly_src);
}
poly_src = ((poly_src & rd_mask) == rd_mask);
if (poly_src)
mach->accel.poly_fill = !mach->accel.poly_fill;
}
if (mach->accel.poly_fill || !(mach->accel.linedraw_opt & 0x02)) {
if (dev->bpp) {
READ((mach->accel.ge_offset << 1) + ((dev->accel.dy) * (dev->pitch)) + (dev->accel.dx), dest_dat);
} else {
READ((mach->accel.ge_offset << 2) + ((dev->accel.dy) * (dev->pitch)) + (dev->accel.dx), dest_dat);
}
switch (compare_mode) {
case 1:
compare = 1;
break;
case 2:
compare = (dest_dat >= dest_cmp_clr) ? 0 : 1;
break;
case 3:
compare = (dest_dat < dest_cmp_clr) ? 0 : 1;
break;
case 4:
compare = (dest_dat != dest_cmp_clr) ? 0 : 1;
break;
case 5:
compare = (dest_dat == dest_cmp_clr) ? 0 : 1;
break;
case 6:
compare = (dest_dat <= dest_cmp_clr) ? 0 : 1;
break;
case 7:
compare = (dest_dat > dest_cmp_clr) ? 0 : 1;
break;
default:
break;
}
if (!compare) {
if (mach_pixel_write(mach)) {
old_dest_dat = dest_dat;
MIX(mix, dest_dat, src_dat);
dest_dat = (dest_dat & wrt_mask) | (old_dest_dat & ~wrt_mask);
}
}
if (mach->accel.dp_config & 0x10) {
if (mach->accel.linedraw_opt & 0x04) {
if (((mono_src != 1) && (dev->accel.sx < mach->accel.width)) || ((mono_src == 1) && count)) {
if (dev->bpp) {
WRITE((mach->accel.ge_offset << 1) + ((dev->accel.dy) * (dev->pitch)) + (dev->accel.dx), dest_dat);
} else {
WRITE((mach->accel.ge_offset << 2) + ((dev->accel.dy) * (dev->pitch)) + (dev->accel.dx), dest_dat);
}
}
} else {
if (dev->bpp) {
WRITE((mach->accel.ge_offset << 1) + ((dev->accel.dy) * (dev->pitch)) + (dev->accel.dx), dest_dat);
} else {
WRITE((mach->accel.ge_offset << 2) + ((dev->accel.dy) * (dev->pitch)) + (dev->accel.dx), dest_dat);
}
}
}
}
}
if ((mono_src == 1) && !count)
break;
else if ((mono_src != 1) && (dev->accel.sx >= mach->accel.width))
break;
if (dev->bpp)
cpu_dat >>= 16;
else
cpu_dat >>= 8;
switch (mach->accel.linedraw_opt & 0xe0) {
case 0x00:
dev->accel.cx++;
dev->accel.dx++;
break;
case 0x20:
dev->accel.cx++;
dev->accel.dx++;
dev->accel.cy--;
dev->accel.dy--;
break;
case 0x40:
dev->accel.cy--;
dev->accel.dy--;
break;
case 0x60:
dev->accel.cx--;
dev->accel.dx--;
dev->accel.cy--;
dev->accel.dy--;
break;
case 0x80:
dev->accel.cx--;
dev->accel.dx--;
break;
case 0xa0:
dev->accel.cx--;
dev->accel.dx--;
dev->accel.cy++;
dev->accel.dy++;
break;
case 0xc0:
dev->accel.cy++;
dev->accel.dy++;
break;
case 0xe0:
dev->accel.cx++;
dev->accel.dx++;
dev->accel.cy++;
dev->accel.dy++;
break;
default:
break;
}
dev->accel.sx++;
}
} else { /*Bresenham*/
while (count--) {
switch (mono_src) {
case 0:
mix = 1;
break;
case 1:
if (!dev->accel.temp_cnt) {
dev->accel.temp_cnt = 8;
mix_dat >>= 8;
}
mix = (mix_dat & 0x80);
dev->accel.temp_cnt--;
mix_dat <<= 1;
mix_dat |= 1;
break;
case 2:
if (mach->accel.dp_config & 0x1000) {
mix = mix_dat >> 0x1f;
mix_dat <<= 1;
} else {
if (mach->accel.dp_config & 0x200) {
mix = mix_dat & 1;
mix_dat >>= 1;
} else {
mix = mix_dat & 0x80;
mix_dat <<= 1;
mix_dat |= 1;
}
}
break;
case 3:
if (dev->bpp) {
READ((mach->accel.ge_offset << 1) + ((dev->accel.cy) * (dev->pitch)) + (dev->accel.cx), mix);
} else {
READ((mach->accel.ge_offset << 2) + ((dev->accel.cy) * (dev->pitch)) + (dev->accel.cx), mix);
}
mix = (mix & rd_mask) == rd_mask;
break;
default:
break;
}
if (((dev->accel.dx) >= clip_l) && ((dev->accel.dx) <= clip_r) && ((dev->accel.dy) >= clip_t) && ((dev->accel.dy) <= clip_b)) {
switch (mix ? frgd_sel : bkgd_sel) {
case 0:
src_dat = dev->accel.bkgd_color;
break;
case 1:
src_dat = dev->accel.frgd_color;
break;
case 2:
src_dat = cpu_dat;
break;
case 3:
if (mach_pixel_read(mach))
src_dat = cpu_dat;
else {
if (dev->bpp) {
READ((mach->accel.ge_offset << 1) + ((dev->accel.cy) * (dev->pitch)) + (dev->accel.cx), src_dat);
} else {
READ((mach->accel.ge_offset << 2) + ((dev->accel.cy) * (dev->pitch)) + (dev->accel.cx), src_dat);
}
if (mono_src == 3) {
src_dat = (src_dat & rd_mask) == rd_mask;
}
}
break;
case 5:
if (mix) {
src_dat = mach->accel.color_pattern[((dev->accel.dx) + ((dev->accel.dy) << 3)) & mach->accel.patt_len];
} else
src_dat = 0;
break;
default:
break;
}
if (mach->accel.linedraw_opt & 0x02) {
if (dev->bpp) {
READ((mach->accel.ge_offset << 1) + ((dev->accel.cy) * (dev->pitch)) + (dev->accel.cx), poly_src);
} else {
READ((mach->accel.ge_offset << 2) + ((dev->accel.cy) * (dev->pitch)) + (dev->accel.cx), poly_src);
}
poly_src = ((poly_src & rd_mask) == rd_mask);
if (poly_src)
mach->accel.poly_fill = !mach->accel.poly_fill;
}
if (mach->accel.poly_fill || !(mach->accel.linedraw_opt & 0x02)) {
if (dev->bpp) {
READ((mach->accel.ge_offset << 1) + ((dev->accel.dy) * (dev->pitch)) + (dev->accel.dx), dest_dat);
} else {
READ((mach->accel.ge_offset << 2) + ((dev->accel.dy) * (dev->pitch)) + (dev->accel.dx), dest_dat);
}
switch (compare_mode) {
case 1:
compare = 1;
break;
case 2:
compare = (dest_dat >= dest_cmp_clr) ? 0 : 1;
break;
case 3:
compare = (dest_dat < dest_cmp_clr) ? 0 : 1;
break;
case 4:
compare = (dest_dat != dest_cmp_clr) ? 0 : 1;
break;
case 5:
compare = (dest_dat == dest_cmp_clr) ? 0 : 1;
break;
case 6:
compare = (dest_dat <= dest_cmp_clr) ? 0 : 1;
break;
case 7:
compare = (dest_dat > dest_cmp_clr) ? 0 : 1;
break;
default:
break;
}
if (!compare) {
if (mach_pixel_write(mach)) {
old_dest_dat = dest_dat;
MIX(mix, dest_dat, src_dat);
dest_dat = (dest_dat & wrt_mask) | (old_dest_dat & ~wrt_mask);
}
}
if (mach->accel.dp_config & 0x10) {
if (mach->accel.linedraw_opt & 0x04) {
if (((mono_src != 1) && (dev->accel.sx < mach->accel.width)) || ((mono_src == 1) && count)) {
if (dev->bpp) {
WRITE((mach->accel.ge_offset << 1) + ((dev->accel.dy) * (dev->pitch)) + (dev->accel.dx), dest_dat);
} else {
WRITE((mach->accel.ge_offset << 2) + ((dev->accel.dy) * (dev->pitch)) + (dev->accel.dx), dest_dat);
}
}
} else {
if (dev->bpp) {
WRITE((mach->accel.ge_offset << 1) + ((dev->accel.dy) * (dev->pitch)) + (dev->accel.dx), dest_dat);
} else {
WRITE((mach->accel.ge_offset << 2) + ((dev->accel.dy) * (dev->pitch)) + (dev->accel.dx), dest_dat);
}
}
}
}
}
if ((mono_src == 1) && !count)
break;
else if ((mono_src != 1) && (dev->accel.sx >= mach->accel.width))
break;
if (dev->bpp)
cpu_dat >>= 16;
else
cpu_dat >>= 8;
if (mach->accel.linedraw_opt & 0x40) {
dev->accel.dy += mach->accel.stepy;
if ((frgd_sel == 3) || (bkgd_sel == 3))
dev->accel.cy += mach->accel.stepy;
if (dev->accel.err_term >= 0) {
dev->accel.err_term += dev->accel.destx_distp;
dev->accel.dx += mach->accel.stepx;
if ((frgd_sel == 3) || (bkgd_sel == 3))
dev->accel.cx += mach->accel.stepx;
} else {
dev->accel.err_term += dev->accel.desty_axstp;
}
} else {
dev->accel.dx += mach->accel.stepx;
if ((frgd_sel == 3) || (bkgd_sel == 3))
dev->accel.cx += mach->accel.stepx;
if (dev->accel.err_term >= 0) {
dev->accel.err_term += dev->accel.destx_distp;
dev->accel.dy += mach->accel.stepy;
if ((frgd_sel == 3) || (bkgd_sel == 3))
dev->accel.cy += mach->accel.stepy;
} else {
dev->accel.err_term += dev->accel.desty_axstp;
}
}
dev->accel.sx++;
}
}
mach->accel.poly_fill = 0;
dev->accel.cur_x = dev->accel.dx;
dev->accel.cur_y = dev->accel.dy;
break;
case 2: /*Non-conforming BitBLT from dest_y_end register (0xaeee)*/
if (!cpu_input) {
mach->accel.stepx = 0;
mach->accel.stepy = 0;
dev->accel.dx = dev->accel.cur_x;
if (dev->accel.cur_x >= 0x600)
dev->accel.dx |= ~0x5ff;
dev->accel.dy = dev->accel.cur_y;
if (dev->accel.cur_y >= 0x600)
dev->accel.dy |= ~0x5ff;
if (mach->accel.dp_config == 0x5211) {
if (mach->accel.dest_x_end == 1024) {
goto skip_dx;
}
}
/*Destination Width*/
if (mach->accel.dest_x_start != dev->accel.dx)
mach->accel.dest_x_start = dev->accel.dx;
skip_dx:
mach->accel.dx_start = mach->accel.dest_x_start;
if (mach->accel.dest_x_start >= 0x600)
mach->accel.dx_start |= ~0x5ff;
mach->accel.dx_end = mach->accel.dest_x_end;
if (mach->accel.dest_x_end >= 0x600)
mach->accel.dx_end |= ~0x5ff;
if (mach->accel.dx_end > mach->accel.dx_start) {
mach->accel.width = (mach->accel.dx_end - mach->accel.dx_start);
mach->accel.stepx = 1;
} else if (mach->accel.dx_end < mach->accel.dx_start) {
mach->accel.width = (mach->accel.dx_start - mach->accel.dx_end);
mach->accel.stepx = -1;
if (dev->accel.dx > 0)
dev->accel.dx--;
mach_log("BitBLT: Dst Negative X, dxstart = %d, end = %d, width = %d, dx = %d, dpconfig = %04x.\n", mach->accel.dest_x_start, mach->accel.dest_x_end, mach->accel.width, dev->accel.dx, mach->accel.dp_config);
} else {
mach->accel.stepx = 1;
mach->accel.width = 0;
mach_log("BitBLT: Dst Indeterminate X, dpconfig = %04x, destxend = %d, destxstart = %d.\n", mach->accel.dp_config, mach->accel.dest_x_end, mach->accel.dest_x_start);
}
dev->accel.sx = 0;
mach->accel.poly_fill = 0;
mach->accel.color_pattern_idx = ((dev->accel.dx + (dev->accel.dy << 3)) & mach->accel.patt_len);
if ((dev->accel_bpp == 24) && (mono_src != 1)) {
if (mach->accel.color_pattern_idx == mach->accel.patt_len)
mach->accel.color_pattern_idx = mach->accel.patt_data_idx;
} else if ((dev->accel_bpp == 24) && (frgd_sel == 5) && (mono_src == 1) && (mach->accel.patt_len_reg & 0x4000))
mach->accel.color_pattern_idx = 0;
/*Height*/
mach->accel.dy_start = dev->accel.cur_y;
if (dev->accel.cur_y >= 0x600)
mach->accel.dy_start |= ~0x5ff;
mach->accel.dy_end = mach->accel.dest_y_end;
if (mach->accel.dest_y_end >= 0x600)
mach->accel.dy_end |= ~0x5ff;
if (mach->accel.dy_end > mach->accel.dy_start) {
mach->accel.height = (mach->accel.dy_end - mach->accel.dy_start);
mach->accel.stepy = 1;
} else if (mach->accel.dy_end < mach->accel.dy_start) {
mach->accel.height = (mach->accel.dy_start - mach->accel.dy_end);
mach->accel.stepy = -1;
} else {
mach->accel.height = 0;
mach->accel.stepy = 1;
}
dev->accel.sy = 0;
if (dev->bpp)
dev->accel.dest = (mach->accel.ge_offset << 1) + (dev->accel.dy * (dev->pitch));
else
dev->accel.dest = (mach->accel.ge_offset << 2) + (dev->accel.dy * (dev->pitch));
mach->accel.src_stepx = 0;
/*Source Width*/
dev->accel.cx = mach->accel.src_x;
if (mach->accel.src_x >= 0x600)
dev->accel.cx |= ~0x5ff;
dev->accel.cy = mach->accel.src_y;
if (mach->accel.src_y >= 0x600)
dev->accel.cy |= ~0x5ff;
mach->accel.sx_start = mach->accel.src_x_start;
if (mach->accel.src_x_start >= 0x600)
mach->accel.sx_start |= ~0x5ff;
mach->accel.sx_end = mach->accel.src_x_end;
if (mach->accel.src_x_end >= 0x600)
mach->accel.sx_end |= ~0x5ff;
if (mach->accel.sx_end > mach->accel.sx_start) {
mach->accel.src_width = (mach->accel.sx_end - mach->accel.sx_start);
mach->accel.src_stepx = 1;
mach_log("BitBLT: Src Positive X: wh(%d,%d), srcwidth = %d, coordinates: %d,%d px, start: %d, end: %d px, stepx = %d, dpconfig = %04x, oddwidth = %d.\n", mach->accel.width, mach->accel.height, mach->accel.src_width, dev->accel.cx, dev->accel.cy, mach->accel.src_x_start, mach->accel.src_x_end, mach->accel.src_stepx, mach->accel.dp_config, mach->accel.src_width & 1);
} else if (mach->accel.sx_end < mach->accel.sx_start) {
mach->accel.src_width = (mach->accel.sx_start - mach->accel.sx_end);
mach->accel.src_stepx = -1;
if (dev->accel.cx > 0)
dev->accel.cx--;
mach_log("BitBLT: Src Negative X: width = %d, coordinates: %d,%d px, end: %d px, stepx = %d, dpconfig = %04x, oddwidth = %d.\n", mach->accel.src_width, dev->accel.cx, dev->accel.cy, mach->accel.src_x_end, mach->accel.src_stepx, mach->accel.dp_config, mach->accel.src_width & 1);
} else {
mach->accel.src_stepx = 1;
mach->accel.src_width = 0;
mach_log("BitBLT: Src Indeterminate X: width = %d, coordinates: %d,%d px, end: %d px, stepx = %d, dpconfig = %04x, oddwidth = %d.\n", mach->accel.src_width, dev->accel.cx, dev->accel.cy, mach->accel.src_x_end, mach->accel.src_stepx, mach->accel.dp_config, mach->accel.src_width & 1);
}
mach->accel.sx = 0;
if (dev->bpp)
dev->accel.src = (mach->accel.ge_offset << 1) + (dev->accel.cy * (dev->pitch));
else
dev->accel.src = (mach->accel.ge_offset << 2) + (dev->accel.cy * (dev->pitch));
if ((dev->accel_bpp == 24) && (frgd_sel == 5))
mach_log("BitBLT=%04x, WH(%d,%d), SRCWidth=%d, c(%d,%d), s(%d,%d).\n", mach->accel.dp_config, mach->accel.width, mach->accel.height, mach->accel.src_width, dev->accel.dx, dev->accel.dy, dev->accel.cx, dev->accel.cy);
else if (mach->accel.dp_config & 0x02)
mach_log("BitBLT=%04x, Pitch=%d, C(%d,%d), D(%d,%d), SRCWidth=%d, SRCXStep=%d, WH(%d,%d), clipt=%d, clipb=%d, geoffset=%08x.\n", mach->accel.dp_config, dev->ext_pitch, mach->accel.src_x, mach->accel.src_y, dev->accel.cur_x, dev->accel.cur_y, mach->accel.src_width, mach->accel.src_stepx, mach->accel.width, mach->accel.height, clip_t, clip_b, (mach->accel.ge_offset << 2));
if (mono_src == 1) {
if ((mach->accel.mono_pattern_enable) && !(mach->accel.patt_len_reg & 0x4000)) {
mono_dat0 = mach->accel.patt_data[0x10];
mono_dat0 |= (mach->accel.patt_data[0x11] << 8);
mono_dat0 |= (mach->accel.patt_data[0x12] << 16);
mono_dat0 |= (mach->accel.patt_data[0x13] << 24);
mono_dat1 = mach->accel.patt_data[0x14];
mono_dat1 |= (mach->accel.patt_data[0x15] << 8);
mono_dat1 |= (mach->accel.patt_data[0x16] << 16);
mono_dat1 |= (mach->accel.patt_data[0x17] << 24);
for (uint8_t y = 0; y < 8; y++) {
for (uint8_t x = 0; x < 8; x++) {
uint32_t temp = (y & 4) ? mono_dat1 : mono_dat0;
mach->accel.mono_pattern[y][7 - x] = (temp >> (x + ((y & 3) << 3))) & 1;
}
}
}
}
if ((mono_src == 2) || (bkgd_sel == 2) || (frgd_sel == 2) || mach_pixel_read(mach)) {
if (mach_pixel_write(mach)) {
dev->data_available = 0;
dev->data_available2 = 0;
return;
} else if (mach_pixel_read(mach)) {
dev->data_available = 1;
dev->data_available2 = 1;
return;
}
}
}
if (mono_src == 1) {
if (!mach->accel.mono_pattern_enable && !(mach->accel.patt_len_reg & 0x4000)) {
count = mach->accel.width;
mix_dat = mach->accel.patt_data[0x10] ^ ((mach->accel.patt_idx & 1) ? 0xff : 0);
dev->accel.temp_cnt = 8;
}
}
if (frgd_sel == 5) {
if (dev->bpp) {
for (int x = 0; x <= mach->accel.patt_len; x += 2) {
mach->accel.color_pattern_word[x + (mach->accel.color_pattern_idx & 1)] = (mach->accel.patt_data[x & mach->accel.patt_len] & 0xff);
mach->accel.color_pattern_word[x + (mach->accel.color_pattern_idx & 1)] |= (mach->accel.patt_data[(x + 1) & mach->accel.patt_len] << 8);
}
} else {
if ((dev->accel_bpp == 24) && (mach->accel.patt_len < 3)) {
for (int x = 0; x <= mach->accel.patt_len; x++) {
mach->accel.color_pattern[x] = mach->accel.patt_data[x];
mach_log("BITBLT: Color Pattern 24bpp[%d]=%02x, dataidx=%d, pattlen=%d.\n", x, mach->accel.color_pattern[x], mach->accel.patt_data_idx, mach->accel.patt_len);
}
} else {
for (int x = 0; x <= mach->accel.patt_len; x++) {
mach->accel.color_pattern[x] = mach->accel.patt_data[x & mach->accel.patt_len];
}
}
}
/*The destination coordinates should match the pattern index.*/
if (mach->accel.color_pattern_idx != mach->accel.patt_idx)
mach->accel.color_pattern_idx = mach->accel.patt_idx;
}
if (mach->accel.dy_end == mach->accel.dy_start) {
mach_log("No DEST.\n");
return;
}
if ((mono_src == 3) || (bkgd_sel == 3) || (frgd_sel == 3)) {
if (mach->accel.sx_end == mach->accel.sx_start) {
mach_log("No SRC.\n");
return;
}
}
if (cpu_input) {
if (mach->accel.dp_config == 0x3251) {
mach_log("DPCONFIG 3251: monosrc=%d, frgdsel=%d, bkgdsel=%d, pitch=%d.\n", mono_src, frgd_sel, bkgd_sel, dev->pitch);
if (dev->accel.sy == mach->accel.height)
return;
}
}
while (count--) {
switch (mono_src) {
case 0:
mix = 1;
break;
case 1:
if (mach->accel.mono_pattern_enable)
mix = mach->accel.mono_pattern[dev->accel.dy & 7][dev->accel.dx & 7];
else {
if ((dev->accel_bpp == 24) && (frgd_sel == 5) && (mach->accel.patt_len_reg & 0x4000))
mix = 1;
else {
if (!dev->accel.temp_cnt) {
dev->accel.temp_cnt = 8;
mix_dat >>= 8;
}
mix = (mix_dat & 0x80);
dev->accel.temp_cnt--;
mix_dat <<= 1;
mix_dat |= 1;
}
}
break;
case 2:
if (mach->accel.dp_config & 0x1000) {
mix = mix_dat >> 0x1f;
mix_dat <<= 1;
} else {
if (mach->accel.dp_config & 0x200) {
mix = mix_dat & 1;
mix_dat >>= 1;
} else {
mix = mix_dat & 0x80;
mix_dat <<= 1;
mix_dat |= 1;
}
}
break;
case 3:
READ(dev->accel.src + dev->accel.cx, mix);
mix = (mix & rd_mask) == rd_mask;
break;
default:
break;
}
if (((dev->accel.dx) >= clip_l) && ((dev->accel.dx) <= clip_r) && ((dev->accel.dy) >= clip_t) && ((dev->accel.dy) <= clip_b)) {
if ((mach->accel.dp_config & 0x02) || (mach->accel.linedraw_opt & 0x02)) {
READ(dev->accel.src + dev->accel.cx, poly_src);
poly_src = ((poly_src & rd_mask) == rd_mask);
if (poly_src)
mach->accel.poly_fill ^= 1;
}
if (mach->accel.poly_fill || !(mach->accel.dp_config & 0x02) || !(mach->accel.linedraw_opt & 0x02)) {
switch (mix ? frgd_sel : bkgd_sel) {
case 0:
src_dat = dev->accel.bkgd_color;
break;
case 1:
src_dat = dev->accel.frgd_color;
break;
case 2:
src_dat = cpu_dat;
break;
case 3:
if (mach_pixel_read(mach))
src_dat = cpu_dat;
else {
READ(dev->accel.src + dev->accel.cx, src_dat);
if (mono_src == 3)
src_dat = (src_dat & rd_mask) == rd_mask;
}
break;
case 5:
if (mix) {
if (dev->bpp)
src_dat = mach->accel.color_pattern_word[mach->accel.color_pattern_idx];
else
src_dat = mach->accel.color_pattern[mach->accel.color_pattern_idx];
} else
src_dat = 0;
break;
default:
break;
}
if ((dev->accel_bpp == 24) && (mono_src == 1) && (frgd_sel == 5) && (mach->accel.patt_len_reg & 0x4000)) {
if (dev->accel.sy & 1) {
READ(dev->accel.dest + dev->accel.dx - dev->ext_pitch, dest_dat);
} else {
READ(dev->accel.dest + dev->accel.dx, dest_dat);
}
} else {
READ(dev->accel.dest + dev->accel.dx, dest_dat);
}
switch (compare_mode) {
case 1:
compare = 1;
break;
case 2:
compare = (dest_dat >= dest_cmp_clr) ? 0 : 1;
break;
case 3:
compare = (dest_dat < dest_cmp_clr) ? 0 : 1;
break;
case 4:
compare = (dest_dat != dest_cmp_clr) ? 0 : 1;
break;
case 5:
compare = (dest_dat == dest_cmp_clr) ? 0 : 1;
break;
case 6:
compare = (dest_dat <= dest_cmp_clr) ? 0 : 1;
break;
case 7:
compare = (dest_dat > dest_cmp_clr) ? 0 : 1;
break;
default:
break;
}
if (!compare) {
if (mach_pixel_write(mach)) {
old_dest_dat = dest_dat;
MIX(mix, dest_dat, src_dat);
dest_dat = (dest_dat & wrt_mask) | (old_dest_dat & ~wrt_mask);
}
}
if (mach->accel.dp_config & 0x10) {
if ((dev->accel_bpp == 24) && (mono_src == 1) && (frgd_sel == 5) && (mach->accel.patt_len_reg & 0x4000)) {
if (dev->accel.sy & 1) {
WRITE(dev->accel.dest + dev->accel.dx - dev->ext_pitch, dest_dat);
} else {
WRITE(dev->accel.dest + dev->accel.dx, dest_dat);
}
} else {
WRITE(dev->accel.dest + dev->accel.dx, dest_dat);
}
}
}
}
if (dev->bpp)
cpu_dat >>= 16;
else
cpu_dat >>= 8;
if ((mono_src == 3) || (frgd_sel == 3) || (bkgd_sel == 3) || (mach->accel.dp_config & 0x02)) {
dev->accel.cx += mach->accel.src_stepx;
mach->accel.sx++;
if (mach->accel.sx >= mach->accel.src_width) {
mach->accel.sx = 0;
if (mach->accel.src_stepx == -1)
dev->accel.cx += mach->accel.src_width;
else
dev->accel.cx -= mach->accel.src_width;
dev->accel.cy += (mach->accel.src_y_dir ? 1 : -1);
if (dev->bpp)
dev->accel.src = (mach->accel.ge_offset << 1) + (dev->accel.cy * (dev->pitch));
else
dev->accel.src = (mach->accel.ge_offset << 2) + (dev->accel.cy * (dev->pitch));
}
}
dev->accel.dx += mach->accel.stepx;
if ((dev->accel_bpp == 8) || ((dev->accel_bpp == 24) && (mach->accel.patt_len >= 3) && (mono_src != 1)))
mach->accel.color_pattern_idx = (mach->accel.color_pattern_idx + mach->accel.stepx) & mach->accel.patt_len;
if ((dev->accel_bpp == 24) && (mach->accel.color_pattern_idx == mach->accel.patt_len) && (mach->accel.patt_len >= 3) && (mono_src != 1)) {
mach->accel.color_pattern_idx = mach->accel.patt_data_idx;
} else if ((dev->accel_bpp == 24) && (mach->accel.patt_len < 3)) {
if (mach->accel.patt_len == 2) {
mach->accel.color_pattern_idx++;
if (mach->accel.color_pattern_idx == 3)
mach->accel.color_pattern_idx = 0;
} else
mach->accel.color_pattern_idx = (mach->accel.color_pattern_idx + mach->accel.stepx) & mach->accel.patt_len;
} else if ((dev->accel_bpp == 24) && (mach->accel.patt_len_reg & 0x4000) && (frgd_sel == 5)) {
mach->accel.color_pattern_idx++;
if (mach->accel.color_pattern_idx == 3)
mach->accel.color_pattern_idx = 0;
}
if (dev->bpp) {
mach->accel.color_pattern_idx = (mach->accel.color_pattern_idx + mach->accel.stepx) & mach->accel.patt_len;
mach->accel.color_pattern_idx = (mach->accel.color_pattern_idx + mach->accel.stepx) & mach->accel.patt_len;
}
dev->accel.sx++;
if ((dev->accel.sx >= mach->accel.width) || (dev->accel.dx >= 0x600)) {
dev->accel.sx = 0;
if (mach->accel.stepx == -1)
dev->accel.dx += mach->accel.width;
else
dev->accel.dx -= mach->accel.width;
dev->accel.dy += mach->accel.stepy;
dev->accel.sy++;
mach->accel.poly_fill = 0;
if (dev->bpp)
dev->accel.dest = (mach->accel.ge_offset << 1) + (dev->accel.dy * (dev->pitch));
else
dev->accel.dest = (mach->accel.ge_offset << 2) + (dev->accel.dy * (dev->pitch));
if ((mono_src == 1) && (dev->accel_bpp == 24) && (frgd_sel == 5))
mach->accel.color_pattern_idx = 0;
else
mach->accel.color_pattern_idx = ((dev->accel.dx + (dev->accel.dy << 3)) & mach->accel.patt_len);
if ((dev->accel_bpp == 24) && (mach->accel.color_pattern_idx == mach->accel.patt_len) && (mono_src != 1))
mach->accel.color_pattern_idx = 0;
if ((mono_src == 1) && !mach->accel.mono_pattern_enable && !(mach->accel.patt_len_reg & 0x4000)) {
dev->accel.cur_x = dev->accel.dx;
dev->accel.cur_y = dev->accel.dy;
return;
}
if (dev->accel.sy >= mach->accel.height) {
if ((mono_src == 2) || (mono_src == 3) || (frgd_sel == 3) || (bkgd_sel == 3) || (mach->accel.dp_config & 0x02) || (mach->accel.linedraw_opt & 0x02))
return;
if ((mono_src == 1) && (frgd_sel == 5) && (dev->accel_bpp == 24) && (mach->accel.patt_len_reg & 0x4000))
return;
dev->accel.cur_x = dev->accel.dx;
dev->accel.cur_y = dev->accel.dy;
return;
}
}
}
break;
case 3: /*Direct Linedraw (Polyline) from linedraw indexes (0xfeee)*/
case 4:
if (!cpu_input) {
dev->accel.cx = dev->accel.cur_x;
dev->accel.cy = dev->accel.cur_y;
if (dev->accel.cur_x >= 0x600) {
mach_log("Linedraw XOver = %d.\n", dev->accel.cur_x);
dev->accel.cx |= ~0x5ff;
}
if (dev->accel.cur_y >= 0x600) {
mach_log("Linedraw YOver = %d.\n", dev->accel.cur_y);
dev->accel.cy |= ~0x5ff;
}
dev->accel.dx = ABS(mach->accel.cx_end_line - dev->accel.cx) << 1;
dev->accel.dy = ABS(mach->accel.cy_end_line - dev->accel.cy) << 1;
mach->accel.stepx = (mach->accel.cx_end_line < dev->accel.cx) ? -1 : 1;
mach->accel.stepy = (mach->accel.cy_end_line < dev->accel.cy) ? -1 : 1;
dev->accel.sx = 0;
mach_log("Linedraw: c(%d,%d), d(%d,%d), cend(%d,%d), bounds: l=%d, r=%d, t=%d, b=%d.\n", dev->accel.cur_x, dev->accel.cur_y, dev->accel.dx, dev->accel.dy, mach->accel.cx_end_line, mach->accel.cy_end_line, mach->accel.bleft, mach->accel.bright, mach->accel.btop, mach->accel.bbottom);
if ((mono_src == 2) || (bkgd_sel == 2) || (frgd_sel == 2) || mach_pixel_read(mach)) {
if (mach_pixel_write(mach)) {
dev->data_available = 0;
dev->data_available2 = 0;
return;
} else if (mach_pixel_read(mach)) {
dev->data_available = 1;
dev->data_available2 = 1;
return;
}
}
}
if (frgd_sel == 5) {
for (int x = 0; x <= mach->accel.patt_len; x++) {
mach->accel.color_pattern[x] = mach->accel.patt_data[x & mach->accel.patt_len];
}
}
if (mono_src == 1) {
mix_dat = mach->accel.patt_data[0x10];
dev->accel.temp_cnt = 8;
}
count = (dev->accel.dx > dev->accel.dy) ? (dev->accel.dx >> 1) : (dev->accel.dy >> 1);
mach->accel.width = count;
if (dev->accel.dx > dev->accel.dy) {
mach->accel.err = (dev->accel.dy - dev->accel.dx) >> 1;
if (mono_src == 1) {
while (count--) {
if (!dev->accel.temp_cnt) {
dev->accel.temp_cnt = 8;
mix_dat >>= 8;
}
mix = (mix_dat & 0x80);
dev->accel.temp_cnt--;
mix_dat <<= 1;
mix_dat |= 1;
if ((dev->accel.cx >= clip_l) && (dev->accel.cx <= clip_r) && (dev->accel.cy >= clip_t) && (dev->accel.cy <= clip_b)) {
mach->accel.clip_overrun = 0;
switch (mix ? frgd_sel : bkgd_sel) {
case 0:
src_dat = dev->accel.bkgd_color;
break;
case 1:
src_dat = dev->accel.frgd_color;
break;
case 2:
src_dat = cpu_dat;
break;
case 3:
if (mach_pixel_read(mach))
src_dat = cpu_dat;
else
src_dat = 0;
break;
case 5:
if (mix)
src_dat = mach->accel.color_pattern[((dev->accel.cx) + ((dev->accel.cy) << 3)) & mach->accel.patt_len];
else
src_dat = 0;
break;
default:
break;
}
if (dev->bpp) {
READ((mach->accel.ge_offset << 1) + ((dev->accel.cy) * (dev->pitch)) + (dev->accel.cx), dest_dat);
} else {
READ((mach->accel.ge_offset << 2) + ((dev->accel.cy) * (dev->pitch)) + (dev->accel.cx), dest_dat);
}
switch (compare_mode) {
case 1:
compare = 1;
break;
case 2:
compare = (dest_dat >= dest_cmp_clr) ? 0 : 1;
break;
case 3:
compare = (dest_dat < dest_cmp_clr) ? 0 : 1;
break;
case 4:
compare = (dest_dat != dest_cmp_clr) ? 0 : 1;
break;
case 5:
compare = (dest_dat == dest_cmp_clr) ? 0 : 1;
break;
case 6:
compare = (dest_dat <= dest_cmp_clr) ? 0 : 1;
break;
case 7:
compare = (dest_dat > dest_cmp_clr) ? 0 : 1;
break;
default:
break;
}
if (!compare) {
if (mach_pixel_write(mach)) {
old_dest_dat = dest_dat;
MIX(mix, dest_dat, src_dat);
dest_dat = (dest_dat & wrt_mask) | (old_dest_dat & ~wrt_mask);
}
}
if ((mach->accel.dp_config & 0x10) && (cmd_type == 3)) {
if (dev->bpp) {
WRITE((mach->accel.ge_offset << 1) + ((dev->accel.cy) * (dev->pitch)) + (dev->accel.cx), dest_dat);
} else {
WRITE((mach->accel.ge_offset << 2) + ((dev->accel.cy) * (dev->pitch)) + (dev->accel.cx), dest_dat);
}
}
} else
mach->accel.clip_overrun = ((mach->accel.clip_overrun + 1) & 0x0f);
if (!count)
break;
if (dev->bpp)
cpu_dat >>= 16;
else
cpu_dat >>= 8;
if (mach->accel.err >= 0) {
dev->accel.cy += mach->accel.stepy;
mach->accel.err -= dev->accel.dx;
}
dev->accel.cx += mach->accel.stepx;
mach->accel.err += dev->accel.dy;
}
} else {
while (count--) {
switch (mono_src) {
case 0:
case 3:
mix = 1;
break;
case 2:
if (mach->accel.dp_config & 0x1000) {
mix = mix_dat >> 0x1f;
mix_dat <<= 1;
} else {
if (mach->accel.dp_config & 0x200) {
mix = mix_dat & 1;
mix_dat >>= 1;
} else {
mix = mix_dat & 0x80;
mix_dat <<= 1;
mix_dat |= 1;
}
}
break;
default:
break;
}
if ((dev->accel.cx >= clip_l) && (dev->accel.cx <= clip_r) && (dev->accel.cy >= clip_t) && (dev->accel.cy <= clip_b)) {
mach->accel.clip_overrun = 0;
if (mach->accel.linedraw_opt & 0x02) {
READ((mach->accel.ge_offset << 2) + ((dev->accel.cy) * (dev->pitch)) + (dev->accel.cx), poly_src);
if (poly_src)
mach->accel.poly_fill = !mach->accel.poly_fill;
}
switch (mix ? frgd_sel : bkgd_sel) {
case 0:
src_dat = dev->accel.bkgd_color;
break;
case 1:
src_dat = dev->accel.frgd_color;
break;
case 2:
src_dat = cpu_dat;
break;
case 3:
if (mach_pixel_read(mach))
src_dat = cpu_dat;
else {
src_dat = 0;
}
break;
case 5:
if (mix) {
src_dat = mach->accel.color_pattern[((dev->accel.cx) + ((dev->accel.cy) << 3)) & mach->accel.patt_len];
} else
src_dat = 0;
break;
default:
break;
}
if (dev->bpp) {
READ((mach->accel.ge_offset << 1) + ((dev->accel.cy) * (dev->pitch)) + (dev->accel.cx), dest_dat);
} else {
READ((mach->accel.ge_offset << 2) + ((dev->accel.cy) * (dev->pitch)) + (dev->accel.cx), dest_dat);
}
switch (compare_mode) {
case 1:
compare = 1;
break;
case 2:
compare = (dest_dat >= dest_cmp_clr) ? 0 : 1;
break;
case 3:
compare = (dest_dat < dest_cmp_clr) ? 0 : 1;
break;
case 4:
compare = (dest_dat != dest_cmp_clr) ? 0 : 1;
break;
case 5:
compare = (dest_dat == dest_cmp_clr) ? 0 : 1;
break;
case 6:
compare = (dest_dat <= dest_cmp_clr) ? 0 : 1;
break;
case 7:
compare = (dest_dat > dest_cmp_clr) ? 0 : 1;
break;
default:
break;
}
if (!compare) {
if (mach_pixel_write(mach)) {
old_dest_dat = dest_dat;
if (mach->accel.poly_fill || !(mach->accel.linedraw_opt & 0x02)) {
MIX(mix, dest_dat, src_dat);
}
dest_dat = (dest_dat & wrt_mask) | (old_dest_dat & ~wrt_mask);
}
}
if ((mach->accel.dp_config & 0x10) && (cmd_type == 3)) {
if (mach->accel.linedraw_opt & 0x04) {
if (dev->accel.sx < mach->accel.width) {
if (dev->bpp) {
WRITE((mach->accel.ge_offset << 1) + ((dev->accel.cy) * (dev->pitch)) + (dev->accel.cx), dest_dat);
} else {
WRITE((mach->accel.ge_offset << 2) + ((dev->accel.cy) * (dev->pitch)) + (dev->accel.cx), dest_dat);
}
}
} else {
if (dev->bpp) {
WRITE((mach->accel.ge_offset << 1) + ((dev->accel.cy) * (dev->pitch)) + (dev->accel.cx), dest_dat);
} else {
WRITE((mach->accel.ge_offset << 2) + ((dev->accel.cy) * (dev->pitch)) + (dev->accel.cx), dest_dat);
}
}
}
} else
mach->accel.clip_overrun = ((mach->accel.clip_overrun + 1) & 0x0f);
if (dev->accel.sx >= mach->accel.width)
break;
if (dev->bpp)
cpu_dat >>= 16;
else
cpu_dat >>= 8;
if (mach->accel.err >= 0) {
dev->accel.cy += mach->accel.stepy;
mach->accel.err -= dev->accel.dx;
}
dev->accel.cx += mach->accel.stepx;
mach->accel.err += dev->accel.dy;
dev->accel.sx++;
}
}
} else {
mach->accel.err = (dev->accel.dx - dev->accel.dy) >> 1;
if (mono_src == 1) {
while (count--) {
if (dev->accel.temp_cnt == 0) {
dev->accel.temp_cnt = 8;
mix_dat >>= 8;
}
mix = (mix_dat & 0x80);
dev->accel.temp_cnt--;
mix_dat <<= 1;
mix_dat |= 1;
if ((dev->accel.cx >= clip_l) && (dev->accel.cx <= clip_r) && (dev->accel.cy >= clip_t) && (dev->accel.cy <= clip_b)) {
mach->accel.clip_overrun = 0;
switch (mix ? frgd_sel : bkgd_sel) {
case 0:
src_dat = dev->accel.bkgd_color;
break;
case 1:
src_dat = dev->accel.frgd_color;
break;
case 2:
src_dat = cpu_dat;
break;
case 3:
if (mach_pixel_read(mach))
src_dat = cpu_dat;
else {
src_dat = 0;
}
break;
case 5:
if (mix) {
src_dat = mach->accel.color_pattern[((dev->accel.cx) + ((dev->accel.cy) << 3)) & mach->accel.patt_len];
} else
src_dat = 0;
break;
default:
break;
}
if (dev->bpp) {
READ((mach->accel.ge_offset << 1) + ((dev->accel.cy) * (dev->pitch)) + (dev->accel.cx), dest_dat);
} else {
READ((mach->accel.ge_offset << 2) + ((dev->accel.cy) * (dev->pitch)) + (dev->accel.cx), dest_dat);
}
switch (compare_mode) {
case 1:
compare = 1;
break;
case 2:
compare = (dest_dat >= dest_cmp_clr) ? 0 : 1;
break;
case 3:
compare = (dest_dat < dest_cmp_clr) ? 0 : 1;
break;
case 4:
compare = (dest_dat != dest_cmp_clr) ? 0 : 1;
break;
case 5:
compare = (dest_dat == dest_cmp_clr) ? 0 : 1;
break;
case 6:
compare = (dest_dat <= dest_cmp_clr) ? 0 : 1;
break;
case 7:
compare = (dest_dat > dest_cmp_clr) ? 0 : 1;
break;
default:
break;
}
if (!compare) {
if (mach_pixel_write(mach)) {
old_dest_dat = dest_dat;
MIX(mix, dest_dat, src_dat);
dest_dat = (dest_dat & wrt_mask) | (old_dest_dat & ~wrt_mask);
}
}
if ((mach->accel.dp_config & 0x10) && (cmd_type == 3)) {
if (dev->bpp) {
WRITE((mach->accel.ge_offset << 1) + ((dev->accel.cy) * (dev->pitch)) + (dev->accel.cx), dest_dat);
} else {
WRITE((mach->accel.ge_offset << 2) + ((dev->accel.cy) * (dev->pitch)) + (dev->accel.cx), dest_dat);
}
}
} else
mach->accel.clip_overrun = ((mach->accel.clip_overrun + 1) & 0x0f);
if (!count)
break;
if (dev->bpp)
cpu_dat >>= 16;
else
cpu_dat >>= 8;
if (mach->accel.err >= 0) {
dev->accel.cx += mach->accel.stepx;
mach->accel.err -= dev->accel.dy;
}
dev->accel.cy += mach->accel.stepy;
mach->accel.err += dev->accel.dx;
}
} else {
while (count--) {
switch (mono_src) {
case 0:
case 3:
mix = 1;
break;
case 2:
if (mach->accel.dp_config & 0x1000) {
mix = mix_dat >> 0x1f;
mix_dat <<= 1;
} else {
if (mach->accel.dp_config & 0x200) {
mix = mix_dat & 1;
mix_dat >>= 1;
} else {
mix = mix_dat & 0x80;
mix_dat <<= 1;
mix_dat |= 1;
}
}
break;
default:
break;
}
if ((dev->accel.cx >= clip_l) && (dev->accel.cx <= clip_r) && (dev->accel.cy >= clip_t) && (dev->accel.cy <= clip_b)) {
mach->accel.clip_overrun = 0;
switch (mix ? frgd_sel : bkgd_sel) {
case 0:
src_dat = dev->accel.bkgd_color;
break;
case 1:
src_dat = dev->accel.frgd_color;
break;
case 2:
src_dat = cpu_dat;
break;
case 3:
if (mach_pixel_read(mach))
src_dat = cpu_dat;
else {
src_dat = 0;
}
break;
case 5:
if (mix) {
src_dat = mach->accel.color_pattern[((dev->accel.cx) + ((dev->accel.cy) << 3)) & mach->accel.patt_len];
} else
src_dat = 0;
break;
default:
break;
}
if (dev->bpp) {
READ((mach->accel.ge_offset << 1) + ((dev->accel.cy) * (dev->pitch)) + (dev->accel.cx), dest_dat);
} else {
READ((mach->accel.ge_offset << 2) + ((dev->accel.cy) * (dev->pitch)) + (dev->accel.cx), dest_dat);
}
switch (compare_mode) {
case 1:
compare = 1;
break;
case 2:
compare = (dest_dat >= dest_cmp_clr) ? 0 : 1;
break;
case 3:
compare = (dest_dat < dest_cmp_clr) ? 0 : 1;
break;
case 4:
compare = (dest_dat != dest_cmp_clr) ? 0 : 1;
break;
case 5:
compare = (dest_dat == dest_cmp_clr) ? 0 : 1;
break;
case 6:
compare = (dest_dat <= dest_cmp_clr) ? 0 : 1;
break;
case 7:
compare = (dest_dat > dest_cmp_clr) ? 0 : 1;
break;
default:
break;
}
if (!compare) {
if (mach_pixel_write(mach)) {
old_dest_dat = dest_dat;
MIX(mix, dest_dat, src_dat);
dest_dat = (dest_dat & wrt_mask) | (old_dest_dat & ~wrt_mask);
}
}
if ((mach->accel.dp_config & 0x10) && (cmd_type == 3)) {
if (mach->accel.linedraw_opt & 0x04) {
if (dev->accel.sx < mach->accel.width) {
if (dev->bpp) {
WRITE((mach->accel.ge_offset << 1) + ((dev->accel.cy) * (dev->pitch)) + (dev->accel.cx), dest_dat);
} else {
WRITE((mach->accel.ge_offset << 2) + ((dev->accel.cy) * (dev->pitch)) + (dev->accel.cx), dest_dat);
}
}
} else {
if (dev->bpp) {
WRITE((mach->accel.ge_offset << 1) + ((dev->accel.cy) * (dev->pitch)) + (dev->accel.cx), dest_dat);
} else {
WRITE((mach->accel.ge_offset << 2) + ((dev->accel.cy) * (dev->pitch)) + (dev->accel.cx), dest_dat);
}
}
}
} else
mach->accel.clip_overrun = ((mach->accel.clip_overrun + 1) & 0x0f);
if (dev->accel.sx >= mach->accel.width)
break;
if (dev->bpp)
cpu_dat >>= 16;
else
cpu_dat >>= 8;
if (mach->accel.err >= 0) {
dev->accel.cx += mach->accel.stepx;
mach->accel.err -= dev->accel.dy;
}
dev->accel.cy += mach->accel.stepy;
mach->accel.err += dev->accel.dx;
dev->accel.sx++;
}
}
}
mach->accel.poly_fill = 0;
mach->accel.line_array[(cmd_type == 4) ? 4 : 0] = dev->accel.cx;
mach->accel.line_array[(cmd_type == 4) ? 5 : 1] = dev->accel.cy;
dev->accel.cur_x = mach->accel.line_array[(cmd_type == 4) ? 4 : 0];
dev->accel.cur_y = mach->accel.line_array[(cmd_type == 4) ? 5 : 1];
break;
case 5: /*Horizontal Raster Draw from scan_to_x register (0xcaee)*/
if (!cpu_input) {
mach->accel.stepx = 0;
mach->accel.stepy = 0;
dev->accel.dx = dev->accel.cur_x;
if (dev->accel.cur_x >= 0x600)
dev->accel.dx |= ~0x5ff;
dev->accel.dy = dev->accel.cur_y;
if (dev->accel.cur_y >= 0x600)
dev->accel.dy |= ~0x5ff;
/*Destination Width*/
mach->accel.dx_start = dev->accel.cur_x;
if (dev->accel.cur_x >= 0x600)
mach->accel.dx_start |= ~0x5ff;
mach->accel.dx_end = mach->accel.scan_to_x;
if (mach->accel.scan_to_x >= 0x600)
mach->accel.dx_end |= ~0x5ff;
if (mach->accel.dx_end > mach->accel.dx_start) {
mach->accel.width = (mach->accel.dx_end - mach->accel.dx_start);
mach->accel.stepx = 1;
} else if (mach->accel.dx_end < mach->accel.dx_start) {
mach->accel.width = (mach->accel.dx_start - mach->accel.dx_end);
mach->accel.stepx = -1;
if (dev->accel.dx > 0)
dev->accel.dx--;
} else {
mach->accel.stepx = 1;
mach->accel.width = 0;
}
dev->accel.sx = 0;
if ((dev->accel_bpp == 24) && (mach->accel.patt_len < 0x17))
mach->accel.color_pattern_idx = 0;
/*Step Y*/
mach->accel.dy_start = dev->accel.cur_y;
if (dev->accel.cur_y >= 0x600)
mach->accel.dy_start |= ~0x5ff;
mach->accel.dy_end = mach->accel.dest_y_end;
if (mach->accel.dest_y_end >= 0x600)
mach->accel.dy_end |= ~0x5ff;
if (mach->accel.dy_end > mach->accel.dy_start) {
mach->accel.stepy = 1;
} else if (mach->accel.dy_end < mach->accel.dy_start) {
mach->accel.stepy = -1;
} else {
mach->accel.stepy = 0;
}
if (dev->bpp)
dev->accel.dest = (mach->accel.ge_offset << 1) + (dev->accel.dy * (dev->pitch));
else
dev->accel.dest = (mach->accel.ge_offset << 2) + (dev->accel.dy * (dev->pitch));
mach->accel.src_stepx = 0;
/*Source Width*/
dev->accel.cx = mach->accel.src_x;
if (mach->accel.src_x >= 0x600)
dev->accel.cx |= ~0x5ff;
dev->accel.cy = mach->accel.src_y;
if (mach->accel.src_y >= 0x600)
dev->accel.cy |= ~0x5ff;
mach->accel.sx_start = mach->accel.src_x_start;
if (mach->accel.src_x_start >= 0x600)
mach->accel.sx_start |= ~0x5ff;
mach->accel.sx_end = mach->accel.src_x_end;
if (mach->accel.src_x_end >= 0x600)
mach->accel.sx_end |= ~0x5ff;
if (mach->accel.sx_end > mach->accel.sx_start) {
mach->accel.src_width = (mach->accel.sx_end - mach->accel.sx_start);
mach->accel.src_stepx = 1;
} else if (mach->accel.sx_end < mach->accel.sx_start) {
mach->accel.src_width = (mach->accel.sx_start - mach->accel.sx_end);
mach->accel.src_stepx = -1;
if (dev->accel.cx > 0)
dev->accel.cx--;
} else {
mach->accel.src_stepx = 1;
mach->accel.src_width = 0;
}
mach->accel.sx = 0;
if (dev->bpp)
dev->accel.src = (mach->accel.ge_offset << 1) + (dev->accel.cy * (dev->pitch));
else
dev->accel.src = (mach->accel.ge_offset << 2) + (dev->accel.cy * (dev->pitch));
if ((dev->accel_bpp == 24) && (frgd_sel == 5)) {
if (mach->accel.patt_len == 0x17)
mach->accel.color_pattern_idx = 0;
dev->accel.x1 = dev->accel.dx + mach->accel.width;
if (dev->accel.x1 == dev->pitch) {
dev->accel.x2 = mach->accel.width & 1;
} else if ((dev->accel.x1 == mach->accel.width) && (dev->accel.dy & 1) && !dev->accel.y1 && dev->accel.x2) {
if (mach->accel.patt_len == 0x17)
mach->accel.color_pattern_idx = 3;
dev->accel.x3 = 1;
} else
dev->accel.x3 = 0;
} else
mach_log("ScanToX=%04x, Pitch=%d, C(%d,%d), SRCWidth=%d, WH(%d,%d), geoffset=%08x.\n", mach->accel.dp_config, dev->ext_pitch, dev->accel.cx, dev->accel.cy, mach->accel.src_width, mach->accel.width, mach->accel.height, (mach->accel.ge_offset << 1));
dev->accel.y1 = 0;
if ((mono_src == 2) || (bkgd_sel == 2) || (frgd_sel == 2) || mach_pixel_read(mach)) {
if (mach_pixel_write(mach)) {
dev->data_available = 0;
dev->data_available2 = 0;
return;
} else if (mach_pixel_read(mach)) {
dev->data_available = 1;
dev->data_available2 = 1;
return;
}
}
}
if (mono_src == 1) {
count = mach->accel.width;
mix_dat = mach->accel.patt_data[0x10];
dev->accel.temp_cnt = 8;
}
if (frgd_sel == 5) {
if (dev->accel_bpp != 24) {
for (int x = 0; x <= mach->accel.patt_len; x++) {
mach->accel.color_pattern[x] = mach->accel.patt_data[x & mach->accel.patt_len];
}
} else {
if (mach->accel.patt_len == 0x17) {
for (int x = 0; x <= mach->accel.patt_len; x++) {
mach->accel.color_pattern_full[x] = mach->accel.patt_data[x];
mach_log("ScanToX: Color Pattern 24bpp[%d]=%02x, dataidx=%d, pattlen=%d.\n", x, mach->accel.color_pattern_full[x], mach->accel.patt_data_idx, mach->accel.patt_len);
}
} else {
for (int x = 0; x <= mach->accel.patt_len; x++) {
mach->accel.color_pattern[x] = mach->accel.patt_data[x];
mach_log("ScanToX: Color Pattern 24bpp[%d]=%02x, dataidx=%d, pattlen=%d.\n", x, mach->accel.color_pattern[x], mach->accel.patt_data_idx, mach->accel.patt_len);
}
}
}
}
while (count--) {
switch (mono_src) {
case 0:
mix = 1;
break;
case 1:
if (!dev->accel.temp_cnt) {
dev->accel.temp_cnt = 8;
mix_dat >>= 8;
}
mix = (mix_dat & 0x80);
dev->accel.temp_cnt--;
mix_dat <<= 1;
mix_dat |= 1;
break;
case 2:
if (mach->accel.dp_config & 0x1000) {
mix = mix_dat >> 0x1f;
mix_dat <<= 1;
} else {
if (mach->accel.dp_config & 0x200) {
mix = mix_dat & 1;
mix_dat >>= 1;
} else {
mix = mix_dat & 0x80;
mix_dat <<= 1;
mix_dat |= 1;
}
}
break;
case 3:
READ(dev->accel.src + (dev->accel.cx), mix);
mix = (mix & rd_mask) == rd_mask;
break;
default:
break;
}
if (((dev->accel.dx) >= clip_l) && ((dev->accel.dx) <= clip_r) && ((dev->accel.dy) >= clip_t) && ((dev->accel.dy) <= clip_b)) {
switch (mix ? frgd_sel : bkgd_sel) {
case 0:
src_dat = dev->accel.bkgd_color;
break;
case 1:
src_dat = dev->accel.frgd_color;
break;
case 2:
src_dat = cpu_dat;
break;
case 3:
if (mach_pixel_read(mach))
src_dat = cpu_dat;
else {
READ(dev->accel.src + dev->accel.cx, src_dat);
if (mono_src == 3)
src_dat = (src_dat & rd_mask) == rd_mask;
}
break;
case 5:
if (mix) {
if (dev->accel_bpp == 24) {
if (mach->accel.patt_len == 0x17)
src_dat = mach->accel.color_pattern_full[mach->accel.color_pattern_idx];
else
src_dat = mach->accel.color_pattern[mach->accel.color_pattern_idx];
} else
src_dat = mach->accel.color_pattern[(dev->accel.dx + (dev->accel.dy << 3)) & mach->accel.patt_len];
} else
src_dat = 0;
break;
default:
break;
}
READ(dev->accel.dest + dev->accel.dx, dest_dat);
switch (compare_mode) {
case 1:
compare = 1;
break;
case 2:
compare = (dest_dat >= dest_cmp_clr) ? 0 : 1;
break;
case 3:
compare = (dest_dat < dest_cmp_clr) ? 0 : 1;
break;
case 4:
compare = (dest_dat != dest_cmp_clr) ? 0 : 1;
break;
case 5:
compare = (dest_dat == dest_cmp_clr) ? 0 : 1;
break;
case 6:
compare = (dest_dat <= dest_cmp_clr) ? 0 : 1;
break;
case 7:
compare = (dest_dat > dest_cmp_clr) ? 0 : 1;
break;
default:
break;
}
if (!compare) {
if (mach_pixel_write(mach)) {
old_dest_dat = dest_dat;
MIX(mix, dest_dat, src_dat);
dest_dat = (dest_dat & wrt_mask) | (old_dest_dat & ~wrt_mask);
}
}
if (mach->accel.dp_config & 0x10) {
WRITE(dev->accel.dest + (dev->accel.dx), dest_dat);
}
}
if (dev->bpp)
cpu_dat >>= 16;
else
cpu_dat >>= 8;
dev->accel.cx += mach->accel.src_stepx;
mach->accel.sx++;
if (mach->accel.sx >= mach->accel.src_width) {
mach->accel.sx = 0;
if (mach->accel.src_stepx == -1) {
dev->accel.cx += mach->accel.src_width;
} else
dev->accel.cx -= mach->accel.src_width;
dev->accel.cy += (mach->accel.src_y_dir ? 1 : -1);
if (dev->bpp)
dev->accel.src = (mach->accel.ge_offset << 1) + (dev->accel.cy * (dev->pitch));
else
dev->accel.src = (mach->accel.ge_offset << 2) + (dev->accel.cy * (dev->pitch));
}
dev->accel.dx += mach->accel.stepx;
if ((dev->accel_bpp == 24) && (mach->accel.patt_len == 0x17)) {
mach->accel.color_pattern_idx++;
if (dev->accel.x3) {
if (mach->accel.color_pattern_idx == 9)
mach->accel.color_pattern_idx = 3;
} else {
if (mach->accel.color_pattern_idx == 6)
mach->accel.color_pattern_idx = 0;
}
} else if ((dev->accel_bpp == 24) && (mach->accel.patt_len < 3)) {
mach->accel.color_pattern_idx++;
if (mach->accel.color_pattern_idx == 3)
mach->accel.color_pattern_idx = 0;
} else
mach->accel.color_pattern_idx = (mach->accel.color_pattern_idx + mach->accel.stepx) & mach->accel.patt_len;
dev->accel.sx++;
if (dev->accel.sx >= mach->accel.width) {
dev->accel.sx = 0;
dev->accel.dy += mach->accel.stepy;
if (dev->bpp)
dev->accel.dest = (mach->accel.ge_offset << 1) + (dev->accel.dy * (dev->pitch));
else
dev->accel.dest = (mach->accel.ge_offset << 2) + (dev->accel.dy * (dev->pitch));
if (mach->accel.line_idx == 2) {
mach->accel.line_array[0] = dev->accel.dx;
mach->accel.line_array[4] = dev->accel.dx;
}
return;
}
}
break;
default:
break;
}
}
static void
mach_accel_out_pixtrans(mach_t *mach, ibm8514_t *dev, uint16_t val)
{
int frgd_sel;
int bkgd_sel;
int mono_src;
frgd_sel = (mach->accel.dp_config >> 13) & 7;
bkgd_sel = (mach->accel.dp_config >> 7) & 3;
mono_src = (mach->accel.dp_config >> 5) & 3;
if ((mach->accel.dp_config & 4) && (mach->accel.cmd_type != 5)) {
val = (val >> 8) | (val << 8);
}
switch (mach->accel.dp_config & 0x200) {
case 0x000: /*8-bit size*/
if (mono_src == 2) {
if ((frgd_sel != 2) && (bkgd_sel != 2)) {
if (mach->accel.dp_config & 0x1000)
val = (val >> 8) | (val << 8);
mach_accel_start(mach->accel.cmd_type, 1, 8, val | (val << 16), 0, mach, dev);
} else
mach_accel_start(mach->accel.cmd_type, 1, 1, -1, val | (val << 16), mach, dev);
} else
mach_accel_start(mach->accel.cmd_type, 1, 1, -1, val | (val << 16), mach, dev);
break;
case 0x200: /*16-bit size*/
if (mono_src == 2) {
if ((frgd_sel != 2) && (bkgd_sel != 2)) {
if (mach->accel.dp_config & 0x1000)
val = (val >> 8) | (val << 8);
mach_accel_start(mach->accel.cmd_type, 1, 16, val | (val << 16), 0, mach, dev);
} else
mach_accel_start(mach->accel.cmd_type, 1, 2, -1, val | (val << 16), mach, dev);
} else
mach_accel_start(mach->accel.cmd_type, 1, 2, -1, val | (val << 16), mach, dev);
break;
default:
break;
}
}
static void
mach_out(uint16_t addr, uint8_t val, void *priv)
{
mach_t *mach = (mach_t *) priv;
svga_t *svga = &mach->svga;
const ibm8514_t *dev = (ibm8514_t *) svga->dev8514;
uint8_t old;
uint8_t rs2;
uint8_t rs3;
if (((addr & 0xFFF0) == 0x3D0 || (addr & 0xFFF0) == 0x3B0) && !(svga->miscout & 1))
addr ^= 0x60;
switch (addr) {
case 0x1ce:
mach->index = val;
break;
case 0x1cf:
old = mach->regs[mach->index];
mach->regs[mach->index] = val;
mach_log("ATI VGA write reg=0x%02X, val=0x%02X\n", mach->index, val);
switch (mach->index) {
case 0xa3:
if ((old ^ val) & 0x10)
svga_recalctimings(svga);
break;
case 0xa7:
if ((old ^ val) & 0x80)
svga_recalctimings(svga);
break;
case 0xad:
if ((dev->local & 0xff) >= 0x02) {
if ((old ^ val) & 0x0c)
svga_recalctimings(svga);
}
break;
case 0xb0:
if ((old ^ val) & 0x60)
svga_recalctimings(svga);
break;
case 0xae:
case 0xb2:
case 0xbe:
mach_log("ATI VGA write reg=0x%02X, val=0x%02X\n", mach->index, val);
if (mach->regs[0xbe] & 0x08) { /* Read/write bank mode */
mach->bank_r = (((mach->regs[0xb2] & 1) << 3) | ((mach->regs[0xb2] & 0xe0) >> 5));
mach->bank_w = ((mach->regs[0xb2] & 0x1e) >> 1);
if ((dev->local & 0xff) >= 0x02) {
mach->bank_r |= ((mach->regs[0xae] & 0x0c) << 2);
mach->bank_w |= ((mach->regs[0xae] & 3) << 4);
}
if (dev->on[0] || dev->on[1])
mach_log("Separate B2Bank = %02x, AEbank = %02x.\n", mach->regs[0xb2], mach->regs[0xae]);
} else { /* Single bank mode */
mach->bank_w = ((mach->regs[0xb2] & 0x1e) >> 1);
if ((dev->local & 0xff) >= 0x02) {
mach->bank_w |= ((mach->regs[0xae] & 3) << 4);
}
mach->bank_r = mach->bank_w;
if (dev->on[0] || dev->on[1])
mach_log("Single B2Bank = %02x, AEbank = %02x.\n", mach->regs[0xb2], mach->regs[0xae]);
}
svga->read_bank = mach->bank_r << 16;
svga->write_bank = mach->bank_w << 16;
if (mach->index == 0xbe) {
if ((old ^ val) & 0x10)
svga_recalctimings(svga);
}
break;
case 0xbd:
if ((old ^ val) & 4) {
mach32_updatemapping(mach, svga);
}
break;
case 0xb3:
ati_eeprom_write(&mach->eeprom, val & 8, val & 2, val & 1);
break;
case 0xb6:
if ((old ^ val) & 0x10)
svga_recalctimings(svga);
break;
case 0xb8:
if ((dev->local & 0xff) >= 0x02) {
if ((old ^ val) & 0x40)
svga_recalctimings(svga);
} else {
if ((old ^ val) & 0xc0)
svga_recalctimings(svga);
}
break;
case 0xb9:
if ((old ^ val) & 2)
svga_recalctimings(svga);
break;
default:
break;
}
break;
case 0x2ea:
case 0x2eb:
case 0x2ec:
case 0x2ed:
rs2 = !!(mach->accel.ext_ge_config & 0x1000);
rs3 = !!(mach->accel.ext_ge_config & 0x2000);
if ((dev->local & 0xff) >= 0x02) {
if (mach->pci_bus && !mach->ramdac_type)
ati68860_ramdac_out((addr & 3) | (rs2 << 2) | (rs3 << 3), val, svga->ramdac, svga);
else
ati68875_ramdac_out(addr, rs2, rs3, val, svga->ramdac, svga);
} else
svga_out(addr, val, svga);
return;
case 0x3C6:
case 0x3C7:
case 0x3C8:
case 0x3C9:
rs2 = !!(mach->regs[0xa0] & 0x20);
rs3 = !!(mach->regs[0xa0] & 0x40);
if ((dev->local & 0xff) >= 0x02) {
if (mach->pci_bus && !mach->ramdac_type)
ati68860_ramdac_out((addr & 3) | (rs2 << 2) | (rs3 << 3), val, svga->ramdac, svga);
else
ati68875_ramdac_out(addr, rs2, rs3, val, svga->ramdac, svga);
} else
svga_out(addr, val, svga);
return;
case 0x3D4:
svga->crtcreg = val & 0x3f;
return;
case 0x3D5:
if (svga->crtcreg & 0x20)
return;
if ((svga->crtcreg < 7) && (svga->crtc[0x11] & 0x80) && !(mach->regs[0xb4] & 0x80))
return;
if ((svga->crtcreg == 7) && (svga->crtc[0x11] & 0x80) && !(mach->regs[0xb4] & 0x80))
val = (svga->crtc[7] & ~0x10) | (val & 0x10);
old = svga->crtc[svga->crtcreg];
svga->crtc[svga->crtcreg] = val;
if (old != val) {
if (svga->crtcreg < 0xe || svga->crtcreg > 0x10) {
if ((svga->crtcreg == 0xc) || (svga->crtcreg == 0xd)) {
svga->fullchange = 3;
svga->ma_latch = ((svga->crtc[0xc] << 8) | svga->crtc[0xd]) + ((svga->crtc[8] & 0x60) >> 5);
} else {
svga->fullchange = changeframecount;
svga_recalctimings(svga);
}
}
}
break;
default:
break;
}
svga_out(addr, val, svga);
}
static uint8_t
mach_in(uint16_t addr, void *priv)
{
mach_t *mach = (mach_t *) priv;
svga_t *svga = &mach->svga;
const ibm8514_t *dev = (ibm8514_t *) svga->dev8514;
uint8_t temp = 0xff;
uint8_t rs2;
uint8_t rs3;
if (((addr & 0xFFF0) == 0x3D0 || (addr & 0xFFF0) == 0x3B0) && !(svga->miscout & 1))
addr ^= 0x60;
if ((addr >= 0x3c6) && (addr <= 0x3c9) && (dev->on[0] || dev->on[1]))
addr -= 0xdc;
switch (addr) {
case 0x1ce:
temp = mach->index;
break;
case 0x1cf:
switch (mach->index) {
case 0xa0:
temp = mach->regs[0xa0] | 0x10;
break;
case 0xa8:
temp = (svga->vc >> 8) & 3;
break;
case 0xa9:
temp = svga->vc & 0xff;
break;
case 0xb0:
temp = mach->regs[0xb0] | 0x80;
temp &= ~0x18;
if ((dev->local & 0xff) >= 0x02) { /*Mach32 VGA 1MB memory*/
temp |= 0x08;
} else { /*ATI 28800 VGA 512kB memory*/
temp |= 0x10;
}
break;
case 0xb7:
temp = mach->regs[0xb7] & ~0x08;
if (ati_eeprom_read(&mach->eeprom))
temp |= 0x08;
break;
case 0xbd:
temp = mach->regs[0xbd] | 0x10;
break;
default:
temp = mach->regs[mach->index];
break;
}
break;
case 0x2ea:
case 0x2eb:
case 0x2ec:
case 0x2ed:
rs2 = !!(mach->accel.ext_ge_config & 0x1000);
rs3 = !!(mach->accel.ext_ge_config & 0x2000);
if ((dev->local & 0xff) >= 0x02) {
if (mach->pci_bus && !mach->ramdac_type)
temp = ati68860_ramdac_in((addr & 3) | (rs2 << 2) | (rs3 << 3), svga->ramdac, svga);
else
temp = ati68875_ramdac_in(addr, rs2, rs3, svga->ramdac, svga);
} else
temp = svga_in(addr, svga);
break;
case 0x3D4:
temp = svga->crtcreg;
break;
case 0x3D5:
if (svga->crtcreg & 0x20)
temp = 0xff;
else
temp = svga->crtc[svga->crtcreg];
break;
default:
temp = svga_in(addr, svga);
break;
}
return temp;
}
#ifdef ATI_8514_ULTRA
static void
ati8514_out(uint16_t addr, uint8_t val, void *priv)
{
mach_log("[%04X:%08X]: ADDON OUT addr=%03x, val=%02x.\n", CS, cpu_state.pc, addr, val);
svga_out(addr, val, priv);
}
static uint8_t
ati8514_in(uint16_t addr, void *priv)
{
uint8_t temp = 0xff;
temp = svga_in(addr, priv);
mach_log("[%04X:%08X]: ADDON IN addr=%03x, temp=%02x.\n", CS, cpu_state.pc, addr, temp);
return temp;
}
void
ati8514_recalctimings(svga_t *svga)
{
mach_t *mach = (mach_t *) svga->ext8514;
ibm8514_t *dev = (ibm8514_t *) svga->dev8514;
mach_log("ON0=%d, ON1=%d, vgahdisp=%d.\n", dev->on[0], dev->on[1], svga->hdisp);
if (dev->on[0] || dev->on[1]) {
mach_log("8514/A ON.\n");
dev->h_total = dev->htotal + 1;
dev->rowcount = !!(dev->disp_cntl & 0x08);
dev->accel.ge_offset = (mach->accel.ge_offset_lo | (mach->accel.ge_offset_hi << 16));
mach->accel.ge_offset = dev->accel.ge_offset;
mach_log("HDISP=%d, VDISP=%d, shadowset=%x, 8514/A mode=%x, clocksel=%02x.\n", dev->hdisp, dev->vdisp, mach->shadow_set & 0x03, dev->accel.advfunc_cntl & 0x04, mach->accel.clock_sel & 0xfe);
if (dev->accel.advfunc_cntl & 0x01) {
if (dev->accel.advfunc_cntl & 0x04) {
dev->h_disp = dev->hdisp;
dev->dispend = dev->vdisp;
} else {
dev->h_disp = 640;
dev->dispend = 480;
}
} else {
dev->h_disp = dev->hdisp;
dev->dispend = dev->vdisp;
}
if (dev->accel.advfunc_cntl & 0x04) {
svga->clock8514 = (cpuclock * (double) (1ULL << 32)) / 44900000.0;
} else {
svga->clock8514 = (cpuclock * (double) (1ULL << 32)) / 25175000.0;
}
if (dev->dispend == 766)
dev->dispend += 2;
if (dev->dispend == 598)
dev->dispend += 2;
if (dev->dispend == 478)
dev->dispend += 2;
dev->pitch = dev->ext_pitch;
dev->rowoffset = dev->ext_crt_pitch;
mach_log("cntl=%d, hv(%d,%d), pitch=%d, rowoffset=%d, gextconfig=%03x, shadow=%x interlace=%d.\n", dev->accel.advfunc_cntl & 0x04, dev->h_disp, dev->dispend, dev->pitch, dev->rowoffset, mach->accel.ext_ge_config & 0xcec0, mach->shadow_set & 3, dev->interlace);
svga->map8 = dev->pallook;
svga->render8514 = ibm8514_render_8bpp;
} else {
if (!(svga->gdcreg[6] & 1) && !(svga->attrregs[0x10] & 1)) { /*Text mode*/
if (svga->seqregs[1] & 8) { /*40 column*/
svga->render = svga_render_text_40;
} else {
svga->render = svga_render_text_80;
}
}
}
}
#endif
static void
mach_recalctimings(svga_t *svga)
{
mach_t *mach = (mach_t *) svga->priv;
ibm8514_t *dev = (ibm8514_t *) svga->dev8514;
int clock_sel;
if (mach->regs[0xad] & 0x08)
svga->hblankstart = ((mach->regs[0x0d] >> 2) << 8) + svga->crtc[2];
clock_sel = ((svga->miscout >> 2) & 3) | ((mach->regs[0xbe] & 0x10) >> 1) | ((mach->regs[0xb9] & 2) << 1);
if ((dev->local & 0xff) >= 0x02) {
if (mach->regs[0xad] & 0x04)
svga->ma_latch |= 0x40000;
if (mach->regs[0xad] & 0x08)
svga->ma_latch |= 0x80000;
}
if (mach->regs[0xa3] & 0x10)
svga->ma_latch |= 0x10000;
if (mach->regs[0xb0] & 0x40)
svga->ma_latch |= 0x20000;
if ((mach->regs[0xb6] & 0x18) >= 0x10) {
svga->hdisp <<= 1;
svga->htotal <<= 1;
svga->dots_per_clock <<= 1;
svga->rowoffset <<= 1;
svga->gdcreg[5] &= ~0x40;
}
if (mach->regs[0xb0] & 0x20) {
svga->gdcreg[5] |= 0x40;
if ((mach->regs[0xb6] & 0x18) >= 0x10)
svga->packed_4bpp = 1;
else
svga->packed_4bpp = 0;
} else
svga->packed_4bpp = 0;
if ((dev->local & 0xff) < 0x02) {
if ((mach->regs[0xb6] & 0x18) == 8) {
svga->hdisp <<= 1;
svga->htotal <<= 1;
svga->dots_per_clock <<= 1;
svga->ati_4color = 1;
} else
svga->ati_4color = 0;
}
svga->render8514 = ibm8514_render_blank;
mach_log("ON[0]=%d, ON[1]=%d, exton[0]=%d, exton[1]=%d, vendormode0=%d, vendormode1=%d.\n", dev->on[0], dev->on[1], mach->ext_on[0], mach->ext_on[1], dev->vendor_mode[0], dev->vendor_mode[1]);
if (dev->on[0] || dev->on[1]) {
mach_log("8514/A ON.\n");
dev->h_total = dev->htotal + 1;
dev->rowcount = !!(dev->disp_cntl & 0x08);
dev->accel.ge_offset = (mach->accel.ge_offset_lo | (mach->accel.ge_offset_hi << 16));
mach->accel.ge_offset = dev->accel.ge_offset;
mach_log("HDISP=%d, VDISP=%d, shadowset=%x, 8514/A mode=%x, clocksel=%02x.\n", dev->hdisp, dev->vdisp, mach->shadow_set & 0x03, dev->accel.advfunc_cntl & 0x04, mach->accel.clock_sel & 0xfe);
if (!dev->bpp) {
if (dev->accel.advfunc_cntl & 0x01) {
if (dev->accel.advfunc_cntl & 0x04) {
dev->h_disp = dev->hdisp;
dev->dispend = dev->vdisp;
} else {
dev->h_disp = 640;
dev->dispend = 480;
}
} else {
dev->h_disp = dev->hdisp;
dev->dispend = dev->vdisp;
}
} else {
dev->h_disp = dev->hdisp;
dev->dispend = dev->vdisp;
}
svga->clock8514 = (cpuclock * (double) (1ULL << 32)) / svga->getclock((mach->accel.clock_sel >> 2) & 0x0f, svga->clock_gen);
if (dev->interlace)
dev->dispend >>= 1;
if (dev->dispend == 478)
dev->dispend += 2;
if (dev->dispend == 598)
dev->dispend += 2;
if (dev->dispend == 766)
dev->dispend += 2;
if (dev->dispend == 1022)
dev->dispend += 2;
if ((dev->local & 0xff) >= 0x02) {
mach_log("HDISP=%d.\n", dev->h_disp);
dev->pitch = dev->ext_pitch;
dev->rowoffset = dev->ext_crt_pitch;
if ((mach->accel.ext_ge_config & 0x800) || (!(mach->accel.ext_ge_config & 0x8000) && !(mach->accel.ext_ge_config & 0x800))) {
if ((mach->accel.ext_ge_config & 0x30) == 0x20) {
if ((mach->accel.ext_ge_config & 0xc0) == 0x40)
dev->accel_bpp = 16;
else
dev->accel_bpp = 15;
} else if ((mach->accel.ext_ge_config & 0x30) == 0x30) {
if (mach->accel.ext_ge_config & 0x200)
dev->accel_bpp = 32;
else
dev->accel_bpp = 24;
} else
dev->accel_bpp = 8;
mach_log("hv(%d,%d), pitch=%d, rowoffset=%d, gextconfig=%03x, bpp=%d, shadow=%x, vgahdisp=%d.\n", dev->h_disp, dev->dispend, dev->pitch, dev->ext_crt_pitch, mach->accel.ext_ge_config & 0xcec0, dev->accel_bpp, mach->shadow_set & 3, svga->hdisp);
switch (dev->accel_bpp) {
case 8:
svga->render8514 = ibm8514_render_8bpp;
break;
case 15:
svga->render8514 = ibm8514_render_15bpp;
break;
case 16:
svga->render8514 = ibm8514_render_16bpp;
break;
case 24:
mach_log("GEConfig24bpp: %03x.\n", mach->accel.ext_ge_config & 0x600);
if (mach->accel.ext_ge_config & 0x400)
svga->render8514 = ibm8514_render_BGR;
else
svga->render8514 = ibm8514_render_24bpp;
break;
case 32:
mach_log("GEConfig32bpp: %03x.\n", mach->accel.ext_ge_config & 0x600);
if (mach->accel.ext_ge_config & 0x400)
svga->render8514 = ibm8514_render_ABGR8888;
else
svga->render8514 = ibm8514_render_32bpp;
break;
default:
break;
}
}
} else {
dev->pitch = dev->ext_pitch;
dev->rowoffset = dev->ext_crt_pitch;
mach_log("cntl=%d, hv(%d,%d), pitch=%d, rowoffset=%d, gextconfig=%03x, shadow=%x interlace=%d.\n", dev->accel.advfunc_cntl & 0x04, dev->h_disp, dev->dispend, dev->pitch, dev->rowoffset, mach->accel.ext_ge_config & 0xcec0, mach->shadow_set & 3, dev->interlace);
svga->map8 = dev->pallook;
svga->render8514 = ibm8514_render_8bpp;
}
}
if (!svga->scrblank && (svga->crtc[0x17] & 0x80) && svga->attr_palette_enable) {
if (((svga->gdcreg[6] & 1) || (svga->attrregs[0x10] & 1))) {
svga->clock = (cpuclock * (double) (1ULL << 32)) / svga->getclock(clock_sel, svga->clock_gen);
mach_log("VGA clock=%02x.\n", mach->regs[0xa7] & 0x80);
if ((dev->local & 0xff) >= 0x02) {
if (mach->regs[0xb8] & 0x40)
svga->clock *= 2;
} else {
switch (mach->regs[0xb8] & 0xc0) {
case 0x40:
svga->clock *= 2;
break;
case 0x80:
svga->clock *= 3;
break;
case 0xc0:
svga->clock *= 4;
break;
default:
break;
}
}
switch (svga->gdcreg[5] & 0x60) {
case 0x00:
if (svga->seqregs[1] & 8) /*Low res (320)*/
svga->render = svga_render_4bpp_lowres;
else
svga->render = svga_render_4bpp_highres;
break;
case 0x20: /*4 colours*/
if (svga->seqregs[1] & 8) /*Low res (320)*/
svga->render = svga_render_2bpp_lowres;
else
svga->render = svga_render_2bpp_highres;
break;
case 0x40:
case 0x60: /*256+ colours*/
switch (svga->bpp) {
default:
case 8:
svga->map8 = svga->pallook;
mach_log("Lowres=%x, seqreg[1]bit3=%x.\n", svga->lowres, svga->seqregs[1] & 8);
if (svga->lowres)
svga->render = svga_render_8bpp_lowres;
else {
svga->render = svga_render_8bpp_highres;
if (!svga->packed_4bpp) {
svga->ma_latch <<= 1;
svga->rowoffset <<= 1;
}
}
break;
}
break;
default:
break;
}
}
}
}
static void
mach_accel_out_fifo(mach_t *mach, svga_t *svga, ibm8514_t *dev, uint16_t port, uint16_t val, int len)
{
int frgd_sel;
int bkgd_sel;
int mono_src;
mach_log("[%04X:%08X]: Port FIFO OUT=%04x, val=%04x, len=%d.\n", CS, cpu_state.pc, port, val, len);
switch (port) {
case 0x82e8:
case 0x82e9:
case 0x86e8:
case 0x86e9:
case 0xc2e8:
case 0xc2e9:
case 0xc6e8:
case 0xc6e9:
ibm8514_accel_out_fifo(svga, port, val, len);
break;
case 0xf6ee:
ibm8514_accel_out_fifo(svga, 0x82e8, val, len);
break;
case 0xf6ef:
ibm8514_accel_out_fifo(svga, 0x82e9, val, len);
break;
case 0x8ae8:
case 0xcae8:
ibm8514_accel_out_fifo(svga, port, val, len);
if (len != 1)
mach->accel.src_y = val;
break;
case 0x8ae9:
case 0x8ee9:
case 0xcae9:
case 0xcee9:
ibm8514_accel_out_fifo(svga, port, val, len);
break;
case 0x8ee8:
case 0xcee8:
ibm8514_accel_out_fifo(svga, port, val, len);
if (len != 1)
mach->accel.src_x = val;
break;
case 0x92e8:
case 0x92e9:
case 0x96e9:
case 0xd2e8:
case 0xd2e9:
case 0xd6e9:
ibm8514_accel_out_fifo(svga, port, val, len);
break;
case 0x96e8:
case 0xd6e8:
ibm8514_accel_out_fifo(svga, port, val, len);
if (len != 1)
mach->accel.test = val & 0x1fff;
break;
case 0x9ae8:
case 0xdae8:
dev->accel.ssv_state = 0;
if (len == 1)
dev->accel.cmd = (dev->accel.cmd & 0xff00) | val;
else {
dev->data_available = 0;
dev->data_available2 = 0;
dev->accel.cmd = val;
mach_log("CMD8514=%04x, len=%d, pixcntl=%02x.\n", val, len, dev->accel.multifunc[0x0a]);
mach->accel.cmd_type = -1;
if (port == 0xdae8) {
if (dev->accel.cmd & 0x100)
dev->accel.cmd_back = 0;
}
ibm8514_accel_start(-1, 0, -1, 0, svga, len);
}
break;
case 0x9ae9:
case 0xdae9:
if (len == 1) {
dev->data_available = 0;
dev->data_available2 = 0;
dev->accel.cmd = (dev->accel.cmd & 0xff) | (val << 8);
mach->accel.cmd_type = -1;
if (port == 0xdae9) {
if (dev->accel.cmd & 0x100)
dev->accel.cmd_back = 0;
}
ibm8514_accel_start(-1, 0, -1, 0, svga, len);
}
break;
case 0x9ee8:
case 0xdee8:
dev->accel.ssv_state = 1;
if (len == 1)
dev->accel.short_stroke = (dev->accel.short_stroke & 0xff00) | val;
else {
dev->accel.short_stroke = val;
dev->accel.cx = dev->accel.cur_x;
dev->accel.cy = dev->accel.cur_y;
if (dev->accel.cur_x >= 0x600)
dev->accel.cx |= ~0x5ff;
if (dev->accel.cur_y >= 0x600)
dev->accel.cy |= ~0x5ff;
if (dev->accel.cmd & 0x1000) {
ibm8514_short_stroke_start(-1, 0, -1, 0, svga, dev->accel.short_stroke & 0xff, len);
ibm8514_short_stroke_start(-1, 0, -1, 0, svga, dev->accel.short_stroke >> 8, len);
} else {
ibm8514_short_stroke_start(-1, 0, -1, 0, svga, dev->accel.short_stroke >> 8, len);
ibm8514_short_stroke_start(-1, 0, -1, 0, svga, dev->accel.short_stroke & 0xff, len);
}
}
break;
case 0x9ee9:
case 0xdee9:
if (len == 1) {
dev->accel.short_stroke = (dev->accel.short_stroke & 0xff) | (val << 8);
dev->accel.cx = dev->accel.cur_x;
dev->accel.cy = dev->accel.cur_y;
if (dev->accel.cur_x >= 0x600) {
dev->accel.cx |= ~0x5ff;
}
if (dev->accel.cur_y >= 0x600) {
dev->accel.cy |= ~0x5ff;
}
if (dev->accel.cmd & 0x1000) {
ibm8514_short_stroke_start(-1, 0, -1, 0, svga, dev->accel.short_stroke & 0xff, len);
ibm8514_short_stroke_start(-1, 0, -1, 0, svga, dev->accel.short_stroke >> 8, len);
} else {
ibm8514_short_stroke_start(-1, 0, -1, 0, svga, dev->accel.short_stroke >> 8, len);
ibm8514_short_stroke_start(-1, 0, -1, 0, svga, dev->accel.short_stroke & 0xff, len);
}
}
break;
case 0xa2e8:
case 0xe2e8:
if (port == 0xe2e8) {
if (dev->accel.cmd_back) {
if (len == 1)
dev->accel.bkgd_color = (dev->accel.bkgd_color & 0x00ff) | val;
else
dev->accel.bkgd_color = val;
} else {
if (len == 1) {
if (mach->accel.cmd_type >= 0) {
if (mach_pixel_read(mach))
break;
mach->accel.pix_trans[1] = val;
}
} else {
if (mach->accel.cmd_type >= 0) {
if (mach_pixel_read(mach))
break;
mach_accel_out_pixtrans(mach, dev, val);
} else {
if (ibm8514_cpu_dest(svga))
break;
ibm8514_accel_out_pixtrans(svga, port, val, len);
}
}
}
} else {
if (len == 1)
dev->accel.bkgd_color = (dev->accel.bkgd_color & 0x00ff) | val;
else
dev->accel.bkgd_color = val;
}
break;
case 0xa2e9:
case 0xe2e9:
if (port == 0xe2e9) {
if (dev->accel.cmd_back) {
if (len == 1)
dev->accel.bkgd_color = (dev->accel.bkgd_color & 0xff00) | (val << 8);
} else {
if (len == 1) {
if (mach->accel.cmd_type >= 0) {
if (mach_pixel_read(mach))
break;
mach->accel.pix_trans[0] = val;
frgd_sel = (mach->accel.dp_config >> 13) & 7;
bkgd_sel = (mach->accel.dp_config >> 7) & 3;
mono_src = (mach->accel.dp_config >> 5) & 3;
switch (mach->accel.dp_config & 0x200) {
case 0x000: /*8-bit size*/
if (mono_src == 2) {
if ((frgd_sel != 2) && (bkgd_sel != 2)) {
mach_accel_start(mach->accel.cmd_type, 1, 8, mach->accel.pix_trans[0] | (mach->accel.pix_trans[1] << 8), 0, mach, dev);
} else
mach_accel_start(mach->accel.cmd_type, 1, 1, -1, mach->accel.pix_trans[0] | (mach->accel.pix_trans[1] << 8), mach, dev);
} else
mach_accel_start(mach->accel.cmd_type, 1, 1, -1, mach->accel.pix_trans[0] | (mach->accel.pix_trans[1] << 8), mach, dev);
break;
case 0x200: /*16-bit size*/
if (mono_src == 2) {
if ((frgd_sel != 2) && (bkgd_sel != 2)) {
if (mach->accel.dp_config & 0x1000)
mach_accel_start(mach->accel.cmd_type, 1, 16, mach->accel.pix_trans[1] | (mach->accel.pix_trans[0] << 8), 0, mach, dev);
else
mach_accel_start(mach->accel.cmd_type, 1, 16, mach->accel.pix_trans[0] | (mach->accel.pix_trans[1] << 8), 0, mach, dev);
} else
mach_accel_start(mach->accel.cmd_type, 1, 2, -1, mach->accel.pix_trans[0] | (mach->accel.pix_trans[1] << 8), mach, dev);
} else
mach_accel_start(mach->accel.cmd_type, 1, 2, -1, mach->accel.pix_trans[0] | (mach->accel.pix_trans[1] << 8), mach, dev);
break;
default:
break;
}
}
}
}
} else {
if (len == 1)
dev->accel.bkgd_color = (dev->accel.bkgd_color & 0xff00) | (val << 8);
}
break;
case 0xa6e8:
case 0xe6e8:
if (port == 0xe6e8) {
if (dev->accel.cmd_back) {
if (len == 1)
dev->accel.frgd_color = (dev->accel.frgd_color & 0x00ff) | val;
else
dev->accel.frgd_color = val;
} else {
if (len == 1) {
if (mach->accel.cmd_type >= 0) {
if (mach_pixel_read(mach))
break;
mach->accel.pix_trans[1] = val;
}
} else {
if (mach->accel.cmd_type >= 0) {
if (mach_pixel_read(mach))
break;
mach_accel_out_pixtrans(mach, dev, val);
} else {
if (ibm8514_cpu_dest(svga))
break;
ibm8514_accel_out_pixtrans(svga, port, val, len);
}
}
}
} else {
if (len == 1)
dev->accel.frgd_color = (dev->accel.frgd_color & 0x00ff) | val;
else
dev->accel.frgd_color = val;
}
break;
case 0xa6e9:
case 0xe6e9:
if (port == 0xe6e9) {
if (dev->accel.cmd_back) {
if (len == 1)
dev->accel.frgd_color = (dev->accel.frgd_color & 0xff00) | (val << 8);
} else {
if (len == 1) {
if (mach->accel.cmd_type >= 0) {
if (mach_pixel_read(mach))
break;
mach->accel.pix_trans[0] = val;
frgd_sel = (mach->accel.dp_config >> 13) & 7;
bkgd_sel = (mach->accel.dp_config >> 7) & 3;
mono_src = (mach->accel.dp_config >> 5) & 3;
switch (mach->accel.dp_config & 0x200) {
case 0x000: /*8-bit size*/
if (mono_src == 2) {
if ((frgd_sel != 2) && (bkgd_sel != 2)) {
mach_accel_start(mach->accel.cmd_type, 1, 8, mach->accel.pix_trans[0] | (mach->accel.pix_trans[1] << 8), 0, mach, dev);
} else
mach_accel_start(mach->accel.cmd_type, 1, 1, -1, mach->accel.pix_trans[0] | (mach->accel.pix_trans[1] << 8), mach, dev);
} else
mach_accel_start(mach->accel.cmd_type, 1, 1, -1, mach->accel.pix_trans[0] | (mach->accel.pix_trans[1] << 8), mach, dev);
break;
case 0x200: /*16-bit size*/
if (mono_src == 2) {
if ((frgd_sel != 2) && (bkgd_sel != 2)) {
if (mach->accel.dp_config & 0x1000)
mach_accel_start(mach->accel.cmd_type, 1, 16, mach->accel.pix_trans[1] | (mach->accel.pix_trans[0] << 8), 0, mach, dev);
else
mach_accel_start(mach->accel.cmd_type, 1, 16, mach->accel.pix_trans[0] | (mach->accel.pix_trans[1] << 8), 0, mach, dev);
} else
mach_accel_start(mach->accel.cmd_type, 1, 2, -1, mach->accel.pix_trans[0] | (mach->accel.pix_trans[1] << 8), mach, dev);
} else
mach_accel_start(mach->accel.cmd_type, 1, 2, -1, mach->accel.pix_trans[0] | (mach->accel.pix_trans[1] << 8), mach, dev);
break;
default:
break;
}
}
}
}
} else {
if (len == 1)
dev->accel.frgd_color = (dev->accel.frgd_color & 0xff00) | (val << 8);
}
break;
case 0xaae8:
case 0xaae9:
case 0xaee8:
case 0xaee9:
case 0xb2e8:
case 0xb2e9:
case 0xb6e8:
case 0xbae8:
case 0xeae8:
case 0xeae9:
case 0xeee8:
case 0xeee9:
case 0xf2e8:
case 0xf2e9:
case 0xf6e8:
case 0xfae8:
ibm8514_accel_out_fifo(svga, port, val, len);
break;
case 0xbee8:
case 0xfee8:
if (len == 1)
dev->accel.multifunc_cntl = (dev->accel.multifunc_cntl & 0xff00) | val;
else {
dev->accel.multifunc_cntl = val;
dev->accel.multifunc[dev->accel.multifunc_cntl >> 12] = dev->accel.multifunc_cntl & 0xfff;
if ((dev->accel.multifunc_cntl >> 12) == 1)
dev->accel.clip_top = val & 0x7ff;
if ((dev->accel.multifunc_cntl >> 12) == 2)
dev->accel.clip_left = val & 0x7ff;
if ((dev->accel.multifunc_cntl >> 12) == 3)
dev->accel.multifunc[3] = val & 0x7ff;
if ((dev->accel.multifunc_cntl >> 12) == 4)
dev->accel.multifunc[4] = val & 0x7ff;
mach_log("CLIPBOTTOM=%d, CLIPRIGHT=%d, bpp=%d, pitch=%d.\n", dev->accel.multifunc[3], dev->accel.multifunc[4], dev->accel_bpp, dev->pitch);
if ((dev->accel.multifunc_cntl >> 12) == 5) {
if ((dev->local & 0xff) < 0x02)
dev->ext_crt_pitch = 128;
}
if (port == 0xfee8)
dev->accel.cmd_back = 1;
else
dev->accel.cmd_back = 0;
}
break;
case 0xbee9:
case 0xfee9:
if (len == 1) {
dev->accel.multifunc_cntl = (dev->accel.multifunc_cntl & 0xff) | (val << 8);
dev->accel.multifunc[dev->accel.multifunc_cntl >> 12] = dev->accel.multifunc_cntl & 0xfff;
if ((dev->accel.multifunc_cntl >> 12) == 1)
dev->accel.clip_top = dev->accel.multifunc_cntl & 0x7ff;
if ((dev->accel.multifunc_cntl >> 12) == 2)
dev->accel.clip_left = dev->accel.multifunc_cntl & 0x7ff;
if ((dev->accel.multifunc_cntl >> 12) == 5) {
if ((dev->local & 0xff) < 0x02)
dev->ext_crt_pitch = 128;
}
if (port == 0xfee9)
dev->accel.cmd_back = 1;
else
dev->accel.cmd_back = 0;
}
break;
/*ATI Mach8/32 specific registers*/
case 0x82ee:
mach->accel.patt_data_idx = val & 0x1f;
mach_log("Pattern Data Index = %d.\n", val & 0x1f);
break;
case 0x8eee:
if (len == 1)
mach->accel.patt_data[mach->accel.patt_data_idx] = val;
else {
mach->accel.patt_data[mach->accel.patt_data_idx] = val & 0xff;
mach->accel.patt_data[mach->accel.patt_data_idx + 1] = (val >> 8) & 0xff;
if (mach->accel.mono_pattern_enable)
mach->accel.patt_data_idx = (mach->accel.patt_data_idx + 2) & 0x17;
else {
frgd_sel = (mach->accel.dp_config >> 13) & 7;
mono_src = (mach->accel.dp_config >> 5) & 3;
if ((dev->accel_bpp == 24) && (mach->accel.patt_len == 0x17) && (frgd_sel == 5)) {
mach->accel.patt_data_idx += 2;
dev->accel.y1 = 1;
} else {
if (dev->accel_bpp == 24)
mach->accel.patt_data_idx += 2;
else
mach->accel.patt_data_idx = (mach->accel.patt_data_idx + 2) & mach->accel.patt_len;
}
mach_log("ExtCONFIG = %04x, Pattern Mono = %04x, selidx = %d, dataidx = %d, bit 0 = %02x len = %d.\n", mach->accel.ext_ge_config, val, mach->accel.patt_idx, mach->accel.patt_data_idx, val & 1, mach->accel.patt_len);
}
}
break;
case 0x8eef:
if (len == 1) {
mach->accel.patt_data[mach->accel.patt_data_idx + 1] = val;
if (mach->accel.mono_pattern_enable)
mach->accel.patt_data_idx = (mach->accel.patt_data_idx + 2) & 7;
else {
frgd_sel = (mach->accel.dp_config >> 13) & 7;
if ((dev->accel_bpp == 24) && (mach->accel.patt_len == 0x17) && (frgd_sel == 5)) {
mach->accel.patt_data_idx += 2;
dev->accel.y1 = 1;
} else
mach->accel.patt_data_idx = (mach->accel.patt_data_idx + 2) & mach->accel.patt_len;
}
}
break;
case 0x96ee:
if (len == 1)
mach->accel.bres_count = (mach->accel.bres_count & 0x700) | val;
else {
mach->accel.bres_count = val & 0x7ff;
mach_log("BresenhamDraw = %04x.\n", mach->accel.dp_config);
dev->data_available = 0;
dev->data_available2 = 0;
mach->accel.cmd_type = 1;
mach_accel_start(mach->accel.cmd_type, 0, -1, -1, 0, mach, dev);
}
break;
case 0x96ef:
if (len == 1) {
mach->accel.bres_count = (mach->accel.bres_count & 0xff) | ((val & 0x07) << 8);
mach_log("96EE (2) line draw.\n");
dev->data_available = 0;
dev->data_available2 = 0;
mach->accel.cmd_type = 1;
mach_accel_start(mach->accel.cmd_type, 0, -1, -1, 0, mach, dev);
}
break;
case 0x9aee:
mach->accel.line_idx = val & 0x07;
break;
case 0xa2ee:
mach_log("Line OPT = %04x\n", val);
if (len == 1)
mach->accel.linedraw_opt = (mach->accel.linedraw_opt & 0xff00) | val;
else {
mach->accel.linedraw_opt = val;
mach->accel.bbottom = dev->accel.multifunc[3] & 0x7ff;
mach->accel.btop = dev->accel.clip_top & 0x7ff;
mach->accel.bleft = dev->accel.clip_left & 0x7ff;
mach->accel.bright = dev->accel.multifunc[4] & 0x7ff;
if (mach->accel.linedraw_opt & 0x100) {
mach->accel.bbottom = 2047;
mach->accel.btop = 0;
mach->accel.bleft = 0;
mach->accel.bright = 2047;
}
}
break;
case 0xa2ef:
if (len == 1)
mach->accel.linedraw_opt = (mach->accel.linedraw_opt & 0x00ff) | (val << 8);
break;
case 0xa6ee:
if (len == 1)
mach->accel.dest_x_start = (mach->accel.dest_x_start & 0x700) | val;
else
mach->accel.dest_x_start = val & 0x7ff;
break;
case 0xa6ef:
if (len == 1)
mach->accel.dest_x_start = (mach->accel.dest_x_start & 0x0ff) | ((val & 0x07) << 8);
break;
case 0xaaee:
if (len == 1)
mach->accel.dest_x_end = (mach->accel.dest_x_end & 0x700) | val;
else
mach->accel.dest_x_end = val & 0x7ff;
break;
case 0xaaef:
if (len == 1)
mach->accel.dest_x_end = (mach->accel.dest_x_end & 0x0ff) | ((val & 0x07) << 8);
break;
case 0xaeee:
if (len == 1)
mach->accel.dest_y_end = (mach->accel.dest_y_end & 0x700) | val;
else {
mach->accel.dest_y_end = val & 0x7ff;
if ((val + 1) == 0x10000) {
mach_log("Dest_Y_end overflow val = %04x\n", val);
mach->accel.dest_y_end = 0;
}
dev->data_available = 0;
dev->data_available2 = 0;
mach_log("BitBLT = %04x.\n", mach->accel.dp_config);
mach->accel.cmd_type = 2; /*Non-conforming BitBLT from dest_y_end register (0xaeee)*/
mach_accel_start(mach->accel.cmd_type, 0, -1, -1, 0, mach, dev);
}
break;
case 0xaeef:
if (len == 1) {
mach->accel.dest_y_end = (mach->accel.dest_y_end & 0x0ff) | ((val & 0x07) << 8);
dev->data_available = 0;
dev->data_available2 = 0;
mach->accel.cmd_type = 2; /*Non-conforming BitBLT from dest_y_end register (0xaeee)*/
mach_accel_start(mach->accel.cmd_type, 0, -1, -1, 0, mach, dev);
}
break;
case 0xb2ee:
if (len == 1)
mach->accel.src_x_start = (mach->accel.src_x_start & 0x700) | val;
else
mach->accel.src_x_start = val & 0x7ff;
break;
case 0xb2ef:
if (len == 1)
mach->accel.src_x_start = (mach->accel.src_x_start & 0x0ff) | ((val & 0x07) << 8);
break;
case 0xb6ee:
dev->accel.bkgd_mix = val & 0xff;
break;
case 0xbaee:
dev->accel.frgd_mix = val & 0xff;
break;
case 0xbeee:
if (len == 1)
mach->accel.src_x_end = (mach->accel.src_x_end & 0x700) | val;
else
mach->accel.src_x_end = val & 0x7ff;
break;
case 0xbeef:
if (len == 1)
mach->accel.src_x_end = (mach->accel.src_x_end & 0x0ff) | ((val & 0x07) << 8);
break;
case 0xc2ee:
mach->accel.src_y_dir = val & 1;
break;
case 0xc6ee:
mach->accel.cmd_type = 0;
mach_log("TODO: Short Stroke.\n");
break;
case 0xcaee:
if (len == 1)
mach->accel.scan_to_x = (mach->accel.scan_to_x & 0x700) | val;
else {
mach->accel.scan_to_x = (val & 0x7ff);
if ((val + 1) == 0x10000) {
mach_log("Scan_to_X overflow val = %04x\n", val);
mach->accel.scan_to_x = 0;
}
dev->data_available = 0;
dev->data_available2 = 0;
mach->accel.cmd_type = 5; /*Horizontal Raster Draw from scan_to_x register (0xcaee)*/
mach_log("ScanToX = %04x.\n", mach->accel.dp_config);
mach_accel_start(mach->accel.cmd_type, 0, -1, -1, 0, mach, dev);
}
break;
case 0xcaef:
if (len == 1) {
mach->accel.scan_to_x = (mach->accel.scan_to_x & 0x0ff) | ((val & 0x07) << 8);
dev->data_available = 0;
dev->data_available2 = 0;
mach->accel.cmd_type = 5; /*Horizontal Raster Draw from scan_to_x register (0xcaee)*/
mach_accel_start(mach->accel.cmd_type, 0, -1, -1, 0, mach, dev);
}
break;
case 0xceee:
mach_log("CEEE write val = %04x.\n", val);
if (len == 1)
mach->accel.dp_config = (mach->accel.dp_config & 0xff00) | val;
else {
dev->data_available = 0;
dev->data_available2 = 0;
mach->accel.dp_config = val;
}
break;
case 0xceef:
if (len == 1)
mach->accel.dp_config = (mach->accel.dp_config & 0x00ff) | (val << 8);
break;
case 0xd2ee:
mach->accel.patt_len = val & 0x1f;
mach_log("Pattern Length = %d, val = %04x.\n", val & 0x1f, val);
mach->accel.mono_pattern_enable = !!(val & 0x80);
if (len != 1)
mach->accel.patt_len_reg = val;
else
mach->accel.patt_len_reg = (mach->accel.patt_len_reg & 0xff00) | val;
break;
case 0xd2ef:
if (len == 1)
mach->accel.patt_len_reg = (mach->accel.patt_len_reg & 0x00ff) | (val << 8);
break;
case 0xd6ee:
mach->accel.patt_idx = val & 0x1f;
mach_log("Pattern Index = %d, val = %02x.\n", val & 0x1f, val);
break;
case 0xdaee:
mach_log("DAEE (extclipl) write val = %d\n", val);
if (len == 1)
dev->accel.clip_left = (dev->accel.clip_left & 0x700) | val;
else
dev->accel.clip_left = val & 0x7ff;
break;
case 0xdaef:
if (len == 1)
dev->accel.clip_left = (dev->accel.clip_left & 0x0ff) | ((val & 0x07) << 8);
break;
case 0xdeee:
mach_log("DEEE (extclipt) write val = %d\n", val);
if (len == 1)
dev->accel.clip_top = (dev->accel.clip_top & 0x700) | val;
else
dev->accel.clip_top = val & 0x7ff;
break;
case 0xdeef:
if (len == 1)
dev->accel.clip_top = (dev->accel.clip_top & 0x0ff) | ((val & 0x07) << 8);
break;
case 0xe2ee:
mach_log("E2EE (extclipr) write val = %d\n", val);
if (len == 1)
dev->accel.multifunc[4] = (dev->accel.multifunc[4] & 0x700) | val;
else
dev->accel.multifunc[4] = val & 0x7ff;
break;
case 0xe2ef:
if (len == 1)
dev->accel.multifunc[4] = (dev->accel.multifunc[4] & 0x0ff) | ((val & 0x07) << 8);
break;
case 0xe6ee:
mach_log("E6EE (extclipb) write val = %d\n", val);
if (len == 1)
dev->accel.multifunc[3] = (dev->accel.multifunc[3] & 0x700) | val;
else
dev->accel.multifunc[3] = val & 0x7ff;
break;
case 0xe6ef:
if (len == 1)
dev->accel.multifunc[3] = (dev->accel.multifunc[3] & 0x0ff) | ((val & 0x07) << 8);
break;
case 0xeeee:
if (len == 1)
mach->accel.dest_cmp_fn = (mach->accel.dest_cmp_fn & 0xff00) | val;
else
mach->accel.dest_cmp_fn = val;
break;
case 0xeeef:
if (len == 1)
mach->accel.dest_cmp_fn = (mach->accel.dest_cmp_fn & 0x00ff) | (val << 8);
break;
case 0xf2ee:
mach_log("F2EE.\n");
if (len == 1)
mach->accel.dst_clr_cmp_mask = (mach->accel.dst_clr_cmp_mask & 0xff00) | val;
else
mach->accel.dst_clr_cmp_mask = val;
break;
case 0xf2ef:
if (len == 1)
mach->accel.dst_clr_cmp_mask = (mach->accel.dst_clr_cmp_mask & 0x00ff) | (val << 8);
break;
case 0xfeee:
mach_log("LineDraw = %04x.\n", mach->accel.dp_config);
if (len != 1) {
mach->accel.line_array[mach->accel.line_idx] = val;
dev->accel.cur_x = mach->accel.line_array[(mach->accel.line_idx == 4) ? 4 : 0];
dev->accel.cur_y = mach->accel.line_array[(mach->accel.line_idx == 5) ? 5 : 1];
mach->accel.cx_end_line = mach->accel.line_array[2];
mach->accel.cy_end_line = mach->accel.line_array[3];
if ((mach->accel.line_idx == 3) || (mach->accel.line_idx == 5)) {
mach->accel.cmd_type = (mach->accel.line_idx == 5) ? 4 : 3;
mach_accel_start(mach->accel.cmd_type, 0, -1, -1, 0, mach, dev);
mach->accel.line_idx = (mach->accel.line_idx == 5) ? 4 : 2;
break;
}
mach->accel.line_idx++;
}
break;
default:
break;
}
}
static void
mach_accel_out_call(uint16_t port, uint8_t val, mach_t *mach, svga_t *svga, ibm8514_t *dev)
{
if (port != 0x7aee && port != 0x7aef && port != 0x42e8 && port != 0x42e9 && port != 0x46e8 && port != 0x46e9)
mach_log("[%04X:%08X]: Port CALL OUT=%04x, val=%02x.\n", CS, cpu_state.pc, port, val);
switch (port) {
case 0x2e8:
case 0x6e9:
case 0xae8:
case 0xee8:
case 0x12e8:
case 0x12e9:
case 0x1ae8:
case 0x1ae9:
case 0x1ee8:
case 0x1ee9:
case 0x22e8:
case 0x42e8:
case 0x42e9:
ibm8514_accel_out(port, val, svga, 2);
break;
case 0x6e8:
/*In preparation to switch from VGA to 8514/A mode*/
if (!dev->on[0] || !dev->on[1] || (mach->accel.clock_sel & 0x01)) {
dev->hdisped = val;
dev->hdisp = (dev->hdisped + 1) << 3;
}
mach_log("[%04X:%08X]: ATI 8514/A: (0x%04x): hdisp=0x%02x.\n", CS, cpu_state.pc, port, val);
svga_recalctimings(svga);
break;
case 0x16e8:
case 0x16e9:
/*In preparation to switch from VGA to 8514/A mode*/
if (!dev->on[0] || !dev->on[1] || (mach->accel.clock_sel & 0x01)) {
WRITE8(port, dev->v_disp, val);
dev->v_disp &= 0x1fff;
dev->vdisp = (dev->v_disp + 1) >> 1;
}
mach_log("ATI 8514/A: V_DISP write 16E8 = %d\n", dev->v_disp);
mach_log("ATI 8514/A: (0x%04x): vdisp=0x%02x.\n", port, val);
svga_recalctimings(svga);
break;
case 0x4ae8:
case 0x4ae9:
WRITE8(port, dev->accel.advfunc_cntl, val);
dev->on[port & 1] = dev->accel.advfunc_cntl & 0x01;
if ((dev->local & 0xff) < 0x02)
dev->ext_crt_pitch = 128;
vga_on = !dev->on[port & 1];
mach->ext_on[port & 1] = dev->on[port & 1];
mach32_updatemapping(mach, svga);
dev->vendor_mode[port & 1] = 0;
mach_log("[%04X:%08X]: ATI 8514/A: (0x%04x): ON=%d, shadow crt=%x, hdisp=%d, vdisp=%d.\n", CS, cpu_state.pc, port, dev->on[port & 1], dev->accel.advfunc_cntl & 0x04, dev->hdisp, dev->vdisp);
mach_log("IBM mode set %s resolution.\n", (dev->accel.advfunc_cntl & 0x04) ? "2: 1024x768" : "1: 640x480");
svga_recalctimings(svga);
break;
/*ATI Mach8/32 specific registers*/
case 0x2ee:
mach_log("2EE write val = %02x.\n", val);
break;
case 0x2ef:
mach_log("2EF write val = %02x.\n", val);
break;
case 0x6ee:
mach_log("6EE write val = %02x.\n", val);
break;
case 0x6ef:
mach_log("6EF write val = %02x.\n", val);
break;
case 0xaee:
case 0xaef:
WRITE8(port, mach->cursor_offset_lo_reg, val);
mach->cursor_offset_lo = mach->cursor_offset_lo_reg;
break;
case 0xeee:
case 0xeef:
WRITE8(port, mach->cursor_offset_hi_reg, val);
mach->cursor_offset_hi = mach->cursor_offset_hi_reg & 0x0f;
dev->hwcursor.addr = (mach->cursor_offset_lo | (mach->cursor_offset_hi << 16)) << 2;
dev->hwcursor.ena = !!(mach->cursor_offset_hi_reg & 0x8000);
break;
case 0x12ee:
case 0x12ef:
WRITE8(port, mach->cursor_x, val);
dev->hwcursor.x = mach->cursor_x & 0x7ff;
break;
case 0x16ee:
case 0x16ef:
WRITE8(port, mach->cursor_y, val);
dev->hwcursor.y = mach->cursor_y & 0xfff;
break;
case 0x1aee:
case 0x1aef:
WRITE8(port, mach->cursor_col_b, val);
mach->cursor_col_0 = mach->cursor_col_b & 0xff;
mach->cursor_col_1 = (mach->cursor_col_b >> 8) & 0xff;
break;
case 0x1eee:
case 0x1eef:
WRITE8(port, mach->cursor_vh_offset, val);
dev->hwcursor.xoff = mach->cursor_vh_offset & 0x3f;
dev->hwcursor.yoff = (mach->cursor_vh_offset >> 8) & 0x3f;
break;
case 0x22ee:
if (mach->pci_bus) {
mach->pci_cntl_reg = val;
mach32_updatemapping(mach, svga);
}
break;
case 0x26ee:
case 0x26ef:
WRITE8(port, mach->accel.crt_pitch, val);
dev->ext_crt_pitch = mach->accel.crt_pitch & 0xff;
if (dev->accel_bpp > 8) {
if (dev->accel_bpp == 24)
dev->ext_crt_pitch *= 3;
else if (dev->accel_bpp == 32)
dev->ext_crt_pitch <<= 2;
else
dev->ext_crt_pitch <<= 1;
}
mach_log("ATI 8514/A: (0x%04x) val=0x%02x.\n", port, val);
svga_recalctimings(svga);
break;
case 0x32ee:
case 0x32ef:
WRITE8(port, mach->local_cntl, val);
mach32_updatemapping(mach, svga);
break;
case 0x36ee:
case 0x36ef:
mach_log("ATI 8514/A: (0x%04x) val = %04x.\n", port, val);
WRITE8(port, mach->misc, val);
mach->misc &= 0xfff0;
break;
case 0x3aee:
case 0x3aef:
WRITE8(port, mach->cursor_col_0_rg, val);
mach->ext_cur_col_0_g = mach->cursor_col_0_rg & 0xff;
mach->ext_cur_col_0_r = (mach->cursor_col_0_rg >> 8) & 0xff;
break;
case 0x3eee:
case 0x3eef:
WRITE8(port, mach->cursor_col_1_rg, val);
mach->ext_cur_col_1_g = mach->cursor_col_1_rg & 0xff;
mach->ext_cur_col_1_r = (mach->cursor_col_1_rg >> 8) & 0xff;
break;
case 0x42ee:
case 0x42ef:
mach_log("ATI 8514/A: (0x%04x) val = %04x.\n", port, val);
WRITE8(port, mach->accel.test2, val);
break;
case 0x46ee:
case 0x46ef:
WRITE8(port, mach->shadow_cntl, val);
mach_log("ATI 8514/A: (0x%04x) val=%02x.\n", port, val);
break;
case 0x4aee:
case 0x4aef:
WRITE8(port, mach->accel.clock_sel, val);
dev->on[port & 1] = mach->accel.clock_sel & 0x01;
mach_log("ATI 8514/A: (0x%04x): ON=%d, val=%04x, hdisp=%d, vdisp=%d, val=0x%02x.\n", port, dev->on[port & 1], val, dev->hdisp, dev->vdisp, val & 0xfe);
mach_log("ATI mode set %s resolution.\n", (dev->accel.advfunc_cntl & 0x04) ? "2: 1024x768" : "1: 640x480");
mach->ext_on[port & 1] = dev->on[port & 1];
vga_on = !dev->on[port & 1];
dev->vendor_mode[port & 1] = 1;
svga_recalctimings(svga);
break;
case 0x52ee:
case 0x52ef:
mach_log("ATI 8514/A: (0x%04x) val=%04x.\n", port, val);
WRITE8(port, mach->accel.scratch0, val);
break;
case 0x56ee:
case 0x56ef:
mach_log("ATI 8514/A: (0x%04x) val=%04x.\n", port, val);
WRITE8(port, mach->accel.scratch1, val);
break;
case 0x5aee:
case 0x5aef:
WRITE8(port, mach->shadow_set, val);
mach_log("ATI 8514/A: (0x%04x) val=0x%02x.\n", port, val);
if ((mach->shadow_set & 0x03) == 0x00)
mach_log("Primary CRT register set.\n");
else if ((mach->shadow_set & 0x03) == 0x01)
mach_log("CRT Shadow Set 1: 640x480.\n");
else if ((mach->shadow_set & 0x03) == 0x02)
mach_log("CRT Shadow Set 2: 1024x768.\n");
break;
case 0x5eee:
case 0x5eef:
WRITE8(port, mach->memory_aperture, val);
mach_log("Memory Aperture = %04x.\n", mach->memory_aperture);
if (!mach->pci_bus)
mach->linear_base = (mach->memory_aperture & 0xff00) << 12;
mach32_updatemapping(mach, svga);
break;
case 0x62ee:
mach_log("62EE write val = %04x, len = %d.\n", val, len);
break;
case 0x66ee:
mach_log("66EE write val = %04x, len = %d.\n", val, len);
break;
case 0x6aee:
case 0x6aef:
WRITE8(port, mach->accel.max_waitstates, val);
break;
case 0x6eee:
case 0x6eef:
WRITE8(port, mach->accel.ge_offset_lo, val);
svga_recalctimings(svga);
break;
case 0x72ee:
case 0x72ef:
WRITE8(port, mach->accel.ge_offset_hi, val);
mach_log("ATI 8514/A: (0x%04x) val=0x%02x, geoffset=%04x.\n", port, val, dev->accel.ge_offset);
svga_recalctimings(svga);
break;
case 0x76ee:
case 0x76ef:
WRITE8(port, mach->accel.ge_pitch, val);
dev->ext_pitch = ((mach->accel.ge_pitch & 0xff) << 3);
mach_log("ATI 8514/A: (0x%04x) val=0x%02x, extpitch=%d.\n", port, val, dev->ext_pitch);
svga_recalctimings(svga);
break;
case 0x7aee:
case 0x7aef:
WRITE8(port, mach->accel.ext_ge_config, val);
if ((dev->local & 0xff) >= 0x02) {
if (mach->accel.crt_pitch & 0xff)
dev->ext_crt_pitch = mach->accel.crt_pitch & 0xff;
switch (mach->accel.ext_ge_config & 0x30) {
case 0:
case 0x10:
dev->bpp = 0;
break;
case 0x20:
dev->bpp = 1;
dev->ext_crt_pitch <<= 1;
break;
case 0x30:
dev->bpp = 0;
if (mach->accel.ext_ge_config & 0x200)
dev->ext_crt_pitch <<= 2;
else
dev->ext_crt_pitch *= 3;
break;
default:
break;
}
svga_set_ramdac_type(svga, !!(mach->accel.ext_ge_config & 0x4000));
dev->vendor_mode[port & 1] = 1;
mach32_updatemapping(mach, svga);
mach_log("ATI 8514/A: (0x%04x) val=%02x.\n", port, val);
svga_recalctimings(svga);
} else {
ati_eeprom_write(&mach->eeprom, !!(mach->accel.ext_ge_config & 0x4040), !!(mach->accel.ext_ge_config & 0x2020), !!(mach->accel.ext_ge_config & 0x1010));
}
break;
case 0x7eee:
case 0x7eef:
WRITE8(port, mach->accel.eeprom_control, val);
ati_eeprom_write(&mach->eeprom, !!(mach->accel.eeprom_control & 8), !!(mach->accel.eeprom_control & 2), !!(mach->accel.eeprom_control & 1));
mach_log("ATI 8514/A: (0x%04x) val = %04x.\n", port, val);
break;
default:
break;
}
}
static void
mach_accel_out(uint16_t port, uint8_t val, mach_t *mach)
{
svga_t *svga = &mach->svga;
mach_log("[%04X:%08X]: Port NORMAL OUT=%04x, val=%04x.\n", CS, cpu_state.pc, port, val);
mach_accel_out_call(port, val, mach, svga, (ibm8514_t *) svga->dev8514);
}
static uint16_t
mach_accel_in_fifo(mach_t *mach, svga_t *svga, ibm8514_t *dev, uint16_t port, int len)
{
const uint16_t *vram_w = (uint16_t *) dev->vram;
uint16_t temp = 0;
int cmd;
int frgd_sel;
int bkgd_sel;
int mono_src;
switch (port) {
case 0x82e8:
case 0x86e8:
case 0x92e8:
case 0x96e8:
case 0xc2e8:
case 0xc6e8:
temp = ibm8514_accel_in_fifo(svga, port, len);
break;
case 0x9ae8:
case 0xdae8:
if (len != 1) {
if (dev->force_busy)
temp |= 0x200; /*Hardware busy*/
dev->force_busy = 0;
if (dev->data_available) {
temp |= 0x100; /*Read Data available*/
if (mach->accel.cmd_type >= 0) {
switch (mach->accel.cmd_type) {
case 2:
if (dev->accel.sy >= mach->accel.height)
dev->data_available = 0;
break;
case 5:
if (dev->accel.sx >= mach->accel.width)
dev->data_available = 0;
break;
default:
if (dev->accel.sy < 0)
dev->data_available = 0;
break;
}
} else {
if (dev->accel.sy < 0)
dev->data_available = 0;
}
}
}
mach_log("[%04X:%08X]: 9AE8: Temp = %04x, len = %d\n\n", CS, cpu_state.pc, temp, len);
break;
case 0x9ae9:
case 0xdae9:
if (len == 1) {
if (dev->force_busy2)
temp |= 2; /*Hardware busy*/
dev->force_busy2 = 0;
if (dev->data_available2) {
temp |= 1; /*Read Data available*/
if (mach->accel.cmd_type >= 0) {
switch (mach->accel.cmd_type) {
case 2:
if (dev->accel.sy >= mach->accel.height)
dev->data_available2 = 0;
break;
case 5:
if (dev->accel.sx >= mach->accel.width)
dev->data_available2 = 0;
break;
default:
if (dev->accel.sy < 0)
dev->data_available2 = 0;
break;
}
} else {
if (dev->accel.sy < 0)
dev->data_available2 = 0;
}
}
}
mach_log("[%04X:%08X]: 9AE9: Temp = %04x, len = %d\n\n", CS, cpu_state.pc, temp, len);
break;
case 0xe2e8:
case 0xe6e8:
if (mach->accel.cmd_type >= 0) {
if (mach_pixel_read(mach)) {
cmd = -1;
if (len == 1) {
READ_PIXTRANS_BYTE_IO(dev->accel.dx, 1)
temp = mach->accel.pix_trans[1];
} else {
if (mach->accel.cmd_type == 3) {
READ_PIXTRANS_WORD(dev->accel.cx, 0)
} else {
READ_PIXTRANS_WORD(dev->accel.dx, 0)
}
mach_accel_out_pixtrans(mach, dev, temp);
}
}
} else {
if (ibm8514_cpu_dest(svga)) {
cmd = (dev->accel.cmd >> 13);
if (len != 1) {
READ_PIXTRANS_WORD(dev->accel.cx, 0)
if (dev->accel.input && !dev->accel.odd_in && !dev->accel.sx) {
temp &= ~0xff00;
temp |= (dev->vram[(dev->accel.newdest_in + dev->accel.cur_x) & dev->vram_mask] << 8);
}
if (dev->subsys_stat & 1) {
dev->force_busy = 1;
dev->data_available = 1;
}
}
ibm8514_accel_out_pixtrans(svga, port, temp, len);
}
}
break;
case 0xe2e9:
case 0xe6e9:
if (mach->accel.cmd_type >= 0) {
mach_log("%04x pixtrans read, len=%d.\n", port, len);
if (mach_pixel_read(mach)) {
if (len == 1) {
cmd = -1;
READ_PIXTRANS_BYTE_IO(dev->accel.dx, 0)
temp = mach->accel.pix_trans[0];
frgd_sel = (mach->accel.dp_config >> 13) & 7;
bkgd_sel = (mach->accel.dp_config >> 7) & 3;
mono_src = (mach->accel.dp_config >> 5) & 3;
switch (mach->accel.dp_config & 0x200) {
case 0x000: /*8-bit size*/
if (mono_src == 2) {
if ((frgd_sel != 2) && (bkgd_sel != 2)) {
mach_accel_start(mach->accel.cmd_type, 1, 8, mach->accel.pix_trans[0] | (mach->accel.pix_trans[1] << 8), 0, mach, dev);
} else
mach_accel_start(mach->accel.cmd_type, 1, 1, -1, mach->accel.pix_trans[0] | (mach->accel.pix_trans[1] << 8), mach, dev);
} else
mach_accel_start(mach->accel.cmd_type, 1, 1, -1, mach->accel.pix_trans[0] | (mach->accel.pix_trans[1] << 8), mach, dev);
break;
case 0x200: /*16-bit size*/
if (mono_src == 2) {
if ((frgd_sel != 2) && (bkgd_sel != 2)) {
if (mach->accel.dp_config & 0x1000)
mach_accel_start(mach->accel.cmd_type, 1, 16, mach->accel.pix_trans[1] | (mach->accel.pix_trans[0] << 8), 0, mach, dev);
else
mach_accel_start(mach->accel.cmd_type, 1, 16, mach->accel.pix_trans[0] | (mach->accel.pix_trans[1] << 8), 0, mach, dev);
} else
mach_accel_start(mach->accel.cmd_type, 1, 2, -1, mach->accel.pix_trans[0] | (mach->accel.pix_trans[1] << 8), mach, dev);
} else
mach_accel_start(mach->accel.cmd_type, 1, 2, -1, mach->accel.pix_trans[0] | (mach->accel.pix_trans[1] << 8), mach, dev);
break;
default:
break;
}
}
}
}
break;
case 0xbee8:
case 0xfee8:
if (len != 1) {
mach_log("Multifunc_cntl = %d.\n", dev->accel.multifunc_cntl >> 12);
switch ((dev->accel.multifunc_cntl >> 12) & 0x0f) {
case 0:
temp = dev->accel.multifunc[0];
break;
case 1:
temp = dev->accel.clip_top;
break;
case 2:
temp = dev->accel.clip_left;
break;
case 3:
temp = dev->accel.multifunc[3];
break;
case 4:
temp = dev->accel.multifunc[4];
break;
case 5:
temp = dev->accel.multifunc[5];
break;
case 8:
temp = dev->accel.multifunc[8];
break;
case 9:
temp = dev->accel.multifunc[9];
break;
case 0x0a:
temp = dev->accel.multifunc[0x0a];
break;
default:
break;
}
}
break;
case 0x82ee:
temp = mach->accel.patt_data_idx;
break;
case 0x86ee:
case 0x86ef:
temp = 0x0000;
break;
case 0x8eee:
if (len == 1)
temp = mach->accel.ext_ge_config & 0xff;
else
temp = mach->accel.ext_ge_config;
mach_log("ExtGE Read = %04x, len=%d.\n", temp, len);
break;
case 0x8eef:
if (len == 1)
temp = mach->accel.ext_ge_config >> 8;
break;
case 0x92ee:
if (len == 1)
temp = mach->accel.eeprom_control & 0xff;
else
temp = mach->accel.eeprom_control;
mach_log("EEPROM cntl read=%04x, len=%d.\n", temp, len);
break;
case 0x92ef:
if (len == 1)
temp = mach->accel.eeprom_control >> 8;
mach_log("EEPROM cntl read+1=%02x, len=%d.\n", temp, len);
break;
case 0x96ee:
if (len == 1)
temp = mach->accel.test & 0xff;
else
temp = mach->accel.test;
break;
case 0x96ef:
if (len == 1)
temp = mach->accel.test >> 8;
break;
case 0xa2ee:
if (len == 1)
temp = mach->accel.linedraw_opt & 0xff;
else
temp = mach->accel.linedraw_opt;
break;
case 0xa2ef:
if (len == 1)
temp = mach->accel.linedraw_opt >> 8;
break;
case 0xb2ee:
if (len == 1)
temp = dev->hdisped;
else {
temp = dev->hdisped & 0xff;
temp |= (dev->htotal << 8);
}
mach_log("B2EE read=%02x.\n", temp & 0xff);
break;
case 0xb2ef:
if (len == 1)
temp = dev->htotal;
break;
case 0xb6ee:
temp = dev->hsync_start;
break;
case 0xbaee:
temp = dev->hsync_width;
break;
case 0xc2ee:
if (len == 1)
temp = dev->v_total_reg & 0xff;
else {
temp = dev->v_total_reg;
mach_log("VTOTAL read=%d.\n", temp);
}
break;
case 0xc2ef:
if (len == 1)
temp = dev->v_total_reg >> 8;
break;
case 0xc6ee:
if (len == 1)
temp = dev->v_disp & 0xff;
else {
temp = dev->v_disp;
mach_log("VDISP read=%d.\n", temp);
}
break;
case 0xc6ef:
if (len == 1)
temp = dev->v_disp >> 8;
break;
case 0xcaee:
if (len == 1)
temp = dev->v_sync_start & 0xff;
else
temp = dev->v_sync_start;
break;
case 0xcaef:
if (len == 1)
temp = dev->v_sync_start >> 8;
break;
case 0xceee:
if (len == 1)
temp = dev->vc & 0xff;
else
temp = dev->vc & 0x7ff;
break;
case 0xceef:
if (len == 1)
temp = (dev->vc >> 8) & 7;
break;
case 0xdaee:
if (len != 1) {
temp = mach->accel.src_x;
if ((dev->local & 0xff) >= 0x02)
temp &= 0x7ff;
} else
temp = mach->accel.src_x & 0xff;
break;
case 0xdaef:
if (len == 1)
temp = mach->accel.src_x >> 8;
break;
case 0xdeee:
if (len != 1) {
temp = mach->accel.src_y;
if ((dev->local & 0xff) >= 0x02)
temp &= 0x7ff;
} else
temp = mach->accel.src_y & 0xff;
break;
case 0xdeef:
if (len == 1)
temp = mach->accel.src_y >> 8;
break;
case 0xfaee:
if (len != 1) {
if ((dev->local & 0xff) >= 0x02) {
if (mach->pci_bus)
temp = 0x0017;
else
temp = 0x22f7;
}
} else {
if ((dev->local & 0xff) >= 0x02) {
if (mach->pci_bus)
temp = 0x17;
else
temp = 0xf7;
}
}
break;
case 0xfaef:
if (len == 1) {
if ((dev->local & 0xff) >= 0x02) {
if (mach->pci_bus)
temp = 0x00;
else
temp = 0x22;
}
}
break;
default:
break;
}
mach_log("[%04X:%08X]: Port FIFO IN=%04x, temp=%04x, len=%d.\n", CS, cpu_state.pc, port, temp, len);
return temp;
}
static uint8_t
mach_accel_in_call(uint16_t port, mach_t *mach, svga_t *svga, ibm8514_t *dev)
{
uint8_t temp = 0;
uint16_t clip_b_ibm = dev->accel.multifunc[3];
uint16_t clip_r_ibm = dev->accel.multifunc[4];
int16_t clip_l = dev->accel.clip_left & 0x7ff;
int16_t clip_t = dev->accel.clip_top & 0x7ff;
int16_t clip_r = dev->accel.multifunc[4] & 0x7ff;
int16_t clip_b = dev->accel.multifunc[3] & 0x7ff;
int cmd = (dev->accel.cmd >> 13);
switch (port) {
case 0x2e8:
case 0x6e8:
case 0x22e8:
case 0x26e8:
case 0x26e9:
case 0x2ee8:
case 0x2ee9:
temp = ibm8514_accel_in(port, svga);
break;
case 0x42e8:
case 0x42e9:
if (dev->vc == dev->v_syncstart)
dev->subsys_stat |= 1;
if (mach->accel.cmd_type >= 0) {
if (((dev->accel.dx) >= clip_l) && ((dev->accel.dx) <= clip_r) && ((dev->accel.dy) >= clip_t) && ((dev->accel.dy) <= clip_b))
temp |= 2;
} else {
if (cmd == 6) {
if (((dev->accel.dx) >= dev->accel.clip_left) && ((dev->accel.dx) <= clip_r_ibm) && ((dev->accel.dy) >= dev->accel.clip_top) && ((dev->accel.dy) <= clip_b_ibm))
temp |= 2;
} else {
if (((dev->accel.cx) >= dev->accel.clip_left) && ((dev->accel.dx) <= clip_r_ibm) && ((dev->accel.cy) >= dev->accel.clip_top) && ((dev->accel.cy) <= clip_b_ibm))
temp |= 2;
}
}
if (!dev->force_busy)
temp |= 8;
if (port & 1)
temp = 0x80;
else {
temp |= (dev->subsys_stat | 0x80);
if (mach->accel.ext_ge_config & 0x08)
temp |= ((mach->accel.ext_ge_config & 0x07) << 4);
else
temp |= 0x20;
}
mach_log("0x%04x read: Subsystem Status=%02x.\n", port, temp);
break;
/*ATI Mach8/32 specific registers*/
case 0x12ee:
case 0x12ef:
READ8(port, mach->config1);
break;
case 0x16ee:
case 0x16ef:
READ8(port, mach->config2);
break;
case 0x1aee:
case 0x1aef:
temp = 0x00;
break;
case 0x22ee:
if (mach->pci_bus)
temp = mach->pci_cntl_reg;
break;
case 0x32ee:
case 0x32ef:
READ8(port, mach->local_cntl);
break;
case 0x36ee:
case 0x36ef:
READ8(port, mach->misc);
if (!(port & 1)) {
temp &= ~0x0c;
switch (mach->memory) {
case 1024:
temp |= 0x04;
break;
case 2048:
temp |= 0x08;
break;
case 4096:
temp |= 0x0c;
break;
default:
if ((dev->local & 0xff) < 0x02)
temp |= 0x04;
break;
}
}
break;
case 0x42ee:
case 0x42ef:
READ8(port, mach->accel.test2);
break;
case 0x46ee:
case 0x46ef:
READ8(port, mach->shadow_cntl);
break;
case 0x4aee:
case 0x4aef:
READ8(port, mach->accel.clock_sel);
break;
case 0x52ee:
case 0x52ef:
READ8(port, mach->accel.scratch0);
#ifdef ATI_8514_ULTRA
if (mach->mca_bus) {
if (!(port & 1)) {
if (svga->ext8514 != NULL)
temp = dev->pos_regs[4];
} else {
if (svga->ext8514 != NULL)
temp = dev->pos_regs[5];
}
} else {
if (svga->ext8514 != NULL) {
temp = ((dev->bios_addr >> 7) - 0x1000) >> 4;
if (port & 1) {
temp &= ~0x80;
temp |= 0x01;
}
} else
temp = 0x00;
}
#endif
break;
case 0x56ee:
case 0x56ef:
READ8(port, mach->accel.scratch1);
break;
case 0x5eee:
case 0x5eef:
if (mach->pci_bus)
mach->memory_aperture = (mach->memory_aperture & ~0xfff0) | ((mach->linear_base >> 20) << 4);
READ8(port, mach->memory_aperture);
break;
case 0x62ee:
temp = mach->accel.clip_overrun;
mach_log("ClipOverrun = %02x.\n", temp);
break;
case 0x62ef:
if (mach->force_busy)
temp |= 0x20;
mach->force_busy = 0;
if (ati_eeprom_read(&mach->eeprom))
temp |= 0x40;
mach_log("Mach busy temp=%02x.\n", temp);
break;
case 0x6aee:
case 0x6aef:
READ8(port, mach->accel.max_waitstates);
break;
case 0x72ee:
case 0x72ef:
READ8(port, (mach->accel.bleft));
break;
case 0x76ee:
case 0x76ef:
READ8(port, (mach->accel.btop));
break;
case 0x7aee:
case 0x7aef:
READ8(port, (mach->accel.bright));
break;
case 0x7eee:
case 0x7eef:
READ8(port, (mach->accel.bbottom));
break;
default:
break;
}
if (port != 0x62ee && port != 0x62ef && port != 0x42e8 && port != 0x42e9)
mach_log("[%04X:%08X]: Port NORMAL IN=%04x, temp=%04x.\n", CS, cpu_state.pc, port, temp);
return temp;
}
#ifdef ATI_8514_ULTRA
static void
ati8514_accel_out(uint16_t port, uint8_t val, svga_t *svga)
{
mach_log("[%04X:%08X]: Port NORMAL OUT=%04x, val=%04x.\n", CS, cpu_state.pc, port, val);
mach_accel_out_call(port, val, (mach_t *)svga->ext8514, svga, (ibm8514_t *) svga->dev8514);
}
static void
ati8514_accel_outb(uint16_t port, uint8_t val, void *priv)
{
svga_t *svga = (svga_t *)priv;
mach_t *mach = (mach_t *)svga->ext8514;
if (port & 0x8000)
mach_accel_out_fifo(mach, svga, (ibm8514_t *) svga->dev8514, port, val, 1);
else
ati8514_accel_out(port, val, svga);
}
static void
ati8514_accel_outw(uint16_t port, uint16_t val, void *priv)
{
svga_t *svga = (svga_t *)priv;
mach_t *mach = (mach_t *)svga->ext8514;
if (port & 0x8000)
mach_accel_out_fifo(mach, svga, (ibm8514_t *) svga->dev8514, port, val, 2);
else {
ati8514_accel_out(port, val, svga);
ati8514_accel_out(port + 1, (val >> 8), svga);
}
}
static void
ati8514_accel_outl(uint16_t port, uint32_t val, void *priv)
{
svga_t *svga = (svga_t *)priv;
mach_t *mach = (mach_t *)svga->ext8514;
if (port & 0x8000) {
mach_accel_out_fifo(mach, svga, (ibm8514_t *) svga->dev8514, port, val & 0xffff, 2);
mach_accel_out_fifo(mach, svga, (ibm8514_t *) svga->dev8514, port + 2, val >> 16, 2);
} else {
ati8514_accel_out(port, val, svga);
ati8514_accel_out(port + 1, (val >> 8), svga);
ati8514_accel_out(port + 2, (val >> 16), svga);
ati8514_accel_out(port + 3, (val >> 24), svga);
}
}
#endif
static void
mach_accel_outb(uint16_t port, uint8_t val, void *priv)
{
mach_t *mach = (mach_t *) priv;
svga_t *svga = &mach->svga;
if (port & 0x8000)
mach_accel_out_fifo(mach, svga, (ibm8514_t *) svga->dev8514, port, val, 1);
else
mach_accel_out(port, val, mach);
}
static void
mach_accel_outw(uint16_t port, uint16_t val, void *priv)
{
mach_t *mach = (mach_t *) priv;
svga_t *svga = &mach->svga;
if (port & 0x8000)
mach_accel_out_fifo(mach, svga, (ibm8514_t *) svga->dev8514, port, val, 2);
else {
mach_accel_out(port, val, mach);
mach_accel_out(port + 1, (val >> 8), mach);
}
}
static void
mach_accel_outl(uint16_t port, uint32_t val, void *priv)
{
mach_t *mach = (mach_t *) priv;
svga_t *svga = &mach->svga;
if (port & 0x8000) {
mach_accel_out_fifo(mach, svga, (ibm8514_t *) svga->dev8514, port, val & 0xffff, 2);
mach_accel_out_fifo(mach, svga, (ibm8514_t *) svga->dev8514, port + 2, val >> 16, 2);
} else {
mach_accel_out(port, val, mach);
mach_accel_out(port + 1, (val >> 8), mach);
mach_accel_out(port + 2, (val >> 16), mach);
mach_accel_out(port + 3, (val >> 24), mach);
}
}
#ifdef ATI_8514_ULTRA
static uint8_t
ati8514_accel_in(uint16_t port, svga_t *svga)
{
return mach_accel_in_call(port, (mach_t *) svga->ext8514, svga, (ibm8514_t *) svga->dev8514);
}
static uint8_t
ati8514_accel_inb(uint16_t port, void *priv)
{
svga_t *svga = (svga_t *)priv;
mach_t *mach = (mach_t *)svga->ext8514;
uint8_t temp;
if (port & 0x8000)
temp = mach_accel_in_fifo(mach, svga, (ibm8514_t *) svga->dev8514, port, 1);
else
temp = ati8514_accel_in(port, svga);
return temp;
}
static uint16_t
ati8514_accel_inw(uint16_t port, void *priv)
{
svga_t *svga = (svga_t *)priv;
mach_t *mach = (mach_t *)svga->ext8514;
uint16_t temp;
if (port & 0x8000)
temp = mach_accel_in_fifo(mach, svga, (ibm8514_t *) svga->dev8514, port, 2);
else {
temp = ati8514_accel_in(port, svga);
temp |= (ati8514_accel_in(port + 1, svga) << 8);
}
return temp;
}
static uint32_t
ati8514_accel_inl(uint16_t port, void *priv)
{
svga_t *svga = (svga_t *)priv;
mach_t *mach = (mach_t *)svga->ext8514;
uint32_t temp;
if (port & 0x8000) {
temp = mach_accel_in_fifo(mach, svga, (ibm8514_t *) svga->dev8514, port, 2);
temp = (mach_accel_in_fifo(mach, svga, (ibm8514_t *) svga->dev8514, port + 2, 2) << 16);
} else {
temp = ati8514_accel_in(port, svga);
temp |= (ati8514_accel_in(port + 1, svga) << 8);
temp |= (ati8514_accel_in(port + 2, svga) << 16);
temp |= (ati8514_accel_in(port + 3, svga) << 24);
}
return temp;
}
#endif
static uint8_t
mach_accel_in(uint16_t port, mach_t *mach)
{
svga_t *svga = &mach->svga;
return mach_accel_in_call(port, mach, svga, (ibm8514_t *) svga->dev8514);
}
static uint8_t
mach_accel_inb(uint16_t port, void *priv)
{
mach_t *mach = (mach_t *) priv;
svga_t *svga = &mach->svga;
uint8_t temp;
if (port & 0x8000)
temp = mach_accel_in_fifo(mach, svga, (ibm8514_t *) svga->dev8514, port, 1);
else
temp = mach_accel_in(port, mach);
return temp;
}
static uint16_t
mach_accel_inw(uint16_t port, void *priv)
{
mach_t *mach = (mach_t *) priv;
svga_t *svga = &mach->svga;
uint16_t temp;
if (port & 0x8000)
temp = mach_accel_in_fifo(mach, svga, (ibm8514_t *) svga->dev8514, port, 2);
else {
temp = mach_accel_in(port, mach);
temp |= (mach_accel_in(port + 1, mach) << 8);
}
return temp;
}
static uint32_t
mach_accel_inl(uint16_t port, void *priv)
{
mach_t *mach = (mach_t *) priv;
svga_t *svga = &mach->svga;
uint32_t temp;
if (port & 0x8000) {
temp = mach_accel_in_fifo(mach, svga, (ibm8514_t *) svga->dev8514, port, 2);
temp = (mach_accel_in_fifo(mach, svga, (ibm8514_t *) svga->dev8514, port + 2, 2) << 16);
} else {
temp = mach_accel_in(port, mach);
temp |= (mach_accel_in(port + 1, mach) << 8);
temp |= (mach_accel_in(port + 2, mach) << 16);
temp |= (mach_accel_in(port + 3, mach) << 24);
}
return temp;
}
static uint32_t
mach32_decode_addr(svga_t *svga, uint32_t addr, int write)
{
int memory_map_mode = (svga->gdcreg[6] >> 2) & 3;
addr &= 0x1ffff;
switch (memory_map_mode) {
case 0:
break;
case 1:
if (addr >= 0x10000)
return 0xffffffff;
break;
case 2:
addr -= 0x10000;
if (addr >= 0x8000)
return 0xffffffff;
break;
default:
case 3:
addr -= 0x18000;
if (addr >= 0x8000)
return 0xffffffff;
break;
}
if (memory_map_mode <= 1) {
if (write)
addr = (addr & svga->banked_mask) + svga->write_bank;
else
addr = (addr & svga->banked_mask) + svga->read_bank;
}
return addr;
}
static __inline void
mach32_write_common(uint32_t addr, uint8_t val, int linear, mach_t *mach, svga_t *svga)
{
ibm8514_t *dev = (ibm8514_t *) svga->dev8514;
int writemask2 = svga->writemask;
int reset_wm = 0;
latch8514_t vall;
uint8_t wm = svga->writemask;
uint8_t count;
uint8_t i;
cycles -= svga->monitor->mon_video_timing_write_b;
if (linear) {
addr &= svga->decode_mask;
if (addr >= dev->vram_size)
return;
addr &= dev->vram_mask;
dev->changedvram[addr >> 12] = svga->monitor->mon_changeframecount;
dev->vram[addr] = val;
return;
} else {
addr = mach32_decode_addr(svga, addr, 1);
if (addr == 0xffffffff)
return;
}
if (!(svga->gdcreg[6] & 1))
svga->fullchange = 2;
if (((svga->chain4 && (svga->packed_chain4 || svga->force_old_addr)) || svga->fb_only) && (svga->writemode < 4)) {
writemask2 = 1 << (addr & 3);
addr &= ~3;
} else if (svga->chain4 && (svga->writemode < 4)) {
writemask2 = 1 << (addr & 3);
addr &= ~3;
addr = ((addr & 0xfffc) << 2) | ((addr & 0x30000) >> 14) | (addr & ~0x3ffff);
} else if (svga->chain2_write) {
writemask2 &= ~0xa;
if (addr & 1)
writemask2 <<= 1;
addr &= ~1;
addr &= dev->vram_mask;
} else {
writemask2 = 1 << (addr & 3);
addr &= ~3;
addr &= dev->vram_mask;
}
addr &= svga->decode_mask;
if (addr >= dev->vram_size)
return;
addr &= dev->vram_mask;
dev->changedvram[addr >> 12] = svga->monitor->mon_changeframecount;
count = 4;
switch (svga->writemode) {
case 0:
val = ((val >> (svga->gdcreg[3] & 7)) | (val << (8 - (svga->gdcreg[3] & 7))));
if ((svga->gdcreg[8] == 0xff) && !(svga->gdcreg[3] & 0x18) && (!svga->gdcreg[1] || svga->set_reset_disabled)) {
for (i = 0; i < count; i++) {
if (writemask2 & (1 << i))
dev->vram[addr | i] = val;
}
return;
} else {
for (i = 0; i < count; i++) {
if (svga->gdcreg[1] & (1 << i))
vall.b[i] = !!(svga->gdcreg[0] & (1 << i)) * 0xff;
else
vall.b[i] = val;
}
}
break;
case 1:
for (i = 0; i < count; i++) {
if (writemask2 & (1 << i))
dev->vram[addr | i] = dev->latch.b[i];
}
return;
case 2:
for (i = 0; i < count; i++)
vall.b[i] = !!(val & (1 << i)) * 0xff;
if (!(svga->gdcreg[3] & 0x18) && (!svga->gdcreg[1] || svga->set_reset_disabled)) {
for (i = 0; i < count; i++) {
if (writemask2 & (1 << i))
dev->vram[addr | i] = (vall.b[i] & svga->gdcreg[8]) | (dev->latch.b[i] & ~svga->gdcreg[8]);
}
return;
}
break;
case 3:
val = ((val >> (svga->gdcreg[3] & 7)) | (val << (8 - (svga->gdcreg[3] & 7))));
wm = svga->gdcreg[8];
svga->gdcreg[8] &= val;
for (i = 0; i < count; i++)
vall.b[i] = !!(svga->gdcreg[0] & (1 << i)) * 0xff;
reset_wm = 1;
break;
default:
break;
}
switch (svga->gdcreg[3] & 0x18) {
case 0x00: /* Set */
for (i = 0; i < count; i++) {
if (writemask2 & (1 << i))
dev->vram[addr | i] = (vall.b[i] & svga->gdcreg[8]) | (dev->latch.b[i] & ~svga->gdcreg[8]);
}
break;
case 0x08: /* AND */
for (i = 0; i < count; i++) {
if (writemask2 & (1 << i))
dev->vram[addr | i] = (vall.b[i] | ~svga->gdcreg[8]) & dev->latch.b[i];
}
break;
case 0x10: /* OR */
for (i = 0; i < count; i++) {
if (writemask2 & (1 << i))
dev->vram[addr | i] = (vall.b[i] & svga->gdcreg[8]) | dev->latch.b[i];
}
break;
case 0x18: /* XOR */
for (i = 0; i < count; i++) {
if (writemask2 & (1 << i))
dev->vram[addr | i] = (vall.b[i] & svga->gdcreg[8]) ^ dev->latch.b[i];
}
break;
default:
break;
}
if (reset_wm)
svga->gdcreg[8] = wm;
}
#ifdef ATI_8514_ULTRA
static void
ati8514_write(uint32_t addr, uint8_t val, void *priv)
{
svga_t *svga = (svga_t *) priv;
mach_t *mach = (mach_t *) svga->ext8514;
mach32_write_common(addr, val, 0, mach, svga);
}
static void
ati8514_writew(uint32_t addr, uint16_t val, void *priv)
{
svga_t *svga = (svga_t *) priv;
mach_t *mach = (mach_t *) svga->ext8514;
mach32_write_common(addr, val & 0xff, 0, mach, svga);
mach32_write_common(addr + 1, val >> 8, 0, mach, svga);
}
static void
ati8514_writel(uint32_t addr, uint32_t val, void *priv)
{
svga_t *svga = (svga_t *) priv;
mach_t *mach = (mach_t *) svga->ext8514;
mach32_write_common(addr, val & 0xff, 0, mach, svga);
mach32_write_common(addr + 1, val >> 8, 0, mach, svga);
mach32_write_common(addr + 2, val >> 16, 0, mach, svga);
mach32_write_common(addr + 3, val >> 24, 0, mach, svga);
}
#endif
static void
mach32_write(uint32_t addr, uint8_t val, void *priv)
{
mach_t *mach = (mach_t *) priv;
mach32_write_common(addr, val, 0, mach, &mach->svga);
}
static void
mach32_writew(uint32_t addr, uint16_t val, void *priv)
{
mach_t *mach = (mach_t *) priv;
mach32_write_common(addr, val & 0xff, 0, mach, &mach->svga);
mach32_write_common(addr + 1, val >> 8, 0, mach, &mach->svga);
}
static void
mach32_writel(uint32_t addr, uint32_t val, void *priv)
{
mach_t *mach = (mach_t *) priv;
mach32_write_common(addr, val & 0xff, 0, mach, &mach->svga);
mach32_write_common(addr + 1, val >> 8, 0, mach, &mach->svga);
mach32_write_common(addr + 2, val >> 16, 0, mach, &mach->svga);
mach32_write_common(addr + 3, val >> 24, 0, mach, &mach->svga);
}
static __inline void
mach32_writew_linear(uint32_t addr, uint16_t val, mach_t *mach)
{
svga_t *svga = &mach->svga;
ibm8514_t *dev = (ibm8514_t *) svga->dev8514;
cycles -= svga->monitor->mon_video_timing_write_w;
addr &= svga->decode_mask;
if (addr >= dev->vram_size)
return;
addr &= dev->vram_mask;
dev->changedvram[addr >> 12] = svga->monitor->mon_changeframecount;
*(uint16_t *) &dev->vram[addr] = val;
}
static __inline void
mach32_writel_linear(uint32_t addr, uint32_t val, mach_t *mach)
{
svga_t *svga = &mach->svga;
ibm8514_t *dev = (ibm8514_t *) svga->dev8514;
cycles -= svga->monitor->mon_video_timing_write_l;
addr &= svga->decode_mask;
if (addr >= dev->vram_size)
return;
addr &= dev->vram_mask;
dev->changedvram[addr >> 12] = svga->monitor->mon_changeframecount;
*(uint32_t *) &dev->vram[addr] = val;
}
static __inline uint8_t
mach32_read_common(uint32_t addr, int linear, mach_t *mach, svga_t *svga)
{
ibm8514_t *dev = (ibm8514_t *) svga->dev8514;
uint32_t latch_addr = 0;
int readplane = svga->readplane;
uint8_t count;
uint8_t temp;
uint8_t ret;
cycles -= svga->monitor->mon_video_timing_read_b;
if (linear) {
addr &= svga->decode_mask;
if (addr >= dev->vram_size)
return 0xff;
return dev->vram[addr & dev->vram_mask];
} else {
addr = mach32_decode_addr(svga, addr, 0);
if (addr == 0xffffffff)
return 0xff;
}
count = 2;
latch_addr = (addr << count) & svga->decode_mask;
count = (1 << count);
if ((svga->chain4 && (svga->packed_chain4 || svga->force_old_addr)) || svga->fb_only) {
addr &= svga->decode_mask;
if (addr >= dev->vram_size)
return 0xff;
latch_addr = (addr & dev->vram_mask) & ~3;
for (uint8_t i = 0; i < count; i++)
dev->latch.b[i] = dev->vram[latch_addr | i];
return dev->vram[addr & dev->vram_mask];
} else if (svga->chain4 && !svga->force_old_addr) {
readplane = addr & 3;
addr = ((addr & 0xfffc) << 2) | ((addr & 0x30000) >> 14) | (addr & ~0x3ffff);
} else if (svga->chain2_read) {
readplane = (readplane & 2) | (addr & 1);
addr &= ~1;
addr &= dev->vram_mask;
} else {
addr &= svga->decode_mask;
if (addr >= dev->vram_size)
return 0xff;
latch_addr = (addr & dev->vram_mask) & ~3;
for (uint8_t i = 0; i < count; i++)
dev->latch.b[i] = dev->vram[latch_addr | i];
return dev->vram[addr & dev->vram_mask];
}
addr &= svga->decode_mask;
/* standard VGA latched access */
if (latch_addr >= dev->vram_size) {
for (uint8_t i = 0; i < count; i++)
dev->latch.b[i] = 0xff;
} else {
latch_addr &= dev->vram_mask;
for (uint8_t i = 0; i < count; i++)
dev->latch.b[i] = dev->vram[latch_addr | i];
}
if (addr >= dev->vram_size)
return 0xff;
addr &= dev->vram_mask;
if (svga->readmode) {
temp = 0xff;
for (uint8_t pixel = 0; pixel < 8; pixel++) {
for (uint8_t plane = 0; plane < count; plane++) {
if (svga->colournocare & (1 << plane)) {
/* If we care about a plane, and the pixel has a mismatch on it, clear its bit. */
if (((dev->latch.b[plane] >> pixel) & 1) != ((svga->colourcompare >> plane) & 1))
temp &= ~(1 << pixel);
}
}
}
ret = temp;
} else
ret = dev->vram[addr | readplane];
return ret;
}
#ifdef ATI_8514_ULTRA
static uint8_t
ati8514_read(uint32_t addr, void *priv)
{
svga_t *svga = (svga_t *) priv;
mach_t *mach = (mach_t *) svga->ext8514;
uint8_t ret;
ret = mach32_read_common(addr, 0, mach, svga);
return ret;
}
static uint16_t
ati8514_readw(uint32_t addr, void *priv)
{
svga_t *svga = (svga_t *) priv;
mach_t *mach = (mach_t *) svga->ext8514;
uint16_t ret;
ret = mach32_read_common(addr, 0, mach, svga);
ret |= (mach32_read_common(addr + 1, 0, mach, svga) << 8);
return ret;
}
static uint32_t
ati8514_readl(uint32_t addr, void *priv)
{
svga_t *svga = (svga_t *) priv;
mach_t *mach = (mach_t *) svga->ext8514;
uint32_t ret;
ret = mach32_read_common(addr, 0, mach, svga);
ret |= (mach32_read_common(addr + 1, 0, mach, svga) << 8);
ret |= (mach32_read_common(addr + 2, 0, mach, svga) << 16);
ret |= (mach32_read_common(addr + 3, 0, mach, svga) << 24);
return ret;
}
#endif
static uint8_t
mach32_read(uint32_t addr, void *priv)
{
mach_t *mach = (mach_t *) priv;
uint8_t ret;
ret = mach32_read_common(addr, 0, mach, &mach->svga);
return ret;
}
static uint16_t
mach32_readw(uint32_t addr, void *priv)
{
mach_t *mach = (mach_t *) priv;
uint16_t ret;
ret = mach32_read_common(addr, 0, mach, &mach->svga);
ret |= (mach32_read_common(addr + 1, 0, mach, &mach->svga) << 8);
return ret;
}
static uint32_t
mach32_readl(uint32_t addr, void *priv)
{
mach_t *mach = (mach_t *) priv;
uint32_t ret;
ret = mach32_read_common(addr, 0, mach, &mach->svga);
ret |= (mach32_read_common(addr + 1, 0, mach, &mach->svga) << 8);
ret |= (mach32_read_common(addr + 2, 0, mach, &mach->svga) << 16);
ret |= (mach32_read_common(addr + 3, 0, mach, &mach->svga) << 24);
return ret;
}
static __inline uint16_t
mach32_readw_linear(uint32_t addr, mach_t *mach)
{
svga_t *svga = &mach->svga;
ibm8514_t *dev = (ibm8514_t *) svga->dev8514;
cycles -= svga->monitor->mon_video_timing_read_w;
addr &= svga->decode_mask;
if (addr >= dev->vram_size)
return 0xffff;
return *(uint16_t *) &dev->vram[addr & dev->vram_mask];
}
static __inline uint32_t
mach32_readl_linear(uint32_t addr, mach_t *mach)
{
svga_t *svga = &mach->svga;
ibm8514_t *dev = (ibm8514_t *) svga->dev8514;
cycles -= svga->monitor->mon_video_timing_read_l;
addr &= svga->decode_mask;
if (addr >= dev->vram_size)
return 0xffffffff;
return *(uint32_t *) &dev->vram[addr & dev->vram_mask];
}
static void
mach32_ap_writeb(uint32_t addr, uint8_t val, void *priv)
{
mach_t *mach = (mach_t *) priv;
svga_t *svga = &mach->svga;
const ibm8514_t *dev = (ibm8514_t *) svga->dev8514;
uint8_t port_dword = addr & 0xfc;
if (((mach->local_cntl & 0x20) || (mach->pci_cntl_reg & 0x80)) &&
((addr >= ((mach->ap_size << 20) - 0x200)) && (addr < (mach->ap_size << 20)))) {
if (addr & 0x100) {
mach_log("Port WORDB Write=%04x.\n", 0x02ee + (port_dword << 8));
mach_accel_outb(0x02ee + (addr & 1) + (port_dword << 8), val, mach);
} else {
mach_log("Port WORDB Write=%04x.\n", 0x02e8 + (port_dword << 8));
mach_accel_outb(0x02e8 + (addr & 1) + (port_dword << 8), val, mach);
}
} else {
mach_log("Linear WORDB Write=%08x, val=%02x.\n", addr, val);
if (dev->on[0] || dev->on[1])
mach32_write_common(addr, val, 1, mach, svga);
else
svga_write_linear(addr, val, svga);
}
}
static void
mach32_ap_writew(uint32_t addr, uint16_t val, void *priv)
{
mach_t *mach = (mach_t *) priv;
svga_t *svga = &mach->svga;
const ibm8514_t *dev = (ibm8514_t *) svga->dev8514;
uint8_t port_dword = addr & 0xfc;
if (((mach->local_cntl & 0x20) || (mach->pci_cntl_reg & 0x80)) &&
((addr >= ((mach->ap_size << 20) - 0x200)) && (addr < (mach->ap_size << 20)))) {
if (addr & 0x100) {
mach_log("Port WORDW Write=%04x.\n", 0x02ee + (port_dword << 8));
mach_accel_outw(0x02ee + (port_dword << 8), val, mach);
} else {
mach_log("Port WORDW Write=%04x.\n", 0x02e8 + (port_dword << 8));
mach_accel_outw(0x02e8 + (port_dword << 8), val, mach);
}
} else {
mach_log("Linear WORDW Write=%08x, val=%04x.\n", addr, val);
if (dev->on[0] || dev->on[1]) {
mach32_writew_linear(addr, val, mach);
} else
svga_writew_linear(addr, val, svga);
}
}
static void
mach32_ap_writel(uint32_t addr, uint32_t val, void *priv)
{
mach_t *mach = (mach_t *) priv;
svga_t *svga = &mach->svga;
const ibm8514_t *dev = (ibm8514_t *) svga->dev8514;
uint8_t port_dword = addr & 0xfc;
if (((mach->local_cntl & 0x20) || (mach->pci_cntl_reg & 0x80)) &&
((addr >= ((mach->ap_size << 20) - 0x200)) && (addr < (mach->ap_size << 20)))) {
if (addr & 0x100) {
mach_log("Port WORDL Write=%04x.\n", 0x02ee + (port_dword << 8));
mach_accel_outw(0x02ee + (port_dword << 8), val & 0xffff, mach);
mach_accel_outw(0x02ee + (port_dword << 8) + 4, val >> 16, mach);
} else {
mach_log("Port WORDL Write=%04x.\n", 0x02e8 + (port_dword << 8));
mach_accel_outw(0x02e8 + (port_dword << 8), val & 0xffff, mach);
mach_accel_outw(0x02e8 + (port_dword << 8) + 4, val >> 16, mach);
}
} else {
mach_log("Linear WORDL Write=%08x, val=%08x.\n", addr, val);
if (dev->on[0] || dev->on[1]) {
mach32_writel_linear(addr, val, mach);
} else
svga_writel_linear(addr, val, svga);
}
}
static uint8_t
mach32_ap_readb(uint32_t addr, void *priv)
{
mach_t *mach = (mach_t *) priv;
svga_t *svga = &mach->svga;
const ibm8514_t *dev = (ibm8514_t *) svga->dev8514;
uint8_t temp;
uint8_t port_dword = addr & 0xfc;
if (((mach->local_cntl & 0x20) || (mach->pci_cntl_reg & 0x80)) &&
((addr >= ((mach->ap_size << 20) - 0x200)) && (addr < (mach->ap_size << 20)))) {
if (addr & 0x100)
temp = mach_accel_inb(0x02ee + (addr & 1) + (port_dword << 8), mach);
else
temp = mach_accel_inb(0x02e8 + (addr & 1) + (port_dword << 8), mach);
} else {
if (dev->on[0] || dev->on[1])
temp = mach32_read_common(addr, 1, mach, svga);
else
temp = svga_read_linear(addr, svga);
mach_log("Linear WORDB Read=%08x, ret=%02x, fast=%d.\n", addr, temp, svga->fast);
}
return temp;
}
static uint16_t
mach32_ap_readw(uint32_t addr, void *priv)
{
mach_t *mach = (mach_t *) priv;
svga_t *svga = &mach->svga;
const ibm8514_t *dev = (ibm8514_t *) svga->dev8514;
uint16_t temp;
uint8_t port_dword = addr & 0xfc;
if (((mach->local_cntl & 0x20) || (mach->pci_cntl_reg & 0x80)) &&
((addr >= ((mach->ap_size << 20) - 0x200)) && (addr < (mach->ap_size << 20)))) {
if (addr & 0x100)
temp = mach_accel_inw(0x02ee + (port_dword << 8), mach);
else
temp = mach_accel_inw(0x02e8 + (port_dword << 8), mach);
} else {
if (dev->on[0] || dev->on[1]) {
temp = mach32_readw_linear(addr, mach);
} else
temp = svga_readw_linear(addr, svga);
mach_log("Linear WORDW Read=%08x, ret=%04x.\n", addr, temp);
}
return temp;
}
static uint32_t
mach32_ap_readl(uint32_t addr, void *priv)
{
mach_t *mach = (mach_t *) priv;
svga_t *svga = &mach->svga;
const ibm8514_t *dev = (ibm8514_t *) svga->dev8514;
uint32_t temp;
uint8_t port_dword = addr & 0xfc;
if (((mach->local_cntl & 0x20) || (mach->pci_cntl_reg & 0x80)) &&
((addr >= ((mach->ap_size << 20) - 0x200)) && (addr < (mach->ap_size << 20)))) {
if (addr & 0x100) {
temp = mach_accel_inw(0x02ee + (port_dword << 8), mach);
temp |= (mach_accel_inw(0x02ee + (port_dword << 8) + 4, mach) << 8);
} else {
temp = mach_accel_inw(0x02e8 + (port_dword << 8), mach);
temp |= (mach_accel_inw(0x02e8 + (port_dword << 8) + 4, mach) << 8);
}
} else {
if (dev->on[0] || dev->on[1]) {
temp = mach32_readl_linear(addr, mach);
} else
temp = svga_readl_linear(addr, svga);
mach_log("Linear WORDL Read=%08x, ret=%08x, ON0=%d, ON1=%d.\n", addr, temp, dev->on[0], dev->on[1]);
}
return temp;
}
static void
mach32_updatemapping(mach_t *mach, svga_t *svga)
{
ibm8514_t *dev = (ibm8514_t *) svga->dev8514;
if (mach->pci_bus && (!(mach->pci_regs[PCI_REG_COMMAND] & PCI_COMMAND_MEM))) {
mem_mapping_disable(&svga->mapping);
mem_mapping_disable(&mach->mmio_linear_mapping);
return;
}
if (mach->regs[0xbd] & 4) {
mem_mapping_set_addr(&svga->mapping, 0xa0000, 0x20000);
svga->banked_mask = 0xffff;
} else {
switch (svga->gdcreg[6] & 0x0c) {
case 0x0: /*128k at A0000*/
mem_mapping_set_addr(&svga->mapping, 0xa0000, 0x20000);
svga->banked_mask = 0xffff;
break;
case 0x4: /*64k at A0000*/
mem_mapping_set_addr(&svga->mapping, 0xa0000, 0x10000);
svga->banked_mask = 0xffff;
break;
case 0x8: /*32k at B0000*/
mem_mapping_set_addr(&svga->mapping, 0xb0000, 0x08000);
svga->banked_mask = 0x7fff;
break;
case 0xC: /*32k at B8000*/
mem_mapping_set_addr(&svga->mapping, 0xb8000, 0x08000);
svga->banked_mask = 0x7fff;
break;
default:
break;
}
}
mach_log("Linear base = %08x, aperture = %04x, localcntl = %02x svgagdc = %x.\n", mach->linear_base, mach->memory_aperture, mach->local_cntl, svga->gdcreg[6] & 0x0c);
if (mach->linear_base) {
if (((mach->memory_aperture & 3) == 1) && !mach->pci_bus) {
/*1 MB aperture*/
mach->ap_size = 1;
mem_mapping_set_addr(&mach->mmio_linear_mapping, mach->linear_base, mach->ap_size << 20);
} else {
/*4 MB aperture*/
mach->ap_size = 4;
mem_mapping_set_addr(&mach->mmio_linear_mapping, mach->linear_base, mach->ap_size << 20);
}
} else {
mach->ap_size = 4;
mem_mapping_disable(&mach->mmio_linear_mapping);
}
if ((dev->on[0] || dev->on[1]) && (mach->ext_on[0] || mach->ext_on[1]) && (dev->vendor_mode[0] || dev->vendor_mode[1])) {
mach_log("ExtON.\n");
#ifdef ATI_8514_ULTRA
if (svga->ext8514 != NULL) {
mem_mapping_set_handler(&svga->mapping, ati8514_read, ati8514_readw, ati8514_readl, ati8514_write, ati8514_writew, ati8514_writel);
mem_mapping_set_p(&svga->mapping, svga);
} else
#endif
{
mem_mapping_set_handler(&svga->mapping, mach32_read, mach32_readw, mach32_readl, mach32_write, mach32_writew, mach32_writel);
mem_mapping_set_p(&svga->mapping, mach);
}
} else {
mach_log("ExtOFF.\n");
mem_mapping_set_handler(&svga->mapping, svga_read, svga_readw, svga_readl, svga_write, svga_writew, svga_writel);
mem_mapping_set_p(&svga->mapping, svga);
}
}
static void
mach32_hwcursor_draw(svga_t *svga, int displine)
{
const mach_t *mach = (mach_t *) svga->priv;
ibm8514_t *dev = (ibm8514_t *) svga->dev8514;
uint16_t dat;
int comb;
int offset = dev->hwcursor_latch.x - dev->hwcursor_latch.xoff;
uint32_t color0;
uint32_t color1;
uint32_t *p;
int x_pos;
int y_pos;
mach_log("BPP=%d.\n", dev->accel_bpp);
switch (dev->accel_bpp) {
default:
case 8:
color0 = dev->pallook[mach->cursor_col_0];
color1 = dev->pallook[mach->cursor_col_1];
break;
case 15:
color0 = video_15to32[((mach->ext_cur_col_0_r << 16) | (mach->ext_cur_col_0_g << 8) | mach->cursor_col_0) & 0xffff];
color1 = video_15to32[((mach->ext_cur_col_1_r << 16) | (mach->ext_cur_col_1_g << 8) | mach->cursor_col_1) & 0xffff];
break;
case 16:
color0 = video_16to32[((mach->ext_cur_col_0_r << 16) | (mach->ext_cur_col_0_g << 8) | mach->cursor_col_0) & 0xffff];
color1 = video_16to32[((mach->ext_cur_col_1_r << 16) | (mach->ext_cur_col_1_g << 8) | mach->cursor_col_1) & 0xffff];
break;
case 24:
case 32:
color0 = ((mach->ext_cur_col_0_r << 16) | (mach->ext_cur_col_0_g << 8) | mach->cursor_col_0);
color1 = ((mach->ext_cur_col_1_r << 16) | (mach->ext_cur_col_1_g << 8) | mach->cursor_col_1);
break;
}
if (dev->interlace && dev->hwcursor_oddeven)
dev->hwcursor_latch.addr += 16;
for (int x = 0; x < 64; x += 8) {
dat = dev->vram[dev->hwcursor_latch.addr & dev->vram_mask] | (dev->vram[(dev->hwcursor_latch.addr + 1) & dev->vram_mask] << 8);
for (int xx = 0; xx < 8; xx++) {
comb = (dat >> (xx << 1)) & 0x03;
y_pos = displine;
x_pos = offset + svga->x_add;
p = buffer32->line[y_pos];
if (offset >= dev->hwcursor_latch.x) {
mach_log("COMB=%d.\n", comb);
switch (comb) {
case 0:
p[x_pos] = color0;
break;
case 1:
p[x_pos] = color1;
break;
case 3:
p[x_pos] ^= 0xffffff;
break;
default:
break;
}
}
offset++;
}
dev->hwcursor_latch.addr += 2;
}
if (dev->interlace && !dev->hwcursor_oddeven)
dev->hwcursor_latch.addr += 16;
}
#ifdef ATI_8514_ULTRA
static void
ati8514_io_set(svga_t *svga)
{
io_sethandler(0x2e8, 0x0002, ati8514_accel_inb, ati8514_accel_inw, ati8514_accel_inl, ati8514_accel_outb, ati8514_accel_outw, ati8514_accel_outl, svga);
io_sethandler(0x6e8, 0x0002, ati8514_accel_inb, ati8514_accel_inw, ati8514_accel_inl, ati8514_accel_outb, ati8514_accel_outw, ati8514_accel_outl, svga);
io_sethandler(0xae8, 0x0002, ati8514_accel_inb, ati8514_accel_inw, ati8514_accel_inl, ati8514_accel_outb, ati8514_accel_outw, ati8514_accel_outl, svga);
io_sethandler(0xee8, 0x0002, ati8514_accel_inb, ati8514_accel_inw, ati8514_accel_inl, ati8514_accel_outb, ati8514_accel_outw, ati8514_accel_outl, svga);
io_sethandler(0x12e8, 0x0002, ati8514_accel_inb, ati8514_accel_inw, ati8514_accel_inl, ati8514_accel_outb, ati8514_accel_outw, ati8514_accel_outl, svga);
io_sethandler(0x16e8, 0x0002, ati8514_accel_inb, ati8514_accel_inw, ati8514_accel_inl, ati8514_accel_outb, ati8514_accel_outw, ati8514_accel_outl, svga);
io_sethandler(0x1ae8, 0x0002, ati8514_accel_inb, ati8514_accel_inw, ati8514_accel_inl, ati8514_accel_outb, ati8514_accel_outw, ati8514_accel_outl, svga);
io_sethandler(0x1ee8, 0x0002, ati8514_accel_inb, ati8514_accel_inw, ati8514_accel_inl, ati8514_accel_outb, ati8514_accel_outw, ati8514_accel_outl, svga);
io_sethandler(0x22e8, 0x0002, ati8514_accel_inb, ati8514_accel_inw, ati8514_accel_inl, ati8514_accel_outb, ati8514_accel_outw, ati8514_accel_outl, svga);
io_sethandler(0x26e8, 0x0002, ati8514_accel_inb, ati8514_accel_inw, ati8514_accel_inl, ati8514_accel_outb, ati8514_accel_outw, ati8514_accel_outl, svga);
io_sethandler(0x2ee8, 0x0002, ati8514_accel_inb, ati8514_accel_inw, ati8514_accel_inl, ati8514_accel_outb, ati8514_accel_outw, ati8514_accel_outl, svga);
io_sethandler(0x42e8, 0x0002, ati8514_accel_inb, ati8514_accel_inw, ati8514_accel_inl, ati8514_accel_outb, ati8514_accel_outw, ati8514_accel_outl, svga);
io_sethandler(0x46e8, 0x0002, ati8514_accel_inb, ati8514_accel_inw, ati8514_accel_inl, ati8514_accel_outb, ati8514_accel_outw, ati8514_accel_outl, svga);
io_sethandler(0x4ae8, 0x0002, ati8514_accel_inb, ati8514_accel_inw, ati8514_accel_inl, ati8514_accel_outb, ati8514_accel_outw, ati8514_accel_outl, svga);
io_sethandler(0x52e8, 0x0002, ati8514_accel_inb, ati8514_accel_inw, ati8514_accel_inl, ati8514_accel_outb, ati8514_accel_outw, ati8514_accel_outl, svga);
io_sethandler(0x56e8, 0x0002, ati8514_accel_inb, ati8514_accel_inw, ati8514_accel_inl, ati8514_accel_outb, ati8514_accel_outw, ati8514_accel_outl, svga);
io_sethandler(0x5ae8, 0x0002, ati8514_accel_inb, ati8514_accel_inw, ati8514_accel_inl, ati8514_accel_outb, ati8514_accel_outw, ati8514_accel_outl, svga);
io_sethandler(0x5ee8, 0x0002, ati8514_accel_inb, ati8514_accel_inw, ati8514_accel_inl, ati8514_accel_outb, ati8514_accel_outw, ati8514_accel_outl, svga);
io_sethandler(0x82e8, 0x0002, ati8514_accel_inb, ati8514_accel_inw, ati8514_accel_inl, ati8514_accel_outb, ati8514_accel_outw, ati8514_accel_outl, svga);
io_sethandler(0x86e8, 0x0002, ati8514_accel_inb, ati8514_accel_inw, ati8514_accel_inl, ati8514_accel_outb, ati8514_accel_outw, ati8514_accel_outl, svga);
io_sethandler(0x8ae8, 0x0002, ati8514_accel_inb, ati8514_accel_inw, ati8514_accel_inl, ati8514_accel_outb, ati8514_accel_outw, ati8514_accel_outl, svga);
io_sethandler(0x8ee8, 0x0002, ati8514_accel_inb, ati8514_accel_inw, ati8514_accel_inl, ati8514_accel_outb, ati8514_accel_outw, ati8514_accel_outl, svga);
io_sethandler(0x92e8, 0x0002, ati8514_accel_inb, ati8514_accel_inw, ati8514_accel_inl, ati8514_accel_outb, ati8514_accel_outw, ati8514_accel_outl, svga);
io_sethandler(0x96e8, 0x0002, ati8514_accel_inb, ati8514_accel_inw, ati8514_accel_inl, ati8514_accel_outb, ati8514_accel_outw, ati8514_accel_outl, svga);
io_sethandler(0x9ae8, 0x0002, ati8514_accel_inb, ati8514_accel_inw, ati8514_accel_inl, ati8514_accel_outb, ati8514_accel_outw, ati8514_accel_outl, svga);
io_sethandler(0x9ee8, 0x0002, ati8514_accel_inb, ati8514_accel_inw, ati8514_accel_inl, ati8514_accel_outb, ati8514_accel_outw, ati8514_accel_outl, svga);
io_sethandler(0xa2e8, 0x0002, ati8514_accel_inb, ati8514_accel_inw, ati8514_accel_inl, ati8514_accel_outb, ati8514_accel_outw, ati8514_accel_outl, svga);
io_sethandler(0xa6e8, 0x0002, ati8514_accel_inb, ati8514_accel_inw, ati8514_accel_inl, ati8514_accel_outb, ati8514_accel_outw, ati8514_accel_outl, svga);
io_sethandler(0xaae8, 0x0002, ati8514_accel_inb, ati8514_accel_inw, ati8514_accel_inl, ati8514_accel_outb, ati8514_accel_outw, ati8514_accel_outl, svga);
io_sethandler(0xaee8, 0x0002, ati8514_accel_inb, ati8514_accel_inw, ati8514_accel_inl, ati8514_accel_outb, ati8514_accel_outw, ati8514_accel_outl, svga);
io_sethandler(0xb2e8, 0x0002, ati8514_accel_inb, ati8514_accel_inw, ati8514_accel_inl, ati8514_accel_outb, ati8514_accel_outw, ati8514_accel_outl, svga);
io_sethandler(0xb6e8, 0x0002, ati8514_accel_inb, ati8514_accel_inw, ati8514_accel_inl, ati8514_accel_outb, ati8514_accel_outw, ati8514_accel_outl, svga);
io_sethandler(0xbae8, 0x0002, ati8514_accel_inb, ati8514_accel_inw, ati8514_accel_inl, ati8514_accel_outb, ati8514_accel_outw, ati8514_accel_outl, svga);
io_sethandler(0xbee8, 0x0002, ati8514_accel_inb, ati8514_accel_inw, ati8514_accel_inl, ati8514_accel_outb, ati8514_accel_outw, ati8514_accel_outl, svga);
io_sethandler(0xe2e8, 0x0002, ati8514_accel_inb, ati8514_accel_inw, ati8514_accel_inl, ati8514_accel_outb, ati8514_accel_outw, ati8514_accel_outl, svga);
io_sethandler(0xc2e8, 0x0002, ati8514_accel_inb, ati8514_accel_inw, ati8514_accel_inl, ati8514_accel_outb, ati8514_accel_outw, ati8514_accel_outl, svga);
io_sethandler(0xc6e8, 0x0002, ati8514_accel_inb, ati8514_accel_inw, ati8514_accel_inl, ati8514_accel_outb, ati8514_accel_outw, ati8514_accel_outl, svga);
io_sethandler(0xcae8, 0x0002, ati8514_accel_inb, ati8514_accel_inw, ati8514_accel_inl, ati8514_accel_outb, ati8514_accel_outw, ati8514_accel_outl, svga);
io_sethandler(0xcee8, 0x0002, ati8514_accel_inb, ati8514_accel_inw, ati8514_accel_inl, ati8514_accel_outb, ati8514_accel_outw, ati8514_accel_outl, svga);
io_sethandler(0xd2e8, 0x0002, ati8514_accel_inb, ati8514_accel_inw, ati8514_accel_inl, ati8514_accel_outb, ati8514_accel_outw, ati8514_accel_outl, svga);
io_sethandler(0xd6e8, 0x0002, ati8514_accel_inb, ati8514_accel_inw, ati8514_accel_inl, ati8514_accel_outb, ati8514_accel_outw, ati8514_accel_outl, svga);
io_sethandler(0xdae8, 0x0002, ati8514_accel_inb, ati8514_accel_inw, ati8514_accel_inl, ati8514_accel_outb, ati8514_accel_outw, ati8514_accel_outl, svga);
io_sethandler(0xdee8, 0x0002, ati8514_accel_inb, ati8514_accel_inw, ati8514_accel_inl, ati8514_accel_outb, ati8514_accel_outw, ati8514_accel_outl, svga);
io_sethandler(0xe6e8, 0x0002, ati8514_accel_inb, ati8514_accel_inw, ati8514_accel_inl, ati8514_accel_outb, ati8514_accel_outw, ati8514_accel_outl, svga);
io_sethandler(0xeae8, 0x0002, ati8514_accel_inb, ati8514_accel_inw, ati8514_accel_inl, ati8514_accel_outb, ati8514_accel_outw, ati8514_accel_outl, svga);
io_sethandler(0xeee8, 0x0002, ati8514_accel_inb, ati8514_accel_inw, ati8514_accel_inl, ati8514_accel_outb, ati8514_accel_outw, ati8514_accel_outl, svga);
io_sethandler(0xf2e8, 0x0002, ati8514_accel_inb, ati8514_accel_inw, ati8514_accel_inl, ati8514_accel_outb, ati8514_accel_outw, ati8514_accel_outl, svga);
io_sethandler(0xf6e8, 0x0002, ati8514_accel_inb, ati8514_accel_inw, ati8514_accel_inl, ati8514_accel_outb, ati8514_accel_outw, ati8514_accel_outl, svga);
io_sethandler(0xfae8, 0x0002, ati8514_accel_inb, ati8514_accel_inw, ati8514_accel_inl, ati8514_accel_outb, ati8514_accel_outw, ati8514_accel_outl, svga);
io_sethandler(0xfee8, 0x0002, ati8514_accel_inb, ati8514_accel_inw, ati8514_accel_inl, ati8514_accel_outb, ati8514_accel_outw, ati8514_accel_outl, svga);
io_sethandler(0x02ee, 0x0002, ati8514_accel_inb, ati8514_accel_inw, ati8514_accel_inl, ati8514_accel_outb, ati8514_accel_outw, ati8514_accel_outl, svga);
io_sethandler(0x06ee, 0x0002, ati8514_accel_inb, ati8514_accel_inw, ati8514_accel_inl, ati8514_accel_outb, ati8514_accel_outw, ati8514_accel_outl, svga);
io_sethandler(0x0aee, 0x0002, ati8514_accel_inb, ati8514_accel_inw, ati8514_accel_inl, ati8514_accel_outb, ati8514_accel_outw, ati8514_accel_outl, svga);
io_sethandler(0x0eee, 0x0002, ati8514_accel_inb, ati8514_accel_inw, ati8514_accel_inl, ati8514_accel_outb, ati8514_accel_outw, ati8514_accel_outl, svga);
io_sethandler(0x12ee, 0x0002, ati8514_accel_inb, ati8514_accel_inw, ati8514_accel_inl, ati8514_accel_outb, ati8514_accel_outw, ati8514_accel_outl, svga);
io_sethandler(0x16ee, 0x0002, ati8514_accel_inb, ati8514_accel_inw, ati8514_accel_inl, ati8514_accel_outb, ati8514_accel_outw, ati8514_accel_outl, svga);
io_sethandler(0x1aee, 0x0002, ati8514_accel_inb, ati8514_accel_inw, ati8514_accel_inl, ati8514_accel_outb, ati8514_accel_outw, ati8514_accel_outl, svga);
io_sethandler(0x1eee, 0x0002, ati8514_accel_inb, ati8514_accel_inw, ati8514_accel_inl, ati8514_accel_outb, ati8514_accel_outw, ati8514_accel_outl, svga);
io_sethandler(0x22ee, 0x0002, ati8514_accel_inb, ati8514_accel_inw, ati8514_accel_inl, ati8514_accel_outb, ati8514_accel_outw, ati8514_accel_outl, svga);
io_sethandler(0x26ee, 0x0002, ati8514_accel_inb, ati8514_accel_inw, ati8514_accel_inl, ati8514_accel_outb, ati8514_accel_outw, ati8514_accel_outl, svga);
io_sethandler(0x2aee, 0x0002, ati8514_accel_inb, ati8514_accel_inw, ati8514_accel_inl, ati8514_accel_outb, ati8514_accel_outw, ati8514_accel_outl, svga);
io_sethandler(0x2eee, 0x0002, ati8514_accel_inb, ati8514_accel_inw, ati8514_accel_inl, ati8514_accel_outb, ati8514_accel_outw, ati8514_accel_outl, svga);
io_sethandler(0x32ee, 0x0002, ati8514_accel_inb, ati8514_accel_inw, ati8514_accel_inl, ati8514_accel_outb, ati8514_accel_outw, ati8514_accel_outl, svga);
io_sethandler(0x36ee, 0x0002, ati8514_accel_inb, ati8514_accel_inw, ati8514_accel_inl, ati8514_accel_outb, ati8514_accel_outw, ati8514_accel_outl, svga);
io_sethandler(0x3aee, 0x0002, ati8514_accel_inb, ati8514_accel_inw, ati8514_accel_inl, ati8514_accel_outb, ati8514_accel_outw, ati8514_accel_outl, svga);
io_sethandler(0x3eee, 0x0002, ati8514_accel_inb, ati8514_accel_inw, ati8514_accel_inl, ati8514_accel_outb, ati8514_accel_outw, ati8514_accel_outl, svga);
io_sethandler(0x42ee, 0x0002, ati8514_accel_inb, ati8514_accel_inw, ati8514_accel_inl, ati8514_accel_outb, ati8514_accel_outw, ati8514_accel_outl, svga);
io_sethandler(0x46ee, 0x0002, ati8514_accel_inb, ati8514_accel_inw, ati8514_accel_inl, ati8514_accel_outb, ati8514_accel_outw, ati8514_accel_outl, svga);
io_sethandler(0x4aee, 0x0002, ati8514_accel_inb, ati8514_accel_inw, ati8514_accel_inl, ati8514_accel_outb, ati8514_accel_outw, ati8514_accel_outl, svga);
io_sethandler(0x52ee, 0x0002, ati8514_accel_inb, ati8514_accel_inw, ati8514_accel_inl, ati8514_accel_outb, ati8514_accel_outw, ati8514_accel_outl, svga);
io_sethandler(0x56ee, 0x0002, ati8514_accel_inb, ati8514_accel_inw, ati8514_accel_inl, ati8514_accel_outb, ati8514_accel_outw, ati8514_accel_outl, svga);
io_sethandler(0x5aee, 0x0002, ati8514_accel_inb, ati8514_accel_inw, ati8514_accel_inl, ati8514_accel_outb, ati8514_accel_outw, ati8514_accel_outl, svga);
io_sethandler(0x5eee, 0x0002, ati8514_accel_inb, ati8514_accel_inw, ati8514_accel_inl, ati8514_accel_outb, ati8514_accel_outw, ati8514_accel_outl, svga);
io_sethandler(0x62ee, 0x0002, ati8514_accel_inb, ati8514_accel_inw, ati8514_accel_inl, ati8514_accel_outb, ati8514_accel_outw, ati8514_accel_outl, svga);
io_sethandler(0x66ee, 0x0002, ati8514_accel_inb, ati8514_accel_inw, ati8514_accel_inl, ati8514_accel_outb, ati8514_accel_outw, ati8514_accel_outl, svga);
io_sethandler(0x6aee, 0x0002, ati8514_accel_inb, ati8514_accel_inw, ati8514_accel_inl, ati8514_accel_outb, ati8514_accel_outw, ati8514_accel_outl, svga);
io_sethandler(0x6eee, 0x0002, ati8514_accel_inb, ati8514_accel_inw, ati8514_accel_inl, ati8514_accel_outb, ati8514_accel_outw, ati8514_accel_outl, svga);
io_sethandler(0x72ee, 0x0002, ati8514_accel_inb, ati8514_accel_inw, ati8514_accel_inl, ati8514_accel_outb, ati8514_accel_outw, ati8514_accel_outl, svga);
io_sethandler(0x76ee, 0x0002, ati8514_accel_inb, ati8514_accel_inw, ati8514_accel_inl, ati8514_accel_outb, ati8514_accel_outw, ati8514_accel_outl, svga);
io_sethandler(0x7aee, 0x0002, ati8514_accel_inb, ati8514_accel_inw, ati8514_accel_inl, ati8514_accel_outb, ati8514_accel_outw, ati8514_accel_outl, svga);
io_sethandler(0x7eee, 0x0002, ati8514_accel_inb, ati8514_accel_inw, ati8514_accel_inl, ati8514_accel_outb, ati8514_accel_outw, ati8514_accel_outl, svga);
io_sethandler(0x82ee, 0x0002, ati8514_accel_inb, ati8514_accel_inw, ati8514_accel_inl, ati8514_accel_outb, ati8514_accel_outw, ati8514_accel_outl, svga);
io_sethandler(0x86ee, 0x0002, ati8514_accel_inb, ati8514_accel_inw, ati8514_accel_inl, ati8514_accel_outb, ati8514_accel_outw, ati8514_accel_outl, svga);
io_sethandler(0x8eee, 0x0002, ati8514_accel_inb, ati8514_accel_inw, ati8514_accel_inl, ati8514_accel_outb, ati8514_accel_outw, ati8514_accel_outl, svga);
io_sethandler(0x92ee, 0x0002, ati8514_accel_inb, ati8514_accel_inw, ati8514_accel_inl, ati8514_accel_outb, ati8514_accel_outw, ati8514_accel_outl, svga);
io_sethandler(0x96ee, 0x0002, ati8514_accel_inb, ati8514_accel_inw, ati8514_accel_inl, ati8514_accel_outb, ati8514_accel_outw, ati8514_accel_outl, svga);
io_sethandler(0x9aee, 0x0002, ati8514_accel_inb, ati8514_accel_inw, ati8514_accel_inl, ati8514_accel_outb, ati8514_accel_outw, ati8514_accel_outl, svga);
io_sethandler(0xa2ee, 0x0002, ati8514_accel_inb, ati8514_accel_inw, ati8514_accel_inl, ati8514_accel_outb, ati8514_accel_outw, ati8514_accel_outl, svga);
io_sethandler(0xa6ee, 0x0002, ati8514_accel_inb, ati8514_accel_inw, ati8514_accel_inl, ati8514_accel_outb, ati8514_accel_outw, ati8514_accel_outl, svga);
io_sethandler(0xaaee, 0x0002, ati8514_accel_inb, ati8514_accel_inw, ati8514_accel_inl, ati8514_accel_outb, ati8514_accel_outw, ati8514_accel_outl, svga);
io_sethandler(0xaeee, 0x0002, ati8514_accel_inb, ati8514_accel_inw, ati8514_accel_inl, ati8514_accel_outb, ati8514_accel_outw, ati8514_accel_outl, svga);
io_sethandler(0xb2ee, 0x0002, ati8514_accel_inb, ati8514_accel_inw, ati8514_accel_inl, ati8514_accel_outb, ati8514_accel_outw, ati8514_accel_outl, svga);
io_sethandler(0xb6ee, 0x0002, ati8514_accel_inb, ati8514_accel_inw, ati8514_accel_inl, ati8514_accel_outb, ati8514_accel_outw, ati8514_accel_outl, svga);
io_sethandler(0xbaee, 0x0002, ati8514_accel_inb, ati8514_accel_inw, ati8514_accel_inl, ati8514_accel_outb, ati8514_accel_outw, ati8514_accel_outl, svga);
io_sethandler(0xbeee, 0x0002, ati8514_accel_inb, ati8514_accel_inw, ati8514_accel_inl, ati8514_accel_outb, ati8514_accel_outw, ati8514_accel_outl, svga);
io_sethandler(0xc2ee, 0x0002, ati8514_accel_inb, ati8514_accel_inw, ati8514_accel_inl, ati8514_accel_outb, ati8514_accel_outw, ati8514_accel_outl, svga);
io_sethandler(0xc6ee, 0x0002, ati8514_accel_inb, ati8514_accel_inw, ati8514_accel_inl, ati8514_accel_outb, ati8514_accel_outw, ati8514_accel_outl, svga);
io_sethandler(0xcaee, 0x0002, ati8514_accel_inb, ati8514_accel_inw, ati8514_accel_inl, ati8514_accel_outb, ati8514_accel_outw, ati8514_accel_outl, svga);
io_sethandler(0xceee, 0x0002, ati8514_accel_inb, ati8514_accel_inw, ati8514_accel_inl, ati8514_accel_outb, ati8514_accel_outw, ati8514_accel_outl, svga);
io_sethandler(0xd2ee, 0x0002, ati8514_accel_inb, ati8514_accel_inw, ati8514_accel_inl, ati8514_accel_outb, ati8514_accel_outw, ati8514_accel_outl, svga);
io_sethandler(0xd6ee, 0x0002, ati8514_accel_inb, ati8514_accel_inw, ati8514_accel_inl, ati8514_accel_outb, ati8514_accel_outw, ati8514_accel_outl, svga);
io_sethandler(0xdaee, 0x0002, ati8514_accel_inb, ati8514_accel_inw, ati8514_accel_inl, ati8514_accel_outb, ati8514_accel_outw, ati8514_accel_outl, svga);
io_sethandler(0xdeee, 0x0002, ati8514_accel_inb, ati8514_accel_inw, ati8514_accel_inl, ati8514_accel_outb, ati8514_accel_outw, ati8514_accel_outl, svga);
io_sethandler(0xe2ee, 0x0002, ati8514_accel_inb, ati8514_accel_inw, ati8514_accel_inl, ati8514_accel_outb, ati8514_accel_outw, ati8514_accel_outl, svga);
io_sethandler(0xe6ee, 0x0002, ati8514_accel_inb, ati8514_accel_inw, ati8514_accel_inl, ati8514_accel_outb, ati8514_accel_outw, ati8514_accel_outl, svga);
io_sethandler(0xeeee, 0x0002, ati8514_accel_inb, ati8514_accel_inw, ati8514_accel_inl, ati8514_accel_outb, ati8514_accel_outw, ati8514_accel_outl, svga);
io_sethandler(0xf2ee, 0x0002, ati8514_accel_inb, ati8514_accel_inw, ati8514_accel_inl, ati8514_accel_outb, ati8514_accel_outw, ati8514_accel_outl, svga);
io_sethandler(0xf6ee, 0x0002, ati8514_accel_inb, ati8514_accel_inw, ati8514_accel_inl, ati8514_accel_outb, ati8514_accel_outw, ati8514_accel_outl, svga);
io_sethandler(0xfeee, 0x0002, ati8514_accel_inb, ati8514_accel_inw, ati8514_accel_inl, ati8514_accel_outb, ati8514_accel_outw, ati8514_accel_outl, svga);
}
#endif
static void
mach_io_set(mach_t *mach)
{
io_sethandler(0x2e8, 0x0002, mach_accel_inb, mach_accel_inw, mach_accel_inl, mach_accel_outb, mach_accel_outw, mach_accel_outl, mach);
io_sethandler(0x6e8, 0x0002, mach_accel_inb, mach_accel_inw, mach_accel_inl, mach_accel_outb, mach_accel_outw, mach_accel_outl, mach);
io_sethandler(0xae8, 0x0002, mach_accel_inb, mach_accel_inw, mach_accel_inl, mach_accel_outb, mach_accel_outw, mach_accel_outl, mach);
io_sethandler(0xee8, 0x0002, mach_accel_inb, mach_accel_inw, mach_accel_inl, mach_accel_outb, mach_accel_outw, mach_accel_outl, mach);
io_sethandler(0x12e8, 0x0002, mach_accel_inb, mach_accel_inw, mach_accel_inl, mach_accel_outb, mach_accel_outw, mach_accel_outl, mach);
io_sethandler(0x16e8, 0x0002, mach_accel_inb, mach_accel_inw, mach_accel_inl, mach_accel_outb, mach_accel_outw, mach_accel_outl, mach);
io_sethandler(0x1ae8, 0x0002, mach_accel_inb, mach_accel_inw, mach_accel_inl, mach_accel_outb, mach_accel_outw, mach_accel_outl, mach);
io_sethandler(0x1ee8, 0x0002, mach_accel_inb, mach_accel_inw, mach_accel_inl, mach_accel_outb, mach_accel_outw, mach_accel_outl, mach);
io_sethandler(0x22e8, 0x0002, mach_accel_inb, mach_accel_inw, mach_accel_inl, mach_accel_outb, mach_accel_outw, mach_accel_outl, mach);
io_sethandler(0x26e8, 0x0002, mach_accel_inb, mach_accel_inw, mach_accel_inl, mach_accel_outb, mach_accel_outw, mach_accel_outl, mach);
io_sethandler(0x2ee8, 0x0002, mach_accel_inb, mach_accel_inw, mach_accel_inl, mach_accel_outb, mach_accel_outw, mach_accel_outl, mach);
io_sethandler(0x42e8, 0x0002, mach_accel_inb, mach_accel_inw, mach_accel_inl, mach_accel_outb, mach_accel_outw, mach_accel_outl, mach);
io_sethandler(0x46e8, 0x0002, mach_accel_inb, mach_accel_inw, mach_accel_inl, mach_accel_outb, mach_accel_outw, mach_accel_outl, mach);
io_sethandler(0x4ae8, 0x0002, mach_accel_inb, mach_accel_inw, mach_accel_inl, mach_accel_outb, mach_accel_outw, mach_accel_outl, mach);
io_sethandler(0x52e8, 0x0002, mach_accel_inb, mach_accel_inw, mach_accel_inl, mach_accel_outb, mach_accel_outw, mach_accel_outl, mach);
io_sethandler(0x56e8, 0x0002, mach_accel_inb, mach_accel_inw, mach_accel_inl, mach_accel_outb, mach_accel_outw, mach_accel_outl, mach);
io_sethandler(0x5ae8, 0x0002, mach_accel_inb, mach_accel_inw, mach_accel_inl, mach_accel_outb, mach_accel_outw, mach_accel_outl, mach);
io_sethandler(0x5ee8, 0x0002, mach_accel_inb, mach_accel_inw, mach_accel_inl, mach_accel_outb, mach_accel_outw, mach_accel_outl, mach);
io_sethandler(0x82e8, 0x0002, mach_accel_inb, mach_accel_inw, mach_accel_inl, mach_accel_outb, mach_accel_outw, mach_accel_outl, mach);
io_sethandler(0x86e8, 0x0002, mach_accel_inb, mach_accel_inw, mach_accel_inl, mach_accel_outb, mach_accel_outw, mach_accel_outl, mach);
io_sethandler(0x8ae8, 0x0002, mach_accel_inb, mach_accel_inw, mach_accel_inl, mach_accel_outb, mach_accel_outw, mach_accel_outl, mach);
io_sethandler(0x8ee8, 0x0002, mach_accel_inb, mach_accel_inw, mach_accel_inl, mach_accel_outb, mach_accel_outw, mach_accel_outl, mach);
io_sethandler(0x92e8, 0x0002, mach_accel_inb, mach_accel_inw, mach_accel_inl, mach_accel_outb, mach_accel_outw, mach_accel_outl, mach);
io_sethandler(0x96e8, 0x0002, mach_accel_inb, mach_accel_inw, mach_accel_inl, mach_accel_outb, mach_accel_outw, mach_accel_outl, mach);
io_sethandler(0x9ae8, 0x0002, mach_accel_inb, mach_accel_inw, mach_accel_inl, mach_accel_outb, mach_accel_outw, mach_accel_outl, mach);
io_sethandler(0x9ee8, 0x0002, mach_accel_inb, mach_accel_inw, mach_accel_inl, mach_accel_outb, mach_accel_outw, mach_accel_outl, mach);
io_sethandler(0xa2e8, 0x0002, mach_accel_inb, mach_accel_inw, mach_accel_inl, mach_accel_outb, mach_accel_outw, mach_accel_outl, mach);
io_sethandler(0xa6e8, 0x0002, mach_accel_inb, mach_accel_inw, mach_accel_inl, mach_accel_outb, mach_accel_outw, mach_accel_outl, mach);
io_sethandler(0xaae8, 0x0002, mach_accel_inb, mach_accel_inw, mach_accel_inl, mach_accel_outb, mach_accel_outw, mach_accel_outl, mach);
io_sethandler(0xaee8, 0x0002, mach_accel_inb, mach_accel_inw, mach_accel_inl, mach_accel_outb, mach_accel_outw, mach_accel_outl, mach);
io_sethandler(0xb2e8, 0x0002, mach_accel_inb, mach_accel_inw, mach_accel_inl, mach_accel_outb, mach_accel_outw, mach_accel_outl, mach);
io_sethandler(0xb6e8, 0x0002, mach_accel_inb, mach_accel_inw, mach_accel_inl, mach_accel_outb, mach_accel_outw, mach_accel_outl, mach);
io_sethandler(0xbae8, 0x0002, mach_accel_inb, mach_accel_inw, mach_accel_inl, mach_accel_outb, mach_accel_outw, mach_accel_outl, mach);
io_sethandler(0xbee8, 0x0002, mach_accel_inb, mach_accel_inw, mach_accel_inl, mach_accel_outb, mach_accel_outw, mach_accel_outl, mach);
io_sethandler(0xe2e8, 0x0002, mach_accel_inb, mach_accel_inw, mach_accel_inl, mach_accel_outb, mach_accel_outw, mach_accel_outl, mach);
io_sethandler(0xc2e8, 0x0002, mach_accel_inb, mach_accel_inw, mach_accel_inl, mach_accel_outb, mach_accel_outw, mach_accel_outl, mach);
io_sethandler(0xc6e8, 0x0002, mach_accel_inb, mach_accel_inw, mach_accel_inl, mach_accel_outb, mach_accel_outw, mach_accel_outl, mach);
io_sethandler(0xcae8, 0x0002, mach_accel_inb, mach_accel_inw, mach_accel_inl, mach_accel_outb, mach_accel_outw, mach_accel_outl, mach);
io_sethandler(0xcee8, 0x0002, mach_accel_inb, mach_accel_inw, mach_accel_inl, mach_accel_outb, mach_accel_outw, mach_accel_outl, mach);
io_sethandler(0xd2e8, 0x0002, mach_accel_inb, mach_accel_inw, mach_accel_inl, mach_accel_outb, mach_accel_outw, mach_accel_outl, mach);
io_sethandler(0xd6e8, 0x0002, mach_accel_inb, mach_accel_inw, mach_accel_inl, mach_accel_outb, mach_accel_outw, mach_accel_outl, mach);
io_sethandler(0xdae8, 0x0002, mach_accel_inb, mach_accel_inw, mach_accel_inl, mach_accel_outb, mach_accel_outw, mach_accel_outl, mach);
io_sethandler(0xdee8, 0x0002, mach_accel_inb, mach_accel_inw, mach_accel_inl, mach_accel_outb, mach_accel_outw, mach_accel_outl, mach);
io_sethandler(0xe6e8, 0x0002, mach_accel_inb, mach_accel_inw, mach_accel_inl, mach_accel_outb, mach_accel_outw, mach_accel_outl, mach);
io_sethandler(0xeae8, 0x0002, mach_accel_inb, mach_accel_inw, mach_accel_inl, mach_accel_outb, mach_accel_outw, mach_accel_outl, mach);
io_sethandler(0xeee8, 0x0002, mach_accel_inb, mach_accel_inw, mach_accel_inl, mach_accel_outb, mach_accel_outw, mach_accel_outl, mach);
io_sethandler(0xf2e8, 0x0002, mach_accel_inb, mach_accel_inw, mach_accel_inl, mach_accel_outb, mach_accel_outw, mach_accel_outl, mach);
io_sethandler(0xf6e8, 0x0002, mach_accel_inb, mach_accel_inw, mach_accel_inl, mach_accel_outb, mach_accel_outw, mach_accel_outl, mach);
io_sethandler(0xfae8, 0x0002, mach_accel_inb, mach_accel_inw, mach_accel_inl, mach_accel_outb, mach_accel_outw, mach_accel_outl, mach);
io_sethandler(0xfee8, 0x0002, mach_accel_inb, mach_accel_inw, mach_accel_inl, mach_accel_outb, mach_accel_outw, mach_accel_outl, mach);
io_sethandler(0x02ee, 0x0002, mach_accel_inb, mach_accel_inw, mach_accel_inl, mach_accel_outb, mach_accel_outw, mach_accel_outl, mach);
io_sethandler(0x06ee, 0x0002, mach_accel_inb, mach_accel_inw, mach_accel_inl, mach_accel_outb, mach_accel_outw, mach_accel_outl, mach);
io_sethandler(0x0aee, 0x0002, mach_accel_inb, mach_accel_inw, mach_accel_inl, mach_accel_outb, mach_accel_outw, mach_accel_outl, mach);
io_sethandler(0x0eee, 0x0002, mach_accel_inb, mach_accel_inw, mach_accel_inl, mach_accel_outb, mach_accel_outw, mach_accel_outl, mach);
io_sethandler(0x12ee, 0x0002, mach_accel_inb, mach_accel_inw, mach_accel_inl, mach_accel_outb, mach_accel_outw, mach_accel_outl, mach);
io_sethandler(0x16ee, 0x0002, mach_accel_inb, mach_accel_inw, mach_accel_inl, mach_accel_outb, mach_accel_outw, mach_accel_outl, mach);
io_sethandler(0x1aee, 0x0002, mach_accel_inb, mach_accel_inw, mach_accel_inl, mach_accel_outb, mach_accel_outw, mach_accel_outl, mach);
io_sethandler(0x1eee, 0x0002, mach_accel_inb, mach_accel_inw, mach_accel_inl, mach_accel_outb, mach_accel_outw, mach_accel_outl, mach);
io_sethandler(0x22ee, 0x0002, mach_accel_inb, mach_accel_inw, mach_accel_inl, mach_accel_outb, mach_accel_outw, mach_accel_outl, mach);
io_sethandler(0x26ee, 0x0002, mach_accel_inb, mach_accel_inw, mach_accel_inl, mach_accel_outb, mach_accel_outw, mach_accel_outl, mach);
io_sethandler(0x2aee, 0x0002, mach_accel_inb, mach_accel_inw, mach_accel_inl, mach_accel_outb, mach_accel_outw, mach_accel_outl, mach);
io_sethandler(0x2eee, 0x0002, mach_accel_inb, mach_accel_inw, mach_accel_inl, mach_accel_outb, mach_accel_outw, mach_accel_outl, mach);
io_sethandler(0x32ee, 0x0002, mach_accel_inb, mach_accel_inw, mach_accel_inl, mach_accel_outb, mach_accel_outw, mach_accel_outl, mach);
io_sethandler(0x36ee, 0x0002, mach_accel_inb, mach_accel_inw, mach_accel_inl, mach_accel_outb, mach_accel_outw, mach_accel_outl, mach);
io_sethandler(0x3aee, 0x0002, mach_accel_inb, mach_accel_inw, mach_accel_inl, mach_accel_outb, mach_accel_outw, mach_accel_outl, mach);
io_sethandler(0x3eee, 0x0002, mach_accel_inb, mach_accel_inw, mach_accel_inl, mach_accel_outb, mach_accel_outw, mach_accel_outl, mach);
io_sethandler(0x42ee, 0x0002, mach_accel_inb, mach_accel_inw, mach_accel_inl, mach_accel_outb, mach_accel_outw, mach_accel_outl, mach);
io_sethandler(0x46ee, 0x0002, mach_accel_inb, mach_accel_inw, mach_accel_inl, mach_accel_outb, mach_accel_outw, mach_accel_outl, mach);
io_sethandler(0x4aee, 0x0002, mach_accel_inb, mach_accel_inw, mach_accel_inl, mach_accel_outb, mach_accel_outw, mach_accel_outl, mach);
io_sethandler(0x52ee, 0x0002, mach_accel_inb, mach_accel_inw, mach_accel_inl, mach_accel_outb, mach_accel_outw, mach_accel_outl, mach);
io_sethandler(0x56ee, 0x0002, mach_accel_inb, mach_accel_inw, mach_accel_inl, mach_accel_outb, mach_accel_outw, mach_accel_outl, mach);
io_sethandler(0x5aee, 0x0002, mach_accel_inb, mach_accel_inw, mach_accel_inl, mach_accel_outb, mach_accel_outw, mach_accel_outl, mach);
io_sethandler(0x5eee, 0x0002, mach_accel_inb, mach_accel_inw, mach_accel_inl, mach_accel_outb, mach_accel_outw, mach_accel_outl, mach);
io_sethandler(0x62ee, 0x0002, mach_accel_inb, mach_accel_inw, mach_accel_inl, mach_accel_outb, mach_accel_outw, mach_accel_outl, mach);
io_sethandler(0x66ee, 0x0002, mach_accel_inb, mach_accel_inw, mach_accel_inl, mach_accel_outb, mach_accel_outw, mach_accel_outl, mach);
io_sethandler(0x6aee, 0x0002, mach_accel_inb, mach_accel_inw, mach_accel_inl, mach_accel_outb, mach_accel_outw, mach_accel_outl, mach);
io_sethandler(0x6eee, 0x0002, mach_accel_inb, mach_accel_inw, mach_accel_inl, mach_accel_outb, mach_accel_outw, mach_accel_outl, mach);
io_sethandler(0x72ee, 0x0002, mach_accel_inb, mach_accel_inw, mach_accel_inl, mach_accel_outb, mach_accel_outw, mach_accel_outl, mach);
io_sethandler(0x76ee, 0x0002, mach_accel_inb, mach_accel_inw, mach_accel_inl, mach_accel_outb, mach_accel_outw, mach_accel_outl, mach);
io_sethandler(0x7aee, 0x0002, mach_accel_inb, mach_accel_inw, mach_accel_inl, mach_accel_outb, mach_accel_outw, mach_accel_outl, mach);
io_sethandler(0x7eee, 0x0002, mach_accel_inb, mach_accel_inw, mach_accel_inl, mach_accel_outb, mach_accel_outw, mach_accel_outl, mach);
io_sethandler(0x82ee, 0x0002, mach_accel_inb, mach_accel_inw, mach_accel_inl, mach_accel_outb, mach_accel_outw, mach_accel_outl, mach);
io_sethandler(0x86ee, 0x0002, mach_accel_inb, mach_accel_inw, mach_accel_inl, mach_accel_outb, mach_accel_outw, mach_accel_outl, mach);
io_sethandler(0x8eee, 0x0002, mach_accel_inb, mach_accel_inw, mach_accel_inl, mach_accel_outb, mach_accel_outw, mach_accel_outl, mach);
io_sethandler(0x92ee, 0x0002, mach_accel_inb, mach_accel_inw, mach_accel_inl, mach_accel_outb, mach_accel_outw, mach_accel_outl, mach);
io_sethandler(0x96ee, 0x0002, mach_accel_inb, mach_accel_inw, mach_accel_inl, mach_accel_outb, mach_accel_outw, mach_accel_outl, mach);
io_sethandler(0x9aee, 0x0002, mach_accel_inb, mach_accel_inw, mach_accel_inl, mach_accel_outb, mach_accel_outw, mach_accel_outl, mach);
io_sethandler(0xa2ee, 0x0002, mach_accel_inb, mach_accel_inw, mach_accel_inl, mach_accel_outb, mach_accel_outw, mach_accel_outl, mach);
io_sethandler(0xa6ee, 0x0002, mach_accel_inb, mach_accel_inw, mach_accel_inl, mach_accel_outb, mach_accel_outw, mach_accel_outl, mach);
io_sethandler(0xaaee, 0x0002, mach_accel_inb, mach_accel_inw, mach_accel_inl, mach_accel_outb, mach_accel_outw, mach_accel_outl, mach);
io_sethandler(0xaeee, 0x0002, mach_accel_inb, mach_accel_inw, mach_accel_inl, mach_accel_outb, mach_accel_outw, mach_accel_outl, mach);
io_sethandler(0xb2ee, 0x0002, mach_accel_inb, mach_accel_inw, mach_accel_inl, mach_accel_outb, mach_accel_outw, mach_accel_outl, mach);
io_sethandler(0xb6ee, 0x0002, mach_accel_inb, mach_accel_inw, mach_accel_inl, mach_accel_outb, mach_accel_outw, mach_accel_outl, mach);
io_sethandler(0xbaee, 0x0002, mach_accel_inb, mach_accel_inw, mach_accel_inl, mach_accel_outb, mach_accel_outw, mach_accel_outl, mach);
io_sethandler(0xbeee, 0x0002, mach_accel_inb, mach_accel_inw, mach_accel_inl, mach_accel_outb, mach_accel_outw, mach_accel_outl, mach);
io_sethandler(0xc2ee, 0x0002, mach_accel_inb, mach_accel_inw, mach_accel_inl, mach_accel_outb, mach_accel_outw, mach_accel_outl, mach);
io_sethandler(0xc6ee, 0x0002, mach_accel_inb, mach_accel_inw, mach_accel_inl, mach_accel_outb, mach_accel_outw, mach_accel_outl, mach);
io_sethandler(0xcaee, 0x0002, mach_accel_inb, mach_accel_inw, mach_accel_inl, mach_accel_outb, mach_accel_outw, mach_accel_outl, mach);
io_sethandler(0xceee, 0x0002, mach_accel_inb, mach_accel_inw, mach_accel_inl, mach_accel_outb, mach_accel_outw, mach_accel_outl, mach);
io_sethandler(0xd2ee, 0x0002, mach_accel_inb, mach_accel_inw, mach_accel_inl, mach_accel_outb, mach_accel_outw, mach_accel_outl, mach);
io_sethandler(0xd6ee, 0x0002, mach_accel_inb, mach_accel_inw, mach_accel_inl, mach_accel_outb, mach_accel_outw, mach_accel_outl, mach);
io_sethandler(0xdaee, 0x0002, mach_accel_inb, mach_accel_inw, mach_accel_inl, mach_accel_outb, mach_accel_outw, mach_accel_outl, mach);
io_sethandler(0xdeee, 0x0002, mach_accel_inb, mach_accel_inw, mach_accel_inl, mach_accel_outb, mach_accel_outw, mach_accel_outl, mach);
io_sethandler(0xe2ee, 0x0002, mach_accel_inb, mach_accel_inw, mach_accel_inl, mach_accel_outb, mach_accel_outw, mach_accel_outl, mach);
io_sethandler(0xe6ee, 0x0002, mach_accel_inb, mach_accel_inw, mach_accel_inl, mach_accel_outb, mach_accel_outw, mach_accel_outl, mach);
io_sethandler(0xeeee, 0x0002, mach_accel_inb, mach_accel_inw, mach_accel_inl, mach_accel_outb, mach_accel_outw, mach_accel_outl, mach);
io_sethandler(0xf2ee, 0x0002, mach_accel_inb, mach_accel_inw, mach_accel_inl, mach_accel_outb, mach_accel_outw, mach_accel_outl, mach);
io_sethandler(0xf6ee, 0x0002, mach_accel_inb, mach_accel_inw, mach_accel_inl, mach_accel_outb, mach_accel_outw, mach_accel_outl, mach);
io_sethandler(0xfaee, 0x0002, mach_accel_inb, mach_accel_inw, mach_accel_inl, mach_accel_outb, mach_accel_outw, mach_accel_outl, mach);
io_sethandler(0xfeee, 0x0002, mach_accel_inb, mach_accel_inw, mach_accel_inl, mach_accel_outb, mach_accel_outw, mach_accel_outl, mach);
}
static uint8_t
mach_mca_read(int port, void *priv)
{
const mach_t *mach = (mach_t *) priv;
mach_log("[%04X]: MCA read port = %x, val = %02x.\n", CS, port & 7, mach->pos_regs[port & 7]);
return mach->pos_regs[port & 7];
}
static void
mach_mca_write(int port, uint8_t val, void *priv)
{
mach_t *mach = (mach_t *) priv;
if (port < 0x102)
return;
mach->pos_regs[port & 7] = val;
mach_log("[%04X]: MCA write port = %x, val = %02x, biosaddr = %05x.\n", CS, port & 7, mach->pos_regs[port & 7], (((mach->pos_regs[3] & 0x3e) << 0x0c) >> 1) + 0xc0000);
mem_mapping_disable(&mach->bios_rom.mapping);
mem_mapping_disable(&mach->bios_rom2.mapping);
if (mach->pos_regs[2] & 0x01) {
mem_mapping_enable(&mach->bios_rom.mapping);
mem_mapping_enable(&mach->bios_rom2.mapping);
}
}
static uint8_t
mach_mca_feedb(void *priv)
{
const mach_t *mach = (mach_t *) priv;
mach_log("FeedB = %x.\n", mach->pos_regs[2] & 0x01);
return mach->pos_regs[2] & 0x01;
}
static void
mach_mca_reset(void *priv)
{
mach_t *mach = (mach_t *) priv;
svga_t *svga = &mach->svga;
ibm8514_t *dev = (ibm8514_t *) svga->dev8514;
mem_mapping_disable(&mach->bios_rom.mapping);
mem_mapping_disable(&mach->bios_rom2.mapping);
mach_log("MCA reset.\n");
dev->on[0] = 0;
dev->on[1] = 0;
vga_on = 1;
mach_mca_write(0x102, 0, mach);
}
#ifdef ATI_8514_ULTRA
uint8_t
ati8514_mca_read(int port, void *priv)
{
const svga_t *svga = (svga_t *) priv;
const ibm8514_t *dev = (ibm8514_t *) svga->dev8514;
return (dev->pos_regs[port & 7]);
}
void
ati8514_mca_write(int port, uint8_t val, void *priv)
{
svga_t *svga = (svga_t *) priv;
ibm8514_t *dev = (ibm8514_t *) svga->dev8514;
if (port < 0x102)
return;
dev->pos_regs[port & 7] = val;
mach_log("[%04X]: MCA write port = %x, val = %02x, biosaddr = %05x.\n", CS, port & 7, dev->pos_regs[port & 7], (((dev->pos_regs[3] & 0x3e) << 0x0c) >> 1) + 0xc0000);
mem_mapping_disable(&dev->bios_rom.mapping);
if (dev->pos_regs[2] & 0x01)
mem_mapping_enable(&dev->bios_rom.mapping);
}
void
ati8514_pos_write(uint16_t port, uint8_t val, void *priv)
{
ati8514_mca_write(port, val, priv);
}
#endif
static uint8_t
mach32_pci_read(UNUSED(int func), int addr, void *priv)
{
const mach_t *mach = (mach_t *) priv;
uint8_t ret = 0x00;
if ((addr >= 0x30) && (addr <= 0x33) && !mach->has_bios)
return ret;
switch (addr) {
case 0x00:
ret = 0x02; /*ATI*/
break;
case 0x01:
ret = 0x10;
break;
case 0x02:
ret = 0x58;
break;
case 0x03:
ret = 0x41;
break;
case PCI_REG_COMMAND:
ret = mach->pci_regs[PCI_REG_COMMAND] | 0x80; /*Respond to IO and memory accesses*/
break;
case 0x07:
ret = 0x01; /*Medium DEVSEL timing*/
break;
case 0x0a:
ret = 0x00; /*Supports VGA interface*/
break;
case 0x0b:
ret = 0x03;
break;
case 0x10:
ret = 0x00; /*Linear frame buffer address*/
break;
case 0x11:
ret = 0x00;
break;
case 0x12:
ret = mach->linear_base >> 16;
break;
case 0x13:
ret = mach->linear_base >> 24;
break;
case 0x30:
ret = (mach->pci_regs[0x30] & 0x01); /*BIOS ROM address*/
break;
case 0x31:
ret = 0x00;
break;
case 0x32:
ret = mach->pci_regs[0x32];
break;
case 0x33:
ret = mach->pci_regs[0x33];
break;
case 0x3c:
ret = mach->int_line;
break;
case 0x3d:
ret = PCI_INTA;
break;
default:
break;
}
return ret;
}
static void
mach32_pci_write(UNUSED(int func), int addr, uint8_t val, void *priv)
{
mach_t *mach = (mach_t *) priv;
if ((addr >= 0x30) && (addr <= 0x33) && !mach->has_bios)
return;
switch (addr) {
case PCI_REG_COMMAND:
mach->pci_regs[PCI_REG_COMMAND] = val & 0x27;
if (val & PCI_COMMAND_IO) {
io_removehandler(0x02ea, 4, mach_in, NULL, NULL, mach_out, NULL, NULL, mach);
io_removehandler(0x03c0, 32, mach_in, NULL, NULL, mach_out, NULL, NULL, mach);
io_sethandler(0x02ea, 4, mach_in, NULL, NULL, mach_out, NULL, NULL, mach);
io_sethandler(0x03c0, 32, mach_in, NULL, NULL, mach_out, NULL, NULL, mach);
} else {
io_removehandler(0x02ea, 4, mach_in, NULL, NULL, mach_out, NULL, NULL, mach);
io_removehandler(0x03c0, 32, mach_in, NULL, NULL, mach_out, NULL, NULL, mach);
}
mach32_updatemapping(mach, &mach->svga);
break;
case 0x12:
mach->linear_base = (mach->linear_base & 0xff000000) | ((val & 0xc0) << 16);
mach32_updatemapping(mach, &mach->svga);
break;
case 0x13:
mach->linear_base = (mach->linear_base & 0xc00000) | (val << 24);
mach32_updatemapping(mach, &mach->svga);
break;
case 0x30:
case 0x32:
case 0x33:
mach->pci_regs[addr] = val;
if (mach->pci_regs[0x30] & 0x01) {
uint32_t bios_addr = (mach->pci_regs[0x32] << 16) | (mach->pci_regs[0x33] << 24);
mach_log("Mach32 bios_rom enabled at %08x\n", bios_addr);
mem_mapping_set_addr(&mach->bios_rom.mapping, bios_addr, 0x8000);
} else {
mach_log("Mach32 bios_rom disabled\n");
mem_mapping_disable(&mach->bios_rom.mapping);
}
return;
case 0x3c:
mach->int_line = val;
break;
default:
break;
}
}
static void *
mach8_init(const device_t *info)
{
mach_t *mach;
svga_t *svga;
ibm8514_t *dev;
mach = calloc(1, sizeof(mach_t));
svga = &mach->svga;
dev = (ibm8514_t *) calloc(1, sizeof(ibm8514_t));
svga->dev8514 = dev;
mach->pci_bus = !!(info->flags & DEVICE_PCI);
mach->vlb_bus = !!(info->flags & DEVICE_VLB);
mach->mca_bus = !!(info->flags & DEVICE_MCA);
dev->type = info->flags;
dev->local = info->local & 0xff;
mach->has_bios = !(info->local & 0xff00);
mach->memory = device_get_config_int("memory");
mach->ramdac_type = mach->pci_bus ? device_get_config_int("ramdac") : 1;
if ((dev->local & 0xff) >= 0x02) {
if (mach->pci_bus) {
if (mach->has_bios) {
rom_init(&mach->bios_rom,
BIOS_MACH32_PCI_ROM_PATH,
0xc0000, 0x8000, 0x7fff,
0, MEM_MAPPING_EXTERNAL);
}
}
else if (mach->vlb_bus)
rom_init(&mach->bios_rom,
BIOS_MACH32_VLB_ROM_PATH,
0xc0000, 0x8000, 0x7fff,
0, MEM_MAPPING_EXTERNAL);
else if (mach->mca_bus) {
rom_init(&mach->bios_rom,
BIOS_MACH32_MCA_ROM_PATH,
0xc0000, 0x8000, 0x7fff,
0, MEM_MAPPING_EXTERNAL);
rom_init(&mach->bios_rom2,
BIOS_MACH32_MCA_ROM_PATH,
0xc8000, 0x1000, 0x0fff,
0x8000, MEM_MAPPING_EXTERNAL);
} else {
rom_init(&mach->bios_rom,
BIOS_MACH32_ISA_ROM_PATH,
0xc0000, 0x8000, 0x7fff,
0, MEM_MAPPING_EXTERNAL);
}
} else
rom_init(&mach->bios_rom,
BIOS_MACH8_VGA_ROM_PATH,
0xc0000, 0x8000, 0x7fff,
0, MEM_MAPPING_EXTERNAL);
if ((dev->local & 0xff) >= 0x02) {
svga_init(info, svga, mach, mach->memory << 10, /*default: 2MB for Mach32*/
mach_recalctimings,
mach_in, mach_out,
mach32_hwcursor_draw,
NULL);
dev->vram_size = mach->memory << 10;
dev->vram = calloc(dev->vram_size, 1);
dev->changedvram = calloc((dev->vram_size >> 12) + 1, 1);
dev->vram_mask = dev->vram_size - 1;
dev->hwcursor.cur_ysize = 64;
mach->config1 = 0x20;
if (mach->pci_bus && !mach->ramdac_type)
svga->ramdac = device_add(&ati68860_ramdac_device);
else
svga->ramdac = device_add(&ati68875_ramdac_device);
if (mach->vlb_bus) {
video_inform(VIDEO_FLAG_TYPE_8514, &timing_mach32_vlb);
if (!is486)
mach->config1 |= 0x0a;
else
mach->config1 |= 0x0c;
mach->config1 |= 0x0400;
svga->clock_gen = device_add(&ati18811_0_device);
} else if (mach->mca_bus) {
video_inform(VIDEO_FLAG_TYPE_8514, &timing_mach32_mca);
if (is286 && !is386)
mach->config1 |= 0x04;
else
mach->config1 |= 0x06;
mach->config1 |= 0x0400;
svga->clock_gen = device_add(&ati18811_1_device);
} else if (mach->pci_bus) {
video_inform(VIDEO_FLAG_TYPE_8514, &timing_mach32_pci);
mach->config1 |= 0x0e;
if (mach->ramdac_type)
mach->config1 |= 0x0400;
else
mach->config1 |= 0x0a00;
mach->config2 |= 0x2000;
svga->clock_gen = device_add(&ati18811_0_device);
} else {
video_inform(VIDEO_FLAG_TYPE_8514, &timing_gfxultra_isa);
mach->config1 |= 0x0400;
svga->clock_gen = device_add(&ati18811_0_device);
}
mem_mapping_add(&mach->mmio_linear_mapping, 0, 0, mach32_ap_readb, mach32_ap_readw, mach32_ap_readl, mach32_ap_writeb, mach32_ap_writew, mach32_ap_writel, NULL, MEM_MAPPING_EXTERNAL, mach);
mem_mapping_disable(&mach->mmio_linear_mapping);
} else {
svga_init(info, svga, mach, (512 << 10), /*default: 512kB VGA for 28800-6 + 1MB for Mach8*/
mach_recalctimings,
mach_in, mach_out,
NULL,
NULL);
dev->vram_size = (1024 << 10);
dev->vram = calloc(dev->vram_size, 1);
dev->changedvram = calloc((dev->vram_size >> 12) + 1, 1);
dev->vram_mask = dev->vram_size - 1;
video_inform(VIDEO_FLAG_TYPE_8514, &timing_gfxultra_isa);
mach->config1 = 0x01 | 0x02 | 0x20 | 0x08 | 0x80;
mach->config2 = 0x02;
svga->clock_gen = device_add(&ati18810_device);
}
dev->bpp = 0;
svga->getclock = ics2494_getclock;
dev->on[0] = 0;
dev->on[1] = 0;
dev->ext_pitch = 1024;
dev->ext_crt_pitch = 0x80;
dev->accel_bpp = 8;
svga->force_old_addr = 1;
svga->miscout = 1;
svga->bpp = 8;
svga->packed_chain4 = 1;
dev->rowoffset = 0x80;
io_sethandler(0x01ce, 2, mach_in, NULL, NULL, mach_out, NULL, NULL, mach);
io_sethandler(0x03c0, 32, mach_in, NULL, NULL, mach_out, NULL, NULL, mach);
io_sethandler(0x02ea, 4, mach_in, NULL, NULL, mach_out, NULL, NULL, mach);
mach_io_set(mach);
if ((dev->local & 0xff) >= 0x02) {
svga->decode_mask = (4 << 20) - 1;
mach->cursor_col_1 = 0xff;
mach->ext_cur_col_1_r = 0xff;
mach->ext_cur_col_1_g = 0xff;
if (mach->vlb_bus)
ati_eeprom_load(&mach->eeprom, "mach32_vlb.nvr", 1);
else if (mach->mca_bus) {
ati_eeprom_load(&mach->eeprom, "mach32_mca.nvr", 1);
mem_mapping_disable(&mach->bios_rom.mapping);
mem_mapping_disable(&mach->bios_rom2.mapping);
mach->pos_regs[0] = 0x89;
mach->pos_regs[1] = 0x80;
mca_add(mach_mca_read, mach_mca_write, mach_mca_feedb, mach_mca_reset, mach);
} else if (mach->pci_bus) {
ati_eeprom_load(&mach->eeprom, "mach32_pci.nvr", 1);
if (mach->has_bios) {
mem_mapping_disable(&mach->bios_rom.mapping);
pci_add_card(PCI_ADD_NORMAL, mach32_pci_read, mach32_pci_write, mach, &mach->pci_slot);
} else
pci_add_card(PCI_ADD_VIDEO, mach32_pci_read, mach32_pci_write, mach, &mach->pci_slot);
mach->pci_regs[PCI_REG_COMMAND] = 0x83;
mach->pci_regs[0x30] = 0x00;
mach->pci_regs[0x32] = 0x0c;
mach->pci_regs[0x33] = 0x00;
} else
ati_eeprom_load(&mach->eeprom, "mach32.nvr", 1);
} else
ati_eeprom_load_mach8(&mach->eeprom, "mach8.nvr");
return mach;
}
#ifdef ATI_8514_ULTRA
void
ati8514_init(svga_t *svga, void *ext8514, void *dev8514)
{
mach_t *mach = (mach_t *) ext8514;
ibm8514_t *dev = (ibm8514_t *) dev8514;
dev->on[0] = 0;
dev->on[1] = 0;
dev->ext_pitch = 1024;
dev->ext_crt_pitch = 0x80;
dev->accel_bpp = 8;
dev->rowoffset = 0x80;
dev->hdisp = 1024;
dev->vdisp = 768;
io_sethandler(0x02ea, 4, ati8514_in, NULL, NULL, ati8514_out, NULL, NULL, svga);
ati8514_io_set(svga);
mach->mca_bus = !!(dev->type & DEVICE_MCA);
if (mach->mca_bus)
mach->config1 = 0x02 | 0x04 | 0x08 | 0x20 | 0x80;
else
mach->config1 = 0x02 | 0x08 | 0x20 | 0x80;
mach->config2 = 0x01 | 0x02;
}
#endif
static int
mach8_vga_available(void)
{
return rom_present(BIOS_MACH8_VGA_ROM_PATH);
}
static int
mach32_isa_available(void)
{
return rom_present(BIOS_MACH32_ISA_ROM_PATH);
}
static int
mach32_vlb_available(void)
{
return rom_present(BIOS_MACH32_VLB_ROM_PATH);
}
static int
mach32_mca_available(void)
{
return rom_present(BIOS_MACH32_MCA_ROM_PATH);
}
static int
mach32_pci_available(void)
{
return rom_present(BIOS_MACH32_PCI_ROM_PATH);
}
static void
mach_close(void *priv)
{
mach_t *mach = (mach_t *) priv;
svga_t *svga = &mach->svga;
ibm8514_t *dev = (ibm8514_t *) svga->dev8514;
if (dev) {
free(dev->vram);
free(dev->changedvram);
free(dev);
}
svga_close(svga);
free(mach);
}
static void
mach_speed_changed(void *priv)
{
mach_t *mach = (mach_t *) priv;
svga_t *svga = &mach->svga;
svga_recalctimings(svga);
}
static void
mach_force_redraw(void *priv)
{
mach_t *mach = (mach_t *) priv;
svga_t *svga = &mach->svga;
svga->fullchange = svga->monitor->mon_changeframecount;
}
// clang-format off
static const device_config_t mach32_config[] = {
{
.name = "memory",
.description = "Memory size",
.type = CONFIG_SELECTION,
.default_int = 2048,
.selection = {
{
.description = "512 KB",
.value = 512
},
{
.description = "1 MB",
.value = 1024
},
{
.description = "2 MB",
.value = 2048
},
{
.description = "4 MB",
.value = 4096
},
{
.description = ""
}
}
},
{
.type = CONFIG_END
}
};
// clang-format off
static const device_config_t mach32_pci_config[] = {
{
.name = "ramdac",
.description = "RAMDAC type",
.type = CONFIG_SELECTION,
.default_int = 0,
.selection = {
{
.description = "ATI 68860",
.value = 0
},
{
.description = "ATI 68875",
.value = 1
},
{
.description = ""
}
}
},
{
.name = "memory",
.description = "Memory size",
.type = CONFIG_SELECTION,
.default_int = 2048,
.selection = {
{
.description = "512 KB",
.value = 512
},
{
.description = "1 MB",
.value = 1024
},
{
.description = "2 MB",
.value = 2048
},
{
.description = "4 MB",
.value = 4096
},
{
.description = ""
}
}
},
{
.type = CONFIG_END
}
};
const device_t mach8_vga_isa_device = {
.name = "ATI Mach8 (ATI Graphics Ultra) (ISA)",
.internal_name = "mach8_vga_isa",
.flags = DEVICE_ISA,
.local = 1,
.init = mach8_init,
.close = mach_close,
.reset = NULL,
{ .available = mach8_vga_available },
.speed_changed = mach_speed_changed,
.force_redraw = mach_force_redraw,
.config = NULL
};
const device_t mach32_isa_device = {
.name = "ATI Mach32 (ISA)",
.internal_name = "mach32_isa",
.flags = DEVICE_ISA,
.local = 2,
.init = mach8_init,
.close = mach_close,
.reset = NULL,
{ .available = mach32_isa_available },
.speed_changed = mach_speed_changed,
.force_redraw = mach_force_redraw,
.config = mach32_config
};
const device_t mach32_vlb_device = {
.name = "ATI Mach32 (VLB)",
.internal_name = "mach32_vlb",
.flags = DEVICE_VLB,
.local = 2,
.init = mach8_init,
.close = mach_close,
.reset = NULL,
{ .available = mach32_vlb_available },
.speed_changed = mach_speed_changed,
.force_redraw = mach_force_redraw,
.config = mach32_config
};
const device_t mach32_mca_device = {
.name = "ATI Mach32 (MCA)",
.internal_name = "mach32_mca",
.flags = DEVICE_MCA,
.local = 2,
.init = mach8_init,
.close = mach_close,
.reset = NULL,
{ .available = mach32_mca_available },
.speed_changed = mach_speed_changed,
.force_redraw = mach_force_redraw,
.config = mach32_config
};
const device_t mach32_pci_device = {
.name = "ATI Mach32 (PCI)",
.internal_name = "mach32_pci",
.flags = DEVICE_PCI,
.local = 2,
.init = mach8_init,
.close = mach_close,
.reset = NULL,
{ .available = mach32_pci_available },
.speed_changed = mach_speed_changed,
.force_redraw = mach_force_redraw,
.config = mach32_pci_config
};
const device_t mach32_onboard_pci_device = {
.name = "ATI Mach32 (PCI) On-Board",
.internal_name = "mach32_pci_onboard",
.flags = DEVICE_PCI,
.local = 2 | 0x100,
.init = mach8_init,
.close = mach_close,
.reset = NULL,
{ .available = NULL },
.speed_changed = mach_speed_changed,
.force_redraw = mach_force_redraw,
.config = mach32_pci_config
};
``` | /content/code_sandbox/src/video/vid_ati_mach8.c | c | 2016-06-25T22:29:10 | 2024-08-16T19:09:21 | 86Box | 86Box/86Box | 2,616 | 74,236 |
```c
/*
* 86Box A hypervisor and IBM PC system emulator that specializes in
* running old operating systems and software designed for IBM
* PC systems and compatibles from 1981 through fairly recent
* system designs based on the PCI bus.
*
* This file is part of the 86Box distribution.
*
* Generic SVGA handling.
*
* This is intended to be used by another SVGA driver,
* and not as a card in its own right.
*
*
*
* Authors: Sarah Walker, <path_to_url
* Miran Grca, <mgrca8@gmail.com>
*
*/
#include <inttypes.h>
#include <stdarg.h>
#include <stdio.h>
#include <stdint.h>
#include <stdlib.h>
#include <string.h>
#include <wchar.h>
#define HAVE_STDARG_H
#include <86box/86box.h>
#include "cpu.h"
#include <86box/device.h>
#include <86box/machine.h>
#include <86box/timer.h>
#include <86box/io.h>
#include <86box/pit.h>
#include <86box/mem.h>
#include <86box/rom.h>
#include <86box/plat.h>
#include <86box/ui.h>
#include <86box/video.h>
#include <86box/vid_8514a.h>
#include <86box/vid_xga.h>
#include <86box/vid_svga.h>
#include <86box/vid_svga_render.h>
#include <86box/vid_xga_device.h>
void svga_doblit(int wx, int wy, svga_t *svga);
void svga_poll(void *priv);
svga_t *svga_8514;
extern int cyc_total;
extern uint8_t edatlookup[4][4];
uint8_t svga_rotate[8][256];
/*Primary SVGA device. As multiple video cards are not yet supported this is the
only SVGA device.*/
static svga_t *svga_pri;
int vga_on;
#ifdef ENABLE_SVGA_LOG
int svga_do_log = ENABLE_SVGA_LOG;
static void
svga_log(const char *fmt, ...)
{
va_list ap;
if (svga_do_log) {
va_start(ap, fmt);
pclog_ex(fmt, ap);
va_end(ap);
}
}
#else
# define svga_log(fmt, ...)
#endif
svga_t *
svga_get_pri(void)
{
return svga_pri;
}
void
svga_set_override(svga_t *svga, int val)
{
if (svga->override && !val)
svga->fullchange = svga->monitor->mon_changeframecount;
svga->override = val;
#ifdef OVERRIDE_OVERSCAN
if (!val) {
/* Override turned off, restore overscan X and Y per the CRTC. */
svga->monitor->mon_overscan_y = (svga->rowcount + 1) << 1;
if (svga->monitor->mon_overscan_y < 16)
svga->monitor->mon_overscan_y = 16;
svga->monitor->mon_overscan_x = (svga->seqregs[1] & 1) ? 16 : 18;
if (svga->seqregs[1] & 8)
svga->monitor->mon_overscan_x <<= 1;
} else
svga->monitor->mon_overscan_x = svga->monitor->mon_overscan_y = 16;
/* Override turned off, fix overcan X and Y to 16. */
#endif
}
void
svga_out(uint16_t addr, uint8_t val, void *priv)
{
svga_t *svga = (svga_t *) priv;
ibm8514_t *dev = (ibm8514_t *) svga->dev8514;
xga_t *xga = (xga_t *) svga->xga;
uint8_t o;
uint8_t index;
uint8_t pal4to16[16] = { 0, 7, 0x38, 0x3f, 0, 3, 4, 0x3f, 0, 2, 4, 0x3e, 0, 3, 5, 0x3f };
if (!dev && (addr >= 0x2ea) && (addr <= 0x2ed))
return;
if (addr >= 0x3c6 && addr <= 0x3c9)
svga_log("VGA OUT addr=%03x, val=%02x.\n", addr, val);
switch (addr) {
case 0x2ea:
dev->dac_mask = val;
break;
case 0x2eb:
case 0x2ec:
dev->dac_pos = 0;
dev->dac_status = addr & 0x03;
dev->dac_addr = (val + (addr & 0x01)) & 0xff;
break;
case 0x2ed:
svga->fullchange = svga->monitor->mon_changeframecount;
switch (dev->dac_pos) {
case 0:
dev->dac_r = val;
dev->dac_pos++;
break;
case 1:
dev->dac_g = val;
dev->dac_pos++;
break;
case 2:
index = dev->dac_addr & 0xff;
dev->dac_b = val;
svga->vgapal[index].r = dev->dac_r;
svga->vgapal[index].g = dev->dac_g;
svga->vgapal[index].b = dev->dac_b;
if (svga->ramdac_type == RAMDAC_8BIT)
dev->pallook[index] = makecol32(svga->vgapal[index].r, svga->vgapal[index].g, svga->vgapal[index].b);
else
dev->pallook[index] = makecol32(video_6to8[svga->vgapal[index].r & 0x3f], video_6to8[svga->vgapal[index].g & 0x3f], video_6to8[svga->vgapal[index].b & 0x3f]);
dev->dac_pos = 0;
dev->dac_addr = (dev->dac_addr + 1) & 0xff;
break;
default:
break;
}
break;
case 0x3c0:
case 0x3c1:
if (!svga->attrff) {
svga->attraddr = val & 0x1f;
if ((val & 0x20) != svga->attr_palette_enable) {
svga->fullchange = 3;
svga->attr_palette_enable = val & 0x20;
svga_recalctimings(svga);
}
} else {
if ((svga->attraddr == 0x13) && (svga->attrregs[0x13] != val))
svga->fullchange = svga->monitor->mon_changeframecount;
o = svga->attrregs[svga->attraddr & 0x1f];
svga->attrregs[svga->attraddr & 0x1f] = val;
if (svga->attraddr < 0x10)
svga->fullchange = svga->monitor->mon_changeframecount;
if ((svga->attraddr == 0x10) || (svga->attraddr == 0x14) || (svga->attraddr < 0x10)) {
for (int c = 0; c < 0x10; c++) {
if (svga->attrregs[0x10] & 0x80)
svga->egapal[c] = (svga->attrregs[c] & 0xf) | ((svga->attrregs[0x14] & 0xf) << 4);
else if (svga->ati_4color)
svga->egapal[c] = pal4to16[(c & 0x03) | ((val >> 2) & 0xc)];
else
svga->egapal[c] = (svga->attrregs[c] & 0x3f) | ((svga->attrregs[0x14] & 0xc) << 4);
}
svga->fullchange = svga->monitor->mon_changeframecount;
}
/* Recalculate timings on change of attribute register 0x11
(overscan border color) too. */
if (svga->attraddr == 0x10) {
if (o != val)
svga_recalctimings(svga);
} else if (svga->attraddr == 0x11) {
svga->overscan_color = svga->pallook[svga->attrregs[0x11]];
if (o != val)
svga_recalctimings(svga);
} else if (svga->attraddr == 0x12) {
if ((val & 0xf) != svga->plane_mask)
svga->fullchange = svga->monitor->mon_changeframecount;
svga->plane_mask = val & 0xf;
}
}
svga->attrff ^= 1;
break;
case 0x3c2:
svga->miscout = val;
svga->vidclock = val & 4;
io_removehandler(0x03a0, 0x0020, svga->video_in, NULL, NULL, svga->video_out, NULL, NULL, svga->priv);
if (!(val & 1))
io_sethandler(0x03a0, 0x0020, svga->video_in, NULL, NULL, svga->video_out, NULL, NULL, svga->priv);
svga_recalctimings(svga);
break;
case 0x3c3:
if (xga_active && xga)
xga->on = (val & 0x01) ? 0 : 1;
if (ibm8514_active && dev) {
dev->on[0] = (val & 0x01) ? 0 : 1;
if (dev->local & 0xff)
dev->on[1] = dev->on[0];
}
svga_log("3C3: VGA ON = %d.\n", val & 0x01);
vga_on = val & 0x01;
svga_recalctimings(svga);
break;
case 0x3c4:
svga->seqaddr = val;
break;
case 0x3c5:
if (svga->seqaddr > 0xf)
return;
o = svga->seqregs[svga->seqaddr & 0xf];
svga->seqregs[svga->seqaddr & 0xf] = val;
if (o != val && (svga->seqaddr & 0xf) == 1)
svga_recalctimings(svga);
switch (svga->seqaddr & 0xf) {
case 1:
if (svga->scrblank && !(val & 0x20))
svga->fullchange = 3;
svga->scrblank = (svga->scrblank & ~0x20) | (val & 0x20);
svga_recalctimings(svga);
break;
case 2:
svga->writemask = val & 0xf;
break;
case 3:
svga->charsetb = (((val >> 2) & 3) * 0x10000) + 2;
svga->charseta = ((val & 3) * 0x10000) + 2;
if (val & 0x10)
svga->charseta += 0x8000;
if (val & 0x20)
svga->charsetb += 0x8000;
break;
case 4:
svga->chain2_write = !(val & 4);
svga->chain4 = (svga->chain4 & ~8) | (val & 8);
svga->fast = (svga->gdcreg[8] == 0xff && !(svga->gdcreg[3] & 0x18) && !svga->gdcreg[1]) && ((svga->chain4 && (svga->packed_chain4 || svga->force_old_addr)) || svga->fb_only) && !(svga->adv_flags & FLAG_ADDR_BY8);
break;
default:
break;
}
break;
case 0x3c6:
svga->dac_mask = val;
break;
case 0x3c7:
case 0x3c8:
svga->dac_pos = 0;
svga->dac_status = addr & 0x03;
svga->dac_addr = (val + (addr & 0x01)) & 255;
break;
case 0x3c9:
if (svga->adv_flags & FLAG_RAMDAC_SHIFT)
val <<= 2;
svga->fullchange = svga->monitor->mon_changeframecount;
switch (svga->dac_pos) {
case 0:
svga->dac_r = val;
svga->dac_pos++;
break;
case 1:
svga->dac_g = val;
svga->dac_pos++;
break;
case 2:
index = svga->dac_addr & 255;
svga->dac_b = val;
svga->vgapal[index].r = svga->dac_r;
svga->vgapal[index].g = svga->dac_g;
svga->vgapal[index].b = svga->dac_b;
if (svga->ramdac_type == RAMDAC_8BIT)
svga->pallook[index] = makecol32(svga->vgapal[index].r, svga->vgapal[index].g, svga->vgapal[index].b);
else
svga->pallook[index] = makecol32(video_6to8[svga->vgapal[index].r & 0x3f], video_6to8[svga->vgapal[index].g & 0x3f], video_6to8[svga->vgapal[index].b & 0x3f]);
svga->dac_pos = 0;
svga->dac_addr = (svga->dac_addr + 1) & 255;
break;
default:
break;
}
break;
case 0x3ce:
svga->gdcaddr = val;
break;
case 0x3cf:
o = svga->gdcreg[svga->gdcaddr & 15];
switch (svga->gdcaddr & 15) {
case 2:
svga->colourcompare = val;
break;
case 4:
svga->readplane = val & 3;
break;
case 5:
svga->writemode = val & 3;
svga->readmode = val & 8;
svga->chain2_read = val & 0x10;
break;
case 6:
if ((svga->gdcreg[6] & 0xc) != (val & 0xc)) {
switch (val & 0xc) {
case 0x0: /*128k at A0000*/
mem_mapping_set_addr(&svga->mapping, 0xa0000, 0x20000);
svga->banked_mask = 0xffff;
break;
case 0x4: /*64k at A0000*/
mem_mapping_set_addr(&svga->mapping, 0xa0000, 0x10000);
svga->banked_mask = 0xffff;
break;
case 0x8: /*32k at B0000*/
mem_mapping_set_addr(&svga->mapping, 0xb0000, 0x08000);
svga->banked_mask = 0x7fff;
break;
case 0xC: /*32k at B8000*/
mem_mapping_set_addr(&svga->mapping, 0xb8000, 0x08000);
svga->banked_mask = 0x7fff;
break;
default:
break;
}
}
break;
case 7:
svga->colournocare = val;
break;
default:
break;
}
svga->gdcreg[svga->gdcaddr & 15] = val;
svga->fast = (svga->gdcreg[8] == 0xff && !(svga->gdcreg[3] & 0x18) && !svga->gdcreg[1]) && ((svga->chain4 && (svga->packed_chain4 || svga->force_old_addr)) || svga->fb_only);
if (((svga->gdcaddr & 15) == 5 && (val ^ o) & 0x70) || ((svga->gdcaddr & 15) == 6 && (val ^ o) & 1))
svga_recalctimings(svga);
break;
case 0x3da:
svga->fcr = val;
break;
default:
break;
}
}
uint8_t
svga_in(uint16_t addr, void *priv)
{
svga_t *svga = (svga_t *) priv;
ibm8514_t *dev = (ibm8514_t *) svga->dev8514;
uint8_t index;
uint8_t ret = 0xff;
if (!dev && (addr >= 0x2ea) && (addr <= 0x2ed))
return ret;
switch (addr) {
case 0x2ea:
ret = dev->dac_mask;
break;
case 0x2eb:
ret = dev->dac_status;
break;
case 0x2ec:
ret = dev->dac_addr;
break;
case 0x2ed:
index = (dev->dac_addr - 1) & 0xff;
switch (dev->dac_pos) {
case 0:
dev->dac_pos++;
if (svga->ramdac_type == RAMDAC_8BIT)
ret = svga->vgapal[index].r;
else
ret = svga->vgapal[index].r & 0x3f;
break;
case 1:
dev->dac_pos++;
if (svga->ramdac_type == RAMDAC_8BIT)
ret = svga->vgapal[index].g;
else
ret = svga->vgapal[index].g & 0x3f;
break;
case 2:
dev->dac_pos = 0;
dev->dac_addr = (dev->dac_addr + 1) & 0xff;
if (svga->ramdac_type == RAMDAC_8BIT)
ret = svga->vgapal[index].b;
else
ret = svga->vgapal[index].b & 0x3f;
break;
default:
break;
}
break;
case 0x3c0:
ret = svga->attraddr | svga->attr_palette_enable;
break;
case 0x3c1:
ret = svga->attrregs[svga->attraddr];
break;
case 0x3c2:
if ((svga->vgapal[0].r + svga->vgapal[0].g + svga->vgapal[0].b) >= 0x4e)
ret = 0;
else
ret = 0x10;
break;
case 0x3c3:
ret = vga_on;
break;
case 0x3c4:
ret = svga->seqaddr;
break;
case 0x3c5:
ret = svga->seqregs[svga->seqaddr & 0x0f];
break;
case 0x3c6:
ret = svga->dac_mask;
break;
case 0x3c7:
ret = svga->dac_status;
break;
case 0x3c8:
ret = svga->dac_addr;
break;
case 0x3c9:
index = (svga->dac_addr - 1) & 255;
switch (svga->dac_pos) {
case 0:
svga->dac_pos++;
if (svga->ramdac_type == RAMDAC_8BIT)
ret = svga->vgapal[index].r;
else
ret = svga->vgapal[index].r & 0x3f;
break;
case 1:
svga->dac_pos++;
if (svga->ramdac_type == RAMDAC_8BIT)
ret = svga->vgapal[index].g;
else
ret = svga->vgapal[index].g & 0x3f;
break;
case 2:
svga->dac_pos = 0;
svga->dac_addr = (svga->dac_addr + 1) & 255;
if (svga->ramdac_type == RAMDAC_8BIT)
ret = svga->vgapal[index].b;
else
ret = svga->vgapal[index].b & 0x3f;
break;
default:
break;
}
if (svga->adv_flags & FLAG_RAMDAC_SHIFT)
ret >>= 2;
break;
case 0x3ca:
ret = svga->fcr;
break;
case 0x3cc:
ret = svga->miscout;
break;
case 0x3ce:
ret = svga->gdcaddr;
break;
case 0x3cf:
/* The spec says GDC addresses 0xF8 to 0xFB return the latch. */
switch (svga->gdcaddr) {
case 0xf8:
ret = svga->latch.b[0];
break;
case 0xf9:
ret = svga->latch.b[1];
break;
case 0xfa:
ret = svga->latch.b[2];
break;
case 0xfb:
ret = svga->latch.b[3];
break;
default:
ret = svga->gdcreg[svga->gdcaddr & 0xf];
break;
}
break;
case 0x3da:
svga->attrff = 0;
if (svga->cgastat & 0x01)
svga->cgastat &= ~0x30;
else
svga->cgastat ^= 0x30;
ret = svga->cgastat;
if ((svga->fcr & 0x08) && svga->dispon)
ret |= 0x08;
break;
default:
break;
}
if ((addr >= 0x3c6) && (addr <= 0x3c9))
svga_log("VGA IN addr=%03x, temp=%02x.\n", addr, ret);
return ret;
}
void
svga_set_ramdac_type(svga_t *svga, int type)
{
ibm8514_t *dev = (ibm8514_t *) svga->dev8514;
xga_t *xga = (xga_t *) svga->xga;
if (svga->ramdac_type != type) {
svga->ramdac_type = type;
for (int c = 0; c < 256; c++) {
if (ibm8514_active && dev) {
if (svga->ramdac_type == RAMDAC_8BIT)
dev->pallook[c] = makecol32(svga->vgapal[c].r, svga->vgapal[c].g, svga->vgapal[c].b);
else
dev->pallook[c] = makecol32((svga->vgapal[c].r & 0x3f) * 4,
(svga->vgapal[c].g & 0x3f) * 4,
(svga->vgapal[c].b & 0x3f) * 4);
}
if (xga_active && xga) {
if (svga->ramdac_type == RAMDAC_8BIT)
xga->pallook[c] = makecol32(svga->vgapal[c].r, svga->vgapal[c].g, svga->vgapal[c].b);
else
xga->pallook[c] = makecol32((svga->vgapal[c].r & 0x3f) * 4,
(svga->vgapal[c].g & 0x3f) * 4,
(svga->vgapal[c].b & 0x3f) * 4);
}
if (svga->ramdac_type == RAMDAC_8BIT)
svga->pallook[c] = makecol32(svga->vgapal[c].r, svga->vgapal[c].g, svga->vgapal[c].b);
else
svga->pallook[c] = makecol32((svga->vgapal[c].r & 0x3f) * 4,
(svga->vgapal[c].g & 0x3f) * 4,
(svga->vgapal[c].b & 0x3f) * 4);
}
}
}
void
svga_recalctimings(svga_t *svga)
{
ibm8514_t *dev = (ibm8514_t *) svga->dev8514;
double crtcconst;
double _dispontime;
double _dispofftime;
double disptime;
double crtcconst8514 = 0.0;
double _dispontime8514 = 0.0;
double _dispofftime8514 = 0.0;
double disptime8514 = 0.0;
#ifdef ENABLE_SVGA_LOG
int vsyncend;
int vblankend;
int hdispstart;
int hdispend;
int hsyncstart;
int hsyncend;
#endif
svga->vtotal = svga->crtc[6];
svga->dispend = svga->crtc[0x12];
svga->vsyncstart = svga->crtc[0x10];
svga->split = svga->crtc[0x18];
svga->vblankstart = svga->crtc[0x15];
if (svga->crtc[7] & 1)
svga->vtotal |= 0x100;
if (svga->crtc[7] & 32)
svga->vtotal |= 0x200;
svga->vtotal += 2;
if (svga->crtc[7] & 2)
svga->dispend |= 0x100;
if (svga->crtc[7] & 64)
svga->dispend |= 0x200;
svga->dispend++;
if (svga->crtc[7] & 4)
svga->vsyncstart |= 0x100;
if (svga->crtc[7] & 128)
svga->vsyncstart |= 0x200;
svga->vsyncstart++;
if (svga->crtc[7] & 0x10)
svga->split |= 0x100;
if (svga->crtc[9] & 0x40)
svga->split |= 0x200;
svga->split++;
if (svga->crtc[7] & 0x08)
svga->vblankstart |= 0x100;
if (svga->crtc[9] & 0x20)
svga->vblankstart |= 0x200;
svga->vblankstart++;
svga->hdisp = svga->crtc[1];
svga->hdisp++;
svga->htotal = svga->crtc[0];
/* +5 has been verified by Sergi to be correct - +6 must have been an off by one error. */
svga->htotal += 5; /*+5 is required for Tyrian*/
svga->rowoffset = svga->crtc[0x13];
svga->clock = (svga->vidclock) ? VGACONST2 : VGACONST1;
svga->lowres = !!(svga->attrregs[0x10] & 0x40);
svga->interlace = 0;
svga->ma_latch = ((svga->crtc[0xc] << 8) | svga->crtc[0xd]) + ((svga->crtc[8] & 0x60) >> 5);
svga->ca_adj = 0;
svga->rowcount = svga->crtc[9] & 0x1f;
svga->hdisp_time = svga->hdisp;
svga->render = svga_render_blank;
if (!svga->scrblank && (svga->crtc[0x17] & 0x80) && svga->attr_palette_enable) {
/* TODO: In case of bug reports, disable 9-dots-wide character clocks in graphics modes. */
if (!(svga->gdcreg[6] & 1) && !(svga->attrregs[0x10] & 1)) {
if (svga->seqregs[1] & 8)
svga->hdisp *= (svga->seqregs[1] & 1) ? 16 : 18;
else
svga->hdisp *= (svga->seqregs[1] & 1) ? 8 : 9;
} else {
if (svga->seqregs[1] & 8)
svga->hdisp *= 16;
else
svga->hdisp *= 8;
}
if (!(svga->gdcreg[6] & 1) && !(svga->attrregs[0x10] & 1)) { /*Text mode*/
if (svga->seqregs[1] & 8) { /*40 column*/
svga->render = svga_render_text_40;
} else {
svga->render = svga_render_text_80;
}
svga->hdisp_old = svga->hdisp;
} else {
svga->hdisp_old = svga->hdisp;
if ((svga->bpp <= 8) || ((svga->gdcreg[5] & 0x60) <= 0x20)) {
if ((svga->gdcreg[5] & 0x60) == 0x00) {
if (svga->seqregs[1] & 8) /*Low res (320)*/
svga->render = svga_render_4bpp_lowres;
else
svga->render = svga_render_4bpp_highres;
} else if ((svga->gdcreg[5] & 0x60) == 0x20) {
if (svga->seqregs[1] & 8) { /*Low res (320)*/
svga->render = svga_render_2bpp_lowres;
svga_log("2 bpp low res\n");
} else
svga->render = svga_render_2bpp_highres;
} else {
svga->map8 = svga->pallook;
if (svga->lowres) /*Low res (320)*/
svga->render = svga_render_8bpp_lowres;
else
svga->render = svga_render_8bpp_highres;
}
} else {
switch (svga->gdcreg[5] & 0x60) {
case 0x40:
case 0x60: /*256+ colours*/
switch (svga->bpp) {
case 15:
if (svga->lowres)
svga->render = svga_render_15bpp_lowres;
else
svga->render = svga_render_15bpp_highres;
break;
case 16:
if (svga->lowres)
svga->render = svga_render_16bpp_lowres;
else
svga->render = svga_render_16bpp_highres;
break;
case 17:
if (svga->lowres)
svga->render = svga_render_15bpp_mix_lowres;
else
svga->render = svga_render_15bpp_mix_highres;
break;
case 24:
if (svga->lowres)
svga->render = svga_render_24bpp_lowres;
else
svga->render = svga_render_24bpp_highres;
break;
case 32:
if (svga->lowres)
svga->render = svga_render_32bpp_lowres;
else
svga->render = svga_render_32bpp_highres;
break;
default:
break;
}
break;
default:
break;
}
}
}
}
svga->linedbl = svga->crtc[9] & 0x80;
svga->char_width = (svga->seqregs[1] & 1) ? 8 : 9;
svga->monitor->mon_overscan_y = (svga->rowcount + 1) << 1;
if (svga->monitor->mon_overscan_y < 16)
svga->monitor->mon_overscan_y = 16;
if (!(svga->gdcreg[6] & 1) && !(svga->attrregs[0x10] & 1)) {
svga->monitor->mon_overscan_x = (svga->seqregs[1] & 1) ? 16 : 18;
if (svga->seqregs[1] & 8)
svga->monitor->mon_overscan_x <<= 1;
} else
svga->monitor->mon_overscan_x = 16;
svga->hblankstart = svga->crtc[2];
svga->hblank_end_val = (svga->crtc[3] & 0x1f) | ((svga->crtc[5] & 0x80) ? 0x20 : 0x00);
svga->hblank_end_mask = 0x0000003f;
svga_log("htotal = %i, hblankstart = %i, hblank_end_val = %02X\n",
svga->htotal, svga->hblankstart, svga->hblank_end_val);
if (!svga->scrblank && svga->attr_palette_enable) {
/* TODO: In case of bug reports, disable 9-dots-wide character clocks in graphics modes. */
if (!(svga->gdcreg[6] & 1) && !(svga->attrregs[0x10] & 1)) {
if (svga->seqregs[1] & 8)
svga->dots_per_clock = ((svga->seqregs[1] & 1) ? 16 : 18);
else
svga->dots_per_clock = ((svga->seqregs[1] & 1) ? 8 : 9);
} else {
if (svga->seqregs[1] & 8)
svga->dots_per_clock = 16;
else
svga->dots_per_clock = 8;
}
} else
svga->dots_per_clock = 1;
svga->multiplier = 1.0;
if (svga->recalctimings_ex)
svga->recalctimings_ex(svga);
if (ibm8514_active && (svga->dev8514 != NULL)) {
if ((dev->local & 0xff) == 0x00)
ibm8514_recalctimings(svga);
}
if (xga_active && (svga->xga != NULL))
xga_recalctimings(svga);
if (!svga->hoverride) {
uint32_t dot = svga->hblankstart;
uint32_t adj_dot = svga->hblankstart;
/* Verified with both the Voodoo 3 and the S3 cards: compare 7 bits if bit 7 is set,
otherwise compare 6 bits. */
uint32_t eff_mask = (svga->hblank_end_val & ~0x0000003f) ? svga->hblank_end_mask : 0x0000003f;
svga->hblank_sub = 0;
svga_log("HDISP=%d, CRTC1+1=%d, Blank: %04i-%04i, Total: %04i, Mask: %02X, ADJ_DOT=%04i.\n", svga->hdisp, svga->crtc[1] + 1, svga->hblankstart, svga->hblank_end_val,
svga->htotal, eff_mask, adj_dot);
while (adj_dot < (svga->htotal << 1)) {
if (dot == svga->htotal)
dot = 0;
if (adj_dot >= svga->htotal)
svga->hblank_sub++;
svga_log("Loop: adjdot=%d, htotal=%d, dotmask=%02x, hblankendvalmask=%02x, blankendval=%02x.\n", adj_dot, svga->htotal, dot & eff_mask, svga->hblank_end_val & eff_mask, svga->hblank_end_val);
if ((dot & eff_mask) == (svga->hblank_end_val & eff_mask))
break;
dot++;
adj_dot++;
}
svga->hdisp -= (svga->hblank_sub * svga->dots_per_clock);
}
#ifdef TBD
if (ibm8514_active && (svga->dev8514 != NULL)) {
if (dev->on[0] || dev->on[1]) {
uint32_t dot8514 = dev->h_blankstart;
uint32_t adj_dot8514 = dev->h_blankstart;
uint32_t eff_mask8514 = 0x0000003f;
dev->hblank_sub = 0;
while (adj_dot8514 < (dev->h_total << 1)) {
if (dot8514 == dev->h_total)
dot8514 = 0;
if (adj_dot8514 >= dev->h_total)
dev->hblank_sub++;
if ((dot8514 & eff_mask8514) == (dev->h_blank_end_val & eff_mask8514))
break;
dot8514++;
adj_dot8514++;
}
dev->h_disp -= dev->hblank_sub;
}
}
#endif
if (svga->hdisp >= 2048)
svga->monitor->mon_overscan_x = 0;
svga->y_add = (svga->monitor->mon_overscan_y >> 1);
svga->x_add = (svga->monitor->mon_overscan_x >> 1);
if (svga->vblankstart < svga->dispend) {
svga_log("DISPEND > VBLANKSTART.\n");
svga->dispend = svga->vblankstart;
}
crtcconst = svga->clock * svga->char_width;
if (ibm8514_active && (svga->dev8514 != NULL)) {
if (dev->on[0] || dev->on[1])
crtcconst8514 = svga->clock8514;
}
#ifdef ENABLE_SVGA_LOG
vsyncend = (svga->vsyncstart & 0xfffffff0) | (svga->crtc[0x11] & 0x0f);
if (vsyncend <= svga->vsyncstart)
vsyncend += 0x00000010;
vblankend = (svga->vblankstart & 0xffffff80) | (svga->crtc[0x16] & 0x7f);
if (vblankend <= svga->vblankstart)
vblankend += 0x00000080;
hdispstart = ((svga->crtc[3] >> 5) & 3);
hdispend = svga->crtc[1] + 1;
hsyncstart = svga->crtc[4] + ((svga->crtc[5] >> 5) & 3) + 1;
hsyncend = (hsyncstart & 0xffffffe0) | (svga->crtc[5] & 0x1f);
if (hsyncend <= hsyncstart)
hsyncend += 0x00000020;
#endif
svga_log("Last scanline in the vertical period: %i\n"
"First scanline after the last of active display: %i\n"
"First scanline with vertical retrace asserted: %i\n"
"First scanline after the last with vertical retrace asserted: %i\n"
"First scanline of blanking: %i\n"
"First scanline after the last of blanking: %i\n"
"\n"
"Last character in the horizontal period: %i\n"
"First character of active display: %i\n"
"First character after the last of active display: %i\n"
"First character with horizontal retrace asserted: %i\n"
"First character after the last with horizontal retrace asserted: %i\n"
"First character of blanking: %i\n"
"First character after the last of blanking: %i\n"
"\n"
"\n",
svga->vtotal, svga->dispend, svga->vsyncstart, vsyncend,
svga->vblankstart, vblankend,
svga->htotal, hdispstart, hdispend, hsyncstart, hsyncend,
svga->hblankstart, svga->hblankend);
disptime = svga->htotal * svga->multiplier;
_dispontime = svga->hdisp_time;
if (ibm8514_active && (svga->dev8514 != NULL)) {
if (dev->on[0] || dev->on[1]) {
disptime8514 = dev->h_total ? dev->h_total : TIMER_USEC;
_dispontime8514 = dev->hdisped;
}
}
if (svga->seqregs[1] & 8) {
disptime *= 2;
_dispontime *= 2;
}
_dispofftime = disptime - _dispontime;
_dispontime *= crtcconst;
_dispofftime *= crtcconst;
svga->dispontime = (uint64_t) (_dispontime);
svga->dispofftime = (uint64_t) (_dispofftime);
if (svga->dispontime < TIMER_USEC)
svga->dispontime = TIMER_USEC;
if (svga->dispofftime < TIMER_USEC)
svga->dispofftime = TIMER_USEC;
if (ibm8514_active && (svga->dev8514 != NULL)) {
if (dev->on[0] || dev->on[1]) {
_dispofftime8514 = disptime8514 - _dispontime8514;
_dispontime8514 *= crtcconst8514;
_dispofftime8514 *= crtcconst8514;
dev->dispontime = (uint64_t) (_dispontime8514);
dev->dispofftime = (uint64_t) (_dispofftime8514);
if (dev->dispontime < TIMER_USEC)
dev->dispontime = TIMER_USEC;
if (dev->dispofftime < TIMER_USEC)
dev->dispofftime = TIMER_USEC;
svga_log("IBM 8514/A poll.\n");
timer_set_callback(&svga->timer, ibm8514_poll);
} else {
svga_log("SVGA Poll.\n");
timer_set_callback(&svga->timer, svga_poll);
}
}
if (!svga->force_old_addr)
svga_recalc_remap_func(svga);
/* Inform the user interface of any DPMS mode changes. */
if (svga->dpms) {
if (!svga->dpms_ui) {
/* Make sure to black out the entire screen to avoid lingering image. */
int y_add = enable_overscan ? svga->monitor->mon_overscan_y : 0;
int x_add = enable_overscan ? svga->monitor->mon_overscan_x : 0;
int y_start = enable_overscan ? 0 : (svga->monitor->mon_overscan_y >> 1);
int x_start = enable_overscan ? 0 : (svga->monitor->mon_overscan_x >> 1);
video_wait_for_buffer_monitor(svga->monitor_index);
memset(svga->monitor->target_buffer->dat, 0, svga->monitor->target_buffer->w * svga->monitor->target_buffer->h * 4);
video_blit_memtoscreen_monitor(x_start, y_start, svga->monitor->mon_xsize + x_add, svga->monitor->mon_ysize + y_add, svga->monitor_index);
video_wait_for_buffer_monitor(svga->monitor_index);
svga->dpms_ui = 1;
ui_sb_set_text_w(plat_get_string(STRING_MONITOR_SLEEP));
}
} else if (svga->dpms_ui) {
svga->dpms_ui = 0;
ui_sb_set_text_w(NULL);
}
}
static void
svga_do_render(svga_t *svga)
{
/* Always render a blank screen and nothing else while in DPMS mode. */
if (svga->dpms) {
svga_render_blank(svga);
return;
}
if (!svga->override) {
svga->render(svga);
svga->x_add = (svga->monitor->mon_overscan_x >> 1);
svga_render_overscan_left(svga);
svga_render_overscan_right(svga);
svga->x_add = (svga->monitor->mon_overscan_x >> 1) - svga->scrollcache;
}
if (svga->overlay_on) {
if (!svga->override && svga->overlay_draw)
svga->overlay_draw(svga, svga->displine + svga->y_add);
svga->overlay_on--;
if (svga->overlay_on && svga->interlace)
svga->overlay_on--;
}
if (svga->dac_hwcursor_on) {
if (!svga->override && svga->dac_hwcursor_draw)
svga->dac_hwcursor_draw(svga, (svga->displine + svga->y_add + ((svga->dac_hwcursor_latch.y >= 0) ? 0 : svga->dac_hwcursor_latch.y)) & 2047);
svga->dac_hwcursor_on--;
if (svga->dac_hwcursor_on && svga->interlace)
svga->dac_hwcursor_on--;
}
if (svga->hwcursor_on) {
if (!svga->override && svga->hwcursor_draw)
svga->hwcursor_draw(svga, (svga->displine + svga->y_add + ((svga->hwcursor_latch.y >= 0) ? 0 : svga->hwcursor_latch.y)) & 2047);
svga->hwcursor_on--;
if (svga->hwcursor_on && svga->interlace)
svga->hwcursor_on--;
}
}
void
svga_poll(void *priv)
{
svga_t *svga = (svga_t *) priv;
xga_t *xga = (xga_t *) svga->xga;
uint32_t x;
uint32_t blink_delay;
int wx;
int wy;
int ret;
int old_ma;
if (!svga->override) {
if (xga_active && xga && xga->on) {
if ((xga->disp_cntl_2 & 7) >= 2) {
xga_poll(xga, svga);
return;
}
}
}
if (!svga->linepos) {
if (svga->displine == ((svga->hwcursor_latch.y < 0) ? 0 : svga->hwcursor_latch.y) && svga->hwcursor_latch.ena) {
svga->hwcursor_on = svga->hwcursor_latch.cur_ysize - svga->hwcursor_latch.yoff;
svga->hwcursor_oddeven = 0;
}
if (svga->displine == (((svga->hwcursor_latch.y < 0) ? 0 : svga->hwcursor_latch.y) + 1) && svga->hwcursor_latch.ena && svga->interlace) {
svga->hwcursor_on = svga->hwcursor_latch.cur_ysize - (svga->hwcursor_latch.yoff + 1);
svga->hwcursor_oddeven = 1;
}
if (svga->displine == ((svga->dac_hwcursor_latch.y < 0) ? 0 : svga->dac_hwcursor_latch.y) && svga->dac_hwcursor_latch.ena) {
svga->dac_hwcursor_on = svga->dac_hwcursor_latch.cur_ysize - svga->dac_hwcursor_latch.yoff;
svga->dac_hwcursor_oddeven = 0;
}
if (svga->displine == (((svga->dac_hwcursor_latch.y < 0) ? 0 : svga->dac_hwcursor_latch.y) + 1) && svga->dac_hwcursor_latch.ena && svga->interlace) {
svga->dac_hwcursor_on = svga->dac_hwcursor_latch.cur_ysize - (svga->dac_hwcursor_latch.yoff + 1);
svga->dac_hwcursor_oddeven = 1;
}
if (svga->displine == svga->overlay_latch.y && svga->overlay_latch.ena) {
svga->overlay_on = svga->overlay_latch.cur_ysize - svga->overlay_latch.yoff;
svga->overlay_oddeven = 0;
}
if (svga->displine == svga->overlay_latch.y + 1 && svga->overlay_latch.ena && svga->interlace) {
svga->overlay_on = svga->overlay_latch.cur_ysize - svga->overlay_latch.yoff;
svga->overlay_oddeven = 1;
}
timer_advance_u64(&svga->timer, svga->dispofftime);
svga->cgastat |= 1;
svga->linepos = 1;
if (svga->dispon) {
svga->hdisp_on = 1;
svga->ma &= svga->vram_display_mask;
if (svga->firstline == 2000) {
svga->firstline = svga->displine;
video_wait_for_buffer_monitor(svga->monitor_index);
}
if (svga->hwcursor_on || svga->dac_hwcursor_on || svga->overlay_on) {
svga->changedvram[svga->ma >> 12] = svga->changedvram[(svga->ma >> 12) + 1] = svga->interlace ? 3 : 2;
}
if (svga->vertical_linedbl) {
old_ma = svga->ma;
svga->displine <<= 1;
svga->y_add <<= 1;
svga_do_render(svga);
svga->displine++;
svga->ma = old_ma;
svga_do_render(svga);
svga->y_add >>= 1;
svga->displine >>= 1;
} else
svga_do_render(svga);
if (svga->lastline < svga->displine)
svga->lastline = svga->displine;
}
svga->displine++;
if (svga->interlace)
svga->displine++;
if ((svga->cgastat & 8) && ((svga->displine & 15) == (svga->crtc[0x11] & 15)) && svga->vslines)
svga->cgastat &= ~8;
svga->vslines++;
if (svga->displine > 2000)
svga->displine = 0;
} else {
timer_advance_u64(&svga->timer, svga->dispontime);
if (svga->dispon)
svga->cgastat &= ~1;
svga->hdisp_on = 0;
svga->linepos = 0;
if ((svga->sc == (svga->crtc[11] & 31)) || (svga->sc == svga->rowcount))
svga->con = 0;
if (svga->dispon) {
/* TODO: Verify real hardware behaviour for out-of-range fine vertical scroll
- S3 Trio64V2/DX: sc == rowcount, wrapping 5-bit counter. */
if (svga->linedbl && !svga->linecountff) {
svga->linecountff = 1;
svga->ma = svga->maback;
} else if (svga->sc == svga->rowcount) {
svga->linecountff = 0;
svga->sc = 0;
svga->maback += (svga->adv_flags & FLAG_NO_SHIFT3) ? svga->rowoffset : (svga->rowoffset << 3);
if (svga->interlace)
svga->maback += (svga->adv_flags & FLAG_NO_SHIFT3) ? svga->rowoffset : (svga->rowoffset << 3);
svga->maback &= svga->vram_display_mask;
svga->ma = svga->maback;
} else {
svga->linecountff = 0;
svga->sc++;
svga->sc &= 0x1f;
svga->ma = svga->maback;
}
}
svga->hsync_divisor ^= 1;
if (svga->hsync_divisor && (svga->crtc[0x17] & 4))
return;
svga->vc++;
svga->vc &= 0x7ff;
if (svga->vc == svga->split) {
ret = 1;
if (svga->line_compare)
ret = svga->line_compare(svga);
if (ret) {
if (svga->interlace && svga->oddeven)
svga->ma = svga->maback = (svga->rowoffset << 1) + svga->hblank_sub;
else
svga->ma = svga->maback = svga->hblank_sub;
svga->ma = (svga->ma << 2);
svga->maback = (svga->maback << 2);
svga->sc = 0;
if (svga->attrregs[0x10] & 0x20) {
svga->scrollcache = 0;
svga->x_add = (svga->monitor->mon_overscan_x >> 1);
}
}
}
if (svga->vc == svga->dispend) {
if (svga->vblank_start)
svga->vblank_start(svga);
svga->dispon = 0;
blink_delay = (svga->crtc[11] & 0x60) >> 5;
if (svga->crtc[10] & 0x20)
svga->cursoron = 0;
else if (blink_delay == 2)
svga->cursoron = ((svga->blink % 96) >= 48);
else
svga->cursoron = svga->blink & (16 + (16 * blink_delay));
if (!(svga->blink & 15))
svga->fullchange = 2;
svga->blink = (svga->blink + 1) & 0x7f;
for (x = 0; x < ((svga->vram_mask + 1) >> 12); x++) {
if (svga->changedvram[x])
svga->changedvram[x]--;
}
if (svga->fullchange)
svga->fullchange--;
}
if (svga->vc == svga->vsyncstart) {
svga->dispon = 0;
svga->cgastat |= 8;
x = svga->hdisp;
if (svga->interlace && !svga->oddeven)
svga->lastline++;
if (svga->interlace && svga->oddeven)
svga->firstline--;
wx = x;
if (!svga->override) {
if (svga->vertical_linedbl) {
wy = (svga->lastline - svga->firstline) << 1;
svga->vdisp = wy + 1;
svga_doblit(wx, wy, svga);
} else {
wy = svga->lastline - svga->firstline;
svga->vdisp = wy + 1;
svga_doblit(wx, wy, svga);
}
}
svga->firstline = 2000;
svga->lastline = 0;
svga->firstline_draw = 2000;
svga->lastline_draw = 0;
svga->oddeven ^= 1;
svga->monitor->mon_changeframecount = svga->interlace ? 3 : 2;
svga->vslines = 0;
if (svga->interlace && svga->oddeven)
svga->ma = svga->maback = svga->ma_latch + (svga->rowoffset << 1) + svga->hblank_sub;
else
svga->ma = svga->maback = svga->ma_latch + svga->hblank_sub;
svga->ca = ((svga->crtc[0xe] << 8) | svga->crtc[0xf]) + ((svga->crtc[0xb] & 0x60) >> 5) + svga->ca_adj;
if (!(svga->adv_flags & FLAG_NO_SHIFT3)) {
svga->ma = (svga->ma << 2);
svga->maback = (svga->maback << 2);
}
svga->ca = (svga->ca << 2);
if (svga->vsync_callback)
svga->vsync_callback(svga);
}
#if 0
if (svga->vc == lines_num) {
#endif
if (svga->vc == svga->vtotal) {
svga->vc = 0;
svga->sc = (svga->crtc[0x8] & 0x1f);
svga->dispon = 1;
svga->displine = (svga->interlace && svga->oddeven) ? 1 : 0;
svga->scrollcache = (svga->attrregs[0x13] & 0x0f);
if (!(svga->gdcreg[6] & 1) && !(svga->attrregs[0x10] & 1)) { /*Text mode*/
if (svga->seqregs[1] & 1)
svga->scrollcache &= 0x07;
else {
svga->scrollcache++;
if (svga->scrollcache > 8)
svga->scrollcache = 0;
}
} else if ((svga->render == svga_render_2bpp_lowres) || (svga->render == svga_render_2bpp_highres) || (svga->render == svga_render_4bpp_lowres) || (svga->render == svga_render_4bpp_highres))
svga->scrollcache &= 0x07;
else
svga->scrollcache = (svga->scrollcache & 0x06) >> 1;
if ((svga->seqregs[1] & 8) || (svga->render == svga_render_8bpp_lowres))
svga->scrollcache <<= 1;
svga->x_add = (svga->monitor->mon_overscan_x >> 1) - svga->scrollcache;
svga->linecountff = 0;
svga->hwcursor_on = 0;
svga->hwcursor_latch = svga->hwcursor;
svga->dac_hwcursor_on = 0;
svga->dac_hwcursor_latch = svga->dac_hwcursor;
svga->overlay_on = 0;
svga->overlay_latch = svga->overlay;
}
if (svga->sc == (svga->crtc[10] & 31))
svga->con = 1;
}
}
uint32_t
svga_conv_16to32(struct svga_t *svga, uint16_t color, uint8_t bpp)
{
return (bpp == 15) ? video_15to32[color] : video_16to32[color];
}
int
svga_init(const device_t *info, svga_t *svga, void *priv, int memsize,
void (*recalctimings_ex)(struct svga_t *svga),
uint8_t (*video_in)(uint16_t addr, void *priv),
void (*video_out)(uint16_t addr, uint8_t val, void *priv),
void (*hwcursor_draw)(struct svga_t *svga, int displine),
void (*overlay_draw)(struct svga_t *svga, int displine))
{
int e;
svga->priv = priv;
svga->monitor_index = monitor_index_global;
svga->monitor = &monitors[svga->monitor_index];
for (int c = 0; c < 256; c++) {
e = c;
for (int d = 0; d < 8; d++) {
svga_rotate[d][c] = e;
e = (e >> 1) | ((e & 1) ? 0x80 : 0);
}
}
svga->readmode = 0;
svga->attrregs[0x11] = 0;
svga->overscan_color = 0x000000;
svga->monitor->mon_overscan_x = 16;
svga->monitor->mon_overscan_y = 32;
svga->x_add = 8;
svga->y_add = 16;
svga->crtc[0] = 63;
svga->crtc[6] = 255;
svga->dispontime = 1000ULL << 32;
svga->dispofftime = 1000ULL << 32;
svga->bpp = 8;
svga->vram = calloc(memsize + 8, 1);
svga->vram_max = memsize;
svga->vram_display_mask = svga->vram_mask = memsize - 1;
svga->decode_mask = 0x7fffff;
svga->changedvram = calloc((memsize >> 12) + 1, 1);
svga->recalctimings_ex = recalctimings_ex;
svga->video_in = video_in;
svga->video_out = video_out;
svga->hwcursor_draw = hwcursor_draw;
svga->overlay_draw = overlay_draw;
svga->conv_16to32 = svga_conv_16to32;
svga->render = svga_render_blank;
svga->hwcursor.cur_xsize = svga->hwcursor.cur_ysize = 32;
svga->dac_hwcursor.cur_xsize = svga->dac_hwcursor.cur_ysize = 32;
svga->translate_address = NULL;
svga->ksc5601_english_font_type = 0;
vga_on = 1;
if ((info->flags & DEVICE_PCI) || (info->flags & DEVICE_VLB) || (info->flags & DEVICE_MCA)) {
mem_mapping_add(&svga->mapping, 0xa0000, 0x20000,
svga_read, svga_readw, svga_readl,
svga_write, svga_writew, svga_writel,
NULL, MEM_MAPPING_EXTERNAL, svga);
} else if ((info->flags & DEVICE_ISA) && (info->flags & DEVICE_AT)) {
mem_mapping_add(&svga->mapping, 0xa0000, 0x20000,
svga_read, svga_readw, NULL,
svga_write, svga_writew, NULL,
NULL, MEM_MAPPING_EXTERNAL, svga);
} else {
mem_mapping_add(&svga->mapping, 0xa0000, 0x20000,
svga_read, NULL, NULL,
svga_write, NULL, NULL,
NULL, MEM_MAPPING_EXTERNAL, svga);
}
timer_add(&svga->timer, svga_poll, svga, 1);
svga_pri = svga;
svga->ramdac_type = RAMDAC_6BIT;
svga->map8 = svga->pallook;
return 0;
}
void
svga_close(svga_t *svga)
{
free(svga->changedvram);
free(svga->vram);
if (svga->dpms_ui)
ui_sb_set_text_w(NULL);
svga_pri = NULL;
}
static uint32_t
svga_decode_addr(svga_t *svga, uint32_t addr, int write)
{
int memory_map_mode = (svga->gdcreg[6] >> 2) & 3;
addr &= 0x1ffff;
switch (memory_map_mode) {
case 0:
break;
case 1:
if (addr >= 0x10000)
return 0xffffffff;
break;
case 2:
addr -= 0x10000;
if (addr >= 0x8000)
return 0xffffffff;
break;
default:
case 3:
addr -= 0x18000;
if (addr >= 0x8000)
return 0xffffffff;
break;
}
if (memory_map_mode <= 1) {
if (write)
addr += svga->write_bank;
else
addr += svga->read_bank;
}
return addr;
}
static __inline void
svga_write_common(uint32_t addr, uint8_t val, uint8_t linear, void *priv)
{
svga_t *svga = (svga_t *) priv;
xga_t *xga = (xga_t *) svga->xga;
int writemask2 = svga->writemask;
int reset_wm = 0;
latch_t vall;
uint8_t wm = svga->writemask;
uint8_t count;
uint8_t i;
if (svga->adv_flags & FLAG_ADDR_BY8)
writemask2 = svga->seqregs[2];
cycles -= svga->monitor->mon_video_timing_write_b;
if (!linear) {
if (xga_active && xga) {
if (((xga->op_mode & 7) >= 4) && (xga->aperture_cntl >= 1)) {
if (val == 0xa5) { /*Memory size test of XGA*/
xga->test = val;
if (addr == 0xa0001)
xga->a5_test = 1;
else if (addr == 0xafffe)
xga->a5_test = 2;
xga->on = 0;
vga_on = 1;
xga->disp_cntl_2 = 0;
svga_log("XGA test1 addr = %05x.\n", addr);
return;
} else if (val == 0x5a) {
xga->test = val;
xga->on = 0;
vga_on = 1;
xga->disp_cntl_2 = 0;
svga_log("XGA test2 addr = %05x.\n", addr);
return;
} else if ((addr == 0xa0000) || (addr == 0xa0010)) {
addr += xga->write_bank;
xga->vram[addr & xga->vram_mask] = val;
svga_log("XGA Linear endian reverse write, val = %02x, addr = %05x, banked mask = %04x.\n", val, addr, svga->banked_mask);
if (!xga->a5_test)
xga->linear_endian_reverse = 1;
return;
}
} else {
xga->on = 0;
vga_on = 1;
}
}
addr = svga_decode_addr(svga, addr, 1);
if (addr == 0xffffffff)
return;
}
if (!(svga->gdcreg[6] & 1))
svga->fullchange = 2;
if ((svga->adv_flags & FLAG_ADDR_BY16) && (svga->writemode == 4 || svga->writemode == 5))
addr <<= 4;
else if ((svga->adv_flags & FLAG_ADDR_BY8) && (svga->writemode < 4))
addr <<= 3;
else if (((svga->chain4 && (svga->packed_chain4 || svga->force_old_addr)) || svga->fb_only) && (svga->writemode < 4)) {
writemask2 = 1 << (addr & 3);
addr &= ~3;
} else if (svga->chain4 && (svga->writemode < 4)) {
writemask2 = 1 << (addr & 3);
if (!linear)
addr &= ~3;
addr = ((addr & 0xfffc) << 2) | ((addr & 0x30000) >> 14) | (addr & ~0x3ffff);
} else if (svga->chain2_write) {
writemask2 &= ~0xa;
if (addr & 1)
writemask2 <<= 1;
addr &= ~1;
addr <<= 2;
} else
addr <<= 2;
addr &= svga->decode_mask;
if (svga->translate_address)
addr = svga->translate_address(addr, priv);
if (addr >= svga->vram_max)
return;
addr &= svga->vram_mask;
svga->changedvram[addr >> 12] = svga->monitor->mon_changeframecount;
count = 4;
if (svga->adv_flags & FLAG_LATCH8)
count = 8;
/* Undocumented Cirrus Logic behavior: The datasheet says that, with EXT_WRITE and FLAG_ADDR_BY8, the write mask only
changes meaning in write modes 4 and 5, as well as write mode 1. In reality, however, all other write modes are also
affected, as proven by the Windows 3.1 CL-GD 5422/4 drivers in 8bpp modes. */
switch (svga->writemode) {
case 0:
val = ((val >> (svga->gdcreg[3] & 7)) | (val << (8 - (svga->gdcreg[3] & 7))));
if ((svga->gdcreg[8] == 0xff) && !(svga->gdcreg[3] & 0x18) && (!svga->gdcreg[1] || svga->set_reset_disabled)) {
for (i = 0; i < count; i++) {
if ((svga->adv_flags & FLAG_EXT_WRITE) && (svga->adv_flags & FLAG_ADDR_BY8)) {
if (writemask2 & (0x80 >> i))
svga->vram[addr | i] = val;
} else {
if (writemask2 & (1 << i))
svga->vram[addr | i] = val;
}
}
return;
} else {
for (i = 0; i < count; i++) {
if (svga->gdcreg[1] & (1 << i))
vall.b[i] = !!(svga->gdcreg[0] & (1 << i)) * 0xff;
else
vall.b[i] = val;
}
}
break;
case 1:
for (i = 0; i < count; i++) {
if ((svga->adv_flags & FLAG_EXT_WRITE) && (svga->adv_flags & FLAG_ADDR_BY8)) {
if (writemask2 & (0x80 >> i))
svga->vram[addr | i] = svga->latch.b[i];
} else {
if (writemask2 & (1 << i))
svga->vram[addr | i] = svga->latch.b[i];
}
}
return;
case 2:
for (i = 0; i < count; i++)
vall.b[i] = !!(val & (1 << i)) * 0xff;
if (!(svga->gdcreg[3] & 0x18) && (!svga->gdcreg[1] || svga->set_reset_disabled)) {
for (i = 0; i < count; i++) {
if ((svga->adv_flags & FLAG_EXT_WRITE) && (svga->adv_flags & FLAG_ADDR_BY8)) {
if (writemask2 & (0x80 >> i))
svga->vram[addr | i] = (vall.b[i] & svga->gdcreg[8]) | (svga->latch.b[i] & ~svga->gdcreg[8]);
} else {
if (writemask2 & (1 << i))
svga->vram[addr | i] = (vall.b[i] & svga->gdcreg[8]) | (svga->latch.b[i] & ~svga->gdcreg[8]);
}
}
return;
}
break;
case 3:
val = ((val >> (svga->gdcreg[3] & 7)) | (val << (8 - (svga->gdcreg[3] & 7))));
wm = svga->gdcreg[8];
svga->gdcreg[8] &= val;
for (i = 0; i < count; i++)
vall.b[i] = !!(svga->gdcreg[0] & (1 << i)) * 0xff;
reset_wm = 1;
break;
default:
if (svga->ven_write)
svga->ven_write(svga, val, addr);
return;
}
switch (svga->gdcreg[3] & 0x18) {
case 0x00: /* Set */
for (i = 0; i < count; i++) {
if ((svga->adv_flags & FLAG_EXT_WRITE) && (svga->adv_flags & FLAG_ADDR_BY8)) {
if (writemask2 & (0x80 >> i))
svga->vram[addr | i] = (vall.b[i] & svga->gdcreg[8]) | (svga->latch.b[i] & ~svga->gdcreg[8]);
} else {
if (writemask2 & (1 << i))
svga->vram[addr | i] = (vall.b[i] & svga->gdcreg[8]) | (svga->latch.b[i] & ~svga->gdcreg[8]);
}
}
break;
case 0x08: /* AND */
for (i = 0; i < count; i++) {
if ((svga->adv_flags & FLAG_EXT_WRITE) && (svga->adv_flags & FLAG_ADDR_BY8)) {
if (writemask2 & (0x80 >> i))
svga->vram[addr | i] = (vall.b[i] | ~svga->gdcreg[8]) & svga->latch.b[i];
} else {
if (writemask2 & (1 << i))
svga->vram[addr | i] = (vall.b[i] | ~svga->gdcreg[8]) & svga->latch.b[i];
}
}
break;
case 0x10: /* OR */
for (i = 0; i < count; i++) {
if ((svga->adv_flags & FLAG_EXT_WRITE) && (svga->adv_flags & FLAG_ADDR_BY8)) {
if (writemask2 & (0x80 >> i))
svga->vram[addr | i] = (vall.b[i] & svga->gdcreg[8]) | svga->latch.b[i];
} else {
if (writemask2 & (1 << i))
svga->vram[addr | i] = (vall.b[i] & svga->gdcreg[8]) | svga->latch.b[i];
}
}
break;
case 0x18: /* XOR */
for (i = 0; i < count; i++) {
if ((svga->adv_flags & FLAG_EXT_WRITE) && (svga->adv_flags & FLAG_ADDR_BY8)) {
if (writemask2 & (0x80 >> i))
svga->vram[addr | i] = (vall.b[i] & svga->gdcreg[8]) ^ svga->latch.b[i];
} else {
if (writemask2 & (1 << i))
svga->vram[addr | i] = (vall.b[i] & svga->gdcreg[8]) ^ svga->latch.b[i];
}
}
break;
default:
break;
}
if (reset_wm)
svga->gdcreg[8] = wm;
}
static __inline uint8_t
svga_read_common(uint32_t addr, uint8_t linear, void *priv)
{
svga_t *svga = (svga_t *) priv;
xga_t *xga = (xga_t *) svga->xga;
uint32_t latch_addr = 0;
int readplane = svga->readplane;
uint8_t count;
uint8_t temp;
uint8_t ret;
if (svga->adv_flags & FLAG_ADDR_BY8)
readplane = svga->gdcreg[4] & 7;
cycles -= svga->monitor->mon_video_timing_read_b;
if (!linear) {
if (xga_active && xga) {
if (((xga->op_mode & 7) >= 4) && (xga->aperture_cntl >= 1)) {
if (xga->test == 0xa5) { /*Memory size test of XGA*/
if (addr == 0xa0001) {
ret = xga->test;
xga->on = 1;
vga_on = 0;
} else if ((addr == 0xa0000) && (xga->a5_test == 1)) { /*This is required by XGAKIT to pass the memory test*/
svga_log("A5 test bank = %x.\n", addr);
addr += xga->read_bank;
ret = xga->vram[addr & xga->vram_mask];
} else {
ret = xga->test;
xga->on = 1;
vga_on = 0;
}
svga_log("A5 read: XGA ON = %d, addr = %05x, ret = %02x, test1 = %x.\n", xga->on, addr, ret, xga->a5_test);
return ret;
} else if (xga->test == 0x5a) {
ret = xga->test;
xga->on = 1;
vga_on = 0;
svga_log("5A read: XGA ON = %d.\n", xga->on);
return ret;
} else if ((addr == 0xa0000) || (addr == 0xa0010)) {
addr += xga->read_bank;
return xga->vram[addr & xga->vram_mask];
}
} else {
xga->on = 0;
vga_on = 1;
}
}
addr = svga_decode_addr(svga, addr, 0);
if (addr == 0xffffffff)
return 0xff;
}
count = 2;
if (svga->adv_flags & FLAG_LATCH8)
count = 3;
latch_addr = (addr << count) & svga->decode_mask;
count = (1 << count);
if (svga->adv_flags & FLAG_ADDR_BY16)
addr <<= 4;
else if (svga->adv_flags & FLAG_ADDR_BY8)
addr <<= 3;
else if ((svga->chain4 && (svga->packed_chain4 || svga->force_old_addr)) || svga->fb_only) {
addr &= svga->decode_mask;
if (svga->translate_address)
addr = svga->translate_address(addr, priv);
if (addr >= svga->vram_max)
return 0xff;
latch_addr = (addr & svga->vram_mask) & ~3;
for (uint8_t i = 0; i < count; i++)
svga->latch.b[i] = svga->vram[latch_addr | i];
return svga->vram[addr & svga->vram_mask];
} else if (svga->chain4 && !svga->force_old_addr) {
readplane = addr & 3;
addr = ((addr & 0xfffc) << 2) | ((addr & 0x30000) >> 14) | (addr & ~0x3ffff);
} else if (svga->chain2_read) {
readplane = (readplane & 2) | (addr & 1);
addr &= ~1;
addr <<= 2;
} else
addr <<= 2;
addr &= svga->decode_mask;
if (svga->translate_address) {
latch_addr = svga->translate_address(latch_addr, priv);
addr = svga->translate_address(addr, priv);
}
/* standard VGA latched access */
if (latch_addr >= svga->vram_max) {
for (uint8_t i = 0; i < count; i++)
svga->latch.b[i] = 0xff;
} else {
latch_addr &= svga->vram_mask;
for (uint8_t i = 0; i < count; i++)
svga->latch.b[i] = svga->vram[latch_addr | i];
}
if (addr >= svga->vram_max)
return 0xff;
addr &= svga->vram_mask;
if (svga->readmode) {
temp = 0xff;
for (uint8_t pixel = 0; pixel < 8; pixel++) {
for (uint8_t plane = 0; plane < count; plane++) {
if (svga->colournocare & (1 << plane)) {
/* If we care about a plane, and the pixel has a mismatch on it, clear its bit. */
if (((svga->latch.b[plane] >> pixel) & 1) != ((svga->colourcompare >> plane) & 1))
temp &= ~(1 << pixel);
}
}
}
ret = temp;
} else
ret = svga->vram[addr | readplane];
return ret;
}
void
svga_write(uint32_t addr, uint8_t val, void *priv)
{
svga_write_common(addr, val, 0, priv);
}
void
svga_write_linear(uint32_t addr, uint8_t val, void *priv)
{
svga_write_common(addr, val, 1, priv);
}
uint8_t
svga_read(uint32_t addr, void *priv)
{
return svga_read_common(addr, 0, priv);
}
uint8_t
svga_read_linear(uint32_t addr, void *priv)
{
return svga_read_common(addr, 1, priv);
}
void
svga_doblit(int wx, int wy, svga_t *svga)
{
int y_add;
int x_add;
int y_start;
int x_start;
int bottom;
uint32_t *p;
int i;
int j;
int xs_temp;
int ys_temp;
y_add = enable_overscan ? svga->monitor->mon_overscan_y : 0;
x_add = enable_overscan ? svga->monitor->mon_overscan_x : 0;
y_start = enable_overscan ? 0 : (svga->monitor->mon_overscan_y >> 1);
x_start = enable_overscan ? 0 : (svga->monitor->mon_overscan_x >> 1);
bottom = (svga->monitor->mon_overscan_y >> 1);
if (svga->vertical_linedbl) {
y_add <<= 1;
y_start <<= 1;
bottom <<= 1;
}
if ((wx <= 0) || (wy <= 0))
return;
if (svga->vertical_linedbl)
svga->y_add <<= 1;
xs_temp = wx;
ys_temp = wy + 1;
if (svga->vertical_linedbl)
ys_temp++;
if (xs_temp < 64)
xs_temp = 640;
if (ys_temp < 32)
ys_temp = 200;
if ((svga->crtc[0x17] & 0x80) && ((xs_temp != svga->monitor->mon_xsize) || (ys_temp != svga->monitor->mon_ysize) || video_force_resize_get_monitor(svga->monitor_index))) {
/* Screen res has changed.. fix up, and let them know. */
svga->monitor->mon_xsize = xs_temp;
svga->monitor->mon_ysize = ys_temp;
if ((svga->monitor->mon_xsize > 1984) || (svga->monitor->mon_ysize > 2016)) {
/* 2048x2048 is the biggest safe render texture, to account for overscan,
we suppress overscan starting from x 1984 and y 2016. */
x_add = 0;
y_add = 0;
suppress_overscan = 1;
} else
suppress_overscan = 0;
/* Block resolution changes while in DPMS mode to avoid getting a bogus
screen width (320). We're already rendering a blank screen anyway. */
if (!svga->dpms)
set_screen_size_monitor(svga->monitor->mon_xsize + x_add, svga->monitor->mon_ysize + y_add, svga->monitor_index);
if (video_force_resize_get_monitor(svga->monitor_index))
video_force_resize_set_monitor(0, svga->monitor_index);
}
if ((wx >= 160) && ((wy + 1) >= 120)) {
/* Draw (overscan_size - scroll size) lines of overscan on top and bottom. */
for (i = 0; i < svga->y_add; i++) {
p = &svga->monitor->target_buffer->line[i & 0x7ff][0];
for (j = 0; j < (svga->monitor->mon_xsize + x_add); j++)
p[j] = svga->dpms ? 0 : svga->overscan_color;
}
for (i = 0; i < bottom; i++) {
p = &svga->monitor->target_buffer->line[(svga->monitor->mon_ysize + svga->y_add + i) & 0x7ff][0];
for (j = 0; j < (svga->monitor->mon_xsize + x_add); j++)
p[j] = svga->dpms ? 0 : svga->overscan_color;
}
}
video_blit_memtoscreen_monitor(x_start, y_start, svga->monitor->mon_xsize + x_add, svga->monitor->mon_ysize + y_add, svga->monitor_index);
if (svga->vertical_linedbl)
svga->vertical_linedbl >>= 1;
}
void
svga_writeb_linear(uint32_t addr, uint8_t val, void *priv)
{
svga_t *svga = (svga_t *) priv;
if (!svga->fast) {
svga_write_linear(addr, val, priv);
return;
}
addr &= svga->decode_mask;
if (addr >= svga->vram_max)
return;
addr &= svga->vram_mask;
svga->changedvram[addr >> 12] = svga->monitor->mon_changeframecount;
svga->vram[addr] = val;
}
void
svga_writew_common(uint32_t addr, uint16_t val, uint8_t linear, void *priv)
{
svga_t *svga = (svga_t *) priv;
if (!svga->fast) {
svga_write_common(addr, val, linear, priv);
svga_write_common(addr + 1, val >> 8, linear, priv);
return;
}
cycles -= svga->monitor->mon_video_timing_write_w;
if (!linear) {
addr = svga_decode_addr(svga, addr, 1);
if (addr == 0xffffffff)
return;
}
addr &= svga->decode_mask;
if (svga->translate_address) {
uint32_t addr2 = svga->translate_address(addr, priv);
if (addr2 < svga->vram_max) {
svga->vram[addr2 & svga->vram_mask] = val & 0xff;
svga->changedvram[addr2 >> 12] = svga->monitor->mon_changeframecount;
}
addr2 = svga->translate_address(addr + 1, priv);
if (addr2 < svga->vram_max) {
svga->vram[addr2 & svga->vram_mask] = (val >> 8) & 0xff;
svga->changedvram[addr2 >> 12] = svga->monitor->mon_changeframecount;
}
return;
}
if (addr >= svga->vram_max)
return;
addr &= svga->vram_mask;
svga->changedvram[addr >> 12] = svga->monitor->mon_changeframecount;
*(uint16_t *) &svga->vram[addr] = val;
}
void
svga_writew(uint32_t addr, uint16_t val, void *priv)
{
svga_writew_common(addr, val, 0, priv);
}
void
svga_writew_linear(uint32_t addr, uint16_t val, void *priv)
{
svga_writew_common(addr, val, 1, priv);
}
void
svga_writel_common(uint32_t addr, uint32_t val, uint8_t linear, void *priv)
{
svga_t *svga = (svga_t *) priv;
if (!svga->fast) {
svga_write_common(addr, val, linear, priv);
svga_write_common(addr + 1, val >> 8, linear, priv);
svga_write_common(addr + 2, val >> 16, linear, priv);
svga_write_common(addr + 3, val >> 24, linear, priv);
return;
}
cycles -= svga->monitor->mon_video_timing_write_l;
if (!linear) {
addr = svga_decode_addr(svga, addr, 1);
if (addr == 0xffffffff)
return;
}
addr &= svga->decode_mask;
if (svga->translate_address) {
uint32_t addr2 = svga->translate_address(addr, priv);
if (addr2 < svga->vram_max) {
svga->vram[addr2 & svga->vram_mask] = val & 0xff;
svga->changedvram[addr2 >> 12] = svga->monitor->mon_changeframecount;
}
addr2 = svga->translate_address(addr + 1, priv);
if (addr2 < svga->vram_max) {
svga->vram[addr2 & svga->vram_mask] = (val >> 8) & 0xff;
svga->changedvram[addr2 >> 12] = svga->monitor->mon_changeframecount;
}
addr2 = svga->translate_address(addr + 2, priv);
if (addr2 < svga->vram_max) {
svga->vram[addr2 & svga->vram_mask] = (val >> 16) & 0xff;
svga->changedvram[addr2 >> 12] = svga->monitor->mon_changeframecount;
}
addr2 = svga->translate_address(addr + 3, priv);
if (addr2 < svga->vram_max) {
svga->vram[addr2 & svga->vram_mask] = (val >> 24) & 0xff;
svga->changedvram[addr2 >> 12] = svga->monitor->mon_changeframecount;
}
return;
}
if (addr >= svga->vram_max)
return;
addr &= svga->vram_mask;
svga->changedvram[addr >> 12] = svga->monitor->mon_changeframecount;
*(uint32_t *) &svga->vram[addr] = val;
}
void
svga_writel(uint32_t addr, uint32_t val, void *priv)
{
svga_writel_common(addr, val, 0, priv);
}
void
svga_writel_linear(uint32_t addr, uint32_t val, void *priv)
{
svga_writel_common(addr, val, 1, priv);
}
uint8_t
svga_readb_linear(uint32_t addr, void *priv)
{
const svga_t *svga = (svga_t *) priv;
if (!svga->fast)
return svga_read_linear(addr, priv);
addr &= svga->decode_mask;
if (addr >= svga->vram_max)
return 0xff;
return svga->vram[addr & svga->vram_mask];
}
uint16_t
svga_readw_common(uint32_t addr, uint8_t linear, void *priv)
{
svga_t *svga = (svga_t *) priv;
if (!svga->fast)
return svga_read_common(addr, linear, priv) | (svga_read_common(addr + 1, linear, priv) << 8);
cycles -= svga->monitor->mon_video_timing_read_w;
if (!linear) {
addr = svga_decode_addr(svga, addr, 0);
if (addr == 0xffffffff)
return 0xffff;
}
addr &= svga->decode_mask;
if (svga->translate_address) {
uint8_t val1 = 0xff;
uint8_t val2 = 0xff;
uint32_t addr2 = svga->translate_address(addr, priv);
if (addr2 < svga->vram_max)
val1 = svga->vram[addr2 & svga->vram_mask];
addr2 = svga->translate_address(addr + 1, priv);
if (addr2 < svga->vram_max)
val2 = svga->vram[addr2 & svga->vram_mask];
return (val2 << 8) | val1;
}
if (addr >= svga->vram_max)
return 0xffff;
return *(uint16_t *) &svga->vram[addr & svga->vram_mask];
}
uint16_t
svga_readw(uint32_t addr, void *priv)
{
return svga_readw_common(addr, 0, priv);
}
uint16_t
svga_readw_linear(uint32_t addr, void *priv)
{
return svga_readw_common(addr, 1, priv);
}
uint32_t
svga_readl_common(uint32_t addr, uint8_t linear, void *priv)
{
svga_t *svga = (svga_t *) priv;
if (!svga->fast)
return svga_read_common(addr, linear, priv) | (svga_read_common(addr + 1, linear, priv) << 8) | (svga_read_common(addr + 2, linear, priv) << 16) | (svga_read_common(addr + 3, linear, priv) << 24);
cycles -= svga->monitor->mon_video_timing_read_l;
if (!linear) {
addr = svga_decode_addr(svga, addr, 0);
if (addr == 0xffffffff)
return 0xffffffff;
}
addr &= svga->decode_mask;
if (svga->translate_address) {
uint8_t val1 = 0xff;
uint8_t val2 = 0xff;
uint8_t val3 = 0xff;
uint8_t val4 = 0xff;
uint32_t addr2 = svga->translate_address(addr, priv);
if (addr2 < svga->vram_max)
val1 = svga->vram[addr2 & svga->vram_mask];
addr2 = svga->translate_address(addr + 1, priv);
if (addr2 < svga->vram_max)
val2 = svga->vram[addr2 & svga->vram_mask];
addr2 = svga->translate_address(addr + 2, priv);
if (addr2 < svga->vram_max)
val3 = svga->vram[addr2 & svga->vram_mask];
addr2 = svga->translate_address(addr + 3, priv);
if (addr2 < svga->vram_max)
val4 = svga->vram[addr2 & svga->vram_mask];
return (val4 << 24) | (val3 << 16) | (val2 << 8) | val1;
}
if (addr >= svga->vram_max)
return 0xffffffff;
return *(uint32_t *) &svga->vram[addr & svga->vram_mask];
}
uint32_t
svga_readl(uint32_t addr, void *priv)
{
return svga_readl_common(addr, 0, priv);
}
uint32_t
svga_readl_linear(uint32_t addr, void *priv)
{
return svga_readl_common(addr, 1, priv);
}
``` | /content/code_sandbox/src/video/vid_svga.c | c | 2016-06-25T22:29:10 | 2024-08-16T19:09:21 | 86Box | 86Box/86Box | 2,616 | 22,989 |
```c
/*
* 86Box A hypervisor and IBM PC system emulator that specializes in
* running old operating systems and software designed for IBM
* PC systems and compatibles from 1981 through fairly recent
* system designs based on the PCI bus.
*
* This file is part of the 86Box distribution.
*
* STG1702 true colour RAMDAC emulation.
*
*
*
* Authors: Sarah Walker, <path_to_url
* Miran Grca, <mgrca8@gmail.com>
*
*/
#include <stdio.h>
#include <stdint.h>
#include <stdlib.h>
#include <string.h>
#include <wchar.h>
#include <86box/86box.h>
#include <86box/device.h>
#include <86box/mem.h>
#include <86box/timer.h>
#include <86box/video.h>
#include <86box/vid_svga.h>
#include <86box/plat_unused.h>
typedef struct stg_ramdac_t {
int magic_count, index;
uint8_t regs[256];
uint8_t command;
} stg_ramdac_t;
static int stg_state_read[2][8] = {
{1, 2, 3, 4, 0, 0, 0, 0},
{ 1, 2, 3, 4, 5, 6, 7, 7}
};
static int stg_state_write[8] = { 0, 0, 0, 0, 0, 6, 7, 7 };
void
stg_ramdac_set_bpp(svga_t *svga, stg_ramdac_t *ramdac)
{
if (ramdac->command & 0x8) {
switch (ramdac->regs[3]) {
default:
case 0:
case 5:
case 7:
svga->bpp = 8;
break;
case 1:
case 2:
case 8:
svga->bpp = 15;
break;
case 3:
case 6:
svga->bpp = 16;
break;
case 4:
case 9:
svga->bpp = 24;
break;
}
} else {
switch (ramdac->command >> 5) {
default:
case 0:
svga->bpp = 8;
break;
case 5:
svga->bpp = 15;
break;
case 6:
svga->bpp = 16;
break;
case 7:
svga->bpp = 24;
break;
}
}
svga_recalctimings(svga);
}
void
stg_ramdac_out(uint16_t addr, uint8_t val, void *priv, svga_t *svga)
{
stg_ramdac_t *ramdac = (stg_ramdac_t *) priv;
int didwrite;
int old;
switch (addr) {
case 0x3c6:
switch (ramdac->magic_count) {
/* 0 = PEL mask register */
case 0:
case 1:
case 2:
case 3:
break;
case 4: /* REG06 */
old = ramdac->command;
ramdac->command = val;
if ((old ^ val) & 8)
stg_ramdac_set_bpp(svga, ramdac);
else {
if ((old ^ val) & 0xE0)
stg_ramdac_set_bpp(svga, ramdac);
}
break;
case 5:
ramdac->index = (ramdac->index & 0xff00) | val;
break;
case 6:
ramdac->index = (ramdac->index & 0xff) | (val << 8);
break;
case 7:
if (ramdac->index < 0x100)
ramdac->regs[ramdac->index] = val;
if ((ramdac->index == 3) && (ramdac->command & 8))
stg_ramdac_set_bpp(svga, ramdac);
ramdac->index++;
break;
default:
break;
}
didwrite = (ramdac->magic_count >= 4);
ramdac->magic_count = stg_state_write[ramdac->magic_count & 7];
if (didwrite)
return;
break;
case 0x3c7:
case 0x3c8:
case 0x3c9:
ramdac->magic_count = 0;
break;
default:
break;
}
svga_out(addr, val, svga);
}
uint8_t
stg_ramdac_in(uint16_t addr, void *priv, svga_t *svga)
{
stg_ramdac_t *ramdac = (stg_ramdac_t *) priv;
uint8_t temp = 0xff;
switch (addr) {
case 0x3c6:
switch (ramdac->magic_count) {
case 0:
case 1:
case 2:
case 3:
temp = 0xff;
break;
case 4:
temp = ramdac->command;
break;
case 5:
temp = ramdac->index & 0xff;
break;
case 6:
temp = ramdac->index >> 8;
break;
case 7:
switch (ramdac->index) {
case 0:
temp = 0x44;
break;
case 1:
temp = 0x03;
break;
case 7:
temp = 0x88;
break;
default:
if (ramdac->index < 0x100)
temp = ramdac->regs[ramdac->index];
else
temp = 0xff;
break;
}
ramdac->index++;
break;
default:
break;
}
ramdac->magic_count = stg_state_read[(ramdac->command & 0x10) ? 1 : 0][ramdac->magic_count & 7];
return temp;
case 0x3c7:
case 0x3c8:
case 0x3c9:
ramdac->magic_count = 0;
break;
default:
break;
}
return svga_in(addr, svga);
}
float
stg_getclock(int clock, void *priv)
{
stg_ramdac_t *ramdac = (stg_ramdac_t *) priv;
float t;
int m;
int n;
int n2;
const uint16_t *c;
if (clock == 0)
return 25175000.0;
if (clock == 1)
return 28322000.0;
clock ^= 1; /*Clocks 2 and 3 seem to be reversed*/
c = (uint16_t *) &ramdac->regs[0x20 + (clock << 1)];
m = (*c & 0xff) + 2; /* B+2 */
n = ((*c >> 8) & 0x1f) + 2; /* N1+2 */
n2 = ((*c >> 13) & 0x07); /* D */
n2 = (1 << n2);
t = (14318184.0f * (float) m) / (float) (n * n2);
return t;
}
static void *
stg_ramdac_init(UNUSED(const device_t *info))
{
stg_ramdac_t *ramdac = (stg_ramdac_t *) malloc(sizeof(stg_ramdac_t));
memset(ramdac, 0, sizeof(stg_ramdac_t));
return ramdac;
}
static void
stg_ramdac_close(void *priv)
{
stg_ramdac_t *ramdac = (stg_ramdac_t *) priv;
if (ramdac)
free(ramdac);
}
const device_t stg_ramdac_device = {
.name = "SGS-Thompson STG170x RAMDAC",
.internal_name = "stg_ramdac",
.flags = 0,
.local = 0,
.init = stg_ramdac_init,
.close = stg_ramdac_close,
.reset = NULL,
{ .available = NULL },
.speed_changed = NULL,
.force_redraw = NULL,
.config = NULL
};
``` | /content/code_sandbox/src/video/vid_stg_ramdac.c | c | 2016-06-25T22:29:10 | 2024-08-16T19:09:21 | 86Box | 86Box/86Box | 2,616 | 1,910 |
```c
/*
* 86Box A hypervisor and IBM PC system emulator that specializes in
* running old operating systems and software designed for IBM
* PC systems and compatibles from 1981 through fairly recent
* system designs based on the PCI bus.
*
* This file is part of the 86Box distribution.
*
* ICS2494 clock generator emulation.
*
* Used by the AMI S3 924.
*
*
*
* Authors: Miran Grca, <mgrca8@gmail.com>
*
*/
#include <stdarg.h>
#include <stdio.h>
#include <stdint.h>
#include <stdlib.h>
#include <string.h>
#include <wchar.h>
#define HAVE_STDARG_H
#include <86box/86box.h>
#include <86box/device.h>
typedef struct ics2494_t {
float freq[16];
} ics2494_t;
#ifdef ENABLE_ICS2494_LOG
int ics2494_do_log = ENABLE_ICS2494_LOG;
static void
ics2494_log(const char *fmt, ...)
{
va_list ap;
if (ics2494_do_log) {
va_start(ap, fmt);
pclog_ex(fmt, ap);
va_end(ap);
}
}
#else
# define ics2494_log(fmt, ...)
#endif
float
ics2494_getclock(int clock, void *priv)
{
const ics2494_t *ics2494 = (ics2494_t *) priv;
if (clock > 15)
clock = 15;
ics2494_log("Clock=%d, freq=%f.\n", clock, ics2494->freq[clock]);
return ics2494->freq[clock];
}
static void *
ics2494_init(const device_t *info)
{
ics2494_t *ics2494 = (ics2494_t *) malloc(sizeof(ics2494_t));
memset(ics2494, 0, sizeof(ics2494_t));
switch (info->local) {
case 10:
/* ATI 18810 for ATI 28800 */
ics2494->freq[0x0] = 42954000.0;
ics2494->freq[0x1] = 48771000.0;
ics2494->freq[0x2] = 0.0;
ics2494->freq[0x3] = 36000000.0;
ics2494->freq[0x4] = 50350000.0;
ics2494->freq[0x5] = 56640000.0;
ics2494->freq[0x6] = 0.0;
ics2494->freq[0x7] = 44900000.0;
ics2494->freq[0x8] = 30240000.0;
ics2494->freq[0x9] = 32000000.0;
ics2494->freq[0xa] = 37500000.0;
ics2494->freq[0xb] = 39000000.0;
ics2494->freq[0xc] = 40000000.0;
ics2494->freq[0xd] = 56644000.0;
ics2494->freq[0xe] = 75000000.0;
ics2494->freq[0xf] = 65000000.0;
break;
case 110:
/* ATI 18811-0 for ATI Mach32 */
ics2494->freq[0x0] = 42954000.0;
ics2494->freq[0x1] = 48771000.0;
ics2494->freq[0x2] = 92400000.0;
ics2494->freq[0x3] = 36000000.0;
ics2494->freq[0x4] = 50350000.0;
ics2494->freq[0x5] = 56640000.0;
ics2494->freq[0x6] = 0.0;
ics2494->freq[0x7] = 44900000.0;
ics2494->freq[0x8] = 30240000.0;
ics2494->freq[0x9] = 32000000.0;
ics2494->freq[0xa] = 110000000.0;
ics2494->freq[0xb] = 80000000.0;
ics2494->freq[0xc] = 39910000.0;
ics2494->freq[0xd] = 44900000.0;
ics2494->freq[0xe] = 75000000.0;
ics2494->freq[0xf] = 65000000.0;
break;
case 111:
/* ATI 18811-1 for ATI Mach32 MCA */
ics2494->freq[0x0] = 100000000.0;
ics2494->freq[0x1] = 126000000.0;
ics2494->freq[0x2] = 92400000.0;
ics2494->freq[0x3] = 36000000.0;
ics2494->freq[0x4] = 50350000.0;
ics2494->freq[0x5] = 56640000.0;
ics2494->freq[0x6] = 0.0;
ics2494->freq[0x7] = 44900000.0;
ics2494->freq[0x8] = 135000000.0;
ics2494->freq[0x9] = 32000000.0;
ics2494->freq[0xa] = 110000000.0;
ics2494->freq[0xb] = 80000000.0;
ics2494->freq[0xc] = 39910000.0;
ics2494->freq[0xd] = 44900000.0;
ics2494->freq[0xe] = 75000000.0;
ics2494->freq[0xf] = 65000000.0;
break;
case 305:
/* ICS2494A(N)-205 for S3 86C924 */
ics2494->freq[0x0] = 25175000.0;
ics2494->freq[0x1] = 28322000.0;
ics2494->freq[0x2] = 40000000.0;
ics2494->freq[0x3] = 0.0;
ics2494->freq[0x4] = 50000000.0;
ics2494->freq[0x5] = 77000000.0;
ics2494->freq[0x6] = 36000000.0;
ics2494->freq[0x7] = 44889000.0;
ics2494->freq[0x8] = 130000000.0;
ics2494->freq[0x9] = 120000000.0;
ics2494->freq[0xa] = 80000000.0;
ics2494->freq[0xb] = 31500000.0;
ics2494->freq[0xc] = 110000000.0;
ics2494->freq[0xd] = 65000000.0;
ics2494->freq[0xe] = 75000000.0;
ics2494->freq[0xf] = 94500000.0;
break;
default:
break;
}
return ics2494;
}
static void
ics2494_close(void *priv)
{
ics2494_t *ics2494 = (ics2494_t *) priv;
if (ics2494)
free(ics2494);
}
const device_t ics2494an_305_device = {
.name = "ICS2494AN-305 Clock Generator",
.internal_name = "ics2494an_305",
.flags = 0,
.local = 305,
.init = ics2494_init,
.close = ics2494_close,
.reset = NULL,
{ .available = NULL },
.speed_changed = NULL,
.force_redraw = NULL,
.config = NULL
};
const device_t ati18810_device = {
.name = "ATI 18810 Clock Generator",
.internal_name = "ati18810",
.flags = 0,
.local = 10,
.init = ics2494_init,
.close = ics2494_close,
.reset = NULL,
{ .available = NULL },
.speed_changed = NULL,
.force_redraw = NULL,
.config = NULL
};
const device_t ati18811_0_device = {
.name = "ATI 18811-0 Clock Generator",
.internal_name = "ati18811_0",
.flags = 0,
.local = 110,
.init = ics2494_init,
.close = ics2494_close,
.reset = NULL,
{ .available = NULL },
.speed_changed = NULL,
.force_redraw = NULL,
.config = NULL
};
const device_t ati18811_1_device = {
.name = "ATI 18811-1 Clock Generator",
.internal_name = "ati18811_1",
.flags = 0,
.local = 111,
.init = ics2494_init,
.close = ics2494_close,
.reset = NULL,
{ .available = NULL },
.speed_changed = NULL,
.force_redraw = NULL,
.config = NULL
};
``` | /content/code_sandbox/src/video/vid_ics2494.c | c | 2016-06-25T22:29:10 | 2024-08-16T19:09:21 | 86Box | 86Box/86Box | 2,616 | 2,287 |
```c
/*
* 86Box A hypervisor and IBM PC system emulator that specializes in
* running old operating systems and software designed for IBM
* PC systems and compatibles from 1981 through fairly recent
* system designs based on the PCI bus.
*
* This file is part of the 86Box distribution.
*
* ATI 28800 emulation (VGA Charger and Korean VGA)
*
*
*
* Authors: Sarah Walker, <path_to_url
* Miran Grca, <mgrca8@gmail.com>
* greatpsycho,
*
*/
#include <stdarg.h>
#include <stdint.h>
#include <stdio.h>
#include <string.h>
#include <stdlib.h>
#include <wchar.h>
#define HAVE_STDARG_H
#include <86box/86box.h>
#include <86box/io.h>
#include <86box/mem.h>
#include <86box/rom.h>
#include <86box/device.h>
#include <86box/timer.h>
#include <86box/video.h>
#include <86box/vid_ati_eeprom.h>
#include <86box/vid_svga.h>
#include <86box/vid_svga_render.h>
#define VGAWONDERXL 1
#ifdef USE_XL24
# define VGAWONDERXL24 2
#endif /* USE_XL24 */
#define BIOS_ATIKOR_PATH "roms/video/ati28800/atikorvga.bin"
#define BIOS_ATIKOR_4620P_PATH_L "roms/machines/spc4620p/31005h.u8"
#define BIOS_ATIKOR_4620P_PATH_H "roms/machines/spc4620p/31005h.u10"
#define BIOS_ATIKOR_6033P_PATH "roms/machines/spc6033p/phoenix.BIN"
#define FONT_ATIKOR_PATH "roms/video/ati28800/ati_ksc5601.rom"
#define FONT_ATIKOR_4620P_PATH "roms/machines/spc4620p/svb6120a_font.rom"
#define FONT_ATIKOR_6033P_PATH "roms/machines/spc6033p/svb6120a_font.rom"
#define BIOS_VGAXL_EVEN_PATH "roms/video/ati28800/xleven.bin"
#define BIOS_VGAXL_ODD_PATH "roms/video/ati28800/xlodd.bin"
#ifdef USE_XL24
# define BIOS_XL24_EVEN_PATH "roms/video/ati28800/112-14318-102.bin"
# define BIOS_XL24_ODD_PATH "roms/video/ati28800/112-14319-102.bin"
#endif /* USE_XL24 */
#define BIOS_ROM_PATH "roms/video/ati28800/bios.bin"
#define BIOS_VGAXL_ROM_PATH "roms/video/ati28800/ATI_VGAWonder_XL.bin"
typedef struct ati28800_t {
svga_t svga;
ati_eeprom_t eeprom;
rom_t bios_rom;
uint8_t regs[256];
int index;
uint16_t vtotal;
uint32_t memory;
uint8_t id;
uint8_t port_03dd_val;
uint16_t get_korean_font_kind;
int in_get_korean_font_kind_set;
int get_korean_font_enabled;
int get_korean_font_index;
uint16_t get_korean_font_base;
int ksc5601_mode_enabled;
int type, type_korean;
} ati28800_t;
static video_timings_t timing_ati28800 = { .type = VIDEO_ISA, .write_b = 3, .write_w = 3, .write_l = 6, .read_b = 5, .read_w = 5, .read_l = 10 };
static video_timings_t timing_ati28800_spc = { .type = VIDEO_ISA, .write_b = 2, .write_w = 2, .write_l = 4, .read_b = 4, .read_w = 4, .read_l = 8 };
#ifdef ENABLE_ATI28800_LOG
int ati28800_do_log = ENABLE_ATI28800_LOG;
static void
ati28800_log(const char *fmt, ...)
{
va_list ap;
if (ati28800_do_log) {
va_start(ap, fmt);
pclog_ex(fmt, ap);
va_end(ap);
}
}
#else
# define ati28800_log(fmt, ...)
#endif
static void ati28800_recalctimings(svga_t *svga);
static void
ati28800_out(uint16_t addr, uint8_t val, void *priv)
{
ati28800_t *ati28800 = (ati28800_t *) priv;
svga_t *svga = &ati28800->svga;
uint8_t old;
ati28800_log("ati28800_out : %04X %02X\n", addr, val);
if (((addr & 0xFFF0) == 0x3D0 || (addr & 0xFFF0) == 0x3B0) && !(svga->miscout & 1))
addr ^= 0x60;
switch (addr) {
case 0x1ce:
ati28800->index = val;
break;
case 0x1cf:
old = ati28800->regs[ati28800->index];
ati28800->regs[ati28800->index] = val;
ati28800_log("ATI 28800 write reg=0x%02X, val=0x%02X\n", ati28800->index, val);
switch (ati28800->index) {
case 0xa3:
if ((old ^ val) & 0x10)
svga_recalctimings(svga);
break;
case 0xa7:
if ((old ^ val) & 0x80)
svga_recalctimings(svga);
break;
case 0xad:
if ((old ^ val) & 0x0c)
svga_recalctimings(svga);
break;
case 0xb0:
if ((old ^ val) & 0x60)
svga_recalctimings(svga);
break;
case 0xb2:
case 0xbe:
if (ati28800->regs[0xbe] & 0x08) { /* Read/write bank mode */
svga->read_bank = (((ati28800->regs[0xb2] & 0x01) << 3) | ((ati28800->regs[0xb2] & 0xe0) >> 5)) * 0x10000;
svga->write_bank = ((ati28800->regs[0xb2] & 0x1e) >> 1) * 0x10000;
} else { /* Single bank mode */
svga->read_bank = ((ati28800->regs[0xb2] & 0x1e) >> 1) * 0x10000;
svga->write_bank = ((ati28800->regs[0xb2] & 0x1e) >> 1) * 0x10000;
}
if (ati28800->index == 0xbe) {
if ((old ^ val) & 0x10)
svga_recalctimings(svga);
}
break;
case 0xb3:
ati_eeprom_write(&ati28800->eeprom, val & 8, val & 2, val & 1);
break;
case 0xb6:
if ((old ^ val) & 0x10)
svga_recalctimings(svga);
break;
case 0xb8:
if ((old ^ val) & 0x40)
svga_recalctimings(svga);
break;
case 0xb9:
if ((old ^ val) & 2)
svga_recalctimings(svga);
break;
default:
break;
}
break;
case 0x3C6:
case 0x3C7:
case 0x3C8:
case 0x3C9:
if (ati28800->type == 1)
sc1148x_ramdac_out(addr, 0, val, svga->ramdac, svga);
else
svga_out(addr, val, svga);
return;
case 0x3D4:
svga->crtcreg = val & 0x3f;
return;
case 0x3D5:
if ((svga->crtcreg < 7) && (svga->crtc[0x11] & 0x80))
return;
if ((svga->crtcreg == 7) && (svga->crtc[0x11] & 0x80))
val = (svga->crtc[7] & ~0x10) | (val & 0x10);
old = svga->crtc[svga->crtcreg];
svga->crtc[svga->crtcreg] = val;
if (old != val) {
if (svga->crtcreg < 0xe || svga->crtcreg > 0x10) {
if ((svga->crtcreg == 0xc) || (svga->crtcreg == 0xd)) {
svga->fullchange = 3;
svga->ma_latch = ((svga->crtc[0xc] << 8) | svga->crtc[0xd]) + ((svga->crtc[8] & 0x60) >> 5);
} else {
svga->fullchange = changeframecount;
svga_recalctimings(svga);
}
}
}
break;
default:
break;
}
svga_out(addr, val, svga);
}
static void
ati28800k_out(uint16_t addr, uint8_t val, void *priv)
{
ati28800_t *ati28800 = (ati28800_t *) priv;
svga_t *svga = &ati28800->svga;
uint16_t oldaddr = addr;
if (((addr & 0xFFF0) == 0x3D0 || (addr & 0xFFF0) == 0x3B0) && !(svga->miscout & 1))
addr ^= 0x60;
switch (addr) {
case 0x1CF:
if (ati28800->index == 0xBF && ((ati28800->regs[0xBF] ^ val) & 0x20)) {
ati28800->ksc5601_mode_enabled = val & 0x20;
svga_recalctimings(svga);
}
ati28800_out(oldaddr, val, priv);
break;
case 0x3DD:
ati28800->port_03dd_val = val;
if (val == 1)
ati28800->get_korean_font_enabled = 0;
if (ati28800->in_get_korean_font_kind_set) {
ati28800->get_korean_font_kind = (val << 8) | (ati28800->get_korean_font_kind & 0xFF);
ati28800->get_korean_font_enabled = 1;
ati28800->get_korean_font_index = 0;
ati28800->in_get_korean_font_kind_set = 0;
}
break;
case 0x3DE:
ati28800->in_get_korean_font_kind_set = 0;
if (ati28800->get_korean_font_enabled) {
if ((ati28800->get_korean_font_base & 0x7F) > 0x20 && (ati28800->get_korean_font_base & 0x7F) < 0x7F) {
fontdatksc5601_user[(ati28800->get_korean_font_kind & 4) * 24 + (ati28800->get_korean_font_base & 0x7F) - 0x20].chr[ati28800->get_korean_font_index] = val;
}
ati28800->get_korean_font_index++;
ati28800->get_korean_font_index &= 0x1F;
} else {
switch (ati28800->port_03dd_val) {
case 0x10:
ati28800->get_korean_font_base = ((val & 0x7F) << 7) | (ati28800->get_korean_font_base & 0x7F);
break;
case 8:
ati28800->get_korean_font_base = (ati28800->get_korean_font_base & 0x3F80) | (val & 0x7F);
break;
case 1:
ati28800->get_korean_font_kind = (ati28800->get_korean_font_kind & 0xFF00) | val;
if (val & 2)
ati28800->in_get_korean_font_kind_set = 1;
break;
default:
break;
}
break;
}
break;
default:
ati28800_out(oldaddr, val, priv);
break;
}
}
static uint8_t
ati28800_in(uint16_t addr, void *priv)
{
ati28800_t *ati28800 = (ati28800_t *) priv;
svga_t *svga = &ati28800->svga;
uint8_t temp;
if (addr != 0x3da)
ati28800_log("ati28800_in : %04X ", addr);
if (((addr & 0xFFF0) == 0x3D0 || (addr & 0xFFF0) == 0x3B0) && !(svga->miscout & 1))
addr ^= 0x60;
switch (addr) {
case 0x1ce:
temp = ati28800->index;
break;
case 0x1cf:
switch (ati28800->index) {
case 0xaa:
temp = ati28800->id;
break;
case 0xb0:
temp = ati28800->regs[0xb0] | 0x80;
if (ati28800->memory == 1024) {
temp &= ~0x10;
temp |= 0x08;
} else if (ati28800->memory == 512) {
temp |= 0x10;
temp &= ~0x08;
} else {
temp &= ~0x18;
}
break;
case 0xb7:
temp = ati28800->regs[0xb7] & ~8;
if (ati_eeprom_read(&ati28800->eeprom))
temp |= 8;
break;
default:
temp = ati28800->regs[ati28800->index];
break;
}
break;
case 0x3c2:
if ((svga->vgapal[0].r + svga->vgapal[0].g + svga->vgapal[0].b) >= 0x50)
temp = 0;
else
temp = 0x10;
break;
case 0x3C6:
case 0x3C7:
case 0x3C8:
case 0x3C9:
if (ati28800->type == 1)
return sc1148x_ramdac_in(addr, 0, svga->ramdac, svga);
return svga_in(addr, svga);
case 0x3D4:
temp = svga->crtcreg;
break;
case 0x3D5:
temp = svga->crtc[svga->crtcreg];
break;
default:
temp = svga_in(addr, svga);
break;
}
if (addr != 0x3da)
ati28800_log("%02X\n", temp);
return temp;
}
static uint8_t
ati28800k_in(uint16_t addr, void *priv)
{
ati28800_t *ati28800 = (ati28800_t *) priv;
const svga_t *svga = &ati28800->svga;
uint16_t oldaddr = addr;
uint8_t temp = 0xFF;
if (addr != 0x3da)
ati28800_log("ati28800k_in : %04X ", addr);
if (((addr & 0xFFF0) == 0x3D0 || (addr & 0xFFF0) == 0x3B0) && !(svga->miscout & 1))
addr ^= 0x60;
switch (addr) {
case 0x3DE:
if (ati28800->get_korean_font_enabled) {
switch (ati28800->get_korean_font_kind >> 8) {
case 4: /* ROM font */
temp = fontdatksc5601[ati28800->get_korean_font_base].chr[ati28800->get_korean_font_index++];
break;
case 2: /* User defined font */
if ((ati28800->get_korean_font_base & 0x7F) > 0x20 && (ati28800->get_korean_font_base & 0x7F) < 0x7F) {
temp = fontdatksc5601_user[(ati28800->get_korean_font_kind & 4) * 24 + (ati28800->get_korean_font_base & 0x7F) - 0x20].chr[ati28800->get_korean_font_index];
} else
temp = 0xFF;
ati28800->get_korean_font_index++;
break;
default:
break;
}
ati28800->get_korean_font_index &= 0x1F;
}
break;
default:
temp = ati28800_in(oldaddr, priv);
break;
}
if (addr != 0x3da)
ati28800_log("%02X\n", temp);
return temp;
}
static void
ati28800_recalctimings(svga_t *svga)
{
ati28800_t *ati28800 = (ati28800_t *) svga->priv;
int clock_sel;
if (ati28800->regs[0xad] & 0x08)
svga->hblankstart = ((ati28800->regs[0x0d] >> 2) << 8) + svga->crtc[2];
clock_sel = ((svga->miscout >> 2) & 3) | ((ati28800->regs[0xbe] & 0x10) >> 1) |
((ati28800->regs[0xb9] & 2) << 1);
if (ati28800->regs[0xa3] & 0x10)
svga->ma_latch |= 0x10000;
if (ati28800->regs[0xb0] & 0x40)
svga->ma_latch |= 0x20000;
if (ati28800->regs[0xb8] & 0x40)
svga->clock *= 2;
if (ati28800->regs[0xa7] & 0x80)
svga->clock *= 3;
if ((ati28800->regs[0xb6] & 0x18) >= 0x10) {
svga->hdisp <<= 1;
svga->htotal <<= 1;
svga->rowoffset <<= 1;
svga->dots_per_clock <<= 1;
svga->gdcreg[5] &= ~0x40;
}
if (ati28800->regs[0xb0] & 0x20) {
svga->gdcreg[5] |= 0x40;
if ((ati28800->regs[0xb6] & 0x18) >= 0x10)
svga->packed_4bpp = 1;
else
svga->packed_4bpp = 0;
} else
svga->packed_4bpp = 0;
if ((ati28800->regs[0xb6] & 0x18) == 8) {
svga->hdisp <<= 1;
svga->htotal <<= 1;
svga->dots_per_clock <<= 1;
svga->ati_4color = 1;
} else
svga->ati_4color = 0;
if (!svga->scrblank && (svga->crtc[0x17] & 0x80) && svga->attr_palette_enable) {
if ((svga->gdcreg[6] & 1) || (svga->attrregs[0x10] & 1)) {
svga->clock = (cpuclock * (double) (1ULL << 32)) / svga->getclock(clock_sel, svga->clock_gen);
ati28800_log("SEQREG1 bit 3=%x. gdcreg5 bits 5-6=%02x, 4bit pel=%02x, "
"planar 16color=%02x, apa mode=%02x, attregs10 bit 7=%02x.\n",
svga->seqregs[1] & 8, svga->gdcreg[5] & 0x60,
ati28800->regs[0xb3] & 0x40, ati28800->regs[0xac] & 0x40,
ati28800->regs[0xb6] & 0x18, ati28800->svga.attrregs[0x10] & 0x80);
switch (svga->gdcreg[5] & 0x60) {
case 0x00:
if (svga->seqregs[1] & 8) /*Low res (320)*/
svga->render = svga_render_4bpp_lowres;
else
svga->render = svga_render_4bpp_highres;
break;
case 0x20: /*4 colours*/
if (svga->seqregs[1] & 8) /*Low res (320)*/
svga->render = svga_render_2bpp_lowres;
else
svga->render = svga_render_2bpp_highres;
break;
case 0x40:
case 0x60: /*256+ colours*/
switch (svga->bpp) {
case 8:
svga->map8 = svga->pallook;
if (svga->lowres)
svga->render = svga_render_8bpp_lowres;
else {
svga->render = svga_render_8bpp_highres;
if (!svga->packed_4bpp) {
svga->ma_latch <<= 1;
svga->rowoffset <<= 1;
}
}
break;
case 15:
if (svga->lowres)
svga->render = svga_render_15bpp_lowres;
else {
svga->render = svga_render_15bpp_highres;
svga->hdisp >>= 1;
svga->dots_per_clock >>= 1;
svga->rowoffset <<= 1;
svga->ma_latch <<= 1;
}
break;
default:
break;
}
break;
default:
break;
}
}
}
}
static void
ati28800k_recalctimings(svga_t *svga)
{
const ati28800_t *ati28800 = (ati28800_t *) svga->priv;
ati28800_recalctimings(svga);
if (svga->render == svga_render_text_80 && ati28800->ksc5601_mode_enabled)
svga->render = svga_render_text_80_ksc5601;
}
void *
ati28800k_init(const device_t *info)
{
ati28800_t *ati28800 = (ati28800_t *) malloc(sizeof(ati28800_t));
memset(ati28800, 0, sizeof(ati28800_t));
ati28800->type_korean = info->local;
if (ati28800->type_korean == 0) {
ati28800->memory = device_get_config_int("memory");
video_inform(VIDEO_FLAG_TYPE_SPECIAL, &timing_ati28800);
} else {
ati28800->memory = 512;
video_inform(VIDEO_FLAG_TYPE_SPECIAL, &timing_ati28800_spc);
}
ati28800->port_03dd_val = 0;
ati28800->get_korean_font_base = 0;
ati28800->get_korean_font_index = 0;
ati28800->get_korean_font_enabled = 0;
ati28800->get_korean_font_kind = 0;
ati28800->in_get_korean_font_kind_set = 0;
ati28800->ksc5601_mode_enabled = 0;
switch (ati28800->type_korean) {
default:
case 0:
rom_init(&ati28800->bios_rom, BIOS_ATIKOR_PATH, 0xc0000, 0x8000, 0x7fff, 0, MEM_MAPPING_EXTERNAL);
loadfont(FONT_ATIKOR_PATH, 6);
break;
case 1:
rom_init_interleaved(&ati28800->bios_rom, BIOS_ATIKOR_4620P_PATH_L, BIOS_ATIKOR_4620P_PATH_H, 0xc0000,
0x8000, 0x7fff, 0, MEM_MAPPING_EXTERNAL);
loadfont(FONT_ATIKOR_4620P_PATH, 6);
break;
case 2:
rom_init(&ati28800->bios_rom, BIOS_ATIKOR_6033P_PATH, 0xc0000, 0x8000, 0x7fff, 0, MEM_MAPPING_EXTERNAL);
loadfont(FONT_ATIKOR_6033P_PATH, 6);
break;
}
svga_init(info, &ati28800->svga, ati28800, ati28800->memory << 10, /*Memory size, default 512KB*/
ati28800k_recalctimings,
ati28800k_in, ati28800k_out,
NULL,
NULL);
ati28800->svga.clock_gen = device_add(&ati18810_device);
ati28800->svga.getclock = ics2494_getclock;
io_sethandler(0x01ce, 0x0002, ati28800k_in, NULL, NULL, ati28800k_out, NULL, NULL, ati28800);
io_sethandler(0x03c0, 0x0020, ati28800k_in, NULL, NULL, ati28800k_out, NULL, NULL, ati28800);
ati28800->svga.miscout = 1;
ati28800->svga.bpp = 8;
ati28800->svga.packed_chain4 = 1;
ati28800->svga.ksc5601_sbyte_mask = 0;
ati28800->svga.ksc5601_udc_area_msb[0] = 0xC9;
ati28800->svga.ksc5601_udc_area_msb[1] = 0xFE;
ati28800->svga.ksc5601_swap_mode = 0;
ati28800->svga.ksc5601_english_font_type = 0;
ati_eeprom_load(&ati28800->eeprom, "atikorvga.nvr", 0);
return ati28800;
}
static void *
ati28800_init(const device_t *info)
{
ati28800_t *ati28800;
ati28800 = malloc(sizeof(ati28800_t));
memset(ati28800, 0x00, sizeof(ati28800_t));
video_inform(VIDEO_FLAG_TYPE_SPECIAL, &timing_ati28800);
ati28800->memory = device_get_config_int("memory");
ati28800->type = info->local;
switch (ati28800->type) {
case VGAWONDERXL:
ati28800->id = 5;
rom_init(&ati28800->bios_rom,
BIOS_VGAXL_ROM_PATH,
0xc0000, 0x8000, 0x7fff,
0, MEM_MAPPING_EXTERNAL);
ati28800->svga.ramdac = device_add(&sc11486_ramdac_device);
break;
#ifdef USE_XL24
case VGAWONDERXL24:
ati28800->id = 6;
rom_init_interleaved(&ati28800->bios_rom,
BIOS_XL24_EVEN_PATH,
BIOS_XL24_ODD_PATH,
0xc0000, 0x10000, 0xffff,
0, MEM_MAPPING_EXTERNAL);
break;
#endif /* USE_XL24 */
default:
ati28800->id = 5;
rom_init(&ati28800->bios_rom,
BIOS_ROM_PATH,
0xc0000, 0x8000, 0x7fff,
0, MEM_MAPPING_EXTERNAL);
break;
}
svga_init(info, &ati28800->svga, ati28800, ati28800->memory << 10, /*default: 512kb*/
ati28800_recalctimings,
ati28800_in, ati28800_out,
NULL,
NULL);
ati28800->svga.clock_gen = device_add(&ati18810_device);
ati28800->svga.getclock = ics2494_getclock;
io_sethandler(0x01ce, 2,
ati28800_in, NULL, NULL,
ati28800_out, NULL, NULL, ati28800);
io_sethandler(0x03c0, 32,
ati28800_in, NULL, NULL,
ati28800_out, NULL, NULL, ati28800);
ati28800->svga.miscout = 1;
ati28800->svga.bpp = 8;
ati28800->svga.packed_chain4 = 1;
switch (ati28800->type) {
case VGAWONDERXL:
ati_eeprom_load(&ati28800->eeprom, "ati28800xl.nvr", 0);
break;
#ifdef USE_XL24
case VGAWONDERXL24:
ati_eeprom_load(&ati28800->eeprom, "ati28800xl24.nvr", 0);
break;
#endif /* USE_XL24 */
default:
ati_eeprom_load(&ati28800->eeprom, "ati28800.nvr", 0);
break;
}
return ati28800;
}
static int
ati28800_available(void)
{
return (rom_present(BIOS_ROM_PATH));
}
static int
ati28800k_available(void)
{
return (rom_present(BIOS_ATIKOR_PATH) && rom_present(FONT_ATIKOR_PATH));
}
static int
compaq_ati28800_available(void)
{
return (rom_present(BIOS_VGAXL_ROM_PATH));
}
#ifdef USE_XL24
static int
ati28800_wonderxl24_available(void)
{
return (rom_present(BIOS_XL24_EVEN_PATH) && rom_present(BIOS_XL24_ODD_PATH));
}
#endif /* USE_XL24 */
static void
ati28800_close(void *priv)
{
ati28800_t *ati28800 = (ati28800_t *) priv;
svga_close(&ati28800->svga);
free(ati28800);
}
static void
ati28800_speed_changed(void *priv)
{
ati28800_t *ati28800 = (ati28800_t *) priv;
svga_recalctimings(&ati28800->svga);
}
static void
ati28800_force_redraw(void *priv)
{
ati28800_t *ati28800 = (ati28800_t *) priv;
ati28800->svga.fullchange = changeframecount;
}
// clang-format off
static const device_config_t ati28800_config[] = {
{
.name = "memory",
.description = "Memory size",
.type = CONFIG_SELECTION,
.default_int = 512,
.selection = {
{
.description = "256 kB",
.value = 256
},
{
.description = "512 kB",
.value = 512
},
{
.description = "1 MB",
.value = 1024
},
{
.description = ""
}
}
},
{
.type = CONFIG_END
}
};
#ifdef USE_XL24
static const device_config_t ati28800_wonderxl_config[] = {
{
.name = "memory",
.description = "Memory size",
.type = CONFIG_SELECTION,
.default_int = 512,
.selection = {
{
.description = "256 kB",
.value = 256
},
{
.description = "512 kB",
.value = 512
},
{
.description = "1 MB",
.value = 1024
},
{
.description = ""
}
}
},
{
.type = CONFIG_END
}
};
#endif /* USE_XL24 */
// clang-format on
const device_t ati28800_device = {
.name = "ATI 28800-5 (ATI VGA Charger)",
.internal_name = "ati28800",
.flags = DEVICE_ISA,
.local = 0,
.init = ati28800_init,
.close = ati28800_close,
.reset = NULL,
{ .available = ati28800_available },
.speed_changed = ati28800_speed_changed,
.force_redraw = ati28800_force_redraw,
.config = ati28800_config
};
const device_t ati28800k_device = {
.name = "ATI Korean VGA",
.internal_name = "ati28800k",
.flags = DEVICE_ISA,
.local = 0,
.init = ati28800k_init,
.close = ati28800_close,
.reset = NULL,
{ .available = ati28800k_available },
.speed_changed = ati28800_speed_changed,
.force_redraw = ati28800_force_redraw,
.config = ati28800_config
};
const device_t ati28800k_spc4620p_device = {
.name = "ATI Korean VGA On-Board SPC-4620P",
.internal_name = "ati28800k_spc4620p",
.flags = DEVICE_ISA,
.local = 1,
.init = ati28800k_init,
.close = ati28800_close,
.reset = NULL,
{ .available = NULL },
.speed_changed = ati28800_speed_changed,
.force_redraw = ati28800_force_redraw,
.config = NULL
};
const device_t ati28800k_spc6033p_device = {
.name = "ATI Korean VGA On-Board SPC-6033P",
.internal_name = "ati28800k_spc6033p",
.flags = DEVICE_ISA,
.local = 2,
.init = ati28800k_init,
.close = ati28800_close,
.reset = NULL,
{ .available = NULL },
.speed_changed = ati28800_speed_changed,
.force_redraw = ati28800_force_redraw,
.config = NULL
};
const device_t compaq_ati28800_device = {
.name = "ATI 28800-5 (ATI VGA Wonder XL)",
.internal_name = "compaq_ati28800",
.flags = DEVICE_ISA,
.local = VGAWONDERXL,
.init = ati28800_init,
.close = ati28800_close,
.reset = NULL,
{ .available = compaq_ati28800_available },
.speed_changed = ati28800_speed_changed,
.force_redraw = ati28800_force_redraw,
.config = ati28800_config
};
#ifdef USE_XL24
const device_t ati28800_wonderxl24_device = {
.name = "ATI-28800 (VGA Wonder XL24)",
.internal_name = "ati28800w",
.flags = DEVICE_ISA,
.local = VGAWONDERXL24,
.init = ati28800_init,
.close = ati28800_close,
.reset = NULL,
{ .available = ati28800_wonderxl24_available },
.speed_changed = ati28800_speed_changed,
.force_redraw = ati28800_force_redraw,
.config = ati28800_wonderxl_config
};
#endif /* USE_XL24 */
``` | /content/code_sandbox/src/video/vid_ati28800.c | c | 2016-06-25T22:29:10 | 2024-08-16T19:09:21 | 86Box | 86Box/86Box | 2,616 | 8,545 |
```c
/*
* 86Box A hypervisor and IBM PC system emulator that specializes in
* running old operating systems and software designed for IBM
* PC systems and compatibles from 1981 through fairly recent
* system designs based on the PCI bus.
*
* This file is part of the 86Box distribution.
*
* Emulation of the Texas Instruments TVP3026 true colour RAMDAC
* family.
*
*
* TODO: Clock and other parts.
*
* Authors: TheCollector1995,
*
*/
#include <stdio.h>
#include <stdint.h>
#include <stdlib.h>
#include <string.h>
#include <wchar.h>
#include <86box/86box.h>
#include <86box/device.h>
#include <86box/mem.h>
#include <86box/timer.h>
#include <86box/video.h>
#include <86box/vid_svga.h>
#include <86box/plat_fallthrough.h>
typedef struct tvp3026_ramdac_t {
PALETTE extpal;
uint32_t extpallook[256];
uint8_t cursor64_data[1024];
int hwc_y;
int hwc_x;
uint8_t ind_idx;
uint8_t dcc;
uint8_t dc_init;
uint8_t ccr;
uint8_t true_color;
uint8_t latch_cntl;
uint8_t mcr;
uint8_t ppr;
uint8_t general_cntl;
uint8_t mclk;
uint8_t misc;
uint8_t type;
uint8_t mode;
uint8_t pll_addr;
uint8_t clock_sel;
struct {
uint8_t m;
uint8_t n;
uint8_t p;
} pix, mem, loop;
uint8_t gpio_cntl;
uint8_t gpio_data;
uint8_t (*gpio_read)(uint8_t cntl, void *priv);
void (*gpio_write)(uint8_t cntl, uint8_t val, void *priv);
void *gpio_priv;
} tvp3026_ramdac_t;
static void
tvp3026_set_bpp(tvp3026_ramdac_t *ramdac, svga_t *svga)
{
if (ramdac->true_color & 0x80) {
if (ramdac->mcr & 0x08)
svga->bpp = 8;
else
svga->bpp = 4;
} else {
switch (ramdac->true_color & 0x0f) {
case 0x01:
case 0x03:
case 0x05:
svga->bpp = 16;
break;
case 0x04:
svga->bpp = 15;
break;
case 0x06:
case 0x07:
if (ramdac->true_color & 0x10)
svga->bpp = 24;
else
svga->bpp = 32;
break;
case 0x0e:
case 0x0f:
svga->bpp = 24;
break;
default:
break;
}
}
svga_recalctimings(svga);
}
void
tvp3026_ramdac_out(uint16_t addr, int rs2, int rs3, uint8_t val, void *priv, svga_t *svga)
{
tvp3026_ramdac_t *ramdac = (tvp3026_ramdac_t *) priv;
uint32_t o32;
uint8_t *cd;
uint16_t index;
uint8_t rs = (addr & 0x03);
uint16_t da_mask = 0x03ff;
rs |= (!!rs2 << 2);
rs |= (!!rs3 << 3);
switch (rs) {
case 0x00: /* Palette Write Index Register (RS value = 0000) */
ramdac->ind_idx = val;
fallthrough;
case 0x04: /* Ext Palette Write Index Register (RS value = 0100) */
case 0x03:
case 0x07: /* Ext Palette Read Index Register (RS value = 0111) */
svga->dac_pos = 0;
svga->dac_status = addr & 0x03;
svga->dac_addr = val;
if (svga->dac_status)
svga->dac_addr = (svga->dac_addr + 1) & da_mask;
break;
case 0x01: /* Palette Data Register (RS value = 0001) */
case 0x02: /* Pixel Read Mask Register (RS value = 0010) */
svga_out(addr, val, svga);
break;
case 0x05: /* Ext Palette Data Register (RS value = 0101) */
svga->dac_status = 0;
svga->fullchange = changeframecount;
switch (svga->dac_pos) {
case 0:
svga->dac_r = val;
svga->dac_pos++;
break;
case 1:
svga->dac_g = val;
svga->dac_pos++;
break;
case 2:
index = svga->dac_addr & 3;
ramdac->extpal[index].r = svga->dac_r;
ramdac->extpal[index].g = svga->dac_g;
ramdac->extpal[index].b = val;
if (svga->ramdac_type == RAMDAC_8BIT)
ramdac->extpallook[index] = makecol32(ramdac->extpal[index].r, ramdac->extpal[index].g, ramdac->extpal[index].b);
else
ramdac->extpallook[index] = makecol32(video_6to8[ramdac->extpal[index].r & 0x3f], video_6to8[ramdac->extpal[index].g & 0x3f], video_6to8[ramdac->extpal[index].b & 0x3f]);
if (svga->ext_overscan && !index) {
o32 = svga->overscan_color;
svga->overscan_color = ramdac->extpallook[0];
if (o32 != svga->overscan_color)
svga_recalctimings(svga);
}
svga->dac_addr = (svga->dac_addr + 1) & 0xff;
svga->dac_pos = 0;
break;
default:
break;
}
break;
case 0x09: /* Direct Cursor Control (RS value = 1001) */
ramdac->dcc = val;
if (ramdac->ccr & 0x80) {
svga->dac_hwcursor.cur_xsize = svga->dac_hwcursor.cur_ysize = 64;
svga->dac_hwcursor.x = ramdac->hwc_x - svga->dac_hwcursor.cur_xsize;
svga->dac_hwcursor.y = ramdac->hwc_y - svga->dac_hwcursor.cur_ysize;
svga->dac_hwcursor.ena = !!(val & 0x03);
ramdac->mode = val & 0x03;
}
break;
case 0x0a: /* Indexed Data (RS value = 1010) */
switch (ramdac->ind_idx) {
case 0x06: /* Indirect Cursor Control */
ramdac->ccr = val;
if (!(ramdac->ccr & 0x80)) {
svga->dac_hwcursor.cur_xsize = svga->dac_hwcursor.cur_ysize = 64;
svga->dac_hwcursor.x = ramdac->hwc_x - svga->dac_hwcursor.cur_xsize;
svga->dac_hwcursor.y = ramdac->hwc_y - svga->dac_hwcursor.cur_ysize;
svga->dac_hwcursor.ena = !!(val & 0x03);
ramdac->mode = val & 0x03;
} else {
svga->dac_hwcursor.cur_xsize = svga->dac_hwcursor.cur_ysize = 64;
svga->dac_hwcursor.x = ramdac->hwc_x - svga->dac_hwcursor.cur_xsize;
svga->dac_hwcursor.y = ramdac->hwc_y - svga->dac_hwcursor.cur_ysize;
svga->dac_hwcursor.ena = !!(ramdac->dcc & 0x03);
ramdac->mode = ramdac->dcc & 0x03;
}
break;
case 0x0f: /* Latch Control */
ramdac->latch_cntl = val;
break;
case 0x18: /* True Color Control */
ramdac->true_color = val;
tvp3026_set_bpp(ramdac, svga);
break;
case 0x19: /* Multiplex Control */
ramdac->mcr = val;
tvp3026_set_bpp(ramdac, svga);
break;
case 0x1a: /* Clock Selection */
ramdac->clock_sel = val;
break;
case 0x1c: /* Palette-Page Register */
ramdac->ppr = val;
break;
case 0x1d: /* General Control Register */
ramdac->general_cntl = val;
break;
case 0x1e: /* Miscellaneous Control */
ramdac->misc = val;
svga->ramdac_type = (val & 0x08) ? RAMDAC_8BIT : RAMDAC_6BIT;
break;
case 0x2a: /* General-Purpose I/O Control */
ramdac->gpio_cntl = val;
if (ramdac->gpio_write)
ramdac->gpio_write(ramdac->gpio_cntl, ramdac->gpio_data, ramdac->gpio_priv);
break;
case 0x2b: /* General-Purpose I/O Data */
ramdac->gpio_data = val;
if (ramdac->gpio_write)
ramdac->gpio_write(ramdac->gpio_cntl, ramdac->gpio_data, ramdac->gpio_priv);
break;
case 0x2c: /* PLL Address */
ramdac->pll_addr = val;
break;
case 0x2d: /* Pixel clock PLL data */
switch (ramdac->pll_addr & 3) {
case 0:
ramdac->pix.n = val;
break;
case 1:
ramdac->pix.m = val;
break;
case 2:
ramdac->pix.p = val;
break;
default:
break;
}
ramdac->pll_addr = ((ramdac->pll_addr + 1) & 3) | (ramdac->pll_addr & 0xfc);
break;
case 0x2e: /* Memory Clock PLL Data */
switch ((ramdac->pll_addr >> 2) & 3) {
case 0:
ramdac->mem.n = val;
break;
case 1:
ramdac->mem.m = val;
break;
case 2:
ramdac->mem.p = val;
break;
default:
break;
}
ramdac->pll_addr = ((ramdac->pll_addr + 4) & 0x0c) | (ramdac->pll_addr & 0xf3);
break;
case 0x2f: /* Loop Clock PLL Data */
switch ((ramdac->pll_addr >> 4) & 3) {
case 0:
ramdac->loop.n = val;
break;
case 1:
ramdac->loop.m = val;
break;
case 2:
ramdac->loop.p = val;
break;
default:
break;
}
ramdac->pll_addr = ((ramdac->pll_addr + 0x10) & 0x30) | (ramdac->pll_addr & 0xcf);
break;
case 0x39: /* MCLK/Loop Clock Control */
ramdac->mclk = val;
break;
default:
break;
}
break;
case 0x0b: /* Cursor RAM Data Register (RS value = 1011) */
index = (svga->dac_addr & da_mask) | ((ramdac->ccr & 0x0c) << 6);
cd = (uint8_t *) ramdac->cursor64_data;
cd[index] = val;
svga->dac_addr = (svga->dac_addr + 1) & da_mask;
break;
case 0x0c: /* Cursor X Low Register (RS value = 1100) */
ramdac->hwc_x = (ramdac->hwc_x & 0x0f00) | val;
svga->dac_hwcursor.x = ramdac->hwc_x - svga->dac_hwcursor.cur_xsize;
break;
case 0x0d: /* Cursor X High Register (RS value = 1101) */
ramdac->hwc_x = (ramdac->hwc_x & 0x00ff) | ((val & 0x0f) << 8);
svga->dac_hwcursor.x = ramdac->hwc_x - svga->dac_hwcursor.cur_xsize;
break;
case 0x0e: /* Cursor Y Low Register (RS value = 1110) */
ramdac->hwc_y = (ramdac->hwc_y & 0x0f00) | val;
svga->dac_hwcursor.y = ramdac->hwc_y - svga->dac_hwcursor.cur_ysize;
break;
case 0x0f: /* Cursor Y High Register (RS value = 1111) */
ramdac->hwc_y = (ramdac->hwc_y & 0x00ff) | ((val & 0x0f) << 8);
svga->dac_hwcursor.y = ramdac->hwc_y - svga->dac_hwcursor.cur_ysize;
break;
default:
break;
}
return;
}
uint8_t
tvp3026_ramdac_in(uint16_t addr, int rs2, int rs3, void *priv, svga_t *svga)
{
tvp3026_ramdac_t *ramdac = (tvp3026_ramdac_t *) priv;
uint8_t temp = 0xff;
const uint8_t *cd;
uint16_t index;
uint8_t rs = (addr & 0x03);
uint16_t da_mask = 0x03ff;
rs |= (!!rs2 << 2);
rs |= (!!rs3 << 3);
switch (rs) {
case 0x00: /* Palette Write Index Register (RS value = 0000) */
case 0x01: /* Palette Data Register (RS value = 0001) */
case 0x02: /* Pixel Read Mask Register (RS value = 0010) */
case 0x04: /* Ext Palette Write Index Register (RS value = 0100) */
temp = svga_in(addr, svga);
break;
case 0x03: /* Palette Read Index Register (RS value = 0011) */
case 0x07: /* Ext Palette Read Index Register (RS value = 0111) */
temp = svga->dac_addr & 0xff;
break;
case 0x05: /* Ext Palette Data Register (RS value = 0101) */
index = (svga->dac_addr - 1) & 3;
svga->dac_status = 3;
switch (svga->dac_pos) {
case 0:
svga->dac_pos++;
if (svga->ramdac_type == RAMDAC_8BIT)
temp = ramdac->extpal[index].r;
else
temp = ramdac->extpal[index].r & 0x3f;
break;
case 1:
svga->dac_pos++;
if (svga->ramdac_type == RAMDAC_8BIT)
temp = ramdac->extpal[index].g;
else
temp = ramdac->extpal[index].g & 0x3f;
break;
case 2:
svga->dac_pos = 0;
svga->dac_addr = svga->dac_addr + 1;
if (svga->ramdac_type == RAMDAC_8BIT)
temp = ramdac->extpal[index].b;
else
temp = ramdac->extpal[index].b & 0x3f;
break;
default:
break;
}
break;
case 0x09: /* Direct Cursor Control (RS value = 1001) */
temp = ramdac->dcc;
break;
case 0x0a: /* Indexed Data (RS value = 1010) */
switch (ramdac->ind_idx) {
case 0x01: /* Silicon Revision */
temp = 0x00;
break;
case 0x06: /* Indirect Cursor Control */
temp = ramdac->ccr;
break;
case 0x0f: /* Latch Control */
temp = ramdac->latch_cntl;
break;
case 0x18: /* True Color Control */
temp = ramdac->true_color;
break;
case 0x19: /* Multiplex Control */
temp = ramdac->mcr;
break;
case 0x1a: /* Clock Selection */
temp = ramdac->clock_sel;
break;
case 0x1c: /* Palette-Page Register */
temp = ramdac->ppr;
break;
case 0x1d: /* General Control Register */
temp = ramdac->general_cntl;
break;
case 0x1e: /* Miscellaneous Control */
temp = ramdac->misc;
break;
case 0x2a: /* General-Purpose I/O Control */
temp = ramdac->gpio_cntl;
break;
case 0x2b: /* General-Purpose I/O Data */
if (ramdac->gpio_read) {
temp = 0xe0 | (ramdac->gpio_cntl & 0x1f); /* keep upper bits untouched */
ramdac->gpio_data = (ramdac->gpio_data & temp) | (ramdac->gpio_read(ramdac->gpio_cntl, ramdac->gpio_priv) & ~temp);
}
temp = ramdac->gpio_data;
break;
case 0x2c: /* PLL Address */
temp = ramdac->pll_addr;
break;
case 0x2d: /* Pixel clock PLL data */
switch (ramdac->pll_addr & 3) {
case 0:
temp = ramdac->pix.n;
break;
case 1:
temp = ramdac->pix.m;
break;
case 2:
temp = ramdac->pix.p;
break;
case 3:
temp = 0x40; /*PLL locked to frequency*/
break;
default:
break;
}
break;
case 0x2e: /* Memory Clock PLL Data */
switch ((ramdac->pll_addr >> 2) & 3) {
case 0:
temp = ramdac->mem.n;
break;
case 1:
temp = ramdac->mem.m;
break;
case 2:
temp = ramdac->mem.p;
break;
case 3:
temp = 0x40; /*PLL locked to frequency*/
break;
default:
break;
}
break;
case 0x2f: /* Loop Clock PLL Data */
switch ((ramdac->pll_addr >> 4) & 3) {
case 0:
temp = ramdac->loop.n;
break;
case 1:
temp = ramdac->loop.m;
break;
case 2:
temp = ramdac->loop.p;
break;
default:
break;
}
break;
case 0x39: /* MCLK/Loop Clock Control */
temp = ramdac->mclk;
break;
case 0x3f: /* ID */
temp = 0x26;
break;
default:
break;
}
break;
case 0x0b: /* Cursor RAM Data Register (RS value = 1011) */
index = ((svga->dac_addr - 1) & da_mask) | ((ramdac->ccr & 0x0c) << 6);
cd = (uint8_t *) ramdac->cursor64_data;
temp = cd[index];
svga->dac_addr = (svga->dac_addr + 1) & da_mask;
break;
case 0x0c: /* Cursor X Low Register (RS value = 1100) */
temp = ramdac->hwc_x & 0xff;
break;
case 0x0d: /* Cursor X High Register (RS value = 1101) */
temp = (ramdac->hwc_x >> 8) & 0xff;
break;
case 0x0e: /* Cursor Y Low Register (RS value = 1110) */
temp = ramdac->hwc_y & 0xff;
break;
case 0x0f: /* Cursor Y High Register (RS value = 1111) */
temp = (ramdac->hwc_y >> 8) & 0xff;
break;
default:
break;
}
return temp;
}
void
tvp3026_recalctimings(void *priv, svga_t *svga)
{
const tvp3026_ramdac_t *ramdac = (tvp3026_ramdac_t *) priv;
svga->interlace = !!(ramdac->ccr & 0x40);
/* TODO: Figure out gamma correction for 15/16 bpp color. */
svga->lut_map = !!((svga->bpp >= 15 && (svga->bpp != 24)) && (ramdac->true_color & 0xf0) != 0x00);
if (!(ramdac->clock_sel & 0x70)) {
if (ramdac->mcr != 0x98) {
svga->hdisp <<= 1;
svga->dots_per_clock <<= 1;
}
}
}
uint32_t
tvp3026_conv_16to32(svga_t* svga, uint16_t color, uint8_t bpp)
{
uint32_t ret = 0x00000000;
if (svga->lut_map) {
if (bpp == 15) {
uint8_t b = getcolr(svga->pallook[(color & 0x1f) << 3]);
uint8_t g = getcolg(svga->pallook[(color & 0x3e0) >> 2]);
uint8_t r = getcolb(svga->pallook[(color & 0x7c00) >> 7]);
ret = (video_15to32[color] & 0xFF000000) | makecol(r, g, b);
} else {
uint8_t b = getcolr(svga->pallook[(color & 0x1f) << 3]);
uint8_t g = getcolg(svga->pallook[(color & 0x7e0) >> 3]);
uint8_t r = getcolb(svga->pallook[(color & 0xf800) >> 8]);
ret = (video_16to32[color] & 0xFF000000) | makecol(r, g, b);
}
} else
ret = (bpp == 15) ? video_15to32[color] : video_16to32[color];
return ret;
}
void
tvp3026_hwcursor_draw(svga_t *svga, int displine)
{
int comb;
int b0;
int b1;
uint16_t dat[2];
int offset = svga->dac_hwcursor_latch.x + svga->dac_hwcursor_latch.xoff;
int pitch;
int bppl;
int mode;
int x_pos;
int y_pos;
uint32_t clr1;
uint32_t clr2;
uint32_t clr3;
uint32_t *p;
const uint8_t *cd;
tvp3026_ramdac_t *ramdac = (tvp3026_ramdac_t *) svga->ramdac;
clr1 = ramdac->extpallook[1];
clr2 = ramdac->extpallook[2];
clr3 = ramdac->extpallook[3];
/* The planes come in two parts, and each plane is 1bpp,
so a 32x32 cursor has 4 bytes per line, and a 64x64
cursor has 8 bytes per line. */
pitch = (svga->dac_hwcursor_latch.cur_xsize >> 3); /* Bytes per line. */
/* A 32x32 cursor has 128 bytes per line, and a 64x64
cursor has 512 bytes per line. */
bppl = (pitch * svga->dac_hwcursor_latch.cur_ysize); /* Bytes per plane. */
mode = ramdac->mode;
if (svga->interlace && svga->dac_hwcursor_oddeven)
svga->dac_hwcursor_latch.addr += pitch;
cd = (uint8_t *) ramdac->cursor64_data;
for (int x = 0; x < svga->dac_hwcursor_latch.cur_xsize; x += 16) {
dat[0] = (cd[svga->dac_hwcursor_latch.addr] << 8) | cd[svga->dac_hwcursor_latch.addr + 1];
dat[1] = (cd[svga->dac_hwcursor_latch.addr + bppl] << 8) | cd[svga->dac_hwcursor_latch.addr + bppl + 1];
for (uint8_t xx = 0; xx < 16; xx++) {
b0 = (dat[0] >> (15 - xx)) & 1;
b1 = (dat[1] >> (15 - xx)) & 1;
comb = (b0 | (b1 << 1));
y_pos = displine;
x_pos = (offset + svga->x_add) & 2047;
p = svga->monitor->target_buffer->line[y_pos];
if (offset >= svga->dac_hwcursor_latch.x) {
switch (mode) {
case 1: /* Three Color */
switch (comb) {
case 1:
p[x_pos] = clr1;
break;
case 2:
p[x_pos] = clr2;
break;
case 3:
p[x_pos] = clr3;
break;
default:
break;
}
break;
case 2: /* XGA */
switch (comb) {
case 0:
p[x_pos] = clr1;
break;
case 1:
p[x_pos] = clr2;
break;
case 3:
p[x_pos] ^= 0xffffff;
break;
default:
break;
}
break;
case 3: /* X-Windows */
switch (comb) {
case 2:
p[x_pos] = clr1;
break;
case 3:
p[x_pos] = clr2;
break;
default:
break;
}
break;
default:
break;
}
}
offset++;
}
svga->dac_hwcursor_latch.addr += 2;
}
if (svga->interlace && !svga->dac_hwcursor_oddeven)
svga->dac_hwcursor_latch.addr += pitch;
}
float
tvp3026_getclock(int clock, void *priv)
{
const tvp3026_ramdac_t *ramdac = (tvp3026_ramdac_t *) priv;
int n;
int m;
int pl;
float f_vco;
float f_pll;
if (clock == 0)
return 25175000.0;
if (clock == 1)
return 28322000.0;
/*Fvco = 8 x Fref x (65 - M) / (65 - N)*/
/*Fpll = Fvco / 2^P*/
n = ramdac->pix.n & 0x3f;
m = ramdac->pix.m & 0x3f;
pl = ramdac->pix.p & 0x03;
f_vco = 8.0f * 14318184 * (float) (65 - m) / (float) (65 - n);
f_pll = f_vco / (float) (1 << pl);
return f_pll;
}
void
tvp3026_gpio(uint8_t (*read)(uint8_t cntl, void *priv),
void (*write)(uint8_t cntl, uint8_t val, void *priv),
void *cb_priv, void *priv)
{
tvp3026_ramdac_t *ramdac = (tvp3026_ramdac_t *) priv;
ramdac->gpio_read = read;
ramdac->gpio_write = write;
ramdac->gpio_priv = cb_priv;
}
void *
tvp3026_ramdac_init(const device_t *info)
{
tvp3026_ramdac_t *ramdac = (tvp3026_ramdac_t *) malloc(sizeof(tvp3026_ramdac_t));
memset(ramdac, 0, sizeof(tvp3026_ramdac_t));
ramdac->type = info->local;
ramdac->latch_cntl = 0x06;
ramdac->true_color = 0x80;
ramdac->mcr = 0x98;
ramdac->clock_sel = 0x07;
ramdac->mclk = 0x18;
return ramdac;
}
static void
tvp3026_ramdac_close(void *priv)
{
tvp3026_ramdac_t *ramdac = (tvp3026_ramdac_t *) priv;
if (ramdac)
free(ramdac);
}
const device_t tvp3026_ramdac_device = {
.name = "TI TVP3026 RAMDAC",
.internal_name = "tvp3026_ramdac",
.flags = 0,
.local = 0,
.init = tvp3026_ramdac_init,
.close = tvp3026_ramdac_close,
.reset = NULL,
{ .available = NULL },
.speed_changed = NULL,
.force_redraw = NULL,
.config = NULL
};
``` | /content/code_sandbox/src/video/vid_tvp3026_ramdac.c | c | 2016-06-25T22:29:10 | 2024-08-16T19:09:21 | 86Box | 86Box/86Box | 2,616 | 6,990 |
```c
/*
* 86Box A hypervisor and IBM PC system emulator that specializes in
* running old operating systems and software designed for IBM
* PC systems and compatibles from 1981 through fairly recent
* system designs based on the PCI bus.
*
* This file is part of the 86Box distribution.
*
* Voodoo Banshee and 3 specific emulation.
*
*
*
* Authors: Sarah Walker, <path_to_url
*
*/
#include <assert.h>
#include <stdarg.h>
#include <stdio.h>
#include <stdint.h>
#include <string.h>
#include <stdlib.h>
#include <stddef.h>
#include <wchar.h>
#include <math.h>
#define HAVE_STDARG_H
#include <86box/86box.h>
#include "cpu.h"
#include <86box/machine.h>
#include <86box/device.h>
#include <86box/io.h>
#include <86box/mem.h>
#include <86box/pci.h>
#include <86box/rom.h>
#include <86box/timer.h>
#include <86box/device.h>
#include <86box/plat.h>
#include <86box/thread.h>
#include <86box/video.h>
#include <86box/i2c.h>
#include <86box/vid_ddc.h>
#include <86box/vid_svga.h>
#include <86box/vid_svga_render.h>
#include <86box/vid_voodoo_common.h>
#include <86box/vid_voodoo_display.h>
#include <86box/vid_voodoo_fifo.h>
#include <86box/vid_voodoo_regs.h>
#include <86box/vid_voodoo_render.h>
#define ROM_BANSHEE "roms/video/voodoo/Pci_sg.rom"
#define ROM_CREATIVE_BANSHEE "roms/video/voodoo/BlasterPCI.rom"
#define ROM_VOODOO3_1000 "roms/video/voodoo/1k11sg.rom"
#define ROM_VOODOO3_2000 "roms/video/voodoo/2k11sd.rom"
#define ROM_VOODOO3_3000 "roms/video/voodoo/3k12sd.rom"
#define ROM_VOODOO3_3500_AGP_NTSC "roms/video/voodoo/35k05n.rom"
#define ROM_VOODOO3_3500_AGP_PAL "roms/video/voodoo/35k05p.rom"
#define ROM_VOODOO3_3500_AGP_COMPAQ "roms/video/voodoo/V3_3500_AGP_SD_2.15.05_Compaq.rom"
#define ROM_VOODOO3_3500_SE_AGP "roms/video/voodoo/V3_3500_AGP_SD_2.15.06_NTSC_Falcon_Northwest.rom"
#define ROM_VOODOO3_3500_SI_AGP "roms/video/voodoo/V3_3500_AGP_SD_2.15.07_PAL_3500TV-SI.rom"
#define ROM_VELOCITY_100 "roms/video/voodoo/Velocity100.VBI"
#define ROM_VELOCITY_200 "roms/video/voodoo/Velocity200sg.rom"
static video_timings_t timing_banshee = { .type = VIDEO_PCI, .write_b = 2, .write_w = 2, .write_l = 1, .read_b = 20, .read_w = 20, .read_l = 21 };
static video_timings_t timing_banshee_agp = { .type = VIDEO_AGP, .write_b = 2, .write_w = 2, .write_l = 1, .read_b = 20, .read_w = 20, .read_l = 21 };
#ifdef CLAMP
# undef CLAMP
#endif
static uint8_t vb_filter_v1_rb[256][256];
static uint8_t vb_filter_v1_g[256][256];
static uint8_t vb_filter_bx_rb[256][256];
static uint8_t vb_filter_bx_g[256][256];
enum {
TYPE_BANSHEE = 0,
TYPE_V3_1000,
TYPE_V3_2000,
TYPE_V3_3000,
TYPE_V3_3500,
TYPE_V3_3500_COMPAQ,
TYPE_V3_3500_SI,
TYPE_VELOCITY100,
TYPE_VELOCITY200
};
typedef struct banshee_t {
svga_t svga;
rom_t bios_rom;
uint8_t pci_regs[256];
uint32_t memBaseAddr0;
uint32_t memBaseAddr1;
uint32_t ioBaseAddr;
uint32_t agpInit0;
uint32_t dramInit0, dramInit1;
uint32_t lfbMemoryConfig;
uint32_t miscInit0, miscInit1;
uint32_t pciInit0;
uint32_t vgaInit0, vgaInit1;
uint32_t command_2d;
uint32_t srcBaseAddr_2d;
uint32_t pllCtrl0, pllCtrl1, pllCtrl2;
uint32_t dacMode;
int dacAddr;
uint32_t vidDesktopOverlayStride;
uint32_t vidDesktopStartAddr;
uint32_t vidProcCfg;
uint32_t vidScreenSize;
uint32_t vidSerialParallelPort;
uint32_t agpReqSize;
uint32_t agpHostAddressHigh;
uint32_t agpHostAddressLow;
uint32_t agpGraphicsAddress;
uint32_t agpGraphicsStride;
int overlay_pix_fmt;
uint32_t hwCurPatAddr, hwCurLoc, hwCurC0, hwCurC1;
uint32_t intrCtrl;
uint32_t overlay_buffer[2][4096];
mem_mapping_t linear_mapping;
mem_mapping_t reg_mapping_low; /*0000000-07fffff*/
mem_mapping_t reg_mapping_high; /*0c00000-1ffffff - Windows 2000 puts the BIOS ROM in between these two areas*/
voodoo_t *voodoo;
uint32_t desktop_addr;
int desktop_y;
uint32_t desktop_stride_tiled;
int type, agp;
int has_bios, vblank_irq;
uint8_t pci_slot;
uint8_t irq_state;
void *i2c, *i2c_ddc, *ddc;
} banshee_t;
enum {
Init_status = 0x00,
Init_pciInit0 = 0x04,
Init_lfbMemoryConfig = 0x0c,
Init_miscInit0 = 0x10,
Init_miscInit1 = 0x14,
Init_dramInit0 = 0x18,
Init_dramInit1 = 0x1c,
Init_agpInit0 = 0x20,
Init_vgaInit0 = 0x28,
Init_vgaInit1 = 0x2c,
Init_2dCommand = 0x30,
Init_2dSrcBaseAddr = 0x34,
Init_strapInfo = 0x38,
PLL_pllCtrl0 = 0x40,
PLL_pllCtrl1 = 0x44,
PLL_pllCtrl2 = 0x48,
DAC_dacMode = 0x4c,
DAC_dacAddr = 0x50,
DAC_dacData = 0x54,
Video_vidProcCfg = 0x5c,
Video_maxRgbDelta = 0x58,
Video_hwCurPatAddr = 0x60,
Video_hwCurLoc = 0x64,
Video_hwCurC0 = 0x68,
Video_hwCurC1 = 0x6c,
Video_vidSerialParallelPort = 0x78,
Video_vidScreenSize = 0x98,
Video_vidOverlayStartCoords = 0x9c,
Video_vidOverlayEndScreenCoords = 0xa0,
Video_vidOverlayDudx = 0xa4,
Video_vidOverlayDudxOffsetSrcWidth = 0xa8,
Video_vidOverlayDvdy = 0xac,
Video_vidOverlayDvdyOffset = 0xe0,
Video_vidDesktopStartAddr = 0xe4,
Video_vidDesktopOverlayStride = 0xe8,
};
enum {
cmdBaseAddr0 = 0x20,
cmdBaseSize0 = 0x24,
cmdBump0 = 0x28,
cmdRdPtrL0 = 0x2c,
cmdRdPtrH0 = 0x30,
cmdAMin0 = 0x34,
cmdAMax0 = 0x3c,
cmdStatus0 = 0x40,
cmdFifoDepth0 = 0x44,
cmdHoleCnt0 = 0x48,
Agp_agpReqSize = 0x00,
Agp_agpHostAddressLow = 0x04,
Agp_agpHostAddressHigh = 0x08,
Agp_agpGraphicsAddress = 0x0C,
Agp_agpGraphicsStride = 0x10,
};
#define VGAINIT0_RAMDAC_8BIT (1 << 2)
#define VGAINIT0_EXTENDED_SHIFT_OUT (1 << 12)
#define VIDPROCCFG_VIDPROC_ENABLE (1 << 0)
#define VIDPROCCFG_CURSOR_MODE (1 << 1)
#define VIDPROCCFG_INTERLACE (1 << 3)
#define VIDPROCCFG_HALF_MODE (1 << 4)
#define VIDPROCCFG_OVERLAY_ENABLE (1 << 8)
#define VIDPROCCFG_DESKTOP_CLUT_BYPASS (1 << 10)
#define VIDPROCCFG_OVERLAY_CLUT_BYPASS (1 << 11)
#define VIDPROCCFG_DESKTOP_CLUT_SEL (1 << 12)
#define VIDPROCCFG_OVERLAY_CLUT_SEL (1 << 13)
#define VIDPROCCFG_H_SCALE_ENABLE (1 << 14)
#define VIDPROCCFG_V_SCALE_ENABLE (1 << 15)
#define VIDPROCCFG_FILTER_MODE_MASK (3 << 16)
#define VIDPROCCFG_FILTER_MODE_POINT (0 << 16)
#define VIDPROCCFG_FILTER_MODE_DITHER_2X2 (1 << 16)
#define VIDPROCCFG_FILTER_MODE_DITHER_4X4 (2 << 16)
#define VIDPROCCFG_FILTER_MODE_BILINEAR (3 << 16)
#define VIDPROCCFG_DESKTOP_PIX_FORMAT ((banshee->vidProcCfg >> 18) & 7)
#define VIDPROCCFG_OVERLAY_PIX_FORMAT ((banshee->vidProcCfg >> 21) & 7)
#define VIDPROCCFG_OVERLAY_PIX_FORMAT_SHIFT (21)
#define VIDPROCCFG_OVERLAY_PIX_FORMAT_MASK (7 << VIDPROCCFG_OVERLAY_PIX_FORMAT_SHIFT)
#define VIDPROCCFG_DESKTOP_TILE (1 << 24)
#define VIDPROCCFG_OVERLAY_TILE (1 << 25)
#define VIDPROCCFG_2X_MODE (1 << 26)
#define VIDPROCCFG_HWCURSOR_ENA (1 << 27)
#define OVERLAY_FMT_565 (1)
#define OVERLAY_FMT_YUYV422 (5)
#define OVERLAY_FMT_UYVY422 (6)
#define OVERLAY_FMT_565_DITHER (7)
#define OVERLAY_START_X_MASK (0xfff)
#define OVERLAY_START_Y_SHIFT (12)
#define OVERLAY_START_Y_MASK (0xfff << OVERLAY_START_Y_SHIFT)
#define OVERLAY_END_X_MASK (0xfff)
#define OVERLAY_END_Y_SHIFT (12)
#define OVERLAY_END_Y_MASK (0xfff << OVERLAY_END_Y_SHIFT)
#define OVERLAY_SRC_WIDTH_SHIFT (19)
#define OVERLAY_SRC_WIDTH_MASK (0x1fff << OVERLAY_SRC_WIDTH_SHIFT)
#define VID_STRIDE_OVERLAY_SHIFT (16)
#define VID_STRIDE_OVERLAY_MASK (0x7fff << VID_STRIDE_OVERLAY_SHIFT)
#define VID_DUDX_MASK (0xffffff)
#define VID_DVDY_MASK (0xffffff)
#define PIX_FORMAT_8 0
#define PIX_FORMAT_RGB565 1
#define PIX_FORMAT_RGB24 2
#define PIX_FORMAT_RGB32 3
#define VIDSERIAL_DDC_EN (1 << 18)
#define VIDSERIAL_DDC_DCK_W (1 << 19)
#define VIDSERIAL_DDC_DDA_W (1 << 20)
#define VIDSERIAL_DDC_DCK_R (1 << 21)
#define VIDSERIAL_DDC_DDA_R (1 << 22)
#define VIDSERIAL_I2C_EN (1 << 23)
#define VIDSERIAL_I2C_SCK_W (1 << 24)
#define VIDSERIAL_I2C_SDA_W (1 << 25)
#define VIDSERIAL_I2C_SCK_R (1 << 26)
#define VIDSERIAL_I2C_SDA_R (1 << 27)
#define MISCINIT0_Y_ORIGIN_SWAP_SHIFT (18)
#define MISCINIT0_Y_ORIGIN_SWAP_MASK (0xfff << MISCINIT0_Y_ORIGIN_SWAP_SHIFT)
#ifdef ENABLE_BANSHEE_LOG
int banshee_do_log = ENABLE_BANSHEE_LOG;
static void
banshee_log(const char *fmt, ...)
{
va_list ap;
if (banshee_do_log) {
va_start(ap, fmt);
pclog_ex(fmt, ap);
va_end(ap);
}
}
#else
# define banshee_log(fmt, ...)
#endif
static uint32_t banshee_status(banshee_t *banshee);
static int
banshee_vga_vsync_enabled(banshee_t *banshee)
{
if (!(banshee->svga.crtc[0x11] & 0x20) && (banshee->svga.crtc[0x11] & 0x10) && ((banshee->pciInit0 >> 18) & 1) != 0)
return 1;
return 0;
}
static void
banshee_update_irqs(banshee_t *banshee)
{
if (banshee->vblank_irq > 0 && banshee_vga_vsync_enabled(banshee)) {
pci_set_irq(banshee->pci_slot, PCI_INTA, &banshee->irq_state);
} else {
pci_clear_irq(banshee->pci_slot, PCI_INTA, &banshee->irq_state);
}
}
static void
banshee_vblank_start(svga_t *svga)
{
banshee_t *banshee = (banshee_t *) svga->priv;
if (banshee->vblank_irq >= 0) {
banshee->vblank_irq = 1;
banshee_update_irqs(banshee);
}
}
static void
banshee_out(uint16_t addr, uint8_t val, void *priv)
{
banshee_t *banshee = (banshee_t *) priv;
svga_t *svga = &banshee->svga;
uint8_t old;
#if 0
if (addr != 0x3c9)
banshee_log("banshee_out : %04X %02X %04X:%04X\n", addr, val, CS,cpu_state.pc);
#endif
if (((addr & 0xfff0) == 0x3d0 || (addr & 0xfff0) == 0x3b0) && !(svga->miscout & 1))
addr ^= 0x60;
switch (addr) {
case 0x3D4:
svga->crtcreg = val & 0x3f;
return;
case 0x3D5:
if ((svga->crtcreg < 7) && (svga->crtc[0x11] & 0x80))
return;
if ((svga->crtcreg == 7) && (svga->crtc[0x11] & 0x80))
val = (svga->crtc[7] & ~0x10) | (val & 0x10);
old = svga->crtc[svga->crtcreg];
svga->crtc[svga->crtcreg] = val;
if (old != val) {
if (svga->crtcreg == 0x11) {
if (!(val & 0x10)) {
if (banshee->vblank_irq > 0)
banshee->vblank_irq = -1;
} else if (banshee->vblank_irq < 0) {
banshee->vblank_irq = 0;
}
banshee_update_irqs(banshee);
if ((val & ~0x30) == (old & ~0x30))
old = val;
}
if (svga->crtcreg < 0xe || svga->crtcreg > 0x11 || (svga->crtcreg == 0x11 && old != val)) {
if ((svga->crtcreg == 0xc) || (svga->crtcreg == 0xd)) {
svga->fullchange = 3;
svga->ma_latch = ((svga->crtc[0xc] << 8) | svga->crtc[0xd]) + ((svga->crtc[8] & 0x60) >> 5);
} else {
svga->fullchange = changeframecount;
svga_recalctimings(svga);
}
}
}
break;
default:
break;
}
svga_out(addr, val, svga);
}
static uint8_t
banshee_in(uint16_t addr, void *priv)
{
banshee_t *banshee = (banshee_t *) priv;
svga_t *svga = &banshee->svga;
uint8_t temp;
#if 0
if (addr != 0x3da)
banshee_log("banshee_in : %04X ", addr);
#endif
if (((addr & 0xfff0) == 0x3d0 || (addr & 0xfff0) == 0x3b0) && !(svga->miscout & 1))
addr ^= 0x60;
switch (addr) {
case 0x3c2:
if ((svga->vgapal[0].r + svga->vgapal[0].g + svga->vgapal[0].b) >= 0x40)
temp = 0;
else
temp = 0x10;
if (banshee->vblank_irq > 0)
temp |= 0x80;
break;
case 0x3D4:
temp = svga->crtcreg;
break;
case 0x3D5:
temp = svga->crtc[svga->crtcreg];
break;
default:
temp = svga_in(addr, svga);
break;
}
#if 0
if (addr != 0x3da)
banshee_log("%02X %04X:%04X %i\n", temp, CS,cpu_state.pc, ins);
#endif
return temp;
}
static void
banshee_updatemapping(banshee_t *banshee)
{
svga_t *svga = &banshee->svga;
if (!(banshee->pci_regs[PCI_REG_COMMAND] & PCI_COMMAND_MEM)) {
// banshee_log("Update mapping - PCI disabled\n");
mem_mapping_disable(&svga->mapping);
mem_mapping_disable(&banshee->linear_mapping);
mem_mapping_disable(&banshee->reg_mapping_low);
mem_mapping_disable(&banshee->reg_mapping_high);
return;
}
banshee_log("Update mapping - bank %02X ", svga->gdcreg[6] & 0xc);
switch (svga->gdcreg[6] & 0xc) { /*Banked framebuffer*/
case 0x0: /*128k at A0000*/
mem_mapping_set_addr(&svga->mapping, 0xa0000, 0x20000);
svga->banked_mask = 0xffff;
break;
case 0x4: /*64k at A0000*/
mem_mapping_set_addr(&svga->mapping, 0xa0000, 0x10000);
svga->banked_mask = 0xffff;
break;
case 0x8: /*32k at B0000*/
mem_mapping_set_addr(&svga->mapping, 0xb0000, 0x08000);
svga->banked_mask = 0x7fff;
break;
case 0xC: /*32k at B8000*/
mem_mapping_set_addr(&svga->mapping, 0xb8000, 0x08000);
svga->banked_mask = 0x7fff;
break;
default:
break;
}
banshee_log("Linear framebuffer %08X ", banshee->memBaseAddr1);
mem_mapping_set_addr(&banshee->linear_mapping, banshee->memBaseAddr1, 32 << 20);
banshee_log("registers %08X\n", banshee->memBaseAddr0);
mem_mapping_set_addr(&banshee->reg_mapping_low, banshee->memBaseAddr0, 8 << 20);
mem_mapping_set_addr(&banshee->reg_mapping_high, banshee->memBaseAddr0 + 0xc00000, 20 << 20);
}
uint32_t
banshee_conv_16to32(svga_t* svga, uint16_t color, uint8_t bpp)
{
banshee_t *banshee = (banshee_t *) svga->priv;
uint32_t ret = 0x00000000;
uint16_t src_b = (color & 0x1f) << 3;
uint16_t src_g = (color & 0x7e0) >> 3;
uint16_t src_r = (color & 0xf800) >> 8;
if (banshee->vidProcCfg & VIDPROCCFG_DESKTOP_CLUT_SEL) {
src_b += 256;
src_g += 256;
src_r += 256;
}
if (svga->lut_map) {
uint8_t b = getcolr(svga->pallook[src_b]);
uint8_t g = getcolg(svga->pallook[src_g]);
uint8_t r = getcolb(svga->pallook[src_r]);
ret = (video_16to32[color] & 0xFF000000) | makecol(r, g, b);
} else
ret = video_16to32[color];
return ret;
}
static void
banshee_render_16bpp_tiled(svga_t *svga)
{
banshee_t *banshee = (banshee_t *) svga->priv;
uint32_t *p = &(svga->monitor->target_buffer->line[svga->displine + svga->y_add])[svga->x_add];
uint32_t addr;
int drawn = 0;
if ((svga->displine + svga->y_add) < 0)
return;
if (banshee->vidProcCfg & VIDPROCCFG_HALF_MODE)
addr = banshee->desktop_addr + ((banshee->desktop_y >> 1) & 31) * 128 + ((banshee->desktop_y >> 6) * banshee->desktop_stride_tiled);
else
addr = banshee->desktop_addr + (banshee->desktop_y & 31) * 128 + ((banshee->desktop_y >> 5) * banshee->desktop_stride_tiled);
if (addr >= svga->vram_max)
return;
for (int x = 0; x < svga->hdisp; x += 64) {
if (svga->hwcursor_on || svga->overlay_on)
svga->changedvram[addr >> 12] = 2;
if (svga->changedvram[addr >> 12] || svga->fullchange) {
const uint16_t *vram_p = (uint16_t *) &svga->vram[addr & svga->vram_display_mask];
for (uint8_t xx = 0; xx < 64; xx++)
*p++ = banshee_conv_16to32(svga, *vram_p++, 16);
drawn = 1;
} else
p += 64;
addr += 128 * 32;
}
if (drawn) {
if (svga->firstline_draw == 2000)
svga->firstline_draw = svga->displine;
svga->lastline_draw = svga->displine;
}
banshee->desktop_y++;
}
static void
banshee_recalctimings(svga_t *svga)
{
banshee_t *banshee = (banshee_t *) svga->priv;
const voodoo_t *voodoo = banshee->voodoo;
/*7 R/W Horizontal Retrace End bit 5. -
6 R/W Horizontal Retrace Start bit 8 0x4
5 R/W Horizontal Blank End bit 6. -
4 R/W Horizontal Blank Start bit 8. 0x3 ---- Erratum: Actually, 0x02!
3 R/W Reserved. -
2 R/W Horizontal Display Enable End bit 8. 0x1
1 R/W Reserved. -
0 R/W Horizontal Total bit 8. 0x0*/
if (svga->crtc[0x1a] & 0x01)
svga->htotal += 0x100;
if (svga->crtc[0x1a] & 0x04)
svga->hdisp += 0x100;
if (banshee->vidProcCfg & VIDPROCCFG_VIDPROC_ENABLE) {
/* Video processing mode - assume timings akin to Cirrus' special blanking mode,
that is, no overscan and relying on display end to blank. */
if (banshee->vgaInit0 & 0x40) {
svga->hblankstart = svga->crtc[1]/* + ((svga->crtc[3] >> 5) & 3)*/ +
(((svga->crtc[0x1a] & 0x04) >> 2) << 8);
svga->hblank_end_mask = 0x0000007f;
} else {
svga->hblankstart = svga->crtc[1]/* + ((svga->crtc[3] >> 5) & 3)*/;
svga->hblank_end_mask = 0x0000003f;
}
svga->hblank_end_val = svga->htotal - 1 /* + ((svga->crtc[3] >> 5) & 3)*/;
/* In this mode, the dots per clock are always 8 or 16, never 9 or 18. */
if (!svga->scrblank && svga->attr_palette_enable)
svga->dots_per_clock = (svga->seqregs[1] & 8) ? 16 : 8;
svga->monitor->mon_overscan_y = 0;
svga->monitor->mon_overscan_x = 0;
/* Also make sure vertical blanking starts on display end. */
svga->vblankstart = svga->dispend;
svga->linedbl = 0;
} else {
if (banshee->vgaInit0 & 0x40) {
svga->hblankstart = (((svga->crtc[0x1a] & 0x10) >> 4) << 8) + svga->crtc[2];
svga->hblank_end_val = (svga->crtc[3] & 0x1f) | (((svga->crtc[5] & 0x80) >> 7) << 5) |
(((svga->crtc[0x1a] & 0x20) >> 5) << 6);
svga->hblank_end_mask = 0x0000007f;
} else {
svga->hblankstart = svga->crtc[2];
svga->hblank_end_val = (svga->crtc[3] & 0x1f) | (((svga->crtc[5] & 0x80) >> 7) << 5);
svga->hblank_end_mask = 0x0000003f;
}
}
/*6 R/W Vertical Retrace Start bit 10 0x10
5 R/W Reserved. -
4 R/W Vertical Blank Start bit 10. 0x15
3 R/W Reserved. -
2 R/W Vertical Display Enable End bit 10 0x12
1 R/W Reserved. -
0 R/W Vertical Total bit 10. 0x6*/
if (svga->crtc[0x1b] & 0x01)
svga->vtotal += 0x400;
if (svga->crtc[0x1b] & 0x04)
svga->dispend += 0x400;
if (svga->crtc[0x1b] & 0x10)
svga->vblankstart += 0x400;
if (svga->crtc[0x1b] & 0x40)
svga->vsyncstart += 0x400;
#if 0
banshee_log("svga->hdisp=%i\n", svga->hdisp);
#endif
svga->interlace = 0;
if (banshee->vgaInit0 & VGAINIT0_EXTENDED_SHIFT_OUT) {
switch (VIDPROCCFG_DESKTOP_PIX_FORMAT) {
case PIX_FORMAT_8:
svga->render = svga_render_8bpp_highres;
svga->bpp = 8;
break;
case PIX_FORMAT_RGB565:
svga->render = (banshee->vidProcCfg & VIDPROCCFG_DESKTOP_TILE) ? banshee_render_16bpp_tiled : svga_render_16bpp_highres;
svga->bpp = 16;
break;
case PIX_FORMAT_RGB24:
svga->render = svga_render_24bpp_highres;
svga->bpp = 24;
break;
case PIX_FORMAT_RGB32:
svga->render = svga_render_32bpp_highres;
svga->bpp = 32;
break;
default:
fatal("Unknown pixel format %08x (vgaInit0=%08x)\n", VIDPROCCFG_DESKTOP_PIX_FORMAT, banshee->vgaInit0);
}
if (!(banshee->vidProcCfg & VIDPROCCFG_DESKTOP_TILE) && (banshee->vidProcCfg & VIDPROCCFG_HALF_MODE))
svga->rowcount = 1;
else
svga->rowcount = 0;
if (banshee->vidProcCfg & VIDPROCCFG_DESKTOP_TILE)
svga->rowoffset = ((banshee->vidDesktopOverlayStride & 0x3fff) * 128) >> 3;
else
svga->rowoffset = (banshee->vidDesktopOverlayStride & 0x3fff) >> 3;
svga->ma_latch = banshee->vidDesktopStartAddr >> 2;
banshee->desktop_stride_tiled = (banshee->vidDesktopOverlayStride & 0x3fff) * 128 * 32;
#if 0
banshee_log("Extended shift out %i rowoffset=%i %02x\n", VIDPROCCFG_DESKTOP_PIX_FORMAT, svga->rowoffset, svga->crtc[1]);
#endif
svga->char_width = 8;
svga->split = 99999;
if (banshee->vidProcCfg & VIDPROCCFG_2X_MODE) {
svga->hdisp *= 2;
svga->dots_per_clock *= 2;
}
svga->interlace = !!(banshee->vidProcCfg & VIDPROCCFG_INTERLACE);
svga->overlay.ena = banshee->vidProcCfg & VIDPROCCFG_OVERLAY_ENABLE;
svga->overlay.x = voodoo->overlay.start_x;
svga->overlay.y = voodoo->overlay.start_y;
svga->overlay.cur_xsize = voodoo->overlay.size_x;
svga->overlay.cur_ysize = voodoo->overlay.size_y;
svga->overlay.pitch = (banshee->vidDesktopOverlayStride & VID_STRIDE_OVERLAY_MASK) >> VID_STRIDE_OVERLAY_SHIFT;
if (banshee->vidProcCfg & VIDPROCCFG_OVERLAY_TILE)
svga->overlay.pitch *= 128 * 32;
if (svga->overlay.cur_xsize <= 0 || svga->overlay.cur_ysize <= 0)
svga->overlay.ena = 0;
if (svga->overlay.ena) {
#if 0
banshee_log("Overlay enabled : start=%i,%i end=%i,%i size=%i,%i pitch=%x\n",
voodoo->overlay.start_x, voodoo->overlay.start_y,
voodoo->overlay.end_x, voodoo->overlay.end_y,
voodoo->overlay.size_x, voodoo->overlay.size_y,
svga->overlay.pitch);
#endif
if (!voodoo->overlay.start_x && !voodoo->overlay.start_y && svga->hdisp == voodoo->overlay.size_x && svga->dispend == voodoo->overlay.size_y) {
/*Overlay is full screen, so don't bother rendering the desktop
behind it*/
svga->render = svga_render_null;
svga->bpp = 0;
}
}
} else {
#if 0
banshee_log("Normal shift out\n");
#endif
svga->bpp = 8;
}
svga->fb_only = (banshee->vidProcCfg & VIDPROCCFG_VIDPROC_ENABLE);
if (((svga->miscout >> 2) & 3) == 3) {
int k = banshee->pllCtrl0 & 3;
int m = (banshee->pllCtrl0 >> 2) & 0x3f;
int n = (banshee->pllCtrl0 >> 8) & 0xff;
double freq = (((double) n + 2) / (((double) m + 2) * (double) (1 << k))) * 14318184.0;
svga->clock = (cpuclock * (float) (1ULL << 32)) / freq;
#if 0
svga->clock = cpuclock / freq;
#endif
#if 0
banshee_log("svga->clock = %g %g m=%i k=%i n=%i\n", freq, freq / 1000000.0, m, k, n);
#endif
}
}
static void
banshee_ext_out(uint16_t addr, uint8_t val, void *priv)
{
#if 0
banshee_t *banshee = (banshee_t *)priv;
svga_t *svga = &banshee->svga;
#endif
#if 0
banshee_log("banshee_ext_out: addr=%04x val=%02x\n", addr, val);
#endif
switch (addr & 0xff) {
case 0xb0:
case 0xb1:
case 0xb2:
case 0xb3:
case 0xb4:
case 0xb5:
case 0xb6:
case 0xb7:
case 0xb8:
case 0xb9:
case 0xba:
case 0xbb:
case 0xbc:
case 0xbd:
case 0xbe:
case 0xbf:
case 0xc0:
case 0xc1:
case 0xc2:
case 0xc3:
case 0xc4:
case 0xc5:
case 0xc6:
case 0xc7:
case 0xc8:
case 0xc9:
case 0xca:
case 0xcb:
case 0xcc:
case 0xcd:
case 0xce:
case 0xcf:
case 0xd0:
case 0xd1:
case 0xd2:
case 0xd3:
case 0xd4:
case 0xd5:
case 0xd6:
case 0xd7:
case 0xd8:
case 0xd9:
case 0xda:
case 0xdb:
case 0xdc:
case 0xdd:
case 0xde:
case 0xdf:
banshee_out((addr & 0xff) + 0x300, val, priv);
break;
default:
banshee_log("bad banshee_ext_out: addr=%04x val=%02x\n", addr, val);
}
}
static void
banshee_ext_outl(uint16_t addr, uint32_t val, void *priv)
{
banshee_t *banshee = (banshee_t *) priv;
voodoo_t *voodoo = banshee->voodoo;
svga_t *svga = &banshee->svga;
#if 0
banshee_log("banshee_ext_outl: addr=%04x val=%08x %04x(%08x):%08x\n", addr, val, CS,cs,cpu_state.pc);
#endif
switch (addr & 0xff) {
case Init_pciInit0:
banshee->pciInit0 = val;
voodoo->read_time = (banshee->agp ? agp_nonburst_time : pci_nonburst_time) + (banshee->agp ? agp_burst_time : pci_burst_time) * ((val & 0x100) ? 2 : 1);
voodoo->burst_time = (banshee->agp ? agp_burst_time : pci_burst_time) * ((val & 0x200) ? 1 : 0);
voodoo->write_time = (banshee->agp ? agp_nonburst_time : pci_nonburst_time) + voodoo->burst_time;
break;
case Init_lfbMemoryConfig:
banshee->lfbMemoryConfig = val;
#if 0
banshee_log("lfbMemoryConfig=%08x\n", val);
#endif
voodoo->tile_base = (val & 0x1fff) << 12;
voodoo->tile_stride = 1024 << ((val >> 13) & 7);
voodoo->tile_stride_shift = 10 + ((val >> 13) & 7);
voodoo->tile_x = ((val >> 16) & 0x7f) * 128;
voodoo->tile_x_real = ((val >> 16) & 0x7f) * 128 * 32;
break;
case Init_miscInit0:
banshee->miscInit0 = val;
voodoo->y_origin_swap = (val & MISCINIT0_Y_ORIGIN_SWAP_MASK) >> MISCINIT0_Y_ORIGIN_SWAP_SHIFT;
break;
case Init_miscInit1:
banshee->miscInit1 = val;
break;
case Init_dramInit0:
banshee->dramInit0 = val;
break;
case Init_dramInit1:
banshee->dramInit1 = val;
break;
case Init_agpInit0:
banshee->agpInit0 = val;
break;
case Init_2dCommand:
banshee->command_2d = val;
break;
case Init_2dSrcBaseAddr:
banshee->srcBaseAddr_2d = val;
break;
case Init_vgaInit0:
banshee->vgaInit0 = val;
svga_set_ramdac_type(svga, (val & VGAINIT0_RAMDAC_8BIT ? RAMDAC_8BIT : RAMDAC_6BIT));
svga_recalctimings(svga);
break;
case Init_vgaInit1:
banshee->vgaInit1 = val;
svga->write_bank = (val & 0x3ff) << 15;
svga->read_bank = ((val >> 10) & 0x3ff) << 15;
svga->packed_chain4 = !!(val & 0x00100000);
break;
case PLL_pllCtrl0:
banshee->pllCtrl0 = val;
break;
case PLL_pllCtrl1:
banshee->pllCtrl1 = val;
break;
case PLL_pllCtrl2:
banshee->pllCtrl2 = val;
break;
case DAC_dacMode:
banshee->dacMode = val;
svga->dpms = !!(val & 0x0a);
svga_recalctimings(svga);
break;
case DAC_dacAddr:
banshee->dacAddr = val & 0x1ff;
break;
case DAC_dacData:
svga->pallook[banshee->dacAddr] = val & 0xffffff;
svga->fullchange = changeframecount;
break;
case Video_vidProcCfg:
banshee->vidProcCfg = val;
#if 0
banshee_log("vidProcCfg=%08x\n", val);
#endif
banshee->overlay_pix_fmt = (val & VIDPROCCFG_OVERLAY_PIX_FORMAT_MASK) >> VIDPROCCFG_OVERLAY_PIX_FORMAT_SHIFT;
svga->hwcursor.ena = val & VIDPROCCFG_HWCURSOR_ENA;
svga->fullchange = changeframecount;
svga->lut_map = !(val & VIDPROCCFG_DESKTOP_CLUT_BYPASS) && (svga->bpp < 24);
svga_recalctimings(svga);
break;
case Video_maxRgbDelta:
banshee->voodoo->scrfilterThreshold = val;
if (val > 0x00)
banshee->voodoo->scrfilterEnabled = 1;
else
banshee->voodoo->scrfilterEnabled = 0;
voodoo_threshold_check(banshee->voodoo);
banshee_log("Banshee Filter: %06x\n", val);
break;
case Video_hwCurPatAddr:
banshee->hwCurPatAddr = val;
svga->hwcursor.addr = (val & 0xfffff0) + (svga->hwcursor.yoff * 16);
break;
case Video_hwCurLoc:
banshee->hwCurLoc = val;
svga->hwcursor.x = (val & 0x7ff) - 64;
svga->hwcursor.y = ((val >> 16) & 0x7ff) - 64;
if (svga->hwcursor.y < 0) {
svga->hwcursor.yoff = -svga->hwcursor.y;
svga->hwcursor.y = 0;
} else
svga->hwcursor.yoff = 0;
svga->hwcursor.addr = (banshee->hwCurPatAddr & 0xfffff0) + (svga->hwcursor.yoff * 16);
svga->hwcursor.cur_xsize = 64;
svga->hwcursor.cur_ysize = 64;
#if 0
banshee_log("hwCurLoc %08x %i\n", val, svga->hwcursor.y);
#endif
break;
case Video_hwCurC0:
banshee->hwCurC0 = val;
break;
case Video_hwCurC1:
banshee->hwCurC1 = val;
break;
case Video_vidSerialParallelPort:
banshee->vidSerialParallelPort = val;
#if 0
banshee_log("vidSerialParallelPort: write %08x %08x %04x(%08x):%08x\n", val, val & (VIDSERIAL_DDC_DCK_W | VIDSERIAL_DDC_DDA_W), CS,cs,cpu_state.pc);
#endif
i2c_gpio_set(banshee->i2c_ddc, !!(val & VIDSERIAL_DDC_DCK_W), !!(val & VIDSERIAL_DDC_DDA_W));
i2c_gpio_set(banshee->i2c, !!(val & VIDSERIAL_I2C_SCK_W), !!(val & VIDSERIAL_I2C_SDA_W));
break;
case Video_vidScreenSize:
banshee->vidScreenSize = val;
voodoo->h_disp = (val & 0xfff) + 1;
voodoo->v_disp = (val >> 12) & 0xfff;
break;
case Video_vidOverlayStartCoords:
voodoo->overlay.vidOverlayStartCoords = val;
voodoo->overlay.start_x = val & OVERLAY_START_X_MASK;
voodoo->overlay.start_y = (val & OVERLAY_START_Y_MASK) >> OVERLAY_START_Y_SHIFT;
voodoo->overlay.size_x = voodoo->overlay.end_x - voodoo->overlay.start_x;
voodoo->overlay.size_y = voodoo->overlay.end_y - voodoo->overlay.start_y;
svga_recalctimings(svga);
break;
case Video_vidOverlayEndScreenCoords:
voodoo->overlay.vidOverlayEndScreenCoords = val;
voodoo->overlay.end_x = val & OVERLAY_END_X_MASK;
voodoo->overlay.end_y = (val & OVERLAY_END_Y_MASK) >> OVERLAY_END_Y_SHIFT;
voodoo->overlay.size_x = (voodoo->overlay.end_x - voodoo->overlay.start_x) + 1;
voodoo->overlay.size_y = (voodoo->overlay.end_y - voodoo->overlay.start_y) + 1;
svga_recalctimings(svga);
break;
case Video_vidOverlayDudx:
voodoo->overlay.vidOverlayDudx = val & VID_DUDX_MASK;
#if 0
banshee_log("vidOverlayDudx=%08x\n", val);
#endif
break;
case Video_vidOverlayDudxOffsetSrcWidth:
voodoo->overlay.vidOverlayDudxOffsetSrcWidth = val;
voodoo->overlay.overlay_bytes = (val & OVERLAY_SRC_WIDTH_MASK) >> OVERLAY_SRC_WIDTH_SHIFT;
#if 0
banshee_log("vidOverlayDudxOffsetSrcWidth=%08x\n", val);
#endif
break;
case Video_vidOverlayDvdy:
voodoo->overlay.vidOverlayDvdy = val & VID_DVDY_MASK;
#if 0
banshee_log("vidOverlayDvdy=%08x\n", val);
#endif
break;
case Video_vidOverlayDvdyOffset:
voodoo->overlay.vidOverlayDvdyOffset = val;
break;
case Video_vidDesktopStartAddr:
banshee->vidDesktopStartAddr = val & 0xffffff;
#if 0
banshee_log("vidDesktopStartAddr=%08x\n", val);
#endif
svga->fullchange = changeframecount;
svga_recalctimings(svga);
break;
case Video_vidDesktopOverlayStride:
banshee->vidDesktopOverlayStride = val;
#if 0
banshee_log("vidDesktopOverlayStride=%08x\n", val);
#endif
svga->fullchange = changeframecount;
svga_recalctimings(svga);
break;
default:
#if 0
fatal("bad banshee_ext_outl: addr=%04x val=%08x\n", addr, val);
#endif
break;
}
}
static uint8_t
banshee_ext_in(uint16_t addr, void *priv)
{
banshee_t *banshee = (banshee_t *) priv;
#if 0
svga_t *svga = &banshee->svga;
#endif
uint8_t ret = 0xff;
switch (addr & 0xff) {
case Init_status:
case Init_status + 1:
case Init_status + 2:
case Init_status + 3:
ret = (banshee_status(banshee) >> ((addr & 3) * 8)) & 0xff;
#if 0
banshee_log("Read status reg! %04x(%08x):%08x\n", CS, cs, cpu_state.pc);
#endif
break;
case 0xb0:
case 0xb1:
case 0xb2:
case 0xb3:
case 0xb4:
case 0xb5:
case 0xb6:
case 0xb7:
case 0xb8:
case 0xb9:
case 0xba:
case 0xbb:
case 0xbc:
case 0xbd:
case 0xbe:
case 0xbf:
case 0xc0:
case 0xc1:
case 0xc2:
case 0xc3:
case 0xc4:
case 0xc5:
case 0xc6:
case 0xc7:
case 0xc8:
case 0xc9:
case 0xca:
case 0xcb:
case 0xcc:
case 0xcd:
case 0xce:
case 0xcf:
case 0xd0:
case 0xd1:
case 0xd2:
case 0xd3:
case 0xd4:
case 0xd5:
case 0xd6:
case 0xd7:
case 0xd8:
case 0xd9:
case 0xda:
case 0xdb:
case 0xdc:
case 0xdd:
case 0xde:
case 0xdf:
ret = banshee_in((addr & 0xff) + 0x300, priv);
break;
default:
banshee_log("bad banshee_ext_in: addr=%04x\n", addr);
break;
}
// banshee_log("banshee_ext_in: addr=%04x val=%02x\n", addr, ret);
return ret;
}
static uint32_t
banshee_status(banshee_t *banshee)
{
voodoo_t *voodoo = banshee->voodoo;
const svga_t *svga = &banshee->svga;
int fifo_entries = FIFO_ENTRIES;
int swap_count = voodoo->swap_count;
int written = voodoo->cmd_written + voodoo->cmd_written_fifo;
int busy = (written - voodoo->cmd_read) || (voodoo->cmdfifo_depth_rd != voodoo->cmdfifo_depth_wr) || voodoo->render_voodoo_busy[0] || voodoo->render_voodoo_busy[1] || voodoo->render_voodoo_busy[2] || voodoo->render_voodoo_busy[3] || voodoo->voodoo_busy;
uint32_t ret = 0;
if (fifo_entries < 0x20)
ret |= 0x1f - fifo_entries;
else
ret |= 0x1f;
if (fifo_entries)
ret |= 0x20;
if (swap_count < 7)
ret |= (swap_count << 28);
else
ret |= (7 << 28);
if (!(svga->cgastat & 8))
ret |= 0x40;
if (busy)
ret |= 0x780; /*Busy*/
if (voodoo->cmdfifo_depth_rd != voodoo->cmdfifo_depth_wr)
ret |= (1 << 11);
if (!voodoo->voodoo_busy)
voodoo_wake_fifo_thread(voodoo);
#if 0
banshee_log("banshee_status: busy %i %i (%i %i) %i %i %i %04x(%08x):%08x %08x\n", busy, written, voodoo->cmd_written, voodoo->cmd_written_fifo, voodoo->cmd_read, voodoo->cmdfifo_depth_rd, voodoo->cmdfifo_depth_wr, CS,cs,cpu_state.pc, ret);
#endif
return ret;
}
static uint32_t
banshee_ext_inl(uint16_t addr, void *priv)
{
banshee_t *banshee = (banshee_t *) priv;
const voodoo_t *voodoo = banshee->voodoo;
const svga_t *svga = &banshee->svga;
uint32_t ret = 0xffffffff;
cycles -= voodoo->read_time;
switch (addr & 0xff) {
case Init_status:
ret = banshee_status(banshee);
#if 0
banshee_log("Read status reg! %04x(%08x):%08x\n", CS, cs, cpu_state.pc);
#endif
break;
case Init_pciInit0:
ret = banshee->pciInit0;
break;
case Init_lfbMemoryConfig:
ret = banshee->lfbMemoryConfig;
break;
case Init_miscInit0:
ret = banshee->miscInit0;
break;
case Init_miscInit1:
ret = banshee->miscInit1;
break;
case Init_dramInit0:
ret = banshee->dramInit0;
break;
case Init_dramInit1:
ret = banshee->dramInit1;
break;
case Init_agpInit0:
ret = banshee->agpInit0;
break;
case Init_vgaInit0:
ret = banshee->vgaInit0;
break;
case Init_vgaInit1:
ret = banshee->vgaInit1;
break;
case Init_2dCommand:
ret = banshee->command_2d;
break;
case Init_2dSrcBaseAddr:
ret = banshee->srcBaseAddr_2d;
break;
case Init_strapInfo:
ret = 0x00000040; /*8 MB SGRAM, PCI, IRQ enabled, 32kB BIOS*/
break;
case PLL_pllCtrl0:
ret = banshee->pllCtrl0;
break;
case PLL_pllCtrl1:
ret = banshee->pllCtrl1;
break;
case PLL_pllCtrl2:
ret = banshee->pllCtrl2;
break;
case DAC_dacMode:
ret = banshee->dacMode;
break;
case DAC_dacAddr:
ret = banshee->dacAddr;
break;
case DAC_dacData:
ret = svga->pallook[banshee->dacAddr];
break;
case Video_vidProcCfg:
ret = banshee->vidProcCfg;
break;
case Video_hwCurPatAddr:
ret = banshee->hwCurPatAddr;
break;
case Video_hwCurLoc:
ret = banshee->hwCurLoc;
break;
case Video_hwCurC0:
ret = banshee->hwCurC0;
break;
case Video_hwCurC1:
ret = banshee->hwCurC1;
break;
case Video_vidSerialParallelPort:
ret = banshee->vidSerialParallelPort & ~(VIDSERIAL_DDC_DCK_R | VIDSERIAL_DDC_DDA_R | VIDSERIAL_I2C_SCK_R | VIDSERIAL_I2C_SDA_R);
if (banshee->vidSerialParallelPort & VIDSERIAL_DDC_EN) {
if (i2c_gpio_get_scl(banshee->i2c_ddc))
ret |= VIDSERIAL_DDC_DCK_R;
if (i2c_gpio_get_sda(banshee->i2c_ddc))
ret |= VIDSERIAL_DDC_DDA_R;
}
if (banshee->vidSerialParallelPort & VIDSERIAL_I2C_EN) {
if (i2c_gpio_get_scl(banshee->i2c))
ret |= VIDSERIAL_I2C_SCK_R;
if (i2c_gpio_get_sda(banshee->i2c))
ret |= VIDSERIAL_I2C_SDA_R;
}
#if 0
banshee_log("vidSerialParallelPort: read %08x %08x %04x(%08x):%08x\n", ret, ret & (VIDSERIAL_DDC_DCK_R | VIDSERIAL_DDC_DDA_R), CS,cs,cpu_state.pc);
#endif
break;
case Video_vidScreenSize:
ret = banshee->vidScreenSize;
break;
case Video_vidOverlayStartCoords:
ret = voodoo->overlay.vidOverlayStartCoords;
break;
case Video_vidOverlayEndScreenCoords:
ret = voodoo->overlay.vidOverlayEndScreenCoords;
break;
case Video_vidOverlayDudx:
ret = voodoo->overlay.vidOverlayDudx;
break;
case Video_vidOverlayDudxOffsetSrcWidth:
ret = voodoo->overlay.vidOverlayDudxOffsetSrcWidth;
break;
case Video_vidOverlayDvdy:
ret = voodoo->overlay.vidOverlayDvdy;
break;
case Video_vidOverlayDvdyOffset:
ret = voodoo->overlay.vidOverlayDvdyOffset;
break;
case Video_vidDesktopStartAddr:
ret = banshee->vidDesktopStartAddr;
break;
case Video_vidDesktopOverlayStride:
ret = banshee->vidDesktopOverlayStride;
break;
default:
// fatal("bad banshee_ext_inl: addr=%04x\n", addr);
break;
}
#if 0
if (addr)
banshee_log("banshee_ext_inl: addr=%04x val=%08x\n", addr, ret);
#endif
return ret;
}
static uint32_t banshee_reg_readl(uint32_t addr, void *priv);
static uint8_t
banshee_reg_read(uint32_t addr, void *priv)
{
#if 0
banshee_log("banshee_reg_read: addr=%08x\n", addr);
#endif
return banshee_reg_readl(addr & ~3, priv) >> (8 * (addr & 3));
}
static uint16_t
banshee_reg_readw(uint32_t addr, void *priv)
{
#if 0
banshee_log("banshee_reg_readw: addr=%08x\n", addr);
#endif
return banshee_reg_readl(addr & ~3, priv) >> (8 * (addr & 2));
}
static uint32_t
banshee_cmd_read(banshee_t *banshee, uint32_t addr)
{
const voodoo_t *voodoo = banshee->voodoo;
uint32_t ret = 0xffffffff;
switch (addr & 0x1fc) {
case Agp_agpHostAddressLow:
ret = banshee->agpHostAddressLow;
break;
case Agp_agpHostAddressHigh:
ret = banshee->agpHostAddressHigh;
break;
case Agp_agpGraphicsAddress:
ret = banshee->agpGraphicsAddress;
break;
case Agp_agpGraphicsStride:
ret = banshee->agpGraphicsStride;
break;
case Agp_agpReqSize:
ret = banshee->agpReqSize;
break;
case cmdBaseAddr0:
ret = voodoo->cmdfifo_base >> 12;
// banshee_log("Read cmdfifo_base %08x\n", ret);
break;
case cmdRdPtrL0:
ret = voodoo->cmdfifo_rp;
// banshee_log("Read cmdfifo_rp %08x\n", ret);
break;
case cmdFifoDepth0:
ret = voodoo->cmdfifo_depth_wr - voodoo->cmdfifo_depth_rd;
// banshee_log("Read cmdfifo_depth %08x\n", ret);
break;
case cmdStatus0:
ret = voodoo->cmd_status;
break;
case cmdBaseSize0:
ret = voodoo->cmdfifo_size;
break;
case 0x108:
break;
default:
fatal("Unknown banshee_cmd_read 0x%08x (reg 0x%03x)\n", addr, addr & 0x1fc);
}
return ret;
}
static uint32_t
banshee_reg_readl(uint32_t addr, void *priv)
{
banshee_t *banshee = (banshee_t *) priv;
voodoo_t *voodoo = banshee->voodoo;
uint32_t ret = 0xffffffff;
cycles -= voodoo->read_time;
switch (addr & 0x1f00000) {
case 0x0000000: /*IO remap*/
if (!(addr & 0x80000))
ret = banshee_ext_inl(addr & 0xff, banshee);
else
ret = banshee_cmd_read(banshee, addr);
break;
case 0x0100000: /*2D registers*/
voodoo_flush(voodoo);
switch (addr & 0x1fc) {
case SST_status:
ret = banshee_status(banshee);
break;
case SST_intrCtrl:
ret = banshee->intrCtrl & 0x0030003f;
break;
case 0x08:
ret = voodoo->banshee_blt.clip0Min;
break;
case 0x0c:
ret = voodoo->banshee_blt.clip0Max;
break;
case 0x10:
ret = voodoo->banshee_blt.dstBaseAddr;
break;
case 0x14:
ret = voodoo->banshee_blt.dstFormat;
break;
case 0x34:
ret = voodoo->banshee_blt.srcBaseAddr;
break;
case 0x38:
ret = voodoo->banshee_blt.commandExtra;
break;
case 0x5c:
ret = voodoo->banshee_blt.srcXY;
break;
case 0x60:
ret = voodoo->banshee_blt.colorBack;
break;
case 0x64:
ret = voodoo->banshee_blt.colorFore;
break;
case 0x68:
ret = voodoo->banshee_blt.dstSize;
break;
case 0x6c:
ret = voodoo->banshee_blt.dstXY;
break;
case 0x70:
ret = voodoo->banshee_blt.command;
break;
default:
banshee_log("banshee_reg_readl: addr=%08x\n", addr);
}
break;
case 0x0200000:
case 0x0300000:
case 0x0400000:
case 0x0500000: /*3D registers*/
switch (addr & 0x3fc) {
case SST_status:
ret = banshee_status(banshee);
break;
case SST_intrCtrl:
ret = banshee->intrCtrl & 0x0030003f;
break;
case SST_fbzColorPath:
voodoo_flush(voodoo);
ret = voodoo->params.fbzColorPath;
break;
case SST_fogMode:
voodoo_flush(voodoo);
ret = voodoo->params.fogMode;
break;
case SST_alphaMode:
voodoo_flush(voodoo);
ret = voodoo->params.alphaMode;
break;
case SST_fbzMode:
voodoo_flush(voodoo);
ret = voodoo->params.fbzMode;
break;
case SST_lfbMode:
voodoo_flush(voodoo);
ret = voodoo->lfbMode;
break;
case SST_clipLeftRight:
ret = voodoo->params.clipRight | (voodoo->params.clipLeft << 16);
break;
case SST_clipLowYHighY:
ret = voodoo->params.clipHighY | (voodoo->params.clipLowY << 16);
break;
case SST_clipLeftRight1:
ret = voodoo->params.clipRight1 | (voodoo->params.clipLeft1 << 16);
break;
case SST_clipTopBottom1:
ret = voodoo->params.clipHighY1 | (voodoo->params.clipLowY1 << 16);
break;
case SST_stipple:
voodoo_flush(voodoo);
ret = voodoo->params.stipple;
break;
case SST_color0:
voodoo_flush(voodoo);
ret = voodoo->params.color0;
break;
case SST_color1:
voodoo_flush(voodoo);
ret = voodoo->params.color1;
break;
case SST_fbiPixelsIn:
ret = voodoo->fbiPixelsIn & 0xffffff;
break;
case SST_fbiChromaFail:
ret = voodoo->fbiChromaFail & 0xffffff;
break;
case SST_fbiZFuncFail:
ret = voodoo->fbiZFuncFail & 0xffffff;
break;
case SST_fbiAFuncFail:
ret = voodoo->fbiAFuncFail & 0xffffff;
break;
case SST_fbiPixelsOut:
ret = voodoo->fbiPixelsOut & 0xffffff;
break;
default:
banshee_log("banshee_reg_readl: 3D addr=%08x\n", addr);
break;
}
break;
default:
break;
}
#if 0
if (addr != 0xe0000000)
banshee_log("banshee_reg_readl: addr=%08x ret=%08x %04x(%08x):%08x\n", addr, ret, CS,cs,cpu_state.pc);
#endif
return ret;
}
static void
banshee_reg_write(UNUSED(uint32_t addr), UNUSED(uint8_t val), UNUSED(void *priv))
{
#if 0
banshee_log("banshee_reg_writeb: addr=%08x val=%02x\n", addr, val);
#endif
}
static void
banshee_reg_writew(uint32_t addr, uint16_t val, void *priv)
{
banshee_t *banshee = (banshee_t *) priv;
voodoo_t *voodoo = banshee->voodoo;
cycles -= voodoo->write_time;
#if 0
banshee_log("banshee_reg_writew: addr=%08x val=%04x\n", addr, val);
#endif
switch (addr & 0x1f00000) {
case 0x1000000:
case 0x1100000:
case 0x1200000:
case 0x1300000: /*3D LFB*/
case 0x1400000:
case 0x1500000:
case 0x1600000:
case 0x1700000:
case 0x1800000:
case 0x1900000:
case 0x1a00000:
case 0x1b00000:
case 0x1c00000:
case 0x1d00000:
case 0x1e00000:
case 0x1f00000:
voodoo_queue_command(voodoo, (addr & 0xffffff) | FIFO_WRITEW_FB, val);
break;
default:
break;
}
}
static void
banshee_cmd_write(banshee_t *banshee, uint32_t addr, uint32_t val)
{
voodoo_t *voodoo = banshee->voodoo;
#if 0
banshee_log("banshee_cmd_write: addr=%03x val=%08x\n", addr & 0x1fc, val);
#endif
switch (addr & 0x1fc) {
case Agp_agpHostAddressLow:
banshee->agpHostAddressLow = val;
break;
case Agp_agpHostAddressHigh:
banshee->agpHostAddressHigh = val;
break;
case Agp_agpGraphicsAddress:
banshee->agpGraphicsAddress = val;
break;
case Agp_agpGraphicsStride:
banshee->agpGraphicsStride = val;
break;
case Agp_agpReqSize:
banshee->agpReqSize = val;
break;
case cmdBaseAddr0:
voodoo->cmdfifo_base = (val & 0xfff) << 12;
voodoo->cmdfifo_end = voodoo->cmdfifo_base + (((voodoo->cmdfifo_size & 0xff) + 1) << 12);
#if 0
banshee_log("cmdfifo_base=%08x cmdfifo_end=%08x %08x\n", voodoo->cmdfifo_base, voodoo->cmdfifo_end, val);
#endif
break;
case cmdBaseSize0:
voodoo->cmdfifo_size = val;
voodoo->cmdfifo_end = voodoo->cmdfifo_base + (((voodoo->cmdfifo_size & 0xff) + 1) << 12);
voodoo->cmdfifo_enabled = val & 0x100;
if (!voodoo->cmdfifo_enabled)
voodoo->cmdfifo_in_sub = 0; /*Not sure exactly when this should be reset*/
#if 0
banshee_log("cmdfifo_base=%08x cmdfifo_end=%08x\n", voodoo->cmdfifo_base, voodoo->cmdfifo_end);
#endif
break;
#if 0
voodoo->cmdfifo_end = ((val >> 16) & 0x3ff) << 12;
banshee_log("CMDFIFO base=%08x end=%08x\n", voodoo->cmdfifo_base, voodoo->cmdfifo_end);
break;
#endif
case cmdRdPtrL0:
voodoo->cmdfifo_rp = val;
break;
case cmdAMin0:
voodoo->cmdfifo_amin = val;
break;
case cmdAMax0:
voodoo->cmdfifo_amax = val;
break;
case cmdFifoDepth0:
voodoo->cmdfifo_depth_rd = 0;
voodoo->cmdfifo_depth_wr = val & 0xffff;
break;
default:
banshee_log("Unknown banshee_cmd_write: addr=%08x val=%08x reg=0x%03x\n", addr, val, addr & 0x1fc);
break;
}
#if 0
cmdBaseSize0 = 0x24,
cmdBump0 = 0x28,
cmdRdPtrL0 = 0x2c,
cmdRdPtrH0 = 0x30,
cmdAMin0 = 0x34,
cmdAMax0 = 0x3c,
cmdFifoDepth0 = 0x44,
cmdHoleCnt0 = 0x48
}
#endif
}
static void
banshee_reg_writel(uint32_t addr, uint32_t val, void *priv)
{
banshee_t *banshee = (banshee_t *) priv;
voodoo_t *voodoo = banshee->voodoo;
if (addr == voodoo->last_write_addr + 4)
cycles -= voodoo->burst_time;
else
cycles -= voodoo->write_time;
voodoo->last_write_addr = addr;
#if 0
banshee_log("banshee_reg_writel: addr=%08x val=%08x\n", addr, val);
#endif
switch (addr & 0x1f00000) {
case 0x0000000: /*IO remap*/
if (!(addr & 0x80000))
banshee_ext_outl(addr & 0xff, val, banshee);
else
banshee_cmd_write(banshee, addr, val);
#if 0
banshee_log("CMD!!! write %08x %08x\n", addr, val);
#endif
break;
case 0x0100000: /*2D registers*/
if ((addr & 0x3fc) == SST_intrCtrl) {
banshee->intrCtrl = val & 0x0030003f;
} else {
voodoo_queue_command(voodoo, (addr & 0x1fc) | FIFO_WRITEL_2DREG, val);
}
break;
case 0x0200000:
case 0x0300000:
case 0x0400000:
case 0x0500000: /*3D registers*/
switch (addr & 0x3fc) {
case SST_intrCtrl:
banshee->intrCtrl = val & 0x0030003f;
#if 0
banshee_log("intrCtrl=%08x\n", val);
#endif
break;
case SST_userIntrCMD:
fatal("userIntrCMD write %08x\n", val);
break;
case SST_swapbufferCMD:
voodoo->cmd_written++;
voodoo_queue_command(voodoo, (addr & 0x3fc) | FIFO_WRITEL_REG, val);
if (!voodoo->voodoo_busy)
voodoo_wake_fifo_threads(voodoo->set, voodoo);
#if 0
banshee_log("SST_swapbufferCMD write: %i %i\n", voodoo->cmd_written, voodoo->cmd_written_fifo);
#endif
break;
case SST_triangleCMD:
voodoo->cmd_written++;
voodoo_queue_command(voodoo, (addr & 0x3fc) | FIFO_WRITEL_REG, val);
if (!voodoo->voodoo_busy)
voodoo_wake_fifo_threads(voodoo->set, voodoo);
break;
case SST_ftriangleCMD:
voodoo->cmd_written++;
voodoo_queue_command(voodoo, (addr & 0x3fc) | FIFO_WRITEL_REG, val);
if (!voodoo->voodoo_busy)
voodoo_wake_fifo_threads(voodoo->set, voodoo);
break;
case SST_fastfillCMD:
voodoo->cmd_written++;
voodoo_queue_command(voodoo, (addr & 0x3fc) | FIFO_WRITEL_REG, val);
if (!voodoo->voodoo_busy)
voodoo_wake_fifo_threads(voodoo->set, voodoo);
break;
case SST_nopCMD:
voodoo->cmd_written++;
voodoo_queue_command(voodoo, (addr & 0x3fc) | FIFO_WRITEL_REG, val);
if (!voodoo->voodoo_busy)
voodoo_wake_fifo_threads(voodoo->set, voodoo);
break;
case SST_swapPending:
thread_wait_mutex(voodoo->swap_mutex);
voodoo->swap_count++;
thread_release_mutex(voodoo->swap_mutex);
#if 0
voodoo->cmd_written++;
#endif
break;
default:
voodoo_queue_command(voodoo, (addr & 0x3ffffc) | FIFO_WRITEL_REG, val);
break;
}
break;
case 0x0600000:
case 0x0700000: /*TMU0 Texture download*/
voodoo->tex_count++;
voodoo_queue_command(voodoo, (addr & 0x1ffffc) | FIFO_WRITEL_TEX, val);
break;
case 0x1000000:
case 0x1100000:
case 0x1200000:
case 0x1300000: /*3D LFB*/
case 0x1400000:
case 0x1500000:
case 0x1600000:
case 0x1700000:
case 0x1800000:
case 0x1900000:
case 0x1a00000:
case 0x1b00000:
case 0x1c00000:
case 0x1d00000:
case 0x1e00000:
case 0x1f00000:
voodoo_queue_command(voodoo, (addr & 0xfffffc) | FIFO_WRITEL_FB, val);
break;
default:
break;
}
}
static uint8_t
banshee_read_linear(uint32_t addr, void *priv)
{
banshee_t *banshee = (banshee_t *) priv;
const voodoo_t *voodoo = banshee->voodoo;
const svga_t *svga = &banshee->svga;
cycles -= voodoo->read_time;
if ((banshee->pci_regs[0x30] & 0x01) && addr >= banshee->bios_rom.mapping.base && addr < (banshee->bios_rom.mapping.base + banshee->bios_rom.sz)) {
return rom_read(addr & (banshee->bios_rom.sz - 1), &banshee->bios_rom);
}
addr &= svga->decode_mask;
if (addr >= voodoo->tile_base) {
int x;
int y;
addr -= voodoo->tile_base;
x = addr & (voodoo->tile_stride - 1);
y = addr >> voodoo->tile_stride_shift;
addr = voodoo->tile_base + (x & 127) + ((x >> 7) * 128 * 32) + ((y & 31) * 128) + (y >> 5) * voodoo->tile_x_real;
#if 0
banshee_log(" Tile rb %08x->%08x %i %i\n", old_addr, addr, x, y);
#endif
}
if (addr >= svga->vram_max)
return 0xff;
cycles -= svga->monitor->mon_video_timing_read_b;
#if 0
banshee_log("read_linear: addr=%08x val=%02x\n", addr, svga->vram[addr & svga->vram_mask]);
#endif
return svga->vram[addr & svga->vram_mask];
}
static uint16_t
banshee_read_linear_w(uint32_t addr, void *priv)
{
banshee_t *banshee = (banshee_t *) priv;
const voodoo_t *voodoo = banshee->voodoo;
svga_t *svga = &banshee->svga;
if (addr & 1)
return banshee_read_linear(addr, priv) | (banshee_read_linear(addr + 1, priv) << 8);
cycles -= voodoo->read_time;
if ((banshee->pci_regs[0x30] & 0x01) && addr >= banshee->bios_rom.mapping.base && addr < (banshee->bios_rom.mapping.base + banshee->bios_rom.sz)) {
return rom_readw(addr & (banshee->bios_rom.sz - 1), &banshee->bios_rom);
}
addr &= svga->decode_mask;
if (addr >= voodoo->tile_base) {
int x;
int y;
addr -= voodoo->tile_base;
x = addr & (voodoo->tile_stride - 1);
y = addr >> voodoo->tile_stride_shift;
addr = voodoo->tile_base + (x & 127) + ((x >> 7) * 128 * 32) + ((y & 31) * 128) + (y >> 5) * voodoo->tile_x_real;
#if 0
banshee_log(" Tile rb %08x->%08x %i %i\n", old_addr, addr, x, y);
#endif
}
if (addr >= svga->vram_max)
return 0xff;
cycles -= svga->monitor->mon_video_timing_read_w;
#if 0
banshee_log("read_linear: addr=%08x val=%02x\n", addr, svga->vram[addr & svga->vram_mask]);
#endif
return *(uint16_t *) &svga->vram[addr & svga->vram_mask];
}
static uint32_t
banshee_read_linear_l(uint32_t addr, void *priv)
{
banshee_t *banshee = (banshee_t *) priv;
const voodoo_t *voodoo = banshee->voodoo;
svga_t *svga = &banshee->svga;
if (addr & 3)
return banshee_read_linear_w(addr, priv) | (banshee_read_linear_w(addr + 2, priv) << 16);
cycles -= voodoo->read_time;
if ((banshee->pci_regs[0x30] & 0x01) && addr >= banshee->bios_rom.mapping.base && addr < (banshee->bios_rom.mapping.base + banshee->bios_rom.sz)) {
return rom_readl(addr & (banshee->bios_rom.sz - 1), &banshee->bios_rom);
}
addr &= svga->decode_mask;
if (addr >= voodoo->tile_base) {
int x;
int y;
addr -= voodoo->tile_base;
x = addr & (voodoo->tile_stride - 1);
y = addr >> voodoo->tile_stride_shift;
addr = voodoo->tile_base + (x & 127) + ((x >> 7) * 128 * 32) + ((y & 31) * 128) + (y >> 5) * voodoo->tile_x_real;
#if 0
banshee_log(" Tile rb %08x->%08x %i %i\n", old_addr, addr, x, y);
#endif
}
if (addr >= svga->vram_max)
return 0xff;
cycles -= svga->monitor->mon_video_timing_read_l;
#if 0
banshee_log("read_linear: addr=%08x val=%02x\n", addr, svga->vram[addr & svga->vram_mask]);
#endif
return *(uint32_t *) &svga->vram[addr & svga->vram_mask];
}
static void
banshee_write_linear(uint32_t addr, uint8_t val, void *priv)
{
banshee_t *banshee = (banshee_t *) priv;
const voodoo_t *voodoo = banshee->voodoo;
svga_t *svga = &banshee->svga;
cycles -= voodoo->write_time;
#if 0
banshee_log("write_linear: addr=%08x val=%02x\n", addr, val);
#endif
addr &= svga->decode_mask;
if (addr >= voodoo->tile_base) {
int x;
int y;
addr -= voodoo->tile_base;
x = addr & (voodoo->tile_stride - 1);
y = addr >> voodoo->tile_stride_shift;
addr = voodoo->tile_base + (x & 127) + ((x >> 7) * 128 * 32) + ((y & 31) * 128) + (y >> 5) * voodoo->tile_x_real;
#if 0
banshee_log(" Tile b %08x->%08x %i %i\n", old_addr, addr, x, y);
#endif
}
if (addr >= svga->vram_max)
return;
cycles -= svga->monitor->mon_video_timing_write_b;
svga->changedvram[addr >> 12] = changeframecount;
svga->vram[addr & svga->vram_mask] = val;
}
static void
banshee_write_linear_w(uint32_t addr, uint16_t val, void *priv)
{
banshee_t *banshee = (banshee_t *) priv;
const voodoo_t *voodoo = banshee->voodoo;
svga_t *svga = &banshee->svga;
if (addr & 1) {
banshee_write_linear(addr, val, priv);
banshee_write_linear(addr + 1, val >> 8, priv);
return;
}
cycles -= voodoo->write_time;
#if 0
banshee_log("write_linear: addr=%08x val=%02x\n", addr, val);
#endif
addr &= svga->decode_mask;
if (addr >= voodoo->tile_base) {
int x;
int y;
addr -= voodoo->tile_base;
x = addr & (voodoo->tile_stride - 1);
y = addr >> voodoo->tile_stride_shift;
addr = voodoo->tile_base + (x & 127) + ((x >> 7) * 128 * 32) + ((y & 31) * 128) + (y >> 5) * voodoo->tile_x_real;
#if 0
banshee_log(" Tile b %08x->%08x %i %i\n", old_addr, addr, x, y);
#endif
}
if (addr >= svga->vram_max)
return;
cycles -= svga->monitor->mon_video_timing_write_w;
svga->changedvram[addr >> 12] = changeframecount;
*(uint16_t *) &svga->vram[addr & svga->vram_mask] = val;
}
static void
banshee_write_linear_l(uint32_t addr, uint32_t val, void *priv)
{
banshee_t *banshee = (banshee_t *) priv;
voodoo_t *voodoo = banshee->voodoo;
svga_t *svga = &banshee->svga;
int timing;
if (addr & 3) {
banshee_write_linear_w(addr, val, priv);
banshee_write_linear_w(addr + 2, val >> 16, priv);
return;
}
if (addr == voodoo->last_write_addr + 4)
timing = voodoo->burst_time;
else
timing = voodoo->write_time;
cycles -= timing;
voodoo->last_write_addr = addr;
#if 0
if (val)
banshee_log("write_linear_l: addr=%08x val=%08x %08x\n", addr, val, voodoo->tile_base);
#endif
addr &= svga->decode_mask;
if (addr >= voodoo->tile_base) {
int x;
int y;
addr -= voodoo->tile_base;
x = addr & (voodoo->tile_stride - 1);
y = addr >> voodoo->tile_stride_shift;
addr = voodoo->tile_base + (x & 127) + ((x >> 7) * 128 * 32) + ((y & 31) * 128) + (y >> 5) * voodoo->tile_x_real;
#if 0
banshee_log(" Tile %08x->%08x->%08x->%08x %i %i tile_x=%i\n", old_addr, addr_off, addr2, addr, x, y, voodoo->tile_x_real);
#endif
}
if (addr >= svga->vram_max)
return;
cycles -= svga->monitor->mon_video_timing_write_l;
svga->changedvram[addr >> 12] = changeframecount;
*(uint32_t *) &svga->vram[addr & svga->vram_mask] = val;
if (voodoo->cmdfifo_enabled && addr >= voodoo->cmdfifo_base && addr < voodoo->cmdfifo_end) {
#if 0
banshee_log("CMDFIFO write %08x %08x old amin=%08x amax=%08x hlcnt=%i depth_wr=%i rp=%08x\n", addr, val, voodoo->cmdfifo_amin, voodoo->cmdfifo_amax, voodoo->cmdfifo_holecount, voodoo->cmdfifo_depth_wr, voodoo->cmdfifo_rp);
#endif
if (addr == voodoo->cmdfifo_base && !voodoo->cmdfifo_holecount) {
#if 0
if (voodoo->cmdfifo_holecount)
fatal("CMDFIFO reset pointers while outstanding holes\n");
#endif
/*Reset pointers*/
voodoo->cmdfifo_amin = voodoo->cmdfifo_base;
voodoo->cmdfifo_amax = voodoo->cmdfifo_base;
voodoo->cmdfifo_depth_wr++;
voodoo_wake_fifo_thread(voodoo);
} else if (voodoo->cmdfifo_holecount) {
#if 0
if ((addr <= voodoo->cmdfifo_amin && voodoo->cmdfifo_amin != -4) || addr >= voodoo->cmdfifo_amax)
fatal("CMDFIFO holecount write outside of amin/amax - amin=%08x amax=%08x holecount=%i\n", voodoo->cmdfifo_amin, voodoo->cmdfifo_amax, voodoo->cmdfifo_holecount);
banshee_log("holecount %i\n", voodoo->cmdfifo_holecount);
#endif
voodoo->cmdfifo_holecount--;
if (!voodoo->cmdfifo_holecount) {
/*Filled in holes, resume normal operation*/
voodoo->cmdfifo_depth_wr += ((voodoo->cmdfifo_amax - voodoo->cmdfifo_amin) >> 2);
voodoo->cmdfifo_amin = voodoo->cmdfifo_amax;
voodoo_wake_fifo_thread(voodoo);
#if 0
banshee_log("hole filled! amin=%08x amax=%08x added %i words\n", voodoo->cmdfifo_amin, voodoo->cmdfifo_amax, words_to_add);
#endif
}
} else if (addr == voodoo->cmdfifo_amax + 4) {
/*In-order write*/
voodoo->cmdfifo_amin = addr;
voodoo->cmdfifo_amax = addr;
voodoo->cmdfifo_depth_wr++;
voodoo_wake_fifo_thread(voodoo);
} else {
/*Out-of-order write*/
if (addr < voodoo->cmdfifo_amin) {
/*Reset back to start. Note that write is still out of order!*/
voodoo->cmdfifo_amin = voodoo->cmdfifo_base - 4;
}
#if 0
else if (addr < voodoo->cmdfifo_amax)
fatal("Out-of-order write really out of order\n");
#endif
voodoo->cmdfifo_amax = addr;
voodoo->cmdfifo_holecount = ((voodoo->cmdfifo_amax - voodoo->cmdfifo_amin) >> 2) - 1;
#if 0
banshee_log("CMDFIFO out of order: amin=%08x amax=%08x holecount=%i\n", voodoo->cmdfifo_amin, voodoo->cmdfifo_amax, voodoo->cmdfifo_holecount);
#endif
}
}
}
void
banshee_hwcursor_draw(svga_t *svga, int displine)
{
const banshee_t *banshee = (banshee_t *) svga->priv;
int x;
int x_off;
int xx;
uint32_t col0 = banshee->hwCurC0;
uint32_t col1 = banshee->hwCurC1;
uint8_t plane0[8];
uint8_t plane1[8];
for (uint8_t c = 0; c < 8; c++)
plane0[c] = svga->vram[svga->hwcursor_latch.addr + c];
for (uint8_t c = 0; c < 8; c++)
plane1[c] = svga->vram[svga->hwcursor_latch.addr + c + 8];
svga->hwcursor_latch.addr += 16;
x_off = svga->hwcursor_latch.x;
if (banshee->vidProcCfg & VIDPROCCFG_CURSOR_MODE) {
/*X11 mode*/
for (x = 0; x < 64; x += 8) {
if (x_off > -8) {
for (xx = 0; xx < 8; xx++) {
if (plane0[x >> 3] & (1 << 7))
(svga->monitor->target_buffer->line[displine])[x_off + xx + svga->x_add] = (plane1[x >> 3] & (1 << 7)) ? col1 : col0;
plane0[x >> 3] <<= 1;
plane1[x >> 3] <<= 1;
}
}
x_off += 8;
}
} else {
/*Windows mode*/
for (x = 0; x < 64; x += 8) {
if (x_off > -8) {
for (xx = 0; xx < 8; xx++) {
if (((x_off + xx + svga->x_add) >= 0) && ((x_off + xx + svga->x_add) <= 2047)) {
if (!(plane0[x >> 3] & (1 << 7)))
(svga->monitor->target_buffer->line[displine])[x_off + xx + svga->x_add] = (plane1[x >> 3] & (1 << 7)) ? col1 : col0;
else if (plane1[x >> 3] & (1 << 7))
(svga->monitor->target_buffer->line[displine])[x_off + xx + svga->x_add] ^= 0xffffff;
}
plane0[x >> 3] <<= 1;
plane1[x >> 3] <<= 1;
}
}
x_off += 8;
}
}
}
#define CLAMP(x) \
do { \
if ((x) & ~0xff) \
x = ((x) < 0) ? 0 : 0xff; \
} while (0)
#define DECODE_RGB565(buf) \
do { \
int c; \
int wp = 0; \
\
for (c = 0; c < voodoo->overlay.overlay_bytes; c += 2) { \
uint16_t data = *(uint16_t *) src; \
int r = data & 0x1f; \
int g = (data >> 5) & 0x3f; \
int b = data >> 11; \
\
if (banshee->vidProcCfg & VIDPROCCFG_OVERLAY_CLUT_BYPASS) \
buf[wp++] = (r << 3) | (g << 10) | (b << 19); \
else \
buf[wp++] = (clut[r << 3] & 0x0000ff) | (clut[g << 2] & 0x00ff00) | (clut[b << 3] & 0xff0000); \
src += 2; \
} \
} while (0)
#define DECODE_RGB565_TILED(buf) \
do { \
int c; \
int wp = 0; \
uint32_t base_addr = (buf == banshee->overlay_buffer[1]) ? src_addr2 : src_addr; \
\
for (c = 0; c < voodoo->overlay.overlay_bytes; c += 2) { \
uint16_t data = *(uint16_t *) &svga->vram[(base_addr + (c & 127) + (c >> 7) * 128 * 32) & svga->vram_mask]; \
int r = data & 0x1f; \
int g = (data >> 5) & 0x3f; \
int b = data >> 11; \
\
if (banshee->vidProcCfg & VIDPROCCFG_OVERLAY_CLUT_BYPASS) \
buf[wp++] = (r << 3) | (g << 10) | (b << 19); \
else \
buf[wp++] = (clut[r << 3] & 0x0000ff) | (clut[g << 2] & 0x00ff00) | (clut[b << 3] & 0xff0000); \
} \
} while (0)
#define DECODE_YUYV422(buf) \
do { \
int c; \
int wp = 0; \
\
for (c = 0; c < voodoo->overlay.overlay_bytes; c += 4) { \
uint8_t y1, y2; \
int8_t Cr, Cb; \
int dR, dG, dB; \
int r, g, b; \
\
y1 = src[0]; \
Cr = src[1] - 0x80; \
y2 = src[2]; \
Cb = src[3] - 0x80; \
src += 4; \
\
dR = (359 * Cr) >> 8; \
dG = (88 * Cb + 183 * Cr) >> 8; \
dB = (453 * Cb) >> 8; \
\
r = y1 + dR; \
CLAMP(r); \
g = y1 - dG; \
CLAMP(g); \
b = y1 + dB; \
CLAMP(b); \
buf[wp++] = r | (g << 8) | (b << 16); \
\
r = y2 + dR; \
CLAMP(r); \
g = y2 - dG; \
CLAMP(g); \
b = y2 + dB; \
CLAMP(b); \
buf[wp++] = r | (g << 8) | (b << 16); \
} \
} while (0)
#define DECODE_UYUV422(buf) \
do { \
int c; \
int wp = 0; \
\
for (c = 0; c < voodoo->overlay.overlay_bytes; c += 4) { \
uint8_t y1, y2; \
int8_t Cr, Cb; \
int dR, dG, dB; \
int r, g, b; \
\
Cr = src[0] - 0x80; \
y1 = src[1]; \
Cb = src[2] - 0x80; \
y2 = src[3]; \
src += 4; \
\
dR = (359 * Cr) >> 8; \
dG = (88 * Cb + 183 * Cr) >> 8; \
dB = (453 * Cb) >> 8; \
\
r = y1 + dR; \
CLAMP(r); \
g = y1 - dG; \
CLAMP(g); \
b = y1 + dB; \
CLAMP(b); \
buf[wp++] = r | (g << 8) | (b << 16); \
\
r = y2 + dR; \
CLAMP(r); \
g = y2 - dG; \
CLAMP(g); \
b = y2 + dB; \
CLAMP(b); \
buf[wp++] = r | (g << 8) | (b << 16); \
} \
} while (0)
#define OVERLAY_SAMPLE(buf) \
do { \
switch (banshee->overlay_pix_fmt) { \
case 0: \
break; \
\
case OVERLAY_FMT_YUYV422: \
DECODE_YUYV422(buf); \
break; \
\
case OVERLAY_FMT_UYVY422: \
DECODE_UYUV422(buf); \
break; \
\
case OVERLAY_FMT_565: \
case OVERLAY_FMT_565_DITHER: \
if (banshee->vidProcCfg & VIDPROCCFG_OVERLAY_TILE) \
DECODE_RGB565_TILED(buf); \
else \
DECODE_RGB565(buf); \
break; \
\
default: \
fatal("Unknown overlay pix fmt %i\n", banshee->overlay_pix_fmt); \
} \
} while (0)
/* generate both filters for the static table here */
void
voodoo_generate_vb_filters(voodoo_t *voodoo, int fcr, int fcg)
{
float difference;
float diffg;
float thiscol;
float thiscolg;
float clr;
float clg = 0;
float hack = 1.0f;
// pre-clamping
fcr *= hack;
fcg *= hack;
/* box prefilter */
for (uint16_t g = 0; g < 256; g++) { // pixel 1 - our target pixel we want to bleed into
for (uint16_t h = 0; h < 256; h++) { // pixel 2 - our main pixel
float avg;
float avgdiff;
difference = (float) (g - h);
avg = g;
avgdiff = avg - h;
avgdiff = avgdiff * 0.75f;
if (avgdiff < 0)
avgdiff *= -1;
if (difference < 0)
difference *= -1;
thiscol = thiscolg = g;
if (h > g) {
clr = clg = avgdiff;
if (clr > fcr)
clr = fcr;
if (clg > fcg)
clg = fcg;
thiscol = g;
thiscolg = g;
if (thiscol > g + fcr)
thiscol = g + fcr;
if (thiscolg > g + fcg)
thiscolg = g + fcg;
if (thiscol > g + difference)
thiscol = g + difference;
if (thiscolg > g + difference)
thiscolg = g + difference;
// hmm this might not be working out..
int ugh = g - h;
if (ugh < fcr)
thiscol = h;
if (ugh < fcg)
thiscolg = h;
}
if (difference > fcr)
thiscol = g;
if (difference > fcg)
thiscolg = g;
// clamp
if (thiscol < 0)
thiscol = 0;
if (thiscolg < 0)
thiscolg = 0;
if (thiscol > 255)
thiscol = 255;
if (thiscolg > 255)
thiscolg = 255;
vb_filter_bx_rb[g][h] = thiscol;
vb_filter_bx_g[g][h] = thiscolg;
}
float lined = g + 4;
if (lined > 255)
lined = 255;
voodoo->purpleline[g][0] = lined;
voodoo->purpleline[g][2] = lined;
lined = g + 0;
if (lined > 255)
lined = 255;
voodoo->purpleline[g][1] = lined;
}
/* 4x1 and 2x2 filter */
#if 0
fcr *= 5;
fcg *= 6;
#endif
for (uint16_t g = 0; g < 256; g++) { // pixel 1
for (uint16_t h = 0; h < 256; h++) { // pixel 2
difference = (float) (h - g);
diffg = difference;
thiscol = thiscolg = g;
if (difference > fcr)
difference = fcr;
if (difference < -fcr)
difference = -fcr;
if (diffg > fcg)
diffg = fcg;
if (diffg < -fcg)
diffg = -fcg;
if ((difference < fcr) || (-difference > -fcr))
thiscol = g + (difference / 2);
if ((diffg < fcg) || (-diffg > -fcg))
thiscolg = g + (diffg / 2);
if (thiscol < 0)
thiscol = 0;
if (thiscol > 255)
thiscol = 255;
if (thiscolg < 0)
thiscolg = 0;
if (thiscolg > 255)
thiscolg = 255;
vb_filter_v1_rb[g][h] = thiscol;
vb_filter_v1_g[g][h] = thiscolg;
}
}
}
static void
banshee_overlay_draw(svga_t *svga, int displine)
{
banshee_t *banshee = (banshee_t *) svga->priv;
voodoo_t *voodoo = banshee->voodoo;
uint32_t *p;
int x;
int y = voodoo->overlay.src_y >> 20;
uint32_t src_addr = svga->overlay_latch.addr + ((banshee->vidProcCfg & VIDPROCCFG_OVERLAY_TILE) ? ((y & 31) * 128 + (y >> 5) * svga->overlay_latch.pitch) : y * svga->overlay_latch.pitch);
uint32_t src_addr2 = svga->overlay_latch.addr + ((banshee->vidProcCfg & VIDPROCCFG_OVERLAY_TILE) ? (((y + 1) & 31) * 128 + ((y + 1) >> 5) * svga->overlay_latch.pitch) : (y + 1) * svga->overlay_latch.pitch);
uint8_t *src = &svga->vram[src_addr & svga->vram_mask];
uint32_t src_x = 0;
unsigned int y_coeff = (voodoo->overlay.src_y & 0xfffff) >> 4;
int skip_filtering;
const uint32_t *clut = &svga->pallook[(banshee->vidProcCfg & VIDPROCCFG_OVERLAY_CLUT_SEL) ? 256 : 0];
if (svga->render == svga_render_null && !svga->changedvram[src_addr >> 12] && !svga->changedvram[src_addr2 >> 12] && !svga->fullchange && ((voodoo->overlay.src_y >> 20) < 2048 && !voodoo->dirty_line[voodoo->overlay.src_y >> 20]) && !(banshee->vidProcCfg & VIDPROCCFG_V_SCALE_ENABLE)) {
voodoo->overlay.src_y += (1 << 20);
return;
}
if ((voodoo->overlay.src_y >> 20) < 2048)
voodoo->dirty_line[voodoo->overlay.src_y >> 20] = 0;
#if 0
pclog("displine=%i addr=%08x %08x %08x %08x\n", displine, svga->overlay_latch.addr, src_addr, voodoo->overlay.vidOverlayDvdy, *(uint32_t *)src);
if (src_addr >= 0x800000)
fatal("overlay out of range!\n");
#endif
p = &(svga->monitor->target_buffer->line[displine])[svga->overlay_latch.x + svga->x_add];
if (banshee->voodoo->scrfilter && banshee->voodoo->scrfilterEnabled)
skip_filtering = ((banshee->vidProcCfg & VIDPROCCFG_FILTER_MODE_MASK) != VIDPROCCFG_FILTER_MODE_BILINEAR && !(banshee->vidProcCfg & VIDPROCCFG_H_SCALE_ENABLE) && !(banshee->vidProcCfg & VIDPROCCFG_FILTER_MODE_DITHER_4X4) && !(banshee->vidProcCfg & VIDPROCCFG_FILTER_MODE_DITHER_2X2));
else
skip_filtering = ((banshee->vidProcCfg & VIDPROCCFG_FILTER_MODE_MASK) != VIDPROCCFG_FILTER_MODE_BILINEAR && !(banshee->vidProcCfg & VIDPROCCFG_H_SCALE_ENABLE));
if (skip_filtering) {
/*No scaling or filtering required, just write straight to output buffer*/
OVERLAY_SAMPLE(p);
} else {
OVERLAY_SAMPLE(banshee->overlay_buffer[0]);
switch (banshee->vidProcCfg & VIDPROCCFG_FILTER_MODE_MASK) {
case VIDPROCCFG_FILTER_MODE_BILINEAR:
src = &svga->vram[src_addr2 & svga->vram_mask];
OVERLAY_SAMPLE(banshee->overlay_buffer[1]);
if (banshee->vidProcCfg & VIDPROCCFG_H_SCALE_ENABLE) {
for (x = 0; x < svga->overlay_latch.cur_xsize; x++) {
unsigned int x_coeff = (src_x & 0xfffff) >> 4;
unsigned int coeffs[4] = {
((0x10000 - x_coeff) * (0x10000 - y_coeff)) >> 16,
(x_coeff * (0x10000 - y_coeff)) >> 16,
((0x10000 - x_coeff) * y_coeff) >> 16,
(x_coeff * y_coeff) >> 16
};
uint32_t samp0 = banshee->overlay_buffer[0][src_x >> 20];
uint32_t samp1 = banshee->overlay_buffer[0][(src_x >> 20) + 1];
uint32_t samp2 = banshee->overlay_buffer[1][src_x >> 20];
uint32_t samp3 = banshee->overlay_buffer[1][(src_x >> 20) + 1];
int r = (((samp0 >> 16) & 0xff) * coeffs[0] + ((samp1 >> 16) & 0xff) * coeffs[1] + ((samp2 >> 16) & 0xff) * coeffs[2] + ((samp3 >> 16) & 0xff) * coeffs[3]) >> 16;
int g = (((samp0 >> 8) & 0xff) * coeffs[0] + ((samp1 >> 8) & 0xff) * coeffs[1] + ((samp2 >> 8) & 0xff) * coeffs[2] + ((samp3 >> 8) & 0xff) * coeffs[3]) >> 16;
int b = ((samp0 & 0xff) * coeffs[0] + (samp1 & 0xff) * coeffs[1] + (samp2 & 0xff) * coeffs[2] + (samp3 & 0xff) * coeffs[3]) >> 16;
p[x] = (r << 16) | (g << 8) | b;
src_x += voodoo->overlay.vidOverlayDudx;
}
} else {
for (x = 0; x < svga->overlay_latch.cur_xsize; x++) {
uint32_t samp0 = banshee->overlay_buffer[0][src_x >> 20];
uint32_t samp1 = banshee->overlay_buffer[1][src_x >> 20];
int r = (((samp0 >> 16) & 0xff) * (0x10000 - y_coeff) + ((samp1 >> 16) & 0xff) * y_coeff) >> 16;
int g = (((samp0 >> 8) & 0xff) * (0x10000 - y_coeff) + ((samp1 >> 8) & 0xff) * y_coeff) >> 16;
int b = ((samp0 & 0xff) * (0x10000 - y_coeff) + (samp1 & 0xff) * y_coeff) >> 16;
p[x] = (r << 16) | (g << 8) | b;
}
}
break;
case VIDPROCCFG_FILTER_MODE_DITHER_4X4:
if (banshee->voodoo->scrfilter && banshee->voodoo->scrfilterEnabled) {
uint8_t fil[2048 * 3];
uint8_t fil3[2048 * 3];
if (banshee->vidProcCfg & VIDPROCCFG_H_SCALE_ENABLE) /* leilei HACK - don't know of real 4x1 hscaled behavior yet, double for now */
{
for (x = 0; x < svga->overlay_latch.cur_xsize; x++) {
fil[x * 3] = (banshee->overlay_buffer[0][src_x >> 20]);
fil[x * 3 + 1] = (banshee->overlay_buffer[0][src_x >> 20] >> 8);
fil[x * 3 + 2] = (banshee->overlay_buffer[0][src_x >> 20] >> 16);
fil3[x * 3 + 0] = fil[x * 3 + 0];
fil3[x * 3 + 1] = fil[x * 3 + 1];
fil3[x * 3 + 2] = fil[x * 3 + 2];
src_x += voodoo->overlay.vidOverlayDudx;
}
} else {
for (x = 0; x < svga->overlay_latch.cur_xsize; x++) {
fil[x * 3] = (banshee->overlay_buffer[0][x]);
fil[x * 3 + 1] = (banshee->overlay_buffer[0][x] >> 8);
fil[x * 3 + 2] = (banshee->overlay_buffer[0][x] >> 16);
fil3[x * 3 + 0] = fil[x * 3 + 0];
fil3[x * 3 + 1] = fil[x * 3 + 1];
fil3[x * 3 + 2] = fil[x * 3 + 2];
}
}
if (y % 2 == 0) {
for (x = 0; x < svga->overlay_latch.cur_xsize; x++) {
fil[x * 3] = banshee->voodoo->purpleline[fil[x * 3 + 0]][0];
fil[x * 3 + 1] = banshee->voodoo->purpleline[fil[x * 3 + 1]][1];
fil[x * 3 + 2] = banshee->voodoo->purpleline[fil[x * 3 + 2]][2];
}
}
for (x = 1; x < svga->overlay_latch.cur_xsize; x++) {
fil3[x * 3] = vb_filter_v1_rb[fil[x * 3]][fil[(x - 1) * 3]];
fil3[x * 3 + 1] = vb_filter_v1_g[fil[x * 3 + 1]][fil[(x - 1) * 3 + 1]];
fil3[x * 3 + 2] = vb_filter_v1_rb[fil[x * 3 + 2]][fil[(x - 1) * 3 + 2]];
}
for (x = 1; x < svga->overlay_latch.cur_xsize; x++) {
fil[x * 3] = vb_filter_v1_rb[fil[x * 3]][fil3[(x - 1) * 3]];
fil[x * 3 + 1] = vb_filter_v1_g[fil[x * 3 + 1]][fil3[(x - 1) * 3 + 1]];
fil[x * 3 + 2] = vb_filter_v1_rb[fil[x * 3 + 2]][fil3[(x - 1) * 3 + 2]];
}
for (x = 1; x < svga->overlay_latch.cur_xsize; x++) {
fil3[x * 3] = vb_filter_v1_rb[fil[x * 3]][fil[(x - 1) * 3]];
fil3[x * 3 + 1] = vb_filter_v1_g[fil[x * 3 + 1]][fil[(x - 1) * 3 + 1]];
fil3[x * 3 + 2] = vb_filter_v1_rb[fil[x * 3 + 2]][fil[(x - 1) * 3 + 2]];
}
for (x = 0; x < svga->overlay_latch.cur_xsize; x++) {
fil[x * 3] = vb_filter_v1_rb[fil[x * 3]][fil3[(x + 1) * 3]];
fil[x * 3 + 1] = vb_filter_v1_g[fil[x * 3 + 1]][fil3[(x + 1) * 3 + 1]];
fil[x * 3 + 2] = vb_filter_v1_rb[fil[x * 3 + 2]][fil3[(x + 1) * 3 + 2]];
p[x] = (fil[x * 3 + 2] << 16) | (fil[x * 3 + 1] << 8) | fil[x * 3];
}
} else /* filter disabled by emulator option */
{
if (banshee->vidProcCfg & VIDPROCCFG_H_SCALE_ENABLE) {
for (x = 0; x < svga->overlay_latch.cur_xsize; x++) {
p[x] = banshee->overlay_buffer[0][src_x >> 20];
src_x += voodoo->overlay.vidOverlayDudx;
}
} else {
for (x = 0; x < svga->overlay_latch.cur_xsize; x++)
p[x] = banshee->overlay_buffer[0][x];
}
}
break;
case VIDPROCCFG_FILTER_MODE_DITHER_2X2:
if (banshee->voodoo->scrfilter && banshee->voodoo->scrfilterEnabled) {
uint8_t fil[2048 * 3];
uint8_t soak[2048 * 3];
uint8_t soak2[2048 * 3];
uint8_t samp1[2048 * 3];
uint8_t samp2[2048 * 3];
uint8_t samp3[2048 * 3];
uint8_t samp4[2048 * 3];
src = &svga->vram[src_addr2 & svga->vram_mask];
OVERLAY_SAMPLE(banshee->overlay_buffer[1]);
for (x = 0; x < svga->overlay_latch.cur_xsize; x++) {
samp1[x * 3] = (banshee->overlay_buffer[0][x]);
samp1[x * 3 + 1] = (banshee->overlay_buffer[0][x] >> 8);
samp1[x * 3 + 2] = (banshee->overlay_buffer[0][x] >> 16);
samp2[x * 3 + 0] = (banshee->overlay_buffer[0][x + 1]);
samp2[x * 3 + 1] = (banshee->overlay_buffer[0][x + 1] >> 8);
samp2[x * 3 + 2] = (banshee->overlay_buffer[0][x + 1] >> 16);
samp3[x * 3 + 0] = (banshee->overlay_buffer[1][x]);
samp3[x * 3 + 1] = (banshee->overlay_buffer[1][x] >> 8);
samp3[x * 3 + 2] = (banshee->overlay_buffer[1][x] >> 16);
samp4[x * 3 + 0] = (banshee->overlay_buffer[1][x + 1]);
samp4[x * 3 + 1] = (banshee->overlay_buffer[1][x + 1] >> 8);
samp4[x * 3 + 2] = (banshee->overlay_buffer[1][x + 1] >> 16);
/* sample two lines */
soak[x * 3 + 0] = vb_filter_bx_rb[samp1[x * 3 + 0]][samp2[x * 3 + 0]];
soak[x * 3 + 1] = vb_filter_bx_g[samp1[x * 3 + 1]][samp2[x * 3 + 1]];
soak[x * 3 + 2] = vb_filter_bx_rb[samp1[x * 3 + 2]][samp2[x * 3 + 2]];
soak2[x * 3 + 0] = vb_filter_bx_rb[samp3[x * 3 + 0]][samp4[x * 3 + 0]];
soak2[x * 3 + 1] = vb_filter_bx_g[samp3[x * 3 + 1]][samp4[x * 3 + 1]];
soak2[x * 3 + 2] = vb_filter_bx_rb[samp3[x * 3 + 2]][samp4[x * 3 + 2]];
/* then pour it on the rest */
fil[x * 3 + 0] = vb_filter_v1_rb[soak[x * 3 + 0]][soak2[x * 3 + 0]];
fil[x * 3 + 1] = vb_filter_v1_g[soak[x * 3 + 1]][soak2[x * 3 + 1]];
fil[x * 3 + 2] = vb_filter_v1_rb[soak[x * 3 + 2]][soak2[x * 3 + 2]];
}
if (banshee->vidProcCfg & VIDPROCCFG_H_SCALE_ENABLE) /* 2x2 on a scaled low res */
{
for (x = 0; x < svga->overlay_latch.cur_xsize; x++) {
p[x] = (fil[(src_x >> 20) * 3 + 2] << 16) | (fil[(src_x >> 20) * 3 + 1] << 8) | fil[(src_x >> 20) * 3];
src_x += voodoo->overlay.vidOverlayDudx;
}
} else {
for (x = 0; x < svga->overlay_latch.cur_xsize; x++) {
p[x] = (fil[x * 3 + 2] << 16) | (fil[x * 3 + 1] << 8) | fil[x * 3];
}
}
} else /* filter disabled by emulator option */
{
if (banshee->vidProcCfg & VIDPROCCFG_H_SCALE_ENABLE) {
for (x = 0; x < svga->overlay_latch.cur_xsize; x++) {
p[x] = banshee->overlay_buffer[0][src_x >> 20];
src_x += voodoo->overlay.vidOverlayDudx;
}
} else {
for (x = 0; x < svga->overlay_latch.cur_xsize; x++)
p[x] = banshee->overlay_buffer[0][x];
}
}
break;
case VIDPROCCFG_FILTER_MODE_POINT:
default:
if (banshee->vidProcCfg & VIDPROCCFG_H_SCALE_ENABLE) {
for (x = 0; x < svga->overlay_latch.cur_xsize; x++) {
p[x] = banshee->overlay_buffer[0][src_x >> 20];
src_x += voodoo->overlay.vidOverlayDudx;
}
} else {
for (x = 0; x < svga->overlay_latch.cur_xsize; x++)
p[x] = banshee->overlay_buffer[0][x];
}
break;
}
}
if (banshee->vidProcCfg & VIDPROCCFG_V_SCALE_ENABLE)
voodoo->overlay.src_y += voodoo->overlay.vidOverlayDvdy;
else
voodoo->overlay.src_y += (1 << 20);
}
void
banshee_set_overlay_addr(void *priv, UNUSED(uint32_t addr))
{
banshee_t *banshee = (banshee_t *) priv;
voodoo_t *voodoo = banshee->voodoo;
banshee->svga.overlay.addr = banshee->voodoo->leftOverlayBuf & 0xfffffff;
banshee->svga.overlay_latch.addr = banshee->voodoo->leftOverlayBuf & 0xfffffff;
memset(voodoo->dirty_line, 1, sizeof(voodoo->dirty_line));
}
static void
banshee_vsync_callback(svga_t *svga)
{
banshee_t *banshee = (banshee_t *) svga->priv;
voodoo_t *voodoo = banshee->voodoo;
voodoo->retrace_count++;
thread_wait_mutex(voodoo->swap_mutex);
if (voodoo->swap_pending && (voodoo->retrace_count > voodoo->swap_interval)) {
if (voodoo->swap_count > 0)
voodoo->swap_count--;
voodoo->swap_pending = 0;
thread_release_mutex(voodoo->swap_mutex);
memset(voodoo->dirty_line, 1, sizeof(voodoo->dirty_line));
voodoo->retrace_count = 0;
banshee_set_overlay_addr(banshee, voodoo->swap_offset);
thread_set_event(voodoo->wake_fifo_thread);
voodoo->frame_count++;
} else
thread_release_mutex(voodoo->swap_mutex);
voodoo->overlay.src_y = 0;
banshee->desktop_addr = banshee->vidDesktopStartAddr;
banshee->desktop_y = 0;
}
static uint8_t
banshee_pci_read(int func, int addr, void *priv)
{
const banshee_t *banshee = (banshee_t *) priv;
#if 0
svga_t *svga = &banshee->svga;
#endif
uint8_t ret = 0;
if (func)
return 0xff;
// banshee_log("Banshee PCI read %08X ", addr);
switch (addr) {
case 0x00:
ret = 0x1a;
break; /*3DFX*/
case 0x01:
ret = 0x12;
break;
case 0x02:
ret = (banshee->type == TYPE_BANSHEE) ? 0x03 : 0x05;
break;
case 0x03:
ret = 0x00;
break;
case 0x04:
ret = banshee->pci_regs[0x04] & 0x27;
break;
case 0x07:
ret = banshee->pci_regs[0x07] & 0x36;
break;
case 0x08:
ret = (banshee->type == TYPE_BANSHEE) ? 3 : 1;
break; /*Revision ID*/
case 0x09:
ret = 0;
break; /*Programming interface*/
case 0x0a:
ret = 0x00;
break; /*Supports VGA interface*/
case 0x0b:
ret = 0x03;
break;
case 0x0d:
ret = banshee->pci_regs[0x0d] & 0xf8;
break;
case 0x10:
ret = 0x00;
break; /*memBaseAddr0*/
case 0x11:
ret = 0x00;
break;
case 0x12:
ret = 0x00;
break;
case 0x13:
ret = banshee->memBaseAddr0 >> 24;
break;
case 0x14:
ret = 0x00;
break; /*memBaseAddr1*/
case 0x15:
ret = 0x00;
break;
case 0x16:
ret = 0x00;
break;
case 0x17:
ret = banshee->memBaseAddr1 >> 24;
break;
case 0x18:
ret = 0x01;
break; /*ioBaseAddr*/
case 0x19:
ret = banshee->ioBaseAddr >> 8;
break;
case 0x1a:
ret = banshee->ioBaseAddr >> 16;
break;
case 0x1b:
ret = banshee->ioBaseAddr >> 24;
break;
/*Subsystem vendor ID*/
case 0x2c:
ret = banshee->pci_regs[0x2c];
break;
case 0x2d:
ret = banshee->pci_regs[0x2d];
break;
case 0x2e:
ret = banshee->pci_regs[0x2e];
break;
case 0x2f:
ret = banshee->pci_regs[0x2f];
break;
case 0x30:
ret = banshee->pci_regs[0x30] & 0x01;
break; /*BIOS ROM address*/
case 0x31:
ret = 0x00;
break;
case 0x32:
ret = banshee->pci_regs[0x32];
break;
case 0x33:
ret = banshee->pci_regs[0x33];
break;
case 0x34:
ret = banshee->agp ? 0x54 : 0x60;
break;
case 0x3c:
ret = banshee->pci_regs[0x3c];
break;
case 0x3d:
ret = 0x01;
break; /*INTA*/
case 0x3e:
ret = 0x04;
break;
case 0x3f:
ret = 0xff;
break;
case 0x40:
ret = 0x01;
break;
case 0x50:
ret = banshee->pci_regs[0x50];
break;
case 0x54:
ret = 0x02;
break;
case 0x55:
ret = 0x60;
break;
case 0x56:
ret = 0x10;
break; /* assumed AGP 1.0 */
case 0x58:
ret = (banshee->type == TYPE_BANSHEE) ? 0x21 : 0x23;
break;
case 0x59:
ret = 0x02;
break;
case 0x5b:
ret = 0x07;
break;
case 0x5c:
ret = banshee->pci_regs[0x5c];
break;
case 0x5d:
ret = banshee->pci_regs[0x5d];
break;
case 0x5e:
ret = banshee->pci_regs[0x5e];
break;
case 0x5f:
ret = banshee->pci_regs[0x5f];
break;
case 0x60:
ret = 0x01;
break;
case 0x62:
ret = 0x21;
break;
case 0x64:
ret = banshee->pci_regs[0x64];
break;
case 0x65:
ret = banshee->pci_regs[0x65];
break;
case 0x66:
ret = banshee->pci_regs[0x66];
break;
case 0x67:
ret = banshee->pci_regs[0x67];
break;
default:
break;
}
#if 0
banshee_log("%02X\n", ret);
#endif
return ret;
}
static void
banshee_pci_write(int func, int addr, uint8_t val, void *priv)
{
banshee_t *banshee = (banshee_t *) priv;
#if 0
svga_t *svga = &banshee->svga;
#endif
if (func)
return;
#if 0
banshee_log("Banshee write %08X %02X %04X:%08X\n", addr, val, CS, cpu_state.pc);
#endif
switch (addr) {
case 0x00:
case 0x01:
case 0x02:
case 0x03:
case 0x08:
case 0x09:
case 0x0a:
case 0x0b:
case 0x3d:
case 0x3e:
case 0x3f:
return;
case PCI_REG_COMMAND:
if (val & PCI_COMMAND_IO) {
io_removehandler(0x03c0, 0x0020, banshee_in, NULL, NULL, banshee_out, NULL, NULL, banshee);
if (banshee->ioBaseAddr)
io_removehandler(banshee->ioBaseAddr, 0x0100, banshee_ext_in, NULL, banshee_ext_inl, banshee_ext_out, NULL, banshee_ext_outl, banshee);
io_sethandler(0x03c0, 0x0020, banshee_in, NULL, NULL, banshee_out, NULL, NULL, banshee);
if (banshee->ioBaseAddr)
io_sethandler(banshee->ioBaseAddr, 0x0100, banshee_ext_in, NULL, banshee_ext_inl, banshee_ext_out, NULL, banshee_ext_outl, banshee);
} else {
io_removehandler(0x03c0, 0x0020, banshee_in, NULL, NULL, banshee_out, NULL, NULL, banshee);
io_removehandler(banshee->ioBaseAddr, 0x0100, banshee_ext_in, NULL, banshee_ext_inl, banshee_ext_out, NULL, banshee_ext_outl, banshee);
}
banshee->pci_regs[PCI_REG_COMMAND] = val & 0x27;
banshee_updatemapping(banshee);
return;
case 0x07:
banshee->pci_regs[0x07] = val & 0x3e;
return;
case 0x0d:
banshee->pci_regs[0x0d] = val & 0xf8;
return;
case 0x13:
banshee->memBaseAddr0 = (val & 0xfe) << 24;
banshee_updatemapping(banshee);
return;
case 0x17:
banshee->memBaseAddr1 = (val & 0xfe) << 24;
banshee_updatemapping(banshee);
return;
case 0x19:
if (banshee->pci_regs[PCI_REG_COMMAND] & PCI_COMMAND_IO)
io_removehandler(banshee->ioBaseAddr, 0x0100, banshee_ext_in, NULL, banshee_ext_inl, banshee_ext_out, NULL, banshee_ext_outl, banshee);
banshee->ioBaseAddr &= 0xffff00ff;
banshee->ioBaseAddr |= val << 8;
if ((banshee->pci_regs[PCI_REG_COMMAND] & PCI_COMMAND_IO) && banshee->ioBaseAddr)
io_sethandler(banshee->ioBaseAddr, 0x0100, banshee_ext_in, NULL, banshee_ext_inl, banshee_ext_out, NULL, banshee_ext_outl, banshee);
banshee_log("Banshee ioBaseAddr=%08x\n", banshee->ioBaseAddr);
return;
case 0x1a:
banshee->ioBaseAddr &= 0xff00ffff;
banshee->ioBaseAddr |= val << 16;
break;
case 0x1b:
banshee->ioBaseAddr &= 0x00ffffff;
banshee->ioBaseAddr |= val << 24;
break;
case 0x30:
case 0x32:
case 0x33:
if (!banshee->has_bios)
return;
banshee->pci_regs[addr] = val;
if (banshee->pci_regs[0x30] & 0x01) {
uint32_t biosaddr = (banshee->pci_regs[0x32] << 16) | (banshee->pci_regs[0x33] << 24);
banshee_log("Banshee bios_rom enabled at %08x\n", biosaddr);
mem_mapping_set_addr(&banshee->bios_rom.mapping, biosaddr, 0x10000);
mem_mapping_enable(&banshee->bios_rom.mapping);
} else {
banshee_log("Banshee bios_rom disabled\n");
mem_mapping_disable(&banshee->bios_rom.mapping);
}
return;
case 0x3c:
case 0x50:
case 0x65:
case 0x67:
banshee->pci_regs[addr] = val;
return;
case 0x5c:
banshee->pci_regs[0x5c] = val & 0x27;
return;
case 0x5d:
banshee->pci_regs[0x5d] = val & 0x03;
return;
case 0x5f:
banshee->pci_regs[0x5e] = val;
return;
case 0x64:
banshee->pci_regs[0x64] = val & 0x03;
return;
case 0x66:
banshee->pci_regs[0x66] = val & 0xc0;
return;
default:
break;
}
}
// clang-format off
static const device_config_t banshee_sgram_config[] = {
{
.name = "memory",
.description = "Memory size",
.type = CONFIG_SELECTION,
.selection = {
{
.description = "8 MB",
.value = 8
},
{
.description = "16 MB",
.value = 16
},
{
.description = ""
}
},
.default_int = 16
},
{
.name = "bilinear",
.description = "Bilinear filtering",
.type = CONFIG_BINARY,
.default_int = 1
},
{
.name = "dithersub",
.description = "Dither subtraction",
.type = CONFIG_BINARY,
.default_int = 1
},
{
.name = "dacfilter",
.description = "Screen Filter",
.type = CONFIG_BINARY,
.default_int = 0
},
{
.name = "render_threads",
.description = "Render threads",
.type = CONFIG_SELECTION,
.selection = {
{
.description = "1",
.value = 1
},
{
.description = "2",
.value = 2
},
{
.description = "4",
.value = 4
},
{
.description = ""
}
},
.default_int = 2
},
#ifndef NO_CODEGEN
{
.name = "recompiler",
.description = "Recompiler",
.type = CONFIG_BINARY,
.default_int = 1
},
#endif
{
.type = CONFIG_END
}
};
static const device_config_t banshee_sgram_16mbonly_config[] = {
{
.name = "bilinear",
.description = "Bilinear filtering",
.type = CONFIG_BINARY,
.default_int = 1
},
{
.name = "dithersub",
.description = "Dither subtraction",
.type = CONFIG_BINARY,
.default_int = 1
},
{
.name = "dacfilter",
.description = "Screen Filter",
.type = CONFIG_BINARY,
.default_int = 0
},
{
.name = "render_threads",
.description = "Render threads",
.type = CONFIG_SELECTION,
.selection = {
{
.description = "1",
.value = 1
},
{
.description = "2",
.value = 2
},
{
.description = "4",
.value = 4
},
{
.description = ""
}
},
.default_int = 2
},
#ifndef NO_CODEGEN
{
.name = "recompiler",
.description = "Recompiler",
.type = CONFIG_BINARY,
.default_int = 1
},
#endif
{
.type = CONFIG_END
}
};
static const device_config_t banshee_sdram_config[] = {
{
.name = "bilinear",
.description = "Bilinear filtering",
.type = CONFIG_BINARY,
.default_int = 1
},
{
.name = "dithersub",
.description = "Dither subtraction",
.type = CONFIG_BINARY,
.default_int = 1
},
{
.name = "dacfilter",
.description = "Screen Filter",
.type = CONFIG_BINARY,
.default_int = 0
},
{
.name = "render_threads",
.description = "Render threads",
.type = CONFIG_SELECTION,
.selection = {
{
.description = "1",
.value = 1
},
{
.description = "2",
.value = 2
},
{
.description = "4",
.value = 4
},
{
.description = ""
}
},
.default_int = 2
},
#ifndef NO_CODEGEN
{
.name = "recompiler",
.description = "Recompiler",
.type = CONFIG_BINARY,
.default_int = 1
},
#endif
{
.type = CONFIG_END
}
};
// clang-format on
static void *
banshee_init_common(const device_t *info, char *fn, int has_sgram, int type, int voodoo_type, int agp)
{
int mem_size;
banshee_t *banshee = malloc(sizeof(banshee_t));
memset(banshee, 0, sizeof(banshee_t));
banshee->type = type;
banshee->agp = agp;
banshee->has_bios = !!fn;
if (banshee->has_bios) {
rom_init(&banshee->bios_rom, fn, 0xc0000, 0x10000, 0xffff, 0, MEM_MAPPING_EXTERNAL);
mem_mapping_disable(&banshee->bios_rom.mapping);
}
if (!banshee->has_bios)
#if 0
mem_size = info->local; /* fixed size for on-board chips */
#endif
mem_size = device_get_config_int("memory"); /* MS-6168 / Bora Pro can do both 8 and 16 MB. */
else if (has_sgram) {
if ((banshee->type == TYPE_V3_1000) || (banshee->type == TYPE_VELOCITY200))
mem_size = 16; /* Our Voodoo 3 1000 and Velocity 200 bios'es are hardcoded to 16 MB. */
else if (banshee->type == TYPE_VELOCITY100)
mem_size = 8; /* Velocity 100 only supports 8 MB */
else
mem_size = device_get_config_int("memory");
} else
mem_size = 16; /* SDRAM Banshee only supports 16 MB */
svga_init(info, &banshee->svga, banshee, mem_size << 20,
banshee_recalctimings,
banshee_in, banshee_out,
banshee_hwcursor_draw,
banshee_overlay_draw);
banshee->svga.vsync_callback = banshee_vsync_callback;
mem_mapping_add(&banshee->linear_mapping, 0, 0, banshee_read_linear,
banshee_read_linear_w,
banshee_read_linear_l,
banshee_write_linear,
banshee_write_linear_w,
banshee_write_linear_l,
NULL,
MEM_MAPPING_EXTERNAL,
&banshee->svga);
mem_mapping_add(&banshee->reg_mapping_low, 0, 0, banshee_reg_read,
banshee_reg_readw,
banshee_reg_readl,
banshee_reg_write,
banshee_reg_writew,
banshee_reg_writel,
NULL,
MEM_MAPPING_EXTERNAL,
banshee);
mem_mapping_add(&banshee->reg_mapping_high, 0, 0, banshee_reg_read,
banshee_reg_readw,
banshee_reg_readl,
banshee_reg_write,
banshee_reg_writew,
banshee_reg_writel,
NULL,
MEM_MAPPING_EXTERNAL,
banshee);
banshee->svga.vblank_start = banshee_vblank_start;
#if 0
io_sethandler(0x03c0, 0x0020, banshee_in, NULL, NULL, banshee_out, NULL, NULL, banshee);
#endif
banshee->svga.bpp = 8;
banshee->svga.miscout = 1;
banshee->dramInit0 = 1 << 27;
if (has_sgram && mem_size == 16)
banshee->dramInit0 |= (1 << 26); /*2xSGRAM = 16 MB*/
if (!has_sgram)
banshee->dramInit1 = 1 << 30; /*SDRAM*/
banshee->svga.decode_mask = 0x1ffffff;
if (banshee->has_bios)
pci_add_card(banshee->agp ? PCI_ADD_AGP : PCI_ADD_NORMAL, banshee_pci_read, banshee_pci_write, banshee, &banshee->pci_slot);
else
pci_add_card(banshee->agp ? PCI_ADD_AGP : PCI_ADD_VIDEO, banshee_pci_read, banshee_pci_write, banshee, &banshee->pci_slot);
banshee->voodoo = voodoo_2d3d_card_init(voodoo_type);
banshee->voodoo->priv = banshee;
banshee->voodoo->vram = banshee->svga.vram;
banshee->voodoo->changedvram = banshee->svga.changedvram;
banshee->voodoo->fb_mem = banshee->svga.vram;
banshee->voodoo->fb_mask = banshee->svga.vram_mask;
banshee->voodoo->tex_mem[0] = banshee->svga.vram;
banshee->voodoo->tex_mem_w[0] = (uint16_t *) banshee->svga.vram;
banshee->voodoo->tex_mem[1] = banshee->svga.vram;
banshee->voodoo->tex_mem_w[1] = (uint16_t *) banshee->svga.vram;
banshee->voodoo->texture_mask = banshee->svga.vram_mask;
banshee->voodoo->cmd_status = (1 << 28);
voodoo_generate_filter_v1(banshee->voodoo);
banshee->vidSerialParallelPort = VIDSERIAL_DDC_DCK_W | VIDSERIAL_DDC_DDA_W;
banshee->i2c = i2c_gpio_init("i2c_voodoo_banshee");
banshee->i2c_ddc = i2c_gpio_init("ddc_voodoo_banshee");
banshee->ddc = ddc_init(i2c_gpio_get_bus(banshee->i2c_ddc));
banshee->svga.conv_16to32 = banshee_conv_16to32;
switch (type) {
case TYPE_BANSHEE:
if (has_sgram) {
banshee->pci_regs[0x2c] = 0x1a;
banshee->pci_regs[0x2d] = 0x12;
banshee->pci_regs[0x2e] = 0x04;
banshee->pci_regs[0x2f] = 0x00;
} else {
banshee->pci_regs[0x2c] = 0x02;
banshee->pci_regs[0x2d] = 0x11;
banshee->pci_regs[0x2e] = 0x17;
banshee->pci_regs[0x2f] = 0x10;
}
break;
case TYPE_V3_1000:
banshee->pci_regs[0x2c] = 0x1a;
banshee->pci_regs[0x2d] = 0x12;
banshee->pci_regs[0x2e] = 0x52;
banshee->pci_regs[0x2f] = 0x00;
break;
case TYPE_V3_2000:
banshee->pci_regs[0x2c] = 0x1a;
banshee->pci_regs[0x2d] = 0x12;
banshee->pci_regs[0x2e] = 0x30;
banshee->pci_regs[0x2f] = 0x00;
break;
case TYPE_V3_3000:
banshee->pci_regs[0x2c] = 0x1a;
banshee->pci_regs[0x2d] = 0x12;
banshee->pci_regs[0x2e] = 0x3a;
banshee->pci_regs[0x2f] = 0x00;
break;
case TYPE_V3_3500:
banshee->pci_regs[0x2c] = 0x1a;
banshee->pci_regs[0x2d] = 0x12;
banshee->pci_regs[0x2e] = 0x60;
banshee->pci_regs[0x2f] = 0x00;
break;
case TYPE_V3_3500_COMPAQ:
banshee->pci_regs[0x2c] = 0x1a;
banshee->pci_regs[0x2d] = 0x12;
banshee->pci_regs[0x2e] = 0x4f;
banshee->pci_regs[0x2f] = 0x12;
break;
case TYPE_V3_3500_SI:
banshee->pci_regs[0x2c] = 0x1a;
banshee->pci_regs[0x2d] = 0x12;
banshee->pci_regs[0x2e] = 0x61;
banshee->pci_regs[0x2f] = 0x00;
break;
case TYPE_VELOCITY100:
banshee->pci_regs[0x2c] = 0x1a;
banshee->pci_regs[0x2d] = 0x12;
banshee->pci_regs[0x2e] = 0x4b;
banshee->pci_regs[0x2f] = 0x00;
break;
case TYPE_VELOCITY200:
banshee->pci_regs[0x2c] = 0x1a;
banshee->pci_regs[0x2d] = 0x12;
banshee->pci_regs[0x2e] = 0x54;
banshee->pci_regs[0x2f] = 0x00;
break;
default:
break;
}
video_inform(VIDEO_FLAG_TYPE_SPECIAL, banshee->agp ? &timing_banshee_agp : &timing_banshee);
return banshee;
}
static void *
banshee_init(const device_t *info)
{
return banshee_init_common(info, ROM_BANSHEE, 1, TYPE_BANSHEE, VOODOO_BANSHEE, 0);
}
static void *
creative_banshee_init(const device_t *info)
{
return banshee_init_common(info, ROM_CREATIVE_BANSHEE, 0, TYPE_BANSHEE, VOODOO_BANSHEE, 0);
}
static void *
v3_1000_init(const device_t *info)
{
return banshee_init_common(info, ROM_VOODOO3_1000, 1, TYPE_V3_1000, VOODOO_3, 0);
}
static void *
v3_1000_agp_init(const device_t *info)
{
return banshee_init_common(info, ROM_VOODOO3_1000, 1, TYPE_V3_1000, VOODOO_3, 1);
}
static void *
v3_2000_init(const device_t *info)
{
return banshee_init_common(info, ROM_VOODOO3_2000, 0, TYPE_V3_2000, VOODOO_3, 0);
}
static void *
v3_2000_agp_init(const device_t *info)
{
return banshee_init_common(info, ROM_VOODOO3_2000, 0, TYPE_V3_2000, VOODOO_3, 1);
}
static void *
v3_2000_agp_onboard_init(const device_t *info)
{
return banshee_init_common(info, NULL, 1, TYPE_V3_2000, VOODOO_3, 1);
}
static void *
v3_3000_init(const device_t *info)
{
return banshee_init_common(info, ROM_VOODOO3_3000, 0, TYPE_V3_3000, VOODOO_3, 0);
}
static void *
v3_3000_agp_init(const device_t *info)
{
return banshee_init_common(info, ROM_VOODOO3_3000, 0, TYPE_V3_3000, VOODOO_3, 1);
}
static void *
v3_3500_agp_ntsc_init(const device_t *info)
{
return banshee_init_common(info, ROM_VOODOO3_3500_AGP_NTSC, 0, TYPE_V3_3500, VOODOO_3, 1);
}
static void *
v3_3500_agp_pal_init(const device_t *info)
{
return banshee_init_common(info, ROM_VOODOO3_3500_AGP_PAL, 0, TYPE_V3_3500, VOODOO_3, 1);
}
static void *
compaq_v3_3500_agp_init(const device_t *info)
{
return banshee_init_common(info, ROM_VOODOO3_3500_AGP_COMPAQ, 0, TYPE_V3_3500_COMPAQ, VOODOO_3, 1);
}
static void *
v3_3500_se_agp_init(const device_t *info)
{
return banshee_init_common(info, ROM_VOODOO3_3500_SE_AGP, 0, TYPE_V3_3500, VOODOO_3, 1);
}
static void *
v3_3500_si_agp_init(const device_t *info)
{
return banshee_init_common(info, ROM_VOODOO3_3500_SI_AGP, 0, TYPE_V3_3500_SI, VOODOO_3, 1);
}
static void *
velocity_100_agp_init(const device_t *info)
{
return banshee_init_common(info, ROM_VELOCITY_100, 1, TYPE_VELOCITY100, VOODOO_3, 1);
}
static void *
velocity_200_agp_init(const device_t *info)
{
return banshee_init_common(info, ROM_VELOCITY_200, 1, TYPE_VELOCITY200, VOODOO_3, 1);
}
static int
banshee_available(void)
{
return rom_present(ROM_BANSHEE);
}
static int
creative_banshee_available(void)
{
return rom_present(ROM_CREATIVE_BANSHEE);
}
static int
v3_1000_available(void)
{
return rom_present(ROM_VOODOO3_1000);
}
#define v3_1000_agp_available v3_1000_available
static int
v3_2000_available(void)
{
return rom_present(ROM_VOODOO3_2000);
}
#define v3_2000_agp_available v3_2000_available
static int
v3_3000_available(void)
{
return rom_present(ROM_VOODOO3_3000);
}
#define v3_3000_agp_available v3_3000_available
static int
v3_3500_agp_ntsc_available(void)
{
return rom_present(ROM_VOODOO3_3500_AGP_NTSC);
}
static int
v3_3500_agp_pal_available(void)
{
return rom_present(ROM_VOODOO3_3500_AGP_PAL);
}
static int
compaq_v3_3500_agp_available(void)
{
return rom_present(ROM_VOODOO3_3500_AGP_COMPAQ);
}
static int
v3_3500_se_agp_available(void)
{
return rom_present(ROM_VOODOO3_3500_SE_AGP);
}
static int
v3_3500_si_agp_available(void)
{
return rom_present(ROM_VOODOO3_3500_SI_AGP);
}
static int
velocity_100_available(void)
{
return rom_present(ROM_VELOCITY_100);
}
static int
velocity_200_available(void)
{
return rom_present(ROM_VELOCITY_200);
}
static void
banshee_close(void *priv)
{
banshee_t *banshee = (banshee_t *) priv;
voodoo_card_close(banshee->voodoo);
svga_close(&banshee->svga);
ddc_close(banshee->ddc);
i2c_gpio_close(banshee->i2c_ddc);
i2c_gpio_close(banshee->i2c);
free(banshee);
}
static void
banshee_speed_changed(void *priv)
{
banshee_t *banshee = (banshee_t *) priv;
svga_recalctimings(&banshee->svga);
}
static void
banshee_force_redraw(void *priv)
{
banshee_t *banshee = (banshee_t *) priv;
banshee->svga.fullchange = changeframecount;
}
const device_t voodoo_banshee_device = {
.name = "3Dfx Voodoo Banshee",
.internal_name = "voodoo_banshee_pci",
.flags = DEVICE_PCI,
.local = 0,
.init = banshee_init,
.close = banshee_close,
.reset = NULL,
{ .available = banshee_available },
.speed_changed = banshee_speed_changed,
.force_redraw = banshee_force_redraw,
.config = banshee_sgram_config
};
const device_t creative_voodoo_banshee_device = {
.name = "Creative 3D Blaster Banshee",
.internal_name = "ctl3d_banshee_pci",
.flags = DEVICE_PCI,
.local = 0,
.init = creative_banshee_init,
.close = banshee_close,
.reset = NULL,
{ .available = creative_banshee_available },
.speed_changed = banshee_speed_changed,
.force_redraw = banshee_force_redraw,
.config = banshee_sdram_config
};
const device_t voodoo_3_1000_device = {
.name = "3dfx Voodoo3 1000",
.internal_name = "voodoo3_1k_pci",
.flags = DEVICE_PCI,
.local = 0,
.init = v3_1000_init,
.close = banshee_close,
.reset = NULL,
{ .available = v3_1000_available },
.speed_changed = banshee_speed_changed,
.force_redraw = banshee_force_redraw,
.config = banshee_sgram_config
};
const device_t voodoo_3_1000_agp_device = {
.name = "3dfx Voodoo3 1000",
.internal_name = "voodoo3_1k_agp",
.flags = DEVICE_AGP,
.local = 0,
.init = v3_1000_agp_init,
.close = banshee_close,
.reset = NULL,
{ .available = v3_1000_agp_available },
.speed_changed = banshee_speed_changed,
.force_redraw = banshee_force_redraw,
.config = banshee_sgram_16mbonly_config
};
const device_t voodoo_3_2000_device = {
.name = "3dfx Voodoo3 2000",
.internal_name = "voodoo3_2k_pci",
.flags = DEVICE_PCI,
.local = 0,
.init = v3_2000_init,
.close = banshee_close,
.reset = NULL,
{ .available = v3_2000_available },
.speed_changed = banshee_speed_changed,
.force_redraw = banshee_force_redraw,
.config = banshee_sdram_config
};
const device_t voodoo_3_2000_agp_device = {
.name = "3dfx Voodoo3 2000",
.internal_name = "voodoo3_2k_agp",
.flags = DEVICE_AGP,
.local = 0,
.init = v3_2000_agp_init,
.close = banshee_close,
.reset = NULL,
{ .available = v3_2000_agp_available },
.speed_changed = banshee_speed_changed,
.force_redraw = banshee_force_redraw,
.config = banshee_sdram_config
};
const device_t voodoo_3_2000_agp_onboard_8m_device = {
.name = "3dfx Voodoo3 2000 (On-Board 8MB SGRAM)",
.internal_name = "voodoo3_2k_agp_onboard_8m",
.flags = DEVICE_AGP,
.local = 8,
.init = v3_2000_agp_onboard_init,
.close = banshee_close,
.reset = NULL,
{ .available = NULL },
.speed_changed = banshee_speed_changed,
.force_redraw = banshee_force_redraw,
.config = banshee_sgram_config
};
const device_t voodoo_3_3000_device = {
.name = "3dfx Voodoo3 3000",
.internal_name = "voodoo3_3k_pci",
.flags = DEVICE_PCI,
.local = 0,
.init = v3_3000_init,
.close = banshee_close,
.reset = NULL,
{ .available = v3_3000_available },
.speed_changed = banshee_speed_changed,
.force_redraw = banshee_force_redraw,
.config = banshee_sdram_config
};
const device_t voodoo_3_3000_agp_device = {
.name = "3dfx Voodoo3 3000",
.internal_name = "voodoo3_3k_agp",
.flags = DEVICE_AGP,
.local = 0,
.init = v3_3000_agp_init,
.close = banshee_close,
.reset = NULL,
{ .available = v3_3000_agp_available },
.speed_changed = banshee_speed_changed,
.force_redraw = banshee_force_redraw,
.config = banshee_sdram_config
};
const device_t voodoo_3_3500_agp_ntsc_device = {
.name = "3dfx Voodoo3 3500 TV (NTSC)",
.internal_name = "voodoo3_3500_agp_ntsc",
.flags = DEVICE_AGP,
.local = 0,
.init = v3_3500_agp_ntsc_init,
.close = banshee_close,
.reset = NULL,
{ .available = v3_3500_agp_ntsc_available },
.speed_changed = banshee_speed_changed,
.force_redraw = banshee_force_redraw,
.config = banshee_sdram_config
};
const device_t voodoo_3_3500_agp_pal_device = {
.name = "3dfx Voodoo3 3500 TV (PAL)",
.internal_name = "voodoo3_3500_agp_pal",
.flags = DEVICE_AGP,
.local = 0,
.init = v3_3500_agp_pal_init,
.close = banshee_close,
.reset = NULL,
{ .available = v3_3500_agp_pal_available },
.speed_changed = banshee_speed_changed,
.force_redraw = banshee_force_redraw,
.config = banshee_sdram_config
};
const device_t compaq_voodoo_3_3500_agp_device = {
.name = "Compaq Voodoo3 3500 TV",
.internal_name = "compaq_voodoo3_3500_agp",
.flags = DEVICE_AGP,
.local = 0,
.init = compaq_v3_3500_agp_init,
.close = banshee_close,
.reset = NULL,
{ .available = compaq_v3_3500_agp_available },
.speed_changed = banshee_speed_changed,
.force_redraw = banshee_force_redraw,
.config = banshee_sdram_config
};
const device_t voodoo_3_3500_se_agp_device = {
.name = "Falcon Northwest Voodoo3 3500 SE",
.internal_name = "voodoo3_3500_se_agp",
.flags = DEVICE_AGP,
.local = 0,
.init = v3_3500_se_agp_init,
.close = banshee_close,
.reset = NULL,
{ .available = v3_3500_se_agp_available },
.speed_changed = banshee_speed_changed,
.force_redraw = banshee_force_redraw,
.config = banshee_sdram_config
};
const device_t voodoo_3_3500_si_agp_device = {
.name = "3dfx Voodoo3 3500 SI",
.internal_name = "voodoo3_3500_si_agp",
.flags = DEVICE_AGP,
.local = 0,
.init = v3_3500_si_agp_init,
.close = banshee_close,
.reset = NULL,
{ .available = v3_3500_si_agp_available },
.speed_changed = banshee_speed_changed,
.force_redraw = banshee_force_redraw,
.config = banshee_sdram_config
};
const device_t velocity_100_agp_device = {
.name = "3dfx Velocity 100",
.internal_name = "velocity100_agp",
.flags = DEVICE_AGP,
.local = 0,
.init = velocity_100_agp_init,
.close = banshee_close,
.reset = NULL,
{ .available = velocity_100_available },
.speed_changed = banshee_speed_changed,
.force_redraw = banshee_force_redraw,
.config = banshee_sdram_config
};
const device_t velocity_200_agp_device = {
.name = "3dfx Velocity 200",
.internal_name = "velocity200_agp",
.flags = DEVICE_AGP,
.local = 0,
.init = velocity_200_agp_init,
.close = banshee_close,
.reset = NULL,
{ .available = velocity_200_available },
.speed_changed = banshee_speed_changed,
.force_redraw = banshee_force_redraw,
.config = banshee_sgram_16mbonly_config
};
``` | /content/code_sandbox/src/video/vid_voodoo_banshee.c | c | 2016-06-25T22:29:10 | 2024-08-16T19:09:21 | 86Box | 86Box/86Box | 2,616 | 38,273 |
```c
/*
* 86Box A hypervisor and IBM PC system emulator that specializes in
* running old operating systems and software designed for IBM
* PC systems and compatibles from 1981 through fairly recent
* system designs based on the PCI bus.
*
* This file is part of the 86Box distribution.
*
* Emulation of the 8514/A card from IBM for the MCA bus and
* ISA bus clones.
*
*
*
* Authors: TheCollector1995.
*
*/
#include <stdarg.h>
#include <stdint.h>
#include <stdio.h>
#include <string.h>
#include <stdlib.h>
#include <wchar.h>
#include <stdatomic.h>
#define HAVE_STDARG_H
#include <86box/86box.h>
#include <86box/device.h>
#include <86box/io.h>
#include <86box/machine.h>
#include <86box/mem.h>
#include <86box/timer.h>
#include <86box/mca.h>
#include <86box/rom.h>
#include <86box/plat.h>
#include <86box/thread.h>
#include <86box/video.h>
#include <86box/vid_8514a.h>
#include <86box/vid_xga.h>
#include <86box/vid_svga.h>
#include <86box/vid_svga_render.h>
#include <86box/vid_ati_eeprom.h>
#include <86box/vid_ati_mach8.h>
#include "cpu.h"
#ifdef ATI_8514_ULTRA
#define BIOS_MACH8_ROM_PATH "roms/video/mach8/11301113140.BIN"
static video_timings_t timing_8514ultra_isa = { .type = VIDEO_ISA, .write_b = 3, .write_w = 3, .write_l = 6, .read_b = 5, .read_w = 5, .read_l = 10 };
#endif
static void ibm8514_accel_outb(uint16_t port, uint8_t val, void *priv);
static void ibm8514_accel_outw(uint16_t port, uint16_t val, void *priv);
static uint8_t ibm8514_accel_inb(uint16_t port, void *priv);
static uint16_t ibm8514_accel_inw(uint16_t port, void *priv);
#ifdef ENABLE_IBM8514_LOG
int ibm8514_do_log = ENABLE_IBM8514_LOG;
static void
ibm8514_log(const char *fmt, ...)
{
va_list ap;
if (ibm8514_do_log) {
va_start(ap, fmt);
pclog_ex(fmt, ap);
va_end(ap);
}
}
#else
# define ibm8514_log(fmt, ...)
#endif
#define WRITE8(addr, var, val) \
switch ((addr) & 1) { \
case 0: \
var = (var & 0xff00) | (val); \
break; \
case 1: \
var = (var & 0x00ff) | ((val) << 8); \
break; \
}
#define READ8(addr, var) \
switch ((addr) & 1) { \
case 0: \
temp = (var) & 0xff; \
break; \
case 1: \
temp = ((var) >> 8) & 0xff; \
break; \
}
#define READ_PIXTRANS_WORD(cx, n) \
if ((cmd <= 1) || (cmd == 5)) { \
temp = dev->vram[((dev->accel.cy * dev->pitch) + (cx) + (n)) & dev->vram_mask]; \
temp |= (dev->vram[((dev->accel.cy * dev->pitch) + (cx) + (n + 1)) & dev->vram_mask] << 8); \
} else { \
temp = dev->vram[(dev->accel.dest + (cx) + (n)) & dev->vram_mask]; \
temp |= (dev->vram[(dev->accel.dest + (cx) + (n + 1)) & dev->vram_mask] << 8); \
}
#define READ(addr, dat) \
if (dev->bpp) { \
dat = vram_w[(addr) & (dev->vram_mask >> 1)]; \
} else { \
dat = (dev->vram[(addr) & (dev->vram_mask)]); \
}
#define MIX(mixmode, dest_dat, src_dat) \
{ \
switch ((mixmode) ? (dev->accel.frgd_mix & 0x1f) : (dev->accel.bkgd_mix & 0x1f)) { \
case 0x00: \
dest_dat = ~dest_dat; \
break; \
case 0x01: \
dest_dat = 0; \
break; \
case 0x02: \
dest_dat = ~0; \
break; \
case 0x03: \
dest_dat = dest_dat; \
break; \
case 0x04: \
dest_dat = ~src_dat; \
break; \
case 0x05: \
dest_dat = src_dat ^ dest_dat; \
break; \
case 0x06: \
dest_dat = ~(src_dat ^ dest_dat); \
break; \
case 0x07: \
dest_dat = src_dat; \
break; \
case 0x08: \
dest_dat = ~(src_dat & dest_dat); \
break; \
case 0x09: \
dest_dat = ~src_dat | dest_dat; \
break; \
case 0x0a: \
dest_dat = src_dat | ~dest_dat; \
break; \
case 0x0b: \
dest_dat = src_dat | dest_dat; \
break; \
case 0x0c: \
dest_dat = src_dat & dest_dat; \
break; \
case 0x0d: \
dest_dat = src_dat & ~dest_dat; \
break; \
case 0x0e: \
dest_dat = ~src_dat & dest_dat; \
break; \
case 0x0f: \
dest_dat = ~(src_dat | dest_dat); \
break; \
case 0x10: \
dest_dat = MIN(src_dat, dest_dat); \
break; \
case 0x11: \
dest_dat = dest_dat - src_dat; \
break; \
case 0x12: \
dest_dat = src_dat - dest_dat; \
break; \
case 0x13: \
dest_dat = src_dat + dest_dat; \
break; \
case 0x14: \
dest_dat = MAX(src_dat, dest_dat); \
break; \
case 0x15: \
dest_dat = (dest_dat - src_dat) >> 1; \
break; \
case 0x16: \
dest_dat = (src_dat - dest_dat) >> 1; \
break; \
case 0x17: \
dest_dat = (dest_dat + src_dat) >> 1; \
break; \
case 0x18: \
dest_dat = MAX(0, (dest_dat - src_dat)); \
break; \
case 0x19: \
dest_dat = MAX(0, (dest_dat - src_dat)); \
break; \
case 0x1a: \
dest_dat = MAX(0, (src_dat - dest_dat)); \
break; \
case 0x1b: \
dest_dat = MIN(~0, (dest_dat + src_dat)); \
break; \
case 0x1c: \
dest_dat = MAX(0, (dest_dat - src_dat)) / 2; \
break; \
case 0x1d: \
dest_dat = MAX(0, (dest_dat - src_dat)) / 2; \
break; \
case 0x1e: \
dest_dat = MAX(0, (src_dat - dest_dat)) / 2; \
break; \
case 0x1f: \
dest_dat = (~0 < (src_dat + dest_dat)) ? ~0 : ((src_dat + dest_dat) >> 1); \
break; \
} \
}
#define WRITE(addr, dat) \
if (dev->bpp) { \
vram_w[((addr)) & (dev->vram_mask >> 1)] = dat; \
dev->changedvram[(((addr)) & (dev->vram_mask >> 1)) >> 11] = changeframecount; \
} else { \
dev->vram[((addr)) & (dev->vram_mask)] = dat; \
dev->changedvram[(((addr)) & (dev->vram_mask)) >> 12] = changeframecount; \
}
int ibm8514_active = 0;
int
ibm8514_cpu_src(svga_t *svga)
{
const ibm8514_t *dev = (ibm8514_t *) svga->dev8514;
if (!(dev->accel.cmd & 0x100))
return 0;
if (dev->accel.cmd & 1)
return 1;
return 0;
}
int
ibm8514_cpu_dest(svga_t *svga)
{
const ibm8514_t *dev = (ibm8514_t *) svga->dev8514;
if (!(dev->accel.cmd & 0x100))
return 0;
if (dev->accel.cmd & 1)
return 0;
return 1;
}
void
ibm8514_accel_out_pixtrans(svga_t *svga, UNUSED(uint16_t port), uint32_t val, int len)
{
ibm8514_t *dev = (ibm8514_t *) svga->dev8514;
uint8_t nibble = 0;
uint32_t pixelxfer = 0;
uint32_t monoxfer = 0xffffffff;
int pixcnt = 0;
int pixcntl = (dev->accel.multifunc[0x0a] >> 6) & 3;
int frgd_mix = (dev->accel.frgd_mix >> 5) & 3;
int bkgd_mix = (dev->accel.bkgd_mix >> 5) & 3;
int cmd = dev->accel.cmd >> 13;
int and3 = dev->accel.cur_x & 3;
if (dev->accel.cmd & 0x100) {
if (len != 1) {
/*Bus size*/
if (dev->accel.cmd & 0x200) /*16-bit*/
pixcnt = 16;
else /*8-bit*/
pixcnt = 8;
/*Pixel transfer data mode, can't be the same as Foreground/Background CPU data*/
if (pixcntl == 2) {
if ((frgd_mix == 2) || (bkgd_mix == 2)) {
pixelxfer = val;
} else {
if (dev->accel.cmd & 2) {
if (pixcnt == 16) {
if ((cmd >= 2) && (dev->accel.cmd & 0x1000))
val = (val >> 8) | (val << 8);
}
if (and3 == 3) {
if (dev->accel.cmd & 0x1000)
goto regular_nibble;
if (val & 0x02)
nibble |= 0x10;
if (val & 0x04)
nibble |= 0x08;
if (val & 0x08)
nibble |= 0x04;
if (val & 0x10)
nibble |= 0x02;
if (val & 0x200)
nibble |= 0x01;
if (val & 0x400)
nibble |= 0x80;
if (val & 0x800)
nibble |= 0x40;
if (val & 0x1000)
nibble |= 0x20;
} else if (and3 == 2) {
if (dev->accel.cmd & 0x1000)
goto regular_nibble;
if (val & 0x02)
nibble |= 0x20;
if (val & 0x04)
nibble |= 0x10;
if (val & 0x08)
nibble |= 0x08;
if (val & 0x10)
nibble |= 0x04;
if (val & 0x200)
nibble |= 0x02;
if (val & 0x400)
nibble |= 0x01;
if (val & 0x800)
nibble |= 0x80;
if (val & 0x1000)
nibble |= 0x40;
} else if (and3 == 1) {
if (dev->accel.cmd & 0x1000)
goto regular_nibble;
if (val & 0x02)
nibble |= 0x40;
if (val & 0x04)
nibble |= 0x20;
if (val & 0x08)
nibble |= 0x10;
if (val & 0x10)
nibble |= 0x08;
if (val & 0x200)
nibble |= 0x04;
if (val & 0x400)
nibble |= 0x02;
if (val & 0x800)
nibble |= 0x01;
if (val & 0x1000)
nibble |= 0x80;
} else {
regular_nibble:
if (val & 0x02)
nibble |= 0x80;
if (val & 0x04)
nibble |= 0x40;
if (val & 0x08)
nibble |= 0x20;
if (val & 0x10)
nibble |= 0x10;
if (val & 0x200)
nibble |= 0x08;
if (val & 0x400)
nibble |= 0x04;
if (val & 0x800)
nibble |= 0x02;
if (val & 0x1000)
nibble |= 0x01;
}
if ((and3 == 0) || (dev->accel.cmd & 0x1000) || ((dev->accel.cmd & 8) && ibm8514_cpu_src(svga))) {
if ((dev->accel.cmd & 8) && ibm8514_cpu_src(svga)) {
monoxfer = val;
} else
monoxfer = nibble;
ibm8514_accel_start(pixcnt, 1, monoxfer, pixelxfer, svga, len);
if (dev->accel.nibbleset != NULL) {
free(dev->accel.nibbleset);
dev->accel.nibbleset = NULL;
}
if (dev->accel.writemono != NULL) {
free(dev->accel.writemono);
dev->accel.writemono = NULL;
}
return;
}
dev->accel.writemono[dev->accel.x_count] = nibble;
if (val & 0x1c00) {
if (and3 == 1) {
if (val & 0x1000)
dev->accel.nibbleset[dev->accel.x_count] = 0x80;
else
dev->accel.nibbleset[dev->accel.x_count] = 0;
} else if (and3 == 2) {
if (val & 0x1000) {
if (val & 0x800)
dev->accel.nibbleset[dev->accel.x_count] = 0xc0;
else
dev->accel.nibbleset[dev->accel.x_count] = 0x40;
} else if (val & 0x800) {
if (val & 0x1000)
dev->accel.nibbleset[dev->accel.x_count] = 0xc0;
else
dev->accel.nibbleset[dev->accel.x_count] = 0x80;
} else
dev->accel.nibbleset[dev->accel.x_count] = 0;
} else if (and3 == 3) {
if (val & 0x1000) {
if (val & 0x800) {
if (val & 0x400)
dev->accel.nibbleset[dev->accel.x_count] = 0xe0;
else
dev->accel.nibbleset[dev->accel.x_count] = 0x60;
} else if (val & 0x400) {
if (val & 0x800)
dev->accel.nibbleset[dev->accel.x_count] = 0xe0;
else
dev->accel.nibbleset[dev->accel.x_count] = 0xa0;
} else
dev->accel.nibbleset[dev->accel.x_count] = 0x20;
} else if (val & 0x800) {
if (val & 0x400) {
if (val & 0x1000)
dev->accel.nibbleset[dev->accel.x_count] = 0xe0;
else
dev->accel.nibbleset[dev->accel.x_count] = 0xc0;
} else if (val & 0x1000) {
if (val & 0x400)
dev->accel.nibbleset[dev->accel.x_count] = 0xe0;
else
dev->accel.nibbleset[dev->accel.x_count] = 0x60;
} else
dev->accel.nibbleset[dev->accel.x_count] = 0x40;
} else if (val & 0x400) {
if (val & 0x800) {
if (val & 0x1000)
dev->accel.nibbleset[dev->accel.x_count] = 0xe0;
else
dev->accel.nibbleset[dev->accel.x_count] = 0xc0;
} else if (val & 0x1000) {
if (val & 0x800)
dev->accel.nibbleset[dev->accel.x_count] = 0xe0;
else
dev->accel.nibbleset[dev->accel.x_count] = 0xa0;
} else
dev->accel.nibbleset[dev->accel.x_count] = 0x80;
} else
dev->accel.nibbleset[dev->accel.x_count] = 0;
}
} else
dev->accel.nibbleset[dev->accel.x_count] = 0;
dev->accel.x_count++;
if (dev->accel.x_count == dev->accel.sys_cnt) {
for (int i = 0; i < dev->accel.x_count; i++) {
dev->accel.writemono[i] &= ~dev->accel.nibbleset[i];
dev->accel.writemono[i] |= dev->accel.nibbleset[i + 1];
ibm8514_accel_start(pixcnt, 1, dev->accel.writemono[i], pixelxfer, svga, len);
}
dev->accel.x_count = 0;
if (dev->accel.nibbleset != NULL) {
free(dev->accel.nibbleset);
dev->accel.nibbleset = NULL;
}
if (dev->accel.writemono != NULL) {
free(dev->accel.writemono);
dev->accel.writemono = NULL;
}
}
return;
}
monoxfer = val;
}
} else {
pixelxfer = val;
}
ibm8514_accel_start(pixcnt, 1, monoxfer, pixelxfer, svga, len);
}
}
}
void
ibm8514_accel_out_fifo(svga_t *svga, uint16_t port, uint32_t val, int len)
{
ibm8514_t *dev = (ibm8514_t *) svga->dev8514;
if (port != 0x9ae8 && port != 0xe2e8)
ibm8514_log("Port OUT FIFO=%04x, val=%04x, len=%d.\n", port, val, len);
switch (port) {
case 0x82e8:
case 0xc2e8:
if (len == 1)
dev->accel.cur_y = (dev->accel.cur_y & 0x700) | val;
else
dev->accel.cur_y = val & 0x7ff;
break;
case 0x82e9:
case 0xc2e9:
if (len == 1)
dev->accel.cur_y = (dev->accel.cur_y & 0xff) | ((val & 0x07) << 8);
break;
case 0x86e8:
case 0xc6e8:
if (len == 1)
dev->accel.cur_x = (dev->accel.cur_x & 0x700) | val;
else
dev->accel.cur_x = val & 0x7ff;
break;
case 0x86e9:
case 0xc6e9:
if (len == 1) {
dev->accel.cur_x = (dev->accel.cur_x & 0xff) | ((val & 0x07) << 8);
}
break;
case 0x8ae8:
case 0xcae8:
if (len == 1)
dev->accel.desty_axstp = (dev->accel.desty_axstp & 0x3f00) | val;
else {
dev->accel.desty = val & 0x07ff;
dev->accel.desty_axstp = val & 0x3fff;
if (val & 0x2000)
dev->accel.desty_axstp |= ~0x1fff;
}
break;
case 0x8ae9:
case 0xcae9:
if (len == 1) {
dev->accel.desty_axstp = (dev->accel.desty_axstp & 0xff) | ((val & 0x3f) << 8);
if (val & 0x20)
dev->accel.desty_axstp |= ~0x1fff;
}
break;
case 0x8ee8:
case 0xcee8:
if (len == 1)
dev->accel.destx_distp = (dev->accel.destx_distp & 0x3f00) | val;
else {
dev->accel.destx = val & 0x07ff;
dev->accel.destx_distp = val & 0x3fff;
if (val & 0x2000)
dev->accel.destx_distp |= ~0x1fff;
}
break;
case 0x8ee9:
case 0xcee9:
if (len == 1) {
dev->accel.destx_distp = (dev->accel.destx_distp & 0xff) | ((val & 0x3f) << 8);
if (val & 0x20)
dev->accel.destx_distp |= ~0x1fff;
}
break;
case 0x92e8:
if (len != 1)
dev->test = val;
fallthrough;
case 0xd2e8:
if (len == 1)
dev->accel.err_term = (dev->accel.err_term & 0x3f00) | val;
else {
dev->accel.err_term = val & 0x3fff;
if (val & 0x2000)
dev->accel.err_term |= ~0x1fff;
}
break;
case 0x92e9:
case 0xd2e9:
if (len == 1) {
dev->accel.err_term = (dev->accel.err_term & 0xff) | ((val & 0x3f) << 8);
if (val & 0x20)
dev->accel.err_term |= ~0x1fff;
}
break;
case 0x96e8:
case 0xd6e8:
if (len == 1)
dev->accel.maj_axis_pcnt = (dev->accel.maj_axis_pcnt & 0x700) | val;
else {
dev->accel.maj_axis_pcnt = val & 0x7ff;
dev->accel.maj_axis_pcnt_no_limit = val;
}
break;
case 0x96e9:
case 0xd6e9:
if (len == 1)
dev->accel.maj_axis_pcnt = (dev->accel.maj_axis_pcnt & 0xff) | ((val & 0x07) << 8);
break;
case 0x9ae8:
case 0xdae8:
dev->accel.ssv_state = 0;
if (len == 1)
dev->accel.cmd = (dev->accel.cmd & 0xff00) | val;
else {
dev->data_available = 0;
dev->data_available2 = 0;
dev->accel.cmd = val;
if (port == 0xdae8) {
if (dev->accel.cmd & 0x100)
dev->accel.cmd_back = 0;
}
ibm8514_log("8514/A CMD=%04x.\n", dev->accel.cmd);
ibm8514_accel_start(-1, 0, -1, 0, svga, len);
}
break;
case 0x9ae9:
case 0xdae9:
if (len == 1) {
dev->data_available = 0;
dev->data_available2 = 0;
dev->accel.cmd = (dev->accel.cmd & 0xff) | (val << 8);
if (port == 0xdae9) {
if (dev->accel.cmd & 0x100)
dev->accel.cmd_back = 0;
}
ibm8514_accel_start(-1, 0, -1, 0, svga, len);
}
break;
case 0x9ee8:
case 0xdee8:
dev->accel.ssv_state = 1;
if (len == 1)
dev->accel.short_stroke = (dev->accel.short_stroke & 0xff00) | val;
else {
dev->accel.short_stroke = val;
dev->accel.cx = dev->accel.cur_x;
dev->accel.cy = dev->accel.cur_y;
if (dev->accel.cur_x >= 0x600)
dev->accel.cx |= ~0x5ff;
if (dev->accel.cur_y >= 0x600)
dev->accel.cy |= ~0x5ff;
if (dev->accel.cmd & 0x1000) {
ibm8514_short_stroke_start(-1, 0, -1, 0, svga, dev->accel.short_stroke & 0xff, len);
ibm8514_short_stroke_start(-1, 0, -1, 0, svga, dev->accel.short_stroke >> 8, len);
} else {
ibm8514_short_stroke_start(-1, 0, -1, 0, svga, dev->accel.short_stroke >> 8, len);
ibm8514_short_stroke_start(-1, 0, -1, 0, svga, dev->accel.short_stroke & 0xff, len);
}
}
break;
case 0x9ee9:
case 0xdee9:
dev->accel.ssv_state = 1;
if (len == 1) {
dev->accel.short_stroke = (dev->accel.short_stroke & 0xff) | (val << 8);
dev->accel.cx = dev->accel.cur_x;
dev->accel.cy = dev->accel.cur_y;
if (dev->accel.cur_x >= 0x600)
dev->accel.cx |= ~0x5ff;
if (dev->accel.cur_y >= 0x600)
dev->accel.cy |= ~0x5ff;
if (dev->accel.cmd & 0x1000) {
ibm8514_short_stroke_start(-1, 0, -1, 0, svga, dev->accel.short_stroke & 0xff, len);
ibm8514_short_stroke_start(-1, 0, -1, 0, svga, dev->accel.short_stroke >> 8, len);
} else {
ibm8514_short_stroke_start(-1, 0, -1, 0, svga, dev->accel.short_stroke >> 8, len);
ibm8514_short_stroke_start(-1, 0, -1, 0, svga, dev->accel.short_stroke & 0xff, len);
}
}
break;
case 0xa2e8:
case 0xe2e8:
if (port == 0xe2e8) {
if (dev->accel.cmd_back) {
if (len == 1)
dev->accel.bkgd_color = (dev->accel.bkgd_color & 0x00ff) | val;
else
dev->accel.bkgd_color = val;
} else {
if (ibm8514_cpu_dest(svga))
break;
ibm8514_accel_out_pixtrans(svga, port, val, len);
}
} else {
if (len == 1)
dev->accel.bkgd_color = (dev->accel.bkgd_color & 0x00ff) | val;
else
dev->accel.bkgd_color = val;
}
break;
case 0xa2e9:
case 0xe2e9:
if (len == 1)
dev->accel.bkgd_color = (dev->accel.bkgd_color & 0xff00) | (val << 8);
break;
case 0xa6e8:
case 0xe6e8:
if (port == 0xe6e8) {
if (dev->accel.cmd_back) {
if (len == 1)
dev->accel.frgd_color = (dev->accel.frgd_color & 0x00ff) | val;
else
dev->accel.frgd_color = val;
} else {
if (ibm8514_cpu_dest(svga))
break;
ibm8514_accel_out_pixtrans(svga, port, val, len);
}
} else {
if (len == 1)
dev->accel.frgd_color = (dev->accel.frgd_color & 0x00ff) | val;
else
dev->accel.frgd_color = val;
}
break;
case 0xa6e9:
case 0xe6e9:
if (len == 1)
dev->accel.frgd_color = (dev->accel.frgd_color & 0xff00) | (val << 8);
break;
case 0xaae8:
case 0xeae8:
if (len == 1)
dev->accel.wrt_mask = (dev->accel.wrt_mask & 0x00ff) | val;
else
dev->accel.wrt_mask = val;
break;
case 0xaae9:
case 0xeae9:
if (len == 1)
dev->accel.wrt_mask = (dev->accel.wrt_mask & 0xff00) | (val << 8);
break;
case 0xaee8:
case 0xeee8:
if (len == 1)
dev->accel.rd_mask = (dev->accel.rd_mask & 0x00ff) | val;
else
dev->accel.rd_mask = val;
break;
case 0xaee9:
case 0xeee9:
if (len == 1)
dev->accel.rd_mask = (dev->accel.rd_mask & 0xff00) | (val << 8);
break;
case 0xb2e8:
case 0xf2e8:
if (len == 1)
dev->accel.color_cmp = (dev->accel.color_cmp & 0x00ff) | val;
else
dev->accel.color_cmp = val;
break;
case 0xb2e9:
case 0xf2e9:
if (len == 1)
dev->accel.color_cmp = (dev->accel.color_cmp & 0xff00) | (val << 8);
break;
case 0xb6e8:
case 0xf6e8:
dev->accel.bkgd_mix = val & 0xff;
break;
case 0xbae8:
case 0xfae8:
dev->accel.frgd_mix = val & 0xff;
break;
case 0xbee8:
case 0xfee8:
if (len == 1)
dev->accel.multifunc_cntl = (dev->accel.multifunc_cntl & 0xff00) | val;
else {
dev->accel.multifunc_cntl = val;
dev->accel.multifunc[dev->accel.multifunc_cntl >> 12] = dev->accel.multifunc_cntl & 0xfff;
if ((dev->accel.multifunc_cntl >> 12) == 1)
dev->accel.clip_top = val & 0x7ff;
if ((dev->accel.multifunc_cntl >> 12) == 2)
dev->accel.clip_left = val & 0x7ff;
if ((dev->accel.multifunc_cntl >> 12) == 3)
dev->accel.multifunc[3] = val & 0x7ff;
if ((dev->accel.multifunc_cntl >> 12) == 4)
dev->accel.multifunc[4] = val & 0x7ff;
ibm8514_log("CLIPBOTTOM=%d, CLIPRIGHT=%d, bpp=%d, pitch=%d.\n", dev->accel.multifunc[3], dev->accel.multifunc[4], dev->accel_bpp, dev->pitch);
if (port == 0xfee8)
dev->accel.cmd_back = 1;
else
dev->accel.cmd_back = 0;
}
break;
case 0xbee9:
case 0xfee9:
if (len == 1) {
dev->accel.multifunc_cntl = (dev->accel.multifunc_cntl & 0xff) | (val << 8);
dev->accel.multifunc[dev->accel.multifunc_cntl >> 12] = dev->accel.multifunc_cntl & 0xfff;
if ((dev->accel.multifunc_cntl >> 12) == 1)
dev->accel.clip_top = dev->accel.multifunc_cntl & 0x7ff;
if ((dev->accel.multifunc_cntl >> 12) == 2)
dev->accel.clip_left = dev->accel.multifunc_cntl & 0x7ff;
if (port == 0xfee9)
dev->accel.cmd_back = 1;
else
dev->accel.cmd_back = 0;
}
break;
default:
break;
}
}
void
ibm8514_ramdac_out(uint16_t port, uint8_t val, void *priv)
{
svga_t *svga = (svga_t *) priv;
svga_out(port, val, svga);
}
uint8_t
ibm8514_ramdac_in(uint16_t port, void *priv)
{
svga_t *svga = (svga_t *) priv;
uint8_t ret;
ret = svga_in(port, svga);
return ret;
}
static void
ibm8514_io_set(svga_t *svga)
{
io_sethandler(0x2e8, 0x0002, ibm8514_accel_inb, ibm8514_accel_inw, NULL, ibm8514_accel_outb, ibm8514_accel_outw, NULL, svga);
io_sethandler(0x2ea, 0x0004, ibm8514_ramdac_in, NULL, NULL, ibm8514_ramdac_out, NULL, NULL, svga);
io_sethandler(0x6e8, 0x0002, ibm8514_accel_inb, ibm8514_accel_inw, NULL, ibm8514_accel_outb, ibm8514_accel_outw, NULL, svga);
io_sethandler(0xae8, 0x0002, ibm8514_accel_inb, ibm8514_accel_inw, NULL, ibm8514_accel_outb, ibm8514_accel_outw, NULL, svga);
io_sethandler(0xee8, 0x0002, ibm8514_accel_inb, ibm8514_accel_inw, NULL, ibm8514_accel_outb, ibm8514_accel_outw, NULL, svga);
io_sethandler(0x12e8, 0x0002, ibm8514_accel_inb, ibm8514_accel_inw, NULL, ibm8514_accel_outb, ibm8514_accel_outw, NULL, svga);
io_sethandler(0x16e8, 0x0002, ibm8514_accel_inb, ibm8514_accel_inw, NULL, ibm8514_accel_outb, ibm8514_accel_outw, NULL, svga);
io_sethandler(0x1ae8, 0x0002, ibm8514_accel_inb, ibm8514_accel_inw, NULL, ibm8514_accel_outb, ibm8514_accel_outw, NULL, svga);
io_sethandler(0x1ee8, 0x0002, ibm8514_accel_inb, ibm8514_accel_inw, NULL, ibm8514_accel_outb, ibm8514_accel_outw, NULL, svga);
io_sethandler(0x22e8, 0x0002, ibm8514_accel_inb, ibm8514_accel_inw, NULL, ibm8514_accel_outb, ibm8514_accel_outw, NULL, svga);
io_sethandler(0x26e8, 0x0002, ibm8514_accel_inb, ibm8514_accel_inw, NULL, ibm8514_accel_outb, ibm8514_accel_outw, NULL, svga);
io_sethandler(0x2ee8, 0x0002, ibm8514_accel_inb, ibm8514_accel_inw, NULL, ibm8514_accel_outb, ibm8514_accel_outw, NULL, svga);
io_sethandler(0x42e8, 0x0002, ibm8514_accel_inb, ibm8514_accel_inw, NULL, ibm8514_accel_outb, ibm8514_accel_outw, NULL, svga);
io_sethandler(0x4ae8, 0x0002, ibm8514_accel_inb, ibm8514_accel_inw, NULL, ibm8514_accel_outb, ibm8514_accel_outw, NULL, svga);
io_sethandler(0x52e8, 0x0002, ibm8514_accel_inb, ibm8514_accel_inw, NULL, ibm8514_accel_outb, ibm8514_accel_outw, NULL, svga);
io_sethandler(0x56e8, 0x0002, ibm8514_accel_inb, ibm8514_accel_inw, NULL, ibm8514_accel_outb, ibm8514_accel_outw, NULL, svga);
io_sethandler(0x5ae8, 0x0002, ibm8514_accel_inb, ibm8514_accel_inw, NULL, ibm8514_accel_outb, ibm8514_accel_outw, NULL, svga);
io_sethandler(0x5ee8, 0x0002, ibm8514_accel_inb, ibm8514_accel_inw, NULL, ibm8514_accel_outb, ibm8514_accel_outw, NULL, svga);
io_sethandler(0x82e8, 0x0002, ibm8514_accel_inb, ibm8514_accel_inw, NULL, ibm8514_accel_outb, ibm8514_accel_outw, NULL, svga);
io_sethandler(0x86e8, 0x0002, ibm8514_accel_inb, ibm8514_accel_inw, NULL, ibm8514_accel_outb, ibm8514_accel_outw, NULL, svga);
io_sethandler(0x8ae8, 0x0002, ibm8514_accel_inb, ibm8514_accel_inw, NULL, ibm8514_accel_outb, ibm8514_accel_outw, NULL, svga);
io_sethandler(0x8ee8, 0x0002, ibm8514_accel_inb, ibm8514_accel_inw, NULL, ibm8514_accel_outb, ibm8514_accel_outw, NULL, svga);
io_sethandler(0x92e8, 0x0002, ibm8514_accel_inb, ibm8514_accel_inw, NULL, ibm8514_accel_outb, ibm8514_accel_outw, NULL, svga);
io_sethandler(0x96e8, 0x0002, ibm8514_accel_inb, ibm8514_accel_inw, NULL, ibm8514_accel_outb, ibm8514_accel_outw, NULL, svga);
io_sethandler(0x9ae8, 0x0002, ibm8514_accel_inb, ibm8514_accel_inw, NULL, ibm8514_accel_outb, ibm8514_accel_outw, NULL, svga);
io_sethandler(0x9ee8, 0x0002, ibm8514_accel_inb, ibm8514_accel_inw, NULL, ibm8514_accel_outb, ibm8514_accel_outw, NULL, svga);
io_sethandler(0xa2e8, 0x0002, ibm8514_accel_inb, ibm8514_accel_inw, NULL, ibm8514_accel_outb, ibm8514_accel_outw, NULL, svga);
io_sethandler(0xa6e8, 0x0002, ibm8514_accel_inb, ibm8514_accel_inw, NULL, ibm8514_accel_outb, ibm8514_accel_outw, NULL, svga);
io_sethandler(0xaae8, 0x0002, ibm8514_accel_inb, ibm8514_accel_inw, NULL, ibm8514_accel_outb, ibm8514_accel_outw, NULL, svga);
io_sethandler(0xaee8, 0x0002, ibm8514_accel_inb, ibm8514_accel_inw, NULL, ibm8514_accel_outb, ibm8514_accel_outw, NULL, svga);
io_sethandler(0xb2e8, 0x0002, ibm8514_accel_inb, ibm8514_accel_inw, NULL, ibm8514_accel_outb, ibm8514_accel_outw, NULL, svga);
io_sethandler(0xb6e8, 0x0002, ibm8514_accel_inb, ibm8514_accel_inw, NULL, ibm8514_accel_outb, ibm8514_accel_outw, NULL, svga);
io_sethandler(0xbae8, 0x0002, ibm8514_accel_inb, ibm8514_accel_inw, NULL, ibm8514_accel_outb, ibm8514_accel_outw, NULL, svga);
io_sethandler(0xbee8, 0x0002, ibm8514_accel_inb, ibm8514_accel_inw, NULL, ibm8514_accel_outb, ibm8514_accel_outw, NULL, svga);
io_sethandler(0xe2e8, 0x0002, ibm8514_accel_inb, ibm8514_accel_inw, NULL, ibm8514_accel_outb, ibm8514_accel_outw, NULL, svga);
io_sethandler(0xc2e8, 0x0002, ibm8514_accel_inb, ibm8514_accel_inw, NULL, ibm8514_accel_outb, ibm8514_accel_outw, NULL, svga);
io_sethandler(0xc6e8, 0x0002, ibm8514_accel_inb, ibm8514_accel_inw, NULL, ibm8514_accel_outb, ibm8514_accel_outw, NULL, svga);
io_sethandler(0xcae8, 0x0002, ibm8514_accel_inb, ibm8514_accel_inw, NULL, ibm8514_accel_outb, ibm8514_accel_outw, NULL, svga);
io_sethandler(0xcee8, 0x0002, ibm8514_accel_inb, ibm8514_accel_inw, NULL, ibm8514_accel_outb, ibm8514_accel_outw, NULL, svga);
io_sethandler(0xd2e8, 0x0002, ibm8514_accel_inb, ibm8514_accel_inw, NULL, ibm8514_accel_outb, ibm8514_accel_outw, NULL, svga);
io_sethandler(0xd6e8, 0x0002, ibm8514_accel_inb, ibm8514_accel_inw, NULL, ibm8514_accel_outb, ibm8514_accel_outw, NULL, svga);
io_sethandler(0xdae8, 0x0002, ibm8514_accel_inb, ibm8514_accel_inw, NULL, ibm8514_accel_outb, ibm8514_accel_outw, NULL, svga);
io_sethandler(0xdee8, 0x0002, ibm8514_accel_inb, ibm8514_accel_inw, NULL, ibm8514_accel_outb, ibm8514_accel_outw, NULL, svga);
io_sethandler(0xe6e8, 0x0002, ibm8514_accel_inb, ibm8514_accel_inw, NULL, ibm8514_accel_outb, ibm8514_accel_outw, NULL, svga);
io_sethandler(0xeae8, 0x0002, ibm8514_accel_inb, ibm8514_accel_inw, NULL, ibm8514_accel_outb, ibm8514_accel_outw, NULL, svga);
io_sethandler(0xeee8, 0x0002, ibm8514_accel_inb, ibm8514_accel_inw, NULL, ibm8514_accel_outb, ibm8514_accel_outw, NULL, svga);
io_sethandler(0xf2e8, 0x0002, ibm8514_accel_inb, ibm8514_accel_inw, NULL, ibm8514_accel_outb, ibm8514_accel_outw, NULL, svga);
io_sethandler(0xf6e8, 0x0002, ibm8514_accel_inb, ibm8514_accel_inw, NULL, ibm8514_accel_outb, ibm8514_accel_outw, NULL, svga);
io_sethandler(0xfae8, 0x0002, ibm8514_accel_inb, ibm8514_accel_inw, NULL, ibm8514_accel_outb, ibm8514_accel_outw, NULL, svga);
io_sethandler(0xfee8, 0x0002, ibm8514_accel_inb, ibm8514_accel_inw, NULL, ibm8514_accel_outb, ibm8514_accel_outw, NULL, svga);
}
void
ibm8514_accel_out(uint16_t port, uint32_t val, svga_t *svga, int len)
{
ibm8514_t *dev = (ibm8514_t *) svga->dev8514;
uint8_t old = 0;
if (port & 0x8000)
ibm8514_accel_out_fifo(svga, port, val, len);
else {
switch (port) {
case 0x2e8:
case 0x6e9:
WRITE8(port, dev->htotal, val);
ibm8514_log("IBM 8514/A compatible: (0x%04x): htotal=0x%02x.\n", port, val);
svga_recalctimings(svga);
break;
case 0x6e8:
/*In preparation to switch from VGA to 8514/A mode*/
if (!dev->on[0] || !dev->on[1]) {
dev->hdisped = val;
dev->hdisp = (dev->hdisped + 1) << 3;
}
ibm8514_log("[%04X:%08X]: IBM 8514/A: (0x%04x): hdisp=0x%02x.\n", CS, cpu_state.pc, port, val);
svga_recalctimings(svga);
break;
case 0xae8:
dev->hsync_start = val;
ibm8514_log("IBM 8514/A compatible: (0x%04x): val=0x%02x, hsync_start=%d.\n", port, val, (val + 1) << 3);
svga_recalctimings(svga);
break;
case 0xee8:
dev->hsync_width = val;
ibm8514_log("IBM 8514/A compatible: (0x%04x): val=0x%02x, hsync_width=%d, hsyncpol=%02x.\n", port, val & 0x1f, ((val & 0x1f) + 1) << 3, val & 0x20);
svga_recalctimings(svga);
break;
case 0x12e8:
case 0x12e9:
/*In preparation to switch from VGA to 8514/A mode*/
WRITE8(port, dev->v_total_reg, val);
dev->v_total_reg &= 0x1fff;
dev->v_total = dev->v_total_reg + 1;
if (dev->interlace)
dev->v_total >>= 1;
ibm8514_log("IBM 8514/A compatible: (0x%04x): vtotal=0x%02x.\n", port, val);
svga_recalctimings(svga);
break;
case 0x16e8:
case 0x16e9:
/*In preparation to switch from VGA to 8514/A mode*/
if (!dev->on[0] || !dev->on[1]) {
WRITE8(port, dev->v_disp, val);
dev->v_disp &= 0x1fff;
dev->vdisp = (dev->v_disp + 1) >> 1;
}
ibm8514_log("IBM 8514/A: V_DISP write 16E8 = %d\n", dev->v_disp);
ibm8514_log("IBM 8514/A: (0x%04x): vdisp=0x%02x.\n", port, val);
svga_recalctimings(svga);
break;
case 0x1ae8:
case 0x1ae9:
/*In preparation to switch from VGA to 8514/A mode*/
WRITE8(port, dev->v_sync_start, val);
dev->v_sync_start &= 0x1fff;
dev->v_syncstart = dev->v_sync_start + 1;
if (dev->interlace)
dev->v_syncstart >>= 1;
ibm8514_log("IBM 8514/A compatible: V_SYNCSTART write 1AE8 = %d\n", dev->v_syncstart);
ibm8514_log("IBM 8514/A compatible: (0x%04x): vsyncstart=0x%02x.\n", port, val);
svga_recalctimings(svga);
break;
case 0x1ee8:
case 0x1ee9:
ibm8514_log("IBM 8514/A compatible: V_SYNC_WID write 1EE8 = %02x\n", val);
ibm8514_log("IBM 8514/A compatible: (0x%04x): vsyncwidth=0x%02x.\n", port, val);
svga_recalctimings(svga);
break;
case 0x22e8:
dev->disp_cntl = val;
dev->interlace = !!(dev->disp_cntl & 0x10);
ibm8514_log("IBM 8514/A compatible: DISP_CNTL write %04x=%02x, interlace=%d.\n", port, dev->disp_cntl, dev->interlace);
svga_recalctimings(svga);
break;
case 0x42e8:
if (val & 1)
dev->subsys_stat &= ~1;
if (val & 2)
dev->subsys_stat &= ~2;
if (val & 4)
dev->subsys_stat &= ~4;
if (val & 8)
dev->subsys_stat &= ~8;
break;
case 0x42e9:
old = dev->subsys_cntl;
dev->subsys_cntl = val;
if ((old ^ val) & 1)
dev->subsys_stat |= 1;
if ((old ^ val) & 2)
dev->subsys_stat |= 2;
if ((old ^ val) & 4)
dev->subsys_stat |= 4;
if ((old ^ val) & 8)
dev->subsys_stat |= 8;
break;
case 0x4ae8:
case 0x4ae9:
WRITE8(port, dev->accel.advfunc_cntl, val);
dev->on[0] = dev->accel.advfunc_cntl & 0x01;
vga_on = !dev->on[0];
dev->vendor_mode[0] = 0;
ibm8514_log("[%04X:%08X]: IBM 8514/A: (0x%04x): ON=%d, shadow crt=%x, hdisp=%d, vdisp=%d.\n", CS, cpu_state.pc, port, dev->on[port & 1], dev->accel.advfunc_cntl & 0x04, dev->hdisp, dev->vdisp);
ibm8514_log("IBM mode set %s resolution.\n", (dev->accel.advfunc_cntl & 0x04) ? "2: 1024x768" : "1: 640x480");
svga_recalctimings(svga);
break;
default:
break;
}
}
}
static void
ibm8514_accel_outb(uint16_t port, uint8_t val, void *priv)
{
svga_t *svga = (svga_t *) priv;
ibm8514_accel_out(port, val, svga, 1);
}
static void
ibm8514_accel_outw(uint16_t port, uint16_t val, void *priv)
{
svga_t *svga = (svga_t *) priv;
ibm8514_accel_out(port, val, svga, 2);
}
uint16_t
ibm8514_accel_in_fifo(svga_t *svga, uint16_t port, int len)
{
ibm8514_t *dev = (ibm8514_t *) svga->dev8514;
uint16_t temp = 0;
int cmd = 0;
switch (port) {
case 0x82e8:
case 0xc2e8:
if (len != 1)
temp = dev->accel.cur_y;
break;
case 0x86e8:
case 0xc6e8:
if (len != 1)
temp = dev->accel.cur_x;
break;
case 0x92e8:
if (len != 1)
temp = dev->test;
break;
case 0x96e8:
if (len != 1)
temp = dev->accel.maj_axis_pcnt;
break;
case 0x9ae8:
case 0xdae8:
if (len != 1) {
if (dev->force_busy)
temp |= 0x200; /*Hardware busy*/
dev->force_busy = 0;
if (dev->data_available) {
temp |= 0x100; /*Read Data available*/
dev->data_available = 0;
}
}
break;
case 0x9ae9:
case 0xdae9:
if (len == 1) {
if (dev->force_busy2)
temp |= 2; /*Hardware busy*/
dev->force_busy2 = 0;
if (dev->data_available2) {
temp |= 1; /*Read Data available*/
dev->data_available2 = 0;
}
}
break;
case 0xe2e8:
case 0xe6e8:
if (ibm8514_cpu_dest(svga)) {
if (len != 1) {
cmd = (dev->accel.cmd >> 13);
READ_PIXTRANS_WORD(dev->accel.cx, 0);
if (dev->accel.input && !dev->accel.odd_in && !dev->accel.sx) {
temp &= ~0xff00;
temp |= (dev->vram[(dev->accel.newdest_in + dev->accel.cur_x) & dev->vram_mask] << 8);
}
ibm8514_accel_out_pixtrans(svga, port, temp, len);
}
}
break;
default:
break;
}
return temp;
}
uint8_t
ibm8514_accel_in(uint16_t port, svga_t *svga)
{
ibm8514_t *dev = (ibm8514_t *) svga->dev8514;
uint8_t temp = 0;
uint16_t clip_b_ibm = dev->accel.multifunc[3];
uint16_t clip_r_ibm = dev->accel.multifunc[4];
int cmd = (dev->accel.cmd >> 13);
switch (port) {
case 0x2e8:
if (dev->vc == dev->v_syncstart)
temp |= 2;
ibm8514_log("0x2E8 read: Display Status=%02x.\n", temp);
break;
case 0x6e8:
temp = dev->hdisped;
break;
case 0x22e8:
temp = dev->disp_cntl;
break;
case 0x26e8:
case 0x26e9:
READ8(port, dev->htotal);
break;
case 0x2ee8:
temp = dev->subsys_cntl;
break;
case 0x2ee9:
temp = 0xff;
break;
case 0x42e8:
case 0x42e9:
if (dev->vc == dev->v_syncstart)
dev->subsys_stat |= 1;
if (cmd == 6) {
if (((dev->accel.dx) >= dev->accel.clip_left) && ((dev->accel.dx) <= clip_r_ibm) && ((dev->accel.dy) >= dev->accel.clip_top) && ((dev->accel.dy) <= clip_b_ibm))
temp |= 2;
} else {
if (((dev->accel.cx) >= dev->accel.clip_left) && ((dev->accel.dx) <= clip_r_ibm) && ((dev->accel.cy) >= dev->accel.clip_top) && ((dev->accel.cy) <= clip_b_ibm))
temp |= 2;
}
if (!dev->force_busy)
temp |= 8;
if (port & 1)
temp = 0x80;
else {
temp |= (dev->subsys_stat | 0x80);
temp |= 0x20;
}
break;
default:
break;
}
return temp;
}
static uint8_t
ibm8514_accel_inb(uint16_t port, void *priv)
{
svga_t *svga = (svga_t *) priv;
uint8_t temp;
if (port & 0x8000)
temp = ibm8514_accel_in_fifo(svga, port, 1);
else
temp = ibm8514_accel_in(port, svga);
return temp;
}
static uint16_t
ibm8514_accel_inw(uint16_t port, void *priv)
{
svga_t *svga = (svga_t *) priv;
uint16_t temp;
if (port & 0x8000)
temp = ibm8514_accel_in_fifo(svga, port, 2);
else {
temp = ibm8514_accel_in(port, svga);
temp |= (ibm8514_accel_in(port + 1, svga) << 8);
}
return temp;
}
void
ibm8514_short_stroke_start(int count, int cpu_input, uint32_t mix_dat, uint32_t cpu_dat, svga_t *svga, uint8_t ssv, int len)
{
ibm8514_t *dev = (ibm8514_t *) svga->dev8514;
if (!cpu_input) {
dev->accel.ssv_len = ssv & 0x0f;
dev->accel.ssv_dir = ssv & 0xe0;
dev->accel.ssv_draw = ssv & 0x10;
if (ibm8514_cpu_src(svga)) {
return; /*Wait for data from CPU*/
}
}
ibm8514_accel_start(count, cpu_input, mix_dat, cpu_dat, svga, len);
}
void
ibm8514_accel_start(int count, int cpu_input, uint32_t mix_dat, uint32_t cpu_dat, svga_t *svga, UNUSED(int len))
{
ibm8514_t *dev = (ibm8514_t *) svga->dev8514;
uint16_t *vram_w = (uint16_t *) dev->vram;
uint16_t src_dat = 0;
uint16_t dest_dat;
uint16_t old_dest_dat;
int frgd_mix;
int bkgd_mix;
uint16_t clip_b = dev->accel.multifunc[3];
uint16_t clip_r = dev->accel.multifunc[4];
int pixcntl = (dev->accel.multifunc[0x0a] >> 6) & 3;
uint16_t mix_mask = dev->bpp ? 0x8000 : 0x80;
uint16_t compare = dev->accel.color_cmp;
int compare_mode = dev->accel.multifunc[0x0a] & 0x38;
int cmd = dev->accel.cmd >> 13;
uint16_t wrt_mask = dev->accel.wrt_mask;
uint16_t rd_mask = dev->accel.rd_mask;
uint16_t rd_mask_polygon = dev->accel.rd_mask;
uint16_t frgd_color = dev->accel.frgd_color;
uint16_t bkgd_color = dev->accel.bkgd_color;
uint32_t old_mix_dat;
int and3 = dev->accel.cur_x & 3;
if (!dev->bpp) {
compare &= 0xff;
frgd_color &= 0xff;
bkgd_color &= 0xff;
rd_mask = ((dev->accel.rd_mask & 0x01) << 7) | ((dev->accel.rd_mask & 0xfe) >> 1);
rd_mask &= 0xff;
rd_mask_polygon &= 0xff;
}
if (dev->accel.cmd & 0x100) {
dev->force_busy = 1;
dev->force_busy2 = 1;
}
frgd_mix = (dev->accel.frgd_mix >> 5) & 3;
bkgd_mix = (dev->accel.bkgd_mix >> 5) & 3;
if (cpu_input) {
if ((dev->accel.cmd & 2) || (pixcntl == 2)) {
if ((frgd_mix == 2) || (bkgd_mix == 2))
count >>= 3;
else if (pixcntl == 2) {
if (dev->accel.cmd & 2)
count >>= 1;
else
count >>= 3;
}
} else
count >>= 3;
if (dev->bpp) {
if ((dev->accel.cmd & 0x200) && (count == 2))
count >>= 1;
}
}
if (pixcntl == 1) {
mix_dat = 0;
if (and3 == 3) {
if (dev->accel.multifunc[8] & 0x02)
mix_dat |= 0x08;
if (dev->accel.multifunc[8] & 0x04)
mix_dat |= 0x10;
if (dev->accel.multifunc[8] & 0x08)
mix_dat |= 0x20;
if (dev->accel.multifunc[8] & 0x10)
mix_dat |= 0x40;
if (dev->accel.multifunc[9] & 0x02)
mix_dat |= 0x80;
if (dev->accel.multifunc[9] & 0x04)
mix_dat |= 0x01;
if (dev->accel.multifunc[9] & 0x08)
mix_dat |= 0x02;
if (dev->accel.multifunc[9] & 0x10)
mix_dat |= 0x04;
}
if (and3 == 2) {
if (dev->accel.multifunc[8] & 0x02)
mix_dat |= 0x04;
if (dev->accel.multifunc[8] & 0x04)
mix_dat |= 0x08;
if (dev->accel.multifunc[8] & 0x08)
mix_dat |= 0x10;
if (dev->accel.multifunc[8] & 0x10)
mix_dat |= 0x20;
if (dev->accel.multifunc[9] & 0x02)
mix_dat |= 0x40;
if (dev->accel.multifunc[9] & 0x04)
mix_dat |= 0x80;
if (dev->accel.multifunc[9] & 0x08)
mix_dat |= 0x01;
if (dev->accel.multifunc[9] & 0x10)
mix_dat |= 0x02;
}
if (and3 == 1) {
if (dev->accel.multifunc[8] & 0x02)
mix_dat |= 0x02;
if (dev->accel.multifunc[8] & 0x04)
mix_dat |= 0x04;
if (dev->accel.multifunc[8] & 0x08)
mix_dat |= 0x08;
if (dev->accel.multifunc[8] & 0x10)
mix_dat |= 0x10;
if (dev->accel.multifunc[9] & 0x02)
mix_dat |= 0x20;
if (dev->accel.multifunc[9] & 0x04)
mix_dat |= 0x40;
if (dev->accel.multifunc[9] & 0x08)
mix_dat |= 0x80;
if (dev->accel.multifunc[9] & 0x10)
mix_dat |= 0x01;
}
if (and3 == 0) {
if (dev->accel.multifunc[8] & 0x02)
mix_dat |= 0x01;
if (dev->accel.multifunc[8] & 0x04)
mix_dat |= 0x02;
if (dev->accel.multifunc[8] & 0x08)
mix_dat |= 0x04;
if (dev->accel.multifunc[8] & 0x10)
mix_dat |= 0x08;
if (dev->accel.multifunc[9] & 0x02)
mix_dat |= 0x10;
if (dev->accel.multifunc[9] & 0x04)
mix_dat |= 0x20;
if (dev->accel.multifunc[9] & 0x08)
mix_dat |= 0x40;
if (dev->accel.multifunc[9] & 0x10)
mix_dat |= 0x80;
}
}
old_mix_dat = mix_dat;
/*Bit 4 of the Command register is the draw yes bit, which enables writing to memory/reading from memory when enabled.
When this bit is disabled, no writing to memory/reading from memory is allowed. (This bit is almost meaningless on
the NOP command)*/
switch (cmd) {
case 0: /*NOP (Short Stroke Vectors)*/
if (dev->accel.ssv_state == 0)
break;
if (dev->accel.cmd & 8) {
while (count-- && dev->accel.ssv_len >= 0) {
if (dev->accel.cx >= dev->accel.clip_left && dev->accel.cx <= clip_r && dev->accel.cy >= dev->accel.clip_top && dev->accel.cy <= clip_b) {
switch ((mix_dat & mix_mask) ? frgd_mix : bkgd_mix) {
case 0:
src_dat = bkgd_color;
break;
case 1:
src_dat = frgd_color;
break;
case 2:
src_dat = cpu_dat;
break;
case 3:
src_dat = 0;
break;
default:
break;
}
READ((dev->accel.cy * dev->pitch) + dev->accel.cx, dest_dat);
if ((compare_mode == 0) || ((compare_mode == 0x10) && (dest_dat >= compare)) || ((compare_mode == 0x18) && (dest_dat < compare)) || ((compare_mode == 0x20) && (dest_dat != compare)) || ((compare_mode == 0x28) && (dest_dat == compare)) || ((compare_mode == 0x30) && (dest_dat <= compare)) || ((compare_mode == 0x38) && (dest_dat > compare))) {
old_dest_dat = dest_dat;
MIX(mix_dat & mix_mask, dest_dat, src_dat);
dest_dat = (dest_dat & wrt_mask) | (old_dest_dat & ~wrt_mask);
if (dev->accel.ssv_draw) {
if ((dev->accel.cmd & 4) && dev->accel.ssv_len) {
WRITE((dev->accel.cy * dev->pitch) + dev->accel.cx, dest_dat);
} else if (!(dev->accel.cmd & 4)) {
WRITE((dev->accel.cy * dev->pitch) + dev->accel.cx, dest_dat);
}
}
}
}
mix_dat <<= 1;
mix_dat |= 1;
if (dev->bpp)
cpu_dat >>= 16;
else
cpu_dat >>= 8;
if (!dev->accel.ssv_len)
break;
switch (dev->accel.ssv_dir & 0xe0) {
case 0x00:
dev->accel.cx++;
break;
case 0x20:
dev->accel.cx++;
dev->accel.cy--;
break;
case 0x40:
dev->accel.cy--;
break;
case 0x60:
dev->accel.cx--;
dev->accel.cy--;
break;
case 0x80:
dev->accel.cx--;
break;
case 0xa0:
dev->accel.cx--;
dev->accel.cy++;
break;
case 0xc0:
dev->accel.cy++;
break;
case 0xe0:
dev->accel.cx++;
dev->accel.cy++;
break;
default:
break;
}
dev->accel.ssv_len--;
}
} else {
while (count-- && (dev->accel.ssv_len >= 0)) {
if ((dev->accel.cx >= dev->accel.clip_left) && (dev->accel.cx <= clip_r) &&
(dev->accel.cy >= dev->accel.clip_top) && (dev->accel.cy <= clip_b)) {
switch ((mix_dat & mix_mask) ? frgd_mix : bkgd_mix) {
case 0:
src_dat = bkgd_color;
break;
case 1:
src_dat = frgd_color;
break;
case 2:
src_dat = cpu_dat;
break;
case 3:
src_dat = 0;
break;
default:
break;
}
READ((dev->accel.cy * dev->pitch) + dev->accel.cx, dest_dat);
if ((compare_mode == 0) || ((compare_mode == 0x10) && (dest_dat >= compare)) || ((compare_mode == 0x18) && (dest_dat < compare)) || ((compare_mode == 0x20) && (dest_dat != compare)) || ((compare_mode == 0x28) && (dest_dat == compare)) || ((compare_mode == 0x30) && (dest_dat <= compare)) || ((compare_mode == 0x38) && (dest_dat > compare))) {
old_dest_dat = dest_dat;
MIX(mix_dat & mix_mask, dest_dat, src_dat);
dest_dat = (dest_dat & wrt_mask) | (old_dest_dat & ~wrt_mask);
if (dev->accel.ssv_draw) {
if ((dev->accel.cmd & 4) && dev->accel.ssv_len) {
WRITE((dev->accel.cy * dev->pitch) + dev->accel.cx, dest_dat);
} else if (!(dev->accel.cmd & 4)) {
WRITE((dev->accel.cy * dev->pitch) + dev->accel.cx, dest_dat);
}
}
}
}
mix_dat <<= 1;
mix_dat |= 1;
if (dev->bpp)
cpu_dat >>= 16;
else
cpu_dat >>= 8;
if (!dev->accel.ssv_len)
break;
if (dev->accel.err_term >= dev->accel.maj_axis_pcnt) {
dev->accel.err_term += dev->accel.destx_distp;
/*Step minor axis*/
switch (dev->accel.cmd & 0xe0) {
case 0x00:
dev->accel.cy--;
break;
case 0x20:
dev->accel.cy--;
break;
case 0x40:
dev->accel.cx--;
break;
case 0x60:
dev->accel.cx++;
break;
case 0x80:
dev->accel.cy++;
break;
case 0xa0:
dev->accel.cy++;
break;
case 0xc0:
dev->accel.cx--;
break;
case 0xe0:
dev->accel.cx++;
break;
default:
break;
}
} else
dev->accel.err_term += dev->accel.desty_axstp;
/*Step major axis*/
switch (dev->accel.cmd & 0xe0) {
case 0x00:
dev->accel.cx--;
break;
case 0x20:
dev->accel.cx++;
break;
case 0x40:
dev->accel.cy--;
break;
case 0x60:
dev->accel.cy--;
break;
case 0x80:
dev->accel.cx--;
break;
case 0xa0:
dev->accel.cx++;
break;
case 0xc0:
dev->accel.cy++;
break;
case 0xe0:
dev->accel.cy++;
break;
default:
break;
}
dev->accel.ssv_len--;
}
}
dev->accel.cur_x = dev->accel.cx;
dev->accel.cur_y = dev->accel.cy;
break;
case 1: /*Draw line*/
if (!cpu_input) {
dev->accel.xx_count = 0;
dev->accel.cx = dev->accel.cur_x;
dev->accel.cy = dev->accel.cur_y;
if (dev->accel.cur_x >= 0x600)
dev->accel.cx |= ~0x5ff;
if (dev->accel.cur_y >= 0x600)
dev->accel.cy |= ~0x5ff;
dev->accel.sy = dev->accel.maj_axis_pcnt;
ibm8514_log("Line Draw 8514/A, frgdmix=%d, bkgdmix=%d, c(%d,%d), pixcntl=%d, sy=%d, polyfill=%x, selfrmix=%02x, selbkmix=%02x, bkgdcol=%02x, frgdcol=%02x, clipt=%d, clipb=%d.\n", frgd_mix, bkgd_mix, dev->accel.cx, dev->accel.cy, pixcntl, dev->accel.sy, dev->accel.multifunc[0x0a] & 6, dev->accel.frgd_mix & 0x1f, dev->accel.bkgd_mix & 0x1f, bkgd_color, frgd_color, dev->accel.clip_top, clip_b);
if (ibm8514_cpu_src(svga)) {
if (dev->accel.cmd & 2) {
if (dev->accel.cmd & 8) {
if (and3 == 1) {
dev->accel.sy += 4;
if (dev->accel.cmd & 0x20)
dev->accel.cx += 4;
else
dev->accel.cx -= 4;
} else if (and3 == 2) {
dev->accel.sy += 5;
if (dev->accel.cmd & 0x20)
dev->accel.cx += 5;
else
dev->accel.cx -= 5;
} else if (and3 == 3) {
dev->accel.sy += 6;
if (dev->accel.cmd & 0x20)
dev->accel.cx += 6;
else
dev->accel.cx -= 6;
} else {
dev->accel.sy += 3;
if (dev->accel.cmd & 0x20)
dev->accel.cx += 3;
else
dev->accel.cx -= 3;
}
}
}
dev->data_available = 0;
dev->data_available2 = 0;
return; /*Wait for data from CPU*/
} else if (ibm8514_cpu_dest(svga)) {
dev->data_available = 1;
dev->data_available2 = 1;
return;
}
}
if (dev->accel.cmd & 8) { /*Vector Line*/
if (ibm8514_cpu_dest(svga) && cpu_input && (dev->accel.cmd & 2))
count >>= 1;
dev->accel.xx_count++;
while (count-- && (dev->accel.sy >= 0)) {
if (dev->accel.cx >= dev->accel.clip_left && dev->accel.cx <= clip_r && dev->accel.cy >= dev->accel.clip_top && dev->accel.cy <= clip_b) {
if (ibm8514_cpu_dest(svga) && (pixcntl == 0)) {
mix_dat = mix_mask; /* Mix data = forced to foreground register. */
} else if (ibm8514_cpu_dest(svga) && (pixcntl == 3)) {
/* Mix data = current video memory value. */
READ((dev->accel.cy * dev->pitch) + dev->accel.cx, mix_dat);
mix_dat = ((mix_dat & rd_mask) == rd_mask);
mix_dat = mix_dat ? mix_mask : 0;
}
if (ibm8514_cpu_dest(svga)) {
READ((dev->accel.cy * dev->pitch) + dev->accel.cx, src_dat);
if (pixcntl == 3)
src_dat = ((src_dat & rd_mask) == rd_mask);
} else {
switch ((mix_dat & mix_mask) ? frgd_mix : bkgd_mix) {
case 0:
src_dat = bkgd_color;
break;
case 1:
src_dat = frgd_color;
break;
case 2:
src_dat = cpu_dat;
break;
case 3:
src_dat = 0;
break;
default:
break;
}
}
READ((dev->accel.cy * dev->pitch) + dev->accel.cx, dest_dat);
if ((compare_mode == 0) || ((compare_mode == 0x10) && (dest_dat >= compare)) || ((compare_mode == 0x18) && (dest_dat < compare)) || ((compare_mode == 0x20) && (dest_dat != compare)) || ((compare_mode == 0x28) && (dest_dat == compare)) || ((compare_mode == 0x30) && (dest_dat <= compare)) || ((compare_mode == 0x38) && (dest_dat > compare))) {
old_dest_dat = dest_dat;
MIX(mix_dat & mix_mask, dest_dat, src_dat);
dest_dat = (dest_dat & wrt_mask) | (old_dest_dat & ~wrt_mask);
if ((dev->accel.cmd & 2) && ibm8514_cpu_src(svga)) {
if (and3 == 1) {
if (dev->accel.xx_count >= 2) {
if ((dev->accel.cmd & 4) && dev->accel.sy) {
WRITE((dev->accel.cy * dev->pitch) + dev->accel.cx, dest_dat);
} else if (!(dev->accel.cmd & 4)) {
WRITE((dev->accel.cy * dev->pitch) + dev->accel.cx, dest_dat);
}
}
} else if (and3 == 2) {
if (dev->accel.xx_count == 2) {
if (count <= 2) {
if ((dev->accel.cmd & 4) && dev->accel.sy) {
WRITE((dev->accel.cy * dev->pitch) + dev->accel.cx, dest_dat);
} else if (!(dev->accel.cmd & 4)) {
WRITE((dev->accel.cy * dev->pitch) + dev->accel.cx, dest_dat);
}
}
} else if (dev->accel.xx_count >= 3) {
if ((dev->accel.cmd & 4) && dev->accel.sy) {
WRITE((dev->accel.cy * dev->pitch) + dev->accel.cx, dest_dat);
} else if (!(dev->accel.cmd & 4)) {
WRITE((dev->accel.cy * dev->pitch) + dev->accel.cx, dest_dat);
}
}
} else if (and3 == 3) {
if (dev->accel.xx_count == 2) {
if (count <= 1) {
if ((dev->accel.cmd & 4) && dev->accel.sy) {
WRITE((dev->accel.cy * dev->pitch) + dev->accel.cx, dest_dat);
} else if (!(dev->accel.cmd & 4)) {
WRITE((dev->accel.cy * dev->pitch) + dev->accel.cx, dest_dat);
}
}
} else if (dev->accel.xx_count >= 3) {
if ((dev->accel.cmd & 4) && dev->accel.sy) {
WRITE((dev->accel.cy * dev->pitch) + dev->accel.cx, dest_dat);
} else if (!(dev->accel.cmd & 4)) {
WRITE((dev->accel.cy * dev->pitch) + dev->accel.cx, dest_dat);
}
}
} else {
if (dev->accel.xx_count == 1) {
if (!count) {
if ((dev->accel.cmd & 4) && dev->accel.sy) {
WRITE((dev->accel.cy * dev->pitch) + dev->accel.cx, dest_dat);
} else if (!(dev->accel.cmd & 4)) {
WRITE((dev->accel.cy * dev->pitch) + dev->accel.cx, dest_dat);
}
}
} else if (dev->accel.xx_count >= 2) {
if ((dev->accel.cmd & 4) && dev->accel.sy) {
WRITE((dev->accel.cy * dev->pitch) + dev->accel.cx, dest_dat);
} else if (!(dev->accel.cmd & 4)) {
WRITE((dev->accel.cy * dev->pitch) + dev->accel.cx, dest_dat);
}
}
}
} else {
if (ibm8514_cpu_src(svga) || !cpu_input) {
if ((dev->accel.cmd & 4) && dev->accel.sy) {
WRITE((dev->accel.cy * dev->pitch) + dev->accel.cx, dest_dat);
} else if (!(dev->accel.cmd & 4)) {
WRITE((dev->accel.cy * dev->pitch) + dev->accel.cx, dest_dat);
}
}
}
}
}
mix_dat <<= 1;
mix_dat |= 1;
if (dev->bpp)
cpu_dat >>= 16;
else
cpu_dat >>= 8;
if (dev->accel.sy == 0) {
break;
}
switch (dev->accel.cmd & 0xe0) {
case 0x00:
dev->accel.cx++;
break;
case 0x20:
dev->accel.cx++;
dev->accel.cy--;
break;
case 0x40:
dev->accel.cy--;
break;
case 0x60:
dev->accel.cx--;
dev->accel.cy--;
break;
case 0x80:
dev->accel.cx--;
break;
case 0xa0:
dev->accel.cx--;
dev->accel.cy++;
break;
case 0xc0:
dev->accel.cy++;
break;
case 0xe0:
dev->accel.cx++;
dev->accel.cy++;
break;
default:
break;
}
dev->accel.sy--;
}
dev->accel.cur_x = dev->accel.cx;
dev->accel.cur_y = dev->accel.cy;
} else { /*Bresenham*/
if (pixcntl == 1) {
dev->accel.temp_cnt = 8;
while (count-- && (dev->accel.sy >= 0)) {
if (dev->accel.temp_cnt == 0) {
dev->accel.temp_cnt = 8;
mix_dat = old_mix_dat;
}
if (dev->accel.cx >= dev->accel.clip_left && dev->accel.cx <= clip_r && dev->accel.cy >= dev->accel.clip_top && dev->accel.cy <= clip_b) {
if (ibm8514_cpu_dest(svga)) {
READ((dev->accel.cy * dev->pitch) + dev->accel.cx, src_dat);
} else
switch ((mix_dat & 1) ? frgd_mix : bkgd_mix) {
case 0:
src_dat = bkgd_color;
break;
case 1:
src_dat = frgd_color;
break;
case 2:
src_dat = cpu_dat;
break;
case 3:
src_dat = 0;
break;
default:
break;
}
READ((dev->accel.cy * dev->pitch) + dev->accel.cx, dest_dat);
if ((compare_mode == 0) || ((compare_mode == 0x10) && (dest_dat >= compare)) || ((compare_mode == 0x18) && (dest_dat < compare)) || ((compare_mode == 0x20) && (dest_dat != compare)) || ((compare_mode == 0x28) && (dest_dat == compare)) || ((compare_mode == 0x30) && (dest_dat <= compare)) || ((compare_mode == 0x38) && (dest_dat > compare))) {
old_dest_dat = dest_dat;
MIX(mix_dat & 1, dest_dat, src_dat);
dest_dat = (dest_dat & wrt_mask) | (old_dest_dat & ~wrt_mask);
if ((dev->accel.cmd & 4) && dev->accel.sy) {
WRITE((dev->accel.cy * dev->pitch) + dev->accel.cx, dest_dat);
} else if (!(dev->accel.cmd & 4)) {
WRITE((dev->accel.cy * dev->pitch) + dev->accel.cx, dest_dat);
}
}
}
dev->accel.temp_cnt--;
mix_dat >>= 1;
if (dev->bpp)
cpu_dat >>= 16;
else
cpu_dat >>= 8;
if (dev->accel.sy == 0) {
break;
}
if (dev->accel.cmd & 0x40) {
if (dev->accel.cmd & 0x80)
dev->accel.cy++;
else
dev->accel.cy--;
if (dev->accel.err_term >= 0) {
dev->accel.err_term += dev->accel.destx_distp;
if (dev->accel.cmd & 0x20)
dev->accel.cx++;
else
dev->accel.cx--;
} else
dev->accel.err_term += dev->accel.desty_axstp;
} else {
if (dev->accel.cmd & 0x20)
dev->accel.cx++;
else
dev->accel.cx--;
if (dev->accel.err_term >= 0) {
dev->accel.err_term += dev->accel.destx_distp;
if (dev->accel.cmd & 0x80)
dev->accel.cy++;
else
dev->accel.cy--;
} else
dev->accel.err_term += dev->accel.desty_axstp;
}
dev->accel.sy--;
}
} else {
while (count-- && (dev->accel.sy >= 0)) {
if ((dev->accel.cx) >= dev->accel.clip_left && (dev->accel.cx) <= clip_r && (dev->accel.cy) >= dev->accel.clip_top && (dev->accel.cy) <= clip_b) {
if (ibm8514_cpu_dest(svga) && (pixcntl == 0)) {
mix_dat = mix_mask; /* Mix data = forced to foreground register. */
} else if (ibm8514_cpu_dest(svga) && (pixcntl == 3)) {
/* Mix data = current video memory value. */
READ((dev->accel.cy * dev->pitch) + dev->accel.cx, mix_dat);
mix_dat = ((mix_dat & rd_mask) == rd_mask);
mix_dat = mix_dat ? mix_mask : 0;
}
if (ibm8514_cpu_dest(svga)) {
READ((dev->accel.cy * dev->pitch) + dev->accel.cx, src_dat);
if (pixcntl == 3)
src_dat = ((src_dat & rd_mask) == rd_mask);
} else
switch ((mix_dat & mix_mask) ? frgd_mix : bkgd_mix) {
case 0:
src_dat = bkgd_color;
break;
case 1:
src_dat = frgd_color;
break;
case 2:
src_dat = cpu_dat;
break;
case 3:
src_dat = 0;
break;
default:
break;
}
READ((dev->accel.cy * dev->pitch) + dev->accel.cx, dest_dat);
if ((compare_mode == 0) || ((compare_mode == 0x10) && (dest_dat >= compare)) || ((compare_mode == 0x18) && (dest_dat < compare)) || ((compare_mode == 0x20) && (dest_dat != compare)) || ((compare_mode == 0x28) && (dest_dat == compare)) || ((compare_mode == 0x30) && (dest_dat <= compare)) || ((compare_mode == 0x38) && (dest_dat > compare))) {
old_dest_dat = dest_dat;
MIX(mix_dat & mix_mask, dest_dat, src_dat);
dest_dat = (dest_dat & wrt_mask) | (old_dest_dat & ~wrt_mask);
if ((dev->accel.cmd & 4) && dev->accel.sy) {
WRITE((dev->accel.cy * dev->pitch) + dev->accel.cx, dest_dat);
} else if (!(dev->accel.cmd & 4)) {
WRITE((dev->accel.cy * dev->pitch) + dev->accel.cx, dest_dat);
}
}
}
mix_dat <<= 1;
mix_dat |= 1;
if (dev->bpp)
cpu_dat >>= 16;
else
cpu_dat >>= 8;
if (dev->accel.sy == 0)
break;
if (dev->accel.cmd & 0x40) {
if (dev->accel.cmd & 0x80)
dev->accel.cy++;
else
dev->accel.cy--;
if (dev->accel.err_term >= 0) {
dev->accel.err_term += dev->accel.destx_distp;
if (dev->accel.cmd & 0x20)
dev->accel.cx++;
else
dev->accel.cx--;
} else
dev->accel.err_term += dev->accel.desty_axstp;
} else {
if (dev->accel.cmd & 0x20)
dev->accel.cx++;
else
dev->accel.cx--;
if (dev->accel.err_term >= 0) {
dev->accel.err_term += dev->accel.destx_distp;
if (dev->accel.cmd & 0x80)
dev->accel.cy++;
else
dev->accel.cy--;
} else
dev->accel.err_term += dev->accel.desty_axstp;
}
dev->accel.sy--;
}
}
dev->accel.cur_x = dev->accel.cx;
dev->accel.cur_y = dev->accel.cy;
}
break;
case 2: /*Rectangle fill (X direction)*/
case 3: /*Rectangle fill (Y direction)*/
case 4: /*Rectangle fill (Y direction using nibbles)*/
if (!cpu_input) {
dev->accel.x_count = 0;
dev->accel.xx_count = 0;
dev->accel.odd_out = 0;
dev->accel.odd_in = 0;
dev->accel.input = 0;
dev->accel.output = 0;
dev->accel.newdest_out = 0;
dev->accel.newdest_in = 0;
dev->accel.sx = dev->accel.maj_axis_pcnt & 0x7ff;
dev->accel.sy = dev->accel.multifunc[0] & 0x7ff;
dev->accel.cx = dev->accel.cur_x;
if (dev->accel.cur_x >= 0x600)
dev->accel.cx |= ~0x5ff;
dev->accel.cy = dev->accel.cur_y;
if (dev->accel.cur_y >= 0x600)
dev->accel.cy |= ~0x5ff;
if (((dev->local & 0xff) >= 0x02) && dev->accel.ge_offset && ((dev->accel_bpp == 24) || (dev->accel_bpp == 8)))
dev->accel.dest = (dev->accel.ge_offset << 2) + (dev->accel.cy * dev->pitch);
else
dev->accel.dest = dev->accel.cy * dev->pitch;
if (cmd == 4)
dev->accel.cmd |= 2;
else if (cmd == 3)
dev->accel.cmd &= ~2;
if (ibm8514_cpu_src(svga)) {
if (dev->accel.cmd & 2) {
if (!(dev->accel.cmd & 0x1000)) {
if (!(dev->accel.cmd & 8)) {
dev->accel.sx += and3;
dev->accel.nibbleset = (uint8_t *) calloc(1, (dev->accel.sx >> 3) + 1);
dev->accel.writemono = (uint8_t *) calloc(1, (dev->accel.sx >> 3) + 1);
dev->accel.sys_cnt = (dev->accel.sx >> 3) + 1;
} else {
if (and3 == 1) {
dev->accel.sx += 4;
if (dev->accel.cmd & 0x20)
dev->accel.cx += 4;
else
dev->accel.cx -= 4;
} else if (and3 == 2) {
dev->accel.sx += 5;
if (dev->accel.cmd & 0x20)
dev->accel.cx += 5;
else
dev->accel.cx -= 5;
} else if (and3 == 3) {
dev->accel.sx += 6;
if (dev->accel.cmd & 0x20)
dev->accel.cx += 6;
else
dev->accel.cx -= 6;
} else {
dev->accel.sx += 3;
if (dev->accel.cmd & 0x20)
dev->accel.cx += 3;
else
dev->accel.cx -= 3;
}
}
}
} else {
if (!(dev->accel.cmd & 0x40) && (frgd_mix == 2) && (bkgd_mix == 2) && (pixcntl == 0) && (cmd == 2)) {
if (!(dev->accel.sx & 1)) {
dev->accel.output = 1;
if (((dev->local & 0xff) >= 0x02) && dev->accel.ge_offset && ((dev->accel_bpp == 24) || (dev->accel_bpp == 8)))
dev->accel.newdest_out = (dev->accel.ge_offset << 2) + ((dev->accel.cy + 1) * dev->pitch);
else
dev->accel.newdest_out = (dev->accel.cy + 1) * dev->pitch;
}
}
}
dev->data_available = 0;
dev->data_available2 = 0;
return; /*Wait for data from CPU*/
} else if (ibm8514_cpu_dest(svga)) {
if (!(dev->accel.cmd & 2) && (frgd_mix == 2) && (pixcntl == 0) && (cmd == 2)) {
if (!(dev->accel.sx & 1)) {
dev->accel.input = 1;
if (((dev->local & 0xff) >= 0x02) && dev->accel.ge_offset && ((dev->accel_bpp == 24) || (dev->accel_bpp == 8)))
dev->accel.newdest_in = (dev->accel.ge_offset << 2) + ((dev->accel.cy + 1) * dev->pitch);
else
dev->accel.newdest_in = (dev->accel.cy + 1) * dev->pitch;
}
} else if (dev->accel.cmd & 2) {
if (dev->accel.cmd & 8) {
dev->accel.sx += and3;
dev->accel.nibbleset = (uint8_t *) calloc(1, (dev->accel.sx >> 3) + 1);
dev->accel.writemono = (uint8_t *) calloc(1, (dev->accel.sx >> 3) + 1);
dev->accel.sys_cnt = (dev->accel.sx >> 3) + 1;
}
}
dev->data_available = 1;
dev->data_available2 = 1;
return; /*Wait for data from CPU*/
}
}
if (dev->accel.cmd & 2) {
if (cpu_input) {
rect_fill_pix:
if ((dev->accel.cmd & 8) && ibm8514_cpu_src(svga)) {
dev->accel.xx_count++;
while (count-- && (dev->accel.sy >= 0)) {
if (dev->accel.cx >= dev->accel.clip_left && dev->accel.cx <= clip_r && dev->accel.cy >= dev->accel.clip_top && dev->accel.cy <= clip_b) {
switch ((mix_dat & mix_mask) ? frgd_mix : bkgd_mix) {
case 0:
src_dat = bkgd_color;
break;
case 1:
src_dat = frgd_color;
break;
case 2:
src_dat = cpu_dat;
break;
case 3:
src_dat = 0;
break;
default:
break;
}
READ(dev->accel.dest + dev->accel.cx, dest_dat);
if ((compare_mode == 0) || ((compare_mode == 0x10) && (dest_dat >= compare)) || ((compare_mode == 0x18) && (dest_dat < compare)) || ((compare_mode == 0x20) && (dest_dat != compare)) || ((compare_mode == 0x28) && (dest_dat == compare)) || ((compare_mode == 0x30) && (dest_dat <= compare)) || ((compare_mode == 0x38) && (dest_dat > compare))) {
old_dest_dat = dest_dat;
MIX(mix_dat & mix_mask, dest_dat, src_dat);
dest_dat = (dest_dat & wrt_mask) | (old_dest_dat & ~wrt_mask);
if (and3 == 1) {
if (dev->accel.xx_count >= 2) {
if ((dev->accel.cmd & 4) && dev->accel.sx) {
WRITE(dev->accel.dest + dev->accel.cx, dest_dat);
} else if (!(dev->accel.cmd & 4)) {
WRITE(dev->accel.dest + dev->accel.cx, dest_dat);
}
}
} else if (and3 == 2) {
if (dev->accel.xx_count == 2) {
if (count <= 2) {
if ((dev->accel.cmd & 4) && dev->accel.sx) {
WRITE(dev->accel.dest + dev->accel.cx, dest_dat);
} else if (!(dev->accel.cmd & 4)) {
WRITE(dev->accel.dest + dev->accel.cx, dest_dat);
}
}
} else if (dev->accel.xx_count >= 3) {
if ((dev->accel.cmd & 4) && dev->accel.sx) {
WRITE(dev->accel.dest + dev->accel.cx, dest_dat);
} else if (!(dev->accel.cmd & 4)) {
WRITE(dev->accel.dest + dev->accel.cx, dest_dat);
}
}
} else if (and3 == 3) {
if (dev->accel.xx_count == 2) {
if (count <= 1) {
if ((dev->accel.cmd & 4) && dev->accel.sx) {
WRITE(dev->accel.dest + dev->accel.cx, dest_dat);
} else if (!(dev->accel.cmd & 4)) {
WRITE(dev->accel.dest + dev->accel.cx, dest_dat);
}
}
} else if (dev->accel.xx_count >= 3) {
if ((dev->accel.cmd & 4) && dev->accel.sx) {
WRITE(dev->accel.dest + dev->accel.cx, dest_dat);
} else if (!(dev->accel.cmd & 4)) {
WRITE(dev->accel.dest + dev->accel.cx, dest_dat);
}
}
} else {
if (dev->accel.xx_count == 1) {
if (!count) {
if ((dev->accel.cmd & 4) && dev->accel.sx) {
WRITE(dev->accel.dest + dev->accel.cx, dest_dat);
} else if (!(dev->accel.cmd & 4)) {
WRITE(dev->accel.dest + dev->accel.cx, dest_dat);
}
}
} else if (dev->accel.xx_count >= 2) {
if ((dev->accel.cmd & 4) && dev->accel.sx) {
WRITE(dev->accel.dest + dev->accel.cx, dest_dat);
} else if (!(dev->accel.cmd & 4)) {
WRITE(dev->accel.dest + dev->accel.cx, dest_dat);
}
}
}
}
}
mix_dat <<= 1;
mix_dat |= 1;
if (dev->bpp)
cpu_dat >>= 16;
else
cpu_dat >>= 8;
switch (dev->accel.cmd & 0xe0) {
case 0x00:
dev->accel.cx++;
break;
case 0x20:
dev->accel.cx++;
break;
case 0x60:
dev->accel.cx--;
break;
case 0x80:
dev->accel.cx--;
break;
case 0xa0:
dev->accel.cx--;
break;
case 0xe0:
dev->accel.cx++;
break;
default:
break;
}
dev->accel.sx--;
if (dev->accel.sx < 0) {
dev->accel.sx = dev->accel.maj_axis_pcnt & 0x7ff;
if (and3 == 1)
dev->accel.sx += 4;
else if (and3 == 2)
dev->accel.sx += 5;
else if (and3 == 3)
dev->accel.sx += 6;
else
dev->accel.sx += 3;
if (dev->accel.cmd & 0x20)
dev->accel.cx -= (dev->accel.sx + 1);
else
dev->accel.cx += (dev->accel.sx + 1);
switch (dev->accel.cmd & 0xe0) {
case 0x20:
dev->accel.cy--;
break;
case 0x40:
dev->accel.cy--;
break;
case 0x60:
dev->accel.cy--;
break;
case 0xa0:
dev->accel.cy++;
break;
case 0xc0:
dev->accel.cy++;
break;
case 0xe0:
dev->accel.cy++;
break;
default:
break;
}
if (((dev->local & 0xff) >= 0x02) && dev->accel.ge_offset && ((dev->accel_bpp == 24) || (dev->accel_bpp == 8)))
dev->accel.dest = (dev->accel.ge_offset << 2) + (dev->accel.cy * dev->pitch);
else
dev->accel.dest = dev->accel.cy * dev->pitch;
dev->accel.sy--;
return;
}
}
break;
}
if (count < 8) {
while (count-- && (dev->accel.sy >= 0)) {
if (dev->accel.cx >= dev->accel.clip_left && dev->accel.cx <= clip_r && dev->accel.cy >= dev->accel.clip_top && dev->accel.cy <= clip_b) {
if (ibm8514_cpu_dest(svga) && (pixcntl == 0)) {
mix_dat = mix_mask; /* Mix data = forced to foreground register. */
} else if (ibm8514_cpu_dest(svga) && (pixcntl == 3)) {
/* Mix data = current video memory value. */
READ(dev->accel.dest + dev->accel.cx, mix_dat);
mix_dat = ((mix_dat & rd_mask) == rd_mask);
mix_dat = mix_dat ? mix_mask : 0;
}
if (ibm8514_cpu_dest(svga)) {
READ(dev->accel.dest + dev->accel.cx, src_dat);
if (pixcntl == 3)
src_dat = ((src_dat & rd_mask) == rd_mask);
} else
switch ((mix_dat & mix_mask) ? frgd_mix : bkgd_mix) {
case 0:
src_dat = bkgd_color;
break;
case 1:
src_dat = frgd_color;
break;
case 2:
src_dat = cpu_dat;
break;
case 3:
src_dat = 0;
break;
default:
break;
}
READ(dev->accel.dest + dev->accel.cx, dest_dat);
if ((compare_mode == 0) || ((compare_mode == 0x10) && (dest_dat >= compare)) || ((compare_mode == 0x18) && (dest_dat < compare)) || ((compare_mode == 0x20) && (dest_dat != compare)) || ((compare_mode == 0x28) && (dest_dat == compare)) || ((compare_mode == 0x30) && (dest_dat <= compare)) || ((compare_mode == 0x38) && (dest_dat > compare))) {
old_dest_dat = dest_dat;
MIX(mix_dat & mix_mask, dest_dat, src_dat);
dest_dat = (dest_dat & wrt_mask) | (old_dest_dat & ~wrt_mask);
WRITE(dev->accel.dest + dev->accel.cx, dest_dat);
}
}
mix_dat <<= 1;
mix_dat |= 1;
if (dev->bpp)
cpu_dat >>= 16;
else
cpu_dat >>= 8;
if (dev->accel.cmd & 0x20)
dev->accel.cx++;
else
dev->accel.cx--;
dev->accel.sx--;
if (dev->accel.sx < 0) {
dev->accel.sx = dev->accel.maj_axis_pcnt & 0x7ff;
if (dev->accel.cmd & 2) {
dev->accel.sx += (dev->accel.cur_x & 3);
}
if (dev->accel.cmd & 0x20) {
dev->accel.cx -= (dev->accel.sx) + 1;
} else
dev->accel.cx += (dev->accel.sx) + 1;
if (dev->accel.cmd & 0x80)
dev->accel.cy++;
else
dev->accel.cy--;
if (((dev->local & 0xff) >= 0x02) && dev->accel.ge_offset && ((dev->accel_bpp == 24) || (dev->accel_bpp == 8)))
dev->accel.dest = (dev->accel.ge_offset << 2) + (dev->accel.cy * dev->pitch);
else
dev->accel.dest = dev->accel.cy * dev->pitch;
dev->accel.sy--;
return;
}
}
} else {
while (count-- && (dev->accel.sy >= 0)) {
if (dev->accel.cx >= dev->accel.clip_left && dev->accel.cx <= clip_r && dev->accel.cy >= dev->accel.clip_top && dev->accel.cy <= clip_b) {
if (ibm8514_cpu_dest(svga) && (pixcntl == 0)) {
mix_dat = 1; /* Mix data = forced to foreground register. */
} else if (ibm8514_cpu_dest(svga) && (pixcntl == 3)) {
/* Mix data = current video memory value. */
READ(dev->accel.dest + dev->accel.cx, mix_dat);
mix_dat = ((mix_dat & rd_mask) == rd_mask);
mix_dat = mix_dat ? 1 : 0;
}
if (ibm8514_cpu_dest(svga)) {
READ(dev->accel.dest + dev->accel.cx, src_dat);
if (pixcntl == 3)
src_dat = ((src_dat & rd_mask) == rd_mask);
} else {
switch ((mix_dat & 1) ? frgd_mix : bkgd_mix) {
case 0:
src_dat = bkgd_color;
break;
case 1:
src_dat = frgd_color;
break;
case 2:
src_dat = cpu_dat;
break;
case 3:
src_dat = 0;
break;
default:
break;
}
}
READ(dev->accel.dest + dev->accel.cx, dest_dat);
if ((compare_mode == 0) || ((compare_mode == 0x10) && (dest_dat >= compare)) || ((compare_mode == 0x18) && (dest_dat < compare)) || ((compare_mode == 0x20) && (dest_dat != compare)) || ((compare_mode == 0x28) && (dest_dat == compare)) || ((compare_mode == 0x30) && (dest_dat <= compare)) || ((compare_mode == 0x38) && (dest_dat > compare))) {
old_dest_dat = dest_dat;
MIX(mix_dat & 1, dest_dat, src_dat);
dest_dat = (dest_dat & wrt_mask) | (old_dest_dat & ~wrt_mask);
WRITE(dev->accel.dest + dev->accel.cx, dest_dat);
}
}
mix_dat >>= 1;
if (dev->bpp)
cpu_dat >>= 16;
else
cpu_dat >>= 8;
if (dev->accel.cmd & 0x20)
dev->accel.cx++;
else
dev->accel.cx--;
dev->accel.sx--;
if (dev->accel.sx < 0) {
dev->accel.sx = dev->accel.maj_axis_pcnt & 0x7ff;
if (dev->accel.cmd & 2) {
if (!(dev->accel.cmd & 0x1000))
dev->accel.sx += (dev->accel.cur_x & 3);
}
if (dev->accel.cmd & 0x20) {
dev->accel.cx -= (dev->accel.sx) + 1;
} else
dev->accel.cx += (dev->accel.sx) + 1;
if (dev->accel.cmd & 2) {
if (dev->accel.cmd & 0x1000) {
dev->accel.cx = dev->accel.cur_x;
if (dev->accel.cur_x >= 0x600)
dev->accel.cx |= ~0x5ff;
}
}
if (dev->accel.cmd & 0x80)
dev->accel.cy++;
else
dev->accel.cy--;
if (((dev->local & 0xff) >= 0x02) && dev->accel.ge_offset && ((dev->accel_bpp == 24) || (dev->accel_bpp == 8)))
dev->accel.dest = (dev->accel.ge_offset << 2) + (dev->accel.cy * dev->pitch);
else
dev->accel.dest = dev->accel.cy * dev->pitch;
dev->accel.sy--;
return;
}
}
}
} else {
goto rect_fill;
}
} else {
if (cpu_input) {
if (pixcntl == 2) {
goto rect_fill_pix;
} else {
if (dev->accel.input && !dev->accel.output) {
while (count-- && (dev->accel.sy >= 0)) {
if (dev->accel.cx >= dev->accel.clip_left && dev->accel.cx <= clip_r && dev->accel.cy >= dev->accel.clip_top && dev->accel.cy <= clip_b) {
mix_dat = mix_mask; /* Mix data = forced to foreground register. */
if (!dev->accel.odd_in && !dev->accel.sx) {
READ(dev->accel.newdest_in + dev->accel.cur_x, src_dat);
READ(dev->accel.newdest_in + dev->accel.cur_x, dest_dat);
} else {
READ(dev->accel.dest + dev->accel.cx, src_dat);
READ(dev->accel.dest + dev->accel.cx, dest_dat);
}
if ((compare_mode == 0) || ((compare_mode == 0x10) && (dest_dat >= compare)) || ((compare_mode == 0x18) && (dest_dat < compare)) || ((compare_mode == 0x20) && (dest_dat != compare)) || ((compare_mode == 0x28) && (dest_dat == compare)) || ((compare_mode == 0x30) && (dest_dat <= compare)) || ((compare_mode == 0x38) && (dest_dat > compare))) {
old_dest_dat = dest_dat;
MIX(mix_dat & mix_mask, dest_dat, src_dat);
dest_dat = (dest_dat & wrt_mask) | (old_dest_dat & ~wrt_mask);
if (!dev->accel.odd_in && !dev->accel.sx) {
WRITE(dev->accel.newdest_in + dev->accel.cur_x, dest_dat);
} else {
WRITE(dev->accel.dest + dev->accel.cx, dest_dat);
}
}
}
mix_dat <<= 1;
mix_dat |= 1;
if (dev->accel.cmd & 0x20)
dev->accel.cx++;
else
dev->accel.cx--;
dev->accel.sx--;
if (dev->accel.odd_in) {
if (dev->accel.sx < 0) {
dev->accel.sx = dev->accel.maj_axis_pcnt & 0x7ff;
dev->accel.odd_in = 0;
dev->accel.cx = dev->accel.cur_x;
if (dev->accel.cmd & 0x80)
dev->accel.cy++;
else
dev->accel.cy--;
if (((dev->local & 0xff) >= 0x02) && dev->accel.ge_offset && ((dev->accel_bpp == 24) || (dev->accel_bpp == 8))) {
dev->accel.dest = (dev->accel.ge_offset << 2) + (dev->accel.cy * dev->pitch);
dev->accel.newdest_in = (dev->accel.ge_offset << 2) + ((dev->accel.cy + 1) * dev->pitch);
} else {
dev->accel.dest = dev->accel.cy * dev->pitch;
dev->accel.newdest_in = (dev->accel.cy + 1) * dev->pitch;
}
dev->accel.sy--;
return;
}
} else {
if (dev->accel.sx < 0) {
dev->accel.sx = dev->accel.maj_axis_pcnt & 0x7ff;
dev->accel.sx--;
dev->accel.cx = dev->accel.cur_x;
dev->accel.odd_in = 1;
if (dev->accel.cmd & 0x20)
dev->accel.cx++;
else
dev->accel.cx--;
if (dev->accel.cmd & 0x80)
dev->accel.cy++;
else
dev->accel.cy--;
if (((dev->local & 0xff) >= 0x02) && dev->accel.ge_offset && ((dev->accel_bpp == 24) || (dev->accel_bpp == 8))) {
dev->accel.dest = (dev->accel.ge_offset << 2) + (dev->accel.cy * dev->pitch);
dev->accel.newdest_in = (dev->accel.ge_offset << 2) + ((dev->accel.cy + 1) * dev->pitch);
} else {
dev->accel.dest = dev->accel.cy * dev->pitch;
dev->accel.newdest_in = (dev->accel.cy + 1) * dev->pitch;
}
dev->accel.sy--;
return;
}
}
}
} else if (dev->accel.output && !dev->accel.input) {
while (count-- && (dev->accel.sy >= 0)) {
if (dev->accel.cx >= dev->accel.clip_left && dev->accel.cx <= clip_r && dev->accel.cy >= dev->accel.clip_top && dev->accel.cy <= clip_b) {
src_dat = cpu_dat;
if (!dev->accel.odd_out && !dev->accel.sx) {
READ(dev->accel.newdest_out + dev->accel.cur_x, dest_dat);
} else {
READ(dev->accel.dest + dev->accel.cx, dest_dat);
}
if ((compare_mode == 0) || ((compare_mode == 0x10) && (dest_dat >= compare)) || ((compare_mode == 0x18) && (dest_dat < compare)) || ((compare_mode == 0x20) && (dest_dat != compare)) || ((compare_mode == 0x28) && (dest_dat == compare)) || ((compare_mode == 0x30) && (dest_dat <= compare)) || ((compare_mode == 0x38) && (dest_dat > compare))) {
old_dest_dat = dest_dat;
MIX(mix_dat & mix_mask, dest_dat, src_dat);
dest_dat = (dest_dat & wrt_mask) | (old_dest_dat & ~wrt_mask);
if (!dev->accel.odd_out && !dev->accel.sx) {
WRITE(dev->accel.newdest_out + dev->accel.cur_x, dest_dat);
} else {
WRITE(dev->accel.dest + dev->accel.cx, dest_dat);
}
}
}
mix_dat <<= 1;
mix_dat |= 1;
if (dev->bpp)
cpu_dat >>= 16;
else
cpu_dat >>= 8;
if (dev->accel.cmd & 0x20)
dev->accel.cx++;
else
dev->accel.cx--;
dev->accel.sx--;
if (dev->accel.odd_out) {
if (dev->accel.sx < 0) {
dev->accel.sx = dev->accel.maj_axis_pcnt & 0x7ff;
dev->accel.odd_out = 0;
dev->accel.cx = dev->accel.cur_x;
if (dev->accel.cmd & 0x80)
dev->accel.cy++;
else
dev->accel.cy--;
if (((dev->local & 0xff) >= 0x02) && dev->accel.ge_offset && ((dev->accel_bpp == 24) || (dev->accel_bpp == 8))) {
dev->accel.dest = (dev->accel.ge_offset << 2) + (dev->accel.cy * dev->pitch);
dev->accel.newdest_out = (dev->accel.ge_offset << 2) + ((dev->accel.cy + 1) * dev->pitch);
} else {
dev->accel.dest = dev->accel.cy * dev->pitch;
dev->accel.newdest_out = (dev->accel.cy + 1) * dev->pitch;
}
dev->accel.sy--;
return;
}
} else {
if (dev->accel.sx < 0) {
dev->accel.sx = dev->accel.maj_axis_pcnt & 0x7ff;
dev->accel.odd_out = 1;
dev->accel.sx--;
dev->accel.cx = dev->accel.cur_x;
if (dev->accel.cmd & 0x20)
dev->accel.cx++;
else
dev->accel.cx--;
if (dev->accel.cmd & 0x80)
dev->accel.cy++;
else
dev->accel.cy--;
if (((dev->local & 0xff) >= 0x02) && dev->accel.ge_offset && ((dev->accel_bpp == 24) || (dev->accel_bpp == 8))) {
dev->accel.dest = (dev->accel.ge_offset << 2) + (dev->accel.cy * dev->pitch);
dev->accel.newdest_out = (dev->accel.ge_offset << 2) + ((dev->accel.cy + 1) * dev->pitch);
} else {
dev->accel.dest = dev->accel.cy * dev->pitch;
dev->accel.newdest_out = (dev->accel.cy + 1) * dev->pitch;
}
dev->accel.sy--;
return;
}
}
}
} else {
while (count-- && (dev->accel.sy >= 0)) {
if (dev->accel.cx >= dev->accel.clip_left && dev->accel.cx <= clip_r && dev->accel.cy >= dev->accel.clip_top && dev->accel.cy <= clip_b) {
if (ibm8514_cpu_dest(svga) && (pixcntl == 0)) {
mix_dat = mix_mask; /* Mix data = forced to foreground register. */
} else if (ibm8514_cpu_dest(svga) && (pixcntl == 3)) {
/* Mix data = current video memory value. */
READ(dev->accel.dest + dev->accel.cx, mix_dat);
mix_dat = ((mix_dat & rd_mask) == rd_mask);
mix_dat = mix_dat ? mix_mask : 0;
}
if (ibm8514_cpu_dest(svga)) {
READ(dev->accel.dest + dev->accel.cx, src_dat);
if (pixcntl == 3) {
src_dat = ((src_dat & rd_mask) == rd_mask);
}
} else
switch ((mix_dat & mix_mask) ? frgd_mix : bkgd_mix) {
case 0:
src_dat = bkgd_color;
break;
case 1:
src_dat = frgd_color;
break;
case 2:
src_dat = cpu_dat;
break;
case 3:
src_dat = 0;
break;
default:
break;
}
READ(dev->accel.dest + dev->accel.cx, dest_dat);
if ((compare_mode == 0) || ((compare_mode == 0x10) && (dest_dat >= compare)) || ((compare_mode == 0x18) && (dest_dat < compare)) || ((compare_mode == 0x20) && (dest_dat != compare)) || ((compare_mode == 0x28) && (dest_dat == compare)) || ((compare_mode == 0x30) && (dest_dat <= compare)) || ((compare_mode == 0x38) && (dest_dat > compare))) {
old_dest_dat = dest_dat;
if (ibm8514_cpu_dest(svga)) {
if (pixcntl == 3) {
MIX(mix_dat & mix_mask, dest_dat, src_dat);
}
} else {
MIX(mix_dat & mix_mask, dest_dat, src_dat);
}
dest_dat = (dest_dat & wrt_mask) | (old_dest_dat & ~wrt_mask);
WRITE(dev->accel.dest + dev->accel.cx, dest_dat);
}
}
mix_dat <<= 1;
mix_dat |= 1;
if (dev->bpp)
cpu_dat >>= 16;
else
cpu_dat >>= 8;
if (dev->accel.cmd & 0x20)
dev->accel.cx++;
else
dev->accel.cx--;
dev->accel.sx--;
if (dev->accel.sx < 0) {
dev->accel.sx = dev->accel.maj_axis_pcnt & 0x7ff;
if (dev->accel.cmd & 0x20) {
dev->accel.cx -= (dev->accel.sx) + 1;
} else
dev->accel.cx += (dev->accel.sx) + 1;
if (dev->accel.cmd & 0x80)
dev->accel.cy++;
else
dev->accel.cy--;
if (((dev->local & 0xff) >= 0x02) && dev->accel.ge_offset && ((dev->accel_bpp == 24) || (dev->accel_bpp == 8)))
dev->accel.dest = (dev->accel.ge_offset << 2) + (dev->accel.cy * dev->pitch);
else
dev->accel.dest = dev->accel.cy * dev->pitch;
dev->accel.sy--;
return;
}
}
}
}
} else {
rect_fill:
if (pixcntl == 1) {
if (dev->accel.cmd & 0x40) {
count = dev->accel.maj_axis_pcnt + 1;
dev->accel.temp_cnt = 8;
while (count-- && dev->accel.sy >= 0) {
if (dev->accel.temp_cnt == 0) {
mix_dat >>= 8;
dev->accel.temp_cnt = 8;
}
if (dev->accel.cx >= dev->accel.clip_left && dev->accel.cx <= clip_r && dev->accel.cy >= dev->accel.clip_top && dev->accel.cy <= clip_b) {
switch ((mix_dat & mix_mask) ? frgd_mix : bkgd_mix) {
case 0:
src_dat = bkgd_color;
break;
case 1:
src_dat = frgd_color;
break;
case 2:
src_dat = 0;
break;
case 3:
src_dat = 0;
break;
default:
break;
}
READ(dev->accel.dest + dev->accel.cx, dest_dat);
if ((compare_mode == 0) || ((compare_mode == 0x10) && (dest_dat >= compare)) || ((compare_mode == 0x18) && (dest_dat < compare)) || ((compare_mode == 0x20) && (dest_dat != compare)) || ((compare_mode == 0x28) && (dest_dat == compare)) || ((compare_mode == 0x30) && (dest_dat <= compare)) || ((compare_mode == 0x38) && (dest_dat > compare))) {
old_dest_dat = dest_dat;
MIX(mix_dat & mix_mask, dest_dat, src_dat);
dest_dat = (dest_dat & wrt_mask) | (old_dest_dat & ~wrt_mask);
WRITE(dev->accel.dest + dev->accel.cx, dest_dat);
}
}
if (dev->accel.temp_cnt > 0) {
dev->accel.temp_cnt--;
mix_dat <<= 1;
mix_dat |= 1;
}
if (dev->accel.cmd & 0x20)
dev->accel.cx++;
else
dev->accel.cx--;
dev->accel.sx--;
if (dev->accel.sx < 0) {
dev->accel.sx = dev->accel.maj_axis_pcnt & 0x7ff;
if (dev->accel.cmd & 0x20) {
dev->accel.cx -= (dev->accel.sx) + 1;
} else
dev->accel.cx += (dev->accel.sx) + 1;
if (dev->accel.cmd & 0x80)
dev->accel.cy++;
else
dev->accel.cy--;
if (((dev->local & 0xff) >= 0x02) && dev->accel.ge_offset && ((dev->accel_bpp == 24) || (dev->accel_bpp == 8)))
dev->accel.dest = (dev->accel.ge_offset << 2) + (dev->accel.cy * dev->pitch);
else
dev->accel.dest = dev->accel.cy * dev->pitch;
dev->accel.sy--;
dev->accel.cur_x = dev->accel.cx;
dev->accel.cur_y = dev->accel.cy;
return;
}
}
} else {
dev->accel.temp_cnt = 8;
while (count-- && dev->accel.sy >= 0) {
if (!dev->accel.temp_cnt) {
dev->accel.temp_cnt = 8;
mix_dat = old_mix_dat;
}
if (dev->accel.cx >= dev->accel.clip_left && dev->accel.cx <= clip_r && dev->accel.cy >= dev->accel.clip_top && dev->accel.cy <= clip_b) {
switch ((mix_dat & 1) ? frgd_mix : bkgd_mix) {
case 0:
src_dat = bkgd_color;
break;
case 1:
src_dat = frgd_color;
break;
case 2:
src_dat = 0;
break;
case 3:
src_dat = 0;
break;
default:
break;
}
READ(dev->accel.dest + dev->accel.cx, dest_dat);
if ((compare_mode == 0) || ((compare_mode == 0x10) && (dest_dat >= compare)) || ((compare_mode == 0x18) && (dest_dat < compare)) || ((compare_mode == 0x20) && (dest_dat != compare)) || ((compare_mode == 0x28) && (dest_dat == compare)) || ((compare_mode == 0x30) && (dest_dat <= compare)) || ((compare_mode == 0x38) && (dest_dat > compare))) {
old_dest_dat = dest_dat;
MIX(mix_dat & 1, dest_dat, src_dat);
dest_dat = (dest_dat & wrt_mask) | (old_dest_dat & ~wrt_mask);
WRITE(dev->accel.dest + dev->accel.cx, dest_dat);
}
}
dev->accel.temp_cnt--;
mix_dat >>= 1;
if (dev->accel.cmd & 0x20)
dev->accel.cx++;
else
dev->accel.cx--;
dev->accel.sx--;
if (dev->accel.sx < 0) {
dev->accel.sx = dev->accel.maj_axis_pcnt & 0x7ff;
if (dev->accel.cmd & 0x20) {
dev->accel.cx -= (dev->accel.sx) + 1;
} else
dev->accel.cx += (dev->accel.sx) + 1;
if (dev->accel.cmd & 0x80)
dev->accel.cy++;
else
dev->accel.cy--;
if (((dev->local & 0xff) >= 0x02) && dev->accel.ge_offset && ((dev->accel_bpp == 24) || (dev->accel_bpp == 8)))
dev->accel.dest = (dev->accel.ge_offset << 2) + (dev->accel.cy * dev->pitch);
else
dev->accel.dest = dev->accel.cy * dev->pitch;
dev->accel.sy--;
if (dev->accel.sy < 0) {
dev->accel.cur_x = dev->accel.cx;
dev->accel.cur_y = dev->accel.cy;
return;
}
}
}
}
} else {
if ((dev->accel.multifunc[0x0a] & 6) == 4) {
while (count-- && (dev->accel.sy >= 0)) {
if (dev->accel.cx >= dev->accel.clip_left && dev->accel.cx <= clip_r && dev->accel.cy >= dev->accel.clip_top && dev->accel.cy <= clip_b) {
READ(dev->accel.dest + dev->accel.cx, mix_dat);
if ((mix_dat & rd_mask_polygon) == rd_mask_polygon)
dev->accel.fill_state = !dev->accel.fill_state;
READ(dev->accel.dest + dev->accel.cx, dest_dat);
old_dest_dat = dest_dat;
if (dev->accel.fill_state) {
if (!(rd_mask_polygon & 1) && (wrt_mask & 1)) {
MIX(mix_dat ^ rd_mask_polygon, dest_dat, mix_dat);
ibm8514_log("Filling c(%d,%d) without bit 0 of rdmask=%02x, wrtmask=%02x, mixdat=%02x, dest=%02x, old=%02x.\n", dev->accel.cx, dev->accel.cy, rd_mask_polygon, wrt_mask, mix_dat, dest_dat, old_dest_dat);
dest_dat &= ~rd_mask_polygon;
} else if ((rd_mask_polygon & 1) && (wrt_mask & 1)) {
ibm8514_log("Filling c(%d,%d) with bit 0 of rdmask=%02x, wrtmask=%02x.\n", dev->accel.cx, dev->accel.cy, rd_mask_polygon, wrt_mask);
dest_dat &= ~(rd_mask_polygon & wrt_mask);
}
} else {
if (!(rd_mask_polygon & 1) && (wrt_mask & 1))
dest_dat &= ~rd_mask_polygon;
else if ((rd_mask_polygon & 1) && (wrt_mask & 1))
dest_dat &= ~(rd_mask_polygon & wrt_mask);
}
dest_dat = (dest_dat & wrt_mask) | (old_dest_dat & ~wrt_mask);
if ((compare_mode == 0) || ((compare_mode == 0x10) && (dest_dat >= compare)) || ((compare_mode == 0x18) && (dest_dat < compare)) || ((compare_mode == 0x20) && (dest_dat != compare)) || ((compare_mode == 0x28) && (dest_dat == compare)) || ((compare_mode == 0x30) && (dest_dat <= compare)) || ((compare_mode == 0x38) && (dest_dat > compare))) {
ibm8514_log("Results c(%d,%d):rdmask=%02x, wrtmask=%02x, mix=%02x, destdat=%02x, nowrite=%d.\n", dev->accel.cx, dev->accel.cy, rd_mask_polygon, wrt_mask, mix_dat, dest_dat, dev->accel.cx_back);
WRITE(dev->accel.dest + dev->accel.cx, dest_dat);
}
}
if (dev->accel.cmd & 0x20)
dev->accel.cx++;
else
dev->accel.cx--;
dev->accel.sx--;
if (dev->accel.sx < 0) {
dev->accel.fill_state = 0;
dev->accel.sx = dev->accel.maj_axis_pcnt & 0x7ff;
if (dev->accel.cmd & 0x20)
dev->accel.cx -= (dev->accel.sx) + 1;
else
dev->accel.cx += (dev->accel.sx) + 1;
if (dev->accel.cmd & 0x80)
dev->accel.cy++;
else
dev->accel.cy--;
dev->accel.dest = dev->accel.cy * dev->pitch;
dev->accel.sy--;
if (dev->accel.sy < 0) {
ibm8514_log(".\n");
return;
}
}
}
} else {
ibm8514_log("Rectangle Fill Normal CMD=%04x, CURRENT(%d,%d), sx=%d, FR(%02x), linedraw=%d.\n", dev->accel.cmd, dev->accel.cx, dev->accel.cy, dev->accel.sx, frgd_color, dev->accel.linedraw);
while (count-- && dev->accel.sy >= 0) {
if (dev->accel.cx >= dev->accel.clip_left && dev->accel.cx <= clip_r && dev->accel.cy >= dev->accel.clip_top && dev->accel.cy <= clip_b) {
switch ((mix_dat & mix_mask) ? frgd_mix : bkgd_mix) {
case 0:
src_dat = bkgd_color;
if (!bkgd_mix && (dev->accel.cmd & 0x40) && ((dev->accel.frgd_mix & 0x1f) == 7) && ((dev->accel.bkgd_mix & 0x1f) == 3) && !dev->bpp && (bkgd_color == 0x00)) /*For some reason, the September 1992 Mach8/32 drivers for Win3.x don't set the background colors properly.*/
src_dat = frgd_color;
break;
case 1:
src_dat = frgd_color;
break;
case 2:
src_dat = 0;
break;
case 3:
src_dat = 0;
break;
default:
break;
}
READ(dev->accel.dest + dev->accel.cx, dest_dat);
if ((compare_mode == 0) || ((compare_mode == 0x10) && (dest_dat >= compare)) || ((compare_mode == 0x18) && (dest_dat < compare)) || ((compare_mode == 0x20) && (dest_dat != compare)) || ((compare_mode == 0x28) && (dest_dat == compare)) || ((compare_mode == 0x30) && (dest_dat <= compare)) || ((compare_mode == 0x38) && (dest_dat > compare))) {
old_dest_dat = dest_dat;
MIX(mix_dat & mix_mask, dest_dat, src_dat);
dest_dat = (dest_dat & wrt_mask) | (old_dest_dat & ~wrt_mask);
if (dev->accel.cmd & 0x10) {
WRITE(dev->accel.dest + dev->accel.cx, dest_dat);
}
}
}
mix_dat <<= 1;
mix_dat |= 1;
if (dev->accel.cmd & 0x20)
dev->accel.cx++;
else
dev->accel.cx--;
dev->accel.sx--;
if (dev->accel.sx < 0) {
dev->accel.fill_state = 0;
dev->accel.sx = dev->accel.maj_axis_pcnt & 0x7ff;
if (dev->accel.cmd & 0x20)
dev->accel.cx -= (dev->accel.sx) + 1;
else
dev->accel.cx += (dev->accel.sx) + 1;
if (dev->accel.cmd & 0x80)
dev->accel.cy++;
else
dev->accel.cy--;
if (((dev->local & 0xff) >= 0x02) && dev->accel.ge_offset && ((dev->accel_bpp == 24) || (dev->accel_bpp == 8)))
dev->accel.dest = (dev->accel.ge_offset << 2) + (dev->accel.cy * dev->pitch);
else
dev->accel.dest = dev->accel.cy * dev->pitch;
dev->accel.sy--;
if (dev->accel.sy < 0) {
dev->accel.cur_x = dev->accel.cx;
dev->accel.cur_y = dev->accel.cy;
return;
}
}
}
}
}
}
}
break;
case 5: /*Draw Polygon Boundary Line*/ {
if (!cpu_input) {
dev->accel.cx = dev->accel.cur_x;
if (dev->accel.cur_x >= 0x600)
dev->accel.cx |= ~0x5ff;
dev->accel.cy = dev->accel.cur_y;
if (dev->accel.cur_y >= 0x600)
dev->accel.cy |= ~0x5ff;
dev->accel.sy = dev->accel.maj_axis_pcnt_no_limit;
if (dev->accel.cmd & 0x80)
dev->accel.oldcy = dev->accel.cy + 1;
else
dev->accel.oldcy = dev->accel.cy - 1;
dev->accel.oldcx = 0;
ibm8514_log("Polygon Boundary activated=%04x, len=%d, cur(%d,%d), frgdmix=%02x, err=%d, clipping: l=%d, r=%d, t=%d, b=%d, pixcntl=%02x.\n", dev->accel.cmd, dev->accel.sy, dev->accel.cur_x_nolimit, dev->accel.cy, dev->accel.frgd_mix & 0x1f, dev->accel.err_term, dev->accel.clip_left, clip_r, dev->accel.clip_top, clip_b, compare_mode, dev->accel.multifunc[0x0a]);
if (ibm8514_cpu_src(svga)) {
dev->data_available = 0;
dev->data_available2 = 0;
return; /*Wait for data from CPU*/
} else if (ibm8514_cpu_dest(svga)) {
dev->data_available = 1;
dev->data_available2 = 1;
return;
}
}
if (dev->accel.cmd & 8) {
while (count-- && (dev->accel.sy >= 0)) {
if (dev->accel.cx < 0)
dev->accel.cx = 0;
if (dev->accel.cy < 0)
dev->accel.cy = 0;
if (dev->accel.cx >= dev->accel.clip_left && dev->accel.cx <= clip_r && dev->accel.cy >= dev->accel.clip_top && dev->accel.cy <= clip_b) {
switch ((mix_dat & mix_mask) ? frgd_mix : bkgd_mix) {
case 0:
src_dat = bkgd_color;
break;
case 1:
src_dat = frgd_color;
break;
case 2:
src_dat = cpu_dat;
break;
case 3:
src_dat = 0;
break;
default:
break;
}
READ((dev->accel.cy * dev->pitch) + dev->accel.cx, dest_dat);
if ((compare_mode == 0) || ((compare_mode == 0x10) && (dest_dat >= compare)) || ((compare_mode == 0x18) && (dest_dat < compare)) || ((compare_mode == 0x20) && (dest_dat != compare)) || ((compare_mode == 0x28) && (dest_dat == compare)) || ((compare_mode == 0x30) && (dest_dat <= compare)) || ((compare_mode == 0x38) && (dest_dat > compare))) {
old_dest_dat = dest_dat;
MIX(mix_dat & mix_mask, dest_dat, src_dat);
dest_dat = (dest_dat & wrt_mask) | (old_dest_dat & ~wrt_mask);
if (dev->accel.cmd & 0x10) {
if (dev->accel.sy && (dev->accel.cmd & 4)) {
if (dev->accel.oldcy != dev->accel.cy) {
WRITE((dev->accel.cy * dev->pitch) + (dev->accel.cx), dest_dat);
}
} else if (!(dev->accel.cmd & 4)) {
if (dev->accel.oldcy != dev->accel.cy) {
WRITE((dev->accel.cy * dev->pitch) + (dev->accel.cx), dest_dat);
}
}
}
}
}
mix_dat <<= 1;
mix_dat |= 1;
if (dev->bpp)
cpu_dat >>= 16;
else
cpu_dat >>= 8;
if (!dev->accel.sy)
break;
switch (dev->accel.cmd & 0xe0) {
case 0x00:
dev->accel.cx++;
break;
case 0x20:
dev->accel.cx++;
dev->accel.oldcy = dev->accel.cy;
dev->accel.cy--;
break;
case 0x40:
dev->accel.oldcy = dev->accel.cy;
dev->accel.cy--;
break;
case 0x60:
dev->accel.cx--;
dev->accel.oldcy = dev->accel.cy;
dev->accel.cy--;
break;
case 0x80:
dev->accel.cx--;
break;
case 0xa0:
dev->accel.cx--;
dev->accel.oldcy = dev->accel.cy;
dev->accel.cy++;
break;
case 0xc0:
dev->accel.oldcy = dev->accel.cy;
dev->accel.cy++;
break;
case 0xe0:
dev->accel.cx++;
dev->accel.oldcy = dev->accel.cy;
dev->accel.cy++;
break;
default:
break;
}
dev->accel.sy--;
}
} else {
while (count-- && (dev->accel.sy >= 0)) {
if (dev->accel.cx < 0)
dev->accel.cx = 0;
if (dev->accel.cy < 0)
dev->accel.cy = 0;
if (dev->accel.cx >= dev->accel.clip_left && dev->accel.cx <= clip_r && dev->accel.cy >= dev->accel.clip_top && dev->accel.cy <= clip_b) {
switch ((mix_dat & mix_mask) ? frgd_mix : bkgd_mix) {
case 0:
src_dat = bkgd_color;
break;
case 1:
src_dat = frgd_color;
break;
case 2:
src_dat = cpu_dat;
break;
case 3:
src_dat = 0;
break;
default:
break;
}
READ((dev->accel.cy * dev->pitch) + dev->accel.cx, dest_dat);
if ((compare_mode == 0) || ((compare_mode == 0x10) && (dest_dat >= compare)) || ((compare_mode == 0x18) && (dest_dat < compare)) || ((compare_mode == 0x20) && (dest_dat != compare)) || ((compare_mode == 0x28) && (dest_dat == compare)) || ((compare_mode == 0x30) && (dest_dat <= compare)) || ((compare_mode == 0x38) && (dest_dat > compare))) {
old_dest_dat = dest_dat;
MIX(mix_dat & mix_mask, dest_dat, src_dat);
dest_dat = (dest_dat & wrt_mask) | (old_dest_dat & ~wrt_mask);
if ((dev->accel.cmd & 0x14) == 0x14) {
if (dev->accel.sy) {
if (dev->accel.cmd & 0x40) {
WRITE((dev->accel.cy * dev->pitch) + dev->accel.cx, dest_dat);
} else {
if (dev->accel.oldcy != dev->accel.cy) {
WRITE((dev->accel.cy * dev->pitch) + dev->accel.cx, dest_dat);
}
}
}
}
}
}
mix_dat <<= 1;
mix_dat |= 1;
if (dev->bpp)
cpu_dat >>= 16;
else
cpu_dat >>= 8;
if (!dev->accel.sy)
break;
if (dev->accel.cmd & 0x40) {
if (dev->accel.cmd & 0x80)
dev->accel.cy++;
else
dev->accel.cy--;
if (dev->accel.err_term >= 0) {
dev->accel.err_term += dev->accel.destx_distp;
if (dev->accel.cmd & 0x20)
dev->accel.cx++;
else
dev->accel.cx--;
} else
dev->accel.err_term += dev->accel.desty_axstp;
} else {
if (dev->accel.cmd & 0x20)
dev->accel.cx++;
else
dev->accel.cx--;
dev->accel.oldcy = dev->accel.cy;
if (dev->accel.err_term >= 0) {
dev->accel.err_term += dev->accel.destx_distp;
if (dev->accel.cmd & 0x80)
dev->accel.cy++;
else
dev->accel.cy--;
} else
dev->accel.err_term += dev->accel.desty_axstp;
}
dev->accel.sy--;
}
}
}
break;
case 6: /*BitBlt*/
if (!cpu_input) /*!cpu_input is trigger to start operation*/
{
dev->accel.x_count = 0;
dev->accel.output = 0;
dev->accel.sx = dev->accel.maj_axis_pcnt & 0x7ff;
dev->accel.sy = dev->accel.multifunc[0] & 0x7ff;
dev->accel.dx = dev->accel.destx;
dev->accel.dy = dev->accel.desty;
if (dev->accel.destx >= 0x600)
dev->accel.dx |= ~0x5ff;
if (dev->accel.desty >= 0x600)
dev->accel.dy |= ~0x5ff;
dev->accel.cx = dev->accel.cur_x;
dev->accel.cy = dev->accel.cur_y;
if (dev->accel.cur_x >= 0x600)
dev->accel.cx |= ~0x5ff;
if (dev->accel.cur_y >= 0x600)
dev->accel.cy |= ~0x5ff;
dev->accel.src = dev->accel.cy * dev->pitch;
dev->accel.dest = dev->accel.dy * dev->pitch;
dev->accel.fill_state = 0;
if (ibm8514_cpu_src(svga)) {
if (dev->accel.cmd & 2) {
if (!(dev->accel.cmd & 0x1000)) {
dev->accel.sx += (dev->accel.cur_x & 3);
dev->accel.nibbleset = (uint8_t *) calloc(1, (dev->accel.sx >> 3) + 1);
dev->accel.writemono = (uint8_t *) calloc(1, (dev->accel.sx >> 3) + 1);
dev->accel.sys_cnt = (dev->accel.sx >> 3) + 1;
}
}
dev->data_available = 0;
dev->data_available2 = 0;
return; /*Wait for data from CPU*/
} else if (ibm8514_cpu_dest(svga)) {
dev->data_available = 1;
dev->data_available2 = 1;
return; /*Wait for data from CPU*/
}
}
if (dev->accel.cmd & 2) {
if (cpu_input) {
bitblt_pix:
if (count < 8) {
while (count-- && (dev->accel.sy >= 0)) {
if (dev->accel.dx >= dev->accel.clip_left && dev->accel.dx <= clip_r && dev->accel.dy >= dev->accel.clip_top && dev->accel.dy <= clip_b) {
if (pixcntl == 3) {
if (!(dev->accel.cmd & 0x10) && ((frgd_mix != 3) || (bkgd_mix != 3))) {
READ(dev->accel.src + dev->accel.cx, mix_dat);
mix_dat = ((mix_dat & rd_mask) == rd_mask);
mix_dat = mix_dat ? mix_mask : 0;
} else if (dev->accel.cmd & 0x10) {
READ(dev->accel.src + dev->accel.cx, mix_dat);
mix_dat = ((mix_dat & rd_mask) == rd_mask);
mix_dat = mix_dat ? mix_mask : 0;
}
}
switch ((mix_dat & mix_mask) ? frgd_mix : bkgd_mix) {
case 0:
src_dat = bkgd_color;
break;
case 1:
src_dat = frgd_color;
break;
case 2:
src_dat = cpu_dat;
break;
case 3:
READ(dev->accel.src + dev->accel.cx, src_dat);
if (pixcntl == 3) {
if (dev->accel.cmd & 0x10) {
src_dat = ((src_dat & rd_mask) == rd_mask);
}
}
break;
default:
break;
}
READ(dev->accel.dest + dev->accel.dx, dest_dat);
if ((compare_mode == 0) || ((compare_mode == 0x10) && (dest_dat >= compare)) || ((compare_mode == 0x18) && (dest_dat < compare)) || ((compare_mode == 0x20) && (dest_dat != compare)) || ((compare_mode == 0x28) && (dest_dat == compare)) || ((compare_mode == 0x30) && (dest_dat <= compare)) || ((compare_mode == 0x38) && (dest_dat > compare))) {
old_dest_dat = dest_dat;
MIX(mix_dat & mix_mask, dest_dat, src_dat);
dest_dat = (dest_dat & wrt_mask) | (old_dest_dat & ~wrt_mask);
WRITE(dev->accel.dest + dev->accel.dx, dest_dat);
}
}
mix_dat <<= 1;
mix_dat |= 1;
if (dev->bpp)
cpu_dat >>= 16;
else
cpu_dat >>= 8;
if (dev->accel.cmd & 0x20) {
dev->accel.dx++;
dev->accel.cx++;
} else {
dev->accel.dx--;
dev->accel.cx--;
}
dev->accel.sx--;
if (dev->accel.sx < 0) {
dev->accel.sx = dev->accel.maj_axis_pcnt & 0x7ff;
if (dev->accel.cmd & 2) {
dev->accel.sx += (dev->accel.cur_x & 3);
}
if (dev->accel.cmd & 0x20) {
dev->accel.dx -= (dev->accel.sx) + 1;
dev->accel.cx -= (dev->accel.sx) + 1;
} else {
dev->accel.dx += (dev->accel.sx) + 1;
dev->accel.cx += (dev->accel.sx) + 1;
}
if (dev->accel.cmd & 0x80) {
dev->accel.dy++;
dev->accel.cy++;
} else {
dev->accel.dy--;
dev->accel.cy--;
}
dev->accel.src = dev->accel.cy * dev->pitch;
dev->accel.dest = dev->accel.dy * dev->pitch;
dev->accel.sy--;
return;
}
}
} else {
while (count-- && (dev->accel.sy >= 0)) {
if (dev->accel.dx >= dev->accel.clip_left && dev->accel.dx <= clip_r && dev->accel.dy >= dev->accel.clip_top && dev->accel.dy <= clip_b) {
if (pixcntl == 3) {
if (!(dev->accel.cmd & 0x10) && ((frgd_mix != 3) || (bkgd_mix != 3))) {
READ(dev->accel.src + dev->accel.cx, mix_dat);
mix_dat = ((mix_dat & rd_mask) == rd_mask);
mix_dat = mix_dat ? 1 : 0;
} else if (dev->accel.cmd & 0x10) {
READ(dev->accel.src + dev->accel.cx, mix_dat);
mix_dat = ((mix_dat & rd_mask) == rd_mask);
mix_dat = mix_dat ? 1 : 0;
}
}
switch ((mix_dat & 1) ? frgd_mix : bkgd_mix) {
case 0:
src_dat = bkgd_color;
break;
case 1:
src_dat = frgd_color;
break;
case 2:
src_dat = cpu_dat;
break;
case 3:
READ(dev->accel.src + dev->accel.cx, src_dat);
if (pixcntl == 3) {
if (dev->accel.cmd & 0x10) {
src_dat = ((src_dat & rd_mask) == rd_mask);
}
}
break;
default:
break;
}
READ(dev->accel.dest + dev->accel.dx, dest_dat);
if ((compare_mode == 0) || ((compare_mode == 0x10) && (dest_dat >= compare)) || ((compare_mode == 0x18) && (dest_dat < compare)) || ((compare_mode == 0x20) && (dest_dat != compare)) || ((compare_mode == 0x28) && (dest_dat == compare)) || ((compare_mode == 0x30) && (dest_dat <= compare)) || ((compare_mode == 0x38) && (dest_dat > compare))) {
old_dest_dat = dest_dat;
MIX(mix_dat & 1, dest_dat, src_dat);
dest_dat = (dest_dat & wrt_mask) | (old_dest_dat & ~wrt_mask);
WRITE(dev->accel.dest + dev->accel.dx, dest_dat);
}
}
mix_dat >>= 1;
if (dev->bpp)
cpu_dat >>= 16;
else
cpu_dat >>= 8;
if (dev->accel.cmd & 0x20) {
dev->accel.dx++;
dev->accel.cx++;
} else {
dev->accel.dx--;
dev->accel.cx--;
}
dev->accel.sx--;
if (dev->accel.sx < 0) {
dev->accel.sx = dev->accel.maj_axis_pcnt & 0x7ff;
if (dev->accel.cmd & 2) {
if (!(dev->accel.cmd & 0x1000))
dev->accel.sx += (dev->accel.cur_x & 3);
}
if (dev->accel.cmd & 0x20) {
dev->accel.dx -= (dev->accel.sx) + 1;
dev->accel.cx -= (dev->accel.sx) + 1;
} else {
dev->accel.dx += (dev->accel.sx) + 1;
dev->accel.cx += (dev->accel.sx) + 1;
}
if (dev->accel.cmd & 2) {
if (dev->accel.cmd & 0x1000) {
dev->accel.cx = dev->accel.cur_x;
if (dev->accel.cur_x >= 0x600)
dev->accel.cx |= ~0x5ff;
dev->accel.dx = dev->accel.destx;
if (dev->accel.destx >= 0x600)
dev->accel.dx |= ~0x5ff;
}
}
if (dev->accel.cmd & 0x80) {
dev->accel.dy++;
dev->accel.cy++;
} else {
dev->accel.dy--;
dev->accel.cy--;
}
dev->accel.dest = dev->accel.dy * dev->pitch;
dev->accel.src = dev->accel.cy * dev->pitch;
dev->accel.sy--;
return;
}
}
}
} else {
goto bitblt;
}
} else {
if (cpu_input) {
if (pixcntl == 2) {
goto bitblt_pix;
} else {
while (count-- && (dev->accel.sy >= 0)) {
if (dev->accel.dx >= dev->accel.clip_left && dev->accel.dx <= clip_r && dev->accel.dy >= dev->accel.clip_top && dev->accel.dy <= clip_b) {
if (pixcntl == 3) {
if (!(dev->accel.cmd & 0x10) && ((frgd_mix != 3) || (bkgd_mix != 3))) {
READ(dev->accel.src + dev->accel.cx, mix_dat);
mix_dat = ((mix_dat & rd_mask) == rd_mask);
mix_dat = mix_dat ? mix_mask : 0;
} else if (dev->accel.cmd & 0x10) {
READ(dev->accel.src + dev->accel.cx, mix_dat);
mix_dat = ((mix_dat & rd_mask) == rd_mask);
mix_dat = mix_dat ? mix_mask : 0;
}
}
switch ((mix_dat & mix_mask) ? frgd_mix : bkgd_mix) {
case 0:
src_dat = bkgd_color;
break;
case 1:
src_dat = frgd_color;
break;
case 2:
src_dat = cpu_dat;
break;
case 3:
READ(dev->accel.src + dev->accel.cx, src_dat);
if (pixcntl == 3) {
if (dev->accel.cmd & 0x10) {
src_dat = ((src_dat & rd_mask) == rd_mask);
}
}
break;
default:
break;
}
READ(dev->accel.dest + dev->accel.dx, dest_dat);
if ((compare_mode == 0) || ((compare_mode == 0x10) && (dest_dat >= compare)) || ((compare_mode == 0x18) && (dest_dat < compare)) || ((compare_mode == 0x20) && (dest_dat != compare)) || ((compare_mode == 0x28) && (dest_dat == compare)) || ((compare_mode == 0x30) && (dest_dat <= compare)) || ((compare_mode == 0x38) && (dest_dat > compare))) {
old_dest_dat = dest_dat;
MIX(mix_dat & mix_mask, dest_dat, src_dat);
dest_dat = (dest_dat & wrt_mask) | (old_dest_dat & ~wrt_mask);
WRITE(dev->accel.dest + dev->accel.dx, dest_dat);
}
}
mix_dat <<= 1;
mix_dat |= 1;
if (dev->bpp)
cpu_dat >>= 16;
else
cpu_dat >>= 8;
if (dev->accel.cmd & 0x20) {
dev->accel.dx++;
dev->accel.cx++;
} else {
dev->accel.dx--;
dev->accel.cx--;
}
dev->accel.sx--;
if (dev->accel.sx < 0) {
dev->accel.sx = dev->accel.maj_axis_pcnt & 0x7ff;
if (dev->accel.cmd & 0x20) {
dev->accel.dx -= (dev->accel.sx) + 1;
dev->accel.cx -= (dev->accel.sx) + 1;
} else {
dev->accel.dx += (dev->accel.sx) + 1;
dev->accel.cx += (dev->accel.sx) + 1;
}
if (dev->accel.cmd & 0x80) {
dev->accel.dy++;
dev->accel.cy++;
} else {
dev->accel.dy--;
dev->accel.cy--;
}
dev->accel.dest = dev->accel.dy * dev->pitch;
dev->accel.src = dev->accel.cy * dev->pitch;
dev->accel.sy--;
return;
}
}
}
} else {
bitblt:
if (pixcntl == 1) {
if (dev->accel.cmd & 0x40) {
count = dev->accel.maj_axis_pcnt + 1;
dev->accel.temp_cnt = 8;
while (count-- && dev->accel.sy >= 0) {
if (!dev->accel.temp_cnt) {
mix_dat >>= 8;
dev->accel.temp_cnt = 8;
}
if (dev->accel.dx >= dev->accel.clip_left && dev->accel.dx <= clip_r && dev->accel.dy >= dev->accel.clip_top && dev->accel.dy <= clip_b) {
switch ((mix_dat & mix_mask) ? frgd_mix : bkgd_mix) {
case 0:
src_dat = bkgd_color;
break;
case 1:
src_dat = frgd_color;
break;
case 2:
src_dat = 0;
break;
case 3:
READ(dev->accel.src + dev->accel.cx, src_dat);
break;
default:
break;
}
READ(dev->accel.dest + dev->accel.dx, dest_dat);
if ((compare_mode == 0) || ((compare_mode == 0x10) && (dest_dat >= compare)) || ((compare_mode == 0x18) && (dest_dat < compare)) || ((compare_mode == 0x20) && (dest_dat != compare)) || ((compare_mode == 0x28) && (dest_dat == compare)) || ((compare_mode == 0x30) && (dest_dat <= compare)) || ((compare_mode == 0x38) && (dest_dat > compare))) {
old_dest_dat = dest_dat;
MIX(mix_dat & mix_mask, dest_dat, src_dat);
dest_dat = (dest_dat & wrt_mask) | (old_dest_dat & ~wrt_mask);
WRITE(dev->accel.dest + dev->accel.dx, dest_dat);
}
}
if (dev->accel.temp_cnt > 0) {
dev->accel.temp_cnt--;
mix_dat <<= 1;
mix_dat |= 1;
}
if (dev->accel.cmd & 0x20) {
dev->accel.dx++;
dev->accel.cx++;
} else {
dev->accel.dx--;
dev->accel.cx--;
}
dev->accel.sx--;
if (dev->accel.sx < 0) {
dev->accel.sx = dev->accel.maj_axis_pcnt & 0x7ff;
if (dev->accel.cmd & 0x20) {
dev->accel.dx -= (dev->accel.sx) + 1;
dev->accel.cx -= (dev->accel.sx) + 1;
} else {
dev->accel.dx += (dev->accel.sx) + 1;
dev->accel.cx += (dev->accel.sx) + 1;
}
if (dev->accel.cmd & 0x80) {
dev->accel.dy++;
dev->accel.cy++;
} else {
dev->accel.dy--;
dev->accel.cy--;
}
dev->accel.dest = dev->accel.dy * dev->pitch;
dev->accel.src = dev->accel.cy * dev->pitch;
dev->accel.sy--;
return;
}
}
} else {
dev->accel.temp_cnt = 8;
while (count-- && dev->accel.sy >= 0) {
if (!dev->accel.temp_cnt) {
dev->accel.temp_cnt = 8;
mix_dat = old_mix_dat;
}
if (dev->accel.dx >= dev->accel.clip_left && dev->accel.dx <= clip_r && dev->accel.dy >= dev->accel.clip_top && dev->accel.dy <= clip_b) {
switch ((mix_dat & 1) ? frgd_mix : bkgd_mix) {
case 0:
src_dat = bkgd_color;
break;
case 1:
src_dat = frgd_color;
break;
case 2:
src_dat = 0;
break;
case 3:
READ(dev->accel.src + dev->accel.cx, src_dat);
break;
default:
break;
}
READ(dev->accel.dest + dev->accel.dx, dest_dat);
if ((compare_mode == 0) || ((compare_mode == 0x10) && (dest_dat >= compare)) || ((compare_mode == 0x18) && (dest_dat < compare)) || ((compare_mode == 0x20) && (dest_dat != compare)) || ((compare_mode == 0x28) && (dest_dat == compare)) || ((compare_mode == 0x30) && (dest_dat <= compare)) || ((compare_mode == 0x38) && (dest_dat > compare))) {
old_dest_dat = dest_dat;
MIX(mix_dat & 1, dest_dat, src_dat);
dest_dat = (dest_dat & wrt_mask) | (old_dest_dat & ~wrt_mask);
WRITE(dev->accel.dest + dev->accel.dx, dest_dat);
}
}
dev->accel.temp_cnt--;
mix_dat >>= 1;
if (dev->accel.cmd & 0x20) {
dev->accel.dx++;
dev->accel.cx++;
} else {
dev->accel.dx--;
dev->accel.cx--;
}
dev->accel.sx--;
if (dev->accel.sx < 0) {
dev->accel.sx = dev->accel.maj_axis_pcnt & 0x7ff;
if (dev->accel.cmd & 0x20) {
dev->accel.dx -= (dev->accel.sx) + 1;
dev->accel.cx -= (dev->accel.sx) + 1;
} else {
dev->accel.dx += (dev->accel.sx) + 1;
dev->accel.cx += (dev->accel.sx) + 1;
}
if (dev->accel.cmd & 0x80) {
dev->accel.dy++;
dev->accel.cy++;
} else {
dev->accel.dy--;
dev->accel.cy--;
}
dev->accel.dest = dev->accel.dy * dev->pitch;
dev->accel.src = dev->accel.cy * dev->pitch;
dev->accel.sy--;
if (dev->accel.sy < 0) {
return;
}
}
}
}
} else {
if ((dev->accel_bpp == 24) && ((dev->local & 0xff) >= 0x02) && (dev->accel.cmd == 0xc2b5)) {
int64_t cx;
int64_t dx;
cx = (int64_t) dev->accel.cx;
dx = (int64_t) dev->accel.dx;
while (1) {
if ((dx >= (((int64_t)dev->accel.clip_left) * 3)) && (dx <= (((uint64_t)clip_r) * 3)) &&
(dev->accel.dy >= (dev->accel.clip_top << 1)) && (dev->accel.dy <= (clip_b << 1))) {
READ(dev->accel.src + (dev->accel.ge_offset << 2) + cx, src_dat);
READ(dev->accel.dest + (dev->accel.ge_offset << 2) + dx, dest_dat);
dest_dat = (src_dat & wrt_mask) | (dest_dat & ~wrt_mask);
WRITE(dev->accel.dest + (dev->accel.ge_offset << 2) + dx, dest_dat);
}
cx++;
dx++;
dev->accel.sx--;
if (dev->accel.sx < 0)
return;
}
return;
}
ibm8514_log("BitBLT 8514/A=%04x, selfrmix=%d, selbkmix=%d, d(%d,%d), c(%d,%d), pixcntl=%d, sy=%d, frgdmix=%02x, bkgdmix=%02x, rdmask=%02x, wrtmask=%02x, linedraw=%d.\n", dev->accel.cmd, frgd_mix, bkgd_mix, dev->accel.dx, dev->accel.dy, dev->accel.cx, dev->accel.cy, pixcntl, dev->accel.sy, dev->accel.frgd_mix & 0x1f, dev->accel.bkgd_mix & 0x1f, dev->accel.rd_mask, wrt_mask, dev->accel.linedraw);
while (count-- && dev->accel.sy >= 0) {
if ((dev->accel.dx >= dev->accel.clip_left) && (dev->accel.dx <= clip_r) &&
(dev->accel.dy >= dev->accel.clip_top) && (dev->accel.dy <= clip_b)) {
if (pixcntl == 3) {
if (!(dev->accel.cmd & 0x10) && ((frgd_mix != 3) || (bkgd_mix != 3))) {
READ(dev->accel.src + dev->accel.cx, mix_dat);
mix_dat = ((mix_dat & rd_mask) == rd_mask);
mix_dat = mix_dat ? mix_mask : 0;
} else if (dev->accel.cmd & 0x10) {
READ(dev->accel.src + dev->accel.cx, mix_dat);
mix_dat = ((mix_dat & rd_mask) == rd_mask);
mix_dat = mix_dat ? mix_mask : 0;
}
}
switch ((mix_dat & mix_mask) ? frgd_mix : bkgd_mix) {
case 0:
src_dat = bkgd_color;
break;
case 1:
src_dat = frgd_color;
break;
case 2:
src_dat = 0;
break;
case 3:
READ(dev->accel.src + dev->accel.cx, src_dat);
if (pixcntl == 3) {
if ((dev->accel.cmd & 0x10) && !(dev->accel.cmd & 0x40)) {
src_dat = ((src_dat & rd_mask) == rd_mask);
}
}
break;
default:
break;
}
READ(dev->accel.dest + dev->accel.dx, dest_dat);
if ((compare_mode == 0) || ((compare_mode == 0x10) && (dest_dat >= compare)) || ((compare_mode == 0x18) && (dest_dat < compare)) || ((compare_mode == 0x20) && (dest_dat != compare)) || ((compare_mode == 0x28) && (dest_dat == compare)) || ((compare_mode == 0x30) && (dest_dat <= compare)) || ((compare_mode == 0x38) && (dest_dat > compare))) {
old_dest_dat = dest_dat;
MIX(mix_dat & mix_mask, dest_dat, src_dat);
dest_dat = (dest_dat & wrt_mask) | (old_dest_dat & ~wrt_mask);
if (dev->accel.cmd & 4) {
if (dev->accel.sx > 0) {
WRITE(dev->accel.dest + dev->accel.dx, dest_dat);
}
} else {
WRITE(dev->accel.dest + dev->accel.dx, dest_dat);
}
}
}
mix_dat <<= 1;
mix_dat |= 1;
if (dev->accel.cmd & 0x20) {
dev->accel.dx++;
dev->accel.cx++;
} else {
dev->accel.dx--;
dev->accel.cx--;
}
dev->accel.sx--;
if (dev->accel.sx < 0) {
dev->accel.fill_state = 0;
dev->accel.sx = dev->accel.maj_axis_pcnt & 0x7ff;
dev->accel.dx = dev->accel.destx;
if (dev->accel.destx >= 0x600)
dev->accel.dx |= ~0x5ff;
dev->accel.cx = dev->accel.cur_x;
if (dev->accel.cur_x >= 0x600)
dev->accel.cx |= ~0x5ff;
if (dev->accel.cmd & 0x80) {
dev->accel.dy++;
dev->accel.cy++;
} else {
dev->accel.dy--;
dev->accel.cy--;
}
dev->accel.dest = dev->accel.dy * dev->pitch;
dev->accel.src = dev->accel.cy * dev->pitch;
dev->accel.sy--;
if (dev->accel.sy < 0)
return;
}
}
}
}
}
break;
default:
break;
}
}
void
ibm8514_render_blank(svga_t *svga)
{
ibm8514_t *dev = (ibm8514_t *) svga->dev8514;
if ((dev->displine + svga->y_add) < 0)
return;
if (dev->firstline_draw == 2000)
dev->firstline_draw = dev->displine;
dev->lastline_draw = dev->displine;
uint32_t *line_ptr = &svga->monitor->target_buffer->line[dev->displine + svga->y_add][svga->x_add];
uint32_t line_width = (uint32_t)(dev->h_disp) * sizeof(uint32_t);
if (dev->h_disp > 0)
memset(line_ptr, 0, line_width);
}
void
ibm8514_render_8bpp(svga_t *svga)
{
ibm8514_t *dev = (ibm8514_t *) svga->dev8514;
uint32_t *p;
uint32_t dat;
if ((dev->displine + svga->y_add) < 0)
return;
if (dev->changedvram[dev->ma >> 12] || dev->changedvram[(dev->ma >> 12) + 1] || svga->fullchange) {
p = &buffer32->line[dev->displine + svga->y_add][svga->x_add];
if (dev->firstline_draw == 2000)
dev->firstline_draw = dev->displine;
dev->lastline_draw = dev->displine;
for (int x = 0; x <= dev->h_disp; x += 8) {
dat = *(uint32_t *) (&dev->vram[dev->ma & dev->vram_mask]);
p[0] = dev->pallook[dat & 0xff];
p[1] = dev->pallook[(dat >> 8) & 0xff];
p[2] = dev->pallook[(dat >> 16) & 0xff];
p[3] = dev->pallook[(dat >> 24) & 0xff];
dat = *(uint32_t *) (&dev->vram[(dev->ma + 4) & dev->vram_mask]);
p[4] = dev->pallook[dat & 0xff];
p[5] = dev->pallook[(dat >> 8) & 0xff];
p[6] = dev->pallook[(dat >> 16) & 0xff];
p[7] = dev->pallook[(dat >> 24) & 0xff];
dev->ma += 8;
p += 8;
}
dev->ma &= dev->vram_mask;
}
}
void
ibm8514_render_15bpp(svga_t *svga)
{
ibm8514_t *dev = (ibm8514_t *) svga->dev8514;
int x;
uint32_t *p;
uint32_t dat;
if ((dev->displine + svga->y_add) < 0) {
return;
}
if (dev->changedvram[dev->ma >> 12] || dev->changedvram[(dev->ma >> 12) + 1] || svga->fullchange) {
p = &buffer32->line[dev->displine + svga->y_add][svga->x_add];
if (dev->firstline_draw == 2000)
dev->firstline_draw = dev->displine;
dev->lastline_draw = dev->displine;
for (x = 0; x <= dev->h_disp; x += 8) {
dat = *(uint32_t *) (&dev->vram[(dev->ma + (x << 1)) & dev->vram_mask]);
p[x] = video_15to32[dat & 0xffff];
p[x + 1] = video_15to32[dat >> 16];
dat = *(uint32_t *) (&dev->vram[(dev->ma + (x << 1) + 4) & dev->vram_mask]);
p[x + 2] = video_15to32[dat & 0xffff];
p[x + 3] = video_15to32[dat >> 16];
dat = *(uint32_t *) (&dev->vram[(dev->ma + (x << 1) + 8) & dev->vram_mask]);
p[x + 4] = video_15to32[dat & 0xffff];
p[x + 5] = video_15to32[dat >> 16];
dat = *(uint32_t *) (&dev->vram[(dev->ma + (x << 1) + 12) & dev->vram_mask]);
p[x + 6] = video_15to32[dat & 0xffff];
p[x + 7] = video_15to32[dat >> 16];
}
dev->ma += (x << 1);
dev->ma &= dev->vram_mask;
}
}
void
ibm8514_render_16bpp(svga_t *svga)
{
ibm8514_t *dev = (ibm8514_t *) svga->dev8514;
int x;
uint32_t *p;
uint32_t dat;
if ((dev->displine + svga->y_add) < 0) {
return;
}
if (dev->changedvram[dev->ma >> 12] || dev->changedvram[(dev->ma >> 12) + 1] || svga->fullchange) {
p = &buffer32->line[dev->displine + svga->y_add][svga->x_add];
if (dev->firstline_draw == 2000)
dev->firstline_draw = dev->displine;
dev->lastline_draw = dev->displine;
for (x = 0; x <= dev->h_disp; x += 8) {
dat = *(uint32_t *) (&dev->vram[(dev->ma + (x << 1)) & dev->vram_mask]);
p[x] = video_16to32[dat & 0xffff];
p[x + 1] = video_16to32[dat >> 16];
dat = *(uint32_t *) (&dev->vram[(dev->ma + (x << 1) + 4) & dev->vram_mask]);
p[x + 2] = video_16to32[dat & 0xffff];
p[x + 3] = video_16to32[dat >> 16];
dat = *(uint32_t *) (&dev->vram[(dev->ma + (x << 1) + 8) & dev->vram_mask]);
p[x + 4] = video_16to32[dat & 0xffff];
p[x + 5] = video_16to32[dat >> 16];
dat = *(uint32_t *) (&dev->vram[(dev->ma + (x << 1) + 12) & dev->vram_mask]);
p[x + 6] = video_16to32[dat & 0xffff];
p[x + 7] = video_16to32[dat >> 16];
}
dev->ma += (x << 1);
dev->ma &= dev->vram_mask;
}
}
void
ibm8514_render_24bpp(svga_t *svga)
{
ibm8514_t *dev = (ibm8514_t *) svga->dev8514;
uint32_t *p;
uint32_t dat;
if ((dev->displine + svga->y_add) < 0)
return;
if (dev->changedvram[dev->ma >> 12] || dev->changedvram[(dev->ma >> 12) + 1] || svga->fullchange) {
p = &buffer32->line[dev->displine + svga->y_add][svga->x_add];
if (dev->firstline_draw == 2000)
dev->firstline_draw = dev->displine;
dev->lastline_draw = dev->displine;
for (int x = 0; x <= dev->h_disp; x += 4) {
dat = *(uint32_t *) (&dev->vram[dev->ma & dev->vram_mask]);
p[x] = dat & 0xffffff;
dat = *(uint32_t *) (&dev->vram[(dev->ma + 3) & dev->vram_mask]);
p[x + 1] = dat & 0xffffff;
dat = *(uint32_t *) (&dev->vram[(dev->ma + 6) & dev->vram_mask]);
p[x + 2] = dat & 0xffffff;
dat = *(uint32_t *) (&dev->vram[(dev->ma + 9) & dev->vram_mask]);
p[x + 3] = dat & 0xffffff;
dev->ma += 12;
}
dev->ma &= dev->vram_mask;
}
}
void
ibm8514_render_BGR(svga_t *svga)
{
ibm8514_t *dev = (ibm8514_t *) svga->dev8514;
uint32_t *p;
uint32_t dat;
if ((dev->displine + svga->y_add) < 0)
return;
if (dev->changedvram[dev->ma >> 12] || dev->changedvram[(dev->ma >> 12) + 1] || svga->fullchange) {
p = &buffer32->line[dev->displine + svga->y_add][svga->x_add];
if (dev->firstline_draw == 2000)
dev->firstline_draw = dev->displine;
dev->lastline_draw = dev->displine;
for (int x = 0; x <= dev->h_disp; x += 4) {
dat = *(uint32_t *) (&dev->vram[dev->ma & dev->vram_mask]);
p[x] = ((dat & 0xff0000) >> 16) | (dat & 0x00ff00) | ((dat & 0x0000ff) << 16);
dat = *(uint32_t *) (&dev->vram[(dev->ma + 3) & dev->vram_mask]);
p[x + 1] = ((dat & 0xff0000) >> 16) | (dat & 0x00ff00) | ((dat & 0x0000ff) << 16);
dat = *(uint32_t *) (&dev->vram[(dev->ma + 6) & dev->vram_mask]);
p[x + 2] = ((dat & 0xff0000) >> 16) | (dat & 0x00ff00) | ((dat & 0x0000ff) << 16);
dat = *(uint32_t *) (&dev->vram[(dev->ma + 9) & dev->vram_mask]);
p[x + 3] = ((dat & 0xff0000) >> 16) | (dat & 0x00ff00) | ((dat & 0x0000ff) << 16);
dev->ma += 12;
}
dev->ma &= dev->vram_mask;
}
}
void
ibm8514_render_ABGR8888(svga_t *svga)
{
ibm8514_t *dev = (ibm8514_t *) svga->dev8514;
int x;
uint32_t *p;
uint32_t dat;
if ((dev->displine + svga->y_add) < 0)
return;
if (dev->changedvram[dev->ma >> 12] || dev->changedvram[(dev->ma >> 12) + 1] || svga->fullchange) {
p = &buffer32->line[dev->displine + svga->y_add][svga->x_add];
if (dev->firstline_draw == 2000)
dev->firstline_draw = dev->displine;
dev->lastline_draw = dev->displine;
for (x = 0; x <= dev->h_disp; x++) {
dat = *(uint32_t *) (&dev->vram[(dev->ma + (x << 2)) & dev->vram_mask]);
*p++ = ((dat & 0xff0000) >> 16) | (dat & 0x00ff00) | ((dat & 0x0000ff) << 16);
}
dev->ma += (x * 4);
dev->ma &= dev->vram_mask;
}
}
void
ibm8514_render_32bpp(svga_t *svga)
{
ibm8514_t *dev = (ibm8514_t *) svga->dev8514;
int x;
uint32_t *p;
uint32_t dat;
if ((dev->displine + svga->y_add) < 0)
return;
if (dev->changedvram[dev->ma >> 12] || dev->changedvram[(dev->ma >> 12) + 1] || dev->changedvram[(dev->ma >> 12) + 2] || svga->fullchange) {
p = &buffer32->line[dev->displine + svga->y_add][svga->x_add];
if (dev->firstline_draw == 2000)
dev->firstline_draw = dev->displine;
dev->lastline_draw = dev->displine;
for (x = 0; x <= dev->h_disp; x++) {
dat = *(uint32_t *) (&dev->vram[(dev->ma + (x << 2)) & dev->vram_mask]);
p[x] = dat & 0xffffff;
}
dev->ma += (x * 4);
dev->ma &= dev->vram_mask;
}
}
static void
ibm8514_render_overscan_left(ibm8514_t *dev, svga_t *svga)
{
if ((dev->displine + svga->y_add) < 0)
return;
if (svga->scrblank || (dev->h_disp == 0))
return;
for (int i = 0; i < svga->x_add; i++)
buffer32->line[dev->displine + svga->y_add][i] = svga->overscan_color;
}
static void
ibm8514_render_overscan_right(ibm8514_t *dev, svga_t *svga)
{
int right;
if ((dev->displine + svga->y_add) < 0)
return;
if (svga->scrblank || (dev->h_disp == 0))
return;
right = (overscan_x >> 1);
for (int i = 0; i < right; i++)
buffer32->line[dev->displine + svga->y_add][svga->x_add + dev->h_disp + i] = svga->overscan_color;
}
void
ibm8514_poll(void *priv)
{
svga_t *svga = (svga_t *)priv;
ibm8514_t *dev = (ibm8514_t *)svga->dev8514;
uint32_t x;
int wx;
int wy;
ibm8514_log("IBM 8514/A poll.\n");
if (dev->on[0] || dev->on[1]) {
ibm8514_log("ON!\n");
if (!dev->linepos) {
if ((dev->displine == dev->hwcursor_latch.y) && dev->hwcursor_latch.ena) {
dev->hwcursor_on = dev->hwcursor_latch.cur_ysize - dev->hwcursor_latch.yoff;
dev->hwcursor_oddeven = 0;
}
if ((dev->displine == (dev->hwcursor_latch.y + 1)) && dev->hwcursor_latch.ena && dev->interlace) {
dev->hwcursor_on = dev->hwcursor_latch.cur_ysize - (dev->hwcursor_latch.yoff + 1);
dev->hwcursor_oddeven = 1;
}
timer_advance_u64(&svga->timer, dev->dispofftime);
svga->cgastat |= 1;
dev->linepos = 1;
if (dev->dispon) {
dev->hdisp_on = 1;
dev->ma &= dev->vram_mask;
if (dev->firstline == 2000) {
dev->firstline = dev->displine;
video_wait_for_buffer_monitor(svga->monitor_index);
}
if (dev->hwcursor_on)
dev->changedvram[dev->ma >> 12] = dev->changedvram[(dev->ma >> 12) + 1] = dev->interlace ? 3 : 2;
svga->render8514(svga);
svga->x_add = (overscan_x >> 1);
ibm8514_render_overscan_left(dev, svga);
ibm8514_render_overscan_right(dev, svga);
svga->x_add = (overscan_x >> 1);
if (dev->hwcursor_on) {
if (svga->hwcursor_draw)
svga->hwcursor_draw(svga, dev->displine + svga->y_add);
dev->hwcursor_on--;
if (dev->hwcursor_on && dev->interlace)
dev->hwcursor_on--;
}
if (dev->lastline < dev->displine)
dev->lastline = dev->displine;
}
dev->displine++;
if (dev->interlace)
dev->displine++;
if ((svga->cgastat & 8) && ((dev->displine & 0x0f) == (svga->crtc[0x11] & 0x0f)) && svga->vslines)
svga->cgastat &= ~8;
svga->vslines++;
if (dev->displine > 1500)
dev->displine = 0;
} else {
timer_advance_u64(&svga->timer, dev->dispontime);
if (dev->dispon)
svga->cgastat &= ~1;
dev->hdisp_on = 0;
dev->linepos = 0;
if (dev->dispon) {
if (dev->sc == dev->rowcount) {
dev->sc = 0;
dev->maback += (dev->rowoffset << 3);
if (dev->interlace)
dev->maback += (dev->rowoffset << 3);
dev->maback &= dev->vram_mask;
dev->ma = dev->maback;
} else {
dev->sc++;
dev->sc &= 0x1f;
dev->ma = dev->maback;
}
}
dev->vc++;
dev->vc &= 0xfff;
if (dev->vc == dev->dispend) {
dev->dispon = 0;
for (x = 0; x < ((dev->vram_mask + 1) >> 12); x++) {
if (dev->changedvram[x])
dev->changedvram[x]--;
}
if (svga->fullchange)
svga->fullchange--;
}
if (dev->vc == dev->v_syncstart) {
dev->dispon = 0;
svga->cgastat |= 8;
x = dev->h_disp;
if (dev->interlace && !dev->oddeven)
dev->lastline++;
if (dev->interlace && dev->oddeven)
dev->firstline--;
wx = x;
wy = dev->lastline - dev->firstline;
svga_doblit(wx, wy, svga);
dev->firstline = 2000;
dev->lastline = 0;
dev->firstline_draw = 2000;
dev->lastline_draw = 0;
dev->oddeven ^= 1;
svga->monitor->mon_changeframecount = dev->interlace ? 3 : 2;
svga->vslines = 0;
if (dev->interlace && dev->oddeven)
dev->ma = dev->maback = (dev->rowoffset << 1);
else
dev->ma = dev->maback = 0;
dev->ma = (dev->ma << 2);
dev->maback = (dev->maback << 2);
}
if (dev->vc == dev->v_total) {
dev->vc = 0;
dev->sc = 0;
dev->dispon = 1;
dev->displine = (dev->interlace && dev->oddeven) ? 1 : 0;
svga->x_add = (overscan_x >> 1);
dev->hwcursor_on = 0;
dev->hwcursor_latch = dev->hwcursor;
}
}
}
}
void
ibm8514_recalctimings(svga_t *svga)
{
ibm8514_t *dev = (ibm8514_t *) svga->dev8514;
svga->render8514 = ibm8514_render_blank;
#ifdef ATI_8514_ULTRA
if (dev->extensions) {
if (svga->ext8514 != NULL)
ati8514_recalctimings(svga);
} else
#endif
{
if (dev->on[0]) {
dev->h_total = dev->htotal + 1;
dev->rowcount = !!(dev->disp_cntl & 0x08);
if (dev->accel.advfunc_cntl & 0x01) {
if (dev->accel.advfunc_cntl & 0x04) {
dev->h_disp = dev->hdisp;
dev->dispend = dev->vdisp;
} else {
dev->h_disp = 640;
dev->dispend = 480;
}
} else {
dev->h_disp = dev->hdisp;
dev->dispend = dev->vdisp;
}
if (dev->accel.advfunc_cntl & 0x04)
svga->clock8514 = (cpuclock * (double) (1ULL << 32)) / 44900000.0;
else
svga->clock8514 = (cpuclock * (double) (1ULL << 32)) / 25175000.0;
if (dev->interlace)
dev->dispend >>= 1;
if (dev->dispend == 766)
dev->dispend += 2;
if (dev->dispend == 478)
dev->dispend += 2;
dev->pitch = 1024;
dev->rowoffset = 0x80;
svga->map8 = dev->pallook;
svga->render8514 = ibm8514_render_8bpp;
ibm8514_log("BPP=%d, Pitch = %d, rowoffset = %d, crtc13 = %02x, highres bit = %02x, has_vga? = %d.\n", dev->bpp, dev->pitch, dev->rowoffset, svga->crtc[0x13], dev->accel.advfunc_cntl & 4, !ibm8514_standalone_enabled);
}
}
ibm8514_log("8514 enabled, hdisp=%d, vtotal=%d, htotal=%d, dispend=%d, rowoffset=%d, split=%d, vsyncstart=%d, split=%08x\n", dev->hdisp, dev->vtotal, dev->htotal, dev->dispend, dev->rowoffset, dev->split, dev->vsyncstart, dev->split);
}
static uint8_t
ibm8514_mca_read(int port, void *priv)
{
const svga_t *svga = (svga_t *) priv;
const ibm8514_t *dev = (ibm8514_t *) svga->dev8514;
return (dev->pos_regs[port & 7]);
}
static void
ibm8514_mca_write(int port, uint8_t val, void *priv)
{
svga_t *svga = (svga_t *) priv;
ibm8514_t *dev = (ibm8514_t *) svga->dev8514;
/* MCA does not write registers below 0x0100. */
if (port < 0x0102)
return;
/* Save the MCA register value. */
dev->pos_regs[port & 7] = val;
}
static uint8_t
ibm8514_mca_feedb(void *priv)
{
const svga_t *svga = (svga_t *) priv;
const ibm8514_t *dev = (ibm8514_t *) svga->dev8514;
return dev->pos_regs[2] & 1;
}
static void
ibm8514_mca_reset(void *priv)
{
svga_t *svga = (svga_t *) priv;
ibm8514_t *dev = (ibm8514_t *) svga->dev8514;
ibm8514_log("MCA reset.\n");
dev->on[0] = 0;
dev->on[1] = 0;
vga_on = 1;
#ifdef ATI_8514_ULTRA
if (dev->extensions)
ati8514_mca_write(0x102, 0, svga);
else
#endif
ibm8514_mca_write(0x102, 0, svga);
}
static void *
ibm8514_init(const device_t *info)
{
if (svga_get_pri() == NULL)
return NULL;
svga_t *svga = svga_get_pri();
ibm8514_t *dev = (ibm8514_t *) calloc(1, sizeof(ibm8514_t));
svga->dev8514 = dev;
svga->ext8514 = NULL;
dev->vram_size = 1024 << 10;
dev->vram = calloc(dev->vram_size, 1);
dev->changedvram = calloc((dev->vram_size >> 12) + 1, 1);
dev->vram_mask = dev->vram_size - 1;
dev->map8 = dev->pallook;
dev->local = 0;
dev->type = info->flags;
dev->bpp = 0;
#ifdef ATI_8514_ULTRA
dev->extensions = device_get_config_int("extensions");
switch (dev->extensions) {
case 1:
if (rom_present(BIOS_MACH8_ROM_PATH)) {
mach_t * mach = (mach_t *) calloc(1, sizeof(mach_t));
svga->ext8514 = mach;
if (dev->type & DEVICE_MCA) {
rom_init(&dev->bios_rom,
BIOS_MACH8_ROM_PATH,
0xc6000, 0x2000, 0x1fff,
0, MEM_MAPPING_EXTERNAL);
dev->pos_regs[0] = 0x88;
dev->pos_regs[1] = 0x80;
mca_add(ati8514_mca_read, ati8514_mca_write, ibm8514_mca_feedb, ibm8514_mca_reset, svga);
ati_eeprom_load(&mach->eeprom, "ati8514_mca.nvr", 0);
mem_mapping_disable(&dev->bios_rom.mapping);
} else {
rom_init(&dev->bios_rom,
BIOS_MACH8_ROM_PATH,
0xd0000, 0x2000, 0x1fff,
0, MEM_MAPPING_EXTERNAL);
ati_eeprom_load(&mach->eeprom, "ati8514.nvr", 0);
dev->bios_addr = dev->bios_rom.mapping.base;
}
ati8514_init(svga, svga->ext8514, svga->dev8514);
break;
}
fallthrough;
default:
ibm8514_io_set(svga);
if (dev->type & DEVICE_MCA) {
dev->pos_regs[0] = 0x7f;
dev->pos_regs[1] = 0xef;
mca_add(ibm8514_mca_read, ibm8514_mca_write, ibm8514_mca_feedb, ibm8514_mca_reset, svga);
}
break;
}
#else
ibm8514_io_set(svga);
if (dev->type & DEVICE_MCA) {
dev->pos_regs[0] = 0x7f;
dev->pos_regs[1] = 0xef;
mca_add(ibm8514_mca_read, ibm8514_mca_write, ibm8514_mca_feedb, ibm8514_mca_reset, svga);
}
#endif
return svga;
}
static void
ibm8514_close(void *priv)
{
svga_t *svga = (svga_t *) priv;
ibm8514_t *dev = (ibm8514_t *) svga->dev8514;
#ifdef ATI_8514_ULTRA
mach_t *mach = (mach_t *) svga->ext8514;
if (mach)
free(mach);
#endif
if (dev) {
free(dev->vram);
free(dev->changedvram);
free(dev);
}
}
static void
ibm8514_speed_changed(void *priv)
{
svga_t *svga = (svga_t *) priv;
svga_recalctimings(svga);
}
static void
ibm8514_force_redraw(void *priv)
{
svga_t *svga = (svga_t *) priv;
svga->fullchange = changeframecount;
}
#ifdef ATI_8514_ULTRA
// clang-format off
static const device_config_t ext8514_config[] = {
{
.name = "extensions",
.description = "Vendor",
.type = CONFIG_SELECTION,
.default_int = 0,
.selection = {
{
.description = "IBM",
.value = 0
},
{
.description = "ATI",
.value = 1
},
{
.description = ""
}
}
},
{
.type = CONFIG_END
}
};
#endif
// clang-format off
const device_t gen8514_isa_device = {
.name = "IBM 8514/A clone (ISA)",
.internal_name = "8514_isa",
.flags = DEVICE_AT | DEVICE_ISA,
.local = 0,
.init = ibm8514_init,
.close = ibm8514_close,
.reset = NULL,
{ .available = NULL },
.speed_changed = ibm8514_speed_changed,
.force_redraw = ibm8514_force_redraw,
#ifdef ATI_8514_ULTRA
.config = ext8514_config
#else
.config = NULL
#endif
};
const device_t ibm8514_mca_device = {
.name = "IBM 8514/A (MCA)",
.internal_name = "8514_mca",
.flags = DEVICE_MCA,
.local = 0,
.init = ibm8514_init,
.close = ibm8514_close,
.reset = NULL,
{ .available = NULL },
.speed_changed = ibm8514_speed_changed,
.force_redraw = ibm8514_force_redraw,
#ifdef ATI_8514_ULTRA
.config = ext8514_config
#else
.config = NULL
#endif
};
void
ibm8514_device_add(void)
{
if (!ibm8514_standalone_enabled)
return;
if (machine_has_bus(machine, MACHINE_BUS_MCA))
device_add(&ibm8514_mca_device);
else
device_add(&gen8514_isa_device);
}
``` | /content/code_sandbox/src/video/vid_8514a.c | c | 2016-06-25T22:29:10 | 2024-08-16T19:09:21 | 86Box | 86Box/86Box | 2,616 | 47,872 |
```c
/*
* 86Box A hypervisor and IBM PC system emulator that specializes in
* running old operating systems and software designed for IBM
* PC systems and compatibles from 1981 through fairly recent
* system designs based on the PCI bus.
*
* This file is part of the 86Box distribution.
*
* Paradise VGA emulation
* PC2086, PC3086 use PVGA1A
* MegaPC uses W90C11A
*
*
*
* Authors: Sarah Walker, <path_to_url
* Miran Grca, <mgrca8@gmail.com>
*
*/
#include <stdio.h>
#include <stdint.h>
#include <string.h>
#include <stdlib.h>
#include <wchar.h>
#include <86box/86box.h>
#include <86box/io.h>
#include <86box/timer.h>
#include <86box/mem.h>
#include <86box/rom.h>
#include <86box/device.h>
#include <86box/video.h>
#include <86box/vid_svga.h>
#include <86box/vid_svga_render.h>
typedef struct paradise_t {
svga_t svga;
rom_t bios_rom;
enum {
PVGA1A = 0,
WD90C11,
WD90C30
} type;
uint32_t vram_mask;
uint32_t memory;
uint32_t read_bank[4], write_bank[4];
int interlace;
struct {
uint8_t reg_block_ptr;
uint8_t reg_idx;
uint8_t disable_autoinc;
uint16_t int_status;
uint16_t blt_ctrl1, blt_ctrl2;
uint16_t srclow, srchigh;
uint16_t dstlow, dsthigh;
uint32_t srcaddr, dstaddr;
int invalid_block;
} accel;
} paradise_t;
static video_timings_t timing_paradise_pvga1a = { .type = VIDEO_ISA, .write_b = 6, .write_w = 8, .write_l = 16, .read_b = 6, .read_w = 8, .read_l = 16 };
static video_timings_t timing_paradise_wd90c = { .type = VIDEO_ISA, .write_b = 3, .write_w = 3, .write_l = 6, .read_b = 5, .read_w = 5, .read_l = 10 };
void paradise_remap(paradise_t *paradise);
uint8_t
paradise_in(uint16_t addr, void *priv)
{
paradise_t *paradise = (paradise_t *) priv;
svga_t *svga = ¶dise->svga;
if (((addr & 0xfff0) == 0x3d0 || (addr & 0xfff0) == 0x3b0) && !(svga->miscout & 1))
addr ^= 0x60;
switch (addr) {
case 0x3c5:
if (svga->seqaddr > 7) {
if (paradise->type < WD90C11 || svga->seqregs[6] != 0x48)
return 0xff;
if (svga->seqaddr > 0x12)
return 0xff;
return svga->seqregs[svga->seqaddr & 0x1f];
}
break;
case 0x3c6:
case 0x3c7:
case 0x3c8:
case 0x3c9:
if (paradise->type == WD90C30)
return sc1148x_ramdac_in(addr, 0, svga->ramdac, svga);
return svga_in(addr, svga);
case 0x3cf:
if (svga->gdcaddr >= 9 && svga->gdcaddr <= 0x0e) {
if (svga->gdcreg[0x0f] & 0x10)
return 0xff;
}
switch (svga->gdcaddr) {
case 0x0f:
return (svga->gdcreg[0x0f] & 0x17) | 0x80;
default:
break;
}
break;
case 0x3D4:
return svga->crtcreg;
case 0x3D5:
if ((paradise->type == PVGA1A) && (svga->crtcreg & 0x20))
return 0xff;
if (svga->crtcreg > 0x29 && svga->crtcreg < 0x30 && (svga->crtc[0x29] & 0x88) != 0x80)
return 0xff;
return svga->crtc[svga->crtcreg];
default:
break;
}
return svga_in(addr, svga);
}
void
paradise_out(uint16_t addr, uint8_t val, void *priv)
{
paradise_t *paradise = (paradise_t *) priv;
svga_t *svga = ¶dise->svga;
uint8_t old;
if (((addr & 0xfff0) == 0x3d0 || (addr & 0xfff0) == 0x3b0) && !(svga->miscout & 1))
addr ^= 0x60;
switch (addr) {
case 0x3c5:
if (svga->seqaddr > 7) {
if (paradise->type < WD90C11 || svga->seqregs[6] != 0x48)
return;
svga->seqregs[svga->seqaddr & 0x1f] = val;
if (svga->seqaddr == 0x11) {
paradise_remap(paradise);
}
return;
}
break;
case 0x3c6:
case 0x3c7:
case 0x3c8:
case 0x3c9:
if (paradise->type == WD90C30)
sc1148x_ramdac_out(addr, 0, val, svga->ramdac, svga);
else
svga_out(addr, val, svga);
return;
case 0x3cf:
if (svga->gdcaddr >= 9 && svga->gdcaddr <= 0x0e) {
if ((svga->gdcreg[0x0f] & 7) != 5)
return;
}
switch (svga->gdcaddr) {
case 6:
if ((svga->gdcreg[6] & 0x0c) != (val & 0xc)) {
switch (val & 0x0c) {
case 0x0: /*128k at A0000*/
mem_mapping_set_addr(&svga->mapping, 0xa0000, 0x20000);
svga->banked_mask = 0xffff;
break;
case 0x4: /*64k at A0000*/
mem_mapping_set_addr(&svga->mapping, 0xa0000, 0x10000);
svga->banked_mask = 0xffff;
break;
case 0x8: /*32k at B0000*/
mem_mapping_set_addr(&svga->mapping, 0xb0000, 0x08000);
svga->banked_mask = 0x7fff;
break;
case 0xC: /*32k at B8000*/
mem_mapping_set_addr(&svga->mapping, 0xb8000, 0x08000);
svga->banked_mask = 0x7fff;
break;
default:
break;
}
}
svga->gdcreg[6] = val;
paradise_remap(paradise);
return;
case 9:
case 0x0a:
svga->gdcreg[svga->gdcaddr] = val;
paradise_remap(paradise);
return;
case 0x0b:
svga->gdcreg[0x0b] = val;
paradise_remap(paradise);
return;
case 0x0e:
svga->gdcreg[0x0e] = val;
svga_recalctimings(svga);
return;
default:
break;
}
break;
case 0x3D4:
svga->crtcreg = val & 0x3f;
return;
case 0x3D5:
if ((paradise->type == PVGA1A) && (svga->crtcreg & 0x20))
return;
if ((svga->crtcreg < 7) && (svga->crtc[0x11] & 0x80))
return;
if ((svga->crtcreg == 7) && (svga->crtc[0x11] & 0x80))
val = (svga->crtc[7] & ~0x10) | (val & 0x10);
if (svga->crtcreg > 0x29 && (svga->crtc[0x29] & 7) != 5)
return;
if (svga->crtcreg >= 0x31 && svga->crtcreg <= 0x37)
return;
old = svga->crtc[svga->crtcreg];
svga->crtc[svga->crtcreg] = val;
if (old != val) {
if (svga->crtcreg < 0xe || svga->crtcreg > 0x10) {
if ((svga->crtcreg == 0xc) || (svga->crtcreg == 0xd)) {
svga->fullchange = 3;
svga->ma_latch = ((svga->crtc[0xc] << 8) | svga->crtc[0xd]) + ((svga->crtc[8] & 0x60) >> 5);
} else {
svga->fullchange = changeframecount;
svga_recalctimings(svga);
}
}
}
break;
default:
break;
}
svga_out(addr, val, svga);
}
void
paradise_remap(paradise_t *paradise)
{
svga_t *svga = ¶dise->svga;
if (svga->seqregs[0x11] & 0x80) {
paradise->read_bank[0] = paradise->read_bank[2] = svga->gdcreg[9] << 12;
paradise->read_bank[1] = paradise->read_bank[3] = (svga->gdcreg[9] << 12) + ((svga->gdcreg[6] & 0x08) ? 0 : 0x8000);
paradise->write_bank[0] = paradise->write_bank[2] = svga->gdcreg[0x0a] << 12;
paradise->write_bank[1] = paradise->write_bank[3] = (svga->gdcreg[0x0a] << 12) + ((svga->gdcreg[6] & 0x08) ? 0 : 0x8000);
} else if (svga->gdcreg[0x0b] & 0x08) {
if (svga->gdcreg[6] & 0x0c) {
paradise->read_bank[0] = paradise->read_bank[2] = svga->gdcreg[0x0a] << 12;
paradise->write_bank[0] = paradise->write_bank[2] = svga->gdcreg[0x0a] << 12;
paradise->read_bank[1] = paradise->read_bank[3] = (svga->gdcreg[9] << 12) + ((svga->gdcreg[6] & 0x08) ? 0 : 0x8000);
paradise->write_bank[1] = paradise->write_bank[3] = (svga->gdcreg[9] << 12) + ((svga->gdcreg[6] & 0x08) ? 0 : 0x8000);
} else {
paradise->read_bank[0] = paradise->write_bank[0] = svga->gdcreg[0x0a] << 12;
paradise->read_bank[1] = paradise->write_bank[1] = (svga->gdcreg[0xa] << 12) + ((svga->gdcreg[6] & 0x08) ? 0 : 0x8000);
paradise->read_bank[2] = paradise->write_bank[2] = svga->gdcreg[9] << 12;
paradise->read_bank[3] = paradise->write_bank[3] = (svga->gdcreg[9] << 12) + ((svga->gdcreg[6] & 0x08) ? 0 : 0x8000);
}
} else {
paradise->read_bank[0] = paradise->read_bank[2] = svga->gdcreg[9] << 12;
paradise->read_bank[1] = paradise->read_bank[3] = (svga->gdcreg[9] << 12) + ((svga->gdcreg[6] & 0x08) ? 0 : 0x8000);
paradise->write_bank[0] = paradise->write_bank[2] = svga->gdcreg[9] << 12;
paradise->write_bank[1] = paradise->write_bank[3] = (svga->gdcreg[9] << 12) + ((svga->gdcreg[6] & 0x08) ? 0 : 0x8000);
}
if ((svga->gdcreg[0x0b] & 0xc0) < 0xc0) {
paradise->read_bank[1] &= 0x7ffff;
paradise->write_bank[1] &= 0x7ffff;
} else {
paradise->read_bank[1] &= 0xfffff;
paradise->write_bank[1] &= 0xfffff;
}
}
void
paradise_recalctimings(svga_t *svga)
{
const paradise_t *paradise = (paradise_t *) svga->priv;
svga->lowres = !(svga->gdcreg[0x0e] & 0x01);
if (paradise->type == WD90C30) {
if (svga->crtc[0x3e] & 0x01)
svga->vtotal |= 0x400;
if (svga->crtc[0x3e] & 0x02)
svga->dispend |= 0x400;
if (svga->crtc[0x3e] & 0x04)
svga->vsyncstart |= 0x400;
if (svga->crtc[0x3e] & 0x08)
svga->vblankstart |= 0x400;
if (svga->crtc[0x3e] & 0x10)
svga->split |= 0x400;
svga->interlace = !!(svga->crtc[0x2d] & 0x20);
}
if (paradise->type < WD90C30) {
if ((svga->gdcreg[6] & 1) || (svga->attrregs[0x10] & 1)) {
if ((svga->bpp >= 8) && !svga->lowres) {
svga->render = svga_render_8bpp_highres;
svga->vram_display_mask = (svga->crtc[0x2f] & 0x02) ? 0x3ffff : paradise->vram_mask;
}
}
} else {
if ((svga->gdcreg[6] & 1) || (svga->attrregs[0x10] & 1)) {
if ((svga->bpp >= 8) && !svga->lowres) {
if (svga->bpp == 16) {
svga->render = svga_render_16bpp_highres;
svga->hdisp >>= 1;
if (svga->hdisp == 788)
svga->hdisp += 12;
if (svga->hdisp == 800)
svga->ma_latch -= 3;
} else if (svga->bpp == 15) {
svga->render = svga_render_15bpp_highres;
svga->hdisp >>= 1;
if (svga->hdisp == 788)
svga->hdisp += 12;
if (svga->hdisp == 800)
svga->ma_latch -= 3;
} else
svga->render = svga_render_8bpp_highres;
svga->vram_display_mask = (svga->crtc[0x2f] & 0x02) ? 0x3ffff : paradise->vram_mask;
} else if ((svga->bpp <= 8) && svga->lowres && !svga->interlace && (svga->hdisp >= 1024) &&
(svga->miscout >= 0x27) && (svga->miscout <= 0x2f))
svga->interlace = 1; /*Horrible tweak to re-enable the interlace after returning to
a windowed DOS box in Win3.x*/
}
}
}
static void
paradise_write(uint32_t addr, uint8_t val, void *priv)
{
paradise_t *paradise = (paradise_t *) priv;
svga_t *svga = ¶dise->svga;
uint32_t prev_addr;
uint32_t prev_addr2;
addr = (addr & 0x7fff) + paradise->write_bank[(addr >> 15) & 3];
/*Could be done in a better way but it works.*/
if (!svga->lowres || (svga->attrregs[0x10] & 0x40)) {
if (((svga->gdcreg[6] & 0x0c) == 0x04) && (svga->crtc[0x14] & 0x40) && ((svga->gdcreg[0x0b] & 0xc0) == 0xc0) && !svga->chain4) {
prev_addr = addr & 3;
prev_addr2 = addr & 0xfffc;
if (prev_addr == 3) {
if ((addr & 0x30000) != 0x30000)
addr = (addr >> 16) | (prev_addr << 16) | prev_addr2;
} else if (prev_addr == 2) {
if ((addr & 0x30000) != 0x20000)
addr = (addr >> 16) | (prev_addr << 16) | prev_addr2;
} else if (prev_addr == 1) {
if ((addr & 0x30000) != 0x10000)
addr = (addr >> 16) | (prev_addr << 16) | prev_addr2;
} else {
if (addr & 0x30000)
addr = (addr >> 16) | (prev_addr << 16) | prev_addr2;
}
}
}
svga_write_linear(addr, val, svga);
}
static void
paradise_writew(uint32_t addr, uint16_t val, void *priv)
{
paradise_t *paradise = (paradise_t *) priv;
svga_t *svga = ¶dise->svga;
uint32_t prev_addr;
uint32_t prev_addr2;
addr = (addr & 0x7fff) + paradise->write_bank[(addr >> 15) & 3];
/*Could be done in a better way but it works.*/
if (!svga->lowres || (svga->attrregs[0x10] & 0x40)) {
if (((svga->gdcreg[6] & 0x0c) == 0x04) && (svga->crtc[0x14] & 0x40) && ((svga->gdcreg[0x0b] & 0xc0) == 0xc0) && !svga->chain4) {
prev_addr = addr & 3;
prev_addr2 = addr & 0xfffc;
if (prev_addr == 3) {
if ((addr & 0x30000) != 0x30000)
addr = (addr >> 16) | (prev_addr << 16) | prev_addr2;
} else if (prev_addr == 2) {
if ((addr & 0x30000) != 0x20000)
addr = (addr >> 16) | (prev_addr << 16) | prev_addr2;
} else if (prev_addr == 1) {
if ((addr & 0x30000) != 0x10000)
addr = (addr >> 16) | (prev_addr << 16) | prev_addr2;
} else {
if (addr & 0x30000)
addr = (addr >> 16) | (prev_addr << 16) | prev_addr2;
}
}
}
svga_writew_linear(addr, val, svga);
}
static uint8_t
paradise_read(uint32_t addr, void *priv)
{
paradise_t *paradise = (paradise_t *) priv;
svga_t *svga = ¶dise->svga;
uint32_t prev_addr;
uint32_t prev_addr2;
addr = (addr & 0x7fff) + paradise->read_bank[(addr >> 15) & 3];
/*Could be done in a better way but it works.*/
if (!svga->lowres || (svga->attrregs[0x10] & 0x40)) {
if (((svga->gdcreg[6] & 0x0c) == 0x04) && (svga->crtc[0x14] & 0x40) && ((svga->gdcreg[0x0b] & 0xc0) == 0xc0) && !svga->chain4) {
prev_addr = addr & 3;
prev_addr2 = addr & 0xfffc;
if (prev_addr == 3) {
if ((addr & 0x30000) != 0x30000)
addr = (addr >> 16) | (prev_addr << 16) | prev_addr2;
} else if (prev_addr == 2) {
if ((addr & 0x30000) != 0x20000)
addr = (addr >> 16) | (prev_addr << 16) | prev_addr2;
} else if (prev_addr == 1) {
if ((addr & 0x30000) != 0x10000)
addr = (addr >> 16) | (prev_addr << 16) | prev_addr2;
} else {
if (addr & 0x30000)
addr = (addr >> 16) | (prev_addr << 16) | prev_addr2;
}
}
}
return svga_read_linear(addr, svga);
}
static uint16_t
paradise_readw(uint32_t addr, void *priv)
{
paradise_t *paradise = (paradise_t *) priv;
svga_t *svga = ¶dise->svga;
uint32_t prev_addr;
uint32_t prev_addr2;
addr = (addr & 0x7fff) + paradise->read_bank[(addr >> 15) & 3];
/*Could be done in a better way but it works.*/
if (!svga->lowres || (svga->attrregs[0x10] & 0x40)) {
if (((svga->gdcreg[6] & 0x0c) == 0x04) && (svga->crtc[0x14] & 0x40) && ((svga->gdcreg[0x0b] & 0xc0) == 0xc0) && !svga->chain4) {
prev_addr = addr & 3;
prev_addr2 = addr & 0xfffc;
if (prev_addr == 3) {
if ((addr & 0x30000) != 0x30000)
addr = (addr >> 16) | (prev_addr << 16) | prev_addr2;
} else if (prev_addr == 2) {
if ((addr & 0x30000) != 0x20000)
addr = (addr >> 16) | (prev_addr << 16) | prev_addr2;
} else if (prev_addr == 1) {
if ((addr & 0x30000) != 0x10000)
addr = (addr >> 16) | (prev_addr << 16) | prev_addr2;
} else {
if (addr & 0x30000)
addr = (addr >> 16) | (prev_addr << 16) | prev_addr2;
}
}
}
return svga_readw_linear(addr, svga);
}
void *
paradise_init(const device_t *info, uint32_t memsize)
{
paradise_t *paradise = malloc(sizeof(paradise_t));
svga_t *svga = ¶dise->svga;
memset(paradise, 0, sizeof(paradise_t));
if (info->local == PVGA1A)
video_inform(VIDEO_FLAG_TYPE_SPECIAL, &timing_paradise_pvga1a);
else
video_inform(VIDEO_FLAG_TYPE_SPECIAL, &timing_paradise_wd90c);
paradise->memory = memsize >> 10;
switch (info->local) {
case PVGA1A:
svga_init(info, svga, paradise, memsize, /*256kb*/
paradise_recalctimings,
paradise_in, paradise_out,
NULL,
NULL);
paradise->vram_mask = memsize - 1;
svga->decode_mask = memsize - 1;
break;
case WD90C11:
svga_init(info, svga, paradise, 1 << 19, /*512kb*/
paradise_recalctimings,
paradise_in, paradise_out,
NULL,
NULL);
paradise->vram_mask = (1 << 19) - 1;
svga->decode_mask = (1 << 19) - 1;
break;
case WD90C30:
svga_init(info, svga, paradise, memsize,
paradise_recalctimings,
paradise_in, paradise_out,
NULL,
NULL);
paradise->vram_mask = memsize - 1;
svga->decode_mask = memsize - 1;
svga->ramdac = device_add(&sc11487_ramdac_device); /*Actually a Winbond W82c487-80, probably a clone.*/
break;
default:
break;
}
mem_mapping_set_handler(&svga->mapping, paradise_read, paradise_readw, NULL, paradise_write, paradise_writew, NULL);
mem_mapping_set_p(&svga->mapping, paradise);
io_sethandler(0x03c0, 0x0020, paradise_in, NULL, NULL, paradise_out, NULL, NULL, paradise);
/* Common to all three types. */
svga->crtc[0x31] = 'W';
svga->crtc[0x32] = 'D';
svga->crtc[0x33] = '9';
svga->crtc[0x34] = '0';
svga->crtc[0x35] = 'C';
switch (info->local) {
case WD90C11:
svga->crtc[0x36] = '1';
svga->crtc[0x37] = '1';
break;
case WD90C30:
svga->crtc[0x36] = '3';
svga->crtc[0x37] = '0';
break;
default:
break;
}
svga->bpp = 8;
svga->miscout = 1;
paradise->type = info->local;
return paradise;
}
static void *
paradise_pvga1a_ncr3302_init(const device_t *info)
{
paradise_t *paradise = paradise_init(info, 1 << 18);
if (paradise)
rom_init(¶dise->bios_rom, "roms/machines/3302/c000-wd_1987-1989-740011-003058-019c.bin", 0xc0000, 0x8000, 0x7fff, 0, MEM_MAPPING_EXTERNAL);
return paradise;
}
static void *
paradise_pvga1a_pc2086_init(const device_t *info)
{
paradise_t *paradise = paradise_init(info, 1 << 18);
if (paradise)
rom_init(¶dise->bios_rom, "roms/machines/pc2086/40186.ic171", 0xc0000, 0x8000, 0x7fff, 0, MEM_MAPPING_EXTERNAL);
return paradise;
}
static void *
paradise_pvga1a_pc3086_init(const device_t *info)
{
paradise_t *paradise = paradise_init(info, 1 << 18);
if (paradise)
rom_init(¶dise->bios_rom, "roms/machines/pc3086/c000.bin", 0xc0000, 0x8000, 0x7fff, 0, MEM_MAPPING_EXTERNAL);
return paradise;
}
static void *
paradise_pvga1a_standalone_init(const device_t *info)
{
paradise_t *paradise;
uint32_t memory = 512;
memory = device_get_config_int("memory");
memory <<= 10;
paradise = paradise_init(info, memory);
if (paradise)
rom_init(¶dise->bios_rom, "roms/video/pvga1a/BIOS.BIN", 0xc0000, 0x8000, 0x7fff, 0, MEM_MAPPING_EXTERNAL);
return paradise;
}
static int
paradise_pvga1a_standalone_available(void)
{
return rom_present("roms/video/pvga1a/BIOS.BIN");
}
static void *
paradise_wd90c11_megapc_init(const device_t *info)
{
paradise_t *paradise = paradise_init(info, 0);
if (paradise)
rom_init_interleaved(¶dise->bios_rom,
"roms/machines/megapc/41651-bios lo.u18",
"roms/machines/megapc/211253-bios hi.u19",
0xc0000, 0x8000, 0x7fff, 0, MEM_MAPPING_EXTERNAL);
return paradise;
}
static void *
paradise_wd90c11_standalone_init(const device_t *info)
{
paradise_t *paradise = paradise_init(info, 0);
if (paradise)
rom_init(¶dise->bios_rom, "roms/video/wd90c11/WD90C11.VBI", 0xc0000, 0x8000, 0x7fff, 0, MEM_MAPPING_EXTERNAL);
return paradise;
}
static int
paradise_wd90c11_standalone_available(void)
{
return rom_present("roms/video/wd90c11/WD90C11.VBI");
}
static void *
paradise_wd90c30_standalone_init(const device_t *info)
{
paradise_t *paradise;
uint32_t memory = 512;
memory = device_get_config_int("memory");
memory <<= 10;
paradise = paradise_init(info, memory);
if (paradise)
rom_init(¶dise->bios_rom, "roms/video/wd90c30/90C30-LR.VBI", 0xc0000, 0x8000, 0x7fff, 0, MEM_MAPPING_EXTERNAL);
return paradise;
}
static int
paradise_wd90c30_standalone_available(void)
{
return rom_present("roms/video/wd90c30/90C30-LR.VBI");
}
void
paradise_close(void *priv)
{
paradise_t *paradise = (paradise_t *) priv;
svga_close(¶dise->svga);
free(paradise);
}
void
paradise_speed_changed(void *priv)
{
paradise_t *paradise = (paradise_t *) priv;
svga_recalctimings(¶dise->svga);
}
void
paradise_force_redraw(void *priv)
{
paradise_t *paradise = (paradise_t *) priv;
paradise->svga.fullchange = changeframecount;
}
const device_t paradise_pvga1a_pc2086_device = {
.name = "Paradise PVGA1A (Amstrad PC2086)",
.internal_name = "pvga1a_pc2086",
.flags = 0,
.local = PVGA1A,
.init = paradise_pvga1a_pc2086_init,
.close = paradise_close,
.reset = NULL,
{ .available = NULL },
.speed_changed = paradise_speed_changed,
.force_redraw = paradise_force_redraw,
.config = NULL
};
const device_t paradise_pvga1a_pc3086_device = {
.name = "Paradise PVGA1A (Amstrad PC3086)",
.internal_name = "pvga1a_pc3086",
.flags = 0,
.local = PVGA1A,
.init = paradise_pvga1a_pc3086_init,
.close = paradise_close,
.reset = NULL,
{ .available = NULL },
.speed_changed = paradise_speed_changed,
.force_redraw = paradise_force_redraw,
.config = NULL
};
static const device_config_t paradise_pvga1a_config[] = {
// clang-format off
{
.name = "memory",
.description = "Memory size",
.type = CONFIG_SELECTION,
.default_int = 512,
.selection = {
{
.description = "256 kB",
.value = 256
},
{
.description = "512 kB",
.value = 512
},
{
.description = ""
}
}
},
{
.type = CONFIG_END
}
// clang-format on
};
const device_t paradise_pvga1a_ncr3302_device = {
.name = "Paradise PVGA1A (NCR 3302)",
.internal_name = "pvga1a_ncr3302",
.flags = 0,
.local = PVGA1A,
.init = paradise_pvga1a_ncr3302_init,
.close = paradise_close,
.reset = NULL,
{ .available = NULL },
.speed_changed = paradise_speed_changed,
.force_redraw = paradise_force_redraw,
.config = paradise_pvga1a_config
};
const device_t paradise_pvga1a_device = {
.name = "Paradise PVGA1A",
.internal_name = "pvga1a",
.flags = DEVICE_ISA,
.local = PVGA1A,
.init = paradise_pvga1a_standalone_init,
.close = paradise_close,
.reset = NULL,
{ .available = paradise_pvga1a_standalone_available },
.speed_changed = paradise_speed_changed,
.force_redraw = paradise_force_redraw,
.config = paradise_pvga1a_config
};
const device_t paradise_wd90c11_megapc_device = {
.name = "Paradise WD90C11 (Amstrad MegaPC)",
.internal_name = "wd90c11_megapc",
.flags = 0,
.local = WD90C11,
.init = paradise_wd90c11_megapc_init,
.close = paradise_close,
.reset = NULL,
{ .available = NULL },
.speed_changed = paradise_speed_changed,
.force_redraw = paradise_force_redraw,
.config = NULL
};
const device_t paradise_wd90c11_device = {
.name = "Paradise WD90C11-LR",
.internal_name = "wd90c11",
.flags = DEVICE_ISA,
.local = WD90C11,
.init = paradise_wd90c11_standalone_init,
.close = paradise_close,
.reset = NULL,
{ .available = paradise_wd90c11_standalone_available },
.speed_changed = paradise_speed_changed,
.force_redraw = paradise_force_redraw,
.config = NULL
};
static const device_config_t paradise_wd90c30_config[] = {
// clang-format off
{
.name = "memory",
.description = "Memory size",
.type = CONFIG_SELECTION,
.default_int = 1024,
.selection = {
{
.description = "512 kB",
.value = 512
},
{
.description = "1 MB",
.value = 1024
},
{
.description = ""
}
}
},
{
.type = CONFIG_END
}
// clang-format on
};
const device_t paradise_wd90c30_device = {
.name = "Paradise WD90C30-LR",
.internal_name = "wd90c30",
.flags = DEVICE_ISA,
.local = WD90C30,
.init = paradise_wd90c30_standalone_init,
.close = paradise_close,
.reset = NULL,
{ .available = paradise_wd90c30_standalone_available },
.speed_changed = paradise_speed_changed,
.force_redraw = paradise_force_redraw,
.config = paradise_wd90c30_config
};
``` | /content/code_sandbox/src/video/vid_paradise.c | c | 2016-06-25T22:29:10 | 2024-08-16T19:09:21 | 86Box | 86Box/86Box | 2,616 | 8,854 |
```c
/*
* 86Box A hypervisor and IBM PC system emulator that specializes in
* running old operating systems and software designed for IBM
* PC systems and compatibles from 1981 through fairly recent
* system designs based on the PCI bus.
*
* This file is part of the 86Box distribution.
*
* Emulation of select Cirrus Logic cards (CL-GD 5428,
* CL-GD 5429, CL-GD 5430, CL-GD 5434 and CL-GD 5436 are supported).
*
*
*
* Authors: Miran Grca, <mgrca8@gmail.com>
* tonioni,
* TheCollector1995,
*
*/
#include <stdio.h>
#include <stdint.h>
#include <string.h>
#include <stdarg.h>
#include <stdlib.h>
#include <wchar.h>
#include <86box/86box.h>
#include "cpu.h"
#include <86box/io.h>
#include <86box/mca.h>
#include <86box/mem.h>
#include <86box/pci.h>
#include <86box/rom.h>
#include <86box/device.h>
#include <86box/timer.h>
#include <86box/video.h>
#include <86box/i2c.h>
#include <86box/vid_ddc.h>
#include <86box/vid_svga.h>
#include <86box/vid_svga_render.h>
#include <86box/plat_fallthrough.h>
#include <86box/plat_unused.h>
#define BIOS_GD5401_PATH "roms/video/cirruslogic/avga1.rom"
#define BIOS_GD5402_PATH "roms/video/cirruslogic/avga2.rom"
#define BIOS_GD5402_ONBOARD_PATH "roms/machines/cmdsl386sx25/c000.rom"
#define BIOS_GD5420_PATH "roms/video/cirruslogic/5420.vbi"
#define BIOS_GD5422_PATH "roms/video/cirruslogic/cl5422.bin"
#define BIOS_GD5426_DIAMOND_A1_ISA_PATH "roms/video/cirruslogic/diamond5426.vbi"
#define BIOS_GD5426_MCA_PATH "roms/video/cirruslogic/Reply.BIN"
#define BIOS_GD5428_DIAMOND_B1_VLB_PATH "roms/video/cirruslogic/Diamond SpeedStar PRO VLB v3.04.bin"
#define BIOS_GD5428_ISA_PATH "roms/video/cirruslogic/5428.bin"
#define BIOS_GD5428_MCA_PATH "roms/video/cirruslogic/SVGA141.ROM"
#define BIOS_GD5428_PATH "roms/video/cirruslogic/vlbusjapan.BIN"
#define BIOS_GD5428_BOCA_ISA_PATH_1 "roms/video/cirruslogic/boca_gd5428_1.30b_1.bin"
#define BIOS_GD5428_BOCA_ISA_PATH_2 "roms/video/cirruslogic/boca_gd5428_1.30b_2.bin"
#define BIOS_GD5429_PATH "roms/video/cirruslogic/5429.vbi"
#define BIOS_GD5430_DIAMOND_A8_VLB_PATH "roms/video/cirruslogic/diamondvlbus.bin"
#define BIOS_GD5430_ORCHID_VLB_PATH "roms/video/cirruslogic/orchidvlbus.bin"
#define BIOS_GD5430_PATH "roms/video/cirruslogic/pci.bin"
#define BIOS_GD5434_DIAMOND_A3_ISA_PATH "roms/video/cirruslogic/Diamond Multimedia SpeedStar 64 v2.02 EPROM Backup from ST M27C256B-12F1.BIN"
#define BIOS_GD5434_PATH "roms/video/cirruslogic/gd5434.BIN"
#define BIOS_GD5436_PATH "roms/video/cirruslogic/5436.vbi"
#define BIOS_GD5440_PATH "roms/video/cirruslogic/BIOS.BIN"
#define BIOS_GD5446_PATH "roms/video/cirruslogic/5446bv.vbi"
#define BIOS_GD5446_STB_PATH "roms/video/cirruslogic/stb nitro64v.BIN"
#define BIOS_GD5480_PATH "roms/video/cirruslogic/clgd5480.rom"
#define CIRRUS_ID_CLGD5401 0x88
#define CIRRUS_ID_CLGD5402 0x89
#define CIRRUS_ID_CLGD5420 0x8a
#define CIRRUS_ID_CLGD5422 0x8c
#define CIRRUS_ID_CLGD5424 0x94
#define CIRRUS_ID_CLGD5426 0x90
#define CIRRUS_ID_CLGD5428 0x98
#define CIRRUS_ID_CLGD5429 0x9c
#define CIRRUS_ID_CLGD5430 0xa0
#define CIRRUS_ID_CLGD5432 0xa2
#define CIRRUS_ID_CLGD5434_4 0xa4
#define CIRRUS_ID_CLGD5434 0xa8
#define CIRRUS_ID_CLGD5436 0xac
#define CIRRUS_ID_CLGD5440 0xa0 /* Yes, the 5440 has the same ID as the 5430. */
#define CIRRUS_ID_CLGD5446 0xb8
#define CIRRUS_ID_CLGD5480 0xbc
/* sequencer 0x07 */
#define CIRRUS_SR7_BPP_VGA 0x00
#define CIRRUS_SR7_BPP_SVGA 0x01
#define CIRRUS_SR7_BPP_MASK 0x0e
#define CIRRUS_SR7_BPP_8 0x00
#define CIRRUS_SR7_BPP_16_DOUBLEVCLK 0x02
#define CIRRUS_SR7_BPP_24 0x04
#define CIRRUS_SR7_BPP_16 0x06
#define CIRRUS_SR7_BPP_32 0x08
#define CIRRUS_SR7_ISAADDR_MASK 0xe0
/* sequencer 0x12 */
#define CIRRUS_CURSOR_SHOW 0x01
#define CIRRUS_CURSOR_HIDDENPEL 0x02
#define CIRRUS_CURSOR_LARGE 0x04 /* 64x64 if set, 32x32 if clear */
/* sequencer 0x17 */
#define CIRRUS_BUSTYPE_VLBFAST 0x10
#define CIRRUS_BUSTYPE_PCI 0x20
#define CIRRUS_BUSTYPE_VLBSLOW 0x30
#define CIRRUS_BUSTYPE_ISA 0x38
#define CIRRUS_MMIO_ENABLE 0x04
#define CIRRUS_MMIO_USE_PCIADDR 0x40 /* 0xb8000 if cleared. */
#define CIRRUS_MEMSIZEEXT_DOUBLE 0x80
/* control 0x0b */
#define CIRRUS_BANKING_DUAL 0x01
#define CIRRUS_BANKING_GRANULARITY_16K 0x20 /* set:16k, clear:4k */
/* control 0x30 */
#define CIRRUS_BLTMODE_BACKWARDS 0x01
#define CIRRUS_BLTMODE_MEMSYSDEST 0x02
#define CIRRUS_BLTMODE_MEMSYSSRC 0x04
#define CIRRUS_BLTMODE_TRANSPARENTCOMP 0x08
#define CIRRUS_BLTMODE_PATTERNCOPY 0x40
#define CIRRUS_BLTMODE_COLOREXPAND 0x80
#define CIRRUS_BLTMODE_PIXELWIDTHMASK 0x30
#define CIRRUS_BLTMODE_PIXELWIDTH8 0x00
#define CIRRUS_BLTMODE_PIXELWIDTH16 0x10
#define CIRRUS_BLTMODE_PIXELWIDTH24 0x20
#define CIRRUS_BLTMODE_PIXELWIDTH32 0x30
/* control 0x31 */
#define CIRRUS_BLT_BUSY 0x01
#define CIRRUS_BLT_START 0x02
#define CIRRUS_BLT_RESET 0x04
#define CIRRUS_BLT_FIFOUSED 0x10
#define CIRRUS_BLT_PAUSED 0x20
#define CIRRUS_BLT_APERTURE2 0x40
#define CIRRUS_BLT_AUTOSTART 0x80
/* control 0x33 */
#define CIRRUS_BLTMODEEXT_BACKGROUNDONLY 0x08
#define CIRRUS_BLTMODEEXT_SOLIDFILL 0x04
#define CIRRUS_BLTMODEEXT_COLOREXPINV 0x02
#define CIRRUS_BLTMODEEXT_DWORDGRANULARITY 0x01
#define CL_GD5428_SYSTEM_BUS_MCA 5
#define CL_GD5428_SYSTEM_BUS_VESA 6
#define CL_GD5428_SYSTEM_BUS_ISA 7
#define CL_GD5429_SYSTEM_BUS_VESA 5
#define CL_GD5429_SYSTEM_BUS_ISA 7
#define CL_GD543X_SYSTEM_BUS_PCI 4
#define CL_GD543X_SYSTEM_BUS_VESA 6
#define CL_GD543X_SYSTEM_BUS_ISA 7
typedef struct gd54xx_t {
mem_mapping_t mmio_mapping;
mem_mapping_t linear_mapping;
mem_mapping_t aperture2_mapping;
mem_mapping_t vgablt_mapping;
svga_t svga;
int has_bios;
int rev;
int bit32;
rom_t bios_rom;
uint32_t vram_size;
uint32_t vram_mask;
uint8_t vclk_n[4];
uint8_t vclk_d[4];
struct {
uint8_t state;
int ctrl;
} ramdac;
struct {
uint16_t width;
uint16_t height;
uint16_t dst_pitch;
uint16_t src_pitch;
uint16_t trans_col;
uint16_t trans_mask;
uint16_t height_internal;
uint16_t msd_buf_pos;
uint16_t msd_buf_cnt;
uint8_t status;
uint8_t mask;
uint8_t mode;
uint8_t rop;
uint8_t modeext;
uint8_t ms_is_dest;
uint8_t msd_buf[32];
uint32_t fg_col;
uint32_t bg_col;
uint32_t dst_addr_backup;
uint32_t src_addr_backup;
uint32_t dst_addr;
uint32_t src_addr;
uint32_t sys_src32;
uint32_t sys_cnt;
/* Internal state */
int pixel_width;
int pattern_x;
int x_count;
int y_count;
int xx_count;
int dir;
int unlock_special;
} blt;
struct {
int mode;
uint16_t stride;
uint16_t r1sz;
uint16_t r1adjust;
uint16_t r2sz;
uint16_t r2adjust;
uint16_t r2sdz;
uint16_t wvs;
uint16_t wve;
uint16_t hzoom;
uint16_t vzoom;
uint8_t occlusion;
uint8_t colorkeycomparemask;
uint8_t colorkeycompare;
int region1size;
int region2size;
int colorkeymode;
uint32_t ck;
} overlay;
int pci;
int vlb;
int mca;
int countminusone;
int vblank_irq;
int vportsync;
uint8_t pci_regs[256];
uint8_t int_line;
uint8_t unlocked;
uint8_t status;
uint8_t extensions;
uint8_t crtcreg_mask;
uint8_t fc; /* Feature Connector */
int id;
uint8_t pci_slot;
uint8_t irq_state;
uint8_t pos_regs[8];
uint32_t lfb_base;
uint32_t vgablt_base;
int mmio_vram_overlap;
uint32_t extpallook[256];
PALETTE extpal;
void *i2c;
void *ddc;
} gd54xx_t;
static video_timings_t timing_gd54xx_isa = { .type = VIDEO_ISA, .write_b = 3, .write_w = 3, .write_l = 6, .read_b = 8, .read_w = 8, .read_l = 12 };
static video_timings_t timing_gd54xx_vlb = { .type = VIDEO_BUS, .write_b = 4, .write_w = 4, .write_l = 8, .read_b = 10, .read_w = 10, .read_l = 20 };
static video_timings_t timing_gd54xx_pci = { .type = VIDEO_PCI, .write_b = 4, .write_w = 4, .write_l = 8, .read_b = 10, .read_w = 10, .read_l = 20 };
static void
gd543x_mmio_write(uint32_t addr, uint8_t val, void *priv);
static void
gd543x_mmio_writeb(uint32_t addr, uint8_t val, void *priv);
static void
gd543x_mmio_writew(uint32_t addr, uint16_t val, void *priv);
static void
gd543x_mmio_writel(uint32_t addr, uint32_t val, void *priv);
static uint8_t
gd543x_mmio_read(uint32_t addr, void *priv);
static uint16_t
gd543x_mmio_readw(uint32_t addr, void *priv);
static uint32_t
gd543x_mmio_readl(uint32_t addr, void *priv);
static void
gd54xx_recalc_banking(gd54xx_t *gd54xx);
static void
gd543x_recalc_mapping(gd54xx_t *gd54xx);
static void
gd54xx_reset_blit(gd54xx_t *gd54xx);
static void
gd54xx_start_blit(uint32_t cpu_dat, uint32_t count, gd54xx_t *gd54xx, svga_t *svga);
#define CLAMP(x) \
do { \
if ((x) & ~0xff) \
x = ((x) < 0) ? 0 : 0xff; \
} while (0)
#define DECODE_YCbCr() \
do { \
int c; \
\
for (c = 0; c < 2; c++) { \
uint8_t y1, y2; \
int8_t Cr, Cb; \
int dR, dG, dB; \
\
y1 = src[0]; \
Cr = src[1] - 0x80; \
y2 = src[2]; \
Cb = src[3] - 0x80; \
src += 4; \
\
dR = (359 * Cr) >> 8; \
dG = (88 * Cb + 183 * Cr) >> 8; \
dB = (453 * Cb) >> 8; \
\
r[x_write] = y1 + dR; \
CLAMP(r[x_write]); \
g[x_write] = y1 - dG; \
CLAMP(g[x_write]); \
b[x_write] = y1 + dB; \
CLAMP(b[x_write]); \
\
r[x_write + 1] = y2 + dR; \
CLAMP(r[x_write + 1]); \
g[x_write + 1] = y2 - dG; \
CLAMP(g[x_write + 1]); \
b[x_write + 1] = y2 + dB; \
CLAMP(b[x_write + 1]); \
\
x_write = (x_write + 2) & 7; \
} \
} while (0)
/*Both YUV formats are untested*/
#define DECODE_YUV211() \
do { \
uint8_t y1, y2, y3, y4; \
int8_t U, V; \
int dR, dG, dB; \
\
U = src[0] - 0x80; \
y1 = (298 * (src[1] - 16)) >> 8; \
y2 = (298 * (src[2] - 16)) >> 8; \
V = src[3] - 0x80; \
y3 = (298 * (src[4] - 16)) >> 8; \
y4 = (298 * (src[5] - 16)) >> 8; \
src += 6; \
\
dR = (309 * V) >> 8; \
dG = (100 * U + 208 * V) >> 8; \
dB = (516 * U) >> 8; \
\
r[x_write] = y1 + dR; \
CLAMP(r[x_write]); \
g[x_write] = y1 - dG; \
CLAMP(g[x_write]); \
b[x_write] = y1 + dB; \
CLAMP(b[x_write]); \
\
r[x_write + 1] = y2 + dR; \
CLAMP(r[x_write + 1]); \
g[x_write + 1] = y2 - dG; \
CLAMP(g[x_write + 1]); \
b[x_write + 1] = y2 + dB; \
CLAMP(b[x_write + 1]); \
\
r[x_write + 2] = y3 + dR; \
CLAMP(r[x_write + 2]); \
g[x_write + 2] = y3 - dG; \
CLAMP(g[x_write + 2]); \
b[x_write + 2] = y3 + dB; \
CLAMP(b[x_write + 2]); \
\
r[x_write + 3] = y4 + dR; \
CLAMP(r[x_write + 3]); \
g[x_write + 3] = y4 - dG; \
CLAMP(g[x_write + 3]); \
b[x_write + 3] = y4 + dB; \
CLAMP(b[x_write + 3]); \
\
x_write = (x_write + 4) & 7; \
} while (0)
#define DECODE_YUV422() \
do { \
int c; \
\
for (c = 0; c < 2; c++) { \
uint8_t y1, y2; \
int8_t U, V; \
int dR, dG, dB; \
\
U = src[0] - 0x80; \
y1 = (298 * (src[1] - 16)) >> 8; \
V = src[2] - 0x80; \
y2 = (298 * (src[3] - 16)) >> 8; \
src += 4; \
\
dR = (309 * V) >> 8; \
dG = (100 * U + 208 * V) >> 8; \
dB = (516 * U) >> 8; \
\
r[x_write] = y1 + dR; \
CLAMP(r[x_write]); \
g[x_write] = y1 - dG; \
CLAMP(g[x_write]); \
b[x_write] = y1 + dB; \
CLAMP(b[x_write]); \
\
r[x_write + 1] = y2 + dR; \
CLAMP(r[x_write + 1]); \
g[x_write + 1] = y2 - dG; \
CLAMP(g[x_write + 1]); \
b[x_write + 1] = y2 + dB; \
CLAMP(b[x_write + 1]); \
\
x_write = (x_write + 2) & 7; \
} \
} while (0)
#define DECODE_RGB555() \
do { \
int c; \
\
for (c = 0; c < 4; c++) { \
uint16_t dat; \
\
dat = *(uint16_t *) src; \
src += 2; \
\
r[x_write + c] = ((dat & 0x001f) << 3) | ((dat & 0x001f) >> 2); \
g[x_write + c] = ((dat & 0x03e0) >> 2) | ((dat & 0x03e0) >> 7); \
b[x_write + c] = ((dat & 0x7c00) >> 7) | ((dat & 0x7c00) >> 12); \
} \
x_write = (x_write + 4) & 7; \
} while (0)
#define DECODE_RGB565() \
do { \
int c; \
\
for (c = 0; c < 4; c++) { \
uint16_t dat; \
\
dat = *(uint16_t *) src; \
src += 2; \
\
r[x_write + c] = ((dat & 0x001f) << 3) | ((dat & 0x001f) >> 2); \
g[x_write + c] = ((dat & 0x07e0) >> 3) | ((dat & 0x07e0) >> 9); \
b[x_write + c] = ((dat & 0xf800) >> 8) | ((dat & 0xf800) >> 13); \
} \
x_write = (x_write + 4) & 7; \
} while (0)
#define DECODE_CLUT() \
do { \
int c; \
\
for (c = 0; c < 4; c++) { \
uint8_t dat; \
\
dat = *(uint8_t *) src; \
src++; \
\
r[x_write + c] = svga->pallook[dat] >> 0; \
g[x_write + c] = svga->pallook[dat] >> 8; \
b[x_write + c] = svga->pallook[dat] >> 16; \
} \
x_write = (x_write + 4) & 7; \
} while (0)
#define OVERLAY_SAMPLE() \
do { \
switch (gd54xx->overlay.mode) { \
case 0: \
DECODE_YUV422(); \
break; \
case 2: \
DECODE_CLUT(); \
break; \
case 3: \
DECODE_YUV211(); \
break; \
case 4: \
DECODE_RGB555(); \
break; \
case 5: \
DECODE_RGB565(); \
break; \
} \
} while (0)
static int
gd54xx_interrupt_enabled(gd54xx_t *gd54xx)
{
return !gd54xx->pci || (gd54xx->svga.gdcreg[0x17] & 0x04);
}
static int
gd54xx_vga_vsync_enabled(gd54xx_t *gd54xx)
{
if (!(gd54xx->svga.crtc[0x11] & 0x20) && (gd54xx->svga.crtc[0x11] & 0x10) && gd54xx_interrupt_enabled(gd54xx))
return 1;
return 0;
}
static void
gd54xx_update_irqs(gd54xx_t *gd54xx)
{
if (!gd54xx->pci)
return;
if ((gd54xx->vblank_irq > 0) && gd54xx_vga_vsync_enabled(gd54xx))
pci_set_irq(gd54xx->pci_slot, PCI_INTA, &gd54xx->irq_state);
else
pci_clear_irq(gd54xx->pci_slot, PCI_INTA, &gd54xx->irq_state);
}
static void
gd54xx_vblank_start(svga_t *svga)
{
gd54xx_t *gd54xx = (gd54xx_t *) svga->priv;
if (gd54xx->vblank_irq >= 0) {
gd54xx->vblank_irq = 1;
gd54xx_update_irqs(gd54xx);
}
}
/* Returns 1 if the card is a 5422+ */
static int
gd54xx_is_5422(svga_t *svga)
{
if (svga->crtc[0x27] >= CIRRUS_ID_CLGD5422)
return 1;
else
return 0;
}
static void
gd54xx_overlay_draw(svga_t *svga, int displine)
{
const gd54xx_t *gd54xx = (gd54xx_t *) svga->priv;
int shift = (svga->crtc[0x27] >= CIRRUS_ID_CLGD5446) ? 2 : 0;
int h_acc = svga->overlay_latch.h_acc;
int r[8];
int g[8];
int b[8];
int x_read = 4;
int x_write = 4;
uint32_t *p;
uint8_t *src = &svga->vram[(svga->overlay_latch.addr << shift) & svga->vram_mask];
int bpp = svga->bpp;
int bytesperpix = (bpp + 7) / 8;
uint8_t *src2 = &svga->vram[(svga->ma - (svga->hdisp * bytesperpix)) & svga->vram_display_mask];
int occl;
int ckval;
p = &(svga->monitor->target_buffer->line[displine])[gd54xx->overlay.region1size + svga->x_add];
src2 += gd54xx->overlay.region1size * bytesperpix;
OVERLAY_SAMPLE();
for (int x = 0; (x < gd54xx->overlay.region2size) && ((x + gd54xx->overlay.region1size) < svga->hdisp); x++) {
if (gd54xx->overlay.occlusion) {
occl = 1;
ckval = gd54xx->overlay.ck;
if (bytesperpix == 1) {
if (*src2 == ckval)
occl = 0;
} else if (bytesperpix == 2) {
if (*((uint16_t *) src2) == ckval)
occl = 0;
} else
occl = 0;
if (!occl)
*p++ = r[x_read] | (g[x_read] << 8) | (b[x_read] << 16);
src2 += bytesperpix;
} else
*p++ = r[x_read] | (g[x_read] << 8) | (b[x_read] << 16);
h_acc += gd54xx->overlay.hzoom;
if (h_acc >= 256) {
if ((x_read ^ (x_read + 1)) & ~3)
OVERLAY_SAMPLE();
x_read = (x_read + 1) & 7;
h_acc -= 256;
}
}
svga->overlay_latch.v_acc += gd54xx->overlay.vzoom;
if (svga->overlay_latch.v_acc >= 256) {
svga->overlay_latch.v_acc -= 256;
svga->overlay_latch.addr += svga->overlay.pitch << 1;
}
}
static void
gd54xx_update_overlay(gd54xx_t *gd54xx)
{
svga_t *svga = &gd54xx->svga;
int bpp = svga->bpp;
svga->overlay.cur_ysize = gd54xx->overlay.wve - gd54xx->overlay.wvs + 1;
gd54xx->overlay.region1size = 32 * gd54xx->overlay.r1sz / bpp + (gd54xx->overlay.r1adjust * 8 / bpp);
gd54xx->overlay.region2size = 32 * gd54xx->overlay.r2sz / bpp + (gd54xx->overlay.r2adjust * 8 / bpp);
gd54xx->overlay.occlusion = (svga->crtc[0x3e] & 0x80) != 0 && svga->bpp <= 16;
/* Mask and chroma key ignored. */
if (gd54xx->overlay.colorkeymode == 0)
gd54xx->overlay.ck = gd54xx->overlay.colorkeycompare;
else if (gd54xx->overlay.colorkeymode == 1)
gd54xx->overlay.ck = gd54xx->overlay.colorkeycompare | (gd54xx->overlay.colorkeycomparemask << 8);
else
gd54xx->overlay.occlusion = 0;
}
/* Returns 1 if the card supports the 8-bpp/16-bpp transparency color or mask. */
static int
gd54xx_has_transp(svga_t *svga, int mask)
{
if (((svga->crtc[0x27] == CIRRUS_ID_CLGD5446) || (svga->crtc[0x27] == CIRRUS_ID_CLGD5480)) && !mask)
return 1; /* 5446 and 5480 have mask but not transparency. */
if ((svga->crtc[0x27] == CIRRUS_ID_CLGD5426) || (svga->crtc[0x27] == CIRRUS_ID_CLGD5428))
return 1; /* 5426 and 5428 have both. */
else
return 0; /* The rest have neither. */
}
/* Returns 1 if the card is a 5434, 5436/46, or 5480. */
static int
gd54xx_is_5434(svga_t *svga)
{
if (svga->crtc[0x27] >= CIRRUS_ID_CLGD5434)
return 1;
else
return 0;
}
static void
gd54xx_set_svga_fast(gd54xx_t *gd54xx)
{
svga_t *svga = &gd54xx->svga;
if ((svga->crtc[0x27] == CIRRUS_ID_CLGD5422) || (svga->crtc[0x27] == CIRRUS_ID_CLGD5424))
svga->fast = ((svga->gdcreg[8] == 0xff) && !(svga->gdcreg[3] & 0x18) &&
!svga->gdcreg[1]) &&
((svga->chain4 && svga->packed_chain4) || svga->fb_only) &&
!(svga->adv_flags & FLAG_ADDR_BY8);
/* TODO: needs verification on other Cirrus chips */
else
svga->fast = ((svga->gdcreg[8] == 0xff) && !(svga->gdcreg[3] & 0x18) &&
!svga->gdcreg[1]) && ((svga->chain4 && svga->packed_chain4) ||
svga->fb_only);
}
static void
gd54xx_out(uint16_t addr, uint8_t val, void *priv)
{
gd54xx_t *gd54xx = (gd54xx_t *) priv;
svga_t *svga = &gd54xx->svga;
uint8_t old;
uint8_t o;
uint8_t index;
uint32_t o32;
if (((addr & 0xfff0) == 0x3d0 || (addr & 0xfff0) == 0x3b0) && !(svga->miscout & 1))
addr ^= 0x60;
switch (addr) {
case 0x3c0:
case 0x3c1:
if (!svga->attrff) {
svga->attraddr = val & 31;
if ((val & 0x20) != svga->attr_palette_enable) {
svga->fullchange = 3;
svga->attr_palette_enable = val & 0x20;
svga_recalctimings(svga);
}
} else {
o = svga->attrregs[svga->attraddr & 31];
svga->attrregs[svga->attraddr & 31] = val;
if (svga->attraddr < 16)
svga->fullchange = changeframecount;
if (svga->attraddr == 0x10 || svga->attraddr == 0x14 || svga->attraddr < 0x10) {
for (uint8_t c = 0; c < 16; c++) {
if (svga->attrregs[0x10] & 0x80)
svga->egapal[c] = (svga->attrregs[c] & 0xf) | ((svga->attrregs[0x14] & 0xf) << 4);
else
svga->egapal[c] = (svga->attrregs[c] & 0x3f) | ((svga->attrregs[0x14] & 0xc) << 4);
}
}
/* Recalculate timings on change of attribute register 0x11 (overscan border color) too. */
if (svga->attraddr == 0x10) {
if (o != val)
svga_recalctimings(svga);
} else if (svga->attraddr == 0x11) {
if (!(svga->seqregs[0x12] & 0x80)) {
svga->overscan_color = svga->pallook[svga->attrregs[0x11]];
if (o != val)
svga_recalctimings(svga);
}
} else if (svga->attraddr == 0x12) {
if ((val & 0xf) != svga->plane_mask)
svga->fullchange = changeframecount;
svga->plane_mask = val & 0xf;
}
}
svga->attrff ^= 1;
return;
case 0x3c4:
svga->seqaddr = val;
break;
case 0x3c5:
if ((svga->seqaddr == 2) && !gd54xx->unlocked) {
o = svga->seqregs[svga->seqaddr & 0x1f];
svga_out(addr, val, svga);
if (svga->gdcreg[0xb] & 0x04)
svga->seqregs[svga->seqaddr & 0x1f] = (o & 0xf0) | (val & 0x0f);
return;
} else if ((svga->seqaddr > 6) && !gd54xx->unlocked)
return;
if (svga->seqaddr > 5) {
o = svga->seqregs[svga->seqaddr & 0x1f];
svga->seqregs[svga->seqaddr & 0x1f] = val;
switch (svga->seqaddr) {
case 6:
val &= 0x17;
if (val == 0x12)
svga->seqregs[6] = 0x12;
else
svga->seqregs[6] = 0x0f;
if (svga->crtc[0x27] < CIRRUS_ID_CLGD5429)
gd54xx->unlocked = (svga->seqregs[6] == 0x12);
break;
case 0x08:
if (gd54xx->i2c)
i2c_gpio_set(gd54xx->i2c, !!(val & 0x01), !!(val & 0x02));
break;
case 0x0b:
case 0x0c:
case 0x0d:
case 0x0e: /* VCLK stuff */
gd54xx->vclk_n[svga->seqaddr - 0x0b] = val;
break;
case 0x1b:
case 0x1c:
case 0x1d:
case 0x1e: /* VCLK stuff */
gd54xx->vclk_d[svga->seqaddr - 0x1b] = val;
break;
case 0x10:
case 0x30:
case 0x50:
case 0x70:
case 0x90:
case 0xb0:
case 0xd0:
case 0xf0:
svga->hwcursor.x = (val << 3) | (svga->seqaddr >> 5);
break;
case 0x11:
case 0x31:
case 0x51:
case 0x71:
case 0x91:
case 0xb1:
case 0xd1:
case 0xf1:
svga->hwcursor.y = (val << 3) | (svga->seqaddr >> 5);
break;
case 0x12:
svga->ext_overscan = !!(val & 0x80);
if (svga->ext_overscan && (svga->crtc[0x27] >= CIRRUS_ID_CLGD5426))
svga->overscan_color = gd54xx->extpallook[2];
else
svga->overscan_color = svga->pallook[svga->attrregs[0x11]];
svga_recalctimings(svga);
svga->hwcursor.ena = val & CIRRUS_CURSOR_SHOW;
if (svga->crtc[0x27] >= CIRRUS_ID_CLGD5422)
svga->hwcursor.cur_xsize = svga->hwcursor.cur_ysize = ((val & CIRRUS_CURSOR_LARGE) && (svga->crtc[0x27] >= CIRRUS_ID_CLGD5422)) ? 64 : 32;
else
svga->hwcursor.cur_xsize = 32;
if ((svga->seqregs[0x12] & CIRRUS_CURSOR_LARGE) && (svga->crtc[0x27] >= CIRRUS_ID_CLGD5422))
svga->hwcursor.addr = ((gd54xx->vram_size - 0x4000) + ((svga->seqregs[0x13] & 0x3c) * 256));
else
svga->hwcursor.addr = ((gd54xx->vram_size - 0x4000) + ((svga->seqregs[0x13] & 0x3f) * 256));
break;
case 0x13:
if ((svga->seqregs[0x12] & CIRRUS_CURSOR_LARGE) && (svga->crtc[0x27] >= CIRRUS_ID_CLGD5422))
svga->hwcursor.addr = ((gd54xx->vram_size - 0x4000) + ((val & 0x3c) * 256));
else
svga->hwcursor.addr = ((gd54xx->vram_size - 0x4000) + ((val & 0x3f) * 256));
break;
case 0x07:
svga->packed_chain4 = svga->seqregs[0x07] & CIRRUS_SR7_BPP_SVGA;
if (gd54xx_is_5422(svga))
gd543x_recalc_mapping(gd54xx);
else
svga->seqregs[svga->seqaddr] &= 0x0f;
if (svga->crtc[0x27] >= CIRRUS_ID_CLGD5429)
svga->set_reset_disabled = svga->seqregs[0x07] & CIRRUS_SR7_BPP_SVGA;
gd54xx_set_svga_fast(gd54xx);
svga_recalctimings(svga);
break;
case 0x17:
if (gd54xx_is_5422(svga))
gd543x_recalc_mapping(gd54xx);
else
return;
break;
default:
break;
}
return;
}
break;
case 0x3c6:
if (!gd54xx->unlocked)
break;
if (gd54xx->ramdac.state == 4) {
gd54xx->ramdac.state = 0;
gd54xx->ramdac.ctrl = val;
svga_recalctimings(svga);
return;
}
gd54xx->ramdac.state = 0;
break;
case 0x3c7:
case 0x3c8:
gd54xx->ramdac.state = 0;
break;
case 0x3c9:
gd54xx->ramdac.state = 0;
svga->dac_status = 0;
svga->fullchange = changeframecount;
switch (svga->dac_pos) {
case 0:
svga->dac_r = val;
svga->dac_pos++;
break;
case 1:
svga->dac_g = val;
svga->dac_pos++;
break;
case 2:
index = svga->dac_addr & 0xff;
if (svga->seqregs[0x12] & 2) {
index &= 0x0f;
gd54xx->extpal[index].r = svga->dac_r;
gd54xx->extpal[index].g = svga->dac_g;
gd54xx->extpal[index].b = val;
gd54xx->extpallook[index] = makecol32(video_6to8[gd54xx->extpal[index].r & 0x3f], video_6to8[gd54xx->extpal[index].g & 0x3f], video_6to8[gd54xx->extpal[index].b & 0x3f]);
if (svga->ext_overscan && (index == 2)) {
o32 = svga->overscan_color;
svga->overscan_color = gd54xx->extpallook[2];
if (o32 != svga->overscan_color)
svga_recalctimings(svga);
}
} else {
svga->vgapal[index].r = svga->dac_r;
svga->vgapal[index].g = svga->dac_g;
svga->vgapal[index].b = val;
svga->pallook[index] = makecol32(video_6to8[svga->vgapal[index].r & 0x3f], video_6to8[svga->vgapal[index].g & 0x3f], video_6to8[svga->vgapal[index].b & 0x3f]);
}
svga->dac_addr = (svga->dac_addr + 1) & 255;
svga->dac_pos = 0;
break;
default:
break;
}
return;
case 0x3ce:
/* Per the CL-GD 5446 manual: bits 0-5 are the GDC register index, bits 6-7 are reserved. */
svga->gdcaddr = val /* & 0x3f*/;
return;
case 0x3cf:
if ((svga->gdcaddr > 0x1f) && ((svga->crtc[0x27] <= CIRRUS_ID_CLGD5422) || (svga->crtc[0x27] == CIRRUS_ID_CLGD5424)))
return;
o = svga->gdcreg[svga->gdcaddr];
if ((svga->gdcaddr < 2) && !gd54xx->unlocked)
svga->gdcreg[svga->gdcaddr] = (svga->gdcreg[svga->gdcaddr] & 0xf0) | (val & 0x0f);
else if ((svga->gdcaddr <= 8) || gd54xx->unlocked)
svga->gdcreg[svga->gdcaddr] = val;
if (svga->gdcaddr <= 8) {
switch (svga->gdcaddr) {
case 0:
gd543x_mmio_write(0xb8000, val, gd54xx);
break;
case 1:
gd543x_mmio_write(0xb8004, val, gd54xx);
break;
case 2:
svga->colourcompare = val;
break;
case 4:
svga->readplane = val & 3;
break;
case 5:
if (svga->gdcreg[0xb] & 0x04)
svga->writemode = val & 7;
else
svga->writemode = val & 3;
svga->readmode = val & 8;
svga->chain2_read = val & 0x10;
break;
case 6:
if ((o ^ val) & 0x0c)
gd543x_recalc_mapping(gd54xx);
break;
case 7:
svga->colournocare = val;
break;
default:
break;
}
gd54xx_set_svga_fast(gd54xx);
if (((svga->gdcaddr == 5) && ((val ^ o) & 0x70)) || ((svga->gdcaddr == 6) && ((val ^ o) & 1)))
svga_recalctimings(svga);
} else {
switch (svga->gdcaddr) {
case 0x0b:
svga->adv_flags = 0;
if (svga->gdcreg[0xb] & 0x01)
svga->adv_flags = FLAG_EXTRA_BANKS;
if (svga->gdcreg[0xb] & 0x02)
svga->adv_flags |= FLAG_ADDR_BY8;
if (svga->gdcreg[0xb] & 0x04)
svga->adv_flags |= FLAG_EXT_WRITE;
if (svga->gdcreg[0xb] & 0x08)
svga->adv_flags |= FLAG_LATCH8;
if ((svga->gdcreg[0xb] & 0x10) && (svga->adv_flags & FLAG_EXT_WRITE))
svga->adv_flags |= FLAG_ADDR_BY16;
if (svga->gdcreg[0xb] & 0x04)
svga->writemode = svga->gdcreg[5] & 7;
else if (o & 0x4) {
svga->gdcreg[5] &= ~0x04;
svga->writemode = svga->gdcreg[5] & 3;
svga->adv_flags &= (FLAG_EXTRA_BANKS | FLAG_ADDR_BY8 | FLAG_LATCH8);
if (svga->crtc[0x27] != CIRRUS_ID_CLGD5436) {
svga->gdcreg[0] &= 0x0f;
gd543x_mmio_write(0xb8000, svga->gdcreg[0], gd54xx);
svga->gdcreg[1] &= 0x0f;
gd543x_mmio_write(0xb8004, svga->gdcreg[1], gd54xx);
}
svga->seqregs[2] &= 0x0f;
}
fallthrough;
case 0x09:
case 0x0a:
gd54xx_recalc_banking(gd54xx);
break;
case 0x0c:
gd54xx->overlay.colorkeycompare = val;
gd54xx_update_overlay(gd54xx);
break;
case 0x0d:
gd54xx->overlay.colorkeycomparemask = val;
gd54xx_update_overlay(gd54xx);
break;
case 0x0e:
if (svga->crtc[0x27] >= CIRRUS_ID_CLGD5429) {
svga->dpms = (val & 0x06) && ((svga->miscout & ((val & 0x06) << 5)) != 0xc0);
svga_recalctimings(svga);
}
break;
case 0x10:
gd543x_mmio_write(0xb8001, val, gd54xx);
break;
case 0x11:
gd543x_mmio_write(0xb8005, val, gd54xx);
break;
case 0x12:
gd543x_mmio_write(0xb8002, val, gd54xx);
break;
case 0x13:
gd543x_mmio_write(0xb8006, val, gd54xx);
break;
case 0x14:
gd543x_mmio_write(0xb8003, val, gd54xx);
break;
case 0x15:
gd543x_mmio_write(0xb8007, val, gd54xx);
break;
case 0x20:
gd543x_mmio_write(0xb8008, val, gd54xx);
break;
case 0x21:
gd543x_mmio_write(0xb8009, val, gd54xx);
break;
case 0x22:
gd543x_mmio_write(0xb800a, val, gd54xx);
break;
case 0x23:
gd543x_mmio_write(0xb800b, val, gd54xx);
break;
case 0x24:
gd543x_mmio_write(0xb800c, val, gd54xx);
break;
case 0x25:
gd543x_mmio_write(0xb800d, val, gd54xx);
break;
case 0x26:
gd543x_mmio_write(0xb800e, val, gd54xx);
break;
case 0x27:
gd543x_mmio_write(0xb800f, val, gd54xx);
break;
case 0x28:
gd543x_mmio_write(0xb8010, val, gd54xx);
break;
case 0x29:
gd543x_mmio_write(0xb8011, val, gd54xx);
break;
case 0x2a:
gd543x_mmio_write(0xb8012, val, gd54xx);
break;
case 0x2c:
gd543x_mmio_write(0xb8014, val, gd54xx);
break;
case 0x2d:
gd543x_mmio_write(0xb8015, val, gd54xx);
break;
case 0x2e:
gd543x_mmio_write(0xb8016, val, gd54xx);
break;
case 0x2f:
gd543x_mmio_write(0xb8017, val, gd54xx);
break;
case 0x30:
gd543x_mmio_write(0xb8018, val, gd54xx);
break;
case 0x32:
gd543x_mmio_write(0xb801a, val, gd54xx);
break;
case 0x33:
gd543x_mmio_write(0xb801b, val, gd54xx);
break;
case 0x31:
gd543x_mmio_write(0xb8040, val, gd54xx);
break;
case 0x34:
gd543x_mmio_write(0xb801c, val, gd54xx);
break;
case 0x35:
gd543x_mmio_write(0xb801d, val, gd54xx);
break;
case 0x38:
gd543x_mmio_write(0xb8020, val, gd54xx);
break;
case 0x39:
gd543x_mmio_write(0xb8021, val, gd54xx);
break;
default:
break;
}
}
return;
case 0x3d4:
svga->crtcreg = val & gd54xx->crtcreg_mask;
return;
case 0x3d5:
if (((svga->crtcreg == 0x19) || (svga->crtcreg == 0x1a) || (svga->crtcreg == 0x1b) || (svga->crtcreg == 0x1d) || (svga->crtcreg == 0x25) || (svga->crtcreg == 0x27)) && !gd54xx->unlocked)
return;
if ((svga->crtcreg == 0x25) || (svga->crtcreg == 0x27))
return;
if ((svga->crtcreg < 7) && (svga->crtc[0x11] & 0x80))
return;
if ((svga->crtcreg == 7) && (svga->crtc[0x11] & 0x80))
val = (svga->crtc[7] & ~0x10) | (val & 0x10);
old = svga->crtc[svga->crtcreg];
svga->crtc[svga->crtcreg] = val;
if (svga->crtcreg == 0x11) {
if (!(val & 0x10)) {
if (gd54xx->vblank_irq > 0)
gd54xx->vblank_irq = -1;
} else if (gd54xx->vblank_irq < 0)
gd54xx->vblank_irq = 0;
gd54xx_update_irqs(gd54xx);
if ((val & ~0x30) == (old & ~0x30))
old = val;
}
if (old != val) {
/* Overlay registers */
switch (svga->crtcreg) {
case 0x1d:
if (((old >> 3) & 7) != ((val >> 3) & 7)) {
gd54xx->overlay.colorkeymode = (val >> 3) & 7;
gd54xx_update_overlay(gd54xx);
}
break;
case 0x31:
gd54xx->overlay.hzoom = val == 0 ? 256 : val;
gd54xx_update_overlay(gd54xx);
break;
case 0x32:
gd54xx->overlay.vzoom = val == 0 ? 256 : val;
gd54xx_update_overlay(gd54xx);
break;
case 0x33:
gd54xx->overlay.r1sz &= ~0xff;
gd54xx->overlay.r1sz |= val;
gd54xx_update_overlay(gd54xx);
break;
case 0x34:
gd54xx->overlay.r2sz &= ~0xff;
gd54xx->overlay.r2sz |= val;
gd54xx_update_overlay(gd54xx);
break;
case 0x35:
gd54xx->overlay.r2sdz &= ~0xff;
gd54xx->overlay.r2sdz |= val;
gd54xx_update_overlay(gd54xx);
break;
case 0x36:
gd54xx->overlay.r1sz &= 0xff;
gd54xx->overlay.r1sz |= (val << 8) & 0x300;
gd54xx->overlay.r2sz &= 0xff;
gd54xx->overlay.r2sz |= (val << 6) & 0x300;
gd54xx->overlay.r2sdz &= 0xff;
gd54xx->overlay.r2sdz |= (val << 4) & 0x300;
gd54xx_update_overlay(gd54xx);
break;
case 0x37:
gd54xx->overlay.wvs &= ~0xff;
gd54xx->overlay.wvs |= val;
svga->overlay.y = gd54xx->overlay.wvs;
break;
case 0x38:
gd54xx->overlay.wve &= ~0xff;
gd54xx->overlay.wve |= val;
gd54xx_update_overlay(gd54xx);
break;
case 0x39:
gd54xx->overlay.wvs &= 0xff;
gd54xx->overlay.wvs |= (val << 8) & 0x300;
gd54xx->overlay.wve &= 0xff;
gd54xx->overlay.wve |= (val << 6) & 0x300;
gd54xx_update_overlay(gd54xx);
break;
case 0x3a:
svga->overlay.addr &= ~0xff;
svga->overlay.addr |= val;
gd54xx_update_overlay(gd54xx);
break;
case 0x3b:
svga->overlay.addr &= ~0xff00;
svga->overlay.addr |= val << 8;
gd54xx_update_overlay(gd54xx);
break;
case 0x3c:
svga->overlay.addr &= ~0x0f0000;
svga->overlay.addr |= (val << 16) & 0x0f0000;
svga->overlay.pitch &= ~0x100;
svga->overlay.pitch |= (val & 0x20) << 3;
gd54xx_update_overlay(gd54xx);
break;
case 0x3d:
svga->overlay.pitch &= ~0xff;
svga->overlay.pitch |= val;
gd54xx_update_overlay(gd54xx);
break;
case 0x3e:
gd54xx->overlay.mode = (val >> 1) & 7;
svga->overlay.ena = (val & 1) != 0;
gd54xx_update_overlay(gd54xx);
break;
default:
break;
}
if (svga->crtcreg < 0xe || svga->crtcreg > 0x10) {
if ((svga->crtcreg == 0xc) || (svga->crtcreg == 0xd)) {
svga->fullchange = 3;
svga->ma_latch = ((svga->crtc[0xc] << 8) | svga->crtc[0xd]) + ((svga->crtc[8] & 0x60) >> 5);
} else {
svga->fullchange = changeframecount;
svga_recalctimings(svga);
}
}
}
break;
default:
break;
}
svga_out(addr, val, svga);
}
static uint8_t
gd54xx_in(uint16_t addr, void *priv)
{
gd54xx_t *gd54xx = (gd54xx_t *) priv;
svga_t *svga = &gd54xx->svga;
uint8_t index;
uint8_t ret = 0xff;
if (((addr & 0xfff0) == 0x3d0 || (addr & 0xfff0) == 0x3b0) && !(svga->miscout & 1))
addr ^= 0x60;
switch (addr) {
case 0x3c2:
ret = svga_in(addr, svga);
ret |= gd54xx->vblank_irq > 0 ? 0x80 : 0x00;
break;
case 0x3c4:
if (svga->seqregs[6] == 0x12) {
ret = svga->seqaddr;
if ((ret & 0x1e) == 0x10) {
if (ret & 1)
ret = ((svga->hwcursor.y & 7) << 5) | 0x11;
else
ret = ((svga->hwcursor.x & 7) << 5) | 0x10;
}
} else
ret = svga->seqaddr;
break;
case 0x3c5:
if ((svga->seqaddr == 2) && !gd54xx->unlocked)
ret = svga_in(addr, svga) & 0x0f;
else if ((svga->seqaddr > 6) && !gd54xx->unlocked)
ret = 0xff;
else if (svga->seqaddr > 5) {
ret = svga->seqregs[svga->seqaddr & 0x3f];
switch (svga->seqaddr) {
case 6:
ret = svga->seqregs[6];
break;
case 0x08:
if (gd54xx->i2c) {
ret &= 0x7b;
if (i2c_gpio_get_scl(gd54xx->i2c))
ret |= 0x04;
if (i2c_gpio_get_sda(gd54xx->i2c))
ret |= 0x80;
}
break;
case 0x0a: /*Scratch Pad 1 (Memory size for 5402/542x)*/
ret = svga->seqregs[0x0a] & ~0x1a;
if (svga->crtc[0x27] == CIRRUS_ID_CLGD5402) {
ret |= 0x01; /*512K of memory*/
} else if (svga->crtc[0x27] > CIRRUS_ID_CLGD5402) {
switch (gd54xx->vram_size >> 10) {
case 512:
ret |= 0x08;
break;
case 1024:
ret |= 0x10;
break;
case 2048:
ret |= 0x18;
break;
default:
break;
}
}
break;
case 0x0b:
case 0x0c:
case 0x0d:
case 0x0e:
ret = gd54xx->vclk_n[svga->seqaddr - 0x0b];
break;
case 0x0f: /*DRAM control*/
ret = svga->seqregs[0x0f] & ~0x98;
switch (gd54xx->vram_size >> 10) {
case 512:
ret |= 0x08; /*16-bit DRAM data bus width*/
break;
case 1024:
ret |= 0x10; /*32-bit DRAM data bus width for 1M of memory*/
break;
case 2048:
ret |= (gd54xx_is_5434(svga)) ? 0x98 : 0x18; /*32-bit (Pre-5434)/64-bit (5434 and up) DRAM data bus width for 2M of memory*/
break;
case 4096:
ret |= 0x98; /*64-bit (5434 and up) DRAM data bus width for 4M of memory*/
break;
default:
break;
}
break;
case 0x15: /*Scratch Pad 3 (Memory size for 543x)*/
ret = svga->seqregs[0x15] & ~0x0f;
if (svga->crtc[0x27] >= CIRRUS_ID_CLGD5430) {
switch (gd54xx->vram_size >> 20) {
case 1:
ret |= 0x02;
break;
case 2:
ret |= 0x03;
break;
case 4:
ret |= 0x04;
break;
default:
break;
}
}
break;
case 0x17:
ret = svga->seqregs[0x17] & ~(7 << 3);
if (svga->crtc[0x27] <= CIRRUS_ID_CLGD5429) {
if ((svga->crtc[0x27] == CIRRUS_ID_CLGD5428) || (svga->crtc[0x27] == CIRRUS_ID_CLGD5426)) {
if (gd54xx->vlb)
ret |= (CL_GD5428_SYSTEM_BUS_VESA << 3);
else if (gd54xx->mca)
ret |= (CL_GD5428_SYSTEM_BUS_MCA << 3);
else
ret |= (CL_GD5428_SYSTEM_BUS_ISA << 3);
} else {
if (gd54xx->vlb)
ret |= (CL_GD5429_SYSTEM_BUS_VESA << 3);
else
ret |= (CL_GD5429_SYSTEM_BUS_ISA << 3);
}
} else {
if (gd54xx->pci)
ret |= (CL_GD543X_SYSTEM_BUS_PCI << 3);
else if (gd54xx->vlb)
ret |= (CL_GD543X_SYSTEM_BUS_VESA << 3);
else
ret |= (CL_GD543X_SYSTEM_BUS_ISA << 3);
}
break;
case 0x18:
ret = svga->seqregs[0x18] & 0xfe;
break;
case 0x1b:
case 0x1c:
case 0x1d:
case 0x1e:
ret = gd54xx->vclk_d[svga->seqaddr - 0x1b];
break;
default:
break;
}
break;
} else
ret = svga_in(addr, svga);
break;
case 0x3c6:
if (!gd54xx->unlocked)
ret = svga_in(addr, svga);
else if (gd54xx->ramdac.state == 4) {
/* CL-GD 5428 does not lock the register when it's read. */
if (svga->crtc[0x27] != CIRRUS_ID_CLGD5428)
gd54xx->ramdac.state = 0;
ret = gd54xx->ramdac.ctrl;
} else {
gd54xx->ramdac.state++;
if (gd54xx->ramdac.state == 4)
ret = gd54xx->ramdac.ctrl;
else
ret = svga_in(addr, svga);
}
break;
case 0x3c7:
case 0x3c8:
gd54xx->ramdac.state = 0;
ret = svga_in(addr, svga);
break;
case 0x3c9:
gd54xx->ramdac.state = 0;
svga->dac_status = 3;
index = (svga->dac_addr - 1) & 0xff;
if (svga->seqregs[0x12] & 2)
index &= 0x0f;
switch (svga->dac_pos) {
case 0:
svga->dac_pos++;
if (svga->seqregs[0x12] & 2)
ret = gd54xx->extpal[index].r & 0x3f;
else
ret = svga->vgapal[index].r & 0x3f;
break;
case 1:
svga->dac_pos++;
if (svga->seqregs[0x12] & 2)
ret = gd54xx->extpal[index].g & 0x3f;
else
ret = svga->vgapal[index].g & 0x3f;
break;
case 2:
svga->dac_pos = 0;
svga->dac_addr = (svga->dac_addr + 1) & 255;
if (svga->seqregs[0x12] & 2)
ret = gd54xx->extpal[index].b & 0x3f;
else
ret = svga->vgapal[index].b & 0x3f;
break;
default:
break;
}
break;
case 0x3ce:
ret = svga->gdcaddr & 0x3f;
break;
case 0x3cf:
if (svga->gdcaddr >= 0x10) {
if ((svga->gdcaddr > 8) && !gd54xx->unlocked)
ret = 0xff;
else if ((svga->gdcaddr > 0x1f) && ((svga->crtc[0x27] <= CIRRUS_ID_CLGD5422) || (svga->crtc[0x27] == CIRRUS_ID_CLGD5424)))
ret = 0xff;
else
switch (svga->gdcaddr) {
case 0x10:
ret = gd543x_mmio_read(0xb8001, gd54xx);
break;
case 0x11:
ret = gd543x_mmio_read(0xb8005, gd54xx);
break;
case 0x12:
ret = gd543x_mmio_read(0xb8002, gd54xx);
break;
case 0x13:
ret = gd543x_mmio_read(0xb8006, gd54xx);
break;
case 0x14:
ret = gd543x_mmio_read(0xb8003, gd54xx);
break;
case 0x15:
ret = gd543x_mmio_read(0xb8007, gd54xx);
break;
case 0x20:
ret = gd543x_mmio_read(0xb8008, gd54xx);
break;
case 0x21:
ret = gd543x_mmio_read(0xb8009, gd54xx);
break;
case 0x22:
ret = gd543x_mmio_read(0xb800a, gd54xx);
break;
case 0x23:
ret = gd543x_mmio_read(0xb800b, gd54xx);
break;
case 0x24:
ret = gd543x_mmio_read(0xb800c, gd54xx);
break;
case 0x25:
ret = gd543x_mmio_read(0xb800d, gd54xx);
break;
case 0x26:
ret = gd543x_mmio_read(0xb800e, gd54xx);
break;
case 0x27:
ret = gd543x_mmio_read(0xb800f, gd54xx);
break;
case 0x28:
ret = gd543x_mmio_read(0xb8010, gd54xx);
break;
case 0x29:
ret = gd543x_mmio_read(0xb8011, gd54xx);
break;
case 0x2a:
ret = gd543x_mmio_read(0xb8012, gd54xx);
break;
case 0x2c:
ret = gd543x_mmio_read(0xb8014, gd54xx);
break;
case 0x2d:
ret = gd543x_mmio_read(0xb8015, gd54xx);
break;
case 0x2e:
ret = gd543x_mmio_read(0xb8016, gd54xx);
break;
case 0x2f:
ret = gd543x_mmio_read(0xb8017, gd54xx);
break;
case 0x30:
ret = gd543x_mmio_read(0xb8018, gd54xx);
break;
case 0x32:
ret = gd543x_mmio_read(0xb801a, gd54xx);
break;
case 0x33:
ret = gd543x_mmio_read(0xb801b, gd54xx);
break;
case 0x31:
ret = gd543x_mmio_read(0xb8040, gd54xx);
break;
case 0x34:
ret = gd543x_mmio_read(0xb801c, gd54xx);
break;
case 0x35:
ret = gd543x_mmio_read(0xb801d, gd54xx);
break;
case 0x38:
ret = gd543x_mmio_read(0xb8020, gd54xx);
break;
case 0x39:
ret = gd543x_mmio_read(0xb8021, gd54xx);
break;
case 0x3f:
if (svga->crtc[0x27] == CIRRUS_ID_CLGD5446)
gd54xx->vportsync = !gd54xx->vportsync;
ret = gd54xx->vportsync ? 0x80 : 0x00;
break;
default:
break;
}
} else {
if ((svga->gdcaddr < 2) && !gd54xx->unlocked)
ret = (svga->gdcreg[svga->gdcaddr] & 0x0f);
else {
if (svga->gdcaddr == 0)
ret = gd543x_mmio_read(0xb8000, gd54xx);
else if (svga->gdcaddr == 1)
ret = gd543x_mmio_read(0xb8004, gd54xx);
else
ret = svga->gdcreg[svga->gdcaddr];
}
}
break;
case 0x3d4:
ret = svga->crtcreg;
break;
case 0x3d5:
ret = svga->crtc[svga->crtcreg];
if (((svga->crtcreg == 0x19) || (svga->crtcreg == 0x1a) || (svga->crtcreg == 0x1b) || (svga->crtcreg == 0x1d) || (svga->crtcreg == 0x25) || (svga->crtcreg == 0x27)) && !gd54xx->unlocked)
ret = 0xff;
else
switch (svga->crtcreg) {
case 0x22: /*Graphics Data Latches Readback Register*/
/*Should this be & 7 if 8 byte latch is enabled? */
ret = svga->latch.b[svga->gdcreg[4] & 3];
break;
case 0x24: /*Attribute controller toggle readback (R)*/
ret = svga->attrff << 7;
break;
case 0x26: /*Attribute controller index readback (R)*/
ret = svga->attraddr & 0x3f;
break;
case 0x27: /*ID*/
ret = svga->crtc[0x27]; /*GD542x/GD543x*/
break;
case 0x28: /*Class ID*/
if ((svga->crtc[0x27] == CIRRUS_ID_CLGD5430) || (svga->crtc[0x27] == CIRRUS_ID_CLGD5440))
ret = 0xff; /*Standard CL-GD5430/40*/
break;
default:
break;
}
break;
default:
ret = svga_in(addr, svga);
break;
}
return ret;
}
static void
gd54xx_recalc_banking(gd54xx_t *gd54xx)
{
svga_t *svga = &gd54xx->svga;
if (!gd54xx_is_5422(svga)) {
svga->extra_banks[0] = (svga->gdcreg[0x09] & 0x7f) << 12;
if (svga->gdcreg[0x0b] & CIRRUS_BANKING_DUAL)
svga->extra_banks[1] = (svga->gdcreg[0x0a] & 0x7f) << 12;
else
svga->extra_banks[1] = svga->extra_banks[0] + 0x8000;
} else {
if ((svga->gdcreg[0x0b] & CIRRUS_BANKING_GRANULARITY_16K) && (svga->crtc[0x27] >= CIRRUS_ID_CLGD5426) && (svga->crtc[0x27] != CIRRUS_ID_CLGD5424))
svga->extra_banks[0] = svga->gdcreg[0x09] << 14;
else
svga->extra_banks[0] = svga->gdcreg[0x09] << 12;
if (svga->gdcreg[0x0b] & CIRRUS_BANKING_DUAL) {
if ((svga->gdcreg[0x0b] & CIRRUS_BANKING_GRANULARITY_16K) && (svga->crtc[0x27] >= CIRRUS_ID_CLGD5426) && (svga->crtc[0x27] != CIRRUS_ID_CLGD5424))
svga->extra_banks[1] = svga->gdcreg[0x0a] << 14;
else
svga->extra_banks[1] = svga->gdcreg[0x0a] << 12;
} else
svga->extra_banks[1] = svga->extra_banks[0] + 0x8000;
}
}
static void
gd543x_recalc_mapping(gd54xx_t *gd54xx)
{
svga_t *svga = &gd54xx->svga;
uint32_t base;
uint32_t size;
if (gd54xx->pci && (!(gd54xx->pci_regs[PCI_REG_COMMAND] & PCI_COMMAND_MEM))) {
mem_mapping_disable(&svga->mapping);
mem_mapping_disable(&gd54xx->linear_mapping);
mem_mapping_disable(&gd54xx->mmio_mapping);
return;
}
gd54xx->mmio_vram_overlap = 0;
if (!gd54xx_is_5422(svga) || !(svga->seqregs[0x07] & 0xf0) || !(svga->seqregs[0x07] & CIRRUS_SR7_BPP_SVGA)) {
mem_mapping_disable(&gd54xx->linear_mapping);
mem_mapping_disable(&gd54xx->aperture2_mapping);
switch (svga->gdcreg[6] & 0x0c) {
case 0x0: /*128k at A0000*/
mem_mapping_set_addr(&svga->mapping, 0xa0000, 0x20000);
svga->banked_mask = 0xffff;
break;
case 0x4: /*64k at A0000*/
mem_mapping_set_addr(&svga->mapping, 0xa0000, 0x10000);
svga->banked_mask = 0xffff;
break;
case 0x8: /*32k at B0000*/
mem_mapping_set_addr(&svga->mapping, 0xb0000, 0x08000);
svga->banked_mask = 0x7fff;
break;
case 0xC: /*32k at B8000*/
mem_mapping_set_addr(&svga->mapping, 0xb8000, 0x08000);
svga->banked_mask = 0x7fff;
gd54xx->mmio_vram_overlap = 1;
break;
default:
break;
}
if ((svga->seqregs[0x17] & CIRRUS_MMIO_ENABLE) && (svga->seqregs[0x07] & CIRRUS_SR7_BPP_SVGA) && (svga->crtc[0x27] >= CIRRUS_ID_CLGD5429)) {
if (gd54xx->mmio_vram_overlap) {
mem_mapping_disable(&svga->mapping);
mem_mapping_set_addr(&gd54xx->mmio_mapping, 0xb8000, 0x08000);
} else
mem_mapping_set_addr(&gd54xx->mmio_mapping, 0xb8000, 0x00100);
} else
mem_mapping_disable(&gd54xx->mmio_mapping);
} else {
if ((svga->crtc[0x27] <= CIRRUS_ID_CLGD5429) || (!gd54xx->pci && !gd54xx->vlb)) {
if (svga->gdcreg[0x0b] & CIRRUS_BANKING_GRANULARITY_16K) {
base = (svga->seqregs[0x07] & 0xf0) << 16;
size = 1 * 1024 * 1024;
} else {
base = (svga->seqregs[0x07] & 0xe0) << 16;
size = 2 * 1024 * 1024;
}
} else if (gd54xx->pci) {
base = gd54xx->lfb_base;
#if 0
if (svga->crtc[0x27] == CIRRUS_ID_CLGD5480)
size = 32 * 1024 * 1024;
else
#endif
if (svga->crtc[0x27] >= CIRRUS_ID_CLGD5436)
size = 16 * 1024 * 1024;
else
size = 4 * 1024 * 1024;
} else { /*VLB/ISA/MCA*/
base = 128 * 1024 * 1024;
if (svga->crtc[0x27] >= CIRRUS_ID_CLGD5436)
size = 16 * 1024 * 1024;
else
size = 4 * 1024 * 1024;
}
mem_mapping_disable(&svga->mapping);
mem_mapping_set_addr(&gd54xx->linear_mapping, base, size);
if ((svga->seqregs[0x17] & CIRRUS_MMIO_ENABLE) && (svga->crtc[0x27] >= CIRRUS_ID_CLGD5429)) {
if (svga->seqregs[0x17] & CIRRUS_MMIO_USE_PCIADDR)
mem_mapping_disable(&gd54xx->mmio_mapping); /* MMIO is handled in the linear read/write functions */
else
mem_mapping_set_addr(&gd54xx->mmio_mapping, 0xb8000, 0x00100);
} else
mem_mapping_disable(&gd54xx->mmio_mapping);
if ((svga->crtc[0x27] >= CIRRUS_ID_CLGD5436) && (gd54xx->blt.status & CIRRUS_BLT_APERTURE2) && ((gd54xx->blt.mode & (CIRRUS_BLTMODE_COLOREXPAND | CIRRUS_BLTMODE_MEMSYSSRC)) == (CIRRUS_BLTMODE_COLOREXPAND | CIRRUS_BLTMODE_MEMSYSSRC))) {
if (svga->crtc[0x27] == CIRRUS_ID_CLGD5480)
mem_mapping_set_addr(&gd54xx->aperture2_mapping, gd54xx->lfb_base + 16777216, 16777216);
else
mem_mapping_set_addr(&gd54xx->aperture2_mapping, 0xbc000, 0x04000);
} else
mem_mapping_disable(&gd54xx->aperture2_mapping);
}
}
static void
gd54xx_recalctimings(svga_t *svga)
{
const gd54xx_t *gd54xx = (gd54xx_t *) svga->priv;
uint8_t clocksel;
uint8_t rdmask;
uint8_t linedbl = svga->dispend * 9 / 10 >= svga->hdisp;
svga->hblankstart = svga->crtc[2];
if (svga->crtc[0x1b] & ((svga->crtc[0x27] >= CIRRUS_ID_CLGD5424) ? 0xa0 : 0x20)) {
/* Special blanking mode: the blank start and end become components of the window generator,
and the actual blanking comes from the display enable signal. */
/* This means blanking during overscan, we already calculate it that way, so just use the
same calculation and force otvercan to 0. */
svga->hblank_end_val = (svga->crtc[3] & 0x1f) | ((svga->crtc[5] & 0x80) ? 0x20 : 0x00) |
(((svga->crtc[0x1a] >> 4) & 3) << 6);
svga->hblank_end_mask = 0x000000ff;
if (svga->crtc[0x1b] & 0x20) {
svga->hblankstart = svga->crtc[1]/* + ((svga->crtc[3] >> 5) & 3) + 1*/;
svga->hblank_end_val = svga->htotal - 1 /* + ((svga->crtc[3] >> 5) & 3)*/;
/* In this mode, the dots per clock are always 8 or 16, never 9 or 18. */
if (!svga->scrblank && svga->attr_palette_enable)
svga->dots_per_clock = (svga->seqregs[1] & 8) ? 16 : 8;
svga->monitor->mon_overscan_y = 0;
svga->monitor->mon_overscan_x = 0;
/* Also make sure vertical blanking starts on display end. */
svga->vblankstart = svga->dispend;
}
}
svga->rowoffset = (svga->crtc[0x13]) | (((int) (uint32_t) (svga->crtc[0x1b] & 0x10)) << 4);
svga->interlace = (svga->crtc[0x1a] & 0x01);
if (!(svga->gdcreg[6] & 1) && !(svga->attrregs[0x10] & 1)) { /*Text mode*/
svga->interlace = 0;
}
svga->map8 = svga->pallook;
if (svga->seqregs[0x07] & CIRRUS_SR7_BPP_SVGA) {
if (linedbl)
svga->render = svga_render_8bpp_lowres;
else {
svga->render = svga_render_8bpp_highres;
if ((svga->dispend == 512) && !svga->interlace && gd54xx_is_5434(svga)) {
svga->hdisp <<= 1;
svga->dots_per_clock <<= 1;
}
}
} else if (svga->gdcreg[5] & 0x40)
svga->render = svga_render_8bpp_lowres;
svga->ma_latch |= ((svga->crtc[0x1b] & 0x01) << 16) | ((svga->crtc[0x1b] & 0xc) << 15);
svga->bpp = 8;
if (gd54xx->ramdac.ctrl & 0x80) {
if (gd54xx->ramdac.ctrl & 0x40) {
if ((svga->crtc[0x27] >= CIRRUS_ID_CLGD5428) || (svga->crtc[0x27] == CIRRUS_ID_CLGD5426))
rdmask = 0xf;
else
rdmask = 0x7;
switch (gd54xx->ramdac.ctrl & rdmask) {
case 0:
svga->bpp = 15;
if (linedbl) {
if (gd54xx->ramdac.ctrl & 0x10)
svga->render = svga_render_15bpp_mix_lowres;
else
svga->render = svga_render_15bpp_lowres;
} else {
if (gd54xx->ramdac.ctrl & 0x10)
svga->render = svga_render_15bpp_mix_highres;
else
svga->render = svga_render_15bpp_highres;
}
break;
case 1:
svga->bpp = 16;
if (linedbl)
svga->render = svga_render_16bpp_lowres;
else
svga->render = svga_render_16bpp_highres;
break;
case 5:
if (gd54xx_is_5434(svga) && (svga->seqregs[0x07] & CIRRUS_SR7_BPP_32)) {
svga->bpp = 32;
if (linedbl)
svga->render = svga_render_32bpp_lowres;
else
svga->render = svga_render_32bpp_highres;
if (svga->crtc[0x27] < CIRRUS_ID_CLGD5436) {
svga->rowoffset *= 2;
}
} else {
svga->bpp = 24;
if (linedbl)
svga->render = svga_render_24bpp_lowres;
else
svga->render = svga_render_24bpp_highres;
}
break;
case 8:
svga->bpp = 8;
svga->map8 = video_8togs;
if (linedbl)
svga->render = svga_render_8bpp_lowres;
else
svga->render = svga_render_8bpp_highres;
break;
case 9:
svga->bpp = 8;
svga->map8 = video_8to32;
if (linedbl)
svga->render = svga_render_8bpp_lowres;
else
svga->render = svga_render_8bpp_highres;
break;
case 0xf:
switch (svga->seqregs[0x07] & CIRRUS_SR7_BPP_MASK) {
case CIRRUS_SR7_BPP_32:
if (svga->crtc[0x27] >= CIRRUS_ID_CLGD5430) {
svga->bpp = 32;
if (linedbl)
svga->render = svga_render_32bpp_lowres;
else
svga->render = svga_render_32bpp_highres;
svga->rowoffset *= 2;
}
break;
case CIRRUS_SR7_BPP_24:
svga->bpp = 24;
if (linedbl)
svga->render = svga_render_24bpp_lowres;
else
svga->render = svga_render_24bpp_highres;
break;
case CIRRUS_SR7_BPP_16:
if ((svga->crtc[0x27] >= CIRRUS_ID_CLGD5428) || (svga->crtc[0x27] == CIRRUS_ID_CLGD5426)) {
svga->bpp = 16;
if (linedbl)
svga->render = svga_render_16bpp_lowres;
else
svga->render = svga_render_16bpp_highres;
}
break;
case CIRRUS_SR7_BPP_16_DOUBLEVCLK:
svga->bpp = 16;
if (linedbl)
svga->render = svga_render_16bpp_lowres;
else
svga->render = svga_render_16bpp_highres;
break;
case CIRRUS_SR7_BPP_8:
svga->bpp = 8;
if (linedbl)
svga->render = svga_render_8bpp_lowres;
else
svga->render = svga_render_8bpp_highres;
break;
default:
break;
}
break;
default:
break;
}
} else {
svga->bpp = 15;
if (linedbl) {
if (gd54xx->ramdac.ctrl & 0x10)
svga->render = svga_render_15bpp_mix_lowres;
else
svga->render = svga_render_15bpp_lowres;
} else {
if (gd54xx->ramdac.ctrl & 0x10)
svga->render = svga_render_15bpp_mix_highres;
else
svga->render = svga_render_15bpp_highres;
}
}
}
clocksel = (svga->miscout >> 2) & 3;
if (!gd54xx->vclk_n[clocksel] || !gd54xx->vclk_d[clocksel])
svga->clock = (cpuclock * (float) (1ULL << 32)) / ((svga->miscout & 0xc) ? 28322000.0 : 25175000.0);
else {
int n = gd54xx->vclk_n[clocksel] & 0x7f;
int d = (gd54xx->vclk_d[clocksel] & 0x3e) >> 1;
uint8_t m = gd54xx->vclk_d[clocksel] & 0x01 ? 2 : 1;
float freq = (14318184.0F * ((float) n / ((float) d * m)));
if (gd54xx_is_5422(svga)) {
switch (svga->seqregs[0x07] & (gd54xx_is_5434(svga) ? 0xe : 6)) {
case 2:
freq /= 2.0F;
break;
case 4:
if (!gd54xx_is_5434(svga))
freq /= 3.0F;
break;
default:
break;
}
}
svga->clock = (cpuclock * (double) (1ULL << 32)) / freq;
}
svga->vram_display_mask = (svga->crtc[0x1b] & 2) ? gd54xx->vram_mask : 0x3ffff;
if (svga->crtc[0x27] >= CIRRUS_ID_CLGD5430)
svga->htotal += ((svga->crtc[0x1c] >> 3) & 0x07);
if (!(svga->gdcreg[6] & 1) && !(svga->attrregs[0x10] & 1)) { /*Text mode*/
if (svga->seqregs[1] & 8)
svga->render = svga_render_text_40;
else
svga->render = svga_render_text_80;
}
if (!(svga->seqregs[0x07] & CIRRUS_SR7_BPP_SVGA)) {
svga->extra_banks[0] = 0;
svga->extra_banks[1] = 0x8000;
}
}
static void
gd54xx_hwcursor_draw(svga_t *svga, int displine)
{
const gd54xx_t *gd54xx = (gd54xx_t *) svga->priv;
int comb;
int b0;
int b1;
uint8_t dat[2];
int offset = svga->hwcursor_latch.x - svga->hwcursor_latch.xoff;
int pitch = (svga->hwcursor.cur_xsize == 64) ? 16 : 4;
uint32_t bgcol = gd54xx->extpallook[0x00];
uint32_t fgcol = gd54xx->extpallook[0x0f];
uint8_t linedbl = svga->dispend * 9 / 10 >= svga->hdisp;
offset <<= linedbl;
if (svga->interlace && svga->hwcursor_oddeven)
svga->hwcursor_latch.addr += pitch;
for (int x = 0; x < svga->hwcursor.cur_xsize; x += 8) {
dat[0] = svga->vram[svga->hwcursor_latch.addr & gd54xx->vram_mask];
if (svga->hwcursor.cur_xsize == 64)
dat[1] = svga->vram[(svga->hwcursor_latch.addr + 0x08) & gd54xx->vram_mask];
else
dat[1] = svga->vram[(svga->hwcursor_latch.addr + 0x80) & gd54xx->vram_mask];
for (uint8_t xx = 0; xx < 8; xx++) {
b0 = (dat[0] >> (7 - xx)) & 1;
b1 = (dat[1] >> (7 - xx)) & 1;
comb = (b1 | (b0 << 1));
if (offset >= svga->hwcursor_latch.x) {
switch (comb) {
case 0:
/* The original screen pixel is shown (invisible cursor) */
break;
case 1:
/* The pixel is shown in the cursor background color */
(svga->monitor->target_buffer->line[displine])[offset + svga->x_add] = bgcol;
break;
case 2:
/* The pixel is shown as the inverse of the original screen pixel
(XOR cursor) */
(svga->monitor->target_buffer->line[displine])[offset + svga->x_add] ^= 0xffffff;
break;
case 3:
/* The pixel is shown in the cursor foreground color */
(svga->monitor->target_buffer->line[displine])[offset + svga->x_add] = fgcol;
break;
default:
break;
}
}
offset++;
}
svga->hwcursor_latch.addr++;
}
if (svga->hwcursor.cur_xsize == 64)
svga->hwcursor_latch.addr += 8;
if (svga->interlace && !svga->hwcursor_oddeven)
svga->hwcursor_latch.addr += pitch;
}
static void
gd54xx_rop(gd54xx_t *gd54xx, uint8_t *res, uint8_t *dst, const uint8_t *src)
{
switch (gd54xx->blt.rop) {
case 0x00:
*res = 0x00;
break;
case 0x05:
*res = *src & *dst;
break;
case 0x06:
*res = *dst;
break;
case 0x09:
*res = *src & ~*dst;
break;
case 0x0b:
*res = ~*dst;
break;
case 0x0d:
*res = *src;
break;
case 0x0e:
*res = 0xff;
break;
case 0x50:
*res = ~*src & *dst;
break;
case 0x59:
*res = *src ^ *dst;
break;
case 0x6d:
*res = *src | *dst;
break;
case 0x90:
*res = ~(*src | *dst);
break;
case 0x95:
*res = ~(*src ^ *dst);
break;
case 0xad:
*res = *src | ~*dst;
break;
case 0xd0:
*res = ~*src;
break;
case 0xd6:
*res = ~*src | *dst;
break;
case 0xda:
*res = ~(*src & *dst);
break;
default:
break;
}
}
static uint8_t
gd54xx_get_aperture(uint32_t addr)
{
uint32_t ap = addr >> 22;
return (uint8_t) (ap & 0x03);
}
static uint32_t
gd54xx_mem_sys_pos_adj(gd54xx_t *gd54xx, uint8_t ap, uint32_t pos)
{
uint32_t ret = pos;
if ((gd54xx->blt.mode & CIRRUS_BLTMODE_COLOREXPAND) &&
!(gd54xx->blt.modeext & CIRRUS_BLTMODEEXT_DWORDGRANULARITY)) {
switch (ap) {
case 1:
ret ^= 1;
break;
case 2:
ret ^= 3;
break;
}
}
return ret;
}
static uint8_t
gd54xx_mem_sys_dest_read(gd54xx_t *gd54xx, uint8_t ap)
{
uint32_t adj_pos = gd54xx_mem_sys_pos_adj(gd54xx, ap, gd54xx->blt.msd_buf_pos);
uint8_t ret = 0xff;
if (gd54xx->blt.msd_buf_cnt != 0) {
ret = gd54xx->blt.msd_buf[adj_pos];
gd54xx->blt.msd_buf_pos++;
gd54xx->blt.msd_buf_cnt--;
if (gd54xx->blt.msd_buf_cnt == 0) {
if (gd54xx->countminusone == 1) {
gd54xx->blt.msd_buf_pos = 0;
if ((gd54xx->blt.mode & CIRRUS_BLTMODE_COLOREXPAND) &&
!(gd54xx->blt.modeext & CIRRUS_BLTMODEEXT_DWORDGRANULARITY))
gd54xx_start_blit(0xff, 8, gd54xx, &gd54xx->svga);
else
gd54xx_start_blit(0xffffffff, 32, gd54xx, &gd54xx->svga);
} else
gd54xx_reset_blit(gd54xx); /* End of blit, do no more. */
}
}
return ret;
}
static void
gd54xx_mem_sys_src_write(gd54xx_t *gd54xx, uint8_t val, uint8_t ap)
{
uint32_t adj_pos = gd54xx_mem_sys_pos_adj(gd54xx, ap, gd54xx->blt.sys_cnt);
gd54xx->blt.sys_src32 &= ~(0xff << (adj_pos << 3));
gd54xx->blt.sys_src32 |= (val << (adj_pos << 3));
gd54xx->blt.sys_cnt = (gd54xx->blt.sys_cnt + 1) & 3;
if (gd54xx->blt.sys_cnt == 0) {
if ((gd54xx->blt.mode & CIRRUS_BLTMODE_COLOREXPAND) &&
!(gd54xx->blt.modeext & CIRRUS_BLTMODEEXT_DWORDGRANULARITY)) {
for (uint8_t i = 0; i < 32; i += 8)
gd54xx_start_blit((gd54xx->blt.sys_src32 >> i) & 0xff, 8, gd54xx, &gd54xx->svga);
} else
gd54xx_start_blit(gd54xx->blt.sys_src32, 32, gd54xx, &gd54xx->svga);
}
}
static void
gd54xx_write(uint32_t addr, uint8_t val, void *priv)
{
gd54xx_t *gd54xx = (gd54xx_t *) priv;
svga_t *svga = &gd54xx->svga;
if (gd54xx->countminusone && !gd54xx->blt.ms_is_dest && !(gd54xx->blt.status & CIRRUS_BLT_PAUSED)) {
gd54xx_mem_sys_src_write(gd54xx, val, 0);
return;
}
addr &= svga->banked_mask;
addr = (addr & 0x7fff) + svga->extra_banks[(addr >> 15) & 1];
svga_write_linear(addr, val, svga);
}
static void
gd54xx_writew(uint32_t addr, uint16_t val, void *priv)
{
gd54xx_t *gd54xx = (gd54xx_t *) priv;
svga_t *svga = &gd54xx->svga;
if (gd54xx->countminusone && !gd54xx->blt.ms_is_dest && !(gd54xx->blt.status & CIRRUS_BLT_PAUSED)) {
gd54xx_write(addr, val, gd54xx);
gd54xx_write(addr + 1, val >> 8, gd54xx);
return;
}
addr &= svga->banked_mask;
addr = (addr & 0x7fff) + svga->extra_banks[(addr >> 15) & 1];
if (svga->writemode < 4)
svga_writew_linear(addr, val, svga);
else {
svga_write_linear(addr, val, svga);
svga_write_linear(addr + 1, val >> 8, svga);
}
}
static void
gd54xx_writel(uint32_t addr, uint32_t val, void *priv)
{
gd54xx_t *gd54xx = (gd54xx_t *) priv;
svga_t *svga = &gd54xx->svga;
if (gd54xx->countminusone && !gd54xx->blt.ms_is_dest && !(gd54xx->blt.status & CIRRUS_BLT_PAUSED)) {
gd54xx_write(addr, val, gd54xx);
gd54xx_write(addr + 1, val >> 8, gd54xx);
gd54xx_write(addr + 2, val >> 16, gd54xx);
gd54xx_write(addr + 3, val >> 24, gd54xx);
return;
}
addr &= svga->banked_mask;
addr = (addr & 0x7fff) + svga->extra_banks[(addr >> 15) & 1];
if (svga->writemode < 4)
svga_writel_linear(addr, val, svga);
else {
svga_write_linear(addr, val, svga);
svga_write_linear(addr + 1, val >> 8, svga);
svga_write_linear(addr + 2, val >> 16, svga);
svga_write_linear(addr + 3, val >> 24, svga);
}
}
/* This adds write modes 4 and 5 to SVGA. */
static void
gd54xx_write_modes45(svga_t *svga, uint8_t val, uint32_t addr)
{
uint32_t i;
uint32_t j;
switch (svga->writemode) {
case 4:
if (svga->adv_flags & FLAG_ADDR_BY16) {
addr &= svga->decode_mask;
for (i = 0; i < 8; i++) {
if (val & svga->seqregs[2] & (0x80 >> i)) {
svga->vram[addr + (i << 1)] = svga->gdcreg[1];
svga->vram[addr + (i << 1) + 1] = svga->gdcreg[0x11];
}
}
} else {
addr <<= 1;
addr &= svga->decode_mask;
for (i = 0; i < 8; i++) {
if (val & svga->seqregs[2] & (0x80 >> i))
svga->vram[addr + i] = svga->gdcreg[1];
}
}
break;
case 5:
if (svga->adv_flags & FLAG_ADDR_BY16) {
addr &= svga->decode_mask;
for (i = 0; i < 8; i++) {
j = (0x80 >> i);
if (svga->seqregs[2] & j) {
svga->vram[addr + (i << 1)] = (val & j) ? svga->gdcreg[1] : svga->gdcreg[0];
svga->vram[addr + (i << 1) + 1] = (val & j) ? svga->gdcreg[0x11] : svga->gdcreg[0x10];
}
}
} else {
addr <<= 1;
addr &= svga->decode_mask;
for (i = 0; i < 8; i++) {
j = (0x80 >> i);
if (svga->seqregs[2] & j)
svga->vram[addr + i] = (val & j) ? svga->gdcreg[1] : svga->gdcreg[0];
}
}
break;
default:
break;
}
svga->changedvram[addr >> 12] = changeframecount;
}
static int
gd54xx_aperture2_enabled(gd54xx_t *gd54xx)
{
const svga_t *svga = &gd54xx->svga;
if (svga->crtc[0x27] < CIRRUS_ID_CLGD5436)
return 0;
if (!(gd54xx->blt.mode & CIRRUS_BLTMODE_COLOREXPAND))
return 0;
if (!(gd54xx->blt.status & CIRRUS_BLT_APERTURE2))
return 0;
return 1;
}
static uint8_t
gd54xx_readb_linear(uint32_t addr, void *priv)
{
gd54xx_t *gd54xx = (gd54xx_t *) priv;
svga_t *svga = &gd54xx->svga;
uint8_t ap = gd54xx_get_aperture(addr);
addr &= 0x003fffff; /* 4 MB mask */
if (!(svga->seqregs[0x07] & CIRRUS_SR7_BPP_SVGA))
return svga_read_linear(addr, svga);
if ((addr >= (svga->vram_max - 256)) && (addr < svga->vram_max)) {
if ((svga->seqregs[0x17] & CIRRUS_MMIO_ENABLE) && (svga->seqregs[0x17] & CIRRUS_MMIO_USE_PCIADDR))
return gd543x_mmio_read(addr & 0x000000ff, gd54xx);
}
/* Do mem sys dest reads here if the blitter is neither paused, nor is there a second aperture. */
if (gd54xx->countminusone && gd54xx->blt.ms_is_dest && !gd54xx_aperture2_enabled(gd54xx) && !(gd54xx->blt.status & CIRRUS_BLT_PAUSED))
return gd54xx_mem_sys_dest_read(gd54xx, ap);
switch (ap) {
default:
case 0:
break;
case 1:
/* 0 -> 1, 1 -> 0, 2 -> 3, 3 -> 2 */
addr ^= 0x00000001;
break;
case 2:
/* 0 -> 3, 1 -> 2, 2 -> 1, 3 -> 0 */
addr ^= 0x00000003;
break;
case 3:
return 0xff;
}
return svga_read_linear(addr, svga);
}
static uint16_t
gd54xx_readw_linear(uint32_t addr, void *priv)
{
gd54xx_t *gd54xx = (gd54xx_t *) priv;
svga_t *svga = &gd54xx->svga;
uint32_t old_addr = addr;
uint8_t ap = gd54xx_get_aperture(addr);
uint16_t temp;
addr &= 0x003fffff; /* 4 MB mask */
if (!(svga->seqregs[0x07] & CIRRUS_SR7_BPP_SVGA))
return svga_readw_linear(addr, svga);
if ((addr >= (svga->vram_max - 256)) && (addr < svga->vram_max)) {
if ((svga->seqregs[0x17] & CIRRUS_MMIO_ENABLE) && (svga->seqregs[0x17] & CIRRUS_MMIO_USE_PCIADDR)) {
temp = gd543x_mmio_readw(addr & 0x000000ff, gd54xx);
return temp;
}
}
/* Do mem sys dest reads here if the blitter is neither paused, nor is there a second aperture. */
if (gd54xx->countminusone && gd54xx->blt.ms_is_dest && !gd54xx_aperture2_enabled(gd54xx) && !(gd54xx->blt.status & CIRRUS_BLT_PAUSED)) {
temp = gd54xx_readb_linear(old_addr, priv);
temp |= gd54xx_readb_linear(old_addr + 1, priv) << 8;
return temp;
}
switch (ap) {
default:
case 0:
return svga_readw_linear(addr, svga);
case 2:
/* 0 -> 3, 1 -> 2, 2 -> 1, 3 -> 0 */
addr ^= 0x00000002;
fallthrough;
case 1:
temp = svga_readb_linear(addr + 1, svga);
temp |= (svga_readb_linear(addr, svga) << 8);
if (svga->fast)
cycles -= svga->monitor->mon_video_timing_read_w;
return temp;
case 3:
return 0xffff;
}
}
static uint32_t
gd54xx_readl_linear(uint32_t addr, void *priv)
{
gd54xx_t *gd54xx = (gd54xx_t *) priv;
svga_t *svga = &gd54xx->svga;
uint32_t old_addr = addr;
uint8_t ap = gd54xx_get_aperture(addr);
uint32_t temp;
addr &= 0x003fffff; /* 4 MB mask */
if (!(svga->seqregs[0x07] & CIRRUS_SR7_BPP_SVGA))
return svga_readl_linear(addr, svga);
if ((addr >= (svga->vram_max - 256)) && (addr < svga->vram_max)) {
if ((svga->seqregs[0x17] & CIRRUS_MMIO_ENABLE) && (svga->seqregs[0x17] & CIRRUS_MMIO_USE_PCIADDR)) {
temp = gd543x_mmio_readl(addr & 0x000000ff, gd54xx);
return temp;
}
}
/* Do mem sys dest reads here if the blitter is neither paused, nor is there a second aperture. */
if (gd54xx->countminusone && gd54xx->blt.ms_is_dest && !gd54xx_aperture2_enabled(gd54xx) && !(gd54xx->blt.status & CIRRUS_BLT_PAUSED)) {
temp = gd54xx_readb_linear(old_addr, priv);
temp |= gd54xx_readb_linear(old_addr + 1, priv) << 8;
temp |= gd54xx_readb_linear(old_addr + 2, priv) << 16;
temp |= gd54xx_readb_linear(old_addr + 3, priv) << 24;
return temp;
}
switch (ap) {
default:
case 0:
return svga_readl_linear(addr, svga);
case 1:
temp = svga_readb_linear(addr + 1, svga);
temp |= (svga_readb_linear(addr, svga) << 8);
temp |= (svga_readb_linear(addr + 3, svga) << 16);
temp |= (svga_readb_linear(addr + 2, svga) << 24);
if (svga->fast)
cycles -= svga->monitor->mon_video_timing_read_l;
return temp;
case 2:
temp = svga_readb_linear(addr + 3, svga);
temp |= (svga_readb_linear(addr + 2, svga) << 8);
temp |= (svga_readb_linear(addr + 1, svga) << 16);
temp |= (svga_readb_linear(addr, svga) << 24);
if (svga->fast)
cycles -= svga->monitor->mon_video_timing_read_l;
return temp;
case 3:
return 0xffffffff;
}
}
static uint8_t
gd5436_aperture2_readb(UNUSED(uint32_t addr), void *priv)
{
gd54xx_t *gd54xx = (gd54xx_t *) priv;
uint8_t ap = gd54xx_get_aperture(addr);
if (gd54xx->countminusone && gd54xx->blt.ms_is_dest &&
gd54xx_aperture2_enabled(gd54xx) && !(gd54xx->blt.status & CIRRUS_BLT_PAUSED))
return gd54xx_mem_sys_dest_read(gd54xx, ap);
return 0xff;
}
static uint16_t
gd5436_aperture2_readw(uint32_t addr, void *priv)
{
gd54xx_t *gd54xx = (gd54xx_t *) priv;
uint16_t ret = 0xffff;
if (gd54xx->countminusone && gd54xx->blt.ms_is_dest &&
gd54xx_aperture2_enabled(gd54xx) && !(gd54xx->blt.status & CIRRUS_BLT_PAUSED)) {
ret = gd5436_aperture2_readb(addr, priv);
ret |= gd5436_aperture2_readb(addr + 1, priv) << 8;
return ret;
}
return ret;
}
static uint32_t
gd5436_aperture2_readl(uint32_t addr, void *priv)
{
gd54xx_t *gd54xx = (gd54xx_t *) priv;
uint32_t ret = 0xffffffff;
if (gd54xx->countminusone && gd54xx->blt.ms_is_dest &&
gd54xx_aperture2_enabled(gd54xx) && !(gd54xx->blt.status & CIRRUS_BLT_PAUSED)) {
ret = gd5436_aperture2_readb(addr, priv);
ret |= gd5436_aperture2_readb(addr + 1, priv) << 8;
ret |= gd5436_aperture2_readb(addr + 2, priv) << 16;
ret |= gd5436_aperture2_readb(addr + 3, priv) << 24;
return ret;
}
return ret;
}
static void
gd5436_aperture2_writeb(UNUSED(uint32_t addr), uint8_t val, void *priv)
{
gd54xx_t *gd54xx = (gd54xx_t *) priv;
uint8_t ap = gd54xx_get_aperture(addr);
if (gd54xx->countminusone && !gd54xx->blt.ms_is_dest &&
gd54xx_aperture2_enabled(gd54xx) && !(gd54xx->blt.status & CIRRUS_BLT_PAUSED))
gd54xx_mem_sys_src_write(gd54xx, val, ap);
}
static void
gd5436_aperture2_writew(uint32_t addr, uint16_t val, void *priv)
{
gd54xx_t *gd54xx = (gd54xx_t *) priv;
if (gd54xx->countminusone && !gd54xx->blt.ms_is_dest &&
gd54xx_aperture2_enabled(gd54xx) && !(gd54xx->blt.status & CIRRUS_BLT_PAUSED)) {
gd5436_aperture2_writeb(addr, val, gd54xx);
gd5436_aperture2_writeb(addr + 1, val >> 8, gd54xx);
}
}
static void
gd5436_aperture2_writel(uint32_t addr, uint32_t val, void *priv)
{
gd54xx_t *gd54xx = (gd54xx_t *) priv;
if (gd54xx->countminusone && !gd54xx->blt.ms_is_dest &&
gd54xx_aperture2_enabled(gd54xx) && !(gd54xx->blt.status & CIRRUS_BLT_PAUSED)) {
gd5436_aperture2_writeb(addr, val, gd54xx);
gd5436_aperture2_writeb(addr + 1, val >> 8, gd54xx);
gd5436_aperture2_writeb(addr + 2, val >> 16, gd54xx);
gd5436_aperture2_writeb(addr + 3, val >> 24, gd54xx);
}
}
static void
gd54xx_writeb_linear(uint32_t addr, uint8_t val, void *priv)
{
gd54xx_t *gd54xx = (gd54xx_t *) priv;
svga_t *svga = &gd54xx->svga;
uint8_t ap = gd54xx_get_aperture(addr);
if (!(svga->seqregs[0x07] & CIRRUS_SR7_BPP_SVGA)) {
svga_write_linear(addr, val, svga);
return;
}
addr &= 0x003fffff; /* 4 MB mask */
if ((addr >= (svga->vram_max - 256)) && (addr < svga->vram_max)) {
if ((svga->seqregs[0x17] & CIRRUS_MMIO_ENABLE) && (svga->seqregs[0x17] & CIRRUS_MMIO_USE_PCIADDR)) {
gd543x_mmio_write(addr & 0x000000ff, val, gd54xx);
return;
}
}
/* Do mem sys src writes here if the blitter is neither paused, nor is there a second aperture. */
if (gd54xx->countminusone && !gd54xx->blt.ms_is_dest && !gd54xx_aperture2_enabled(gd54xx) && !(gd54xx->blt.status & CIRRUS_BLT_PAUSED)) {
gd54xx_mem_sys_src_write(gd54xx, val, ap);
return;
}
switch (ap) {
default:
case 0:
break;
case 1:
/* 0 -> 1, 1 -> 0, 2 -> 3, 3 -> 2 */
addr ^= 0x00000001;
break;
case 2:
/* 0 -> 3, 1 -> 2, 2 -> 1, 3 -> 0 */
addr ^= 0x00000003;
break;
case 3:
return;
}
svga_write_linear(addr, val, svga);
}
static void
gd54xx_writew_linear(uint32_t addr, uint16_t val, void *priv)
{
gd54xx_t *gd54xx = (gd54xx_t *) priv;
svga_t *svga = &gd54xx->svga;
uint32_t old_addr = addr;
uint8_t ap = gd54xx_get_aperture(addr);
if (!(svga->seqregs[0x07] & CIRRUS_SR7_BPP_SVGA)) {
svga_writew_linear(addr, val, svga);
return;
}
addr &= 0x003fffff; /* 4 MB mask */
if ((addr >= (svga->vram_max - 256)) && (addr < svga->vram_max)) {
if ((svga->seqregs[0x17] & CIRRUS_MMIO_ENABLE) && (svga->seqregs[0x17] & CIRRUS_MMIO_USE_PCIADDR)) {
gd543x_mmio_writew(addr & 0x000000ff, val, gd54xx);
return;
}
}
/* Do mem sys src writes here if the blitter is neither paused, nor is there a second aperture. */
if (gd54xx->countminusone && !gd54xx->blt.ms_is_dest && !gd54xx_aperture2_enabled(gd54xx) && !(gd54xx->blt.status & CIRRUS_BLT_PAUSED)) {
gd54xx_writeb_linear(old_addr, val, gd54xx);
gd54xx_writeb_linear(old_addr + 1, val >> 8, gd54xx);
return;
}
if (svga->writemode < 4) {
switch (ap) {
default:
case 0:
svga_writew_linear(addr, val, svga);
return;
case 2:
addr ^= 0x00000002;
case 1:
svga_writeb_linear(addr + 1, val & 0xff, svga);
svga_writeb_linear(addr, val >> 8, svga);
if (svga->fast)
cycles -= svga->monitor->mon_video_timing_write_w;
return;
case 3:
return;
}
} else {
switch (ap) {
default:
case 0:
svga_write_linear(addr, val & 0xff, svga);
svga_write_linear(addr + 1, val >> 8, svga);
return;
case 2:
addr ^= 0x00000002;
fallthrough;
case 1:
svga_write_linear(addr + 1, val & 0xff, svga);
svga_write_linear(addr, val >> 8, svga);
return;
case 3:
return;
}
}
}
static void
gd54xx_writel_linear(uint32_t addr, uint32_t val, void *priv)
{
gd54xx_t *gd54xx = (gd54xx_t *) priv;
svga_t *svga = &gd54xx->svga;
uint32_t old_addr = addr;
uint8_t ap = gd54xx_get_aperture(addr);
if (!(svga->seqregs[0x07] & CIRRUS_SR7_BPP_SVGA)) {
svga_writel_linear(addr, val, svga);
return;
}
addr &= 0x003fffff; /* 4 MB mask */
if ((addr >= (svga->vram_max - 256)) && (addr < svga->vram_max)) {
if ((svga->seqregs[0x17] & CIRRUS_MMIO_ENABLE) && (svga->seqregs[0x17] & CIRRUS_MMIO_USE_PCIADDR)) {
gd543x_mmio_writel(addr & 0x000000ff, val, gd54xx);
return;
}
}
/* Do mem sys src writes here if the blitter is neither paused, nor is there a second aperture. */
if (gd54xx->countminusone && !gd54xx->blt.ms_is_dest && !gd54xx_aperture2_enabled(gd54xx) && !(gd54xx->blt.status & CIRRUS_BLT_PAUSED)) {
gd54xx_writeb_linear(old_addr, val, gd54xx);
gd54xx_writeb_linear(old_addr + 1, val >> 8, gd54xx);
gd54xx_writeb_linear(old_addr + 2, val >> 16, gd54xx);
gd54xx_writeb_linear(old_addr + 3, val >> 24, gd54xx);
return;
}
if (svga->writemode < 4) {
switch (ap) {
default:
case 0:
svga_writel_linear(addr, val, svga);
return;
case 1:
svga_writeb_linear(addr + 1, val & 0xff, svga);
svga_writeb_linear(addr, val >> 8, svga);
svga_writeb_linear(addr + 3, val >> 16, svga);
svga_writeb_linear(addr + 2, val >> 24, svga);
return;
case 2:
svga_writeb_linear(addr + 3, val & 0xff, svga);
svga_writeb_linear(addr + 2, val >> 8, svga);
svga_writeb_linear(addr + 1, val >> 16, svga);
svga_writeb_linear(addr, val >> 24, svga);
return;
case 3:
return;
}
} else {
switch (ap) {
default:
case 0:
svga_write_linear(addr, val & 0xff, svga);
svga_write_linear(addr + 1, val >> 8, svga);
svga_write_linear(addr + 2, val >> 16, svga);
svga_write_linear(addr + 3, val >> 24, svga);
return;
case 1:
svga_write_linear(addr + 1, val & 0xff, svga);
svga_write_linear(addr, val >> 8, svga);
svga_write_linear(addr + 3, val >> 16, svga);
svga_write_linear(addr + 2, val >> 24, svga);
return;
case 2:
svga_write_linear(addr + 3, val & 0xff, svga);
svga_write_linear(addr + 2, val >> 8, svga);
svga_write_linear(addr + 1, val >> 16, svga);
svga_write_linear(addr, val >> 24, svga);
return;
case 3:
return;
}
}
}
static uint8_t
gd54xx_read(uint32_t addr, void *priv)
{
gd54xx_t *gd54xx = (gd54xx_t *) priv;
svga_t *svga = &gd54xx->svga;
if (gd54xx->countminusone && gd54xx->blt.ms_is_dest && !(gd54xx->blt.status & CIRRUS_BLT_PAUSED))
return gd54xx_mem_sys_dest_read(gd54xx, 0);
addr &= svga->banked_mask;
addr = (addr & 0x7fff) + svga->extra_banks[(addr >> 15) & 1];
return svga_read_linear(addr, svga);
}
static uint16_t
gd54xx_readw(uint32_t addr, void *priv)
{
gd54xx_t *gd54xx = (gd54xx_t *) priv;
svga_t *svga = &gd54xx->svga;
uint16_t ret;
if (gd54xx->countminusone && gd54xx->blt.ms_is_dest && !(gd54xx->blt.status & CIRRUS_BLT_PAUSED)) {
ret = gd54xx_read(addr, priv);
ret |= gd54xx_read(addr + 1, priv) << 8;
return ret;
}
addr &= svga->banked_mask;
addr = (addr & 0x7fff) + svga->extra_banks[(addr >> 15) & 1];
return svga_readw_linear(addr, svga);
}
static uint32_t
gd54xx_readl(uint32_t addr, void *priv)
{
gd54xx_t *gd54xx = (gd54xx_t *) priv;
svga_t *svga = &gd54xx->svga;
uint32_t ret;
if (gd54xx->countminusone && gd54xx->blt.ms_is_dest && !(gd54xx->blt.status & CIRRUS_BLT_PAUSED)) {
ret = gd54xx_read(addr, priv);
ret |= gd54xx_read(addr + 1, priv) << 8;
ret |= gd54xx_read(addr + 2, priv) << 16;
ret |= gd54xx_read(addr + 3, priv) << 24;
return ret;
}
addr &= svga->banked_mask;
addr = (addr & 0x7fff) + svga->extra_banks[(addr >> 15) & 1];
return svga_readl_linear(addr, svga);
}
static int
gd543x_do_mmio(svga_t *svga, uint32_t addr)
{
if (svga->seqregs[0x17] & CIRRUS_MMIO_USE_PCIADDR)
return 1;
else
return ((addr & ~0xff) == 0xb8000);
}
static void
gd543x_mmio_write(uint32_t addr, uint8_t val, void *priv)
{
gd54xx_t *gd54xx = (gd54xx_t *) priv;
svga_t *svga = &gd54xx->svga;
uint8_t old;
if (gd543x_do_mmio(svga, addr)) {
switch (addr & 0xff) {
case 0x00:
if (gd54xx_is_5434(svga))
gd54xx->blt.bg_col = (gd54xx->blt.bg_col & 0xffffff00) | val;
else
gd54xx->blt.bg_col = (gd54xx->blt.bg_col & 0xff00) | val;
break;
case 0x01:
if (gd54xx_is_5434(svga))
gd54xx->blt.bg_col = (gd54xx->blt.bg_col & 0xffff00ff) | (val << 8);
else
gd54xx->blt.bg_col = (gd54xx->blt.bg_col & 0x00ff) | (val << 8);
break;
case 0x02:
if (gd54xx_is_5434(svga))
gd54xx->blt.bg_col = (gd54xx->blt.bg_col & 0xff00ffff) | (val << 16);
break;
case 0x03:
if (gd54xx_is_5434(svga))
gd54xx->blt.bg_col = (gd54xx->blt.bg_col & 0x00ffffff) | (val << 24);
break;
case 0x04:
if (gd54xx_is_5434(svga))
gd54xx->blt.fg_col = (gd54xx->blt.fg_col & 0xffffff00) | val;
else
gd54xx->blt.fg_col = (gd54xx->blt.fg_col & 0xff00) | val;
break;
case 0x05:
if (gd54xx_is_5434(svga))
gd54xx->blt.fg_col = (gd54xx->blt.fg_col & 0xffff00ff) | (val << 8);
else
gd54xx->blt.fg_col = (gd54xx->blt.fg_col & 0x00ff) | (val << 8);
break;
case 0x06:
if (gd54xx_is_5434(svga))
gd54xx->blt.fg_col = (gd54xx->blt.fg_col & 0xff00ffff) | (val << 16);
break;
case 0x07:
if (gd54xx_is_5434(svga))
gd54xx->blt.fg_col = (gd54xx->blt.fg_col & 0x00ffffff) | (val << 24);
break;
case 0x08:
gd54xx->blt.width = (gd54xx->blt.width & 0xff00) | val;
break;
case 0x09:
gd54xx->blt.width = (gd54xx->blt.width & 0x00ff) | (val << 8);
if (gd54xx_is_5434(svga))
gd54xx->blt.width &= 0x1fff;
else
gd54xx->blt.width &= 0x07ff;
break;
case 0x0a:
gd54xx->blt.height = (gd54xx->blt.height & 0xff00) | val;
break;
case 0x0b:
gd54xx->blt.height = (gd54xx->blt.height & 0x00ff) | (val << 8);
if (svga->crtc[0x27] >= CIRRUS_ID_CLGD5436)
gd54xx->blt.height &= 0x07ff;
else
gd54xx->blt.height &= 0x03ff;
break;
case 0x0c:
gd54xx->blt.dst_pitch = (gd54xx->blt.dst_pitch & 0xff00) | val;
break;
case 0x0d:
gd54xx->blt.dst_pitch = (gd54xx->blt.dst_pitch & 0x00ff) | (val << 8);
gd54xx->blt.dst_pitch &= 0x1fff;
break;
case 0x0e:
gd54xx->blt.src_pitch = (gd54xx->blt.src_pitch & 0xff00) | val;
break;
case 0x0f:
gd54xx->blt.src_pitch = (gd54xx->blt.src_pitch & 0x00ff) | (val << 8);
gd54xx->blt.src_pitch &= 0x1fff;
break;
case 0x10:
gd54xx->blt.dst_addr = (gd54xx->blt.dst_addr & 0xffff00) | val;
break;
case 0x11:
gd54xx->blt.dst_addr = (gd54xx->blt.dst_addr & 0xff00ff) | (val << 8);
break;
case 0x12:
gd54xx->blt.dst_addr = (gd54xx->blt.dst_addr & 0x00ffff) | (val << 16);
if (gd54xx_is_5434(svga))
gd54xx->blt.dst_addr &= 0x3fffff;
else
gd54xx->blt.dst_addr &= 0x1fffff;
if ((svga->crtc[0x27] >= CIRRUS_ID_CLGD5436) && (gd54xx->blt.status & CIRRUS_BLT_AUTOSTART) && !(gd54xx->blt.status & CIRRUS_BLT_BUSY)) {
gd54xx->blt.status |= CIRRUS_BLT_BUSY;
gd54xx_start_blit(0, 0xffffffff, gd54xx, svga);
}
break;
case 0x14:
gd54xx->blt.src_addr = (gd54xx->blt.src_addr & 0xffff00) | val;
break;
case 0x15:
gd54xx->blt.src_addr = (gd54xx->blt.src_addr & 0xff00ff) | (val << 8);
break;
case 0x16:
gd54xx->blt.src_addr = (gd54xx->blt.src_addr & 0x00ffff) | (val << 16);
if (gd54xx_is_5434(svga))
gd54xx->blt.src_addr &= 0x3fffff;
else
gd54xx->blt.src_addr &= 0x1fffff;
break;
case 0x17:
gd54xx->blt.mask = val;
break;
case 0x18:
gd54xx->blt.mode = val;
gd543x_recalc_mapping(gd54xx);
break;
case 0x1a:
gd54xx->blt.rop = val;
break;
case 0x1b:
if (svga->crtc[0x27] >= CIRRUS_ID_CLGD5436)
gd54xx->blt.modeext = val;
break;
case 0x1c:
gd54xx->blt.trans_col = (gd54xx->blt.trans_col & 0xff00) | val;
break;
case 0x1d:
gd54xx->blt.trans_col = (gd54xx->blt.trans_col & 0x00ff) | (val << 8);
break;
case 0x20:
gd54xx->blt.trans_mask = (gd54xx->blt.trans_mask & 0xff00) | val;
break;
case 0x21:
gd54xx->blt.trans_mask = (gd54xx->blt.trans_mask & 0x00ff) | (val << 8);
break;
case 0x40:
old = gd54xx->blt.status;
gd54xx->blt.status = val;
gd543x_recalc_mapping(gd54xx);
if (!(old & CIRRUS_BLT_RESET) && (gd54xx->blt.status & CIRRUS_BLT_RESET))
gd54xx_reset_blit(gd54xx);
else if (!(old & CIRRUS_BLT_START) && (gd54xx->blt.status & CIRRUS_BLT_START)) {
gd54xx->blt.status |= CIRRUS_BLT_BUSY;
gd54xx_start_blit(0, 0xffffffff, gd54xx, svga);
}
break;
default:
break;
}
} else if (gd54xx->mmio_vram_overlap)
gd54xx_write(addr, val, gd54xx);
}
static void
gd543x_mmio_writeb(uint32_t addr, uint8_t val, void *priv)
{
gd54xx_t *gd54xx = (gd54xx_t *) priv;
svga_t *svga = &gd54xx->svga;
if (!gd543x_do_mmio(svga, addr) && !gd54xx->blt.ms_is_dest && gd54xx->countminusone && !(gd54xx->blt.status & CIRRUS_BLT_PAUSED)) {
gd54xx_mem_sys_src_write(gd54xx, val, 0);
return;
}
gd543x_mmio_write(addr, val, priv);
}
static void
gd543x_mmio_writew(uint32_t addr, uint16_t val, void *priv)
{
gd54xx_t *gd54xx = (gd54xx_t *) priv;
svga_t *svga = &gd54xx->svga;
if (gd543x_do_mmio(svga, addr)) {
gd543x_mmio_write(addr, val & 0xff, gd54xx);
gd543x_mmio_write(addr + 1, val >> 8, gd54xx);
} else if (gd54xx->mmio_vram_overlap) {
if (gd54xx->countminusone && !gd54xx->blt.ms_is_dest && !(gd54xx->blt.status & CIRRUS_BLT_PAUSED)) {
gd543x_mmio_write(addr, val & 0xff, gd54xx);
gd543x_mmio_write(addr + 1, val >> 8, gd54xx);
} else {
gd54xx_write(addr, val, gd54xx);
gd54xx_write(addr + 1, val >> 8, gd54xx);
}
}
}
static void
gd543x_mmio_writel(uint32_t addr, uint32_t val, void *priv)
{
gd54xx_t *gd54xx = (gd54xx_t *) priv;
svga_t *svga = &gd54xx->svga;
if (gd543x_do_mmio(svga, addr)) {
gd543x_mmio_write(addr, val & 0xff, gd54xx);
gd543x_mmio_write(addr + 1, val >> 8, gd54xx);
gd543x_mmio_write(addr + 2, val >> 16, gd54xx);
gd543x_mmio_write(addr + 3, val >> 24, gd54xx);
} else if (gd54xx->mmio_vram_overlap) {
if (gd54xx->countminusone && !gd54xx->blt.ms_is_dest && !(gd54xx->blt.status & CIRRUS_BLT_PAUSED)) {
gd543x_mmio_write(addr, val & 0xff, gd54xx);
gd543x_mmio_write(addr + 1, val >> 8, gd54xx);
gd543x_mmio_write(addr + 2, val >> 16, gd54xx);
gd543x_mmio_write(addr + 3, val >> 24, gd54xx);
} else {
gd54xx_write(addr, val, gd54xx);
gd54xx_write(addr + 1, val >> 8, gd54xx);
gd54xx_write(addr + 2, val >> 16, gd54xx);
gd54xx_write(addr + 3, val >> 24, gd54xx);
}
}
}
static uint8_t
gd543x_mmio_read(uint32_t addr, void *priv)
{
gd54xx_t *gd54xx = (gd54xx_t *) priv;
svga_t *svga = &gd54xx->svga;
uint8_t ret = 0xff;
if (gd543x_do_mmio(svga, addr)) {
switch (addr & 0xff) {
case 0x00:
ret = gd54xx->blt.bg_col & 0xff;
break;
case 0x01:
ret = (gd54xx->blt.bg_col >> 8) & 0xff;
break;
case 0x02:
if (gd54xx_is_5434(svga))
ret = (gd54xx->blt.bg_col >> 16) & 0xff;
break;
case 0x03:
if (gd54xx_is_5434(svga))
ret = (gd54xx->blt.bg_col >> 24) & 0xff;
break;
case 0x04:
ret = gd54xx->blt.fg_col & 0xff;
break;
case 0x05:
ret = (gd54xx->blt.fg_col >> 8) & 0xff;
break;
case 0x06:
if (gd54xx_is_5434(svga))
ret = (gd54xx->blt.fg_col >> 16) & 0xff;
break;
case 0x07:
if (gd54xx_is_5434(svga))
ret = (gd54xx->blt.fg_col >> 24) & 0xff;
break;
case 0x08:
ret = gd54xx->blt.width & 0xff;
break;
case 0x09:
if (gd54xx_is_5434(svga))
ret = (gd54xx->blt.width >> 8) & 0x1f;
else
ret = (gd54xx->blt.width >> 8) & 0x07;
break;
case 0x0a:
ret = gd54xx->blt.height & 0xff;
break;
case 0x0b:
if (svga->crtc[0x27] >= CIRRUS_ID_CLGD5436)
ret = (gd54xx->blt.height >> 8) & 0x07;
else
ret = (gd54xx->blt.height >> 8) & 0x03;
break;
case 0x0c:
ret = gd54xx->blt.dst_pitch & 0xff;
break;
case 0x0d:
ret = (gd54xx->blt.dst_pitch >> 8) & 0x1f;
break;
case 0x0e:
ret = gd54xx->blt.src_pitch & 0xff;
break;
case 0x0f:
ret = (gd54xx->blt.src_pitch >> 8) & 0x1f;
break;
case 0x10:
ret = gd54xx->blt.dst_addr & 0xff;
break;
case 0x11:
ret = (gd54xx->blt.dst_addr >> 8) & 0xff;
break;
case 0x12:
if (gd54xx_is_5434(svga))
ret = (gd54xx->blt.dst_addr >> 16) & 0x3f;
else
ret = (gd54xx->blt.dst_addr >> 16) & 0x1f;
break;
case 0x14:
ret = gd54xx->blt.src_addr & 0xff;
break;
case 0x15:
ret = (gd54xx->blt.src_addr >> 8) & 0xff;
break;
case 0x16:
if (gd54xx_is_5434(svga))
ret = (gd54xx->blt.src_addr >> 16) & 0x3f;
else
ret = (gd54xx->blt.src_addr >> 16) & 0x1f;
break;
case 0x17:
ret = gd54xx->blt.mask;
break;
case 0x18:
ret = gd54xx->blt.mode;
break;
case 0x1a:
ret = gd54xx->blt.rop;
break;
case 0x1b:
if (svga->crtc[0x27] >= CIRRUS_ID_CLGD5436)
ret = gd54xx->blt.modeext;
break;
case 0x1c:
ret = gd54xx->blt.trans_col & 0xff;
break;
case 0x1d:
ret = (gd54xx->blt.trans_col >> 8) & 0xff;
break;
case 0x20:
ret = gd54xx->blt.trans_mask & 0xff;
break;
case 0x21:
ret = (gd54xx->blt.trans_mask >> 8) & 0xff;
break;
case 0x40:
ret = gd54xx->blt.status;
break;
default:
break;
}
} else if (gd54xx->mmio_vram_overlap)
ret = gd54xx_read(addr, gd54xx);
else if (gd54xx->countminusone && gd54xx->blt.ms_is_dest && !(gd54xx->blt.status & CIRRUS_BLT_PAUSED)) {
ret = gd54xx_mem_sys_dest_read(gd54xx, 0);
}
return ret;
}
static uint16_t
gd543x_mmio_readw(uint32_t addr, void *priv)
{
gd54xx_t *gd54xx = (gd54xx_t *) priv;
svga_t *svga = &gd54xx->svga;
uint16_t ret = 0xffff;
if (gd543x_do_mmio(svga, addr))
ret = gd543x_mmio_read(addr, gd54xx) | (gd543x_mmio_read(addr + 1, gd54xx) << 8);
else if (gd54xx->mmio_vram_overlap)
ret = gd54xx_read(addr, gd54xx) | (gd54xx_read(addr + 1, gd54xx) << 8);
else if (gd54xx->countminusone && gd54xx->blt.ms_is_dest && !(gd54xx->blt.status & CIRRUS_BLT_PAUSED)) {
ret = gd543x_mmio_read(addr, priv);
ret |= gd543x_mmio_read(addr + 1, priv) << 8;
return ret;
}
return ret;
}
static uint32_t
gd543x_mmio_readl(uint32_t addr, void *priv)
{
gd54xx_t *gd54xx = (gd54xx_t *) priv;
svga_t *svga = &gd54xx->svga;
uint32_t ret = 0xffffffff;
if (gd543x_do_mmio(svga, addr))
ret = gd543x_mmio_read(addr, gd54xx) | (gd543x_mmio_read(addr + 1, gd54xx) << 8) | (gd543x_mmio_read(addr + 2, gd54xx) << 16) | (gd543x_mmio_read(addr + 3, gd54xx) << 24);
else if (gd54xx->mmio_vram_overlap)
ret = gd54xx_read(addr, gd54xx) | (gd54xx_read(addr + 1, gd54xx) << 8) | (gd54xx_read(addr + 2, gd54xx) << 16) | (gd54xx_read(addr + 3, gd54xx) << 24);
else if (gd54xx->countminusone && gd54xx->blt.ms_is_dest && !(gd54xx->blt.status & CIRRUS_BLT_PAUSED)) {
ret = gd543x_mmio_read(addr, priv);
ret |= gd543x_mmio_read(addr + 1, priv) << 8;
ret |= gd543x_mmio_read(addr + 2, priv) << 16;
ret |= gd543x_mmio_read(addr + 3, priv) << 24;
return ret;
}
return ret;
}
static void
gd5480_vgablt_write(uint32_t addr, uint8_t val, void *priv)
{
addr &= 0x00000fff;
if ((addr >= 0x00000100) && (addr < 0x00000200))
gd543x_mmio_writeb((addr & 0x000000ff) | 0x000b8000, val, priv);
else if (addr < 0x00000100)
gd54xx_out(0x03c0 + addr, val, priv);
}
static void
gd5480_vgablt_writew(uint32_t addr, uint16_t val, void *priv)
{
addr &= 0x00000fff;
if ((addr >= 0x00000100) && (addr < 0x00000200))
gd543x_mmio_writew((addr & 0x000000ff) | 0x000b8000, val, priv);
else if (addr < 0x00000100) {
gd5480_vgablt_write(addr, val & 0xff, priv);
gd5480_vgablt_write(addr + 1, val >> 8, priv);
}
}
static void
gd5480_vgablt_writel(uint32_t addr, uint32_t val, void *priv)
{
addr &= 0x00000fff;
if ((addr >= 0x00000100) && (addr < 0x00000200))
gd543x_mmio_writel((addr & 0x000000ff) | 0x000b8000, val, priv);
else if (addr < 0x00000100) {
gd5480_vgablt_writew(addr, val & 0xffff, priv);
gd5480_vgablt_writew(addr + 2, val >> 16, priv);
}
}
static uint8_t
gd5480_vgablt_read(uint32_t addr, void *priv)
{
uint8_t ret = 0xff;
addr &= 0x00000fff;
if ((addr >= 0x00000100) && (addr < 0x00000200))
ret = gd543x_mmio_read((addr & 0x000000ff) | 0x000b8000, priv);
else if (addr < 0x00000100)
ret = gd54xx_in(0x03c0 + addr, priv);
return ret;
}
static uint16_t
gd5480_vgablt_readw(uint32_t addr, void *priv)
{
uint16_t ret = 0xffff;
addr &= 0x00000fff;
if ((addr >= 0x00000100) && (addr < 0x00000200))
ret = gd543x_mmio_readw((addr & 0x000000ff) | 0x000b8000, priv);
else if (addr < 0x00000100) {
ret = gd5480_vgablt_read(addr, priv);
ret |= (gd5480_vgablt_read(addr + 1, priv) << 8);
}
return ret;
}
static uint32_t
gd5480_vgablt_readl(uint32_t addr, void *priv)
{
uint32_t ret = 0xffffffff;
addr &= 0x00000fff;
if ((addr >= 0x00000100) && (addr < 0x00000200))
ret = gd543x_mmio_readl((addr & 0x000000ff) | 0x000b8000, priv);
else if (addr < 0x00000100) {
ret = gd5480_vgablt_readw(addr, priv);
ret |= (gd5480_vgablt_readw(addr + 2, priv) << 16);
}
return ret;
}
static uint8_t
gd54xx_color_expand(gd54xx_t *gd54xx, int mask, int shift)
{
uint8_t ret;
if (gd54xx->blt.mode & CIRRUS_BLTMODE_TRANSPARENTCOMP)
ret = gd54xx->blt.fg_col >> (shift << 3);
else
ret = mask ? (gd54xx->blt.fg_col >> (shift << 3)) : (gd54xx->blt.bg_col >> (shift << 3));
return ret;
}
static int
gd54xx_get_pixel_width(gd54xx_t *gd54xx)
{
int ret = 1;
switch (gd54xx->blt.mode & CIRRUS_BLTMODE_PIXELWIDTHMASK) {
case CIRRUS_BLTMODE_PIXELWIDTH8:
ret = 1;
break;
case CIRRUS_BLTMODE_PIXELWIDTH16:
ret = 2;
break;
case CIRRUS_BLTMODE_PIXELWIDTH24:
ret = 3;
break;
case CIRRUS_BLTMODE_PIXELWIDTH32:
ret = 4;
break;
default:
break;
}
return ret;
}
static void
gd54xx_blit(gd54xx_t *gd54xx, uint8_t mask, uint8_t *dst, uint8_t target, int skip)
{
int is_transp;
int is_bgonly;
/* skip indicates whether or not it is a pixel to be skipped (used for left skip);
mask indicates transparency or not (only when transparent comparison is enabled):
color expand: direct pattern bit; 1 = write, 0 = do not write
(the other way around in inverse mode);
normal 8-bpp or 16-bpp: does not match transparent color = write,
matches transparent color = do not write */
/* Make sure to always ignore transparency and skip in case of mem sys dest. */
is_transp = (gd54xx->blt.mode & CIRRUS_BLTMODE_MEMSYSDEST) ? 0 : (gd54xx->blt.mode & CIRRUS_BLTMODE_TRANSPARENTCOMP);
is_bgonly = (gd54xx->blt.mode & CIRRUS_BLTMODE_MEMSYSDEST) ? 0 : (gd54xx->blt.modeext & CIRRUS_BLTMODEEXT_BACKGROUNDONLY);
skip = (gd54xx->blt.mode & CIRRUS_BLTMODE_MEMSYSDEST) ? 0 : skip;
if (is_transp) {
if ((gd54xx->blt.mode & CIRRUS_BLTMODE_COLOREXPAND) && (gd54xx->blt.modeext & CIRRUS_BLTMODEEXT_COLOREXPINV))
mask = !mask;
/* If mask is 1 and it is not a pixel to be skipped, write it. */
if (mask && !skip)
*dst = target;
} else if ((gd54xx->blt.mode & CIRRUS_BLTMODE_COLOREXPAND) && is_bgonly) {
/* If mask is 1 or it is not a pixel to be skipped, write it.
(Skip only background pixels.) */
if (mask || !skip)
*dst = target;
} else {
/* If if it is not a pixel to be skipped, write it. */
if (!skip)
*dst = target;
}
}
static int
gd54xx_transparent_comp(gd54xx_t *gd54xx, uint32_t xx, uint8_t src)
{
svga_t *svga = &gd54xx->svga;
int ret = 1;
if ((gd54xx->blt.pixel_width <= 2) && gd54xx_has_transp(svga, 0)) {
ret = src ^ ((uint8_t *) &(gd54xx->blt.trans_col))[xx];
if (gd54xx_has_transp(svga, 1))
ret &= ~(((uint8_t *) &(gd54xx->blt.trans_mask))[xx]);
ret = !ret;
}
return ret;
}
static void
gd54xx_pattern_copy(gd54xx_t *gd54xx)
{
uint8_t target;
uint8_t src;
uint8_t *dst;
int pattern_y;
int pattern_pitch;
uint32_t bitmask = 0;
uint32_t pixel;
uint32_t srca;
uint32_t srca2;
uint32_t dsta;
svga_t *svga = &gd54xx->svga;
pattern_pitch = gd54xx->blt.pixel_width << 3;
if (gd54xx->blt.pixel_width == 3)
pattern_pitch = 32;
if (gd54xx->blt.mode & CIRRUS_BLTMODE_COLOREXPAND)
pattern_pitch = 1;
dsta = gd54xx->blt.dst_addr & gd54xx->vram_mask;
/* The vertical offset is in the three low-order bits of the Source Address register. */
pattern_y = gd54xx->blt.src_addr & 0x07;
/* Mode Pattern bytes Pattern line bytes
---------------------------------------------------
Color Expansion 8 1
8-bpp 64 8
16-bpp 128 16
24-bpp 256 32
32-bpp 256 32
*/
/* The boundary has to be equal to the size of the pattern. */
srca = (gd54xx->blt.src_addr & ~0x07) & gd54xx->vram_mask;
for (uint16_t y = 0; y <= gd54xx->blt.height; y++) {
/* Go to the correct pattern line. */
srca2 = srca + (pattern_y * pattern_pitch);
pixel = 0;
for (uint16_t x = 0; x <= gd54xx->blt.width; x += gd54xx->blt.pixel_width) {
if (gd54xx->blt.mode & CIRRUS_BLTMODE_COLOREXPAND) {
if (gd54xx->blt.modeext & CIRRUS_BLTMODEEXT_SOLIDFILL)
bitmask = 1;
else
bitmask = svga->vram[srca2 & gd54xx->vram_mask] & (0x80 >> pixel);
}
for (int xx = 0; xx < gd54xx->blt.pixel_width; xx++) {
if (gd54xx->blt.mode & CIRRUS_BLTMODE_COLOREXPAND)
src = gd54xx_color_expand(gd54xx, bitmask, xx);
else {
src = svga->vram[(srca2 + (x % (gd54xx->blt.pixel_width << 3)) + xx) & gd54xx->vram_mask];
bitmask = gd54xx_transparent_comp(gd54xx, xx, src);
}
dst = &(svga->vram[(dsta + x + xx) & gd54xx->vram_mask]);
target = *dst;
gd54xx_rop(gd54xx, &target, &target, &src);
if (gd54xx->blt.pixel_width == 3)
gd54xx_blit(gd54xx, bitmask, dst, target, ((x + xx) < gd54xx->blt.pattern_x));
else
gd54xx_blit(gd54xx, bitmask, dst, target, (x < gd54xx->blt.pattern_x));
}
pixel = (pixel + 1) & 7;
svga->changedvram[((dsta + x) & gd54xx->vram_mask) >> 12] = changeframecount;
}
pattern_y = (pattern_y + 1) & 7;
dsta += gd54xx->blt.dst_pitch;
}
}
static void
gd54xx_reset_blit(gd54xx_t *gd54xx)
{
gd54xx->countminusone = 0;
gd54xx->blt.status &= ~(CIRRUS_BLT_START | CIRRUS_BLT_BUSY | CIRRUS_BLT_FIFOUSED);
}
/* Each blit is either 1 byte -> 1 byte (non-color expand blit)
or 1 byte -> 8/16/24/32 bytes (color expand blit). */
static void
gd54xx_mem_sys_src(gd54xx_t *gd54xx, uint32_t cpu_dat, uint32_t count)
{
uint8_t *dst;
uint8_t exp;
uint8_t target;
int mask_shift;
uint32_t byte_pos;
uint32_t bitmask = 0;
svga_t *svga = &gd54xx->svga;
gd54xx->blt.ms_is_dest = 0;
if (gd54xx->blt.mode & (CIRRUS_BLTMODE_MEMSYSDEST | CIRRUS_BLTMODE_PATTERNCOPY))
gd54xx_reset_blit(gd54xx);
else if (count == 0xffffffff) {
gd54xx->blt.dst_addr_backup = gd54xx->blt.dst_addr;
gd54xx->blt.src_addr_backup = gd54xx->blt.src_addr;
gd54xx->blt.x_count = gd54xx->blt.xx_count = 0;
gd54xx->blt.y_count = 0;
gd54xx->countminusone = 1;
gd54xx->blt.sys_src32 = 0x00000000;
gd54xx->blt.sys_cnt = 0;
return;
} else if (gd54xx->countminusone) {
if (!(gd54xx->blt.mode & CIRRUS_BLTMODE_COLOREXPAND) || (gd54xx->blt.modeext & CIRRUS_BLTMODEEXT_DWORDGRANULARITY)) {
if (!gd54xx->blt.xx_count && !gd54xx->blt.x_count)
byte_pos = (((gd54xx->blt.mask >> 5) & 3) << 3);
else
byte_pos = 0;
mask_shift = 31 - byte_pos;
if (!(gd54xx->blt.mode & CIRRUS_BLTMODE_COLOREXPAND))
cpu_dat >>= byte_pos;
} else
mask_shift = 7;
while (mask_shift > -1) {
if (gd54xx->blt.mode & CIRRUS_BLTMODE_COLOREXPAND) {
bitmask = (cpu_dat >> mask_shift) & 0x01;
exp = gd54xx_color_expand(gd54xx, bitmask, gd54xx->blt.xx_count);
} else {
exp = cpu_dat & 0xff;
bitmask = gd54xx_transparent_comp(gd54xx, gd54xx->blt.xx_count, exp);
}
dst = &(svga->vram[gd54xx->blt.dst_addr_backup & gd54xx->vram_mask]);
target = *dst;
gd54xx_rop(gd54xx, &target, &target, &exp);
if ((gd54xx->blt.pixel_width == 3) && (gd54xx->blt.mode & CIRRUS_BLTMODE_COLOREXPAND))
gd54xx_blit(gd54xx, bitmask, dst, target, ((gd54xx->blt.x_count + gd54xx->blt.xx_count) < gd54xx->blt.pattern_x));
else
gd54xx_blit(gd54xx, bitmask, dst, target, (gd54xx->blt.x_count < gd54xx->blt.pattern_x));
gd54xx->blt.dst_addr_backup += gd54xx->blt.dir;
if (gd54xx->blt.mode & CIRRUS_BLTMODE_COLOREXPAND)
gd54xx->blt.xx_count = (gd54xx->blt.xx_count + 1) % gd54xx->blt.pixel_width;
svga->changedvram[(gd54xx->blt.dst_addr_backup & gd54xx->vram_mask) >> 12] = changeframecount;
if (!gd54xx->blt.xx_count) {
/* 1 mask bit = 1 blitted pixel */
if (gd54xx->blt.mode & CIRRUS_BLTMODE_COLOREXPAND)
mask_shift--;
else {
cpu_dat >>= 8;
mask_shift -= 8;
}
if (gd54xx->blt.mode & CIRRUS_BLTMODE_COLOREXPAND)
gd54xx->blt.x_count = (gd54xx->blt.x_count + gd54xx->blt.pixel_width) % (gd54xx->blt.width + 1);
else
gd54xx->blt.x_count = (gd54xx->blt.x_count + 1) % (gd54xx->blt.width + 1);
if (!gd54xx->blt.x_count) {
gd54xx->blt.y_count = (gd54xx->blt.y_count + 1) % (gd54xx->blt.height + 1);
if (gd54xx->blt.y_count)
gd54xx->blt.dst_addr_backup = gd54xx->blt.dst_addr + (gd54xx->blt.dst_pitch * gd54xx->blt.y_count * gd54xx->blt.dir);
else {
/* If we're here, the blit is over, reset. */
gd54xx_reset_blit(gd54xx);
}
/* Stop blitting and request new data if end of line reached. */
return;
}
}
}
}
}
static void
gd54xx_normal_blit(uint32_t count, gd54xx_t *gd54xx, svga_t *svga)
{
uint8_t src = 0;
uint8_t dst;
uint16_t width = gd54xx->blt.width;
int x_max = 0;
int shift = 0;
int mask = 0;
uint32_t src_addr = gd54xx->blt.src_addr;
uint32_t dst_addr = gd54xx->blt.dst_addr;
x_max = gd54xx->blt.pixel_width << 3;
gd54xx->blt.dst_addr_backup = gd54xx->blt.dst_addr;
gd54xx->blt.src_addr_backup = gd54xx->blt.src_addr;
gd54xx->blt.height_internal = gd54xx->blt.height;
gd54xx->blt.x_count = 0;
gd54xx->blt.y_count = 0;
while (count) {
src = 0;
mask = 0;
if (gd54xx->blt.mode & CIRRUS_BLTMODE_COLOREXPAND) {
mask = svga->vram[src_addr & gd54xx->vram_mask] & (0x80 >> (gd54xx->blt.x_count / gd54xx->blt.pixel_width));
shift = (gd54xx->blt.x_count % gd54xx->blt.pixel_width);
src = gd54xx_color_expand(gd54xx, mask, shift);
} else {
src = svga->vram[src_addr & gd54xx->vram_mask];
src_addr += gd54xx->blt.dir;
mask = 1;
}
count--;
dst = svga->vram[dst_addr & gd54xx->vram_mask];
svga->changedvram[(dst_addr & gd54xx->vram_mask) >> 12] = changeframecount;
gd54xx_rop(gd54xx, &dst, &dst, (const uint8_t *) &src);
if ((gd54xx->blt.mode & CIRRUS_BLTMODE_COLOREXPAND) && (gd54xx->blt.modeext & CIRRUS_BLTMODEEXT_COLOREXPINV))
mask = !mask;
/* This handles 8bpp and 16bpp non-color-expanding transparent comparisons. */
if ((gd54xx->blt.mode & CIRRUS_BLTMODE_TRANSPARENTCOMP) && !(gd54xx->blt.mode & CIRRUS_BLTMODE_COLOREXPAND) && ((gd54xx->blt.mode & CIRRUS_BLTMODE_PIXELWIDTHMASK) <= CIRRUS_BLTMODE_PIXELWIDTH16) && (src != ((gd54xx->blt.trans_mask >> (shift << 3)) & 0xff)))
mask = 0;
if (((gd54xx->blt.width - width) >= gd54xx->blt.pattern_x) && !((gd54xx->blt.mode & CIRRUS_BLTMODE_TRANSPARENTCOMP) && !mask)) {
svga->vram[dst_addr & gd54xx->vram_mask] = dst;
}
dst_addr += gd54xx->blt.dir;
gd54xx->blt.x_count++;
if (gd54xx->blt.x_count == x_max) {
gd54xx->blt.x_count = 0;
if (gd54xx->blt.mode & CIRRUS_BLTMODE_COLOREXPAND)
src_addr++;
}
width--;
if (width == 0xffff) {
width = gd54xx->blt.width;
dst_addr = gd54xx->blt.dst_addr_backup = gd54xx->blt.dst_addr_backup + (gd54xx->blt.dst_pitch * gd54xx->blt.dir);
gd54xx->blt.y_count = (gd54xx->blt.y_count + gd54xx->blt.dir) & 7;
if (gd54xx->blt.mode & CIRRUS_BLTMODE_COLOREXPAND) {
if (gd54xx->blt.x_count != 0)
src_addr++;
} else
src_addr = gd54xx->blt.src_addr_backup = gd54xx->blt.src_addr_backup + (gd54xx->blt.src_pitch * gd54xx->blt.dir);
dst_addr &= gd54xx->vram_mask;
gd54xx->blt.dst_addr_backup &= gd54xx->vram_mask;
src_addr &= gd54xx->vram_mask;
gd54xx->blt.src_addr_backup &= gd54xx->vram_mask;
gd54xx->blt.x_count = 0;
gd54xx->blt.height_internal--;
if (gd54xx->blt.height_internal == 0xffff) {
gd54xx_reset_blit(gd54xx);
return;
}
}
}
/* Count exhausted, stuff still left to blit. */
gd54xx_reset_blit(gd54xx);
}
static void
gd54xx_mem_sys_dest(uint32_t count, gd54xx_t *gd54xx, svga_t *svga)
{
gd54xx->blt.ms_is_dest = 1;
if (gd54xx->blt.mode & CIRRUS_BLTMODE_PATTERNCOPY) {
fatal("mem sys dest pattern copy not allowed (see 1994 manual)\n");
gd54xx_reset_blit(gd54xx);
} else if (gd54xx->blt.mode & CIRRUS_BLTMODE_COLOREXPAND) {
fatal("mem sys dest color expand not allowed (see 1994 manual)\n");
gd54xx_reset_blit(gd54xx);
} else {
if (count == 0xffffffff) {
gd54xx->blt.dst_addr_backup = gd54xx->blt.dst_addr;
gd54xx->blt.msd_buf_cnt = 0;
gd54xx->blt.src_addr_backup = gd54xx->blt.src_addr;
gd54xx->blt.x_count = gd54xx->blt.xx_count = 0;
gd54xx->blt.y_count = 0;
gd54xx->countminusone = 1;
count = 32;
}
gd54xx->blt.msd_buf_pos = 0;
while (gd54xx->blt.msd_buf_pos < 32) {
gd54xx->blt.msd_buf[gd54xx->blt.msd_buf_pos & 0x1f] = svga->vram[gd54xx->blt.src_addr_backup & gd54xx->vram_mask];
gd54xx->blt.src_addr_backup += gd54xx->blt.dir;
gd54xx->blt.msd_buf_pos++;
gd54xx->blt.x_count = (gd54xx->blt.x_count + 1) % (gd54xx->blt.width + 1);
if (!gd54xx->blt.x_count) {
gd54xx->blt.y_count = (gd54xx->blt.y_count + 1) % (gd54xx->blt.height + 1);
if (gd54xx->blt.y_count)
gd54xx->blt.src_addr_backup = gd54xx->blt.src_addr + (gd54xx->blt.src_pitch * gd54xx->blt.y_count * gd54xx->blt.dir);
else
gd54xx->countminusone = 2; /* Signal end of blit. */
/* End of line reached, stop and notify regardless of how much we already transferred. */
goto request_more_data;
}
}
/* End of while. */
request_more_data:
/* If the byte count we have blitted are not divisible by 4, round them up. */
if (gd54xx->blt.msd_buf_pos & 3)
gd54xx->blt.msd_buf_cnt = (gd54xx->blt.msd_buf_pos & ~3) + 4;
else
gd54xx->blt.msd_buf_cnt = gd54xx->blt.msd_buf_pos;
gd54xx->blt.msd_buf_pos = 0;
return;
}
}
static void
gd54xx_start_blit(uint32_t cpu_dat, uint32_t count, gd54xx_t *gd54xx, svga_t *svga)
{
if ((gd54xx->blt.mode & CIRRUS_BLTMODE_BACKWARDS) && !(gd54xx->blt.mode & (CIRRUS_BLTMODE_PATTERNCOPY | CIRRUS_BLTMODE_COLOREXPAND)) && !(gd54xx->blt.mode & CIRRUS_BLTMODE_TRANSPARENTCOMP))
gd54xx->blt.dir = -1;
else
gd54xx->blt.dir = 1;
gd54xx->blt.pixel_width = gd54xx_get_pixel_width(gd54xx);
if (gd54xx->blt.mode & (CIRRUS_BLTMODE_PATTERNCOPY | CIRRUS_BLTMODE_COLOREXPAND)) {
if (gd54xx->blt.pixel_width == 3)
gd54xx->blt.pattern_x = gd54xx->blt.mask & 0x1f; /* (Mask & 0x1f) bytes. */
else
gd54xx->blt.pattern_x = (gd54xx->blt.mask & 0x07) * gd54xx->blt.pixel_width; /* (Mask & 0x07) pixels. */
} else
gd54xx->blt.pattern_x = 0; /* No skip in normal blit mode. */
if (gd54xx->blt.mode & CIRRUS_BLTMODE_MEMSYSSRC)
gd54xx_mem_sys_src(gd54xx, cpu_dat, count);
else if (gd54xx->blt.mode & CIRRUS_BLTMODE_MEMSYSDEST)
gd54xx_mem_sys_dest(count, gd54xx, svga);
else if (gd54xx->blt.mode & CIRRUS_BLTMODE_PATTERNCOPY) {
gd54xx_pattern_copy(gd54xx);
gd54xx_reset_blit(gd54xx);
} else
gd54xx_normal_blit(count, gd54xx, svga);
}
static uint8_t
cl_pci_read(UNUSED(int func), int addr, void *priv)
{
const gd54xx_t *gd54xx = (gd54xx_t *) priv;
const svga_t *svga = &gd54xx->svga;
uint8_t ret = 0x00;
if ((addr >= 0x30) && (addr <= 0x33) && (!gd54xx->has_bios))
ret = 0x00;
else switch (addr) {
case 0x00:
ret = 0x13; /*Cirrus Logic*/
break;
case 0x01:
ret = 0x10;
break;
case 0x02:
ret = svga->crtc[0x27];
break;
case 0x03:
ret = 0x00;
break;
case PCI_REG_COMMAND:
ret = gd54xx->pci_regs[PCI_REG_COMMAND]; /*Respond to IO and memory accesses*/
break;
case 0x07:
ret = 0x02; /*Fast DEVSEL timing*/
break;
case 0x08:
ret = gd54xx->rev; /*Revision ID*/
break;
case 0x09:
ret = 0x00; /*Programming interface*/
break;
case 0x0a:
ret = 0x00; /*Supports VGA interface*/
break;
case 0x0b:
ret = 0x03;
break;
case 0x10:
ret = 0x08; /*Linear frame buffer address*/
break;
case 0x11:
ret = 0x00;
break;
case 0x12:
ret = 0x00;
break;
case 0x13:
ret = gd54xx->lfb_base >> 24;
if (svga->crtc[0x27] == CIRRUS_ID_CLGD5480)
ret &= 0xfe;
break;
case 0x14:
ret = 0x00; /*PCI VGA/BitBLT Register Base Address*/
break;
case 0x15:
ret = (svga->crtc[0x27] == CIRRUS_ID_CLGD5480) ? ((gd54xx->vgablt_base >> 8) & 0xf0) : 0x00;
break;
case 0x16:
ret = (svga->crtc[0x27] == CIRRUS_ID_CLGD5480) ? ((gd54xx->vgablt_base >> 16) & 0xff) : 0x00;
break;
case 0x17:
ret = (svga->crtc[0x27] == CIRRUS_ID_CLGD5480) ? ((gd54xx->vgablt_base >> 24) & 0xff) : 0x00;
break;
case 0x30:
ret = (gd54xx->pci_regs[0x30] & 0x01); /*BIOS ROM address*/
break;
case 0x31:
ret = 0x00;
break;
case 0x32:
ret = gd54xx->pci_regs[0x32];
break;
case 0x33:
ret = gd54xx->pci_regs[0x33];
break;
case 0x3c:
ret = gd54xx->int_line;
break;
case 0x3d:
ret = PCI_INTA;
break;
default:
break;
}
return ret;
}
static void
cl_pci_write(UNUSED(int func), int addr, uint8_t val, void *priv)
{
gd54xx_t *gd54xx = (gd54xx_t *) priv;
const svga_t *svga = &gd54xx->svga;
uint32_t byte;
if ((addr >= 0x30) && (addr <= 0x33) && (!gd54xx->has_bios))
return;
switch (addr) {
case PCI_REG_COMMAND:
gd54xx->pci_regs[PCI_REG_COMMAND] = val & 0x23;
mem_mapping_disable(&gd54xx->vgablt_mapping);
io_removehandler(0x03c0, 0x0020, gd54xx_in, NULL, NULL, gd54xx_out, NULL, NULL, gd54xx);
if (val & PCI_COMMAND_IO)
io_sethandler(0x03c0, 0x0020, gd54xx_in, NULL, NULL, gd54xx_out, NULL, NULL, gd54xx);
if ((val & PCI_COMMAND_MEM) && (gd54xx->vgablt_base != 0x00000000) && (gd54xx->vgablt_base < 0xfff00000))
mem_mapping_set_addr(&gd54xx->vgablt_mapping, gd54xx->vgablt_base, 0x1000);
if ((gd54xx->pci_regs[PCI_REG_COMMAND] & PCI_COMMAND_MEM) && (gd54xx->pci_regs[0x30] & 0x01)) {
uint32_t addr = (gd54xx->pci_regs[0x32] << 16) | (gd54xx->pci_regs[0x33] << 24);
mem_mapping_set_addr(&gd54xx->bios_rom.mapping, addr, 0x8000);
} else
mem_mapping_disable(&gd54xx->bios_rom.mapping);
gd543x_recalc_mapping(gd54xx);
break;
case 0x13:
/* 5480, like 5446 rev. B, has a 32 MB aperture, with the second set used for
BitBLT transfers. */
if (svga->crtc[0x27] == CIRRUS_ID_CLGD5480)
val &= 0xfe;
gd54xx->lfb_base = val << 24;
gd543x_recalc_mapping(gd54xx);
break;
case 0x15:
case 0x16:
case 0x17:
if (svga->crtc[0x27] != CIRRUS_ID_CLGD5480)
return;
byte = (addr & 3) << 3;
gd54xx->vgablt_base &= ~(0xff << byte);
if (addr == 0x15)
val &= 0xf0;
gd54xx->vgablt_base |= (val << byte);
mem_mapping_disable(&gd54xx->vgablt_mapping);
if ((gd54xx->pci_regs[PCI_REG_COMMAND] & PCI_COMMAND_MEM) && (gd54xx->vgablt_base != 0x00000000) && (gd54xx->vgablt_base < 0xfff00000))
mem_mapping_set_addr(&gd54xx->vgablt_mapping, gd54xx->vgablt_base, 0x1000);
break;
case 0x30:
case 0x32:
case 0x33:
gd54xx->pci_regs[addr] = val;
if ((gd54xx->pci_regs[PCI_REG_COMMAND] & PCI_COMMAND_MEM) && (gd54xx->pci_regs[0x30] & 0x01)) {
uint32_t addr = (gd54xx->pci_regs[0x32] << 16) | (gd54xx->pci_regs[0x33] << 24);
mem_mapping_set_addr(&gd54xx->bios_rom.mapping, addr, 0x8000);
} else
mem_mapping_disable(&gd54xx->bios_rom.mapping);
return;
case 0x3c:
gd54xx->int_line = val;
return;
default:
break;
}
}
static uint8_t
gd5428_mca_read(int port, void *priv)
{
const gd54xx_t *gd54xx = (gd54xx_t *) priv;
return gd54xx->pos_regs[port & 7];
}
static void
gd5428_mca_write(int port, uint8_t val, void *priv)
{
gd54xx_t *gd54xx = (gd54xx_t *) priv;
if (port < 0x102)
return;
gd54xx->pos_regs[port & 7] = val;
mem_mapping_disable(&gd54xx->bios_rom.mapping);
if (gd54xx->pos_regs[2] & 0x01)
mem_mapping_enable(&gd54xx->bios_rom.mapping);
}
static uint8_t
gd5428_mca_feedb(void *priv)
{
const gd54xx_t *gd54xx = (gd54xx_t *) priv;
return gd54xx->pos_regs[2] & 0x01;
}
static void
gd54xx_reset(void *priv)
{
gd54xx_t *gd54xx = (gd54xx_t *) priv;
svga_t *svga = &gd54xx->svga;
memset(svga->crtc, 0x00, sizeof(svga->crtc));
memset(svga->seqregs, 0x00, sizeof(svga->seqregs));
memset(svga->gdcreg, 0x00, sizeof(svga->gdcreg));
svga->crtc[0] = 63;
svga->crtc[6] = 255;
svga->dispontime = 1000ULL << 32;
svga->dispofftime = 1000ULL << 32;
svga->bpp = 8;
io_removehandler(0x03c0, 0x0020, gd54xx_in, NULL, NULL, gd54xx_out, NULL, NULL, gd54xx);
io_sethandler(0x03c0, 0x0020, gd54xx_in, NULL, NULL, gd54xx_out, NULL, NULL, gd54xx);
mem_mapping_disable(&gd54xx->vgablt_mapping);
if (gd54xx->has_bios && (gd54xx->pci || gd54xx->mca))
mem_mapping_disable(&gd54xx->bios_rom.mapping);
memset(gd54xx->pci_regs, 0x00, 256);
mem_mapping_set_p(&svga->mapping, gd54xx);
mem_mapping_disable(&gd54xx->mmio_mapping);
mem_mapping_disable(&gd54xx->linear_mapping);
mem_mapping_disable(&gd54xx->aperture2_mapping);
mem_mapping_disable(&gd54xx->vgablt_mapping);
gd543x_recalc_mapping(gd54xx);
gd54xx_recalc_banking(gd54xx);
svga->hwcursor.yoff = svga->hwcursor.xoff = 0;
if (gd54xx->id >= CIRRUS_ID_CLGD5420) {
gd54xx->vclk_n[0] = 0x4a;
gd54xx->vclk_d[0] = 0x2b;
gd54xx->vclk_n[1] = 0x5b;
gd54xx->vclk_d[1] = 0x2f;
gd54xx->vclk_n[2] = 0x45;
gd54xx->vclk_d[2] = 0x30;
gd54xx->vclk_n[3] = 0x7e;
gd54xx->vclk_d[3] = 0x33;
} else {
gd54xx->vclk_n[0] = 0x66;
gd54xx->vclk_d[0] = 0x3b;
gd54xx->vclk_n[1] = 0x5b;
gd54xx->vclk_d[1] = 0x2f;
gd54xx->vclk_n[2] = 0x45;
gd54xx->vclk_d[2] = 0x2c;
gd54xx->vclk_n[3] = 0x7e;
gd54xx->vclk_d[3] = 0x33;
}
svga->extra_banks[1] = 0x8000;
gd54xx->pci_regs[PCI_REG_COMMAND] = 7;
gd54xx->pci_regs[0x30] = 0x00;
gd54xx->pci_regs[0x32] = 0x0c;
gd54xx->pci_regs[0x33] = 0x00;
svga->crtc[0x27] = gd54xx->id;
svga->seqregs[6] = 0x0f;
if (svga->crtc[0x27] >= CIRRUS_ID_CLGD5429)
gd54xx->unlocked = 1;
else
gd54xx->unlocked = 0;
}
static void *
gd54xx_init(const device_t *info)
{
gd54xx_t *gd54xx = malloc(sizeof(gd54xx_t));
svga_t *svga = &gd54xx->svga;
int id = info->local & 0xff;
int vram;
const char *romfn = NULL;
const char *romfn1 = NULL;
const char *romfn2 = NULL;
memset(gd54xx, 0, sizeof(gd54xx_t));
gd54xx->pci = !!(info->flags & DEVICE_PCI);
gd54xx->vlb = !!(info->flags & DEVICE_VLB);
gd54xx->mca = !!(info->flags & DEVICE_MCA);
gd54xx->bit32 = gd54xx->pci || gd54xx->vlb;
gd54xx->rev = 0;
gd54xx->has_bios = 1;
gd54xx->id = id;
switch (id) {
case CIRRUS_ID_CLGD5401:
romfn = BIOS_GD5401_PATH;
break;
case CIRRUS_ID_CLGD5402:
if (info->local & 0x200)
romfn = BIOS_GD5402_ONBOARD_PATH;
else
romfn = BIOS_GD5402_PATH;
break;
case CIRRUS_ID_CLGD5420:
romfn = BIOS_GD5420_PATH;
break;
case CIRRUS_ID_CLGD5422:
case CIRRUS_ID_CLGD5424:
romfn = BIOS_GD5422_PATH;
break;
case CIRRUS_ID_CLGD5426:
if (info->local & 0x200)
romfn = NULL;
else {
if (info->local & 0x100)
romfn = BIOS_GD5426_DIAMOND_A1_ISA_PATH;
else {
if (gd54xx->vlb)
romfn = BIOS_GD5428_PATH;
else if (gd54xx->mca)
romfn = BIOS_GD5426_MCA_PATH;
else
romfn = BIOS_GD5428_ISA_PATH;
}
}
break;
case CIRRUS_ID_CLGD5428:
if (info->local & 0x100)
if (gd54xx->vlb)
romfn = BIOS_GD5428_DIAMOND_B1_VLB_PATH;
else {
romfn1 = BIOS_GD5428_BOCA_ISA_PATH_1;
romfn2 = BIOS_GD5428_BOCA_ISA_PATH_2;
}
else {
if (gd54xx->vlb)
romfn = BIOS_GD5428_PATH;
else if (gd54xx->mca)
romfn = BIOS_GD5428_MCA_PATH;
else
romfn = BIOS_GD5428_ISA_PATH;
}
break;
case CIRRUS_ID_CLGD5429:
romfn = BIOS_GD5429_PATH;
break;
case CIRRUS_ID_CLGD5432:
case CIRRUS_ID_CLGD5434_4:
if (info->local & 0x200) {
romfn = NULL;
gd54xx->has_bios = 0;
}
break;
case CIRRUS_ID_CLGD5434:
if (info->local & 0x200) {
romfn = NULL;
gd54xx->has_bios = 0;
} else if (gd54xx->vlb) {
romfn = BIOS_GD5430_ORCHID_VLB_PATH;
} else {
if (info->local & 0x100)
romfn = BIOS_GD5434_DIAMOND_A3_ISA_PATH;
else
romfn = BIOS_GD5434_PATH;
}
break;
case CIRRUS_ID_CLGD5436:
if (info->local & 0x200) {
romfn = NULL;
gd54xx->has_bios = 0;
} else
romfn = BIOS_GD5436_PATH;
break;
case CIRRUS_ID_CLGD5430:
if (info->local & 0x400) {
/* CL-GD 5440 */
gd54xx->rev = 0x47;
if (info->local & 0x200) {
romfn = NULL;
gd54xx->has_bios = 0;
} else
romfn = BIOS_GD5440_PATH;
} else {
/* CL-GD 5430 */
if (info->local & 0x200) {
romfn = NULL;
gd54xx->has_bios = 0;
} else if (gd54xx->pci)
romfn = BIOS_GD5430_PATH;
else if ((gd54xx->vlb) && (info->local & 0x100))
romfn = BIOS_GD5430_ORCHID_VLB_PATH;
else
romfn = BIOS_GD5430_DIAMOND_A8_VLB_PATH;
}
break;
case CIRRUS_ID_CLGD5446:
if (info->local & 0x100)
romfn = BIOS_GD5446_STB_PATH;
else
romfn = BIOS_GD5446_PATH;
break;
case CIRRUS_ID_CLGD5480:
romfn = BIOS_GD5480_PATH;
break;
default:
break;
}
if (info->flags & DEVICE_MCA) {
if (id == CIRRUS_ID_CLGD5428)
vram = 1024;
else
vram = device_get_config_int("memory");
gd54xx->vram_size = vram << 10;
} else {
if (id <= CIRRUS_ID_CLGD5428) {
if ((id == CIRRUS_ID_CLGD5426) && (info->local & 0x200))
vram = 1024;
else if (id == CIRRUS_ID_CLGD5401)
vram = 256;
else if (id == CIRRUS_ID_CLGD5402)
vram = 512;
else
vram = device_get_config_int("memory");
gd54xx->vram_size = vram << 10;
} else {
vram = device_get_config_int("memory");
gd54xx->vram_size = vram << 20;
}
}
gd54xx->vram_mask = gd54xx->vram_size - 1;
if (romfn)
rom_init(&gd54xx->bios_rom, romfn, 0xc0000, 0x8000, 0x7fff, 0, MEM_MAPPING_EXTERNAL);
else if (romfn1 && romfn2)
rom_init_interleaved(&gd54xx->bios_rom, BIOS_GD5428_BOCA_ISA_PATH_1, BIOS_GD5428_BOCA_ISA_PATH_2, 0xc0000,
0x8000, 0x7fff, 0, MEM_MAPPING_EXTERNAL);
if (info->flags & DEVICE_ISA)
video_inform(VIDEO_FLAG_TYPE_SPECIAL, &timing_gd54xx_isa);
else if (info->flags & DEVICE_PCI)
video_inform(VIDEO_FLAG_TYPE_SPECIAL, &timing_gd54xx_pci);
else
video_inform(VIDEO_FLAG_TYPE_SPECIAL, &timing_gd54xx_vlb);
if (id >= CIRRUS_ID_CLGD5426) {
svga_init(info, &gd54xx->svga, gd54xx, gd54xx->vram_size,
gd54xx_recalctimings, gd54xx_in, gd54xx_out,
gd54xx_hwcursor_draw, gd54xx_overlay_draw);
} else {
svga_init(info, &gd54xx->svga, gd54xx, gd54xx->vram_size,
gd54xx_recalctimings, gd54xx_in, gd54xx_out,
gd54xx_hwcursor_draw, NULL);
}
svga->vblank_start = gd54xx_vblank_start;
svga->ven_write = gd54xx_write_modes45;
if ((vram == 1) || (vram >= 256 && vram <= 1024))
svga->decode_mask = gd54xx->vram_mask;
if (gd54xx->bit32) {
mem_mapping_set_handler(&svga->mapping, gd54xx_read, gd54xx_readw, gd54xx_readl, gd54xx_write, gd54xx_writew, gd54xx_writel);
mem_mapping_add(&gd54xx->mmio_mapping, 0, 0,
gd543x_mmio_read, gd543x_mmio_readw, gd543x_mmio_readl,
gd543x_mmio_writeb, gd543x_mmio_writew, gd543x_mmio_writel,
NULL, MEM_MAPPING_EXTERNAL, gd54xx);
mem_mapping_add(&gd54xx->linear_mapping, 0, 0,
gd54xx_readb_linear, gd54xx_readw_linear, gd54xx_readl_linear,
gd54xx_writeb_linear, gd54xx_writew_linear, gd54xx_writel_linear,
NULL, MEM_MAPPING_EXTERNAL, gd54xx);
mem_mapping_add(&gd54xx->aperture2_mapping, 0, 0,
gd5436_aperture2_readb, gd5436_aperture2_readw, gd5436_aperture2_readl,
gd5436_aperture2_writeb, gd5436_aperture2_writew, gd5436_aperture2_writel,
NULL, MEM_MAPPING_EXTERNAL, gd54xx);
mem_mapping_add(&gd54xx->vgablt_mapping, 0, 0,
gd5480_vgablt_read, gd5480_vgablt_readw, gd5480_vgablt_readl,
gd5480_vgablt_write, gd5480_vgablt_writew, gd5480_vgablt_writel,
NULL, MEM_MAPPING_EXTERNAL, gd54xx);
} else {
mem_mapping_set_handler(&svga->mapping, gd54xx_read, gd54xx_readw, NULL, gd54xx_write, gd54xx_writew, NULL);
mem_mapping_add(&gd54xx->mmio_mapping, 0, 0,
gd543x_mmio_read, gd543x_mmio_readw, NULL,
gd543x_mmio_writeb, gd543x_mmio_writew, NULL,
NULL, MEM_MAPPING_EXTERNAL, gd54xx);
mem_mapping_add(&gd54xx->linear_mapping, 0, 0,
gd54xx_readb_linear, gd54xx_readw_linear, NULL,
gd54xx_writeb_linear, gd54xx_writew_linear, NULL,
NULL, MEM_MAPPING_EXTERNAL, gd54xx);
mem_mapping_add(&gd54xx->aperture2_mapping, 0, 0,
gd5436_aperture2_readb, gd5436_aperture2_readw, NULL,
gd5436_aperture2_writeb, gd5436_aperture2_writew, NULL,
NULL, MEM_MAPPING_EXTERNAL, gd54xx);
mem_mapping_add(&gd54xx->vgablt_mapping, 0, 0,
gd5480_vgablt_read, gd5480_vgablt_readw, NULL,
gd5480_vgablt_write, gd5480_vgablt_writew, NULL,
NULL, MEM_MAPPING_EXTERNAL, gd54xx);
}
io_sethandler(0x03c0, 0x0020, gd54xx_in, NULL, NULL, gd54xx_out, NULL, NULL, gd54xx);
if (gd54xx->pci && id >= CIRRUS_ID_CLGD5430) {
if (romfn == NULL)
pci_add_card(PCI_ADD_VIDEO, cl_pci_read, cl_pci_write, gd54xx, &gd54xx->pci_slot);
else
pci_add_card(PCI_ADD_NORMAL, cl_pci_read, cl_pci_write, gd54xx, &gd54xx->pci_slot);
mem_mapping_disable(&gd54xx->bios_rom.mapping);
}
mem_mapping_set_p(&svga->mapping, gd54xx);
mem_mapping_disable(&gd54xx->mmio_mapping);
mem_mapping_disable(&gd54xx->linear_mapping);
mem_mapping_disable(&gd54xx->aperture2_mapping);
mem_mapping_disable(&gd54xx->vgablt_mapping);
svga->hwcursor.yoff = svga->hwcursor.xoff = 0;
if (id >= CIRRUS_ID_CLGD5420) {
gd54xx->vclk_n[0] = 0x4a;
gd54xx->vclk_d[0] = 0x2b;
gd54xx->vclk_n[1] = 0x5b;
gd54xx->vclk_d[1] = 0x2f;
gd54xx->vclk_n[2] = 0x45;
gd54xx->vclk_d[2] = 0x30;
gd54xx->vclk_n[3] = 0x7e;
gd54xx->vclk_d[3] = 0x33;
} else {
gd54xx->vclk_n[0] = 0x66;
gd54xx->vclk_d[0] = 0x3b;
gd54xx->vclk_n[1] = 0x5b;
gd54xx->vclk_d[1] = 0x2f;
gd54xx->vclk_n[2] = 0x45;
gd54xx->vclk_d[2] = 0x2c;
gd54xx->vclk_n[3] = 0x7e;
gd54xx->vclk_d[3] = 0x33;
}
svga->extra_banks[1] = 0x8000;
gd54xx->pci_regs[PCI_REG_COMMAND] = 7;
gd54xx->pci_regs[0x30] = 0x00;
gd54xx->pci_regs[0x32] = 0x0c;
gd54xx->pci_regs[0x33] = 0x00;
svga->crtc[0x27] = id;
svga->seqregs[6] = 0x0f;
if (svga->crtc[0x27] >= CIRRUS_ID_CLGD5429)
gd54xx->unlocked = 1;
if (gd54xx->mca) {
gd54xx->pos_regs[0] = svga->crtc[0x27] == CIRRUS_ID_CLGD5426 ? 0x82 : 0x7b;
gd54xx->pos_regs[1] = svga->crtc[0x27] == CIRRUS_ID_CLGD5426 ? 0x81 : 0x91;
mem_mapping_disable(&gd54xx->bios_rom.mapping);
mca_add(gd5428_mca_read, gd5428_mca_write, gd5428_mca_feedb, NULL, gd54xx);
io_sethandler(0x46e8, 0x0001, gd54xx_in, NULL, NULL, gd54xx_out, NULL, NULL, gd54xx);
}
if (gd54xx_is_5434(svga)) {
gd54xx->i2c = i2c_gpio_init("ddc_cl54xx");
gd54xx->ddc = ddc_init(i2c_gpio_get_bus(gd54xx->i2c));
}
if (svga->crtc[0x27] >= CIRRUS_ID_CLGD5446)
gd54xx->crtcreg_mask = 0x7f;
else
gd54xx->crtcreg_mask = 0x3f;
gd54xx->overlay.colorkeycompare = 0xff;
return gd54xx;
}
static int
gd5401_available(void)
{
return rom_present(BIOS_GD5401_PATH);
}
static int
gd5402_available(void)
{
return rom_present(BIOS_GD5402_PATH);
}
static int
gd5420_available(void)
{
return rom_present(BIOS_GD5420_PATH);
}
static int
gd5422_available(void)
{
return rom_present(BIOS_GD5422_PATH);
}
static int
gd5426_diamond_a1_available(void)
{
return rom_present(BIOS_GD5426_DIAMOND_A1_ISA_PATH);
}
static int
gd5428_available(void)
{
return rom_present(BIOS_GD5428_PATH);
}
static int
gd5428_diamond_b1_available(void)
{
return rom_present(BIOS_GD5428_DIAMOND_B1_VLB_PATH);
}
static int
gd5428_boca_isa_available(void)
{
return rom_present(BIOS_GD5428_BOCA_ISA_PATH_1) && rom_present(BIOS_GD5428_BOCA_ISA_PATH_2);
}
static int
gd5428_isa_available(void)
{
return rom_present(BIOS_GD5428_ISA_PATH);
}
static int
gd5426_mca_available(void)
{
return rom_present(BIOS_GD5426_MCA_PATH);
}
static int
gd5428_mca_available(void)
{
return rom_present(BIOS_GD5428_MCA_PATH);
}
static int
gd5429_available(void)
{
return rom_present(BIOS_GD5429_PATH);
}
static int
gd5430_diamond_a8_available(void)
{
return rom_present(BIOS_GD5430_DIAMOND_A8_VLB_PATH);
}
static int
gd5430_available(void)
{
return rom_present(BIOS_GD5430_PATH);
}
static int
gd5434_available(void)
{
return rom_present(BIOS_GD5434_PATH);
}
static int
gd5434_isa_available(void)
{
return rom_present(BIOS_GD5434_PATH);
}
static int
gd5430_orchid_vlb_available(void)
{
return rom_present(BIOS_GD5430_ORCHID_VLB_PATH);
}
static int
gd5434_diamond_a3_available(void)
{
return rom_present(BIOS_GD5434_DIAMOND_A3_ISA_PATH);
}
static int
gd5436_available(void)
{
return rom_present(BIOS_GD5436_PATH);
}
static int
gd5440_available(void)
{
return rom_present(BIOS_GD5440_PATH);
}
static int
gd5446_available(void)
{
return rom_present(BIOS_GD5446_PATH);
}
static int
gd5446_stb_available(void)
{
return rom_present(BIOS_GD5446_STB_PATH);
}
static int
gd5480_available(void)
{
return rom_present(BIOS_GD5480_PATH);
}
void
gd54xx_close(void *priv)
{
gd54xx_t *gd54xx = (gd54xx_t *) priv;
svga_close(&gd54xx->svga);
if (gd54xx->i2c) {
ddc_close(gd54xx->ddc);
i2c_gpio_close(gd54xx->i2c);
}
free(gd54xx);
}
void
gd54xx_speed_changed(void *priv)
{
gd54xx_t *gd54xx = (gd54xx_t *) priv;
svga_recalctimings(&gd54xx->svga);
}
void
gd54xx_force_redraw(void *priv)
{
gd54xx_t *gd54xx = (gd54xx_t *) priv;
gd54xx->svga.fullchange = gd54xx->svga.monitor->mon_changeframecount;
}
// clang-format off
static const device_config_t gd542x_config[] = {
{
.name = "memory",
.description = "Memory size",
.type = CONFIG_SELECTION,
.selection = {
{
.description = "512 KB",
.value = 512
},
{
.description = "1 MB",
.value = 1024
},
{
.description = ""
}
},
.default_int = 512
},
{
.type = CONFIG_END
}
};
static const device_config_t gd5426_config[] = {
{
.name = "memory",
.description = "Memory size",
.type = CONFIG_SELECTION,
.selection = {
{
.description = "512 KB",
.value = 512
},
{
.description = "1 MB",
.value = 1024
},
{
.description = "2 MB",
.value = 2048
},
{
.description = ""
}
},
.default_int = 2048
},
{
.type = CONFIG_END
}
};
static const device_config_t gd5428_onboard_config[] = {
{
.name = "memory",
.description = "Onboard memory size",
.type = CONFIG_SELECTION,
.selection = {
{
.description = "512 KB",
.value = 512
},
{
.description = "1 MB",
.value = 1024
},
{
.description = "2 MB",
.value = 2048
},
{
.description = ""
}
},
.default_int = 2048
},
{
.type = CONFIG_END
}
};
static const device_config_t gd5429_config[] = {
{
.name = "memory",
.description = "Memory size",
.type = CONFIG_SELECTION,
.selection = {
{
.description = "1 MB",
.value = 1
},
{
.description = "2 MB",
.value = 2
},
{
.description = ""
}
},
.default_int = 2
},
{
.type = CONFIG_END
}
};
static const device_config_t gd5440_onboard_config[] = {
{
.name = "memory",
.description = "Onboard memory size",
.type = CONFIG_SELECTION,
.selection = {
{
.description = "1 MB",
.value = 1
},
{
.description = "2 MB",
.value = 2
},
{
.description = ""
}
},
.default_int = 2
},
{
.type = CONFIG_END
}
};
static const device_config_t gd5434_config[] = {
{
.name = "memory",
.description = "Memory size",
.type = CONFIG_SELECTION,
.selection = {
{
.description = "1 MB",
.value = 1
},
{
.description = "2 MB",
.value = 2
},
{
.description = "4 MB",
.value = 4
},
{
.description = ""
}
},
.default_int = 4
},
{
.type = CONFIG_END
}
};
static const device_config_t gd5434_onboard_config[] = {
{
.name = "memory",
.description = "Onboard memory size",
.type = CONFIG_SELECTION,
.selection = {
{
.description = "1 MB",
.value = 1
},
{
.description = "2 MB",
.value = 2
},
{
.description = "4 MB",
.value = 4
},
{
.description = ""
}
},
.default_int = 4
},
{
.type = CONFIG_END
}
};
static const device_config_t gd5480_config[] = {
{
.name = "memory",
.description = "Memory size",
.type = CONFIG_SELECTION,
.selection = {
{
.description = "2 MB",
.value = 2
},
{
.description = "4 MB",
.value = 4
},
{
.description = ""
}
},
.default_int = 4
},
{
.type = -1
}
};
// clang-format on
const device_t gd5401_isa_device = {
.name = "Cirrus Logic GD5401 (ISA) (ACUMOS AVGA1)",
.internal_name = "cl_gd5401_isa",
.flags = DEVICE_ISA,
.local = CIRRUS_ID_CLGD5401,
.init = gd54xx_init,
.close = gd54xx_close,
.reset = gd54xx_reset,
{ .available = gd5401_available },
.speed_changed = gd54xx_speed_changed,
.force_redraw = gd54xx_force_redraw,
.config = NULL,
};
const device_t gd5402_isa_device = {
.name = "Cirrus Logic GD5402 (ISA) (ACUMOS AVGA2)",
.internal_name = "cl_gd5402_isa",
.flags = DEVICE_ISA,
.local = CIRRUS_ID_CLGD5402,
.init = gd54xx_init,
.close = gd54xx_close,
.reset = gd54xx_reset,
{ .available = gd5402_available },
.speed_changed = gd54xx_speed_changed,
.force_redraw = gd54xx_force_redraw,
.config = NULL,
};
const device_t gd5402_onboard_device = {
.name = "Cirrus Logic GD5402 (ISA) (ACUMOS AVGA2) (On-Board)",
.internal_name = "cl_gd5402_onboard",
.flags = DEVICE_AT | DEVICE_ISA,
.local = CIRRUS_ID_CLGD5402 | 0x200,
.init = gd54xx_init,
.close = gd54xx_close,
.reset = gd54xx_reset,
{ .available = NULL },
.speed_changed = gd54xx_speed_changed,
.force_redraw = gd54xx_force_redraw,
.config = NULL,
};
const device_t gd5420_isa_device = {
.name = "Cirrus Logic GD5420 (ISA)",
.internal_name = "cl_gd5420_isa",
.flags = DEVICE_AT | DEVICE_ISA,
.local = CIRRUS_ID_CLGD5420,
.init = gd54xx_init,
.close = gd54xx_close,
.reset = gd54xx_reset,
{ .available = gd5420_available },
.speed_changed = gd54xx_speed_changed,
.force_redraw = gd54xx_force_redraw,
.config = gd542x_config,
};
const device_t gd5422_isa_device = {
.name = "Cirrus Logic GD5422 (ISA)",
.internal_name = "cl_gd5422_isa",
.flags = DEVICE_AT | DEVICE_ISA,
.local = CIRRUS_ID_CLGD5422,
.init = gd54xx_init,
.close = gd54xx_close,
.reset = gd54xx_reset,
{ .available = gd5422_available }, /* Common BIOS between 5422 and 5424 */
.speed_changed = gd54xx_speed_changed,
.force_redraw = gd54xx_force_redraw,
.config = gd542x_config,
};
const device_t gd5424_vlb_device = {
.name = "Cirrus Logic GD5424 (VLB)",
.internal_name = "cl_gd5424_vlb",
.flags = DEVICE_VLB,
.local = CIRRUS_ID_CLGD5424,
.init = gd54xx_init,
.close = gd54xx_close,
.reset = gd54xx_reset,
{ .available = gd5422_available }, /* Common BIOS between 5422 and 5424 */
.speed_changed = gd54xx_speed_changed,
.force_redraw = gd54xx_force_redraw,
.config = gd542x_config,
};
const device_t gd5426_isa_device = {
.name = "Cirrus Logic GD5426 (ISA)",
.internal_name = "cl_gd5426_isa",
.flags = DEVICE_AT | DEVICE_ISA,
.local = CIRRUS_ID_CLGD5426,
.init = gd54xx_init,
.close = gd54xx_close,
.reset = gd54xx_reset,
{ .available = gd5428_isa_available },
.speed_changed = gd54xx_speed_changed,
.force_redraw = gd54xx_force_redraw,
.config = gd5426_config
};
/*According to a Diamond bios file listing and vgamuseum*/
const device_t gd5426_diamond_speedstar_pro_a1_isa_device = {
.name = "Cirrus Logic GD5426 (ISA) (Diamond SpeedStar Pro Rev. A1)",
.internal_name = "cl_gd5426_diamond_a1_isa",
.flags = DEVICE_AT | DEVICE_ISA,
.local = CIRRUS_ID_CLGD5426 | 0x100,
.init = gd54xx_init,
.close = gd54xx_close,
.reset = gd54xx_reset,
{ .available = gd5426_diamond_a1_available },
.speed_changed = gd54xx_speed_changed,
.force_redraw = gd54xx_force_redraw,
.config = gd5426_config
};
const device_t gd5426_vlb_device = {
.name = "Cirrus Logic GD5426 (VLB)",
.internal_name = "cl_gd5426_vlb",
.flags = DEVICE_VLB,
.local = CIRRUS_ID_CLGD5426,
.init = gd54xx_init,
.close = gd54xx_close,
.reset = gd54xx_reset,
{ .available = gd5428_available },
.speed_changed = gd54xx_speed_changed,
.force_redraw = gd54xx_force_redraw,
.config = gd5426_config
};
const device_t gd5426_onboard_device = {
.name = "Cirrus Logic GD5426 (VLB) (On-Board)",
.internal_name = "cl_gd5426_onboard",
.flags = DEVICE_VLB,
.local = CIRRUS_ID_CLGD5426 | 0x200,
.init = gd54xx_init,
.close = gd54xx_close,
.reset = gd54xx_reset,
{ .available = NULL },
.speed_changed = gd54xx_speed_changed,
.force_redraw = gd54xx_force_redraw,
.config = NULL
};
const device_t gd5428_isa_device = {
.name = "Cirrus Logic GD5428 (ISA)",
.internal_name = "cl_gd5428_isa",
.flags = DEVICE_AT | DEVICE_ISA,
.local = CIRRUS_ID_CLGD5428,
.init = gd54xx_init,
.close = gd54xx_close,
.reset = gd54xx_reset,
{ .available = gd5428_isa_available },
.speed_changed = gd54xx_speed_changed,
.force_redraw = gd54xx_force_redraw,
.config = gd5426_config
};
const device_t gd5428_vlb_device = {
.name = "Cirrus Logic GD5428 (VLB)",
.internal_name = "cl_gd5428_vlb",
.flags = DEVICE_VLB,
.local = CIRRUS_ID_CLGD5428,
.init = gd54xx_init,
.close = gd54xx_close,
.reset = gd54xx_reset,
{ .available = gd5428_available },
.speed_changed = gd54xx_speed_changed,
.force_redraw = gd54xx_force_redraw,
.config = gd5426_config
};
/*According to a Diamond bios file listing and vgamuseum*/
const device_t gd5428_diamond_speedstar_pro_b1_vlb_device = {
.name = "Cirrus Logic GD5428 (VLB) (Diamond SpeedStar Pro Rev. B1)",
.internal_name = "cl_gd5428_diamond_b1_vlb",
.flags = DEVICE_VLB,
.local = CIRRUS_ID_CLGD5428 | 0x100,
.init = gd54xx_init,
.close = gd54xx_close,
.reset = gd54xx_reset,
{ .available = gd5428_diamond_b1_available },
.speed_changed = gd54xx_speed_changed,
.force_redraw = gd54xx_force_redraw,
.config = gd5426_config
};
const device_t gd5428_boca_isa_device = {
.name = "Cirrus Logic GD5428 (ISA) (BOCA Research 4610)",
.internal_name = "cl_gd5428_boca_isa",
.flags = DEVICE_AT | DEVICE_ISA,
.local = CIRRUS_ID_CLGD5428 | 0x100,
.init = gd54xx_init,
.close = gd54xx_close,
.reset = gd54xx_reset,
{ .available = gd5428_boca_isa_available },
.speed_changed = gd54xx_speed_changed,
.force_redraw = gd54xx_force_redraw,
.config = gd5426_config
};
const device_t gd5428_mca_device = {
.name = "Cirrus Logic GD5428 (MCA) (IBM SVGA Adapter/A)",
.internal_name = "ibm1mbsvga",
.flags = DEVICE_MCA,
.local = CIRRUS_ID_CLGD5428,
.init = gd54xx_init,
.close = gd54xx_close,
.reset = gd54xx_reset,
{ .available = gd5428_mca_available },
.speed_changed = gd54xx_speed_changed,
.force_redraw = gd54xx_force_redraw,
.config = NULL
};
const device_t gd5426_mca_device = {
.name = "Cirrus Logic GD5426 (MCA) (Reply Video Adapter)",
.internal_name = "replymcasvga",
.flags = DEVICE_MCA,
.local = CIRRUS_ID_CLGD5426,
.init = gd54xx_init,
.close = gd54xx_close,
.reset = gd54xx_reset,
{ .available = gd5426_mca_available },
.speed_changed = gd54xx_speed_changed,
.force_redraw = gd54xx_force_redraw,
.config = gd5426_config
};
const device_t gd5428_onboard_device = {
.name = "Cirrus Logic GD5428 (ISA) (On-Board)",
.internal_name = "cl_gd5428_onboard",
.flags = DEVICE_AT | DEVICE_ISA,
.local = CIRRUS_ID_CLGD5428,
.init = gd54xx_init,
.close = gd54xx_close,
.reset = gd54xx_reset,
{ .available = gd5428_isa_available },
.speed_changed = gd54xx_speed_changed,
.force_redraw = gd54xx_force_redraw,
.config = gd5428_onboard_config
};
const device_t gd5428_vlb_onboard_device = {
.name = "Cirrus Logic GD5428 (VLB) (On-Board)",
.internal_name = "cl_gd5428_vlb_onboard",
.flags = DEVICE_VLB,
.local = CIRRUS_ID_CLGD5428,
.init = gd54xx_init,
.close = gd54xx_close,
.reset = gd54xx_reset,
{ .available = NULL },
.speed_changed = gd54xx_speed_changed,
.force_redraw = gd54xx_force_redraw,
.config = gd5428_onboard_config
};
const device_t gd5429_isa_device = {
.name = "Cirrus Logic GD5429 (ISA)",
.internal_name = "cl_gd5429_isa",
.flags = DEVICE_AT | DEVICE_ISA,
.local = CIRRUS_ID_CLGD5429,
.init = gd54xx_init,
.close = gd54xx_close,
.reset = gd54xx_reset,
{ .available = gd5429_available },
.speed_changed = gd54xx_speed_changed,
.force_redraw = gd54xx_force_redraw,
.config = gd5429_config
};
const device_t gd5429_vlb_device = {
.name = "Cirrus Logic GD5429 (VLB)",
.internal_name = "cl_gd5429_vlb",
.flags = DEVICE_VLB,
.local = CIRRUS_ID_CLGD5429,
.init = gd54xx_init,
.close = gd54xx_close,
.reset = gd54xx_reset,
{ .available = gd5429_available },
.speed_changed = gd54xx_speed_changed,
.force_redraw = gd54xx_force_redraw,
.config = gd5429_config
};
/*According to a Diamond bios file listing and vgamuseum*/
const device_t gd5430_diamond_speedstar_pro_se_a8_vlb_device = {
.name = "Cirrus Logic GD5430 (VLB) (Diamond SpeedStar Pro SE Rev. A8)",
.internal_name = "cl_gd5430_vlb_diamond",
.flags = DEVICE_VLB,
.local = CIRRUS_ID_CLGD5430,
.init = gd54xx_init,
.close = gd54xx_close,
.reset = gd54xx_reset,
{ .available = gd5430_diamond_a8_available },
.speed_changed = gd54xx_speed_changed,
.force_redraw = gd54xx_force_redraw,
.config = gd5429_config
};
const device_t gd5430_vlb_device = {
.name = "Cirrus Logic GD5430",
.internal_name = "cl_gd5430_vlb",
.flags = DEVICE_VLB,
.local = CIRRUS_ID_CLGD5430 | 0x100,
.init = gd54xx_init,
.close = gd54xx_close,
.reset = gd54xx_reset,
{ .available = gd5430_orchid_vlb_available },
.speed_changed = gd54xx_speed_changed,
.force_redraw = gd54xx_force_redraw,
.config = gd5429_config
};
const device_t gd5430_onboard_vlb_device = {
.name = "Cirrus Logic GD5430 (On-Board)",
.internal_name = "cl_gd5430_onboard_vlb",
.flags = DEVICE_VLB,
.local = CIRRUS_ID_CLGD5430 | 0x200,
.init = gd54xx_init,
.close = gd54xx_close,
.reset = gd54xx_reset,
{ .available = NULL },
.speed_changed = gd54xx_speed_changed,
.force_redraw = gd54xx_force_redraw,
.config = gd5429_config
};
const device_t gd5430_pci_device = {
.name = "Cirrus Logic GD5430 (PCI)",
.internal_name = "cl_gd5430_pci",
.flags = DEVICE_PCI,
.local = CIRRUS_ID_CLGD5430,
.init = gd54xx_init,
.close = gd54xx_close,
.reset = gd54xx_reset,
{ .available = gd5430_available },
.speed_changed = gd54xx_speed_changed,
.force_redraw = gd54xx_force_redraw,
.config = gd5429_config
};
const device_t gd5430_onboard_pci_device = {
.name = "Cirrus Logic GD5430 (PCI) (On-Board)",
.internal_name = "cl_gd5430_onboard_pci",
.flags = DEVICE_PCI,
.local = CIRRUS_ID_CLGD5430 | 0x200,
.init = gd54xx_init,
.close = gd54xx_close,
.reset = gd54xx_reset,
{ .available = NULL },
.speed_changed = gd54xx_speed_changed,
.force_redraw = gd54xx_force_redraw,
.config = gd5429_config
};
const device_t gd5434_isa_device = {
.name = "Cirrus Logic GD5434 (ISA)",
.internal_name = "cl_gd5434_isa",
.flags = DEVICE_AT | DEVICE_ISA,
.local = CIRRUS_ID_CLGD5434,
.init = gd54xx_init,
.close = gd54xx_close,
.reset = gd54xx_reset,
{ .available = gd5434_isa_available },
.speed_changed = gd54xx_speed_changed,
.force_redraw = gd54xx_force_redraw,
.config = gd5434_config
};
/*According to a Diamond bios file listing and vgamuseum*/
const device_t gd5434_diamond_speedstar_64_a3_isa_device = {
.name = "Cirrus Logic GD5434 (ISA) (Diamond SpeedStar 64 Rev. A3)",
.internal_name = "cl_gd5434_diamond_a3_isa",
.flags = DEVICE_AT | DEVICE_ISA,
.local = CIRRUS_ID_CLGD5434 | 0x100,
.init = gd54xx_init,
.close = gd54xx_close,
.reset = gd54xx_reset,
{ .available = gd5434_diamond_a3_available },
.speed_changed = gd54xx_speed_changed,
.force_redraw = gd54xx_force_redraw,
.config = gd5429_config
};
const device_t gd5434_onboard_pci_device = {
.name = "Cirrus Logic GD5434-4 (PCI) (On-Board)",
.internal_name = "cl_gd5434_onboard_pci",
.flags = DEVICE_PCI,
.local = CIRRUS_ID_CLGD5434 | 0x200,
.init = gd54xx_init,
.close = gd54xx_close,
.reset = gd54xx_reset,
{ .available = NULL },
.speed_changed = gd54xx_speed_changed,
.force_redraw = gd54xx_force_redraw,
.config = gd5434_onboard_config
};
const device_t gd5434_vlb_device = {
.name = "Cirrus Logic GD5434 (VLB)",
.internal_name = "cl_gd5434_vlb",
.flags = DEVICE_VLB,
.local = CIRRUS_ID_CLGD5434,
.init = gd54xx_init,
.close = gd54xx_close,
.reset = gd54xx_reset,
{ .available = gd5430_orchid_vlb_available },
.speed_changed = gd54xx_speed_changed,
.force_redraw = gd54xx_force_redraw,
.config = gd5434_config
};
const device_t gd5434_pci_device = {
.name = "Cirrus Logic GD5434 (PCI)",
.internal_name = "cl_gd5434_pci",
.flags = DEVICE_PCI,
.local = CIRRUS_ID_CLGD5434,
.init = gd54xx_init,
.close = gd54xx_close,
.reset = gd54xx_reset,
{ .available = gd5434_available },
.speed_changed = gd54xx_speed_changed,
.force_redraw = gd54xx_force_redraw,
.config = gd5434_config
};
const device_t gd5436_onboard_pci_device = {
.name = "Cirrus Logic GD5436 (PCI) (On-Board)",
.internal_name = "cl_gd5436_onboard_pci",
.flags = DEVICE_PCI,
.local = CIRRUS_ID_CLGD5436 | 0x200,
.init = gd54xx_init,
.close = gd54xx_close,
.reset = gd54xx_reset,
{ .available = NULL },
.speed_changed = gd54xx_speed_changed,
.force_redraw = gd54xx_force_redraw,
.config = gd5434_config
};
const device_t gd5436_pci_device = {
.name = "Cirrus Logic GD5436 (PCI)",
.internal_name = "cl_gd5436_pci",
.flags = DEVICE_PCI,
.local = CIRRUS_ID_CLGD5436,
.init = gd54xx_init,
.close = gd54xx_close,
.reset = gd54xx_reset,
{ .available = gd5436_available },
.speed_changed = gd54xx_speed_changed,
.force_redraw = gd54xx_force_redraw,
.config = gd5434_config
};
const device_t gd5440_onboard_pci_device = {
.name = "Cirrus Logic GD5440 (PCI) (On-Board)",
.internal_name = "cl_gd5440_onboard_pci",
.flags = DEVICE_PCI,
.local = CIRRUS_ID_CLGD5440 | 0x600,
.init = gd54xx_init,
.close = gd54xx_close,
.reset = gd54xx_reset,
{ .available = NULL },
.speed_changed = gd54xx_speed_changed,
.force_redraw = gd54xx_force_redraw,
.config = gd5440_onboard_config
};
const device_t gd5440_pci_device = {
.name = "Cirrus Logic GD5440 (PCI)",
.internal_name = "cl_gd5440_pci",
.flags = DEVICE_PCI,
.local = CIRRUS_ID_CLGD5440 | 0x400,
.init = gd54xx_init,
.close = gd54xx_close,
.reset = gd54xx_reset,
{ .available = gd5440_available },
.speed_changed = gd54xx_speed_changed,
.force_redraw = gd54xx_force_redraw,
.config = gd5429_config
};
const device_t gd5446_pci_device = {
.name = "Cirrus Logic GD5446 (PCI)",
.internal_name = "cl_gd5446_pci",
.flags = DEVICE_PCI,
.local = CIRRUS_ID_CLGD5446,
.init = gd54xx_init,
.close = gd54xx_close,
.reset = gd54xx_reset,
{ .available = gd5446_available },
.speed_changed = gd54xx_speed_changed,
.force_redraw = gd54xx_force_redraw,
.config = gd5434_config
};
const device_t gd5446_stb_pci_device = {
.name = "Cirrus Logic GD5446 (PCI) (STB Nitro 64V)",
.internal_name = "cl_gd5446_stb_pci",
.flags = DEVICE_PCI,
.local = CIRRUS_ID_CLGD5446 | 0x100,
.init = gd54xx_init,
.close = gd54xx_close,
.reset = gd54xx_reset,
{ .available = gd5446_stb_available },
.speed_changed = gd54xx_speed_changed,
.force_redraw = gd54xx_force_redraw,
.config = gd5434_config
};
const device_t gd5480_pci_device = {
.name = "Cirrus Logic GD5480 (PCI)",
.internal_name = "cl_gd5480_pci",
.flags = DEVICE_PCI,
.local = CIRRUS_ID_CLGD5480,
.init = gd54xx_init,
.close = gd54xx_close,
.reset = gd54xx_reset,
{ .available = gd5480_available },
.speed_changed = gd54xx_speed_changed,
.force_redraw = gd54xx_force_redraw,
.config = gd5480_config
};
``` | /content/code_sandbox/src/video/vid_cl54xx.c | c | 2016-06-25T22:29:10 | 2024-08-16T19:09:21 | 86Box | 86Box/86Box | 2,616 | 55,389 |
```c
/*
* 86Box A hypervisor and IBM PC system emulator that specializes in
* running old operating systems and software designed for IBM
* PC systems and compatibles from 1981 through fairly recent
* system designs based on the PCI bus.
*
* This file is part of the 86Box distribution.
*
* 3DFX Voodoo emulation.
*
*
*
* Authors: Sarah Walker, <path_to_url
*
*/
#include <stdarg.h>
#include <stdio.h>
#include <stdint.h>
#include <string.h>
#include <stdlib.h>
#include <stddef.h>
#include <wchar.h>
#include <math.h>
#define HAVE_STDARG_H
#include <86box/86box.h>
#include "cpu.h"
#include <86box/machine.h>
#include <86box/device.h>
#include <86box/mem.h>
#include <86box/timer.h>
#include <86box/device.h>
#include <86box/plat.h>
#include <86box/thread.h>
#include <86box/video.h>
#include <86box/vid_svga.h>
#include <86box/vid_voodoo_common.h>
#include <86box/vid_voodoo_banshee_blitter.h>
#include <86box/vid_voodoo_fb.h>
#include <86box/vid_voodoo_fifo.h>
#include <86box/vid_voodoo_reg.h>
#include <86box/vid_voodoo_regs.h>
#include <86box/vid_voodoo_render.h>
#include <86box/vid_voodoo_texture.h>
#ifdef ENABLE_VOODOO_FIFO_LOG
int voodoo_fifo_do_log = ENABLE_VOODOO_FIFO_LOG;
static void
voodoo_fifo_log(const char *fmt, ...)
{
va_list ap;
if (voodoo_fifo_do_log) {
va_start(ap, fmt);
pclog_ex(fmt, ap);
va_end(ap);
}
}
#else
# define voodoo_fifo_log(fmt, ...)
#endif
#define WAKE_DELAY (TIMER_USEC * 100)
void
voodoo_wake_fifo_thread(voodoo_t *voodoo)
{
if (!timer_is_enabled(&voodoo->wake_timer)) {
/*Don't wake FIFO thread immediately - if we do that it will probably
process one word and go back to sleep, requiring it to be woken on
almost every write. Instead, wait a short while so that the CPU
emulation writes more data so we have more batched-up work.*/
timer_set_delay_u64(&voodoo->wake_timer, WAKE_DELAY);
}
}
void
voodoo_wake_fifo_thread_now(voodoo_t *voodoo)
{
thread_set_event(voodoo->wake_fifo_thread); /*Wake up FIFO thread if moving from idle*/
}
void
voodoo_wake_timer(void *priv)
{
voodoo_t *voodoo = (voodoo_t *) priv;
thread_set_event(voodoo->wake_fifo_thread); /*Wake up FIFO thread if moving from idle*/
}
void
voodoo_queue_command(voodoo_t *voodoo, uint32_t addr_type, uint32_t val)
{
fifo_entry_t *fifo = &voodoo->fifo[voodoo->fifo_write_idx & FIFO_MASK];
while (FIFO_FULL) {
thread_reset_event(voodoo->fifo_not_full_event);
if (FIFO_FULL) {
thread_wait_event(voodoo->fifo_not_full_event, 1); /*Wait for room in ringbuffer*/
if (FIFO_FULL)
voodoo_wake_fifo_thread_now(voodoo);
}
}
fifo->val = val;
fifo->addr_type = addr_type;
voodoo->fifo_write_idx++;
voodoo->cmd_status &= ~(1 << 24);
if (FIFO_ENTRIES > 0xe000)
voodoo_wake_fifo_thread(voodoo);
}
void
voodoo_flush(voodoo_t *voodoo)
{
voodoo->flush = 1;
while (!FIFO_EMPTY) {
voodoo_wake_fifo_thread_now(voodoo);
thread_wait_event(voodoo->fifo_not_full_event, 1);
}
voodoo_wait_for_render_thread_idle(voodoo);
voodoo->flush = 0;
}
void
voodoo_wake_fifo_threads(voodoo_set_t *set, voodoo_t *voodoo)
{
voodoo_wake_fifo_thread(voodoo);
if (SLI_ENABLED && voodoo->type != VOODOO_2 && set->voodoos[0] == voodoo)
voodoo_wake_fifo_thread(set->voodoos[1]);
}
void
voodoo_wait_for_swap_complete(voodoo_t *voodoo)
{
while (voodoo->swap_pending) {
thread_wait_event(voodoo->wake_fifo_thread, -1);
thread_reset_event(voodoo->wake_fifo_thread);
thread_wait_mutex(voodoo->swap_mutex);
if ((voodoo->swap_pending && voodoo->flush) || FIFO_FULL) {
/*Main thread is waiting for FIFO to empty, so skip vsync wait and just swap*/
memset(voodoo->dirty_line, 1, sizeof(voodoo->dirty_line));
voodoo->front_offset = voodoo->params.front_offset;
if (voodoo->swap_count > 0)
voodoo->swap_count--;
voodoo->swap_pending = 0;
thread_release_mutex(voodoo->swap_mutex);
break;
} else
thread_release_mutex(voodoo->swap_mutex);
}
}
static uint32_t
cmdfifo_get(voodoo_t *voodoo)
{
uint32_t val;
if (!voodoo->cmdfifo_in_sub) {
while (voodoo->fifo_thread_run && (voodoo->cmdfifo_depth_rd == voodoo->cmdfifo_depth_wr)) {
thread_wait_event(voodoo->wake_fifo_thread, -1);
thread_reset_event(voodoo->wake_fifo_thread);
}
}
val = *(uint32_t *) &voodoo->fb_mem[voodoo->cmdfifo_rp & voodoo->fb_mask];
if (!voodoo->cmdfifo_in_sub)
voodoo->cmdfifo_depth_rd++;
voodoo->cmdfifo_rp += 4;
// voodoo_fifo_log(" CMDFIFO get %08x\n", val);
return val;
}
static inline float
cmdfifo_get_f(voodoo_t *voodoo)
{
union {
uint32_t i;
float f;
} tempif;
tempif.i = cmdfifo_get(voodoo);
return tempif.f;
}
enum {
CMDFIFO3_PC_MASK_RGB = (1 << 10),
CMDFIFO3_PC_MASK_ALPHA = (1 << 11),
CMDFIFO3_PC_MASK_Z = (1 << 12),
CMDFIFO3_PC_MASK_Wb = (1 << 13),
CMDFIFO3_PC_MASK_W0 = (1 << 14),
CMDFIFO3_PC_MASK_S0_T0 = (1 << 15),
CMDFIFO3_PC_MASK_W1 = (1 << 16),
CMDFIFO3_PC_MASK_S1_T1 = (1 << 17),
CMDFIFO3_PC = (1 << 28)
};
void
voodoo_fifo_thread(void *param)
{
voodoo_t *voodoo = (voodoo_t *) param;
while (voodoo->fifo_thread_run) {
thread_set_event(voodoo->fifo_not_full_event);
thread_wait_event(voodoo->wake_fifo_thread, -1);
thread_reset_event(voodoo->wake_fifo_thread);
voodoo->voodoo_busy = 1;
while (!FIFO_EMPTY) {
uint64_t start_time = plat_timer_read();
uint64_t end_time;
fifo_entry_t *fifo = &voodoo->fifo[voodoo->fifo_read_idx & FIFO_MASK];
switch (fifo->addr_type & FIFO_TYPE) {
case FIFO_WRITEL_REG:
while ((fifo->addr_type & FIFO_TYPE) == FIFO_WRITEL_REG) {
voodoo_reg_writel(fifo->addr_type & FIFO_ADDR, fifo->val, voodoo);
fifo->addr_type = FIFO_INVALID;
voodoo->fifo_read_idx++;
if (FIFO_EMPTY)
break;
fifo = &voodoo->fifo[voodoo->fifo_read_idx & FIFO_MASK];
}
break;
case FIFO_WRITEW_FB:
voodoo_wait_for_render_thread_idle(voodoo);
while ((fifo->addr_type & FIFO_TYPE) == FIFO_WRITEW_FB) {
voodoo_fb_writew(fifo->addr_type & FIFO_ADDR, fifo->val, voodoo);
fifo->addr_type = FIFO_INVALID;
voodoo->fifo_read_idx++;
if (FIFO_EMPTY)
break;
fifo = &voodoo->fifo[voodoo->fifo_read_idx & FIFO_MASK];
}
break;
case FIFO_WRITEL_FB:
voodoo_wait_for_render_thread_idle(voodoo);
while ((fifo->addr_type & FIFO_TYPE) == FIFO_WRITEL_FB) {
voodoo_fb_writel(fifo->addr_type & FIFO_ADDR, fifo->val, voodoo);
fifo->addr_type = FIFO_INVALID;
voodoo->fifo_read_idx++;
if (FIFO_EMPTY)
break;
fifo = &voodoo->fifo[voodoo->fifo_read_idx & FIFO_MASK];
}
break;
case FIFO_WRITEL_TEX:
while ((fifo->addr_type & FIFO_TYPE) == FIFO_WRITEL_TEX) {
if (!(fifo->addr_type & 0x400000))
voodoo_tex_writel(fifo->addr_type & FIFO_ADDR, fifo->val, voodoo);
fifo->addr_type = FIFO_INVALID;
voodoo->fifo_read_idx++;
if (FIFO_EMPTY)
break;
fifo = &voodoo->fifo[voodoo->fifo_read_idx & FIFO_MASK];
}
break;
case FIFO_WRITEL_2DREG:
while ((fifo->addr_type & FIFO_TYPE) == FIFO_WRITEL_2DREG) {
voodoo_2d_reg_writel(voodoo, fifo->addr_type & FIFO_ADDR, fifo->val);
fifo->addr_type = FIFO_INVALID;
voodoo->fifo_read_idx++;
if (FIFO_EMPTY)
break;
fifo = &voodoo->fifo[voodoo->fifo_read_idx & FIFO_MASK];
}
break;
default:
fatal("Unknown fifo entry %08x\n", fifo->addr_type);
}
if (FIFO_ENTRIES > 0xe000)
thread_set_event(voodoo->fifo_not_full_event);
end_time = plat_timer_read();
voodoo->time += end_time - start_time;
}
voodoo->cmd_status |= (1 << 24);
while (voodoo->cmdfifo_enabled && (voodoo->cmdfifo_depth_rd != voodoo->cmdfifo_depth_wr || voodoo->cmdfifo_in_sub)) {
uint64_t start_time = plat_timer_read();
uint64_t end_time;
uint32_t header = cmdfifo_get(voodoo);
uint32_t addr;
uint32_t mask;
int smode;
int num;
int num_verticies;
int v_num;
#if 0
voodoo_fifo_log(" CMDFIFO header %08x at %08x\n", header, voodoo->cmdfifo_rp);
#endif
voodoo->cmd_status &= ~7;
voodoo->cmd_status |= (header & 7);
voodoo->cmd_status |= (1 << 11);
switch (header & 7) {
case 0:
#if 0
voodoo_fifo_log("CMDFIFO0\n");
#endif
voodoo->cmd_status = (voodoo->cmd_status & 0xffff8fff) | (((header >> 3) & 7) << 12);
switch ((header >> 3) & 7) {
case 0: /*NOP*/
break;
case 1: /*JSR*/
#if 0
voodoo_fifo_log("JSR %08x\n", (header >> 4) & 0xfffffc);
#endif
voodoo->cmdfifo_ret_addr = voodoo->cmdfifo_rp;
voodoo->cmdfifo_rp = (header >> 4) & 0xfffffc;
voodoo->cmdfifo_in_sub = 1;
break;
case 2: /*RET*/
voodoo->cmdfifo_rp = voodoo->cmdfifo_ret_addr;
voodoo->cmdfifo_in_sub = 0;
break;
case 3: /*JMP local frame buffer*/
voodoo->cmdfifo_rp = (header >> 4) & 0xfffffc;
#if 0
voodoo_fifo_log("JMP to %08x %04x\n", voodoo->cmdfifo_rp, header);
#endif
break;
default:
fatal("Bad CMDFIFO0 %08x\n", header);
}
voodoo->cmd_status = (voodoo->cmd_status & ~(1 << 27)) | (voodoo->cmdfifo_in_sub << 27);
break;
case 1:
num = header >> 16;
addr = (header & 0x7ff8) >> 1;
#if 0
voodoo_fifo_log("CMDFIFO1 addr=%08x\n",addr);
#endif
while (num--) {
uint32_t val = cmdfifo_get(voodoo);
if ((addr & (1 << 13)) && voodoo->type >= VOODOO_BANSHEE) {
#if 0
if (voodoo->type != VOODOO_BANSHEE)
fatal("CMDFIFO1: Not Banshee\n");
#endif
#if 0
voodoo_fifo_log("CMDFIFO1: write %08x %08x\n", addr, val);
#endif
voodoo_2d_reg_writel(voodoo, addr, val);
} else {
if ((addr & 0x3ff) == SST_triangleCMD || (addr & 0x3ff) == SST_ftriangleCMD || (addr & 0x3ff) == SST_fastfillCMD || (addr & 0x3ff) == SST_nopCMD)
voodoo->cmd_written_fifo++;
if (voodoo->type >= VOODOO_BANSHEE && (addr & 0x3ff) == SST_swapbufferCMD)
voodoo->cmd_written_fifo++;
voodoo_reg_writel(addr, val, voodoo);
}
if (header & (1 << 15))
addr += 4;
}
break;
case 2:
if (voodoo->type < VOODOO_2)
fatal("CMDFIFO2: Not Voodoo 2\n");
mask = (header >> 3);
addr = 8;
while (mask) {
if (mask & 1) {
uint32_t val = cmdfifo_get(voodoo);
voodoo_2d_reg_writel(voodoo, addr, val);
}
addr += 4;
mask >>= 1;
}
break;
case 3:
num = (header >> 29) & 7;
mask = header; //(header >> 10) & 0xff;
smode = (header >> 22) & 0xf;
voodoo_reg_writel(SST_sSetupMode, ((header >> 10) & 0xff) | (smode << 16), voodoo);
num_verticies = (header >> 6) & 0xf;
v_num = 0;
if (((header >> 3) & 7) == 2)
v_num = 1;
#if 0
voodoo_fifo_log("CMDFIFO3: num=%i verts=%i mask=%02x\n", num, num_verticies, (header >> 10) & 0xff);
voodoo_fifo_log("CMDFIFO3 %02x %i\n", (header >> 10), (header >> 3) & 7);
#endif
while (num_verticies--) {
voodoo->verts[3].sVx = cmdfifo_get_f(voodoo);
voodoo->verts[3].sVy = cmdfifo_get_f(voodoo);
if (mask & CMDFIFO3_PC_MASK_RGB) {
if (header & CMDFIFO3_PC) {
uint32_t val = cmdfifo_get(voodoo);
voodoo->verts[3].sBlue = (float) (val & 0xff);
voodoo->verts[3].sGreen = (float) ((val >> 8) & 0xff);
voodoo->verts[3].sRed = (float) ((val >> 16) & 0xff);
voodoo->verts[3].sAlpha = (float) ((val >> 24) & 0xff);
} else {
voodoo->verts[3].sRed = cmdfifo_get_f(voodoo);
voodoo->verts[3].sGreen = cmdfifo_get_f(voodoo);
voodoo->verts[3].sBlue = cmdfifo_get_f(voodoo);
}
}
if ((mask & CMDFIFO3_PC_MASK_ALPHA) && !(header & CMDFIFO3_PC))
voodoo->verts[3].sAlpha = cmdfifo_get_f(voodoo);
if (mask & CMDFIFO3_PC_MASK_Z)
voodoo->verts[3].sVz = cmdfifo_get_f(voodoo);
if (mask & CMDFIFO3_PC_MASK_Wb)
voodoo->verts[3].sWb = cmdfifo_get_f(voodoo);
if (mask & CMDFIFO3_PC_MASK_W0)
voodoo->verts[3].sW0 = cmdfifo_get_f(voodoo);
if (mask & CMDFIFO3_PC_MASK_S0_T0) {
voodoo->verts[3].sS0 = cmdfifo_get_f(voodoo);
voodoo->verts[3].sT0 = cmdfifo_get_f(voodoo);
}
if (mask & CMDFIFO3_PC_MASK_W1)
voodoo->verts[3].sW1 = cmdfifo_get_f(voodoo);
if (mask & CMDFIFO3_PC_MASK_S1_T1) {
voodoo->verts[3].sS1 = cmdfifo_get_f(voodoo);
voodoo->verts[3].sT1 = cmdfifo_get_f(voodoo);
}
if (v_num)
voodoo_reg_writel(SST_sDrawTriCMD, 0, voodoo);
else
voodoo_reg_writel(SST_sBeginTriCMD, 0, voodoo);
v_num++;
if (v_num == 3 && ((header >> 3) & 7) == 0)
v_num = 0;
}
while (num--)
cmdfifo_get(voodoo);
break;
case 4:
num = (header >> 29) & 7;
mask = (header >> 15) & 0x3fff;
addr = (header & 0x7ff8) >> 1;
#if 0
voodoo_fifo_log("CMDFIFO4 addr=%08x\n",addr);
#endif
while (mask) {
if (mask & 1) {
uint32_t val = cmdfifo_get(voodoo);
if ((addr & (1 << 13)) && voodoo->type >= VOODOO_BANSHEE) {
if (voodoo->type < VOODOO_BANSHEE)
fatal("CMDFIFO1: Not Banshee\n");
#if 0
voodoo_fifo_log("CMDFIFO1: write %08x %08x\n", addr, val);
#endif
voodoo_2d_reg_writel(voodoo, addr, val);
} else {
if ((addr & 0x3ff) == SST_triangleCMD || (addr & 0x3ff) == SST_ftriangleCMD || (addr & 0x3ff) == SST_fastfillCMD || (addr & 0x3ff) == SST_nopCMD)
voodoo->cmd_written_fifo++;
if (voodoo->type >= VOODOO_BANSHEE && (addr & 0x3ff) == SST_swapbufferCMD)
voodoo->cmd_written_fifo++;
voodoo_reg_writel(addr, val, voodoo);
}
}
addr += 4;
mask >>= 1;
}
while (num--)
cmdfifo_get(voodoo);
break;
case 5:
#if 0
if (header & 0x3fc00000)
fatal("CMDFIFO packet 5 has byte disables set %08x\n", header);
#endif
num = (header >> 3) & 0x7ffff;
addr = cmdfifo_get(voodoo) & 0xffffff;
if (!num)
num = 1;
#if 0
voodoo_fifo_log("CMDFIFO5 addr=%08x num=%i\n", addr, num);
#endif
switch (header >> 30) {
case 0: /*Linear framebuffer (Banshee)*/
case 1: /*Planar YUV*/
if (voodoo->texture_present[0][(addr & voodoo->texture_mask) >> TEX_DIRTY_SHIFT]) {
#if 0
voodoo_fifo_log("texture_present at %08x %i\n", addr, (addr & voodoo->texture_mask) >> TEX_DIRTY_SHIFT);
#endif
flush_texture_cache(voodoo, addr & voodoo->texture_mask, 0);
}
if (voodoo->texture_present[1][(addr & voodoo->texture_mask) >> TEX_DIRTY_SHIFT]) {
#if 0
voodoo_fifo_log("texture_present at %08x %i\n", addr, (addr & voodoo->texture_mask) >> TEX_DIRTY_SHIFT);
#endif
flush_texture_cache(voodoo, addr & voodoo->texture_mask, 1);
}
while (num--) {
uint32_t val = cmdfifo_get(voodoo);
if (addr <= voodoo->fb_mask)
*(uint32_t *) &voodoo->fb_mem[addr] = val;
addr += 4;
}
break;
case 2: /*Framebuffer*/
while (num--) {
uint32_t val = cmdfifo_get(voodoo);
voodoo_fb_writel(addr, val, voodoo);
addr += 4;
}
break;
case 3: /*Texture*/
while (num--) {
uint32_t val = cmdfifo_get(voodoo);
voodoo_tex_writel(addr, val, voodoo);
addr += 4;
}
break;
default:
fatal("CMDFIFO packet 5 bad space %08x %08x\n", header, voodoo->cmdfifo_rp);
}
break;
default:
fatal("Bad CMDFIFO packet %08x %08x\n", header, voodoo->cmdfifo_rp);
}
end_time = plat_timer_read();
voodoo->time += end_time - start_time;
}
voodoo->voodoo_busy = 0;
}
}
``` | /content/code_sandbox/src/video/vid_voodoo_fifo.c | c | 2016-06-25T22:29:10 | 2024-08-16T19:09:21 | 86Box | 86Box/86Box | 2,616 | 5,036 |
```c
/*
* 86Box A hypervisor and IBM PC system emulator that specializes in
* running old operating systems and software designed for IBM
* PC systems and compatibles from 1981 through fairly recent
* system designs based on the PCI bus.
*
* This file is part of the 86Box distribution.
*
* Emulation of the EEPROM on select ATI cards.
*
*
*
* Authors: Sarah Walker, <path_to_url
* Miran Grca, <mgrca8@gmail.com>
*
*/
#include <stdio.h>
#include <stdint.h>
#include <string.h>
#include <wchar.h>
#include <86box/86box.h>
#include <86box/device.h>
#include <86box/mem.h>
#include <86box/timer.h>
#include <86box/nvr.h>
#include <86box/vid_ati_eeprom.h>
#include <86box/plat_fallthrough.h>
void
ati_eeprom_load(ati_eeprom_t *eeprom, char *fn, int type)
{
FILE *fp;
int size;
eeprom->type = type;
strncpy(eeprom->fn, fn, sizeof(eeprom->fn) - 1);
fp = nvr_fopen(eeprom->fn, "rb");
size = eeprom->type ? 512 : 128;
if (!fp) {
memset(eeprom->data, 0xff, size);
return;
}
if (fread(eeprom->data, 1, size, fp) != size)
memset(eeprom->data, 0, size);
fclose(fp);
}
void
ati_eeprom_load_mach8(ati_eeprom_t *eeprom, char *fn)
{
FILE *fp;
int size;
eeprom->type = 0;
strncpy(eeprom->fn, fn, sizeof(eeprom->fn) - 1);
fp = nvr_fopen(eeprom->fn, "rb");
size = 128;
if (!fp) { /*The ATI Graphics Ultra bios expects an immediate write to nvram if none is present at boot time otherwise
it would hang the machine.*/
memset(eeprom->data, 0, size);
fp = nvr_fopen(eeprom->fn, "wb");
fwrite(eeprom->data, 1, size, fp);
}
if (fread(eeprom->data, 1, size, fp) != size)
memset(eeprom->data, 0, size);
fclose(fp);
}
void
ati_eeprom_save(ati_eeprom_t *eeprom)
{
FILE *fp = nvr_fopen(eeprom->fn, "wb");
if (!fp)
return;
fwrite(eeprom->data, 1, eeprom->type ? 512 : 128, fp);
fclose(fp);
}
void
ati_eeprom_write(ati_eeprom_t *eeprom, int ena, int clk, int dat)
{
if (!ena) {
eeprom->out = 1;
}
if (clk && !eeprom->oldclk) {
if (ena && !eeprom->oldena) {
eeprom->state = EEPROM_WAIT;
eeprom->opcode = 0;
eeprom->count = 3;
eeprom->out = 1;
} else if (ena) {
switch (eeprom->state) {
case EEPROM_WAIT:
if (!dat)
break;
eeprom->state = EEPROM_OPCODE;
fallthrough;
case EEPROM_OPCODE:
eeprom->opcode = (eeprom->opcode << 1) | (dat ? 1 : 0);
eeprom->count--;
if (!eeprom->count) {
switch (eeprom->opcode) {
case EEPROM_OP_WRITE:
eeprom->count = eeprom->type ? 24 : 22;
eeprom->state = EEPROM_INPUT;
eeprom->dat = 0;
break;
case EEPROM_OP_READ:
eeprom->count = eeprom->type ? 8 : 6;
eeprom->state = EEPROM_INPUT;
eeprom->dat = 0;
break;
case EEPROM_OP_EW:
eeprom->count = 2;
eeprom->state = EEPROM_INPUT;
eeprom->dat = 0;
break;
case EEPROM_OP_ERASE:
eeprom->count = eeprom->type ? 8 : 6;
eeprom->state = EEPROM_INPUT;
eeprom->dat = 0;
break;
default:
break;
}
}
break;
case EEPROM_INPUT:
eeprom->dat = (eeprom->dat << 1) | (dat ? 1 : 0);
eeprom->count--;
if (!eeprom->count) {
switch (eeprom->opcode) {
case EEPROM_OP_WRITE:
if (!eeprom->wp) {
eeprom->data[(eeprom->dat >> 16) & (eeprom->type ? 255 : 63)] = eeprom->dat & 0xffff;
ati_eeprom_save(eeprom);
}
eeprom->state = EEPROM_IDLE;
eeprom->out = 1;
break;
case EEPROM_OP_READ:
eeprom->count = 17;
eeprom->state = EEPROM_OUTPUT;
eeprom->dat = eeprom->data[eeprom->dat];
break;
case EEPROM_OP_EW:
switch (eeprom->dat) {
case EEPROM_OP_EWDS:
eeprom->wp = 1;
break;
case EEPROM_OP_WRAL:
eeprom->opcode = EEPROM_OP_WRALMAIN;
eeprom->count = 20;
break;
case EEPROM_OP_ERAL:
if (!eeprom->wp) {
memset(eeprom->data, 0xff, 128);
ati_eeprom_save(eeprom);
}
break;
case EEPROM_OP_EWEN:
eeprom->wp = 0;
break;
default:
break;
}
eeprom->state = EEPROM_IDLE;
eeprom->out = 1;
break;
case EEPROM_OP_ERASE:
if (!eeprom->wp) {
eeprom->data[eeprom->dat] = 0xffff;
ati_eeprom_save(eeprom);
}
eeprom->state = EEPROM_IDLE;
eeprom->out = 1;
break;
case EEPROM_OP_WRALMAIN:
if (!eeprom->wp) {
for (uint16_t c = 0; c < 256; c++)
eeprom->data[c] = eeprom->dat;
ati_eeprom_save(eeprom);
}
eeprom->state = EEPROM_IDLE;
eeprom->out = 1;
break;
default:
break;
}
}
break;
default:
break;
}
}
eeprom->oldena = ena;
} else if (!clk && eeprom->oldclk) {
if (ena) {
switch (eeprom->state) {
case EEPROM_OUTPUT:
eeprom->out = (eeprom->dat & 0x10000) ? 1 : 0;
eeprom->dat <<= 1;
eeprom->count--;
if (!eeprom->count) {
eeprom->state = EEPROM_IDLE;
}
break;
default:
break;
}
}
}
eeprom->oldclk = clk;
}
int
ati_eeprom_read(ati_eeprom_t *eeprom)
{
return eeprom->out;
}
``` | /content/code_sandbox/src/video/vid_ati_eeprom.c | c | 2016-06-25T22:29:10 | 2024-08-16T19:09:21 | 86Box | 86Box/86Box | 2,616 | 1,671 |
```c
/*
* 86Box A hypervisor and IBM PC system emulator that specializes in
* running old operating systems and software designed for IBM
* PC systems and compatibles from 1981 through fairly recent
* system designs based on the PCI bus.
*
* This file is part of the 86Box distribution.
*
* Sigma Color 400 emulation.
*
*
*
* Authors: John Elliott,
*
*/
#include <stdio.h>
#include <stdint.h>
#include <string.h>
#include <stdlib.h>
#include <wchar.h>
#include <86box/86box.h>
#include "cpu.h"
#include <86box/io.h>
#include <86box/timer.h>
#include <86box/pit.h>
#include <86box/mem.h>
#include <86box/nmi.h>
#include <86box/rom.h>
#include <86box/device.h>
#include <86box/video.h>
#include <86box/plat_unused.h>
#define ROM_SIGMA_FONT "roms/video/sigma/sigma400_font.rom"
#define ROM_SIGMA_BIOS "roms/video/sigma/sigma400_bios.rom"
/* The Sigma Designs Color 400 is a video card from 1985, presumably intended
* as an EGA competitor.
*
* The hardware seems to have gone through various iterations; I've seen
* pictures of full-length and half-length versions.
* TH99 describes the jumpers / switches:
* <path_to_url
*
* The card is CGA-compatible at BIOS level, but to improve compatibility
* attempts to write to the CGA I/O ports at 0x3D0-0x3DF trigger an NMI. The
* card's BIOS handles the NMI and translates the CGA writes into commands
* to its own hardware at 0x2D0-0x2DF. (DIP switches on the card allow the
* base address to be changed, but since the BIOS dump I have doesn't support
* this I haven't emulated it. Likewise the BIOS ROM address can be changed,
* but I'm going with the default of 0xC0000).
*
* The BIOS still functions if the NMI system isn't operational. There
* doesn't seem to be a jumper or DIP switch to lock it out, but at startup
* the BIOS tests for its presence and configures itself to work or not
* as required. I've therefore added a configuration option to handle this.
*
* The card's real CRTC at 0x2D0/0x2D1 appears to be a 6845. One oddity is
* that all its horizontal counts are halved compared to what a real CGA
* uses; 40-column modes have a width of 20, and 80-column modes have a
* width of 40. This means that the CRTC cursor position (registers 14/15) can
* only address even-numbered columns, so the top bit of the control
* register at 0x2D9 is used to adjust the position.
*
* Apart from the CRTC, registers are:
*
* 0x2D8: Mode register. Values written by the card BIOS are:
* Text 40x25: 0xA8
* Text 80x25: 0xB9
* Text 80x30: 0xB9
* Text 80x50: 0x79
* Graphics 320x200: 0x0F
* Graphics 640x200: 0x1F
* Graphics 640x400: 0x7F
*
* I have assumed this is a bitmap with the following meaning: */
#define MODE_80COLS 0x01 /* For text modes, 80 columns across */
#define MODE_GRAPHICS 0x02 /* Graphics mode */
#define MODE_NOBLINK 0x04 /* Disable blink? */
#define MODE_ENABLE 0x08 /* Enable display */
#define MODE_HRGFX 0x10 /* For graphics modes, 640 pixels across */
#define MODE_640x400 0x40 /* 400-line graphics mode */
#define MODE_FONT16 0x80 /* Use 16-pixel high font */
/*
* 0x2D9: Control register, with the following bits: */
#define CTL_CURSOR 0x80 /* Low bit of cursor position */
#define CTL_NMI 0x20 /* Writes to 0x3D0-0x3DF trigger NMI */
#define CTL_CLEAR_LPEN 0x08 /* Strobe 0 to clear lightpen latch */
#define CTL_SET_LPEN 0x04 /* Strobe 0 to set lightpen latch */
#define CTL_PALETTE 0x01 /* 0x2DE writes to palette (1) or plane (0) */
/*
* The card BIOS seems to support two variants of the hardware: One where
* bits 2 and 3 are normally 1 and are set to 0 to set/clear the latch, and
* one where they are normally 0 and are set to 1. Behaviour is selected by
* whether the byte at C000:17FFh is greater than 2Fh.
*
* 0x2DA: Status register.
*/
#define STATUS_CURSOR 0x80 /* Last value written to bit 7 of 0x2D9 */
#define STATUS_NMI 0x20 /* Last value written to bit 5 of 0x2D9 */
#define STATUS_RETR_V 0x10 /* Vertical retrace */
#define STATUS_LPEN_T 0x04 /* Lightpen switch is off */
#define STATUS_LPEN_A 0x02 /* Edge from lightpen has set trigger */
#define STATUS_RETR_H 0x01 /* Horizontal retrace */
/*
* 0x2DB: On read: Byte written to the card that triggered NMI
* 0x2DB: On write: Resets the 'card raised NMI' flag.
* 0x2DC: On read: Bit 7 set if the card raised NMI. If so, bits 0-3
* give the low 4 bits of the I/O port address.
* 0x2DC: On write: Resets the NMI.
* 0x2DD: Memory paging. The memory from 0xC1800 to 0xC1FFF can be either:
*
* > ROM: A 128 character 8x16 font for use in graphics modes
* > RAM: Use by the video BIOS to hold its settings.
*
* Reading port 2DD switches to ROM. Bit 7 of the value read gives the
* previous paging state: bit 7 set if ROM was paged, clear if RAM was
* paged.
*
* Writing port 2DD switches to RAM.
*
* 0x2DE: Meaning depends on bottom bit of value written to port 0x2D9.
* Bit 0 set: Write to palette. High 4 bits of value = register,
* low 4 bits = RGBI values (active low)
* Bit 0 clear: Write to plane select. Low 2 bits of value select
* plane 0-3
*/
typedef struct sigma_t {
mem_mapping_t mapping, bios_ram;
rom_t bios_rom;
uint8_t crtc[32]; /* CRTC: Real values */
uint8_t lastport; /* Last I/O port written */
uint8_t lastwrite; /* Value written to that port */
uint8_t sigma_ctl; /* Controls register:
* Bit 7 is low bit of cursor position
* Bit 5 set if writes to CGA ports trigger NMI
* Bit 3 clears lightpen latch
* Bit 2 sets lightpen latch
* Bit 1 controls meaning of port 2DE
*/
uint8_t enable_nmi; /* Enable the NMI mechanism for CGA emulation?*/
uint8_t rom_paged; /* Is ROM paged in at 0xC1800? */
uint8_t crtc_value; /* Value to return from a CRTC register read */
uint8_t sigmastat, /* Status register [0x2DA] */
fake_stat; /* see sigma_in() for comment */
uint8_t sigmamode; /* Mode control register [0x2D8] */
uint16_t ma, maback;
int crtcreg; /* CRTC: Real selected register */
int linepos, displine;
int sc, vc;
int cgadispon;
int con, coff, cursoron, cgablink;
int vsynctime, vadj;
int oddeven;
uint64_t dispontime, dispofftime;
int firstline, lastline;
int drawcursor;
pc_timer_t timer;
uint8_t *vram;
uint8_t bram[2048];
uint8_t palette[16];
int plane;
int revision;
int fullchange;
} sigma_t;
#define COMPOSITE_OLD 0
#define COMPOSITE_NEW 1
static uint8_t crtcmask[32] = {
0xff, 0xff, 0xff, 0xff, 0x7f, 0x1f, 0x7f, 0x7f, 0xf3, 0x1f, 0x7f, 0x1f, 0x3f, 0xff, 0x3f, 0xff,
0xff, 0xff, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
};
static video_timings_t timing_sigma = { .type = VIDEO_ISA, .write_b = 8, .write_w = 16, .write_l = 32, .read_b = 8, .read_w = 16, .read_l = 32 };
static void sigma_recalctimings(sigma_t *cga);
static void
sigma_out(uint16_t addr, uint8_t val, void *priv)
{
sigma_t *sigma = (sigma_t *) priv;
uint8_t old;
if (addr >= 0x3D0 && addr < 0x3E0) {
sigma->lastport = addr & 0x0F;
sigma->lastwrite = val;
/* If set to NMI on video I/O... */
if (sigma->enable_nmi && (sigma->sigma_ctl & CTL_NMI)) {
sigma->lastport |= 0x80; /* Card raised NMI */
nmi_raise();
}
/* For CRTC emulation, the card BIOS sets the value to be
* read from port 0x3D1 like this */
if (addr == 0x3D1)
sigma->crtc_value = val;
} else
switch (addr) {
case 0x2D0:
case 0x2D2:
case 0x2D4:
case 0x2D6:
sigma->crtcreg = val & 31;
return;
case 0x2D1:
case 0x2D3:
case 0x2D5:
case 0x2D7:
old = sigma->crtc[sigma->crtcreg];
sigma->crtc[sigma->crtcreg] = val & crtcmask[sigma->crtcreg];
if (old != val) {
if (sigma->crtcreg < 0xe || sigma->crtcreg > 0x10) {
sigma->fullchange = changeframecount;
sigma_recalctimings(sigma);
}
}
return;
case 0x2D8:
sigma->sigmamode = val;
return;
case 0x2D9:
sigma->sigma_ctl = val;
return;
case 0x2DB:
sigma->lastport &= 0x7F;
return;
case 0x2DC: /* Reset NMI */
nmi = 0;
sigma->lastport &= 0x7F;
return;
case 0x2DD: /* Page in RAM at 0xC1800 */
if (sigma->rom_paged != 0)
flushmmucache_nopc();
sigma->rom_paged = 0x00;
return;
case 0x2DE:
if (sigma->sigma_ctl & CTL_PALETTE)
sigma->palette[val >> 4] = (val & 0x0F) ^ 0x0F;
else
sigma->plane = val & 3;
return;
default:
break;
}
}
static uint8_t
sigma_in(uint16_t addr, void *priv)
{
uint8_t result = 0xFF;
sigma_t *sigma = (sigma_t *) priv;
switch (addr) {
case 0x2D0:
case 0x2D2:
case 0x2D4:
case 0x2D6:
result = sigma->crtcreg;
break;
case 0x2D1:
case 0x2D3:
case 0x2D5:
case 0x2D7:
result = sigma->crtc[sigma->crtcreg & 0x1F];
break;
case 0x2DA:
result = (sigma->sigma_ctl & 0xE0) | (sigma->sigmastat & 0x1F);
break;
case 0x2DB:
result = sigma->lastwrite; /* Value that triggered NMI */
break;
case 0x2DC:
result = sigma->lastport; /* Port that triggered NMI */
break;
case 0x2DD: /* Page in ROM at 0xC1800 */
result = (sigma->rom_paged ? 0x80 : 0);
if (sigma->rom_paged != 0x80)
flushmmucache_nopc();
sigma->rom_paged = 0x80;
break;
case 0x3D1:
case 0x3D3:
case 0x3D5:
case 0x3D7:
result = sigma->crtc_value;
break;
/* For CGA compatibility we have to return something palatable on this port.
On a real card this functionality can be turned on or off with SW1/6 */
case 0x3DA:
if (sigma->sigmamode & MODE_ENABLE) {
result = sigma->sigmastat & 0x07;
if (sigma->sigmastat & STATUS_RETR_V)
result |= 0x08;
} else {
/*
* The card is not running yet, and someone
* (probably the system BIOS) is trying to
* read our status in CGA mode.
*
* One of the systems that do this, is the
* DTK XT (PIM-10TB-Z board) with ERSO 2.42
* BIOS. If this test fails (i.e. it doesnt
* see valid HS and VS bits alternate) it
* will generate lots of annoying beeps..
*
* So, the trick here is to just send it
* some alternating bits, making it think
* the CGA circuitry is operational.
*/
sigma->fake_stat ^= (0x08 | 0x01);
result = sigma->fake_stat;
}
break;
default:
break;
}
return result;
}
static void
sigma_write(uint32_t addr, uint8_t val, void *priv)
{
sigma_t *sigma = (sigma_t *) priv;
sigma->vram[sigma->plane * 0x8000 + (addr & 0x7fff)] = val;
cycles -= 4;
}
static uint8_t
sigma_read(uint32_t addr, void *priv)
{
const sigma_t *sigma = (sigma_t *) priv;
cycles -= 4;
return sigma->vram[sigma->plane * 0x8000 + (addr & 0x7fff)];
}
static void
sigma_bwrite(uint32_t addr, uint8_t val, void *priv)
{
sigma_t *sigma = (sigma_t *) priv;
addr &= 0x3FFF;
if ((addr < 0x1800) || sigma->rom_paged || (addr >= 0x2000))
;
else
sigma->bram[addr & 0x7FF] = val;
}
static uint8_t
sigma_bread(uint32_t addr, void *priv)
{
const sigma_t *sigma = (sigma_t *) priv;
uint8_t result;
addr &= 0x3FFF;
if (addr >= 0x2000)
return 0xFF;
if (addr < 0x1800 || sigma->rom_paged)
result = sigma->bios_rom.rom[addr & 0x1FFF];
else
result = sigma->bram[addr & 0x7FF];
return result;
}
static void
sigma_recalctimings(sigma_t *sigma)
{
double disptime;
double _dispontime;
double _dispofftime;
if (sigma->sigmamode & MODE_80COLS) {
disptime = (sigma->crtc[0] + 1) << 1;
_dispontime = (sigma->crtc[1]) << 1;
} else {
disptime = (sigma->crtc[0] + 1) << 2;
_dispontime = sigma->crtc[1] << 2;
}
_dispofftime = disptime - _dispontime;
_dispontime *= CGACONST;
_dispofftime *= CGACONST;
sigma->dispontime = (uint64_t) (_dispontime);
sigma->dispofftime = (uint64_t) (_dispofftime);
}
/* Render a line in 80-column text mode */
static void
sigma_text80(sigma_t *sigma)
{
uint8_t chr;
uint8_t attr;
uint16_t ca = (sigma->crtc[15] | (sigma->crtc[14] << 8));
uint16_t ma = ((sigma->ma & 0x3FFF) << 1);
int drawcursor;
uint32_t cols[4];
const uint8_t *vram = sigma->vram + (ma << 1);
ca = ca << 1;
if (sigma->sigma_ctl & CTL_CURSOR)
++ca;
ca &= 0x3fff;
/* The Sigma 400 seems to use screen widths stated in words
(40 for 80-column, 20 for 40-column) */
for (uint32_t x = 0; x < (sigma->crtc[1] << 1); x++) {
chr = vram[x << 1];
attr = vram[(x << 1) + 1];
drawcursor = ((ma == ca) && sigma->con && sigma->cursoron);
if (!(sigma->sigmamode & MODE_NOBLINK)) {
cols[1] = (attr & 15) | 16;
cols[0] = ((attr >> 4) & 7) | 16;
if ((sigma->cgablink & 8) && (attr & 0x80) && !sigma->drawcursor)
cols[1] = cols[0];
} else { /* No blink */
cols[1] = (attr & 15) | 16;
cols[0] = (attr >> 4) | 16;
}
if (drawcursor) {
for (uint8_t c = 0; c < 8; c++) {
if (sigma->sigmamode & MODE_FONT16)
buffer32->line[sigma->displine][(x << 3) + c + 8] = cols[(fontdatm[chr][sigma->sc & 15] & (1 << (c ^ 7))) ? 1 : 0] ^ 0xf;
else
buffer32->line[sigma->displine][(x << 3) + c + 8] = cols[(fontdat[chr][sigma->sc & 7] & (1 << (c ^ 7))) ? 1 : 0] ^ 0xf;
}
} else {
for (uint8_t c = 0; c < 8; c++) {
if (sigma->sigmamode & MODE_FONT16)
buffer32->line[sigma->displine][(x << 3) + c + 8] = cols[(fontdatm[chr][sigma->sc & 15] & (1 << (c ^ 7))) ? 1 : 0];
else
buffer32->line[sigma->displine][(x << 3) + c + 8] = cols[(fontdat[chr][sigma->sc & 7] & (1 << (c ^ 7))) ? 1 : 0];
}
}
++ma;
}
sigma->ma += sigma->crtc[1];
}
/* Render a line in 40-column text mode */
static void
sigma_text40(sigma_t *sigma)
{
uint8_t chr;
uint8_t attr;
uint16_t ca = (sigma->crtc[15] | (sigma->crtc[14] << 8));
uint16_t ma = ((sigma->ma & 0x3FFF) << 1);
int drawcursor;
uint32_t cols[4];
const uint8_t *vram = sigma->vram + ((ma << 1) & 0x3FFF);
ca = ca << 1;
if (sigma->sigma_ctl & CTL_CURSOR)
++ca;
ca &= 0x3fff;
/* The Sigma 400 seems to use screen widths stated in words
(40 for 80-column, 20 for 40-column) */
for (uint32_t x = 0; x < (sigma->crtc[1] << 1); x++) {
chr = vram[x << 1];
attr = vram[(x << 1) + 1];
drawcursor = ((ma == ca) && sigma->con && sigma->cursoron);
if (!(sigma->sigmamode & MODE_NOBLINK)) {
cols[1] = (attr & 15) | 16;
cols[0] = ((attr >> 4) & 7) | 16;
if ((sigma->cgablink & 8) && (attr & 0x80) && !sigma->drawcursor)
cols[1] = cols[0];
} else { /* No blink */
cols[1] = (attr & 15) | 16;
cols[0] = (attr >> 4) | 16;
}
if (drawcursor) {
for (uint8_t c = 0; c < 8; c++) {
buffer32->line[sigma->displine][(x << 4) + 2 * c + 8] = buffer32->line[sigma->displine][(x << 4) + 2 * c + 9] = cols[(fontdatm[chr][sigma->sc & 15] & (1 << (c ^ 7))) ? 1 : 0] ^ 0xf;
}
} else {
for (uint8_t c = 0; c < 8; c++) {
buffer32->line[sigma->displine][(x << 4) + 2 * c + 8] = buffer32->line[sigma->displine][(x << 4) + 2 * c + 9] = cols[(fontdatm[chr][sigma->sc & 15] & (1 << (c ^ 7))) ? 1 : 0];
}
}
ma++;
}
sigma->ma += sigma->crtc[1];
}
/* Draw a line in the 640x400 graphics mode */
static void
sigma_gfx400(sigma_t *sigma)
{
const uint8_t *vram = &sigma->vram[((sigma->ma << 1) & 0x1FFF) + (sigma->sc & 3) * 0x2000];
uint8_t plane[4];
uint8_t col;
for (uint32_t x = 0; x < (sigma->crtc[1] << 1); x++) {
plane[0] = vram[x];
plane[1] = vram[0x8000 + x];
plane[2] = vram[0x10000 + x];
plane[3] = vram[0x18000 + x];
for (uint8_t c = 0, mask = 0x80; c < 8; c++, mask >>= 1) {
col = ((plane[3] & mask) ? 8 : 0) | ((plane[2] & mask) ? 4 : 0) | ((plane[1] & mask) ? 2 : 0) | ((plane[0] & mask) ? 1 : 0);
col |= 16;
buffer32->line[sigma->displine][(x << 3) + c + 8] = col;
}
if (x & 1)
++sigma->ma;
}
}
/* Draw a line in the 640x200 graphics mode.
* This is actually a 640x200x16 mode; on startup, the BIOS selects plane 2,
* blanks the other planes, and sets palette ink 4 to white. Pixels plotted
* in plane 2 come out in white, others black; but by programming the palette
* and plane registers manually you can get the full resolution. */
static void
sigma_gfx200(sigma_t *sigma)
{
const uint8_t *vram = &sigma->vram[((sigma->ma << 1) & 0x1FFF) + (sigma->sc & 2) * 0x1000];
uint8_t plane[4];
uint8_t col;
for (uint32_t x = 0; x < (sigma->crtc[1] << 1); x++) {
plane[0] = vram[x];
plane[1] = vram[0x8000 + x];
plane[2] = vram[0x10000 + x];
plane[3] = vram[0x18000 + x];
for (uint8_t c = 0, mask = 0x80; c < 8; c++, mask >>= 1) {
col = ((plane[3] & mask) ? 8 : 0) | ((plane[2] & mask) ? 4 : 0) | ((plane[1] & mask) ? 2 : 0) | ((plane[0] & mask) ? 1 : 0);
col |= 16;
buffer32->line[sigma->displine][(x << 3) + c + 8] = col;
}
if (x & 1)
++sigma->ma;
}
}
/* Draw a line in the 320x200 graphics mode */
static void
sigma_gfx4col(sigma_t *sigma)
{
const uint8_t *vram = &sigma->vram[((sigma->ma << 1) & 0x1FFF) + (sigma->sc & 2) * 0x1000];
uint8_t plane[4];
uint8_t mask;
uint8_t col;
for (uint32_t x = 0; x < (sigma->crtc[1] << 1); x++) {
plane[0] = vram[x];
plane[1] = vram[0x8000 + x];
plane[2] = vram[0x10000 + x];
plane[3] = vram[0x18000 + x];
mask = 0x80;
for (uint8_t c = 0; c < 4; c++) {
col = ((plane[3] & mask) ? 2 : 0) | ((plane[2] & mask) ? 1 : 0);
mask = mask >> 1;
col |= ((plane[3] & mask) ? 8 : 0) | ((plane[2] & mask) ? 4 : 0);
col |= 16;
mask = mask >> 1;
buffer32->line[sigma->displine][(x << 3) + (c << 1) + 8] = buffer32->line[sigma->displine][(x << 3) + (c << 1) + 9] = col;
}
if (x & 1)
++sigma->ma;
}
}
static void
sigma_poll(void *priv)
{
sigma_t *sigma = (sigma_t *) priv;
int x;
int c;
int oldvc;
uint32_t cols[4];
int oldsc;
if (!sigma->linepos) {
timer_advance_u64(&sigma->timer, sigma->dispofftime);
sigma->sigmastat |= STATUS_RETR_H;
sigma->linepos = 1;
oldsc = sigma->sc;
if ((sigma->crtc[8] & 3) == 3)
sigma->sc = ((sigma->sc << 1) + sigma->oddeven) & 7;
if (sigma->cgadispon) {
if (sigma->displine < sigma->firstline) {
sigma->firstline = sigma->displine;
video_wait_for_buffer();
}
sigma->lastline = sigma->displine;
cols[0] = 16;
/* Left overscan */
for (c = 0; c < 8; c++) {
buffer32->line[sigma->displine][c] = cols[0];
if (sigma->sigmamode & MODE_80COLS)
buffer32->line[sigma->displine][c + (sigma->crtc[1] << 4) + 8] = cols[0];
else
buffer32->line[sigma->displine][c + (sigma->crtc[1] << 5) + 8] = cols[0];
}
if (sigma->sigmamode & MODE_GRAPHICS) {
if (sigma->sigmamode & MODE_640x400)
sigma_gfx400(sigma);
else if (sigma->sigmamode & MODE_HRGFX)
sigma_gfx200(sigma);
else
sigma_gfx4col(sigma);
} else { /* Text modes */
if (sigma->sigmamode & MODE_80COLS)
sigma_text80(sigma);
else
sigma_text40(sigma);
}
} else {
cols[0] = 16;
if (sigma->sigmamode & MODE_80COLS)
hline(buffer32, 0, sigma->displine, (sigma->crtc[1] << 4) + 16, cols[0]);
else
hline(buffer32, 0, sigma->displine, (sigma->crtc[1] << 5) + 16, cols[0]);
}
if (sigma->sigmamode & MODE_80COLS)
x = (sigma->crtc[1] << 4) + 16;
else
x = (sigma->crtc[1] << 5) + 16;
for (c = 0; c < x; c++)
buffer32->line[sigma->displine][c] = sigma->palette[buffer32->line[sigma->displine][c] & 0xf] | 16;
video_process_8(x, sigma->displine);
sigma->sc = oldsc;
if (sigma->vc == sigma->crtc[7] && !sigma->sc)
sigma->sigmastat |= STATUS_RETR_V;
sigma->displine++;
if (sigma->displine >= 560)
sigma->displine = 0;
} else {
timer_advance_u64(&sigma->timer, sigma->dispontime);
sigma->linepos = 0;
if (sigma->vsynctime) {
sigma->vsynctime--;
if (!sigma->vsynctime)
sigma->sigmastat &= ~STATUS_RETR_V;
}
if (sigma->sc == (sigma->crtc[11] & 31) || ((sigma->crtc[8] & 3) == 3 && sigma->sc == ((sigma->crtc[11] & 31) >> 1))) {
sigma->con = 0;
sigma->coff = 1;
}
if ((sigma->crtc[8] & 3) == 3 && sigma->sc == (sigma->crtc[9] >> 1))
sigma->maback = sigma->ma;
if (sigma->vadj) {
sigma->sc++;
sigma->sc &= 31;
sigma->ma = sigma->maback;
sigma->vadj--;
if (!sigma->vadj) {
sigma->cgadispon = 1;
sigma->ma = sigma->maback = (sigma->crtc[13] | (sigma->crtc[12] << 8)) & 0x3fff;
sigma->sc = 0;
}
} else if (sigma->sc == sigma->crtc[9]) {
sigma->maback = sigma->ma;
sigma->sc = 0;
oldvc = sigma->vc;
sigma->vc++;
sigma->vc &= 127;
if (sigma->vc == sigma->crtc[6])
sigma->cgadispon = 0;
if (oldvc == sigma->crtc[4]) {
sigma->vc = 0;
sigma->vadj = sigma->crtc[5];
if (!sigma->vadj)
sigma->cgadispon = 1;
if (!sigma->vadj)
sigma->ma = sigma->maback = (sigma->crtc[13] | (sigma->crtc[12] << 8)) & 0x3fff;
if ((sigma->crtc[10] & 0x60) == 0x20)
sigma->cursoron = 0;
else
sigma->cursoron = sigma->cgablink & 8;
}
if (sigma->vc == sigma->crtc[7]) {
sigma->cgadispon = 0;
sigma->displine = 0;
sigma->vsynctime = 16;
if (sigma->crtc[7]) {
if (sigma->sigmamode & MODE_80COLS)
x = (sigma->crtc[1] << 4) + 16;
else
x = (sigma->crtc[1] << 5) + 16;
sigma->lastline++;
if ((x != xsize) || ((sigma->lastline - sigma->firstline) != ysize) || video_force_resize_get()) {
xsize = x;
ysize = sigma->lastline - sigma->firstline;
if (xsize < 64)
xsize = 656;
if (ysize < 32)
ysize = 200;
if (ysize <= 250)
set_screen_size(xsize, (ysize << 1) + 16);
else
set_screen_size(xsize, ysize + 8);
if (video_force_resize_get())
video_force_resize_set(0);
}
video_blit_memtoscreen(0, sigma->firstline - 4, xsize, (sigma->lastline - sigma->firstline) + 8);
frames++;
video_res_x = xsize - 16;
video_res_y = ysize;
if (sigma->sigmamode & MODE_GRAPHICS) {
if (sigma->sigmamode & (MODE_HRGFX | MODE_640x400))
video_bpp = 1;
else {
video_res_x /= 2;
video_bpp = 2;
}
} else if (sigma->sigmamode & MODE_80COLS) {
/* 80-column text */
video_res_x /= 8;
video_res_y /= sigma->crtc[9] + 1;
video_bpp = 0;
} else {
/* 40-column text */
video_res_x /= 16;
video_res_y /= sigma->crtc[9] + 1;
video_bpp = 0;
}
}
sigma->firstline = 1000;
sigma->lastline = 0;
sigma->cgablink++;
sigma->oddeven ^= 1;
}
} else {
sigma->sc++;
sigma->sc &= 31;
sigma->ma = sigma->maback;
}
if (sigma->cgadispon)
sigma->sigmastat &= ~STATUS_RETR_H;
if (sigma->sc == (sigma->crtc[10] & 31) || ((sigma->crtc[8] & 3) == 3 && sigma->sc == ((sigma->crtc[10] & 31) >> 1)))
sigma->con = 1;
}
}
static void *
sigma_init(UNUSED(const device_t *info))
{
int bios_addr;
sigma_t *sigma = malloc(sizeof(sigma_t));
memset(sigma, 0, sizeof(sigma_t));
bios_addr = device_get_config_hex20("bios_addr");
video_inform(VIDEO_FLAG_TYPE_CGA, &timing_sigma);
sigma->enable_nmi = device_get_config_int("enable_nmi");
loadfont(ROM_SIGMA_FONT, 7);
rom_init(&sigma->bios_rom, ROM_SIGMA_BIOS, bios_addr, 0x2000,
0x1FFF, 0, MEM_MAPPING_EXTERNAL);
/* The BIOS ROM is overlaid by RAM, so remove its default mapping
and access it through sigma_bread() / sigma_bwrite() below */
mem_mapping_disable(&sigma->bios_rom.mapping);
memcpy(sigma->bram, &sigma->bios_rom.rom[0x1800], 0x800);
sigma->vram = malloc(0x8000 * 4);
timer_add(&sigma->timer, sigma_poll, sigma, 1);
mem_mapping_add(&sigma->mapping, 0xb8000, 0x08000,
sigma_read, NULL, NULL,
sigma_write, NULL, NULL,
NULL, MEM_MAPPING_EXTERNAL, sigma);
mem_mapping_add(&sigma->bios_ram, bios_addr, 0x2000,
sigma_bread, NULL, NULL,
sigma_bwrite, NULL, NULL,
sigma->bios_rom.rom, MEM_MAPPING_EXTERNAL, sigma);
io_sethandler(0x03d0, 0x0010,
sigma_in, NULL, NULL,
sigma_out, NULL, NULL, sigma);
io_sethandler(0x02d0, 0x0010,
sigma_in, NULL, NULL,
sigma_out, NULL, NULL, sigma);
/* Start with ROM paged in, BIOS RAM paged out */
sigma->rom_paged = 0x80;
cga_palette = device_get_config_int("rgb_type") << 1;
if (cga_palette > 6)
cga_palette = 0;
cgapal_rebuild();
if (sigma->enable_nmi)
sigma->sigmastat = STATUS_LPEN_T;
return sigma;
}
static int
sigma_available(void)
{
return (rom_present(ROM_SIGMA_FONT) && rom_present(ROM_SIGMA_BIOS));
}
static void
sigma_close(void *priv)
{
sigma_t *sigma = (sigma_t *) priv;
free(sigma->vram);
free(sigma);
}
void
sigma_speed_changed(void *priv)
{
sigma_t *sigma = (sigma_t *) priv;
sigma_recalctimings(sigma);
}
device_config_t sigma_config[] = {
// clang-format off
{
.name = "rgb_type",
.description = "RGB type",
.type = CONFIG_SELECTION,
.default_int = 0,
.selection = {
{
.description = "Color",
.value = 0
},
{
.description = "Green Monochrome",
.value = 1
},
{
.description = "Amber Monochrome",
.value = 2
},
{
.description = "Gray Monochrome",
.value = 3
},
{
.description = "Color (no brown)",
.value = 4
},
{
.description = ""
}
}
},
{
.name = "enable_nmi",
.description = "Enable NMI for CGA emulation",
.type = CONFIG_BINARY,
.default_int = 1
},
{
.name = "bios_addr",
.description = "BIOS Address",
.type = CONFIG_HEX20,
.default_int = 0xc0000,
.selection = {
{
.description = "C000H",
.value = 0xc0000
},
{
.description = "C800H",
.value = 0xc8000
},
{
.description = "CC00H",
.value = 0xcc000
},
{
.description = "D000H",
.value = 0xd0000
},
{
.description = "D400H",
.value = 0xd4000
},
{
.description = "D800H",
.value = 0xd8000
},
{
.description = "DC00H",
.value = 0xdc000
},
{
.description = "E000H",
.value = 0xe0000
},
{
.description = "E400H",
.value = 0xe4000
},
{
.description = "E800H",
.value = 0xe8000
},
{
.description = "EC00H",
.value = 0xec000
},
{
.description = ""
}
},
},
{
.type = CONFIG_END
}
// clang-format on
};
const device_t sigma_device = {
.name = "Sigma Color 400",
.internal_name = "sigma400",
.flags = DEVICE_ISA,
.local = 0,
.init = sigma_init,
.close = sigma_close,
.reset = NULL,
{ .available = sigma_available },
.speed_changed = sigma_speed_changed,
.force_redraw = NULL,
.config = sigma_config
};
``` | /content/code_sandbox/src/video/vid_sigma.c | c | 2016-06-25T22:29:10 | 2024-08-16T19:09:21 | 86Box | 86Box/86Box | 2,616 | 9,640 |
```c
/*
* 86Box A hypervisor and IBM PC system emulator that specializes in
* running old operating systems and software designed for IBM
* PC systems and compatibles from 1981 through fairly recent
* system designs based on the PCI bus.
*
* This file is part of the 86Box distribution.
*
* Emulation of Sierra SC1148x RAMDACs and clones (e.g.: Winbond).
*
* Used by the S3 911 and 924 chips.
*
*
*
* Authors: TheCollector1995, <mariogplayer90@gmail.com>
*
*/
#include <stdio.h>
#include <stdint.h>
#include <stdlib.h>
#include <string.h>
#include <wchar.h>
#include <86box/86box.h>
#include <86box/device.h>
#include <86box/mem.h>
#include <86box/timer.h>
#include <86box/video.h>
#include <86box/vid_svga.h>
typedef struct sc1148x_ramdac_t {
int type;
int state;
int rs2;
uint8_t ctrl;
} sc1148x_ramdac_t;
void
sc1148x_ramdac_out(uint16_t addr, int rs2, uint8_t val, void *priv, svga_t *svga)
{
sc1148x_ramdac_t *ramdac = (sc1148x_ramdac_t *) priv;
uint8_t rs = (addr & 0x03) | ((!!rs2) << 2);
int oldbpp = 0;
switch (rs) {
case 2:
case 6:
switch (ramdac->state) {
case 4:
ramdac->state = 0;
if (val == 0xff)
break;
ramdac->ctrl = val;
ramdac->ctrl = (ramdac->ctrl & ~1) | ((((val >> 2) ^ val) & (val & 0x20)) >> 5);
oldbpp = svga->bpp;
switch (ramdac->type) {
case 0: /* Sierra Mark 2 (11483)*/
case 2: /* Sierra Mark 2 (11484)*/
case 3: /* Sierra Mark 1 (11486)*/
if (val & 0xa0) {
svga->bpp = 15;
} else if (val == 0x00)
svga->bpp = 8;
break;
case 1: /* Sierra Mark 3 (11487)*/
if (val & 0xa0) {
if (val & 0x40)
svga->bpp = 16;
else
svga->bpp = 15;
} else if (val == 0x00)
svga->bpp = 8;
break;
default:
break;
}
if (oldbpp != svga->bpp)
svga_recalctimings(svga);
return;
default:
svga_out(addr, val, svga);
break;
}
break;
default:
ramdac->state = 0;
svga_out(addr, val, svga);
break;
}
}
uint8_t
sc1148x_ramdac_in(uint16_t addr, int rs2, void *priv, svga_t *svga)
{
sc1148x_ramdac_t *ramdac = (sc1148x_ramdac_t *) priv;
uint8_t ret = 0xff;
uint8_t rs = (addr & 0x03) | ((!!rs2) << 2);
switch (rs) {
case 2:
case 6:
switch (ramdac->state) {
case 1:
case 2:
case 3:
ret = 0x00;
ramdac->state++;
break;
case 4:
ret = ramdac->ctrl;
ret = (ret & ~0x18) | (svga->dac_mask & 0x18);
break;
default:
ret = svga_in(addr, svga);
ramdac->state++;
break;
}
break;
default:
ret = svga_in(addr, svga);
ramdac->state = 0;
break;
}
return ret;
}
static void *
sc1148x_ramdac_init(const device_t *info)
{
sc1148x_ramdac_t *ramdac = (sc1148x_ramdac_t *) malloc(sizeof(sc1148x_ramdac_t));
memset(ramdac, 0, sizeof(sc1148x_ramdac_t));
ramdac->type = info->local;
return ramdac;
}
static void
sc1148x_ramdac_close(void *priv)
{
sc1148x_ramdac_t *ramdac = (sc1148x_ramdac_t *) priv;
if (ramdac)
free(ramdac);
}
const device_t sc11483_ramdac_device = {
.name = "Sierra SC11483 RAMDAC",
.internal_name = "sc11483_ramdac",
.flags = 0,
.local = 0,
.init = sc1148x_ramdac_init,
.close = sc1148x_ramdac_close,
.reset = NULL,
{ .available = NULL },
.speed_changed = NULL,
.force_redraw = NULL,
.config = NULL
};
const device_t sc11487_ramdac_device = {
.name = "Sierra SC11487 RAMDAC",
.internal_name = "sc11487_ramdac",
.flags = 0,
.local = 1,
.init = sc1148x_ramdac_init,
.close = sc1148x_ramdac_close,
.reset = NULL,
{ .available = NULL },
.speed_changed = NULL,
.force_redraw = NULL,
.config = NULL
};
const device_t sc11484_nors2_ramdac_device = {
.name = "Sierra SC11484 RAMDAC (no RS2 signal)",
.internal_name = "sc11484_nors2_ramdac",
.flags = 0,
.local = 2,
.init = sc1148x_ramdac_init,
.close = sc1148x_ramdac_close,
.reset = NULL,
{ .available = NULL },
.speed_changed = NULL,
.force_redraw = NULL,
.config = NULL
};
const device_t sc11486_ramdac_device = {
.name = "Sierra SC11486 RAMDAC",
.internal_name = "sc11486_ramdac",
.flags = 0,
.local = 3,
.init = sc1148x_ramdac_init,
.close = sc1148x_ramdac_close,
.reset = NULL,
{ .available = NULL },
.speed_changed = NULL,
.force_redraw = NULL,
.config = NULL
};
``` | /content/code_sandbox/src/video/vid_sc1148x_ramdac.c | c | 2016-06-25T22:29:10 | 2024-08-16T19:09:21 | 86Box | 86Box/86Box | 2,616 | 1,566 |
```c
/*
* 86Box A hypervisor and IBM PC system emulator that specializes in
* running old operating systems and software designed for IBM
* PC systems and compatibles from 1981 through fairly recent
* system designs based on the PCI bus.
*
* This file is part of the 86Box distribution.
*
* 87C716 'SDAC' true colour RAMDAC emulation.
*
*
*
* Authors: Sarah Walker, <path_to_url
* Miran Grca, <mgrca8@gmail.com>
*
*/
#include <stdio.h>
#include <stdint.h>
#include <stdlib.h>
#include <string.h>
#include <wchar.h>
#include <86box/86box.h>
#include <86box/device.h>
#include <86box/mem.h>
#include <86box/timer.h>
#include <86box/video.h>
#include <86box/vid_svga.h>
enum {
ICS_5300 = 0,
ICS_5301,
ICS_5340,
ICS_5341,
ICS_5342
};
#define ICS_S3_MASK 7
#define ICS_S3 8
#define S3_86C708 (ICS_5300 | ICS_S3)
#define S3_86C716 (ICS_5342 | ICS_S3)
typedef struct sdac_ramdac_t {
uint16_t regs[256];
int magic_count;
int windex;
int rindex;
int reg_ff;
int rs2;
uint8_t type;
uint8_t command;
} sdac_ramdac_t;
static void
sdac_control_write(sdac_ramdac_t *ramdac, svga_t *svga, uint8_t val)
{
ramdac->command = val;
switch (ramdac->type & ICS_S3_MASK) {
case ICS_5300:
case ICS_5301:
switch (val >> 5) {
default:
case 0x00:
svga->bpp = 8;
break;
case 0x01:
case 0x04:
case 0x05:
svga->bpp = 15;
break;
case 0x03:
case 0x06:
svga->bpp = 16;
break;
case 0x02:
case 0x07:
svga->bpp = 24;
break;
}
break;
case ICS_5340:
case ICS_5341:
case ICS_5342:
switch (val >> 4) {
default:
case 0x00:
case 0x01: /* This is actually 8bpp with two pixels read at a time. */
svga->bpp = 8;
break;
case 0x02:
case 0x03:
case 0x08:
case 0x0a:
svga->bpp = 15;
break;
case 0x05:
case 0x06:
case 0x0c:
svga->bpp = 16;
break;
case 0x04:
case 0x09:
case 0x0e:
svga->bpp = 24;
break;
case 0x07:
svga->bpp = 32;
break;
}
break;
default:
break;
}
svga_recalctimings(svga);
}
static void
sdac_reg_write(sdac_ramdac_t *ramdac, int reg, uint8_t val)
{
if ((reg >= 2 && reg <= 7) || (reg == 0xa) || (reg == 0xe)) {
if (!ramdac->reg_ff)
ramdac->regs[reg] = (ramdac->regs[reg] & 0xff00) | val;
else
ramdac->regs[reg] = (ramdac->regs[reg] & 0x00ff) | (val << 8);
}
ramdac->reg_ff = !ramdac->reg_ff;
if (!ramdac->reg_ff)
ramdac->windex++;
}
static uint8_t
sdac_reg_read(sdac_ramdac_t *ramdac, int reg)
{
uint8_t temp;
if (!ramdac->reg_ff)
temp = ramdac->regs[reg] & 0xff;
else
temp = ramdac->regs[reg] >> 8;
ramdac->reg_ff = !ramdac->reg_ff;
if (!ramdac->reg_ff)
ramdac->rindex++;
return temp;
}
void
sdac_ramdac_out(uint16_t addr, int rs2, uint8_t val, void *priv, svga_t *svga)
{
sdac_ramdac_t *ramdac = (sdac_ramdac_t *) priv;
uint8_t rs = (addr & 0x03);
rs |= ((!!rs2) << 2);
if (rs != 0x02)
ramdac->magic_count = 0;
switch (rs) {
case 0x02:
switch (ramdac->magic_count) {
case 4:
sdac_control_write(ramdac, svga, val);
ramdac->magic_count = 0;
break;
default:
svga_out(addr, val, svga);
break;
}
break;
case 0x00:
case 0x01:
case 0x03:
svga_out(addr, val, svga);
break;
case 0x04:
ramdac->windex = val;
ramdac->reg_ff = 0;
break;
case 0x05:
sdac_reg_write(ramdac, ramdac->windex & 0xff, val);
break;
case 0x06:
sdac_control_write(ramdac, svga, val);
break;
case 0x07:
ramdac->rindex = val;
ramdac->reg_ff = 0;
break;
default:
break;
}
}
uint8_t
sdac_ramdac_in(uint16_t addr, int rs2, void *priv, svga_t *svga)
{
sdac_ramdac_t *ramdac = (sdac_ramdac_t *) priv;
uint8_t temp = 0xff;
uint8_t rs = (addr & 0x03);
rs |= ((!!rs2) << 2);
if (rs != 0x02)
ramdac->magic_count = 0;
switch (rs) {
case 0x02:
switch (ramdac->magic_count) {
case 1:
case 2:
temp = 0x00;
ramdac->magic_count++;
break;
case 3:
temp = (ramdac->type & ICS_S3) ? 0x70 : 0x00;
ramdac->magic_count++;
break;
case 4:
temp = ramdac->command;
ramdac->magic_count = 0;
break;
default:
temp = svga_in(addr, svga);
ramdac->magic_count++;
break;
}
break;
case 0x00:
case 0x01:
case 0x03:
temp = svga_in(addr, svga);
break;
case 0x04:
temp = ramdac->windex;
break;
case 0x05:
temp = sdac_reg_read(ramdac, ramdac->rindex & 0xff);
break;
case 0x06:
temp = ramdac->command;
break;
case 0x07:
temp = ramdac->rindex;
break;
default:
break;
}
return temp;
}
float
sdac_getclock(int clock, void *priv)
{
const sdac_ramdac_t *ramdac = (sdac_ramdac_t *) priv;
float t;
int m;
int n1;
int n2;
if (ramdac->regs[0xe] & (1 << 5))
clock = ramdac->regs[0xe] & 7;
clock &= 7;
if (clock == 0)
return 25175000.0;
if (clock == 1)
return 28322000.0;
m = (ramdac->regs[clock] & 0x7f) + 2;
n1 = ((ramdac->regs[clock] >> 8) & 0x1f) + 2;
n2 = ((ramdac->regs[clock] >> 13) & 0x07);
n2 = (1 << n2);
t = (14318184.0f * (float) m) / (float) (n1 * n2);
return t;
}
void *
sdac_ramdac_init(const device_t *info)
{
sdac_ramdac_t *ramdac = (sdac_ramdac_t *) malloc(sizeof(sdac_ramdac_t));
memset(ramdac, 0, sizeof(sdac_ramdac_t));
ramdac->type = info->local;
ramdac->regs[0] = 0x6128;
ramdac->regs[1] = 0x623d;
return ramdac;
}
static void
sdac_ramdac_close(void *priv)
{
sdac_ramdac_t *ramdac = (sdac_ramdac_t *) priv;
if (ramdac)
free(ramdac);
}
const device_t gendac_ramdac_device = {
.name = "S3 GENDAC 86c708 RAMDAC",
.internal_name = "gendac_ramdac",
.flags = 0,
.local = S3_86C708,
.init = sdac_ramdac_init,
.close = sdac_ramdac_close,
.reset = NULL,
{ .available = NULL },
.speed_changed = NULL,
.force_redraw = NULL,
.config = NULL
};
const device_t tseng_ics5301_ramdac_device = {
.name = "Tseng ICS5301 GENDAC RAMDAC",
.internal_name = "tseng_ics5301_ramdac",
.flags = 0,
.local = ICS_5301,
.init = sdac_ramdac_init,
.close = sdac_ramdac_close,
.reset = NULL,
{ .available = NULL },
.speed_changed = NULL,
.force_redraw = NULL,
.config = NULL
};
const device_t tseng_ics5341_ramdac_device = {
.name = "Tseng ICS5341 GENDAC RAMDAC",
.internal_name = "tseng_ics5341_ramdac",
.flags = 0,
.local = ICS_5341,
.init = sdac_ramdac_init,
.close = sdac_ramdac_close,
.reset = NULL,
{ .available = NULL },
.speed_changed = NULL,
.force_redraw = NULL,
.config = NULL
};
const device_t sdac_ramdac_device = {
.name = "S3 SDAC 86c716 RAMDAC",
.internal_name = "sdac_ramdac",
.flags = 0,
.local = S3_86C716,
.init = sdac_ramdac_init,
.close = sdac_ramdac_close,
.reset = NULL,
{ .available = NULL },
.speed_changed = NULL,
.force_redraw = NULL,
.config = NULL
};
``` | /content/code_sandbox/src/video/vid_sdac_ramdac.c | c | 2016-06-25T22:29:10 | 2024-08-16T19:09:21 | 86Box | 86Box/86Box | 2,616 | 2,641 |
```c
/*
* 86Box A hypervisor and IBM PC system emulator that specializes in
* running old operating systems and software designed for IBM
* PC systems and compatibles from 1981 through fairly recent
* system designs based on the PCI bus.
*
* This file is part of the 86Box distribution.
*
* ET4000/W32 series emulation.
*
* Known bugs: Accelerator doesn't work in planar modes
*
*
*
* Authors: Sarah Walker, <path_to_url
* Miran Grca, <mgrca8@gmail.com>
*
*/
#include <stdarg.h>
#include <stdint.h>
#include <stdio.h>
#include <string.h>
#include <stdlib.h>
#include <wchar.h>
#define HAVE_STDARG_H
#include <86box/86box.h>
#include <86box/io.h>
#include <86box/mem.h>
#include <86box/pci.h>
#include <86box/rom.h>
#include <86box/device.h>
#include <86box/timer.h>
#include <86box/plat.h>
#include <86box/video.h>
#include <86box/vid_svga.h>
#include <86box/vid_svga_render.h>
#define BIOS_ROM_PATH_DIAMOND "roms/video/et4000w32/et4000w32.bin"
#define BIOS_ROM_PATH_CARDEX "roms/video/et4000w32/cardex.vbi"
#define BIOS_ROM_PATH_W32 "roms/video/et4000w32/ET4000W32VLB_bios_MX27C512.BIN"
#define BIOS_ROM_PATH_W32I_ISA "roms/video/et4000w32/ET4KW32I.VBI"
#define BIOS_ROM_PATH_W32I_VLB "roms/video/et4000w32/tseng.u41.bin"
#define BIOS_ROM_PATH_W32P_VIDEOMAGIC_REVB_VLB "roms/video/et4000w32/VideoMagic-BioS-HXIRTW32PWSRL.bin"
#define BIOS_ROM_PATH_W32P "roms/video/et4000w32/ET4K_W32.BIN"
#define BIOS_ROM_PATH_W32P_REVC "roms/video/et4000w32/et4000w32pcardex.BIN"
#define ACL_WRST 1
#define ACL_RDST 2
#define ACL_XYST 4
#define ACL_SSO 8
enum {
ET4000W32,
ET4000W32I,
ET4000W32P_REVC,
ET4000W32P_VIDEOMAGIC_REVB,
ET4000W32P,
ET4000W32P_CARDEX,
ET4000W32P_DIAMOND
};
typedef struct et4000w32p_t {
mem_mapping_t linear_mapping;
mem_mapping_t mmu_mapping;
rom_t bios_rom;
svga_t svga;
uint8_t banking, banking2, adjust_cursor, rev, pci_slot;
uint8_t regs[256], pci_regs[256];
int index, vlb, pci, interleaved,
bank, type;
uint32_t linearbase;
uint32_t vram_mask;
/* Accelerator */
struct {
struct {
uint8_t vbus, pixel_depth, xy_dir, pattern_wrap,
source_wrap, ctrl_routing, ctrl_reload, rop_fg,
rop_bg;
uint16_t pattern_off, source_off, dest_off, mix_off,
count_x, count_y, pos_x, pos_y,
error, dmin, dmaj;
uint32_t pattern_addr, source_addr, dest_addr, mix_addr;
} queued, internal;
uint8_t suspend_terminate, osr;
uint8_t status;
uint16_t x_count, y_count;
uint16_t cpu_x_cnt, cpu_x_cnt_back, cpu_y_cnt;
int pattern_x, source_x, pattern_x_back, source_x_back,
pattern_y, source_y, cpu_dat_pos, pix_pos,
cpu_input_num, fifo_queue;
int mmu_start;
uint32_t pattern_addr, source_addr, dest_addr, mix_addr,
pattern_back, source_back, dest_back, mix_back,
cpu_input;
uint64_t cpu_dat;
} acl;
struct {
uint32_t base[3];
uint8_t ctrl;
} mmu;
volatile int busy;
} et4000w32p_t;
static int et4000w32_vbus[4] = { 1, 2, 4, 4 };
static int et4000w32_max_x[8] = { 0, 0, 4, 8, 0x10, 0x20, 0x40, 0x70000000 };
static int et4000w32_wrap_x[8] = { 0, 0, 3, 7, 0x0f, 0x1f, 0x3f, ~0 };
static int et4000w32_wrap_y[8] = { 1, 2, 4, 8, ~0, ~0, ~0, ~0 };
static video_timings_t timing_et4000w32_vlb = { .type = VIDEO_BUS, .write_b = 4, .write_w = 4, .write_l = 4, .read_b = 10, .read_w = 10, .read_l = 10 };
static video_timings_t timing_et4000w32_pci = { .type = VIDEO_PCI, .write_b = 4, .write_w = 4, .write_l = 4, .read_b = 10, .read_w = 10, .read_l = 10 };
static video_timings_t timing_et4000w32_isa = { .type = VIDEO_ISA, .write_b = 4, .write_w = 4, .write_l = 4, .read_b = 10, .read_w = 10, .read_l = 10 };
void et4000w32p_recalcmapping(et4000w32p_t *et4000);
static uint8_t et4000w32p_mmu_read(uint32_t addr, void *priv);
static void et4000w32p_mmu_write(uint32_t addr, uint8_t val, void *priv);
static void et4000w32_blit_start(et4000w32p_t *et4000);
static void et4000w32p_blit_start(et4000w32p_t *et4000);
static void et4000w32_blit(int count, int cpu_input, uint32_t src_dat, uint32_t mix_dat, et4000w32p_t *et4000);
static void et4000w32p_blit(int count, uint32_t mix, uint32_t sdat, int cpu_input, et4000w32p_t *et4000);
uint8_t et4000w32p_in(uint16_t addr, void *priv);
#ifdef ENABLE_ET4000W32_LOG
int et4000w32_do_log = ENABLE_ET4000W32_LOG;
static void
et4000w32_log(const char *fmt, ...)
{
va_list ap;
if (et4000w32_do_log) {
va_start(ap, fmt);
pclog_ex(fmt, ap);
va_end(ap);
}
}
#else
# define et4000w32_log(fmt, ...)
#endif
void
et4000w32p_out(uint16_t addr, uint8_t val, void *priv)
{
et4000w32p_t *et4000 = (et4000w32p_t *) priv;
svga_t *svga = &et4000->svga;
uint8_t old;
uint32_t add2addr = 0;
if (((addr & 0xfff0) == 0x3d0 || (addr & 0xfff0) == 0x3b0) && !(svga->miscout & 1))
addr ^= 0x60;
switch (addr) {
case 0x3c2:
if (et4000->type == ET4000W32P_DIAMOND)
icd2061_write(svga->clock_gen, (val >> 2) & 3);
break;
case 0x3c6:
case 0x3c7:
case 0x3c8:
case 0x3c9:
if (et4000->type <= ET4000W32P_REVC)
sdac_ramdac_out(addr, 0, val, svga->ramdac, svga);
else
stg_ramdac_out(addr, val, svga->ramdac, svga);
return;
case 0x3cb: /* Banking extension */
if (!(svga->crtc[0x36] & 0x10) && !(svga->gdcreg[6] & 0x08)) {
svga->write_bank = (svga->write_bank & 0xfffff) | ((val & 1) << 20);
svga->read_bank = (svga->read_bank & 0xfffff) | ((val & 0x10) << 16);
}
et4000->banking2 = val;
return;
case 0x3cd: /* Banking */
if (!(svga->crtc[0x36] & 0x10) && !(svga->gdcreg[6] & 0x08)) {
svga->write_bank = (svga->write_bank & 0x100000) | ((val & 0xf) * 65536);
svga->read_bank = (svga->read_bank & 0x100000) | (((val >> 4) & 0xf) * 65536);
}
et4000->banking = val;
return;
case 0x3cf:
switch (svga->gdcaddr & 15) {
case 6:
if (!(svga->crtc[0x36] & 0x10) && !(val & 0x08)) {
svga->write_bank = ((et4000->banking2 & 1) << 20) | ((et4000->banking & 0xf) * 65536);
svga->read_bank = ((et4000->banking2 & 0x10) << 16) | (((et4000->banking >> 4) & 0xf) * 65536);
} else
svga->write_bank = svga->read_bank = 0;
svga->gdcreg[svga->gdcaddr & 15] = val;
et4000w32p_recalcmapping(et4000);
return;
default:
break;
}
break;
case 0x3d4:
svga->crtcreg = val & 0x3f;
return;
case 0x3d5:
if ((svga->crtcreg < 7) && (svga->crtc[0x11] & 0x80))
return;
if ((svga->crtcreg == 0x35) && (svga->crtc[0x11] & 0x80))
return;
if ((svga->crtcreg == 7) && (svga->crtc[0x11] & 0x80))
val = (svga->crtc[7] & ~0x10) | (val & 0x10);
old = svga->crtc[svga->crtcreg];
svga->crtc[svga->crtcreg] = val;
if (svga->crtcreg == 0x36) {
if (!(val & 0x10) && !(svga->gdcreg[6] & 0x08)) {
svga->write_bank = ((et4000->banking2 & 1) << 20) | ((et4000->banking & 0xf) * 65536);
svga->read_bank = ((et4000->banking2 & 0x10) << 16) | (((et4000->banking >> 4) & 0xf) * 65536);
} else
svga->write_bank = svga->read_bank = 0;
}
if (old != val) {
if (svga->crtcreg < 0xe || svga->crtcreg > 0x10) {
if ((svga->crtcreg == 0xc) || (svga->crtcreg == 0xd)) {
svga->fullchange = 3;
svga->ma_latch = ((svga->crtc[0xc] << 8) | svga->crtc[0xd]) + ((svga->crtc[8] & 0x60) >> 5);
} else {
svga->fullchange = changeframecount;
svga_recalctimings(svga);
}
}
}
if (svga->crtcreg == 0x30) {
if (et4000->pci && (et4000->rev != 5))
et4000->linearbase = (et4000->linearbase & 0xc0000000) | ((val & 0xfc) << 22);
else
et4000->linearbase = val << 22;
et4000w32p_recalcmapping(et4000);
}
if (svga->crtcreg == 0x32 || svga->crtcreg == 0x36)
et4000w32p_recalcmapping(et4000);
break;
case 0x210a:
case 0x211a:
case 0x212a:
case 0x213a:
case 0x214a:
case 0x215a:
case 0x216a:
case 0x217a:
et4000->index = val;
return;
case 0x210b:
case 0x211b:
case 0x212b:
case 0x213b:
case 0x214b:
case 0x215b:
case 0x216b:
case 0x217b:
et4000->regs[et4000->index] = val;
svga->hwcursor.x = et4000->regs[0xE0] | ((et4000->regs[0xE1] & 7) << 8);
svga->hwcursor.y = et4000->regs[0xE4] | ((et4000->regs[0xE5] & 7) << 8);
svga->hwcursor.ena = !!(et4000->regs[0xF7] & 0x80);
svga->hwcursor.xoff = et4000->regs[0xE2];
svga->hwcursor.yoff = et4000->regs[0xE6];
svga->hwcursor.cur_xsize = svga->hwcursor.cur_ysize = ((et4000->regs[0xEF] & 4) || ((et4000->type == ET4000W32) && (et4000->regs[0xe2] >= 0x1f) && (et4000->regs[0xe6] >= 0x1f))) ? 128 : 64;
if (et4000->type == ET4000W32) {
if ((svga->bpp == 15) || (svga->bpp == 16)) {
svga->hwcursor.cur_xsize = svga->hwcursor.cur_ysize = 128;
}
}
if ((et4000->type == ET4000W32) && (svga->hwcursor.cur_xsize == 128)) {
switch (svga->bpp) {
case 8:
svga->hwcursor.xoff += 32;
break;
default:
break;
}
}
if (svga->hwcursor.cur_xsize == 128) {
svga->hwcursor.xoff &= 0x7f;
svga->hwcursor.yoff &= 0x7f;
if (et4000->type > ET4000W32P_REVC) {
if (svga->bpp == 24) {
et4000->adjust_cursor = 2;
}
}
} else {
if (et4000->type > ET4000W32P_REVC) {
if ((svga->bpp == 24) && et4000->adjust_cursor) {
et4000->adjust_cursor = 0;
}
}
svga->hwcursor.xoff &= 0x3f;
svga->hwcursor.yoff &= 0x3f;
}
svga->hwcursor.addr = (et4000->regs[0xe8] | (et4000->regs[0xe9] << 8) | ((et4000->regs[0xea] & 7) << 16)) << 2;
add2addr = svga->hwcursor.yoff * ((svga->hwcursor.cur_xsize == 128) ? 32 : 16);
svga->hwcursor.addr += add2addr;
return;
default:
break;
}
svga_out(addr, val, svga);
}
uint8_t
et4000w32p_in(uint16_t addr, void *priv)
{
et4000w32p_t *et4000 = (et4000w32p_t *) priv;
svga_t *svga = &et4000->svga;
if (((addr & 0xfff0) == 0x3d0 || (addr & 0xfff0) == 0x3b0) && !(svga->miscout & 1))
addr ^= 0x60;
switch (addr) {
case 0x3c5:
if ((svga->seqaddr & 0xf) == 7)
return svga->seqregs[svga->seqaddr & 0xf] | 4;
break;
case 0x3c6:
case 0x3c7:
case 0x3c8:
case 0x3c9:
if (et4000->type <= ET4000W32P_REVC)
return sdac_ramdac_in(addr, 0, svga->ramdac, svga);
else
return stg_ramdac_in(addr, svga->ramdac, svga);
case 0x3cb:
return et4000->banking2;
case 0x3cd:
return et4000->banking;
case 0x3d4:
return svga->crtcreg;
case 0x3d5:
if (et4000->type == ET4000W32) {
if (svga->crtcreg == 0x37)
return 0x09;
}
return svga->crtc[svga->crtcreg];
case 0x3da:
svga->attrff = 0;
/*Bit 1 of the Input Status Register is required by the OS/2 and NT ET4000W32/I drivers to be set otherwise
the guest will loop infinitely upon reaching the GUI*/
if (svga->cgastat & 0x01)
svga->cgastat &= ~0x32;
else
svga->cgastat ^= 0x32;
return svga->cgastat;
case 0x210a:
case 0x211a:
case 0x212a:
case 0x213a:
case 0x214a:
case 0x215a:
case 0x216a:
case 0x217a:
return et4000->index;
case 0x210B:
case 0x211B:
case 0x212B:
case 0x213B:
case 0x214B:
case 0x215B:
case 0x216B:
case 0x217B:
if (et4000->index == 0xec) {
return (et4000->regs[0xec] & 0xf) | (et4000->rev << 4);
}
if (et4000->index == 0xee) {
if (svga->bpp == 8) {
if ((svga->gdcreg[5] & 0x60) >= 0x40)
return 3;
else if ((svga->gdcreg[5] & 0x60) == 0x20)
return 1;
else
return 2;
} else if (svga->bpp == 15 || svga->bpp == 16)
return 4;
else
break;
}
if (et4000->index == 0xef) {
if (et4000->pci)
return (et4000->regs[0xef] & 0x0f) | (et4000->rev << 4) | et4000->pci;
else
return (et4000->regs[0xef] & 0x8f) | (et4000->rev << 4) | et4000->vlb;
}
return et4000->regs[et4000->index];
default:
break;
}
return svga_in(addr, svga);
}
void
et4000w32p_recalctimings(svga_t *svga)
{
et4000w32p_t *et4000 = (et4000w32p_t *) svga->priv;
svga->ma_latch |= (svga->crtc[0x33] & 0x7) << 16;
svga->hblankstart = (((svga->crtc[0x3f] & 0x4) >> 2) << 8) + svga->crtc[2];
if (svga->crtc[0x35] & 0x01)
svga->vblankstart |= 0x400;
if (svga->crtc[0x35] & 0x02)
svga->vtotal |= 0x400;
if (svga->crtc[0x35] & 0x04)
svga->dispend |= 0x400;
if (svga->crtc[0x35] & 0x08)
svga->vsyncstart |= 0x400;
if (svga->crtc[0x35] & 0x10)
svga->split |= 0x400;
if (svga->crtc[0x3F] & 0x80)
svga->rowoffset |= 0x100;
if (svga->crtc[0x3F] & 0x01)
svga->htotal |= 0x100;
if (svga->attrregs[0x16] & 0x20) {
svga->hdisp <<= 1;
svga->dots_per_clock <<= 1;
}
svga->clock = (cpuclock * (double) (1ULL << 32)) / svga->getclock((svga->miscout >> 2) & 3, svga->clock_gen);
if (et4000->type != ET4000W32P_DIAMOND) {
if ((svga->gdcreg[6] & 1) || (svga->attrregs[0x10] & 1)) {
if (svga->gdcreg[5] & 0x40) {
switch (svga->bpp) {
case 8:
svga->clock /= 2;
break;
case 15:
case 16:
svga->clock /= 3;
break;
case 24:
svga->clock /= 4;
break;
default:
break;
}
}
}
}
if (et4000->type == ET4000W32) {
if ((svga->gdcreg[6] & 1) || (svga->attrregs[0x10] & 1)) {
if (svga->gdcreg[5] & 0x40) {
switch (svga->bpp) {
case 8:
if (svga->hdisp == 640 || svga->hdisp == 800 || svga->hdisp == 1024)
break;
svga->hdisp -= 24;
break;
default:
break;
}
}
}
}
et4000->adjust_cursor = 0;
switch (svga->bpp) {
case 15:
case 16:
if ((svga->gdcreg[6] & 1) || (svga->attrregs[0x10] & 1)) {
svga->hdisp >>= 1;
svga->dots_per_clock >>= 1;
}
if (et4000->type <= ET4000W32P_REVC) {
if (et4000->type == ET4000W32P_REVC) {
if (svga->hdisp != 1024)
et4000->adjust_cursor = 1;
} else
et4000->adjust_cursor = 1;
}
break;
case 24:
svga->hdisp /= 3;
svga->dots_per_clock /= 3;
if (et4000->type <= ET4000W32P_REVC)
et4000->adjust_cursor = 2;
if ((et4000->type == ET4000W32P_DIAMOND) && ((svga->hdisp == (640 / 2)) || (svga->hdisp == 1232))) {
svga->hdisp = 640;
}
break;
default:
break;
}
svga->render = svga_render_blank;
if (!svga->scrblank && svga->attr_palette_enable) {
if (!(svga->gdcreg[6] & 1) && !(svga->attrregs[0x10] & 1)) { /* Text mode */
if (svga->seqregs[1] & 8) /* 40 column */
svga->render = svga_render_text_40;
else
svga->render = svga_render_text_80;
} else {
switch (svga->gdcreg[5] & 0x60) {
case 0x00:
if (svga->seqregs[1] & 8) /* Low res (320) */
svga->render = svga_render_4bpp_lowres;
else
svga->render = svga_render_4bpp_highres;
break;
case 0x20: /* 4 colours */
if (svga->seqregs[1] & 8) /*Low res (320)*/
svga->render = svga_render_2bpp_lowres;
else
svga->render = svga_render_2bpp_highres;
break;
case 0x40:
case 0x60: /* 256+ colours */
if (et4000->type <= ET4000W32P_REVC)
svga->clock /= 2;
switch (svga->bpp) {
case 8:
svga->map8 = svga->pallook;
if (svga->lowres)
svga->render = svga_render_8bpp_lowres;
else
svga->render = svga_render_8bpp_highres;
break;
case 15:
if (svga->lowres || (svga->seqregs[1] & 8))
svga->render = svga_render_15bpp_lowres;
else
svga->render = svga_render_15bpp_highres;
break;
case 16:
if (svga->lowres || (svga->seqregs[1] & 8))
svga->render = svga_render_16bpp_lowres;
else
svga->render = svga_render_16bpp_highres;
break;
case 17:
if (svga->lowres || (svga->seqregs[1] & 8))
svga->render = svga_render_15bpp_mix_lowres;
else
svga->render = svga_render_15bpp_mix_highres;
break;
case 24:
if (svga->lowres || (svga->seqregs[1] & 8))
svga->render = svga_render_24bpp_lowres;
else
svga->render = svga_render_24bpp_highres;
break;
case 32:
if (svga->lowres || (svga->seqregs[1] & 8))
svga->render = svga_render_32bpp_lowres;
else
svga->render = svga_render_32bpp_highres;
break;
default:
break;
}
break;
default:
break;
}
}
}
}
void
et4000w32p_recalcmapping(et4000w32p_t *et4000)
{
svga_t *svga = &et4000->svga;
int map;
if (et4000->pci && !(et4000->pci_regs[PCI_REG_COMMAND] & PCI_COMMAND_MEM)) {
mem_mapping_disable(&svga->mapping);
mem_mapping_disable(&et4000->linear_mapping);
mem_mapping_disable(&et4000->mmu_mapping);
return;
}
if (svga->crtc[0x36] & 0x10) { /* Linear frame buffer */
mem_mapping_set_addr(&et4000->linear_mapping, et4000->linearbase, 0x200000);
mem_mapping_disable(&svga->mapping);
mem_mapping_disable(&et4000->mmu_mapping);
} else {
map = (svga->gdcreg[6] & 0xc) >> 2;
if (svga->crtc[0x36] & 0x20)
map |= 4;
if (svga->crtc[0x36] & 0x08)
map |= 8;
mem_mapping_disable(&et4000->linear_mapping);
switch (map) {
case 0x0:
case 0x4:
case 0x8:
case 0xc: /* 128k at A0000 */
mem_mapping_set_addr(&svga->mapping, 0xa0000, 0x20000);
mem_mapping_disable(&et4000->mmu_mapping);
svga->banked_mask = 0x1ffff;
break;
case 0x1: /* 64k at A0000 */
mem_mapping_set_addr(&svga->mapping, 0xa0000, 0x10000);
mem_mapping_disable(&et4000->mmu_mapping);
svga->banked_mask = 0xffff;
break;
case 0x2: /* 32k at B0000 */
mem_mapping_set_addr(&svga->mapping, 0xb0000, 0x08000);
mem_mapping_disable(&et4000->mmu_mapping);
svga->banked_mask = 0x7fff;
break;
case 0x3: /* 32k at B8000 */
mem_mapping_set_addr(&svga->mapping, 0xb8000, 0x08000);
mem_mapping_disable(&et4000->mmu_mapping);
svga->banked_mask = 0x7fff;
break;
case 0x5:
case 0x9:
case 0xd: /* 64k at A0000, MMU at B8000 */
mem_mapping_set_addr(&svga->mapping, 0xa0000, 0x10000);
mem_mapping_set_addr(&et4000->mmu_mapping, 0xb8000, 0x08000);
svga->banked_mask = 0xffff;
break;
case 0x6:
case 0xa:
case 0xe: /* 32k at B0000, MMU at A8000 */
mem_mapping_set_addr(&svga->mapping, 0xb0000, 0x08000);
mem_mapping_set_addr(&et4000->mmu_mapping, 0xa8000, 0x08000);
svga->banked_mask = 0x7fff;
break;
case 0x7:
case 0xb:
case 0xf: /* 32k at B8000, MMU at A8000 */
mem_mapping_set_addr(&svga->mapping, 0xb8000, 0x08000);
mem_mapping_set_addr(&et4000->mmu_mapping, 0xa8000, 0x08000);
svga->banked_mask = 0x7fff;
break;
default:
break;
}
}
if (!et4000->interleaved && (svga->crtc[0x32] & 0x80))
mem_mapping_disable(&svga->mapping);
}
static void
et4000w32p_accel_write_fifo(et4000w32p_t *et4000, uint32_t addr, uint8_t val)
{
et4000->acl.fifo_queue++;
switch (addr & 0xff) {
case 0x80:
et4000->acl.queued.pattern_addr = (et4000->acl.queued.pattern_addr & 0xffffff00) | val;
break;
case 0x81:
et4000->acl.queued.pattern_addr = (et4000->acl.queued.pattern_addr & 0xffff00ff) | (val << 8);
break;
case 0x82:
et4000->acl.queued.pattern_addr = (et4000->acl.queued.pattern_addr & 0xff00ffff) | (val << 16);
break;
case 0x83:
et4000->acl.queued.pattern_addr = (et4000->acl.queued.pattern_addr & 0x00ffffff) | (val << 24);
break;
case 0x84:
et4000->acl.queued.source_addr = (et4000->acl.queued.source_addr & 0xffffff00) | val;
break;
case 0x85:
et4000->acl.queued.source_addr = (et4000->acl.queued.source_addr & 0xffff00ff) | (val << 8);
break;
case 0x86:
et4000->acl.queued.source_addr = (et4000->acl.queued.source_addr & 0xff00ffff) | (val << 16);
break;
case 0x87:
et4000->acl.queued.source_addr = (et4000->acl.queued.source_addr & 0x00ffffff) | (val << 24);
break;
case 0x88:
et4000->acl.queued.pattern_off = (et4000->acl.queued.pattern_off & 0xff00) | val;
break;
case 0x89:
et4000->acl.queued.pattern_off = (et4000->acl.queued.pattern_off & 0x00ff) | (val << 8);
break;
case 0x8a:
et4000->acl.queued.source_off = (et4000->acl.queued.source_off & 0xff00) | val;
break;
case 0x8b:
et4000->acl.queued.source_off = (et4000->acl.queued.source_off & 0x00ff) | (val << 8);
break;
case 0x8c:
et4000->acl.queued.dest_off = (et4000->acl.queued.dest_off & 0xff00) | val;
break;
case 0x8d:
et4000->acl.queued.dest_off = (et4000->acl.queued.dest_off & 0x00ff) | (val << 8);
break;
case 0x8e:
if (et4000->type >= ET4000W32P_REVC)
et4000->acl.queued.pixel_depth = val & 0x30;
else
et4000->acl.queued.vbus = val & 0x03;
break;
case 0x8f:
if (et4000->type >= ET4000W32P_REVC)
et4000->acl.queued.xy_dir = val & 0xb7;
else
et4000->acl.queued.xy_dir = val & 0x03;
break;
case 0x90:
et4000->acl.queued.pattern_wrap = val & 0x77;
break;
case 0x92:
et4000->acl.queued.source_wrap = val & 0x77;
break;
case 0x98:
et4000->acl.queued.count_x = (et4000->acl.queued.count_x & 0xff00) | val;
break;
case 0x99:
et4000->acl.queued.count_x = (et4000->acl.queued.count_x & 0x00ff) | (val << 8);
break;
case 0x9a:
et4000->acl.queued.count_y = (et4000->acl.queued.count_y & 0xff00) | val;
break;
case 0x9b:
et4000->acl.queued.count_y = (et4000->acl.queued.count_y & 0x00ff) | (val << 8);
break;
case 0x9c:
if (et4000->type >= ET4000W32P_REVC)
et4000->acl.queued.ctrl_routing = val & 0xdb;
else
et4000->acl.queued.ctrl_routing = val & 0xb7;
break;
case 0x9d:
et4000->acl.queued.ctrl_reload = val & 0x03;
break;
case 0x9e:
et4000->acl.queued.rop_bg = val;
break;
case 0x9f:
et4000->acl.queued.rop_fg = val;
break;
case 0xa0:
et4000->acl.queued.dest_addr = (et4000->acl.queued.dest_addr & 0xffffff00) | val;
break;
case 0xa1:
et4000->acl.queued.dest_addr = (et4000->acl.queued.dest_addr & 0xffff00ff) | (val << 8);
break;
case 0xa2:
et4000->acl.queued.dest_addr = (et4000->acl.queued.dest_addr & 0xff00ffff) | (val << 16);
break;
case 0xa3:
et4000->acl.queued.dest_addr = (et4000->acl.queued.dest_addr & 0x00ffffff) | (val << 24);
et4000->acl.internal = et4000->acl.queued;
if (et4000->type >= ET4000W32P_REVC) {
et4000w32p_blit_start(et4000);
et4000w32_log("Destination Address write and start XY Block, xcnt = %i, ycnt = %i\n", et4000->acl.x_count + 1, et4000->acl.y_count + 1);
if (!(et4000->acl.queued.ctrl_routing & 0x43)) {
et4000w32p_blit(0xffffff, ~0, 0, 0, et4000);
}
if ((et4000->acl.queued.ctrl_routing & 0x40) && !(et4000->acl.internal.ctrl_routing & 3)) {
et4000w32p_blit(4, ~0, 0, 0, et4000);
}
} else {
et4000w32_blit_start(et4000);
et4000->acl.cpu_input_num = 0;
if (!(et4000->acl.queued.ctrl_routing & 0x37)) {
et4000->acl.mmu_start = 1;
et4000w32_blit(-1, 0, 0, 0xffffffff, et4000);
} else
et4000->acl.mmu_start = 0;
}
break;
case 0xa4:
et4000->acl.queued.mix_addr = (et4000->acl.queued.mix_addr & 0xFFFFFF00) | val;
break;
case 0xa5:
et4000->acl.queued.mix_addr = (et4000->acl.queued.mix_addr & 0xFFFF00FF) | (val << 8);
break;
case 0xa6:
et4000->acl.queued.mix_addr = (et4000->acl.queued.mix_addr & 0xFF00FFFF) | (val << 16);
break;
case 0xa7:
et4000->acl.queued.mix_addr = (et4000->acl.queued.mix_addr & 0x00FFFFFF) | (val << 24);
break;
case 0xa8:
et4000->acl.queued.mix_off = (et4000->acl.queued.mix_off & 0xFF00) | val;
break;
case 0xa9:
et4000->acl.queued.mix_off = (et4000->acl.queued.mix_off & 0x00FF) | (val << 8);
break;
case 0xaa:
et4000->acl.queued.error = (et4000->acl.queued.error & 0xFF00) | val;
break;
case 0xab:
et4000->acl.queued.error = (et4000->acl.queued.error & 0x00FF) | (val << 8);
break;
case 0xac:
et4000->acl.queued.dmin = (et4000->acl.queued.dmin & 0xFF00) | val;
break;
case 0xad:
et4000->acl.queued.dmin = (et4000->acl.queued.dmin & 0x00FF) | (val << 8);
break;
case 0xae:
et4000->acl.queued.dmaj = (et4000->acl.queued.dmaj & 0xFF00) | val;
break;
case 0xaf:
et4000->acl.queued.dmaj = (et4000->acl.queued.dmaj & 0x00FF) | (val << 8);
break;
default:
break;
}
}
static void
et4000w32p_accel_write_mmu(et4000w32p_t *et4000, uint32_t addr, uint8_t val, uint8_t bank)
{
if (et4000->type >= ET4000W32P_REVC) {
if (!(et4000->acl.status & ACL_XYST)) {
et4000w32_log("XY MMU block not started\n");
return;
}
if (et4000->acl.internal.ctrl_routing & 3) {
et4000->acl.fifo_queue++;
if ((et4000->acl.internal.ctrl_routing & 3) == 2) /*CPU data is Mix data*/
et4000w32p_blit(8 - (et4000->acl.mix_addr & 7), val >> (et4000->acl.mix_addr & 7), 0, 1, et4000);
else if ((et4000->acl.internal.ctrl_routing & 3) == 1) /*CPU data is Source data*/
et4000w32p_blit(1, ~0, val, 2, et4000);
}
} else {
if (!(et4000->acl.status & ACL_XYST)) {
et4000->acl.fifo_queue++;
et4000->acl.queued.dest_addr = ((addr & 0x1fff) + et4000->mmu.base[bank]);
et4000->acl.internal = et4000->acl.queued;
et4000w32_blit_start(et4000);
et4000w32_log("ET4000W32 Accelerated MMU aperture start XY Block (Implicit): bank = %i, patx = %i, paty = %i, wrap x = %i, wrap y = %i\n", et4000->bank, et4000->acl.pattern_x, et4000->acl.pattern_y, et4000w32_wrap_x[et4000->acl.internal.pattern_wrap & 7], et4000w32_wrap_y[(et4000->acl.internal.pattern_wrap >> 4) & 7]);
et4000->acl.cpu_input_num = 0;
if (!(et4000->acl.queued.ctrl_routing & 0x37)) {
et4000->acl.mmu_start = 1;
et4000w32_blit(-1, 0, 0, 0xffffffff, et4000);
} else {
et4000->acl.mmu_start = 0;
}
}
if (et4000->acl.internal.ctrl_routing & 7) {
et4000->acl.fifo_queue++;
et4000->acl.cpu_input = (et4000->acl.cpu_input & ~(0xff << (et4000->acl.cpu_input_num << 3))) | (val << (et4000->acl.cpu_input_num << 3));
et4000->acl.cpu_input_num++;
if (et4000->acl.cpu_input_num == et4000w32_vbus[et4000->acl.internal.vbus]) {
if ((et4000->acl.internal.ctrl_routing & 7) == 2) /*CPU data is Mix data*/
et4000w32_blit(et4000->acl.cpu_input_num << 3, 2, 0, et4000->acl.cpu_input, et4000);
else if ((et4000->acl.internal.ctrl_routing & 7) == 1) /*CPU data is Source data*/
et4000w32_blit(et4000->acl.cpu_input_num, 1, et4000->acl.cpu_input, 0xffffffff, et4000);
et4000->acl.cpu_input_num = 0;
}
if (et4000w32_vbus[et4000->acl.internal.vbus] == 1) {
if ((et4000->acl.internal.ctrl_routing & 7) == 4) { /*CPU data is X Count*/
et4000w32_log("ET4000W32 Accelerated MMU aperture routing = %02x: val = %02x, cx = %02x.\n", et4000->acl.internal.ctrl_routing, val, et4000->acl.internal.count_x);
et4000->acl.cpu_x_cnt = val + 1;
et4000->acl.cpu_x_cnt |= ((et4000->acl.queued.count_x >> 8) << 8);
et4000w32_blit(et4000->acl.cpu_x_cnt, 3, 0, 0xffffffff, et4000);
} else if ((et4000->acl.internal.ctrl_routing & 7) == 5) { /*CPU data is Y Count*/
et4000w32_log("ET4000W32 Accelerated MMU aperture routing = %02x: val = %02x, cy = %02x.\n", et4000->acl.internal.ctrl_routing, val, et4000->acl.internal.count_y);
et4000->acl.cpu_y_cnt = val + 1;
et4000->acl.cpu_y_cnt |= ((et4000->acl.queued.count_y >> 8) << 8);
et4000w32_blit(et4000->acl.cpu_y_cnt, 4, 0, 0xffffffff, et4000);
}
}
}
}
}
static void
et4000w32p_mmu_write(uint32_t addr, uint8_t val, void *priv)
{
et4000w32p_t *et4000 = (et4000w32p_t *) priv;
svga_t *svga = &et4000->svga;
switch (addr & 0x6000) {
case 0x0000: /* MMU 0 */
case 0x2000: /* MMU 1 */
case 0x4000: /* MMU 2 */
et4000->bank = (addr >> 13) & 3;
if (et4000->mmu.ctrl & (1 << et4000->bank)) {
et4000w32p_accel_write_mmu(et4000, addr & 0x7fff, val, et4000->bank);
} else {
if (((addr & 0x1fff) + et4000->mmu.base[et4000->bank]) < svga->vram_max) {
svga->vram[((addr & 0x1fff) + et4000->mmu.base[et4000->bank]) & et4000->vram_mask] = val;
svga->changedvram[(((addr & 0x1fff) + et4000->mmu.base[et4000->bank]) & et4000->vram_mask) >> 12] = changeframecount;
}
}
break;
case 0x6000:
if ((addr & 0xff) >= 0x80) {
et4000w32p_accel_write_fifo(et4000, addr & 0x7fff, val);
} else {
switch (addr & 0xff) {
case 0x00:
et4000->mmu.base[0] = (et4000->mmu.base[0] & 0xffffff00) | val;
break;
case 0x01:
et4000->mmu.base[0] = (et4000->mmu.base[0] & 0xffff00ff) | (val << 8);
break;
case 0x02:
et4000->mmu.base[0] = (et4000->mmu.base[0] & 0xff00ffff) | (val << 16);
break;
case 0x03:
et4000->mmu.base[0] = (et4000->mmu.base[0] & 0x00ffffff) | (val << 24);
break;
case 0x04:
et4000->mmu.base[1] = (et4000->mmu.base[1] & 0xffffff00) | val;
break;
case 0x05:
et4000->mmu.base[1] = (et4000->mmu.base[1] & 0xffff00ff) | (val << 8);
break;
case 0x06:
et4000->mmu.base[1] = (et4000->mmu.base[1] & 0xff00ffff) | (val << 16);
break;
case 0x07:
et4000->mmu.base[1] = (et4000->mmu.base[1] & 0x00ffffff) | (val << 24);
break;
case 0x08:
et4000->mmu.base[2] = (et4000->mmu.base[2] & 0xffffff00) | val;
break;
case 0x09:
et4000->mmu.base[2] = (et4000->mmu.base[2] & 0xffff00ff) | (val << 8);
break;
case 0x0a:
et4000->mmu.base[2] = (et4000->mmu.base[2] & 0xff00ffff) | (val << 16);
break;
case 0x0b:
et4000->mmu.base[2] = (et4000->mmu.base[2] & 0x00ffffff) | (val << 24);
break;
case 0x13:
et4000->mmu.ctrl = val;
break;
case 0x30:
et4000->acl.suspend_terminate = val;
break;
case 0x31:
et4000->acl.osr = val;
break;
default:
break;
}
}
break;
default:
break;
}
}
static uint8_t
et4000w32p_mmu_read(uint32_t addr, void *priv)
{
et4000w32p_t *et4000 = (et4000w32p_t *) priv;
const svga_t *svga = &et4000->svga;
uint8_t temp;
switch (addr & 0x6000) {
case 0x0000: /* MMU 0 */
case 0x2000: /* MMU 1 */
case 0x4000: /* MMU 2 */
et4000->bank = (addr >> 13) & 3;
if (et4000->mmu.ctrl & (1 << et4000->bank)) {
temp = 0xff;
if (et4000->acl.cpu_dat_pos) {
et4000->acl.cpu_dat_pos--;
temp = et4000->acl.cpu_dat & 0xff;
et4000->acl.cpu_dat >>= 8;
}
if ((et4000->acl.queued.ctrl_routing & 0x40) && !et4000->acl.cpu_dat_pos && !(et4000->acl.internal.ctrl_routing & 3))
et4000w32p_blit(4, ~0, 0, 0, et4000);
/* ???? */
return temp;
}
if ((addr & 0x1fff) + et4000->mmu.base[et4000->bank] >= svga->vram_max)
return 0xff;
return svga->vram[(addr & 0x1fff) + et4000->mmu.base[et4000->bank]];
case 0x6000:
switch (addr & 0xff) {
case 0x00:
return et4000->mmu.base[0] & 0xff;
case 0x01:
return et4000->mmu.base[0] >> 8;
case 0x02:
return et4000->mmu.base[0] >> 16;
case 0x03:
return et4000->mmu.base[0] >> 24;
case 0x04:
return et4000->mmu.base[1] & 0xff;
case 0x05:
return et4000->mmu.base[1] >> 8;
case 0x06:
return et4000->mmu.base[1] >> 16;
case 0x07:
return et4000->mmu.base[1] >> 24;
case 0x08:
return et4000->mmu.base[2] & 0xff;
case 0x09:
return et4000->mmu.base[2] >> 8;
case 0x0a:
return et4000->mmu.base[2] >> 16;
case 0x0b:
return et4000->mmu.base[2] >> 24;
case 0x13:
return et4000->mmu.ctrl;
case 0x36:
if (et4000->acl.fifo_queue) {
et4000->acl.status |= ACL_RDST;
et4000->acl.fifo_queue = 0;
} else
et4000->acl.status &= ~ACL_RDST;
return et4000->acl.status;
case 0x80:
return et4000->acl.internal.pattern_addr & 0xff;
case 0x81:
return et4000->acl.internal.pattern_addr >> 8;
case 0x82:
return et4000->acl.internal.pattern_addr >> 16;
case 0x83:
return et4000->acl.internal.pattern_addr >> 24;
case 0x84:
return et4000->acl.internal.source_addr & 0xff;
case 0x85:
return et4000->acl.internal.source_addr >> 8;
case 0x86:
return et4000->acl.internal.source_addr >> 16;
case 0x87:
return et4000->acl.internal.source_addr >> 24;
case 0x88:
return et4000->acl.internal.pattern_off & 0xff;
case 0x89:
return et4000->acl.internal.pattern_off >> 8;
case 0x8a:
return et4000->acl.internal.source_off & 0xff;
case 0x8b:
return et4000->acl.internal.source_off >> 8;
case 0x8c:
return et4000->acl.internal.dest_off & 0xff;
case 0x8d:
return et4000->acl.internal.dest_off >> 8;
case 0x8e:
if (et4000->type >= ET4000W32P_REVC)
return et4000->acl.internal.pixel_depth;
return et4000->acl.internal.vbus;
case 0x8f:
return et4000->acl.internal.xy_dir;
case 0x90:
return et4000->acl.internal.pattern_wrap;
case 0x92:
return et4000->acl.internal.source_wrap;
case 0x98:
return et4000->acl.internal.count_x & 0xff;
case 0x99:
return et4000->acl.internal.count_x >> 8;
case 0x9a:
return et4000->acl.internal.count_y & 0xff;
case 0x9b:
return et4000->acl.internal.count_y >> 8;
case 0x9c:
return et4000->acl.internal.ctrl_routing;
case 0x9d:
return et4000->acl.internal.ctrl_reload;
case 0x9e:
return et4000->acl.internal.rop_bg;
case 0x9f:
return et4000->acl.internal.rop_fg;
case 0xa0:
return et4000->acl.internal.dest_addr & 0xff;
case 0xa1:
return et4000->acl.internal.dest_addr >> 8;
case 0xa2:
return et4000->acl.internal.dest_addr >> 16;
case 0xa3:
return et4000->acl.internal.dest_addr >> 24;
default:
break;
}
return 0xff;
default:
break;
}
return 0xff;
}
void
et4000w32_blit_start(et4000w32p_t *et4000)
{
et4000->acl.x_count = et4000->acl.internal.count_x;
et4000->acl.y_count = et4000->acl.internal.count_y;
et4000->acl.pattern_addr = et4000->acl.internal.pattern_addr;
et4000->acl.source_addr = et4000->acl.internal.source_addr;
et4000->acl.dest_addr = et4000->acl.internal.dest_addr;
et4000->acl.dest_back = et4000->acl.dest_addr;
et4000->acl.pattern_x = et4000->acl.source_x = et4000->acl.pattern_y = et4000->acl.source_y = 0;
et4000->acl.status |= ACL_XYST;
et4000->acl.status &= ~ACL_SSO;
if (!(et4000->acl.internal.ctrl_routing & 7) || (et4000->acl.internal.ctrl_routing & 4))
et4000->acl.status |= ACL_SSO;
if (et4000w32_wrap_x[et4000->acl.internal.pattern_wrap & 7]) {
et4000->acl.pattern_x = et4000->acl.pattern_addr & et4000w32_wrap_x[et4000->acl.internal.pattern_wrap & 7];
et4000->acl.pattern_addr &= ~et4000w32_wrap_x[et4000->acl.internal.pattern_wrap & 7];
}
et4000->acl.pattern_back = et4000->acl.pattern_addr;
if (!(et4000->acl.internal.pattern_wrap & 0x40)) {
if ((et4000w32_wrap_x[et4000->acl.internal.pattern_wrap & 7] + 1) == 0x00) { /*This is to avoid a division by zero crash*/
et4000->acl.pattern_y = (et4000->acl.pattern_addr / (0x7f + 1)) & (et4000w32_wrap_y[(et4000->acl.internal.pattern_wrap >> 4) & 7] - 1);
} else
et4000->acl.pattern_y = (et4000->acl.pattern_addr / (et4000w32_wrap_x[et4000->acl.internal.pattern_wrap & 7] + 1)) & (et4000w32_wrap_y[(et4000->acl.internal.pattern_wrap >> 4) & 7] - 1);
et4000->acl.pattern_back &= ~(((et4000w32_wrap_x[et4000->acl.internal.pattern_wrap & 7] + 1) * et4000w32_wrap_y[(et4000->acl.internal.pattern_wrap >> 4) & 7]) - 1);
}
et4000->acl.pattern_x_back = et4000->acl.pattern_x;
if (et4000w32_wrap_x[et4000->acl.internal.source_wrap & 7]) {
et4000->acl.source_x = et4000->acl.source_addr & et4000w32_wrap_x[et4000->acl.internal.source_wrap & 7];
et4000->acl.source_addr &= ~et4000w32_wrap_x[et4000->acl.internal.source_wrap & 7];
}
et4000->acl.source_back = et4000->acl.source_addr;
if (!(et4000->acl.internal.source_wrap & 0x40)) {
if ((et4000w32_wrap_x[et4000->acl.internal.source_wrap & 7] + 1) == 0x00) { /*This is to avoid a division by zero crash*/
et4000->acl.source_y = (et4000->acl.source_addr / (0x7f + 1)) & (et4000w32_wrap_y[(et4000->acl.internal.source_wrap >> 4) & 7] - 1);
} else
et4000->acl.source_y = (et4000->acl.source_addr / (et4000w32_wrap_x[et4000->acl.internal.source_wrap & 7] + 1)) & (et4000w32_wrap_y[(et4000->acl.internal.source_wrap >> 4) & 7] - 1);
et4000->acl.source_back &= ~(((et4000w32_wrap_x[et4000->acl.internal.source_wrap & 7] + 1) * et4000w32_wrap_y[(et4000->acl.internal.source_wrap >> 4) & 7]) - 1);
}
et4000->acl.source_x_back = et4000->acl.source_x;
if ((et4000w32_wrap_x[et4000->acl.internal.pattern_wrap & 7] == 7) && !(et4000->acl.internal.ctrl_routing & 0x37) && (et4000->acl.internal.rop_fg == 0x5a)) {
if ((et4000->acl.internal.count_y > 0) && (et4000->acl.pattern_y > 0)) {
if (et4000->acl.pattern_addr == et4000->acl.pattern_back)
et4000->acl.pattern_y = 0;
else {
et4000->acl.pattern_y = (et4000->acl.pattern_addr - et4000->acl.pattern_back) & 0x70;
et4000->acl.pattern_y >>= 4;
}
}
} else if ((et4000w32_wrap_x[et4000->acl.internal.pattern_wrap & 7] == 15) && !(et4000->acl.internal.ctrl_routing & 0x37) && (et4000->acl.internal.rop_fg == 0x5a)) {
if ((et4000->acl.internal.count_y > 0) && (et4000->acl.pattern_y > 0)) {
if (et4000->acl.pattern_addr == et4000->acl.pattern_back)
et4000->acl.pattern_y = 0;
else {
et4000->acl.pattern_y = (et4000->acl.pattern_addr - et4000->acl.pattern_back) & 0xf0;
et4000->acl.pattern_y >>= 5;
}
}
}
}
static void
et4000w32p_blit_start(et4000w32p_t *et4000)
{
et4000->acl.x_count = et4000->acl.internal.count_x;
et4000->acl.y_count = et4000->acl.internal.count_y;
if (!(et4000->acl.queued.xy_dir & 0x20))
et4000->acl.internal.error = et4000->acl.internal.dmaj / 2;
et4000->acl.pattern_addr = et4000->acl.internal.pattern_addr;
et4000->acl.source_addr = et4000->acl.internal.source_addr;
et4000->acl.mix_addr = et4000->acl.internal.mix_addr;
et4000->acl.mix_back = et4000->acl.mix_addr;
et4000->acl.dest_addr = et4000->acl.internal.dest_addr;
et4000->acl.dest_back = et4000->acl.dest_addr;
et4000->acl.internal.pos_x = et4000->acl.internal.pos_y = 0;
et4000->acl.pattern_x = et4000->acl.source_x = et4000->acl.pattern_y = et4000->acl.source_y = 0;
et4000->acl.status |= ACL_XYST;
et4000w32_log("ACL status XYST set\n");
if ((!(et4000->acl.internal.ctrl_routing & 7) || (et4000->acl.internal.ctrl_routing & 4)) && !(et4000->acl.internal.ctrl_routing & 0x40))
et4000->acl.status |= ACL_SSO;
if (et4000w32_wrap_x[et4000->acl.internal.pattern_wrap & 7]) {
et4000->acl.pattern_x = et4000->acl.pattern_addr & et4000w32_wrap_x[et4000->acl.internal.pattern_wrap & 7];
et4000->acl.pattern_addr &= ~et4000w32_wrap_x[et4000->acl.internal.pattern_wrap & 7];
}
et4000->acl.pattern_back = et4000->acl.pattern_addr;
if (!(et4000->acl.internal.pattern_wrap & 0x40)) {
et4000->acl.pattern_y = (et4000->acl.pattern_addr / (et4000w32_wrap_x[et4000->acl.internal.pattern_wrap & 7] + 1)) & (et4000w32_wrap_y[(et4000->acl.internal.pattern_wrap >> 4) & 7] - 1);
et4000->acl.pattern_back &= ~(((et4000w32_wrap_x[et4000->acl.internal.pattern_wrap & 7] + 1) * et4000w32_wrap_y[(et4000->acl.internal.pattern_wrap >> 4) & 7]) - 1);
}
et4000->acl.pattern_x_back = et4000->acl.pattern_x;
if (et4000w32_wrap_x[et4000->acl.internal.source_wrap & 7]) {
et4000->acl.source_x = et4000->acl.source_addr & et4000w32_wrap_x[et4000->acl.internal.source_wrap & 7];
et4000->acl.source_addr &= ~et4000w32_wrap_x[et4000->acl.internal.source_wrap & 7];
}
et4000->acl.source_back = et4000->acl.source_addr;
if (!(et4000->acl.internal.source_wrap & 0x40)) {
et4000->acl.source_y = (et4000->acl.source_addr / (et4000w32_wrap_x[et4000->acl.internal.source_wrap & 7] + 1)) & (et4000w32_wrap_y[(et4000->acl.internal.source_wrap >> 4) & 7] - 1);
et4000->acl.source_back &= ~(((et4000w32_wrap_x[et4000->acl.internal.source_wrap & 7] + 1) * et4000w32_wrap_y[(et4000->acl.internal.source_wrap >> 4) & 7]) - 1);
}
et4000->acl.source_x_back = et4000->acl.source_x;
et4000w32_max_x[2] = (et4000->acl.internal.pixel_depth == 0x20) ? 3 : 4;
et4000->acl.internal.count_x += (et4000->acl.internal.pixel_depth >> 4) & 3;
et4000->acl.cpu_dat_pos = 0;
et4000->acl.cpu_dat = 0;
et4000->acl.pix_pos = 0;
}
void
et4000w32_incx(int c, et4000w32p_t *et4000)
{
et4000->acl.dest_addr += c;
et4000->acl.pattern_x += c;
et4000->acl.source_x += c;
et4000->acl.mix_addr += c;
if (et4000->acl.pattern_x >= et4000w32_max_x[et4000->acl.internal.pattern_wrap & 7])
et4000->acl.pattern_x -= et4000w32_max_x[et4000->acl.internal.pattern_wrap & 7];
if (et4000->acl.source_x >= et4000w32_max_x[et4000->acl.internal.source_wrap & 7])
et4000->acl.source_x -= et4000w32_max_x[et4000->acl.internal.source_wrap & 7];
}
void
et4000w32_decx(int c, et4000w32p_t *et4000)
{
et4000->acl.dest_addr -= c;
et4000->acl.pattern_x -= c;
et4000->acl.source_x -= c;
et4000->acl.mix_addr -= c;
if (et4000->acl.pattern_x < 0)
et4000->acl.pattern_x += et4000w32_max_x[et4000->acl.internal.pattern_wrap & 7];
if (et4000->acl.source_x < 0)
et4000->acl.source_x += et4000w32_max_x[et4000->acl.internal.source_wrap & 7];
}
void
et4000w32_incy(et4000w32p_t *et4000)
{
et4000->acl.pattern_addr += et4000->acl.internal.pattern_off + 1;
et4000->acl.source_addr += et4000->acl.internal.source_off + 1;
et4000->acl.mix_addr += et4000->acl.internal.mix_off + 1;
et4000->acl.dest_addr += et4000->acl.internal.dest_off + 1;
et4000->acl.pattern_y++;
if (et4000->acl.pattern_y == et4000w32_wrap_y[(et4000->acl.internal.pattern_wrap >> 4) & 7]) {
et4000->acl.pattern_y = 0;
et4000->acl.pattern_addr = et4000->acl.pattern_back;
}
et4000->acl.source_y++;
if (et4000->acl.source_y == et4000w32_wrap_y[(et4000->acl.internal.source_wrap >> 4) & 7]) {
et4000->acl.source_y = 0;
et4000->acl.source_addr = et4000->acl.source_back;
}
}
void
et4000w32_decy(et4000w32p_t *et4000)
{
et4000->acl.pattern_addr -= et4000->acl.internal.pattern_off + 1;
et4000->acl.source_addr -= et4000->acl.internal.source_off + 1;
et4000->acl.mix_addr -= et4000->acl.internal.mix_off + 1;
et4000->acl.dest_addr -= et4000->acl.internal.dest_off + 1;
et4000->acl.pattern_y--;
if ((et4000->acl.pattern_y < 0) && !(et4000->acl.internal.pattern_wrap & 0x40)) {
et4000->acl.pattern_y = et4000w32_wrap_y[(et4000->acl.internal.pattern_wrap >> 4) & 7] - 1;
et4000->acl.pattern_addr = et4000->acl.pattern_back + (et4000w32_wrap_x[et4000->acl.internal.pattern_wrap & 7] * (et4000w32_wrap_y[(et4000->acl.internal.pattern_wrap >> 4) & 7] - 1));
}
et4000->acl.source_y--;
if ((et4000->acl.source_y < 0) && !(et4000->acl.internal.source_wrap & 0x40)) {
et4000->acl.source_y = et4000w32_wrap_y[(et4000->acl.internal.source_wrap >> 4) & 7] - 1;
et4000->acl.source_addr = et4000->acl.source_back + (et4000w32_wrap_x[et4000->acl.internal.source_wrap & 7] * (et4000w32_wrap_y[(et4000->acl.internal.source_wrap >> 4) & 7] - 1));
}
}
#define ROPMIX(R, D, P, S, out) \
{ \
switch (R) { \
case 0x00: \
out = 0; \
break; \
case 0x01: \
out = ~(D | (P | S)); \
break; \
case 0x02: \
out = D & ~(P | S); \
break; \
case 0x03: \
out = ~(P | S); \
break; \
case 0x04: \
out = S & ~(D | P); \
break; \
case 0x05: \
out = ~(D | P); \
break; \
case 0x06: \
out = ~(P | ~(D ^ S)); \
break; \
case 0x07: \
out = ~(P | (D & S)); \
break; \
case 0x08: \
out = S & (D & ~P); \
break; \
case 0x09: \
out = ~(P | (D ^ S)); \
break; \
case 0x0a: \
out = D & ~P; \
break; \
case 0x0b: \
out = ~(P | (S & ~D)); \
break; \
case 0x0c: \
out = S & ~P; \
break; \
case 0x0d: \
out = ~(P | (D & ~S)); \
break; \
case 0x0e: \
out = ~(P | ~(D | S)); \
break; \
case 0x0f: \
out = ~P; \
break; \
case 0x10: \
out = P & ~(D | S); \
break; \
case 0x11: \
out = ~(D | S); \
break; \
case 0x12: \
out = ~(S | ~(D ^ P)); \
break; \
case 0x13: \
out = ~(S | (D & P)); \
break; \
case 0x14: \
out = ~(D | ~(P ^ S)); \
break; \
case 0x15: \
out = ~(D | (P & S)); \
break; \
case 0x16: \
out = P ^ (S ^ (D & ~(P & S))); \
break; \
case 0x17: \
out = ~(S ^ ((S ^ P) & (D ^ S))); \
break; \
case 0x18: \
out = (S ^ P) & (P ^ D); \
break; \
case 0x19: \
out = ~(S ^ (D & ~(P & S))); \
break; \
case 0x1a: \
out = P ^ (D | (S & P)); \
break; \
case 0x1b: \
out = ~(S ^ (D & (P ^ S))); \
break; \
case 0x1c: \
out = P ^ (S | (D & P)); \
break; \
case 0x1d: \
out = ~(D ^ (S & (P ^ D))); \
break; \
case 0x1e: \
out = P ^ (D | S); \
break; \
case 0x1f: \
out = ~(P & (D | S)); \
break; \
case 0x20: \
out = D & (P & ~S); \
break; \
case 0x21: \
out = ~(S | (D ^ P)); \
break; \
case 0x22: \
out = D & ~S; \
break; \
case 0x23: \
out = ~(S | (P & ~D)); \
break; \
case 0x24: \
out = (S ^ P) & (D ^ S); \
break; \
case 0x25: \
out = ~(P ^ (D & ~(S & P))); \
break; \
case 0x26: \
out = S ^ (D | (P & S)); \
break; \
case 0x27: \
out = S ^ (D | ~(P ^ S)); \
break; \
case 0x28: \
out = D & (P ^ S); \
break; \
case 0x29: \
out = ~(P ^ (S ^ (D | (P & S)))); \
break; \
case 0x2a: \
out = D & ~(P & S); \
break; \
case 0x2b: \
out = ~(S ^ ((S ^ P) & (P ^ D))); \
break; \
case 0x2c: \
out = S ^ (P & (D | S)); \
break; \
case 0x2d: \
out = P ^ (S | ~D); \
break; \
case 0x2e: \
out = P ^ (S | (D ^ P)); \
break; \
case 0x2f: \
out = ~(P & (S | ~D)); \
break; \
case 0x30: \
out = P & ~S; \
break; \
case 0x31: \
out = ~(S | (D & ~P)); \
break; \
case 0x32: \
out = S ^ (D | (P | S)); \
break; \
case 0x33: \
out = ~S; \
break; \
case 0x34: \
out = S ^ (P | (D & S)); \
break; \
case 0x35: \
out = S ^ (P | ~(D ^ S)); \
break; \
case 0x36: \
out = S ^ (D | P); \
break; \
case 0x37: \
out = ~(S & (D | P)); \
break; \
case 0x38: \
out = P ^ (S & (D | P)); \
break; \
case 0x39: \
out = S ^ (P | ~D); \
break; \
case 0x3a: \
out = S ^ (P | (D ^ S)); \
break; \
case 0x3b: \
out = ~(S & (P | ~D)); \
break; \
case 0x3c: \
out = P ^ S; \
break; \
case 0x3d: \
out = S ^ (P | ~(D | S)); \
break; \
case 0x3e: \
out = S ^ (P | (D & ~S)); \
break; \
case 0x3f: \
out = ~(P & S); \
break; \
case 0x40: \
out = P & (S & ~D); \
break; \
case 0x41: \
out = ~(D | (P ^ S)); \
break; \
case 0x42: \
out = (S ^ D) & (P ^ D); \
break; \
case 0x43: \
out = ~(S ^ (P & ~(D & S))); \
break; \
case 0x44: \
out = S & ~D; \
break; \
case 0x45: \
out = ~(D | (P & ~S)); \
break; \
case 0x46: \
out = D ^ (S | (P & D)); \
break; \
case 0x47: \
out = ~(P ^ (S & (D ^ P))); \
break; \
case 0x48: \
out = S & (D ^ P); \
break; \
case 0x49: \
out = ~(P ^ (D ^ (S | (P & D)))); \
break; \
case 0x4a: \
out = D ^ (P & (S | D)); \
break; \
case 0x4b: \
out = P ^ (D | ~S); \
break; \
case 0x4c: \
out = S & ~(D & P); \
break; \
case 0x4d: \
out = ~(S ^ ((S ^ P) | (D ^ S))); \
break; \
case 0x4e: \
out = P ^ (D | (S ^ P)); \
break; \
case 0x4f: \
out = ~(P & (D | ~S)); \
break; \
case 0x50: \
out = P & ~D; \
break; \
case 0x51: \
out = ~(D | (S & ~P)); \
break; \
case 0x52: \
out = D ^ (P | (S & D)); \
break; \
case 0x53: \
out = ~(S ^ (P & (D ^ S))); \
break; \
case 0x54: \
out = ~(D | ~(P | S)); \
break; \
case 0x55: \
out = ~D; \
break; \
case 0x56: \
out = D ^ (P | S); \
break; \
case 0x57: \
out = ~(D & (P | S)); \
break; \
case 0x58: \
out = P ^ (D & (S | P)); \
break; \
case 0x59: \
out = D ^ (P | ~S); \
break; \
case 0x5a: \
out = D ^ P; \
break; \
case 0x5b: \
out = D ^ (P | ~(S | D)); \
break; \
case 0x5c: \
out = D ^ (P | (S ^ D)); \
break; \
case 0x5d: \
out = ~(D & (P | ~S)); \
break; \
case 0x5e: \
out = D ^ (P | (S & ~D)); \
break; \
case 0x5f: \
out = ~(D & P); \
break; \
case 0x60: \
out = P & (D ^ S); \
break; \
case 0x61: \
out = ~(D ^ (S ^ (P | (D & S)))); \
break; \
case 0x62: \
out = D ^ (S & (P | D)); \
break; \
case 0x63: \
out = S ^ (D | ~P); \
break; \
case 0x64: \
out = S ^ (D & (P | S)); \
break; \
case 0x65: \
out = D ^ (S | ~P); \
break; \
case 0x66: \
out = D ^ S; \
break; \
case 0x67: \
out = S ^ (D | ~(P | S)); \
break; \
case 0x68: \
out = ~(D ^ (S ^ (P | ~(D | S)))); \
break; \
case 0x69: \
out = ~(P ^ (D ^ S)); \
break; \
case 0x6a: \
out = D ^ (P & S); \
break; \
case 0x6b: \
out = ~(P ^ (S ^ (D & (P | S)))); \
break; \
case 0x6c: \
out = S ^ (D & P); \
break; \
case 0x6d: \
out = ~(P ^ (D ^ (S & (P | D)))); \
break; \
case 0x6e: \
out = S ^ (D & (P | ~S)); \
break; \
case 0x6f: \
out = ~(P & ~(D ^ S)); \
break; \
case 0x70: \
out = P & ~(D & S); \
break; \
case 0x71: \
out = ~(S ^ ((S ^ D) & (P ^ D))); \
break; \
case 0x72: \
out = S ^ (D | (P ^ S)); \
break; \
case 0x73: \
out = ~(S & (D | ~P)); \
break; \
case 0x74: \
out = D ^ (S | (P ^ D)); \
break; \
case 0x75: \
out = ~(D & (S | ~P)); \
break; \
case 0x76: \
out = S ^ (D | (P & ~S)); \
break; \
case 0x77: \
out = ~(D & S); \
break; \
case 0x78: \
out = P ^ (D & S); \
break; \
case 0x79: \
out = ~(D ^ (S ^ (P & (D | S)))); \
break; \
case 0x7a: \
out = D ^ (P & (S | ~D)); \
break; \
case 0x7b: \
out = ~(S & ~(D ^ P)); \
break; \
case 0x7c: \
out = S ^ (P & (D | ~S)); \
break; \
case 0x7d: \
out = ~(D & ~(P ^ S)); \
break; \
case 0x7e: \
out = (S ^ P) | (D ^ S); \
break; \
case 0x7f: \
out = ~(D & (P & S)); \
break; \
case 0x80: \
out = D & (P & S); \
break; \
case 0x81: \
out = ~((S ^ P) | (D ^ S)); \
break; \
case 0x82: \
out = D & ~(P ^ S); \
break; \
case 0x83: \
out = ~(S ^ (P & (D | ~S))); \
break; \
case 0x84: \
out = S & ~(D ^ P); \
break; \
case 0x85: \
out = ~(P ^ (D & (S | ~P))); \
break; \
case 0x86: \
out = D ^ (S ^ (P & (D | S))); \
break; \
case 0x87: \
out = ~(P ^ (D & S)); \
break; \
case 0x88: \
out = D & S; \
break; \
case 0x89: \
out = ~(S ^ (D | (P & ~S))); \
break; \
case 0x8a: \
out = D & (S | ~P); \
break; \
case 0x8b: \
out = ~(D ^ (S | (P ^ D))); \
break; \
case 0x8c: \
out = S & (D | ~P); \
break; \
case 0x8d: \
out = ~(S ^ (D | (P ^ S))); \
break; \
case 0x8e: \
out = S ^ ((S ^ D) & (P ^ D)); \
break; \
case 0x8f: \
out = ~(P & ~(D & S)); \
break; \
case 0x90: \
out = P & ~(D ^ S); \
break; \
case 0x91: \
out = ~(S ^ (D & (P | ~S))); \
break; \
case 0x92: \
out = D ^ (P ^ (S & (D | P))); \
break; \
case 0x93: \
out = ~(S ^ (P & D)); \
break; \
case 0x94: \
out = P ^ (S ^ (D & (P | S))); \
break; \
case 0x95: \
out = ~(D ^ (P & S)); \
break; \
case 0x96: \
out = D ^ (P ^ S); \
break; \
case 0x97: \
out = P ^ (S ^ (D | ~(P | S))); \
break; \
case 0x98: \
out = ~(S ^ (D | ~(P | S))); \
break; \
case 0x99: \
out = ~(D ^ S); \
break; \
case 0x9a: \
out = D ^ (P & ~S); \
break; \
case 0x9b: \
out = ~(S ^ (D & (P | S))); \
break; \
case 0x9c: \
out = S ^ (P & ~D); \
break; \
case 0x9d: \
out = ~(D ^ (S & (P | D))); \
break; \
case 0x9e: \
out = D ^ (S ^ (P | (D & S))); \
break; \
case 0x9f: \
out = ~(P & (D ^ S)); \
break; \
case 0xa0: \
out = D & P; \
break; \
case 0xa1: \
out = ~(P ^ (D | (S & ~P))); \
break; \
case 0xa2: \
out = D & (P | ~S); \
break; \
case 0xa3: \
out = ~(D ^ (P | (S ^ D))); \
break; \
case 0xa4: \
out = ~(P ^ (D | ~(S | P))); \
break; \
case 0xa5: \
out = ~(P ^ D); \
break; \
case 0xa6: \
out = D ^ (S & ~P); \
break; \
case 0xa7: \
out = ~(P ^ (D & (S | P))); \
break; \
case 0xa8: \
out = D & (P | S); \
break; \
case 0xa9: \
out = ~(D ^ (P | S)); \
break; \
case 0xaa: \
out = D; \
break; \
case 0xab: \
out = D | ~(P | S); \
break; \
case 0xac: \
out = S ^ (P & (D ^ S)); \
break; \
case 0xad: \
out = ~(D ^ (P | (S & D))); \
break; \
case 0xae: \
out = D | (S & ~P); \
break; \
case 0xaf: \
out = D | ~P; \
break; \
case 0xb0: \
out = P & (D | ~S); \
break; \
case 0xb1: \
out = ~(P ^ (D | (S ^ P))); \
break; \
case 0xb2: \
out = S ^ ((S ^ P) | (D ^ S)); \
break; \
case 0xb3: \
out = ~(S & ~(D & P)); \
break; \
case 0xb4: \
out = P ^ (S & ~D); \
break; \
case 0xb5: \
out = ~(D ^ (P & (S | D))); \
break; \
case 0xb6: \
out = D ^ (P ^ (S | (D & P))); \
break; \
case 0xb7: \
out = ~(S & (D ^ P)); \
break; \
case 0xb8: \
out = P ^ (S & (D ^ P)); \
break; \
case 0xb9: \
out = ~(D ^ (S | (P & D))); \
break; \
case 0xba: \
out = D | (P & ~S); \
break; \
case 0xbb: \
out = D | ~S; \
break; \
case 0xbc: \
out = S ^ (P & ~(D & S)); \
break; \
case 0xbd: \
out = ~((S ^ D) & (P ^ D)); \
break; \
case 0xbe: \
out = D | (P ^ S); \
break; \
case 0xbf: \
out = D | ~(P & S); \
break; \
case 0xc0: \
out = P & S; \
break; \
case 0xc1: \
out = ~(S ^ (P | (D & ~S))); \
break; \
case 0xc2: \
out = ~(S ^ (P | ~(D | S))); \
break; \
case 0xc3: \
out = ~(P ^ S); \
break; \
case 0xc4: \
out = S & (P | ~D); \
break; \
case 0xc5: \
out = ~(S ^ (P | (D ^ S))); \
break; \
case 0xc6: \
out = S ^ (D & ~P); \
break; \
case 0xc7: \
out = ~(P ^ (S & (D | P))); \
break; \
case 0xc8: \
out = S & (D | P); \
break; \
case 0xc9: \
out = ~(S ^ (P | D)); \
break; \
case 0xca: \
out = D ^ (P & (S ^ D)); \
break; \
case 0xcb: \
out = ~(S ^ (P | (D & S))); \
break; \
case 0xcc: \
out = S; \
break; \
case 0xcd: \
out = S | ~(D | P); \
break; \
case 0xce: \
out = S | (D & ~P); \
break; \
case 0xcf: \
out = S | ~P; \
break; \
case 0xd0: \
out = P & (S | ~D); \
break; \
case 0xd1: \
out = ~(P ^ (S | (D ^ P))); \
break; \
case 0xd2: \
out = P ^ (D & ~S); \
break; \
case 0xd3: \
out = ~(S ^ (P & (D | S))); \
break; \
case 0xd4: \
out = S ^ ((S ^ P) & (P ^ D)); \
break; \
case 0xd5: \
out = ~(D & ~(P & S)); \
break; \
case 0xd6: \
out = P ^ (S ^ (D | (P & S))); \
break; \
case 0xd7: \
out = ~(D & (P ^ S)); \
break; \
case 0xd8: \
out = P ^ (D & (S ^ P)); \
break; \
case 0xd9: \
out = ~(S ^ (D | (P & S))); \
break; \
case 0xda: \
out = D ^ (P & ~(S & D)); \
break; \
case 0xdb: \
out = ~((S ^ P) & (D ^ S)); \
break; \
case 0xdc: \
out = S | (P & ~D); \
break; \
case 0xdd: \
out = S | ~D; \
break; \
case 0xde: \
out = S | (D ^ P); \
break; \
case 0xdf: \
out = S | ~(D & P); \
break; \
case 0xe0: \
out = P & (D | S); \
break; \
case 0xe1: \
out = ~(P ^ (D | S)); \
break; \
case 0xe2: \
out = D ^ (S & (P ^ D)); \
break; \
case 0xe3: \
out = ~(P ^ (S | (D & P))); \
break; \
case 0xe4: \
out = S ^ (D & (P ^ S)); \
break; \
case 0xe5: \
out = ~(P ^ (D | (S & P))); \
break; \
case 0xe6: \
out = S ^ (D & ~(P & S)); \
break; \
case 0xe7: \
out = ~((S ^ P) & (P ^ D)); \
break; \
case 0xe8: \
out = S ^ ((S ^ P) & (D ^ S)); \
break; \
case 0xe9: \
out = ~(D ^ (S ^ (P & ~(D & S)))); \
break; \
case 0xea: \
out = D | (P & S); \
break; \
case 0xeb: \
out = D | ~(P ^ S); \
break; \
case 0xec: \
out = S | (D & P); \
break; \
case 0xed: \
out = S | ~(D ^ P); \
break; \
case 0xee: \
out = D | S; \
break; \
case 0xef: \
out = S | (D | ~P); \
break; \
case 0xf0: \
out = P; \
break; \
case 0xf1: \
out = P | ~(D | S); \
break; \
case 0xf2: \
out = P | (D & ~S); \
break; \
case 0xf3: \
out = P | ~S; \
break; \
case 0xf4: \
out = P | (S & ~D); \
break; \
case 0xf5: \
out = P | ~D; \
break; \
case 0xf6: \
out = P | (D ^ S); \
break; \
case 0xf7: \
out = P | ~(D & S); \
break; \
case 0xf8: \
out = P | (D & S); \
break; \
case 0xf9: \
out = P | ~(D ^ S); \
break; \
case 0xfa: \
out = D | P; \
break; \
case 0xfb: \
out = D | (P | ~S); \
break; \
case 0xfc: \
out = P | S; \
break; \
case 0xfd: \
out = P | (S | ~D); \
break; \
case 0xfe: \
out = D | (P | S); \
break; \
case 0xff: \
out = ~0; \
break; \
} \
}
static void
et4000w32_blit(int count, int cpu_input, uint32_t src_dat, uint32_t mix_dat, et4000w32p_t *et4000)
{
svga_t *svga = &et4000->svga;
uint8_t pattern;
uint8_t source;
uint8_t dest;
uint8_t rop;
uint8_t out = 0;
int mixmap;
if (!(et4000->acl.status & ACL_XYST) && !et4000->acl.mmu_start) {
et4000w32_log("XY Block not started\n");
return;
}
if (cpu_input == 3) {
while (1) {
pattern = svga->vram[(et4000->acl.pattern_addr + et4000->acl.pattern_x) & et4000->vram_mask];
source = svga->vram[(et4000->acl.source_addr + et4000->acl.source_x) & et4000->vram_mask];
dest = svga->vram[et4000->acl.dest_addr & et4000->vram_mask];
mixmap = mix_dat & 1;
rop = mixmap ? et4000->acl.internal.rop_fg : et4000->acl.internal.rop_bg;
mix_dat >>= 1;
mix_dat |= 0x80000000;
ROPMIX(rop, dest, pattern, source, out);
/*Write the data*/
svga->vram[et4000->acl.dest_addr & et4000->vram_mask] = out;
svga->changedvram[(et4000->acl.dest_addr & et4000->vram_mask) >> 12] = changeframecount;
if (et4000->acl.internal.xy_dir & 1)
et4000w32_decx(1, et4000);
else
et4000w32_incx(1, et4000);
count--;
if (!count) {
count = et4000->acl.cpu_x_cnt;
if (et4000->acl.internal.xy_dir & 2) {
et4000w32_decy(et4000);
et4000->acl.dest_back = et4000->acl.dest_addr = et4000->acl.dest_back - (et4000->acl.internal.dest_off + 1);
} else {
et4000w32_incy(et4000);
et4000->acl.dest_back = et4000->acl.dest_addr = et4000->acl.dest_back + et4000->acl.internal.dest_off + 1;
}
et4000->acl.pattern_x = et4000->acl.pattern_x_back;
et4000->acl.source_x = et4000->acl.source_x_back;
et4000->acl.y_count--;
if (et4000->acl.y_count == 0xffff) {
et4000->acl.status &= ~ACL_XYST;
if (!(et4000->acl.internal.ctrl_routing & 7) || (et4000->acl.internal.ctrl_routing & 4)) {
et4000w32_log("W32i: end blit, xcount = %i\n", et4000->acl.x_count);
et4000->acl.status &= ~ACL_SSO;
}
return;
}
}
}
} else if (cpu_input == 4) {
while (1) {
pattern = svga->vram[(et4000->acl.pattern_addr + et4000->acl.pattern_x) & et4000->vram_mask];
source = svga->vram[(et4000->acl.source_addr + et4000->acl.source_x) & et4000->vram_mask];
dest = svga->vram[et4000->acl.dest_addr & et4000->vram_mask];
mixmap = mix_dat & 1;
rop = mixmap ? et4000->acl.internal.rop_fg : et4000->acl.internal.rop_bg;
mix_dat >>= 1;
mix_dat |= 0x80000000;
ROPMIX(rop, dest, pattern, source, out);
/*Write the data*/
svga->vram[et4000->acl.dest_addr & et4000->vram_mask] = out;
svga->changedvram[(et4000->acl.dest_addr & et4000->vram_mask) >> 12] = changeframecount;
if (et4000->acl.internal.xy_dir & 1)
et4000w32_decx(1, et4000);
else
et4000w32_incx(1, et4000);
et4000->acl.x_count--;
if (et4000->acl.x_count == 0xffff) {
et4000->acl.x_count = et4000->acl.internal.count_x;
if (et4000->acl.internal.xy_dir & 2) {
et4000w32_decy(et4000);
et4000->acl.dest_back = et4000->acl.dest_addr = et4000->acl.dest_back - (et4000->acl.internal.dest_off + 1);
} else {
et4000w32_incy(et4000);
et4000->acl.dest_back = et4000->acl.dest_addr = et4000->acl.dest_back + et4000->acl.internal.dest_off + 1;
}
et4000->acl.pattern_x = et4000->acl.pattern_x_back;
et4000->acl.source_x = et4000->acl.source_x_back;
count--;
if (!count) {
et4000->acl.status &= ~ACL_XYST;
if (!(et4000->acl.internal.ctrl_routing & 7) || (et4000->acl.internal.ctrl_routing & 4)) {
et4000w32_log("W32i: end blit, xcount = %i\n", et4000->acl.x_count);
et4000->acl.status &= ~ACL_SSO;
}
return;
}
}
}
} else {
while (count-- && (et4000->acl.y_count >= 0)) {
pattern = svga->vram[(et4000->acl.pattern_addr + et4000->acl.pattern_x) & et4000->vram_mask];
if (cpu_input == 1) {
source = src_dat & 0xff;
src_dat >>= 8;
} else /*The source data is from the display memory if the Control Routing register is not set to 1*/
source = svga->vram[(et4000->acl.source_addr + et4000->acl.source_x) & et4000->vram_mask];
dest = svga->vram[et4000->acl.dest_addr & et4000->vram_mask];
mixmap = mix_dat & 1;
/*Now determine the Raster Operation*/
rop = mixmap ? et4000->acl.internal.rop_fg : et4000->acl.internal.rop_bg;
mix_dat >>= 1;
mix_dat |= 0x80000000;
ROPMIX(rop, dest, pattern, source, out);
/*Write the data*/
svga->vram[et4000->acl.dest_addr & et4000->vram_mask] = out;
svga->changedvram[(et4000->acl.dest_addr & et4000->vram_mask) >> 12] = changeframecount;
if (et4000->acl.internal.xy_dir & 1)
et4000w32_decx(1, et4000);
else
et4000w32_incx(1, et4000);
et4000->acl.x_count--;
if (et4000->acl.x_count == 0xffff) {
et4000->acl.x_count = et4000->acl.internal.count_x;
if (et4000->acl.internal.xy_dir & 2) {
et4000w32_decy(et4000);
et4000->acl.dest_back = et4000->acl.dest_addr = et4000->acl.dest_back - (et4000->acl.internal.dest_off + 1);
} else {
et4000w32_incy(et4000);
et4000->acl.dest_back = et4000->acl.dest_addr = et4000->acl.dest_back + et4000->acl.internal.dest_off + 1;
}
et4000->acl.pattern_x = et4000->acl.pattern_x_back;
et4000->acl.source_x = et4000->acl.source_x_back;
et4000->acl.y_count--;
if (et4000->acl.y_count == 0xffff) {
et4000->acl.status &= ~ACL_XYST;
if (!(et4000->acl.internal.ctrl_routing & 7) || (et4000->acl.internal.ctrl_routing & 4)) {
et4000w32_log("W32i: end blit, xcount = %i\n", et4000->acl.x_count);
et4000->acl.status &= ~ACL_SSO;
}
et4000->acl.cpu_input_num = 0;
return;
}
if (cpu_input) {
return;
}
}
}
}
}
static void
et4000w32p_blit(int count, uint32_t mix, uint32_t sdat, int cpu_input, et4000w32p_t *et4000)
{
svga_t *svga = &et4000->svga;
uint8_t pattern;
uint8_t source;
uint8_t dest;
uint8_t out;
uint8_t rop;
int mixdat;
if (!(et4000->acl.status & ACL_XYST)) {
et4000w32_log("XY Block not started\n");
return;
}
if (et4000->acl.internal.xy_dir & 0x80) { /* Line draw */
et4000w32_log("Line draw\n");
while (count--) {
et4000w32_log("%i,%i : ", et4000->acl.internal.pos_x, et4000->acl.internal.pos_y);
pattern = svga->vram[(et4000->acl.pattern_addr + et4000->acl.pattern_x) & et4000->vram_mask];
source = svga->vram[(et4000->acl.source_addr + et4000->acl.source_x) & et4000->vram_mask];
et4000w32_log("%06X %06X ", (et4000->acl.pattern_addr + et4000->acl.pattern_x) & et4000->vram_mask, (et4000->acl.source_addr + et4000->acl.source_x) & et4000->vram_mask);
if (cpu_input == 2) {
source = sdat & 0xff;
sdat >>= 8;
}
dest = svga->vram[et4000->acl.dest_addr & et4000->vram_mask];
out = 0;
et4000w32_log("%06X ", et4000->acl.dest_addr);
if ((et4000->acl.internal.ctrl_routing & 0xa) == 8) {
mixdat = svga->vram[(et4000->acl.mix_addr >> 3) & et4000->vram_mask] & (1 << (et4000->acl.mix_addr & 7));
et4000w32_log("%06X %02X ", et4000->acl.mix_addr, svga->vram[(et4000->acl.mix_addr >> 3) & et4000->vram_mask]);
} else {
mixdat = mix & 1;
mix >>= 1;
mix |= 0x80000000;
}
et4000->acl.mix_addr++;
rop = mixdat ? et4000->acl.internal.rop_fg : et4000->acl.internal.rop_bg;
ROPMIX(rop, dest, pattern, source, out);
et4000w32_log("%06X = %02X\n", et4000->acl.dest_addr & et4000->vram_mask, out);
if (!(et4000->acl.internal.ctrl_routing & 0x40)) {
svga->vram[et4000->acl.dest_addr & et4000->vram_mask] = out;
svga->changedvram[(et4000->acl.dest_addr & et4000->vram_mask) >> 12] = changeframecount;
} else {
et4000->acl.cpu_dat |= ((uint64_t) out << (et4000->acl.cpu_dat_pos * 8));
et4000->acl.cpu_dat_pos++;
}
et4000->acl.pix_pos++;
et4000->acl.internal.pos_x++;
if (et4000->acl.pix_pos <= ((et4000->acl.internal.pixel_depth >> 4) & 3)) {
if (et4000->acl.internal.xy_dir & 1)
et4000w32_decx(1, et4000);
else
et4000w32_incx(1, et4000);
} else {
if (et4000->acl.internal.xy_dir & 1)
et4000w32_incx((et4000->acl.internal.pixel_depth >> 4) & 3, et4000);
else
et4000w32_decx((et4000->acl.internal.pixel_depth >> 4) & 3, et4000);
et4000->acl.pix_pos = 0;
/*Next pixel*/
switch (et4000->acl.internal.xy_dir & 7) {
case 0:
case 1: /* Y+ */
et4000w32_incy(et4000);
et4000->acl.internal.pos_y++;
et4000->acl.internal.pos_x -= ((et4000->acl.internal.pixel_depth >> 4) & 3) + 1;
break;
case 2:
case 3: /* Y- */
et4000w32_decy(et4000);
et4000->acl.internal.pos_y++;
et4000->acl.internal.pos_x -= ((et4000->acl.internal.pixel_depth >> 4) & 3) + 1;
break;
case 4:
case 6: /* X+ */
et4000w32_incx(((et4000->acl.internal.pixel_depth >> 4) & 3) + 1, et4000);
break;
case 5:
case 7: /* X- */
et4000w32_decx(((et4000->acl.internal.pixel_depth >> 4) & 3) + 1, et4000);
break;
default:
break;
}
et4000->acl.internal.error += et4000->acl.internal.dmin;
if (et4000->acl.internal.error > et4000->acl.internal.dmaj) {
et4000->acl.internal.error -= et4000->acl.internal.dmaj;
switch (et4000->acl.internal.xy_dir & 7) {
case 0:
case 2: /* X+ */
et4000w32_incx(((et4000->acl.internal.pixel_depth >> 4) & 3) + 1, et4000);
et4000->acl.internal.pos_x++;
break;
case 1:
case 3: /* X- */
et4000w32_decx(((et4000->acl.internal.pixel_depth >> 4) & 3) + 1, et4000);
et4000->acl.internal.pos_x++;
break;
case 4:
case 5: /* Y+ */
et4000w32_incy(et4000);
et4000->acl.internal.pos_y++;
break;
case 6:
case 7: /* Y- */
et4000w32_decy(et4000);
et4000->acl.internal.pos_y++;
break;
default:
break;
}
}
if ((et4000->acl.internal.pos_x > et4000->acl.internal.count_x) || (et4000->acl.internal.pos_y > et4000->acl.internal.count_y)) {
et4000w32_log("ACL status linedraw 0\n");
et4000->acl.status &= ~(ACL_XYST | ACL_SSO);
return;
}
}
}
} else {
et4000w32_log("BitBLT: count = %i\n", count);
while (count-- && et4000->acl.y_count >= 0) {
pattern = svga->vram[(et4000->acl.pattern_addr + et4000->acl.pattern_x) & et4000->vram_mask];
if (cpu_input == 2) {
source = sdat & 0xff;
sdat >>= 8;
} else
source = svga->vram[(et4000->acl.source_addr + et4000->acl.source_x) & et4000->vram_mask];
dest = svga->vram[et4000->acl.dest_addr & et4000->vram_mask];
out = 0;
if ((et4000->acl.internal.ctrl_routing & 0xa) == 8) {
mixdat = svga->vram[(et4000->acl.mix_addr >> 3) & et4000->vram_mask] & (1 << (et4000->acl.mix_addr & 7));
} else {
mixdat = mix & 1;
mix >>= 1;
mix |= 0x80000000;
}
rop = mixdat ? et4000->acl.internal.rop_fg : et4000->acl.internal.rop_bg;
ROPMIX(rop, dest, pattern, source, out);
if (!(et4000->acl.internal.ctrl_routing & 0x40)) {
svga->vram[et4000->acl.dest_addr & et4000->vram_mask] = out;
svga->changedvram[(et4000->acl.dest_addr & et4000->vram_mask) >> 12] = changeframecount;
} else {
et4000->acl.cpu_dat |= ((uint64_t) out << (et4000->acl.cpu_dat_pos * 8));
et4000->acl.cpu_dat_pos++;
}
if (et4000->acl.internal.xy_dir & 1)
et4000w32_decx(1, et4000);
else
et4000w32_incx(1, et4000);
et4000->acl.x_count--;
if (et4000->acl.x_count == 0xffff) {
if (et4000->acl.internal.xy_dir & 2) {
et4000w32_decy(et4000);
et4000->acl.mix_back = et4000->acl.mix_addr = et4000->acl.mix_back - (et4000->acl.internal.mix_off + 1);
et4000->acl.dest_back = et4000->acl.dest_addr = et4000->acl.dest_back - (et4000->acl.internal.dest_off + 1);
} else {
et4000w32_incy(et4000);
et4000->acl.mix_back = et4000->acl.mix_addr = et4000->acl.mix_back + et4000->acl.internal.mix_off + 1;
et4000->acl.dest_back = et4000->acl.dest_addr = et4000->acl.dest_back + et4000->acl.internal.dest_off + 1;
}
et4000->acl.pattern_x = et4000->acl.pattern_x_back;
et4000->acl.source_x = et4000->acl.source_x_back;
et4000->acl.y_count--;
et4000->acl.x_count = et4000->acl.internal.count_x;
if (et4000->acl.y_count == 0xffff) {
et4000w32_log("BitBLT end\n");
et4000->acl.status &= ~(ACL_XYST | ACL_SSO);
return;
}
if (cpu_input)
return;
if (et4000->acl.internal.ctrl_routing & 0x40) {
if (et4000->acl.cpu_dat_pos & 3)
et4000->acl.cpu_dat_pos += 4 - (et4000->acl.cpu_dat_pos & 3);
return;
}
}
}
}
}
void
et4000w32p_hwcursor_draw(svga_t *svga, int displine)
{
const et4000w32p_t *et4000 = (et4000w32p_t *) svga->priv;
int offset;
int xx;
int xx2;
int shift = (et4000->adjust_cursor + 1);
int width = (svga->hwcursor_latch.cur_xsize - svga->hwcursor_latch.xoff);
int pitch = (svga->hwcursor_latch.cur_xsize == 128) ? 32 : 16;
int x_acc = 4;
int minus_width = 0;
uint8_t dat;
offset = svga->hwcursor_latch.xoff;
if ((et4000->type == ET4000W32) && (pitch == 32)) {
switch (svga->bpp) {
case 8:
minus_width = 0;
x_acc = 2;
break;
case 15:
case 16:
minus_width = 64;
x_acc = 2;
break;
default:
break;
}
}
for (int x = 0; x < (width - minus_width); x += x_acc) {
dat = svga->vram[svga->hwcursor_latch.addr + (offset >> 2)];
xx = svga->hwcursor_latch.x + svga->x_add + x;
if (!(xx % shift)) {
xx2 = xx / shift;
if (!(dat & 2))
buffer32->line[displine][xx2] = (dat & 1) ? 0xFFFFFF : 0;
else if ((dat & 3) == 3)
buffer32->line[displine][xx2] ^= 0xFFFFFF;
}
dat >>= 2;
xx++;
if (!(xx % shift)) {
xx2 = xx / shift;
if (!(dat & 2))
buffer32->line[displine][xx2] = (dat & 1) ? 0xFFFFFF : 0;
else if ((dat & 3) == 3)
buffer32->line[displine][xx2] ^= 0xFFFFFF;
}
dat >>= 2;
xx++;
if (!(xx % shift)) {
xx2 = xx / shift;
if (!(dat & 2))
buffer32->line[displine][xx2] = (dat & 1) ? 0xFFFFFF : 0;
else if ((dat & 3) == 3)
buffer32->line[displine][xx2] ^= 0xFFFFFF;
}
dat >>= 2;
xx++;
if (!(xx % shift)) {
xx2 = xx / shift;
if (!(dat & 2))
buffer32->line[displine][xx2] = (dat & 1) ? 0xFFFFFF : 0;
else if ((dat & 3) == 3)
buffer32->line[displine][xx2] ^= 0xFFFFFF;
}
dat >>= 2;
offset += 4;
}
svga->hwcursor_latch.addr += pitch;
}
static void
et4000w32p_io_remove(et4000w32p_t *et4000)
{
io_removehandler(0x03c0, 0x0020, et4000w32p_in, NULL, NULL, et4000w32p_out, NULL, NULL, et4000);
io_removehandler(0x210a, 0x0002, et4000w32p_in, NULL, NULL, et4000w32p_out, NULL, NULL, et4000);
io_removehandler(0x211a, 0x0002, et4000w32p_in, NULL, NULL, et4000w32p_out, NULL, NULL, et4000);
io_removehandler(0x212a, 0x0002, et4000w32p_in, NULL, NULL, et4000w32p_out, NULL, NULL, et4000);
io_removehandler(0x213a, 0x0002, et4000w32p_in, NULL, NULL, et4000w32p_out, NULL, NULL, et4000);
io_removehandler(0x214a, 0x0002, et4000w32p_in, NULL, NULL, et4000w32p_out, NULL, NULL, et4000);
io_removehandler(0x215a, 0x0002, et4000w32p_in, NULL, NULL, et4000w32p_out, NULL, NULL, et4000);
io_removehandler(0x216a, 0x0002, et4000w32p_in, NULL, NULL, et4000w32p_out, NULL, NULL, et4000);
io_removehandler(0x217a, 0x0002, et4000w32p_in, NULL, NULL, et4000w32p_out, NULL, NULL, et4000);
}
static void
et4000w32p_io_set(et4000w32p_t *et4000)
{
et4000w32p_io_remove(et4000);
io_sethandler(0x03c0, 0x0020, et4000w32p_in, NULL, NULL, et4000w32p_out, NULL, NULL, et4000);
io_sethandler(0x210a, 0x0002, et4000w32p_in, NULL, NULL, et4000w32p_out, NULL, NULL, et4000);
io_sethandler(0x211a, 0x0002, et4000w32p_in, NULL, NULL, et4000w32p_out, NULL, NULL, et4000);
io_sethandler(0x212a, 0x0002, et4000w32p_in, NULL, NULL, et4000w32p_out, NULL, NULL, et4000);
io_sethandler(0x213a, 0x0002, et4000w32p_in, NULL, NULL, et4000w32p_out, NULL, NULL, et4000);
io_sethandler(0x214a, 0x0002, et4000w32p_in, NULL, NULL, et4000w32p_out, NULL, NULL, et4000);
io_sethandler(0x215a, 0x0002, et4000w32p_in, NULL, NULL, et4000w32p_out, NULL, NULL, et4000);
io_sethandler(0x216a, 0x0002, et4000w32p_in, NULL, NULL, et4000w32p_out, NULL, NULL, et4000);
io_sethandler(0x217a, 0x0002, et4000w32p_in, NULL, NULL, et4000w32p_out, NULL, NULL, et4000);
}
uint8_t
et4000w32p_pci_read(UNUSED(int func), int addr, void *priv)
{
const et4000w32p_t *et4000 = (et4000w32p_t *) priv;
if (func > 0)
return 0xff;
addr &= 0xff;
switch (addr) {
case 0x00:
return 0x0c; /* Tseng Labs */
case 0x01:
return 0x10;
case 0x02:
return (et4000->rev);
case 0x03:
return 0x32;
case PCI_REG_COMMAND:
return et4000->pci_regs[PCI_REG_COMMAND] | 0x80; /* Respond to IO and memory accesses */
case 0x07:
return 1 << 1; /* Medium DEVSEL timing */
case 0x08:
return (et4000->rev); /* Revision ID */
case 0x09:
return 0; /* Programming interface */
case 0x0a:
return 0x00; /* Supports VGA interface */
case 0x0b:
return 0x03; /* This has to be done in order to make this card work with the two 486 PCI machines. */
case 0x10:
return 0x00; /* Linear frame buffer address */
case 0x11:
return 0x00;
case 0x12:
return 0x00;
case 0x13:
return (et4000->linearbase >> 24);
case 0x30:
return et4000->pci_regs[0x30] & 0x01; /* BIOS ROM address */
case 0x31:
return 0x00;
case 0x32:
return 0x00;
case 0x33:
return et4000->pci_regs[0x33] & 0xf0;
default:
break;
}
return 0;
}
void
et4000w32p_pci_write(UNUSED(int func), int addr, uint8_t val, void *priv)
{
et4000w32p_t *et4000 = (et4000w32p_t *) priv;
svga_t *svga = &et4000->svga;
if (func > 0)
return;
addr &= 0xff;
switch (addr) {
case PCI_REG_COMMAND:
et4000->pci_regs[PCI_REG_COMMAND] = (val & 0x23) | 0x80;
if (val & PCI_COMMAND_IO)
et4000w32p_io_set(et4000);
else
et4000w32p_io_remove(et4000);
et4000w32p_recalcmapping(et4000);
break;
case 0x13:
et4000->linearbase &= 0x00c00000;
et4000->linearbase |= (et4000->pci_regs[0x13] << 24);
svga->crtc[0x30] &= 3;
svga->crtc[0x30] |= ((et4000->linearbase & 0x3f000000) >> 22);
et4000w32p_recalcmapping(et4000);
break;
case 0x30:
case 0x31:
case 0x32:
case 0x33:
et4000->pci_regs[addr] = val;
et4000->pci_regs[0x30] = 1;
et4000->pci_regs[0x31] = 0;
et4000->pci_regs[0x32] = 0;
et4000->pci_regs[0x33] &= 0xf0;
if (et4000->pci_regs[0x30] & 0x01) {
uint32_t biosaddr = (et4000->pci_regs[0x33] << 24);
if (!biosaddr)
biosaddr = 0xc0000;
et4000w32_log("ET4000 bios_rom enabled at %08x\n", biosaddr);
mem_mapping_set_addr(&et4000->bios_rom.mapping, biosaddr, 0x8000);
} else {
et4000w32_log("ET4000 bios_rom disabled\n");
mem_mapping_disable(&et4000->bios_rom.mapping);
}
return;
default:
break;
}
}
void *
et4000w32p_init(const device_t *info)
{
int vram_size;
et4000w32p_t *et4000 = malloc(sizeof(et4000w32p_t));
memset(et4000, 0, sizeof(et4000w32p_t));
et4000->pci = (info->flags & DEVICE_PCI) ? 0x80 : 0x00;
et4000->vlb = (info->flags & DEVICE_VLB) ? 0x40 : 0x00;
/*The ET4000/W32i ISA BIOS seems to not support 2MB of VRAM*/
if ((info->local == ET4000W32) || ((info->local == ET4000W32I) && !(et4000->vlb)))
vram_size = 1;
else
vram_size = device_get_config_int("memory");
/*The interleaved VRAM was introduced by the ET4000/W32i*/
et4000->interleaved = ((vram_size == 2) && (info->local != ET4000W32)) ? 1 : 0;
if (info->flags & DEVICE_PCI)
video_inform(VIDEO_FLAG_TYPE_SPECIAL, &timing_et4000w32_pci);
else if (info->flags & DEVICE_VLB)
video_inform(VIDEO_FLAG_TYPE_SPECIAL, &timing_et4000w32_vlb);
else
video_inform(VIDEO_FLAG_TYPE_SPECIAL, &timing_et4000w32_isa);
svga_init(info, &et4000->svga, et4000, vram_size << 20,
et4000w32p_recalctimings,
et4000w32p_in, et4000w32p_out,
et4000w32p_hwcursor_draw,
NULL);
et4000->vram_mask = (vram_size << 20) - 1;
et4000->svga.decode_mask = (vram_size << 20) - 1;
et4000->type = info->local;
switch (et4000->type) {
case ET4000W32:
/* ET4000/W32 */
et4000->rev = 0;
rom_init(&et4000->bios_rom, BIOS_ROM_PATH_W32, 0xc0000, 0x8000, 0x7fff, 0,
MEM_MAPPING_EXTERNAL);
et4000->svga.ramdac = device_add(&tseng_ics5301_ramdac_device);
et4000->svga.clock_gen = et4000->svga.ramdac;
et4000->svga.getclock = sdac_getclock;
break;
case ET4000W32I:
/* ET4000/W32i rev B */
et4000->rev = 3;
if (et4000->vlb) {
rom_init(&et4000->bios_rom, BIOS_ROM_PATH_W32I_VLB, 0xc0000, 0x8000, 0x7fff, 0,
MEM_MAPPING_EXTERNAL);
} else {
rom_init(&et4000->bios_rom, BIOS_ROM_PATH_W32I_ISA, 0xc0000, 0x8000, 0x7fff, 0,
MEM_MAPPING_EXTERNAL);
}
et4000->svga.ramdac = device_add(&tseng_ics5301_ramdac_device);
et4000->svga.clock_gen = et4000->svga.ramdac;
et4000->svga.getclock = sdac_getclock;
break;
case ET4000W32P_VIDEOMAGIC_REVB:
/* ET4000/W32p rev B */
et4000->rev = 5;
rom_init(&et4000->bios_rom, BIOS_ROM_PATH_W32P_VIDEOMAGIC_REVB_VLB, 0xc0000, 0x8000, 0x7fff, 0,
MEM_MAPPING_EXTERNAL);
et4000->svga.ramdac = device_add(&stg_ramdac_device);
et4000->svga.clock_gen = et4000->svga.ramdac;
et4000->svga.getclock = stg_getclock;
break;
case ET4000W32P_REVC:
/* ET4000/W32p rev C */
et4000->rev = 7;
rom_init(&et4000->bios_rom, BIOS_ROM_PATH_W32P_REVC, 0xc0000, 0x8000, 0x7fff, 0,
MEM_MAPPING_EXTERNAL);
et4000->svga.ramdac = device_add(&tseng_ics5341_ramdac_device);
et4000->svga.clock_gen = et4000->svga.ramdac;
et4000->svga.getclock = sdac_getclock;
break;
case ET4000W32P:
/* ET4000/W32p rev D */
et4000->rev = 6;
rom_init(&et4000->bios_rom, BIOS_ROM_PATH_W32P, 0xc0000, 0x8000, 0x7fff, 0,
MEM_MAPPING_EXTERNAL);
et4000->svga.ramdac = device_add(&stg_ramdac_device);
et4000->svga.clock_gen = et4000->svga.ramdac;
et4000->svga.getclock = stg_getclock;
break;
case ET4000W32P_CARDEX:
/* ET4000/W32p rev D */
et4000->rev = 6;
rom_init(&et4000->bios_rom, BIOS_ROM_PATH_CARDEX, 0xc0000, 0x8000, 0x7fff, 0,
MEM_MAPPING_EXTERNAL);
et4000->svga.ramdac = device_add(&stg_ramdac_device);
et4000->svga.clock_gen = et4000->svga.ramdac;
et4000->svga.getclock = stg_getclock;
break;
case ET4000W32P_DIAMOND:
/* ET4000/W32p rev D */
et4000->rev = 6;
rom_init(&et4000->bios_rom, BIOS_ROM_PATH_DIAMOND, 0xc0000, 0x8000, 0x7fff, 0,
MEM_MAPPING_EXTERNAL);
et4000->svga.ramdac = device_add(&stg_ramdac_device);
et4000->svga.clock_gen = device_add(&icd2061_device);
et4000->svga.getclock = icd2061_getclock;
break;
default:
break;
}
if (info->flags & DEVICE_PCI)
mem_mapping_disable(&et4000->bios_rom.mapping);
mem_mapping_add(&et4000->linear_mapping, 0, 0, svga_read_linear, svga_readw_linear, svga_readl_linear, svga_write_linear, svga_writew_linear, svga_writel_linear, NULL, MEM_MAPPING_EXTERNAL, &et4000->svga);
mem_mapping_add(&et4000->mmu_mapping, 0, 0, et4000w32p_mmu_read, NULL, NULL, et4000w32p_mmu_write, NULL, NULL, NULL, MEM_MAPPING_EXTERNAL, et4000);
et4000w32p_io_set(et4000);
if (info->flags & DEVICE_PCI)
pci_add_card(PCI_ADD_NORMAL, et4000w32p_pci_read, et4000w32p_pci_write, et4000, &et4000->pci_slot);
/* Hardwired bits: 00000000 1xx0x0xx */
/* R/W bits: xx xxxx */
/* PCem bits: 111 */
et4000->pci_regs[0x04] = 0x83;
et4000->pci_regs[0x10] = 0x00;
et4000->pci_regs[0x11] = 0x00;
et4000->pci_regs[0x12] = 0xff;
et4000->pci_regs[0x13] = 0xff;
et4000->pci_regs[0x30] = 0x00;
et4000->pci_regs[0x31] = 0x00;
et4000->pci_regs[0x32] = 0x00;
et4000->pci_regs[0x33] = 0xf0;
et4000->svga.packed_chain4 = 1;
return et4000;
}
int
et4000w32_available(void)
{
return rom_present(BIOS_ROM_PATH_W32);
}
int
et4000w32i_isa_available(void)
{
return rom_present(BIOS_ROM_PATH_W32I_ISA);
}
int
et4000w32i_vlb_available(void)
{
return rom_present(BIOS_ROM_PATH_W32I_VLB);
}
int
et4000w32p_videomagic_revb_vlb_available(void)
{
return rom_present(BIOS_ROM_PATH_W32P_VIDEOMAGIC_REVB_VLB);
}
int
et4000w32p_revc_available(void)
{
return rom_present(BIOS_ROM_PATH_W32P_REVC);
}
int
et4000w32p_noncardex_available(void)
{
return rom_present(BIOS_ROM_PATH_W32P);
}
int
et4000w32p_available(void)
{
return rom_present(BIOS_ROM_PATH_DIAMOND);
}
int
et4000w32p_cardex_available(void)
{
return rom_present(BIOS_ROM_PATH_CARDEX);
}
void
et4000w32p_close(void *priv)
{
et4000w32p_t *et4000 = (et4000w32p_t *) priv;
svga_close(&et4000->svga);
free(et4000);
}
void
et4000w32p_speed_changed(void *priv)
{
et4000w32p_t *et4000 = (et4000w32p_t *) priv;
svga_recalctimings(&et4000->svga);
}
void
et4000w32p_force_redraw(void *priv)
{
et4000w32p_t *et4000 = (et4000w32p_t *) priv;
et4000->svga.fullchange = changeframecount;
}
static const device_config_t et4000w32p_config[] = {
// clang-format off
{
.name = "memory",
.description = "Memory size",
.type = CONFIG_SELECTION,
.default_int = 2,
.selection = {
{
.description = "1 MB",
.value = 1
},
{
.description = "2 MB",
.value = 2
},
{
.description = ""
}
}
},
{
.type = CONFIG_END
}
// clang-format on
};
const device_t et4000w32_device = {
.name = "Tseng Labs ET4000/w32 ISA",
.internal_name = "et4000w32",
.flags = DEVICE_ISA | DEVICE_AT,
.local = ET4000W32,
.init = et4000w32p_init,
.close = et4000w32p_close,
.reset = NULL,
{ .available = et4000w32_available },
.speed_changed = et4000w32p_speed_changed,
.force_redraw = et4000w32p_force_redraw,
.config = NULL
};
const device_t et4000w32_onboard_device = {
.name = "Tseng Labs ET4000/w32 (ISA) (On-Board)",
.internal_name = "et4000w32_onboard",
.flags = DEVICE_ISA | DEVICE_AT,
.local = ET4000W32,
.init = et4000w32p_init,
.close = et4000w32p_close,
.reset = NULL,
{ .available = et4000w32_available },
.speed_changed = et4000w32p_speed_changed,
.force_redraw = et4000w32p_force_redraw,
.config = NULL
};
const device_t et4000w32i_isa_device = {
.name = "Tseng Labs ET4000/w32i Rev. B ISA",
.internal_name = "et4000w32i",
.flags = DEVICE_ISA | DEVICE_AT,
.local = ET4000W32I,
.init = et4000w32p_init,
.close = et4000w32p_close,
.reset = NULL,
{ .available = et4000w32i_isa_available },
.speed_changed = et4000w32p_speed_changed,
.force_redraw = et4000w32p_force_redraw,
.config = NULL
};
const device_t et4000w32i_vlb_device = {
.name = "Tseng Labs ET4000/w32i Rev. B VLB",
.internal_name = "et4000w32i_vlb",
.flags = DEVICE_VLB,
.local = ET4000W32I,
.init = et4000w32p_init,
.close = et4000w32p_close,
.reset = NULL,
{ .available = et4000w32i_vlb_available },
.speed_changed = et4000w32p_speed_changed,
.force_redraw = et4000w32p_force_redraw,
.config = et4000w32p_config
};
const device_t et4000w32p_videomagic_revb_vlb_device = {
.name = "Tseng Labs ET4000/w32p Rev. B VLB (VideoMagic)",
.internal_name = "et4000w32p_videomagic_revb_vlb",
.flags = DEVICE_VLB,
.local = ET4000W32P_VIDEOMAGIC_REVB,
.init = et4000w32p_init,
.close = et4000w32p_close,
.reset = NULL,
{ .available = et4000w32p_videomagic_revb_vlb_available },
.speed_changed = et4000w32p_speed_changed,
.force_redraw = et4000w32p_force_redraw,
.config = et4000w32p_config
};
const device_t et4000w32p_videomagic_revb_pci_device = {
.name = "Tseng Labs ET4000/w32p Rev. B PCI (VideoMagic)",
.internal_name = "et4000w32p_videomagic_revb_pci",
.flags = DEVICE_PCI,
.local = ET4000W32P_VIDEOMAGIC_REVB,
.init = et4000w32p_init,
.close = et4000w32p_close,
.reset = NULL,
{ .available = et4000w32p_videomagic_revb_vlb_available },
.speed_changed = et4000w32p_speed_changed,
.force_redraw = et4000w32p_force_redraw,
.config = et4000w32p_config
};
const device_t et4000w32p_revc_vlb_device = {
.name = "Tseng Labs ET4000/w32p Rev. C VLB (Cardex)",
.internal_name = "et4000w32p_revc_vlb",
.flags = DEVICE_VLB,
.local = ET4000W32P_REVC,
.init = et4000w32p_init,
.close = et4000w32p_close,
.reset = NULL,
{ .available = et4000w32p_revc_available },
.speed_changed = et4000w32p_speed_changed,
.force_redraw = et4000w32p_force_redraw,
.config = et4000w32p_config
};
const device_t et4000w32p_revc_pci_device = {
.name = "Tseng Labs ET4000/w32p Rev. C PCI (Cardex)",
.internal_name = "et4000w32p_revc_pci",
.flags = DEVICE_PCI,
.local = ET4000W32P_REVC,
.init = et4000w32p_init,
.close = et4000w32p_close,
.reset = NULL,
{ .available = et4000w32p_revc_available },
.speed_changed = et4000w32p_speed_changed,
.force_redraw = et4000w32p_force_redraw,
.config = et4000w32p_config
};
const device_t et4000w32p_noncardex_vlb_device = {
.name = "Tseng Labs ET4000/w32p Rev. D VLB",
.internal_name = "et4000w32p_nc_vlb",
.flags = DEVICE_VLB,
.local = ET4000W32P,
.init = et4000w32p_init,
.close = et4000w32p_close,
.reset = NULL,
{ .available = et4000w32p_noncardex_available },
.speed_changed = et4000w32p_speed_changed,
.force_redraw = et4000w32p_force_redraw,
.config = et4000w32p_config
};
const device_t et4000w32p_noncardex_pci_device = {
.name = "Tseng Labs ET4000/w32p Rev. D PCI",
.internal_name = "et4000w32p_nc_pci",
.flags = DEVICE_PCI,
.local = ET4000W32P,
.init = et4000w32p_init,
.close = et4000w32p_close,
.reset = NULL,
{ .available = et4000w32p_noncardex_available },
.speed_changed = et4000w32p_speed_changed,
.force_redraw = et4000w32p_force_redraw,
.config = et4000w32p_config
};
const device_t et4000w32p_cardex_vlb_device = {
.name = "Tseng Labs ET4000/w32p Rev. D VLB (Cardex)",
.internal_name = "et4000w32p_vlb",
.flags = DEVICE_VLB,
.local = ET4000W32P_CARDEX,
.init = et4000w32p_init,
.close = et4000w32p_close,
.reset = NULL,
{ .available = et4000w32p_cardex_available },
.speed_changed = et4000w32p_speed_changed,
.force_redraw = et4000w32p_force_redraw,
.config = et4000w32p_config
};
const device_t et4000w32p_cardex_pci_device = {
.name = "Tseng Labs ET4000/w32p Rev. D PCI (Cardex)",
.internal_name = "et4000w32p_pci",
.flags = DEVICE_PCI,
.local = ET4000W32P_CARDEX,
.init = et4000w32p_init,
.close = et4000w32p_close,
.reset = NULL,
{ .available = et4000w32p_cardex_available },
.speed_changed = et4000w32p_speed_changed,
.force_redraw = et4000w32p_force_redraw,
.config = et4000w32p_config
};
const device_t et4000w32p_vlb_device = {
.name = "Tseng Labs ET4000/w32p Rev. D VLB (Diamond Stealth32)",
.internal_name = "stealth32_vlb",
.flags = DEVICE_VLB,
.local = ET4000W32P_DIAMOND,
.init = et4000w32p_init,
.close = et4000w32p_close,
.reset = NULL,
{ .available = et4000w32p_available },
.speed_changed = et4000w32p_speed_changed,
.force_redraw = et4000w32p_force_redraw,
.config = et4000w32p_config
};
const device_t et4000w32p_pci_device = {
.name = "Tseng Labs ET4000/w32p Rev. D PCI (Diamond Stealth32)",
.internal_name = "stealth32_pci",
.flags = DEVICE_PCI,
.local = ET4000W32P_DIAMOND,
.init = et4000w32p_init,
.close = et4000w32p_close,
.reset = NULL,
{ .available = et4000w32p_available },
.speed_changed = et4000w32p_speed_changed,
.force_redraw = et4000w32p_force_redraw,
.config = et4000w32p_config
};
``` | /content/code_sandbox/src/video/vid_et4000w32.c | c | 2016-06-25T22:29:10 | 2024-08-16T19:09:21 | 86Box | 86Box/86Box | 2,616 | 35,886 |
```c
/*
* 86Box A hypervisor and IBM PC system emulator that specializes in
* running old operating systems and software designed for IBM
* PC systems and compatibles from 1981 through fairly recent
* system designs based on the PCI bus.
*
* This file is part of the 86Box distribution.
*
* Emulation of the Tseng Labs ET4000.
*
*
*
* Authors: Fred N. van Kempen, <decwiz@yahoo.com>
* Miran Grca, <mgrca8@gmail.com>
* GreatPsycho, <greatpsycho@yahoo.com>
* Sarah Walker, <path_to_url
*
*
* This program is free software; you can redistribute it and/or modify
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful, but
* WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
*
* along with this program; if not, write to the:
*
* Free Software Foundation, Inc.
* 59 Temple Place - Suite 330
* Boston, MA 02111-1307
* USA.
*/
#include <stdio.h>
#include <stdint.h>
#include <string.h>
#include <stdlib.h>
#include <wchar.h>
#include <86box/86box.h>
#include <86box/io.h>
#include <86box/mca.h>
#include <86box/mem.h>
#include <86box/rom.h>
#include <86box/device.h>
#include <86box/timer.h>
#include <86box/video.h>
#include <86box/vid_svga.h>
#include <86box/vid_svga_render.h>
#include <86box/plat_fallthrough.h>
#include <86box/plat_unused.h>
#define ET4000_TYPE_TC6058AF 0 /* ISA ET4000AX (TC6058AF) */
#define ET4000_TYPE_ISA 1 /* ISA ET4000AX */
#define ET4000_TYPE_MCA 2 /* MCA ET4000AX */
#define ET4000_TYPE_KOREAN 3 /* Korean ET4000 */
#define ET4000_TYPE_TRIGEM 4 /* Trigem 286M ET4000 */
#define ET4000_TYPE_KASAN 5 /* Kasan ET4000 */
#define BIOS_ROM_PATH "roms/video/et4000/ET4000.BIN"
#define V8_06_BIOS_ROM_PATH "roms/video/et4000/ET4000_V8_06.BIN"
#define TC6058AF_BIOS_ROM_PATH "roms/video/et4000/Tseng_Labs_VGA-4000_BIOS_V1.1.bin"
#define V1_21_BIOS_ROM_PATH "roms/video/et4000/Tseng_Labs_VGA-4000_BIOS_V1.21.bin"
#define KOREAN_BIOS_ROM_PATH "roms/video/et4000/tgkorvga.bin"
#define KOREAN_FONT_ROM_PATH "roms/video/et4000/tg_ksc5601.rom"
#define KASAN_BIOS_ROM_PATH "roms/video/et4000/et4000_kasan16.bin"
#define KASAN_FONT_ROM_PATH "roms/video/et4000/kasan_ksc5601.rom"
typedef struct {
const char *name;
int type;
svga_t svga;
uint8_t pos_regs[8];
rom_t bios_rom;
uint8_t banking;
uint32_t vram_size,
vram_mask;
uint8_t port_22cb_val;
uint8_t port_32cb_val;
int get_korean_font_enabled;
int get_korean_font_index;
uint16_t get_korean_font_base;
uint8_t kasan_cfg_index;
uint8_t kasan_cfg_regs[16];
uint16_t kasan_access_addr;
uint8_t kasan_font_data[4];
} et4000_t;
static const uint8_t crtc_mask[0x40] = {
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
0xff, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0xff, 0xff, 0xff, 0x0f, 0xff, 0xff, 0xff, 0xff,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
};
static video_timings_t timing_et4000_isa = { .type = VIDEO_ISA, .write_b = 3, .write_w = 3, .write_l = 6, .read_b = 5, .read_w = 5, .read_l = 10 };
static video_timings_t timing_et4000_mca = { .type = VIDEO_MCA, .write_b = 4, .write_w = 5, .write_l = 10, .read_b = 5, .read_w = 5, .read_l = 10 };
static void et4000_kasan_out(uint16_t addr, uint8_t val, void *priv);
static uint8_t et4000_kasan_in(uint16_t addr, void *priv);
static uint8_t
et4000_in(uint16_t addr, void *priv)
{
et4000_t *dev = (et4000_t *) priv;
svga_t *svga = &dev->svga;
uint8_t ret;
if (((addr & 0xfff0) == 0x3d0 || (addr & 0xfff0) == 0x3b0) && !(svga->miscout & 1))
addr ^= 0x60;
switch (addr) {
case 0x3c2:
if (dev->type == ET4000_TYPE_MCA) {
if ((svga->vgapal[0].r + svga->vgapal[0].g + svga->vgapal[0].b) >= 0x4e)
return 0;
else
return 0x10;
}
break;
case 0x3c5:
if ((svga->seqaddr & 0xf) == 7)
return svga->seqregs[svga->seqaddr & 0xf] | 4;
break;
case 0x3c6:
case 0x3c7:
case 0x3c8:
case 0x3c9:
if (dev->type >= ET4000_TYPE_ISA)
return sc1502x_ramdac_in(addr, svga->ramdac, svga);
break;
case 0x3cd: /*Banking*/
return dev->banking;
case 0x3d4:
return svga->crtcreg;
case 0x3d5:
return svga->crtc[svga->crtcreg];
case 0x3da:
svga->attrff = 0;
if (svga->cgastat & 0x01)
svga->cgastat &= ~0x30;
else
svga->cgastat ^= 0x30;
ret = svga->cgastat;
if ((svga->fcr & 0x08) && svga->dispon)
ret |= 0x08;
if (ret & 0x08)
ret &= 0x7f;
else
ret |= 0x80;
return ret;
default:
break;
}
return svga_in(addr, svga);
}
static uint8_t
et4000k_in(uint16_t addr, void *priv)
{
et4000_t *dev = (et4000_t *) priv;
uint8_t val = 0xff;
switch (addr) {
case 0x22cb:
return dev->port_22cb_val;
case 0x22cf:
val = 0;
switch (dev->get_korean_font_enabled) {
case 3:
if ((dev->port_32cb_val & 0x30) == 0x30) {
val = fontdatksc5601[dev->get_korean_font_base].chr[dev->get_korean_font_index++];
dev->get_korean_font_index &= 0x1f;
} else if ((dev->port_32cb_val & 0x30) == 0x20 && (dev->get_korean_font_base & 0x7f) > 0x20 && (dev->get_korean_font_base & 0x7f) < 0x7f) {
switch (dev->get_korean_font_base & 0x3f80) {
case 0x2480:
if (dev->get_korean_font_index < 16)
val = fontdatksc5601_user[(dev->get_korean_font_base & 0x7f) - 0x20].chr[dev->get_korean_font_index];
else if (dev->get_korean_font_index >= 24 && dev->get_korean_font_index < 40)
val = fontdatksc5601_user[(dev->get_korean_font_base & 0x7f) - 0x20].chr[dev->get_korean_font_index - 8];
break;
case 0x3f00:
if (dev->get_korean_font_index < 16)
val = fontdatksc5601_user[96 + (dev->get_korean_font_base & 0x7f) - 0x20].chr[dev->get_korean_font_index];
else if (dev->get_korean_font_index >= 24 && dev->get_korean_font_index < 40)
val = fontdatksc5601_user[96 + (dev->get_korean_font_base & 0x7f) - 0x20].chr[dev->get_korean_font_index - 8];
break;
default:
break;
}
dev->get_korean_font_index++;
dev->get_korean_font_index %= 72;
}
break;
case 4:
val = 0x0f;
break;
default:
break;
}
return val;
case 0x32cb:
return dev->port_32cb_val;
default:
return et4000_in(addr, priv);
}
}
static void
et4000_out(uint16_t addr, uint8_t val, void *priv)
{
et4000_t *dev = (et4000_t *) priv;
svga_t *svga = &dev->svga;
uint8_t old;
uint8_t pal4to16[16] = { 0, 7, 0x38, 0x3f, 0, 3, 4, 0x3f, 0, 2, 4, 0x3e, 0, 3, 5, 0x3f };
if (((addr & 0xfff0) == 0x3d0 || (addr & 0xfff0) == 0x3b0) && !(svga->miscout & 1))
addr ^= 0x60;
switch (addr) {
case 0x3c0:
case 0x3c1:
if (!svga->attrff) {
svga->attraddr = val & 0x1f;
if ((val & 0x20) != svga->attr_palette_enable) {
svga->fullchange = 3;
svga->attr_palette_enable = val & 0x20;
svga_recalctimings(svga);
}
} else {
if ((svga->attraddr == 0x13) && (svga->attrregs[0x13] != val))
svga->fullchange = svga->monitor->mon_changeframecount;
old = svga->attrregs[svga->attraddr & 0x1f];
svga->attrregs[svga->attraddr & 0x1f] = val;
if (svga->attraddr < 0x10)
svga->fullchange = svga->monitor->mon_changeframecount;
if ((svga->attraddr == 0x10) || (svga->attraddr == 0x14) || (svga->attraddr < 0x10)) {
for (int c = 0; c < 0x10; c++) {
if (svga->attrregs[0x10] & 0x80)
svga->egapal[c] = (svga->attrregs[c] & 0xf) | ((svga->attrregs[0x14] & 0xf) << 4);
else if (svga->ati_4color)
svga->egapal[c] = pal4to16[(c & 0x03) | ((val >> 2) & 0xc)];
else
svga->egapal[c] = (svga->attrregs[c] & 0x3f) | ((svga->attrregs[0x14] & 0xc) << 4);
}
svga->fullchange = svga->monitor->mon_changeframecount;
}
/* Recalculate timings on change of attribute register 0x11
(overscan border color) too. */
if (svga->attraddr == 0x10) {
svga->chain4 &= ~0x02;
if ((val & 0x40) && (svga->attrregs[0x10] & 0x40))
svga->chain4 |= (svga->seqregs[0x0e] & 0x02);
if (old != val)
svga_recalctimings(svga);
} else if (svga->attraddr == 0x11) {
svga->overscan_color = svga->pallook[svga->attrregs[0x11]];
if (old != val)
svga_recalctimings(svga);
} else if (svga->attraddr == 0x12) {
if ((val & 0xf) != svga->plane_mask)
svga->fullchange = svga->monitor->mon_changeframecount;
svga->plane_mask = val & 0xf;
}
}
svga->attrff ^= 1;
return;
case 0x3c5:
if (svga->seqaddr == 4) {
svga->seqregs[4] = val;
svga->chain2_write = !(val & 4);
svga->chain4 = (svga->chain4 & ~8) | (val & 8);
svga->fast = (svga->gdcreg[8] == 0xff && !(svga->gdcreg[3] & 0x18) && !svga->gdcreg[1]) && svga->chain4 && !(svga->adv_flags & FLAG_ADDR_BY8);
return;
} else if (svga->seqaddr == 0x0e) {
svga->seqregs[0x0e] = val;
svga->chain4 &= ~0x02;
if ((svga->gdcreg[5] & 0x40) && svga->lowres)
svga->chain4 |= (svga->seqregs[0x0e] & 0x02);
svga_recalctimings(svga);
return;
}
break;
case 0x3c6:
case 0x3c7:
case 0x3c8:
case 0x3c9:
if (dev->type >= ET4000_TYPE_ISA) {
sc1502x_ramdac_out(addr, val, svga->ramdac, svga);
return;
}
break;
case 0x3cd: /*Banking*/
if (!(svga->crtc[0x36] & 0x10) && !(svga->gdcreg[6] & 0x08)) {
svga->write_bank = (val & 0xf) * 0x10000;
svga->read_bank = ((val >> 4) & 0xf) * 0x10000;
}
dev->banking = val;
return;
case 0x3cf:
if ((svga->gdcaddr & 15) == 5) {
svga->chain4 &= ~0x02;
if ((val & 0x40) && svga->lowres)
svga->chain4 |= (svga->seqregs[0x0e] & 0x02);
} else if ((svga->gdcaddr & 15) == 6) {
if (!(svga->crtc[0x36] & 0x10) && !(val & 0x08)) {
svga->write_bank = (dev->banking & 0x0f) * 0x10000;
svga->read_bank = ((dev->banking >> 4) & 0x0f) * 0x10000;
} else
svga->write_bank = svga->read_bank = 0;
old = svga->gdcreg[6];
svga_out(addr, val, svga);
if ((old & 0xc) != 0 && (val & 0xc) == 0) {
/*override mask - ET4000 supports linear 128k at A0000*/
svga->banked_mask = 0x1ffff;
}
return;
}
break;
case 0x3d4:
svga->crtcreg = val & 0x3f;
return;
case 0x3d5:
if ((svga->crtcreg < 7) && (svga->crtc[0x11] & 0x80))
return;
if ((svga->crtcreg == 0x35) && (svga->crtc[0x11] & 0x80))
return;
if ((svga->crtcreg == 7) && (svga->crtc[0x11] & 0x80))
val = (svga->crtc[7] & ~0x10) | (val & 0x10);
old = svga->crtc[svga->crtcreg];
val &= crtc_mask[svga->crtcreg];
svga->crtc[svga->crtcreg] = val;
if (svga->crtcreg == 0x36) {
if (!(val & 0x10) && !(svga->gdcreg[6] & 0x08)) {
svga->write_bank = (dev->banking & 0x0f) * 0x10000;
svga->read_bank = ((dev->banking >> 4) & 0x0f) * 0x10000;
} else
svga->write_bank = svga->read_bank = 0;
}
if (old != val) {
if (svga->crtcreg < 0xe || svga->crtcreg > 0x10) {
if ((svga->crtcreg == 0xc) || (svga->crtcreg == 0xd)) {
svga->fullchange = 3;
svga->ma_latch = ((svga->crtc[0xc] << 8) | svga->crtc[0xd]) + ((svga->crtc[8] & 0x60) >> 5);
} else {
svga->fullchange = changeframecount;
svga_recalctimings(svga);
}
}
}
break;
default:
break;
}
svga_out(addr, val, svga);
}
static void
et4000k_out(uint16_t addr, uint8_t val, void *priv)
{
et4000_t *dev = (et4000_t *) priv;
switch (addr) {
case 0x22cb:
dev->port_22cb_val = (dev->port_22cb_val & 0xf0) | (val & 0x0f);
dev->get_korean_font_enabled = val & 7;
if (dev->get_korean_font_enabled == 3)
dev->get_korean_font_index = 0;
break;
case 0x22cf:
switch (dev->get_korean_font_enabled) {
case 1:
dev->get_korean_font_base = ((val & 0x7f) << 7) | (dev->get_korean_font_base & 0x7f);
break;
case 2:
dev->get_korean_font_base = (dev->get_korean_font_base & 0x3f80) | (val & 0x7f) | (((val ^ 0x80) & 0x80) << 8);
break;
case 3:
if ((dev->port_32cb_val & 0x30) == 0x20 && (dev->get_korean_font_base & 0x7f) > 0x20 && (dev->get_korean_font_base & 0x7f) < 0x7f) {
switch (dev->get_korean_font_base & 0x3f80) {
case 0x2480:
if (dev->get_korean_font_index < 16)
fontdatksc5601_user[(dev->get_korean_font_base & 0x7f) - 0x20].chr[dev->get_korean_font_index] = val;
else if (dev->get_korean_font_index >= 24 && dev->get_korean_font_index < 40)
fontdatksc5601_user[(dev->get_korean_font_base & 0x7f) - 0x20].chr[dev->get_korean_font_index - 8] = val;
break;
case 0x3f00:
if (dev->get_korean_font_index < 16)
fontdatksc5601_user[96 + (dev->get_korean_font_base & 0x7f) - 0x20].chr[dev->get_korean_font_index] = val;
else if (dev->get_korean_font_index >= 24 && dev->get_korean_font_index < 40)
fontdatksc5601_user[96 + (dev->get_korean_font_base & 0x7f) - 0x20].chr[dev->get_korean_font_index - 8] = val;
break;
default:
break;
}
dev->get_korean_font_index++;
}
break;
default:
break;
}
break;
case 0x32cb:
dev->port_32cb_val = val;
svga_recalctimings(&dev->svga);
break;
default:
et4000_out(addr, val, priv);
break;
}
}
static uint8_t
et4000_kasan_in(uint16_t addr, void *priv)
{
const et4000_t *et4000 = (et4000_t *) priv;
uint8_t val = 0xFF;
if (addr == 0x258) {
val = et4000->kasan_cfg_index;
} else if (addr == 0x259) {
if (et4000->kasan_cfg_index >= 0xF0) {
val = et4000->kasan_cfg_regs[et4000->kasan_cfg_index - 0xF0];
if (et4000->kasan_cfg_index == 0xF4 && et4000->kasan_cfg_regs[0] & 0x20)
val |= 0x80;
}
} else if (addr >= et4000->kasan_access_addr && addr < et4000->kasan_access_addr + 8) {
switch (addr - ((et4000->kasan_cfg_regs[2] << 8) | (et4000->kasan_cfg_regs[1]))) {
case 2:
val = 0;
break;
case 5:
if (((et4000->get_korean_font_base >> 7) & 0x7F) == (et4000->svga.ksc5601_udc_area_msb[0] & 0x7F) && (et4000->svga.ksc5601_udc_area_msb[0] & 0x80))
val = fontdatksc5601_user[(et4000->get_korean_font_base & 0x7F) - 0x20].chr[et4000->get_korean_font_index];
else if (((et4000->get_korean_font_base >> 7) & 0x7F) == (et4000->svga.ksc5601_udc_area_msb[1] & 0x7F) && (et4000->svga.ksc5601_udc_area_msb[1] & 0x80))
val = fontdatksc5601_user[96 + (et4000->get_korean_font_base & 0x7F) - 0x20].chr[et4000->get_korean_font_index];
else
val = fontdatksc5601[et4000->get_korean_font_base].chr[et4000->get_korean_font_index];
break;
default:
break;
}
} else
val = et4000_in(addr, priv);
return val;
}
static void
et4000_kasan_out(uint16_t addr, uint8_t val, void *priv)
{
et4000_t *et4000 = (et4000_t *) priv;
if (addr == 0x258) {
et4000->kasan_cfg_index = val;
} else if (addr == 0x259) {
if (et4000->kasan_cfg_index >= 0xF0) {
switch (et4000->kasan_cfg_index - 0xF0) {
case 0:
if (et4000->kasan_cfg_regs[4] & 8)
val = (val & 0xFC) | (et4000->kasan_cfg_regs[0] & 3);
et4000->kasan_cfg_regs[0] = val;
svga_recalctimings(&et4000->svga);
break;
case 1:
case 2:
if ((et4000->kasan_cfg_index - 0xF0) <= 16)
et4000->kasan_cfg_regs[et4000->kasan_cfg_index - 0xF0] = val;
io_removehandler(et4000->kasan_access_addr, 0x0008, et4000_kasan_in, NULL, NULL, et4000_kasan_out, NULL, NULL, et4000);
et4000->kasan_access_addr = (et4000->kasan_cfg_regs[2] << 8) | et4000->kasan_cfg_regs[1];
io_sethandler(et4000->kasan_access_addr, 0x0008, et4000_kasan_in, NULL, NULL, et4000_kasan_out, NULL, NULL, et4000);
break;
case 4:
if (et4000->kasan_cfg_regs[0] & 0x20)
val |= 0x80;
et4000->svga.ksc5601_swap_mode = (val & 4) >> 2;
et4000->kasan_cfg_regs[4] = val;
svga_recalctimings(&et4000->svga);
break;
case 5:
et4000->kasan_cfg_regs[5] = val;
et4000->svga.ksc5601_english_font_type = 0x100 | val;
fallthrough;
case 6:
case 7:
et4000->svga.ksc5601_udc_area_msb[et4000->kasan_cfg_index - 0xF6] = val;
default:
et4000->kasan_cfg_regs[et4000->kasan_cfg_index - 0xF0] = val;
svga_recalctimings(&et4000->svga);
break;
}
}
} else if (addr >= et4000->kasan_access_addr && addr < et4000->kasan_access_addr + 8) {
switch (addr - ((et4000->kasan_cfg_regs[2] << 8) | (et4000->kasan_cfg_regs[1]))) {
case 0:
if (et4000->kasan_cfg_regs[0] & 2) {
et4000->get_korean_font_index = ((val & 1) << 4) | ((val & 0x1E) >> 1);
et4000->get_korean_font_base = (et4000->get_korean_font_base & ~7) | (val >> 5);
}
break;
case 1:
if (et4000->kasan_cfg_regs[0] & 2)
et4000->get_korean_font_base = (et4000->get_korean_font_base & ~0x7F8) | (val << 3);
break;
case 2:
if (et4000->kasan_cfg_regs[0] & 2)
et4000->get_korean_font_base = (et4000->get_korean_font_base & ~0x7F800) | ((val & 7) << 11);
break;
case 3:
case 4:
case 5:
if (et4000->kasan_cfg_regs[0] & 1) {
if ((addr - (((et4000->kasan_cfg_regs[2] << 8) | (et4000->kasan_cfg_regs[1])) + 3)) <= 4)
et4000->kasan_font_data[addr - (((et4000->kasan_cfg_regs[2] << 8) | (et4000->kasan_cfg_regs[1])) + 3)] = val;
}
break;
case 6:
if ((et4000->kasan_cfg_regs[0] & 1) && (et4000->kasan_font_data[3] & !(val & 0x80)) && (et4000->get_korean_font_base & 0x7F) >= 0x20 && (et4000->get_korean_font_base & 0x7F) < 0x7F) {
if (((et4000->get_korean_font_base >> 7) & 0x7F) == (et4000->svga.ksc5601_udc_area_msb[0] & 0x7F) && (et4000->svga.ksc5601_udc_area_msb[0] & 0x80))
fontdatksc5601_user[(et4000->get_korean_font_base & 0x7F) - 0x20].chr[et4000->get_korean_font_index] = et4000->kasan_font_data[2];
else if (((et4000->get_korean_font_base >> 7) & 0x7F) == (et4000->svga.ksc5601_udc_area_msb[1] & 0x7F) && (et4000->svga.ksc5601_udc_area_msb[1] & 0x80))
fontdatksc5601_user[96 + (et4000->get_korean_font_base & 0x7F) - 0x20].chr[et4000->get_korean_font_index] = et4000->kasan_font_data[2];
}
et4000->kasan_font_data[3] = val;
break;
default:
break;
}
} else
et4000_out(addr, val, priv);
}
uint32_t
get_et4000_addr(uint32_t addr, void *priv)
{
const svga_t *svga = (svga_t *) priv;
uint32_t nbank;
switch (svga->crtc[0x37] & 0x0B) {
case 0x00:
case 0x01:
nbank = 0;
addr &= 0xFFFF;
break;
case 0x02:
nbank = (addr & 1) << 1;
addr = (addr >> 1) & 0xFFFF;
break;
case 0x03:
nbank = addr & 3;
addr = (addr >> 2) & 0xFFFF;
break;
case 0x08:
case 0x09:
nbank = 0;
addr &= 0x3FFFF;
break;
case 0x0A:
nbank = (addr & 1) << 1;
addr = (addr >> 1) & 0x3FFFF;
break;
case 0x0B:
nbank = addr & 3;
addr = (addr >> 2) & 0x3FFFF;
break;
default:
nbank = 0;
break;
}
if (svga->vram_max >= 1024 * 1024) {
addr = (addr << 2) | (nbank & 3);
if ((svga->crtc[0x37] & 3) == 2)
addr >>= 1;
else if ((svga->crtc[0x37] & 3) < 2)
addr >>= 2;
} else if (svga->vram_max >= 512 * 1024) {
addr = (addr << 1) | ((nbank & 2) >> 1) | ((nbank & 1) << 19);
if ((svga->crtc[0x37] & 3) < 2)
addr >>= 1;
} else if (svga->vram_max >= 256 * 1024)
addr = addr | (nbank << 18);
else if (svga->vram_max > 128 * 1024) {
addr = (addr << 1) | ((nbank & 2) >> 1) | ((nbank & 1) << 17);
if ((svga->crtc[0x37] & 3) < 2)
addr >>= 1;
} else
addr = addr | (nbank << 16);
return addr;
}
static void
et4000_recalctimings(svga_t *svga)
{
const et4000_t *dev = (et4000_t *) svga->priv;
svga->ma_latch |= (svga->crtc[0x33] & 3) << 16;
svga->hblankstart = (((svga->crtc[0x3f] & 0x4) >> 2) << 8) + svga->crtc[2];
svga->ps_bit_bug = (dev->type == ET4000_TYPE_TC6058AF) && svga->lowres && ((svga->gdcreg[5] & 0x60) >= 0x40);
if (svga->crtc[0x35] & 1)
svga->vblankstart |= 0x400;
if (svga->crtc[0x35] & 2)
svga->vtotal |= 0x400;
if (svga->crtc[0x35] & 4)
svga->dispend |= 0x400;
if (svga->crtc[0x35] & 8)
svga->vsyncstart |= 0x400;
if (svga->crtc[0x35] & 0x10)
svga->split |= 0x400;
if (!svga->rowoffset && !svga->ps_bit_bug)
svga->rowoffset = 0x100;
if (svga->crtc[0x3f] & 1)
svga->htotal |= 0x100;
if (svga->attrregs[0x16] & 0x20) {
svga->hdisp <<= 1;
svga->dots_per_clock <<= 1;
}
switch (((svga->miscout >> 2) & 3) | ((svga->crtc[0x34] << 1) & 4)) {
case 0:
case 1:
break;
case 3:
svga->clock = (cpuclock * (double) (1ULL << 32)) / 40000000.0;
break;
case 5:
svga->clock = (cpuclock * (double) (1ULL << 32)) / 65000000.0;
break;
default:
svga->clock = (cpuclock * (double) (1ULL << 32)) / 36000000.0;
break;
}
switch (svga->bpp) {
case 15:
case 16:
svga->hdisp /= 2;
svga->dots_per_clock /= 2;
break;
case 24:
svga->hdisp /= 3;
svga->dots_per_clock /= 3;
break;
default:
break;
}
if (dev->type == ET4000_TYPE_KOREAN || dev->type == ET4000_TYPE_TRIGEM || dev->type == ET4000_TYPE_KASAN) {
if ((svga->render == svga_render_text_80) && ((svga->crtc[0x37] & 0x0A) == 0x0A)) {
if (dev->port_32cb_val & 0x80) {
svga->ma_latch -= 2;
svga->ca_adj = -2;
}
if ((dev->port_32cb_val & 0xB4) == ((svga->crtc[0x37] & 3) == 2 ? 0xB4 : 0xB0)) {
svga->render = svga_render_text_80_ksc5601;
}
}
}
if ((svga->bpp == 8) && ((svga->gdcreg[5] & 0x60) >= 0x40)) {
svga->map8 = svga->pallook;
if (svga->lowres)
svga->render = svga_render_8bpp_lowres;
else
svga->render = svga_render_8bpp_highres;
}
if ((svga->seqregs[0x0e] & 0x02) && ((svga->gdcreg[5] & 0x60) >= 0x40) && svga->lowres) {
svga->ma_latch <<= 1;
svga->rowoffset <<= 1;
svga->render = svga_render_8bpp_highres;
}
}
static void
et4000_kasan_recalctimings(svga_t *svga)
{
const et4000_t *et4000 = (et4000_t *) svga->priv;
et4000_recalctimings(svga);
if (svga->render == svga_render_text_80 && (et4000->kasan_cfg_regs[0] & 8)) {
svga->hdisp += svga->dots_per_clock;
svga->ma_latch -= 4;
svga->ca_adj = (et4000->kasan_cfg_regs[0] >> 6) - 3;
svga->ksc5601_sbyte_mask = (et4000->kasan_cfg_regs[0] & 4) << 5;
if ((et4000->kasan_cfg_regs[0] & 0x23) == 0x20 && (et4000->kasan_cfg_regs[4] & 0x80) && ((svga->crtc[0x37] & 0x0B) == 0x0A))
svga->render = svga_render_text_80_ksc5601;
}
}
static uint8_t
et4000_mca_read(int port, void *priv)
{
const et4000_t *et4000 = (et4000_t *) priv;
return (et4000->pos_regs[port & 7]);
}
static void
et4000_mca_write(int port, uint8_t val, void *priv)
{
et4000_t *et4000 = (et4000_t *) priv;
/* MCA does not write registers below 0x0100. */
if (port < 0x0102)
return;
/* Save the MCA register value. */
et4000->pos_regs[port & 7] = val;
}
static uint8_t
et4000_mca_feedb(UNUSED(void *priv))
{
return 1;
}
static void *
et4000_init(const device_t *info)
{
const char *bios_ver = NULL;
const char *fn;
et4000_t *dev;
int i;
dev = (et4000_t *) malloc(sizeof(et4000_t));
memset(dev, 0x00, sizeof(et4000_t));
dev->name = info->name;
dev->type = info->local;
fn = BIOS_ROM_PATH;
switch (dev->type) {
case ET4000_TYPE_TC6058AF: /* ISA ET4000AX (TC6058AF) */
case ET4000_TYPE_ISA: /* ISA ET4000AX */
dev->vram_size = device_get_config_int("memory") << 10;
video_inform(VIDEO_FLAG_TYPE_SPECIAL, &timing_et4000_isa);
svga_init(info, &dev->svga, dev, dev->vram_size,
et4000_recalctimings, et4000_in, et4000_out,
NULL, NULL);
io_sethandler(0x03c0, 32,
et4000_in, NULL, NULL, et4000_out, NULL, NULL, dev);
bios_ver = (char *) device_get_config_bios("bios_ver");
fn = (char *) device_get_bios_file(info, bios_ver, 0);
break;
case ET4000_TYPE_MCA: /* MCA ET4000AX */
dev->vram_size = 1024 << 10;
video_inform(VIDEO_FLAG_TYPE_SPECIAL, &timing_et4000_mca);
svga_init(info, &dev->svga, dev, dev->vram_size,
et4000_recalctimings, et4000_in, et4000_out,
NULL, NULL);
io_sethandler(0x03c0, 32,
et4000_in, NULL, NULL, et4000_out, NULL, NULL, dev);
dev->pos_regs[0] = 0xf2; /* ET4000 MCA board ID */
dev->pos_regs[1] = 0x80;
mca_add(et4000_mca_read, et4000_mca_write, et4000_mca_feedb, NULL, dev);
break;
case ET4000_TYPE_KOREAN: /* Korean ET4000 */
case ET4000_TYPE_TRIGEM: /* Trigem 286M ET4000 */
dev->vram_size = device_get_config_int("memory") << 10;
dev->port_22cb_val = 0x60;
dev->port_32cb_val = 0;
dev->svga.ksc5601_sbyte_mask = 0x80;
dev->svga.ksc5601_udc_area_msb[0] = 0xC9;
dev->svga.ksc5601_udc_area_msb[1] = 0xFE;
dev->svga.ksc5601_swap_mode = 0;
dev->svga.ksc5601_english_font_type = 0;
video_inform(VIDEO_FLAG_TYPE_SPECIAL, &timing_et4000_isa);
svga_init(info, &dev->svga, dev, dev->vram_size,
et4000_recalctimings, et4000k_in, et4000k_out,
NULL, NULL);
io_sethandler(0x03c0, 32,
et4000k_in, NULL, NULL, et4000k_out, NULL, NULL, dev);
io_sethandler(0x22cb, 1,
et4000k_in, NULL, NULL, et4000k_out, NULL, NULL, dev);
io_sethandler(0x22cf, 1,
et4000k_in, NULL, NULL, et4000k_out, NULL, NULL, dev);
io_sethandler(0x32cb, 1,
et4000k_in, NULL, NULL, et4000k_out, NULL, NULL, dev);
loadfont(KOREAN_FONT_ROM_PATH, 6);
fn = KOREAN_BIOS_ROM_PATH;
break;
case ET4000_TYPE_KASAN: /* Kasan ET4000 */
dev->vram_size = device_get_config_int("memory") << 10;
dev->svga.ksc5601_sbyte_mask = 0;
dev->svga.ksc5601_udc_area_msb[0] = 0xC9;
dev->svga.ksc5601_udc_area_msb[1] = 0xFE;
dev->svga.ksc5601_swap_mode = 0;
dev->svga.ksc5601_english_font_type = 0x1FF;
dev->kasan_cfg_index = 0;
for (i = 0; i < 16; i++)
dev->kasan_cfg_regs[i] = 0;
for (i = 0; i < 4; i++)
dev->kasan_font_data[i] = 0;
dev->kasan_cfg_regs[1] = 0x50;
dev->kasan_cfg_regs[2] = 2;
dev->kasan_cfg_regs[3] = 6;
dev->kasan_cfg_regs[4] = 0x78;
dev->kasan_cfg_regs[5] = 0xFF;
dev->kasan_cfg_regs[6] = 0xC9;
dev->kasan_cfg_regs[7] = 0xFE;
dev->kasan_access_addr = 0x250;
video_inform(VIDEO_FLAG_TYPE_SPECIAL, &timing_et4000_isa);
svga_init(info, &dev->svga, dev, dev->vram_size,
et4000_kasan_recalctimings, et4000_in, et4000_out,
NULL, NULL);
io_sethandler(0x03c0, 32,
et4000k_in, NULL, NULL, et4000k_out, NULL, NULL, dev);
io_sethandler(0x0250, 8,
et4000_kasan_in, NULL, NULL, et4000_kasan_out, NULL, NULL, dev);
io_sethandler(0x0258, 2,
et4000_kasan_in, NULL, NULL, et4000_kasan_out, NULL, NULL, dev);
loadfont(KASAN_FONT_ROM_PATH, 6);
fn = KASAN_BIOS_ROM_PATH;
break;
default:
break;
}
if (dev->type >= ET4000_TYPE_ISA)
dev->svga.ramdac = device_add(&sc1502x_ramdac_device);
dev->vram_mask = dev->vram_size - 1;
rom_init(&dev->bios_rom, fn,
0xc0000, 0x8000, 0x7fff, 0, MEM_MAPPING_EXTERNAL);
dev->svga.translate_address = get_et4000_addr;
dev->svga.packed_chain4 = 1;
return dev;
}
static void
et4000_close(void *priv)
{
et4000_t *dev = (et4000_t *) priv;
svga_close(&dev->svga);
free(dev);
}
static void
et4000_speed_changed(void *priv)
{
et4000_t *dev = (et4000_t *) priv;
svga_recalctimings(&dev->svga);
}
static void
et4000_force_redraw(void *priv)
{
et4000_t *dev = (et4000_t *) priv;
dev->svga.fullchange = changeframecount;
}
static int
et4000_available(void)
{
return rom_present(BIOS_ROM_PATH);
}
static int
et4000k_available(void)
{
return rom_present(KOREAN_BIOS_ROM_PATH) && rom_present(KOREAN_FONT_ROM_PATH);
}
static int
et4000_kasan_available(void)
{
return rom_present(KASAN_BIOS_ROM_PATH) && rom_present(KASAN_FONT_ROM_PATH);
}
static const device_config_t et4000_tc6058af_config[] = {
// clang-format off
{
.name = "memory",
.description = "Memory size",
.type = CONFIG_SELECTION,
.default_int = 512,
.selection = {
{
.description = "256 KB",
.value = 256
},
{
.description = "512 KB",
.value = 512
},
{
.description = "1 MB",
.value = 1024
},
{
.description = ""
}
}
},
{
.name = "bios_ver",
.description = "BIOS Version",
.type = CONFIG_BIOS,
.default_string = "v1_10",
.default_int = 0,
.file_filter = "",
.spinner = { 0 }, /*W1*/
.bios = {
{ .name = "Version 1.10", .internal_name = "v1_10", .bios_type = BIOS_NORMAL,
.files_no = 1, .local = 0, .size = 32768, .files = { TC6058AF_BIOS_ROM_PATH, "" } },
{ .name = "Version 1.21", .internal_name = "v1_21", .bios_type = BIOS_NORMAL,
.files_no = 1, .local = 0, .size = 32768, .files = { V1_21_BIOS_ROM_PATH, "" } },
{ .files_no = 0 }
},
},
{
.type = CONFIG_END
}
// clang-format on
};
static const device_config_t et4000_bios_config[] = {
// clang-format off
{
.name = "memory",
.description = "Memory size",
.type = CONFIG_SELECTION,
.default_int = 1024,
.selection = {
{
.description = "256 KB",
.value = 256
},
{
.description = "512 KB",
.value = 512
},
{
.description = "1 MB",
.value = 1024
},
{
.description = ""
}
}
},
{
.name = "bios_ver",
.description = "BIOS Version",
.type = CONFIG_BIOS,
.default_string = "v8_01",
.default_int = 0,
.file_filter = "",
.spinner = { 0 }, /*W1*/
.bios = {
{ .name = "Version 8.01", .internal_name = "v8_01", .bios_type = BIOS_NORMAL,
.files_no = 1, .local = 0, .size = 32768, .files = { BIOS_ROM_PATH, "" } },
{ .name = "Version 8.06", .internal_name = "v8_06", .bios_type = BIOS_NORMAL,
.files_no = 1, .local = 0, .size = 32768, .files = { V8_06_BIOS_ROM_PATH, "" } },
{ .files_no = 0 }
},
},
{
.type = CONFIG_END
}
// clang-format on
};
static const device_config_t et4000_config[] = {
// clang-format off
{
.name = "memory",
.description = "Memory size",
.type = CONFIG_SELECTION,
.default_int = 1024,
.selection = {
{
.description = "256 KB",
.value = 256
},
{
.description = "512 KB",
.value = 512
},
{
.description = "1 MB",
.value = 1024
},
{
.description = ""
}
}
},
{
.type = CONFIG_END
}
// clang-format on
};
const device_t et4000_tc6058af_isa_device = {
.name = "Tseng Labs ET4000AX (TC6058AF) (ISA)",
.internal_name = "et4000ax_tc6058af",
.flags = DEVICE_ISA,
.local = ET4000_TYPE_TC6058AF,
.init = et4000_init,
.close = et4000_close,
.reset = NULL,
{ .available = NULL },
.speed_changed = et4000_speed_changed,
.force_redraw = et4000_force_redraw,
.config = et4000_tc6058af_config
};
const device_t et4000_isa_device = {
.name = "Tseng Labs ET4000AX (ISA)",
.internal_name = "et4000ax",
.flags = DEVICE_ISA,
.local = ET4000_TYPE_ISA,
.init = et4000_init,
.close = et4000_close,
.reset = NULL,
{ .available = NULL },
.speed_changed = et4000_speed_changed,
.force_redraw = et4000_force_redraw,
.config = et4000_bios_config
};
const device_t et4000_mca_device = {
.name = "Tseng Labs ET4000AX (MCA)",
.internal_name = "et4000mca",
.flags = DEVICE_MCA,
.local = ET4000_TYPE_MCA,
.init = et4000_init,
.close = et4000_close,
.reset = NULL,
{ .available = et4000_available },
.speed_changed = et4000_speed_changed,
.force_redraw = et4000_force_redraw,
.config = et4000_config
};
const device_t et4000k_isa_device = {
.name = "Trigem Korean VGA (Tseng Labs ET4000AX Korean)",
.internal_name = "tgkorvga",
.flags = DEVICE_ISA,
.local = ET4000_TYPE_KOREAN,
.init = et4000_init,
.close = et4000_close,
.reset = NULL,
{ .available = et4000k_available },
.speed_changed = et4000_speed_changed,
.force_redraw = et4000_force_redraw,
.config = et4000_config
};
const device_t et4000k_tg286_isa_device = {
.name = "Trigem Korean VGA (Trigem 286M)",
.internal_name = "et4000k_tg286_isa",
.flags = DEVICE_ISA,
.local = ET4000_TYPE_TRIGEM,
.init = et4000_init,
.close = et4000_close,
.reset = NULL,
{ .available = et4000k_available },
.speed_changed = et4000_speed_changed,
.force_redraw = et4000_force_redraw,
.config = et4000_config
};
const device_t et4000_kasan_isa_device = {
.name = "Kasan Hangulmadang-16 VGA (Tseng Labs ET4000AX Korean)",
.internal_name = "kasan16vga",
.flags = DEVICE_ISA,
.local = ET4000_TYPE_KASAN,
.init = et4000_init,
.close = et4000_close,
.reset = NULL,
{ .available = et4000_kasan_available },
.speed_changed = et4000_speed_changed,
.force_redraw = et4000_force_redraw,
.config = et4000_config
};
``` | /content/code_sandbox/src/video/vid_et4000.c | c | 2016-06-25T22:29:10 | 2024-08-16T19:09:21 | 86Box | 86Box/86Box | 2,616 | 13,069 |
```c
/*
* 86Box A hypervisor and IBM PC system emulator that specializes in
* running old operating systems and software designed for IBM
* PC systems and compatibles from 1981 through fairly recent
* system designs based on the PCI bus.
*
* This file is part of the 86Box distribution.
*
* Voodoo Graphics, 2, Banshee, 3 emulation.
*
*
*
* Authors: Sarah Walker, <path_to_url
* leilei
*
*/
#include <stdarg.h>
#include <stdio.h>
#include <stdint.h>
#include <string.h>
#include <stdlib.h>
#include <stddef.h>
#include <wchar.h>
#include <math.h>
#define HAVE_STDARG_H
#include <86box/86box.h>
#include "cpu.h"
#include <86box/machine.h>
#include <86box/device.h>
#include <86box/mem.h>
#include <86box/pci.h>
#include <86box/rom.h>
#include <86box/timer.h>
#include <86box/device.h>
#include <86box/plat.h>
#include <86box/thread.h>
#include <86box/video.h>
#include <86box/vid_svga.h>
#include <86box/vid_voodoo_common.h>
#include <86box/vid_voodoo_blitter.h>
#include <86box/vid_voodoo_display.h>
#include <86box/vid_voodoo_dither.h>
#include <86box/vid_voodoo_fb.h>
#include <86box/vid_voodoo_fifo.h>
#include <86box/vid_voodoo_reg.h>
#include <86box/vid_voodoo_regs.h>
#include <86box/vid_voodoo_render.h>
#include <86box/vid_voodoo_texture.h>
rgba8_t rgb332[0x100];
rgba8_t ai44[0x100];
rgba8_t rgb565[0x10000];
rgba8_t argb1555[0x10000];
rgba8_t argb4444[0x10000];
rgba8_t ai88[0x10000];
int tris = 0;
#ifdef ENABLE_VOODOO_LOG
int voodoo_do_log = ENABLE_VOODOO_LOG;
static void
voodoo_log(const char *fmt, ...)
{
va_list ap;
if (voodoo_do_log) {
va_start(ap, fmt);
pclog_ex(fmt, ap);
va_end(ap);
}
}
#else
# define voodoo_log(fmt, ...)
#endif
void
voodoo_recalc(voodoo_t *voodoo)
{
uint32_t buffer_offset = ((voodoo->fbiInit2 >> 11) & 511) * 4096;
if (voodoo->type >= VOODOO_BANSHEE)
return;
voodoo->params.front_offset = voodoo->disp_buffer * buffer_offset;
voodoo->back_offset = voodoo->draw_buffer * buffer_offset;
voodoo->buffer_cutoff = TRIPLE_BUFFER ? (buffer_offset * 4) : (buffer_offset * 3);
if (TRIPLE_BUFFER)
voodoo->params.aux_offset = buffer_offset * 3;
else
voodoo->params.aux_offset = buffer_offset * 2;
switch (voodoo->lfbMode & LFB_WRITE_MASK) {
case LFB_WRITE_FRONT:
voodoo->fb_write_offset = voodoo->params.front_offset;
voodoo->fb_write_buffer = voodoo->disp_buffer;
break;
case LFB_WRITE_BACK:
voodoo->fb_write_offset = voodoo->back_offset;
voodoo->fb_write_buffer = voodoo->draw_buffer;
break;
default:
/*BreakNeck sets invalid LFB write buffer select*/
voodoo->fb_write_offset = voodoo->params.front_offset;
break;
}
switch (voodoo->lfbMode & LFB_READ_MASK) {
case LFB_READ_FRONT:
voodoo->fb_read_offset = voodoo->params.front_offset;
break;
case LFB_READ_BACK:
voodoo->fb_read_offset = voodoo->back_offset;
break;
case LFB_READ_AUX:
voodoo->fb_read_offset = voodoo->params.aux_offset;
break;
default:
fatal("voodoo_recalc : unknown lfb source\n");
}
switch (voodoo->params.fbzMode & FBZ_DRAW_MASK) {
case FBZ_DRAW_FRONT:
voodoo->params.draw_offset = voodoo->params.front_offset;
voodoo->fb_draw_buffer = voodoo->disp_buffer;
break;
case FBZ_DRAW_BACK:
voodoo->params.draw_offset = voodoo->back_offset;
voodoo->fb_draw_buffer = voodoo->draw_buffer;
break;
default:
fatal("voodoo_recalc : unknown draw buffer\n");
}
voodoo->block_width = ((voodoo->fbiInit1 >> 4) & 15) * 2;
if (voodoo->fbiInit6 & (1 << 30))
voodoo->block_width += 1;
if (voodoo->fbiInit1 & (1 << 24))
voodoo->block_width += 32;
voodoo->row_width = voodoo->block_width * 32 * 2;
voodoo->params.row_width = voodoo->row_width;
voodoo->aux_row_width = voodoo->row_width;
voodoo->params.aux_row_width = voodoo->aux_row_width;
}
static uint16_t
voodoo_readw(uint32_t addr, void *priv)
{
voodoo_t *voodoo = (voodoo_t *) priv;
addr &= 0xffffff;
cycles -= voodoo->read_time;
if ((addr & 0xc00000) == 0x400000) /*Framebuffer*/
{
if (SLI_ENABLED) {
const voodoo_set_t *set = voodoo->set;
int y = (addr >> 11) & 0x3ff;
if (y & 1)
voodoo = set->voodoos[1];
else
voodoo = set->voodoos[0];
}
voodoo->flush = 1;
while (!FIFO_EMPTY) {
voodoo_wake_fifo_thread_now(voodoo);
thread_wait_event(voodoo->fifo_not_full_event, 1);
}
voodoo_wait_for_render_thread_idle(voodoo);
voodoo->flush = 0;
return voodoo_fb_readw(addr, voodoo);
}
return 0xffff;
}
static uint32_t
voodoo_readl(uint32_t addr, void *priv)
{
voodoo_t *voodoo = (voodoo_t *) priv;
uint32_t temp = 0xffffffff;
int fifo_size;
voodoo->rd_count++;
addr &= 0xffffff;
cycles -= voodoo->read_time;
if (addr & 0x800000) { /*Texture*/
} else if (addr & 0x400000) /*Framebuffer*/
{
if (SLI_ENABLED) {
const voodoo_set_t *set = voodoo->set;
int y = (addr >> 11) & 0x3ff;
if (y & 1)
voodoo = set->voodoos[1];
else
voodoo = set->voodoos[0];
}
voodoo->flush = 1;
while (!FIFO_EMPTY) {
voodoo_wake_fifo_thread_now(voodoo);
thread_wait_event(voodoo->fifo_not_full_event, 1);
}
voodoo_wait_for_render_thread_idle(voodoo);
voodoo->flush = 0;
temp = voodoo_fb_readl(addr, voodoo);
} else
switch (addr & 0x3fc) {
case SST_status:
{
int fifo_entries = FIFO_ENTRIES;
int swap_count = voodoo->swap_count;
int written = voodoo->cmd_written + voodoo->cmd_written_fifo;
int busy = (written - voodoo->cmd_read) || (voodoo->cmdfifo_depth_rd != voodoo->cmdfifo_depth_wr);
if (SLI_ENABLED && voodoo->type != VOODOO_2) {
voodoo_t *voodoo_other = (voodoo == voodoo->set->voodoos[0]) ? voodoo->set->voodoos[1] : voodoo->set->voodoos[0];
int other_written = voodoo_other->cmd_written + voodoo_other->cmd_written_fifo;
if (voodoo_other->swap_count > swap_count)
swap_count = voodoo_other->swap_count;
if ((voodoo_other->fifo_write_idx - voodoo_other->fifo_read_idx) > fifo_entries)
fifo_entries = voodoo_other->fifo_write_idx - voodoo_other->fifo_read_idx;
if ((other_written - voodoo_other->cmd_read) || (voodoo_other->cmdfifo_depth_rd != voodoo_other->cmdfifo_depth_wr))
busy = 1;
if (!voodoo_other->voodoo_busy)
voodoo_wake_fifo_thread(voodoo_other);
}
fifo_size = 0xffff - fifo_entries;
temp = fifo_size << 12;
if (fifo_size < 0x40)
temp |= fifo_size;
else
temp |= 0x3f;
if (swap_count < 7)
temp |= (swap_count << 28);
else
temp |= (7 << 28);
if (!voodoo->v_retrace)
temp |= 0x40;
if (busy)
temp |= 0x380; /*Busy*/
if (!voodoo->voodoo_busy)
voodoo_wake_fifo_thread(voodoo);
}
break;
case SST_fbzColorPath:
voodoo_flush(voodoo);
temp = voodoo->params.fbzColorPath;
break;
case SST_fogMode:
voodoo_flush(voodoo);
temp = voodoo->params.fogMode;
break;
case SST_alphaMode:
voodoo_flush(voodoo);
temp = voodoo->params.alphaMode;
break;
case SST_fbzMode:
voodoo_flush(voodoo);
temp = voodoo->params.fbzMode;
break;
case SST_lfbMode:
voodoo_flush(voodoo);
temp = voodoo->lfbMode;
break;
case SST_clipLeftRight:
voodoo_flush(voodoo);
temp = voodoo->params.clipRight | (voodoo->params.clipLeft << 16);
break;
case SST_clipLowYHighY:
voodoo_flush(voodoo);
temp = voodoo->params.clipHighY | (voodoo->params.clipLowY << 16);
break;
case SST_stipple:
voodoo_flush(voodoo);
temp = voodoo->params.stipple;
break;
case SST_color0:
voodoo_flush(voodoo);
temp = voodoo->params.color0;
break;
case SST_color1:
voodoo_flush(voodoo);
temp = voodoo->params.color1;
break;
case SST_fbiPixelsIn:
temp = voodoo->fbiPixelsIn & 0xffffff;
break;
case SST_fbiChromaFail:
temp = voodoo->fbiChromaFail & 0xffffff;
break;
case SST_fbiZFuncFail:
temp = voodoo->fbiZFuncFail & 0xffffff;
break;
case SST_fbiAFuncFail:
temp = voodoo->fbiAFuncFail & 0xffffff;
break;
case SST_fbiPixelsOut:
temp = voodoo->fbiPixelsOut & 0xffffff;
break;
case SST_fbiInit4:
temp = voodoo->fbiInit4;
break;
case SST_fbiInit0:
temp = voodoo->fbiInit0;
break;
case SST_fbiInit1:
temp = voodoo->fbiInit1;
break;
case SST_fbiInit2:
if (voodoo->initEnable & 0x04)
temp = voodoo->dac_readdata;
else
temp = voodoo->fbiInit2;
break;
case SST_fbiInit3:
temp = voodoo->fbiInit3 | (1 << 10) | (2 << 8);
break;
case SST_vRetrace:
temp = voodoo->line & 0x1fff;
break;
case SST_hvRetrace:
{
uint32_t line_time = (uint32_t) (voodoo->line_time >> 32);
uint32_t diff = (timer_get_ts_int(&voodoo->timer) > (tsc & 0xffffffff)) ? (timer_get_ts_int(&voodoo->timer) - (tsc & 0xffffffff)) : 0;
uint32_t pre_div = diff * voodoo->h_total;
uint32_t post_div = pre_div / line_time;
uint32_t h_pos = (voodoo->h_total - 1) - post_div;
if (h_pos >= voodoo->h_total)
h_pos = 0;
temp = voodoo->line & 0x1fff;
temp |= (h_pos << 16);
}
break;
case SST_fbiInit5:
temp = voodoo->fbiInit5 & ~0x1ff;
break;
case SST_fbiInit6:
temp = voodoo->fbiInit6;
break;
case SST_fbiInit7:
temp = voodoo->fbiInit7 & ~0xff;
break;
case SST_cmdFifoBaseAddr:
temp = voodoo->cmdfifo_base >> 12;
temp |= (voodoo->cmdfifo_end >> 12) << 16;
break;
case SST_cmdFifoRdPtr:
temp = voodoo->cmdfifo_rp;
break;
case SST_cmdFifoAMin:
temp = voodoo->cmdfifo_amin;
break;
case SST_cmdFifoAMax:
temp = voodoo->cmdfifo_amax;
break;
case SST_cmdFifoDepth:
temp = voodoo->cmdfifo_depth_wr - voodoo->cmdfifo_depth_rd;
break;
default:
voodoo_log("voodoo_readl : bad addr %08X\n", addr);
temp = 0xffffffff;
}
return temp;
}
static void
voodoo_writew(uint32_t addr, uint16_t val, void *priv)
{
voodoo_t *voodoo = (voodoo_t *) priv;
voodoo->wr_count++;
addr &= 0xffffff;
cycles -= voodoo->write_time;
if ((addr & 0xc00000) == 0x400000) /*Framebuffer*/
voodoo_queue_command(voodoo, addr | FIFO_WRITEW_FB, val);
}
static void
voodoo_writel(uint32_t addr, uint32_t val, void *priv)
{
voodoo_t *voodoo = (voodoo_t *) priv;
voodoo->wr_count++;
addr &= 0xffffff;
if (addr == voodoo->last_write_addr + 4)
cycles -= voodoo->burst_time;
else
cycles -= voodoo->write_time;
voodoo->last_write_addr = addr;
if (addr & 0x800000) /*Texture*/
{
voodoo->tex_count++;
voodoo_queue_command(voodoo, addr | FIFO_WRITEL_TEX, val);
} else if (addr & 0x400000) /*Framebuffer*/
{
voodoo_queue_command(voodoo, addr | FIFO_WRITEL_FB, val);
} else if ((addr & 0x200000) && (voodoo->fbiInit7 & FBIINIT7_CMDFIFO_ENABLE)) {
#if 0
voodoo_log("Write CMDFIFO %08x(%08x) %08x %08x\n", addr, voodoo->cmdfifo_base + (addr & 0x3fffc), val, (voodoo->cmdfifo_base + (addr & 0x3fffc)) & voodoo->fb_mask);
#endif
*(uint32_t *) &voodoo->fb_mem[(voodoo->cmdfifo_base + (addr & 0x3fffc)) & voodoo->fb_mask] = val;
voodoo->cmdfifo_depth_wr++;
if ((voodoo->cmdfifo_depth_wr - voodoo->cmdfifo_depth_rd) < 20)
voodoo_wake_fifo_thread(voodoo);
} else
switch (addr & 0x3fc) {
case SST_intrCtrl:
fatal("intrCtrl write %08x\n", val);
break;
case SST_userIntrCMD:
fatal("userIntrCMD write %08x\n", val);
break;
case SST_swapbufferCMD:
voodoo->cmd_written++;
thread_wait_mutex(voodoo->swap_mutex);
voodoo->swap_count++;
thread_release_mutex(voodoo->swap_mutex);
if (voodoo->fbiInit7 & FBIINIT7_CMDFIFO_ENABLE)
return;
voodoo_queue_command(voodoo, addr | FIFO_WRITEL_REG, val);
if (!voodoo->voodoo_busy)
voodoo_wake_fifo_threads(voodoo->set, voodoo);
break;
case SST_triangleCMD:
if (voodoo->fbiInit7 & FBIINIT7_CMDFIFO_ENABLE)
return;
voodoo->cmd_written++;
voodoo_queue_command(voodoo, addr | FIFO_WRITEL_REG, val);
if (!voodoo->voodoo_busy)
voodoo_wake_fifo_threads(voodoo->set, voodoo);
break;
case SST_ftriangleCMD:
if (voodoo->fbiInit7 & FBIINIT7_CMDFIFO_ENABLE)
return;
voodoo->cmd_written++;
voodoo_queue_command(voodoo, addr | FIFO_WRITEL_REG, val);
if (!voodoo->voodoo_busy)
voodoo_wake_fifo_threads(voodoo->set, voodoo);
break;
case SST_fastfillCMD:
if (voodoo->fbiInit7 & FBIINIT7_CMDFIFO_ENABLE)
return;
voodoo->cmd_written++;
voodoo_queue_command(voodoo, addr | FIFO_WRITEL_REG, val);
if (!voodoo->voodoo_busy)
voodoo_wake_fifo_threads(voodoo->set, voodoo);
break;
case SST_nopCMD:
if (voodoo->fbiInit7 & FBIINIT7_CMDFIFO_ENABLE)
return;
voodoo->cmd_written++;
voodoo_queue_command(voodoo, addr | FIFO_WRITEL_REG, val);
if (!voodoo->voodoo_busy)
voodoo_wake_fifo_threads(voodoo->set, voodoo);
break;
case SST_fbiInit4:
if (voodoo->initEnable & 0x01) {
voodoo->fbiInit4 = val;
voodoo->read_time = pci_nonburst_time + pci_burst_time * ((voodoo->fbiInit4 & 1) ? 2 : 1);
#if 0
voodoo_log("fbiInit4 write %08x - read_time=%i\n", val, voodoo->read_time);
#endif
}
break;
case SST_backPorch:
voodoo->backPorch = val;
break;
case SST_videoDimensions:
voodoo->videoDimensions = val;
voodoo->h_disp = (val & 0xfff) + 1;
voodoo->v_disp = (val >> 16) & 0xfff;
if ((voodoo->v_disp == 386) || (voodoo->v_disp == 402) ||
(voodoo->v_disp == 482) || (voodoo->v_disp == 602))
voodoo->v_disp -= 2;
break;
case SST_fbiInit0:
if (voodoo->initEnable & 0x01) {
voodoo->fbiInit0 = val;
thread_wait_mutex(voodoo->force_blit_mutex);
voodoo->can_blit = (voodoo->fbiInit0 & FBIINIT0_VGA_PASS) ? 1 : 0;
if (!voodoo->can_blit)
voodoo->force_blit_count = 0;
thread_release_mutex(voodoo->force_blit_mutex);
if (voodoo->set->nr_cards == 2)
svga_set_override(voodoo->svga, (voodoo->set->voodoos[0]->fbiInit0 | voodoo->set->voodoos[1]->fbiInit0) & 1);
else
svga_set_override(voodoo->svga, val & 1);
if (val & FBIINIT0_GRAPHICS_RESET) {
/*Reset display/draw buffer selection. This may not actually
happen here on a real Voodoo*/
voodoo->disp_buffer = 0;
voodoo->draw_buffer = 1;
voodoo_recalc(voodoo);
voodoo->front_offset = voodoo->params.front_offset;
}
}
break;
case SST_fbiInit1:
if (voodoo->initEnable & 0x01) {
if ((voodoo->fbiInit1 & FBIINIT1_VIDEO_RESET) && !(val & FBIINIT1_VIDEO_RESET)) {
voodoo->line = 0;
thread_wait_mutex(voodoo->swap_mutex);
voodoo->swap_count = 0;
thread_release_mutex(voodoo->swap_mutex);
voodoo->retrace_count = 0;
}
voodoo->fbiInit1 = (val & ~5) | (voodoo->fbiInit1 & 5);
voodoo->write_time = pci_nonburst_time + pci_burst_time * ((voodoo->fbiInit1 & 2) ? 1 : 0);
voodoo->burst_time = pci_burst_time * ((voodoo->fbiInit1 & 2) ? 2 : 1);
#if 0
voodoo_log("fbiInit1 write %08x - write_time=%i burst_time=%i\n", val, voodoo->write_time, voodoo->burst_time);
#endif
}
break;
case SST_fbiInit2:
if (voodoo->initEnable & 0x01) {
voodoo->fbiInit2 = val;
voodoo_recalc(voodoo);
}
break;
case SST_fbiInit3:
if (voodoo->initEnable & 0x01)
voodoo->fbiInit3 = val;
break;
case SST_hSync:
voodoo->hSync = val;
voodoo->h_total = (val & 0xffff) + (val >> 16);
voodoo_pixelclock_update(voodoo);
break;
case SST_vSync:
voodoo->vSync = val;
voodoo->v_total = (val & 0xffff) + (val >> 16);
break;
case SST_clutData:
voodoo->clutData[(val >> 24) & 0x3f].b = val & 0xff;
voodoo->clutData[(val >> 24) & 0x3f].g = (val >> 8) & 0xff;
voodoo->clutData[(val >> 24) & 0x3f].r = (val >> 16) & 0xff;
if (val & 0x20000000) {
voodoo->clutData[(val >> 24) & 0x3f].b = 255;
voodoo->clutData[(val >> 24) & 0x3f].g = 255;
voodoo->clutData[(val >> 24) & 0x3f].r = 255;
}
voodoo->clutData_dirty = 1;
break;
case SST_dacData:
voodoo->dac_reg = (val >> 8) & 7;
voodoo->dac_readdata = 0xff;
if (val & 0x800) {
// voodoo_log(" dacData read %i %02X\n", voodoo->dac_reg, voodoo->dac_data[7]);
if (voodoo->dac_reg == 5) {
switch (voodoo->dac_data[7]) {
case 0x01:
voodoo->dac_readdata = 0x55;
break;
case 0x07:
voodoo->dac_readdata = 0x71;
break;
case 0x0b:
voodoo->dac_readdata = 0x79;
break;
default:
break;
}
} else
voodoo->dac_readdata = voodoo->dac_data[voodoo->dac_readdata & 7];
} else {
if (voodoo->dac_reg == 5) {
if (!voodoo->dac_reg_ff)
voodoo->dac_pll_regs[voodoo->dac_data[4] & 0xf] = (voodoo->dac_pll_regs[voodoo->dac_data[4] & 0xf] & 0xff00) | val;
else
voodoo->dac_pll_regs[voodoo->dac_data[4] & 0xf] = (voodoo->dac_pll_regs[voodoo->dac_data[4] & 0xf] & 0xff) | (val << 8);
#if 0
voodoo_log("Write PLL reg %x %04x\n", voodoo->dac_data[4] & 0xf, voodoo->dac_pll_regs[voodoo->dac_data[4] & 0xf]);
#endif
voodoo->dac_reg_ff = !voodoo->dac_reg_ff;
if (!voodoo->dac_reg_ff)
voodoo->dac_data[4]++;
} else {
voodoo->dac_data[voodoo->dac_reg] = val & 0xff;
voodoo->dac_reg_ff = 0;
}
voodoo_pixelclock_update(voodoo);
}
break;
case SST_scrFilter:
if (voodoo->initEnable & 0x01) {
voodoo->scrfilterEnabled = 1;
voodoo->scrfilterThreshold = val; /* update the threshold values and generate a new lookup table if necessary */
if (val < 1)
voodoo->scrfilterEnabled = 0;
voodoo_threshold_check(voodoo);
voodoo_log("Voodoo Filter: %06x\n", val);
}
break;
case SST_fbiInit5:
if (voodoo->initEnable & 0x01)
voodoo->fbiInit5 = (val & ~0x41e6) | (voodoo->fbiInit5 & 0x41e6);
break;
case SST_fbiInit6:
if (voodoo->initEnable & 0x01)
voodoo->fbiInit6 = val;
break;
case SST_fbiInit7:
if (voodoo->initEnable & 0x01) {
voodoo->fbiInit7 = val;
voodoo->cmdfifo_enabled = val & 0x100;
}
break;
case SST_cmdFifoBaseAddr:
voodoo->cmdfifo_base = (val & 0x3ff) << 12;
voodoo->cmdfifo_end = ((val >> 16) & 0x3ff) << 12;
#if 0
voodoo_log("CMDFIFO base=%08x end=%08x\n", voodoo->cmdfifo_base, voodoo->cmdfifo_end);
#endif
break;
case SST_cmdFifoRdPtr:
voodoo->cmdfifo_rp = val;
break;
case SST_cmdFifoAMin:
voodoo->cmdfifo_amin = val;
break;
case SST_cmdFifoAMax:
voodoo->cmdfifo_amax = val;
break;
case SST_cmdFifoDepth:
voodoo->cmdfifo_depth_rd = 0;
voodoo->cmdfifo_depth_wr = val & 0xffff;
break;
default:
if (voodoo->fbiInit7 & FBIINIT7_CMDFIFO_ENABLE) {
voodoo_log("Unknown register write in CMDFIFO mode %08x %08x\n", addr, val);
} else {
voodoo_queue_command(voodoo, addr | FIFO_WRITEL_REG, val);
}
break;
}
}
static uint16_t
voodoo_snoop_readw(uint32_t addr, void *priv)
{
const voodoo_set_t *set = (voodoo_set_t *) priv;
return voodoo_readw(addr, set->voodoos[0]);
}
static uint32_t
voodoo_snoop_readl(uint32_t addr, void *priv)
{
const voodoo_set_t *set = (voodoo_set_t *) priv;
return voodoo_readl(addr, set->voodoos[0]);
}
static void
voodoo_snoop_writew(uint32_t addr, uint16_t val, void *priv)
{
const voodoo_set_t *set = (voodoo_set_t *) priv;
voodoo_writew(addr, val, set->voodoos[0]);
voodoo_writew(addr, val, set->voodoos[1]);
}
static void
voodoo_snoop_writel(uint32_t addr, uint32_t val, void *priv)
{
const voodoo_set_t *set = (voodoo_set_t *) priv;
voodoo_writel(addr, val, set->voodoos[0]);
voodoo_writel(addr, val, set->voodoos[1]);
}
static void
voodoo_recalcmapping(voodoo_set_t *set)
{
if (set->nr_cards == 2) {
if (set->voodoos[0]->pci_enable && set->voodoos[0]->memBaseAddr) {
if (set->voodoos[0]->type == VOODOO_2 && set->voodoos[1]->initEnable & (1 << 23)) {
voodoo_log("voodoo_recalcmapping (pri) with snoop : memBaseAddr %08X\n", set->voodoos[0]->memBaseAddr);
mem_mapping_disable(&set->voodoos[0]->mapping);
mem_mapping_set_addr(&set->snoop_mapping, set->voodoos[0]->memBaseAddr, 0x01000000);
} else if (set->voodoos[1]->pci_enable && (set->voodoos[0]->memBaseAddr == set->voodoos[1]->memBaseAddr)) {
voodoo_log("voodoo_recalcmapping (pri) (sec) same addr : memBaseAddr %08X\n", set->voodoos[0]->memBaseAddr);
mem_mapping_disable(&set->voodoos[0]->mapping);
mem_mapping_disable(&set->voodoos[1]->mapping);
mem_mapping_set_addr(&set->snoop_mapping, set->voodoos[0]->memBaseAddr, 0x01000000);
return;
} else {
voodoo_log("voodoo_recalcmapping (pri) : memBaseAddr %08X\n", set->voodoos[0]->memBaseAddr);
mem_mapping_disable(&set->snoop_mapping);
mem_mapping_set_addr(&set->voodoos[0]->mapping, set->voodoos[0]->memBaseAddr, 0x01000000);
}
} else {
voodoo_log("voodoo_recalcmapping (pri) : disabled\n");
mem_mapping_disable(&set->voodoos[0]->mapping);
}
if (set->voodoos[1]->pci_enable && set->voodoos[1]->memBaseAddr) {
voodoo_log("voodoo_recalcmapping (sec) : memBaseAddr %08X\n", set->voodoos[1]->memBaseAddr);
mem_mapping_set_addr(&set->voodoos[1]->mapping, set->voodoos[1]->memBaseAddr, 0x01000000);
} else {
voodoo_log("voodoo_recalcmapping (sec) : disabled\n");
mem_mapping_disable(&set->voodoos[1]->mapping);
}
} else {
voodoo_t *voodoo = set->voodoos[0];
if (voodoo->pci_enable && voodoo->memBaseAddr) {
voodoo_log("voodoo_recalcmapping : memBaseAddr %08X\n", voodoo->memBaseAddr);
mem_mapping_set_addr(&voodoo->mapping, voodoo->memBaseAddr, 0x01000000);
} else {
voodoo_log("voodoo_recalcmapping : disabled\n");
mem_mapping_disable(&voodoo->mapping);
}
}
}
uint8_t
voodoo_pci_read(int func, int addr, void *priv)
{
const voodoo_t *voodoo = (voodoo_t *) priv;
if (func)
return 0;
#if 0
voodoo_log("Voodoo PCI read %08X PC=%08x\n", addr, cpu_state.pc);
#endif
switch (addr) {
case 0x00:
return 0x1a; /*3Dfx*/
case 0x01:
return 0x12;
case 0x02:
if (voodoo->type == VOODOO_2)
return 0x02; /*Voodoo 2*/
else
return 0x01; /*SST-1 (Voodoo Graphics)*/
case 0x03:
return 0x00;
case 0x04:
return voodoo->pci_enable ? 0x02 : 0x00; /*Respond to memory accesses*/
case 0x08:
return 2; /*Revision ID*/
case 0x09:
return 0; /*Programming interface*/
case 0x0a:
return 0;
case 0x0b:
return 0x04;
case 0x10:
return 0x00; /*memBaseAddr*/
case 0x11:
return 0x00;
case 0x12:
return 0x00;
case 0x13:
return voodoo->memBaseAddr >> 24;
case 0x40:
return voodoo->initEnable & 0xff;
case 0x41:
if (voodoo->type == VOODOO_2)
return 0x50 | ((voodoo->initEnable >> 8) & 0x0f);
return (voodoo->initEnable >> 8) & 0x0f;
case 0x42:
return (voodoo->initEnable >> 16) & 0xff;
case 0x43:
return (voodoo->initEnable >> 24) & 0xff;
default:
break;
}
return 0;
}
void
voodoo_pci_write(int func, int addr, uint8_t val, void *priv)
{
voodoo_t *voodoo = (voodoo_t *) priv;
if (func)
return;
#if 0
voodoo_log("Voodoo PCI write %04X %02X PC=%08x\n", addr, val, cpu_state.pc);
#endif
switch (addr) {
case 0x04:
voodoo->pci_enable = val & 2;
voodoo_recalcmapping(voodoo->set);
break;
case 0x13:
voodoo->memBaseAddr = val << 24;
voodoo_recalcmapping(voodoo->set);
break;
case 0x40:
voodoo->initEnable = (voodoo->initEnable & ~0x000000ff) | val;
break;
case 0x41:
voodoo->initEnable = (voodoo->initEnable & ~0x0000ff00) | (val << 8);
break;
case 0x42:
voodoo->initEnable = (voodoo->initEnable & ~0x00ff0000) | (val << 16);
voodoo_recalcmapping(voodoo->set);
break;
case 0x43:
voodoo->initEnable = (voodoo->initEnable & ~0xff000000) | (val << 24);
voodoo_recalcmapping(voodoo->set);
break;
default:
break;
}
}
static void
voodoo_speed_changed(void *priv)
{
const voodoo_set_t *voodoo_set = (voodoo_set_t *) priv;
voodoo_pixelclock_update(voodoo_set->voodoos[0]);
voodoo_set->voodoos[0]->read_time = pci_nonburst_time + pci_burst_time * ((voodoo_set->voodoos[0]->fbiInit4 & 1) ? 2 : 1);
voodoo_set->voodoos[0]->write_time = pci_nonburst_time + pci_burst_time * ((voodoo_set->voodoos[0]->fbiInit1 & 2) ? 1 : 0);
voodoo_set->voodoos[0]->burst_time = pci_burst_time * ((voodoo_set->voodoos[0]->fbiInit1 & 2) ? 2 : 1);
if (voodoo_set->nr_cards == 2) {
voodoo_pixelclock_update(voodoo_set->voodoos[1]);
voodoo_set->voodoos[1]->read_time = pci_nonburst_time + pci_burst_time * ((voodoo_set->voodoos[1]->fbiInit4 & 1) ? 2 : 1);
voodoo_set->voodoos[1]->write_time = pci_nonburst_time + pci_burst_time * ((voodoo_set->voodoos[1]->fbiInit1 & 2) ? 1 : 0);
voodoo_set->voodoos[1]->burst_time = pci_burst_time * ((voodoo_set->voodoos[1]->fbiInit1 & 2) ? 2 : 1);
}
#if 0
voodoo_log("Voodoo read_time=%i write_time=%i burst_time=%i %08x %08x\n", voodoo->read_time, voodoo->write_time, voodoo->burst_time, voodoo->fbiInit1, voodoo->fbiInit4);
#endif
}
static void
voodoo_force_blit(void *priv)
{
const voodoo_set_t *voodoo_set = (voodoo_set_t *) priv;
thread_wait_mutex(voodoo_set->voodoos[0]->force_blit_mutex);
if (voodoo_set->voodoos[0]->can_blit) {
voodoo_set->voodoos[0]->force_blit_count++;
}
thread_release_mutex(voodoo_set->voodoos[0]->force_blit_mutex);
if (voodoo_set->nr_cards == 2) {
thread_wait_mutex(voodoo_set->voodoos[1]->force_blit_mutex);
if (voodoo_set->voodoos[1]->can_blit) {
voodoo_set->voodoos[1]->force_blit_count++;
}
thread_release_mutex(voodoo_set->voodoos[1]->force_blit_mutex);
}
}
void *
voodoo_card_init(void)
{
int c;
voodoo_t *voodoo = malloc(sizeof(voodoo_t));
memset(voodoo, 0, sizeof(voodoo_t));
voodoo->bilinear_enabled = device_get_config_int("bilinear");
voodoo->dithersub_enabled = device_get_config_int("dithersub");
voodoo->scrfilter = device_get_config_int("dacfilter");
voodoo->texture_size = device_get_config_int("texture_memory");
voodoo->texture_mask = (voodoo->texture_size << 20) - 1;
voodoo->fb_size = device_get_config_int("framebuffer_memory");
voodoo->fb_mask = (voodoo->fb_size << 20) - 1;
voodoo->render_threads = device_get_config_int("render_threads");
voodoo->odd_even_mask = voodoo->render_threads - 1;
#ifndef NO_CODEGEN
voodoo->use_recompiler = device_get_config_int("recompiler");
#endif
voodoo->type = device_get_config_int("type");
switch (voodoo->type) {
case VOODOO_1:
voodoo->dual_tmus = 0;
break;
case VOODOO_SB50:
voodoo->dual_tmus = 1;
break;
case VOODOO_2:
voodoo->dual_tmus = 1;
break;
default:
break;
}
if (voodoo->type == VOODOO_2) /*generate filter lookup tables*/
voodoo_generate_filter_v2(voodoo);
else
voodoo_generate_filter_v1(voodoo);
pci_add_card(PCI_ADD_NORMAL, voodoo_pci_read, voodoo_pci_write, voodoo, &voodoo->pci_slot);
mem_mapping_add(&voodoo->mapping, 0, 0, NULL, voodoo_readw, voodoo_readl, NULL, voodoo_writew, voodoo_writel, NULL, MEM_MAPPING_EXTERNAL, voodoo);
voodoo->fb_mem = malloc(4 * 1024 * 1024);
voodoo->tex_mem[0] = malloc(voodoo->texture_size * 1024 * 1024);
if (voodoo->dual_tmus)
voodoo->tex_mem[1] = malloc(voodoo->texture_size * 1024 * 1024);
voodoo->tex_mem_w[0] = (uint16_t *) voodoo->tex_mem[0];
voodoo->tex_mem_w[1] = (uint16_t *) voodoo->tex_mem[1];
for (c = 0; c < TEX_CACHE_MAX; c++) {
voodoo->texture_cache[0][c].data = malloc((256 * 256 + 256 * 256 + 128 * 128 + 64 * 64 + 32 * 32 + 16 * 16 + 8 * 8 + 4 * 4 + 2 * 2) * 4);
voodoo->texture_cache[0][c].base = -1; /*invalid*/
voodoo->texture_cache[0][c].refcount = 0;
if (voodoo->dual_tmus) {
voodoo->texture_cache[1][c].data = malloc((256 * 256 + 256 * 256 + 128 * 128 + 64 * 64 + 32 * 32 + 16 * 16 + 8 * 8 + 4 * 4 + 2 * 2) * 4);
voodoo->texture_cache[1][c].base = -1; /*invalid*/
voodoo->texture_cache[1][c].refcount = 0;
}
}
timer_add(&voodoo->timer, voodoo_callback, voodoo, 1);
voodoo->svga = svga_get_pri();
voodoo->fbiInit0 = 0;
voodoo->wake_fifo_thread = thread_create_event();
voodoo->wake_render_thread[0] = thread_create_event();
voodoo->wake_render_thread[1] = thread_create_event();
voodoo->wake_render_thread[2] = thread_create_event();
voodoo->wake_render_thread[3] = thread_create_event();
voodoo->wake_main_thread = thread_create_event();
voodoo->fifo_not_full_event = thread_create_event();
voodoo->render_not_full_event[0] = thread_create_event();
voodoo->render_not_full_event[1] = thread_create_event();
voodoo->render_not_full_event[2] = thread_create_event();
voodoo->render_not_full_event[3] = thread_create_event();
voodoo->fifo_thread_run = 1;
voodoo->fifo_thread = thread_create(voodoo_fifo_thread, voodoo);
voodoo->render_thread_run[0] = 1;
voodoo->render_thread[0] = thread_create(voodoo_render_thread_1, voodoo);
if (voodoo->render_threads >= 2) {
voodoo->render_thread_run[1] = 1;
voodoo->render_thread[1] = thread_create(voodoo_render_thread_2, voodoo);
}
if (voodoo->render_threads == 4) {
voodoo->render_thread_run[2] = 1;
voodoo->render_thread[2] = thread_create(voodoo_render_thread_3, voodoo);
voodoo->render_thread_run[3] = 1;
voodoo->render_thread[3] = thread_create(voodoo_render_thread_4, voodoo);
}
voodoo->swap_mutex = thread_create_mutex();
timer_add(&voodoo->wake_timer, voodoo_wake_timer, (void *) voodoo, 0);
for (c = 0; c < 0x100; c++) {
rgb332[c].r = c & 0xe0;
rgb332[c].g = (c << 3) & 0xe0;
rgb332[c].b = (c << 6) & 0xc0;
rgb332[c].r = rgb332[c].r | (rgb332[c].r >> 3) | (rgb332[c].r >> 6);
rgb332[c].g = rgb332[c].g | (rgb332[c].g >> 3) | (rgb332[c].g >> 6);
rgb332[c].b = rgb332[c].b | (rgb332[c].b >> 2);
rgb332[c].b = rgb332[c].b | (rgb332[c].b >> 4);
rgb332[c].a = 0xff;
ai44[c].a = (c & 0xf0) | ((c & 0xf0) >> 4);
ai44[c].r = (c & 0x0f) | ((c & 0x0f) << 4);
ai44[c].g = ai44[c].b = ai44[c].r;
}
for (c = 0; c < 0x10000; c++) {
rgb565[c].r = (c >> 8) & 0xf8;
rgb565[c].g = (c >> 3) & 0xfc;
rgb565[c].b = (c << 3) & 0xf8;
rgb565[c].r |= (rgb565[c].r >> 5);
rgb565[c].g |= (rgb565[c].g >> 6);
rgb565[c].b |= (rgb565[c].b >> 5);
rgb565[c].a = 0xff;
argb1555[c].r = (c >> 7) & 0xf8;
argb1555[c].g = (c >> 2) & 0xf8;
argb1555[c].b = (c << 3) & 0xf8;
argb1555[c].r |= (argb1555[c].r >> 5);
argb1555[c].g |= (argb1555[c].g >> 5);
argb1555[c].b |= (argb1555[c].b >> 5);
argb1555[c].a = (c & 0x8000) ? 0xff : 0;
argb4444[c].a = (c >> 8) & 0xf0;
argb4444[c].r = (c >> 4) & 0xf0;
argb4444[c].g = c & 0xf0;
argb4444[c].b = (c << 4) & 0xf0;
argb4444[c].a |= (argb4444[c].a >> 4);
argb4444[c].r |= (argb4444[c].r >> 4);
argb4444[c].g |= (argb4444[c].g >> 4);
argb4444[c].b |= (argb4444[c].b >> 4);
ai88[c].a = (c >> 8);
ai88[c].r = c & 0xff;
ai88[c].g = c & 0xff;
ai88[c].b = c & 0xff;
}
#ifndef NO_CODEGEN
voodoo_codegen_init(voodoo);
#endif
voodoo->disp_buffer = 0;
voodoo->draw_buffer = 1;
voodoo->force_blit_count = 0;
voodoo->can_blit = 0;
voodoo->force_blit_mutex = thread_create_mutex();
return voodoo;
}
void *
voodoo_2d3d_card_init(int type)
{
int c;
voodoo_t *voodoo = malloc(sizeof(voodoo_t));
memset(voodoo, 0, sizeof(voodoo_t));
voodoo->bilinear_enabled = device_get_config_int("bilinear");
voodoo->dithersub_enabled = device_get_config_int("dithersub");
voodoo->scrfilter = device_get_config_int("dacfilter");
voodoo->render_threads = device_get_config_int("render_threads");
voodoo->odd_even_mask = voodoo->render_threads - 1;
#ifndef NO_CODEGEN
voodoo->use_recompiler = device_get_config_int("recompiler");
#endif
voodoo->type = type;
voodoo->dual_tmus = (type == VOODOO_3) ? 1 : 0;
/*generate filter lookup tables*/
voodoo_generate_filter_v2(voodoo);
for (c = 0; c < TEX_CACHE_MAX; c++) {
voodoo->texture_cache[0][c].data = malloc((256 * 256 + 256 * 256 + 128 * 128 + 64 * 64 + 32 * 32 + 16 * 16 + 8 * 8 + 4 * 4 + 2 * 2) * 4);
voodoo->texture_cache[0][c].base = -1; /*invalid*/
voodoo->texture_cache[0][c].refcount = 0;
if (voodoo->dual_tmus) {
voodoo->texture_cache[1][c].data = malloc((256 * 256 + 256 * 256 + 128 * 128 + 64 * 64 + 32 * 32 + 16 * 16 + 8 * 8 + 4 * 4 + 2 * 2) * 4);
voodoo->texture_cache[1][c].base = -1; /*invalid*/
voodoo->texture_cache[1][c].refcount = 0;
}
}
timer_add(&voodoo->timer, voodoo_callback, voodoo, 1);
voodoo->fbiInit0 = 0;
voodoo->wake_fifo_thread = thread_create_event();
voodoo->wake_render_thread[0] = thread_create_event();
voodoo->wake_render_thread[1] = thread_create_event();
voodoo->wake_render_thread[2] = thread_create_event();
voodoo->wake_render_thread[3] = thread_create_event();
voodoo->wake_main_thread = thread_create_event();
voodoo->fifo_not_full_event = thread_create_event();
voodoo->render_not_full_event[0] = thread_create_event();
voodoo->render_not_full_event[1] = thread_create_event();
voodoo->render_not_full_event[2] = thread_create_event();
voodoo->render_not_full_event[3] = thread_create_event();
voodoo->fifo_thread_run = 1;
voodoo->fifo_thread = thread_create(voodoo_fifo_thread, voodoo);
voodoo->render_thread_run[0] = 1;
voodoo->render_thread[0] = thread_create(voodoo_render_thread_1, voodoo);
if (voodoo->render_threads >= 2) {
voodoo->render_thread_run[1] = 1;
voodoo->render_thread[1] = thread_create(voodoo_render_thread_2, voodoo);
}
if (voodoo->render_threads == 4) {
voodoo->render_thread_run[2] = 1;
voodoo->render_thread[2] = thread_create(voodoo_render_thread_3, voodoo);
voodoo->render_thread_run[3] = 1;
voodoo->render_thread[3] = thread_create(voodoo_render_thread_4, voodoo);
}
voodoo->swap_mutex = thread_create_mutex();
timer_add(&voodoo->wake_timer, voodoo_wake_timer, (void *) voodoo, 0);
for (c = 0; c < 0x100; c++) {
rgb332[c].r = c & 0xe0;
rgb332[c].g = (c << 3) & 0xe0;
rgb332[c].b = (c << 6) & 0xc0;
rgb332[c].r = rgb332[c].r | (rgb332[c].r >> 3) | (rgb332[c].r >> 6);
rgb332[c].g = rgb332[c].g | (rgb332[c].g >> 3) | (rgb332[c].g >> 6);
rgb332[c].b = rgb332[c].b | (rgb332[c].b >> 2);
rgb332[c].b = rgb332[c].b | (rgb332[c].b >> 4);
rgb332[c].a = 0xff;
ai44[c].a = (c & 0xf0) | ((c & 0xf0) >> 4);
ai44[c].r = (c & 0x0f) | ((c & 0x0f) << 4);
ai44[c].g = ai44[c].b = ai44[c].r;
}
for (c = 0; c < 0x10000; c++) {
rgb565[c].r = (c >> 8) & 0xf8;
rgb565[c].g = (c >> 3) & 0xfc;
rgb565[c].b = (c << 3) & 0xf8;
rgb565[c].r |= (rgb565[c].r >> 5);
rgb565[c].g |= (rgb565[c].g >> 6);
rgb565[c].b |= (rgb565[c].b >> 5);
rgb565[c].a = 0xff;
argb1555[c].r = (c >> 7) & 0xf8;
argb1555[c].g = (c >> 2) & 0xf8;
argb1555[c].b = (c << 3) & 0xf8;
argb1555[c].r |= (argb1555[c].r >> 5);
argb1555[c].g |= (argb1555[c].g >> 5);
argb1555[c].b |= (argb1555[c].b >> 5);
argb1555[c].a = (c & 0x8000) ? 0xff : 0;
argb4444[c].a = (c >> 8) & 0xf0;
argb4444[c].r = (c >> 4) & 0xf0;
argb4444[c].g = c & 0xf0;
argb4444[c].b = (c << 4) & 0xf0;
argb4444[c].a |= (argb4444[c].a >> 4);
argb4444[c].r |= (argb4444[c].r >> 4);
argb4444[c].g |= (argb4444[c].g >> 4);
argb4444[c].b |= (argb4444[c].b >> 4);
ai88[c].a = (c >> 8);
ai88[c].r = c & 0xff;
ai88[c].g = c & 0xff;
ai88[c].b = c & 0xff;
}
#ifndef NO_CODEGEN
voodoo_codegen_init(voodoo);
#endif
voodoo->disp_buffer = 0;
voodoo->draw_buffer = 1;
voodoo->force_blit_count = 0;
voodoo->can_blit = 0;
voodoo->force_blit_mutex = thread_create_mutex();
return voodoo;
}
void *
voodoo_init(UNUSED(const device_t *info))
{
voodoo_set_t *voodoo_set = malloc(sizeof(voodoo_set_t));
uint32_t tmuConfig = 1;
int type;
memset(voodoo_set, 0, sizeof(voodoo_set_t));
type = device_get_config_int("type");
voodoo_set->nr_cards = device_get_config_int("sli") ? 2 : 1;
voodoo_set->voodoos[0] = voodoo_card_init();
voodoo_set->voodoos[0]->set = voodoo_set;
if (voodoo_set->nr_cards == 2) {
voodoo_set->voodoos[1] = voodoo_card_init();
voodoo_set->voodoos[1]->set = voodoo_set;
if (type == VOODOO_2) {
voodoo_set->voodoos[0]->fbiInit5 |= FBIINIT5_MULTI_CVG;
voodoo_set->voodoos[1]->fbiInit5 |= FBIINIT5_MULTI_CVG;
} else {
voodoo_set->voodoos[0]->fbiInit1 |= FBIINIT1_MULTI_SST;
voodoo_set->voodoos[1]->fbiInit1 |= FBIINIT1_MULTI_SST;
}
}
switch (type) {
case VOODOO_1:
if (voodoo_set->nr_cards == 2)
tmuConfig = 1 | (3 << 3);
else
tmuConfig = 1;
break;
case VOODOO_SB50:
if (voodoo_set->nr_cards == 2)
tmuConfig = 1 | (3 << 3) | (3 << 6) | (2 << 9);
else
tmuConfig = 1 | (3 << 6);
break;
case VOODOO_2:
tmuConfig = 1 | (3 << 6);
break;
default:
break;
}
voodoo_set->voodoos[0]->tmuConfig = tmuConfig;
if (voodoo_set->nr_cards == 2)
voodoo_set->voodoos[1]->tmuConfig = tmuConfig;
mem_mapping_add(&voodoo_set->snoop_mapping, 0, 0, NULL, voodoo_snoop_readw, voodoo_snoop_readl, NULL, voodoo_snoop_writew, voodoo_snoop_writel, NULL, MEM_MAPPING_EXTERNAL, voodoo_set);
return voodoo_set;
}
void
voodoo_card_close(voodoo_t *voodoo)
{
voodoo->fifo_thread_run = 0;
thread_set_event(voodoo->wake_fifo_thread);
thread_wait(voodoo->fifo_thread);
voodoo->render_thread_run[0] = 0;
thread_set_event(voodoo->wake_render_thread[0]);
thread_wait(voodoo->render_thread[0]);
if (voodoo->render_threads >= 2) {
voodoo->render_thread_run[1] = 0;
thread_set_event(voodoo->wake_render_thread[1]);
thread_wait(voodoo->render_thread[1]);
}
if (voodoo->render_threads == 4) {
voodoo->render_thread_run[2] = 0;
thread_set_event(voodoo->wake_render_thread[2]);
thread_wait(voodoo->render_thread[2]);
voodoo->render_thread_run[3] = 0;
thread_set_event(voodoo->wake_render_thread[3]);
thread_wait(voodoo->render_thread[3]);
}
thread_destroy_event(voodoo->fifo_not_full_event);
thread_destroy_event(voodoo->wake_main_thread);
thread_destroy_event(voodoo->wake_fifo_thread);
thread_destroy_event(voodoo->wake_render_thread[0]);
thread_destroy_event(voodoo->wake_render_thread[1]);
thread_destroy_event(voodoo->render_not_full_event[0]);
thread_destroy_event(voodoo->render_not_full_event[1]);
for (uint8_t c = 0; c < TEX_CACHE_MAX; c++) {
if (voodoo->dual_tmus)
free(voodoo->texture_cache[1][c].data);
free(voodoo->texture_cache[0][c].data);
}
#ifndef NO_CODEGEN
voodoo_codegen_close(voodoo);
#endif
if (voodoo->type < VOODOO_BANSHEE && voodoo->fb_mem) {
free(voodoo->fb_mem);
if (voodoo->dual_tmus)
free(voodoo->tex_mem[1]);
free(voodoo->tex_mem[0]);
}
thread_close_mutex(voodoo->force_blit_mutex);
free(voodoo);
}
void
voodoo_close(void *priv)
{
voodoo_set_t *voodoo_set = (voodoo_set_t *) priv;
if (voodoo_set->nr_cards == 2)
voodoo_card_close(voodoo_set->voodoos[1]);
voodoo_card_close(voodoo_set->voodoos[0]);
free(voodoo_set);
}
static const device_config_t voodoo_config[] = {
// clang-format off
{
.name = "type",
.description = "Voodoo type",
.type = CONFIG_SELECTION,
.selection = {
{
.description = "3Dfx Voodoo Graphics",
.value = VOODOO_1
},
{
.description = "Obsidian SB50 + Amethyst (2 TMUs)",
.value = VOODOO_SB50
},
{
.description = "3Dfx Voodoo 2",
.value = VOODOO_2
},
{
.description = ""
}
},
.default_int = 0
},
{
.name = "framebuffer_memory",
.description = "Framebuffer memory size",
.type = CONFIG_SELECTION,
.selection = {
{
.description = "2 MB",
.value = 2
},
{
.description = "4 MB",
.value = 4
},
{
.description = ""
}
},
.default_int = 2
},
{
.name = "texture_memory",
.description = "Texture memory size",
.type = CONFIG_SELECTION,
.selection = {
{
.description = "2 MB",
.value = 2
},
{
.description = "4 MB",
.value = 4
},
{
.description = ""
}
},
.default_int = 2
},
{
.name = "bilinear",
.description = "Bilinear filtering",
.type = CONFIG_BINARY,
.default_int = 1
},
{
.name = "dithersub",
.description = "Dither subtraction",
.type = CONFIG_BINARY,
.default_int = 1
},
{
.name = "dacfilter",
.description = "Screen Filter",
.type = CONFIG_BINARY,
.default_int = 0
},
{
.name = "render_threads",
.description = "Render threads",
.type = CONFIG_SELECTION,
.selection = {
{
.description = "1",
.value = 1
},
{
.description = "2",
.value = 2
},
{
.description = "4",
.value = 4
},
{
.description = ""
}
},
.default_int = 2
},
{
.name = "sli",
.description = "SLI",
.type = CONFIG_BINARY,
.default_int = 0
},
#ifndef NO_CODEGEN
{
.name = "recompiler",
.description = "Recompiler",
.type = CONFIG_BINARY,
.default_int = 1
},
#endif
{
.type = CONFIG_END
}
// clang-format on
};
const device_t voodoo_device = {
.name = "3Dfx Voodoo Graphics",
.internal_name = "voodoo",
.flags = DEVICE_PCI,
.local = 0,
.init = voodoo_init,
.close = voodoo_close,
.reset = NULL,
{ .available = NULL },
.speed_changed = voodoo_speed_changed,
.force_redraw = voodoo_force_blit,
.config = voodoo_config
};
``` | /content/code_sandbox/src/video/vid_voodoo.c | c | 2016-06-25T22:29:10 | 2024-08-16T19:09:21 | 86Box | 86Box/86Box | 2,616 | 14,607 |
```c
/*
* 86Box A hypervisor and IBM PC system emulator that specializes in
* running old operating systems and software designed for IBM
* PC systems and compatibles from 1981 through fairly recent
* system designs based on the PCI bus.
*
* This file is part of the 86Box distribution.
*
* Chips & Technologies 82C425 display controller emulation,
* with support for 640x200 LCD and SMARTMAP text contrast
* enhancement.
*
* Relevant literature:
*
* [1] Chips and Technologies, Inc., 82C425 CGA LCD/CRT Controller,
* Data Sheet, Revision No. 2.2, September 1991.
* <path_to_url
*
* [2] Pleva et al., COLOR TO MONOCHROME CONVERSION,
* U.S. Patent 4,977,398, Dec. 11, 1990.
* <path_to_url
*
* Based on Toshiba T1000 plasma display emulation code.
*
* Authors: Fred N. van Kempen, <decwiz@yahoo.com>
* Miran Grca, <mgrca8@gmail.com>
* John Elliott, <jce@seasip.info>
* Lubomir Rintel, <lkundrak@v3.sk>
*
*
* This program is free software; you can redistribute it and/or modify
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful, but
* WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
*
* along with this program; if not, write to the:
*
* Free Software Foundation, Inc.
* 59 Temple Place - Suite 330
* Boston, MA 02111-1307
* USA.
*/
#include <stdint.h>
#include <stdio.h>
#include <stdlib.h>
#include <string.h>
#include <wchar.h>
#include <86box/86box.h>
#include <86box/device.h>
#include <86box/io.h>
#include <86box/mem.h>
#include <86box/timer.h>
#include "cpu.h"
#include <86box/video.h>
#include <86box/vid_cga.h>
#include <86box/plat_unused.h>
#define F82C425_XSIZE 640
#define F82C425_YSIZE 200
/* Mapping of attributes to colours */
static uint32_t smartmap[256][2];
static uint32_t colormap[4];
static video_timings_t timing_f82c425 = { .type = VIDEO_ISA, .write_b = 8, .write_w = 16, .write_l = 32, .read_b = 8, .read_w = 16, .read_l = 32 };
static uint8_t st_video_options;
static uint8_t st_enabled = 1;
static int8_t st_display_internal = -1;
void
f82c425_video_options_set(uint8_t options)
{
st_video_options = options;
}
void
f82c425_video_enable(uint8_t enabled)
{
st_enabled = enabled;
}
void
f82c425_display_set(uint8_t internal)
{
st_display_internal = (int8_t) internal;
}
uint8_t
f82c425_display_get(void)
{
return (uint8_t) st_display_internal;
}
typedef struct f82c425_t {
mem_mapping_t mapping;
cga_t cga;
uint8_t crtcreg;
uint64_t dispontime, dispofftime;
int linepos, displine;
int dispon;
uint8_t video_options;
uint8_t *vram;
/* Registers specific to 82C425. */
uint8_t ac_limit;
uint8_t threshold;
uint8_t shift;
uint8_t hsync;
uint8_t vsync_blink;
uint8_t timing;
uint8_t function;
} f82c425_t;
/* Convert IRGB representation to RGBI,
* useful in SMARTMAP calculations. */
static inline uint8_t
f82c425_rgbi(uint8_t irgb)
{
return ((irgb & 0x7) << 1) | (irgb >> 3);
}
/* Convert IRGB SMARTMAP output to a RGB representation of one of 4/8 grey
* shades we'd see on an actual V86P display: with some bias toward lighter
* shades and a backlight with yellow/green-ish tint. */
static inline uint32_t
f82c425_makecol(uint8_t rgbi, int gs4, int inv)
{
uint8_t c;
gs4 = 1 + !!gs4;
if (!inv) {
rgbi = 15 - rgbi;
}
c = 0x10 * gs4 * ((rgbi >> gs4) + 2);
#ifdef NO_BLUE
return makecol(c, c + 0x08, c - 0x20);
#else
return makecol(c, c + 0x08, 0x70);
#endif
}
/* Saturating/non-saturating addition for SMARTMAP(see below). */
static inline int
f82c425_smartmap_add(int a, int b, int sat)
{
int c = a + b;
/* (SATURATING OR NON SATURATING) */
if (sat) {
if (c < 0)
c = 0;
else if (c > 15)
c = 15;
}
return c & 0xf;
}
/* Calculate and cache mapping of CGA text color attribute to a
* shade of gray enhanced via the SMARTMAP algorithm.
*
* This is a straightforward implementation of the algorithm as described
* in U.S. Patent 4,977,398 [2]. The comments in capitals refer to portions
* of a figure on page 4. */
static void
f82c425_smartmap(f82c425_t *f82c425)
{
for (uint16_t i = 0; i < 256; i++) {
uint8_t bg = f82c425_rgbi(i >> 4);
uint8_t fg = f82c425_rgbi(i & 0xf);
/* FIG._4. */
if (abs(bg - fg) <= (f82c425->threshold & 0x0f)) {
/* FOREGROUND=BACKGROUND */
if (bg == fg) {
/* SPECIAL CASE */
if (f82c425->shift == 0xff) {
/* CHECK MOST SIGNIFICANT BIT */
if (fg & 0x8) {
/* FULL WHITE */
fg = bg = 15;
} else {
/* FULL BLACK */
fg = bg = 0;
}
}
} else {
uint8_t sat = f82c425->threshold & 0x10;
/* DETERMINE WHICH IS LIGHT */
if (fg > bg) {
fg = f82c425_smartmap_add(fg, f82c425->shift & 0x0f, sat);
bg = f82c425_smartmap_add(bg, -(f82c425->shift >> 4), sat);
} else {
fg = f82c425_smartmap_add(fg, -(f82c425->shift & 0x0f), sat);
bg = f82c425_smartmap_add(bg, f82c425->shift >> 4, sat);
}
}
}
smartmap[i][0] = f82c425_makecol(bg, f82c425->threshold & 0x20, f82c425->function & 0x80);
smartmap[i][1] = f82c425_makecol(fg, f82c425->threshold & 0x20, f82c425->function & 0x80);
}
}
/* Calculate mapping of 320x200 graphical mode colors. */
static void
f82c425_colormap(f82c425_t *f82c425)
{
for (uint8_t i = 0; i < 4; i++)
colormap[i] = f82c425_makecol(5 * i, 0, f82c425->function & 0x80);
}
static void
f82c425_out(uint16_t addr, uint8_t val, void *priv)
{
f82c425_t *f82c425 = (f82c425_t *) priv;
if (addr == 0x3d4)
f82c425->crtcreg = val;
if (((f82c425->function & 0x01) == 0) && ((f82c425->crtcreg != 0xdf) || (addr != 0x3d5)))
return;
if (addr != 0x3d5 || f82c425->crtcreg <= 31) {
cga_out(addr, val, &f82c425->cga);
return;
}
switch (f82c425->crtcreg) {
case 0xd9:
f82c425->ac_limit = val;
break;
case 0xda:
f82c425->threshold = val;
f82c425_smartmap(f82c425);
break;
case 0xdb:
f82c425->shift = val;
f82c425_smartmap(f82c425);
break;
case 0xdc:
f82c425->hsync = val;
break;
case 0xdd:
f82c425->vsync_blink = val;
break;
case 0xde:
f82c425->timing = val;
break;
case 0xdf:
f82c425->function = val;
f82c425_smartmap(f82c425);
f82c425_colormap(f82c425);
break;
default:
break;
}
}
static uint8_t
f82c425_in(uint16_t addr, void *priv)
{
f82c425_t *f82c425 = (f82c425_t *) priv;
if ((f82c425->function & 0x01) == 0)
return 0xff;
if (addr == 0x3d4)
return f82c425->crtcreg;
if (addr != 0x3d5 || f82c425->crtcreg <= 31)
return cga_in(addr, &f82c425->cga);
switch (f82c425->crtcreg) {
case 0xd9:
return f82c425->ac_limit;
case 0xda:
return f82c425->threshold;
case 0xdb:
return f82c425->shift;
case 0xdc:
return f82c425->hsync;
case 0xdd:
return f82c425->vsync_blink;
case 0xde:
return f82c425->timing;
case 0xdf:
return f82c425->function;
default:
break;
}
return 0xff;
}
static void
f82c425_write(uint32_t addr, uint8_t val, void *priv)
{
f82c425_t *f82c425 = (f82c425_t *) priv;
f82c425->vram[addr & 0x3fff] = val;
cycles -= 4;
}
static uint8_t
f82c425_read(uint32_t addr, void *priv)
{
const f82c425_t *f82c425 = (f82c425_t *) priv;
cycles -= 4;
return f82c425->vram[addr & 0x3fff];
}
static void
f82c425_recalctimings(f82c425_t *f82c425)
{
double disptime;
double _dispontime;
double _dispofftime;
if (f82c425->function & 0x08) {
cga_recalctimings(&f82c425->cga);
return;
}
disptime = 651;
_dispontime = 640;
_dispofftime = disptime - _dispontime;
f82c425->dispontime = (uint64_t) (_dispontime * xt_cpu_multi);
f82c425->dispofftime = (uint64_t) (_dispofftime * xt_cpu_multi);
}
/* Draw a row of text. */
static void
f82c425_text_row(f82c425_t *f82c425)
{
uint32_t colors[2];
int c;
uint8_t chr;
uint8_t attr;
int drawcursor;
int cursorline;
int blink;
uint16_t addr;
uint8_t sc;
uint16_t ma = (f82c425->cga.crtc[0x0d] | (f82c425->cga.crtc[0x0c] << 8)) & 0x3fff;
uint16_t ca = (f82c425->cga.crtc[0x0f] | (f82c425->cga.crtc[0x0e] << 8)) & 0x3fff;
uint8_t sl = f82c425->cga.crtc[9] + 1;
int columns = f82c425->cga.crtc[1];
sc = (f82c425->displine) & 7;
addr = ((ma & ~1) + (f82c425->displine >> 3) * columns) * 2;
ma += (f82c425->displine >> 3) * columns;
if ((f82c425->cga.crtc[0x0a] & 0x60) == 0x20) {
cursorline = 0;
} else {
cursorline = ((f82c425->cga.crtc[0x0a] & 0x0F) <= sc) && ((f82c425->cga.crtc[0x0b] & 0x0F) >= sc);
}
for (int x = 0; x < columns; x++) {
chr = f82c425->vram[(addr + 2 * x) & 0x3FFF];
attr = f82c425->vram[(addr + 2 * x + 1) & 0x3FFF];
drawcursor = ((ma == ca) && cursorline && (f82c425->cga.cgamode & 0x8) && (f82c425->cga.cgablink & 0x10));
blink = ((f82c425->cga.cgablink & 0x10) && (f82c425->cga.cgamode & 0x20) && (attr & 0x80) && !drawcursor);
if (drawcursor) {
colors[0] = smartmap[~attr & 0xff][0];
colors[1] = smartmap[~attr & 0xff][1];
} else {
colors[0] = smartmap[attr][0];
colors[1] = smartmap[attr][1];
}
if (blink)
colors[1] = colors[0];
if (f82c425->cga.cgamode & 0x01) {
/* High resolution (80 cols) */
for (c = 0; c < sl; c++) {
(buffer32->line[f82c425->displine])[(x << 3) + c] = colors[(fontdat[chr][sc] & (1 << (c ^ 7))) ? 1 : 0];
}
} else {
/* Low resolution (40 columns, stretch pixels horizontally) */
for (c = 0; c < sl; c++) {
(buffer32->line[f82c425->displine])[(x << 4) + c * 2] = (buffer32->line[f82c425->displine])[(x << 4) + c * 2 + 1] = colors[(fontdat[chr][sc] & (1 << (c ^ 7))) ? 1 : 0];
}
}
++ma;
}
}
/* Draw a line in CGA 640x200 mode */
static void
f82c425_cgaline6(f82c425_t *f82c425)
{
uint8_t dat;
uint16_t addr;
uint16_t ma = (f82c425->cga.crtc[0x0d] | (f82c425->cga.crtc[0x0c] << 8)) & 0x3fff;
addr = ((f82c425->displine) & 1) * 0x2000 + (f82c425->displine >> 1) * 80 + ((ma & ~1) << 1);
for (uint8_t x = 0; x < 80; x++) {
dat = f82c425->vram[addr & 0x3FFF];
addr++;
for (uint8_t c = 0; c < 8; c++) {
(buffer32->line[f82c425->displine])[x * 8 + c] = colormap[dat & 0x80 ? 3 : 0];
dat = dat << 1;
}
}
}
/* Draw a line in CGA 320x200 mode. */
static void
f82c425_cgaline4(f82c425_t *f82c425)
{
uint8_t dat;
uint8_t pattern;
uint16_t addr;
uint16_t ma = (f82c425->cga.crtc[0x0d] | (f82c425->cga.crtc[0x0c] << 8)) & 0x3fff;
addr = ((f82c425->displine) & 1) * 0x2000 + (f82c425->displine >> 1) * 80 + ((ma & ~1) << 1);
for (uint8_t x = 0; x < 80; x++) {
dat = f82c425->vram[addr & 0x3FFF];
addr++;
for (uint8_t c = 0; c < 4; c++) {
pattern = (dat & 0xC0) >> 6;
if (!(f82c425->cga.cgamode & 0x08))
pattern = 0;
(buffer32->line[f82c425->displine])[x * 8 + 2 * c] = (buffer32->line[f82c425->displine])[x * 8 + 2 * c + 1] = colormap[pattern & 3];
dat = dat << 2;
}
}
}
static void
f82c425_poll(void *priv)
{
f82c425_t *f82c425 = (f82c425_t *) priv;
if (f82c425->video_options != st_video_options || !!(f82c425->function & 1) != st_enabled) {
f82c425->video_options = st_video_options;
f82c425->function &= ~1;
f82c425->function |= st_enabled ? 1 : 0;
if (f82c425->function & 0x01)
mem_mapping_enable(&f82c425->mapping);
else
mem_mapping_disable(&f82c425->mapping);
}
/* Switch between internal LCD and external CRT display. */
if (st_display_internal != -1 && st_display_internal != !!(f82c425->function & 0x08)) {
if (st_display_internal) {
f82c425->function &= ~0x08;
f82c425->timing &= ~0x20;
} else {
f82c425->function |= 0x08;
f82c425->timing |= 0x20;
}
f82c425_recalctimings(f82c425);
}
if (f82c425->function & 0x08) {
cga_poll(&f82c425->cga);
return;
}
if (!f82c425->linepos) {
timer_advance_u64(&f82c425->cga.timer, f82c425->dispofftime);
f82c425->cga.cgastat |= 1;
f82c425->linepos = 1;
if (f82c425->dispon) {
if (f82c425->displine == 0) {
video_wait_for_buffer();
}
switch (f82c425->cga.cgamode & 0x13) {
case 0x12:
f82c425_cgaline6(f82c425);
break;
case 0x02:
f82c425_cgaline4(f82c425);
break;
case 0x00:
case 0x01:
f82c425_text_row(f82c425);
break;
default:
break;
}
}
f82c425->displine++;
/* Hardcode a fixed refresh rate and VSYNC timing */
if (f82c425->displine >= 216) {
/* End of VSYNC */
f82c425->displine = 0;
f82c425->cga.cgastat &= ~8;
f82c425->dispon = 1;
} else if (f82c425->displine == (f82c425->cga.crtc[9] + 1) * f82c425->cga.crtc[6]) {
/* Start of VSYNC */
f82c425->cga.cgastat |= 8;
f82c425->dispon = 0;
}
} else {
if (f82c425->dispon)
f82c425->cga.cgastat &= ~1;
timer_advance_u64(&f82c425->cga.timer, f82c425->dispontime);
f82c425->linepos = 0;
if (f82c425->displine == 200) {
/* Hardcode 640x200 window size */
if ((F82C425_XSIZE != xsize) || (F82C425_YSIZE != ysize) || video_force_resize_get()) {
xsize = F82C425_XSIZE;
ysize = F82C425_YSIZE;
set_screen_size(xsize, ysize);
if (video_force_resize_get())
video_force_resize_set(0);
}
video_blit_memtoscreen(0, 0, xsize, ysize);
frames++;
/* Fixed 640x200 resolution */
video_res_x = F82C425_XSIZE;
video_res_y = F82C425_YSIZE;
switch (f82c425->cga.cgamode & 0x12) {
case 0x12:
video_bpp = 1;
break;
case 0x02:
video_bpp = 2;
break;
default:
video_bpp = 0;
}
f82c425->cga.cgablink++;
}
}
}
static void *
f82c425_init(UNUSED(const device_t *info))
{
f82c425_t *f82c425 = malloc(sizeof(f82c425_t));
memset(f82c425, 0, sizeof(f82c425_t));
cga_init(&f82c425->cga);
video_inform(VIDEO_FLAG_TYPE_CGA, &timing_f82c425);
/* Initialize registers that don't default to zero. */
f82c425->hsync = 0x40;
f82c425->vsync_blink = 0x72;
/* 16k video RAM */
f82c425->vram = malloc(0x4000);
timer_set_callback(&f82c425->cga.timer, f82c425_poll);
timer_set_p(&f82c425->cga.timer, f82c425);
/* Occupy memory between 0xB8000 and 0xBFFFF */
mem_mapping_add(&f82c425->mapping, 0xb8000, 0x8000, f82c425_read, NULL, NULL, f82c425_write, NULL, NULL, NULL, 0, f82c425);
/* Respond to CGA I/O ports */
io_sethandler(0x03d0, 0x000c, f82c425_in, NULL, NULL, f82c425_out, NULL, NULL, f82c425);
/* Initialize color maps for text & graphic modes */
f82c425_smartmap(f82c425);
f82c425_colormap(f82c425);
/* Start off in 80x25 text mode */
f82c425->cga.cgastat = 0xF4;
f82c425->cga.vram = f82c425->vram;
f82c425->video_options = 0x01;
return f82c425;
}
static void
f82c425_close(void *priv)
{
f82c425_t *f82c425 = (f82c425_t *) priv;
free(f82c425->vram);
free(f82c425);
}
static void
f82c425_speed_changed(void *priv)
{
f82c425_t *f82c425 = (f82c425_t *) priv;
f82c425_recalctimings(f82c425);
}
const device_t f82c425_video_device = {
.name = "82C425 CGA LCD/CRT Controller",
.internal_name = "f82c425_video",
.flags = 0,
.local = 0,
.init = f82c425_init,
.close = f82c425_close,
.reset = NULL,
{ .available = NULL },
.speed_changed = f82c425_speed_changed,
.force_redraw = NULL,
.config = NULL
};
``` | /content/code_sandbox/src/video/vid_f82c425.c | c | 2016-06-25T22:29:10 | 2024-08-16T19:09:21 | 86Box | 86Box/86Box | 2,616 | 5,872 |
```c
/*
* 86Box A hypervisor and IBM PC system emulator that specializes in
* running old operating systems and software designed for IBM
* PC systems and compatibles from 1981 through fairly recent
* system designs based on the PCI bus.
*
* This file is part of the 86Box distribution.
*
* DDC monitor emulation.
*
*
*
* Authors: RichardG, <richardg867@gmail.com>
*
*/
#include <stdio.h>
#include <stdint.h>
#include <string.h>
#include <stdlib.h>
#include <stddef.h>
#include <wchar.h>
#include <math.h>
#include <86box/86box.h>
#include <86box/i2c.h>
#define PIXEL_MM(px) (((px) * 25.4) / 96.0)
#define STANDARD_TIMING(slot, width, aspect_ratio, refresh) \
do { \
edid->slot.horiz_pixels = ((width) >> 3) - 31; \
edid->slot.aspect_ratio_refresh_rate = ((aspect_ratio) << 6) | ((refresh) -60); \
} while (0)
#define DETAILED_TIMING(slot, clk, width, height, hblank, vblank, hfp, hsp, vfp, vsp) \
do { \
edid->slot.pixel_clock_lsb = ((clk) / 10) & 0xff; \
edid->slot.pixel_clock_msb = ((clk) / 10) >> 8; \
edid->slot.h_active_lsb = (width) &0xff; \
edid->slot.h_blank_lsb = (hblank) &0xff; \
edid->slot.h_active_blank_msb = (((width) >> 4) & 0xf0) | (((hblank) >> 8) & 0x0f); \
edid->slot.v_active_lsb = (height) &0xff; \
edid->slot.v_blank_lsb = (vblank) &0xff; \
edid->slot.v_active_blank_msb = (((height) >> 4) & 0xf0) | (((vblank) >> 8) & 0x0f); \
edid->slot.h_front_porch_lsb = (hfp) &0xff; \
edid->slot.h_sync_pulse_lsb = (hsp) &0xff; \
edid->slot.v_front_porch_sync_pulse_lsb = (((vfp) &0x0f) << 4) | ((vsp) &0x0f); \
edid->slot.hv_front_porch_sync_pulse_msb = (((hfp) >> 2) & 0xc0) | (((hsp) >> 4) & 0x30) | (((vfp) >> 2) & 0x0c) | (((vsp) >> 4) & 0x03); \
edid->slot.h_size_lsb = (uint8_t) horiz_mm; \
edid->slot.v_size_lsb = (uint8_t) vert_mm; \
edid->slot.hv_size_msb = ((((uint16_t) horiz_mm) >> 4) & 0xf0) | ((((uint16_t) vert_mm) >> 8) & 0x0f); \
} while (0)
enum {
STD_ASPECT_16_10 = 0x0,
STD_ASPECT_4_3,
STD_ASPECT_5_4,
STD_ASPECT_16_9
};
typedef struct {
uint8_t horiz_pixels, aspect_ratio_refresh_rate;
} edid_standard_timing_t;
typedef struct {
uint8_t pixel_clock_lsb, pixel_clock_msb, h_active_lsb, h_blank_lsb,
h_active_blank_msb, v_active_lsb, v_blank_lsb, v_active_blank_msb,
h_front_porch_lsb, h_sync_pulse_lsb, v_front_porch_sync_pulse_lsb,
hv_front_porch_sync_pulse_msb, h_size_lsb, v_size_lsb, hv_size_msb,
h_border, v_border, features;
} edid_detailed_timing_t;
typedef struct {
uint8_t magic[2], reserved, tag, range_limit_offsets;
union {
char ascii[13];
struct {
uint8_t min_v_field, max_v_field, min_h_line, max_h_line, max_pixel_clock,
timing_type;
union {
uint8_t padding[7];
struct {
uint8_t reserved, gtf_start_freq, gtf_c, gtf_m_lsb, gtf_m_msb,
gtf_k, gtf_j;
};
struct {
uint8_t cvt_version, add_clock_precision, max_active_pixels,
aspect_ratios, aspect_ratio_pref, scaling_support,
refresh_pref;
};
};
} range_limits;
struct {
edid_standard_timing_t timings[6];
uint8_t padding;
} ext_standard_timings;
struct {
uint8_t version;
struct {
uint8_t lines_lsb, lines_msb_aspect_ratio, refresh_rate;
} timings[4];
} cvt_timings;
struct {
uint8_t version, timings[6], reserved[6];
} established_timings3;
};
} edid_descriptor_t;
typedef struct {
uint8_t magic[8], mfg[2], mfg_product[2], serial[4], mfg_week, mfg_year,
edid_version, edid_rev;
uint8_t input_params, horiz_size, vert_size, gamma, features;
uint8_t red_green_lsb, blue_white_lsb, red_x_msb, red_y_msb, green_x_msb,
green_y_msb, blue_x_msb, blue_y_msb, white_x_msb, white_y_msb;
uint8_t established_timings[3];
edid_standard_timing_t standard_timings[8];
union {
edid_detailed_timing_t detailed_timings[4];
edid_descriptor_t descriptors[4];
};
uint8_t extensions, checksum;
uint8_t ext_tag, ext_rev, ext_dtd_offset, ext_native_dtds;
union {
edid_detailed_timing_t ext_detailed_timings[6];
edid_descriptor_t ext_descriptors[6];
};
uint8_t padding[15], checksum2;
} edid_t;
void *
ddc_init(void *i2c)
{
edid_t *edid = malloc(sizeof(edid_t));
memset(edid, 0, sizeof(edid_t));
uint8_t *edid_bytes = (uint8_t *) edid;
double horiz_mm = PIXEL_MM(800);
double vert_mm = PIXEL_MM(600);
memset(&edid->magic[1], 0xff, sizeof(edid->magic) - 2);
edid->mfg[0] = 0x09; /* manufacturer "BOX" (currently unassigned by UEFI) */
edid->mfg[1] = 0xf8;
edid->mfg_week = 48;
edid->mfg_year = 2020 - 1990;
edid->edid_version = 0x01;
edid->edid_rev = 0x04; /* EDID 1.4, required for Xorg on newer Linux to use the preferred mode timing instead of maxing out */
edid->input_params = 0x0e; /* analog input; separate sync; composite sync; sync on green */
edid->horiz_size = round(horiz_mm / 10.0);
edid->vert_size = round(vert_mm / 10.0);
edid->features = 0xeb; /* DPMS standby/suspend/active-off; RGB color; first timing is preferred; GTF/CVT */
edid->red_green_lsb = 0x81;
edid->blue_white_lsb = 0xf1;
edid->red_x_msb = 0xa3;
edid->red_y_msb = 0x57;
edid->green_x_msb = 0x53;
edid->green_y_msb = 0x9f;
edid->blue_x_msb = 0x27;
edid->blue_y_msb = 0x0a;
edid->white_x_msb = 0x50;
edid->white_y_msb = 0x00;
memset(&edid->established_timings, 0xff, sizeof(edid->established_timings)); /* all enabled */
/* 60 Hz timings */
STANDARD_TIMING(standard_timings[0], 1280, STD_ASPECT_16_9, 60); /* 1280x720 */
STANDARD_TIMING(standard_timings[1], 1280, STD_ASPECT_16_10, 60); /* 1280x800 */
STANDARD_TIMING(standard_timings[2], 1366, STD_ASPECT_16_9, 60); /* 1360x768 (closest to 1366x768) */
STANDARD_TIMING(standard_timings[3], 1440, STD_ASPECT_16_10, 60); /* 1440x900 */
STANDARD_TIMING(standard_timings[4], 1600, STD_ASPECT_16_9, 60); /* 1600x900 */
STANDARD_TIMING(standard_timings[5], 1600, STD_ASPECT_4_3, 60); /* 1600x1200 */
STANDARD_TIMING(standard_timings[6], 1920, STD_ASPECT_16_9, 60); /* 1920x1080 */
STANDARD_TIMING(standard_timings[7], 2048, STD_ASPECT_4_3, 60); /* 2048x1536 */
/* Detailed timing for the preferred mode of 800x600 @ 60 Hz */
DETAILED_TIMING(detailed_timings[0], 40000, 800, 600, 256, 28, 40, 128, 1, 4);
edid->descriptors[1].tag = 0xf7; /* established timings 3 */
edid->descriptors[1].established_timings3.version = 0x0a;
memset(&edid->descriptors[1].established_timings3.timings, 0xff, sizeof(edid->descriptors[1].established_timings3.timings)); /* all enabled */
edid->descriptors[1].established_timings3.timings[5] &= 0xf0; /* reserved bits */
edid->descriptors[2].tag = 0xfd; /* range limits */
edid->descriptors[2].range_limits.min_v_field = 45;
edid->descriptors[2].range_limits.max_v_field = 125;
edid->descriptors[2].range_limits.min_h_line = 30; /* 640x480 = ~31.5 KHz */
edid->descriptors[2].range_limits.max_h_line = 115; /* 1920x1440 = 112.5 KHz */
edid->descriptors[2].range_limits.max_pixel_clock = 30; /* 1920x1440 = 297 MHz */
edid->descriptors[2].range_limits.timing_type = 0x00; /* default GTF */
edid->descriptors[2].range_limits.padding[0] = 0x0a;
memset(&edid->descriptors[2].range_limits.padding[1], 0x20, sizeof(edid->descriptors[2].range_limits.padding) - 1);
edid->descriptors[3].tag = 0xfc; /* display name */
memcpy(&edid->descriptors[3].ascii, "86Box Monitor", 13); /* exactly 13 characters (would otherwise require LF termination and space padding) */
edid->extensions = 1;
for (uint8_t c = 0; c < 127; c++)
edid->checksum += edid_bytes[c];
edid->checksum = 256 - edid->checksum;
edid->ext_tag = 0x02;
edid->ext_rev = 0x03;
edid->ext_native_dtds = 0x80; /* underscans IT; no native extended modes */
edid->ext_dtd_offset = 0x04;
/* Detailed timing for 1366x768 */
DETAILED_TIMING(ext_detailed_timings[0], 85500, 1366, 768, 426, 30, 70, 143, 3, 3);
/* High refresh rate timings (within the standard 85 Hz VGA limit) */
edid->ext_descriptors[1].tag = 0xfa; /* standard timing identifiers */
#define ext_standard_timings0 ext_descriptors[1].ext_standard_timings.timings
STANDARD_TIMING(ext_standard_timings0[0], 640, STD_ASPECT_4_3, 85); /* 640x480 @ 85 Hz */
STANDARD_TIMING(ext_standard_timings0[1], 800, STD_ASPECT_4_3, 85); /* 800x600 @ 85 Hz */
STANDARD_TIMING(ext_standard_timings0[2], 1024, STD_ASPECT_4_3, 85); /* 1024x768 @ 85 Hz */
STANDARD_TIMING(ext_standard_timings0[3], 1280, STD_ASPECT_5_4, 85); /* 1280x1024 @ 85 Hz */
STANDARD_TIMING(ext_standard_timings0[4], 1600, STD_ASPECT_4_3, 85); /* 1600x1200 @ 85 Hz */
STANDARD_TIMING(ext_standard_timings0[5], 1680, STD_ASPECT_16_10, 60); /* 1680x1050 @ 60 Hz (previously in standard timings) */
edid->ext_descriptors[1].ext_standard_timings.padding = 0x0a;
for (uint8_t c = 128; c < 255; c++)
edid->checksum2 += edid_bytes[c];
edid->checksum2 = 256 - edid->checksum2;
return i2c_eeprom_init(i2c, 0x50, edid_bytes, sizeof(edid_t), 0);
}
void
ddc_close(void *eeprom)
{
i2c_eeprom_close(eeprom);
}
``` | /content/code_sandbox/src/video/vid_ddc.c | c | 2016-06-25T22:29:10 | 2024-08-16T19:09:21 | 86Box | 86Box/86Box | 2,616 | 3,317 |
```c
/*
* 86Box A hypervisor and IBM PC system emulator that specializes in
* running old operating systems and software designed for IBM
* PC systems and compatibles from 1981 through fairly recent
* system designs based on the PCI bus.
*
* This file is part of the 86Box distribution.
*
* Emulation of the Olivetti OGC 8-bit ISA (GO708) and
* M21/M24/M28 16-bit bus (GO317/318/380/709) video cards.
*
*
*
* Authors: Sarah Walker, <path_to_url
* Miran Grca, <mgrca8@gmail.com>
* Fred N. van Kempen, <decwiz@yahoo.com>
* EngiNerd, <webmaster.crrc@yahoo.it>
*
*/
#include <stdio.h>
#include <stdint.h>
#include <string.h>
#include <stdlib.h>
#include <stdarg.h>
#include <wchar.h>
#include <86box/io.h>
#include <86box/video.h>
#include <86box/86box.h>
#include <86box/timer.h>
#include <86box/mem.h>
#include <86box/pit.h>
#include <86box/rom.h>
#include <86box/device.h>
#include <86box/vid_cga.h>
#include <86box/vid_ogc.h>
#include <86box/vid_cga_comp.h>
#include <86box/plat_unused.h>
/*
* Current bugs:
* - Olivetti diagnostics fail with errors: 6845 crtc write / read error out 0000 in 00ff
* - Dark blue (almost black) picture in composite mode
*/
#define CGA_RGB 0
#define CGA_COMPOSITE 1
#define COMPOSITE_OLD 0
#define COMPOSITE_NEW 1
static video_timings_t timing_ogc = { .type = VIDEO_ISA, .write_b = 8, .write_w = 16, .write_l = 32, .read_b = 8, .read_w = 16, .read_l = 32 };
static uint8_t mdaattr[256][2][2];
void
ogc_recalctimings(ogc_t *ogc)
{
double _dispontime;
double _dispofftime;
double disptime;
if (ogc->cga.cgamode & 1) {
disptime = ogc->cga.crtc[0] + 1;
_dispontime = ogc->cga.crtc[1];
} else {
disptime = (ogc->cga.crtc[0] + 1) << 1;
_dispontime = ogc->cga.crtc[1] << 1;
}
_dispofftime = disptime - _dispontime;
_dispontime *= CGACONST / 2;
_dispofftime *= CGACONST / 2;
ogc->cga.dispontime = (uint64_t) (_dispontime);
ogc->cga.dispofftime = (uint64_t) (_dispofftime);
}
void
ogc_out(uint16_t addr, uint8_t val, void *priv)
{
ogc_t *ogc = (ogc_t *) priv;
#if 0
if (addr >= 0x3c0 && addr <= 0x3cf)
addr = addr + 16;
#endif
switch (addr) {
case 0x3d4:
case 0x3d5:
case 0x3d8:
case 0x3d9:
cga_out(addr, val, &ogc->cga);
break;
case 0x3de:
/* set control register */
ogc->ctrl_3de = val;
/* select 1st or 2nd 16k vram block to be used */
ogc->base = (val & 0x08) ? 0x4000 : 0;
break;
default:
break;
}
}
uint8_t
ogc_in(uint16_t addr, void *priv)
{
ogc_t *ogc = (ogc_t *) priv;
#if 0
if (addr >= 0x3c0 && addr <= 0x3cf)
addr = addr + 16;
#endif
uint8_t ret = 0xff;
switch (addr) {
case 0x3d4:
case 0x3d5:
case 0x3da:
/*
* bits 6-7: 3 = no DEB expansion board installed
* bits 4-5: 2 color, 3 mono
* bit 3: high during 1st half of vertical retrace in character mode (CCA standard)
* bit 2: lightpen switch (CGA standard)
* bit 1: lightpen strobe (CGA standard)
* bit 0: high during retrace (CGA standard)
*/
ret = cga_in(addr, &ogc->cga);
if (addr == 0x3da) {
ret = ret | 0xe0;
if (ogc->mono_display)
ret = ret | 0x10;
}
break;
default:
break;
}
return ret;
}
void
ogc_waitstates(UNUSED(void *priv))
{
int ws_array[16] = { 3, 4, 5, 6, 7, 8, 4, 5, 6, 7, 8, 4, 5, 6, 7, 8 };
int ws;
ws = ws_array[cycles & 0xf];
sub_cycles(ws);
}
void
ogc_write(uint32_t addr, uint8_t val, void *priv)
{
ogc_t *ogc = (ogc_t *) priv;
int offset;
ogc->cga.vram[addr & 0x7FFF] = val;
if (ogc->cga.snow_enabled) {
/* recreate snow effect */
offset = ((timer_get_remaining_u64(&ogc->cga.timer) / CGACONST) * 4) & 0xfc;
ogc->cga.charbuffer[offset] = ogc->cga.vram[addr & 0x7fff];
ogc->cga.charbuffer[offset | 1] = ogc->cga.vram[addr & 0x7fff];
}
ogc_waitstates(&ogc->cga);
}
uint8_t
ogc_read(uint32_t addr, void *priv)
{
ogc_t *ogc = (ogc_t *) priv;
int offset;
ogc_waitstates(&ogc->cga);
if (ogc->cga.snow_enabled) {
/* recreate snow effect */
offset = ((timer_get_remaining_u64(&ogc->cga.timer) / CGACONST) * 4) & 0xfc;
ogc->cga.charbuffer[offset] = ogc->cga.vram[addr & 0x7fff];
ogc->cga.charbuffer[offset | 1] = ogc->cga.vram[addr & 0x7fff];
}
return (ogc->cga.vram[addr & 0x7FFF]);
}
void
ogc_poll(void *priv)
{
ogc_t *ogc = (ogc_t *) priv;
uint16_t ca = (ogc->cga.crtc[15] | (ogc->cga.crtc[14] << 8)) & 0x3fff;
int drawcursor;
int x;
int c;
int xs_temp;
int ys_temp;
int oldvc;
uint8_t chr;
uint8_t attr;
uint16_t dat;
uint16_t dat2;
int cols[4];
int oldsc;
int blink = 0;
int underline = 0;
// composito colore appare blu scuro
/* graphic mode and not mode 40h */
if (!(ogc->ctrl_3de & 0x1 || !(ogc->cga.cgamode & 2))) {
/* standard cga mode */
cga_poll(&ogc->cga);
return;
} else {
/* mode 40h or text mode */
if (!ogc->cga.linepos) {
timer_advance_u64(&ogc->cga.timer, ogc->cga.dispofftime);
ogc->cga.cgastat |= 1;
ogc->cga.linepos = 1;
oldsc = ogc->cga.sc;
if ((ogc->cga.crtc[8] & 3) == 3)
ogc->cga.sc = ((ogc->cga.sc << 1) + ogc->cga.oddeven) & 7;
if (ogc->cga.cgadispon) {
if (ogc->cga.displine < ogc->cga.firstline) {
ogc->cga.firstline = ogc->cga.displine;
video_wait_for_buffer();
}
ogc->cga.lastline = ogc->cga.displine;
/* 80-col */
if (ogc->cga.cgamode & 1) {
/* for each text column */
for (x = 0; x < ogc->cga.crtc[1]; x++) {
/* video output enabled */
if (ogc->cga.cgamode & 8) {
/* character */
chr = ogc->cga.charbuffer[x << 1];
/* text attributes */
attr = ogc->cga.charbuffer[(x << 1) + 1];
} else
chr = attr = 0;
/* check if cursor has to be drawn */
drawcursor = ((ogc->cga.ma == ca) && ogc->cga.con && ogc->cga.cursoron);
/* check if character underline mode should be set */
underline = ((ogc->ctrl_3de & 0x40) && (attr & 0x1) && !(attr & 0x6));
if (underline) {
/* set forecolor to white */
attr = attr | 0x7;
}
blink = 0;
/* set foreground */
cols[1] = (attr & 15) + 16;
/* blink active */
if (ogc->cga.cgamode & 0x20) {
cols[0] = ((attr >> 4) & 7) + 16;
/* attribute 7 active and not cursor */
if ((ogc->cga.cgablink & 8) && (attr & 0x80) && !ogc->cga.drawcursor) {
/* set blinking */
cols[1] = cols[0];
blink = 1;
}
} else {
/* Set intensity bit */
cols[0] = (attr >> 4) + 16;
blink = (attr & 0x80) * 8 + 7 + 16;
}
/* character underline active and 7th row of pixels in character height being drawn */
if (underline && (ogc->cga.sc == 7)) {
/* for each pixel in character width */
for (c = 0; c < 8; c++)
buffer32->line[ogc->cga.displine][(x << 3) + c + 8] = mdaattr[attr][blink][1];
} else if (drawcursor) {
for (c = 0; c < 8; c++)
buffer32->line[ogc->cga.displine][(x << 3) + c + 8] = cols[(fontdatm[chr][((ogc->cga.sc & 7) << 1) | ogc->lineff] & (1 << (c ^ 7))) ? 1 : 0] ^ 15;
} else {
for (c = 0; c < 8; c++)
buffer32->line[ogc->cga.displine][(x << 3) + c + 8] = cols[(fontdatm[chr][((ogc->cga.sc & 7) << 1) | ogc->lineff] & (1 << (c ^ 7))) ? 1 : 0];
}
ogc->cga.ma++;
}
}
/* 40-col */
else if (!(ogc->cga.cgamode & 2)) {
for (x = 0; x < ogc->cga.crtc[1]; x++) {
if (ogc->cga.cgamode & 8) {
chr = ogc->cga.vram[((ogc->cga.ma << 1) & 0x3fff) + ogc->base];
attr = ogc->cga.vram[(((ogc->cga.ma << 1) + 1) & 0x3fff) + ogc->base];
} else {
chr = attr = 0;
}
drawcursor = ((ogc->cga.ma == ca) && ogc->cga.con && ogc->cga.cursoron);
/* check if character underline mode should be set */
underline = ((ogc->ctrl_3de & 0x40) && (attr & 0x1) && !(attr & 0x6));
if (underline) {
/* set forecolor to white */
attr = attr | 0x7;
}
blink = 0;
/* set foreground */
cols[1] = (attr & 15) + 16;
/* blink active */
if (ogc->cga.cgamode & 0x20) {
cols[0] = ((attr >> 4) & 7) + 16;
if ((ogc->cga.cgablink & 8) && (attr & 0x80) && !ogc->cga.drawcursor) {
/* set blinking */
cols[1] = cols[0];
blink = 1;
}
} else {
/* Set intensity bit */
cols[0] = (attr >> 4) + 16;
blink = (attr & 0x80) * 8 + 7 + 16;
}
/* character underline active and 7th row of pixels in character height being drawn */
if (underline && (ogc->cga.sc == 7)) {
/* for each pixel in character width */
for (c = 0; c < 8; c++)
buffer32->line[ogc->cga.displine][(x << 4) + (c << 1) + 8] = buffer32->line[ogc->cga.displine][(x << 4) + (c << 1) + 1 + 8] = mdaattr[attr][blink][1];
} else if (drawcursor) {
for (c = 0; c < 8; c++)
buffer32->line[ogc->cga.displine][(x << 4) + (c << 1) + 8] = buffer32->line[ogc->cga.displine][(x << 4) + (c << 1) + 1 + 8] = cols[(fontdatm[chr][((ogc->cga.sc & 7) << 1) | ogc->lineff] & (1 << (c ^ 7))) ? 1 : 0] ^ 15;
} else {
for (c = 0; c < 8; c++)
buffer32->line[ogc->cga.displine][(x << 4) + (c << 1) + 8] = buffer32->line[ogc->cga.displine][(x << 4) + (c << 1) + 1 + 8] = cols[(fontdatm[chr][((ogc->cga.sc & 7) << 1) | ogc->lineff] & (1 << (c ^ 7))) ? 1 : 0];
}
ogc->cga.ma++;
}
} else {
/* 640x400 mode */
if (ogc->ctrl_3de & 1) {
dat2 = ((ogc->cga.sc & 1) * 0x4000) | (ogc->lineff * 0x2000);
cols[0] = 0;
cols[1] = 15 + 16;
} else {
dat2 = (ogc->cga.sc & 1) * 0x2000;
cols[0] = 0;
cols[1] = (ogc->cga.cgacol & 15) + 16;
}
for (x = 0; x < ogc->cga.crtc[1]; x++) {
/* video out */
if (ogc->cga.cgamode & 8) {
dat = (ogc->cga.vram[((ogc->cga.ma << 1) & 0x1fff) + dat2] << 8) | ogc->cga.vram[((ogc->cga.ma << 1) & 0x1fff) + dat2 + 1];
} else {
dat = 0;
}
ogc->cga.ma++;
for (c = 0; c < 16; c++) {
buffer32->line[ogc->cga.displine][(x << 4) + c + 8] = cols[dat >> 15];
dat <<= 1;
}
}
}
} else {
/* ogc specific */
cols[0] = ((ogc->cga.cgamode & 0x12) == 0x12) ? 0 : (ogc->cga.cgacol & 15) + 16;
if (ogc->cga.cgamode & 1)
hline(buffer32, 0, ogc->cga.displine, ((ogc->cga.crtc[1] << 3) + 16) << 2, cols[0]);
else
hline(buffer32, 0, ogc->cga.displine, ((ogc->cga.crtc[1] << 4) + 16) << 2, cols[0]);
}
/* 80 columns */
if (ogc->cga.cgamode & 1)
x = (ogc->cga.crtc[1] << 3) + 16;
else
x = (ogc->cga.crtc[1] << 4) + 16;
video_process_8(x, ogc->cga.displine);
ogc->cga.sc = oldsc;
if (ogc->cga.vc == ogc->cga.crtc[7] && !ogc->cga.sc)
ogc->cga.cgastat |= 8;
ogc->cga.displine++;
if (ogc->cga.displine >= 720)
ogc->cga.displine = 0;
} else {
timer_advance_u64(&ogc->cga.timer, ogc->cga.dispontime);
if (ogc->cga.cgadispon)
ogc->cga.cgastat &= ~1;
ogc->cga.linepos = 0;
/* ogc specific */
ogc->lineff ^= 1;
if (ogc->lineff) {
ogc->cga.ma = ogc->cga.maback;
} else {
if (ogc->cga.vsynctime) {
ogc->cga.vsynctime--;
if (!ogc->cga.vsynctime)
ogc->cga.cgastat &= ~8;
}
if (ogc->cga.sc == (ogc->cga.crtc[11] & 31) || ((ogc->cga.crtc[8] & 3) == 3 && ogc->cga.sc == ((ogc->cga.crtc[11] & 31) >> 1))) {
ogc->cga.con = 0;
ogc->cga.coff = 1;
}
if ((ogc->cga.crtc[8] & 3) == 3 && ogc->cga.sc == (ogc->cga.crtc[9] >> 1))
ogc->cga.maback = ogc->cga.ma;
if (ogc->cga.vadj) {
ogc->cga.sc++;
ogc->cga.sc &= 31;
ogc->cga.ma = ogc->cga.maback;
ogc->cga.vadj--;
if (!ogc->cga.vadj) {
ogc->cga.cgadispon = 1;
ogc->cga.ma = ogc->cga.maback = (ogc->cga.crtc[13] | (ogc->cga.crtc[12] << 8)) & 0x3fff;
ogc->cga.sc = 0;
}
// potrebbe dare problemi con composito
} else if (ogc->cga.sc == ogc->cga.crtc[9] || ((ogc->cga.crtc[8] & 3) == 3 && ogc->cga.sc == (ogc->cga.crtc[9] >> 1))) {
ogc->cga.maback = ogc->cga.ma;
ogc->cga.sc = 0;
oldvc = ogc->cga.vc;
ogc->cga.vc++;
ogc->cga.vc &= 127;
if (ogc->cga.vc == ogc->cga.crtc[6])
ogc->cga.cgadispon = 0;
if (oldvc == ogc->cga.crtc[4]) {
ogc->cga.vc = 0;
ogc->cga.vadj = ogc->cga.crtc[5];
if (!ogc->cga.vadj) {
ogc->cga.cgadispon = 1;
ogc->cga.ma = ogc->cga.maback = (ogc->cga.crtc[13] | (ogc->cga.crtc[12] << 8)) & 0x3fff;
}
switch (ogc->cga.crtc[10] & 0x60) {
case 0x20:
ogc->cga.cursoron = 0;
break;
case 0x60:
ogc->cga.cursoron = ogc->cga.cgablink & 0x10;
break;
default:
ogc->cga.cursoron = ogc->cga.cgablink & 0x08;
break;
}
}
if (ogc->cga.vc == ogc->cga.crtc[7]) {
ogc->cga.cgadispon = 0;
ogc->cga.displine = 0;
/* ogc specific */
ogc->cga.vsynctime = (ogc->cga.crtc[3] >> 4) + 1;
if (ogc->cga.crtc[7]) {
if (ogc->cga.cgamode & 1)
x = (ogc->cga.crtc[1] << 3) + 16;
else
x = (ogc->cga.crtc[1] << 4) + 16;
ogc->cga.lastline++;
xs_temp = x;
ys_temp = (ogc->cga.lastline - ogc->cga.firstline);
if ((xs_temp > 0) && (ys_temp > 0)) {
if (xsize < 64)
xs_temp = 656;
/* ogc specific */
if (ysize < 32)
ys_temp = 200;
if (!enable_overscan)
xs_temp -= 16;
if ((ogc->cga.cgamode & 8) && ((xs_temp != xsize) || (ys_temp != ysize) || video_force_resize_get())) {
xsize = xs_temp;
ysize = ys_temp;
set_screen_size(xsize, ysize + (enable_overscan ? 16 : 0));
if (video_force_resize_get())
video_force_resize_set(0);
}
/* ogc specific */
if (enable_overscan) {
video_blit_memtoscreen(0, (ogc->cga.firstline - 8),
xsize, (ogc->cga.lastline - ogc->cga.firstline) + 16);
} else {
video_blit_memtoscreen(8, ogc->cga.firstline,
xsize, (ogc->cga.lastline - ogc->cga.firstline));
}
}
frames++;
video_res_x = xsize;
video_res_y = ysize;
/* 80-col */
if (ogc->cga.cgamode & 1) {
video_res_x /= 8;
video_res_y /= (ogc->cga.crtc[9] + 1) * 2;
video_bpp = 0;
/* 40-col */
} else if (!(ogc->cga.cgamode & 2)) {
video_res_x /= 16;
video_res_y /= (ogc->cga.crtc[9] + 1) * 2;
video_bpp = 0;
} else if (!(ogc->ctrl_3de & 1)) {
video_res_y /= 2;
video_bpp = 1;
}
}
ogc->cga.firstline = 1000;
ogc->cga.lastline = 0;
ogc->cga.cgablink++;
ogc->cga.oddeven ^= 1;
}
} else {
ogc->cga.sc++;
ogc->cga.sc &= 31;
ogc->cga.ma = ogc->cga.maback;
}
if (ogc->cga.cgadispon)
ogc->cga.cgastat &= ~1;
if (ogc->cga.sc == (ogc->cga.crtc[10] & 31) || ((ogc->cga.crtc[8] & 3) == 3 && ogc->cga.sc == ((ogc->cga.crtc[10] & 31) >> 1)))
ogc->cga.con = 1;
}
/* 80-columns */
if (ogc->cga.cgadispon && (ogc->cga.cgamode & 1)) {
for (x = 0; x < (ogc->cga.crtc[1] << 1); x++)
ogc->cga.charbuffer[x] = ogc->cga.vram[(((ogc->cga.ma << 1) + x) & 0x3fff) + ogc->base];
}
}
}
}
void
ogc_close(void *priv)
{
ogc_t *ogc = (ogc_t *) priv;
free(ogc->cga.vram);
free(ogc);
}
void
ogc_speed_changed(void *priv)
{
ogc_t *ogc = (ogc_t *) priv;
ogc_recalctimings(ogc);
}
void
ogc_mdaattr_rebuild(void)
{
for (uint16_t c = 0; c < 256; c++) {
mdaattr[c][0][0] = mdaattr[c][1][0] = mdaattr[c][1][1] = 16;
if (c & 8)
mdaattr[c][0][1] = 15 + 16;
else
mdaattr[c][0][1] = 7 + 16;
}
mdaattr[0x70][0][1] = 16;
mdaattr[0x70][0][0] = mdaattr[0x70][1][0] = mdaattr[0x70][1][1] = 16 + 15;
mdaattr[0xF0][0][1] = 16;
mdaattr[0xF0][0][0] = mdaattr[0xF0][1][0] = mdaattr[0xF0][1][1] = 16 + 15;
mdaattr[0x78][0][1] = 16 + 7;
mdaattr[0x78][0][0] = mdaattr[0x78][1][0] = mdaattr[0x78][1][1] = 16 + 15;
mdaattr[0xF8][0][1] = 16 + 7;
mdaattr[0xF8][0][0] = mdaattr[0xF8][1][0] = mdaattr[0xF8][1][1] = 16 + 15;
mdaattr[0x00][0][1] = mdaattr[0x00][1][1] = 16;
mdaattr[0x08][0][1] = mdaattr[0x08][1][1] = 16;
mdaattr[0x80][0][1] = mdaattr[0x80][1][1] = 16;
mdaattr[0x88][0][1] = mdaattr[0x88][1][1] = 16;
}
/*
* Missing features
* - Composite video mode not working
* - Optional EGC expansion board (which handles 640x400x16) not implemented
*/
void *
ogc_init(UNUSED(const device_t *info))
{
#if 0
int display_type;
#endif
ogc_t *ogc = (ogc_t *) malloc(sizeof(ogc_t));
memset(ogc, 0x00, sizeof(ogc_t));
video_inform(VIDEO_FLAG_TYPE_CGA, &timing_ogc);
loadfont("roms/video/ogc/ogc graphics board go380 258 pqbq.bin", 1);
/* FIXME: composite is not working yet */
#if 0
display_type = device_get_config_int("display_type");
#endif
ogc->cga.composite = 0; // (display_type != CGA_RGB);
ogc->cga.revision = device_get_config_int("composite_type");
ogc->cga.snow_enabled = device_get_config_int("snow_enabled");
ogc->cga.vram = malloc(0x8000);
cga_comp_init(ogc->cga.revision);
timer_add(&ogc->cga.timer, ogc_poll, ogc, 1);
mem_mapping_add(&ogc->cga.mapping, 0xb8000, 0x08000,
ogc_read, NULL, NULL,
ogc_write, NULL, NULL, NULL, 0, ogc);
io_sethandler(0x03d0, 16, ogc_in, NULL, NULL, ogc_out, NULL, NULL, ogc);
overscan_x = overscan_y = 16;
ogc->cga.rgb_type = device_get_config_int("rgb_type");
cga_palette = (ogc->cga.rgb_type << 1);
cgapal_rebuild();
ogc_mdaattr_rebuild();
/* color display */
if (device_get_config_int("rgb_type") == 0 || device_get_config_int("rgb_type") == 4)
ogc->mono_display = 0;
else
ogc->mono_display = 1;
return ogc;
}
const device_config_t ogc_m24_config[] = {
// clang-format off
{
/* Olivetti / ATT compatible displays */
.name = "rgb_type",
.description = "RGB type",
.type = CONFIG_SELECTION,
.default_int = CGA_RGB,
.selection = {
{
.description = "Color",
.value = 0
},
{
.description = "Green Monochrome",
.value = 1
},
{
.description = "Amber Monochrome",
.value = 2
},
{
.description = "Gray Monochrome",
.value = 3
},
{
.description = ""
}
}
},
{
.name = "snow_enabled",
.description = "Snow emulation",
.type = CONFIG_BINARY,
.default_int = 1,
},
{
.type = CONFIG_END
}
// clang-format on
};
const device_t ogc_m24_device = {
.name = "Olivetti M21/M24/M28 (GO317/318/380/709) video card",
.internal_name = "ogc_m24",
.flags = DEVICE_ISA,
.local = 0,
.init = ogc_init,
.close = ogc_close,
.reset = NULL,
{ .available = NULL },
.speed_changed = ogc_speed_changed,
.force_redraw = NULL,
.config = ogc_m24_config
};
const device_t ogc_device = {
.name = "Olivetti OGC (GO708)",
.internal_name = "ogc",
.flags = DEVICE_ISA,
.local = 0,
.init = ogc_init,
.close = ogc_close,
.reset = NULL,
{ .available = NULL },
.speed_changed = ogc_speed_changed,
.force_redraw = NULL,
.config = cga_config
};
``` | /content/code_sandbox/src/video/vid_ogc.c | c | 2016-06-25T22:29:10 | 2024-08-16T19:09:21 | 86Box | 86Box/86Box | 2,616 | 7,699 |
```objective-c
/*
*
* Redistribution and use in source and binary forms, with or without modifica-
* tion, are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MER-
* CHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO
* EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPE-
* CIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTH-
* ERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED
* OF THE POSSIBILITY OF SUCH DAMAGE.
*
* Alternatively, the contents of this file may be used under the terms of
* in which case the provisions of the GPL are applicable instead of
* the above. If you wish to allow the use of your version of this file
* only under the terms of the GPL and not to allow others to use your
* version of this file under the BSD license, indicate your decision
* by deleting the provisions above and replace them with the notice
* and other provisions required by the GPL. If you do not delete the
* provisions above, a recipient may use your version of this file under
* either the BSD or the GPL.
*/
#ifndef LZF_H
#define LZF_H
/***********************************************************************
**
** lzf -- an extremely fast/free compression/decompression-method
** path_to_url
**
** This algorithm is believed to be patent-free.
**
***********************************************************************/
#define LZF_VERSION 0x0105 /* 1.5, API version */
/*
* Compress in_len bytes stored at the memory block starting at
* in_data and write the result to out_data, up to a maximum length
* of out_len bytes.
*
* If the output buffer is not large enough or any error occurs return 0,
* otherwise return the number of bytes used, which might be considerably
* more than in_len (but less than 104% of the original size), so it
* makes sense to always use out_len == in_len - 1), to ensure _some_
* compression, and store the data uncompressed otherwise (with a flag, of
* course.
*
* lzf_compress might use different algorithms on different systems and
* even different runs, thus might result in different compressed strings
* depending on the phase of the moon or similar factors. However, all
* these strings are architecture-independent and will result in the
* original data when decompressed using lzf_decompress.
*
* The buffers must not be overlapping.
*
* If the option LZF_STATE_ARG is enabled, an extra argument must be
* supplied which is not reflected in this header file. Refer to lzfP.h
* and lzf_c.c.
*
*/
unsigned int
lzf_compress (const void *const in_data, unsigned int in_len,
void *out_data, unsigned int out_len);
/*
* Decompress data compressed with some version of the lzf_compress
* function and stored at location in_data and length in_len. The result
* will be stored at out_data up to a maximum of out_len characters.
*
* If the output buffer is not large enough to hold the decompressed
* data, a 0 is returned and errno is set to E2BIG. Otherwise the number
* of decompressed bytes (i.e. the original length of the data) is
* returned.
*
* If an error in the compressed data is detected, a zero is returned and
* errno is set to EINVAL.
*
* This function is very fast, about as fast as a copying loop.
*/
unsigned int
lzf_decompress (const void *const in_data, unsigned int in_len,
void *out_data, unsigned int out_len);
#endif
``` | /content/code_sandbox/src/include/lzf.h | objective-c | 2016-06-25T22:29:10 | 2024-08-16T19:09:21 | 86Box | 86Box/86Box | 2,616 | 927 |
```objective-c
/*
* 86Box A hypervisor and IBM PC system emulator that specializes in
* running old operating systems and software designed for IBM
* PC systems and compatibles from 1981 through fairly recent
* system designs based on the PCI bus.
*
* This file is part of the 86Box distribution.
*
* Definitions for the FDI floppy file format.
*
*
*
* Authors: Toni Wilen, <twilen@arabuusimiehet.com>
* and Vincent Joguin,
* Thomas Harte, <T.Harte@excite.co.uk>
*
*/
#ifndef __FDI2RAW_H
#define __FDI2RAW_H
#include <stdint.h>
#include <stdbool.h>
#include <stdio.h>
typedef struct fdi FDI;
#ifdef __cplusplus
extern "C" {
#endif
/*!
Attempts to parse and return an FDI header from the file @c file.
@parameter file the file from which to attempt to read the FDI.
@returns a newly-allocated `FDI` if parsing succeeded; @c NULL otherwise.
*/
extern FDI *fdi2raw_header(FILE *file);
/*!
Release all memory associated with @c file.
*/
extern void fdi2raw_header_free(FDI *file);
extern int fdi2raw_loadtrack(FDI *, uint16_t *mfmbuf, uint16_t *tracktiming, int track, int *tracklength, int *indexoffset, int *multirev, int mfm);
extern int fdi2raw_loadrevolution(FDI *, uint16_t *mfmbuf, uint16_t *tracktiming, int track, int *tracklength, int mfm);
typedef enum {
FDI2RawDiskType8Inch = 0,
FDI2RawDiskType5_25Inch = 1,
FDI2RawDiskType3_5Inch = 2,
FDI2RawDiskType3Inch = 3,
} FDI2RawDiskType;
/// @returns the disk type described by @c fdi.
extern FDI2RawDiskType fdi2raw_get_type(FDI *fdi);
/// @returns the bit rate at which @c fdi is sampled if spinning at the intended rate, in Kbit/s.
extern int fdi2raw_get_bit_rate(FDI *fdi);
/// @returns the intended rotation speed of @c fdi, in rotations per minute.
extern int fdi2raw_get_rotation(FDI *fdi);
/// @returns whether the imaged disk was write protected.
extern bool fdi2raw_get_write_protect(FDI *fdi);
/// @returns the final enumerated track represented in @c fdi.
extern int fdi2raw_get_last_track(FDI *fdi);
/// @returns the final enumerated head represented in @c fdi.
extern int fdi2raw_get_last_head(FDI *fdi);
/// @returns @c 22 if track 0 is a standard Amiga high-density; @c 11 otherwise.
extern int fdi2raw_get_num_sector(FDI *fdi);
extern int fdi2raw_get_tpi(FDI *fdi);
#ifdef __cplusplus
}
#endif
#endif
``` | /content/code_sandbox/src/include/fdi2raw.h | objective-c | 2016-06-25T22:29:10 | 2024-08-16T19:09:21 | 86Box | 86Box/86Box | 2,616 | 685 |
```objective-c
/* map xaudio2 API to faudio API */
typedef uint32_t HRESULT;
typedef uint32_t UINT32;
typedef uint32_t DWORD;
typedef uint8_t BOOL;
#define WINAPI FAUDIOCALL
#define TRUE 1
#define FALSE 0
#define S_OK 0
#define XAUDIO2_E_INVALID_CALL FAUDIO_E_INVALID_CALL
#define XAUDIO2_DEFAULT_PROCESSOR FAUDIO_DEFAULT_PROCESSOR
#define XAUDIO2_COMMIT_NOW FAUDIO_COMMIT_NOW
#define XAUDIO2_END_OF_STREAM FAUDIO_END_OF_STREAM
#define WAVE_FORMAT_PCM FAUDIO_FORMAT_PCM
#define WAVE_FORMAT_IEEE_FLOAT FAUDIO_FORMAT_IEEE_FLOAT
#define AudioCategory_GameEffects FAudioStreamCategory_GameEffects
#define GlobalDefaultDevice FAudioGlobalDefaultDevice
#define NotDefaultDevice FAudioNotDefaultDevice
#define XAudio2Create FAudioCreate
typedef FAudioBuffer XAUDIO2_BUFFER;
typedef FAudioDeviceDetails XAUDIO2_DEVICE_DETAILS;
typedef FAudioEffectChain XAUDIO2_EFFECT_CHAIN;
typedef FAudioEffectDescriptor XAUDIO2_EFFECT_DESCRIPTOR;
typedef FAudioVoiceDetails XAUDIO2_VOICE_DETAILS;
typedef FAudioVoiceDetails XAUDIO27_VOICE_DETAILS;
typedef FAudioVoiceState XAUDIO2_VOICE_STATE;
typedef FAudioWaveFormatEx WAVEFORMATEX;
typedef FAudioPerformanceData XAUDIO2_PERFORMANCE_DATA;
typedef FAudioEngineCallback IXAudio2EngineCallback;
typedef FAudioVoiceCallback IXAudio2VoiceCallback;
typedef FAPO IXAPO;
typedef FAudio IXAudio27;
#define IXAudio27_CreateMasteringVoice FAudio_CreateMasteringVoice
#define IXAudio27_CreateSourceVoice FAudio_CreateSourceVoice
#define IXAudio27_CreateSubmixVoice FAudio_CreateSubmixVoice
#define IXAudio27_GetDeviceCount FAudio_GetDeviceCount
#define IXAudio27_GetDeviceDetails FAudio_GetDeviceDetails
#define IXAudio27_GetPerformanceData FAudio_GetPerformanceData
#define IXAudio27_Initialize FAudio_Initialize
#define IXAudio27_RegisterForCallbacks FAudio_RegisterForCallbacks
#define IXAudio27_Release FAudio_Release
#define IXAudio27_StartEngine FAudio_StartEngine
#define IXAudio27_StopEngine FAudio_StopEngine
#define IXAudio27_UnregisterForCallbacks FAudio_UnregisterForCallbacks
typedef FAudio IXAudio2;
#define IXAudio2_CreateMasteringVoice FAudio_CreateMasteringVoice8
#define IXAudio2_CreateSourceVoice FAudio_CreateSourceVoice
#define IXAudio2_CreateSubmixVoice FAudio_CreateSubmixVoice
#define IXAudio2_GetPerformanceData FAudio_GetPerformanceData
#define IXAudio2_RegisterForCallbacks FAudio_RegisterForCallbacks
#define IXAudio2_Release FAudio_Release
#define IXAudio2_StartEngine FAudio_StartEngine
#define IXAudio2_StopEngine FAudio_StopEngine
#define IXAudio2_UnregisterForCallbacks FAudio_UnregisterForCallbacks
typedef FAudioMasteringVoice IXAudio2MasteringVoice;
#define IXAudio2MasteringVoice_DestroyVoice FAudioVoice_DestroyVoice
#define IXAudio2MasteringVoice_GetChannelMask FAudioMasteringVoice_GetChannelMask
#define IXAudio2MasteringVoice_SetEffectChain FAudioVoice_SetEffectChain
#define IXAudio2MasteringVoice_SetVolume FAudioVoice_SetVolume
typedef FAudioSourceVoice IXAudio27SourceVoice;
#define IXAudio27SourceVoice_DestroyVoice FAudioVoice_DestroyVoice
#define IXAudio27SourceVoice_ExitLoop FAudioSourceVoice_ExitLoop
#define IXAudio27SourceVoice_FlushSourceBuffers FAudioSourceVoice_FlushSourceBuffers
#define IXAudio27SourceVoice_GetState(a,b) FAudioSourceVoice_GetState(a,b,0)
#define IXAudio27SourceVoice_GetVoiceDetails FAudioVoice_GetVoiceDetails
#define IXAudio27SourceVoice_SetChannelVolumes FAudioVoice_SetChannelVolumes
#define IXAudio27SourceVoice_SetSourceSampleRate FAudioSourceVoice_SetSourceSampleRate
#define IXAudio27SourceVoice_Start FAudioSourceVoice_Start
#define IXAudio27SourceVoice_Stop FAudioSourceVoice_Stop
#define IXAudio27SourceVoice_SubmitSourceBuffer FAudioSourceVoice_SubmitSourceBuffer
typedef FAudioSourceVoice IXAudio2SourceVoice;
#define IXAudio2SourceVoice_DestroyVoice FAudioVoice_DestroyVoice
#define IXAudio2SourceVoice_ExitLoop FAudioSourceVoice_ExitLoop
#define IXAudio2SourceVoice_FlushSourceBuffers FAudioSourceVoice_FlushSourceBuffers
#define IXAudio2SourceVoice_GetState FAudioSourceVoice_GetState
#define IXAudio2SourceVoice_GetVoiceDetails FAudioVoice_GetVoiceDetails
#define IXAudio2SourceVoice_SetChannelVolumes FAudioVoice_SetChannelVolumes
#define IXAudio2SourceVoice_SetSourceSampleRate FAudioSourceVoice_SetSourceSampleRate
#define IXAudio2SourceVoice_SetVolume FAudioVoice_SetVolume
#define IXAudio2SourceVoice_Start FAudioSourceVoice_Start
#define IXAudio2SourceVoice_Stop FAudioSourceVoice_Stop
#define IXAudio2SourceVoice_SubmitSourceBuffer FAudioSourceVoice_SubmitSourceBuffer
typedef FAudioSubmixVoice IXAudio27SubmixVoice;
#define IXAudio27SubmixVoice_GetVoiceDetails FAudioVoice_GetVoiceDetails
#define IXAudio27SubmixVoice_DestroyVoice FAudioVoice_DestroyVoice
typedef FAudioSubmixVoice IXAudio2SubmixVoice;
#define IXAudio2SubmixVoice_GetVoiceDetails FAudioVoice_GetVoiceDetails
#define IXAudio2SubmixVoice_DestroyVoice FAudioVoice_DestroyVoice
``` | /content/code_sandbox/src/include/FAudio_compat.h | objective-c | 2016-06-25T22:29:10 | 2024-08-16T19:09:21 | 86Box | 86Box/86Box | 2,616 | 1,117 |
```c
/*
* 86Box A hypervisor and IBM PC system emulator that specializes in
* running old operating systems and software designed for IBM
* PC systems and compatibles from 1981 through fairly recent
* system designs based on the PCI bus.
*
* This file is part of the 86Box distribution.
*
* Emulation of the ImageManager 1024 video controller.
*
* Just enough of the Vermont Microsystems IM-1024 is implemented
* to support the Windows 1.03 driver. Functions are partially
* implemented or hardwired to the behavior expected by the
* Windows driver.
*
* One major difference seems to be that in hex mode, coordinates
* are passed as 2-byte integer words rather than 4-byte
* fixed-point fractions.
*
* It is unknown what triggers this, so for now it's always on.
*
* As well as the usual PGC ring buffer at 0xC6000, the IM1024
* appears to have an alternate method of passing commands. This
* is enabled by setting 0xC6330 to 1, and then:
*
* CX = count to write
* SI -> bytes to write
*
* Set pending bytes to 0
* Read [C6331]. This gives number of bytes that can be written:
* 0xFF => 0, 0xFE => 1, 0xFD => 2 etc.
* Write that number of bytes to C6000.
* If there are more to come, go back to reading [C6331].
*
* As far as can be determined, at least one byte is always
* written; there is no provision to pause if the queue is full.
*
* This is implemented by holding a FIFO of unlimited depth in
* the IM1024 to receive the data.
*
*
*
* Authors: Fred N. van Kempen, <decwiz@yahoo.com>
* John Elliott, <jce@seasip.info>
*
*/
#include <stdarg.h>
#include <stdio.h>
#include <stdint.h>
#include <string.h>
#include <stdlib.h>
#include <wchar.h>
#include <ctype.h>
#define HAVE_STDARG_H
#include <86box/86box.h>
#include <86box/io.h>
#include <86box/mem.h>
#include <86box/rom.h>
#include <86box/timer.h>
#include <86box/device.h>
#include <86box/pit.h>
#include <86box/plat.h>
#include <86box/thread.h>
#include <86box/video.h>
#include <86box/vid_pgc.h>
#define BIOS_ROM_PATH "roms/video/im1024/im1024font.bin"
typedef struct {
pgc_t pgc;
uint8_t fontx[256];
uint8_t fonty[256];
uint8_t font[256][128];
uint8_t *fifo;
unsigned fifo_len,
fifo_wrptr,
fifo_rdptr;
} im1024_t;
static video_timings_t timing_im1024 = { .type = VIDEO_ISA, .write_b = 8, .write_w = 16, .write_l = 32, .read_b = 8, .read_w = 16, .read_l = 32 };
#ifdef ENABLE_IM1024_LOG
int im1024_do_log = ENABLE_IM1024_LOG;
static void
im1024_log(const char *fmt, ...)
{
va_list ap;
if (im1024_do_log) {
va_start(ap, fmt);
pclog_ex(fmt, ap);
va_end(ap);
}
}
#else
# define im1024_log(fmt, ...)
#endif
static void
fifo_write(im1024_t *dev, uint8_t val)
{
im1024_log("IM1024: fifo_write: %02x [rd=%04x wr=%04x]\n",
val, dev->fifo_rdptr, dev->fifo_wrptr);
if (((dev->fifo_wrptr + 1) % dev->fifo_len) == dev->fifo_rdptr) {
/* FIFO is full. Double its size. */
uint8_t *buf;
im1024_log("IM1024: fifo_resize: %i to %i\n",
dev->fifo_len, 2 * dev->fifo_len);
buf = realloc(dev->fifo, 2 * dev->fifo_len);
if (buf == NULL)
return;
/* Move the [0..wrptr] range to the newly-allocated area [len..len+wrptr] */
memmove(buf + dev->fifo_len, buf, dev->fifo_wrptr);
dev->fifo = buf;
dev->fifo_wrptr += dev->fifo_len;
dev->fifo_len *= 2;
}
/* Append to the queue. */
dev->fifo[dev->fifo_wrptr++] = val;
/* Wrap if end of buffer reached. */
if (dev->fifo_wrptr >= dev->fifo_len)
dev->fifo_wrptr = 0;
}
static int
fifo_read(im1024_t *dev)
{
uint8_t ret;
if (dev->fifo_wrptr == dev->fifo_rdptr)
return -1; /* FIFO empty */
ret = dev->fifo[dev->fifo_rdptr++];
if (dev->fifo_rdptr >= dev->fifo_len)
dev->fifo_rdptr = 0;
im1024_log("IM1024: fifo_read: %02x\n", ret);
return ret;
}
/*
* Where a normal PGC would just read from the ring buffer at 0xC6300,
* the IM-1024 can read from either this or from its internal FIFO.
*
* The internal FIFO has priority.
*/
static int
input_byte(pgc_t *pgc, uint8_t *result)
{
im1024_t *dev = (im1024_t *) pgc;
/* If input buffer empty, wait for it to fill. */
while (!pgc->stopped && (dev->fifo_wrptr == dev->fifo_rdptr) && (pgc->mapram[0x300] == pgc->mapram[0x301])) {
pgc->waiting_input_fifo = 1;
pgc_sleep(pgc);
}
if (pgc->stopped)
return 0;
if (pgc->mapram[0x3ff]) {
/* Reset triggered. */
pgc_reset(pgc);
return 0;
}
if (dev->fifo_wrptr == dev->fifo_rdptr) {
*result = pgc->mapram[pgc->mapram[0x301]];
pgc->mapram[0x301]++;
} else
*result = fifo_read(dev);
return 1;
}
/* Macros to disable clipping and save clip state. */
#define PUSHCLIP \
{ \
uint16_t vp_x1, vp_x2, vp_y1, vp_y2; \
vp_x1 = pgc->vp_x1; \
vp_y1 = pgc->vp_y1; \
vp_x2 = pgc->vp_x2; \
vp_y2 = pgc->vp_y2; \
pgc->vp_x1 = 0; \
pgc->vp_y1 = 0; \
pgc->vp_x2 = pgc->maxw - 1; \
pgc->vp_y2 = pgc->maxh - 1;
/* And to restore clip state */
#define POPCLIP \
pgc->vp_x1 = vp_x1; \
pgc->vp_y1 = vp_y1; \
pgc->vp_x2 = vp_x2; \
pgc->vp_y2 = vp_y2; \
}
/* Override memory read to return FIFO space. */
static uint8_t
im1024_read(uint32_t addr, void *priv)
{
im1024_t *dev = (im1024_t *) priv;
if (addr == 0xc6331 && dev->pgc.mapram[0x330] == 1) {
/* Hardcode that there are 128 bytes free. */
return 0x80;
}
return (pgc_read(addr, &dev->pgc));
}
/* Override memory write to handle writes to the FIFO. */
static void
im1024_write(uint32_t addr, uint8_t val, void *priv)
{
im1024_t *dev = (im1024_t *) priv;
/*
* If we are in 'fast' input mode, send all
* writes to the internal FIFO.
*/
if (addr >= 0xc6000 && addr < 0xc6100 && dev->pgc.mapram[0x330] == 1) {
fifo_write(dev, val);
im1024_log("IM1024: write(%02x)\n", val);
if (dev->pgc.waiting_input_fifo) {
dev->pgc.waiting_input_fifo = 0;
pgc_wake(&dev->pgc);
}
return;
}
pgc_write(addr, val, &dev->pgc);
}
/*
* I don't know what the IMGSIZ command does, only that the
* Windows driver issues it. So just parse and ignore it.
*/
static void
hndl_imgsiz(pgc_t *pgc)
{
#if 0
im1024_t *dev = (im1024_t *)pgc;
#endif
int16_t w;
int16_t h;
uint8_t a;
uint8_t b;
if (!pgc_param_word(pgc, &w))
return;
if (!pgc_param_word(pgc, &h))
return;
if (!pgc_param_byte(pgc, &a))
return;
if (!pgc_param_byte(pgc, &b))
return;
im1024_log("IM1024: IMGSIZ %i,%i,%i,%i\n", w, h, a, b);
}
/*
* I don't know what the IPREC command does, only that the
* Windows driver issues it. So just parse and ignore it.
*/
static void
hndl_iprec(pgc_t *pgc)
{
#if 0
im1024_t *dev = (im1024_t *)pgc;
#endif
uint8_t param;
if (!pgc_param_byte(pgc, ¶m))
return;
im1024_log("IM1024: IPREC %i\n", param);
}
/*
* Set drawing mode.
*
* 0 => Draw
* 1 => Invert
* 2 => XOR (IM-1024)
* 3 => AND (IM-1024)
*/
static void
hndl_linfun(pgc_t *pgc)
{
uint8_t param;
if (!pgc_param_byte(pgc, ¶m))
return;
if (param < 4) {
pgc->draw_mode = param;
im1024_log("IM1024: LINFUN(%i)\n", param);
} else
pgc_error(pgc, PGC_ERROR_RANGE);
}
/*
* I think PAN controls which part of the 1024x1024 framebuffer
* is displayed in the 1024x800 visible screen.
*/
static void
hndl_pan(pgc_t *pgc)
{
int16_t x;
int16_t y;
if (!pgc_param_word(pgc, &x))
return;
if (!pgc_param_word(pgc, &y))
return;
im1024_log("IM1024: PAN %i,%i\n", x, y);
pgc->pan_x = x;
pgc->pan_y = y;
}
/* PLINE draws a non-filled polyline at a fixed position. */
static void
hndl_pline(pgc_t *pgc)
{
int16_t x[257];
int16_t y[257];
uint16_t linemask = pgc->line_pattern;
uint8_t count;
unsigned n;
if (!pgc_param_byte(pgc, &count))
return;
im1024_log("IM1024: PLINE (%i) ", count);
for (n = 0; n < count; n++) {
if (!pgc_param_word(pgc, &x[n]))
return;
if (!pgc_param_word(pgc, &y[n]))
return;
im1024_log(" (%i,%i)\n", x[n], y[n]);
}
for (n = 1; n < count; n++) {
linemask = pgc_draw_line(pgc, x[n - 1] << 16, y[n - 1] << 16,
x[n] << 16, y[n] << 16, linemask);
}
}
/*
* Blit a single row of pixels from one location to another.
*
* To avoid difficulties if the two overlap, read both rows
* into memory, process them there, and write the result back.
*/
static void
blkmov_row(pgc_t *pgc, int16_t x0, int16_t x1, int16_t x2, int16_t sy, int16_t ty)
{
uint8_t src[1024];
uint8_t dst[1024];
int16_t x;
for (x = x0; x <= x1; x++) {
src[x - x0] = pgc_read_pixel(pgc, x, sy);
dst[x - x0] = pgc_read_pixel(pgc, x - x0 + x2, ty);
}
for (x = x0; x <= x1; x++)
switch (pgc->draw_mode) {
default:
case 0:
pgc_write_pixel(pgc, (x - x0 + x2), ty, src[x - x0]);
break;
case 1:
pgc_write_pixel(pgc, (x - x0 + x2), ty, dst[x - x0] ^ 0xff);
break;
case 2:
pgc_write_pixel(pgc, (x - x0 + x2), ty, src[x - x0] ^ dst[x - x0]);
break;
case 3:
pgc_write_pixel(pgc, (x - x0 + x2), ty, src[x - x0] & dst[x - x0]);
break;
}
}
/*
* BLKMOV blits a rectangular area from one location to another.
*
* Clipping is disabled.
*/
static void
hndl_blkmov(pgc_t *pgc)
{
int16_t x0;
int16_t y0;
int16_t x1;
int16_t y1;
int16_t x2;
int16_t y2;
int16_t y;
if (!pgc_param_word(pgc, &x0))
return;
if (!pgc_param_word(pgc, &y0))
return;
if (!pgc_param_word(pgc, &x1))
return;
if (!pgc_param_word(pgc, &y1))
return;
if (!pgc_param_word(pgc, &x2))
return;
if (!pgc_param_word(pgc, &y2))
return;
im1024_log("IM1024: BLKMOV %i,%i,%i,%i,%i,%i\n", x0, y0, x1, y1, x2, y2);
/* Disable clipping. */
PUSHCLIP
/*
* Either go down from the top, or up from the bottom,
* depending whether areas might overlap.
*/
if (y2 <= y0) {
for (y = y0; y <= y1; y++)
blkmov_row(pgc, x0, x1, x2, y, y - y0 + y2);
} else {
for (y = y1; y >= y0; y--)
blkmov_row(pgc, x0, x1, x2, y, y - y0 + y2);
}
/* Restore clipping. */
POPCLIP
}
/*
* Override the PGC ELIPSE command to parse its
* parameters as words rather than coordinates.
*/
static void
hndl_ellipse(pgc_t *pgc)
{
int16_t x;
int16_t y;
if (!pgc_param_word(pgc, &x))
return;
if (!pgc_param_word(pgc, &y))
return;
im1024_log("IM1024: ELLIPSE %i,%i @ %i,%i\n",
x, y, pgc->x >> 16, pgc->y >> 16);
pgc_draw_ellipse(pgc, x << 16, y << 16);
}
/*
* Override the PGC MOVE command to parse its
* parameters as words rather than coordinates.
*/
static void
hndl_move(pgc_t *pgc)
{
int16_t x;
int16_t y;
if (!pgc_param_word(pgc, &x))
return;
if (!pgc_param_word(pgc, &y))
return;
im1024_log("IM1024: MOVE %i,%i\n", x, y);
pgc->x = x << 16;
pgc->y = y << 16;
}
/*
* Override the PGC DRAW command to parse its
* parameters as words rather than coordinates.
*/
static void
hndl_draw(pgc_t *pgc)
{
int16_t x;
int16_t y;
if (!pgc_param_word(pgc, &x))
return;
if (!pgc_param_word(pgc, &y))
return;
im1024_log("IM1024: DRAW %i,%i to %i,%i\n", pgc->x >> 16, pgc->y >> 16, x, y);
pgc_draw_line(pgc, pgc->x, pgc->y, x << 16, y << 16, pgc->line_pattern);
pgc->x = x << 16;
pgc->y = y << 16;
}
/*
* Override the PGC POLY command to parse its
* parameters as words rather than coordinates.
*/
static void
hndl_poly(pgc_t *pgc)
{
int32_t *x;
int32_t *y;
int32_t *nx;
int32_t *ny;
int16_t xw;
int16_t yw;
int16_t mask;
unsigned realcount = 0;
unsigned n;
unsigned as = 256;
int parsing = 1;
uint8_t count;
x = (int32_t *) malloc(as * sizeof(int32_t));
y = (int32_t *) malloc(as * sizeof(int32_t));
if (!x || !y) {
#ifdef ENABLE_IM1024_LOG
im1024_log("IM1024: POLY: out of memory\n");
#endif
if (x)
free(x);
if (y)
free(y);
return;
}
while (parsing) {
if (!pgc_param_byte(pgc, &count)) {
if (x)
free(x);
if (y)
free(y);
return;
}
if (count + realcount >= as) {
nx = (int32_t *) realloc(x, 2 * as * sizeof(int32_t));
ny = (int32_t *) realloc(y, 2 * as * sizeof(int32_t));
if (!x || !y) {
#ifdef ENABLE_IM1024_LOG
im1024_log("IM1024: poly: realloc failed\n");
#endif
break;
}
x = nx;
y = ny;
as *= 2;
}
for (n = 0; n < count; n++) {
if (!pgc_param_word(pgc, &xw)) {
if (x)
free(x);
if (y)
free(y);
return;
}
if (!pgc_param_word(pgc, &yw)) {
if (x)
free(x);
if (y)
free(y);
return;
}
/* Skip degenerate line segments. */
if (realcount > 0 && (xw << 16) == x[realcount - 1] && (yw << 16) == y[realcount - 1])
continue;
x[realcount] = xw << 16;
y[realcount] = yw << 16;
realcount++;
}
/*
* If we are in a command list, peek ahead to see if the next
* command is also POLY. If so, that's a continuation of this
* polygon!
*/
parsing = 0;
if (pgc->clcur && (pgc->clcur->rdptr + 1) < pgc->clcur->wrptr && pgc->clcur->list[pgc->clcur->rdptr] == 0x30) {
#ifdef ENABLE_IM1024_LOG
im1024_log("IM1024: POLY continues!\n");
#endif
parsing = 1;
/* Swallow the POLY. */
pgc->clcur->rdptr++;
}
}
im1024_log("IM1024: POLY (%i) fill_mode=%i\n", realcount, pgc->fill_mode);
#ifdef ENABLE_IM1024_LOG
for (n = 0; n < realcount; n++) {
im1024_log(" (%i,%i)\n", x[n] >> 16, y[n] >> 16);
}
#endif
if (pgc->fill_mode)
pgc_fill_polygon(pgc, realcount, x, y);
/* Now draw borders. */
mask = pgc->line_pattern;
for (n = 1; n < realcount; n++)
mask = pgc_draw_line(pgc, x[n - 1], y[n - 1], x[n], y[n], mask);
pgc_draw_line(pgc, x[realcount - 1], y[realcount - 1], x[0], y[0], mask);
free(y);
free(x);
}
static int
parse_poly(pgc_t *pgc, pgc_cl_t *cl, UNUSED(int c))
{
uint8_t count;
#ifdef ENABLE_IM1024_LOG
im1024_log("IM1024: parse_poly\n");
#endif
if (!pgc_param_byte(pgc, &count))
return 0;
im1024_log("IM1024: parse_poly: count=%02x\n", count);
if (!pgc_cl_append(cl, count)) {
pgc_error(pgc, PGC_ERROR_OVERFLOW);
return 0;
}
im1024_log("IM1024: parse_poly: parse %i words\n", 2 * count);
return pgc_parse_words(pgc, cl, count * 2);
}
/*
* Override the PGC RECT command to parse its
* parameters as words rather than coordinates.
*/
static void
hndl_rect(pgc_t *pgc)
{
int16_t x0;
int16_t y0;
int16_t x1;
int16_t y1;
int16_t p;
int16_t q;
x0 = pgc->x >> 16;
y0 = pgc->y >> 16;
if (!pgc_param_word(pgc, &x1))
return;
if (!pgc_param_word(pgc, &y1))
return;
/* Convert to raster coords. */
pgc_sto_raster(pgc, &x0, &y0);
pgc_sto_raster(pgc, &x1, &y1);
if (x0 > x1) {
p = x0;
x0 = x1;
x1 = p;
}
if (y0 > y1) {
q = y0;
y0 = y1;
y1 = q;
}
im1024_log("IM1024: RECT (%i,%i) -> (%i,%i)\n", x0, y0, x1, y1);
if (pgc->fill_mode) {
for (p = y0; p <= y1; p++)
pgc_fill_line_r(pgc, x0, x1, p);
} else {
/* Outline: 4 lines. */
p = pgc->line_pattern;
p = pgc_draw_line_r(pgc, x0, y0, x1, y0, p);
p = pgc_draw_line_r(pgc, x1, y0, x1, y1, p);
p = pgc_draw_line_r(pgc, x1, y1, x0, y1, p);
p = pgc_draw_line_r(pgc, x0, y1, x0, y0, p);
}
}
/*
* FIXME:
* Define a font character.
*
* Text drawing should probably be implemented in
* vid_pgc.c rather than here..
*/
static void
hndl_tdefin(pgc_t *pgc)
{
im1024_t *dev = (im1024_t *) pgc;
uint8_t ch;
uint8_t bt;
uint8_t rows;
uint8_t cols;
unsigned len;
if (!pgc_param_byte(pgc, &ch))
return;
if (!pgc_param_byte(pgc, &cols))
return;
if (!pgc_param_byte(pgc, &rows))
return;
im1024_log("IM1024: TDEFIN (%i,%i,%i) 0x%02x 0x%02x\n",
ch, rows, cols, pgc->mapram[0x300], pgc->mapram[0x301]);
len = ((cols + 7) / 8) * rows;
for (unsigned int n = 0; n < len; n++) {
if (!pgc_param_byte(pgc, &bt))
return;
if (n < sizeof(dev->font[ch]))
dev->font[ch][n] = bt;
}
dev->fontx[ch] = cols;
dev->fonty[ch] = rows;
}
static void
hndl_tsize(pgc_t *pgc)
{
int16_t size;
if (!pgc_param_word(pgc, &size))
return;
im1024_log("IM1024: TSIZE(%i)\n", size);
pgc->tsize = size << 16;
}
static void
hndl_twrite(pgc_t *pgc)
{
uint8_t buf[256];
const im1024_t *dev = (im1024_t *) pgc;
uint8_t count;
uint8_t mask;
const uint8_t *row;
int wb;
int n;
int16_t x0 = pgc->x >> 16;
int16_t y0 = pgc->y >> 16;
if (!pgc_param_byte(pgc, &count))
return;
for (n = 0; n < count; n++)
if (!pgc_param_byte(pgc, &buf[n]))
return;
buf[count] = 0;
pgc_sto_raster(pgc, &x0, &y0);
im1024_log("IM1024: TWRITE (%i) x0=%i y0=%i\n", count, x0, y0);
for (n = 0; n < count; n++) {
wb = (dev->fontx[buf[n]] + 7) / 8;
im1024_log("IM1024: ch=0x%02x w=%i h=%i wb=%i\n",
buf[n], dev->fontx[buf[n]], dev->fonty[buf[n]], wb);
for (uint8_t y = 0; y < dev->fonty[buf[n]]; y++) {
mask = 0x80;
row = &dev->font[buf[n]][y * wb];
for (uint8_t x = 0; x < dev->fontx[buf[n]]; x++) {
if (row[0] & mask)
pgc_plot(pgc, x + x0, y0 - y);
mask = mask >> 1;
if (mask == 0) {
mask = 0x80;
row++;
}
}
}
x0 += dev->fontx[buf[n]];
}
}
static void
hndl_txt88(pgc_t *pgc)
{
uint8_t buf[256];
uint8_t count;
uint8_t mask;
const uint8_t *row;
int16_t x0 = pgc->x >> 16;
int16_t y0 = pgc->y >> 16;
unsigned int n;
if (!pgc_param_byte(pgc, &count))
return;
for (n = 0; n < count; n++)
if (!pgc_param_byte(pgc, &buf[n]))
return;
buf[count] = 0;
pgc_sto_raster(pgc, &x0, &y0);
im1024_log("IM204: TXT88 (%i) x0=%i y0=%i\n", count, x0, y0);
for (n = 0; n < count; n++) {
im1024_log("ch=0x%02x w=12 h=18\n", buf[n]);
for (uint8_t y = 0; y < 18; y++) {
mask = 0x80;
row = &fontdat12x18[buf[n]][y * 2];
for (uint8_t x = 0; x < 12; x++) {
if (row[0] & mask)
pgc_plot(pgc, x + x0, y0 - y);
mask = mask >> 1;
if (mask == 0) {
mask = 0x80;
row++;
}
}
}
x0 += 12;
}
}
static void
hndl_imagew(pgc_t *pgc)
{
int16_t vp_x1;
int16_t vp_y1;
int16_t vp_x2;
int16_t vp_y2;
int16_t row1;
int16_t col1;
int16_t col2;
uint8_t v1;
uint8_t v2;
if (!pgc_param_word(pgc, &row1))
return;
if (!pgc_param_word(pgc, &col1))
return;
if (!pgc_param_word(pgc, &col2))
return;
/* Already using raster coordinates, no need to convert. */
im1024_log("IM1024: IMAGEW (row=%i,col1=%i,col2=%i)\n", row1, col1, col2);
vp_x1 = pgc->vp_x1;
vp_y1 = pgc->vp_y1;
vp_x2 = pgc->vp_x2;
vp_y2 = pgc->vp_y2;
/* Disable clipping. */
pgc->vp_x1 = 0;
pgc->vp_y1 = 0;
pgc->vp_x2 = pgc->maxw - 1;
pgc->vp_y2 = pgc->maxh - 1;
/* In ASCII mode, what is written is a stream of bytes. */
if (pgc->ascii_mode) {
while (col1 <= col2) {
if (!pgc_param_byte(pgc, &v1))
return;
pgc_write_pixel(pgc, col1, row1, v1);
col1++;
}
} else {
/* In hex mode, it's RLE compressed. */
while (col1 <= col2) {
if (!pgc_param_byte(pgc, &v1))
return;
if (v1 & 0x80) {
/* Literal run. */
v1 -= 0x7f;
while (col1 <= col2 && v1 != 0) {
if (!pgc_param_byte(pgc, &v2))
return;
pgc_write_pixel(pgc, col1, row1, v2);
col1++;
v1--;
}
} else {
/* Repeated run. */
if (!pgc_param_byte(pgc, &v2))
return;
v1++;
while (col1 <= col2 && v1 != 0) {
pgc_write_pixel(pgc, col1, row1, v2);
col1++;
v1--;
}
}
}
}
/* Restore clipping. */
pgc->vp_x1 = vp_x1;
pgc->vp_y1 = vp_y1;
pgc->vp_x2 = vp_x2;
pgc->vp_y2 = vp_y2;
}
/*
* I have called this command DOT - I don't know its proper name.
*
* Draws a single pixel at the current location.
*/
static void
hndl_dot(pgc_t *pgc)
{
int16_t x = pgc->x >> 16;
int16_t y = pgc->y >> 16;
pgc_sto_raster(pgc, &x, &y);
im1024_log("IM1024: DOT @ %i,%i ink=%i mode=%i\n",
x, y, pgc->color, pgc->draw_mode);
pgc_plot(pgc, x, y);
}
/*
* This command (which I have called IMAGEX, since I don't know its real
* name) is a screen-to-memory blit. It reads a rectangle of bytes, rather
* than the single row read by IMAGER, and does not attempt to compress
* the result.
*/
static void
hndl_imagex(pgc_t *pgc)
{
int16_t x0;
int16_t x1;
int16_t y0;
int16_t y1;
if (!pgc_param_word(pgc, &x0))
return;
if (!pgc_param_word(pgc, &y0))
return;
if (!pgc_param_word(pgc, &x1))
return;
if (!pgc_param_word(pgc, &y1))
return;
/* Already using raster coordinates, no need to convert. */
im1024_log("IM1024: IMAGEX (%i,%i,%i,%i)\n", x0, y0, x1, y1);
for (int16_t p = y0; p <= y1; p++) {
for (int16_t q = x0; q <= x1; q++) {
if (!pgc_result_byte(pgc, pgc_read_pixel(pgc, q, p)))
return;
}
}
}
/*
* Commands implemented by the IM-1024.
*
* TODO: A lot of commands need commandlist parsers.
* TODO: The IM-1024 has a lot more commands that are not included here
* (BLINK, BUTRD, COPROC, RBAND etc) because the Windows 1.03 driver
* does not use them.
*/
static const pgc_cmd_t im1024_commands[] = {
{"BLKMOV", 0xdf, hndl_blkmov, pgc_parse_words, 6},
{ "DRAW", 0x28, hndl_draw, pgc_parse_words, 2},
{ "D", 0x28, hndl_draw, pgc_parse_words, 2},
{ "DOT", 0x08, hndl_dot, NULL, 0},
{ "ELIPSE", 0x39, hndl_ellipse, pgc_parse_words, 2},
{ "EL", 0x39, hndl_ellipse, pgc_parse_words, 2},
{ "IMAGEW", 0xd9, hndl_imagew, NULL, 0},
{ "IMAGEX", 0xda, hndl_imagex, NULL, 0},
{ "IMGSIZ", 0x4e, hndl_imgsiz, NULL, 0},
{ "IPREC", 0xe4, hndl_iprec, NULL, 0},
{ "IW", 0xd9, hndl_imagew, NULL, 0},
{ "L8", 0xe6, pgc_hndl_lut8, NULL, 0},
{ "LF", 0xeb, hndl_linfun, pgc_parse_bytes, 1},
{ "LINFUN", 0xeb, hndl_linfun, pgc_parse_bytes, 1},
{ "LUT8", 0xe6, pgc_hndl_lut8, NULL, 0},
{ "LUT8RD", 0x53, pgc_hndl_lut8rd, NULL, 0},
{ "L8RD", 0x53, pgc_hndl_lut8rd, NULL, 0},
{ "TDEFIN", 0x84, hndl_tdefin, NULL, 0},
{ "TD", 0x84, hndl_tdefin, NULL, 0},
{ "TSIZE", 0x81, hndl_tsize, NULL, 0},
{ "TS", 0x81, hndl_tsize, NULL, 0},
{ "TWRITE", 0x8b, hndl_twrite, NULL, 0},
{ "TXT88", 0x88, hndl_txt88, NULL, 0},
{ "PAN", 0xb7, hndl_pan, NULL, 0},
{ "POLY", 0x30, hndl_poly, parse_poly, 0},
{ "P", 0x30, hndl_poly, parse_poly, 0},
{ "PLINE", 0x36, hndl_pline, NULL, 0},
{ "PL", 0x37, hndl_pline, NULL, 0},
{ "MOVE", 0x10, hndl_move, pgc_parse_words, 2},
{ "M", 0x10, hndl_move, pgc_parse_words, 2},
{ "RECT", 0x34, hndl_rect, NULL, 0},
{ "R", 0x34, hndl_rect, NULL, 0},
{ "******", 0x00, NULL, NULL, 0}
};
static void *
im1024_init(UNUSED(const device_t *info))
{
im1024_t *dev;
dev = (im1024_t *) malloc(sizeof(im1024_t));
memset(dev, 0x00, sizeof(im1024_t));
loadfont(BIOS_ROM_PATH, 9);
dev->fifo_len = 4096;
dev->fifo = (uint8_t *) malloc(dev->fifo_len);
dev->fifo_wrptr = 0;
dev->fifo_rdptr = 0;
/* Create a 1024x1024 framebuffer with 1024x800 visible. */
pgc_init(&dev->pgc, 1024, 1024, 1024, 800, input_byte, 65000000.0);
dev->pgc.commands = im1024_commands;
mem_mapping_set_handler(&dev->pgc.mapping,
im1024_read, NULL, NULL, im1024_write, NULL, NULL);
video_inform(VIDEO_FLAG_TYPE_CGA, &timing_im1024);
return dev;
}
static void
im1024_close(void *priv)
{
im1024_t *dev = (im1024_t *) priv;
pgc_close_common(&dev->pgc);
free(dev);
}
static int
im1024_available(void)
{
return rom_present(BIOS_ROM_PATH);
}
static void
im1024_speed_changed(void *priv)
{
im1024_t *dev = (im1024_t *) priv;
pgc_speed_changed(&dev->pgc);
}
const device_t im1024_device = {
.name = "ImageManager 1024",
.internal_name = "im1024",
.flags = DEVICE_ISA,
.local = 0,
.init = im1024_init,
.close = im1024_close,
.reset = NULL,
{ .available = im1024_available },
.speed_changed = im1024_speed_changed,
.force_redraw = NULL,
.config = NULL
};
``` | /content/code_sandbox/src/video/vid_im1024.c | c | 2016-06-25T22:29:10 | 2024-08-16T19:09:21 | 86Box | 86Box/86Box | 2,616 | 9,117 |
```objective-c
/*
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
*/
#ifndef cJSON__h
#define cJSON__h
#ifdef __cplusplus
extern "C"
{
#endif
#if !defined(__WINDOWS__) && (defined(WIN32) || defined(WIN64) || defined(_MSC_VER) || defined(_WIN32))
#define __WINDOWS__
#endif
#ifdef __WINDOWS__
/* When compiling for windows, we specify a specific calling convention to avoid issues where we are being called from a project with a different default calling convention. For windows you have 3 define options:
CJSON_HIDE_SYMBOLS - Define this in the case where you don't want to ever dllexport symbols
CJSON_EXPORT_SYMBOLS - Define this on library build when you want to dllexport symbols (default)
CJSON_IMPORT_SYMBOLS - Define this if you want to dllimport symbol
For *nix builds that support visibility attribute, you can define similar behavior by
setting default visibility to hidden by adding
-fvisibility=hidden (for gcc)
or
-xldscope=hidden (for sun cc)
to CFLAGS
then using the CJSON_API_VISIBILITY flag to "export" the same symbols the way CJSON_EXPORT_SYMBOLS does
*/
#define CJSON_CDECL __cdecl
#define CJSON_STDCALL __stdcall
/* export symbols by default, this is necessary for copy pasting the C and header file */
#if !defined(CJSON_HIDE_SYMBOLS) && !defined(CJSON_IMPORT_SYMBOLS) && !defined(CJSON_EXPORT_SYMBOLS)
#define CJSON_EXPORT_SYMBOLS
#endif
#if defined(CJSON_HIDE_SYMBOLS)
#define CJSON_PUBLIC(type) type CJSON_STDCALL
#elif defined(CJSON_EXPORT_SYMBOLS)
#define CJSON_PUBLIC(type) __declspec(dllexport) type CJSON_STDCALL
#elif defined(CJSON_IMPORT_SYMBOLS)
#define CJSON_PUBLIC(type) __declspec(dllimport) type CJSON_STDCALL
#endif
#else /* !__WINDOWS__ */
#define CJSON_CDECL
#define CJSON_STDCALL
#if (defined(__GNUC__) || defined(__SUNPRO_CC) || defined (__SUNPRO_C)) && defined(CJSON_API_VISIBILITY)
#define CJSON_PUBLIC(type) __attribute__((visibility("default"))) type
#else
#define CJSON_PUBLIC(type) type
#endif
#endif
/* project version */
#define CJSON_VERSION_MAJOR 1
#define CJSON_VERSION_MINOR 7
#define CJSON_VERSION_PATCH 17
#include <stddef.h>
/* cJSON Types: */
#define cJSON_Invalid (0)
#define cJSON_False (1 << 0)
#define cJSON_True (1 << 1)
#define cJSON_NULL (1 << 2)
#define cJSON_Number (1 << 3)
#define cJSON_String (1 << 4)
#define cJSON_Array (1 << 5)
#define cJSON_Object (1 << 6)
#define cJSON_Raw (1 << 7) /* raw json */
#define cJSON_IsReference 256
#define cJSON_StringIsConst 512
/* The cJSON structure: */
typedef struct cJSON
{
/* next/prev allow you to walk array/object chains. Alternatively, use GetArraySize/GetArrayItem/GetObjectItem */
struct cJSON *next;
struct cJSON *prev;
/* An array or object item will have a child pointer pointing to a chain of the items in the array/object. */
struct cJSON *child;
/* The type of the item, as above. */
int type;
/* The item's string, if type==cJSON_String and type == cJSON_Raw */
char *valuestring;
/* writing to valueint is DEPRECATED, use cJSON_SetNumberValue instead */
int valueint;
/* The item's number, if type==cJSON_Number */
double valuedouble;
/* The item's name string, if this item is the child of, or is in the list of subitems of an object. */
char *string;
} cJSON;
typedef struct cJSON_Hooks
{
/* malloc/free are CDECL on Windows regardless of the default calling convention of the compiler, so ensure the hooks allow passing those functions directly. */
void *(CJSON_CDECL *malloc_fn)(size_t sz);
void (CJSON_CDECL *free_fn)(void *ptr);
} cJSON_Hooks;
typedef int cJSON_bool;
/* Limits how deeply nested arrays/objects can be before cJSON rejects to parse them.
* This is to prevent stack overflows. */
#ifndef CJSON_NESTING_LIMIT
#define CJSON_NESTING_LIMIT 1000
#endif
/* returns the version of cJSON as a string */
CJSON_PUBLIC(const char*) cJSON_Version(void);
/* Supply malloc, realloc and free functions to cJSON */
CJSON_PUBLIC(void) cJSON_InitHooks(cJSON_Hooks* hooks);
/* Memory Management: the caller is always responsible to free the results from all variants of cJSON_Parse (with cJSON_Delete) and cJSON_Print (with stdlib free, cJSON_Hooks.free_fn, or cJSON_free as appropriate). The exception is cJSON_PrintPreallocated, where the caller has full responsibility of the buffer. */
/* Supply a block of JSON, and this returns a cJSON object you can interrogate. */
CJSON_PUBLIC(cJSON *) cJSON_Parse(const char *value);
CJSON_PUBLIC(cJSON *) cJSON_ParseWithLength(const char *value, size_t buffer_length);
/* ParseWithOpts allows you to require (and check) that the JSON is null terminated, and to retrieve the pointer to the final byte parsed. */
/* If you supply a ptr in return_parse_end and parsing fails, then return_parse_end will contain a pointer to the error so will match cJSON_GetErrorPtr(). */
CJSON_PUBLIC(cJSON *) cJSON_ParseWithOpts(const char *value, const char **return_parse_end, cJSON_bool require_null_terminated);
CJSON_PUBLIC(cJSON *) cJSON_ParseWithLengthOpts(const char *value, size_t buffer_length, const char **return_parse_end, cJSON_bool require_null_terminated);
/* Render a cJSON entity to text for transfer/storage. */
CJSON_PUBLIC(char *) cJSON_Print(const cJSON *item);
/* Render a cJSON entity to text for transfer/storage without any formatting. */
CJSON_PUBLIC(char *) cJSON_PrintUnformatted(const cJSON *item);
/* Render a cJSON entity to text using a buffered strategy. prebuffer is a guess at the final size. guessing well reduces reallocation. fmt=0 gives unformatted, =1 gives formatted */
CJSON_PUBLIC(char *) cJSON_PrintBuffered(const cJSON *item, int prebuffer, cJSON_bool fmt);
/* Render a cJSON entity to text using a buffer already allocated in memory with given length. Returns 1 on success and 0 on failure. */
/* NOTE: cJSON is not always 100% accurate in estimating how much memory it will use, so to be safe allocate 5 bytes more than you actually need */
CJSON_PUBLIC(cJSON_bool) cJSON_PrintPreallocated(cJSON *item, char *buffer, const int length, const cJSON_bool format);
/* Delete a cJSON entity and all subentities. */
CJSON_PUBLIC(void) cJSON_Delete(cJSON *item);
/* Returns the number of items in an array (or object). */
CJSON_PUBLIC(int) cJSON_GetArraySize(const cJSON *array);
/* Retrieve item number "index" from array "array". Returns NULL if unsuccessful. */
CJSON_PUBLIC(cJSON *) cJSON_GetArrayItem(const cJSON *array, int index);
/* Get item "string" from object. Case insensitive. */
CJSON_PUBLIC(cJSON *) cJSON_GetObjectItem(const cJSON * const object, const char * const string);
CJSON_PUBLIC(cJSON *) cJSON_GetObjectItemCaseSensitive(const cJSON * const object, const char * const string);
CJSON_PUBLIC(cJSON_bool) cJSON_HasObjectItem(const cJSON *object, const char *string);
/* For analysing failed parses. This returns a pointer to the parse error. You'll probably need to look a few chars back to make sense of it. Defined when cJSON_Parse() returns 0. 0 when cJSON_Parse() succeeds. */
CJSON_PUBLIC(const char *) cJSON_GetErrorPtr(void);
/* Check item type and return its value */
CJSON_PUBLIC(char *) cJSON_GetStringValue(const cJSON * const item);
CJSON_PUBLIC(double) cJSON_GetNumberValue(const cJSON * const item);
/* These functions check the type of an item */
CJSON_PUBLIC(cJSON_bool) cJSON_IsInvalid(const cJSON * const item);
CJSON_PUBLIC(cJSON_bool) cJSON_IsFalse(const cJSON * const item);
CJSON_PUBLIC(cJSON_bool) cJSON_IsTrue(const cJSON * const item);
CJSON_PUBLIC(cJSON_bool) cJSON_IsBool(const cJSON * const item);
CJSON_PUBLIC(cJSON_bool) cJSON_IsNull(const cJSON * const item);
CJSON_PUBLIC(cJSON_bool) cJSON_IsNumber(const cJSON * const item);
CJSON_PUBLIC(cJSON_bool) cJSON_IsString(const cJSON * const item);
CJSON_PUBLIC(cJSON_bool) cJSON_IsArray(const cJSON * const item);
CJSON_PUBLIC(cJSON_bool) cJSON_IsObject(const cJSON * const item);
CJSON_PUBLIC(cJSON_bool) cJSON_IsRaw(const cJSON * const item);
/* These calls create a cJSON item of the appropriate type. */
CJSON_PUBLIC(cJSON *) cJSON_CreateNull(void);
CJSON_PUBLIC(cJSON *) cJSON_CreateTrue(void);
CJSON_PUBLIC(cJSON *) cJSON_CreateFalse(void);
CJSON_PUBLIC(cJSON *) cJSON_CreateBool(cJSON_bool boolean);
CJSON_PUBLIC(cJSON *) cJSON_CreateNumber(double num);
CJSON_PUBLIC(cJSON *) cJSON_CreateString(const char *string);
/* raw json */
CJSON_PUBLIC(cJSON *) cJSON_CreateRaw(const char *raw);
CJSON_PUBLIC(cJSON *) cJSON_CreateArray(void);
CJSON_PUBLIC(cJSON *) cJSON_CreateObject(void);
/* Create a string where valuestring references a string so
* it will not be freed by cJSON_Delete */
CJSON_PUBLIC(cJSON *) cJSON_CreateStringReference(const char *string);
/* Create an object/array that only references it's elements so
* they will not be freed by cJSON_Delete */
CJSON_PUBLIC(cJSON *) cJSON_CreateObjectReference(const cJSON *child);
CJSON_PUBLIC(cJSON *) cJSON_CreateArrayReference(const cJSON *child);
/* These utilities create an Array of count items.
* The parameter count cannot be greater than the number of elements in the number array, otherwise array access will be out of bounds.*/
CJSON_PUBLIC(cJSON *) cJSON_CreateIntArray(const int *numbers, int count);
CJSON_PUBLIC(cJSON *) cJSON_CreateFloatArray(const float *numbers, int count);
CJSON_PUBLIC(cJSON *) cJSON_CreateDoubleArray(const double *numbers, int count);
CJSON_PUBLIC(cJSON *) cJSON_CreateStringArray(const char *const *strings, int count);
/* Append item to the specified array/object. */
CJSON_PUBLIC(cJSON_bool) cJSON_AddItemToArray(cJSON *array, cJSON *item);
CJSON_PUBLIC(cJSON_bool) cJSON_AddItemToObject(cJSON *object, const char *string, cJSON *item);
/* Use this when string is definitely const (i.e. a literal, or as good as), and will definitely survive the cJSON object.
* WARNING: When this function was used, make sure to always check that (item->type & cJSON_StringIsConst) is zero before
* writing to `item->string` */
CJSON_PUBLIC(cJSON_bool) cJSON_AddItemToObjectCS(cJSON *object, const char *string, cJSON *item);
/* Append reference to item to the specified array/object. Use this when you want to add an existing cJSON to a new cJSON, but don't want to corrupt your existing cJSON. */
CJSON_PUBLIC(cJSON_bool) cJSON_AddItemReferenceToArray(cJSON *array, cJSON *item);
CJSON_PUBLIC(cJSON_bool) cJSON_AddItemReferenceToObject(cJSON *object, const char *string, cJSON *item);
/* Remove/Detach items from Arrays/Objects. */
CJSON_PUBLIC(cJSON *) cJSON_DetachItemViaPointer(cJSON *parent, cJSON * const item);
CJSON_PUBLIC(cJSON *) cJSON_DetachItemFromArray(cJSON *array, int which);
CJSON_PUBLIC(void) cJSON_DeleteItemFromArray(cJSON *array, int which);
CJSON_PUBLIC(cJSON *) cJSON_DetachItemFromObject(cJSON *object, const char *string);
CJSON_PUBLIC(cJSON *) cJSON_DetachItemFromObjectCaseSensitive(cJSON *object, const char *string);
CJSON_PUBLIC(void) cJSON_DeleteItemFromObject(cJSON *object, const char *string);
CJSON_PUBLIC(void) cJSON_DeleteItemFromObjectCaseSensitive(cJSON *object, const char *string);
/* Update array items. */
CJSON_PUBLIC(cJSON_bool) cJSON_InsertItemInArray(cJSON *array, int which, cJSON *newitem); /* Shifts pre-existing items to the right. */
CJSON_PUBLIC(cJSON_bool) cJSON_ReplaceItemViaPointer(cJSON * const parent, cJSON * const item, cJSON * replacement);
CJSON_PUBLIC(cJSON_bool) cJSON_ReplaceItemInArray(cJSON *array, int which, cJSON *newitem);
CJSON_PUBLIC(cJSON_bool) cJSON_ReplaceItemInObject(cJSON *object,const char *string,cJSON *newitem);
CJSON_PUBLIC(cJSON_bool) cJSON_ReplaceItemInObjectCaseSensitive(cJSON *object,const char *string,cJSON *newitem);
/* Duplicate a cJSON item */
CJSON_PUBLIC(cJSON *) cJSON_Duplicate(const cJSON *item, cJSON_bool recurse);
/* Duplicate will create a new, identical cJSON item to the one you pass, in new memory that will
* need to be released. With recurse!=0, it will duplicate any children connected to the item.
* The item->next and ->prev pointers are always zero on return from Duplicate. */
/* Recursively compare two cJSON items for equality. If either a or b is NULL or invalid, they will be considered unequal.
* case_sensitive determines if object keys are treated case sensitive (1) or case insensitive (0) */
CJSON_PUBLIC(cJSON_bool) cJSON_Compare(const cJSON * const a, const cJSON * const b, const cJSON_bool case_sensitive);
/* Minify a strings, remove blank characters(such as ' ', '\t', '\r', '\n') from strings.
* The input pointer json cannot point to a read-only address area, such as a string constant,
* but should point to a readable and writable address area. */
CJSON_PUBLIC(void) cJSON_Minify(char *json);
/* Helper functions for creating and adding items to an object at the same time.
* They return the added item or NULL on failure. */
CJSON_PUBLIC(cJSON*) cJSON_AddNullToObject(cJSON * const object, const char * const name);
CJSON_PUBLIC(cJSON*) cJSON_AddTrueToObject(cJSON * const object, const char * const name);
CJSON_PUBLIC(cJSON*) cJSON_AddFalseToObject(cJSON * const object, const char * const name);
CJSON_PUBLIC(cJSON*) cJSON_AddBoolToObject(cJSON * const object, const char * const name, const cJSON_bool boolean);
CJSON_PUBLIC(cJSON*) cJSON_AddNumberToObject(cJSON * const object, const char * const name, const double number);
CJSON_PUBLIC(cJSON*) cJSON_AddStringToObject(cJSON * const object, const char * const name, const char * const string);
CJSON_PUBLIC(cJSON*) cJSON_AddRawToObject(cJSON * const object, const char * const name, const char * const raw);
CJSON_PUBLIC(cJSON*) cJSON_AddObjectToObject(cJSON * const object, const char * const name);
CJSON_PUBLIC(cJSON*) cJSON_AddArrayToObject(cJSON * const object, const char * const name);
/* When assigning an integer value, it needs to be propagated to valuedouble too. */
#define cJSON_SetIntValue(object, number) ((object) ? (object)->valueint = (object)->valuedouble = (number) : (number))
/* helper for the cJSON_SetNumberValue macro */
CJSON_PUBLIC(double) cJSON_SetNumberHelper(cJSON *object, double number);
#define cJSON_SetNumberValue(object, number) ((object != NULL) ? cJSON_SetNumberHelper(object, (double)number) : (number))
/* Change the valuestring of a cJSON_String object, only takes effect when type of object is cJSON_String */
CJSON_PUBLIC(char*) cJSON_SetValuestring(cJSON *object, const char *valuestring);
/* If the object is not a boolean type this does nothing and returns cJSON_Invalid else it returns the new type*/
#define cJSON_SetBoolValue(object, boolValue) ( \
(object != NULL && ((object)->type & (cJSON_False|cJSON_True))) ? \
(object)->type=((object)->type &(~(cJSON_False|cJSON_True)))|((boolValue)?cJSON_True:cJSON_False) : \
cJSON_Invalid\
)
/* Macro for iterating over an array or object */
#define cJSON_ArrayForEach(element, array) for(element = (array != NULL) ? (array)->child : NULL; element != NULL; element = element->next)
/* malloc/free objects using the malloc/free functions that have been set with cJSON_InitHooks */
CJSON_PUBLIC(void *) cJSON_malloc(size_t size);
CJSON_PUBLIC(void) cJSON_free(void *object);
#ifdef __cplusplus
}
#endif
#endif
``` | /content/code_sandbox/src/include/cJSON.h | objective-c | 2016-06-25T22:29:10 | 2024-08-16T19:09:21 | 86Box | 86Box/86Box | 2,616 | 3,779 |
```objective-c
#ifndef __khrplatform_h_
#define __khrplatform_h_
/*
**
** Permission is hereby granted, free of charge, to any person obtaining a
** copy of this software and/or associated documentation files (the
** "Materials"), to deal in the Materials without restriction, including
** without limitation the rights to use, copy, modify, merge, publish,
** distribute, sublicense, and/or sell copies of the Materials, and to
** permit persons to whom the Materials are furnished to do so, subject to
** the following conditions:
**
** The above copyright notice and this permission notice shall be included
** in all copies or substantial portions of the Materials.
**
** THE MATERIALS ARE PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
** EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
** MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
** IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
** CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
** TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
** MATERIALS OR THE USE OR OTHER DEALINGS IN THE MATERIALS.
*/
/* Khronos platform-specific types and definitions.
*
* The master copy of khrplatform.h is maintained in the Khronos EGL
* Registry repository at path_to_url
* The last semantic modification to khrplatform.h was at commit ID:
* 67a3e0864c2d75ea5287b9f3d2eb74a745936692
*
* Adopters may modify this file to suit their platform. Adopters are
* encouraged to submit platform specific modifications to the Khronos
* group so that they can be included in future versions of this file.
* Please submit changes by filing pull requests or issues on
* the EGL Registry repository linked above.
*
*
* See the Implementer's Guidelines for information about where this file
* should be located on your system and for more details of its use:
* path_to_url
*
* This file should be included as
* #include <KHR/khrplatform.h>
* by Khronos client API header files that use its types and defines.
*
* The types in khrplatform.h should only be used to define API-specific types.
*
* Types defined in khrplatform.h:
* khronos_int8_t signed 8 bit
* khronos_uint8_t unsigned 8 bit
* khronos_int16_t signed 16 bit
* khronos_uint16_t unsigned 16 bit
* khronos_int32_t signed 32 bit
* khronos_uint32_t unsigned 32 bit
* khronos_int64_t signed 64 bit
* khronos_uint64_t unsigned 64 bit
* khronos_intptr_t signed same number of bits as a pointer
* khronos_uintptr_t unsigned same number of bits as a pointer
* khronos_ssize_t signed size
* khronos_usize_t unsigned size
* khronos_float_t signed 32 bit floating point
* khronos_time_ns_t unsigned 64 bit time in nanoseconds
* khronos_utime_nanoseconds_t unsigned time interval or absolute time in
* nanoseconds
* khronos_stime_nanoseconds_t signed time interval in nanoseconds
* khronos_boolean_enum_t enumerated boolean type. This should
* only be used as a base type when a client API's boolean type is
* an enum. Client APIs which use an integer or other type for
* booleans cannot use this as the base type for their boolean.
*
* Tokens defined in khrplatform.h:
*
* KHRONOS_FALSE, KHRONOS_TRUE Enumerated boolean false/true values.
*
* KHRONOS_SUPPORT_INT64 is 1 if 64 bit integers are supported; otherwise 0.
* KHRONOS_SUPPORT_FLOAT is 1 if floats are supported; otherwise 0.
*
* Calling convention macros defined in this file:
* KHRONOS_APICALL
* KHRONOS_APIENTRY
* KHRONOS_APIATTRIBUTES
*
* These may be used in function prototypes as:
*
* KHRONOS_APICALL void KHRONOS_APIENTRY funcname(
* int arg1,
* int arg2) KHRONOS_APIATTRIBUTES;
*/
#if defined(__SCITECH_SNAP__) && !defined(KHRONOS_STATIC)
# define KHRONOS_STATIC 1
#endif
/*your_sha256_hash---------
* Definition of KHRONOS_APICALL
*your_sha256_hash---------
* This precedes the return type of the function in the function prototype.
*/
#if defined(KHRONOS_STATIC)
/* If the preprocessor constant KHRONOS_STATIC is defined, make the
* header compatible with static linking. */
# define KHRONOS_APICALL
#elif defined(_WIN32)
# define KHRONOS_APICALL __declspec(dllimport)
#elif defined (__SYMBIAN32__)
# define KHRONOS_APICALL IMPORT_C
#elif defined(__ANDROID__)
# define KHRONOS_APICALL __attribute__((visibility("default")))
#else
# define KHRONOS_APICALL
#endif
/*your_sha256_hash---------
* Definition of KHRONOS_APIENTRY
*your_sha256_hash---------
* This follows the return type of the function and precedes the function
* name in the function prototype.
*/
#if defined(_WIN32) && !defined(_WIN32_WCE) && !defined(__SCITECH_SNAP__)
/* Win32 but not WinCE */
# define KHRONOS_APIENTRY __stdcall
#else
# define KHRONOS_APIENTRY
#endif
/*your_sha256_hash---------
* Definition of KHRONOS_APIATTRIBUTES
*your_sha256_hash---------
* This follows the closing parenthesis of the function prototype arguments.
*/
#if defined (__ARMCC_2__)
#define KHRONOS_APIATTRIBUTES __softfp
#else
#define KHRONOS_APIATTRIBUTES
#endif
/*your_sha256_hash---------
* basic type definitions
*your_sha256_hash-------*/
#if (defined(__STDC_VERSION__) && __STDC_VERSION__ >= 199901L) || defined(__GNUC__) || defined(__SCO__) || defined(__USLC__)
/*
* Using <stdint.h>
*/
#include <stdint.h>
typedef int32_t khronos_int32_t;
typedef uint32_t khronos_uint32_t;
typedef int64_t khronos_int64_t;
typedef uint64_t khronos_uint64_t;
#define KHRONOS_SUPPORT_INT64 1
#define KHRONOS_SUPPORT_FLOAT 1
/*
* To support platform where unsigned long cannot be used interchangeably with
* inptr_t (e.g. CHERI-extended ISAs), we can use the stdint.h intptr_t.
* Ideally, we could just use (u)intptr_t everywhere, but this could result in
* ABI breakage if khronos_uintptr_t is changed from unsigned long to
* unsigned long long or similar (this results in different C++ name mangling).
* To avoid changes for existing platforms, we restrict usage of intptr_t to
* platforms where the size of a pointer is larger than the size of long.
*/
#if defined(__SIZEOF_LONG__) && defined(__SIZEOF_POINTER__)
#if __SIZEOF_POINTER__ > __SIZEOF_LONG__
#define KHRONOS_USE_INTPTR_T
#endif
#endif
#elif defined(__VMS ) || defined(__sgi)
/*
* Using <inttypes.h>
*/
#include <inttypes.h>
typedef int32_t khronos_int32_t;
typedef uint32_t khronos_uint32_t;
typedef int64_t khronos_int64_t;
typedef uint64_t khronos_uint64_t;
#define KHRONOS_SUPPORT_INT64 1
#define KHRONOS_SUPPORT_FLOAT 1
#elif defined(_WIN32) && !defined(__SCITECH_SNAP__)
/*
* Win32
*/
typedef __int32 khronos_int32_t;
typedef unsigned __int32 khronos_uint32_t;
typedef __int64 khronos_int64_t;
typedef unsigned __int64 khronos_uint64_t;
#define KHRONOS_SUPPORT_INT64 1
#define KHRONOS_SUPPORT_FLOAT 1
#elif defined(__sun__) || defined(__digital__)
/*
* Sun or Digital
*/
typedef int khronos_int32_t;
typedef unsigned int khronos_uint32_t;
#if defined(__arch64__) || defined(_LP64)
typedef long int khronos_int64_t;
typedef unsigned long int khronos_uint64_t;
#else
typedef long long int khronos_int64_t;
typedef unsigned long long int khronos_uint64_t;
#endif /* __arch64__ */
#define KHRONOS_SUPPORT_INT64 1
#define KHRONOS_SUPPORT_FLOAT 1
#elif 0
/*
* Hypothetical platform with no float or int64 support
*/
typedef int khronos_int32_t;
typedef unsigned int khronos_uint32_t;
#define KHRONOS_SUPPORT_INT64 0
#define KHRONOS_SUPPORT_FLOAT 0
#else
/*
* Generic fallback
*/
#include <stdint.h>
typedef int32_t khronos_int32_t;
typedef uint32_t khronos_uint32_t;
typedef int64_t khronos_int64_t;
typedef uint64_t khronos_uint64_t;
#define KHRONOS_SUPPORT_INT64 1
#define KHRONOS_SUPPORT_FLOAT 1
#endif
/*
* Types that are (so far) the same on all platforms
*/
typedef signed char khronos_int8_t;
typedef unsigned char khronos_uint8_t;
typedef signed short int khronos_int16_t;
typedef unsigned short int khronos_uint16_t;
/*
* Types that differ between LLP64 and LP64 architectures - in LLP64,
* pointers are 64 bits, but 'long' is still 32 bits. Win64 appears
* to be the only LLP64 architecture in current use.
*/
#ifdef KHRONOS_USE_INTPTR_T
typedef intptr_t khronos_intptr_t;
typedef uintptr_t khronos_uintptr_t;
#elif defined(_WIN64)
typedef signed long long int khronos_intptr_t;
typedef unsigned long long int khronos_uintptr_t;
#else
typedef signed long int khronos_intptr_t;
typedef unsigned long int khronos_uintptr_t;
#endif
#if defined(_WIN64)
typedef signed long long int khronos_ssize_t;
typedef unsigned long long int khronos_usize_t;
#else
typedef signed long int khronos_ssize_t;
typedef unsigned long int khronos_usize_t;
#endif
#if KHRONOS_SUPPORT_FLOAT
/*
* Float type
*/
typedef float khronos_float_t;
#endif
#if KHRONOS_SUPPORT_INT64
/* Time types
*
* These types can be used to represent a time interval in nanoseconds or
* an absolute Unadjusted System Time. Unadjusted System Time is the number
* of nanoseconds since some arbitrary system event (e.g. since the last
* time the system booted). The Unadjusted System Time is an unsigned
* 64 bit value that wraps back to 0 every 584 years. Time intervals
* may be either signed or unsigned.
*/
typedef khronos_uint64_t khronos_utime_nanoseconds_t;
typedef khronos_int64_t khronos_stime_nanoseconds_t;
#endif
/*
* Dummy value used to pad enum types to 32 bits.
*/
#ifndef KHRONOS_MAX_ENUM
#define KHRONOS_MAX_ENUM 0x7FFFFFFF
#endif
/*
* Enumerated boolean type
*
* Values other than zero should be considered to be true. Therefore
* comparisons should not be made against KHRONOS_TRUE.
*/
typedef enum {
KHRONOS_FALSE = 0,
KHRONOS_TRUE = 1,
KHRONOS_BOOLEAN_ENUM_FORCE_SIZE = KHRONOS_MAX_ENUM
} khronos_boolean_enum_t;
#endif /* __khrplatform_h_ */
``` | /content/code_sandbox/src/include/KHR/khrplatform.h | objective-c | 2016-06-25T22:29:10 | 2024-08-16T19:09:21 | 86Box | 86Box/86Box | 2,616 | 2,706 |
```objective-c
*
* This program is free software: you can redistribute it and/or modify
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
*
* along with this program. If not, see <path_to_url
*/
#ifndef MT32EMU_CONFIG_H
#define MT32EMU_CONFIG_H
#define MT32EMU_VERSION "2.7.0"
#define MT32EMU_VERSION_MAJOR 2
#define MT32EMU_VERSION_MINOR 7
#define MT32EMU_VERSION_PATCH 0
/* Library Exports Configuration
*
* This reflects the API types actually provided by the library build.
* 0: The full-featured C++ API is only available in this build. The client application may ONLY use MT32EMU_API_TYPE 0.
* 1: The C-compatible API is only available. The library is built as a shared object, only C functions are exported,
* and thus the client application may NOT use MT32EMU_API_TYPE 0.
* 2: The C-compatible API is only available. The library is built as a shared object, only the factory function
* is exported, and thus the client application may ONLY use MT32EMU_API_TYPE 2.
* 3: All the available API types are provided by the library build.
*/
#define MT32EMU_EXPORTS_TYPE 3
#define MT32EMU_API_TYPE 0
#define MT32EMU_WITH_LIBSOXR_RESAMPLER 0
#define MT32EMU_WITH_LIBSAMPLERATE_RESAMPLER 0
#define MT32EMU_WITH_INTERNAL_RESAMPLER 1
#endif /* #ifndef MT32EMU_CONFIG_H */
``` | /content/code_sandbox/src/include/mt32emu/config.h | objective-c | 2016-06-25T22:29:10 | 2024-08-16T19:09:21 | 86Box | 86Box/86Box | 2,616 | 380 |
```objective-c
/*
* This file is distributed as a part of the Discord Game SDK.
* Downloading, accessing, or using the API or SDK is bound by
* the Discord Developer Terms of Service:
* path_to_url
*/
#ifndef _DISCORD_GAME_SDK_H_
#define _DISCORD_GAME_SDK_H_
#ifdef _WIN32
#include <windows.h>
#include <dxgi.h>
#endif
#ifdef _WIN32
# ifdef _WIN64
# define DISCORD_API
# else
# define DISCORD_API __stdcall
# endif
#else
# define DISCORD_API
#endif
#define DISCORD_CALLBACK DISCORD_API
#ifdef __cplusplus
extern "C" {
#endif
#include <stdint.h>
#include <string.h>
#ifndef __cplusplus
#include <stdbool.h>
#endif
#define DISCORD_VERSION 3
#define DISCORD_APPLICATION_MANAGER_VERSION 1
#define DISCORD_USER_MANAGER_VERSION 1
#define DISCORD_IMAGE_MANAGER_VERSION 1
#define DISCORD_ACTIVITY_MANAGER_VERSION 1
#define DISCORD_RELATIONSHIP_MANAGER_VERSION 1
#define DISCORD_LOBBY_MANAGER_VERSION 1
#define DISCORD_NETWORK_MANAGER_VERSION 1
#define DISCORD_OVERLAY_MANAGER_VERSION 2
#define DISCORD_STORAGE_MANAGER_VERSION 1
#define DISCORD_STORE_MANAGER_VERSION 1
#define DISCORD_VOICE_MANAGER_VERSION 1
#define DISCORD_ACHIEVEMENT_MANAGER_VERSION 1
enum EDiscordResult {
DiscordResult_Ok = 0,
DiscordResult_ServiceUnavailable = 1,
DiscordResult_InvalidVersion = 2,
DiscordResult_LockFailed = 3,
DiscordResult_InternalError = 4,
DiscordResult_InvalidPayload = 5,
DiscordResult_InvalidCommand = 6,
DiscordResult_InvalidPermissions = 7,
DiscordResult_NotFetched = 8,
DiscordResult_NotFound = 9,
DiscordResult_Conflict = 10,
DiscordResult_InvalidSecret = 11,
DiscordResult_InvalidJoinSecret = 12,
DiscordResult_NoEligibleActivity = 13,
DiscordResult_InvalidInvite = 14,
DiscordResult_NotAuthenticated = 15,
DiscordResult_InvalidAccessToken = 16,
DiscordResult_ApplicationMismatch = 17,
DiscordResult_InvalidDataUrl = 18,
DiscordResult_InvalidBase64 = 19,
DiscordResult_NotFiltered = 20,
DiscordResult_LobbyFull = 21,
DiscordResult_InvalidLobbySecret = 22,
DiscordResult_InvalidFilename = 23,
DiscordResult_InvalidFileSize = 24,
DiscordResult_InvalidEntitlement = 25,
DiscordResult_NotInstalled = 26,
DiscordResult_NotRunning = 27,
DiscordResult_InsufficientBuffer = 28,
DiscordResult_PurchaseCanceled = 29,
DiscordResult_InvalidGuild = 30,
DiscordResult_InvalidEvent = 31,
DiscordResult_InvalidChannel = 32,
DiscordResult_InvalidOrigin = 33,
DiscordResult_RateLimited = 34,
DiscordResult_OAuth2Error = 35,
DiscordResult_SelectChannelTimeout = 36,
DiscordResult_GetGuildTimeout = 37,
DiscordResult_SelectVoiceForceRequired = 38,
DiscordResult_CaptureShortcutAlreadyListening = 39,
DiscordResult_UnauthorizedForAchievement = 40,
DiscordResult_InvalidGiftCode = 41,
DiscordResult_PurchaseError = 42,
DiscordResult_TransactionAborted = 43,
DiscordResult_DrawingInitFailed = 44,
};
enum EDiscordCreateFlags {
DiscordCreateFlags_Default = 0,
DiscordCreateFlags_NoRequireDiscord = 1,
};
enum EDiscordLogLevel {
DiscordLogLevel_Error = 1,
DiscordLogLevel_Warn,
DiscordLogLevel_Info,
DiscordLogLevel_Debug,
};
enum EDiscordUserFlag {
DiscordUserFlag_Partner = 2,
DiscordUserFlag_HypeSquadEvents = 4,
DiscordUserFlag_HypeSquadHouse1 = 64,
DiscordUserFlag_HypeSquadHouse2 = 128,
DiscordUserFlag_HypeSquadHouse3 = 256,
};
enum EDiscordPremiumType {
DiscordPremiumType_None = 0,
DiscordPremiumType_Tier1 = 1,
DiscordPremiumType_Tier2 = 2,
};
enum EDiscordImageType {
DiscordImageType_User,
};
enum EDiscordActivityPartyPrivacy {
DiscordActivityPartyPrivacy_Private = 0,
DiscordActivityPartyPrivacy_Public = 1,
};
enum EDiscordActivityType {
DiscordActivityType_Playing,
DiscordActivityType_Streaming,
DiscordActivityType_Listening,
DiscordActivityType_Watching,
};
enum EDiscordActivityActionType {
DiscordActivityActionType_Join = 1,
DiscordActivityActionType_Spectate,
};
enum EDiscordActivitySupportedPlatformFlags {
DiscordActivitySupportedPlatformFlags_Desktop = 1,
DiscordActivitySupportedPlatformFlags_Android = 2,
DiscordActivitySupportedPlatformFlags_iOS = 4,
};
enum EDiscordActivityJoinRequestReply {
DiscordActivityJoinRequestReply_No,
DiscordActivityJoinRequestReply_Yes,
DiscordActivityJoinRequestReply_Ignore,
};
enum EDiscordStatus {
DiscordStatus_Offline = 0,
DiscordStatus_Online = 1,
DiscordStatus_Idle = 2,
DiscordStatus_DoNotDisturb = 3,
};
enum EDiscordRelationshipType {
DiscordRelationshipType_None,
DiscordRelationshipType_Friend,
DiscordRelationshipType_Blocked,
DiscordRelationshipType_PendingIncoming,
DiscordRelationshipType_PendingOutgoing,
DiscordRelationshipType_Implicit,
};
enum EDiscordLobbyType {
DiscordLobbyType_Private = 1,
DiscordLobbyType_Public,
};
enum EDiscordLobbySearchComparison {
DiscordLobbySearchComparison_LessThanOrEqual = -2,
DiscordLobbySearchComparison_LessThan,
DiscordLobbySearchComparison_Equal,
DiscordLobbySearchComparison_GreaterThan,
DiscordLobbySearchComparison_GreaterThanOrEqual,
DiscordLobbySearchComparison_NotEqual,
};
enum EDiscordLobbySearchCast {
DiscordLobbySearchCast_String = 1,
DiscordLobbySearchCast_Number,
};
enum EDiscordLobbySearchDistance {
DiscordLobbySearchDistance_Local,
DiscordLobbySearchDistance_Default,
DiscordLobbySearchDistance_Extended,
DiscordLobbySearchDistance_Global,
};
enum EDiscordKeyVariant {
DiscordKeyVariant_Normal,
DiscordKeyVariant_Right,
DiscordKeyVariant_Left,
};
enum EDiscordMouseButton {
DiscordMouseButton_Left,
DiscordMouseButton_Middle,
DiscordMouseButton_Right,
};
enum EDiscordEntitlementType {
DiscordEntitlementType_Purchase = 1,
DiscordEntitlementType_PremiumSubscription,
DiscordEntitlementType_DeveloperGift,
DiscordEntitlementType_TestModePurchase,
DiscordEntitlementType_FreePurchase,
DiscordEntitlementType_UserGift,
DiscordEntitlementType_PremiumPurchase,
};
enum EDiscordSkuType {
DiscordSkuType_Application = 1,
DiscordSkuType_DLC,
DiscordSkuType_Consumable,
DiscordSkuType_Bundle,
};
enum EDiscordInputModeType {
DiscordInputModeType_VoiceActivity = 0,
DiscordInputModeType_PushToTalk,
};
typedef int64_t DiscordClientId;
typedef int32_t DiscordVersion;
typedef int64_t DiscordSnowflake;
typedef int64_t DiscordTimestamp;
typedef DiscordSnowflake DiscordUserId;
typedef char DiscordLocale[128];
typedef char DiscordBranch[4096];
typedef DiscordSnowflake DiscordLobbyId;
typedef char DiscordLobbySecret[128];
typedef char DiscordMetadataKey[256];
typedef char DiscordMetadataValue[4096];
typedef uint64_t DiscordNetworkPeerId;
typedef uint8_t DiscordNetworkChannelId;
#ifdef __APPLE__
typedef void IDXGISwapChain;
#endif
#ifdef __linux__
typedef void IDXGISwapChain;
#endif
#ifdef __APPLE__
typedef void MSG;
#endif
#ifdef __linux__
typedef void MSG;
#endif
typedef char DiscordPath[4096];
typedef char DiscordDateTime[64];
struct DiscordUser {
DiscordUserId id;
char username[256];
char discriminator[8];
char avatar[128];
bool bot;
};
struct DiscordOAuth2Token {
char access_token[128];
char scopes[1024];
DiscordTimestamp expires;
};
struct DiscordImageHandle {
enum EDiscordImageType type;
int64_t id;
uint32_t size;
};
struct DiscordImageDimensions {
uint32_t width;
uint32_t height;
};
struct DiscordActivityTimestamps {
DiscordTimestamp start;
DiscordTimestamp end;
};
struct DiscordActivityAssets {
char large_image[128];
char large_text[128];
char small_image[128];
char small_text[128];
};
struct DiscordPartySize {
int32_t current_size;
int32_t max_size;
};
struct DiscordActivityParty {
char id[128];
struct DiscordPartySize size;
enum EDiscordActivityPartyPrivacy privacy;
};
struct DiscordActivitySecrets {
char match[128];
char join[128];
char spectate[128];
};
struct DiscordActivity {
enum EDiscordActivityType type;
int64_t application_id;
char name[128];
char state[128];
char details[128];
struct DiscordActivityTimestamps timestamps;
struct DiscordActivityAssets assets;
struct DiscordActivityParty party;
struct DiscordActivitySecrets secrets;
bool instance;
uint32_t supported_platforms;
};
struct DiscordPresence {
enum EDiscordStatus status;
struct DiscordActivity activity;
};
struct DiscordRelationship {
enum EDiscordRelationshipType type;
struct DiscordUser user;
struct DiscordPresence presence;
};
struct DiscordLobby {
DiscordLobbyId id;
enum EDiscordLobbyType type;
DiscordUserId owner_id;
DiscordLobbySecret secret;
uint32_t capacity;
bool locked;
};
struct DiscordImeUnderline {
int32_t from;
int32_t to;
uint32_t color;
uint32_t background_color;
bool thick;
};
struct DiscordRect {
int32_t left;
int32_t top;
int32_t right;
int32_t bottom;
};
struct DiscordFileStat {
char filename[260];
uint64_t size;
uint64_t last_modified;
};
struct DiscordEntitlement {
DiscordSnowflake id;
enum EDiscordEntitlementType type;
DiscordSnowflake sku_id;
};
struct DiscordSkuPrice {
uint32_t amount;
char currency[16];
};
struct DiscordSku {
DiscordSnowflake id;
enum EDiscordSkuType type;
char name[256];
struct DiscordSkuPrice price;
};
struct DiscordInputMode {
enum EDiscordInputModeType type;
char shortcut[256];
};
struct DiscordUserAchievement {
DiscordSnowflake user_id;
DiscordSnowflake achievement_id;
uint8_t percent_complete;
DiscordDateTime unlocked_at;
};
struct IDiscordLobbyTransaction {
enum EDiscordResult (DISCORD_API *set_type)(struct IDiscordLobbyTransaction* lobby_transaction, enum EDiscordLobbyType type);
enum EDiscordResult (DISCORD_API *set_owner)(struct IDiscordLobbyTransaction* lobby_transaction, DiscordUserId owner_id);
enum EDiscordResult (DISCORD_API *set_capacity)(struct IDiscordLobbyTransaction* lobby_transaction, uint32_t capacity);
enum EDiscordResult (DISCORD_API *set_metadata)(struct IDiscordLobbyTransaction* lobby_transaction, DiscordMetadataKey key, DiscordMetadataValue value);
enum EDiscordResult (DISCORD_API *delete_metadata)(struct IDiscordLobbyTransaction* lobby_transaction, DiscordMetadataKey key);
enum EDiscordResult (DISCORD_API *set_locked)(struct IDiscordLobbyTransaction* lobby_transaction, bool locked);
};
struct IDiscordLobbyMemberTransaction {
enum EDiscordResult (DISCORD_API *set_metadata)(struct IDiscordLobbyMemberTransaction* lobby_member_transaction, DiscordMetadataKey key, DiscordMetadataValue value);
enum EDiscordResult (DISCORD_API *delete_metadata)(struct IDiscordLobbyMemberTransaction* lobby_member_transaction, DiscordMetadataKey key);
};
struct IDiscordLobbySearchQuery {
enum EDiscordResult (DISCORD_API *filter)(struct IDiscordLobbySearchQuery* lobby_search_query, DiscordMetadataKey key, enum EDiscordLobbySearchComparison comparison, enum EDiscordLobbySearchCast cast, DiscordMetadataValue value);
enum EDiscordResult (DISCORD_API *sort)(struct IDiscordLobbySearchQuery* lobby_search_query, DiscordMetadataKey key, enum EDiscordLobbySearchCast cast, DiscordMetadataValue value);
enum EDiscordResult (DISCORD_API *limit)(struct IDiscordLobbySearchQuery* lobby_search_query, uint32_t limit);
enum EDiscordResult (DISCORD_API *distance)(struct IDiscordLobbySearchQuery* lobby_search_query, enum EDiscordLobbySearchDistance distance);
};
typedef void* IDiscordApplicationEvents;
struct IDiscordApplicationManager {
void (DISCORD_API *validate_or_exit)(struct IDiscordApplicationManager* manager, void* callback_data, void (DISCORD_API *callback)(void* callback_data, enum EDiscordResult result));
void (DISCORD_API *get_current_locale)(struct IDiscordApplicationManager* manager, DiscordLocale* locale);
void (DISCORD_API *get_current_branch)(struct IDiscordApplicationManager* manager, DiscordBranch* branch);
void (DISCORD_API *get_oauth2_token)(struct IDiscordApplicationManager* manager, void* callback_data, void (DISCORD_API *callback)(void* callback_data, enum EDiscordResult result, struct DiscordOAuth2Token* oauth2_token));
void (DISCORD_API *get_ticket)(struct IDiscordApplicationManager* manager, void* callback_data, void (DISCORD_API *callback)(void* callback_data, enum EDiscordResult result, const char* data));
};
struct IDiscordUserEvents {
void (DISCORD_API *on_current_user_update)(void* event_data);
};
struct IDiscordUserManager {
enum EDiscordResult (DISCORD_API *get_current_user)(struct IDiscordUserManager* manager, struct DiscordUser* current_user);
void (DISCORD_API *get_user)(struct IDiscordUserManager* manager, DiscordUserId user_id, void* callback_data, void (DISCORD_API *callback)(void* callback_data, enum EDiscordResult result, struct DiscordUser* user));
enum EDiscordResult (DISCORD_API *get_current_user_premium_type)(struct IDiscordUserManager* manager, enum EDiscordPremiumType* premium_type);
enum EDiscordResult (DISCORD_API *current_user_has_flag)(struct IDiscordUserManager* manager, enum EDiscordUserFlag flag, bool* has_flag);
};
typedef void* IDiscordImageEvents;
struct IDiscordImageManager {
void (DISCORD_API *fetch)(struct IDiscordImageManager* manager, struct DiscordImageHandle handle, bool refresh, void* callback_data, void (DISCORD_API *callback)(void* callback_data, enum EDiscordResult result, struct DiscordImageHandle handle_result));
enum EDiscordResult (DISCORD_API *get_dimensions)(struct IDiscordImageManager* manager, struct DiscordImageHandle handle, struct DiscordImageDimensions* dimensions);
enum EDiscordResult (DISCORD_API *get_data)(struct IDiscordImageManager* manager, struct DiscordImageHandle handle, uint8_t* data, uint32_t data_length);
};
struct IDiscordActivityEvents {
void (DISCORD_API *on_activity_join)(void* event_data, const char* secret);
void (DISCORD_API *on_activity_spectate)(void* event_data, const char* secret);
void (DISCORD_API *on_activity_join_request)(void* event_data, struct DiscordUser* user);
void (DISCORD_API *on_activity_invite)(void* event_data, enum EDiscordActivityActionType type, struct DiscordUser* user, struct DiscordActivity* activity);
};
struct IDiscordActivityManager {
enum EDiscordResult (DISCORD_API *register_command)(struct IDiscordActivityManager* manager, const char* command);
enum EDiscordResult (DISCORD_API *register_steam)(struct IDiscordActivityManager* manager, uint32_t steam_id);
void (DISCORD_API *update_activity)(struct IDiscordActivityManager* manager, struct DiscordActivity* activity, void* callback_data, void (DISCORD_API *callback)(void* callback_data, enum EDiscordResult result));
void (DISCORD_API *clear_activity)(struct IDiscordActivityManager* manager, void* callback_data, void (DISCORD_API *callback)(void* callback_data, enum EDiscordResult result));
void (DISCORD_API *send_request_reply)(struct IDiscordActivityManager* manager, DiscordUserId user_id, enum EDiscordActivityJoinRequestReply reply, void* callback_data, void (DISCORD_API *callback)(void* callback_data, enum EDiscordResult result));
void (DISCORD_API *send_invite)(struct IDiscordActivityManager* manager, DiscordUserId user_id, enum EDiscordActivityActionType type, const char* content, void* callback_data, void (DISCORD_API *callback)(void* callback_data, enum EDiscordResult result));
void (DISCORD_API *accept_invite)(struct IDiscordActivityManager* manager, DiscordUserId user_id, void* callback_data, void (DISCORD_API *callback)(void* callback_data, enum EDiscordResult result));
};
struct IDiscordRelationshipEvents {
void (DISCORD_API *on_refresh)(void* event_data);
void (DISCORD_API *on_relationship_update)(void* event_data, struct DiscordRelationship* relationship);
};
struct IDiscordRelationshipManager {
void (DISCORD_API *filter)(struct IDiscordRelationshipManager* manager, void* filter_data, bool (DISCORD_API *filter)(void* filter_data, struct DiscordRelationship* relationship));
enum EDiscordResult (DISCORD_API *count)(struct IDiscordRelationshipManager* manager, int32_t* count);
enum EDiscordResult (DISCORD_API *get)(struct IDiscordRelationshipManager* manager, DiscordUserId user_id, struct DiscordRelationship* relationship);
enum EDiscordResult (DISCORD_API *get_at)(struct IDiscordRelationshipManager* manager, uint32_t index, struct DiscordRelationship* relationship);
};
struct IDiscordLobbyEvents {
void (DISCORD_API *on_lobby_update)(void* event_data, int64_t lobby_id);
void (DISCORD_API *on_lobby_delete)(void* event_data, int64_t lobby_id, uint32_t reason);
void (DISCORD_API *on_member_connect)(void* event_data, int64_t lobby_id, int64_t user_id);
void (DISCORD_API *on_member_update)(void* event_data, int64_t lobby_id, int64_t user_id);
void (DISCORD_API *on_member_disconnect)(void* event_data, int64_t lobby_id, int64_t user_id);
void (DISCORD_API *on_lobby_message)(void* event_data, int64_t lobby_id, int64_t user_id, uint8_t* data, uint32_t data_length);
void (DISCORD_API *on_speaking)(void* event_data, int64_t lobby_id, int64_t user_id, bool speaking);
void (DISCORD_API *on_network_message)(void* event_data, int64_t lobby_id, int64_t user_id, uint8_t channel_id, uint8_t* data, uint32_t data_length);
};
struct IDiscordLobbyManager {
enum EDiscordResult (DISCORD_API *get_lobby_create_transaction)(struct IDiscordLobbyManager* manager, struct IDiscordLobbyTransaction** transaction);
enum EDiscordResult (DISCORD_API *get_lobby_update_transaction)(struct IDiscordLobbyManager* manager, DiscordLobbyId lobby_id, struct IDiscordLobbyTransaction** transaction);
enum EDiscordResult (DISCORD_API *get_member_update_transaction)(struct IDiscordLobbyManager* manager, DiscordLobbyId lobby_id, DiscordUserId user_id, struct IDiscordLobbyMemberTransaction** transaction);
void (DISCORD_API *create_lobby)(struct IDiscordLobbyManager* manager, struct IDiscordLobbyTransaction* transaction, void* callback_data, void (DISCORD_API *callback)(void* callback_data, enum EDiscordResult result, struct DiscordLobby* lobby));
void (DISCORD_API *update_lobby)(struct IDiscordLobbyManager* manager, DiscordLobbyId lobby_id, struct IDiscordLobbyTransaction* transaction, void* callback_data, void (DISCORD_API *callback)(void* callback_data, enum EDiscordResult result));
void (DISCORD_API *delete_lobby)(struct IDiscordLobbyManager* manager, DiscordLobbyId lobby_id, void* callback_data, void (DISCORD_API *callback)(void* callback_data, enum EDiscordResult result));
void (DISCORD_API *connect_lobby)(struct IDiscordLobbyManager* manager, DiscordLobbyId lobby_id, DiscordLobbySecret secret, void* callback_data, void (DISCORD_API *callback)(void* callback_data, enum EDiscordResult result, struct DiscordLobby* lobby));
void (DISCORD_API *connect_lobby_with_activity_secret)(struct IDiscordLobbyManager* manager, DiscordLobbySecret activity_secret, void* callback_data, void (DISCORD_API *callback)(void* callback_data, enum EDiscordResult result, struct DiscordLobby* lobby));
void (DISCORD_API *disconnect_lobby)(struct IDiscordLobbyManager* manager, DiscordLobbyId lobby_id, void* callback_data, void (DISCORD_API *callback)(void* callback_data, enum EDiscordResult result));
enum EDiscordResult (DISCORD_API *get_lobby)(struct IDiscordLobbyManager* manager, DiscordLobbyId lobby_id, struct DiscordLobby* lobby);
enum EDiscordResult (DISCORD_API *get_lobby_activity_secret)(struct IDiscordLobbyManager* manager, DiscordLobbyId lobby_id, DiscordLobbySecret* secret);
enum EDiscordResult (DISCORD_API *get_lobby_metadata_value)(struct IDiscordLobbyManager* manager, DiscordLobbyId lobby_id, DiscordMetadataKey key, DiscordMetadataValue* value);
enum EDiscordResult (DISCORD_API *get_lobby_metadata_key)(struct IDiscordLobbyManager* manager, DiscordLobbyId lobby_id, int32_t index, DiscordMetadataKey* key);
enum EDiscordResult (DISCORD_API *lobby_metadata_count)(struct IDiscordLobbyManager* manager, DiscordLobbyId lobby_id, int32_t* count);
enum EDiscordResult (DISCORD_API *member_count)(struct IDiscordLobbyManager* manager, DiscordLobbyId lobby_id, int32_t* count);
enum EDiscordResult (DISCORD_API *get_member_user_id)(struct IDiscordLobbyManager* manager, DiscordLobbyId lobby_id, int32_t index, DiscordUserId* user_id);
enum EDiscordResult (DISCORD_API *get_member_user)(struct IDiscordLobbyManager* manager, DiscordLobbyId lobby_id, DiscordUserId user_id, struct DiscordUser* user);
enum EDiscordResult (DISCORD_API *get_member_metadata_value)(struct IDiscordLobbyManager* manager, DiscordLobbyId lobby_id, DiscordUserId user_id, DiscordMetadataKey key, DiscordMetadataValue* value);
enum EDiscordResult (DISCORD_API *get_member_metadata_key)(struct IDiscordLobbyManager* manager, DiscordLobbyId lobby_id, DiscordUserId user_id, int32_t index, DiscordMetadataKey* key);
enum EDiscordResult (DISCORD_API *member_metadata_count)(struct IDiscordLobbyManager* manager, DiscordLobbyId lobby_id, DiscordUserId user_id, int32_t* count);
void (DISCORD_API *update_member)(struct IDiscordLobbyManager* manager, DiscordLobbyId lobby_id, DiscordUserId user_id, struct IDiscordLobbyMemberTransaction* transaction, void* callback_data, void (DISCORD_API *callback)(void* callback_data, enum EDiscordResult result));
void (DISCORD_API *send_lobby_message)(struct IDiscordLobbyManager* manager, DiscordLobbyId lobby_id, uint8_t* data, uint32_t data_length, void* callback_data, void (DISCORD_API *callback)(void* callback_data, enum EDiscordResult result));
enum EDiscordResult (DISCORD_API *get_search_query)(struct IDiscordLobbyManager* manager, struct IDiscordLobbySearchQuery** query);
void (DISCORD_API *search)(struct IDiscordLobbyManager* manager, struct IDiscordLobbySearchQuery* query, void* callback_data, void (DISCORD_API *callback)(void* callback_data, enum EDiscordResult result));
void (DISCORD_API *lobby_count)(struct IDiscordLobbyManager* manager, int32_t* count);
enum EDiscordResult (DISCORD_API *get_lobby_id)(struct IDiscordLobbyManager* manager, int32_t index, DiscordLobbyId* lobby_id);
void (DISCORD_API *connect_voice)(struct IDiscordLobbyManager* manager, DiscordLobbyId lobby_id, void* callback_data, void (DISCORD_API *callback)(void* callback_data, enum EDiscordResult result));
void (DISCORD_API *disconnect_voice)(struct IDiscordLobbyManager* manager, DiscordLobbyId lobby_id, void* callback_data, void (DISCORD_API *callback)(void* callback_data, enum EDiscordResult result));
enum EDiscordResult (DISCORD_API *connect_network)(struct IDiscordLobbyManager* manager, DiscordLobbyId lobby_id);
enum EDiscordResult (DISCORD_API *disconnect_network)(struct IDiscordLobbyManager* manager, DiscordLobbyId lobby_id);
enum EDiscordResult (DISCORD_API *flush_network)(struct IDiscordLobbyManager* manager);
enum EDiscordResult (DISCORD_API *open_network_channel)(struct IDiscordLobbyManager* manager, DiscordLobbyId lobby_id, uint8_t channel_id, bool reliable);
enum EDiscordResult (DISCORD_API *send_network_message)(struct IDiscordLobbyManager* manager, DiscordLobbyId lobby_id, DiscordUserId user_id, uint8_t channel_id, uint8_t* data, uint32_t data_length);
};
struct IDiscordNetworkEvents {
void (DISCORD_API *on_message)(void* event_data, DiscordNetworkPeerId peer_id, DiscordNetworkChannelId channel_id, uint8_t* data, uint32_t data_length);
void (DISCORD_API *on_route_update)(void* event_data, const char* route_data);
};
struct IDiscordNetworkManager {
/**
* Get the local peer ID for this process.
*/
void (DISCORD_API *get_peer_id)(struct IDiscordNetworkManager* manager, DiscordNetworkPeerId* peer_id);
/**
* Send pending network messages.
*/
enum EDiscordResult (DISCORD_API *flush)(struct IDiscordNetworkManager* manager);
/**
* Open a connection to a remote peer.
*/
enum EDiscordResult (DISCORD_API *open_peer)(struct IDiscordNetworkManager* manager, DiscordNetworkPeerId peer_id, const char* route_data);
/**
* Update the route data for a connected peer.
*/
enum EDiscordResult (DISCORD_API *update_peer)(struct IDiscordNetworkManager* manager, DiscordNetworkPeerId peer_id, const char* route_data);
/**
* Close the connection to a remote peer.
*/
enum EDiscordResult (DISCORD_API *close_peer)(struct IDiscordNetworkManager* manager, DiscordNetworkPeerId peer_id);
/**
* Open a message channel to a connected peer.
*/
enum EDiscordResult (DISCORD_API *open_channel)(struct IDiscordNetworkManager* manager, DiscordNetworkPeerId peer_id, DiscordNetworkChannelId channel_id, bool reliable);
/**
* Close a message channel to a connected peer.
*/
enum EDiscordResult (DISCORD_API *close_channel)(struct IDiscordNetworkManager* manager, DiscordNetworkPeerId peer_id, DiscordNetworkChannelId channel_id);
/**
* Send a message to a connected peer over an opened message channel.
*/
enum EDiscordResult (DISCORD_API *send_message)(struct IDiscordNetworkManager* manager, DiscordNetworkPeerId peer_id, DiscordNetworkChannelId channel_id, uint8_t* data, uint32_t data_length);
};
struct IDiscordOverlayEvents {
void (DISCORD_API *on_toggle)(void* event_data, bool locked);
};
struct IDiscordOverlayManager {
void (DISCORD_API *is_enabled)(struct IDiscordOverlayManager* manager, bool* enabled);
void (DISCORD_API *is_locked)(struct IDiscordOverlayManager* manager, bool* locked);
void (DISCORD_API *set_locked)(struct IDiscordOverlayManager* manager, bool locked, void* callback_data, void (DISCORD_API *callback)(void* callback_data, enum EDiscordResult result));
void (DISCORD_API *open_activity_invite)(struct IDiscordOverlayManager* manager, enum EDiscordActivityActionType type, void* callback_data, void (DISCORD_API *callback)(void* callback_data, enum EDiscordResult result));
void (DISCORD_API *open_guild_invite)(struct IDiscordOverlayManager* manager, const char* code, void* callback_data, void (DISCORD_API *callback)(void* callback_data, enum EDiscordResult result));
void (DISCORD_API *open_voice_settings)(struct IDiscordOverlayManager* manager, void* callback_data, void (DISCORD_API *callback)(void* callback_data, enum EDiscordResult result));
enum EDiscordResult (DISCORD_API *init_drawing_dxgi)(struct IDiscordOverlayManager* manager, IDXGISwapChain* swapchain, bool use_message_forwarding);
void (DISCORD_API *on_present)(struct IDiscordOverlayManager* manager);
void (DISCORD_API *forward_message)(struct IDiscordOverlayManager* manager, MSG* message);
void (DISCORD_API *key_event)(struct IDiscordOverlayManager* manager, bool down, const char* key_code, enum EDiscordKeyVariant variant);
void (DISCORD_API *char_event)(struct IDiscordOverlayManager* manager, const char* character);
void (DISCORD_API *mouse_button_event)(struct IDiscordOverlayManager* manager, uint8_t down, int32_t click_count, enum EDiscordMouseButton which, int32_t x, int32_t y);
void (DISCORD_API *mouse_motion_event)(struct IDiscordOverlayManager* manager, int32_t x, int32_t y);
void (DISCORD_API *ime_commit_text)(struct IDiscordOverlayManager* manager, const char* text);
void (DISCORD_API *ime_set_composition)(struct IDiscordOverlayManager* manager, const char* text, struct DiscordImeUnderline* underlines, uint32_t underlines_length, int32_t from, int32_t to);
void (DISCORD_API *ime_cancel_composition)(struct IDiscordOverlayManager* manager);
void (DISCORD_API *set_ime_composition_range_callback)(struct IDiscordOverlayManager* manager, void* on_ime_composition_range_changed_data, void (DISCORD_API *on_ime_composition_range_changed)(void* on_ime_composition_range_changed_data, int32_t from, int32_t to, struct DiscordRect* bounds, uint32_t bounds_length));
void (DISCORD_API *set_ime_selection_bounds_callback)(struct IDiscordOverlayManager* manager, void* on_ime_selection_bounds_changed_data, void (DISCORD_API *on_ime_selection_bounds_changed)(void* on_ime_selection_bounds_changed_data, struct DiscordRect anchor, struct DiscordRect focus, bool is_anchor_first));
bool (DISCORD_API *is_point_inside_click_zone)(struct IDiscordOverlayManager* manager, int32_t x, int32_t y);
};
typedef void* IDiscordStorageEvents;
struct IDiscordStorageManager {
enum EDiscordResult (DISCORD_API *read)(struct IDiscordStorageManager* manager, const char* name, uint8_t* data, uint32_t data_length, uint32_t* read);
void (DISCORD_API *read_async)(struct IDiscordStorageManager* manager, const char* name, void* callback_data, void (DISCORD_API *callback)(void* callback_data, enum EDiscordResult result, uint8_t* data, uint32_t data_length));
void (DISCORD_API *read_async_partial)(struct IDiscordStorageManager* manager, const char* name, uint64_t offset, uint64_t length, void* callback_data, void (DISCORD_API *callback)(void* callback_data, enum EDiscordResult result, uint8_t* data, uint32_t data_length));
enum EDiscordResult (DISCORD_API *write)(struct IDiscordStorageManager* manager, const char* name, uint8_t* data, uint32_t data_length);
void (DISCORD_API *write_async)(struct IDiscordStorageManager* manager, const char* name, uint8_t* data, uint32_t data_length, void* callback_data, void (DISCORD_API *callback)(void* callback_data, enum EDiscordResult result));
enum EDiscordResult (DISCORD_API *delete_)(struct IDiscordStorageManager* manager, const char* name);
enum EDiscordResult (DISCORD_API *exists)(struct IDiscordStorageManager* manager, const char* name, bool* exists);
void (DISCORD_API *count)(struct IDiscordStorageManager* manager, int32_t* count);
enum EDiscordResult (DISCORD_API *stat)(struct IDiscordStorageManager* manager, const char* name, struct DiscordFileStat* stat);
enum EDiscordResult (DISCORD_API *stat_at)(struct IDiscordStorageManager* manager, int32_t index, struct DiscordFileStat* stat);
enum EDiscordResult (DISCORD_API *get_path)(struct IDiscordStorageManager* manager, DiscordPath* path);
};
struct IDiscordStoreEvents {
void (DISCORD_API *on_entitlement_create)(void* event_data, struct DiscordEntitlement* entitlement);
void (DISCORD_API *on_entitlement_delete)(void* event_data, struct DiscordEntitlement* entitlement);
};
struct IDiscordStoreManager {
void (DISCORD_API *fetch_skus)(struct IDiscordStoreManager* manager, void* callback_data, void (DISCORD_API *callback)(void* callback_data, enum EDiscordResult result));
void (DISCORD_API *count_skus)(struct IDiscordStoreManager* manager, int32_t* count);
enum EDiscordResult (DISCORD_API *get_sku)(struct IDiscordStoreManager* manager, DiscordSnowflake sku_id, struct DiscordSku* sku);
enum EDiscordResult (DISCORD_API *get_sku_at)(struct IDiscordStoreManager* manager, int32_t index, struct DiscordSku* sku);
void (DISCORD_API *fetch_entitlements)(struct IDiscordStoreManager* manager, void* callback_data, void (DISCORD_API *callback)(void* callback_data, enum EDiscordResult result));
void (DISCORD_API *count_entitlements)(struct IDiscordStoreManager* manager, int32_t* count);
enum EDiscordResult (DISCORD_API *get_entitlement)(struct IDiscordStoreManager* manager, DiscordSnowflake entitlement_id, struct DiscordEntitlement* entitlement);
enum EDiscordResult (DISCORD_API *get_entitlement_at)(struct IDiscordStoreManager* manager, int32_t index, struct DiscordEntitlement* entitlement);
enum EDiscordResult (DISCORD_API *has_sku_entitlement)(struct IDiscordStoreManager* manager, DiscordSnowflake sku_id, bool* has_entitlement);
void (DISCORD_API *start_purchase)(struct IDiscordStoreManager* manager, DiscordSnowflake sku_id, void* callback_data, void (DISCORD_API *callback)(void* callback_data, enum EDiscordResult result));
};
struct IDiscordVoiceEvents {
void (DISCORD_API *on_settings_update)(void* event_data);
};
struct IDiscordVoiceManager {
enum EDiscordResult (DISCORD_API *get_input_mode)(struct IDiscordVoiceManager* manager, struct DiscordInputMode* input_mode);
void (DISCORD_API *set_input_mode)(struct IDiscordVoiceManager* manager, struct DiscordInputMode input_mode, void* callback_data, void (DISCORD_API *callback)(void* callback_data, enum EDiscordResult result));
enum EDiscordResult (DISCORD_API *is_self_mute)(struct IDiscordVoiceManager* manager, bool* mute);
enum EDiscordResult (DISCORD_API *set_self_mute)(struct IDiscordVoiceManager* manager, bool mute);
enum EDiscordResult (DISCORD_API *is_self_deaf)(struct IDiscordVoiceManager* manager, bool* deaf);
enum EDiscordResult (DISCORD_API *set_self_deaf)(struct IDiscordVoiceManager* manager, bool deaf);
enum EDiscordResult (DISCORD_API *is_local_mute)(struct IDiscordVoiceManager* manager, DiscordSnowflake user_id, bool* mute);
enum EDiscordResult (DISCORD_API *set_local_mute)(struct IDiscordVoiceManager* manager, DiscordSnowflake user_id, bool mute);
enum EDiscordResult (DISCORD_API *get_local_volume)(struct IDiscordVoiceManager* manager, DiscordSnowflake user_id, uint8_t* volume);
enum EDiscordResult (DISCORD_API *set_local_volume)(struct IDiscordVoiceManager* manager, DiscordSnowflake user_id, uint8_t volume);
};
struct IDiscordAchievementEvents {
void (DISCORD_API *on_user_achievement_update)(void* event_data, struct DiscordUserAchievement* user_achievement);
};
struct IDiscordAchievementManager {
void (DISCORD_API *set_user_achievement)(struct IDiscordAchievementManager* manager, DiscordSnowflake achievement_id, uint8_t percent_complete, void* callback_data, void (DISCORD_API *callback)(void* callback_data, enum EDiscordResult result));
void (DISCORD_API *fetch_user_achievements)(struct IDiscordAchievementManager* manager, void* callback_data, void (DISCORD_API *callback)(void* callback_data, enum EDiscordResult result));
void (DISCORD_API *count_user_achievements)(struct IDiscordAchievementManager* manager, int32_t* count);
enum EDiscordResult (DISCORD_API *get_user_achievement)(struct IDiscordAchievementManager* manager, DiscordSnowflake user_achievement_id, struct DiscordUserAchievement* user_achievement);
enum EDiscordResult (DISCORD_API *get_user_achievement_at)(struct IDiscordAchievementManager* manager, int32_t index, struct DiscordUserAchievement* user_achievement);
};
typedef void* IDiscordCoreEvents;
struct IDiscordCore {
void (DISCORD_API *destroy)(struct IDiscordCore* core);
enum EDiscordResult (DISCORD_API *run_callbacks)(struct IDiscordCore* core);
void (DISCORD_API *set_log_hook)(struct IDiscordCore* core, enum EDiscordLogLevel min_level, void* hook_data, void (DISCORD_API *hook)(void* hook_data, enum EDiscordLogLevel level, const char* message));
struct IDiscordApplicationManager* (DISCORD_API *get_application_manager)(struct IDiscordCore* core);
struct IDiscordUserManager* (DISCORD_API *get_user_manager)(struct IDiscordCore* core);
struct IDiscordImageManager* (DISCORD_API *get_image_manager)(struct IDiscordCore* core);
struct IDiscordActivityManager* (DISCORD_API *get_activity_manager)(struct IDiscordCore* core);
struct IDiscordRelationshipManager* (DISCORD_API *get_relationship_manager)(struct IDiscordCore* core);
struct IDiscordLobbyManager* (DISCORD_API *get_lobby_manager)(struct IDiscordCore* core);
struct IDiscordNetworkManager* (DISCORD_API *get_network_manager)(struct IDiscordCore* core);
struct IDiscordOverlayManager* (DISCORD_API *get_overlay_manager)(struct IDiscordCore* core);
struct IDiscordStorageManager* (DISCORD_API *get_storage_manager)(struct IDiscordCore* core);
struct IDiscordStoreManager* (DISCORD_API *get_store_manager)(struct IDiscordCore* core);
struct IDiscordVoiceManager* (DISCORD_API *get_voice_manager)(struct IDiscordCore* core);
struct IDiscordAchievementManager* (DISCORD_API *get_achievement_manager)(struct IDiscordCore* core);
};
struct DiscordCreateParams {
DiscordClientId client_id;
uint64_t flags;
IDiscordCoreEvents* events;
void* event_data;
IDiscordApplicationEvents* application_events;
DiscordVersion application_version;
struct IDiscordUserEvents* user_events;
DiscordVersion user_version;
IDiscordImageEvents* image_events;
DiscordVersion image_version;
struct IDiscordActivityEvents* activity_events;
DiscordVersion activity_version;
struct IDiscordRelationshipEvents* relationship_events;
DiscordVersion relationship_version;
struct IDiscordLobbyEvents* lobby_events;
DiscordVersion lobby_version;
struct IDiscordNetworkEvents* network_events;
DiscordVersion network_version;
struct IDiscordOverlayEvents* overlay_events;
DiscordVersion overlay_version;
IDiscordStorageEvents* storage_events;
DiscordVersion storage_version;
struct IDiscordStoreEvents* store_events;
DiscordVersion store_version;
struct IDiscordVoiceEvents* voice_events;
DiscordVersion voice_version;
struct IDiscordAchievementEvents* achievement_events;
DiscordVersion achievement_version;
};
#ifdef __cplusplus
inline
#else
static
#endif
void DiscordCreateParamsSetDefault(struct DiscordCreateParams* params)
{
memset(params, 0, sizeof(struct DiscordCreateParams));
params->application_version = DISCORD_APPLICATION_MANAGER_VERSION;
params->user_version = DISCORD_USER_MANAGER_VERSION;
params->image_version = DISCORD_IMAGE_MANAGER_VERSION;
params->activity_version = DISCORD_ACTIVITY_MANAGER_VERSION;
params->relationship_version = DISCORD_RELATIONSHIP_MANAGER_VERSION;
params->lobby_version = DISCORD_LOBBY_MANAGER_VERSION;
params->network_version = DISCORD_NETWORK_MANAGER_VERSION;
params->overlay_version = DISCORD_OVERLAY_MANAGER_VERSION;
params->storage_version = DISCORD_STORAGE_MANAGER_VERSION;
params->store_version = DISCORD_STORE_MANAGER_VERSION;
params->voice_version = DISCORD_VOICE_MANAGER_VERSION;
params->achievement_version = DISCORD_ACHIEVEMENT_MANAGER_VERSION;
}
enum EDiscordResult DISCORD_API DiscordCreate(DiscordVersion version, struct DiscordCreateParams* params, struct IDiscordCore** result);
#ifdef __cplusplus
}
#endif
#endif
``` | /content/code_sandbox/src/include/discord_game_sdk.h | objective-c | 2016-06-25T22:29:10 | 2024-08-16T19:09:21 | 86Box | 86Box/86Box | 2,616 | 9,540 |
```objective-c
// Minitrace
//
// path_to_url
// Released under the MIT license.
//
// Ultra-light dependency free library for performance tracing C/C++ applications.
// Produces traces compatible with Google Chrome's trace viewer.
// Simply open "about:tracing" in Chrome and load the produced JSON.
//
// This contains far less template magic than the original libraries from Chrome
// because this is meant to be usable from C.
//
// See README.md for a tutorial.
//
// The trace format is documented here:
// path_to_url
// More:
// path_to_url
#ifndef MINITRACE_H
#define MINITRACE_H
#include <inttypes.h>
// If MTR_ENABLED is not defined, Minitrace does nothing and has near zero overhead.
// Preferably, set this flag in your build system. If you can't just uncomment this line.
// #define MTR_ENABLED
// By default, will collect up to 1000000 events, then you must flush.
// It's recommended that you simply call mtr_flush on a background thread
// occasionally. It's safe...ish.
#define INTERNAL_MINITRACE_BUFFER_SIZE 1000000
#ifdef __cplusplus
extern "C" {
#endif
// Initializes Minitrace. Must be called very early during startup of your executable,
// before any MTR_ statements.
void mtr_init(const char *json_file);
// Same as above, but allows passing in a custom stream (FILE *), as returned by
// fopen(). It should be opened for writing, preferably in binary mode to avoid
// processing of line endings (i.e. the "wb" mode).
void mtr_init_from_stream(void *stream);
// Shuts down minitrace cleanly, flushing the trace buffer.
void mtr_shutdown(void);
// Lets you enable and disable Minitrace at runtime.
// May cause strange discontinuities in the output.
// Minitrace is enabled on startup by default.
void mtr_start(void);
void mtr_stop(void);
// Flushes the collected data to disk, clearing the buffer for new data.
void mtr_flush(void);
// Returns the current time in seconds. Used internally by Minitrace. No caching.
double mtr_time_s(void);
// Registers a handler that will flush the trace on Ctrl+C.
// Works on Linux and MacOSX, and in Win32 console applications.
void mtr_register_sigint_handler(void);
// Utility function that should rarely be used.
// If str is semi dynamic, store it permanently in a small pool so we don't need to malloc it.
// The pool fills up fast though and performance isn't great.
// Returns a fixed string if the pool is full.
const char *mtr_pool_string(const char *str);
// Commented-out types will be supported in the future.
typedef enum {
MTR_ARG_TYPE_NONE = 0,
MTR_ARG_TYPE_INT = 1, // I
// MTR_ARG_TYPE_FLOAT = 2, // TODO
// MTR_ARG_TYPE_DOUBLE = 3, // TODO
MTR_ARG_TYPE_STRING_CONST = 8, // C
MTR_ARG_TYPE_STRING_COPY = 9,
// MTR_ARG_TYPE_JSON_COPY = 10,
} mtr_arg_type;
// TODO: Add support for more than one argument (metadata) per event
// Having more costs speed and memory.
#define MTR_MAX_ARGS 1
// Only use the macros to call these.
void internal_mtr_raw_event(const char *category, const char *name, char ph, void *id);
void internal_mtr_raw_event_arg(const char *category, const char *name, char ph, void *id, mtr_arg_type arg_type, const char *arg_name, void *arg_value);
#ifdef MTR_ENABLED
// c - category. Can be filtered by in trace viewer (or at least that's the intention).
// A good use is to pass __FILE__, there are macros further below that will do it for you.
// n - name. Pass __FUNCTION__ in most cases, unless you are marking up parts of one.
// Scopes. In C++, use MTR_SCOPE. In C, always match them within the same scope.
#define MTR_BEGIN(c, n) internal_mtr_raw_event(c, n, 'B', 0)
#define MTR_END(c, n) internal_mtr_raw_event(c, n, 'E', 0)
#define MTR_SCOPE(c, n) MTRScopedTrace ____mtr_scope(c, n)
#define MTR_SCOPE_LIMIT(c, n, l) MTRScopedTraceLimit ____mtr_scope(c, n, l)
// Async events. Can span threads. ID identifies which events to connect in the view.
#define MTR_START(c, n, id) internal_mtr_raw_event(c, n, 'S', (void *)(id))
#define MTR_STEP(c, n, id, step) internal_mtr_raw_event_arg(c, n, 'T', (void *)(id), MTR_ARG_TYPE_STRING_CONST, "step", (void *)(step))
#define MTR_FINISH(c, n, id) internal_mtr_raw_event(c, n, 'F', (void *)(id))
// Flow events. Like async events, but displayed in a more fancy way in the viewer.
#define MTR_FLOW_START(c, n, id) internal_mtr_raw_event(c, n, 's', (void *)(id))
#define MTR_FLOW_STEP(c, n, id, step) internal_mtr_raw_event_arg(c, n, 't', (void *)(id), MTR_ARG_TYPE_STRING_CONST, "step", (void *)(step))
#define MTR_FLOW_FINISH(c, n, id) internal_mtr_raw_event(c, n, 'f', (void *)(id))
// The same macros, but with a single named argument which shows up as metadata in the viewer.
// _I for int.
// _C is for a const string arg.
// _S will copy the string, freeing on flush (expensive but sometimes necessary).
// but required if the string was generated dynamically.
// Note that it's fine to match BEGIN_S with END and BEGIN with END_S, etc.
#define MTR_BEGIN_C(c, n, aname, astrval) internal_mtr_raw_event_arg(c, n, 'B', 0, MTR_ARG_TYPE_STRING_CONST, aname, (void *)(astrval))
#define MTR_END_C(c, n, aname, astrval) internal_mtr_raw_event_arg(c, n, 'E', 0, MTR_ARG_TYPE_STRING_CONST, aname, (void *)(astrval))
#define MTR_SCOPE_C(c, n, aname, astrval) MTRScopedTraceArg ____mtr_scope(c, n, MTR_ARG_TYPE_STRING_CONST, aname, (void *)(astrval))
#define MTR_BEGIN_S(c, n, aname, astrval) internal_mtr_raw_event_arg(c, n, 'B', 0, MTR_ARG_TYPE_STRING_COPY, aname, (void *)(astrval))
#define MTR_END_S(c, n, aname, astrval) internal_mtr_raw_event_arg(c, n, 'E', 0, MTR_ARG_TYPE_STRING_COPY, aname, (void *)(astrval))
#define MTR_SCOPE_S(c, n, aname, astrval) MTRScopedTraceArg ____mtr_scope(c, n, MTR_ARG_TYPE_STRING_COPY, aname, (void *)(astrval))
#define MTR_BEGIN_I(c, n, aname, aintval) internal_mtr_raw_event_arg(c, n, 'B', 0, MTR_ARG_TYPE_INT, aname, (void*)(intptr_t)(aintval))
#define MTR_END_I(c, n, aname, aintval) internal_mtr_raw_event_arg(c, n, 'E', 0, MTR_ARG_TYPE_INT, aname, (void*)(intptr_t)(aintval))
#define MTR_SCOPE_I(c, n, aname, aintval) MTRScopedTraceArg ____mtr_scope(c, n, MTR_ARG_TYPE_INT, aname, (void*)(intptr_t)(aintval))
// Instant events. For things with no duration.
#define MTR_INSTANT(c, n) internal_mtr_raw_event(c, n, 'I', 0)
#define MTR_INSTANT_C(c, n, aname, astrval) internal_mtr_raw_event_arg(c, n, 'I', 0, MTR_ARG_TYPE_STRING_CONST, aname, (void *)(astrval))
#define MTR_INSTANT_I(c, n, aname, aintval) internal_mtr_raw_event_arg(c, n, 'I', 0, MTR_ARG_TYPE_INT, aname, (void *)(aintval))
// Counters (can't do multi-value counters yet)
#define MTR_COUNTER(c, n, val) internal_mtr_raw_event_arg(c, n, 'C', 0, MTR_ARG_TYPE_INT, n, (void *)(intptr_t)(val))
// Metadata. Call at the start preferably. Must be const strings.
#define MTR_META_PROCESS_NAME(n) internal_mtr_raw_event_arg("", "process_name", 'M', 0, MTR_ARG_TYPE_STRING_COPY, "name", (void *)(n))
#define MTR_META_THREAD_NAME(n) internal_mtr_raw_event_arg("", "thread_name", 'M', 0, MTR_ARG_TYPE_STRING_COPY, "name", (void *)(n))
#define MTR_META_THREAD_SORT_INDEX(i) internal_mtr_raw_event_arg("", "thread_sort_index", 'M', 0, MTR_ARG_TYPE_INT, "sort_index", (void *)(i))
#else
#define MTR_BEGIN(c, n)
#define MTR_END(c, n)
#define MTR_SCOPE(c, n)
#define MTR_START(c, n, id)
#define MTR_STEP(c, n, id, step)
#define MTR_FINISH(c, n, id)
#define MTR_FLOW_START(c, n, id)
#define MTR_FLOW_STEP(c, n, id, step)
#define MTR_FLOW_FINISH(c, n, id)
#define MTR_INSTANT(c, n)
#define MTR_BEGIN_C(c, n, aname, astrval)
#define MTR_END_C(c, n, aname, astrval)
#define MTR_SCOPE_C(c, n, aname, astrval)
#define MTR_BEGIN_S(c, n, aname, astrval)
#define MTR_END_S(c, n, aname, astrval)
#define MTR_SCOPE_S(c, n, aname, astrval)
#define MTR_BEGIN_I(c, n, aname, aintval)
#define MTR_END_I(c, n, aname, aintval)
#define MTR_SCOPE_I(c, n, aname, aintval)
#define MTR_INSTANT(c, n)
#define MTR_INSTANT_C(c, n, aname, astrval)
#define MTR_INSTANT_I(c, n, aname, aintval)
// Counters (can't do multi-value counters yet)
#define MTR_COUNTER(c, n, val)
// Metadata. Call at the start preferably. Must be const strings.
#define MTR_META_PROCESS_NAME(n)
#define MTR_META_THREAD_NAME(n)
#define MTR_META_THREAD_SORT_INDEX(i)
#endif
// Shortcuts for simple function timing with automatic categories and names.
#define MTR_BEGIN_FUNC() MTR_BEGIN(__FILE__, __FUNCTION__)
#define MTR_END_FUNC() MTR_END(__FILE__, __FUNCTION__)
#define MTR_SCOPE_FUNC() MTR_SCOPE(__FILE__, __FUNCTION__)
#define MTR_INSTANT_FUNC() MTR_INSTANT(__FILE__, __FUNCTION__)
#define MTR_SCOPE_FUNC_LIMIT_S(l) MTRScopedTraceLimit ____mtr_scope(__FILE__, __FUNCTION__, l)
#define MTR_SCOPE_FUNC_LIMIT_MS(l) MTRScopedTraceLimit ____mtr_scope(__FILE__, __FUNCTION__, (double)l * 0.000001)
// Same, but with a single argument of the usual types.
#define MTR_BEGIN_FUNC_S(aname, arg) MTR_BEGIN_S(__FILE__, __FUNCTION__, aname, arg)
#define MTR_END_FUNC_S(aname, arg) MTR_END_S(__FILE__, __FUNCTION__, aname, arg)
#define MTR_SCOPE_FUNC_S(aname, arg) MTR_SCOPE_S(__FILE__, __FUNCTION__, aname, arg)
#define MTR_BEGIN_FUNC_C(aname, arg) MTR_BEGIN_C(__FILE__, __FUNCTION__, aname, arg)
#define MTR_END_FUNC_C(aname, arg) MTR_END_C(__FILE__, __FUNCTION__, aname, arg)
#define MTR_SCOPE_FUNC_C(aname, arg) MTR_SCOPE_C(__FILE__, __FUNCTION__, aname, arg)
#define MTR_BEGIN_FUNC_I(aname, arg) MTR_BEGIN_I(__FILE__, __FUNCTION__, aname, arg)
#define MTR_END_FUNC_I(aname, arg) MTR_END_I(__FILE__, __FUNCTION__, aname, arg)
#define MTR_SCOPE_FUNC_I(aname, arg) MTR_SCOPE_I(__FILE__, __FUNCTION__, aname, arg)
#ifdef __cplusplus
}
#ifdef MTR_ENABLED
// These are optimized to use X events (combined B and E). Much easier to do in C++ than in C.
class MTRScopedTrace {
public:
MTRScopedTrace(const char *category, const char *name)
: category_(category), name_(name) {
start_time_ = mtr_time_s();
}
~MTRScopedTrace() {
internal_mtr_raw_event(category_, name_, 'X', &start_time_);
}
private:
const char *category_;
const char *name_;
double start_time_;
};
// Only outputs a block if execution time exceeded the limit.
// TODO: This will effectively call mtr_time_s twice at the end, which is bad.
class MTRScopedTraceLimit {
public:
MTRScopedTraceLimit(const char *category, const char *name, double limit_s)
: category_(category), name_(name), limit_(limit_s) {
start_time_ = mtr_time_s();
}
~MTRScopedTraceLimit() {
double end_time = mtr_time_s();
if (end_time - start_time_ >= limit_) {
internal_mtr_raw_event(category_, name_, 'X', &start_time_);
}
}
private:
const char *category_;
const char *name_;
double start_time_;
double limit_;
};
class MTRScopedTraceArg {
public:
MTRScopedTraceArg(const char *category, const char *name, mtr_arg_type arg_type, const char *arg_name, void *arg_value)
: category_(category), name_(name) {
internal_mtr_raw_event_arg(category, name, 'B', 0, arg_type, arg_name, arg_value);
}
~MTRScopedTraceArg() {
internal_mtr_raw_event(category_, name_, 'E', 0);
}
private:
const char *category_;
const char *name_;
};
#endif
#endif
#endif
``` | /content/code_sandbox/src/include/minitrace/minitrace.h | objective-c | 2016-06-25T22:29:10 | 2024-08-16T19:09:21 | 86Box | 86Box/86Box | 2,616 | 3,184 |
```objective-c
/*
* 86Box A hypervisor and IBM PC system emulator that specializes in
* running old operating systems and software designed for IBM
* PC systems and compatibles from 1981 through fairly recent
* system designs based on the PCI bus.
*
* This file is part of the 86Box distribution.
*
* Sound Blaster emulation.
*
* Authors: Sarah Walker, <path_to_url
* Miran Grca, <mgrca8@gmail.com>
* TheCollector1995, <mariogplayer@gmail.com>
*
*/
#ifndef SOUND_SND_SB_H
#define SOUND_SND_SB_H
#include <86box/snd_cms.h>
#include <86box/snd_emu8k.h>
#include <86box/snd_mpu401.h>
#include <86box/snd_opl.h>
#include <86box/snd_sb_dsp.h>
enum {
SADLIB = 1, /* No DSP */
SB1, /* DSP v1.05 */
SB15, /* DSP v2.00 */
SB2, /* DSP v2.01 - needed for high-speed DMA */
SBPRO, /* DSP v3.00 */
SBPRO2, /* DSP v3.02 + OPL3 */
SB16, /* DSP v4.05 + OPL3 */
SBAWE32, /* DSP v4.12 + OPL3 */
SBAWE32PNP, /* DSP v4.13 + OPL3 */
SBAWE64 /* DSP v4.16 + OPL3 */
};
/* SB 2.0 CD version */
typedef struct sb_ct1335_mixer_t {
double master;
double voice;
double fm;
double cd;
uint8_t index;
uint8_t regs[256];
} sb_ct1335_mixer_t;
/* SB PRO */
typedef struct sb_ct1345_mixer_t {
double master_l;
double master_r;
double voice_l;
double voice_r;
double fm_l;
double fm_r;
double cd_l;
double cd_r;
double line_l;
double line_r;
double mic;
/*see sb_ct1745_mixer for values for input selector*/
int32_t input_selector;
int input_filter;
int in_filter_freq;
int output_filter;
int stereo;
int stereo_isleft;
uint8_t index;
uint8_t regs[256];
} sb_ct1345_mixer_t;
/* SB16 and AWE32 */
typedef struct sb_ct1745_mixer_t {
double master_l;
double master_r;
double voice_l;
double voice_r;
double fm_l;
double fm_r;
double cd_l;
double cd_r;
double line_l;
double line_r;
double mic;
double speaker;
int bass_l;
int bass_r;
int treble_l;
int treble_r;
int output_selector;
#define OUTPUT_MIC 1
#define OUTPUT_CD_R 2
#define OUTPUT_CD_L 4
#define OUTPUT_LINE_R 8
#define OUTPUT_LINE_L 16
int input_selector_left;
int input_selector_right;
#define INPUT_MIC 1
#define INPUT_CD_R 2
#define INPUT_CD_L 4
#define INPUT_LINE_R 8
#define INPUT_LINE_L 16
#define INPUT_MIDI_R 32
#define INPUT_MIDI_L 64
int mic_agc;
int32_t input_gain_L;
int32_t input_gain_R;
double output_gain_L;
double output_gain_R;
uint8_t index;
uint8_t regs[256];
int output_filter; /* for clones */
} sb_ct1745_mixer_t;
/* ESS AudioDrive */
typedef struct ess_mixer_t {
double master_l;
double master_r;
double voice_l;
double voice_r;
double fm_l;
double fm_r;
double cd_l;
double cd_r;
double line_l;
double line_r;
double mic_l;
double mic_r;
double auxb_l;
double auxb_r;
double speaker;
/*see sb_ct1745_mixer for values for input selector*/
int32_t input_selector;
/* extra values for input selector */
#define INPUT_MIXER_L 128
#define INPUT_MIXER_R 256
int input_filter;
int in_filter_freq;
int output_filter;
int stereo;
int stereo_isleft;
uint8_t index;
uint8_t regs[256];
uint8_t ess_id_str[4];
uint8_t ess_id_str_pos;
} ess_mixer_t;
typedef struct sb_t {
uint8_t cms_enabled;
uint8_t opl_enabled;
uint8_t mixer_enabled;
cms_t cms;
fm_drv_t opl;
fm_drv_t opl2;
sb_dsp_t dsp;
union {
sb_ct1335_mixer_t mixer_sb2;
sb_ct1345_mixer_t mixer_sbpro;
sb_ct1745_mixer_t mixer_sb16;
ess_mixer_t mixer_ess;
};
mpu_t *mpu;
emu8k_t emu8k;
void *gameport;
int pnp;
uint8_t pos_regs[8];
uint8_t pnp_rom[512];
uint16_t opl_pnp_addr;
uint16_t midi_addr;
uint16_t gameport_addr;
void *opl_mixer;
void (*opl_mix)(void*, double*, double*);
} sb_t;
extern void sb_ct1345_mixer_write(uint16_t addr, uint8_t val, void *priv);
extern uint8_t sb_ct1345_mixer_read(uint16_t addr, void *priv);
extern void sb_ct1345_mixer_reset(sb_t *sb);
extern void sb_ct1745_mixer_write(uint16_t addr, uint8_t val, void *priv);
extern uint8_t sb_ct1745_mixer_read(uint16_t addr, void *priv);
extern void sb_ct1745_mixer_reset(sb_t *sb);
extern void sb_ess_mixer_write(uint16_t addr, uint8_t val, void *priv);
extern uint8_t sb_ess_mixer_read(uint16_t addr, void *priv);
extern void sb_ess_mixer_reset(sb_t *sb);
extern void sb_get_buffer_sbpro(int32_t *buffer, int len, void *priv);
extern void sb_get_music_buffer_sbpro(int32_t *buffer, int len, void *priv);
extern void sbpro_filter_cd_audio(int channel, double *buffer, void *priv);
extern void sb16_awe32_filter_cd_audio(int channel, double *buffer, void *priv);
extern void sb_close(void *priv);
extern void sb_speed_changed(void *priv);
#endif /*SOUND_SND_SB_H*/
``` | /content/code_sandbox/src/include/86box/snd_sb.h | objective-c | 2016-06-25T22:29:10 | 2024-08-16T19:09:21 | 86Box | 86Box/86Box | 2,616 | 1,512 |
```objective-c
/*
* 86Box A hypervisor and IBM PC system emulator that specializes in
* running old operating systems and software designed for IBM
* PC systems and compatibles from 1981 through fairly recent
* system designs based on the PCI bus.
*
* This file is part of the 86Box distribution.
*
* DDC monitor emulation definitions.
*
*
*
* Authors: Sarah Walker, <path_to_url
* RichardG, <richardg867@gmail.com>
*
*/
#ifndef EMU_VID_DDC_H
#define EMU_VID_DDC_H
extern void *ddc_init(void *i2c);
extern void ddc_close(void *eeprom);
#endif /*EMU_VID_DDC_H*/
``` | /content/code_sandbox/src/include/86box/vid_ddc.h | objective-c | 2016-06-25T22:29:10 | 2024-08-16T19:09:21 | 86Box | 86Box/86Box | 2,616 | 158 |
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