Bit-Exact AI Inference Verification Without Performance Tradeoffs
Paper • 2606.00279 • Published
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# CIS-2 conformance vector: attention_block_v1 |
# op=attention_block, spec ref: docs/CIS2_SPEC_v0.2.md §9.2 (Score), §9.3 |
# (Softmax), §9.4 (V-mix) -- one query head's full score/softmax/V-mix |
# pipeline against a small causal KV cache. Deliberately covers ONE head |
# only: GQA's `kv_head = qh / group` head-mapping (§9, opening paragraph) |
# is a pure indexing detail on top of this same per-head arithmetic, not |
# additional numeric behavior, so it is not separately vectored here. |
# RoPE (§7, already covered by rope_v1) is assumed already applied to |
# `q_head`/`k_j` inputs below, per §9.1's ordering (RoPE happens before |
# scoring) -- this vector starts from already-rotated q/k, as the spec's |
# §9.2 step itself does. |
# |
# Fields are `key=value`. `head_dim`/`seq_len` are plain decimal integers. |
# `q_head_bits` is head_dim values (the current step's query head, already |
# RoPE-rotated). `k_bits`/`v_bits` are `seq_len * head_dim` values, |
# ROW-MAJOR (cached key/value at position 0's head_dim entries, then |
# position 1, ... up to and including the current step `pos = seq_len - |
# 1`, causal -- every cached position is attended, per §9.2's `j = |
# 0..=pos`). All comma-separated `0x`-prefixed 32-bit hex IEEE-754 binary32 |
# bit patterns, per tests/conformance/README.md's general convention. |
op=attention_block |
spec_ref=docs/CIS2_SPEC_v0.2.md#9-attention-gqa-causal-per-decode-step-normative |
head_dim=8 |
seq_len=3 |
q_head_bits=0x3F800000,0x3F000000,0xBF000000,0x40000000,0xBF800000,0x3E800000,0x3F400000,0xC0000000 |
k_bits=0x3F000000,0x3F800000,0x3F800000,0xBF800000,0x3F000000,0x3F000000,0xBF000000,0x3F800000,0x3F800000,0xBF800000,0x3F000000,0x3F000000,0x3F800000,0xBF000000,0x3F000000,0x3F000000,0xBF000000,0x3F000000,0x3F800000,0x3F800000,0xBF800000,0x3F800000,0x3F000000,0xBF000000 |
v_bits=0x3F800000,0x00000000,0x00000000,0x3F800000,0x3F000000,0x3F000000,0xBF000000,0x00000000,0x00000000,0x3F800000,0x3F000000,0x00000000,0x3F800000,0x00000000,0x3F000000,0x3F000000,0x3F000000,0x3F000000,0x3F800000,0xBF000000,0x00000000,0x3F800000,0x00000000,0x3F800000 |
# CIS-2 conformance vector: exp_pinned_v1 |
# op=exp_pinned, spec ref: docs/CIS2_SPEC_v0.2.md §6.2 (pinned exp(x) |
# polynomial, route (b) fallback described in src/math.rs::exp_pinned). |
# |
# Fields are `key=value`. x_bits is a comma-separated list of |
# `0x`-prefixed 32-bit hex strings, each the raw IEEE-754 binary32 bit |
# pattern of one input element, in index order (index 0 first). |
# |
# n=8, deliberately small and hand-sized (same rationale as rmsnorm_v1's |
# n=8 / rope_v1's head_dim=8), spanning §6.2's documented accuracy domain |
# `x in [-40,40]` (softmax post-max-sub args <= 0, SiLU gate args, RoPE |
# inv_freq exponents): the two domain endpoints (-40, 40), a couple of |
# mid-range values on each side (-10, -1, 10), the two special values |
# 0.0 and 1.0 (exp(0)=1 exactly is a useful bit-exact sanity check), and |
# 0.5 to exercise a non-integer, non-zero small positive value. |
op=exp_pinned |
spec_ref=docs/CIS2_SPEC_v0.2.md#62-pinned-transcendentals |
n=8 |
x_bits=0xC2200000,0xC1200000,0xBF800000,0x00000000,0x3F000000,0x3F800000,0x41200000,0x42200000 |
# CIS-2 conformance vector: matvec_v1 |
# op=matvec, spec ref: docs/CIS2_SPEC_v0.2.md §5.2 (Matvec), which in turn |
# depends on §5.1 (strict left-to-right sequential dot product, `dot_seq`). |
# |
# Fields are `key=value`. `out_features`/`in_features` are plain decimal |
# integers (small config constants, no float-parsing ambiguity). |
# `w_bits` is `out_features * in_features` values, ROW-MAJOR (row `o`'s |
# `in_features` entries first, then row `o+1`, ...), each a |
# comma-separated `0x`-prefixed 32-bit hex IEEE-754 binary32 bit pattern |
# (per tests/conformance/README.md's general convention). `x_bits` is |
# `in_features` values, the shared input vector. |
op=matvec |
spec_ref=docs/CIS2_SPEC_v0.2.md#52-matvec-normative |
out_features=3 |
in_features=3 |
# Row 0 is §5.1's own worked example, verbatim: w[0,:] = [1e8, 1.0, -1e8] |
# dotted against x = [1,1,1] MUST give exactly 0.0_f32 (the `1.0` term is |
# lost to rounding against the 1e8 partial sum) -- a conforming |
# implementation MUST reproduce this exact cancellation, not just "close". |
# Row 1 and row 2 use small exactly-representable values (no order |
# sensitivity) as a plain-arithmetic sanity check alongside the |
# order-sensitive row 0. |
w_bits=0x4CBEBC20,0x3F800000,0xCCBEBC20,0x3F800000,0x40000000,0x40400000,0x3F000000,0xBFC00000,0x40800000 |
x_bits=0x3F800000,0x3F800000,0x3F800000 |
# CIS-2 conformance vector: rmsnorm_v1 |
# op=rmsnorm, spec ref: docs/CIS2_SPEC_v0.2.md §8 |
# |
# Fields are `key=value`. Vector fields (x_bits, gamma_bits) are |
# comma-separated lists of `0x`-prefixed 32-bit hex, each the raw IEEE-754 |
# binary32 bit pattern of one element, in index order (index 0 first). |
# eps_bits is the single f32 bit pattern for CIS-2 EPS_F32 (§2.3). |
op=rmsnorm |
spec_ref=docs/CIS2_SPEC_v0.2.md#8-rmsnorm-normative |
n=8 |
eps_bits=0x3727C5AC |
x_bits=0x3F800000,0xC0000000,0x40400000,0x3F000000,0xBF000000,0x40800000,0xBFC00000,0x40100000 |
gamma_bits=0x3F000000,0x3FC00000,0x3F800000,0x40000000,0x3E800000,0x3F800000,0x40400000,0x3F400000 |
# CIS-2 conformance vector: rope_v1 |
# op=rope_table, spec ref: docs/CIS2_SPEC_v0.2.md §7 (RoPE) |
# |
# Fields are `key=value`. head_dim and positions are plain decimal |
# integers (no ambiguity: head_dim is a small config constant, and |
# `positions` values are sequence positions, cast to f32 *exactly* per |
# §7.3 -- both are exact integers well within f32's exact-integer range, |
# so there is no float-parsing-rounding ambiguity to route around here, |
# unlike genuinely fractional float inputs). rope_theta_bits is the single |
# f32 bit pattern of rope_theta (comma-separated 0x-prefixed 32-bit hex |
# convention, per tests/conformance/README.md, applied to a length-1 list). |
op=rope_table |
spec_ref=docs/CIS2_SPEC_v0.2.md#7-rope-normative |
head_dim=8 |
rope_theta_bits=0x461C4000 |
positions=0,3 |
CIS-2 — conformance vectors for bit-identical fp32 transformer inference
Floating-point transformer inference is usually treated as unavoidably nondeterministic across hardware. Reduction order, FMA contraction, denormal handling and platform math libraries all differ between x86_64 and aarch64, and between compilers, so "the same model on the same input" in practice means "agrees to within a tolerance", not bit-for-bit.
CIS-2 is a written specification that removes those degrees of freedom, and this repository holds the artifacts a third party needs to check whether their own implementation conforms: the spec text, five op-level conformance vectors with pinned expected outputs, the expected end-to-end digests, and the GPU result.
Everything here is Apache-2.0. Source of truth and CI:
https://github.com/Aefinity-AI/cis2-spec — tagged release
v0.3b.
This dataset is a snapshot assembled from that repository. If the two ever disagree, the repository wins.
The claim
CIS2_REF, SmolLM2-135M, prompt "Once upon a time", 16 greedy tokens, spec v0.3b
d82743059d1db929e710236fe4ec37f89e6f932524801345a006980f7c3cc9df
That digest is a SHA-256 witness chain folded over the complete fp32 logit vector at every decode step — not the argmax token, the whole vector. It is currently reproduced by:
| implementation | written from | platforms |
|---|---|---|
| Rust reference | — | x86_64, aarch64 (native runners) |
Rust clean-room verify2/ |
the spec text alone | x86_64, aarch64 |
C11 clean-room verify3/ |
the spec text alone | x86_64, aarch64 · gcc and clang |
| CUDA port (not published) | the spec text alone | NVIDIA Tesla P100, sm_60, CUDA 12.8 |
The two clean-room implementations were written without access to the reference
source or to each other. Public CI re-checks all of the CPU rows on every push.
The GPU row is documented in GPU_RESULT.md; on that run the per-step trace was
byte-identical to the CPU trace, not merely equal at the final digest.
What is pinned
- Reduction order — strictly left-to-right, sequential.
- FMA contraction — forbidden, and gated by
objdumpin CI. - Denormals — FTZ/DAZ on, pinned via MXCSR (x86) and FPCR.FZ (aarch64).
- Transcendentals —
sin/cosby octant reduction plus separate Cephes-pattern minimax polynomials;expandlnby pinned Cephes-pattern polynomials;rsqrtcorrectly rounded with no table. Every coefficient is pinned as an f32 hex literal and hashed into the witness chain. - RoPE
inv_freq— pinned table, theta-general. - Tokenization — byte-level BPE pinned at the byte level.
Full normative text: CIS2_SPEC_v0.3b.md (§13.1 carries the pinned vector).
Files
| file | what it is |
|---|---|
CIS2_SPEC_v0.3b.md |
the normative specification |
EXPECTED_DIGESTS.md |
pinned end-to-end digests, including the GPU confirmation |
GPU_RESULT.md |
the 2026-09-08 NVIDIA Tesla P100 run, with its scope limits |
PROTOCOL.md |
the stdin/stdout wire contract a third-party binary implements |
vectors/README.md |
per-op field layout of each vector file |
vectors/*.txt |
five op-level input vectors: matvec, rmsnorm, rope, exp_pinned, attention_block |
vectors/*.expected |
the pinned expected output for each |
The vectors are plain text key=value files with float fields given as exact
hex bit patterns, so parsing introduces no rounding of its own. They exist so an
implementation can be checked op by op — you find out which operation
diverges, instead of only that a 64-character digest came out wrong.
How to check your own implementation
git clone https://github.com/Aefinity-AI/cis2-spec
cd cis2-spec
cargo run --release --bin cis2-conformance -- /path/to/your-binary
PROTOCOL.md is the complete contract; you do not need to read any of this
project's Rust to implement against it.
Scope, stated plainly
fp32 scalar reference semantics, not a fast kernel. Greedy decoding. Models checked up to 1.5B parameters. The GPU leg is one Pascal device, one toolchain, correctness only — no tensor cores, no batching, no timing number is claimed anywhere in this project. The CUDA port itself is deliberately not published, so a second GPU implementation written from the spec would be a genuine independent check rather than a re-run of ours; that is the contribution we are asking for.
Prior art
Reproducible and deterministic inference is prior-occupied ground. Gensyn's
repops demonstrates a hash-matched CPU/CUDA fp32 forward pass; Microsoft's
RepDL provides reproducible linear-algebra operators with CPU and CUDA backends;
vLLM and SGLang both ship batch-invariant determinism modes; and
arXiv:2606.00279 verifies bit-exact GPU inference by emulating vendor silicon
tables. No "first" and no "only" claim is made here, and none should be
inferred.
The narrower thing CIS-2 is testing is whether a written document can carry enough information for strangers to converge on identical bits — across an ISA boundary, a compiler boundary, a language boundary, and a CPU/GPU boundary, with no implementation consulting another.
Falsification bounty
There is a standing $50-per-distinct-root-cause bounty for breaking this:
https://github.com/Aefinity-AI/alice-aegis/blob/main/CHALLENGE.md — write your
own implementation from CIS2_SPEC_v0.3b.md, in any language for any device,
and get a different digest. If the disagreement is because the spec text permits
two readings, that is the finding most worth paying for: it means the document
is not yet sufficient, which is the entire thing CIS-2 claims to be.
Aefinity AI Inc. · Justin Brian Thompson
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