type
stringclasses 5
values | content
stringlengths 9
163k
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|---|---|
defines
|
#define DW_IC_DATA_CMD 0x10
|
defines
|
#define DW_IC_DATA_CMD_CMD (1 << 8)
|
defines
|
#define DW_IC_DATA_CMD_STOP (1 << 9)
|
defines
|
#define DW_IC_SS_SCL_HCNT 0x14
|
defines
|
#define DW_IC_SS_SCL_LCNT 0x18
|
defines
|
#define DW_IC_FS_SCL_HCNT 0x1c
|
defines
|
#define DW_IC_FS_SCL_LCNT 0x20
|
defines
|
#define DW_IC_INTR_MASK 0x30
|
defines
|
#define DW_IC_RAW_INTR_STAT 0x34
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defines
|
#define DW_IC_INTR_RX_UNDER (1 << 0)
|
defines
|
#define DW_IC_INTR_RX_OVER (1 << 1)
|
defines
|
#define DW_IC_INTR_RX_FULL (1 << 2)
|
defines
|
#define DW_IC_INTR_TX_OVER (1 << 3)
|
defines
|
#define DW_IC_INTR_TX_EMPTY (1 << 4)
|
defines
|
#define DW_IC_INTR_RD_REQ (1 << 5)
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defines
|
#define DW_IC_INTR_TX_ABRT (1 << 6)
|
defines
|
#define DW_IC_INTR_RX_DONE (1 << 7)
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defines
|
#define DW_IC_INTR_ACTIVITY (1 << 8)
|
defines
|
#define DW_IC_INTR_STOP_DET (1 << 9)
|
defines
|
#define DW_IC_INTR_START_DET (1 << 10)
|
defines
|
#define DW_IC_INTR_GEN_CALL (1 << 11)
|
defines
|
#define DW_IC_RX_TL 0x38
|
defines
|
#define DW_IC_TX_TL 0x3c
|
defines
|
#define DW_IC_CLR_INTR 0x40
|
defines
|
#define DW_IC_CLR_TX_ABRT 0x54
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defines
|
#define DW_IC_SDA_HOLD 0x7c
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defines
|
#define DW_IC_ENABLE 0x6c
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defines
|
#define DW_IC_ENABLE_ENABLE (1 << 0)
|
defines
|
#define DW_IC_STATUS 0x70
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defines
|
#define DW_IC_STATUS_TFNF (1 << 1)
|
defines
|
#define DW_IC_STATUS_TFE (1 << 2)
|
defines
|
#define DW_IC_STATUS_RFNE (1 << 3)
|
defines
|
#define DW_IC_STATUS_MST_ACTIVITY (1 << 5)
|
defines
|
#define DW_IC_TX_ABRT_SOURCE 0x80
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defines
|
#define DW_IC_ENABLE_STATUS 0x9c
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defines
|
#define DW_IC_ENABLE_STATUS_IC_EN (1 << 0)
|
defines
|
#define DW_IC_COMP_VERSION 0xf8
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defines
|
#define DW_IC_SDA_HOLD_MIN_VERS 0x3131312A
|
defines
|
#define DW_IC_COMP_TYPE 0xfc
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defines
|
#define DW_IC_COMP_TYPE_VALUE 0x44570140
|
defines
|
#define MAX_T_POLL_COUNT 100
|
defines
|
#define DW_TIMEOUT_IDLE (40 * MSECOND)
|
defines
|
#define DW_TIMEOUT_TX (2 * MSECOND)
|
defines
|
#define DW_TIMEOUT_RX (2 * MSECOND)
|
defines
|
#define DW_IC_SDA_HOLD_RX_SHIFT 16
|
defines
|
#define DW_IC_SDA_HOLD_RX_MASK GENMASK(23, DW_IC_SDA_HOLD_RX_SHIFT)
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structs
|
struct dw_i2c_dev {
void __iomem *base;
struct clk *clk;
struct i2c_adapter adapter;
u32 sda_hold_time;
};
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functions
|
void i2c_dw_enable(struct dw_i2c_dev *dw, bool enable)
{
u32 reg = 0;
/*
* This subrotine is an implementation of an algorithm
* described in "Cyclone V Hard Processor System Technical
* Reference * Manual" p. 20-19, "Disabling the I2C Controller"
*/
int timeout = MAX_T_POLL_COUNT;
if (enable)
reg |= DW_IC_ENABLE_ENABLE;
do {
uint32_t ic_enable_status;
writel(reg, dw->base + DW_IC_ENABLE);
ic_enable_status = readl(dw->base + DW_IC_ENABLE_STATUS);
if ((ic_enable_status & DW_IC_ENABLE_STATUS_IC_EN) == enable)
return;
udelay(250);
}
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functions
|
uint32_t
i2c_dw_scl_hcnt(uint32_t ic_clk, uint32_t tSYMBOL, uint32_t tf, int cond,
int offset)
{
/*
* DesignWare I2C core doesn't seem to have solid strategy to meet
* the tHD;STA timing spec. Configuring _HCNT based on tHIGH spec
* will result in violation of the tHD;STA spec.
*/
if (cond)
/*
* Conditional expression:
*
* IC_[FS]S_SCL_HCNT + (1+4+3) >= IC_CLK * tHIGH
*
* This is based on the DW manuals, and represents an ideal
* configuration. The resulting I2C bus speed will be
* faster than any of the others.
*
* If your hardware is free from tHD;STA issue, try this one.
*/
return (ic_clk * tSYMBOL + 500000) / 1000000 - 8 + offset;
else
/*
* Conditional expression:
*
* IC_[FS]S_SCL_HCNT + 3 >= IC_CLK * (tHD;STA + tf)
*
* This is just experimental rule; the tHD;STA period turned
* out to be proportinal to (_HCNT + 3). With this setting,
* we could meet both tHIGH and tHD;STA timing specs.
*
* If unsure, you'd better to take this alternative.
*
* The reason why we need to take into account "tf" here,
* is the same as described in i2c_dw_scl_lcnt().
*/
return (ic_clk * (tSYMBOL + tf) + 500000) / 1000000
- 3 + offset;
}
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functions
|
uint32_t
i2c_dw_scl_lcnt(uint32_t ic_clk, uint32_t tLOW, uint32_t tf, int offset)
{
/*
* Conditional expression:
*
* IC_[FS]S_SCL_LCNT + 1 >= IC_CLK * (tLOW + tf)
*
* DW I2C core starts counting the SCL CNTs for the LOW period
* of the SCL clock (tLOW) as soon as it pulls the SCL line.
* In order to meet the tLOW timing spec, we need to take into
* account the fall time of SCL signal (tf). Default tf value
* should be 0.3 us, for safety.
*/
return ((ic_clk * (tLOW + tf) + 500000) / 1000000) - 1 + offset;
}
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functions
|
void i2c_dw_setup_timings(struct dw_i2c_dev *dw)
{
uint32_t hcnt, lcnt;
u32 reg;
const uint32_t sda_falling_time = 300; /* ns */
const uint32_t scl_falling_time = 300; /* ns */
const unsigned int input_clock_khz = clk_get_rate(dw->clk) / 1000;
/* Set SCL timing parameters for standard-mode */
hcnt = i2c_dw_scl_hcnt(input_clock_khz,
4000, /* tHD;STA = tHIGH = 4.0 us */
sda_falling_time,
0, /* 0: DW default, 1: Ideal */
0); /* No offset */
lcnt = i2c_dw_scl_lcnt(input_clock_khz,
4700, /* tLOW = 4.7 us */
scl_falling_time,
0); /* No offset */
writel(hcnt, dw->base + DW_IC_SS_SCL_HCNT);
writel(lcnt, dw->base + DW_IC_SS_SCL_LCNT);
hcnt = i2c_dw_scl_hcnt(input_clock_khz,
600, /* tHD;STA = tHIGH = 0.6 us */
sda_falling_time,
0, /* 0: DW default, 1: Ideal */
0); /* No offset */
lcnt = i2c_dw_scl_lcnt(input_clock_khz,
1300, /* tLOW = 1.3 us */
scl_falling_time,
0); /* No offset */
writel(hcnt, dw->base + DW_IC_FS_SCL_HCNT);
writel(lcnt, dw->base + DW_IC_FS_SCL_LCNT);
/* Configure SDA Hold Time if required */
reg = readl(dw->base + DW_IC_COMP_VERSION);
if (reg >= DW_IC_SDA_HOLD_MIN_VERS) {
u32 ht;
int ret;
ret = of_property_read_u32(dw->adapter.dev.device_node,
"i2c-sda-hold-time-ns", &ht);
if (ret) {
/* Keep previous hold time setting if no one set it */
dw->sda_hold_time = readl(dw->base + DW_IC_SDA_HOLD);
}
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functions
|
else if (ht) {
dw->sda_hold_time = div_u64((u64)input_clock_khz * ht + 500000,
1000000);
}
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functions
|
int i2c_dw_wait_for_bits(struct dw_i2c_dev *dw, uint32_t offset,
uint32_t mask, uint32_t value, uint64_t timeout)
{
const uint64_t start = get_time_ns();
do {
const uint32_t reg = readl(dw->base + offset);
if ((reg & mask) == value)
return 0;
}
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functions
|
int i2c_dw_wait_for_idle(struct dw_i2c_dev *dw)
{
const uint32_t mask = DW_IC_STATUS_MST_ACTIVITY | DW_IC_STATUS_TFE;
const uint32_t value = DW_IC_STATUS_TFE;
return i2c_dw_wait_for_bits(dw, DW_IC_STATUS, mask, value,
DW_TIMEOUT_IDLE);
}
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functions
|
int i2c_dw_wait_for_tx_fifo_not_full(struct dw_i2c_dev *dw)
{
const uint32_t mask = DW_IC_STATUS_TFNF;
const uint32_t value = DW_IC_STATUS_TFNF;
return i2c_dw_wait_for_bits(dw, DW_IC_STATUS, mask, value,
DW_TIMEOUT_TX);
}
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functions
|
int i2c_dw_wait_for_rx_fifo_not_empty(struct dw_i2c_dev *dw)
{
const uint32_t mask = DW_IC_STATUS_RFNE;
const uint32_t value = DW_IC_STATUS_RFNE;
return i2c_dw_wait_for_bits(dw, DW_IC_STATUS, mask, value,
DW_TIMEOUT_RX);
}
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functions
|
void i2c_dw_reset(struct dw_i2c_dev *dw)
{
i2c_dw_enable(dw, false);
i2c_dw_enable(dw, true);
}
|
functions
|
void i2c_dw_abort_tx(struct dw_i2c_dev *dw)
{
i2c_dw_reset(dw);
}
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functions
|
void i2c_dw_abort_rx(struct dw_i2c_dev *dw)
{
i2c_dw_reset(dw);
}
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functions
|
int i2c_dw_read(struct dw_i2c_dev *dw,
const struct i2c_msg *msg)
{
int i;
for (i = 0; i < msg->len; i++) {
int ret;
const bool last_byte = i == msg->len - 1;
uint32_t ic_cmd_data = DW_IC_DATA_CMD_CMD;
if (last_byte)
ic_cmd_data |= DW_IC_DATA_CMD_STOP;
writel(ic_cmd_data, dw->base + DW_IC_DATA_CMD);
ret = i2c_dw_wait_for_rx_fifo_not_empty(dw);
if (ret < 0) {
i2c_dw_abort_rx(dw);
return ret;
}
|
functions
|
int i2c_dw_write(struct dw_i2c_dev *dw,
const struct i2c_msg *msg)
{
int i;
uint32_t ic_int_stat;
for (i = 0; i < msg->len; i++) {
int ret;
uint32_t ic_cmd_data;
const bool last_byte = i == msg->len - 1;
ic_int_stat = readl(dw->base + DW_IC_RAW_INTR_STAT);
if (ic_int_stat & DW_IC_INTR_TX_ABRT)
return -EIO;
ret = i2c_dw_wait_for_tx_fifo_not_full(dw);
if (ret < 0) {
i2c_dw_abort_tx(dw);
return ret;
}
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functions
|
int i2c_dw_wait_for_stop(struct dw_i2c_dev *dw)
{
const uint32_t mask = DW_IC_INTR_STOP_DET;
const uint32_t value = DW_IC_INTR_STOP_DET;
return i2c_dw_wait_for_bits(dw, DW_IC_RAW_INTR_STAT, mask, value,
DW_TIMEOUT_IDLE);
}
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functions
|
int i2c_dw_finish_xfer(struct dw_i2c_dev *dw)
{
int ret;
uint32_t ic_int_stat;
/*
* We expect the controller to signal STOP condition on the
* bus, so we are going to wait for that first.
*/
ret = i2c_dw_wait_for_stop(dw);
if (ret < 0)
return ret;
/*
* Now that we now that the stop condition has been signaled
* we need to wait for controller to go into IDLE state to
* make sure all of the possible error conditions on the bus
* have been propagated to apporpriate status
* registers. Experiment shows that not doing so often results
* in false positive "successful" transfers
*/
ret = i2c_dw_wait_for_idle(dw);
if (ret >= 0) {
ic_int_stat = readl(dw->base + DW_IC_RAW_INTR_STAT);
if (ic_int_stat & DW_IC_INTR_TX_ABRT)
return -EIO;
}
|
functions
|
int i2c_dw_set_address(struct dw_i2c_dev *dw, uint8_t address)
{
int ret;
uint32_t ic_tar;
/*
* As per "Cyclone V Hard Processor System Technical Reference
* Manual" p. 20-19, we have to wait for controller to be in
* idle state in order to be able to set the address
* dynamically
*/
ret = i2c_dw_wait_for_idle(dw);
if (ret < 0)
return ret;
ic_tar = readl(dw->base + DW_IC_TAR);
ic_tar &= 0xfffffc00;
writel(ic_tar | address, dw->base + DW_IC_TAR);
return 0;
}
|
functions
|
int i2c_dw_xfer(struct i2c_adapter *adapter,
struct i2c_msg *msgs, int num)
{
int i, ret = 0;
struct dw_i2c_dev *dw = to_dw_i2c_dev(adapter);
for (i = 0; i < num; i++) {
if (msgs[i].flags & I2C_M_DATA_ONLY)
return -ENOTSUPP;
ret = i2c_dw_set_address(dw, msgs[i].addr);
if (ret < 0)
break;
if (msgs[i].flags & I2C_M_RD)
ret = i2c_dw_read(dw, &msgs[i]);
else
ret = i2c_dw_write(dw, &msgs[i]);
if (ret < 0)
break;
ret = i2c_dw_finish_xfer(dw);
if (ret < 0)
break;
}
|
functions
|
int i2c_dw_probe(struct device_d *pdev)
{
struct resource *iores;
struct dw_i2c_dev *dw;
struct i2c_platform_data *pdata;
int ret, bitrate;
uint32_t ic_con, ic_comp_type_value;
pdata = pdev->platform_data;
dw = xzalloc(sizeof(*dw));
if (IS_ENABLED(CONFIG_COMMON_CLK)) {
dw->clk = clk_get(pdev, NULL);
if (IS_ERR(dw->clk)) {
ret = PTR_ERR(dw->clk);
goto fail;
}
|
defines
|
#define IAR_SECTION(arg)
|
defines
|
#define __no_init
|
defines
|
#define USB_FLG_TX_PACKET (1<<0)
|
defines
|
#define USB_FLG_MSGPTR_IS_ROM (1<<6)
|
defines
|
#define USB_FLG_USE_DEFAULT_RW (1<<7)
|
defines
|
#define USB_CFG_DESCR_PROPS_STRING_0 sizeof(usbDescriptorString0)
|
defines
|
#define USB_CFG_DESCR_PROPS_STRING_VENDOR sizeof(usbDescriptorStringVendor)
|
defines
|
#define USB_CFG_DESCR_PROPS_STRING_PRODUCT sizeof(usbDescriptorStringDevice)
|
defines
|
#define USB_CFG_DESCR_PROPS_STRING_SERIAL_NUMBER sizeof(usbDescriptorStringSerialNumber)
|
defines
|
#define USB_CFG_DESCR_PROPS_DEVICE sizeof(usbDescriptorDevice)
|
defines
|
#define USB_CFG_DESCR_PROPS_HID 9 /* length of HID descriptor in config descriptor below */
|
defines
|
#define USB_CFG_DESCR_PROPS_CONFIGURATION sizeof(usbDescriptorConfiguration)
|
defines
|
#define PRG_RDB(addr) pgm_read_byte(addr)
|
defines
|
#define GET_DESCRIPTOR(cfgProp, staticName) \
|
defines
|
#define SET_REPLY_LEN(len) replyLen = (len); usbMsgPtr = replyData
|
functions
|
void usbSetInterrupt(uchar *data, uchar len)
{
uchar *p, i;
#if USB_CFG_IMPLEMENT_HALT
if(usbTxLen1 == USBPID_STALL)
return;
#endif
#if 0 /* No runtime checks! Caller is responsible for valid data! */
if(len > 8) /* interrupt transfers are limited to 8 bytes */
len = 8;
#endif
if(usbTxLen1 & 0x10){ /* packet buffer was empty */
usbTxBuf1[0] ^= USBPID_DATA0 ^ USBPID_DATA1; /* toggle token */
}
|
functions
|
void usbSetInterrupt3(uchar *data, uchar len)
{
uchar *p, i;
if(usbTxLen3 & 0x10){ /* packet buffer was empty */
usbTxBuf3[0] ^= USBPID_DATA0 ^ USBPID_DATA1; /* toggle token */
}
|
functions
|
uchar usbRead(uchar *data, uchar len)
{
#if USB_CFG_IMPLEMENT_FN_READ
if(usbMsgFlags & USB_FLG_USE_DEFAULT_RW){
#endif
uchar i = len, *r = usbMsgPtr;
if(usbMsgFlags & USB_FLG_MSGPTR_IS_ROM){ /* ROM data */
while(i--){
uchar c = PRG_RDB(r); /* assign to char size variable to enforce byte ops */
*data++ = c;
r++;
}
|
functions
|
void usbProcessRx(uchar *data, uchar len)
{
usbRequest_t *rq = (void *)data;
uchar replyLen = 0, flags = USB_FLG_USE_DEFAULT_RW;
/* We use if() cascades because the compare is done byte-wise while switch()
* is int-based. The if() cascades are therefore more efficient.
*/
/* usbRxToken can be:
* 0x2d 00101101 (USBPID_SETUP for endpoint 0)
* 0xe1 11100001 (USBPID_OUT for endpoint 0)
* 0xff 11111111 (USBPID_OUT for endpoint 1)
*/
DBG2(0x10 + ((usbRxToken >> 1) & 3), data, len); /* SETUP0=12; OUT0=10; OUT1=13 */
#ifdef USB_RX_USER_HOOK
USB_RX_USER_HOOK(data, len)
#endif
#if USB_CFG_IMPLEMENT_FN_WRITEOUT
if(usbRxToken == 0xff){
usbFunctionWriteOut(data, len);
return; /* no reply expected, hence no usbMsgPtr, usbMsgFlags, usbMsgLen set */
}
|
functions
|
else if(rq->bRequest == USBRQ_SET_ADDRESS){ /* 5 */
usbNewDeviceAddr = rq->wValue.bytes[0];
}
|
functions
|
else if(rq->bRequest == USBRQ_GET_DESCRIPTOR){ /* 6 */
flags = USB_FLG_MSGPTR_IS_ROM | USB_FLG_USE_DEFAULT_RW;
if(rq->wValue.bytes[1] == USBDESCR_DEVICE){ /* 1 */
GET_DESCRIPTOR(USB_CFG_DESCR_PROPS_DEVICE, usbDescriptorDevice)
}
|
functions
|
else if(rq->wValue.bytes[1] == USBDESCR_CONFIG){ /* 2 */
GET_DESCRIPTOR(USB_CFG_DESCR_PROPS_CONFIGURATION, usbDescriptorConfiguration)
}
|
functions
|
else if(rq->wValue.bytes[1] == USBDESCR_STRING){ /* 3 */
#if USB_CFG_DESCR_PROPS_STRINGS & USB_PROP_IS_DYNAMIC
if(USB_CFG_DESCR_PROPS_STRINGS & USB_PROP_IS_RAM)
flags &= ~USB_FLG_MSGPTR_IS_ROM;
replyLen = usbFunctionDescriptor(rq);
#else /* USB_CFG_DESCR_PROPS_STRINGS & USB_PROP_IS_DYNAMIC */
if(rq->wValue.bytes[0] == 0){ /* descriptor index */
GET_DESCRIPTOR(USB_CFG_DESCR_PROPS_STRING_0, usbDescriptorString0)
}
|
functions
|
else if(rq->wValue.bytes[0] == 1){
GET_DESCRIPTOR(USB_CFG_DESCR_PROPS_STRING_VENDOR, usbDescriptorStringVendor)
}
|
functions
|
else if(rq->wValue.bytes[0] == 2){
GET_DESCRIPTOR(USB_CFG_DESCR_PROPS_STRING_PRODUCT, usbDescriptorStringDevice)
}
|
functions
|
else if(rq->wValue.bytes[0] == 3){
GET_DESCRIPTOR(USB_CFG_DESCR_PROPS_STRING_SERIAL_NUMBER, usbDescriptorStringSerialNumber)
}
|
functions
|
else if(USB_CFG_DESCR_PROPS_UNKNOWN & USB_PROP_IS_DYNAMIC){
replyLen = usbFunctionDescriptor(rq);
}
|
functions
|
else if(rq->wValue.bytes[1] == USBDESCR_HID){ /* 0x21 */
GET_DESCRIPTOR(USB_CFG_DESCR_PROPS_HID, usbDescriptorConfiguration + 18)
}
|
functions
|
else if(rq->wValue.bytes[1] == USBDESCR_HID_REPORT){ /* 0x22 */
GET_DESCRIPTOR(USB_CFG_DESCR_PROPS_HID_REPORT, usbDescriptorHidReport)
#endif /* USB_CFG_DESCR_PROPS_HID_REPORT */
}
|
functions
|
else if(USB_CFG_DESCR_PROPS_UNKNOWN & USB_PROP_IS_DYNAMIC){
replyLen = usbFunctionDescriptor(rq);
}
|
functions
|
else if(rq->bRequest == USBRQ_GET_CONFIGURATION){ /* 8 */
replyData = &usbConfiguration; /* send current configuration value */
SET_REPLY_LEN(1);
}
|
functions
|
else if(rq->bRequest == USBRQ_SET_CONFIGURATION){ /* 9 */
usbConfiguration = rq->wValue.bytes[0];
#if USB_CFG_IMPLEMENT_HALT
usbTxLen1 = USBPID_NAK;
#endif
}
|
functions
|
else if(rq->bRequest == USBRQ_GET_INTERFACE){ /* 10 */
SET_REPLY_LEN(1);
#if USB_CFG_HAVE_INTRIN_ENDPOINT
}
|
functions
|
else if(rq->bRequest == USBRQ_SET_INTERFACE){ /* 11 */
USB_SET_DATATOKEN1(USB_INITIAL_DATATOKEN); /* reset data toggling for interrupt endpoint */
# if USB_CFG_HAVE_INTRIN_ENDPOINT3
USB_SET_DATATOKEN3(USB_INITIAL_DATATOKEN); /* reset data toggling for interrupt endpoint */
# endif
# if USB_CFG_IMPLEMENT_HALT
usbTxLen1 = USBPID_NAK;
}
|
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