type stringclasses 5
values | content stringlengths 9 163k |
|---|---|
functions | int drm_dp_get_phy_test_pattern(struct drm_dp_aux *aux,
struct drm_dp_phy_test_params *data)
{
int err;
u8 rate, lanes;
err = drm_dp_dpcd_readb(aux, DP_TEST_LINK_RATE, &rate);
if (err < 0)
return err;
data->link_rate = drm_dp_bw_code_to_link_rate(rate);
err = drm_dp_dpcd_readb(aux, DP_TEST_LANE_COUNT, &la... |
functions | int drm_dp_set_phy_test_pattern(struct drm_dp_aux *aux,
struct drm_dp_phy_test_params *data, u8 dp_rev)
{
int err, i;
u8 link_config[2];
u8 test_pattern;
link_config[0] = drm_dp_link_rate_to_bw_code(data->link_rate);
link_config[1] = data->num_lanes;
if (data->enhanced_frame_cap)
link_config[1] |= DP_LANE_... |
functions | void drm_dp_vsc_sdp_log(const char *level, struct device *dev,
const struct drm_dp_vsc_sdp *vsc)
{
DP_SDP_LOG("DP SDP: %s, revision %u, length %u\n", "VSC",
vsc->revision, vsc->length);
DP_SDP_LOG(" pixelformat: %s\n",
dp_pixelformat_get_name(vsc->pixelformat));
DP_SDP_LOG(" colorimetry: %s\n",
... |
includes |
#include <linux/delay.h> |
includes | #include <linux/sched.h> |
includes | #include <mach/socinfo.h> |
defines |
#define _SET(_shift, _val) ((_val) << (_shift)) |
defines | #define VBIF_PERF_MASK (VBIF_PERF_CNT_0 | VBIF_PERF_PWR_CNT_0) |
defines | #define RBBM_PERF_ENABLE_MASK (RBBM_RBBM_CTL_ENABLE_PWR_CTR1) |
defines | #define RBBM_PERF_RESET_MASK (RBBM_RBBM_CTL_RESET_PWR_CTR1) |
defines | #define ALU_SHADOW_SIZE (8*1024) /* 8KB */ |
defines | #define REG_SHADOW_SIZE (4*1024) /* 4KB */ |
defines | #define CMD_BUFFER_SIZE (5*1024) /* 5KB */ |
defines | #define TEX_SIZE_MEM_OBJECTS 896 /* bytes */ |
defines | #define TEX_SIZE_MIPMAP 1936 /* bytes */ |
defines | #define TEX_SIZE_SAMPLER_OBJ 256 /* bytes */ |
defines | #define TEX_SHADOW_SIZE \ |
defines | #define SHADER_SHADOW_SIZE (8*1024) /* 8KB */ |
defines | #define CONTEXT_SIZE \ |
defines | #define REG_OFFSET ALU_SHADOW_SIZE |
defines | #define CMD_OFFSET (REG_OFFSET+REG_SHADOW_SIZE) |
defines | #define SHADER_OFFSET (CMD_OFFSET+CMD_BUFFER_SIZE) |
defines | #define TEX_OFFSET (SHADER_OFFSET+SHADER_SHADOW_SIZE) |
defines | #define VS_TEX_OFFSET_MEM_OBJECTS TEX_OFFSET |
defines | #define VS_TEX_OFFSET_MIPMAP (VS_TEX_OFFSET_MEM_OBJECTS+TEX_SIZE_MEM_OBJECTS) |
defines | #define VS_TEX_OFFSET_SAMPLER_OBJ (VS_TEX_OFFSET_MIPMAP+TEX_SIZE_MIPMAP) |
defines | #define FS_TEX_OFFSET_MEM_OBJECTS \ |
defines | #define FS_TEX_OFFSET_MIPMAP (FS_TEX_OFFSET_MEM_OBJECTS+TEX_SIZE_MEM_OBJECTS) |
defines | #define FS_TEX_OFFSET_SAMPLER_OBJ (FS_TEX_OFFSET_MIPMAP+TEX_SIZE_MIPMAP) |
defines | #define SSIZE (16*1024) |
defines |
#define HLSQ_SAMPLER_OFFSET 0x000 |
defines | #define HLSQ_MEMOBJ_OFFSET 0x400 |
defines | #define HLSQ_MIPMAP_OFFSET 0x800 |
defines | #define HLSQ_SHADOW_BASE (0x10000+SSIZE*2) |
defines |
#define REG_TO_MEM_LOOP_COUNT_SHIFT 18 |
defines |
#define BUILD_PC_DRAW_INITIATOR(prim_type, source_select, index_size, \ |
defines |
#define GLOBAL_REGISTER_COUNT ARRAY_SIZE(global_registers) |
defines |
#define A3XX_IRQ_CALLBACK(_c) { .func = _c } |
defines |
#define A3XX_INT_MASK \ |
structs | struct a3xx_vbif_data {
unsigned int reg;
unsigned int val;
}; |
functions | void build_regconstantsave_cmds(struct adreno_device *adreno_dev,
struct adreno_context *drawctxt)
{
unsigned int *cmd = tmp_ctx.cmd;
unsigned int *start;
unsigned int i;
drawctxt->constant_save_commands[0].hostptr = cmd;
drawctxt->constant_save_commands[0].gpuaddr =
virt2gpu(cmd, &drawctxt->gpust... |
functions | int adreno_a3xx_rbbm_clock_ctl_default(struct adreno_device
*adreno_dev)
{
if (adreno_is_a305(adreno_dev))
return A305_RBBM_CLOCK_CTL_DEFAULT;
else if (adreno_is_a305c(adreno_dev))
return A305C_RBBM_CLOCK_CTL_DEFAULT;
else if (adreno_is_a320(adreno_dev))
return A320_RBBM_CLOCK_CTL_DEFAULT;
else if (adr... |
functions | void build_shader_save_cmds(struct adreno_device *adreno_dev,
struct adreno_context *drawctxt)
{
unsigned int *cmd = tmp_ctx.cmd;
unsigned int *start;
/* Reserve space for boolean values used for COND_EXEC packet */
drawctxt->cond_execs[0].hostptr = cmd;
drawctxt->cond_execs[0].gpuaddr = virt2gpu(cmd, &dra... |
functions | void build_save_fixup_cmds(struct adreno_device *adreno_dev,
struct adreno_context *drawctxt)
{
unsigned int *cmd = tmp_ctx.cmd;
unsigned int *start = cmd;
/* Flush HLSQ lazy updates */
*cmd++ = cp_type3_packet(CP_EVENT_WRITE, 1);
*cmd++ = 0x7; /* HLSQ_FLUSH */
*cmd++ = cp_type3_packet(CP_WAIT_FOR_IDLE, 1... |
functions | void build_regrestore_cmds(struct adreno_device *adreno_dev,
struct adreno_context *drawctxt)
{
unsigned int *start = tmp_ctx.cmd;
unsigned int *cmd = start;
unsigned int *lcc_start;
int i;
/* Flush HLSQ lazy updates */
*cmd++ = cp_type3_packet(CP_EVENT_WRITE, 1);
*cmd++ = 0x7; /* HLSQ_FLUSH */
*cmd++ ... |
functions | void build_constantrestore_cmds(struct adreno_device *adreno_dev,
struct adreno_context *drawctxt)
{
unsigned int *cmd = tmp_ctx.cmd;
unsigned int *start = cmd;
unsigned int mode = 4; /* Indirect mode */
unsigned int stateblock;
unsigned int numunits;
unsigned int statetype;
drawctxt->cond_execs[2].h... |
functions | void build_shader_restore_cmds(struct adreno_device *adreno_dev,
struct adreno_context *drawctxt)
{
unsigned int *cmd = tmp_ctx.cmd;
unsigned int *start = cmd;
/* Vertex shader */
*cmd++ = cp_type3_packet(CP_COND_EXEC, 4);
*cmd++ = drawctxt->cond_execs[0].gpuaddr >> 2;
*cmd++ = drawctxt->cond_execs[0].... |
functions | void build_hlsqcontrol_restore_cmds(struct adreno_device *adreno_dev,
struct adreno_context *drawctxt)
{
unsigned int *cmd = tmp_ctx.cmd;
unsigned int *start = cmd;
*cmd++ = cp_type3_packet(CP_SET_CONSTANT, 2);
*cmd++ = CP_REG(A3XX_HLSQ_CONTROL_0_REG);
drawctxt->hlsqcontrol_restore_commands[0].hostptr = c... |
functions | void build_restore_fixup_cmds(struct adreno_device *adreno_dev,
struct adreno_context *drawctxt)
{
unsigned int *cmd = tmp_ctx.cmd;
unsigned int *start = cmd;
#ifdef GSL_CONTEXT_SWITCH_CPU_SYNC
/* Save shader sizes */
*cmd++ = cp_type3_packet(CP_REG_TO_MEM, 2);
*cmd++ = A3XX_SP_VS_CTRL_REG0;
*cmd++ = dr... |
functions | int a3xx_create_gpustate_shadow(struct adreno_device *adreno_dev,
struct adreno_context *drawctxt)
{
build_regrestore_cmds(adreno_dev, drawctxt);
build_constantrestore_cmds(adreno_dev, drawctxt);
build_hlsqcontrol_restore_cmds(adreno_dev, drawctxt);
build_regconstantsave_cmds(adreno_dev, drawctxt);
build_... |
functions | int a3xx_create_gmem_shadow(struct adreno_device *adreno_dev,
struct adreno_context *drawctxt)
{
int result;
calc_gmemsize(&drawctxt->context_gmem_shadow, adreno_dev->gmem_size);
tmp_ctx.gmem_base = adreno_dev->gmem_base;
result = kgsl_allocate(&(adreno_dev->dev),
&drawctxt->context_gmem_shadow.gmemshadow,... |
functions | void a3xx_drawctxt_detach(struct adreno_context *drawctxt)
{
kgsl_sharedmem_free(&drawctxt->gpustate);
kgsl_sharedmem_free(&drawctxt->context_gmem_shadow.gmemshadow);
} |
functions | int a3xx_drawctxt_create(struct adreno_device *adreno_dev,
struct adreno_context *drawctxt)
{
int ret;
/*
* Nothing to do here if the context is using preambles and doesn't need
* GMEM save/restore
*/
if ((drawctxt->base.flags & KGSL_CONTEXT_PREAMBLE) &&
(drawctxt->base.flags & KGSL_CONTEXT_NO_GMEM_ALLOC))... |
functions | int a3xx_drawctxt_save(struct adreno_device *adreno_dev,
struct adreno_context *context)
{
struct kgsl_device *device = &adreno_dev->dev;
int ret;
if (context->state == ADRENO_CONTEXT_STATE_INVALID)
return 0;
if (!(context->base.flags & KGSL_CONTEXT_PREAMBLE)) {
/* Fixup self modifying IBs for save oper... |
functions | int a3xx_drawctxt_restore(struct adreno_device *adreno_dev,
struct adreno_context *context)
{
struct kgsl_device *device = &adreno_dev->dev;
int ret;
/* do the common part */
ret = adreno_context_restore(adreno_dev, context);
if (ret)
return ret;
/*
* Restore GMEM. (note: changes shader.
* Shade... |
functions | int adreno_a3xx_pwron_fixup_init(struct adreno_device *adreno_dev)
{
unsigned int *cmds;
int count = ARRAY_SIZE(_a3xx_pwron_fixup_fs_instructions);
int ret;
/* Return if the fixup is already in place */
if (test_bit(ADRENO_DEVICE_PWRON_FIXUP, &adreno_dev->priv))
return 0;
ret = kgsl_allocate_contiguous(&adren... |
functions | int a3xx_rb_init(struct adreno_device *adreno_dev,
struct adreno_ringbuffer *rb)
{
unsigned int *cmds, cmds_gpu;
cmds = adreno_ringbuffer_allocspace(rb, NULL, 18);
if (cmds == NULL)
return -ENOMEM;
cmds_gpu = rb->buffer_desc.gpuaddr + sizeof(uint) * (rb->wptr - 18);
GSL_RB_WRITE(rb->device, cmds, cmds_gpu,... |
functions | void a3xx_err_callback(struct adreno_device *adreno_dev, int bit)
{
struct kgsl_device *device = &adreno_dev->dev;
const char *err = "";
switch (bit) {
case A3XX_INT_RBBM_AHB_ERROR: {
unsigned int reg;
kgsl_regread(device, A3XX_RBBM_AHB_ERROR_STATUS, ®);
/*
* Return the word address of the erroring r... |
functions | void a3xx_cp_callback(struct adreno_device *adreno_dev, int irq)
{
struct kgsl_device *device = &adreno_dev->dev;
device->pwrctrl.irq_last = 1;
queue_work(device->work_queue, &device->ts_expired_ws);
adreno_dispatcher_schedule(device);
} |
functions | int a3xx_perfcounter_enable_pwr(struct kgsl_device *device,
unsigned int counter)
{
unsigned int in, out;
if (counter > 1)
return -EINVAL;
kgsl_regread(device, A3XX_RBBM_RBBM_CTL, &in);
if (counter == 0)
out = in | RBBM_RBBM_CTL_RESET_PWR_CTR0;
else
out = in | RBBM_RBBM_CTL_RESET_PWR_CTR1;
kgsl_regwrit... |
functions | int a3xx_perfcounter_enable_vbif(struct kgsl_device *device,
unsigned int counter,
unsigned int countable)
{
unsigned int in, out, bit, sel;
if (counter > 1 || countable > 0x7f)
return -EINVAL;
kgsl_regread(device, A3XX_VBIF_PERF_CNT_EN, &in);
kgsl_regread(device, A3XX_VBIF_PERF_CNT_SEL, &sel);
if... |
functions | int a3xx_perfcounter_enable_vbif_pwr(struct kgsl_device *device,
unsigned int counter)
{
unsigned int in, out, bit;
if (counter > 2)
return -EINVAL;
kgsl_regread(device, A3XX_VBIF_PERF_CNT_EN, &in);
if (counter == 0)
bit = VBIF_PERF_PWR_CNT_0;
else if (counter == 1)
bit = VBIF_PERF_PWR_CNT_1;
el... |
functions | int a3xx_perfcounter_enable(struct adreno_device *adreno_dev,
unsigned int group, unsigned int counter, unsigned int countable)
{
struct kgsl_device *device = &adreno_dev->dev;
struct adreno_perfcount_register *reg;
/* Special cases */
if (group == KGSL_PERFCOUNTER_GROUP_PWR)
return a3xx_perfcounter_enable_pwr(... |
functions | uint64_t a3xx_perfcounter_read_pwr(struct adreno_device *adreno_dev,
unsigned int counter)
{
struct kgsl_device *device = &adreno_dev->dev;
struct adreno_perfcounters *counters = adreno_dev->gpudev->perfcounters;
struct adreno_perfcount_register *reg;
unsigned int in, out, lo = 0, hi = 0;
unsigned int enable_b... |
functions | uint64_t a3xx_perfcounter_read_vbif(struct adreno_device *adreno_dev,
unsigned int counter)
{
struct adreno_perfcounters *counters = adreno_dev->gpudev->perfcounters;
struct kgsl_device *device = &adreno_dev->dev;
struct adreno_perfcount_register *reg;
unsigned int in, out, lo = 0, hi = 0;
if (counter > 1)
... |
functions | uint64_t a3xx_perfcounter_read_vbif_pwr(struct adreno_device *adreno_dev,
unsigned int counter)
{
struct adreno_perfcounters *counters = adreno_dev->gpudev->perfcounters;
struct kgsl_device *device = &adreno_dev->dev;
struct adreno_perfcount_register *reg;
unsigned int in, out, lo = 0, hi = 0;
if (counter > 2... |
functions | uint64_t a3xx_perfcounter_read(struct adreno_device *adreno_dev,
unsigned int group, unsigned int counter)
{
struct kgsl_device *device = &adreno_dev->dev;
struct adreno_perfcount_register *reg;
unsigned int lo = 0, hi = 0;
unsigned int offset;
unsigned int in, out;
if (group == KGSL_PERFCOUNTER_GROUP_VBIF_PWR)... |
functions | int loadable_perfcounter_group(unsigned int groupid)
{
return ((groupid == KGSL_PERFCOUNTER_GROUP_VBIF_PWR) ||
(groupid == KGSL_PERFCOUNTER_GROUP_VBIF) ||
(groupid == KGSL_PERFCOUNTER_GROUP_PWR)) ? 0 : 1;
} |
functions | int active_countable(unsigned int countable)
{
return ((countable != KGSL_PERFCOUNTER_NOT_USED) &&
(countable != KGSL_PERFCOUNTER_BROKEN));
} |
functions | void a3xx_perfcounter_save(struct adreno_device *adreno_dev)
{
struct adreno_perfcounters *counters = adreno_dev->gpudev->perfcounters;
struct adreno_perfcount_group *group;
unsigned int regid, groupid;
for (groupid = 0; groupid < counters->group_count; groupid++) {
if (!loadable_perfcounter_group(groupid))
c... |
functions | void a3xx_perfcounter_write(struct adreno_device *adreno_dev,
unsigned int group, unsigned int counter)
{
struct kgsl_device *device = &(adreno_dev->dev);
struct adreno_perfcount_register *reg;
unsigned int val;
reg = &(adreno_dev->gpudev->perfcounters->groups[group].regs[counter]);
/* Clear the load cmd reg... |
functions | void a3xx_perfcounter_restore(struct adreno_device *adreno_dev)
{
struct kgsl_device *device = &adreno_dev->dev;
struct adreno_perfcounters *counters = adreno_dev->gpudev->perfcounters;
struct adreno_perfcount_group *group;
unsigned int regid, groupid;
for (groupid = 0; groupid < counters->group_count; groupid++)... |
functions | irqreturn_t a3xx_irq_handler(struct adreno_device *adreno_dev)
{
struct kgsl_device *device = &adreno_dev->dev;
irqreturn_t ret = IRQ_NONE;
unsigned int status, tmp;
int i;
kgsl_regread(&adreno_dev->dev, A3XX_RBBM_INT_0_STATUS, &status);
for (tmp = status, i = 0; tmp && i < ARRAY_SIZE(a3xx_irq_funcs); i++) {
... |
functions | void a3xx_irq_control(struct adreno_device *adreno_dev, int state)
{
struct kgsl_device *device = &adreno_dev->dev;
if (state)
kgsl_regwrite(device, A3XX_RBBM_INT_0_MASK, A3XX_INT_MASK);
else
kgsl_regwrite(device, A3XX_RBBM_INT_0_MASK, 0);
} |
functions | int a3xx_irq_pending(struct adreno_device *adreno_dev)
{
unsigned int status;
kgsl_regread(&adreno_dev->dev, A3XX_RBBM_INT_0_STATUS, &status);
return (status & A3XX_INT_MASK) ? 1 : 0;
} |
functions | int counter_delta(struct adreno_device *adreno_dev,
unsigned int reg, unsigned int *counter)
{
struct kgsl_device *device = &adreno_dev->dev;
unsigned int val;
unsigned int ret = 0;
/* Read the value */
if (reg == ADRENO_REG_RBBM_PERFCTR_PWR_1_LO)
adreno_readreg(adreno_dev, reg, &val);
else
kgsl_regread(d... |
functions | void a3xx_busy_cycles(struct adreno_device *adreno_dev,
struct adreno_busy_data *data)
{
struct adreno_busy_data *busy = &adreno_dev->busy_data;
struct kgsl_device *device = &adreno_dev->dev;
memset(data, 0, sizeof(*data));
data->gpu_busy = counter_delta(adreno_dev,
ADRENO_REG_RBBM_PERFCTR_PWR_1_LO,
... |
functions | int _get_counter(struct adreno_device *adreno_dev,
int group, int countable, unsigned int *lo,
unsigned int *hi)
{
int ret = 0;
if (*lo == 0) {
*hi = 0;
ret = adreno_perfcounter_get(adreno_dev, group, countable,
lo, PERFCOUNTER_FLAG_KERNEL);
if (ret == 0)
*hi = *lo + 1;
else {
struct kgsl_devi... |
functions | void _put_counter(struct adreno_device *adreno_dev,
int group, int countable, unsigned int *lo,
unsigned int *hi)
{
if (*lo != 0) {
adreno_perfcounter_put(adreno_dev, group, countable,
PERFCOUNTER_FLAG_KERNEL);
} |
functions | void a3xx_fault_detect_start(struct adreno_device *adreno_dev)
{
_get_counter(adreno_dev, KGSL_PERFCOUNTER_GROUP_SP,
SP_ALU_ACTIVE_CYCLES,
&ft_detect_regs[6], &ft_detect_regs[7]);
_get_counter(adreno_dev, KGSL_PERFCOUNTER_GROUP_SP,
SP0_ICL1_MISSES,
&ft_detect_regs[8], &ft_detect_regs[9]);
_get_counter(adre... |
functions | void a3xx_fault_detect_stop(struct adreno_device *adreno_dev)
{
_put_counter(adreno_dev, KGSL_PERFCOUNTER_GROUP_SP,
SP_ALU_ACTIVE_CYCLES,
&ft_detect_regs[6], &ft_detect_regs[7]);
_put_counter(adreno_dev, KGSL_PERFCOUNTER_GROUP_SP,
SP0_ICL1_MISSES,
&ft_detect_regs[8], &ft_detect_regs[9]);
_put_counter(adren... |
functions | void a3xx_perfcounter_close(struct adreno_device *adreno_dev)
{
adreno_perfcounter_put(adreno_dev, KGSL_PERFCOUNTER_GROUP_PWR, 1,
PERFCOUNTER_FLAG_KERNEL);
adreno_perfcounter_put(adreno_dev, KGSL_PERFCOUNTER_GROUP_VBIF_PWR, 0,
PERFCOUNTER_FLAG_KERNEL);
adreno_perfcounter_put(adreno_dev, KGSL_PERFCOUNTER_GROUP_... |
functions | int a3xx_perfcounter_init(struct adreno_device *adreno_dev)
{
int ret;
struct kgsl_device *device = &adreno_dev->dev;
/* SP[3] counter is broken on a330 so disable it if a330 device */
if (adreno_is_a330(adreno_dev))
a3xx_perfcounters_sp[3].countable = KGSL_PERFCOUNTER_BROKEN;
if (adreno_dev->fast_hang_detect)
... |
functions | void a3xx_protect_init(struct kgsl_device *device)
{
int index = 0;
/* enable access protection to privileged registers */
kgsl_regwrite(device, A3XX_CP_PROTECT_CTRL, 0x00000007);
/* RBBM registers */
adreno_set_protected_registers(device, &index, 0x18, 0);
adreno_set_protected_registers(device, &index, 0x20, 2... |
functions | void a3xx_start(struct adreno_device *adreno_dev)
{
struct kgsl_device *device = &adreno_dev->dev;
struct a3xx_vbif_data *vbif = NULL;
int i;
for (i = 0; i < ARRAY_SIZE(a3xx_vbif_platforms); i++) {
if (a3xx_vbif_platforms[i].devfunc(adreno_dev)) {
vbif = a3xx_vbif_platforms[i].vbif;
break;
} |
functions | int a3xx_coresight_enable(struct kgsl_device *device)
{
mutex_lock(&device->mutex);
if (!kgsl_active_count_get(device)) {
kgsl_regwrite(device, A3XX_RBBM_DEBUG_BUS_CTL, 0x0001093F);
kgsl_regwrite(device, A3XX_RBBM_DEBUG_BUS_STB_CTL0,
0x00000000);
kgsl_regwrite(device, A3XX_RBBM_DEBUG_BUS_STB_CTL1,
0xFFF... |
functions | void a3xx_coresight_disable(struct kgsl_device *device)
{
mutex_lock(&device->mutex);
if (!kgsl_active_count_get(device)) {
kgsl_regwrite(device, A3XX_RBBM_DEBUG_BUS_CTL, 0x0);
kgsl_regwrite(device, A3XX_RBBM_DEBUG_BUS_STB_CTL0, 0x0);
kgsl_regwrite(device, A3XX_RBBM_DEBUG_BUS_STB_CTL1, 0x0);
kgsl_regwrite(dev... |
functions | void a3xx_coresight_write_reg(struct kgsl_device *device,
unsigned int wordoffset, unsigned int val)
{
mutex_lock(&device->mutex);
if (!kgsl_active_count_get(device)) {
kgsl_regwrite(device, wordoffset, val);
kgsl_active_count_put(device);
} |
functions | void a3xx_coresight_config_debug_reg(struct kgsl_device *device,
int debug_reg, unsigned int val)
{
switch (debug_reg) {
case DEBUG_BUS_CTL:
a3xx_coresight_write_reg(device, A3XX_RBBM_DEBUG_BUS_CTL, val);
break;
case TRACE_STOP_CNT:
a3xx_coresight_write_reg(device, A3XX_RBBM_EXT_TRACE_STOP_CNT,
val);
... |
functions | void a3xx_soft_reset(struct adreno_device *adreno_dev)
{
struct kgsl_device *device = &adreno_dev->dev;
unsigned int reg;
kgsl_regwrite(device, A3XX_RBBM_SW_RESET_CMD, 1);
/*
* Do a dummy read to get a brief read cycle delay for the reset to take
* effect
*/
kgsl_regread(device, A3XX_RBBM_SW_RESET_CMD, ®... |
functions | void a3xx_postmortem_dump(struct adreno_device *adreno_dev)
{
struct kgsl_device *device = &adreno_dev->dev;
unsigned int r1, r2, r3, rbbm_status;
unsigned int cp_stat, rb_count;
kgsl_regread(device, REG_RBBM_STATUS, &rbbm_status);
KGSL_LOG_DUMP(device, "RBBM: STATUS = %08X\n", rbbm_status);
{
struct log_... |
includes | #include <linux/export.h> |
includes | #include <linux/kernel.h> |
includes | #include <linux/stddef.h> |
includes | #include <linux/ioport.h> |
includes | #include <linux/delay.h> |
includes | #include <linux/utsname.h> |
includes | #include <linux/initrd.h> |
includes | #include <linux/console.h> |
includes | #include <linux/bootmem.h> |
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