type stringclasses 5
values | content stringlengths 9 163k |
|---|---|
functions | int kvm_get_mce_cap_supported(KVMState *s, uint64_t *mce_cap,
int *max_banks)
{
int r;
r = kvm_check_extension(s, KVM_CAP_MCE);
if (r > 0) {
*max_banks = r;
return kvm_ioctl(s, KVM_X86_GET_MCE_CAP_SUPPORTED, mce_cap);
} |
functions | void kvm_mce_inject(X86CPU *cpu, hwaddr paddr, int code)
{
CPUX86State *env = &cpu->env;
uint64_t status = MCI_STATUS_VAL | MCI_STATUS_UC | MCI_STATUS_EN |
MCI_STATUS_MISCV | MCI_STATUS_ADDRV | MCI_STATUS_S;
uint64_t mcg_status = MCG_STATUS_MCIP;
if (code == BUS_MCEERR_AR) {
... |
functions | void hardware_memory_error(void)
{
fprintf(stderr, "Hardware memory error!\n");
exit(1);
} |
functions | int kvm_arch_on_sigbus_vcpu(CPUX86State *env, int code, void *addr)
{
X86CPU *cpu = x86_env_get_cpu(env);
ram_addr_t ram_addr;
hwaddr paddr;
if ((env->mcg_cap & MCG_SER_P) && addr
&& (code == BUS_MCEERR_AR || code == BUS_MCEERR_AO)) {
if (qemu_ram_addr_from_host(addr, &ram_addr) ||
... |
functions | else if (code == BUS_MCEERR_AR) {
hardware_memory_error();
} |
functions | int kvm_arch_on_sigbus(int code, void *addr)
{
if ((first_cpu->mcg_cap & MCG_SER_P) && addr && code == BUS_MCEERR_AO) {
ram_addr_t ram_addr;
hwaddr paddr;
/* Hope we are lucky for AO MCE */
if (qemu_ram_addr_from_host(addr, &ram_addr) ||
!kvm_physical_memory_addr_from_ho... |
functions | else if (code == BUS_MCEERR_AR) {
hardware_memory_error();
} |
functions | int kvm_inject_mce_oldstyle(CPUX86State *env)
{
if (!kvm_has_vcpu_events() && env->exception_injected == EXCP12_MCHK) {
unsigned int bank, bank_num = env->mcg_cap & 0xff;
struct kvm_x86_mce mce;
env->exception_injected = -1;
/*
* There must be at least one bank in use if a... |
functions | void cpu_update_state(void *opaque, int running, RunState state)
{
CPUX86State *env = opaque;
if (running) {
env->tsc_valid = false;
} |
functions | int kvm_arch_init_vcpu(CPUX86State *env)
{
struct {
struct kvm_cpuid2 cpuid;
struct kvm_cpuid_entry2 entries[100];
} |
functions | void kvm_arch_reset_vcpu(CPUX86State *env)
{
X86CPU *cpu = x86_env_get_cpu(env);
env->exception_injected = -1;
env->interrupt_injected = -1;
env->xcr0 = 1;
if (kvm_irqchip_in_kernel()) {
env->mp_state = cpu_is_bsp(cpu) ? KVM_MP_STATE_RUNNABLE :
KVM_... |
functions | int kvm_get_supported_msrs(KVMState *s)
{
static int kvm_supported_msrs;
int ret = 0;
/* first time */
if (kvm_supported_msrs == 0) {
struct kvm_msr_list msr_list, *kvm_msr_list;
kvm_supported_msrs = -1;
/* Obtain MSR list from KVM. These are the MSRs that we must
* ... |
functions | int kvm_arch_init(KVMState *s)
{
QemuOptsList *list = qemu_find_opts("machine");
uint64_t identity_base = 0xfffbc000;
uint64_t shadow_mem;
int ret;
struct utsname utsname;
ret = kvm_get_supported_msrs(s);
if (ret < 0) {
return ret;
} |
functions | void set_v8086_seg(struct kvm_segment *lhs, const SegmentCache *rhs)
{
lhs->selector = rhs->selector;
lhs->base = rhs->base;
lhs->limit = rhs->limit;
lhs->type = 3;
lhs->present = 1;
lhs->dpl = 3;
lhs->db = 0;
lhs->s = 1;
lhs->l = 0;
lhs->g = 0;
lhs->avl = 0;
lhs->unusabl... |
functions | void set_seg(struct kvm_segment *lhs, const SegmentCache *rhs)
{
unsigned flags = rhs->flags;
lhs->selector = rhs->selector;
lhs->base = rhs->base;
lhs->limit = rhs->limit;
lhs->type = (flags >> DESC_TYPE_SHIFT) & 15;
lhs->present = (flags & DESC_P_MASK) != 0;
lhs->dpl = (flags >> DESC_DPL_S... |
functions | void get_seg(SegmentCache *lhs, const struct kvm_segment *rhs)
{
lhs->selector = rhs->selector;
lhs->base = rhs->base;
lhs->limit = rhs->limit;
lhs->flags = (rhs->type << DESC_TYPE_SHIFT) |
(rhs->present * DESC_P_MASK) |
(rhs->dpl << DESC_DPL_SHIFT) |
(... |
functions | void kvm_getput_reg(__u64 *kvm_reg, target_ulong *qemu_reg, int set)
{
if (set) {
*kvm_reg = *qemu_reg;
} |
functions | int kvm_getput_regs(CPUX86State *env, int set)
{
struct kvm_regs regs;
int ret = 0;
if (!set) {
ret = kvm_vcpu_ioctl(env, KVM_GET_REGS, ®s);
if (ret < 0) {
return ret;
} |
functions | int kvm_put_fpu(CPUX86State *env)
{
struct kvm_fpu fpu;
int i;
memset(&fpu, 0, sizeof fpu);
fpu.fsw = env->fpus & ~(7 << 11);
fpu.fsw |= (env->fpstt & 7) << 11;
fpu.fcw = env->fpuc;
fpu.last_opcode = env->fpop;
fpu.last_ip = env->fpip;
fpu.last_dp = env->fpdp;
for (i = 0; i < 8;... |
functions | int kvm_put_xsave(CPUX86State *env)
{
struct kvm_xsave* xsave = env->kvm_xsave_buf;
uint16_t cwd, swd, twd;
int i, r;
if (!kvm_has_xsave()) {
return kvm_put_fpu(env);
} |
functions | int kvm_put_xcrs(CPUX86State *env)
{
struct kvm_xcrs xcrs;
if (!kvm_has_xcrs()) {
return 0;
} |
functions | int kvm_put_sregs(CPUX86State *env)
{
struct kvm_sregs sregs;
memset(sregs.interrupt_bitmap, 0, sizeof(sregs.interrupt_bitmap));
if (env->interrupt_injected >= 0) {
sregs.interrupt_bitmap[env->interrupt_injected / 64] |=
(uint64_t)1 << (env->interrupt_injected % 64);
} |
functions | void kvm_msr_entry_set(struct kvm_msr_entry *entry,
uint32_t index, uint64_t value)
{
entry->index = index;
entry->data = value;
} |
functions | int kvm_put_msrs(CPUX86State *env, int level)
{
struct {
struct kvm_msrs info;
struct kvm_msr_entry entries[100];
} |
functions | TARGET_X86_64
if (lm_capable_kernel) {
kvm_msr_entry_set(&msrs[n++], MSR_CSTAR, env->cstar);
kvm_msr_entry_set(&msrs[n++], MSR_KERNELGSBASE, env->kernelgsbase);
kvm_msr_entry_set(&msrs[n++], MSR_FMASK, env->fmask);
kvm_msr_entry_set(&msrs[n++], MSR_LSTAR, env->lstar);
} |
functions | endif
if (level == KVM_PUT_FULL_STATE) {
/*
* KVM is yet unable to synchronize TSC values of multiple VCPUs on
* writeback. Until this is fixed, we only write the offset to SMP
* guests after migration, desynchronizing the VCPUs, but avoiding
* huge jump-backs that would ... |
functions | int kvm_get_fpu(CPUX86State *env)
{
struct kvm_fpu fpu;
int i, ret;
ret = kvm_vcpu_ioctl(env, KVM_GET_FPU, &fpu);
if (ret < 0) {
return ret;
} |
functions | int kvm_get_xsave(CPUX86State *env)
{
struct kvm_xsave* xsave = env->kvm_xsave_buf;
int ret, i;
uint16_t cwd, swd, twd;
if (!kvm_has_xsave()) {
return kvm_get_fpu(env);
} |
functions | int kvm_get_xcrs(CPUX86State *env)
{
int i, ret;
struct kvm_xcrs xcrs;
if (!kvm_has_xcrs()) {
return 0;
} |
functions | int kvm_get_sregs(CPUX86State *env)
{
struct kvm_sregs sregs;
uint32_t hflags;
int bit, i, ret;
ret = kvm_vcpu_ioctl(env, KVM_GET_SREGS, &sregs);
if (ret < 0) {
return ret;
} |
functions | int kvm_get_msrs(CPUX86State *env)
{
struct {
struct kvm_msrs info;
struct kvm_msr_entry entries[100];
} |
functions | TARGET_X86_64
if (lm_capable_kernel) {
msrs[n++].index = MSR_CSTAR;
msrs[n++].index = MSR_KERNELGSBASE;
msrs[n++].index = MSR_FMASK;
msrs[n++].index = MSR_LSTAR;
} |
functions | int kvm_put_mp_state(CPUX86State *env)
{
struct kvm_mp_state mp_state = { .mp_state = env->mp_state } |
functions | int kvm_get_mp_state(X86CPU *cpu)
{
CPUX86State *env = &cpu->env;
struct kvm_mp_state mp_state;
int ret;
ret = kvm_vcpu_ioctl(env, KVM_GET_MP_STATE, &mp_state);
if (ret < 0) {
return ret;
} |
functions | int kvm_get_apic(CPUX86State *env)
{
DeviceState *apic = env->apic_state;
struct kvm_lapic_state kapic;
int ret;
if (apic && kvm_irqchip_in_kernel()) {
ret = kvm_vcpu_ioctl(env, KVM_GET_LAPIC, &kapic);
if (ret < 0) {
return ret;
} |
functions | int kvm_put_apic(CPUX86State *env)
{
DeviceState *apic = env->apic_state;
struct kvm_lapic_state kapic;
if (apic && kvm_irqchip_in_kernel()) {
kvm_put_apic_state(apic, &kapic);
return kvm_vcpu_ioctl(env, KVM_SET_LAPIC, &kapic);
} |
functions | int kvm_put_vcpu_events(CPUX86State *env, int level)
{
struct kvm_vcpu_events events;
if (!kvm_has_vcpu_events()) {
return 0;
} |
functions | int kvm_get_vcpu_events(CPUX86State *env)
{
struct kvm_vcpu_events events;
int ret;
if (!kvm_has_vcpu_events()) {
return 0;
} |
functions | int kvm_guest_debug_workarounds(CPUX86State *env)
{
int ret = 0;
unsigned long reinject_trap = 0;
if (!kvm_has_vcpu_events()) {
if (env->exception_injected == 1) {
reinject_trap = KVM_GUESTDBG_INJECT_DB;
} |
functions | else if (env->exception_injected == 3) {
reinject_trap = KVM_GUESTDBG_INJECT_BP;
} |
functions | int kvm_put_debugregs(CPUX86State *env)
{
struct kvm_debugregs dbgregs;
int i;
if (!kvm_has_debugregs()) {
return 0;
} |
functions | int kvm_get_debugregs(CPUX86State *env)
{
struct kvm_debugregs dbgregs;
int i, ret;
if (!kvm_has_debugregs()) {
return 0;
} |
functions | int kvm_arch_put_registers(CPUX86State *env, int level)
{
CPUState *cpu = ENV_GET_CPU(env);
int ret;
assert(cpu_is_stopped(cpu) || qemu_cpu_is_self(cpu));
ret = kvm_getput_regs(env, 1);
if (ret < 0) {
return ret;
} |
functions | int kvm_arch_get_registers(CPUX86State *env)
{
X86CPU *cpu = x86_env_get_cpu(env);
int ret;
assert(cpu_is_stopped(CPU(cpu)) || qemu_cpu_is_self(CPU(cpu)));
ret = kvm_getput_regs(env, 0);
if (ret < 0) {
return ret;
} |
functions | void kvm_arch_pre_run(CPUX86State *env, struct kvm_run *run)
{
int ret;
/* Inject NMI */
if (env->interrupt_request & CPU_INTERRUPT_NMI) {
env->interrupt_request &= ~CPU_INTERRUPT_NMI;
DPRINTF("injected NMI\n");
ret = kvm_vcpu_ioctl(env, KVM_NMI);
if (ret < 0) {
... |
functions | void kvm_arch_post_run(CPUX86State *env, struct kvm_run *run)
{
if (run->if_flag) {
env->eflags |= IF_MASK;
} |
functions | int kvm_arch_process_async_events(CPUX86State *env)
{
X86CPU *cpu = x86_env_get_cpu(env);
if (env->interrupt_request & CPU_INTERRUPT_MCE) {
/* We must not raise CPU_INTERRUPT_MCE if it's not supported. */
assert(env->mcg_cap);
env->interrupt_request &= ~CPU_INTERRUPT_MCE;
kvm_... |
functions | int kvm_handle_halt(X86CPU *cpu)
{
CPUX86State *env = &cpu->env;
if (!((env->interrupt_request & CPU_INTERRUPT_HARD) &&
(env->eflags & IF_MASK)) &&
!(env->interrupt_request & CPU_INTERRUPT_NMI)) {
env->halted = 1;
return EXCP_HLT;
} |
functions | int kvm_handle_tpr_access(CPUX86State *env)
{
struct kvm_run *run = env->kvm_run;
apic_handle_tpr_access_report(env->apic_state, run->tpr_access.rip,
run->tpr_access.is_write ? TPR_ACCESS_WRITE
: TPR_ACCESS_READ);
... |
functions | int kvm_arch_insert_sw_breakpoint(CPUX86State *env, struct kvm_sw_breakpoint *bp)
{
static const uint8_t int3 = 0xcc;
if (cpu_memory_rw_debug(env, bp->pc, (uint8_t *)&bp->saved_insn, 1, 0) ||
cpu_memory_rw_debug(env, bp->pc, (uint8_t *)&int3, 1, 1)) {
return -EINVAL;
} |
functions | int kvm_arch_remove_sw_breakpoint(CPUX86State *env, struct kvm_sw_breakpoint *bp)
{
uint8_t int3;
if (cpu_memory_rw_debug(env, bp->pc, &int3, 1, 0) || int3 != 0xcc ||
cpu_memory_rw_debug(env, bp->pc, (uint8_t *)&bp->saved_insn, 1, 1)) {
return -EINVAL;
} |
functions | int find_hw_breakpoint(target_ulong addr, int len, int type)
{
int n;
for (n = 0; n < nb_hw_breakpoint; n++) {
if (hw_breakpoint[n].addr == addr && hw_breakpoint[n].type == type &&
(hw_breakpoint[n].len == len || len == -1)) {
return n;
} |
functions | int kvm_arch_insert_hw_breakpoint(target_ulong addr,
target_ulong len, int type)
{
switch (type) {
case GDB_BREAKPOINT_HW:
len = 1;
break;
case GDB_WATCHPOINT_WRITE:
case GDB_WATCHPOINT_ACCESS:
switch (len) {
case 1:
break;
... |
functions | int kvm_arch_remove_hw_breakpoint(target_ulong addr,
target_ulong len, int type)
{
int n;
n = find_hw_breakpoint(addr, (type == GDB_BREAKPOINT_HW) ? 1 : len, type);
if (n < 0) {
return -ENOENT;
} |
functions | void kvm_arch_remove_all_hw_breakpoints(void)
{
nb_hw_breakpoint = 0;
} |
functions | int kvm_handle_debug(CPUX86State *env,
struct kvm_debug_exit_arch *arch_info)
{
int ret = 0;
int n;
if (arch_info->exception == 1) {
if (arch_info->dr6 & (1 << 14)) {
if (env->singlestep_enabled) {
ret = EXCP_DEBUG;
} |
functions | void kvm_arch_update_guest_debug(CPUX86State *env, struct kvm_guest_debug *dbg)
{
const uint8_t type_code[] = {
[GDB_BREAKPOINT_HW] = 0x0,
[GDB_WATCHPOINT_WRITE] = 0x1,
[GDB_WATCHPOINT_ACCESS] = 0x3
} |
functions | bool host_supports_vmx(void)
{
uint32_t ecx, unused;
host_cpuid(1, 0, &unused, &unused, &ecx, &unused);
return ecx & CPUID_EXT_VMX;
} |
functions | int kvm_arch_handle_exit(CPUX86State *env, struct kvm_run *run)
{
X86CPU *cpu = x86_env_get_cpu(env);
uint64_t code;
int ret;
switch (run->exit_reason) {
case KVM_EXIT_HLT:
DPRINTF("handle_hlt\n");
ret = kvm_handle_halt(cpu);
break;
case KVM_EXIT_SET_TPR:
ret = 0... |
functions | bool kvm_arch_stop_on_emulation_error(CPUX86State *env)
{
kvm_cpu_synchronize_state(env);
return !(env->cr[0] & CR0_PE_MASK) ||
((env->segs[R_CS].selector & 3) != 3);
} |
functions | void kvm_arch_init_irq_routing(KVMState *s)
{
if (!kvm_check_extension(s, KVM_CAP_IRQ_ROUTING)) {
/* If kernel can't do irq routing, interrupt source
* override 0->2 cannot be set up as required by HPET.
* So we have to disable it.
*/
no_hpet = 1;
} |
functions | int kvm_device_pci_assign(KVMState *s, PCIHostDeviceAddress *dev_addr,
uint32_t flags, uint32_t *dev_id)
{
struct kvm_assigned_pci_dev dev_data = {
.segnr = dev_addr->domain,
.busnr = dev_addr->bus,
.devfn = PCI_DEVFN(dev_addr->slot, dev_addr->function),
.fl... |
functions | int kvm_device_pci_deassign(KVMState *s, uint32_t dev_id)
{
struct kvm_assigned_pci_dev dev_data = {
.assigned_dev_id = dev_id,
} |
functions | int kvm_assign_irq_internal(KVMState *s, uint32_t dev_id,
uint32_t irq_type, uint32_t guest_irq)
{
struct kvm_assigned_irq assigned_irq = {
.assigned_dev_id = dev_id,
.guest_irq = guest_irq,
.flags = irq_type,
} |
functions | int kvm_device_intx_assign(KVMState *s, uint32_t dev_id, bool use_host_msi,
uint32_t guest_irq)
{
uint32_t irq_type = KVM_DEV_IRQ_GUEST_INTX |
(use_host_msi ? KVM_DEV_IRQ_HOST_MSI : KVM_DEV_IRQ_HOST_INTX);
return kvm_assign_irq_internal(s, dev_id, irq_type, guest_irq);
} |
functions | int kvm_device_intx_set_mask(KVMState *s, uint32_t dev_id, bool masked)
{
struct kvm_assigned_pci_dev dev_data = {
.assigned_dev_id = dev_id,
.flags = masked ? KVM_DEV_ASSIGN_MASK_INTX : 0,
} |
functions | int kvm_deassign_irq_internal(KVMState *s, uint32_t dev_id,
uint32_t type)
{
struct kvm_assigned_irq assigned_irq = {
.assigned_dev_id = dev_id,
.flags = type,
} |
functions | int kvm_device_intx_deassign(KVMState *s, uint32_t dev_id, bool use_host_msi)
{
return kvm_deassign_irq_internal(s, dev_id, KVM_DEV_IRQ_GUEST_INTX |
(use_host_msi ? KVM_DEV_IRQ_HOST_MSI : KVM_DEV_IRQ_HOST_INTX));
} |
functions | int kvm_device_msi_assign(KVMState *s, uint32_t dev_id, int virq)
{
return kvm_assign_irq_internal(s, dev_id, KVM_DEV_IRQ_HOST_MSI |
KVM_DEV_IRQ_GUEST_MSI, virq);
} |
functions | int kvm_device_msi_deassign(KVMState *s, uint32_t dev_id)
{
return kvm_deassign_irq_internal(s, dev_id, KVM_DEV_IRQ_GUEST_MSI |
KVM_DEV_IRQ_HOST_MSI);
} |
functions | bool kvm_device_msix_supported(KVMState *s)
{
/* The kernel lacks a corresponding KVM_CAP, so we probe by calling
* KVM_ASSIGN_SET_MSIX_NR with an invalid parameter. */
return kvm_vm_ioctl(s, KVM_ASSIGN_SET_MSIX_NR, NULL) == -EFAULT;
} |
functions | int kvm_device_msix_init_vectors(KVMState *s, uint32_t dev_id,
uint32_t nr_vectors)
{
struct kvm_assigned_msix_nr msix_nr = {
.assigned_dev_id = dev_id,
.entry_nr = nr_vectors,
} |
functions | int kvm_device_msix_set_vector(KVMState *s, uint32_t dev_id, uint32_t vector,
int virq)
{
struct kvm_assigned_msix_entry msix_entry = {
.assigned_dev_id = dev_id,
.gsi = virq,
.entry = vector,
} |
functions | int kvm_device_msix_assign(KVMState *s, uint32_t dev_id)
{
return kvm_assign_irq_internal(s, dev_id, KVM_DEV_IRQ_HOST_MSIX |
KVM_DEV_IRQ_GUEST_MSIX, 0);
} |
functions | int kvm_device_msix_deassign(KVMState *s, uint32_t dev_id)
{
return kvm_deassign_irq_internal(s, dev_id, KVM_DEV_IRQ_GUEST_MSIX |
KVM_DEV_IRQ_HOST_MSIX);
} |
includes |
#include <stddef.h> |
includes | #include <asm/uaccess.h> |
includes |
#include <linux/slab.h> |
functions | IMG_INT
PVRSRVBridgePMRPDumpLoadMem(IMG_UINT32 ui32BridgeID,
PVRSRV_BRIDGE_IN_PMRPDUMPLOADMEM *psPMRPDumpLoadMemIN,
PVRSRV_BRIDGE_OUT_PMRPDUMPLOADMEM *psPMRPDumpLoadMemOUT,
CONNECTION_DATA *psConnection)
{
PMR * psPMRInt = IMG_NULL;
IMG_HANDLE hPMRInt2 = IMG_NULL;
PVRSRV_BRIDGE_ASSERT_CMD(ui32Brid... |
functions | IMG_INT
PVRSRVBridgePMRPDumpLoadMemValue32(IMG_UINT32 ui32BridgeID,
PVRSRV_BRIDGE_IN_PMRPDUMPLOADMEMVALUE32 *psPMRPDumpLoadMemValue32IN,
PVRSRV_BRIDGE_OUT_PMRPDUMPLOADMEMVALUE32 *psPMRPDumpLoadMemValue32OUT,
CONNECTION_DATA *psConnection)
{
PMR * psPMRInt = IMG_NULL;
IMG_HANDLE hPMRInt2 = IMG_NULL;
... |
functions | IMG_INT
PVRSRVBridgePMRPDumpLoadMemValue64(IMG_UINT32 ui32BridgeID,
PVRSRV_BRIDGE_IN_PMRPDUMPLOADMEMVALUE64 *psPMRPDumpLoadMemValue64IN,
PVRSRV_BRIDGE_OUT_PMRPDUMPLOADMEMVALUE64 *psPMRPDumpLoadMemValue64OUT,
CONNECTION_DATA *psConnection)
{
PMR * psPMRInt = IMG_NULL;
IMG_HANDLE hPMRInt2 = IMG_NULL;
... |
functions | IMG_INT
PVRSRVBridgePMRPDumpSaveToFile(IMG_UINT32 ui32BridgeID,
PVRSRV_BRIDGE_IN_PMRPDUMPSAVETOFILE *psPMRPDumpSaveToFileIN,
PVRSRV_BRIDGE_OUT_PMRPDUMPSAVETOFILE *psPMRPDumpSaveToFileOUT,
CONNECTION_DATA *psConnection)
{
PMR * psPMRInt = IMG_NULL;
IMG_HANDLE hPMRInt2 = IMG_NULL;
IMG_CHAR *uiFileNam... |
functions | IMG_INT
PVRSRVBridgePMRPDumpSymbolicAddr(IMG_UINT32 ui32BridgeID,
PVRSRV_BRIDGE_IN_PMRPDUMPSYMBOLICADDR *psPMRPDumpSymbolicAddrIN,
PVRSRV_BRIDGE_OUT_PMRPDUMPSYMBOLICADDR *psPMRPDumpSymbolicAddrOUT,
CONNECTION_DATA *psConnection)
{
PMR * psPMRInt = IMG_NULL;
IMG_HANDLE hPMRInt2 = IMG_NULL;
IMG_CHAR ... |
functions | IMG_INT
PVRSRVBridgePMRPDumpPol32(IMG_UINT32 ui32BridgeID,
PVRSRV_BRIDGE_IN_PMRPDUMPPOL32 *psPMRPDumpPol32IN,
PVRSRV_BRIDGE_OUT_PMRPDUMPPOL32 *psPMRPDumpPol32OUT,
CONNECTION_DATA *psConnection)
{
PMR * psPMRInt = IMG_NULL;
IMG_HANDLE hPMRInt2 = IMG_NULL;
PVRSRV_BRIDGE_ASSERT_CMD(ui32BridgeID, PVRS... |
functions | IMG_INT
PVRSRVBridgePMRPDumpCBP(IMG_UINT32 ui32BridgeID,
PVRSRV_BRIDGE_IN_PMRPDUMPCBP *psPMRPDumpCBPIN,
PVRSRV_BRIDGE_OUT_PMRPDUMPCBP *psPMRPDumpCBPOUT,
CONNECTION_DATA *psConnection)
{
PMR * psPMRInt = IMG_NULL;
IMG_HANDLE hPMRInt2 = IMG_NULL;
PVRSRV_BRIDGE_ASSERT_CMD(ui32BridgeID, PVRSRV_BRIDGE_... |
functions | IMG_INT
PVRSRVBridgeDevmemIntPDumpSaveToFileVirtual(IMG_UINT32 ui32BridgeID,
PVRSRV_BRIDGE_IN_DEVMEMINTPDUMPSAVETOFILEVIRTUAL *psDevmemIntPDumpSaveToFileVirtualIN,
PVRSRV_BRIDGE_OUT_DEVMEMINTPDUMPSAVETOFILEVIRTUAL *psDevmemIntPDumpSaveToFileVirtualOUT,
CONNECTION_DATA *psConnection)
{
DEVMEMINT_CTX *... |
functions | PVRSRV_ERROR RegisterPDUMPMMFunctions(IMG_VOID)
{
SetDispatchTableEntry(PVRSRV_BRIDGE_PDUMPMM_PMRPDUMPLOADMEM, PVRSRVBridgePMRPDumpLoadMem);
SetDispatchTableEntry(PVRSRV_BRIDGE_PDUMPMM_PMRPDUMPLOADMEMVALUE32, PVRSRVBridgePMRPDumpLoadMemValue32);
SetDispatchTableEntry(PVRSRV_BRIDGE_PDUMPMM_PMRPDUMPLOADMEMVALUE64, PVR... |
functions | IMG_VOID UnregisterPDUMPMMFunctions(IMG_VOID)
{
} |
includes |
#include <curses.priv.h> |
includes | #include <stdlib.h> |
defines |
#define WIDTH 32 |
defines | #define HEIGHT 32 |
defines |
#define TRANSFORM(v00, v01, v10, v11) \ |
defines |
#define F1 pixman_fixed_1 |
defines |
#define RANDOM_FORMAT() \ |
defines |
#define RANDOM_OP() \ |
defines |
#define RANDOM_TRANSFORM() \ |
functions | void
on_destroy (pixman_image_t *image, void *data)
{
free (data);
} |
functions | uint32_t
test_transform (int testnum, int verbose)
{
pixman_image_t *src, *dest;
uint32_t crc;
prng_srand (testnum);
src = make_image ();
dest = make_image ();
pixman_image_composite (RANDOM_OP(),
src, NULL, dest,
0, 0, 0, 0, WIDTH / 2, HEIGHT / 2,
WIDTH, HEIGHT);
... |
main | int
main (int argc, const char *argv[])
{
return fuzzer_test_main ("rotate", 15000,
0x81E9EC2F,
test_transform, argc, argv);
} |
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