type stringclasses 5
values | content stringlengths 9 163k |
|---|---|
functions | void anc_service_SetParameter(unsigned long arg)
{
if (copy_from_user((void *)(&ancserv.RegData), (const void __user *)(arg), sizeof(ancserv.RegData)))
{
return -EFAULT;
} |
functions | int anc_service_getDumpAddr(void)
{
ancserv.dumpwait = true;
while (ancserv.dumpwait)
{
msleep(ANC_WAITDUMP_INTERVAL_MS);
} |
functions | void anc_service_EnableLog(void)
{
printk("[ANC] Enable Debug Log\n");
ancserv.debugmode = true;
} |
functions | void anc_service_DisableLog(void)
{
printk("[ANC_Kernel] Disable Debug Log\n");
ancserv.debugmode = false;
} |
functions | bool anc_service_SwapToANC(void)
{
int ret;
printk("[ANC] Swap TCM to ANC group+\n");
ret = true;
if (GROUP_A != get_current_group())
{
ancserv.swapwait = true;
ancserv.swapid = GROUP_A;
// md32_prepare_swap(GROUP_A);
ret = anc_swaptcm_wait();
} |
functions | bool anc_service_SwapFromANC(void)
{
bool ret;
printk("[ANC] Swap TCM from ANC group+\n");
ret = true;
if (GROUP_BASIC != get_current_group())
{
ancserv.swapwait = true;
ancserv.swapid = GROUP_BASIC;
// md32_prepare_swap(GROUP_BASIC);
ret = anc_swaptcm_wait();
... |
functions | bool anc_service_Enable(void)
{
bool ret;
printk("[ANC_Kernel] ANC Enable+\n");
if (GROUP_A != get_current_group())
{
printk("[ANC_Kernel] ANC Enable NotANC group Fail\n");
return;
} |
functions | bool anc_service_Disable(void)
{
printk("[ANC_Kernel] ANC Disable+\n");
if (GROUP_A != get_current_group())
{
printk("[ANC_Kernel] ANC Disable NotANC group Fail\n");
return;
} |
functions | bool anc_service_Close(void)
{
printk("[ANC_Kernel] ANC Close+\n");
if (GROUP_A != get_current_group())
{
printk("[ANC_Kernel] ANC Close NotANC group Fail\n");
return;
} |
functions | long AudDrv_anc_ioctl(struct file *fp, unsigned int cmd, unsigned long arg)
{
int ret = 0;
printk("AudDrv_anc_ioctl cmd = 0x%x arg = %lu\n", cmd, arg);
switch (cmd)
{
case SET_ANC_CONTROL:
{
printk("SET_ANC_CONTROL(%d)", arg);
switch (arg)
{
... |
functions | int AudDrv_anc_probe(struct platform_device *dev)
{
int ret = 0;
printk("AudDrv_anc_probe \n");
if (ret < 0)
{
printk("AudDrv_anc_probe request_irq MT6595_AP_ANC Fail \n");
} |
functions | int AudDrv_anc_open(struct inode *inode, struct file *fp)
{
printk("AudDrv_anc_open \n");
return 0;
} |
functions | int AudDrv_anc_mod_init(void)
{
int ret = 0;
printk("+AudDrv_anc_mod_init \n");
printk("platform_device_alloc \n");
AudDrv_ANC_dev = platform_device_alloc("AudioMTKANC", -1);
if (!AudDrv_ANC_dev)
{
return -ENOMEM;
} |
functions | void AudDrv_anc_mod_exit(void)
{
printk("+AudDrv_anc_mod_exit \n");
printk("-AudDrv_anc_mod_exit \n");
} |
includes |
#include <linux/init.h> |
includes | #include <linux/err.h> |
includes | #include <linux/bug.h> |
includes | #include <linux/kernel.h> |
includes | #include <linux/module.h> |
includes | #include <linux/spinlock.h> |
includes | #include <linux/compiler.h> |
includes | #include <linux/types.h> |
includes | #include <linux/errno.h> |
includes | #include <linux/log2.h> |
includes | #include <linux/ioport.h> |
includes | #include <linux/io.h> |
includes | #include <linux/gpio/driver.h> |
includes | #include <linux/slab.h> |
includes | #include <linux/bitops.h> |
includes | #include <linux/platform_device.h> |
includes | #include <linux/mod_devicetable.h> |
includes | #include <linux/of.h> |
includes | #include <linux/of_device.h> |
functions | void bgpio_write8(void __iomem *reg, unsigned long data)
{
writeb(data, reg);
} |
functions | long bgpio_read8(void __iomem *reg)
{
return readb(reg);
} |
functions | void bgpio_write16(void __iomem *reg, unsigned long data)
{
writew(data, reg);
} |
functions | long bgpio_read16(void __iomem *reg)
{
return readw(reg);
} |
functions | void bgpio_write32(void __iomem *reg, unsigned long data)
{
writel(data, reg);
} |
functions | long bgpio_read32(void __iomem *reg)
{
return readl(reg);
} |
functions | void bgpio_write64(void __iomem *reg, unsigned long data)
{
writeq(data, reg);
} |
functions | long bgpio_read64(void __iomem *reg)
{
return readq(reg);
} |
functions | void bgpio_write16be(void __iomem *reg, unsigned long data)
{
iowrite16be(data, reg);
} |
functions | long bgpio_read16be(void __iomem *reg)
{
return ioread16be(reg);
} |
functions | void bgpio_write32be(void __iomem *reg, unsigned long data)
{
iowrite32be(data, reg);
} |
functions | long bgpio_read32be(void __iomem *reg)
{
return ioread32be(reg);
} |
functions | long bgpio_line2mask(struct gpio_chip *gc, unsigned int line)
{
if (gc->be_bits)
return BIT(gc->bgpio_bits - 1 - line);
return BIT(line);
} |
functions | int bgpio_get_set(struct gpio_chip *gc, unsigned int gpio)
{
unsigned long pinmask = bgpio_line2mask(gc, gpio);
if (gc->bgpio_dir & pinmask)
return !!(gc->read_reg(gc->reg_set) & pinmask);
else
return !!(gc->read_reg(gc->reg_dat) & pinmask);
} |
functions | int bgpio_get_set_multiple(struct gpio_chip *gc, unsigned long *mask,
unsigned long *bits)
{
unsigned long get_mask = 0;
unsigned long set_mask = 0;
int bit = 0;
while ((bit = find_next_bit(mask, gc->ngpio, bit)) != gc->ngpio) {
if (gc->bgpio_dir & BIT(bit))
set_mask |= BIT(bit);
else
get_mask |= B... |
functions | int bgpio_get(struct gpio_chip *gc, unsigned int gpio)
{
return !!(gc->read_reg(gc->reg_dat) & bgpio_line2mask(gc, gpio));
} |
functions | int bgpio_get_multiple(struct gpio_chip *gc, unsigned long *mask,
unsigned long *bits)
{
*bits = gc->read_reg(gc->reg_dat) & *mask;
return 0;
} |
functions | int bgpio_get_multiple_be(struct gpio_chip *gc, unsigned long *mask,
unsigned long *bits)
{
unsigned long readmask = 0;
unsigned long val;
int bit;
/* Create a mirrored mask */
bit = 0;
while ((bit = find_next_bit(mask, gc->ngpio, bit)) != gc->ngpio)
readmask |= bgpio_line2mask(gc, bit);
/* Read the reg... |
functions | void bgpio_set_none(struct gpio_chip *gc, unsigned int gpio, int val)
{
} |
functions | void bgpio_set(struct gpio_chip *gc, unsigned int gpio, int val)
{
unsigned long mask = bgpio_line2mask(gc, gpio);
unsigned long flags;
spin_lock_irqsave(&gc->bgpio_lock, flags);
if (val)
gc->bgpio_data |= mask;
else
gc->bgpio_data &= ~mask;
gc->write_reg(gc->reg_dat, gc->bgpio_data);
spin_unlock_irqrest... |
functions | void bgpio_set_with_clear(struct gpio_chip *gc, unsigned int gpio,
int val)
{
unsigned long mask = bgpio_line2mask(gc, gpio);
if (val)
gc->write_reg(gc->reg_set, mask);
else
gc->write_reg(gc->reg_clr, mask);
} |
functions | void bgpio_set_set(struct gpio_chip *gc, unsigned int gpio, int val)
{
unsigned long mask = bgpio_line2mask(gc, gpio);
unsigned long flags;
spin_lock_irqsave(&gc->bgpio_lock, flags);
if (val)
gc->bgpio_data |= mask;
else
gc->bgpio_data &= ~mask;
gc->write_reg(gc->reg_set, gc->bgpio_data);
spin_unlock_irq... |
functions | void bgpio_multiple_get_masks(struct gpio_chip *gc,
unsigned long *mask, unsigned long *bits,
unsigned long *set_mask,
unsigned long *clear_mask)
{
int i;
*set_mask = 0;
*clear_mask = 0;
for (i = 0; i < gc->bgpio_bits; i++) {
if (*mask == 0)
break;
if (__test_and_clear_bit(i, mas... |
functions | void bgpio_set_multiple_single_reg(struct gpio_chip *gc,
unsigned long *mask,
unsigned long *bits,
void __iomem *reg)
{
unsigned long flags;
unsigned long set_mask, clear_mask;
spin_lock_irqsave(&gc->bgpio_lock, flags);
bgpio_multiple_get_masks(gc, mask, bits, &set_mask, &clear_mask);
gc->b... |
functions | void bgpio_set_multiple(struct gpio_chip *gc, unsigned long *mask,
unsigned long *bits)
{
bgpio_set_multiple_single_reg(gc, mask, bits, gc->reg_dat);
} |
functions | void bgpio_set_multiple_set(struct gpio_chip *gc, unsigned long *mask,
unsigned long *bits)
{
bgpio_set_multiple_single_reg(gc, mask, bits, gc->reg_set);
} |
functions | void bgpio_set_multiple_with_clear(struct gpio_chip *gc,
unsigned long *mask,
unsigned long *bits)
{
unsigned long set_mask, clear_mask;
bgpio_multiple_get_masks(gc, mask, bits, &set_mask, &clear_mask);
if (set_mask)
gc->write_reg(gc->reg_set, set_mask);
if (clear_mask)
gc->write_reg(gc->reg_clr... |
functions | int bgpio_simple_dir_in(struct gpio_chip *gc, unsigned int gpio)
{
return 0;
} |
functions | int bgpio_dir_out_err(struct gpio_chip *gc, unsigned int gpio,
int val)
{
return -EINVAL;
} |
functions | int bgpio_simple_dir_out(struct gpio_chip *gc, unsigned int gpio,
int val)
{
gc->set(gc, gpio, val);
return 0;
} |
functions | int bgpio_dir_in(struct gpio_chip *gc, unsigned int gpio)
{
unsigned long flags;
spin_lock_irqsave(&gc->bgpio_lock, flags);
gc->bgpio_dir &= ~bgpio_line2mask(gc, gpio);
gc->write_reg(gc->reg_dir, gc->bgpio_dir);
spin_unlock_irqrestore(&gc->bgpio_lock, flags);
return 0;
} |
functions | int bgpio_get_dir(struct gpio_chip *gc, unsigned int gpio)
{
/* Return 0 if output, 1 of input */
return !(gc->read_reg(gc->reg_dir) & bgpio_line2mask(gc, gpio));
} |
functions | int bgpio_dir_out(struct gpio_chip *gc, unsigned int gpio, int val)
{
unsigned long flags;
gc->set(gc, gpio, val);
spin_lock_irqsave(&gc->bgpio_lock, flags);
gc->bgpio_dir |= bgpio_line2mask(gc, gpio);
gc->write_reg(gc->reg_dir, gc->bgpio_dir);
spin_unlock_irqrestore(&gc->bgpio_lock, flags);
return 0;
} |
functions | int bgpio_dir_in_inv(struct gpio_chip *gc, unsigned int gpio)
{
unsigned long flags;
spin_lock_irqsave(&gc->bgpio_lock, flags);
gc->bgpio_dir |= bgpio_line2mask(gc, gpio);
gc->write_reg(gc->reg_dir, gc->bgpio_dir);
spin_unlock_irqrestore(&gc->bgpio_lock, flags);
return 0;
} |
functions | int bgpio_dir_out_inv(struct gpio_chip *gc, unsigned int gpio, int val)
{
unsigned long flags;
gc->set(gc, gpio, val);
spin_lock_irqsave(&gc->bgpio_lock, flags);
gc->bgpio_dir &= ~bgpio_line2mask(gc, gpio);
gc->write_reg(gc->reg_dir, gc->bgpio_dir);
spin_unlock_irqrestore(&gc->bgpio_lock, flags);
return 0;
... |
functions | int bgpio_get_dir_inv(struct gpio_chip *gc, unsigned int gpio)
{
/* Return 0 if output, 1 if input */
return !!(gc->read_reg(gc->reg_dir) & bgpio_line2mask(gc, gpio));
} |
functions | int bgpio_setup_accessors(struct device *dev,
struct gpio_chip *gc,
bool byte_be)
{
switch (gc->bgpio_bits) {
case 8:
gc->read_reg = bgpio_read8;
gc->write_reg = bgpio_write8;
break;
case 16:
if (byte_be) {
gc->read_reg = bgpio_read16be;
gc->write_reg = bgpio_write16be;
} |
functions | int bgpio_setup_io(struct gpio_chip *gc,
void __iomem *dat,
void __iomem *set,
void __iomem *clr,
unsigned long flags)
{
gc->reg_dat = dat;
if (!gc->reg_dat)
return -EINVAL;
if (set && clr) {
gc->reg_set = set;
gc->reg_clr = clr;
gc->set = bgpio_set_with_clear;
gc->set_multiple = bgpi... |
functions | else if (set && !clr) {
gc->reg_set = set;
gc->set = bgpio_set_set;
gc->set_multiple = bgpio_set_multiple_set;
} |
functions | else if (flags & BGPIOF_NO_OUTPUT) {
gc->set = bgpio_set_none;
gc->set_multiple = NULL;
} |
functions | int bgpio_setup_direction(struct gpio_chip *gc,
void __iomem *dirout,
void __iomem *dirin,
unsigned long flags)
{
if (dirout && dirin) {
return -EINVAL;
} |
functions | else if (dirout) {
gc->reg_dir = dirout;
gc->direction_output = bgpio_dir_out;
gc->direction_input = bgpio_dir_in;
gc->get_direction = bgpio_get_dir;
} |
functions | else if (dirin) {
gc->reg_dir = dirin;
gc->direction_output = bgpio_dir_out_inv;
gc->direction_input = bgpio_dir_in_inv;
gc->get_direction = bgpio_get_dir_inv;
} |
functions | int bgpio_request(struct gpio_chip *chip, unsigned gpio_pin)
{
if (gpio_pin < chip->ngpio)
return 0;
return -EINVAL;
} |
functions | int bgpio_init(struct gpio_chip *gc, struct device *dev,
unsigned long sz, void __iomem *dat, void __iomem *set,
void __iomem *clr, void __iomem *dirout, void __iomem *dirin,
unsigned long flags)
{
int ret;
if (!is_power_of_2(sz))
return -EINVAL;
gc->bgpio_bits = sz * 8;
if (gc->bgpio_bi... |
functions | int bgpio_pdev_probe(struct platform_device *pdev)
{
struct device *dev = &pdev->dev;
struct resource *r;
void __iomem *dat;
void __iomem *set;
void __iomem *clr;
void __iomem *dirout;
void __iomem *dirin;
unsigned long sz;
unsigned long flags = 0;
int err;
struct gpio_chip *gc;
struct bgpio_pdata *pdata;
... |
includes | #include <linux/firmware.h> |
defines |
#define ARRAY_MODE(x) ((x) << GB_TILE_MODE0__ARRAY_MODE__SHIFT) |
defines | #define PIPE_CONFIG(x) ((x) << GB_TILE_MODE0__PIPE_CONFIG__SHIFT) |
defines | #define TILE_SPLIT(x) ((x) << GB_TILE_MODE0__TILE_SPLIT__SHIFT) |
defines | #define MICRO_TILE_MODE(x) ((x) << 0) |
defines | #define SAMPLE_SPLIT(x) ((x) << GB_TILE_MODE0__SAMPLE_SPLIT__SHIFT) |
defines | #define BANK_WIDTH(x) ((x) << 14) |
defines | #define BANK_HEIGHT(x) ((x) << 16) |
defines | #define MACRO_TILE_ASPECT(x) ((x) << 18) |
defines | #define NUM_BANKS(x) ((x) << 20) |
functions | int gfx_v6_0_init_microcode(struct amdgpu_device *adev)
{
const char *chip_name;
char fw_name[30];
int err;
const struct gfx_firmware_header_v1_0 *cp_hdr;
const struct rlc_firmware_header_v1_0 *rlc_hdr;
DRM_DEBUG("\n");
switch (adev->asic_type) {
case CHIP_TAHITI:
chip_name = "tahiti";
break;
case CHIP_P... |
functions | void gfx_v6_0_tiling_mode_table_init(struct amdgpu_device *adev)
{
const u32 num_tile_mode_states = ARRAY_SIZE(adev->gfx.config.tile_mode_array);
u32 reg_offset, split_equal_to_row_size, *tilemode;
memset(adev->gfx.config.tile_mode_array, 0, sizeof(adev->gfx.config.tile_mode_array));
tilemode = adev->gfx.config.ti... |
functions | else if (adev->asic_type == CHIP_OLAND) {
tilemode[0] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
PIPE_CONFIG(ADDR_SURF_P4_8x16) |
TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
NUM_BANKS(ADDR_SURF_16_BANK) |
BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
BANK_HEIGHT(A... |
functions | else if (adev->asic_type == CHIP_HAINAN) {
tilemode[0] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
PIPE_CONFIG(ADDR_SURF_P2) |
TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
MACRO_TIL... |
functions | void gfx_v6_0_select_se_sh(struct amdgpu_device *adev, u32 se_num,
u32 sh_num, u32 instance)
{
u32 data;
if (instance == 0xffffffff)
data = REG_SET_FIELD(0, GRBM_GFX_INDEX, INSTANCE_BROADCAST_WRITES, 1);
else
data = REG_SET_FIELD(0, GRBM_GFX_INDEX, INSTANCE_INDEX, instance);
if ((se_num == 0xffffffff) &... |
functions | u32 gfx_v6_0_get_rb_active_bitmap(struct amdgpu_device *adev)
{
u32 data, mask;
data = RREG32(mmCC_RB_BACKEND_DISABLE) |
RREG32(mmGC_USER_RB_BACKEND_DISABLE);
data = REG_GET_FIELD(data, GC_USER_RB_BACKEND_DISABLE, BACKEND_DISABLE);
mask = amdgpu_gfx_create_bitmask(adev->gfx.config.max_backends_per_se/
ad... |
functions | void gfx_v6_0_raster_config(struct amdgpu_device *adev, u32 *rconf)
{
switch (adev->asic_type) {
case CHIP_TAHITI:
case CHIP_PITCAIRN:
*rconf |=
(2 << PA_SC_RASTER_CONFIG__RB_XSEL2__SHIFT) |
(1 << PA_SC_RASTER_CONFIG__RB_XSEL__SHIFT) |
(2 << PA_SC_RASTER_CONFIG__PKR_MAP__SHIFT) |
(1 << PA_S... |
functions | void gfx_v6_0_write_harvested_raster_configs(struct amdgpu_device *adev,
u32 raster_config, unsigned rb_mask,
unsigned num_rb)
{
unsigned sh_per_se = max_t(unsigned, adev->gfx.config.max_sh_per_se, 1);
unsigned num_se = max_t(unsigned, adev->gfx.config.max_shader_engines, 1);
unsigned rb_per_pkr ... |
functions | void gfx_v6_0_setup_rb(struct amdgpu_device *adev)
{
int i, j;
u32 data;
u32 raster_config = 0;
u32 active_rbs = 0;
u32 rb_bitmap_width_per_sh = adev->gfx.config.max_backends_per_se /
adev->gfx.config.max_sh_per_se;
unsigned num_rb_pipes;
mutex_lock(&adev->grbm_idx_mutex);
for (i = 0; i < adev->gfx.config... |
functions | void gfx_v6_0_set_user_cu_inactive_bitmap(struct amdgpu_device *adev,
u32 bitmap)
{
u32 data;
if (!bitmap)
return;
data = bitmap << GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_CUS__SHIFT;
data &= GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_CUS_MASK;
WREG32(mmGC_USER_SHADER_ARRAY_CONFIG, data);
} |
functions | u32 gfx_v6_0_get_cu_enabled(struct amdgpu_device *adev)
{
u32 data, mask;
data = RREG32(mmCC_GC_SHADER_ARRAY_CONFIG) |
RREG32(mmGC_USER_SHADER_ARRAY_CONFIG);
mask = amdgpu_gfx_create_bitmask(adev->gfx.config.max_cu_per_sh);
return ~REG_GET_FIELD(data, CC_GC_SHADER_ARRAY_CONFIG, INACTIVE_CUS) & mask;
} |
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