type stringclasses 5
values | content stringlengths 9 163k |
|---|---|
includes | #include <linux/leds.h> |
includes | #include <linux/gpio.h> |
includes | #include <linux/rfkill.h> |
includes |
#include <mach/regs-gpio.h> |
includes | #include <mach/hardware.h> |
includes | #include <mach/h1940-latch.h> |
defines |
#define DRV_NAME "h1940-bt" |
functions | void h1940bt_enable(int on)
{
if (on) {
/* Power on the chip */
h1940_latch_control(0, H1940_LATCH_BLUETOOTH_POWER);
/* Reset the chip */
mdelay(10);
s3c2410_gpio_setpin(S3C2410_GPH(1), 1);
mdelay(10);
s3c2410_gpio_setpin(S3C2410_GPH(1), 0);
} |
functions | int h1940bt_set_block(void *data, bool blocked)
{
h1940bt_enable(!blocked);
return 0;
} |
functions | __init h1940bt_probe(struct platform_device *pdev)
{
struct rfkill *rfk;
int ret = 0;
/* Configures BT serial port GPIOs */
s3c2410_gpio_cfgpin(S3C2410_GPH(0), S3C2410_GPH0_nCTS0);
s3c2410_gpio_pullup(S3C2410_GPH(0), 1);
s3c2410_gpio_cfgpin(S3C2410_GPH(1), S3C2410_GPIO_OUTPUT);
s3c2410_gpio_pullup(S3C2410_GPH(1... |
functions | int h1940bt_remove(struct platform_device *pdev)
{
struct rfkill *rfk = platform_get_drvdata(pdev);
platform_set_drvdata(pdev, NULL);
if (rfk) {
rfkill_unregister(rfk);
rfkill_destroy(rfk);
} |
functions | __init h1940bt_init(void)
{
return platform_driver_register(&h1940bt_driver);
} |
functions | __exit h1940bt_exit(void)
{
platform_driver_unregister(&h1940bt_driver);
} |
includes |
#include <linux/module.h> |
includes | #include <linux/init.h> |
includes | #include <linux/slab.h> |
includes | #include <linux/jiffies.h> |
includes | #include <linux/i2c.h> |
includes | #include <linux/hwmon.h> |
includes | #include <linux/hwmon-sysfs.h> |
includes | #include <linux/err.h> |
includes | #include <linux/of_device.h> |
includes | #include <linux/thermal.h> |
defines |
#define MAX6650_REG_SPEED 0x00 |
defines | #define MAX6650_REG_CONFIG 0x02 |
defines | #define MAX6650_REG_GPIO_DEF 0x04 |
defines | #define MAX6650_REG_DAC 0x06 |
defines | #define MAX6650_REG_ALARM_EN 0x08 |
defines | #define MAX6650_REG_ALARM 0x0A |
defines | #define MAX6650_REG_TACH0 0x0C |
defines | #define MAX6650_REG_TACH1 0x0E |
defines | #define MAX6650_REG_TACH2 0x10 |
defines | #define MAX6650_REG_TACH3 0x12 |
defines | #define MAX6650_REG_GPIO_STAT 0x14 |
defines | #define MAX6650_REG_COUNT 0x16 |
defines |
#define MAX6650_CFG_V12 0x08 |
defines | #define MAX6650_CFG_PRESCALER_MASK 0x07 |
defines | #define MAX6650_CFG_PRESCALER_2 0x01 |
defines | #define MAX6650_CFG_PRESCALER_4 0x02 |
defines | #define MAX6650_CFG_PRESCALER_8 0x03 |
defines | #define MAX6650_CFG_PRESCALER_16 0x04 |
defines | #define MAX6650_CFG_MODE_MASK 0x30 |
defines | #define MAX6650_CFG_MODE_ON 0x00 |
defines | #define MAX6650_CFG_MODE_OFF 0x10 |
defines | #define MAX6650_CFG_MODE_CLOSED_LOOP 0x20 |
defines | #define MAX6650_CFG_MODE_OPEN_LOOP 0x30 |
defines | #define MAX6650_COUNT_MASK 0x03 |
defines |
#define MAX6650_ALRM_MAX 0x01 |
defines | #define MAX6650_ALRM_MIN 0x02 |
defines | #define MAX6650_ALRM_TACH 0x04 |
defines | #define MAX6650_ALRM_GPIO1 0x08 |
defines | #define MAX6650_ALRM_GPIO2 0x10 |
defines | #define FAN_RPM_MIN 240 |
defines | #define FAN_RPM_MAX 30000 |
defines |
#define DIV_FROM_REG(reg) (1 << ((reg) & 7)) |
defines | #define DAC_LIMIT(v12) ((v12) ? 180 : 76) |
structs | struct max6650_data {
struct i2c_client *client;
struct mutex update_lock; /* protect alarm register updates */
int nr_fans;
bool valid; /* false until following fields are valid */
unsigned long last_updated; /* in jiffies */
/* register values */
u8 speed;
u8 config;
u8 tach[4];
u8 count;
u8 dac;
u8 alar... |
functions | int dac_to_pwm(int dac, bool v12)
{
/*
* Useful range for dac is 0-180 for 12V fans and 0-76 for 5V fans.
* Lower DAC values mean higher speeds.
*/
return clamp_val(255 - (255 * dac) / DAC_LIMIT(v12), 0, 255);
} |
functions | u8 pwm_to_dac(unsigned int pwm, bool v12)
{
int limit = DAC_LIMIT(v12);
return limit - (limit * pwm) / 255;
} |
functions | int max6650_set_operating_mode(struct max6650_data *data, u8 mode)
{
int result;
u8 config = data->config;
if (mode == (config & MAX6650_CFG_MODE_MASK))
return 0;
config = (config & ~MAX6650_CFG_MODE_MASK) | mode;
result = i2c_smbus_write_byte_data(data->client, MAX6650_REG_CONFIG,
config);
if (resul... |
functions | int max6650_set_target(struct max6650_data *data, unsigned long rpm)
{
int kscale, ktach;
if (rpm == 0)
return max6650_set_operating_mode(data, MAX6650_CFG_MODE_OFF);
rpm = clamp_val(rpm, FAN_RPM_MIN, FAN_RPM_MAX);
/*
* Divide the required speed by 60 to get from rpm to rps, then
* use the datasheet equati... |
functions | ssize_t alarm_show(struct device *dev,
struct device_attribute *devattr, char *buf)
{
struct sensor_device_attribute *attr = to_sensor_dev_attr(devattr);
struct max6650_data *data = max6650_update_device(dev);
bool alarm;
if (IS_ERR(data))
return PTR_ERR(data);
alarm = data->alarm & attr->index;
if (alar... |
functions | umode_t max6650_attrs_visible(struct kobject *kobj, struct attribute *a,
int n)
{
struct device *dev = container_of(kobj, struct device, kobj);
struct max6650_data *data = dev_get_drvdata(dev);
struct device_attribute *devattr;
/*
* Hide the alarms that have not been enabled by the firmware
*/
devat... |
functions | int max6650_init_client(struct max6650_data *data,
struct i2c_client *client)
{
struct device *dev = &client->dev;
int reg;
int err;
u32 voltage;
u32 prescale;
u32 target_rpm;
if (of_property_read_u32(dev->of_node, "maxim,fan-microvolt",
&voltage))
voltage = fan_voltage;
else
voltage /= 1000... |
functions | int max6650_get_max_state(struct thermal_cooling_device *cdev,
unsigned long *state)
{
*state = 255;
return 0;
} |
functions | int max6650_get_cur_state(struct thermal_cooling_device *cdev,
unsigned long *state)
{
struct max6650_data *data = cdev->devdata;
*state = data->cooling_dev_state;
return 0;
} |
functions | int max6650_set_cur_state(struct thermal_cooling_device *cdev,
unsigned long state)
{
struct max6650_data *data = cdev->devdata;
struct i2c_client *client = data->client;
int err;
state = clamp_val(state, 0, 255);
mutex_lock(&data->update_lock);
data->dac = pwm_to_dac(state, data->config & MAX6650_CFG_V12... |
functions | int max6650_read(struct device *dev, enum hwmon_sensor_types type,
u32 attr, int channel, long *val)
{
struct max6650_data *data = max6650_update_device(dev);
int mode;
if (IS_ERR(data))
return PTR_ERR(data);
switch (type) {
case hwmon_pwm:
switch (attr) {
case hwmon_pwm_input:
*val = dac_to_pwm(data... |
functions | int max6650_write(struct device *dev, enum hwmon_sensor_types type,
u32 attr, int channel, long val)
{
struct max6650_data *data = dev_get_drvdata(dev);
int ret = 0;
u8 reg;
mutex_lock(&data->update_lock);
switch (type) {
case hwmon_pwm:
switch (attr) {
case hwmon_pwm_input:
reg = pwm_to_dac(clamp_va... |
functions | umode_t max6650_is_visible(const void *_data,
enum hwmon_sensor_types type, u32 attr,
int channel)
{
const struct max6650_data *data = _data;
if (channel && (channel >= data->nr_fans || type != hwmon_fan))
return 0;
switch (type) {
case hwmon_fan:
switch (attr) {
case hwmon_fan_input:
return ... |
functions | int max6650_probe(struct i2c_client *client)
{
struct thermal_cooling_device *cooling_dev;
struct device *dev = &client->dev;
const struct of_device_id *of_id =
of_match_device(of_match_ptr(max6650_dt_match), dev);
struct max6650_data *data;
struct device *hwmon_dev;
int err;
data = devm_kzalloc(dev, sizeof(s... |
defines |
#define TARGET_83xx |
functions | void platform_fixups(void)
{
void *soc;
dt_fixup_memory(bd.bi_memstart, bd.bi_memsize);
dt_fixup_mac_address_by_alias("ethernet0", bd.bi_enetaddr);
dt_fixup_mac_address_by_alias("ethernet1", bd.bi_enet1addr);
dt_fixup_cpu_clocks(bd.bi_intfreq, bd.bi_busfreq / 4, bd.bi_busfreq);
/* Unfortunately, the specific mo... |
functions | void platform_init(unsigned long r3, unsigned long r4, unsigned long r5,
unsigned long r6, unsigned long r7)
{
CUBOOT_INIT();
fdt_init(_dtb_start);
serial_console_init();
platform_ops.fixups = platform_fixups;
} |
structs | struct regmask {
i915_reg_t reg;
u8 graphics_ver;
}; |
functions | int request_add_sync(struct i915_request *rq, int err)
{
i915_request_get(rq);
i915_request_add(rq);
if (i915_request_wait(rq, 0, HZ / 5) < 0)
err = -EIO;
i915_request_put(rq);
return err;
} |
functions | int request_add_spin(struct i915_request *rq, struct igt_spinner *spin)
{
int err = 0;
i915_request_get(rq);
i915_request_add(rq);
if (spin && !igt_wait_for_spinner(spin, rq))
err = -ETIMEDOUT;
i915_request_put(rq);
return err;
} |
functions | void
reference_lists_init(struct intel_gt *gt, struct wa_lists *lists)
{
struct intel_engine_cs *engine;
enum intel_engine_id id;
memset(lists, 0, sizeof(*lists));
wa_init_start(&lists->gt_wa_list, "GT_REF", "global");
gt_init_workarounds(gt, &lists->gt_wa_list);
wa_init_finish(&lists->gt_wa_list);
for_each_e... |
functions | void
reference_lists_fini(struct intel_gt *gt, struct wa_lists *lists)
{
struct intel_engine_cs *engine;
enum intel_engine_id id;
for_each_engine(engine, gt, id)
intel_wa_list_free(&lists->engine[id].wa_list);
intel_wa_list_free(&lists->gt_wa_list);
} |
functions | u32
get_whitelist_reg(const struct intel_engine_cs *engine, unsigned int i)
{
i915_reg_t reg = i < engine->whitelist.count ?
engine->whitelist.list[i].reg :
RING_NOPID(engine->mmio_base);
return i915_mmio_reg_offset(reg);
} |
functions | void
print_results(const struct intel_engine_cs *engine, const u32 *results)
{
unsigned int i;
for (i = 0; i < RING_MAX_NONPRIV_SLOTS; i++) {
u32 expected = get_whitelist_reg(engine, i);
u32 actual = results[i];
pr_info("RING_NONPRIV[%d]: expected 0x%08x, found 0x%08x\n",
i, expected, actual);
} |
functions | int check_whitelist(struct intel_context *ce)
{
struct intel_engine_cs *engine = ce->engine;
struct drm_i915_gem_object *results;
struct intel_wedge_me wedge;
u32 *vaddr;
int err;
int i;
results = read_nonprivs(ce);
if (IS_ERR(results))
return PTR_ERR(results);
err = 0;
i915_gem_object_lock(results, NULL)... |
functions | int do_device_reset(struct intel_engine_cs *engine)
{
intel_gt_reset(engine->gt, engine->mask, "live_workarounds");
return 0;
} |
functions | int do_engine_reset(struct intel_engine_cs *engine)
{
return intel_engine_reset(engine, "live_workarounds");
} |
functions | int do_guc_reset(struct intel_engine_cs *engine)
{
/* Currently a no-op as the reset is handled by GuC */
return 0;
} |
functions | int
switch_to_scratch_context(struct intel_engine_cs *engine,
struct igt_spinner *spin,
struct i915_request **rq)
{
struct intel_context *ce;
int err = 0;
ce = intel_context_create(engine);
if (IS_ERR(ce))
return PTR_ERR(ce);
*rq = igt_spinner_create_request(spin, ce, MI_NOOP);
intel_context_put(ce)... |
functions | u32 reg_write(u32 old, u32 new, u32 rsvd)
{
if (rsvd == 0x0000ffff) {
old &= ~(new >> 16);
old |= new & (new >> 16);
} |
functions | bool wo_register(struct intel_engine_cs *engine, u32 reg)
{
enum intel_platform platform = INTEL_INFO(engine->i915)->platform;
int i;
if ((reg & RING_FORCE_TO_NONPRIV_ACCESS_MASK) ==
RING_FORCE_TO_NONPRIV_ACCESS_WR)
return true;
for (i = 0; i < ARRAY_SIZE(wo_registers); i++) {
if (wo_registers[i].platfo... |
functions | bool timestamp(const struct intel_engine_cs *engine, u32 reg)
{
reg = (reg - engine->mmio_base) & ~RING_FORCE_TO_NONPRIV_ACCESS_MASK;
switch (reg) {
case 0x358:
case 0x35c:
case 0x3a8:
return true;
default:
return false;
} |
functions | bool ro_register(u32 reg)
{
if ((reg & RING_FORCE_TO_NONPRIV_ACCESS_MASK) ==
RING_FORCE_TO_NONPRIV_ACCESS_RD)
return true;
return false;
} |
functions | int whitelist_writable_count(struct intel_engine_cs *engine)
{
int count = engine->whitelist.count;
int i;
for (i = 0; i < engine->whitelist.count; i++) {
u32 reg = i915_mmio_reg_offset(engine->whitelist.list[i].reg);
if (ro_register(reg))
count--;
} |
functions | int check_dirty_whitelist(struct intel_context *ce)
{
const u32 values[] = {
0x00000000,
0x01010101,
0x10100101,
0x03030303,
0x30300303,
0x05050505,
0x50500505,
0x0f0f0f0f,
0xf00ff00f,
0x10101010,
0xf0f01010,
0x30303030,
0xa0a03030,
0x50505050,
0xc0c05050,
0xf0f0f0f0,
0x11111111,
0x... |
functions | int live_dirty_whitelist(void *arg)
{
struct intel_gt *gt = arg;
struct intel_engine_cs *engine;
enum intel_engine_id id;
/* Can the user write to the whitelisted registers? */
if (GRAPHICS_VER(gt->i915) < 7) /* minimum requirement for LRI, SRM, LRM */
return 0;
for_each_engine(engine, gt, id) {
struct int... |
functions | int live_reset_whitelist(void *arg)
{
struct intel_gt *gt = arg;
struct intel_engine_cs *engine;
enum intel_engine_id id;
int err = 0;
/* If we reset the gpu, we should not lose the RING_NONPRIV */
igt_global_reset_lock(gt);
for_each_engine(engine, gt, id) {
if (engine->whitelist.count == 0)
continue;
... |
functions | int read_whitelisted_registers(struct intel_context *ce,
struct i915_vma *results)
{
struct intel_engine_cs *engine = ce->engine;
struct i915_request *rq;
int i, err = 0;
u32 srm, *cs;
rq = intel_context_create_request(ce);
if (IS_ERR(rq))
return PTR_ERR(rq);
i915_vma_lock(results);
err = i915_req... |
functions | int scrub_whitelisted_registers(struct intel_context *ce)
{
struct intel_engine_cs *engine = ce->engine;
struct i915_request *rq;
struct i915_vma *batch;
int i, err = 0;
u32 *cs;
batch = create_batch(ce->vm);
if (IS_ERR(batch))
return PTR_ERR(batch);
cs = i915_gem_object_pin_map_unlocked(batch->obj, I915_MA... |
functions | bool find_reg(struct drm_i915_private *i915,
i915_reg_t reg,
const struct regmask *tbl,
unsigned long count)
{
u32 offset = i915_mmio_reg_offset(reg);
while (count--) {
if (GRAPHICS_VER(i915) == tbl->graphics_ver &&
i915_mmio_reg_offset(tbl->reg) == offset)
return true;
tbl++;
} |
functions | bool pardon_reg(struct drm_i915_private *i915, i915_reg_t reg)
{
/* Alas, we must pardon some whitelists. Mistakes already made */
static const struct regmask pardon[] = {
{ GEN9_CTX_PREEMPT_REG, 9 } |
functions | bool result_eq(struct intel_engine_cs *engine,
u32 a, u32 b, i915_reg_t reg)
{
if (a != b && !pardon_reg(engine->i915, reg)) {
pr_err("Whitelisted register 0x%4x not context saved: A=%08x, B=%08x\n",
i915_mmio_reg_offset(reg), a, b);
return false;
} |
functions | bool writeonly_reg(struct drm_i915_private *i915, i915_reg_t reg)
{
/* Some registers do not seem to behave and our writes unreadable */
static const struct regmask wo[] = {
{ GEN9_SLICE_COMMON_ECO_CHICKEN1, 9 } |
Subsets and Splits
No community queries yet
The top public SQL queries from the community will appear here once available.