commit_title
stringlengths 13
124
| commit_body
stringlengths 0
1.9k
| release_summary
stringclasses 52
values | changes_summary
stringlengths 1
758
| release_affected_domains
stringclasses 33
values | release_affected_drivers
stringclasses 51
values | domain_of_changes
stringlengths 2
571
| language_set
stringclasses 983
values | diffstat_files
int64 1
300
| diffstat_insertions
int64 0
309k
| diffstat_deletions
int64 0
168k
| commit_diff
stringlengths 92
23.4M
| category
stringclasses 108
values | commit_hash
stringlengths 34
40
| related_people
stringlengths 0
370
| domain
stringclasses 21
values | subdomain
stringclasses 241
values | leaf_module
stringlengths 0
912
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|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
drm/amdgpu: enable freesync for a+a configs
|
some newer apus can scanout directly from gtt, that saves us from allocating another bounce buffer in vram and enables freesync in such configurations.
|
this release allows to map an uid to a different one in a mount; it also adds support for selecting the preemption model at runtime; support for a low-overhead memory error detector designed to be used in production; support for the acrn hypervisor designed for embedded systems; btrfs initial support for zoned devices, subpage blocks sizes and performance improvements; support for eager nfs writes; support for a thermal power management to control the surface temperature of embedded devices in an unified way; the napi polling can be moved to a kernel thread; and support for non-blocking path lookups. as always, there are many other features, new drivers, improvements and fixes.
|
enable freesync for a+a configs
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'cryptography', 'security', 'networking', 'architectures x86 arm risc-v powerpc mips csky s390 pa-risc c6x']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'cpu frequency scaling', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'cryptography hardware acceleration', 'pci', 'non-transparent bridge (ntb)', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'cxl (compute express link)', 'various']
|
['amdgpu ']
|
['c']
| 2
| 7
| 3
|
--- diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c - struct drm_gem_object *obj; + struct drm_gem_object *obj; + struct amdgpu_bo *bo; + uint32_t domains; - if (obj->import_attach) { + bo = gem_to_amdgpu_bo(obj); + domains = amdgpu_display_supported_domains(drm_to_adev(dev), bo->flags); + if (obj->import_attach && !(domains & amdgpu_gem_domain_gtt)) { diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c - if (bo->prime_shared_count) { + if (bo->prime_shared_count || bo->tbo.base.import_attach) {
|
Graphics
|
dd017d01c3d96e48abd6fe6ccce4ef977fb5e10b
|
christian k nig
|
drivers
|
gpu
|
amd, amdgpu, drm
|
drm/amd/pm: populate sienna cichlid default overdrive table settings
|
populate the bootup overdrive table settings.
|
this release allows to map an uid to a different one in a mount; it also adds support for selecting the preemption model at runtime; support for a low-overhead memory error detector designed to be used in production; support for the acrn hypervisor designed for embedded systems; btrfs initial support for zoned devices, subpage blocks sizes and performance improvements; support for eager nfs writes; support for a thermal power management to control the surface temperature of embedded devices in an unified way; the napi polling can be moved to a kernel thread; and support for non-blocking path lookups. as always, there are many other features, new drivers, improvements and fixes.
|
sienna cichild overdrive support
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'cryptography', 'security', 'networking', 'architectures x86 arm risc-v powerpc mips csky s390 pa-risc c6x']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'cpu frequency scaling', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'cryptography hardware acceleration', 'pci', 'non-transparent bridge (ntb)', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'cxl (compute express link)', 'various']
|
['amdgpu ']
|
['c']
| 1
| 38
| 0
|
--- diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c --- a/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c +++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c + /* + * instead of having its own buffer space and get overdrive_table copied, + * smu->od_settings just points to the actual overdrive_table + */ + smu->od_settings = &powerplay_table->overdrive_table; + +static void sienna_cichlid_dump_od_table(struct smu_context *smu, + overdrivetable_t *od_table) +{ + dev_dbg(smu->adev->dev, "od: gfxclk: (%d, %d) ", od_table->gfxclkfmin, + od_table->gfxclkfmax); + dev_dbg(smu->adev->dev, "od: uclk: (%d, %d) ", od_table->uclkfmin, + od_table->uclkfmax); +} + +static int sienna_cichlid_set_default_od_settings(struct smu_context *smu) +{ + overdrivetable_t *od_table = + (overdrivetable_t *)smu->smu_table.overdrive_table; + overdrivetable_t *boot_od_table = + (overdrivetable_t *)smu->smu_table.boot_overdrive_table; + int ret = 0; + + ret = smu_cmn_update_table(smu, smu_table_overdrive, + 0, (void *)od_table, false); + if (ret) { + dev_err(smu->adev->dev, "failed to get overdrive table! "); + return ret; + } + + memcpy(boot_od_table, od_table, sizeof(overdrivetable_t)); + + sienna_cichlid_dump_od_table(smu, od_table); + + return 0; +} + + .set_default_od_settings = sienna_cichlid_set_default_od_settings,
|
Graphics
|
aa75fa34e04c842d93a45087adac66ab3a2a7f33
|
evan quan alex deucher alexander deucher amd com
|
drivers
|
gpu
|
amd, drm, pm, smu11, swsmu
|
drm/amd/pm: enable sienna cichlid overdrive support
|
enable sienna cichlid gfxclk/uclk overdrive support.
|
this release allows to map an uid to a different one in a mount; it also adds support for selecting the preemption model at runtime; support for a low-overhead memory error detector designed to be used in production; support for the acrn hypervisor designed for embedded systems; btrfs initial support for zoned devices, subpage blocks sizes and performance improvements; support for eager nfs writes; support for a thermal power management to control the surface temperature of embedded devices in an unified way; the napi polling can be moved to a kernel thread; and support for non-blocking path lookups. as always, there are many other features, new drivers, improvements and fixes.
|
sienna cichild overdrive support
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'cryptography', 'security', 'networking', 'architectures x86 arm risc-v powerpc mips csky s390 pa-risc c6x']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'cpu frequency scaling', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'cryptography hardware acceleration', 'pci', 'non-transparent bridge (ntb)', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'cxl (compute express link)', 'various']
|
['amdgpu ']
|
['c']
| 2
| 243
| 1
|
--- diff --git a/drivers/gpu/drm/amd/pm/amdgpu_pm.c b/drivers/gpu/drm/amd/pm/amdgpu_pm.c --- a/drivers/gpu/drm/amd/pm/amdgpu_pm.c +++ b/drivers/gpu/drm/amd/pm/amdgpu_pm.c - * - maximum memory clock labeled od_mclk + * - minimum(not available for vega20 and navi1x) and maximum memory + * clock labeled od_mclk diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c --- a/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c +++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c +static bool sienna_cichlid_is_od_feature_supported(struct smu_11_0_7_overdrive_table *od_table, + enum smu_11_0_7_odfeature_cap cap) +{ + return od_table->cap[cap]; +} + +static void sienna_cichlid_get_od_setting_range(struct smu_11_0_7_overdrive_table *od_table, + enum smu_11_0_7_odsetting_id setting, + uint32_t *min, uint32_t *max) +{ + if (min) + *min = od_table->min[setting]; + if (max) + *max = od_table->max[setting]; +} + + struct smu_11_0_7_overdrive_table *od_settings = smu->od_settings; + overdrivetable_t *od_table = + (overdrivetable_t *)table_context->overdrive_table; + uint32_t min_value, max_value; + case smu_od_sclk: + if (!smu->od_enabled || !od_table || !od_settings) + break; + + if (!sienna_cichlid_is_od_feature_supported(od_settings, smu_11_0_7_odcap_gfxclk_limits)) + break; + + size += sprintf(buf + size, "od_sclk: "); + size += sprintf(buf + size, "0: %umhz 1: %umhz ", od_table->gfxclkfmin, od_table->gfxclkfmax); + break; + + case smu_od_mclk: + if (!smu->od_enabled || !od_table || !od_settings) + break; + + if (!sienna_cichlid_is_od_feature_supported(od_settings, smu_11_0_7_odcap_uclk_limits)) + break; + + size += sprintf(buf + size, "od_mclk: "); + size += sprintf(buf + size, "0: %umhz 1: %umhz ", od_table->uclkfmin, od_table->uclkfmax); + break; + + case smu_od_range: + if (!smu->od_enabled || !od_table || !od_settings) + break; + + size = sprintf(buf, "%s: ", "od_range"); + + if (sienna_cichlid_is_od_feature_supported(od_settings, smu_11_0_7_odcap_gfxclk_limits)) { + sienna_cichlid_get_od_setting_range(od_settings, smu_11_0_7_odsetting_gfxclkfmin, + &min_value, null); + sienna_cichlid_get_od_setting_range(od_settings, smu_11_0_7_odsetting_gfxclkfmax, + null, &max_value); + size += sprintf(buf + size, "sclk: %7umhz %10umhz ", + min_value, max_value); + } + + if (sienna_cichlid_is_od_feature_supported(od_settings, smu_11_0_7_odcap_uclk_limits)) { + sienna_cichlid_get_od_setting_range(od_settings, smu_11_0_7_odsetting_uclkfmin, + &min_value, null); + sienna_cichlid_get_od_setting_range(od_settings, smu_11_0_7_odsetting_uclkfmax, + null, &max_value); + size += sprintf(buf + size, "mclk: %7umhz %10umhz ", + min_value, max_value); + } + break; + +static int sienna_cichlid_od_setting_check_range(struct smu_context *smu, + struct smu_11_0_7_overdrive_table *od_table, + enum smu_11_0_7_odsetting_id setting, + uint32_t value) +{ + if (value < od_table->min[setting]) { + dev_warn(smu->adev->dev, "od setting (%d, %d) is less than the minimum allowed (%d) ", + setting, value, od_table->min[setting]); + return -einval; + } + if (value > od_table->max[setting]) { + dev_warn(smu->adev->dev, "od setting (%d, %d) is greater than the maximum allowed (%d) ", + setting, value, od_table->max[setting]); + return -einval; + } + + return 0; +} + +static int sienna_cichlid_od_edit_dpm_table(struct smu_context *smu, + enum pp_od_dpm_table_command type, + long input[], uint32_t size) +{ + struct smu_table_context *table_context = &smu->smu_table; + overdrivetable_t *od_table = + (overdrivetable_t *)table_context->overdrive_table; + struct smu_11_0_7_overdrive_table *od_settings = + (struct smu_11_0_7_overdrive_table *)smu->od_settings; + enum smu_11_0_7_odsetting_id freq_setting; + uint16_t *freq_ptr; + int i, ret = 0; + + if (!smu->od_enabled) { + dev_warn(smu->adev->dev, "overdrive is not enabled! "); + return -einval; + } + + if (!smu->od_settings) { + dev_err(smu->adev->dev, "od board limits are not set! "); + return -enoent; + } + + if (!(table_context->overdrive_table && table_context->boot_overdrive_table)) { + dev_err(smu->adev->dev, "overdrive table was not initialized! "); + return -einval; + } + + switch (type) { + case pp_od_edit_sclk_vddc_table: + if (!sienna_cichlid_is_od_feature_supported(od_settings, + smu_11_0_7_odcap_gfxclk_limits)) { + dev_warn(smu->adev->dev, "gfxclk_limits not supported! "); + return -enotsupp; + } + + for (i = 0; i < size; i += 2) { + if (i + 2 > size) { + dev_info(smu->adev->dev, "invalid number of input parameters %d ", size); + return -einval; + } + + switch (input[i]) { + case 0: + if (input[i + 1] > od_table->gfxclkfmax) { + dev_info(smu->adev->dev, "gfxclkfmin (%ld) must be <= gfxclkfmax (%u)! ", + input[i + 1], od_table->gfxclkfmax); + return -einval; + } + + freq_setting = smu_11_0_7_odsetting_gfxclkfmin; + freq_ptr = &od_table->gfxclkfmin; + break; + + case 1: + if (input[i + 1] < od_table->gfxclkfmin) { + dev_info(smu->adev->dev, "gfxclkfmax (%ld) must be >= gfxclkfmin (%u)! ", + input[i + 1], od_table->gfxclkfmin); + return -einval; + } + + freq_setting = smu_11_0_7_odsetting_gfxclkfmax; + freq_ptr = &od_table->gfxclkfmax; + break; + + default: + dev_info(smu->adev->dev, "invalid sclk_vddc_table index: %ld ", input[i]); + dev_info(smu->adev->dev, "supported indices: [0:min,1:max] "); + return -einval; + } + + ret = sienna_cichlid_od_setting_check_range(smu, od_settings, + freq_setting, input[i + 1]); + if (ret) + return ret; + + *freq_ptr = (uint16_t)input[i + 1]; + } + break; + + case pp_od_edit_mclk_vddc_table: + if (!sienna_cichlid_is_od_feature_supported(od_settings, smu_11_0_7_odcap_uclk_limits)) { + dev_warn(smu->adev->dev, "uclk_limits not supported! "); + return -enotsupp; + } + + for (i = 0; i < size; i += 2) { + if (i + 2 > size) { + dev_info(smu->adev->dev, "invalid number of input parameters %d ", size); + return -einval; + } + + switch (input[i]) { + case 0: + if (input[i + 1] > od_table->uclkfmax) { + dev_info(smu->adev->dev, "uclkfmin (%ld) must be <= uclkfmax (%u)! ", + input[i + 1], od_table->uclkfmax); + return -einval; + } + + freq_setting = smu_11_0_7_odsetting_uclkfmin; + freq_ptr = &od_table->uclkfmin; + break; + + case 1: + if (input[i + 1] < od_table->uclkfmin) { + dev_info(smu->adev->dev, "uclkfmax (%ld) must be >= uclkfmin (%u)! ", + input[i + 1], od_table->uclkfmin); + return -einval; + } + + freq_setting = smu_11_0_7_odsetting_uclkfmax; + freq_ptr = &od_table->uclkfmax; + break; + + default: + dev_info(smu->adev->dev, "invalid mclk_vddc_table index: %ld ", input[i]); + dev_info(smu->adev->dev, "supported indices: [0:min,1:max] "); + return -einval; + } + + ret = sienna_cichlid_od_setting_check_range(smu, od_settings, + freq_setting, input[i + 1]); + if (ret) + return ret; + + *freq_ptr = (uint16_t)input[i + 1]; + } + break; + + case pp_od_restore_default_table: + memcpy(table_context->overdrive_table, + table_context->boot_overdrive_table, + sizeof(overdrivetable_t)); + fallthrough; + + case pp_od_commit_dpm_table: + sienna_cichlid_dump_od_table(smu, od_table); + + ret = smu_cmn_update_table(smu, smu_table_overdrive, + 0, (void *)od_table, true); + if (ret) { + dev_err(smu->adev->dev, "failed to import overdrive table! "); + return ret; + } + break; + + default: + return -enosys; + } + + return ret; +} + + .od_edit_dpm_table = sienna_cichlid_od_edit_dpm_table,
|
Graphics
|
37a58f691551dfdff4f1035ee119c9ebdb9eb119
|
evan quan alex deucher alexander deucher amd com
|
drivers
|
gpu
|
amd, drm, pm, smu11, swsmu
|
drm/amd/pm: support overdrive vddgfx offset setting(v2)
|
this is supported by sienna cichlid, navy flounder and dimgrey cavefish. for these asics, the target voltage calculation can be illustrated by "voltage = voltage calculated from v/f curve + overdrive vddgfx offset".
|
this release allows to map an uid to a different one in a mount; it also adds support for selecting the preemption model at runtime; support for a low-overhead memory error detector designed to be used in production; support for the acrn hypervisor designed for embedded systems; btrfs initial support for zoned devices, subpage blocks sizes and performance improvements; support for eager nfs writes; support for a thermal power management to control the surface temperature of embedded devices in an unified way; the napi polling can be moved to a kernel thread; and support for non-blocking path lookups. as always, there are many other features, new drivers, improvements and fixes.
|
sienna cichild overdrive support
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'cryptography', 'security', 'networking', 'architectures x86 arm risc-v powerpc mips csky s390 pa-risc c6x']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'cpu frequency scaling', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'cryptography hardware acceleration', 'pci', 'non-transparent bridge (ntb)', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'cxl (compute express link)', 'various']
|
['amdgpu ']
|
['h', 'c']
| 4
| 70
| 2
|
--- diff --git a/drivers/gpu/drm/amd/include/kgd_pp_interface.h b/drivers/gpu/drm/amd/include/kgd_pp_interface.h --- a/drivers/gpu/drm/amd/include/kgd_pp_interface.h +++ b/drivers/gpu/drm/amd/include/kgd_pp_interface.h - pp_od_commit_dpm_table + pp_od_commit_dpm_table, + pp_od_edit_vddgfx_offset diff --git a/drivers/gpu/drm/amd/pm/amdgpu_pm.c b/drivers/gpu/drm/amd/pm/amdgpu_pm.c --- a/drivers/gpu/drm/amd/pm/amdgpu_pm.c +++ b/drivers/gpu/drm/amd/pm/amdgpu_pm.c + * - voltage offset(in mv) applied on target voltage calculation. + * this is available for sienna cichlid, navy flounder and dimgrey + * cavefish. for these asics, the target voltage calculation can be + * illustrated by "voltage = voltage calculated from v/f curve + + * overdrive vddgfx offset" + * + * to update the voltage offset applied for gfxclk/voltage calculation, + * enter the new value by writing a string that contains "vo offset". + * this is supported by sienna cichlid, navy flounder and dimgrey cavefish. + * and the offset can be a positive or negative value. + * + else if (!strncmp(buf, "vo", 2)) + type = pp_od_edit_vddgfx_offset; - if (type == pp_od_edit_vddc_curve) + if ((type == pp_od_edit_vddc_curve) || + (type == pp_od_edit_vddgfx_offset)) + size += smu_print_clk_levels(&adev->smu, smu_od_vddgfx_offset, buf+size); diff --git a/drivers/gpu/drm/amd/pm/inc/smu_types.h b/drivers/gpu/drm/amd/pm/inc/smu_types.h --- a/drivers/gpu/drm/amd/pm/inc/smu_types.h +++ b/drivers/gpu/drm/amd/pm/inc/smu_types.h + smu_od_vddgfx_offset, diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c --- a/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c +++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c + uint32_t smu_version; + case smu_od_vddgfx_offset: + if (!smu->od_enabled || !od_table || !od_settings) + break; + + /* + * od gfx voltage offset functionality is supported only by 58.41.0 + * and onwards smu firmwares. + */ + smu_cmn_get_smc_version(smu, null, &smu_version); + if ((adev->asic_type == chip_sienna_cichlid) && + (smu_version < 0x003a2900)) + break; + + size += sprintf(buf + size, "od_vddgfx_offset: "); + size += sprintf(buf + size, "%dmv ", od_table->vddgfxoffset); + break; + + struct amdgpu_device *adev = smu->adev; + uint32_t smu_version; + + + smu_cmn_get_smc_version(smu, null, &smu_version); + if (!((adev->asic_type == chip_sienna_cichlid) && + (smu_version < 0x003a2900))) + dev_dbg(smu->adev->dev, "od: vddgfxoffset: %d ", od_table->vddgfxoffset); + struct amdgpu_device *adev = smu->adev; + uint32_t smu_version; + case pp_od_edit_vddgfx_offset: + if (size != 1) { + dev_info(smu->adev->dev, "invalid number of parameters: %d ", size); + return -einval; + } + + /* + * od gfx voltage offset functionality is supported only by 58.41.0 + * and onwards smu firmwares. + */ + smu_cmn_get_smc_version(smu, null, &smu_version); + if ((adev->asic_type == chip_sienna_cichlid) && + (smu_version < 0x003a2900)) { + dev_err(smu->adev->dev, "od gfx voltage offset functionality is supported " + "only by 58.41.0 and onwards smu firmwares! "); + return -eopnotsupp; + } + + od_table->vddgfxoffset = (int16_t)input[0]; + + sienna_cichlid_dump_od_table(smu, od_table); + break; +
|
Graphics
|
a2b6df4fd6e3c0ba088b00fc00579dac263b0a64
|
evan quan
|
drivers
|
gpu
|
amd, drm, inc, include, pm, smu11, swsmu
|
drm/amd/display: check plane scaling against format specific hw plane caps.
|
this takes hw constraints specific to pixel formats into account, e.g., the inability of older hw to scale fp16 format framebuffers.
|
this release allows to map an uid to a different one in a mount; it also adds support for selecting the preemption model at runtime; support for a low-overhead memory error detector designed to be used in production; support for the acrn hypervisor designed for embedded systems; btrfs initial support for zoned devices, subpage blocks sizes and performance improvements; support for eager nfs writes; support for a thermal power management to control the surface temperature of embedded devices in an unified way; the napi polling can be moved to a kernel thread; and support for non-blocking path lookups. as always, there are many other features, new drivers, improvements and fixes.
|
fp16 on dce8-11 support
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'cryptography', 'security', 'networking', 'architectures x86 arm risc-v powerpc mips csky s390 pa-risc c6x']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'cpu frequency scaling', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'cryptography hardware acceleration', 'pci', 'non-transparent bridge (ntb)', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'cxl (compute express link)', 'various']
|
['amdgpu ']
|
['c']
| 1
| 73
| 8
|
--- diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +static void get_min_max_dc_plane_scaling(struct drm_device *dev, + struct drm_framebuffer *fb, + int *min_downscale, int *max_upscale) +{ + struct amdgpu_device *adev = drm_to_adev(dev); + struct dc *dc = adev->dm.dc; + /* caps for all supported planes are the same on dce and dcn 1 - 3 */ + struct dc_plane_cap *plane_cap = &dc->caps.planes[0]; + + switch (fb->format->format) { + case drm_format_p010: + case drm_format_nv12: + case drm_format_nv21: + *max_upscale = plane_cap->max_upscale_factor.nv12; + *min_downscale = plane_cap->max_downscale_factor.nv12; + break; + + case drm_format_xrgb16161616f: + case drm_format_argb16161616f: + case drm_format_xbgr16161616f: + case drm_format_abgr16161616f: + *max_upscale = plane_cap->max_upscale_factor.fp16; + *min_downscale = plane_cap->max_downscale_factor.fp16; + break; + + default: + *max_upscale = plane_cap->max_upscale_factor.argb8888; + *min_downscale = plane_cap->max_downscale_factor.argb8888; + break; + } + + /* + * a factor of 1 in the plane_cap means to not allow scaling, ie. use a + * scaling factor of 1.0 == 1000 units. + */ + if (*max_upscale == 1) + *max_upscale = 1000; + + if (*min_downscale == 1) + *min_downscale = 1000; +} + + - int scale_w, scale_h; + int scale_w, scale_h, min_downscale, max_upscale; - /* todo: validate scaling per-format with dc plane caps */ + /* validate scaling per-format with dc plane caps */ + if (state->plane && state->plane->dev && state->fb) { + get_min_max_dc_plane_scaling(state->plane->dev, state->fb, + &min_downscale, &max_upscale); + } else { + min_downscale = 250; + max_upscale = 16000; + } + - if (scale_w < 250 || scale_w > 16000) + if (scale_w < min_downscale || scale_w > max_upscale) - if (scale_h < 250 || scale_h > 16000) + if (scale_h < min_downscale || scale_h > max_upscale) - int max_downscale = 0; - int max_upscale = int_max; + struct drm_framebuffer *fb = state->fb; + int min_downscale, max_upscale; + int min_scale = 0; + int max_scale = int_max; + + /* plane enabled? get min/max allowed scaling factors from plane caps. */ + if (fb && state->crtc) { + get_min_max_dc_plane_scaling(state->crtc->dev, fb, + &min_downscale, &max_upscale); + /* + * convert to drm convention: 16.16 fixed point, instead of dc's + * 1.0 == 1000. also drm scaling is src/dst instead of dc's + * dst/src, so min_scale = 1.0 / max_upscale, etc. + */ + min_scale = (1000 << 16) / max_upscale; + max_scale = (1000 << 16) / min_downscale; + } - /* todo: these should be checked against dc plane caps */ - state, new_crtc_state, max_downscale, max_upscale, true, true); + state, new_crtc_state, min_scale, max_scale, true, true);
|
Graphics
|
6300b3bd9d0d7afaf085dd086ce6258511c3f057
|
mario kleiner
|
drivers
|
gpu
|
amd, amdgpu_dm, display, drm
|
drm/amd/display: enable fp16 also on dce-8/10/11.
|
the hw supports fp16, this is not only useful for hdr, but also for standard dynamic range displays, because it allows to get more precise color reproduction with about 11 - 12 bpc linear precision in the unorm range 0.0 - 1.0.
|
this release allows to map an uid to a different one in a mount; it also adds support for selecting the preemption model at runtime; support for a low-overhead memory error detector designed to be used in production; support for the acrn hypervisor designed for embedded systems; btrfs initial support for zoned devices, subpage blocks sizes and performance improvements; support for eager nfs writes; support for a thermal power management to control the surface temperature of embedded devices in an unified way; the napi polling can be moved to a kernel thread; and support for non-blocking path lookups. as always, there are many other features, new drivers, improvements and fixes.
|
fp16 on dce8-11 support
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'cryptography', 'security', 'networking', 'architectures x86 arm risc-v powerpc mips csky s390 pa-risc c6x']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'cpu frequency scaling', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'cryptography hardware acceleration', 'pci', 'non-transparent bridge (ntb)', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'cxl (compute express link)', 'various']
|
['amdgpu ']
|
['c']
| 3
| 3
| 3
|
--- diff --git a/drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c b/drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c --- a/drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c +++ b/drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c - .fp16 = false + .fp16 = true diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c --- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c +++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c - .fp16 = false + .fp16 = true diff --git a/drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c b/drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c --- a/drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c +++ b/drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c - .fp16 = false + .fp16 = true
|
Graphics
|
4b6b7437b19d3116d409e747582c99152725288d
|
mario kleiner
|
drivers
|
gpu
|
amd, dc, dce100, dce110, dce80, display, drm
|
drm/amdgpu: add mode2 reset support for vangogh
|
gpu reset is handled via smu similar to previous apus.
|
this release allows to map an uid to a different one in a mount; it also adds support for selecting the preemption model at runtime; support for a low-overhead memory error detector designed to be used in production; support for the acrn hypervisor designed for embedded systems; btrfs initial support for zoned devices, subpage blocks sizes and performance improvements; support for eager nfs writes; support for a thermal power management to control the surface temperature of embedded devices in an unified way; the napi polling can be moved to a kernel thread; and support for non-blocking path lookups. as always, there are many other features, new drivers, improvements and fixes.
|
gpu reset on navy flounder/vangogh
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'cryptography', 'security', 'networking', 'architectures x86 arm risc-v powerpc mips csky s390 pa-risc c6x']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'cpu frequency scaling', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'cryptography hardware acceleration', 'pci', 'non-transparent bridge (ntb)', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'cxl (compute express link)', 'various']
|
['amdgpu ']
|
['c']
| 1
| 6
| 0
|
--- diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c --- a/drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c +++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c +static int vangogh_mode2_reset(struct smu_context *smu) +{ + return smu_cmn_send_smc_msg_with_param(smu, smu_msg_gfxdevicedriverreset, smu_reset_mode_2, null); +} + + .mode2_reset = vangogh_mode2_reset,
|
Graphics
|
20e157c725783caba0a880d48ef0e1355074175b
|
alex deucher evan quan evan quan amd com huang rui ray huang amd com
|
drivers
|
gpu
|
amd, drm, pm, smu11, swsmu
|
drm/amdgpu/nv: add mode2 reset handling
|
vangogh will use mode2 reset, so plumb it through the nv soc driver.
|
this release allows to map an uid to a different one in a mount; it also adds support for selecting the preemption model at runtime; support for a low-overhead memory error detector designed to be used in production; support for the acrn hypervisor designed for embedded systems; btrfs initial support for zoned devices, subpage blocks sizes and performance improvements; support for eager nfs writes; support for a thermal power management to control the surface temperature of embedded devices in an unified way; the napi polling can be moved to a kernel thread; and support for non-blocking path lookups. as always, there are many other features, new drivers, improvements and fixes.
|
gpu reset on navy flounder/vangogh
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'cryptography', 'security', 'networking', 'architectures x86 arm risc-v powerpc mips csky s390 pa-risc c6x']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'cpu frequency scaling', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'cryptography hardware acceleration', 'pci', 'non-transparent bridge (ntb)', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'cxl (compute express link)', 'various']
|
['amdgpu ']
|
['c']
| 1
| 12
| 2
|
--- diff --git a/drivers/gpu/drm/amd/amdgpu/nv.c b/drivers/gpu/drm/amd/amdgpu/nv.c --- a/drivers/gpu/drm/amd/amdgpu/nv.c +++ b/drivers/gpu/drm/amd/amdgpu/nv.c + amdgpu_reset_method == amd_reset_method_mode2 || + case chip_vangogh: + return amd_reset_method_mode2; - if (nv_asic_reset_method(adev) == amd_reset_method_baco) { + switch (nv_asic_reset_method(adev)) { + case amd_reset_method_baco: - } else { + break; + case amd_reset_method_mode2: + dev_info(adev->dev, "mode2 reset "); + ret = amdgpu_dpm_mode2_reset(adev); + break; + default: + break;
|
Graphics
|
1608635534fb8cc42e94d19d52789d9448f02536
|
alex deucher evan quan evan quan amd com huang rui ray huang amd com
|
drivers
|
gpu
|
amd, amdgpu, drm
|
drm/amdgpu: fix mode2 reset sequence for vangogh
|
we need to save and restore pci config space.
|
this release allows to map an uid to a different one in a mount; it also adds support for selecting the preemption model at runtime; support for a low-overhead memory error detector designed to be used in production; support for the acrn hypervisor designed for embedded systems; btrfs initial support for zoned devices, subpage blocks sizes and performance improvements; support for eager nfs writes; support for a thermal power management to control the surface temperature of embedded devices in an unified way; the napi polling can be moved to a kernel thread; and support for non-blocking path lookups. as always, there are many other features, new drivers, improvements and fixes.
|
gpu reset on navy flounder/vangogh
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'cryptography', 'security', 'networking', 'architectures x86 arm risc-v powerpc mips csky s390 pa-risc c6x']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'cpu frequency scaling', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'cryptography hardware acceleration', 'pci', 'non-transparent bridge (ntb)', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'cxl (compute express link)', 'various']
|
['amdgpu ']
|
['c']
| 1
| 33
| 1
|
--- diff --git a/drivers/gpu/drm/amd/amdgpu/nv.c b/drivers/gpu/drm/amd/amdgpu/nv.c --- a/drivers/gpu/drm/amd/amdgpu/nv.c +++ b/drivers/gpu/drm/amd/amdgpu/nv.c +static int nv_asic_mode2_reset(struct amdgpu_device *adev) +{ + u32 i; + int ret = 0; + + amdgpu_atombios_scratch_regs_engine_hung(adev, true); + + /* disable bm */ + pci_clear_master(adev->pdev); + + amdgpu_device_cache_pci_state(adev->pdev); + + ret = amdgpu_dpm_mode2_reset(adev); + if (ret) + dev_err(adev->dev, "gpu mode2 reset failed "); + + amdgpu_device_load_pci_state(adev->pdev); + + /* wait for asic to come out of reset */ + for (i = 0; i < adev->usec_timeout; i++) { + u32 memsize = adev->nbio.funcs->get_memsize(adev); + + if (memsize != 0xffffffff) + break; + udelay(1); + } + + amdgpu_atombios_scratch_regs_engine_hung(adev, false); + + return ret; +} + - ret = amdgpu_dpm_mode2_reset(adev); + ret = nv_asic_mode2_reset(adev);
|
Graphics
|
b913ec628ce2e701ba5a7d5f060f4d62d7a2ce06
|
alex deucher huang rui ray huang amd com
|
drivers
|
gpu
|
amd, amdgpu, drm
|
drm/amdgpu: enable gpu reset for vangogh
|
enable gpu reset when we encounter a hang.
|
this release allows to map an uid to a different one in a mount; it also adds support for selecting the preemption model at runtime; support for a low-overhead memory error detector designed to be used in production; support for the acrn hypervisor designed for embedded systems; btrfs initial support for zoned devices, subpage blocks sizes and performance improvements; support for eager nfs writes; support for a thermal power management to control the surface temperature of embedded devices in an unified way; the napi polling can be moved to a kernel thread; and support for non-blocking path lookups. as always, there are many other features, new drivers, improvements and fixes.
|
gpu reset on navy flounder/vangogh
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'cryptography', 'security', 'networking', 'architectures x86 arm risc-v powerpc mips csky s390 pa-risc c6x']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'cpu frequency scaling', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'cryptography hardware acceleration', 'pci', 'non-transparent bridge (ntb)', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'cxl (compute express link)', 'various']
|
['amdgpu ']
|
['c']
| 1
| 1
| 0
|
--- diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c + case chip_vangogh:
|
Graphics
|
b6903089a5ab74e8bcae963d5ca60b0005b75c05
|
alex deucher evan quan evan quan amd com huang rui ray huang amd com
|
drivers
|
gpu
|
amd, amdgpu, drm
|
drm/amdgpu: enable gpu recovery for navy_flounder
|
enable gpu recovery for navy_flounder by default to trigger reset once needed.
|
this release allows to map an uid to a different one in a mount; it also adds support for selecting the preemption model at runtime; support for a low-overhead memory error detector designed to be used in production; support for the acrn hypervisor designed for embedded systems; btrfs initial support for zoned devices, subpage blocks sizes and performance improvements; support for eager nfs writes; support for a thermal power management to control the surface temperature of embedded devices in an unified way; the napi polling can be moved to a kernel thread; and support for non-blocking path lookups. as always, there are many other features, new drivers, improvements and fixes.
|
gpu reset on navy flounder/vangogh
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'cryptography', 'security', 'networking', 'architectures x86 arm risc-v powerpc mips csky s390 pa-risc c6x']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'cpu frequency scaling', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'cryptography hardware acceleration', 'pci', 'non-transparent bridge (ntb)', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'cxl (compute express link)', 'various']
|
['amdgpu ']
|
['c']
| 1
| 1
| 0
|
--- diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c + case chip_navy_flounder:
|
Graphics
|
665fe4dce83d14177f46fac814964ec107f196b5
|
jiansong chen tao zhou tao zhou amd com
|
drivers
|
gpu
|
amd, amdgpu, drm
|
drm/amd/display: add freesync hdmi support to dmcu
|
[why] adding support for freesync hdmi to dc and dmcu
|
this release allows to map an uid to a different one in a mount; it also adds support for selecting the preemption model at runtime; support for a low-overhead memory error detector designed to be used in production; support for the acrn hypervisor designed for embedded systems; btrfs initial support for zoned devices, subpage blocks sizes and performance improvements; support for eager nfs writes; support for a thermal power management to control the surface temperature of embedded devices in an unified way; the napi polling can be moved to a kernel thread; and support for non-blocking path lookups. as always, there are many other features, new drivers, improvements and fixes.
|
add freesync hdmi support to dmcu
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'cryptography', 'security', 'networking', 'architectures x86 arm risc-v powerpc mips csky s390 pa-risc c6x']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'cpu frequency scaling', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'cryptography hardware acceleration', 'pci', 'non-transparent bridge (ntb)', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'cxl (compute express link)', 'various']
|
['amdgpu ']
|
['h', 'c', 'makefile']
| 6
| 268
| 1
|
--- diff --git a/drivers/gpu/drm/amd/display/dc/makefile b/drivers/gpu/drm/amd/display/dc/makefile --- a/drivers/gpu/drm/amd/display/dc/makefile +++ b/drivers/gpu/drm/amd/display/dc/makefile +dc_edid += dc_edid_parser.o -amd_display_files += $(amd_display_dmub) +amd_display_edid = $(addprefix $(amddalpath)/dc/,$(dc_edid)) +amd_display_files += $(amd_display_dmub) $(amd_display_edid) diff --git a/drivers/gpu/drm/amd/display/dc/dc_edid_parser.c b/drivers/gpu/drm/amd/display/dc/dc_edid_parser.c --- /dev/null +++ b/drivers/gpu/drm/amd/display/dc/dc_edid_parser.c +/* + * copyright 2021 advanced micro devices, inc. + * + * permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "software"), + * to deal in the software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the software, and to permit persons to whom the + * software is furnished to do so, subject to the following conditions: + * + * the above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the software. + * + * the software is provided "as is", without warranty of any kind, express or + * implied, including but not limited to the warranties of merchantability, + * fitness for a particular purpose and noninfringement. in no event shall + * the copyright holder(s) or author(s) be liable for any claim, damages or + * other liability, whether in an action of contract, tort or otherwise, + * arising from, out of or in connection with the software or the use or + * other dealings in the software. + * + * authors: amd + * + */ + +#include "dce/dce_dmcu.h" +#include "dc_edid_parser.h" + +bool dc_edid_parser_send_cea(struct dc *dc, + int offset, + int total_length, + uint8_t *data, + int length) +{ + struct dmcu *dmcu = dc->res_pool->dmcu; + + if (dmcu && + dmcu->funcs->is_dmcu_initialized(dmcu) && + dmcu->funcs->send_edid_cea) { + return dmcu->funcs->send_edid_cea(dmcu, + offset, + total_length, + data, + length); + } + + return false; +} + +bool dc_edid_parser_recv_cea_ack(struct dc *dc, int *offset) +{ + struct dmcu *dmcu = dc->res_pool->dmcu; + + if (dmcu && + dmcu->funcs->is_dmcu_initialized(dmcu) && + dmcu->funcs->recv_edid_cea_ack) { + return dmcu->funcs->recv_edid_cea_ack(dmcu, offset); + } + + return false; +} + +bool dc_edid_parser_recv_amd_vsdb(struct dc *dc, + int *version, + int *min_frame_rate, + int *max_frame_rate) +{ + struct dmcu *dmcu = dc->res_pool->dmcu; + + if (dmcu && + dmcu->funcs->is_dmcu_initialized(dmcu) && + dmcu->funcs->recv_amd_vsdb) { + return dmcu->funcs->recv_amd_vsdb(dmcu, + version, + min_frame_rate, + max_frame_rate); + } + + return false; +} diff --git a/drivers/gpu/drm/amd/display/dc/dc_edid_parser.h b/drivers/gpu/drm/amd/display/dc/dc_edid_parser.h --- /dev/null +++ b/drivers/gpu/drm/amd/display/dc/dc_edid_parser.h +/* + * copyright 2021 advanced micro devices, inc. + * + * permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "software"), + * to deal in the software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the software, and to permit persons to whom the + * software is furnished to do so, subject to the following conditions: + * + * the above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the software. + * + * the software is provided "as is", without warranty of any kind, express or + * implied, including but not limited to the warranties of merchantability, + * fitness for a particular purpose and noninfringement. in no event shall + * the copyright holder(s) or author(s) be liable for any claim, damages or + * other liability, whether in an action of contract, tort or otherwise, + * arising from, out of or in connection with the software or the use or + * other dealings in the software. + * + * authors: amd + * + */ + +#ifndef _dc_edid_parser_h_ +#define _dc_edid_parser_h_ + +#include "core_types.h" + +bool dc_edid_parser_send_cea(struct dc *dc, + int offset, + int total_length, + uint8_t *data, + int length); + +bool dc_edid_parser_recv_cea_ack(struct dc *dc, int *offset); + +bool dc_edid_parser_recv_amd_vsdb(struct dc *dc, + int *version, + int *min_frame_rate, + int *max_frame_rate); + +#endif /* _dc_edid_parser_h_ */ diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c b/drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c --- a/drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c +++ b/drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c +#define mcp_send_edid_cea 0xa0 +#define edid_cea_cmd_ack 1 +#define edid_cea_cmd_nack 2 +static bool dcn10_send_edid_cea(struct dmcu *dmcu, + int offset, + int total_length, + uint8_t *data, + int length) +{ + struct dce_dmcu *dmcu_dce = to_dce_dmcu(dmcu); + uint32_t header, data1, data2; + + /* if microcontroller is not running, do nothing */ + if (dmcu->dmcu_state != dmcu_running) + return false; + + if (length > 8 || length <= 0) + return false; + + header = ((uint32_t)offset & 0xffff) << 16 | (total_length & 0xffff); + data1 = (((uint32_t)data[0]) << 24) | (((uint32_t)data[1]) << 16) | + (((uint32_t)data[2]) << 8) | ((uint32_t)data[3]); + data2 = (((uint32_t)data[4]) << 24) | (((uint32_t)data[5]) << 16) | + (((uint32_t)data[6]) << 8) | ((uint32_t)data[7]); + + /* waitdmcureadyforcmd */ + reg_wait(master_comm_cntl_reg, master_comm_interrupt, 0, 1, 10000); + + /* setdmcuparam_cmd */ + reg_update(master_comm_cmd_reg, master_comm_cmd_reg_byte0, mcp_send_edid_cea); + + reg_write(master_comm_data_reg1, header); + reg_write(master_comm_data_reg2, data1); + reg_write(master_comm_data_reg3, data2); + + /* notifydmcumsg */ + reg_update(master_comm_cntl_reg, master_comm_interrupt, 1); + + /* waitdmcureadyforcmd */ + reg_wait(master_comm_cntl_reg, master_comm_interrupt, 0, 1, 10000); + + return true; +} + +static bool dcn10_get_scp_results(struct dmcu *dmcu, + uint32_t *cmd, + uint32_t *data1, + uint32_t *data2, + uint32_t *data3) +{ + struct dce_dmcu *dmcu_dce = to_dce_dmcu(dmcu); + + /* if microcontroller is not running, do nothing */ + if (dmcu->dmcu_state != dmcu_running) + return false; + + *cmd = reg_read(slave_comm_cmd_reg); + *data1 = reg_read(slave_comm_data_reg1); + *data2 = reg_read(slave_comm_data_reg2); + *data3 = reg_read(slave_comm_data_reg3); + + /* clear scp interrupt */ + reg_update(slave_comm_cntl_reg, slave_comm_interrupt, 0); + + return true; +} + +static bool dcn10_recv_amd_vsdb(struct dmcu *dmcu, + int *version, + int *min_frame_rate, + int *max_frame_rate) +{ + uint32_t data[4]; + int cmd, ack, len; + + if (!dcn10_get_scp_results(dmcu, &data[0], &data[1], &data[2], &data[3])) + return false; + + cmd = data[0] & 0x3ff; + len = (data[0] >> 10) & 0x3f; + ack = data[1]; + + if (cmd != mcp_send_edid_cea || ack != edid_cea_cmd_ack || len != 12) + return false; + + if ((data[2] & 0xff)) { + *version = (data[2] >> 8) & 0xff; + *min_frame_rate = (data[3] >> 16) & 0xffff; + *max_frame_rate = data[3] & 0xffff; + return true; + } + + return false; +} + +static bool dcn10_recv_edid_cea_ack(struct dmcu *dmcu, int *offset) +{ + uint32_t data[4]; + int cmd, ack; + + if (!dcn10_get_scp_results(dmcu, + &data[0], &data[1], &data[2], &data[3])) + return false; + + cmd = data[0] & 0x3ff; + ack = data[1]; + + if (cmd != mcp_send_edid_cea) + return false; + + if (ack == edid_cea_cmd_ack) + return true; + + *offset = data[2]; /* nack */ + return false; +} + + .send_edid_cea = dcn10_send_edid_cea, + .recv_amd_vsdb = dcn10_recv_amd_vsdb, + .recv_edid_cea_ack = dcn10_recv_edid_cea_ack, diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.h b/drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.h --- a/drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.h +++ b/drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.h + sr(slave_comm_data_reg1), \ + sr(slave_comm_data_reg2), \ + sr(slave_comm_data_reg3), \ + sr(slave_comm_cmd_reg), \ + dmcu_sf(slave_comm_cntl_reg, slave_comm_interrupt, mask_sh), \ + type slave_comm_interrupt; \ + uint32_t slave_comm_data_reg1; + uint32_t slave_comm_data_reg2; + uint32_t slave_comm_data_reg3; + uint32_t slave_comm_cmd_reg; + uint32_t slave_comm_cntl_reg; diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/dmcu.h b/drivers/gpu/drm/amd/display/dc/inc/hw/dmcu.h --- a/drivers/gpu/drm/amd/display/dc/inc/hw/dmcu.h +++ b/drivers/gpu/drm/amd/display/dc/inc/hw/dmcu.h + bool (*send_edid_cea)(struct dmcu *dmcu, + int offset, + int total_length, + uint8_t *data, + int length); + bool (*recv_amd_vsdb)(struct dmcu *dmcu, + int *version, + int *min_frame_rate, + int *max_frame_rate); + bool (*recv_edid_cea_ack)(struct dmcu *dmcu, int *offset);
|
Graphics
|
a0c898f28a3b6d97d425aafc56085c273e9f1cff
|
stylon wang
|
drivers
|
gpu
|
amd, dc, dce, display, drm, hw, inc
|
drm/amd/display: enable "trigger_hotplug" debugfs on all outputs
|
[why] per-connector debugfs entry "trigger_hotplug" is available on dp/edp only. new igt tests need this entry to test other outputs.
|
this release allows to map an uid to a different one in a mount; it also adds support for selecting the preemption model at runtime; support for a low-overhead memory error detector designed to be used in production; support for the acrn hypervisor designed for embedded systems; btrfs initial support for zoned devices, subpage blocks sizes and performance improvements; support for eager nfs writes; support for a thermal power management to control the surface temperature of embedded devices in an unified way; the napi polling can be moved to a kernel thread; and support for non-blocking path lookups. as always, there are many other features, new drivers, improvements and fixes.
|
enable "trigger_hotplug" debugfs on all outputs
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'cryptography', 'security', 'networking', 'architectures x86 arm risc-v powerpc mips csky s390 pa-risc c6x']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'cpu frequency scaling', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'cryptography hardware acceleration', 'pci', 'non-transparent bridge (ntb)', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'cxl (compute express link)', 'various']
|
['amdgpu ']
|
['c']
| 1
| 6
| 4
|
--- diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c -static ssize_t dp_trigger_hotplug(struct file *f, const char __user *buf, +static ssize_t trigger_hotplug(struct file *f, const char __user *buf, -static const struct file_operations dp_trigger_hotplug_debugfs_fops = { +static const struct file_operations trigger_hotplug_debugfs_fops = { - .write = dp_trigger_hotplug, + .write = trigger_hotplug, - {"trigger_hotplug", &dp_trigger_hotplug_debugfs_fops}, + debugfs_create_file("trigger_hotplug", 0644, dir, connector, + &trigger_hotplug_debugfs_fops); +
|
Graphics
|
02a342e3c4e511f43f24918921866254913c759d
|
stylon wang
|
drivers
|
gpu
|
amd, amdgpu_dm, display, drm
|
drm/amd/display: enable hubp blank behaviour
|
- reverts "drm/amd/display: revert hubp blank behaviour for now" - hubp blank will fail if the pipe is locked (this is the case on linux), so add a check to make sure pipe isn't locked, if it is then defer the blank to post_unlock.
|
this release allows to map an uid to a different one in a mount; it also adds support for selecting the preemption model at runtime; support for a low-overhead memory error detector designed to be used in production; support for the acrn hypervisor designed for embedded systems; btrfs initial support for zoned devices, subpage blocks sizes and performance improvements; support for eager nfs writes; support for a thermal power management to control the surface temperature of embedded devices in an unified way; the napi polling can be moved to a kernel thread; and support for non-blocking path lookups. as always, there are many other features, new drivers, improvements and fixes.
|
enable hubp blank behaviour
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'cryptography', 'security', 'networking', 'architectures x86 arm risc-v powerpc mips csky s390 pa-risc c6x']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'cpu frequency scaling', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'cryptography hardware acceleration', 'pci', 'non-transparent bridge (ntb)', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'cxl (compute express link)', 'various']
|
['amdgpu ']
|
['h', 'c']
| 8
| 45
| 3
|
- reverts "drm/amd/display: revert hubp blank behaviour for now" - hubp blank will fail if the pipe is locked (this is the case on --- diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c --- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c +++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c +bool optc1_is_locked(struct timing_generator *optc) +{ + struct optc *optc1 = dcn10tg_from_tg(optc); + uint32_t locked; + + reg_get(otg_master_update_lock, update_lock_status, &locked); + + return (locked == 1); +} + + .is_locked = optc1_is_locked, diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h --- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h +++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h +bool optc1_is_locked(struct timing_generator *optc); diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c --- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c +++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c + for (i = 0; i < dc->res_pool->pipe_count; i++) { + struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i]; + + if (pipe->vtp_locked) { + dc->hwss.set_hubp_blank(dc, pipe, true); + pipe->vtp_locked = false; + } + } diff --git a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_hwseq.c b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_hwseq.c --- a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_hwseq.c +++ b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_hwseq.c - pipe_ctx->stream_res.opp->funcs->opp_set_disp_pattern_generator(pipe_ctx->stream_res.opp, test_pattern, - color_space, color_depth, solid_color, width, height, offset); + struct stream_resource *stream_res = &pipe_ctx->stream_res; + + if (test_pattern != controller_dp_test_pattern_videomode) { + pipe_ctx->vtp_locked = false; + /* turning on dpg */ + stream_res->opp->funcs->opp_set_disp_pattern_generator(stream_res->opp, test_pattern, color_space, + color_depth, solid_color, width, height, offset); + + /* defer hubp blank if tg is locked */ + if (stream_res->tg->funcs->is_tg_enabled(stream_res->tg)) { + if (stream_res->tg->funcs->is_locked(stream_res->tg)) + pipe_ctx->vtp_locked = true; + else + dc->hwss.set_hubp_blank(dc, pipe_ctx, true); + } + } else { + dc->hwss.set_hubp_blank(dc, pipe_ctx, false); + /* turning off dpg */ + stream_res->opp->funcs->opp_set_disp_pattern_generator(stream_res->opp, test_pattern, color_space, + color_depth, solid_color, width, height, offset); + } diff --git a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_optc.c b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_optc.c --- a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_optc.c +++ b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_optc.c + .is_locked = optc1_is_locked, diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c b/drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c --- a/drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c +++ b/drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c - if (mode_lib->vba.minactivedramclockchangemargin > 0 && prefetchmode == 0) { + if (mode_lib->vba.minactivedramclockchangemargin > 0) { diff --git a/drivers/gpu/drm/amd/display/dc/inc/core_types.h b/drivers/gpu/drm/amd/display/dc/inc/core_types.h --- a/drivers/gpu/drm/amd/display/dc/inc/core_types.h +++ b/drivers/gpu/drm/amd/display/dc/inc/core_types.h + bool vtp_locked; diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/timing_generator.h b/drivers/gpu/drm/amd/display/dc/inc/hw/timing_generator.h --- a/drivers/gpu/drm/amd/display/dc/inc/hw/timing_generator.h +++ b/drivers/gpu/drm/amd/display/dc/inc/hw/timing_generator.h + bool (*is_locked)(struct timing_generator *tg);
|
Graphics
|
d209124ddae35fd5d86470421d3212c473169436
|
bhawanpreet lakha rodrigo siqueira rodrigo siqueira amd com nicholas kazlauskas nicholas kazlauskas amd com daniel wheeler daniel wheeler amd com
|
drivers
|
gpu
|
amd, dc, dcn10, dcn20, dcn30, display, dml, drm, hw, inc
|
drm/amd/display: implement t12 compliance
|
[why] when os reboots, and panel is turned off, t12 may not be maintained. t12 is defined as the interval between vddc off (occurs at shutdown) and the next vddc on (occurs when edp is post-ed)
|
this release allows to map an uid to a different one in a mount; it also adds support for selecting the preemption model at runtime; support for a low-overhead memory error detector designed to be used in production; support for the acrn hypervisor designed for embedded systems; btrfs initial support for zoned devices, subpage blocks sizes and performance improvements; support for eager nfs writes; support for a thermal power management to control the surface temperature of embedded devices in an unified way; the napi polling can be moved to a kernel thread; and support for non-blocking path lookups. as always, there are many other features, new drivers, improvements and fixes.
|
implement t12 compliance
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'cryptography', 'security', 'networking', 'architectures x86 arm risc-v powerpc mips csky s390 pa-risc c6x']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'cpu frequency scaling', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'cryptography hardware acceleration', 'pci', 'non-transparent bridge (ntb)', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'cxl (compute express link)', 'various']
|
['amdgpu ']
|
['h', 'c']
| 6
| 53
| 0
|
--- diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link.c b/drivers/gpu/drm/amd/display/dc/core/dc_link.c --- a/drivers/gpu/drm/amd/display/dc/core/dc_link.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc_link.c +bool dc_link_wait_for_t12(struct dc_link *link) +{ + if (link->connector_signal == signal_type_edp && link->dc->hwss.edp_wait_for_t12) { + link->dc->hwss.edp_wait_for_t12(link); + + return true; + } + + return false; +} + diff --git a/drivers/gpu/drm/amd/display/dc/dc_link.h b/drivers/gpu/drm/amd/display/dc/dc_link.h --- a/drivers/gpu/drm/amd/display/dc/dc_link.h +++ b/drivers/gpu/drm/amd/display/dc/dc_link.h +/* + * on edp links this function call will stall until t12 has elapsed. + * if the panel is not in power off state, this function will return + * immediately. + */ +bool dc_link_wait_for_t12(struct dc_link *link); + diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c --- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c +++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c +void dce110_edp_wait_for_t12( + struct dc_link *link) +{ + struct dc_context *ctx = link->ctx; + + if (dal_graphics_object_id_get_connector_id(link->link_enc->connector) + != connector_id_edp) { + break_to_debugger(); + return; + } + + if (!link->panel_cntl) + return; + + if (!link->panel_cntl->funcs->is_panel_powered_on(link->panel_cntl) && + link->link_trace.time_stamp.edp_poweroff != 0) { + unsigned int t12_duration = 500; // default t12 as per spec + unsigned long long current_ts = dm_get_timestamp(ctx); + unsigned long long time_since_edp_poweroff_ms = + div64_u64(dm_get_elapse_time_in_ns( + ctx, + current_ts, + link->link_trace.time_stamp.edp_poweroff), 1000000); + + t12_duration += link->local_sink->edid_caps.panel_patch.extra_t12_ms; // add extra t12 + + if (time_since_edp_poweroff_ms < t12_duration) + msleep(t12_duration - time_since_edp_poweroff_ms); + } +} + diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.h b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.h --- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.h +++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.h +void dce110_edp_wait_for_t12( + struct dc_link *link); diff --git a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_init.c b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_init.c --- a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_init.c +++ b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_init.c + .edp_wait_for_t12 = dce110_edp_wait_for_t12, diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h b/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h --- a/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h +++ b/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h + void (*edp_wait_for_t12)(struct dc_link *link);
|
Graphics
|
cf3a2627597794797ce5930537c0e75df284b6e9
|
jun lei
|
drivers
|
gpu
|
amd, core, dc, dce110, dcn10, dcn30, display, drm, inc
|
drm/amd/pm: add interface for request wgps
|
when user specifies a reduced wgp(cu) config via disalbe_cu module parameter, this does not disable the clocks which uses additional power. this interface send active wgp number to smu and smu will cooperate with rlc to power off relative wgps.
|
this release allows to map an uid to a different one in a mount; it also adds support for selecting the preemption model at runtime; support for a low-overhead memory error detector designed to be used in production; support for the acrn hypervisor designed for embedded systems; btrfs initial support for zoned devices, subpage blocks sizes and performance improvements; support for eager nfs writes; support for a thermal power management to control the surface temperature of embedded devices in an unified way; the napi polling can be moved to a kernel thread; and support for non-blocking path lookups. as always, there are many other features, new drivers, improvements and fixes.
|
add interface for request wgps
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'cryptography', 'security', 'networking', 'architectures x86 arm risc-v powerpc mips csky s390 pa-risc c6x']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'cpu frequency scaling', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'cryptography hardware acceleration', 'pci', 'non-transparent bridge (ntb)', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'cxl (compute express link)', 'various']
|
['amdgpu ']
|
['h', 'c']
| 3
| 41
| 3
|
--- diff --git a/drivers/gpu/drm/amd/pm/inc/smu_types.h b/drivers/gpu/drm/amd/pm/inc/smu_types.h --- a/drivers/gpu/drm/amd/pm/inc/smu_types.h +++ b/drivers/gpu/drm/amd/pm/inc/smu_types.h + __smu_dummy_map(requestactivewgp), \ diff --git a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c b/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c --- a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c +++ b/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c - if (adev->asic_type == chip_vangogh) - return 0; - + if (adev->asic_type == chip_vangogh) + return 0; + diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c --- a/drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c +++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c +#include "soc15_common.h" +#include "asic_reg/gc/gc_10_3_0_offset.h" +#include "asic_reg/gc/gc_10_3_0_sh_mask.h" + msg_map(requestactivewgp, ppsmc_msg_requestactivewgp, 0), +static int vangogh_post_smu_init(struct smu_context *smu) +{ + struct amdgpu_device *adev = smu->adev; + uint32_t tmp; + uint8_t aon_bits = 0; + /* two cus in one wgp */ + uint32_t req_active_wgps = adev->gfx.cu_info.number/2; + uint32_t total_cu = adev->gfx.config.max_cu_per_sh * + adev->gfx.config.max_sh_per_se * adev->gfx.config.max_shader_engines; + + /* if all cus are active, no need to power off any wgps */ + if (total_cu == adev->gfx.cu_info.number) + return 0; + + /* + * calculate the total bits number of always on wgps for all sa/ses in + * rlc_pg_always_on_wgp_mask. + */ + tmp = rreg32_kiq(soc15_reg_offset(gc, 0, mmrlc_pg_always_on_wgp_mask)); + tmp &= rlc_pg_always_on_wgp_mask__aon_wgp_mask_mask; + + aon_bits = hweight32(tmp) * adev->gfx.config.max_sh_per_se * adev->gfx.config.max_shader_engines; + + /* do not request any wgps less than set in the aon_wgp_mask */ + if (aon_bits > req_active_wgps) { + dev_info(adev->dev, "number of always on wgps greater than active wgps: wgp power save not requested. "); + return 0; + } else { + return smu_cmn_send_smc_msg_with_param(smu, smu_msg_requestactivewgp, req_active_wgps, null); + } +} + + .post_init = vangogh_post_smu_init,
|
Graphics
|
eefdf0471069a41e7c3c2c2498270165464152be
|
jinzhou su
|
drivers
|
gpu
|
amd, drm, inc, pm, smu11, swsmu
|
drm/amd/pm: add support for hwmon control of slow and fast ppt limit on vangogh
|
implement hwmon api for reading/setting slow and fast ppt limit.
|
this release allows to map an uid to a different one in a mount; it also adds support for selecting the preemption model at runtime; support for a low-overhead memory error detector designed to be used in production; support for the acrn hypervisor designed for embedded systems; btrfs initial support for zoned devices, subpage blocks sizes and performance improvements; support for eager nfs writes; support for a thermal power management to control the surface temperature of embedded devices in an unified way; the napi polling can be moved to a kernel thread; and support for non-blocking path lookups. as always, there are many other features, new drivers, improvements and fixes.
|
add support for hwmon control of slow and fast ppt limit on vangogh
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'cryptography', 'security', 'networking', 'architectures x86 arm risc-v powerpc mips csky s390 pa-risc c6x']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'cpu frequency scaling', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'cryptography hardware acceleration', 'pci', 'non-transparent bridge (ntb)', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'cxl (compute express link)', 'various']
|
['amdgpu ']
|
['h', 'c']
| 6
| 204
| 18
|
--- diff --git a/drivers/gpu/drm/amd/pm/amdgpu_pm.c b/drivers/gpu/drm/amd/pm/amdgpu_pm.c --- a/drivers/gpu/drm/amd/pm/amdgpu_pm.c +++ b/drivers/gpu/drm/amd/pm/amdgpu_pm.c - uint32_t limit = 0; + int limit_type = to_sensor_dev_attr(attr)->index; + uint32_t limit = limit_type << 24; - uint32_t limit = 0; + int limit_type = to_sensor_dev_attr(attr)->index; + uint32_t limit = limit_type << 24; +static ssize_t amdgpu_hwmon_show_power_label(struct device *dev, + struct device_attribute *attr, + char *buf) +{ + int limit_type = to_sensor_dev_attr(attr)->index; + + return snprintf(buf, page_size, "%s ", + limit_type == smu_fast_ppt_limit ? "fastppt" : "slowppt"); +} + int limit_type = to_sensor_dev_attr(attr)->index; - + value |= limit_type << 24; +static sensor_device_attr(power1_label, s_irugo, amdgpu_hwmon_show_power_label, null, 0); +static sensor_device_attr(power2_average, s_irugo, amdgpu_hwmon_show_power_avg, null, 1); +static sensor_device_attr(power2_cap_max, s_irugo, amdgpu_hwmon_show_power_cap_max, null, 1); +static sensor_device_attr(power2_cap_min, s_irugo, amdgpu_hwmon_show_power_cap_min, null, 1); +static sensor_device_attr(power2_cap, s_irugo | s_iwusr, amdgpu_hwmon_show_power_cap, amdgpu_hwmon_set_power_cap, 1); +static sensor_device_attr(power2_label, s_irugo, amdgpu_hwmon_show_power_label, null, 1); + &sensor_dev_attr_power1_label.dev_attr.attr, + &sensor_dev_attr_power2_average.dev_attr.attr, + &sensor_dev_attr_power2_cap_max.dev_attr.attr, + &sensor_dev_attr_power2_cap_min.dev_attr.attr, + &sensor_dev_attr_power2_cap.dev_attr.attr, + &sensor_dev_attr_power2_label.dev_attr.attr, - if (((adev->flags & amd_is_apu) || - adev->family == amdgpu_family_si) && /* not implemented yet */ + if (((adev->family == amdgpu_family_si) || + ((adev->flags & amd_is_apu) && + (adev->asic_type != chip_vangogh))) && /* not implemented yet */ + /* only vangogh has fast ppt limit and power labels */ + if (!(adev->asic_type == chip_vangogh) && + (attr == &sensor_dev_attr_power2_average.dev_attr.attr || + attr == &sensor_dev_attr_power2_cap_max.dev_attr.attr || + attr == &sensor_dev_attr_power2_cap_min.dev_attr.attr || + attr == &sensor_dev_attr_power2_cap.dev_attr.attr || + attr == &sensor_dev_attr_power2_label.dev_attr.attr || + attr == &sensor_dev_attr_power1_label.dev_attr.attr)) + return 0; + diff --git a/drivers/gpu/drm/amd/pm/inc/amdgpu_smu.h b/drivers/gpu/drm/amd/pm/inc/amdgpu_smu.h --- a/drivers/gpu/drm/amd/pm/inc/amdgpu_smu.h +++ b/drivers/gpu/drm/amd/pm/inc/amdgpu_smu.h +enum smu_ppt_limit_type +{ + smu_default_ppt_limit = 0, + smu_fast_ppt_limit, +}; + + /** + * @get_ppt_limit: get the device's ppt limits. + */ + int (*get_ppt_limit)(struct smu_context *smu, uint32_t *ppt_limit, + enum smu_ppt_limit_type limit_type, enum smu_ppt_limit_level limit_level); + diff --git a/drivers/gpu/drm/amd/pm/inc/smu_v11_0.h b/drivers/gpu/drm/amd/pm/inc/smu_v11_0.h --- a/drivers/gpu/drm/amd/pm/inc/smu_v11_0.h +++ b/drivers/gpu/drm/amd/pm/inc/smu_v11_0.h +struct smu_11_5_power_context { + uint32_t power_source; + uint8_t in_power_limit_boost_mode; + enum smu_11_0_power_state power_state; + + uint32_t current_fast_ppt_limit; + uint32_t max_fast_ppt_limit; +}; + diff --git a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c b/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c --- a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c +++ b/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c + uint32_t limit_type = *limit >> 24; + int ret = 0; + - switch (limit_level) { - case smu_ppt_limit_current: - *limit = smu->current_power_limit; - break; - case smu_ppt_limit_max: - *limit = smu->max_power_limit; - break; - default: - break; + if (limit_type != smu_default_ppt_limit) { + if (smu->ppt_funcs->get_ppt_limit) + ret = smu->ppt_funcs->get_ppt_limit(smu, limit, limit_type, limit_level); + } else { + switch (limit_level) { + case smu_ppt_limit_current: + *limit = smu->current_power_limit; + break; + case smu_ppt_limit_max: + *limit = smu->max_power_limit; + break; + default: + break; + } - return 0; + return ret; + uint32_t limit_type = limit >> 24; + if (limit_type != smu_default_ppt_limit) + if (smu->ppt_funcs->set_power_limit) { + ret = smu->ppt_funcs->set_power_limit(smu, limit); + goto out; + } + diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/smu_v11_0.c b/drivers/gpu/drm/amd/pm/swsmu/smu11/smu_v11_0.c --- a/drivers/gpu/drm/amd/pm/swsmu/smu11/smu_v11_0.c +++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/smu_v11_0.c + size_t size = smu->adev->asic_type == chip_vangogh ? + sizeof(struct smu_11_5_power_context) : + sizeof(struct smu_11_0_power_context); - smu_power->power_context = kzalloc(sizeof(struct smu_11_0_power_context), - gfp_kernel); + smu_power->power_context = kzalloc(size, gfp_kernel); - smu_power->power_context_size = sizeof(struct smu_11_0_power_context); + smu_power->power_context_size = size; diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c --- a/drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c +++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c + msg_map(setfastpptlimit, ppsmc_msg_setfastpptlimit, 0), + msg_map(setslowpptlimit, ppsmc_msg_setslowpptlimit, 0), + msg_map(getfastpptlimit, ppsmc_msg_getfastpptlimit, 0), + msg_map(getslowpptlimit, ppsmc_msg_getslowpptlimit, 0), +static int vangogh_get_power_limit(struct smu_context *smu) +{ + struct smu_11_5_power_context *power_context = + smu->smu_power.power_context; + uint32_t ppt_limit; + int ret = 0; + + if (smu->adev->pm.fw_version < 0x43f1e00) + return ret; + + ret = smu_cmn_send_smc_msg(smu, smu_msg_getslowpptlimit, &ppt_limit); + if (ret) { + dev_err(smu->adev->dev, "get slow ppt limit failed! "); + return ret; + } + /* convert from milliwatt to watt */ + smu->current_power_limit = ppt_limit / 1000; + smu->max_power_limit = 29; + + ret = smu_cmn_send_smc_msg(smu, smu_msg_getfastpptlimit, &ppt_limit); + if (ret) { + dev_err(smu->adev->dev, "get fast ppt limit failed! "); + return ret; + } + /* convert from milliwatt to watt */ + power_context->current_fast_ppt_limit = ppt_limit / 1000; + power_context->max_fast_ppt_limit = 30; + + return ret; +} + +static int vangogh_get_ppt_limit(struct smu_context *smu, + uint32_t *ppt_limit, + enum smu_ppt_limit_type type, + enum smu_ppt_limit_level level) +{ + struct smu_11_5_power_context *power_context = + smu->smu_power.power_context; + + if (!power_context) + return -eopnotsupp; + + if (type == smu_fast_ppt_limit) { + switch (level) { + case smu_ppt_limit_max: + *ppt_limit = power_context->max_fast_ppt_limit; + break; + case smu_ppt_limit_current: + *ppt_limit = power_context->current_fast_ppt_limit; + break; + default: + break; + } + } + + return 0; +} + +static int vangogh_set_power_limit(struct smu_context *smu, uint32_t ppt_limit) +{ + struct smu_11_5_power_context *power_context = + smu->smu_power.power_context; + uint32_t limit_type = ppt_limit >> 24; + int ret = 0; + + if (!smu_cmn_feature_is_enabled(smu, smu_feature_ppt_bit)) { + dev_err(smu->adev->dev, "setting new power limit is not supported! "); + return -eopnotsupp; + } + + switch (limit_type) { + case smu_default_ppt_limit: + ret = smu_cmn_send_smc_msg_with_param(smu, + smu_msg_setslowpptlimit, + ppt_limit * 1000, /* convert from watt to milliwatt */ + null); + if (ret) + return ret; + + smu->current_power_limit = ppt_limit; + break; + case smu_fast_ppt_limit: + ppt_limit &= ~(smu_fast_ppt_limit << 24); + if (ppt_limit > power_context->max_fast_ppt_limit) { + dev_err(smu->adev->dev, + "new power limit (%d) is over the max allowed %d ", + ppt_limit, power_context->max_fast_ppt_limit); + return ret; + } + + ret = smu_cmn_send_smc_msg_with_param(smu, + smu_msg_setfastpptlimit, + ppt_limit * 1000, /* convert from watt to milliwatt */ + null); + if (ret) + return ret; + + power_context->current_fast_ppt_limit = ppt_limit; + break; + default: + return -einval; + } + + return ret; +} + + .get_ppt_limit = vangogh_get_ppt_limit, + .get_power_limit = vangogh_get_power_limit, + .set_power_limit = vangogh_set_power_limit,
|
Graphics
|
ae07970a0621d67a8bc0dc5b44e3fc652bd2ba20
|
xiaomeng hou
|
drivers
|
gpu
|
amd, drm, inc, pm, smu11, swsmu
|
drm/amd/pm: add two new sysfs nodes for vangogh
|
this patch is to add two new sysfs nodes for vangogh: pp_dpm_dclk and pp_dpm_vclk. the two sysfs nodes are similar to pp_dpm_fclk/memclk/socclk. pp_dpm_dclk represents the dpm frequency of dcn unit. pp_dpm_vclk represents the dpm frequency of vcn unit.
|
this release allows to map an uid to a different one in a mount; it also adds support for selecting the preemption model at runtime; support for a low-overhead memory error detector designed to be used in production; support for the acrn hypervisor designed for embedded systems; btrfs initial support for zoned devices, subpage blocks sizes and performance improvements; support for eager nfs writes; support for a thermal power management to control the surface temperature of embedded devices in an unified way; the napi polling can be moved to a kernel thread; and support for non-blocking path lookups. as always, there are many other features, new drivers, improvements and fixes.
|
add two new sysfs nodes for vangogh
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'cryptography', 'security', 'networking', 'architectures x86 arm risc-v powerpc mips csky s390 pa-risc c6x']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'cpu frequency scaling', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'cryptography hardware acceleration', 'pci', 'non-transparent bridge (ntb)', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'cxl (compute express link)', 'various']
|
['amdgpu ']
|
['c']
| 1
| 140
| 0
|
--- diff --git a/drivers/gpu/drm/amd/pm/amdgpu_pm.c b/drivers/gpu/drm/amd/pm/amdgpu_pm.c --- a/drivers/gpu/drm/amd/pm/amdgpu_pm.c +++ b/drivers/gpu/drm/amd/pm/amdgpu_pm.c +static ssize_t amdgpu_get_pp_dpm_vclk(struct device *dev, + struct device_attribute *attr, + char *buf) +{ + struct drm_device *ddev = dev_get_drvdata(dev); + struct amdgpu_device *adev = drm_to_adev(ddev); + ssize_t size; + int ret; + + if (amdgpu_in_reset(adev)) + return -eperm; + + ret = pm_runtime_get_sync(ddev->dev); + if (ret < 0) { + pm_runtime_put_autosuspend(ddev->dev); + return ret; + } + + if (is_support_sw_smu(adev)) + size = smu_print_clk_levels(&adev->smu, smu_vclk, buf); + else + size = snprintf(buf, page_size, " "); + + pm_runtime_mark_last_busy(ddev->dev); + pm_runtime_put_autosuspend(ddev->dev); + + return size; +} + +static ssize_t amdgpu_set_pp_dpm_vclk(struct device *dev, + struct device_attribute *attr, + const char *buf, + size_t count) +{ + struct drm_device *ddev = dev_get_drvdata(dev); + struct amdgpu_device *adev = drm_to_adev(ddev); + int ret; + uint32_t mask = 0; + + if (amdgpu_in_reset(adev)) + return -eperm; + + ret = amdgpu_read_mask(buf, count, &mask); + if (ret) + return ret; + + ret = pm_runtime_get_sync(ddev->dev); + if (ret < 0) { + pm_runtime_put_autosuspend(ddev->dev); + return ret; + } + + if (is_support_sw_smu(adev)) + ret = smu_force_clk_levels(&adev->smu, smu_vclk, mask); + else + ret = 0; + + pm_runtime_mark_last_busy(ddev->dev); + pm_runtime_put_autosuspend(ddev->dev); + + if (ret) + return -einval; + + return count; +} + +static ssize_t amdgpu_get_pp_dpm_dclk(struct device *dev, + struct device_attribute *attr, + char *buf) +{ + struct drm_device *ddev = dev_get_drvdata(dev); + struct amdgpu_device *adev = drm_to_adev(ddev); + ssize_t size; + int ret; + + if (amdgpu_in_reset(adev)) + return -eperm; + + ret = pm_runtime_get_sync(ddev->dev); + if (ret < 0) { + pm_runtime_put_autosuspend(ddev->dev); + return ret; + } + + if (is_support_sw_smu(adev)) + size = smu_print_clk_levels(&adev->smu, smu_dclk, buf); + else + size = snprintf(buf, page_size, " "); + + pm_runtime_mark_last_busy(ddev->dev); + pm_runtime_put_autosuspend(ddev->dev); + + return size; +} + +static ssize_t amdgpu_set_pp_dpm_dclk(struct device *dev, + struct device_attribute *attr, + const char *buf, + size_t count) +{ + struct drm_device *ddev = dev_get_drvdata(dev); + struct amdgpu_device *adev = drm_to_adev(ddev); + int ret; + uint32_t mask = 0; + + if (amdgpu_in_reset(adev)) + return -eperm; + + ret = amdgpu_read_mask(buf, count, &mask); + if (ret) + return ret; + + ret = pm_runtime_get_sync(ddev->dev); + if (ret < 0) { + pm_runtime_put_autosuspend(ddev->dev); + return ret; + } + + if (is_support_sw_smu(adev)) + ret = smu_force_clk_levels(&adev->smu, smu_dclk, mask); + else + ret = 0; + + pm_runtime_mark_last_busy(ddev->dev); + pm_runtime_put_autosuspend(ddev->dev); + + if (ret) + return -einval; + + return count; +} + + amdgpu_device_attr_rw(pp_dpm_vclk, attr_flag_basic|attr_flag_onevf), + amdgpu_device_attr_rw(pp_dpm_dclk, attr_flag_basic|attr_flag_onevf), + } else if (device_attr_is(pp_dpm_vclk)) { + if (!(asic_type == chip_vangogh)) + *states = attr_state_unsupported; + } else if (device_attr_is(pp_dpm_dclk)) { + if (!(asic_type == chip_vangogh)) + *states = attr_state_unsupported;
|
Graphics
|
9577b0ec2be8410b94e9928f25b740b55de2c13d
|
xiaojian du evan quan evan quan amd com
|
drivers
|
gpu
|
amd, drm, pm
|
drm/amdgpu/nv: add pci reset support
|
use generic pci reset for gpu reset if the user specifies pci reset as the reset mechanism. this should in general only be used for validation.
|
this release allows to map an uid to a different one in a mount; it also adds support for selecting the preemption model at runtime; support for a low-overhead memory error detector designed to be used in production; support for the acrn hypervisor designed for embedded systems; btrfs initial support for zoned devices, subpage blocks sizes and performance improvements; support for eager nfs writes; support for a thermal power management to control the surface temperature of embedded devices in an unified way; the napi polling can be moved to a kernel thread; and support for non-blocking path lookups. as always, there are many other features, new drivers, improvements and fixes.
|
add pci reset support for several models
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'cryptography', 'security', 'networking', 'architectures x86 arm risc-v powerpc mips csky s390 pa-risc c6x']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'cpu frequency scaling', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'cryptography hardware acceleration', 'pci', 'non-transparent bridge (ntb)', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'cxl (compute express link)', 'various']
|
['amdgpu ']
|
['c']
| 1
| 6
| 1
|
--- diff --git a/drivers/gpu/drm/amd/amdgpu/nv.c b/drivers/gpu/drm/amd/amdgpu/nv.c --- a/drivers/gpu/drm/amd/amdgpu/nv.c +++ b/drivers/gpu/drm/amd/amdgpu/nv.c - amdgpu_reset_method == amd_reset_method_baco) + amdgpu_reset_method == amd_reset_method_baco || + amdgpu_reset_method == amd_reset_method_pci) + case amd_reset_method_pci: + dev_info(adev->dev, "pci reset "); + ret = amdgpu_device_pci_reset(adev); + break;
|
Graphics
|
f172865a3632b85f29c2af9b044f4dd51581740f
|
alex deucher evan quan evan quan amd com
|
drivers
|
gpu
|
amd, amdgpu, drm
|
drm/amdgpu/soc15: add pci reset support
|
use generic pci reset for gpu reset if the user specifies pci reset as the reset mechanism. this should in general only be used for validation.
|
this release allows to map an uid to a different one in a mount; it also adds support for selecting the preemption model at runtime; support for a low-overhead memory error detector designed to be used in production; support for the acrn hypervisor designed for embedded systems; btrfs initial support for zoned devices, subpage blocks sizes and performance improvements; support for eager nfs writes; support for a thermal power management to control the surface temperature of embedded devices in an unified way; the napi polling can be moved to a kernel thread; and support for non-blocking path lookups. as always, there are many other features, new drivers, improvements and fixes.
|
add pci reset support for several models
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'cryptography', 'security', 'networking', 'architectures x86 arm risc-v powerpc mips csky s390 pa-risc c6x']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'cpu frequency scaling', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'cryptography hardware acceleration', 'pci', 'non-transparent bridge (ntb)', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'cxl (compute express link)', 'various']
|
['amdgpu ']
|
['c']
| 1
| 14
| 10
|
--- diff --git a/drivers/gpu/drm/amd/amdgpu/soc15.c b/drivers/gpu/drm/amd/amdgpu/soc15.c --- a/drivers/gpu/drm/amd/amdgpu/soc15.c +++ b/drivers/gpu/drm/amd/amdgpu/soc15.c - amdgpu_reset_method == amd_reset_method_baco) + amdgpu_reset_method == amd_reset_method_baco || + amdgpu_reset_method == amd_reset_method_pci) - case amd_reset_method_baco: - dev_info(adev->dev, "baco reset "); - return soc15_asic_baco_reset(adev); - case amd_reset_method_mode2: - dev_info(adev->dev, "mode2 reset "); - return amdgpu_dpm_mode2_reset(adev); - default: - dev_info(adev->dev, "mode1 reset "); - return soc15_asic_mode1_reset(adev); + case amd_reset_method_pci: + dev_info(adev->dev, "pci reset "); + return amdgpu_device_pci_reset(adev); + case amd_reset_method_baco: + dev_info(adev->dev, "baco reset "); + return soc15_asic_baco_reset(adev); + case amd_reset_method_mode2: + dev_info(adev->dev, "mode2 reset "); + return amdgpu_dpm_mode2_reset(adev); + default: + dev_info(adev->dev, "mode1 reset "); + return soc15_asic_mode1_reset(adev);
|
Graphics
|
1176a1e0b9d50255d733a1e04c039405a3ab5948
|
alex deucher evan quan evan quan amd com
|
drivers
|
gpu
|
amd, amdgpu, drm
|
drm/amdgpu/si: add pci reset support
|
use generic pci reset for gpu reset if the user specifies pci reset as the reset mechanism. this should in general only be used for validation.
|
this release allows to map an uid to a different one in a mount; it also adds support for selecting the preemption model at runtime; support for a low-overhead memory error detector designed to be used in production; support for the acrn hypervisor designed for embedded systems; btrfs initial support for zoned devices, subpage blocks sizes and performance improvements; support for eager nfs writes; support for a thermal power management to control the surface temperature of embedded devices in an unified way; the napi polling can be moved to a kernel thread; and support for non-blocking path lookups. as always, there are many other features, new drivers, improvements and fixes.
|
add pci reset support for several models
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'cryptography', 'security', 'networking', 'architectures x86 arm risc-v powerpc mips csky s390 pa-risc c6x']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'cpu frequency scaling', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'cryptography hardware acceleration', 'pci', 'non-transparent bridge (ntb)', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'cxl (compute express link)', 'various']
|
['amdgpu ']
|
['c']
| 1
| 23
| 14
|
--- diff --git a/drivers/gpu/drm/amd/amdgpu/si.c b/drivers/gpu/drm/amd/amdgpu/si.c --- a/drivers/gpu/drm/amd/amdgpu/si.c +++ b/drivers/gpu/drm/amd/amdgpu/si.c -static int si_asic_reset(struct amdgpu_device *adev) -{ - int r; - - dev_info(adev->dev, "pci config reset "); - - r = si_gpu_pci_config_reset(adev); - - return r; -} - - if (amdgpu_reset_method != amd_reset_method_legacy && - amdgpu_reset_method != -1) + if (amdgpu_reset_method == amd_reset_method_pci) + return amdgpu_reset_method; + else if (amdgpu_reset_method != amd_reset_method_legacy && + amdgpu_reset_method != -1) - amdgpu_reset_method); + amdgpu_reset_method); +static int si_asic_reset(struct amdgpu_device *adev) +{ + int r; + + switch (si_asic_reset_method(adev)) { + case amd_reset_method_pci: + dev_info(adev->dev, "pci reset "); + r = amdgpu_device_pci_reset(adev); + break; + default: + dev_info(adev->dev, "pci config reset "); + r = si_gpu_pci_config_reset(adev); + break; + } + + return r; +} +
|
Graphics
|
ffbfd081b47cf4b23dc6e2923534ad8984fe6ec6
|
alex deucher evan quan evan quan amd com
|
drivers
|
gpu
|
amd, amdgpu, drm
|
drm/amdgpu: add secure display ta header file
|
add file ta_securedisplay_if.h for secure display ta
|
this release allows to map an uid to a different one in a mount; it also adds support for selecting the preemption model at runtime; support for a low-overhead memory error detector designed to be used in production; support for the acrn hypervisor designed for embedded systems; btrfs initial support for zoned devices, subpage blocks sizes and performance improvements; support for eager nfs writes; support for a thermal power management to control the surface temperature of embedded devices in an unified way; the napi polling can be moved to a kernel thread; and support for non-blocking path lookups. as always, there are many other features, new drivers, improvements and fixes.
|
add secure display ta interface
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'cryptography', 'security', 'networking', 'architectures x86 arm risc-v powerpc mips csky s390 pa-risc c6x']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'cpu frequency scaling', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'cryptography hardware acceleration', 'pci', 'non-transparent bridge (ntb)', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'cxl (compute express link)', 'various']
|
['amdgpu ']
|
['h']
| 1
| 154
| 0
|
--- diff --git a/drivers/gpu/drm/amd/amdgpu/ta_securedisplay_if.h b/drivers/gpu/drm/amd/amdgpu/ta_securedisplay_if.h --- /dev/null +++ b/drivers/gpu/drm/amd/amdgpu/ta_securedisplay_if.h +/* + * copyright 2019 advanced micro devices, inc. + * + * permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "software"), + * to deal in the software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the software, and to permit persons to whom the + * software is furnished to do so, subject to the following conditions: + * + * the above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the software. + * + * the software is provided "as is", without warranty of any kind, express or + * implied, including but not limited to the warranties of merchantability, + * fitness for a particular purpose and noninfringement. in no event shall + * the copyright holder(s) or author(s) be liable for any claim, damages or + * other liability, whether in an action of contract, tort or otherwise, + * arising from, out of or in connection with the software or the use or + * other dealings in the software. + * + */ + +#ifndef _ta_securedisplay_if_h +#define _ta_securedisplay_if_h + +/** secure display related enumerations */ +/**********************************************************/ + +/** @enum ta_securedisplay_command + * secure display command id + */ +enum ta_securedisplay_command { + /* query whether ta is responding used only for validation purpose */ + ta_securedisplay_command__query_ta = 1, + /* send region of interest and crc value to i2c */ + ta_securedisplay_command__send_roi_crc = 2, + /* maximum command id */ + ta_securedisplay_command__max_id = 0x7fffffff, +}; + +/** @enum ta_securedisplay_status + * secure display status returns in shared buffer status + */ +enum ta_securedisplay_status { + ta_securedisplay_status__success = 0x00, /* success */ + ta_securedisplay_status__generic_failure = 0x01, /* generic failure */ + ta_securedisplay_status__invalid_parameter = 0x02, /* invalid parameter */ + ta_securedisplay_status__null_pointer = 0x03, /* null pointer*/ + ta_securedisplay_status__i2c_write_error = 0x04, /* fail to write to i2c */ + ta_securedisplay_status__read_dio_scratch_error = 0x05, /*fail read dio scratch register*/ + ta_securedisplay_status__read_crc_error = 0x06, /* fail to read crc*/ + + ta_securedisplay_status__max = 0x7fffffff,/* maximum value for status*/ +}; + +/** @enum ta_securedisplay_max_phy + * physical id number to use for reading corresponding dio scratch register for roi + */ +enum ta_securedisplay_max_phy { + ta_securedisplay_phy0 = 0, + ta_securedisplay_phy1 = 1, + ta_securedisplay_phy2 = 2, + ta_securedisplay_phy3 = 3, + ta_securedisplay_max_phy = 4, +}; + +/** @enum ta_securedisplay_ta_query_cmd_ret + * a predefined specific reteurn value which is 0xab only used to validate + * communication to secure display ta is functional. + * this value is used to validate whether ta is responding successfully + */ +enum ta_securedisplay_ta_query_cmd_ret { + /* this is a value to validate if ta is loaded successfully */ + ta_securedisplay_query_cmd_ret = 0xab, +}; + +/** @enum ta_securedisplay_buffer_size + * i2c buffer size which contains 8 bytes of roi (x start, x end, y start, y end) + * and 6 bytes of crc( r,g,b) and 1 byte for physical id + */ +enum ta_securedisplay_buffer_size { + /* 15 bytes = 8 byte (roi) + 6 byte(crc) + 1 byte(phy_id) */ + ta_securedisplay_i2c_buffer_size = 15, +}; + +/** input/output structures for secure display commands */ +/**********************************************************/ +/** + * input structures + */ + +/** @struct ta_securedisplay_send_roi_crc_input + * physical id to determine which dio scratch register should be used to get roi + */ +struct ta_securedisplay_send_roi_crc_input { + uint32_t phy_id; /* physical id */ +}; + +/** @union ta_securedisplay_cmd_input + * input buffer + */ +union ta_securedisplay_cmd_input { + /* send roi and crc input buffer format */ + struct ta_securedisplay_send_roi_crc_input send_roi_crc; + uint32_t reserved[4]; +}; + +/** + * output structures + */ + +/** @struct ta_securedisplay_query_ta_output + * output buffer format for query ta whether ta is responding used only for validation purpose + */ +struct ta_securedisplay_query_ta_output { + /* return value from ta when it is queried for validation purpose only */ + uint32_t query_cmd_ret; +}; + +/** @struct ta_securedisplay_send_roi_crc_output + * output buffer format for send roi crc command which will pass i2c buffer created inside ta + * and used to write to i2c used only for validation purpose + */ +struct ta_securedisplay_send_roi_crc_output { + uint8_t i2c_buf[ta_securedisplay_i2c_buffer_size]; /* i2c buffer */ + uint8_t reserved; +}; + +/** @union ta_securedisplay_cmd_output + * output buffer + */ +union ta_securedisplay_cmd_output { + /* query ta output buffer format used only for validation purpose*/ + struct ta_securedisplay_query_ta_output query_ta; + /* send roi crc output buffer format used only for validation purpose */ + struct ta_securedisplay_send_roi_crc_output send_roi_crc; + uint32_t reserved[4]; +}; + +/** @struct securedisplay_cmd + * secure display command which is shared buffer memory + */ +struct securedisplay_cmd { + uint32_t cmd_id; /* +0 bytes command id */ + enum ta_securedisplay_status status; /* +4 bytes status of secure display ta */ + uint32_t reserved[2]; /* +8 bytes reserved */ + union ta_securedisplay_cmd_input securedisplay_in_message; /* +16 bytes input buffer */ + union ta_securedisplay_cmd_output securedisplay_out_message;/* +32 bytes output buffer */ + /**@note total 48 bytes */ +}; + +#endif //_ta_securedisplay_if_h +
|
Graphics
|
a944c12724b7ba774126d87d5d9c7f6ef179e237
|
jinzhou su huang rui ray huang amd com alex deucher alexander deucher amd com
|
drivers
|
gpu
|
amd, amdgpu, drm
|
drm/amdgpu: add secure display ta interface
|
add interface to load, unload, invoke command for secure display ta.
|
this release allows to map an uid to a different one in a mount; it also adds support for selecting the preemption model at runtime; support for a low-overhead memory error detector designed to be used in production; support for the acrn hypervisor designed for embedded systems; btrfs initial support for zoned devices, subpage blocks sizes and performance improvements; support for eager nfs writes; support for a thermal power management to control the surface temperature of embedded devices in an unified way; the napi polling can be moved to a kernel thread; and support for non-blocking path lookups. as always, there are many other features, new drivers, improvements and fixes.
|
add secure display ta interface
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'cryptography', 'security', 'networking', 'architectures x86 arm risc-v powerpc mips csky s390 pa-risc c6x']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'cpu frequency scaling', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'cryptography hardware acceleration', 'pci', 'non-transparent bridge (ntb)', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'cxl (compute express link)', 'various']
|
['amdgpu ']
|
['h', 'c', 'makefile']
| 8
| 438
| 3
|
--- diff --git a/drivers/gpu/drm/amd/amdgpu/makefile b/drivers/gpu/drm/amd/amdgpu/makefile --- a/drivers/gpu/drm/amd/amdgpu/makefile +++ b/drivers/gpu/drm/amd/amdgpu/makefile - amdgpu_fw_attestation.o + amdgpu_fw_attestation.o amdgpu_securedisplay.o diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c +#include "amdgpu_securedisplay.h" + amdgpu_securedisplay_debugfs_init(adev); + diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c +#include "amdgpu_securedisplay.h" +/* securedisplay start */ +static int psp_securedisplay_init_shared_buf(struct psp_context *psp) +{ + int ret; + + /* + * allocate 16k memory aligned to 4k from frame buffer (local + * physical) for sa ta <-> driver + */ + ret = amdgpu_bo_create_kernel(psp->adev, psp_securedisplay_shared_mem_size, + page_size, amdgpu_gem_domain_vram, + &psp->securedisplay_context.securedisplay_shared_bo, + &psp->securedisplay_context.securedisplay_shared_mc_addr, + &psp->securedisplay_context.securedisplay_shared_buf); + + return ret; +} + +static int psp_securedisplay_load(struct psp_context *psp) +{ + int ret; + struct psp_gfx_cmd_resp *cmd; + + cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), gfp_kernel); + if (!cmd) + return -enomem; + + memset(psp->fw_pri_buf, 0, psp_1_meg); + memcpy(psp->fw_pri_buf, psp->ta_securedisplay_start_addr, psp->ta_securedisplay_ucode_size); + + psp_prep_ta_load_cmd_buf(cmd, + psp->fw_pri_mc_addr, + psp->ta_securedisplay_ucode_size, + psp->securedisplay_context.securedisplay_shared_mc_addr, + psp_securedisplay_shared_mem_size); + + ret = psp_cmd_submit_buf(psp, null, cmd, psp->fence_buf_mc_addr); + + if (ret) + goto failed; + + psp->securedisplay_context.securedisplay_initialized = true; + psp->securedisplay_context.session_id = cmd->resp.session_id; + mutex_init(&psp->securedisplay_context.mutex); + +failed: + kfree(cmd); + return ret; +} + +static int psp_securedisplay_unload(struct psp_context *psp) +{ + int ret; + struct psp_gfx_cmd_resp *cmd; + + cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), gfp_kernel); + if (!cmd) + return -enomem; + + psp_prep_ta_unload_cmd_buf(cmd, psp->securedisplay_context.session_id); + + ret = psp_cmd_submit_buf(psp, null, cmd, psp->fence_buf_mc_addr); + + kfree(cmd); + + return ret; +} + +static int psp_securedisplay_initialize(struct psp_context *psp) +{ + int ret; + struct securedisplay_cmd *securedisplay_cmd; + + /* + * todo: bypass the initialize in sriov for now + */ + if (amdgpu_sriov_vf(psp->adev)) + return 0; + + if (!psp->adev->psp.ta_securedisplay_ucode_size || + !psp->adev->psp.ta_securedisplay_start_addr) { + dev_info(psp->adev->dev, "securedisplay: securedisplay ta ucode is not available "); + return 0; + } + + if (!psp->securedisplay_context.securedisplay_initialized) { + ret = psp_securedisplay_init_shared_buf(psp); + if (ret) + return ret; + } + + ret = psp_securedisplay_load(psp); + if (ret) + return ret; + + psp_prep_securedisplay_cmd_buf(psp, &securedisplay_cmd, + ta_securedisplay_command__query_ta); + + ret = psp_securedisplay_invoke(psp, ta_securedisplay_command__query_ta); + if (ret) { + psp_securedisplay_unload(psp); + + amdgpu_bo_free_kernel(&psp->securedisplay_context.securedisplay_shared_bo, + &psp->securedisplay_context.securedisplay_shared_mc_addr, + &psp->securedisplay_context.securedisplay_shared_buf); + + psp->securedisplay_context.securedisplay_initialized = false; + + dev_err(psp->adev->dev, "securedisplay ta initialize fail. "); + return -einval; + } + + if (securedisplay_cmd->status != ta_securedisplay_status__success) { + psp_securedisplay_parse_resp_status(psp, securedisplay_cmd->status); + dev_err(psp->adev->dev, "securedisplay: query securedisplay ta failed. ret 0x%x ", + securedisplay_cmd->securedisplay_out_message.query_ta.query_cmd_ret); + } + + return 0; +} + +static int psp_securedisplay_terminate(struct psp_context *psp) +{ + int ret; + + /* + * todo:bypass the terminate in sriov for now + */ + if (amdgpu_sriov_vf(psp->adev)) + return 0; + + if (!psp->securedisplay_context.securedisplay_initialized) + return 0; + + ret = psp_securedisplay_unload(psp); + if (ret) + return ret; + + psp->securedisplay_context.securedisplay_initialized = false; + + /* free securedisplay shared memory */ + amdgpu_bo_free_kernel(&psp->securedisplay_context.securedisplay_shared_bo, + &psp->securedisplay_context.securedisplay_shared_mc_addr, + &psp->securedisplay_context.securedisplay_shared_buf); + + return ret; +} + +int psp_securedisplay_invoke(struct psp_context *psp, uint32_t ta_cmd_id) +{ + int ret; + + if (!psp->securedisplay_context.securedisplay_initialized) + return -einval; + + if (ta_cmd_id != ta_securedisplay_command__query_ta && + ta_cmd_id != ta_securedisplay_command__send_roi_crc) + return -einval; + + mutex_lock(&psp->securedisplay_context.mutex); + + ret = psp_ta_invoke(psp, ta_cmd_id, psp->securedisplay_context.session_id); + + mutex_unlock(&psp->securedisplay_context.mutex); + + return ret; +} +/* securedisplay end */ + + + ret = psp_securedisplay_initialize(psp); + if (ret) + dev_err(psp->adev->dev, + "securedisplay: failed to initialize securedisplay "); + psp_securedisplay_terminate(psp); + ret = psp_securedisplay_terminate(psp); + if (ret) { + drm_error("failed to terminate securedisplay ta "); + return ret; + } + + ret = psp_securedisplay_initialize(psp); + if (ret) + dev_err(psp->adev->dev, + "securedisplay: failed to initialize securedisplay "); + case ta_fw_type_psp_securedisplay: + psp->ta_securedisplay_ucode_version = le32_to_cpu(desc->fw_version); + psp->ta_securedisplay_ucode_size = le32_to_cpu(desc->size_bytes); + psp->ta_securedisplay_start_addr = ucode_start_addr; + break; diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h +#include "ta_securedisplay_if.h" +#define psp_securedisplay_shared_mem_size 0x4000 +struct psp_securedisplay_context { + bool securedisplay_initialized; + uint32_t session_id; + struct amdgpu_bo *securedisplay_shared_bo; + uint64_t securedisplay_shared_mc_addr; + void *securedisplay_shared_buf; + struct mutex mutex; +}; + + uint32_t ta_securedisplay_ucode_version; + uint32_t ta_securedisplay_ucode_size; + uint8_t *ta_securedisplay_start_addr; + + struct psp_securedisplay_context securedisplay_context; +int psp_securedisplay_invoke(struct psp_context *psp, uint32_t ta_cmd_id); diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_securedisplay.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_securedisplay.c --- /dev/null +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_securedisplay.c +/* + * copyright 2021 advanced micro devices, inc. + * + * permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "software"), + * to deal in the software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the software, and to permit persons to whom the + * software is furnished to do so, subject to the following conditions: + * + * the above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the software. + * + * the software is provided "as is", without warranty of any kind, express or + * implied, including but not limited to the warranties of merchantability, + * fitness for a particular purpose and noninfringement. in no event shall + * the copyright holder(s) or author(s) be liable for any claim, damages or + * other liability, whether in an action of contract, tort or otherwise, + * arising from, out of or in connection with the software or the use or + * other dealings in the software. + * + * + */ +#include <linux/debugfs.h> +#include <linux/pm_runtime.h> + +#include "amdgpu.h" +#include "amdgpu_securedisplay.h" + +/** + * doc: amdgpu securedisplay debugfs test interface + * + * how to use? + * echo opcode <value> > <debugfs_dir>/dri/xxx/securedisplay_test + * eg. echo 1 > <debugfs_dir>/dri/xxx/securedisplay_test + * eg. echo 2 phy_id > <debugfs_dir>/dri/xxx/securedisplay_test + * + * opcode: + * 1:query whether ta is responding used only for validation pupose + * 2: send region of interest and crc value to i2c. (uint32)phy_id is + * send to determine which dio scratch register should be used to get + * roi and receive i2c_buf as the output. + * + * you can refer more detail from header file ta_securedisplay_if.h + * + */ + +void psp_securedisplay_parse_resp_status(struct psp_context *psp, + enum ta_securedisplay_status status) +{ + switch (status) { + case ta_securedisplay_status__success: + break; + case ta_securedisplay_status__generic_failure: + dev_err(psp->adev->dev, "secure display: generic failure."); + break; + case ta_securedisplay_status__invalid_parameter: + dev_err(psp->adev->dev, "secure display: invalid parameter."); + break; + case ta_securedisplay_status__null_pointer: + dev_err(psp->adev->dev, "secure display: null pointer."); + break; + case ta_securedisplay_status__i2c_write_error: + dev_err(psp->adev->dev, "secure display: failed to write to i2c."); + break; + case ta_securedisplay_status__read_dio_scratch_error: + dev_err(psp->adev->dev, "secure display: failed to read dio scratch register."); + break; + case ta_securedisplay_status__read_crc_error: + dev_err(psp->adev->dev, "secure display: failed to read crc"); + break; + default: + dev_err(psp->adev->dev, "secure display: failed to parse status: %d ", status); + } +} + +void psp_prep_securedisplay_cmd_buf(struct psp_context *psp, struct securedisplay_cmd **cmd, + enum ta_securedisplay_command command_id) +{ + *cmd = (struct securedisplay_cmd *)psp->securedisplay_context.securedisplay_shared_buf; + memset(*cmd, 0, sizeof(struct securedisplay_cmd)); + (*cmd)->status = ta_securedisplay_status__generic_failure; + (*cmd)->cmd_id = command_id; +} + +static ssize_t amdgpu_securedisplay_debugfs_write(struct file *f, const char __user *buf, + size_t size, loff_t *pos) +{ + struct amdgpu_device *adev = (struct amdgpu_device *)file_inode(f)->i_private; + struct psp_context *psp = &adev->psp; + struct securedisplay_cmd *securedisplay_cmd; + struct drm_device *dev = adev_to_drm(adev); + uint32_t phy_id; + uint32_t op; + int i; + char str[64]; + char i2c_output[256]; + int ret; + + if (*pos || size > sizeof(str) - 1) + return -einval; + + memset(str, 0, sizeof(str)); + ret = copy_from_user(str, buf, size); + if (ret) + return -efault; + + ret = pm_runtime_get_sync(dev->dev); + if (ret < 0) { + pm_runtime_put_autosuspend(dev->dev); + return ret; + } + + if (size < 3) + sscanf(str, "%u ", &op); + else + sscanf(str, "%u %u", &op, &phy_id); + + switch (op) { + case 1: + psp_prep_securedisplay_cmd_buf(psp, &securedisplay_cmd, + ta_securedisplay_command__query_ta); + ret = psp_securedisplay_invoke(psp, ta_securedisplay_command__query_ta); + if (!ret) { + if (securedisplay_cmd->status == ta_securedisplay_status__success) + dev_info(adev->dev, "securedisplay: query securedisplay ta ret is 0x%x ", + securedisplay_cmd->securedisplay_out_message.query_ta.query_cmd_ret); + else + psp_securedisplay_parse_resp_status(psp, securedisplay_cmd->status); + } + break; + case 2: + psp_prep_securedisplay_cmd_buf(psp, &securedisplay_cmd, + ta_securedisplay_command__send_roi_crc); + securedisplay_cmd->securedisplay_in_message.send_roi_crc.phy_id = phy_id; + ret = psp_securedisplay_invoke(psp, ta_securedisplay_command__send_roi_crc); + if (!ret) { + if (securedisplay_cmd->status == ta_securedisplay_status__success) { + memset(i2c_output, 0, sizeof(i2c_output)); + for (i = 0; i < ta_securedisplay_i2c_buffer_size; i++) + sprintf(i2c_output, "%s 0x%x", i2c_output, + securedisplay_cmd->securedisplay_out_message.send_roi_crc.i2c_buf[i]); + dev_info(adev->dev, "securedisplay: i2c buffer out put is :%s ", i2c_output); + } else { + psp_securedisplay_parse_resp_status(psp, securedisplay_cmd->status); + } + } + break; + default: + dev_err(adev->dev, "invalid input: %s ", str); + } + + pm_runtime_mark_last_busy(dev->dev); + pm_runtime_put_autosuspend(dev->dev); + + return size; +} + +static const struct file_operations amdgpu_securedisplay_debugfs_ops = { + .owner = this_module, + .read = null, + .write = amdgpu_securedisplay_debugfs_write, + .llseek = default_llseek +}; + +void amdgpu_securedisplay_debugfs_init(struct amdgpu_device *adev) +{ +#if defined(config_debug_fs) + + if (!adev->psp.securedisplay_context.securedisplay_initialized) + return; + + debugfs_create_file("securedisplay_test", s_iwusr, adev_to_drm(adev)->primary->debugfs_root, + adev, &amdgpu_securedisplay_debugfs_ops); +#endif +} diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_securedisplay.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_securedisplay.h --- /dev/null +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_securedisplay.h +/* + * copyright 2021 advanced micro devices, inc. + * + * permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "software"), + * to deal in the software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the software, and to permit persons to whom the + * software is furnished to do so, subject to the following conditions: + * + * the above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the software. + * + * the software is provided "as is", without warranty of any kind, express or + * implied, including but not limited to the warranties of merchantability, + * fitness for a particular purpose and noninfringement. in no event shall + * the copyright holder(s) or author(s) be liable for any claim, damages or + * other liability, whether in an action of contract, tort or otherwise, + * arising from, out of or in connection with the software or the use or + * other dealings in the software. + * + * + */ +#ifndef _amdgpu_securedisplay_h +#define _amdgpu_securedisplay_h + +#include "amdgpu.h" +#include "ta_securedisplay_if.h" + +void amdgpu_securedisplay_debugfs_init(struct amdgpu_device *adev); +void psp_securedisplay_parse_resp_status(struct psp_context *psp, + enum ta_securedisplay_status status); +void psp_prep_securedisplay_cmd_buf(struct psp_context *psp, struct securedisplay_cmd **cmd, + enum ta_securedisplay_command command_id); + +#endif diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.h --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.h + uint32_t ta_securedisplay_ucode_version; + uint32_t ta_securedisplay_offset_bytes; + uint32_t ta_securedisplay_size_bytes; + ta_fw_type_psp_securedisplay, diff --git a/drivers/gpu/drm/amd/amdgpu/psp_v10_0.c b/drivers/gpu/drm/amd/amdgpu/psp_v10_0.c --- a/drivers/gpu/drm/amd/amdgpu/psp_v10_0.c +++ b/drivers/gpu/drm/amd/amdgpu/psp_v10_0.c - adev->psp.ta_fw_version = le32_to_cpu(ta_hdr->header.ucode_version); - + + adev->psp.ta_securedisplay_ucode_version = + le32_to_cpu(ta_hdr->ta_securedisplay_ucode_version); + adev->psp.ta_securedisplay_ucode_size = + le32_to_cpu(ta_hdr->ta_securedisplay_size_bytes); + adev->psp.ta_securedisplay_start_addr = + (uint8_t *)adev->psp.ta_hdcp_start_addr + + le32_to_cpu(ta_hdr->ta_securedisplay_offset_bytes); + + adev->psp.ta_fw_version = le32_to_cpu(ta_hdr->header.ucode_version);
|
Graphics
|
ecaafb7b5ab6406587341d8727f237b3ee00dedf
|
jinzhou su
|
drivers
|
gpu
|
amd, amdgpu, drm
|
drm/amdgpu: add green_sardine device id (v2)
|
add green_sardine pci id support and map it to renoir asic type.
|
this release allows to map an uid to a different one in a mount; it also adds support for selecting the preemption model at runtime; support for a low-overhead memory error detector designed to be used in production; support for the acrn hypervisor designed for embedded systems; btrfs initial support for zoned devices, subpage blocks sizes and performance improvements; support for eager nfs writes; support for a thermal power management to control the surface temperature of embedded devices in an unified way; the napi polling can be moved to a kernel thread; and support for non-blocking path lookups. as always, there are many other features, new drivers, improvements and fixes.
|
add green_sardine device id (v2)
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'cryptography', 'security', 'networking', 'architectures x86 arm risc-v powerpc mips csky s390 pa-risc c6x']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'cpu frequency scaling', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'cryptography hardware acceleration', 'pci', 'non-transparent bridge (ntb)', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'cxl (compute express link)', 'various']
|
['amdgpu ']
|
['c']
| 1
| 1
| 0
|
--- diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c + {0x1002, 0x1638, pci_any_id, pci_any_id, 0, 0, chip_renoir|amd_is_apu},
|
Graphics
|
8bf0835132c19437e1530621b730dd4f29fe938e
|
prike liang
|
drivers
|
gpu
|
amd, amdgpu, drm
|
amdgpu: add missing sienna cichlid did
|
the purpose of this patch is to add a missing device id for sienna cichlid. the missing id "0x73a1" is now added to the "amdgpu_drv.c" file.
|
this release allows to map an uid to a different one in a mount; it also adds support for selecting the preemption model at runtime; support for a low-overhead memory error detector designed to be used in production; support for the acrn hypervisor designed for embedded systems; btrfs initial support for zoned devices, subpage blocks sizes and performance improvements; support for eager nfs writes; support for a thermal power management to control the surface temperature of embedded devices in an unified way; the napi polling can be moved to a kernel thread; and support for non-blocking path lookups. as always, there are many other features, new drivers, improvements and fixes.
|
add missing sienna cichlid did
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'cryptography', 'security', 'networking', 'architectures x86 arm risc-v powerpc mips csky s390 pa-risc c6x']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'cpu frequency scaling', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'cryptography hardware acceleration', 'pci', 'non-transparent bridge (ntb)', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'cxl (compute express link)', 'various']
|
['amdgpu ']
|
['c']
| 1
| 1
| 0
|
--- diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c + {0x1002, 0x73a1, pci_any_id, pci_any_id, 0, 0, chip_sienna_cichlid},
|
Graphics
|
d26bbbcc160f6d9feabed73dca62b9e8b86671b4
|
ori messinger kent russell kent russell amd com
|
drivers
|
gpu
|
amd, amdgpu, drm
|
drm/amdgpu: add new device id for renior
|
add did 0x164c into pciidlist under chip_renoir family.
|
this release allows to map an uid to a different one in a mount; it also adds support for selecting the preemption model at runtime; support for a low-overhead memory error detector designed to be used in production; support for the acrn hypervisor designed for embedded systems; btrfs initial support for zoned devices, subpage blocks sizes and performance improvements; support for eager nfs writes; support for a thermal power management to control the surface temperature of embedded devices in an unified way; the napi polling can be moved to a kernel thread; and support for non-blocking path lookups. as always, there are many other features, new drivers, improvements and fixes.
|
add new device id for renior
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'cryptography', 'security', 'networking', 'architectures x86 arm risc-v powerpc mips csky s390 pa-risc c6x']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'cpu frequency scaling', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'cryptography hardware acceleration', 'pci', 'non-transparent bridge (ntb)', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'cxl (compute express link)', 'various']
|
['amdgpu ']
|
['c']
| 2
| 3
| 1
|
--- diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c + {0x1002, 0x164c, pci_any_id, pci_any_id, 0, 0, chip_renoir|amd_is_apu}, diff --git a/drivers/gpu/drm/amd/amdgpu/soc15.c b/drivers/gpu/drm/amd/amdgpu/soc15.c --- a/drivers/gpu/drm/amd/amdgpu/soc15.c +++ b/drivers/gpu/drm/amd/amdgpu/soc15.c - if (adev->pdev->device == 0x1636) + if ((adev->pdev->device == 0x1636) || + (adev->pdev->device == 0x164c))
|
Graphics
|
278cdb6834901658a81a1e22f5799aa15dca5029
|
mengwang huang rui ray huang amd com
|
drivers
|
gpu
|
amd, amdgpu, drm
|
drm/amdgpu: support aspm for some specific asic
|
support to program aspm and ltr for sienna cichlid and forward asic. disable aspm for sienna cichlid and forward asic by default.
|
this release allows to map an uid to a different one in a mount; it also adds support for selecting the preemption model at runtime; support for a low-overhead memory error detector designed to be used in production; support for the acrn hypervisor designed for embedded systems; btrfs initial support for zoned devices, subpage blocks sizes and performance improvements; support for eager nfs writes; support for a thermal power management to control the surface temperature of embedded devices in an unified way; the napi polling can be moved to a kernel thread; and support for non-blocking path lookups. as always, there are many other features, new drivers, improvements and fixes.
|
support aspm for some specific asic
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'cryptography', 'security', 'networking', 'architectures x86 arm risc-v powerpc mips csky s390 pa-risc c6x']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'cpu frequency scaling', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'cryptography hardware acceleration', 'pci', 'non-transparent bridge (ntb)', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'cxl (compute express link)', 'various']
|
['amdgpu ']
|
['h', 'c']
| 3
| 124
| 6
|
--- diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_nbio.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_nbio.h --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_nbio.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_nbio.h + void (*program_aspm)(struct amdgpu_device *adev); diff --git a/drivers/gpu/drm/amd/amdgpu/nbio_v2_3.c b/drivers/gpu/drm/amd/amdgpu/nbio_v2_3.c --- a/drivers/gpu/drm/amd/amdgpu/nbio_v2_3.c +++ b/drivers/gpu/drm/amd/amdgpu/nbio_v2_3.c +#define smnpcie_lc_cntl3 0x111402d4 +#define smnpcie_lc_cntl6 0x111402ec +#define smnpcie_lc_cntl7 0x111402f0 +#define smnbif_cfg_dev0_epf0_device_cntl2 0x1014008c +#define smnrcc_ep_dev0_0_ep_pcie_tx_ltr_cntl 0x10123538 +#define smnbif_cfg_dev0_epf0_pcie_ltr_cap 0x10140324 +#define smnpswusp0_pcie_lc_cntl2 0x111402c4 +#define smnnbif_mgcg_ctrl_lclk 0x1013a21c +static void nbio_v2_3_program_ltr(struct amdgpu_device *adev) +{ + uint32_t def, data; + + wreg32_pcie(smnrcc_ep_dev0_0_ep_pcie_tx_ltr_cntl, 0x75eb); + + def = data = rreg32_soc15(nbio, 0, mmrcc_bif_strap2); + data &= ~rcc_bif_strap2__strap_ltr_in_aspml1_dis_mask; + if (def != data) + wreg32_soc15(nbio, 0, mmrcc_bif_strap2, data); + + def = data = rreg32_pcie(smnrcc_ep_dev0_0_ep_pcie_tx_ltr_cntl); + data &= ~ep_pcie_tx_ltr_cntl__ltr_priv_msg_dis_in_pm_non_d0_mask; + if (def != data) + wreg32_pcie(smnrcc_ep_dev0_0_ep_pcie_tx_ltr_cntl, data); + + def = data = rreg32_pcie(smnbif_cfg_dev0_epf0_device_cntl2); + data |= bif_cfg_dev0_epf0_device_cntl2__ltr_en_mask; + if (def != data) + wreg32_pcie(smnbif_cfg_dev0_epf0_device_cntl2, data); +} + +static void nbio_v2_3_program_aspm(struct amdgpu_device *adev) +{ + uint32_t def, data; + + def = data = rreg32_pcie(smnpcie_lc_cntl); + data &= ~pcie_lc_cntl__lc_l1_inactivity_mask; + data &= ~pcie_lc_cntl__lc_l0s_inactivity_mask; + data |= pcie_lc_cntl__lc_pmi_to_l1_dis_mask; + if (def != data) + wreg32_pcie(smnpcie_lc_cntl, data); + + def = data = rreg32_pcie(smnpcie_lc_cntl7); + data |= pcie_lc_cntl7__lc_nbif_aspm_input_en_mask; + if (def != data) + wreg32_pcie(smnpcie_lc_cntl7, data); + + def = data = rreg32_pcie(smnnbif_mgcg_ctrl_lclk); + data |= nbif_mgcg_ctrl_lclk__nbif_mgcg_reg_dis_lclk_mask; + if (def != data) + wreg32_pcie(smnnbif_mgcg_ctrl_lclk, data); + + def = data = rreg32_pcie(smnpcie_lc_cntl3); + data |= pcie_lc_cntl3__lc_dsc_dont_enter_l23_after_pme_ack_mask; + if (def != data) + wreg32_pcie(smnpcie_lc_cntl3, data); + + def = data = rreg32_soc15(nbio, 0, mmrcc_bif_strap3); + data &= ~rcc_bif_strap3__strap_vlink_aspm_idle_timer_mask; + data &= ~rcc_bif_strap3__strap_vlink_pm_l1_entry_timer_mask; + if (def != data) + wreg32_soc15(nbio, 0, mmrcc_bif_strap3, data); + + def = data = rreg32_soc15(nbio, 0, mmrcc_bif_strap5); + data &= ~rcc_bif_strap5__strap_vlink_ldn_entry_timer_mask; + if (def != data) + wreg32_soc15(nbio, 0, mmrcc_bif_strap5, data); + + def = data = rreg32_pcie(smnbif_cfg_dev0_epf0_device_cntl2); + data &= ~bif_cfg_dev0_epf0_device_cntl2__ltr_en_mask; + if (def != data) + wreg32_pcie(smnbif_cfg_dev0_epf0_device_cntl2, data); + + wreg32_pcie(smnbif_cfg_dev0_epf0_pcie_ltr_cap, 0x10011001); + + def = data = rreg32_pcie(smnpswusp0_pcie_lc_cntl2); + data |= pswusp0_pcie_lc_cntl2__lc_allow_pdwn_in_l1_mask | + pswusp0_pcie_lc_cntl2__lc_allow_pdwn_in_l23_mask; + data &= ~pswusp0_pcie_lc_cntl2__lc_rcv_l0_to_rcv_l0s_dis_mask; + if (def != data) + wreg32_pcie(smnpswusp0_pcie_lc_cntl2, data); + + def = data = rreg32_pcie(smnpcie_lc_cntl6); + data |= pcie_lc_cntl6__lc_l1_powerdown_mask | + pcie_lc_cntl6__lc_rx_l0s_standby_en_mask; + if (def != data) + wreg32_pcie(smnpcie_lc_cntl6, data); + + nbio_v2_3_program_ltr(adev); + + def = data = rreg32_soc15(nbio, 0, mmrcc_bif_strap3); + data |= 0x5de0 << rcc_bif_strap3__strap_vlink_aspm_idle_timer__shift; + data |= 0x0010 << rcc_bif_strap3__strap_vlink_pm_l1_entry_timer__shift; + if (def != data) + wreg32_soc15(nbio, 0, mmrcc_bif_strap3, data); + + def = data = rreg32_soc15(nbio, 0, mmrcc_bif_strap5); + data |= 0x0010 << rcc_bif_strap5__strap_vlink_ldn_entry_timer__shift; + if (def != data) + wreg32_soc15(nbio, 0, mmrcc_bif_strap5, data); + + def = data = rreg32_pcie(smnpcie_lc_cntl); + data &= ~pcie_lc_cntl__lc_l0s_inactivity_mask; + data |= 0x9 << pcie_lc_cntl__lc_l1_inactivity__shift; + data |= 0x1 << pcie_lc_cntl__lc_pmi_to_l1_dis__shift; + if (def != data) + wreg32_pcie(smnpcie_lc_cntl, data); + + def = data = rreg32_pcie(smnpcie_lc_cntl3); + data &= ~pcie_lc_cntl3__lc_dsc_dont_enter_l23_after_pme_ack_mask; + if (def != data) + wreg32_pcie(smnpcie_lc_cntl3, data); +} + + .program_aspm = nbio_v2_3_program_aspm, diff --git a/drivers/gpu/drm/amd/amdgpu/nv.c b/drivers/gpu/drm/amd/amdgpu/nv.c --- a/drivers/gpu/drm/amd/amdgpu/nv.c +++ b/drivers/gpu/drm/amd/amdgpu/nv.c - - if (amdgpu_aspm == 0) + if (amdgpu_aspm != 1) - /* todo */ + if ((adev->asic_type >= chip_sienna_cichlid) && + !(adev->flags & amd_is_apu) && + (adev->nbio.funcs->program_aspm)) + adev->nbio.funcs->program_aspm(adev); + -#if 0 - if (adev->nbio.funcs->enable_aspm) + if ((adev->asic_type >= chip_sienna_cichlid) && + !(adev->flags & amd_is_apu) && + (adev->nbio.funcs->enable_aspm)) -#endif
|
Graphics
|
e1edaeafeb667688125ef1c4e2a098d2c798fc24
|
likun gao kenneth feng kenneth feng amd com hawking zhang hawking zhang amd com
|
drivers
|
gpu
|
amd, amdgpu, drm
|
drm/i915/display: add hdr capability detection for lspcon
|
lspcon firmware exposes hdr capability through lpcon_capabilities dpcd register. lspcon implementations capable of supporting hdr set hdr_capability bit in lspcon_capabilities to 1. this patch reads the same, detects the hdr capability and adds this to intel_lspcon struct.
|
this release allows to map an uid to a different one in a mount; it also adds support for selecting the preemption model at runtime; support for a low-overhead memory error detector designed to be used in production; support for the acrn hypervisor designed for embedded systems; btrfs initial support for zoned devices, subpage blocks sizes and performance improvements; support for eager nfs writes; support for a thermal power management to control the surface temperature of embedded devices in an unified way; the napi polling can be moved to a kernel thread; and support for non-blocking path lookups. as always, there are many other features, new drivers, improvements and fixes.
|
enable hdr on mca lspcon based gen9 devices
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'cryptography', 'security', 'networking', 'architectures x86 arm risc-v powerpc mips csky s390 pa-risc c6x']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'cpu frequency scaling', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'cryptography hardware acceleration', 'pci', 'non-transparent bridge (ntb)', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'cxl (compute express link)', 'various']
|
['intel ']
|
['h', 'c']
| 3
| 29
| 0
|
--- diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h --- a/drivers/gpu/drm/i915/display/intel_display_types.h +++ b/drivers/gpu/drm/i915/display/intel_display_types.h + bool hdr_supported; diff --git a/drivers/gpu/drm/i915/display/intel_lspcon.c b/drivers/gpu/drm/i915/display/intel_lspcon.c --- a/drivers/gpu/drm/i915/display/intel_lspcon.c +++ b/drivers/gpu/drm/i915/display/intel_lspcon.c +#define dpcd_mca_lspcon_hdr_status 0x70003 + +void lspcon_detect_hdr_capability(struct intel_lspcon *lspcon) +{ + struct intel_digital_port *dig_port = + container_of(lspcon, struct intel_digital_port, lspcon); + struct drm_device *dev = dig_port->base.base.dev; + struct intel_dp *dp = lspcon_to_intel_dp(lspcon); + u8 hdr_caps; + int ret; + + /* enable hdr for mca based lspcon devices */ + if (lspcon->vendor == lspcon_vendor_mca) + ret = drm_dp_dpcd_read(&dp->aux, dpcd_mca_lspcon_hdr_status, + &hdr_caps, 1); + else + return; + + if (ret < 0) { + drm_dbg_kms(dev, "hdr capability detection failed "); + lspcon->hdr_supported = false; + } else if (hdr_caps & 0x1) { + drm_dbg_kms(dev, "lspcon capable of hdr "); + lspcon->hdr_supported = true; + } +} + diff --git a/drivers/gpu/drm/i915/display/intel_lspcon.h b/drivers/gpu/drm/i915/display/intel_lspcon.h --- a/drivers/gpu/drm/i915/display/intel_lspcon.h +++ b/drivers/gpu/drm/i915/display/intel_lspcon.h +void lspcon_detect_hdr_capability(struct intel_lspcon *lspcon);
|
Graphics
|
81cc320aa3592ee257d1a4a5d72124546f981dad
|
uma shankar
|
drivers
|
gpu
|
display, drm, i915
|
drm/i915/display: enable hdr on gen9 devices with mca lspcon
|
gen9 hardware supports hdmi2.0 through lspcon chips. extending hdr support for mca lspcon based gen9 devices.
|
this release allows to map an uid to a different one in a mount; it also adds support for selecting the preemption model at runtime; support for a low-overhead memory error detector designed to be used in production; support for the acrn hypervisor designed for embedded systems; btrfs initial support for zoned devices, subpage blocks sizes and performance improvements; support for eager nfs writes; support for a thermal power management to control the surface temperature of embedded devices in an unified way; the napi polling can be moved to a kernel thread; and support for non-blocking path lookups. as always, there are many other features, new drivers, improvements and fixes.
|
enable hdr on mca lspcon based gen9 devices
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'cryptography', 'security', 'networking', 'architectures x86 arm risc-v powerpc mips csky s390 pa-risc c6x']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'cpu frequency scaling', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'cryptography hardware acceleration', 'pci', 'non-transparent bridge (ntb)', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'cxl (compute express link)', 'various']
|
['intel ']
|
['h', 'c']
| 3
| 26
| 17
|
--- diff --git a/drivers/gpu/drm/i915/display/intel_hdmi.c b/drivers/gpu/drm/i915/display/intel_hdmi.c --- a/drivers/gpu/drm/i915/display/intel_hdmi.c +++ b/drivers/gpu/drm/i915/display/intel_hdmi.c -static void hsw_write_infoframe(struct intel_encoder *encoder, - const struct intel_crtc_state *crtc_state, - unsigned int type, - const void *frame, ssize_t len) +void hsw_write_infoframe(struct intel_encoder *encoder, + const struct intel_crtc_state *crtc_state, + unsigned int type, + const void *frame, ssize_t len) diff --git a/drivers/gpu/drm/i915/display/intel_lspcon.c b/drivers/gpu/drm/i915/display/intel_lspcon.c --- a/drivers/gpu/drm/i915/display/intel_lspcon.c +++ b/drivers/gpu/drm/i915/display/intel_lspcon.c - bool ret; + bool ret = true; - /* lspcon only needs avi if */ - if (type != hdmi_infoframe_type_avi) + switch (type) { + case hdmi_infoframe_type_avi: + if (lspcon->vendor == lspcon_vendor_mca) + ret = _lspcon_write_avi_infoframe_mca(&intel_dp->aux, + frame, len); + else + ret = _lspcon_write_avi_infoframe_parade(&intel_dp->aux, + frame, len); + break; + case hdmi_packet_type_gamut_metadata: + drm_dbg_kms(encoder->base.dev, "update hdr metadata for lspcon "); + /* it uses the legacy hsw implementation for the same */ + hsw_write_infoframe(encoder, crtc_state, type, frame, len); + break; + default: - - if (lspcon->vendor == lspcon_vendor_mca) - ret = _lspcon_write_avi_infoframe_mca(&intel_dp->aux, - frame, len); - else - ret = _lspcon_write_avi_infoframe_parade(&intel_dp->aux, - frame, len); + } - drm_error("failed to write avi infoframes "); + drm_error("failed to write infoframes "); - - drm_debug_driver("avi infoframes updated successfully "); diff --git a/drivers/gpu/drm/i915/display/intel_lspcon.h b/drivers/gpu/drm/i915/display/intel_lspcon.h --- a/drivers/gpu/drm/i915/display/intel_lspcon.h +++ b/drivers/gpu/drm/i915/display/intel_lspcon.h +void hsw_write_infoframe(struct intel_encoder *encoder, + const struct intel_crtc_state *crtc_state, + unsigned int type, + const void *frame, ssize_t len);
|
Graphics
|
1a911350dd6c777b4a08ca60fe6e2249fd3c254a
|
uma shankar
|
drivers
|
gpu
|
display, drm, i915
|
drm/i915/display: attach hdr property for capable gen9 devices
|
attach hdr property for gen9 devices with mca lspcon chips.
|
this release allows to map an uid to a different one in a mount; it also adds support for selecting the preemption model at runtime; support for a low-overhead memory error detector designed to be used in production; support for the acrn hypervisor designed for embedded systems; btrfs initial support for zoned devices, subpage blocks sizes and performance improvements; support for eager nfs writes; support for a thermal power management to control the surface temperature of embedded devices in an unified way; the napi polling can be moved to a kernel thread; and support for non-blocking path lookups. as always, there are many other features, new drivers, improvements and fixes.
|
enable hdr on mca lspcon based gen9 devices
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'cryptography', 'security', 'networking', 'architectures x86 arm risc-v powerpc mips csky s390 pa-risc c6x']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'cpu frequency scaling', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'cryptography hardware acceleration', 'pci', 'non-transparent bridge (ntb)', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'cxl (compute express link)', 'various']
|
['intel ']
|
['h', 'c']
| 3
| 20
| 1
|
--- diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c --- a/drivers/gpu/drm/i915/display/intel_dp.c +++ b/drivers/gpu/drm/i915/display/intel_dp.c + struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); + struct intel_lspcon *lspcon = &dig_port->lspcon; + + if (!intel_bios_is_lspcon_present(i915, dig_port->base.port)) + return ret; + + /* + * todo: clean this up to handle lspcon init and resume more + * efficiently and streamlined. + */ + if (lspcon_init(dig_port)) { + lspcon_detect_hdr_capability(lspcon); + if (lspcon->hdr_supported) + drm_object_attach_property(&connector->base, + connector->dev->mode_config.hdr_output_metadata_property, + 0); + } + diff --git a/drivers/gpu/drm/i915/display/intel_lspcon.c b/drivers/gpu/drm/i915/display/intel_lspcon.c --- a/drivers/gpu/drm/i915/display/intel_lspcon.c +++ b/drivers/gpu/drm/i915/display/intel_lspcon.c -static bool lspcon_init(struct intel_digital_port *dig_port) +bool lspcon_init(struct intel_digital_port *dig_port) diff --git a/drivers/gpu/drm/i915/display/intel_lspcon.h b/drivers/gpu/drm/i915/display/intel_lspcon.h --- a/drivers/gpu/drm/i915/display/intel_lspcon.h +++ b/drivers/gpu/drm/i915/display/intel_lspcon.h +bool lspcon_init(struct intel_digital_port *dig_port);
|
Graphics
|
2e666613b24e3c7d2ae5cf5c1e264751bb5b2a8f
|
uma shankar
|
drivers
|
gpu
|
display, drm, i915
|
drm/i915/display: fixes quantization range for ycbcr output
|
this patch fixes the quantization range for ycbcr output on lspcon based devices.
|
this release allows to map an uid to a different one in a mount; it also adds support for selecting the preemption model at runtime; support for a low-overhead memory error detector designed to be used in production; support for the acrn hypervisor designed for embedded systems; btrfs initial support for zoned devices, subpage blocks sizes and performance improvements; support for eager nfs writes; support for a thermal power management to control the surface temperature of embedded devices in an unified way; the napi polling can be moved to a kernel thread; and support for non-blocking path lookups. as always, there are many other features, new drivers, improvements and fixes.
|
enable hdr on mca lspcon based gen9 devices
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'cryptography', 'security', 'networking', 'architectures x86 arm risc-v powerpc mips csky s390 pa-risc c6x']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'cpu frequency scaling', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'cryptography hardware acceleration', 'pci', 'non-transparent bridge (ntb)', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'cxl (compute express link)', 'various']
|
['intel ']
|
['c']
| 1
| 11
| 6
|
--- diff --git a/drivers/gpu/drm/i915/display/intel_lspcon.c b/drivers/gpu/drm/i915/display/intel_lspcon.c --- a/drivers/gpu/drm/i915/display/intel_lspcon.c +++ b/drivers/gpu/drm/i915/display/intel_lspcon.c - drm_hdmi_avi_infoframe_quant_range(&frame.avi, - conn_state->connector, - adjusted_mode, - crtc_state->limited_color_range ? - hdmi_quantization_range_limited : - hdmi_quantization_range_full); + if (crtc_state->output_format == intel_output_format_rgb) { + drm_hdmi_avi_infoframe_quant_range(&frame.avi, + conn_state->connector, + adjusted_mode, + crtc_state->limited_color_range ? + hdmi_quantization_range_limited : + hdmi_quantization_range_full); + } else { + frame.avi.quantization_range = hdmi_quantization_range_default; + frame.avi.ycc_quantization_range = hdmi_ycc_quantization_range_limited; + }
|
Graphics
|
9559c0d13b6b35abc2659bdd3024849d552e3c4e
|
uma shankar
|
drivers
|
gpu
|
display, drm, i915
|
drm/i915/display: add a warn for invalid output range and format
|
add a warn to rule out an invalid output range and format combination. this is to align the lspcon code with compute_avi_infoframes.
|
this release allows to map an uid to a different one in a mount; it also adds support for selecting the preemption model at runtime; support for a low-overhead memory error detector designed to be used in production; support for the acrn hypervisor designed for embedded systems; btrfs initial support for zoned devices, subpage blocks sizes and performance improvements; support for eager nfs writes; support for a thermal power management to control the surface temperature of embedded devices in an unified way; the napi polling can be moved to a kernel thread; and support for non-blocking path lookups. as always, there are many other features, new drivers, improvements and fixes.
|
enable hdr on mca lspcon based gen9 devices
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'cryptography', 'security', 'networking', 'architectures x86 arm risc-v powerpc mips csky s390 pa-risc c6x']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'cpu frequency scaling', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'cryptography hardware acceleration', 'pci', 'non-transparent bridge (ntb)', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'cxl (compute express link)', 'various']
|
['intel ']
|
['c']
| 1
| 4
| 0
|
--- diff --git a/drivers/gpu/drm/i915/display/intel_lspcon.c b/drivers/gpu/drm/i915/display/intel_lspcon.c --- a/drivers/gpu/drm/i915/display/intel_lspcon.c +++ b/drivers/gpu/drm/i915/display/intel_lspcon.c + /* nonsense combination */ + drm_warn_on(encoder->base.dev, crtc_state->limited_color_range && + crtc_state->output_format != intel_output_format_rgb); +
|
Graphics
|
55b1f9ddf41d369f2d480596822c6d17817a8d78
|
uma shankar ville syrj l ville syrjala linux intel com
|
drivers
|
gpu
|
display, drm, i915
|
drm/i915/display: attach content type property for lspcon
|
content type is supported on hdmi sink devices. attached the property for the same for lspcon based devices.
|
this release allows to map an uid to a different one in a mount; it also adds support for selecting the preemption model at runtime; support for a low-overhead memory error detector designed to be used in production; support for the acrn hypervisor designed for embedded systems; btrfs initial support for zoned devices, subpage blocks sizes and performance improvements; support for eager nfs writes; support for a thermal power management to control the surface temperature of embedded devices in an unified way; the napi polling can be moved to a kernel thread; and support for non-blocking path lookups. as always, there are many other features, new drivers, improvements and fixes.
|
enable hdr on mca lspcon based gen9 devices
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'cryptography', 'security', 'networking', 'architectures x86 arm risc-v powerpc mips csky s390 pa-risc c6x']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'cpu frequency scaling', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'cryptography hardware acceleration', 'pci', 'non-transparent bridge (ntb)', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'cxl (compute express link)', 'various']
|
['intel ']
|
['c']
| 2
| 5
| 0
|
--- diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c --- a/drivers/gpu/drm/i915/display/intel_dp.c +++ b/drivers/gpu/drm/i915/display/intel_dp.c + if (intel_bios_is_lspcon_present(dev_priv, port)) + drm_connector_attach_content_type_property(connector); + diff --git a/drivers/gpu/drm/i915/display/intel_lspcon.c b/drivers/gpu/drm/i915/display/intel_lspcon.c --- a/drivers/gpu/drm/i915/display/intel_lspcon.c +++ b/drivers/gpu/drm/i915/display/intel_lspcon.c + drm_hdmi_avi_infoframe_content_type(&frame.avi, conn_state); +
|
Graphics
|
b983675709e07523c5e8bacfcfa153a49f7eca7f
|
uma shankar
|
drivers
|
gpu
|
display, drm, i915
|
drm/i915: split intel_attach_colorspace_property() into hdmi vs. dp variants
|
with lspcon we use the avi infoframe to convey the colorimetry information (as opposed to dp msa/sdp), so the property we expose should match the values we can stuff into the infoframe. ie. we must use the hdmi variant of the property, even though we drive lspcon in pcon mode. to that end just split intel_attach_colorspace_property() into hdmi and dp variants and let the caller worry about which one it wants to use.
|
this release allows to map an uid to a different one in a mount; it also adds support for selecting the preemption model at runtime; support for a low-overhead memory error detector designed to be used in production; support for the acrn hypervisor designed for embedded systems; btrfs initial support for zoned devices, subpage blocks sizes and performance improvements; support for eager nfs writes; support for a thermal power management to control the surface temperature of embedded devices in an unified way; the napi polling can be moved to a kernel thread; and support for non-blocking path lookups. as always, there are many other features, new drivers, improvements and fixes.
|
enable hdr on mca lspcon based gen9 devices
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'cryptography', 'security', 'networking', 'architectures x86 arm risc-v powerpc mips csky s390 pa-risc c6x']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'cpu frequency scaling', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'cryptography hardware acceleration', 'pci', 'non-transparent bridge (ntb)', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'cxl (compute express link)', 'various']
|
['intel ']
|
['h', 'c']
| 4
| 15
| 21
|
--- diff --git a/drivers/gpu/drm/i915/display/intel_connector.c b/drivers/gpu/drm/i915/display/intel_connector.c --- a/drivers/gpu/drm/i915/display/intel_connector.c +++ b/drivers/gpu/drm/i915/display/intel_connector.c -intel_attach_colorspace_property(struct drm_connector *connector) +intel_attach_hdmi_colorspace_property(struct drm_connector *connector) - switch (connector->connector_type) { - case drm_mode_connector_hdmia: - case drm_mode_connector_hdmib: - if (drm_mode_create_hdmi_colorspace_property(connector)) - return; - break; - case drm_mode_connector_displayport: - case drm_mode_connector_edp: - if (drm_mode_create_dp_colorspace_property(connector)) - return; - break; - default: - missing_case(connector->connector_type); - return; - } + if (!drm_mode_create_hdmi_colorspace_property(connector)) + drm_object_attach_property(&connector->base, + connector->colorspace_property, 0); +} - drm_object_attach_property(&connector->base, - connector->colorspace_property, 0); +void +intel_attach_dp_colorspace_property(struct drm_connector *connector) +{ + if (!drm_mode_create_dp_colorspace_property(connector)) + drm_object_attach_property(&connector->base, + connector->colorspace_property, 0); diff --git a/drivers/gpu/drm/i915/display/intel_connector.h b/drivers/gpu/drm/i915/display/intel_connector.h --- a/drivers/gpu/drm/i915/display/intel_connector.h +++ b/drivers/gpu/drm/i915/display/intel_connector.h -void intel_attach_colorspace_property(struct drm_connector *connector); +void intel_attach_hdmi_colorspace_property(struct drm_connector *connector); +void intel_attach_dp_colorspace_property(struct drm_connector *connector); diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c --- a/drivers/gpu/drm/i915/display/intel_dp.c +++ b/drivers/gpu/drm/i915/display/intel_dp.c - intel_attach_colorspace_property(connector); + intel_attach_dp_colorspace_property(connector); diff --git a/drivers/gpu/drm/i915/display/intel_hdmi.c b/drivers/gpu/drm/i915/display/intel_hdmi.c --- a/drivers/gpu/drm/i915/display/intel_hdmi.c +++ b/drivers/gpu/drm/i915/display/intel_hdmi.c - intel_attach_colorspace_property(connector); + intel_attach_hdmi_colorspace_property(connector);
|
Graphics
|
174da987bc8da65327c230ba404a98bcd1b16cf1
|
ville syrj l uma shankar uma shankar intel com
|
drivers
|
gpu
|
display, drm, i915
|
drm/i915/display: enable colorspace programming for lspcon devices
|
enable hdmi colorspace for lspcon based devices. sending colorimetry data for hdr using avi infoframe. lspcon firmware expects this and though soc drives dp, for hdmi panel avi infoframe is sent to the lspcon device which transfers the same to hdmi sink.
|
this release allows to map an uid to a different one in a mount; it also adds support for selecting the preemption model at runtime; support for a low-overhead memory error detector designed to be used in production; support for the acrn hypervisor designed for embedded systems; btrfs initial support for zoned devices, subpage blocks sizes and performance improvements; support for eager nfs writes; support for a thermal power management to control the surface temperature of embedded devices in an unified way; the napi polling can be moved to a kernel thread; and support for non-blocking path lookups. as always, there are many other features, new drivers, improvements and fixes.
|
enable hdr on mca lspcon based gen9 devices
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'cryptography', 'security', 'networking', 'architectures x86 arm risc-v powerpc mips csky s390 pa-risc c6x']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'cpu frequency scaling', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'cryptography hardware acceleration', 'pci', 'non-transparent bridge (ntb)', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'cxl (compute express link)', 'various']
|
['intel ']
|
['c']
| 2
| 9
| 3
|
--- diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c --- a/drivers/gpu/drm/i915/display/intel_dp.c +++ b/drivers/gpu/drm/i915/display/intel_dp.c - intel_attach_dp_colorspace_property(connector); - - if (intel_bios_is_lspcon_present(dev_priv, port)) + /* register hdmi colorspace for case of lspcon */ + if (intel_bios_is_lspcon_present(dev_priv, port)) { + intel_attach_hdmi_colorspace_property(connector); + } else { + intel_attach_dp_colorspace_property(connector); + } diff --git a/drivers/gpu/drm/i915/display/intel_lspcon.c b/drivers/gpu/drm/i915/display/intel_lspcon.c --- a/drivers/gpu/drm/i915/display/intel_lspcon.c +++ b/drivers/gpu/drm/i915/display/intel_lspcon.c + /* set the colorspace as per the hdmi spec */ + drm_hdmi_avi_infoframe_colorspace(&frame.avi, conn_state); +
|
Graphics
|
5d36f2b2dd4d973880ee0450f1c287d1c368ebb2
|
uma shankar
|
drivers
|
gpu
|
display, drm, i915
|
drm/i915/display: nuke bogus lspcon check
|
dropped a irrelevant lspcon check from intel_hdmi_add_properties function.
|
this release allows to map an uid to a different one in a mount; it also adds support for selecting the preemption model at runtime; support for a low-overhead memory error detector designed to be used in production; support for the acrn hypervisor designed for embedded systems; btrfs initial support for zoned devices, subpage blocks sizes and performance improvements; support for eager nfs writes; support for a thermal power management to control the surface temperature of embedded devices in an unified way; the napi polling can be moved to a kernel thread; and support for non-blocking path lookups. as always, there are many other features, new drivers, improvements and fixes.
|
enable hdr on mca lspcon based gen9 devices
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'cryptography', 'security', 'networking', 'architectures x86 arm risc-v powerpc mips csky s390 pa-risc c6x']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'cpu frequency scaling', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'cryptography hardware acceleration', 'pci', 'non-transparent bridge (ntb)', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'cxl (compute express link)', 'various']
|
['intel ']
|
['c']
| 1
| 1
| 10
|
--- diff --git a/drivers/gpu/drm/i915/display/intel_hdmi.c b/drivers/gpu/drm/i915/display/intel_hdmi.c --- a/drivers/gpu/drm/i915/display/intel_hdmi.c +++ b/drivers/gpu/drm/i915/display/intel_hdmi.c - struct intel_digital_port *dig_port = - hdmi_to_dig_port(intel_hdmi); - /* - * attach colorspace property for non lspcon based device - * todo: this needs to be extended for lspcon implementation - * as well. will be implemented separately. - */ - if (!dig_port->lspcon.active) - intel_attach_hdmi_colorspace_property(connector); - + intel_attach_hdmi_colorspace_property(connector);
|
Graphics
|
84ab44b757d59e50584c0ca86890dd139f9daed0
|
uma shankar ville syrj l ville syrjala linux intel com ville syrj l ville syrjala linux intel com
|
drivers
|
gpu
|
display, drm, i915
|
drm/i915/display: enable hdr for parade based lspcon
|
enable hdr for lspcon based on parade along with mca.
|
this release allows to map an uid to a different one in a mount; it also adds support for selecting the preemption model at runtime; support for a low-overhead memory error detector designed to be used in production; support for the acrn hypervisor designed for embedded systems; btrfs initial support for zoned devices, subpage blocks sizes and performance improvements; support for eager nfs writes; support for a thermal power management to control the surface temperature of embedded devices in an unified way; the napi polling can be moved to a kernel thread; and support for non-blocking path lookups. as always, there are many other features, new drivers, improvements and fixes.
|
enable hdr on mca lspcon based gen9 devices
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'cryptography', 'security', 'networking', 'architectures x86 arm risc-v powerpc mips csky s390 pa-risc c6x']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'cpu frequency scaling', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'cryptography hardware acceleration', 'pci', 'non-transparent bridge (ntb)', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'cxl (compute express link)', 'various']
|
['intel ']
|
['c']
| 1
| 11
| 6
|
--- diff --git a/drivers/gpu/drm/i915/display/intel_lspcon.c b/drivers/gpu/drm/i915/display/intel_lspcon.c --- a/drivers/gpu/drm/i915/display/intel_lspcon.c +++ b/drivers/gpu/drm/i915/display/intel_lspcon.c +#define dpcd_parade_lspcon_hdr_status 0x00511 +static u32 get_hdr_status_reg(struct intel_lspcon *lspcon) +{ + if (lspcon->vendor == lspcon_vendor_mca) + return dpcd_mca_lspcon_hdr_status; + else + return dpcd_parade_lspcon_hdr_status; +} + - /* enable hdr for mca based lspcon devices */ - if (lspcon->vendor == lspcon_vendor_mca) - ret = drm_dp_dpcd_read(&dp->aux, dpcd_mca_lspcon_hdr_status, - &hdr_caps, 1); - else - return; + ret = drm_dp_dpcd_read(&dp->aux, get_hdr_status_reg(lspcon), + &hdr_caps, 1);
|
Graphics
|
c5044aee4039671d72ddcfdb38ea0a3b32effab4
|
uma shankar
|
drivers
|
gpu
|
display, drm, i915
|
drm/i915/lspcon: create separate infoframe_enabled helper
|
lspcon has infoframes as well as dip for hdr metadata(drm infoframe). create a separate mechanism for lspcon compared to hdmi in order to address the same and ensure future scalability.
|
this release allows to map an uid to a different one in a mount; it also adds support for selecting the preemption model at runtime; support for a low-overhead memory error detector designed to be used in production; support for the acrn hypervisor designed for embedded systems; btrfs initial support for zoned devices, subpage blocks sizes and performance improvements; support for eager nfs writes; support for a thermal power management to control the surface temperature of embedded devices in an unified way; the napi polling can be moved to a kernel thread; and support for non-blocking path lookups. as always, there are many other features, new drivers, improvements and fixes.
|
enable hdr on mca lspcon based gen9 devices
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'cryptography', 'security', 'networking', 'architectures x86 arm risc-v powerpc mips csky s390 pa-risc c6x']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'cpu frequency scaling', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'cryptography hardware acceleration', 'pci', 'non-transparent bridge (ntb)', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'cxl (compute express link)', 'various']
|
['intel ']
|
['h', 'c']
| 3
| 18
| 3
|
--- diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c --- a/drivers/gpu/drm/i915/display/intel_ddi.c +++ b/drivers/gpu/drm/i915/display/intel_ddi.c + struct intel_digital_port *dig_port = enc_to_dig_port(encoder); - pipe_config->infoframes.enable |= - intel_hdmi_infoframes_enabled(encoder, pipe_config); - + if (dig_port->lspcon.active && dig_port->dp.has_hdmi_sink) + pipe_config->infoframes.enable |= + intel_lspcon_infoframes_enabled(encoder, pipe_config); + else + pipe_config->infoframes.enable |= + intel_hdmi_infoframes_enabled(encoder, pipe_config); diff --git a/drivers/gpu/drm/i915/display/intel_lspcon.c b/drivers/gpu/drm/i915/display/intel_lspcon.c --- a/drivers/gpu/drm/i915/display/intel_lspcon.c +++ b/drivers/gpu/drm/i915/display/intel_lspcon.c +#include "intel_hdmi.h" +u32 intel_lspcon_infoframes_enabled(struct intel_encoder *encoder, + const struct intel_crtc_state *pipe_config) +{ + struct intel_digital_port *dig_port = enc_to_dig_port(encoder); + + return dig_port->infoframes_enabled(encoder, pipe_config); +} + diff --git a/drivers/gpu/drm/i915/display/intel_lspcon.h b/drivers/gpu/drm/i915/display/intel_lspcon.h --- a/drivers/gpu/drm/i915/display/intel_lspcon.h +++ b/drivers/gpu/drm/i915/display/intel_lspcon.h +u32 intel_lspcon_infoframes_enabled(struct intel_encoder *encoder, + const struct intel_crtc_state *pipe_config);
|
Graphics
|
a44289b923f6092e3103e8e1b83a5d0b86d34769
|
uma shankar
|
drivers
|
gpu
|
display, drm, i915
|
drm/i915/display: implement infoframes readback for lspcon
|
implemented infoframes enabled readback for lspcon devices. this will help align the implementation with state readback infrastructure.
|
this release allows to map an uid to a different one in a mount; it also adds support for selecting the preemption model at runtime; support for a low-overhead memory error detector designed to be used in production; support for the acrn hypervisor designed for embedded systems; btrfs initial support for zoned devices, subpage blocks sizes and performance improvements; support for eager nfs writes; support for a thermal power management to control the surface temperature of embedded devices in an unified way; the napi polling can be moved to a kernel thread; and support for non-blocking path lookups. as always, there are many other features, new drivers, improvements and fixes.
|
enable hdr on mca lspcon based gen9 devices
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'cryptography', 'security', 'networking', 'architectures x86 arm risc-v powerpc mips csky s390 pa-risc c6x']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'cpu frequency scaling', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'cryptography hardware acceleration', 'pci', 'non-transparent bridge (ntb)', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'cxl (compute express link)', 'various']
|
['intel ']
|
['c']
| 1
| 55
| 2
|
--- diff --git a/drivers/gpu/drm/i915/display/intel_lspcon.c b/drivers/gpu/drm/i915/display/intel_lspcon.c --- a/drivers/gpu/drm/i915/display/intel_lspcon.c +++ b/drivers/gpu/drm/i915/display/intel_lspcon.c +static bool _lspcon_read_avi_infoframe_enabled_mca(struct drm_dp_aux *aux) +{ + int ret; + u32 val = 0; + u16 reg = lspcon_mca_avi_if_ctrl; + + ret = drm_dp_dpcd_read(aux, reg, &val, 1); + if (ret < 0) { + drm_error("dpcd read failed, address 0x%x ", reg); + return false; + } + + return val & lspcon_mca_avi_if_kickoff; +} + +static bool _lspcon_read_avi_infoframe_enabled_parade(struct drm_dp_aux *aux) +{ + int ret; + u32 val = 0; + u16 reg = lspcon_parade_avi_if_ctrl; + + ret = drm_dp_dpcd_read(aux, reg, &val, 1); + if (ret < 0) { + drm_error("dpcd read failed, address 0x%x ", reg); + return false; + } + + return val & lspcon_parade_avi_if_kickoff; +} + - /* fixme actually read this from the hw */ - return 0; + struct intel_dp *intel_dp = enc_to_intel_dp(encoder); + struct intel_lspcon *lspcon = enc_to_intel_lspcon(encoder); + struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); + bool infoframes_enabled; + u32 val = 0; + u32 mask, tmp; + + if (lspcon->vendor == lspcon_vendor_mca) + infoframes_enabled = _lspcon_read_avi_infoframe_enabled_mca(&intel_dp->aux); + else + infoframes_enabled = _lspcon_read_avi_infoframe_enabled_parade(&intel_dp->aux); + + if (infoframes_enabled) + val |= intel_hdmi_infoframe_enable(hdmi_infoframe_type_avi); + + if (lspcon->hdr_supported) { + tmp = intel_de_read(dev_priv, + hsw_tvideo_dip_ctl(pipe_config->cpu_transcoder)); + mask = video_dip_enable_gmp_hsw; + + if (tmp & mask) + val |= intel_hdmi_infoframe_enable(hdmi_packet_type_gamut_metadata); + } + + return val;
|
Graphics
|
34108a03e430ea0e7a1d9005e3caa0d6a746fa95
|
uma shankar
|
drivers
|
gpu
|
display, drm, i915
|
drm/i915/display: implement drm infoframe read for lspcon
|
implement read back of hdr metadata infoframes i.e dynamic range and mastering infoframe for lspcon devices.
|
this release allows to map an uid to a different one in a mount; it also adds support for selecting the preemption model at runtime; support for a low-overhead memory error detector designed to be used in production; support for the acrn hypervisor designed for embedded systems; btrfs initial support for zoned devices, subpage blocks sizes and performance improvements; support for eager nfs writes; support for a thermal power management to control the surface temperature of embedded devices in an unified way; the napi polling can be moved to a kernel thread; and support for non-blocking path lookups. as always, there are many other features, new drivers, improvements and fixes.
|
enable hdr on mca lspcon based gen9 devices
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'cryptography', 'security', 'networking', 'architectures x86 arm risc-v powerpc mips csky s390 pa-risc c6x']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'cpu frequency scaling', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'cryptography hardware acceleration', 'pci', 'non-transparent bridge (ntb)', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'cxl (compute express link)', 'various']
|
['intel ']
|
['h', 'c']
| 3
| 11
| 5
|
--- diff --git a/drivers/gpu/drm/i915/display/intel_hdmi.c b/drivers/gpu/drm/i915/display/intel_hdmi.c --- a/drivers/gpu/drm/i915/display/intel_hdmi.c +++ b/drivers/gpu/drm/i915/display/intel_hdmi.c -static void hsw_read_infoframe(struct intel_encoder *encoder, - const struct intel_crtc_state *crtc_state, - unsigned int type, - void *frame, ssize_t len) +void hsw_read_infoframe(struct intel_encoder *encoder, + const struct intel_crtc_state *crtc_state, + unsigned int type, void *frame, ssize_t len) diff --git a/drivers/gpu/drm/i915/display/intel_lspcon.c b/drivers/gpu/drm/i915/display/intel_lspcon.c --- a/drivers/gpu/drm/i915/display/intel_lspcon.c +++ b/drivers/gpu/drm/i915/display/intel_lspcon.c - /* fixme implement this */ + /* fixme implement for avi infoframe as well */ + if (type == hdmi_packet_type_gamut_metadata) + hsw_read_infoframe(encoder, crtc_state, type, + frame, len); diff --git a/drivers/gpu/drm/i915/display/intel_lspcon.h b/drivers/gpu/drm/i915/display/intel_lspcon.h --- a/drivers/gpu/drm/i915/display/intel_lspcon.h +++ b/drivers/gpu/drm/i915/display/intel_lspcon.h +void hsw_read_infoframe(struct intel_encoder *encoder, + const struct intel_crtc_state *crtc_state, + unsigned int type, + void *frame, ssize_t len);
|
Graphics
|
b759415020b335aea8329f210ee162cb0c3c86a0
|
uma shankar
|
drivers
|
gpu
|
display, drm, i915
|
drm/i915/lspcon: do not send drm infoframes to non-hdmi sinks
|
non-hdmi sinks shouldn't be sent dynamic range and mastering infoframes. check for that when using lspcon.
|
this release allows to map an uid to a different one in a mount; it also adds support for selecting the preemption model at runtime; support for a low-overhead memory error detector designed to be used in production; support for the acrn hypervisor designed for embedded systems; btrfs initial support for zoned devices, subpage blocks sizes and performance improvements; support for eager nfs writes; support for a thermal power management to control the surface temperature of embedded devices in an unified way; the napi polling can be moved to a kernel thread; and support for non-blocking path lookups. as always, there are many other features, new drivers, improvements and fixes.
|
enable hdr on mca lspcon based gen9 devices
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'cryptography', 'security', 'networking', 'architectures x86 arm risc-v powerpc mips csky s390 pa-risc c6x']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'cpu frequency scaling', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'cryptography hardware acceleration', 'pci', 'non-transparent bridge (ntb)', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'cxl (compute express link)', 'various']
|
['intel ']
|
['c']
| 1
| 5
| 1
|
--- diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c --- a/drivers/gpu/drm/i915/display/intel_ddi.c +++ b/drivers/gpu/drm/i915/display/intel_ddi.c + struct intel_digital_port *dig_port = enc_to_dig_port(encoder); - intel_dp_set_infoframes(encoder, true, crtc_state, conn_state); + + if (!dig_port->lspcon.active || dig_port->dp.has_hdmi_sink) + intel_dp_set_infoframes(encoder, true, crtc_state, conn_state); +
|
Graphics
|
998cc864955d9ec0a0675e7e2ea4e069ba640214
|
uma shankar
|
drivers
|
gpu
|
display, drm, i915
|
drm/i915/dp: program source oui on edp panels
|
since we're about to start adding support for intel's magic hdr backlight interface over dpcd, we need to ensure we're properly programming this field so that intel specific sink services are exposed. otherwise, 0x300-0x3ff will just read zeroes.
|
this release allows to map an uid to a different one in a mount; it also adds support for selecting the preemption model at runtime; support for a low-overhead memory error detector designed to be used in production; support for the acrn hypervisor designed for embedded systems; btrfs initial support for zoned devices, subpage blocks sizes and performance improvements; support for eager nfs writes; support for a thermal power management to control the surface temperature of embedded devices in an unified way; the napi polling can be moved to a kernel thread; and support for non-blocking path lookups. as always, there are many other features, new drivers, improvements and fixes.
|
add support for intel's edp backlight controls
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'cryptography', 'security', 'networking', 'architectures x86 arm risc-v powerpc mips csky s390 pa-risc c6x']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'cpu frequency scaling', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'cryptography hardware acceleration', 'pci', 'non-transparent bridge (ntb)', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'cxl (compute express link)', 'various']
|
['intel ']
|
['c']
| 1
| 33
| 0
|
--- diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c --- a/drivers/gpu/drm/i915/display/intel_dp.c +++ b/drivers/gpu/drm/i915/display/intel_dp.c +static void +intel_edp_init_source_oui(struct intel_dp *intel_dp, bool careful) +{ + struct drm_i915_private *i915 = dp_to_i915(intel_dp); + u8 oui[] = { 0x00, 0xaa, 0x01 }; + u8 buf[3] = { 0 }; + + /* + * during driver init, we want to be careful and avoid changing the source oui if it's + * already set to what we want, so as to avoid clearing any state by accident + */ + if (careful) { + if (drm_dp_dpcd_read(&intel_dp->aux, dp_source_oui, buf, sizeof(buf)) < 0) + drm_err(&i915->drm, "failed to read source oui "); + + if (memcmp(oui, buf, sizeof(oui)) == 0) + return; + } + + if (drm_dp_dpcd_write(&intel_dp->aux, dp_source_oui, oui, sizeof(oui)) < 0) + drm_err(&i915->drm, "failed to write source oui "); +} + + /* write the source oui as early as possible */ + if (intel_dp_is_edp(intel_dp)) + intel_edp_init_source_oui(intel_dp, false); + + /* + * if needed, program our source oui so we can make various intel-specific aux services + * available (such as hdr backlight controls) + */ + intel_edp_init_source_oui(intel_dp, true); +
|
Graphics
|
f12110afee058a2e6e816e315d3291765625cc87
|
lyude paul
|
drivers
|
gpu
|
display, drm, i915
|
drm/i915: rename pwm_* backlight callbacks to ext_pwm_*
|
since we're going to need to add a set of lower-level pwm backlight control hooks to be shared by normal backlight controls and hdr backlight controls in sdr mode, let's add a prefix to the external pwm backlight functions so that the difference between them and the high level pwm-only backlight functions is a bit more obvious.
|
this release allows to map an uid to a different one in a mount; it also adds support for selecting the preemption model at runtime; support for a low-overhead memory error detector designed to be used in production; support for the acrn hypervisor designed for embedded systems; btrfs initial support for zoned devices, subpage blocks sizes and performance improvements; support for eager nfs writes; support for a thermal power management to control the surface temperature of embedded devices in an unified way; the napi polling can be moved to a kernel thread; and support for non-blocking path lookups. as always, there are many other features, new drivers, improvements and fixes.
|
add support for intel's edp backlight controls
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'cryptography', 'security', 'networking', 'architectures x86 arm risc-v powerpc mips csky s390 pa-risc c6x']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'cpu frequency scaling', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'cryptography hardware acceleration', 'pci', 'non-transparent bridge (ntb)', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'cxl (compute express link)', 'various']
|
['intel ']
|
['c']
| 1
| 14
| 14
|
--- diff --git a/drivers/gpu/drm/i915/display/intel_panel.c b/drivers/gpu/drm/i915/display/intel_panel.c --- a/drivers/gpu/drm/i915/display/intel_panel.c +++ b/drivers/gpu/drm/i915/display/intel_panel.c -static u32 pwm_get_backlight(struct intel_connector *connector) +static u32 ext_pwm_get_backlight(struct intel_connector *connector) -static void pwm_set_backlight(const struct drm_connector_state *conn_state, u32 level) +static void ext_pwm_set_backlight(const struct drm_connector_state *conn_state, u32 level) -static void pwm_disable_backlight(const struct drm_connector_state *old_conn_state) +static void ext_pwm_disable_backlight(const struct drm_connector_state *old_conn_state) -static void pwm_enable_backlight(const struct intel_crtc_state *crtc_state, - const struct drm_connector_state *conn_state) +static void ext_pwm_enable_backlight(const struct intel_crtc_state *crtc_state, + const struct drm_connector_state *conn_state) -static int pwm_setup_backlight(struct intel_connector *connector, - enum pipe pipe) +static int ext_pwm_setup_backlight(struct intel_connector *connector, + enum pipe pipe) -static const struct intel_panel_bl_funcs pwm_funcs = { - .setup = pwm_setup_backlight, - .enable = pwm_enable_backlight, - .disable = pwm_disable_backlight, - .set = pwm_set_backlight, - .get = pwm_get_backlight, +static const struct intel_panel_bl_funcs ext_pwm_funcs = { + .setup = ext_pwm_setup_backlight, + .enable = ext_pwm_enable_backlight, + .disable = ext_pwm_disable_backlight, + .set = ext_pwm_set_backlight, + .get = ext_pwm_get_backlight, - panel->backlight.funcs = &pwm_funcs; + panel->backlight.funcs = &ext_pwm_funcs;
|
Graphics
|
390218ca9b927c4a8395fbc2c50997f405374194
|
lyude paul
|
drivers
|
gpu
|
display, drm, i915
|
drm/i915: pass down brightness values to enable/disable backlight callbacks
|
instead of using intel_panel->backlight.level, have the caller provide us with the current panel backlight value. we'll need this for when we separate pwm-related backlight callbacks from other means of backlight control (like dpcd backlight controls), as the caller of each pwm callback will be responsible for converting the current brightness value to it's respective pwm level.
|
this release allows to map an uid to a different one in a mount; it also adds support for selecting the preemption model at runtime; support for a low-overhead memory error detector designed to be used in production; support for the acrn hypervisor designed for embedded systems; btrfs initial support for zoned devices, subpage blocks sizes and performance improvements; support for eager nfs writes; support for a thermal power management to control the surface temperature of embedded devices in an unified way; the napi polling can be moved to a kernel thread; and support for non-blocking path lookups. as always, there are many other features, new drivers, improvements and fixes.
|
add support for intel's edp backlight controls
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'cryptography', 'security', 'networking', 'architectures x86 arm risc-v powerpc mips csky s390 pa-risc c6x']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'cpu frequency scaling', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'cryptography hardware acceleration', 'pci', 'non-transparent bridge (ntb)', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'cxl (compute express link)', 'various']
|
['intel ']
|
['h', 'c']
| 4
| 42
| 44
|
--- diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h --- a/drivers/gpu/drm/i915/display/intel_display_types.h +++ b/drivers/gpu/drm/i915/display/intel_display_types.h - void (*disable)(const struct drm_connector_state *conn_state); + void (*disable)(const struct drm_connector_state *conn_state, u32 level); - const struct drm_connector_state *conn_state); + const struct drm_connector_state *conn_state, u32 level); diff --git a/drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c b/drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c --- a/drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c +++ b/drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c - const struct drm_connector_state *conn_state) + const struct drm_connector_state *conn_state, u32 level) - intel_dp_aux_set_backlight(conn_state, - connector->panel.backlight.level); + intel_dp_aux_set_backlight(conn_state, level); -static void intel_dp_aux_disable_backlight(const struct drm_connector_state *old_conn_state) +static void intel_dp_aux_disable_backlight(const struct drm_connector_state *old_conn_state, + u32 level) diff --git a/drivers/gpu/drm/i915/display/intel_dsi_dcs_backlight.c b/drivers/gpu/drm/i915/display/intel_dsi_dcs_backlight.c --- a/drivers/gpu/drm/i915/display/intel_dsi_dcs_backlight.c +++ b/drivers/gpu/drm/i915/display/intel_dsi_dcs_backlight.c -static void dcs_disable_backlight(const struct drm_connector_state *conn_state) +static void dcs_disable_backlight(const struct drm_connector_state *conn_state, u32 level) - const struct drm_connector_state *conn_state) + const struct drm_connector_state *conn_state, u32 level) - struct intel_panel *panel = &to_intel_connector(conn_state->connector)->panel; - dcs_set_backlight(conn_state, panel->backlight.level); + dcs_set_backlight(conn_state, level); diff --git a/drivers/gpu/drm/i915/display/intel_panel.c b/drivers/gpu/drm/i915/display/intel_panel.c --- a/drivers/gpu/drm/i915/display/intel_panel.c +++ b/drivers/gpu/drm/i915/display/intel_panel.c -static void lpt_disable_backlight(const struct drm_connector_state *old_conn_state) +static void lpt_disable_backlight(const struct drm_connector_state *old_conn_state, u32 level) - intel_panel_actually_set_backlight(old_conn_state, 0); + intel_panel_actually_set_backlight(old_conn_state, level); -static void pch_disable_backlight(const struct drm_connector_state *old_conn_state) +static void pch_disable_backlight(const struct drm_connector_state *old_conn_state, u32 val) - intel_panel_actually_set_backlight(old_conn_state, 0); + intel_panel_actually_set_backlight(old_conn_state, val); -static void i9xx_disable_backlight(const struct drm_connector_state *old_conn_state) +static void i9xx_disable_backlight(const struct drm_connector_state *old_conn_state, u32 val) - intel_panel_actually_set_backlight(old_conn_state, 0); + intel_panel_actually_set_backlight(old_conn_state, val); -static void i965_disable_backlight(const struct drm_connector_state *old_conn_state) +static void i965_disable_backlight(const struct drm_connector_state *old_conn_state, u32 val) - intel_panel_actually_set_backlight(old_conn_state, 0); + intel_panel_actually_set_backlight(old_conn_state, val); -static void vlv_disable_backlight(const struct drm_connector_state *old_conn_state) +static void vlv_disable_backlight(const struct drm_connector_state *old_conn_state, u32 val) - intel_panel_actually_set_backlight(old_conn_state, 0); + intel_panel_actually_set_backlight(old_conn_state, val); -static void bxt_disable_backlight(const struct drm_connector_state *old_conn_state) +static void bxt_disable_backlight(const struct drm_connector_state *old_conn_state, u32 val) - u32 tmp, val; + u32 tmp; - intel_panel_actually_set_backlight(old_conn_state, 0); + intel_panel_actually_set_backlight(old_conn_state, val); -static void cnp_disable_backlight(const struct drm_connector_state *old_conn_state) +static void cnp_disable_backlight(const struct drm_connector_state *old_conn_state, u32 val) - intel_panel_actually_set_backlight(old_conn_state, 0); + intel_panel_actually_set_backlight(old_conn_state, val); -static void ext_pwm_disable_backlight(const struct drm_connector_state *old_conn_state) +static void ext_pwm_disable_backlight(const struct drm_connector_state *old_conn_state, u32 level) - panel->backlight.funcs->disable(old_conn_state); + panel->backlight.funcs->disable(old_conn_state, 0); - const struct drm_connector_state *conn_state) + const struct drm_connector_state *conn_state, u32 level) - intel_panel_actually_set_backlight(conn_state, panel->backlight.level); + intel_panel_actually_set_backlight(conn_state, level); - const struct drm_connector_state *conn_state) + const struct drm_connector_state *conn_state, u32 level) - intel_panel_actually_set_backlight(conn_state, panel->backlight.level); + intel_panel_actually_set_backlight(conn_state, level); - const struct drm_connector_state *conn_state) + const struct drm_connector_state *conn_state, u32 level) - intel_panel_actually_set_backlight(conn_state, panel->backlight.level); + intel_panel_actually_set_backlight(conn_state, level); - const struct drm_connector_state *conn_state) + const struct drm_connector_state *conn_state, u32 level) - intel_panel_actually_set_backlight(conn_state, panel->backlight.level); + intel_panel_actually_set_backlight(conn_state, level); - const struct drm_connector_state *conn_state) + const struct drm_connector_state *conn_state, u32 level) - intel_panel_actually_set_backlight(conn_state, panel->backlight.level); + intel_panel_actually_set_backlight(conn_state, level); - const struct drm_connector_state *conn_state) + const struct drm_connector_state *conn_state, u32 level) - intel_panel_actually_set_backlight(conn_state, panel->backlight.level); + intel_panel_actually_set_backlight(conn_state, level); - const struct drm_connector_state *conn_state) + const struct drm_connector_state *conn_state, u32 level) - intel_panel_actually_set_backlight(conn_state, panel->backlight.level); + intel_panel_actually_set_backlight(conn_state, level); - const struct drm_connector_state *conn_state) + const struct drm_connector_state *conn_state, u32 level) - int level = panel->backlight.level; - panel->backlight.funcs->enable(crtc_state, conn_state); + panel->backlight.funcs->enable(crtc_state, conn_state, panel->backlight.level);
|
Graphics
|
6423cb7f9249aa213c25b7a9fc2c3fbb271a10a4
|
lyude paul
|
drivers
|
gpu
|
display, drm, i915
|
drm/i915: keep track of pwm-related backlight hooks separately
|
currently, every different type of backlight hook that i915 supports is pretty straight forward - you have a backlight, probably through pwm (but maybe dpcd), with a single set of platform-specific hooks that are used for controlling it.
|
this release allows to map an uid to a different one in a mount; it also adds support for selecting the preemption model at runtime; support for a low-overhead memory error detector designed to be used in production; support for the acrn hypervisor designed for embedded systems; btrfs initial support for zoned devices, subpage blocks sizes and performance improvements; support for eager nfs writes; support for a thermal power management to control the surface temperature of embedded devices in an unified way; the napi polling can be moved to a kernel thread; and support for non-blocking path lookups. as always, there are many other features, new drivers, improvements and fixes.
|
add support for intel's edp backlight controls
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'cryptography', 'security', 'networking', 'architectures x86 arm risc-v powerpc mips csky s390 pa-risc c6x']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'cpu frequency scaling', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'cryptography hardware acceleration', 'pci', 'non-transparent bridge (ntb)', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'cxl (compute express link)', 'various']
|
['intel ']
|
['h', 'c']
| 2
| 186
| 150
|
- an additional call to lpt_get_backlight() in lpt_setup_backlight() is --- diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h --- a/drivers/gpu/drm/i915/display/intel_display_types.h +++ b/drivers/gpu/drm/i915/display/intel_display_types.h + u32 pwm_level_min; + u32 pwm_level_max; + bool pwm_enabled; + const struct intel_panel_bl_funcs *pwm_funcs; diff --git a/drivers/gpu/drm/i915/display/intel_panel.c b/drivers/gpu/drm/i915/display/intel_panel.c --- a/drivers/gpu/drm/i915/display/intel_panel.c +++ b/drivers/gpu/drm/i915/display/intel_panel.c -static u32 intel_panel_compute_brightness(struct intel_connector *connector, - u32 val) +static u32 intel_panel_invert_pwm_level(struct intel_connector *connector, u32 val) - drm_warn_on(&dev_priv->drm, panel->backlight.max == 0); + drm_warn_on(&dev_priv->drm, panel->backlight.pwm_level_max == 0); - return panel->backlight.max - val + panel->backlight.min; + return panel->backlight.pwm_level_max - val + panel->backlight.pwm_level_min; +void intel_panel_set_pwm_level(const struct drm_connector_state *conn_state, u32 val) +{ + struct intel_connector *connector = to_intel_connector(conn_state->connector); + struct drm_i915_private *i915 = to_i915(connector->base.dev); + struct intel_panel *panel = &connector->panel; + + drm_dbg_kms(&i915->drm, "set backlight pwm = %d ", val); + panel->backlight.pwm_funcs->set(conn_state, val); +} + - drm_warn_on(&dev_priv->drm, panel->backlight.max == 0); + drm_warn_on(&dev_priv->drm, panel->backlight.pwm_level_max == 0); - lbpc = level * 0xfe / panel->backlight.max + 1; + lbpc = level * 0xfe / panel->backlight.pwm_level_max + 1; - drm_dbg_kms(&i915->drm, "set backlight pwm = %d ", level); + drm_dbg_kms(&i915->drm, "set backlight level = %d ", level); - level = intel_panel_compute_brightness(connector, level); - intel_panel_actually_set_backlight(old_conn_state, level); + intel_panel_set_pwm_level(old_conn_state, level); - intel_panel_actually_set_backlight(old_conn_state, val); + intel_panel_set_pwm_level(old_conn_state, val); - intel_panel_actually_set_backlight(old_conn_state, val); + intel_panel_set_pwm_level(old_conn_state, val); - intel_panel_actually_set_backlight(old_conn_state, val); + intel_panel_set_pwm_level(old_conn_state, val); - intel_panel_actually_set_backlight(old_conn_state, val); + intel_panel_set_pwm_level(old_conn_state, val); - intel_panel_actually_set_backlight(old_conn_state, val); + intel_panel_set_pwm_level(old_conn_state, val); - intel_panel_actually_set_backlight(old_conn_state, val); + intel_panel_set_pwm_level(old_conn_state, val); - pch_ctl2 = panel->backlight.max << 16; + pch_ctl2 = panel->backlight.pwm_level_max << 16; - intel_panel_actually_set_backlight(conn_state, level); + intel_panel_set_pwm_level(conn_state, level); - intel_panel_actually_set_backlight(conn_state, level); + intel_panel_set_pwm_level(conn_state, level); - pch_ctl2 = panel->backlight.max << 16; + pch_ctl2 = panel->backlight.pwm_level_max << 16; - freq = panel->backlight.max; + freq = panel->backlight.pwm_level_max; - intel_panel_actually_set_backlight(conn_state, level); + intel_panel_set_pwm_level(conn_state, level); - freq = panel->backlight.max; + freq = panel->backlight.pwm_level_max; - intel_panel_actually_set_backlight(conn_state, level); + intel_panel_set_pwm_level(conn_state, level); - ctl = panel->backlight.max << 16; + ctl = panel->backlight.pwm_level_max << 16; - intel_panel_actually_set_backlight(conn_state, level); + intel_panel_set_pwm_level(conn_state, level); - panel->backlight.max); + panel->backlight.pwm_level_max); - intel_panel_actually_set_backlight(conn_state, level); + intel_panel_set_pwm_level(conn_state, level); - panel->backlight.max); + panel->backlight.pwm_level_max); - intel_panel_actually_set_backlight(conn_state, level); + intel_panel_set_pwm_level(conn_state, level); - level = intel_panel_compute_brightness(connector, level); - if (panel->backlight.enabled) { + if (panel->backlight.enabled) - val = intel_panel_compute_brightness(connector, val); - } - if (!panel->backlight.funcs->hz_to_pwm) { + if (!panel->backlight.pwm_funcs->hz_to_pwm) { - pwm = panel->backlight.funcs->hz_to_pwm(connector, pwm_freq_hz); + pwm = panel->backlight.pwm_funcs->hz_to_pwm(connector, pwm_freq_hz); - drm_warn_on(&dev_priv->drm, panel->backlight.max == 0); + drm_warn_on(&dev_priv->drm, panel->backlight.pwm_level_max == 0); - return scale(min, 0, 255, 0, panel->backlight.max); + return scale(min, 0, 255, 0, panel->backlight.pwm_level_max); - panel->backlight.max = pch_ctl2 >> 16; + panel->backlight.pwm_level_max = pch_ctl2 >> 16; - if (!panel->backlight.max) - panel->backlight.max = get_backlight_max_vbt(connector); + if (!panel->backlight.pwm_level_max) + panel->backlight.pwm_level_max = get_backlight_max_vbt(connector); - if (!panel->backlight.max) + if (!panel->backlight.pwm_level_max) - panel->backlight.min = get_backlight_min_vbt(connector); + panel->backlight.pwm_level_min = get_backlight_min_vbt(connector); - panel->backlight.enabled = pch_ctl1 & blm_pch_pwm_enable; + panel->backlight.pwm_enabled = pch_ctl1 & blm_pch_pwm_enable; - cpu_mode = panel->backlight.enabled && has_pch_lpt(dev_priv) && + cpu_mode = panel->backlight.pwm_enabled && has_pch_lpt(dev_priv) && - if (cpu_mode) - val = pch_get_backlight(connector, unused); - else - val = lpt_get_backlight(connector, unused); + val = pch_get_backlight(connector, unused); + - val = intel_panel_compute_brightness(connector, val); - panel->backlight.level = clamp(val, panel->backlight.min, - panel->backlight.max); - - u32 cpu_ctl2, pch_ctl1, pch_ctl2, val; + u32 cpu_ctl2, pch_ctl1, pch_ctl2; - panel->backlight.max = pch_ctl2 >> 16; + panel->backlight.pwm_level_max = pch_ctl2 >> 16; - if (!panel->backlight.max) - panel->backlight.max = get_backlight_max_vbt(connector); + if (!panel->backlight.pwm_level_max) + panel->backlight.pwm_level_max = get_backlight_max_vbt(connector); - if (!panel->backlight.max) + if (!panel->backlight.pwm_level_max) - panel->backlight.min = get_backlight_min_vbt(connector); - - val = pch_get_backlight(connector, unused); - val = intel_panel_compute_brightness(connector, val); - panel->backlight.level = clamp(val, panel->backlight.min, - panel->backlight.max); + panel->backlight.pwm_level_min = get_backlight_min_vbt(connector); - panel->backlight.enabled = (cpu_ctl2 & blm_pwm_enable) && + panel->backlight.pwm_enabled = (cpu_ctl2 & blm_pwm_enable) && - panel->backlight.max = ctl >> 17; + panel->backlight.pwm_level_max = ctl >> 17; - if (!panel->backlight.max) { - panel->backlight.max = get_backlight_max_vbt(connector); - panel->backlight.max >>= 1; + if (!panel->backlight.pwm_level_max) { + panel->backlight.pwm_level_max = get_backlight_max_vbt(connector); + panel->backlight.pwm_level_max >>= 1; - if (!panel->backlight.max) + if (!panel->backlight.pwm_level_max) - panel->backlight.max *= 0xff; + panel->backlight.pwm_level_max *= 0xff; - panel->backlight.min = get_backlight_min_vbt(connector); + panel->backlight.pwm_level_min = get_backlight_min_vbt(connector); - val = intel_panel_compute_brightness(connector, val); - panel->backlight.level = clamp(val, panel->backlight.min, - panel->backlight.max); + val = intel_panel_invert_pwm_level(connector, val); + val = clamp(val, panel->backlight.pwm_level_min, panel->backlight.pwm_level_max); - panel->backlight.enabled = val != 0; + panel->backlight.pwm_enabled = val != 0; - u32 ctl, ctl2, val; + u32 ctl, ctl2; - panel->backlight.max = ctl >> 16; + panel->backlight.pwm_level_max = ctl >> 16; - if (!panel->backlight.max) - panel->backlight.max = get_backlight_max_vbt(connector); + if (!panel->backlight.pwm_level_max) + panel->backlight.pwm_level_max = get_backlight_max_vbt(connector); - if (!panel->backlight.max) + if (!panel->backlight.pwm_level_max) - panel->backlight.max *= 0xff; - - panel->backlight.min = get_backlight_min_vbt(connector); + panel->backlight.pwm_level_max *= 0xff; - val = i9xx_get_backlight(connector, unused); - val = intel_panel_compute_brightness(connector, val); - panel->backlight.level = clamp(val, panel->backlight.min, - panel->backlight.max); + panel->backlight.pwm_level_min = get_backlight_min_vbt(connector); - panel->backlight.enabled = ctl2 & blm_pwm_enable; + panel->backlight.pwm_enabled = ctl2 & blm_pwm_enable; - u32 ctl, ctl2, val; + u32 ctl, ctl2; - panel->backlight.max = ctl >> 16; + panel->backlight.pwm_level_max = ctl >> 16; - if (!panel->backlight.max) - panel->backlight.max = get_backlight_max_vbt(connector); + if (!panel->backlight.pwm_level_max) + panel->backlight.pwm_level_max = get_backlight_max_vbt(connector); - if (!panel->backlight.max) + if (!panel->backlight.pwm_level_max) - panel->backlight.min = get_backlight_min_vbt(connector); + panel->backlight.pwm_level_min = get_backlight_min_vbt(connector); - val = vlv_get_backlight(connector, pipe); - val = intel_panel_compute_brightness(connector, val); - panel->backlight.level = clamp(val, panel->backlight.min, - panel->backlight.max); - - panel->backlight.enabled = ctl2 & blm_pwm_enable; + panel->backlight.pwm_enabled = ctl2 & blm_pwm_enable; - panel->backlight.max = - intel_de_read(dev_priv, - bxt_blc_pwm_freq(panel->backlight.controller)); + panel->backlight.pwm_level_max = + intel_de_read(dev_priv, bxt_blc_pwm_freq(panel->backlight.controller)); - if (!panel->backlight.max) - panel->backlight.max = get_backlight_max_vbt(connector); + if (!panel->backlight.pwm_level_max) + panel->backlight.pwm_level_max = get_backlight_max_vbt(connector); - if (!panel->backlight.max) + if (!panel->backlight.pwm_level_max) - panel->backlight.min = get_backlight_min_vbt(connector); - - val = bxt_get_backlight(connector, unused); - val = intel_panel_compute_brightness(connector, val); - panel->backlight.level = clamp(val, panel->backlight.min, - panel->backlight.max); + panel->backlight.pwm_level_min = get_backlight_min_vbt(connector); - panel->backlight.enabled = pwm_ctl & bxt_blc_pwm_enable; + panel->backlight.pwm_enabled = pwm_ctl & bxt_blc_pwm_enable; - u32 pwm_ctl, val; + u32 pwm_ctl; - panel->backlight.max = - intel_de_read(dev_priv, - bxt_blc_pwm_freq(panel->backlight.controller)); + panel->backlight.pwm_level_max = + intel_de_read(dev_priv, bxt_blc_pwm_freq(panel->backlight.controller)); - if (!panel->backlight.max) - panel->backlight.max = get_backlight_max_vbt(connector); + if (!panel->backlight.pwm_level_max) + panel->backlight.pwm_level_max = get_backlight_max_vbt(connector); - if (!panel->backlight.max) + if (!panel->backlight.pwm_level_max) - panel->backlight.min = get_backlight_min_vbt(connector); + panel->backlight.pwm_level_min = get_backlight_min_vbt(connector); - val = bxt_get_backlight(connector, unused); - val = intel_panel_compute_brightness(connector, val); - panel->backlight.level = clamp(val, panel->backlight.min, - panel->backlight.max); - - panel->backlight.enabled = pwm_ctl & bxt_blc_pwm_enable; + panel->backlight.pwm_enabled = pwm_ctl & bxt_blc_pwm_enable; - panel->backlight.max = 100; /* 100% */ - panel->backlight.min = get_backlight_min_vbt(connector); + panel->backlight.pwm_level_max = 100; /* 100% */ + panel->backlight.pwm_level_min = get_backlight_min_vbt(connector); - level = intel_panel_compute_brightness(connector, level); - panel->backlight.level = clamp(level, panel->backlight.min, - panel->backlight.max); - panel->backlight.enabled = true; + level = intel_panel_invert_pwm_level(connector, level); + panel->backlight.pwm_enabled = true; +static void intel_pwm_set_backlight(const struct drm_connector_state *conn_state, u32 level) +{ + struct intel_connector *connector = to_intel_connector(conn_state->connector); + struct intel_panel *panel = &connector->panel; + + panel->backlight.pwm_funcs->set(conn_state, + intel_panel_invert_pwm_level(connector, level)); +} + +static u32 intel_pwm_get_backlight(struct intel_connector *connector, enum pipe pipe) +{ + struct intel_panel *panel = &connector->panel; + + return intel_panel_invert_pwm_level(connector, + panel->backlight.pwm_funcs->get(connector, pipe)); +} + +static void intel_pwm_enable_backlight(const struct intel_crtc_state *crtc_state, + const struct drm_connector_state *conn_state, u32 level) +{ + struct intel_connector *connector = to_intel_connector(conn_state->connector); + struct intel_panel *panel = &connector->panel; + + panel->backlight.pwm_funcs->enable(crtc_state, conn_state, + intel_panel_invert_pwm_level(connector, level)); +} + +static void intel_pwm_disable_backlight(const struct drm_connector_state *conn_state, u32 level) +{ + struct intel_connector *connector = to_intel_connector(conn_state->connector); + struct intel_panel *panel = &connector->panel; + + panel->backlight.pwm_funcs->disable(conn_state, + intel_panel_invert_pwm_level(connector, level)); +} + +static int intel_pwm_setup_backlight(struct intel_connector *connector, enum pipe pipe) +{ + struct intel_panel *panel = &connector->panel; + int ret = panel->backlight.pwm_funcs->setup(connector, pipe); + + if (ret < 0) + return ret; + + panel->backlight.min = panel->backlight.pwm_level_min; + panel->backlight.max = panel->backlight.pwm_level_max; + panel->backlight.level = intel_pwm_get_backlight(connector, pipe); + panel->backlight.enabled = panel->backlight.pwm_enabled; + + return 0; +} + -static const struct intel_panel_bl_funcs bxt_funcs = { +static const struct intel_panel_bl_funcs bxt_pwm_funcs = { -static const struct intel_panel_bl_funcs cnp_funcs = { +static const struct intel_panel_bl_funcs cnp_pwm_funcs = { -static const struct intel_panel_bl_funcs lpt_funcs = { +static const struct intel_panel_bl_funcs lpt_pwm_funcs = { -static const struct intel_panel_bl_funcs spt_funcs = { +static const struct intel_panel_bl_funcs spt_pwm_funcs = { -static const struct intel_panel_bl_funcs pch_funcs = { +static const struct intel_panel_bl_funcs pch_pwm_funcs = { -static const struct intel_panel_bl_funcs vlv_funcs = { +static const struct intel_panel_bl_funcs vlv_pwm_funcs = { -static const struct intel_panel_bl_funcs i965_funcs = { +static const struct intel_panel_bl_funcs i965_pwm_funcs = { -static const struct intel_panel_bl_funcs i9xx_funcs = { +static const struct intel_panel_bl_funcs i9xx_pwm_funcs = { +static const struct intel_panel_bl_funcs pwm_bl_funcs = { + .setup = intel_pwm_setup_backlight, + .enable = intel_pwm_enable_backlight, + .disable = intel_pwm_disable_backlight, + .set = intel_pwm_set_backlight, + .get = intel_pwm_get_backlight, +}; + - panel->backlight.funcs = &bxt_funcs; + panel->backlight.pwm_funcs = &bxt_pwm_funcs; - panel->backlight.funcs = &cnp_funcs; + panel->backlight.pwm_funcs = &cnp_pwm_funcs; - panel->backlight.funcs = &lpt_funcs; + panel->backlight.pwm_funcs = &lpt_pwm_funcs; - panel->backlight.funcs = &spt_funcs; + panel->backlight.pwm_funcs = &spt_pwm_funcs; - panel->backlight.funcs = &pch_funcs; + panel->backlight.pwm_funcs = &pch_pwm_funcs; - panel->backlight.funcs = &ext_pwm_funcs; + panel->backlight.pwm_funcs = &ext_pwm_funcs; - panel->backlight.funcs = &vlv_funcs; + panel->backlight.pwm_funcs = &vlv_pwm_funcs; - panel->backlight.funcs = &i965_funcs; + panel->backlight.pwm_funcs = &i965_pwm_funcs; - panel->backlight.funcs = &i9xx_funcs; + panel->backlight.pwm_funcs = &i9xx_pwm_funcs; + + /* we're using a standard pwm backlight interface */ + panel->backlight.funcs = &pwm_bl_funcs;
|
Graphics
|
a575c00e5bc153ab380a097d5be54b97b496cdeb
|
lyude paul
|
drivers
|
gpu
|
display, drm, i915
|
drm/i915/dp: rename edp vesa backlight interface functions
|
since we're about to add support for a second type of backlight control interface over dp aux (specifically, intel's proprietary hdr backlight controls) let's rename all of the current backlight hooks we have for vesa to make it clear that they're specific to the vesa interface and not intel's.
|
this release allows to map an uid to a different one in a mount; it also adds support for selecting the preemption model at runtime; support for a low-overhead memory error detector designed to be used in production; support for the acrn hypervisor designed for embedded systems; btrfs initial support for zoned devices, subpage blocks sizes and performance improvements; support for eager nfs writes; support for a thermal power management to control the surface temperature of embedded devices in an unified way; the napi polling can be moved to a kernel thread; and support for non-blocking path lookups. as always, there are many other features, new drivers, improvements and fixes.
|
add support for intel's edp backlight controls
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'cryptography', 'security', 'networking', 'architectures x86 arm risc-v powerpc mips csky s390 pa-risc c6x']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'cpu frequency scaling', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'cryptography hardware acceleration', 'pci', 'non-transparent bridge (ntb)', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'cxl (compute express link)', 'various']
|
['intel ']
|
['c']
| 1
| 32
| 30
|
--- diff --git a/drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c b/drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c --- a/drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c +++ b/drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c -static void set_aux_backlight_enable(struct intel_dp *intel_dp, bool enable) +static void set_vesa_backlight_enable(struct intel_dp *intel_dp, bool enable) -static bool intel_dp_aux_backlight_dpcd_mode(struct intel_connector *connector) +static bool intel_dp_aux_vesa_backlight_dpcd_mode(struct intel_connector *connector) -static u32 intel_dp_aux_get_backlight(struct intel_connector *connector) +static u32 intel_dp_aux_vesa_get_backlight(struct intel_connector *connector) - if (!intel_dp_aux_backlight_dpcd_mode(connector)) + if (!intel_dp_aux_vesa_backlight_dpcd_mode(connector)) -intel_dp_aux_set_backlight(const struct drm_connector_state *conn_state, u32 level) +intel_dp_aux_vesa_set_backlight(const struct drm_connector_state *conn_state, + u32 level) -static bool intel_dp_aux_set_pwm_freq(struct intel_connector *connector) +static bool intel_dp_aux_vesa_set_pwm_freq(struct intel_connector *connector) -static void intel_dp_aux_enable_backlight(const struct intel_crtc_state *crtc_state, - const struct drm_connector_state *conn_state, u32 level) +static void +intel_dp_aux_vesa_enable_backlight(const struct intel_crtc_state *crtc_state, + const struct drm_connector_state *conn_state, u32 level) - if (intel_dp_aux_set_pwm_freq(connector)) + if (intel_dp_aux_vesa_set_pwm_freq(connector)) - intel_dp_aux_set_backlight(conn_state, level); - set_aux_backlight_enable(intel_dp, true); + intel_dp_aux_vesa_set_backlight(conn_state, level); + set_vesa_backlight_enable(intel_dp, true); -static void intel_dp_aux_disable_backlight(const struct drm_connector_state *old_conn_state, - u32 level) +static void intel_dp_aux_vesa_disable_backlight(const struct drm_connector_state *old_conn_state, + u32 level) - set_aux_backlight_enable(enc_to_intel_dp(to_intel_encoder(old_conn_state->best_encoder)), - false); + set_vesa_backlight_enable(enc_to_intel_dp(to_intel_encoder(old_conn_state->best_encoder)), + false); -static u32 intel_dp_aux_calc_max_backlight(struct intel_connector *connector) +static u32 intel_dp_aux_vesa_calc_max_backlight(struct intel_connector *connector) -static int intel_dp_aux_setup_backlight(struct intel_connector *connector, - enum pipe pipe) +static int intel_dp_aux_vesa_setup_backlight(struct intel_connector *connector, + enum pipe pipe) - panel->backlight.max = intel_dp_aux_calc_max_backlight(connector); + panel->backlight.max = intel_dp_aux_vesa_calc_max_backlight(connector); - panel->backlight.level = intel_dp_aux_get_backlight(connector); - panel->backlight.enabled = intel_dp_aux_backlight_dpcd_mode(connector) && + panel->backlight.level = intel_dp_aux_vesa_get_backlight(connector); + panel->backlight.enabled = intel_dp_aux_vesa_backlight_dpcd_mode(connector) && -intel_dp_aux_display_control_capable(struct intel_connector *connector) +intel_dp_aux_supports_vesa_backlight(struct intel_connector *connector) -static const struct intel_panel_bl_funcs intel_dp_bl_funcs = { - .setup = intel_dp_aux_setup_backlight, - .enable = intel_dp_aux_enable_backlight, - .disable = intel_dp_aux_disable_backlight, - .set = intel_dp_aux_set_backlight, - .get = intel_dp_aux_get_backlight, +static const struct intel_panel_bl_funcs intel_dp_vesa_bl_funcs = { + .setup = intel_dp_aux_vesa_setup_backlight, + .enable = intel_dp_aux_vesa_enable_backlight, + .disable = intel_dp_aux_vesa_disable_backlight, + .set = intel_dp_aux_vesa_set_backlight, + .get = intel_dp_aux_vesa_get_backlight, - !intel_dp_aux_display_control_capable(intel_connector)) + !intel_dp_aux_supports_vesa_backlight(intel_connector)) - panel->backlight.funcs = &intel_dp_bl_funcs; + panel->backlight.funcs = &intel_dp_vesa_bl_funcs;
|
Graphics
|
8fd1806d36c556fcadd2debcb3e0b0cf0ee1143f
|
lyude paul
|
drivers
|
gpu
|
display, drm, i915
|
drm/i915/dp: add register definitions for intel hdr backlight interface
|
no functional changes yet, this just adds definitions for all of the known dpcd registers used by intel's hdr backlight interface. since we'll only ever use this in i915, we just define them in intel_dp_aux_backlight.c
|
this release allows to map an uid to a different one in a mount; it also adds support for selecting the preemption model at runtime; support for a low-overhead memory error detector designed to be used in production; support for the acrn hypervisor designed for embedded systems; btrfs initial support for zoned devices, subpage blocks sizes and performance improvements; support for eager nfs writes; support for a thermal power management to control the surface temperature of embedded devices in an unified way; the napi polling can be moved to a kernel thread; and support for non-blocking path lookups. as always, there are many other features, new drivers, improvements and fixes.
|
add support for intel's edp backlight controls
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'cryptography', 'security', 'networking', 'architectures x86 arm risc-v powerpc mips csky s390 pa-risc c6x']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'cpu frequency scaling', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'cryptography hardware acceleration', 'pci', 'non-transparent bridge (ntb)', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'cxl (compute express link)', 'various']
|
['intel ']
|
['c']
| 1
| 53
| 0
|
--- diff --git a/drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c b/drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c --- a/drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c +++ b/drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c +/* + * dp aux registers for intel's proprietary hdr backlight interface. we define + * them here since we'll likely be the only driver to ever use these. + */ +#define intel_edp_hdr_tcon_cap0 0x340 + +#define intel_edp_hdr_tcon_cap1 0x341 +# define intel_edp_hdr_tcon_2084_decode_cap bit(0) +# define intel_edp_hdr_tcon_2020_gamut_cap bit(1) +# define intel_edp_hdr_tcon_tone_mapping_cap bit(2) +# define intel_edp_hdr_tcon_segmented_backlight_cap bit(3) +# define intel_edp_hdr_tcon_brightness_nits_cap bit(4) +# define intel_edp_hdr_tcon_optimization_cap bit(5) +# define intel_edp_hdr_tcon_sdp_colorimetry_cap bit(6) +# define intel_edp_hdr_tcon_srgb_to_panel_gamut_conversion_cap bit(7) + +#define intel_edp_hdr_tcon_cap2 0x342 +# define intel_edp_sdr_tcon_brightness_aux_cap bit(0) + +#define intel_edp_hdr_tcon_cap3 0x343 + +#define intel_edp_hdr_getset_ctrl_params 0x344 +# define intel_edp_hdr_tcon_2084_decode_enable bit(0) +# define intel_edp_hdr_tcon_2020_gamut_enable bit(1) +# define intel_edp_hdr_tcon_tone_mapping_enable bit(2) /* pre-tgl+ */ +# define intel_edp_hdr_tcon_segmented_backlight_enable bit(3) +# define intel_edp_hdr_tcon_brightness_aux_enable bit(4) +# define intel_edp_hdr_tcon_srgb_to_panel_gamut_enable bit(5) +/* bit 6 is reserved */ +# define intel_edp_hdr_tcon_sdp_colorimetry_enable bit(7) + +#define intel_edp_hdr_content_luminance 0x346 /* pre-tgl+ */ +#define intel_edp_hdr_panel_luminance_override 0x34a +#define intel_edp_sdr_luminance_level 0x352 +#define intel_edp_brightness_nits_lsb 0x354 +#define intel_edp_brightness_nits_msb 0x355 +#define intel_edp_brightness_delay_frames 0x356 +#define intel_edp_brightness_per_frame_steps 0x357 + +#define intel_edp_brightness_optimization_0 0x358 +# define intel_edp_tcon_usage_mask genmask(0, 3) +# define intel_edp_tcon_usage_unknown 0x0 +# define intel_edp_tcon_usage_desktop 0x1 +# define intel_edp_tcon_usage_full_screen_media 0x2 +# define intel_edp_tcon_usage_full_screen_gaming 0x3 +# define intel_edp_tcon_power_mask bit(4) +# define intel_edp_tcon_power_dc (0 << 4) +# define intel_edp_tcon_power_ac (1 << 4) +# define intel_edp_tcon_optimization_strength_mask genmask(5, 7) + +#define intel_edp_brightness_optimization_1 0x359 + +/* vesa backlight callbacks */
|
Graphics
|
021a3ac2a09592cb5d9d0946989b0e29e54a4e7b
|
lyude paul rodrigo vivi rodrigo vivi intel com
|
drivers
|
gpu
|
display, drm, i915
|
drm/i915/dp: enable intel's hdr backlight interface (only sdr for now)
|
so-recently a bunch of laptops on the market have started using dpcd backlight controls instead of the traditional ddi backlight controls. originally we thought we had this handled by adding vesa backlight control support to i915, but the story ended up being a lot more complicated then that.
|
this release allows to map an uid to a different one in a mount; it also adds support for selecting the preemption model at runtime; support for a low-overhead memory error detector designed to be used in production; support for the acrn hypervisor designed for embedded systems; btrfs initial support for zoned devices, subpage blocks sizes and performance improvements; support for eager nfs writes; support for a thermal power management to control the surface temperature of embedded devices in an unified way; the napi polling can be moved to a kernel thread; and support for non-blocking path lookups. as always, there are many other features, new drivers, improvements and fixes.
|
add support for intel's edp backlight controls
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'cryptography', 'security', 'networking', 'architectures x86 arm risc-v powerpc mips csky s390 pa-risc c6x']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'cpu frequency scaling', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'cryptography hardware acceleration', 'pci', 'non-transparent bridge (ntb)', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'cxl (compute express link)', 'various']
|
['intel ']
|
['h', 'c']
| 4
| 269
| 31
|
--- diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h --- a/drivers/gpu/drm/i915/display/intel_display_types.h +++ b/drivers/gpu/drm/i915/display/intel_display_types.h - u8 pwmgen_bit_count; + union { + struct { + u8 pwmgen_bit_count; + } vesa; + struct { + bool sdr_uses_aux; + } intel; + } edp; diff --git a/drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c b/drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c --- a/drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c +++ b/drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c +/* + * laptops with intel gpus which have panels that support controlling the + * backlight through dp aux can actually use two different interfaces: intel's + * proprietary dp aux backlight interface, and the standard vesa backlight + * interface. unfortunately, at the time of writing this a lot of laptops will + * advertise support for the standard vesa backlight interface when they + * don't properly support it. however, on these systems the intel backlight + * interface generally does work properly. additionally, these systems will + * usually just indicate that they use pwm backlight controls in their vbios + * for some reason. + */ + +#include "intel_panel.h" + +/* todo: + * implement hdr, right now we just implement the bare minimum to bring us back into sdr mode so we + * can make people's backlights work in the mean time + */ +/* intel edp backlight callbacks */ +static bool +intel_dp_aux_supports_hdr_backlight(struct intel_connector *connector) +{ + struct drm_i915_private *i915 = to_i915(connector->base.dev); + struct intel_dp *intel_dp = enc_to_intel_dp(connector->encoder); + struct drm_dp_aux *aux = &intel_dp->aux; + struct intel_panel *panel = &connector->panel; + int ret; + u8 tcon_cap[4]; + + ret = drm_dp_dpcd_read(aux, intel_edp_hdr_tcon_cap0, tcon_cap, sizeof(tcon_cap)); + if (ret < 0) + return false; + + if (!(tcon_cap[1] & intel_edp_hdr_tcon_brightness_nits_cap)) + return false; + + if (tcon_cap[0] >= 1) { + drm_dbg_kms(&i915->drm, "detected intel hdr backlight interface version %d ", + tcon_cap[0]); + } else { + drm_dbg_kms(&i915->drm, "detected unsupported hdr backlight interface version %d ", + tcon_cap[0]); + return false; + } + + panel->backlight.edp.intel.sdr_uses_aux = + tcon_cap[2] & intel_edp_sdr_tcon_brightness_aux_cap; + + return true; +} + +static u32 +intel_dp_aux_hdr_get_backlight(struct intel_connector *connector, enum pipe pipe) +{ + struct drm_i915_private *i915 = to_i915(connector->base.dev); + struct intel_panel *panel = &connector->panel; + struct intel_dp *intel_dp = enc_to_intel_dp(connector->encoder); + u8 tmp; + u8 buf[2] = { 0 }; + + if (drm_dp_dpcd_readb(&intel_dp->aux, intel_edp_hdr_getset_ctrl_params, &tmp) < 0) { + drm_err(&i915->drm, "failed to read current backlight mode from dpcd "); + return 0; + } + + if (!(tmp & intel_edp_hdr_tcon_brightness_aux_enable)) { + if (!panel->backlight.edp.intel.sdr_uses_aux) { + u32 pwm_level = panel->backlight.pwm_funcs->get(connector, pipe); + + return intel_panel_backlight_level_from_pwm(connector, pwm_level); + } + + /* assume 100% brightness if backlight controls aren't enabled yet */ + return panel->backlight.max; + } + + if (drm_dp_dpcd_read(&intel_dp->aux, intel_edp_brightness_nits_lsb, buf, sizeof(buf)) < 0) { + drm_err(&i915->drm, "failed to read brightness from dpcd "); + return 0; + } + + return (buf[1] << 8 | buf[0]); +} + +static void +intel_dp_aux_hdr_set_aux_backlight(const struct drm_connector_state *conn_state, u32 level) +{ + struct intel_connector *connector = to_intel_connector(conn_state->connector); + struct drm_device *dev = connector->base.dev; + struct intel_dp *intel_dp = enc_to_intel_dp(connector->encoder); + u8 buf[4] = { 0 }; + + buf[0] = level & 0xff; + buf[1] = (level & 0xff00) >> 8; + + if (drm_dp_dpcd_write(&intel_dp->aux, intel_edp_brightness_nits_lsb, buf, 4) < 0) + drm_err(dev, "failed to write brightness level to dpcd "); +} + +static void +intel_dp_aux_hdr_set_backlight(const struct drm_connector_state *conn_state, u32 level) +{ + struct intel_connector *connector = to_intel_connector(conn_state->connector); + struct intel_panel *panel = &connector->panel; + + if (panel->backlight.edp.intel.sdr_uses_aux) { + intel_dp_aux_hdr_set_aux_backlight(conn_state, level); + } else { + const u32 pwm_level = intel_panel_backlight_level_to_pwm(connector, level); + + intel_panel_set_pwm_level(conn_state, pwm_level); + } +} + +static void +intel_dp_aux_hdr_enable_backlight(const struct intel_crtc_state *crtc_state, + const struct drm_connector_state *conn_state, u32 level) +{ + struct intel_connector *connector = to_intel_connector(conn_state->connector); + struct intel_panel *panel = &connector->panel; + struct drm_i915_private *i915 = to_i915(connector->base.dev); + struct intel_dp *intel_dp = enc_to_intel_dp(connector->encoder); + int ret; + u8 old_ctrl, ctrl; + + ret = drm_dp_dpcd_readb(&intel_dp->aux, intel_edp_hdr_getset_ctrl_params, &old_ctrl); + if (ret < 0) { + drm_err(&i915->drm, "failed to read current backlight control mode: %d ", ret); + return; + } + + ctrl = old_ctrl; + if (panel->backlight.edp.intel.sdr_uses_aux) { + ctrl |= intel_edp_hdr_tcon_brightness_aux_enable; + intel_dp_aux_hdr_set_aux_backlight(conn_state, level); + } else { + u32 pwm_level = intel_panel_backlight_level_to_pwm(connector, level); + + panel->backlight.pwm_funcs->enable(crtc_state, conn_state, pwm_level); + + ctrl &= ~intel_edp_hdr_tcon_brightness_aux_enable; + } + + if (ctrl != old_ctrl) + if (drm_dp_dpcd_writeb(&intel_dp->aux, intel_edp_hdr_getset_ctrl_params, ctrl) < 0) + drm_err(&i915->drm, "failed to configure dpcd brightness controls "); +} + +static void +intel_dp_aux_hdr_disable_backlight(const struct drm_connector_state *conn_state, u32 level) +{ + struct intel_connector *connector = to_intel_connector(conn_state->connector); + struct intel_panel *panel = &connector->panel; + + /* nothing to do for aux based backlight controls */ + if (panel->backlight.edp.intel.sdr_uses_aux) + return; + + /* note we want the actual pwm_level to be 0, regardless of pwm_min */ + panel->backlight.pwm_funcs->disable(conn_state, intel_panel_invert_pwm_level(connector, 0)); +} + +static int +intel_dp_aux_hdr_setup_backlight(struct intel_connector *connector, enum pipe pipe) +{ + struct drm_i915_private *i915 = to_i915(connector->base.dev); + struct intel_panel *panel = &connector->panel; + int ret; + + if (panel->backlight.edp.intel.sdr_uses_aux) { + drm_dbg_kms(&i915->drm, "sdr backlight is controlled through dpcd "); + } else { + drm_dbg_kms(&i915->drm, "sdr backlight is controlled through pwm "); + + ret = panel->backlight.pwm_funcs->setup(connector, pipe); + if (ret < 0) { + drm_err(&i915->drm, + "failed to setup sdr backlight controls through pwm: %d ", ret); + return ret; + } + } + + panel->backlight.max = 512; + panel->backlight.min = 0; + panel->backlight.level = intel_dp_aux_hdr_get_backlight(connector, pipe); + panel->backlight.enabled = panel->backlight.level != 0; + + return 0; +} + - const u8 pn = connector->panel.backlight.pwmgen_bit_count; + const u8 pn = connector->panel.backlight.edp.vesa.pwmgen_bit_count; + u8 pwmgen_bit_count = panel->backlight.edp.vesa.pwmgen_bit_count; - panel->backlight.pwmgen_bit_count) < 0) + pwmgen_bit_count) < 0) - panel->backlight.pwmgen_bit_count = pn; + panel->backlight.edp.vesa.pwmgen_bit_count = pn; +static const struct intel_panel_bl_funcs intel_dp_hdr_bl_funcs = { + .setup = intel_dp_aux_hdr_setup_backlight, + .enable = intel_dp_aux_hdr_enable_backlight, + .disable = intel_dp_aux_hdr_disable_backlight, + .set = intel_dp_aux_hdr_set_backlight, + .get = intel_dp_aux_hdr_get_backlight, +}; + -int intel_dp_aux_init_backlight_funcs(struct intel_connector *intel_connector) +int intel_dp_aux_init_backlight_funcs(struct intel_connector *connector) - struct intel_panel *panel = &intel_connector->panel; - struct intel_dp *intel_dp = enc_to_intel_dp(intel_connector->encoder); + struct drm_device *dev = connector->base.dev; + struct intel_panel *panel = &connector->panel; + struct intel_dp *intel_dp = enc_to_intel_dp(connector->encoder); - if (i915->params.enable_dpcd_backlight == 0 || - !intel_dp_aux_supports_vesa_backlight(intel_connector)) + if (i915->params.enable_dpcd_backlight == 0) - * there are a lot of machines that don't advertise the backlight - * control interface to use properly in their vbios, :\ + * a lot of edp panels in the wild will report supporting both the + * intel proprietary backlight control interface, and the vesa + * backlight control interface. many of these panels are liars though, + * and will only work with the intel interface. so, always probe for + * that first. - if (i915->vbt.backlight.type != - intel_backlight_vesa_edp_aux_interface && - i915->params.enable_dpcd_backlight != 1 && - !drm_dp_has_quirk(&intel_dp->desc, intel_dp->edid_quirks, - dp_quirk_force_dpcd_backlight)) { - drm_info(&i915->drm, - "panel advertises dpcd backlight support, but " - "vbt disagrees. if your backlight controls " - "don't work try booting with " - "i915.enable_dpcd_backlight=1. if your machine " - "needs this, please file a _new_ bug report on " - "drm/i915, see " fdo_bug_url " for details. "); - return -enodev; + if (intel_dp_aux_supports_hdr_backlight(connector)) { + drm_dbg_kms(dev, "using intel proprietary edp backlight controls "); + panel->backlight.funcs = &intel_dp_hdr_bl_funcs; + return 0; - panel->backlight.funcs = &intel_dp_vesa_bl_funcs; + if (intel_dp_aux_supports_vesa_backlight(connector)) { + drm_dbg_kms(dev, "using vesa edp backlight controls "); + panel->backlight.funcs = &intel_dp_vesa_bl_funcs; + return 0; + } - return 0; + return -enodev; diff --git a/drivers/gpu/drm/i915/display/intel_panel.c b/drivers/gpu/drm/i915/display/intel_panel.c --- a/drivers/gpu/drm/i915/display/intel_panel.c +++ b/drivers/gpu/drm/i915/display/intel_panel.c -static u32 intel_panel_invert_pwm_level(struct intel_connector *connector, u32 val) +u32 intel_panel_invert_pwm_level(struct intel_connector *connector, u32 val) +u32 intel_panel_backlight_level_to_pwm(struct intel_connector *connector, u32 val) +{ + struct drm_i915_private *dev_priv = to_i915(connector->base.dev); + struct intel_panel *panel = &connector->panel; + + drm_warn_on_once(&dev_priv->drm, + panel->backlight.max == 0 || panel->backlight.pwm_level_max == 0); + + val = scale(val, panel->backlight.min, panel->backlight.max, + panel->backlight.pwm_level_min, panel->backlight.pwm_level_max); + + return intel_panel_invert_pwm_level(connector, val); +} + +u32 intel_panel_backlight_level_from_pwm(struct intel_connector *connector, u32 val) +{ + struct drm_i915_private *dev_priv = to_i915(connector->base.dev); + struct intel_panel *panel = &connector->panel; + + drm_warn_on_once(&dev_priv->drm, + panel->backlight.max == 0 || panel->backlight.pwm_level_max == 0); + + if (dev_priv->params.invert_brightness > 0 || + (dev_priv->params.invert_brightness == 0 && dev_priv->quirks & quirk_invert_brightness)) + val = panel->backlight.pwm_level_max - (val - panel->backlight.pwm_level_min); + + return scale(val, panel->backlight.pwm_level_min, panel->backlight.pwm_level_max, + panel->backlight.min, panel->backlight.max); +} + - if (connector->base.connector_type == drm_mode_connector_edp && - intel_dp_aux_init_backlight_funcs(connector) == 0) - return; - + if (connector->base.connector_type == drm_mode_connector_edp && + intel_dp_aux_init_backlight_funcs(connector) == 0) + return; + diff --git a/drivers/gpu/drm/i915/display/intel_panel.h b/drivers/gpu/drm/i915/display/intel_panel.h --- a/drivers/gpu/drm/i915/display/intel_panel.h +++ b/drivers/gpu/drm/i915/display/intel_panel.h +void intel_panel_set_pwm_level(const struct drm_connector_state *conn_state, u32 level); +u32 intel_panel_invert_pwm_level(struct intel_connector *connector, u32 level); +u32 intel_panel_backlight_level_to_pwm(struct intel_connector *connector, u32 level); +u32 intel_panel_backlight_level_from_pwm(struct intel_connector *connector, u32 val);
|
Graphics
|
4a8d79901d5bed0812d272c372aa40282937b50f
|
lyude paul
|
drivers
|
gpu
|
display, drm, i915
|
drm/i915/dp: allow forcing specific interfaces through enable_dpcd_backlight
|
since we now support controlling panel backlights through dpcd using both the standard vesa interface, and intel's proprietary hdr backlight interface, we should allow the user to be able to explicitly choose between one or the other in the event that we're wrong about panels reliably reporting support for the intel hdr interface.
|
this release allows to map an uid to a different one in a mount; it also adds support for selecting the preemption model at runtime; support for a low-overhead memory error detector designed to be used in production; support for the acrn hypervisor designed for embedded systems; btrfs initial support for zoned devices, subpage blocks sizes and performance improvements; support for eager nfs writes; support for a thermal power management to control the surface temperature of embedded devices in an unified way; the napi polling can be moved to a kernel thread; and support for non-blocking path lookups. as always, there are many other features, new drivers, improvements and fixes.
|
add support for intel's edp backlight controls
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'cryptography', 'security', 'networking', 'architectures x86 arm risc-v powerpc mips csky s390 pa-risc c6x']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'cpu frequency scaling', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'cryptography hardware acceleration', 'pci', 'non-transparent bridge (ntb)', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'cxl (compute express link)', 'various']
|
['intel ']
|
['c']
| 2
| 43
| 4
|
--- diff --git a/drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c b/drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c --- a/drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c +++ b/drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c +enum intel_dp_aux_backlight_modparam { + intel_dp_aux_backlight_auto = -1, + intel_dp_aux_backlight_off = 0, + intel_dp_aux_backlight_on = 1, + intel_dp_aux_backlight_force_vesa = 2, + intel_dp_aux_backlight_force_intel = 3, +}; + + bool try_intel_interface = false, try_vesa_interface = false; - if (i915->params.enable_dpcd_backlight == 0) + /* check the vbt and user's module parameters to figure out which + * interfaces to probe + */ + switch (i915->params.enable_dpcd_backlight) { + case intel_dp_aux_backlight_off: + case intel_dp_aux_backlight_auto: + switch (i915->vbt.backlight.type) { + case intel_backlight_vesa_edp_aux_interface: + try_vesa_interface = true; + break; + case intel_backlight_display_ddi: + try_intel_interface = true; + try_vesa_interface = true; + break; + default: + return -enodev; + } + break; + case intel_dp_aux_backlight_on: + if (i915->vbt.backlight.type != intel_backlight_vesa_edp_aux_interface) + try_intel_interface = true; + + try_vesa_interface = true; + break; + case intel_dp_aux_backlight_force_vesa: + try_vesa_interface = true; + break; + case intel_dp_aux_backlight_force_intel: + try_intel_interface = true; + break; + } - if (intel_dp_aux_supports_hdr_backlight(connector)) { + if (try_intel_interface && intel_dp_aux_supports_hdr_backlight(connector)) { - if (intel_dp_aux_supports_vesa_backlight(connector)) { + if (try_vesa_interface && intel_dp_aux_supports_vesa_backlight(connector)) { diff --git a/drivers/gpu/drm/i915/i915_params.c b/drivers/gpu/drm/i915/i915_params.c --- a/drivers/gpu/drm/i915/i915_params.c +++ b/drivers/gpu/drm/i915/i915_params.c - "(-1=use per-vbt lfp backlight type setting [default], 0=disabled, 1=enabled)"); + "(-1=use per-vbt lfp backlight type setting [default], 0=disabled, 1=enable, 2=force vesa interface, 3=force intel interface)");
|
Graphics
|
2227816e647ae9f55935719f0ef05453eaf3fac7
|
lyude paul
|
drivers
|
gpu
|
display, drm, i915
|
drm/dp: revert "drm/dp: introduce edid-based quirks"
|
this reverts commit 0883ce8146ed6074c76399f4e70dbed788582e12. originally these quirks were added because of the issues with using the edp backlight interfaces on certain laptop panels, which made it impossible to properly probe for dpcd backlight support without having a whitelist for panels that we know have working vesa backlight control interfaces over dpcd. as well, it should be noted it was impossible to use the normal sink oui for recognizing these panels as none of them actually filled out their ouis, hence needing to resort to checking edids.
|
this release allows to map an uid to a different one in a mount; it also adds support for selecting the preemption model at runtime; support for a low-overhead memory error detector designed to be used in production; support for the acrn hypervisor designed for embedded systems; btrfs initial support for zoned devices, subpage blocks sizes and performance improvements; support for eager nfs writes; support for a thermal power management to control the surface temperature of embedded devices in an unified way; the napi polling can be moved to a kernel thread; and support for non-blocking path lookups. as always, there are many other features, new drivers, improvements and fixes.
|
add support for intel's edp backlight controls
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'cryptography', 'security', 'networking', 'architectures x86 arm risc-v powerpc mips csky s390 pa-risc c6x']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'cpu frequency scaling', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'cryptography hardware acceleration', 'pci', 'non-transparent bridge (ntb)', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'cxl (compute express link)', 'various']
|
['intel ']
|
['h', 'c']
| 7
| 9
| 113
|
--- diff --git a/drivers/gpu/drm/drm_dp_helper.c b/drivers/gpu/drm/drm_dp_helper.c --- a/drivers/gpu/drm/drm_dp_helper.c +++ b/drivers/gpu/drm/drm_dp_helper.c - !drm_dp_has_quirk(desc, 0, dp_dpcd_quirk_no_sink_count); + !drm_dp_has_quirk(desc, dp_dpcd_quirk_no_sink_count); -struct edid_quirk { - u8 mfg_id[2]; - u8 prod_id[2]; - u32 quirks; -}; - -#define mfg(first, second) { (first), (second) } -#define prod_id(first, second) { (first), (second) } - -/* - * some devices have unreliable ouids where they don't set the device id - * correctly, and as a result we need to use the edid for finding additional - * dp quirks in such cases. - */ -static const struct edid_quirk edid_quirk_list[] = { - /* optional 4k amoled panel in the thinkpad x1 extreme 2nd generation - * only supports dpcd backlight controls - */ - { mfg(0x4c, 0x83), prod_id(0x41, 0x41), bit(dp_quirk_force_dpcd_backlight) }, - /* - * some dell cml 2020 systems have panels support both aux and pwm - * backlight control, and some only support aux backlight control. all - * said panels start up in aux mode by default, and we don't have any - * support for disabling hdr mode on these panels which would be - * required to switch to pwm backlight control mode (plus, i'm not - * even sure we want pwm backlight controls over dpcd backlight - * controls anyway...). until we have a better way of detecting these, - * force dpcd backlight mode on all of them. - */ - { mfg(0x06, 0xaf), prod_id(0x9b, 0x32), bit(dp_quirk_force_dpcd_backlight) }, - { mfg(0x06, 0xaf), prod_id(0xeb, 0x41), bit(dp_quirk_force_dpcd_backlight) }, - { mfg(0x4d, 0x10), prod_id(0xc7, 0x14), bit(dp_quirk_force_dpcd_backlight) }, - { mfg(0x4d, 0x10), prod_id(0xe6, 0x14), bit(dp_quirk_force_dpcd_backlight) }, - { mfg(0x4c, 0x83), prod_id(0x47, 0x41), bit(dp_quirk_force_dpcd_backlight) }, - { mfg(0x09, 0xe5), prod_id(0xde, 0x08), bit(dp_quirk_force_dpcd_backlight) }, -}; - -#undef mfg -#undef prod_id - -/** - * drm_dp_get_edid_quirks() - check the edid of a dp device to find additional - * dp-specific quirks - * @edid: the edid to check - * - * while ouids are meant to be used to recognize a displayport device, a lot - * of manufacturers don't seem to like following standards and neglect to fill - * the dev-id in, making it impossible to only use ouids for determining - * quirks in some cases. this function can be used to check the edid and look - * up any additional dp quirks. the bits returned by this function correspond - * to the quirk bits in &drm_dp_quirk. - * - * returns: a bitmask of quirks, if any. the driver can check this using - * drm_dp_has_quirk(). - */ -u32 drm_dp_get_edid_quirks(const struct edid *edid) -{ - const struct edid_quirk *quirk; - u32 quirks = 0; - int i; - - if (!edid) - return 0; - - for (i = 0; i < array_size(edid_quirk_list); i++) { - quirk = &edid_quirk_list[i]; - if (memcmp(quirk->mfg_id, edid->mfg_id, - sizeof(edid->mfg_id)) == 0 && - memcmp(quirk->prod_id, edid->prod_code, - sizeof(edid->prod_code)) == 0) - quirks |= quirk->quirks; - } - - drm_debug_kms("dp sink: edid mfg %*phd prod-id %*phd quirks: 0x%04x ", - (int)sizeof(edid->mfg_id), edid->mfg_id, - (int)sizeof(edid->prod_code), edid->prod_code, quirks); - - return quirks; -} -export_symbol(drm_dp_get_edid_quirks); - diff --git a/drivers/gpu/drm/drm_dp_mst_topology.c b/drivers/gpu/drm/drm_dp_mst_topology.c --- a/drivers/gpu/drm/drm_dp_mst_topology.c +++ b/drivers/gpu/drm/drm_dp_mst_topology.c - if (drm_dp_has_quirk(&desc, 0, - dp_dpcd_quirk_dsc_without_virtual_dpcd) && + if (drm_dp_has_quirk(&desc, dp_dpcd_quirk_dsc_without_virtual_dpcd) && diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h --- a/drivers/gpu/drm/i915/display/intel_display_types.h +++ b/drivers/gpu/drm/i915/display/intel_display_types.h - u32 edid_quirks; diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c --- a/drivers/gpu/drm/i915/display/intel_dp.c +++ b/drivers/gpu/drm/i915/display/intel_dp.c - if (drm_dp_has_quirk(&intel_dp->desc, 0, - dp_dpcd_quirk_can_do_max_link_rate_3_24_gbps)) { + if (drm_dp_has_quirk(&intel_dp->desc, dp_dpcd_quirk_can_do_max_link_rate_3_24_gbps)) { - bool constant_n = drm_dp_has_quirk(&intel_dp->desc, 0, - dp_dpcd_quirk_constant_n); + bool constant_n = drm_dp_has_quirk(&intel_dp->desc, dp_dpcd_quirk_constant_n); - intel_dp->edid_quirks = drm_dp_get_edid_quirks(edid); - intel_dp->edid_quirks = 0; - intel_dp->edid_quirks = drm_dp_get_edid_quirks(edid); diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c b/drivers/gpu/drm/i915/display/intel_dp_mst.c --- a/drivers/gpu/drm/i915/display/intel_dp_mst.c +++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c - bool constant_n = drm_dp_has_quirk(&intel_dp->desc, 0, - dp_dpcd_quirk_constant_n); + bool constant_n = drm_dp_has_quirk(&intel_dp->desc, dp_dpcd_quirk_constant_n); diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c --- a/drivers/gpu/drm/i915/display/intel_psr.c +++ b/drivers/gpu/drm/i915/display/intel_psr.c - if (drm_dp_has_quirk(&intel_dp->desc, 0, dp_dpcd_quirk_no_psr)) { + if (drm_dp_has_quirk(&intel_dp->desc, dp_dpcd_quirk_no_psr)) { diff --git a/include/drm/drm_dp_helper.h b/include/drm/drm_dp_helper.h --- a/include/drm/drm_dp_helper.h +++ b/include/drm/drm_dp_helper.h -u32 drm_dp_get_edid_quirks(const struct edid *edid); - * implement workarounds for them. note that because some devices have - * unreliable ouids, the edid of sinks should also be checked for quirks using - * drm_dp_get_edid_quirks(). + * implement workarounds for them. - /** - * @dp_quirk_force_dpcd_backlight: - * - * the device is telling the truth when it says that it uses dpcd - * backlight controls, even if the system's firmware disagrees. this - * quirk should be checked against both the ident and panel edid. - * when present, the driver should honor the dpcd backlight - * capabilities advertised. - */ - dp_quirk_force_dpcd_backlight, - * @edid_quirks: optional quirk bitmask filled by drm_dp_get_edid_quirks() -drm_dp_has_quirk(const struct drm_dp_desc *desc, u32 edid_quirks, - enum drm_dp_quirk quirk) +drm_dp_has_quirk(const struct drm_dp_desc *desc, enum drm_dp_quirk quirk) - return (desc->quirks | edid_quirks) & bit(quirk); + return desc->quirks & bit(quirk);
|
Graphics
|
7c553f8b5a7dcf45f7a06da23b45e431aafbbdba
|
lyude paul
|
drivers
|
gpu
|
display, drm, i915
|
drm/i915: allow the sysadmin to override security mitigations
|
the clear-residuals mitigation is a relatively heavy hammer and under some circumstances the user may wish to forgo the context isolation in order to meet some performance requirement. introduce a generic module parameter to allow selectively enabling/disabling different mitigations.
|
this release allows to map an uid to a different one in a mount; it also adds support for selecting the preemption model at runtime; support for a low-overhead memory error detector designed to be used in production; support for the acrn hypervisor designed for embedded systems; btrfs initial support for zoned devices, subpage blocks sizes and performance improvements; support for eager nfs writes; support for a thermal power management to control the surface temperature of embedded devices in an unified way; the napi polling can be moved to a kernel thread; and support for non-blocking path lookups. as always, there are many other features, new drivers, improvements and fixes.
|
allow the sysadmin to override security mitigations
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'cryptography', 'security', 'networking', 'architectures x86 arm risc-v powerpc mips csky s390 pa-risc c6x']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'cpu frequency scaling', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'cryptography hardware acceleration', 'pci', 'non-transparent bridge (ntb)', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'cxl (compute express link)', 'various']
|
['intel ']
|
['h', 'c', 'makefile']
| 4
| 163
| 1
|
--- diff --git a/drivers/gpu/drm/i915/makefile b/drivers/gpu/drm/i915/makefile --- a/drivers/gpu/drm/i915/makefile +++ b/drivers/gpu/drm/i915/makefile + i915_mitigations.o \ diff --git a/drivers/gpu/drm/i915/gt/intel_ring_submission.c b/drivers/gpu/drm/i915/gt/intel_ring_submission.c --- a/drivers/gpu/drm/i915/gt/intel_ring_submission.c +++ b/drivers/gpu/drm/i915/gt/intel_ring_submission.c +#include "i915_mitigations.h" - if (engine->wa_ctx.vma->private != ce) { + if (engine->wa_ctx.vma->private != ce && + i915_mitigate_clear_residuals()) { diff --git a/drivers/gpu/drm/i915/i915_mitigations.c b/drivers/gpu/drm/i915/i915_mitigations.c --- /dev/null +++ b/drivers/gpu/drm/i915/i915_mitigations.c +// spdx-license-identifier: mit +/* + * copyright ©️ 2021 intel corporation + */ + +#include <linux/kernel.h> +#include <linux/moduleparam.h> +#include <linux/slab.h> +#include <linux/string.h> + +#include "i915_drv.h" +#include "i915_mitigations.h" + +static unsigned long mitigations __read_mostly = ~0ul; + +enum { + clear_residuals = 0, +}; + +static const char * const names[] = { + [clear_residuals] = "residuals", +}; + +bool i915_mitigate_clear_residuals(void) +{ + return read_once(mitigations) & bit(clear_residuals); +} + +static int mitigations_set(const char *val, const struct kernel_param *kp) +{ + unsigned long new = ~0ul; + char *str, *sep, *tok; + bool first = true; + int err = 0; + + build_bug_on(array_size(names) >= bits_per_type(mitigations)); + + str = kstrdup(val, gfp_kernel); + if (!str) + return -enomem; + + for (sep = str; (tok = strsep(&sep, ","));) { + bool enable = true; + int i; + + /* be tolerant of leading/trailing whitespace */ + tok = strim(tok); + + if (first) { + first = false; + + if (!strcmp(tok, "auto")) + continue; + + new = 0; + if (!strcmp(tok, "off")) + continue; + } + + if (*tok == '!') { + enable = !enable; + tok++; + } + + if (!strncmp(tok, "no", 2)) { + enable = !enable; + tok += 2; + } + + if (*tok == '') + continue; + + for (i = 0; i < array_size(names); i++) { + if (!strcmp(tok, names[i])) { + if (enable) + new |= bit(i); + else + new &= ~bit(i); + break; + } + } + if (i == array_size(names)) { + pr_err("bad "%s.mitigations=%s", '%s' is unknown ", + driver_name, val, tok); + err = -einval; + break; + } + } + kfree(str); + if (err) + return err; + + write_once(mitigations, new); + return 0; +} + +static int mitigations_get(char *buffer, const struct kernel_param *kp) +{ + unsigned long local = read_once(mitigations); + int count, i; + bool enable; + + if (!local) + return scnprintf(buffer, page_size, "%s ", "off"); + + if (local & bit(bits_per_long - 1)) { + count = scnprintf(buffer, page_size, "%s,", "auto"); + enable = false; + } else { + enable = true; + count = 0; + } + + for (i = 0; i < array_size(names); i++) { + if ((local & bit(i)) != enable) + continue; + + count += scnprintf(buffer + count, page_size - count, + "%s%s,", enable ? "" : "!", names[i]); + } + + buffer[count - 1] = ' '; + return count; +} + +static const struct kernel_param_ops ops = { + .set = mitigations_set, + .get = mitigations_get, +}; + +module_param_cb_unsafe(mitigations, &ops, null, 0600); +module_parm_desc(mitigations, +"selectively enable security mitigations for all intel®️ gpus in the system. " +" " +" auto -- enables all mitigations required for the platform [default] " +" off -- disables all mitigations " +" " +"individual mitigations can be enabled by passing a comma-separated string, " +"e.g. mitigations=residuals to enable only clearing residuals or " +"mitigations=auto,noresiduals to disable only the clear residual mitigation. " +"either '!' or 'no' may be used to switch from enabling the mitigation to " +"disabling it. " +" " +"active mitigations for ivybridge, baytrail, haswell: " +" residuals -- clear all thread-local registers between contexts" +); diff --git a/drivers/gpu/drm/i915/i915_mitigations.h b/drivers/gpu/drm/i915/i915_mitigations.h --- /dev/null +++ b/drivers/gpu/drm/i915/i915_mitigations.h +/* spdx-license-identifier: mit */ +/* + * copyright ©️ 2021 intel corporation + */ + +#ifndef __i915_mitigations_h__ +#define __i915_mitigations_h__ + +#include <linux/types.h> + +bool i915_mitigate_clear_residuals(void); + +#endif /* __i915_mitigations_h__ */
|
Graphics
|
f7452c7cbd5b5dfb9a6c84cb20bea04c89be50cd
|
chris wilson
|
drivers
|
gpu
|
drm, gt, i915
|
drm/i915: mark per-engine-reset as supported on gen7
|
the benefit of only resetting a single engine is that we leave other streams of userspace work intact across a hang; vital for process isolation. we had wired up individual engine resets for gen6, but only enabled it from gen8; now let's turn it on for the forgotten gen7. gen6 is still a mystery as how to unravel some global state that appears to be reset along with an engine (in particular the ppgtt enabling in gfx_mode).
|
this release allows to map an uid to a different one in a mount; it also adds support for selecting the preemption model at runtime; support for a low-overhead memory error detector designed to be used in production; support for the acrn hypervisor designed for embedded systems; btrfs initial support for zoned devices, subpage blocks sizes and performance improvements; support for eager nfs writes; support for a thermal power management to control the surface temperature of embedded devices in an unified way; the napi polling can be moved to a kernel thread; and support for non-blocking path lookups. as always, there are many other features, new drivers, improvements and fixes.
|
gen7 per-engine-reset support
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'cryptography', 'security', 'networking', 'architectures x86 arm risc-v powerpc mips csky s390 pa-risc c6x']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'cpu frequency scaling', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'cryptography hardware acceleration', 'pci', 'non-transparent bridge (ntb)', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'cxl (compute express link)', 'various']
|
['intel ']
|
['c']
| 1
| 3
| 2
|
--- diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c --- a/drivers/gpu/drm/i915/i915_pci.c +++ b/drivers/gpu/drm/i915/i915_pci.c + .has_reset_engine = true, \ + .has_reset_engine = true, - .has_64bit_reloc = 1, \ - .has_reset_engine = 1 + .has_64bit_reloc = 1
|
Graphics
|
6f0f70cdaf872cd5146a4af96c179bf5d39703b5
|
chris wilson mika kuoppala mika kuoppala linux intel com
|
drivers
|
gpu
|
drm, i915
|
drm/i915/hdcp: update cp property in update_pipe
|
when crtc state need_modeset is true it is not necessary it is going to be a real modeset, it can turns to be a fastset instead of modeset. this turns content protection property to be desired and hdcp update_pipe left with property to be in desired state but actual hdcp->value was enabled.
|
this release allows to map an uid to a different one in a mount; it also adds support for selecting the preemption model at runtime; support for a low-overhead memory error detector designed to be used in production; support for the acrn hypervisor designed for embedded systems; btrfs initial support for zoned devices, subpage blocks sizes and performance improvements; support for eager nfs writes; support for a thermal power management to control the surface temperature of embedded devices in an unified way; the napi polling can be moved to a kernel thread; and support for non-blocking path lookups. as always, there are many other features, new drivers, improvements and fixes.
|
hdcp 2.2 and hdcp 1.4 gen12 dp mst support
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'cryptography', 'security', 'networking', 'architectures x86 arm risc-v powerpc mips csky s390 pa-risc c6x']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'cpu frequency scaling', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'cryptography hardware acceleration', 'pci', 'non-transparent bridge (ntb)', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'cxl (compute express link)', 'various']
|
['intel ']
|
['c']
| 1
| 8
| 0
|
- fixed connector->base.registration_state == drm_connector_registered - commit log improvement. [uma] - added a comment before scheduling prop_work. [uma] --- diff --git a/drivers/gpu/drm/i915/display/intel_hdcp.c b/drivers/gpu/drm/i915/display/intel_hdcp.c --- a/drivers/gpu/drm/i915/display/intel_hdcp.c +++ b/drivers/gpu/drm/i915/display/intel_hdcp.c + /* + * if hdcp already enabled and cp property is desired, schedule + * prop_work to update correct cp property to user space. + */ + if (!desired_and_not_enabled && !content_protection_type_changed) { + drm_connector_get(&connector->base); + schedule_work(&hdcp->prop_work); + }
|
Graphics
|
d276e16702e2d634094f75f69df3b493f359fe31
|
anshuman gupta
|
drivers
|
gpu
|
display, drm, i915
|
drm/i915/hdcp: get conn while content_type changed
|
get drm connector reference count while scheduling a prop work to avoid any possible destroy of drm connector when it is in drm_connector_registered state.
|
this release allows to map an uid to a different one in a mount; it also adds support for selecting the preemption model at runtime; support for a low-overhead memory error detector designed to be used in production; support for the acrn hypervisor designed for embedded systems; btrfs initial support for zoned devices, subpage blocks sizes and performance improvements; support for eager nfs writes; support for a thermal power management to control the surface temperature of embedded devices in an unified way; the napi polling can be moved to a kernel thread; and support for non-blocking path lookups. as always, there are many other features, new drivers, improvements and fixes.
|
hdcp 2.2 and hdcp 1.4 gen12 dp mst support
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'cryptography', 'security', 'networking', 'architectures x86 arm risc-v powerpc mips csky s390 pa-risc c6x']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'cpu frequency scaling', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'cryptography hardware acceleration', 'pci', 'non-transparent bridge (ntb)', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'cxl (compute express link)', 'various']
|
['intel ']
|
['c']
| 1
| 1
| 0
|
--- diff --git a/drivers/gpu/drm/i915/display/intel_hdcp.c b/drivers/gpu/drm/i915/display/intel_hdcp.c --- a/drivers/gpu/drm/i915/display/intel_hdcp.c +++ b/drivers/gpu/drm/i915/display/intel_hdcp.c + drm_connector_get(&connector->base);
|
Graphics
|
b3c6661aad979ec3d4f5675cf3e6a35828607d6a
|
anshuman gupta uma shankar uma shankar intel com ramalingam c ramalingam c intel com karthik b s karthik b s intel com
|
drivers
|
gpu
|
display, drm, i915
|
drm/i915/hotplug: handle cp_irq for dp-mst
|
handle cp_irq in device_service_irq_vector_esi0 it requires to call intel_hdcp_handle_cp_irq() in case of cp_irq is triggered by a sink in dp-mst topology.
|
this release allows to map an uid to a different one in a mount; it also adds support for selecting the preemption model at runtime; support for a low-overhead memory error detector designed to be used in production; support for the acrn hypervisor designed for embedded systems; btrfs initial support for zoned devices, subpage blocks sizes and performance improvements; support for eager nfs writes; support for a thermal power management to control the surface temperature of embedded devices in an unified way; the napi polling can be moved to a kernel thread; and support for non-blocking path lookups. as always, there are many other features, new drivers, improvements and fixes.
|
hdcp 2.2 and hdcp 1.4 gen12 dp mst support
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'cryptography', 'security', 'networking', 'architectures x86 arm risc-v powerpc mips csky s390 pa-risc c6x']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'cpu frequency scaling', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'cryptography hardware acceleration', 'pci', 'non-transparent bridge (ntb)', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'cxl (compute express link)', 'various']
|
['intel ']
|
['c']
| 1
| 13
| 1
|
--- diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c --- a/drivers/gpu/drm/i915/display/intel_dp.c +++ b/drivers/gpu/drm/i915/display/intel_dp.c +static void +intel_dp_mst_hpd_irq(struct intel_dp *intel_dp, u8 *esi, bool *handled) +{ + drm_dp_mst_hpd_irq(&intel_dp->mst_mgr, esi, handled); + + if (esi[1] & dp_cp_irq) { + intel_hdcp_handle_cp_irq(intel_dp->attached_connector); + *handled = true; + } +} + - drm_dp_mst_hpd_irq(&intel_dp->mst_mgr, esi, &handled); + intel_dp_mst_hpd_irq(intel_dp, esi, &handled); +
|
Graphics
|
0abd3acf8a3113132ebf860f6a596d99a5a70c28
|
anshuman gupta uma shankar uma shankar intel com ramalingam c ramalingam c intel com karthik b s karthik b s intel com
|
drivers
|
gpu
|
display, drm, i915
|
drm/i915/hdcp: no hdcp when encoder is't initialized
|
there can be situation when dp mst connector is created without mst modeset being done, in those cases connector->encoder will be null. mst connector->encoder initializes after modeset. don't enable hdcp in such cases to prevent any crash.
|
this release allows to map an uid to a different one in a mount; it also adds support for selecting the preemption model at runtime; support for a low-overhead memory error detector designed to be used in production; support for the acrn hypervisor designed for embedded systems; btrfs initial support for zoned devices, subpage blocks sizes and performance improvements; support for eager nfs writes; support for a thermal power management to control the surface temperature of embedded devices in an unified way; the napi polling can be moved to a kernel thread; and support for non-blocking path lookups. as always, there are many other features, new drivers, improvements and fixes.
|
hdcp 2.2 and hdcp 1.4 gen12 dp mst support
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'cryptography', 'security', 'networking', 'architectures x86 arm risc-v powerpc mips csky s390 pa-risc c6x']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'cpu frequency scaling', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'cryptography hardware acceleration', 'pci', 'non-transparent bridge (ntb)', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'cxl (compute express link)', 'various']
|
['intel ']
|
['c']
| 1
| 6
| 0
|
--- diff --git a/drivers/gpu/drm/i915/display/intel_hdcp.c b/drivers/gpu/drm/i915/display/intel_hdcp.c --- a/drivers/gpu/drm/i915/display/intel_hdcp.c +++ b/drivers/gpu/drm/i915/display/intel_hdcp.c + if (!connector->encoder) { + drm_err(&dev_priv->drm, "[%s:%d] encoder is not initialized ", + connector->base.name, connector->base.base.id); + return -enodev; + } +
|
Graphics
|
6c63e6e14da7f55114d7e9077e89dc9ab8adeebb
|
anshuman gupta ramalingam c ramalingam c intel com karthik b s karthik b s intel com
|
drivers
|
gpu
|
display, drm, i915
|
drm/i915/hdcp: dp mst transcoder for link and stream
|
gen12 has h/w delta with respect to hdcp{1.x,2.x} display engine instances lies in transcoder instead of ddi as in gen11.
|
this release allows to map an uid to a different one in a mount; it also adds support for selecting the preemption model at runtime; support for a low-overhead memory error detector designed to be used in production; support for the acrn hypervisor designed for embedded systems; btrfs initial support for zoned devices, subpage blocks sizes and performance improvements; support for eager nfs writes; support for a thermal power management to control the surface temperature of embedded devices in an unified way; the napi polling can be moved to a kernel thread; and support for non-blocking path lookups. as always, there are many other features, new drivers, improvements and fixes.
|
hdcp 2.2 and hdcp 1.4 gen12 dp mst support
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'cryptography', 'security', 'networking', 'architectures x86 arm risc-v powerpc mips csky s390 pa-risc c6x']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'cpu frequency scaling', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'cryptography hardware acceleration', 'pci', 'non-transparent bridge (ntb)', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'cxl (compute express link)', 'various']
|
['intel ']
|
['h', 'c']
| 5
| 16
| 7
|
--- diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c --- a/drivers/gpu/drm/i915/display/intel_ddi.c +++ b/drivers/gpu/drm/i915/display/intel_ddi.c - crtc_state->cpu_transcoder, + crtc_state, diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h --- a/drivers/gpu/drm/i915/display/intel_display_types.h +++ b/drivers/gpu/drm/i915/display/intel_display_types.h + /* only used for dp mst stream encryption */ + enum transcoder stream_transcoder; diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c b/drivers/gpu/drm/i915/display/intel_dp_mst.c --- a/drivers/gpu/drm/i915/display/intel_dp_mst.c +++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c - pipe_config->cpu_transcoder, + pipe_config, diff --git a/drivers/gpu/drm/i915/display/intel_hdcp.c b/drivers/gpu/drm/i915/display/intel_hdcp.c --- a/drivers/gpu/drm/i915/display/intel_hdcp.c +++ b/drivers/gpu/drm/i915/display/intel_hdcp.c - enum transcoder cpu_transcoder, u8 content_type) + const struct intel_crtc_state *pipe_config, u8 content_type) - hdcp->cpu_transcoder = cpu_transcoder; + + if (intel_crtc_has_type(pipe_config, intel_output_dp_mst)) { + hdcp->cpu_transcoder = pipe_config->mst_master_transcoder; + hdcp->stream_transcoder = pipe_config->cpu_transcoder; + } else { + hdcp->cpu_transcoder = pipe_config->cpu_transcoder; + hdcp->stream_transcoder = invalid_transcoder; + } - hdcp->port_data.fw_tc = intel_get_mei_fw_tc(cpu_transcoder); + hdcp->port_data.fw_tc = intel_get_mei_fw_tc(hdcp->cpu_transcoder); - crtc_state->cpu_transcoder, + crtc_state, diff --git a/drivers/gpu/drm/i915/display/intel_hdcp.h b/drivers/gpu/drm/i915/display/intel_hdcp.h --- a/drivers/gpu/drm/i915/display/intel_hdcp.h +++ b/drivers/gpu/drm/i915/display/intel_hdcp.h - enum transcoder cpu_transcoder, u8 content_type); + const struct intel_crtc_state *pipe_config, u8 content_type);
|
Graphics
|
fc6097d4fb2988f12954993be70b882a345a35e5
|
anshuman gupta
|
drivers
|
gpu
|
display, drm, i915
|
drm/i915/hdcp: move hdcp enc status timeout to header
|
dp mst stream encryption status requires time of a link frame in order to change its status, but as there were some hdcp encryption timeout observed earlier, it is safer to use encrypt_status_change_timeout_ms timeout for stream status too, it requires to move the macro to a header. it will be used by both hdcp{1.x,2.x} stream status timeout.
|
this release allows to map an uid to a different one in a mount; it also adds support for selecting the preemption model at runtime; support for a low-overhead memory error detector designed to be used in production; support for the acrn hypervisor designed for embedded systems; btrfs initial support for zoned devices, subpage blocks sizes and performance improvements; support for eager nfs writes; support for a thermal power management to control the surface temperature of embedded devices in an unified way; the napi polling can be moved to a kernel thread; and support for non-blocking path lookups. as always, there are many other features, new drivers, improvements and fixes.
|
hdcp 2.2 and hdcp 1.4 gen12 dp mst support
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'cryptography', 'security', 'networking', 'architectures x86 arm risc-v powerpc mips csky s390 pa-risc c6x']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'cpu frequency scaling', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'cryptography hardware acceleration', 'pci', 'non-transparent bridge (ntb)', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'cxl (compute express link)', 'various']
|
['intel ']
|
['h', 'c']
| 2
| 6
| 5
|
--- diff --git a/drivers/gpu/drm/i915/display/intel_hdcp.c b/drivers/gpu/drm/i915/display/intel_hdcp.c --- a/drivers/gpu/drm/i915/display/intel_hdcp.c +++ b/drivers/gpu/drm/i915/display/intel_hdcp.c -#define encrypt_status_change_timeout_ms 50 - encrypt_status_change_timeout_ms)) { + hdcp_encrypt_status_change_timeout_ms)) { - ~0, encrypt_status_change_timeout_ms)) { + ~0, hdcp_encrypt_status_change_timeout_ms)) { - encrypt_status_change_timeout_ms); + hdcp_encrypt_status_change_timeout_ms); - encrypt_status_change_timeout_ms); + hdcp_encrypt_status_change_timeout_ms); diff --git a/drivers/gpu/drm/i915/display/intel_hdcp.h b/drivers/gpu/drm/i915/display/intel_hdcp.h --- a/drivers/gpu/drm/i915/display/intel_hdcp.h +++ b/drivers/gpu/drm/i915/display/intel_hdcp.h +#define hdcp_encrypt_status_change_timeout_ms 50 +
|
Graphics
|
fbf652bdb4b24908dd4e44d542488fcc7bb423af
|
anshuman gupta uma shankar uma shankar intel com ramalingam c ramalingam c intel com karthik b s karthik b s intel com
|
drivers
|
gpu
|
display, drm, i915
|
drm/i915/hdcp: hdcp stream encryption support
|
both hdcp_{1.x,2.x} requires to select/deselect multistream hdcp bit in trans_ddi_func_ctl in order to enable/disable stream hdcp encryption over dp mst transport link.
|
this release allows to map an uid to a different one in a mount; it also adds support for selecting the preemption model at runtime; support for a low-overhead memory error detector designed to be used in production; support for the acrn hypervisor designed for embedded systems; btrfs initial support for zoned devices, subpage blocks sizes and performance improvements; support for eager nfs writes; support for a thermal power management to control the surface temperature of embedded devices in an unified way; the napi polling can be moved to a kernel thread; and support for non-blocking path lookups. as always, there are many other features, new drivers, improvements and fixes.
|
hdcp 2.2 and hdcp 1.4 gen12 dp mst support
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'cryptography', 'security', 'networking', 'architectures x86 arm risc-v powerpc mips csky s390 pa-risc c6x']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'cpu frequency scaling', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'cryptography hardware acceleration', 'pci', 'non-transparent bridge (ntb)', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'cxl (compute express link)', 'various']
|
['intel ']
|
['h', 'c']
| 6
| 97
| 28
|
- cosmetic changes function name, error msg print and - uniformity for connector detail in dmesg. [ram] --- diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c --- a/drivers/gpu/drm/i915/display/intel_ddi.c +++ b/drivers/gpu/drm/i915/display/intel_ddi.c -int intel_ddi_toggle_hdcp_signalling(struct intel_encoder *intel_encoder, - enum transcoder cpu_transcoder, - bool enable) +int intel_ddi_toggle_hdcp_bits(struct intel_encoder *intel_encoder, + enum transcoder cpu_transcoder, + bool enable, u32 hdcp_mask) - tmp |= trans_ddi_hdcp_signalling; + tmp |= hdcp_mask; - tmp &= ~trans_ddi_hdcp_signalling; + tmp &= ~hdcp_mask; diff --git a/drivers/gpu/drm/i915/display/intel_ddi.h b/drivers/gpu/drm/i915/display/intel_ddi.h --- a/drivers/gpu/drm/i915/display/intel_ddi.h +++ b/drivers/gpu/drm/i915/display/intel_ddi.h -int intel_ddi_toggle_hdcp_signalling(struct intel_encoder *intel_encoder, - enum transcoder cpu_transcoder, - bool enable); +int intel_ddi_toggle_hdcp_bits(struct intel_encoder *intel_encoder, + enum transcoder cpu_transcoder, + bool enable, u32 hdcp_mask); diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h --- a/drivers/gpu/drm/i915/display/intel_display_types.h +++ b/drivers/gpu/drm/i915/display/intel_display_types.h + /* enable/disable stream encryption on dp mst transport link */ + int (*stream_encryption)(struct intel_connector *connector, + bool enable); + diff --git a/drivers/gpu/drm/i915/display/intel_dp_hdcp.c b/drivers/gpu/drm/i915/display/intel_dp_hdcp.c --- a/drivers/gpu/drm/i915/display/intel_dp_hdcp.c +++ b/drivers/gpu/drm/i915/display/intel_dp_hdcp.c +static unsigned int transcoder_to_stream_enc_status(enum transcoder cpu_transcoder) +{ + u32 stream_enc_mask; + + switch (cpu_transcoder) { + case transcoder_a: + stream_enc_mask = hdcp_status_stream_a_enc; + break; + case transcoder_b: + stream_enc_mask = hdcp_status_stream_b_enc; + break; + case transcoder_c: + stream_enc_mask = hdcp_status_stream_c_enc; + break; + case transcoder_d: + stream_enc_mask = hdcp_status_stream_d_enc; + break; + default: + stream_enc_mask = 0; + } + + return stream_enc_mask; +} + -intel_dp_mst_hdcp_toggle_signalling(struct intel_digital_port *dig_port, - enum transcoder cpu_transcoder, - bool enable) +intel_dp_mst_toggle_hdcp_stream_select(struct intel_connector *connector, + bool enable) - struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev); + struct intel_digital_port *dig_port = intel_attached_dig_port(connector); + struct drm_i915_private *i915 = to_i915(connector->base.dev); + struct intel_hdcp *hdcp = &connector->hdcp; - if (!enable) - usleep_range(6, 60); /* bspec says >= 6us */ - - ret = intel_ddi_toggle_hdcp_signalling(&dig_port->base, - cpu_transcoder, enable); + ret = intel_ddi_toggle_hdcp_bits(&dig_port->base, + hdcp->stream_transcoder, enable, + trans_ddi_hdcp_select); - drm_dbg_kms(&i915->drm, "%s hdcp signalling failed (%d) ", - enable ? "enable" : "disable", ret); + drm_err(&i915->drm, "%s hdcp stream select failed (%d) ", + enable ? "enable" : "disable", ret); +static int +intel_dp_mst_hdcp_stream_encryption(struct intel_connector *connector, + bool enable) +{ + struct intel_digital_port *dig_port = intel_attached_dig_port(connector); + struct drm_i915_private *i915 = to_i915(connector->base.dev); + struct intel_hdcp *hdcp = &connector->hdcp; + enum port port = dig_port->base.port; + enum transcoder cpu_transcoder = hdcp->stream_transcoder; + u32 stream_enc_status; + int ret; + + ret = intel_dp_mst_toggle_hdcp_stream_select(connector, enable); + if (ret) + return ret; + + stream_enc_status = transcoder_to_stream_enc_status(cpu_transcoder); + if (!stream_enc_status) + return -einval; + + /* wait for encryption confirmation */ + if (intel_de_wait_for_register(i915, + hdcp_status(i915, cpu_transcoder, port), + stream_enc_status, + enable ? stream_enc_status : 0, + hdcp_encrypt_status_change_timeout_ms)) { + drm_err(&i915->drm, "timed out waiting for transcoder: %s stream encryption %s ", + transcoder_name(cpu_transcoder), enable ? "enabled" : "disabled"); + return -etimedout; + } + + return 0; +} + - "[connector:%d:%s] failed qses ret=%d ", - connector->base.base.id, connector->base.name, ret); + "[%s:%d] failed qses ret=%d ", + connector->base.name, connector->base.base.id, ret); + drm_dbg_kms(&i915->drm, "[%s:%d] qses stream auth: %d stream enc: %d ", + connector->base.name, connector->base.base.id, + reply.auth_completed, reply.encryption_enabled); + - .toggle_signalling = intel_dp_mst_hdcp_toggle_signalling, + .toggle_signalling = intel_dp_hdcp_toggle_signalling, + .stream_encryption = intel_dp_mst_hdcp_stream_encryption, diff --git a/drivers/gpu/drm/i915/display/intel_hdmi.c b/drivers/gpu/drm/i915/display/intel_hdmi.c --- a/drivers/gpu/drm/i915/display/intel_hdmi.c +++ b/drivers/gpu/drm/i915/display/intel_hdmi.c - ret = intel_ddi_toggle_hdcp_signalling(&dig_port->base, cpu_transcoder, - false); + ret = intel_ddi_toggle_hdcp_bits(&dig_port->base, cpu_transcoder, + false, trans_ddi_hdcp_signalling); - ret = intel_ddi_toggle_hdcp_signalling(&dig_port->base, cpu_transcoder, - true); + + ret = intel_ddi_toggle_hdcp_bits(&dig_port->base, cpu_transcoder, + true, trans_ddi_hdcp_signalling); - ret = intel_ddi_toggle_hdcp_signalling(&dig_port->base, cpu_transcoder, - enable); + ret = intel_ddi_toggle_hdcp_bits(&dig_port->base, + cpu_transcoder, enable, + trans_ddi_hdcp_signalling); diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h +#define trans_ddi_hdcp_select reg_bit(5)
|
Graphics
|
1a67a168f57b68a63220871676a9e1e25ce3b867
|
anshuman gupta
|
drivers
|
gpu
|
display, drm, i915
|
drm/i915/hdcp: configure hdcp1.4 mst steram encryption status
|
enable hdcp 1.4 dp mst stream encryption.
|
this release allows to map an uid to a different one in a mount; it also adds support for selecting the preemption model at runtime; support for a low-overhead memory error detector designed to be used in production; support for the acrn hypervisor designed for embedded systems; btrfs initial support for zoned devices, subpage blocks sizes and performance improvements; support for eager nfs writes; support for a thermal power management to control the surface temperature of embedded devices in an unified way; the napi polling can be moved to a kernel thread; and support for non-blocking path lookups. as always, there are many other features, new drivers, improvements and fixes.
|
hdcp 2.2 and hdcp 1.4 gen12 dp mst support
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'cryptography', 'security', 'networking', 'architectures x86 arm risc-v powerpc mips csky s390 pa-risc c6x']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'cpu frequency scaling', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'cryptography hardware acceleration', 'pci', 'non-transparent bridge (ntb)', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'cxl (compute express link)', 'various']
|
['intel ']
|
['c']
| 1
| 25
| 13
|
- added debug print for stream encryption. - disable the hdcp on port after disabling last stream - cosmetic change, removed the value less comment. [uma] - split the gen12 hdcp enablement patch. [ram] - add connector details in drm_err. - uniformity for connector detail in dmesg. [ram] - comments improvement. [ram] --- diff --git a/drivers/gpu/drm/i915/display/intel_hdcp.c b/drivers/gpu/drm/i915/display/intel_hdcp.c --- a/drivers/gpu/drm/i915/display/intel_hdcp.c +++ b/drivers/gpu/drm/i915/display/intel_hdcp.c - /* - * xxx: if we have mst-connected devices, we need to enable encryption - * on those as well. - */ + /* dp mst auth part 1 step 2.a and step 2.b */ + if (shim->stream_encryption) { + ret = shim->stream_encryption(connector, true); + if (ret) { + drm_err(&dev_priv->drm, "[%s:%d] failed to enable hdcp 1.4 stream enc ", + connector->base.name, connector->base.base.id); + return ret; + } + drm_dbg_kms(&dev_priv->drm, "hdcp 1.4 transcoder: %s stream encrypted ", + transcoder_name(hdcp->stream_transcoder)); + } + if (hdcp->shim->stream_encryption) { + ret = hdcp->shim->stream_encryption(connector, false); + if (ret) { + drm_err(&dev_priv->drm, "[%s:%d] failed to disable hdcp 1.4 stream enc ", + connector->base.name, connector->base.base.id); + return ret; + } + drm_dbg_kms(&dev_priv->drm, "hdcp 1.4 transcoder: %s stream encryption disabled ", + transcoder_name(hdcp->stream_transcoder)); + } + - * if there are other connectors on this port using hdcp, don't disable - * it. instead, toggle the hdcp signalling off on that particular - * connector/pipe and exit. + * if there are other connectors on this port using hdcp, don't disable it + * until it disabled hdcp encryption for all connectors in mst topology. - if (dig_port->num_hdcp_streams > 0) { - ret = hdcp->shim->toggle_signalling(dig_port, - cpu_transcoder, false); - if (ret) - drm_error("failed to disable hdcp signalling "); + if (dig_port->num_hdcp_streams > 0) - }
|
Graphics
|
2a743b7b8a8be8c8fc7c130c304c1243f6bbe9b7
|
anshuman gupta
|
drivers
|
gpu
|
display, drm, i915
|
drm/i915/hdcp: enable gen12 hdcp 1.4 dp mst support
|
enable hdcp 1.4 over dp mst for gen12.
|
this release allows to map an uid to a different one in a mount; it also adds support for selecting the preemption model at runtime; support for a low-overhead memory error detector designed to be used in production; support for the acrn hypervisor designed for embedded systems; btrfs initial support for zoned devices, subpage blocks sizes and performance improvements; support for eager nfs writes; support for a thermal power management to control the surface temperature of embedded devices in an unified way; the napi polling can be moved to a kernel thread; and support for non-blocking path lookups. as always, there are many other features, new drivers, improvements and fixes.
|
hdcp 2.2 and hdcp 1.4 gen12 dp mst support
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'cryptography', 'security', 'networking', 'architectures x86 arm risc-v powerpc mips csky s390 pa-risc c6x']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'cpu frequency scaling', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'cryptography hardware acceleration', 'pci', 'non-transparent bridge (ntb)', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'cxl (compute express link)', 'various']
|
['intel ']
|
['c']
| 1
| 3
| 4
|
- enable hdcp for <= gen12 platforms. [ram] - connector detials in debug msg. [ram] --- diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c b/drivers/gpu/drm/i915/display/intel_dp_mst.c --- a/drivers/gpu/drm/i915/display/intel_dp_mst.c +++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c - - /* todo: figure out how to make hdcp work on gen12+ */ - if (intel_gen(dev_priv) < 12) { + if (intel_gen(dev_priv) <= 12) { - drm_debug_kms("hdcp init failed, skipping. "); + drm_dbg_kms(&dev_priv->drm, "[%s:%d] hdcp mst init failed, skipping. ", + connector->name, connector->base.id);
|
Graphics
|
3d2e4e8c930bf8cbf12b3bf8caf114b543d5e9ee
|
anshuman gupta
|
drivers
|
gpu
|
display, drm, i915
|
drm/i915/hdcp: pass dig_port to intel_hdcp_init
|
pass dig_port as an argument to intel_hdcp_init() and intel_hdcp2_init(). this will be required for hdcp 2.2 stream encryption.
|
this release allows to map an uid to a different one in a mount; it also adds support for selecting the preemption model at runtime; support for a low-overhead memory error detector designed to be used in production; support for the acrn hypervisor designed for embedded systems; btrfs initial support for zoned devices, subpage blocks sizes and performance improvements; support for eager nfs writes; support for a thermal power management to control the surface temperature of embedded devices in an unified way; the napi polling can be moved to a kernel thread; and support for non-blocking path lookups. as always, there are many other features, new drivers, improvements and fixes.
|
hdcp 2.2 and hdcp 1.4 gen12 dp mst support
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'cryptography', 'security', 'networking', 'architectures x86 arm risc-v powerpc mips csky s390 pa-risc c6x']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'cpu frequency scaling', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'cryptography hardware acceleration', 'pci', 'non-transparent bridge (ntb)', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'cxl (compute express link)', 'various']
|
['intel ']
|
['h', 'c']
| 4
| 13
| 9
|
--- diff --git a/drivers/gpu/drm/i915/display/intel_dp_hdcp.c b/drivers/gpu/drm/i915/display/intel_dp_hdcp.c --- a/drivers/gpu/drm/i915/display/intel_dp_hdcp.c +++ b/drivers/gpu/drm/i915/display/intel_dp_hdcp.c - return intel_hdcp_init(intel_connector, port, + return intel_hdcp_init(intel_connector, dig_port, - return intel_hdcp_init(intel_connector, port, + return intel_hdcp_init(intel_connector, dig_port, diff --git a/drivers/gpu/drm/i915/display/intel_hdcp.c b/drivers/gpu/drm/i915/display/intel_hdcp.c --- a/drivers/gpu/drm/i915/display/intel_hdcp.c +++ b/drivers/gpu/drm/i915/display/intel_hdcp.c - enum port port, + struct intel_digital_port *dig_port, + enum port port = dig_port->base.port; -static void intel_hdcp2_init(struct intel_connector *connector, enum port port, +static void intel_hdcp2_init(struct intel_connector *connector, + struct intel_digital_port *dig_port, - ret = initialize_hdcp_port_data(connector, port, shim); + ret = initialize_hdcp_port_data(connector, dig_port, shim); - enum port port, + struct intel_digital_port *dig_port, - intel_hdcp2_init(connector, port, shim); + intel_hdcp2_init(connector, dig_port, shim); diff --git a/drivers/gpu/drm/i915/display/intel_hdcp.h b/drivers/gpu/drm/i915/display/intel_hdcp.h --- a/drivers/gpu/drm/i915/display/intel_hdcp.h +++ b/drivers/gpu/drm/i915/display/intel_hdcp.h +struct intel_digital_port; -int intel_hdcp_init(struct intel_connector *connector, enum port port, +int intel_hdcp_init(struct intel_connector *connector, + struct intel_digital_port *dig_port, diff --git a/drivers/gpu/drm/i915/display/intel_hdmi.c b/drivers/gpu/drm/i915/display/intel_hdmi.c --- a/drivers/gpu/drm/i915/display/intel_hdmi.c +++ b/drivers/gpu/drm/i915/display/intel_hdmi.c - int ret = intel_hdcp_init(intel_connector, port, + int ret = intel_hdcp_init(intel_connector, dig_port,
|
Graphics
|
29b283a49c2b3193b5ce39b6c541a8696d4ca5fe
|
anshuman gupta uma shankar uma shankar intel com ramalingam c ramalingam c intel com karthik b s karthik b s intel com
|
drivers
|
gpu
|
display, drm, i915
|
drm/i915/hdcp: encapsulate hdcp_port_data to dig_port
|
hdcp_port_data is specific to a port on which hdcp encryption is getting enabled, so encapsulate it to intel_digital_port. this will be required to enable hdcp 2.2 stream encryption.
|
this release allows to map an uid to a different one in a mount; it also adds support for selecting the preemption model at runtime; support for a low-overhead memory error detector designed to be used in production; support for the acrn hypervisor designed for embedded systems; btrfs initial support for zoned devices, subpage blocks sizes and performance improvements; support for eager nfs writes; support for a thermal power management to control the surface temperature of embedded devices in an unified way; the napi polling can be moved to a kernel thread; and support for non-blocking path lookups. as always, there are many other features, new drivers, improvements and fixes.
|
hdcp 2.2 and hdcp 1.4 gen12 dp mst support
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'cryptography', 'security', 'networking', 'architectures x86 arm risc-v powerpc mips csky s390 pa-risc c6x']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'cpu frequency scaling', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'cryptography hardware acceleration', 'pci', 'non-transparent bridge (ntb)', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'cxl (compute express link)', 'various']
|
['intel ']
|
['h', 'c']
| 3
| 39
| 24
|
- 's/port_data/hdcp_port_data'. [ram] --- diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c --- a/drivers/gpu/drm/i915/display/intel_ddi.c +++ b/drivers/gpu/drm/i915/display/intel_ddi.c + if (dig_port) + kfree(dig_port->hdcp_port_data.streams); diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h --- a/drivers/gpu/drm/i915/display/intel_display_types.h +++ b/drivers/gpu/drm/i915/display/intel_display_types.h - struct hdcp_port_data port_data; - /* protects num_hdcp_streams reference count */ + /* protects num_hdcp_streams reference count, hdcp_port_data */ + /* hdcp port data need to pass to security f/w */ + struct hdcp_port_data hdcp_port_data; diff --git a/drivers/gpu/drm/i915/display/intel_hdcp.c b/drivers/gpu/drm/i915/display/intel_hdcp.c --- a/drivers/gpu/drm/i915/display/intel_hdcp.c +++ b/drivers/gpu/drm/i915/display/intel_hdcp.c +#include "i915_drv.h" - struct hdcp_port_data *data = &connector->hdcp.port_data; + struct intel_digital_port *dig_port = intel_attached_dig_port(connector); + struct hdcp_port_data *data = &dig_port->hdcp_port_data; - struct hdcp_port_data *data = &connector->hdcp.port_data; + struct intel_digital_port *dig_port = intel_attached_dig_port(connector); + struct hdcp_port_data *data = &dig_port->hdcp_port_data; - struct hdcp_port_data *data = &connector->hdcp.port_data; + struct intel_digital_port *dig_port = intel_attached_dig_port(connector); + struct hdcp_port_data *data = &dig_port->hdcp_port_data; - struct hdcp_port_data *data = &connector->hdcp.port_data; + struct intel_digital_port *dig_port = intel_attached_dig_port(connector); + struct hdcp_port_data *data = &dig_port->hdcp_port_data; - struct hdcp_port_data *data = &connector->hdcp.port_data; + struct intel_digital_port *dig_port = intel_attached_dig_port(connector); + struct hdcp_port_data *data = &dig_port->hdcp_port_data; - struct hdcp_port_data *data = &connector->hdcp.port_data; + struct intel_digital_port *dig_port = intel_attached_dig_port(connector); + struct hdcp_port_data *data = &dig_port->hdcp_port_data; - struct hdcp_port_data *data = &connector->hdcp.port_data; + struct intel_digital_port *dig_port = intel_attached_dig_port(connector); + struct hdcp_port_data *data = &dig_port->hdcp_port_data; - struct hdcp_port_data *data = &connector->hdcp.port_data; + struct intel_digital_port *dig_port = intel_attached_dig_port(connector); + struct hdcp_port_data *data = &dig_port->hdcp_port_data; - struct hdcp_port_data *data = &connector->hdcp.port_data; + struct intel_digital_port *dig_port = intel_attached_dig_port(connector); + struct hdcp_port_data *data = &dig_port->hdcp_port_data; - struct hdcp_port_data *data = &connector->hdcp.port_data; + struct intel_digital_port *dig_port = intel_attached_dig_port(connector); + struct hdcp_port_data *data = &dig_port->hdcp_port_data; + struct intel_digital_port *dig_port = intel_attached_dig_port(connector); - &connector->hdcp.port_data); + &dig_port->hdcp_port_data); - hdcp->port_data.seq_num_m = hdcp->seq_num_m; - hdcp->port_data.streams[0].stream_type = hdcp->content_type; + dig_port->hdcp_port_data.seq_num_m = hdcp->seq_num_m; + dig_port->hdcp_port_data.streams[0].stream_type = hdcp->content_type; + + struct intel_digital_port *dig_port = intel_attached_dig_port(connector); + struct hdcp_port_data *data = &dig_port->hdcp_port_data; - hdcp->port_data.streams[0].stream_type = - hdcp->content_type; + data->streams[0].stream_type = hdcp->content_type; + struct hdcp_port_data *data = &dig_port->hdcp_port_data; - struct hdcp_port_data *data = &hdcp->port_data; - data->k = 1; - data->streams = kcalloc(data->k, + data->streams = kcalloc(intel_num_pipes(dev_priv), - + /* for sst */ - kfree(hdcp->port_data.streams); + kfree(dig_port->hdcp_port_data.streams); - hdcp->port_data.fw_tc = intel_get_mei_fw_tc(hdcp->cpu_transcoder); + dig_port->hdcp_port_data.fw_tc = intel_get_mei_fw_tc(hdcp->cpu_transcoder); - kfree(hdcp->port_data.streams);
|
Graphics
|
a6c6eac947d5190b215b481ce616ab6cdaf44b1e
|
anshuman gupta
|
drivers
|
gpu
|
display, drm, i915
|
misc/mei/hdcp: fix auth_stream_req cmd buffer len
|
fix the size of wired_repeater_auth_stream_req cmd buffer size. it is based upon the actual number of mst streams and size of wired_cmd_repeater_auth_stream_req_in. excluding the size of hdcp_cmd_header.
|
this release allows to map an uid to a different one in a mount; it also adds support for selecting the preemption model at runtime; support for a low-overhead memory error detector designed to be used in production; support for the acrn hypervisor designed for embedded systems; btrfs initial support for zoned devices, subpage blocks sizes and performance improvements; support for eager nfs writes; support for a thermal power management to control the surface temperature of embedded devices in an unified way; the napi polling can be moved to a kernel thread; and support for non-blocking path lookups. as always, there are many other features, new drivers, improvements and fixes.
|
hdcp 2.2 and hdcp 1.4 gen12 dp mst support
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'cryptography', 'security', 'networking', 'architectures x86 arm risc-v powerpc mips csky s390 pa-risc c6x']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'cpu frequency scaling', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'cryptography hardware acceleration', 'pci', 'non-transparent bridge (ntb)', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'cxl (compute express link)', 'various']
|
['intel ']
|
['c']
| 1
| 1
| 2
|
- hdcp_cmd_header size annotation nitpick. [tomas] --- diff --git a/drivers/misc/mei/hdcp/mei_hdcp.c b/drivers/misc/mei/hdcp/mei_hdcp.c --- a/drivers/misc/mei/hdcp/mei_hdcp.c +++ b/drivers/misc/mei/hdcp/mei_hdcp.c - verify_mprime_in->header.buffer_len = - wired_cmd_buf_len_repeater_auth_stream_req_min_in; + verify_mprime_in->header.buffer_len = cmd_size - sizeof(verify_mprime_in->header);
|
Graphics
|
6581cc9e5da9844760122b108198f509c88cb543
|
anshuman gupta
|
drivers
|
misc
|
hdcp, mei
|
drm/hdcp: max mst content streams
|
let's define maximum mst content streams up to four generically which can be supported by modern display controllers.
|
this release allows to map an uid to a different one in a mount; it also adds support for selecting the preemption model at runtime; support for a low-overhead memory error detector designed to be used in production; support for the acrn hypervisor designed for embedded systems; btrfs initial support for zoned devices, subpage blocks sizes and performance improvements; support for eager nfs writes; support for a thermal power management to control the surface temperature of embedded devices in an unified way; the napi polling can be moved to a kernel thread; and support for non-blocking path lookups. as always, there are many other features, new drivers, improvements and fixes.
|
hdcp 2.2 and hdcp 1.4 gen12 dp mst support
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'cryptography', 'security', 'networking', 'architectures x86 arm risc-v powerpc mips csky s390 pa-risc c6x']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'cpu frequency scaling', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'cryptography hardware acceleration', 'pci', 'non-transparent bridge (ntb)', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'cxl (compute express link)', 'various']
|
['intel ']
|
['h']
| 1
| 4
| 4
|
--- diff --git a/include/drm/drm_hdcp.h b/include/drm/drm_hdcp.h --- a/include/drm/drm_hdcp.h +++ b/include/drm/drm_hdcp.h - * todo: this has to be changed for dp mst, as multiple stream on - * same port is possible. - * for hdcp2.2 on hdmi and dp sst this value is always 1. + * todo: hdcp_2_2_max_content_streams_cnt is based upon actual + * h/w mst streams capacity. + * this required to be moved out to platform specific header. -#define hdcp_2_2_max_content_streams_cnt 1 +#define hdcp_2_2_max_content_streams_cnt 4
|
Graphics
|
90103622c30b13d97a1f5ae7d03cdd0fd79951c3
|
anshuman gupta maarten lankhorst maarten lankhorst linux intel com uma shankar uma shankar intel com ramalingam c ramalingam c intel com karthik b s karthik b s intel com
|
include
|
drm
| |
drm/i915/hdcp: mst streams support in hdcp port_data
|
add support for multiple mst stream in hdcp port data which will be used by repeaterauthstreammanage msg and hdcp 2.2 security f/w for m' validation.
|
this release allows to map an uid to a different one in a mount; it also adds support for selecting the preemption model at runtime; support for a low-overhead memory error detector designed to be used in production; support for the acrn hypervisor designed for embedded systems; btrfs initial support for zoned devices, subpage blocks sizes and performance improvements; support for eager nfs writes; support for a thermal power management to control the surface temperature of embedded devices in an unified way; the napi polling can be moved to a kernel thread; and support for non-blocking path lookups. as always, there are many other features, new drivers, improvements and fixes.
|
hdcp 2.2 and hdcp 1.4 gen12 dp mst support
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'cryptography', 'security', 'networking', 'architectures x86 arm risc-v powerpc mips csky s390 pa-risc c6x']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'cpu frequency scaling', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'cryptography hardware acceleration', 'pci', 'non-transparent bridge (ntb)', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'cxl (compute express link)', 'various']
|
['intel ']
|
['h', 'c']
| 2
| 102
| 15
|
- init the hdcp port data k for hdmi/dp sst stream. - cosmetic changes. [uma] - 's/port_auth/hdcp_port_auth'. [ram] - commit log improvement. - comment and commit log improvement. [ram] - check first connector connected status before intel_encoder_is_mst --- diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h --- a/drivers/gpu/drm/i915/display/intel_display_types.h +++ b/drivers/gpu/drm/i915/display/intel_display_types.h - /* protects num_hdcp_streams reference count, hdcp_port_data */ + /* protects num_hdcp_streams reference count, hdcp_port_data and hdcp_auth_status */ + /* port hdcp auth status */ + bool hdcp_auth_status; diff --git a/drivers/gpu/drm/i915/display/intel_hdcp.c b/drivers/gpu/drm/i915/display/intel_hdcp.c --- a/drivers/gpu/drm/i915/display/intel_hdcp.c +++ b/drivers/gpu/drm/i915/display/intel_hdcp.c +static int intel_conn_to_vcpi(struct intel_connector *connector) +{ + /* for hdmi this is forced to be 0x0. for dp sst also this is 0x0. */ + return connector->port ? connector->port->vcpi.vcpi : 0; +} + +/* + * intel_hdcp_required_content_stream selects the most highest common possible hdcp + * content_type for all streams in dp mst topology because security f/w doesn't + * have any provision to mark content_type for each stream separately, it marks + * all available streams with the content_type proivided at the time of port + * authentication. this may prohibit the userspace to use type1 content on + * hdcp 2.2 capable sink because of other sink are not capable of hdcp 2.2 in + * dp mst topology. though it is not compulsory, security fw should change its + * policy to mark different content_types for different streams. + */ +static int +intel_hdcp_required_content_stream(struct intel_digital_port *dig_port) +{ + struct drm_connector_list_iter conn_iter; + struct intel_digital_port *conn_dig_port; + struct intel_connector *connector; + struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev); + struct hdcp_port_data *data = &dig_port->hdcp_port_data; + bool enforce_type0 = false; + int k; + + if (dig_port->hdcp_auth_status) + return 0; + + drm_connector_list_iter_begin(&i915->drm, &conn_iter); + for_each_intel_connector_iter(connector, &conn_iter) { + if (connector->base.status == connector_status_disconnected) + continue; + + if (!intel_encoder_is_mst(intel_attached_encoder(connector))) + continue; + + conn_dig_port = intel_attached_dig_port(connector); + if (conn_dig_port != dig_port) + continue; + + if (!enforce_type0 && !intel_hdcp2_capable(connector)) + enforce_type0 = true; + + data->streams[data->k].stream_id = intel_conn_to_vcpi(connector); + data->k++; + + /* if there is only one active stream */ + if (dig_port->dp.active_mst_links <= 1) + break; + } + drm_connector_list_iter_end(&conn_iter); + + if (drm_warn_on(&i915->drm, data->k > intel_num_pipes(i915) || data->k == 0)) + return -einval; + + /* + * apply common protection level across all streams in dp mst topology. + * use highest supported content type for all streams in dp mst topology. + */ + for (k = 0; k < data->k; k++) + data->streams[k].stream_type = + enforce_type0 ? drm_mode_hdcp_content_type0 : drm_mode_hdcp_content_type1; + + return 0; +} + + struct hdcp_port_data *data = &dig_port->hdcp_port_data; - int ret; + int ret, streams_size_delta, i; - /* k no of streams is fixed as 1. stored as big-endian. */ - msgs.stream_manage.k = cpu_to_be16(1); + msgs.stream_manage.k = cpu_to_be16(data->k); - /* for hdmi this is forced to be 0x0. for dp sst also this is 0x0. */ - msgs.stream_manage.streams[0].stream_id = 0; - msgs.stream_manage.streams[0].stream_type = hdcp->content_type; + for (i = 0; i < data->k; i++) { + msgs.stream_manage.streams[i].stream_id = data->streams[i].stream_id; + msgs.stream_manage.streams[i].stream_type = data->streams[i].stream_type; + } + streams_size_delta = (hdcp_2_2_max_content_streams_cnt - data->k) * + sizeof(struct hdcp2_streamid_type); - sizeof(msgs.stream_manage)); + sizeof(msgs.stream_manage) - streams_size_delta); - dig_port->hdcp_port_data.seq_num_m = hdcp->seq_num_m; - dig_port->hdcp_port_data.streams[0].stream_type = hdcp->content_type; + data->seq_num_m = hdcp->seq_num_m; + dig_port->hdcp_auth_status = true; - struct hdcp_port_data *data = &dig_port->hdcp_port_data; - struct intel_hdcp *hdcp = &connector->hdcp; - int ret, i, tries = 3; + int ret = 0, i, tries = 3; - for (i = 0; i < tries; i++) { + for (i = 0; i < tries && !dig_port->hdcp_auth_status; i++) { - data->streams[0].stream_type = hdcp->content_type; + + struct intel_digital_port *dig_port = intel_attached_dig_port(connector); + struct hdcp_port_data *data = &dig_port->hdcp_port_data; + /* stream which requires encryption */ + if (!intel_encoder_is_mst(intel_attached_encoder(connector))) { + data->k = 1; + data->streams[0].stream_type = hdcp->content_type; + } else { + ret = intel_hdcp_required_content_stream(dig_port); + if (ret) + return ret; + } + + struct intel_digital_port *dig_port = intel_attached_dig_port(connector); + struct hdcp_port_data *data = &dig_port->hdcp_port_data; + dig_port->hdcp_auth_status = false; + data->k = 0;
|
Graphics
|
e03187e12cae57c09b521b6f7dd7c7f9aa2b62e9
|
anshuman gupta
|
drivers
|
gpu
|
display, drm, i915
|
drm/i915/hdcp: pass connector to check_2_2_link
|
this requires for hdcp 2.2 mst check link. as for dp/hdmi shims check_2_2_link retrieves the connector from dig_port, this is not sufficient or dp mst connector, there can be multiple dp mst topology connector associated with same dig_port.
|
this release allows to map an uid to a different one in a mount; it also adds support for selecting the preemption model at runtime; support for a low-overhead memory error detector designed to be used in production; support for the acrn hypervisor designed for embedded systems; btrfs initial support for zoned devices, subpage blocks sizes and performance improvements; support for eager nfs writes; support for a thermal power management to control the surface temperature of embedded devices in an unified way; the napi polling can be moved to a kernel thread; and support for non-blocking path lookups. as always, there are many other features, new drivers, improvements and fixes.
|
hdcp 2.2 and hdcp 1.4 gen12 dp mst support
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'cryptography', 'security', 'networking', 'architectures x86 arm risc-v powerpc mips csky s390 pa-risc c6x']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'cpu frequency scaling', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'cryptography hardware acceleration', 'pci', 'non-transparent bridge (ntb)', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'cxl (compute express link)', 'various']
|
['intel ']
|
['h', 'c']
| 4
| 7
| 4
|
--- diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h --- a/drivers/gpu/drm/i915/display/intel_display_types.h +++ b/drivers/gpu/drm/i915/display/intel_display_types.h - int (*check_2_2_link)(struct intel_digital_port *dig_port); + int (*check_2_2_link)(struct intel_digital_port *dig_port, + struct intel_connector *connector); diff --git a/drivers/gpu/drm/i915/display/intel_dp_hdcp.c b/drivers/gpu/drm/i915/display/intel_dp_hdcp.c --- a/drivers/gpu/drm/i915/display/intel_dp_hdcp.c +++ b/drivers/gpu/drm/i915/display/intel_dp_hdcp.c -int intel_dp_hdcp2_check_link(struct intel_digital_port *dig_port) +int intel_dp_hdcp2_check_link(struct intel_digital_port *dig_port, + struct intel_connector *connector) diff --git a/drivers/gpu/drm/i915/display/intel_hdcp.c b/drivers/gpu/drm/i915/display/intel_hdcp.c --- a/drivers/gpu/drm/i915/display/intel_hdcp.c +++ b/drivers/gpu/drm/i915/display/intel_hdcp.c - ret = hdcp->shim->check_2_2_link(dig_port); + ret = hdcp->shim->check_2_2_link(dig_port, connector); diff --git a/drivers/gpu/drm/i915/display/intel_hdmi.c b/drivers/gpu/drm/i915/display/intel_hdmi.c --- a/drivers/gpu/drm/i915/display/intel_hdmi.c +++ b/drivers/gpu/drm/i915/display/intel_hdmi.c -int intel_hdmi_hdcp2_check_link(struct intel_digital_port *dig_port) +int intel_hdmi_hdcp2_check_link(struct intel_digital_port *dig_port, + struct intel_connector *connector)
|
Graphics
|
5bd29e32bb99f10569239b0c72e71a27889a2dae
|
anshuman gupta uma shankar uma shankar intel com ramalingam c ramalingam c intel com karthik b s karthik b s intel com
|
drivers
|
gpu
|
display, drm, i915
|
drm/i915/hdcp: add hdcp 2.2 stream register
|
add hdcp 2.2 dp mst hdcp2_stream_status and hdcp2_auth_stream register in i915_reg header.
|
this release allows to map an uid to a different one in a mount; it also adds support for selecting the preemption model at runtime; support for a low-overhead memory error detector designed to be used in production; support for the acrn hypervisor designed for embedded systems; btrfs initial support for zoned devices, subpage blocks sizes and performance improvements; support for eager nfs writes; support for a thermal power management to control the surface temperature of embedded devices in an unified way; the napi polling can be moved to a kernel thread; and support for non-blocking path lookups. as always, there are many other features, new drivers, improvements and fixes.
|
hdcp 2.2 and hdcp 1.4 gen12 dp mst support
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'cryptography', 'security', 'networking', 'architectures x86 arm risc-v powerpc mips csky s390 pa-risc c6x']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'cpu frequency scaling', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'cryptography hardware acceleration', 'pci', 'non-transparent bridge (ntb)', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'cxl (compute express link)', 'various']
|
['intel ']
|
['h']
| 1
| 39
| 0
|
- modified naming convention of hdcp2_stream_status --- diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h + +#define _pipea_hdcp2_stream_status 0x668c0 +#define _pipeb_hdcp2_stream_status 0x665c0 +#define _pipec_hdcp2_stream_status 0x666c0 +#define _piped_hdcp2_stream_status 0x667c0 +#define pipe_hdcp2_stream_status(pipe) _mmio(_pick((pipe), \ + _pipea_hdcp2_stream_status, \ + _pipeb_hdcp2_stream_status, \ + _pipec_hdcp2_stream_status, \ + _piped_hdcp2_stream_status)) + +#define _transa_hdcp2_stream_status 0x664c0 +#define _transb_hdcp2_stream_status 0x665c0 +#define trans_hdcp2_stream_status(trans) _mmio_trans(trans, \ + _transa_hdcp2_stream_status, \ + _transb_hdcp2_stream_status) +#define stream_encryption_status bit(31) +#define stream_type_status bit(30) +#define hdcp2_stream_status(dev_priv, trans, port) \ + (intel_gen(dev_priv) >= 12 ? \ + trans_hdcp2_stream_status(trans) : \ + pipe_hdcp2_stream_status(pipe)) + +#define _porta_hdcp2_auth_stream 0x66f00 +#define _portb_hdcp2_auth_stream 0x66f04 +#define port_hdcp2_auth_stream(port) _mmio_port(port, \ + _porta_hdcp2_auth_stream, \ + _portb_hdcp2_auth_stream) +#define _transa_hdcp2_auth_stream 0x66f00 +#define _transb_hdcp2_auth_stream 0x66f04 +#define trans_hdcp2_auth_stream(trans) _mmio_trans(trans, \ + _transa_hdcp2_auth_stream, \ + _transb_hdcp2_auth_stream) +#define auth_stream_type bit(31) +#define hdcp2_auth_stream(dev_priv, trans, port) \ + (intel_gen(dev_priv) >= 12 ? \ + trans_hdcp2_auth_stream(trans) : \ + port_hdcp2_auth_stream(port)) +
|
Graphics
|
d631b984cc90bb2995adbdf0c7346d9bb371d1ed
|
anshuman gupta
|
drivers
|
gpu
|
drm, i915
|
drm/i915/hdcp: support for hdcp 2.2 mst shim callbacks
|
add support for hdcp 2.2 dp mst shim callback. this adds existing dp hdcp shim callback for link authentication and encryption and hdcp 2.2 stream encryption callback.
|
this release allows to map an uid to a different one in a mount; it also adds support for selecting the preemption model at runtime; support for a low-overhead memory error detector designed to be used in production; support for the acrn hypervisor designed for embedded systems; btrfs initial support for zoned devices, subpage blocks sizes and performance improvements; support for eager nfs writes; support for a thermal power management to control the surface temperature of embedded devices in an unified way; the napi polling can be moved to a kernel thread; and support for non-blocking path lookups. as always, there are many other features, new drivers, improvements and fixes.
|
hdcp 2.2 and hdcp 1.4 gen12 dp mst support
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'cryptography', 'security', 'networking', 'architectures x86 arm risc-v powerpc mips csky s390 pa-risc c6x']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'cpu frequency scaling', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'cryptography hardware acceleration', 'pci', 'non-transparent bridge (ntb)', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'cxl (compute express link)', 'various']
|
['intel ']
|
['h', 'c']
| 2
| 85
| 8
|
- added a warn_on() instead of drm_err. [uma] - cosmetic changes. [uma] - 's/port_data/hdcp_port_data' [ram] - skip redundant link check. [ram] - use pipe instead of port to access hdcp2_stream_status --- diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h --- a/drivers/gpu/drm/i915/display/intel_display_types.h +++ b/drivers/gpu/drm/i915/display/intel_display_types.h + /* enable/disable hdcp 2.2 stream encryption on dp mst transport link */ + int (*stream_2_2_encryption)(struct intel_connector *connector, + bool enable); + diff --git a/drivers/gpu/drm/i915/display/intel_dp_hdcp.c b/drivers/gpu/drm/i915/display/intel_dp_hdcp.c --- a/drivers/gpu/drm/i915/display/intel_dp_hdcp.c +++ b/drivers/gpu/drm/i915/display/intel_dp_hdcp.c -static -bool intel_dp_mst_hdcp_check_link(struct intel_digital_port *dig_port, - struct intel_connector *connector) +static bool intel_dp_mst_get_qses_status(struct intel_digital_port *dig_port, + struct intel_connector *connector) - struct intel_dp *intel_dp = &dig_port->dp; + struct intel_dp *intel_dp = &dig_port->dp; - if (!intel_dp_hdcp_check_link(dig_port, connector)) - return false; - +static +bool intel_dp_mst_hdcp_check_link(struct intel_digital_port *dig_port, + struct intel_connector *connector) +{ + if (!intel_dp_hdcp_check_link(dig_port, connector)) + return false; + + return intel_dp_mst_get_qses_status(dig_port, connector); +} + +static int +intel_dp_mst_hdcp2_stream_encryption(struct intel_connector *connector, + bool enable) +{ + struct intel_digital_port *dig_port = intel_attached_dig_port(connector); + struct drm_i915_private *i915 = to_i915(connector->base.dev); + struct hdcp_port_data *data = &dig_port->hdcp_port_data; + struct intel_hdcp *hdcp = &connector->hdcp; + enum transcoder cpu_transcoder = hdcp->stream_transcoder; + enum pipe pipe = (enum pipe)cpu_transcoder; + enum port port = dig_port->base.port; + int ret; + + drm_warn_on(&i915->drm, enable && + !!(intel_de_read(i915, hdcp2_auth_stream(i915, cpu_transcoder, port)) + & auth_stream_type) != data->streams[0].stream_type); + + ret = intel_dp_mst_toggle_hdcp_stream_select(connector, enable); + if (ret) + return ret; + + /* wait for encryption confirmation */ + if (intel_de_wait_for_register(i915, + hdcp2_stream_status(i915, cpu_transcoder, pipe), + stream_encryption_status, + enable ? stream_encryption_status : 0, + hdcp_encrypt_status_change_timeout_ms)) { + drm_err(&i915->drm, "timed out waiting for transcoder: %s stream encryption %s ", + transcoder_name(cpu_transcoder), enable ? "enabled" : "disabled"); + return -etimedout; + } + + return 0; +} + +/* + * dp v2.0 i.3.3 ignore the stream signature l' in qses reply msg reply. + * i.3.5 mst source device may use a qses msg to query downstream status + * for a particular stream. + */ +static +int intel_dp_mst_hdcp2_check_link(struct intel_digital_port *dig_port, + struct intel_connector *connector) +{ + struct intel_hdcp *hdcp = &connector->hdcp; + int ret; + + /* + * we do need to do the link check only for the connector involved with + * hdcp port authentication and encryption. + * we can re-use the hdcp->is_repeater flag to know that the connector + * involved with hdcp port authentication and encryption. + */ + if (hdcp->is_repeater) { + ret = intel_dp_hdcp2_check_link(dig_port, connector); + if (ret) + return ret; + } + + return intel_dp_mst_get_qses_status(dig_port, connector) ? 0 : -einval; +} + - + .write_2_2_msg = intel_dp_hdcp2_write_msg, + .read_2_2_msg = intel_dp_hdcp2_read_msg, + .config_stream_type = intel_dp_hdcp2_config_stream_type, + .stream_2_2_encryption = intel_dp_mst_hdcp2_stream_encryption, + .check_2_2_link = intel_dp_mst_hdcp2_check_link, + .hdcp_2_2_capable = intel_dp_hdcp2_capable,
|
Graphics
|
e9fd05c3e4f21a623c98feace601a02179522fea
|
anshuman gupta
|
drivers
|
gpu
|
display, drm, i915
|
drm/i915/hdcp: configure hdcp2.2 mst steram encryption status
|
authenticate and enable port encryption only once for an active hdcp 2.2 session, once port is authenticated and encrypted enable encryption for each stream that requires encryption on this port.
|
this release allows to map an uid to a different one in a mount; it also adds support for selecting the preemption model at runtime; support for a low-overhead memory error detector designed to be used in production; support for the acrn hypervisor designed for embedded systems; btrfs initial support for zoned devices, subpage blocks sizes and performance improvements; support for eager nfs writes; support for a thermal power management to control the surface temperature of embedded devices in an unified way; the napi polling can be moved to a kernel thread; and support for non-blocking path lookups. as always, there are many other features, new drivers, improvements and fixes.
|
hdcp 2.2 and hdcp 1.4 gen12 dp mst support
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'cryptography', 'security', 'networking', 'architectures x86 arm risc-v powerpc mips csky s390 pa-risc c6x']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'cpu frequency scaling', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'cryptography hardware acceleration', 'pci', 'non-transparent bridge (ntb)', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'cxl (compute express link)', 'various']
|
['intel ']
|
['c']
| 1
| 50
| 1
|
- add connector details in drm_err. [ram] - 's/port_auth/hdcp_auth_status'. [ram] - added a debug print for stream enc. - uniformity for connector detail in dmesg. [ram] --- diff --git a/drivers/gpu/drm/i915/display/intel_hdcp.c b/drivers/gpu/drm/i915/display/intel_hdcp.c --- a/drivers/gpu/drm/i915/display/intel_hdcp.c +++ b/drivers/gpu/drm/i915/display/intel_hdcp.c +static int hdcp2_enable_stream_encryption(struct intel_connector *connector) +{ + struct intel_digital_port *dig_port = intel_attached_dig_port(connector); + struct drm_i915_private *dev_priv = to_i915(connector->base.dev); + struct intel_hdcp *hdcp = &connector->hdcp; + enum transcoder cpu_transcoder = hdcp->cpu_transcoder; + enum port port = dig_port->base.port; + int ret = 0; + + if (!(intel_de_read(dev_priv, hdcp2_status(dev_priv, cpu_transcoder, port)) & + link_encryption_status)) { + drm_err(&dev_priv->drm, "[%s:%d] hdcp 2.2 link is not encrypted ", + connector->base.name, connector->base.base.id); + return -eperm; + } + + if (hdcp->shim->stream_2_2_encryption) { + ret = hdcp->shim->stream_2_2_encryption(connector, true); + if (ret) { + drm_err(&dev_priv->drm, "[%s:%d] failed to enable hdcp 2.2 stream enc ", + connector->base.name, connector->base.base.id); + return ret; + } + drm_dbg_kms(&dev_priv->drm, "hdcp 2.2 transcoder: %s stream encrypted ", + transcoder_name(hdcp->stream_transcoder)); + } + + return ret; +} + - if (!ret) { + if (!ret && !dig_port->hdcp_auth_status) { + ret = hdcp2_enable_stream_encryption(connector); + + struct intel_hdcp *hdcp = &connector->hdcp; + if (hdcp->shim->stream_2_2_encryption) { + ret = hdcp->shim->stream_2_2_encryption(connector, false); + if (ret) { + drm_err(&i915->drm, "[%s:%d] failed to disable hdcp 2.2 stream enc ", + connector->base.name, connector->base.base.id); + return ret; + } + drm_dbg_kms(&i915->drm, "hdcp 2.2 transcoder: %s stream encryption disabled ", + transcoder_name(hdcp->stream_transcoder)); + } + + if (dig_port->num_hdcp_streams > 0) + return ret; + + mutex_lock(&dig_port->hdcp_mutex); + mutex_unlock(&dig_port->hdcp_mutex);
|
Graphics
|
899c8762f981553c5d572bf81f4c9c28c25793ef
|
anshuman gupta
|
drivers
|
gpu
|
display, drm, i915
|
drm/i915/hdcp: enable hdcp 2.2 mst support
|
enable hdcp 2.2 mst support till gen12.
|
this release allows to map an uid to a different one in a mount; it also adds support for selecting the preemption model at runtime; support for a low-overhead memory error detector designed to be used in production; support for the acrn hypervisor designed for embedded systems; btrfs initial support for zoned devices, subpage blocks sizes and performance improvements; support for eager nfs writes; support for a thermal power management to control the surface temperature of embedded devices in an unified way; the napi polling can be moved to a kernel thread; and support for non-blocking path lookups. as always, there are many other features, new drivers, improvements and fixes.
|
hdcp 2.2 and hdcp 1.4 gen12 dp mst support
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'cryptography', 'security', 'networking', 'architectures x86 arm risc-v powerpc mips csky s390 pa-risc c6x']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'cpu frequency scaling', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'cryptography hardware acceleration', 'pci', 'non-transparent bridge (ntb)', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'cxl (compute express link)', 'various']
|
['intel ']
|
['c']
| 1
| 1
| 1
|
--- diff --git a/drivers/gpu/drm/i915/display/intel_hdcp.c b/drivers/gpu/drm/i915/display/intel_hdcp.c --- a/drivers/gpu/drm/i915/display/intel_hdcp.c +++ b/drivers/gpu/drm/i915/display/intel_hdcp.c - if (is_hdcp2_supported(dev_priv) && !connector->mst_port) + if (is_hdcp2_supported(dev_priv))
|
Graphics
|
d5a0d4b9380a499cc140c7ee04ec80e15a8d49e5
|
anshuman gupta ramalingam c ramalingam c intel com karthik b s karthik b s intel com
|
drivers
|
gpu
|
display, drm, i915
|
drm/framebuffer: format modifier for intel gen 12 render compression with clear color
|
gen12 display can decompress surfaces compressed by render engine with clear color, add a new modifier as the driver needs to know the surface was compressed by render engine.
|
this release allows to map an uid to a different one in a mount; it also adds support for selecting the preemption model at runtime; support for a low-overhead memory error detector designed to be used in production; support for the acrn hypervisor designed for embedded systems; btrfs initial support for zoned devices, subpage blocks sizes and performance improvements; support for eager nfs writes; support for a thermal power management to control the surface temperature of embedded devices in an unified way; the napi polling can be moved to a kernel thread; and support for non-blocking path lookups. as always, there are many other features, new drivers, improvements and fixes.
|
clear color support for tgl render decompression
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'cryptography', 'security', 'networking', 'architectures x86 arm risc-v powerpc mips csky s390 pa-risc c6x']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'cpu frequency scaling', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'cryptography hardware acceleration', 'pci', 'non-transparent bridge (ntb)', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'cxl (compute express link)', 'various']
|
['intel ']
|
['h']
| 1
| 19
| 0
|
--- diff --git a/include/uapi/drm/drm_fourcc.h b/include/uapi/drm/drm_fourcc.h --- a/include/uapi/drm/drm_fourcc.h +++ b/include/uapi/drm/drm_fourcc.h +/* + * intel color control surface with clear color (ccs) for gen-12 render + * compression. + * + * the main surface is y-tiled and is at plane index 0 whereas ccs is linear + * and at index 1. the clear color is stored at index 2, and the pitch should + * be ignored. the clear color structure is 256 bits. the first 128 bits + * represents raw clear color red, green, blue and alpha color each represented + * by 32 bits. the raw clear color is consumed by the 3d engine and generates + * the converted clear color of size 64 bits. the first 32 bits store the lower + * converted clear color value and the next 32 bits store the higher converted + * clear color value when applicable. the converted clear color values are + * consumed by the de. the last 64 bits are used to store color discard enable + * and depth clear value valid which are ignored by the de. a ccs cache line + * corresponds to an area of 4x1 tiles in the main surface. the main surface + * pitch is required to be a multiple of 4 tile widths. + */ +#define i915_format_mod_y_tiled_gen12_rc_ccs_cc fourcc_mod_code(intel, 8) +
|
Graphics
|
87199e4c2490ab4ba0483a5ae5690c19b5c3d45b
|
radhakrishna sripada
|
include
|
uapi
|
drm
|
drm/i915/gem: add a helper to read data from a gem object page
|
add a simple helper to read data with the cpu from the page of a gem object. do the read either via a kmap if the object has struct pages or an iomap otherwise. this is needed by the next patch, reading a u64 value from the object (w/o requiring the obj to be mapped to the gpu).
|
this release allows to map an uid to a different one in a mount; it also adds support for selecting the preemption model at runtime; support for a low-overhead memory error detector designed to be used in production; support for the acrn hypervisor designed for embedded systems; btrfs initial support for zoned devices, subpage blocks sizes and performance improvements; support for eager nfs writes; support for a thermal power management to control the surface temperature of embedded devices in an unified way; the napi polling can be moved to a kernel thread; and support for non-blocking path lookups. as always, there are many other features, new drivers, improvements and fixes.
|
clear color support for tgl render decompression
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'cryptography', 'security', 'networking', 'architectures x86 arm risc-v powerpc mips csky s390 pa-risc c6x']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'cpu frequency scaling', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'cryptography hardware acceleration', 'pci', 'non-transparent bridge (ntb)', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'cxl (compute express link)', 'various']
|
['intel ']
|
['h', 'c']
| 2
| 73
| 0
|
- sanitize the type and order of func params. - avoid consts requiring too many casts. - use bug_on instead of warn_on, simplify the conditions. - fix __iomem sparse errors. - leave locking/syncing/pinning up to the caller, require only that the - check for iomem backing store before reading via an iomap. - fix offset passed to io_mapping_map_wc() missing a mem.region.start --- diff --git a/drivers/gpu/drm/i915/gem/i915_gem_object.c b/drivers/gpu/drm/i915/gem/i915_gem_object.c --- a/drivers/gpu/drm/i915/gem/i915_gem_object.c +++ b/drivers/gpu/drm/i915/gem/i915_gem_object.c +#include "i915_memcpy.h" +static void +i915_gem_object_read_from_page_kmap(struct drm_i915_gem_object *obj, u64 offset, void *dst, int size) +{ + void *src_map; + void *src_ptr; + + src_map = kmap_atomic(i915_gem_object_get_page(obj, offset >> page_shift)); + + src_ptr = src_map + offset_in_page(offset); + if (!(obj->cache_coherent & i915_bo_cache_coherent_for_read)) + drm_clflush_virt_range(src_ptr, size); + memcpy(dst, src_ptr, size); + + kunmap_atomic(src_map); +} + +static void +i915_gem_object_read_from_page_iomap(struct drm_i915_gem_object *obj, u64 offset, void *dst, int size) +{ + void __iomem *src_map; + void __iomem *src_ptr; + dma_addr_t dma = i915_gem_object_get_dma_address(obj, offset >> page_shift); + + src_map = io_mapping_map_wc(&obj->mm.region->iomap, + dma - obj->mm.region->region.start, + page_size); + + src_ptr = src_map + offset_in_page(offset); + if (!i915_memcpy_from_wc(dst, (void __force *)src_ptr, size)) + memcpy_fromio(dst, src_ptr, size); + + io_mapping_unmap(src_map); +} + +/** + * i915_gem_object_read_from_page - read data from the page of a gem object + * @obj: gem object to read from + * @offset: offset within the object + * @dst: buffer to store the read data + * @size: size to read + * + * reads data from @obj at the specified offset. the requested region to read + * from can't cross a page boundary. the caller must ensure that @obj pages + * are pinned and that @obj is synced wrt. any related writes. + * + * returns 0 on success or -enodev if the type of @obj's backing store is + * unsupported. + */ +int i915_gem_object_read_from_page(struct drm_i915_gem_object *obj, u64 offset, void *dst, int size) +{ + gem_bug_on(offset >= obj->base.size); + gem_bug_on(offset_in_page(offset) > page_size - size); + gem_bug_on(!i915_gem_object_has_pinned_pages(obj)); + + if (i915_gem_object_has_struct_page(obj)) + i915_gem_object_read_from_page_kmap(obj, offset, dst, size); + else if (i915_gem_object_has_iomem(obj)) + i915_gem_object_read_from_page_iomap(obj, offset, dst, size); + else + return -enodev; + + return 0; +} + diff --git a/drivers/gpu/drm/i915/gem/i915_gem_object.h b/drivers/gpu/drm/i915/gem/i915_gem_object.h --- a/drivers/gpu/drm/i915/gem/i915_gem_object.h +++ b/drivers/gpu/drm/i915/gem/i915_gem_object.h +static inline bool +i915_gem_object_has_iomem(const struct drm_i915_gem_object *obj) +{ + return i915_gem_object_type_has(obj, i915_gem_object_has_iomem); +} + +int i915_gem_object_read_from_page(struct drm_i915_gem_object *obj, u64 offset, void *dst, int size); +
|
Graphics
|
5fbc2c2bfa5c9daf885e51038e66645916e83966
|
imre deak
|
drivers
|
gpu
|
drm, gem, i915
|
drm/i915/tgl: add clear color support for tgl render decompression
|
render decompression is supported with y-tiled main surface. the ccs is linear and has 4 bits of data for each main surface cache line pair, a ratio of 1:256. additional clear color information is passed from the user-space through an offset in the gem bo. add a new modifier to identify and parse new clear color information and extend gen12 render decompression functionality to the newly added modifier.
|
this release allows to map an uid to a different one in a mount; it also adds support for selecting the preemption model at runtime; support for a low-overhead memory error detector designed to be used in production; support for the acrn hypervisor designed for embedded systems; btrfs initial support for zoned devices, subpage blocks sizes and performance improvements; support for eager nfs writes; support for a thermal power management to control the surface temperature of embedded devices in an unified way; the napi polling can be moved to a kernel thread; and support for non-blocking path lookups. as always, there are many other features, new drivers, improvements and fixes.
|
clear color support for tgl render decompression
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'cryptography', 'security', 'networking', 'architectures x86 arm risc-v powerpc mips csky s390 pa-risc c6x']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'cpu frequency scaling', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'cryptography hardware acceleration', 'pci', 'non-transparent bridge (ntb)', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'cxl (compute express link)', 'various']
|
['intel ']
|
['h', 'c']
| 4
| 116
| 5
|
- use format block descriptors to get the subsampling calculations for - use helpers to convert between main and ccs surfaces. - prevent coordinate checks for the cc surface. - simplify reading cc value from surface map, add description of cc val - remove redundant ccval variable from skl_program_plane(). - move the cc value readout after syncing against any gpu write on the - make sure the cc value readout works on platforms w/o struct pages - rebase on the function param order change of - clarify code comment on the clear color value format and the required - remove redundant variables in - fix s/sizeof(&ccval)/sizeof(ccval)/ typo. --- diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c --- a/drivers/gpu/drm/i915/display/intel_display.c +++ b/drivers/gpu/drm/i915/display/intel_display.c +#include "gem/i915_gem_object.h" + + modifier == i915_format_mod_y_tiled_gen12_rc_ccs_cc || - +static bool is_gen12_ccs_cc_plane(const struct drm_framebuffer *fb, int plane) +{ + return fb->modifier == i915_format_mod_y_tiled_gen12_rc_ccs_cc && + plane == 2; +} + + if (is_gen12_ccs_cc_plane(fb, ccs_plane)) + return 0; + + case i915_format_mod_y_tiled_gen12_rc_ccs_cc: + case i915_format_mod_y_tiled_gen12_rc_ccs_cc: + case i915_format_mod_y_tiled_gen12_rc_ccs_cc: +/* + * same as gen12_ccs_formats[] above, but with additional surface used + * to pass clear color information in plane 2 with 64 bits of data. + */ +static const struct drm_format_info gen12_ccs_cc_formats[] = { + { .format = drm_format_xrgb8888, .depth = 24, .num_planes = 3, + .char_per_block = { 4, 1, 0 }, .block_w = { 1, 2, 2 }, .block_h = { 1, 1, 1 }, + .hsub = 1, .vsub = 1, }, + { .format = drm_format_xbgr8888, .depth = 24, .num_planes = 3, + .char_per_block = { 4, 1, 0 }, .block_w = { 1, 2, 2 }, .block_h = { 1, 1, 1 }, + .hsub = 1, .vsub = 1, }, + { .format = drm_format_argb8888, .depth = 32, .num_planes = 3, + .char_per_block = { 4, 1, 0 }, .block_w = { 1, 2, 2 }, .block_h = { 1, 1, 1 }, + .hsub = 1, .vsub = 1, .has_alpha = true }, + { .format = drm_format_abgr8888, .depth = 32, .num_planes = 3, + .char_per_block = { 4, 1, 0 }, .block_w = { 1, 2, 2 }, .block_h = { 1, 1, 1 }, + .hsub = 1, .vsub = 1, .has_alpha = true }, +}; + + case i915_format_mod_y_tiled_gen12_rc_ccs_cc: + return lookup_format_info(gen12_ccs_cc_formats, + array_size(gen12_ccs_cc_formats), + cmd->pixel_format); + modifier == i915_format_mod_y_tiled_gen12_rc_ccs_cc || - if (!is_ccs_plane(fb, ccs_plane)) + if (!is_ccs_plane(fb, ccs_plane) || is_gen12_ccs_cc_plane(fb, ccs_plane)) + /* + * plane 2 of render compression with clear color fb modifier + * is consumed by the driver and not passed to de. skip the + * arithmetic related to alignment and offset calculation. + */ + if (is_gen12_ccs_cc_plane(fb, i)) { + if (is_aligned(fb->offsets[i], page_size)) + continue; + else + return -einval; + } + - if (!is_ccs_plane(fb, ccs_plane)) + if (!is_ccs_plane(fb, ccs_plane) || + is_gen12_ccs_cc_plane(fb, ccs_plane)) + case i915_format_mod_y_tiled_gen12_rc_ccs_cc: +static void intel_atomic_prepare_plane_clear_colors(struct intel_atomic_state *state) +{ + struct drm_i915_private *i915 = to_i915(state->base.dev); + struct intel_plane *plane; + struct intel_plane_state *plane_state; + int i; + + for_each_new_intel_plane_in_state(state, plane, plane_state, i) { + struct drm_framebuffer *fb = plane_state->hw.fb; + int ret; + + if (!fb || + fb->modifier != i915_format_mod_y_tiled_gen12_rc_ccs_cc) + continue; + + /* + * the layout of the fast clear color value expected by hw + * (the drm abi requiring this value to be located in fb at offset 0 of plane#2): + * - 4 x 4 bytes per-channel value + * (in surface type specific float/int format provided by the fb user) + * - 8 bytes native color value used by the display + * (converted/written by gpu during a fast clear operation using the + * above per-channel values) + * + * the commit's fb prepare hook already ensured that fb obj is pinned and the + * caller made sure that the object is synced wrt. the related color clear value + * gpu write on it. + */ + ret = i915_gem_object_read_from_page(intel_fb_obj(fb), + fb->offsets[2] + 16, + &plane_state->ccval, + sizeof(plane_state->ccval)); + /* the above could only fail if the fb obj has an unexpected backing store type. */ + drm_warn_on(&i915->drm, ret); + } +} + + intel_atomic_prepare_plane_clear_colors(state); + - if (is_gen12_ccs_plane(fb, i)) { + if (is_gen12_ccs_plane(fb, i) && !is_gen12_ccs_cc_plane(fb, i)) { diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h --- a/drivers/gpu/drm/i915/display/intel_display_types.h +++ b/drivers/gpu/drm/i915/display/intel_display_types.h + + /* clear color value */ + u64 ccval; diff --git a/drivers/gpu/drm/i915/display/intel_sprite.c b/drivers/gpu/drm/i915/display/intel_sprite.c --- a/drivers/gpu/drm/i915/display/intel_sprite.c +++ b/drivers/gpu/drm/i915/display/intel_sprite.c + if (fb->modifier == i915_format_mod_y_tiled_gen12_rc_ccs_cc) + intel_uncore_write64_fw(&dev_priv->uncore, + plane_cc_val(pipe, plane_id), plane_state->ccval); + - fb->modifier == i915_format_mod_y_tiled_gen12_mc_ccs)) { + fb->modifier == i915_format_mod_y_tiled_gen12_mc_ccs || + fb->modifier == i915_format_mod_y_tiled_gen12_rc_ccs_cc)) { + i915_format_mod_y_tiled_gen12_rc_ccs_cc, + i915_format_mod_y_tiled_gen12_rc_ccs_cc, + case i915_format_mod_y_tiled_gen12_rc_ccs_cc: diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h +#define _plane_cc_val_1_a 0x701b4 +#define _plane_cc_val_2_a 0x702b4 +#define _plane_cc_val_1_b 0x711b4 +#define _plane_cc_val_2_b 0x712b4 +#define _plane_cc_val_1(pipe) _pipe(pipe, _plane_cc_val_1_a, _plane_cc_val_1_b) +#define _plane_cc_val_2(pipe) _pipe(pipe, _plane_cc_val_2_a, _plane_cc_val_2_b) +#define plane_cc_val(pipe, plane) \ + _mmio_plane(plane, _plane_cc_val_1(pipe), _plane_cc_val_2(pipe)) +
|
Graphics
|
d1e2775e9b9690b3f4488ee8e44773b580654d68
|
radhakrishna sripada
|
drivers
|
gpu
|
display, drm, i915
|
drm/i915: add vrr_ctl_line_count field to vrr_ctl register def
|
vrr_ctl register only had a genmask but no field prep define for trans_vrr_ctl_line_count field so add that
|
this release allows to map an uid to a different one in a mount; it also adds support for selecting the preemption model at runtime; support for a low-overhead memory error detector designed to be used in production; support for the acrn hypervisor designed for embedded systems; btrfs initial support for zoned devices, subpage blocks sizes and performance improvements; support for eager nfs writes; support for a thermal power management to control the surface temperature of embedded devices in an unified way; the napi polling can be moved to a kernel thread; and support for non-blocking path lookups. as always, there are many other features, new drivers, improvements and fixes.
|
vrr/adaptive sync enabling on dp/edp for tgl+
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'cryptography', 'security', 'networking', 'architectures x86 arm risc-v powerpc mips csky s390 pa-risc c6x']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'cpu frequency scaling', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'cryptography hardware acceleration', 'pci', 'non-transparent bridge (ntb)', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'cxl (compute express link)', 'various']
|
['intel ']
|
['h']
| 1
| 1
| 0
|
--- diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h +#define vrr_ctl_line_count(x) reg_field_prep(vrr_ctl_line_count_mask, (x))
|
Graphics
|
97ffcd0d1eeca8b123453a900e7768d07408ebf9
|
manasi navare jani nikula jani nikula intel com
|
drivers
|
gpu
|
drm, i915
|
drm/i915/display/vrr: create vrr file and add vrr capability check
|
we create a new file for all vrr related helpers. also add a function to check vrr capability based on platform support, dpcd bits and edid monitor range.
|
this release allows to map an uid to a different one in a mount; it also adds support for selecting the preemption model at runtime; support for a low-overhead memory error detector designed to be used in production; support for the acrn hypervisor designed for embedded systems; btrfs initial support for zoned devices, subpage blocks sizes and performance improvements; support for eager nfs writes; support for a thermal power management to control the surface temperature of embedded devices in an unified way; the napi polling can be moved to a kernel thread; and support for non-blocking path lookups. as always, there are many other features, new drivers, improvements and fixes.
|
vrr/adaptive sync enabling on dp/edp for tgl+
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'cryptography', 'security', 'networking', 'architectures x86 arm risc-v powerpc mips csky s390 pa-risc c6x']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'cpu frequency scaling', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'cryptography hardware acceleration', 'pci', 'non-transparent bridge (ntb)', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'cxl (compute express link)', 'various']
|
['intel ']
|
['h', 'c', 'makefile']
| 4
| 49
| 0
|
--- diff --git a/drivers/gpu/drm/i915/makefile b/drivers/gpu/drm/i915/makefile --- a/drivers/gpu/drm/i915/makefile +++ b/drivers/gpu/drm/i915/makefile + display/intel_vrr.o \ diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c b/drivers/gpu/drm/i915/display/intel_vrr.c --- /dev/null +++ b/drivers/gpu/drm/i915/display/intel_vrr.c +// spdx-license-identifier: mit +/* + * copyright ©️ 2020 intel corporation + * + */ + +#include "i915_drv.h" +#include "intel_display_types.h" +#include "intel_vrr.h" + +bool intel_vrr_is_capable(struct drm_connector *connector) +{ + struct intel_dp *intel_dp; + const struct drm_display_info *info = &connector->display_info; + struct drm_i915_private *i915 = to_i915(connector->dev); + + if (connector->connector_type != drm_mode_connector_edp && + connector->connector_type != drm_mode_connector_displayport) + return false; + + intel_dp = intel_attached_dp(to_intel_connector(connector)); + /* + * dp sink is capable of variable refresh video timings if + * ignore msa bit is set in dpcd. + * edid monitor range also should be atleast 10 for reasonable + * adaptive sync/ vrr end user experience. + */ + return has_vrr(i915) && + drm_dp_sink_can_do_video_without_timing_msa(intel_dp->dpcd) && + info->monitor_range.max_vfreq - info->monitor_range.min_vfreq > 10; +} diff --git a/drivers/gpu/drm/i915/display/intel_vrr.h b/drivers/gpu/drm/i915/display/intel_vrr.h --- /dev/null +++ b/drivers/gpu/drm/i915/display/intel_vrr.h +/* spdx-license-identifier: mit */ +/* + * copyright ©️ 2019 intel corporation + */ + +#ifndef __intel_vrr_h__ +#define __intel_vrr_h__ + +#include <linux/types.h> + +struct drm_connector; + +bool intel_vrr_is_capable(struct drm_connector *connector); + +#endif /* __intel_vrr_h__ */ diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h +#define has_vrr(i915) (intel_gen(i915) >= 12) +
|
Graphics
|
5b0c59454314f1c6f384826c6fb30023c981b5e6
|
manasi navare
|
drivers
|
gpu
|
display, drm, i915
|
drm/i915/display/dp: attach and set drm connector vrr property
|
this function sets the vrr property for connector based on the platform support, edid monitor range and dp sink dpcd capability of outputing video without msa timing information.
|
this release allows to map an uid to a different one in a mount; it also adds support for selecting the preemption model at runtime; support for a low-overhead memory error detector designed to be used in production; support for the acrn hypervisor designed for embedded systems; btrfs initial support for zoned devices, subpage blocks sizes and performance improvements; support for eager nfs writes; support for a thermal power management to control the surface temperature of embedded devices in an unified way; the napi polling can be moved to a kernel thread; and support for non-blocking path lookups. as always, there are many other features, new drivers, improvements and fixes.
|
vrr/adaptive sync enabling on dp/edp for tgl+
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'cryptography', 'security', 'networking', 'architectures x86 arm risc-v powerpc mips csky s390 pa-risc c6x']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'cpu frequency scaling', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'cryptography hardware acceleration', 'pci', 'non-transparent bridge (ntb)', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'cxl (compute express link)', 'various']
|
['intel ']
|
['c']
| 2
| 10
| 2
|
--- diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c --- a/drivers/gpu/drm/i915/display/intel_dp.c +++ b/drivers/gpu/drm/i915/display/intel_dp.c +#include "intel_vrr.h" + + if (intel_vrr_is_capable(connector)) + drm_connector_set_vrr_capable_property(connector, + true); + + if (has_vrr(dev_priv)) + drm_connector_attach_vrr_capable_property(connector); diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c b/drivers/gpu/drm/i915/display/intel_vrr.c --- a/drivers/gpu/drm/i915/display/intel_vrr.c +++ b/drivers/gpu/drm/i915/display/intel_vrr.c - * dp sink is capable of variable refresh video timings if + * dp sink is capable of vrr video timings if - * adaptive sync/ vrr end user experience. + * adaptive sync or variable refresh rate end user experience.
|
Graphics
|
3dafe8a8532dc5fa2ae7e9d1dd77e3a6932b808f
|
aditya swarup
|
drivers
|
gpu
|
display, drm, i915
|
drm/i915/display/dp: compute vrr state in atomic_check
|
this forces a complete modeset if vrr drm crtc state goes from enabled to disabled and vice versa. this patch also computes vrr state variables from the mode timings and based on the vrr property set by userspace as well as hardware's vrr capability.
|
this release allows to map an uid to a different one in a mount; it also adds support for selecting the preemption model at runtime; support for a low-overhead memory error detector designed to be used in production; support for the acrn hypervisor designed for embedded systems; btrfs initial support for zoned devices, subpage blocks sizes and performance improvements; support for eager nfs writes; support for a thermal power management to control the surface temperature of embedded devices in an unified way; the napi polling can be moved to a kernel thread; and support for non-blocking path lookups. as always, there are many other features, new drivers, improvements and fixes.
|
vrr/adaptive sync enabling on dp/edp for tgl+
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'cryptography', 'security', 'networking', 'architectures x86 arm risc-v powerpc mips csky s390 pa-risc c6x']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'cpu frequency scaling', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'cryptography hardware acceleration', 'pci', 'non-transparent bridge (ntb)', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'cxl (compute express link)', 'various']
|
['intel ']
|
['h', 'c']
| 5
| 95
| 0
|
--- diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c --- a/drivers/gpu/drm/i915/display/intel_display.c +++ b/drivers/gpu/drm/i915/display/intel_display.c +#include "display/intel_vrr.h" + pipe_conf_check_bool(vrr.enable); + pipe_conf_check_i(vrr.vmin); + pipe_conf_check_i(vrr.vmax); + pipe_conf_check_i(vrr.flipline); + pipe_conf_check_i(vrr.pipeline_full); + + intel_vrr_check_modeset(state); + diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h --- a/drivers/gpu/drm/i915/display/intel_display_types.h +++ b/drivers/gpu/drm/i915/display/intel_display_types.h + + /* variable refresh rate state */ + struct { + bool enable; + u8 pipeline_full; + u16 flipline, vmin, vmax; + } vrr; diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c --- a/drivers/gpu/drm/i915/display/intel_dp.c +++ b/drivers/gpu/drm/i915/display/intel_dp.c + intel_vrr_compute_config(pipe_config, conn_state); diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c b/drivers/gpu/drm/i915/display/intel_vrr.c --- a/drivers/gpu/drm/i915/display/intel_vrr.c +++ b/drivers/gpu/drm/i915/display/intel_vrr.c + +void +intel_vrr_check_modeset(struct intel_atomic_state *state) +{ + int i; + struct intel_crtc_state *old_crtc_state, *new_crtc_state; + struct intel_crtc *crtc; + + for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, + new_crtc_state, i) { + if (new_crtc_state->uapi.vrr_enabled != + old_crtc_state->uapi.vrr_enabled) + new_crtc_state->uapi.mode_changed = true; + } +} + +void +intel_vrr_compute_config(struct intel_crtc_state *crtc_state, + struct drm_connector_state *conn_state) +{ + struct intel_connector *connector = + to_intel_connector(conn_state->connector); + struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode; + const struct drm_display_info *info = &connector->base.display_info; + int vmin, vmax; + + if (!intel_vrr_is_capable(&connector->base)) + return; + + if (adjusted_mode->flags & drm_mode_flag_interlace) + return; + + if (!crtc_state->uapi.vrr_enabled) + return; + + vmin = div_round_up(adjusted_mode->crtc_clock * 1000, + adjusted_mode->crtc_htotal * info->monitor_range.max_vfreq); + vmax = adjusted_mode->crtc_clock * 1000 / + (adjusted_mode->crtc_htotal * info->monitor_range.min_vfreq); + + vmin = max_t(int, vmin, adjusted_mode->crtc_vtotal); + vmax = max_t(int, vmax, adjusted_mode->crtc_vtotal); + + if (vmin >= vmax) + return; + + /* + * flipline determines the min vblank length the hardware will + * generate, and flipline>=vmin+1, hence we reduce vmin by one + * to make sure we can get the actual min vblank length. + */ + crtc_state->vrr.vmin = vmin - 1; + crtc_state->vrr.vmax = vmax; + crtc_state->vrr.enable = true; + + crtc_state->vrr.flipline = crtc_state->vrr.vmin + 1; + + /* + * fixme: s/4/framestart_delay+1/ to get consistent + * earliest/latest points for register latching regardless + * of the framestart_delay used? + * + * fixme: this really needs the extra scanline to provide consistent + * behaviour for all framestart_delay values. otherwise with + * framestart_delay==3 we will end up extending the min vblank by + * one extra line. + */ + crtc_state->vrr.pipeline_full = + min(255, crtc_state->vrr.vmin - adjusted_mode->crtc_vdisplay - 4 - 1); +} diff --git a/drivers/gpu/drm/i915/display/intel_vrr.h b/drivers/gpu/drm/i915/display/intel_vrr.h --- a/drivers/gpu/drm/i915/display/intel_vrr.h +++ b/drivers/gpu/drm/i915/display/intel_vrr.h +struct drm_connector_state; +struct intel_atomic_state; +struct intel_crtc; +struct intel_crtc_state; +struct intel_dp; +void intel_vrr_check_modeset(struct intel_atomic_state *state); +void intel_vrr_compute_config(struct intel_crtc_state *crtc_state, + struct drm_connector_state *conn_state);
|
Graphics
|
117cd09ba52857a60dc5d7f61941046625d8ff5a
|
manasi navare
|
drivers
|
gpu
|
display, drm, i915
|
drm/i915/display/dp: do not enable psr if vrr is enabled
|
even though our hw supports psr + vrr, the available panels do not work reliably with psr and vrr together. so if user requested vrr and is supported by hw enable that and do not enable psr in that case.
|
this release allows to map an uid to a different one in a mount; it also adds support for selecting the preemption model at runtime; support for a low-overhead memory error detector designed to be used in production; support for the acrn hypervisor designed for embedded systems; btrfs initial support for zoned devices, subpage blocks sizes and performance improvements; support for eager nfs writes; support for a thermal power management to control the surface temperature of embedded devices in an unified way; the napi polling can be moved to a kernel thread; and support for non-blocking path lookups. as always, there are many other features, new drivers, improvements and fixes.
|
vrr/adaptive sync enabling on dp/edp for tgl+
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'cryptography', 'security', 'networking', 'architectures x86 arm risc-v powerpc mips csky s390 pa-risc c6x']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'cpu frequency scaling', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'cryptography hardware acceleration', 'pci', 'non-transparent bridge (ntb)', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'cxl (compute express link)', 'various']
|
['intel ']
|
['c']
| 1
| 7
| 0
|
--- diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c --- a/drivers/gpu/drm/i915/display/intel_psr.c +++ b/drivers/gpu/drm/i915/display/intel_psr.c + /* + * current psr panels dont work reliably with vrr enabled + * so if vrr is enabled, do not enable psr. + */ + if (crtc_state->vrr.enable) + return; +
|
Graphics
|
38ff8d2824b7d65577d145114de3b7188fa265ac
|
manasi navare gwan gyeong mun gwan gyeong mun intel com
|
drivers
|
gpu
|
display, drm, i915
|
drm/i915/display/vrr: configure and enable vrr in modeset enable
|
this patch computes the vrr parameters from vrr crtc states and configures them in vrr registers during crtc enable in the modeset enable sequence.
|
this release allows to map an uid to a different one in a mount; it also adds support for selecting the preemption model at runtime; support for a low-overhead memory error detector designed to be used in production; support for the acrn hypervisor designed for embedded systems; btrfs initial support for zoned devices, subpage blocks sizes and performance improvements; support for eager nfs writes; support for a thermal power management to control the surface temperature of embedded devices in an unified way; the napi polling can be moved to a kernel thread; and support for non-blocking path lookups. as always, there are many other features, new drivers, improvements and fixes.
|
vrr/adaptive sync enabling on dp/edp for tgl+
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'cryptography', 'security', 'networking', 'architectures x86 arm risc-v powerpc mips csky s390 pa-risc c6x']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'cpu frequency scaling', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'cryptography hardware acceleration', 'pci', 'non-transparent bridge (ntb)', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'cxl (compute express link)', 'various']
|
['intel ']
|
['h', 'c']
| 3
| 28
| 0
|
--- diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c --- a/drivers/gpu/drm/i915/display/intel_ddi.c +++ b/drivers/gpu/drm/i915/display/intel_ddi.c +#include "intel_vrr.h" + intel_vrr_enable(encoder, crtc_state); + diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c b/drivers/gpu/drm/i915/display/intel_vrr.c --- a/drivers/gpu/drm/i915/display/intel_vrr.c +++ b/drivers/gpu/drm/i915/display/intel_vrr.c + +void intel_vrr_enable(struct intel_encoder *encoder, + const struct intel_crtc_state *crtc_state) +{ + struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); + enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; + u32 trans_vrr_ctl; + + if (!crtc_state->vrr.enable) + return; + + trans_vrr_ctl = vrr_ctl_vrr_enable | + vrr_ctl_ign_max_shift | vrr_ctl_flip_line_en | + vrr_ctl_pipeline_full(crtc_state->vrr.pipeline_full) | + vrr_ctl_pipeline_full_override; + + intel_de_write(dev_priv, trans_vrr_vmin(cpu_transcoder), crtc_state->vrr.vmin - 1); + intel_de_write(dev_priv, trans_vrr_vmax(cpu_transcoder), crtc_state->vrr.vmax - 1); + intel_de_write(dev_priv, trans_vrr_ctl(cpu_transcoder), trans_vrr_ctl); + intel_de_write(dev_priv, trans_vrr_flipline(cpu_transcoder), crtc_state->vrr.flipline - 1); + intel_de_write(dev_priv, trans_push(cpu_transcoder), trans_push_en); +} diff --git a/drivers/gpu/drm/i915/display/intel_vrr.h b/drivers/gpu/drm/i915/display/intel_vrr.h --- a/drivers/gpu/drm/i915/display/intel_vrr.h +++ b/drivers/gpu/drm/i915/display/intel_vrr.h +struct intel_encoder; +void intel_vrr_enable(struct intel_encoder *encoder, + const struct intel_crtc_state *crtc_state);
|
Graphics
|
aa52b39dc554de07ef7a9eb5c80b487ebbde7e7c
|
manasi navare
|
drivers
|
gpu
|
display, drm, i915
|
drm/i915/display/vrr: send vrr push to flip the frame
|
vrr achieves vblank stretching using the hw push functionality. so once the vrr is enabled during modeset then for each flip request from userspace, in the atomic tail pipe_update_end() we need to set the vrr push bit in hw for it to terminate the vblank at configured flipline or anytime after flipline or latest at the vmax.
|
this release allows to map an uid to a different one in a mount; it also adds support for selecting the preemption model at runtime; support for a low-overhead memory error detector designed to be used in production; support for the acrn hypervisor designed for embedded systems; btrfs initial support for zoned devices, subpage blocks sizes and performance improvements; support for eager nfs writes; support for a thermal power management to control the surface temperature of embedded devices in an unified way; the napi polling can be moved to a kernel thread; and support for non-blocking path lookups. as always, there are many other features, new drivers, improvements and fixes.
|
vrr/adaptive sync enabling on dp/edp for tgl+
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'cryptography', 'security', 'networking', 'architectures x86 arm risc-v powerpc mips csky s390 pa-risc c6x']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'cpu frequency scaling', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'cryptography hardware acceleration', 'pci', 'non-transparent bridge (ntb)', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'cxl (compute express link)', 'various']
|
['intel ']
|
['h', 'c']
| 3
| 18
| 0
|
--- diff --git a/drivers/gpu/drm/i915/display/intel_sprite.c b/drivers/gpu/drm/i915/display/intel_sprite.c --- a/drivers/gpu/drm/i915/display/intel_sprite.c +++ b/drivers/gpu/drm/i915/display/intel_sprite.c +#include "intel_vrr.h" + /* send vrr push to terminate vblank */ + intel_vrr_send_push(new_crtc_state); + diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c b/drivers/gpu/drm/i915/display/intel_vrr.c --- a/drivers/gpu/drm/i915/display/intel_vrr.c +++ b/drivers/gpu/drm/i915/display/intel_vrr.c + +void intel_vrr_send_push(const struct intel_crtc_state *crtc_state) +{ + struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); + struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); + enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; + + if (!crtc_state->vrr.enable) + return; + + intel_de_write(dev_priv, trans_push(cpu_transcoder), + trans_push_en | trans_push_send); +} diff --git a/drivers/gpu/drm/i915/display/intel_vrr.h b/drivers/gpu/drm/i915/display/intel_vrr.h --- a/drivers/gpu/drm/i915/display/intel_vrr.h +++ b/drivers/gpu/drm/i915/display/intel_vrr.h +void intel_vrr_send_push(const struct intel_crtc_state *crtc_state);
|
Graphics
|
13c6d51f530dcea38ae71d54e29b3507615e8b4b
|
manasi navare
|
drivers
|
gpu
|
display, drm, i915
|
drm/i915/display/vrr: disable vrr in modeset disable path
|
this patch disables the vrr enable and vrr push bits in the hw during commit modeset disable sequence.
|
this release allows to map an uid to a different one in a mount; it also adds support for selecting the preemption model at runtime; support for a low-overhead memory error detector designed to be used in production; support for the acrn hypervisor designed for embedded systems; btrfs initial support for zoned devices, subpage blocks sizes and performance improvements; support for eager nfs writes; support for a thermal power management to control the surface temperature of embedded devices in an unified way; the napi polling can be moved to a kernel thread; and support for non-blocking path lookups. as always, there are many other features, new drivers, improvements and fixes.
|
vrr/adaptive sync enabling on dp/edp for tgl+
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'cryptography', 'security', 'networking', 'architectures x86 arm risc-v powerpc mips csky s390 pa-risc c6x']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'cpu frequency scaling', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'cryptography hardware acceleration', 'pci', 'non-transparent bridge (ntb)', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'cxl (compute express link)', 'various']
|
['intel ']
|
['h', 'c']
| 3
| 16
| 0
|
--- diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c --- a/drivers/gpu/drm/i915/display/intel_ddi.c +++ b/drivers/gpu/drm/i915/display/intel_ddi.c + intel_vrr_disable(old_crtc_state); + diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c b/drivers/gpu/drm/i915/display/intel_vrr.c --- a/drivers/gpu/drm/i915/display/intel_vrr.c +++ b/drivers/gpu/drm/i915/display/intel_vrr.c + +void intel_vrr_disable(const struct intel_crtc_state *old_crtc_state) +{ + struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc); + struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); + enum transcoder cpu_transcoder = old_crtc_state->cpu_transcoder; + + if (!old_crtc_state->vrr.enable) + return; + + intel_de_write(dev_priv, trans_vrr_ctl(cpu_transcoder), 0); + intel_de_write(dev_priv, trans_push(cpu_transcoder), 0); +} diff --git a/drivers/gpu/drm/i915/display/intel_vrr.h b/drivers/gpu/drm/i915/display/intel_vrr.h --- a/drivers/gpu/drm/i915/display/intel_vrr.h +++ b/drivers/gpu/drm/i915/display/intel_vrr.h +void intel_vrr_disable(const struct intel_crtc_state *old_crtc_state);
|
Graphics
|
f065123299f5af97e9a41567560413d453279d5e
|
manasi navare
|
drivers
|
gpu
|
display, drm, i915
|
drm/i915/display/vrr: set ignore_msa_par state in dp sink
|
if vrr is enabled, the sink should ignore msa parameters and regenerate incoming video stream without depending on these parameters. hence set the msa_timing_par_ignore_en bit if vrr is enabled. reset this bit on vrr disable.
|
this release allows to map an uid to a different one in a mount; it also adds support for selecting the preemption model at runtime; support for a low-overhead memory error detector designed to be used in production; support for the acrn hypervisor designed for embedded systems; btrfs initial support for zoned devices, subpage blocks sizes and performance improvements; support for eager nfs writes; support for a thermal power management to control the surface temperature of embedded devices in an unified way; the napi polling can be moved to a kernel thread; and support for non-blocking path lookups. as always, there are many other features, new drivers, improvements and fixes.
|
vrr/adaptive sync enabling on dp/edp for tgl+
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'cryptography', 'security', 'networking', 'architectures x86 arm risc-v powerpc mips csky s390 pa-risc c6x']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'cpu frequency scaling', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'cryptography hardware acceleration', 'pci', 'non-transparent bridge (ntb)', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'cxl (compute express link)', 'various']
|
['intel ']
|
['c']
| 2
| 20
| 1
|
--- diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c --- a/drivers/gpu/drm/i915/display/intel_ddi.c +++ b/drivers/gpu/drm/i915/display/intel_ddi.c +static void intel_dp_sink_set_msa_timing_par_ignore_state(struct intel_dp *intel_dp, + const struct intel_crtc_state *crtc_state, + bool enable) +{ + struct drm_i915_private *i915 = dp_to_i915(intel_dp); + + if (!crtc_state->vrr.enable) + return; + + if (drm_dp_dpcd_writeb(&intel_dp->aux, dp_downspread_ctrl, + enable ? dp_msa_timing_par_ignore_en : 0) <= 0) + drm_dbg_kms(&i915->drm, + "failed to set msa_timing_par_ignore %s in the sink ", + enable ? "enable" : "disable"); +} + + /* disable ignore_msa bit in dp sink */ + intel_dp_sink_set_msa_timing_par_ignore_state(intel_dp, old_crtc_state, + false); diff --git a/drivers/gpu/drm/i915/display/intel_dp_link_training.c b/drivers/gpu/drm/i915/display/intel_dp_link_training.c --- a/drivers/gpu/drm/i915/display/intel_dp_link_training.c +++ b/drivers/gpu/drm/i915/display/intel_dp_link_training.c - link_config[0] = 0; + link_config[0] = crtc_state->vrr.enable ? dp_msa_timing_par_ignore_en : 0;
|
Graphics
|
1639406a31c23ca07a2b8a9b45d1c400debda9e9
|
manasi navare
|
drivers
|
gpu
|
display, drm, i915
|
drm/i915/display: add hw state readout for vrr
|
this functions gets the vrr config from the vrr registers to match the crtc state variables for vrr.
|
this release allows to map an uid to a different one in a mount; it also adds support for selecting the preemption model at runtime; support for a low-overhead memory error detector designed to be used in production; support for the acrn hypervisor designed for embedded systems; btrfs initial support for zoned devices, subpage blocks sizes and performance improvements; support for eager nfs writes; support for a thermal power management to control the surface temperature of embedded devices in an unified way; the napi polling can be moved to a kernel thread; and support for non-blocking path lookups. as always, there are many other features, new drivers, improvements and fixes.
|
vrr/adaptive sync enabling on dp/edp for tgl+
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'cryptography', 'security', 'networking', 'architectures x86 arm risc-v powerpc mips csky s390 pa-risc c6x']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'cpu frequency scaling', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'cryptography hardware acceleration', 'pci', 'non-transparent bridge (ntb)', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'cxl (compute express link)', 'various']
|
['intel ']
|
['h', 'c']
| 3
| 26
| 0
|
--- diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c --- a/drivers/gpu/drm/i915/display/intel_display.c +++ b/drivers/gpu/drm/i915/display/intel_display.c + if (has_vrr(dev_priv)) + intel_vrr_get_config(crtc, pipe_config); + diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c b/drivers/gpu/drm/i915/display/intel_vrr.c --- a/drivers/gpu/drm/i915/display/intel_vrr.c +++ b/drivers/gpu/drm/i915/display/intel_vrr.c + +void intel_vrr_get_config(struct intel_crtc *crtc, + struct intel_crtc_state *crtc_state) +{ + struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); + enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; + u32 trans_vrr_ctl; + + trans_vrr_ctl = intel_de_read(dev_priv, trans_vrr_ctl(cpu_transcoder)); + crtc_state->vrr.enable = trans_vrr_ctl & vrr_ctl_vrr_enable; + if (!crtc_state->vrr.enable) + return; + + if (trans_vrr_ctl & vrr_ctl_pipeline_full_override) + crtc_state->vrr.pipeline_full = reg_field_get(vrr_ctl_pipeline_full_mask, trans_vrr_ctl); + if (trans_vrr_ctl & vrr_ctl_flip_line_en) + crtc_state->vrr.flipline = intel_de_read(dev_priv, trans_vrr_flipline(cpu_transcoder)) + 1; + crtc_state->vrr.vmax = intel_de_read(dev_priv, trans_vrr_vmax(cpu_transcoder)) + 1; + crtc_state->vrr.vmin = intel_de_read(dev_priv, trans_vrr_vmin(cpu_transcoder)) + 1; +} diff --git a/drivers/gpu/drm/i915/display/intel_vrr.h b/drivers/gpu/drm/i915/display/intel_vrr.h --- a/drivers/gpu/drm/i915/display/intel_vrr.h +++ b/drivers/gpu/drm/i915/display/intel_vrr.h +struct intel_crtc; +void intel_vrr_get_config(struct intel_crtc *crtc, + struct intel_crtc_state *crtc_state);
|
Graphics
|
c7f0f4372b30e5496bea1a6cfdf94904dee8c0fd
|
manasi navare
|
drivers
|
gpu
|
display, drm, i915
|
drm/i915: warn if plane src coords are too big
|
inform us if we're buggy and are about to exceed the size of the bitfields in the plane tileoff/offset registers.
|
this release allows to map an uid to a different one in a mount; it also adds support for selecting the preemption model at runtime; support for a low-overhead memory error detector designed to be used in production; support for the acrn hypervisor designed for embedded systems; btrfs initial support for zoned devices, subpage blocks sizes and performance improvements; support for eager nfs writes; support for a thermal power management to control the surface temperature of embedded devices in an unified way; the napi polling can be moved to a kernel thread; and support for non-blocking path lookups. as always, there are many other features, new drivers, improvements and fixes.
|
async flips for all ilk+ platforms
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'cryptography', 'security', 'networking', 'architectures x86 arm risc-v powerpc mips csky s390 pa-risc c6x']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'cpu frequency scaling', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'cryptography hardware acceleration', 'pci', 'non-transparent bridge (ntb)', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'cxl (compute express link)', 'various']
|
['intel ']
|
['c']
| 2
| 11
| 0
|
--- diff --git a/drivers/gpu/drm/i915/display/i9xx_plane.c b/drivers/gpu/drm/i915/display/i9xx_plane.c --- a/drivers/gpu/drm/i915/display/i9xx_plane.c +++ b/drivers/gpu/drm/i915/display/i9xx_plane.c + if (is_haswell(dev_priv) || is_broadwell(dev_priv)) { + drm_warn_on(&dev_priv->drm, src_x > 8191 || src_y > 4095); + } else if (intel_gen(dev_priv) >= 4 && + fb->modifier == i915_format_mod_x_tiled) { + drm_warn_on(&dev_priv->drm, src_x > 4095 || src_y > 4095); + } + diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c --- a/drivers/gpu/drm/i915/display/intel_display.c +++ b/drivers/gpu/drm/i915/display/intel_display.c + drm_warn_on(&dev_priv->drm, x > 8191 || y > 8191); + + drm_warn_on(&i915->drm, x > 8191 || y > 8191); +
|
Graphics
|
2aa0f4faa1649199dd714f05672788910a811ce0
|
ville syrj l karthik b s karthik b s intel com
|
drivers
|
gpu
|
display, drm, i915
|
drm/i915/display: prevent double yuv range correction on hdr planes
|
prevent the icl hdr plane pipeline from performing yuv color range correction twice when the input is in limited range. this is done by removing the limited-range code from icl_program_input_csc().
|
this release allows to map an uid to a different one in a mount; it also adds support for selecting the preemption model at runtime; support for a low-overhead memory error detector designed to be used in production; support for the acrn hypervisor designed for embedded systems; btrfs initial support for zoned devices, subpage blocks sizes and performance improvements; support for eager nfs writes; support for a thermal power management to control the surface temperature of embedded devices in an unified way; the napi polling can be moved to a kernel thread; and support for non-blocking path lookups. as always, there are many other features, new drivers, improvements and fixes.
|
async flips for all ilk+ platforms
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'cryptography', 'security', 'networking', 'architectures x86 arm risc-v powerpc mips csky s390 pa-risc c6x']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'cpu frequency scaling', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'cryptography hardware acceleration', 'pci', 'non-transparent bridge (ntb)', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'cxl (compute express link)', 'various']
|
['intel ']
|
['c']
| 2
| 12
| 55
|
--- diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c --- a/drivers/gpu/drm/i915/display/intel_display.c +++ b/drivers/gpu/drm/i915/display/intel_display.c + if (plane_state->hw.color_range == drm_color_ycbcr_full_range) + plane_color_ctl |= plane_color_yuv_range_correction_disable; diff --git a/drivers/gpu/drm/i915/display/intel_sprite.c b/drivers/gpu/drm/i915/display/intel_sprite.c --- a/drivers/gpu/drm/i915/display/intel_sprite.c +++ b/drivers/gpu/drm/i915/display/intel_sprite.c -#define preoff_yuv_to_rgb_me 0x1f00 +#define preoff_yuv_to_rgb_me 0x0000 +/* + * programs the input color space conversion stage for icl hdr planes. + * note that it is assumed that this stage always happens after yuv + * range correction. thus, the input to this stage is assumed to be + * in full-range ycbcr. + */ - - /* matrix for limited range to full range conversion */ - static const u16 input_csc_matrix_lr[][9] = { - /* - * bt.601 limted range ycbcr -> full range rgb - * the matrix required is : - * [1.164384, 0.000, 1.596027, - * 1.164384, -0.39175, -0.812813, - * 1.164384, 2.017232, 0.0000] - */ - [drm_color_ycbcr_bt601] = { - 0x7cc8, 0x7950, 0x0, - 0x8d00, 0x7950, 0x9c88, - 0x0, 0x7950, 0x6810, - }, - /* - * bt.709 limited range ycbcr -> full range rgb - * the matrix required is : - * [1.164384, 0.000, 1.792741, - * 1.164384, -0.213249, -0.532909, - * 1.164384, 2.112402, 0.0000] - */ - [drm_color_ycbcr_bt709] = { - 0x7e58, 0x7950, 0x0, - 0x8888, 0x7950, 0xada8, - 0x0, 0x7950, 0x6870, - }, - /* - * bt.2020 limited range ycbcr -> full range rgb - * the matrix required is : - * [1.164, 0.000, 1.678, - * 1.164, -0.1873, -0.6504, - * 1.164, 2.1417, 0.0000] - */ - [drm_color_ycbcr_bt2020] = { - 0x7d70, 0x7950, 0x0, - 0x8a68, 0x7950, 0xac00, - 0x0, 0x7950, 0x6890, - }, - }; - const u16 *csc; - - if (plane_state->hw.color_range == drm_color_ycbcr_full_range) - csc = input_csc_matrix[plane_state->hw.color_encoding]; - else - csc = input_csc_matrix_lr[plane_state->hw.color_encoding]; + const u16 *csc = input_csc_matrix[plane_state->hw.color_encoding]; - if (plane_state->hw.color_range == drm_color_ycbcr_full_range) - intel_de_write_fw(dev_priv, - plane_input_csc_preoff(pipe, plane_id, 1), - 0); - else - intel_de_write_fw(dev_priv, - plane_input_csc_preoff(pipe, plane_id, 1), - preoff_yuv_to_rgb_me); + intel_de_write_fw(dev_priv, plane_input_csc_preoff(pipe, plane_id, 1), + preoff_yuv_to_rgb_me);
|
Graphics
|
fed387572040e84ead53852a7820e30a30e515d0
|
andres calderon jaramillo
|
drivers
|
gpu
|
display, drm, i915
|
drm/i915/hdcp: disable the qses check for hdcp 1.4 over mst
|
the hdcp 1.4 spec does not require the query_stream_encryption_status check, it was always a nice-to-have. after deploying this across various devices, we've determined that some mst bridge chips do not properly support this call for hdcp 1.4 (namely synaptics and realtek).
|
this release allows to map an uid to a different one in a mount; it also adds support for selecting the preemption model at runtime; support for a low-overhead memory error detector designed to be used in production; support for the acrn hypervisor designed for embedded systems; btrfs initial support for zoned devices, subpage blocks sizes and performance improvements; support for eager nfs writes; support for a thermal power management to control the surface temperature of embedded devices in an unified way; the napi polling can be moved to a kernel thread; and support for non-blocking path lookups. as always, there are many other features, new drivers, improvements and fixes.
|
async flips for all ilk+ platforms
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'cryptography', 'security', 'networking', 'architectures x86 arm risc-v powerpc mips csky s390 pa-risc c6x']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'cpu frequency scaling', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'cryptography hardware acceleration', 'pci', 'non-transparent bridge (ntb)', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'cxl (compute express link)', 'various']
|
['intel ']
|
['c']
| 1
| 1
| 11
|
-rebased on -tip --- diff --git a/drivers/gpu/drm/i915/display/intel_dp_hdcp.c b/drivers/gpu/drm/i915/display/intel_dp_hdcp.c --- a/drivers/gpu/drm/i915/display/intel_dp_hdcp.c +++ b/drivers/gpu/drm/i915/display/intel_dp_hdcp.c -static -bool intel_dp_mst_hdcp_check_link(struct intel_digital_port *dig_port, - struct intel_connector *connector) -{ - if (!intel_dp_hdcp_check_link(dig_port, connector)) - return false; - - return intel_dp_mst_get_qses_status(dig_port, connector); -} - - .check_link = intel_dp_mst_hdcp_check_link, + .check_link = intel_dp_hdcp_check_link,
|
Graphics
|
03b3a759c60b1d18c6119119be6672fd02d957ae
|
sean paul
|
drivers
|
gpu
|
display, drm, i915
|
drm/dp/mst: export drm_dp_get_vc_payload_bw()
|
this function will be needed by the next patch where the driver calculates the bw based on driver specific parameters, so export it.
|
this release allows to map an uid to a different one in a mount; it also adds support for selecting the preemption model at runtime; support for a low-overhead memory error detector designed to be used in production; support for the acrn hypervisor designed for embedded systems; btrfs initial support for zoned devices, subpage blocks sizes and performance improvements; support for eager nfs writes; support for a thermal power management to control the surface temperature of embedded devices in an unified way; the napi polling can be moved to a kernel thread; and support for non-blocking path lookups. as always, there are many other features, new drivers, improvements and fixes.
|
async flips for all ilk+ platforms
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'cryptography', 'security', 'networking', 'architectures x86 arm risc-v powerpc mips csky s390 pa-risc c6x']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'cpu frequency scaling', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'cryptography hardware acceleration', 'pci', 'non-transparent bridge (ntb)', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'cxl (compute express link)', 'various']
|
['intel ']
|
['h', 'c']
| 2
| 19
| 6
|
- fix function documentation. (lyude) --- diff --git a/drivers/gpu/drm/drm_dp_mst_topology.c b/drivers/gpu/drm/drm_dp_mst_topology.c --- a/drivers/gpu/drm/drm_dp_mst_topology.c +++ b/drivers/gpu/drm/drm_dp_mst_topology.c -static int drm_dp_get_vc_payload_bw(u8 dp_link_bw, u8 dp_link_count) +/** + * drm_dp_get_vc_payload_bw - get the vc payload bw for an mst link + * @link_rate: link rate in 10kbits/s units + * @link_lane_count: lane count + * + * calculate the total bandwidth of a multistream transport link. the returned + * value is in units of pbns/(timeslots/1 mtp). this value can be used to + * convert the number of pbns required for a given stream to the number of + * timeslots this stream requires in each mtp. + */ +int drm_dp_get_vc_payload_bw(int link_rate, int link_lane_count) - if (dp_link_bw == 0 || dp_link_count == 0) - drm_debug_kms("invalid link bandwidth in dpcd: %x (link count: %d) ", - dp_link_bw, dp_link_count); + if (link_rate == 0 || link_lane_count == 0) + drm_debug_kms("invalid link rate/lane count: (%d / %d) ", + link_rate, link_lane_count); - return dp_link_bw * dp_link_count / 2; + /* see dp v2.0 2.6.4.2, vcpayload_bandwidth_for_onetimeslotper_mtp_allocation */ + return link_rate * link_lane_count / 54000; +export_symbol(drm_dp_get_vc_payload_bw); - mgr->pbn_div = drm_dp_get_vc_payload_bw(mgr->dpcd[1], + mgr->pbn_div = drm_dp_get_vc_payload_bw(drm_dp_bw_code_to_link_rate(mgr->dpcd[1]), diff --git a/include/drm/drm_dp_mst_helper.h b/include/drm/drm_dp_mst_helper.h --- a/include/drm/drm_dp_mst_helper.h +++ b/include/drm/drm_dp_mst_helper.h +int drm_dp_get_vc_payload_bw(int link_rate, int link_lane_count);
|
Graphics
|
a321fc2b4e60fc1b39517d26c8104351636a6062
|
imre deak
|
drivers
|
gpu
|
drm
|
drm/i915: fix the mst pbn divider calculation
|
atm the driver will calculate a wrong mst timeslots/mtp (aka time unit) value for mst streams if the link parameters (link rate or lane count) are limited in a way independent of the sink capabilities (reported by dpcd).
|
this release allows to map an uid to a different one in a mount; it also adds support for selecting the preemption model at runtime; support for a low-overhead memory error detector designed to be used in production; support for the acrn hypervisor designed for embedded systems; btrfs initial support for zoned devices, subpage blocks sizes and performance improvements; support for eager nfs writes; support for a thermal power management to control the surface temperature of embedded devices in an unified way; the napi polling can be moved to a kernel thread; and support for non-blocking path lookups. as always, there are many other features, new drivers, improvements and fixes.
|
async flips for all ilk+ platforms
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'cryptography', 'security', 'networking', 'architectures x86 arm risc-v powerpc mips csky s390 pa-risc c6x']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'cpu frequency scaling', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'cryptography hardware acceleration', 'pci', 'non-transparent bridge (ntb)', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'cxl (compute express link)', 'various']
|
['intel ']
|
['c']
| 1
| 3
| 1
|
--- diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c b/drivers/gpu/drm/i915/display/intel_dp_mst.c --- a/drivers/gpu/drm/i915/display/intel_dp_mst.c +++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c - crtc_state->pbn, 0); + crtc_state->pbn, + drm_dp_get_vc_payload_bw(crtc_state->port_clock, + crtc_state->lane_count));
|
Graphics
|
b59c27cab257cfbff939615a87b72bce83925710
|
imre deak
|
drivers
|
gpu
|
display, drm, i915
|
drm/i915: nuke not needed members of dram_info
|
valid, ranks and bandwidth_kbps are set into dram_info but are not used anywhere else so nuking it.
|
this release allows to map an uid to a different one in a mount; it also adds support for selecting the preemption model at runtime; support for a low-overhead memory error detector designed to be used in production; support for the acrn hypervisor designed for embedded systems; btrfs initial support for zoned devices, subpage blocks sizes and performance improvements; support for eager nfs writes; support for a thermal power management to control the surface temperature of embedded devices in an unified way; the napi polling can be moved to a kernel thread; and support for non-blocking path lookups. as always, there are many other features, new drivers, improvements and fixes.
|
async flips for all ilk+ platforms
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'cryptography', 'security', 'networking', 'architectures x86 arm risc-v powerpc mips csky s390 pa-risc c6x']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'cpu frequency scaling', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'cryptography hardware acceleration', 'pci', 'non-transparent bridge (ntb)', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'cxl (compute express link)', 'various']
|
['intel ']
|
['h', 'c']
| 3
| 12
| 42
|
--- diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c --- a/drivers/gpu/drm/i915/i915_drv.c +++ b/drivers/gpu/drm/i915/i915_drv.c - * fill the dram structure to get the system raw bandwidth and - * dram info. this will be used for memory latency calculation. + * fill the dram structure to get the system dram info. this will be + * used for memory latency calculation. diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h - bool valid; - u8 ranks; - u32 bandwidth_kbps; diff --git a/drivers/gpu/drm/i915/intel_dram.c b/drivers/gpu/drm/i915/intel_dram.c --- a/drivers/gpu/drm/i915/intel_dram.c +++ b/drivers/gpu/drm/i915/intel_dram.c - /* - * if any of the channel is single rank channel, worst case output - * will be same as if single rank memory, so consider single rank - * memory. - */ - if (ch0.ranks == 1 || ch1.ranks == 1) - dram_info->ranks = 1; - else - dram_info->ranks = max(ch0.ranks, ch1.ranks); - - if (dram_info->ranks == 0) { + if (ch0.ranks == 0 && ch1.ranks == 0) { - dram_info->bandwidth_kbps = dram_info->num_channels * - mem_freq_khz * 8; - - if (dram_info->bandwidth_kbps == 0) { + if (dram_info->num_channels * mem_freq_khz == 0) { - dram_info->valid = true; - u8 num_active_channels; + u8 num_active_channels, valid_ranks = 0; - /* each active bit represents 4-byte channel */ - dram_info->bandwidth_kbps = (mem_freq_khz * num_active_channels * 4); - - if (dram_info->bandwidth_kbps == 0) { + if (mem_freq_khz * num_active_channels == 0) { - /* - * if any of the channel is single rank channel, - * worst case output will be same as if single rank - * memory, so consider single rank memory. - */ - if (dram_info->ranks == 0) - dram_info->ranks = dimm.ranks; - else if (dimm.ranks == 1) - dram_info->ranks = 1; + if (valid_ranks == 0) + valid_ranks = dimm.ranks; - if (dram_info->type == intel_dram_unknown || dram_info->ranks == 0) { + if (dram_info->type == intel_dram_unknown || valid_ranks == 0) { - dram_info->valid = true; - - drm_dbg_kms(&i915->drm, "dram bandwidth: %u kbps, channels: %u ", - dram_info->bandwidth_kbps, dram_info->num_channels); + drm_dbg_kms(&i915->drm, "dram channels: %u ", dram_info->num_channels); - drm_dbg_kms(&i915->drm, "dram ranks: %u, 16gb dimms: %s ", - dram_info->ranks, yesno(dram_info->is_16gb_dimm)); + drm_dbg_kms(&i915->drm, "dram 16gb dimms: %s ", + yesno(dram_info->is_16gb_dimm));
|
Graphics
|
f0b29707baa9e6f3d7b90090fcce62d2f1023fa1
|
jos roberto de souza lucas de marchi lucas demarchi intel com
|
drivers
|
gpu
|
drm, i915
|
drm/i915/gen11+: only load dram information from pcode
|
up to now we were reading some dram information from mchbar register and from pcode what is already not good but some gen12(tgl-h and adl-s) platforms have mchbar dram information in different offsets.
|
this release allows to map an uid to a different one in a mount; it also adds support for selecting the preemption model at runtime; support for a low-overhead memory error detector designed to be used in production; support for the acrn hypervisor designed for embedded systems; btrfs initial support for zoned devices, subpage blocks sizes and performance improvements; support for eager nfs writes; support for a thermal power management to control the surface temperature of embedded devices in an unified way; the napi polling can be moved to a kernel thread; and support for non-blocking path lookups. as always, there are many other features, new drivers, improvements and fixes.
|
async flips for all ilk+ platforms
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'cryptography', 'security', 'networking', 'architectures x86 arm risc-v powerpc mips csky s390 pa-risc c6x']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'cpu frequency scaling', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'cryptography hardware acceleration', 'pci', 'non-transparent bridge (ntb)', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'cxl (compute express link)', 'various']
|
['intel ']
|
['h', 'c']
| 4
| 93
| 75
|
- bring back num_points to intel_qgv_info as num_qgv_point can be - add gen12_get_dram_info() and simplify gen11_get_dram_info() --- diff --git a/drivers/gpu/drm/i915/display/intel_bw.c b/drivers/gpu/drm/i915/display/intel_bw.c --- a/drivers/gpu/drm/i915/display/intel_bw.c +++ b/drivers/gpu/drm/i915/display/intel_bw.c - u8 num_channels; - enum intel_dram_type dram_type; -static int icl_pcode_read_mem_global_info(struct drm_i915_private *dev_priv, - struct intel_qgv_info *qi) -{ - u32 val = 0; - int ret; - - ret = sandybridge_pcode_read(dev_priv, - icl_pcode_mem_subsysystem_info | - icl_pcode_mem_ss_read_global_info, - &val, null); - if (ret) - return ret; - - if (is_gen(dev_priv, 12)) { - switch (val & 0xf) { - case 0: - qi->dram_type = intel_dram_ddr4; - break; - case 3: - qi->dram_type = intel_dram_lpddr4; - break; - case 4: - qi->dram_type = intel_dram_ddr3; - break; - case 5: - qi->dram_type = intel_dram_lpddr3; - break; - default: - missing_case(val & 0xf); - break; - } - } else if (is_gen(dev_priv, 11)) { - switch (val & 0xf) { - case 0: - qi->dram_type = intel_dram_ddr4; - break; - case 1: - qi->dram_type = intel_dram_ddr3; - break; - case 2: - qi->dram_type = intel_dram_lpddr3; - break; - case 3: - qi->dram_type = intel_dram_lpddr4; - break; - default: - missing_case(val & 0xf); - break; - } - } else { - missing_case(intel_gen(dev_priv)); - qi->dram_type = intel_dram_lpddr3; /* conservative default */ - } - - qi->num_channels = (val & 0xf0) >> 4; - qi->num_points = (val & 0xf00) >> 8; - - if (is_gen(dev_priv, 12)) - qi->t_bl = qi->dram_type == intel_dram_ddr4 ? 4 : 16; - else if (is_gen(dev_priv, 11)) - qi->t_bl = qi->dram_type == intel_dram_ddr4 ? 4 : 8; - - return 0; -} - + const struct dram_info *dram_info = &dev_priv->dram_info; - ret = icl_pcode_read_mem_global_info(dev_priv, qi); - if (ret) - return ret; + qi->num_points = dram_info->num_qgv_points; + + if (is_gen(dev_priv, 12)) + qi->t_bl = dev_priv->dram_info.type == intel_dram_ddr4 ? 4 : 16; + else if (is_gen(dev_priv, 11)) + qi->t_bl = dev_priv->dram_info.type == intel_dram_ddr4 ? 4 : 8; - int num_channels; + int num_channels = dev_priv->dram_info.num_channels; - num_channels = qi.num_channels; diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c --- a/drivers/gpu/drm/i915/i915_drv.c +++ b/drivers/gpu/drm/i915/i915_drv.c + + intel_pcode_init(dev_priv); + - intel_pcode_init(dev_priv); - diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h + u8 num_qgv_points; diff --git a/drivers/gpu/drm/i915/intel_dram.c b/drivers/gpu/drm/i915/intel_dram.c --- a/drivers/gpu/drm/i915/intel_dram.c +++ b/drivers/gpu/drm/i915/intel_dram.c +#include "intel_sideband.h" +static int icl_pcode_read_mem_global_info(struct drm_i915_private *dev_priv) +{ + struct dram_info *dram_info = &dev_priv->dram_info; + u32 val = 0; + int ret; + + ret = sandybridge_pcode_read(dev_priv, + icl_pcode_mem_subsysystem_info | + icl_pcode_mem_ss_read_global_info, + &val, null); + if (ret) + return ret; + + if (is_gen(dev_priv, 12)) { + switch (val & 0xf) { + case 0: + dram_info->type = intel_dram_ddr4; + break; + case 3: + dram_info->type = intel_dram_lpddr4; + break; + case 4: + dram_info->type = intel_dram_ddr3; + break; + case 5: + dram_info->type = intel_dram_lpddr3; + break; + default: + missing_case(val & 0xf); + return -1; + } + } else { + switch (val & 0xf) { + case 0: + dram_info->type = intel_dram_ddr4; + break; + case 1: + dram_info->type = intel_dram_ddr3; + break; + case 2: + dram_info->type = intel_dram_lpddr3; + break; + case 3: + dram_info->type = intel_dram_lpddr4; + break; + default: + missing_case(val & 0xf); + return -1; + } + } + + dram_info->num_channels = (val & 0xf0) >> 4; + dram_info->num_qgv_points = (val & 0xf00) >> 8; + + return 0; +} + +static int gen11_get_dram_info(struct drm_i915_private *i915) +{ + int ret = skl_get_dram_info(i915); + + if (ret) + return ret; + + return icl_pcode_read_mem_global_info(i915); +} + +static int gen12_get_dram_info(struct drm_i915_private *i915) +{ + /* always needed for gen12+ */ + i915->dram_info.is_16gb_dimm = true; + + return icl_pcode_read_mem_global_info(i915); +} + - if (is_gen9_lp(i915)) + if (intel_gen(i915) >= 12) + ret = gen12_get_dram_info(i915); + else if (intel_gen(i915) >= 11) + ret = gen11_get_dram_info(i915); + else if (is_gen9_lp(i915))
|
Graphics
|
5d0c938ec9cc96fc7b8abcff0ca8b2a084e9c90c
|
jos roberto de souza
|
drivers
|
gpu
|
display, drm, i915
|
drm/i915: rename is_16gb_dimm to wm_lv_0_adjust_needed
|
as it now it is always required for gen12+ the is_16gb_dimm name do not make sense for gen12+.
|
this release allows to map an uid to a different one in a mount; it also adds support for selecting the preemption model at runtime; support for a low-overhead memory error detector designed to be used in production; support for the acrn hypervisor designed for embedded systems; btrfs initial support for zoned devices, subpage blocks sizes and performance improvements; support for eager nfs writes; support for a thermal power management to control the surface temperature of embedded devices in an unified way; the napi polling can be moved to a kernel thread; and support for non-blocking path lookups. as always, there are many other features, new drivers, improvements and fixes.
|
async flips for all ilk+ platforms
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'cryptography', 'security', 'networking', 'architectures x86 arm risc-v powerpc mips csky s390 pa-risc c6x']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'cpu frequency scaling', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'cryptography hardware acceleration', 'pci', 'non-transparent bridge (ntb)', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'cxl (compute express link)', 'various']
|
['intel ']
|
['h', 'c']
| 3
| 9
| 10
|
- updated comment on top of "dram_info->wm_lv_0_adjust_needed = --- diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h - bool is_16gb_dimm; + bool wm_lv_0_adjust_needed; diff --git a/drivers/gpu/drm/i915/intel_dram.c b/drivers/gpu/drm/i915/intel_dram.c --- a/drivers/gpu/drm/i915/intel_dram.c +++ b/drivers/gpu/drm/i915/intel_dram.c - dram_info->is_16gb_dimm = ch0.is_16gb_dimm || ch1.is_16gb_dimm; + dram_info->wm_lv_0_adjust_needed = ch0.is_16gb_dimm || ch1.is_16gb_dimm; - i915->dram_info.is_16gb_dimm = true; + i915->dram_info.wm_lv_0_adjust_needed = true; - * assume 16gb dimms are present until proven otherwise. - * this is only used for the level 0 watermark latency - * w/a which does not apply to bxt/glk. + * assume level 0 watermark latency adjustment is needed until proven + * otherwise, this w/a is not needed by bxt/glk. - dram_info->is_16gb_dimm = !is_gen9_lp(i915); + dram_info->wm_lv_0_adjust_needed = !is_gen9_lp(i915); - drm_dbg_kms(&i915->drm, "dram 16gb dimms: %s ", - yesno(dram_info->is_16gb_dimm)); + drm_dbg_kms(&i915->drm, "watermark level 0 adjustment needed: %s ", + yesno(dram_info->wm_lv_0_adjust_needed)); diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c --- a/drivers/gpu/drm/i915/intel_pm.c +++ b/drivers/gpu/drm/i915/intel_pm.c - if (dev_priv->dram_info.is_16gb_dimm) + if (dev_priv->dram_info.wm_lv_0_adjust_needed)
|
Graphics
|
66a245092baab799242aa3ca6c37325f7f5e4dfa
|
jos roberto de souza
|
drivers
|
gpu
|
drm, i915
|
drm/i915: limit plane stride to below tileoff.x limit
|
limit pre-skl plane stride to below 4k or 8k pixels (depending on the platform). we do this in order guarantee that tileoff/offset.x does not get too big.
|
this release allows to map an uid to a different one in a mount; it also adds support for selecting the preemption model at runtime; support for a low-overhead memory error detector designed to be used in production; support for the acrn hypervisor designed for embedded systems; btrfs initial support for zoned devices, subpage blocks sizes and performance improvements; support for eager nfs writes; support for a thermal power management to control the surface temperature of embedded devices in an unified way; the napi polling can be moved to a kernel thread; and support for non-blocking path lookups. as always, there are many other features, new drivers, improvements and fixes.
|
async flips for all ilk+ platforms
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'cryptography', 'security', 'networking', 'architectures x86 arm risc-v powerpc mips csky s390 pa-risc c6x']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'cpu frequency scaling', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'cryptography hardware acceleration', 'pci', 'non-transparent bridge (ntb)', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'cxl (compute express link)', 'various']
|
['intel ']
|
['h', 'c']
| 3
| 83
| 16
|
--- diff --git a/drivers/gpu/drm/i915/display/i9xx_plane.c b/drivers/gpu/drm/i915/display/i9xx_plane.c --- a/drivers/gpu/drm/i915/display/i9xx_plane.c +++ b/drivers/gpu/drm/i915/display/i9xx_plane.c +static unsigned int +hsw_primary_max_stride(struct intel_plane *plane, + u32 pixel_format, u64 modifier, + unsigned int rotation) +{ + const struct drm_format_info *info = drm_format_info(pixel_format); + int cpp = info->cpp[0]; + + /* limit to 8k pixels to guarantee offset.x doesn't get too big. */ + return min(8192 * cpp, 32 * 1024); +} + +static unsigned int +ilk_primary_max_stride(struct intel_plane *plane, + u32 pixel_format, u64 modifier, + unsigned int rotation) +{ + const struct drm_format_info *info = drm_format_info(pixel_format); + int cpp = info->cpp[0]; + + /* limit to 4k pixels to guarantee tileoff.x doesn't get too big. */ + if (modifier == i915_format_mod_x_tiled) + return min(4096 * cpp, 32 * 1024); + else + return 32 * 1024; +} + +i965_plane_max_stride(struct intel_plane *plane, + u32 pixel_format, u64 modifier, + unsigned int rotation) +{ + const struct drm_format_info *info = drm_format_info(pixel_format); + int cpp = info->cpp[0]; + + /* limit to 4k pixels to guarantee tileoff.x doesn't get too big. */ + if (modifier == i915_format_mod_x_tiled) + return min(4096 * cpp, 16 * 1024); + else + return 32 * 1024; +} + +static unsigned int - if (!has_gmch(dev_priv)) { - return 32*1024; - } else if (intel_gen(dev_priv) >= 4) { - if (modifier == i915_format_mod_x_tiled) - return 16*1024; - else - return 32*1024; - } else if (intel_gen(dev_priv) >= 3) { + if (intel_gen(dev_priv) >= 3) { - plane->max_stride = i9xx_plane_max_stride; + if (has_gmch(dev_priv)) { + if (intel_gen(dev_priv) >= 4) + plane->max_stride = i965_plane_max_stride; + else + plane->max_stride = i9xx_plane_max_stride; + } else { + if (is_broadwell(dev_priv) || is_haswell(dev_priv)) + plane->max_stride = hsw_primary_max_stride; + else + plane->max_stride = ilk_primary_max_stride; + } + diff --git a/drivers/gpu/drm/i915/display/i9xx_plane.h b/drivers/gpu/drm/i915/display/i9xx_plane.h --- a/drivers/gpu/drm/i915/display/i9xx_plane.h +++ b/drivers/gpu/drm/i915/display/i9xx_plane.h -unsigned int i9xx_plane_max_stride(struct intel_plane *plane, +unsigned int i965_plane_max_stride(struct intel_plane *plane, diff --git a/drivers/gpu/drm/i915/display/intel_sprite.c b/drivers/gpu/drm/i915/display/intel_sprite.c --- a/drivers/gpu/drm/i915/display/intel_sprite.c +++ b/drivers/gpu/drm/i915/display/intel_sprite.c - return 16384; + const struct drm_format_info *info = drm_format_info(pixel_format); + int cpp = info->cpp[0]; + + /* limit to 4k pixels to guarantee tileoff.x doesn't get too big. */ + if (modifier == i915_format_mod_x_tiled) + return min(4096 * cpp, 16 * 1024); + else + return 16 * 1024; +} + +static unsigned int +hsw_sprite_max_stride(struct intel_plane *plane, + u32 pixel_format, u64 modifier, + unsigned int rotation) +{ + const struct drm_format_info *info = drm_format_info(pixel_format); + int cpp = info->cpp[0]; + + /* limit to 8k pixels to guarantee offset.x doesn't get too big. */ + return min(8192 * cpp, 16 * 1024); - plane->max_stride = i9xx_plane_max_stride; + plane->max_stride = i965_plane_max_stride; - plane->max_stride = g4x_sprite_max_stride; - if (is_broadwell(dev_priv) || is_haswell(dev_priv)) + if (is_broadwell(dev_priv) || is_haswell(dev_priv)) { + plane->max_stride = hsw_sprite_max_stride; - else + } else { + plane->max_stride = g4x_sprite_max_stride; + } - plane->max_stride = g4x_sprite_max_stride; + plane->max_stride = g4x_sprite_max_stride;
|
Graphics
|
cb807055497c39bd657da9288ebdf07b81fc8d69
|
ville syrj l
|
drivers
|
gpu
|
display, drm, i915
|
drm/i915: implement async flips for bdw
|
implement async flip support for bdw. the implementation is similar to the skl+ code. and just like skl/bxt/glk bdw also needs the disable w/a, thus we need to plumb the desired state of the async flip all the way down to i9xx_plane_ctl_crtc().
|
this release allows to map an uid to a different one in a mount; it also adds support for selecting the preemption model at runtime; support for a low-overhead memory error detector designed to be used in production; support for the acrn hypervisor designed for embedded systems; btrfs initial support for zoned devices, subpage blocks sizes and performance improvements; support for eager nfs writes; support for a thermal power management to control the surface temperature of embedded devices in an unified way; the napi polling can be moved to a kernel thread; and support for non-blocking path lookups. as always, there are many other features, new drivers, improvements and fixes.
|
async flips for all ilk+ platforms
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'cryptography', 'security', 'networking', 'architectures x86 arm risc-v powerpc mips csky s390 pa-risc c6x']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'cpu frequency scaling', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'cryptography hardware acceleration', 'pci', 'non-transparent bridge (ntb)', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'cxl (compute express link)', 'various']
|
['intel ']
|
['h', 'c']
| 4
| 73
| 14
|
--- diff --git a/drivers/gpu/drm/i915/display/i9xx_plane.c b/drivers/gpu/drm/i915/display/i9xx_plane.c --- a/drivers/gpu/drm/i915/display/i9xx_plane.c +++ b/drivers/gpu/drm/i915/display/i9xx_plane.c +static void +g4x_primary_async_flip(struct intel_plane *plane, + const struct intel_crtc_state *crtc_state, + const struct intel_plane_state *plane_state, + bool async_flip) +{ + struct drm_i915_private *dev_priv = to_i915(plane->base.dev); + u32 dspcntr = plane_state->ctl | i9xx_plane_ctl_crtc(crtc_state); + u32 dspaddr_offset = plane_state->color_plane[0].offset; + enum i9xx_plane_id i9xx_plane = plane->i9xx_plane; + unsigned long irqflags; + + if (async_flip) + dspcntr |= dispplane_async_flip; + + spin_lock_irqsave(&dev_priv->uncore.lock, irqflags); + intel_de_write_fw(dev_priv, dspcntr(i9xx_plane), dspcntr); + intel_de_write_fw(dev_priv, dspsurf(i9xx_plane), + intel_plane_ggtt_offset(plane_state) + dspaddr_offset); + spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags); +} + +static void +bdw_primary_enable_flip_done(struct intel_plane *plane) +{ + struct drm_i915_private *i915 = to_i915(plane->base.dev); + enum pipe pipe = plane->pipe; + + spin_lock_irq(&i915->irq_lock); + bdw_enable_pipe_irq(i915, pipe, gen8_pipe_primary_flip_done); + spin_unlock_irq(&i915->irq_lock); +} + +static void +bdw_primary_disable_flip_done(struct intel_plane *plane) +{ + struct drm_i915_private *i915 = to_i915(plane->base.dev); + enum pipe pipe = plane->pipe; + + spin_lock_irq(&i915->irq_lock); + bdw_disable_pipe_irq(i915, pipe, gen8_pipe_primary_flip_done); + spin_unlock_irq(&i915->irq_lock); +} + + if (is_broadwell(dev_priv)) { + plane->need_async_flip_disable_wa = true; + plane->async_flip = g4x_primary_async_flip; + plane->enable_flip_done = bdw_primary_enable_flip_done; + plane->disable_flip_done = bdw_primary_disable_flip_done; + } + diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c --- a/drivers/gpu/drm/i915/display/intel_display.c +++ b/drivers/gpu/drm/i915/display/intel_display.c +static bool has_async_flips(struct drm_i915_private *i915) +{ + return intel_gen(i915) >= 9 || is_broadwell(i915); +} + - if (intel_gen(dev_priv) >= 9) + if (has_async_flips(dev_priv)) - if (intel_gen(i915) >= 9) - mode_config->async_page_flip = true; + mode_config->async_page_flip = has_async_flips(i915); diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c --- a/drivers/gpu/drm/i915/i915_irq.c +++ b/drivers/gpu/drm/i915/i915_irq.c +static u32 gen8_de_pipe_flip_done_mask(struct drm_i915_private *i915) +{ + if (intel_gen(i915) >= 9) + return gen9_pipe_plane1_flip_done; + else + return gen8_pipe_primary_flip_done; +} + - if (iir & gen9_pipe_plane1_flip_done) + if (iir & gen8_de_pipe_flip_done_mask(dev_priv)) - - u32 extra_ier = gen8_pipe_vblank | gen8_pipe_fifo_underrun; + u32 extra_ier = gen8_pipe_vblank | gen8_pipe_fifo_underrun | + gen8_de_pipe_flip_done_mask(dev_priv); - if (intel_gen(dev_priv) >= 9) - extra_ier |= gen9_pipe_plane1_flip_done; - - de_pipe_enables = de_pipe_masked | gen8_pipe_vblank | - gen8_pipe_fifo_underrun; - - if (intel_gen(dev_priv) >= 9) - de_pipe_enables |= gen9_pipe_plane1_flip_done; + de_pipe_enables = de_pipe_masked | + gen8_pipe_vblank | gen8_pipe_fifo_underrun | + gen8_de_pipe_flip_done_mask(dev_priv); diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h +#define dispplane_async_flip (1 << 9) /* g4x+ */
|
Graphics
|
cda195f13abd77fe024bbe1a2cb9ac99b9915270
|
ville syrj l
|
drivers
|
gpu
|
display, drm, i915
|
drm/i915: implement async flip for ivb/hsw
|
add support for async flips on ivb/hsw. unlike bdw+ we don't need any workarounds to disable async flips. apart from that the only real difference from the bdw implementation is the location of the flip_done interrupt bits.
|
this release allows to map an uid to a different one in a mount; it also adds support for selecting the preemption model at runtime; support for a low-overhead memory error detector designed to be used in production; support for the acrn hypervisor designed for embedded systems; btrfs initial support for zoned devices, subpage blocks sizes and performance improvements; support for eager nfs writes; support for a thermal power management to control the surface temperature of embedded devices in an unified way; the napi polling can be moved to a kernel thread; and support for non-blocking path lookups. as always, there are many other features, new drivers, improvements and fixes.
|
async flips for all ilk+ platforms
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'cryptography', 'security', 'networking', 'architectures x86 arm risc-v powerpc mips csky s390 pa-risc c6x']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'cpu frequency scaling', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'cryptography hardware acceleration', 'pci', 'non-transparent bridge (ntb)', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'cxl (compute express link)', 'various']
|
['intel ']
|
['c']
| 3
| 32
| 1
|
--- diff --git a/drivers/gpu/drm/i915/display/i9xx_plane.c b/drivers/gpu/drm/i915/display/i9xx_plane.c --- a/drivers/gpu/drm/i915/display/i9xx_plane.c +++ b/drivers/gpu/drm/i915/display/i9xx_plane.c +static void +ivb_primary_enable_flip_done(struct intel_plane *plane) +{ + struct drm_i915_private *i915 = to_i915(plane->base.dev); + + spin_lock_irq(&i915->irq_lock); + ilk_enable_display_irq(i915, de_plane_flip_done_ivb(plane->i9xx_plane)); + spin_unlock_irq(&i915->irq_lock); +} + +static void +ivb_primary_disable_flip_done(struct intel_plane *plane) +{ + struct drm_i915_private *i915 = to_i915(plane->base.dev); + + spin_lock_irq(&i915->irq_lock); + ilk_disable_display_irq(i915, de_plane_flip_done_ivb(plane->i9xx_plane)); + spin_unlock_irq(&i915->irq_lock); +} + + } else if (is_haswell(dev_priv) || is_ivybridge(dev_priv)) { + plane->async_flip = g4x_primary_async_flip; + plane->enable_flip_done = ivb_primary_enable_flip_done; + plane->disable_flip_done = ivb_primary_disable_flip_done; diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c --- a/drivers/gpu/drm/i915/display/intel_display.c +++ b/drivers/gpu/drm/i915/display/intel_display.c - return intel_gen(i915) >= 9 || is_broadwell(i915); + return intel_gen(i915) >= 9 || is_broadwell(i915) || + is_haswell(i915) || is_ivybridge(i915); diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c --- a/drivers/gpu/drm/i915/i915_irq.c +++ b/drivers/gpu/drm/i915/i915_irq.c + + if (de_iir & de_plane_flip_done_ivb(pipe)) + flip_done_handler(dev_priv, pipe); + de_plane_flip_done_ivb(plane_c) | + de_plane_flip_done_ivb(plane_b) | + de_plane_flip_done_ivb(plane_a) |
|
Graphics
|
2a636e240c77c81f11e17abf2de86fdad6c43f53
|
ville syrj l karthik b s karthik b s intel com
|
drivers
|
gpu
|
display, drm, i915
|
drm/i915: implement async flip for ilk/snb
|
add support for async flips on ivb/hsw. again no need for any workarounds and just have to deal with the interrupt bits being shuffled around a bit.
|
this release allows to map an uid to a different one in a mount; it also adds support for selecting the preemption model at runtime; support for a low-overhead memory error detector designed to be used in production; support for the acrn hypervisor designed for embedded systems; btrfs initial support for zoned devices, subpage blocks sizes and performance improvements; support for eager nfs writes; support for a thermal power management to control the surface temperature of embedded devices in an unified way; the napi polling can be moved to a kernel thread; and support for non-blocking path lookups. as always, there are many other features, new drivers, improvements and fixes.
|
async flips for all ilk+ platforms
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'cryptography', 'security', 'networking', 'architectures x86 arm risc-v powerpc mips csky s390 pa-risc c6x']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'cpu frequency scaling', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'cryptography hardware acceleration', 'pci', 'non-transparent bridge (ntb)', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'cxl (compute express link)', 'various']
|
['intel ']
|
['c']
| 3
| 31
| 1
|
--- diff --git a/drivers/gpu/drm/i915/display/i9xx_plane.c b/drivers/gpu/drm/i915/display/i9xx_plane.c --- a/drivers/gpu/drm/i915/display/i9xx_plane.c +++ b/drivers/gpu/drm/i915/display/i9xx_plane.c +static void +ilk_primary_enable_flip_done(struct intel_plane *plane) +{ + struct drm_i915_private *i915 = to_i915(plane->base.dev); + + spin_lock_irq(&i915->irq_lock); + ilk_enable_display_irq(i915, de_plane_flip_done(plane->i9xx_plane)); + spin_unlock_irq(&i915->irq_lock); +} + +static void +ilk_primary_disable_flip_done(struct intel_plane *plane) +{ + struct drm_i915_private *i915 = to_i915(plane->base.dev); + + spin_lock_irq(&i915->irq_lock); + ilk_disable_display_irq(i915, de_plane_flip_done(plane->i9xx_plane)); + spin_unlock_irq(&i915->irq_lock); +} + + } else if (is_gen_range(dev_priv, 5, 6)) { + plane->async_flip = g4x_primary_async_flip; + plane->enable_flip_done = ilk_primary_enable_flip_done; + plane->disable_flip_done = ilk_primary_disable_flip_done; diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c --- a/drivers/gpu/drm/i915/display/intel_display.c +++ b/drivers/gpu/drm/i915/display/intel_display.c - is_haswell(i915) || is_ivybridge(i915); + is_haswell(i915) || is_ivybridge(i915) || + is_gen_range(i915, 5, 6); diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c --- a/drivers/gpu/drm/i915/i915_irq.c +++ b/drivers/gpu/drm/i915/i915_irq.c + if (de_iir & de_plane_flip_done(pipe)) + flip_done_handler(dev_priv, pipe); + + de_plane_flip_done(plane_a) | + de_plane_flip_done(plane_b) |
|
Graphics
|
4bb18054adc4939a3c1f895d8d0a1556a5f8b26a
|
ville syrj l karthik b s karthik b s intel com
|
drivers
|
gpu
|
display, drm, i915
|
drm/i915: implement async flips for vlv/chv
|
add support for async flips on vlv/chv. unlike all the other platforms vlv/chv do not use the async flip bit in dspcntr and instead we select between async vs. sync flips based on the surface address register. the normal dspsurf generates sync flips dspaddr_vlv generates async flips. and as usual the interrupt bits are different from the other platforms.
|
this release allows to map an uid to a different one in a mount; it also adds support for selecting the preemption model at runtime; support for a low-overhead memory error detector designed to be used in production; support for the acrn hypervisor designed for embedded systems; btrfs initial support for zoned devices, subpage blocks sizes and performance improvements; support for eager nfs writes; support for a thermal power management to control the surface temperature of embedded devices in an unified way; the napi polling can be moved to a kernel thread; and support for non-blocking path lookups. as always, there are many other features, new drivers, improvements and fixes.
|
async flips for all ilk+ platforms
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'cryptography', 'security', 'networking', 'architectures x86 arm risc-v powerpc mips csky s390 pa-risc c6x']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'cpu frequency scaling', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'cryptography hardware acceleration', 'pci', 'non-transparent bridge (ntb)', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'cxl (compute express link)', 'various']
|
['intel ']
|
['h', 'c']
| 4
| 52
| 6
|
--- diff --git a/drivers/gpu/drm/i915/display/i9xx_plane.c b/drivers/gpu/drm/i915/display/i9xx_plane.c --- a/drivers/gpu/drm/i915/display/i9xx_plane.c +++ b/drivers/gpu/drm/i915/display/i9xx_plane.c +static void +vlv_primary_async_flip(struct intel_plane *plane, + const struct intel_crtc_state *crtc_state, + const struct intel_plane_state *plane_state, + bool async_flip) +{ + struct drm_i915_private *dev_priv = to_i915(plane->base.dev); + u32 dspaddr_offset = plane_state->color_plane[0].offset; + enum i9xx_plane_id i9xx_plane = plane->i9xx_plane; + unsigned long irqflags; + + spin_lock_irqsave(&dev_priv->uncore.lock, irqflags); + intel_de_write_fw(dev_priv, dspaddr_vlv(i9xx_plane), + intel_plane_ggtt_offset(plane_state) + dspaddr_offset); + spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags); +} + +static void +vlv_primary_enable_flip_done(struct intel_plane *plane) +{ + struct drm_i915_private *i915 = to_i915(plane->base.dev); + enum pipe pipe = plane->pipe; + + spin_lock_irq(&i915->irq_lock); + i915_enable_pipestat(i915, pipe, plane_flip_done_int_status_vlv); + spin_unlock_irq(&i915->irq_lock); +} + +static void +vlv_primary_disable_flip_done(struct intel_plane *plane) +{ + struct drm_i915_private *i915 = to_i915(plane->base.dev); + enum pipe pipe = plane->pipe; + + spin_lock_irq(&i915->irq_lock); + i915_disable_pipestat(i915, pipe, plane_flip_done_int_status_vlv); + spin_unlock_irq(&i915->irq_lock); +} + - if (is_broadwell(dev_priv)) { + if (is_valleyview(dev_priv) || is_cherryview(dev_priv)) { + plane->async_flip = vlv_primary_async_flip; + plane->enable_flip_done = vlv_primary_enable_flip_done; + plane->disable_flip_done = vlv_primary_disable_flip_done; + } else if (is_broadwell(dev_priv)) { - } else if (is_haswell(dev_priv) || is_ivybridge(dev_priv)) { + } else if (intel_gen(dev_priv) >= 7) { - } else if (is_gen_range(dev_priv, 5, 6)) { + } else if (intel_gen(dev_priv) >= 5) { diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c --- a/drivers/gpu/drm/i915/display/intel_display.c +++ b/drivers/gpu/drm/i915/display/intel_display.c - return intel_gen(i915) >= 9 || is_broadwell(i915) || - is_haswell(i915) || is_ivybridge(i915) || - is_gen_range(i915, 5, 6); + return intel_gen(i915) >= 5; diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c --- a/drivers/gpu/drm/i915/i915_irq.c +++ b/drivers/gpu/drm/i915/i915_irq.c + if (pipe_stats[pipe] & plane_flip_done_int_status_vlv) + flip_done_handler(dev_priv, pipe); + diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h +#define _dspaaddr_vlv 0x7017c /* vlv/chv */ +#define dspaddr_vlv(plane) _mmio_pipe2(plane, _dspaaddr_vlv)
|
Graphics
|
6ede6b0616b23611560ec9dc4053ae35651810d2
|
ville syrj l karthik b s karthik b s intel com
|
drivers
|
gpu
|
display, drm, i915
|
drm/edid: add additional hfvsdb fields for hdmi2.1
|
the hdmi2.1 extends hfvsdb (hdmi forum vendor specific data block) to have fields related to newly defined methods of frl (fixed rate link) levels, number of lanes supported, dsc color bit depth, vrr min/max, fva (fast vactive), allm etc.
|
this release allows to map an uid to a different one in a mount; it also adds support for selecting the preemption model at runtime; support for a low-overhead memory error detector designed to be used in production; support for the acrn hypervisor designed for embedded systems; btrfs initial support for zoned devices, subpage blocks sizes and performance improvements; support for eager nfs writes; support for a thermal power management to control the surface temperature of embedded devices in an unified way; the napi polling can be moved to a kernel thread; and support for non-blocking path lookups. as always, there are many other features, new drivers, improvements and fixes.
|
add support for dp-hdmi2.1 pcon
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'cryptography', 'security', 'networking', 'architectures x86 arm risc-v powerpc mips csky s390 pa-risc c6x']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'cpu frequency scaling', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'cryptography hardware acceleration', 'pci', 'non-transparent bridge (ntb)', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'cxl (compute express link)', 'various']
|
['intel ']
|
['h']
| 1
| 30
| 0
|
--- diff --git a/include/drm/drm_edid.h b/include/drm/drm_edid.h --- a/include/drm/drm_edid.h +++ b/include/drm/drm_edid.h +/* hdmi 2.1 additional fields */ +#define drm_edid_max_frl_rate_mask 0xf0 +#define drm_edid_fapa_start_location (1 << 0) +#define drm_edid_allm (1 << 1) +#define drm_edid_fva (1 << 2) + +/* deep color specific */ +#define drm_edid_dc_30bit_420 (1 << 0) +#define drm_edid_dc_36bit_420 (1 << 1) +#define drm_edid_dc_48bit_420 (1 << 2) + +/* vrr specific */ +#define drm_edid_cnmvrr (1 << 3) +#define drm_edid_cinema_vrr (1 << 4) +#define drm_edid_mdelta (1 << 5) +#define drm_edid_vrr_max_upper_mask 0xc0 +#define drm_edid_vrr_max_lower_mask 0xff +#define drm_edid_vrr_min_mask 0x3f + +/* dsc specific */ +#define drm_edid_dsc_10bpc (1 << 0) +#define drm_edid_dsc_12bpc (1 << 1) +#define drm_edid_dsc_16bpc (1 << 2) +#define drm_edid_dsc_all_bpp (1 << 3) +#define drm_edid_dsc_native_420 (1 << 6) +#define drm_edid_dsc_1p2 (1 << 7) +#define drm_edid_dsc_max_frl_rate_mask 0xf0 +#define drm_edid_dsc_max_slices 0xf +#define drm_edid_dsc_total_chunk_kbytes 0x3f +
|
Graphics
|
9bb85a6e29de5f9e1194c918dbfafbb3fcbbb157
|
swati sharma
|
include
|
drm
| |
drm/edid: parse max_frl field from hfvsdb block
|
this patch parses max_frl field to get the max rate in gbps that the hdmi 2.1 panel can support in frl mode. source need this field to determine the optimal rate between the source and sink during frl training.
|
this release allows to map an uid to a different one in a mount; it also adds support for selecting the preemption model at runtime; support for a low-overhead memory error detector designed to be used in production; support for the acrn hypervisor designed for embedded systems; btrfs initial support for zoned devices, subpage blocks sizes and performance improvements; support for eager nfs writes; support for a thermal power management to control the surface temperature of embedded devices in an unified way; the napi polling can be moved to a kernel thread; and support for non-blocking path lookups. as always, there are many other features, new drivers, improvements and fixes.
|
add support for dp-hdmi2.1 pcon
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'cryptography', 'security', 'networking', 'architectures x86 arm risc-v powerpc mips csky s390 pa-risc c6x']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'cpu frequency scaling', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'cryptography hardware acceleration', 'pci', 'non-transparent bridge (ntb)', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'cxl (compute express link)', 'various']
|
['intel ']
|
['h', 'c']
| 2
| 50
| 0
|
--- diff --git a/drivers/gpu/drm/drm_edid.c b/drivers/gpu/drm/drm_edid.c --- a/drivers/gpu/drm/drm_edid.c +++ b/drivers/gpu/drm/drm_edid.c +static +void drm_get_max_frl_rate(int max_frl_rate, u8 *max_lanes, u8 *max_rate_per_lane) +{ + switch (max_frl_rate) { + case 1: + *max_lanes = 3; + *max_rate_per_lane = 3; + break; + case 2: + *max_lanes = 3; + *max_rate_per_lane = 6; + break; + case 3: + *max_lanes = 4; + *max_rate_per_lane = 6; + break; + case 4: + *max_lanes = 4; + *max_rate_per_lane = 8; + break; + case 5: + *max_lanes = 4; + *max_rate_per_lane = 10; + break; + case 6: + *max_lanes = 4; + *max_rate_per_lane = 12; + break; + case 0: + default: + *max_lanes = 0; + *max_rate_per_lane = 0; + } +} + + if (hf_vsdb[7]) { + u8 max_frl_rate; + + drm_debug_kms("hdmi_21 sink detected. parsing edid "); + max_frl_rate = (hf_vsdb[7] & drm_edid_max_frl_rate_mask) >> 4; + drm_get_max_frl_rate(max_frl_rate, &hdmi->max_lanes, + &hdmi->max_frl_rate_per_lane); + } + diff --git a/include/drm/drm_connector.h b/include/drm/drm_connector.h --- a/include/drm/drm_connector.h +++ b/include/drm/drm_connector.h + + /** @max_frl_rate_per_lane: support fixed rate link */ + u8 max_frl_rate_per_lane; + + /** @max_lanes: supported by sink */ + u8 max_lanes;
|
Graphics
|
4499d488f6eeb1f1d6a5c10c0c96361c02bb5145
|
swati sharma
|
drivers
|
gpu
|
drm
|
drm/edid: parse dsc1.2 cap fields from hfvsdb block
|
this patch parses hfvsdb fields for dsc1.2 capabilities of an hdmi2.1 sink. these fields are required by a source to understand the dsc capability of the sink, to set appropriate pps parameters, before transmitting compressed data stream.
|
this release allows to map an uid to a different one in a mount; it also adds support for selecting the preemption model at runtime; support for a low-overhead memory error detector designed to be used in production; support for the acrn hypervisor designed for embedded systems; btrfs initial support for zoned devices, subpage blocks sizes and performance improvements; support for eager nfs writes; support for a thermal power management to control the surface temperature of embedded devices in an unified way; the napi polling can be moved to a kernel thread; and support for non-blocking path lookups. as always, there are many other features, new drivers, improvements and fixes.
|
add support for dp-hdmi2.1 pcon
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'cryptography', 'security', 'networking', 'architectures x86 arm risc-v powerpc mips csky s390 pa-risc c6x']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'cpu frequency scaling', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'cryptography hardware acceleration', 'pci', 'non-transparent bridge (ntb)', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'cxl (compute express link)', 'various']
|
['intel ']
|
['h', 'c']
| 2
| 102
| 0
|
-added a new struct for hdmi dsc cap -fixed bugs in macros usage. --- diff --git a/drivers/gpu/drm/drm_edid.c b/drivers/gpu/drm/drm_edid.c --- a/drivers/gpu/drm/drm_edid.c +++ b/drivers/gpu/drm/drm_edid.c + u8 dsc_max_frl_rate; + u8 dsc_max_slices; + struct drm_hdmi_dsc_cap *hdmi_dsc = &hdmi->dsc_cap; + hdmi_dsc->v_1p2 = hf_vsdb[11] & drm_edid_dsc_1p2; + + if (hdmi_dsc->v_1p2) { + hdmi_dsc->native_420 = hf_vsdb[11] & drm_edid_dsc_native_420; + hdmi_dsc->all_bpp = hf_vsdb[11] & drm_edid_dsc_all_bpp; + + if (hf_vsdb[11] & drm_edid_dsc_16bpc) + hdmi_dsc->bpc_supported = 16; + else if (hf_vsdb[11] & drm_edid_dsc_12bpc) + hdmi_dsc->bpc_supported = 12; + else if (hf_vsdb[11] & drm_edid_dsc_10bpc) + hdmi_dsc->bpc_supported = 10; + else + hdmi_dsc->bpc_supported = 0; + + dsc_max_frl_rate = (hf_vsdb[12] & drm_edid_dsc_max_frl_rate_mask) >> 4; + drm_get_max_frl_rate(dsc_max_frl_rate, &hdmi_dsc->max_lanes, + &hdmi_dsc->max_frl_rate_per_lane); + hdmi_dsc->total_chunk_kbytes = hf_vsdb[13] & drm_edid_dsc_total_chunk_kbytes; + + dsc_max_slices = hf_vsdb[12] & drm_edid_dsc_max_slices; + switch (dsc_max_slices) { + case 1: + hdmi_dsc->max_slices = 1; + hdmi_dsc->clk_per_slice = 340; + break; + case 2: + hdmi_dsc->max_slices = 2; + hdmi_dsc->clk_per_slice = 340; + break; + case 3: + hdmi_dsc->max_slices = 4; + hdmi_dsc->clk_per_slice = 340; + break; + case 4: + hdmi_dsc->max_slices = 8; + hdmi_dsc->clk_per_slice = 340; + break; + case 5: + hdmi_dsc->max_slices = 8; + hdmi_dsc->clk_per_slice = 400; + break; + case 6: + hdmi_dsc->max_slices = 12; + hdmi_dsc->clk_per_slice = 400; + break; + case 7: + hdmi_dsc->max_slices = 16; + hdmi_dsc->clk_per_slice = 400; + break; + case 0: + default: + hdmi_dsc->max_slices = 0; + hdmi_dsc->clk_per_slice = 0; + } + } diff --git a/include/drm/drm_connector.h b/include/drm/drm_connector.h --- a/include/drm/drm_connector.h +++ b/include/drm/drm_connector.h +/** + * struct drm_hdmi_dsc_cap - dsc capabilities of hdmi sink + * + * describes the dsc support provided by hdmi 2.1 sink. + * the information is fetched fom additional hfvsdb blocks defined + * for hdmi 2.1. + */ +struct drm_hdmi_dsc_cap { + /** @v_1p2: flag for dsc1.2 version support by sink */ + bool v_1p2; + + /** @native_420: does sink support dsc with 4:2:0 compression */ + bool native_420; + + /** + * @all_bpp: does sink support all bpp with 4:4:4: or 4:2:2 + * compressed formats + */ + bool all_bpp; + + /** + * @bpc_supported: compressed bpc supported by sink : 10, 12 or 16 bpc + */ + u8 bpc_supported; + + /** @max_slices: maximum number of horizontal slices supported by */ + u8 max_slices; + + /** @clk_per_slice : max pixel clock in mhz supported per slice */ + int clk_per_slice; + + /** @max_lanes : dsc max lanes supported for fixed rate link training */ + u8 max_lanes; + + /** @max_frl_rate_per_lane : maximum frl rate with dsc per lane */ + u8 max_frl_rate_per_lane; + + /** @total_chunk_kbytes: max size of chunks in kbs supported per line*/ + u8 total_chunk_kbytes; +}; + + /** @dsc_cap: dsc capabilities of the sink */ + struct drm_hdmi_dsc_cap dsc_cap;
|
Graphics
|
76ee7b905678f415b49af9c2d4932844db8f01cd
|
ankit nautiyal
|
drivers
|
gpu
|
drm
|
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