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912
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|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
drm/amdgpu: enable freesync for a+a configs
|
some newer apus can scanout directly from gtt, that saves us from allocating another bounce buffer in vram and enables freesync in such configurations.
|
this release allows to map an uid to a different one in a mount; it also adds support for selecting the preemption model at runtime; support for a low-overhead memory error detector designed to be used in production; support for the acrn hypervisor designed for embedded systems; btrfs initial support for zoned devices, subpage blocks sizes and performance improvements; support for eager nfs writes; support for a thermal power management to control the surface temperature of embedded devices in an unified way; the napi polling can be moved to a kernel thread; and support for non-blocking path lookups. as always, there are many other features, new drivers, improvements and fixes.
|
enable freesync for a+a configs
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'cryptography', 'security', 'networking', 'architectures x86 arm risc-v powerpc mips csky s390 pa-risc c6x']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'cpu frequency scaling', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'cryptography hardware acceleration', 'pci', 'non-transparent bridge (ntb)', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'cxl (compute express link)', 'various']
|
['amdgpu ']
|
['c']
| 2
| 7
| 3
|
--- diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c - struct drm_gem_object *obj; + struct drm_gem_object *obj; + struct amdgpu_bo *bo; + uint32_t domains; - if (obj->import_attach) { + bo = gem_to_amdgpu_bo(obj); + domains = amdgpu_display_supported_domains(drm_to_adev(dev), bo->flags); + if (obj->import_attach && !(domains & amdgpu_gem_domain_gtt)) { diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c - if (bo->prime_shared_count) { + if (bo->prime_shared_count || bo->tbo.base.import_attach) {
|
Graphics
|
dd017d01c3d96e48abd6fe6ccce4ef977fb5e10b
|
christian k nig
|
drivers
|
gpu
|
amd, amdgpu, drm
|
drm/amd/pm: populate sienna cichlid default overdrive table settings
|
populate the bootup overdrive table settings.
|
this release allows to map an uid to a different one in a mount; it also adds support for selecting the preemption model at runtime; support for a low-overhead memory error detector designed to be used in production; support for the acrn hypervisor designed for embedded systems; btrfs initial support for zoned devices, subpage blocks sizes and performance improvements; support for eager nfs writes; support for a thermal power management to control the surface temperature of embedded devices in an unified way; the napi polling can be moved to a kernel thread; and support for non-blocking path lookups. as always, there are many other features, new drivers, improvements and fixes.
|
sienna cichild overdrive support
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'cryptography', 'security', 'networking', 'architectures x86 arm risc-v powerpc mips csky s390 pa-risc c6x']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'cpu frequency scaling', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'cryptography hardware acceleration', 'pci', 'non-transparent bridge (ntb)', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'cxl (compute express link)', 'various']
|
['amdgpu ']
|
['c']
| 1
| 38
| 0
|
--- diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c --- a/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c +++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c + /* + * instead of having its own buffer space and get overdrive_table copied, + * smu->od_settings just points to the actual overdrive_table + */ + smu->od_settings = &powerplay_table->overdrive_table; + +static void sienna_cichlid_dump_od_table(struct smu_context *smu, + overdrivetable_t *od_table) +{ + dev_dbg(smu->adev->dev, "od: gfxclk: (%d, %d) ", od_table->gfxclkfmin, + od_table->gfxclkfmax); + dev_dbg(smu->adev->dev, "od: uclk: (%d, %d) ", od_table->uclkfmin, + od_table->uclkfmax); +} + +static int sienna_cichlid_set_default_od_settings(struct smu_context *smu) +{ + overdrivetable_t *od_table = + (overdrivetable_t *)smu->smu_table.overdrive_table; + overdrivetable_t *boot_od_table = + (overdrivetable_t *)smu->smu_table.boot_overdrive_table; + int ret = 0; + + ret = smu_cmn_update_table(smu, smu_table_overdrive, + 0, (void *)od_table, false); + if (ret) { + dev_err(smu->adev->dev, "failed to get overdrive table! "); + return ret; + } + + memcpy(boot_od_table, od_table, sizeof(overdrivetable_t)); + + sienna_cichlid_dump_od_table(smu, od_table); + + return 0; +} + + .set_default_od_settings = sienna_cichlid_set_default_od_settings,
|
Graphics
|
aa75fa34e04c842d93a45087adac66ab3a2a7f33
|
evan quan alex deucher alexander deucher amd com
|
drivers
|
gpu
|
amd, drm, pm, smu11, swsmu
|
drm/amd/pm: enable sienna cichlid overdrive support
|
enable sienna cichlid gfxclk/uclk overdrive support.
|
this release allows to map an uid to a different one in a mount; it also adds support for selecting the preemption model at runtime; support for a low-overhead memory error detector designed to be used in production; support for the acrn hypervisor designed for embedded systems; btrfs initial support for zoned devices, subpage blocks sizes and performance improvements; support for eager nfs writes; support for a thermal power management to control the surface temperature of embedded devices in an unified way; the napi polling can be moved to a kernel thread; and support for non-blocking path lookups. as always, there are many other features, new drivers, improvements and fixes.
|
sienna cichild overdrive support
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'cryptography', 'security', 'networking', 'architectures x86 arm risc-v powerpc mips csky s390 pa-risc c6x']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'cpu frequency scaling', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'cryptography hardware acceleration', 'pci', 'non-transparent bridge (ntb)', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'cxl (compute express link)', 'various']
|
['amdgpu ']
|
['c']
| 2
| 243
| 1
|
--- diff --git a/drivers/gpu/drm/amd/pm/amdgpu_pm.c b/drivers/gpu/drm/amd/pm/amdgpu_pm.c --- a/drivers/gpu/drm/amd/pm/amdgpu_pm.c +++ b/drivers/gpu/drm/amd/pm/amdgpu_pm.c - * - maximum memory clock labeled od_mclk + * - minimum(not available for vega20 and navi1x) and maximum memory + * clock labeled od_mclk diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c --- a/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c +++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c +static bool sienna_cichlid_is_od_feature_supported(struct smu_11_0_7_overdrive_table *od_table, + enum smu_11_0_7_odfeature_cap cap) +{ + return od_table->cap[cap]; +} + +static void sienna_cichlid_get_od_setting_range(struct smu_11_0_7_overdrive_table *od_table, + enum smu_11_0_7_odsetting_id setting, + uint32_t *min, uint32_t *max) +{ + if (min) + *min = od_table->min[setting]; + if (max) + *max = od_table->max[setting]; +} + + struct smu_11_0_7_overdrive_table *od_settings = smu->od_settings; + overdrivetable_t *od_table = + (overdrivetable_t *)table_context->overdrive_table; + uint32_t min_value, max_value; + case smu_od_sclk: + if (!smu->od_enabled || !od_table || !od_settings) + break; + + if (!sienna_cichlid_is_od_feature_supported(od_settings, smu_11_0_7_odcap_gfxclk_limits)) + break; + + size += sprintf(buf + size, "od_sclk: "); + size += sprintf(buf + size, "0: %umhz 1: %umhz ", od_table->gfxclkfmin, od_table->gfxclkfmax); + break; + + case smu_od_mclk: + if (!smu->od_enabled || !od_table || !od_settings) + break; + + if (!sienna_cichlid_is_od_feature_supported(od_settings, smu_11_0_7_odcap_uclk_limits)) + break; + + size += sprintf(buf + size, "od_mclk: "); + size += sprintf(buf + size, "0: %umhz 1: %umhz ", od_table->uclkfmin, od_table->uclkfmax); + break; + + case smu_od_range: + if (!smu->od_enabled || !od_table || !od_settings) + break; + + size = sprintf(buf, "%s: ", "od_range"); + + if (sienna_cichlid_is_od_feature_supported(od_settings, smu_11_0_7_odcap_gfxclk_limits)) { + sienna_cichlid_get_od_setting_range(od_settings, smu_11_0_7_odsetting_gfxclkfmin, + &min_value, null); + sienna_cichlid_get_od_setting_range(od_settings, smu_11_0_7_odsetting_gfxclkfmax, + null, &max_value); + size += sprintf(buf + size, "sclk: %7umhz %10umhz ", + min_value, max_value); + } + + if (sienna_cichlid_is_od_feature_supported(od_settings, smu_11_0_7_odcap_uclk_limits)) { + sienna_cichlid_get_od_setting_range(od_settings, smu_11_0_7_odsetting_uclkfmin, + &min_value, null); + sienna_cichlid_get_od_setting_range(od_settings, smu_11_0_7_odsetting_uclkfmax, + null, &max_value); + size += sprintf(buf + size, "mclk: %7umhz %10umhz ", + min_value, max_value); + } + break; + +static int sienna_cichlid_od_setting_check_range(struct smu_context *smu, + struct smu_11_0_7_overdrive_table *od_table, + enum smu_11_0_7_odsetting_id setting, + uint32_t value) +{ + if (value < od_table->min[setting]) { + dev_warn(smu->adev->dev, "od setting (%d, %d) is less than the minimum allowed (%d) ", + setting, value, od_table->min[setting]); + return -einval; + } + if (value > od_table->max[setting]) { + dev_warn(smu->adev->dev, "od setting (%d, %d) is greater than the maximum allowed (%d) ", + setting, value, od_table->max[setting]); + return -einval; + } + + return 0; +} + +static int sienna_cichlid_od_edit_dpm_table(struct smu_context *smu, + enum pp_od_dpm_table_command type, + long input[], uint32_t size) +{ + struct smu_table_context *table_context = &smu->smu_table; + overdrivetable_t *od_table = + (overdrivetable_t *)table_context->overdrive_table; + struct smu_11_0_7_overdrive_table *od_settings = + (struct smu_11_0_7_overdrive_table *)smu->od_settings; + enum smu_11_0_7_odsetting_id freq_setting; + uint16_t *freq_ptr; + int i, ret = 0; + + if (!smu->od_enabled) { + dev_warn(smu->adev->dev, "overdrive is not enabled! "); + return -einval; + } + + if (!smu->od_settings) { + dev_err(smu->adev->dev, "od board limits are not set! "); + return -enoent; + } + + if (!(table_context->overdrive_table && table_context->boot_overdrive_table)) { + dev_err(smu->adev->dev, "overdrive table was not initialized! "); + return -einval; + } + + switch (type) { + case pp_od_edit_sclk_vddc_table: + if (!sienna_cichlid_is_od_feature_supported(od_settings, + smu_11_0_7_odcap_gfxclk_limits)) { + dev_warn(smu->adev->dev, "gfxclk_limits not supported! "); + return -enotsupp; + } + + for (i = 0; i < size; i += 2) { + if (i + 2 > size) { + dev_info(smu->adev->dev, "invalid number of input parameters %d ", size); + return -einval; + } + + switch (input[i]) { + case 0: + if (input[i + 1] > od_table->gfxclkfmax) { + dev_info(smu->adev->dev, "gfxclkfmin (%ld) must be <= gfxclkfmax (%u)! ", + input[i + 1], od_table->gfxclkfmax); + return -einval; + } + + freq_setting = smu_11_0_7_odsetting_gfxclkfmin; + freq_ptr = &od_table->gfxclkfmin; + break; + + case 1: + if (input[i + 1] < od_table->gfxclkfmin) { + dev_info(smu->adev->dev, "gfxclkfmax (%ld) must be >= gfxclkfmin (%u)! ", + input[i + 1], od_table->gfxclkfmin); + return -einval; + } + + freq_setting = smu_11_0_7_odsetting_gfxclkfmax; + freq_ptr = &od_table->gfxclkfmax; + break; + + default: + dev_info(smu->adev->dev, "invalid sclk_vddc_table index: %ld ", input[i]); + dev_info(smu->adev->dev, "supported indices: [0:min,1:max] "); + return -einval; + } + + ret = sienna_cichlid_od_setting_check_range(smu, od_settings, + freq_setting, input[i + 1]); + if (ret) + return ret; + + *freq_ptr = (uint16_t)input[i + 1]; + } + break; + + case pp_od_edit_mclk_vddc_table: + if (!sienna_cichlid_is_od_feature_supported(od_settings, smu_11_0_7_odcap_uclk_limits)) { + dev_warn(smu->adev->dev, "uclk_limits not supported! "); + return -enotsupp; + } + + for (i = 0; i < size; i += 2) { + if (i + 2 > size) { + dev_info(smu->adev->dev, "invalid number of input parameters %d ", size); + return -einval; + } + + switch (input[i]) { + case 0: + if (input[i + 1] > od_table->uclkfmax) { + dev_info(smu->adev->dev, "uclkfmin (%ld) must be <= uclkfmax (%u)! ", + input[i + 1], od_table->uclkfmax); + return -einval; + } + + freq_setting = smu_11_0_7_odsetting_uclkfmin; + freq_ptr = &od_table->uclkfmin; + break; + + case 1: + if (input[i + 1] < od_table->uclkfmin) { + dev_info(smu->adev->dev, "uclkfmax (%ld) must be >= uclkfmin (%u)! ", + input[i + 1], od_table->uclkfmin); + return -einval; + } + + freq_setting = smu_11_0_7_odsetting_uclkfmax; + freq_ptr = &od_table->uclkfmax; + break; + + default: + dev_info(smu->adev->dev, "invalid mclk_vddc_table index: %ld ", input[i]); + dev_info(smu->adev->dev, "supported indices: [0:min,1:max] "); + return -einval; + } + + ret = sienna_cichlid_od_setting_check_range(smu, od_settings, + freq_setting, input[i + 1]); + if (ret) + return ret; + + *freq_ptr = (uint16_t)input[i + 1]; + } + break; + + case pp_od_restore_default_table: + memcpy(table_context->overdrive_table, + table_context->boot_overdrive_table, + sizeof(overdrivetable_t)); + fallthrough; + + case pp_od_commit_dpm_table: + sienna_cichlid_dump_od_table(smu, od_table); + + ret = smu_cmn_update_table(smu, smu_table_overdrive, + 0, (void *)od_table, true); + if (ret) { + dev_err(smu->adev->dev, "failed to import overdrive table! "); + return ret; + } + break; + + default: + return -enosys; + } + + return ret; +} + + .od_edit_dpm_table = sienna_cichlid_od_edit_dpm_table,
|
Graphics
|
37a58f691551dfdff4f1035ee119c9ebdb9eb119
|
evan quan alex deucher alexander deucher amd com
|
drivers
|
gpu
|
amd, drm, pm, smu11, swsmu
|
drm/amd/pm: support overdrive vddgfx offset setting(v2)
|
this is supported by sienna cichlid, navy flounder and dimgrey cavefish. for these asics, the target voltage calculation can be illustrated by "voltage = voltage calculated from v/f curve + overdrive vddgfx offset".
|
this release allows to map an uid to a different one in a mount; it also adds support for selecting the preemption model at runtime; support for a low-overhead memory error detector designed to be used in production; support for the acrn hypervisor designed for embedded systems; btrfs initial support for zoned devices, subpage blocks sizes and performance improvements; support for eager nfs writes; support for a thermal power management to control the surface temperature of embedded devices in an unified way; the napi polling can be moved to a kernel thread; and support for non-blocking path lookups. as always, there are many other features, new drivers, improvements and fixes.
|
sienna cichild overdrive support
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'cryptography', 'security', 'networking', 'architectures x86 arm risc-v powerpc mips csky s390 pa-risc c6x']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'cpu frequency scaling', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'cryptography hardware acceleration', 'pci', 'non-transparent bridge (ntb)', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'cxl (compute express link)', 'various']
|
['amdgpu ']
|
['h', 'c']
| 4
| 70
| 2
|
--- diff --git a/drivers/gpu/drm/amd/include/kgd_pp_interface.h b/drivers/gpu/drm/amd/include/kgd_pp_interface.h --- a/drivers/gpu/drm/amd/include/kgd_pp_interface.h +++ b/drivers/gpu/drm/amd/include/kgd_pp_interface.h - pp_od_commit_dpm_table + pp_od_commit_dpm_table, + pp_od_edit_vddgfx_offset diff --git a/drivers/gpu/drm/amd/pm/amdgpu_pm.c b/drivers/gpu/drm/amd/pm/amdgpu_pm.c --- a/drivers/gpu/drm/amd/pm/amdgpu_pm.c +++ b/drivers/gpu/drm/amd/pm/amdgpu_pm.c + * - voltage offset(in mv) applied on target voltage calculation. + * this is available for sienna cichlid, navy flounder and dimgrey + * cavefish. for these asics, the target voltage calculation can be + * illustrated by "voltage = voltage calculated from v/f curve + + * overdrive vddgfx offset" + * + * to update the voltage offset applied for gfxclk/voltage calculation, + * enter the new value by writing a string that contains "vo offset". + * this is supported by sienna cichlid, navy flounder and dimgrey cavefish. + * and the offset can be a positive or negative value. + * + else if (!strncmp(buf, "vo", 2)) + type = pp_od_edit_vddgfx_offset; - if (type == pp_od_edit_vddc_curve) + if ((type == pp_od_edit_vddc_curve) || + (type == pp_od_edit_vddgfx_offset)) + size += smu_print_clk_levels(&adev->smu, smu_od_vddgfx_offset, buf+size); diff --git a/drivers/gpu/drm/amd/pm/inc/smu_types.h b/drivers/gpu/drm/amd/pm/inc/smu_types.h --- a/drivers/gpu/drm/amd/pm/inc/smu_types.h +++ b/drivers/gpu/drm/amd/pm/inc/smu_types.h + smu_od_vddgfx_offset, diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c --- a/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c +++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c + uint32_t smu_version; + case smu_od_vddgfx_offset: + if (!smu->od_enabled || !od_table || !od_settings) + break; + + /* + * od gfx voltage offset functionality is supported only by 58.41.0 + * and onwards smu firmwares. + */ + smu_cmn_get_smc_version(smu, null, &smu_version); + if ((adev->asic_type == chip_sienna_cichlid) && + (smu_version < 0x003a2900)) + break; + + size += sprintf(buf + size, "od_vddgfx_offset: "); + size += sprintf(buf + size, "%dmv ", od_table->vddgfxoffset); + break; + + struct amdgpu_device *adev = smu->adev; + uint32_t smu_version; + + + smu_cmn_get_smc_version(smu, null, &smu_version); + if (!((adev->asic_type == chip_sienna_cichlid) && + (smu_version < 0x003a2900))) + dev_dbg(smu->adev->dev, "od: vddgfxoffset: %d ", od_table->vddgfxoffset); + struct amdgpu_device *adev = smu->adev; + uint32_t smu_version; + case pp_od_edit_vddgfx_offset: + if (size != 1) { + dev_info(smu->adev->dev, "invalid number of parameters: %d ", size); + return -einval; + } + + /* + * od gfx voltage offset functionality is supported only by 58.41.0 + * and onwards smu firmwares. + */ + smu_cmn_get_smc_version(smu, null, &smu_version); + if ((adev->asic_type == chip_sienna_cichlid) && + (smu_version < 0x003a2900)) { + dev_err(smu->adev->dev, "od gfx voltage offset functionality is supported " + "only by 58.41.0 and onwards smu firmwares! "); + return -eopnotsupp; + } + + od_table->vddgfxoffset = (int16_t)input[0]; + + sienna_cichlid_dump_od_table(smu, od_table); + break; +
|
Graphics
|
a2b6df4fd6e3c0ba088b00fc00579dac263b0a64
|
evan quan
|
drivers
|
gpu
|
amd, drm, inc, include, pm, smu11, swsmu
|
drm/amd/display: check plane scaling against format specific hw plane caps.
|
this takes hw constraints specific to pixel formats into account, e.g., the inability of older hw to scale fp16 format framebuffers.
|
this release allows to map an uid to a different one in a mount; it also adds support for selecting the preemption model at runtime; support for a low-overhead memory error detector designed to be used in production; support for the acrn hypervisor designed for embedded systems; btrfs initial support for zoned devices, subpage blocks sizes and performance improvements; support for eager nfs writes; support for a thermal power management to control the surface temperature of embedded devices in an unified way; the napi polling can be moved to a kernel thread; and support for non-blocking path lookups. as always, there are many other features, new drivers, improvements and fixes.
|
fp16 on dce8-11 support
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'cryptography', 'security', 'networking', 'architectures x86 arm risc-v powerpc mips csky s390 pa-risc c6x']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'cpu frequency scaling', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'cryptography hardware acceleration', 'pci', 'non-transparent bridge (ntb)', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'cxl (compute express link)', 'various']
|
['amdgpu ']
|
['c']
| 1
| 73
| 8
|
--- diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +static void get_min_max_dc_plane_scaling(struct drm_device *dev, + struct drm_framebuffer *fb, + int *min_downscale, int *max_upscale) +{ + struct amdgpu_device *adev = drm_to_adev(dev); + struct dc *dc = adev->dm.dc; + /* caps for all supported planes are the same on dce and dcn 1 - 3 */ + struct dc_plane_cap *plane_cap = &dc->caps.planes[0]; + + switch (fb->format->format) { + case drm_format_p010: + case drm_format_nv12: + case drm_format_nv21: + *max_upscale = plane_cap->max_upscale_factor.nv12; + *min_downscale = plane_cap->max_downscale_factor.nv12; + break; + + case drm_format_xrgb16161616f: + case drm_format_argb16161616f: + case drm_format_xbgr16161616f: + case drm_format_abgr16161616f: + *max_upscale = plane_cap->max_upscale_factor.fp16; + *min_downscale = plane_cap->max_downscale_factor.fp16; + break; + + default: + *max_upscale = plane_cap->max_upscale_factor.argb8888; + *min_downscale = plane_cap->max_downscale_factor.argb8888; + break; + } + + /* + * a factor of 1 in the plane_cap means to not allow scaling, ie. use a + * scaling factor of 1.0 == 1000 units. + */ + if (*max_upscale == 1) + *max_upscale = 1000; + + if (*min_downscale == 1) + *min_downscale = 1000; +} + + - int scale_w, scale_h; + int scale_w, scale_h, min_downscale, max_upscale; - /* todo: validate scaling per-format with dc plane caps */ + /* validate scaling per-format with dc plane caps */ + if (state->plane && state->plane->dev && state->fb) { + get_min_max_dc_plane_scaling(state->plane->dev, state->fb, + &min_downscale, &max_upscale); + } else { + min_downscale = 250; + max_upscale = 16000; + } + - if (scale_w < 250 || scale_w > 16000) + if (scale_w < min_downscale || scale_w > max_upscale) - if (scale_h < 250 || scale_h > 16000) + if (scale_h < min_downscale || scale_h > max_upscale) - int max_downscale = 0; - int max_upscale = int_max; + struct drm_framebuffer *fb = state->fb; + int min_downscale, max_upscale; + int min_scale = 0; + int max_scale = int_max; + + /* plane enabled? get min/max allowed scaling factors from plane caps. */ + if (fb && state->crtc) { + get_min_max_dc_plane_scaling(state->crtc->dev, fb, + &min_downscale, &max_upscale); + /* + * convert to drm convention: 16.16 fixed point, instead of dc's + * 1.0 == 1000. also drm scaling is src/dst instead of dc's + * dst/src, so min_scale = 1.0 / max_upscale, etc. + */ + min_scale = (1000 << 16) / max_upscale; + max_scale = (1000 << 16) / min_downscale; + } - /* todo: these should be checked against dc plane caps */ - state, new_crtc_state, max_downscale, max_upscale, true, true); + state, new_crtc_state, min_scale, max_scale, true, true);
|
Graphics
|
6300b3bd9d0d7afaf085dd086ce6258511c3f057
|
mario kleiner
|
drivers
|
gpu
|
amd, amdgpu_dm, display, drm
|
drm/amd/display: enable fp16 also on dce-8/10/11.
|
the hw supports fp16, this is not only useful for hdr, but also for standard dynamic range displays, because it allows to get more precise color reproduction with about 11 - 12 bpc linear precision in the unorm range 0.0 - 1.0.
|
this release allows to map an uid to a different one in a mount; it also adds support for selecting the preemption model at runtime; support for a low-overhead memory error detector designed to be used in production; support for the acrn hypervisor designed for embedded systems; btrfs initial support for zoned devices, subpage blocks sizes and performance improvements; support for eager nfs writes; support for a thermal power management to control the surface temperature of embedded devices in an unified way; the napi polling can be moved to a kernel thread; and support for non-blocking path lookups. as always, there are many other features, new drivers, improvements and fixes.
|
fp16 on dce8-11 support
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'cryptography', 'security', 'networking', 'architectures x86 arm risc-v powerpc mips csky s390 pa-risc c6x']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'cpu frequency scaling', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'cryptography hardware acceleration', 'pci', 'non-transparent bridge (ntb)', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'cxl (compute express link)', 'various']
|
['amdgpu ']
|
['c']
| 3
| 3
| 3
|
--- diff --git a/drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c b/drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c --- a/drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c +++ b/drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c - .fp16 = false + .fp16 = true diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c --- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c +++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c - .fp16 = false + .fp16 = true diff --git a/drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c b/drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c --- a/drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c +++ b/drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c - .fp16 = false + .fp16 = true
|
Graphics
|
4b6b7437b19d3116d409e747582c99152725288d
|
mario kleiner
|
drivers
|
gpu
|
amd, dc, dce100, dce110, dce80, display, drm
|
drm/amdgpu: add mode2 reset support for vangogh
|
gpu reset is handled via smu similar to previous apus.
|
this release allows to map an uid to a different one in a mount; it also adds support for selecting the preemption model at runtime; support for a low-overhead memory error detector designed to be used in production; support for the acrn hypervisor designed for embedded systems; btrfs initial support for zoned devices, subpage blocks sizes and performance improvements; support for eager nfs writes; support for a thermal power management to control the surface temperature of embedded devices in an unified way; the napi polling can be moved to a kernel thread; and support for non-blocking path lookups. as always, there are many other features, new drivers, improvements and fixes.
|
gpu reset on navy flounder/vangogh
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'cryptography', 'security', 'networking', 'architectures x86 arm risc-v powerpc mips csky s390 pa-risc c6x']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'cpu frequency scaling', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'cryptography hardware acceleration', 'pci', 'non-transparent bridge (ntb)', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'cxl (compute express link)', 'various']
|
['amdgpu ']
|
['c']
| 1
| 6
| 0
|
--- diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c --- a/drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c +++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c +static int vangogh_mode2_reset(struct smu_context *smu) +{ + return smu_cmn_send_smc_msg_with_param(smu, smu_msg_gfxdevicedriverreset, smu_reset_mode_2, null); +} + + .mode2_reset = vangogh_mode2_reset,
|
Graphics
|
20e157c725783caba0a880d48ef0e1355074175b
|
alex deucher evan quan evan quan amd com huang rui ray huang amd com
|
drivers
|
gpu
|
amd, drm, pm, smu11, swsmu
|
drm/amdgpu/nv: add mode2 reset handling
|
vangogh will use mode2 reset, so plumb it through the nv soc driver.
|
this release allows to map an uid to a different one in a mount; it also adds support for selecting the preemption model at runtime; support for a low-overhead memory error detector designed to be used in production; support for the acrn hypervisor designed for embedded systems; btrfs initial support for zoned devices, subpage blocks sizes and performance improvements; support for eager nfs writes; support for a thermal power management to control the surface temperature of embedded devices in an unified way; the napi polling can be moved to a kernel thread; and support for non-blocking path lookups. as always, there are many other features, new drivers, improvements and fixes.
|
gpu reset on navy flounder/vangogh
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'cryptography', 'security', 'networking', 'architectures x86 arm risc-v powerpc mips csky s390 pa-risc c6x']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'cpu frequency scaling', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'cryptography hardware acceleration', 'pci', 'non-transparent bridge (ntb)', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'cxl (compute express link)', 'various']
|
['amdgpu ']
|
['c']
| 1
| 12
| 2
|
--- diff --git a/drivers/gpu/drm/amd/amdgpu/nv.c b/drivers/gpu/drm/amd/amdgpu/nv.c --- a/drivers/gpu/drm/amd/amdgpu/nv.c +++ b/drivers/gpu/drm/amd/amdgpu/nv.c + amdgpu_reset_method == amd_reset_method_mode2 || + case chip_vangogh: + return amd_reset_method_mode2; - if (nv_asic_reset_method(adev) == amd_reset_method_baco) { + switch (nv_asic_reset_method(adev)) { + case amd_reset_method_baco: - } else { + break; + case amd_reset_method_mode2: + dev_info(adev->dev, "mode2 reset "); + ret = amdgpu_dpm_mode2_reset(adev); + break; + default: + break;
|
Graphics
|
1608635534fb8cc42e94d19d52789d9448f02536
|
alex deucher evan quan evan quan amd com huang rui ray huang amd com
|
drivers
|
gpu
|
amd, amdgpu, drm
|
drm/amdgpu: fix mode2 reset sequence for vangogh
|
we need to save and restore pci config space.
|
this release allows to map an uid to a different one in a mount; it also adds support for selecting the preemption model at runtime; support for a low-overhead memory error detector designed to be used in production; support for the acrn hypervisor designed for embedded systems; btrfs initial support for zoned devices, subpage blocks sizes and performance improvements; support for eager nfs writes; support for a thermal power management to control the surface temperature of embedded devices in an unified way; the napi polling can be moved to a kernel thread; and support for non-blocking path lookups. as always, there are many other features, new drivers, improvements and fixes.
|
gpu reset on navy flounder/vangogh
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'cryptography', 'security', 'networking', 'architectures x86 arm risc-v powerpc mips csky s390 pa-risc c6x']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'cpu frequency scaling', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'cryptography hardware acceleration', 'pci', 'non-transparent bridge (ntb)', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'cxl (compute express link)', 'various']
|
['amdgpu ']
|
['c']
| 1
| 33
| 1
|
--- diff --git a/drivers/gpu/drm/amd/amdgpu/nv.c b/drivers/gpu/drm/amd/amdgpu/nv.c --- a/drivers/gpu/drm/amd/amdgpu/nv.c +++ b/drivers/gpu/drm/amd/amdgpu/nv.c +static int nv_asic_mode2_reset(struct amdgpu_device *adev) +{ + u32 i; + int ret = 0; + + amdgpu_atombios_scratch_regs_engine_hung(adev, true); + + /* disable bm */ + pci_clear_master(adev->pdev); + + amdgpu_device_cache_pci_state(adev->pdev); + + ret = amdgpu_dpm_mode2_reset(adev); + if (ret) + dev_err(adev->dev, "gpu mode2 reset failed "); + + amdgpu_device_load_pci_state(adev->pdev); + + /* wait for asic to come out of reset */ + for (i = 0; i < adev->usec_timeout; i++) { + u32 memsize = adev->nbio.funcs->get_memsize(adev); + + if (memsize != 0xffffffff) + break; + udelay(1); + } + + amdgpu_atombios_scratch_regs_engine_hung(adev, false); + + return ret; +} + - ret = amdgpu_dpm_mode2_reset(adev); + ret = nv_asic_mode2_reset(adev);
|
Graphics
|
b913ec628ce2e701ba5a7d5f060f4d62d7a2ce06
|
alex deucher huang rui ray huang amd com
|
drivers
|
gpu
|
amd, amdgpu, drm
|
drm/amdgpu: enable gpu reset for vangogh
|
enable gpu reset when we encounter a hang.
|
this release allows to map an uid to a different one in a mount; it also adds support for selecting the preemption model at runtime; support for a low-overhead memory error detector designed to be used in production; support for the acrn hypervisor designed for embedded systems; btrfs initial support for zoned devices, subpage blocks sizes and performance improvements; support for eager nfs writes; support for a thermal power management to control the surface temperature of embedded devices in an unified way; the napi polling can be moved to a kernel thread; and support for non-blocking path lookups. as always, there are many other features, new drivers, improvements and fixes.
|
gpu reset on navy flounder/vangogh
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'cryptography', 'security', 'networking', 'architectures x86 arm risc-v powerpc mips csky s390 pa-risc c6x']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'cpu frequency scaling', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'cryptography hardware acceleration', 'pci', 'non-transparent bridge (ntb)', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'cxl (compute express link)', 'various']
|
['amdgpu ']
|
['c']
| 1
| 1
| 0
|
--- diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c + case chip_vangogh:
|
Graphics
|
b6903089a5ab74e8bcae963d5ca60b0005b75c05
|
alex deucher evan quan evan quan amd com huang rui ray huang amd com
|
drivers
|
gpu
|
amd, amdgpu, drm
|
drm/amdgpu: enable gpu recovery for navy_flounder
|
enable gpu recovery for navy_flounder by default to trigger reset once needed.
|
this release allows to map an uid to a different one in a mount; it also adds support for selecting the preemption model at runtime; support for a low-overhead memory error detector designed to be used in production; support for the acrn hypervisor designed for embedded systems; btrfs initial support for zoned devices, subpage blocks sizes and performance improvements; support for eager nfs writes; support for a thermal power management to control the surface temperature of embedded devices in an unified way; the napi polling can be moved to a kernel thread; and support for non-blocking path lookups. as always, there are many other features, new drivers, improvements and fixes.
|
gpu reset on navy flounder/vangogh
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'cryptography', 'security', 'networking', 'architectures x86 arm risc-v powerpc mips csky s390 pa-risc c6x']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'cpu frequency scaling', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'cryptography hardware acceleration', 'pci', 'non-transparent bridge (ntb)', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'cxl (compute express link)', 'various']
|
['amdgpu ']
|
['c']
| 1
| 1
| 0
|
--- diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c + case chip_navy_flounder:
|
Graphics
|
665fe4dce83d14177f46fac814964ec107f196b5
|
jiansong chen tao zhou tao zhou amd com
|
drivers
|
gpu
|
amd, amdgpu, drm
|
drm/amd/display: add freesync hdmi support to dmcu
|
[why] adding support for freesync hdmi to dc and dmcu
|
this release allows to map an uid to a different one in a mount; it also adds support for selecting the preemption model at runtime; support for a low-overhead memory error detector designed to be used in production; support for the acrn hypervisor designed for embedded systems; btrfs initial support for zoned devices, subpage blocks sizes and performance improvements; support for eager nfs writes; support for a thermal power management to control the surface temperature of embedded devices in an unified way; the napi polling can be moved to a kernel thread; and support for non-blocking path lookups. as always, there are many other features, new drivers, improvements and fixes.
|
add freesync hdmi support to dmcu
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'cryptography', 'security', 'networking', 'architectures x86 arm risc-v powerpc mips csky s390 pa-risc c6x']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'cpu frequency scaling', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'cryptography hardware acceleration', 'pci', 'non-transparent bridge (ntb)', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'cxl (compute express link)', 'various']
|
['amdgpu ']
|
['h', 'c', 'makefile']
| 6
| 268
| 1
|
--- diff --git a/drivers/gpu/drm/amd/display/dc/makefile b/drivers/gpu/drm/amd/display/dc/makefile --- a/drivers/gpu/drm/amd/display/dc/makefile +++ b/drivers/gpu/drm/amd/display/dc/makefile +dc_edid += dc_edid_parser.o -amd_display_files += $(amd_display_dmub) +amd_display_edid = $(addprefix $(amddalpath)/dc/,$(dc_edid)) +amd_display_files += $(amd_display_dmub) $(amd_display_edid) diff --git a/drivers/gpu/drm/amd/display/dc/dc_edid_parser.c b/drivers/gpu/drm/amd/display/dc/dc_edid_parser.c --- /dev/null +++ b/drivers/gpu/drm/amd/display/dc/dc_edid_parser.c +/* + * copyright 2021 advanced micro devices, inc. + * + * permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "software"), + * to deal in the software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the software, and to permit persons to whom the + * software is furnished to do so, subject to the following conditions: + * + * the above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the software. + * + * the software is provided "as is", without warranty of any kind, express or + * implied, including but not limited to the warranties of merchantability, + * fitness for a particular purpose and noninfringement. in no event shall + * the copyright holder(s) or author(s) be liable for any claim, damages or + * other liability, whether in an action of contract, tort or otherwise, + * arising from, out of or in connection with the software or the use or + * other dealings in the software. + * + * authors: amd + * + */ + +#include "dce/dce_dmcu.h" +#include "dc_edid_parser.h" + +bool dc_edid_parser_send_cea(struct dc *dc, + int offset, + int total_length, + uint8_t *data, + int length) +{ + struct dmcu *dmcu = dc->res_pool->dmcu; + + if (dmcu && + dmcu->funcs->is_dmcu_initialized(dmcu) && + dmcu->funcs->send_edid_cea) { + return dmcu->funcs->send_edid_cea(dmcu, + offset, + total_length, + data, + length); + } + + return false; +} + +bool dc_edid_parser_recv_cea_ack(struct dc *dc, int *offset) +{ + struct dmcu *dmcu = dc->res_pool->dmcu; + + if (dmcu && + dmcu->funcs->is_dmcu_initialized(dmcu) && + dmcu->funcs->recv_edid_cea_ack) { + return dmcu->funcs->recv_edid_cea_ack(dmcu, offset); + } + + return false; +} + +bool dc_edid_parser_recv_amd_vsdb(struct dc *dc, + int *version, + int *min_frame_rate, + int *max_frame_rate) +{ + struct dmcu *dmcu = dc->res_pool->dmcu; + + if (dmcu && + dmcu->funcs->is_dmcu_initialized(dmcu) && + dmcu->funcs->recv_amd_vsdb) { + return dmcu->funcs->recv_amd_vsdb(dmcu, + version, + min_frame_rate, + max_frame_rate); + } + + return false; +} diff --git a/drivers/gpu/drm/amd/display/dc/dc_edid_parser.h b/drivers/gpu/drm/amd/display/dc/dc_edid_parser.h --- /dev/null +++ b/drivers/gpu/drm/amd/display/dc/dc_edid_parser.h +/* + * copyright 2021 advanced micro devices, inc. + * + * permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "software"), + * to deal in the software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the software, and to permit persons to whom the + * software is furnished to do so, subject to the following conditions: + * + * the above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the software. + * + * the software is provided "as is", without warranty of any kind, express or + * implied, including but not limited to the warranties of merchantability, + * fitness for a particular purpose and noninfringement. in no event shall + * the copyright holder(s) or author(s) be liable for any claim, damages or + * other liability, whether in an action of contract, tort or otherwise, + * arising from, out of or in connection with the software or the use or + * other dealings in the software. + * + * authors: amd + * + */ + +#ifndef _dc_edid_parser_h_ +#define _dc_edid_parser_h_ + +#include "core_types.h" + +bool dc_edid_parser_send_cea(struct dc *dc, + int offset, + int total_length, + uint8_t *data, + int length); + +bool dc_edid_parser_recv_cea_ack(struct dc *dc, int *offset); + +bool dc_edid_parser_recv_amd_vsdb(struct dc *dc, + int *version, + int *min_frame_rate, + int *max_frame_rate); + +#endif /* _dc_edid_parser_h_ */ diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c b/drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c --- a/drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c +++ b/drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c +#define mcp_send_edid_cea 0xa0 +#define edid_cea_cmd_ack 1 +#define edid_cea_cmd_nack 2 +static bool dcn10_send_edid_cea(struct dmcu *dmcu, + int offset, + int total_length, + uint8_t *data, + int length) +{ + struct dce_dmcu *dmcu_dce = to_dce_dmcu(dmcu); + uint32_t header, data1, data2; + + /* if microcontroller is not running, do nothing */ + if (dmcu->dmcu_state != dmcu_running) + return false; + + if (length > 8 || length <= 0) + return false; + + header = ((uint32_t)offset & 0xffff) << 16 | (total_length & 0xffff); + data1 = (((uint32_t)data[0]) << 24) | (((uint32_t)data[1]) << 16) | + (((uint32_t)data[2]) << 8) | ((uint32_t)data[3]); + data2 = (((uint32_t)data[4]) << 24) | (((uint32_t)data[5]) << 16) | + (((uint32_t)data[6]) << 8) | ((uint32_t)data[7]); + + /* waitdmcureadyforcmd */ + reg_wait(master_comm_cntl_reg, master_comm_interrupt, 0, 1, 10000); + + /* setdmcuparam_cmd */ + reg_update(master_comm_cmd_reg, master_comm_cmd_reg_byte0, mcp_send_edid_cea); + + reg_write(master_comm_data_reg1, header); + reg_write(master_comm_data_reg2, data1); + reg_write(master_comm_data_reg3, data2); + + /* notifydmcumsg */ + reg_update(master_comm_cntl_reg, master_comm_interrupt, 1); + + /* waitdmcureadyforcmd */ + reg_wait(master_comm_cntl_reg, master_comm_interrupt, 0, 1, 10000); + + return true; +} + +static bool dcn10_get_scp_results(struct dmcu *dmcu, + uint32_t *cmd, + uint32_t *data1, + uint32_t *data2, + uint32_t *data3) +{ + struct dce_dmcu *dmcu_dce = to_dce_dmcu(dmcu); + + /* if microcontroller is not running, do nothing */ + if (dmcu->dmcu_state != dmcu_running) + return false; + + *cmd = reg_read(slave_comm_cmd_reg); + *data1 = reg_read(slave_comm_data_reg1); + *data2 = reg_read(slave_comm_data_reg2); + *data3 = reg_read(slave_comm_data_reg3); + + /* clear scp interrupt */ + reg_update(slave_comm_cntl_reg, slave_comm_interrupt, 0); + + return true; +} + +static bool dcn10_recv_amd_vsdb(struct dmcu *dmcu, + int *version, + int *min_frame_rate, + int *max_frame_rate) +{ + uint32_t data[4]; + int cmd, ack, len; + + if (!dcn10_get_scp_results(dmcu, &data[0], &data[1], &data[2], &data[3])) + return false; + + cmd = data[0] & 0x3ff; + len = (data[0] >> 10) & 0x3f; + ack = data[1]; + + if (cmd != mcp_send_edid_cea || ack != edid_cea_cmd_ack || len != 12) + return false; + + if ((data[2] & 0xff)) { + *version = (data[2] >> 8) & 0xff; + *min_frame_rate = (data[3] >> 16) & 0xffff; + *max_frame_rate = data[3] & 0xffff; + return true; + } + + return false; +} + +static bool dcn10_recv_edid_cea_ack(struct dmcu *dmcu, int *offset) +{ + uint32_t data[4]; + int cmd, ack; + + if (!dcn10_get_scp_results(dmcu, + &data[0], &data[1], &data[2], &data[3])) + return false; + + cmd = data[0] & 0x3ff; + ack = data[1]; + + if (cmd != mcp_send_edid_cea) + return false; + + if (ack == edid_cea_cmd_ack) + return true; + + *offset = data[2]; /* nack */ + return false; +} + + .send_edid_cea = dcn10_send_edid_cea, + .recv_amd_vsdb = dcn10_recv_amd_vsdb, + .recv_edid_cea_ack = dcn10_recv_edid_cea_ack, diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.h b/drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.h --- a/drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.h +++ b/drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.h + sr(slave_comm_data_reg1), \ + sr(slave_comm_data_reg2), \ + sr(slave_comm_data_reg3), \ + sr(slave_comm_cmd_reg), \ + dmcu_sf(slave_comm_cntl_reg, slave_comm_interrupt, mask_sh), \ + type slave_comm_interrupt; \ + uint32_t slave_comm_data_reg1; + uint32_t slave_comm_data_reg2; + uint32_t slave_comm_data_reg3; + uint32_t slave_comm_cmd_reg; + uint32_t slave_comm_cntl_reg; diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/dmcu.h b/drivers/gpu/drm/amd/display/dc/inc/hw/dmcu.h --- a/drivers/gpu/drm/amd/display/dc/inc/hw/dmcu.h +++ b/drivers/gpu/drm/amd/display/dc/inc/hw/dmcu.h + bool (*send_edid_cea)(struct dmcu *dmcu, + int offset, + int total_length, + uint8_t *data, + int length); + bool (*recv_amd_vsdb)(struct dmcu *dmcu, + int *version, + int *min_frame_rate, + int *max_frame_rate); + bool (*recv_edid_cea_ack)(struct dmcu *dmcu, int *offset);
|
Graphics
|
a0c898f28a3b6d97d425aafc56085c273e9f1cff
|
stylon wang
|
drivers
|
gpu
|
amd, dc, dce, display, drm, hw, inc
|
drm/amd/display: enable "trigger_hotplug" debugfs on all outputs
|
[why] per-connector debugfs entry "trigger_hotplug" is available on dp/edp only. new igt tests need this entry to test other outputs.
|
this release allows to map an uid to a different one in a mount; it also adds support for selecting the preemption model at runtime; support for a low-overhead memory error detector designed to be used in production; support for the acrn hypervisor designed for embedded systems; btrfs initial support for zoned devices, subpage blocks sizes and performance improvements; support for eager nfs writes; support for a thermal power management to control the surface temperature of embedded devices in an unified way; the napi polling can be moved to a kernel thread; and support for non-blocking path lookups. as always, there are many other features, new drivers, improvements and fixes.
|
enable "trigger_hotplug" debugfs on all outputs
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'cryptography', 'security', 'networking', 'architectures x86 arm risc-v powerpc mips csky s390 pa-risc c6x']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'cpu frequency scaling', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'cryptography hardware acceleration', 'pci', 'non-transparent bridge (ntb)', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'cxl (compute express link)', 'various']
|
['amdgpu ']
|
['c']
| 1
| 6
| 4
|
--- diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c -static ssize_t dp_trigger_hotplug(struct file *f, const char __user *buf, +static ssize_t trigger_hotplug(struct file *f, const char __user *buf, -static const struct file_operations dp_trigger_hotplug_debugfs_fops = { +static const struct file_operations trigger_hotplug_debugfs_fops = { - .write = dp_trigger_hotplug, + .write = trigger_hotplug, - {"trigger_hotplug", &dp_trigger_hotplug_debugfs_fops}, + debugfs_create_file("trigger_hotplug", 0644, dir, connector, + &trigger_hotplug_debugfs_fops); +
|
Graphics
|
02a342e3c4e511f43f24918921866254913c759d
|
stylon wang
|
drivers
|
gpu
|
amd, amdgpu_dm, display, drm
|
drm/amd/display: enable hubp blank behaviour
|
- reverts "drm/amd/display: revert hubp blank behaviour for now" - hubp blank will fail if the pipe is locked (this is the case on linux), so add a check to make sure pipe isn't locked, if it is then defer the blank to post_unlock.
|
this release allows to map an uid to a different one in a mount; it also adds support for selecting the preemption model at runtime; support for a low-overhead memory error detector designed to be used in production; support for the acrn hypervisor designed for embedded systems; btrfs initial support for zoned devices, subpage blocks sizes and performance improvements; support for eager nfs writes; support for a thermal power management to control the surface temperature of embedded devices in an unified way; the napi polling can be moved to a kernel thread; and support for non-blocking path lookups. as always, there are many other features, new drivers, improvements and fixes.
|
enable hubp blank behaviour
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'cryptography', 'security', 'networking', 'architectures x86 arm risc-v powerpc mips csky s390 pa-risc c6x']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'cpu frequency scaling', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'cryptography hardware acceleration', 'pci', 'non-transparent bridge (ntb)', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'cxl (compute express link)', 'various']
|
['amdgpu ']
|
['h', 'c']
| 8
| 45
| 3
|
- reverts "drm/amd/display: revert hubp blank behaviour for now" - hubp blank will fail if the pipe is locked (this is the case on --- diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c --- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c +++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c +bool optc1_is_locked(struct timing_generator *optc) +{ + struct optc *optc1 = dcn10tg_from_tg(optc); + uint32_t locked; + + reg_get(otg_master_update_lock, update_lock_status, &locked); + + return (locked == 1); +} + + .is_locked = optc1_is_locked, diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h --- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h +++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h +bool optc1_is_locked(struct timing_generator *optc); diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c --- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c +++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c + for (i = 0; i < dc->res_pool->pipe_count; i++) { + struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i]; + + if (pipe->vtp_locked) { + dc->hwss.set_hubp_blank(dc, pipe, true); + pipe->vtp_locked = false; + } + } diff --git a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_hwseq.c b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_hwseq.c --- a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_hwseq.c +++ b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_hwseq.c - pipe_ctx->stream_res.opp->funcs->opp_set_disp_pattern_generator(pipe_ctx->stream_res.opp, test_pattern, - color_space, color_depth, solid_color, width, height, offset); + struct stream_resource *stream_res = &pipe_ctx->stream_res; + + if (test_pattern != controller_dp_test_pattern_videomode) { + pipe_ctx->vtp_locked = false; + /* turning on dpg */ + stream_res->opp->funcs->opp_set_disp_pattern_generator(stream_res->opp, test_pattern, color_space, + color_depth, solid_color, width, height, offset); + + /* defer hubp blank if tg is locked */ + if (stream_res->tg->funcs->is_tg_enabled(stream_res->tg)) { + if (stream_res->tg->funcs->is_locked(stream_res->tg)) + pipe_ctx->vtp_locked = true; + else + dc->hwss.set_hubp_blank(dc, pipe_ctx, true); + } + } else { + dc->hwss.set_hubp_blank(dc, pipe_ctx, false); + /* turning off dpg */ + stream_res->opp->funcs->opp_set_disp_pattern_generator(stream_res->opp, test_pattern, color_space, + color_depth, solid_color, width, height, offset); + } diff --git a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_optc.c b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_optc.c --- a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_optc.c +++ b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_optc.c + .is_locked = optc1_is_locked, diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c b/drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c --- a/drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c +++ b/drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c - if (mode_lib->vba.minactivedramclockchangemargin > 0 && prefetchmode == 0) { + if (mode_lib->vba.minactivedramclockchangemargin > 0) { diff --git a/drivers/gpu/drm/amd/display/dc/inc/core_types.h b/drivers/gpu/drm/amd/display/dc/inc/core_types.h --- a/drivers/gpu/drm/amd/display/dc/inc/core_types.h +++ b/drivers/gpu/drm/amd/display/dc/inc/core_types.h + bool vtp_locked; diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/timing_generator.h b/drivers/gpu/drm/amd/display/dc/inc/hw/timing_generator.h --- a/drivers/gpu/drm/amd/display/dc/inc/hw/timing_generator.h +++ b/drivers/gpu/drm/amd/display/dc/inc/hw/timing_generator.h + bool (*is_locked)(struct timing_generator *tg);
|
Graphics
|
d209124ddae35fd5d86470421d3212c473169436
|
bhawanpreet lakha rodrigo siqueira rodrigo siqueira amd com nicholas kazlauskas nicholas kazlauskas amd com daniel wheeler daniel wheeler amd com
|
drivers
|
gpu
|
amd, dc, dcn10, dcn20, dcn30, display, dml, drm, hw, inc
|
drm/amd/display: implement t12 compliance
|
[why] when os reboots, and panel is turned off, t12 may not be maintained. t12 is defined as the interval between vddc off (occurs at shutdown) and the next vddc on (occurs when edp is post-ed)
|
this release allows to map an uid to a different one in a mount; it also adds support for selecting the preemption model at runtime; support for a low-overhead memory error detector designed to be used in production; support for the acrn hypervisor designed for embedded systems; btrfs initial support for zoned devices, subpage blocks sizes and performance improvements; support for eager nfs writes; support for a thermal power management to control the surface temperature of embedded devices in an unified way; the napi polling can be moved to a kernel thread; and support for non-blocking path lookups. as always, there are many other features, new drivers, improvements and fixes.
|
implement t12 compliance
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'cryptography', 'security', 'networking', 'architectures x86 arm risc-v powerpc mips csky s390 pa-risc c6x']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'cpu frequency scaling', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'cryptography hardware acceleration', 'pci', 'non-transparent bridge (ntb)', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'cxl (compute express link)', 'various']
|
['amdgpu ']
|
['h', 'c']
| 6
| 53
| 0
|
--- diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link.c b/drivers/gpu/drm/amd/display/dc/core/dc_link.c --- a/drivers/gpu/drm/amd/display/dc/core/dc_link.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc_link.c +bool dc_link_wait_for_t12(struct dc_link *link) +{ + if (link->connector_signal == signal_type_edp && link->dc->hwss.edp_wait_for_t12) { + link->dc->hwss.edp_wait_for_t12(link); + + return true; + } + + return false; +} + diff --git a/drivers/gpu/drm/amd/display/dc/dc_link.h b/drivers/gpu/drm/amd/display/dc/dc_link.h --- a/drivers/gpu/drm/amd/display/dc/dc_link.h +++ b/drivers/gpu/drm/amd/display/dc/dc_link.h +/* + * on edp links this function call will stall until t12 has elapsed. + * if the panel is not in power off state, this function will return + * immediately. + */ +bool dc_link_wait_for_t12(struct dc_link *link); + diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c --- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c +++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c +void dce110_edp_wait_for_t12( + struct dc_link *link) +{ + struct dc_context *ctx = link->ctx; + + if (dal_graphics_object_id_get_connector_id(link->link_enc->connector) + != connector_id_edp) { + break_to_debugger(); + return; + } + + if (!link->panel_cntl) + return; + + if (!link->panel_cntl->funcs->is_panel_powered_on(link->panel_cntl) && + link->link_trace.time_stamp.edp_poweroff != 0) { + unsigned int t12_duration = 500; // default t12 as per spec + unsigned long long current_ts = dm_get_timestamp(ctx); + unsigned long long time_since_edp_poweroff_ms = + div64_u64(dm_get_elapse_time_in_ns( + ctx, + current_ts, + link->link_trace.time_stamp.edp_poweroff), 1000000); + + t12_duration += link->local_sink->edid_caps.panel_patch.extra_t12_ms; // add extra t12 + + if (time_since_edp_poweroff_ms < t12_duration) + msleep(t12_duration - time_since_edp_poweroff_ms); + } +} + diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.h b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.h --- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.h +++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.h +void dce110_edp_wait_for_t12( + struct dc_link *link); diff --git a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_init.c b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_init.c --- a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_init.c +++ b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_init.c + .edp_wait_for_t12 = dce110_edp_wait_for_t12, diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h b/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h --- a/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h +++ b/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h + void (*edp_wait_for_t12)(struct dc_link *link);
|
Graphics
|
cf3a2627597794797ce5930537c0e75df284b6e9
|
jun lei
|
drivers
|
gpu
|
amd, core, dc, dce110, dcn10, dcn30, display, drm, inc
|
drm/amd/pm: add interface for request wgps
|
when user specifies a reduced wgp(cu) config via disalbe_cu module parameter, this does not disable the clocks which uses additional power. this interface send active wgp number to smu and smu will cooperate with rlc to power off relative wgps.
|
this release allows to map an uid to a different one in a mount; it also adds support for selecting the preemption model at runtime; support for a low-overhead memory error detector designed to be used in production; support for the acrn hypervisor designed for embedded systems; btrfs initial support for zoned devices, subpage blocks sizes and performance improvements; support for eager nfs writes; support for a thermal power management to control the surface temperature of embedded devices in an unified way; the napi polling can be moved to a kernel thread; and support for non-blocking path lookups. as always, there are many other features, new drivers, improvements and fixes.
|
add interface for request wgps
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'cryptography', 'security', 'networking', 'architectures x86 arm risc-v powerpc mips csky s390 pa-risc c6x']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'cpu frequency scaling', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'cryptography hardware acceleration', 'pci', 'non-transparent bridge (ntb)', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'cxl (compute express link)', 'various']
|
['amdgpu ']
|
['h', 'c']
| 3
| 41
| 3
|
--- diff --git a/drivers/gpu/drm/amd/pm/inc/smu_types.h b/drivers/gpu/drm/amd/pm/inc/smu_types.h --- a/drivers/gpu/drm/amd/pm/inc/smu_types.h +++ b/drivers/gpu/drm/amd/pm/inc/smu_types.h + __smu_dummy_map(requestactivewgp), \ diff --git a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c b/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c --- a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c +++ b/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c - if (adev->asic_type == chip_vangogh) - return 0; - + if (adev->asic_type == chip_vangogh) + return 0; + diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c --- a/drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c +++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c +#include "soc15_common.h" +#include "asic_reg/gc/gc_10_3_0_offset.h" +#include "asic_reg/gc/gc_10_3_0_sh_mask.h" + msg_map(requestactivewgp, ppsmc_msg_requestactivewgp, 0), +static int vangogh_post_smu_init(struct smu_context *smu) +{ + struct amdgpu_device *adev = smu->adev; + uint32_t tmp; + uint8_t aon_bits = 0; + /* two cus in one wgp */ + uint32_t req_active_wgps = adev->gfx.cu_info.number/2; + uint32_t total_cu = adev->gfx.config.max_cu_per_sh * + adev->gfx.config.max_sh_per_se * adev->gfx.config.max_shader_engines; + + /* if all cus are active, no need to power off any wgps */ + if (total_cu == adev->gfx.cu_info.number) + return 0; + + /* + * calculate the total bits number of always on wgps for all sa/ses in + * rlc_pg_always_on_wgp_mask. + */ + tmp = rreg32_kiq(soc15_reg_offset(gc, 0, mmrlc_pg_always_on_wgp_mask)); + tmp &= rlc_pg_always_on_wgp_mask__aon_wgp_mask_mask; + + aon_bits = hweight32(tmp) * adev->gfx.config.max_sh_per_se * adev->gfx.config.max_shader_engines; + + /* do not request any wgps less than set in the aon_wgp_mask */ + if (aon_bits > req_active_wgps) { + dev_info(adev->dev, "number of always on wgps greater than active wgps: wgp power save not requested. "); + return 0; + } else { + return smu_cmn_send_smc_msg_with_param(smu, smu_msg_requestactivewgp, req_active_wgps, null); + } +} + + .post_init = vangogh_post_smu_init,
|
Graphics
|
eefdf0471069a41e7c3c2c2498270165464152be
|
jinzhou su
|
drivers
|
gpu
|
amd, drm, inc, pm, smu11, swsmu
|
drm/amd/pm: add support for hwmon control of slow and fast ppt limit on vangogh
|
implement hwmon api for reading/setting slow and fast ppt limit.
|
this release allows to map an uid to a different one in a mount; it also adds support for selecting the preemption model at runtime; support for a low-overhead memory error detector designed to be used in production; support for the acrn hypervisor designed for embedded systems; btrfs initial support for zoned devices, subpage blocks sizes and performance improvements; support for eager nfs writes; support for a thermal power management to control the surface temperature of embedded devices in an unified way; the napi polling can be moved to a kernel thread; and support for non-blocking path lookups. as always, there are many other features, new drivers, improvements and fixes.
|
add support for hwmon control of slow and fast ppt limit on vangogh
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'cryptography', 'security', 'networking', 'architectures x86 arm risc-v powerpc mips csky s390 pa-risc c6x']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'cpu frequency scaling', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'cryptography hardware acceleration', 'pci', 'non-transparent bridge (ntb)', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'cxl (compute express link)', 'various']
|
['amdgpu ']
|
['h', 'c']
| 6
| 204
| 18
|
--- diff --git a/drivers/gpu/drm/amd/pm/amdgpu_pm.c b/drivers/gpu/drm/amd/pm/amdgpu_pm.c --- a/drivers/gpu/drm/amd/pm/amdgpu_pm.c +++ b/drivers/gpu/drm/amd/pm/amdgpu_pm.c - uint32_t limit = 0; + int limit_type = to_sensor_dev_attr(attr)->index; + uint32_t limit = limit_type << 24; - uint32_t limit = 0; + int limit_type = to_sensor_dev_attr(attr)->index; + uint32_t limit = limit_type << 24; +static ssize_t amdgpu_hwmon_show_power_label(struct device *dev, + struct device_attribute *attr, + char *buf) +{ + int limit_type = to_sensor_dev_attr(attr)->index; + + return snprintf(buf, page_size, "%s ", + limit_type == smu_fast_ppt_limit ? "fastppt" : "slowppt"); +} + int limit_type = to_sensor_dev_attr(attr)->index; - + value |= limit_type << 24; +static sensor_device_attr(power1_label, s_irugo, amdgpu_hwmon_show_power_label, null, 0); +static sensor_device_attr(power2_average, s_irugo, amdgpu_hwmon_show_power_avg, null, 1); +static sensor_device_attr(power2_cap_max, s_irugo, amdgpu_hwmon_show_power_cap_max, null, 1); +static sensor_device_attr(power2_cap_min, s_irugo, amdgpu_hwmon_show_power_cap_min, null, 1); +static sensor_device_attr(power2_cap, s_irugo | s_iwusr, amdgpu_hwmon_show_power_cap, amdgpu_hwmon_set_power_cap, 1); +static sensor_device_attr(power2_label, s_irugo, amdgpu_hwmon_show_power_label, null, 1); + &sensor_dev_attr_power1_label.dev_attr.attr, + &sensor_dev_attr_power2_average.dev_attr.attr, + &sensor_dev_attr_power2_cap_max.dev_attr.attr, + &sensor_dev_attr_power2_cap_min.dev_attr.attr, + &sensor_dev_attr_power2_cap.dev_attr.attr, + &sensor_dev_attr_power2_label.dev_attr.attr, - if (((adev->flags & amd_is_apu) || - adev->family == amdgpu_family_si) && /* not implemented yet */ + if (((adev->family == amdgpu_family_si) || + ((adev->flags & amd_is_apu) && + (adev->asic_type != chip_vangogh))) && /* not implemented yet */ + /* only vangogh has fast ppt limit and power labels */ + if (!(adev->asic_type == chip_vangogh) && + (attr == &sensor_dev_attr_power2_average.dev_attr.attr || + attr == &sensor_dev_attr_power2_cap_max.dev_attr.attr || + attr == &sensor_dev_attr_power2_cap_min.dev_attr.attr || + attr == &sensor_dev_attr_power2_cap.dev_attr.attr || + attr == &sensor_dev_attr_power2_label.dev_attr.attr || + attr == &sensor_dev_attr_power1_label.dev_attr.attr)) + return 0; + diff --git a/drivers/gpu/drm/amd/pm/inc/amdgpu_smu.h b/drivers/gpu/drm/amd/pm/inc/amdgpu_smu.h --- a/drivers/gpu/drm/amd/pm/inc/amdgpu_smu.h +++ b/drivers/gpu/drm/amd/pm/inc/amdgpu_smu.h +enum smu_ppt_limit_type +{ + smu_default_ppt_limit = 0, + smu_fast_ppt_limit, +}; + + /** + * @get_ppt_limit: get the device's ppt limits. + */ + int (*get_ppt_limit)(struct smu_context *smu, uint32_t *ppt_limit, + enum smu_ppt_limit_type limit_type, enum smu_ppt_limit_level limit_level); + diff --git a/drivers/gpu/drm/amd/pm/inc/smu_v11_0.h b/drivers/gpu/drm/amd/pm/inc/smu_v11_0.h --- a/drivers/gpu/drm/amd/pm/inc/smu_v11_0.h +++ b/drivers/gpu/drm/amd/pm/inc/smu_v11_0.h +struct smu_11_5_power_context { + uint32_t power_source; + uint8_t in_power_limit_boost_mode; + enum smu_11_0_power_state power_state; + + uint32_t current_fast_ppt_limit; + uint32_t max_fast_ppt_limit; +}; + diff --git a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c b/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c --- a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c +++ b/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c + uint32_t limit_type = *limit >> 24; + int ret = 0; + - switch (limit_level) { - case smu_ppt_limit_current: - *limit = smu->current_power_limit; - break; - case smu_ppt_limit_max: - *limit = smu->max_power_limit; - break; - default: - break; + if (limit_type != smu_default_ppt_limit) { + if (smu->ppt_funcs->get_ppt_limit) + ret = smu->ppt_funcs->get_ppt_limit(smu, limit, limit_type, limit_level); + } else { + switch (limit_level) { + case smu_ppt_limit_current: + *limit = smu->current_power_limit; + break; + case smu_ppt_limit_max: + *limit = smu->max_power_limit; + break; + default: + break; + } - return 0; + return ret; + uint32_t limit_type = limit >> 24; + if (limit_type != smu_default_ppt_limit) + if (smu->ppt_funcs->set_power_limit) { + ret = smu->ppt_funcs->set_power_limit(smu, limit); + goto out; + } + diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/smu_v11_0.c b/drivers/gpu/drm/amd/pm/swsmu/smu11/smu_v11_0.c --- a/drivers/gpu/drm/amd/pm/swsmu/smu11/smu_v11_0.c +++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/smu_v11_0.c + size_t size = smu->adev->asic_type == chip_vangogh ? + sizeof(struct smu_11_5_power_context) : + sizeof(struct smu_11_0_power_context); - smu_power->power_context = kzalloc(sizeof(struct smu_11_0_power_context), - gfp_kernel); + smu_power->power_context = kzalloc(size, gfp_kernel); - smu_power->power_context_size = sizeof(struct smu_11_0_power_context); + smu_power->power_context_size = size; diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c --- a/drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c +++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c + msg_map(setfastpptlimit, ppsmc_msg_setfastpptlimit, 0), + msg_map(setslowpptlimit, ppsmc_msg_setslowpptlimit, 0), + msg_map(getfastpptlimit, ppsmc_msg_getfastpptlimit, 0), + msg_map(getslowpptlimit, ppsmc_msg_getslowpptlimit, 0), +static int vangogh_get_power_limit(struct smu_context *smu) +{ + struct smu_11_5_power_context *power_context = + smu->smu_power.power_context; + uint32_t ppt_limit; + int ret = 0; + + if (smu->adev->pm.fw_version < 0x43f1e00) + return ret; + + ret = smu_cmn_send_smc_msg(smu, smu_msg_getslowpptlimit, &ppt_limit); + if (ret) { + dev_err(smu->adev->dev, "get slow ppt limit failed! "); + return ret; + } + /* convert from milliwatt to watt */ + smu->current_power_limit = ppt_limit / 1000; + smu->max_power_limit = 29; + + ret = smu_cmn_send_smc_msg(smu, smu_msg_getfastpptlimit, &ppt_limit); + if (ret) { + dev_err(smu->adev->dev, "get fast ppt limit failed! "); + return ret; + } + /* convert from milliwatt to watt */ + power_context->current_fast_ppt_limit = ppt_limit / 1000; + power_context->max_fast_ppt_limit = 30; + + return ret; +} + +static int vangogh_get_ppt_limit(struct smu_context *smu, + uint32_t *ppt_limit, + enum smu_ppt_limit_type type, + enum smu_ppt_limit_level level) +{ + struct smu_11_5_power_context *power_context = + smu->smu_power.power_context; + + if (!power_context) + return -eopnotsupp; + + if (type == smu_fast_ppt_limit) { + switch (level) { + case smu_ppt_limit_max: + *ppt_limit = power_context->max_fast_ppt_limit; + break; + case smu_ppt_limit_current: + *ppt_limit = power_context->current_fast_ppt_limit; + break; + default: + break; + } + } + + return 0; +} + +static int vangogh_set_power_limit(struct smu_context *smu, uint32_t ppt_limit) +{ + struct smu_11_5_power_context *power_context = + smu->smu_power.power_context; + uint32_t limit_type = ppt_limit >> 24; + int ret = 0; + + if (!smu_cmn_feature_is_enabled(smu, smu_feature_ppt_bit)) { + dev_err(smu->adev->dev, "setting new power limit is not supported! "); + return -eopnotsupp; + } + + switch (limit_type) { + case smu_default_ppt_limit: + ret = smu_cmn_send_smc_msg_with_param(smu, + smu_msg_setslowpptlimit, + ppt_limit * 1000, /* convert from watt to milliwatt */ + null); + if (ret) + return ret; + + smu->current_power_limit = ppt_limit; + break; + case smu_fast_ppt_limit: + ppt_limit &= ~(smu_fast_ppt_limit << 24); + if (ppt_limit > power_context->max_fast_ppt_limit) { + dev_err(smu->adev->dev, + "new power limit (%d) is over the max allowed %d ", + ppt_limit, power_context->max_fast_ppt_limit); + return ret; + } + + ret = smu_cmn_send_smc_msg_with_param(smu, + smu_msg_setfastpptlimit, + ppt_limit * 1000, /* convert from watt to milliwatt */ + null); + if (ret) + return ret; + + power_context->current_fast_ppt_limit = ppt_limit; + break; + default: + return -einval; + } + + return ret; +} + + .get_ppt_limit = vangogh_get_ppt_limit, + .get_power_limit = vangogh_get_power_limit, + .set_power_limit = vangogh_set_power_limit,
|
Graphics
|
ae07970a0621d67a8bc0dc5b44e3fc652bd2ba20
|
xiaomeng hou
|
drivers
|
gpu
|
amd, drm, inc, pm, smu11, swsmu
|
drm/amd/pm: add two new sysfs nodes for vangogh
|
this patch is to add two new sysfs nodes for vangogh: pp_dpm_dclk and pp_dpm_vclk. the two sysfs nodes are similar to pp_dpm_fclk/memclk/socclk. pp_dpm_dclk represents the dpm frequency of dcn unit. pp_dpm_vclk represents the dpm frequency of vcn unit.
|
this release allows to map an uid to a different one in a mount; it also adds support for selecting the preemption model at runtime; support for a low-overhead memory error detector designed to be used in production; support for the acrn hypervisor designed for embedded systems; btrfs initial support for zoned devices, subpage blocks sizes and performance improvements; support for eager nfs writes; support for a thermal power management to control the surface temperature of embedded devices in an unified way; the napi polling can be moved to a kernel thread; and support for non-blocking path lookups. as always, there are many other features, new drivers, improvements and fixes.
|
add two new sysfs nodes for vangogh
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'cryptography', 'security', 'networking', 'architectures x86 arm risc-v powerpc mips csky s390 pa-risc c6x']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'cpu frequency scaling', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'cryptography hardware acceleration', 'pci', 'non-transparent bridge (ntb)', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'cxl (compute express link)', 'various']
|
['amdgpu ']
|
['c']
| 1
| 140
| 0
|
--- diff --git a/drivers/gpu/drm/amd/pm/amdgpu_pm.c b/drivers/gpu/drm/amd/pm/amdgpu_pm.c --- a/drivers/gpu/drm/amd/pm/amdgpu_pm.c +++ b/drivers/gpu/drm/amd/pm/amdgpu_pm.c +static ssize_t amdgpu_get_pp_dpm_vclk(struct device *dev, + struct device_attribute *attr, + char *buf) +{ + struct drm_device *ddev = dev_get_drvdata(dev); + struct amdgpu_device *adev = drm_to_adev(ddev); + ssize_t size; + int ret; + + if (amdgpu_in_reset(adev)) + return -eperm; + + ret = pm_runtime_get_sync(ddev->dev); + if (ret < 0) { + pm_runtime_put_autosuspend(ddev->dev); + return ret; + } + + if (is_support_sw_smu(adev)) + size = smu_print_clk_levels(&adev->smu, smu_vclk, buf); + else + size = snprintf(buf, page_size, " "); + + pm_runtime_mark_last_busy(ddev->dev); + pm_runtime_put_autosuspend(ddev->dev); + + return size; +} + +static ssize_t amdgpu_set_pp_dpm_vclk(struct device *dev, + struct device_attribute *attr, + const char *buf, + size_t count) +{ + struct drm_device *ddev = dev_get_drvdata(dev); + struct amdgpu_device *adev = drm_to_adev(ddev); + int ret; + uint32_t mask = 0; + + if (amdgpu_in_reset(adev)) + return -eperm; + + ret = amdgpu_read_mask(buf, count, &mask); + if (ret) + return ret; + + ret = pm_runtime_get_sync(ddev->dev); + if (ret < 0) { + pm_runtime_put_autosuspend(ddev->dev); + return ret; + } + + if (is_support_sw_smu(adev)) + ret = smu_force_clk_levels(&adev->smu, smu_vclk, mask); + else + ret = 0; + + pm_runtime_mark_last_busy(ddev->dev); + pm_runtime_put_autosuspend(ddev->dev); + + if (ret) + return -einval; + + return count; +} + +static ssize_t amdgpu_get_pp_dpm_dclk(struct device *dev, + struct device_attribute *attr, + char *buf) +{ + struct drm_device *ddev = dev_get_drvdata(dev); + struct amdgpu_device *adev = drm_to_adev(ddev); + ssize_t size; + int ret; + + if (amdgpu_in_reset(adev)) + return -eperm; + + ret = pm_runtime_get_sync(ddev->dev); + if (ret < 0) { + pm_runtime_put_autosuspend(ddev->dev); + return ret; + } + + if (is_support_sw_smu(adev)) + size = smu_print_clk_levels(&adev->smu, smu_dclk, buf); + else + size = snprintf(buf, page_size, " "); + + pm_runtime_mark_last_busy(ddev->dev); + pm_runtime_put_autosuspend(ddev->dev); + + return size; +} + +static ssize_t amdgpu_set_pp_dpm_dclk(struct device *dev, + struct device_attribute *attr, + const char *buf, + size_t count) +{ + struct drm_device *ddev = dev_get_drvdata(dev); + struct amdgpu_device *adev = drm_to_adev(ddev); + int ret; + uint32_t mask = 0; + + if (amdgpu_in_reset(adev)) + return -eperm; + + ret = amdgpu_read_mask(buf, count, &mask); + if (ret) + return ret; + + ret = pm_runtime_get_sync(ddev->dev); + if (ret < 0) { + pm_runtime_put_autosuspend(ddev->dev); + return ret; + } + + if (is_support_sw_smu(adev)) + ret = smu_force_clk_levels(&adev->smu, smu_dclk, mask); + else + ret = 0; + + pm_runtime_mark_last_busy(ddev->dev); + pm_runtime_put_autosuspend(ddev->dev); + + if (ret) + return -einval; + + return count; +} + + amdgpu_device_attr_rw(pp_dpm_vclk, attr_flag_basic|attr_flag_onevf), + amdgpu_device_attr_rw(pp_dpm_dclk, attr_flag_basic|attr_flag_onevf), + } else if (device_attr_is(pp_dpm_vclk)) { + if (!(asic_type == chip_vangogh)) + *states = attr_state_unsupported; + } else if (device_attr_is(pp_dpm_dclk)) { + if (!(asic_type == chip_vangogh)) + *states = attr_state_unsupported;
|
Graphics
|
9577b0ec2be8410b94e9928f25b740b55de2c13d
|
xiaojian du evan quan evan quan amd com
|
drivers
|
gpu
|
amd, drm, pm
|
drm/amdgpu/nv: add pci reset support
|
use generic pci reset for gpu reset if the user specifies pci reset as the reset mechanism. this should in general only be used for validation.
|
this release allows to map an uid to a different one in a mount; it also adds support for selecting the preemption model at runtime; support for a low-overhead memory error detector designed to be used in production; support for the acrn hypervisor designed for embedded systems; btrfs initial support for zoned devices, subpage blocks sizes and performance improvements; support for eager nfs writes; support for a thermal power management to control the surface temperature of embedded devices in an unified way; the napi polling can be moved to a kernel thread; and support for non-blocking path lookups. as always, there are many other features, new drivers, improvements and fixes.
|
add pci reset support for several models
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'cryptography', 'security', 'networking', 'architectures x86 arm risc-v powerpc mips csky s390 pa-risc c6x']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'cpu frequency scaling', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'cryptography hardware acceleration', 'pci', 'non-transparent bridge (ntb)', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'cxl (compute express link)', 'various']
|
['amdgpu ']
|
['c']
| 1
| 6
| 1
|
--- diff --git a/drivers/gpu/drm/amd/amdgpu/nv.c b/drivers/gpu/drm/amd/amdgpu/nv.c --- a/drivers/gpu/drm/amd/amdgpu/nv.c +++ b/drivers/gpu/drm/amd/amdgpu/nv.c - amdgpu_reset_method == amd_reset_method_baco) + amdgpu_reset_method == amd_reset_method_baco || + amdgpu_reset_method == amd_reset_method_pci) + case amd_reset_method_pci: + dev_info(adev->dev, "pci reset "); + ret = amdgpu_device_pci_reset(adev); + break;
|
Graphics
|
f172865a3632b85f29c2af9b044f4dd51581740f
|
alex deucher evan quan evan quan amd com
|
drivers
|
gpu
|
amd, amdgpu, drm
|
drm/amdgpu/soc15: add pci reset support
|
use generic pci reset for gpu reset if the user specifies pci reset as the reset mechanism. this should in general only be used for validation.
|
this release allows to map an uid to a different one in a mount; it also adds support for selecting the preemption model at runtime; support for a low-overhead memory error detector designed to be used in production; support for the acrn hypervisor designed for embedded systems; btrfs initial support for zoned devices, subpage blocks sizes and performance improvements; support for eager nfs writes; support for a thermal power management to control the surface temperature of embedded devices in an unified way; the napi polling can be moved to a kernel thread; and support for non-blocking path lookups. as always, there are many other features, new drivers, improvements and fixes.
|
add pci reset support for several models
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'cryptography', 'security', 'networking', 'architectures x86 arm risc-v powerpc mips csky s390 pa-risc c6x']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'cpu frequency scaling', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'cryptography hardware acceleration', 'pci', 'non-transparent bridge (ntb)', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'cxl (compute express link)', 'various']
|
['amdgpu ']
|
['c']
| 1
| 14
| 10
|
--- diff --git a/drivers/gpu/drm/amd/amdgpu/soc15.c b/drivers/gpu/drm/amd/amdgpu/soc15.c --- a/drivers/gpu/drm/amd/amdgpu/soc15.c +++ b/drivers/gpu/drm/amd/amdgpu/soc15.c - amdgpu_reset_method == amd_reset_method_baco) + amdgpu_reset_method == amd_reset_method_baco || + amdgpu_reset_method == amd_reset_method_pci) - case amd_reset_method_baco: - dev_info(adev->dev, "baco reset "); - return soc15_asic_baco_reset(adev); - case amd_reset_method_mode2: - dev_info(adev->dev, "mode2 reset "); - return amdgpu_dpm_mode2_reset(adev); - default: - dev_info(adev->dev, "mode1 reset "); - return soc15_asic_mode1_reset(adev); + case amd_reset_method_pci: + dev_info(adev->dev, "pci reset "); + return amdgpu_device_pci_reset(adev); + case amd_reset_method_baco: + dev_info(adev->dev, "baco reset "); + return soc15_asic_baco_reset(adev); + case amd_reset_method_mode2: + dev_info(adev->dev, "mode2 reset "); + return amdgpu_dpm_mode2_reset(adev); + default: + dev_info(adev->dev, "mode1 reset "); + return soc15_asic_mode1_reset(adev);
|
Graphics
|
1176a1e0b9d50255d733a1e04c039405a3ab5948
|
alex deucher evan quan evan quan amd com
|
drivers
|
gpu
|
amd, amdgpu, drm
|
drm/amdgpu/si: add pci reset support
|
use generic pci reset for gpu reset if the user specifies pci reset as the reset mechanism. this should in general only be used for validation.
|
this release allows to map an uid to a different one in a mount; it also adds support for selecting the preemption model at runtime; support for a low-overhead memory error detector designed to be used in production; support for the acrn hypervisor designed for embedded systems; btrfs initial support for zoned devices, subpage blocks sizes and performance improvements; support for eager nfs writes; support for a thermal power management to control the surface temperature of embedded devices in an unified way; the napi polling can be moved to a kernel thread; and support for non-blocking path lookups. as always, there are many other features, new drivers, improvements and fixes.
|
add pci reset support for several models
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'cryptography', 'security', 'networking', 'architectures x86 arm risc-v powerpc mips csky s390 pa-risc c6x']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'cpu frequency scaling', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'cryptography hardware acceleration', 'pci', 'non-transparent bridge (ntb)', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'cxl (compute express link)', 'various']
|
['amdgpu ']
|
['c']
| 1
| 23
| 14
|
--- diff --git a/drivers/gpu/drm/amd/amdgpu/si.c b/drivers/gpu/drm/amd/amdgpu/si.c --- a/drivers/gpu/drm/amd/amdgpu/si.c +++ b/drivers/gpu/drm/amd/amdgpu/si.c -static int si_asic_reset(struct amdgpu_device *adev) -{ - int r; - - dev_info(adev->dev, "pci config reset "); - - r = si_gpu_pci_config_reset(adev); - - return r; -} - - if (amdgpu_reset_method != amd_reset_method_legacy && - amdgpu_reset_method != -1) + if (amdgpu_reset_method == amd_reset_method_pci) + return amdgpu_reset_method; + else if (amdgpu_reset_method != amd_reset_method_legacy && + amdgpu_reset_method != -1) - amdgpu_reset_method); + amdgpu_reset_method); +static int si_asic_reset(struct amdgpu_device *adev) +{ + int r; + + switch (si_asic_reset_method(adev)) { + case amd_reset_method_pci: + dev_info(adev->dev, "pci reset "); + r = amdgpu_device_pci_reset(adev); + break; + default: + dev_info(adev->dev, "pci config reset "); + r = si_gpu_pci_config_reset(adev); + break; + } + + return r; +} +
|
Graphics
|
ffbfd081b47cf4b23dc6e2923534ad8984fe6ec6
|
alex deucher evan quan evan quan amd com
|
drivers
|
gpu
|
amd, amdgpu, drm
|
drm/amdgpu: add secure display ta header file
|
add file ta_securedisplay_if.h for secure display ta
|
this release allows to map an uid to a different one in a mount; it also adds support for selecting the preemption model at runtime; support for a low-overhead memory error detector designed to be used in production; support for the acrn hypervisor designed for embedded systems; btrfs initial support for zoned devices, subpage blocks sizes and performance improvements; support for eager nfs writes; support for a thermal power management to control the surface temperature of embedded devices in an unified way; the napi polling can be moved to a kernel thread; and support for non-blocking path lookups. as always, there are many other features, new drivers, improvements and fixes.
|
add secure display ta interface
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'cryptography', 'security', 'networking', 'architectures x86 arm risc-v powerpc mips csky s390 pa-risc c6x']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'cpu frequency scaling', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'cryptography hardware acceleration', 'pci', 'non-transparent bridge (ntb)', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'cxl (compute express link)', 'various']
|
['amdgpu ']
|
['h']
| 1
| 154
| 0
|
--- diff --git a/drivers/gpu/drm/amd/amdgpu/ta_securedisplay_if.h b/drivers/gpu/drm/amd/amdgpu/ta_securedisplay_if.h --- /dev/null +++ b/drivers/gpu/drm/amd/amdgpu/ta_securedisplay_if.h +/* + * copyright 2019 advanced micro devices, inc. + * + * permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "software"), + * to deal in the software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the software, and to permit persons to whom the + * software is furnished to do so, subject to the following conditions: + * + * the above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the software. + * + * the software is provided "as is", without warranty of any kind, express or + * implied, including but not limited to the warranties of merchantability, + * fitness for a particular purpose and noninfringement. in no event shall + * the copyright holder(s) or author(s) be liable for any claim, damages or + * other liability, whether in an action of contract, tort or otherwise, + * arising from, out of or in connection with the software or the use or + * other dealings in the software. + * + */ + +#ifndef _ta_securedisplay_if_h +#define _ta_securedisplay_if_h + +/** secure display related enumerations */ +/**********************************************************/ + +/** @enum ta_securedisplay_command + * secure display command id + */ +enum ta_securedisplay_command { + /* query whether ta is responding used only for validation purpose */ + ta_securedisplay_command__query_ta = 1, + /* send region of interest and crc value to i2c */ + ta_securedisplay_command__send_roi_crc = 2, + /* maximum command id */ + ta_securedisplay_command__max_id = 0x7fffffff, +}; + +/** @enum ta_securedisplay_status + * secure display status returns in shared buffer status + */ +enum ta_securedisplay_status { + ta_securedisplay_status__success = 0x00, /* success */ + ta_securedisplay_status__generic_failure = 0x01, /* generic failure */ + ta_securedisplay_status__invalid_parameter = 0x02, /* invalid parameter */ + ta_securedisplay_status__null_pointer = 0x03, /* null pointer*/ + ta_securedisplay_status__i2c_write_error = 0x04, /* fail to write to i2c */ + ta_securedisplay_status__read_dio_scratch_error = 0x05, /*fail read dio scratch register*/ + ta_securedisplay_status__read_crc_error = 0x06, /* fail to read crc*/ + + ta_securedisplay_status__max = 0x7fffffff,/* maximum value for status*/ +}; + +/** @enum ta_securedisplay_max_phy + * physical id number to use for reading corresponding dio scratch register for roi + */ +enum ta_securedisplay_max_phy { + ta_securedisplay_phy0 = 0, + ta_securedisplay_phy1 = 1, + ta_securedisplay_phy2 = 2, + ta_securedisplay_phy3 = 3, + ta_securedisplay_max_phy = 4, +}; + +/** @enum ta_securedisplay_ta_query_cmd_ret + * a predefined specific reteurn value which is 0xab only used to validate + * communication to secure display ta is functional. + * this value is used to validate whether ta is responding successfully + */ +enum ta_securedisplay_ta_query_cmd_ret { + /* this is a value to validate if ta is loaded successfully */ + ta_securedisplay_query_cmd_ret = 0xab, +}; + +/** @enum ta_securedisplay_buffer_size + * i2c buffer size which contains 8 bytes of roi (x start, x end, y start, y end) + * and 6 bytes of crc( r,g,b) and 1 byte for physical id + */ +enum ta_securedisplay_buffer_size { + /* 15 bytes = 8 byte (roi) + 6 byte(crc) + 1 byte(phy_id) */ + ta_securedisplay_i2c_buffer_size = 15, +}; + +/** input/output structures for secure display commands */ +/**********************************************************/ +/** + * input structures + */ + +/** @struct ta_securedisplay_send_roi_crc_input + * physical id to determine which dio scratch register should be used to get roi + */ +struct ta_securedisplay_send_roi_crc_input { + uint32_t phy_id; /* physical id */ +}; + +/** @union ta_securedisplay_cmd_input + * input buffer + */ +union ta_securedisplay_cmd_input { + /* send roi and crc input buffer format */ + struct ta_securedisplay_send_roi_crc_input send_roi_crc; + uint32_t reserved[4]; +}; + +/** + * output structures + */ + +/** @struct ta_securedisplay_query_ta_output + * output buffer format for query ta whether ta is responding used only for validation purpose + */ +struct ta_securedisplay_query_ta_output { + /* return value from ta when it is queried for validation purpose only */ + uint32_t query_cmd_ret; +}; + +/** @struct ta_securedisplay_send_roi_crc_output + * output buffer format for send roi crc command which will pass i2c buffer created inside ta + * and used to write to i2c used only for validation purpose + */ +struct ta_securedisplay_send_roi_crc_output { + uint8_t i2c_buf[ta_securedisplay_i2c_buffer_size]; /* i2c buffer */ + uint8_t reserved; +}; + +/** @union ta_securedisplay_cmd_output + * output buffer + */ +union ta_securedisplay_cmd_output { + /* query ta output buffer format used only for validation purpose*/ + struct ta_securedisplay_query_ta_output query_ta; + /* send roi crc output buffer format used only for validation purpose */ + struct ta_securedisplay_send_roi_crc_output send_roi_crc; + uint32_t reserved[4]; +}; + +/** @struct securedisplay_cmd + * secure display command which is shared buffer memory + */ +struct securedisplay_cmd { + uint32_t cmd_id; /* +0 bytes command id */ + enum ta_securedisplay_status status; /* +4 bytes status of secure display ta */ + uint32_t reserved[2]; /* +8 bytes reserved */ + union ta_securedisplay_cmd_input securedisplay_in_message; /* +16 bytes input buffer */ + union ta_securedisplay_cmd_output securedisplay_out_message;/* +32 bytes output buffer */ + /**@note total 48 bytes */ +}; + +#endif //_ta_securedisplay_if_h +
|
Graphics
|
a944c12724b7ba774126d87d5d9c7f6ef179e237
|
jinzhou su huang rui ray huang amd com alex deucher alexander deucher amd com
|
drivers
|
gpu
|
amd, amdgpu, drm
|
drm/amdgpu: add secure display ta interface
|
add interface to load, unload, invoke command for secure display ta.
|
this release allows to map an uid to a different one in a mount; it also adds support for selecting the preemption model at runtime; support for a low-overhead memory error detector designed to be used in production; support for the acrn hypervisor designed for embedded systems; btrfs initial support for zoned devices, subpage blocks sizes and performance improvements; support for eager nfs writes; support for a thermal power management to control the surface temperature of embedded devices in an unified way; the napi polling can be moved to a kernel thread; and support for non-blocking path lookups. as always, there are many other features, new drivers, improvements and fixes.
|
add secure display ta interface
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'cryptography', 'security', 'networking', 'architectures x86 arm risc-v powerpc mips csky s390 pa-risc c6x']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'cpu frequency scaling', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'cryptography hardware acceleration', 'pci', 'non-transparent bridge (ntb)', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'cxl (compute express link)', 'various']
|
['amdgpu ']
|
['h', 'c', 'makefile']
| 8
| 438
| 3
|
--- diff --git a/drivers/gpu/drm/amd/amdgpu/makefile b/drivers/gpu/drm/amd/amdgpu/makefile --- a/drivers/gpu/drm/amd/amdgpu/makefile +++ b/drivers/gpu/drm/amd/amdgpu/makefile - amdgpu_fw_attestation.o + amdgpu_fw_attestation.o amdgpu_securedisplay.o diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c +#include "amdgpu_securedisplay.h" + amdgpu_securedisplay_debugfs_init(adev); + diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c +#include "amdgpu_securedisplay.h" +/* securedisplay start */ +static int psp_securedisplay_init_shared_buf(struct psp_context *psp) +{ + int ret; + + /* + * allocate 16k memory aligned to 4k from frame buffer (local + * physical) for sa ta <-> driver + */ + ret = amdgpu_bo_create_kernel(psp->adev, psp_securedisplay_shared_mem_size, + page_size, amdgpu_gem_domain_vram, + &psp->securedisplay_context.securedisplay_shared_bo, + &psp->securedisplay_context.securedisplay_shared_mc_addr, + &psp->securedisplay_context.securedisplay_shared_buf); + + return ret; +} + +static int psp_securedisplay_load(struct psp_context *psp) +{ + int ret; + struct psp_gfx_cmd_resp *cmd; + + cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), gfp_kernel); + if (!cmd) + return -enomem; + + memset(psp->fw_pri_buf, 0, psp_1_meg); + memcpy(psp->fw_pri_buf, psp->ta_securedisplay_start_addr, psp->ta_securedisplay_ucode_size); + + psp_prep_ta_load_cmd_buf(cmd, + psp->fw_pri_mc_addr, + psp->ta_securedisplay_ucode_size, + psp->securedisplay_context.securedisplay_shared_mc_addr, + psp_securedisplay_shared_mem_size); + + ret = psp_cmd_submit_buf(psp, null, cmd, psp->fence_buf_mc_addr); + + if (ret) + goto failed; + + psp->securedisplay_context.securedisplay_initialized = true; + psp->securedisplay_context.session_id = cmd->resp.session_id; + mutex_init(&psp->securedisplay_context.mutex); + +failed: + kfree(cmd); + return ret; +} + +static int psp_securedisplay_unload(struct psp_context *psp) +{ + int ret; + struct psp_gfx_cmd_resp *cmd; + + cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), gfp_kernel); + if (!cmd) + return -enomem; + + psp_prep_ta_unload_cmd_buf(cmd, psp->securedisplay_context.session_id); + + ret = psp_cmd_submit_buf(psp, null, cmd, psp->fence_buf_mc_addr); + + kfree(cmd); + + return ret; +} + +static int psp_securedisplay_initialize(struct psp_context *psp) +{ + int ret; + struct securedisplay_cmd *securedisplay_cmd; + + /* + * todo: bypass the initialize in sriov for now + */ + if (amdgpu_sriov_vf(psp->adev)) + return 0; + + if (!psp->adev->psp.ta_securedisplay_ucode_size || + !psp->adev->psp.ta_securedisplay_start_addr) { + dev_info(psp->adev->dev, "securedisplay: securedisplay ta ucode is not available "); + return 0; + } + + if (!psp->securedisplay_context.securedisplay_initialized) { + ret = psp_securedisplay_init_shared_buf(psp); + if (ret) + return ret; + } + + ret = psp_securedisplay_load(psp); + if (ret) + return ret; + + psp_prep_securedisplay_cmd_buf(psp, &securedisplay_cmd, + ta_securedisplay_command__query_ta); + + ret = psp_securedisplay_invoke(psp, ta_securedisplay_command__query_ta); + if (ret) { + psp_securedisplay_unload(psp); + + amdgpu_bo_free_kernel(&psp->securedisplay_context.securedisplay_shared_bo, + &psp->securedisplay_context.securedisplay_shared_mc_addr, + &psp->securedisplay_context.securedisplay_shared_buf); + + psp->securedisplay_context.securedisplay_initialized = false; + + dev_err(psp->adev->dev, "securedisplay ta initialize fail. "); + return -einval; + } + + if (securedisplay_cmd->status != ta_securedisplay_status__success) { + psp_securedisplay_parse_resp_status(psp, securedisplay_cmd->status); + dev_err(psp->adev->dev, "securedisplay: query securedisplay ta failed. ret 0x%x ", + securedisplay_cmd->securedisplay_out_message.query_ta.query_cmd_ret); + } + + return 0; +} + +static int psp_securedisplay_terminate(struct psp_context *psp) +{ + int ret; + + /* + * todo:bypass the terminate in sriov for now + */ + if (amdgpu_sriov_vf(psp->adev)) + return 0; + + if (!psp->securedisplay_context.securedisplay_initialized) + return 0; + + ret = psp_securedisplay_unload(psp); + if (ret) + return ret; + + psp->securedisplay_context.securedisplay_initialized = false; + + /* free securedisplay shared memory */ + amdgpu_bo_free_kernel(&psp->securedisplay_context.securedisplay_shared_bo, + &psp->securedisplay_context.securedisplay_shared_mc_addr, + &psp->securedisplay_context.securedisplay_shared_buf); + + return ret; +} + +int psp_securedisplay_invoke(struct psp_context *psp, uint32_t ta_cmd_id) +{ + int ret; + + if (!psp->securedisplay_context.securedisplay_initialized) + return -einval; + + if (ta_cmd_id != ta_securedisplay_command__query_ta && + ta_cmd_id != ta_securedisplay_command__send_roi_crc) + return -einval; + + mutex_lock(&psp->securedisplay_context.mutex); + + ret = psp_ta_invoke(psp, ta_cmd_id, psp->securedisplay_context.session_id); + + mutex_unlock(&psp->securedisplay_context.mutex); + + return ret; +} +/* securedisplay end */ + + + ret = psp_securedisplay_initialize(psp); + if (ret) + dev_err(psp->adev->dev, + "securedisplay: failed to initialize securedisplay "); + psp_securedisplay_terminate(psp); + ret = psp_securedisplay_terminate(psp); + if (ret) { + drm_error("failed to terminate securedisplay ta "); + return ret; + } + + ret = psp_securedisplay_initialize(psp); + if (ret) + dev_err(psp->adev->dev, + "securedisplay: failed to initialize securedisplay "); + case ta_fw_type_psp_securedisplay: + psp->ta_securedisplay_ucode_version = le32_to_cpu(desc->fw_version); + psp->ta_securedisplay_ucode_size = le32_to_cpu(desc->size_bytes); + psp->ta_securedisplay_start_addr = ucode_start_addr; + break; diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h +#include "ta_securedisplay_if.h" +#define psp_securedisplay_shared_mem_size 0x4000 +struct psp_securedisplay_context { + bool securedisplay_initialized; + uint32_t session_id; + struct amdgpu_bo *securedisplay_shared_bo; + uint64_t securedisplay_shared_mc_addr; + void *securedisplay_shared_buf; + struct mutex mutex; +}; + + uint32_t ta_securedisplay_ucode_version; + uint32_t ta_securedisplay_ucode_size; + uint8_t *ta_securedisplay_start_addr; + + struct psp_securedisplay_context securedisplay_context; +int psp_securedisplay_invoke(struct psp_context *psp, uint32_t ta_cmd_id); diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_securedisplay.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_securedisplay.c --- /dev/null +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_securedisplay.c +/* + * copyright 2021 advanced micro devices, inc. + * + * permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "software"), + * to deal in the software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the software, and to permit persons to whom the + * software is furnished to do so, subject to the following conditions: + * + * the above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the software. + * + * the software is provided "as is", without warranty of any kind, express or + * implied, including but not limited to the warranties of merchantability, + * fitness for a particular purpose and noninfringement. in no event shall + * the copyright holder(s) or author(s) be liable for any claim, damages or + * other liability, whether in an action of contract, tort or otherwise, + * arising from, out of or in connection with the software or the use or + * other dealings in the software. + * + * + */ +#include <linux/debugfs.h> +#include <linux/pm_runtime.h> + +#include "amdgpu.h" +#include "amdgpu_securedisplay.h" + +/** + * doc: amdgpu securedisplay debugfs test interface + * + * how to use? + * echo opcode <value> > <debugfs_dir>/dri/xxx/securedisplay_test + * eg. echo 1 > <debugfs_dir>/dri/xxx/securedisplay_test + * eg. echo 2 phy_id > <debugfs_dir>/dri/xxx/securedisplay_test + * + * opcode: + * 1:query whether ta is responding used only for validation pupose + * 2: send region of interest and crc value to i2c. (uint32)phy_id is + * send to determine which dio scratch register should be used to get + * roi and receive i2c_buf as the output. + * + * you can refer more detail from header file ta_securedisplay_if.h + * + */ + +void psp_securedisplay_parse_resp_status(struct psp_context *psp, + enum ta_securedisplay_status status) +{ + switch (status) { + case ta_securedisplay_status__success: + break; + case ta_securedisplay_status__generic_failure: + dev_err(psp->adev->dev, "secure display: generic failure."); + break; + case ta_securedisplay_status__invalid_parameter: + dev_err(psp->adev->dev, "secure display: invalid parameter."); + break; + case ta_securedisplay_status__null_pointer: + dev_err(psp->adev->dev, "secure display: null pointer."); + break; + case ta_securedisplay_status__i2c_write_error: + dev_err(psp->adev->dev, "secure display: failed to write to i2c."); + break; + case ta_securedisplay_status__read_dio_scratch_error: + dev_err(psp->adev->dev, "secure display: failed to read dio scratch register."); + break; + case ta_securedisplay_status__read_crc_error: + dev_err(psp->adev->dev, "secure display: failed to read crc"); + break; + default: + dev_err(psp->adev->dev, "secure display: failed to parse status: %d ", status); + } +} + +void psp_prep_securedisplay_cmd_buf(struct psp_context *psp, struct securedisplay_cmd **cmd, + enum ta_securedisplay_command command_id) +{ + *cmd = (struct securedisplay_cmd *)psp->securedisplay_context.securedisplay_shared_buf; + memset(*cmd, 0, sizeof(struct securedisplay_cmd)); + (*cmd)->status = ta_securedisplay_status__generic_failure; + (*cmd)->cmd_id = command_id; +} + +static ssize_t amdgpu_securedisplay_debugfs_write(struct file *f, const char __user *buf, + size_t size, loff_t *pos) +{ + struct amdgpu_device *adev = (struct amdgpu_device *)file_inode(f)->i_private; + struct psp_context *psp = &adev->psp; + struct securedisplay_cmd *securedisplay_cmd; + struct drm_device *dev = adev_to_drm(adev); + uint32_t phy_id; + uint32_t op; + int i; + char str[64]; + char i2c_output[256]; + int ret; + + if (*pos || size > sizeof(str) - 1) + return -einval; + + memset(str, 0, sizeof(str)); + ret = copy_from_user(str, buf, size); + if (ret) + return -efault; + + ret = pm_runtime_get_sync(dev->dev); + if (ret < 0) { + pm_runtime_put_autosuspend(dev->dev); + return ret; + } + + if (size < 3) + sscanf(str, "%u ", &op); + else + sscanf(str, "%u %u", &op, &phy_id); + + switch (op) { + case 1: + psp_prep_securedisplay_cmd_buf(psp, &securedisplay_cmd, + ta_securedisplay_command__query_ta); + ret = psp_securedisplay_invoke(psp, ta_securedisplay_command__query_ta); + if (!ret) { + if (securedisplay_cmd->status == ta_securedisplay_status__success) + dev_info(adev->dev, "securedisplay: query securedisplay ta ret is 0x%x ", + securedisplay_cmd->securedisplay_out_message.query_ta.query_cmd_ret); + else + psp_securedisplay_parse_resp_status(psp, securedisplay_cmd->status); + } + break; + case 2: + psp_prep_securedisplay_cmd_buf(psp, &securedisplay_cmd, + ta_securedisplay_command__send_roi_crc); + securedisplay_cmd->securedisplay_in_message.send_roi_crc.phy_id = phy_id; + ret = psp_securedisplay_invoke(psp, ta_securedisplay_command__send_roi_crc); + if (!ret) { + if (securedisplay_cmd->status == ta_securedisplay_status__success) { + memset(i2c_output, 0, sizeof(i2c_output)); + for (i = 0; i < ta_securedisplay_i2c_buffer_size; i++) + sprintf(i2c_output, "%s 0x%x", i2c_output, + securedisplay_cmd->securedisplay_out_message.send_roi_crc.i2c_buf[i]); + dev_info(adev->dev, "securedisplay: i2c buffer out put is :%s ", i2c_output); + } else { + psp_securedisplay_parse_resp_status(psp, securedisplay_cmd->status); + } + } + break; + default: + dev_err(adev->dev, "invalid input: %s ", str); + } + + pm_runtime_mark_last_busy(dev->dev); + pm_runtime_put_autosuspend(dev->dev); + + return size; +} + +static const struct file_operations amdgpu_securedisplay_debugfs_ops = { + .owner = this_module, + .read = null, + .write = amdgpu_securedisplay_debugfs_write, + .llseek = default_llseek +}; + +void amdgpu_securedisplay_debugfs_init(struct amdgpu_device *adev) +{ +#if defined(config_debug_fs) + + if (!adev->psp.securedisplay_context.securedisplay_initialized) + return; + + debugfs_create_file("securedisplay_test", s_iwusr, adev_to_drm(adev)->primary->debugfs_root, + adev, &amdgpu_securedisplay_debugfs_ops); +#endif +} diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_securedisplay.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_securedisplay.h --- /dev/null +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_securedisplay.h +/* + * copyright 2021 advanced micro devices, inc. + * + * permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "software"), + * to deal in the software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the software, and to permit persons to whom the + * software is furnished to do so, subject to the following conditions: + * + * the above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the software. + * + * the software is provided "as is", without warranty of any kind, express or + * implied, including but not limited to the warranties of merchantability, + * fitness for a particular purpose and noninfringement. in no event shall + * the copyright holder(s) or author(s) be liable for any claim, damages or + * other liability, whether in an action of contract, tort or otherwise, + * arising from, out of or in connection with the software or the use or + * other dealings in the software. + * + * + */ +#ifndef _amdgpu_securedisplay_h +#define _amdgpu_securedisplay_h + +#include "amdgpu.h" +#include "ta_securedisplay_if.h" + +void amdgpu_securedisplay_debugfs_init(struct amdgpu_device *adev); +void psp_securedisplay_parse_resp_status(struct psp_context *psp, + enum ta_securedisplay_status status); +void psp_prep_securedisplay_cmd_buf(struct psp_context *psp, struct securedisplay_cmd **cmd, + enum ta_securedisplay_command command_id); + +#endif diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.h --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.h + uint32_t ta_securedisplay_ucode_version; + uint32_t ta_securedisplay_offset_bytes; + uint32_t ta_securedisplay_size_bytes; + ta_fw_type_psp_securedisplay, diff --git a/drivers/gpu/drm/amd/amdgpu/psp_v10_0.c b/drivers/gpu/drm/amd/amdgpu/psp_v10_0.c --- a/drivers/gpu/drm/amd/amdgpu/psp_v10_0.c +++ b/drivers/gpu/drm/amd/amdgpu/psp_v10_0.c - adev->psp.ta_fw_version = le32_to_cpu(ta_hdr->header.ucode_version); - + + adev->psp.ta_securedisplay_ucode_version = + le32_to_cpu(ta_hdr->ta_securedisplay_ucode_version); + adev->psp.ta_securedisplay_ucode_size = + le32_to_cpu(ta_hdr->ta_securedisplay_size_bytes); + adev->psp.ta_securedisplay_start_addr = + (uint8_t *)adev->psp.ta_hdcp_start_addr + + le32_to_cpu(ta_hdr->ta_securedisplay_offset_bytes); + + adev->psp.ta_fw_version = le32_to_cpu(ta_hdr->header.ucode_version);
|
Graphics
|
ecaafb7b5ab6406587341d8727f237b3ee00dedf
|
jinzhou su
|
drivers
|
gpu
|
amd, amdgpu, drm
|
drm/amdgpu: add green_sardine device id (v2)
|
add green_sardine pci id support and map it to renoir asic type.
|
this release allows to map an uid to a different one in a mount; it also adds support for selecting the preemption model at runtime; support for a low-overhead memory error detector designed to be used in production; support for the acrn hypervisor designed for embedded systems; btrfs initial support for zoned devices, subpage blocks sizes and performance improvements; support for eager nfs writes; support for a thermal power management to control the surface temperature of embedded devices in an unified way; the napi polling can be moved to a kernel thread; and support for non-blocking path lookups. as always, there are many other features, new drivers, improvements and fixes.
|
add green_sardine device id (v2)
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'cryptography', 'security', 'networking', 'architectures x86 arm risc-v powerpc mips csky s390 pa-risc c6x']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'cpu frequency scaling', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'cryptography hardware acceleration', 'pci', 'non-transparent bridge (ntb)', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'cxl (compute express link)', 'various']
|
['amdgpu ']
|
['c']
| 1
| 1
| 0
|
--- diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c + {0x1002, 0x1638, pci_any_id, pci_any_id, 0, 0, chip_renoir|amd_is_apu},
|
Graphics
|
8bf0835132c19437e1530621b730dd4f29fe938e
|
prike liang
|
drivers
|
gpu
|
amd, amdgpu, drm
|
amdgpu: add missing sienna cichlid did
|
the purpose of this patch is to add a missing device id for sienna cichlid. the missing id "0x73a1" is now added to the "amdgpu_drv.c" file.
|
this release allows to map an uid to a different one in a mount; it also adds support for selecting the preemption model at runtime; support for a low-overhead memory error detector designed to be used in production; support for the acrn hypervisor designed for embedded systems; btrfs initial support for zoned devices, subpage blocks sizes and performance improvements; support for eager nfs writes; support for a thermal power management to control the surface temperature of embedded devices in an unified way; the napi polling can be moved to a kernel thread; and support for non-blocking path lookups. as always, there are many other features, new drivers, improvements and fixes.
|
add missing sienna cichlid did
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'cryptography', 'security', 'networking', 'architectures x86 arm risc-v powerpc mips csky s390 pa-risc c6x']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'cpu frequency scaling', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'cryptography hardware acceleration', 'pci', 'non-transparent bridge (ntb)', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'cxl (compute express link)', 'various']
|
['amdgpu ']
|
['c']
| 1
| 1
| 0
|
--- diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c + {0x1002, 0x73a1, pci_any_id, pci_any_id, 0, 0, chip_sienna_cichlid},
|
Graphics
|
d26bbbcc160f6d9feabed73dca62b9e8b86671b4
|
ori messinger kent russell kent russell amd com
|
drivers
|
gpu
|
amd, amdgpu, drm
|
drm/amdgpu: add new device id for renior
|
add did 0x164c into pciidlist under chip_renoir family.
|
this release allows to map an uid to a different one in a mount; it also adds support for selecting the preemption model at runtime; support for a low-overhead memory error detector designed to be used in production; support for the acrn hypervisor designed for embedded systems; btrfs initial support for zoned devices, subpage blocks sizes and performance improvements; support for eager nfs writes; support for a thermal power management to control the surface temperature of embedded devices in an unified way; the napi polling can be moved to a kernel thread; and support for non-blocking path lookups. as always, there are many other features, new drivers, improvements and fixes.
|
add new device id for renior
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'cryptography', 'security', 'networking', 'architectures x86 arm risc-v powerpc mips csky s390 pa-risc c6x']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'cpu frequency scaling', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'cryptography hardware acceleration', 'pci', 'non-transparent bridge (ntb)', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'cxl (compute express link)', 'various']
|
['amdgpu ']
|
['c']
| 2
| 3
| 1
|
--- diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c + {0x1002, 0x164c, pci_any_id, pci_any_id, 0, 0, chip_renoir|amd_is_apu}, diff --git a/drivers/gpu/drm/amd/amdgpu/soc15.c b/drivers/gpu/drm/amd/amdgpu/soc15.c --- a/drivers/gpu/drm/amd/amdgpu/soc15.c +++ b/drivers/gpu/drm/amd/amdgpu/soc15.c - if (adev->pdev->device == 0x1636) + if ((adev->pdev->device == 0x1636) || + (adev->pdev->device == 0x164c))
|
Graphics
|
278cdb6834901658a81a1e22f5799aa15dca5029
|
mengwang huang rui ray huang amd com
|
drivers
|
gpu
|
amd, amdgpu, drm
|
drm/amdgpu: support aspm for some specific asic
|
support to program aspm and ltr for sienna cichlid and forward asic. disable aspm for sienna cichlid and forward asic by default.
|
this release allows to map an uid to a different one in a mount; it also adds support for selecting the preemption model at runtime; support for a low-overhead memory error detector designed to be used in production; support for the acrn hypervisor designed for embedded systems; btrfs initial support for zoned devices, subpage blocks sizes and performance improvements; support for eager nfs writes; support for a thermal power management to control the surface temperature of embedded devices in an unified way; the napi polling can be moved to a kernel thread; and support for non-blocking path lookups. as always, there are many other features, new drivers, improvements and fixes.
|
support aspm for some specific asic
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'cryptography', 'security', 'networking', 'architectures x86 arm risc-v powerpc mips csky s390 pa-risc c6x']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'cpu frequency scaling', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'cryptography hardware acceleration', 'pci', 'non-transparent bridge (ntb)', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'cxl (compute express link)', 'various']
|
['amdgpu ']
|
['h', 'c']
| 3
| 124
| 6
|
--- diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_nbio.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_nbio.h --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_nbio.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_nbio.h + void (*program_aspm)(struct amdgpu_device *adev); diff --git a/drivers/gpu/drm/amd/amdgpu/nbio_v2_3.c b/drivers/gpu/drm/amd/amdgpu/nbio_v2_3.c --- a/drivers/gpu/drm/amd/amdgpu/nbio_v2_3.c +++ b/drivers/gpu/drm/amd/amdgpu/nbio_v2_3.c +#define smnpcie_lc_cntl3 0x111402d4 +#define smnpcie_lc_cntl6 0x111402ec +#define smnpcie_lc_cntl7 0x111402f0 +#define smnbif_cfg_dev0_epf0_device_cntl2 0x1014008c +#define smnrcc_ep_dev0_0_ep_pcie_tx_ltr_cntl 0x10123538 +#define smnbif_cfg_dev0_epf0_pcie_ltr_cap 0x10140324 +#define smnpswusp0_pcie_lc_cntl2 0x111402c4 +#define smnnbif_mgcg_ctrl_lclk 0x1013a21c +static void nbio_v2_3_program_ltr(struct amdgpu_device *adev) +{ + uint32_t def, data; + + wreg32_pcie(smnrcc_ep_dev0_0_ep_pcie_tx_ltr_cntl, 0x75eb); + + def = data = rreg32_soc15(nbio, 0, mmrcc_bif_strap2); + data &= ~rcc_bif_strap2__strap_ltr_in_aspml1_dis_mask; + if (def != data) + wreg32_soc15(nbio, 0, mmrcc_bif_strap2, data); + + def = data = rreg32_pcie(smnrcc_ep_dev0_0_ep_pcie_tx_ltr_cntl); + data &= ~ep_pcie_tx_ltr_cntl__ltr_priv_msg_dis_in_pm_non_d0_mask; + if (def != data) + wreg32_pcie(smnrcc_ep_dev0_0_ep_pcie_tx_ltr_cntl, data); + + def = data = rreg32_pcie(smnbif_cfg_dev0_epf0_device_cntl2); + data |= bif_cfg_dev0_epf0_device_cntl2__ltr_en_mask; + if (def != data) + wreg32_pcie(smnbif_cfg_dev0_epf0_device_cntl2, data); +} + +static void nbio_v2_3_program_aspm(struct amdgpu_device *adev) +{ + uint32_t def, data; + + def = data = rreg32_pcie(smnpcie_lc_cntl); + data &= ~pcie_lc_cntl__lc_l1_inactivity_mask; + data &= ~pcie_lc_cntl__lc_l0s_inactivity_mask; + data |= pcie_lc_cntl__lc_pmi_to_l1_dis_mask; + if (def != data) + wreg32_pcie(smnpcie_lc_cntl, data); + + def = data = rreg32_pcie(smnpcie_lc_cntl7); + data |= pcie_lc_cntl7__lc_nbif_aspm_input_en_mask; + if (def != data) + wreg32_pcie(smnpcie_lc_cntl7, data); + + def = data = rreg32_pcie(smnnbif_mgcg_ctrl_lclk); + data |= nbif_mgcg_ctrl_lclk__nbif_mgcg_reg_dis_lclk_mask; + if (def != data) + wreg32_pcie(smnnbif_mgcg_ctrl_lclk, data); + + def = data = rreg32_pcie(smnpcie_lc_cntl3); + data |= pcie_lc_cntl3__lc_dsc_dont_enter_l23_after_pme_ack_mask; + if (def != data) + wreg32_pcie(smnpcie_lc_cntl3, data); + + def = data = rreg32_soc15(nbio, 0, mmrcc_bif_strap3); + data &= ~rcc_bif_strap3__strap_vlink_aspm_idle_timer_mask; + data &= ~rcc_bif_strap3__strap_vlink_pm_l1_entry_timer_mask; + if (def != data) + wreg32_soc15(nbio, 0, mmrcc_bif_strap3, data); + + def = data = rreg32_soc15(nbio, 0, mmrcc_bif_strap5); + data &= ~rcc_bif_strap5__strap_vlink_ldn_entry_timer_mask; + if (def != data) + wreg32_soc15(nbio, 0, mmrcc_bif_strap5, data); + + def = data = rreg32_pcie(smnbif_cfg_dev0_epf0_device_cntl2); + data &= ~bif_cfg_dev0_epf0_device_cntl2__ltr_en_mask; + if (def != data) + wreg32_pcie(smnbif_cfg_dev0_epf0_device_cntl2, data); + + wreg32_pcie(smnbif_cfg_dev0_epf0_pcie_ltr_cap, 0x10011001); + + def = data = rreg32_pcie(smnpswusp0_pcie_lc_cntl2); + data |= pswusp0_pcie_lc_cntl2__lc_allow_pdwn_in_l1_mask | + pswusp0_pcie_lc_cntl2__lc_allow_pdwn_in_l23_mask; + data &= ~pswusp0_pcie_lc_cntl2__lc_rcv_l0_to_rcv_l0s_dis_mask; + if (def != data) + wreg32_pcie(smnpswusp0_pcie_lc_cntl2, data); + + def = data = rreg32_pcie(smnpcie_lc_cntl6); + data |= pcie_lc_cntl6__lc_l1_powerdown_mask | + pcie_lc_cntl6__lc_rx_l0s_standby_en_mask; + if (def != data) + wreg32_pcie(smnpcie_lc_cntl6, data); + + nbio_v2_3_program_ltr(adev); + + def = data = rreg32_soc15(nbio, 0, mmrcc_bif_strap3); + data |= 0x5de0 << rcc_bif_strap3__strap_vlink_aspm_idle_timer__shift; + data |= 0x0010 << rcc_bif_strap3__strap_vlink_pm_l1_entry_timer__shift; + if (def != data) + wreg32_soc15(nbio, 0, mmrcc_bif_strap3, data); + + def = data = rreg32_soc15(nbio, 0, mmrcc_bif_strap5); + data |= 0x0010 << rcc_bif_strap5__strap_vlink_ldn_entry_timer__shift; + if (def != data) + wreg32_soc15(nbio, 0, mmrcc_bif_strap5, data); + + def = data = rreg32_pcie(smnpcie_lc_cntl); + data &= ~pcie_lc_cntl__lc_l0s_inactivity_mask; + data |= 0x9 << pcie_lc_cntl__lc_l1_inactivity__shift; + data |= 0x1 << pcie_lc_cntl__lc_pmi_to_l1_dis__shift; + if (def != data) + wreg32_pcie(smnpcie_lc_cntl, data); + + def = data = rreg32_pcie(smnpcie_lc_cntl3); + data &= ~pcie_lc_cntl3__lc_dsc_dont_enter_l23_after_pme_ack_mask; + if (def != data) + wreg32_pcie(smnpcie_lc_cntl3, data); +} + + .program_aspm = nbio_v2_3_program_aspm, diff --git a/drivers/gpu/drm/amd/amdgpu/nv.c b/drivers/gpu/drm/amd/amdgpu/nv.c --- a/drivers/gpu/drm/amd/amdgpu/nv.c +++ b/drivers/gpu/drm/amd/amdgpu/nv.c - - if (amdgpu_aspm == 0) + if (amdgpu_aspm != 1) - /* todo */ + if ((adev->asic_type >= chip_sienna_cichlid) && + !(adev->flags & amd_is_apu) && + (adev->nbio.funcs->program_aspm)) + adev->nbio.funcs->program_aspm(adev); + -#if 0 - if (adev->nbio.funcs->enable_aspm) + if ((adev->asic_type >= chip_sienna_cichlid) && + !(adev->flags & amd_is_apu) && + (adev->nbio.funcs->enable_aspm)) -#endif
|
Graphics
|
e1edaeafeb667688125ef1c4e2a098d2c798fc24
|
likun gao kenneth feng kenneth feng amd com hawking zhang hawking zhang amd com
|
drivers
|
gpu
|
amd, amdgpu, drm
|
drm/i915/display: add hdr capability detection for lspcon
|
lspcon firmware exposes hdr capability through lpcon_capabilities dpcd register. lspcon implementations capable of supporting hdr set hdr_capability bit in lspcon_capabilities to 1. this patch reads the same, detects the hdr capability and adds this to intel_lspcon struct.
|
this release allows to map an uid to a different one in a mount; it also adds support for selecting the preemption model at runtime; support for a low-overhead memory error detector designed to be used in production; support for the acrn hypervisor designed for embedded systems; btrfs initial support for zoned devices, subpage blocks sizes and performance improvements; support for eager nfs writes; support for a thermal power management to control the surface temperature of embedded devices in an unified way; the napi polling can be moved to a kernel thread; and support for non-blocking path lookups. as always, there are many other features, new drivers, improvements and fixes.
|
enable hdr on mca lspcon based gen9 devices
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'cryptography', 'security', 'networking', 'architectures x86 arm risc-v powerpc mips csky s390 pa-risc c6x']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'cpu frequency scaling', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'cryptography hardware acceleration', 'pci', 'non-transparent bridge (ntb)', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'cxl (compute express link)', 'various']
|
['intel ']
|
['h', 'c']
| 3
| 29
| 0
|
--- diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h --- a/drivers/gpu/drm/i915/display/intel_display_types.h +++ b/drivers/gpu/drm/i915/display/intel_display_types.h + bool hdr_supported; diff --git a/drivers/gpu/drm/i915/display/intel_lspcon.c b/drivers/gpu/drm/i915/display/intel_lspcon.c --- a/drivers/gpu/drm/i915/display/intel_lspcon.c +++ b/drivers/gpu/drm/i915/display/intel_lspcon.c +#define dpcd_mca_lspcon_hdr_status 0x70003 + +void lspcon_detect_hdr_capability(struct intel_lspcon *lspcon) +{ + struct intel_digital_port *dig_port = + container_of(lspcon, struct intel_digital_port, lspcon); + struct drm_device *dev = dig_port->base.base.dev; + struct intel_dp *dp = lspcon_to_intel_dp(lspcon); + u8 hdr_caps; + int ret; + + /* enable hdr for mca based lspcon devices */ + if (lspcon->vendor == lspcon_vendor_mca) + ret = drm_dp_dpcd_read(&dp->aux, dpcd_mca_lspcon_hdr_status, + &hdr_caps, 1); + else + return; + + if (ret < 0) { + drm_dbg_kms(dev, "hdr capability detection failed "); + lspcon->hdr_supported = false; + } else if (hdr_caps & 0x1) { + drm_dbg_kms(dev, "lspcon capable of hdr "); + lspcon->hdr_supported = true; + } +} + diff --git a/drivers/gpu/drm/i915/display/intel_lspcon.h b/drivers/gpu/drm/i915/display/intel_lspcon.h --- a/drivers/gpu/drm/i915/display/intel_lspcon.h +++ b/drivers/gpu/drm/i915/display/intel_lspcon.h +void lspcon_detect_hdr_capability(struct intel_lspcon *lspcon);
|
Graphics
|
81cc320aa3592ee257d1a4a5d72124546f981dad
|
uma shankar
|
drivers
|
gpu
|
display, drm, i915
|
drm/i915/display: enable hdr on gen9 devices with mca lspcon
|
gen9 hardware supports hdmi2.0 through lspcon chips. extending hdr support for mca lspcon based gen9 devices.
|
this release allows to map an uid to a different one in a mount; it also adds support for selecting the preemption model at runtime; support for a low-overhead memory error detector designed to be used in production; support for the acrn hypervisor designed for embedded systems; btrfs initial support for zoned devices, subpage blocks sizes and performance improvements; support for eager nfs writes; support for a thermal power management to control the surface temperature of embedded devices in an unified way; the napi polling can be moved to a kernel thread; and support for non-blocking path lookups. as always, there are many other features, new drivers, improvements and fixes.
|
enable hdr on mca lspcon based gen9 devices
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'cryptography', 'security', 'networking', 'architectures x86 arm risc-v powerpc mips csky s390 pa-risc c6x']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'cpu frequency scaling', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'cryptography hardware acceleration', 'pci', 'non-transparent bridge (ntb)', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'cxl (compute express link)', 'various']
|
['intel ']
|
['h', 'c']
| 3
| 26
| 17
|
--- diff --git a/drivers/gpu/drm/i915/display/intel_hdmi.c b/drivers/gpu/drm/i915/display/intel_hdmi.c --- a/drivers/gpu/drm/i915/display/intel_hdmi.c +++ b/drivers/gpu/drm/i915/display/intel_hdmi.c -static void hsw_write_infoframe(struct intel_encoder *encoder, - const struct intel_crtc_state *crtc_state, - unsigned int type, - const void *frame, ssize_t len) +void hsw_write_infoframe(struct intel_encoder *encoder, + const struct intel_crtc_state *crtc_state, + unsigned int type, + const void *frame, ssize_t len) diff --git a/drivers/gpu/drm/i915/display/intel_lspcon.c b/drivers/gpu/drm/i915/display/intel_lspcon.c --- a/drivers/gpu/drm/i915/display/intel_lspcon.c +++ b/drivers/gpu/drm/i915/display/intel_lspcon.c - bool ret; + bool ret = true; - /* lspcon only needs avi if */ - if (type != hdmi_infoframe_type_avi) + switch (type) { + case hdmi_infoframe_type_avi: + if (lspcon->vendor == lspcon_vendor_mca) + ret = _lspcon_write_avi_infoframe_mca(&intel_dp->aux, + frame, len); + else + ret = _lspcon_write_avi_infoframe_parade(&intel_dp->aux, + frame, len); + break; + case hdmi_packet_type_gamut_metadata: + drm_dbg_kms(encoder->base.dev, "update hdr metadata for lspcon "); + /* it uses the legacy hsw implementation for the same */ + hsw_write_infoframe(encoder, crtc_state, type, frame, len); + break; + default: - - if (lspcon->vendor == lspcon_vendor_mca) - ret = _lspcon_write_avi_infoframe_mca(&intel_dp->aux, - frame, len); - else - ret = _lspcon_write_avi_infoframe_parade(&intel_dp->aux, - frame, len); + } - drm_error("failed to write avi infoframes "); + drm_error("failed to write infoframes "); - - drm_debug_driver("avi infoframes updated successfully "); diff --git a/drivers/gpu/drm/i915/display/intel_lspcon.h b/drivers/gpu/drm/i915/display/intel_lspcon.h --- a/drivers/gpu/drm/i915/display/intel_lspcon.h +++ b/drivers/gpu/drm/i915/display/intel_lspcon.h +void hsw_write_infoframe(struct intel_encoder *encoder, + const struct intel_crtc_state *crtc_state, + unsigned int type, + const void *frame, ssize_t len);
|
Graphics
|
1a911350dd6c777b4a08ca60fe6e2249fd3c254a
|
uma shankar
|
drivers
|
gpu
|
display, drm, i915
|
drm/i915/display: attach hdr property for capable gen9 devices
|
attach hdr property for gen9 devices with mca lspcon chips.
|
this release allows to map an uid to a different one in a mount; it also adds support for selecting the preemption model at runtime; support for a low-overhead memory error detector designed to be used in production; support for the acrn hypervisor designed for embedded systems; btrfs initial support for zoned devices, subpage blocks sizes and performance improvements; support for eager nfs writes; support for a thermal power management to control the surface temperature of embedded devices in an unified way; the napi polling can be moved to a kernel thread; and support for non-blocking path lookups. as always, there are many other features, new drivers, improvements and fixes.
|
enable hdr on mca lspcon based gen9 devices
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'cryptography', 'security', 'networking', 'architectures x86 arm risc-v powerpc mips csky s390 pa-risc c6x']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'cpu frequency scaling', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'cryptography hardware acceleration', 'pci', 'non-transparent bridge (ntb)', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'cxl (compute express link)', 'various']
|
['intel ']
|
['h', 'c']
| 3
| 20
| 1
|
--- diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c --- a/drivers/gpu/drm/i915/display/intel_dp.c +++ b/drivers/gpu/drm/i915/display/intel_dp.c + struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); + struct intel_lspcon *lspcon = &dig_port->lspcon; + + if (!intel_bios_is_lspcon_present(i915, dig_port->base.port)) + return ret; + + /* + * todo: clean this up to handle lspcon init and resume more + * efficiently and streamlined. + */ + if (lspcon_init(dig_port)) { + lspcon_detect_hdr_capability(lspcon); + if (lspcon->hdr_supported) + drm_object_attach_property(&connector->base, + connector->dev->mode_config.hdr_output_metadata_property, + 0); + } + diff --git a/drivers/gpu/drm/i915/display/intel_lspcon.c b/drivers/gpu/drm/i915/display/intel_lspcon.c --- a/drivers/gpu/drm/i915/display/intel_lspcon.c +++ b/drivers/gpu/drm/i915/display/intel_lspcon.c -static bool lspcon_init(struct intel_digital_port *dig_port) +bool lspcon_init(struct intel_digital_port *dig_port) diff --git a/drivers/gpu/drm/i915/display/intel_lspcon.h b/drivers/gpu/drm/i915/display/intel_lspcon.h --- a/drivers/gpu/drm/i915/display/intel_lspcon.h +++ b/drivers/gpu/drm/i915/display/intel_lspcon.h +bool lspcon_init(struct intel_digital_port *dig_port);
|
Graphics
|
2e666613b24e3c7d2ae5cf5c1e264751bb5b2a8f
|
uma shankar
|
drivers
|
gpu
|
display, drm, i915
|
drm/i915/display: fixes quantization range for ycbcr output
|
this patch fixes the quantization range for ycbcr output on lspcon based devices.
|
this release allows to map an uid to a different one in a mount; it also adds support for selecting the preemption model at runtime; support for a low-overhead memory error detector designed to be used in production; support for the acrn hypervisor designed for embedded systems; btrfs initial support for zoned devices, subpage blocks sizes and performance improvements; support for eager nfs writes; support for a thermal power management to control the surface temperature of embedded devices in an unified way; the napi polling can be moved to a kernel thread; and support for non-blocking path lookups. as always, there are many other features, new drivers, improvements and fixes.
|
enable hdr on mca lspcon based gen9 devices
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'cryptography', 'security', 'networking', 'architectures x86 arm risc-v powerpc mips csky s390 pa-risc c6x']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'cpu frequency scaling', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'cryptography hardware acceleration', 'pci', 'non-transparent bridge (ntb)', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'cxl (compute express link)', 'various']
|
['intel ']
|
['c']
| 1
| 11
| 6
|
--- diff --git a/drivers/gpu/drm/i915/display/intel_lspcon.c b/drivers/gpu/drm/i915/display/intel_lspcon.c --- a/drivers/gpu/drm/i915/display/intel_lspcon.c +++ b/drivers/gpu/drm/i915/display/intel_lspcon.c - drm_hdmi_avi_infoframe_quant_range(&frame.avi, - conn_state->connector, - adjusted_mode, - crtc_state->limited_color_range ? - hdmi_quantization_range_limited : - hdmi_quantization_range_full); + if (crtc_state->output_format == intel_output_format_rgb) { + drm_hdmi_avi_infoframe_quant_range(&frame.avi, + conn_state->connector, + adjusted_mode, + crtc_state->limited_color_range ? + hdmi_quantization_range_limited : + hdmi_quantization_range_full); + } else { + frame.avi.quantization_range = hdmi_quantization_range_default; + frame.avi.ycc_quantization_range = hdmi_ycc_quantization_range_limited; + }
|
Graphics
|
9559c0d13b6b35abc2659bdd3024849d552e3c4e
|
uma shankar
|
drivers
|
gpu
|
display, drm, i915
|
drm/i915/display: add a warn for invalid output range and format
|
add a warn to rule out an invalid output range and format combination. this is to align the lspcon code with compute_avi_infoframes.
|
this release allows to map an uid to a different one in a mount; it also adds support for selecting the preemption model at runtime; support for a low-overhead memory error detector designed to be used in production; support for the acrn hypervisor designed for embedded systems; btrfs initial support for zoned devices, subpage blocks sizes and performance improvements; support for eager nfs writes; support for a thermal power management to control the surface temperature of embedded devices in an unified way; the napi polling can be moved to a kernel thread; and support for non-blocking path lookups. as always, there are many other features, new drivers, improvements and fixes.
|
enable hdr on mca lspcon based gen9 devices
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'cryptography', 'security', 'networking', 'architectures x86 arm risc-v powerpc mips csky s390 pa-risc c6x']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'cpu frequency scaling', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'cryptography hardware acceleration', 'pci', 'non-transparent bridge (ntb)', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'cxl (compute express link)', 'various']
|
['intel ']
|
['c']
| 1
| 4
| 0
|
--- diff --git a/drivers/gpu/drm/i915/display/intel_lspcon.c b/drivers/gpu/drm/i915/display/intel_lspcon.c --- a/drivers/gpu/drm/i915/display/intel_lspcon.c +++ b/drivers/gpu/drm/i915/display/intel_lspcon.c + /* nonsense combination */ + drm_warn_on(encoder->base.dev, crtc_state->limited_color_range && + crtc_state->output_format != intel_output_format_rgb); +
|
Graphics
|
55b1f9ddf41d369f2d480596822c6d17817a8d78
|
uma shankar ville syrj l ville syrjala linux intel com
|
drivers
|
gpu
|
display, drm, i915
|
drm/i915/display: attach content type property for lspcon
|
content type is supported on hdmi sink devices. attached the property for the same for lspcon based devices.
|
this release allows to map an uid to a different one in a mount; it also adds support for selecting the preemption model at runtime; support for a low-overhead memory error detector designed to be used in production; support for the acrn hypervisor designed for embedded systems; btrfs initial support for zoned devices, subpage blocks sizes and performance improvements; support for eager nfs writes; support for a thermal power management to control the surface temperature of embedded devices in an unified way; the napi polling can be moved to a kernel thread; and support for non-blocking path lookups. as always, there are many other features, new drivers, improvements and fixes.
|
enable hdr on mca lspcon based gen9 devices
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'cryptography', 'security', 'networking', 'architectures x86 arm risc-v powerpc mips csky s390 pa-risc c6x']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'cpu frequency scaling', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'cryptography hardware acceleration', 'pci', 'non-transparent bridge (ntb)', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'cxl (compute express link)', 'various']
|
['intel ']
|
['c']
| 2
| 5
| 0
|
--- diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c --- a/drivers/gpu/drm/i915/display/intel_dp.c +++ b/drivers/gpu/drm/i915/display/intel_dp.c + if (intel_bios_is_lspcon_present(dev_priv, port)) + drm_connector_attach_content_type_property(connector); + diff --git a/drivers/gpu/drm/i915/display/intel_lspcon.c b/drivers/gpu/drm/i915/display/intel_lspcon.c --- a/drivers/gpu/drm/i915/display/intel_lspcon.c +++ b/drivers/gpu/drm/i915/display/intel_lspcon.c + drm_hdmi_avi_infoframe_content_type(&frame.avi, conn_state); +
|
Graphics
|
b983675709e07523c5e8bacfcfa153a49f7eca7f
|
uma shankar
|
drivers
|
gpu
|
display, drm, i915
|
drm/i915: split intel_attach_colorspace_property() into hdmi vs. dp variants
|
with lspcon we use the avi infoframe to convey the colorimetry information (as opposed to dp msa/sdp), so the property we expose should match the values we can stuff into the infoframe. ie. we must use the hdmi variant of the property, even though we drive lspcon in pcon mode. to that end just split intel_attach_colorspace_property() into hdmi and dp variants and let the caller worry about which one it wants to use.
|
this release allows to map an uid to a different one in a mount; it also adds support for selecting the preemption model at runtime; support for a low-overhead memory error detector designed to be used in production; support for the acrn hypervisor designed for embedded systems; btrfs initial support for zoned devices, subpage blocks sizes and performance improvements; support for eager nfs writes; support for a thermal power management to control the surface temperature of embedded devices in an unified way; the napi polling can be moved to a kernel thread; and support for non-blocking path lookups. as always, there are many other features, new drivers, improvements and fixes.
|
enable hdr on mca lspcon based gen9 devices
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'cryptography', 'security', 'networking', 'architectures x86 arm risc-v powerpc mips csky s390 pa-risc c6x']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'cpu frequency scaling', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'cryptography hardware acceleration', 'pci', 'non-transparent bridge (ntb)', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'cxl (compute express link)', 'various']
|
['intel ']
|
['h', 'c']
| 4
| 15
| 21
|
--- diff --git a/drivers/gpu/drm/i915/display/intel_connector.c b/drivers/gpu/drm/i915/display/intel_connector.c --- a/drivers/gpu/drm/i915/display/intel_connector.c +++ b/drivers/gpu/drm/i915/display/intel_connector.c -intel_attach_colorspace_property(struct drm_connector *connector) +intel_attach_hdmi_colorspace_property(struct drm_connector *connector) - switch (connector->connector_type) { - case drm_mode_connector_hdmia: - case drm_mode_connector_hdmib: - if (drm_mode_create_hdmi_colorspace_property(connector)) - return; - break; - case drm_mode_connector_displayport: - case drm_mode_connector_edp: - if (drm_mode_create_dp_colorspace_property(connector)) - return; - break; - default: - missing_case(connector->connector_type); - return; - } + if (!drm_mode_create_hdmi_colorspace_property(connector)) + drm_object_attach_property(&connector->base, + connector->colorspace_property, 0); +} - drm_object_attach_property(&connector->base, - connector->colorspace_property, 0); +void +intel_attach_dp_colorspace_property(struct drm_connector *connector) +{ + if (!drm_mode_create_dp_colorspace_property(connector)) + drm_object_attach_property(&connector->base, + connector->colorspace_property, 0); diff --git a/drivers/gpu/drm/i915/display/intel_connector.h b/drivers/gpu/drm/i915/display/intel_connector.h --- a/drivers/gpu/drm/i915/display/intel_connector.h +++ b/drivers/gpu/drm/i915/display/intel_connector.h -void intel_attach_colorspace_property(struct drm_connector *connector); +void intel_attach_hdmi_colorspace_property(struct drm_connector *connector); +void intel_attach_dp_colorspace_property(struct drm_connector *connector); diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c --- a/drivers/gpu/drm/i915/display/intel_dp.c +++ b/drivers/gpu/drm/i915/display/intel_dp.c - intel_attach_colorspace_property(connector); + intel_attach_dp_colorspace_property(connector); diff --git a/drivers/gpu/drm/i915/display/intel_hdmi.c b/drivers/gpu/drm/i915/display/intel_hdmi.c --- a/drivers/gpu/drm/i915/display/intel_hdmi.c +++ b/drivers/gpu/drm/i915/display/intel_hdmi.c - intel_attach_colorspace_property(connector); + intel_attach_hdmi_colorspace_property(connector);
|
Graphics
|
174da987bc8da65327c230ba404a98bcd1b16cf1
|
ville syrj l uma shankar uma shankar intel com
|
drivers
|
gpu
|
display, drm, i915
|
drm/i915/display: enable colorspace programming for lspcon devices
|
enable hdmi colorspace for lspcon based devices. sending colorimetry data for hdr using avi infoframe. lspcon firmware expects this and though soc drives dp, for hdmi panel avi infoframe is sent to the lspcon device which transfers the same to hdmi sink.
|
this release allows to map an uid to a different one in a mount; it also adds support for selecting the preemption model at runtime; support for a low-overhead memory error detector designed to be used in production; support for the acrn hypervisor designed for embedded systems; btrfs initial support for zoned devices, subpage blocks sizes and performance improvements; support for eager nfs writes; support for a thermal power management to control the surface temperature of embedded devices in an unified way; the napi polling can be moved to a kernel thread; and support for non-blocking path lookups. as always, there are many other features, new drivers, improvements and fixes.
|
enable hdr on mca lspcon based gen9 devices
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'cryptography', 'security', 'networking', 'architectures x86 arm risc-v powerpc mips csky s390 pa-risc c6x']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'cpu frequency scaling', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'cryptography hardware acceleration', 'pci', 'non-transparent bridge (ntb)', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'cxl (compute express link)', 'various']
|
['intel ']
|
['c']
| 2
| 9
| 3
|
--- diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c --- a/drivers/gpu/drm/i915/display/intel_dp.c +++ b/drivers/gpu/drm/i915/display/intel_dp.c - intel_attach_dp_colorspace_property(connector); - - if (intel_bios_is_lspcon_present(dev_priv, port)) + /* register hdmi colorspace for case of lspcon */ + if (intel_bios_is_lspcon_present(dev_priv, port)) { + intel_attach_hdmi_colorspace_property(connector); + } else { + intel_attach_dp_colorspace_property(connector); + } diff --git a/drivers/gpu/drm/i915/display/intel_lspcon.c b/drivers/gpu/drm/i915/display/intel_lspcon.c --- a/drivers/gpu/drm/i915/display/intel_lspcon.c +++ b/drivers/gpu/drm/i915/display/intel_lspcon.c + /* set the colorspace as per the hdmi spec */ + drm_hdmi_avi_infoframe_colorspace(&frame.avi, conn_state); +
|
Graphics
|
5d36f2b2dd4d973880ee0450f1c287d1c368ebb2
|
uma shankar
|
drivers
|
gpu
|
display, drm, i915
|
drm/i915/display: nuke bogus lspcon check
|
dropped a irrelevant lspcon check from intel_hdmi_add_properties function.
|
this release allows to map an uid to a different one in a mount; it also adds support for selecting the preemption model at runtime; support for a low-overhead memory error detector designed to be used in production; support for the acrn hypervisor designed for embedded systems; btrfs initial support for zoned devices, subpage blocks sizes and performance improvements; support for eager nfs writes; support for a thermal power management to control the surface temperature of embedded devices in an unified way; the napi polling can be moved to a kernel thread; and support for non-blocking path lookups. as always, there are many other features, new drivers, improvements and fixes.
|
enable hdr on mca lspcon based gen9 devices
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'cryptography', 'security', 'networking', 'architectures x86 arm risc-v powerpc mips csky s390 pa-risc c6x']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'cpu frequency scaling', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'cryptography hardware acceleration', 'pci', 'non-transparent bridge (ntb)', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'cxl (compute express link)', 'various']
|
['intel ']
|
['c']
| 1
| 1
| 10
|
--- diff --git a/drivers/gpu/drm/i915/display/intel_hdmi.c b/drivers/gpu/drm/i915/display/intel_hdmi.c --- a/drivers/gpu/drm/i915/display/intel_hdmi.c +++ b/drivers/gpu/drm/i915/display/intel_hdmi.c - struct intel_digital_port *dig_port = - hdmi_to_dig_port(intel_hdmi); - /* - * attach colorspace property for non lspcon based device - * todo: this needs to be extended for lspcon implementation - * as well. will be implemented separately. - */ - if (!dig_port->lspcon.active) - intel_attach_hdmi_colorspace_property(connector); - + intel_attach_hdmi_colorspace_property(connector);
|
Graphics
|
84ab44b757d59e50584c0ca86890dd139f9daed0
|
uma shankar ville syrj l ville syrjala linux intel com ville syrj l ville syrjala linux intel com
|
drivers
|
gpu
|
display, drm, i915
|
drm/i915/display: enable hdr for parade based lspcon
|
enable hdr for lspcon based on parade along with mca.
|
this release allows to map an uid to a different one in a mount; it also adds support for selecting the preemption model at runtime; support for a low-overhead memory error detector designed to be used in production; support for the acrn hypervisor designed for embedded systems; btrfs initial support for zoned devices, subpage blocks sizes and performance improvements; support for eager nfs writes; support for a thermal power management to control the surface temperature of embedded devices in an unified way; the napi polling can be moved to a kernel thread; and support for non-blocking path lookups. as always, there are many other features, new drivers, improvements and fixes.
|
enable hdr on mca lspcon based gen9 devices
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'cryptography', 'security', 'networking', 'architectures x86 arm risc-v powerpc mips csky s390 pa-risc c6x']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'cpu frequency scaling', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'cryptography hardware acceleration', 'pci', 'non-transparent bridge (ntb)', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'cxl (compute express link)', 'various']
|
['intel ']
|
['c']
| 1
| 11
| 6
|
--- diff --git a/drivers/gpu/drm/i915/display/intel_lspcon.c b/drivers/gpu/drm/i915/display/intel_lspcon.c --- a/drivers/gpu/drm/i915/display/intel_lspcon.c +++ b/drivers/gpu/drm/i915/display/intel_lspcon.c +#define dpcd_parade_lspcon_hdr_status 0x00511 +static u32 get_hdr_status_reg(struct intel_lspcon *lspcon) +{ + if (lspcon->vendor == lspcon_vendor_mca) + return dpcd_mca_lspcon_hdr_status; + else + return dpcd_parade_lspcon_hdr_status; +} + - /* enable hdr for mca based lspcon devices */ - if (lspcon->vendor == lspcon_vendor_mca) - ret = drm_dp_dpcd_read(&dp->aux, dpcd_mca_lspcon_hdr_status, - &hdr_caps, 1); - else - return; + ret = drm_dp_dpcd_read(&dp->aux, get_hdr_status_reg(lspcon), + &hdr_caps, 1);
|
Graphics
|
c5044aee4039671d72ddcfdb38ea0a3b32effab4
|
uma shankar
|
drivers
|
gpu
|
display, drm, i915
|
drm/i915/lspcon: create separate infoframe_enabled helper
|
lspcon has infoframes as well as dip for hdr metadata(drm infoframe). create a separate mechanism for lspcon compared to hdmi in order to address the same and ensure future scalability.
|
this release allows to map an uid to a different one in a mount; it also adds support for selecting the preemption model at runtime; support for a low-overhead memory error detector designed to be used in production; support for the acrn hypervisor designed for embedded systems; btrfs initial support for zoned devices, subpage blocks sizes and performance improvements; support for eager nfs writes; support for a thermal power management to control the surface temperature of embedded devices in an unified way; the napi polling can be moved to a kernel thread; and support for non-blocking path lookups. as always, there are many other features, new drivers, improvements and fixes.
|
enable hdr on mca lspcon based gen9 devices
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'cryptography', 'security', 'networking', 'architectures x86 arm risc-v powerpc mips csky s390 pa-risc c6x']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'cpu frequency scaling', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'cryptography hardware acceleration', 'pci', 'non-transparent bridge (ntb)', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'cxl (compute express link)', 'various']
|
['intel ']
|
['h', 'c']
| 3
| 18
| 3
|
--- diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c --- a/drivers/gpu/drm/i915/display/intel_ddi.c +++ b/drivers/gpu/drm/i915/display/intel_ddi.c + struct intel_digital_port *dig_port = enc_to_dig_port(encoder); - pipe_config->infoframes.enable |= - intel_hdmi_infoframes_enabled(encoder, pipe_config); - + if (dig_port->lspcon.active && dig_port->dp.has_hdmi_sink) + pipe_config->infoframes.enable |= + intel_lspcon_infoframes_enabled(encoder, pipe_config); + else + pipe_config->infoframes.enable |= + intel_hdmi_infoframes_enabled(encoder, pipe_config); diff --git a/drivers/gpu/drm/i915/display/intel_lspcon.c b/drivers/gpu/drm/i915/display/intel_lspcon.c --- a/drivers/gpu/drm/i915/display/intel_lspcon.c +++ b/drivers/gpu/drm/i915/display/intel_lspcon.c +#include "intel_hdmi.h" +u32 intel_lspcon_infoframes_enabled(struct intel_encoder *encoder, + const struct intel_crtc_state *pipe_config) +{ + struct intel_digital_port *dig_port = enc_to_dig_port(encoder); + + return dig_port->infoframes_enabled(encoder, pipe_config); +} + diff --git a/drivers/gpu/drm/i915/display/intel_lspcon.h b/drivers/gpu/drm/i915/display/intel_lspcon.h --- a/drivers/gpu/drm/i915/display/intel_lspcon.h +++ b/drivers/gpu/drm/i915/display/intel_lspcon.h +u32 intel_lspcon_infoframes_enabled(struct intel_encoder *encoder, + const struct intel_crtc_state *pipe_config);
|
Graphics
|
a44289b923f6092e3103e8e1b83a5d0b86d34769
|
uma shankar
|
drivers
|
gpu
|
display, drm, i915
|
drm/i915/display: implement infoframes readback for lspcon
|
implemented infoframes enabled readback for lspcon devices. this will help align the implementation with state readback infrastructure.
|
this release allows to map an uid to a different one in a mount; it also adds support for selecting the preemption model at runtime; support for a low-overhead memory error detector designed to be used in production; support for the acrn hypervisor designed for embedded systems; btrfs initial support for zoned devices, subpage blocks sizes and performance improvements; support for eager nfs writes; support for a thermal power management to control the surface temperature of embedded devices in an unified way; the napi polling can be moved to a kernel thread; and support for non-blocking path lookups. as always, there are many other features, new drivers, improvements and fixes.
|
enable hdr on mca lspcon based gen9 devices
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'cryptography', 'security', 'networking', 'architectures x86 arm risc-v powerpc mips csky s390 pa-risc c6x']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'cpu frequency scaling', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'cryptography hardware acceleration', 'pci', 'non-transparent bridge (ntb)', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'cxl (compute express link)', 'various']
|
['intel ']
|
['c']
| 1
| 55
| 2
|
--- diff --git a/drivers/gpu/drm/i915/display/intel_lspcon.c b/drivers/gpu/drm/i915/display/intel_lspcon.c --- a/drivers/gpu/drm/i915/display/intel_lspcon.c +++ b/drivers/gpu/drm/i915/display/intel_lspcon.c +static bool _lspcon_read_avi_infoframe_enabled_mca(struct drm_dp_aux *aux) +{ + int ret; + u32 val = 0; + u16 reg = lspcon_mca_avi_if_ctrl; + + ret = drm_dp_dpcd_read(aux, reg, &val, 1); + if (ret < 0) { + drm_error("dpcd read failed, address 0x%x ", reg); + return false; + } + + return val & lspcon_mca_avi_if_kickoff; +} + +static bool _lspcon_read_avi_infoframe_enabled_parade(struct drm_dp_aux *aux) +{ + int ret; + u32 val = 0; + u16 reg = lspcon_parade_avi_if_ctrl; + + ret = drm_dp_dpcd_read(aux, reg, &val, 1); + if (ret < 0) { + drm_error("dpcd read failed, address 0x%x ", reg); + return false; + } + + return val & lspcon_parade_avi_if_kickoff; +} + - /* fixme actually read this from the hw */ - return 0; + struct intel_dp *intel_dp = enc_to_intel_dp(encoder); + struct intel_lspcon *lspcon = enc_to_intel_lspcon(encoder); + struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); + bool infoframes_enabled; + u32 val = 0; + u32 mask, tmp; + + if (lspcon->vendor == lspcon_vendor_mca) + infoframes_enabled = _lspcon_read_avi_infoframe_enabled_mca(&intel_dp->aux); + else + infoframes_enabled = _lspcon_read_avi_infoframe_enabled_parade(&intel_dp->aux); + + if (infoframes_enabled) + val |= intel_hdmi_infoframe_enable(hdmi_infoframe_type_avi); + + if (lspcon->hdr_supported) { + tmp = intel_de_read(dev_priv, + hsw_tvideo_dip_ctl(pipe_config->cpu_transcoder)); + mask = video_dip_enable_gmp_hsw; + + if (tmp & mask) + val |= intel_hdmi_infoframe_enable(hdmi_packet_type_gamut_metadata); + } + + return val;
|
Graphics
|
34108a03e430ea0e7a1d9005e3caa0d6a746fa95
|
uma shankar
|
drivers
|
gpu
|
display, drm, i915
|
drm/i915/display: implement drm infoframe read for lspcon
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implement read back of hdr metadata infoframes i.e dynamic range and mastering infoframe for lspcon devices.
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this release allows to map an uid to a different one in a mount; it also adds support for selecting the preemption model at runtime; support for a low-overhead memory error detector designed to be used in production; support for the acrn hypervisor designed for embedded systems; btrfs initial support for zoned devices, subpage blocks sizes and performance improvements; support for eager nfs writes; support for a thermal power management to control the surface temperature of embedded devices in an unified way; the napi polling can be moved to a kernel thread; and support for non-blocking path lookups. as always, there are many other features, new drivers, improvements and fixes.
|
enable hdr on mca lspcon based gen9 devices
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['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'cryptography', 'security', 'networking', 'architectures x86 arm risc-v powerpc mips csky s390 pa-risc c6x']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'cpu frequency scaling', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'cryptography hardware acceleration', 'pci', 'non-transparent bridge (ntb)', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'cxl (compute express link)', 'various']
|
['intel ']
|
['h', 'c']
| 3
| 11
| 5
|
--- diff --git a/drivers/gpu/drm/i915/display/intel_hdmi.c b/drivers/gpu/drm/i915/display/intel_hdmi.c --- a/drivers/gpu/drm/i915/display/intel_hdmi.c +++ b/drivers/gpu/drm/i915/display/intel_hdmi.c -static void hsw_read_infoframe(struct intel_encoder *encoder, - const struct intel_crtc_state *crtc_state, - unsigned int type, - void *frame, ssize_t len) +void hsw_read_infoframe(struct intel_encoder *encoder, + const struct intel_crtc_state *crtc_state, + unsigned int type, void *frame, ssize_t len) diff --git a/drivers/gpu/drm/i915/display/intel_lspcon.c b/drivers/gpu/drm/i915/display/intel_lspcon.c --- a/drivers/gpu/drm/i915/display/intel_lspcon.c +++ b/drivers/gpu/drm/i915/display/intel_lspcon.c - /* fixme implement this */ + /* fixme implement for avi infoframe as well */ + if (type == hdmi_packet_type_gamut_metadata) + hsw_read_infoframe(encoder, crtc_state, type, + frame, len); diff --git a/drivers/gpu/drm/i915/display/intel_lspcon.h b/drivers/gpu/drm/i915/display/intel_lspcon.h --- a/drivers/gpu/drm/i915/display/intel_lspcon.h +++ b/drivers/gpu/drm/i915/display/intel_lspcon.h +void hsw_read_infoframe(struct intel_encoder *encoder, + const struct intel_crtc_state *crtc_state, + unsigned int type, + void *frame, ssize_t len);
|
Graphics
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b759415020b335aea8329f210ee162cb0c3c86a0
|
uma shankar
|
drivers
|
gpu
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display, drm, i915
|
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