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def set_screen_config(self, size_id, rotation, config_timestamp, rate=0, timestamp=X.CurrentTime):
"""Sets the screen to the specified size, rate, rotation and reflection. rate can be 0 to have the server select an appropriate rate. """ |
return SetScreenConfig(
display=self.display,
opcode=self.display.get_extension_major(extname),
drawable=self,
timestamp=timestamp,
config_timestamp=config_timestamp,
size_id=size_id,
rotation=rotation,
rate=rate,
) |
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def get_screen_info(self):
"""Retrieve information about the current and available configurations for the screen associated with this window. """ |
return GetScreenInfo(
display=self.display,
opcode=self.display.get_extension_major(extname),
window=self,
) |
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def get_screen_size_range(self):
"""Retrieve the range of possible screen sizes. The screen may be set to any size within this range. """ |
return GetScreenSizeRange(
display=self.display,
opcode=self.display.get_extension_major(extname),
window=self,
) |
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def get_screen_size(self, screen_no):
"""Returns the size of the given screen number""" |
return GetScreenSize(display=self.display,
opcode=self.display.get_extension_major(extname),
window=self.id,
screen=screen_no,
) |
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def get_query_cache_key(compiler):
""" Generates a cache key from a SQLCompiler. This cache key is specific to the SQL query and its context (which database is used). The same query in the same context (= the same database) must generate the same cache key. :arg compiler: A SQLCompiler that will generate the SQL query :type compiler: django.db.models.sql.compiler.SQLCompiler :return: A cache key :rtype: int """ |
sql, params = compiler.as_sql()
check_parameter_types(params)
cache_key = '%s:%s:%s' % (compiler.using, sql,
[text_type(p) for p in params])
return sha1(cache_key.encode('utf-8')).hexdigest() |
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def get_table_cache_key(db_alias, table):
""" Generates a cache key from a SQL table. :arg db_alias: Alias of the used database :type db_alias: str or unicode :arg table: Name of the SQL table :type table: str or unicode :return: A cache key :rtype: int """ |
cache_key = '%s:%s' % (db_alias, table)
return sha1(cache_key.encode('utf-8')).hexdigest() |
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def translate(self, instr):
"""Return the SMT representation of a REIL instruction. """ |
try:
translator = self._instr_translators[instr.mnemonic]
return translator(*instr.operands)
except Exception:
logger.error("Failed to translate instruction: %s", instr, exc_info=True)
raise |
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def get_name_init(self, name):
"""Get initial name of symbol. """ |
self._register_name(name)
return self._var_name_mappers[name].get_init() |
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def get_name_curr(self, name):
"""Get current name of symbol. """ |
self._register_name(name)
return self._var_name_mappers[name].get_current() |
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def reset(self):
"""Reset internal state. """ |
self._solver.reset()
# Memory versioning.
self._mem_instance = 0
self._mem_init = smtsymbol.BitVecArray(self._address_size, 8, "MEM_{}".format(self._mem_instance))
self._mem_curr = self.make_array(self._address_size, "MEM_{}".format(self._mem_instance))
self._var_name_mappers = {} |
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def _register_name(self, name):
"""Get register name. """ |
if name not in self._var_name_mappers:
self._var_name_mappers[name] = VariableNamer(name) |
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def _get_var_name(self, name, fresh=False):
"""Get variable name. """ |
if name not in self._var_name_mappers:
self._var_name_mappers[name] = VariableNamer(name)
if fresh:
var_name = self._var_name_mappers[name].get_next()
else:
var_name = self._var_name_mappers[name].get_current()
return var_name |
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def _translate_src_oprnd(self, operand):
"""Translate source operand to a SMT expression. """ |
if isinstance(operand, ReilRegisterOperand):
return self._translate_src_register_oprnd(operand)
elif isinstance(operand, ReilImmediateOperand):
return smtsymbol.Constant(operand.size, operand.immediate)
else:
raise Exception("Invalid operand type") |
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def _translate_dst_oprnd(self, operand):
"""Translate destination operand to a SMT expression. """ |
if isinstance(operand, ReilRegisterOperand):
return self._translate_dst_register_oprnd(operand)
else:
raise Exception("Invalid operand type") |
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def _translate_src_register_oprnd(self, operand):
"""Translate source register operand to SMT expr. """ |
reg_info = self._arch_alias_mapper.get(operand.name, None)
if reg_info:
var_base_name, offset = reg_info
var_size = self._arch_regs_size[var_base_name]
else:
var_base_name = operand.name
var_size = operand.size
var_name = self._get_var_name(var_base_name)
ret_val = self.make_bitvec(var_size, var_name)
if reg_info:
ret_val = smtfunction.extract(ret_val, offset, operand.size)
return ret_val |
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def _translate_dst_register_oprnd(self, operand):
"""Translate destination register operand to SMT expr. """ |
reg_info = self._arch_alias_mapper.get(operand.name, None)
parent_reg_constrs = []
if reg_info:
var_base_name, offset = reg_info
var_name_old = self._get_var_name(var_base_name, fresh=False)
var_name_new = self._get_var_name(var_base_name, fresh=True)
var_size = self._arch_regs_size[var_base_name]
ret_val_old = self.make_bitvec(var_size, var_name_old)
ret_val_new = self.make_bitvec(var_size, var_name_new)
ret_val = smtfunction.extract(ret_val_new, offset, operand.size)
if 0 < offset < var_size - 1:
lower_expr_1 = smtfunction.extract(ret_val_new, 0, offset)
lower_expr_2 = smtfunction.extract(ret_val_old, 0, offset)
parent_reg_constrs += [lower_expr_1 == lower_expr_2]
upper_expr_1 = smtfunction.extract(ret_val_new, offset + operand.size, var_size - offset - operand.size)
upper_expr_2 = smtfunction.extract(ret_val_old, offset + operand.size, var_size - offset - operand.size)
parent_reg_constrs += [upper_expr_1 == upper_expr_2]
elif offset == 0:
upper_expr_1 = smtfunction.extract(ret_val_new, offset + operand.size, var_size - offset - operand.size)
upper_expr_2 = smtfunction.extract(ret_val_old, offset + operand.size, var_size - offset - operand.size)
parent_reg_constrs += [upper_expr_1 == upper_expr_2]
elif offset == var_size-1:
lower_expr_1 = smtfunction.extract(ret_val_new, 0, offset)
lower_expr_2 = smtfunction.extract(ret_val_old, 0, offset)
parent_reg_constrs += [lower_expr_1 == lower_expr_2]
else:
var_name_new = self._get_var_name(operand.name, fresh=True)
ret_val = self.make_bitvec(operand.size, var_name_new)
return ret_val, parent_reg_constrs |
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def _translate_add(self, oprnd1, oprnd2, oprnd3):
"""Return a formula representation of an ADD instruction. """ |
assert oprnd1.size and oprnd2.size and oprnd3.size
assert oprnd1.size == oprnd2.size
op1_var = self._translate_src_oprnd(oprnd1)
op2_var = self._translate_src_oprnd(oprnd2)
op3_var, op3_var_constrs = self._translate_dst_oprnd(oprnd3)
if oprnd3.size > oprnd1.size:
result = smtfunction.zero_extend(op1_var, oprnd3.size) + smtfunction.zero_extend(op2_var, oprnd3.size)
elif oprnd3.size < oprnd1.size:
result = smtfunction.extract(op1_var + op2_var, 0, oprnd3.size)
else:
result = op1_var + op2_var
return [op3_var == result] + op3_var_constrs |
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def _translate_bsh(self, oprnd1, oprnd2, oprnd3):
"""Return a formula representation of a BSH instruction. """ |
assert oprnd1.size and oprnd2.size and oprnd3.size
assert oprnd1.size == oprnd2.size
op1_var = self._translate_src_oprnd(oprnd1)
op2_var = self._translate_src_oprnd(oprnd2)
op3_var, op3_var_constrs = self._translate_dst_oprnd(oprnd3)
if oprnd3.size > oprnd1.size:
op1_var_zx = smtfunction.zero_extend(op1_var, oprnd3.size)
op2_var_zx = smtfunction.zero_extend(op2_var, oprnd3.size)
op2_var_neg_sx = smtfunction.sign_extend(-op2_var, oprnd3.size)
shr = smtfunction.extract(op1_var_zx >> op2_var_neg_sx, 0, op3_var.size)
shl = smtfunction.extract(op1_var_zx << op2_var_zx, 0, op3_var.size)
elif oprnd3.size < oprnd1.size:
shr = smtfunction.extract(op1_var >> -op2_var, 0, op3_var.size)
shl = smtfunction.extract(op1_var << op2_var, 0, op3_var.size)
else:
shr = op1_var >> -op2_var
shl = op1_var << op2_var
result = smtfunction.ite(oprnd3.size, op2_var >= 0, shl, shr)
return [op3_var == result] + op3_var_constrs |
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def _translate_ldm(self, oprnd1, oprnd2, oprnd3):
"""Return a formula representation of a LDM instruction. """ |
assert oprnd1.size and oprnd3.size
assert oprnd1.size == self._address_size
op1_var = self._translate_src_oprnd(oprnd1)
op3_var, op3_var_constrs = self._translate_dst_oprnd(oprnd3)
exprs = []
for i in reversed(range(0, oprnd3.size, 8)):
exprs += [self._mem_curr[op1_var + i // 8] == smtfunction.extract(op3_var, i, 8)]
return exprs + op3_var_constrs |
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def _translate_stm(self, oprnd1, oprnd2, oprnd3):
"""Return a formula representation of a STM instruction. """ |
assert oprnd1.size and oprnd3.size
assert oprnd3.size == self._address_size
op1_var = self._translate_src_oprnd(oprnd1)
op3_var = self._translate_src_oprnd(oprnd3)
for i in range(0, oprnd1.size, 8):
self._mem_curr[op3_var + i//8] = smtfunction.extract(op1_var, i, 8)
# Memory versioning.
self._mem_instance += 1
mem_old = self._mem_curr
mem_new = self.make_array(self._address_size, "MEM_{}".format(self._mem_instance))
self._mem_curr = mem_new
return [mem_new == mem_old] |
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def _translate_str(self, oprnd1, oprnd2, oprnd3):
"""Return a formula representation of a STR instruction. """ |
assert oprnd1.size and oprnd3.size
op1_var = self._translate_src_oprnd(oprnd1)
op3_var, op3_var_constrs = self._translate_dst_oprnd(oprnd3)
if oprnd3.size > oprnd1.size:
result = smtfunction.zero_extend(op1_var, op3_var.size)
elif oprnd3.size < oprnd1.size:
result = smtfunction.extract(op1_var, 0, op3_var.size)
else:
result = op1_var
return [op3_var == result] + op3_var_constrs |
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def _translate_bisz(self, oprnd1, oprnd2, oprnd3):
"""Return a formula representation of a BISZ instruction. """ |
assert oprnd1.size and oprnd3.size
op1_var = self._translate_src_oprnd(oprnd1)
op3_var, op3_var_constrs = self._translate_dst_oprnd(oprnd3)
result = smtfunction.ite(oprnd3.size, op1_var == 0x0, smtsymbol.Constant(oprnd3.size, 0x1),
smtsymbol.Constant(oprnd3.size, 0x0))
return [op3_var == result] + op3_var_constrs |
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def _translate_jcc(self, oprnd1, oprnd2, oprnd3):
"""Return a formula representation of a JCC instruction. """ |
assert oprnd1.size and oprnd3.size
op1_var = self._translate_src_oprnd(oprnd1)
return [op1_var != 0x0] |
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def _translate_sext(self, oprnd1, oprnd2, oprnd3):
"""Return a formula representation of a SEXT instruction. """ |
assert oprnd1.size and oprnd3.size
op1_var = self._translate_src_oprnd(oprnd1)
op3_var, op3_var_constrs = self._translate_dst_oprnd(oprnd3)
if oprnd3.size > oprnd1.size:
result = smtfunction.sign_extend(op1_var, op3_var.size)
elif oprnd3.size < oprnd1.size:
raise Exception("Operands size mismatch.")
else:
result = op1_var
return [op3_var == result] + op3_var_constrs |
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def verify(self, gadget):
"""Verify gadgets. """ |
# Add instructions to the analyzer
self.analyzer.reset()
for reil_instr in gadget.ir_instrs:
self.analyzer.add_instruction(reil_instr)
# Generate constraints for the gadgets type.
constrs = self._constraints_generators[gadget.type](gadget)
# Check constraints.
if not constrs:
return False
for constr in constrs:
self.analyzer.add_constraint(constr)
return self.analyzer.check() == 'unsat' |
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def _get_constrs_no_operation(self, gadget):
"""Verify NoOperation gadgets. """ |
# Constraints on memory locations.
# mem_constrs = [self.analyzer.get_memory("pre") != self.analyzer.get_memory("post")]
mem_constrs = [self.analyzer.get_memory_curr("pre").__neq__(self.analyzer.get_memory_curr("post"))]
# Constraints on flags.
flags_constrs = []
for name in self._arch_info.registers_flags:
var_initial = self.analyzer.get_register_expr(name, mode="pre")
var_final = self.analyzer.get_register_expr(name, mode="post")
flags_constrs += [var_initial != var_final]
# Constraints on registers.
reg_constrs = []
for name in self._arch_info.registers_gp_base:
var_initial = self.analyzer.get_register_expr(name, mode="pre")
var_final = self.analyzer.get_register_expr(name, mode="post")
reg_constrs += [var_initial != var_final]
# Make a big OR expression.
constrs = mem_constrs + flags_constrs + reg_constrs
constrs = [reduce(lambda c, acc: acc | c, constrs[1:], constrs[0])]
return constrs |
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def infer_operands_size(operands):
"""Infer x86 instruction operand size based on other operands. """ |
size = None
for oprnd in operands:
if oprnd.size:
size = oprnd.size
break
if size:
for oprnd in operands:
if not oprnd.size:
oprnd.size = size
else:
for oprnd in operands:
if isinstance(oprnd, X86ImmediateOperand) and not oprnd.size:
oprnd.size = arch_info.architecture_size |
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def parse_operand(string, location, tokens):
"""Parse an x86 instruction operand. """ |
mod = " ".join(tokens.get("modifier", ""))
if "immediate" in tokens:
imm = parse_immediate("".join(tokens["immediate"]))
size = modifier_size.get(mod, None)
oprnd = X86ImmediateOperand(imm, size)
if "register" in tokens:
name = tokens["register"]
size = arch_info.registers_size[tokens["register"]]
oprnd = X86RegisterOperand(name, size)
if "memory" in tokens:
seg_reg = tokens.get("segment", None)
base_reg = tokens.get("base", None)
index_reg = tokens.get("index", None)
scale_imm = int(tokens.get("scale", "0x1"), 16)
displ_imm = int("".join(tokens.get("displacement", "0x0")), 16)
oprnd = X86MemoryOperand(seg_reg, base_reg, index_reg, scale_imm, displ_imm)
oprnd.modifier = mod
if not oprnd.size and oprnd.modifier:
oprnd.size = modifier_size[oprnd.modifier]
return oprnd |
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def execute_lite(self, instructions, context=None):
"""Execute a list of instructions. It does not support loops. """ |
if context:
self.__cpu.registers = dict(context)
for instr in instructions:
self.__execute_one(instr)
return dict(self.__cpu.registers), self.__mem |
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def reset(self):
"""Reset emulator. All registers and memory are reset. """ |
self.__mem.reset()
self.__cpu.reset()
self.__tainter.reset()
# Instructions pre and post handlers.
self.__instr_handler_pre = None, None
self.__instr_handler_post = None, None
self.__set_default_handlers() |
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def __execute_bsh(self, instr):
"""Execute BSH instruction. """ |
op0_val = self.read_operand(instr.operands[0])
op1_val = self.read_operand(instr.operands[1])
op1_size = instr.operands[1].size
# Check sign bit.
if extract_sign_bit(op1_val, op1_size) == 0:
op2_val = op0_val << op1_val
else:
op2_val = op0_val >> twos_complement(op1_val, op1_size)
self.write_operand(instr.operands[2], op2_val)
return None |
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def __execute_ldm(self, instr):
"""Execute LDM instruction. """ |
assert instr.operands[0].size == self.__mem.address_size
assert instr.operands[2].size in [8, 16, 32, 64, 128, 256]
# Memory address.
op0_val = self.read_operand(instr.operands[0])
# Data.
op2_val = self.read_memory(op0_val, instr.operands[2].size // 8)
self.write_operand(instr.operands[2], op2_val)
return None |
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def __execute_stm(self, instr):
"""Execute STM instruction. """ |
assert instr.operands[0].size in [8, 16, 32, 64, 128, 256]
assert instr.operands[2].size == self.__mem.address_size
op0_val = self.read_operand(instr.operands[0]) # Data.
op2_val = self.read_operand(instr.operands[2]) # Memory address.
op0_size = instr.operands[0].size
self.write_memory(op2_val, op0_size // 8, op0_val)
return None |
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def __execute_str(self, instr):
"""Execute STR instruction. """ |
op0_val = self.read_operand(instr.operands[0])
self.write_operand(instr.operands[2], op0_val)
return None |
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def __execute_bisz(self, instr):
"""Execute BISZ instruction. """ |
op0_val = self.read_operand(instr.operands[0])
op2_val = 1 if op0_val == 0 else 0
self.write_operand(instr.operands[2], op2_val)
return None |
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def __execute_jcc(self, instr):
"""Execute JCC instruction. """ |
op0_val = self.read_operand(instr.operands[0]) # Branch condition.
op2_val = self.read_operand(instr.operands[2]) # Target address.
return op2_val if op0_val != 0 else None |
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def __execute_undef(self, instr):
"""Execute UNDEF instruction. """ |
op2_val = random.randint(0, instr.operands[2].size)
self.write_operand(instr.operands[2], op2_val)
return None |
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def __execute_sext(self, instr):
"""Execute SEXT instruction. """ |
op0_size = instr.operands[0].size
op2_size = instr.operands[2].size
op0_val = self.read_operand(instr.operands[0])
op0_msb = extract_sign_bit(op0_val, op0_size)
op2_mask = (2**op2_size-1) & ~(2**op0_size-1) if op0_msb == 1 else 0x0
op2_val = op0_val | op2_mask
self.write_operand(instr.operands[2], op2_val)
return None |
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Description:
def get_init(self):
"""Return initial name. """ |
suffix = self._separator + "%s" % str(self._counter_init)
return self._base_name + suffix |
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def get_current(self):
"""Return current name. """ |
suffix = self._separator + "%s" % str(self._counter_curr)
return self._base_name + suffix |
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def get_next(self):
"""Return next name. """ |
self._counter_curr += 1
suffix = self._separator + "%s" % str(self._counter_curr)
return self._base_name + suffix |
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def check_path_satisfiability(code_analyzer, path, start_address):
"""Check satisfiability of a basic block path. """ |
start_instr_found = False
sat = False
# Traverse basic blocks, translate its instructions to SMT
# expressions and add them as assertions.
for bb_curr, bb_next in zip(path[:-1], path[1:]):
logger.info("BB @ {:#x}".format(bb_curr.address))
# For each instruction...
for instr in bb_curr:
# If the start instruction have not been found, keep
# looking...
if not start_instr_found:
if instr.address == start_address:
start_instr_found = True
else:
continue
logger.info("{:#x} {}".format(instr.address, instr))
# For each REIL instruction...
for reil_instr in instr.ir_instrs:
logger.info("{:#x} {:02d} {}".format(reil_instr.address >> 0x8, reil_instr.address & 0xff,
reil_instr))
if reil_instr.mnemonic == ReilMnemonic.JCC:
# Check that the JCC is the last instruction of
# the basic block (skip CALL instructions.)
if instr.address + instr.size - 1 != bb_curr.end_address:
logger.error("Unexpected JCC instruction: {:#x} {} ({})".format(instr.address,
instr,
reil_instr))
# raise Exception()
continue
# Make sure branch target address from current
# basic block is the start address of the next.
assert(bb_curr.taken_branch == bb_next.address or
bb_curr.not_taken_branch == bb_next.address or
bb_curr.direct_branch == bb_next.address)
# Set branch condition accordingly.
if bb_curr.taken_branch == bb_next.address:
branch_var_goal = 0x1
elif bb_curr.not_taken_branch == bb_next.address:
branch_var_goal = 0x0
else:
continue
# Add branch condition goal constraint.
code_analyzer.add_constraint(code_analyzer.get_operand_expr(reil_instr.operands[0]) == branch_var_goal)
# The JCC instruction was the last within the
# current basic block. End this iteration and
# start next one.
break
# Translate and add SMT expressions to the solver.
code_analyzer.add_instruction(reil_instr)
sat = code_analyzer.check() == 'sat'
logger.info("BB @ {:#x} sat? {}".format(bb_curr.address, sat))
if not sat:
break
# Return satisfiability.
return sat |
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Description:
def to_string(mnemonic):
"""Return the string representation of the given mnemonic. """ |
strings = {
# Arithmetic Instructions
ReilMnemonic.ADD: "add",
ReilMnemonic.SUB: "sub",
ReilMnemonic.MUL: "mul",
ReilMnemonic.DIV: "div",
ReilMnemonic.MOD: "mod",
ReilMnemonic.BSH: "bsh",
# Bitwise Instructions
ReilMnemonic.AND: "and",
ReilMnemonic.OR: "or",
ReilMnemonic.XOR: "xor",
# Data Transfer Instructions
ReilMnemonic.LDM: "ldm",
ReilMnemonic.STM: "stm",
ReilMnemonic.STR: "str",
# Conditional Instructions
ReilMnemonic.BISZ: "bisz",
ReilMnemonic.JCC: "jcc",
# Other Instructions
ReilMnemonic.UNKN: "unkn",
ReilMnemonic.UNDEF: "undef",
ReilMnemonic.NOP: "nop",
# Extensions
ReilMnemonic.SEXT: "sext",
ReilMnemonic.SDIV: "sdiv",
ReilMnemonic.SMOD: "smod",
ReilMnemonic.SMUL: "smul",
}
return strings[mnemonic] |
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def from_string(string):
"""Return the mnemonic represented by the given string. """ |
mnemonics = {
# Arithmetic Instructions
"add": ReilMnemonic.ADD,
"sub": ReilMnemonic.SUB,
"mul": ReilMnemonic.MUL,
"div": ReilMnemonic.DIV,
"mod": ReilMnemonic.MOD,
"bsh": ReilMnemonic.BSH,
# Bitwise Instructions
"and": ReilMnemonic.AND,
"or": ReilMnemonic.OR,
"xor": ReilMnemonic.XOR,
# Data Transfer Instructions
"ldm": ReilMnemonic.LDM,
"stm": ReilMnemonic.STM,
"str": ReilMnemonic.STR,
# Conditional Instructions
"bisz": ReilMnemonic.BISZ,
"jcc": ReilMnemonic.JCC,
# Other Instructions
"unkn": ReilMnemonic.UNKN,
"undef": ReilMnemonic.UNDEF,
"nop": ReilMnemonic.NOP,
# Added Instructions
"sext": ReilMnemonic.SEXT,
"sdiv": ReilMnemonic.SDIV,
"smod": ReilMnemonic.SMOD,
"smul": ReilMnemonic.SMUL,
}
return mnemonics[string] |
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def mnemonic(self, value):
"""Set instruction mnemonic. """ |
if value not in REIL_MNEMONICS:
raise Exception("Invalid instruction mnemonic : %s" % str(value))
self._mnemonic = value |
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def operands(self, value):
"""Set instruction operands. """ |
if len(value) != 3:
raise Exception("Invalid instruction operands : %s" % str(value))
self._operands = value |
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def __taint_load(self, instr):
"""Taint LDM instruction. """ |
# Get memory address.
op0_val = self.__emu.read_operand(instr.operands[0])
# Get taint information.
op0_taint = self.get_memory_taint(op0_val, instr.operands[2].size // 8)
# Propagate taint.
self.set_operand_taint(instr.operands[2], op0_taint) |
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def __taint_store(self, instr):
"""Taint STM instruction. """ |
# Get memory address.
op2_val = self.__emu.read_operand(instr.operands[2])
# Get taint information.
op0_size = instr.operands[0].size
op0_taint = self.get_operand_taint(instr.operands[0])
# Propagate taint.
self.set_memory_taint(op2_val, op0_size // 8, op0_taint) |
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def __taint_move(self, instr):
"""Taint registers move instruction. """ |
# Get taint information.
op0_taint = self.get_operand_taint(instr.operands[0])
# Propagate taint.
self.set_operand_taint(instr.operands[2], op0_taint) |
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def execute(self, asm_instr):
"""Execute an assembler instruction. Args: asm_instr (X86Instruction):
A instruction to execute. Returns: A int. The address of the next instruction to execute. """ |
# Update the instruction pointer.
self.ir_emulator.registers[self.ip] = asm_instr.address + asm_instr.size
# Process syscall.
if self.arch_info.instr_is_syscall(asm_instr):
raise Syscall()
# Process instruction and return next address instruction to execute.
return self.__execute(asm_instr) |
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def ir_instrs(self):
"""Get gadgets IR instructions. """ |
ir_instrs = []
for asm_instr in self._instrs:
ir_instrs += asm_instr.ir_instrs
return ir_instrs |
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def load_symbols_elf(filename):
""" Load the symbol tables contained in the file """ |
f = open(filename, 'rb')
elffile = ELFFile(f)
symbols = []
for section in elffile.iter_sections():
if not isinstance(section, SymbolTableSection):
continue
if section['sh_entsize'] == 0:
logger.warn("Symbol table {} has a sh_entsize of zero.".format(section.name))
continue
logger.info("Symbol table {} contains {} entries.".format(section.name, section.num_symbols()))
for _, symbol in enumerate(section.iter_symbols()):
if describe_symbol_shndx(symbol['st_shndx']) != "UND" and \
describe_symbol_type(symbol['st_info']['type']) == "FUNC":
symbols.append((symbol['st_value'], symbol['st_size'], symbol.name))
f.close()
symbols_by_addr = {
addr: (name, size, True) for addr, size, name in symbols
}
return symbols_by_addr |
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def _classify_no_operation(self, regs_init, regs_fini, mem_fini, written_regs, read_regs):
"""Classify no-operation gadgets. """ |
# TODO: Flags should be taken into account
matches = []
# Check that registers didn't change their value.
regs_changed = any(regs_init[r] != regs_fini[r] for r in regs_init)
# Check that flags didn't change their value.
flags_changed = False
# Check that memory didn't change.
mem_changed = mem_fini.get_write_count() != 0
if not regs_changed and not flags_changed and not mem_changed:
matches.append({
"op": "nop",
})
return matches |
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def _classify_move_register(self, regs_init, regs_fini, mem_fini, written_regs, read_regs):
"""Classify move-register gadgets. """ |
matches = []
regs_init_inv = self._invert_dictionary(regs_init)
# Check for "dst_reg <- src_reg" pattern.
for dst_reg, dst_val in regs_fini.items():
# Make sure the *dst* register was written.
if dst_reg not in written_regs:
continue
for src_reg in regs_init_inv.get(dst_val, []):
# Make sure the *src* register was read.
if src_reg not in read_regs:
continue
# Check restrictions...
if self._arch_regs_size[src_reg] != self._arch_regs_size[dst_reg]:
continue
if src_reg == dst_reg:
continue
if regs_init[dst_reg] == regs_init[src_reg]:
continue
src_reg_ir = ReilRegisterOperand(src_reg, self._arch_regs_size[src_reg])
dst_reg_ir = ReilRegisterOperand(dst_reg, self._arch_regs_size[dst_reg])
matches.append({
"src": [src_reg_ir],
"dst": [dst_reg_ir]
})
return matches |
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def _classify_load_constant(self, regs_init, regs_fini, mem_fini, written_regs, read_regs):
"""Classify load-constant gadgets. """ |
matches = []
# Check for "dst_reg <- constant" pattern.
for dst_reg, dst_val in regs_fini.items():
# Make sure the *dst* register was written.
if dst_reg not in written_regs:
continue
# Check restrictions...
if dst_val == regs_init[dst_reg]:
continue
dst_val_ir = ReilImmediateOperand(dst_val, self._arch_regs_size[dst_reg])
dst_reg_ir = ReilRegisterOperand(dst_reg, self._arch_regs_size[dst_reg])
matches.append({
"src": [dst_val_ir],
"dst": [dst_reg_ir]
})
return matches |
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def _classify_arithmetic(self, regs_init, regs_fini, mem_fini, written_regs, read_regs):
"""Classify binary-operation gadgets. """ |
matches = []
# TODO: Review these restrictions.
op_restrictions = {
"+": lambda x, y: False,
"-": lambda x, y: x == y,
"|": lambda x, y: x == y,
"&": lambda x, y: x == y,
"^": lambda x, y: x == y,
}
# Check for "dst_reg <- src1_reg OP src2_reg" pattern.
for op_name, op_fn in self._binary_ops.items():
for src_1_reg, src_1_val in regs_init.items():
# Make sure the *src* register was read.
if src_1_reg not in read_regs:
continue
for src_2_reg, src_2_val in regs_init.items():
# Make sure the *src* register was read.
if src_2_reg not in read_regs:
continue
for dst_reg, dst_val in regs_fini.items():
# Make sure the *dst* register was written.
if dst_reg not in written_regs:
continue
# Check restrictions.
if self._arch_regs_size[src_1_reg] != self._arch_regs_size[src_2_reg] or \
self._arch_regs_size[src_1_reg] != self._arch_regs_size[dst_reg]:
continue
# Avoid trivial operations.
if op_restrictions[op_name](src_1_reg, src_2_reg):
continue
size = self._arch_regs_size[src_1_reg]
if dst_val == op_fn(src_1_val, src_2_val) & (2**size - 1):
src = sorted([src_1_reg, src_2_reg])
src_ir = [
ReilRegisterOperand(src[0], self._arch_regs_size[src[0]]),
ReilRegisterOperand(src[1], self._arch_regs_size[src[1]])
]
dst_reg_ir = ReilRegisterOperand(dst_reg, self._arch_regs_size[dst_reg])
matches.append({
"src": src_ir,
"dst": [dst_reg_ir],
"op": op_name
})
return matches |
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def _classify_load_memory(self, regs_init, regs_fini, mem_fini, written_regs, read_regs):
"""Classify load-memory gadgets. """ |
matches = []
regs_init_inv = self._invert_dictionary(regs_init)
# Check for "dst_reg <- mem[src_reg + offset]" pattern.
for dst_reg, dst_val in regs_fini.items():
# Make sure the *dst* register was written.
if dst_reg not in written_regs:
continue
dst_size = self._arch_regs_size[dst_reg]
# Look for memory addresses that contain *dst_val*.
for src_addr in mem_fini.read_inverse(dst_val, dst_size // 8):
# Look for registers whose values are used as memory
# addresses.
for src_reg, src_val in regs_init.items():
# Make sure the *src* register was read.
if src_reg not in read_regs:
continue
# Check restrictions.
if self._arch_regs_size[src_reg] != self._address_size:
continue
offset = (src_addr - src_val) & (2**self._address_size - 1)
src_reg_ir = ReilRegisterOperand(src_reg, self._arch_regs_size[src_reg])
src_off_ir = ReilImmediateOperand(offset, self._arch_regs_size[src_reg])
dst_reg_ir = ReilRegisterOperand(dst_reg, self._arch_regs_size[dst_reg])
matches.append({
"src": [src_reg_ir, src_off_ir],
"dst": [dst_reg_ir]
})
# Check for "dst_reg <- mem[offset]" pattern.
for dst_reg, dst_val in regs_fini.items():
# Make sure the *dst* register was written.
if dst_reg not in written_regs:
continue
dst_size = self._arch_regs_size[dst_reg]
for src_addr in mem_fini.read_inverse(dst_val, dst_size // 8):
src_reg_ir = ReilEmptyOperand()
src_off_ir = ReilImmediateOperand(src_addr, self._address_size)
dst_reg_ir = ReilRegisterOperand(dst_reg, self._arch_regs_size[dst_reg])
matches.append({
"src": [src_reg_ir, src_off_ir],
"dst": [dst_reg_ir]
})
return matches |
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def _classify_store_memory(self, regs_init, regs_fini, mem_fini, written_regs, read_regs):
"""Classify store-memory gadgets. """ |
matches = []
regs_init_inv = self._invert_dictionary(regs_init)
# Check for "mem[dst_reg + offset] <- src_reg" pattern.
for src_reg, src_val in regs_init.items():
# Make sure the *src* register was read.
if src_reg not in read_regs:
continue
src_size = self._arch_regs_size[src_reg]
for addr in mem_fini.read_inverse(src_val, src_size // 8):
for dst_reg, dst_val in regs_init.items():
# Make sure the *dst* register was written.
if dst_reg not in read_regs:
continue
# Check restrictions.
if self._arch_regs_size[dst_reg] != self._address_size:
continue
offset = (addr - dst_val) & (2**self._address_size - 1)
src_reg_ir = ReilRegisterOperand(src_reg, self._arch_regs_size[src_reg])
dst_reg_ir = ReilRegisterOperand(dst_reg, self._arch_regs_size[dst_reg])
dst_off_ir = ReilImmediateOperand(offset, self._arch_regs_size[dst_reg])
matches.append({
"src": [src_reg_ir],
"dst": [dst_reg_ir, dst_off_ir]
})
# Check for "mem[offset] <- src_reg" pattern.
for src_reg, src_val in regs_init.items():
# Make sure the *src* register was read.
if src_reg not in read_regs:
continue
src_size = self._arch_regs_size[src_reg]
for addr in mem_fini.read_inverse(src_val, src_size // 8):
offset = addr & (2**self._address_size - 1)
src_reg_ir = ReilRegisterOperand(src_reg, self._arch_regs_size[src_reg])
dst_reg_ir = ReilEmptyOperand()
dst_off_ir = ReilImmediateOperand(offset, self._address_size)
matches.append({
"src": [src_reg_ir],
"dst": [dst_reg_ir, dst_off_ir]
})
return matches |
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def _classify_arithmetic_load(self, regs_init, regs_fini, mem_fini, written_regs, read_regs):
"""Classify arithmetic-load gadgets. """ |
matches = []
# Check for "dst_reg <- dst_reg OP mem[src_reg + offset]" pattern.
for op_name, op_fn in self._binary_ops.items():
for dst_reg, dst_val in regs_fini.items():
# Make sure the *dst* register was read and written.
if dst_reg not in written_regs or dst_reg not in read_regs:
continue
dst_size = self._arch_regs_size[dst_reg]
for addr in mem_fini.get_addresses():
success, val = mem_fini.try_read(addr, dst_size // 8)
if success and dst_val == op_fn(regs_init[dst_reg], val) & (2**dst_size - 1):
for src_reg, src_val in regs_init.items():
# Make sure the *src* register was read.
if src_reg not in read_regs:
continue
# Check restrictions.
if self._arch_regs_size[src_reg] != self._address_size:
continue
offset = (addr - src_val) & (2**self._address_size - 1)
src_reg_ir = ReilRegisterOperand(src_reg, self._arch_regs_size[src_reg])
src_off_ir = ReilImmediateOperand(offset, self._address_size)
dst_reg_ir = ReilRegisterOperand(dst_reg, self._arch_regs_size[dst_reg])
matches.append({
"src": [dst_reg_ir, src_reg_ir, src_off_ir],
"dst": [dst_reg_ir],
"op": op_name
})
# Check for "dst_reg <- dst_reg OP mem[offset]" pattern.
for op_name, op_fn in self._binary_ops.items():
for dst_reg, dst_val in regs_fini.items():
# Make sure the *dst* register was read and written.
if dst_reg not in written_regs or dst_reg not in read_regs:
continue
dst_size = self._arch_regs_size[dst_reg]
for addr in mem_fini.get_addresses():
success, val = mem_fini.try_read(addr, dst_size // 8)
if success and dst_val == op_fn(regs_init[dst_reg], val) & (2**dst_size - 1):
src_reg_ir = ReilEmptyOperand()
src_off_ir = ReilImmediateOperand(addr, self._address_size)
dst_reg_ir = ReilRegisterOperand(dst_reg, self._arch_regs_size[dst_reg])
matches.append({
"src": [dst_reg_ir, src_reg_ir, src_off_ir],
"dst": [dst_reg_ir],
"op": op_name
})
return matches |
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def _classify_arithmetic_store(self, regs_init, regs_fini, mem_fini, written_regs, read_regs):
"""Classify arithmetic-store gadgets. """ |
matches = []
# Check for "m[dst_reg + offset] <- m[dst_reg + offset] OP src_reg" pattern.
for op_name, op_fn in self._binary_ops.items():
for size in [8, 16, 32, 64]:
for addr in mem_fini.get_addresses():
success_read_curr, val_curr = mem_fini.try_read(addr, size // 8)
success_read_prev, val_prev = mem_fini.try_read_prev(addr, size // 8)
if success_read_curr and success_read_prev:
for src_reg, src_val in regs_init.items():
# Make sure the *src* register was read.
if src_reg not in read_regs:
continue
# Check restrictions.
if self._arch_regs_size[src_reg] != size:
continue
if val_curr == op_fn(src_val, val_prev) & (2**size - 1):
# find dst + offset
for dst_reg, dst_val in regs_init.items():
# Make sure the *dst* register was written.
if dst_reg not in read_regs:
continue
# Check restrictions.
if self._arch_regs_size[dst_reg] != self._address_size:
continue
offset = (addr - dst_val) & (2**self._address_size - 1)
src_reg_ir = ReilRegisterOperand(src_reg, self._arch_regs_size[src_reg])
dst_reg_ir = ReilRegisterOperand(dst_reg, self._arch_regs_size[dst_reg])
dst_off_ir = ReilImmediateOperand(offset, self._address_size)
matches.append({
"src": [dst_reg_ir, dst_off_ir, src_reg_ir],
"dst": [dst_reg_ir, dst_off_ir],
"op": op_name
})
# Check for "m[offset] <- m[offset] OP src_reg" pattern.
for op_name, op_fn in self._binary_ops.items():
for size in [8, 16, 32, 64]:
for addr in mem_fini.get_addresses():
success_read_curr, val_curr = mem_fini.try_read(addr, size // 8)
success_read_prev, val_prev = mem_fini.try_read_prev(addr, size // 8)
if success_read_curr and success_read_prev:
for src_reg, src_val in regs_init.items():
# Make sure the *src* register was read.
if src_reg not in read_regs:
continue
# Check restrictions.
if self._arch_regs_size[src_reg] != size:
continue
if val_curr == op_fn(src_val, val_prev) & (2**size - 1):
src_reg_ir = ReilRegisterOperand(src_reg, self._arch_regs_size[src_reg])
dst_reg_ir = ReilEmptyOperand()
dst_off_ir = ReilImmediateOperand(addr, self._address_size)
matches.append({
"src": [dst_reg_ir, dst_off_ir, src_reg_ir],
"dst": [dst_reg_ir, dst_off_ir],
"op": op_name
})
return matches |
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def _init_regs_random(self):
"""Initialize register with random values. """ |
# Generate random values and make sure they are all different.
values = set()
while len(values) != len(self._arch_regs_parent):
values.add(random.randint(0, 2**self._arch_info.operand_size - 1))
values = list(values)
# Assign random values to registers.
regs = {}
for idx, reg in enumerate(self._arch_regs_parent):
regs[reg] = values[idx] & (2**self._arch_regs_size[reg] - 1)
return regs |
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def _compute_mod_regs(self, regs_init, regs_fini):
"""Compute modified registers. """ |
assert regs_init.keys() == regs_fini.keys()
modified_regs = []
for reg in regs_init:
if regs_init[reg] != regs_fini[reg]:
modified_regs.append(reg)
return modified_regs |
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def _invert_dictionary(self, d):
"""Invert a dictionary. """ |
inv_dict = {}
for k, v in d.items():
inv_dict[v] = inv_dict.get(v, [])
inv_dict[v] += [k]
return inv_dict |
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def _print_memory(self, memory):
"""Print memory. """ |
for addr, value in memory.items():
print(" 0x%08x : 0x%08x (%d)" % (addr, value, value)) |
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def _print_registers(self, registers):
"""Print registers. """ |
for reg, value in registers.items():
print(" %s : 0x%08x (%d)" % (reg, value, value)) |
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def bb_get_instr_max_width(basic_block):
"""Get maximum instruction mnemonic width """ |
asm_mnemonic_max_width = 0
for instr in basic_block:
if len(instr.mnemonic) > asm_mnemonic_max_width:
asm_mnemonic_max_width = len(instr.mnemonic)
return asm_mnemonic_max_width |
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def end_address(self):
"""Get basic block end address. """ |
if self._instrs is []:
return None
return self._instrs[-1].address + self._instrs[-1].size - 1 |
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def size(self):
"""Get basic block size. """ |
if self._instrs is []:
return None
return sum([instr.size for instr in self._instrs]) |
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def branches(self):
"""Get basic block branches. """ |
branches = []
if self._taken_branch:
branches += [(self._taken_branch, 'taken')]
if self._not_taken_branch:
branches += [(self._not_taken_branch, 'not-taken')]
if self._direct_branch:
branches += [(self._direct_branch, 'direct')]
return branches |
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def _compute_register_list(self, operand):
"""Return operand register list. """ |
ret = []
for reg_range in operand.reg_list:
if len(reg_range) == 1:
ret.append(ReilRegisterOperand(reg_range[0].name, reg_range[0].size))
else:
reg_num = int(reg_range[0].name[1:]) # Assuming the register is named with one letter + number
reg_end = int(reg_range[1].name[1:])
if reg_num > reg_end:
raise NotImplementedError("Instruction Not Implemented: Invalid register range.")
while reg_num <= reg_end:
ret.append(ReilRegisterOperand(reg_range[0].name[0] + str(reg_num), reg_range[0].size))
reg_num = reg_num + 1
return ret |
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def translate(self, instruction):
"""Return IR representation of an instruction. """ |
try:
trans_instrs = self.__translate(instruction)
except NotImplementedError:
unkn_instr = self._builder.gen_unkn()
unkn_instr.address = instruction.address << 8 | (0x0 & 0xff)
trans_instrs = [unkn_instr]
self._log_not_supported_instruction(instruction)
except Exception:
self._log_translation_exception(instruction)
raise
return trans_instrs |
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def read(self, address, size):
"""Read arbitrary size content from memory. """ |
value = 0x0
for i in range(0, size):
value |= self._read_byte(address + i) << (i * 8)
return value |
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def _read_byte(self, address):
"""Read a byte from memory. """ |
# Initialize memory location with a random value.
if address not in self._memory:
self._memory[address] = random.randint(0x00, 0xff)
return self._memory[address] |
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def write(self, address, size, value):
"""Write arbitrary size content to memory. """ |
for i in range(0, size):
self.__write_byte(address + i, (value >> (i * 8)) & 0xff) |
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def read_inverse(self, value, size):
"""Return a list of memory addresses that contain the specified value. """ |
addr_candidates = [addr for addr, val in self._memory.items() if val == (value & 0xff)]
addr_matches = []
for addr in addr_candidates:
match = True
for i in range(0, size):
byte_curr = (value >> (i * 8)) & 0xff
try:
match = self._memory[addr + i] == byte_curr
except KeyError:
match = False
if not match:
break
if match:
addr_matches += [addr]
return addr_matches |
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def try_read(self, address, size):
"""Try to read memory content at specified address. If any location was not written before, it returns a tuple (False, None). Otherwise, it returns (True, memory content). """ |
value = 0x0
for i in range(0, size):
addr = address + i
if addr in self._memory:
value |= self._read_byte(addr) << (i * 8)
else:
return False, None
return True, value |
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def try_read_prev(self, address, size):
"""Try to read previous memory content at specified address. If any location was not written before, it returns a tuple (False, None). Otherwise, it returns (True, memory content). """ |
value = 0x0
for i in range(0, size):
addr = address + i
if addr in self.__memory_prev:
_, val_byte = self.__try_read_byte_prev(addr)
value |= val_byte << (i * 8)
else:
return False, None
return True, value |
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def __try_read_byte_prev(self, address):
"""Read previous value for memory location. Return a tuple (True, Byte) in case of successful read, (False, None) otherwise. """ |
# Initialize memory location with a random value
if address not in self.__memory_prev:
return False, None
return True, self.__memory_prev[address] |
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def __write_byte(self, address, value):
"""Write byte in memory. """ |
# Save previous address content.
if address in self._memory:
self.__memory_prev[address] = self._memory[address]
self._memory[address] = value & 0xff |
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def gen_add(src1, src2, dst):
"""Return an ADD instruction. """ |
assert src1.size == src2.size
return ReilBuilder.build(ReilMnemonic.ADD, src1, src2, dst) |
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def gen_sub(src1, src2, dst):
"""Return a SUB instruction. """ |
assert src1.size == src2.size
return ReilBuilder.build(ReilMnemonic.SUB, src1, src2, dst) |
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def gen_mul(src1, src2, dst):
"""Return a MUL instruction. """ |
assert src1.size == src2.size
return ReilBuilder.build(ReilMnemonic.MUL, src1, src2, dst) |
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def gen_div(src1, src2, dst):
"""Return a DIV instruction. """ |
assert src1.size == src2.size
return ReilBuilder.build(ReilMnemonic.DIV, src1, src2, dst) |
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def gen_mod(src1, src2, dst):
"""Return a MOD instruction. """ |
assert src1.size == src2.size
return ReilBuilder.build(ReilMnemonic.MOD, src1, src2, dst) |
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def gen_bsh(src1, src2, dst):
"""Return a BSH instruction. """ |
assert src1.size == src2.size
return ReilBuilder.build(ReilMnemonic.BSH, src1, src2, dst) |
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def gen_and(src1, src2, dst):
"""Return an AND instruction. """ |
assert src1.size == src2.size
return ReilBuilder.build(ReilMnemonic.AND, src1, src2, dst) |
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def gen_or(src1, src2, dst):
"""Return an OR instruction. """ |
assert src1.size == src2.size
return ReilBuilder.build(ReilMnemonic.OR, src1, src2, dst) |
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def gen_xor(src1, src2, dst):
"""Return a XOR instruction. """ |
assert src1.size == src2.size
return ReilBuilder.build(ReilMnemonic.XOR, src1, src2, dst) |
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def gen_ldm(src, dst):
"""Return a LDM instruction. """ |
return ReilBuilder.build(ReilMnemonic.LDM, src, ReilEmptyOperand(), dst) |
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def gen_stm(src, dst):
"""Return a STM instruction. """ |
return ReilBuilder.build(ReilMnemonic.STM, src, ReilEmptyOperand(), dst) |
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def gen_str(src, dst):
"""Return a STR instruction. """ |
return ReilBuilder.build(ReilMnemonic.STR, src, ReilEmptyOperand(), dst) |
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def gen_bisz(src, dst):
"""Return a BISZ instruction. """ |
return ReilBuilder.build(ReilMnemonic.BISZ, src, ReilEmptyOperand(), dst) |
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def gen_jcc(src, dst):
"""Return a JCC instruction. """ |
return ReilBuilder.build(ReilMnemonic.JCC, src, ReilEmptyOperand(), dst) |
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def gen_unkn():
"""Return an UNKN instruction. """ |
empty_reg = ReilEmptyOperand()
return ReilBuilder.build(ReilMnemonic.UNKN, empty_reg, empty_reg, empty_reg) |
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def gen_undef():
"""Return an UNDEF instruction. """ |
empty_reg = ReilEmptyOperand()
return ReilBuilder.build(ReilMnemonic.UNDEF, empty_reg, empty_reg, empty_reg) |
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def gen_nop():
"""Return a NOP instruction. """ |
empty_reg = ReilEmptyOperand()
return ReilBuilder.build(ReilMnemonic.NOP, empty_reg, empty_reg, empty_reg) |
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def gen_sext(src, dst):
"""Return a SEXT instruction. """ |
assert src.size <= dst.size
empty_reg = ReilEmptyOperand()
return ReilBuilder.build(ReilMnemonic.SEXT, src, empty_reg, dst) |
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def gen_sdiv(src1, src2, dst):
"""Return a SDIV instruction. """ |
assert src1.size == src2.size
return ReilBuilder.build(ReilMnemonic.SDIV, src1, src2, dst) |
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def gen_smod(src1, src2, dst):
"""Return a SMOD instruction. """ |
assert src1.size == src2.size
return ReilBuilder.build(ReilMnemonic.SMOD, src1, src2, dst) |
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def gen_smul(src1, src2, dst):
"""Return a SMUL instruction. """ |
assert src1.size == src2.size
return ReilBuilder.build(ReilMnemonic.SMUL, src1, src2, dst) |
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