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78c261f | 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 | # Multi-Cycle RISC Processor (MCRP)
This repository contains the Verilog implementation of a Multi-Cycle RISC Processor (MCRP). The processor is designed to execute a subset of RISC instructions and is organized into five main stages: Instruction Fetch (IF), Instruction Decode (ID), Execute (EX), Memory Access (MEM), and Write Back (WB). The processor supports various control signals and operations, providing a flexible and extensible architecture.
## Processor Specifications
- **Instruction Size**: 32 bits
- **Registers**: 32 general-purpose registers (R0 to R31)
- **Special Registers**: Program Counter (PC), Stack Pointer (SP)
- **Control Stack**: Used for saving return addresses
- **Instruction Types**: R-type, I-type, J-type, S-type
- **Memory Organization**: Separate data and instruction memories.
## Modules
1. **MCRP (Main Processor Module):**
- Inputs: clk, reset
- Outputs: Various control signals, register outputs, ALU, and memory results.
2. **State Machine (IF, ID, EX, MEM, WB):**
- Determines the current state of the processor and transitions based on the instruction being executed.
3. **ALU (alu):**
- Performs operations like ADD, SUB, AND, SLL, SLR based on the instruction type.
4. **Memory (mem):**
- Handles memory access for load (LW) and store (SW) operations.
5. **Stack Memory (stack):**
- Manages the control stack for saving return addresses.
6. **Control Unit (ctrl):**
- Generates control signals for various operations in the processor.
## State Machine
- **States**: IF (Instruction Fetch), ID (Instruction Decode), EX (Execute), MEM (Memory Access), WB (Write Back)
- **State Transitions**: Based on the type of instruction being executed and the current state.
## Features
- Supports a variety of instructions (R-type, I-type, J-type, S-type).
- Flexibility in ALU operations and memory access.
- Separate data and instruction memories.
- Control signals for register write, memory read/write, ALU operations.
## Usage
To use the MCRP processor, instantiate the module and provide appropriate input signals. Ensure that the clock (clk) and reset (reset) signals are connected properly.
## Testing
Thoroughly test the processor to validate functionality and correctness. A testbench code (`new_tb.v`) is included in the same folder for testing purposes.
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