- 0thbit_CRC_parallel
- Abdelrahman1810_SPI_Slave_with_Single_Port_RAM
- Amr-HAlahla_Multi-Cycle-RISC-Processor-In-Verilog
- CharanK-glitch_RV32I
- Crimsonninja_senior_design_puf
- MohamedHussein27_AMPA_APB4_Protocol
- MohamedHussein27_RISC-V-Single-Cycle-Implementation
- MohamedHussein27_SPI_Slave_With_Single_Port_Memory
- Mr-Bossman_KISC-V
- OrsuVenkataKrishnaiah1235_RTL-Coding
- Vaibhav-Gunthe_Verilog-Projects
- Varunkumar0610_RISC-V-32I-5-stage-Pipeline-Core
- Weiyet_RTLStructLib
- WilliamZhang20_ECE298A-TPU
- accomdemy_accomdemy_rv32i
- akira2963753_Pipelined-RV32-SoC
- alexforencich_verilog-axi
- apfaudio_eurorack-pmod
- arhamhashmi01_Axi4-lite
- ayushc13_32-bit-RISC-processor-using-HDL-Verilog
- biren15_Design-and-Implementation-of-a-Cruise-Control-System
- biren15_Design-and-Verification-of-LDPC-Decoder
- chili-chips-ba_wireguard-fpga
- circuitvalley_USB_C_Industrial_Camera_FPGA_USB3
- cocotb_cocotb-bus
- daringpatil3134_SPI_Serial_Peripheral_Interface_Verilog_Modules
- dashboard
- defano_digital-design
- dpretet_async_fifo
- fcayci_sv-digital-design
- mciepluc_cocotb-coverage
- meiniKi_RV32I_SC_Logisim
- mnmhdanas_Router-1-x-3-
- mnmhdanas_UART-protocol
- nimanaqavi_Verilog-MathFunctions
- projf_isle
- qossayrida_PipelineProcessorDesign
- roo16kie_MAC_Verilog
- saivittalb_simd-processor-verification
- scarv_xcrypto
- shahsaumya00_Floating-Point-Adder
- snbk001_100DaysofRTL
- srpoyrek_RISC-V
- sumukhathrey_Verilog_ASIC_Design
- thedatabusdotio_fpga-ml-accelerator
- thejefflarson_little-cpu
- ttchisholm_10g-low-latency-ethernet
- wicker_SystemVerilog-FSM
- yaseensalah_Digital-Design-of-FIR-Filter
- zhangxin6_iverilog_testbench