File size: 677 Bytes
78c261f | 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 | module memory (
input clk,
input [31:0] addr,
input [31:0] data_in,
input write_signal,
input read_signal,
output reg [31:0] data_out
);
reg [31:0] mem [0:1023]; // Assuming 1024 32-bit words in memory
always @(posedge clk or read_signal or write_signal) begin
if (write_signal) begin
mem[addr] = data_in;
end
else if (read_signal) begin
data_out = mem[addr];
end
end
// Initialize memory with some random values
initial begin
integer i;
for (i = 0; i < 1024; i = i + 1) begin
mem[i] = i;
end
end
endmodule |