ayushc13_32-bit-RISC-processor-using-HDL-Verilog/testbenches.json

[
  {
    "file_path": "mips32_tb1.v",
    "tb_type": "verilog",
    "simulator": "icarus",
    "makefile_path": null,
    "top_module": "mips32",
    "rtl_files": [
      "mips32.v"
    ]
  },
  {
    "file_path": "mips32_tb2.v",
    "tb_type": "verilog",
    "simulator": "icarus",
    "makefile_path": null,
    "top_module": "mips32",
    "rtl_files": [
      "mips32.v"
    ]
  }
]