Amr-HAlahla_Multi-Cycle-RISC-Processor-In-Verilog/candidates/stack_control__stack_control/sim.sh

#!/usr/bin/env bash
set -euo pipefail
if ! command -v python &>/dev/null; then
    _TMPBIN=$(mktemp -d)
    ln -s "$(command -v python3)" "$_TMPBIN/python"
    export PATH="$_TMPBIN:$PATH"
    trap 'rm -rf "$_TMPBIN"' EXIT
fi
SRCDIR="$(cd "$(dirname "${BASH_SOURCE[0]}")" && pwd)"
iverilog -g2012 -o /tmp/sim_stack_control "$SRCDIR/Source Code/ControlUnits/stack_control_tb.v" "$SRCDIR/Source Code/ControlUnits/stack_control.v"
vvp /tmp/sim_stack_control -fst