Amr-HAlahla_Multi-Cycle-RISC-Processor-In-Verilog/sim_script_map.json

{
  "Source Code/ALU/alu_tb.v": "alu_sim.sh",
  "Source Code/ControlUnits/main_control_tb.v": "control_unit_sim.sh",
  "Source Code/ControlUnits/pc_control_tb.v": "pc_control_sim.sh",
  "Source Code/ControlUnits/stack_control_tb.v": "stack_control_sim.sh",
  "Source Code/Memory/memory_tb.v": "memory_sim.sh",
  "Source Code/Memory/memory_tb2.v": "memory_sim.sh",
  "Source Code/extenders/immediate_extender_tb.v": "immediate_extender_sim.sh",
  "Source Code/instruction_memory/instruction_memory_tb.v": "instruction_memory_sim.sh",
  "Source Code/registers/register_file_tb.v": "register_file_sim.sh",
  "Source Code/stack/stack_memory_tb.v": "stack_memory_sim.sh"
}