Amr-HAlahla_Multi-Cycle-RISC-Processor-In-Verilog/waveform_map.json

{
  "Source Code/ALU/alu_tb.v": "wave_alu.fst",
  "Source Code/ControlUnits/main_control_tb.v": "wave_control_unit.fst",
  "Source Code/ControlUnits/pc_control_tb.v": "wave_pc_control.fst",
  "Source Code/ControlUnits/stack_control_tb.v": "wave_stack_control.fst",
  "Source Code/extenders/immediate_extender_tb.v": "wave_immediate_extender.fst",
  "Source Code/instruction_memory/instruction_memory_tb.v": "wave_instruction_memory.fst",
  "Source Code/registers/register_file_tb.v": "wave_register_file.fst",
  "Source Code/stack/stack_memory_tb.v": "wave_stack_memory.fst"
}