saivittalb_simd-processor-verification/simulations.jsonl

{"tb_file_path":"src/vlog/processor_tb.v","simulator":"iverilog","top_module":"CPUtop","work_subdir":null,"requires_submodules":false,"compile":{"args":["-g2012"],"sources":["src/vlog/CPUtop.v","src/vlog/SIMDadd.v","src/vlog/SIMDmultiply.v","src/vlog/SIMDshifter.v","src/vlog/processor_tb.v"]},"run":{"args":["-fst"]},"waveform":"wave_CPUtop.fst"}