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Weiyet_RTLStructLib/source/Doubly_Linked_List/src/doubly_linked_list.sv

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+`timescale 1ns / 1ps
+//////////////////////////////////////////////////////////////////////////////////
+// Create Date: 09/10/2024 08:46:52 PM
+// Last Update: 02/20/2025 10:17 PM
+// Module Name: doubly_linked_list
+// Description: Supported Operation 
+//             0. Read_Addr(addr_in) -> data_out 
+//             1. Insert_Addr(addr_in, data_in) 
+//             5. Insert_Index(addr_in, data_in)
+//             2. Delete_Value(data_in)
+//             3. Delete_Addr(addr_in)
+//             7. Delete_Index(addr_in) 
+// Additional Comments: .
+// 
+//////////////////////////////////////////////////////////////////////////////////
+
+
+module doubly_linked_list #(
+    parameter DATA_WIDTH = 8, // Data Width
+    parameter MAX_NODE = 8  // Maximum number of nodes stored
+    )(
+        input rst,
+        input clk,
+        input [DATA_WIDTH-1:0] data_in, 
+        input [ADDR_WIDTH-1:0] addr_in, // index of element
+        input [2:0] op, // 0: Read(addr_in); 1: Delete_value(data_in); 2: Push_back(data_in); 3: Push_front(data_in)
+        input op_start, 
+        output reg op_done,
+        output reg [DATA_WIDTH-1:0] data_out,
+        output reg [ADDR_WIDTH-1:0] pre_node_addr, // Addr of pre node
+        output reg [ADDR_WIDTH-1:0] next_node_addr, // Addr of next node
+        // status 
+        output reg [ADDR_WIDTH-1:0] length,
+        output reg [ADDR_WIDTH-1:0] head, // Addr of head
+        output reg [ADDR_WIDTH-1:0] tail, // Addr of tail
+        output wire full, 
+        output wire empty,
+        output reg fault 
+    );
+
+    localparam ADDR_WIDTH = $clog2(MAX_NODE+1); // Reserve {ADDR_WIDTH(1'b1)} as NULL/INVALID ADDR.
+    localparam NODE_WIDTH = $clog2(MAX_NODE);
+    localparam ADDR_NULL = (MAX_NODE);
+
+    // yosys does not support sv typedef
+    // typedef struct {  
+    //     reg [DATA_WIDTH-1:0] data; // RAM
+    //     reg [ADDR_WIDTH-1:0] next_node_addr; // RAM 
+    //     reg [ADDR_WIDTH-1:0] pre_node_addr; // RAM
+    //     reg valid; // Register
+    // } node_st;
+    
+    //node_st node [0:MAX_NODE-1];
+    reg [DATA_WIDTH-1:0] node_data [0:MAX_NODE-1]; // RAM
+    reg [ADDR_WIDTH-1:0] node_next_node_addr [0:MAX_NODE-1]; // RAM
+    reg [ADDR_WIDTH-1:0] node_pre_node_addr [0:MAX_NODE-1]; // RAM
+    reg node_valid [0:MAX_NODE-1]; // Register
+
+    wire [MAX_NODE-1:0] valid_bits;
+    wire op_is_read; 
+    wire op_is_insert_at_addr;
+    wire op_is_insert_at_index;
+    wire op_is_delete_by_addr;
+    wire op_is_delete_by_index;
+    wire op_is_delete_by_value;
+ //   wire addr_match;
+    wire ascending; 
+    wire [ADDR_WIDTH-1:0] head_idx_sel;
+    wire [ADDR_WIDTH-1:0] tail_idx_sel;
+    wire addr_overflow;
+    reg [NODE_WIDTH-1:0] index;
+    reg [ADDR_WIDTH-1:0] cur_ptr; 
+    reg [ADDR_WIDTH-1:0] pre_ptr; 
+    //reg [ADDR_WIDTH-1:0] head; // Addr of head
+    //reg [ADDR_WIDTH-1:0] tail; // Addr of tail
+    reg [2:0] state;
+    reg [2:0] next_state;
+    reg wr_req;
+    reg rd_req;
+    reg valid_rd_buf;
+    reg valid_wr; 
+    reg [ADDR_WIDTH-1:0] next_addr_rd_buf;
+    reg [ADDR_WIDTH-1:0] pre_addr_rd_buf;
+    reg [DATA_WIDTH-1:0] data_rd_buf;
+    reg [ADDR_WIDTH-1:0] target_idx; 
+    reg [ADDR_WIDTH-1:0] next_node_addr_idx;
+    reg [ADDR_WIDTH-1:0] next_node_addr_in;
+    reg [ADDR_WIDTH-1:0] pre_node_addr_idx;
+    reg [ADDR_WIDTH-1:0] pre_node_addr_in;
+
+    integer i;
+    
+    localparam IDLE = 3'b000;
+    localparam FIND_ADDR = 3'b001;
+    localparam FIND_VALUE = 3'b010;
+    localparam FIND_INDEX = 3'b110;
+    localparam INSERT_STG1 = 3'b011;
+    localparam FAULT = 3'b101;
+    localparam EXECUTE = 3'b100;
+
+    assign op_is_read = op[2:0] == 3'd0 & op_start;
+    assign op_is_insert_at_index = op[2:0] == 3'd5 & op_start; 
+    assign op_is_insert_at_addr = op[2:0] == 3'd1 & op_start; 
+    assign op_is_delete_by_value = op[2:0] == 3'd2 & op_start;
+    assign op_is_delete_by_index = op[2:0] == 3'd7 & op_start; 
+    assign op_is_delete_by_addr = op[2:0] == 3'd3 & op_start;
+
+    always @ (posedge clk or posedge rst) begin
+        if (rst) begin
+            for (i = 0; i < MAX_NODE; i = i+1) begin
+                node_data[i] <= {DATA_WIDTH{1'b0}};
+                node_valid[i] <= 1'b0;
+            end
+        end else if (wr_req & state != INSERT_STG1 & target_idx != ADDR_NULL) begin  
+            node_data[target_idx[NODE_WIDTH-1:0]] <= data_in; 
+            node_valid[target_idx[NODE_WIDTH-1:0]] <= valid_wr;
+        end 
+    end
+
+    always @ (posedge clk or posedge rst) begin
+        if (rst) begin
+            for (i = 0; i < MAX_NODE; i = i+1) begin
+                node_next_node_addr[i] <= ADDR_NULL;
+            end
+        end else if (wr_req & next_node_addr_idx != ADDR_NULL) begin  
+            node_next_node_addr[next_node_addr_idx[NODE_WIDTH-1:0]] <= next_node_addr_in;
+        end 
+    end
+    
+    always @ (posedge clk or posedge rst) begin
+        if (rst) begin
+            for (i = 0; i < MAX_NODE; i = i+1) begin
+                node_pre_node_addr[i] <= ADDR_NULL;
+            end
+        end else if (wr_req & pre_node_addr_idx != ADDR_NULL) begin  
+            node_pre_node_addr[pre_node_addr_idx[NODE_WIDTH-1:0]] <= pre_node_addr_in;
+        end 
+    end
+    
+    assign head_idx_sel = op[2] ? 0 : head;
+    assign tail_idx_sel = op[2] ? (length-1) : tail;
+    assign addr_overflow = (op[2] & (addr_in >= length)) | (addr_in >= ADDR_NULL);
+    assign ascending = (addr_in < (length << 2)); 
+   
+    always @ (posedge clk or posedge rst) begin
+        if (rst) begin
+            state <= 3'b0;
+        end else begin
+            state <= next_state; 
+        end
+    end
+   
+    // op_done
+    always @ (*) begin
+        op_done <= 1'b0;
+        rd_req <= 1'b0;
+        wr_req <= 1'b0;
+        target_idx <= ADDR_NULL;
+        valid_wr <= 1'b0;
+        next_node_addr_idx <= ADDR_NULL;
+        next_node_addr_in <= ADDR_NULL;
+        pre_node_addr_idx <= ADDR_NULL;
+        pre_node_addr_in <= ADDR_NULL;
+        fault <= 1'b0;
+        next_state <= IDLE;
+        case(state)
+            IDLE: begin
+                if (op_is_insert_at_addr | op_is_insert_at_index) begin
+                    if (full) begin
+                        next_state <= FAULT; 
+                    end else if (addr_in == head_idx_sel) begin // push_front
+                        // Add new node 
+                        // Next node addr of new node point to head
+                        wr_req <= 1'b1;
+                        target_idx <= find_next_ptr(valid_bits);
+                        valid_wr <= 1'b1;
+                        next_node_addr_idx <= find_next_ptr(valid_bits);
+                        next_node_addr_in <= head;
+                        pre_node_addr_idx <= head;
+                        pre_node_addr_in <= find_next_ptr(valid_bits);
+                        next_state <= EXECUTE;
+                    end else if (addr_overflow) begin // push_back
+                        // Add new node 
+                        // Next node addr of tail point to new node
+                        wr_req <= 1'b1;
+                        target_idx <= find_next_ptr(valid_bits);
+                        valid_wr <= 1'b1;
+                        next_node_addr_idx <= tail;
+                        next_node_addr_in <= find_next_ptr(valid_bits);
+                        pre_node_addr_idx <= find_next_ptr(valid_bits);
+                        pre_node_addr_in <= tail;
+                        next_state <= EXECUTE;                        
+                    end else begin
+                        rd_req <= 1'b1;
+                        target_idx <= op[2]? (ascending ? head : tail) : addr_in;
+                        next_state <= op[2]? FIND_INDEX : FIND_ADDR;
+                    end
+                end else if (op_is_read) begin
+                   if(empty | addr_overflow) begin 
+                      next_state <= FAULT;    
+                   end else begin            
+                      rd_req <= 1'b1;
+                      target_idx <= addr_in;
+                      next_state <= EXECUTE;
+                   end
+                end else if (op_is_delete_by_value) begin 
+                   if(empty) begin
+                      next_state <= FAULT; 
+                   end else begin
+                      rd_req <= 1'b1;
+                      target_idx <= head;
+                      next_state <= FIND_VALUE;
+                   end
+                end else if (op_is_delete_by_addr | op_is_delete_by_index) begin 
+                   if(empty | addr_overflow) begin
+                      next_state <= FAULT; 
+                   end else begin
+                      rd_req <= 1'b1;
+                      target_idx <= op[2] ? (ascending ? head : tail) : addr_in;
+                      next_state <= op[2] ? FIND_INDEX : FIND_ADDR;
+                   end
+                end else if(op_start)begin
+                   next_state <= FAULT; // Invalid operation
+                end else begin 
+                   next_state <= IDLE;
+                end
+            end
+            FIND_ADDR: begin // to get pre pos (pre_ptr)
+                if (!valid_rd_buf) begin
+                    next_state <= FAULT;     
+                end else begin 
+                    if(op_is_delete_by_addr) begin
+                        // update curr pos to invalid
+                        wr_req <= 1'b1;
+                        target_idx <= cur_ptr;
+                        valid_wr <= 1'b0;
+                        // update next_node_addr of pre pos to next pos
+                        next_node_addr_idx <= pre_addr_rd_buf; 
+                        next_node_addr_in <= next_addr_rd_buf;
+                        // update pre_node_addr of next post to pre pos
+                        pre_node_addr_idx <= next_addr_rd_buf;
+                        pre_node_addr_in <= pre_addr_rd_buf;
+                        next_state <= EXECUTE; 
+                    end else if (op_is_insert_at_addr) begin
+                        // insert new pos 
+                        wr_req <= 1'b1;
+                        target_idx <= find_next_ptr(valid_bits);
+                        valid_wr <= 1'b1;    
+                        // update next_node_addr of curr pos to new pos
+                        next_node_addr_idx <= pre_addr_rd_buf; 
+                        next_node_addr_in <= find_next_ptr(valid_bits);  
+                        // update next_node_addr of next pos to neew pos
+                        pre_node_addr_idx <= find_next_ptr(valid_bits);
+                        pre_node_addr_in <= pre_addr_rd_buf;
+                        next_state <= INSERT_STG1;   
+                    end          
+                end 
+            end
+            FIND_INDEX: begin 
+                if (!valid_rd_buf) begin
+                    next_state <= FAULT;     
+                end else if (addr_in == index) begin 
+                    if(op_is_delete_by_index) begin
+                        // update cur pos to invalid
+                        wr_req <= 1'b1;
+                        target_idx <= cur_ptr;
+                        valid_wr <= 1'b0;
+                        // update next_node_addr of pre pos to next pos
+                        next_node_addr_idx <= pre_addr_rd_buf; 
+                        next_node_addr_in <= next_addr_rd_buf;
+                        // update pre_node_addr of next post to pre pos
+                        pre_node_addr_idx <= next_addr_rd_buf;
+                        pre_node_addr_in <= pre_addr_rd_buf;
+                        next_state <= EXECUTE; 
+                    end else if (op_is_insert_at_index) begin
+                        // insert new pos 
+                        wr_req <= 1'b1;
+                        target_idx <= find_next_ptr(valid_bits);
+                        valid_wr <= 1'b1;    
+                        // update next_node_addr of curr pos to new pos
+                        next_node_addr_idx <= pre_addr_rd_buf; 
+                        next_node_addr_in <= find_next_ptr(valid_bits);  
+                        // update next_node_addr of next pos to neew pos
+                        pre_node_addr_idx <= find_next_ptr(valid_bits);
+                        pre_node_addr_in <= pre_addr_rd_buf;
+                        next_state <= INSERT_STG1;         
+                    end 
+                end else if ((ascending & index >= (length - 1)) | (!ascending & index == 0)) begin
+                    next_state <= FAULT;            
+                end else begin
+                   rd_req <= 1'b1;
+                   target_idx <= ascending ? next_addr_rd_buf : pre_addr_rd_buf;
+                   next_state <= FIND_INDEX;     
+                end
+            end
+            FIND_VALUE: begin  
+                if(data_rd_buf == data_in) begin 
+                    // update curr pos to invalid
+                    wr_req <= 1'b1;
+                    target_idx <= cur_ptr;
+                    valid_wr <= 1'b0;
+                    // update next_node_addr of pre pos to next pos
+                    next_node_addr_idx <= pre_ptr; 
+                    next_node_addr_in <= next_addr_rd_buf;
+                    // update pre_node_addr of next pos to pre pos
+                    pre_node_addr_idx <= next_addr_rd_buf; 
+                    pre_node_addr_in <= pre_ptr;
+                    next_state <= EXECUTE;    
+                end else if (index >= (length - 1)) begin
+                    next_state <= FAULT; 
+                end else begin
+                   rd_req <= 1'b1;
+                   target_idx <= next_addr_rd_buf;
+                   next_state <= FIND_VALUE;
+                end
+            end 
+            INSERT_STG1: begin
+                wr_req <= 1'b1; 
+                next_node_addr_idx <= cur_ptr; //new inserted node
+                next_node_addr_in <= pre_ptr;
+                pre_node_addr_idx <= pre_ptr; 
+                pre_node_addr_in <= cur_ptr;
+                next_state <= EXECUTE;  
+            end
+            EXECUTE: begin
+                op_done <= 1'b1;
+                fault <= op_is_read & !valid_rd_buf;
+                next_state <= IDLE;
+            end 
+            FAULT: begin
+                fault <= 1'b1;
+                op_done <= 1'b1;
+                next_state <= IDLE;
+            end 
+            default: begin
+                next_state <= IDLE;
+            end
+       endcase
+    end
+
+    always @ (posedge clk, posedge rst) begin
+        if (rst) begin
+            index <= 0;
+        end else if (state == FIND_VALUE) begin
+            index <= index + 1;
+        end else if (state == FIND_INDEX) begin
+            index <= ascending ? (index + 1) : (index - 1);
+        end else if (!ascending & next_state == FIND_INDEX) begin
+            index <= length - 1; 
+        end else begin
+            index <= 0;
+        end
+    end
+
+    always @ (posedge clk, posedge rst) begin
+        if (rst) begin
+            data_rd_buf <= {DATA_WIDTH{1'b0}};
+            valid_rd_buf <= 1'b0;
+            next_addr_rd_buf <= {ADDR_WIDTH{1'b0}};
+            pre_addr_rd_buf <= {ADDR_WIDTH{1'b0}};
+        end else if (rd_req) begin
+            data_rd_buf <=  node_data[target_idx];
+            valid_rd_buf <= node_valid[target_idx];
+            next_addr_rd_buf <= node_next_node_addr[target_idx];
+            pre_addr_rd_buf <= node_pre_node_addr[target_idx];
+        end
+    end
+    
+    always @ (posedge clk, posedge rst) begin
+        if (rst) begin
+            data_out <= {DATA_WIDTH{1'b0}};
+            next_node_addr <= ADDR_NULL;
+            pre_node_addr <= ADDR_NULL;
+        end else if (op_is_read & (next_state == EXECUTE)) begin
+            data_out <=  node_data[target_idx];
+            next_node_addr <= (addr_in == tail) ? ADDR_NULL : node_next_node_addr[target_idx];
+            pre_node_addr <= (addr_in == head) ? ADDR_NULL : node_pre_node_addr[target_idx];
+        end
+    end
+   
+    always @ (posedge clk, posedge rst) begin
+        if (rst) begin
+            cur_ptr <= ADDR_NULL;
+            pre_ptr <= ADDR_NULL;
+        end else if(next_state == IDLE) begin
+            cur_ptr <= ADDR_NULL;
+            pre_ptr <= ADDR_NULL;
+        end
+        else if (rd_req | wr_req) begin
+            cur_ptr <= target_idx;
+            pre_ptr <= cur_ptr;
+        end
+    end
+
+    genvar j;
+    // Status
+    generate 
+        for (j = 0; j < MAX_NODE; j = j+1) begin
+            assign valid_bits[j] = node_valid[j];
+        end
+    endgenerate
+
+    assign full = & valid_bits;
+    assign empty = ~(| valid_bits);
+    
+    always @ (posedge clk or posedge rst) begin
+        if (rst) begin
+            head <= ADDR_NULL;
+        end else if ((op_is_insert_at_addr | op_is_insert_at_index) & ((addr_in == head_idx_sel) | empty) & (next_state == EXECUTE)) begin //INVALID addr
+            head <= find_next_ptr(valid_bits);
+        end else if ((op_is_delete_by_value | op_is_delete_by_addr | op_is_delete_by_index) & (next_state == EXECUTE) & (length == 1)) begin
+            head <= ADDR_NULL;
+        end else if ((op_is_delete_by_addr | op_is_delete_by_index) & (addr_in == head_idx_sel)  & (next_state == EXECUTE)) begin
+            head <= next_addr_rd_buf;
+        end else if (op_is_delete_by_value & (cur_ptr == head) & (next_state == EXECUTE)) begin
+            head <= next_addr_rd_buf;
+        end
+    end 
+    
+    always @ (posedge clk or posedge rst) begin
+        if (rst) begin
+            tail <= ADDR_NULL;
+        end else if ((op_is_insert_at_addr | op_is_insert_at_index) & (addr_overflow | empty) & (next_state == EXECUTE)) begin
+            tail <= find_next_ptr(valid_bits);
+        end else if ((op_is_delete_by_value | op_is_delete_by_addr | op_is_delete_by_index) & (next_state == EXECUTE) & (length == 1)) begin
+            tail <= ADDR_NULL;
+        end else if ((op_is_delete_by_addr | op_is_delete_by_index) & (addr_in == tail_idx_sel) & (next_state == EXECUTE)) begin
+            tail <= pre_ptr; 
+        end else if (op_is_delete_by_value & (cur_ptr == tail) & (next_state == EXECUTE)) begin
+            tail <= pre_ptr;
+        end
+    end
+    
+    always @ (posedge clk or posedge rst) begin
+        if (rst) begin
+            length <= 0;
+        end else if ((op_is_insert_at_addr | op_is_insert_at_index) & (next_state == EXECUTE)) begin
+            length <= length + 1;
+        end else if ((op_is_delete_by_addr | op_is_delete_by_index)& (next_state == EXECUTE)) begin
+            length <= length - 1;
+        end else if (op_is_delete_by_value & (next_state == EXECUTE)) begin
+            length <= length - 1;
+        end
+    end
+    
+    function integer find_next_ptr(input integer valid_bits);
+        integer done;
+        done = 0;
+        find_next_ptr = 0;
+        for (i = 0; i < MAX_NODE ; i = i+1) begin
+            if(valid_bits[i] == 0 & done == 0) begin
+                find_next_ptr = i; 
+                done = 1;
+            end 
+        end
+    endfunction
+
+endmodule

Weiyet_RTLStructLib/source/Doubly_Linked_List/src/rtl_list.f

@@ -0,0 +1 @@
+doubly_linked_list.sv

Weiyet_RTLStructLib/source/Doubly_Linked_List/tb/cocotb/Makefile

@@ -0,0 +1,41 @@
+SIM ?= icarus
+TOPLEVEL_LANG ?= verilog
+WAVES ?= 1 #set 1 to enable waveform dump. 
+
+PWD=$(shell pwd)
+
+#export PYTHONPATH := $(PWD)/../model:$(PYTHONPATH)
+
+VERILOG_SOURCES = $(PWD)/../../src/doubly_linked_list.sv
+
+# DUT Top
+TOPLEVEL = doubly_linked_list
+# top python file name
+MODULE   = tb
+
+#use , separtor to run multiple TESTCASE, by default all @cocotb.test will be run
+#TESTCASE = index_op_test ， addr_op_test
+
+COMPILE_ARGS = -Ptable_top.DATA_WIDTH=8 # DUT parameter #"-p" (parameter) iverilog command flags
+COMPILE_ARGS += -Ptable_top.MAX_NODE=8 # DUT parameter #"-p" (parameter) iverilog command flags
+#run make clean before running with new parameter.
+
+#Set RANDOM_SEED number
+#PLUSARGS = +seed=1716033254
+COCOTB_HDL_TIMEUNIT = 1ns
+COCOTB_HDL_TIMEPRECISION = 1ps
+
+ifeq ($(SIM), icarus) 
+   $(shell echo 'module iverilog_dump();' > iverilog_dump.v)
+   $(shell echo 'initial begin' >> iverilog_dump.v)
+   $(shell echo '    $$dumpfile("$(TOPLEVEL).vcd");' >> iverilog_dump.v)
+   $(shell echo '    $$dumpvars(0, $(TOPLEVEL));' >> iverilog_dump.v)
+   $(shell echo 'end' >> iverilog_dump.v)
+   $(shell echo 'endmodule' >> iverilog_dump.v)
+   VERILOG_SOURCES += $(PWD)/iverilog_dump.v
+   COMPILE_ARGS += -s iverilog_dump  
+endif
+
+include $(shell cocotb-config --makefiles)/Makefile.sim
+
+

Weiyet_RTLStructLib/source/Doubly_Linked_List/tb/cocotb/tb.py

@@ -0,0 +1,480 @@
+import random
+#import asyncio
+import math
+import cocotb
+import cocotb.result
+from cocotb.triggers import Timer, RisingEdge, ReadOnly
+from cocotb.clock import Clock
+from cocotb_bus.drivers import BusDriver
+from cocotb_bus.monitors import BusMonitor
+from cocotb.binary import BinaryValue
+
+#BIN string
+#BinaryValue(dut.data_wr.value, n_bits=8) ; BinaryValue.integar ; BinaryValue.hex ; BinaryValue.binstr; BinaryValue.signed_integer ; can represent x,z
+
+DATA_WIDTH = 8 # DUT paramter
+MAX_NODE = 8 # DUT paramter
+
+ADDR_NULL = MAX_NODE + 1
+MAX_DATA  = 2**DATA_WIDTH - 1
+
+OP_Read = 0b000
+OP_Insert_At_Addr = 0b001
+OP_Insert_At_Index = 0b101
+OP_Delete_Value = 0b010
+OP_Delete_At_Addr = 0b011
+OP_Delete_At_Index = 0b111;
+
+TB_CLK_PERIOD = 30 # TB clk generator
+TB_SIM_TIMEOUT = 30 # TB sim timeout 30ms
+TB_TEST_WEIGHT = 1
+err_cnt = 0
+
+# doubly_linked_list #(.DATA_WIDTH(DUT_DATA_WIDTH),.MAX_NODE(DUT_MAX_NODE)) DUT
+# (   /*input*/  .rst(rst),
+#     /*input*/  .clk(clk),
+#     /*input [DATA_WIDTH-1:0]*/ .data_in(data_in), 
+#     /*input [ADDR_WIDTH-1:0]*/ .addr_in(addr_in),
+#     /*input [1:0]*/ .op(op), // 0: Read(addr_in); 1: Delete_Value(data_in); 2: Push_Back(data_in); 3: Push_front(data_in)
+#     /*input*/  .op_start(op_start), 
+#     /*output reg [DATA_WIDTH-1:0]*/ .data_out(data_out),
+#     /*output reg*/  .op_done(op_done),
+#     /*output wire [ADDR_WIDTH-1:0]*/ .pre_node_addr(pre_node_addr),// Addr of pre node
+#     /*output wire [ADDR_WIDTH-1:0]*/ .next_node_addr(next_node_addr), // Addr of next node
+#     // status 
+#     /*output reg [ADDR_WIDTH-1:0]*/  .length(length), 
+#     /*output wire*/ .full(full), 
+#     /*output reg [ADDR_WIDTH-1:0]*/ .head(head), // Addr of head
+#     /*output reg [ADDR_WIDTH-1:0]*/ .tail(tail), // Addr of head
+#     /*output wire*/ .empty(empty),
+#     /*output reg*/  .fault(fault) // Invalid Errors 
+# );
+
+# Actual Python linked_list class: https://www.datacamp.com/tutorial/python-linked-lists
+# To mimic harware linked_list, we need to keep track of the address of each node, model in below way also for our ease of debug. 
+class doubly_linked_list:
+    def __init__(self, dut):
+        self.dut = dut
+        self.linked_list_value = []
+        self.linked_list_addr = []
+
+    def remove(self, index):
+        self.linked_list_value.pop(index)
+        self.linked_list_addr.pop(index)
+
+    def find_next_addr(self):
+        for i in range(len(self.linked_list_addr)+2):
+            if i not in self.linked_list_addr:
+                return i
+
+    def insert_by_addr(self, addr, data):
+        if(addr == -1):
+            self.linked_list_value.append(data)
+            self.linked_list_addr.append(self.find_next_addr())
+        else:
+            self.linked_list_value.insert(self.linked_list_addr.index(addr), data)
+            self.linked_list_addr.insert(self.linked_list_addr.index(addr), self.find_next_addr())
+
+    def insert_by_index(self, index, data):
+        if(index == -1):
+            self.linked_list_value.append(data)
+            self.linked_list_addr.append(self.find_next_addr())
+        else:
+            self.linked_list_value.insert(index, data)
+            self.linked_list_addr.insert(index, self.find_next_addr())
+
+    def delete_by_value(self, data):
+        self.linked_list_addr.remove(self.linked_list_value.index(data))
+        self.linked_list_value.remove(data)
+        
+    def delete_by_addr(self, addr):
+        self.linked_list_value.pop(self.linked_list_addr.index(addr))
+        self.linked_list_addr.pop(self.linked_list_addr.index(addr))
+
+    def read_by_addr(self, addr):
+        return self.linked_list_value[self.linked_list_addr.index(addr)]
+
+    def print_content(self):
+        cocotb.log.info(f"Linked List Content: value = {self.linked_list_value}, addr = {self.linked_list_addr}")
+
+async def read_n_front(dut, list_exp, n):
+    global err_cnt
+    cocotb.log.info("OP_Read %0d values", n)
+    i = 0
+    await RisingEdge(dut.clk)
+    await Timer (1, units = 'ns')
+    dut.op.value = OP_Read
+    dut.op_start.value = 1
+    dut.addr_in.value = dut.head.value
+    i = i + 1
+    while (i <= n):
+        await RisingEdge(dut.clk)
+        await Timer (1, units = 'ns')
+        if (dut.op_done.value == 1):
+            if( (i-1) >= len(list_exp.linked_list_addr)):
+                if(dut.fault.value == 1):
+                    cocotb.log.info("Data read out of bound, fault flag is asserted correctly")
+                else:
+                    cocotb.log.error("Data read out of bound, fault flag is not asserted")
+                    err_cnt += 1
+            elif (list_exp.linked_list_value[i-1] == dut.data_out.value):
+                cocotb.log.info("Data read : %0d at Index %0d", dut.data_out.value, i-1)
+            else:
+                cocotb.log.error("Data read at Index %0d is Correct, ACT: %0d, EXP: %0d", i-1, dut.data_out.value, list_exp.linked_list_value[i-1])
+                err_cnt += 1
+            if(i==n):
+                dut.op_start.value = 0
+            dut.addr_in.value = dut.next_node_addr.value
+            i = i + 1
+    list_exp.print_content()
+
+async def read_n_back(dut, list_exp, n):
+    global err_cnt
+    cocotb.log.info("OP_Read %0d values", n)
+    i = 0
+    await RisingEdge(dut.clk)
+    await Timer (1, units = 'ns')
+    dut.op.value = OP_Read
+    dut.op_start.value = 1
+    dut.addr_in.value = dut.tail.value
+    i = i + 1
+    while (i <= n):
+        await RisingEdge(dut.clk)
+        await Timer (1, units = 'ns')
+        if (dut.op_done.value == 1):
+            if( (i-1) >= len(list_exp.linked_list_addr)):
+                if(dut.fault.value == 1):
+                    cocotb.log.info("Data read out of bound, fault flag is asserted correctly")
+                else:
+                    cocotb.log.error("Data read out of bound, fault flag is not asserted")
+                    err_cnt += 1
+            elif (list_exp.linked_list_value[-i] == dut.data_out.value):
+                cocotb.log.info("Data read : %0d at Index %0d", dut.data_out.value, len(list_exp.linked_list_addr)-1-(i-1))
+            else:
+                cocotb.log.error("Data read at Index %0d is Correct, ACT: %0d, EXP: %0d", i-1, dut.data_out.value, list_exp.linked_list_value[-i])
+                err_cnt += 1
+            if(i==n):
+                dut.op_start.value = 0
+            dut.addr_in.value = dut.pre_node_addr.value
+            i = i + 1
+    list_exp.print_content()
+
+async def delete_value(dut, list_exp, value):
+     global err_cnt
+     cocotb.log.info("OP_Delete_Value %0d value", value)
+     i = 0
+     found = 0
+     await RisingEdge(dut.clk)
+     await Timer (1, units = 'ns')
+     dut.op.value = OP_Delete_Value
+     dut.data_in.value = value
+     dut.op_start.value = 1
+     await RisingEdge(dut.op_done)
+     await Timer (1, units = 'ns')
+     for i in range(len(list_exp.linked_list_addr)):
+         if list_exp.linked_list_value[i] == value:
+             cocotb.log.info("Data %0d at Index %0d is Deleted_by_Value", value, i)
+             list_exp.remove(i)
+             found = 1
+             break
+     if found == 0:
+         if(dut.fault.value == 1):
+             cocotb.log.info("Data delete out of bound, fault flag is asserted correctly")
+         else:
+             cocotb.log.error("Data delete out of bound, fault flag is not asserted")
+             err_cnt += 1
+     else:
+         if(dut.fault.value == 1):
+             cocotb.log.error("Data delete in bound, fault flag is asserted incorrectly")
+             err_cnt += 1 
+     dut.op_start.value = 0 
+     list_exp.print_content()
+
+async def delete_at_index(dut, list_exp, index):
+    global err_cnt
+    cocotb.log.info("OP_Delete_At_Index %0d index", index)
+    await RisingEdge(dut.clk)
+    await Timer (1, units = 'ns')
+    dut.op.value = OP_Delete_At_Index
+    dut.addr_in.value = index
+    dut.op_start.value = 1
+    await RisingEdge(dut.op_done)
+    await Timer (1, units = 'ns')
+    if (index >= len(list_exp.linked_list_addr)):
+        if(dut.fault.value == 1):
+            cocotb.log.info("Data delete out of bound, fault flag is asserted correctly")
+        else:
+            cocotb.log.error("Data delete out of bound, fault flag is not asserted")
+            err_cnt += 1
+    elif (index == 0):
+        if(dut.fault.value == 1):
+            cocotb.log.error("Fault flag is asserted incorrectly")
+            err_cnt += 1
+        cocotb.log.info("Data %0d at Front is Deleted_by_Index", list_exp.linked_list_value[0])
+        list_exp.remove(0)
+    else:
+        if(dut.fault.value == 1):
+            cocotb.log.error("Fault flag is asserted incorrectly")
+            err_cnt += 1
+        cocotb.log.info("Data %0d at Index %0d is Deleted_by_Index", list_exp.linked_list_value[index], index)
+        list_exp.remove(index)
+    dut.op_start.value = 0
+    list_exp.print_content()
+
+async def insert_at_index(dut, list_exp, index, data):
+    global err_cnt
+    cocotb.log.info("OP_Insert_At_Index %0d index, %0d data", index, data)
+    await RisingEdge(dut.clk)
+    await Timer (1, units = 'ns')
+    dut.op.value = OP_Insert_At_Index
+    dut.addr_in.value = index
+    dut.data_in.value = data
+    dut.op_start.value = 1
+    await RisingEdge(dut.op_done)
+    await Timer (1, units = 'ns')
+    if (len(list_exp.linked_list_value) >= MAX_NODE):
+        if(dut.fault.value == 1):
+            cocotb.log.info("Data insert out of bound, fault flag is asserted correctly")
+        else:
+            cocotb.log.error("Data insert out of bound, fault flag is not asserted")
+            err_cnt += 1
+    elif (index == 0):
+        if(dut.fault.value == 1):
+            cocotb.log.error("Fault flag is asserted incorrectly")
+            err_cnt += 1
+        list_exp.insert_by_index(0, data)
+        cocotb.log.info("Data %0d at Front is Inserted_by_Index", data)
+    elif (index >= len(list_exp.linked_list_value)):
+        if(dut.fault.value == 1):
+            cocotb.log.error("Fault flag is asserted incorrectly")
+            err_cnt += 1
+        list_exp.insert_by_index(-1, data)
+        cocotb.log.info("Data %0d at End is Inserted_by_Index", data)
+    else:
+        if(dut.fault.value == 1):
+            cocotb.log.error("Fault flag is asserted incorrectly")
+            err_cnt += 1
+        list_exp.insert_by_index(index, data)
+        cocotb.log.info("Data %0d at Index %0d is Inserted_by_Index", data, index)
+    if(len(list_exp.linked_list_value) >= MAX_NODE):
+        if(dut.full.value == 1):
+            cocotb.log.info("Full flag is asserted correctly")
+        else:
+            cocotb.log.error("Full flag is not asserted")
+            err_cnt += 1
+    elif (dut.full.value == 1):
+        cocotb.log.error("Full flag is asserted incorrectly")
+        err_cnt += 1
+    dut.op_start.value = 0
+    list_exp.print_content()
+
+async def delete_at_addr (dut, list_exp, addr):
+    global err_cnt
+    cocotb.log.info("OP_Delete_At_Addr %0d addr", addr)
+    await RisingEdge(dut.clk)
+    await Timer (1, units = 'ns')
+    dut.op.value = OP_Delete_At_Addr
+    dut.addr_in.value = addr
+    dut.op_start.value = 1
+    pre_head = int(dut.head.value)
+    pre_tail = int(dut.tail.value)
+
+    await RisingEdge(dut.op_done)
+    await Timer (1, units = 'ns')
+    if (addr >= ADDR_NULL):
+        if(dut.fault.value == 1):
+            cocotb.log.info("Data delete out of bound, fault flag is asserted correctly")
+        else:
+            cocotb.log.error("Data delete out of bound, fault flag is not asserted")
+            err_cnt += 1
+    elif (addr == pre_head):
+        if(dut.fault.value == 1):
+            cocotb.log.error("Fault flag is asserted incorrectly")
+            err_cnt += 1
+        cocotb.log.info("Data %0d at Front is Deleted_by_Addr", list_exp.linked_list_value[0])
+        list_exp.remove(0)
+    elif (addr == pre_tail):
+        if(dut.fault.value == 1):
+            cocotb.log.error("Fault flag is asserted incorrectly")
+            err_cnt += 1
+        cocotb.log.info("Data %0d at Back is Deleted_by_Addr", list_exp.linked_list_value[0])
+        list_exp.remove(-1)
+    else:
+        if(addr not in list_exp.linked_list_addr):
+            if(dut.fault.value == 0):
+                cocotb.log.error("Fault flag is not asserted")
+                err_cnt += 1
+        else:
+            if(dut.fault.value == 1):
+                cocotb.log.error("Fault flag is asserted incorrectly")
+                err_cnt += 1
+            cocotb.log.info("Data %0d at Addr %0d is Inserted_by_Addr", list_exp.linked_list_value[list_exp.linked_list_addr.index(addr)], addr)
+            list_exp.delete_by_addr(addr)
+    if(len(list_exp.linked_list_value) == 0):
+        if(dut.empty.value == 1):
+            cocotb.log.info("Full flag is asserted correctly")
+        else:
+            cocotb.log.error("Full flag is not asserted")
+            err_cnt += 1
+    elif (dut.empty.value == 1):
+        cocotb.log.error("Full flag is asserted incorrectly")
+        err_cnt += 1
+    dut.op_start.value = 0
+    list_exp.print_content()
+
+async def insert_at_addr(dut, list_exp, addr, data):
+    global err_cnt
+    cocotb.log.info("OP_Insert_At_Addr %0d addr, %0d data", addr, data)
+    await RisingEdge(dut.clk)
+    await Timer (1, units = 'ns')
+    dut.op.value = OP_Insert_At_Addr
+    dut.addr_in.value = addr
+    dut.data_in.value = data
+    dut.op_start.value = 1
+    pre_head = int(dut.head.value)
+    pre_tail = int(dut.tail.value)
+
+    await RisingEdge(dut.op_done)
+    await Timer (1, units = 'ns')
+    if (len(list_exp.linked_list_value) >= MAX_NODE):
+        if(dut.fault.value == 1):
+            cocotb.log.info("Data insert out of bound, fault flag is asserted correctly")
+        else:
+            cocotb.log.error("Data insert out of bound, fault flag is not asserted")
+            err_cnt += 1
+    elif (addr >= ADDR_NULL):
+        if(dut.fault.value == 1):
+            cocotb.log.error("Fault flag is asserted incorrectly")
+            err_cnt += 1
+        list_exp.insert_by_addr(-1, data)
+        cocotb.log.info("Data %0d at End is Inserted_by_Addr", data)
+    elif (addr == pre_head):
+        if(dut.fault.value == 1):
+            cocotb.log.error("Fault flag is asserted incorrectly")
+            err_cnt += 1
+        list_exp.insert_by_addr(addr, data)
+        cocotb.log.info("Data %0d at Front is Inserted_by_Addr", data)
+    elif (addr == pre_tail):
+        if(dut.fault.value == 1):
+            cocotb.log.error("Fault flag is asserted incorrectly")
+            err_cnt += 1
+        list_exp.insert_by_index(len(list_exp.linked_list_value)-1, data)
+        cocotb.log.info("Data %0d at End is Inserted_by_Addr", data)
+    else:
+        if(addr not in list_exp.linked_list_addr):
+            if(dut.fault.value == 0):
+                cocotb.log.error("Fault flag is not asserted")
+                err_cnt += 1
+        else:
+            if(dut.fault.value == 1):
+                cocotb.log.error("Fault flag is asserted incorrectly")
+                err_cnt += 1
+            list_exp.insert_by_addr(addr, data)
+            cocotb.log.info("Data %0d at Addr %0d is Inserted_by_Addr", data, addr)
+    if(len(list_exp.linked_list_value) >= MAX_NODE):
+        if(dut.full.value == 1):
+            cocotb.log.info("Full flag is asserted correctly")
+        else:
+            cocotb.log.error("Full flag is not asserted")
+            err_cnt += 1
+    elif (dut.full.value == 1):
+        cocotb.log.error("Full flag is asserted incorrectly")
+        err_cnt += 1
+    dut.op_start.value = 0
+    list_exp.print_content()
+
+async def dut_init(dut):
+    global DATA_WIDTH # DUT paramter
+    global MAX_NODE # DUT paramter
+    global ADDR_NULL
+    global MAX_DATA 
+    DATA_WIDTH = dut.DATA_WIDTH.value
+    MAX_NODE = dut.MAX_NODE.value
+    ADDR_NULL = MAX_NODE
+    MAX_DATA  = 2**DATA_WIDTH - 1
+    await cocotb.start(Clock(dut.clk, TB_CLK_PERIOD, units="ns").start())
+    dut.data_in.value = 0
+    dut.addr_in.value = 0
+    dut.op.value = 0
+    dut.op_start.value = 0
+    dut.rst.value = 1
+    await(Timer(100,'ns'))
+    dut.rst.value = 0
+    await(Timer(100,'ns'))
+
+@cocotb.test()
+async def index_op_test(dut):
+    await dut_init(dut)
+    list_exp = doubly_linked_list(dut)
+    cocotb.log.info("SEED NUMBER = %d",cocotb.RANDOM_SEED)
+    await insert_at_index(dut,list_exp,0,3)
+    await insert_at_index(dut,list_exp,0,0)
+    await Timer(200, units = 'ns')
+    await insert_at_index(dut,list_exp,4,5)
+    await insert_at_index(dut,list_exp,0,6)
+    await insert_at_index(dut,list_exp,0,7)  
+    await insert_at_index(dut,list_exp,1,3)
+    await insert_at_index(dut,list_exp,2,4)
+    await insert_at_index(dut,list_exp,ADDR_NULL,3)
+    await insert_at_index(dut,list_exp,ADDR_NULL,4)
+    await insert_at_index(dut,list_exp,ADDR_NULL,1)
+    await insert_at_index(dut,list_exp,0,3)
+    await Timer(200, units = 'ns')
+    await read_n_front(dut,list_exp,len(list_exp.linked_list_value))
+    await read_n_back(dut,list_exp,len(list_exp.linked_list_value))
+    await Timer(200, units = 'ns')
+    await delete_value(dut,list_exp,7)
+    await delete_at_index(dut,list_exp,0)
+    await delete_at_index(dut,list_exp,0)
+    await delete_value(dut,list_exp,2)
+    await delete_value(dut,list_exp,4)
+    await delete_at_index(dut,list_exp,0)
+    await delete_at_index(dut,list_exp,7)
+    await delete_at_index(dut,list_exp,dut.length.value-1)
+    await delete_at_index(dut,list_exp,dut.length.value-1)
+    await delete_at_index(dut,list_exp,0)    
+    await delete_at_index(dut,list_exp,0)
+    await delete_at_index(dut,list_exp,0)    
+    await Timer(200, units = 'ns')
+
+    if (err_cnt > 0):
+        cocotb.log.error("Errors count = %d",err_cnt)
+        cocotb.result.TestFailure() #FIX ME
+
+@cocotb.test()
+async def addr_op_test(dut):
+    await dut_init(dut)
+    list_exp = doubly_linked_list(dut)
+    cocotb.log.info("SEED NUMBER = %d",cocotb.RANDOM_SEED)
+    await insert_at_addr(dut, list_exp, int(dut.head.value), 3)
+    await insert_at_addr(dut, list_exp, int(dut.head.value), 0)
+    await Timer(100, units='ns')
+    await insert_at_addr(dut, list_exp, int(dut.head.value), 5)
+    await insert_at_addr(dut, list_exp, int(dut.head.value), 6)
+    await insert_at_addr(dut, list_exp, list_exp.linked_list_addr[2], 7)
+    await insert_at_addr(dut, list_exp, 0, 3)
+    await insert_at_addr(dut, list_exp, int(dut.head.value), 4)
+    await insert_at_addr(dut, list_exp, int(dut.tail.value), 3)
+    await insert_at_addr(dut, list_exp, ADDR_NULL, 4)
+    await insert_at_addr(dut, list_exp, ADDR_NULL, 1)
+    await insert_at_addr(dut, list_exp, 0, 3)
+    await Timer(200, units='ns')
+    await read_n_front(dut, list_exp, len(list_exp.linked_list_value))
+    await read_n_back(dut, list_exp, len(list_exp.linked_list_value))
+    await Timer(500, units='ns')
+    await delete_value(dut, list_exp, 7)
+    await delete_at_addr(dut, list_exp, 0)
+    await delete_at_addr(dut, list_exp, 0)
+    await delete_value(dut, list_exp, 2)
+    await read_n_front(dut, list_exp, len(list_exp.linked_list_value))
+    await delete_value(dut, list_exp, 4)
+    await delete_at_addr(dut, list_exp, 0)
+    await delete_at_addr(dut, list_exp, 7)
+    await delete_at_addr(dut, list_exp, int(dut.head.value))
+    await delete_at_addr(dut, list_exp, int(dut.tail.value)-1)
+    await delete_at_addr(dut, list_exp, 0)
+    await Timer(500, units='ns')
+
+    if (err_cnt > 0):
+        cocotb.log.error("Errors count = %d",err_cnt)
+        cocotb.result.TestError() #FIX ME 

Weiyet_RTLStructLib/source/Doubly_Linked_List/tb/sv/Makefile

@@ -0,0 +1,38 @@
+
+DUT ?= doubly_linked_list
+SIM_OPTS ?= ../../src/doubly_linked_list.sv
+SEED ?= $$(shuf -i 1-10000 -n 1)
+
+# DUT parameter #"-p" iverilog command flags
+# COMPILE_ARGS = -P tb.DUT_DATA_WIDTH=8
+# COMPILE_ARGS += -P tb.DUT_MAX_NODE=8
+# COMPILE_ARGS += -P tb.TB_CLK_PERIOD=25
+# COMPILE_ARGS += -P tb.TB_TEST_WEIGHT=1
+# COMPILE_ARGS += -P tb.TB_CLK_PERIOD=100
+# COMPILE_ARGS += -P tb.SIM_TIMEOUT=500000 
+
+XILINX_LIB_URL ?= https://github.com/Xilinx/XilinxUnisimLibrary.git
+XILINX_LIB_DIR ?= XilinxUnisimLibrary/verilog/src
+
+sim: gen_sim 
+	./${DUT}.sim +VCDFILE=sim.vcd +VCDLEVEL=0 +SEED=${SEED} | tee sim.log
+
+gen_sim: tb.sv ${SIM_OPTS}  # to generate executable file by using iverilator  
+	iverilog -g2012 -s tb ${COMPILE_ARGS} -o ${DUT}.sim $^
+
+synth: ${SIM_OPTS}
+	yosys -p synth_xilinx ${SIM_OPTS} -L synth.log -o ${DUT}.netlist.v
+    #timeout
+
+netlist_sim: gen_netlist_sim
+	./${DUT}.netlist.sim +VCDFILE=netlist_sim.vcd +VCDLEVEL=0 +SEED=${SEED} | tee netlist_sim.log
+
+gen_netlist_sim: tb.sv ${DUT}.netlist.v | ${XILINX_LIBS_DIR}/.got
+	iverilog -g2012 -s tb -y ${XILINX_LIB_DIR} -y ${XILINX_LIB_DIR}/unisims -DXILINX_GLS ${COMPILE_ARGS} -o ${DUT}.netlist.sim $^
+
+${XILINX_LIBS_DIR}/.git:
+	git clone ${XILINX_LIB_URL}
+
+clean:
+	rm -f ${DUT}_sim sim.log sim.vcd
+	rm -f ${DUT}.netlist.v synth.log

Weiyet_RTLStructLib/source/Doubly_Linked_List/tb/sv/tb.sv

@@ -0,0 +1,744 @@
+`timescale 1ns / 1ps
+//////////////////////////////////////////////////////////////////////////////////
+// Create Date: 09/22/2024 01:42:52 PM
+// Module Name: tb
+// Description: Supported Operation 
+//             0. Read_Addr(addr_in) -> data_out 
+//             1. Insert_At_Addr(addr_in, data_in) 
+//             5. Insert_At_Index(addr_in, data_in)
+//             2. Delete_Value(data_in)
+//             3. Delete_At_Addr(addr_in)
+//             7. Delete_At_Index(addr_in) 
+// Additional Comments:
+// 
+//////////////////////////////////////////////////////////////////////////////////
+
+
+module tb(
+    );
+    // DUT parameter
+    localparam DUT_DATA_WIDTH = 8;
+    localparam DUT_MAX_NODE = 8;
+    // TB parameter
+    localparam TB_CLK_PERIOD = 25;
+    localparam ADDR_WIDTH = $clog2(DUT_MAX_NODE+1); // Reserve {ADDR_WIDTH(1'b1)} as NULL/INVALID ADDR  
+    localparam MAX_DATA = 2**DUT_DATA_WIDTH - 1;
+    localparam TB_TEST_WEIGHT = 1;
+    localparam SIM_TIMEOUT = 500000;
+
+localparam ADDR_NULL = (DUT_MAX_NODE);
+
+localparam OP_Read = 3'b000;
+localparam OP_Insert_At_Addr = 3'b001;
+localparam OP_Insert_At_Index = 3'b101;
+localparam OP_Delete_Value = 3'b010;
+localparam OP_Delete_At_Addr = 3'b011;
+localparam OP_Delete_At_Index = 3'b111;
+
+integer err_cnt = 0;
+
+// input 
+reg clk = 0;
+reg rst = 0;
+reg [DUT_DATA_WIDTH-1:0] data_in = 0; 
+reg [ADDR_WIDTH-1:0] addr_in = 0; 
+reg [2:0] op = 0;
+reg op_start = 0;
+// output
+wire [DUT_DATA_WIDTH-1:0] data_out;
+wire op_done;
+wire [ADDR_WIDTH-1:0] pre_node_addr;
+wire [ADDR_WIDTH-1:0] next_node_addr; 
+wire [ADDR_WIDTH-1:0] length;
+wire [ADDR_WIDTH-1:0] head; // Addr of head
+reg  [ADDR_WIDTH-1:0] pre_head;
+wire [ADDR_WIDTH-1:0] tail; // Addr of tail
+reg  [ADDR_WIDTH-1:0] pre_tail; // Addr of tail
+wire full;
+wire empty;
+wire fault; 
+
+`ifdef XILINX_GLS
+    // for xilinx gate sim
+    glbl glbl();
+`endif
+ 
+    doubly_linked_list #(.DATA_WIDTH(DUT_DATA_WIDTH),.MAX_NODE(DUT_MAX_NODE)) DUT
+    (   /*input*/  .rst(rst),
+        /*input*/  .clk(clk),
+        /*input [DATA_WIDTH-1:0]*/ .data_in(data_in), 
+        /*input [ADDR_WIDTH-1:0]*/ .addr_in(addr_in),
+        /*input [1:0]*/ .op(op), // 0: Read(addr_in); 1: Delete_Value(data_in); 2: Push_Back(data_in); 3: Push_front(data_in)
+        /*input*/  .op_start(op_start), 
+        /*output reg [DATA_WIDTH-1:0]*/ .data_out(data_out),
+        /*output reg*/  .op_done(op_done),
+        /*output wire [ADDR_WIDTH-1:0]*/ .pre_node_addr(pre_node_addr),// Addr of pre node
+        /*output wire [ADDR_WIDTH-1:0]*/ .next_node_addr(next_node_addr), // Addr of next node
+        // status 
+        /*output reg [ADDR_WIDTH-1:0]*/  .length(length), 
+        /*output wire*/ .full(full), 
+        /*output reg [ADDR_WIDTH-1:0]*/ .head(head), // Addr of head
+        /*output reg [ADDR_WIDTH-1:0]*/ .tail(tail), // Addr of head
+        /*output wire*/ .empty(empty),
+        /*output reg*/  .fault(fault) // Invalid Errors 
+    );
+    
+always #(TB_CLK_PERIOD/2) clk = ~clk; 
+
+integer linked_list_exp[$];    
+integer linked_list_addr[$]; // corresponding to linked_list_exp. 
+integer data_wr[$];
+integer i = 0;
+integer next;
+int dummy[$];
+int temp[$];
+integer temp2;
+
+
+task list_print_contents();
+   $write("%0t linked_list_exp = ", $realtime);
+   for (int i = 0; i < linked_list_exp.size(); i = i + 1) begin
+      $write("%0d ", linked_list_exp[i]);
+   end
+   $write("\n%0t linked_list_addr = ", $realtime);
+   for (int i = 0; i < linked_list_addr.size(); i = i + 1) begin
+      $write("%0d ", linked_list_addr[i]);
+   end
+   $write("\n");
+endtask 
+
+task find_first_index (input integer addr); // input integer list[$], ref integer addr[$]); icarus does not support ref.
+begin
+   temp = {};
+   for (integer i = 0; i < linked_list_addr.size(); i = i + 1) begin
+      if(addr == linked_list_addr[i]) begin
+         temp.push_back(i);
+         $display("%0t Addr %0d found at Index %0d", $realtime, addr, i);
+      end
+   end
+end
+endtask
+
+task find_first_index2 (input integer addr); //avoid temp output conflict
+begin
+   dummy = {};
+   for (integer i = 0; i < linked_list_addr.size(); i = i + 1) begin
+      if(addr == linked_list_addr[i]) begin
+         dummy.push_back(i);
+         $display("%0t Addr %0d found at Index %0d", $realtime, addr, i);
+      end
+   end
+end
+endtask
+
+task find_next_addr (output integer next_addr);
+begin
+   next_addr = 0;
+   for (int i = 0; i < (linked_list_addr.size()+1); i = i + 1) begin
+      dummy = {};
+      //dummy = (linked_list_addr.find_first_index(x) with ( x == i )); // icarus does not support built in find_first_index method, so used workaround below. 
+      find_first_index2(i);
+      if(dummy.size() == 0) begin
+        next_addr = i;
+        //break;  //icarus does not support break statement, so used workaround below. 
+        i = linked_list_addr.size()+1; 
+      end
+   end
+   $display("%0t Next Addr = %0d", $realtime, next_addr);
+end
+endtask
+
+task read_n_front(input integer count); 
+begin
+    $display("%0t OP_Read from front %0d times", $realtime,count); 
+    i = 0;
+    @(posedge (clk));
+    #1 
+    op = OP_Read;  
+    op_start = 1;
+    addr_in = head;
+    i = i + 1;
+    while (i<=count) begin  
+        @(posedge (clk));
+        #1 
+        if(op_done) begin
+            if( (i-1) >= linked_list_exp.size()) begin
+               if(fault) begin
+                  $display("%0t Data read out of bound, fault flag is asserted correctly",$realtime);
+               end else begin
+                  $error("%0t Data read out of bound, fault flag is not asserted",$realtime);
+                  err_cnt = err_cnt + 1;
+               end
+            end else if(data_out == linked_list_exp[i-1]) begin
+               $display("%0t Data read: %0d",$realtime,data_out);
+            end else begin
+               $error("%0t Data read: %0d, Data Exp: %0d", $realtime, data_out, linked_list_exp[i-1]);
+               err_cnt = err_cnt + 1; 
+            end
+            if(i == count) begin
+               op_start = 0;
+            end else if ( ((i-1) == 0) && ((i-1) < linked_list_exp.size()-2) ) begin
+               if(next_node_addr != linked_list_addr[i]) begin
+                  $error("%0t Next Addr: %0d, Addr Exp: %0d", $realtime, next_node_addr, linked_list_addr[i]);
+                  err_cnt = err_cnt + 1; 
+               end
+               if(pre_node_addr != ADDR_NULL) begin
+                  $error("%0t Pre Addr: %0d, Addr Exp: %0d", $realtime, pre_node_addr, ADDR_NULL);
+                  err_cnt = err_cnt + 1; 
+               end
+            end else if ( ((i-1) > 0) && ((i-1) < linked_list_exp.size()-2) ) begin
+               if(next_node_addr != linked_list_addr[i]) begin
+                  $error("%0t Next Addr: %0d, Addr Exp: %0d", $realtime, next_node_addr, linked_list_addr[i]);
+                  err_cnt = err_cnt + 1; 
+               end
+               if(pre_node_addr != linked_list_addr[i-2]) begin
+                  $error("%0t Pre Addr: %0d, Addr Exp: %0d", $realtime, pre_node_addr, linked_list_addr[i-2]);
+                  err_cnt = err_cnt + 1; 
+               end
+            end else if ( (i-1) == linked_list_exp.size()-1) begin
+               if(next_node_addr != ADDR_NULL) begin
+                  $error("%0t Next Addr: %0d, Addr Exp: %0d", $realtime, next_node_addr, ADDR_NULL);
+                  err_cnt = err_cnt + 1; 
+               end
+               if(pre_node_addr != linked_list_addr[i-2]) begin
+                  $error("%0t Pre Addr: %0d, Addr Exp: %0d", $realtime, pre_node_addr, linked_list_addr[i-2]);
+                  err_cnt = err_cnt + 1; 
+               end
+            end
+            addr_in = next_node_addr;
+            i = i + 1;
+        end
+    end
+    // icarus does not support %p concanation, so used workaround below.
+    list_print_contents();
+    //$display("%0t Complete OP_Read from front %0d times, linked_list_exp = %p", $realtime,count,linked_list_exp[0:(linked_list_exp.size()-1)]); 
+    //$display("%0t Complete OP_Read from front %0d times, linked_list_addr = %p\n", $realtime,count,linked_list_addr[0:(linked_list_addr.size()-1)]); 
+end
+endtask  
+
+task read_n_back(input integer count); 
+begin
+    $display("%0t OP_Read from back %0d times", $realtime,count); 
+    i = 0;
+    @(posedge (clk));
+    #1 
+    op = OP_Read;  
+    op_start = 1;
+    addr_in = tail;
+    i = i + 1;
+    while (i<=count) begin  
+        @(posedge (clk));
+        #1 
+        if(op_done) begin
+            if( (i-1) >= linked_list_exp.size()) begin
+               if(fault) begin
+                  $display("%0t Data read out of bound, fault flag is asserted correctly",$realtime);
+               end else begin
+                  $error("%0t Data read out of bound, fault flag is not asserted",$realtime);
+                  err_cnt = err_cnt + 1;
+               end
+            end else if(data_out == linked_list_exp[linked_list_exp.size()-1-(i-1)]) begin
+               $display("%0t Data read: %0d",$realtime,data_out);
+            end else begin
+               $error("%0t Data read: %0d, Data Exp: %0d", $realtime, data_out, linked_list_exp[linked_list_exp.size()-1-(i-1)]);
+               err_cnt = err_cnt + 1; 
+            end
+            if(i == count) begin
+               op_start = 0;
+            end else if ( ((i-1) == 0) && ((i-1) < linked_list_exp.size()-2) ) begin
+               if(next_node_addr != ADDR_NULL) begin
+                  $error("%0t Next Addr: %0d, Addr Exp: %0d", $realtime, next_node_addr, ADDR_NULL);
+                  err_cnt = err_cnt + 1; 
+               end
+               if(pre_node_addr != linked_list_addr[linked_list_exp.size()-1-(i-2)]) begin
+                  $error("%0t Pre Addr: %0d, Addr Exp: %0d", $realtime, pre_node_addr, linked_list_addr[linked_list_exp.size()-1-(i-2)]);
+                  err_cnt = err_cnt + 1; 
+            end else if ( ((i-1) > 0) && ((i-1) < linked_list_exp.size()-2) ) begin
+               if(next_node_addr != linked_list_addr[linked_list_exp.size()-1-(i)]) begin
+                  $error("%0t Next Addr: %0d, Addr Exp: %0d", $realtime, next_node_addr, linked_list_addr[linked_list_exp.size()-1-(i)]);
+                  err_cnt = err_cnt + 1; 
+               end
+               if(pre_node_addr != linked_list_addr[linked_list_exp.size()-1-(i-2)]) begin
+                  $error("%0t Pre Addr: %0d, Addr Exp: %0d", $realtime, pre_node_addr, linked_list_addr[linked_list_exp.size()-1-(i-2)]);
+                  err_cnt = err_cnt + 1; 
+               end
+            end else if ( (i-1) == linked_list_exp.size()-1) begin
+               if(next_node_addr != linked_list_addr[linked_list_exp.size()-1-(i)]) begin
+                  $error("%0t Next Addr: %0d, Addr Exp: %0d", $realtime, next_node_addr, linked_list_addr[linked_list_exp.size()-1-(i)]);
+                  err_cnt = err_cnt + 1; 
+               end
+               if(pre_node_addr != ADDR_NULL) begin
+                  $error("%0t Pre Addr: %0d, Addr Exp: %0d", $realtime, pre_node_addr, ADDR_NULL);
+                  err_cnt = err_cnt + 1; 
+               end
+            end
+            end
+            addr_in = pre_node_addr;
+            i = i + 1;
+        end
+    end
+   // icarus does not support %p concanation, so used workaround below.
+   list_print_contents();
+   // $display("%0t Complete OP_Read from back %0d times, linked_list_exp = %p", $realtime,count,linked_list_exp[0:(linked_list_exp.size()-1)]); 
+   // $display("%0t Complete OP_Read from back %0d times, linked_list_addr = %p\n", $realtime,count,linked_list_addr[0:(linked_list_addr.size()-1)]); 
+end
+endtask  
+
+bit found = 0;
+
+task delete_value(input integer value); 
+begin
+    $display("%0t OP_Delete_Value %0d value", $realtime,value);    
+    i = 0; 
+    found = 0;
+    @(posedge (clk));
+    #1 
+    op = OP_Delete_Value;  
+    data_in = value;
+    op_start = 1;
+    wait (op_done)
+    #1 
+    for (int j = 0; j < linked_list_exp.size(); j=j+1) begin
+        if(value == linked_list_exp[j]) begin
+           $display("%0t Data %0d at Index %0d is Deleted_by_Value", $realtime, linked_list_exp[j],j);
+           linked_list_exp.delete(j);  
+           linked_list_addr.delete(j); 
+           found = 1;      
+           //break;
+           j = linked_list_exp.size() + 1; 
+        end
+    end
+    if (!found) begin
+       if(fault) begin
+          $display("%0t Data delete out of bound, fault flag is asserted correctly",$realtime);
+       end else begin
+          $error("%0t Data delete out of bound, fault flag is not asserted",$realtime);
+          err_cnt = err_cnt + 1;
+       end
+    end else begin
+       if(fault) begin
+          $error("%0t fault flag is asserted incorrectly",$realtime);
+          err_cnt = err_cnt + 1;
+       end
+    end
+    op_start = 0;
+    // icarus does not support %p concanation, so used workaround below.
+    list_print_contents();
+    //$display("%0t Complete OP_Delete_Value %0d value, linked_list_exp = %p", $realtime,value,linked_list_exp[0:(linked_list_exp.size()-1)]); 
+    //$display("%0t Complete OP_Delete_Value %0d value, linked_list_addr = %p\n", $realtime,value,linked_list_addr[0:(linked_list_addr.size()-1)]); 
+end
+endtask  
+    
+task delete_at_index (input integer addr); 
+begin
+    $display("%0t OP_Delete_At_Index %0d index", $realtime,addr);
+    i = 0; 
+    @(posedge (clk));
+    #1 
+    op = OP_Delete_At_Index;  
+    addr_in = addr; 
+    op_start = 1;
+
+    wait (op_done)
+    #1 
+    if( addr >= linked_list_exp.size()) begin
+       if(fault) begin
+          $display("%0t Data delete out of bound, fault flag is asserted correctly",$realtime);
+       end else begin
+          $error("%0t Data delete out of bound, fault flag is not asserted",$realtime);
+          err_cnt = err_cnt + 1;
+       end
+    end else if ( addr == 0 ) begin
+       if(fault) begin
+          $error("%0t fault flag is asserted incorrectly",$realtime);
+          err_cnt = err_cnt + 1;
+       end
+       $display("%0t Data %0d at Front is Deleted", $realtime, linked_list_exp[0]);
+       temp2 = linked_list_exp.pop_front();
+       temp2 = linked_list_addr.pop_front();
+    end else begin
+       if(fault) begin
+          $error("%0t fault flag is asserted incorrectly",$realtime);
+          err_cnt = err_cnt + 1;
+       end
+       $display("%0t Data %0d at Index %0d is Deleted", $realtime, linked_list_exp[addr],addr);
+       linked_list_exp.delete(addr);
+       linked_list_addr.delete(addr);
+    end
+    if(linked_list_exp.size() == 0) begin
+       if(empty) begin
+          $display("%0t Queue is empty and empty flag is asserted correctly",$realtime);
+       end else begin
+          $error("%0t Queue is empty but empty flag is not asserted",$realtime);
+          err_cnt = err_cnt + 1;
+       end
+    end else if(empty) begin
+       $error("%0t Empty flag is asserted incorrectly",$realtime);
+       err_cnt = err_cnt + 1;
+    end
+    op_start = 0;
+    // icarus does not support %p concanation, so used workaround below.
+    list_print_contents();
+    //$display("%0t Complete OP_Delete_At_Index %0d index, linked_list_exp = %p", $realtime,addr,linked_list_exp[0:(linked_list_exp.size()-1)]); 
+    //$display("%0t Complete OP_Delete_At_Index %0d index, linked_list_addr = %p\n", $realtime,addr,linked_list_addr[0:(linked_list_addr.size()-1)]); 
+end
+endtask  
+
+task insert_at_index (input integer addr, input integer value); 
+begin 
+    $display("%0t OP_Insert_At_Index %0d index, %0d value", $realtime,addr,value);
+    i = 0; 
+    @(posedge (clk));
+    #1 
+    op = OP_Insert_At_Index;  
+    addr_in = addr;
+    data_in = value;
+    op_start = 1; 
+    wait (op_done)
+    #1 
+    if(linked_list_exp.size() >= DUT_MAX_NODE) begin
+       if(!fault) begin
+          $error("%0t Fault flag is not asserted",$realtime);
+          err_cnt = err_cnt + 1;
+       end else begin
+          $display("%0t Fault flag is asserted correctly",$realtime);
+       end
+    end else if( addr == 0 ) begin
+       if(fault) begin
+          $error("%0t Fault flag is asserted incorrectly",$realtime);
+          err_cnt = err_cnt + 1;
+       end 
+       linked_list_exp.push_front(value);
+       find_next_addr(next);
+       linked_list_addr.push_front(next);
+       $display("%0t Data Written to Front : %0d",$realtime,value);
+    end else if ( addr >= linked_list_exp.size() ) begin
+       if(fault) begin
+          $error("%0t Fault flag is asserted incorrectly",$realtime);
+          err_cnt = err_cnt + 1;
+       end 
+       linked_list_exp.push_back(value);
+       find_next_addr(next);
+       linked_list_addr.push_back(next);
+       $display("%0t Data Written to Back : %0d",$realtime,value);
+    end else begin
+       if(fault) begin
+          $error("%0t Fault flag is asserted incorrectly",$realtime);
+          err_cnt = err_cnt + 1;
+       end 
+       linked_list_exp.insert(addr, value);
+       find_next_addr(next);
+       linked_list_addr.insert(addr, next);
+       $display("%0t Data Written to Index %0d : %0d",$realtime,addr,value);
+    end
+    if(linked_list_exp.size() >=  (DUT_MAX_NODE)) begin
+       if(full) begin
+          $display("%0t Queue is full and full flag is asserted correctly",$realtime);
+       end else begin
+          $error("%0t Queue is full but full flag is not asserted",$realtime);
+          err_cnt = err_cnt + 1;
+       end
+    end else if(full) begin
+       $error("%0t Full flag is asserted incorrectly",$realtime);
+       err_cnt = err_cnt + 1; 
+    end
+    op_start = 0;
+    // icarus does not support %p concanation, so used workaround below.
+    list_print_contents();
+    //$display("%0t Complete OP_Insert_At_Index %0d index %0d value, linked_list_exp = %p", $realtime,addr,value,linked_list_exp[0:(linked_list_exp.size()-1)]); 
+    //$display("%0t Complete OP_Insert_At_Index %0d index %0d value, linked_list_addr = %p\n", $realtime,addr,value,linked_list_addr[0:(linked_list_addr.size()-1)]); 
+end
+endtask
+
+task delete_at_addr (input int addr); 
+begin
+    $display("%0t OP_Delete_At_Addr %0d Addr", $realtime,addr);
+    i = 0; 
+    @(posedge (clk));
+    #1 
+    op = OP_Delete_At_Addr;  
+    addr_in = addr; 
+    op_start = 1;
+    pre_head = head;
+    pre_tail = tail;
+
+    wait (op_done)
+    #1 
+    if( addr >= ADDR_NULL) begin
+       if(fault) begin
+          $display("%0t Data delete out of bound, fault flag is asserted correctly",$realtime);
+       end else begin
+          $error("%0t Data delete out of bound, fault flag is not asserted",$realtime);
+          err_cnt = err_cnt + 1;
+       end
+    end else if ( addr == pre_head ) begin
+       if(fault) begin
+          $error("%0t fault flag is asserted incorrectly",$realtime);
+          err_cnt = err_cnt + 1;
+       end
+       $display("%0t Data %0d at Front is Deleted", $realtime, linked_list_exp[0]);
+       temp2 = linked_list_exp.pop_front();
+       temp2 = linked_list_addr.pop_front();
+    end else if ( addr == pre_tail ) begin
+       if(fault) begin
+          $error("%0t fault flag is asserted incorrectly",$realtime);
+          err_cnt = err_cnt + 1;
+       end
+       $display("%0t Data %0d at Back is Deleted", $realtime, linked_list_exp[0]);
+       temp2 = linked_list_exp.pop_back();
+       temp2 = linked_list_addr.pop_back();
+    end else begin
+       temp = {};
+      //  for (int j  = 0; j <1; j = j+1) begin
+      //    temp = (linked_list_addr.find_first_index(x) with (x == addr));
+      //  end
+       find_first_index(addr);
+       if (temp.size() == 0) begin
+           if(!fault) begin
+              $error("%0t Fault flag is not asserted",$realtime);
+              err_cnt = err_cnt + 1;
+           end else begin
+              $display("%0t Fault flag is asserted correctly",$realtime);
+           end       
+       end else begin
+          $display("%0t Data %0d at Addr %0d is Deleted", $realtime, linked_list_exp[temp[0]],linked_list_addr[temp[0]]);
+          linked_list_exp.delete(temp[0]);
+          linked_list_addr.delete(temp[0]);
+       end
+    end
+    if(linked_list_exp.size() == 0) begin
+       if(empty) begin
+          $display("%0t Queue is empty and empty flag is asserted correctly",$realtime);
+       end else begin
+          $error("%0t Queue is empty but empty flag is not asserted",$realtime);
+          err_cnt = err_cnt + 1;
+       end
+    end else if(empty) begin
+       $error("%0t Empty flag is asserted incorrectly",$realtime);
+       err_cnt = err_cnt + 1;
+    end
+    op_start = 0;
+    // icarus does not support %p concanation, so used workaround below.
+    list_print_contents();
+    //$display("%0t Complete OP_Delete_At_Addr %0d addr, linked_list_exp = %p", $realtime,addr,linked_list_exp[0:(linked_list_exp.size()-1)]); 
+    //$display("%0t Complete OP_Delete_At_Addr %0d addr, linked_list_addr = %p\n", $realtime,addr,linked_list_addr[0:(linked_list_addr.size()-1)]); 
+end
+endtask  
+
+task insert_at_addr (input int addr, input integer value); 
+begin 
+    $display("%0t OP_Insert_At_Addr %0d addr, %0d value", $realtime,addr,value);
+    i = 0; 
+    @(posedge (clk));
+    #1 
+    op = OP_Insert_At_Addr;  
+    addr_in = addr;
+    data_in = value;
+    op_start = 1; 
+    pre_head = head;
+    pre_tail = tail;
+    wait (op_done)
+    #1 
+    if(linked_list_exp.size() >= DUT_MAX_NODE) begin
+       if(!fault) begin
+          $error("%0t Fault flag is not asserted",$realtime);
+          err_cnt = err_cnt + 1;
+       end else begin
+          $display("%0t Fault flag is asserted correctly",$realtime);
+       end
+    end else if( addr == pre_head ) begin
+       if(fault) begin
+          $error("%0t Fault flag is asserted incorrectly",$realtime);
+          err_cnt = err_cnt + 1;
+       end 
+       linked_list_exp.push_front(value);
+       find_next_addr(next);
+       linked_list_addr.push_front(next);
+       $display("%0t Data Written to Front : %0d",$realtime,value);
+    end else if( addr == pre_tail ) begin
+       if(fault) begin
+          $error("%0t Fault flag is asserted incorrectly",$realtime);
+          err_cnt = err_cnt + 1;
+       end 
+       linked_list_exp.insert(linked_list_exp.size()-1, value);
+       find_next_addr(next);
+       linked_list_addr.insert(linked_list_addr.size()-1, next);
+       $display("%0t Data Written to Back : %0d",$realtime,value);
+    end else if ( addr >= ADDR_NULL ) begin
+       if(fault) begin
+          $error("%0t Fault flag is asserted incorrectly",$realtime);
+          err_cnt = err_cnt + 1;
+       end 
+       linked_list_exp.push_back(value);
+       find_next_addr(next);
+       linked_list_addr.push_back(next);
+       $display("%0t Data Written to Back : %0d",$realtime,value);
+    end else begin
+       temp = {};
+      //  for (int j  = 0; j <1; j = j+1) begin
+      //    temp = (linked_list_addr.find_first_index(x) with (x == addr));
+      //  end
+       find_first_index(addr);
+       if (temp.size() == 0) begin
+           if(!fault) begin
+              $error("%0t Fault flag is not asserted",$realtime);
+              err_cnt = err_cnt + 1;
+           end else begin
+              $display("%0t Fault flag is asserted correctly",$realtime);
+           end       
+       end else begin
+          linked_list_exp.insert(temp[0], value);
+          find_next_addr(next);
+          linked_list_addr.insert(temp[0], next);
+          $display("%0t Data Written to Addr %0d : %0d",$realtime,addr,value);
+       end      
+    end
+    if(linked_list_exp.size() >=  (DUT_MAX_NODE)) begin
+       if(full) begin
+          $display("%0t Queue is full and full flag is asserted correctly",$realtime);
+       end else begin
+          $error("%0t Queue is full but full flag is not asserted",$realtime);
+          err_cnt = err_cnt + 1;
+       end
+    end else if(full) begin
+       $error("%0t Full flag is asserted incorrectly",$realtime);
+       err_cnt = err_cnt + 1; 
+    end
+    op_start = 0;
+    // icarus does not support %p concanation, so used workaround below.
+    list_print_contents();
+    //$display("%0t Complete OP_Insert_At_Addr %0d addr %0d value, linked_list_exp = %p", $realtime,addr,value,linked_list_exp[0:(linked_list_exp.size()-1)]);
+    //$display("%0t Complete OP_Insert_At_Addr %0d addr %0d value, linked_list_addr = %p\n", $realtime,addr,value,linked_list_addr[0:(linked_list_addr.size()-1)]); 
+end
+endtask
+
+task direct_index_op_test();
+begin
+    $display("\n======================================");
+    $display("Direct Index Op Test");
+    $display("======================================");
+    //DIRECT TEST Index Mode
+    rst = 1'b1;
+    #100
+    rst = 1'b0;
+    linked_list_exp = {};
+    linked_list_addr = {};
+    insert_at_index(0,3);
+    insert_at_index(0,0);
+    #100
+    insert_at_index(4,5); 
+    insert_at_index(0,6);
+    insert_at_index(0,7);  
+    insert_at_index(1,3); 
+    insert_at_index(2,4);
+    insert_at_index(ADDR_NULL,3);
+    insert_at_index(ADDR_NULL,4);
+    read_n_back(linked_list_exp.size());
+    insert_at_index(ADDR_NULL,1);
+    insert_at_index(0,3);
+    #200
+    read_n_front(linked_list_exp.size());
+    #500
+    delete_value(7);
+    delete_at_index(0);
+    read_n_back(linked_list_exp.size());
+    delete_at_index(0);
+    delete_value(2);  
+    delete_value(4);
+    delete_at_index(0);
+    read_n_front(linked_list_exp.size());
+    delete_at_index(7);
+    delete_at_index(length-1);
+    delete_at_index(length-1);
+    delete_at_index(0);     
+    delete_at_index(0); 
+    delete_at_index(0);    
+    #500;
+end
+endtask
+
+task direct_addr_op_test();
+begin
+    //DIRECT TEST Index Mode
+    $display("\n======================================");
+    $display("Direct Address Op Test");
+    $display("======================================");
+    rst = 1'b1;
+    #100
+    rst = 1'b0;
+    linked_list_exp = {};
+    linked_list_addr = {};
+    insert_at_addr(head,3);
+    insert_at_addr(head,0);
+    #100
+    insert_at_addr(0,5); 
+    insert_at_addr(head,6);
+    insert_at_addr(linked_list_addr[2],7);  
+    insert_at_addr(tail,3); 
+    insert_at_addr(head,4);
+    read_n_back(linked_list_exp.size());
+    insert_at_addr(ADDR_NULL,3);
+    insert_at_addr(ADDR_NULL,4);
+    insert_at_addr(ADDR_NULL,1);
+    insert_at_addr(0,3);
+    #200
+    read_n_front(linked_list_exp.size());
+    #500
+    delete_value(7); 
+    read_n_front(linked_list_exp.size());
+    delete_at_addr(0);
+    delete_at_addr(head);
+    delete_value(2);  
+    read_n_front(linked_list_exp.size());
+    read_n_back(linked_list_exp.size());
+    delete_value(4);
+    read_n_front(linked_list_exp.size());
+    delete_at_addr(head);
+    delete_at_addr(7);
+    delete_at_addr(tail);
+    delete_at_addr(tail-1); 
+    delete_at_addr(0);        
+    #500;
+end
+endtask
+
+initial begin
+    string vcdfile;
+    int vcdlevel;
+    int seed;
+    int temp;
+
+    rst = 1'b1;
+    if ($value$plusargs("VCDFILE=%s",vcdfile))
+        $dumpfile(vcdfile);
+    if ($value$plusargs("VCDLEVEL=%d",vcdlevel))
+        $dumpvars(vcdlevel,tb);
+    if ($value$plusargs("SEED=%d",seed)) begin
+        temp = $urandom(seed);
+        $display("Seed = %d",seed);
+    end
+    
+    direct_index_op_test();
+    
+    #1000;
+    
+    direct_addr_op_test();
+    
+    //DIRECT TEST Index Mode
+    
+    if (err_cnt > 0) begin
+        $display("\n%0t TEST FAILED",$realtime);
+        $display("Error count = %d\n", err_cnt);
+    end else
+        $display("\n%0t TEST PASSED\n", $realtime);
+    $finish;
+end
+
+initial begin
+    #(SIM_TIMEOUT)
+    $display("\n%0t TEST FAILED", $realtime);
+    $display("SIM TIMEOUT!\n");
+    $finish;
+end
+
+endmodule

Weiyet_RTLStructLib/source/Doubly_Linked_List/vip/pyuvm/Makefile

@@ -0,0 +1,61 @@
+# Makefile for Doubly Linked List pyUVM VIP
+
+SIM ?= icarus
+TOPLEVEL_LANG ?= verilog
+WAVES ?= 1  # Set 1 to enable waveform dump
+
+PWD=$(shell pwd)
+
+# RTL source files
+VERILOG_SOURCES = $(PWD)/../../src/doubly_linked_list.sv
+
+TOPLEVEL = doubly_linked_list  # DUT Top
+MODULE   = tb_dll  # Top Python file (without .py)
+
+# DUT parameters - passed to simulator
+COMPILE_ARGS = -Pdoubly_linked_list.DATA_WIDTH=8
+COMPILE_ARGS += -Pdoubly_linked_list.MAX_NODE=8
+
+# Set RANDOM_SEED number (optional)
+#PLUSARGS = +seed=42
+
+# Time units
+COCOTB_HDL_TIMEUNIT = 1ns
+COCOTB_HDL_TIMEPRECISION = 1ps
+
+# Icarus Verilog waveform dump
+ifeq ($(SIM), icarus)
+ifeq ($(WAVES), 1)
+	$(shell echo 'module iverilog_dump();' > iverilog_dump.v)
+	$(shell echo 'initial begin' >> iverilog_dump.v)
+	$(shell echo '    $$dumpfile("$(TOPLEVEL).vcd");' >> iverilog_dump.v)
+	$(shell echo '    $$dumpvars(0, $(TOPLEVEL));' >> iverilog_dump.v)
+	$(shell echo 'end' >> iverilog_dump.v)
+	$(shell echo 'endmodule' >> iverilog_dump.v)
+	VERILOG_SOURCES += $(PWD)/iverilog_dump.v
+	COMPILE_ARGS += -s iverilog_dump
+endif
+endif
+
+# Include cocotb Makefile
+include $(shell cocotb-config --makefiles)/Makefile.sim
+
+# Additional targets
+.PHONY: help
+help:
+	@echo "Doubly Linked List pyUVM VIP Makefile"
+	@echo "======================================"
+	@echo ""
+	@echo "Usage:"
+	@echo "  make                    - Run all tests with Icarus Verilog"
+	@echo "  make WAVES=0            - Disable waveforms"
+	@echo "  make clean              - Clean build files"
+	@echo ""
+	@echo "Environment Variables:"
+	@echo "  WAVES      - Enable waveforms (0/1)"
+	@echo "  PLUSARGS   - Additional simulator arguments"
+	@echo ""
+	@echo "Examples:"
+	@echo "  make                               # Run with icarus, waves enabled"
+	@echo "  make WAVES=0                       # Run without waveforms (faster)"
+	@echo "  make PLUSARGS=+seed=123            # Run with specific seed"

Weiyet_RTLStructLib/source/Doubly_Linked_List/vip/uvm/README.md

@@ -0,0 +1,242 @@
+# Doubly Linked List UVM VIP (Verification IP) User Guide
+
+## 📁 Directory Structure
+
+```
+uvm/
+├── README.md                                  [User guide and documentation]
+├── common/                                    [Core VIP source files]
+│   ├── dll_vip_pkg.sv                        [Main package + enums]
+│   ├── dll_vip_config.sv                     [Configuration class]
+│   └── dll_vip_seq_item.sv                   [Transaction definitions]
+├── interface/                                 [Interface definition]
+│   └── dll_vip_if.sv                         [Virtual interface]
+├── agent/                                     [Agent layer components]
+│   ├── dll_vip_driver.sv                     [Driver implementation]
+│   ├── dll_vip_monitor.sv                    [Monitor implementation]
+│   ├── dll_vip_sequencer.sv                  [Sequencer]
+│   └── dll_vip_agent.sv                      [Agent wrapper]
+├── env/                                       [Environment layer]
+│   ├── dll_vip_env.sv                        [Environment]
+│   └── dll_vip_scoreboard.sv                 [Checking with doubly linked list model]
+├── sequences/                                 [Test sequences]
+│   ├── dll_vip_base_seq.sv                   [Base sequence]
+│   ├── dll_vip_insert_seq.sv                 [Insert sequences (addr & index)]
+│   ├── dll_vip_read_seq.sv                   [Read sequence]
+│   └── dll_vip_delete_seq.sv                 [Delete sequences (addr, index, value)]
+└── sim/                                       [Testbench]
+    ├── tb_top.sv                              [Testbench top module]
+    └── tests/
+        ├── dll_vip_base_test.sv               [Base test class]
+        └── dll_vip_simple_test.sv             [Simple & random tests]
+```
+
+## 🚀 Quick Start
+
+**Step 1:** Update interface signals in your testbench:
+```systemverilog
+dll_vip_if dut_if(clk);
+// Connect to DUT
+uvm_config_db#(virtual dll_vip_if)::set(null, "*", "dll_vip_vif", dut_if);
+```
+
+**Step 2:** Configure DUT parameters in your test:
+```systemverilog
+cfg = dll_vip_config::type_id::create("cfg");
+cfg.DATA_WIDTH = 8;
+cfg.MAX_NODE = 8;
+uvm_config_db#(dll_vip_config)::set(this, "*", "dll_vip_cfg", cfg);
+```
+
+**Step 3:** Create environment:
+```systemverilog
+dll_env = dll_vip_env::type_id::create("dll_env", this);
+```
+
+## 🚀 Available Sequences
+
+**Insert at Address:**
+```systemverilog
+dll_vip_insert_at_addr_seq insert_seq = dll_vip_insert_at_addr_seq::type_id::create("insert_seq");
+insert_seq.num_inserts = 5;
+insert_seq.start(env.get_sequencer());
+```
+
+**Insert at Index:**
+```systemverilog
+dll_vip_insert_at_index_seq insert_seq = dll_vip_insert_at_index_seq::type_id::create("insert_seq");
+insert_seq.num_inserts = 5;
+insert_seq.start(env.get_sequencer());
+```
+
+**Read from Address:**
+```systemverilog
+dll_vip_read_seq read_seq = dll_vip_read_seq::type_id::create("read_seq");
+read_seq.num_reads = 5;
+read_seq.start(env.get_sequencer());
+```
+
+**Delete at Address:**
+```systemverilog
+dll_vip_delete_at_addr_seq delete_seq = dll_vip_delete_at_addr_seq::type_id::create("delete_seq");
+delete_seq.num_deletes = 3;
+delete_seq.start(env.get_sequencer());
+```
+
+**Delete at Index:**
+```systemverilog
+dll_vip_delete_at_index_seq delete_seq = dll_vip_delete_at_index_seq::type_id::create("delete_seq");
+delete_seq.num_deletes = 3;
+delete_seq.start(env.get_sequencer());
+```
+
+**Delete by Value:**
+```systemverilog
+dll_vip_delete_value_seq delete_seq = dll_vip_delete_value_seq::type_id::create("delete_seq");
+delete_seq.num_deletes = 2;
+delete_seq.start(env.get_sequencer());
+```
+
+## 🧪 Available Tests
+
+### 1. Simple Test
+Basic insert, read, and delete operations:
+```bash
+vsim -c +UVM_TESTNAME=simple_test -do "run -all; quit"
+```
+
+### 2. Random Test
+Random sequence of insert/read/delete operations:
+```bash
+vsim -c +UVM_TESTNAME=random_test -do "run -all; quit"
+```
+
+## 📋 Doubly Linked List Operations
+
+The VIP supports 6 operations matching the DUT (doubly_linked_list.sv):
+
+| Operation | op | Description | Inputs | Outputs |
+|-----------|-------|-------------|--------|---------|
+| **READ_ADDR** | 3'b000 | Read data at address | addr_in | data_out, pre_node_addr, next_node_addr |
+| **INSERT_AT_ADDR** | 3'b001 | Insert at address | addr_in, data_in | head, tail, length |
+| **DELETE_VALUE** | 3'b010 | Delete first occurrence of value | data_in | head, tail, length |
+| **DELETE_AT_ADDR** | 3'b011 | Delete node at address | addr_in | head, tail, length |
+| **INSERT_AT_INDEX** | 3'b101 | Insert at index position | addr_in (index), data_in | head, tail, length |
+| **DELETE_AT_INDEX** | 3'b111 | Delete at index position | addr_in (index) | head, tail, length |
+
+## ✅ Self-Checking Features
+
+The scoreboard automatically verifies:
+- ✅ Data integrity for READ operations
+- ✅ Correct list length after INSERT/DELETE
+- ✅ INSERT when full behavior
+- ✅ READ/DELETE when empty behavior
+- ✅ Address-based operations vs index-based operations
+- ✅ DELETE_VALUE finds correct first occurrence
+- ✅ Fault flag correctness
+- ✅ Head/tail pointer management
+
+## 📊 Test Coverage Comparison
+
+| tb/sv/tb.sv | UVM VIP Equivalent | Description |
+|-------------|-------------------|-------------|
+| `read_n_front()` (line 151) | `dll_vip_read_seq` | Read from front (head) |
+| `read_n_back()` (line 219) | `dll_vip_read_seq` | Read from back (tail) |
+| Insert operations | `dll_vip_insert_at_addr_seq` | Insert at address |
+| Insert operations | `dll_vip_insert_at_index_seq` | Insert at index |
+| Delete operations | `dll_vip_delete_at_addr_seq` | Delete at address |
+| Delete operations | `dll_vip_delete_at_index_seq` | Delete at index |
+| Delete operations | `dll_vip_delete_value_seq` | Delete by value |
+
+## 🔧 Key Features
+
+1. **Address-based and Index-based Operations**: Supports both addressing schemes
+2. **Doubly Linked Structure**: Tracks both previous and next node addresses
+3. **Value-based Deletion**: Can delete nodes by searching for value
+4. **Intelligent Scoreboard**: Models linked list with address and data tracking
+5. **Fault Detection**: Validates boundary conditions and error flags
+6. **Head/Tail Tracking**: Monitors list head and tail pointers
+
+## 🔍 Differences from Singly Linked List
+
+| Aspect | Singly Linked List | Doubly Linked List |
+|--------|-------------------|-------------------|
+| **Node Structure** | data + next pointer | data + next + previous pointers |
+| **Traversal** | Forward only | Forward and backward |
+| **Operations** | 8 ops (includes sort, sum) | 6 ops (focus on insert/delete/read) |
+| **Address Outputs** | Single next pointer | Both pre and next pointers |
+| **Complexity** | Higher (functional ops) | Moderate (structural focus) |
+
+## 🚨 Common Issues & Solutions
+
+### Issue: Interface signal width mismatch
+**Solution:** Update `dll_vip_if.sv` lines 9-19 to match your DLL's parameters:
+```systemverilog
+logic [DATA_WIDTH-1:0] data_in;
+logic [ADDR_WIDTH-1:0] addr_in;
+logic [DATA_WIDTH-1:0] data_out;
+logic [ADDR_WIDTH-1:0] pre_node_addr;
+logic [ADDR_WIDTH-1:0] next_node_addr;
+```
+
+### Issue: Address vs Index confusion
+**Solution:**
+- **Address operations (op[2]==0)**: Use actual node addresses from DUT
+- **Index operations (op[2]==1)**: Use sequential index (0, 1, 2, ...)
+
+### Future Work
+- Add assertions for doubly-linked integrity (prev->next consistency)
+- Add functional coverage for:
+  - Insert/delete at head/tail/middle
+  - Forward vs backward traversal
+  - Empty to full transitions
+- Enhanced scoreboard to track full doubly-linked structure
+
+## 📚 Example Usage
+
+```systemverilog
+class my_test extends base_test;
+    `uvm_component_utils(my_test)
+
+    task run_phase(uvm_phase phase);
+        dll_vip_insert_at_index_seq insert_seq;
+        dll_vip_read_seq read_seq;
+        dll_vip_delete_value_seq delete_seq;
+
+        phase.raise_objection(this);
+
+        // Build a list
+        insert_seq = dll_vip_insert_at_index_seq::type_id::create("insert_seq");
+        insert_seq.num_inserts = 5;
+        insert_seq.start(env.get_sequencer());
+
+        #500ns;
+
+        // Read from front to back
+        read_seq = dll_vip_read_seq::type_id::create("read_seq");
+        read_seq.num_reads = 5;
+        read_seq.start(env.get_sequencer());
+
+        #500ns;
+
+        // Delete specific values
+        delete_seq = dll_vip_delete_value_seq::type_id::create("delete_seq");
+        delete_seq.num_deletes = 2;
+        delete_seq.start(env.get_sequencer());
+
+        #500ns;
+        phase.drop_objection(this);
+    endtask
+endclass
+```
+
+## 🎯 Key Characteristics
+
+- **Bidirectional Traversal**: Can navigate both forward (head→tail) and backward (tail→head)
+- **Address Management**: Internal addresses managed by DUT, not sequential
+- **Flexible Insert/Delete**: Supports both address-based and index-based operations
+- **Value Search**: Can find and delete nodes by data value
+
+**Happy Verifying! 🚀**
+
+*This VIP demonstrates advanced verification of pointer-based data structures with UVM.*

Weiyet_RTLStructLib/source/FIFO/vip/pyuvm/agent/__init__.py

@@ -0,0 +1,9 @@
+"""
+FIFO VIP Agent Components
+Create Date: 01/05/2026
+"""
+
+from .fifo_vip_driver import *
+from .fifo_vip_monitor import *
+from .fifo_vip_sequencer import *
+from .fifo_vip_agent import *

Weiyet_RTLStructLib/source/FIFO/vip/pyuvm/agent/fifo_vip_driver.py

@@ -0,0 +1,100 @@
+"""
+FIFO VIP Driver
+Create Date: 01/05/2026
+"""
+
+from pyuvm import *
+import cocotb
+from cocotb.triggers import RisingEdge, FallingEdge
+from ..common.fifo_vip_types import FifoOp
+
+
+class FifoVipDriver(uvm_driver):
+    """Driver for FIFO transactions"""
+
+    def __init__(self, name, parent, driver_type="WR"):
+        super().__init__(name, parent)
+        self.driver_type = driver_type  # "WR" or "RD"
+        self.dut = None
+        self.cfg = None
+
+    def build_phase(self):
+        super().build_phase()
+        # Get DUT handle
+        self.dut = cocotb.top
+        # Get config
+        self.cfg = ConfigDB().get(self, "", "fifo_vip_cfg")
+        if self.cfg is None:
+            self.logger.critical("No config found")
+
+    async def run_phase(self):
+        """Main driver run phase"""
+        # Initialize signals
+        if self.driver_type == "WR":
+            self.dut.wr_en.value = 0
+            self.dut.data_wr.value = 0
+            # Wait for reset
+            await FallingEdge(self.dut.rst)
+            await RisingEdge(self.dut.wr_clk)
+        else:  # RD
+            self.dut.rd_en.value = 0
+            # Wait for reset
+            await FallingEdge(self.dut.rst)
+            await RisingEdge(self.dut.rd_clk)
+
+        # Main loop
+        while True:
+            item = await self.seq_item_port.get_next_item()
+            await self.drive_item(item)
+            self.seq_item_port.item_done()
+
+    async def drive_item(self, item):
+        """Drive a single transaction"""
+        # Set config on item
+        item.set_config(self.cfg)
+
+        if item.op == FifoOp.WRITE and self.driver_type == "WR":
+            await self.drive_write(item)
+        elif item.op == FifoOp.READ and self.driver_type == "RD":
+            await self.drive_read(item)
+        elif item.op == FifoOp.IDLE:
+            # Just wait 2 clocks
+            if self.driver_type == "WR":
+                await RisingEdge(self.dut.wr_clk)
+                await RisingEdge(self.dut.wr_clk)
+            else:
+                await RisingEdge(self.dut.rd_clk)
+                await RisingEdge(self.dut.rd_clk)
+
+    async def drive_write(self, item):
+        """Drive write transaction"""
+        await RisingEdge(self.dut.wr_clk)
+        # Mask data to correct width
+        data_mask = (1 << self.cfg.DATA_WIDTH) - 1
+        self.dut.data_wr.value = item.data & data_mask
+        self.dut.wr_en.value = 1
+
+        await RisingEdge(self.dut.wr_clk)
+        item.full = bool(self.dut.fifo_full.value)
+        item.success = not item.full
+        self.dut.wr_en.value = 0
+
+        self.logger.debug(f"WR_DRV: Write: {item.convert2string()}")
+
+    async def drive_read(self, item):
+        """Drive read transaction"""
+        await RisingEdge(self.dut.rd_clk)
+        self.dut.rd_en.value = 1
+
+        await RisingEdge(self.dut.rd_clk)
+        item.empty = bool(self.dut.fifo_empty.value)
+        item.success = not item.empty
+
+        # Wait extra cycle for buffered read
+        if self.cfg.RD_BUFFER:
+            await RisingEdge(self.dut.rd_clk)
+
+        item.read_data = int(self.dut.data_rd.value)
+        self.dut.rd_en.value = 0
+
+        self.logger.debug(f"RD_DRV: Read: {item.convert2string()}")

Weiyet_RTLStructLib/source/FIFO/vip/pyuvm/agent/fifo_vip_sequencer.py

@@ -0,0 +1,16 @@
+"""
+FIFO VIP Sequencer
+Create Date: 01/05/2026
+"""
+
+from pyuvm import *
+
+
+class FifoVipSequencer(uvm_sequencer):
+    """Sequencer for FIFO transactions"""
+
+    def __init__(self, name, parent):
+        super().__init__(name, parent)
+
+    def build_phase(self):
+        super().build_phase()

Weiyet_RTLStructLib/source/FIFO/vip/pyuvm/common/__init__.py

@@ -0,0 +1,8 @@
+"""
+FIFO VIP Common Components
+Create Date: 01/05/2026
+"""
+
+from .fifo_vip_config import *
+from .fifo_vip_seq_item import *
+from .fifo_vip_types import *

Weiyet_RTLStructLib/source/FIFO/vip/pyuvm/common/fifo_vip_config.py

@@ -0,0 +1,39 @@
+"""
+FIFO VIP Configuration Class
+Create Date: 01/05/2026
+"""
+
+from pyuvm import *
+from .fifo_vip_types import FifoAgentMode
+
+
+class FifoVipConfig(uvm_object):
+    """Configuration object for FIFO VIP"""
+
+    def __init__(self, name="fifo_vip_config"):
+        super().__init__(name)
+        # DUT parameters - CHANGE THESE FOR YOUR FIFO
+        self.DEPTH = 12
+        self.DATA_WIDTH = 8
+        self.ASYNC = 1  # 1=async clocks, 0=sync
+        self.RD_BUFFER = 1  # 1=buffered read, 0=combinational
+
+        # VIP control
+        self.has_wr_agent = True
+        self.has_rd_agent = True
+        self.enable_scoreboard = True
+
+        # Agent modes
+        self.wr_agent_mode = FifoAgentMode.MASTER
+        self.rd_agent_mode = FifoAgentMode.MASTER
+
+    def print_config(self):
+        """Print configuration"""
+        self.logger.info(
+            f"DEPTH={self.DEPTH}, DATA_WIDTH={self.DATA_WIDTH}, "
+            f"ASYNC={self.ASYNC}, RD_BUFFER={self.RD_BUFFER}"
+        )
+
+    def __str__(self):
+        return (f"FifoVipConfig: DEPTH={self.DEPTH}, DATA_WIDTH={self.DATA_WIDTH}, "
+                f"ASYNC={self.ASYNC}, RD_BUFFER={self.RD_BUFFER}")

Weiyet_RTLStructLib/source/FIFO/vip/pyuvm/common/fifo_vip_seq_item.py

@@ -0,0 +1,63 @@
+"""
+FIFO VIP Sequence Item
+Create Date: 01/05/2026
+"""
+
+from pyuvm import *
+from .fifo_vip_types import FifoOp
+import random
+
+
+class FifoVipSeqItem(uvm_sequence_item):
+    """Sequence item for FIFO transactions"""
+
+    def __init__(self, name="fifo_vip_seq_item"):
+        super().__init__(name)
+        # Transaction fields
+        self.op = FifoOp.WRITE
+        self.data = 0
+
+        # Response fields
+        self.read_data = 0
+        self.full = False
+        self.empty = False
+        self.success = True
+
+        # Config reference
+        self.cfg = None
+
+    def randomize(self):
+        """Randomize transaction fields"""
+        # Randomize operation
+        self.op = random.choice([FifoOp.WRITE, FifoOp.READ])
+
+        # Randomize data based on config
+        if self.cfg is not None:
+            max_val = (1 << self.cfg.DATA_WIDTH) - 1
+        else:
+            max_val = 255  # 8-bit default
+
+        self.data = random.randint(0, max_val)
+        return True
+
+    def randomize_with_op(self, op):
+        """Randomize with specific operation"""
+        self.op = op
+        if self.cfg is not None:
+            max_val = (1 << self.cfg.DATA_WIDTH) - 1
+        else:
+            max_val = 255
+        self.data = random.randint(0, max_val)
+        return True
+
+    def set_config(self, cfg):
+        """Set configuration reference"""
+        self.cfg = cfg
+
+    def convert2string(self):
+        """Convert to string for printing"""
+        return (f"Op:{self.op.name} Data:0x{self.data:x} ReadData:0x{self.read_data:x} "
+                f"Full:{self.full} Empty:{self.empty} Success:{self.success}")
+
+    def __str__(self):
+        return self.convert2string()

Weiyet_RTLStructLib/source/FIFO/vip/pyuvm/common/fifo_vip_types.py

@@ -0,0 +1,20 @@
+"""
+FIFO VIP Types and Enums
+Create Date: 01/05/2026
+"""
+
+from enum import Enum, auto
+
+
+class FifoOp(Enum):
+    """FIFO operation types"""
+    WRITE = auto()
+    READ = auto()
+    IDLE = auto()
+
+
+class FifoAgentMode(Enum):
+    """Agent mode types"""
+    MASTER = auto()
+    SLAVE = auto()
+    MONITOR_ONLY = auto()

Weiyet_RTLStructLib/source/FIFO/vip/pyuvm/env/__init__.py

@@ -0,0 +1,7 @@
+"""
+FIFO VIP Environment Components
+Create Date: 01/05/2026
+"""
+
+from .fifo_vip_scoreboard import *
+from .fifo_vip_env import *

Weiyet_RTLStructLib/source/FIFO/vip/pyuvm/env/fifo_vip_env.py

@@ -0,0 +1,68 @@
+"""
+FIFO VIP Environment
+Create Date: 01/05/2026
+"""
+
+from pyuvm import *
+from ..agent.fifo_vip_agent import FifoVipAgent
+from .fifo_vip_scoreboard import FifoVipScoreboard
+
+
+class FifoVipEnv(uvm_env):
+    """Environment for FIFO VIP"""
+
+    def __init__(self, name, parent):
+        super().__init__(name, parent)
+        self.cfg = None
+        self.wr_agent = None
+        self.rd_agent = None
+        self.sb = None
+
+    def build_phase(self):
+        super().build_phase()
+
+        # Get config
+        self.cfg = ConfigDB().get(self, "", "fifo_vip_cfg")
+        if self.cfg is None:
+            self.logger.critical("No config found")
+
+        # Set config for all components
+        ConfigDB().set(self, "*", "fifo_vip_cfg", self.cfg)
+
+        # Create agents
+        if self.cfg.has_wr_agent:
+            self.wr_agent = FifoVipAgent("wr_agent", self, agent_type="WR")
+
+        if self.cfg.has_rd_agent:
+            self.rd_agent = FifoVipAgent("rd_agent", self, agent_type="RD")
+
+        # Create scoreboard
+        if self.cfg.enable_scoreboard:
+            self.sb = FifoVipScoreboard("sb", self)
+
+    def connect_phase(self):
+        super().connect_phase()
+
+        # Connect agents to scoreboard
+        if self.cfg.enable_scoreboard and self.sb is not None:
+            if self.wr_agent is not None:
+                self.wr_agent.ap.connect(self.sb.wr_export)
+                # Connect write callback
+                self.sb.wr_export.connect_transaction_handler(self.sb.write_wr)
+
+            if self.rd_agent is not None:
+                self.rd_agent.ap.connect(self.sb.rd_export)
+                # Connect read callback
+                self.sb.rd_export.connect_transaction_handler(self.sb.write_rd)
+
+    def get_wr_sequencer(self):
+        """Get write sequencer"""
+        if self.wr_agent is not None:
+            return self.wr_agent.sequencer
+        return None
+
+    def get_rd_sequencer(self):
+        """Get read sequencer"""
+        if self.rd_agent is not None:
+            return self.rd_agent.sequencer
+        return None

Weiyet_RTLStructLib/source/FIFO/vip/pyuvm/env/fifo_vip_scoreboard.py

@@ -0,0 +1,73 @@
+"""
+FIFO VIP Scoreboard
+Create Date: 01/05/2026
+"""
+
+from pyuvm import *
+from ..common.fifo_vip_types import FifoOp
+
+
+class FifoVipScoreboard(uvm_scoreboard):
+    """Scoreboard for FIFO VIP"""
+
+    def __init__(self, name, parent):
+        super().__init__(name, parent)
+        # Simple queue model
+        self.fifo_model = []
+        self.errors = 0
+        self.wr_count = 0
+        self.rd_count = 0
+
+        # Create analysis exports
+        self.wr_export = uvm_analysis_export("wr_export", self)
+        self.rd_export = uvm_analysis_export("rd_export", self)
+
+    def build_phase(self):
+        super().build_phase()
+
+    def connect_phase(self):
+        super().connect_phase()
+
+    def write_wr(self, item):
+        """Write port callback for write transactions"""
+        if item.op == FifoOp.WRITE and item.success:
+            self.fifo_model.append(item.data)
+            self.wr_count += 1
+            self.logger.info(
+                f"SB: Write: data=0x{item.data:x}, queue_size={len(self.fifo_model)}"
+            )
+
+    def write_rd(self, item):
+        """Write port callback for read transactions"""
+        if item.op == FifoOp.READ and item.success:
+            if len(self.fifo_model) > 0:
+                expected = self.fifo_model.pop(0)
+                self.rd_count += 1
+                if item.read_data == expected:
+                    self.logger.info(
+                        f"SB: Read OK: data=0x{item.read_data:x}, queue_size={len(self.fifo_model)}"
+                    )
+                else:
+                    self.logger.error(
+                        f"SB: Data mismatch! Expected:0x{expected:x} Got:0x{item.read_data:x}"
+                    )
+                    self.errors += 1
+            else:
+                self.logger.error("SB: Read from empty FIFO model")
+                self.errors += 1
+
+    def report_phase(self):
+        """Report phase - print results"""
+        self.logger.info(f"\n{'='*50}")
+        self.logger.info(f"FIFO VIP Scoreboard Report")
+        self.logger.info(f"{'='*50}")
+        self.logger.info(f"Total Writes: {self.wr_count}")
+        self.logger.info(f"Total Reads: {self.rd_count}")
+        self.logger.info(f"Errors: {self.errors}")
+        self.logger.info(f"Final Queue Size: {len(self.fifo_model)}")
+
+        if self.errors == 0:
+            self.logger.info("*** TEST PASSED ***")
+        else:
+            self.logger.error(f"*** TEST FAILED - {self.errors} errors ***")
+        self.logger.info(f"{'='*50}\n")

Weiyet_RTLStructLib/source/FIFO/vip/pyuvm/sequences/__init__.py

@@ -0,0 +1,8 @@
+"""
+FIFO VIP Sequences
+Create Date: 01/05/2026
+"""
+
+from .fifo_vip_base_seq import *
+from .fifo_vip_write_req_seq import *
+from .fifo_vip_read_req_seq import *

Weiyet_RTLStructLib/source/FIFO/vip/pyuvm/sequences/fifo_vip_base_seq.py

@@ -0,0 +1,13 @@
+"""
+FIFO VIP Base Sequence
+Create Date: 01/05/2026
+"""
+
+from pyuvm import *
+
+
+class FifoVipBaseSeq(uvm_sequence):
+    """Base sequence for FIFO VIP"""
+
+    def __init__(self, name="fifo_vip_base_seq"):
+        super().__init__(name)

Weiyet_RTLStructLib/source/FIFO/vip/pyuvm/sequences/fifo_vip_read_req_seq.py

@@ -0,0 +1,28 @@
+"""
+FIFO VIP Read Request Sequence
+Create Date: 01/05/2026
+"""
+
+from pyuvm import *
+from .fifo_vip_base_seq import FifoVipBaseSeq
+from ..common.fifo_vip_seq_item import FifoVipSeqItem
+from ..common.fifo_vip_types import FifoOp
+import random
+
+
+class FifoVipReadReqSeq(FifoVipBaseSeq):
+    """Read request sequence for FIFO VIP"""
+
+    def __init__(self, name="fifo_vip_read_req_seq"):
+        super().__init__(name)
+        self.num_reads = random.randint(1, 20)
+
+    async def body(self):
+        """Sequence body"""
+        self.logger.info(f"RD_SEQ: Starting {self.num_reads} reads")
+
+        for i in range(self.num_reads):
+            item = FifoVipSeqItem(f"rd_item_{i}")
+            await self.start_item(item)
+            item.randomize_with_op(FifoOp.READ)
+            await self.finish_item(item)

Weiyet_RTLStructLib/source/FIFO/vip/pyuvm/sequences/fifo_vip_write_req_seq.py

@@ -0,0 +1,28 @@
+"""
+FIFO VIP Write Request Sequence
+Create Date: 01/05/2026
+"""
+
+from pyuvm import *
+from .fifo_vip_base_seq import FifoVipBaseSeq
+from ..common.fifo_vip_seq_item import FifoVipSeqItem
+from ..common.fifo_vip_types import FifoOp
+import random
+
+
+class FifoVipWriteReqSeq(FifoVipBaseSeq):
+    """Write request sequence for FIFO VIP"""
+
+    def __init__(self, name="fifo_vip_write_req_seq"):
+        super().__init__(name)
+        self.num_writes = random.randint(1, 20)
+
+    async def body(self):
+        """Sequence body"""
+        self.logger.info(f"WR_SEQ: Starting {self.num_writes} writes")
+
+        for i in range(self.num_writes):
+            item = FifoVipSeqItem(f"wr_item_{i}")
+            await self.start_item(item)
+            item.randomize_with_op(FifoOp.WRITE)
+            await self.finish_item(item)

Weiyet_RTLStructLib/source/FIFO/vip/uvm/agent/fifo_vip_agent.sv

@@ -0,0 +1,45 @@
+//////////////////////////////////////////////////////////////////////////////////
+// 
+// Create Date: 05/24/2024 03:37 PM
+// Last Update Date: 05/24/2024 08:57 PM
+// Module Name: fifo_vip_agent
+// Author: https://www.linkedin.com/in/wei-yet-ng-065485119/
+// Description: This package contains the FIFO VIP agent.
+// 
+//////////////////////////////////////////////////////////////////////////////////
+
+class fifo_vip_agent extends uvm_agent;
+    `uvm_component_utils(fifo_vip_agent)
+    
+    fifo_vip_driver driver;
+    fifo_vip_monitor monitor;
+    fifo_vip_sequencer sequencer;
+    
+    uvm_analysis_port #(fifo_vip_seq_item) ap;
+    
+    function new(string name = "fifo_vip_agent", uvm_component parent = null);
+        super.new(name, parent);
+    endfunction
+    
+    function void build_phase(uvm_phase phase);
+        super.build_phase(phase);
+        
+        monitor = fifo_vip_monitor::type_id::create("monitor", this);
+        
+        if (is_active == UVM_ACTIVE) begin
+            driver = fifo_vip_driver::type_id::create("driver", this);
+            sequencer = fifo_vip_sequencer::type_id::create("sequencer", this);
+        end
+    endfunction
+    
+    function void connect_phase(uvm_phase phase);
+        super.connect_phase(phase);
+        
+        ap = monitor.ap;
+        
+        if (is_active == UVM_ACTIVE) begin
+            driver.seq_item_port.connect(sequencer.seq_item_export);
+        end
+    endfunction
+
+endclass

Weiyet_RTLStructLib/source/FIFO/vip/uvm/agent/fifo_vip_driver.sv

@@ -0,0 +1,89 @@
+//////////////////////////////////////////////////////////////////////////////////
+// 
+// Create Date: 05/24/2024 03:37 PM
+// Last Update Date: 05/24/2024 08:45 PM
+// Module Name: fifo_vip_driver
+// Author: https://www.linkedin.com/in/wei-yet-ng-065485119/
+// Description: This package contains the FIFO VIP driver.
+// 
+//////////////////////////////////////////////////////////////////////////////////
+
+
+class fifo_vip_driver extends uvm_driver #(fifo_vip_seq_item);
+    `uvm_component_utils(fifo_vip_driver)
+    
+    virtual fifo_vip_if vif;
+    fifo_vip_config cfg;
+    string driver_type; // "WR" or "RD"
+    
+    function new(string name = "fifo_vip_driver", uvm_component parent = null);
+        super.new(name, parent);
+    endfunction
+    
+    function void build_phase(uvm_phase phase);
+        if (!uvm_config_db#(virtual fifo_vip_if)::get(this, "", "vif", vif))
+            `uvm_fatal("DRV", "No virtual interface")
+        if (!uvm_config_db#(fifo_vip_config)::get(this, "", "cfg", cfg))
+            `uvm_fatal("DRV", "No config")
+            
+        // Figure out if this is write or read driver
+        driver_type = (get_name().substr(0,1) == "w") ? "WR" : "RD";
+    endfunction
+    
+    task run_phase(uvm_phase phase);
+        fifo_vip_seq_item item;
+        
+        // Initialize
+        if (driver_type == "WR") begin
+            vif.wr_cb.wr_en <= 0;
+            vif.wr_cb.data_wr <= 0;
+        end else begin
+            vif.rd_cb.rd_en <= 0;
+        end
+        
+        // Wait for reset
+        @(negedge vif.rst);
+        @(posedge vif.wr_clk);
+        
+        forever begin
+            seq_item_port.get_next_item(item);
+            drive_item(item);
+            seq_item_port.item_done();
+        end
+    endtask
+    
+    task drive_item(fifo_vip_seq_item item);
+        // Set config on item
+        item.set_config(cfg);
+        
+        case (item.op)
+            WRITE: if (driver_type == "WR") drive_write(item);
+            READ:  if (driver_type == "RD") drive_read(item);
+            IDLE:  repeat(2) @(vif.wr_cb);
+        endcase
+    endtask
+    
+    task drive_write(fifo_vip_seq_item item);
+        @(vif.wr_cb);
+        vif.wr_cb.data_wr <= item.data[cfg.DATA_WIDTH-1:0];
+        vif.wr_cb.wr_en <= 1;
+        @(vif.wr_cb);
+        item.full = vif.wr_cb.fifo_full;
+        item.success = !vif.wr_cb.fifo_full;
+        vif.wr_cb.wr_en <= 0;
+        `uvm_info("WR_DRV", $sformatf("Write: %s", item.convert2string()), UVM_HIGH)
+    endtask
+    
+    task drive_read(fifo_vip_seq_item item);
+        @(vif.rd_cb);
+        vif.rd_cb.rd_en <= 1;
+        @(vif.rd_cb);
+        item.empty = vif.rd_cb.fifo_empty;
+        item.success = !vif.rd_cb.fifo_empty;
+        if (cfg.RD_BUFFER) @(vif.rd_cb); // Wait extra cycle for buffered read
+        item.read_data = vif.rd_cb.data_rd;
+        vif.rd_cb.rd_en <= 0;
+        `uvm_info("RD_DRV", $sformatf("Read: %s", item.convert2string()), UVM_HIGH)
+    endtask
+
+endclass

Weiyet_RTLStructLib/source/FIFO/vip/uvm/agent/fifo_vip_monitor.sv

@@ -0,0 +1,77 @@
+//////////////////////////////////////////////////////////////////////////////////
+// 
+// Create Date: 05/24/2024 03:37 PM
+// Last Update Date: 05/24/2024 08:56 PM
+// Module Name: fifo_vip_monitor
+// Author: https://www.linkedin.com/in/wei-yet-ng-065485119/
+// Description: This package contains the FIFO VIP monitor.
+// 
+//////////////////////////////////////////////////////////////////////////////////
+
+class fifo_vip_monitor extends uvm_monitor;
+    `uvm_component_utils(fifo_vip_monitor)
+    
+    virtual fifo_vip_if vif;
+    fifo_vip_config cfg;
+    uvm_analysis_port #(fifo_vip_seq_item) ap;
+    string monitor_type; // "WR" or "RD"
+    
+    function new(string name = "fifo_vip_monitor", uvm_component parent = null);
+        super.new(name, parent);
+        ap = new("ap", this);
+    endfunction
+    
+    function void build_phase(uvm_phase phase);
+        if (!uvm_config_db#(virtual fifo_vip_if)::get(this, "", "fifo_vip_vif", vif))
+            `uvm_fatal("MON", "No virtual interface")
+        if (!uvm_config_db#(fifo_vip_config)::get(this, "", "fifo_vip_cfg", cfg))
+            `uvm_fatal("MON", "No config")
+            
+        // Figure out monitor type
+        monitor_type = (get_name().substr(0,1) == "w") ? "WR" : "RD";
+    endfunction
+    
+    task run_phase(uvm_phase phase);
+        @(negedge vif.rst);
+        
+        if (monitor_type == "WR") begin
+            monitor_writes();
+        end else begin
+            monitor_reads();
+        end
+    endtask
+    
+    task monitor_writes();
+        fifo_vip_seq_item item;
+        forever begin
+            @(posedge vif.wr_clk);
+            if (vif.wr_en && !vif.rst) begin
+                item = fifo_vip_seq_item::type_id::create("wr_item");
+                item.op = WRITE;
+                item.data = vif.data_wr;
+                item.full = vif.fifo_full;
+                item.success = !vif.fifo_full;
+                ap.write(item);
+                `uvm_info("WR_MON", $sformatf("Monitored: %s", item.convert2string()), UVM_HIGH)
+            end
+        end
+    endtask
+    
+    task monitor_reads();
+        fifo_vip_seq_item item;
+        forever begin
+            @(posedge vif.rd_clk);
+            if (vif.rd_en && !vif.rst) begin
+                item = fifo_vip_seq_item::type_id::create("rd_item");
+                item.op = READ;
+                item.empty = vif.fifo_empty;
+                item.success = !vif.fifo_empty;
+                if (cfg.RD_BUFFER) @(posedge vif.rd_clk); // Wait for buffered read
+                item.read_data = vif.data_rd;
+                ap.write(item);
+                `uvm_info("RD_MON", $sformatf("Monitored: %s", item.convert2string()), UVM_HIGH)
+            end
+        end
+    endtask
+
+endclass

Weiyet_RTLStructLib/source/FIFO/vip/uvm/agent/fifo_vip_sequencer.sv

@@ -0,0 +1,19 @@
+//////////////////////////////////////////////////////////////////////////////////
+// 
+// Create Date: 05/24/2024 03:37 PM
+// Last Update Date: 05/24/2024 09:25 PM
+// Module Name: fifo_vip_sequencer
+// Author: https://www.linkedin.com/in/wei-yet-ng-065485119/
+// Description: This package contains all the components of the FIFO VIP.
+// 
+//////////////////////////////////////////////////////////////////////////////////
+
+
+class fifo_vip_sequencer extends uvm_sequencer #(fifo_vip_seq_item);
+    `uvm_component_utils(fifo_vip_sequencer)
+    
+    function new(string name = "fifo_vip_sequencer", uvm_component parent = null);
+        super.new(name, parent);
+    endfunction
+
+endclass

Weiyet_RTLStructLib/source/FIFO/vip/uvm/common/fifo_vip_config.sv

@@ -0,0 +1,38 @@
+//////////////////////////////////////////////////////////////////////////////////
+// 
+// Create Date: 05/24/2024 03:37 PM
+// Last Update Date: 05/24/2024 08:41 PM
+// Module Name: fifo_vip_config
+// Author: https://www.linkedin.com/in/wei-yet-ng-065485119/
+// Description: This package contains the configuration class for the FIFO VIP.
+// 
+//////////////////////////////////////////////////////////////////////////////////
+
+class fifo_vip_config extends uvm_object;
+    `uvm_object_utils(fifo_vip_config)
+    
+    // DUT parameters - CHANGE THESE FOR YOUR FIFO
+    int DEPTH = 12;
+    int DATA_WIDTH = 8;
+    bit ASYNC = 1;
+    bit RD_BUFFER = 1;
+    
+    // VIP control
+    bit has_wr_agent = 1;
+    bit has_rd_agent = 1;
+    bit enable_scoreboard = 1;
+    
+    // Agent modes
+    fifo_agent_mode_e wr_agent_mode = MASTER;
+    fifo_agent_mode_e rd_agent_mode = MASTER;
+    
+    function new(string name = "fifo_vip_config");
+        super.new(name);
+    endfunction
+    
+    function void print_config();
+        `uvm_info("CFG", $sformatf("DEPTH=%0d, DATA_WIDTH=%0d, ASYNC=%0b, RD_BUFFER=%0b", 
+                 DEPTH, DATA_WIDTH, ASYNC, RD_BUFFER), UVM_LOW)
+    endfunction
+
+endclass

Weiyet_RTLStructLib/source/FIFO/vip/uvm/common/fifo_vip_pkg.sv

@@ -0,0 +1,42 @@
+//////////////////////////////////////////////////////////////////////////////////
+// 
+// Create Date: 05/24/2024 03:37 PM
+// Last Update Date: 05/24/2024 10:37 PM
+// Module Name: fifo_vip_pkg
+// Author: https://www.linkedin.com/in/wei-yet-ng-065485119/
+// Description: This package contains all the components of the FIFO VIP.
+// 
+//////////////////////////////////////////////////////////////////////////////////
+
+package fifo_vip_pkg;
+    
+    import uvm_pkg::*;
+    `include "uvm_macros.svh"
+    
+    // Types and enums defined directly in package
+    typedef enum {
+        WRITE,
+        READ,
+        IDLE
+    } fifo_op_e;
+    
+    typedef enum {
+        MASTER,
+        SLAVE,
+        MONITOR_ONLY
+    } fifo_agent_mode_e;
+    
+    // Include files in order
+    `include "../src/fifo_vip_config.sv"
+    `include "../src/fifo_vip_seq_item.sv"
+    `include "../agent/fifo_vip_driver.sv"
+    `include "../agent/fifo_vip_monitor.sv"
+    `include "../agent/fifo_vip_sequencer.sv"
+    `include "../agent/fifo_vip_agent.sv"
+    `include "../env/fifo_vip_scoreboard.sv"
+    `include "../env/fifo_vip_env.sv"
+    `include "../sequences/fifo_vip_base_seq.sv"
+    `include "../sequences/fifo_vip_write_req_seq.sv"
+    `include "../sequences/fifo_vip_read_req_seq.sv"
+    
+endpackage

Weiyet_RTLStructLib/source/FIFO/vip/uvm/common/fifo_vip_seq_item.sv

@@ -0,0 +1,50 @@
+//////////////////////////////////////////////////////////////////////////////////
+// 
+// Create Date: 05/24/2024 03:37 PM
+// Last Update Date: 05/24/2024 08:37 PM
+// Module Name: fifo_vip_seq_item
+// Author: https://www.linkedin.com/in/wei-yet-ng-065485119/
+// Description: This package contains the sequence item for the FIFO VIP.
+// 
+//////////////////////////////////////////////////////////////////////////////////
+
+class fifo_vip_seq_item extends uvm_sequence_item;
+    `uvm_object_utils(fifo_vip_seq_item)
+    
+    // Transaction fields
+    rand fifo_op_e op;
+    rand bit [31:0] data;
+    
+    // Response fields
+    bit [31:0] read_data;
+    bit full;
+    bit empty;
+    bit success;
+    
+    // Config reference
+    fifo_vip_config cfg;
+    
+    // Simple constraints
+    constraint op_dist {
+        op dist {WRITE := 50, READ := 50};
+    }
+    
+    constraint data_c {
+        if (cfg != null) {
+            data < (1 << cfg.DATA_WIDTH);
+        } else {
+            data < 256; // 8-bit default
+        }
+    }
+    
+    function new(string name = "fifo_vip_seq_item");
+        super.new(name);
+        success = 1;
+    endfunction
+    
+    function string convert2string();
+        return $sformatf("Op:%s Data:0x%0h ReadData:0x%0h Full:%0b Empty:%0b Success:%0b", 
+                        op.name(), data, read_data, full, empty, success);
+    endfunction
+
+endclass

Weiyet_RTLStructLib/source/FIFO/vip/uvm/env/fifo_vip_env.sv

@@ -0,0 +1,64 @@
+//////////////////////////////////////////////////////////////////////////////////
+// 
+// Create Date: 05/24/2024 03:37 PM
+// Last Update Date: 05/24/2024 08:57 PM
+// Module Name: fifo_vip_env
+// Author: https://www.linkedin.com/in/wei-yet-ng-065485119/
+// Description: This package contains the FIFO VIP environment.
+// 
+//////////////////////////////////////////////////////////////////////////////////
+class fifo_vip_env extends uvm_env;
+    `uvm_component_utils(fifo_vip_env)
+    
+    fifo_vip_config cfg;
+    fifo_vip_agent wr_agent;
+    fifo_vip_agent rd_agent;
+    fifo_vip_scoreboard sb;
+    
+    function new(string name = "fifo_vip_env", uvm_component parent = null);
+        super.new(name, parent);
+    endfunction
+    
+    function void build_phase(uvm_phase phase);
+        super.build_phase(phase);
+        
+        if (!uvm_config_db#(fifo_vip_config)::get(this, "", "fifo_vip_cfg", cfg))
+            `uvm_fatal("ENV", "No config")
+        
+        // Set config for all components
+        uvm_config_db#(fifo_vip_config)::set(this, "*", "fifo_vip_cfg", cfg);
+        
+        // Create agents
+        if (cfg.has_wr_agent) begin
+            wr_agent = fifo_vip_agent::type_id::create("wr_agent", this);
+        end
+        
+        if (cfg.has_rd_agent) begin
+            rd_agent = fifo_vip_agent::type_id::create("rd_agent", this);
+        end
+        
+        // Create scoreboard
+        if (cfg.enable_scoreboard) begin
+            sb = fifo_vip_scoreboard::type_id::create("sb", this);
+        end
+    endfunction
+    
+    function void connect_phase(uvm_phase phase);
+        super.connect_phase(phase);
+        
+        if (cfg.enable_scoreboard && sb != null) begin
+            if (wr_agent != null) wr_agent.ap.connect(sb.wr_imp);
+            if (rd_agent != null) rd_agent.ap.connect(sb.rd_imp);
+        end
+    endfunction
+    
+    // Helper functions for tests
+    function fifo_vip_sequencer get_wr_sequencer();
+        return (wr_agent != null) ? wr_agent.sequencer : null;
+    endfunction
+    
+    function fifo_vip_sequencer get_rd_sequencer();
+        return (rd_agent != null) ? rd_agent.sequencer : null;
+    endfunction
+
+endclass

Weiyet_RTLStructLib/source/FIFO/vip/uvm/env/fifo_vip_scoreboard.sv

@@ -0,0 +1,58 @@
+//////////////////////////////////////////////////////////////////////////////////
+// 
+// Create Date: 05/24/2024 03:37 PM
+// Last Update Date: 05/24/2024 09:01 PM
+// Module Name: fifo_vip_scoreboard.sv
+// Author: https://www.linkedin.com/in/wei-yet-ng-065485119/
+// Description: This package contains the FIFO VIP scoreboard.
+// 
+//////////////////////////////////////////////////////////////////////////////////
+
+class fifo_vip_scoreboard extends uvm_scoreboard;
+    `uvm_component_utils(fifo_vip_scoreboard)
+    
+    uvm_analysis_imp_wr #(fifo_vip_seq_item, fifo_vip_scoreboard) wr_imp;
+    uvm_analysis_imp_rd #(fifo_vip_seq_item, fifo_vip_scoreboard) rd_imp;
+    
+    // Simple queue model
+    int fifo_model[$];
+    int errors = 0;
+    
+    function new(string name = "fifo_vip_scoreboard", uvm_component parent = null);
+        super.new(name, parent);
+        wr_imp = new("wr_imp", this);
+        rd_imp = new("rd_imp", this);
+    endfunction
+    
+    function void write_wr(fifo_vip_seq_item item);
+        if (item.op == WRITE && item.success) begin
+            fifo_model.push_back(item.data);
+            `uvm_info("SB", $sformatf("Write: data=0x%0h, queue_size=%0d", item.data, fifo_model.size()), UVM_MEDIUM)
+        end
+    endfunction
+    
+    function void write_rd(fifo_vip_seq_item item);
+        if (item.op == READ && item.success) begin
+            if (fifo_model.size() > 0) begin
+                int expected = fifo_model.pop_front();
+                if (item.read_data == expected) begin
+                    `uvm_info("SB", $sformatf("Read OK: data=0x%0h, queue_size=%0d", item.read_data, fifo_model.size()), UVM_MEDIUM)
+                end else begin
+                    `uvm_error("SB", $sformatf("Data mismatch! Expected:0x%0h Got:0x%0h", expected, item.read_data))
+                    errors++;
+                end
+            end else begin
+                `uvm_error("SB", "Read from empty FIFO model")
+                errors++;
+            end
+        end
+    endfunction
+    
+    function void report_phase(uvm_phase phase);
+        if (errors == 0)
+            `uvm_info("SB", "*** TEST PASSED ***", UVM_LOW)
+        else
+            `uvm_error("SB", $sformatf("*** TEST FAILED - %0d errors ***", errors))
+    endfunction
+
+endclass

Weiyet_RTLStructLib/source/FIFO/vip/uvm/interface/fifo_vip_if.sv

@@ -0,0 +1,38 @@
+//////////////////////////////////////////////////////////////////////////////////
+// 
+// Create Date: 05/24/2024 03:37 PM
+// Last Update Date: 05/24/2024 09:28 PM
+// Module Name: fifo_vip_if
+// Author: https://www.linkedin.com/in/wei-yet-ng-065485119/
+// Description: This package contains the FIFO VIP interface.
+// 
+//////////////////////////////////////////////////////////////////////////////////
+
+
+interface fifo_vip_if(input logic wr_clk, input logic rd_clk);
+
+    // Signals matching your FIFO
+    logic rst;
+    logic [7:0] data_wr;
+    logic wr_en;
+    logic fifo_full;
+    logic [7:0] data_rd;
+    logic rd_en;
+    logic fifo_empty;
+    
+    // Simple clocking blocks
+    clocking wr_cb @(posedge wr_clk);
+        output data_wr, wr_en;
+        input fifo_full;
+    endclocking
+    
+    clocking rd_cb @(posedge rd_clk);
+        output rd_en;
+        input data_rd, fifo_empty;
+    endclocking
+    
+    // Modports
+    modport wr_drv (clocking wr_cb, input rst);
+    modport rd_drv (clocking rd_cb, input rst);
+
+endinterface

Weiyet_RTLStructLib/source/FIFO/vip/uvm/sequences/fifo_vip_base_seq.sv

@@ -0,0 +1,26 @@
+//////////////////////////////////////////////////////////////////////////////////
+// 
+// Create Date: 05/24/2024 03:37 PM
+// Last Update Date: 05/24/2024 09:27 PM
+// Module Name: fifo_vip_base_seq	
+// Author: https://www.linkedin.com/in/wei-yet-ng-065485119/
+// Description: This sequence serves as a base class for FIFO VIP sequences.
+// 
+//////////////////////////////////////////////////////////////////////////////////
+
+class fifo_vip_base_seq extends uvm_sequence #(fifo_vip_seq_item);
+    `uvm_object_utils(fifo_vip_base_seq)
+    
+    fifo_vip_config cfg;
+    
+    function new(string name = "fifo_vip_base_seq");
+        super.new(name);
+    endfunction
+    
+    task pre_body();
+        if (!uvm_config_db#(fifo_vip_config)::get(m_sequencer, "", "fifo_vip_cfg", cfg)) begin
+            `uvm_warning("SEQ", "No config found")
+        end
+    endtask
+
+endclass

Weiyet_RTLStructLib/source/FIFO/vip/uvm/sequences/fifo_vip_read_req_seq.sv

@@ -0,0 +1,37 @@
+//////////////////////////////////////////////////////////////////////////////////
+// 
+// Create Date: 05/24/2024 03:37 PM
+// Last Update Date: 05/24/2024 09:04 PM
+// Module Name: fifo_vip_read_req_seq
+// Author: https://www.linkedin.com/in/wei-yet-ng-065485119/
+// Description: This sequence generates read requests for the FIFO VIP.
+// 
+//////////////////////////////////////////////////////////////////////////////////
+
+class fifo_vip_read_req_seq extends fifo_vip_base_seq;
+    `uvm_object_utils(fifo_vip_read_req_seq)
+    
+    rand int num_reads;
+    
+    constraint num_reads_c {
+        num_reads inside {[1:20]};
+    }
+    
+    function new(string name = "fifo_vip_read_req_seq");
+        super.new(name);
+    endfunction
+    
+    task body();
+        fifo_vip_seq_item item;
+        
+        `uvm_info("RD_SEQ", $sformatf("Starting %0d reads", num_reads), UVM_MEDIUM)
+        
+        repeat(num_reads) begin
+            item = fifo_vip_seq_item::type_id::create("item");
+            start_item(item);
+            assert(item.randomize() with {op == READ;});
+            finish_item(item);
+        end
+    endtask
+
+endclass

Weiyet_RTLStructLib/source/FIFO/vip/uvm/sequences/fifo_vip_write_req_seq.sv

@@ -0,0 +1,38 @@
+//////////////////////////////////////////////////////////////////////////////////
+// 
+// Create Date: 05/24/2024 03:37 PM
+// Last Update Date: 05/24/2024 09:25 PM
+// Module Name: fifo_vip_write_req_seq
+// Author: https://www.linkedin.com/in/wei-yet-ng-065485119/
+// Description: This sequence generates write requests for the FIFO VIP.
+// 
+//////////////////////////////////////////////////////////////////////////////////
+
+
+class fifo_vip_write_req_seq extends fifo_vip_base_seq;
+    `uvm_object_utils(fifo_vip_write_req_seq)
+    
+    rand int num_writes;
+    
+    constraint num_writes_c {
+        num_writes inside {[1:20]};
+    }
+    
+    function new(string name = "fifo_vip_write_req_seq");
+        super.new(name);
+    endfunction
+    
+    task body();
+        fifo_vip_seq_item item;
+        
+        `uvm_info("WR_SEQ", $sformatf("Starting %0d writes", num_writes), UVM_MEDIUM)
+        
+        repeat(num_writes) begin
+            item = fifo_vip_seq_item::type_id::create("item");
+            start_item(item);
+            assert(item.randomize() with {op == WRITE;});
+            finish_item(item);
+        end
+    endtask
+
+endclass

Weiyet_RTLStructLib/source/FIFO/vip/uvm/sim/tb_top.sv

@@ -0,0 +1,70 @@
+//////////////////////////////////////////////////////////////////////////////////
+// 
+// Create Date: 05/24/2024 03:37 PM
+// Last Update Date: 05/24/2024 09:04 PM
+// Module Name: tb_top
+// Author: https://www.linkedin.com/in/wei-yet-ng-065485119/
+// Description: This is the top-level testbench for the FIFO VIP.
+// 
+//////////////////////////////////////////////////////////////////////////////////
+
+
+`timescale 1ns/1ps
+
+module tb_top;
+    import uvm_pkg::*;
+    import fifo_vip_pkg::*;
+    
+    // Clocks
+    logic wr_clk = 0;
+    logic rd_clk = 0;
+    
+    // Clock generation - MODIFY PERIODS AS NEEDED
+    always #10 wr_clk = ~wr_clk;  // 50MHz
+    always #16 rd_clk = ~rd_clk;  // 31.25MHz
+    
+    // Interface
+    fifo_vip_if dut_if(wr_clk, rd_clk);
+    
+    // Reset
+    initial begin
+        dut_if.rst = 1;
+        repeat(5) @(posedge wr_clk);
+        dut_if.rst = 0;
+    end
+    
+    // DUT instantiation - MODIFY FOR YOUR FIFO
+    fifo #(
+        .DEPTH(12),
+        .DATA_WIDTH(8),
+        .ASYNC(1),
+        .RD_BUFFER(1)
+    ) dut (
+        .rd_clk(rd_clk),
+        .wr_clk(wr_clk),
+        .rst(dut_if.rst),
+        .data_wr(dut_if.data_wr),
+        .wr_en(dut_if.wr_en),
+        .fifo_full(dut_if.fifo_full),
+        .data_rd(dut_if.data_rd),
+        .rd_en(dut_if.rd_en),
+        .fifo_empty(dut_if.fifo_empty)
+    );
+    
+    // UVM testbench
+    initial begin
+        uvm_config_db#(virtual fifo_vip_if)::set(null, "*", "fifo_vip_vif", dut_if);
+        
+        $dumpfile("waves.vcd");
+        $dumpvars(0, tb_top);
+        
+        run_test();
+    end
+    
+    // Timeout
+    initial begin
+        #50us;
+        $finish;
+    end
+
+endmodule

Weiyet_RTLStructLib/source/FIFO/vip/uvm/sim/tests/fifo_vip_base_test.sv

@@ -0,0 +1,42 @@
+//////////////////////////////////////////////////////////////////////////////////
+// 
+// Create Date: 05/24/2024 03:37 PM
+// Last Update Date: 05/24/2024 10:04 PM
+// Module Name: fifo_vip_base_test
+// Author: https://www.linkedin.com/in/wei-yet-ng-065485119/
+// Description: This package contains the base test for the FIFO VIP.
+// 
+//////////////////////////////////////////////////////////////////////////////////
+
+class base_test extends uvm_test;
+    `uvm_component_utils(base_test)
+    
+    fifo_vip_env env;
+    fifo_vip_config cfg;
+    
+    function new(string name = "base_test", uvm_component parent = null);
+        super.new(name, parent);
+    endfunction
+    
+    function void build_phase(uvm_phase phase);
+        super.build_phase(phase);
+        
+        // Create config - MODIFY FOR YOUR FIFO
+        cfg = fifo_vip_config::type_id::create("cfg");
+        cfg.DEPTH = 12;        // Change this
+        cfg.DATA_WIDTH = 8;    // Change this
+        cfg.ASYNC = 1;         // Change this
+        cfg.RD_BUFFER = 1;     // Change this
+        
+        // Set config in database with better field name
+        uvm_config_db#(fifo_vip_config)::set(this, "*", "fifo_vip_cfg", cfg);
+        
+        env = fifo_vip_env::type_id::create("env", this);
+    endfunction
+    
+    function void end_of_elaboration_phase(uvm_phase phase);
+        cfg.print_config();
+        uvm_top.print_topology();
+    endfunction
+
+endclass

Weiyet_RTLStructLib/source/FIFO/vip/uvm/sim/tests/fifo_vip_simple_test.sv

@@ -0,0 +1,40 @@
+//////////////////////////////////////////////////////////////////////////////////
+// 
+// Create Date: 05/24/2024 03:37 PM
+// Last Update Date: 05/24/2024 10:04 PM
+// Module Name: fifo_vip_base_test
+// Author: https://www.linkedin.com/in/wei-yet-ng-065485119/
+// Description: This package contains the base test for the FIFO VIP.
+// 
+//////////////////////////////////////////////////////////////////////////////////
+    
+class simple_test extends base_test;
+    `uvm_component_utils(simple_test)
+    
+    function new(string name = "simple_test", uvm_component parent = null);
+        super.new(name, parent);
+    endfunction
+    
+    task run_phase(uvm_phase phase);
+        fifo_vip_write_req_seq wr_seq;
+        fifo_vip_read_req_seq rd_seq;
+        
+        phase.raise_objection(this);
+        
+        // Write some data
+        wr_seq = fifo_vip_write_req_seq::type_id::create("wr_seq");
+        wr_seq.num_writes = 8;
+        wr_seq.start(env.get_wr_sequencer());
+        
+        #200ns;
+        
+        // Read it back
+        rd_seq = fifo_vip_read_req_seq::type_id::create("rd_seq");
+        rd_seq.num_reads = 8;
+        rd_seq.start(env.get_rd_sequencer());
+        
+        #200ns;
+        phase.drop_objection(this);
+    endtask
+
+endclass

Weiyet_RTLStructLib/source/Hash_Table/vip/pyuvm/agent/__init__.py

@@ -0,0 +1,9 @@
+"""
+Hash Table VIP Agent Package
+"""
+from .ht_vip_driver import HtVipDriver
+from .ht_vip_monitor import HtVipMonitor
+from .ht_vip_sequencer import HtVipSequencer
+from .ht_vip_agent import HtVipAgent
+
+__all__ = ['HtVipDriver', 'HtVipMonitor', 'HtVipSequencer', 'HtVipAgent']

Weiyet_RTLStructLib/source/Hash_Table/vip/pyuvm/agent/ht_vip_agent.py

@@ -0,0 +1,28 @@
+"""Hash Table VIP Agent"""
+from pyuvm import *
+from .ht_vip_driver import HtVipDriver
+from .ht_vip_monitor import HtVipMonitor
+from .ht_vip_sequencer import HtVipSequencer
+
+class HtVipAgent(uvm_agent):
+    def __init__(self, name, parent):
+        super().__init__(name, parent)
+        self.driver = None
+        self.monitor = None
+        self.sequencer = None
+        self.ap = None
+
+    def build_phase(self):
+        super().build_phase()
+        self.monitor = HtVipMonitor("monitor", self)
+        cfg = ConfigDB().get(self, "", "ht_vip_cfg")
+        if cfg and cfg.is_active:
+            self.driver = HtVipDriver("driver", self)
+            self.sequencer = HtVipSequencer("sequencer", self)
+
+    def connect_phase(self):
+        super().connect_phase()
+        self.ap = self.monitor.ap
+        cfg = ConfigDB().get(self, "", "ht_vip_cfg")
+        if cfg and cfg.is_active and self.driver and self.sequencer:
+            self.driver.seq_item_port.connect(self.sequencer.seq_item_export)

Weiyet_RTLStructLib/source/Hash_Table/vip/pyuvm/agent/ht_vip_driver.py

@@ -0,0 +1,48 @@
+"""Hash Table VIP Driver"""
+from pyuvm import *
+import cocotb
+from cocotb.triggers import RisingEdge
+from ..common.ht_vip_seq_item import HtVipSeqItem
+from ..common.ht_vip_types import HtOp
+
+class HtVipDriver(uvm_driver):
+    def __init__(self, name, parent):
+        super().__init__(name, parent)
+        self.dut = None
+        self.cfg = None
+
+    def build_phase(self):
+        super().build_phase()
+        self.cfg = ConfigDB().get(self, "", "ht_vip_cfg")
+
+    async def run_phase(self):
+        self.dut = ConfigDB().get(self, "", "ht_vip_dut")
+        self.dut.op_sel.value = 3
+        self.dut.op_en.value = 0
+        self.dut.key_in.value = 0
+        self.dut.value_in.value = 0
+
+        while True:
+            item = await self.seq_item_port.get_next_item()
+            await self.drive_item(item)
+            self.seq_item_port.item_done()
+
+    async def drive_item(self, item):
+        await RisingEdge(self.dut.clk)
+        self.dut.op_sel.value = item.op.value
+        self.dut.op_en.value = 1
+        self.dut.key_in.value = item.key
+        self.dut.value_in.value = item.value
+
+        await RisingEdge(self.dut.clk)
+        self.dut.op_en.value = 0
+
+        while not self.dut.op_done.value:
+            await RisingEdge(self.dut.clk)
+
+        item.result_value = int(self.dut.value_out.value)
+        item.op_done = bool(self.dut.op_done.value)
+        item.op_error = bool(self.dut.op_error.value)
+        item.collision_count = int(self.dut.collision_count.value)
+
+        await RisingEdge(self.dut.clk)

Weiyet_RTLStructLib/source/Hash_Table/vip/pyuvm/common/__init__.py

@@ -0,0 +1,14 @@
+"""
+Hash Table VIP Common Package
+Contains configuration, types, and sequence item definitions
+"""
+
+from .ht_vip_types import HtOp
+from .ht_vip_config import HtVipConfig
+from .ht_vip_seq_item import HtVipSeqItem
+
+__all__ = [
+    'HtOp',
+    'HtVipConfig',
+    'HtVipSeqItem',
+]

Weiyet_RTLStructLib/source/Hash_Table/vip/pyuvm/common/ht_vip_config.py

@@ -0,0 +1,37 @@
+"""
+Hash Table VIP Configuration
+Create Date: 01/05/2026
+
+Configuration class for Hash Table VIP
+"""
+
+from pyuvm import *
+
+
+class HtVipConfig(uvm_object):
+    """Configuration object for Hash Table VIP"""
+
+    def __init__(self, name="ht_vip_config"):
+        super().__init__(name)
+
+        # DUT parameters
+        self.KEY_WIDTH = 32
+        self.VALUE_WIDTH = 32
+        self.TOTAL_INDEX = 8
+        self.CHAINING_SIZE = 4
+        self.COLLISION_METHOD = "MULTI_STAGE_CHAINING"
+        self.HASH_ALGORITHM = "MODULUS"
+
+        # VIP configuration
+        self.has_agent = True
+        self.enable_scoreboard = True
+        self.is_active = True
+
+    def do_print(self, printer=None):
+        """Print configuration"""
+        self.logger.info(f"KEY_WIDTH: {self.KEY_WIDTH}")
+        self.logger.info(f"VALUE_WIDTH: {self.VALUE_WIDTH}")
+        self.logger.info(f"TOTAL_INDEX: {self.TOTAL_INDEX}")
+        self.logger.info(f"CHAINING_SIZE: {self.CHAINING_SIZE}")
+        self.logger.info(f"COLLISION_METHOD: {self.COLLISION_METHOD}")
+        self.logger.info(f"HASH_ALGORITHM: {self.HASH_ALGORITHM}")

Weiyet_RTLStructLib/source/Hash_Table/vip/pyuvm/common/ht_vip_seq_item.py

@@ -0,0 +1,62 @@
+"""
+Hash Table VIP Sequence Item
+Create Date: 01/05/2026
+
+Transaction item for Hash Table operations (key-value pairs)
+"""
+
+from pyuvm import *
+import random
+from .ht_vip_types import HtOp
+
+
+class HtVipSeqItem(uvm_sequence_item):
+    """Sequence item for Hash Table transactions"""
+
+    def __init__(self, name="ht_vip_seq_item"):
+        super().__init__(name)
+
+        # Transaction fields (key-value pairs)
+        self.op = HtOp.INSERT
+        self.key = 0
+        self.value = 0
+
+        # Response fields
+        self.result_value = 0
+        self.op_done = False
+        self.op_error = False
+        self.collision_count = 0
+
+        # Config reference
+        self.cfg = None
+
+    def randomize_with_op(self, op):
+        """Randomize item with specific operation"""
+        self.op = op
+
+        if self.cfg:
+            key_max = (1 << self.cfg.KEY_WIDTH) - 1
+            value_max = (1 << self.cfg.VALUE_WIDTH) - 1
+        else:
+            key_max = 0xFFFFFFFF
+            value_max = 0xFFFFFFFF
+
+        # Key should not be 0
+        self.key = random.randint(1, key_max)
+        self.value = random.randint(0, value_max)
+
+    def randomize(self):
+        """Randomize all fields with distribution"""
+        # Random operation with distribution
+        op_choice = random.choices(
+            [HtOp.INSERT, HtOp.DELETE, HtOp.SEARCH],
+            weights=[40, 30, 30]
+        )[0]
+
+        self.randomize_with_op(op_choice)
+
+    def convert2string(self):
+        """Convert to string for printing"""
+        return (f"Op:{self.op.name} Key:0x{self.key:x} Value:0x{self.value:x} "
+                f"Result:0x{self.result_value:x} Done:{self.op_done} "
+                f"Error:{self.op_error} Collisions:{self.collision_count}")

Weiyet_RTLStructLib/source/Hash_Table/vip/pyuvm/common/ht_vip_types.py

@@ -0,0 +1,16 @@
+"""
+Hash Table VIP Types
+Create Date: 01/05/2026
+
+Enumerations and types for Hash Table VIP
+"""
+
+from enum import Enum
+
+
+class HtOp(Enum):
+    """Hash Table operation types matching DUT operations"""
+    INSERT = 0  # Insert key-value pair
+    DELETE = 1  # Delete by key
+    SEARCH = 2  # Search by key
+    IDLE = 3    # No operation

Weiyet_RTLStructLib/source/Hash_Table/vip/pyuvm/env/__init__.py

@@ -0,0 +1,4 @@
+"""Hash Table VIP Environment Package"""
+from .ht_vip_scoreboard import HtVipScoreboard
+from .ht_vip_env import HtVipEnv
+__all__ = ['HtVipScoreboard', 'HtVipEnv']

Weiyet_RTLStructLib/source/Hash_Table/vip/pyuvm/env/ht_vip_env.py

@@ -0,0 +1,28 @@
+"""Hash Table VIP Environment"""
+from pyuvm import *
+from ..agent.ht_vip_agent import HtVipAgent
+from .ht_vip_scoreboard import HtVipScoreboard
+
+class HtVipEnv(uvm_env):
+    def __init__(self, name, parent):
+        super().__init__(name, parent)
+        self.cfg = None
+        self.agent = None
+        self.sb = None
+
+    def build_phase(self):
+        super().build_phase()
+        self.cfg = ConfigDB().get(self, "", "ht_vip_cfg")
+        ConfigDB().set(self, "*", "ht_vip_cfg", self.cfg)
+        if self.cfg.has_agent:
+            self.agent = HtVipAgent("agent", self)
+        if self.cfg.enable_scoreboard:
+            self.sb = HtVipScoreboard("sb", self)
+
+    def connect_phase(self):
+        super().connect_phase()
+        if self.cfg.enable_scoreboard and self.sb and self.agent:
+            self.agent.ap.connect(self.sb.imp)
+
+    def get_sequencer(self):
+        return self.agent.sequencer if self.agent else None

Weiyet_RTLStructLib/source/Hash_Table/vip/pyuvm/env/ht_vip_scoreboard.py

@@ -0,0 +1,42 @@
+"""Hash Table VIP Scoreboard - tracks key-value pairs"""
+from pyuvm import *
+from ..common.ht_vip_types import HtOp
+
+class HtVipScoreboard(uvm_scoreboard):
+    def __init__(self, name, parent):
+        super().__init__(name, parent)
+        self.imp = uvm_analysis_export("imp", self)
+        self.hash_model = {}  # Python dict as reference model
+        self.error_count = 0
+
+    def connect_phase(self):
+        super().connect_phase()
+        self.imp.connect(self)
+
+    def write(self, item):
+        if item.op == HtOp.INSERT:
+            if not item.op_error:
+                self.hash_model[item.key] = item.value
+                self.logger.info(f"INSERT key=0x{item.key:x} value=0x{item.value:x}")
+        elif item.op == HtOp.DELETE:
+            if not item.op_error:
+                if item.key in self.hash_model:
+                    del self.hash_model[item.key]
+                    self.logger.info(f"DELETE key=0x{item.key:x}")
+        elif item.op == HtOp.SEARCH:
+            if item.key in self.hash_model:
+                if item.result_value != self.hash_model[item.key]:
+                    self.logger.error(f"SEARCH mismatch! Expected=0x{self.hash_model[item.key]:x} Actual=0x{item.result_value:x}")
+                    self.error_count += 1
+                else:
+                    self.logger.info(f"SEARCH key=0x{item.key:x} MATCH")
+
+    def report_phase(self):
+        super().report_phase()
+        self.logger.info("="*50)
+        self.logger.info(f"Hash Table Size: {len(self.hash_model)}")
+        self.logger.info(f"Error Count: {self.error_count}")
+        if self.error_count > 0:
+            self.logger.error(f"Test FAILED with {self.error_count} errors")
+        else:
+            self.logger.info("Test PASSED")

Weiyet_RTLStructLib/source/Hash_Table/vip/pyuvm/sequences/__init__.py

@@ -0,0 +1,6 @@
+"""Hash Table VIP Sequences Package"""
+from .ht_vip_base_seq import HtVipBaseSeq
+from .ht_vip_insert_seq import HtVipInsertSeq
+from .ht_vip_search_seq import HtVipSearchSeq
+from .ht_vip_delete_seq import HtVipDeleteSeq
+__all__ = ['HtVipBaseSeq', 'HtVipInsertSeq', 'HtVipSearchSeq', 'HtVipDeleteSeq']

Weiyet_RTLStructLib/source/Hash_Table/vip/pyuvm/sequences/ht_vip_base_seq.py

@@ -0,0 +1,14 @@
+"""Hash Table VIP Base Sequence"""
+from pyuvm import *
+from ..common.ht_vip_seq_item import HtVipSeqItem
+
+class HtVipBaseSeq(uvm_sequence):
+    def __init__(self, name):
+        super().__init__(name)
+        self.cfg = None
+
+    async def pre_body(self):
+        self.cfg = ConfigDB().get(None, "", "ht_vip_cfg")
+
+    async def body(self):
+        pass