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Weiyet_RTLStructLib/source/.gitignore

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+# Ignore simulation files
+*.log
+*.vcd
+*.sim
+XilinxUnisimLibrary
+*netlist.v
+__pycache__
+iverilog_dump.v
+results.xml
+sim_build

Weiyet_RTLStructLib/source/Doubly_Linked_List/README.md

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+# Doubly Linked List
+
+A configurable hardware implementation of a doubly linked list data structure in Verilog. The module supports bidirectional traversal with both forward and backward pointers, providing efficient insertion, deletion, and reading operations at specific addresses or indices.
+
+## Features
+
+- Configurable data width and maximum node count
+- Bidirectional traversal support
+- Multiple insertion and deletion operations
+- Hardware-based node management
+- Full status monitoring (full, empty, length)
+- Fault detection
+- Head and tail pointer tracking
+- Synchronous operation with start/done handshaking
+
+## Parameters
+
+| Parameter    | Description                                      | Default |
+|-------------|--------------------------------------------------|---------|
+| DATA_WIDTH  | Width of data stored in each node                | 8       |
+| MAX_NODE    | Maximum number of nodes supported                | 8       |
+
+## Interface Signals
+
+| Signal           | Direction | Width         | Description                                    |
+|-----------------|-----------|---------------|------------------------------------------------|
+| clk             | Input     | 1            | System clock                                   |
+| rst             | Input     | 1            | Active high reset                              |
+| data_in         | Input     | DATA_WIDTH   | Input data for insertion                      |
+| addr_in         | Input     | ADDR_WIDTH   | Target address/index for operations           |
+| op              | Input     | 3            | Operation code                                |
+| op_start        | Input     | 1            | Start signal for operation                    |
+| op_done         | Output    | 1            | Operation completion signal                   |
+| data_out        | Output    | DATA_WIDTH   | Output data from read operations             |
+| pre_node_addr   | Output    | ADDR_WIDTH   | Address of previous node in list             |
+| next_node_addr  | Output    | ADDR_WIDTH   | Address of next node in list                 |
+| length          | Output    | ADDR_WIDTH   | Current number of nodes in list              |
+| head            | Output    | ADDR_WIDTH   | Address of first node                        |
+| tail            | Output    | ADDR_WIDTH   | Address of last node                         |
+| full            | Output    | 1            | List full indicator                          |
+| empty           | Output    | 1            | List empty indicator                         |
+| fault           | Output    | 1            | Error indicator                              |
+
+## Supported Operations
+
+| Op Code | Operation         | Description                                             |
+|---------|------------------|---------------------------------------------------------|
+| 0       | Read_Addr        | Read data at specified address                          |
+| 1       | Insert_Addr      | Insert new node at specified address                    |
+| 2       | Delete_Value     | Delete first occurrence of specified value              |
+| 3       | Delete_Addr      | Delete node at specified address                        |
+| 5       | Insert_Index     | Insert new node at specified index                      |
+| 7       | Delete_Index     | Delete node at specified index                          |
+
+## State Machine
+
+The module implements a FSM with the following states:
+
+1. **IDLE (3'b000)**
+   - Initial state, waits for operation start
+   - Validates operation parameters
+   - Handles direct head/tail operations
+
+2. **FIND_ADDR (3'b001)**
+   - Traverses list to find target address
+   - Used for address-based operations
+
+3. **FIND_VALUE (3'b010)**
+   - Traverses list to find target value
+   - Used for value-based deletion
+
+4. **FIND_INDEX (3'b110)**
+   - Traverses list to find target index
+   - Supports both ascending and descending search
+
+5. **INSERT_STG1 (3'b011)**
+   - First stage of node insertion
+   - Updates bidirectional links
+
+6. **EXECUTE (3'b100)**
+   - Completes operation
+   - Updates status signals
+
+7. **FAULT (3'b101)**
+   - Handles error conditions
+
+## Memory Organization
+
+The implementation uses three separate memory arrays:
+1. Data storage (`node_data`)
+2. Forward pointers (`node_next_node_addr`)
+3. Backward pointers (`node_pre_node_addr`)
+
+This organization allows for:
+- Independent access to data and pointers
+- Efficient pointer updates
+- Parallel validity checking
+
+## Usage Example
+
+```verilog
+// Instantiate a doubly linked list with 16 nodes and 32-bit data
+doubly_linked_list #(
+    .DATA_WIDTH(32),
+    .MAX_NODE(16)
+) list_inst (
+    .clk(system_clock),
+    .rst(reset),
+    .data_in(input_data),
+    .addr_in(target_addr),
+    .op(operation_code),
+    .op_start(start_signal),
+    .op_done(done_signal),
+    .data_out(output_data),
+    .pre_node_addr(prev_addr),
+    .next_node_addr(next_addr),
+    .length(list_length),
+    .head(head_addr),
+    .tail(tail_addr),
+    .full(list_full),
+    .empty(list_empty),
+    .fault(error_signal)
+);
+```
+## Reset Behavior
+
+On assertion of reset:
+- All nodes are invalidated
+- Head and tail pointers set to NULL
+- Length cleared to zero
+- All node data cleared
+- All status signals deasserted
+
+## Implementation Notes
+
+1. **Memory Organization**:
+   - Next node pointers stored separately
+   - Valid bits for node tracking
+
+2. **Address Handling**:
+   - NULL address = MAX_NODE
+   - Valid addresses: 0 to (MAX_NODE-1)
+
+3. **Error Conditions**:
+   - List full during insertion
+   - List empty during deletion/read
+   - Invalid address/index
+   - Address overflow
+
+## Limitations
+
+- Fixed maximum size defined by MAX_NODE
+- Sequential search for operations
+- Single operation at a time
+- No concurrent access support
+

Weiyet_RTLStructLib/source/Dual_Edge_FF/README.md

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+# Dual Edge Flip Flop
+## Overview
+This Verilog module implements a dual-edge triggered flip-flop that can capture data on both the positive and negative edges of the clock signal. This design effectively doubles the data throughput rate compared to traditional single-edge flip-flops by utilizing both clock transitions for data latching operations.
+
+## Parameters
+| Parameter    | Description                           | Default |
+|-------------|---------------------------------------|---------|
+| DATA_WIDTH  | Width of data bus in bits             | 8       |
+| RESET_VALUE | Reset value of flops                  | 0       |
+
+## Port Descriptions
+### Input Ports
+| Port               | Width       | Description                                    |
+|-------------------|-------------|------------------------------------------------|
+| clk               | 1           | System clock signal                            |
+| rst_n             | 1           | Active-low asynchronous reset signal           |
+| data_in           | DATA_WIDTH  | Input data to be latched                       |
+| pos_edge_latch_en | DATA_WIDTH  | Per-bit latch enable for positive clock edge  |
+| neg_edge_latch_en | DATA_WIDTH  | Per-bit latch enable for negative clock edge  |
+
+### Output Ports
+| Port     | Width      | Description                    |
+|----------|------------|--------------------------------|
+| data_out | DATA_WIDTH | Latched output data           |
+
+
+## Usage Example
+Below shows a simple usage of a counter that increments on both edges of the clock.
+```verilog
+always @ (*) begin
+  if (data_out <= {(DATA_WIDTH){1'b1}}) input_data <= data_out + 1;
+  else input_data <= data_out;
+end
+
+dual_edge_ff #(
+    .DATA_WIDTH(16),
+    .RESET_VALUE(16'h0000)
+) dual_ff_inst (
+    .clk(system_clk),
+    .rst_n(system_rst_n),
+    .data_in(input_data),
+    .pos_edge_latch_en(16'hFFFF),  // Enable all bits on positive edge
+    .neg_edge_latch_en(16'hFFFF),  // Enable all bits on negative edge
+    .data_out(output_data)
+);
+```

Weiyet_RTLStructLib/source/Dual_Edge_FF/src/dual_edge_ff.sv

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+`timescale 1ns / 1ps
+//////////////////////////////////////////////////////////////////////////////////
+// Create Date: 30/07/2025 07:22 PM
+// Created By: https://www.linkedin.com/in/wei-yet-ng-065485119/
+// Last Update: 03/08/2025 02:30 PM
+// Last Updated By: https://www.linkedin.com/in/wei-yet-ng-065485119/
+// Module Name: Dual Edge Flip Flop 
+// Description: Synthesiazble structure that can latch data corresponding to dual edge of clock to achive double input and output rate. 
+// Additional Comments: .
+// 
+//////////////////////////////////////////////////////////////////////////////////
+
+
+module dual_edge_ff #(
+    parameter DATA_WIDTH = 8,   
+    parameter RESET_VALUE = 0 
+    )(
+       input  wire clk,
+       input  wire rst_n,
+       input  wire [DATA_WIDTH-1:0] data_in,
+       input  wire [DATA_WIDTH-1:0] pos_edge_latch_en,
+       input  wire [DATA_WIDTH-1:0] neg_edge_latch_en,
+       output wire [DATA_WIDTH-1:0] data_out
+    );
+    
+    reg [DATA_WIDTH-1:0] d_in_pos;
+    reg [DATA_WIDTH-1:0] q_out_pos;
+    reg [DATA_WIDTH-1:0] d_in_neg;
+    reg [DATA_WIDTH-1:0] q_out_neg;
+    
+
+    assign clk_n = ~clk; // Invert clock for negative edge latching
+
+    genvar i;   
+
+    generate 
+    for(i=0;i<DATA_WIDTH;i=i+1) begin
+    
+        assign d_in_pos[i] = data_in[i] ^ q_out_neg[i];
+        always @ (posedge clk or negedge rst_n) begin
+            if(!rst_n) 
+                q_out_pos[i] <= RESET_VALUE[i];
+            else if(pos_edge_latch_en[i])
+                q_out_pos[i] <= d_in_pos[i];
+        end
+        
+        assign d_in_neg[i] = (data_in[i] ^ q_out_pos[i]);      
+        always @ (posedge clk_n or negedge rst_n) begin
+            if(!rst_n)
+                q_out_neg[i] <= 1'b0;
+            else if(neg_edge_latch_en[i])
+                q_out_neg[i] <= d_in_neg[i];
+        end   
+        
+        assign data_out[i] = q_out_pos[i] ^ q_out_neg[i];
+    end 
+    endgenerate
+    
+
+
+endmodule

Weiyet_RTLStructLib/source/Dual_Edge_FF/src/rtl_list.f

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+dual_edge_ff.sv

Weiyet_RTLStructLib/source/Dual_Edge_FF/tb/cocotb/Makefile

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+SIM ?= icarus
+TOPLEVEL_LANG ?= verilog
+WAVES ?= 1 #set 1 to enable waveform dump. 
+
+PWD=$(shell pwd)
+
+#export PYTHONPATH := $(PWD)/../model:$(PYTHONPATH)
+
+SRC_DIR = ../../src
+VERILOG_SOURCES = $(addprefix $(SRC_DIR)/, $(shell cat ../../src/rtl_list.f))
+
+# DUT Top
+TOPLEVEL = dual_edge_ff
+# top python file name
+MODULE   = tb
+
+#use , separtor to run multiple TESTCASE, by default all @cocotb.test will be run
+TESTCASE = direct_test
+
+COMPILE_ARGS = -Pdual_edge_ff.DATA_WIDTH=8 # DUT parameter #"-p" (parameter) iverilog command flags
+COMPILE_ARGS += -Pdual_edge_ff.RESET_VALUE=0 # DUT parameter #"-p" (parameter) iverilog command flags
+#run make clean before running with new parameter.
+
+#Set RANDOM_SEED number
+#PLUSARGS = +seed=1716033254
+COCOTB_HDL_TIMEUNIT = 1ns
+COCOTB_HDL_TIMEPRECISION = 1ps
+
+ifeq ($(SIM), icarus) 
+   $(shell echo 'module iverilog_dump();' > iverilog_dump.v)
+   $(shell echo 'initial begin' >> iverilog_dump.v)
+   $(shell echo '    $$dumpfile("$(TOPLEVEL).vcd");' >> iverilog_dump.v)
+   $(shell echo '    $$dumpvars(0, $(TOPLEVEL));' >> iverilog_dump.v)
+   $(shell echo 'end' >> iverilog_dump.v)
+   $(shell echo 'endmodule' >> iverilog_dump.v)
+   VERILOG_SOURCES += $(PWD)/iverilog_dump.v
+   COMPILE_ARGS += -s iverilog_dump  
+endif
+
+include $(shell cocotb-config --makefiles)/Makefile.sim
+
+

Weiyet_RTLStructLib/source/Dual_Edge_FF/tb/cocotb/tb.py

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+import random
+#import asyncio
+import math
+import cocotb
+from cocotb.triggers import Timer, RisingEdge, FallingEdge, ReadOnly
+from cocotb.clock import Clock
+from cocotb_bus.drivers import BusDriver
+from cocotb_bus.monitors import BusMonitor
+from cocotb.binary import BinaryValue
+
+#BIN string
+#BinaryValue(dut.data_wr.value, n_bits=8) ; BinaryValue.integar ; BinaryValue.hex ; BinaryValue.binstr; BinaryValue.signed_integer ; can represent x,z
+
+DUT_DATA_WIDTH = 8 # DUT paramter
+DUT_RESET_VALUE = 0 # DUT parameter
+TB_CLK_PERIOD = 30 # TB clk generator
+TB_SIM_TIMEOUT = 30 # TB sim timeout 30ms
+TB_TEST_WEIGHT = 1
+
+err_cnt = 0
+
+#    dual_edge_ff #(
+#         .DATA_WIDTH(DUT_DATA_WIDTH),   
+#         .RESET_VALUE(DUT_RESET_VALUE) 
+#     ) DUT (
+#        /*input  wire                  */.clk(clk),
+#        /*input  wire                  */.rst_n(rst_n),
+#        /*input  wire [DATA_WIDTH-1:0] */.data_in(data_in),
+#        /*input  wire [DATA_WIDTH-1:0] */.pos_edge_latch_en(pos_edge_latch_en),
+#        /*input  wire [DATA_WIDTH-1:0] */.neg_edge_latch_en(neg_edge_latch_en),
+#        /*output wire [DATA_WIDTH-1:0] */.data_out(data_out)
+#     );
+
+async def dut_init(dut):
+    global DUT_DATA_WIDTH  # DUT parameter
+    global DUT_RESET_VALUE # DUT parameter
+    DUT_DATA_WIDTH = dut.DATA_WIDTH.value
+    DUT_RESET_VALUE = dut.RESET_VALUE.value
+    await cocotb.start(Clock(dut.clk, TB_CLK_PERIOD, units="ns").start())
+    dut.data_in.value = 0
+    dut.pos_edge_latch_en.value = 0
+    dut.neg_edge_latch_en.value = 0
+    dut.rst_n.value = 0
+    await(Timer(100,'ns'))
+    dut.rst_n.value = 1
+    await(Timer(100,'ns'))
+    
+
+@cocotb.test()
+async def direct_test(dut):
+    global err_cnt
+    await dut_init(dut)
+    cocotb.log.info("SEED NUMBER = %d",cocotb.RANDOM_SEED)
+
+    for j in range(TB_TEST_WEIGHT):
+        for i in range(20):
+            k = random.randint(0, 3)
+            match k:
+                case 0: # positive edge only 
+                    input_data = random.randint(0, 2**DUT_DATA_WIDTH)
+                    await FallingEdge(dut.clk)
+                    await Timer(1, units='ns')
+                    dut.data_in.value = input_data
+                    dut.pos_edge_latch_en.value = 2**DUT_DATA_WIDTH - 1
+                    await RisingEdge(dut.clk)
+                    await(Timer(1, units='ns'))
+                    if(dut.data_out.value != input_data):
+                        cocotb.log.error("Data out is incorrect at posedge, EXP: %0d, ACT: %0d", input_data, dut.data_out.value)
+                        err_cnt += 1
+                    else:
+                        cocotb.log.info("Data out is correct at posedge with value %0d", dut.data_out.value)
+                    
+                    dut.data_in.value = input_data + 1
+                    await FallingEdge(dut.clk)
+                    await(Timer(1, units='ns'))
+                    if(dut.data_out.value != input_data):
+                        cocotb.log.error("Data out is incorrect, should not be updated at negedge, EXP: %0d, ACT: %0d", input_data + 1, dut.data_out.value)
+                        err_cnt += 1
+                    dut.pos_edge_latch_en.value = 0
+                case 1: # negative edge only
+                    input_data = random.randint(0, 2**DUT_DATA_WIDTH)
+                    await RisingEdge(dut.clk)
+                    await Timer(1, units='ns')
+                    dut.data_in.value = input_data
+                    dut.neg_edge_latch_en.value = 2**DUT_DATA_WIDTH - 1
+                    await FallingEdge(dut.clk)
+                    await(Timer(1, units='ns'))
+                    if(dut.data_out.value != input_data):
+                        cocotb.log.error("Data out is incorrect at negedge, EXP: %0d, ACT: %0d", input_data, dut.data_out.value)
+                        err_cnt += 1
+                    else:
+                        cocotb.log.info("Data out is correct at negedge with value %0d", dut.data_out.value)
+
+                    dut.data_in.value = input_data + 1
+                    await RisingEdge(dut.clk)
+                    await(Timer(1, units='ns'))
+                    if(dut.data_out.value != input_data):
+                        cocotb.log.error("Data out is incorrect, should not be updated at posedge, EXP: %0d, ACT: %0d", input_data + 1, dut.data_out.value)
+                        err_cnt += 1
+                    dut.neg_edge_latch_en.value = 0
+                
+                case 2: # both edges
+                    input_data = random.randint(0, 2**DUT_DATA_WIDTH)
+                    await FallingEdge(dut.clk)
+                    await Timer(1, units='ns')
+                    dut.data_in.value = input_data
+                    dut.pos_edge_latch_en.value = 2**DUT_DATA_WIDTH - 1
+                    dut.neg_edge_latch_en.value = 2**DUT_DATA_WIDTH - 1
+                    await RisingEdge(dut.clk)
+                    await(Timer(1, units='ns'))
+                    if(dut.data_out.value != input_data):
+                        cocotb.log.error("Data out is incorrect at posedge, EXP: %0d, ACT: %0d", input_data, dut.data_out.value)
+                        err_cnt += 1
+                    else:
+                        cocotb.log.info("Data out is correct at posedge with value %0d", dut.data_out.value)
+
+                    input_data = random.randint(0, 2**DUT_DATA_WIDTH)
+                    dut.data_in.value = input_data 
+                    await FallingEdge(dut.clk)
+                    await(Timer(1, units='ns'))
+                    if(dut.data_out.value != input_data):
+                        cocotb.log.error("Data out is incorrect at negedge, EXP: %0d, ACT: %0d", input_data, dut.data_out.value)
+                        err_cnt += 1
+                    else:
+                        cocotb.log.info("Data out is correct at negedge with value %0d", dut.data_out.value)
+
+                    dut.pos_edge_latch_en.value = 0
+                    dut.neg_edge_latch_en.value = 0
+    
+    if (err_cnt > 0):
+        cocotb.log.error("Errors count = %d",err_cnt)
+        #cocotb.result.test_fail()
+        #assert False, f"Test failed with {err_cnt} errors"
+        raise cocotb.result.TestFailure(f"Test failed with {err_cnt} errors")

Weiyet_RTLStructLib/source/Dual_Edge_FF/tb/sv/Makefile

@@ -0,0 +1,48 @@
+
+.PHONY: sim gen_sim synth netlist_sim gen_netlist_sim clean 
+
+DUT ?= list
+SRC_DIR = ../../src
+SIM_OPTS ?= $(addprefix $(SRC_DIR)/, $(shell cat ../../src/rtl_list.f))
+SEED ?= $$(shuf -i 1-10000 -n 1)
+
+# DUT parameter #"-P" iverilog command flags
+COMPILE_ARGS ?= -P DUT_DATA_WIDTH=8 
+COMPILE_ARGS += -P DUT_RESET_VALUE=0
+COMPILE_ARGS += -P TB_CLK_PERIOD=100
+COMPILE_ARGS += -P TB_TEST_WEIGHT=1 
+COMPILE_ARGS += -P TB_SIM_TIMEOUT=30 #//ms.
+
+XILINX_LIB_URL ?= https://github.com/Xilinx/XilinxUnisimLibrary.git
+XILINX_LIB_DIR ?= XilinxUnisimLibrary/verilog/src
+
+sim: gen_sim 
+	./${DUT}.sim +VCDFILE=sim.vcd +VCDLEVEL=0 +SEED=${SEED} | tee sim.log
+
+gen_sim: tb.sv ${SIM_OPTS}  # to generate executable file by using iverilator  
+	iverilog -g2012 -s tb ${COMPILE_ARGS} -o ${DUT}.sim $^
+
+synth: ${SIM_OPTS}
+	yosys -p synth_xilinx ${SIM_OPTS} -L synth.log -o ${DUT}.netlist.v
+    #timeout
+
+netlist_sim: gen_netlist_sim
+	./${DUT}.netlist.sim +VCDFILE=netlist_sim.vcd +VCDLEVEL=0 +SEED=${SEED} | tee netlist_sim.log
+
+gen_netlist_sim: tb.sv ${DUT}.netlist.v | ${XILINX_LIBS_DIR}/.git
+	iverilog -g2012 -s tb -y ${XILINX_LIB_DIR} -y ${XILINX_LIB_DIR}/unisims -DXILINX_GLS ${COMPILE_ARGS} -o ${DUT}.netlist.sim $^
+
+${XILINX_LIBS_DIR}/.git:
+	@echo "XILINX_LIBS_DIR = ${XILINX_LIBS_DIR}"
+	@echo "XILINX_LIB_URL = ${XILINX_LIB_URL}"
+	@echo "Checking if XilinxUnisimLibrar/.git exists..."
+	@if [ ! -d "XilinxUnisimLibrary/.git" ]; then \
+		echo "Directory XilinxUnisimLibrar/.git does not exist, cloning..."; \
+		git clone ${XILINX_LIB_URL}; \
+	else \
+		echo "Xilinx library already cloned"; \
+	fi
+
+clean:
+	rm -f ${DUT}_sim sim.log sim.vcd
+	rm -f ${DUT}.netlist.v synth.log

Weiyet_RTLStructLib/source/Dual_Edge_FF/tb/sv/tb.sv

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+`timescale 1ns / 1ps
+//////////////////////////////////////////////////////////////////////////////////
+// Create Date: 09/22/2024 01:42:52 PM
+// Created By: https://www.linkedin.com/in/wei-yet-ng-065485119/
+// Author: https://www.linkedin.com/in/wei-yet-ng-065485119/
+// Last Update: 13/06/2025 09:23 PM
+// Last Updated By: https://www.linkedin.com/in/wei-yet-ng-065485119/
+// Module Name: tb
+// Description: Testbench for dual_edge_ff module.
+// Additional Comments:
+// 
+//////////////////////////////////////////////////////////////////////////////////
+
+
+module tb(
+    );
+    // DUT parameter
+    localparam DUT_DATA_WIDTH = 8;
+    localparam DUT_RESET_VALUE = 0; // Max number of nodes in the list
+    
+    // TB parameter
+    localparam TB_CLK_PERIOD = 25;
+    localparam TB_TEST_WEIGHT = 1;
+    localparam SIM_TIMEOUT = 500000;
+
+integer err_cnt = 0;
+
+// input 
+reg clk = 0;
+reg rst_n = 1;
+reg [DUT_DATA_WIDTH-1:0] data_in = 0;
+reg [DUT_DATA_WIDTH-1:0] pos_edge_latch_en = 0;
+reg [DUT_DATA_WIDTH-1:0] neg_edge_latch_en = 0;
+// output
+wire [DUT_DATA_WIDTH-1:0] data_out; 
+
+`ifdef XILINX_GLS
+    // for xilinx gate sim
+    glbl glbl();
+`endif
+
+
+
+   dual_edge_ff #(
+        .DATA_WIDTH(DUT_DATA_WIDTH),   
+        .RESET_VALUE(DUT_RESET_VALUE) 
+    ) DUT (
+       /*input  wire                  */.clk(clk),
+       /*input  wire                  */.rst_n(rst_n),
+       /*input  wire [DATA_WIDTH-1:0] */.data_in(data_in),
+       /*input  wire [DATA_WIDTH-1:0] */.pos_edge_latch_en(pos_edge_latch_en),
+       /*input  wire [DATA_WIDTH-1:0] */.neg_edge_latch_en(neg_edge_latch_en),
+       /*output wire [DATA_WIDTH-1:0] */.data_out(data_out)
+    );
+    
+always #(TB_CLK_PERIOD/2) clk = ~clk; 
+
+integer i = 0;
+integer j = 0;
+reg [DUT_DATA_WIDTH-1:0] target_data_wr;
+
+task direct_test();
+begin
+   $display("Starting direct operation test");
+   for (i = 0; i<50; i=i+1) begin
+        j = $urandom_range(0,2);
+        case (j)
+            0: begin //posedge only 
+               @ (negedge clk) // change data_in at negedge, expect DUT to latch at next posedge 
+               #1;
+               pos_edge_latch_en= 2**DUT_DATA_WIDTH -1;
+               target_data_wr = $urandom;
+               data_in = target_data_wr;
+               @ (posedge clk) 
+               #1;
+               if (data_out != target_data_wr) begin
+                    $error("%0t Data out is incorrect at posedge, EXP: %0d, ACT: %0d",$realtime, target_data_wr, data_out);
+                    err_cnt = err_cnt + 1;               
+               end else begin
+                    $display("%0t Data out is correctly latched at posedge with value %0d", $realtime, data_out); 
+               end
+              
+               data_in = target_data_wr + 1;
+               @ (negedge clk) 
+               #1;
+               if (data_out != target_data_wr) begin
+                    $error("%0t Data out is incorrect, should not be updated at posedge, EXP: %0d, ACT: %0d",$realtime, target_data_wr, data_out);
+                    err_cnt = err_cnt + 1;               
+               end
+               pos_edge_latch_en = 1'b0;
+               
+            end
+            1: begin //negedge only 
+               @ (posedge clk) // change data in at posedge, expect DUT to latch at next negedge 
+               #1;
+               neg_edge_latch_en= 2**DUT_DATA_WIDTH -1;
+               target_data_wr = $urandom;
+               data_in = target_data_wr;
+               @ (negedge clk) 
+               #1;
+               if (data_out != target_data_wr) begin
+                    $error("%0t Data out is incorrect at negedge, EXP: %0d, ACT: %0d",$realtime, target_data_wr, data_out);
+                    err_cnt = err_cnt + 1;               
+               end else begin
+                    $display("%0t Data out is correctly latched at negedge with value %0d", $realtime, data_out); 
+               end
+
+               data_in = target_data_wr + 1;
+               @ (posedge clk) 
+               #1;
+               if (data_out != target_data_wr) begin
+                    $error("%0t Data out is incorrect, should not be updated at posedge, EXP: %0d, ACT: %0d",$realtime, target_data_wr, data_out);
+                    err_cnt = err_cnt + 1;               
+               end
+               neg_edge_latch_en = 1'b0;
+               
+            end
+            default: begin // both edge 
+               @ (posedge clk) // change data in at posedge, expect DUT to latch at next negedge 
+               #1;
+               neg_edge_latch_en= 2**DUT_DATA_WIDTH -1;
+               pos_edge_latch_en= 2**DUT_DATA_WIDTH -1;
+               target_data_wr = $urandom;
+               data_in = target_data_wr;
+               @ (negedge clk) 
+               #1;
+               if (data_out != target_data_wr) begin
+                    $error("%0t Data out is incorrect at negedge, EXP: %0d, ACT: %0d",$realtime, target_data_wr, data_out);
+                    err_cnt = err_cnt + 1;               
+               end else begin
+                    $display("%0t Data out is correctly latched at negedge with value %0d", $realtime, data_out); 
+               end
+               
+               target_data_wr = $urandom;
+               data_in = target_data_wr;
+               @ (posedge clk) 
+               #1;
+               if (data_out != target_data_wr) begin
+                    $error("%0t Data out is incorrect at posedge, EXP: %0d, ACT: %0d",$realtime, target_data_wr, data_out);
+                    err_cnt = err_cnt + 1;               
+               end else begin
+                    $display("%0t Data out is correctly latched at posedge with value %0d", $realtime, data_out); 
+               end
+               neg_edge_latch_en= 0;
+               pos_edge_latch_en= 0;
+            end
+        
+        endcase;
+        
+   end
+
+
+end
+endtask
+
+initial begin
+    string vcdfile;
+    int vcdlevel;
+    int seed;
+    int temp;
+
+    rst_n = 1'b0;
+    if ($value$plusargs("VCDFILE=%s",vcdfile))
+        $dumpfile(vcdfile);
+    if ($value$plusargs("VCDLEVEL=%d",vcdlevel))
+        $dumpvars(vcdlevel,tb);
+    if ($value$plusargs("SEED=%d",seed)) begin
+        temp = $urandom(seed);
+        $display("Seed = %0d",seed);
+    end
+    #100;
+    rst_n = 1'b1;
+    direct_test();
+    
+    #1000;
+    
+    if (err_cnt > 0) begin
+        $display("\n%0t TEST FAILED",$realtime);
+        $display("Error count = %0d\n", err_cnt);
+    end else
+        $display("\n%0t TEST PASSED\n", $realtime);
+    $finish;
+end
+
+initial begin
+    #(SIM_TIMEOUT)
+    $display("\n%0t TEST FAILED", $realtime);
+    $display("SIM TIMEOUT!\n");
+    $finish;
+end
+
+endmodule
+

Weiyet_RTLStructLib/source/Dual_Edge_FF/vip/pyuvm/Makefile

@@ -0,0 +1,46 @@
+# Makefile for Dual Edge FF pyUVM VIP
+
+SIM ?= icarus
+TOPLEVEL_LANG ?= verilog
+WAVES ?= 1
+
+PWD=$(shell pwd)
+
+# RTL source files
+VERILOG_SOURCES = $(PWD)/../../src/dual_edge_ff.sv
+
+TOPLEVEL = dual_edge_ff
+MODULE   = tb_deff
+
+# DUT parameters
+COMPILE_ARGS = -Pdual_edge_ff.DATA_WIDTH=8
+COMPILE_ARGS += -Pdual_edge_ff.RESET_VALUE=0
+
+COCOTB_HDL_TIMEUNIT = 1ns
+COCOTB_HDL_TIMEPRECISION = 1ps
+
+# Waveform dump
+ifeq ($(SIM), icarus)
+ifeq ($(WAVES), 1)
+	$(shell echo 'module iverilog_dump();' > iverilog_dump.v)
+	$(shell echo 'initial begin' >> iverilog_dump.v)
+	$(shell echo '    $$dumpfile("$(TOPLEVEL).vcd");' >> iverilog_dump.v)
+	$(shell echo '    $$dumpvars(0, $(TOPLEVEL));' >> iverilog_dump.v)
+	$(shell echo 'end' >> iverilog_dump.v)
+	$(shell echo 'endmodule' >> iverilog_dump.v)
+	VERILOG_SOURCES += $(PWD)/iverilog_dump.v
+	COMPILE_ARGS += -s iverilog_dump
+endif
+endif
+
+include $(shell cocotb-config --makefiles)/Makefile.sim
+
+.PHONY: help
+help:
+	@echo "Dual Edge FF pyUVM VIP Makefile"
+	@echo "================================"
+	@echo ""
+	@echo "Usage:"
+	@echo "  make           - Run test with Icarus Verilog"
+	@echo "  make WAVES=0   - Disable waveforms"
+	@echo "  make clean     - Clean build files"

Weiyet_RTLStructLib/source/Dual_Edge_FF/vip/pyuvm/__init__.py

@@ -0,0 +1,9 @@
+"""Dual Edge FF VIP - pyUVM Implementation
+Create Date: 01/05/2026
+"""
+__version__ = "1.0.0"
+from .common import *
+from .agent import *
+from .env import *
+from .sequences import *
+from .tests import *

Weiyet_RTLStructLib/source/Dual_Edge_FF/vip/uvm/README.md

@@ -0,0 +1,318 @@
+# Dual Edge Flip-Flop UVM VIP (Verification IP) User Guide
+
+## 📁 Directory Structure
+
+```
+uvm/
+├── README.md                                  [User guide and documentation]
+├── common/                                    [Core VIP source files]
+│   ├── deff_vip_pkg.sv                       [Main package]
+│   ├── deff_vip_config.sv                    [Configuration class]
+│   └── deff_vip_seq_item.sv                  [Transaction definitions]
+├── interface/                                 [Interface definition]
+│   └── deff_vip_if.sv                        [Virtual interface]
+├── agent/                                     [Agent layer components]
+│   ├── deff_vip_driver.sv                    [Driver implementation]
+│   ├── deff_vip_monitor.sv                   [Monitor implementation]
+│   ├── deff_vip_sequencer.sv                 [Sequencer]
+│   └── deff_vip_agent.sv                     [Agent wrapper]
+├── env/                                       [Environment layer]
+│   ├── deff_vip_env.sv                       [Environment]
+│   └── deff_vip_scoreboard.sv                [Checking with dual-edge model]
+├── sequences/                                 [Test sequences]
+│   ├── deff_vip_base_seq.sv                  [Base sequence]
+│   └── deff_vip_random_seq.sv                [Random, pos-edge, neg-edge, dual-edge]
+└── sim/                                       [Testbench]
+    ├── tb_top.sv                              [Testbench top module]
+    └── tests/
+        ├── deff_vip_base_test.sv              [Base test class]
+        └── deff_vip_simple_test.sv            [Multiple test scenarios]
+```
+
+## 🚀 Quick Start
+
+**Step 1:** Update interface signals in your testbench:
+```systemverilog
+deff_vip_if dut_if(clk);
+// Connect to DUT
+uvm_config_db#(virtual deff_vip_if)::set(null, "*", "deff_vip_vif", dut_if);
+```
+
+**Step 2:** Configure DUT parameters in your test:
+```systemverilog
+cfg = deff_vip_config::type_id::create("cfg");
+cfg.DATA_WIDTH = 8;
+cfg.RESET_VALUE = 8'h00;
+uvm_config_db#(deff_vip_config)::set(this, "*", "deff_vip_cfg", cfg);
+```
+
+**Step 3:** Create environment:
+```systemverilog
+deff_env = deff_vip_env::type_id::create("deff_env", this);
+```
+
+## 🚀 Available Sequences
+
+**Random (Both Edges):**
+```systemverilog
+deff_vip_random_seq seq = deff_vip_random_seq::type_id::create("seq");
+seq.num_items = 50;
+seq.start(env.get_sequencer());
+```
+
+**Positive Edge Only:**
+```systemverilog
+deff_vip_pos_edge_only_seq seq = deff_vip_pos_edge_only_seq::type_id::create("seq");
+seq.num_items = 30;
+seq.start(env.get_sequencer());
+```
+
+**Negative Edge Only:**
+```systemverilog
+deff_vip_neg_edge_only_seq seq = deff_vip_neg_edge_only_seq::type_id::create("seq");
+seq.num_items = 30;
+seq.start(env.get_sequencer());
+```
+
+**Dual Edge (Both Active):**
+```systemverilog
+deff_vip_dual_edge_seq seq = deff_vip_dual_edge_seq::type_id::create("seq");
+seq.num_items = 30;
+seq.start(env.get_sequencer());
+```
+
+## 🧪 Available Tests
+
+### 1. Simple Test
+Random transactions with mixed edge enables:
+```bash
+vsim -c +UVM_TESTNAME=simple_test -do "run -all; quit"
+```
+
+### 2. Positive Edge Test
+Only positive edge latching active:
+```bash
+vsim -c +UVM_TESTNAME=pos_edge_test -do "run -all; quit"
+```
+
+### 3. Negative Edge Test
+Only negative edge latching active:
+```bash
+vsim -c +UVM_TESTNAME=neg_edge_test -do "run -all; quit"
+```
+
+### 4. Dual Edge Test
+Both edges active simultaneously:
+```bash
+vsim -c +UVM_TESTNAME=dual_edge_test -do "run -all; quit"
+```
+
+### 5. Random Test
+Mix of all edge configurations:
+```bash
+vsim -c +UVM_TESTNAME=random_test -do "run -all; quit"
+```
+
+## 📋 Dual Edge FF Operation
+
+The Dual Edge FF latches data on **both** positive and negative clock edges to achieve **double data rate**:
+
+| Signal | Description | Width |
+|--------|-------------|-------|
+| **data_in** | Input data | 8 bits |
+| **pos_edge_latch_en** | Enable latching on positive edge (per-bit) | 8 bits |
+| **neg_edge_latch_en** | Enable latching on negative edge (per-bit) | 8 bits |
+| **data_out** | Output data (XOR of pos and neg registers) | 8 bits |
+
+## ✅ Self-Checking Features
+
+The scoreboard automatically verifies:
+- ✅ Correct XOR behavior between pos and neg registers
+- ✅ Positive edge latching when enabled
+- ✅ Negative edge latching when enabled
+- ✅ Per-bit independent latch enable control
+- ✅ Reset value initialization
+- ✅ Output = q_out_pos XOR q_out_neg
+
+## 🔧 Key Features
+
+1. **Dual-Edge Triggering**: Latches on both rising and falling clock edges
+2. **Per-Bit Control**: Independent latch enable for each bit
+3. **XOR Output**: Output is XOR of positive and negative edge registers
+4. **Double Data Rate**: Can capture data at 2× clock frequency
+5. **Synthesizable**: Uses XOR encoding for dual-edge behavior
+6. **Intelligent Scoreboard**: Models both pos and neg registers
+
+## 📊 Dual Edge FF Architecture
+
+### Internal Structure:
+```
+For each bit i:
+
+Positive Edge Path:
+  d_in_pos[i] = data_in[i] XOR q_out_neg[i]
+  @ posedge clk: if (pos_edge_latch_en[i]) q_out_pos[i] <= d_in_pos[i]
+
+Negative Edge Path:
+  d_in_neg[i] = data_in[i] XOR q_out_pos[i]
+  @ negedge clk: if (neg_edge_latch_en[i]) q_out_neg[i] <= d_in_neg[i]
+
+Output:
+  data_out[i] = q_out_pos[i] XOR q_out_neg[i]
+```
+
+### Why XOR Encoding?
+The XOR encoding allows **synthesizable** dual-edge behavior:
+- Traditional dual-edge FFs need special libraries
+- XOR encoding works with standard cells
+- Positive and negative edge FFs can be synthesized normally
+- XOR gates combine the outputs
+
+## 🔍 Operation Modes
+
+### Mode 1: Positive Edge Only
+```systemverilog
+pos_edge_latch_en = 8'hFF;  // All bits enabled
+neg_edge_latch_en = 8'h00;  // All bits disabled
+// Behaves like normal positive-edge FF
+```
+
+### Mode 2: Negative Edge Only
+```systemverilog
+pos_edge_latch_en = 8'h00;  // All bits disabled
+neg_edge_latch_en = 8'hFF;  // All bits enabled
+// Behaves like negative-edge FF
+```
+
+### Mode 3: Dual Edge (DDR)
+```systemverilog
+pos_edge_latch_en = 8'hFF;  // All bits enabled
+neg_edge_latch_en = 8'hFF;  // All bits enabled
+// Captures data on BOTH edges (double data rate)
+```
+
+### Mode 4: Per-Bit Mixed
+```systemverilog
+pos_edge_latch_en = 8'hF0;  // Upper nibble on pos edge
+neg_edge_latch_en = 8'h0F;  // Lower nibble on neg edge
+// Different bits use different edges
+```
+
+## 🚨 Common Issues & Solutions
+
+### Issue: Output doesn't match expected
+**Solution:** Remember output is **XOR** of two registers:
+```systemverilog
+data_out = q_out_pos XOR q_out_neg
+```
+Not a simple register value.
+
+### Issue: Understanding XOR encoding
+**Solution:**
+- When only pos_edge active: q_out_neg stays 0, so data_out = q_out_pos
+- When only neg_edge active: q_out_pos stays at reset, output depends on XOR
+- When both active: data toggles between edges
+
+### Issue: Reset behavior
+**Solution:**
+- q_out_pos resets to RESET_VALUE
+- q_out_neg always resets to 0
+- Initial data_out = RESET_VALUE XOR 0 = RESET_VALUE
+
+## 📚 Example Usage
+
+```systemverilog
+class my_test extends base_test;
+    `uvm_component_utils(my_test)
+
+    task run_phase(uvm_phase phase);
+        deff_vip_pos_edge_only_seq pos_seq;
+        deff_vip_neg_edge_only_seq neg_seq;
+        deff_vip_dual_edge_seq dual_seq;
+
+        phase.raise_objection(this);
+
+        // Test positive edge latching
+        pos_seq = deff_vip_pos_edge_only_seq::type_id::create("pos_seq");
+        pos_seq.num_items = 20;
+        pos_seq.start(env.get_sequencer());
+
+        #200ns;
+
+        // Test negative edge latching
+        neg_seq = deff_vip_neg_edge_only_seq::type_id::create("neg_seq");
+        neg_seq.num_items = 20;
+        neg_seq.start(env.get_sequencer());
+
+        #200ns;
+
+        // Test dual edge (DDR) mode
+        dual_seq = deff_vip_dual_edge_seq::type_id::create("dual_seq");
+        dual_seq.num_items = 20;
+        dual_seq.start(env.get_sequencer());
+
+        #200ns;
+        phase.drop_objection(this);
+    endtask
+endclass
+```
+
+## 🎯 Key Characteristics
+
+- **Dual-Edge Sensitive**: Responds to both rising and falling clock edges
+- **XOR-Based Encoding**: Synthesizable implementation of dual-edge behavior
+- **Per-Bit Control**: Each bit can independently use pos/neg/both edges
+- **Double Data Rate**: Effective 2× data throughput
+- **Standard Cell Compatible**: No special library cells required
+
+## 📈 Performance Characteristics
+
+**Effective Frequency:**
+- Single edge FF: 1× clock frequency
+- Dual edge FF: 2× clock frequency (captures on both edges)
+
+**Example at 40MHz:**
+- Clock period: 25ns
+- Pos edge: data captured at 0ns, 25ns, 50ns...
+- Neg edge: data captured at 12.5ns, 37.5ns, 62.5ns...
+- Effective rate: 80 Mega-samples/second
+
+## 🔬 Test Strategy
+
+The test suite covers:
+
+1. **simple_test**: Random mix of edge enables
+2. **pos_edge_test**: Verify positive edge path only
+3. **neg_edge_test**: Verify negative edge path only
+4. **dual_edge_test**: Verify both edges active (DDR mode)
+5. **random_test**: Random switching between modes
+
+**Coverage Goals:**
+- All 256 combinations of pos_edge_latch_en
+- All 256 combinations of neg_edge_latch_en
+- Edge transitions (pos→neg, neg→pos, both→single)
+- Data patterns (walking 1s, walking 0s, random)
+
+## 🔍 Differences from Standard FF
+
+| Aspect | Standard FF | Dual Edge FF |
+|--------|------------|--------------|
+| **Edge Sensitivity** | Single edge (pos or neg) | Both edges |
+| **Data Rate** | 1× clock | 2× clock |
+| **Implementation** | Simple D-FF | XOR-encoded dual registers |
+| **Output** | Direct Q | XOR of two registers |
+| **Complexity** | Low | Medium |
+| **Use Case** | Normal clocking | DDR, high-speed I/O |
+
+## 💡 Applications
+
+The Dual Edge FF is used in:
+- **DDR Memory Interfaces**: Data on both edges
+- **High-Speed Serial I/O**: Double throughput
+- **Clock Domain Crossing**: Phase alignment
+- **Video Interfaces**: Pixel clock doubling
+- **FPGA I/O Blocks**: Standard DDR support
+
+**Happy Verifying! 🚀**
+
+*This VIP demonstrates verification of dual-edge triggered flip-flops with XOR encoding using UVM.*

Weiyet_RTLStructLib/source/FIFO/README.md

@@ -0,0 +1,95 @@
+# FIFO (Queue)
+
+A configurable FIFO (First-In-First-Out) buffer implementation in Verilog with support for both synchronous and asynchronous clock domains. The module uses Gray code for pointer synchronization in asynchronous mode to prevent metastability issues.
+
+## Features
+
+- Configurable data width and depth
+- Support for both synchronous and asynchronous clock domains
+- Optional registered read output
+- Gray code synchronization for clock domain crossing
+- Full and empty status flags
+- Automatic pointer wraparound
+- Parameterized design for easy customization
+
+## Parameters
+
+| Parameter    | Description                                      | Default |
+|-------------|--------------------------------------------------|---------|
+| DEPTH       | Number of entries in the FIFO                     | 12      |
+| DATA_WIDTH  | Width of each data entry                         | 8       |
+| ASYNC       | Enable asynchronous mode (1) or synchronous (0)   | 1       |
+| RD_BUFFER   | Enable registered read output (1) or bypass (0)   | 1       |
+
+## Interface Signals
+
+| Signal      | Direction | Width         | Description                                    |
+|-------------|-----------|---------------|------------------------------------------------|
+| rd_clk      | Input     | 1            | Read clock domain                              |
+| wr_clk      | Input     | 1            | Write clock domain                             |
+| rst         | Input     | 1            | Active high reset                              |
+| data_wr     | Input     | DATA_WIDTH   | Data input for writing                        |
+| wr_en       | Input     | 1            | Write enable signal                           |
+| fifo_full   | Output    | 1            | FIFO full indicator                           |
+| data_rd     | Output    | DATA_WIDTH   | Data output from reading                      |
+| rd_en       | Input     | 1            | Read enable signal                            |
+| fifo_empty  | Output    | 1            | FIFO empty indicator                          |
+
+## Usage Example
+
+```verilog
+// Instantiate a 16-deep, 32-bit wide asynchronous FIFO with registered output
+fifo #(
+    .DEPTH(16),
+    .DATA_WIDTH(32),
+    .ASYNC(1),
+    .RD_BUFFER(1)
+) fifo_inst (
+    .rd_clk(read_clock),
+    .wr_clk(write_clock),
+    .rst(reset),
+    .data_wr(write_data),
+    .wr_en(write_enable),
+    .fifo_full(full_flag),
+    .data_rd(read_data),
+    .rd_en(read_enable),
+    .fifo_empty(empty_flag)
+);
+```
+
+## Design Notes
+
+1. **Clock Domain Crossing**: In asynchronous mode (ASYNC=1), the design uses Gray code encoding for pointer synchronization to prevent metastability issues when crossing clock domains.
+
+2. **Read Buffer**: When RD_BUFFER=1, the read data output is registered, adding one clock cycle of latency but improving timing. When RD_BUFFER=0, the read data is combinatorial.
+
+3. **Full/Empty Flags**: 
+   - The empty flag is asserted when read and write pointers are equal
+   - The full flag is asserted when the next write pointer would equal the current read pointer
+
+4. **Reset Behavior**: 
+   - All pointers are reset to zero
+   - All memory locations are cleared
+   - All flags are deasserted
+
+## Implementation Details
+
+The module uses separate read and write pointers for tracking FIFO occupancy. In asynchronous mode, these pointers are converted to Gray code before being synchronized across clock domains. The implementation includes:
+
+- Binary counters for read/write operation
+- Gray code conversion for pointer synchronization
+- Two-stage synchronizers for clock domain crossing
+- Configurable output registration
+- Automatic pointer wraparound at FIFO boundaries
+
+## Timing Considerations
+
+1. In asynchronous mode, allow at least 2 clock cycles for pointer synchronization
+2. When RD_BUFFER=1, read data is available one clock cycle after rd_en assertion
+3. Full and empty flags are registered outputs
+
+## Limitations
+
+- The DEPTH parameter must be a power of 2 for proper wraparound behavior
+- Simultaneous read/write at full/empty conditions should be managed by external logic
+- The reset signal must be synchronized to both clock domains

Weiyet_RTLStructLib/source/Hash_Table/README.md

@@ -0,0 +1,91 @@
+# Hash Table Module
+## Overview
+This Verilog module implements a flexible hash table with configurable collision resolution methods and hash algorithms. It provides support for key-value storage with operations such as insert, delete, and search.
+
+## Features
+- Configurable key and value widths
+- Support for different collision resolution methods
+- Multiple hash algorithm options
+- Synchronous operation with reset capability
+- Collision tracking and error reporting
+
+## Parameters
+| Parameter | Description | Default |
+|-----------|-------------|---------|
+| KEY_WIDTH | Width of keys in bits | 32 |
+| VALUE_WIDTH | Width of values in bits | 32 |
+| TOTAL_ENTRY | Number of indices in the hash table | 64 |
+| CHAINING_SIZE | Maximum chain length for collision resolution | 4 |
+| COLLISION_METHOD | Method for handling collisions | "MULTI_STAGE_CHAINING" |
+| HASH_ALGORITHM | Algorithm used for hashing | "MODULUS" |
+
+## Port Descriptions
+### Input Ports
+| Port | Width | Description |
+|------|-------|-------------|
+| clk | 1 | System clock signal |
+| rst | 1 | Active-high reset signal |
+| key_in | KEY_WIDTH | Key for insert, delete, or search operations |
+| value_in | VALUE_WIDTH | Value to be stored (for insert operations) |
+| op_sel | 2 | Operation selector (00: Insert, 01: Delete, 10: Search) |
+| op_en | 1 | Operation enable signal |
+
+### Output Ports
+| Port | Width | Description |
+|------|-------|-------------|
+| value_out | VALUE_WIDTH | Value retrieved during search operations |
+| op_done | 1 | Operation completion indicator |
+| op_error | 1 | Error indicator (FULL for insert, KEY_NOT_FOUND for delete/search) |
+| collision_count | log2(CHAINING_SIZE) | Number of collisions encountered |
+
+## Collision Methods
+- **MULTI_STAGE_CHAINING**: Multiple entries at the same index using a linked list approach
+- **LINEAR_PROBING**: Referenced in parameters but not fully implemented in the provided code
+
+## Hash Algorithms
+- **MODULUS**: Simple modulus operation (key % TABLE_SIZE)
+- **SHA1**, **FNV1A**: Referenced in parameters but not fully implemented in the provided code
+
+## Timing
+- All operations are synchronized to the positive edge of the clock
+- Reset is asynchronous and active-high
+- Operations are initiated when op_en is asserted
+- op_done indicates completion of an operation
+
+## Usage Example
+```verilog
+hash_table #(
+    .KEY_WIDTH(32),
+    .VALUE_WIDTH(32),
+    .TOTAL_ENTRY(128),
+    .CHAINING_SIZE(8),
+    .COLLISION_METHOD("MULTI_STAGE_CHAINING"),
+    .HASH_ALGORITHM("MODULUS")
+) hash_module (
+    .clk(system_clk),
+    .rst(system_rst),
+    .key_in(key),
+    .value_in(value),
+    .op_sel(operation),
+    .op_en(enable),
+    .value_out(retrieved_value),
+    .op_done(operation_complete),
+    .op_error(operation_error),
+    .collision_count(collisions)
+);
+```
+
+## Implementation Details
+- Uses a state machine for operation control
+- Implements chained hash entries for collision resolution
+- Provides error reporting for table overflow or key not found conditions
+- Uses Verilog parameter-based configuration for flexibility
+
+## Limitations and Issues
+- Implementation for alternative hash algorithms is mentioned but not provided
+
+## Performance Considerations
+- Search and delete operations may require multiple cycles depending on chain length
+- Performance degrades as collision chains grow longer
+- No optimization for locality or cache behavior
+- Please consider using [CAM(Content Addressable Memory)](https://en.wikipedia.org/wiki/Content-addressable_memory) if you have the resources.

Weiyet_RTLStructLib/source/LICENSE

@@ -0,0 +1,21 @@
+MIT License
+
+Copyright (c) [Wei Yet Ng]
+
+Permission is hereby granted, free of charge, to any person obtaining a copy
+of this software and associated documentation files (the "Software"), to deal
+in the Software without restriction, including without limitation the rights
+to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+copies of the Software, and to permit persons to whom the Software is
+furnished to do so, subject to the following conditions:
+
+The above copyright notice and this permission notice shall be included in all
+copies or substantial portions of the Software.
+
+THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+SOFTWARE.

Weiyet_RTLStructLib/source/LIFO/README.md

@@ -0,0 +1,114 @@
+# LIFO (Stack) 
+
+A configurable LIFO (Last-In-First-Out) buffer implementation in Verilog. This module implements a stack-like behavior where the last element written is the first one to be read out. The design includes bypass functionality for simultaneous read/write operations.
+
+## Features
+
+- Configurable data width and depth
+- Single clock domain operation
+- Full and empty status flags
+- Bypass path for simultaneous read/write
+- Registered read output
+- Automatic pointer management
+- Parameterized design for easy customization
+
+## Parameters
+
+| Parameter    | Description                                      | Default |
+|-------------|--------------------------------------------------|---------|
+| DEPTH       | Number of entries in the LIFO                     | 12      |
+| DATA_WIDTH  | Width of each data entry                         | 8       |
+
+## Interface Signals
+
+| Signal      | Direction | Width         | Description                                    |
+|-------------|-----------|---------------|------------------------------------------------|
+| clk         | Input     | 1            | System clock                                   |
+| rst         | Input     | 1            | Active high reset                              |
+| data_wr     | Input     | DATA_WIDTH   | Data input for writing                        |
+| wr_en       | Input     | 1            | Write enable signal                           |
+| lifo_full   | Output    | 1            | LIFO full indicator                           |
+| data_rd     | Output    | DATA_WIDTH   | Data output from reading                      |
+| rd_en       | Input     | 1            | Read enable signal                            |
+| lifo_empty  | Output    | 1            | LIFO empty indicator                          |
+
+## Usage Example
+
+```verilog
+// Instantiate a 16-deep, 32-bit wide LIFO
+lifo #(
+    .DEPTH(16),
+    .DATA_WIDTH(32)
+) lifo_inst (
+    .clk(system_clock),
+    .rst(reset),
+    .data_wr(write_data),
+    .wr_en(write_enable),
+    .lifo_full(full_flag),
+    .data_rd(read_data),
+    .rd_en(read_enable),
+    .lifo_empty(empty_flag)
+);
+```
+
+## Operation Modes
+
+The module supports three operation modes:
+
+1. **Write Operation (wr_op)**
+   - Activated when wr_en=1 and rd_en=0
+   - Data is written to current pointer location
+   - Pointer increments if not full
+
+2. **Read Operation (rd_op)**
+   - Activated when rd_en=1 and wr_en=0
+   - Data is read from (pointer-1) location
+   - Pointer decrements if not empty
+
+3. **Bypass Operation (bypass_op)**
+   - Activated when both wr_en=1 and rd_en=1
+   - Input data (data_wr) is directly passed to output (data_rd)
+   - Pointer remains unchanged
+
+## Design Notes
+
+1. **Pointer Management**:
+   - Single pointer tracks both read and write positions
+   - Increments on write, decrements on read
+   - Range: 0 to (DEPTH-1)
+
+2. **Memory Organization**:
+   - Stack-like structure with DEPTH entries
+   - Each entry is DATA_WIDTH bits wide
+   - Last written data is first to be read
+
+3. **Flag Generation**:
+   - Empty flag is combinatorial (pointer = 0)
+   - Full flag is registered (pointer = DEPTH-1)
+   - Flags prevent invalid operations
+
+## Reset Behavior
+
+On assertion of reset:
+- Pointer is cleared to zero
+- All memory locations are cleared
+- Full flag is deasserted
+- Output data is cleared
+- Empty flag becomes active
+
+## Timing Considerations
+
+1. All outputs except lifo_empty are registered
+2. Data is available on the next clock cycle after rd_en assertion
+3. Bypass operation provides data in the same clock cycle
+
+## Limitations
+
+- Single clock domain operation only
+- No protection against overflow/underflow if flags are ignored
+- DEPTH parameter should be at least 2 for proper operation
+- Simultaneous read/write operations bypass the stack memory
+
+## Alternative Implementation Note
+
+The commented code at the bottom of the module suggests an alternative implementation for full flag handling and read operations, which could be implemented if different timing behavior is needed.

Weiyet_RTLStructLib/source/LIFO/src/lifo.sv

@@ -0,0 +1,77 @@
+module lifo #(
+    parameter DEPTH = 12,
+    parameter DATA_WIDTH = 8
+)(
+    input wire clk,
+    input wire rst,
+    input wire [DATA_WIDTH-1:0] data_wr,
+    input wire wr_en,
+    output reg lifo_full,
+    output reg [DATA_WIDTH-1:0] data_rd,
+    input wire rd_en,
+    output wire lifo_empty
+);
+    localparam CNTR_WIDTH = $clog2(DEPTH);
+   
+    reg [CNTR_WIDTH-1:0] pointer;
+    reg [DATA_WIDTH-1:0] lifo_stored [DEPTH-1:0];
+    wire wr_op;
+    wire rd_op;
+    wire bypass_op;
+    
+    integer i;
+    
+    assign wr_op = wr_en & !rd_en;
+    assign rd_op = rd_en & !wr_en;
+    assign bypass_op = wr_en & rd_en;
+
+    // pointer logic 
+    always @ (posedge clk, posedge rst) begin
+        if(rst) begin
+            pointer <= {CNTR_WIDTH{1'b0}};
+        end else if(rd_op & !lifo_empty) begin
+            pointer <= pointer - 1;
+        end else if(wr_op & !lifo_full) begin
+            pointer <= pointer + 1;
+        end
+    end
+    
+    // lifo memory
+    always @ (posedge clk, posedge rst) begin
+        if(rst) begin
+            for (i = 0; i < DEPTH; i = i + 1)
+                lifo_stored[i] <= {DATA_WIDTH{1'b0}};
+        end else if (wr_op & !lifo_full) begin
+            lifo_stored[pointer] <= data_wr;
+        end 
+    end
+
+    // data_rd
+    always @ (posedge clk, posedge rst) begin
+        if(rst) begin
+            data_rd <= {DATA_WIDTH{1'b0}};
+        end else if (rd_op & !lifo_empty) begin
+            data_rd <= lifo_stored[pointer-1];
+        end else if (bypass_op) begin
+            data_rd <= data_wr;
+        end
+    end
+
+    // flag
+    assign lifo_empty = pointer ==  {CNTR_WIDTH{1'b0}};
+    always @ (posedge clk, posedge rst) begin
+        if(rst) begin
+            lifo_full <= 1'b0;
+        end else if(rd_op) begin
+            lifo_full <= 1'b0;
+        end else if(pointer == (DEPTH-1) & wr_op) begin
+            lifo_full <= 1'b1;
+        end
+    end
+    
+    // assign lifo_full = pointer == (DEPTH); 
+    // can use this as flag and modify read cond when lifo is full
+    // if lifo_full : data_rd <= (lifo_stored[pointer-1]) else data_rd <= lifo_stored[pointer]
+    //              : pointer <= pointer - 2             else pointer <= pointer <= pointer -1
+    
+endmodule

Weiyet_RTLStructLib/source/LIFO/src/rtl_list.f

@@ -0,0 +1 @@
+lifo.sv

Weiyet_RTLStructLib/source/LIFO/tb/cocotb/Makefile

@@ -0,0 +1,43 @@
+SIM ?= icarus
+TOPLEVEL_LANG ?= verilog
+WAVES ?= 1 #set 1 to enable waveform dump. 
+
+PWD=$(shell pwd)
+
+#export PYTHONPATH := $(PWD)/../model:$(PYTHONPATH)
+
+VERILOG_SOURCES = $(PWD)/../../src/lifo.sv
+
+# DUT Top
+TOPLEVEL = lifo
+# top python file
+MODULE   = tb
+
+#use , separtor to run multiple TESTCASE, by default all @cocotb.test will be run
+#TESTCASE = lifo_rand_op_test
+TESTCASE = lifo_rand_op_test
+
+COMPILE_ARGS = -Plifo.DEPTH=12 # DUT parameter #"-p" iverilog command flags
+COMPILE_ARGS += -Plifo.DATA_WIDTH=8 # DUT parameter #"-p" iverilog command flags
+#run make clean before running with new parameter.
+
+#Set RANDOM_SEED number
+#PLUSARGS = +seed=1716033254
+COCOTB_HDL_TIMEUNIT = 1ns
+COCOTB_HDL_TIMEPRECISION = 1ps
+
+ifeq ($(SIM), icarus) 
+   $(shell echo 'module iverilog_dump();' > iverilog_dump.v)
+   $(shell echo 'initial begin' >> iverilog_dump.v)
+   $(shell echo '    $$dumpfile("$(TOPLEVEL).vcd");' >> iverilog_dump.v)
+   $(shell echo '    $$dumpvars(0, $(TOPLEVEL));' >> iverilog_dump.v)
+   $(shell echo '    $$dumpvars(0, $(TOPLEVEL));' >> iverilog_dump.v)
+   $(shell echo 'end' >> iverilog_dump.v)
+   $(shell echo 'endmodule' >> iverilog_dump.v)
+   VERILOG_SOURCES += $(PWD)/iverilog_dump.v
+   COMPILE_ARGS += -s iverilog_dump  
+endif
+
+include $(shell cocotb-config --makefiles)/Makefile.sim
+
+

Weiyet_RTLStructLib/source/LIFO/tb/cocotb/tb.py

@@ -0,0 +1,182 @@
+import random
+#import asyncio
+import cocotb
+from cocotb.triggers import Timer, RisingEdge, ReadOnly
+from cocotb.clock import Clock
+from cocotb_bus.drivers import BusDriver
+from cocotb_bus.monitors import BusMonitor
+
+DEPTH = 12 # DUT parameter
+DATA_WIDTH = 8 # DUT paramter
+TEST_WEIGHT = 1 # TB multiplier for stimulus injected
+CLK_PERIOD = 20 # TB clk generator
+#SIM_TIMEOUT = 100000; // TB simulation time out
+MAX_DATA = 2**DATA_WIDTH - 1
+err_cnt = 0
+
+# lifo #(
+# .DEPTH(DEPTH), 
+# .DATA_WIDTH(DATA_WIDTH)) DUT (
+#     /*input wire*/ .clk(clk),
+#     /*input wire*/ .rst(rst),
+#     /*input wire [DATA_WIDTH-1:0]*/ .data_wr(data_wr),
+#     /*input wire*/ .wr_en(wr_en),
+#     /*output reg*/ .lifo_full(lifo_full),
+#     /*output reg [DATA_WIDTH-1:0]*/ .data_rd(data_rd),
+#     /*input wire*/ .rd_en(rd_en),
+#     /*output wire*/ .lifo_empty(lifo_empty));
+
+class OutputDriver(BusDriver):
+    _signals = ["wr_en", "rd_en", "data_wr"] #dut.wr_en ; dut.rd_en; dut.data_wr
+
+    def __init__(self, dut, name, clk):
+        BusDriver.__init__(self, dut, name, clk)
+        self.bus.wr_en.value = 0
+        self.bus.rd_en.value = 0
+        self.dut = dut
+        self.clk = clk
+
+    async def _driver_send(self, op_sel, op_count):
+        match op_sel:
+            case 0:
+                wr_data_array = []
+                for i in range (op_count):
+                    wr_data_array.append(random.randint(0,MAX_DATA))
+                await self.lifo_write(wr_data_array)
+            case 1:
+                await self.lifo_read(op_count)
+            case 2:
+                wr_data_array = []
+                for i in range (op_count):
+                    wr_data_array.append(random.randint(0,MAX_DATA))
+                await self.lifo_read_write_simul(wr_data_array)
+
+    async def lifo_write(self, wr_data_array):
+        data_w = 0
+        while len(wr_data_array) != 0:
+            await RisingEdge(self.clk)
+            await Timer (1, units = 'ns')
+            self.bus.wr_en.value = 1
+            data_w = wr_data_array.pop()
+            self.bus.data_wr.value = data_w
+            self.dut._log.info("Driver: Writting Data = %d",data_w)
+        await RisingEdge(self.clk)
+        self.bus.wr_en.value = 0
+        
+    async def lifo_read(self,op_count):
+        for i in range(op_count):
+            await RisingEdge(self.clk)
+            self.bus.rd_en.value = 1
+            self.dut._log.info("Driver: Reading Data = %d",)
+        await RisingEdge(self.clk)
+        await Timer (1, units='ns')
+        self.bus.rd_en.value = 0
+
+    async def lifo_read_write_simul(self,wr_data_array):
+        data_w = 0
+        while len(wr_data_array) != 0:
+            await RisingEdge(self.clk)
+            await Timer (1, units = 'ns')
+            self.bus.rd_en.value = 1
+            self.bus.wr_en.value = 1
+            data_w = wr_data_array.pop()
+            self.bus.data_wr.value = data_w    
+            self.dut._log.info("Driver: Simultanenous read write, data = %d",data_w)
+        await RisingEdge(self.clk)
+        await Timer (1, units='ns')      
+        self.bus.rd_en.value = 0
+        self.bus.wr_en.value = 0
+
+class InputMonitor(BusMonitor):
+    _signals = ["wr_en","rd_en","lifo_empty","lifo_full","data_rd","data_wr"]
+
+    def __init__(self, dut, name, clk, reset):
+        BusMonitor.__init__(self, dut, name, clk, reset)
+        self.clk = clk
+        self.reset = reset
+        self.dut = dut
+
+    async def _monitor_recv(self):
+        global err_cnt
+        lifo_expected = []
+        rd_en_buf = 0
+        wr_en_buf = 0
+        data_wr_buf = 0
+        while True:
+             await RisingEdge(self.clock)
+             await Timer(3,units='ns') 
+             await ReadOnly()
+
+             if self.reset.value == 1:
+                 rd_en_buf = 0
+                 wr_en_buf = 0
+                 data_wr_buf = 0
+                 continue
+
+             if(rd_en_buf == 1 and wr_en_buf == 1):
+                if(self.bus.data_rd.value == data_wr_buf):
+                    self.dut._log.info("Monitor: Simultaneous Data read/write, ACT = %d, EXP = %d, FIFO entry = %d", self.bus.data_rd.value, data_wr_buf, len(lifo_expected))
+             elif(wr_en_buf and len(lifo_expected) != DEPTH): 
+                lifo_expected.append(data_wr_buf)
+                self.dut._log.info("Monitor: Data write = %d, FIFO entry = %d", data_wr_buf, len(lifo_expected))
+             elif(rd_en_buf == 1 and len(lifo_expected) != 0):
+                lifo_expected.pop()
+                self.dut._log.info("Monitor: Data read = %d, FIFO entry = %d", self.bus.data_rd.value, len(lifo_expected))
+
+             if(len(lifo_expected) == 0):
+                if(self.bus.lifo_empty.value):
+                    self.dut._log.info("Monitor: LIFO is empty, lifo_full flag is asserted correctly")
+                else:
+                    self.dut._log.error("Monitor: LIFO is empty, but lifo_full flag is not asserted")
+                    err_cnt += 1
+             elif(self.bus.lifo_empty.value): 
+                    self.dut._log.error("Monitor: LIFO is not empty, but lifo_empty flag is asserted")
+             
+             if(len(lifo_expected) == DEPTH):
+                if(self.bus.lifo_full.value):
+                    self.dut._log.info("Monitor: LIFO is full, lifo_full flag is asserted correctly")
+                else:
+                    self.dut._log.error("Monitor: LIFO is full, but lifo_full flag is not asserted")
+                    err_cnt += 1
+             elif(self.bus.lifo_full.value):
+                self.dut._log.error("Monitor: LIFO is not full, but lifo_full flag is asserted")
+
+             rd_en_buf = int(self.bus.rd_en.value)
+             wr_en_buf = int(self.bus.wr_en.value)
+             data_wr_buf = int(self.bus.data_wr.value)
+
+
+async def dut_init(dut):
+    global DEPTH 
+    global DATA_WIDTH
+    global MAX_DATA
+    DEPTH = dut.DEPTH.value 
+    DATA_WIDTH = dut.DATA_WIDTH.value
+    MAX_DATA = 2**DATA_WIDTH - 1
+    await cocotb.start(Clock(dut.clk, CLK_PERIOD, units="ns").start())
+    dut.data_wr.value = 0
+    dut.rd_en.value = 0
+    dut.wr_en.value = 0
+    dut.rst.value = 1
+    await(Timer(100,'ns'))
+    dut.rst.value = 0
+    await(Timer(100,'ns'))
+    
+
+@cocotb.test()
+async def lifo_rand_op_test(dut):
+    await dut_init(dut)
+    driver = OutputDriver(dut, None, dut.clk) #set name='None', refer to Bus class
+    monitor = InputMonitor(dut, None, dut.clk, dut.rst)
+    cocotb.log.info("SEED NUMBER = %d",cocotb.RANDOM_SEED)
+    i = DEPTH
+    lifo_expected = []
+    while(i >= 0):
+        op_sel = random.randint(0,1)
+        op_count = random.randint(1,5)
+        i = i - op_count      
+        await driver._driver_send(op_sel,op_count)
+        await Timer(CLK_PERIOD,'ns')
+        if (err_cnt > 0):
+            cocotb.log.error("Errors count = %d",err_cnt)
+            cocotb.result.test_fail()

Weiyet_RTLStructLib/source/LIFO/tb/sv/Makefile

@@ -0,0 +1,29 @@
+
+DUT = lifo
+SIM_OPTS ?= ../../src/lifo.sv
+SEED ?= $$(shuf -i 1-10000 -n 1)
+XILINX_LIB_URL ?= https://github.com/Xilinx/XilinxUnisimLibrary.git
+XILINX_LIB_DIR ?= XilinxUnisimLibrary/verilog/src
+
+sim: gen_sim 
+	./${DUT}.sim +VCDFILE=sim.vcd +VCDLEVEL=0 +SEED=${SEED} | tee sim.log
+
+gen_sim: tb.sv ${SIM_OPTS}  # to generate executable file by using iverilator  
+	iverilog -g2012 -s tb -o ${DUT}.sim $^
+
+synth: ${SIM_OPTS}
+	yosys -p synth_xilinx ${SIM_OPTS} -L synth.log -o ${DUT}.netlist.v
+    #timeout
+
+netlist_sim: gen_netlist_sim
+	./${DUT}.netlist.sim +VCDFILE=netlist_sim.vcd +VCDLEVEL=0 +SEED=${SEED} | tee netlist_sim.log
+
+gen_netlist_sim: tb.sv ${DUT}.netlist.v | ${XILINX_LIBS_DIR}/.git
+	iverilog -g2012 -s tb -y ${XILINX_LIB_DIR} -y ${XILINX_LIB_DIR}/unisims -DXILINX_GLS -o ${DUT}.netlist.sim $^
+
+${XILINX_LIBS_DIR}/.git:
+	git clone ${XILINX_LIB_URL}
+
+clean:
+	rm -f ${DUT}_sim sim.log sim.vcd
+	rm -f ${DUT}.netlist.v synth.log

Weiyet_RTLStructLib/source/LIFO/tb/sv/tb.sv

@@ -0,0 +1,229 @@
+`timescale 1ns / 1ps
+//////////////////////////////////////////////////////////////////////////////////
+// 
+// Create Date: 05/05/2024 05:05:34 PM
+// Last Update Date: 05/05/2024 05:05:34 PM
+// Module Name: tb
+// Author: https://www.linkedin.com/in/wei-yet-ng-065485119/
+// Description: 1. lifo_random_op_test
+//                  - Read/Write/Read_write_simultaneous 
+// Additional Comments:
+// 
+//////////////////////////////////////////////////////////////////////////////////
+
+
+module tb(
+);
+parameter DEPTH = 12; // DUT parameter
+parameter DATA_WIDTH = 8; // DUT paramter
+parameter CLK_PERIOD = 20; // TB clk generator
+parameter SIM_TIMEOUT = 100000; // TB simulation time out
+parameter TEST_WEIGHT = 1; //TB Test weight
+
+integer lifo_expected [$];
+integer i; 
+integer op_sel,op_count;
+integer err_cnt = 0;
+reg clk = 0; 
+
+reg rst = 1;
+reg [DATA_WIDTH-1:0] data_wr = 0;
+reg wr_en = 0;
+reg rd_en = 0;
+wire [DATA_WIDTH-1:0] data_rd;
+wire lifo_empty;
+wire lifo_full;
+
+`ifdef XILINX_GLS
+    // for xilinx gate sim
+    glbl glbl();
+`endif
+
+lifo #(
+.DEPTH(DEPTH), 
+.DATA_WIDTH(DATA_WIDTH)) DUT (
+    /*input wire*/ .clk(clk),
+    /*input wire*/ .rst(rst),
+    /*input wire [DATA_WIDTH-1:0]*/ .data_wr(data_wr),
+    /*input wire*/ .wr_en(wr_en),
+    /*output reg*/ .lifo_full(lifo_full),
+    /*output reg [DATA_WIDTH-1:0]*/ .data_rd(data_rd),
+    /*input wire*/ .rd_en(rd_en),
+    /*output wire*/ .lifo_empty(lifo_empty));
+
+always #(CLK_PERIOD>>1) clk = ~clk;
+
+integer exp_data_wr = 0;
+
+task lifo_write(input integer wr_data_array[$]);
+    while($size(wr_data_array) != 0) begin
+        exp_data_wr = wr_data_array.pop_front();
+        @(posedge(clk))
+        wr_en <= 1;
+        data_wr <= exp_data_wr;
+        #1
+        if($size(lifo_expected)<DEPTH) begin
+            if(!lifo_full) begin
+                lifo_expected.push_back(exp_data_wr);
+                $display("%0t Data written = %d, entry = %d",$realtime,exp_data_wr,$size(lifo_expected));
+            end
+            else begin
+                $error("%0t LIFO is not full but lifo_full flag is asserted incorrectly",$realtime);
+                err_cnt = err_cnt + 1;
+            end 
+        end else begin
+            if(lifo_full) begin
+                $display("%0t LIFO is full, lifo_full flag is asserted correctly",$realtime);
+            end
+            else begin
+                $error("%0t LIFO is full but lifo_full flag is not asserted",$realtime);
+                err_cnt = err_cnt + 1;
+            end 
+        end
+    end
+    @(posedge(clk))
+    wr_en <= 0;
+endtask
+
+integer j;
+integer act_data_rd = 0;
+integer exp_data_rd = 0;
+
+task lifo_read(input integer count);
+    @(posedge(clk))
+    rd_en <= 1;
+    for (j = 0; j<count; j=j+1)begin
+       @(posedge(clk))
+       if($size(lifo_expected)>0) begin
+            if(lifo_empty) begin
+                $error("%0t LIFO is not empty but lifo_empty flag is asserted incorrectly",$realtime);
+            end
+            #1
+            act_data_rd = data_rd;
+            exp_data_rd = lifo_expected.pop_back();
+            if(act_data_rd == exp_data_rd) begin
+               $display("%0t Data read = %d, FIFO entry = %d", $realtime, act_data_rd, $size(lifo_expected));
+            end 
+            else begin
+               $error("%0t Data read mismatch, ACT = %d, EXP =%d, FIFO entry = %d", $realtime, act_data_rd, exp_data_rd, $size(lifo_expected));
+               err_cnt = err_cnt + 1;
+            end
+       end else begin
+            if(!lifo_empty) begin
+                $error("%0t LIFO is empty but lifo_empty flag is not asserted",$realtime);
+                err_cnt = err_cnt + 1;
+            end 
+            else begin
+                $display("%0t LIFO is empty, lifo_empty flag is asserted correctly",$realtime);
+            end 
+       end 
+    end
+    rd_en = 0;
+endtask
+
+task lifo_simul_read_write(input integer wr_data_array[$]);
+    exp_data_wr = wr_data_array.pop_front();
+    @(posedge(clk))
+    rd_en <= 1;
+    wr_en <= 1;
+    data_wr <= exp_data_wr;    
+    
+    while($size(wr_data_array) != 0) begin
+        @(posedge(clk))
+        #1 
+        act_data_rd = data_rd;
+        if(act_data_rd == exp_data_wr) begin    
+            $display("%0t Simultaneous Data read/write = %d, FIFO entry = %d", $realtime, act_data_rd, $size(lifo_expected));
+        end
+        else begin
+            $error("%0t Simultaneous Data read/write, ACT = %d, EXP = %d, FIFO entry = %d", $realtime, act_data_rd, exp_data_wr, $size(lifo_expected));
+        end
+        #1
+        exp_data_wr = wr_data_array.pop_front();
+        data_wr <= exp_data_wr;
+    end
+    @(posedge(clk))
+    wr_en <= 0;
+    rd_en <= 0;
+    #1
+    act_data_rd = data_rd;
+    if(act_data_rd == exp_data_wr) begin    
+        $display("%0t Simultaneous Data read/write = %d, FIFO entry = %d", $realtime, act_data_rd, $size(lifo_expected));
+    end
+    else begin
+        $error("%0t Simultaneous Data read/write, ACT = %d, EXP = %d, FIFO entry = %d", $realtime, act_data_rd, exp_data_wr, $size(lifo_expected));
+    end
+endtask
+
+integer wr_data_array[$];
+integer k;
+
+task lifo_random_op_test(input integer count);
+    i = count;
+    while (i > 0) begin
+        op_sel = $urandom_range(0,2);
+        op_count = $urandom_range(1,i);
+        i = i - op_count;
+        case(op_sel)
+            0: begin // read
+                 $display("%0t LIFO Read %d times", $realtime, op_count);
+                lifo_read(op_count);
+            end
+            1: begin // write
+                 $display("%0t LIFO Write %d times", $realtime, op_count);
+                for(k=0 ; k < op_count; k = k+1) begin
+                    wr_data_array.push_back($urandom_range(0,2**DATA_WIDTH-1));
+                end
+                lifo_write(wr_data_array);
+            end
+            2: begin // simultaneous read write
+                $display("%0t LIFO Simul Read Write %d times", $realtime, op_count);
+                for(k=0 ; k < op_count; k = k+1) begin
+                    wr_data_array.push_back($urandom_range(0,2**DATA_WIDTH-1));
+                end
+                lifo_simul_read_write(wr_data_array);
+            end
+        endcase
+    end
+endtask
+
+initial begin
+    string vcdfile;
+    int vcdlevel;
+    int seed;
+    int temp;
+    if ($value$plusargs("VCDFILE=%s",vcdfile))
+        $dumpfile(vcdfile);
+    if ($value$plusargs("VCDLEVEL=%d",vcdlevel))
+        $dumpvars(vcdlevel, tb);
+        $display("Seed number: %d",vcdlevel);
+    if ($value$plusargs("SEED=%d",seed)) begin
+        $display("Seed number: %d",seed);
+        temp = $urandom(seed);
+    end
+    
+    repeat(TEST_WEIGHT) begin
+        rst = 1;
+        #100 
+        rst = 0;
+        #100
+        lifo_expected = {};
+        lifo_random_op_test(DEPTH);
+        #1000;
+    end
+    if (err_cnt > 0) begin
+        $display("\n%0t TEST FAILED",$realtime);
+        $display("Error count = %d\n", err_cnt);
+    end else
+        $display("\n%0t TEST PASSED\n", $realtime);
+    $finish;
+end
+
+initial begin
+    #(SIM_TIMEOUT);
+    $display("\n%0t TEST FAILED", $realtime);
+    $display("SIM TIMEOUT!\n");
+    $finish;
+end
+
+endmodule

Weiyet_RTLStructLib/source/LIFO/vip/pyuvm/Makefile

@@ -0,0 +1,46 @@
+# Makefile for LIFO pyUVM VIP
+
+SIM ?= icarus
+TOPLEVEL_LANG ?= verilog
+WAVES ?= 1
+
+PWD=$(shell pwd)
+
+# RTL source files
+VERILOG_SOURCES = $(PWD)/../../src/lifo.sv
+
+TOPLEVEL = lifo
+MODULE   = tb_lifo
+
+# DUT parameters
+COMPILE_ARGS = -Plifo.DEPTH=12
+COMPILE_ARGS += -Plifo.DATA_WIDTH=8
+
+COCOTB_HDL_TIMEUNIT = 1ns
+COCOTB_HDL_TIMEPRECISION = 1ps
+
+# Waveform dump
+ifeq ($(SIM), icarus)
+ifeq ($(WAVES), 1)
+	$(shell echo 'module iverilog_dump();' > iverilog_dump.v)
+	$(shell echo 'initial begin' >> iverilog_dump.v)
+	$(shell echo '    $$dumpfile("$(TOPLEVEL).vcd");' >> iverilog_dump.v)
+	$(shell echo '    $$dumpvars(0, $(TOPLEVEL));' >> iverilog_dump.v)
+	$(shell echo 'end' >> iverilog_dump.v)
+	$(shell echo 'endmodule' >> iverilog_dump.v)
+	VERILOG_SOURCES += $(PWD)/iverilog_dump.v
+	COMPILE_ARGS += -s iverilog_dump
+endif
+endif
+
+include $(shell cocotb-config --makefiles)/Makefile.sim
+
+.PHONY: help
+help:
+	@echo "LIFO pyUVM VIP Makefile"
+	@echo "======================="
+	@echo ""
+	@echo "Usage:"
+	@echo "  make           - Run test with Icarus Verilog"
+	@echo "  make WAVES=0   - Disable waveforms"
+	@echo "  make clean     - Clean build files"

Weiyet_RTLStructLib/source/LIFO/vip/pyuvm/README.md

@@ -0,0 +1,72 @@
+# LIFO pyUVM VIP User Guide
+
+## Overview
+
+Complete pyUVM-based Verification IP for **Last-In-First-Out (LIFO) Stack** - standard stack data structure.
+
+## Quick Start
+
+```bash
+cd LIFO/vip/pyuvm
+make                     # Run test
+gtkwave lifo.vcd         # View waveforms
+```
+
+## LIFO Features
+
+**Key Capability**: Last-In-First-Out stack with PUSH and POP operations
+
+| Signal | Description | Width |
+|--------|-------------|-------|
+| `data_wr` | Write data for PUSH | DATA_WIDTH |
+| `wr_en` | Write enable (PUSH) | 1 |
+| `rd_en` | Read enable (POP) | 1 |
+| `data_rd` | Read data from POP | DATA_WIDTH |
+| `lifo_full` | Stack full flag | 1 |
+| `lifo_empty` | Stack empty flag | 1 |
+
+## Configuration
+
+```python
+cfg = LifoVipConfig("cfg")
+cfg.DEPTH = 12
+cfg.DATA_WIDTH = 8
+```
+
+## Self-Checking
+
+The scoreboard uses a Python list as the LIFO reference model:
+- PUSH: `list.append(data)` - adds to end
+- POP: `list.pop()` - removes from end (LIFO behavior)
+
+## Example
+
+```python
+from sequences.lifo_vip_push_seq import LifoVipPushSeq
+from sequences.lifo_vip_pop_seq import LifoVipPopSeq
+
+# Push data
+push_seq = LifoVipPushSeq("push_seq")
+push_seq.num_trans = 10
+await push_seq.start(env.get_sequencer())
+
+# Pop data
+pop_seq = LifoVipPopSeq("pop_seq")
+pop_seq.num_trans = 5
+await pop_seq.start(env.get_sequencer())
+```
+
+## Available Sequences
+
+- `LifoVipPushSeq` - Push-only operations
+- `LifoVipPopSeq` - Pop-only operations
+- `LifoVipRandomSeq` - Random PUSH/POP mix
+
+## Use Cases
+
+- Stack data structure verification
+- LIFO behavior validation
+- Full/empty flag checking
+- Bypass operation testing (simultaneous push/pop)
+
+**Happy Verifying!**

Weiyet_RTLStructLib/source/LIFO/vip/pyuvm/__init__.py

@@ -0,0 +1 @@
+"""LIFO VIP - pyUVM Verification IP for Last-In-First-Out Stack"""

Weiyet_RTLStructLib/source/LIFO/vip/pyuvm/agent/__init__.py

@@ -0,0 +1 @@
+"""LIFO VIP Agent Components"""

Weiyet_RTLStructLib/source/LIFO/vip/pyuvm/agent/lifo_vip_agent.py

@@ -0,0 +1,35 @@
+"""LIFO VIP Agent"""
+from pyuvm import uvm_agent
+from .lifo_vip_driver import LifoVipDriver
+from .lifo_vip_monitor import LifoVipMonitor
+from .lifo_vip_sequencer import LifoVipSequencer
+
+class LifoVipAgent(uvm_agent):
+    def __init__(self, name, parent):
+        super().__init__(name, parent)
+        self.driver = None
+        self.monitor = None
+        self.sequencer = None
+        self.cfg = None
+
+    def build_phase(self):
+        super().build_phase()
+        from pyuvm import ConfigDB
+        arr = []
+        if not ConfigDB().get(self, "", "lifo_vip_cfg", arr):
+            self.logger.critical("No config found in ConfigDB!")
+        else:
+            self.cfg = arr[0]
+
+        # Always create monitor
+        self.monitor = LifoVipMonitor("monitor", self)
+
+        # Create driver and sequencer if active
+        if self.cfg.is_active:
+            self.driver = LifoVipDriver("driver", self)
+            self.sequencer = LifoVipSequencer("sequencer", self)
+
+    def connect_phase(self):
+        super().connect_phase()
+        if self.cfg.is_active:
+            self.driver.seq_item_port.connect(self.sequencer.seq_item_export)

Weiyet_RTLStructLib/source/LIFO/vip/pyuvm/agent/lifo_vip_driver.py

@@ -0,0 +1,78 @@
+"""LIFO VIP Driver"""
+from pyuvm import uvm_driver
+from cocotb.triggers import RisingEdge
+from ..common.lifo_vip_seq_item import LifoVipSeqItem
+from ..common import LifoOp
+
+class LifoVipDriver(uvm_driver):
+    def __init__(self, name, parent):
+        super().__init__(name, parent)
+        self.dut = None
+        self.cfg = None
+
+    def build_phase(self):
+        super().build_phase()
+        from pyuvm import ConfigDB
+        arr = []
+        if not ConfigDB().get(self, "", "lifo_vip_dut", arr):
+            self.logger.critical("No DUT found in ConfigDB!")
+        else:
+            self.dut = arr[0]
+
+        arr = []
+        if not ConfigDB().get(self, "", "lifo_vip_cfg", arr):
+            self.logger.critical("No config found in ConfigDB!")
+        else:
+            self.cfg = arr[0]
+
+    async def run_phase(self):
+        while True:
+            item = await self.seq_item_port.get_next_item()
+            await self.drive_item(item)
+            self.seq_item_port.item_done()
+
+    async def drive_item(self, item):
+        """Drive transaction to DUT"""
+        if item.op == LifoOp.PUSH:
+            await self.drive_push(item)
+        elif item.op == LifoOp.POP:
+            await self.drive_pop(item)
+        elif item.op == LifoOp.IDLE:
+            await self.drive_idle()
+
+    async def drive_push(self, item):
+        """Drive PUSH operation"""
+        await RisingEdge(self.dut.clk)
+        self.dut.wr_en.value = 1
+        self.dut.rd_en.value = 0
+        data_mask = (1 << self.cfg.DATA_WIDTH) - 1
+        self.dut.data_wr.value = item.data & data_mask
+
+        await RisingEdge(self.dut.clk)
+        item.full = bool(self.dut.lifo_full.value)
+        item.success = not item.full
+
+        self.dut.wr_en.value = 0
+
+        self.logger.debug(f"PUSH: data=0x{item.data:x} full={item.full}")
+
+    async def drive_pop(self, item):
+        """Drive POP operation"""
+        await RisingEdge(self.dut.clk)
+        self.dut.rd_en.value = 1
+        self.dut.wr_en.value = 0
+
+        await RisingEdge(self.dut.clk)
+        item.empty = bool(self.dut.lifo_empty.value)
+        item.read_data = int(self.dut.data_rd.value)
+        item.success = not item.empty
+
+        self.dut.rd_en.value = 0
+
+        self.logger.debug(f"POP: data=0x{item.read_data:x} empty={item.empty}")
+
+    async def drive_idle(self):
+        """Drive IDLE cycle"""
+        await RisingEdge(self.dut.clk)
+        self.dut.wr_en.value = 0
+        self.dut.rd_en.value = 0

Weiyet_RTLStructLib/source/LIFO/vip/pyuvm/agent/lifo_vip_monitor.py

@@ -0,0 +1,68 @@
+"""LIFO VIP Monitor"""
+from pyuvm import uvm_monitor
+from cocotb.triggers import RisingEdge
+from ..common.lifo_vip_seq_item import LifoVipSeqItem
+from ..common import LifoOp
+
+class LifoVipMonitor(uvm_monitor):
+    def __init__(self, name, parent):
+        super().__init__(name, parent)
+        self.dut = None
+        self.cfg = None
+        from pyuvm import uvm_analysis_port
+        self.ap = uvm_analysis_port("ap", self)
+
+    def build_phase(self):
+        super().build_phase()
+        from pyuvm import ConfigDB
+        arr = []
+        if not ConfigDB().get(self, "", "lifo_vip_dut", arr):
+            self.logger.critical("No DUT found in ConfigDB!")
+        else:
+            self.dut = arr[0]
+
+        arr = []
+        if not ConfigDB().get(self, "", "lifo_vip_cfg", arr):
+            self.logger.critical("No config found in ConfigDB!")
+        else:
+            self.cfg = arr[0]
+
+    async def run_phase(self):
+        while True:
+            await RisingEdge(self.dut.clk)
+
+            wr_en = bool(self.dut.wr_en.value)
+            rd_en = bool(self.dut.rd_en.value)
+
+            # Detect push operation
+            if wr_en and not rd_en:
+                item = LifoVipSeqItem("item")
+                item.op = LifoOp.PUSH
+                item.data = int(self.dut.data_wr.value)
+                item.full = bool(self.dut.lifo_full.value)
+                item.success = not item.full
+                self.ap.write(item)
+                self.logger.debug(f"Observed PUSH: data=0x{item.data:x} full={item.full}")
+
+            # Detect pop operation
+            elif rd_en and not wr_en:
+                await RisingEdge(self.dut.clk)  # Wait one cycle to capture read data
+                item = LifoVipSeqItem("item")
+                item.op = LifoOp.POP
+                item.read_data = int(self.dut.data_rd.value)
+                item.empty = bool(self.dut.lifo_empty.value)
+                item.success = not item.empty
+                self.ap.write(item)
+                self.logger.debug(f"Observed POP: data=0x{item.read_data:x} empty={item.empty}")
+
+            # Detect simultaneous push/pop (bypass)
+            elif wr_en and rd_en:
+                await RisingEdge(self.dut.clk)
+                item = LifoVipSeqItem("item")
+                item.op = LifoOp.PUSH  # Record as push for scoreboard
+                item.data = int(self.dut.data_wr.value)
+                item.read_data = int(self.dut.data_rd.value)  # Bypass data
+                item.full = bool(self.dut.lifo_full.value)
+                item.empty = bool(self.dut.lifo_empty.value)
+                self.ap.write(item)
+                self.logger.debug(f"Observed BYPASS: wr=0x{item.data:x} rd=0x{item.read_data:x}")

Weiyet_RTLStructLib/source/LIFO/vip/pyuvm/agent/lifo_vip_sequencer.py

@@ -0,0 +1,7 @@
+"""LIFO VIP Sequencer"""
+from pyuvm import uvm_sequencer
+from ..common.lifo_vip_seq_item import LifoVipSeqItem
+
+class LifoVipSequencer(uvm_sequencer):
+    def __init__(self, name, parent):
+        super().__init__(name, parent)

Weiyet_RTLStructLib/source/LIFO/vip/pyuvm/common/__init__.py

@@ -0,0 +1,8 @@
+"""LIFO VIP Common Components"""
+from enum import IntEnum
+
+class LifoOp(IntEnum):
+    """LIFO Operation Types"""
+    PUSH = 0
+    POP = 1
+    IDLE = 2

Weiyet_RTLStructLib/source/LIFO/vip/pyuvm/common/lifo_vip_config.py

@@ -0,0 +1,14 @@
+"""LIFO VIP Configuration"""
+from pyuvm import uvm_object
+
+class LifoVipConfig(uvm_object):
+    def __init__(self, name="lifo_vip_config"):
+        super().__init__(name)
+        # DUT parameters
+        self.DEPTH = 12
+        self.DATA_WIDTH = 8
+
+        # VIP configuration
+        self.has_agent = True
+        self.enable_scoreboard = True
+        self.is_active = True

Weiyet_RTLStructLib/source/LIFO/vip/pyuvm/common/lifo_vip_seq_item.py

@@ -0,0 +1,40 @@
+"""LIFO VIP Sequence Item"""
+from pyuvm import uvm_sequence_item
+from .import LifoOp
+import random
+
+class LifoVipSeqItem(uvm_sequence_item):
+    def __init__(self, name="lifo_vip_seq_item"):
+        super().__init__(name)
+        # Transaction fields
+        self.op = LifoOp.PUSH
+        self.data = 0
+
+        # Response fields
+        self.read_data = 0
+        self.full = False
+        self.empty = False
+        self.success = True
+
+        # Config reference
+        self.cfg = None
+
+    def randomize(self):
+        """Randomize transaction fields"""
+        # Randomize operation
+        self.op = random.choice([LifoOp.PUSH, LifoOp.POP])
+
+        # Randomize data
+        if self.cfg:
+            max_val = (1 << self.cfg.DATA_WIDTH) - 1
+        else:
+            max_val = 255  # 8-bit default
+        self.data = random.randint(0, max_val)
+
+        return True
+
+    def __str__(self):
+        op_name = self.op.name if hasattr(self.op, 'name') else str(self.op)
+        return (f"Op:{op_name} Data:0x{self.data:x} "
+                f"ReadData:0x{self.read_data:x} Full:{self.full} "
+                f"Empty:{self.empty} Success:{self.success}")

Weiyet_RTLStructLib/source/LIFO/vip/pyuvm/env/__init__.py

@@ -0,0 +1 @@
+"""LIFO VIP Environment Components"""

Weiyet_RTLStructLib/source/LIFO/vip/pyuvm/env/lifo_vip_env.py

@@ -0,0 +1,38 @@
+"""LIFO VIP Environment"""
+from pyuvm import uvm_env, ConfigDB
+from ..agent.lifo_vip_agent import LifoVipAgent
+from .lifo_vip_scoreboard import LifoVipScoreboard
+
+class LifoVipEnv(uvm_env):
+    def __init__(self, name, parent):
+        super().__init__(name, parent)
+        self.agent = None
+        self.scoreboard = None
+        self.cfg = None
+
+    def build_phase(self):
+        super().build_phase()
+        arr = []
+        if not ConfigDB().get(self, "", "lifo_vip_cfg", arr):
+            self.logger.critical("No config found in ConfigDB!")
+        else:
+            self.cfg = arr[0]
+
+        # Create agent
+        if self.cfg.has_agent:
+            self.agent = LifoVipAgent("agent", self)
+
+        # Create scoreboard
+        if self.cfg.enable_scoreboard:
+            self.scoreboard = LifoVipScoreboard("scoreboard", self)
+
+    def connect_phase(self):
+        super().connect_phase()
+        if self.cfg.has_agent and self.cfg.enable_scoreboard:
+            self.agent.monitor.ap.connect(self.scoreboard.imp)
+
+    def get_sequencer(self):
+        """Return sequencer for use by sequences"""
+        if self.agent and self.agent.sequencer:
+            return self.agent.sequencer
+        return None

Weiyet_RTLStructLib/source/LIFO/vip/pyuvm/env/lifo_vip_scoreboard.py

@@ -0,0 +1,92 @@
+"""LIFO VIP Scoreboard"""
+from pyuvm import uvm_scoreboard, uvm_analysis_imp
+from ..common import LifoOp
+
+class LifoVipScoreboard(uvm_scoreboard):
+    def __init__(self, name, parent):
+        super().__init__(name, parent)
+        self.imp = uvm_analysis_imp("imp", self)
+        self.cfg = None
+        self.expected_queue = []  # Python list as LIFO model
+        self.push_count = 0
+        self.pop_count = 0
+        self.error_count = 0
+        self.bypass_count = 0
+
+    def build_phase(self):
+        super().build_phase()
+        from pyuvm import ConfigDB
+        arr = []
+        if not ConfigDB().get(self, "", "lifo_vip_cfg", arr):
+            self.logger.critical("No config found in ConfigDB!")
+        else:
+            self.cfg = arr[0]
+
+    def write(self, item):
+        """Receive transaction from monitor"""
+        if item.op == LifoOp.PUSH:
+            self.check_push(item)
+        elif item.op == LifoOp.POP:
+            self.check_pop(item)
+
+    def check_push(self, item):
+        """Check PUSH operation"""
+        if item.success:
+            # Successful push - add to model
+            self.expected_queue.append(item.data)
+            self.push_count += 1
+            self.logger.info(f"PUSH: data=0x{item.data:x} depth={len(self.expected_queue)}")
+
+            # Check full flag
+            if len(self.expected_queue) == self.cfg.DEPTH and not item.full:
+                self.logger.error(f"LIFO should be full but full flag not set. Depth={len(self.expected_queue)}")
+                self.error_count += 1
+        else:
+            # Failed push due to full LIFO
+            if not item.full:
+                self.logger.error("Push failed but full flag not set")
+                self.error_count += 1
+            self.logger.info("PUSH failed - LIFO full")
+
+    def check_pop(self, item):
+        """Check POP operation"""
+        if item.success:
+            # Successful pop - check data
+            if len(self.expected_queue) == 0:
+                self.logger.error("Pop succeeded but model is empty")
+                self.error_count += 1
+                return
+
+            expected_data = self.expected_queue.pop()  # LIFO: pop from back
+            self.pop_count += 1
+
+            if item.read_data != expected_data:
+                self.logger.error(f"Data mismatch! Expected=0x{expected_data:x} Actual=0x{item.read_data:x}")
+                self.error_count += 1
+            else:
+                self.logger.info(f"POP: data=0x{item.read_data:x} depth={len(self.expected_queue)} MATCH")
+
+            # Check empty flag
+            if len(self.expected_queue) == 0 and not item.empty:
+                self.logger.error("LIFO should be empty but empty flag not set")
+                self.error_count += 1
+        else:
+            # Failed pop due to empty LIFO
+            if not item.empty:
+                self.logger.error("Pop failed but empty flag not set")
+                self.error_count += 1
+            self.logger.info("POP failed - LIFO empty")
+
+    def report_phase(self):
+        super().report_phase()
+        self.logger.info("=" * 50)
+        self.logger.info(f"Push Count: {self.push_count}")
+        self.logger.info(f"Pop Count: {self.pop_count}")
+        self.logger.info(f"Error Count: {self.error_count}")
+        self.logger.info(f"Final Queue Depth: {len(self.expected_queue)}")
+        self.logger.info("=" * 50)
+
+        if self.error_count > 0:
+            self.logger.error(f"Test FAILED with {self.error_count} errors")
+        else:
+            self.logger.info("Test PASSED - No errors detected")

Weiyet_RTLStructLib/source/LIFO/vip/pyuvm/sequences/__init__.py

@@ -0,0 +1 @@
+"""LIFO VIP Sequences"""

Weiyet_RTLStructLib/source/LIFO/vip/pyuvm/sequences/lifo_vip_base_seq.py

@@ -0,0 +1,13 @@
+"""LIFO VIP Base Sequence"""
+from pyuvm import uvm_sequence
+from ..common.lifo_vip_seq_item import LifoVipSeqItem
+
+class LifoVipBaseSeq(uvm_sequence):
+    def __init__(self, name):
+        super().__init__(name)
+        self.num_trans = 10
+        self.cfg = None
+
+    async def body(self):
+        """Sequence body - override in derived classes"""
+        pass

Weiyet_RTLStructLib/source/LIFO/vip/pyuvm/sequences/lifo_vip_pop_seq.py

@@ -0,0 +1,17 @@
+"""LIFO VIP Pop Sequence"""
+from .lifo_vip_base_seq import LifoVipBaseSeq
+from ..common.lifo_vip_seq_item import LifoVipSeqItem
+from ..common import LifoOp
+
+class LifoVipPopSeq(LifoVipBaseSeq):
+    def __init__(self, name):
+        super().__init__(name)
+
+    async def body(self):
+        """Generate POP transactions"""
+        for i in range(self.num_trans):
+            item = LifoVipSeqItem(f"pop_item_{i}")
+            item.cfg = self.cfg
+            item.op = LifoOp.POP
+            await self.start_item(item)
+            await self.finish_item(item)

Weiyet_RTLStructLib/source/LIFO/vip/pyuvm/sequences/lifo_vip_push_seq.py

@@ -0,0 +1,18 @@
+"""LIFO VIP Push Sequence"""
+from .lifo_vip_base_seq import LifoVipBaseSeq
+from ..common.lifo_vip_seq_item import LifoVipSeqItem
+from ..common import LifoOp
+
+class LifoVipPushSeq(LifoVipBaseSeq):
+    def __init__(self, name):
+        super().__init__(name)
+
+    async def body(self):
+        """Generate PUSH transactions"""
+        for i in range(self.num_trans):
+            item = LifoVipSeqItem(f"push_item_{i}")
+            item.cfg = self.cfg
+            item.op = LifoOp.PUSH
+            item.randomize()
+            await self.start_item(item)
+            await self.finish_item(item)

Weiyet_RTLStructLib/source/LIFO/vip/pyuvm/sequences/lifo_vip_random_seq.py

@@ -0,0 +1,16 @@
+"""LIFO VIP Random Sequence"""
+from .lifo_vip_base_seq import LifoVipBaseSeq
+from ..common.lifo_vip_seq_item import LifoVipSeqItem
+
+class LifoVipRandomSeq(LifoVipBaseSeq):
+    def __init__(self, name):
+        super().__init__(name)
+
+    async def body(self):
+        """Generate random PUSH/POP transactions"""
+        for i in range(self.num_trans):
+            item = LifoVipSeqItem(f"rand_item_{i}")
+            item.cfg = self.cfg
+            item.randomize()  # Randomizes op and data
+            await self.start_item(item)
+            await self.finish_item(item)

Weiyet_RTLStructLib/source/LIFO/vip/pyuvm/tb_lifo.py

@@ -0,0 +1,36 @@
+"""LIFO VIP Testbench"""
+import cocotb
+from cocotb.clock import Clock
+from cocotb.triggers import Timer, FallingEdge
+from pyuvm import *
+from tests.lifo_vip_simple_test import SimpleTest
+
+async def dut_init(dut):
+    """Initialize DUT"""
+    cocotb.log.info("="*60)
+    cocotb.log.info("LIFO VIP Testbench Initialization")
+    cocotb.log.info("="*60)
+
+    # Start clock
+    cocotb.start_soon(Clock(dut.clk, 10, units="ns").start())
+
+    # Reset
+    dut.rst.value = 1
+    dut.data_wr.value = 0
+    dut.wr_en.value = 0
+    dut.rd_en.value = 0
+
+    await Timer(50, units="ns")
+    dut.rst.value = 0
+    await Timer(10, units="ns")
+
+    cocotb.log.info("DUT initialization complete")
+    ConfigDB().set(None, "*", "lifo_vip_dut", dut)
+
+@cocotb.test()
+async def lifo_simple_test(dut):
+    """Simple test for LIFO"""
+    await dut_init(dut)
+    cocotb.log.info("Starting LIFO Simple Test (pyUVM)")
+    await uvm_root().run_test("SimpleTest")
+    cocotb.log.info("LIFO Simple Test Complete")

Weiyet_RTLStructLib/source/LIFO/vip/pyuvm/tests/__init__.py

@@ -0,0 +1 @@
+"""LIFO VIP Tests"""

Weiyet_RTLStructLib/source/LIFO/vip/pyuvm/tests/lifo_vip_base_test.py

@@ -0,0 +1,37 @@
+"""LIFO VIP Base Test"""
+from pyuvm import *
+from ..env.lifo_vip_env import LifoVipEnv
+from ..common.lifo_vip_config import LifoVipConfig
+
+class BaseTest(uvm_test):
+    def __init__(self, name, parent):
+        super().__init__(name, parent)
+        self.env = None
+        self.cfg = None
+
+    def build_phase(self):
+        super().build_phase()
+
+        # Create configuration
+        self.cfg = LifoVipConfig("cfg")
+        self.cfg.DEPTH = 12
+        self.cfg.DATA_WIDTH = 8
+        self.cfg.has_agent = True
+        self.cfg.enable_scoreboard = True
+        self.cfg.is_active = True
+
+        # Set config in ConfigDB
+        ConfigDB().set(None, "*", "lifo_vip_cfg", self.cfg)
+
+        # Get DUT from ConfigDB
+        arr = []
+        if not ConfigDB().get(self, "", "lifo_vip_dut", arr):
+            self.logger.critical("No DUT found in ConfigDB!")
+
+        # Create environment
+        self.env = LifoVipEnv("env", self)
+
+    async def run_phase(self):
+        self.raise_objection()
+        # Base test does nothing - override in derived classes
+        self.drop_objection()

Weiyet_RTLStructLib/source/LIFO/vip/pyuvm/tests/lifo_vip_simple_test.py

@@ -0,0 +1,35 @@
+"""LIFO VIP Simple Test"""
+from pyuvm import *
+from cocotb.triggers import Timer
+from .lifo_vip_base_test import BaseTest
+from ..sequences.lifo_vip_push_seq import LifoVipPushSeq
+from ..sequences.lifo_vip_pop_seq import LifoVipPopSeq
+from ..sequences.lifo_vip_random_seq import LifoVipRandomSeq
+
+class SimpleTest(BaseTest):
+    def __init__(self, name, parent):
+        super().__init__(name, parent)
+
+    async def run_phase(self):
+        self.raise_objection()
+
+        # Push some data
+        push_seq = LifoVipPushSeq("push_seq")
+        push_seq.cfg = self.cfg
+        push_seq.num_trans = 10
+        await push_seq.start(self.env.get_sequencer())
+
+        # Pop some data
+        pop_seq = LifoVipPopSeq("pop_seq")
+        pop_seq.cfg = self.cfg
+        pop_seq.num_trans = 5
+        await pop_seq.start(self.env.get_sequencer())
+
+        # Random sequence
+        rand_seq = LifoVipRandomSeq("rand_seq")
+        rand_seq.cfg = self.cfg
+        rand_seq.num_trans = 20
+        await rand_seq.start(self.env.get_sequencer())
+
+        await Timer(200, units="ns")
+        self.drop_objection()

Weiyet_RTLStructLib/source/LIFO/vip/uvm/README.md

@@ -0,0 +1,194 @@
+# LIFO (Stack) UVM VIP (Verification IP) User Guide
+
+## 📁 Directory Structure
+
+```
+uvm/
+├── common/                        # Core VIP source files
+│   ├── lifo_vip_pkg.sv           # Main package + types/enums
+│   ├── lifo_vip_config.sv        # Configuration class
+│   └── lifo_vip_seq_item.sv      # Transaction definitions
+├── agent/                         # Agent layer components
+│   ├── lifo_vip_driver.sv        # Driver implementation
+│   ├── lifo_vip_monitor.sv       # Monitor implementation
+│   ├── lifo_vip_sequencer.sv     # Sequencer (simple)
+│   └── lifo_vip_agent.sv         # Agent wrapper
+├── env/                          # Environment layer
+│   ├── lifo_vip_env.sv           # Environment
+│   └── lifo_vip_scoreboard.sv    # Checking components
+├── sequences/                     # Test sequences
+│   ├── lifo_vip_base_seq.sv      # Base sequence
+│   ├── lifo_vip_push_seq.sv      # Push sequences
+│   └── lifo_vip_pop_seq.sv       # Pop sequences
+├── interface/                     # Interface definition
+│   └── lifo_vip_if.sv            # Virtual interface
+└── sim/                           # Testbench
+    ├── tests/
+    │   ├── lifo_vip_base_test.sv    # Base test class
+    │   └── lifo_vip_simple_test.sv  # Simple test + random test + full/empty test
+    └── tb_top.sv                    # Testbench top module
+```
+
+## 🚀 Quick Start
+
+**Step 1:** Update Agent Interface with correct internal signals (refer to `lifo_vip_if.sv`) in your top level testbench:
+```systemverilog
+// Update interface signal widths and connections in tb_top.sv
+lifo_vip_if dut_if(clk);
+assign dut_if.rst = u_lifo.rst;
+assign dut_if.data_wr = u_lifo.data_wr;
+assign dut_if.wr_en = u_lifo.wr_en;
+assign dut_if.lifo_full = u_lifo.lifo_full;
+assign dut_if.data_rd = u_lifo.data_rd;
+assign dut_if.rd_en = u_lifo.rd_en;
+assign dut_if.lifo_empty = u_lifo.lifo_empty;
+
+// Set interface in config DB
+uvm_config_db#(virtual lifo_vip_if)::set(null, "*", "lifo_vip_vif", dut_if);
+```
+
+**Step 2:** Update DUT parameters/configuration (refer to `lifo_vip_config.sv`) in your test:
+```systemverilog
+// In your test's build_phase()
+cfg = lifo_vip_config::type_id::create("cfg");
+cfg.DEPTH = 12;        // Match your LIFO depth
+cfg.DATA_WIDTH = 8;    // Match your data width
+
+// Set config in database
+uvm_config_db#(lifo_vip_config)::set(this, "*", "lifo_vip_cfg", cfg);
+```
+
+**Step 3:** Agent instantiation in your environment (refer to `lifo_vip_env.sv`):
+```systemverilog
+// Create LIFO VIP environment
+lifo_env = lifo_vip_env::type_id::create("lifo_env", this);
+```
+
+## 🚀 Available Sequences
+
+**Push Sequence:**
+```systemverilog
+lifo_vip_push_seq push_seq = lifo_vip_push_seq::type_id::create("push_seq");
+push_seq.num_pushes = 10;
+push_seq.start(env.get_sequencer());
+```
+
+**Pop Sequence:**
+```systemverilog
+lifo_vip_pop_seq pop_seq = lifo_vip_pop_seq::type_id::create("pop_seq");
+pop_seq.num_pops = 10;
+pop_seq.start(env.get_sequencer());
+```
+
+## 🧪 Available Tests
+
+The VIP includes three pre-built tests that match the testing patterns from `tb/sv/tb.sv`:
+
+### 1. Simple Test
+Basic push and pop operations:
+```bash
+# Run simple test
+vsim -c +UVM_TESTNAME=simple_test -do "run -all; quit"
+```
+
+### 2. Random Test
+Random sequence of push/pop operations (similar to `lifo_random_op_test` in tb.sv):
+```bash
+# Run random test
+vsim -c +UVM_TESTNAME=random_test -do "run -all; quit"
+```
+
+### 3. Full/Empty Test
+Tests boundary conditions - filling LIFO completely and emptying it:
+```bash
+# Run full/empty test
+vsim -c +UVM_TESTNAME=full_empty_test -do "run -all; quit"
+```
+
+## ✅ Self-Checking Features
+
+The scoreboard automatically verifies:
+- ✅ Data integrity through LIFO (Last-In-First-Out order)
+- ✅ Push when full behavior
+- ✅ Pop when empty behavior
+- ✅ LIFO flag correctness (full/empty)
+- ✅ Transaction success/failure
+- ✅ LIFO depth tracking
+
+## 📊 Test Coverage Comparison
+
+The UVM VIP tests provide equivalent coverage to the original testbench:
+
+| tb/sv/tb.sv | UVM VIP Test | Description |
+|-------------|--------------|-------------|
+| `lifo_write()` | `lifo_vip_push_seq` | Push data to LIFO |
+| `lifo_read()` | `lifo_vip_pop_seq` | Pop data from LIFO |
+| `lifo_random_op_test()` | `random_test` | Random push/pop/bypass operations |
+| `lifo_simul_read_write()` | Monitor bypass detection | Simultaneous read/write |
+| Full/empty flag checking | `full_empty_test` + scoreboard | Boundary condition testing |
+
+## 🔧 Key Differences from FIFO VIP
+
+1. **Single Clock Domain**: LIFO uses single clock (synchronous), unlike FIFO's dual-clock support
+2. **Operation Types**:
+   - FIFO: `WRITE`, `READ`, `IDLE`
+   - LIFO: `PUSH`, `POP`, `IDLE`
+3. **Data Order**:
+   - FIFO: First-In-First-Out (queue model)
+   - LIFO: Last-In-First-Out (stack model - `push_back`/`pop_back`)
+4. **Bypass Mode**: LIFO supports simultaneous push/pop (bypass operation)
+5. **Single Agent**: One agent handles all operations (vs separate read/write agents in FIFO)
+
+## 🚨 Common Issues & Solutions
+
+### Issue: Interface signal width mismatch
+**Solution:** Update `lifo_vip_if.sv` line 16-17 to match your LIFO's `DATA_WIDTH`:
+```systemverilog
+logic [DATA_WIDTH-1:0] data_wr;
+logic [DATA_WIDTH-1:0] data_rd;
+```
+
+### Issue: Config parameters don't match DUT
+**Solution:** Ensure `lifo_vip_config.sv` parameters match your DUT instantiation in `tb_top.sv`
+
+### Future Work
+- Add assertions to `lifo_vip_if.sv` or create a separate checker component
+- Add functional coverage for:
+  - Push/pop distribution
+  - Full/empty transitions
+  - Bypass operations
+  - Back-to-back operations
+
+## 📚 Example Usage
+
+```systemverilog
+class my_test extends base_test;
+    `uvm_component_utils(my_test)
+
+    task run_phase(uvm_phase phase);
+        lifo_vip_push_seq push_seq;
+        lifo_vip_pop_seq pop_seq;
+
+        phase.raise_objection(this);
+
+        // Fill LIFO
+        push_seq = lifo_vip_push_seq::type_id::create("push_seq");
+        push_seq.num_pushes = cfg.DEPTH;
+        push_seq.start(env.get_sequencer());
+
+        #100ns;
+
+        // Empty LIFO and verify LIFO order
+        pop_seq = lifo_vip_pop_seq::type_id::create("pop_seq");
+        pop_seq.num_pops = cfg.DEPTH;
+        pop_seq.start(env.get_sequencer());
+
+        #100ns;
+        phase.drop_objection(this);
+    endtask
+endclass
+```
+
+**Happy Verifying! 🚀**
+
+*This VIP follows UVM best practices while keeping complexity minimal for ease of use and learning.*

Weiyet_RTLStructLib/source/LIFO/vip/uvm/agent/lifo_vip_agent.sv

@@ -0,0 +1,44 @@
+//////////////////////////////////////////////////////////////////////////////////
+//
+// Create Date: 01/04/2026
+// Module Name: lifo_vip_agent
+// Author: https://www.linkedin.com/in/wei-yet-ng-065485119/
+// Description: Agent wrapper containing driver, monitor, and sequencer
+//
+//////////////////////////////////////////////////////////////////////////////////
+
+class lifo_vip_agent extends uvm_agent;
+    `uvm_component_utils(lifo_vip_agent)
+
+    lifo_vip_driver driver;
+    lifo_vip_monitor monitor;
+    lifo_vip_sequencer sequencer;
+
+    uvm_analysis_port #(lifo_vip_seq_item) ap;
+
+    function new(string name = "lifo_vip_agent", uvm_component parent = null);
+        super.new(name, parent);
+    endfunction
+
+    function void build_phase(uvm_phase phase);
+        super.build_phase(phase);
+
+        monitor = lifo_vip_monitor::type_id::create("monitor", this);
+
+        if (is_active == UVM_ACTIVE) begin
+            driver = lifo_vip_driver::type_id::create("driver", this);
+            sequencer = lifo_vip_sequencer::type_id::create("sequencer", this);
+        end
+    endfunction
+
+    function void connect_phase(uvm_phase phase);
+        super.connect_phase(phase);
+
+        ap = monitor.ap;
+
+        if (is_active == UVM_ACTIVE) begin
+            driver.seq_item_port.connect(sequencer.seq_item_export);
+        end
+    endfunction
+
+endclass

Weiyet_RTLStructLib/source/LIFO/vip/uvm/agent/lifo_vip_driver.sv

@@ -0,0 +1,80 @@
+//////////////////////////////////////////////////////////////////////////////////
+//
+// Create Date: 01/04/2026
+// Module Name: lifo_vip_driver
+// Author: https://www.linkedin.com/in/wei-yet-ng-065485119/
+// Description: Driver for LIFO VIP - drives transactions to DUT
+//
+//////////////////////////////////////////////////////////////////////////////////
+
+class lifo_vip_driver extends uvm_driver #(lifo_vip_seq_item);
+    `uvm_component_utils(lifo_vip_driver)
+
+    virtual lifo_vip_if vif;
+    lifo_vip_config cfg;
+
+    function new(string name = "lifo_vip_driver", uvm_component parent = null);
+        super.new(name, parent);
+    endfunction
+
+    function void build_phase(uvm_phase phase);
+        super.build_phase(phase);
+        if (!uvm_config_db#(virtual lifo_vip_if)::get(this, "", "lifo_vip_vif", vif))
+            `uvm_fatal("DRIVER", "No virtual interface")
+        if (!uvm_config_db#(lifo_vip_config)::get(this, "", "lifo_vip_cfg", cfg))
+            `uvm_fatal("DRIVER", "No config")
+    endfunction
+
+    task run_phase(uvm_phase phase);
+        forever begin
+            seq_item_port.get_next_item(req);
+            drive_item(req);
+            seq_item_port.item_done();
+        end
+    endtask
+
+    task drive_item(lifo_vip_seq_item item);
+        case (item.op)
+            PUSH: drive_push(item);
+            POP: drive_pop(item);
+            IDLE: drive_idle();
+        endcase
+    endtask
+
+    task drive_push(lifo_vip_seq_item item);
+        @(vif.cb);
+        vif.cb.wr_en <= 1'b1;
+        vif.cb.rd_en <= 1'b0;
+        vif.cb.data_wr <= item.data[cfg.DATA_WIDTH-1:0];
+
+        @(vif.cb);
+        item.full = vif.cb.lifo_full;
+        item.success = !vif.cb.lifo_full;
+
+        vif.cb.wr_en <= 1'b0;
+
+        `uvm_info("DRIVER", $sformatf("Push: data=0x%0h full=%0b", item.data, item.full), UVM_HIGH)
+    endtask
+
+    task drive_pop(lifo_vip_seq_item item);
+        @(vif.cb);
+        vif.cb.rd_en <= 1'b1;
+        vif.cb.wr_en <= 1'b0;
+
+        @(vif.cb);
+        item.empty = vif.cb.lifo_empty;
+        item.read_data = vif.cb.data_rd;
+        item.success = !vif.cb.lifo_empty;
+
+        vif.cb.rd_en <= 1'b0;
+
+        `uvm_info("DRIVER", $sformatf("Pop: data=0x%0h empty=%0b", item.read_data, item.empty), UVM_HIGH)
+    endtask
+
+    task drive_idle();
+        @(vif.cb);
+        vif.cb.wr_en <= 1'b0;
+        vif.cb.rd_en <= 1'b0;
+    endtask
+
+endclass

Weiyet_RTLStructLib/source/LIFO/vip/uvm/agent/lifo_vip_monitor.sv

@@ -0,0 +1,74 @@
+//////////////////////////////////////////////////////////////////////////////////
+//
+// Create Date: 01/04/2026
+// Module Name: lifo_vip_monitor
+// Author: https://www.linkedin.com/in/wei-yet-ng-065485119/
+// Description: Monitor for LIFO VIP - observes DUT signals
+//
+//////////////////////////////////////////////////////////////////////////////////
+
+class lifo_vip_monitor extends uvm_monitor;
+    `uvm_component_utils(lifo_vip_monitor)
+
+    virtual lifo_vip_if vif;
+    lifo_vip_config cfg;
+    uvm_analysis_port #(lifo_vip_seq_item) ap;
+
+    function new(string name = "lifo_vip_monitor", uvm_component parent = null);
+        super.new(name, parent);
+        ap = new("ap", this);
+    endfunction
+
+    function void build_phase(uvm_phase phase);
+        super.build_phase(phase);
+        if (!uvm_config_db#(virtual lifo_vip_if)::get(this, "", "lifo_vip_vif", vif))
+            `uvm_fatal("MONITOR", "No virtual interface")
+        if (!uvm_config_db#(lifo_vip_config)::get(this, "", "lifo_vip_cfg", cfg))
+            `uvm_fatal("MONITOR", "No config")
+    endfunction
+
+    task run_phase(uvm_phase phase);
+        lifo_vip_seq_item item;
+
+        forever begin
+            @(vif.mon_cb);
+
+            // Detect push operation
+            if (vif.mon_cb.wr_en && !vif.mon_cb.rd_en) begin
+                item = lifo_vip_seq_item::type_id::create("item");
+                item.op = PUSH;
+                item.data = vif.mon_cb.data_wr;
+                item.full = vif.mon_cb.lifo_full;
+                item.success = !vif.mon_cb.lifo_full;
+                ap.write(item);
+                `uvm_info("MONITOR", $sformatf("Observed PUSH: data=0x%0h full=%0b", item.data, item.full), UVM_HIGH)
+            end
+
+            // Detect pop operation
+            else if (vif.mon_cb.rd_en && !vif.mon_cb.wr_en) begin
+                @(vif.mon_cb); // Wait one cycle to capture read data
+                item = lifo_vip_seq_item::type_id::create("item");
+                item.op = POP;
+                item.read_data = vif.mon_cb.data_rd;
+                item.empty = vif.mon_cb.lifo_empty;
+                item.success = !vif.mon_cb.lifo_empty;
+                ap.write(item);
+                `uvm_info("MONITOR", $sformatf("Observed POP: data=0x%0h empty=%0b", item.read_data, item.empty), UVM_HIGH)
+            end
+
+            // Detect simultaneous push/pop (bypass)
+            else if (vif.mon_cb.wr_en && vif.mon_cb.rd_en) begin
+                @(vif.mon_cb);
+                item = lifo_vip_seq_item::type_id::create("item");
+                item.op = PUSH; // Record as push for scoreboard
+                item.data = vif.mon_cb.data_wr;
+                item.read_data = vif.mon_cb.data_rd; // Bypass data
+                item.full = vif.mon_cb.lifo_full;
+                item.empty = vif.mon_cb.lifo_empty;
+                ap.write(item);
+                `uvm_info("MONITOR", $sformatf("Observed BYPASS: wr=0x%0h rd=0x%0h", item.data, item.read_data), UVM_HIGH)
+            end
+        end
+    endtask
+
+endclass

Weiyet_RTLStructLib/source/LIFO/vip/uvm/agent/lifo_vip_sequencer.sv

@@ -0,0 +1,17 @@
+//////////////////////////////////////////////////////////////////////////////////
+//
+// Create Date: 01/04/2026
+// Module Name: lifo_vip_sequencer
+// Author: https://www.linkedin.com/in/wei-yet-ng-065485119/
+// Description: Sequencer for LIFO VIP - coordinates sequences
+//
+//////////////////////////////////////////////////////////////////////////////////
+
+class lifo_vip_sequencer extends uvm_sequencer #(lifo_vip_seq_item);
+    `uvm_component_utils(lifo_vip_sequencer)
+
+    function new(string name = "lifo_vip_sequencer", uvm_component parent = null);
+        super.new(name, parent);
+    endfunction
+
+endclass