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Datasets:
architect-ubc-capstone
/
rtl-augmented-v3

Tasks:
Text Generation
Size:
1K<n<10K
Tags:
rtl
verilog
bug-fix
sft
License:
Dataset card Files
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AveryWong03 commited on
Commit
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1 Parent(s): 33ff46c

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Files changed (14) hide show
  1. .gitattributes +13 -0
  2. zhangxin6_iverilog_testbench/candidates/display_pal__display_pal/bugs/case_swap/buggy_waveform.vcd +3 -0
  3. zhangxin6_iverilog_testbench/candidates/display_pal__display_pal/bugs/delayed_signal/buggy_waveform.vcd +3 -0
  4. zhangxin6_iverilog_testbench/candidates/display_pal__display_pal/bugs/inverted_condition/buggy_waveform.vcd +3 -0
  5. zhangxin6_iverilog_testbench/candidates/display_pal__display_pal/bugs/missing_reset/buggy_waveform.vcd +3 -0
  6. zhangxin6_iverilog_testbench/candidates/display_pal__display_pal/bugs/wrong_bitwidth/buggy_waveform.vcd +3 -0
  7. zhangxin6_iverilog_testbench/candidates/hdlcrev__hdlcrev/bugs/delayed_signal/buggy_waveform.vcd +3 -0
  8. zhangxin6_iverilog_testbench/candidates/hdlcrev__hdlcrev/bugs/inverted_condition/buggy_waveform.vcd +3 -0
  9. zhangxin6_iverilog_testbench/candidates/hdlcrev__hdlcrev/bugs/missing_reset/buggy_waveform.vcd +3 -0
  10. zhangxin6_iverilog_testbench/candidates/hdlcrev__hdlcrev/bugs/off_by_one_counter/buggy_waveform.vcd +3 -0
  11. zhangxin6_iverilog_testbench/candidates/hdlcrev__hdlcrev/bugs/operator_typo/buggy_waveform.vcd +3 -0
  12. zhangxin6_iverilog_testbench/candidates/hdlcrev__hdlcrev/bugs/state_transition/buggy_waveform.vcd +3 -0
  13. zhangxin6_iverilog_testbench/candidates/hdlcrev__hdlcrev/bugs/unconnected_port/buggy_waveform.vcd +3 -0
  14. zhangxin6_iverilog_testbench/candidates/hdlcrev__hdlcrev/bugs/wrong_bitwidth/buggy_waveform.vcd +3 -0
.gitattributes CHANGED
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  zhangxin6_iverilog_testbench/source/bat/dsp_hdlc_ctrl_testbench.vcd filter=lfs diff=lfs merge=lfs -text
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  zhangxin6_iverilog_testbench/candidates/hdlcrev__hdlcrev/bugs/concat_swap/buggy_waveform.vcd filter=lfs diff=lfs merge=lfs -text
 
 
 
 
 
 
 
 
 
 
 
 
 
 
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  zhangxin6_iverilog_testbench/source/bat/insert0_testbench.vcd filter=lfs diff=lfs merge=lfs -text
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  zhangxin6_iverilog_testbench/candidates/hdlcrev__hdlcrev/bugs/concat_swap/buggy_waveform.vcd filter=lfs diff=lfs merge=lfs -text
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275
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276
+ zhangxin6_iverilog_testbench/candidates/hdlcrev__hdlcrev/bugs/unconnected_port/buggy_waveform.vcd filter=lfs diff=lfs merge=lfs -text
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+ zhangxin6_iverilog_testbench/candidates/hdlcrev__hdlcrev/bugs/wrong_bitwidth/buggy_waveform.vcd filter=lfs diff=lfs merge=lfs -text
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+ zhangxin6_iverilog_testbench/candidates/hdlcrev__hdlcrev/bugs/missing_reset/buggy_waveform.vcd filter=lfs diff=lfs merge=lfs -text
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284
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zhangxin6_iverilog_testbench/candidates/display_pal__display_pal/bugs/delayed_signal/buggy_waveform.vcd ADDED
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zhangxin6_iverilog_testbench/candidates/display_pal__display_pal/bugs/inverted_condition/buggy_waveform.vcd ADDED
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zhangxin6_iverilog_testbench/candidates/hdlcrev__hdlcrev/bugs/delayed_signal/buggy_waveform.vcd ADDED
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zhangxin6_iverilog_testbench/candidates/hdlcrev__hdlcrev/bugs/missing_reset/buggy_waveform.vcd ADDED
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